[
  {
    "path": ".gitattributes",
    "content": "* -text\n"
  },
  {
    "path": ".github/FUNDING.yml",
    "content": "custom: [ 'https://openwrt.org/donate' ]\n"
  },
  {
    "path": ".github/pull_request_template",
    "content": "Thanks for your contribution to OpenWrt!\n\nTo help keep the codebase consistent and readable,\nand to help people review your contribution,\nwe ask you to follow the rules you find in the wiki at this link\nhttps://openwrt.org/submitting-patches\n\nPlease remove this message before posting the pull request.\n"
  },
  {
    "path": ".github/workflows/ci_helpers.sh",
    "content": "#!/bin/sh\n\ncolor_out() {\n\tprintf \"\\e[0;$1m%s\\e[0;0m\\n\" \"$2\"\n}\n\nsuccess() {\n\tcolor_out 32 \"$1\"\n}\n\ninfo() {\n\tcolor_out 36 \"$1\"\n}\n\nerr() {\n\tcolor_out 31 \"$1\"\n}\n\nwarn() {\n\tcolor_out 33 \"$1\"\n}\n\nerr_die() {\n\terr \"$1\"\n\texit 1\n}\n"
  },
  {
    "path": ".github/workflows/formal.yml",
    "content": "name: Test Formalities\n\non:\n  pull_request:\n\njobs:\n  build:\n    name: Test Formalities\n    runs-on: ubuntu-latest\n    strategy:\n      fail-fast: false\n\n    steps:\n      - uses: actions/checkout@v2\n        with:\n          ref: ${{ github.event.pull_request.head.sha }}\n          fetch-depth: 0\n\n      - name: Determine branch name\n        run: |\n          BRANCH=\"${GITHUB_BASE_REF#refs/heads/}\"\n          echo \"Building for $BRANCH\"\n          echo \"BRANCH=$BRANCH\" >> $GITHUB_ENV\n\n      - name: Test formalities\n        run: |\n          source .github/workflows/ci_helpers.sh\n\n          RET=0\n          for commit in $(git rev-list HEAD ^origin/$BRANCH); do\n            info \"=== Checking commit '$commit'\"\n            if git show --format='%P' -s $commit | grep -qF ' '; then\n              err \"Pull request should not include merge commits\"\n              RET=1\n            fi\n\n            author=\"$(git show -s --format=%aN $commit)\"\n            if echo $author | grep -q '\\S\\+\\s\\+\\S\\+'; then\n              success \"Author name ($author) seems ok\"\n            else\n              err \"Author name ($author) need to be your real name 'firstname lastname'\"\n              RET=1\n            fi\n\n            subject=\"$(git show -s --format=%s $commit)\"\n            if echo \"$subject\" | grep -q -e '^[0-9A-Za-z,+/_\\.-]\\+: ' -e '^Revert '; then\n              success \"Commit subject line seems ok ($subject)\"\n            else\n              err \"Commit subject line MUST start with '<area>: ' ($subject)\"\n              RET=1\n            fi\n\n            body=\"$(git show -s --format=%b $commit)\"\n            sob=\"$(git show -s --format='Signed-off-by: %aN <%aE>' $commit)\"\n            if echo \"$body\" | grep -qF \"$sob\"; then\n              success \"Signed-off-by match author\"\n            else\n              err \"Signed-off-by is missing or doesn't match author (should be '$sob')\"\n              RET=1\n            fi\n\n            if echo \"$body\" | grep -v \"Signed-off-by:\"; then\n              success \"A commit message exists\"\n            else\n              err \"Missing commit message. Please describe your changes\"\n              RET=1\n            fi\n          done\n\n          exit $RET\n"
  },
  {
    "path": ".github/workflows/tools.yml",
    "content": "name: Build host tools\n\non:\n  pull_request:\n    paths:\n      - 'tools/**'\n      - '.github/workflows/tools.yml'\n\njobs:\n  build:\n    name: tools-${{ matrix.os }}\n    runs-on: ${{ matrix.os }}\n    strategy:\n      fail-fast: False\n      matrix:\n        os: \n          - ubuntu-latest\n          - macos-latest\n    steps:\n      - name: Checkout\n        uses: actions/checkout@v2\n        with:\n          fetch-depth: 0\n          path: openwrt\n\n      - name: Setup MacOS\n        if: ${{ matrix.os == 'macos-latest' }}\n        run: |\n          echo \"WORKPATH=/Volumes/OpenWrt/openwrt/\" >> \"$GITHUB_ENV\"\n          hdiutil create -size 20g -type SPARSE -fs \"Case-sensitive HFS+\" -volname OpenWrt OpenWrt.sparseimage\n          hdiutil attach OpenWrt.sparseimage\n          mv \"$GITHUB_WORKSPACE/openwrt\" /Volumes/OpenWrt/\n          cd \"$WORKPATH\"\n\n          brew install \\\n            autoconf \\\n            automake \\\n            coreutils \\\n            diffutils \\\n            findutils \\\n            gawk \\\n            gettext \\\n            git-extras \\\n            gmp \\\n            gnu-getopt \\\n            gnu-sed \\\n            gnu-tar \\\n            grep \\\n            libidn2 \\\n            libunistring \\\n            m4 \\\n            make \\\n            mpfr \\\n            ncurses \\\n            openssl@1.1 \\\n            pcre \\\n            pkg-config \\\n            quilt \\\n            readline \\\n            wget \\\n            zstd\n\n            echo \"/bin\" >> \"$GITHUB_PATH\"\n            echo \"/sbin/Library/Apple/usr/bin\" >> \"$GITHUB_PATH\"\n            echo \"/usr/bin\" >> \"$GITHUB_PATH\"\n            echo \"/usr/local/bin\" >> \"$GITHUB_PATH\"\n            echo \"/usr/local/opt/coreutils/bin\" >> \"$GITHUB_PATH\"\n            echo \"/usr/local/opt/findutils/libexec/gnubin\" >> \"$GITHUB_PATH\"\n            echo \"/usr/local/opt/gettext/bin\" >> \"$GITHUB_PATH\"\n            echo \"/usr/local/opt/gnu-getopt/bin\" >> \"$GITHUB_PATH\"\n            echo \"/usr/local/opt/make/libexec/gnubin\" >> \"$GITHUB_PATH\"\n            echo \"/usr/local/opt/make/libexec/gnubin\" >> \"$GITHUB_PATH\"\n            echo \"/usr/sbin\" >> \"$GITHUB_PATH\"\n            pwd\n\n      - name: Setup Ubuntu\n        if: ${{ matrix.os == 'ubuntu-latest' }}\n        env:\n          DEBIAN_FRONTEND: noninteractive\n        run: |\n          sudo apt-get update\n          sudo apt-get -y install \\\n            build-essential \\\n            ccache \\\n            clang-12 \\\n            ecj \\\n            fastjar \\\n            file \\\n            g++ \\\n            gawk \\\n            gettext \\\n            git \\\n            java-propose-classpath \\\n            libelf-dev \\\n            libncurses-dev \\\n            libssl-dev \\\n            mkisofs \\\n            python3 \\\n            python3-dev \\\n            python3-distutils \\\n            python3-setuptools \\\n            qemu-utils \\\n            rsync \\\n            subversion \\\n            swig \\\n            unzip \\\n            wget \\\n            xsltproc \\\n            zlib1g-dev\n          echo \"WORKPATH=$GITHUB_WORKSPACE/openwrt/\" >> \"$GITHUB_ENV\"\n          cd \"$WORKPATH\"\n          pwd\n\n      - name: Make prereq\n        run: |\n          cd \"$WORKPATH\"\n          pwd\n          make defconfig\n\n      - name: Build tools\n        run: |\n          cd \"$WORKPATH\"\n          make tools/install -j$(nproc) BUILD_LOG=1\n\n      - name: Move logs to GITHUB_WORKSPACE\n        if: always()\n        run: |\n          cp -r \"$WORKPATH/logs\" \"$GITHUB_WORKSPACE\"\n          cp -r \"$WORKPATH/.config\" \"$GITHUB_WORKSPACE/config\"\n\n\n      - name: Upload logs\n        if: always()\n        uses: actions/upload-artifact@v2\n        with:\n          name: ${{ matrix.os }}-logs\n          path: \"logs\"\n\n      - name: Upload config\n        if: always()\n        uses: actions/upload-artifact@v2\n        with:\n          name: ${{ matrix.os }}-config\n          path: \"config\"\n"
  },
  {
    "path": ".gitignore",
    "content": "*.o\n.DS_Store\n.*.swp\n/env\n/dl\n/.config\n/.config.old\n/.toolchain_build_ver\n/bin\n/build_dir\n/staging_dir\n/tmp\n/logs\n/feeds\n/feeds.conf\n/files\n/overlay\n/package/feeds\n/package/openwrt-packages\n/*.patch\n/llvm-bpf*\nkey-build*\n*.orig\n*.rej\n*~\n.#*\n*#\n.emacs.desktop*\nTAGS*~\ngit-src\n.project\n.cproject\n.ccache\n.vscode*\n"
  },
  {
    "path": "BSDmakefile",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2006 OpenWrt.org\n\nworld ${.TARGETS}:\n\t@gmake $@\n"
  },
  {
    "path": "COPYING",
    "content": "OpenWrt is provided under:\n\n\tSPDX-License-Identifier: GPL-2.0-only\n\nBeing under the terms of the GNU General Public License version 2 only,\naccording with:\n\n\tLICENSES/GPL-2.0\n\nIn addition, other licenses may also apply.\n\nAll contributions to OpenWrt are subject to this COPYING file.\n"
  },
  {
    "path": "Config.in",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2006-2013 OpenWrt.org\n\nmainmenu \"OpenWrt Configuration\"\n\nconfig MODULES\n\tmodules\n\tbool\n\tdefault y\n\nconfig HAVE_DOT_CONFIG\n\tbool\n\tdefault y\n\nHOST_OS := $(shell, uname)\n\nconfig HOST_OS_LINUX\n\tdef_bool $(shell, ./config/check-uname.sh Linux)\n\nconfig HOST_OS_MACOS\n\tdef_bool $(shell, ./config/check-uname.sh Darwin)\n\nsource \"target/Config.in\"\n\nsource \"config/Config-images.in\"\n\nsource \"config/Config-build.in\"\n\nsource \"config/Config-devel.in\"\n\nsource \"toolchain/Config.in\"\n\nsource \"target/imagebuilder/Config.in\"\n\nsource \"target/sdk/Config.in\"\n\nsource \"target/toolchain/Config.in\"\n\nsource \"tmp/.config-package.in\"\n"
  },
  {
    "path": "LICENSES/BSD-2-Clause",
    "content": "Valid-License-Identifier: BSD-2-Clause\nSPDX-URL: https://spdx.org/licenses/BSD-2-Clause.html\nUsage-Guide:\n  To use the BSD 2-clause \"Simplified\" License put the following SPDX\n  tag/value pair into a comment according to the placement guidelines in\n  the licensing rules documentation:\n    SPDX-License-Identifier: BSD-2-Clause\nLicense-Text:\n\nCopyright (c) <year> <owner> . All rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n1. Redistributions of source code must retain the above copyright notice,\n   this list of conditions and the following disclaimer.\n\n2. Redistributions in binary form must reproduce the above copyright\n   notice, this list of conditions and the following disclaimer in the\n   documentation and/or other materials provided with the distribution.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\nARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE\nLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\nCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\nSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\nINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\nCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\nARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n"
  },
  {
    "path": "LICENSES/BSD-3-Clause",
    "content": "Valid-License-Identifier: BSD-3-Clause\nSPDX-URL: https://spdx.org/licenses/BSD-3-Clause.html\nUsage-Guide:\n  To use the BSD 3-clause \"New\" or \"Revised\" License put the following SPDX\n  tag/value pair into a comment according to the placement guidelines in\n  the licensing rules documentation:\n    SPDX-License-Identifier: BSD-3-Clause\nLicense-Text:\n\nCopyright (c) <year> <owner> . All rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n1. Redistributions of source code must retain the above copyright notice,\n   this list of conditions and the following disclaimer.\n\n2. Redistributions in binary form must reproduce the above copyright\n   notice, this list of conditions and the following disclaimer in the\n   documentation and/or other materials provided with the distribution.\n\n3. Neither the name of the copyright holder nor the names of its\n   contributors may be used to endorse or promote products derived from this\n   software without specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\nARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE\nLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\nCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\nSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\nINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\nCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\nARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n"
  },
  {
    "path": "LICENSES/GPL-1.0",
    "content": "Valid-License-Identifier: GPL-1.0-or-later\nValid-License-Identifier: GPL-1.0+\nSPDX-URL: https://spdx.org/licenses/GPL-1.0.html\nUsage-Guide:\n  The GNU General Public License (GPL) version 1 should not be used in new\n  code. For existing kernel code the 'or any later version' option is\n  required to be compatible with the general license of the project: GPLv2.\n  To use the license in source code, put the following SPDX tag/value pair\n  into a comment according to the placement guidelines in the licensing\n  rules documentation:\n    SPDX-License-Identifier: GPL-1.0-or-later\nLicense-Text:\n\n\t    GNU GENERAL PUBLIC LICENSE\n\t     Version 1, February 1989\n\n Copyright (C) 1989 Free Software Foundation, Inc.\n                    675 Mass Ave, Cambridge, MA 02139, USA\n Everyone is permitted to copy and distribute verbatim copies\n of this license document, but changing it is not allowed.\n\n\t\t\t    Preamble\n\n  The license agreements of most software companies try to keep users\nat the mercy of those companies.  By contrast, our General Public\nLicense is intended to guarantee your freedom to share and change free\nsoftware--to make sure the software is free for all its users.  The\nGeneral Public License applies to the Free Software Foundation's\nsoftware and to any other program whose authors commit to using it.\nYou can use it for your programs, too.\n\n  When we speak of free software, we are referring to freedom, not\nprice.  Specifically, the General Public License is designed to make\nsure that you have the freedom to give away or sell copies of free\nsoftware, that you receive source code or can get it if you want it,\nthat you can change the software or use pieces of it in new free\nprograms; and that you know you can do these things.\n\n  To protect your rights, we need to make restrictions that forbid\nanyone to deny you these rights or to ask you to surrender the rights.\nThese restrictions translate to certain responsibilities for you if you\ndistribute copies of the software, or if you modify it.\n\n  For example, if you distribute copies of a such a program, whether\ngratis or for a fee, you must give the recipients all the rights that\nyou have.  You must make sure that they, too, receive or can get the\nsource code.  And you must tell them their rights.\n\n  We protect your rights with two steps: (1) copyright the software, and\n(2) offer you this license which gives you legal permission to copy,\ndistribute and/or modify the software.\n\n  Also, for each author's protection and ours, we want to make certain\nthat everyone understands that there is no warranty for this free\nsoftware.  If the software is modified by someone else and passed on, we\nwant its recipients to know that what they have is not the original, so\nthat any problems introduced by others will not reflect on the original\nauthors' reputations.\n\n  The precise terms and conditions for copying, distribution and\nmodification follow.\n\n\t\t    GNU GENERAL PUBLIC LICENSE\n   TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION\n\n  0. This License Agreement applies to any program or other work which\ncontains a notice placed by the copyright holder saying it may be\ndistributed under the terms of this General Public License.  The\n\"Program\", below, refers to any such program or work, and a \"work based\non the Program\" means either the Program or any work containing the\nProgram or a portion of it, either verbatim or with modifications.  Each\nlicensee is addressed as \"you\".\n\n  1. You may copy and distribute verbatim copies of the Program's source\ncode as you receive it, in any medium, provided that you conspicuously and\nappropriately publish on each copy an appropriate copyright notice and\ndisclaimer of warranty; keep intact all the notices that refer to this\nGeneral Public License and to the absence of any warranty; and give any\nother recipients of the Program a copy of this General Public License\nalong with the Program.  You may charge a fee for the physical act of\ntransferring a copy.\n\n  2. You may modify your copy or copies of the Program or any portion of\nit, and copy and distribute such modifications under the terms of Paragraph\n1 above, provided that you also do the following:\n\n    a) cause the modified files to carry prominent notices stating that\n    you changed the files and the date of any change; and\n\n    b) cause the whole of any work that you distribute or publish, that\n    in whole or in part contains the Program or any part thereof, either\n    with or without modifications, to be licensed at no charge to all\n    third parties under the terms of this General Public License (except\n    that you may choose to grant warranty protection to some or all\n    third parties, at your option).\n\n    c) If the modified program normally reads commands interactively when\n    run, you must cause it, when started running for such interactive use\n    in the simplest and most usual way, to print or display an\n    announcement including an appropriate copyright notice and a notice\n    that there is no warranty (or else, saying that you provide a\n    warranty) and that users may redistribute the program under these\n    conditions, and telling the user how to view a copy of this General\n    Public License.\n\n    d) You may charge a fee for the physical act of transferring a\n    copy, and you may at your option offer warranty protection in\n    exchange for a fee.\n\nMere aggregation of another independent work with the Program (or its\nderivative) on a volume of a storage or distribution medium does not bring\nthe other work under the scope of these terms.\n\n  3. You may copy and distribute the Program (or a portion or derivative of\nit, under Paragraph 2) in object code or executable form under the terms of\nParagraphs 1 and 2 above provided that you also do one of the following:\n\n    a) accompany it with the complete corresponding machine-readable\n    source code, which must be distributed under the terms of\n    Paragraphs 1 and 2 above; or,\n\n    b) accompany it with a written offer, valid for at least three\n    years, to give any third party free (except for a nominal charge\n    for the cost of distribution) a complete machine-readable copy of the\n    corresponding source code, to be distributed under the terms of\n    Paragraphs 1 and 2 above; or,\n\n    c) accompany it with the information you received as to where the\n    corresponding source code may be obtained.  (This alternative is\n    allowed only for noncommercial distribution and only if you\n    received the program in object code or executable form alone.)\n\nSource code for a work means the preferred form of the work for making\nmodifications to it.  For an executable file, complete source code means\nall the source code for all modules it contains; but, as a special\nexception, it need not include source code for modules which are standard\nlibraries that accompany the operating system on which the executable\nfile runs, or for standard header files or definitions files that\naccompany that operating system.\n\n  4. You may not copy, modify, sublicense, distribute or transfer the\nProgram except as expressly provided under this General Public License.\nAny attempt otherwise to copy, modify, sublicense, distribute or transfer\nthe Program is void, and will automatically terminate your rights to use\nthe Program under this License.  However, parties who have received\ncopies, or rights to use copies, from you under this General Public\nLicense will not have their licenses terminated so long as such parties\nremain in full compliance.\n\n  5. By copying, distributing or modifying the Program (or any work based\non the Program) you indicate your acceptance of this license to do so,\nand all its terms and conditions.\n\n  6. Each time you redistribute the Program (or any work based on the\nProgram), the recipient automatically receives a license from the original\nlicensor to copy, distribute or modify the Program subject to these\nterms and conditions.  You may not impose any further restrictions on the\nrecipients' exercise of the rights granted herein.\n\n  7. The Free Software Foundation may publish revised and/or new versions\nof the General Public License from time to time.  Such new versions will\nbe similar in spirit to the present version, but may differ in detail to\naddress new problems or concerns.\n\nEach version is given a distinguishing version number.  If the Program\nspecifies a version number of the license which applies to it and \"any\nlater version\", you have the option of following the terms and conditions\neither of that version or of any later version published by the Free\nSoftware Foundation.  If the Program does not specify a version number of\nthe license, you may choose any version ever published by the Free Software\nFoundation.\n\n  8. If you wish to incorporate parts of the Program into other free\nprograms whose distribution conditions are different, write to the author\nto ask for permission.  For software which is copyrighted by the Free\nSoftware Foundation, write to the Free Software Foundation; we sometimes\nmake exceptions for this.  Our decision will be guided by the two goals\nof preserving the free status of all derivatives of our free software and\nof promoting the sharing and reuse of software generally.\n\n\t\t\t    NO WARRANTY\n\n  9. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY\nFOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW.  EXCEPT WHEN\nOTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES\nPROVIDE THE PROGRAM \"AS IS\" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED\nOR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\nMERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.  THE ENTIRE RISK AS\nTO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU.  SHOULD THE\nPROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING,\nREPAIR OR CORRECTION.\n\n  10. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING\nWILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR\nREDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES,\nINCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING\nOUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED\nTO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY\nYOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER\nPROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGES.\n\n\t\t     END OF TERMS AND CONDITIONS\n\n\tAppendix: How to Apply These Terms to Your New Programs\n\n  If you develop a new program, and you want it to be of the greatest\npossible use to humanity, the best way to achieve this is to make it\nfree software which everyone can redistribute and change under these\nterms.\n\n  To do so, attach the following notices to the program.  It is safest to\nattach them to the start of each source file to most effectively convey\nthe exclusion of warranty; and each file should have at least the\n\"copyright\" line and a pointer to where the full notice is found.\n\n    <one line to give the program's name and a brief idea of what it does.>\n    Copyright (C) 19yy  <name of author>\n\n    This program is free software; you can redistribute it and/or modify\n    it under the terms of the GNU General Public License as published by\n    the Free Software Foundation; either version 1, or (at your option)\n    any later version.\n\n    This program is distributed in the hope that it will be useful,\n    but WITHOUT ANY WARRANTY; without even the implied warranty of\n    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n    GNU General Public License for more details.\n\n    You should have received a copy of the GNU General Public License\n    along with this program; if not, write to the Free Software\n    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.\n\nAlso add information on how to contact you by electronic and paper mail.\n\nIf the program is interactive, make it output a short notice like this\nwhen it starts in an interactive mode:\n\n    Gnomovision version 69, Copyright (C) 19xx name of author\n    Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'.\n    This is free software, and you are welcome to redistribute it\n    under certain conditions; type `show c' for details.\n\nThe hypothetical commands `show w' and `show c' should show the\nappropriate parts of the General Public License.  Of course, the\ncommands you use may be called something other than `show w' and `show\nc'; they could even be mouse-clicks or menu items--whatever suits your\nprogram.\n\nYou should also get your employer (if you work as a programmer) or your\nschool, if any, to sign a \"copyright disclaimer\" for the program, if\nnecessary.  Here a sample; alter the names:\n\n  Yoyodyne, Inc., hereby disclaims all copyright interest in the\n  program `Gnomovision' (a program to direct compilers to make passes\n  at assemblers) written by James Hacker.\n\n  <signature of Ty Coon>, 1 April 1989\n  Ty Coon, President of Vice\n\nThat's all there is to it!\n"
  },
  {
    "path": "LICENSES/GPL-2.0",
    "content": "Valid-License-Identifier: GPL-2.0-only\nValid-License-Identifier: GPL-2.0\nValid-License-Identifier: GPL-2.0-or-later\nValid-License-Identifier: GPL-2.0+\nSPDX-URL: https://spdx.org/licenses/GPL-2.0.html\nUsage-Guide:\n  To use this license in source code, put one of the following SPDX\n  tag/value pairs into a comment according to the placement\n  guidelines in the licensing rules documentation.\n  For 'GNU General Public License (GPL) version 2 only' use:\n    SPDX-License-Identifier: GPL-2.0-only\n  For 'GNU General Public License (GPL) version 2 or any later version' use:\n    SPDX-License-Identifier: GPL-2.0-or-later\nLicense-Text:\n\n\t\t    GNU GENERAL PUBLIC LICENSE\n\t\t       Version 2, June 1991\n\n Copyright (C) 1989, 1991 Free Software Foundation, Inc.\n                       51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA\n Everyone is permitted to copy and distribute verbatim copies\n of this license document, but changing it is not allowed.\n\n\t\t\t    Preamble\n\n  The licenses for most software are designed to take away your\nfreedom to share and change it.  By contrast, the GNU General Public\nLicense is intended to guarantee your freedom to share and change free\nsoftware--to make sure the software is free for all its users.  This\nGeneral Public License applies to most of the Free Software\nFoundation's software and to any other program whose authors commit to\nusing it.  (Some other Free Software Foundation software is covered by\nthe GNU Library General Public License instead.)  You can apply it to\nyour programs, too.\n\n  When we speak of free software, we are referring to freedom, not\nprice.  Our General Public Licenses are designed to make sure that you\nhave the freedom to distribute copies of free software (and charge for\nthis service if you wish), that you receive source code or can get it\nif you want it, that you can change the software or use pieces of it\nin new free programs; and that you know you can do these things.\n\n  To protect your rights, we need to make restrictions that forbid\nanyone to deny you these rights or to ask you to surrender the rights.\nThese restrictions translate to certain responsibilities for you if you\ndistribute copies of the software, or if you modify it.\n\n  For example, if you distribute copies of such a program, whether\ngratis or for a fee, you must give the recipients all the rights that\nyou have.  You must make sure that they, too, receive or can get the\nsource code.  And you must show them these terms so they know their\nrights.\n\n  We protect your rights with two steps: (1) copyright the software, and\n(2) offer you this license which gives you legal permission to copy,\ndistribute and/or modify the software.\n\n  Also, for each author's protection and ours, we want to make certain\nthat everyone understands that there is no warranty for this free\nsoftware.  If the software is modified by someone else and passed on, we\nwant its recipients to know that what they have is not the original, so\nthat any problems introduced by others will not reflect on the original\nauthors' reputations.\n\n  Finally, any free program is threatened constantly by software\npatents.  We wish to avoid the danger that redistributors of a free\nprogram will individually obtain patent licenses, in effect making the\nprogram proprietary.  To prevent this, we have made it clear that any\npatent must be licensed for everyone's free use or not licensed at all.\n\n  The precise terms and conditions for copying, distribution and\nmodification follow.\n\f\n\t\t    GNU GENERAL PUBLIC LICENSE\n   TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION\n\n  0. This License applies to any program or other work which contains\na notice placed by the copyright holder saying it may be distributed\nunder the terms of this General Public License.  The \"Program\", below,\nrefers to any such program or work, and a \"work based on the Program\"\nmeans either the Program or any derivative work under copyright law:\nthat is to say, a work containing the Program or a portion of it,\neither verbatim or with modifications and/or translated into another\nlanguage.  (Hereinafter, translation is included without limitation in\nthe term \"modification\".)  Each licensee is addressed as \"you\".\n\nActivities other than copying, distribution and modification are not\ncovered by this License; they are outside its scope.  The act of\nrunning the Program is not restricted, and the output from the Program\nis covered only if its contents constitute a work based on the\nProgram (independent of having been made by running the Program).\nWhether that is true depends on what the Program does.\n\n  1. You may copy and distribute verbatim copies of the Program's\nsource code as you receive it, in any medium, provided that you\nconspicuously and appropriately publish on each copy an appropriate\ncopyright notice and disclaimer of warranty; keep intact all the\nnotices that refer to this License and to the absence of any warranty;\nand give any other recipients of the Program a copy of this License\nalong with the Program.\n\nYou may charge a fee for the physical act of transferring a copy, and\nyou may at your option offer warranty protection in exchange for a fee.\n\n  2. You may modify your copy or copies of the Program or any portion\nof it, thus forming a work based on the Program, and copy and\ndistribute such modifications or work under the terms of Section 1\nabove, provided that you also meet all of these conditions:\n\n    a) You must cause the modified files to carry prominent notices\n    stating that you changed the files and the date of any change.\n\n    b) You must cause any work that you distribute or publish, that in\n    whole or in part contains or is derived from the Program or any\n    part thereof, to be licensed as a whole at no charge to all third\n    parties under the terms of this License.\n\n    c) If the modified program normally reads commands interactively\n    when run, you must cause it, when started running for such\n    interactive use in the most ordinary way, to print or display an\n    announcement including an appropriate copyright notice and a\n    notice that there is no warranty (or else, saying that you provide\n    a warranty) and that users may redistribute the program under\n    these conditions, and telling the user how to view a copy of this\n    License.  (Exception: if the Program itself is interactive but\n    does not normally print such an announcement, your work based on\n    the Program is not required to print an announcement.)\n\f\nThese requirements apply to the modified work as a whole.  If\nidentifiable sections of that work are not derived from the Program,\nand can be reasonably considered independent and separate works in\nthemselves, then this License, and its terms, do not apply to those\nsections when you distribute them as separate works.  But when you\ndistribute the same sections as part of a whole which is a work based\non the Program, the distribution of the whole must be on the terms of\nthis License, whose permissions for other licensees extend to the\nentire whole, and thus to each and every part regardless of who wrote it.\n\nThus, it is not the intent of this section to claim rights or contest\nyour rights to work written entirely by you; rather, the intent is to\nexercise the right to control the distribution of derivative or\ncollective works based on the Program.\n\nIn addition, mere aggregation of another work not based on the Program\nwith the Program (or with a work based on the Program) on a volume of\na storage or distribution medium does not bring the other work under\nthe scope of this License.\n\n  3. You may copy and distribute the Program (or a work based on it,\nunder Section 2) in object code or executable form under the terms of\nSections 1 and 2 above provided that you also do one of the following:\n\n    a) Accompany it with the complete corresponding machine-readable\n    source code, which must be distributed under the terms of Sections\n    1 and 2 above on a medium customarily used for software interchange; or,\n\n    b) Accompany it with a written offer, valid for at least three\n    years, to give any third party, for a charge no more than your\n    cost of physically performing source distribution, a complete\n    machine-readable copy of the corresponding source code, to be\n    distributed under the terms of Sections 1 and 2 above on a medium\n    customarily used for software interchange; or,\n\n    c) Accompany it with the information you received as to the offer\n    to distribute corresponding source code.  (This alternative is\n    allowed only for noncommercial distribution and only if you\n    received the program in object code or executable form with such\n    an offer, in accord with Subsection b above.)\n\nThe source code for a work means the preferred form of the work for\nmaking modifications to it.  For an executable work, complete source\ncode means all the source code for all modules it contains, plus any\nassociated interface definition files, plus the scripts used to\ncontrol compilation and installation of the executable.  However, as a\nspecial exception, the source code distributed need not include\nanything that is normally distributed (in either source or binary\nform) with the major components (compiler, kernel, and so on) of the\noperating system on which the executable runs, unless that component\nitself accompanies the executable.\n\nIf distribution of executable or object code is made by offering\naccess to copy from a designated place, then offering equivalent\naccess to copy the source code from the same place counts as\ndistribution of the source code, even though third parties are not\ncompelled to copy the source along with the object code.\n\f\n  4. You may not copy, modify, sublicense, or distribute the Program\nexcept as expressly provided under this License.  Any attempt\notherwise to copy, modify, sublicense or distribute the Program is\nvoid, and will automatically terminate your rights under this License.\nHowever, parties who have received copies, or rights, from you under\nthis License will not have their licenses terminated so long as such\nparties remain in full compliance.\n\n  5. You are not required to accept this License, since you have not\nsigned it.  However, nothing else grants you permission to modify or\ndistribute the Program or its derivative works.  These actions are\nprohibited by law if you do not accept this License.  Therefore, by\nmodifying or distributing the Program (or any work based on the\nProgram), you indicate your acceptance of this License to do so, and\nall its terms and conditions for copying, distributing or modifying\nthe Program or works based on it.\n\n  6. Each time you redistribute the Program (or any work based on the\nProgram), the recipient automatically receives a license from the\noriginal licensor to copy, distribute or modify the Program subject to\nthese terms and conditions.  You may not impose any further\nrestrictions on the recipients' exercise of the rights granted herein.\nYou are not responsible for enforcing compliance by third parties to\nthis License.\n\n  7. If, as a consequence of a court judgment or allegation of patent\ninfringement or for any other reason (not limited to patent issues),\nconditions are imposed on you (whether by court order, agreement or\notherwise) that contradict the conditions of this License, they do not\nexcuse you from the conditions of this License.  If you cannot\ndistribute so as to satisfy simultaneously your obligations under this\nLicense and any other pertinent obligations, then as a consequence you\nmay not distribute the Program at all.  For example, if a patent\nlicense would not permit royalty-free redistribution of the Program by\nall those who receive copies directly or indirectly through you, then\nthe only way you could satisfy both it and this License would be to\nrefrain entirely from distribution of the Program.\n\nIf any portion of this section is held invalid or unenforceable under\nany particular circumstance, the balance of the section is intended to\napply and the section as a whole is intended to apply in other\ncircumstances.\n\nIt is not the purpose of this section to induce you to infringe any\npatents or other property right claims or to contest validity of any\nsuch claims; this section has the sole purpose of protecting the\nintegrity of the free software distribution system, which is\nimplemented by public license practices.  Many people have made\ngenerous contributions to the wide range of software distributed\nthrough that system in reliance on consistent application of that\nsystem; it is up to the author/donor to decide if he or she is willing\nto distribute software through any other system and a licensee cannot\nimpose that choice.\n\nThis section is intended to make thoroughly clear what is believed to\nbe a consequence of the rest of this License.\n\f\n  8. If the distribution and/or use of the Program is restricted in\ncertain countries either by patents or by copyrighted interfaces, the\noriginal copyright holder who places the Program under this License\nmay add an explicit geographical distribution limitation excluding\nthose countries, so that distribution is permitted only in or among\ncountries not thus excluded.  In such case, this License incorporates\nthe limitation as if written in the body of this License.\n\n  9. The Free Software Foundation may publish revised and/or new versions\nof the General Public License from time to time.  Such new versions will\nbe similar in spirit to the present version, but may differ in detail to\naddress new problems or concerns.\n\nEach version is given a distinguishing version number.  If the Program\nspecifies a version number of this License which applies to it and \"any\nlater version\", you have the option of following the terms and conditions\neither of that version or of any later version published by the Free\nSoftware Foundation.  If the Program does not specify a version number of\nthis License, you may choose any version ever published by the Free Software\nFoundation.\n\n  10. If you wish to incorporate parts of the Program into other free\nprograms whose distribution conditions are different, write to the author\nto ask for permission.  For software which is copyrighted by the Free\nSoftware Foundation, write to the Free Software Foundation; we sometimes\nmake exceptions for this.  Our decision will be guided by the two goals\nof preserving the free status of all derivatives of our free software and\nof promoting the sharing and reuse of software generally.\n\n\t\t\t    NO WARRANTY\n\n  11. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY\nFOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW.  EXCEPT WHEN\nOTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES\nPROVIDE THE PROGRAM \"AS IS\" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED\nOR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\nMERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.  THE ENTIRE RISK AS\nTO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU.  SHOULD THE\nPROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING,\nREPAIR OR CORRECTION.\n\n  12. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING\nWILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR\nREDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES,\nINCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING\nOUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED\nTO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY\nYOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER\nPROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGES.\n\n\t\t     END OF TERMS AND CONDITIONS\n\f\n\t    How to Apply These Terms to Your New Programs\n\n  If you develop a new program, and you want it to be of the greatest\npossible use to the public, the best way to achieve this is to make it\nfree software which everyone can redistribute and change under these terms.\n\n  To do so, attach the following notices to the program.  It is safest\nto attach them to the start of each source file to most effectively\nconvey the exclusion of warranty; and each file should have at least\nthe \"copyright\" line and a pointer to where the full notice is found.\n\n    <one line to give the program's name and a brief idea of what it does.>\n    Copyright (C) <year>  <name of author>\n\n    This program is free software; you can redistribute it and/or modify\n    it under the terms of the GNU General Public License as published by\n    the Free Software Foundation; either version 2 of the License, or\n    (at your option) any later version.\n\n    This program is distributed in the hope that it will be useful,\n    but WITHOUT ANY WARRANTY; without even the implied warranty of\n    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n    GNU General Public License for more details.\n\n    You should have received a copy of the GNU General Public License\n    along with this program; if not, write to the Free Software\n    Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA\n\n\nAlso add information on how to contact you by electronic and paper mail.\n\nIf the program is interactive, make it output a short notice like this\nwhen it starts in an interactive mode:\n\n    Gnomovision version 69, Copyright (C) year name of author\n    Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'.\n    This is free software, and you are welcome to redistribute it\n    under certain conditions; type `show c' for details.\n\nThe hypothetical commands `show w' and `show c' should show the appropriate\nparts of the General Public License.  Of course, the commands you use may\nbe called something other than `show w' and `show c'; they could even be\nmouse-clicks or menu items--whatever suits your program.\n\nYou should also get your employer (if you work as a programmer) or your\nschool, if any, to sign a \"copyright disclaimer\" for the program, if\nnecessary.  Here is a sample; alter the names:\n\n  Yoyodyne, Inc., hereby disclaims all copyright interest in the program\n  `Gnomovision' (which makes passes at compilers) written by James Hacker.\n\n  <signature of Ty Coon>, 1 April 1989\n  Ty Coon, President of Vice\n\nThis General Public License does not permit incorporating your program into\nproprietary programs.  If your program is a subroutine library, you may\nconsider it more useful to permit linking proprietary applications with the\nlibrary.  If this is what you want to do, use the GNU Library General\nPublic License instead of this License.\n"
  },
  {
    "path": "LICENSES/ISC",
    "content": "Valid-License-Identifier: ISC\nSPDX-URL: https://spdx.org/licenses/ISC.html\nUsage-Guide:\n  To use the ISC License put the following SPDX tag/value pair into a\n  comment according to the placement guidelines in the licensing rules\n  documentation:\n    SPDX-License-Identifier: ISC\nLicense-Text:\n\nISC License\n\nCopyright (c) <year> <copyright holders>\n\nPermission to use, copy, modify, and/or distribute this software for any\npurpose with or without fee is hereby granted, provided that the above\ncopyright notice and this permission notice appear in all copies.\n\nTHE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\nWITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\nMERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY\nSPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\nWHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION\nOF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN\nCONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n"
  },
  {
    "path": "LICENSES/Linux-syscall-note",
    "content": "SPDX-Exception-Identifier: Linux-syscall-note\nSPDX-URL: https://spdx.org/licenses/Linux-syscall-note.html\nSPDX-Licenses: GPL-2.0-only, GPL-2.0, GPL-2.0-or-later, GPL-2.0+, GPL-1.0-or-later, GPL-1.0+, LGPL-2.0, LGPL-2.0+, LGPL-2.1, LGPL-2.1+\nUsage-Guide:\n  This exception is used together with one of the above SPDX-Licenses\n  to mark user space API (uapi) header files so they can be included\n  into non GPL compliant user space application code.\n  To use this exception add it with the keyword WITH to one of the\n  identifiers in the SPDX-Licenses tag:\n    SPDX-License-Identifier: <SPDX-License> WITH Linux-syscall-note\nLicense-Text:\n\n   NOTE! This copyright does *not* cover user programs that use kernel\n services by normal system calls - this is merely considered normal use\n of the kernel, and does *not* fall under the heading of \"derived work\".\n Also note that the GPL below is copyrighted by the Free Software\n Foundation, but the instance of code that it refers to (the Linux\n kernel) is copyrighted by me and others who actually wrote it.\n\n Also note that the only valid version of the GPL as far as the kernel\n is concerned is _this_ particular version of the license (ie v2, not\n v2.2 or v3.x or whatever), unless explicitly otherwise stated.\n\n\t\t\tLinus Torvalds\n\n"
  },
  {
    "path": "LICENSES/MIT",
    "content": "Valid-License-Identifier: MIT\nSPDX-URL: https://spdx.org/licenses/MIT.html\nUsage-Guide:\n  To use the MIT License put the following SPDX tag/value pair into a\n  comment according to the placement guidelines in the licensing rules\n  documentation:\n    SPDX-License-Identifier: MIT\nLicense-Text:\n\nMIT License\n\nCopyright (c) <year> <copyright holders>\n\nPermission is hereby granted, free of charge, to any person obtaining a\ncopy of this software and associated documentation files (the \"Software\"),\nto deal in the Software without restriction, including without limitation\nthe rights to use, copy, modify, merge, publish, distribute, sublicense,\nand/or sell copies of the Software, and to permit persons to whom the\nSoftware is furnished to do so, subject to the following conditions:\n\nThe above copyright notice and this permission notice shall be included in\nall copies or substantial portions of the Software.\n\nTHE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\nIMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\nFITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\nAUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\nLIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\nFROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\nDEALINGS IN THE SOFTWARE.\n"
  },
  {
    "path": "Makefile",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2007 OpenWrt.org\n\nTOPDIR:=${CURDIR}\nLC_ALL:=C\nLANG:=C\nTZ:=UTC\nexport TOPDIR LC_ALL LANG TZ\n\nempty:=\nspace:= $(empty) $(empty)\n$(if $(findstring $(space),$(TOPDIR)),$(error ERROR: The path to the OpenWrt directory must not include any spaces))\n\nworld:\n\nDISTRO_PKG_CONFIG:=$(shell $(TOPDIR)/scripts/command_all.sh pkg-config | grep -E '\\/usr' | head -n 1)\nexport PATH:=$(TOPDIR)/staging_dir/host/bin:$(PATH)\n\nifneq ($(OPENWRT_BUILD),1)\n  _SINGLE=export MAKEFLAGS=$(space);\n\n  override OPENWRT_BUILD=1\n  export OPENWRT_BUILD\n  GREP_OPTIONS=\n  export GREP_OPTIONS\n  CDPATH=\n  export CDPATH\n  include $(TOPDIR)/include/debug.mk\n  include $(TOPDIR)/include/depends.mk\n  include $(TOPDIR)/include/toplevel.mk\nelse\n  include rules.mk\n  include $(INCLUDE_DIR)/depends.mk\n  include $(INCLUDE_DIR)/subdir.mk\n  include target/Makefile\n  include package/Makefile\n  include tools/Makefile\n  include toolchain/Makefile\n\n$(toolchain/stamp-compile): $(tools/stamp-compile) $(if $(CONFIG_BUILDBOT),toolchain_rebuild_check)\n$(target/stamp-compile): $(toolchain/stamp-compile) $(tools/stamp-compile) $(BUILD_DIR)/.prepared\n$(package/stamp-compile): $(target/stamp-compile) $(package/stamp-cleanup)\n$(package/stamp-install): $(package/stamp-compile)\n$(target/stamp-install): $(package/stamp-compile) $(package/stamp-install)\ncheck: $(tools/stamp-check) $(toolchain/stamp-check) $(package/stamp-check)\n\nprintdb:\n\t@true\n\nprepare: $(target/stamp-compile)\n\n_clean: FORCE\n\trm -rf $(BUILD_DIR) $(STAGING_DIR) $(BIN_DIR) $(OUTPUT_DIR)/packages/$(ARCH_PACKAGES) $(TOPDIR)/staging_dir/packages\n\nclean: _clean\n\trm -rf $(BUILD_LOG_DIR)\n\ntargetclean: _clean\n\trm -rf $(TOOLCHAIN_DIR) $(BUILD_DIR_BASE)/hostpkg $(BUILD_DIR_TOOLCHAIN)\n\ndirclean: targetclean clean\n\trm -rf $(STAGING_DIR_HOST) $(STAGING_DIR_HOSTPKG) $(BUILD_DIR_BASE)/host\n\trm -rf $(TMP_DIR)\n\t$(MAKE) -C $(TOPDIR)/scripts/config clean\n\ntoolchain_rebuild_check:\n\t$(SCRIPT_DIR)/check-toolchain-clean.sh\n\ncacheclean:\nifneq ($(CONFIG_CCACHE),)\n\t$(STAGING_DIR_HOST)/bin/ccache -C\nendif\n\nifndef DUMP_TARGET_DB\n$(BUILD_DIR)/.prepared: Makefile\n\t@mkdir -p $$(dirname $@)\n\t@touch $@\n\ntmp/.prereq_packages: .config\n\tunset ERROR; \\\n\tfor package in $(sort $(prereq-y) $(prereq-m)); do \\\n\t\t$(_SINGLE)$(NO_TRACE_MAKE) -s -r -C package/$$package prereq || ERROR=1; \\\n\tdone; \\\n\tif [ -n \"$$ERROR\" ]; then \\\n\t\techo \"Package prerequisite check failed.\"; \\\n\t\tfalse; \\\n\tfi\n\ttouch $@\nendif\n\n# check prerequisites before starting to build\nprereq: $(target/stamp-prereq) tmp/.prereq_packages\n\t@if [ ! -f \"$(INCLUDE_DIR)/site/$(ARCH)\" ]; then \\\n\t\techo 'ERROR: Missing site config for architecture \"$(ARCH)\" !'; \\\n\t\techo '       The missing file will cause configure scripts to fail during compilation.'; \\\n\t\techo '       Please provide a \"$(INCLUDE_DIR)/site/$(ARCH)\" file and restart the build.'; \\\n\t\texit 1; \\\n\tfi\n\n$(BIN_DIR)/profiles.json: FORCE\n\t$(if $(CONFIG_JSON_OVERVIEW_IMAGE_INFO), \\\n\t\tWORK_DIR=$(BUILD_DIR)/json_info_files \\\n\t\t\t$(SCRIPT_DIR)/json_overview_image_info.py $@ \\\n\t)\n\njson_overview_image_info: $(BIN_DIR)/profiles.json\n\nchecksum: FORCE\n\t$(call sha256sums,$(BIN_DIR),$(CONFIG_BUILDBOT))\n\nbuildversion: FORCE\n\t$(SCRIPT_DIR)/getver.sh > $(BIN_DIR)/version.buildinfo\n\nfeedsversion: FORCE\n\t$(SCRIPT_DIR)/feeds list -fs > $(BIN_DIR)/feeds.buildinfo\n\ndiffconfig: FORCE\n\tmkdir -p $(BIN_DIR)\n\t$(SCRIPT_DIR)/diffconfig.sh > $(BIN_DIR)/config.buildinfo\n\nbuildinfo: FORCE\n\t$(_SINGLE)$(SUBMAKE) -r diffconfig buildversion feedsversion\n\nprepare: .config $(tools/stamp-compile) $(toolchain/stamp-compile)\n\t$(_SINGLE)$(SUBMAKE) -r buildinfo\n\nworld: prepare $(target/stamp-compile) $(package/stamp-compile) $(package/stamp-install) $(target/stamp-install) FORCE\n\t$(_SINGLE)$(SUBMAKE) -r package/index\n\t$(_SINGLE)$(SUBMAKE) -r json_overview_image_info\n\t$(_SINGLE)$(SUBMAKE) -r checksum\nifneq ($(CONFIG_CCACHE),)\n\t$(STAGING_DIR_HOST)/bin/ccache -s\nendif\n\n.PHONY: clean dirclean prereq prepare world package/symlinks package/symlinks-install package/symlinks-clean\n\nendif\n"
  },
  {
    "path": "README.md",
    "content": "![OpenWrt logo](include/logo.png)\n\nOpenWrt Project is a Linux operating system targeting embedded devices. Instead\nof trying to create a single, static firmware, OpenWrt provides a fully\nwritable filesystem with package management. This frees you from the\napplication selection and configuration provided by the vendor and allows you\nto customize the device through the use of packages to suit any application.\nFor developers, OpenWrt is the framework to build an application without having\nto build a complete firmware around it; for users this means the ability for\nfull customization, to use the device in ways never envisioned.\n\nSunshine!\n\n## Development\n\nTo build your own firmware you need a GNU/Linux, BSD or MacOSX system (case\nsensitive filesystem required). Cygwin is unsupported because of the lack of a\ncase sensitive file system.\n\n### Requirements\n\nYou need the following tools to compile OpenWrt, the package names vary between\ndistributions. A complete list with distribution specific packages is found in\nthe [Build System Setup](https://openwrt.org/docs/guide-developer/build-system/install-buildsystem)\ndocumentation.\n\n```\nbinutils bzip2 diff find flex gawk gcc-6+ getopt grep install libc-dev libz-dev\nmake4.1+ perl python3.6+ rsync subversion unzip which\n```\n\n### Quickstart\n\n1. Run `./scripts/feeds update -a` to obtain all the latest package definitions\n   defined in feeds.conf / feeds.conf.default\n\n2. Run `./scripts/feeds install -a` to install symlinks for all obtained\n   packages into package/feeds/\n\n3. Run `make menuconfig` to select your preferred configuration for the\n   toolchain, target system & firmware packages.\n\n4. Run `make` to build your firmware. This will download all sources, build the\n   cross-compile toolchain and then cross-compile the GNU/Linux kernel & all chosen\n   applications for your target system.\n\n### Related Repositories\n\nThe main repository uses multiple sub-repositories to manage packages of\ndifferent categories. All packages are installed via the OpenWrt package\nmanager called `opkg`. If you're looking to develop the web interface or port\npackages to OpenWrt, please find the fitting repository below.\n\n* [LuCI Web Interface](https://github.com/openwrt/luci): Modern and modular\n  interface to control the device via a web browser.\n\n* [OpenWrt Packages](https://github.com/openwrt/packages): Community repository\n  of ported packages.\n\n* [OpenWrt Routing](https://github.com/openwrt/routing): Packages specifically\n  focused on (mesh) routing.\n\n* [OpenWrt Video](https://github.com/openwrt/video): Packages specifically\n  focused on display servers and clients (Xorg and Wayland).\n\n## Support Information\n\nFor a list of supported devices see the [OpenWrt Hardware Database](https://openwrt.org/supported_devices)\n\n### Documentation\n\n* [Quick Start Guide](https://openwrt.org/docs/guide-quick-start/start)\n* [User Guide](https://openwrt.org/docs/guide-user/start)\n* [Developer Documentation](https://openwrt.org/docs/guide-developer/start)\n* [Technical Reference](https://openwrt.org/docs/techref/start)\n\n### Support Community\n\n* [Forum](https://forum.openwrt.org): For usage, projects, discussions and hardware advise.\n* [Support Chat](https://webchat.oftc.net/#openwrt): Channel `#openwrt` on **oftc.net**.\n\n### Developer Community\n\n* [Bug Reports](https://bugs.openwrt.org): Report bugs in OpenWrt\n* [Dev Mailing List](https://lists.openwrt.org/mailman/listinfo/openwrt-devel): Send patches\n* [Dev Chat](https://webchat.oftc.net/#openwrt-devel): Channel `#openwrt-devel` on **oftc.net**.\n\n## License\n\nOpenWrt is licensed under GPL-2.0\n"
  },
  {
    "path": "config/Config-build.in",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2006-2013 OpenWrt.org\n# Copyright (C) 2016 LEDE Project\n\nconfig EXPERIMENTAL\n\tbool \"Enable experimental features by default\"\n\tdefault n\n\thelp\n\t  Set this option to build with latest bleeding edge features\n\t  which may or may not work as expected.\n\t  If you would like to help the development of OpenWrt, you are\n\t  encouraged to set this option and provide feedback (both\n\t  positive and negative). But do so only if you know how to\n\t  recover your device in case of flashing potentially non-working\n\t  firmware.\n\n\t  If you plan to use this build in production, say NO!\n\nmenu \"Global build settings\"\n\n\tconfig JSON_OVERVIEW_IMAGE_INFO\n\t\tbool \"Create JSON info file overview per target\"\n\t\tdefault y\n\t\thelp\n\t\t  Create a JSON info file called profiles.json in the target\n\t\t  directory containing machine readable list of built profiles\n\t\t  and resulting images.\n\n\tconfig ALL_NONSHARED\n\t\tbool \"Select all target specific packages by default\"\n\t\tselect ALL_KMODS\n\t\tdefault BUILDBOT\n\n\tconfig ALL_KMODS\n\t\tbool \"Select all kernel module packages by default\"\n\n\tconfig ALL\n\t\tbool \"Select all userspace packages by default\"\n\t\tselect ALL_KMODS\n\t\tselect ALL_NONSHARED\n\n\tconfig BUILDBOT\n\t\tbool \"Set build defaults for automatic builds (e.g. via buildbot)\"\n\t\tdefault n\n\t\thelp\n\t\t  This option changes several defaults to be more suitable for\n\t\t  automatic builds. This includes the following changes:\n\t\t  - Deleting build directories after compiling (to save space)\n\t\t  - Enabling per-device rootfs support\n\t\t  ...\n\n\tconfig SIGNED_PACKAGES\n\t\tbool \"Cryptographically signed package lists\"\n\t\tdefault y\n\n\tconfig SIGNATURE_CHECK\n\t\tbool \"Enable signature checking in opkg\"\n\t\tdefault SIGNED_PACKAGES\n\n\tcomment \"General build options\"\n\n\tconfig TESTING_KERNEL\n\t\tbool \"Use the testing kernel version\"\n\t\tdepends on HAS_TESTING_KERNEL\n\t\tdefault EXPERIMENTAL\n\t\thelp\n\t\t  If the target supports a newer kernel version than the default,\n\t\t  you can use this config option to enable it\n\n\n\tconfig DISPLAY_SUPPORT\n\t\tbool \"Show packages that require graphics support (local or remote)\"\n\t\tdefault n\n\n\tconfig BUILD_PATENTED\n\t\tdefault n\n\t\tbool \"Compile with support for patented functionality\"\n\t\thelp\n\t\t  When this option is disabled, software which provides patented functionality\n\t\t  will not be built.  In case software provides optional support for patented\n\t\t  functionality, this optional support will get disabled for this package.\n\n\tconfig BUILD_NLS\n\t\tdefault n\n\t\tbool \"Compile with full language support\"\n\t\thelp\n\t\t  When this option is enabled, packages are built with the full versions of\n\t\t  iconv and GNU gettext instead of the default OpenWrt stubs. If uClibc is\n\t\t  used, it is also built with locale support.\n\n\tconfig SHADOW_PASSWORDS\n\t\tbool\n\t\tdefault y\n\n\tconfig CLEAN_IPKG\n\t\tbool\n\t\tprompt \"Remove ipkg/opkg status data files in final images\"\n\t\tdefault n\n\t\thelp\n\t\t  This removes all ipkg/opkg status data files from the target directory\n\t\t  before building the root filesystem.\n\n\tconfig IPK_FILES_CHECKSUMS\n\t\tbool\n\t\tprompt \"Record files checksums in package metadata\"\n\t\tdefault n\n\t\thelp\n\t\t  This makes file checksums part of package metadata. It increases size\n\t\t  but provides you with pkg_check command to check for flash corruptions.\n\n\tconfig INCLUDE_CONFIG\n\t\tbool \"Include build configuration in firmware\" if DEVEL\n\t\tdefault n\n\t\thelp\n\t\t  If enabled, buildinfo files will be stored in /etc/build.* of firmware.\n\n\tconfig REPRODUCIBLE_DEBUG_INFO\n\t\tbool \"Make debug information reproducible\"\n\t\tdefault BUILDBOT\n\t\thelp\n\t\t  This strips the local build path out of debug information. This has the\n\t\t  advantage of making it reproducible, but the disadvantage of making local\n\t\t  debugging using ./scripts/remote-gdb harder, since the debug data will\n\t\t  no longer point to the full path on the build host.\n\n\tconfig COLLECT_KERNEL_DEBUG\n\t\tbool\n\t\tprompt \"Collect kernel debug information\"\n\t\tselect KERNEL_DEBUG_INFO\n\t\tdefault BUILDBOT\n\t\thelp\n\t\t  This collects debugging symbols from the kernel and all compiled modules.\n\t\t  Useful for release builds, so that kernel issues can be debugged offline\n\t\t  later.\n\n\tmenu \"Kernel build options\"\n\n\tsource \"config/Config-kernel.in\"\n\n\tendmenu\n\n\tcomment \"Package build options\"\n\n\tconfig DEBUG\n\t\tbool\n\t\tprompt \"Compile packages with debugging info\"\n\t\tdefault n\n\t\thelp\n\t\t  Adds -g3 to the CFLAGS.\n\n\tconfig IPV6\n\t\tbool\n\t\tprompt \"Enable IPv6 support in packages\"\n\t\tdefault y\n\t\thelp\n\t\t  Enables IPv6 support in kernel (builtin) and packages.\n\n\tcomment \"Stripping options\"\n\n\tchoice\n\t\tprompt \"Binary stripping method\"\n\t\tdefault USE_STRIP   if EXTERNAL_TOOLCHAIN\n\t\tdefault USE_STRIP   if USE_GLIBC\n\t\tdefault USE_SSTRIP\n\t\thelp\n\t\t  Select the binary stripping method you wish to use.\n\n\t\tconfig NO_STRIP\n\t\t\tbool \"none\"\n\t\t\thelp\n\t\t\t  This will install unstripped binaries (useful for native\n\t\t\t  compiling/debugging).\n\n\t\tconfig USE_STRIP\n\t\t\tbool \"strip\"\n\t\t\thelp\n\t\t\t  This will install binaries stripped using strip from binutils.\n\n\n\t\tconfig USE_SSTRIP\n\t\t\tbool \"sstrip\"\n\t\t\tdepends on !USE_GLIBC\n\t\t\thelp\n\t\t\t  This will install binaries stripped using sstrip.\n\tendchoice\n\n\tconfig STRIP_ARGS\n\t\tstring\n\t\tprompt \"Strip arguments\"\n\t\tdepends on USE_STRIP\n\t\tdefault \"--strip-unneeded --remove-section=.comment --remove-section=.note\" if DEBUG\n\t\tdefault \"--strip-all\"\n\t\thelp\n\t\t  Specifies arguments passed to the strip command when stripping binaries.\n\n\tconfig SSTRIP_ARGS\n\t\tstring\n\t\tprompt \"Sstrip arguments\"\n\t\tdepends on USE_SSTRIP\n\t\tdefault \"-z\"\n\t\thelp\n\t\t  Specifies arguments passed to the sstrip command when stripping binaries.\n\n\tconfig STRIP_KERNEL_EXPORTS\n\t\tbool \"Strip unnecessary exports from the kernel image\"\n\t\thelp\n\t\t  Reduces kernel size by stripping unused kernel exports from the kernel\n\t\t  image.  Note that this might make the kernel incompatible with any kernel\n\t\t  modules that were not selected at the time the kernel image was created.\n\n\tconfig USE_MKLIBS\n\t\tbool \"Strip unnecessary functions from libraries\"\n\t\thelp\n\t\t  Reduces libraries to only those functions that are necessary for using all\n\t\t  selected packages (including those selected as <M>).  Note that this will\n\t\t  make the system libraries incompatible with most of the packages that are\n\t\t  not selected during the build process.\n\n\tcomment \"Hardening build options\"\n\n\tconfig PKG_CHECK_FORMAT_SECURITY\n\t\tbool\n\t\tprompt \"Enable gcc format-security\"\n\t\tdefault y\n\t\thelp\n\t\t  Add -Wformat -Werror=format-security to the CFLAGS.  You can disable\n\t\t  this per package by adding PKG_CHECK_FORMAT_SECURITY:=0 in the package\n\t\t  Makefile.\n\n\tchoice\n\t\tprompt \"User space ASLR PIE compilation\"\n\t\tdefault PKG_ASLR_PIE_NONE if ((SMALL_FLASH || LOW_MEMORY_FOOTPRINT) && !SDK)\n\t\tdefault PKG_ASLR_PIE_REGULAR\n\t\thelp\n\t\t  Add -fPIC to CFLAGS and -specs=hardened-build-ld to LDFLAGS.\n\t\t  This enables package build as Position Independent Executables (PIE)\n\t\t  to protect against \"return-to-text\" attacks. This belongs to the\n\t\t  feature of Address Space Layout Randomisation (ASLR), which is\n\t\t  implemented by the kernel and the ELF loader by randomising the\n\t\t  location of memory allocations. This makes memory addresses harder\n\t\t  to predict when an attacker is attempting a memory-corruption exploit.\n\t\t  You can disable this per package by adding PKG_ASLR_PIE:=0 in the package\n\t\t  Makefile.\n\t\t  Be ware that ASLR increases the binary size.\n\t\tconfig PKG_ASLR_PIE_NONE\n\t\t\tbool \"None\"\n\t\t\thelp\n\t\t\t  PIE is deactivated for all applications\n\t\tconfig PKG_ASLR_PIE_REGULAR\n\t\t\tbool \"Regular\"\n\t\t\thelp\n\t\t\t  PIE is activated for some binaries, mostly network exposed applications\n\t\tconfig PKG_ASLR_PIE_ALL\n\t\t\tbool \"All\"\n\t\t\tselect BUSYBOX_DEFAULT_PIE\n\t\t\thelp\n\t\t\t  PIE is activated for all applications\n\tendchoice\n\n\tchoice\n\t\tprompt \"User space Stack-Smashing Protection\"\n\t\tdefault PKG_CC_STACKPROTECTOR_REGULAR\n\t\thelp\n\t\t  Enable GCC Stack Smashing Protection (SSP) for userspace applications\n\t\tconfig PKG_CC_STACKPROTECTOR_NONE\n\t\t\tbool \"None\"\n\t\tconfig PKG_CC_STACKPROTECTOR_REGULAR\n\t\t\tbool \"Regular\"\n\t\tconfig PKG_CC_STACKPROTECTOR_STRONG\n\t\t\tbool \"Strong\"\n\tendchoice\n\n\tchoice\n\t\tprompt \"Kernel space Stack-Smashing Protection\"\n\t\tdefault KERNEL_CC_STACKPROTECTOR_REGULAR\n\t\thelp\n\t\t  Enable GCC Stack-Smashing Protection (SSP) for the kernel\n\t\tconfig KERNEL_CC_STACKPROTECTOR_NONE\n\t\t\tbool \"None\"\n\t\tconfig KERNEL_CC_STACKPROTECTOR_REGULAR\n\t\t\tbool \"Regular\"\n\t\tconfig KERNEL_CC_STACKPROTECTOR_STRONG\n\t\t\tbool \"Strong\"\n\tendchoice\n\n\tconfig KERNEL_STACKPROTECTOR\n\t\tbool\n\t\tdefault KERNEL_CC_STACKPROTECTOR_REGULAR || KERNEL_CC_STACKPROTECTOR_STRONG\n\n\tconfig KERNEL_STACKPROTECTOR_STRONG\n\t\tbool\n\t\tdefault KERNEL_CC_STACKPROTECTOR_STRONG\n\n\tchoice\n\t\tprompt \"Enable buffer-overflows detection (FORTIFY_SOURCE)\"\n\t\tdefault PKG_FORTIFY_SOURCE_1\n\t\thelp\n\t\t  Enable the _FORTIFY_SOURCE macro which introduces additional\n\t\t  checks to detect buffer-overflows in the following standard library\n\t\t  functions: memcpy, mempcpy, memmove, memset, strcpy, stpcpy,\n\t\t  strncpy, strcat, strncat, sprintf, vsprintf, snprintf, vsnprintf,\n\t\t  gets.  \"Conservative\" (_FORTIFY_SOURCE set to 1) only introduces\n\t\t  checks that shouldn't change the behavior of conforming programs,\n\t\t  while \"aggressive\" (_FORTIFY_SOURCES set to 2) some more checking is\n\t\t  added, but some conforming programs might fail.\n\t\tconfig PKG_FORTIFY_SOURCE_NONE\n\t\t\tbool \"None\"\n\t\tconfig PKG_FORTIFY_SOURCE_1\n\t\t\tbool \"Conservative\"\n\t\tconfig PKG_FORTIFY_SOURCE_2\n\t\t\tbool \"Aggressive\"\n\tendchoice\n\n\tchoice\n\t\tprompt \"Enable RELRO protection\"\n\t\tdefault PKG_RELRO_FULL\n\t\thelp\n\t\t  Enable a link-time protection known as RELRO (Relocation Read Only)\n\t\t  which helps to protect from certain type of exploitation techniques\n\t\t  altering the content of some ELF sections. \"Partial\" RELRO makes the\n\t\t  .dynamic section not writeable after initialization, introducing\n\t\t  almost no performance penalty, while \"full\" RELRO also marks the GOT\n\t\t  as read-only at the cost of initializing all of it at startup.\n\t\tconfig PKG_RELRO_NONE\n\t\t\tbool \"None\"\n\t\tconfig PKG_RELRO_PARTIAL\n\t\t\tbool \"Partial\"\n\t\tconfig PKG_RELRO_FULL\n\t\t\tbool \"Full\"\n\tendchoice\n\n\tconfig TARGET_ROOTFS_SECURITY_LABELS\n\t\tbool\n\t\tselect KERNEL_SQUASHFS_XATTR\n\t\tselect KERNEL_EXT4_FS_SECURITY\n\t\tselect KERNEL_F2FS_FS_SECURITY\n\t\tselect KERNEL_UBIFS_FS_SECURITY\n\t\tselect KERNEL_JFFS2_FS_SECURITY\n\n\tconfig SELINUX\n\t\tbool \"Enable SELinux\"\n\t\tselect KERNEL_SECURITY_SELINUX\n\t\tselect TARGET_ROOTFS_SECURITY_LABELS\n\t\tselect PACKAGE_procd-selinux\n\t\tselect PACKAGE_busybox-selinux\n\t\thelp\n\t\t  This option enables SELinux kernel features, applies security labels\n\t\t  in squashfs rootfs and selects the selinux-variants of busybox and procd.\n\n\t\t  Selecting this option results in about 0.5MiB of additional flash space\n\t\t  usage accounting for increased kernel and rootfs size.\n\n\tchoice\n\t\tprompt \"default SELinux type\"\n\t\tdepends on TARGET_ROOTFS_SECURITY_LABELS\n\t\tdefault SELINUXTYPE_dssp\n\t\thelp\n\t\t  Select SELinux policy to be installed and used for applying rootfs labels.\n\n\t\tconfig SELINUXTYPE_targeted\n\t\t\tbool \"targeted\"\n\t\t\tselect PACKAGE_refpolicy\n\t\t\thelp\n\t\t\t  SELinux Reference Policy (refpolicy)\n\n\t\tconfig SELINUXTYPE_dssp\n\t\t\tbool \"dssp\"\n\t\t\tselect PACKAGE_selinux-policy\n\t\t\thelp\n\t\t\t  Defensec SELinux Security Policy -- OpenWrt edition\n\n\tendchoice\n\n\tconfig SECCOMP\n\t\tbool \"Enable SECCOMP\"\n\t\tselect KERNEL_SECCOMP\n\t\tselect PACKAGE_procd-seccomp\n\t\tdepends on (aarch64 || arm || armeb || mips || mipsel || mips64 || mips64el || i386 || powerpc || x86_64)\n\t\tdepends on !TARGET_uml\n\t\tdefault y\n\t\thelp\n\t\t  This option enables seccomp kernel features to safely\n\t\t  execute untrusted bytecode and selects the seccomp-variants\n\t\t  of procd\n\nendmenu\n"
  },
  {
    "path": "config/Config-devel.in",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2006-2013 OpenWrt.org\n\nmenuconfig DEVEL\n\tbool \"Advanced configuration options (for developers)\"\n\tdefault n\n\n\tconfig BROKEN\n\t\tbool \"Show broken platforms / packages / devices\" if DEVEL\n\t\tdefault n\n\n\tconfig BINARY_FOLDER\n\t\tstring \"Binary folder\" if DEVEL\n\t\tdefault \"\"\n\t\thelp\n\t\t  Store built firmware images and filesystem images in this directory.\n\t\t  If not set, uses './bin/$(BOARD)'\n\n\tconfig DOWNLOAD_FOLDER\n\t\tstring \"Download folder\" if DEVEL\n\t\tdefault \"\"\n\t\thelp\n\t\t  Store downloaded source bundles in this directory.\n\t\t  If not set then defaults to './dl', which is removed by operations such as\n\t\t  'git clean -xdf' or 'make distclean'.\n\t\t  This option is useful if you have a low bandwidth Internet connection, and by\n\t\t  setting a path outside the OpenWrt tree downloads will be saved.\n\n\tconfig LOCALMIRROR\n\t\tstring \"Local mirror for source packages\" if DEVEL\n\t\tdefault \"\"\n\n\tconfig AUTOREBUILD\n\t\tbool \"Automatic rebuild of packages\" if DEVEL\n\t\tdefault y\n\t\thelp\n\t\t  Automatically rebuild packages when their files change.\n\n\tconfig AUTOREMOVE\n\t\tbool \"Automatic removal of build directories\" if DEVEL\n\t\tdefault n\n\t\thelp\n\t\t  Automatically delete build directories after make target completed.\n\t\t  This allows you to symlink build_dir into a scratch location, e.g. a ramdisk,\n\t\t  which does not have enough space to keep a complete build_dir.\n\n\tconfig BUILD_SUFFIX\n\t\tstring \"Build suffix to append to the target BUILD_DIR variable\" if DEVEL\n\t\tdefault \"\"\n\t\thelp\n\t\t  Build suffix to append to the BUILD_DIR variable, i.e: './build_dir/{target-build-dir}_$(BUILD_SUFFIX)'.\n\t\t  This allows you to switch to a different .config whilst retaining all the build\n\t\t  objects generated by the first .config\n\n\tconfig TARGET_ROOTFS_DIR\n\t\tstring \"Override the default TARGET_ROOTFS_DIR variable\" if DEVEL\n\t\tdefault \"\"\n\t\thelp\n\t\t  Override the default TARGET_ROOTFS_DIR variable content $(BUILD_DIR) with\n\t\t  custom path.  Use this option to re-define the location of the target\n\t\t  root filesystem directory.\n\n\tconfig CCACHE\n\t\tbool \"Use ccache\" if DEVEL\n\t\tdefault n\n\t\thelp\n\t\t  Compiler cache; see https://ccache.samba.org/\n\n\tconfig CCACHE_DIR\n\t\tstring \"Set ccache directory\" if CCACHE\n\t\tdefault \"\"\n\t\thelp\n\t\t  Store ccache in this directory.\n\t\t  If not set, uses './.ccache'\n\n\tconfig EXTERNAL_KERNEL_TREE\n\t\tstring \"Use external kernel tree\" if DEVEL\n\t\tdefault \"\"\n\n\tconfig KERNEL_GIT_CLONE_URI\n\t\tstring \"Enter git repository to clone\" if DEVEL\n\t\tdefault \"\"\n\t\thelp\n\t\t  Enter the full git repository path i.e.:\n\t\t  git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git\n\t\t  This will create a git clone of the kernel in your build directory.\n\n\tconfig KERNEL_GIT_LOCAL_REPOSITORY\n\t\tstring \"Enter path to local reference repository\" if DEVEL\n\t\tdepends on (KERNEL_GIT_CLONE_URI != \"\")\n\t\tdefault \"\"\n\t\thelp\n\t\t  Enter a full pathname to a local reference git repository.\n\t\t  In this instance, the --reference option of git clone will\n\t\t  be used thus creating a quick local clone of your repo.\n\n\tconfig KERNEL_GIT_REF\n\t\tstring \"Enter git ref at which to checkout\" if DEVEL\n\t\tdepends on (KERNEL_GIT_CLONE_URI != \"\")\n\t\tdefault \"\"\n\t\thelp\n\t\t  Enter the git ref at which to checkout the git repository\n\t\t  after it is cloned, and before making it a tar-ball.\n\t\t  It can be a git hash or a branch name.\n\t\t  If unused, the clone's repository HEAD will be checked-out.\n\n\tconfig KERNEL_GIT_MIRROR_HASH\n\t\tstring \"Enter hash of Git kernel tree source checkout tarball\" if DEVEL\n\t\tdepends on (KERNEL_GIT_CLONE_URI != \"\")\n\t\tdefault \"\"\n\n\tconfig BUILD_LOG\n\t\tbool \"Enable log files during build process\" if DEVEL\n\t\thelp\n\t\t  If enabled, log files will be written to the ./log directory.\n\n\tconfig BUILD_LOG_DIR\n\t\tstring \"Log folder\" if DEVEL\n\t\tdefault \"\"\n\t\thelp\n\t\t  Store build logs in this directory.\n\t\t  If not set, uses './logs'\n\n\tconfig SRC_TREE_OVERRIDE\n\t\tbool \"Enable package source tree override\" if DEVEL\n\t\thelp\n\t\t  If enabled, you can force a package to use a git tree as source\n\t\t  code instead of the normal tarball. Create a symlink 'git-src'\n\t\t  in the package directory, pointing to the .git tree that you want\n\t\t  to pull the source code from.\n\n\tconfig EXTRA_OPTIMIZATION\n\t\tstring \"Additional compiler options\" if DEVEL\n\t\tdefault \"-fno-caller-saves -fno-plt\" if !CONFIG_EXTERNAL_TOOLCHAIN && !arc\n\t\tdefault \"-fno-caller-saves\"\n\t\thelp\n\t\t  Extra target-independent optimizations to use when building for the target.\n"
  },
  {
    "path": "config/Config-images.in",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2006-2013 OpenWrt.org\n\nmenu \"Target Images\"\n\n\tmenuconfig TARGET_ROOTFS_INITRAMFS\n\t\tbool \"ramdisk\"\n\t\tdefault y if USES_INITRAMFS\n\t\thelp\n\t\t  Embed the root filesystem into the kernel (initramfs).\n\n\t\tchoice\n\t\t\tprompt \"Compression\"\n\t\t\tdefault TARGET_INITRAMFS_COMPRESSION_LZMA if TARGET_apm821xx\n\t\t\tdefault TARGET_INITRAMFS_COMPRESSION_LZMA if TARGET_ath79_mikrotik\n\t\t\tdefault TARGET_INITRAMFS_COMPRESSION_LZMA if TARGET_lantiq\n\t\t\tdefault TARGET_INITRAMFS_COMPRESSION_LZMA if TARGET_mpc85xx\n\t\t\tdefault TARGET_INITRAMFS_COMPRESSION_LZMA if TARGET_ramips\n\t\t\tdefault TARGET_INITRAMFS_COMPRESSION_XZ if USES_SEPARATE_INITRAMFS\n\t\t\tdefault TARGET_INITRAMFS_COMPRESSION_NONE\n\t\t\tdepends on TARGET_ROOTFS_INITRAMFS\n\t\t\thelp\n\t\t\t  Select ramdisk compression.\n\n\t\t\tconfig TARGET_INITRAMFS_COMPRESSION_NONE\n\t\t\t\tbool \"none\"\n\n\t\t\tconfig TARGET_INITRAMFS_COMPRESSION_GZIP\n\t\t\t\tbool \"gzip\"\n\n\t\t\tconfig TARGET_INITRAMFS_COMPRESSION_BZIP2\n\t\t\t\tbool \"bzip2\"\n\n\t\t\tconfig TARGET_INITRAMFS_COMPRESSION_LZMA\n\t\t\t\tbool \"lzma\"\n\n\t\t\tconfig TARGET_INITRAMFS_COMPRESSION_LZO\n\t\t\t\tdepends on !TARGET_ROOTFS_INITRAMFS_SEPARATE\n\t\t\t\tbool \"lzo\"\n\n\t\t\tconfig TARGET_INITRAMFS_COMPRESSION_LZ4\n\t\t\t\tdepends on !TARGET_ROOTFS_INITRAMFS_SEPARATE\n\t\t\t\tbool \"lz4\"\n\n\t\t\tconfig TARGET_INITRAMFS_COMPRESSION_XZ\n\t\t\t\tbool \"xz\"\n\n\t\t\tconfig TARGET_INITRAMFS_COMPRESSION_ZSTD\n\t\t\t\tdepends on !LINUX_5_4 && !LINUX_4_19\n\t\t\t\tbool \"zstd\"\n\t\tendchoice\n\n\t\tconfig EXTERNAL_CPIO\n\t\t\tstring\n\t\t\tprompt \"Use external cpio\" if TARGET_ROOTFS_INITRAMFS\n\t\t\tdefault \"\"\n\t\t\thelp\n\t\t\t  Kernel uses specified external cpio as INITRAMFS_SOURCE.\n\n\t\tconfig TARGET_INITRAMFS_FORCE\n\t\t\tbool \"Force\"\n\t\t\tdepends on TARGET_ROOTFS_INITRAMFS\n\t\t\tdefault n\n\t\t\thelp\n\t\t\t  Ignore the initramfs passed by the bootloader.\n\n\t\tconfig TARGET_ROOTFS_INITRAMFS_SEPARATE\n\t\t\tbool \"separate ramdisk\"\n\t\t\tdepends on USES_SEPARATE_INITRAMFS && TARGET_ROOTFS_INITRAMFS && !TARGET_INITRAMFS_FORCE\n\t\t\tdefault y if USES_SEPARATE_INITRAMFS\n\t\t\thelp\n\t\t\t  Generate separate initrd.cpio instead of embedding it.\n\t\t\t  This is useful for generating images with a dedicated\n\t\t\t  ramdisk e.g. in U-Boot's uImage and uImage.FIT formats.\n\n\tcomment \"Root filesystem archives\"\n\n\tconfig TARGET_ROOTFS_CPIOGZ\n\t\tbool \"cpio.gz\"\n\t\tdefault y if USES_CPIOGZ\n\t\thelp\n\t\t  Build a compressed cpio archive of the root filesystem.\n\n\tconfig TARGET_ROOTFS_TARGZ\n\t\tbool \"tar.gz\"\n\t\tdefault y if USES_TARGZ\n\t\thelp\n\t\t  Build a compressed tar archive of the root filesystem.\n\n\tcomment \"Root filesystem images\"\n\n\tmenuconfig TARGET_ROOTFS_EXT4FS\n\t\tbool \"ext4\"\n\t\tdefault y if USES_EXT4\n\t\thelp\n\t\t  Build an ext4 root filesystem.\n\n\t\tconfig TARGET_EXT4_RESERVED_PCT\n\t\t\tint \"Percentage of reserved blocks in root filesystem\"\n\t\t\tdepends on TARGET_ROOTFS_EXT4FS\n\t\t\tdefault 0\n\t\t\thelp\n\t\t\t  Select the percentage of reserved blocks in the root filesystem.\n\n\t\tchoice\n\t\t\tprompt \"Root filesystem block size\"\n\t\t\tdefault TARGET_EXT4_BLOCKSIZE_4K\n\t\t\tdepends on TARGET_ROOTFS_EXT4FS\n\t\t\thelp\n\t\t\t  Select the block size of the root filesystem.\n\n\t\t\tconfig TARGET_EXT4_BLOCKSIZE_4K\n\t\t\t\tbool \"4k\"\n\n\t\t\tconfig TARGET_EXT4_BLOCKSIZE_2K\n\t\t\t\tbool \"2k\"\n\n\t\t\tconfig TARGET_EXT4_BLOCKSIZE_1K\n\t\t\t\tbool \"1k\"\n\t\tendchoice\n\n\t\tconfig TARGET_EXT4_BLOCKSIZE\n\t\t\tint\n\t\t\tdefault 4096 if TARGET_EXT4_BLOCKSIZE_4K\n\t\t\tdefault 2048 if TARGET_EXT4_BLOCKSIZE_2K\n\t\t\tdefault 1024 if TARGET_EXT4_BLOCKSIZE_1K\n\t\t\tdepends on TARGET_ROOTFS_EXT4FS\n\n\t\tconfig TARGET_EXT4_JOURNAL\n\t\t\tbool \"Create a journaling filesystem\"\n\t\t\tdepends on TARGET_ROOTFS_EXT4FS\n\t\t\tdefault n\n\t\t\thelp\n\t\t\t  Create an ext4 filesystem with a journal.\n\n\tconfig TARGET_ROOTFS_JFFS2\n\t\tbool \"jffs2\"\n\t\tdepends on USES_JFFS2\n\t\thelp\n\t\t  Build a JFFS2 root filesystem.\n\n\tconfig TARGET_ROOTFS_JFFS2_NAND\n\t\tbool \"jffs2 for NAND\"\n\t\tdefault y if USES_JFFS2_NAND\n\t\tdepends on USES_JFFS2_NAND\n\t\thelp\n\t\t  Build a JFFS2 root filesystem for NAND flash.\n\n\tmenuconfig TARGET_ROOTFS_SQUASHFS\n\t\tbool \"squashfs\"\n\t\tdefault y if USES_SQUASHFS\n\t\thelp\n\t\t  Build a squashfs-lzma root filesystem.\n\n\t\tconfig TARGET_SQUASHFS_BLOCK_SIZE\n\t\t\tint \"Block size (in KiB)\"\n\t\t\tdepends on TARGET_ROOTFS_SQUASHFS\n\t\t\tdefault 64 if LOW_MEMORY_FOOTPRINT\n\t\t\tdefault 1024 if (SMALL_FLASH && !LOW_MEMORY_FOOTPRINT)\n\t\t\tdefault 256\n\n\tmenuconfig TARGET_ROOTFS_UBIFS\n\t\tbool \"ubifs\"\n\t\tdefault y if USES_UBIFS\n\t\tdepends on USES_UBIFS\n\t\thelp\n\t\t  Build a UBIFS root filesystem.\n\n\t\tchoice\n\t\t\tprompt \"compression\"\n\t\t\tdefault TARGET_UBIFS_COMPRESSION_ZLIB\n\t\t\tdepends on TARGET_ROOTFS_UBIFS\n\t\t\thelp\n\t\t\t  Select compression type\n\n\t\t\tconfig TARGET_UBIFS_COMPRESSION_NONE\n\t\t\t\tbool \"none\"\n\n\t\t\tconfig TARGET_UBIFS_COMPRESSION_LZO\n\t\t\t\tbool \"lzo\"\n\n\t\t\tconfig TARGET_UBIFS_COMPRESSION_ZLIB\n\t\t\t\tbool \"zlib\"\n\t\tendchoice\n\n\t\tconfig TARGET_UBIFS_FREE_SPACE_FIXUP\n\t\t\tbool \"free space fixup\" if TARGET_ROOTFS_UBIFS\n\t\t\tdefault y\n\t\t\thelp\n\t\t\t  The filesystem free space has to be fixed up on first mount.\n\n\t\tconfig TARGET_UBIFS_JOURNAL_SIZE\n\t\t\tstring\n\t\t\tprompt \"journal size\" if TARGET_ROOTFS_UBIFS\n\t\t\tdefault \"\"\n\n\tconfig GRUB_IMAGES\n\t\tbool \"Build GRUB images (Linux x86 or x86_64 host only)\"\n\t\tdepends on TARGET_x86\n\t\tdepends on TARGET_ROOTFS_EXT4FS || TARGET_ROOTFS_JFFS2 || TARGET_ROOTFS_SQUASHFS\n\t\tselect PACKAGE_grub2\n\t\tselect PACKAGE_grub2-bios-setup\n\t\tdefault y\n\n\tconfig GRUB_EFI_IMAGES\n\t\tbool \"Build GRUB EFI images (Linux x86 or x86_64 host only)\"\n\t\tdepends on TARGET_x86\n\t\tdepends on TARGET_ROOTFS_EXT4FS || TARGET_ROOTFS_JFFS2 || TARGET_ROOTFS_SQUASHFS\n\t\tselect PACKAGE_grub2\n\t\tselect PACKAGE_grub2-efi\n\t\tselect PACKAGE_grub2-bios-setup\n\t\tselect PACKAGE_kmod-fs-vfat\n\t\tdefault y\n\n\tconfig GRUB_CONSOLE\n\t\tbool \"Use Console Terminal (in addition to Serial)\"\n\t\tdepends on GRUB_IMAGES || GRUB_EFI_IMAGES\n\t\tdefault y\n\n\tconfig GRUB_SERIAL\n\t\tstring \"Serial port device\"\n\t\tdepends on GRUB_IMAGES || GRUB_EFI_IMAGES\n\t\tdefault \"ttyS0\"\n\n\tconfig GRUB_BAUDRATE\n\t\tint \"Serial port baud rate\"\n\t\tdepends on GRUB_IMAGES || GRUB_EFI_IMAGES\n\t\tdefault 38400 if TARGET_x86_generic\n\t\tdefault 115200\n\n\tconfig GRUB_FLOWCONTROL\n\t\tbool \"Use RTE/CTS on serial console\"\n\t\tdepends on GRUB_SERIAL != \"\"\n\t\tdefault n\n\n\tconfig GRUB_BOOTOPTS\n\t\tstring \"Extra kernel boot options\"\n\t\tdepends on GRUB_IMAGES || GRUB_EFI_IMAGES\n\t\thelp\n\t\t  If you don't know, just leave it blank.\n\n\tconfig GRUB_TIMEOUT\n\t\tstring \"Seconds to wait before booting the default entry\"\n\t\tdepends on GRUB_IMAGES || GRUB_EFI_IMAGES\n\t\tdefault \"5\"\n\t\thelp\n\t\t  If you don't know, 5 seconds is a reasonable default.\n\n\tconfig GRUB_TITLE\n\t\tstring \"Title for the menu entry in GRUB\"\n\t\tdepends on GRUB_IMAGES || GRUB_EFI_IMAGES\n\t\tdefault \"OpenWrt\"\n\t\thelp\n\t\t  This is the title of the GRUB menu entry.\n\t\t  If unspecified, it defaults to OpenWrt.\n\n\tconfig ISO_IMAGES\n\t\tbool \"Build LiveCD image (ISO)\"\n\t\tdepends on TARGET_x86\n\t\tdepends on GRUB_IMAGES || GRUB_EFI_IMAGES\n\n\tconfig VDI_IMAGES\n\t\tbool \"Build VirtualBox image files (VDI)\"\n\t\tdepends on TARGET_x86\n\t\tdepends on GRUB_IMAGES || GRUB_EFI_IMAGES\n\t\tselect PACKAGE_kmod-e1000\n\n\tconfig VMDK_IMAGES\n\t\tbool \"Build VMware image files (VMDK)\"\n\t\tdepends on TARGET_x86\n\t\tdepends on GRUB_IMAGES || GRUB_EFI_IMAGES\n\t\tselect PACKAGE_kmod-e1000\n\n\tconfig VHDX_IMAGES\n\t\tbool \"Build Hyper-V image files (VHDX)\"\n\t\tdepends on TARGET_x86\n\t\tdepends on GRUB_IMAGES || GRUB_EFI_IMAGES\n\t\tselect PACKAGE_kmod-e1000\n\n\tconfig TARGET_IMAGES_GZIP\n\t\tbool \"GZip images\"\n\t\tdepends on TARGET_ROOTFS_EXT4FS || TARGET_x86 || TARGET_armvirt || TARGET_malta\n\t\tdefault y\n\n\tcomment \"Image Options\"\n\n\tsource \"target/linux/*/image/Config.in\"\n\n\tconfig TARGET_KERNEL_PARTSIZE\n\t\tint \"Kernel partition size (in MiB)\"\n\t\tdepends on USES_BOOT_PART\n\t\tdefault 8 if TARGET_apm821xx_sata\n\t\tdefault 64 if TARGET_bcm27xx\n\t\tdefault 16\n\n\tconfig TARGET_ROOTFS_PARTSIZE\n\t\tint \"Root filesystem partition size (in MiB)\"\n\t\tdepends on USES_ROOTFS_PART || TARGET_ROOTFS_EXT4FS\n\t\tdefault 104\n\t\thelp\n\t\t  Select the root filesystem partition size.\n\n\tconfig TARGET_ROOTFS_PARTNAME\n\t\tstring \"Root partition on target device\"\n\t\tdepends on GRUB_IMAGES || GRUB_EFI_IMAGES\n\t\thelp\n\t\t  Override the root partition on the final device. If left empty,\n\t\t  it will be mounted by PARTUUID which makes the kernel find the\n\t\t  appropriate disk automatically.\n\n\tconfig TARGET_ROOTFS_PERSIST_VAR\n\t\tbool \"Make /var persistent\"\n\t\tdefault n\n\t\thelp\n\t\t  Do not symlink /var to /tmp, so that its content will persist\n\t\t  across reboots. When enabled, /var/run will still be linked\n\t\t  to /tmp/run.\n\nendmenu\n"
  },
  {
    "path": "config/Config-kernel.in",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2006-2014 OpenWrt.org\n\nconfig KERNEL_BUILD_USER\n\tstring \"Custom Kernel Build User Name\"\n\tdefault \"builder\" if BUILDBOT\n\tdefault \"\"\n\thelp\n\t  Sets the Kernel build user string, which for example will be returned\n\t  by 'uname -a' on running systems.\n\t  If not set, uses system user at build time.\n\nconfig KERNEL_BUILD_DOMAIN\n\tstring \"Custom Kernel Build Domain Name\"\n\tdefault \"buildhost\" if BUILDBOT\n\tdefault \"\"\n\thelp\n\t  Sets the Kernel build domain string, which for example will be\n\t  returned by 'uname -a' on running systems.\n\t  If not set, uses system hostname at build time.\n\nconfig KERNEL_PRINTK\n\tbool \"Enable support for printk\"\n\tdefault y\n\nconfig KERNEL_SWAP\n\tbool \"Support for paging of anonymous memory (swap)\"\n\tdefault y if !SMALL_FLASH\n\nconfig KERNEL_PROC_STRIPPED\n\tbool \"Strip non-essential /proc functionality to reduce code size\"\n\tdefault y if SMALL_FLASH\n\nconfig KERNEL_DEBUG_FS\n\tbool \"Compile the kernel with debug filesystem enabled\"\n\tdefault y\n\thelp\n\t  debugfs is a virtual file system that kernel developers use to put\n\t  debugging files into. Enable this option to be able to read and\n\t  write to these files. Many common debugging facilities, such as\n\t  ftrace, require the existence of debugfs.\n\nconfig KERNEL_MIPS_FP_SUPPORT\n\tbool\n\tdefault y if TARGET_pistachio\n\nconfig KERNEL_ARM_PMU\n\tbool\n\tdefault n\n\tdepends on (arm || aarch64)\n\nconfig KERNEL_X86_VSYSCALL_EMULATION\n\tbool \"Enable vsyscall emulation\"\n\tdefault n\n\tdepends on x86_64\n\thelp\n\t  This enables emulation of the legacy vsyscall page.  Disabling\n\t  it is roughly equivalent to booting with vsyscall=none, except\n\t  that it will also disable the helpful warning if a program\n\t  tries to use a vsyscall.  With this option set to N, offending\n\t  programs will just segfault, citing addresses of the form\n\t  0xffffffffff600?00.\n\n\t  This option is required by many programs built before 2013, and\n\t  care should be used even with newer programs if set to N.\n\n\t  Disabling this option saves about 7K of kernel size and\n\t  possibly 4K of additional runtime pagetable memory.\n\nconfig KERNEL_PERF_EVENTS\n\tbool \"Compile the kernel with performance events and counters\"\n\tdefault n\n\tselect KERNEL_ARM_PMU if (arm || aarch64)\n\nconfig KERNEL_PROFILING\n\tbool \"Compile the kernel with profiling enabled\"\n\tdefault n\n\tselect KERNEL_PERF_EVENTS\n\thelp\n\t  Enable the extended profiling support mechanisms used by profilers such\n\t  as OProfile.\n\nconfig KERNEL_UBSAN\n\tbool \"Compile the kernel with undefined behaviour sanity checker\"\n\thelp\n\t  This option enables undefined behaviour sanity checker\n\t  Compile-time instrumentation is used to detect various undefined\n\t  behaviours in runtime. Various types of checks may be enabled\n\t  via boot parameter ubsan_handle\n\t  (see: Documentation/dev-tools/ubsan.rst).\n\nconfig KERNEL_UBSAN_SANITIZE_ALL\n\tbool \"Enable instrumentation for the entire kernel\"\n\tdepends on KERNEL_UBSAN\n\tdefault y\n\thelp\n\t  This option activates instrumentation for the entire kernel.\n\t  If you don't enable this option, you have to explicitly specify\n\t  UBSAN_SANITIZE := y for the files/directories you want to check for UB.\n\t  Enabling this option will get kernel image size increased\n\t  significantly.\n\nconfig KERNEL_UBSAN_ALIGNMENT\n\tbool \"Enable checking of pointers alignment\"\n\tdepends on KERNEL_UBSAN\n\thelp\n\t  This option enables detection of unaligned memory accesses.\n\t  Enabling this option on architectures that support unaligned\n\t  accesses may produce a lot of false positives.\n\nconfig KERNEL_UBSAN_BOUNDS\n\tbool \"Perform array index bounds checking\"\n\tdepends on KERNEL_UBSAN\n\thelp\n\t  This option enables detection of directly indexed out of bounds array\n\t  accesses, where the array size is known at compile time. Note that\n\t  this does not protect array overflows via bad calls to the\n\t  {str,mem}*cpy() family of functions (that is addressed by\n\t  FORTIFY_SOURCE).\n\nconfig KERNEL_UBSAN_NULL\n\tbool \"Enable checking of null pointers\"\n\tdepends on KERNEL_UBSAN\n\thelp\n\t  This option enables detection of memory accesses via a\n\t  null pointer.\n\nconfig KERNEL_UBSAN_TRAP\n\tbool \"On Sanitizer warnings, abort the running kernel code\"\n\tdepends on KERNEL_UBSAN\n\thelp\n\t  Building kernels with Sanitizer features enabled tends to grow the\n\t  kernel size by around 5%, due to adding all the debugging text on\n\t  failure paths. To avoid this, Sanitizer instrumentation can just\n\t  issue a trap. This reduces the kernel size overhead but turns all\n\t  warnings (including potentially harmless conditions) into full\n\t  exceptions that abort the running kernel code (regardless of context,\n\t  locks held, etc), which may destabilize the system. For some system\n\t  builders this is an acceptable trade-off.\n\nconfig KERNEL_KASAN\n\tbool \"Compile the kernel with KASan: runtime memory debugger\"\n\tselect KERNEL_SLUB_DEBUG\n\tdepends on (x86_64 || aarch64)\n\thelp\n\t  Enables kernel address sanitizer - runtime memory debugger,\n\t  designed to find out-of-bounds accesses and use-after-free bugs.\n\t  This is strictly a debugging feature and it requires a gcc version\n\t  of 4.9.2 or later. Detection of out of bounds accesses to stack or\n\t  global variables requires gcc 5.0 or later.\n\t  This feature consumes about 1/8 of available memory and brings about\n\t  ~x3 performance slowdown.\n\t  For better error detection enable CONFIG_STACKTRACE.\n\t  Currently CONFIG_KASAN doesn't work with CONFIG_DEBUG_SLAB\n\t  (the resulting kernel does not boot).\n\nconfig KERNEL_KASAN_EXTRA\n\tbool \"KAsan: extra checks\"\n\tdepends on KERNEL_KASAN && KERNEL_DEBUG_KERNEL\n\thelp\n\t  This enables further checks in the kernel address sanitizer, for now\n\t  it only includes the address-use-after-scope check that can lead\n\t  to excessive kernel stack usage, frame size warnings and longer\n\t  compile time.\n\t  https://gcc.gnu.org/bugzilla/show_bug.cgi?id=81715 has more\n\nconfig KERNEL_KASAN_VMALLOC\n\tbool \"Back mappings in vmalloc space with real shadow memory\"\n\tdepends on KERNEL_KASAN\n\thelp\n\t  By default, the shadow region for vmalloc space is the read-only\n\t  zero page. This means that KASAN cannot detect errors involving\n\t  vmalloc space.\n\n\t  Enabling this option will hook in to vmap/vmalloc and back those\n\t  mappings with real shadow memory allocated on demand. This allows\n\t  for KASAN to detect more sorts of errors (and to support vmapped\n\t  stacks), but at the cost of higher memory usage.\n\n\t  This option depends on HAVE_ARCH_KASAN_VMALLOC, but we can't\n\t  depend on that in here, so it is possible that enabling this\n\t  will have no effect.\n\nif KERNEL_KASAN\n\tconfig KERNEL_KASAN_GENERIC\n\tdef_bool y\n\n\tconfig KERNEL_KASAN_SW_TAGS\n\tdef_bool n\nendif\n\nchoice\n\tprompt \"Instrumentation type\"\n\tdepends on KERNEL_KASAN\n\tdefault KERNEL_KASAN_OUTLINE\n\nconfig KERNEL_KASAN_OUTLINE\n\tbool \"Outline instrumentation\"\n\thelp\n\t  Before every memory access compiler insert function call\n\t  __asan_load*/__asan_store*. These functions performs check\n\t  of shadow memory. This is slower than inline instrumentation,\n\t  however it doesn't bloat size of kernel's .text section so\n\t  much as inline does.\n\nconfig KERNEL_KASAN_INLINE\n\tbool \"Inline instrumentation\"\n\thelp\n\t  Compiler directly inserts code checking shadow memory before\n\t  memory accesses. This is faster than outline (in some workloads\n\t  it gives about x2 boost over outline instrumentation), but\n\t  make kernel's .text size much bigger.\n\t  This requires a gcc version of 5.0 or later.\n\nendchoice\n\nconfig KERNEL_KCOV\n\tbool \"Compile the kernel with code coverage for fuzzing\"\n\tselect KERNEL_DEBUG_FS\n\thelp\n\t  KCOV exposes kernel code coverage information in a form suitable\n\t  for coverage-guided fuzzing (randomized testing).\n\n\t  If RANDOMIZE_BASE is enabled, PC values will not be stable across\n\t  different machines and across reboots. If you need stable PC values,\n\t  disable RANDOMIZE_BASE.\n\n\t  For more details, see Documentation/kcov.txt.\n\nconfig KERNEL_KCOV_ENABLE_COMPARISONS\n\tbool \"Enable comparison operands collection by KCOV\"\n\tdepends on KERNEL_KCOV\n\thelp\n\t  KCOV also exposes operands of every comparison in the instrumented\n\t  code along with operand sizes and PCs of the comparison instructions.\n\t  These operands can be used by fuzzing engines to improve the quality\n\t  of fuzzing coverage.\n\nconfig KERNEL_KCOV_INSTRUMENT_ALL\n\tbool \"Instrument all code by default\"\n\tdepends on KERNEL_KCOV\n\tdefault y if KERNEL_KCOV\n\thelp\n\t  If you are doing generic system call fuzzing (like e.g. syzkaller),\n\t  then you will want to instrument the whole kernel and you should\n\t  say y here. If you are doing more targeted fuzzing (like e.g.\n\t  filesystem fuzzing with AFL) then you will want to enable coverage\n\t  for more specific subsets of files, and should say n here.\n\nconfig KERNEL_TASKSTATS\n\tbool \"Compile the kernel with task resource/io statistics and accounting\"\n\tdefault n\n\thelp\n\t  Enable the collection and publishing of task/io statistics and\n\t  accounting.  Enable this option to enable i/o monitoring in system\n\t  monitors.\n\nif KERNEL_TASKSTATS\n\n\tconfig KERNEL_TASK_DELAY_ACCT\n\t\tdef_bool y\n\n\tconfig KERNEL_TASK_IO_ACCOUNTING\n\t\tdef_bool y\n\n\tconfig KERNEL_TASK_XACCT\n\t\tdef_bool y\n\nendif\n\nconfig KERNEL_KALLSYMS\n\tbool \"Compile the kernel with symbol table information\"\n\tdefault y if !SMALL_FLASH\n\thelp\n\t  This will give you more information in stack traces from kernel oopses.\n\nconfig KERNEL_FTRACE\n\tbool \"Compile the kernel with tracing support\"\n\tdepends on !TARGET_uml\n\tdefault n\n\nconfig KERNEL_FTRACE_SYSCALLS\n\tbool \"Trace system calls\"\n\tdepends on KERNEL_FTRACE\n\tdefault n\n\nconfig KERNEL_ENABLE_DEFAULT_TRACERS\n\tbool \"Trace process context switches and events\"\n\tdepends on KERNEL_FTRACE\n\tdefault n\n\nconfig KERNEL_FUNCTION_TRACER\n\tbool \"Function tracer\"\n\tdepends on KERNEL_FTRACE\n\tdefault n\n\nconfig KERNEL_FUNCTION_GRAPH_TRACER\n\tbool \"Function graph tracer\"\n\tdepends on KERNEL_FUNCTION_TRACER\n\tdefault n\n\nconfig KERNEL_DYNAMIC_FTRACE\n\tbool \"Enable/disable function tracing dynamically\"\n\tdepends on KERNEL_FUNCTION_TRACER\n\tdefault n\n\nconfig KERNEL_FUNCTION_PROFILER\n\tbool \"Function profiler\"\n\tdepends on KERNEL_FUNCTION_TRACER\n\tdefault n\n\nconfig KERNEL_IRQSOFF_TRACER\n\tbool \"Interrupts-off Latency Tracer\"\n\tdepends on KERNEL_FTRACE\n\thelp\n\t  This option measures the time spent in irqs-off critical\n\t  sections, with microsecond accuracy.\n\n\t  The default measurement method is a maximum search, which is\n\t  disabled by default and can be runtime (re-)started\n\t  via:\n\n\t      echo 0 > /sys/kernel/debug/tracing/tracing_max_latency\n\n\t  (Note that kernel size and overhead increase with this option\n\t  enabled. This option and the preempt-off timing option can be\n\t  used together or separately.)\n\nconfig KERNEL_PREEMPT_TRACER\n\tbool \"Preemption-off Latency Tracer\"\n\tdepends on KERNEL_FTRACE\n\thelp\n\t  This option measures the time spent in preemption-off critical\n\t  sections, with microsecond accuracy.\n\n\t  The default measurement method is a maximum search, which is\n\t  disabled by default and can be runtime (re-)started\n\t  via:\n\n\t      echo 0 > /sys/kernel/debug/tracing/tracing_max_latency\n\n\t  (Note that kernel size and overhead increase with this option\n\t  enabled. This option and the irqs-off timing option can be\n\t  used together or separately.)\n\nconfig KERNEL_HIST_TRIGGERS\n\tbool \"Histogram triggers\"\n\tdepends on KERNEL_FTRACE\n\thelp\n\t  Hist triggers allow one or more arbitrary trace event fields to be\n\t  aggregated into hash tables and dumped to stdout by reading a\n\t  debugfs/tracefs file. They're useful for gathering quick and dirty\n\t  (though precise) summaries of event activity as an initial guide for\n\t  further investigation using more advanced tools.\n\n\t  Inter-event tracing of quantities such as latencies is also\n\t  supported using hist triggers under this option.\n\nconfig KERNEL_DEBUG_KERNEL\n\tbool\n\tdefault n\n\nconfig KERNEL_DEBUG_INFO\n\tbool \"Compile the kernel with debug information\"\n\tdefault y if !SMALL_FLASH\n\tselect KERNEL_DEBUG_KERNEL\n\thelp\n\t  This will compile your kernel and modules with debug information.\n\nconfig KERNEL_DEBUG_LL_UART_NONE\n\tbool\n\tdefault n\n\tdepends on arm\n\nconfig KERNEL_DEBUG_LL\n\tbool\n\tdefault n\n\tdepends on arm\n\tselect KERNEL_DEBUG_LL_UART_NONE\n\thelp\n\t  ARM low level debugging.\n\nconfig KERNEL_DYNAMIC_DEBUG\n\tbool \"Compile the kernel with dynamic printk\"\n\tselect KERNEL_DEBUG_FS\n\tdefault n\n\thelp\n\t  Compiles debug level messages into the kernel, which would not\n\t  otherwise be available at runtime. These messages can then be\n\t  enabled/disabled based on various levels of scope - per source file,\n\t  function, module, format string, and line number. This mechanism\n\t  implicitly compiles in all pr_debug() and dev_dbg() calls, which\n\t  enlarges the kernel text size by about 2%.\n\nconfig KERNEL_EARLY_PRINTK\n\tbool \"Compile the kernel with early printk\"\n\tdefault y if TARGET_bcm53xx\n\tdefault n\n\tdepends on arm\n\tselect KERNEL_DEBUG_KERNEL\n\tselect KERNEL_DEBUG_LL if arm\n\thelp\n\t  Compile the kernel with early printk support.  This is only useful for\n\t  debugging purposes to send messages over the serial console in early boot.\n\t  Enable this to debug early boot problems.\n\nconfig KERNEL_KPROBES\n\tbool \"Compile the kernel with kprobes support\"\n\tdefault n\n\tselect KERNEL_FTRACE\n\tselect KERNEL_PERF_EVENTS\n\thelp\n\t  Compiles the kernel with KPROBES support, which allows you to trap\n\t  at almost any kernel address and execute a callback function.\n\t  register_kprobe() establishes a probepoint and specifies the\n\t  callback. Kprobes is useful for kernel debugging, non-intrusive\n\t  instrumentation and testing.\n\t  If in doubt, say \"N\".\n\nconfig KERNEL_KPROBE_EVENTS\n\tbool\n\tdefault y if KERNEL_KPROBES\n\nconfig KERNEL_BPF_KPROBE_OVERRIDE\n\tbool\n\tdepends on KERNEL_KPROBES\n\tdefault n\n\nconfig KERNEL_AIO\n\tbool \"Compile the kernel with asynchronous IO support\"\n\tdefault y if !SMALL_FLASH\n\nconfig KERNEL_IO_URING\n\tbool \"Compile the kernel with io_uring support\"\n\tdefault y if !SMALL_FLASH\n\nconfig KERNEL_FHANDLE\n\tbool \"Compile the kernel with support for fhandle syscalls\"\n\tdefault y if !SMALL_FLASH\n\nconfig KERNEL_FANOTIFY\n\tbool \"Compile the kernel with modern file notification support\"\n\tdefault y if !SMALL_FLASH\n\nconfig KERNEL_BLK_DEV_BSG\n\tbool \"Compile the kernel with SCSI generic v4 support for any block device\"\n\tdefault n\n\nconfig KERNEL_TRANSPARENT_HUGEPAGE\n\tbool\n\nchoice\n\tprompt \"Transparent Hugepage Support sysfs defaults\"\n\tdepends on KERNEL_TRANSPARENT_HUGEPAGE\n\tdefault KERNEL_TRANSPARENT_HUGEPAGE_ALWAYS\n\n\tconfig KERNEL_TRANSPARENT_HUGEPAGE_ALWAYS\n\t\tbool \"always\"\n\n\tconfig KERNEL_TRANSPARENT_HUGEPAGE_MADVISE\n\t\tbool \"madvise\"\nendchoice\n\nconfig KERNEL_HUGETLBFS\n\tbool\n\nconfig KERNEL_HUGETLB_PAGE\n\tbool \"Compile the kernel with HugeTLB support\"\n\tselect KERNEL_TRANSPARENT_HUGEPAGE\n\tselect KERNEL_HUGETLBFS\n\tdefault n\n\nconfig KERNEL_MAGIC_SYSRQ\n\tbool \"Compile the kernel with SysRq support\"\n\tdefault y\n\nconfig KERNEL_DEBUG_PINCTRL\n\tbool \"Compile the kernel with pinctrl debugging\"\n\tselect KERNEL_DEBUG_KERNEL\n\nconfig KERNEL_DEBUG_GPIO\n\tbool \"Compile the kernel with gpio debugging\"\n\tselect KERNEL_DEBUG_KERNEL\n\nconfig KERNEL_COREDUMP\n\tbool\n\nconfig KERNEL_ELF_CORE\n\tbool \"Enable process core dump support\"\n\tselect KERNEL_COREDUMP\n\tdefault y if !SMALL_FLASH\n\nconfig KERNEL_PROVE_LOCKING\n\tbool \"Enable kernel lock checking\"\n\tselect KERNEL_DEBUG_KERNEL\n\tdefault n\n\nconfig KERNEL_SOFTLOCKUP_DETECTOR\n\tbool \"Compile the kernel with detect Soft Lockups\"\n\tdepends on KERNEL_DEBUG_KERNEL\n\thelp\n\t  Say Y here to enable the kernel to act as a watchdog to detect\n\t  soft lockups.\n\n\t  Softlockups are bugs that cause the kernel to loop in kernel\n\t  mode for more than 20 seconds, without giving other tasks a\n\t  chance to run.  The current stack trace is displayed upon\n\t  detection and the system will stay locked up.\n\nconfig KERNEL_DETECT_HUNG_TASK\n\tbool \"Compile the kernel with detect Hung Tasks\"\n\tdepends on KERNEL_DEBUG_KERNEL\n\tdefault KERNEL_SOFTLOCKUP_DETECTOR\n\thelp\n\t  Say Y here to enable the kernel to detect \"hung tasks\",\n\t  which are bugs that cause the task to be stuck in\n\t  uninterruptible \"D\" state indefinitely.\n\n\t  When a hung task is detected, the kernel will print the\n\t  current stack trace (which you should report), but the\n\t  task will stay in uninterruptible state. If lockdep is\n\t  enabled then all held locks will also be reported. This\n\t  feature has negligible overhead.\n\nconfig KERNEL_WQ_WATCHDOG\n\tbool \"Compile the kernel with detect Workqueue Stalls\"\n\tdepends on KERNEL_DEBUG_KERNEL\n\thelp\n\t  Say Y here to enable stall detection on workqueues.  If a\n\t  worker pool doesn't make forward progress on a pending work\n\t  item for over a given amount of time, 30s by default, a\n\t  warning message is printed along with dump of workqueue\n\t  state.  This can be configured through kernel parameter\n\t  \"workqueue.watchdog_thresh\" and its sysfs counterpart.\n\nconfig KERNEL_DEBUG_ATOMIC_SLEEP\n\tbool \"Compile the kernel with sleep inside atomic section checking\"\n\tdepends on KERNEL_DEBUG_KERNEL\n\thelp\n\t  If you say Y here, various routines which may sleep will become very\n\t  noisy if they are called inside atomic sections: when a spinlock is\n\t  held, inside an rcu read side critical section, inside preempt disabled\n\t  sections, inside an interrupt, etc...\n\nconfig KERNEL_DEBUG_VM\n\tbool \"Compile the kernel with debug VM\"\n\tdepends on KERNEL_DEBUG_KERNEL\n\thelp\n\t  Enable this to turn on extended checks in the virtual-memory system\n          that may impact performance.\n\n\t  If unsure, say N.\n\nconfig KERNEL_PRINTK_TIME\n\tbool \"Enable printk timestamps\"\n\tdefault y\n\nconfig KERNEL_SLUB_DEBUG\n\tbool\n\nconfig KERNEL_SLUB_DEBUG_ON\n\tbool\n\nconfig KERNEL_SLABINFO\n\tselect KERNEL_SLUB_DEBUG\n\tselect KERNEL_SLUB_DEBUG_ON\n\tbool \"Enable /proc slab debug info\"\n\nconfig KERNEL_PROC_PAGE_MONITOR\n\tbool \"Enable /proc page monitoring\"\n\nconfig KERNEL_RELAY\n\tbool\n\nconfig KERNEL_KEXEC\n\tbool \"Enable kexec support\"\n\nconfig KERNEL_PROC_VMCORE\n\tbool\n\nconfig KERNEL_PROC_KCORE\n\tbool\n\nconfig KERNEL_CRASH_DUMP\n\tdepends on i386 || x86_64 || arm || armeb\n\tselect KERNEL_KEXEC\n\tselect KERNEL_PROC_VMCORE\n\tselect KERNEL_PROC_KCORE\n\tbool \"Enable support for kexec crashdump\"\n\tdefault y\n\nconfig USE_RFKILL\n\tbool \"Enable rfkill support\"\n\tdefault RFKILL_SUPPORT\n\nconfig USE_SPARSE\n\tbool \"Enable sparse check during kernel build\"\n\tdefault n\n\nconfig KERNEL_DEVTMPFS\n\tbool \"Compile the kernel with device tmpfs enabled\"\n\tdefault n\n\thelp\n\t  devtmpfs is a simple, kernel-managed /dev filesystem. The kernel creates\n\t  devices nodes for all registered devices to simplify boot, but leaves more\n\t  complex tasks to userspace (e.g. udev).\n\nif KERNEL_DEVTMPFS\n\n\tconfig KERNEL_DEVTMPFS_MOUNT\n\t\tbool \"Automatically mount devtmpfs after root filesystem is mounted\"\n\t\tdefault n\n\nendif\n\nconfig KERNEL_KEYS\n\tbool \"Enable kernel access key retention support\"\n\tdefault !SMALL_FLASH\n\nconfig KERNEL_PERSISTENT_KEYRINGS\n\tbool \"Enable kernel persistent keyrings\"\n\tdepends on KERNEL_KEYS\n\tdefault n\n\nconfig KERNEL_KEYS_REQUEST_CACHE\n\tbool \"Enable temporary caching of the last request_key() result\"\n\tdepends on KERNEL_KEYS\n\tdefault n\n\nconfig KERNEL_BIG_KEYS\n\tbool \"Enable large payload keys on kernel keyrings\"\n\tdepends on KERNEL_KEYS\n\tdefault n\n\n#\n# CGROUP support symbols\n#\n\nconfig KERNEL_CGROUPS\n\tbool \"Enable kernel cgroups\"\n\tdefault y if !SMALL_FLASH\n\nif KERNEL_CGROUPS\n\n\tconfig KERNEL_CGROUP_DEBUG\n\t\tbool \"Example debug cgroup subsystem\"\n\t\tdefault n\n\t\thelp\n\t\t  This option enables a simple cgroup subsystem that\n\t\t  exports useful debugging information about the cgroups\n\t\t  framework.\n\n\tconfig KERNEL_FREEZER\n\t\tbool\n\n\tconfig KERNEL_CGROUP_FREEZER\n\t\tbool \"legacy Freezer cgroup subsystem\"\n\t\tdefault n\n\t\tselect KERNEL_FREEZER\n\t\thelp\n\t\t  Provides a way to freeze and unfreeze all tasks in a\n\t\t  cgroup.\n\t\t  (legacy cgroup1-only controller, in cgroup2 freezer\n\t\t  is integrated in the Memory controller)\n\n\tconfig KERNEL_CGROUP_DEVICE\n\t\tbool \"legacy Device controller for cgroups\"\n\t\tdefault n\n\t\thelp\n\t\t  Provides a cgroup implementing whitelists for devices which\n\t\t  a process in the cgroup can mknod or open.\n\t\t  (legacy cgroup1-only controller)\n\n\tconfig KERNEL_CGROUP_HUGETLB\n\t\tbool \"HugeTLB controller\"\n\t\tdefault n\n\t\tselect KERNEL_HUGETLB_PAGE\n\n\tconfig KERNEL_CGROUP_PIDS\n\t\tbool \"PIDs cgroup subsystem\"\n\t\tdefault y\n\t\thelp\n\t\t  Provides enforcement of process number limits in the scope of a\n\t\t  cgroup.\n\n\tconfig KERNEL_CGROUP_RDMA\n\t\tbool \"RDMA controller for cgroups\"\n\t\tdefault y\n\n\tconfig KERNEL_CGROUP_BPF\n\t\tbool \"Support for eBPF programs attached to cgroups\"\n\t\tdefault y\n\n\tconfig KERNEL_CPUSETS\n\t\tbool \"Cpuset support\"\n\t\tdefault y\n\t\thelp\n\t\t  This option will let you create and manage CPUSETs which\n\t\t  allow dynamically partitioning a system into sets of CPUs and\n\t\t  Memory Nodes and assigning tasks to run only within those sets.\n\t\t  This is primarily useful on large SMP or NUMA systems.\n\n\tconfig KERNEL_PROC_PID_CPUSET\n\t\tbool \"Include legacy /proc/<pid>/cpuset file\"\n\t\tdefault n\n\t\tdepends on KERNEL_CPUSETS\n\n\tconfig KERNEL_CGROUP_CPUACCT\n\t\tbool \"Simple CPU accounting cgroup subsystem\"\n\t\tdefault y\n\t\thelp\n\t\t  Provides a simple Resource Controller for monitoring the\n\t\t  total CPU consumed by the tasks in a cgroup.\n\n\tconfig KERNEL_RESOURCE_COUNTERS\n\t\tbool \"Resource counters\"\n\t\tdefault y\n\t\thelp\n\t\t  This option enables controller independent resource accounting\n\t\t  infrastructure that works with cgroups.\n\n\tconfig KERNEL_MM_OWNER\n\t\tbool\n\t\tdefault y if KERNEL_MEMCG\n\n\tconfig KERNEL_MEMCG\n\t\tbool \"Memory Resource Controller for Control Groups\"\n\t\tdefault y\n\t\tselect KERNEL_FREEZER\n\t\tdepends on KERNEL_RESOURCE_COUNTERS || !LINUX_3_18\n\t\thelp\n\t\t  Provides a memory resource controller that manages both anonymous\n\t\t  memory and page cache. (See Documentation/cgroups/memory.txt)\n\n\t\t  Note that setting this option increases fixed memory overhead\n\t\t  associated with each page of memory in the system. By this,\n\t\t  20(40)bytes/PAGE_SIZE on 32(64)bit system will be occupied by memory\n\t\t  usage tracking struct at boot. Total amount of this is printed out\n\t\t  at boot.\n\n\t\t  Only enable when you're ok with these tradeoffs and really\n\t\t  sure you need the memory resource controller. Even when you enable\n\t\t  this, you can set \"cgroup_disable=memory\" at your boot option to\n\t\t  disable memory resource controller and you can avoid overheads\n\t\t  (but lose benefits of memory resource controller).\n\n\t\t  This config option also selects MM_OWNER config option, which\n\t\t  could in turn add some fork/exit overhead.\n\n\tconfig KERNEL_MEMCG_SWAP\n\t\tbool \"Memory Resource Controller Swap Extension\"\n\t\tdefault y\n\t\tdepends on KERNEL_MEMCG\n\t\thelp\n\t\t  Add swap management feature to memory resource controller. When you\n\t\t  enable this, you can limit mem+swap usage per cgroup. In other words,\n\t\t  when you disable this, memory resource controller has no cares to\n\t\t  usage of swap...a process can exhaust all of the swap. This extension\n\t\t  is useful when you want to avoid exhaustion swap but this itself\n\t\t  adds more overheads and consumes memory for remembering information.\n\t\t  Especially if you use 32bit system or small memory system, please\n\t\t  be careful about enabling this. When memory resource controller\n\t\t  is disabled by boot option, this will be automatically disabled and\n\t\t  there will be no overhead from this. Even when you set this config=y,\n\t\t  if boot option \"swapaccount=0\" is set, swap will not be accounted.\n\t\t  Now, memory usage of swap_cgroup is 2 bytes per entry. If swap page\n\t\t  size is 4096bytes, 512k per 1Gbytes of swap.\n\n\tconfig KERNEL_MEMCG_SWAP_ENABLED\n\t\tbool \"Memory Resource Controller Swap Extension enabled by default\"\n\t\tdefault n\n\t\tdepends on KERNEL_MEMCG_SWAP\n\t\thelp\n\t\t  Memory Resource Controller Swap Extension comes with its price in\n\t\t  a bigger memory consumption. General purpose distribution kernels\n\t\t  which want to enable the feature but keep it disabled by default\n\t\t  and let the user enable it by swapaccount boot command line\n\t\t  parameter should have this option unselected.\n\n\t\t  Those who want to have the feature enabled by default should\n\t\t  select this option (if, for some reason, they need to disable it,\n\t\t  then swapaccount=0 does the trick).\n\n\n\tconfig KERNEL_MEMCG_KMEM\n\t\tbool \"Memory Resource Controller Kernel Memory accounting (EXPERIMENTAL)\"\n\t\tdefault y\n\t\tdepends on KERNEL_MEMCG\n\t\thelp\n\t\t  The Kernel Memory extension for Memory Resource Controller can limit\n\t\t  the amount of memory used by kernel objects in the system. Those are\n\t\t  fundamentally different from the entities handled by the standard\n\t\t  Memory Controller, which are page-based, and can be swapped. Users of\n\t\t  the kmem extension can use it to guarantee that no group of processes\n\t\t  will ever exhaust kernel resources alone.\n\n\tconfig KERNEL_CGROUP_PERF\n\t\tbool \"Enable perf_event per-cpu per-container group (cgroup) monitoring\"\n\t\tselect KERNEL_PERF_EVENTS\n\t\tdefault n\n\t\thelp\n\t\t  This option extends the per-cpu mode to restrict monitoring to\n\t\t  threads which belong to the cgroup specified and run on the\n\t\t  designated cpu.\n\n\tmenuconfig KERNEL_CGROUP_SCHED\n\t\tbool \"Group CPU scheduler\"\n\t\tdefault y\n\t\thelp\n\t\t  This feature lets CPU scheduler recognize task groups and control CPU\n\t\t  bandwidth allocation to such task groups. It uses cgroups to group\n\t\t  tasks.\n\n\tif KERNEL_CGROUP_SCHED\n\n\t\tconfig KERNEL_FAIR_GROUP_SCHED\n\t\t\tbool \"Group scheduling for SCHED_OTHER\"\n\t\t\tdefault y\n\n\t\tconfig KERNEL_CFS_BANDWIDTH\n\t\t\tbool \"CPU bandwidth provisioning for FAIR_GROUP_SCHED\"\n\t\t\tdefault y\n\t\t\tdepends on KERNEL_FAIR_GROUP_SCHED\n\t\t\thelp\n\t\t\t  This option allows users to define CPU bandwidth rates (limits) for\n\t\t\t  tasks running within the fair group scheduler.  Groups with no limit\n\t\t\t  set are considered to be unconstrained and will run with no\n\t\t\t  restriction.\n\t\t\t  See tip/Documentation/scheduler/sched-bwc.txt for more information.\n\n\t\tconfig KERNEL_RT_GROUP_SCHED\n\t\t\tbool \"Group scheduling for SCHED_RR/FIFO\"\n\t\t\tdefault y\n\t\t\thelp\n\t\t\t  This feature lets you explicitly allocate real CPU bandwidth\n\t\t\t  to task groups. If enabled, it will also make it impossible to\n\t\t\t  schedule realtime tasks for non-root users until you allocate\n\t\t\t  realtime bandwidth for them.\n\n\tendif\n\n\tconfig KERNEL_BLK_CGROUP\n\t\tbool \"Block IO controller\"\n\t\tdefault y\n\t\thelp\n\t\t  Generic block IO controller cgroup interface. This is the common\n\t\t  cgroup interface which should be used by various IO controlling\n\t\t  policies.\n\n\t\t  Currently, CFQ IO scheduler uses it to recognize task groups and\n\t\t  control disk bandwidth allocation (proportional time slice allocation)\n\t\t  to such task groups. It is also used by bio throttling logic in\n\t\t  block layer to implement upper limit in IO rates on a device.\n\n\t\t  This option only enables generic Block IO controller infrastructure.\n\t\t  One needs to also enable actual IO controlling logic/policy. For\n\t\t  enabling proportional weight division of disk bandwidth in CFQ, set\n\t\t  CONFIG_CFQ_GROUP_IOSCHED=y; for enabling throttling policy, set\n\t\t  CONFIG_BLK_DEV_THROTTLING=y.\n\n\tif KERNEL_BLK_CGROUP\n\n\t\tconfig KERNEL_CFQ_GROUP_IOSCHED\n\t\t\tbool \"Proportional weight of disk bandwidth in CFQ\"\n\n\t\tconfig KERNEL_BLK_DEV_THROTTLING\n\t\t\tbool \"Enable throttling policy\"\n\t\t\tdefault y\n\n\t\tconfig KERNEL_BLK_DEV_THROTTLING_LOW\n\t\t\tbool \"Block throttling .low limit interface support (EXPERIMENTAL)\"\n\t\t\tdepends on KERNEL_BLK_DEV_THROTTLING\n\tendif\n\n\tconfig KERNEL_DEBUG_BLK_CGROUP\n\t\tbool \"Enable Block IO controller debugging\"\n\t\tdefault n\n\t\tdepends on KERNEL_BLK_CGROUP\n\t\thelp\n\t\t  Enable some debugging help. Currently it exports additional stat\n\t\t  files in a cgroup which can be useful for debugging.\n\n\tconfig KERNEL_NET_CLS_CGROUP\n\t\tbool \"legacy Control Group Classifier\"\n\t\tdefault n\n\n\tconfig KERNEL_CGROUP_NET_CLASSID\n\t\tbool \"legacy Network classid cgroup\"\n\t\tdefault n\n\n\tconfig KERNEL_CGROUP_NET_PRIO\n\t\tbool \"legacy Network priority cgroup\"\n\t\tdefault n\n\nendif\n\n#\n# Namespace support symbols\n#\n\nconfig KERNEL_NAMESPACES\n\tbool \"Enable kernel namespaces\"\n\tdefault y if !SMALL_FLASH\n\nif KERNEL_NAMESPACES\n\n\tconfig KERNEL_UTS_NS\n\t\tbool \"UTS namespace\"\n\t\tdefault y\n\t\thelp\n\t\t  In this namespace, tasks see different info provided\n\t\t  with the uname() system call.\n\n\tconfig KERNEL_IPC_NS\n\t\tbool \"IPC namespace\"\n\t\tdefault y\n\t\thelp\n\t\t  In this namespace, tasks work with IPC ids which correspond to\n\t\t  different IPC objects in different namespaces.\n\n\tconfig KERNEL_USER_NS\n\t\tbool \"User namespace (EXPERIMENTAL)\"\n\t\tdefault y\n\t\thelp\n\t\t  This allows containers, i.e. vservers, to use user namespaces\n\t\t  to provide different user info for different servers.\n\n\tconfig KERNEL_PID_NS\n\t\tbool \"PID Namespaces\"\n\t\tdefault y\n\t\thelp\n\t\t  Support process id namespaces. This allows having multiple\n\t\t  processes with the same pid as long as they are in different\n\t\t  pid namespaces. This is a building block of containers.\n\n\tconfig KERNEL_NET_NS\n\t\tbool \"Network namespace\"\n\t\tdefault y\n\t\thelp\n\t\t  Allow user space to create what appear to be multiple instances\n\t\t  of the network stack.\n\nendif\n\nconfig KERNEL_DEVPTS_MULTIPLE_INSTANCES\n\tbool \"Support multiple instances of devpts\"\n\tdefault y if !SMALL_FLASH\n\thelp\n\t  Enable support for multiple instances of devpts filesystem.\n\t  If you want to have isolated PTY namespaces (eg: in containers),\n\t  say Y here. Otherwise, say N. If enabled, each mount of devpts\n\t  filesystem with the '-o newinstance' option will create an\n\t  independent PTY namespace.\n\nconfig KERNEL_POSIX_MQUEUE\n\tbool \"POSIX Message Queues\"\n\tdefault y if !SMALL_FLASH\n\thelp\n\t  POSIX variant of message queues is a part of IPC. In POSIX message\n\t  queues every message has a priority which decides about succession\n\t  of receiving it by a process. If you want to compile and run\n\t  programs written e.g. for Solaris with use of its POSIX message\n\t  queues (functions mq_*) say Y here.\n\n\t  POSIX message queues are visible as a filesystem called 'mqueue'\n\t  and can be mounted somewhere if you want to do filesystem\n\t  operations on message queues.\n\n\nconfig KERNEL_SECCOMP_FILTER\n\tbool\n\tdefault y if !SMALL_FLASH\n\nconfig KERNEL_SECCOMP\n\tbool \"Enable seccomp support\"\n\t\tdepends on !(TARGET_uml)\n\t\tselect KERNEL_SECCOMP_FILTER\n\t\tdefault y if !SMALL_FLASH\n\t\thelp\n\t\t  Build kernel with support for seccomp.\n\n#\n# IPv4 configuration\n#\n\nconfig KERNEL_IP_MROUTE\n\tbool \"Enable IPv4 multicast routing\"\n\tdefault y\n\thelp\n\t  Multicast routing requires a multicast routing daemon in\n\t  addition to kernel support.\n\nif KERNEL_IP_MROUTE\n\n\tconfig KERNEL_IP_MROUTE_MULTIPLE_TABLES\n\t\tdef_bool y\n\n\tconfig KERNEL_IP_PIMSM_V1\n\t\tdef_bool y\n\n\tconfig KERNEL_IP_PIMSM_V2\n\t\tdef_bool y\n\nendif\n\n#\n# IPv6 configuration\n#\n\nconfig KERNEL_IPV6\n\tdef_bool IPV6\n\nif KERNEL_IPV6\n\n\tconfig KERNEL_IPV6_MULTIPLE_TABLES\n\t\tdef_bool y\n\n\tconfig KERNEL_IPV6_SUBTREES\n\t\tdef_bool y\n\n\tconfig KERNEL_IPV6_MROUTE\n\t\tbool \"Enable IPv6 multicast routing\"\n\t\tdefault y\n\t\thelp\n\t\t  Multicast routing requires a multicast routing daemon in\n\t\t  addition to kernel support.\n\n\tif KERNEL_IPV6_MROUTE\n\n\t\tconfig KERNEL_IPV6_MROUTE_MULTIPLE_TABLES\n\t\t\tdef_bool y\n\n\t\tconfig KERNEL_IPV6_PIMSM_V2\n\t\t\tdef_bool y\n\n\tendif\n\n\tconfig KERNEL_IPV6_SEG6_LWTUNNEL\n\t\tbool \"Enable support for lightweight tunnels\"\n\t\tdefault y if !SMALL_FLASH\n\t\thelp\n\t\t  Using lwtunnel (needed for IPv6 segment routing) requires ip-full package.\n\n\tconfig KERNEL_LWTUNNEL_BPF\n\t\tdef_bool n\n\nendif\n\n#\n# Miscellaneous network configuration\n#\n\nconfig KERNEL_NET_L3_MASTER_DEV\n\tbool \"L3 Master device support\"\n\thelp\n\t  This module provides glue between core networking code and device\n\t  drivers to support L3 master devices like VRF.\n\n#\n# NFS related symbols\n#\nconfig KERNEL_IP_PNP\n\tbool \"Compile the kernel with rootfs on NFS\"\n\thelp\n\t   If you want to make your kernel boot off a NFS server as root\n\t   filesystem, select Y here.\n\nif KERNEL_IP_PNP\n\n\tconfig KERNEL_IP_PNP_DHCP\n\t\tdef_bool y\n\n\tconfig KERNEL_IP_PNP_BOOTP\n\t\tdef_bool n\n\n\tconfig KERNEL_IP_PNP_RARP\n\t\tdef_bool n\n\n\tconfig KERNEL_NFS_FS\n\t\tdef_bool y\n\n\tconfig KERNEL_NFS_V2\n\t\tdef_bool y\n\n\tconfig KERNEL_NFS_V3\n\t\tdef_bool y\n\n\tconfig KERNEL_ROOT_NFS\n\t\tdef_bool y\n\nendif\n\nmenu \"Filesystem ACL and attr support options\"\n\tconfig USE_FS_ACL_ATTR\n\t\tbool \"Use filesystem ACL and attr support by default\"\n\t\tdefault n\n\t\thelp\n\t\t  Make using ACLs (e.g. POSIX ACL, NFSv4 ACL) the default\n\t\t  for kernel and packages, except tmpfs, flash filesystems,\n\t\t  and old NFS.  Also enable userspace extended attribute support\n\t\t  by default.  (OpenWrt already has an expection it will be\n\t\t  present in the kernel).\n\n\tconfig KERNEL_FS_POSIX_ACL\n\t\tbool \"Enable POSIX ACL support\"\n\t\tdefault y if USE_FS_ACL_ATTR\n\n\tconfig KERNEL_BTRFS_FS_POSIX_ACL\n\t\tbool \"Enable POSIX ACL for BtrFS Filesystems\"\n\t\tselect KERNEL_FS_POSIX_ACL\n\t\tdefault y if USE_FS_ACL_ATTR\n\n\tconfig KERNEL_EXT4_FS_POSIX_ACL\n\t\tbool \"Enable POSIX ACL for Ext4 Filesystems\"\n\t\tselect KERNEL_FS_POSIX_ACL\n\t\tdefault y if USE_FS_ACL_ATTR\n\n\tconfig KERNEL_F2FS_FS_POSIX_ACL\n\t\tbool \"Enable POSIX ACL for F2FS Filesystems\"\n\t\tselect KERNEL_FS_POSIX_ACL\n\t\tdefault n\n\n\tconfig KERNEL_JFFS2_FS_POSIX_ACL\n\t\tbool \"Enable POSIX ACL for JFFS2 Filesystems\"\n\t\tselect KERNEL_FS_POSIX_ACL\n\t\tdefault n\n\n\tconfig KERNEL_TMPFS_POSIX_ACL\n\t\tbool \"Enable POSIX ACL for TMPFS Filesystems\"\n\t\tselect KERNEL_FS_POSIX_ACL\n\t\tdefault n\n\n\tconfig KERNEL_CIFS_ACL\n\t\tbool \"Enable CIFS ACLs\"\n\t\tselect KERNEL_FS_POSIX_ACL\n\t\tdefault y if USE_FS_ACL_ATTR\n\n\tconfig KERNEL_HFS_FS_POSIX_ACL\n\t\tbool \"Enable POSIX ACL for HFS Filesystems\"\n\t\tselect KERNEL_FS_POSIX_ACL\n\t\tdefault y if USE_FS_ACL_ATTR\n\n\tconfig KERNEL_HFSPLUS_FS_POSIX_ACL\n\t\tbool \"Enable POSIX ACL for HFS+ Filesystems\"\n\t\tselect KERNEL_FS_POSIX_ACL\n\t\tdefault y if USE_FS_ACL_ATTR\n\n\tconfig KERNEL_NFS_ACL_SUPPORT\n\t\tbool \"Enable ACLs for NFS\"\n\t\tdefault y if USE_FS_ACL_ATTR\n\n\tconfig KERNEL_NFS_V3_ACL_SUPPORT\n\t\tbool \"Enable ACLs for NFSv3\"\n\t\tdefault n\n\n\tconfig KERNEL_NFSD_V2_ACL_SUPPORT\n\t\tbool \"Enable ACLs for NFSDv2\"\n\t\tdefault n\n\n\tconfig KERNEL_NFSD_V3_ACL_SUPPORT\n\t\tbool \"Enable ACLs for NFSDv3\"\n\t\tdefault n\n\n\tconfig KERNEL_REISER_FS_POSIX_ACL\n\t\tbool \"Enable POSIX ACLs for ReiserFS\"\n\t\tselect KERNEL_FS_POSIX_ACL\n\t\tdefault y if USE_FS_ACL_ATTR\n\n\tconfig KERNEL_XFS_POSIX_ACL\n\t\tbool \"Enable POSIX ACLs for XFS\"\n\t\tselect KERNEL_FS_POSIX_ACL\n\t\tdefault y if USE_FS_ACL_ATTR\n\n\tconfig KERNEL_JFS_POSIX_ACL\n\t\tbool \"Enable POSIX ACLs for JFS\"\n\t\tselect KERNEL_FS_POSIX_ACL\n\t\tdefault y if USE_FS_ACL_ATTR\n\nendmenu\n\nconfig KERNEL_DEVMEM\n\tbool \"/dev/mem virtual device support\"\n\thelp\n\t  Say Y here if you want to support the /dev/mem device.\n\t  The /dev/mem device is used to access areas of physical\n\t  memory.\n\nconfig KERNEL_DEVKMEM\n\tbool \"/dev/kmem virtual device support\"\n\thelp\n\t  Say Y here if you want to support the /dev/kmem device. The\n\t  /dev/kmem device is rarely used, but can be used for certain\n\t  kind of kernel debugging operations.\n\nconfig KERNEL_SQUASHFS_FRAGMENT_CACHE_SIZE\n\tint \"Number of squashfs fragments cached\"\n\tdefault 2 if (SMALL_FLASH && !LOW_MEMORY_FOOTPRINT)\n\tdefault 3\n\nconfig KERNEL_SQUASHFS_XATTR\n\tbool \"Squashfs XATTR support\"\n\n#\n# compile optimization setting\n#\nchoice\n\tprompt \"Compiler optimization level\"\n\tdefault KERNEL_CC_OPTIMIZE_FOR_SIZE if SMALL_FLASH\n\nconfig KERNEL_CC_OPTIMIZE_FOR_PERFORMANCE\n\tbool \"Optimize for performance\"\n\thelp\n\t  This is the default optimization level for the kernel, building\n\t  with the \"-O2\" compiler flag for best performance and most\n\t  helpful compile-time warnings.\n\nconfig KERNEL_CC_OPTIMIZE_FOR_SIZE\n\tbool \"Optimize for size\"\n\thelp\n\t  Enabling this option will pass \"-Os\" instead of \"-O2\" to\n\t  your compiler resulting in a smaller kernel.\n\nendchoice\n\nconfig KERNEL_AUDIT\n\tbool \"Auditing support\"\n\nconfig KERNEL_SECURITY\n\tbool \"Enable different security models\"\n\nconfig KERNEL_SECURITY_NETWORK\n\tbool \"Socket and Networking Security Hooks\"\n\tselect KERNEL_SECURITY\n\nconfig KERNEL_SECURITY_SELINUX\n\tbool \"NSA SELinux Support\"\n\tselect KERNEL_SECURITY_NETWORK\n\tselect KERNEL_AUDIT\n\nconfig KERNEL_SECURITY_SELINUX_BOOTPARAM\n\tbool \"NSA SELinux boot parameter\"\n\tdepends on KERNEL_SECURITY_SELINUX\n\tdefault y\n\nconfig KERNEL_SECURITY_SELINUX_DISABLE\n\tbool \"NSA SELinux runtime disable\"\n\tdepends on KERNEL_SECURITY_SELINUX\n\nconfig KERNEL_SECURITY_SELINUX_DEVELOP\n\tbool \"NSA SELinux Development Support\"\n\tdepends on KERNEL_SECURITY_SELINUX\n\tdefault y\n\nconfig KERNEL_SECURITY_SELINUX_SIDTAB_HASH_BITS\n\tint\n\tdepends on KERNEL_SECURITY_SELINUX\n\tdefault 9\n\nconfig KERNEL_SECURITY_SELINUX_SID2STR_CACHE_SIZE\n\tint\n\tdepends on KERNEL_SECURITY_SELINUX\n\tdefault 256\n\nconfig KERNEL_LSM\n\tstring\n\tdefault \"lockdown,yama,loadpin,safesetid,integrity,selinux\"\n\tdepends on KERNEL_SECURITY_SELINUX\n\nconfig KERNEL_EXT4_FS_SECURITY\n\tbool \"Ext4 Security Labels\"\n\nconfig KERNEL_F2FS_FS_SECURITY\n\tbool \"F2FS Security Labels\"\n\nconfig KERNEL_UBIFS_FS_SECURITY\n\tbool \"UBIFS Security Labels\"\n\nconfig KERNEL_JFFS2_FS_SECURITY\n\tbool \"JFFS2 Security Labels\"\n"
  },
  {
    "path": "config/check-uname.sh",
    "content": "[ \"$(uname)\" = \"$1\" ] && echo y || echo n\n"
  },
  {
    "path": "configs/OrangePi_R1_Plus_LTS_defconfig",
    "content": "#\n# Automatically generated file; DO NOT EDIT.\n# OpenWrt Configuration\n#\nCONFIG_MODULES=y\nCONFIG_HAVE_DOT_CONFIG=y\nCONFIG_HOST_OS_LINUX=y\n# CONFIG_HOST_OS_MACOS is not set\n# CONFIG_TARGET_sunxi is not set\n# CONFIG_TARGET_apm821xx is not set\n# CONFIG_TARGET_ath25 is not set\n# CONFIG_TARGET_ath79 is not set\n# CONFIG_TARGET_bcm27xx is not set\n# CONFIG_TARGET_bcm53xx is not set\n# CONFIG_TARGET_bcm47xx is not set\n# CONFIG_TARGET_bcm4908 is not set\n# CONFIG_TARGET_bcm63xx is not set\n# CONFIG_TARGET_bmips is not set\n# CONFIG_TARGET_octeon is not set\n# CONFIG_TARGET_gemini is not set\n# CONFIG_TARGET_mpc85xx is not set\n# CONFIG_TARGET_mxs is not set\n# CONFIG_TARGET_lantiq is not set\n# CONFIG_TARGET_malta is not set\n# CONFIG_TARGET_pistachio is not set\n# CONFIG_TARGET_mvebu is not set\n# CONFIG_TARGET_kirkwood is not set\n# CONFIG_TARGET_mediatek is not set\n# CONFIG_TARGET_ramips is not set\n# CONFIG_TARGET_at91 is not set\n# CONFIG_TARGET_tegra is not set\n# CONFIG_TARGET_layerscape is not set\n# CONFIG_TARGET_imx is not set\n# CONFIG_TARGET_octeontx is not set\n# CONFIG_TARGET_oxnas is not set\n# CONFIG_TARGET_armvirt is not set\n# CONFIG_TARGET_ipq40xx is not set\n# CONFIG_TARGET_ipq806x is not set\n# CONFIG_TARGET_ipq807x is not set\n# CONFIG_TARGET_realtek is not set\nCONFIG_TARGET_rockchip=y\n# CONFIG_TARGET_arc770 is not set\n# CONFIG_TARGET_archs38 is not set\n# CONFIG_TARGET_omap is not set\n# CONFIG_TARGET_uml is not set\n# CONFIG_TARGET_zynq is not set\n# CONFIG_TARGET_x86 is not set\nCONFIG_TARGET_rockchip_armv8=y\n# CONFIG_TARGET_MULTI_PROFILE is not set\n# CONFIG_TARGET_rockchip_armv8_DEVICE_xunlong_orangepi-r1-plus is not set\nCONFIG_TARGET_rockchip_armv8_DEVICE_xunlong_orangepi-r1-plus-lts=y\n# CONFIG_TARGET_rockchip_armv8_DEVICE_friendlyarm_nanopi-r2s is not set\n# CONFIG_TARGET_rockchip_armv8_DEVICE_friendlyarm_nanopi-r4s is not set\n# CONFIG_TARGET_rockchip_armv8_DEVICE_pine64_rockpro64 is not set\n# CONFIG_TARGET_rockchip_armv8_DEVICE_radxa_rock-pi-4a is not set\nCONFIG_HAS_SUBTARGETS=y\nCONFIG_HAS_DEVICES=y\nCONFIG_TARGET_BOARD=\"rockchip\"\nCONFIG_TARGET_SUBTARGET=\"armv8\"\nCONFIG_TARGET_PROFILE=\"DEVICE_xunlong_orangepi-r1-plus-lts\"\nCONFIG_TARGET_ARCH_PACKAGES=\"aarch64_generic\"\nCONFIG_DEFAULT_TARGET_OPTIMIZATION=\"-Os -pipe -mcpu=generic\"\nCONFIG_CPU_TYPE=\"generic\"\nCONFIG_LINUX_5_10=y\nCONFIG_DEFAULT_base-files=y\nCONFIG_DEFAULT_busybox=y\nCONFIG_DEFAULT_ca-bundle=y\nCONFIG_DEFAULT_dnsmasq=y\nCONFIG_DEFAULT_dropbear=y\nCONFIG_DEFAULT_e2fsprogs=y\nCONFIG_DEFAULT_firewall=y\nCONFIG_DEFAULT_fstools=y\nCONFIG_DEFAULT_ip6tables=y\nCONFIG_DEFAULT_iptables=y\nCONFIG_DEFAULT_kmod-gpio-button-hotplug=y\nCONFIG_DEFAULT_kmod-ipt-offload=y\nCONFIG_DEFAULT_kmod-usb-net-rtl8152=y\nCONFIG_DEFAULT_libc=y\nCONFIG_DEFAULT_libgcc=y\nCONFIG_DEFAULT_libustream-wolfssl=y\nCONFIG_DEFAULT_logd=y\nCONFIG_DEFAULT_mkf2fs=y\nCONFIG_DEFAULT_mtd=y\nCONFIG_DEFAULT_netifd=y\nCONFIG_DEFAULT_odhcp6c=y\nCONFIG_DEFAULT_odhcpd-ipv6only=y\nCONFIG_DEFAULT_opkg=y\nCONFIG_DEFAULT_partx-utils=y\nCONFIG_DEFAULT_ppp=y\nCONFIG_DEFAULT_ppp-mod-pppoe=y\nCONFIG_DEFAULT_procd=y\nCONFIG_DEFAULT_procd-ujail=y\nCONFIG_DEFAULT_uboot-envtools=y\nCONFIG_DEFAULT_uci=y\nCONFIG_DEFAULT_uclient-fetch=y\nCONFIG_DEFAULT_urandom-seed=y\nCONFIG_DEFAULT_urngd=y\nCONFIG_HAS_FPU=y\nCONFIG_AUDIO_SUPPORT=y\nCONFIG_GPIO_SUPPORT=y\nCONFIG_PCI_SUPPORT=y\nCONFIG_PCIE_SUPPORT=y\nCONFIG_USB_SUPPORT=y\nCONFIG_USB_GADGET_SUPPORT=y\nCONFIG_RTC_SUPPORT=y\nCONFIG_USES_DEVICETREE=y\nCONFIG_USES_SQUASHFS=y\nCONFIG_USES_EXT4=y\nCONFIG_ARCH_64BIT=y\nCONFIG_USES_ROOTFS_PART=y\nCONFIG_USES_BOOT_PART=y\nCONFIG_aarch64=y\nCONFIG_ARCH=\"aarch64\"\n\n#\n# Target Images\n#\n# CONFIG_TARGET_ROOTFS_INITRAMFS is not set\nCONFIG_EXTERNAL_CPIO=\"\"\n\n#\n# Root filesystem archives\n#\n# CONFIG_TARGET_ROOTFS_CPIOGZ is not set\n# CONFIG_TARGET_ROOTFS_TARGZ is not set\n\n#\n# Root filesystem images\n#\nCONFIG_TARGET_ROOTFS_EXT4FS=y\nCONFIG_TARGET_EXT4_RESERVED_PCT=0\nCONFIG_TARGET_EXT4_BLOCKSIZE_4K=y\n# CONFIG_TARGET_EXT4_BLOCKSIZE_2K is not set\n# CONFIG_TARGET_EXT4_BLOCKSIZE_1K is not set\nCONFIG_TARGET_EXT4_BLOCKSIZE=4096\n# CONFIG_TARGET_EXT4_JOURNAL is not set\nCONFIG_TARGET_ROOTFS_SQUASHFS=y\nCONFIG_TARGET_SQUASHFS_BLOCK_SIZE=256\nCONFIG_TARGET_UBIFS_FREE_SPACE_FIXUP=y\nCONFIG_TARGET_UBIFS_JOURNAL_SIZE=\"\"\nCONFIG_TARGET_IMAGES_GZIP=y\n\n#\n# Image Options\n#\nCONFIG_TARGET_KERNEL_PARTSIZE=16\nCONFIG_TARGET_ROOTFS_PARTSIZE=512\n# CONFIG_TARGET_ROOTFS_PERSIST_VAR is not set\n# end of Target Images\n\n# CONFIG_EXPERIMENTAL is not set\n\n#\n# Global build settings\n#\n# CONFIG_JSON_OVERVIEW_IMAGE_INFO is not set\n# CONFIG_ALL_NONSHARED is not set\n# CONFIG_ALL_KMODS is not set\n# CONFIG_ALL is not set\n# CONFIG_BUILDBOT is not set\nCONFIG_SIGNED_PACKAGES=y\nCONFIG_SIGNATURE_CHECK=y\n\n#\n# General build options\n#\nCONFIG_DISPLAY_SUPPORT=y\n# CONFIG_BUILD_PATENTED is not set\n# CONFIG_BUILD_NLS is not set\nCONFIG_SHADOW_PASSWORDS=y\n# CONFIG_CLEAN_IPKG is not set\n# CONFIG_IPK_FILES_CHECKSUMS is not set\n# CONFIG_INCLUDE_CONFIG is not set\n# CONFIG_REPRODUCIBLE_DEBUG_INFO is not set\n# CONFIG_COLLECT_KERNEL_DEBUG is not set\n\n#\n# Kernel build options\n#\nCONFIG_KERNEL_BUILD_USER=\"\"\nCONFIG_KERNEL_BUILD_DOMAIN=\"\"\nCONFIG_KERNEL_PRINTK=y\nCONFIG_KERNEL_SWAP=y\n# CONFIG_KERNEL_PROC_STRIPPED is not set\nCONFIG_KERNEL_DEBUG_FS=y\n# CONFIG_KERNEL_ARM_PMU is not set\n# CONFIG_KERNEL_PERF_EVENTS is not set\n# CONFIG_KERNEL_PROFILING is not set\n# CONFIG_KERNEL_UBSAN is not set\n# CONFIG_KERNEL_KASAN is not set\n# CONFIG_KERNEL_KCOV is not set\n# CONFIG_KERNEL_TASKSTATS is not set\nCONFIG_KERNEL_KALLSYMS=y\n# CONFIG_KERNEL_FTRACE is not set\nCONFIG_KERNEL_DEBUG_KERNEL=y\nCONFIG_KERNEL_DEBUG_INFO=y\n# CONFIG_KERNEL_DYNAMIC_DEBUG is not set\n# CONFIG_KERNEL_KPROBES is not set\nCONFIG_KERNEL_AIO=y\nCONFIG_KERNEL_IO_URING=y\nCONFIG_KERNEL_FHANDLE=y\nCONFIG_KERNEL_FANOTIFY=y\n# CONFIG_KERNEL_BLK_DEV_BSG is not set\n# CONFIG_KERNEL_HUGETLB_PAGE is not set\nCONFIG_KERNEL_MAGIC_SYSRQ=y\n# CONFIG_KERNEL_DEBUG_PINCTRL is not set\n# CONFIG_KERNEL_DEBUG_GPIO is not set\nCONFIG_KERNEL_COREDUMP=y\nCONFIG_KERNEL_ELF_CORE=y\n# CONFIG_KERNEL_PROVE_LOCKING is not set\n# CONFIG_KERNEL_SOFTLOCKUP_DETECTOR is not set\n# CONFIG_KERNEL_DETECT_HUNG_TASK is not set\n# CONFIG_KERNEL_WQ_WATCHDOG is not set\n# CONFIG_KERNEL_DEBUG_ATOMIC_SLEEP is not set\n# CONFIG_KERNEL_DEBUG_VM is not set\nCONFIG_KERNEL_PRINTK_TIME=y\n# CONFIG_KERNEL_SLABINFO is not set\n# CONFIG_KERNEL_PROC_PAGE_MONITOR is not set\n# CONFIG_KERNEL_KEXEC is not set\n# CONFIG_USE_RFKILL is not set\n# CONFIG_USE_SPARSE is not set\n# CONFIG_KERNEL_DEVTMPFS is not set\nCONFIG_KERNEL_KEYS=y\n# CONFIG_KERNEL_PERSISTENT_KEYRINGS is not set\n# CONFIG_KERNEL_KEYS_REQUEST_CACHE is not set\n# CONFIG_KERNEL_BIG_KEYS is not set\nCONFIG_KERNEL_CGROUPS=y\n# CONFIG_KERNEL_CGROUP_DEBUG is not set\nCONFIG_KERNEL_FREEZER=y\nCONFIG_KERNEL_CGROUP_FREEZER=y\nCONFIG_KERNEL_CGROUP_DEVICE=y\n# CONFIG_KERNEL_CGROUP_HUGETLB is not set\nCONFIG_KERNEL_CGROUP_PIDS=y\nCONFIG_KERNEL_CGROUP_RDMA=y\nCONFIG_KERNEL_CGROUP_BPF=y\nCONFIG_KERNEL_CPUSETS=y\n# CONFIG_KERNEL_PROC_PID_CPUSET is not set\nCONFIG_KERNEL_CGROUP_CPUACCT=y\nCONFIG_KERNEL_RESOURCE_COUNTERS=y\nCONFIG_KERNEL_MM_OWNER=y\nCONFIG_KERNEL_MEMCG=y\nCONFIG_KERNEL_MEMCG_SWAP=y\n# CONFIG_KERNEL_MEMCG_SWAP_ENABLED is not set\nCONFIG_KERNEL_MEMCG_KMEM=y\n# CONFIG_KERNEL_CGROUP_PERF is not set\nCONFIG_KERNEL_CGROUP_SCHED=y\nCONFIG_KERNEL_FAIR_GROUP_SCHED=y\nCONFIG_KERNEL_CFS_BANDWIDTH=y\nCONFIG_KERNEL_RT_GROUP_SCHED=y\nCONFIG_KERNEL_BLK_CGROUP=y\n# CONFIG_KERNEL_CFQ_GROUP_IOSCHED is not set\nCONFIG_KERNEL_BLK_DEV_THROTTLING=y\n# CONFIG_KERNEL_BLK_DEV_THROTTLING_LOW is not set\n# CONFIG_KERNEL_DEBUG_BLK_CGROUP is not set\n# CONFIG_KERNEL_NET_CLS_CGROUP is not set\n# CONFIG_KERNEL_CGROUP_NET_CLASSID is not set\n# CONFIG_KERNEL_CGROUP_NET_PRIO is not set\nCONFIG_KERNEL_NAMESPACES=y\nCONFIG_KERNEL_UTS_NS=y\nCONFIG_KERNEL_IPC_NS=y\nCONFIG_KERNEL_USER_NS=y\nCONFIG_KERNEL_PID_NS=y\nCONFIG_KERNEL_NET_NS=y\nCONFIG_KERNEL_DEVPTS_MULTIPLE_INSTANCES=y\nCONFIG_KERNEL_POSIX_MQUEUE=y\nCONFIG_KERNEL_SECCOMP_FILTER=y\nCONFIG_KERNEL_SECCOMP=y\nCONFIG_KERNEL_IP_MROUTE=y\nCONFIG_KERNEL_IPV6=y\nCONFIG_KERNEL_IPV6_MULTIPLE_TABLES=y\nCONFIG_KERNEL_IPV6_SUBTREES=y\nCONFIG_KERNEL_IPV6_MROUTE=y\n# CONFIG_KERNEL_IPV6_PIMSM_V2 is not set\nCONFIG_KERNEL_IPV6_SEG6_LWTUNNEL=y\n# CONFIG_KERNEL_LWTUNNEL_BPF is not set\n# CONFIG_KERNEL_IP_PNP is not set\n\n#\n# Filesystem ACL and attr support options\n#\n# CONFIG_USE_FS_ACL_ATTR is not set\n# CONFIG_KERNEL_FS_POSIX_ACL is not set\n# CONFIG_KERNEL_BTRFS_FS_POSIX_ACL is not set\n# CONFIG_KERNEL_EXT4_FS_POSIX_ACL is not set\n# CONFIG_KERNEL_F2FS_FS_POSIX_ACL is not set\n# CONFIG_KERNEL_JFFS2_FS_POSIX_ACL is not set\n# CONFIG_KERNEL_TMPFS_POSIX_ACL is not set\n# CONFIG_KERNEL_CIFS_ACL is not set\n# CONFIG_KERNEL_HFS_FS_POSIX_ACL is not set\n# CONFIG_KERNEL_HFSPLUS_FS_POSIX_ACL is not set\n# CONFIG_KERNEL_NFS_ACL_SUPPORT is not set\n# CONFIG_KERNEL_NFS_V3_ACL_SUPPORT is not set\n# CONFIG_KERNEL_NFSD_V2_ACL_SUPPORT is not set\n# CONFIG_KERNEL_NFSD_V3_ACL_SUPPORT is not set\n# CONFIG_KERNEL_REISER_FS_POSIX_ACL is not set\n# CONFIG_KERNEL_XFS_POSIX_ACL is not set\n# CONFIG_KERNEL_JFS_POSIX_ACL is not set\n# end of Filesystem ACL and attr support options\n\n# CONFIG_KERNEL_DEVMEM is not set\n# CONFIG_KERNEL_DEVKMEM is not set\nCONFIG_KERNEL_SQUASHFS_FRAGMENT_CACHE_SIZE=3\n# CONFIG_KERNEL_SQUASHFS_XATTR is not set\nCONFIG_KERNEL_CC_OPTIMIZE_FOR_PERFORMANCE=y\n# CONFIG_KERNEL_CC_OPTIMIZE_FOR_SIZE is not set\n# CONFIG_KERNEL_AUDIT is not set\n# CONFIG_KERNEL_SECURITY is not set\n# CONFIG_KERNEL_SECURITY_NETWORK is not set\n# CONFIG_KERNEL_SECURITY_SELINUX is not set\n# CONFIG_KERNEL_EXT4_FS_SECURITY is not set\n# CONFIG_KERNEL_F2FS_FS_SECURITY is not set\n# CONFIG_KERNEL_UBIFS_FS_SECURITY is not set\n# CONFIG_KERNEL_JFFS2_FS_SECURITY is not set\n# end of Kernel build options\n\n#\n# Package build options\n#\n# CONFIG_DEBUG is not set\nCONFIG_IPV6=y\n\n#\n# Stripping options\n#\n# CONFIG_NO_STRIP is not set\n# CONFIG_USE_STRIP is not set\nCONFIG_USE_SSTRIP=y\nCONFIG_SSTRIP_ARGS=\"-z\"\n# CONFIG_STRIP_KERNEL_EXPORTS is not set\n# CONFIG_USE_MKLIBS is not set\n\n#\n# Hardening build options\n#\nCONFIG_PKG_CHECK_FORMAT_SECURITY=y\n# CONFIG_PKG_ASLR_PIE_NONE is not set\nCONFIG_PKG_ASLR_PIE_REGULAR=y\n# CONFIG_PKG_ASLR_PIE_ALL is not set\n# CONFIG_PKG_CC_STACKPROTECTOR_NONE is not set\nCONFIG_PKG_CC_STACKPROTECTOR_REGULAR=y\n# CONFIG_PKG_CC_STACKPROTECTOR_STRONG is not set\n# CONFIG_KERNEL_CC_STACKPROTECTOR_NONE is not set\nCONFIG_KERNEL_CC_STACKPROTECTOR_REGULAR=y\n# CONFIG_KERNEL_CC_STACKPROTECTOR_STRONG is not set\nCONFIG_KERNEL_STACKPROTECTOR=y\n# CONFIG_KERNEL_STACKPROTECTOR_STRONG is not set\n# CONFIG_PKG_FORTIFY_SOURCE_NONE is not set\nCONFIG_PKG_FORTIFY_SOURCE_1=y\n# CONFIG_PKG_FORTIFY_SOURCE_2 is not set\n# CONFIG_PKG_RELRO_NONE is not set\n# CONFIG_PKG_RELRO_PARTIAL is not set\nCONFIG_PKG_RELRO_FULL=y\n# CONFIG_SELINUX is not set\nCONFIG_SECCOMP=y\n# end of Global build settings\n\n# CONFIG_DEVEL is not set\n# CONFIG_BROKEN is not set\nCONFIG_BINARY_FOLDER=\"\"\nCONFIG_DOWNLOAD_FOLDER=\"\"\nCONFIG_LOCALMIRROR=\"\"\nCONFIG_AUTOREBUILD=y\n# CONFIG_AUTOREMOVE is not set\nCONFIG_BUILD_SUFFIX=\"\"\nCONFIG_TARGET_ROOTFS_DIR=\"\"\n# CONFIG_CCACHE is not set\nCONFIG_CCACHE_DIR=\"\"\nCONFIG_EXTERNAL_KERNEL_TREE=\"\"\nCONFIG_KERNEL_GIT_CLONE_URI=\"\"\nCONFIG_BUILD_LOG_DIR=\"\"\nCONFIG_EXTRA_OPTIMIZATION=\"-fno-caller-saves -fno-plt\"\nCONFIG_TARGET_OPTIMIZATION=\"-Os -pipe -mcpu=generic\"\n# CONFIG_EXTRA_TARGET_ARCH is not set\nCONFIG_EXTRA_BINUTILS_CONFIG_OPTIONS=\"\"\nCONFIG_EXTRA_GCC_CONFIG_OPTIONS=\"\"\n# CONFIG_GCC_DEFAULT_PIE is not set\n# CONFIG_GCC_DEFAULT_SSP is not set\n# CONFIG_SJLJ_EXCEPTIONS is not set\n# CONFIG_INSTALL_GFORTRAN is not set\nCONFIG_GDB=y\n# CONFIG_GDB_PYTHON is not set\n# CONFIG_HAS_PREBUILT_LLVM_TOOLCHAIN is not set\nCONFIG_USE_MUSL=y\nCONFIG_SSP_SUPPORT=y\nCONFIG_BINUTILS_VERSION_2_37=y\nCONFIG_BINUTILS_VERSION=\"2.37\"\nCONFIG_GCC_VERSION=\"11.2.0\"\nCONFIG_LIBC=\"musl\"\nCONFIG_TARGET_SUFFIX=\"musl\"\n# CONFIG_IB is not set\n# CONFIG_SDK is not set\n# CONFIG_MAKE_TOOLCHAIN is not set\n# CONFIG_IMAGEOPT is not set\n# CONFIG_PREINITOPT is not set\nCONFIG_TARGET_PREINIT_SUPPRESS_STDERR=y\n# CONFIG_TARGET_PREINIT_DISABLE_FAILSAFE is not set\nCONFIG_TARGET_PREINIT_TIMEOUT=2\n# CONFIG_TARGET_PREINIT_SHOW_NETMSG is not set\n# CONFIG_TARGET_PREINIT_SUPPRESS_FAILSAFE_NETMSG is not set\nCONFIG_TARGET_PREINIT_IFNAME=\"\"\nCONFIG_TARGET_PREINIT_IP=\"192.168.1.1\"\nCONFIG_TARGET_PREINIT_NETMASK=\"255.255.255.0\"\nCONFIG_TARGET_PREINIT_BROADCAST=\"192.168.1.255\"\n# CONFIG_INITOPT is not set\nCONFIG_TARGET_INIT_PATH=\"/usr/sbin:/usr/bin:/sbin:/bin\"\nCONFIG_TARGET_INIT_ENV=\"\"\nCONFIG_TARGET_INIT_CMD=\"/sbin/init\"\nCONFIG_TARGET_INIT_SUPPRESS_STDERR=y\n# CONFIG_VERSIONOPT is not set\nCONFIG_PER_FEED_REPO=y\n# CONFIG_FEED_packages is not set\n# CONFIG_FEED_luci is not set\n# CONFIG_FEED_routing is not set\n# CONFIG_FEED_telephony is not set\n\n#\n# Base system\n#\n# CONFIG_PACKAGE_attendedsysupgrade-common is not set\n# CONFIG_PACKAGE_auc is not set\nCONFIG_PACKAGE_base-files=y\nCONFIG_PACKAGE_block-mount=y\n# CONFIG_PACKAGE_blockd is not set\n# CONFIG_PACKAGE_bridge is not set\nCONFIG_PACKAGE_busybox=y\n# CONFIG_BUSYBOX_CUSTOM is not set\nCONFIG_BUSYBOX_DEFAULT_HAVE_DOT_CONFIG=y\n# CONFIG_BUSYBOX_DEFAULT_DESKTOP is not set\n# CONFIG_BUSYBOX_DEFAULT_EXTRA_COMPAT is not set\n# CONFIG_BUSYBOX_DEFAULT_FEDORA_COMPAT is not set\nCONFIG_BUSYBOX_DEFAULT_INCLUDE_SUSv2=y\nCONFIG_BUSYBOX_DEFAULT_LONG_OPTS=y\nCONFIG_BUSYBOX_DEFAULT_SHOW_USAGE=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_VERBOSE_USAGE=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_COMPRESS_USAGE is not set\nCONFIG_BUSYBOX_DEFAULT_LFS=y\n# CONFIG_BUSYBOX_DEFAULT_PAM is not set\nCONFIG_BUSYBOX_DEFAULT_FEATURE_DEVPTS=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_UTMP is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_WTMP is not set\nCONFIG_BUSYBOX_DEFAULT_FEATURE_PIDFILE=y\nCONFIG_BUSYBOX_DEFAULT_PID_FILE_PATH=\"/var/run\"\n# CONFIG_BUSYBOX_DEFAULT_BUSYBOX is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_SHOW_SCRIPT is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_INSTALLER is not set\n# CONFIG_BUSYBOX_DEFAULT_INSTALL_NO_USR is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_SUID is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_SUID_CONFIG is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_SUID_CONFIG_QUIET is not set\nCONFIG_BUSYBOX_DEFAULT_FEATURE_PREFER_APPLETS=y\nCONFIG_BUSYBOX_DEFAULT_BUSYBOX_EXEC_PATH=\"/proc/self/exe\"\n# CONFIG_BUSYBOX_DEFAULT_SELINUX is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_CLEAN_UP is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_SYSLOG_INFO is not set\nCONFIG_BUSYBOX_DEFAULT_FEATURE_SYSLOG=y\n# CONFIG_BUSYBOX_DEFAULT_STATIC is not set\n# CONFIG_BUSYBOX_DEFAULT_PIE is not set\n# CONFIG_BUSYBOX_DEFAULT_NOMMU is not set\n# CONFIG_BUSYBOX_DEFAULT_BUILD_LIBBUSYBOX is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_LIBBUSYBOX_STATIC is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_INDIVIDUAL is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_SHARED_BUSYBOX is not set\nCONFIG_BUSYBOX_DEFAULT_CROSS_COMPILER_PREFIX=\"\"\nCONFIG_BUSYBOX_DEFAULT_SYSROOT=\"\"\nCONFIG_BUSYBOX_DEFAULT_EXTRA_CFLAGS=\"\"\nCONFIG_BUSYBOX_DEFAULT_EXTRA_LDFLAGS=\"\"\nCONFIG_BUSYBOX_DEFAULT_EXTRA_LDLIBS=\"\"\n# CONFIG_BUSYBOX_DEFAULT_USE_PORTABLE_CODE is not set\n# CONFIG_BUSYBOX_DEFAULT_STACK_OPTIMIZATION_386 is not set\n# CONFIG_BUSYBOX_DEFAULT_STATIC_LIBGCC is not set\nCONFIG_BUSYBOX_DEFAULT_INSTALL_APPLET_SYMLINKS=y\n# CONFIG_BUSYBOX_DEFAULT_INSTALL_APPLET_HARDLINKS is not set\n# CONFIG_BUSYBOX_DEFAULT_INSTALL_APPLET_SCRIPT_WRAPPERS is not set\n# CONFIG_BUSYBOX_DEFAULT_INSTALL_APPLET_DONT is not set\n# CONFIG_BUSYBOX_DEFAULT_INSTALL_SH_APPLET_SYMLINK is not set\n# CONFIG_BUSYBOX_DEFAULT_INSTALL_SH_APPLET_HARDLINK is not set\n# CONFIG_BUSYBOX_DEFAULT_INSTALL_SH_APPLET_SCRIPT_WRAPPER is not set\nCONFIG_BUSYBOX_DEFAULT_PREFIX=\"./_install\"\n# CONFIG_BUSYBOX_DEFAULT_DEBUG is not set\n# CONFIG_BUSYBOX_DEFAULT_DEBUG_PESSIMIZE is not set\n# CONFIG_BUSYBOX_DEFAULT_DEBUG_SANITIZE is not set\n# CONFIG_BUSYBOX_DEFAULT_UNIT_TEST is not set\n# CONFIG_BUSYBOX_DEFAULT_WERROR is not set\n# CONFIG_BUSYBOX_DEFAULT_WARN_SIMPLE_MSG is not set\nCONFIG_BUSYBOX_DEFAULT_NO_DEBUG_LIB=y\n# CONFIG_BUSYBOX_DEFAULT_DMALLOC is not set\n# CONFIG_BUSYBOX_DEFAULT_EFENCE is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_USE_BSS_TAIL is not set\n# CONFIG_BUSYBOX_DEFAULT_FLOAT_DURATION is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_RTMINMAX is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_RTMINMAX_USE_LIBC_DEFINITIONS is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_BUFFERS_USE_MALLOC is not set\nCONFIG_BUSYBOX_DEFAULT_FEATURE_BUFFERS_GO_ON_STACK=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_BUFFERS_GO_IN_BSS is not set\nCONFIG_BUSYBOX_DEFAULT_PASSWORD_MINLEN=6\nCONFIG_BUSYBOX_DEFAULT_MD5_SMALL=1\nCONFIG_BUSYBOX_DEFAULT_SHA3_SMALL=1\nCONFIG_BUSYBOX_DEFAULT_FEATURE_FAST_TOP=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_ETC_NETWORKS is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_ETC_SERVICES is not set\nCONFIG_BUSYBOX_DEFAULT_FEATURE_EDITING=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_EDITING_MAX_LEN=512\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_EDITING_VI is not set\nCONFIG_BUSYBOX_DEFAULT_FEATURE_EDITING_HISTORY=256\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_EDITING_SAVEHISTORY is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_EDITING_SAVE_ON_EXIT is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_REVERSE_SEARCH is not set\nCONFIG_BUSYBOX_DEFAULT_FEATURE_TAB_COMPLETION=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_USERNAME_COMPLETION is not set\nCONFIG_BUSYBOX_DEFAULT_FEATURE_EDITING_FANCY_PROMPT=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_EDITING_WINCH is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_EDITING_ASK_TERMINAL is not set\n# CONFIG_BUSYBOX_DEFAULT_LOCALE_SUPPORT is not set\n# CONFIG_BUSYBOX_DEFAULT_UNICODE_SUPPORT is not set\n# CONFIG_BUSYBOX_DEFAULT_UNICODE_USING_LOCALE is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_CHECK_UNICODE_IN_ENV is not set\nCONFIG_BUSYBOX_DEFAULT_SUBST_WCHAR=0\nCONFIG_BUSYBOX_DEFAULT_LAST_SUPPORTED_WCHAR=0\n# CONFIG_BUSYBOX_DEFAULT_UNICODE_COMBINING_WCHARS is not set\n# CONFIG_BUSYBOX_DEFAULT_UNICODE_WIDE_WCHARS is not set\n# CONFIG_BUSYBOX_DEFAULT_UNICODE_BIDI_SUPPORT is not set\n# CONFIG_BUSYBOX_DEFAULT_UNICODE_NEUTRAL_TABLE is not set\n# CONFIG_BUSYBOX_DEFAULT_UNICODE_PRESERVE_BROKEN is not set\nCONFIG_BUSYBOX_DEFAULT_FEATURE_NON_POSIX_CP=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_VERBOSE_CP_MESSAGE is not set\nCONFIG_BUSYBOX_DEFAULT_FEATURE_USE_SENDFILE=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_COPYBUF_KB=4\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_SKIP_ROOTFS is not set\nCONFIG_BUSYBOX_DEFAULT_MONOTONIC_SYSCALL=y\nCONFIG_BUSYBOX_DEFAULT_IOCTL_HEX2STR_ERROR=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_HWIB is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_SEAMLESS_XZ is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_SEAMLESS_LZMA is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_SEAMLESS_BZ2 is not set\nCONFIG_BUSYBOX_DEFAULT_FEATURE_SEAMLESS_GZ=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_SEAMLESS_Z is not set\n# CONFIG_BUSYBOX_DEFAULT_AR is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_AR_LONG_FILENAMES is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_AR_CREATE is not set\n# CONFIG_BUSYBOX_DEFAULT_UNCOMPRESS is not set\nCONFIG_BUSYBOX_DEFAULT_GUNZIP=y\nCONFIG_BUSYBOX_DEFAULT_ZCAT=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_GUNZIP_LONG_OPTIONS is not set\n# CONFIG_BUSYBOX_DEFAULT_BUNZIP2 is not set\n# CONFIG_BUSYBOX_DEFAULT_BZCAT is not set\n# CONFIG_BUSYBOX_DEFAULT_UNLZMA is not set\n# CONFIG_BUSYBOX_DEFAULT_LZCAT is not set\n# CONFIG_BUSYBOX_DEFAULT_LZMA is not set\n# CONFIG_BUSYBOX_DEFAULT_UNXZ is not set\n# CONFIG_BUSYBOX_DEFAULT_XZCAT is not set\n# CONFIG_BUSYBOX_DEFAULT_XZ is not set\n# CONFIG_BUSYBOX_DEFAULT_BZIP2 is not set\nCONFIG_BUSYBOX_DEFAULT_BZIP2_SMALL=0\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_BZIP2_DECOMPRESS is not set\n# CONFIG_BUSYBOX_DEFAULT_CPIO is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_CPIO_O is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_CPIO_P is not set\n# CONFIG_BUSYBOX_DEFAULT_DPKG is not set\n# CONFIG_BUSYBOX_DEFAULT_DPKG_DEB is not set\nCONFIG_BUSYBOX_DEFAULT_GZIP=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_GZIP_LONG_OPTIONS is not set\nCONFIG_BUSYBOX_DEFAULT_GZIP_FAST=0\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_GZIP_LEVELS is not set\nCONFIG_BUSYBOX_DEFAULT_FEATURE_GZIP_DECOMPRESS=y\n# CONFIG_BUSYBOX_DEFAULT_LZOP is not set\n# CONFIG_BUSYBOX_DEFAULT_UNLZOP is not set\n# CONFIG_BUSYBOX_DEFAULT_LZOPCAT is not set\n# CONFIG_BUSYBOX_DEFAULT_LZOP_COMPR_HIGH is not set\n# CONFIG_BUSYBOX_DEFAULT_RPM is not set\n# CONFIG_BUSYBOX_DEFAULT_RPM2CPIO is not set\nCONFIG_BUSYBOX_DEFAULT_TAR=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_TAR_LONG_OPTIONS is not set\nCONFIG_BUSYBOX_DEFAULT_FEATURE_TAR_CREATE=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_TAR_AUTODETECT is not set\nCONFIG_BUSYBOX_DEFAULT_FEATURE_TAR_FROM=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_TAR_OLDGNU_COMPATIBILITY is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_TAR_OLDSUN_COMPATIBILITY is not set\nCONFIG_BUSYBOX_DEFAULT_FEATURE_TAR_GNU_EXTENSIONS=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_TAR_TO_COMMAND is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_TAR_UNAME_GNAME is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_TAR_NOPRESERVE_TIME is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_TAR_SELINUX is not set\n# CONFIG_BUSYBOX_DEFAULT_UNZIP is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_UNZIP_CDF is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_UNZIP_BZIP2 is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_UNZIP_LZMA is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_UNZIP_XZ is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_LZMA_FAST is not set\nCONFIG_BUSYBOX_DEFAULT_BASENAME=y\nCONFIG_BUSYBOX_DEFAULT_CAT=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_CATN is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_CATV is not set\nCONFIG_BUSYBOX_DEFAULT_CHGRP=y\nCONFIG_BUSYBOX_DEFAULT_CHMOD=y\nCONFIG_BUSYBOX_DEFAULT_CHOWN=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_CHOWN_LONG_OPTIONS is not set\nCONFIG_BUSYBOX_DEFAULT_CHROOT=y\n# CONFIG_BUSYBOX_DEFAULT_CKSUM is not set\n# CONFIG_BUSYBOX_DEFAULT_CRC32 is not set\n# CONFIG_BUSYBOX_DEFAULT_COMM is not set\nCONFIG_BUSYBOX_DEFAULT_CP=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_CP_LONG_OPTIONS is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_CP_REFLINK is not set\nCONFIG_BUSYBOX_DEFAULT_CUT=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_CUT_REGEX is not set\nCONFIG_BUSYBOX_DEFAULT_DATE=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_DATE_ISOFMT=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_DATE_NANO is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_DATE_COMPAT is not set\nCONFIG_BUSYBOX_DEFAULT_DD=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_DD_SIGNAL_HANDLING=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_DD_THIRD_STATUS_LINE is not set\nCONFIG_BUSYBOX_DEFAULT_FEATURE_DD_IBS_OBS=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_DD_STATUS is not set\nCONFIG_BUSYBOX_DEFAULT_DF=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_DF_FANCY is not set\nCONFIG_BUSYBOX_DEFAULT_DIRNAME=y\n# CONFIG_BUSYBOX_DEFAULT_DOS2UNIX is not set\n# CONFIG_BUSYBOX_DEFAULT_UNIX2DOS is not set\nCONFIG_BUSYBOX_DEFAULT_DU=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_DU_DEFAULT_BLOCKSIZE_1K=y\nCONFIG_BUSYBOX_DEFAULT_ECHO=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_FANCY_ECHO=y\nCONFIG_BUSYBOX_DEFAULT_ENV=y\n# CONFIG_BUSYBOX_DEFAULT_EXPAND is not set\n# CONFIG_BUSYBOX_DEFAULT_UNEXPAND is not set\nCONFIG_BUSYBOX_DEFAULT_EXPR=y\nCONFIG_BUSYBOX_DEFAULT_EXPR_MATH_SUPPORT_64=y\n# CONFIG_BUSYBOX_DEFAULT_FACTOR is not set\nCONFIG_BUSYBOX_DEFAULT_FALSE=y\n# CONFIG_BUSYBOX_DEFAULT_FOLD is not set\nCONFIG_BUSYBOX_DEFAULT_HEAD=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_FANCY_HEAD=y\n# CONFIG_BUSYBOX_DEFAULT_HOSTID is not set\nCONFIG_BUSYBOX_DEFAULT_ID=y\n# CONFIG_BUSYBOX_DEFAULT_GROUPS is not set\n# CONFIG_BUSYBOX_DEFAULT_INSTALL is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_INSTALL_LONG_OPTIONS is not set\n# CONFIG_BUSYBOX_DEFAULT_LINK is not set\nCONFIG_BUSYBOX_DEFAULT_LN=y\n# CONFIG_BUSYBOX_DEFAULT_LOGNAME is not set\nCONFIG_BUSYBOX_DEFAULT_LS=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_LS_FILETYPES=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_LS_FOLLOWLINKS=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_LS_RECURSIVE=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_LS_WIDTH=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_LS_SORTFILES=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_LS_TIMESTAMPS=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_LS_USERNAME=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_LS_COLOR=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_LS_COLOR_IS_DEFAULT=y\nCONFIG_BUSYBOX_DEFAULT_MD5SUM=y\n# CONFIG_BUSYBOX_DEFAULT_SHA1SUM is not set\nCONFIG_BUSYBOX_DEFAULT_SHA256SUM=y\n# CONFIG_BUSYBOX_DEFAULT_SHA512SUM is not set\n# CONFIG_BUSYBOX_DEFAULT_SHA3SUM is not set\nCONFIG_BUSYBOX_DEFAULT_FEATURE_MD5_SHA1_SUM_CHECK=y\nCONFIG_BUSYBOX_DEFAULT_MKDIR=y\nCONFIG_BUSYBOX_DEFAULT_MKFIFO=y\nCONFIG_BUSYBOX_DEFAULT_MKNOD=y\nCONFIG_BUSYBOX_DEFAULT_MKTEMP=y\nCONFIG_BUSYBOX_DEFAULT_MV=y\nCONFIG_BUSYBOX_DEFAULT_NICE=y\n# CONFIG_BUSYBOX_DEFAULT_NL is not set\n# CONFIG_BUSYBOX_DEFAULT_NOHUP is not set\n# CONFIG_BUSYBOX_DEFAULT_NPROC is not set\n# CONFIG_BUSYBOX_DEFAULT_OD is not set\n# CONFIG_BUSYBOX_DEFAULT_PASTE is not set\n# CONFIG_BUSYBOX_DEFAULT_PRINTENV is not set\nCONFIG_BUSYBOX_DEFAULT_PRINTF=y\nCONFIG_BUSYBOX_DEFAULT_PWD=y\nCONFIG_BUSYBOX_DEFAULT_READLINK=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_READLINK_FOLLOW=y\n# CONFIG_BUSYBOX_DEFAULT_REALPATH is not set\nCONFIG_BUSYBOX_DEFAULT_RM=y\nCONFIG_BUSYBOX_DEFAULT_RMDIR=y\nCONFIG_BUSYBOX_DEFAULT_SEQ=y\n# CONFIG_BUSYBOX_DEFAULT_SHRED is not set\n# CONFIG_BUSYBOX_DEFAULT_SHUF is not set\nCONFIG_BUSYBOX_DEFAULT_SLEEP=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_FANCY_SLEEP=y\nCONFIG_BUSYBOX_DEFAULT_SORT=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_SORT_BIG is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_SORT_OPTIMIZE_MEMORY is not set\n# CONFIG_BUSYBOX_DEFAULT_SPLIT is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_SPLIT_FANCY is not set\n# CONFIG_BUSYBOX_DEFAULT_STAT is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_STAT_FORMAT is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_STAT_FILESYSTEM is not set\n# CONFIG_BUSYBOX_DEFAULT_STTY is not set\n# CONFIG_BUSYBOX_DEFAULT_SUM is not set\nCONFIG_BUSYBOX_DEFAULT_SYNC=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_SYNC_FANCY is not set\nCONFIG_BUSYBOX_DEFAULT_FSYNC=y\n# CONFIG_BUSYBOX_DEFAULT_TAC is not set\nCONFIG_BUSYBOX_DEFAULT_TAIL=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_FANCY_TAIL=y\nCONFIG_BUSYBOX_DEFAULT_TEE=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_TEE_USE_BLOCK_IO=y\nCONFIG_BUSYBOX_DEFAULT_TEST=y\nCONFIG_BUSYBOX_DEFAULT_TEST1=y\nCONFIG_BUSYBOX_DEFAULT_TEST2=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_TEST_64=y\n# CONFIG_BUSYBOX_DEFAULT_TIMEOUT is not set\nCONFIG_BUSYBOX_DEFAULT_TOUCH=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_TOUCH_SUSV3=y\nCONFIG_BUSYBOX_DEFAULT_TR=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_TR_CLASSES is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_TR_EQUIV is not set\nCONFIG_BUSYBOX_DEFAULT_TRUE=y\n# CONFIG_BUSYBOX_DEFAULT_TRUNCATE is not set\n# CONFIG_BUSYBOX_DEFAULT_TTY is not set\nCONFIG_BUSYBOX_DEFAULT_UNAME=y\nCONFIG_BUSYBOX_DEFAULT_UNAME_OSNAME=\"GNU/Linux\"\n# CONFIG_BUSYBOX_DEFAULT_BB_ARCH is not set\nCONFIG_BUSYBOX_DEFAULT_UNIQ=y\n# CONFIG_BUSYBOX_DEFAULT_UNLINK is not set\n# CONFIG_BUSYBOX_DEFAULT_USLEEP is not set\n# CONFIG_BUSYBOX_DEFAULT_UUDECODE is not set\n# CONFIG_BUSYBOX_DEFAULT_BASE32 is not set\n# CONFIG_BUSYBOX_DEFAULT_BASE64 is not set\n# CONFIG_BUSYBOX_DEFAULT_UUENCODE is not set\nCONFIG_BUSYBOX_DEFAULT_WC=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_WC_LARGE is not set\n# CONFIG_BUSYBOX_DEFAULT_WHO is not set\n# CONFIG_BUSYBOX_DEFAULT_W is not set\n# CONFIG_BUSYBOX_DEFAULT_USERS is not set\n# CONFIG_BUSYBOX_DEFAULT_WHOAMI is not set\nCONFIG_BUSYBOX_DEFAULT_YES=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_VERBOSE is not set\nCONFIG_BUSYBOX_DEFAULT_FEATURE_PRESERVE_HARDLINKS=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_HUMAN_READABLE=y\n# CONFIG_BUSYBOX_DEFAULT_CHVT is not set\nCONFIG_BUSYBOX_DEFAULT_CLEAR=y\n# CONFIG_BUSYBOX_DEFAULT_DEALLOCVT is not set\n# CONFIG_BUSYBOX_DEFAULT_DUMPKMAP is not set\n# CONFIG_BUSYBOX_DEFAULT_FGCONSOLE is not set\n# CONFIG_BUSYBOX_DEFAULT_KBD_MODE is not set\n# CONFIG_BUSYBOX_DEFAULT_LOADFONT is not set\n# CONFIG_BUSYBOX_DEFAULT_SETFONT is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_SETFONT_TEXTUAL_MAP is not set\nCONFIG_BUSYBOX_DEFAULT_DEFAULT_SETFONT_DIR=\"\"\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_LOADFONT_PSF2 is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_LOADFONT_RAW is not set\n# CONFIG_BUSYBOX_DEFAULT_LOADKMAP is not set\n# CONFIG_BUSYBOX_DEFAULT_OPENVT is not set\nCONFIG_BUSYBOX_DEFAULT_RESET=y\n# CONFIG_BUSYBOX_DEFAULT_RESIZE is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_RESIZE_PRINT is not set\n# CONFIG_BUSYBOX_DEFAULT_SETCONSOLE is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_SETCONSOLE_LONG_OPTIONS is not set\n# CONFIG_BUSYBOX_DEFAULT_SETKEYCODES is not set\n# CONFIG_BUSYBOX_DEFAULT_SETLOGCONS is not set\n# CONFIG_BUSYBOX_DEFAULT_SHOWKEY is not set\n# CONFIG_BUSYBOX_DEFAULT_PIPE_PROGRESS is not set\n# CONFIG_BUSYBOX_DEFAULT_RUN_PARTS is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_RUN_PARTS_LONG_OPTIONS is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_RUN_PARTS_FANCY is not set\nCONFIG_BUSYBOX_DEFAULT_START_STOP_DAEMON=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_START_STOP_DAEMON_LONG_OPTIONS is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_START_STOP_DAEMON_FANCY is not set\nCONFIG_BUSYBOX_DEFAULT_WHICH=y\n# CONFIG_BUSYBOX_DEFAULT_MINIPS is not set\n# CONFIG_BUSYBOX_DEFAULT_NUKE is not set\n# CONFIG_BUSYBOX_DEFAULT_RESUME is not set\n# CONFIG_BUSYBOX_DEFAULT_RUN_INIT is not set\nCONFIG_BUSYBOX_DEFAULT_AWK=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_AWK_LIBM=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_AWK_GNU_EXTENSIONS=y\nCONFIG_BUSYBOX_DEFAULT_CMP=y\n# CONFIG_BUSYBOX_DEFAULT_DIFF is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_DIFF_LONG_OPTIONS is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_DIFF_DIR is not set\n# CONFIG_BUSYBOX_DEFAULT_ED is not set\n# CONFIG_BUSYBOX_DEFAULT_PATCH is not set\nCONFIG_BUSYBOX_DEFAULT_SED=y\nCONFIG_BUSYBOX_DEFAULT_VI=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_VI_MAX_LEN=1024\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_VI_8BIT is not set\nCONFIG_BUSYBOX_DEFAULT_FEATURE_VI_COLON=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_VI_COLON_EXPAND is not set\nCONFIG_BUSYBOX_DEFAULT_FEATURE_VI_YANKMARK=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_VI_SEARCH=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_VI_REGEX_SEARCH is not set\nCONFIG_BUSYBOX_DEFAULT_FEATURE_VI_USE_SIGNALS=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_VI_DOT_CMD=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_VI_READONLY=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_VI_SETOPTS=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_VI_SET=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_VI_WIN_RESIZE=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_VI_ASK_TERMINAL=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_VI_UNDO is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_VI_UNDO_QUEUE is not set\nCONFIG_BUSYBOX_DEFAULT_FEATURE_VI_UNDO_QUEUE_MAX=0\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_VI_VERBOSE_STATUS is not set\nCONFIG_BUSYBOX_DEFAULT_FEATURE_ALLOW_EXEC=y\nCONFIG_BUSYBOX_DEFAULT_FIND=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_FIND_PRINT0=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_FIND_MTIME=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_FIND_MMIN=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_FIND_PERM=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_FIND_TYPE=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_FIND_EXECUTABLE is not set\nCONFIG_BUSYBOX_DEFAULT_FEATURE_FIND_XDEV=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_FIND_MAXDEPTH=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_FIND_NEWER=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_FIND_INUM is not set\nCONFIG_BUSYBOX_DEFAULT_FEATURE_FIND_EXEC=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_FIND_EXEC_PLUS is not set\nCONFIG_BUSYBOX_DEFAULT_FEATURE_FIND_USER=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_FIND_GROUP=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_FIND_NOT=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_FIND_DEPTH=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_FIND_PAREN=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_FIND_SIZE=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_FIND_PRUNE=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_FIND_QUIT is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_FIND_DELETE is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_FIND_EMPTY is not set\nCONFIG_BUSYBOX_DEFAULT_FEATURE_FIND_PATH=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_FIND_REGEX=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_FIND_CONTEXT is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_FIND_LINKS is not set\nCONFIG_BUSYBOX_DEFAULT_GREP=y\nCONFIG_BUSYBOX_DEFAULT_EGREP=y\nCONFIG_BUSYBOX_DEFAULT_FGREP=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_GREP_CONTEXT=y\nCONFIG_BUSYBOX_DEFAULT_XARGS=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_XARGS_SUPPORT_CONFIRMATION=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_XARGS_SUPPORT_QUOTES=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_XARGS_SUPPORT_TERMOPT=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_XARGS_SUPPORT_ZERO_TERM=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_XARGS_SUPPORT_REPL_STR is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_XARGS_SUPPORT_PARALLEL is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_XARGS_SUPPORT_ARGS_FILE is not set\n# CONFIG_BUSYBOX_DEFAULT_BOOTCHARTD is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_BOOTCHARTD_BLOATED_HEADER is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_BOOTCHARTD_CONFIG_FILE is not set\nCONFIG_BUSYBOX_DEFAULT_HALT=y\nCONFIG_BUSYBOX_DEFAULT_POWEROFF=y\nCONFIG_BUSYBOX_DEFAULT_REBOOT=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_WAIT_FOR_INIT is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_CALL_TELINIT is not set\nCONFIG_BUSYBOX_DEFAULT_TELINIT_PATH=\"\"\n# CONFIG_BUSYBOX_DEFAULT_INIT is not set\n# CONFIG_BUSYBOX_DEFAULT_LINUXRC is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_USE_INITTAB is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_KILL_REMOVED is not set\nCONFIG_BUSYBOX_DEFAULT_FEATURE_KILL_DELAY=0\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_INIT_SCTTY is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_INIT_SYSLOG is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_INIT_QUIET is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_INIT_COREDUMPS is not set\nCONFIG_BUSYBOX_DEFAULT_INIT_TERMINAL_TYPE=\"\"\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_INIT_MODIFY_CMDLINE is not set\nCONFIG_BUSYBOX_DEFAULT_FEATURE_SHADOWPASSWDS=y\n# CONFIG_BUSYBOX_DEFAULT_USE_BB_PWD_GRP is not set\n# CONFIG_BUSYBOX_DEFAULT_USE_BB_SHADOW is not set\n# CONFIG_BUSYBOX_DEFAULT_USE_BB_CRYPT is not set\n# CONFIG_BUSYBOX_DEFAULT_USE_BB_CRYPT_SHA is not set\n# CONFIG_BUSYBOX_DEFAULT_ADD_SHELL is not set\n# CONFIG_BUSYBOX_DEFAULT_REMOVE_SHELL is not set\n# CONFIG_BUSYBOX_DEFAULT_ADDGROUP is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_ADDUSER_TO_GROUP is not set\n# CONFIG_BUSYBOX_DEFAULT_ADDUSER is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_CHECK_NAMES is not set\nCONFIG_BUSYBOX_DEFAULT_LAST_ID=0\nCONFIG_BUSYBOX_DEFAULT_FIRST_SYSTEM_ID=0\nCONFIG_BUSYBOX_DEFAULT_LAST_SYSTEM_ID=0\n# CONFIG_BUSYBOX_DEFAULT_CHPASSWD is not set\nCONFIG_BUSYBOX_DEFAULT_FEATURE_DEFAULT_PASSWD_ALGO=\"md5\"\n# CONFIG_BUSYBOX_DEFAULT_CRYPTPW is not set\n# CONFIG_BUSYBOX_DEFAULT_MKPASSWD is not set\n# CONFIG_BUSYBOX_DEFAULT_DELUSER is not set\n# CONFIG_BUSYBOX_DEFAULT_DELGROUP is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_DEL_USER_FROM_GROUP is not set\n# CONFIG_BUSYBOX_DEFAULT_GETTY is not set\nCONFIG_BUSYBOX_DEFAULT_LOGIN=y\nCONFIG_BUSYBOX_DEFAULT_LOGIN_SESSION_AS_CHILD=y\n# CONFIG_BUSYBOX_DEFAULT_LOGIN_SCRIPTS is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_NOLOGIN is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_SECURETTY is not set\nCONFIG_BUSYBOX_DEFAULT_PASSWD=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_PASSWD_WEAK_CHECK=y\n# CONFIG_BUSYBOX_DEFAULT_SU is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_SU_SYSLOG is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_SU_CHECKS_SHELLS is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_SU_BLANK_PW_NEEDS_SECURE_TTY is not set\n# CONFIG_BUSYBOX_DEFAULT_SULOGIN is not set\n# CONFIG_BUSYBOX_DEFAULT_VLOCK is not set\n# CONFIG_BUSYBOX_DEFAULT_CHATTR is not set\n# CONFIG_BUSYBOX_DEFAULT_FSCK is not set\n# CONFIG_BUSYBOX_DEFAULT_LSATTR is not set\n# CONFIG_BUSYBOX_DEFAULT_TUNE2FS is not set\n# CONFIG_BUSYBOX_DEFAULT_MODPROBE_SMALL is not set\n# CONFIG_BUSYBOX_DEFAULT_DEPMOD is not set\n# CONFIG_BUSYBOX_DEFAULT_INSMOD is not set\n# CONFIG_BUSYBOX_DEFAULT_LSMOD is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_LSMOD_PRETTY_2_6_OUTPUT is not set\n# CONFIG_BUSYBOX_DEFAULT_MODINFO is not set\n# CONFIG_BUSYBOX_DEFAULT_MODPROBE is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_MODPROBE_BLACKLIST is not set\n# CONFIG_BUSYBOX_DEFAULT_RMMOD is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_CMDLINE_MODULE_OPTIONS is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_MODPROBE_SMALL_CHECK_ALREADY_LOADED is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_2_4_MODULES is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_INSMOD_VERSION_CHECKING is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_INSMOD_KSYMOOPS_SYMBOLS is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_INSMOD_LOADINKMEM is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_INSMOD_LOAD_MAP is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_INSMOD_LOAD_MAP_FULL is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_CHECK_TAINTED_MODULE is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_INSMOD_TRY_MMAP is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_MODUTILS_ALIAS is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_MODUTILS_SYMBOLS is not set\nCONFIG_BUSYBOX_DEFAULT_DEFAULT_MODULES_DIR=\"\"\nCONFIG_BUSYBOX_DEFAULT_DEFAULT_DEPMOD_FILE=\"\"\n# CONFIG_BUSYBOX_DEFAULT_ACPID is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_ACPID_COMPAT is not set\n# CONFIG_BUSYBOX_DEFAULT_BLKDISCARD is not set\n# CONFIG_BUSYBOX_DEFAULT_BLKID is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_BLKID_TYPE is not set\n# CONFIG_BUSYBOX_DEFAULT_BLOCKDEV is not set\n# CONFIG_BUSYBOX_DEFAULT_CAL is not set\n# CONFIG_BUSYBOX_DEFAULT_CHRT is not set\nCONFIG_BUSYBOX_DEFAULT_DMESG=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_DMESG_PRETTY=y\n# CONFIG_BUSYBOX_DEFAULT_EJECT is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_EJECT_SCSI is not set\n# CONFIG_BUSYBOX_DEFAULT_FALLOCATE is not set\n# CONFIG_BUSYBOX_DEFAULT_FATATTR is not set\n# CONFIG_BUSYBOX_DEFAULT_FBSET is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_FBSET_FANCY is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_FBSET_READMODE is not set\n# CONFIG_BUSYBOX_DEFAULT_FDFORMAT is not set\n# CONFIG_BUSYBOX_DEFAULT_FDISK is not set\n# CONFIG_BUSYBOX_DEFAULT_FDISK_SUPPORT_LARGE_DISKS is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_FDISK_WRITABLE is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_AIX_LABEL is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_SGI_LABEL is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_SUN_LABEL is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_OSF_LABEL is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_GPT_LABEL is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_FDISK_ADVANCED is not set\n# CONFIG_BUSYBOX_DEFAULT_FINDFS is not set\nCONFIG_BUSYBOX_DEFAULT_FLOCK=y\n# CONFIG_BUSYBOX_DEFAULT_FDFLUSH is not set\n# CONFIG_BUSYBOX_DEFAULT_FREERAMDISK is not set\n# CONFIG_BUSYBOX_DEFAULT_FSCK_MINIX is not set\n# CONFIG_BUSYBOX_DEFAULT_FSFREEZE is not set\n# CONFIG_BUSYBOX_DEFAULT_FSTRIM is not set\n# CONFIG_BUSYBOX_DEFAULT_GETOPT is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_GETOPT_LONG is not set\nCONFIG_BUSYBOX_DEFAULT_HEXDUMP=y\n# CONFIG_BUSYBOX_DEFAULT_HD is not set\n# CONFIG_BUSYBOX_DEFAULT_XXD is not set\nCONFIG_BUSYBOX_DEFAULT_HWCLOCK=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_HWCLOCK_ADJTIME_FHS is not set\n# CONFIG_BUSYBOX_DEFAULT_IONICE is not set\n# CONFIG_BUSYBOX_DEFAULT_IPCRM is not set\n# CONFIG_BUSYBOX_DEFAULT_IPCS is not set\n# CONFIG_BUSYBOX_DEFAULT_LAST is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_LAST_FANCY is not set\n# CONFIG_BUSYBOX_DEFAULT_LOSETUP is not set\n# CONFIG_BUSYBOX_DEFAULT_LSPCI is not set\n# CONFIG_BUSYBOX_DEFAULT_LSUSB is not set\n# CONFIG_BUSYBOX_DEFAULT_MDEV is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_MDEV_CONF is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_MDEV_RENAME is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_MDEV_RENAME_REGEXP is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_MDEV_EXEC is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_MDEV_LOAD_FIRMWARE is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_MDEV_DAEMON is not set\n# CONFIG_BUSYBOX_DEFAULT_MESG is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_MESG_ENABLE_ONLY_GROUP is not set\n# CONFIG_BUSYBOX_DEFAULT_MKE2FS is not set\n# CONFIG_BUSYBOX_DEFAULT_MKFS_EXT2 is not set\n# CONFIG_BUSYBOX_DEFAULT_MKFS_MINIX is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_MINIX2 is not set\n# CONFIG_BUSYBOX_DEFAULT_MKFS_REISER is not set\n# CONFIG_BUSYBOX_DEFAULT_MKDOSFS is not set\n# CONFIG_BUSYBOX_DEFAULT_MKFS_VFAT is not set\nCONFIG_BUSYBOX_DEFAULT_MKSWAP=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_MKSWAP_UUID is not set\n# CONFIG_BUSYBOX_DEFAULT_MORE is not set\nCONFIG_BUSYBOX_DEFAULT_MOUNT=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_MOUNT_FAKE is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_MOUNT_VERBOSE is not set\nCONFIG_BUSYBOX_DEFAULT_FEATURE_MOUNT_HELPERS=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_MOUNT_LABEL is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_MOUNT_NFS is not set\nCONFIG_BUSYBOX_DEFAULT_FEATURE_MOUNT_CIFS=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_MOUNT_FLAGS=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_MOUNT_FSTAB=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_MOUNT_OTHERTAB is not set\n# CONFIG_BUSYBOX_DEFAULT_MOUNTPOINT is not set\n# CONFIG_BUSYBOX_DEFAULT_NOLOGIN is not set\n# CONFIG_BUSYBOX_DEFAULT_NOLOGIN_DEPENDENCIES is not set\n# CONFIG_BUSYBOX_DEFAULT_NSENTER is not set\nCONFIG_BUSYBOX_DEFAULT_PIVOT_ROOT=y\n# CONFIG_BUSYBOX_DEFAULT_RDATE is not set\n# CONFIG_BUSYBOX_DEFAULT_RDEV is not set\n# CONFIG_BUSYBOX_DEFAULT_READPROFILE is not set\n# CONFIG_BUSYBOX_DEFAULT_RENICE is not set\n# CONFIG_BUSYBOX_DEFAULT_REV is not set\n# CONFIG_BUSYBOX_DEFAULT_RTCWAKE is not set\n# CONFIG_BUSYBOX_DEFAULT_SCRIPT is not set\n# CONFIG_BUSYBOX_DEFAULT_SCRIPTREPLAY is not set\n# CONFIG_BUSYBOX_DEFAULT_SETARCH is not set\n# CONFIG_BUSYBOX_DEFAULT_LINUX32 is not set\n# CONFIG_BUSYBOX_DEFAULT_LINUX64 is not set\n# CONFIG_BUSYBOX_DEFAULT_SETPRIV is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_SETPRIV_DUMP is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_SETPRIV_CAPABILITIES is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_SETPRIV_CAPABILITY_NAMES is not set\n# CONFIG_BUSYBOX_DEFAULT_SETSID is not set\nCONFIG_BUSYBOX_DEFAULT_SWAPON=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_SWAPON_DISCARD=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_SWAPON_PRI=y\nCONFIG_BUSYBOX_DEFAULT_SWAPOFF=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_SWAPONOFF_LABEL is not set\nCONFIG_BUSYBOX_DEFAULT_SWITCH_ROOT=y\n# CONFIG_BUSYBOX_DEFAULT_TASKSET is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_TASKSET_FANCY is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_TASKSET_CPULIST is not set\n# CONFIG_BUSYBOX_DEFAULT_UEVENT is not set\nCONFIG_BUSYBOX_DEFAULT_UMOUNT=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_UMOUNT_ALL=y\n# CONFIG_BUSYBOX_DEFAULT_UNSHARE is not set\n# CONFIG_BUSYBOX_DEFAULT_WALL is not set\nCONFIG_BUSYBOX_DEFAULT_FEATURE_MOUNT_LOOP=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_MOUNT_LOOP_CREATE is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_MTAB_SUPPORT is not set\n# CONFIG_BUSYBOX_DEFAULT_VOLUMEID is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_VOLUMEID_BCACHE is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_VOLUMEID_BTRFS is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_VOLUMEID_CRAMFS is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_VOLUMEID_EROFS is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_VOLUMEID_EXFAT is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_VOLUMEID_EXT is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_VOLUMEID_F2FS is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_VOLUMEID_FAT is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_VOLUMEID_HFS is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_VOLUMEID_ISO9660 is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_VOLUMEID_JFS is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_VOLUMEID_LFS is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_VOLUMEID_LINUXRAID is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_VOLUMEID_LINUXSWAP is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_VOLUMEID_LUKS is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_VOLUMEID_MINIX is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_VOLUMEID_NILFS is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_VOLUMEID_NTFS is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_VOLUMEID_OCFS2 is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_VOLUMEID_REISERFS is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_VOLUMEID_ROMFS is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_VOLUMEID_SQUASHFS is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_VOLUMEID_SYSV is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_VOLUMEID_UBIFS is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_VOLUMEID_UDF is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_VOLUMEID_XFS is not set\n# CONFIG_BUSYBOX_DEFAULT_ADJTIMEX is not set\n# CONFIG_BUSYBOX_DEFAULT_ASCII is not set\n# CONFIG_BUSYBOX_DEFAULT_BBCONFIG is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_COMPRESS_BBCONFIG is not set\n# CONFIG_BUSYBOX_DEFAULT_BC is not set\n# CONFIG_BUSYBOX_DEFAULT_DC is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_DC_BIG is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_DC_LIBM is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_BC_INTERACTIVE is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_BC_LONG_OPTIONS is not set\n# CONFIG_BUSYBOX_DEFAULT_BEEP is not set\nCONFIG_BUSYBOX_DEFAULT_FEATURE_BEEP_FREQ=0\nCONFIG_BUSYBOX_DEFAULT_FEATURE_BEEP_LENGTH_MS=0\n# CONFIG_BUSYBOX_DEFAULT_CHAT is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_CHAT_NOFAIL is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_CHAT_TTY_HIFI is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_CHAT_IMPLICIT_CR is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_CHAT_SWALLOW_OPTS is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_CHAT_SEND_ESCAPES is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_CHAT_VAR_ABORT_LEN is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_CHAT_CLR_ABORT is not set\n# CONFIG_BUSYBOX_DEFAULT_CONSPY is not set\nCONFIG_BUSYBOX_DEFAULT_CROND=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_CROND_D is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_CROND_CALL_SENDMAIL is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_CROND_SPECIAL_TIMES is not set\nCONFIG_BUSYBOX_DEFAULT_FEATURE_CROND_DIR=\"/etc\"\nCONFIG_BUSYBOX_DEFAULT_CRONTAB=y\n# CONFIG_BUSYBOX_DEFAULT_DEVFSD is not set\n# CONFIG_BUSYBOX_DEFAULT_DEVFSD_MODLOAD is not set\n# CONFIG_BUSYBOX_DEFAULT_DEVFSD_FG_NP is not set\n# CONFIG_BUSYBOX_DEFAULT_DEVFSD_VERBOSE is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_DEVFS is not set\n# CONFIG_BUSYBOX_DEFAULT_DEVMEM is not set\n# CONFIG_BUSYBOX_DEFAULT_FBSPLASH is not set\n# CONFIG_BUSYBOX_DEFAULT_FLASH_ERASEALL is not set\n# CONFIG_BUSYBOX_DEFAULT_FLASH_LOCK is not set\n# CONFIG_BUSYBOX_DEFAULT_FLASH_UNLOCK is not set\n# CONFIG_BUSYBOX_DEFAULT_FLASHCP is not set\n# CONFIG_BUSYBOX_DEFAULT_HDPARM is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_HDPARM_GET_IDENTITY is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_HDPARM_HDIO_SCAN_HWIF is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_HDPARM_HDIO_UNREGISTER_HWIF is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_HDPARM_HDIO_DRIVE_RESET is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_HDPARM_HDIO_TRISTATE_HWIF is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_HDPARM_HDIO_GETSET_DMA is not set\n# CONFIG_BUSYBOX_DEFAULT_HEXEDIT is not set\n# CONFIG_BUSYBOX_DEFAULT_I2CGET is not set\n# CONFIG_BUSYBOX_DEFAULT_I2CSET is not set\n# CONFIG_BUSYBOX_DEFAULT_I2CDUMP is not set\n# CONFIG_BUSYBOX_DEFAULT_I2CDETECT is not set\n# CONFIG_BUSYBOX_DEFAULT_I2CTRANSFER is not set\n# CONFIG_BUSYBOX_DEFAULT_INOTIFYD is not set\nCONFIG_BUSYBOX_DEFAULT_LESS=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_LESS_MAXLINES=9999999\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_LESS_BRACKETS is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_LESS_FLAGS is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_LESS_TRUNCATE is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_LESS_MARKS is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_LESS_REGEXP is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_LESS_WINCH is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_LESS_ASK_TERMINAL is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_LESS_DASHCMD is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_LESS_LINENUMS is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_LESS_RAW is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_LESS_ENV is not set\nCONFIG_BUSYBOX_DEFAULT_LOCK=y\n# CONFIG_BUSYBOX_DEFAULT_LSSCSI is not set\n# CONFIG_BUSYBOX_DEFAULT_MAKEDEVS is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_MAKEDEVS_LEAF is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_MAKEDEVS_TABLE is not set\n# CONFIG_BUSYBOX_DEFAULT_MAN is not set\n# CONFIG_BUSYBOX_DEFAULT_MICROCOM is not set\n# CONFIG_BUSYBOX_DEFAULT_MIM is not set\n# CONFIG_BUSYBOX_DEFAULT_MT is not set\n# CONFIG_BUSYBOX_DEFAULT_NANDWRITE is not set\n# CONFIG_BUSYBOX_DEFAULT_NANDDUMP is not set\n# CONFIG_BUSYBOX_DEFAULT_PARTPROBE is not set\n# CONFIG_BUSYBOX_DEFAULT_RAIDAUTORUN is not set\n# CONFIG_BUSYBOX_DEFAULT_READAHEAD is not set\n# CONFIG_BUSYBOX_DEFAULT_RFKILL is not set\n# CONFIG_BUSYBOX_DEFAULT_RUNLEVEL is not set\n# CONFIG_BUSYBOX_DEFAULT_RX is not set\n# CONFIG_BUSYBOX_DEFAULT_SETFATTR is not set\n# CONFIG_BUSYBOX_DEFAULT_SETSERIAL is not set\nCONFIG_BUSYBOX_DEFAULT_STRINGS=y\nCONFIG_BUSYBOX_DEFAULT_TIME=y\n# CONFIG_BUSYBOX_DEFAULT_TS is not set\n# CONFIG_BUSYBOX_DEFAULT_TTYSIZE is not set\n# CONFIG_BUSYBOX_DEFAULT_UBIATTACH is not set\n# CONFIG_BUSYBOX_DEFAULT_UBIDETACH is not set\n# CONFIG_BUSYBOX_DEFAULT_UBIMKVOL is not set\n# CONFIG_BUSYBOX_DEFAULT_UBIRMVOL is not set\n# CONFIG_BUSYBOX_DEFAULT_UBIRSVOL is not set\n# CONFIG_BUSYBOX_DEFAULT_UBIUPDATEVOL is not set\n# CONFIG_BUSYBOX_DEFAULT_UBIRENAME is not set\n# CONFIG_BUSYBOX_DEFAULT_VOLNAME is not set\n# CONFIG_BUSYBOX_DEFAULT_WATCHDOG is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_WATCHDOG_OPEN_TWICE is not set\nCONFIG_BUSYBOX_DEFAULT_FEATURE_IPV6=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_UNIX_LOCAL is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_PREFER_IPV4_ADDRESS is not set\nCONFIG_BUSYBOX_DEFAULT_VERBOSE_RESOLUTION_ERRORS=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_TLS_SHA1 is not set\n# CONFIG_BUSYBOX_DEFAULT_ARP is not set\n# CONFIG_BUSYBOX_DEFAULT_ARPING is not set\nCONFIG_BUSYBOX_DEFAULT_BRCTL=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_BRCTL_FANCY=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_BRCTL_SHOW=y\n# CONFIG_BUSYBOX_DEFAULT_DNSD is not set\n# CONFIG_BUSYBOX_DEFAULT_ETHER_WAKE is not set\n# CONFIG_BUSYBOX_DEFAULT_FTPD is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_FTPD_WRITE is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_FTPD_ACCEPT_BROKEN_LIST is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_FTPD_AUTHENTICATION is not set\n# CONFIG_BUSYBOX_DEFAULT_FTPGET is not set\n# CONFIG_BUSYBOX_DEFAULT_FTPPUT is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_FTPGETPUT_LONG_OPTIONS is not set\n# CONFIG_BUSYBOX_DEFAULT_HOSTNAME is not set\n# CONFIG_BUSYBOX_DEFAULT_DNSDOMAINNAME is not set\n# CONFIG_BUSYBOX_DEFAULT_HTTPD is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_HTTPD_RANGES is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_HTTPD_SETUID is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_HTTPD_BASIC_AUTH is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_HTTPD_AUTH_MD5 is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_HTTPD_CGI is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_HTTPD_CONFIG_WITH_SCRIPT_INTERPR is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_HTTPD_SET_REMOTE_PORT_TO_ENV is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_HTTPD_ENCODE_URL_STR is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_HTTPD_ERROR_PAGES is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_HTTPD_PROXY is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_HTTPD_GZIP is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_HTTPD_ETAG is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_HTTPD_LAST_MODIFIED is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_HTTPD_DATE is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_HTTPD_ACL_IP is not set\nCONFIG_BUSYBOX_DEFAULT_IFCONFIG=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_IFCONFIG_STATUS=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_IFCONFIG_SLIP is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_IFCONFIG_MEMSTART_IOADDR_IRQ is not set\nCONFIG_BUSYBOX_DEFAULT_FEATURE_IFCONFIG_HW=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_IFCONFIG_BROADCAST_PLUS=y\n# CONFIG_BUSYBOX_DEFAULT_IFENSLAVE is not set\n# CONFIG_BUSYBOX_DEFAULT_IFPLUGD is not set\n# CONFIG_BUSYBOX_DEFAULT_IFUP is not set\n# CONFIG_BUSYBOX_DEFAULT_IFDOWN is not set\nCONFIG_BUSYBOX_DEFAULT_IFUPDOWN_IFSTATE_PATH=\"\"\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_IFUPDOWN_IP is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_IFUPDOWN_IPV4 is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_IFUPDOWN_IPV6 is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_IFUPDOWN_MAPPING is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_IFUPDOWN_EXTERNAL_DHCP is not set\n# CONFIG_BUSYBOX_DEFAULT_INETD is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_INETD_SUPPORT_BUILTIN_ECHO is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_INETD_SUPPORT_BUILTIN_DISCARD is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_INETD_SUPPORT_BUILTIN_TIME is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_INETD_SUPPORT_BUILTIN_DAYTIME is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_INETD_SUPPORT_BUILTIN_CHARGEN is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_INETD_RPC is not set\nCONFIG_BUSYBOX_DEFAULT_IP=y\n# CONFIG_BUSYBOX_DEFAULT_IPADDR is not set\n# CONFIG_BUSYBOX_DEFAULT_IPLINK is not set\n# CONFIG_BUSYBOX_DEFAULT_IPROUTE is not set\n# CONFIG_BUSYBOX_DEFAULT_IPTUNNEL is not set\n# CONFIG_BUSYBOX_DEFAULT_IPRULE is not set\n# CONFIG_BUSYBOX_DEFAULT_IPNEIGH is not set\nCONFIG_BUSYBOX_DEFAULT_FEATURE_IP_ADDRESS=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_IP_LINK=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_IP_ROUTE=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_IP_ROUTE_DIR=\"/etc/iproute2\"\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_IP_TUNNEL is not set\nCONFIG_BUSYBOX_DEFAULT_FEATURE_IP_RULE=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_IP_NEIGH=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_IP_RARE_PROTOCOLS is not set\n# CONFIG_BUSYBOX_DEFAULT_IPCALC is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_IPCALC_LONG_OPTIONS is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_IPCALC_FANCY is not set\n# CONFIG_BUSYBOX_DEFAULT_FAKEIDENTD is not set\n# CONFIG_BUSYBOX_DEFAULT_NAMEIF is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_NAMEIF_EXTENDED is not set\n# CONFIG_BUSYBOX_DEFAULT_NBDCLIENT is not set\nCONFIG_BUSYBOX_DEFAULT_NC=y\n# CONFIG_BUSYBOX_DEFAULT_NETCAT is not set\n# CONFIG_BUSYBOX_DEFAULT_NC_SERVER is not set\n# CONFIG_BUSYBOX_DEFAULT_NC_EXTRA is not set\n# CONFIG_BUSYBOX_DEFAULT_NC_110_COMPAT is not set\nCONFIG_BUSYBOX_DEFAULT_NETMSG=y\nCONFIG_BUSYBOX_DEFAULT_NETSTAT=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_NETSTAT_WIDE=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_NETSTAT_PRG=y\nCONFIG_BUSYBOX_DEFAULT_NSLOOKUP=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_NSLOOKUP_BIG=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_NSLOOKUP_LONG_OPTIONS is not set\nCONFIG_BUSYBOX_DEFAULT_NTPD=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_NTPD_SERVER=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_NTPD_CONF is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_NTP_AUTH is not set\nCONFIG_BUSYBOX_DEFAULT_PING=y\nCONFIG_BUSYBOX_DEFAULT_PING6=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_FANCY_PING=y\n# CONFIG_BUSYBOX_DEFAULT_PSCAN is not set\nCONFIG_BUSYBOX_DEFAULT_ROUTE=y\n# CONFIG_BUSYBOX_DEFAULT_SLATTACH is not set\n# CONFIG_BUSYBOX_DEFAULT_SSL_CLIENT is not set\n# CONFIG_BUSYBOX_DEFAULT_TC is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_TC_INGRESS is not set\n# CONFIG_BUSYBOX_DEFAULT_TCPSVD is not set\n# CONFIG_BUSYBOX_DEFAULT_UDPSVD is not set\n# CONFIG_BUSYBOX_DEFAULT_TELNET is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_TELNET_TTYPE is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_TELNET_AUTOLOGIN is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_TELNET_WIDTH is not set\n# CONFIG_BUSYBOX_DEFAULT_TELNETD is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_TELNETD_STANDALONE is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_TELNETD_INETD_WAIT is not set\n# CONFIG_BUSYBOX_DEFAULT_TFTP is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_TFTP_PROGRESS_BAR is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_TFTP_HPA_COMPAT is not set\n# CONFIG_BUSYBOX_DEFAULT_TFTPD is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_TFTP_GET is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_TFTP_PUT is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_TFTP_BLOCKSIZE is not set\n# CONFIG_BUSYBOX_DEFAULT_TFTP_DEBUG is not set\n# CONFIG_BUSYBOX_DEFAULT_TLS is not set\nCONFIG_BUSYBOX_DEFAULT_TRACEROUTE=y\nCONFIG_BUSYBOX_DEFAULT_TRACEROUTE6=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_TRACEROUTE_VERBOSE=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_TRACEROUTE_USE_ICMP is not set\n# CONFIG_BUSYBOX_DEFAULT_TUNCTL is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_TUNCTL_UG is not set\n# CONFIG_BUSYBOX_DEFAULT_VCONFIG is not set\n# CONFIG_BUSYBOX_DEFAULT_WGET is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_WGET_LONG_OPTIONS is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_WGET_STATUSBAR is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_WGET_FTP is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_WGET_AUTHENTICATION is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_WGET_TIMEOUT is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_WGET_HTTPS is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_WGET_OPENSSL is not set\n# CONFIG_BUSYBOX_DEFAULT_WHOIS is not set\n# CONFIG_BUSYBOX_DEFAULT_ZCIP is not set\n# CONFIG_BUSYBOX_DEFAULT_UDHCPD is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_UDHCPD_BASE_IP_ON_MAC is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_UDHCPD_WRITE_LEASES_EARLY is not set\nCONFIG_BUSYBOX_DEFAULT_DHCPD_LEASES_FILE=\"\"\n# CONFIG_BUSYBOX_DEFAULT_DUMPLEASES is not set\n# CONFIG_BUSYBOX_DEFAULT_DHCPRELAY is not set\nCONFIG_BUSYBOX_DEFAULT_UDHCPC=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_UDHCPC_ARPING is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_UDHCPC_SANITIZEOPT is not set\nCONFIG_BUSYBOX_DEFAULT_UDHCPC_DEFAULT_SCRIPT=\"/usr/share/udhcpc/default.script\"\n# CONFIG_BUSYBOX_DEFAULT_UDHCPC6 is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_UDHCPC6_RFC3646 is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_UDHCPC6_RFC4704 is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_UDHCPC6_RFC4833 is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_UDHCPC6_RFC5970 is not set\nCONFIG_BUSYBOX_DEFAULT_UDHCPC_DEFAULT_INTERFACE=\"\"\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_UDHCP_PORT is not set\nCONFIG_BUSYBOX_DEFAULT_UDHCP_DEBUG=0\nCONFIG_BUSYBOX_DEFAULT_UDHCPC_SLACK_FOR_BUGGY_SERVERS=80\nCONFIG_BUSYBOX_DEFAULT_FEATURE_UDHCP_RFC3397=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_UDHCP_8021Q is not set\nCONFIG_BUSYBOX_DEFAULT_IFUPDOWN_UDHCPC_CMD_OPTIONS=\"\"\n# CONFIG_BUSYBOX_DEFAULT_LPD is not set\n# CONFIG_BUSYBOX_DEFAULT_LPR is not set\n# CONFIG_BUSYBOX_DEFAULT_LPQ is not set\n# CONFIG_BUSYBOX_DEFAULT_MAKEMIME is not set\n# CONFIG_BUSYBOX_DEFAULT_POPMAILDIR is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_POPMAILDIR_DELIVERY is not set\n# CONFIG_BUSYBOX_DEFAULT_REFORMIME is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_REFORMIME_COMPAT is not set\n# CONFIG_BUSYBOX_DEFAULT_SENDMAIL is not set\nCONFIG_BUSYBOX_DEFAULT_FEATURE_MIME_CHARSET=\"\"\nCONFIG_BUSYBOX_DEFAULT_FREE=y\n# CONFIG_BUSYBOX_DEFAULT_FUSER is not set\n# CONFIG_BUSYBOX_DEFAULT_IOSTAT is not set\nCONFIG_BUSYBOX_DEFAULT_KILL=y\nCONFIG_BUSYBOX_DEFAULT_KILLALL=y\n# CONFIG_BUSYBOX_DEFAULT_KILLALL5 is not set\n# CONFIG_BUSYBOX_DEFAULT_LSOF is not set\n# CONFIG_BUSYBOX_DEFAULT_MPSTAT is not set\n# CONFIG_BUSYBOX_DEFAULT_NMETER is not set\nCONFIG_BUSYBOX_DEFAULT_PGREP=y\n# CONFIG_BUSYBOX_DEFAULT_PKILL is not set\nCONFIG_BUSYBOX_DEFAULT_PIDOF=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_PIDOF_SINGLE is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_PIDOF_OMIT is not set\n# CONFIG_BUSYBOX_DEFAULT_PMAP is not set\n# CONFIG_BUSYBOX_DEFAULT_POWERTOP is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_POWERTOP_INTERACTIVE is not set\nCONFIG_BUSYBOX_DEFAULT_PS=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_PS_WIDE=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_PS_LONG is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_PS_TIME is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_PS_UNUSUAL_SYSTEMS is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_PS_ADDITIONAL_COLUMNS is not set\n# CONFIG_BUSYBOX_DEFAULT_PSTREE is not set\n# CONFIG_BUSYBOX_DEFAULT_PWDX is not set\n# CONFIG_BUSYBOX_DEFAULT_SMEMCAP is not set\nCONFIG_BUSYBOX_DEFAULT_BB_SYSCTL=y\nCONFIG_BUSYBOX_DEFAULT_TOP=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_TOP_INTERACTIVE is not set\nCONFIG_BUSYBOX_DEFAULT_FEATURE_TOP_CPU_USAGE_PERCENTAGE=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_TOP_CPU_GLOBAL_PERCENTS=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_TOP_SMP_CPU is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_TOP_DECIMALS is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_TOP_SMP_PROCESS is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_TOPMEM is not set\nCONFIG_BUSYBOX_DEFAULT_UPTIME=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_UPTIME_UTMP_SUPPORT is not set\n# CONFIG_BUSYBOX_DEFAULT_WATCH is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_SHOW_THREADS is not set\n# CONFIG_BUSYBOX_DEFAULT_CHPST is not set\n# CONFIG_BUSYBOX_DEFAULT_SETUIDGID is not set\n# CONFIG_BUSYBOX_DEFAULT_ENVUIDGID is not set\n# CONFIG_BUSYBOX_DEFAULT_ENVDIR is not set\n# CONFIG_BUSYBOX_DEFAULT_SOFTLIMIT is not set\n# CONFIG_BUSYBOX_DEFAULT_RUNSV is not set\n# CONFIG_BUSYBOX_DEFAULT_RUNSVDIR is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_RUNSVDIR_LOG is not set\n# CONFIG_BUSYBOX_DEFAULT_SV is not set\nCONFIG_BUSYBOX_DEFAULT_SV_DEFAULT_SERVICE_DIR=\"\"\n# CONFIG_BUSYBOX_DEFAULT_SVC is not set\n# CONFIG_BUSYBOX_DEFAULT_SVOK is not set\n# CONFIG_BUSYBOX_DEFAULT_SVLOGD is not set\n# CONFIG_BUSYBOX_DEFAULT_CHCON is not set\n# CONFIG_BUSYBOX_DEFAULT_GETENFORCE is not set\n# CONFIG_BUSYBOX_DEFAULT_GETSEBOOL is not set\n# CONFIG_BUSYBOX_DEFAULT_LOAD_POLICY is not set\n# CONFIG_BUSYBOX_DEFAULT_MATCHPATHCON is not set\n# CONFIG_BUSYBOX_DEFAULT_RUNCON is not set\n# CONFIG_BUSYBOX_DEFAULT_SELINUXENABLED is not set\n# CONFIG_BUSYBOX_DEFAULT_SESTATUS is not set\n# CONFIG_BUSYBOX_DEFAULT_SETENFORCE is not set\n# CONFIG_BUSYBOX_DEFAULT_SETFILES is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_SETFILES_CHECK_OPTION is not set\n# CONFIG_BUSYBOX_DEFAULT_RESTORECON is not set\n# CONFIG_BUSYBOX_DEFAULT_SETSEBOOL is not set\nCONFIG_BUSYBOX_DEFAULT_SH_IS_ASH=y\n# CONFIG_BUSYBOX_DEFAULT_SH_IS_HUSH is not set\n# CONFIG_BUSYBOX_DEFAULT_SH_IS_NONE is not set\n# CONFIG_BUSYBOX_DEFAULT_BASH_IS_ASH is not set\n# CONFIG_BUSYBOX_DEFAULT_BASH_IS_HUSH is not set\nCONFIG_BUSYBOX_DEFAULT_BASH_IS_NONE=y\nCONFIG_BUSYBOX_DEFAULT_SHELL_ASH=y\nCONFIG_BUSYBOX_DEFAULT_ASH=y\n# CONFIG_BUSYBOX_DEFAULT_ASH_OPTIMIZE_FOR_SIZE is not set\nCONFIG_BUSYBOX_DEFAULT_ASH_INTERNAL_GLOB=y\nCONFIG_BUSYBOX_DEFAULT_ASH_BASH_COMPAT=y\n# CONFIG_BUSYBOX_DEFAULT_ASH_BASH_SOURCE_CURDIR is not set\n# CONFIG_BUSYBOX_DEFAULT_ASH_BASH_NOT_FOUND_HOOK is not set\nCONFIG_BUSYBOX_DEFAULT_ASH_JOB_CONTROL=y\nCONFIG_BUSYBOX_DEFAULT_ASH_ALIAS=y\n# CONFIG_BUSYBOX_DEFAULT_ASH_RANDOM_SUPPORT is not set\nCONFIG_BUSYBOX_DEFAULT_ASH_EXPAND_PRMT=y\n# CONFIG_BUSYBOX_DEFAULT_ASH_IDLE_TIMEOUT is not set\n# CONFIG_BUSYBOX_DEFAULT_ASH_MAIL is not set\nCONFIG_BUSYBOX_DEFAULT_ASH_ECHO=y\nCONFIG_BUSYBOX_DEFAULT_ASH_PRINTF=y\nCONFIG_BUSYBOX_DEFAULT_ASH_TEST=y\n# CONFIG_BUSYBOX_DEFAULT_ASH_HELP is not set\nCONFIG_BUSYBOX_DEFAULT_ASH_GETOPTS=y\nCONFIG_BUSYBOX_DEFAULT_ASH_CMDCMD=y\n# CONFIG_BUSYBOX_DEFAULT_CTTYHACK is not set\n# CONFIG_BUSYBOX_DEFAULT_HUSH is not set\n# CONFIG_BUSYBOX_DEFAULT_SHELL_HUSH is not set\n# CONFIG_BUSYBOX_DEFAULT_HUSH_BASH_COMPAT is not set\n# CONFIG_BUSYBOX_DEFAULT_HUSH_BRACE_EXPANSION is not set\n# CONFIG_BUSYBOX_DEFAULT_HUSH_BASH_SOURCE_CURDIR is not set\n# CONFIG_BUSYBOX_DEFAULT_HUSH_LINENO_VAR is not set\n# CONFIG_BUSYBOX_DEFAULT_HUSH_INTERACTIVE is not set\n# CONFIG_BUSYBOX_DEFAULT_HUSH_SAVEHISTORY is not set\n# CONFIG_BUSYBOX_DEFAULT_HUSH_JOB is not set\n# CONFIG_BUSYBOX_DEFAULT_HUSH_TICK is not set\n# CONFIG_BUSYBOX_DEFAULT_HUSH_IF is not set\n# CONFIG_BUSYBOX_DEFAULT_HUSH_LOOPS is not set\n# CONFIG_BUSYBOX_DEFAULT_HUSH_CASE is not set\n# CONFIG_BUSYBOX_DEFAULT_HUSH_FUNCTIONS is not set\n# CONFIG_BUSYBOX_DEFAULT_HUSH_LOCAL is not set\n# CONFIG_BUSYBOX_DEFAULT_HUSH_RANDOM_SUPPORT is not set\n# CONFIG_BUSYBOX_DEFAULT_HUSH_MODE_X is not set\n# CONFIG_BUSYBOX_DEFAULT_HUSH_ECHO is not set\n# CONFIG_BUSYBOX_DEFAULT_HUSH_PRINTF is not set\n# CONFIG_BUSYBOX_DEFAULT_HUSH_TEST is not set\n# CONFIG_BUSYBOX_DEFAULT_HUSH_HELP is not set\n# CONFIG_BUSYBOX_DEFAULT_HUSH_EXPORT is not set\n# CONFIG_BUSYBOX_DEFAULT_HUSH_EXPORT_N is not set\n# CONFIG_BUSYBOX_DEFAULT_HUSH_READONLY is not set\n# CONFIG_BUSYBOX_DEFAULT_HUSH_KILL is not set\n# CONFIG_BUSYBOX_DEFAULT_HUSH_WAIT is not set\n# CONFIG_BUSYBOX_DEFAULT_HUSH_COMMAND is not set\n# CONFIG_BUSYBOX_DEFAULT_HUSH_TRAP is not set\n# CONFIG_BUSYBOX_DEFAULT_HUSH_TYPE is not set\n# CONFIG_BUSYBOX_DEFAULT_HUSH_TIMES is not set\n# CONFIG_BUSYBOX_DEFAULT_HUSH_READ is not set\n# CONFIG_BUSYBOX_DEFAULT_HUSH_SET is not set\n# CONFIG_BUSYBOX_DEFAULT_HUSH_UNSET is not set\n# CONFIG_BUSYBOX_DEFAULT_HUSH_ULIMIT is not set\n# CONFIG_BUSYBOX_DEFAULT_HUSH_UMASK is not set\n# CONFIG_BUSYBOX_DEFAULT_HUSH_GETOPTS is not set\n# CONFIG_BUSYBOX_DEFAULT_HUSH_MEMLEAK is not set\nCONFIG_BUSYBOX_DEFAULT_FEATURE_SH_MATH=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_SH_MATH_64=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_SH_MATH_BASE is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_SH_EXTRA_QUIET is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_SH_STANDALONE is not set\nCONFIG_BUSYBOX_DEFAULT_FEATURE_SH_NOFORK=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_SH_READ_FRAC is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_SH_HISTFILESIZE is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_SH_EMBEDDED_SCRIPTS is not set\n# CONFIG_BUSYBOX_DEFAULT_KLOGD is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_KLOGD_KLOGCTL is not set\nCONFIG_BUSYBOX_DEFAULT_LOGGER=y\n# CONFIG_BUSYBOX_DEFAULT_LOGREAD is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_LOGREAD_REDUCED_LOCKING is not set\n# CONFIG_BUSYBOX_DEFAULT_SYSLOGD is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_ROTATE_LOGFILE is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_REMOTE_LOG is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_SYSLOGD_DUP is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_SYSLOGD_CFG is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_SYSLOGD_PRECISE_TIMESTAMPS is not set\nCONFIG_BUSYBOX_DEFAULT_FEATURE_SYSLOGD_READ_BUFFER_SIZE=0\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_IPC_SYSLOG is not set\nCONFIG_BUSYBOX_DEFAULT_FEATURE_IPC_SYSLOG_BUFFER_SIZE=0\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_KMSG_SYSLOG is not set\n# CONFIG_BUSYBOX_CONFIG_IP is not set\n# CONFIG_BUSYBOX_CONFIG_FEATURE_IP_LINK is not set\n# CONFIG_PACKAGE_busybox-selinux is not set\nCONFIG_PACKAGE_ca-bundle=y\nCONFIG_PACKAGE_ca-certificates=y\nCONFIG_PACKAGE_dnsmasq=y\n# CONFIG_PACKAGE_dnsmasq-dhcpv6 is not set\n# CONFIG_PACKAGE_dnsmasq-full is not set\nCONFIG_PACKAGE_dropbear=y\n\n#\n# Configuration\n#\nCONFIG_DROPBEAR_CURVE25519=y\n# CONFIG_DROPBEAR_ECC is not set\nCONFIG_DROPBEAR_ED25519=y\nCONFIG_DROPBEAR_CHACHA20POLY1305=y\n# CONFIG_DROPBEAR_ZLIB is not set\nCONFIG_DROPBEAR_DBCLIENT=y\nCONFIG_DROPBEAR_DBCLIENT_AGENTFORWARD=y\nCONFIG_DROPBEAR_SCP=y\n# CONFIG_DROPBEAR_ASKPASS is not set\nCONFIG_DROPBEAR_AGENTFORWARD=y\n# end of Configuration\n\n# CONFIG_PACKAGE_ead is not set\nCONFIG_PACKAGE_firewall=y\n# CONFIG_PACKAGE_firewall4 is not set\nCONFIG_PACKAGE_fstools=y\n# CONFIG_FSTOOLS_OVL_MOUNT_FULL_ACCESS_TIME is not set\n# CONFIG_FSTOOLS_OVL_MOUNT_COMPRESS_ZLIB is not set\nCONFIG_PACKAGE_fwtool=y\nCONFIG_PACKAGE_getrandom=y\nCONFIG_PACKAGE_jsonfilter=y\nCONFIG_PACKAGE_libatomic=y\nCONFIG_PACKAGE_libc=y\nCONFIG_PACKAGE_libgcc=y\n# CONFIG_PACKAGE_libgomp is not set\nCONFIG_PACKAGE_libpthread=y\nCONFIG_PACKAGE_librt=y\nCONFIG_PACKAGE_libstdcpp=y\nCONFIG_PACKAGE_logd=y\nCONFIG_PACKAGE_mtd=y\nCONFIG_PACKAGE_netifd=y\n# CONFIG_PACKAGE_nft-qos is not set\n# CONFIG_PACKAGE_om-watchdog is not set\nCONFIG_PACKAGE_openwrt-keyring=y\nCONFIG_PACKAGE_opkg=y\nCONFIG_PACKAGE_procd=y\n\n#\n# Configuration\n#\n# CONFIG_PROCD_SHOW_BOOT is not set\n# CONFIG_PROCD_ZRAM_TMPFS is not set\n# end of Configuration\n\nCONFIG_PACKAGE_procd-seccomp=y\n# CONFIG_PACKAGE_procd-selinux is not set\n# CONFIG_PACKAGE_procd-ujail is not set\n# CONFIG_PACKAGE_procd-ujail-console is not set\nCONFIG_PACKAGE_qos-scripts=y\n# CONFIG_PACKAGE_refpolicy is not set\nCONFIG_PACKAGE_resolveip=y\nCONFIG_PACKAGE_rpcd=y\nCONFIG_PACKAGE_rpcd-mod-file=y\nCONFIG_PACKAGE_rpcd-mod-iwinfo=y\n# CONFIG_PACKAGE_rpcd-mod-rpcsys is not set\n# CONFIG_PACKAGE_selinux-policy is not set\n# CONFIG_PACKAGE_snapshot-tool is not set\nCONFIG_PACKAGE_sqm-scripts=y\n# CONFIG_PACKAGE_sqm-scripts-extra is not set\n# CONFIG_PACKAGE_swconfig is not set\nCONFIG_PACKAGE_ubox=y\nCONFIG_PACKAGE_ubus=y\nCONFIG_PACKAGE_ubusd=y\n# CONFIG_PACKAGE_ucert is not set\n# CONFIG_PACKAGE_ucert-full is not set\nCONFIG_PACKAGE_uci=y\nCONFIG_PACKAGE_urandom-seed=y\nCONFIG_PACKAGE_urngd=y\nCONFIG_PACKAGE_usign=y\n# CONFIG_PACKAGE_uxc is not set\n# CONFIG_PACKAGE_wireless-tools is not set\n# CONFIG_PACKAGE_zram-swap is not set\n# end of Base system\n\n#\n# Administration\n#\n\n#\n# Zabbix\n#\n# CONFIG_PACKAGE_zabbix-agentd is not set\n\n#\n# SSL support\n#\n# CONFIG_ZABBIX_OPENSSL is not set\n# CONFIG_ZABBIX_GNUTLS is not set\nCONFIG_ZABBIX_NOSSL=y\n# CONFIG_PACKAGE_zabbix-extra-mac80211 is not set\n# CONFIG_PACKAGE_zabbix-extra-network is not set\n# CONFIG_PACKAGE_zabbix-extra-wifi is not set\n# CONFIG_PACKAGE_zabbix-get is not set\n# CONFIG_PACKAGE_zabbix-proxy is not set\n# CONFIG_PACKAGE_zabbix-sender is not set\n# CONFIG_PACKAGE_zabbix-server is not set\n\n#\n# Database Software\n#\n# CONFIG_ZABBIX_MYSQL is not set\nCONFIG_ZABBIX_POSTGRESQL=y\n# CONFIG_PACKAGE_zabbix-server-frontend is not set\n# end of Zabbix\n\n#\n# openwisp\n#\n# CONFIG_PACKAGE_openwisp-config-mbedtls is not set\n# CONFIG_PACKAGE_openwisp-config-nossl is not set\n# CONFIG_PACKAGE_openwisp-config-openssl is not set\n# CONFIG_PACKAGE_openwisp-config-wolfssl is not set\n# end of openwisp\n\n# CONFIG_PACKAGE_atop is not set\n# CONFIG_PACKAGE_backuppc is not set\n# CONFIG_PACKAGE_debian-archive-keyring is not set\n# CONFIG_PACKAGE_debootstrap is not set\n# CONFIG_PACKAGE_gkrellmd is not set\nCONFIG_PACKAGE_htop=y\n# CONFIG_HTOP_LMSENSORS is not set\n# CONFIG_PACKAGE_ipmitool is not set\n# CONFIG_PACKAGE_monit is not set\n# CONFIG_PACKAGE_monit-nossl is not set\n# CONFIG_PACKAGE_muninlite is not set\n# CONFIG_PACKAGE_netatop is not set\n# CONFIG_PACKAGE_netdata is not set\n# CONFIG_PACKAGE_nyx is not set\n# CONFIG_PACKAGE_rsyslog is not set\n# CONFIG_PACKAGE_schroot is not set\n\n#\n# Configuration\n#\n# CONFIG_SCHROOT_BTRFS is not set\n# CONFIG_SCHROOT_LOOPBACK is not set\n# CONFIG_SCHROOT_LVM is not set\n# CONFIG_SCHROOT_UUID is not set\n# end of Configuration\n\n# CONFIG_PACKAGE_sudo is not set\n# CONFIG_PACKAGE_syslog-ng is not set\n# end of Administration\n\n#\n# Boot Loaders\n#\nCONFIG_PACKAGE_arm-trusted-firmware-rk3328=y\nCONFIG_PACKAGE_arm-trusted-firmware-rockchip=y\nCONFIG_PACKAGE_u-boot-orangepi-r1-plus-lts-rk3328=y\n# end of Boot Loaders\n\n#\n# Development\n#\n\n#\n# Libraries\n#\n# CONFIG_PACKAGE_libncurses-dev is not set\n# CONFIG_PACKAGE_libxml2-dev is not set\n# CONFIG_PACKAGE_zlib-dev is not set\n# end of Libraries\n\n# CONFIG_PACKAGE_ar is not set\n# CONFIG_PACKAGE_autoconf is not set\n# CONFIG_PACKAGE_automake is not set\n# CONFIG_PACKAGE_binutils is not set\n# CONFIG_PACKAGE_delve is not set\n# CONFIG_PACKAGE_diffutils is not set\n# CONFIG_PACKAGE_gcc is not set\n# CONFIG_PACKAGE_gdb is not set\n# CONFIG_PACKAGE_gdbserver is not set\n# CONFIG_PACKAGE_gitlab-runner is not set\n# CONFIG_PACKAGE_libtool-bin is not set\n# CONFIG_PACKAGE_lpc21isp is not set\n# CONFIG_PACKAGE_lttng-tools is not set\n# CONFIG_PACKAGE_m4 is not set\n# CONFIG_PACKAGE_make is not set\n# CONFIG_PACKAGE_objdump is not set\n# CONFIG_PACKAGE_packr is not set\n# CONFIG_PACKAGE_patch is not set\n# CONFIG_PACKAGE_pkg-config is not set\n# CONFIG_PACKAGE_pkgconf is not set\n# CONFIG_PACKAGE_statik is not set\n# CONFIG_PACKAGE_trace-cmd is not set\n# CONFIG_PACKAGE_trace-cmd-extra is not set\n# CONFIG_PACKAGE_valgrind is not set\n# end of Development\n\n#\n# Extra packages\n#\n# CONFIG_PACKAGE_jose is not set\nCONFIG_PACKAGE_libiwinfo-data=y\n# CONFIG_PACKAGE_libjose is not set\n# CONFIG_PACKAGE_nginx is not set\n# CONFIG_PACKAGE_nginx-mod-luci-ssl is not set\n# CONFIG_PACKAGE_nginx-util is not set\n# CONFIG_PACKAGE_rclone-config is not set\n# CONFIG_PACKAGE_tang is not set\n# end of Extra packages\n\n#\n# Firmware\n#\n\n#\n# ath10k Board-Specific Overrides\n#\n# end of ath10k Board-Specific Overrides\n\n# CONFIG_PACKAGE_aircard-pcmcia-firmware is not set\n# CONFIG_PACKAGE_amdgpu-firmware is not set\n# CONFIG_PACKAGE_ar3k-firmware is not set\n# CONFIG_PACKAGE_ath10k-board-qca4019 is not set\n# CONFIG_PACKAGE_ath10k-board-qca9377 is not set\n# CONFIG_PACKAGE_ath10k-board-qca9887 is not set\n# CONFIG_PACKAGE_ath10k-board-qca9888 is not set\n# CONFIG_PACKAGE_ath10k-board-qca988x is not set\n# CONFIG_PACKAGE_ath10k-board-qca9984 is not set\n# CONFIG_PACKAGE_ath10k-board-qca99x0 is not set\n# CONFIG_PACKAGE_ath10k-board-qca99x0-2g is not set\n# CONFIG_PACKAGE_ath10k-board-qca99x0-5g is not set\n# CONFIG_PACKAGE_ath10k-firmware-qca4019 is not set\n# CONFIG_PACKAGE_ath10k-firmware-qca4019-ct is not set\n# CONFIG_PACKAGE_ath10k-firmware-qca4019-ct-full-htt is not set\n# CONFIG_PACKAGE_ath10k-firmware-qca4019-ct-htt is not set\n# CONFIG_PACKAGE_ath10k-firmware-qca6174 is not set\n# CONFIG_PACKAGE_ath10k-firmware-qca9377 is not set\n# CONFIG_PACKAGE_ath10k-firmware-qca9887 is not set\n# CONFIG_PACKAGE_ath10k-firmware-qca9887-ct is not set\n# CONFIG_PACKAGE_ath10k-firmware-qca9887-ct-full-htt is not set\n# CONFIG_PACKAGE_ath10k-firmware-qca9888 is not set\n# CONFIG_PACKAGE_ath10k-firmware-qca9888-ct is not set\n# CONFIG_PACKAGE_ath10k-firmware-qca9888-ct-full-htt is not set\n# CONFIG_PACKAGE_ath10k-firmware-qca9888-ct-htt is not set\n# CONFIG_PACKAGE_ath10k-firmware-qca988x is not set\n# CONFIG_PACKAGE_ath10k-firmware-qca988x-ct is not set\n# CONFIG_PACKAGE_ath10k-firmware-qca988x-ct-full-htt is not set\n# CONFIG_PACKAGE_ath10k-firmware-qca9984 is not set\n# CONFIG_PACKAGE_ath10k-firmware-qca9984-ct is not set\n# CONFIG_PACKAGE_ath10k-firmware-qca9984-ct-full-htt is not set\n# CONFIG_PACKAGE_ath10k-firmware-qca9984-ct-htt is not set\n# CONFIG_PACKAGE_ath10k-firmware-qca99x0 is not set\n# CONFIG_PACKAGE_ath10k-firmware-qca99x0-ct is not set\n# CONFIG_PACKAGE_ath10k-firmware-qca99x0-ct-full-htt is not set\n# CONFIG_PACKAGE_ath10k-firmware-qca99x0-ct-htt is not set\n# CONFIG_PACKAGE_ath6k-firmware is not set\n# CONFIG_PACKAGE_ath9k-htc-firmware is not set\n# CONFIG_PACKAGE_b43legacy-firmware is not set\n# CONFIG_PACKAGE_bnx2-firmware is not set\n# CONFIG_PACKAGE_bnx2x-firmware is not set\n# CONFIG_PACKAGE_brcmfmac-firmware-4329-sdio is not set\n# CONFIG_PACKAGE_brcmfmac-firmware-43430-sdio-rpi-3b is not set\n# CONFIG_PACKAGE_brcmfmac-firmware-43430-sdio-rpi-zero-w is not set\n# CONFIG_PACKAGE_brcmfmac-firmware-43430a0-sdio is not set\n# CONFIG_PACKAGE_brcmfmac-firmware-43455-sdio-rpi-3b-plus is not set\n# CONFIG_PACKAGE_brcmfmac-firmware-43455-sdio-rpi-4b is not set\n# CONFIG_PACKAGE_brcmfmac-firmware-43602a1-pcie is not set\n# CONFIG_PACKAGE_brcmfmac-firmware-4366b1-pcie is not set\n# CONFIG_PACKAGE_brcmfmac-firmware-4366c0-pcie is not set\n# CONFIG_PACKAGE_brcmfmac-firmware-usb is not set\n# CONFIG_PACKAGE_brcmsmac-firmware is not set\n# CONFIG_PACKAGE_carl9170-firmware is not set\n# CONFIG_PACKAGE_cypress-firmware-43012-sdio is not set\n# CONFIG_PACKAGE_cypress-firmware-43340-sdio is not set\n# CONFIG_PACKAGE_cypress-firmware-43362-sdio is not set\n# CONFIG_PACKAGE_cypress-firmware-4339-sdio is not set\n# CONFIG_PACKAGE_cypress-firmware-43430-sdio is not set\n# CONFIG_PACKAGE_cypress-firmware-43455-sdio is not set\n# CONFIG_PACKAGE_cypress-firmware-4354-sdio is not set\n# CONFIG_PACKAGE_cypress-firmware-4356-pcie is not set\n# CONFIG_PACKAGE_cypress-firmware-4356-sdio is not set\n# CONFIG_PACKAGE_cypress-firmware-43570-pcie is not set\n# CONFIG_PACKAGE_cypress-firmware-4359-pcie is not set\n# CONFIG_PACKAGE_cypress-firmware-4359-sdio is not set\n# CONFIG_PACKAGE_cypress-firmware-4373-sdio is not set\n# CONFIG_PACKAGE_cypress-firmware-4373-usb is not set\n# CONFIG_PACKAGE_cypress-firmware-54591-pcie is not set\n# CONFIG_PACKAGE_cypress-firmware-89459-pcie is not set\n# CONFIG_PACKAGE_e100-firmware is not set\n# CONFIG_PACKAGE_edgeport-firmware is not set\n# CONFIG_PACKAGE_eip197-mini-firmware is not set\n# CONFIG_PACKAGE_ibt-firmware is not set\n# CONFIG_PACKAGE_iwl3945-firmware is not set\n# CONFIG_PACKAGE_iwl4965-firmware is not set\n# CONFIG_PACKAGE_iwlwifi-firmware-ax200 is not set\n# CONFIG_PACKAGE_iwlwifi-firmware-iwl100 is not set\n# CONFIG_PACKAGE_iwlwifi-firmware-iwl1000 is not set\n# CONFIG_PACKAGE_iwlwifi-firmware-iwl105 is not set\n# CONFIG_PACKAGE_iwlwifi-firmware-iwl135 is not set\n# CONFIG_PACKAGE_iwlwifi-firmware-iwl2000 is not set\n# CONFIG_PACKAGE_iwlwifi-firmware-iwl2030 is not set\n# CONFIG_PACKAGE_iwlwifi-firmware-iwl3160 is not set\n# CONFIG_PACKAGE_iwlwifi-firmware-iwl3168 is not set\n# CONFIG_PACKAGE_iwlwifi-firmware-iwl5000 is not set\n# CONFIG_PACKAGE_iwlwifi-firmware-iwl5150 is not set\n# CONFIG_PACKAGE_iwlwifi-firmware-iwl6000g2 is not set\n# CONFIG_PACKAGE_iwlwifi-firmware-iwl6000g2a is not set\n# CONFIG_PACKAGE_iwlwifi-firmware-iwl6000g2b is not set\n# CONFIG_PACKAGE_iwlwifi-firmware-iwl6050 is not set\n# CONFIG_PACKAGE_iwlwifi-firmware-iwl7260 is not set\n# CONFIG_PACKAGE_iwlwifi-firmware-iwl7265 is not set\n# CONFIG_PACKAGE_iwlwifi-firmware-iwl7265d is not set\n# CONFIG_PACKAGE_iwlwifi-firmware-iwl8260c is not set\n# CONFIG_PACKAGE_iwlwifi-firmware-iwl8265 is not set\n# CONFIG_PACKAGE_iwlwifi-firmware-iwl9000 is not set\n# CONFIG_PACKAGE_iwlwifi-firmware-iwl9260 is not set\n# CONFIG_PACKAGE_libertas-sdio-firmware is not set\n# CONFIG_PACKAGE_libertas-spi-firmware is not set\n# CONFIG_PACKAGE_libertas-usb-firmware is not set\n# CONFIG_PACKAGE_mt7601u-firmware is not set\n# CONFIG_PACKAGE_mt7622bt-firmware is not set\n# CONFIG_PACKAGE_mwifiex-pcie-firmware is not set\n# CONFIG_PACKAGE_mwifiex-sdio-firmware is not set\n# CONFIG_PACKAGE_mwl8k-firmware is not set\n# CONFIG_PACKAGE_p54-pci-firmware is not set\n# CONFIG_PACKAGE_p54-spi-firmware is not set\n# CONFIG_PACKAGE_p54-usb-firmware is not set\n# CONFIG_PACKAGE_prism54-firmware is not set\n# CONFIG_PACKAGE_r8169-firmware is not set\n# CONFIG_PACKAGE_radeon-firmware is not set\n# CONFIG_PACKAGE_rs9113-firmware is not set\n# CONFIG_PACKAGE_rt2800-pci-firmware is not set\n# CONFIG_PACKAGE_rt2800-usb-firmware is not set\n# CONFIG_PACKAGE_rt61-pci-firmware is not set\n# CONFIG_PACKAGE_rt73-usb-firmware is not set\nCONFIG_PACKAGE_rtl8188eu-firmware=y\n# CONFIG_PACKAGE_rtl8192ce-firmware is not set\n# CONFIG_PACKAGE_rtl8192cu-firmware is not set\n# CONFIG_PACKAGE_rtl8192de-firmware is not set\n# CONFIG_PACKAGE_rtl8192eu-firmware is not set\n# CONFIG_PACKAGE_rtl8192se-firmware is not set\n# CONFIG_PACKAGE_rtl8192su-firmware is not set\nCONFIG_PACKAGE_rtl8723au-firmware=y\n# CONFIG_PACKAGE_rtl8723bs-firmware is not set\nCONFIG_PACKAGE_rtl8723bu-firmware=y\nCONFIG_PACKAGE_rtl8821ae-firmware=y\n# CONFIG_PACKAGE_rtl8822be-firmware is not set\n# CONFIG_PACKAGE_rtl8822ce-firmware is not set\n# CONFIG_PACKAGE_ti-3410-firmware is not set\n# CONFIG_PACKAGE_ti-5052-firmware is not set\n# CONFIG_PACKAGE_wil6210-firmware is not set\nCONFIG_PACKAGE_wireless-regdb=y\n# CONFIG_PACKAGE_wl12xx-firmware is not set\n# CONFIG_PACKAGE_wl18xx-firmware is not set\n# end of Firmware\n\n#\n# Fonts\n#\n\n#\n# DejaVu\n#\n# CONFIG_PACKAGE_dejavu-fonts-ttf-DejaVuMathTeXGyre is not set\n# CONFIG_PACKAGE_dejavu-fonts-ttf-DejaVuSans is not set\n# CONFIG_PACKAGE_dejavu-fonts-ttf-DejaVuSans-Bold is not set\n# CONFIG_PACKAGE_dejavu-fonts-ttf-DejaVuSans-BoldOblique is not set\n# CONFIG_PACKAGE_dejavu-fonts-ttf-DejaVuSans-ExtraLight is not set\n# CONFIG_PACKAGE_dejavu-fonts-ttf-DejaVuSans-Oblique is not set\n# CONFIG_PACKAGE_dejavu-fonts-ttf-DejaVuSansCondensed is not set\n# CONFIG_PACKAGE_dejavu-fonts-ttf-DejaVuSansCondensed-Bold is not set\n# CONFIG_PACKAGE_dejavu-fonts-ttf-DejaVuSansCondensed-BoldOblique is not set\n# CONFIG_PACKAGE_dejavu-fonts-ttf-DejaVuSansCondensed-Oblique is not set\n# CONFIG_PACKAGE_dejavu-fonts-ttf-DejaVuSansMono is not set\n# CONFIG_PACKAGE_dejavu-fonts-ttf-DejaVuSansMono-Bold is not set\n# CONFIG_PACKAGE_dejavu-fonts-ttf-DejaVuSansMono-BoldOblique is not set\n# CONFIG_PACKAGE_dejavu-fonts-ttf-DejaVuSansMono-Oblique is not set\n# CONFIG_PACKAGE_dejavu-fonts-ttf-DejaVuSerif is not set\n# CONFIG_PACKAGE_dejavu-fonts-ttf-DejaVuSerif-Bold is not set\n# CONFIG_PACKAGE_dejavu-fonts-ttf-DejaVuSerif-BoldItalic is not set\n# CONFIG_PACKAGE_dejavu-fonts-ttf-DejaVuSerif-Italic is not set\n# CONFIG_PACKAGE_dejavu-fonts-ttf-DejaVuSerifCondensed is not set\n# CONFIG_PACKAGE_dejavu-fonts-ttf-DejaVuSerifCondensed-Bold is not set\n# CONFIG_PACKAGE_dejavu-fonts-ttf-DejaVuSerifCondensed-BoldItalic is not set\n# CONFIG_PACKAGE_dejavu-fonts-ttf-DejaVuSerifCondensed-Italic is not set\n# end of DejaVu\n# end of Fonts\n\n#\n# Kernel\n#\n\n#\n# Kernel modules\n#\n\n#\n# Block Devices\n#\n# CONFIG_PACKAGE_kmod-aoe is not set\n# CONFIG_PACKAGE_kmod-ata-ahci is not set\n# CONFIG_PACKAGE_kmod-ata-artop is not set\n# CONFIG_PACKAGE_kmod-ata-core is not set\n# CONFIG_PACKAGE_kmod-ata-marvell-sata is not set\n# CONFIG_PACKAGE_kmod-ata-nvidia-sata is not set\n# CONFIG_PACKAGE_kmod-ata-pdc202xx-old is not set\n# CONFIG_PACKAGE_kmod-ata-piix is not set\n# CONFIG_PACKAGE_kmod-ata-sil is not set\n# CONFIG_PACKAGE_kmod-ata-sil24 is not set\n# CONFIG_PACKAGE_kmod-ata-via-sata is not set\n# CONFIG_PACKAGE_kmod-block2mtd is not set\nCONFIG_PACKAGE_kmod-dax=y\nCONFIG_PACKAGE_kmod-dm=y\n# CONFIG_PACKAGE_kmod-dm-raid is not set\n# CONFIG_PACKAGE_kmod-iosched-bfq is not set\n# CONFIG_PACKAGE_kmod-iscsi-initiator is not set\n# CONFIG_PACKAGE_kmod-loop is not set\n# CONFIG_PACKAGE_kmod-md-mod is not set\n# CONFIG_PACKAGE_kmod-nbd is not set\n# CONFIG_PACKAGE_kmod-scsi-cdrom is not set\n# CONFIG_PACKAGE_kmod-scsi-core is not set\n# CONFIG_PACKAGE_kmod-scsi-generic is not set\n# CONFIG_PACKAGE_kmod-scsi-tape is not set\n# end of Block Devices\n\n#\n# CAN Support\n#\n# CONFIG_PACKAGE_kmod-can is not set\n# end of CAN Support\n\n#\n# Cryptographic API modules\n#\nCONFIG_PACKAGE_kmod-crypto-acompress=y\nCONFIG_PACKAGE_kmod-crypto-aead=y\n# CONFIG_PACKAGE_kmod-crypto-arc4 is not set\n# CONFIG_PACKAGE_kmod-crypto-authenc is not set\nCONFIG_PACKAGE_kmod-crypto-cbc=y\nCONFIG_PACKAGE_kmod-crypto-ccm=y\nCONFIG_PACKAGE_kmod-crypto-cmac=y\nCONFIG_PACKAGE_kmod-crypto-crc32c=y\nCONFIG_PACKAGE_kmod-crypto-ctr=y\n# CONFIG_PACKAGE_kmod-crypto-cts is not set\n# CONFIG_PACKAGE_kmod-crypto-deflate is not set\n# CONFIG_PACKAGE_kmod-crypto-des is not set\n# CONFIG_PACKAGE_kmod-crypto-ecb is not set\n# CONFIG_PACKAGE_kmod-crypto-ecdh is not set\n# CONFIG_PACKAGE_kmod-crypto-echainiv is not set\n# CONFIG_PACKAGE_kmod-crypto-fcrypt is not set\nCONFIG_PACKAGE_kmod-crypto-gcm=y\nCONFIG_PACKAGE_kmod-crypto-gf128=y\nCONFIG_PACKAGE_kmod-crypto-ghash=y\nCONFIG_PACKAGE_kmod-crypto-hash=y\nCONFIG_PACKAGE_kmod-crypto-hmac=y\n# CONFIG_PACKAGE_kmod-crypto-hw-hifn-795x is not set\n# CONFIG_PACKAGE_kmod-crypto-hw-padlock is not set\n# CONFIG_PACKAGE_kmod-crypto-kpp is not set\nCONFIG_PACKAGE_kmod-crypto-lib-blake2s=y\nCONFIG_PACKAGE_kmod-crypto-lib-chacha20=y\nCONFIG_PACKAGE_kmod-crypto-lib-chacha20poly1305=y\nCONFIG_PACKAGE_kmod-crypto-lib-curve25519=y\nCONFIG_PACKAGE_kmod-crypto-lib-poly1305=y\nCONFIG_PACKAGE_kmod-crypto-manager=y\n# CONFIG_PACKAGE_kmod-crypto-md4 is not set\n# CONFIG_PACKAGE_kmod-crypto-md5 is not set\n# CONFIG_PACKAGE_kmod-crypto-michael-mic is not set\n# CONFIG_PACKAGE_kmod-crypto-misc is not set\nCONFIG_PACKAGE_kmod-crypto-null=y\n# CONFIG_PACKAGE_kmod-crypto-pcbc is not set\n# CONFIG_PACKAGE_kmod-crypto-rmd160 is not set\nCONFIG_PACKAGE_kmod-crypto-rng=y\nCONFIG_PACKAGE_kmod-crypto-seqiv=y\nCONFIG_PACKAGE_kmod-crypto-sha1=y\nCONFIG_PACKAGE_kmod-crypto-sha256=y\n# CONFIG_PACKAGE_kmod-crypto-sha512 is not set\n# CONFIG_PACKAGE_kmod-crypto-test is not set\n# CONFIG_PACKAGE_kmod-crypto-user is not set\n# CONFIG_PACKAGE_kmod-crypto-xcbc is not set\n# CONFIG_PACKAGE_kmod-crypto-xts is not set\n# CONFIG_PACKAGE_kmod-cryptodev is not set\n# end of Cryptographic API modules\n\n#\n# Filesystems\n#\n# CONFIG_PACKAGE_kmod-fs-afs is not set\n# CONFIG_PACKAGE_kmod-fs-antfs is not set\n# CONFIG_PACKAGE_kmod-fs-autofs4 is not set\nCONFIG_PACKAGE_kmod-fs-btrfs=y\n# CONFIG_PACKAGE_kmod-fs-cifs is not set\n# CONFIG_PACKAGE_kmod-fs-configfs is not set\n# CONFIG_PACKAGE_kmod-fs-cramfs is not set\n# CONFIG_PACKAGE_kmod-fs-exfat is not set\n# CONFIG_PACKAGE_kmod-fs-exportfs is not set\nCONFIG_PACKAGE_kmod-fs-ext4=y\n# CONFIG_PACKAGE_kmod-fs-f2fs is not set\n# CONFIG_PACKAGE_kmod-fs-fscache is not set\n# CONFIG_PACKAGE_kmod-fs-hfs is not set\n# CONFIG_PACKAGE_kmod-fs-hfsplus is not set\n# CONFIG_PACKAGE_kmod-fs-isofs is not set\n# CONFIG_PACKAGE_kmod-fs-jfs is not set\n# CONFIG_PACKAGE_kmod-fs-ksmbd is not set\n# CONFIG_PACKAGE_kmod-fs-minix is not set\n# CONFIG_PACKAGE_kmod-fs-msdos is not set\n# CONFIG_PACKAGE_kmod-fs-nfs is not set\n# CONFIG_PACKAGE_kmod-fs-nfs-common is not set\n# CONFIG_PACKAGE_kmod-fs-nfs-common-rpcsec is not set\n# CONFIG_PACKAGE_kmod-fs-nfs-v3 is not set\n# CONFIG_PACKAGE_kmod-fs-nfs-v4 is not set\n# CONFIG_PACKAGE_kmod-fs-nfsd is not set\n# CONFIG_PACKAGE_kmod-fs-ntfs is not set\n# CONFIG_PACKAGE_kmod-fs-reiserfs is not set\n# CONFIG_PACKAGE_kmod-fs-squashfs is not set\n# CONFIG_PACKAGE_kmod-fs-udf is not set\nCONFIG_PACKAGE_kmod-fs-vfat=y\n# CONFIG_PACKAGE_kmod-fs-xfs is not set\n# CONFIG_PACKAGE_kmod-fuse is not set\n# end of Filesystems\n\n#\n# FireWire support\n#\n# CONFIG_PACKAGE_kmod-firewire is not set\n# end of FireWire support\n\n#\n# Hardware Monitoring Support\n#\n# CONFIG_PACKAGE_kmod-gl-mifi-mcu is not set\n# CONFIG_PACKAGE_kmod-hwmon-ad7418 is not set\n# CONFIG_PACKAGE_kmod-hwmon-adcxx is not set\n# CONFIG_PACKAGE_kmod-hwmon-adt7410 is not set\n# CONFIG_PACKAGE_kmod-hwmon-adt7475 is not set\n# CONFIG_PACKAGE_kmod-hwmon-core is not set\n# CONFIG_PACKAGE_kmod-hwmon-dme1737 is not set\n# CONFIG_PACKAGE_kmod-hwmon-drivetemp is not set\n# CONFIG_PACKAGE_kmod-hwmon-gpiofan is not set\n# CONFIG_PACKAGE_kmod-hwmon-ina209 is not set\n# CONFIG_PACKAGE_kmod-hwmon-ina2xx is not set\n# CONFIG_PACKAGE_kmod-hwmon-it87 is not set\n# CONFIG_PACKAGE_kmod-hwmon-lm63 is not set\n# CONFIG_PACKAGE_kmod-hwmon-lm75 is not set\n# CONFIG_PACKAGE_kmod-hwmon-lm77 is not set\n# CONFIG_PACKAGE_kmod-hwmon-lm85 is not set\n# CONFIG_PACKAGE_kmod-hwmon-lm90 is not set\n# CONFIG_PACKAGE_kmod-hwmon-lm92 is not set\n# CONFIG_PACKAGE_kmod-hwmon-lm95241 is not set\n# CONFIG_PACKAGE_kmod-hwmon-ltc4151 is not set\n# CONFIG_PACKAGE_kmod-hwmon-mcp3021 is not set\n# CONFIG_PACKAGE_kmod-hwmon-pwmfan is not set\n# CONFIG_PACKAGE_kmod-hwmon-sch5627 is not set\n# CONFIG_PACKAGE_kmod-hwmon-sht21 is not set\n# CONFIG_PACKAGE_kmod-hwmon-tmp102 is not set\n# CONFIG_PACKAGE_kmod-hwmon-tmp103 is not set\n# CONFIG_PACKAGE_kmod-hwmon-tmp421 is not set\n# CONFIG_PACKAGE_kmod-hwmon-vid is not set\n# CONFIG_PACKAGE_kmod-hwmon-w83793 is not set\n# CONFIG_PACKAGE_kmod-pmbus-core is not set\n# CONFIG_PACKAGE_kmod-pmbus-zl6100 is not set\n# end of Hardware Monitoring Support\n\n#\n# I2C support\n#\n# CONFIG_PACKAGE_kmod-i2c-algo-bit is not set\n# CONFIG_PACKAGE_kmod-i2c-algo-pca is not set\n# CONFIG_PACKAGE_kmod-i2c-algo-pcf is not set\n# CONFIG_PACKAGE_kmod-i2c-core is not set\n# CONFIG_PACKAGE_kmod-i2c-designware-pci is not set\n# CONFIG_PACKAGE_kmod-i2c-gpio is not set\n# CONFIG_PACKAGE_kmod-i2c-mux is not set\n# CONFIG_PACKAGE_kmod-i2c-mux-gpio is not set\n# CONFIG_PACKAGE_kmod-i2c-mux-pca9541 is not set\n# CONFIG_PACKAGE_kmod-i2c-mux-pca954x is not set\n# CONFIG_PACKAGE_kmod-i2c-pxa is not set\n# CONFIG_PACKAGE_kmod-i2c-smbus is not set\n# CONFIG_PACKAGE_kmod-i2c-tiny-usb is not set\n# end of I2C support\n\n#\n# Industrial I/O Modules\n#\n# CONFIG_PACKAGE_kmod-iio-ad799x is not set\n# CONFIG_PACKAGE_kmod-iio-ads1015 is not set\n# CONFIG_PACKAGE_kmod-iio-am2315 is not set\n# CONFIG_PACKAGE_kmod-iio-bh1750 is not set\n# CONFIG_PACKAGE_kmod-iio-bme680 is not set\n# CONFIG_PACKAGE_kmod-iio-bme680-i2c is not set\n# CONFIG_PACKAGE_kmod-iio-bme680-spi is not set\n# CONFIG_PACKAGE_kmod-iio-bmp280 is not set\n# CONFIG_PACKAGE_kmod-iio-bmp280-i2c is not set\n# CONFIG_PACKAGE_kmod-iio-bmp280-spi is not set\n# CONFIG_PACKAGE_kmod-iio-ccs811 is not set\n# CONFIG_PACKAGE_kmod-iio-core is not set\n# CONFIG_PACKAGE_kmod-iio-dht11 is not set\n# CONFIG_PACKAGE_kmod-iio-fxas21002c is not set\n# CONFIG_PACKAGE_kmod-iio-fxas21002c-i2c is not set\n# CONFIG_PACKAGE_kmod-iio-fxas21002c-spi is not set\n# CONFIG_PACKAGE_kmod-iio-fxos8700 is not set\n# CONFIG_PACKAGE_kmod-iio-fxos8700-i2c is not set\n# CONFIG_PACKAGE_kmod-iio-fxos8700-spi is not set\n# CONFIG_PACKAGE_kmod-iio-hmc5843 is not set\n# CONFIG_PACKAGE_kmod-iio-htu21 is not set\n# CONFIG_PACKAGE_kmod-iio-kfifo-buf is not set\n# CONFIG_PACKAGE_kmod-iio-lsm6dsx is not set\n# CONFIG_PACKAGE_kmod-iio-lsm6dsx-i2c is not set\n# CONFIG_PACKAGE_kmod-iio-lsm6dsx-spi is not set\n# CONFIG_PACKAGE_kmod-iio-si7020 is not set\n# CONFIG_PACKAGE_kmod-iio-sps30 is not set\n# CONFIG_PACKAGE_kmod-iio-st_accel is not set\n# CONFIG_PACKAGE_kmod-iio-st_accel-i2c is not set\n# CONFIG_PACKAGE_kmod-iio-st_accel-spi is not set\n# CONFIG_PACKAGE_kmod-iio-tsl4531 is not set\n# CONFIG_PACKAGE_kmod-industrialio-triggered-buffer is not set\n# end of Industrial I/O Modules\n\n#\n# Input modules\n#\n# CONFIG_PACKAGE_kmod-hid is not set\n# CONFIG_PACKAGE_kmod-hid-generic is not set\n# CONFIG_PACKAGE_kmod-input-core is not set\n# CONFIG_PACKAGE_kmod-input-evdev is not set\n# CONFIG_PACKAGE_kmod-input-gpio-encoder is not set\n# CONFIG_PACKAGE_kmod-input-gpio-keys is not set\n# CONFIG_PACKAGE_kmod-input-gpio-keys-polled is not set\n# CONFIG_PACKAGE_kmod-input-joydev is not set\n# CONFIG_PACKAGE_kmod-input-matrixkmap is not set\n# CONFIG_PACKAGE_kmod-input-polldev is not set\n# CONFIG_PACKAGE_kmod-input-touchscreen-ads7846 is not set\n# CONFIG_PACKAGE_kmod-input-uinput is not set\n# end of Input modules\n\n#\n# LED modules\n#\n# CONFIG_PACKAGE_kmod-input-leds is not set\n# CONFIG_PACKAGE_kmod-leds-gpio is not set\n# CONFIG_PACKAGE_kmod-leds-pca963x is not set\n# CONFIG_PACKAGE_kmod-leds-uleds is not set\n# CONFIG_PACKAGE_kmod-ledtrig-activity is not set\n# CONFIG_PACKAGE_kmod-ledtrig-audio is not set\n# CONFIG_PACKAGE_kmod-ledtrig-gpio is not set\n# CONFIG_PACKAGE_kmod-ledtrig-oneshot is not set\n# CONFIG_PACKAGE_kmod-ledtrig-pattern is not set\n# CONFIG_PACKAGE_kmod-ledtrig-transient is not set\n# end of LED modules\n\n#\n# Libraries\n#\n# CONFIG_PACKAGE_kmod-lib-cordic is not set\nCONFIG_PACKAGE_kmod-lib-crc-ccitt=y\n# CONFIG_PACKAGE_kmod-lib-crc-itu-t is not set\nCONFIG_PACKAGE_kmod-lib-crc16=y\nCONFIG_PACKAGE_kmod-lib-crc32c=y\n# CONFIG_PACKAGE_kmod-lib-crc7 is not set\n# CONFIG_PACKAGE_kmod-lib-crc8 is not set\n# CONFIG_PACKAGE_kmod-lib-lz4 is not set\nCONFIG_PACKAGE_kmod-lib-lzo=y\nCONFIG_PACKAGE_kmod-lib-raid6=y\n# CONFIG_PACKAGE_kmod-lib-textsearch is not set\nCONFIG_PACKAGE_kmod-lib-xor=y\nCONFIG_PACKAGE_kmod-lib-zlib-deflate=y\nCONFIG_PACKAGE_kmod-lib-zlib-inflate=y\nCONFIG_PACKAGE_kmod-lib-zstd=y\n# end of Libraries\n\n#\n# Native Language Support\n#\nCONFIG_PACKAGE_kmod-nls-base=y\n# CONFIG_PACKAGE_kmod-nls-cp1250 is not set\n# CONFIG_PACKAGE_kmod-nls-cp1251 is not set\nCONFIG_PACKAGE_kmod-nls-cp437=y\n# CONFIG_PACKAGE_kmod-nls-cp775 is not set\n# CONFIG_PACKAGE_kmod-nls-cp850 is not set\n# CONFIG_PACKAGE_kmod-nls-cp852 is not set\n# CONFIG_PACKAGE_kmod-nls-cp862 is not set\n# CONFIG_PACKAGE_kmod-nls-cp864 is not set\n# CONFIG_PACKAGE_kmod-nls-cp866 is not set\n# CONFIG_PACKAGE_kmod-nls-cp932 is not set\n# CONFIG_PACKAGE_kmod-nls-cp936 is not set\n# CONFIG_PACKAGE_kmod-nls-cp950 is not set\nCONFIG_PACKAGE_kmod-nls-iso8859-1=y\n# CONFIG_PACKAGE_kmod-nls-iso8859-13 is not set\n# CONFIG_PACKAGE_kmod-nls-iso8859-15 is not set\n# CONFIG_PACKAGE_kmod-nls-iso8859-2 is not set\n# CONFIG_PACKAGE_kmod-nls-iso8859-6 is not set\n# CONFIG_PACKAGE_kmod-nls-iso8859-8 is not set\n# CONFIG_PACKAGE_kmod-nls-koi8r is not set\nCONFIG_PACKAGE_kmod-nls-utf8=y\n# end of Native Language Support\n\n#\n# Netfilter Extensions\n#\n# CONFIG_PACKAGE_kmod-arptables is not set\nCONFIG_PACKAGE_kmod-br-netfilter=y\n# CONFIG_PACKAGE_kmod-ebtables is not set\n# CONFIG_PACKAGE_kmod-ebtables-ipv4 is not set\n# CONFIG_PACKAGE_kmod-ebtables-ipv6 is not set\n# CONFIG_PACKAGE_kmod-ebtables-watchers is not set\nCONFIG_PACKAGE_kmod-ip6tables=y\n# CONFIG_PACKAGE_kmod-ip6tables-extra is not set\n# CONFIG_PACKAGE_kmod-ipt-account is not set\n# CONFIG_PACKAGE_kmod-ipt-chaos is not set\n# CONFIG_PACKAGE_kmod-ipt-checksum is not set\n# CONFIG_PACKAGE_kmod-ipt-cluster is not set\n# CONFIG_PACKAGE_kmod-ipt-clusterip is not set\n# CONFIG_PACKAGE_kmod-ipt-compat-xtables is not set\n# CONFIG_PACKAGE_kmod-ipt-condition is not set\nCONFIG_PACKAGE_kmod-ipt-conntrack=y\nCONFIG_PACKAGE_kmod-ipt-conntrack-extra=y\n# CONFIG_PACKAGE_kmod-ipt-conntrack-label is not set\nCONFIG_PACKAGE_kmod-ipt-core=y\n# CONFIG_PACKAGE_kmod-ipt-debug is not set\n# CONFIG_PACKAGE_kmod-ipt-delude is not set\n# CONFIG_PACKAGE_kmod-ipt-dhcpmac is not set\n# CONFIG_PACKAGE_kmod-ipt-dnetmap is not set\nCONFIG_PACKAGE_kmod-ipt-extra=y\n# CONFIG_PACKAGE_kmod-ipt-filter is not set\n# CONFIG_PACKAGE_kmod-ipt-fuzzy is not set\n# CONFIG_PACKAGE_kmod-ipt-geoip is not set\n# CONFIG_PACKAGE_kmod-ipt-hashlimit is not set\n# CONFIG_PACKAGE_kmod-ipt-iface is not set\n# CONFIG_PACKAGE_kmod-ipt-ipmark is not set\nCONFIG_PACKAGE_kmod-ipt-ipopt=y\n# CONFIG_PACKAGE_kmod-ipt-ipp2p is not set\n# CONFIG_PACKAGE_kmod-ipt-iprange is not set\n# CONFIG_PACKAGE_kmod-ipt-ipsec is not set\nCONFIG_PACKAGE_kmod-ipt-ipset=y\n# CONFIG_PACKAGE_kmod-ipt-ipv4options is not set\n# CONFIG_PACKAGE_kmod-ipt-led is not set\n# CONFIG_PACKAGE_kmod-ipt-length2 is not set\n# CONFIG_PACKAGE_kmod-ipt-logmark is not set\n# CONFIG_PACKAGE_kmod-ipt-lscan is not set\n# CONFIG_PACKAGE_kmod-ipt-lua is not set\nCONFIG_PACKAGE_kmod-ipt-nat=y\n# CONFIG_PACKAGE_kmod-ipt-nat-extra is not set\n# CONFIG_PACKAGE_kmod-ipt-nat6 is not set\n# CONFIG_PACKAGE_kmod-ipt-nathelper-rtsp is not set\n# CONFIG_PACKAGE_kmod-ipt-nflog is not set\n# CONFIG_PACKAGE_kmod-ipt-nfqueue is not set\nCONFIG_PACKAGE_kmod-ipt-offload=y\n# CONFIG_PACKAGE_kmod-ipt-physdev is not set\n# CONFIG_PACKAGE_kmod-ipt-proto is not set\n# CONFIG_PACKAGE_kmod-ipt-psd is not set\n# CONFIG_PACKAGE_kmod-ipt-quota2 is not set\nCONFIG_PACKAGE_kmod-ipt-raw=y\n# CONFIG_PACKAGE_kmod-ipt-raw6 is not set\n# CONFIG_PACKAGE_kmod-ipt-rpfilter is not set\n# CONFIG_PACKAGE_kmod-ipt-rtpengine is not set\n# CONFIG_PACKAGE_kmod-ipt-sysrq is not set\n# CONFIG_PACKAGE_kmod-ipt-tarpit is not set\n# CONFIG_PACKAGE_kmod-ipt-tee is not set\nCONFIG_PACKAGE_kmod-ipt-tproxy=y\n# CONFIG_PACKAGE_kmod-ipt-u32 is not set\n# CONFIG_PACKAGE_kmod-ipt-ulog is not set\n# CONFIG_PACKAGE_kmod-netatop is not set\nCONFIG_PACKAGE_kmod-nf-conntrack=y\nCONFIG_PACKAGE_kmod-nf-conntrack-netlink=y\nCONFIG_PACKAGE_kmod-nf-conntrack6=y\nCONFIG_PACKAGE_kmod-nf-flow=y\nCONFIG_PACKAGE_kmod-nf-ipt=y\nCONFIG_PACKAGE_kmod-nf-ipt6=y\nCONFIG_PACKAGE_kmod-nf-ipvs=y\n# CONFIG_PACKAGE_kmod-nf-ipvs-ftp is not set\n# CONFIG_PACKAGE_kmod-nf-ipvs-sip is not set\nCONFIG_PACKAGE_kmod-nf-nat=y\n# CONFIG_PACKAGE_kmod-nf-nat6 is not set\n# CONFIG_PACKAGE_kmod-nf-nathelper is not set\n# CONFIG_PACKAGE_kmod-nf-nathelper-extra is not set\nCONFIG_PACKAGE_kmod-nf-reject=y\nCONFIG_PACKAGE_kmod-nf-reject6=y\nCONFIG_PACKAGE_kmod-nfnetlink=y\n# CONFIG_PACKAGE_kmod-nfnetlink-log is not set\n# CONFIG_PACKAGE_kmod-nfnetlink-queue is not set\n# CONFIG_PACKAGE_kmod-nft-arp is not set\n# CONFIG_PACKAGE_kmod-nft-bridge is not set\n# CONFIG_PACKAGE_kmod-nft-core is not set\n# CONFIG_PACKAGE_kmod-nft-fib is not set\n# CONFIG_PACKAGE_kmod-nft-nat is not set\n# CONFIG_PACKAGE_kmod-nft-nat6 is not set\n# CONFIG_PACKAGE_kmod-nft-netdev is not set\n# CONFIG_PACKAGE_kmod-nft-offload is not set\n# CONFIG_PACKAGE_kmod-nft-queue is not set\n# end of Netfilter Extensions\n\n#\n# Network Devices\n#\n# CONFIG_PACKAGE_kmod-3c59x is not set\n# CONFIG_PACKAGE_kmod-8139cp is not set\n# CONFIG_PACKAGE_kmod-8139too is not set\n# CONFIG_PACKAGE_kmod-alx is not set\n# CONFIG_PACKAGE_kmod-atl1 is not set\n# CONFIG_PACKAGE_kmod-atl1c is not set\n# CONFIG_PACKAGE_kmod-atl1e is not set\n# CONFIG_PACKAGE_kmod-atl2 is not set\n# CONFIG_PACKAGE_kmod-b44 is not set\n# CONFIG_PACKAGE_kmod-be2net is not set\n# CONFIG_PACKAGE_kmod-bnx2 is not set\n# CONFIG_PACKAGE_kmod-bnx2x is not set\n# CONFIG_PACKAGE_kmod-dm9000 is not set\n# CONFIG_PACKAGE_kmod-dummy is not set\n# CONFIG_PACKAGE_kmod-e100 is not set\n# CONFIG_PACKAGE_kmod-e1000 is not set\n# CONFIG_PACKAGE_kmod-e1000e is not set\n# CONFIG_PACKAGE_kmod-et131x is not set\n# CONFIG_PACKAGE_kmod-ethoc is not set\n# CONFIG_PACKAGE_kmod-forcedeth is not set\n# CONFIG_PACKAGE_kmod-hfcmulti is not set\n# CONFIG_PACKAGE_kmod-hfcpci is not set\n# CONFIG_PACKAGE_kmod-i40e is not set\n# CONFIG_PACKAGE_kmod-iavf is not set\nCONFIG_PACKAGE_kmod-ifb=y\n# CONFIG_PACKAGE_kmod-igb is not set\n# CONFIG_PACKAGE_kmod-igc is not set\n# CONFIG_PACKAGE_kmod-ipvlan is not set\n# CONFIG_PACKAGE_kmod-ixgbe is not set\n# CONFIG_PACKAGE_kmod-ixgbevf is not set\n# CONFIG_PACKAGE_kmod-libphy is not set\n# CONFIG_PACKAGE_kmod-macvlan is not set\n# CONFIG_PACKAGE_kmod-mdio-gpio is not set\nCONFIG_PACKAGE_kmod-mii=y\n# CONFIG_PACKAGE_kmod-mlx4-core is not set\n# CONFIG_PACKAGE_kmod-mlx5-core is not set\n# CONFIG_PACKAGE_kmod-natsemi is not set\n# CONFIG_PACKAGE_kmod-ne2k-pci is not set\n# CONFIG_PACKAGE_kmod-niu is not set\n# CONFIG_PACKAGE_kmod-of-mdio is not set\n# CONFIG_PACKAGE_kmod-pcnet32 is not set\n# CONFIG_PACKAGE_kmod-phy-bcm84881 is not set\n# CONFIG_PACKAGE_kmod-phy-broadcom is not set\n# CONFIG_PACKAGE_kmod-phy-realtek is not set\n# CONFIG_PACKAGE_kmod-phylink is not set\n# CONFIG_PACKAGE_kmod-qlcnic is not set\n# CONFIG_PACKAGE_kmod-r6040 is not set\n# CONFIG_PACKAGE_kmod-r8169 is not set\n# CONFIG_PACKAGE_kmod-sfc is not set\n# CONFIG_PACKAGE_kmod-sfc-falcon is not set\n# CONFIG_PACKAGE_kmod-sfp is not set\n# CONFIG_PACKAGE_kmod-siit is not set\n# CONFIG_PACKAGE_kmod-sis190 is not set\n# CONFIG_PACKAGE_kmod-sis900 is not set\n# CONFIG_PACKAGE_kmod-skge is not set\n# CONFIG_PACKAGE_kmod-sky2 is not set\n# CONFIG_PACKAGE_kmod-solos-pci is not set\n# CONFIG_PACKAGE_kmod-spi-ks8995 is not set\n# CONFIG_PACKAGE_kmod-swconfig is not set\n# CONFIG_PACKAGE_kmod-switch-bcm53xx is not set\n# CONFIG_PACKAGE_kmod-switch-bcm53xx-mdio is not set\n# CONFIG_PACKAGE_kmod-switch-ip17xx is not set\n# CONFIG_PACKAGE_kmod-switch-rtl8306 is not set\n# CONFIG_PACKAGE_kmod-switch-rtl8366-smi is not set\n# CONFIG_PACKAGE_kmod-switch-rtl8366rb is not set\n# CONFIG_PACKAGE_kmod-switch-rtl8366s is not set\n# CONFIG_PACKAGE_kmod-switch-rtl8367b is not set\n# CONFIG_PACKAGE_kmod-tg3 is not set\n# CONFIG_PACKAGE_kmod-tulip is not set\n# CONFIG_PACKAGE_kmod-via-rhine is not set\n# CONFIG_PACKAGE_kmod-via-velocity is not set\n# CONFIG_PACKAGE_kmod-vmxnet3 is not set\n# end of Network Devices\n\n#\n# Network Support\n#\n# CONFIG_PACKAGE_kmod-atm is not set\n# CONFIG_PACKAGE_kmod-ax25 is not set\n# CONFIG_PACKAGE_kmod-batman-adv is not set\n# CONFIG_PACKAGE_kmod-bonding is not set\n# CONFIG_PACKAGE_kmod-bpf-test is not set\n# CONFIG_PACKAGE_kmod-dnsresolver is not set\n# CONFIG_PACKAGE_kmod-fou is not set\n# CONFIG_PACKAGE_kmod-fou6 is not set\n# CONFIG_PACKAGE_kmod-geneve is not set\n# CONFIG_PACKAGE_kmod-gre is not set\n# CONFIG_PACKAGE_kmod-gre6 is not set\n# CONFIG_PACKAGE_kmod-ip6-tunnel is not set\n# CONFIG_PACKAGE_kmod-ipip is not set\n# CONFIG_PACKAGE_kmod-ipsec is not set\n# CONFIG_PACKAGE_kmod-iptunnel6 is not set\n# CONFIG_PACKAGE_kmod-isdn4linux is not set\n# CONFIG_PACKAGE_kmod-jool is not set\n# CONFIG_PACKAGE_kmod-l2tp is not set\n# CONFIG_PACKAGE_kmod-l2tp-eth is not set\n# CONFIG_PACKAGE_kmod-l2tp-ip is not set\n# CONFIG_PACKAGE_kmod-macremapper is not set\n# CONFIG_PACKAGE_kmod-macsec is not set\n# CONFIG_PACKAGE_kmod-mdio-netlink is not set\n# CONFIG_PACKAGE_kmod-misdn is not set\n# CONFIG_PACKAGE_kmod-mpls is not set\n# CONFIG_PACKAGE_kmod-nat46 is not set\n# CONFIG_PACKAGE_kmod-netem is not set\n# CONFIG_PACKAGE_kmod-netlink-diag is not set\n# CONFIG_PACKAGE_kmod-nlmon is not set\n# CONFIG_PACKAGE_kmod-nsh is not set\n# CONFIG_PACKAGE_kmod-openvswitch is not set\n# CONFIG_PACKAGE_kmod-openvswitch-geneve is not set\n# CONFIG_PACKAGE_kmod-openvswitch-gre is not set\n# CONFIG_PACKAGE_kmod-openvswitch-vxlan is not set\n# CONFIG_PACKAGE_kmod-ovpn-dco is not set\n# CONFIG_PACKAGE_kmod-pf-ring is not set\n# CONFIG_PACKAGE_kmod-pktgen is not set\nCONFIG_PACKAGE_kmod-ppp=y\n# CONFIG_PACKAGE_kmod-mppe is not set\n# CONFIG_PACKAGE_kmod-ppp-synctty is not set\n# CONFIG_PACKAGE_kmod-pppoa is not set\nCONFIG_PACKAGE_kmod-pppoe=y\n# CONFIG_PACKAGE_kmod-pppol2tp is not set\nCONFIG_PACKAGE_kmod-pppox=y\n# CONFIG_PACKAGE_kmod-pptp is not set\n# CONFIG_PACKAGE_kmod-sched is not set\n# CONFIG_PACKAGE_kmod-sched-act-vlan is not set\n# CONFIG_PACKAGE_kmod-sched-bpf is not set\nCONFIG_PACKAGE_kmod-sched-cake=y\nCONFIG_PACKAGE_kmod-sched-connmark=y\nCONFIG_PACKAGE_kmod-sched-core=y\n# CONFIG_PACKAGE_kmod-sched-ctinfo is not set\n# CONFIG_PACKAGE_kmod-sched-flower is not set\n# CONFIG_PACKAGE_kmod-sched-ipset is not set\n# CONFIG_PACKAGE_kmod-sched-mqprio is not set\n# CONFIG_PACKAGE_kmod-sctp is not set\n# CONFIG_PACKAGE_kmod-sit is not set\nCONFIG_PACKAGE_kmod-slhc=y\n# CONFIG_PACKAGE_kmod-slip is not set\n# CONFIG_PACKAGE_kmod-tcp-bbr is not set\n# CONFIG_PACKAGE_kmod-tcp-hybla is not set\n# CONFIG_PACKAGE_kmod-trelay is not set\nCONFIG_PACKAGE_kmod-tun=y\nCONFIG_PACKAGE_kmod-udptunnel4=y\nCONFIG_PACKAGE_kmod-udptunnel6=y\nCONFIG_PACKAGE_kmod-veth=y\n# CONFIG_PACKAGE_kmod-vxlan is not set\nCONFIG_PACKAGE_kmod-wireguard=y\n# end of Network Support\n\n#\n# Other modules\n#\n# CONFIG_PACKAGE_kmod-6lowpan is not set\n# CONFIG_PACKAGE_kmod-ath3k is not set\n# CONFIG_PACKAGE_kmod-bcma is not set\n# CONFIG_PACKAGE_kmod-bluetooth is not set\n# CONFIG_PACKAGE_kmod-bluetooth-6lowpan is not set\n# CONFIG_PACKAGE_kmod-btmrvl is not set\n# CONFIG_PACKAGE_kmod-button-hotplug is not set\n# CONFIG_PACKAGE_kmod-echo is not set\n# CONFIG_PACKAGE_kmod-eeprom-93cx6 is not set\n# CONFIG_PACKAGE_kmod-eeprom-at24 is not set\n# CONFIG_PACKAGE_kmod-eeprom-at25 is not set\n# CONFIG_PACKAGE_kmod-gpio-beeper is not set\nCONFIG_PACKAGE_kmod-gpio-button-hotplug=y\n# CONFIG_PACKAGE_kmod-gpio-mcp23s08 is not set\n# CONFIG_PACKAGE_kmod-gpio-nxp-74hc164 is not set\n# CONFIG_PACKAGE_kmod-gpio-pca953x is not set\n# CONFIG_PACKAGE_kmod-gpio-pcf857x is not set\nCONFIG_PACKAGE_kmod-ikconfig=y\n# CONFIG_PACKAGE_kmod-it87-wdt is not set\n# CONFIG_PACKAGE_kmod-itco-wdt is not set\nCONFIG_PACKAGE_kmod-keys-encrypted=y\nCONFIG_PACKAGE_kmod-keys-trusted=y\n# CONFIG_PACKAGE_kmod-lp is not set\n# CONFIG_PACKAGE_kmod-mmc is not set\n# CONFIG_PACKAGE_kmod-mtd-rw is not set\n# CONFIG_PACKAGE_kmod-mtdoops is not set\n# CONFIG_PACKAGE_kmod-mtdram is not set\n# CONFIG_PACKAGE_kmod-mtdtests is not set\n# CONFIG_PACKAGE_kmod-parport-pc is not set\n# CONFIG_PACKAGE_kmod-ppdev is not set\n# CONFIG_PACKAGE_kmod-pps is not set\n# CONFIG_PACKAGE_kmod-pps-gpio is not set\n# CONFIG_PACKAGE_kmod-pps-ldisc is not set\n# CONFIG_PACKAGE_kmod-ptp is not set\nCONFIG_PACKAGE_kmod-random-core=y\n# CONFIG_PACKAGE_kmod-rtc-ds1307 is not set\n# CONFIG_PACKAGE_kmod-rtc-ds1374 is not set\n# CONFIG_PACKAGE_kmod-rtc-ds1672 is not set\n# CONFIG_PACKAGE_kmod-rtc-em3027 is not set\n# CONFIG_PACKAGE_kmod-rtc-isl1208 is not set\n# CONFIG_PACKAGE_kmod-rtc-pcf2123 is not set\n# CONFIG_PACKAGE_kmod-rtc-pcf2127 is not set\n# CONFIG_PACKAGE_kmod-rtc-pcf8563 is not set\n# CONFIG_PACKAGE_kmod-rtc-pt7c4338 is not set\n# CONFIG_PACKAGE_kmod-rtc-rs5c372a is not set\n# CONFIG_PACKAGE_kmod-rtc-rx8025 is not set\n# CONFIG_PACKAGE_kmod-rtc-s35390a is not set\n# CONFIG_PACKAGE_kmod-sdhci is not set\n# CONFIG_PACKAGE_kmod-serial-8250 is not set\n# CONFIG_PACKAGE_kmod-serial-8250-exar is not set\n# CONFIG_PACKAGE_kmod-softdog is not set\n# CONFIG_PACKAGE_kmod-ssb is not set\nCONFIG_PACKAGE_kmod-tpm=y\n# CONFIG_PACKAGE_kmod-tpm-i2c-atmel is not set\n# CONFIG_PACKAGE_kmod-tpm-i2c-infineon is not set\n# CONFIG_PACKAGE_kmod-w83627hf-wdt is not set\n# CONFIG_PACKAGE_kmod-zram is not set\n# end of Other modules\n\n#\n# PCMCIA support\n#\n# end of PCMCIA support\n\n#\n# SPI Support\n#\n# CONFIG_PACKAGE_kmod-mmc-spi is not set\n# CONFIG_PACKAGE_kmod-spi-bitbang is not set\n# CONFIG_PACKAGE_kmod-spi-dev is not set\n# CONFIG_PACKAGE_kmod-spi-gpio is not set\n# end of SPI Support\n\n#\n# Sound Support\n#\n# CONFIG_PACKAGE_kmod-sound-core is not set\n# end of Sound Support\n\n#\n# USB Support\n#\n# CONFIG_PACKAGE_kmod-chaoskey is not set\n# CONFIG_PACKAGE_kmod-usb-acm is not set\n# CONFIG_PACKAGE_kmod-usb-atm is not set\n# CONFIG_PACKAGE_kmod-usb-cm109 is not set\nCONFIG_PACKAGE_kmod-usb-core=y\n# CONFIG_PACKAGE_kmod-usb-dwc2 is not set\n# CONFIG_PACKAGE_kmod-usb-dwc3 is not set\n# CONFIG_PACKAGE_kmod-usb-gadget-cdc-composite is not set\n# CONFIG_PACKAGE_kmod-usb-gadget-ehci-debug is not set\n# CONFIG_PACKAGE_kmod-usb-gadget-eth is not set\n# CONFIG_PACKAGE_kmod-usb-gadget-hid is not set\n# CONFIG_PACKAGE_kmod-usb-gadget-mass-storage is not set\n# CONFIG_PACKAGE_kmod-usb-gadget-ncm is not set\n# CONFIG_PACKAGE_kmod-usb-gadget-serial is not set\n# CONFIG_PACKAGE_kmod-usb-hid is not set\n# CONFIG_PACKAGE_kmod-usb-hid-cp2112 is not set\n# CONFIG_PACKAGE_kmod-usb-ledtrig-usbport is not set\nCONFIG_PACKAGE_kmod-usb-net=y\n# CONFIG_PACKAGE_kmod-usb-net-aqc111 is not set\n# CONFIG_PACKAGE_kmod-usb-net-asix is not set\n# CONFIG_PACKAGE_kmod-usb-net-asix-ax88179 is not set\n# CONFIG_PACKAGE_kmod-usb-net-cdc-eem is not set\n# CONFIG_PACKAGE_kmod-usb-net-cdc-ether is not set\n# CONFIG_PACKAGE_kmod-usb-net-cdc-mbim is not set\n# CONFIG_PACKAGE_kmod-usb-net-cdc-ncm is not set\n# CONFIG_PACKAGE_kmod-usb-net-cdc-subset is not set\n# CONFIG_PACKAGE_kmod-usb-net-dm9601-ether is not set\n# CONFIG_PACKAGE_kmod-usb-net-hso is not set\n# CONFIG_PACKAGE_kmod-usb-net-huawei-cdc-ncm is not set\n# CONFIG_PACKAGE_kmod-usb-net-ipheth is not set\n# CONFIG_PACKAGE_kmod-usb-net-kalmia is not set\n# CONFIG_PACKAGE_kmod-usb-net-kaweth is not set\n# CONFIG_PACKAGE_kmod-usb-net-mcs7830 is not set\n# CONFIG_PACKAGE_kmod-usb-net-pegasus is not set\n# CONFIG_PACKAGE_kmod-usb-net-pl is not set\n# CONFIG_PACKAGE_kmod-usb-net-qmi-wwan is not set\n# CONFIG_PACKAGE_kmod-usb-net-rndis is not set\n# CONFIG_PACKAGE_kmod-usb-net-rtl8150 is not set\nCONFIG_PACKAGE_kmod-usb-net-rtl8152=y\n# CONFIG_PACKAGE_kmod-usb-net-sierrawireless is not set\n# CONFIG_PACKAGE_kmod-usb-net-smsc75xx is not set\n# CONFIG_PACKAGE_kmod-usb-net-smsc95xx is not set\n# CONFIG_PACKAGE_kmod-usb-net-sr9700 is not set\n# CONFIG_PACKAGE_kmod-usb-net2280 is not set\n# CONFIG_PACKAGE_kmod-usb-ohci is not set\n# CONFIG_PACKAGE_kmod-usb-ohci-pci is not set\n# CONFIG_PACKAGE_kmod-usb-printer is not set\n# CONFIG_PACKAGE_kmod-usb-serial is not set\n# CONFIG_PACKAGE_kmod-usb-serial-ark3116 is not set\n# CONFIG_PACKAGE_kmod-usb-serial-belkin is not set\n# CONFIG_PACKAGE_kmod-usb-serial-ch341 is not set\n# CONFIG_PACKAGE_kmod-usb-serial-cp210x is not set\n# CONFIG_PACKAGE_kmod-usb-serial-cypress-m8 is not set\n# CONFIG_PACKAGE_kmod-usb-serial-edgeport is not set\n# CONFIG_PACKAGE_kmod-usb-serial-ftdi is not set\n# CONFIG_PACKAGE_kmod-usb-serial-garmin is not set\n# CONFIG_PACKAGE_kmod-usb-serial-ipw is not set\n# CONFIG_PACKAGE_kmod-usb-serial-keyspan is not set\n# CONFIG_PACKAGE_kmod-usb-serial-mct is not set\n# CONFIG_PACKAGE_kmod-usb-serial-mos7720 is not set\n# CONFIG_PACKAGE_kmod-usb-serial-mos7840 is not set\n# CONFIG_PACKAGE_kmod-usb-serial-option is not set\n# CONFIG_PACKAGE_kmod-usb-serial-oti6858 is not set\n# CONFIG_PACKAGE_kmod-usb-serial-pl2303 is not set\n# CONFIG_PACKAGE_kmod-usb-serial-qualcomm is not set\n# CONFIG_PACKAGE_kmod-usb-serial-sierrawireless is not set\n# CONFIG_PACKAGE_kmod-usb-serial-simple is not set\n# CONFIG_PACKAGE_kmod-usb-serial-ti-usb is not set\n# CONFIG_PACKAGE_kmod-usb-serial-visor is not set\n# CONFIG_PACKAGE_kmod-usb-storage is not set\n# CONFIG_PACKAGE_kmod-usb-storage-extras is not set\n# CONFIG_PACKAGE_kmod-usb-storage-uas is not set\n# CONFIG_PACKAGE_kmod-usb-uhci is not set\n# CONFIG_PACKAGE_kmod-usb-wdm is not set\n# CONFIG_PACKAGE_kmod-usb-yealink is not set\n# CONFIG_PACKAGE_kmod-usb2 is not set\n# CONFIG_PACKAGE_kmod-usb2-pci is not set\n# CONFIG_PACKAGE_kmod-usb3 is not set\n# CONFIG_PACKAGE_kmod-usbip is not set\n# CONFIG_PACKAGE_kmod-usbip-client is not set\n# CONFIG_PACKAGE_kmod-usbip-server is not set\n# CONFIG_PACKAGE_kmod-usbmon is not set\n# end of USB Support\n\n#\n# Video Support\n#\n# CONFIG_PACKAGE_kmod-backlight-pwm is not set\n# CONFIG_PACKAGE_kmod-drm-kms-helper is not set\n# CONFIG_PACKAGE_kmod-drm-ttm is not set\n# CONFIG_PACKAGE_kmod-fb is not set\n# CONFIG_PACKAGE_kmod-fb-cfb-copyarea is not set\n# CONFIG_PACKAGE_kmod-fb-cfb-fillrect is not set\n# CONFIG_PACKAGE_kmod-fb-cfb-imgblt is not set\n# CONFIG_PACKAGE_kmod-fb-sys-fops is not set\n# CONFIG_PACKAGE_kmod-fb-sys-ram is not set\n# CONFIG_PACKAGE_kmod-fb-tft is not set\n# CONFIG_PACKAGE_kmod-fb-tft-ili9486 is not set\n# CONFIG_PACKAGE_kmod-video-core is not set\n# CONFIG_PACKAGE_kmod-v4l2loopback is not set\n# end of Video Support\n\n#\n# Virtualization\n#\n# end of Virtualization\n\n#\n# Voice over IP\n#\n# CONFIG_PACKAGE_kmod-dahdi is not set\n# end of Voice over IP\n\n#\n# W1 support\n#\n# CONFIG_PACKAGE_kmod-w1 is not set\n# end of W1 support\n\n#\n# WPAN 802.15.4 Support\n#\n# CONFIG_PACKAGE_kmod-at86rf230 is not set\n# CONFIG_PACKAGE_kmod-atusb is not set\n# CONFIG_PACKAGE_kmod-ca8210 is not set\n# CONFIG_PACKAGE_kmod-cc2520 is not set\n# CONFIG_PACKAGE_kmod-fakelb is not set\n# CONFIG_PACKAGE_kmod-ieee802154 is not set\n# CONFIG_PACKAGE_kmod-ieee802154-6lowpan is not set\n# CONFIG_PACKAGE_kmod-mac802154 is not set\n# CONFIG_PACKAGE_kmod-mrf24j40 is not set\n# end of WPAN 802.15.4 Support\n\n#\n# Wireless Drivers\n#\n# CONFIG_PACKAGE_kmod-adm8211 is not set\n# CONFIG_PACKAGE_kmod-ar5523 is not set\n# CONFIG_PACKAGE_kmod-ath is not set\n# CONFIG_PACKAGE_kmod-ath10k is not set\n# CONFIG_PACKAGE_kmod-ath10k-ct is not set\n# CONFIG_PACKAGE_kmod-ath10k-ct-smallbuffers is not set\n# CONFIG_PACKAGE_kmod-ath5k is not set\n# CONFIG_PACKAGE_kmod-ath6kl-sdio is not set\n# CONFIG_PACKAGE_kmod-ath6kl-usb is not set\n# CONFIG_PACKAGE_kmod-ath9k is not set\n# CONFIG_PACKAGE_kmod-ath9k-htc is not set\n# CONFIG_PACKAGE_kmod-b43 is not set\n# CONFIG_PACKAGE_kmod-b43legacy is not set\n# CONFIG_PACKAGE_kmod-brcmfmac is not set\n# CONFIG_PACKAGE_kmod-brcmsmac is not set\n# CONFIG_PACKAGE_kmod-brcmutil is not set\n# CONFIG_PACKAGE_kmod-carl9170 is not set\nCONFIG_PACKAGE_kmod-cfg80211=y\n# CONFIG_PACKAGE_CFG80211_TESTMODE is not set\n# CONFIG_PACKAGE_kmod-hermes is not set\n# CONFIG_PACKAGE_kmod-hermes-pci is not set\n# CONFIG_PACKAGE_kmod-hermes-plx is not set\n# CONFIG_PACKAGE_kmod-ipw2100 is not set\n# CONFIG_PACKAGE_kmod-ipw2200 is not set\n# CONFIG_PACKAGE_kmod-iwl-legacy is not set\n# CONFIG_PACKAGE_kmod-iwl3945 is not set\n# CONFIG_PACKAGE_kmod-iwl4965 is not set\n# CONFIG_PACKAGE_kmod-iwlwifi is not set\n# CONFIG_PACKAGE_kmod-lib80211 is not set\n# CONFIG_PACKAGE_kmod-libertas-sdio is not set\n# CONFIG_PACKAGE_kmod-libertas-spi is not set\n# CONFIG_PACKAGE_kmod-libertas-usb is not set\n# CONFIG_PACKAGE_kmod-libipw is not set\nCONFIG_PACKAGE_kmod-mac80211=y\nCONFIG_PACKAGE_MAC80211_DEBUGFS=y\n# CONFIG_PACKAGE_MAC80211_TRACING is not set\nCONFIG_PACKAGE_MAC80211_MESH=y\n# CONFIG_PACKAGE_kmod-mac80211-hwsim is not set\n# CONFIG_PACKAGE_kmod-mt76 is not set\n# CONFIG_PACKAGE_kmod-mt7601u is not set\n# CONFIG_PACKAGE_kmod-mt7603 is not set\n# CONFIG_PACKAGE_kmod-mt7615-firmware is not set\n# CONFIG_PACKAGE_kmod-mt7615e is not set\n# CONFIG_PACKAGE_kmod-mt7663-firmware-ap is not set\n# CONFIG_PACKAGE_kmod-mt7663-firmware-sta is not set\n# CONFIG_PACKAGE_kmod-mt7663s is not set\n# CONFIG_PACKAGE_kmod-mt7663u is not set\n# CONFIG_PACKAGE_kmod-mt76x0e is not set\n# CONFIG_PACKAGE_kmod-mt76x0u is not set\n# CONFIG_PACKAGE_kmod-mt76x2 is not set\n# CONFIG_PACKAGE_kmod-mt76x2u is not set\n# CONFIG_PACKAGE_kmod-mt7915e is not set\n# CONFIG_PACKAGE_kmod-mt7921e is not set\n# CONFIG_PACKAGE_kmod-mt7921s is not set\n# CONFIG_PACKAGE_kmod-mwifiex-pcie is not set\n# CONFIG_PACKAGE_kmod-mwifiex-sdio is not set\n# CONFIG_PACKAGE_kmod-mwl8k is not set\n# CONFIG_PACKAGE_kmod-net-prism54 is not set\n# CONFIG_PACKAGE_kmod-net-rtl8192su is not set\n# CONFIG_PACKAGE_kmod-owl-loader is not set\n# CONFIG_PACKAGE_kmod-p54-common is not set\n# CONFIG_PACKAGE_kmod-p54-pci is not set\n# CONFIG_PACKAGE_kmod-p54-usb is not set\n# CONFIG_PACKAGE_kmod-rsi91x is not set\n# CONFIG_PACKAGE_kmod-rsi91x-sdio is not set\n# CONFIG_PACKAGE_kmod-rsi91x-usb is not set\n# CONFIG_PACKAGE_kmod-rt2400-pci is not set\n# CONFIG_PACKAGE_kmod-rt2500-pci is not set\n# CONFIG_PACKAGE_kmod-rt2500-usb is not set\n# CONFIG_PACKAGE_kmod-rt2800-pci is not set\n# CONFIG_PACKAGE_kmod-rt2800-usb is not set\n# CONFIG_PACKAGE_kmod-rt2x00-lib is not set\n# CONFIG_PACKAGE_kmod-rt61-pci is not set\n# CONFIG_PACKAGE_kmod-rt73-usb is not set\n# CONFIG_PACKAGE_kmod-rtl8180 is not set\n# CONFIG_PACKAGE_kmod-rtl8187 is not set\n# CONFIG_PACKAGE_kmod-rtl8192ce is not set\n# CONFIG_PACKAGE_kmod-rtl8192cu is not set\n# CONFIG_PACKAGE_kmod-rtl8192de is not set\n# CONFIG_PACKAGE_kmod-rtl8192se is not set\n# CONFIG_PACKAGE_kmod-rtl8723bs is not set\nCONFIG_PACKAGE_kmod-rtl8812au-ct=y\nCONFIG_PACKAGE_kmod-rtl8821ae=y\nCONFIG_PACKAGE_kmod-rtl8xxxu=y\nCONFIG_PACKAGE_kmod-rtlwifi=y\n# CONFIG_PACKAGE_RTLWIFI_DEBUG is not set\nCONFIG_PACKAGE_kmod-rtlwifi-btcoexist=y\nCONFIG_PACKAGE_kmod-rtlwifi-pci=y\n# CONFIG_PACKAGE_kmod-rtw88 is not set\n# CONFIG_PACKAGE_kmod-wil6210 is not set\n# CONFIG_PACKAGE_kmod-wl12xx is not set\n# CONFIG_PACKAGE_kmod-wl18xx is not set\n# CONFIG_PACKAGE_kmod-wlcore is not set\n# CONFIG_PACKAGE_kmod-zd1211rw is not set\n# end of Wireless Drivers\n# end of Kernel modules\n\n#\n# Languages\n#\n\n#\n# Erlang\n#\n# CONFIG_PACKAGE_erlang is not set\n# CONFIG_PACKAGE_erlang-asn1 is not set\n# CONFIG_PACKAGE_erlang-compiler is not set\n# CONFIG_PACKAGE_erlang-crypto is not set\n# CONFIG_PACKAGE_erlang-erl-interface is not set\n# CONFIG_PACKAGE_erlang-hipe is not set\n# CONFIG_PACKAGE_erlang-inets is not set\n# CONFIG_PACKAGE_erlang-mnesia is not set\n# CONFIG_PACKAGE_erlang-os_mon is not set\n# CONFIG_PACKAGE_erlang-public-key is not set\n# CONFIG_PACKAGE_erlang-reltool is not set\n# CONFIG_PACKAGE_erlang-runtime-tools is not set\n# CONFIG_PACKAGE_erlang-snmp is not set\n# CONFIG_PACKAGE_erlang-ssh is not set\n# CONFIG_PACKAGE_erlang-ssl is not set\n# CONFIG_PACKAGE_erlang-syntax-tools is not set\n# CONFIG_PACKAGE_erlang-tools is not set\n# CONFIG_PACKAGE_erlang-xmerl is not set\n# end of Erlang\n\n#\n# Go\n#\n# CONFIG_PACKAGE_golang is not set\n\n#\n# Configuration\n#\nCONFIG_GOLANG_EXTERNAL_BOOTSTRAP_ROOT=\"\"\nCONFIG_GOLANG_BUILD_CACHE_DIR=\"\"\n# CONFIG_GOLANG_MOD_CACHE_WORLD_READABLE is not set\n# end of Configuration\n\n# CONFIG_PACKAGE_golang-doc is not set\n# CONFIG_PACKAGE_golang-github-jedisct1-dnscrypt-proxy2-dev is not set\n# CONFIG_PACKAGE_golang-github-nextdns-nextdns-dev is not set\n# CONFIG_PACKAGE_golang-gitlab-yawning-obfs4-dev is not set\n# CONFIG_PACKAGE_golang-src is not set\n# CONFIG_PACKAGE_golang-torproject-tor-fw-helper-dev is not set\n# end of Go\n\n#\n# Lua\n#\n# CONFIG_PACKAGE_dkjson is not set\n# CONFIG_PACKAGE_json4lua is not set\n# CONFIG_PACKAGE_ldbus is not set\nCONFIG_PACKAGE_libiwinfo-lua=y\n# CONFIG_PACKAGE_linotify is not set\n# CONFIG_PACKAGE_lpeg is not set\n# CONFIG_PACKAGE_lsqlite3 is not set\nCONFIG_PACKAGE_lua=y\n# CONFIG_PACKAGE_lua-argparse is not set\n# CONFIG_PACKAGE_lua-bencode is not set\n# CONFIG_PACKAGE_lua-bit32 is not set\n# CONFIG_PACKAGE_lua-cjson is not set\n# CONFIG_PACKAGE_lua-copas is not set\n# CONFIG_PACKAGE_lua-coxpcall is not set\n# CONFIG_PACKAGE_lua-curl-v3 is not set\n# CONFIG_PACKAGE_lua-ev is not set\n# CONFIG_PACKAGE_lua-examples is not set\n# CONFIG_PACKAGE_lua-libmodbus is not set\n# CONFIG_PACKAGE_lua-lzlib is not set\n# CONFIG_PACKAGE_lua-md5 is not set\n# CONFIG_PACKAGE_lua-mobdebug is not set\n# CONFIG_PACKAGE_lua-mosquitto is not set\n# CONFIG_PACKAGE_lua-openssl is not set\n# CONFIG_PACKAGE_lua-penlight is not set\n# CONFIG_PACKAGE_lua-rings is not set\n# CONFIG_PACKAGE_lua-rs232 is not set\n# CONFIG_PACKAGE_lua-sha2 is not set\n# CONFIG_PACKAGE_lua-wsapi-base is not set\n# CONFIG_PACKAGE_lua-wsapi-xavante is not set\n# CONFIG_PACKAGE_lua-xavante is not set\n# CONFIG_PACKAGE_lua5.3 is not set\n# CONFIG_PACKAGE_luabitop is not set\n# CONFIG_PACKAGE_luac is not set\n# CONFIG_PACKAGE_luac5.3 is not set\n# CONFIG_PACKAGE_luaexpat is not set\n# CONFIG_PACKAGE_luafilesystem is not set\n# CONFIG_PACKAGE_luajit is not set\n# CONFIG_PACKAGE_lualanes is not set\n# CONFIG_PACKAGE_luaossl is not set\n# CONFIG_PACKAGE_luaposix is not set\n# CONFIG_PACKAGE_luarocks is not set\n# CONFIG_PACKAGE_luasec is not set\n# CONFIG_PACKAGE_luasoap is not set\n# CONFIG_PACKAGE_luasocket is not set\n# CONFIG_PACKAGE_luasocket5.3 is not set\n# CONFIG_PACKAGE_luasql-mysql is not set\n# CONFIG_PACKAGE_luasql-pgsql is not set\n# CONFIG_PACKAGE_luasql-sqlite3 is not set\n# CONFIG_PACKAGE_luasrcdiet is not set\n# CONFIG_PACKAGE_luv is not set\n# CONFIG_PACKAGE_lyaml is not set\n# CONFIG_PACKAGE_lzmq is not set\n# CONFIG_PACKAGE_uuid is not set\n# end of Lua\n\n#\n# Node.js\n#\n# CONFIG_PACKAGE_node is not set\n# CONFIG_PACKAGE_node-arduino-firmata is not set\n# CONFIG_PACKAGE_node-cylon is not set\n# CONFIG_PACKAGE_node-cylon-firmata is not set\n# CONFIG_PACKAGE_node-cylon-gpio is not set\n# CONFIG_PACKAGE_node-cylon-i2c is not set\n# CONFIG_PACKAGE_node-hid is not set\n# CONFIG_PACKAGE_node-homebridge is not set\n# CONFIG_PACKAGE_node-javascript-obfuscator is not set\n# CONFIG_PACKAGE_node-npm is not set\n# CONFIG_PACKAGE_node-serialport is not set\n# CONFIG_PACKAGE_node-serialport-bindings is not set\n# end of Node.js\n\n#\n# PHP7\n#\n# CONFIG_PACKAGE_php7 is not set\n# end of PHP7\n\n#\n# PHP8\n#\n# CONFIG_PACKAGE_php8 is not set\n# end of PHP8\n\n#\n# Perl\n#\n# CONFIG_PACKAGE_perl is not set\n# end of Perl\n\n#\n# Python\n#\n# CONFIG_PACKAGE_libpython3 is not set\n# CONFIG_PACKAGE_micropython is not set\n# CONFIG_PACKAGE_micropython-lib is not set\n# CONFIG_PACKAGE_python-pip-conf is not set\n# CONFIG_PACKAGE_python3 is not set\n# CONFIG_PACKAGE_python3-aiohttp is not set\n# CONFIG_PACKAGE_python3-aiohttp-cors is not set\n# CONFIG_PACKAGE_python3-apipkg is not set\n# CONFIG_PACKAGE_python3-apparmor is not set\n# CONFIG_PACKAGE_python3-appdirs is not set\n# CONFIG_PACKAGE_python3-asgiref is not set\n# CONFIG_PACKAGE_python3-asn1crypto is not set\n# CONFIG_PACKAGE_python3-astral is not set\n# CONFIG_PACKAGE_python3-async-timeout is not set\n# CONFIG_PACKAGE_python3-asyncio is not set\n# CONFIG_PACKAGE_python3-atomicwrites is not set\n# CONFIG_PACKAGE_python3-attrs is not set\n# CONFIG_PACKAGE_python3-augeas is not set\n# CONFIG_PACKAGE_python3-automat is not set\n# CONFIG_PACKAGE_python3-awesomeversion is not set\n# CONFIG_PACKAGE_python3-awscli is not set\n# CONFIG_PACKAGE_python3-babel is not set\n# CONFIG_PACKAGE_python3-base is not set\n# CONFIG_PACKAGE_python3-bcrypt is not set\n# CONFIG_PACKAGE_python3-bidict is not set\n# CONFIG_PACKAGE_python3-boto3 is not set\n# CONFIG_PACKAGE_python3-botocore is not set\n# CONFIG_PACKAGE_python3-bottle is not set\n# CONFIG_PACKAGE_python3-cached-property is not set\n# CONFIG_PACKAGE_python3-cachelib is not set\n# CONFIG_PACKAGE_python3-cachetools is not set\n# CONFIG_PACKAGE_python3-certifi is not set\n# CONFIG_PACKAGE_python3-cffi is not set\n# CONFIG_PACKAGE_python3-cgi is not set\n# CONFIG_PACKAGE_python3-cgitb is not set\n# CONFIG_PACKAGE_python3-chardet is not set\n# CONFIG_PACKAGE_python3-ciso8601 is not set\n# CONFIG_PACKAGE_python3-click is not set\n# CONFIG_PACKAGE_python3-click-log is not set\n# CONFIG_PACKAGE_python3-codecs is not set\n# CONFIG_PACKAGE_python3-colorama is not set\n# CONFIG_PACKAGE_python3-constantly is not set\n# CONFIG_PACKAGE_python3-contextlib2 is not set\n# CONFIG_PACKAGE_python3-cryptodome is not set\n# CONFIG_PACKAGE_python3-cryptodomex is not set\n# CONFIG_PACKAGE_python3-cryptography is not set\n# CONFIG_PACKAGE_python3-ctypes is not set\n# CONFIG_PACKAGE_python3-curl is not set\n# CONFIG_PACKAGE_python3-dateutil is not set\n# CONFIG_PACKAGE_python3-dbm is not set\n# CONFIG_PACKAGE_python3-decimal is not set\n# CONFIG_PACKAGE_python3-decorator is not set\n# CONFIG_PACKAGE_python3-defusedxml is not set\n# CONFIG_PACKAGE_python3-dev is not set\n# CONFIG_PACKAGE_python3-distro is not set\n# CONFIG_PACKAGE_python3-distutils is not set\n# CONFIG_PACKAGE_python3-django is not set\n# CONFIG_PACKAGE_python3-django-appconf is not set\n# CONFIG_PACKAGE_python3-django-compressor is not set\n# CONFIG_PACKAGE_python3-django-cors-headers is not set\n# CONFIG_PACKAGE_python3-django-etesync-journal is not set\n# CONFIG_PACKAGE_python3-django-formtools is not set\n# CONFIG_PACKAGE_python3-django-jsonfield is not set\n# CONFIG_PACKAGE_python3-django-jsonfield2 is not set\n# CONFIG_PACKAGE_python3-django-picklefield is not set\n# CONFIG_PACKAGE_python3-django-postoffice is not set\n# CONFIG_PACKAGE_python3-django-ranged-response is not set\n# CONFIG_PACKAGE_python3-django-restframework is not set\n# CONFIG_PACKAGE_python3-django-restframework39 is not set\n# CONFIG_PACKAGE_python3-django-simple-captcha is not set\n# CONFIG_PACKAGE_python3-django-statici18n is not set\n# CONFIG_PACKAGE_python3-django-webpack-loader is not set\n# CONFIG_PACKAGE_python3-django1 is not set\n# CONFIG_PACKAGE_python3-dns is not set\n# CONFIG_PACKAGE_python3-docker is not set\n# CONFIG_PACKAGE_python3-dockerpty is not set\n# CONFIG_PACKAGE_python3-docopt is not set\n# CONFIG_PACKAGE_python3-docutils is not set\n# CONFIG_PACKAGE_python3-dotenv is not set\n# CONFIG_PACKAGE_python3-drf-nested-routers is not set\n# CONFIG_PACKAGE_python3-email is not set\n# CONFIG_PACKAGE_python3-engineio is not set\n# CONFIG_PACKAGE_python3-et_xmlfile is not set\n# CONFIG_PACKAGE_python3-evdev is not set\n# CONFIG_PACKAGE_python3-eventlet is not set\n# CONFIG_PACKAGE_python3-execnet is not set\n# CONFIG_PACKAGE_python3-flask is not set\n# CONFIG_PACKAGE_python3-flask-babel is not set\n# CONFIG_PACKAGE_python3-flask-httpauth is not set\n# CONFIG_PACKAGE_python3-flask-login is not set\n# CONFIG_PACKAGE_python3-flask-seasurf is not set\n# CONFIG_PACKAGE_python3-flask-session is not set\n# CONFIG_PACKAGE_python3-flask-socketio is not set\n# CONFIG_PACKAGE_python3-flup is not set\n# CONFIG_PACKAGE_python3-gmpy2 is not set\n# CONFIG_PACKAGE_python3-gnupg is not set\n# CONFIG_PACKAGE_python3-gpiod is not set\n# CONFIG_PACKAGE_python3-greenlet is not set\n# CONFIG_PACKAGE_python3-hyperlink is not set\n# CONFIG_PACKAGE_python3-idna is not set\n# CONFIG_PACKAGE_python3-ifaddr is not set\n# CONFIG_PACKAGE_python3-incremental is not set\n# CONFIG_PACKAGE_python3-influxdb is not set\n# CONFIG_PACKAGE_python3-iniconfig is not set\n# CONFIG_PACKAGE_python3-intelhex is not set\n# CONFIG_PACKAGE_python3-itsdangerous is not set\n# CONFIG_PACKAGE_python3-jdcal is not set\n# CONFIG_PACKAGE_python3-jinja2 is not set\n# CONFIG_PACKAGE_python3-jmespath is not set\n# CONFIG_PACKAGE_python3-jsonpath-ng is not set\n# CONFIG_PACKAGE_python3-jsonschema is not set\n# CONFIG_PACKAGE_python3-lib2to3 is not set\n# CONFIG_PACKAGE_python3-libmodbus is not set\n# CONFIG_PACKAGE_python3-libselinux is not set\n# CONFIG_PACKAGE_python3-libsemanage is not set\n# CONFIG_PACKAGE_python3-light is not set\n\n#\n# Configuration\n#\n# CONFIG_PYTHON3_HOST_PIP_CACHE_WORLD_READABLE is not set\n# end of Configuration\n\n# CONFIG_PACKAGE_python3-logging is not set\n# CONFIG_PACKAGE_python3-lxml is not set\n# CONFIG_PACKAGE_python3-lzma is not set\n# CONFIG_PACKAGE_python3-mako is not set\n# CONFIG_PACKAGE_python3-markdown is not set\n# CONFIG_PACKAGE_python3-markupsafe is not set\n# CONFIG_PACKAGE_python3-maxminddb is not set\n# CONFIG_PACKAGE_python3-more-itertools is not set\n# CONFIG_PACKAGE_python3-msgpack is not set\n# CONFIG_PACKAGE_python3-multidict is not set\n# CONFIG_PACKAGE_python3-multiprocessing is not set\n# CONFIG_PACKAGE_python3-ncurses is not set\n# CONFIG_PACKAGE_python3-netdisco is not set\n# CONFIG_PACKAGE_python3-netifaces is not set\n# CONFIG_PACKAGE_python3-networkx is not set\n# CONFIG_PACKAGE_python3-newt is not set\n# CONFIG_PACKAGE_python3-numpy is not set\n\n#\n# Configuration\n#\n# CONFIG_NUMPY_OPENBLAS_SUPPORT is not set\n# end of Configuration\n\n# CONFIG_PACKAGE_python3-oauthlib is not set\n# CONFIG_PACKAGE_python3-openpyxl is not set\n# CONFIG_PACKAGE_python3-openssl is not set\n# CONFIG_PACKAGE_python3-packaging is not set\n# CONFIG_PACKAGE_python3-paho-mqtt is not set\n# CONFIG_PACKAGE_python3-paramiko is not set\n# CONFIG_PACKAGE_python3-parsley is not set\n# CONFIG_PACKAGE_python3-passlib is not set\n# CONFIG_PACKAGE_python3-pillow is not set\n# CONFIG_PACKAGE_python3-pip is not set\n# CONFIG_PACKAGE_python3-pkg-resources is not set\n# CONFIG_PACKAGE_python3-pluggy is not set\n# CONFIG_PACKAGE_python3-ply is not set\n# CONFIG_PACKAGE_python3-psutil is not set\n# CONFIG_PACKAGE_python3-psycopg2 is not set\n# CONFIG_PACKAGE_python3-py is not set\n# CONFIG_PACKAGE_python3-pyasn1 is not set\n# CONFIG_PACKAGE_python3-pyasn1-modules is not set\n# CONFIG_PACKAGE_python3-pycparser is not set\n# CONFIG_PACKAGE_python3-pydoc is not set\n# CONFIG_PACKAGE_python3-pyinotify is not set\n# CONFIG_PACKAGE_python3-pyjwt is not set\n# CONFIG_PACKAGE_python3-pymysql is not set\n# CONFIG_PACKAGE_python3-pynacl is not set\n# CONFIG_PACKAGE_python3-pyodbc is not set\n# CONFIG_PACKAGE_python3-pyopenssl is not set\n# CONFIG_PACKAGE_python3-pyotp is not set\n# CONFIG_PACKAGE_python3-pyparsing is not set\n# CONFIG_PACKAGE_python3-pyroute2 is not set\n# CONFIG_PACKAGE_python3-pyrsistent is not set\n# CONFIG_PACKAGE_python3-pyserial is not set\n# CONFIG_PACKAGE_python3-pysocks is not set\n# CONFIG_PACKAGE_python3-pytest is not set\n# CONFIG_PACKAGE_python3-pytest-forked is not set\n# CONFIG_PACKAGE_python3-pytest-xdist is not set\n# CONFIG_PACKAGE_python3-pytz is not set\n# CONFIG_PACKAGE_python3-qrcode is not set\n# CONFIG_PACKAGE_python3-rcssmin is not set\n# CONFIG_PACKAGE_python3-readline is not set\n# CONFIG_PACKAGE_python3-requests is not set\n# CONFIG_PACKAGE_python3-requests-oauthlib is not set\n# CONFIG_PACKAGE_python3-rsa is not set\n# CONFIG_PACKAGE_python3-ruamel-yaml is not set\n# CONFIG_PACKAGE_python3-s3transfer is not set\n# CONFIG_PACKAGE_python3-schedule is not set\n# CONFIG_PACKAGE_python3-schema is not set\n# CONFIG_PACKAGE_python3-seafile-ccnet is not set\n# CONFIG_PACKAGE_python3-seafile-server is not set\n# CONFIG_PACKAGE_python3-searpc is not set\n# CONFIG_PACKAGE_python3-sentry-sdk is not set\n# CONFIG_PACKAGE_python3-sepolgen is not set\n# CONFIG_PACKAGE_python3-sepolicy is not set\n# CONFIG_PACKAGE_python3-service-identity is not set\n# CONFIG_PACKAGE_python3-setuptools is not set\n# CONFIG_PACKAGE_python3-simplejson is not set\n# CONFIG_PACKAGE_python3-six is not set\n# CONFIG_PACKAGE_python3-slugify is not set\n# CONFIG_PACKAGE_python3-smbus is not set\n# CONFIG_PACKAGE_python3-socketio is not set\n# CONFIG_PACKAGE_python3-speedtest-cli is not set\n# CONFIG_PACKAGE_python3-sqlalchemy is not set\n# CONFIG_PACKAGE_python3-sqlite3 is not set\n# CONFIG_PACKAGE_python3-sqlparse is not set\n# CONFIG_PACKAGE_python3-stem is not set\n# CONFIG_PACKAGE_python3-text-unidecode is not set\n# CONFIG_PACKAGE_python3-texttable is not set\n# CONFIG_PACKAGE_python3-toml is not set\n# CONFIG_PACKAGE_python3-tornado is not set\n# CONFIG_PACKAGE_python3-twisted is not set\n# CONFIG_PACKAGE_python3-typing-extensions is not set\n# CONFIG_PACKAGE_python3-ubus is not set\n# CONFIG_PACKAGE_python3-uci is not set\n# CONFIG_PACKAGE_python3-unidecode is not set\n# CONFIG_PACKAGE_python3-unittest is not set\n# CONFIG_PACKAGE_python3-urllib is not set\n# CONFIG_PACKAGE_python3-urllib3 is not set\n# CONFIG_PACKAGE_python3-uuid is not set\n# CONFIG_PACKAGE_python3-vobject is not set\n# CONFIG_PACKAGE_python3-voluptuous is not set\n# CONFIG_PACKAGE_python3-voluptuous-serialize is not set\n# CONFIG_PACKAGE_python3-wcwidth is not set\n# CONFIG_PACKAGE_python3-websocket-client is not set\n# CONFIG_PACKAGE_python3-websockets is not set\n# CONFIG_PACKAGE_python3-werkzeug is not set\n# CONFIG_PACKAGE_python3-xml is not set\n# CONFIG_PACKAGE_python3-xmltodict is not set\n# CONFIG_PACKAGE_python3-yaml is not set\n# CONFIG_PACKAGE_python3-yarl is not set\n# CONFIG_PACKAGE_python3-zeroconf is not set\n# CONFIG_PACKAGE_python3-zipp is not set\n# CONFIG_PACKAGE_python3-zope-interface is not set\n# end of Python\n\n#\n# Ruby\n#\n# CONFIG_PACKAGE_ruby is not set\n# end of Ruby\n\n#\n# Tcl\n#\n# CONFIG_PACKAGE_tcl is not set\n# end of Tcl\n\n# CONFIG_PACKAGE_chicken-scheme-full is not set\n# CONFIG_PACKAGE_chicken-scheme-interpreter is not set\n# CONFIG_PACKAGE_slsh is not set\n# end of Languages\n\n#\n# Libraries\n#\n\n#\n# Compression\n#\nCONFIG_PACKAGE_libbz2=y\n# CONFIG_PACKAGE_liblz4 is not set\n# CONFIG_PACKAGE_liblzma is not set\n# CONFIG_PACKAGE_libunrar is not set\n# CONFIG_PACKAGE_libzip-gnutls is not set\n# CONFIG_PACKAGE_libzip-mbedtls is not set\n# CONFIG_PACKAGE_libzip-nossl is not set\n# CONFIG_PACKAGE_libzip-openssl is not set\n# CONFIG_PACKAGE_libzstd is not set\n# end of Compression\n\n#\n# Database\n#\n# CONFIG_PACKAGE_libmariadb is not set\n# CONFIG_PACKAGE_libpq is not set\n# CONFIG_PACKAGE_libpqxx is not set\nCONFIG_PACKAGE_libsqlite3=y\n\n#\n# Configuration\n#\n# CONFIG_SQLITE3_BATCH_ATOMIC_WRITE is not set\nCONFIG_SQLITE3_DYNAMIC_EXTENSIONS=y\nCONFIG_SQLITE3_FTS3=y\nCONFIG_SQLITE3_FTS4=y\nCONFIG_SQLITE3_FTS5=y\nCONFIG_SQLITE3_JSON1=y\nCONFIG_SQLITE3_RTREE=y\n# CONFIG_SQLITE3_SESSION is not set\n# end of Configuration\n\n# CONFIG_PACKAGE_pgsqlodbc is not set\n# CONFIG_PACKAGE_psqlodbca is not set\n# CONFIG_PACKAGE_psqlodbcw is not set\n# CONFIG_PACKAGE_redis-cli is not set\n# CONFIG_PACKAGE_redis-server is not set\n# CONFIG_PACKAGE_redis-utils is not set\n# CONFIG_PACKAGE_tdb is not set\n# CONFIG_PACKAGE_unixodbc is not set\n# end of Database\n\n#\n# Filesystem\n#\n# CONFIG_PACKAGE_libacl is not set\nCONFIG_PACKAGE_libattr=y\n# CONFIG_PACKAGE_libfuse is not set\n# CONFIG_PACKAGE_libfuse3 is not set\n# CONFIG_PACKAGE_libow is not set\n# CONFIG_PACKAGE_libow-capi is not set\n# CONFIG_PACKAGE_libsysfs is not set\n# end of Filesystem\n\n#\n# Firewall\n#\n# CONFIG_PACKAGE_libfko is not set\nCONFIG_PACKAGE_libip4tc=y\nCONFIG_PACKAGE_libip6tc=y\nCONFIG_PACKAGE_libxtables=y\n# CONFIG_PACKAGE_libxtables-nft is not set\n# end of Firewall\n\n#\n# Instant Messaging\n#\n# CONFIG_PACKAGE_quasselc is not set\n# end of Instant Messaging\n\n#\n# IoT\n#\n# CONFIG_PACKAGE_libmraa is not set\n# CONFIG_PACKAGE_libmraa-python3 is not set\n# CONFIG_PACKAGE_libupm is not set\n# CONFIG_PACKAGE_libupm-a110x is not set\n# CONFIG_PACKAGE_libupm-a110x-python3 is not set\n# CONFIG_PACKAGE_libupm-abp is not set\n# CONFIG_PACKAGE_libupm-abp-python3 is not set\n# CONFIG_PACKAGE_libupm-ad8232 is not set\n# CONFIG_PACKAGE_libupm-ad8232-python3 is not set\n# CONFIG_PACKAGE_libupm-adafruitms1438 is not set\n# CONFIG_PACKAGE_libupm-adafruitms1438-python3 is not set\n# CONFIG_PACKAGE_libupm-adafruitss is not set\n# CONFIG_PACKAGE_libupm-adafruitss-python3 is not set\n# CONFIG_PACKAGE_libupm-adc121c021 is not set\n# CONFIG_PACKAGE_libupm-adc121c021-python3 is not set\n# CONFIG_PACKAGE_libupm-adis16448 is not set\n# CONFIG_PACKAGE_libupm-adis16448-python3 is not set\n# CONFIG_PACKAGE_libupm-ads1x15 is not set\n# CONFIG_PACKAGE_libupm-ads1x15-python3 is not set\n# CONFIG_PACKAGE_libupm-adxl335 is not set\n# CONFIG_PACKAGE_libupm-adxl335-python3 is not set\n# CONFIG_PACKAGE_libupm-adxl345 is not set\n# CONFIG_PACKAGE_libupm-adxl345-python3 is not set\n# CONFIG_PACKAGE_libupm-adxrs610 is not set\n# CONFIG_PACKAGE_libupm-adxrs610-python3 is not set\n# CONFIG_PACKAGE_libupm-am2315 is not set\n# CONFIG_PACKAGE_libupm-am2315-python3 is not set\n# CONFIG_PACKAGE_libupm-apa102 is not set\n# CONFIG_PACKAGE_libupm-apa102-python3 is not set\n# CONFIG_PACKAGE_libupm-apds9002 is not set\n# CONFIG_PACKAGE_libupm-apds9002-python3 is not set\n# CONFIG_PACKAGE_libupm-apds9930 is not set\n# CONFIG_PACKAGE_libupm-apds9930-python3 is not set\n# CONFIG_PACKAGE_libupm-at42qt1070 is not set\n# CONFIG_PACKAGE_libupm-at42qt1070-python3 is not set\n# CONFIG_PACKAGE_libupm-bh1749 is not set\n# CONFIG_PACKAGE_libupm-bh1749-python3 is not set\n# CONFIG_PACKAGE_libupm-bh1750 is not set\n# CONFIG_PACKAGE_libupm-bh1750-python3 is not set\n# CONFIG_PACKAGE_libupm-bh1792 is not set\n# CONFIG_PACKAGE_libupm-bh1792-python3 is not set\n# CONFIG_PACKAGE_libupm-biss0001 is not set\n# CONFIG_PACKAGE_libupm-biss0001-python3 is not set\n# CONFIG_PACKAGE_libupm-bma220 is not set\n# CONFIG_PACKAGE_libupm-bma220-python3 is not set\n# CONFIG_PACKAGE_libupm-bma250e is not set\n# CONFIG_PACKAGE_libupm-bma250e-python3 is not set\n# CONFIG_PACKAGE_libupm-bmg160 is not set\n# CONFIG_PACKAGE_libupm-bmg160-python3 is not set\n# CONFIG_PACKAGE_libupm-bmi160 is not set\n# CONFIG_PACKAGE_libupm-bmi160-python3 is not set\n# CONFIG_PACKAGE_libupm-bmm150 is not set\n# CONFIG_PACKAGE_libupm-bmm150-python3 is not set\n# CONFIG_PACKAGE_libupm-bmp280 is not set\n# CONFIG_PACKAGE_libupm-bmp280-python3 is not set\n# CONFIG_PACKAGE_libupm-bmpx8x is not set\n# CONFIG_PACKAGE_libupm-bmpx8x-python3 is not set\n# CONFIG_PACKAGE_libupm-bmx055 is not set\n# CONFIG_PACKAGE_libupm-bmx055-python3 is not set\n# CONFIG_PACKAGE_libupm-bno055 is not set\n# CONFIG_PACKAGE_libupm-bno055-python3 is not set\n# CONFIG_PACKAGE_libupm-button is not set\n# CONFIG_PACKAGE_libupm-button-python3 is not set\n# CONFIG_PACKAGE_libupm-buzzer is not set\n# CONFIG_PACKAGE_libupm-buzzer-python3 is not set\n# CONFIG_PACKAGE_libupm-cjq4435 is not set\n# CONFIG_PACKAGE_libupm-cjq4435-python3 is not set\n# CONFIG_PACKAGE_libupm-collision is not set\n# CONFIG_PACKAGE_libupm-collision-python3 is not set\n# CONFIG_PACKAGE_libupm-curieimu is not set\n# CONFIG_PACKAGE_libupm-curieimu-python3 is not set\n# CONFIG_PACKAGE_libupm-cwlsxxa is not set\n# CONFIG_PACKAGE_libupm-cwlsxxa-python3 is not set\n# CONFIG_PACKAGE_libupm-dfrec is not set\n# CONFIG_PACKAGE_libupm-dfrec-python3 is not set\n# CONFIG_PACKAGE_libupm-dfrorp is not set\n# CONFIG_PACKAGE_libupm-dfrorp-python3 is not set\n# CONFIG_PACKAGE_libupm-dfrph is not set\n# CONFIG_PACKAGE_libupm-dfrph-python3 is not set\n# CONFIG_PACKAGE_libupm-ds1307 is not set\n# CONFIG_PACKAGE_libupm-ds1307-python3 is not set\n# CONFIG_PACKAGE_libupm-ds1808lc is not set\n# CONFIG_PACKAGE_libupm-ds1808lc-python3 is not set\n# CONFIG_PACKAGE_libupm-ds18b20 is not set\n# CONFIG_PACKAGE_libupm-ds18b20-python3 is not set\n# CONFIG_PACKAGE_libupm-ds2413 is not set\n# CONFIG_PACKAGE_libupm-ds2413-python3 is not set\n# CONFIG_PACKAGE_libupm-ecezo is not set\n# CONFIG_PACKAGE_libupm-ecezo-python3 is not set\n# CONFIG_PACKAGE_libupm-ecs1030 is not set\n# CONFIG_PACKAGE_libupm-ecs1030-python3 is not set\n# CONFIG_PACKAGE_libupm-ehr is not set\n# CONFIG_PACKAGE_libupm-ehr-python3 is not set\n# CONFIG_PACKAGE_libupm-eldriver is not set\n# CONFIG_PACKAGE_libupm-eldriver-python3 is not set\n# CONFIG_PACKAGE_libupm-electromagnet is not set\n# CONFIG_PACKAGE_libupm-electromagnet-python3 is not set\n# CONFIG_PACKAGE_libupm-emg is not set\n# CONFIG_PACKAGE_libupm-emg-python3 is not set\n# CONFIG_PACKAGE_libupm-enc03r is not set\n# CONFIG_PACKAGE_libupm-enc03r-python3 is not set\n# CONFIG_PACKAGE_libupm-flex is not set\n# CONFIG_PACKAGE_libupm-flex-python3 is not set\n# CONFIG_PACKAGE_libupm-gas is not set\n# CONFIG_PACKAGE_libupm-gas-python3 is not set\n# CONFIG_PACKAGE_libupm-gp2y0a is not set\n# CONFIG_PACKAGE_libupm-gp2y0a-python3 is not set\n# CONFIG_PACKAGE_libupm-gprs is not set\n# CONFIG_PACKAGE_libupm-gprs-python3 is not set\n# CONFIG_PACKAGE_libupm-gsr is not set\n# CONFIG_PACKAGE_libupm-gsr-python3 is not set\n# CONFIG_PACKAGE_libupm-guvas12d is not set\n# CONFIG_PACKAGE_libupm-guvas12d-python3 is not set\n# CONFIG_PACKAGE_libupm-h3lis331dl is not set\n# CONFIG_PACKAGE_libupm-h3lis331dl-python3 is not set\n# CONFIG_PACKAGE_libupm-h803x is not set\n# CONFIG_PACKAGE_libupm-h803x-python3 is not set\n# CONFIG_PACKAGE_libupm-hcsr04 is not set\n# CONFIG_PACKAGE_libupm-hcsr04-python3 is not set\n# CONFIG_PACKAGE_libupm-hdc1000 is not set\n# CONFIG_PACKAGE_libupm-hdc1000-python3 is not set\n# CONFIG_PACKAGE_libupm-hdxxvxta is not set\n# CONFIG_PACKAGE_libupm-hdxxvxta-python3 is not set\n# CONFIG_PACKAGE_libupm-hka5 is not set\n# CONFIG_PACKAGE_libupm-hka5-python3 is not set\n# CONFIG_PACKAGE_libupm-hlg150h is not set\n# CONFIG_PACKAGE_libupm-hlg150h-python3 is not set\n# CONFIG_PACKAGE_libupm-hm11 is not set\n# CONFIG_PACKAGE_libupm-hm11-python3 is not set\n# CONFIG_PACKAGE_libupm-hmc5883l is not set\n# CONFIG_PACKAGE_libupm-hmc5883l-python3 is not set\n# CONFIG_PACKAGE_libupm-hmtrp is not set\n# CONFIG_PACKAGE_libupm-hmtrp-python3 is not set\n# CONFIG_PACKAGE_libupm-hp20x is not set\n# CONFIG_PACKAGE_libupm-hp20x-python3 is not set\n# CONFIG_PACKAGE_libupm-ht9170 is not set\n# CONFIG_PACKAGE_libupm-ht9170-python3 is not set\n# CONFIG_PACKAGE_libupm-htu21d is not set\n# CONFIG_PACKAGE_libupm-htu21d-python3 is not set\n# CONFIG_PACKAGE_libupm-hwxpxx is not set\n# CONFIG_PACKAGE_libupm-hwxpxx-python3 is not set\n# CONFIG_PACKAGE_libupm-hx711 is not set\n# CONFIG_PACKAGE_libupm-hx711-python3 is not set\n# CONFIG_PACKAGE_libupm-ili9341 is not set\n# CONFIG_PACKAGE_libupm-ili9341-python3 is not set\n# CONFIG_PACKAGE_libupm-ims is not set\n# CONFIG_PACKAGE_libupm-ims-python3 is not set\n# CONFIG_PACKAGE_libupm-ina132 is not set\n# CONFIG_PACKAGE_libupm-ina132-python3 is not set\n# CONFIG_PACKAGE_libupm-interfaces is not set\n# CONFIG_PACKAGE_libupm-interfaces-python3 is not set\n# CONFIG_PACKAGE_libupm-isd1820 is not set\n# CONFIG_PACKAGE_libupm-isd1820-python3 is not set\n# CONFIG_PACKAGE_libupm-itg3200 is not set\n# CONFIG_PACKAGE_libupm-itg3200-python3 is not set\n# CONFIG_PACKAGE_libupm-jhd1313m1 is not set\n# CONFIG_PACKAGE_libupm-jhd1313m1-python3 is not set\n# CONFIG_PACKAGE_libupm-joystick12 is not set\n# CONFIG_PACKAGE_libupm-joystick12-python3 is not set\n# CONFIG_PACKAGE_libupm-kx122 is not set\n# CONFIG_PACKAGE_libupm-kx122-python3 is not set\n# CONFIG_PACKAGE_libupm-kxcjk1013 is not set\n# CONFIG_PACKAGE_libupm-kxcjk1013-python3 is not set\n# CONFIG_PACKAGE_libupm-kxtj3 is not set\n# CONFIG_PACKAGE_libupm-kxtj3-python3 is not set\n# CONFIG_PACKAGE_libupm-l298 is not set\n# CONFIG_PACKAGE_libupm-l298-python3 is not set\n# CONFIG_PACKAGE_libupm-l3gd20 is not set\n# CONFIG_PACKAGE_libupm-l3gd20-python3 is not set\n# CONFIG_PACKAGE_libupm-lcd is not set\n# CONFIG_PACKAGE_libupm-lcd-python3 is not set\n# CONFIG_PACKAGE_libupm-lcdks is not set\n# CONFIG_PACKAGE_libupm-lcdks-python3 is not set\n# CONFIG_PACKAGE_libupm-lcm1602 is not set\n# CONFIG_PACKAGE_libupm-lcm1602-python3 is not set\n# CONFIG_PACKAGE_libupm-ldt0028 is not set\n# CONFIG_PACKAGE_libupm-ldt0028-python3 is not set\n# CONFIG_PACKAGE_libupm-led is not set\n# CONFIG_PACKAGE_libupm-led-python3 is not set\n# CONFIG_PACKAGE_libupm-lidarlitev3 is not set\n# CONFIG_PACKAGE_libupm-lidarlitev3-python3 is not set\n# CONFIG_PACKAGE_libupm-light is not set\n# CONFIG_PACKAGE_libupm-light-python3 is not set\n# CONFIG_PACKAGE_libupm-linefinder is not set\n# CONFIG_PACKAGE_libupm-linefinder-python3 is not set\n# CONFIG_PACKAGE_libupm-lis2ds12 is not set\n# CONFIG_PACKAGE_libupm-lis2ds12-python3 is not set\n# CONFIG_PACKAGE_libupm-lis3dh is not set\n# CONFIG_PACKAGE_libupm-lis3dh-python3 is not set\n# CONFIG_PACKAGE_libupm-lm35 is not set\n# CONFIG_PACKAGE_libupm-lm35-python3 is not set\n# CONFIG_PACKAGE_libupm-lol is not set\n# CONFIG_PACKAGE_libupm-lol-python3 is not set\n# CONFIG_PACKAGE_libupm-loudness is not set\n# CONFIG_PACKAGE_libupm-loudness-python3 is not set\n# CONFIG_PACKAGE_libupm-lp8860 is not set\n# CONFIG_PACKAGE_libupm-lp8860-python3 is not set\n# CONFIG_PACKAGE_libupm-lpd8806 is not set\n# CONFIG_PACKAGE_libupm-lpd8806-python3 is not set\n# CONFIG_PACKAGE_libupm-lsm303agr is not set\n# CONFIG_PACKAGE_libupm-lsm303agr-python3 is not set\n# CONFIG_PACKAGE_libupm-lsm303d is not set\n# CONFIG_PACKAGE_libupm-lsm303d-python3 is not set\n# CONFIG_PACKAGE_libupm-lsm303dlh is not set\n# CONFIG_PACKAGE_libupm-lsm303dlh-python3 is not set\n# CONFIG_PACKAGE_libupm-lsm6ds3h is not set\n# CONFIG_PACKAGE_libupm-lsm6ds3h-python3 is not set\n# CONFIG_PACKAGE_libupm-lsm6dsl is not set\n# CONFIG_PACKAGE_libupm-lsm6dsl-python3 is not set\n# CONFIG_PACKAGE_libupm-lsm9ds0 is not set\n# CONFIG_PACKAGE_libupm-lsm9ds0-python3 is not set\n# CONFIG_PACKAGE_libupm-m24lr64e is not set\n# CONFIG_PACKAGE_libupm-m24lr64e-python3 is not set\n# CONFIG_PACKAGE_libupm-mag3110 is not set\n# CONFIG_PACKAGE_libupm-mag3110-python3 is not set\n# CONFIG_PACKAGE_libupm-max30100 is not set\n# CONFIG_PACKAGE_libupm-max30100-python3 is not set\n# CONFIG_PACKAGE_libupm-max31723 is not set\n# CONFIG_PACKAGE_libupm-max31723-python3 is not set\n# CONFIG_PACKAGE_libupm-max31855 is not set\n# CONFIG_PACKAGE_libupm-max31855-python3 is not set\n# CONFIG_PACKAGE_libupm-max44000 is not set\n# CONFIG_PACKAGE_libupm-max44000-python3 is not set\n# CONFIG_PACKAGE_libupm-max44009 is not set\n# CONFIG_PACKAGE_libupm-max44009-python3 is not set\n# CONFIG_PACKAGE_libupm-max5487 is not set\n# CONFIG_PACKAGE_libupm-max5487-python3 is not set\n# CONFIG_PACKAGE_libupm-maxds3231m is not set\n# CONFIG_PACKAGE_libupm-maxds3231m-python3 is not set\n# CONFIG_PACKAGE_libupm-maxsonarez is not set\n# CONFIG_PACKAGE_libupm-maxsonarez-python3 is not set\n# CONFIG_PACKAGE_libupm-mb704x is not set\n# CONFIG_PACKAGE_libupm-mb704x-python3 is not set\n# CONFIG_PACKAGE_libupm-mcp2515 is not set\n# CONFIG_PACKAGE_libupm-mcp2515-python3 is not set\n# CONFIG_PACKAGE_libupm-mcp9808 is not set\n# CONFIG_PACKAGE_libupm-mcp9808-python3 is not set\n# CONFIG_PACKAGE_libupm-md is not set\n# CONFIG_PACKAGE_libupm-md-python3 is not set\n# CONFIG_PACKAGE_libupm-mg811 is not set\n# CONFIG_PACKAGE_libupm-mg811-python3 is not set\n# CONFIG_PACKAGE_libupm-mhz16 is not set\n# CONFIG_PACKAGE_libupm-mhz16-python3 is not set\n# CONFIG_PACKAGE_libupm-mic is not set\n# CONFIG_PACKAGE_libupm-mic-python3 is not set\n# CONFIG_PACKAGE_libupm-micsv89 is not set\n# CONFIG_PACKAGE_libupm-micsv89-python3 is not set\n# CONFIG_PACKAGE_libupm-mlx90614 is not set\n# CONFIG_PACKAGE_libupm-mlx90614-python3 is not set\n# CONFIG_PACKAGE_libupm-mma7361 is not set\n# CONFIG_PACKAGE_libupm-mma7361-python3 is not set\n# CONFIG_PACKAGE_libupm-mma7455 is not set\n# CONFIG_PACKAGE_libupm-mma7455-python3 is not set\n# CONFIG_PACKAGE_libupm-mma7660 is not set\n# CONFIG_PACKAGE_libupm-mma7660-python3 is not set\n# CONFIG_PACKAGE_libupm-mma8x5x is not set\n# CONFIG_PACKAGE_libupm-mma8x5x-python3 is not set\n# CONFIG_PACKAGE_libupm-mmc35240 is not set\n# CONFIG_PACKAGE_libupm-mmc35240-python3 is not set\n# CONFIG_PACKAGE_libupm-moisture is not set\n# CONFIG_PACKAGE_libupm-moisture-python3 is not set\n# CONFIG_PACKAGE_libupm-mpl3115a2 is not set\n# CONFIG_PACKAGE_libupm-mpl3115a2-python3 is not set\n# CONFIG_PACKAGE_libupm-mpr121 is not set\n# CONFIG_PACKAGE_libupm-mpr121-python3 is not set\n# CONFIG_PACKAGE_libupm-mpu9150 is not set\n# CONFIG_PACKAGE_libupm-mpu9150-python3 is not set\n# CONFIG_PACKAGE_libupm-mq303a is not set\n# CONFIG_PACKAGE_libupm-mq303a-python3 is not set\n# CONFIG_PACKAGE_libupm-ms5611 is not set\n# CONFIG_PACKAGE_libupm-ms5611-python3 is not set\n# CONFIG_PACKAGE_libupm-ms5803 is not set\n# CONFIG_PACKAGE_libupm-ms5803-python3 is not set\n# CONFIG_PACKAGE_libupm-my9221 is not set\n# CONFIG_PACKAGE_libupm-my9221-python3 is not set\n# CONFIG_PACKAGE_libupm-nlgpio16 is not set\n# CONFIG_PACKAGE_libupm-nlgpio16-python3 is not set\n# CONFIG_PACKAGE_libupm-nmea_gps is not set\n# CONFIG_PACKAGE_libupm-nmea_gps-python3 is not set\n# CONFIG_PACKAGE_libupm-nrf24l01 is not set\n# CONFIG_PACKAGE_libupm-nrf24l01-python3 is not set\n# CONFIG_PACKAGE_libupm-nrf8001 is not set\n# CONFIG_PACKAGE_libupm-nrf8001-python3 is not set\n# CONFIG_PACKAGE_libupm-nunchuck is not set\n# CONFIG_PACKAGE_libupm-nunchuck-python3 is not set\n# CONFIG_PACKAGE_libupm-o2 is not set\n# CONFIG_PACKAGE_libupm-o2-python3 is not set\n# CONFIG_PACKAGE_libupm-otp538u is not set\n# CONFIG_PACKAGE_libupm-otp538u-python3 is not set\n# CONFIG_PACKAGE_libupm-ozw is not set\n# CONFIG_PACKAGE_libupm-ozw-python3 is not set\n# CONFIG_PACKAGE_libupm-p9813 is not set\n# CONFIG_PACKAGE_libupm-p9813-python3 is not set\n# CONFIG_PACKAGE_libupm-pca9685 is not set\n# CONFIG_PACKAGE_libupm-pca9685-python3 is not set\n# CONFIG_PACKAGE_libupm-pn532 is not set\n# CONFIG_PACKAGE_libupm-pn532-python3 is not set\n# CONFIG_PACKAGE_libupm-ppd42ns is not set\n# CONFIG_PACKAGE_libupm-ppd42ns-python3 is not set\n# CONFIG_PACKAGE_libupm-pulsensor is not set\n# CONFIG_PACKAGE_libupm-pulsensor-python3 is not set\n# CONFIG_PACKAGE_libupm-relay is not set\n# CONFIG_PACKAGE_libupm-relay-python3 is not set\n# CONFIG_PACKAGE_libupm-rf22 is not set\n# CONFIG_PACKAGE_libupm-rf22-python3 is not set\n# CONFIG_PACKAGE_libupm-rfr359f is not set\n# CONFIG_PACKAGE_libupm-rfr359f-python3 is not set\n# CONFIG_PACKAGE_libupm-rgbringcoder is not set\n# CONFIG_PACKAGE_libupm-rgbringcoder-python3 is not set\n# CONFIG_PACKAGE_libupm-rhusb is not set\n# CONFIG_PACKAGE_libupm-rhusb-python3 is not set\n# CONFIG_PACKAGE_libupm-rn2903 is not set\n# CONFIG_PACKAGE_libupm-rn2903-python3 is not set\n# CONFIG_PACKAGE_libupm-rotary is not set\n# CONFIG_PACKAGE_libupm-rotary-python3 is not set\n# CONFIG_PACKAGE_libupm-rotaryencoder is not set\n# CONFIG_PACKAGE_libupm-rotaryencoder-python3 is not set\n# CONFIG_PACKAGE_libupm-rpr220 is not set\n# CONFIG_PACKAGE_libupm-rpr220-python3 is not set\n# CONFIG_PACKAGE_libupm-rsc is not set\n# CONFIG_PACKAGE_libupm-rsc-python3 is not set\n# CONFIG_PACKAGE_libupm-scam is not set\n# CONFIG_PACKAGE_libupm-scam-python3 is not set\n# CONFIG_PACKAGE_libupm-sensortemplate is not set\n# CONFIG_PACKAGE_libupm-sensortemplate-python3 is not set\n# CONFIG_PACKAGE_libupm-servo is not set\n# CONFIG_PACKAGE_libupm-servo-python3 is not set\n# CONFIG_PACKAGE_libupm-sht1x is not set\n# CONFIG_PACKAGE_libupm-sht1x-python3 is not set\n# CONFIG_PACKAGE_libupm-si1132 is not set\n# CONFIG_PACKAGE_libupm-si1132-python3 is not set\n# CONFIG_PACKAGE_libupm-si114x is not set\n# CONFIG_PACKAGE_libupm-si114x-python3 is not set\n# CONFIG_PACKAGE_libupm-si7005 is not set\n# CONFIG_PACKAGE_libupm-si7005-python3 is not set\n# CONFIG_PACKAGE_libupm-slide is not set\n# CONFIG_PACKAGE_libupm-slide-python3 is not set\n# CONFIG_PACKAGE_libupm-sm130 is not set\n# CONFIG_PACKAGE_libupm-sm130-python3 is not set\n# CONFIG_PACKAGE_libupm-smartdrive is not set\n# CONFIG_PACKAGE_libupm-smartdrive-python3 is not set\n# CONFIG_PACKAGE_libupm-speaker is not set\n# CONFIG_PACKAGE_libupm-speaker-python3 is not set\n# CONFIG_PACKAGE_libupm-ssd1351 is not set\n# CONFIG_PACKAGE_libupm-ssd1351-python3 is not set\n# CONFIG_PACKAGE_libupm-st7735 is not set\n# CONFIG_PACKAGE_libupm-st7735-python3 is not set\n# CONFIG_PACKAGE_libupm-stepmotor is not set\n# CONFIG_PACKAGE_libupm-stepmotor-python3 is not set\n# CONFIG_PACKAGE_libupm-sx1276 is not set\n# CONFIG_PACKAGE_libupm-sx1276-python3 is not set\n# CONFIG_PACKAGE_libupm-sx6119 is not set\n# CONFIG_PACKAGE_libupm-sx6119-python3 is not set\n# CONFIG_PACKAGE_libupm-t3311 is not set\n# CONFIG_PACKAGE_libupm-t3311-python3 is not set\n# CONFIG_PACKAGE_libupm-t6713 is not set\n# CONFIG_PACKAGE_libupm-t6713-python3 is not set\n# CONFIG_PACKAGE_libupm-ta12200 is not set\n# CONFIG_PACKAGE_libupm-ta12200-python3 is not set\n# CONFIG_PACKAGE_libupm-tca9548a is not set\n# CONFIG_PACKAGE_libupm-tca9548a-python3 is not set\n# CONFIG_PACKAGE_libupm-tcs3414cs is not set\n# CONFIG_PACKAGE_libupm-tcs3414cs-python3 is not set\n# CONFIG_PACKAGE_libupm-tcs37727 is not set\n# CONFIG_PACKAGE_libupm-tcs37727-python3 is not set\n# CONFIG_PACKAGE_libupm-teams is not set\n# CONFIG_PACKAGE_libupm-teams-python3 is not set\n# CONFIG_PACKAGE_libupm-temperature is not set\n# CONFIG_PACKAGE_libupm-temperature-python3 is not set\n# CONFIG_PACKAGE_libupm-tex00 is not set\n# CONFIG_PACKAGE_libupm-tex00-python3 is not set\n# CONFIG_PACKAGE_libupm-th02 is not set\n# CONFIG_PACKAGE_libupm-th02-python3 is not set\n# CONFIG_PACKAGE_libupm-tm1637 is not set\n# CONFIG_PACKAGE_libupm-tm1637-python3 is not set\n# CONFIG_PACKAGE_libupm-tmp006 is not set\n# CONFIG_PACKAGE_libupm-tmp006-python3 is not set\n# CONFIG_PACKAGE_libupm-tsl2561 is not set\n# CONFIG_PACKAGE_libupm-tsl2561-python3 is not set\n# CONFIG_PACKAGE_libupm-ttp223 is not set\n# CONFIG_PACKAGE_libupm-ttp223-python3 is not set\n# CONFIG_PACKAGE_libupm-uartat is not set\n# CONFIG_PACKAGE_libupm-uartat-python3 is not set\n# CONFIG_PACKAGE_libupm-uln200xa is not set\n# CONFIG_PACKAGE_libupm-uln200xa-python3 is not set\n# CONFIG_PACKAGE_libupm-ultrasonic is not set\n# CONFIG_PACKAGE_libupm-ultrasonic-python3 is not set\n# CONFIG_PACKAGE_libupm-urm37 is not set\n# CONFIG_PACKAGE_libupm-urm37-python3 is not set\n# CONFIG_PACKAGE_libupm-utilities is not set\n# CONFIG_PACKAGE_libupm-utilities-python3 is not set\n# CONFIG_PACKAGE_libupm-vcap is not set\n# CONFIG_PACKAGE_libupm-vcap-python3 is not set\n# CONFIG_PACKAGE_libupm-vdiv is not set\n# CONFIG_PACKAGE_libupm-vdiv-python3 is not set\n# CONFIG_PACKAGE_libupm-veml6070 is not set\n# CONFIG_PACKAGE_libupm-veml6070-python3 is not set\n# CONFIG_PACKAGE_libupm-water is not set\n# CONFIG_PACKAGE_libupm-water-python3 is not set\n# CONFIG_PACKAGE_libupm-waterlevel is not set\n# CONFIG_PACKAGE_libupm-waterlevel-python3 is not set\n# CONFIG_PACKAGE_libupm-wfs is not set\n# CONFIG_PACKAGE_libupm-wfs-python3 is not set\n# CONFIG_PACKAGE_libupm-wheelencoder is not set\n# CONFIG_PACKAGE_libupm-wheelencoder-python3 is not set\n# CONFIG_PACKAGE_libupm-wt5001 is not set\n# CONFIG_PACKAGE_libupm-wt5001-python3 is not set\n# CONFIG_PACKAGE_libupm-xbee is not set\n# CONFIG_PACKAGE_libupm-xbee-python3 is not set\n# CONFIG_PACKAGE_libupm-yg1006 is not set\n# CONFIG_PACKAGE_libupm-yg1006-python3 is not set\n# CONFIG_PACKAGE_libupm-zfm20 is not set\n# CONFIG_PACKAGE_libupm-zfm20-python3 is not set\n# end of IoT\n\n#\n# Languages\n#\n# CONFIG_PACKAGE_libyaml is not set\n# end of Languages\n\n#\n# LibElektra\n#\n# CONFIG_PACKAGE_libelektra-core is not set\n# CONFIG_PACKAGE_libelektra-cpp is not set\n# CONFIG_PACKAGE_libelektra-crypto is not set\n# CONFIG_PACKAGE_libelektra-curlget is not set\n# CONFIG_PACKAGE_libelektra-dbus is not set\n# CONFIG_PACKAGE_libelektra-ev is not set\n# CONFIG_PACKAGE_libelektra-extra is not set\n# CONFIG_PACKAGE_libelektra-lua is not set\n# CONFIG_PACKAGE_libelektra-plugins is not set\n# CONFIG_PACKAGE_libelektra-python3 is not set\n# CONFIG_PACKAGE_libelektra-resolvers is not set\n# CONFIG_PACKAGE_libelektra-uv is not set\n# CONFIG_PACKAGE_libelektra-xerces is not set\n# CONFIG_PACKAGE_libelektra-xml is not set\n# CONFIG_PACKAGE_libelektra-yajl is not set\n# CONFIG_PACKAGE_libelektra-yamlcpp is not set\n# CONFIG_PACKAGE_libelektra-zmq is not set\n# end of LibElektra\n\n#\n# Networking\n#\n# CONFIG_PACKAGE_libdcwproto is not set\n# CONFIG_PACKAGE_libdcwsocket is not set\n# CONFIG_PACKAGE_libsctp is not set\n# CONFIG_PACKAGE_libuhttpd-mbedtls is not set\n# CONFIG_PACKAGE_libuhttpd-nossl is not set\n# CONFIG_PACKAGE_libuhttpd-openssl is not set\n# CONFIG_PACKAGE_libuhttpd-wolfssl is not set\n# CONFIG_PACKAGE_libulfius-gnutls is not set\n# CONFIG_PACKAGE_libulfius-nossl is not set\nCONFIG_PACKAGE_libunbound=y\n# CONFIG_PACKAGE_libunbound_dnscrypt is not set\nCONFIG_PACKAGE_libunbound_ipset=y\nCONFIG_PACKAGE_libunbound_libevent=y\nCONFIG_PACKAGE_libunbound_libpthread=y\n# CONFIG_PACKAGE_libunbound_nghttp2 is not set\n# CONFIG_PACKAGE_libunbound_pythonmodule is not set\n# CONFIG_PACKAGE_libunbound_subnet is not set\n# CONFIG_PACKAGE_libunbound_dnstap is not set\n# CONFIG_PACKAGE_libuwsc-mbedtls is not set\n# CONFIG_PACKAGE_libuwsc-nossl is not set\n# CONFIG_PACKAGE_libuwsc-openssl is not set\n# CONFIG_PACKAGE_libuwsc-wolfssl is not set\n# end of Networking\n\n#\n# SSL\n#\nCONFIG_PACKAGE_libgnutls=y\n\n#\n# Configuration\n#\nCONFIG_GNUTLS_DTLS_SRTP=y\nCONFIG_GNUTLS_ALPN=y\nCONFIG_GNUTLS_OCSP=y\n# CONFIG_GNUTLS_CRYPTODEV is not set\nCONFIG_GNUTLS_HEARTBEAT=y\n# CONFIG_GNUTLS_SRP is not set\nCONFIG_GNUTLS_PSK=y\nCONFIG_GNUTLS_ANON=y\n# CONFIG_GNUTLS_TPM is not set\n# CONFIG_GNUTLS_PKCS11 is not set\n# CONFIG_GNUTLS_EXT_LIBTASN1 is not set\n# end of Configuration\n\n# CONFIG_PACKAGE_libgnutls-dane is not set\nCONFIG_PACKAGE_libmbedtls=y\n# CONFIG_LIBMBEDTLS_DEBUG_C is not set\n# CONFIG_LIBMBEDTLS_HKDF_C is not set\n# CONFIG_PACKAGE_libnss is not set\nCONFIG_PACKAGE_libopenssl=y\n\n#\n# Build Options\n#\n# CONFIG_OPENSSL_OPTIMIZE_SPEED is not set\nCONFIG_OPENSSL_WITH_ASM=y\nCONFIG_OPENSSL_WITH_DEPRECATED=y\n# CONFIG_OPENSSL_NO_DEPRECATED is not set\nCONFIG_OPENSSL_WITH_ERROR_MESSAGES=y\n\n#\n# Protocol Support\n#\nCONFIG_OPENSSL_WITH_TLS13=y\n# CONFIG_OPENSSL_WITH_DTLS is not set\n# CONFIG_OPENSSL_WITH_NPN is not set\nCONFIG_OPENSSL_WITH_SRP=y\nCONFIG_OPENSSL_WITH_CMS=y\n\n#\n# Algorithm Selection\n#\n# CONFIG_OPENSSL_WITH_EC2M is not set\nCONFIG_OPENSSL_WITH_CHACHA_POLY1305=y\n# CONFIG_OPENSSL_PREFER_CHACHA_OVER_GCM is not set\nCONFIG_OPENSSL_WITH_PSK=y\n\n#\n# Less commonly used build options\n#\n# CONFIG_OPENSSL_WITH_ARIA is not set\n# CONFIG_OPENSSL_WITH_CAMELLIA is not set\n# CONFIG_OPENSSL_WITH_IDEA is not set\n# CONFIG_OPENSSL_WITH_SEED is not set\n# CONFIG_OPENSSL_WITH_SM234 is not set\n# CONFIG_OPENSSL_WITH_BLAKE2 is not set\n# CONFIG_OPENSSL_WITH_MDC2 is not set\n# CONFIG_OPENSSL_WITH_WHIRLPOOL is not set\n# CONFIG_OPENSSL_WITH_COMPRESSION is not set\n# CONFIG_OPENSSL_WITH_RFC3779 is not set\n\n#\n# Engine/Hardware Support\n#\nCONFIG_OPENSSL_ENGINE=y\n# CONFIG_OPENSSL_ENGINE_BUILTIN is not set\n# CONFIG_PACKAGE_libopenssl-afalg is not set\n# CONFIG_PACKAGE_libopenssl-afalg_sync is not set\nCONFIG_PACKAGE_libopenssl-conf=y\n# CONFIG_PACKAGE_libopenssl-devcrypto is not set\n# CONFIG_PACKAGE_libopenssl-gost_engine is not set\nCONFIG_PACKAGE_libwolfssl=y\nCONFIG_WOLFSSL_HAS_AES_CCM=y\nCONFIG_WOLFSSL_HAS_CHACHA_POLY=y\nCONFIG_WOLFSSL_HAS_DH=y\nCONFIG_WOLFSSL_HAS_ARC4=y\nCONFIG_WOLFSSL_HAS_CERTGEN=y\nCONFIG_WOLFSSL_HAS_TLSV10=y\nCONFIG_WOLFSSL_HAS_TLSV13=y\nCONFIG_WOLFSSL_HAS_SESSION_TICKET=y\n# CONFIG_WOLFSSL_HAS_DTLS is not set\nCONFIG_WOLFSSL_HAS_OCSP=y\nCONFIG_WOLFSSL_HAS_WPAS=y\n# CONFIG_WOLFSSL_HAS_ECC25519 is not set\n# CONFIG_WOLFSSL_HAS_OPENVPN is not set\nCONFIG_WOLFSSL_HAS_NO_HW=y\n# CONFIG_WOLFSSL_HAS_AFALG is not set\n# CONFIG_WOLFSSL_HAS_DEVCRYPTO_CBC is not set\n# CONFIG_WOLFSSL_HAS_DEVCRYPTO_AES is not set\n# CONFIG_WOLFSSL_HAS_DEVCRYPTO_FULL is not set\n# end of SSL\n\n#\n# Sound\n#\n# CONFIG_PACKAGE_alsa-ucm-conf is not set\n# CONFIG_PACKAGE_liblo is not set\n# end of Sound\n\n#\n# Telephony\n#\n# CONFIG_PACKAGE_bcg729 is not set\n# CONFIG_PACKAGE_dahdi-tools-libtonezone is not set\n# CONFIG_PACKAGE_gsmlib is not set\n# CONFIG_PACKAGE_libctb is not set\n# CONFIG_PACKAGE_libfreetdm is not set\n# CONFIG_PACKAGE_libiksemel is not set\n# CONFIG_PACKAGE_libks is not set\n# CONFIG_PACKAGE_libosip2 is not set\n# CONFIG_PACKAGE_libpj is not set\n# CONFIG_PACKAGE_libpjlib-util is not set\n# CONFIG_PACKAGE_libpjmedia is not set\n# CONFIG_PACKAGE_libpjnath is not set\n# CONFIG_PACKAGE_libpjsip is not set\n# CONFIG_PACKAGE_libpjsip-simple is not set\n# CONFIG_PACKAGE_libpjsip-ua is not set\n# CONFIG_PACKAGE_libpjsua is not set\n# CONFIG_PACKAGE_libpjsua2 is not set\n# CONFIG_PACKAGE_libre is not set\n# CONFIG_PACKAGE_librem is not set\n# CONFIG_PACKAGE_libspandsp is not set\n# CONFIG_PACKAGE_libspandsp3 is not set\n# CONFIG_PACKAGE_libsrtp2 is not set\n# CONFIG_PACKAGE_signalwire-client-c is not set\n# CONFIG_PACKAGE_sofia-sip is not set\n# end of Telephony\n\n#\n# libimobiledevice\n#\n# CONFIG_PACKAGE_libimobiledevice is not set\n# CONFIG_PACKAGE_libirecovery is not set\n# CONFIG_PACKAGE_libplist is not set\n# CONFIG_PACKAGE_libusbmuxd is not set\n# end of libimobiledevice\n\n# CONFIG_PACKAGE_acsccid is not set\n# CONFIG_PACKAGE_alsa-lib is not set\n# CONFIG_PACKAGE_argp-standalone is not set\n# CONFIG_PACKAGE_bind-libs is not set\n# CONFIG_PACKAGE_bluez-libs is not set\n# CONFIG_PACKAGE_boost is not set\n# CONFIG_boost-context-exclude is not set\n# CONFIG_boost-coroutine-exclude is not set\n# CONFIG_boost-fiber-exclude is not set\n# CONFIG_PACKAGE_boringssl is not set\n# CONFIG_PACKAGE_cJSON is not set\n# CONFIG_PACKAGE_ccid is not set\n# CONFIG_PACKAGE_check is not set\nCONFIG_PACKAGE_confuse=y\n# CONFIG_PACKAGE_czmq is not set\n# CONFIG_PACKAGE_dtndht is not set\n# CONFIG_PACKAGE_getdns is not set\n# CONFIG_PACKAGE_giflib is not set\n# CONFIG_PACKAGE_glib2 is not set\n# CONFIG_PACKAGE_google-authenticator-libpam is not set\n# CONFIG_PACKAGE_hidapi is not set\n# CONFIG_PACKAGE_ibrcommon is not set\n# CONFIG_PACKAGE_ibrdtn is not set\n# CONFIG_PACKAGE_icu is not set\n# CONFIG_PACKAGE_icu-data-tools is not set\n# CONFIG_PACKAGE_icu-full-data is not set\n# CONFIG_PACKAGE_jansson is not set\n# CONFIG_PACKAGE_json-glib is not set\n# CONFIG_PACKAGE_jsoncpp is not set\n# CONFIG_PACKAGE_knot-libs is not set\n# CONFIG_PACKAGE_knot-libzscanner is not set\n# CONFIG_PACKAGE_libaio is not set\n# CONFIG_PACKAGE_libantlr3c is not set\n# CONFIG_PACKAGE_libao is not set\n# CONFIG_PACKAGE_libapparmor is not set\n# CONFIG_PACKAGE_libapr is not set\n# CONFIG_PACKAGE_libaprutil is not set\n# CONFIG_PACKAGE_libarchive is not set\n# CONFIG_PACKAGE_libarchive-noopenssl is not set\n# CONFIG_PACKAGE_libasm is not set\n# CONFIG_PACKAGE_libassuan is not set\n# CONFIG_PACKAGE_libatasmart is not set\n# CONFIG_PACKAGE_libaudit is not set\n# CONFIG_PACKAGE_libauparse is not set\nCONFIG_PACKAGE_libavahi-client=y\n# CONFIG_PACKAGE_libavahi-compat-libdnssd is not set\nCONFIG_PACKAGE_libavahi-dbus-support=y\n# CONFIG_PACKAGE_libavahi-nodbus-support is not set\n# CONFIG_PACKAGE_libbfd is not set\nCONFIG_PACKAGE_libblkid=y\nCONFIG_PACKAGE_libblobmsg-json=y\n# CONFIG_PACKAGE_libbpf is not set\n# CONFIG_PACKAGE_libbsd is not set\nCONFIG_PACKAGE_libcap=y\n# CONFIG_PACKAGE_libcap-bin is not set\n# CONFIG_PACKAGE_libcap-ng is not set\nCONFIG_PACKAGE_libcares=y\nCONFIG_PACKAGE_libcbor=y\n# CONFIG_PACKAGE_libcgroup is not set\n# CONFIG_PACKAGE_libcharset is not set\n# CONFIG_PACKAGE_libcoap is not set\nCONFIG_PACKAGE_libcomerr=y\n# CONFIG_PACKAGE_libconfig is not set\n# CONFIG_PACKAGE_libctf is not set\nCONFIG_PACKAGE_libcurl=y\n\n#\n# SSL support\n#\n# CONFIG_LIBCURL_MBEDTLS is not set\nCONFIG_LIBCURL_WOLFSSL=y\n# CONFIG_LIBCURL_OPENSSL is not set\n# CONFIG_LIBCURL_GNUTLS is not set\n# CONFIG_LIBCURL_NOSSL is not set\n\n#\n# Supported protocols\n#\n# CONFIG_LIBCURL_DICT is not set\nCONFIG_LIBCURL_FILE=y\nCONFIG_LIBCURL_FTP=y\n# CONFIG_LIBCURL_GOPHER is not set\nCONFIG_LIBCURL_HTTP=y\nCONFIG_LIBCURL_COOKIES=y\n# CONFIG_LIBCURL_IMAP is not set\n# CONFIG_LIBCURL_LDAP is not set\n# CONFIG_LIBCURL_POP3 is not set\n# CONFIG_LIBCURL_RTSP is not set\n# CONFIG_LIBCURL_SSH2 is not set\nCONFIG_LIBCURL_NO_SMB=\"!\"\n# CONFIG_LIBCURL_SMTP is not set\n# CONFIG_LIBCURL_TELNET is not set\n# CONFIG_LIBCURL_TFTP is not set\n# CONFIG_LIBCURL_NGHTTP2 is not set\n\n#\n# Miscellaneous\n#\nCONFIG_LIBCURL_PROXY=y\n# CONFIG_LIBCURL_CRYPTO_AUTH is not set\n# CONFIG_LIBCURL_TLS_SRP is not set\n# CONFIG_LIBCURL_LIBIDN2 is not set\n# CONFIG_LIBCURL_THREADED_RESOLVER is not set\n# CONFIG_LIBCURL_ZLIB is not set\n# CONFIG_LIBCURL_ZSTD is not set\n# CONFIG_LIBCURL_UNIX_SOCKETS is not set\n# CONFIG_LIBCURL_LIBCURL_OPTION is not set\n# CONFIG_LIBCURL_VERBOSE is not set\nCONFIG_PACKAGE_libdaemon=y\n# CONFIG_PACKAGE_libdaq is not set\n# CONFIG_PACKAGE_libdaq3 is not set\n# CONFIG_PACKAGE_libdb47 is not set\n# CONFIG_PACKAGE_libdb47xx is not set\n# CONFIG_PACKAGE_libdbi is not set\nCONFIG_PACKAGE_libdbus=y\nCONFIG_PACKAGE_libdevmapper=y\n# CONFIG_PACKAGE_libdevmapper-selinux is not set\n# CONFIG_PACKAGE_libdmapsharing is not set\n# CONFIG_PACKAGE_libdnet is not set\n# CONFIG_PACKAGE_libdrm is not set\n# CONFIG_PACKAGE_libdw is not set\n# CONFIG_PACKAGE_libecdsautil is not set\n# CONFIG_PACKAGE_libedit is not set\n# CONFIG_PACKAGE_libelf is not set\n# CONFIG_PACKAGE_libesmtp is not set\n# CONFIG_PACKAGE_libestr is not set\nCONFIG_PACKAGE_libev=y\nCONFIG_PACKAGE_libevdev=y\nCONFIG_PACKAGE_libevent2=y\n# CONFIG_PACKAGE_libevent2-core is not set\n# CONFIG_PACKAGE_libevent2-extra is not set\n# CONFIG_PACKAGE_libevent2-openssl is not set\n# CONFIG_PACKAGE_libevent2-pthreads is not set\nCONFIG_PACKAGE_libexif=y\nCONFIG_PACKAGE_libexpat=y\n# CONFIG_PACKAGE_libexslt is not set\nCONFIG_PACKAGE_libext2fs=y\n# CONFIG_PACKAGE_libextractor is not set\nCONFIG_PACKAGE_libf2fs=y\n# CONFIG_PACKAGE_libf2fs-selinux is not set\n# CONFIG_PACKAGE_libfaad2 is not set\n# CONFIG_PACKAGE_libfastjson is not set\nCONFIG_PACKAGE_libfdisk=y\n# CONFIG_PACKAGE_libfdt is not set\n# CONFIG_PACKAGE_libffi is not set\nCONFIG_PACKAGE_libffmpeg-audio-dec=y\n# CONFIG_PACKAGE_libffmpeg-custom is not set\n# CONFIG_PACKAGE_libffmpeg-full is not set\n# CONFIG_PACKAGE_libffmpeg-mini is not set\nCONFIG_PACKAGE_libfido2=y\nCONFIG_PACKAGE_libflac=y\n# CONFIG_PACKAGE_libfmt is not set\n# CONFIG_PACKAGE_libfreetype is not set\n# CONFIG_PACKAGE_libfstrm is not set\n# CONFIG_PACKAGE_libftdi is not set\n# CONFIG_PACKAGE_libftdi1 is not set\n# CONFIG_PACKAGE_libgabe is not set\n# CONFIG_PACKAGE_libgcrypt is not set\nCONFIG_PACKAGE_libgd=y\n# CONFIG_LIBGD_TIFF is not set\n# CONFIG_LIBGD_FREETYPE is not set\n# CONFIG_PACKAGE_libgd-full is not set\n# CONFIG_PACKAGE_libgdbm is not set\n# CONFIG_PACKAGE_libgee is not set\nCONFIG_PACKAGE_libgmp=y\n# CONFIG_PACKAGE_libgnurl is not set\n# CONFIG_PACKAGE_libgpg-error is not set\n# CONFIG_PACKAGE_libgpgme is not set\n# CONFIG_PACKAGE_libgpgmepp is not set\n# CONFIG_PACKAGE_libgphoto2 is not set\n# CONFIG_PACKAGE_libgpiod is not set\n# CONFIG_PACKAGE_libgps is not set\n# CONFIG_PACKAGE_libh2o is not set\n# CONFIG_PACKAGE_libh2o-evloop is not set\n# CONFIG_PACKAGE_libhamlib is not set\n# CONFIG_PACKAGE_libhavege is not set\n# CONFIG_PACKAGE_libhiredis is not set\n# CONFIG_PACKAGE_libhttp-parser is not set\n# CONFIG_PACKAGE_libhwloc is not set\n# CONFIG_PACKAGE_libi2c is not set\n# CONFIG_PACKAGE_libical is not set\n# CONFIG_PACKAGE_libiconv is not set\n# CONFIG_PACKAGE_libiconv-full is not set\nCONFIG_PACKAGE_libid3tag=y\n# CONFIG_PACKAGE_libidn is not set\n# CONFIG_PACKAGE_libidn2 is not set\n# CONFIG_PACKAGE_libiio is not set\n# CONFIG_PACKAGE_libinotifytools is not set\n# CONFIG_PACKAGE_libinput is not set\n# CONFIG_PACKAGE_libintl-full is not set\n# CONFIG_PACKAGE_libipfs-http-client is not set\n# CONFIG_PACKAGE_libiw is not set\nCONFIG_PACKAGE_libiwinfo=y\nCONFIG_PACKAGE_libjpeg-turbo=y\nCONFIG_PACKAGE_libjson-c=y\n# CONFIG_PACKAGE_libkeyutils is not set\n# CONFIG_PACKAGE_libkmod is not set\n# CONFIG_PACKAGE_libksba is not set\n# CONFIG_PACKAGE_libldns is not set\n# CONFIG_PACKAGE_libleptonica is not set\n# CONFIG_PACKAGE_libloragw is not set\nCONFIG_PACKAGE_libltdl=y\nCONFIG_PACKAGE_liblua=y\n# CONFIG_PACKAGE_liblua5.3 is not set\nCONFIG_PACKAGE_liblucihttp=y\nCONFIG_PACKAGE_liblucihttp-lua=y\nCONFIG_PACKAGE_liblzo=y\n# CONFIG_PACKAGE_libmad is not set\n# CONFIG_PACKAGE_libmagic is not set\n# CONFIG_PACKAGE_libmaxminddb is not set\n# CONFIG_PACKAGE_libmbim is not set\n# CONFIG_PACKAGE_libmcrypt is not set\n# CONFIG_PACKAGE_libmicrohttpd-no-ssl is not set\n# CONFIG_PACKAGE_libmicrohttpd-ssl is not set\n# CONFIG_PACKAGE_libmilter-sendmail is not set\nCONFIG_PACKAGE_libminiupnpc=y\n# CONFIG_PACKAGE_libmms is not set\nCONFIG_PACKAGE_libmnl=y\n# CONFIG_PACKAGE_libmodbus is not set\n# CONFIG_PACKAGE_libmosquitto-nossl is not set\n# CONFIG_PACKAGE_libmosquitto-ssl is not set\nCONFIG_PACKAGE_libmount=y\n# CONFIG_PACKAGE_libmpdclient is not set\n# CONFIG_PACKAGE_libmpeg2 is not set\n# CONFIG_PACKAGE_libmpg123 is not set\nCONFIG_PACKAGE_libnatpmp=y\nCONFIG_PACKAGE_libncurses=y\n# CONFIG_PACKAGE_libndpi is not set\n# CONFIG_PACKAGE_libneon is not set\n# CONFIG_PACKAGE_libnet-1.2.x is not set\n# CONFIG_PACKAGE_libnetconf2 is not set\n# CONFIG_PACKAGE_libnetfilter-acct is not set\n# CONFIG_PACKAGE_libnetfilter-conntrack is not set\n# CONFIG_PACKAGE_libnetfilter-cthelper is not set\n# CONFIG_PACKAGE_libnetfilter-cttimeout is not set\n# CONFIG_PACKAGE_libnetfilter-log is not set\n# CONFIG_PACKAGE_libnetfilter-queue is not set\nCONFIG_PACKAGE_libnetsnmp=y\nCONFIG_PACKAGE_libnettle=y\n\n#\n# Configuration\n#\n# CONFIG_LIBNETTLE_MINI is not set\n# end of Configuration\n\n# CONFIG_PACKAGE_libnewt is not set\n# CONFIG_PACKAGE_libnfnetlink is not set\n# CONFIG_PACKAGE_libnftnl is not set\n# CONFIG_PACKAGE_libnghttp2 is not set\n# CONFIG_PACKAGE_libnl is not set\nCONFIG_PACKAGE_libnl-core=y\n# CONFIG_PACKAGE_libnl-genl is not set\n# CONFIG_PACKAGE_libnl-nf is not set\nCONFIG_PACKAGE_libnl-route=y\nCONFIG_PACKAGE_libnl-tiny=y\n# CONFIG_PACKAGE_libnopoll is not set\n# CONFIG_PACKAGE_libnpth is not set\n# CONFIG_PACKAGE_libnpupnp is not set\nCONFIG_PACKAGE_libogg=y\n# CONFIG_PACKAGE_liboil is not set\n# CONFIG_PACKAGE_libopcodes is not set\n# CONFIG_PACKAGE_libopendkim is not set\n# CONFIG_PACKAGE_libopenobex is not set\n# CONFIG_PACKAGE_libopensc is not set\n# CONFIG_PACKAGE_libopenzwave is not set\n# CONFIG_PACKAGE_liboping is not set\n# CONFIG_PACKAGE_libopus is not set\n# CONFIG_PACKAGE_libopusenc is not set\n# CONFIG_PACKAGE_libopusfile is not set\n# CONFIG_PACKAGE_liborcania is not set\n# CONFIG_PACKAGE_libout123 is not set\n# CONFIG_PACKAGE_libowipcalc is not set\n# CONFIG_PACKAGE_libp11 is not set\n# CONFIG_PACKAGE_libpagekite is not set\n# CONFIG_PACKAGE_libpam is not set\n# CONFIG_PACKAGE_libparted is not set\n# CONFIG_PACKAGE_libpbc is not set\nCONFIG_PACKAGE_libpcap=y\n\n#\n# Configuration\n#\n# CONFIG_PCAP_HAS_USB is not set\n# CONFIG_PCAP_HAS_NETFILTER is not set\n# end of Configuration\n\nCONFIG_PACKAGE_libpci=y\n# CONFIG_PACKAGE_libpciaccess is not set\nCONFIG_PACKAGE_libpcre=y\n# CONFIG_PACKAGE_libpcre16 is not set\n# CONFIG_PACKAGE_libpcre2 is not set\n# CONFIG_PACKAGE_libpcre2-16 is not set\n# CONFIG_PACKAGE_libpcre2-32 is not set\n# CONFIG_PACKAGE_libpcre32 is not set\n# CONFIG_PACKAGE_libpcrecpp is not set\n# CONFIG_PACKAGE_libpcsclite is not set\n# CONFIG_PACKAGE_libpfring is not set\n# CONFIG_PACKAGE_libpkcs11-spy is not set\n# CONFIG_PACKAGE_libpkgconf is not set\nCONFIG_PACKAGE_libpng=y\nCONFIG_PACKAGE_libpopt=y\n# CONFIG_PACKAGE_libpri is not set\n# CONFIG_PACKAGE_libprotobuf-c is not set\n# CONFIG_PACKAGE_libpsl is not set\n# CONFIG_PACKAGE_libqmi is not set\n# CONFIG_PACKAGE_libqrencode is not set\n# CONFIG_PACKAGE_libqrtr-glib is not set\n# CONFIG_PACKAGE_libradcli is not set\n# CONFIG_PACKAGE_libradiotap is not set\nCONFIG_PACKAGE_libreadline=y\n# CONFIG_PACKAGE_libredblack is not set\n# CONFIG_PACKAGE_librouteros is not set\n# CONFIG_PACKAGE_libroxml is not set\nCONFIG_PACKAGE_librrd1=y\n# CONFIG_PACKAGE_librtlsdr is not set\n# CONFIG_PACKAGE_libruby is not set\n# CONFIG_PACKAGE_libsamplerate is not set\n# CONFIG_PACKAGE_libsane is not set\n# CONFIG_PACKAGE_libsasl2 is not set\n# CONFIG_PACKAGE_libsasl2-sasldb is not set\n# CONFIG_PACKAGE_libsearpc is not set\nCONFIG_PACKAGE_libseccomp=y\nCONFIG_PACKAGE_libselinux=y\n# CONFIG_PACKAGE_libsemanage is not set\n# CONFIG_PACKAGE_libsensors is not set\nCONFIG_PACKAGE_libsepol=y\n# CONFIG_PACKAGE_libshout is not set\n# CONFIG_PACKAGE_libshout-full is not set\n# CONFIG_PACKAGE_libshout-nossl is not set\n# CONFIG_PACKAGE_libsispmctl is not set\n# CONFIG_PACKAGE_libslang2 is not set\n# CONFIG_PACKAGE_libslang2-mod-base64 is not set\n# CONFIG_PACKAGE_libslang2-mod-chksum is not set\n# CONFIG_PACKAGE_libslang2-mod-csv is not set\n# CONFIG_PACKAGE_libslang2-mod-fcntl is not set\n# CONFIG_PACKAGE_libslang2-mod-fork is not set\n# CONFIG_PACKAGE_libslang2-mod-histogram is not set\n# CONFIG_PACKAGE_libslang2-mod-iconv is not set\n# CONFIG_PACKAGE_libslang2-mod-json is not set\n# CONFIG_PACKAGE_libslang2-mod-onig is not set\n# CONFIG_PACKAGE_libslang2-mod-pcre is not set\n# CONFIG_PACKAGE_libslang2-mod-png is not set\n# CONFIG_PACKAGE_libslang2-mod-rand is not set\n# CONFIG_PACKAGE_libslang2-mod-select is not set\n# CONFIG_PACKAGE_libslang2-mod-slsmg is not set\n# CONFIG_PACKAGE_libslang2-mod-socket is not set\n# CONFIG_PACKAGE_libslang2-mod-stats is not set\n# CONFIG_PACKAGE_libslang2-mod-sysconf is not set\n# CONFIG_PACKAGE_libslang2-mod-termios is not set\n# CONFIG_PACKAGE_libslang2-mod-varray is not set\n# CONFIG_PACKAGE_libslang2-mod-zlib is not set\n# CONFIG_PACKAGE_libslang2-modules is not set\nCONFIG_PACKAGE_libsmartcols=y\n# CONFIG_PACKAGE_libsndfile is not set\n# CONFIG_PACKAGE_libsoc is not set\n# CONFIG_PACKAGE_libsocks is not set\nCONFIG_PACKAGE_libsodium=y\n\n#\n# Configuration\n#\nCONFIG_LIBSODIUM_MINIMAL=y\n# end of Configuration\n\n# CONFIG_PACKAGE_libsoup is not set\n# CONFIG_PACKAGE_libsoxr is not set\n# CONFIG_PACKAGE_libspeex is not set\n# CONFIG_PACKAGE_libspeexdsp is not set\n# CONFIG_PACKAGE_libspice-server is not set\nCONFIG_PACKAGE_libss=y\n# CONFIG_PACKAGE_libssh is not set\n# CONFIG_PACKAGE_libssh2 is not set\n# CONFIG_PACKAGE_libstoken is not set\n# CONFIG_PACKAGE_libstrophe is not set\n# CONFIG_PACKAGE_libsyn123 is not set\n# CONFIG_PACKAGE_libsysrepo is not set\n# CONFIG_PACKAGE_libtalloc is not set\nCONFIG_PACKAGE_libtasn1=y\n# CONFIG_PACKAGE_libtheora is not set\n# CONFIG_PACKAGE_libtiff is not set\n# CONFIG_PACKAGE_libtins is not set\nCONFIG_PACKAGE_libtirpc=y\n# CONFIG_PACKAGE_libtorrent-rasterbar is not set\nCONFIG_PACKAGE_libubox=y\n# CONFIG_PACKAGE_libubox-lua is not set\nCONFIG_PACKAGE_libubus=y\nCONFIG_PACKAGE_libubus-lua=y\nCONFIG_PACKAGE_libuci=y\nCONFIG_PACKAGE_libuci-lua=y\n# CONFIG_PACKAGE_libuci2 is not set\nCONFIG_PACKAGE_libuclient=y\nCONFIG_PACKAGE_libudev-zero=y\n# CONFIG_PACKAGE_libudns is not set\n# CONFIG_PACKAGE_libuecc is not set\n# CONFIG_PACKAGE_libugpio is not set\n# CONFIG_PACKAGE_libunistring is not set\n# CONFIG_PACKAGE_libunwind is not set\n# CONFIG_PACKAGE_libupnp is not set\n# CONFIG_PACKAGE_libupnpp is not set\n# CONFIG_PACKAGE_liburcu is not set\nCONFIG_PACKAGE_liburing=y\n# CONFIG_PACKAGE_libusb-1.0 is not set\n# CONFIG_PACKAGE_libusb-compat is not set\n# CONFIG_PACKAGE_libustream-mbedtls is not set\nCONFIG_PACKAGE_libustream-openssl=y\n# CONFIG_PACKAGE_libustream-wolfssl is not set\nCONFIG_PACKAGE_libuuid=y\nCONFIG_PACKAGE_libuv=y\n# CONFIG_PACKAGE_libuwifi is not set\n# CONFIG_PACKAGE_libv4l is not set\nCONFIG_PACKAGE_libvorbis=y\n# CONFIG_PACKAGE_libvorbisidec is not set\n# CONFIG_PACKAGE_libvpx is not set\nCONFIG_PACKAGE_libwebp=y\nCONFIG_PACKAGE_libwebsockets-full=y\n# CONFIG_PACKAGE_libwebsockets-mbedtls is not set\n# CONFIG_PACKAGE_libwebsockets-openssl is not set\n# CONFIG_PACKAGE_libwrap is not set\n# CONFIG_PACKAGE_libxerces-c is not set\n# CONFIG_PACKAGE_libxerces-c-samples is not set\n# CONFIG_PACKAGE_libxml2 is not set\n# CONFIG_PACKAGE_libxslt is not set\n# CONFIG_PACKAGE_libyaml-cpp is not set\n# CONFIG_PACKAGE_libyang is not set\n# CONFIG_PACKAGE_libyubikey is not set\n# CONFIG_PACKAGE_libzmq-curve is not set\n# CONFIG_PACKAGE_libzmq-nc is not set\n# CONFIG_PACKAGE_linux-atm is not set\n# CONFIG_PACKAGE_lmdb is not set\n# CONFIG_PACKAGE_log4cplus is not set\n# CONFIG_PACKAGE_loudmouth is not set\n# CONFIG_PACKAGE_lttng-ust is not set\n# CONFIG_PACKAGE_minizip is not set\n# CONFIG_PACKAGE_msgpack-c is not set\n# CONFIG_PACKAGE_mtdev is not set\nCONFIG_PACKAGE_musl-fts=y\n# CONFIG_PACKAGE_mxml is not set\n# CONFIG_PACKAGE_nspr is not set\n# CONFIG_PACKAGE_oniguruma is not set\n# CONFIG_PACKAGE_open-isns is not set\n# CONFIG_PACKAGE_openblas is not set\n# CONFIG_PACKAGE_openpgm is not set\n# CONFIG_PACKAGE_p11-kit is not set\n# CONFIG_PACKAGE_pixman is not set\n# CONFIG_PACKAGE_poco is not set\n# CONFIG_PACKAGE_poco-all is not set\n# CONFIG_PACKAGE_protobuf is not set\n# CONFIG_PACKAGE_protobuf-lite is not set\n# CONFIG_PACKAGE_pthsem is not set\n# CONFIG_PACKAGE_re2 is not set\nCONFIG_PACKAGE_rpcd-mod-luci=y\n# CONFIG_PACKAGE_rpcd-mod-rad2-enc is not set\nCONFIG_PACKAGE_rpcd-mod-rrdns=y\n# CONFIG_PACKAGE_sbc is not set\n# CONFIG_PACKAGE_scmp_sys_resolver is not set\n# CONFIG_PACKAGE_serdisplib is not set\n# CONFIG_PACKAGE_taglib is not set\nCONFIG_PACKAGE_terminfo=y\n# CONFIG_PACKAGE_tinycdb is not set\n# CONFIG_PACKAGE_uw-imap is not set\n# CONFIG_PACKAGE_xmlrpc-c is not set\n# CONFIG_PACKAGE_xmlrpc-c-client is not set\n# CONFIG_PACKAGE_xmlrpc-c-server is not set\n# CONFIG_PACKAGE_yajl is not set\n# CONFIG_PACKAGE_yubico-pam is not set\nCONFIG_PACKAGE_zlib=y\n\n#\n# Configuration\n#\n# CONFIG_ZLIB_OPTIMIZE_SPEED is not set\n# end of Configuration\n# end of Libraries\n\n#\n# LuCI\n#\n\n#\n# 1. Collections\n#\nCONFIG_PACKAGE_luci=y\nCONFIG_PACKAGE_luci-lib-docker=y\n# CONFIG_PACKAGE_luci-nginx is not set\n# CONFIG_PACKAGE_luci-ssl is not set\n# CONFIG_PACKAGE_luci-ssl-nginx is not set\nCONFIG_PACKAGE_luci-ssl-openssl=y\n# end of 1. Collections\n\n#\n# 2. Modules\n#\nCONFIG_PACKAGE_luci-base=y\n# CONFIG_LUCI_SRCDIET is not set\nCONFIG_LUCI_JSMIN=y\nCONFIG_LUCI_CSSTIDY=y\n\n#\n# Translations\n#\n# CONFIG_LUCI_LANG_ar is not set\n# CONFIG_LUCI_LANG_bg is not set\n# CONFIG_LUCI_LANG_bn_BD is not set\n# CONFIG_LUCI_LANG_ca is not set\n# CONFIG_LUCI_LANG_cs is not set\n# CONFIG_LUCI_LANG_da is not set\n# CONFIG_LUCI_LANG_de is not set\n# CONFIG_LUCI_LANG_el is not set\n# CONFIG_LUCI_LANG_en is not set\n# CONFIG_LUCI_LANG_es is not set\n# CONFIG_LUCI_LANG_fi is not set\n# CONFIG_LUCI_LANG_fr is not set\n# CONFIG_LUCI_LANG_he is not set\n# CONFIG_LUCI_LANG_hi is not set\n# CONFIG_LUCI_LANG_hu is not set\n# CONFIG_LUCI_LANG_it is not set\n# CONFIG_LUCI_LANG_ja is not set\n# CONFIG_LUCI_LANG_ko is not set\n# CONFIG_LUCI_LANG_mr is not set\n# CONFIG_LUCI_LANG_ms is not set\n# CONFIG_LUCI_LANG_nb_NO is not set\n# CONFIG_LUCI_LANG_nl is not set\n# CONFIG_LUCI_LANG_pl is not set\n# CONFIG_LUCI_LANG_pt is not set\n# CONFIG_LUCI_LANG_pt_BR is not set\n# CONFIG_LUCI_LANG_ro is not set\n# CONFIG_LUCI_LANG_ru is not set\n# CONFIG_LUCI_LANG_sk is not set\n# CONFIG_LUCI_LANG_sv is not set\n# CONFIG_LUCI_LANG_tr is not set\n# CONFIG_LUCI_LANG_uk is not set\n# CONFIG_LUCI_LANG_vi is not set\nCONFIG_LUCI_LANG_zh_Hans=y\n# CONFIG_LUCI_LANG_zh_Hant is not set\n# end of Translations\n\nCONFIG_PACKAGE_luci-compat=y\nCONFIG_PACKAGE_luci-mod-admin-full=y\n# CONFIG_PACKAGE_luci-mod-battstatus is not set\n# CONFIG_PACKAGE_luci-mod-dashboard is not set\nCONFIG_PACKAGE_luci-mod-network=y\nCONFIG_PACKAGE_luci-mod-rpc=y\nCONFIG_PACKAGE_luci-mod-status=y\nCONFIG_PACKAGE_luci-mod-system=y\n# end of 2. Modules\n\n#\n# 3. Applications\n#\n# CONFIG_PACKAGE_luci-app-acl is not set\n# CONFIG_PACKAGE_luci-app-acme is not set\nCONFIG_PACKAGE_luci-app-adblock=y\nCONFIG_PACKAGE_luci-app-advanced-reboot=y\n# CONFIG_PACKAGE_luci-app-ahcp is not set\nCONFIG_PACKAGE_luci-app-aria2=y\n# CONFIG_PACKAGE_luci-app-attendedsysupgrade is not set\n# CONFIG_PACKAGE_luci-app-babeld is not set\nCONFIG_PACKAGE_luci-app-banip=y\n# CONFIG_PACKAGE_luci-app-bcp38 is not set\n# CONFIG_PACKAGE_luci-app-bird1-ipv4 is not set\n# CONFIG_PACKAGE_luci-app-bird1-ipv6 is not set\n# CONFIG_PACKAGE_luci-app-bmx6 is not set\n# CONFIG_PACKAGE_luci-app-bmx7 is not set\n# CONFIG_PACKAGE_luci-app-cjdns is not set\n# CONFIG_PACKAGE_luci-app-clamav is not set\nCONFIG_PACKAGE_luci-app-commands=y\n# CONFIG_PACKAGE_luci-app-cshark is not set\n# CONFIG_PACKAGE_luci-app-dawn is not set\n# CONFIG_PACKAGE_luci-app-dcwapd is not set\nCONFIG_PACKAGE_luci-app-ddns=y\n# CONFIG_PACKAGE_luci-app-diag-core is not set\n# CONFIG_PACKAGE_luci-app-dnscrypt-proxy is not set\nCONFIG_PACKAGE_luci-app-dockerman=y\n# CONFIG_PACKAGE_luci-app-dump1090 is not set\n# CONFIG_PACKAGE_luci-app-dynapoint is not set\n# CONFIG_PACKAGE_luci-app-eoip is not set\n# CONFIG_PACKAGE_luci-app-example is not set\nCONFIG_PACKAGE_luci-app-firewall=y\n# CONFIG_PACKAGE_luci-app-frpc is not set\n# CONFIG_PACKAGE_luci-app-frps is not set\n# CONFIG_PACKAGE_luci-app-fwknopd is not set\n# CONFIG_PACKAGE_luci-app-hd-idle is not set\n# CONFIG_PACKAGE_luci-app-hnet is not set\n# CONFIG_PACKAGE_luci-app-https-dns-proxy is not set\n# CONFIG_PACKAGE_luci-app-ksmbd is not set\n# CONFIG_PACKAGE_luci-app-ledtrig-rssi is not set\n# CONFIG_PACKAGE_luci-app-ledtrig-switch is not set\n# CONFIG_PACKAGE_luci-app-ledtrig-usbport is not set\n# CONFIG_PACKAGE_luci-app-lxc is not set\nCONFIG_PACKAGE_luci-app-minidlna=y\nCONFIG_PACKAGE_luci-app-mjpg-streamer=y\n# CONFIG_PACKAGE_luci-app-mwan3 is not set\n# CONFIG_PACKAGE_luci-app-nextdns is not set\n# CONFIG_PACKAGE_luci-app-nft-qos is not set\nCONFIG_PACKAGE_luci-app-nlbwmon=y\nCONFIG_PACKAGE_luci-app-ntpc=y\n# CONFIG_PACKAGE_luci-app-nut is not set\n# CONFIG_PACKAGE_luci-app-ocserv is not set\n# CONFIG_PACKAGE_luci-app-olsr is not set\n# CONFIG_PACKAGE_luci-app-olsr-services is not set\n# CONFIG_PACKAGE_luci-app-olsr-viz is not set\n# CONFIG_PACKAGE_luci-app-omcproxy is not set\nCONFIG_PACKAGE_luci-app-openvpn=y\nCONFIG_PACKAGE_luci-app-opkg=y\n# CONFIG_PACKAGE_luci-app-p910nd is not set\n# CONFIG_PACKAGE_luci-app-pagekitec is not set\n# CONFIG_PACKAGE_luci-app-polipo is not set\n# CONFIG_PACKAGE_luci-app-privoxy is not set\nCONFIG_PACKAGE_luci-app-qos=y\n# CONFIG_PACKAGE_luci-app-radicale is not set\n# CONFIG_PACKAGE_luci-app-radicale2 is not set\n# CONFIG_PACKAGE_luci-app-rp-pppoe-server is not set\nCONFIG_PACKAGE_luci-app-samba4=y\n# CONFIG_PACKAGE_luci-app-ser2net is not set\nCONFIG_PACKAGE_luci-app-shadowsocks-libev=y\n# CONFIG_PACKAGE_luci-app-shairplay is not set\n# CONFIG_PACKAGE_luci-app-siitwizard is not set\n# CONFIG_PACKAGE_luci-app-simple-adblock is not set\n# CONFIG_PACKAGE_luci-app-smartdns is not set\n# CONFIG_PACKAGE_luci-app-snmpd is not set\n# CONFIG_PACKAGE_luci-app-softether is not set\n# CONFIG_PACKAGE_luci-app-splash is not set\nCONFIG_PACKAGE_luci-app-sqm=y\nCONFIG_PACKAGE_luci-app-squid=y\nCONFIG_PACKAGE_luci-app-statistics=y\n# CONFIG_PACKAGE_luci-app-tinyproxy is not set\nCONFIG_PACKAGE_luci-app-transmission=y\n# CONFIG_PACKAGE_luci-app-travelmate is not set\nCONFIG_PACKAGE_luci-app-ttyd=y\n# CONFIG_PACKAGE_luci-app-udpxy is not set\n# CONFIG_PACKAGE_luci-app-uhttpd is not set\nCONFIG_PACKAGE_luci-app-unbound=y\n# CONFIG_PACKAGE_luci-app-upnp is not set\n# CONFIG_PACKAGE_luci-app-vnstat is not set\nCONFIG_PACKAGE_luci-app-vnstat2=y\n# CONFIG_PACKAGE_luci-app-vpn-policy-routing is not set\n# CONFIG_PACKAGE_luci-app-vpnbypass is not set\nCONFIG_PACKAGE_luci-app-watchcat=y\n# CONFIG_PACKAGE_luci-app-wifischedule is not set\nCONFIG_PACKAGE_luci-app-wireguard=y\n# CONFIG_PACKAGE_luci-app-wol is not set\n# CONFIG_PACKAGE_luci-app-xinetd is not set\n# CONFIG_PACKAGE_luci-app-yggdrasil is not set\n# end of 3. Applications\n\n#\n# 4. Themes\n#\nCONFIG_PACKAGE_luci-theme-bootstrap=y\n# CONFIG_PACKAGE_luci-theme-material is not set\n# CONFIG_PACKAGE_luci-theme-openwrt is not set\n# CONFIG_PACKAGE_luci-theme-openwrt-2020 is not set\n# end of 4. Themes\n\n#\n# 5. Protocols\n#\n# CONFIG_PACKAGE_luci-proto-3g is not set\n# CONFIG_PACKAGE_luci-proto-bonding is not set\n# CONFIG_PACKAGE_luci-proto-gre is not set\n# CONFIG_PACKAGE_luci-proto-hnet is not set\n# CONFIG_PACKAGE_luci-proto-ipip is not set\nCONFIG_PACKAGE_luci-proto-ipv6=y\n# CONFIG_PACKAGE_luci-proto-modemmanager is not set\n# CONFIG_PACKAGE_luci-proto-ncm is not set\n# CONFIG_PACKAGE_luci-proto-openconnect is not set\n# CONFIG_PACKAGE_luci-proto-openfortivpn is not set\nCONFIG_PACKAGE_luci-proto-ppp=y\n# CONFIG_PACKAGE_luci-proto-pppossh is not set\n# CONFIG_PACKAGE_luci-proto-qmi is not set\n# CONFIG_PACKAGE_luci-proto-relay is not set\n# CONFIG_PACKAGE_luci-proto-sstp is not set\n# CONFIG_PACKAGE_luci-proto-vpnc is not set\n# CONFIG_PACKAGE_luci-proto-vxlan is not set\nCONFIG_PACKAGE_luci-proto-wireguard=y\n# end of 5. Protocols\n\n#\n# 6. Libraries\n#\nCONFIG_PACKAGE_luci-lib-base=y\n# CONFIG_PACKAGE_luci-lib-dracula is not set\n# CONFIG_PACKAGE_luci-lib-httpclient is not set\n# CONFIG_PACKAGE_luci-lib-httpprotoutils is not set\nCONFIG_PACKAGE_luci-lib-ip=y\nCONFIG_PACKAGE_luci-lib-ipkg=y\n# CONFIG_PACKAGE_luci-lib-iptparser is not set\n# CONFIG_PACKAGE_luci-lib-jquery-1-4 is not set\nCONFIG_PACKAGE_luci-lib-json=y\nCONFIG_PACKAGE_luci-lib-jsonc=y\nCONFIG_PACKAGE_luci-lib-nixio=y\nCONFIG_PACKAGE_luci-lib-nixio_notls=y\n# CONFIG_PACKAGE_luci-lib-nixio_axtls is not set\n# CONFIG_PACKAGE_luci-lib-nixio_cyassl is not set\n# CONFIG_PACKAGE_luci-lib-nixio_openssl is not set\n# CONFIG_PACKAGE_luci-lib-px5g is not set\n# end of 6. Libraries\n\n# CONFIG_PACKAGE_luci-i18n-adblock-ar is not set\n# CONFIG_PACKAGE_luci-i18n-adblock-bg is not set\n# CONFIG_PACKAGE_luci-i18n-adblock-bn is not set\n# CONFIG_PACKAGE_luci-i18n-adblock-ca is not set\n# CONFIG_PACKAGE_luci-i18n-adblock-cs is not set\n# CONFIG_PACKAGE_luci-i18n-adblock-da is not set\n# CONFIG_PACKAGE_luci-i18n-adblock-de is not set\n# CONFIG_PACKAGE_luci-i18n-adblock-el is not set\n# CONFIG_PACKAGE_luci-i18n-adblock-en is not set\n# CONFIG_PACKAGE_luci-i18n-adblock-es is not set\n# CONFIG_PACKAGE_luci-i18n-adblock-fi is not set\n# CONFIG_PACKAGE_luci-i18n-adblock-fr is not set\n# CONFIG_PACKAGE_luci-i18n-adblock-he is not set\n# CONFIG_PACKAGE_luci-i18n-adblock-hi is not set\n# CONFIG_PACKAGE_luci-i18n-adblock-hu is not set\n# CONFIG_PACKAGE_luci-i18n-adblock-it is not set\n# CONFIG_PACKAGE_luci-i18n-adblock-ja is not set\n# CONFIG_PACKAGE_luci-i18n-adblock-ko is not set\n# CONFIG_PACKAGE_luci-i18n-adblock-mr is not set\n# CONFIG_PACKAGE_luci-i18n-adblock-ms is not set\n# CONFIG_PACKAGE_luci-i18n-adblock-no is not set\n# CONFIG_PACKAGE_luci-i18n-adblock-pl is not set\n# CONFIG_PACKAGE_luci-i18n-adblock-pt is not set\n# CONFIG_PACKAGE_luci-i18n-adblock-pt-br is not set\n# CONFIG_PACKAGE_luci-i18n-adblock-ro is not set\n# CONFIG_PACKAGE_luci-i18n-adblock-ru is not set\n# CONFIG_PACKAGE_luci-i18n-adblock-si is not set\n# CONFIG_PACKAGE_luci-i18n-adblock-sk is not set\n# CONFIG_PACKAGE_luci-i18n-adblock-sv is not set\n# CONFIG_PACKAGE_luci-i18n-adblock-tr is not set\n# CONFIG_PACKAGE_luci-i18n-adblock-uk is not set\n# CONFIG_PACKAGE_luci-i18n-adblock-vi is not set\nCONFIG_PACKAGE_luci-i18n-adblock-zh-cn=y\n# CONFIG_PACKAGE_luci-i18n-adblock-zh-tw is not set\n# CONFIG_PACKAGE_luci-i18n-advanced-reboot-ar is not set\n# CONFIG_PACKAGE_luci-i18n-advanced-reboot-bg is not set\n# CONFIG_PACKAGE_luci-i18n-advanced-reboot-bn is not set\n# CONFIG_PACKAGE_luci-i18n-advanced-reboot-ca is not set\n# CONFIG_PACKAGE_luci-i18n-advanced-reboot-cs is not set\n# CONFIG_PACKAGE_luci-i18n-advanced-reboot-da is not set\n# CONFIG_PACKAGE_luci-i18n-advanced-reboot-de is not set\n# CONFIG_PACKAGE_luci-i18n-advanced-reboot-el is not set\n# CONFIG_PACKAGE_luci-i18n-advanced-reboot-en is not set\n# CONFIG_PACKAGE_luci-i18n-advanced-reboot-es is not set\n# CONFIG_PACKAGE_luci-i18n-advanced-reboot-fi is not set\n# CONFIG_PACKAGE_luci-i18n-advanced-reboot-fr is not set\n# CONFIG_PACKAGE_luci-i18n-advanced-reboot-he is not set\n# CONFIG_PACKAGE_luci-i18n-advanced-reboot-hi is not set\n# CONFIG_PACKAGE_luci-i18n-advanced-reboot-hu is not set\n# CONFIG_PACKAGE_luci-i18n-advanced-reboot-it is not set\n# CONFIG_PACKAGE_luci-i18n-advanced-reboot-ja is not set\n# CONFIG_PACKAGE_luci-i18n-advanced-reboot-ko is not set\n# CONFIG_PACKAGE_luci-i18n-advanced-reboot-mr is not set\n# CONFIG_PACKAGE_luci-i18n-advanced-reboot-ms is not set\n# CONFIG_PACKAGE_luci-i18n-advanced-reboot-no is not set\n# CONFIG_PACKAGE_luci-i18n-advanced-reboot-pl is not set\n# CONFIG_PACKAGE_luci-i18n-advanced-reboot-pt is not set\n# CONFIG_PACKAGE_luci-i18n-advanced-reboot-pt-br is not set\n# CONFIG_PACKAGE_luci-i18n-advanced-reboot-ro is not set\n# CONFIG_PACKAGE_luci-i18n-advanced-reboot-ru is not set\n# CONFIG_PACKAGE_luci-i18n-advanced-reboot-si is not set\n# CONFIG_PACKAGE_luci-i18n-advanced-reboot-sk is not set\n# CONFIG_PACKAGE_luci-i18n-advanced-reboot-sv is not set\n# CONFIG_PACKAGE_luci-i18n-advanced-reboot-tr is not set\n# CONFIG_PACKAGE_luci-i18n-advanced-reboot-uk is not set\n# CONFIG_PACKAGE_luci-i18n-advanced-reboot-vi is not set\nCONFIG_PACKAGE_luci-i18n-advanced-reboot-zh-cn=y\n# CONFIG_PACKAGE_luci-i18n-advanced-reboot-zh-tw is not set\n# CONFIG_PACKAGE_luci-i18n-aria2-ar is not set\n# CONFIG_PACKAGE_luci-i18n-aria2-bg is not set\n# CONFIG_PACKAGE_luci-i18n-aria2-bn is not set\n# CONFIG_PACKAGE_luci-i18n-aria2-ca is not set\n# CONFIG_PACKAGE_luci-i18n-aria2-cs is not set\n# CONFIG_PACKAGE_luci-i18n-aria2-da is not set\n# CONFIG_PACKAGE_luci-i18n-aria2-de is not set\n# CONFIG_PACKAGE_luci-i18n-aria2-el is not set\n# CONFIG_PACKAGE_luci-i18n-aria2-en is not set\n# CONFIG_PACKAGE_luci-i18n-aria2-es is not set\n# CONFIG_PACKAGE_luci-i18n-aria2-fi is not set\n# CONFIG_PACKAGE_luci-i18n-aria2-fr is not set\n# CONFIG_PACKAGE_luci-i18n-aria2-he is not set\n# CONFIG_PACKAGE_luci-i18n-aria2-hi is not set\n# CONFIG_PACKAGE_luci-i18n-aria2-hu is not set\n# CONFIG_PACKAGE_luci-i18n-aria2-it is not set\n# CONFIG_PACKAGE_luci-i18n-aria2-ja is not set\n# CONFIG_PACKAGE_luci-i18n-aria2-ko is not set\n# CONFIG_PACKAGE_luci-i18n-aria2-mr is not set\n# CONFIG_PACKAGE_luci-i18n-aria2-ms is not set\n# CONFIG_PACKAGE_luci-i18n-aria2-no is not set\n# CONFIG_PACKAGE_luci-i18n-aria2-pl is not set\n# CONFIG_PACKAGE_luci-i18n-aria2-pt is not set\n# CONFIG_PACKAGE_luci-i18n-aria2-pt-br is not set\n# CONFIG_PACKAGE_luci-i18n-aria2-ro is not set\n# CONFIG_PACKAGE_luci-i18n-aria2-ru is not set\n# CONFIG_PACKAGE_luci-i18n-aria2-sk is not set\n# CONFIG_PACKAGE_luci-i18n-aria2-sv is not set\n# CONFIG_PACKAGE_luci-i18n-aria2-tr is not set\n# CONFIG_PACKAGE_luci-i18n-aria2-uk is not set\n# CONFIG_PACKAGE_luci-i18n-aria2-vi is not set\nCONFIG_PACKAGE_luci-i18n-aria2-zh-cn=y\n# CONFIG_PACKAGE_luci-i18n-aria2-zh-tw is not set\n# CONFIG_PACKAGE_luci-i18n-banip-ar is not set\n# CONFIG_PACKAGE_luci-i18n-banip-bg is not set\n# CONFIG_PACKAGE_luci-i18n-banip-bn is not set\n# CONFIG_PACKAGE_luci-i18n-banip-ca is not set\n# CONFIG_PACKAGE_luci-i18n-banip-cs is not set\n# CONFIG_PACKAGE_luci-i18n-banip-da is not set\n# CONFIG_PACKAGE_luci-i18n-banip-de is not set\n# CONFIG_PACKAGE_luci-i18n-banip-el is not set\n# CONFIG_PACKAGE_luci-i18n-banip-en is not set\n# CONFIG_PACKAGE_luci-i18n-banip-es is not set\n# CONFIG_PACKAGE_luci-i18n-banip-fi is not set\n# CONFIG_PACKAGE_luci-i18n-banip-fr is not set\n# CONFIG_PACKAGE_luci-i18n-banip-he is not set\n# CONFIG_PACKAGE_luci-i18n-banip-hi is not set\n# CONFIG_PACKAGE_luci-i18n-banip-hu is not set\n# CONFIG_PACKAGE_luci-i18n-banip-it is not set\n# CONFIG_PACKAGE_luci-i18n-banip-ja is not set\n# CONFIG_PACKAGE_luci-i18n-banip-ko is not set\n# CONFIG_PACKAGE_luci-i18n-banip-mr is not set\n# CONFIG_PACKAGE_luci-i18n-banip-ms is not set\n# CONFIG_PACKAGE_luci-i18n-banip-nl is not set\n# CONFIG_PACKAGE_luci-i18n-banip-no is not set\n# CONFIG_PACKAGE_luci-i18n-banip-pl is not set\n# CONFIG_PACKAGE_luci-i18n-banip-pt is not set\n# CONFIG_PACKAGE_luci-i18n-banip-pt-br is not set\n# CONFIG_PACKAGE_luci-i18n-banip-ro is not set\n# CONFIG_PACKAGE_luci-i18n-banip-ru is not set\n# CONFIG_PACKAGE_luci-i18n-banip-sk is not set\n# CONFIG_PACKAGE_luci-i18n-banip-sv is not set\n# CONFIG_PACKAGE_luci-i18n-banip-sw is not set\n# CONFIG_PACKAGE_luci-i18n-banip-tr is not set\n# CONFIG_PACKAGE_luci-i18n-banip-uk is not set\n# CONFIG_PACKAGE_luci-i18n-banip-vi is not set\nCONFIG_PACKAGE_luci-i18n-banip-zh-cn=y\n# CONFIG_PACKAGE_luci-i18n-banip-zh-tw is not set\n# CONFIG_PACKAGE_luci-i18n-base-ar is not set\n# CONFIG_PACKAGE_luci-i18n-base-bg is not set\n# CONFIG_PACKAGE_luci-i18n-base-bn is not set\n# CONFIG_PACKAGE_luci-i18n-base-ca is not set\n# CONFIG_PACKAGE_luci-i18n-base-cs is not set\n# CONFIG_PACKAGE_luci-i18n-base-da is not set\n# CONFIG_PACKAGE_luci-i18n-base-de is not set\n# CONFIG_PACKAGE_luci-i18n-base-el is not set\n# CONFIG_PACKAGE_luci-i18n-base-en is not set\n# CONFIG_PACKAGE_luci-i18n-base-es is not set\n# CONFIG_PACKAGE_luci-i18n-base-fi is not set\n# CONFIG_PACKAGE_luci-i18n-base-fr is not set\n# CONFIG_PACKAGE_luci-i18n-base-he is not set\n# CONFIG_PACKAGE_luci-i18n-base-hi is not set\n# CONFIG_PACKAGE_luci-i18n-base-hu is not set\n# CONFIG_PACKAGE_luci-i18n-base-it is not set\n# CONFIG_PACKAGE_luci-i18n-base-ja is not set\n# CONFIG_PACKAGE_luci-i18n-base-ko is not set\n# CONFIG_PACKAGE_luci-i18n-base-mr is not set\n# CONFIG_PACKAGE_luci-i18n-base-ms is not set\n# CONFIG_PACKAGE_luci-i18n-base-nl is not set\n# CONFIG_PACKAGE_luci-i18n-base-no is not set\n# CONFIG_PACKAGE_luci-i18n-base-pl is not set\n# CONFIG_PACKAGE_luci-i18n-base-pt is not set\n# CONFIG_PACKAGE_luci-i18n-base-pt-br is not set\n# CONFIG_PACKAGE_luci-i18n-base-ro is not set\n# CONFIG_PACKAGE_luci-i18n-base-ru is not set\n# CONFIG_PACKAGE_luci-i18n-base-sk is not set\n# CONFIG_PACKAGE_luci-i18n-base-sv is not set\n# CONFIG_PACKAGE_luci-i18n-base-tr is not set\n# CONFIG_PACKAGE_luci-i18n-base-uk is not set\n# CONFIG_PACKAGE_luci-i18n-base-vi is not set\nCONFIG_PACKAGE_luci-i18n-base-zh-cn=y\n# CONFIG_PACKAGE_luci-i18n-base-zh-tw is not set\n# CONFIG_PACKAGE_luci-i18n-commands-ar is not set\n# CONFIG_PACKAGE_luci-i18n-commands-bg is not set\n# CONFIG_PACKAGE_luci-i18n-commands-bn is not set\n# CONFIG_PACKAGE_luci-i18n-commands-ca is not set\n# CONFIG_PACKAGE_luci-i18n-commands-cs is not set\n# CONFIG_PACKAGE_luci-i18n-commands-da is not set\n# CONFIG_PACKAGE_luci-i18n-commands-de is not set\n# CONFIG_PACKAGE_luci-i18n-commands-el is not set\n# CONFIG_PACKAGE_luci-i18n-commands-en is not set\n# CONFIG_PACKAGE_luci-i18n-commands-es is not set\n# CONFIG_PACKAGE_luci-i18n-commands-fi is not set\n# CONFIG_PACKAGE_luci-i18n-commands-fr is not set\n# CONFIG_PACKAGE_luci-i18n-commands-he is not set\n# CONFIG_PACKAGE_luci-i18n-commands-hi is not set\n# CONFIG_PACKAGE_luci-i18n-commands-hu is not set\n# CONFIG_PACKAGE_luci-i18n-commands-it is not set\n# CONFIG_PACKAGE_luci-i18n-commands-ja is not set\n# CONFIG_PACKAGE_luci-i18n-commands-ko is not set\n# CONFIG_PACKAGE_luci-i18n-commands-mr is not set\n# CONFIG_PACKAGE_luci-i18n-commands-ms is not set\n# CONFIG_PACKAGE_luci-i18n-commands-no is not set\n# CONFIG_PACKAGE_luci-i18n-commands-pl is not set\n# CONFIG_PACKAGE_luci-i18n-commands-pt is not set\n# CONFIG_PACKAGE_luci-i18n-commands-pt-br is not set\n# CONFIG_PACKAGE_luci-i18n-commands-ro is not set\n# CONFIG_PACKAGE_luci-i18n-commands-ru is not set\n# CONFIG_PACKAGE_luci-i18n-commands-sk is not set\n# CONFIG_PACKAGE_luci-i18n-commands-sv is not set\n# CONFIG_PACKAGE_luci-i18n-commands-tr is not set\n# CONFIG_PACKAGE_luci-i18n-commands-uk is not set\n# CONFIG_PACKAGE_luci-i18n-commands-vi is not set\nCONFIG_PACKAGE_luci-i18n-commands-zh-cn=y\n# CONFIG_PACKAGE_luci-i18n-commands-zh-tw is not set\n# CONFIG_PACKAGE_luci-i18n-ddns-ar is not set\n# CONFIG_PACKAGE_luci-i18n-ddns-bg is not set\n# CONFIG_PACKAGE_luci-i18n-ddns-bn is not set\n# CONFIG_PACKAGE_luci-i18n-ddns-ca is not set\n# CONFIG_PACKAGE_luci-i18n-ddns-cs is not set\n# CONFIG_PACKAGE_luci-i18n-ddns-da is not set\n# CONFIG_PACKAGE_luci-i18n-ddns-de is not set\n# CONFIG_PACKAGE_luci-i18n-ddns-el is not set\n# CONFIG_PACKAGE_luci-i18n-ddns-en is not set\n# CONFIG_PACKAGE_luci-i18n-ddns-es is not set\n# CONFIG_PACKAGE_luci-i18n-ddns-fi is not set\n# CONFIG_PACKAGE_luci-i18n-ddns-fr is not set\n# CONFIG_PACKAGE_luci-i18n-ddns-he is not set\n# CONFIG_PACKAGE_luci-i18n-ddns-hi is not set\n# CONFIG_PACKAGE_luci-i18n-ddns-hu is not set\n# CONFIG_PACKAGE_luci-i18n-ddns-it is not set\n# CONFIG_PACKAGE_luci-i18n-ddns-ja is not set\n# CONFIG_PACKAGE_luci-i18n-ddns-ko is not set\n# CONFIG_PACKAGE_luci-i18n-ddns-mr is not set\n# CONFIG_PACKAGE_luci-i18n-ddns-ms is not set\n# CONFIG_PACKAGE_luci-i18n-ddns-no is not set\n# CONFIG_PACKAGE_luci-i18n-ddns-pl is not set\n# CONFIG_PACKAGE_luci-i18n-ddns-pt is not set\n# CONFIG_PACKAGE_luci-i18n-ddns-pt-br is not set\n# CONFIG_PACKAGE_luci-i18n-ddns-ro is not set\n# CONFIG_PACKAGE_luci-i18n-ddns-ru is not set\n# CONFIG_PACKAGE_luci-i18n-ddns-sk is not set\n# CONFIG_PACKAGE_luci-i18n-ddns-sv is not set\n# CONFIG_PACKAGE_luci-i18n-ddns-tr is not set\n# CONFIG_PACKAGE_luci-i18n-ddns-uk is not set\n# CONFIG_PACKAGE_luci-i18n-ddns-vi is not set\nCONFIG_PACKAGE_luci-i18n-ddns-zh-cn=y\n# CONFIG_PACKAGE_luci-i18n-ddns-zh-tw is not set\n# CONFIG_PACKAGE_luci-i18n-dockerman-ar is not set\n# CONFIG_PACKAGE_luci-i18n-dockerman-bg is not set\n# CONFIG_PACKAGE_luci-i18n-dockerman-bn is not set\n# CONFIG_PACKAGE_luci-i18n-dockerman-ca is not set\n# CONFIG_PACKAGE_luci-i18n-dockerman-cs is not set\n# CONFIG_PACKAGE_luci-i18n-dockerman-da is not set\n# CONFIG_PACKAGE_luci-i18n-dockerman-de is not set\n# CONFIG_PACKAGE_luci-i18n-dockerman-el is not set\n# CONFIG_PACKAGE_luci-i18n-dockerman-en is not set\n# CONFIG_PACKAGE_luci-i18n-dockerman-es is not set\n# CONFIG_PACKAGE_luci-i18n-dockerman-fa is not set\n# CONFIG_PACKAGE_luci-i18n-dockerman-fi is not set\n# CONFIG_PACKAGE_luci-i18n-dockerman-fr is not set\n# CONFIG_PACKAGE_luci-i18n-dockerman-he is not set\n# CONFIG_PACKAGE_luci-i18n-dockerman-hi is not set\n# CONFIG_PACKAGE_luci-i18n-dockerman-hu is not set\n# CONFIG_PACKAGE_luci-i18n-dockerman-id is not set\n# CONFIG_PACKAGE_luci-i18n-dockerman-it is not set\n# CONFIG_PACKAGE_luci-i18n-dockerman-ja is not set\n# CONFIG_PACKAGE_luci-i18n-dockerman-ko is not set\n# CONFIG_PACKAGE_luci-i18n-dockerman-lt is not set\n# CONFIG_PACKAGE_luci-i18n-dockerman-mr is not set\n# CONFIG_PACKAGE_luci-i18n-dockerman-ms is not set\n# CONFIG_PACKAGE_luci-i18n-dockerman-no is not set\n# CONFIG_PACKAGE_luci-i18n-dockerman-pl is not set\n# CONFIG_PACKAGE_luci-i18n-dockerman-pt is not set\n# CONFIG_PACKAGE_luci-i18n-dockerman-pt-br is not set\n# CONFIG_PACKAGE_luci-i18n-dockerman-ro is not set\n# CONFIG_PACKAGE_luci-i18n-dockerman-ru is not set\n# CONFIG_PACKAGE_luci-i18n-dockerman-sk is not set\n# CONFIG_PACKAGE_luci-i18n-dockerman-sv is not set\n# CONFIG_PACKAGE_luci-i18n-dockerman-tr is not set\n# CONFIG_PACKAGE_luci-i18n-dockerman-uk is not set\n# CONFIG_PACKAGE_luci-i18n-dockerman-vi is not set\nCONFIG_PACKAGE_luci-i18n-dockerman-zh-cn=y\n# CONFIG_PACKAGE_luci-i18n-dockerman-zh-tw is not set\n# CONFIG_PACKAGE_luci-i18n-firewall-ar is not set\n# CONFIG_PACKAGE_luci-i18n-firewall-bg is not set\n# CONFIG_PACKAGE_luci-i18n-firewall-bn is not set\n# CONFIG_PACKAGE_luci-i18n-firewall-ca is not set\n# CONFIG_PACKAGE_luci-i18n-firewall-cs is not set\n# CONFIG_PACKAGE_luci-i18n-firewall-da is not set\n# CONFIG_PACKAGE_luci-i18n-firewall-de is not set\n# CONFIG_PACKAGE_luci-i18n-firewall-el is not set\n# CONFIG_PACKAGE_luci-i18n-firewall-en is not set\n# CONFIG_PACKAGE_luci-i18n-firewall-es is not set\n# CONFIG_PACKAGE_luci-i18n-firewall-fa is not set\n# CONFIG_PACKAGE_luci-i18n-firewall-fi is not set\n# CONFIG_PACKAGE_luci-i18n-firewall-fr is not set\n# CONFIG_PACKAGE_luci-i18n-firewall-he is not set\n# CONFIG_PACKAGE_luci-i18n-firewall-hi is not set\n# CONFIG_PACKAGE_luci-i18n-firewall-hu is not set\n# CONFIG_PACKAGE_luci-i18n-firewall-id is not set\n# CONFIG_PACKAGE_luci-i18n-firewall-it is not set\n# CONFIG_PACKAGE_luci-i18n-firewall-ja is not set\n# CONFIG_PACKAGE_luci-i18n-firewall-ko is not set\n# CONFIG_PACKAGE_luci-i18n-firewall-mr is not set\n# CONFIG_PACKAGE_luci-i18n-firewall-ms is not set\n# CONFIG_PACKAGE_luci-i18n-firewall-nl is not set\n# CONFIG_PACKAGE_luci-i18n-firewall-no is not set\n# CONFIG_PACKAGE_luci-i18n-firewall-pl is not set\n# CONFIG_PACKAGE_luci-i18n-firewall-pt is not set\n# CONFIG_PACKAGE_luci-i18n-firewall-pt-br is not set\n# CONFIG_PACKAGE_luci-i18n-firewall-ro is not set\n# CONFIG_PACKAGE_luci-i18n-firewall-ru is not set\n# CONFIG_PACKAGE_luci-i18n-firewall-si is not set\n# CONFIG_PACKAGE_luci-i18n-firewall-sk is not set\n# CONFIG_PACKAGE_luci-i18n-firewall-sv is not set\n# CONFIG_PACKAGE_luci-i18n-firewall-tr is not set\n# CONFIG_PACKAGE_luci-i18n-firewall-uk is not set\n# CONFIG_PACKAGE_luci-i18n-firewall-vi is not set\nCONFIG_PACKAGE_luci-i18n-firewall-zh-cn=y\n# CONFIG_PACKAGE_luci-i18n-firewall-zh-tw is not set\n# CONFIG_PACKAGE_luci-i18n-minidlna-ar is not set\n# CONFIG_PACKAGE_luci-i18n-minidlna-bg is not set\n# CONFIG_PACKAGE_luci-i18n-minidlna-bn is not set\n# CONFIG_PACKAGE_luci-i18n-minidlna-ca is not set\n# CONFIG_PACKAGE_luci-i18n-minidlna-cs is not set\n# CONFIG_PACKAGE_luci-i18n-minidlna-da is not set\n# CONFIG_PACKAGE_luci-i18n-minidlna-de is not set\n# CONFIG_PACKAGE_luci-i18n-minidlna-el is not set\n# CONFIG_PACKAGE_luci-i18n-minidlna-en is not set\n# CONFIG_PACKAGE_luci-i18n-minidlna-es is not set\n# CONFIG_PACKAGE_luci-i18n-minidlna-fi is not set\n# CONFIG_PACKAGE_luci-i18n-minidlna-fr is not set\n# CONFIG_PACKAGE_luci-i18n-minidlna-he is not set\n# CONFIG_PACKAGE_luci-i18n-minidlna-hi is not set\n# CONFIG_PACKAGE_luci-i18n-minidlna-hu is not set\n# CONFIG_PACKAGE_luci-i18n-minidlna-it is not set\n# CONFIG_PACKAGE_luci-i18n-minidlna-ja is not set\n# CONFIG_PACKAGE_luci-i18n-minidlna-ko is not set\n# CONFIG_PACKAGE_luci-i18n-minidlna-mr is not set\n# CONFIG_PACKAGE_luci-i18n-minidlna-ms is not set\n# CONFIG_PACKAGE_luci-i18n-minidlna-no is not set\n# CONFIG_PACKAGE_luci-i18n-minidlna-pl is not set\n# CONFIG_PACKAGE_luci-i18n-minidlna-pt is not set\n# CONFIG_PACKAGE_luci-i18n-minidlna-pt-br is not set\n# CONFIG_PACKAGE_luci-i18n-minidlna-ro is not set\n# CONFIG_PACKAGE_luci-i18n-minidlna-ru is not set\n# CONFIG_PACKAGE_luci-i18n-minidlna-sk is not set\n# CONFIG_PACKAGE_luci-i18n-minidlna-sv is not set\n# CONFIG_PACKAGE_luci-i18n-minidlna-tr is not set\n# CONFIG_PACKAGE_luci-i18n-minidlna-uk is not set\n# CONFIG_PACKAGE_luci-i18n-minidlna-vi is not set\nCONFIG_PACKAGE_luci-i18n-minidlna-zh-cn=y\n# CONFIG_PACKAGE_luci-i18n-minidlna-zh-tw is not set\n# CONFIG_PACKAGE_luci-i18n-mjpg-streamer-ar is not set\n# CONFIG_PACKAGE_luci-i18n-mjpg-streamer-bg is not set\n# CONFIG_PACKAGE_luci-i18n-mjpg-streamer-bn is not set\n# CONFIG_PACKAGE_luci-i18n-mjpg-streamer-ca is not set\n# CONFIG_PACKAGE_luci-i18n-mjpg-streamer-cs is not set\n# CONFIG_PACKAGE_luci-i18n-mjpg-streamer-da is not set\n# CONFIG_PACKAGE_luci-i18n-mjpg-streamer-de is not set\n# CONFIG_PACKAGE_luci-i18n-mjpg-streamer-el is not set\n# CONFIG_PACKAGE_luci-i18n-mjpg-streamer-en is not set\n# CONFIG_PACKAGE_luci-i18n-mjpg-streamer-es is not set\n# CONFIG_PACKAGE_luci-i18n-mjpg-streamer-fi is not set\n# CONFIG_PACKAGE_luci-i18n-mjpg-streamer-fr is not set\n# CONFIG_PACKAGE_luci-i18n-mjpg-streamer-he is not set\n# CONFIG_PACKAGE_luci-i18n-mjpg-streamer-hi is not set\n# CONFIG_PACKAGE_luci-i18n-mjpg-streamer-hu is not set\n# CONFIG_PACKAGE_luci-i18n-mjpg-streamer-it is not set\n# CONFIG_PACKAGE_luci-i18n-mjpg-streamer-ja is not set\n# CONFIG_PACKAGE_luci-i18n-mjpg-streamer-ko is not set\n# CONFIG_PACKAGE_luci-i18n-mjpg-streamer-mr is not set\n# CONFIG_PACKAGE_luci-i18n-mjpg-streamer-ms is not set\n# CONFIG_PACKAGE_luci-i18n-mjpg-streamer-no is not set\n# CONFIG_PACKAGE_luci-i18n-mjpg-streamer-pl is not set\n# CONFIG_PACKAGE_luci-i18n-mjpg-streamer-pt is not set\n# CONFIG_PACKAGE_luci-i18n-mjpg-streamer-pt-br is not set\n# CONFIG_PACKAGE_luci-i18n-mjpg-streamer-ro is not set\n# CONFIG_PACKAGE_luci-i18n-mjpg-streamer-ru is not set\n# CONFIG_PACKAGE_luci-i18n-mjpg-streamer-sk is not set\n# CONFIG_PACKAGE_luci-i18n-mjpg-streamer-sv is not set\n# CONFIG_PACKAGE_luci-i18n-mjpg-streamer-tr is not set\n# CONFIG_PACKAGE_luci-i18n-mjpg-streamer-uk is not set\n# CONFIG_PACKAGE_luci-i18n-mjpg-streamer-vi is not set\nCONFIG_PACKAGE_luci-i18n-mjpg-streamer-zh-cn=y\n# CONFIG_PACKAGE_luci-i18n-mjpg-streamer-zh-tw is not set\n# CONFIG_PACKAGE_luci-i18n-nlbwmon-ar is not set\n# CONFIG_PACKAGE_luci-i18n-nlbwmon-bg is not set\n# CONFIG_PACKAGE_luci-i18n-nlbwmon-bn is not set\n# CONFIG_PACKAGE_luci-i18n-nlbwmon-ca is not set\n# CONFIG_PACKAGE_luci-i18n-nlbwmon-cs is not set\n# CONFIG_PACKAGE_luci-i18n-nlbwmon-da is not set\n# CONFIG_PACKAGE_luci-i18n-nlbwmon-de is not set\n# CONFIG_PACKAGE_luci-i18n-nlbwmon-el is not set\n# CONFIG_PACKAGE_luci-i18n-nlbwmon-en is not set\n# CONFIG_PACKAGE_luci-i18n-nlbwmon-es is not set\n# CONFIG_PACKAGE_luci-i18n-nlbwmon-fi is not set\n# CONFIG_PACKAGE_luci-i18n-nlbwmon-fr is not set\n# CONFIG_PACKAGE_luci-i18n-nlbwmon-he is not set\n# CONFIG_PACKAGE_luci-i18n-nlbwmon-hi is not set\n# CONFIG_PACKAGE_luci-i18n-nlbwmon-hu is not set\n# CONFIG_PACKAGE_luci-i18n-nlbwmon-it is not set\n# CONFIG_PACKAGE_luci-i18n-nlbwmon-ja is not set\n# CONFIG_PACKAGE_luci-i18n-nlbwmon-ko is not set\n# CONFIG_PACKAGE_luci-i18n-nlbwmon-mr is not set\n# CONFIG_PACKAGE_luci-i18n-nlbwmon-ms is not set\n# CONFIG_PACKAGE_luci-i18n-nlbwmon-no is not set\n# CONFIG_PACKAGE_luci-i18n-nlbwmon-pl is not set\n# CONFIG_PACKAGE_luci-i18n-nlbwmon-pt is not set\n# CONFIG_PACKAGE_luci-i18n-nlbwmon-pt-br is not set\n# CONFIG_PACKAGE_luci-i18n-nlbwmon-ro is not set\n# CONFIG_PACKAGE_luci-i18n-nlbwmon-ru is not set\n# CONFIG_PACKAGE_luci-i18n-nlbwmon-sk is not set\n# CONFIG_PACKAGE_luci-i18n-nlbwmon-sv is not set\n# CONFIG_PACKAGE_luci-i18n-nlbwmon-tr is not set\n# CONFIG_PACKAGE_luci-i18n-nlbwmon-uk is not set\n# CONFIG_PACKAGE_luci-i18n-nlbwmon-vi is not set\nCONFIG_PACKAGE_luci-i18n-nlbwmon-zh-cn=y\n# CONFIG_PACKAGE_luci-i18n-nlbwmon-zh-tw is not set\n# CONFIG_PACKAGE_luci-i18n-ntpc-ar is not set\n# CONFIG_PACKAGE_luci-i18n-ntpc-bg is not set\n# CONFIG_PACKAGE_luci-i18n-ntpc-bn is not set\n# CONFIG_PACKAGE_luci-i18n-ntpc-bs is not set\n# CONFIG_PACKAGE_luci-i18n-ntpc-ca is not set\n# CONFIG_PACKAGE_luci-i18n-ntpc-cs is not set\n# CONFIG_PACKAGE_luci-i18n-ntpc-da is not set\n# CONFIG_PACKAGE_luci-i18n-ntpc-de is not set\n# CONFIG_PACKAGE_luci-i18n-ntpc-el is not set\n# CONFIG_PACKAGE_luci-i18n-ntpc-en is not set\n# CONFIG_PACKAGE_luci-i18n-ntpc-es is not set\n# CONFIG_PACKAGE_luci-i18n-ntpc-fi is not set\n# CONFIG_PACKAGE_luci-i18n-ntpc-fr is not set\n# CONFIG_PACKAGE_luci-i18n-ntpc-he is not set\n# CONFIG_PACKAGE_luci-i18n-ntpc-hi is not set\n# CONFIG_PACKAGE_luci-i18n-ntpc-hu is not set\n# CONFIG_PACKAGE_luci-i18n-ntpc-it is not set\n# CONFIG_PACKAGE_luci-i18n-ntpc-ja is not set\n# CONFIG_PACKAGE_luci-i18n-ntpc-ko is not set\n# CONFIG_PACKAGE_luci-i18n-ntpc-mr is not set\n# CONFIG_PACKAGE_luci-i18n-ntpc-ms is not set\n# CONFIG_PACKAGE_luci-i18n-ntpc-no is not set\n# CONFIG_PACKAGE_luci-i18n-ntpc-pl is not set\n# CONFIG_PACKAGE_luci-i18n-ntpc-pt is not set\n# CONFIG_PACKAGE_luci-i18n-ntpc-pt-br is not set\n# CONFIG_PACKAGE_luci-i18n-ntpc-ro is not set\n# CONFIG_PACKAGE_luci-i18n-ntpc-ru is not set\n# CONFIG_PACKAGE_luci-i18n-ntpc-sk is not set\n# CONFIG_PACKAGE_luci-i18n-ntpc-sv is not set\n# CONFIG_PACKAGE_luci-i18n-ntpc-tr is not set\n# CONFIG_PACKAGE_luci-i18n-ntpc-uk is not set\n# CONFIG_PACKAGE_luci-i18n-ntpc-vi is not set\nCONFIG_PACKAGE_luci-i18n-ntpc-zh-cn=y\n# CONFIG_PACKAGE_luci-i18n-ntpc-zh-tw is not set\n# CONFIG_PACKAGE_luci-i18n-openvpn-ar is not set\n# CONFIG_PACKAGE_luci-i18n-openvpn-bg is not set\n# CONFIG_PACKAGE_luci-i18n-openvpn-bn is not set\n# CONFIG_PACKAGE_luci-i18n-openvpn-ca is not set\n# CONFIG_PACKAGE_luci-i18n-openvpn-cs is not set\n# CONFIG_PACKAGE_luci-i18n-openvpn-da is not set\n# CONFIG_PACKAGE_luci-i18n-openvpn-de is not set\n# CONFIG_PACKAGE_luci-i18n-openvpn-el is not set\n# CONFIG_PACKAGE_luci-i18n-openvpn-en is not set\n# CONFIG_PACKAGE_luci-i18n-openvpn-es is not set\n# CONFIG_PACKAGE_luci-i18n-openvpn-fa is not set\n# CONFIG_PACKAGE_luci-i18n-openvpn-fi is not set\n# CONFIG_PACKAGE_luci-i18n-openvpn-fr is not set\n# CONFIG_PACKAGE_luci-i18n-openvpn-he is not set\n# CONFIG_PACKAGE_luci-i18n-openvpn-hi is not set\n# CONFIG_PACKAGE_luci-i18n-openvpn-hu is not set\n# CONFIG_PACKAGE_luci-i18n-openvpn-it is not set\n# CONFIG_PACKAGE_luci-i18n-openvpn-ja is not set\n# CONFIG_PACKAGE_luci-i18n-openvpn-ko is not set\n# CONFIG_PACKAGE_luci-i18n-openvpn-mr is not set\n# CONFIG_PACKAGE_luci-i18n-openvpn-ms is not set\n# CONFIG_PACKAGE_luci-i18n-openvpn-no is not set\n# CONFIG_PACKAGE_luci-i18n-openvpn-pl is not set\n# CONFIG_PACKAGE_luci-i18n-openvpn-pt is not set\n# CONFIG_PACKAGE_luci-i18n-openvpn-pt-br is not set\n# CONFIG_PACKAGE_luci-i18n-openvpn-ro is not set\n# CONFIG_PACKAGE_luci-i18n-openvpn-ru is not set\n# CONFIG_PACKAGE_luci-i18n-openvpn-sk is not set\n# CONFIG_PACKAGE_luci-i18n-openvpn-sv is not set\n# CONFIG_PACKAGE_luci-i18n-openvpn-tr is not set\n# CONFIG_PACKAGE_luci-i18n-openvpn-uk is not set\n# CONFIG_PACKAGE_luci-i18n-openvpn-vi is not set\nCONFIG_PACKAGE_luci-i18n-openvpn-zh-cn=y\n# CONFIG_PACKAGE_luci-i18n-openvpn-zh-tw is not set\n# CONFIG_PACKAGE_luci-i18n-opkg-ar is not set\n# CONFIG_PACKAGE_luci-i18n-opkg-bg is not set\n# CONFIG_PACKAGE_luci-i18n-opkg-bn is not set\n# CONFIG_PACKAGE_luci-i18n-opkg-ca is not set\n# CONFIG_PACKAGE_luci-i18n-opkg-cs is not set\n# CONFIG_PACKAGE_luci-i18n-opkg-da is not set\n# CONFIG_PACKAGE_luci-i18n-opkg-de is not set\n# CONFIG_PACKAGE_luci-i18n-opkg-el is not set\n# CONFIG_PACKAGE_luci-i18n-opkg-en is not set\n# CONFIG_PACKAGE_luci-i18n-opkg-es is not set\n# CONFIG_PACKAGE_luci-i18n-opkg-fi is not set\n# CONFIG_PACKAGE_luci-i18n-opkg-fr is not set\n# CONFIG_PACKAGE_luci-i18n-opkg-he is not set\n# CONFIG_PACKAGE_luci-i18n-opkg-hi is not set\n# CONFIG_PACKAGE_luci-i18n-opkg-hu is not set\n# CONFIG_PACKAGE_luci-i18n-opkg-it is not set\n# CONFIG_PACKAGE_luci-i18n-opkg-ja is not set\n# CONFIG_PACKAGE_luci-i18n-opkg-ko is not set\n# CONFIG_PACKAGE_luci-i18n-opkg-mr is not set\n# CONFIG_PACKAGE_luci-i18n-opkg-ms is not set\n# CONFIG_PACKAGE_luci-i18n-opkg-no is not set\n# CONFIG_PACKAGE_luci-i18n-opkg-pl is not set\n# CONFIG_PACKAGE_luci-i18n-opkg-pt is not set\n# CONFIG_PACKAGE_luci-i18n-opkg-pt-br is not set\n# CONFIG_PACKAGE_luci-i18n-opkg-ro is not set\n# CONFIG_PACKAGE_luci-i18n-opkg-ru is not set\n# CONFIG_PACKAGE_luci-i18n-opkg-sk is not set\n# CONFIG_PACKAGE_luci-i18n-opkg-sv is not set\n# CONFIG_PACKAGE_luci-i18n-opkg-tr is not set\n# CONFIG_PACKAGE_luci-i18n-opkg-uk is not set\n# CONFIG_PACKAGE_luci-i18n-opkg-vi is not set\nCONFIG_PACKAGE_luci-i18n-opkg-zh-cn=y\n# CONFIG_PACKAGE_luci-i18n-opkg-zh-tw is not set\n# CONFIG_PACKAGE_luci-i18n-qos-ar is not set\n# CONFIG_PACKAGE_luci-i18n-qos-bg is not set\n# CONFIG_PACKAGE_luci-i18n-qos-bn is not set\n# CONFIG_PACKAGE_luci-i18n-qos-ca is not set\n# CONFIG_PACKAGE_luci-i18n-qos-cs is not set\n# CONFIG_PACKAGE_luci-i18n-qos-da is not set\n# CONFIG_PACKAGE_luci-i18n-qos-de is not set\n# CONFIG_PACKAGE_luci-i18n-qos-el is not set\n# CONFIG_PACKAGE_luci-i18n-qos-en is not set\n# CONFIG_PACKAGE_luci-i18n-qos-es is not set\n# CONFIG_PACKAGE_luci-i18n-qos-fi is not set\n# CONFIG_PACKAGE_luci-i18n-qos-fr is not set\n# CONFIG_PACKAGE_luci-i18n-qos-he is not set\n# CONFIG_PACKAGE_luci-i18n-qos-hi is not set\n# CONFIG_PACKAGE_luci-i18n-qos-hu is not set\n# CONFIG_PACKAGE_luci-i18n-qos-it is not set\n# CONFIG_PACKAGE_luci-i18n-qos-ja is not set\n# CONFIG_PACKAGE_luci-i18n-qos-ko is not set\n# CONFIG_PACKAGE_luci-i18n-qos-mr is not set\n# CONFIG_PACKAGE_luci-i18n-qos-ms is not set\n# CONFIG_PACKAGE_luci-i18n-qos-no is not set\n# CONFIG_PACKAGE_luci-i18n-qos-pl is not set\n# CONFIG_PACKAGE_luci-i18n-qos-pt is not set\n# CONFIG_PACKAGE_luci-i18n-qos-pt-br is not set\n# CONFIG_PACKAGE_luci-i18n-qos-ro is not set\n# CONFIG_PACKAGE_luci-i18n-qos-ru is not set\n# CONFIG_PACKAGE_luci-i18n-qos-sk is not set\n# CONFIG_PACKAGE_luci-i18n-qos-sv is not set\n# CONFIG_PACKAGE_luci-i18n-qos-tr is not set\n# CONFIG_PACKAGE_luci-i18n-qos-uk is not set\n# CONFIG_PACKAGE_luci-i18n-qos-vi is not set\nCONFIG_PACKAGE_luci-i18n-qos-zh-cn=y\n# CONFIG_PACKAGE_luci-i18n-qos-zh-tw is not set\n# CONFIG_PACKAGE_luci-i18n-samba4-ar is not set\n# CONFIG_PACKAGE_luci-i18n-samba4-bg is not set\n# CONFIG_PACKAGE_luci-i18n-samba4-bn is not set\n# CONFIG_PACKAGE_luci-i18n-samba4-ca is not set\n# CONFIG_PACKAGE_luci-i18n-samba4-cs is not set\n# CONFIG_PACKAGE_luci-i18n-samba4-da is not set\n# CONFIG_PACKAGE_luci-i18n-samba4-de is not set\n# CONFIG_PACKAGE_luci-i18n-samba4-el is not set\n# CONFIG_PACKAGE_luci-i18n-samba4-en is not set\n# CONFIG_PACKAGE_luci-i18n-samba4-es is not set\n# CONFIG_PACKAGE_luci-i18n-samba4-fi is not set\n# CONFIG_PACKAGE_luci-i18n-samba4-fr is not set\n# CONFIG_PACKAGE_luci-i18n-samba4-he is not set\n# CONFIG_PACKAGE_luci-i18n-samba4-hi is not set\n# CONFIG_PACKAGE_luci-i18n-samba4-hu is not set\n# CONFIG_PACKAGE_luci-i18n-samba4-it is not set\n# CONFIG_PACKAGE_luci-i18n-samba4-ja is not set\n# CONFIG_PACKAGE_luci-i18n-samba4-ko is not set\n# CONFIG_PACKAGE_luci-i18n-samba4-mr is not set\n# CONFIG_PACKAGE_luci-i18n-samba4-ms is not set\n# CONFIG_PACKAGE_luci-i18n-samba4-nl is not set\n# CONFIG_PACKAGE_luci-i18n-samba4-no is not set\n# CONFIG_PACKAGE_luci-i18n-samba4-pl is not set\n# CONFIG_PACKAGE_luci-i18n-samba4-pt is not set\n# CONFIG_PACKAGE_luci-i18n-samba4-pt-br is not set\n# CONFIG_PACKAGE_luci-i18n-samba4-ro is not set\n# CONFIG_PACKAGE_luci-i18n-samba4-ru is not set\n# CONFIG_PACKAGE_luci-i18n-samba4-sk is not set\n# CONFIG_PACKAGE_luci-i18n-samba4-sv is not set\n# CONFIG_PACKAGE_luci-i18n-samba4-tr is not set\n# CONFIG_PACKAGE_luci-i18n-samba4-uk is not set\n# CONFIG_PACKAGE_luci-i18n-samba4-vi is not set\nCONFIG_PACKAGE_luci-i18n-samba4-zh-cn=y\n# CONFIG_PACKAGE_luci-i18n-samba4-zh-tw is not set\n# CONFIG_PACKAGE_luci-i18n-shadowsocks-libev-ar is not set\n# CONFIG_PACKAGE_luci-i18n-shadowsocks-libev-bg is not set\n# CONFIG_PACKAGE_luci-i18n-shadowsocks-libev-bn is not set\n# CONFIG_PACKAGE_luci-i18n-shadowsocks-libev-ca is not set\n# CONFIG_PACKAGE_luci-i18n-shadowsocks-libev-cs is not set\n# CONFIG_PACKAGE_luci-i18n-shadowsocks-libev-da is not set\n# CONFIG_PACKAGE_luci-i18n-shadowsocks-libev-de is not set\n# CONFIG_PACKAGE_luci-i18n-shadowsocks-libev-el is not set\n# CONFIG_PACKAGE_luci-i18n-shadowsocks-libev-en is not set\n# CONFIG_PACKAGE_luci-i18n-shadowsocks-libev-es is not set\n# CONFIG_PACKAGE_luci-i18n-shadowsocks-libev-fi is not set\n# CONFIG_PACKAGE_luci-i18n-shadowsocks-libev-fr is not set\n# CONFIG_PACKAGE_luci-i18n-shadowsocks-libev-he is not set\n# CONFIG_PACKAGE_luci-i18n-shadowsocks-libev-hi is not set\n# CONFIG_PACKAGE_luci-i18n-shadowsocks-libev-hu is not set\n# CONFIG_PACKAGE_luci-i18n-shadowsocks-libev-it is not set\n# CONFIG_PACKAGE_luci-i18n-shadowsocks-libev-ja is not set\n# CONFIG_PACKAGE_luci-i18n-shadowsocks-libev-ko is not set\n# CONFIG_PACKAGE_luci-i18n-shadowsocks-libev-mr is not set\n# CONFIG_PACKAGE_luci-i18n-shadowsocks-libev-ms is not set\n# CONFIG_PACKAGE_luci-i18n-shadowsocks-libev-no is not set\n# CONFIG_PACKAGE_luci-i18n-shadowsocks-libev-pl is not set\n# CONFIG_PACKAGE_luci-i18n-shadowsocks-libev-pt is not set\n# CONFIG_PACKAGE_luci-i18n-shadowsocks-libev-pt-br is not set\n# CONFIG_PACKAGE_luci-i18n-shadowsocks-libev-ro is not set\n# CONFIG_PACKAGE_luci-i18n-shadowsocks-libev-ru is not set\n# CONFIG_PACKAGE_luci-i18n-shadowsocks-libev-sk is not set\n# CONFIG_PACKAGE_luci-i18n-shadowsocks-libev-sv is not set\n# CONFIG_PACKAGE_luci-i18n-shadowsocks-libev-tr is not set\n# CONFIG_PACKAGE_luci-i18n-shadowsocks-libev-uk is not set\n# CONFIG_PACKAGE_luci-i18n-shadowsocks-libev-vi is not set\nCONFIG_PACKAGE_luci-i18n-shadowsocks-libev-zh-cn=y\n# CONFIG_PACKAGE_luci-i18n-shadowsocks-libev-zh-tw is not set\n# CONFIG_PACKAGE_luci-i18n-sqm-ar is not set\n# CONFIG_PACKAGE_luci-i18n-sqm-bg is not set\n# CONFIG_PACKAGE_luci-i18n-sqm-bn is not set\n# CONFIG_PACKAGE_luci-i18n-sqm-ca is not set\n# CONFIG_PACKAGE_luci-i18n-sqm-cs is not set\n# CONFIG_PACKAGE_luci-i18n-sqm-da is not set\n# CONFIG_PACKAGE_luci-i18n-sqm-de is not set\n# CONFIG_PACKAGE_luci-i18n-sqm-el is not set\n# CONFIG_PACKAGE_luci-i18n-sqm-en is not set\n# CONFIG_PACKAGE_luci-i18n-sqm-es is not set\n# CONFIG_PACKAGE_luci-i18n-sqm-fi is not set\n# CONFIG_PACKAGE_luci-i18n-sqm-fr is not set\n# CONFIG_PACKAGE_luci-i18n-sqm-he is not set\n# CONFIG_PACKAGE_luci-i18n-sqm-hi is not set\n# CONFIG_PACKAGE_luci-i18n-sqm-hu is not set\n# CONFIG_PACKAGE_luci-i18n-sqm-it is not set\n# CONFIG_PACKAGE_luci-i18n-sqm-ja is not set\n# CONFIG_PACKAGE_luci-i18n-sqm-ko is not set\n# CONFIG_PACKAGE_luci-i18n-sqm-mr is not set\n# CONFIG_PACKAGE_luci-i18n-sqm-ms is not set\n# CONFIG_PACKAGE_luci-i18n-sqm-no is not set\n# CONFIG_PACKAGE_luci-i18n-sqm-pl is not set\n# CONFIG_PACKAGE_luci-i18n-sqm-pt is not set\n# CONFIG_PACKAGE_luci-i18n-sqm-pt-br is not set\n# CONFIG_PACKAGE_luci-i18n-sqm-ro is not set\n# CONFIG_PACKAGE_luci-i18n-sqm-ru is not set\n# CONFIG_PACKAGE_luci-i18n-sqm-sk is not set\n# CONFIG_PACKAGE_luci-i18n-sqm-sv is not set\n# CONFIG_PACKAGE_luci-i18n-sqm-tr is not set\n# CONFIG_PACKAGE_luci-i18n-sqm-uk is not set\n# CONFIG_PACKAGE_luci-i18n-sqm-vi is not set\nCONFIG_PACKAGE_luci-i18n-sqm-zh-cn=y\n# CONFIG_PACKAGE_luci-i18n-sqm-zh-tw is not set\n# CONFIG_PACKAGE_luci-i18n-squid-ar is not set\n# CONFIG_PACKAGE_luci-i18n-squid-bg is not set\n# CONFIG_PACKAGE_luci-i18n-squid-bn is not set\n# CONFIG_PACKAGE_luci-i18n-squid-ca is not set\n# CONFIG_PACKAGE_luci-i18n-squid-cs is not set\n# CONFIG_PACKAGE_luci-i18n-squid-da is not set\n# CONFIG_PACKAGE_luci-i18n-squid-de is not set\n# CONFIG_PACKAGE_luci-i18n-squid-el is not set\n# CONFIG_PACKAGE_luci-i18n-squid-en is not set\n# CONFIG_PACKAGE_luci-i18n-squid-es is not set\n# CONFIG_PACKAGE_luci-i18n-squid-fi is not set\n# CONFIG_PACKAGE_luci-i18n-squid-fr is not set\n# CONFIG_PACKAGE_luci-i18n-squid-he is not set\n# CONFIG_PACKAGE_luci-i18n-squid-hi is not set\n# CONFIG_PACKAGE_luci-i18n-squid-hu is not set\n# CONFIG_PACKAGE_luci-i18n-squid-it is not set\n# CONFIG_PACKAGE_luci-i18n-squid-ja is not set\n# CONFIG_PACKAGE_luci-i18n-squid-ko is not set\n# CONFIG_PACKAGE_luci-i18n-squid-mr is not set\n# CONFIG_PACKAGE_luci-i18n-squid-ms is not set\n# CONFIG_PACKAGE_luci-i18n-squid-no is not set\n# CONFIG_PACKAGE_luci-i18n-squid-pl is not set\n# CONFIG_PACKAGE_luci-i18n-squid-pt is not set\n# CONFIG_PACKAGE_luci-i18n-squid-pt-br is not set\n# CONFIG_PACKAGE_luci-i18n-squid-ro is not set\n# CONFIG_PACKAGE_luci-i18n-squid-ru is not set\n# CONFIG_PACKAGE_luci-i18n-squid-sk is not set\n# CONFIG_PACKAGE_luci-i18n-squid-sv is not set\n# CONFIG_PACKAGE_luci-i18n-squid-tr is not set\n# CONFIG_PACKAGE_luci-i18n-squid-uk is not set\n# CONFIG_PACKAGE_luci-i18n-squid-vi is not set\nCONFIG_PACKAGE_luci-i18n-squid-zh-cn=y\n# CONFIG_PACKAGE_luci-i18n-squid-zh-tw is not set\n# CONFIG_PACKAGE_luci-i18n-statistics-ar is not set\n# CONFIG_PACKAGE_luci-i18n-statistics-bg is not set\n# CONFIG_PACKAGE_luci-i18n-statistics-bn is not set\n# CONFIG_PACKAGE_luci-i18n-statistics-bs is not set\n# CONFIG_PACKAGE_luci-i18n-statistics-ca is not set\n# CONFIG_PACKAGE_luci-i18n-statistics-cs is not set\n# CONFIG_PACKAGE_luci-i18n-statistics-da is not set\n# CONFIG_PACKAGE_luci-i18n-statistics-de is not set\n# CONFIG_PACKAGE_luci-i18n-statistics-el is not set\n# CONFIG_PACKAGE_luci-i18n-statistics-en is not set\n# CONFIG_PACKAGE_luci-i18n-statistics-es is not set\n# CONFIG_PACKAGE_luci-i18n-statistics-fi is not set\n# CONFIG_PACKAGE_luci-i18n-statistics-fr is not set\n# CONFIG_PACKAGE_luci-i18n-statistics-he is not set\n# CONFIG_PACKAGE_luci-i18n-statistics-hi is not set\n# CONFIG_PACKAGE_luci-i18n-statistics-hu is not set\n# CONFIG_PACKAGE_luci-i18n-statistics-it is not set\n# CONFIG_PACKAGE_luci-i18n-statistics-ja is not set\n# CONFIG_PACKAGE_luci-i18n-statistics-ko is not set\n# CONFIG_PACKAGE_luci-i18n-statistics-mr is not set\n# CONFIG_PACKAGE_luci-i18n-statistics-ms is not set\n# CONFIG_PACKAGE_luci-i18n-statistics-nl is not set\n# CONFIG_PACKAGE_luci-i18n-statistics-no is not set\n# CONFIG_PACKAGE_luci-i18n-statistics-pl is not set\n# CONFIG_PACKAGE_luci-i18n-statistics-pt is not set\n# CONFIG_PACKAGE_luci-i18n-statistics-pt-br is not set\n# CONFIG_PACKAGE_luci-i18n-statistics-ro is not set\n# CONFIG_PACKAGE_luci-i18n-statistics-ru is not set\n# CONFIG_PACKAGE_luci-i18n-statistics-sk is not set\n# CONFIG_PACKAGE_luci-i18n-statistics-sv is not set\n# CONFIG_PACKAGE_luci-i18n-statistics-tr is not set\n# CONFIG_PACKAGE_luci-i18n-statistics-uk is not set\n# CONFIG_PACKAGE_luci-i18n-statistics-vi is not set\nCONFIG_PACKAGE_luci-i18n-statistics-zh-cn=y\n# CONFIG_PACKAGE_luci-i18n-statistics-zh-tw is not set\n# CONFIG_PACKAGE_luci-i18n-transmission-ar is not set\n# CONFIG_PACKAGE_luci-i18n-transmission-bg is not set\n# CONFIG_PACKAGE_luci-i18n-transmission-bn is not set\n# CONFIG_PACKAGE_luci-i18n-transmission-ca is not set\n# CONFIG_PACKAGE_luci-i18n-transmission-cs is not set\n# CONFIG_PACKAGE_luci-i18n-transmission-da is not set\n# CONFIG_PACKAGE_luci-i18n-transmission-de is not set\n# CONFIG_PACKAGE_luci-i18n-transmission-el is not set\n# CONFIG_PACKAGE_luci-i18n-transmission-en is not set\n# CONFIG_PACKAGE_luci-i18n-transmission-es is not set\n# CONFIG_PACKAGE_luci-i18n-transmission-fi is not set\n# CONFIG_PACKAGE_luci-i18n-transmission-fr is not set\n# CONFIG_PACKAGE_luci-i18n-transmission-he is not set\n# CONFIG_PACKAGE_luci-i18n-transmission-hi is not set\n# CONFIG_PACKAGE_luci-i18n-transmission-hu is not set\n# CONFIG_PACKAGE_luci-i18n-transmission-it is not set\n# CONFIG_PACKAGE_luci-i18n-transmission-ja is not set\n# CONFIG_PACKAGE_luci-i18n-transmission-ko is not set\n# CONFIG_PACKAGE_luci-i18n-transmission-mr is not set\n# CONFIG_PACKAGE_luci-i18n-transmission-ms is not set\n# CONFIG_PACKAGE_luci-i18n-transmission-no is not set\n# CONFIG_PACKAGE_luci-i18n-transmission-pl is not set\n# CONFIG_PACKAGE_luci-i18n-transmission-pt is not set\n# CONFIG_PACKAGE_luci-i18n-transmission-pt-br is not set\n# CONFIG_PACKAGE_luci-i18n-transmission-ro is not set\n# CONFIG_PACKAGE_luci-i18n-transmission-ru is not set\n# CONFIG_PACKAGE_luci-i18n-transmission-sk is not set\n# CONFIG_PACKAGE_luci-i18n-transmission-sv is not set\n# CONFIG_PACKAGE_luci-i18n-transmission-tr is not set\n# CONFIG_PACKAGE_luci-i18n-transmission-uk is not set\n# CONFIG_PACKAGE_luci-i18n-transmission-vi is not set\nCONFIG_PACKAGE_luci-i18n-transmission-zh-cn=y\n# CONFIG_PACKAGE_luci-i18n-transmission-zh-tw is not set\n# CONFIG_PACKAGE_luci-i18n-ttyd-ar is not set\n# CONFIG_PACKAGE_luci-i18n-ttyd-bg is not set\n# CONFIG_PACKAGE_luci-i18n-ttyd-bn is not set\n# CONFIG_PACKAGE_luci-i18n-ttyd-ca is not set\n# CONFIG_PACKAGE_luci-i18n-ttyd-cs is not set\n# CONFIG_PACKAGE_luci-i18n-ttyd-da is not set\n# CONFIG_PACKAGE_luci-i18n-ttyd-de is not set\n# CONFIG_PACKAGE_luci-i18n-ttyd-el is not set\n# CONFIG_PACKAGE_luci-i18n-ttyd-en is not set\n# CONFIG_PACKAGE_luci-i18n-ttyd-es is not set\n# CONFIG_PACKAGE_luci-i18n-ttyd-fi is not set\n# CONFIG_PACKAGE_luci-i18n-ttyd-fr is not set\n# CONFIG_PACKAGE_luci-i18n-ttyd-he is not set\n# CONFIG_PACKAGE_luci-i18n-ttyd-hi is not set\n# CONFIG_PACKAGE_luci-i18n-ttyd-hu is not set\n# CONFIG_PACKAGE_luci-i18n-ttyd-it is not set\n# CONFIG_PACKAGE_luci-i18n-ttyd-ja is not set\n# CONFIG_PACKAGE_luci-i18n-ttyd-ko is not set\n# CONFIG_PACKAGE_luci-i18n-ttyd-mr is not set\n# CONFIG_PACKAGE_luci-i18n-ttyd-ms is not set\n# CONFIG_PACKAGE_luci-i18n-ttyd-no is not set\n# CONFIG_PACKAGE_luci-i18n-ttyd-pl is not set\n# CONFIG_PACKAGE_luci-i18n-ttyd-pt is not set\n# CONFIG_PACKAGE_luci-i18n-ttyd-pt-br is not set\n# CONFIG_PACKAGE_luci-i18n-ttyd-ro is not set\n# CONFIG_PACKAGE_luci-i18n-ttyd-ru is not set\n# CONFIG_PACKAGE_luci-i18n-ttyd-sk is not set\n# CONFIG_PACKAGE_luci-i18n-ttyd-sv is not set\n# CONFIG_PACKAGE_luci-i18n-ttyd-tr is not set\n# CONFIG_PACKAGE_luci-i18n-ttyd-uk is not set\n# CONFIG_PACKAGE_luci-i18n-ttyd-vi is not set\nCONFIG_PACKAGE_luci-i18n-ttyd-zh-cn=y\n# CONFIG_PACKAGE_luci-i18n-ttyd-zh-tw is not set\n# CONFIG_PACKAGE_luci-i18n-unbound-ar is not set\n# CONFIG_PACKAGE_luci-i18n-unbound-bg is not set\n# CONFIG_PACKAGE_luci-i18n-unbound-bn is not set\n# CONFIG_PACKAGE_luci-i18n-unbound-ca is not set\n# CONFIG_PACKAGE_luci-i18n-unbound-cs is not set\n# CONFIG_PACKAGE_luci-i18n-unbound-da is not set\n# CONFIG_PACKAGE_luci-i18n-unbound-de is not set\n# CONFIG_PACKAGE_luci-i18n-unbound-el is not set\n# CONFIG_PACKAGE_luci-i18n-unbound-en is not set\n# CONFIG_PACKAGE_luci-i18n-unbound-es is not set\n# CONFIG_PACKAGE_luci-i18n-unbound-fi is not set\n# CONFIG_PACKAGE_luci-i18n-unbound-fr is not set\n# CONFIG_PACKAGE_luci-i18n-unbound-he is not set\n# CONFIG_PACKAGE_luci-i18n-unbound-hi is not set\n# CONFIG_PACKAGE_luci-i18n-unbound-hu is not set\n# CONFIG_PACKAGE_luci-i18n-unbound-it is not set\n# CONFIG_PACKAGE_luci-i18n-unbound-ja is not set\n# CONFIG_PACKAGE_luci-i18n-unbound-ko is not set\n# CONFIG_PACKAGE_luci-i18n-unbound-mr is not set\n# CONFIG_PACKAGE_luci-i18n-unbound-ms is not set\n# CONFIG_PACKAGE_luci-i18n-unbound-no is not set\n# CONFIG_PACKAGE_luci-i18n-unbound-pl is not set\n# CONFIG_PACKAGE_luci-i18n-unbound-pt is not set\n# CONFIG_PACKAGE_luci-i18n-unbound-pt-br is not set\n# CONFIG_PACKAGE_luci-i18n-unbound-ro is not set\n# CONFIG_PACKAGE_luci-i18n-unbound-ru is not set\n# CONFIG_PACKAGE_luci-i18n-unbound-sk is not set\n# CONFIG_PACKAGE_luci-i18n-unbound-sv is not set\n# CONFIG_PACKAGE_luci-i18n-unbound-tr is not set\n# CONFIG_PACKAGE_luci-i18n-unbound-uk is not set\n# CONFIG_PACKAGE_luci-i18n-unbound-vi is not set\nCONFIG_PACKAGE_luci-i18n-unbound-zh-cn=y\n# CONFIG_PACKAGE_luci-i18n-unbound-zh-tw is not set\n# CONFIG_PACKAGE_luci-i18n-vnstat2-ar is not set\n# CONFIG_PACKAGE_luci-i18n-vnstat2-bg is not set\n# CONFIG_PACKAGE_luci-i18n-vnstat2-bn is not set\n# CONFIG_PACKAGE_luci-i18n-vnstat2-ca is not set\n# CONFIG_PACKAGE_luci-i18n-vnstat2-cs is not set\n# CONFIG_PACKAGE_luci-i18n-vnstat2-da is not set\n# CONFIG_PACKAGE_luci-i18n-vnstat2-de is not set\n# CONFIG_PACKAGE_luci-i18n-vnstat2-el is not set\n# CONFIG_PACKAGE_luci-i18n-vnstat2-en is not set\n# CONFIG_PACKAGE_luci-i18n-vnstat2-es is not set\n# CONFIG_PACKAGE_luci-i18n-vnstat2-fi is not set\n# CONFIG_PACKAGE_luci-i18n-vnstat2-fr is not set\n# CONFIG_PACKAGE_luci-i18n-vnstat2-he is not set\n# CONFIG_PACKAGE_luci-i18n-vnstat2-hi is not set\n# CONFIG_PACKAGE_luci-i18n-vnstat2-hu is not set\n# CONFIG_PACKAGE_luci-i18n-vnstat2-it is not set\n# CONFIG_PACKAGE_luci-i18n-vnstat2-ja is not set\n# CONFIG_PACKAGE_luci-i18n-vnstat2-ko is not set\n# CONFIG_PACKAGE_luci-i18n-vnstat2-mr is not set\n# CONFIG_PACKAGE_luci-i18n-vnstat2-ms is not set\n# CONFIG_PACKAGE_luci-i18n-vnstat2-no is not set\n# CONFIG_PACKAGE_luci-i18n-vnstat2-pl is not set\n# CONFIG_PACKAGE_luci-i18n-vnstat2-pt is not set\n# CONFIG_PACKAGE_luci-i18n-vnstat2-pt-br is not set\n# CONFIG_PACKAGE_luci-i18n-vnstat2-ro is not set\n# CONFIG_PACKAGE_luci-i18n-vnstat2-ru is not set\n# CONFIG_PACKAGE_luci-i18n-vnstat2-sk is not set\n# CONFIG_PACKAGE_luci-i18n-vnstat2-sv is not set\n# CONFIG_PACKAGE_luci-i18n-vnstat2-tr is not set\n# CONFIG_PACKAGE_luci-i18n-vnstat2-uk is not set\n# CONFIG_PACKAGE_luci-i18n-vnstat2-vi is not set\nCONFIG_PACKAGE_luci-i18n-vnstat2-zh-cn=y\n# CONFIG_PACKAGE_luci-i18n-vnstat2-zh-tw is not set\n# CONFIG_PACKAGE_luci-i18n-watchcat-ar is not set\n# CONFIG_PACKAGE_luci-i18n-watchcat-bg is not set\n# CONFIG_PACKAGE_luci-i18n-watchcat-bn is not set\n# CONFIG_PACKAGE_luci-i18n-watchcat-ca is not set\n# CONFIG_PACKAGE_luci-i18n-watchcat-cs is not set\n# CONFIG_PACKAGE_luci-i18n-watchcat-da is not set\n# CONFIG_PACKAGE_luci-i18n-watchcat-de is not set\n# CONFIG_PACKAGE_luci-i18n-watchcat-el is not set\n# CONFIG_PACKAGE_luci-i18n-watchcat-en is not set\n# CONFIG_PACKAGE_luci-i18n-watchcat-es is not set\n# CONFIG_PACKAGE_luci-i18n-watchcat-fi is not set\n# CONFIG_PACKAGE_luci-i18n-watchcat-fr is not set\n# CONFIG_PACKAGE_luci-i18n-watchcat-he is not set\n# CONFIG_PACKAGE_luci-i18n-watchcat-hi is not set\n# CONFIG_PACKAGE_luci-i18n-watchcat-hu is not set\n# CONFIG_PACKAGE_luci-i18n-watchcat-it is not set\n# CONFIG_PACKAGE_luci-i18n-watchcat-ja is not set\n# CONFIG_PACKAGE_luci-i18n-watchcat-ko is not set\n# CONFIG_PACKAGE_luci-i18n-watchcat-mr is not set\n# CONFIG_PACKAGE_luci-i18n-watchcat-ms is not set\n# CONFIG_PACKAGE_luci-i18n-watchcat-no is not set\n# CONFIG_PACKAGE_luci-i18n-watchcat-pl is not set\n# CONFIG_PACKAGE_luci-i18n-watchcat-pt is not set\n# CONFIG_PACKAGE_luci-i18n-watchcat-pt-br is not set\n# CONFIG_PACKAGE_luci-i18n-watchcat-ro is not set\n# CONFIG_PACKAGE_luci-i18n-watchcat-ru is not set\n# CONFIG_PACKAGE_luci-i18n-watchcat-sk is not set\n# CONFIG_PACKAGE_luci-i18n-watchcat-sv is not set\n# CONFIG_PACKAGE_luci-i18n-watchcat-tr is not set\n# CONFIG_PACKAGE_luci-i18n-watchcat-uk is not set\n# CONFIG_PACKAGE_luci-i18n-watchcat-vi is not set\nCONFIG_PACKAGE_luci-i18n-watchcat-zh-cn=y\n# CONFIG_PACKAGE_luci-i18n-watchcat-zh-tw is not set\n# CONFIG_PACKAGE_luci-i18n-wireguard-ar is not set\n# CONFIG_PACKAGE_luci-i18n-wireguard-bg is not set\n# CONFIG_PACKAGE_luci-i18n-wireguard-bn is not set\n# CONFIG_PACKAGE_luci-i18n-wireguard-ca is not set\n# CONFIG_PACKAGE_luci-i18n-wireguard-cs is not set\n# CONFIG_PACKAGE_luci-i18n-wireguard-da is not set\n# CONFIG_PACKAGE_luci-i18n-wireguard-de is not set\n# CONFIG_PACKAGE_luci-i18n-wireguard-el is not set\n# CONFIG_PACKAGE_luci-i18n-wireguard-en is not set\n# CONFIG_PACKAGE_luci-i18n-wireguard-es is not set\n# CONFIG_PACKAGE_luci-i18n-wireguard-fi is not set\n# CONFIG_PACKAGE_luci-i18n-wireguard-fr is not set\n# CONFIG_PACKAGE_luci-i18n-wireguard-he is not set\n# CONFIG_PACKAGE_luci-i18n-wireguard-hi is not set\n# CONFIG_PACKAGE_luci-i18n-wireguard-hu is not set\n# CONFIG_PACKAGE_luci-i18n-wireguard-id is not set\n# CONFIG_PACKAGE_luci-i18n-wireguard-it is not set\n# CONFIG_PACKAGE_luci-i18n-wireguard-ja is not set\n# CONFIG_PACKAGE_luci-i18n-wireguard-ko is not set\n# CONFIG_PACKAGE_luci-i18n-wireguard-mr is not set\n# CONFIG_PACKAGE_luci-i18n-wireguard-ms is not set\n# CONFIG_PACKAGE_luci-i18n-wireguard-no is not set\n# CONFIG_PACKAGE_luci-i18n-wireguard-pl is not set\n# CONFIG_PACKAGE_luci-i18n-wireguard-pt is not set\n# CONFIG_PACKAGE_luci-i18n-wireguard-pt-br is not set\n# CONFIG_PACKAGE_luci-i18n-wireguard-ro is not set\n# CONFIG_PACKAGE_luci-i18n-wireguard-ru is not set\n# CONFIG_PACKAGE_luci-i18n-wireguard-sk is not set\n# CONFIG_PACKAGE_luci-i18n-wireguard-sv is not set\n# CONFIG_PACKAGE_luci-i18n-wireguard-tr is not set\n# CONFIG_PACKAGE_luci-i18n-wireguard-uk is not set\n# CONFIG_PACKAGE_luci-i18n-wireguard-vi is not set\nCONFIG_PACKAGE_luci-i18n-wireguard-zh-cn=y\n# CONFIG_PACKAGE_luci-i18n-wireguard-zh-tw is not set\n# end of LuCI\n\n#\n# Mail\n#\n# CONFIG_PACKAGE_alpine is not set\n# CONFIG_PACKAGE_bogofilter is not set\n# CONFIG_PACKAGE_dovecot is not set\n# CONFIG_PACKAGE_dovecot-pigeonhole is not set\n# CONFIG_PACKAGE_dovecot-utils is not set\n# CONFIG_PACKAGE_emailrelay is not set\n# CONFIG_PACKAGE_exim is not set\n# CONFIG_PACKAGE_exim-gnutls is not set\n# CONFIG_PACKAGE_exim-ldap is not set\n# CONFIG_PACKAGE_exim-openssl is not set\n# CONFIG_PACKAGE_fdm is not set\n# CONFIG_PACKAGE_greyfix is not set\n# CONFIG_PACKAGE_mailsend is not set\n# CONFIG_PACKAGE_mailsend-nossl is not set\n# CONFIG_PACKAGE_mblaze is not set\n# CONFIG_PACKAGE_msmtp is not set\n# CONFIG_PACKAGE_msmtp-mta is not set\n# CONFIG_PACKAGE_msmtp-nossl is not set\n# CONFIG_PACKAGE_msmtp-queue is not set\n# CONFIG_PACKAGE_mutt is not set\n# CONFIG_PACKAGE_nail is not set\n# CONFIG_PACKAGE_opendkim is not set\n# CONFIG_PACKAGE_opendkim-tools is not set\n# CONFIG_PACKAGE_postfix is not set\n# CONFIG_PACKAGE_spamc is not set\n# CONFIG_PACKAGE_spamc-ssl is not set\n# end of Mail\n\n#\n# Multimedia\n#\n\n#\n# Streaming\n#\n# CONFIG_PACKAGE_oggfwd is not set\n# end of Streaming\n\n# CONFIG_PACKAGE_ffmpeg is not set\n# CONFIG_PACKAGE_ffprobe is not set\n# CONFIG_PACKAGE_fswebcam is not set\n# CONFIG_PACKAGE_gerbera is not set\n# CONFIG_PACKAGE_gphoto2 is not set\n# CONFIG_PACKAGE_graphicsmagick is not set\n# CONFIG_PACKAGE_grilo is not set\n# CONFIG_PACKAGE_grilo-plugins is not set\n# CONFIG_PACKAGE_gst1-libav is not set\n# CONFIG_PACKAGE_gstreamer1-libs is not set\n# CONFIG_PACKAGE_gstreamer1-plugins-bad is not set\n# CONFIG_PACKAGE_gstreamer1-plugins-base is not set\n# CONFIG_PACKAGE_gstreamer1-plugins-good is not set\n# CONFIG_PACKAGE_gstreamer1-plugins-ugly is not set\n# CONFIG_PACKAGE_gstreamer1-utils is not set\n# CONFIG_PACKAGE_icecast is not set\n# CONFIG_PACKAGE_imagemagick is not set\n# CONFIG_PACKAGE_lcdgrilo is not set\nCONFIG_PACKAGE_minidlna=y\n# CONFIG_PACKAGE_minisatip is not set\nCONFIG_PACKAGE_mjpg-streamer=y\n# CONFIG_PACKAGE_mjpg-streamer-input-file is not set\n# CONFIG_PACKAGE_mjpg-streamer-input-http is not set\n# CONFIG_PACKAGE_mjpg-streamer-input-uvc is not set\n# CONFIG_PACKAGE_mjpg-streamer-output-file is not set\n# CONFIG_PACKAGE_mjpg-streamer-output-http is not set\n# CONFIG_PACKAGE_mjpg-streamer-output-rtsp is not set\n# CONFIG_PACKAGE_mjpg-streamer-output-zmq is not set\n# CONFIG_PACKAGE_mjpg-streamer-www is not set\n# CONFIG_PACKAGE_mjpg-streamer-www-simple is not set\n# CONFIG_PACKAGE_motion is not set\n# CONFIG_PACKAGE_tvheadend is not set\n# CONFIG_PACKAGE_v4l2rtspserver is not set\n# CONFIG_PACKAGE_v4l2tools is not set\n# CONFIG_PACKAGE_vips is not set\n# CONFIG_PACKAGE_xupnpd is not set\n# CONFIG_PACKAGE_youtube-dl is not set\n# end of Multimedia\n\n#\n# Network\n#\n\n#\n# BitTorrent\n#\n# CONFIG_PACKAGE_mktorrent is not set\n# CONFIG_PACKAGE_opentracker is not set\n# CONFIG_PACKAGE_opentracker6 is not set\n# CONFIG_PACKAGE_rtorrent is not set\n# CONFIG_PACKAGE_rtorrent-rpc is not set\n# CONFIG_PACKAGE_transmission-cli is not set\nCONFIG_PACKAGE_transmission-daemon=y\n# CONFIG_PACKAGE_transmission-remote is not set\n# CONFIG_PACKAGE_transmission-web is not set\n# CONFIG_PACKAGE_transmission-web-control is not set\n# end of BitTorrent\n\n#\n# Captive Portals\n#\n# CONFIG_PACKAGE_apfree-wifidog is not set\n# CONFIG_PACKAGE_coova-chilli is not set\n# CONFIG_PACKAGE_nodogsplash is not set\n# CONFIG_PACKAGE_opennds is not set\n# CONFIG_PACKAGE_wifidog is not set\n# CONFIG_PACKAGE_wifidog-tls is not set\n# end of Captive Portals\n\n#\n# Cloud Manager\n#\n# CONFIG_PACKAGE_cloudreve is not set\n# CONFIG_PACKAGE_rclone-ng is not set\n# CONFIG_PACKAGE_rclone-webui-react is not set\n# end of Cloud Manager\n\n#\n# Dial-in/up\n#\n# CONFIG_PACKAGE_rp-pppoe-common is not set\n# CONFIG_PACKAGE_rp-pppoe-relay is not set\n# CONFIG_PACKAGE_rp-pppoe-server is not set\n# end of Dial-in/up\n\n#\n# Download Manager\n#\nCONFIG_PACKAGE_ariang=y\n# CONFIG_PACKAGE_ariang-nginx is not set\n# CONFIG_PACKAGE_leech is not set\nCONFIG_PACKAGE_webui-aria2=y\n# end of Download Manager\n\n#\n# File Transfer\n#\nCONFIG_PACKAGE_aria2=y\n\n#\n# Aria2 Configuration\n#\nCONFIG_ARIA2_OPENSSL=y\n# CONFIG_ARIA2_GNUTLS is not set\n# CONFIG_ARIA2_NOSSL is not set\n# CONFIG_ARIA2_LIBXML2 is not set\n# CONFIG_ARIA2_EXPAT is not set\nCONFIG_ARIA2_NOXML=y\nCONFIG_ARIA2_BITTORRENT=y\n# CONFIG_ARIA2_SFTP is not set\n# CONFIG_ARIA2_ASYNC_DNS is not set\n# CONFIG_ARIA2_COOKIE is not set\nCONFIG_ARIA2_WEBSOCKET=y\n# end of Aria2 Configuration\n\n# CONFIG_PACKAGE_atftp is not set\n# CONFIG_PACKAGE_atftpd is not set\n# CONFIG_PACKAGE_curl is not set\n# CONFIG_PACKAGE_gnurl is not set\n# CONFIG_PACKAGE_lftp is not set\n# CONFIG_PACKAGE_rclone is not set\n# CONFIG_PACKAGE_rrsync is not set\nCONFIG_PACKAGE_rsync=y\n# CONFIG_RSYNC_xattr is not set\n# CONFIG_RSYNC_acl is not set\n# CONFIG_RSYNC_zstd is not set\nCONFIG_PACKAGE_rsyncd=y\n# CONFIG_PACKAGE_vsftpd is not set\n# CONFIG_PACKAGE_vsftpd-tls is not set\n# CONFIG_PACKAGE_wget-nossl is not set\n# CONFIG_PACKAGE_wget-ssl is not set\n# end of File Transfer\n\n#\n# Filesystem\n#\n# CONFIG_PACKAGE_davfs2 is not set\n# CONFIG_PACKAGE_ksmbd-avahi-service is not set\n# CONFIG_PACKAGE_ksmbd-server is not set\n# CONFIG_PACKAGE_ksmbd-utils is not set\n# CONFIG_PACKAGE_nfs-kernel-server is not set\n# CONFIG_PACKAGE_owftpd is not set\n# CONFIG_PACKAGE_owhttpd is not set\n# CONFIG_PACKAGE_owserver is not set\n# CONFIG_PACKAGE_sshfs is not set\n# end of Filesystem\n\n#\n# Firewall\n#\n# CONFIG_PACKAGE_arptables is not set\n# CONFIG_PACKAGE_conntrack is not set\n# CONFIG_PACKAGE_conntrackd is not set\n# CONFIG_PACKAGE_ebtables is not set\n# CONFIG_PACKAGE_fwknop is not set\n# CONFIG_PACKAGE_fwknopd is not set\nCONFIG_PACKAGE_ip6tables=y\n# CONFIG_PACKAGE_ip6tables-extra is not set\n# CONFIG_PACKAGE_ip6tables-mod-nat is not set\nCONFIG_PACKAGE_iptables=y\n# CONFIG_IPTABLES_CONNLABEL is not set\n# CONFIG_IPTABLES_NFTABLES is not set\n# CONFIG_PACKAGE_iptables-mod-account is not set\n# CONFIG_PACKAGE_iptables-mod-chaos is not set\n# CONFIG_PACKAGE_iptables-mod-checksum is not set\n# CONFIG_PACKAGE_iptables-mod-cluster is not set\n# CONFIG_PACKAGE_iptables-mod-clusterip is not set\n# CONFIG_PACKAGE_iptables-mod-condition is not set\nCONFIG_PACKAGE_iptables-mod-conntrack-extra=y\n# CONFIG_PACKAGE_iptables-mod-delude is not set\n# CONFIG_PACKAGE_iptables-mod-dhcpmac is not set\n# CONFIG_PACKAGE_iptables-mod-dnetmap is not set\nCONFIG_PACKAGE_iptables-mod-extra=y\n# CONFIG_PACKAGE_iptables-mod-filter is not set\n# CONFIG_PACKAGE_iptables-mod-fuzzy is not set\n# CONFIG_PACKAGE_iptables-mod-geoip is not set\n# CONFIG_PACKAGE_iptables-mod-hashlimit is not set\n# CONFIG_PACKAGE_iptables-mod-iface is not set\n# CONFIG_PACKAGE_iptables-mod-ipmark is not set\nCONFIG_PACKAGE_iptables-mod-ipopt=y\n# CONFIG_PACKAGE_iptables-mod-ipp2p is not set\n# CONFIG_PACKAGE_iptables-mod-iprange is not set\n# CONFIG_PACKAGE_iptables-mod-ipsec is not set\n# CONFIG_PACKAGE_iptables-mod-ipv4options is not set\n# CONFIG_PACKAGE_iptables-mod-led is not set\n# CONFIG_PACKAGE_iptables-mod-length2 is not set\n# CONFIG_PACKAGE_iptables-mod-logmark is not set\n# CONFIG_PACKAGE_iptables-mod-lscan is not set\n# CONFIG_PACKAGE_iptables-mod-lua is not set\n# CONFIG_PACKAGE_iptables-mod-nat-extra is not set\n# CONFIG_PACKAGE_iptables-mod-nflog is not set\n# CONFIG_PACKAGE_iptables-mod-nfqueue is not set\n# CONFIG_PACKAGE_iptables-mod-physdev is not set\n# CONFIG_PACKAGE_iptables-mod-proto is not set\n# CONFIG_PACKAGE_iptables-mod-psd is not set\n# CONFIG_PACKAGE_iptables-mod-quota2 is not set\n# CONFIG_PACKAGE_iptables-mod-rpfilter is not set\n# CONFIG_PACKAGE_iptables-mod-rtpengine is not set\n# CONFIG_PACKAGE_iptables-mod-sysrq is not set\n# CONFIG_PACKAGE_iptables-mod-tarpit is not set\n# CONFIG_PACKAGE_iptables-mod-tee is not set\nCONFIG_PACKAGE_iptables-mod-tproxy=y\n# CONFIG_PACKAGE_iptables-mod-trace is not set\n# CONFIG_PACKAGE_iptables-mod-u32 is not set\n# CONFIG_PACKAGE_iptables-mod-ulog is not set\n# CONFIG_PACKAGE_iptaccount is not set\n# CONFIG_PACKAGE_iptgeoip is not set\n\n#\n# Select iptgeoip options\n#\n# CONFIG_IPTGEOIP_PRESERVE is not set\n# end of Select iptgeoip options\n\n# CONFIG_PACKAGE_miniupnpc is not set\n# CONFIG_PACKAGE_miniupnpd is not set\n# CONFIG_PACKAGE_miniupnpd-igdv1 is not set\n# CONFIG_PACKAGE_natpmpc is not set\n# CONFIG_PACKAGE_nftables-json is not set\n# CONFIG_PACKAGE_nftables-nojson is not set\n# CONFIG_PACKAGE_shorewall is not set\n# CONFIG_PACKAGE_shorewall-core is not set\n# CONFIG_PACKAGE_shorewall-lite is not set\n# CONFIG_PACKAGE_shorewall6 is not set\n# CONFIG_PACKAGE_shorewall6-lite is not set\n# CONFIG_PACKAGE_snort is not set\n# CONFIG_PACKAGE_snort3 is not set\n# end of Firewall\n\n#\n# Firewall Tunnel\n#\n# CONFIG_PACKAGE_iodine is not set\n# CONFIG_PACKAGE_iodined is not set\n# end of Firewall Tunnel\n\n#\n# FreeRADIUS (version 3)\n#\n# CONFIG_PACKAGE_freeradius3 is not set\n# CONFIG_PACKAGE_freeradius3-common is not set\n# CONFIG_PACKAGE_freeradius3-utils is not set\n# end of FreeRADIUS (version 3)\n\n#\n# IP Addresses and Names\n#\n# CONFIG_PACKAGE_aggregate is not set\n# CONFIG_PACKAGE_announce is not set\n# CONFIG_PACKAGE_avahi-autoipd is not set\n# CONFIG_PACKAGE_avahi-daemon-service-http is not set\n# CONFIG_PACKAGE_avahi-daemon-service-ssh is not set\nCONFIG_PACKAGE_avahi-dbus-daemon=y\n# CONFIG_PACKAGE_avahi-dnsconfd is not set\n# CONFIG_PACKAGE_avahi-nodbus-daemon is not set\n# CONFIG_PACKAGE_avahi-utils is not set\n# CONFIG_PACKAGE_bind-check is not set\n# CONFIG_PACKAGE_bind-client is not set\n# CONFIG_PACKAGE_bind-dig is not set\n# CONFIG_PACKAGE_bind-dnssec is not set\n# CONFIG_PACKAGE_bind-host is not set\n# CONFIG_PACKAGE_bind-nslookup is not set\n# CONFIG_PACKAGE_bind-rndc is not set\n# CONFIG_PACKAGE_bind-server is not set\n# CONFIG_PACKAGE_bind-tools is not set\nCONFIG_PACKAGE_ddns-scripts=y\n# CONFIG_PACKAGE_ddns-scripts-cloudflare is not set\n# CONFIG_PACKAGE_ddns-scripts-cnkuai is not set\n# CONFIG_PACKAGE_ddns-scripts-digitalocean is not set\n# CONFIG_PACKAGE_ddns-scripts-dnspod is not set\n# CONFIG_PACKAGE_ddns-scripts-freedns is not set\n# CONFIG_PACKAGE_ddns-scripts-gandi is not set\n# CONFIG_PACKAGE_ddns-scripts-godaddy is not set\n# CONFIG_PACKAGE_ddns-scripts-noip is not set\n# CONFIG_PACKAGE_ddns-scripts-nsupdate is not set\n# CONFIG_PACKAGE_ddns-scripts-pdns is not set\n# CONFIG_PACKAGE_ddns-scripts-route53 is not set\nCONFIG_PACKAGE_ddns-scripts-services=y\n# CONFIG_PACKAGE_dhcp-forwarder is not set\n# CONFIG_PACKAGE_dns-over-https is not set\n# CONFIG_PACKAGE_dnscrypt-proxy is not set\n# CONFIG_PACKAGE_dnscrypt-proxy-resolvers is not set\n# CONFIG_PACKAGE_dnsdist is not set\n# CONFIG_PACKAGE_dnslookup is not set\n# CONFIG_PACKAGE_dnsproxy is not set\n# CONFIG_PACKAGE_drill is not set\n# CONFIG_PACKAGE_hostip is not set\n# CONFIG_PACKAGE_idn is not set\n# CONFIG_PACKAGE_idn2 is not set\n# CONFIG_PACKAGE_inadyn is not set\n# CONFIG_PACKAGE_isc-dhcp-client-ipv4 is not set\n# CONFIG_PACKAGE_isc-dhcp-client-ipv6 is not set\n# CONFIG_PACKAGE_isc-dhcp-omshell-ipv4 is not set\n# CONFIG_PACKAGE_isc-dhcp-omshell-ipv6 is not set\n# CONFIG_PACKAGE_isc-dhcp-relay-ipv4 is not set\n# CONFIG_PACKAGE_isc-dhcp-relay-ipv6 is not set\n# CONFIG_PACKAGE_isc-dhcp-server-ipv4 is not set\n# CONFIG_PACKAGE_isc-dhcp-server-ipv6 is not set\n# CONFIG_PACKAGE_kadnode is not set\n# CONFIG_PACKAGE_kea-admin is not set\n# CONFIG_PACKAGE_kea-ctrl is not set\n# CONFIG_PACKAGE_kea-dhcp-ddns is not set\n# CONFIG_PACKAGE_kea-dhcp4 is not set\n# CONFIG_PACKAGE_kea-dhcp6 is not set\n# CONFIG_PACKAGE_kea-hook-ha is not set\n# CONFIG_PACKAGE_kea-hook-lease-cmds is not set\n# CONFIG_PACKAGE_kea-lfc is not set\n# CONFIG_PACKAGE_kea-libs is not set\n# CONFIG_PACKAGE_kea-perfdhcp is not set\n# CONFIG_PACKAGE_kea-shell is not set\n# CONFIG_PACKAGE_knot is not set\n# CONFIG_PACKAGE_knot-dig is not set\n# CONFIG_PACKAGE_knot-host is not set\n# CONFIG_PACKAGE_knot-keymgr is not set\n# CONFIG_PACKAGE_knot-nsupdate is not set\n# CONFIG_PACKAGE_knot-resolver is not set\n\n#\n# Configuration\n#\n# CONFIG_PACKAGE_knot-resolver_dnstap is not set\n# end of Configuration\n\n# CONFIG_PACKAGE_knot-tests is not set\n# CONFIG_PACKAGE_knot-zonecheck is not set\n# CONFIG_PACKAGE_ldns-examples is not set\n# CONFIG_PACKAGE_mdns-utils is not set\n# CONFIG_PACKAGE_mdnsd is not set\n# CONFIG_PACKAGE_mdnsresponder is not set\n# CONFIG_PACKAGE_nsd is not set\n# CONFIG_PACKAGE_nsd-control is not set\n# CONFIG_PACKAGE_nsd-control-setup is not set\n# CONFIG_PACKAGE_nsd-nossl is not set\n# CONFIG_PACKAGE_ohybridproxy is not set\n# CONFIG_PACKAGE_overture is not set\n# CONFIG_PACKAGE_pdns is not set\n# CONFIG_PACKAGE_pdns-ixfrdist is not set\n# CONFIG_PACKAGE_pdns-recursor is not set\n# CONFIG_PACKAGE_pdns-tools is not set\n# CONFIG_PACKAGE_stubby is not set\n# CONFIG_PACKAGE_tor-hs is not set\n# CONFIG_PACKAGE_torsocks is not set\n# CONFIG_PACKAGE_unbound-anchor is not set\n# CONFIG_PACKAGE_unbound-checkconf is not set\n# CONFIG_PACKAGE_unbound-control is not set\n# CONFIG_PACKAGE_unbound-control-setup is not set\nCONFIG_PACKAGE_unbound-daemon=y\n# CONFIG_PACKAGE_unbound-host is not set\nCONFIG_PACKAGE_wsdd2=y\n# CONFIG_PACKAGE_zonestitcher is not set\n# end of IP Addresses and Names\n\n#\n# Instant Messaging\n#\n# CONFIG_PACKAGE_bitlbee is not set\n# CONFIG_PACKAGE_irssi is not set\n# CONFIG_PACKAGE_ngircd is not set\n# CONFIG_PACKAGE_ngircd-nossl is not set\n# CONFIG_PACKAGE_prosody is not set\n# CONFIG_PACKAGE_quassel-irssi is not set\n# CONFIG_PACKAGE_umurmur-mbedtls is not set\n# CONFIG_PACKAGE_umurmur-openssl is not set\n# CONFIG_PACKAGE_znc is not set\n# end of Instant Messaging\n\n#\n# Linux ATM tools\n#\n# CONFIG_PACKAGE_atm-aread is not set\n# CONFIG_PACKAGE_atm-atmaddr is not set\n# CONFIG_PACKAGE_atm-atmdiag is not set\n# CONFIG_PACKAGE_atm-atmdump is not set\n# CONFIG_PACKAGE_atm-atmloop is not set\n# CONFIG_PACKAGE_atm-atmsigd is not set\n# CONFIG_PACKAGE_atm-atmswitch is not set\n# CONFIG_PACKAGE_atm-atmtcp is not set\n# CONFIG_PACKAGE_atm-awrite is not set\n# CONFIG_PACKAGE_atm-bus is not set\n# CONFIG_PACKAGE_atm-debug-tools is not set\n# CONFIG_PACKAGE_atm-diagnostics is not set\n# CONFIG_PACKAGE_atm-esi is not set\n# CONFIG_PACKAGE_atm-ilmid is not set\n# CONFIG_PACKAGE_atm-ilmidiag is not set\n# CONFIG_PACKAGE_atm-lecs is not set\n# CONFIG_PACKAGE_atm-les is not set\n# CONFIG_PACKAGE_atm-mpcd is not set\n# CONFIG_PACKAGE_atm-saaldump is not set\n# CONFIG_PACKAGE_atm-sonetdiag is not set\n# CONFIG_PACKAGE_atm-svc_recv is not set\n# CONFIG_PACKAGE_atm-svc_send is not set\n# CONFIG_PACKAGE_atm-tools is not set\n# CONFIG_PACKAGE_atm-ttcp_atm is not set\n# CONFIG_PACKAGE_atm-zeppelin is not set\n# CONFIG_PACKAGE_br2684ctl is not set\n# end of Linux ATM tools\n\n#\n# LoRaWAN\n#\n# CONFIG_PACKAGE_libloragw-tests is not set\n# CONFIG_PACKAGE_libloragw-utils is not set\n# end of LoRaWAN\n\n#\n# NMAP Suite\n#\n# CONFIG_PACKAGE_ncat is not set\n# CONFIG_PACKAGE_ncat-full is not set\n# CONFIG_PACKAGE_ncat-ssl is not set\n# CONFIG_PACKAGE_ndiff is not set\n# CONFIG_PACKAGE_nmap is not set\n# CONFIG_PACKAGE_nmap-full is not set\n# CONFIG_PACKAGE_nmap-ssl is not set\n# CONFIG_PACKAGE_nping is not set\n# CONFIG_PACKAGE_nping-ssl is not set\n# end of NMAP Suite\n\n#\n# NTRIP\n#\n# CONFIG_PACKAGE_ntripcaster is not set\n# CONFIG_PACKAGE_ntripclient is not set\n# CONFIG_PACKAGE_ntripserver is not set\n# end of NTRIP\n\n#\n# OLSR.org network framework\n#\n# CONFIG_PACKAGE_oonf-dlep-proxy is not set\n# CONFIG_PACKAGE_oonf-dlep-radio is not set\n# CONFIG_PACKAGE_oonf-init-scripts is not set\n# CONFIG_PACKAGE_oonf-olsrd2 is not set\n# end of OLSR.org network framework\n\n#\n# Open vSwitch\n#\n# CONFIG_PACKAGE_openvswitch is not set\n# CONFIG_PACKAGE_openvswitch-ovn-host is not set\n# CONFIG_PACKAGE_openvswitch-ovn-north is not set\n# CONFIG_PACKAGE_openvswitch-python3 is not set\n# CONFIG_PACKAGE_ovsd is not set\n# end of Open vSwitch\n\n#\n# OpenLDAP\n#\n# CONFIG_PACKAGE_libopenldap is not set\nCONFIG_OPENLDAP_DEBUG=y\n# CONFIG_OPENLDAP_CRYPT is not set\n# CONFIG_OPENLDAP_MONITOR is not set\n# CONFIG_OPENLDAP_DB47 is not set\n# CONFIG_OPENLDAP_ICU is not set\n# CONFIG_PACKAGE_openldap-server is not set\n# CONFIG_PACKAGE_openldap-utils is not set\n# end of OpenLDAP\n\n#\n# Printing\n#\n# CONFIG_PACKAGE_p910nd is not set\n# end of Printing\n\n#\n# Routing and Redirection\n#\n# CONFIG_PACKAGE_babel-pinger is not set\n# CONFIG_PACKAGE_babeld is not set\n# CONFIG_PACKAGE_batmand is not set\n# CONFIG_PACKAGE_bcp38 is not set\n# CONFIG_PACKAGE_bfdd is not set\n# CONFIG_PACKAGE_bird1-ipv4 is not set\n# CONFIG_PACKAGE_bird1-ipv4-uci is not set\n# CONFIG_PACKAGE_bird1-ipv6 is not set\n# CONFIG_PACKAGE_bird1-ipv6-uci is not set\n# CONFIG_PACKAGE_bird1c-ipv4 is not set\n# CONFIG_PACKAGE_bird1c-ipv6 is not set\n# CONFIG_PACKAGE_bird1cl-ipv4 is not set\n# CONFIG_PACKAGE_bird1cl-ipv6 is not set\n# CONFIG_PACKAGE_bird2 is not set\n# CONFIG_PACKAGE_bird2c is not set\n# CONFIG_PACKAGE_bird2cl is not set\n# CONFIG_PACKAGE_bmx6 is not set\n# CONFIG_PACKAGE_bmx7 is not set\n# CONFIG_PACKAGE_cjdns is not set\n# CONFIG_PACKAGE_cjdns-tests is not set\n# CONFIG_PACKAGE_dcstad is not set\n# CONFIG_PACKAGE_dcwapd is not set\n# CONFIG_PACKAGE_devlink is not set\n# CONFIG_PACKAGE_frr is not set\n# CONFIG_PACKAGE_genl is not set\n# CONFIG_PACKAGE_igmpproxy is not set\n# CONFIG_PACKAGE_ip-bridge is not set\n# CONFIG_PACKAGE_ip-full is not set\nCONFIG_PACKAGE_ip-tiny=y\n# CONFIG_PACKAGE_lldpd is not set\n# CONFIG_PACKAGE_mcproxy is not set\n# CONFIG_PACKAGE_mrmctl is not set\n# CONFIG_PACKAGE_mwan3 is not set\n# CONFIG_PACKAGE_nstat is not set\n# CONFIG_PACKAGE_olsrd is not set\n# CONFIG_PACKAGE_prince is not set\n# CONFIG_PACKAGE_quagga is not set\n# CONFIG_PACKAGE_rdma is not set\n# CONFIG_PACKAGE_relayd is not set\n# CONFIG_PACKAGE_smcroute is not set\n# CONFIG_PACKAGE_ss is not set\n# CONFIG_PACKAGE_sslh is not set\n# CONFIG_PACKAGE_tc-full is not set\nCONFIG_PACKAGE_tc-mod-iptables=y\nCONFIG_PACKAGE_tc-tiny=y\n# CONFIG_PACKAGE_tcpproxy is not set\n# CONFIG_PACKAGE_udp-broadcast-relay-redux is not set\n# CONFIG_PACKAGE_vis is not set\n# CONFIG_PACKAGE_yggdrasil is not set\n# end of Routing and Redirection\n\n#\n# SSH\n#\n# CONFIG_PACKAGE_autossh is not set\nCONFIG_PACKAGE_openssh-client=y\n# CONFIG_PACKAGE_openssh-client-utils is not set\nCONFIG_PACKAGE_openssh-keygen=y\n# CONFIG_PACKAGE_openssh-moduli is not set\nCONFIG_PACKAGE_openssh-server=y\nCONFIG_OPENSSH_LIBFIDO2=y\n# CONFIG_PACKAGE_openssh-server-pam is not set\nCONFIG_PACKAGE_openssh-sftp-avahi-service=y\nCONFIG_PACKAGE_openssh-sftp-client=y\nCONFIG_PACKAGE_openssh-sftp-server=y\n# CONFIG_PACKAGE_sshtunnel is not set\n# CONFIG_PACKAGE_tmate is not set\n# end of SSH\n\n#\n# THC-IPv6 attack and analyzing toolkit\n#\n# CONFIG_PACKAGE_thc-ipv6-address6 is not set\n# CONFIG_PACKAGE_thc-ipv6-alive6 is not set\n# CONFIG_PACKAGE_thc-ipv6-covert-send6 is not set\n# CONFIG_PACKAGE_thc-ipv6-covert-send6d is not set\n# CONFIG_PACKAGE_thc-ipv6-denial6 is not set\n# CONFIG_PACKAGE_thc-ipv6-detect-new-ip6 is not set\n# CONFIG_PACKAGE_thc-ipv6-detect-sniffer6 is not set\n# CONFIG_PACKAGE_thc-ipv6-dnsdict6 is not set\n# CONFIG_PACKAGE_thc-ipv6-dnsrevenum6 is not set\n# CONFIG_PACKAGE_thc-ipv6-dos-new-ip6 is not set\n# CONFIG_PACKAGE_thc-ipv6-dump-router6 is not set\n# CONFIG_PACKAGE_thc-ipv6-exploit6 is not set\n# CONFIG_PACKAGE_thc-ipv6-fake-advertise6 is not set\n# CONFIG_PACKAGE_thc-ipv6-fake-dhcps6 is not set\n# CONFIG_PACKAGE_thc-ipv6-fake-dns6d is not set\n# CONFIG_PACKAGE_thc-ipv6-fake-dnsupdate6 is not set\n# CONFIG_PACKAGE_thc-ipv6-fake-mipv6 is not set\n# CONFIG_PACKAGE_thc-ipv6-fake-mld26 is not set\n# CONFIG_PACKAGE_thc-ipv6-fake-mld6 is not set\n# CONFIG_PACKAGE_thc-ipv6-fake-mldrouter6 is not set\n# CONFIG_PACKAGE_thc-ipv6-fake-router26 is not set\n# CONFIG_PACKAGE_thc-ipv6-fake-router6 is not set\n# CONFIG_PACKAGE_thc-ipv6-fake-solicitate6 is not set\n# CONFIG_PACKAGE_thc-ipv6-flood-advertise6 is not set\n# CONFIG_PACKAGE_thc-ipv6-flood-dhcpc6 is not set\n# CONFIG_PACKAGE_thc-ipv6-flood-mld26 is not set\n# CONFIG_PACKAGE_thc-ipv6-flood-mld6 is not set\n# CONFIG_PACKAGE_thc-ipv6-flood-mldrouter6 is not set\n# CONFIG_PACKAGE_thc-ipv6-flood-router26 is not set\n# CONFIG_PACKAGE_thc-ipv6-flood-router6 is not set\n# CONFIG_PACKAGE_thc-ipv6-flood-solicitate6 is not set\n# CONFIG_PACKAGE_thc-ipv6-fragmentation6 is not set\n# CONFIG_PACKAGE_thc-ipv6-fuzz-dhcpc6 is not set\n# CONFIG_PACKAGE_thc-ipv6-fuzz-dhcps6 is not set\n# CONFIG_PACKAGE_thc-ipv6-fuzz-ip6 is not set\n# CONFIG_PACKAGE_thc-ipv6-implementation6 is not set\n# CONFIG_PACKAGE_thc-ipv6-implementation6d is not set\n# CONFIG_PACKAGE_thc-ipv6-inverse-lookup6 is not set\n# CONFIG_PACKAGE_thc-ipv6-kill-router6 is not set\n# CONFIG_PACKAGE_thc-ipv6-ndpexhaust6 is not set\n# CONFIG_PACKAGE_thc-ipv6-node-query6 is not set\n# CONFIG_PACKAGE_thc-ipv6-parasite6 is not set\n# CONFIG_PACKAGE_thc-ipv6-passive-discovery6 is not set\n# CONFIG_PACKAGE_thc-ipv6-randicmp6 is not set\n# CONFIG_PACKAGE_thc-ipv6-redir6 is not set\n# CONFIG_PACKAGE_thc-ipv6-rsmurf6 is not set\n# CONFIG_PACKAGE_thc-ipv6-sendpees6 is not set\n# CONFIG_PACKAGE_thc-ipv6-sendpeesmp6 is not set\n# CONFIG_PACKAGE_thc-ipv6-smurf6 is not set\n# CONFIG_PACKAGE_thc-ipv6-thcping6 is not set\n# CONFIG_PACKAGE_thc-ipv6-toobig6 is not set\n# CONFIG_PACKAGE_thc-ipv6-trace6 is not set\n# end of THC-IPv6 attack and analyzing toolkit\n\n#\n# Tcpreplay\n#\n# CONFIG_PACKAGE_tcpbridge is not set\n# CONFIG_PACKAGE_tcpcapinfo is not set\n# CONFIG_PACKAGE_tcpliveplay is not set\n# CONFIG_PACKAGE_tcpprep is not set\n# CONFIG_PACKAGE_tcpreplay is not set\n# CONFIG_PACKAGE_tcpreplay-all is not set\n# CONFIG_PACKAGE_tcpreplay-edit is not set\n# CONFIG_PACKAGE_tcprewrite is not set\n# end of Tcpreplay\n\n#\n# Telephony\n#\n# CONFIG_PACKAGE_asterisk is not set\n# CONFIG_PACKAGE_baresip is not set\n# CONFIG_PACKAGE_freeswitch is not set\n# CONFIG_PACKAGE_kamailio is not set\n# CONFIG_PACKAGE_miax is not set\n# CONFIG_PACKAGE_pcapsipdump is not set\n# CONFIG_PACKAGE_restund is not set\n# CONFIG_PACKAGE_rtpengine is not set\n# CONFIG_PACKAGE_rtpengine-no-transcode is not set\n# CONFIG_PACKAGE_rtpengine-recording is not set\n# CONFIG_PACKAGE_rtpproxy is not set\n# CONFIG_PACKAGE_sipp is not set\n# CONFIG_PACKAGE_siproxd is not set\n# CONFIG_PACKAGE_yate is not set\n# end of Telephony\n\n#\n# Telephony Lantiq\n#\n# end of Telephony Lantiq\n\n#\n# Time Synchronization\n#\n# CONFIG_PACKAGE_chrony is not set\n# CONFIG_PACKAGE_chrony-nts is not set\n# CONFIG_PACKAGE_htpdate is not set\n# CONFIG_PACKAGE_linuxptp is not set\n# CONFIG_PACKAGE_ntp-keygen is not set\n# CONFIG_PACKAGE_ntp-utils is not set\nCONFIG_PACKAGE_ntpclient=y\n# CONFIG_PACKAGE_ntpd is not set\n# CONFIG_PACKAGE_ntpdate is not set\n# end of Time Synchronization\n\n#\n# VPN\n#\n# CONFIG_PACKAGE_chaosvpn is not set\n# CONFIG_PACKAGE_eoip is not set\n# CONFIG_PACKAGE_fastd is not set\n# CONFIG_PACKAGE_libreswan is not set\n# CONFIG_PACKAGE_ocserv is not set\n# CONFIG_PACKAGE_openconnect is not set\n# CONFIG_PACKAGE_openfortivpn is not set\n# CONFIG_PACKAGE_openvpn-easy-rsa is not set\n# CONFIG_PACKAGE_openvpn-mbedtls is not set\n# CONFIG_PACKAGE_openvpn-openssl is not set\n# CONFIG_PACKAGE_openvpn-wolfssl is not set\n# CONFIG_PACKAGE_pptpd is not set\n# CONFIG_PACKAGE_softethervpn-base is not set\n# CONFIG_PACKAGE_softethervpn-bridge is not set\n# CONFIG_PACKAGE_softethervpn-client is not set\n# CONFIG_PACKAGE_softethervpn-server is not set\n# CONFIG_PACKAGE_softethervpn5-bridge is not set\n# CONFIG_PACKAGE_softethervpn5-client is not set\n# CONFIG_PACKAGE_softethervpn5-server is not set\n# CONFIG_PACKAGE_sstp-client is not set\n# CONFIG_PACKAGE_strongswan is not set\n# CONFIG_PACKAGE_tailscale is not set\n# CONFIG_PACKAGE_tailscaled is not set\n# CONFIG_PACKAGE_tinc is not set\n# CONFIG_PACKAGE_uanytun is not set\n# CONFIG_PACKAGE_uanytun-nettle is not set\n# CONFIG_PACKAGE_uanytun-nocrypt is not set\n# CONFIG_PACKAGE_uanytun-sslcrypt is not set\n# CONFIG_PACKAGE_vpnc is not set\n# CONFIG_PACKAGE_vpnc-scripts is not set\nCONFIG_PACKAGE_wireguard-tools=y\n# CONFIG_PACKAGE_xl2tpd is not set\nCONFIG_PACKAGE_zerotier=y\n\n#\n# Configuration\n#\n# CONFIG_ZEROTIER_ENABLE_DEBUG is not set\n# CONFIG_ZEROTIER_ENABLE_SELFTEST is not set\n# end of Configuration\n# end of VPN\n\n#\n# Version Control Systems\n#\n# CONFIG_PACKAGE_git is not set\n# CONFIG_PACKAGE_git-http is not set\n# CONFIG_PACKAGE_subversion-client is not set\n# CONFIG_PACKAGE_subversion-libs is not set\n# CONFIG_PACKAGE_subversion-server is not set\n# end of Version Control Systems\n\n#\n# WWAN\n#\n# CONFIG_PACKAGE_adb-enablemodem is not set\n# CONFIG_PACKAGE_comgt is not set\n# CONFIG_PACKAGE_comgt-directip is not set\n# CONFIG_PACKAGE_comgt-ncm is not set\n# CONFIG_PACKAGE_umbim is not set\n# CONFIG_PACKAGE_uqmi is not set\n# end of WWAN\n\n#\n# Web Servers/Proxies\n#\n# CONFIG_PACKAGE_apache is not set\nCONFIG_PACKAGE_cgi-io=y\n# CONFIG_PACKAGE_clamav is not set\n# CONFIG_PACKAGE_etebase is not set\n# CONFIG_PACKAGE_freshclam is not set\n# CONFIG_PACKAGE_frpc is not set\n# CONFIG_PACKAGE_frps is not set\n# CONFIG_PACKAGE_gateway-go is not set\n# CONFIG_PACKAGE_gunicorn3 is not set\n# CONFIG_PACKAGE_haproxy is not set\n# CONFIG_PACKAGE_haproxy-nossl is not set\n# CONFIG_PACKAGE_kcptun-client is not set\n# CONFIG_PACKAGE_kcptun-config is not set\n# CONFIG_PACKAGE_kcptun-server is not set\n# CONFIG_PACKAGE_lighttpd is not set\n# CONFIG_PACKAGE_nginx-all-module is not set\n# CONFIG_PACKAGE_nginx-mod-luci is not set\n# CONFIG_PACKAGE_nginx-ssl is not set\n# CONFIG_PACKAGE_nginx-ssl-util is not set\n# CONFIG_PACKAGE_nginx-ssl-util-nopcre is not set\n# CONFIG_PACKAGE_polipo is not set\n# CONFIG_PACKAGE_privoxy is not set\n# CONFIG_PACKAGE_python3-gunicorn is not set\n# CONFIG_PACKAGE_radicale is not set\n# CONFIG_PACKAGE_radicale2 is not set\n# CONFIG_PACKAGE_radicale2-examples is not set\nCONFIG_PACKAGE_shadowsocks-libev-config=y\nCONFIG_PACKAGE_shadowsocks-libev-ss-local=y\nCONFIG_PACKAGE_shadowsocks-libev-ss-redir=y\nCONFIG_PACKAGE_shadowsocks-libev-ss-rules=y\nCONFIG_PACKAGE_shadowsocks-libev-ss-server=y\nCONFIG_PACKAGE_shadowsocks-libev-ss-tunnel=y\n# CONFIG_PACKAGE_sockd is not set\n# CONFIG_PACKAGE_socksify is not set\n# CONFIG_PACKAGE_spawn-fcgi is not set\nCONFIG_PACKAGE_squid=y\n\n#\n# Optional features\n#\nCONFIG_SQUID_enable-ipv6=y\n# CONFIG_SQUID_enable-snmp is not set\n# CONFIG_SQUID_enable-icmp is not set\n# CONFIG_SQUID_enable-icap-client is not set\nCONFIG_SQUID_enable-dlmalloc=y\n# CONFIG_SQUID_enable-ssl-crtd is not set\n# CONFIG_SQUID_auth-basic is not set\n# CONFIG_SQUID_auth-digest is not set\n# CONFIG_SQUID_auth-negotiate is not set\n# CONFIG_SQUID_auth-ntlm is not set\n\n#\n# Optional packages\n#\nCONFIG_SQUID_use-openssl=y\n# CONFIG_SQUID_use-gnutls is not set\n# CONFIG_SQUID_with-libcap is not set\n# CONFIG_SQUID_with-nettle is not set\n# CONFIG_SQUID_with-expat is not set\n# CONFIG_SQUID_with-libxml2 is not set\n\n#\n# Additional tools\n#\n# CONFIG_PACKAGE_squid-mod-cachemgr is not set\n# CONFIG_PACKAGE_tinyproxy is not set\n# CONFIG_PACKAGE_trojan-go is not set\nCONFIG_PACKAGE_uhttpd=y\n# CONFIG_PACKAGE_uhttpd-mod-lua is not set\nCONFIG_PACKAGE_uhttpd-mod-ubus=y\n# CONFIG_PACKAGE_uwsgi is not set\n# CONFIG_PACKAGE_v2raya is not set\n# end of Web Servers/Proxies\n\n#\n# Wireless\n#\n# CONFIG_PACKAGE_aircrack-ng is not set\n# CONFIG_PACKAGE_airmon-ng is not set\n# CONFIG_PACKAGE_dynapoint is not set\n# CONFIG_PACKAGE_hcxdumptool is not set\n# CONFIG_PACKAGE_hcxtools is not set\n# CONFIG_PACKAGE_horst is not set\n# CONFIG_PACKAGE_pixiewps is not set\n# CONFIG_PACKAGE_reaver is not set\n# CONFIG_PACKAGE_wavemon is not set\n# CONFIG_PACKAGE_wifischedule is not set\n# end of Wireless\n\n#\n# WirelessAPD\n#\n# CONFIG_PACKAGE_eapol-test is not set\n# CONFIG_PACKAGE_eapol-test-openssl is not set\n# CONFIG_PACKAGE_eapol-test-wolfssl is not set\n# CONFIG_PACKAGE_hostapd is not set\n# CONFIG_PACKAGE_hostapd-basic is not set\n# CONFIG_PACKAGE_hostapd-basic-openssl is not set\n# CONFIG_PACKAGE_hostapd-basic-wolfssl is not set\nCONFIG_PACKAGE_hostapd-common=y\n# CONFIG_PACKAGE_hostapd-mini is not set\n# CONFIG_PACKAGE_hostapd-openssl is not set\n# CONFIG_PACKAGE_hostapd-wolfssl is not set\n# CONFIG_PACKAGE_hs20-client is not set\n# CONFIG_PACKAGE_hs20-common is not set\n# CONFIG_PACKAGE_hs20-server is not set\n# CONFIG_PACKAGE_wpa-cli is not set\nCONFIG_PACKAGE_wpa-supplicant=y\n# CONFIG_WPA_RFKILL_SUPPORT is not set\nCONFIG_WPA_MSG_MIN_PRIORITY=3\n# CONFIG_WPA_WOLFSSL is not set\n# CONFIG_DRIVER_WEXT_SUPPORT is not set\nCONFIG_DRIVER_11N_SUPPORT=y\nCONFIG_DRIVER_11AC_SUPPORT=y\n# CONFIG_DRIVER_11AX_SUPPORT is not set\n# CONFIG_WPA_ENABLE_WEP is not set\n# CONFIG_PACKAGE_wpa-supplicant-basic is not set\n# CONFIG_PACKAGE_wpa-supplicant-mesh-openssl is not set\n# CONFIG_PACKAGE_wpa-supplicant-mesh-wolfssl is not set\n# CONFIG_PACKAGE_wpa-supplicant-mini is not set\n# CONFIG_PACKAGE_wpa-supplicant-openssl is not set\n# CONFIG_PACKAGE_wpa-supplicant-p2p is not set\n# CONFIG_PACKAGE_wpa-supplicant-wolfssl is not set\n# CONFIG_PACKAGE_wpad is not set\n# CONFIG_PACKAGE_wpad-basic is not set\n# CONFIG_PACKAGE_wpad-basic-openssl is not set\n# CONFIG_PACKAGE_wpad-basic-wolfssl is not set\n# CONFIG_PACKAGE_wpad-mesh-openssl is not set\n# CONFIG_PACKAGE_wpad-mesh-wolfssl is not set\n# CONFIG_PACKAGE_wpad-mini is not set\n# CONFIG_PACKAGE_wpad-openssl is not set\n# CONFIG_PACKAGE_wpad-wolfssl is not set\n# end of WirelessAPD\n\n#\n# arp-scan\n#\n# CONFIG_PACKAGE_arp-scan is not set\n# CONFIG_PACKAGE_arp-scan-database is not set\n# end of arp-scan\n\n# CONFIG_PACKAGE_464xlat is not set\n# CONFIG_PACKAGE_6in4 is not set\n# CONFIG_PACKAGE_6rd is not set\n# CONFIG_PACKAGE_6to4 is not set\n# CONFIG_PACKAGE_UDPspeeder is not set\n# CONFIG_PACKAGE_acme is not set\n# CONFIG_PACKAGE_acme-dnsapi is not set\nCONFIG_PACKAGE_adblock=y\n# CONFIG_PACKAGE_addrwatch is not set\n# CONFIG_PACKAGE_addrwatch-mysql is not set\n# CONFIG_PACKAGE_addrwatch-stdout is not set\n# CONFIG_PACKAGE_addrwatch-syslog is not set\n# CONFIG_PACKAGE_adguardhome is not set\n# CONFIG_PACKAGE_ahcpd is not set\n# CONFIG_PACKAGE_alfred is not set\n# CONFIG_PACKAGE_apcupsd is not set\n# CONFIG_PACKAGE_apcupsd-cgi is not set\n# CONFIG_PACKAGE_apinger is not set\n# CONFIG_PACKAGE_atlas-probe is not set\n# CONFIG_PACKAGE_atlas-sw-probe is not set\n# CONFIG_PACKAGE_atlas-sw-probe-rpc is not set\nCONFIG_PACKAGE_banip=y\n# CONFIG_PACKAGE_batctl-default is not set\n# CONFIG_PACKAGE_batctl-full is not set\n# CONFIG_PACKAGE_batctl-tiny is not set\n# CONFIG_PACKAGE_beanstalkd is not set\nCONFIG_PACKAGE_bmon=y\n# CONFIG_PACKAGE_boinc is not set\n# CONFIG_PACKAGE_bpftool-full is not set\n# CONFIG_PACKAGE_bpftool-minimal is not set\n# CONFIG_PACKAGE_bwm-ng is not set\n# CONFIG_PACKAGE_bwping is not set\n# CONFIG_PACKAGE_chat is not set\n# CONFIG_PACKAGE_cifsmount is not set\n# CONFIG_PACKAGE_coap-server is not set\n# CONFIG_PACKAGE_conserver is not set\n# CONFIG_PACKAGE_crowdsec is not set\n# CONFIG_PACKAGE_crowdsec-firewall-bouncer is not set\n# CONFIG_PACKAGE_cshark is not set\n# CONFIG_PACKAGE_daemonlogger is not set\n# CONFIG_PACKAGE_darkstat is not set\n# CONFIG_PACKAGE_dawn is not set\n# CONFIG_PACKAGE_dhcpcd is not set\n# CONFIG_PACKAGE_dmapd is not set\n# CONFIG_PACKAGE_dnscrypt-proxy2 is not set\n# CONFIG_PACKAGE_dnstap is not set\n# CONFIG_PACKAGE_dnstop is not set\n# CONFIG_PACKAGE_ds-lite is not set\n# CONFIG_PACKAGE_esniper is not set\n# CONFIG_PACKAGE_etherwake is not set\n# CONFIG_PACKAGE_etherwake-nfqueue is not set\n# CONFIG_PACKAGE_ethtool is not set\n# CONFIG_PACKAGE_ethtool-full is not set\n# CONFIG_PACKAGE_fail2ban is not set\n# CONFIG_PACKAGE_fakeidentd is not set\n# CONFIG_PACKAGE_fakepop is not set\n# CONFIG_PACKAGE_family-dns is not set\n# CONFIG_PACKAGE_foolsm is not set\n# CONFIG_PACKAGE_fping is not set\n# CONFIG_PACKAGE_generate-ipv6-address is not set\n# CONFIG_PACKAGE_geth is not set\n# CONFIG_PACKAGE_git-lfs is not set\n# CONFIG_PACKAGE_gnunet is not set\n# CONFIG_PACKAGE_gre is not set\n# CONFIG_PACKAGE_hnet-full is not set\n# CONFIG_PACKAGE_hnet-full-l2tp is not set\n# CONFIG_PACKAGE_hnet-full-secure is not set\n# CONFIG_PACKAGE_hnetd-nossl is not set\n# CONFIG_PACKAGE_hnetd-openssl is not set\n# CONFIG_PACKAGE_httping is not set\n# CONFIG_PACKAGE_httping-nossl is not set\n# CONFIG_PACKAGE_https-dns-proxy is not set\n# CONFIG_PACKAGE_httptunnel is not set\n# CONFIG_PACKAGE_i2pd is not set\n# CONFIG_PACKAGE_ibrdtn-tools is not set\n# CONFIG_PACKAGE_ibrdtnd is not set\n# CONFIG_PACKAGE_ieee8021xclient is not set\nCONFIG_PACKAGE_ifstat=y\nCONFIG_IFSTAT_SNMP=y\nCONFIG_PACKAGE_iftop=y\n# CONFIG_PACKAGE_iiod is not set\nCONFIG_PACKAGE_iperf=y\n# CONFIG_IPERF_ENABLE_MULTICAST is not set\nCONFIG_PACKAGE_iperf3=y\n# CONFIG_PACKAGE_iperf3-ssl is not set\n# CONFIG_PACKAGE_ipip is not set\nCONFIG_PACKAGE_ipset=y\n# CONFIG_PACKAGE_ipset-dns is not set\n# CONFIG_PACKAGE_iptraf-ng is not set\n# CONFIG_PACKAGE_iputils-arping is not set\n# CONFIG_PACKAGE_iputils-clockdiff is not set\n# CONFIG_PACKAGE_iputils-ping is not set\n# CONFIG_PACKAGE_iputils-tftpd is not set\n# CONFIG_PACKAGE_iputils-tracepath is not set\n# CONFIG_PACKAGE_ipvsadm is not set\n# CONFIG_PACKAGE_irtt is not set\nCONFIG_PACKAGE_iw=y\n# CONFIG_PACKAGE_iw-full is not set\n# CONFIG_PACKAGE_jool-tools is not set\n# CONFIG_PACKAGE_keepalived is not set\n# CONFIG_PACKAGE_knxd is not set\n# CONFIG_PACKAGE_kplex is not set\n# CONFIG_PACKAGE_krb5-client is not set\n# CONFIG_PACKAGE_krb5-libs is not set\n# CONFIG_PACKAGE_krb5-server is not set\n# CONFIG_PACKAGE_krb5-server-extras is not set\nCONFIG_PACKAGE_libipset=y\n# CONFIG_PACKAGE_libndp is not set\n# CONFIG_PACKAGE_linknx is not set\n# CONFIG_PACKAGE_lynx is not set\n# CONFIG_PACKAGE_mac-telnet-client is not set\n# CONFIG_PACKAGE_mac-telnet-discover is not set\n# CONFIG_PACKAGE_mac-telnet-ping is not set\n# CONFIG_PACKAGE_mac-telnet-server is not set\n# CONFIG_PACKAGE_map is not set\n# CONFIG_PACKAGE_mbusd is not set\n# CONFIG_PACKAGE_mdns-repeater is not set\n# CONFIG_PACKAGE_memcached is not set\n# CONFIG_PACKAGE_mii-tool is not set\n# CONFIG_PACKAGE_mikrotik-btest is not set\n# CONFIG_PACKAGE_mini_snmpd is not set\n# CONFIG_PACKAGE_minimalist-pcproxy is not set\n# CONFIG_PACKAGE_miredo is not set\n# CONFIG_PACKAGE_modemmanager is not set\n# CONFIG_PACKAGE_mosquitto-client-nossl is not set\n# CONFIG_PACKAGE_mosquitto-client-ssl is not set\n# CONFIG_PACKAGE_mosquitto-nossl is not set\n# CONFIG_PACKAGE_mosquitto-ssl is not set\n# CONFIG_PACKAGE_mrd6 is not set\n# CONFIG_PACKAGE_mstpd is not set\n# CONFIG_PACKAGE_mtr is not set\n# CONFIG_PACKAGE_nbd is not set\n# CONFIG_PACKAGE_nbd-server is not set\n# CONFIG_PACKAGE_ncp is not set\n# CONFIG_PACKAGE_ndppd is not set\n# CONFIG_PACKAGE_ndptool is not set\n# CONFIG_PACKAGE_nebula is not set\n# CONFIG_PACKAGE_nebula-cert is not set\n# CONFIG_PACKAGE_net-tools-route is not set\n# CONFIG_PACKAGE_netcat is not set\n# CONFIG_PACKAGE_netdiscover is not set\n# CONFIG_PACKAGE_netifyd is not set\nCONFIG_PACKAGE_netperf=y\n# CONFIG_PACKAGE_netsniff-ng is not set\n# CONFIG_PACKAGE_netstinky is not set\n# CONFIG_PACKAGE_nextdns is not set\n# CONFIG_PACKAGE_nfdump is not set\nCONFIG_PACKAGE_nlbwmon=y\n# CONFIG_PACKAGE_noping is not set\n# CONFIG_PACKAGE_nut is not set\n# CONFIG_PACKAGE_obfs4proxy is not set\nCONFIG_PACKAGE_odhcp6c=y\nCONFIG_PACKAGE_odhcp6c_ext_cer_id=0\n# CONFIG_PACKAGE_odhcpd is not set\nCONFIG_PACKAGE_odhcpd-ipv6only=y\n\n#\n# Configuration\n#\nCONFIG_PACKAGE_odhcpd_ipv6only_ext_cer_id=0\n# end of Configuration\n\n# CONFIG_PACKAGE_ola is not set\n# CONFIG_PACKAGE_omcproxy is not set\n# CONFIG_PACKAGE_onionshare-cli is not set\n# CONFIG_PACKAGE_ooniprobe is not set\n# CONFIG_PACKAGE_oor is not set\n# CONFIG_PACKAGE_open-iscsi is not set\n# CONFIG_PACKAGE_oping is not set\n# CONFIG_PACKAGE_ostiary is not set\n# CONFIG_PACKAGE_pagekitec is not set\n# CONFIG_PACKAGE_pen is not set\n# CONFIG_PACKAGE_phantap is not set\n# CONFIG_PACKAGE_pimbd is not set\n# CONFIG_PACKAGE_pingcheck is not set\n# CONFIG_PACKAGE_port-mirroring is not set\nCONFIG_PACKAGE_ppp=y\n# CONFIG_PACKAGE_ppp-mod-passwordfd is not set\n# CONFIG_PACKAGE_ppp-mod-pppoa is not set\nCONFIG_PACKAGE_ppp-mod-pppoe=y\n# CONFIG_PACKAGE_ppp-mod-pppol2tp is not set\n# CONFIG_PACKAGE_ppp-mod-pptp is not set\n# CONFIG_PACKAGE_ppp-mod-radius is not set\n# CONFIG_PACKAGE_ppp-multilink is not set\n# CONFIG_PACKAGE_pppdump is not set\n# CONFIG_PACKAGE_pppoe-discovery is not set\n# CONFIG_PACKAGE_pppossh is not set\n# CONFIG_PACKAGE_pppstats is not set\n# CONFIG_PACKAGE_proto-bonding is not set\n# CONFIG_PACKAGE_proxychains-ng is not set\n# CONFIG_PACKAGE_ptunnel-ng is not set\n# CONFIG_PACKAGE_radsecproxy is not set\n# CONFIG_PACKAGE_ratched is not set\n# CONFIG_PACKAGE_ratechecker is not set\n# CONFIG_PACKAGE_redsocks is not set\n# CONFIG_PACKAGE_remserial is not set\n# CONFIG_PACKAGE_restic-rest-server is not set\n# CONFIG_PACKAGE_rpcapd is not set\n# CONFIG_PACKAGE_rpcbind is not set\n# CONFIG_PACKAGE_rssileds is not set\n# CONFIG_PACKAGE_safe-search is not set\n# CONFIG_PACKAGE_samba4-admin is not set\n# CONFIG_PACKAGE_samba4-client is not set\nCONFIG_PACKAGE_samba4-libs=y\nCONFIG_PACKAGE_samba4-server=y\nCONFIG_SAMBA4_SERVER_WSDD2=y\nCONFIG_SAMBA4_SERVER_NETBIOS=y\nCONFIG_SAMBA4_SERVER_AVAHI=y\nCONFIG_SAMBA4_SERVER_VFS=y\n# CONFIG_SAMBA4_SERVER_VFSX is not set\n# CONFIG_SAMBA4_SERVER_AD_DC is not set\n# CONFIG_PACKAGE_samba4-utils is not set\n# CONFIG_PACKAGE_samplicator is not set\n# CONFIG_PACKAGE_scapy is not set\n# CONFIG_PACKAGE_sctp-tools is not set\n# CONFIG_PACKAGE_seafile-ccnet is not set\n# CONFIG_PACKAGE_seafile-seahub is not set\n# CONFIG_PACKAGE_seafile-server is not set\n# CONFIG_PACKAGE_seafile-server-fuse is not set\n# CONFIG_PACKAGE_ser2net is not set\n# CONFIG_PACKAGE_simple-adblock is not set\n# CONFIG_PACKAGE_smartdns is not set\n# CONFIG_PACKAGE_smbinfo is not set\n# CONFIG_PACKAGE_snmp-mibs is not set\n# CONFIG_PACKAGE_snmp-utils is not set\n# CONFIG_PACKAGE_snmpd is not set\n# CONFIG_PACKAGE_snmptrapd is not set\n# CONFIG_PACKAGE_socat is not set\n# CONFIG_PACKAGE_softflowd is not set\n# CONFIG_PACKAGE_soloscli is not set\nCONFIG_PACKAGE_speedtest-netperf=y\n# CONFIG_PACKAGE_spoofer is not set\n# CONFIG_PACKAGE_static-neighbor-reports is not set\n# CONFIG_PACKAGE_stunnel is not set\n# CONFIG_PACKAGE_switchdev-poller is not set\n# CONFIG_PACKAGE_tac_plus is not set\n# CONFIG_PACKAGE_tac_plus-pam is not set\n# CONFIG_PACKAGE_tayga is not set\nCONFIG_PACKAGE_tcpdump=y\n# CONFIG_PACKAGE_tcpdump-mini is not set\n# CONFIG_PACKAGE_tgt is not set\n# CONFIG_PACKAGE_tmate-ssh-server is not set\n# CONFIG_PACKAGE_tor is not set\n# CONFIG_PACKAGE_tor-basic is not set\n# CONFIG_PACKAGE_tor-fw-helper is not set\n# CONFIG_PACKAGE_trafficshaper is not set\n# CONFIG_PACKAGE_travelmate is not set\n# CONFIG_PACKAGE_u2pnpd is not set\n# CONFIG_PACKAGE_uacme is not set\nCONFIG_PACKAGE_uclient-fetch=y\n# CONFIG_PACKAGE_udhcpsnoop is not set\n# CONFIG_PACKAGE_udptunnel is not set\n# CONFIG_PACKAGE_udpxy is not set\n# CONFIG_PACKAGE_ulogd is not set\n# CONFIG_PACKAGE_umdns is not set\n# CONFIG_PACKAGE_uradvd is not set\n# CONFIG_PACKAGE_usbip is not set\n# CONFIG_PACKAGE_usteer is not set\n# CONFIG_PACKAGE_ustp is not set\n# CONFIG_PACKAGE_vallumd is not set\n# CONFIG_PACKAGE_vncrepeater is not set\n# CONFIG_PACKAGE_vnstat is not set\nCONFIG_PACKAGE_vnstat2=y\nCONFIG_PACKAGE_vnstati2=y\n# CONFIG_PACKAGE_vpn-policy-routing is not set\n# CONFIG_PACKAGE_vpnbypass is not set\n# CONFIG_PACKAGE_vxlan is not set\n# CONFIG_PACKAGE_wakeonlan is not set\n# CONFIG_PACKAGE_wg-installer-client is not set\n# CONFIG_PACKAGE_wg-installer-server is not set\n# CONFIG_PACKAGE_wpan-tools is not set\n# CONFIG_PACKAGE_wwan is not set\n# CONFIG_PACKAGE_xinetd is not set\n# CONFIG_PACKAGE_xray-core is not set\n# end of Network\n\n#\n# Sound\n#\n# CONFIG_PACKAGE_alsa-utils is not set\n# CONFIG_PACKAGE_alsa-utils-seq is not set\n# CONFIG_PACKAGE_alsa-utils-tests is not set\n# CONFIG_PACKAGE_aserver is not set\n# CONFIG_PACKAGE_espeak is not set\n# CONFIG_PACKAGE_faad2 is not set\n# CONFIG_PACKAGE_fdk-aac is not set\n# CONFIG_PACKAGE_ices is not set\n# CONFIG_PACKAGE_lame is not set\n# CONFIG_PACKAGE_lame-lib is not set\n# CONFIG_PACKAGE_liblo-utils is not set\n# CONFIG_PACKAGE_madplay is not set\n# CONFIG_PACKAGE_moc is not set\n# CONFIG_PACKAGE_mpc is not set\n# CONFIG_PACKAGE_mpd-avahi-service is not set\n# CONFIG_PACKAGE_mpd-full is not set\n# CONFIG_PACKAGE_mpd-mini is not set\n# CONFIG_PACKAGE_mpg123 is not set\n# CONFIG_PACKAGE_opus-tools is not set\n# CONFIG_PACKAGE_owntone is not set\n# CONFIG_PACKAGE_pianod is not set\n# CONFIG_PACKAGE_pianod-client is not set\n# CONFIG_PACKAGE_portaudio is not set\n# CONFIG_PACKAGE_pulseaudio-daemon is not set\n# CONFIG_PACKAGE_pulseaudio-daemon-avahi is not set\n# CONFIG_PACKAGE_shairplay is not set\n# CONFIG_PACKAGE_shairport-sync-mbedtls is not set\n# CONFIG_PACKAGE_shairport-sync-mini is not set\n# CONFIG_PACKAGE_shairport-sync-openssl is not set\n# CONFIG_PACKAGE_shine is not set\n# CONFIG_PACKAGE_sox is not set\n# CONFIG_PACKAGE_squeezelite-full is not set\n# CONFIG_PACKAGE_squeezelite-mini is not set\n# CONFIG_PACKAGE_svox is not set\n# CONFIG_PACKAGE_upmpdcli is not set\n# end of Sound\n\n#\n# Utilities\n#\n\n#\n# AppArmor\n#\n# CONFIG_PACKAGE_apparmor-profiles is not set\n# CONFIG_PACKAGE_apparmor-utils is not set\n# end of AppArmor\n\n#\n# BigClown\n#\n# CONFIG_PACKAGE_bigclown-control-tool is not set\n# CONFIG_PACKAGE_bigclown-firmware-tool is not set\n# CONFIG_PACKAGE_bigclown-gateway is not set\n# CONFIG_PACKAGE_bigclown-mqtt2influxdb is not set\n# end of BigClown\n\n#\n# Boot Loaders\n#\n# CONFIG_PACKAGE_fconfig is not set\nCONFIG_PACKAGE_uboot-envtools=y\n# end of Boot Loaders\n\n#\n# Compression\n#\n# CONFIG_PACKAGE_bsdtar is not set\n# CONFIG_PACKAGE_bsdtar-noopenssl is not set\n# CONFIG_PACKAGE_bzip2 is not set\n# CONFIG_PACKAGE_gzip is not set\n# CONFIG_PACKAGE_lz4 is not set\n# CONFIG_PACKAGE_pigz is not set\n# CONFIG_PACKAGE_unrar is not set\n# CONFIG_PACKAGE_unzip is not set\n# CONFIG_PACKAGE_xz-utils is not set\n# CONFIG_PACKAGE_zipcmp is not set\n# CONFIG_PACKAGE_zipmerge is not set\n# CONFIG_PACKAGE_ziptool is not set\n# CONFIG_PACKAGE_zstd is not set\n# end of Compression\n\n#\n# Database\n#\n# CONFIG_PACKAGE_mariadb-common is not set\n# CONFIG_PACKAGE_pgsql-cli is not set\n# CONFIG_PACKAGE_pgsql-cli-extra is not set\n# CONFIG_PACKAGE_pgsql-server is not set\n# CONFIG_PACKAGE_rrdcgi1 is not set\nCONFIG_PACKAGE_rrdtool1=y\n# CONFIG_PACKAGE_sqlite3-cli is not set\n# CONFIG_PACKAGE_unixodbc-tools is not set\n# end of Database\n\n#\n# Disc\n#\n# CONFIG_PACKAGE_autopart is not set\n# CONFIG_PACKAGE_blkdiscard is not set\nCONFIG_PACKAGE_blkid=y\n# CONFIG_PACKAGE_blockdev is not set\n# CONFIG_PACKAGE_cfdisk is not set\n# CONFIG_PACKAGE_cgdisk is not set\n# CONFIG_PACKAGE_eject is not set\nCONFIG_PACKAGE_fdisk=y\n# CONFIG_PACKAGE_findfs is not set\n# CONFIG_PACKAGE_fio is not set\n# CONFIG_PACKAGE_fixparts is not set\n# CONFIG_PACKAGE_gdisk is not set\n# CONFIG_PACKAGE_hd-idle is not set\n# CONFIG_PACKAGE_hdparm is not set\n# CONFIG_PACKAGE_lsblk is not set\n# CONFIG_PACKAGE_lvm2 is not set\n# CONFIG_PACKAGE_lvm2-selinux is not set\n# CONFIG_PACKAGE_mdadm is not set\n# CONFIG_PACKAGE_mtools is not set\n# CONFIG_PACKAGE_parted is not set\nCONFIG_PACKAGE_partx-utils=y\n# CONFIG_PACKAGE_sfdisk is not set\n# CONFIG_PACKAGE_sgdisk is not set\n# CONFIG_PACKAGE_uvol is not set\n# CONFIG_PACKAGE_wipefs is not set\n# end of Disc\n\n#\n# Editors\n#\n# CONFIG_PACKAGE_joe is not set\n# CONFIG_PACKAGE_joe-extras is not set\n# CONFIG_PACKAGE_jupp is not set\n# CONFIG_PACKAGE_mg is not set\nCONFIG_PACKAGE_nano=y\n# CONFIG_PACKAGE_vim is not set\n# CONFIG_PACKAGE_vim-full is not set\n# CONFIG_PACKAGE_vim-fuller is not set\n# CONFIG_PACKAGE_vim-help is not set\n# CONFIG_PACKAGE_vim-runtime is not set\n# CONFIG_PACKAGE_zile is not set\n# end of Editors\n\n#\n# Encryption\n#\n# CONFIG_PACKAGE_ccrypt is not set\n# CONFIG_PACKAGE_certtool is not set\n# CONFIG_PACKAGE_cryptsetup is not set\n# CONFIG_PACKAGE_cryptsetup-ssh is not set\n# CONFIG_PACKAGE_gnupg is not set\n# CONFIG_PACKAGE_gnupg2 is not set\n# CONFIG_PACKAGE_gnupg2-dirmngr is not set\n# CONFIG_PACKAGE_gnutls-utils is not set\n# CONFIG_PACKAGE_gpgv is not set\n# CONFIG_PACKAGE_gpgv2 is not set\n# CONFIG_PACKAGE_keyctl is not set\n# CONFIG_PACKAGE_keyutils is not set\n# CONFIG_PACKAGE_px5g-mbedtls is not set\n# CONFIG_PACKAGE_px5g-standalone is not set\nCONFIG_PACKAGE_px5g-wolfssl=y\n# CONFIG_PACKAGE_stoken is not set\n# end of Encryption\n\n#\n# Filesystem\n#\n# CONFIG_PACKAGE_acl is not set\n# CONFIG_PACKAGE_afuse is not set\n# CONFIG_PACKAGE_antfs-mount is not set\nCONFIG_PACKAGE_attr=y\n# CONFIG_PACKAGE_badblocks is not set\nCONFIG_PACKAGE_btrfs-progs=y\n# CONFIG_BTRFS_PROGS_ZSTD is not set\n# CONFIG_PACKAGE_chattr is not set\n# CONFIG_PACKAGE_debugfs is not set\n# CONFIG_PACKAGE_dosfstools is not set\n# CONFIG_PACKAGE_dumpe2fs is not set\n# CONFIG_PACKAGE_e2freefrag is not set\nCONFIG_PACKAGE_e2fsprogs=y\n# CONFIG_PACKAGE_e4crypt is not set\n# CONFIG_PACKAGE_exfat-fsck is not set\n# CONFIG_PACKAGE_exfat-mkfs is not set\n# CONFIG_PACKAGE_f2fs-tools is not set\n# CONFIG_PACKAGE_f2fs-tools-selinux is not set\n# CONFIG_PACKAGE_f2fsck is not set\n# CONFIG_PACKAGE_f2fsck-selinux is not set\n# CONFIG_PACKAGE_filefrag is not set\n# CONFIG_PACKAGE_fstrim is not set\n# CONFIG_PACKAGE_fuse-utils is not set\n# CONFIG_PACKAGE_fuse3-utils is not set\n# CONFIG_PACKAGE_hfsfsck is not set\n# CONFIG_PACKAGE_lsattr is not set\nCONFIG_PACKAGE_mkf2fs=y\n# CONFIG_PACKAGE_mkf2fs-selinux is not set\n# CONFIG_PACKAGE_mkhfs is not set\n# CONFIG_PACKAGE_ncdu is not set\n# CONFIG_PACKAGE_nfs-utils is not set\n# CONFIG_PACKAGE_nfs-utils-libs is not set\n# CONFIG_PACKAGE_ntfs-3g is not set\n# CONFIG_PACKAGE_ntfs-3g-low is not set\n# CONFIG_PACKAGE_ntfs-3g-utils is not set\n# CONFIG_PACKAGE_owfs is not set\n# CONFIG_PACKAGE_owshell is not set\n# CONFIG_PACKAGE_resize2fs is not set\n# CONFIG_PACKAGE_squashfs-tools-mksquashfs is not set\n# CONFIG_PACKAGE_squashfs-tools-unsquashfs is not set\n# CONFIG_PACKAGE_swap-utils is not set\n# CONFIG_PACKAGE_sysfsutils is not set\n# CONFIG_PACKAGE_tune2fs is not set\n# CONFIG_PACKAGE_xfs-admin is not set\n# CONFIG_PACKAGE_xfs-fsck is not set\n# CONFIG_PACKAGE_xfs-growfs is not set\n# CONFIG_PACKAGE_xfs-mkfs is not set\n# end of Filesystem\n\n#\n# Image Manipulation\n#\n# CONFIG_PACKAGE_libjpeg-turbo-utils is not set\n# CONFIG_PACKAGE_tiff-utils is not set\n# end of Image Manipulation\n\n#\n# Microcontroller programming\n#\n# CONFIG_PACKAGE_avrdude is not set\n# CONFIG_PACKAGE_dfu-programmer is not set\n# CONFIG_PACKAGE_stm32flash is not set\n# end of Microcontroller programming\n\n#\n# RTKLIB Suite\n#\n# CONFIG_PACKAGE_convbin is not set\n# CONFIG_PACKAGE_pos2kml is not set\n# CONFIG_PACKAGE_rnx2rtkp is not set\n# CONFIG_PACKAGE_rtkrcv is not set\n# CONFIG_PACKAGE_str2str is not set\n# end of RTKLIB Suite\n\n#\n# Shells\n#\n# CONFIG_PACKAGE_bash is not set\n# CONFIG_PACKAGE_fish is not set\n# CONFIG_PACKAGE_klish is not set\n# CONFIG_PACKAGE_mksh is not set\n# CONFIG_PACKAGE_tcsh is not set\n# CONFIG_PACKAGE_zsh is not set\n# end of Shells\n\n#\n# Telephony\n#\n# CONFIG_PACKAGE_dahdi-cfg is not set\n# CONFIG_PACKAGE_dahdi-monitor is not set\n# CONFIG_PACKAGE_gsm-utils is not set\n# CONFIG_PACKAGE_sipgrep is not set\n# CONFIG_PACKAGE_sngrep is not set\n# end of Telephony\n\n#\n# Terminal\n#\n# CONFIG_PACKAGE_agetty is not set\n# CONFIG_PACKAGE_dvtm is not set\n# CONFIG_PACKAGE_minicom is not set\n# CONFIG_PACKAGE_picocom is not set\n# CONFIG_PACKAGE_rtty-mbedtls is not set\n# CONFIG_PACKAGE_rtty-nossl is not set\n# CONFIG_PACKAGE_rtty-openssl is not set\n# CONFIG_PACKAGE_rtty-wolfssl is not set\n# CONFIG_PACKAGE_screen is not set\n# CONFIG_PACKAGE_script-utils is not set\n# CONFIG_PACKAGE_serialconsole is not set\n# CONFIG_PACKAGE_setterm is not set\n# CONFIG_PACKAGE_tio is not set\n# CONFIG_PACKAGE_tmux is not set\nCONFIG_PACKAGE_ttyd=y\n# CONFIG_PACKAGE_wall is not set\n# end of Terminal\n\n#\n# Virtualization\n#\n# end of Virtualization\n\n#\n# Zoneinfo\n#\n# CONFIG_PACKAGE_zoneinfo-africa is not set\n# CONFIG_PACKAGE_zoneinfo-all is not set\n# CONFIG_PACKAGE_zoneinfo-asia is not set\n# CONFIG_PACKAGE_zoneinfo-atlantic is not set\n# CONFIG_PACKAGE_zoneinfo-australia-nz is not set\n# CONFIG_PACKAGE_zoneinfo-core is not set\n# CONFIG_PACKAGE_zoneinfo-europe is not set\n# CONFIG_PACKAGE_zoneinfo-india is not set\n# CONFIG_PACKAGE_zoneinfo-northamerica is not set\n# CONFIG_PACKAGE_zoneinfo-pacific is not set\n# CONFIG_PACKAGE_zoneinfo-poles is not set\n# CONFIG_PACKAGE_zoneinfo-simple is not set\n# CONFIG_PACKAGE_zoneinfo-southamerica is not set\n# end of Zoneinfo\n\n#\n# libimobiledevice\n#\n# CONFIG_PACKAGE_idevicerestore is not set\n# CONFIG_PACKAGE_irecovery is not set\n# CONFIG_PACKAGE_libimobiledevice-utils is not set\n# CONFIG_PACKAGE_libusbmuxd-utils is not set\n# CONFIG_PACKAGE_plistutil is not set\n# CONFIG_PACKAGE_usbmuxd is not set\n# end of libimobiledevice\n\n#\n# libselinux tools\n#\n# CONFIG_PACKAGE_libselinux-avcstat is not set\n# CONFIG_PACKAGE_libselinux-compute_av is not set\n# CONFIG_PACKAGE_libselinux-compute_create is not set\n# CONFIG_PACKAGE_libselinux-compute_member is not set\n# CONFIG_PACKAGE_libselinux-compute_relabel is not set\n# CONFIG_PACKAGE_libselinux-getconlist is not set\n# CONFIG_PACKAGE_libselinux-getdefaultcon is not set\n# CONFIG_PACKAGE_libselinux-getenforce is not set\n# CONFIG_PACKAGE_libselinux-getfilecon is not set\n# CONFIG_PACKAGE_libselinux-getpidcon is not set\n# CONFIG_PACKAGE_libselinux-getsebool is not set\n# CONFIG_PACKAGE_libselinux-getseuser is not set\n# CONFIG_PACKAGE_libselinux-matchpathcon is not set\n# CONFIG_PACKAGE_libselinux-policyvers is not set\n# CONFIG_PACKAGE_libselinux-sefcontext_compile is not set\n# CONFIG_PACKAGE_libselinux-selabel_digest is not set\n# CONFIG_PACKAGE_libselinux-selabel_get_digests_all_partial_matches is not set\n# CONFIG_PACKAGE_libselinux-selabel_lookup is not set\n# CONFIG_PACKAGE_libselinux-selabel_lookup_best_match is not set\n# CONFIG_PACKAGE_libselinux-selabel_partial_match is not set\n# CONFIG_PACKAGE_libselinux-selinux_check_access is not set\n# CONFIG_PACKAGE_libselinux-selinux_check_securetty_context is not set\n# CONFIG_PACKAGE_libselinux-selinuxenabled is not set\n# CONFIG_PACKAGE_libselinux-selinuxexeccon is not set\n# CONFIG_PACKAGE_libselinux-setenforce is not set\n# CONFIG_PACKAGE_libselinux-setfilecon is not set\n# CONFIG_PACKAGE_libselinux-togglesebool is not set\n# CONFIG_PACKAGE_libselinux-validatetrans is not set\n# end of libselinux tools\n\n# CONFIG_PACKAGE_ack is not set\n# CONFIG_PACKAGE_acpid is not set\n# CONFIG_PACKAGE_adb is not set\n# CONFIG_PACKAGE_airos-dfs-reset is not set\n# CONFIG_PACKAGE_ap51-flash is not set\n# CONFIG_PACKAGE_apk is not set\n# CONFIG_PACKAGE_at is not set\n# CONFIG_PACKAGE_atheepmgr is not set\n# CONFIG_PACKAGE_audit is not set\n# CONFIG_PACKAGE_audit-utils is not set\n# CONFIG_PACKAGE_augeas is not set\n# CONFIG_PACKAGE_augeas-lenses is not set\n# CONFIG_PACKAGE_augeas-lenses-tests is not set\n# CONFIG_PACKAGE_bandwidthd is not set\n# CONFIG_PACKAGE_bandwidthd-pgsql is not set\n# CONFIG_PACKAGE_bandwidthd-php is not set\n# CONFIG_PACKAGE_bandwidthd-sqlite is not set\n# CONFIG_PACKAGE_banhostlist is not set\n# CONFIG_PACKAGE_bc is not set\n# CONFIG_PACKAGE_bluelog is not set\n# CONFIG_PACKAGE_bluez-daemon is not set\n# CONFIG_PACKAGE_bluez-utils is not set\n# CONFIG_PACKAGE_bluez-utils-extra is not set\n# CONFIG_PACKAGE_bluld is not set\n# CONFIG_PACKAGE_bonniexx is not set\n# CONFIG_PACKAGE_bossa is not set\n# CONFIG_PACKAGE_bottlerocket is not set\n# CONFIG_PACKAGE_bsdiff is not set\n# CONFIG_PACKAGE_bspatch is not set\n# CONFIG_PACKAGE_byobu is not set\n# CONFIG_PACKAGE_byobu-utils is not set\n# CONFIG_PACKAGE_cache-domains-mbedtls is not set\n# CONFIG_PACKAGE_cache-domains-openssl is not set\n# CONFIG_PACKAGE_cache-domains-wolfssl is not set\n# CONFIG_PACKAGE_cal is not set\n# CONFIG_PACKAGE_canutils is not set\n# CONFIG_PACKAGE_cgroup-tools is not set\n# CONFIG_PACKAGE_cgroupfs-mount is not set\n# CONFIG_PACKAGE_checkpolicy is not set\n# CONFIG_PACKAGE_checksec is not set\n# CONFIG_PACKAGE_checksec_automator is not set\n# CONFIG_PACKAGE_chkcon is not set\n# CONFIG_PACKAGE_clocate is not set\n# CONFIG_PACKAGE_cmdpad is not set\n# CONFIG_PACKAGE_cni is not set\n# CONFIG_PACKAGE_cni-plugins is not set\n# CONFIG_PACKAGE_cni-plugins-nft is not set\n# CONFIG_PACKAGE_coap-client is not set\nCONFIG_PACKAGE_collectd=y\n# CONFIG_PACKAGE_COLLECTD_ENCRYPTED_NETWORK is not set\n# CONFIG_PACKAGE_COLLECTD_DEBUG_OUTPUT_ENABLE is not set\n# CONFIG_PACKAGE_collectd-mod-apache is not set\n# CONFIG_PACKAGE_collectd-mod-apcups is not set\n# CONFIG_PACKAGE_collectd-mod-ascent is not set\n# CONFIG_PACKAGE_collectd-mod-bind is not set\n# CONFIG_PACKAGE_collectd-mod-chrony is not set\n# CONFIG_PACKAGE_collectd-mod-conntrack is not set\n# CONFIG_PACKAGE_collectd-mod-contextswitch is not set\nCONFIG_PACKAGE_collectd-mod-cpu=y\n# CONFIG_PACKAGE_collectd-mod-cpufreq is not set\n# CONFIG_PACKAGE_collectd-mod-csv is not set\n# CONFIG_PACKAGE_collectd-mod-curl is not set\n# CONFIG_PACKAGE_collectd-mod-df is not set\n# CONFIG_PACKAGE_collectd-mod-dhcpleases is not set\n# CONFIG_PACKAGE_collectd-mod-disk is not set\n# CONFIG_PACKAGE_collectd-mod-dns is not set\n# CONFIG_PACKAGE_collectd-mod-email is not set\n# CONFIG_PACKAGE_collectd-mod-entropy is not set\n# CONFIG_PACKAGE_collectd-mod-ethstat is not set\n# CONFIG_PACKAGE_collectd-mod-exec is not set\n# CONFIG_PACKAGE_collectd-mod-filecount is not set\n# CONFIG_PACKAGE_collectd-mod-fscache is not set\nCONFIG_PACKAGE_collectd-mod-interface=y\n# CONFIG_PACKAGE_collectd-mod-ipstatistics is not set\n# CONFIG_PACKAGE_collectd-mod-iptables is not set\n# CONFIG_PACKAGE_collectd-mod-irq is not set\nCONFIG_PACKAGE_collectd-mod-iwinfo=y\nCONFIG_PACKAGE_collectd-mod-load=y\n# CONFIG_PACKAGE_collectd-mod-logfile is not set\n# CONFIG_PACKAGE_collectd-mod-lua is not set\n# CONFIG_PACKAGE_collectd-mod-match-empty-counter is not set\n# CONFIG_PACKAGE_collectd-mod-match-hashed is not set\n# CONFIG_PACKAGE_collectd-mod-match-regex is not set\n# CONFIG_PACKAGE_collectd-mod-match-timediff is not set\n# CONFIG_PACKAGE_collectd-mod-match-value is not set\nCONFIG_PACKAGE_collectd-mod-memory=y\n# CONFIG_PACKAGE_collectd-mod-modbus is not set\n# CONFIG_PACKAGE_collectd-mod-mqtt is not set\n# CONFIG_PACKAGE_collectd-mod-mysql is not set\n# CONFIG_PACKAGE_collectd-mod-netlink is not set\nCONFIG_PACKAGE_collectd-mod-network=y\n# CONFIG_PACKAGE_collectd-mod-nginx is not set\n# CONFIG_PACKAGE_collectd-mod-ntpd is not set\n# CONFIG_PACKAGE_collectd-mod-olsrd is not set\n# CONFIG_PACKAGE_collectd-mod-openvpn is not set\n# CONFIG_PACKAGE_collectd-mod-ping is not set\n# CONFIG_PACKAGE_collectd-mod-postgresql is not set\n# CONFIG_PACKAGE_collectd-mod-powerdns is not set\n# CONFIG_PACKAGE_collectd-mod-processes is not set\n# CONFIG_PACKAGE_collectd-mod-protocols is not set\n# CONFIG_PACKAGE_collectd-mod-routeros is not set\nCONFIG_PACKAGE_collectd-mod-rrdtool=y\n# CONFIG_PACKAGE_collectd-mod-sensors is not set\n# CONFIG_PACKAGE_collectd-mod-smart is not set\n# CONFIG_PACKAGE_collectd-mod-snmp is not set\n# CONFIG_PACKAGE_collectd-mod-snmp6 is not set\n# CONFIG_PACKAGE_collectd-mod-sqm is not set\n# CONFIG_PACKAGE_collectd-mod-swap is not set\n# CONFIG_PACKAGE_collectd-mod-syslog is not set\n# CONFIG_PACKAGE_collectd-mod-table is not set\n# CONFIG_PACKAGE_collectd-mod-tail is not set\n# CONFIG_PACKAGE_collectd-mod-tail-csv is not set\n# CONFIG_PACKAGE_collectd-mod-tcpconns is not set\n# CONFIG_PACKAGE_collectd-mod-teamspeak2 is not set\n# CONFIG_PACKAGE_collectd-mod-ted is not set\n# CONFIG_PACKAGE_collectd-mod-thermal is not set\n# CONFIG_PACKAGE_collectd-mod-threshold is not set\n# CONFIG_PACKAGE_collectd-mod-unixsock is not set\n# CONFIG_PACKAGE_collectd-mod-uptime is not set\n# CONFIG_PACKAGE_collectd-mod-users is not set\n# CONFIG_PACKAGE_collectd-mod-vmem is not set\n# CONFIG_PACKAGE_collectd-mod-wireless is not set\n# CONFIG_PACKAGE_collectd-mod-write-graphite is not set\n# CONFIG_PACKAGE_collectd-mod-write-http is not set\n# CONFIG_PACKAGE_conmon is not set\nCONFIG_PACKAGE_containerd=y\n# CONFIG_PACKAGE_coremark is not set\nCONFIG_PACKAGE_coreutils=y\n# CONFIG_PACKAGE_coreutils-b2sum is not set\n# CONFIG_PACKAGE_coreutils-base32 is not set\n# CONFIG_PACKAGE_coreutils-base64 is not set\n# CONFIG_PACKAGE_coreutils-basename is not set\n# CONFIG_PACKAGE_coreutils-basenc is not set\n# CONFIG_PACKAGE_coreutils-cat is not set\n# CONFIG_PACKAGE_coreutils-chcon is not set\n# CONFIG_PACKAGE_coreutils-chgrp is not set\n# CONFIG_PACKAGE_coreutils-chmod is not set\n# CONFIG_PACKAGE_coreutils-chown is not set\n# CONFIG_PACKAGE_coreutils-chroot is not set\n# CONFIG_PACKAGE_coreutils-cksum is not set\n# CONFIG_PACKAGE_coreutils-comm is not set\n# CONFIG_PACKAGE_coreutils-cp is not set\n# CONFIG_PACKAGE_coreutils-csplit is not set\n# CONFIG_PACKAGE_coreutils-cut is not set\n# CONFIG_PACKAGE_coreutils-date is not set\n# CONFIG_PACKAGE_coreutils-dd is not set\n# CONFIG_PACKAGE_coreutils-df is not set\n# CONFIG_PACKAGE_coreutils-dir is not set\n# CONFIG_PACKAGE_coreutils-dircolors is not set\n# CONFIG_PACKAGE_coreutils-dirname is not set\n# CONFIG_PACKAGE_coreutils-du is not set\n# CONFIG_PACKAGE_coreutils-echo is not set\n# CONFIG_PACKAGE_coreutils-env is not set\n# CONFIG_PACKAGE_coreutils-expand is not set\n# CONFIG_PACKAGE_coreutils-expr is not set\n# CONFIG_PACKAGE_coreutils-factor is not set\n# CONFIG_PACKAGE_coreutils-false is not set\n# CONFIG_PACKAGE_coreutils-fmt is not set\n# CONFIG_PACKAGE_coreutils-fold is not set\n# CONFIG_PACKAGE_coreutils-groups is not set\n# CONFIG_PACKAGE_coreutils-head is not set\n# CONFIG_PACKAGE_coreutils-hostid is not set\n# CONFIG_PACKAGE_coreutils-id is not set\n# CONFIG_PACKAGE_coreutils-install is not set\n# CONFIG_PACKAGE_coreutils-join is not set\n# CONFIG_PACKAGE_coreutils-kill is not set\n# CONFIG_PACKAGE_coreutils-link is not set\n# CONFIG_PACKAGE_coreutils-ln is not set\n# CONFIG_PACKAGE_coreutils-logname is not set\n# CONFIG_PACKAGE_coreutils-ls is not set\n# CONFIG_PACKAGE_coreutils-md5sum is not set\n# CONFIG_PACKAGE_coreutils-mkdir is not set\n# CONFIG_PACKAGE_coreutils-mkfifo is not set\n# CONFIG_PACKAGE_coreutils-mknod is not set\n# CONFIG_PACKAGE_coreutils-mktemp is not set\n# CONFIG_PACKAGE_coreutils-mv is not set\n# CONFIG_PACKAGE_coreutils-nice is not set\n# CONFIG_PACKAGE_coreutils-nl is not set\n# CONFIG_PACKAGE_coreutils-nohup is not set\n# CONFIG_PACKAGE_coreutils-nproc is not set\n# CONFIG_PACKAGE_coreutils-numfmt is not set\n# CONFIG_PACKAGE_coreutils-od is not set\n# CONFIG_PACKAGE_coreutils-paste is not set\n# CONFIG_PACKAGE_coreutils-pathchk is not set\n# CONFIG_PACKAGE_coreutils-pinky is not set\n# CONFIG_PACKAGE_coreutils-pr is not set\n# CONFIG_PACKAGE_coreutils-printenv is not set\n# CONFIG_PACKAGE_coreutils-printf is not set\n# CONFIG_PACKAGE_coreutils-ptx is not set\n# CONFIG_PACKAGE_coreutils-pwd is not set\n# CONFIG_PACKAGE_coreutils-readlink is not set\n# CONFIG_PACKAGE_coreutils-realpath is not set\n# CONFIG_PACKAGE_coreutils-rm is not set\n# CONFIG_PACKAGE_coreutils-rmdir is not set\n# CONFIG_PACKAGE_coreutils-runcon is not set\n# CONFIG_PACKAGE_coreutils-seq is not set\n# CONFIG_PACKAGE_coreutils-sha1sum is not set\n# CONFIG_PACKAGE_coreutils-sha224sum is not set\n# CONFIG_PACKAGE_coreutils-sha256sum is not set\n# CONFIG_PACKAGE_coreutils-sha384sum is not set\n# CONFIG_PACKAGE_coreutils-sha512sum is not set\n# CONFIG_PACKAGE_coreutils-shred is not set\n# CONFIG_PACKAGE_coreutils-shuf is not set\n# CONFIG_PACKAGE_coreutils-sleep is not set\nCONFIG_PACKAGE_coreutils-sort=y\n# CONFIG_PACKAGE_coreutils-split is not set\n# CONFIG_PACKAGE_coreutils-stat is not set\n# CONFIG_PACKAGE_coreutils-stdbuf is not set\n# CONFIG_PACKAGE_coreutils-stty is not set\n# CONFIG_PACKAGE_coreutils-sum is not set\n# CONFIG_PACKAGE_coreutils-sync is not set\n# CONFIG_PACKAGE_coreutils-tac is not set\n# CONFIG_PACKAGE_coreutils-tail is not set\n# CONFIG_PACKAGE_coreutils-tee is not set\n# CONFIG_PACKAGE_coreutils-test is not set\n# CONFIG_PACKAGE_coreutils-timeout is not set\n# CONFIG_PACKAGE_coreutils-touch is not set\n# CONFIG_PACKAGE_coreutils-tr is not set\n# CONFIG_PACKAGE_coreutils-true is not set\n# CONFIG_PACKAGE_coreutils-truncate is not set\n# CONFIG_PACKAGE_coreutils-tsort is not set\n# CONFIG_PACKAGE_coreutils-tty is not set\n# CONFIG_PACKAGE_coreutils-uname is not set\n# CONFIG_PACKAGE_coreutils-unexpand is not set\n# CONFIG_PACKAGE_coreutils-uniq is not set\n# CONFIG_PACKAGE_coreutils-unlink is not set\n# CONFIG_PACKAGE_coreutils-uptime is not set\n# CONFIG_PACKAGE_coreutils-users is not set\n# CONFIG_PACKAGE_coreutils-vdir is not set\n# CONFIG_PACKAGE_coreutils-wc is not set\n# CONFIG_PACKAGE_coreutils-who is not set\n# CONFIG_PACKAGE_coreutils-whoami is not set\n# CONFIG_PACKAGE_coreutils-yes is not set\n# CONFIG_PACKAGE_crconf is not set\n# CONFIG_PACKAGE_crelay is not set\n# CONFIG_PACKAGE_crun is not set\n# CONFIG_PACKAGE_csstidy is not set\n# CONFIG_PACKAGE_ct-bugcheck is not set\n# CONFIG_PACKAGE_ctop is not set\nCONFIG_PACKAGE_dbus=y\n# CONFIG_PACKAGE_dbus-utils is not set\n# CONFIG_PACKAGE_device-observatory is not set\n# CONFIG_PACKAGE_dfu-util is not set\n# CONFIG_PACKAGE_digitemp is not set\n# CONFIG_PACKAGE_digitemp-usb is not set\nCONFIG_PACKAGE_dmesg=y\nCONFIG_PACKAGE_docker=y\n# CONFIG_PACKAGE_docker-compose is not set\nCONFIG_PACKAGE_dockerd=y\n# CONFIG_DOCKER_CGROUP_OPTIONS is not set\n# CONFIG_DOCKER_OPTIONAL_FEATURES is not set\n\n#\n# Network\n#\n# CONFIG_DOCKER_NET_OVERLAY is not set\n# CONFIG_DOCKER_NET_MACVLAN is not set\n# CONFIG_DOCKER_NET_TFTP is not set\n# end of Network\n\n#\n# Storage\n#\n# CONFIG_DOCKER_STO_EXT4 is not set\n# CONFIG_DOCKER_STO_BTRFS is not set\n# end of Storage\n\n# CONFIG_PACKAGE_domoticz is not set\n# CONFIG_PACKAGE_dropbearconvert is not set\n# CONFIG_PACKAGE_dtc is not set\n# CONFIG_PACKAGE_dumb-init is not set\n# CONFIG_PACKAGE_dump1090 is not set\n# CONFIG_PACKAGE_ecdsautils is not set\n# CONFIG_PACKAGE_elektra-kdb is not set\n# CONFIG_PACKAGE_evtest is not set\n# CONFIG_PACKAGE_extract is not set\n# CONFIG_PACKAGE_fbtest is not set\n# CONFIG_PACKAGE_fdt-utils is not set\n# CONFIG_PACKAGE_file is not set\n# CONFIG_PACKAGE_findutils is not set\n# CONFIG_PACKAGE_findutils-find is not set\n# CONFIG_PACKAGE_findutils-locate is not set\n# CONFIG_PACKAGE_findutils-xargs is not set\n# CONFIG_PACKAGE_flashrom is not set\n# CONFIG_PACKAGE_flashrom-pci is not set\n# CONFIG_PACKAGE_flashrom-spi is not set\n# CONFIG_PACKAGE_flashrom-usb is not set\n# CONFIG_PACKAGE_flent-tools is not set\n# CONFIG_PACKAGE_flock is not set\n# CONFIG_PACKAGE_fritz-caldata is not set\n# CONFIG_PACKAGE_fritz-tffs is not set\n# CONFIG_PACKAGE_fritz-tffs-nand is not set\n# CONFIG_PACKAGE_ftdi_eeprom is not set\n# CONFIG_PACKAGE_fuse-overlayfs is not set\n# CONFIG_PACKAGE_gammu is not set\n# CONFIG_PACKAGE_gawk is not set\n# CONFIG_PACKAGE_gddrescue is not set\n# CONFIG_PACKAGE_getopt is not set\n# CONFIG_PACKAGE_giflib-utils is not set\n# CONFIG_PACKAGE_gkermit is not set\n# CONFIG_PACKAGE_gl-puli-mcu is not set\n# CONFIG_PACKAGE_gnuplot is not set\n# CONFIG_PACKAGE_gpioctl-sysfs is not set\n# CONFIG_PACKAGE_gpiod-tools is not set\n# CONFIG_PACKAGE_gpsd is not set\n# CONFIG_PACKAGE_gpsd-clients is not set\n# CONFIG_PACKAGE_gpsd-utils is not set\n# CONFIG_PACKAGE_grep is not set\n# CONFIG_PACKAGE_hamlib is not set\n# CONFIG_PACKAGE_haserl is not set\n# CONFIG_PACKAGE_hashdeep is not set\n# CONFIG_PACKAGE_haveged is not set\n# CONFIG_PACKAGE_hplip-common is not set\n# CONFIG_PACKAGE_hplip-sane is not set\n# CONFIG_PACKAGE_hub-ctrl is not set\n# CONFIG_PACKAGE_hwclock is not set\n# CONFIG_PACKAGE_hwinfo is not set\n# CONFIG_PACKAGE_hwloc-utils is not set\n# CONFIG_PACKAGE_i2c-tools is not set\n# CONFIG_PACKAGE_iconv is not set\n# CONFIG_PACKAGE_iio-utils is not set\n# CONFIG_PACKAGE_inotifywait is not set\n# CONFIG_PACKAGE_inotifywatch is not set\n# CONFIG_PACKAGE_io is not set\n# CONFIG_PACKAGE_ipfs-http-client-tests is not set\n# CONFIG_PACKAGE_irqbalance is not set\n# CONFIG_PACKAGE_iwcap is not set\nCONFIG_PACKAGE_iwinfo=y\n# CONFIG_PACKAGE_jq is not set\nCONFIG_PACKAGE_jshn=y\n# CONFIG_PACKAGE_kmod is not set\n# CONFIG_PACKAGE_lcd4linux-custom is not set\n# CONFIG_PACKAGE_lcdproc-clients is not set\n# CONFIG_PACKAGE_lcdproc-drivers is not set\n# CONFIG_PACKAGE_lcdproc-server is not set\n# CONFIG_PACKAGE_less is not set\nCONFIG_PACKAGE_libjson-script=y\nCONFIG_PACKAGE_libnetwork=y\n# CONFIG_PACKAGE_libucode is not set\n# CONFIG_PACKAGE_libxml2-utils is not set\n# CONFIG_PACKAGE_lm-sensors is not set\n# CONFIG_PACKAGE_lm-sensors-detect is not set\n# CONFIG_PACKAGE_logger is not set\n# CONFIG_PACKAGE_logrotate is not set\n# CONFIG_PACKAGE_lolcat is not set\n# CONFIG_PACKAGE_look is not set\n# CONFIG_PACKAGE_losetup is not set\n# CONFIG_PACKAGE_lrzsz is not set\n# CONFIG_PACKAGE_lscpu is not set\n# CONFIG_PACKAGE_lsof is not set\n# CONFIG_PACKAGE_lxc is not set\n# CONFIG_PACKAGE_maccalc is not set\n# CONFIG_PACKAGE_macchanger is not set\n# CONFIG_PACKAGE_mandoc is not set\n# CONFIG_PACKAGE_mbedtls-util is not set\n# CONFIG_PACKAGE_mbim-utils is not set\n# CONFIG_PACKAGE_mbtools is not set\n# CONFIG_PACKAGE_mc is not set\n# CONFIG_PACKAGE_mc-skins is not set\n# CONFIG_PACKAGE_mcookie is not set\n# CONFIG_PACKAGE_mdio-tools is not set\n# CONFIG_PACKAGE_micrond is not set\n# CONFIG_PACKAGE_miniflux is not set\n# CONFIG_PACKAGE_mmc-utils is not set\n# CONFIG_PACKAGE_more is not set\n# CONFIG_PACKAGE_moreutils is not set\n# CONFIG_PACKAGE_mosh-client is not set\n# CONFIG_PACKAGE_mosh-server is not set\nCONFIG_PACKAGE_mount-utils=y\n# CONFIG_PACKAGE_mpack is not set\n# CONFIG_PACKAGE_mt-st is not set\n# CONFIG_PACKAGE_namei is not set\n# CONFIG_PACKAGE_naywatch is not set\n# CONFIG_PACKAGE_netopeer2-cli is not set\n# CONFIG_PACKAGE_netopeer2-server is not set\n# CONFIG_PACKAGE_netwhere is not set\n# CONFIG_PACKAGE_nnn is not set\n# CONFIG_PACKAGE_nsenter is not set\n# CONFIG_PACKAGE_nss-utils is not set\n# CONFIG_PACKAGE_oath-toolkit is not set\n# CONFIG_PACKAGE_oci-runtime-tool is not set\n# CONFIG_PACKAGE_open-plc-utils is not set\n# CONFIG_PACKAGE_open2300 is not set\n# CONFIG_PACKAGE_openobex is not set\n# CONFIG_PACKAGE_openobex-apps is not set\n# CONFIG_PACKAGE_openocd is not set\n# CONFIG_PACKAGE_opensc-utils is not set\nCONFIG_PACKAGE_openssl-util=y\n# CONFIG_PACKAGE_openzwave is not set\n# CONFIG_PACKAGE_openzwave-config is not set\n# CONFIG_PACKAGE_owipcalc is not set\n# CONFIG_PACKAGE_pciids is not set\n# CONFIG_PACKAGE_pciutils is not set\n# CONFIG_PACKAGE_pcsc-tools is not set\n# CONFIG_PACKAGE_pcscd is not set\n# CONFIG_PACKAGE_podman is not set\n# CONFIG_PACKAGE_podman-selinux is not set\n# CONFIG_PACKAGE_policycoreutils is not set\n# CONFIG_PACKAGE_powertop is not set\n# CONFIG_PACKAGE_pps-tools is not set\n# CONFIG_PACKAGE_prlimit is not set\n# CONFIG_PACKAGE_procps-ng is not set\n# CONFIG_PACKAGE_progress is not set\n# CONFIG_PACKAGE_prometheus is not set\n# CONFIG_PACKAGE_prometheus-node-exporter-lua is not set\n# CONFIG_PACKAGE_prometheus-statsd-exporter is not set\n# CONFIG_PACKAGE_pservice is not set\n# CONFIG_PACKAGE_psmisc is not set\n# CONFIG_PACKAGE_pv is not set\n# CONFIG_PACKAGE_qmi-utils is not set\n# CONFIG_PACKAGE_qrencode is not set\n# CONFIG_PACKAGE_quota is not set\n# CONFIG_PACKAGE_ravpower-mcu is not set\n# CONFIG_PACKAGE_readsb is not set\n# CONFIG_PACKAGE_relayctl is not set\n# CONFIG_PACKAGE_rename is not set\n# CONFIG_PACKAGE_reptyr is not set\n# CONFIG_PACKAGE_restic is not set\n# CONFIG_PACKAGE_rng-tools is not set\n# CONFIG_PACKAGE_rtl-ais is not set\n# CONFIG_PACKAGE_rtl-sdr is not set\n# CONFIG_PACKAGE_rtl_433 is not set\nCONFIG_PACKAGE_runc=y\n# CONFIG_PACKAGE_sane-backends is not set\n# CONFIG_PACKAGE_sane-daemon is not set\n# CONFIG_PACKAGE_sane-frontends is not set\n# CONFIG_PACKAGE_secilc is not set\n# CONFIG_PACKAGE_sed is not set\n# CONFIG_PACKAGE_selinux-audit2allow is not set\n# CONFIG_PACKAGE_selinux-chcat is not set\n# CONFIG_PACKAGE_selinux-semanage is not set\n# CONFIG_PACKAGE_semodule-utils is not set\n# CONFIG_PACKAGE_serdisplib-tools is not set\n# CONFIG_PACKAGE_setools is not set\n# CONFIG_PACKAGE_setserial is not set\n# CONFIG_PACKAGE_shadow-utils is not set\n# CONFIG_PACKAGE_sipcalc is not set\n# CONFIG_PACKAGE_sispmctl is not set\n# CONFIG_PACKAGE_slide-switch is not set\n# CONFIG_PACKAGE_smartd is not set\n# CONFIG_PACKAGE_smartd-mail is not set\n# CONFIG_PACKAGE_smartmontools is not set\n# CONFIG_PACKAGE_smartmontools-drivedb is not set\n# CONFIG_PACKAGE_smstools3 is not set\n# CONFIG_PACKAGE_sockread is not set\n# CONFIG_PACKAGE_spi-tools is not set\n# CONFIG_PACKAGE_spidev-test is not set\n# CONFIG_PACKAGE_ssdeep is not set\n# CONFIG_PACKAGE_sshpass is not set\n# CONFIG_PACKAGE_strace is not set\nCONFIG_STRACE_NONE=y\n# CONFIG_STRACE_LIBDW is not set\n# CONFIG_STRACE_LIBUNWIND is not set\n# CONFIG_PACKAGE_stress is not set\n# CONFIG_PACKAGE_stress-ng is not set\n# CONFIG_PACKAGE_sumo is not set\n# CONFIG_PACKAGE_syncthing is not set\n# CONFIG_PACKAGE_sysrepo is not set\n# CONFIG_PACKAGE_sysrepocfg is not set\n# CONFIG_PACKAGE_sysrepoctl is not set\n# CONFIG_PACKAGE_sysstat is not set\n# CONFIG_PACKAGE_tar is not set\n# CONFIG_PACKAGE_taskwarrior is not set\n# CONFIG_PACKAGE_telegraf is not set\n# CONFIG_PACKAGE_telegraf-full is not set\n# CONFIG_PACKAGE_telldus-core is not set\n# CONFIG_PACKAGE_temperusb is not set\n# CONFIG_PACKAGE_tesseract is not set\nCONFIG_PACKAGE_tini=y\n# CONFIG_PACKAGE_tracertools is not set\n# CONFIG_PACKAGE_tree is not set\n# CONFIG_PACKAGE_triggerhappy is not set\n# CONFIG_PACKAGE_ucode is not set\n# CONFIG_PACKAGE_udns-dnsget is not set\n# CONFIG_PACKAGE_udns-ex-rdns is not set\n# CONFIG_PACKAGE_udns-rblcheck is not set\n# CONFIG_PACKAGE_ugps is not set\n# CONFIG_PACKAGE_uhubctl is not set\n# CONFIG_PACKAGE_uledd is not set\n# CONFIG_PACKAGE_unshare is not set\n# CONFIG_PACKAGE_usb-modeswitch is not set\n# CONFIG_PACKAGE_usbids is not set\n# CONFIG_PACKAGE_usbutils is not set\n# CONFIG_PACKAGE_uuidd is not set\n# CONFIG_PACKAGE_uuidgen is not set\n# CONFIG_PACKAGE_uvcdynctrl is not set\n# CONFIG_PACKAGE_v4l-utils is not set\n# CONFIG_PACKAGE_view1090 is not set\n# CONFIG_PACKAGE_viewadsb is not set\nCONFIG_PACKAGE_watchcat=y\n# CONFIG_PACKAGE_whereis is not set\n# CONFIG_PACKAGE_which is not set\n# CONFIG_PACKAGE_whiptail is not set\n# CONFIG_PACKAGE_whois is not set\n# CONFIG_PACKAGE_wifitoggle is not set\n# CONFIG_PACKAGE_wipe is not set\n# CONFIG_PACKAGE_xsltproc is not set\n# CONFIG_PACKAGE_xxd is not set\n# CONFIG_PACKAGE_yanglint is not set\n# CONFIG_PACKAGE_yara is not set\n# CONFIG_PACKAGE_ykclient is not set\n# CONFIG_PACKAGE_ykpers is not set\n# CONFIG_PACKAGE_yq is not set\n# end of Utilities\n\n#\n# Xorg\n#\n\n#\n# Font-Utils\n#\n# CONFIG_PACKAGE_fontconfig is not set\n# end of Font-Utils\n# end of Xorg\n"
  },
  {
    "path": "configs/OrangePi_R1_Plus_defconfig",
    "content": "#\n# Automatically generated file; DO NOT EDIT.\n# OpenWrt Configuration\n#\nCONFIG_MODULES=y\nCONFIG_HAVE_DOT_CONFIG=y\nCONFIG_HOST_OS_LINUX=y\n# CONFIG_HOST_OS_MACOS is not set\n# CONFIG_TARGET_sunxi is not set\n# CONFIG_TARGET_apm821xx is not set\n# CONFIG_TARGET_ath25 is not set\n# CONFIG_TARGET_ath79 is not set\n# CONFIG_TARGET_bcm27xx is not set\n# CONFIG_TARGET_bcm53xx is not set\n# CONFIG_TARGET_bcm47xx is not set\n# CONFIG_TARGET_bcm4908 is not set\n# CONFIG_TARGET_bcm63xx is not set\n# CONFIG_TARGET_bmips is not set\n# CONFIG_TARGET_octeon is not set\n# CONFIG_TARGET_gemini is not set\n# CONFIG_TARGET_mpc85xx is not set\n# CONFIG_TARGET_mxs is not set\n# CONFIG_TARGET_lantiq is not set\n# CONFIG_TARGET_malta is not set\n# CONFIG_TARGET_pistachio is not set\n# CONFIG_TARGET_mvebu is not set\n# CONFIG_TARGET_kirkwood is not set\n# CONFIG_TARGET_mediatek is not set\n# CONFIG_TARGET_ramips is not set\n# CONFIG_TARGET_at91 is not set\n# CONFIG_TARGET_tegra is not set\n# CONFIG_TARGET_layerscape is not set\n# CONFIG_TARGET_imx is not set\n# CONFIG_TARGET_octeontx is not set\n# CONFIG_TARGET_oxnas is not set\n# CONFIG_TARGET_armvirt is not set\n# CONFIG_TARGET_ipq40xx is not set\n# CONFIG_TARGET_ipq806x is not set\n# CONFIG_TARGET_ipq807x is not set\n# CONFIG_TARGET_realtek is not set\nCONFIG_TARGET_rockchip=y\n# CONFIG_TARGET_arc770 is not set\n# CONFIG_TARGET_archs38 is not set\n# CONFIG_TARGET_omap is not set\n# CONFIG_TARGET_uml is not set\n# CONFIG_TARGET_zynq is not set\n# CONFIG_TARGET_x86 is not set\nCONFIG_TARGET_rockchip_armv8=y\n# CONFIG_TARGET_MULTI_PROFILE is not set\nCONFIG_TARGET_rockchip_armv8_DEVICE_xunlong_orangepi-r1-plus=y\n# CONFIG_TARGET_rockchip_armv8_DEVICE_xunlong_orangepi-r1-plus-lts is not set\n# CONFIG_TARGET_rockchip_armv8_DEVICE_friendlyarm_nanopi-r2s is not set\n# CONFIG_TARGET_rockchip_armv8_DEVICE_friendlyarm_nanopi-r4s is not set\n# CONFIG_TARGET_rockchip_armv8_DEVICE_pine64_rockpro64 is not set\n# CONFIG_TARGET_rockchip_armv8_DEVICE_radxa_rock-pi-4a is not set\nCONFIG_HAS_SUBTARGETS=y\nCONFIG_HAS_DEVICES=y\nCONFIG_TARGET_BOARD=\"rockchip\"\nCONFIG_TARGET_SUBTARGET=\"armv8\"\nCONFIG_TARGET_PROFILE=\"DEVICE_xunlong_orangepi-r1-plus\"\nCONFIG_TARGET_ARCH_PACKAGES=\"aarch64_generic\"\nCONFIG_DEFAULT_TARGET_OPTIMIZATION=\"-Os -pipe -mcpu=generic\"\nCONFIG_CPU_TYPE=\"generic\"\nCONFIG_LINUX_5_10=y\nCONFIG_DEFAULT_base-files=y\nCONFIG_DEFAULT_busybox=y\nCONFIG_DEFAULT_ca-bundle=y\nCONFIG_DEFAULT_dnsmasq=y\nCONFIG_DEFAULT_dropbear=y\nCONFIG_DEFAULT_e2fsprogs=y\nCONFIG_DEFAULT_firewall=y\nCONFIG_DEFAULT_fstools=y\nCONFIG_DEFAULT_ip6tables=y\nCONFIG_DEFAULT_iptables=y\nCONFIG_DEFAULT_kmod-gpio-button-hotplug=y\nCONFIG_DEFAULT_kmod-ipt-offload=y\nCONFIG_DEFAULT_kmod-usb-net-rtl8152=y\nCONFIG_DEFAULT_libc=y\nCONFIG_DEFAULT_libgcc=y\nCONFIG_DEFAULT_libustream-wolfssl=y\nCONFIG_DEFAULT_logd=y\nCONFIG_DEFAULT_mkf2fs=y\nCONFIG_DEFAULT_mtd=y\nCONFIG_DEFAULT_netifd=y\nCONFIG_DEFAULT_odhcp6c=y\nCONFIG_DEFAULT_odhcpd-ipv6only=y\nCONFIG_DEFAULT_opkg=y\nCONFIG_DEFAULT_partx-utils=y\nCONFIG_DEFAULT_ppp=y\nCONFIG_DEFAULT_ppp-mod-pppoe=y\nCONFIG_DEFAULT_procd=y\nCONFIG_DEFAULT_procd-ujail=y\nCONFIG_DEFAULT_uboot-envtools=y\nCONFIG_DEFAULT_uci=y\nCONFIG_DEFAULT_uclient-fetch=y\nCONFIG_DEFAULT_urandom-seed=y\nCONFIG_DEFAULT_urngd=y\nCONFIG_HAS_FPU=y\nCONFIG_AUDIO_SUPPORT=y\nCONFIG_GPIO_SUPPORT=y\nCONFIG_PCI_SUPPORT=y\nCONFIG_PCIE_SUPPORT=y\nCONFIG_USB_SUPPORT=y\nCONFIG_USB_GADGET_SUPPORT=y\nCONFIG_RTC_SUPPORT=y\nCONFIG_USES_DEVICETREE=y\nCONFIG_USES_SQUASHFS=y\nCONFIG_USES_EXT4=y\nCONFIG_ARCH_64BIT=y\nCONFIG_USES_ROOTFS_PART=y\nCONFIG_USES_BOOT_PART=y\nCONFIG_aarch64=y\nCONFIG_ARCH=\"aarch64\"\n\n#\n# Target Images\n#\n# CONFIG_TARGET_ROOTFS_INITRAMFS is not set\nCONFIG_EXTERNAL_CPIO=\"\"\n\n#\n# Root filesystem archives\n#\n# CONFIG_TARGET_ROOTFS_CPIOGZ is not set\n# CONFIG_TARGET_ROOTFS_TARGZ is not set\n\n#\n# Root filesystem images\n#\nCONFIG_TARGET_ROOTFS_EXT4FS=y\nCONFIG_TARGET_EXT4_RESERVED_PCT=0\nCONFIG_TARGET_EXT4_BLOCKSIZE_4K=y\n# CONFIG_TARGET_EXT4_BLOCKSIZE_2K is not set\n# CONFIG_TARGET_EXT4_BLOCKSIZE_1K is not set\nCONFIG_TARGET_EXT4_BLOCKSIZE=4096\n# CONFIG_TARGET_EXT4_JOURNAL is not set\nCONFIG_TARGET_ROOTFS_SQUASHFS=y\nCONFIG_TARGET_SQUASHFS_BLOCK_SIZE=256\nCONFIG_TARGET_UBIFS_FREE_SPACE_FIXUP=y\nCONFIG_TARGET_UBIFS_JOURNAL_SIZE=\"\"\nCONFIG_TARGET_IMAGES_GZIP=y\n\n#\n# Image Options\n#\nCONFIG_TARGET_KERNEL_PARTSIZE=16\nCONFIG_TARGET_ROOTFS_PARTSIZE=512\n# CONFIG_TARGET_ROOTFS_PERSIST_VAR is not set\n# end of Target Images\n\n# CONFIG_EXPERIMENTAL is not set\n\n#\n# Global build settings\n#\n# CONFIG_JSON_OVERVIEW_IMAGE_INFO is not set\n# CONFIG_ALL_NONSHARED is not set\n# CONFIG_ALL_KMODS is not set\n# CONFIG_ALL is not set\n# CONFIG_BUILDBOT is not set\nCONFIG_SIGNED_PACKAGES=y\nCONFIG_SIGNATURE_CHECK=y\n\n#\n# General build options\n#\nCONFIG_DISPLAY_SUPPORT=y\n# CONFIG_BUILD_PATENTED is not set\n# CONFIG_BUILD_NLS is not set\nCONFIG_SHADOW_PASSWORDS=y\n# CONFIG_CLEAN_IPKG is not set\n# CONFIG_IPK_FILES_CHECKSUMS is not set\n# CONFIG_INCLUDE_CONFIG is not set\n# CONFIG_REPRODUCIBLE_DEBUG_INFO is not set\n# CONFIG_COLLECT_KERNEL_DEBUG is not set\n\n#\n# Kernel build options\n#\nCONFIG_KERNEL_BUILD_USER=\"\"\nCONFIG_KERNEL_BUILD_DOMAIN=\"\"\nCONFIG_KERNEL_PRINTK=y\nCONFIG_KERNEL_SWAP=y\n# CONFIG_KERNEL_PROC_STRIPPED is not set\nCONFIG_KERNEL_DEBUG_FS=y\n# CONFIG_KERNEL_ARM_PMU is not set\n# CONFIG_KERNEL_PERF_EVENTS is not set\n# CONFIG_KERNEL_PROFILING is not set\n# CONFIG_KERNEL_UBSAN is not set\n# CONFIG_KERNEL_KASAN is not set\n# CONFIG_KERNEL_KCOV is not set\n# CONFIG_KERNEL_TASKSTATS is not set\nCONFIG_KERNEL_KALLSYMS=y\n# CONFIG_KERNEL_FTRACE is not set\nCONFIG_KERNEL_DEBUG_KERNEL=y\nCONFIG_KERNEL_DEBUG_INFO=y\n# CONFIG_KERNEL_DYNAMIC_DEBUG is not set\n# CONFIG_KERNEL_KPROBES is not set\nCONFIG_KERNEL_AIO=y\nCONFIG_KERNEL_IO_URING=y\nCONFIG_KERNEL_FHANDLE=y\nCONFIG_KERNEL_FANOTIFY=y\n# CONFIG_KERNEL_BLK_DEV_BSG is not set\n# CONFIG_KERNEL_HUGETLB_PAGE is not set\nCONFIG_KERNEL_MAGIC_SYSRQ=y\n# CONFIG_KERNEL_DEBUG_PINCTRL is not set\n# CONFIG_KERNEL_DEBUG_GPIO is not set\nCONFIG_KERNEL_COREDUMP=y\nCONFIG_KERNEL_ELF_CORE=y\n# CONFIG_KERNEL_PROVE_LOCKING is not set\n# CONFIG_KERNEL_SOFTLOCKUP_DETECTOR is not set\n# CONFIG_KERNEL_DETECT_HUNG_TASK is not set\n# CONFIG_KERNEL_WQ_WATCHDOG is not set\n# CONFIG_KERNEL_DEBUG_ATOMIC_SLEEP is not set\n# CONFIG_KERNEL_DEBUG_VM is not set\nCONFIG_KERNEL_PRINTK_TIME=y\n# CONFIG_KERNEL_SLABINFO is not set\n# CONFIG_KERNEL_PROC_PAGE_MONITOR is not set\n# CONFIG_KERNEL_KEXEC is not set\n# CONFIG_USE_RFKILL is not set\n# CONFIG_USE_SPARSE is not set\n# CONFIG_KERNEL_DEVTMPFS is not set\nCONFIG_KERNEL_KEYS=y\n# CONFIG_KERNEL_PERSISTENT_KEYRINGS is not set\n# CONFIG_KERNEL_KEYS_REQUEST_CACHE is not set\n# CONFIG_KERNEL_BIG_KEYS is not set\nCONFIG_KERNEL_CGROUPS=y\n# CONFIG_KERNEL_CGROUP_DEBUG is not set\nCONFIG_KERNEL_FREEZER=y\nCONFIG_KERNEL_CGROUP_FREEZER=y\nCONFIG_KERNEL_CGROUP_DEVICE=y\n# CONFIG_KERNEL_CGROUP_HUGETLB is not set\nCONFIG_KERNEL_CGROUP_PIDS=y\nCONFIG_KERNEL_CGROUP_RDMA=y\nCONFIG_KERNEL_CGROUP_BPF=y\nCONFIG_KERNEL_CPUSETS=y\n# CONFIG_KERNEL_PROC_PID_CPUSET is not set\nCONFIG_KERNEL_CGROUP_CPUACCT=y\nCONFIG_KERNEL_RESOURCE_COUNTERS=y\nCONFIG_KERNEL_MM_OWNER=y\nCONFIG_KERNEL_MEMCG=y\nCONFIG_KERNEL_MEMCG_SWAP=y\n# CONFIG_KERNEL_MEMCG_SWAP_ENABLED is not set\nCONFIG_KERNEL_MEMCG_KMEM=y\n# CONFIG_KERNEL_CGROUP_PERF is not set\nCONFIG_KERNEL_CGROUP_SCHED=y\nCONFIG_KERNEL_FAIR_GROUP_SCHED=y\nCONFIG_KERNEL_CFS_BANDWIDTH=y\nCONFIG_KERNEL_RT_GROUP_SCHED=y\nCONFIG_KERNEL_BLK_CGROUP=y\n# CONFIG_KERNEL_CFQ_GROUP_IOSCHED is not set\nCONFIG_KERNEL_BLK_DEV_THROTTLING=y\n# CONFIG_KERNEL_BLK_DEV_THROTTLING_LOW is not set\n# CONFIG_KERNEL_DEBUG_BLK_CGROUP is not set\n# CONFIG_KERNEL_NET_CLS_CGROUP is not set\n# CONFIG_KERNEL_CGROUP_NET_CLASSID is not set\n# CONFIG_KERNEL_CGROUP_NET_PRIO is not set\nCONFIG_KERNEL_NAMESPACES=y\nCONFIG_KERNEL_UTS_NS=y\nCONFIG_KERNEL_IPC_NS=y\nCONFIG_KERNEL_USER_NS=y\nCONFIG_KERNEL_PID_NS=y\nCONFIG_KERNEL_NET_NS=y\nCONFIG_KERNEL_DEVPTS_MULTIPLE_INSTANCES=y\nCONFIG_KERNEL_POSIX_MQUEUE=y\nCONFIG_KERNEL_SECCOMP_FILTER=y\nCONFIG_KERNEL_SECCOMP=y\nCONFIG_KERNEL_IP_MROUTE=y\nCONFIG_KERNEL_IPV6=y\nCONFIG_KERNEL_IPV6_MULTIPLE_TABLES=y\nCONFIG_KERNEL_IPV6_SUBTREES=y\nCONFIG_KERNEL_IPV6_MROUTE=y\n# CONFIG_KERNEL_IPV6_PIMSM_V2 is not set\nCONFIG_KERNEL_IPV6_SEG6_LWTUNNEL=y\n# CONFIG_KERNEL_LWTUNNEL_BPF is not set\n# CONFIG_KERNEL_IP_PNP is not set\n\n#\n# Filesystem ACL and attr support options\n#\n# CONFIG_USE_FS_ACL_ATTR is not set\n# CONFIG_KERNEL_FS_POSIX_ACL is not set\n# CONFIG_KERNEL_BTRFS_FS_POSIX_ACL is not set\n# CONFIG_KERNEL_EXT4_FS_POSIX_ACL is not set\n# CONFIG_KERNEL_F2FS_FS_POSIX_ACL is not set\n# CONFIG_KERNEL_JFFS2_FS_POSIX_ACL is not set\n# CONFIG_KERNEL_TMPFS_POSIX_ACL is not set\n# CONFIG_KERNEL_CIFS_ACL is not set\n# CONFIG_KERNEL_HFS_FS_POSIX_ACL is not set\n# CONFIG_KERNEL_HFSPLUS_FS_POSIX_ACL is not set\n# CONFIG_KERNEL_NFS_ACL_SUPPORT is not set\n# CONFIG_KERNEL_NFS_V3_ACL_SUPPORT is not set\n# CONFIG_KERNEL_NFSD_V2_ACL_SUPPORT is not set\n# CONFIG_KERNEL_NFSD_V3_ACL_SUPPORT is not set\n# CONFIG_KERNEL_REISER_FS_POSIX_ACL is not set\n# CONFIG_KERNEL_XFS_POSIX_ACL is not set\n# CONFIG_KERNEL_JFS_POSIX_ACL is not set\n# end of Filesystem ACL and attr support options\n\n# CONFIG_KERNEL_DEVMEM is not set\n# CONFIG_KERNEL_DEVKMEM is not set\nCONFIG_KERNEL_SQUASHFS_FRAGMENT_CACHE_SIZE=3\n# CONFIG_KERNEL_SQUASHFS_XATTR is not set\nCONFIG_KERNEL_CC_OPTIMIZE_FOR_PERFORMANCE=y\n# CONFIG_KERNEL_CC_OPTIMIZE_FOR_SIZE is not set\n# CONFIG_KERNEL_AUDIT is not set\n# CONFIG_KERNEL_SECURITY is not set\n# CONFIG_KERNEL_SECURITY_NETWORK is not set\n# CONFIG_KERNEL_SECURITY_SELINUX is not set\n# CONFIG_KERNEL_EXT4_FS_SECURITY is not set\n# CONFIG_KERNEL_F2FS_FS_SECURITY is not set\n# CONFIG_KERNEL_UBIFS_FS_SECURITY is not set\n# CONFIG_KERNEL_JFFS2_FS_SECURITY is not set\n# end of Kernel build options\n\n#\n# Package build options\n#\n# CONFIG_DEBUG is not set\nCONFIG_IPV6=y\n\n#\n# Stripping options\n#\n# CONFIG_NO_STRIP is not set\n# CONFIG_USE_STRIP is not set\nCONFIG_USE_SSTRIP=y\nCONFIG_SSTRIP_ARGS=\"-z\"\n# CONFIG_STRIP_KERNEL_EXPORTS is not set\n# CONFIG_USE_MKLIBS is not set\n\n#\n# Hardening build options\n#\nCONFIG_PKG_CHECK_FORMAT_SECURITY=y\n# CONFIG_PKG_ASLR_PIE_NONE is not set\nCONFIG_PKG_ASLR_PIE_REGULAR=y\n# CONFIG_PKG_ASLR_PIE_ALL is not set\n# CONFIG_PKG_CC_STACKPROTECTOR_NONE is not set\nCONFIG_PKG_CC_STACKPROTECTOR_REGULAR=y\n# CONFIG_PKG_CC_STACKPROTECTOR_STRONG is not set\n# CONFIG_KERNEL_CC_STACKPROTECTOR_NONE is not set\nCONFIG_KERNEL_CC_STACKPROTECTOR_REGULAR=y\n# CONFIG_KERNEL_CC_STACKPROTECTOR_STRONG is not set\nCONFIG_KERNEL_STACKPROTECTOR=y\n# CONFIG_KERNEL_STACKPROTECTOR_STRONG is not set\n# CONFIG_PKG_FORTIFY_SOURCE_NONE is not set\nCONFIG_PKG_FORTIFY_SOURCE_1=y\n# CONFIG_PKG_FORTIFY_SOURCE_2 is not set\n# CONFIG_PKG_RELRO_NONE is not set\n# CONFIG_PKG_RELRO_PARTIAL is not set\nCONFIG_PKG_RELRO_FULL=y\n# CONFIG_SELINUX is not set\nCONFIG_SECCOMP=y\n# end of Global build settings\n\n# CONFIG_DEVEL is not set\n# CONFIG_BROKEN is not set\nCONFIG_BINARY_FOLDER=\"\"\nCONFIG_DOWNLOAD_FOLDER=\"\"\nCONFIG_LOCALMIRROR=\"\"\nCONFIG_AUTOREBUILD=y\n# CONFIG_AUTOREMOVE is not set\nCONFIG_BUILD_SUFFIX=\"\"\nCONFIG_TARGET_ROOTFS_DIR=\"\"\n# CONFIG_CCACHE is not set\nCONFIG_CCACHE_DIR=\"\"\nCONFIG_EXTERNAL_KERNEL_TREE=\"\"\nCONFIG_KERNEL_GIT_CLONE_URI=\"\"\nCONFIG_BUILD_LOG_DIR=\"\"\nCONFIG_EXTRA_OPTIMIZATION=\"-fno-caller-saves -fno-plt\"\nCONFIG_TARGET_OPTIMIZATION=\"-Os -pipe -mcpu=generic\"\n# CONFIG_EXTRA_TARGET_ARCH is not set\nCONFIG_EXTRA_BINUTILS_CONFIG_OPTIONS=\"\"\nCONFIG_EXTRA_GCC_CONFIG_OPTIONS=\"\"\n# CONFIG_GCC_DEFAULT_PIE is not set\n# CONFIG_GCC_DEFAULT_SSP is not set\n# CONFIG_SJLJ_EXCEPTIONS is not set\n# CONFIG_INSTALL_GFORTRAN is not set\nCONFIG_GDB=y\n# CONFIG_GDB_PYTHON is not set\n# CONFIG_HAS_PREBUILT_LLVM_TOOLCHAIN is not set\nCONFIG_USE_MUSL=y\nCONFIG_SSP_SUPPORT=y\nCONFIG_BINUTILS_VERSION_2_37=y\nCONFIG_BINUTILS_VERSION=\"2.37\"\nCONFIG_GCC_VERSION=\"11.2.0\"\nCONFIG_LIBC=\"musl\"\nCONFIG_TARGET_SUFFIX=\"musl\"\n# CONFIG_IB is not set\n# CONFIG_SDK is not set\n# CONFIG_MAKE_TOOLCHAIN is not set\n# CONFIG_IMAGEOPT is not set\n# CONFIG_PREINITOPT is not set\nCONFIG_TARGET_PREINIT_SUPPRESS_STDERR=y\n# CONFIG_TARGET_PREINIT_DISABLE_FAILSAFE is not set\nCONFIG_TARGET_PREINIT_TIMEOUT=2\n# CONFIG_TARGET_PREINIT_SHOW_NETMSG is not set\n# CONFIG_TARGET_PREINIT_SUPPRESS_FAILSAFE_NETMSG is not set\nCONFIG_TARGET_PREINIT_IFNAME=\"\"\nCONFIG_TARGET_PREINIT_IP=\"192.168.1.1\"\nCONFIG_TARGET_PREINIT_NETMASK=\"255.255.255.0\"\nCONFIG_TARGET_PREINIT_BROADCAST=\"192.168.1.255\"\n# CONFIG_INITOPT is not set\nCONFIG_TARGET_INIT_PATH=\"/usr/sbin:/usr/bin:/sbin:/bin\"\nCONFIG_TARGET_INIT_ENV=\"\"\nCONFIG_TARGET_INIT_CMD=\"/sbin/init\"\nCONFIG_TARGET_INIT_SUPPRESS_STDERR=y\n# CONFIG_VERSIONOPT is not set\nCONFIG_PER_FEED_REPO=y\n# CONFIG_FEED_packages is not set\n# CONFIG_FEED_luci is not set\n# CONFIG_FEED_routing is not set\n# CONFIG_FEED_telephony is not set\n\n#\n# Base system\n#\n# CONFIG_PACKAGE_attendedsysupgrade-common is not set\n# CONFIG_PACKAGE_auc is not set\nCONFIG_PACKAGE_base-files=y\nCONFIG_PACKAGE_block-mount=y\n# CONFIG_PACKAGE_blockd is not set\n# CONFIG_PACKAGE_bridge is not set\nCONFIG_PACKAGE_busybox=y\n# CONFIG_BUSYBOX_CUSTOM is not set\nCONFIG_BUSYBOX_DEFAULT_HAVE_DOT_CONFIG=y\n# CONFIG_BUSYBOX_DEFAULT_DESKTOP is not set\n# CONFIG_BUSYBOX_DEFAULT_EXTRA_COMPAT is not set\n# CONFIG_BUSYBOX_DEFAULT_FEDORA_COMPAT is not set\nCONFIG_BUSYBOX_DEFAULT_INCLUDE_SUSv2=y\nCONFIG_BUSYBOX_DEFAULT_LONG_OPTS=y\nCONFIG_BUSYBOX_DEFAULT_SHOW_USAGE=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_VERBOSE_USAGE=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_COMPRESS_USAGE is not set\nCONFIG_BUSYBOX_DEFAULT_LFS=y\n# CONFIG_BUSYBOX_DEFAULT_PAM is not set\nCONFIG_BUSYBOX_DEFAULT_FEATURE_DEVPTS=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_UTMP is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_WTMP is not set\nCONFIG_BUSYBOX_DEFAULT_FEATURE_PIDFILE=y\nCONFIG_BUSYBOX_DEFAULT_PID_FILE_PATH=\"/var/run\"\n# CONFIG_BUSYBOX_DEFAULT_BUSYBOX is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_SHOW_SCRIPT is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_INSTALLER is not set\n# CONFIG_BUSYBOX_DEFAULT_INSTALL_NO_USR is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_SUID is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_SUID_CONFIG is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_SUID_CONFIG_QUIET is not set\nCONFIG_BUSYBOX_DEFAULT_FEATURE_PREFER_APPLETS=y\nCONFIG_BUSYBOX_DEFAULT_BUSYBOX_EXEC_PATH=\"/proc/self/exe\"\n# CONFIG_BUSYBOX_DEFAULT_SELINUX is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_CLEAN_UP is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_SYSLOG_INFO is not set\nCONFIG_BUSYBOX_DEFAULT_FEATURE_SYSLOG=y\n# CONFIG_BUSYBOX_DEFAULT_STATIC is not set\n# CONFIG_BUSYBOX_DEFAULT_PIE is not set\n# CONFIG_BUSYBOX_DEFAULT_NOMMU is not set\n# CONFIG_BUSYBOX_DEFAULT_BUILD_LIBBUSYBOX is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_LIBBUSYBOX_STATIC is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_INDIVIDUAL is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_SHARED_BUSYBOX is not set\nCONFIG_BUSYBOX_DEFAULT_CROSS_COMPILER_PREFIX=\"\"\nCONFIG_BUSYBOX_DEFAULT_SYSROOT=\"\"\nCONFIG_BUSYBOX_DEFAULT_EXTRA_CFLAGS=\"\"\nCONFIG_BUSYBOX_DEFAULT_EXTRA_LDFLAGS=\"\"\nCONFIG_BUSYBOX_DEFAULT_EXTRA_LDLIBS=\"\"\n# CONFIG_BUSYBOX_DEFAULT_USE_PORTABLE_CODE is not set\n# CONFIG_BUSYBOX_DEFAULT_STACK_OPTIMIZATION_386 is not set\n# CONFIG_BUSYBOX_DEFAULT_STATIC_LIBGCC is not set\nCONFIG_BUSYBOX_DEFAULT_INSTALL_APPLET_SYMLINKS=y\n# CONFIG_BUSYBOX_DEFAULT_INSTALL_APPLET_HARDLINKS is not set\n# CONFIG_BUSYBOX_DEFAULT_INSTALL_APPLET_SCRIPT_WRAPPERS is not set\n# CONFIG_BUSYBOX_DEFAULT_INSTALL_APPLET_DONT is not set\n# CONFIG_BUSYBOX_DEFAULT_INSTALL_SH_APPLET_SYMLINK is not set\n# CONFIG_BUSYBOX_DEFAULT_INSTALL_SH_APPLET_HARDLINK is not set\n# CONFIG_BUSYBOX_DEFAULT_INSTALL_SH_APPLET_SCRIPT_WRAPPER is not set\nCONFIG_BUSYBOX_DEFAULT_PREFIX=\"./_install\"\n# CONFIG_BUSYBOX_DEFAULT_DEBUG is not set\n# CONFIG_BUSYBOX_DEFAULT_DEBUG_PESSIMIZE is not set\n# CONFIG_BUSYBOX_DEFAULT_DEBUG_SANITIZE is not set\n# CONFIG_BUSYBOX_DEFAULT_UNIT_TEST is not set\n# CONFIG_BUSYBOX_DEFAULT_WERROR is not set\n# CONFIG_BUSYBOX_DEFAULT_WARN_SIMPLE_MSG is not set\nCONFIG_BUSYBOX_DEFAULT_NO_DEBUG_LIB=y\n# CONFIG_BUSYBOX_DEFAULT_DMALLOC is not set\n# CONFIG_BUSYBOX_DEFAULT_EFENCE is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_USE_BSS_TAIL is not set\n# CONFIG_BUSYBOX_DEFAULT_FLOAT_DURATION is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_RTMINMAX is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_RTMINMAX_USE_LIBC_DEFINITIONS is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_BUFFERS_USE_MALLOC is not set\nCONFIG_BUSYBOX_DEFAULT_FEATURE_BUFFERS_GO_ON_STACK=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_BUFFERS_GO_IN_BSS is not set\nCONFIG_BUSYBOX_DEFAULT_PASSWORD_MINLEN=6\nCONFIG_BUSYBOX_DEFAULT_MD5_SMALL=1\nCONFIG_BUSYBOX_DEFAULT_SHA3_SMALL=1\nCONFIG_BUSYBOX_DEFAULT_FEATURE_FAST_TOP=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_ETC_NETWORKS is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_ETC_SERVICES is not set\nCONFIG_BUSYBOX_DEFAULT_FEATURE_EDITING=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_EDITING_MAX_LEN=512\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_EDITING_VI is not set\nCONFIG_BUSYBOX_DEFAULT_FEATURE_EDITING_HISTORY=256\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_EDITING_SAVEHISTORY is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_EDITING_SAVE_ON_EXIT is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_REVERSE_SEARCH is not set\nCONFIG_BUSYBOX_DEFAULT_FEATURE_TAB_COMPLETION=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_USERNAME_COMPLETION is not set\nCONFIG_BUSYBOX_DEFAULT_FEATURE_EDITING_FANCY_PROMPT=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_EDITING_WINCH is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_EDITING_ASK_TERMINAL is not set\n# CONFIG_BUSYBOX_DEFAULT_LOCALE_SUPPORT is not set\n# CONFIG_BUSYBOX_DEFAULT_UNICODE_SUPPORT is not set\n# CONFIG_BUSYBOX_DEFAULT_UNICODE_USING_LOCALE is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_CHECK_UNICODE_IN_ENV is not set\nCONFIG_BUSYBOX_DEFAULT_SUBST_WCHAR=0\nCONFIG_BUSYBOX_DEFAULT_LAST_SUPPORTED_WCHAR=0\n# CONFIG_BUSYBOX_DEFAULT_UNICODE_COMBINING_WCHARS is not set\n# CONFIG_BUSYBOX_DEFAULT_UNICODE_WIDE_WCHARS is not set\n# CONFIG_BUSYBOX_DEFAULT_UNICODE_BIDI_SUPPORT is not set\n# CONFIG_BUSYBOX_DEFAULT_UNICODE_NEUTRAL_TABLE is not set\n# CONFIG_BUSYBOX_DEFAULT_UNICODE_PRESERVE_BROKEN is not set\nCONFIG_BUSYBOX_DEFAULT_FEATURE_NON_POSIX_CP=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_VERBOSE_CP_MESSAGE is not set\nCONFIG_BUSYBOX_DEFAULT_FEATURE_USE_SENDFILE=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_COPYBUF_KB=4\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_SKIP_ROOTFS is not set\nCONFIG_BUSYBOX_DEFAULT_MONOTONIC_SYSCALL=y\nCONFIG_BUSYBOX_DEFAULT_IOCTL_HEX2STR_ERROR=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_HWIB is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_SEAMLESS_XZ is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_SEAMLESS_LZMA is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_SEAMLESS_BZ2 is not set\nCONFIG_BUSYBOX_DEFAULT_FEATURE_SEAMLESS_GZ=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_SEAMLESS_Z is not set\n# CONFIG_BUSYBOX_DEFAULT_AR is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_AR_LONG_FILENAMES is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_AR_CREATE is not set\n# CONFIG_BUSYBOX_DEFAULT_UNCOMPRESS is not set\nCONFIG_BUSYBOX_DEFAULT_GUNZIP=y\nCONFIG_BUSYBOX_DEFAULT_ZCAT=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_GUNZIP_LONG_OPTIONS is not set\n# CONFIG_BUSYBOX_DEFAULT_BUNZIP2 is not set\n# CONFIG_BUSYBOX_DEFAULT_BZCAT is not set\n# CONFIG_BUSYBOX_DEFAULT_UNLZMA is not set\n# CONFIG_BUSYBOX_DEFAULT_LZCAT is not set\n# CONFIG_BUSYBOX_DEFAULT_LZMA is not set\n# CONFIG_BUSYBOX_DEFAULT_UNXZ is not set\n# CONFIG_BUSYBOX_DEFAULT_XZCAT is not set\n# CONFIG_BUSYBOX_DEFAULT_XZ is not set\n# CONFIG_BUSYBOX_DEFAULT_BZIP2 is not set\nCONFIG_BUSYBOX_DEFAULT_BZIP2_SMALL=0\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_BZIP2_DECOMPRESS is not set\n# CONFIG_BUSYBOX_DEFAULT_CPIO is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_CPIO_O is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_CPIO_P is not set\n# CONFIG_BUSYBOX_DEFAULT_DPKG is not set\n# CONFIG_BUSYBOX_DEFAULT_DPKG_DEB is not set\nCONFIG_BUSYBOX_DEFAULT_GZIP=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_GZIP_LONG_OPTIONS is not set\nCONFIG_BUSYBOX_DEFAULT_GZIP_FAST=0\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_GZIP_LEVELS is not set\nCONFIG_BUSYBOX_DEFAULT_FEATURE_GZIP_DECOMPRESS=y\n# CONFIG_BUSYBOX_DEFAULT_LZOP is not set\n# CONFIG_BUSYBOX_DEFAULT_UNLZOP is not set\n# CONFIG_BUSYBOX_DEFAULT_LZOPCAT is not set\n# CONFIG_BUSYBOX_DEFAULT_LZOP_COMPR_HIGH is not set\n# CONFIG_BUSYBOX_DEFAULT_RPM is not set\n# CONFIG_BUSYBOX_DEFAULT_RPM2CPIO is not set\nCONFIG_BUSYBOX_DEFAULT_TAR=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_TAR_LONG_OPTIONS is not set\nCONFIG_BUSYBOX_DEFAULT_FEATURE_TAR_CREATE=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_TAR_AUTODETECT is not set\nCONFIG_BUSYBOX_DEFAULT_FEATURE_TAR_FROM=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_TAR_OLDGNU_COMPATIBILITY is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_TAR_OLDSUN_COMPATIBILITY is not set\nCONFIG_BUSYBOX_DEFAULT_FEATURE_TAR_GNU_EXTENSIONS=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_TAR_TO_COMMAND is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_TAR_UNAME_GNAME is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_TAR_NOPRESERVE_TIME is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_TAR_SELINUX is not set\n# CONFIG_BUSYBOX_DEFAULT_UNZIP is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_UNZIP_CDF is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_UNZIP_BZIP2 is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_UNZIP_LZMA is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_UNZIP_XZ is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_LZMA_FAST is not set\nCONFIG_BUSYBOX_DEFAULT_BASENAME=y\nCONFIG_BUSYBOX_DEFAULT_CAT=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_CATN is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_CATV is not set\nCONFIG_BUSYBOX_DEFAULT_CHGRP=y\nCONFIG_BUSYBOX_DEFAULT_CHMOD=y\nCONFIG_BUSYBOX_DEFAULT_CHOWN=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_CHOWN_LONG_OPTIONS is not set\nCONFIG_BUSYBOX_DEFAULT_CHROOT=y\n# CONFIG_BUSYBOX_DEFAULT_CKSUM is not set\n# CONFIG_BUSYBOX_DEFAULT_CRC32 is not set\n# CONFIG_BUSYBOX_DEFAULT_COMM is not set\nCONFIG_BUSYBOX_DEFAULT_CP=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_CP_LONG_OPTIONS is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_CP_REFLINK is not set\nCONFIG_BUSYBOX_DEFAULT_CUT=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_CUT_REGEX is not set\nCONFIG_BUSYBOX_DEFAULT_DATE=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_DATE_ISOFMT=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_DATE_NANO is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_DATE_COMPAT is not set\nCONFIG_BUSYBOX_DEFAULT_DD=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_DD_SIGNAL_HANDLING=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_DD_THIRD_STATUS_LINE is not set\nCONFIG_BUSYBOX_DEFAULT_FEATURE_DD_IBS_OBS=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_DD_STATUS is not set\nCONFIG_BUSYBOX_DEFAULT_DF=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_DF_FANCY is not set\nCONFIG_BUSYBOX_DEFAULT_DIRNAME=y\n# CONFIG_BUSYBOX_DEFAULT_DOS2UNIX is not set\n# CONFIG_BUSYBOX_DEFAULT_UNIX2DOS is not set\nCONFIG_BUSYBOX_DEFAULT_DU=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_DU_DEFAULT_BLOCKSIZE_1K=y\nCONFIG_BUSYBOX_DEFAULT_ECHO=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_FANCY_ECHO=y\nCONFIG_BUSYBOX_DEFAULT_ENV=y\n# CONFIG_BUSYBOX_DEFAULT_EXPAND is not set\n# CONFIG_BUSYBOX_DEFAULT_UNEXPAND is not set\nCONFIG_BUSYBOX_DEFAULT_EXPR=y\nCONFIG_BUSYBOX_DEFAULT_EXPR_MATH_SUPPORT_64=y\n# CONFIG_BUSYBOX_DEFAULT_FACTOR is not set\nCONFIG_BUSYBOX_DEFAULT_FALSE=y\n# CONFIG_BUSYBOX_DEFAULT_FOLD is not set\nCONFIG_BUSYBOX_DEFAULT_HEAD=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_FANCY_HEAD=y\n# CONFIG_BUSYBOX_DEFAULT_HOSTID is not set\nCONFIG_BUSYBOX_DEFAULT_ID=y\n# CONFIG_BUSYBOX_DEFAULT_GROUPS is not set\n# CONFIG_BUSYBOX_DEFAULT_INSTALL is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_INSTALL_LONG_OPTIONS is not set\n# CONFIG_BUSYBOX_DEFAULT_LINK is not set\nCONFIG_BUSYBOX_DEFAULT_LN=y\n# CONFIG_BUSYBOX_DEFAULT_LOGNAME is not set\nCONFIG_BUSYBOX_DEFAULT_LS=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_LS_FILETYPES=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_LS_FOLLOWLINKS=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_LS_RECURSIVE=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_LS_WIDTH=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_LS_SORTFILES=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_LS_TIMESTAMPS=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_LS_USERNAME=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_LS_COLOR=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_LS_COLOR_IS_DEFAULT=y\nCONFIG_BUSYBOX_DEFAULT_MD5SUM=y\n# CONFIG_BUSYBOX_DEFAULT_SHA1SUM is not set\nCONFIG_BUSYBOX_DEFAULT_SHA256SUM=y\n# CONFIG_BUSYBOX_DEFAULT_SHA512SUM is not set\n# CONFIG_BUSYBOX_DEFAULT_SHA3SUM is not set\nCONFIG_BUSYBOX_DEFAULT_FEATURE_MD5_SHA1_SUM_CHECK=y\nCONFIG_BUSYBOX_DEFAULT_MKDIR=y\nCONFIG_BUSYBOX_DEFAULT_MKFIFO=y\nCONFIG_BUSYBOX_DEFAULT_MKNOD=y\nCONFIG_BUSYBOX_DEFAULT_MKTEMP=y\nCONFIG_BUSYBOX_DEFAULT_MV=y\nCONFIG_BUSYBOX_DEFAULT_NICE=y\n# CONFIG_BUSYBOX_DEFAULT_NL is not set\n# CONFIG_BUSYBOX_DEFAULT_NOHUP is not set\n# CONFIG_BUSYBOX_DEFAULT_NPROC is not set\n# CONFIG_BUSYBOX_DEFAULT_OD is not set\n# CONFIG_BUSYBOX_DEFAULT_PASTE is not set\n# CONFIG_BUSYBOX_DEFAULT_PRINTENV is not set\nCONFIG_BUSYBOX_DEFAULT_PRINTF=y\nCONFIG_BUSYBOX_DEFAULT_PWD=y\nCONFIG_BUSYBOX_DEFAULT_READLINK=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_READLINK_FOLLOW=y\n# CONFIG_BUSYBOX_DEFAULT_REALPATH is not set\nCONFIG_BUSYBOX_DEFAULT_RM=y\nCONFIG_BUSYBOX_DEFAULT_RMDIR=y\nCONFIG_BUSYBOX_DEFAULT_SEQ=y\n# CONFIG_BUSYBOX_DEFAULT_SHRED is not set\n# CONFIG_BUSYBOX_DEFAULT_SHUF is not set\nCONFIG_BUSYBOX_DEFAULT_SLEEP=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_FANCY_SLEEP=y\nCONFIG_BUSYBOX_DEFAULT_SORT=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_SORT_BIG is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_SORT_OPTIMIZE_MEMORY is not set\n# CONFIG_BUSYBOX_DEFAULT_SPLIT is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_SPLIT_FANCY is not set\n# CONFIG_BUSYBOX_DEFAULT_STAT is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_STAT_FORMAT is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_STAT_FILESYSTEM is not set\n# CONFIG_BUSYBOX_DEFAULT_STTY is not set\n# CONFIG_BUSYBOX_DEFAULT_SUM is not set\nCONFIG_BUSYBOX_DEFAULT_SYNC=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_SYNC_FANCY is not set\nCONFIG_BUSYBOX_DEFAULT_FSYNC=y\n# CONFIG_BUSYBOX_DEFAULT_TAC is not set\nCONFIG_BUSYBOX_DEFAULT_TAIL=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_FANCY_TAIL=y\nCONFIG_BUSYBOX_DEFAULT_TEE=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_TEE_USE_BLOCK_IO=y\nCONFIG_BUSYBOX_DEFAULT_TEST=y\nCONFIG_BUSYBOX_DEFAULT_TEST1=y\nCONFIG_BUSYBOX_DEFAULT_TEST2=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_TEST_64=y\n# CONFIG_BUSYBOX_DEFAULT_TIMEOUT is not set\nCONFIG_BUSYBOX_DEFAULT_TOUCH=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_TOUCH_SUSV3=y\nCONFIG_BUSYBOX_DEFAULT_TR=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_TR_CLASSES is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_TR_EQUIV is not set\nCONFIG_BUSYBOX_DEFAULT_TRUE=y\n# CONFIG_BUSYBOX_DEFAULT_TRUNCATE is not set\n# CONFIG_BUSYBOX_DEFAULT_TTY is not set\nCONFIG_BUSYBOX_DEFAULT_UNAME=y\nCONFIG_BUSYBOX_DEFAULT_UNAME_OSNAME=\"GNU/Linux\"\n# CONFIG_BUSYBOX_DEFAULT_BB_ARCH is not set\nCONFIG_BUSYBOX_DEFAULT_UNIQ=y\n# CONFIG_BUSYBOX_DEFAULT_UNLINK is not set\n# CONFIG_BUSYBOX_DEFAULT_USLEEP is not set\n# CONFIG_BUSYBOX_DEFAULT_UUDECODE is not set\n# CONFIG_BUSYBOX_DEFAULT_BASE32 is not set\n# CONFIG_BUSYBOX_DEFAULT_BASE64 is not set\n# CONFIG_BUSYBOX_DEFAULT_UUENCODE is not set\nCONFIG_BUSYBOX_DEFAULT_WC=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_WC_LARGE is not set\n# CONFIG_BUSYBOX_DEFAULT_WHO is not set\n# CONFIG_BUSYBOX_DEFAULT_W is not set\n# CONFIG_BUSYBOX_DEFAULT_USERS is not set\n# CONFIG_BUSYBOX_DEFAULT_WHOAMI is not set\nCONFIG_BUSYBOX_DEFAULT_YES=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_VERBOSE is not set\nCONFIG_BUSYBOX_DEFAULT_FEATURE_PRESERVE_HARDLINKS=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_HUMAN_READABLE=y\n# CONFIG_BUSYBOX_DEFAULT_CHVT is not set\nCONFIG_BUSYBOX_DEFAULT_CLEAR=y\n# CONFIG_BUSYBOX_DEFAULT_DEALLOCVT is not set\n# CONFIG_BUSYBOX_DEFAULT_DUMPKMAP is not set\n# CONFIG_BUSYBOX_DEFAULT_FGCONSOLE is not set\n# CONFIG_BUSYBOX_DEFAULT_KBD_MODE is not set\n# CONFIG_BUSYBOX_DEFAULT_LOADFONT is not set\n# CONFIG_BUSYBOX_DEFAULT_SETFONT is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_SETFONT_TEXTUAL_MAP is not set\nCONFIG_BUSYBOX_DEFAULT_DEFAULT_SETFONT_DIR=\"\"\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_LOADFONT_PSF2 is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_LOADFONT_RAW is not set\n# CONFIG_BUSYBOX_DEFAULT_LOADKMAP is not set\n# CONFIG_BUSYBOX_DEFAULT_OPENVT is not set\nCONFIG_BUSYBOX_DEFAULT_RESET=y\n# CONFIG_BUSYBOX_DEFAULT_RESIZE is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_RESIZE_PRINT is not set\n# CONFIG_BUSYBOX_DEFAULT_SETCONSOLE is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_SETCONSOLE_LONG_OPTIONS is not set\n# CONFIG_BUSYBOX_DEFAULT_SETKEYCODES is not set\n# CONFIG_BUSYBOX_DEFAULT_SETLOGCONS is not set\n# CONFIG_BUSYBOX_DEFAULT_SHOWKEY is not set\n# CONFIG_BUSYBOX_DEFAULT_PIPE_PROGRESS is not set\n# CONFIG_BUSYBOX_DEFAULT_RUN_PARTS is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_RUN_PARTS_LONG_OPTIONS is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_RUN_PARTS_FANCY is not set\nCONFIG_BUSYBOX_DEFAULT_START_STOP_DAEMON=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_START_STOP_DAEMON_LONG_OPTIONS is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_START_STOP_DAEMON_FANCY is not set\nCONFIG_BUSYBOX_DEFAULT_WHICH=y\n# CONFIG_BUSYBOX_DEFAULT_MINIPS is not set\n# CONFIG_BUSYBOX_DEFAULT_NUKE is not set\n# CONFIG_BUSYBOX_DEFAULT_RESUME is not set\n# CONFIG_BUSYBOX_DEFAULT_RUN_INIT is not set\nCONFIG_BUSYBOX_DEFAULT_AWK=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_AWK_LIBM=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_AWK_GNU_EXTENSIONS=y\nCONFIG_BUSYBOX_DEFAULT_CMP=y\n# CONFIG_BUSYBOX_DEFAULT_DIFF is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_DIFF_LONG_OPTIONS is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_DIFF_DIR is not set\n# CONFIG_BUSYBOX_DEFAULT_ED is not set\n# CONFIG_BUSYBOX_DEFAULT_PATCH is not set\nCONFIG_BUSYBOX_DEFAULT_SED=y\nCONFIG_BUSYBOX_DEFAULT_VI=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_VI_MAX_LEN=1024\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_VI_8BIT is not set\nCONFIG_BUSYBOX_DEFAULT_FEATURE_VI_COLON=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_VI_COLON_EXPAND is not set\nCONFIG_BUSYBOX_DEFAULT_FEATURE_VI_YANKMARK=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_VI_SEARCH=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_VI_REGEX_SEARCH is not set\nCONFIG_BUSYBOX_DEFAULT_FEATURE_VI_USE_SIGNALS=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_VI_DOT_CMD=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_VI_READONLY=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_VI_SETOPTS=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_VI_SET=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_VI_WIN_RESIZE=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_VI_ASK_TERMINAL=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_VI_UNDO is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_VI_UNDO_QUEUE is not set\nCONFIG_BUSYBOX_DEFAULT_FEATURE_VI_UNDO_QUEUE_MAX=0\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_VI_VERBOSE_STATUS is not set\nCONFIG_BUSYBOX_DEFAULT_FEATURE_ALLOW_EXEC=y\nCONFIG_BUSYBOX_DEFAULT_FIND=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_FIND_PRINT0=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_FIND_MTIME=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_FIND_MMIN=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_FIND_PERM=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_FIND_TYPE=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_FIND_EXECUTABLE is not set\nCONFIG_BUSYBOX_DEFAULT_FEATURE_FIND_XDEV=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_FIND_MAXDEPTH=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_FIND_NEWER=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_FIND_INUM is not set\nCONFIG_BUSYBOX_DEFAULT_FEATURE_FIND_EXEC=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_FIND_EXEC_PLUS is not set\nCONFIG_BUSYBOX_DEFAULT_FEATURE_FIND_USER=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_FIND_GROUP=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_FIND_NOT=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_FIND_DEPTH=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_FIND_PAREN=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_FIND_SIZE=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_FIND_PRUNE=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_FIND_QUIT is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_FIND_DELETE is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_FIND_EMPTY is not set\nCONFIG_BUSYBOX_DEFAULT_FEATURE_FIND_PATH=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_FIND_REGEX=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_FIND_CONTEXT is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_FIND_LINKS is not set\nCONFIG_BUSYBOX_DEFAULT_GREP=y\nCONFIG_BUSYBOX_DEFAULT_EGREP=y\nCONFIG_BUSYBOX_DEFAULT_FGREP=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_GREP_CONTEXT=y\nCONFIG_BUSYBOX_DEFAULT_XARGS=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_XARGS_SUPPORT_CONFIRMATION=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_XARGS_SUPPORT_QUOTES=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_XARGS_SUPPORT_TERMOPT=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_XARGS_SUPPORT_ZERO_TERM=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_XARGS_SUPPORT_REPL_STR is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_XARGS_SUPPORT_PARALLEL is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_XARGS_SUPPORT_ARGS_FILE is not set\n# CONFIG_BUSYBOX_DEFAULT_BOOTCHARTD is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_BOOTCHARTD_BLOATED_HEADER is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_BOOTCHARTD_CONFIG_FILE is not set\nCONFIG_BUSYBOX_DEFAULT_HALT=y\nCONFIG_BUSYBOX_DEFAULT_POWEROFF=y\nCONFIG_BUSYBOX_DEFAULT_REBOOT=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_WAIT_FOR_INIT is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_CALL_TELINIT is not set\nCONFIG_BUSYBOX_DEFAULT_TELINIT_PATH=\"\"\n# CONFIG_BUSYBOX_DEFAULT_INIT is not set\n# CONFIG_BUSYBOX_DEFAULT_LINUXRC is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_USE_INITTAB is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_KILL_REMOVED is not set\nCONFIG_BUSYBOX_DEFAULT_FEATURE_KILL_DELAY=0\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_INIT_SCTTY is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_INIT_SYSLOG is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_INIT_QUIET is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_INIT_COREDUMPS is not set\nCONFIG_BUSYBOX_DEFAULT_INIT_TERMINAL_TYPE=\"\"\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_INIT_MODIFY_CMDLINE is not set\nCONFIG_BUSYBOX_DEFAULT_FEATURE_SHADOWPASSWDS=y\n# CONFIG_BUSYBOX_DEFAULT_USE_BB_PWD_GRP is not set\n# CONFIG_BUSYBOX_DEFAULT_USE_BB_SHADOW is not set\n# CONFIG_BUSYBOX_DEFAULT_USE_BB_CRYPT is not set\n# CONFIG_BUSYBOX_DEFAULT_USE_BB_CRYPT_SHA is not set\n# CONFIG_BUSYBOX_DEFAULT_ADD_SHELL is not set\n# CONFIG_BUSYBOX_DEFAULT_REMOVE_SHELL is not set\n# CONFIG_BUSYBOX_DEFAULT_ADDGROUP is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_ADDUSER_TO_GROUP is not set\n# CONFIG_BUSYBOX_DEFAULT_ADDUSER is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_CHECK_NAMES is not set\nCONFIG_BUSYBOX_DEFAULT_LAST_ID=0\nCONFIG_BUSYBOX_DEFAULT_FIRST_SYSTEM_ID=0\nCONFIG_BUSYBOX_DEFAULT_LAST_SYSTEM_ID=0\n# CONFIG_BUSYBOX_DEFAULT_CHPASSWD is not set\nCONFIG_BUSYBOX_DEFAULT_FEATURE_DEFAULT_PASSWD_ALGO=\"md5\"\n# CONFIG_BUSYBOX_DEFAULT_CRYPTPW is not set\n# CONFIG_BUSYBOX_DEFAULT_MKPASSWD is not set\n# CONFIG_BUSYBOX_DEFAULT_DELUSER is not set\n# CONFIG_BUSYBOX_DEFAULT_DELGROUP is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_DEL_USER_FROM_GROUP is not set\n# CONFIG_BUSYBOX_DEFAULT_GETTY is not set\nCONFIG_BUSYBOX_DEFAULT_LOGIN=y\nCONFIG_BUSYBOX_DEFAULT_LOGIN_SESSION_AS_CHILD=y\n# CONFIG_BUSYBOX_DEFAULT_LOGIN_SCRIPTS is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_NOLOGIN is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_SECURETTY is not set\nCONFIG_BUSYBOX_DEFAULT_PASSWD=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_PASSWD_WEAK_CHECK=y\n# CONFIG_BUSYBOX_DEFAULT_SU is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_SU_SYSLOG is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_SU_CHECKS_SHELLS is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_SU_BLANK_PW_NEEDS_SECURE_TTY is not set\n# CONFIG_BUSYBOX_DEFAULT_SULOGIN is not set\n# CONFIG_BUSYBOX_DEFAULT_VLOCK is not set\n# CONFIG_BUSYBOX_DEFAULT_CHATTR is not set\n# CONFIG_BUSYBOX_DEFAULT_FSCK is not set\n# CONFIG_BUSYBOX_DEFAULT_LSATTR is not set\n# CONFIG_BUSYBOX_DEFAULT_TUNE2FS is not set\n# CONFIG_BUSYBOX_DEFAULT_MODPROBE_SMALL is not set\n# CONFIG_BUSYBOX_DEFAULT_DEPMOD is not set\n# CONFIG_BUSYBOX_DEFAULT_INSMOD is not set\n# CONFIG_BUSYBOX_DEFAULT_LSMOD is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_LSMOD_PRETTY_2_6_OUTPUT is not set\n# CONFIG_BUSYBOX_DEFAULT_MODINFO is not set\n# CONFIG_BUSYBOX_DEFAULT_MODPROBE is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_MODPROBE_BLACKLIST is not set\n# CONFIG_BUSYBOX_DEFAULT_RMMOD is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_CMDLINE_MODULE_OPTIONS is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_MODPROBE_SMALL_CHECK_ALREADY_LOADED is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_2_4_MODULES is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_INSMOD_VERSION_CHECKING is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_INSMOD_KSYMOOPS_SYMBOLS is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_INSMOD_LOADINKMEM is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_INSMOD_LOAD_MAP is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_INSMOD_LOAD_MAP_FULL is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_CHECK_TAINTED_MODULE is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_INSMOD_TRY_MMAP is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_MODUTILS_ALIAS is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_MODUTILS_SYMBOLS is not set\nCONFIG_BUSYBOX_DEFAULT_DEFAULT_MODULES_DIR=\"\"\nCONFIG_BUSYBOX_DEFAULT_DEFAULT_DEPMOD_FILE=\"\"\n# CONFIG_BUSYBOX_DEFAULT_ACPID is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_ACPID_COMPAT is not set\n# CONFIG_BUSYBOX_DEFAULT_BLKDISCARD is not set\n# CONFIG_BUSYBOX_DEFAULT_BLKID is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_BLKID_TYPE is not set\n# CONFIG_BUSYBOX_DEFAULT_BLOCKDEV is not set\n# CONFIG_BUSYBOX_DEFAULT_CAL is not set\n# CONFIG_BUSYBOX_DEFAULT_CHRT is not set\nCONFIG_BUSYBOX_DEFAULT_DMESG=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_DMESG_PRETTY=y\n# CONFIG_BUSYBOX_DEFAULT_EJECT is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_EJECT_SCSI is not set\n# CONFIG_BUSYBOX_DEFAULT_FALLOCATE is not set\n# CONFIG_BUSYBOX_DEFAULT_FATATTR is not set\n# CONFIG_BUSYBOX_DEFAULT_FBSET is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_FBSET_FANCY is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_FBSET_READMODE is not set\n# CONFIG_BUSYBOX_DEFAULT_FDFORMAT is not set\n# CONFIG_BUSYBOX_DEFAULT_FDISK is not set\n# CONFIG_BUSYBOX_DEFAULT_FDISK_SUPPORT_LARGE_DISKS is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_FDISK_WRITABLE is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_AIX_LABEL is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_SGI_LABEL is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_SUN_LABEL is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_OSF_LABEL is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_GPT_LABEL is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_FDISK_ADVANCED is not set\n# CONFIG_BUSYBOX_DEFAULT_FINDFS is not set\nCONFIG_BUSYBOX_DEFAULT_FLOCK=y\n# CONFIG_BUSYBOX_DEFAULT_FDFLUSH is not set\n# CONFIG_BUSYBOX_DEFAULT_FREERAMDISK is not set\n# CONFIG_BUSYBOX_DEFAULT_FSCK_MINIX is not set\n# CONFIG_BUSYBOX_DEFAULT_FSFREEZE is not set\n# CONFIG_BUSYBOX_DEFAULT_FSTRIM is not set\n# CONFIG_BUSYBOX_DEFAULT_GETOPT is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_GETOPT_LONG is not set\nCONFIG_BUSYBOX_DEFAULT_HEXDUMP=y\n# CONFIG_BUSYBOX_DEFAULT_HD is not set\n# CONFIG_BUSYBOX_DEFAULT_XXD is not set\nCONFIG_BUSYBOX_DEFAULT_HWCLOCK=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_HWCLOCK_ADJTIME_FHS is not set\n# CONFIG_BUSYBOX_DEFAULT_IONICE is not set\n# CONFIG_BUSYBOX_DEFAULT_IPCRM is not set\n# CONFIG_BUSYBOX_DEFAULT_IPCS is not set\n# CONFIG_BUSYBOX_DEFAULT_LAST is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_LAST_FANCY is not set\n# CONFIG_BUSYBOX_DEFAULT_LOSETUP is not set\n# CONFIG_BUSYBOX_DEFAULT_LSPCI is not set\n# CONFIG_BUSYBOX_DEFAULT_LSUSB is not set\n# CONFIG_BUSYBOX_DEFAULT_MDEV is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_MDEV_CONF is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_MDEV_RENAME is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_MDEV_RENAME_REGEXP is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_MDEV_EXEC is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_MDEV_LOAD_FIRMWARE is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_MDEV_DAEMON is not set\n# CONFIG_BUSYBOX_DEFAULT_MESG is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_MESG_ENABLE_ONLY_GROUP is not set\n# CONFIG_BUSYBOX_DEFAULT_MKE2FS is not set\n# CONFIG_BUSYBOX_DEFAULT_MKFS_EXT2 is not set\n# CONFIG_BUSYBOX_DEFAULT_MKFS_MINIX is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_MINIX2 is not set\n# CONFIG_BUSYBOX_DEFAULT_MKFS_REISER is not set\n# CONFIG_BUSYBOX_DEFAULT_MKDOSFS is not set\n# CONFIG_BUSYBOX_DEFAULT_MKFS_VFAT is not set\nCONFIG_BUSYBOX_DEFAULT_MKSWAP=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_MKSWAP_UUID is not set\n# CONFIG_BUSYBOX_DEFAULT_MORE is not set\nCONFIG_BUSYBOX_DEFAULT_MOUNT=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_MOUNT_FAKE is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_MOUNT_VERBOSE is not set\nCONFIG_BUSYBOX_DEFAULT_FEATURE_MOUNT_HELPERS=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_MOUNT_LABEL is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_MOUNT_NFS is not set\nCONFIG_BUSYBOX_DEFAULT_FEATURE_MOUNT_CIFS=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_MOUNT_FLAGS=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_MOUNT_FSTAB=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_MOUNT_OTHERTAB is not set\n# CONFIG_BUSYBOX_DEFAULT_MOUNTPOINT is not set\n# CONFIG_BUSYBOX_DEFAULT_NOLOGIN is not set\n# CONFIG_BUSYBOX_DEFAULT_NOLOGIN_DEPENDENCIES is not set\n# CONFIG_BUSYBOX_DEFAULT_NSENTER is not set\nCONFIG_BUSYBOX_DEFAULT_PIVOT_ROOT=y\n# CONFIG_BUSYBOX_DEFAULT_RDATE is not set\n# CONFIG_BUSYBOX_DEFAULT_RDEV is not set\n# CONFIG_BUSYBOX_DEFAULT_READPROFILE is not set\n# CONFIG_BUSYBOX_DEFAULT_RENICE is not set\n# CONFIG_BUSYBOX_DEFAULT_REV is not set\n# CONFIG_BUSYBOX_DEFAULT_RTCWAKE is not set\n# CONFIG_BUSYBOX_DEFAULT_SCRIPT is not set\n# CONFIG_BUSYBOX_DEFAULT_SCRIPTREPLAY is not set\n# CONFIG_BUSYBOX_DEFAULT_SETARCH is not set\n# CONFIG_BUSYBOX_DEFAULT_LINUX32 is not set\n# CONFIG_BUSYBOX_DEFAULT_LINUX64 is not set\n# CONFIG_BUSYBOX_DEFAULT_SETPRIV is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_SETPRIV_DUMP is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_SETPRIV_CAPABILITIES is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_SETPRIV_CAPABILITY_NAMES is not set\n# CONFIG_BUSYBOX_DEFAULT_SETSID is not set\nCONFIG_BUSYBOX_DEFAULT_SWAPON=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_SWAPON_DISCARD=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_SWAPON_PRI=y\nCONFIG_BUSYBOX_DEFAULT_SWAPOFF=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_SWAPONOFF_LABEL is not set\nCONFIG_BUSYBOX_DEFAULT_SWITCH_ROOT=y\n# CONFIG_BUSYBOX_DEFAULT_TASKSET is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_TASKSET_FANCY is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_TASKSET_CPULIST is not set\n# CONFIG_BUSYBOX_DEFAULT_UEVENT is not set\nCONFIG_BUSYBOX_DEFAULT_UMOUNT=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_UMOUNT_ALL=y\n# CONFIG_BUSYBOX_DEFAULT_UNSHARE is not set\n# CONFIG_BUSYBOX_DEFAULT_WALL is not set\nCONFIG_BUSYBOX_DEFAULT_FEATURE_MOUNT_LOOP=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_MOUNT_LOOP_CREATE is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_MTAB_SUPPORT is not set\n# CONFIG_BUSYBOX_DEFAULT_VOLUMEID is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_VOLUMEID_BCACHE is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_VOLUMEID_BTRFS is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_VOLUMEID_CRAMFS is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_VOLUMEID_EROFS is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_VOLUMEID_EXFAT is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_VOLUMEID_EXT is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_VOLUMEID_F2FS is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_VOLUMEID_FAT is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_VOLUMEID_HFS is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_VOLUMEID_ISO9660 is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_VOLUMEID_JFS is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_VOLUMEID_LFS is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_VOLUMEID_LINUXRAID is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_VOLUMEID_LINUXSWAP is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_VOLUMEID_LUKS is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_VOLUMEID_MINIX is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_VOLUMEID_NILFS is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_VOLUMEID_NTFS is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_VOLUMEID_OCFS2 is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_VOLUMEID_REISERFS is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_VOLUMEID_ROMFS is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_VOLUMEID_SQUASHFS is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_VOLUMEID_SYSV is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_VOLUMEID_UBIFS is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_VOLUMEID_UDF is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_VOLUMEID_XFS is not set\n# CONFIG_BUSYBOX_DEFAULT_ADJTIMEX is not set\n# CONFIG_BUSYBOX_DEFAULT_ASCII is not set\n# CONFIG_BUSYBOX_DEFAULT_BBCONFIG is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_COMPRESS_BBCONFIG is not set\n# CONFIG_BUSYBOX_DEFAULT_BC is not set\n# CONFIG_BUSYBOX_DEFAULT_DC is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_DC_BIG is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_DC_LIBM is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_BC_INTERACTIVE is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_BC_LONG_OPTIONS is not set\n# CONFIG_BUSYBOX_DEFAULT_BEEP is not set\nCONFIG_BUSYBOX_DEFAULT_FEATURE_BEEP_FREQ=0\nCONFIG_BUSYBOX_DEFAULT_FEATURE_BEEP_LENGTH_MS=0\n# CONFIG_BUSYBOX_DEFAULT_CHAT is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_CHAT_NOFAIL is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_CHAT_TTY_HIFI is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_CHAT_IMPLICIT_CR is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_CHAT_SWALLOW_OPTS is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_CHAT_SEND_ESCAPES is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_CHAT_VAR_ABORT_LEN is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_CHAT_CLR_ABORT is not set\n# CONFIG_BUSYBOX_DEFAULT_CONSPY is not set\nCONFIG_BUSYBOX_DEFAULT_CROND=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_CROND_D is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_CROND_CALL_SENDMAIL is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_CROND_SPECIAL_TIMES is not set\nCONFIG_BUSYBOX_DEFAULT_FEATURE_CROND_DIR=\"/etc\"\nCONFIG_BUSYBOX_DEFAULT_CRONTAB=y\n# CONFIG_BUSYBOX_DEFAULT_DEVFSD is not set\n# CONFIG_BUSYBOX_DEFAULT_DEVFSD_MODLOAD is not set\n# CONFIG_BUSYBOX_DEFAULT_DEVFSD_FG_NP is not set\n# CONFIG_BUSYBOX_DEFAULT_DEVFSD_VERBOSE is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_DEVFS is not set\n# CONFIG_BUSYBOX_DEFAULT_DEVMEM is not set\n# CONFIG_BUSYBOX_DEFAULT_FBSPLASH is not set\n# CONFIG_BUSYBOX_DEFAULT_FLASH_ERASEALL is not set\n# CONFIG_BUSYBOX_DEFAULT_FLASH_LOCK is not set\n# CONFIG_BUSYBOX_DEFAULT_FLASH_UNLOCK is not set\n# CONFIG_BUSYBOX_DEFAULT_FLASHCP is not set\n# CONFIG_BUSYBOX_DEFAULT_HDPARM is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_HDPARM_GET_IDENTITY is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_HDPARM_HDIO_SCAN_HWIF is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_HDPARM_HDIO_UNREGISTER_HWIF is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_HDPARM_HDIO_DRIVE_RESET is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_HDPARM_HDIO_TRISTATE_HWIF is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_HDPARM_HDIO_GETSET_DMA is not set\n# CONFIG_BUSYBOX_DEFAULT_HEXEDIT is not set\n# CONFIG_BUSYBOX_DEFAULT_I2CGET is not set\n# CONFIG_BUSYBOX_DEFAULT_I2CSET is not set\n# CONFIG_BUSYBOX_DEFAULT_I2CDUMP is not set\n# CONFIG_BUSYBOX_DEFAULT_I2CDETECT is not set\n# CONFIG_BUSYBOX_DEFAULT_I2CTRANSFER is not set\n# CONFIG_BUSYBOX_DEFAULT_INOTIFYD is not set\nCONFIG_BUSYBOX_DEFAULT_LESS=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_LESS_MAXLINES=9999999\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_LESS_BRACKETS is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_LESS_FLAGS is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_LESS_TRUNCATE is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_LESS_MARKS is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_LESS_REGEXP is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_LESS_WINCH is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_LESS_ASK_TERMINAL is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_LESS_DASHCMD is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_LESS_LINENUMS is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_LESS_RAW is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_LESS_ENV is not set\nCONFIG_BUSYBOX_DEFAULT_LOCK=y\n# CONFIG_BUSYBOX_DEFAULT_LSSCSI is not set\n# CONFIG_BUSYBOX_DEFAULT_MAKEDEVS is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_MAKEDEVS_LEAF is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_MAKEDEVS_TABLE is not set\n# CONFIG_BUSYBOX_DEFAULT_MAN is not set\n# CONFIG_BUSYBOX_DEFAULT_MICROCOM is not set\n# CONFIG_BUSYBOX_DEFAULT_MIM is not set\n# CONFIG_BUSYBOX_DEFAULT_MT is not set\n# CONFIG_BUSYBOX_DEFAULT_NANDWRITE is not set\n# CONFIG_BUSYBOX_DEFAULT_NANDDUMP is not set\n# CONFIG_BUSYBOX_DEFAULT_PARTPROBE is not set\n# CONFIG_BUSYBOX_DEFAULT_RAIDAUTORUN is not set\n# CONFIG_BUSYBOX_DEFAULT_READAHEAD is not set\n# CONFIG_BUSYBOX_DEFAULT_RFKILL is not set\n# CONFIG_BUSYBOX_DEFAULT_RUNLEVEL is not set\n# CONFIG_BUSYBOX_DEFAULT_RX is not set\n# CONFIG_BUSYBOX_DEFAULT_SETFATTR is not set\n# CONFIG_BUSYBOX_DEFAULT_SETSERIAL is not set\nCONFIG_BUSYBOX_DEFAULT_STRINGS=y\nCONFIG_BUSYBOX_DEFAULT_TIME=y\n# CONFIG_BUSYBOX_DEFAULT_TS is not set\n# CONFIG_BUSYBOX_DEFAULT_TTYSIZE is not set\n# CONFIG_BUSYBOX_DEFAULT_UBIATTACH is not set\n# CONFIG_BUSYBOX_DEFAULT_UBIDETACH is not set\n# CONFIG_BUSYBOX_DEFAULT_UBIMKVOL is not set\n# CONFIG_BUSYBOX_DEFAULT_UBIRMVOL is not set\n# CONFIG_BUSYBOX_DEFAULT_UBIRSVOL is not set\n# CONFIG_BUSYBOX_DEFAULT_UBIUPDATEVOL is not set\n# CONFIG_BUSYBOX_DEFAULT_UBIRENAME is not set\n# CONFIG_BUSYBOX_DEFAULT_VOLNAME is not set\n# CONFIG_BUSYBOX_DEFAULT_WATCHDOG is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_WATCHDOG_OPEN_TWICE is not set\nCONFIG_BUSYBOX_DEFAULT_FEATURE_IPV6=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_UNIX_LOCAL is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_PREFER_IPV4_ADDRESS is not set\nCONFIG_BUSYBOX_DEFAULT_VERBOSE_RESOLUTION_ERRORS=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_TLS_SHA1 is not set\n# CONFIG_BUSYBOX_DEFAULT_ARP is not set\n# CONFIG_BUSYBOX_DEFAULT_ARPING is not set\nCONFIG_BUSYBOX_DEFAULT_BRCTL=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_BRCTL_FANCY=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_BRCTL_SHOW=y\n# CONFIG_BUSYBOX_DEFAULT_DNSD is not set\n# CONFIG_BUSYBOX_DEFAULT_ETHER_WAKE is not set\n# CONFIG_BUSYBOX_DEFAULT_FTPD is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_FTPD_WRITE is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_FTPD_ACCEPT_BROKEN_LIST is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_FTPD_AUTHENTICATION is not set\n# CONFIG_BUSYBOX_DEFAULT_FTPGET is not set\n# CONFIG_BUSYBOX_DEFAULT_FTPPUT is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_FTPGETPUT_LONG_OPTIONS is not set\n# CONFIG_BUSYBOX_DEFAULT_HOSTNAME is not set\n# CONFIG_BUSYBOX_DEFAULT_DNSDOMAINNAME is not set\n# CONFIG_BUSYBOX_DEFAULT_HTTPD is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_HTTPD_RANGES is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_HTTPD_SETUID is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_HTTPD_BASIC_AUTH is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_HTTPD_AUTH_MD5 is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_HTTPD_CGI is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_HTTPD_CONFIG_WITH_SCRIPT_INTERPR is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_HTTPD_SET_REMOTE_PORT_TO_ENV is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_HTTPD_ENCODE_URL_STR is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_HTTPD_ERROR_PAGES is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_HTTPD_PROXY is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_HTTPD_GZIP is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_HTTPD_ETAG is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_HTTPD_LAST_MODIFIED is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_HTTPD_DATE is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_HTTPD_ACL_IP is not set\nCONFIG_BUSYBOX_DEFAULT_IFCONFIG=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_IFCONFIG_STATUS=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_IFCONFIG_SLIP is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_IFCONFIG_MEMSTART_IOADDR_IRQ is not set\nCONFIG_BUSYBOX_DEFAULT_FEATURE_IFCONFIG_HW=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_IFCONFIG_BROADCAST_PLUS=y\n# CONFIG_BUSYBOX_DEFAULT_IFENSLAVE is not set\n# CONFIG_BUSYBOX_DEFAULT_IFPLUGD is not set\n# CONFIG_BUSYBOX_DEFAULT_IFUP is not set\n# CONFIG_BUSYBOX_DEFAULT_IFDOWN is not set\nCONFIG_BUSYBOX_DEFAULT_IFUPDOWN_IFSTATE_PATH=\"\"\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_IFUPDOWN_IP is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_IFUPDOWN_IPV4 is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_IFUPDOWN_IPV6 is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_IFUPDOWN_MAPPING is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_IFUPDOWN_EXTERNAL_DHCP is not set\n# CONFIG_BUSYBOX_DEFAULT_INETD is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_INETD_SUPPORT_BUILTIN_ECHO is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_INETD_SUPPORT_BUILTIN_DISCARD is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_INETD_SUPPORT_BUILTIN_TIME is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_INETD_SUPPORT_BUILTIN_DAYTIME is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_INETD_SUPPORT_BUILTIN_CHARGEN is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_INETD_RPC is not set\nCONFIG_BUSYBOX_DEFAULT_IP=y\n# CONFIG_BUSYBOX_DEFAULT_IPADDR is not set\n# CONFIG_BUSYBOX_DEFAULT_IPLINK is not set\n# CONFIG_BUSYBOX_DEFAULT_IPROUTE is not set\n# CONFIG_BUSYBOX_DEFAULT_IPTUNNEL is not set\n# CONFIG_BUSYBOX_DEFAULT_IPRULE is not set\n# CONFIG_BUSYBOX_DEFAULT_IPNEIGH is not set\nCONFIG_BUSYBOX_DEFAULT_FEATURE_IP_ADDRESS=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_IP_LINK=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_IP_ROUTE=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_IP_ROUTE_DIR=\"/etc/iproute2\"\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_IP_TUNNEL is not set\nCONFIG_BUSYBOX_DEFAULT_FEATURE_IP_RULE=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_IP_NEIGH=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_IP_RARE_PROTOCOLS is not set\n# CONFIG_BUSYBOX_DEFAULT_IPCALC is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_IPCALC_LONG_OPTIONS is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_IPCALC_FANCY is not set\n# CONFIG_BUSYBOX_DEFAULT_FAKEIDENTD is not set\n# CONFIG_BUSYBOX_DEFAULT_NAMEIF is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_NAMEIF_EXTENDED is not set\n# CONFIG_BUSYBOX_DEFAULT_NBDCLIENT is not set\nCONFIG_BUSYBOX_DEFAULT_NC=y\n# CONFIG_BUSYBOX_DEFAULT_NETCAT is not set\n# CONFIG_BUSYBOX_DEFAULT_NC_SERVER is not set\n# CONFIG_BUSYBOX_DEFAULT_NC_EXTRA is not set\n# CONFIG_BUSYBOX_DEFAULT_NC_110_COMPAT is not set\nCONFIG_BUSYBOX_DEFAULT_NETMSG=y\nCONFIG_BUSYBOX_DEFAULT_NETSTAT=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_NETSTAT_WIDE=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_NETSTAT_PRG=y\nCONFIG_BUSYBOX_DEFAULT_NSLOOKUP=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_NSLOOKUP_BIG=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_NSLOOKUP_LONG_OPTIONS is not set\nCONFIG_BUSYBOX_DEFAULT_NTPD=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_NTPD_SERVER=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_NTPD_CONF is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_NTP_AUTH is not set\nCONFIG_BUSYBOX_DEFAULT_PING=y\nCONFIG_BUSYBOX_DEFAULT_PING6=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_FANCY_PING=y\n# CONFIG_BUSYBOX_DEFAULT_PSCAN is not set\nCONFIG_BUSYBOX_DEFAULT_ROUTE=y\n# CONFIG_BUSYBOX_DEFAULT_SLATTACH is not set\n# CONFIG_BUSYBOX_DEFAULT_SSL_CLIENT is not set\n# CONFIG_BUSYBOX_DEFAULT_TC is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_TC_INGRESS is not set\n# CONFIG_BUSYBOX_DEFAULT_TCPSVD is not set\n# CONFIG_BUSYBOX_DEFAULT_UDPSVD is not set\n# CONFIG_BUSYBOX_DEFAULT_TELNET is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_TELNET_TTYPE is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_TELNET_AUTOLOGIN is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_TELNET_WIDTH is not set\n# CONFIG_BUSYBOX_DEFAULT_TELNETD is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_TELNETD_STANDALONE is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_TELNETD_INETD_WAIT is not set\n# CONFIG_BUSYBOX_DEFAULT_TFTP is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_TFTP_PROGRESS_BAR is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_TFTP_HPA_COMPAT is not set\n# CONFIG_BUSYBOX_DEFAULT_TFTPD is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_TFTP_GET is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_TFTP_PUT is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_TFTP_BLOCKSIZE is not set\n# CONFIG_BUSYBOX_DEFAULT_TFTP_DEBUG is not set\n# CONFIG_BUSYBOX_DEFAULT_TLS is not set\nCONFIG_BUSYBOX_DEFAULT_TRACEROUTE=y\nCONFIG_BUSYBOX_DEFAULT_TRACEROUTE6=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_TRACEROUTE_VERBOSE=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_TRACEROUTE_USE_ICMP is not set\n# CONFIG_BUSYBOX_DEFAULT_TUNCTL is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_TUNCTL_UG is not set\n# CONFIG_BUSYBOX_DEFAULT_VCONFIG is not set\n# CONFIG_BUSYBOX_DEFAULT_WGET is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_WGET_LONG_OPTIONS is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_WGET_STATUSBAR is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_WGET_FTP is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_WGET_AUTHENTICATION is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_WGET_TIMEOUT is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_WGET_HTTPS is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_WGET_OPENSSL is not set\n# CONFIG_BUSYBOX_DEFAULT_WHOIS is not set\n# CONFIG_BUSYBOX_DEFAULT_ZCIP is not set\n# CONFIG_BUSYBOX_DEFAULT_UDHCPD is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_UDHCPD_BASE_IP_ON_MAC is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_UDHCPD_WRITE_LEASES_EARLY is not set\nCONFIG_BUSYBOX_DEFAULT_DHCPD_LEASES_FILE=\"\"\n# CONFIG_BUSYBOX_DEFAULT_DUMPLEASES is not set\n# CONFIG_BUSYBOX_DEFAULT_DHCPRELAY is not set\nCONFIG_BUSYBOX_DEFAULT_UDHCPC=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_UDHCPC_ARPING is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_UDHCPC_SANITIZEOPT is not set\nCONFIG_BUSYBOX_DEFAULT_UDHCPC_DEFAULT_SCRIPT=\"/usr/share/udhcpc/default.script\"\n# CONFIG_BUSYBOX_DEFAULT_UDHCPC6 is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_UDHCPC6_RFC3646 is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_UDHCPC6_RFC4704 is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_UDHCPC6_RFC4833 is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_UDHCPC6_RFC5970 is not set\nCONFIG_BUSYBOX_DEFAULT_UDHCPC_DEFAULT_INTERFACE=\"\"\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_UDHCP_PORT is not set\nCONFIG_BUSYBOX_DEFAULT_UDHCP_DEBUG=0\nCONFIG_BUSYBOX_DEFAULT_UDHCPC_SLACK_FOR_BUGGY_SERVERS=80\nCONFIG_BUSYBOX_DEFAULT_FEATURE_UDHCP_RFC3397=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_UDHCP_8021Q is not set\nCONFIG_BUSYBOX_DEFAULT_IFUPDOWN_UDHCPC_CMD_OPTIONS=\"\"\n# CONFIG_BUSYBOX_DEFAULT_LPD is not set\n# CONFIG_BUSYBOX_DEFAULT_LPR is not set\n# CONFIG_BUSYBOX_DEFAULT_LPQ is not set\n# CONFIG_BUSYBOX_DEFAULT_MAKEMIME is not set\n# CONFIG_BUSYBOX_DEFAULT_POPMAILDIR is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_POPMAILDIR_DELIVERY is not set\n# CONFIG_BUSYBOX_DEFAULT_REFORMIME is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_REFORMIME_COMPAT is not set\n# CONFIG_BUSYBOX_DEFAULT_SENDMAIL is not set\nCONFIG_BUSYBOX_DEFAULT_FEATURE_MIME_CHARSET=\"\"\nCONFIG_BUSYBOX_DEFAULT_FREE=y\n# CONFIG_BUSYBOX_DEFAULT_FUSER is not set\n# CONFIG_BUSYBOX_DEFAULT_IOSTAT is not set\nCONFIG_BUSYBOX_DEFAULT_KILL=y\nCONFIG_BUSYBOX_DEFAULT_KILLALL=y\n# CONFIG_BUSYBOX_DEFAULT_KILLALL5 is not set\n# CONFIG_BUSYBOX_DEFAULT_LSOF is not set\n# CONFIG_BUSYBOX_DEFAULT_MPSTAT is not set\n# CONFIG_BUSYBOX_DEFAULT_NMETER is not set\nCONFIG_BUSYBOX_DEFAULT_PGREP=y\n# CONFIG_BUSYBOX_DEFAULT_PKILL is not set\nCONFIG_BUSYBOX_DEFAULT_PIDOF=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_PIDOF_SINGLE is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_PIDOF_OMIT is not set\n# CONFIG_BUSYBOX_DEFAULT_PMAP is not set\n# CONFIG_BUSYBOX_DEFAULT_POWERTOP is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_POWERTOP_INTERACTIVE is not set\nCONFIG_BUSYBOX_DEFAULT_PS=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_PS_WIDE=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_PS_LONG is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_PS_TIME is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_PS_UNUSUAL_SYSTEMS is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_PS_ADDITIONAL_COLUMNS is not set\n# CONFIG_BUSYBOX_DEFAULT_PSTREE is not set\n# CONFIG_BUSYBOX_DEFAULT_PWDX is not set\n# CONFIG_BUSYBOX_DEFAULT_SMEMCAP is not set\nCONFIG_BUSYBOX_DEFAULT_BB_SYSCTL=y\nCONFIG_BUSYBOX_DEFAULT_TOP=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_TOP_INTERACTIVE is not set\nCONFIG_BUSYBOX_DEFAULT_FEATURE_TOP_CPU_USAGE_PERCENTAGE=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_TOP_CPU_GLOBAL_PERCENTS=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_TOP_SMP_CPU is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_TOP_DECIMALS is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_TOP_SMP_PROCESS is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_TOPMEM is not set\nCONFIG_BUSYBOX_DEFAULT_UPTIME=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_UPTIME_UTMP_SUPPORT is not set\n# CONFIG_BUSYBOX_DEFAULT_WATCH is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_SHOW_THREADS is not set\n# CONFIG_BUSYBOX_DEFAULT_CHPST is not set\n# CONFIG_BUSYBOX_DEFAULT_SETUIDGID is not set\n# CONFIG_BUSYBOX_DEFAULT_ENVUIDGID is not set\n# CONFIG_BUSYBOX_DEFAULT_ENVDIR is not set\n# CONFIG_BUSYBOX_DEFAULT_SOFTLIMIT is not set\n# CONFIG_BUSYBOX_DEFAULT_RUNSV is not set\n# CONFIG_BUSYBOX_DEFAULT_RUNSVDIR is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_RUNSVDIR_LOG is not set\n# CONFIG_BUSYBOX_DEFAULT_SV is not set\nCONFIG_BUSYBOX_DEFAULT_SV_DEFAULT_SERVICE_DIR=\"\"\n# CONFIG_BUSYBOX_DEFAULT_SVC is not set\n# CONFIG_BUSYBOX_DEFAULT_SVOK is not set\n# CONFIG_BUSYBOX_DEFAULT_SVLOGD is not set\n# CONFIG_BUSYBOX_DEFAULT_CHCON is not set\n# CONFIG_BUSYBOX_DEFAULT_GETENFORCE is not set\n# CONFIG_BUSYBOX_DEFAULT_GETSEBOOL is not set\n# CONFIG_BUSYBOX_DEFAULT_LOAD_POLICY is not set\n# CONFIG_BUSYBOX_DEFAULT_MATCHPATHCON is not set\n# CONFIG_BUSYBOX_DEFAULT_RUNCON is not set\n# CONFIG_BUSYBOX_DEFAULT_SELINUXENABLED is not set\n# CONFIG_BUSYBOX_DEFAULT_SESTATUS is not set\n# CONFIG_BUSYBOX_DEFAULT_SETENFORCE is not set\n# CONFIG_BUSYBOX_DEFAULT_SETFILES is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_SETFILES_CHECK_OPTION is not set\n# CONFIG_BUSYBOX_DEFAULT_RESTORECON is not set\n# CONFIG_BUSYBOX_DEFAULT_SETSEBOOL is not set\nCONFIG_BUSYBOX_DEFAULT_SH_IS_ASH=y\n# CONFIG_BUSYBOX_DEFAULT_SH_IS_HUSH is not set\n# CONFIG_BUSYBOX_DEFAULT_SH_IS_NONE is not set\n# CONFIG_BUSYBOX_DEFAULT_BASH_IS_ASH is not set\n# CONFIG_BUSYBOX_DEFAULT_BASH_IS_HUSH is not set\nCONFIG_BUSYBOX_DEFAULT_BASH_IS_NONE=y\nCONFIG_BUSYBOX_DEFAULT_SHELL_ASH=y\nCONFIG_BUSYBOX_DEFAULT_ASH=y\n# CONFIG_BUSYBOX_DEFAULT_ASH_OPTIMIZE_FOR_SIZE is not set\nCONFIG_BUSYBOX_DEFAULT_ASH_INTERNAL_GLOB=y\nCONFIG_BUSYBOX_DEFAULT_ASH_BASH_COMPAT=y\n# CONFIG_BUSYBOX_DEFAULT_ASH_BASH_SOURCE_CURDIR is not set\n# CONFIG_BUSYBOX_DEFAULT_ASH_BASH_NOT_FOUND_HOOK is not set\nCONFIG_BUSYBOX_DEFAULT_ASH_JOB_CONTROL=y\nCONFIG_BUSYBOX_DEFAULT_ASH_ALIAS=y\n# CONFIG_BUSYBOX_DEFAULT_ASH_RANDOM_SUPPORT is not set\nCONFIG_BUSYBOX_DEFAULT_ASH_EXPAND_PRMT=y\n# CONFIG_BUSYBOX_DEFAULT_ASH_IDLE_TIMEOUT is not set\n# CONFIG_BUSYBOX_DEFAULT_ASH_MAIL is not set\nCONFIG_BUSYBOX_DEFAULT_ASH_ECHO=y\nCONFIG_BUSYBOX_DEFAULT_ASH_PRINTF=y\nCONFIG_BUSYBOX_DEFAULT_ASH_TEST=y\n# CONFIG_BUSYBOX_DEFAULT_ASH_HELP is not set\nCONFIG_BUSYBOX_DEFAULT_ASH_GETOPTS=y\nCONFIG_BUSYBOX_DEFAULT_ASH_CMDCMD=y\n# CONFIG_BUSYBOX_DEFAULT_CTTYHACK is not set\n# CONFIG_BUSYBOX_DEFAULT_HUSH is not set\n# CONFIG_BUSYBOX_DEFAULT_SHELL_HUSH is not set\n# CONFIG_BUSYBOX_DEFAULT_HUSH_BASH_COMPAT is not set\n# CONFIG_BUSYBOX_DEFAULT_HUSH_BRACE_EXPANSION is not set\n# CONFIG_BUSYBOX_DEFAULT_HUSH_BASH_SOURCE_CURDIR is not set\n# CONFIG_BUSYBOX_DEFAULT_HUSH_LINENO_VAR is not set\n# CONFIG_BUSYBOX_DEFAULT_HUSH_INTERACTIVE is not set\n# CONFIG_BUSYBOX_DEFAULT_HUSH_SAVEHISTORY is not set\n# CONFIG_BUSYBOX_DEFAULT_HUSH_JOB is not set\n# CONFIG_BUSYBOX_DEFAULT_HUSH_TICK is not set\n# CONFIG_BUSYBOX_DEFAULT_HUSH_IF is not set\n# CONFIG_BUSYBOX_DEFAULT_HUSH_LOOPS is not set\n# CONFIG_BUSYBOX_DEFAULT_HUSH_CASE is not set\n# CONFIG_BUSYBOX_DEFAULT_HUSH_FUNCTIONS is not set\n# CONFIG_BUSYBOX_DEFAULT_HUSH_LOCAL is not set\n# CONFIG_BUSYBOX_DEFAULT_HUSH_RANDOM_SUPPORT is not set\n# CONFIG_BUSYBOX_DEFAULT_HUSH_MODE_X is not set\n# CONFIG_BUSYBOX_DEFAULT_HUSH_ECHO is not set\n# CONFIG_BUSYBOX_DEFAULT_HUSH_PRINTF is not set\n# CONFIG_BUSYBOX_DEFAULT_HUSH_TEST is not set\n# CONFIG_BUSYBOX_DEFAULT_HUSH_HELP is not set\n# CONFIG_BUSYBOX_DEFAULT_HUSH_EXPORT is not set\n# CONFIG_BUSYBOX_DEFAULT_HUSH_EXPORT_N is not set\n# CONFIG_BUSYBOX_DEFAULT_HUSH_READONLY is not set\n# CONFIG_BUSYBOX_DEFAULT_HUSH_KILL is not set\n# CONFIG_BUSYBOX_DEFAULT_HUSH_WAIT is not set\n# CONFIG_BUSYBOX_DEFAULT_HUSH_COMMAND is not set\n# CONFIG_BUSYBOX_DEFAULT_HUSH_TRAP is not set\n# CONFIG_BUSYBOX_DEFAULT_HUSH_TYPE is not set\n# CONFIG_BUSYBOX_DEFAULT_HUSH_TIMES is not set\n# CONFIG_BUSYBOX_DEFAULT_HUSH_READ is not set\n# CONFIG_BUSYBOX_DEFAULT_HUSH_SET is not set\n# CONFIG_BUSYBOX_DEFAULT_HUSH_UNSET is not set\n# CONFIG_BUSYBOX_DEFAULT_HUSH_ULIMIT is not set\n# CONFIG_BUSYBOX_DEFAULT_HUSH_UMASK is not set\n# CONFIG_BUSYBOX_DEFAULT_HUSH_GETOPTS is not set\n# CONFIG_BUSYBOX_DEFAULT_HUSH_MEMLEAK is not set\nCONFIG_BUSYBOX_DEFAULT_FEATURE_SH_MATH=y\nCONFIG_BUSYBOX_DEFAULT_FEATURE_SH_MATH_64=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_SH_MATH_BASE is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_SH_EXTRA_QUIET is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_SH_STANDALONE is not set\nCONFIG_BUSYBOX_DEFAULT_FEATURE_SH_NOFORK=y\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_SH_READ_FRAC is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_SH_HISTFILESIZE is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_SH_EMBEDDED_SCRIPTS is not set\n# CONFIG_BUSYBOX_DEFAULT_KLOGD is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_KLOGD_KLOGCTL is not set\nCONFIG_BUSYBOX_DEFAULT_LOGGER=y\n# CONFIG_BUSYBOX_DEFAULT_LOGREAD is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_LOGREAD_REDUCED_LOCKING is not set\n# CONFIG_BUSYBOX_DEFAULT_SYSLOGD is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_ROTATE_LOGFILE is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_REMOTE_LOG is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_SYSLOGD_DUP is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_SYSLOGD_CFG is not set\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_SYSLOGD_PRECISE_TIMESTAMPS is not set\nCONFIG_BUSYBOX_DEFAULT_FEATURE_SYSLOGD_READ_BUFFER_SIZE=0\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_IPC_SYSLOG is not set\nCONFIG_BUSYBOX_DEFAULT_FEATURE_IPC_SYSLOG_BUFFER_SIZE=0\n# CONFIG_BUSYBOX_DEFAULT_FEATURE_KMSG_SYSLOG is not set\n# CONFIG_BUSYBOX_CONFIG_IP is not set\n# CONFIG_BUSYBOX_CONFIG_FEATURE_IP_LINK is not set\n# CONFIG_PACKAGE_busybox-selinux is not set\nCONFIG_PACKAGE_ca-bundle=y\nCONFIG_PACKAGE_ca-certificates=y\nCONFIG_PACKAGE_dnsmasq=y\n# CONFIG_PACKAGE_dnsmasq-dhcpv6 is not set\n# CONFIG_PACKAGE_dnsmasq-full is not set\nCONFIG_PACKAGE_dropbear=y\n\n#\n# Configuration\n#\nCONFIG_DROPBEAR_CURVE25519=y\n# CONFIG_DROPBEAR_ECC is not set\nCONFIG_DROPBEAR_ED25519=y\nCONFIG_DROPBEAR_CHACHA20POLY1305=y\n# CONFIG_DROPBEAR_ZLIB is not set\nCONFIG_DROPBEAR_DBCLIENT=y\nCONFIG_DROPBEAR_DBCLIENT_AGENTFORWARD=y\nCONFIG_DROPBEAR_SCP=y\n# CONFIG_DROPBEAR_ASKPASS is not set\nCONFIG_DROPBEAR_AGENTFORWARD=y\n# end of Configuration\n\n# CONFIG_PACKAGE_ead is not set\nCONFIG_PACKAGE_firewall=y\n# CONFIG_PACKAGE_firewall4 is not set\nCONFIG_PACKAGE_fstools=y\n# CONFIG_FSTOOLS_OVL_MOUNT_FULL_ACCESS_TIME is not set\n# CONFIG_FSTOOLS_OVL_MOUNT_COMPRESS_ZLIB is not set\nCONFIG_PACKAGE_fwtool=y\nCONFIG_PACKAGE_getrandom=y\nCONFIG_PACKAGE_jsonfilter=y\nCONFIG_PACKAGE_libatomic=y\nCONFIG_PACKAGE_libc=y\nCONFIG_PACKAGE_libgcc=y\n# CONFIG_PACKAGE_libgomp is not set\nCONFIG_PACKAGE_libpthread=y\nCONFIG_PACKAGE_librt=y\nCONFIG_PACKAGE_libstdcpp=y\nCONFIG_PACKAGE_logd=y\nCONFIG_PACKAGE_mtd=y\nCONFIG_PACKAGE_netifd=y\n# CONFIG_PACKAGE_nft-qos is not set\n# CONFIG_PACKAGE_om-watchdog is not set\nCONFIG_PACKAGE_openwrt-keyring=y\nCONFIG_PACKAGE_opkg=y\nCONFIG_PACKAGE_procd=y\n\n#\n# Configuration\n#\n# CONFIG_PROCD_SHOW_BOOT is not set\n# CONFIG_PROCD_ZRAM_TMPFS is not set\n# end of Configuration\n\nCONFIG_PACKAGE_procd-seccomp=y\n# CONFIG_PACKAGE_procd-selinux is not set\n# CONFIG_PACKAGE_procd-ujail is not set\n# CONFIG_PACKAGE_procd-ujail-console is not set\nCONFIG_PACKAGE_qos-scripts=y\n# CONFIG_PACKAGE_refpolicy is not set\nCONFIG_PACKAGE_resolveip=y\nCONFIG_PACKAGE_rpcd=y\nCONFIG_PACKAGE_rpcd-mod-file=y\nCONFIG_PACKAGE_rpcd-mod-iwinfo=y\n# CONFIG_PACKAGE_rpcd-mod-rpcsys is not set\n# CONFIG_PACKAGE_selinux-policy is not set\n# CONFIG_PACKAGE_snapshot-tool is not set\nCONFIG_PACKAGE_sqm-scripts=y\n# CONFIG_PACKAGE_sqm-scripts-extra is not set\n# CONFIG_PACKAGE_swconfig is not set\nCONFIG_PACKAGE_ubox=y\nCONFIG_PACKAGE_ubus=y\nCONFIG_PACKAGE_ubusd=y\n# CONFIG_PACKAGE_ucert is not set\n# CONFIG_PACKAGE_ucert-full is not set\nCONFIG_PACKAGE_uci=y\nCONFIG_PACKAGE_urandom-seed=y\nCONFIG_PACKAGE_urngd=y\nCONFIG_PACKAGE_usign=y\n# CONFIG_PACKAGE_uxc is not set\n# CONFIG_PACKAGE_wireless-tools is not set\n# CONFIG_PACKAGE_zram-swap is not set\n# end of Base system\n\n#\n# Administration\n#\n\n#\n# Zabbix\n#\n# CONFIG_PACKAGE_zabbix-agentd is not set\n\n#\n# SSL support\n#\n# CONFIG_ZABBIX_OPENSSL is not set\n# CONFIG_ZABBIX_GNUTLS is not set\nCONFIG_ZABBIX_NOSSL=y\n# CONFIG_PACKAGE_zabbix-extra-mac80211 is not set\n# CONFIG_PACKAGE_zabbix-extra-network is not set\n# CONFIG_PACKAGE_zabbix-extra-wifi is not set\n# CONFIG_PACKAGE_zabbix-get is not set\n# CONFIG_PACKAGE_zabbix-proxy is not set\n# CONFIG_PACKAGE_zabbix-sender is not set\n# CONFIG_PACKAGE_zabbix-server is not set\n\n#\n# Database Software\n#\n# CONFIG_ZABBIX_MYSQL is not set\nCONFIG_ZABBIX_POSTGRESQL=y\n# CONFIG_PACKAGE_zabbix-server-frontend is not set\n# end of Zabbix\n\n#\n# openwisp\n#\n# CONFIG_PACKAGE_openwisp-config-mbedtls is not set\n# CONFIG_PACKAGE_openwisp-config-nossl is not set\n# CONFIG_PACKAGE_openwisp-config-openssl is not set\n# CONFIG_PACKAGE_openwisp-config-wolfssl is not set\n# end of openwisp\n\n# CONFIG_PACKAGE_atop is not set\n# CONFIG_PACKAGE_backuppc is not set\n# CONFIG_PACKAGE_debian-archive-keyring is not set\n# CONFIG_PACKAGE_debootstrap is not set\n# CONFIG_PACKAGE_gkrellmd is not set\nCONFIG_PACKAGE_htop=y\n# CONFIG_HTOP_LMSENSORS is not set\n# CONFIG_PACKAGE_ipmitool is not set\n# CONFIG_PACKAGE_monit is not set\n# CONFIG_PACKAGE_monit-nossl is not set\n# CONFIG_PACKAGE_muninlite is not set\n# CONFIG_PACKAGE_netatop is not set\n# CONFIG_PACKAGE_netdata is not set\n# CONFIG_PACKAGE_nyx is not set\n# CONFIG_PACKAGE_rsyslog is not set\n# CONFIG_PACKAGE_schroot is not set\n\n#\n# Configuration\n#\n# CONFIG_SCHROOT_BTRFS is not set\n# CONFIG_SCHROOT_LOOPBACK is not set\n# CONFIG_SCHROOT_LVM is not set\n# CONFIG_SCHROOT_UUID is not set\n# end of Configuration\n\n# CONFIG_PACKAGE_sudo is not set\n# CONFIG_PACKAGE_syslog-ng is not set\n# end of Administration\n\n#\n# Boot Loaders\n#\nCONFIG_PACKAGE_arm-trusted-firmware-rk3328=y\nCONFIG_PACKAGE_arm-trusted-firmware-rockchip=y\nCONFIG_PACKAGE_u-boot-orangepi-r1-plus-rk3328=y\n# end of Boot Loaders\n\n#\n# Development\n#\n\n#\n# Libraries\n#\n# CONFIG_PACKAGE_libncurses-dev is not set\n# CONFIG_PACKAGE_libxml2-dev is not set\n# CONFIG_PACKAGE_zlib-dev is not set\n# end of Libraries\n\n# CONFIG_PACKAGE_ar is not set\n# CONFIG_PACKAGE_autoconf is not set\n# CONFIG_PACKAGE_automake is not set\n# CONFIG_PACKAGE_binutils is not set\n# CONFIG_PACKAGE_delve is not set\n# CONFIG_PACKAGE_diffutils is not set\n# CONFIG_PACKAGE_gcc is not set\n# CONFIG_PACKAGE_gdb is not set\n# CONFIG_PACKAGE_gdbserver is not set\n# CONFIG_PACKAGE_gitlab-runner is not set\n# CONFIG_PACKAGE_libtool-bin is not set\n# CONFIG_PACKAGE_lpc21isp is not set\n# CONFIG_PACKAGE_lttng-tools is not set\n# CONFIG_PACKAGE_m4 is not set\n# CONFIG_PACKAGE_make is not set\n# CONFIG_PACKAGE_objdump is not set\n# CONFIG_PACKAGE_packr is not set\n# CONFIG_PACKAGE_patch is not set\n# CONFIG_PACKAGE_pkg-config is not set\n# CONFIG_PACKAGE_pkgconf is not set\n# CONFIG_PACKAGE_statik is not set\n# CONFIG_PACKAGE_trace-cmd is not set\n# CONFIG_PACKAGE_trace-cmd-extra is not set\n# CONFIG_PACKAGE_valgrind is not set\n# end of Development\n\n#\n# Extra packages\n#\n# CONFIG_PACKAGE_jose is not set\nCONFIG_PACKAGE_libiwinfo-data=y\n# CONFIG_PACKAGE_libjose is not set\n# CONFIG_PACKAGE_nginx is not set\n# CONFIG_PACKAGE_nginx-mod-luci-ssl is not set\n# CONFIG_PACKAGE_nginx-util is not set\n# CONFIG_PACKAGE_rclone-config is not set\n# CONFIG_PACKAGE_tang is not set\n# end of Extra packages\n\n#\n# Firmware\n#\n\n#\n# ath10k Board-Specific Overrides\n#\n# end of ath10k Board-Specific Overrides\n\n# CONFIG_PACKAGE_aircard-pcmcia-firmware is not set\n# CONFIG_PACKAGE_amdgpu-firmware is not set\n# CONFIG_PACKAGE_ar3k-firmware is not set\n# CONFIG_PACKAGE_ath10k-board-qca4019 is not set\n# CONFIG_PACKAGE_ath10k-board-qca9377 is not set\n# CONFIG_PACKAGE_ath10k-board-qca9887 is not set\n# CONFIG_PACKAGE_ath10k-board-qca9888 is not set\n# CONFIG_PACKAGE_ath10k-board-qca988x is not set\n# CONFIG_PACKAGE_ath10k-board-qca9984 is not set\n# CONFIG_PACKAGE_ath10k-board-qca99x0 is not set\n# CONFIG_PACKAGE_ath10k-board-qca99x0-2g is not set\n# CONFIG_PACKAGE_ath10k-board-qca99x0-5g is not set\n# CONFIG_PACKAGE_ath10k-firmware-qca4019 is not set\n# CONFIG_PACKAGE_ath10k-firmware-qca4019-ct is not set\n# CONFIG_PACKAGE_ath10k-firmware-qca4019-ct-full-htt is not set\n# CONFIG_PACKAGE_ath10k-firmware-qca4019-ct-htt is not set\n# CONFIG_PACKAGE_ath10k-firmware-qca6174 is not set\n# CONFIG_PACKAGE_ath10k-firmware-qca9377 is not set\n# CONFIG_PACKAGE_ath10k-firmware-qca9887 is not set\n# CONFIG_PACKAGE_ath10k-firmware-qca9887-ct is not set\n# CONFIG_PACKAGE_ath10k-firmware-qca9887-ct-full-htt is not set\n# CONFIG_PACKAGE_ath10k-firmware-qca9888 is not set\n# CONFIG_PACKAGE_ath10k-firmware-qca9888-ct is not set\n# CONFIG_PACKAGE_ath10k-firmware-qca9888-ct-full-htt is not set\n# CONFIG_PACKAGE_ath10k-firmware-qca9888-ct-htt is not set\n# CONFIG_PACKAGE_ath10k-firmware-qca988x is not set\n# CONFIG_PACKAGE_ath10k-firmware-qca988x-ct is not set\n# CONFIG_PACKAGE_ath10k-firmware-qca988x-ct-full-htt is not set\n# CONFIG_PACKAGE_ath10k-firmware-qca9984 is not set\n# CONFIG_PACKAGE_ath10k-firmware-qca9984-ct is not set\n# CONFIG_PACKAGE_ath10k-firmware-qca9984-ct-full-htt is not set\n# CONFIG_PACKAGE_ath10k-firmware-qca9984-ct-htt is not set\n# CONFIG_PACKAGE_ath10k-firmware-qca99x0 is not set\n# CONFIG_PACKAGE_ath10k-firmware-qca99x0-ct is not set\n# CONFIG_PACKAGE_ath10k-firmware-qca99x0-ct-full-htt is not set\n# CONFIG_PACKAGE_ath10k-firmware-qca99x0-ct-htt is not set\n# CONFIG_PACKAGE_ath6k-firmware is not set\n# CONFIG_PACKAGE_ath9k-htc-firmware is not set\n# CONFIG_PACKAGE_b43legacy-firmware is not set\n# CONFIG_PACKAGE_bnx2-firmware is not set\n# CONFIG_PACKAGE_bnx2x-firmware is not set\n# CONFIG_PACKAGE_brcmfmac-firmware-4329-sdio is not set\n# CONFIG_PACKAGE_brcmfmac-firmware-43430-sdio-rpi-3b is not set\n# CONFIG_PACKAGE_brcmfmac-firmware-43430-sdio-rpi-zero-w is not set\n# CONFIG_PACKAGE_brcmfmac-firmware-43430a0-sdio is not set\n# CONFIG_PACKAGE_brcmfmac-firmware-43455-sdio-rpi-3b-plus is not set\n# CONFIG_PACKAGE_brcmfmac-firmware-43455-sdio-rpi-4b is not set\n# CONFIG_PACKAGE_brcmfmac-firmware-43602a1-pcie is not set\n# CONFIG_PACKAGE_brcmfmac-firmware-4366b1-pcie is not set\n# CONFIG_PACKAGE_brcmfmac-firmware-4366c0-pcie is not set\n# CONFIG_PACKAGE_brcmfmac-firmware-usb is not set\n# CONFIG_PACKAGE_brcmsmac-firmware is not set\n# CONFIG_PACKAGE_carl9170-firmware is not set\n# CONFIG_PACKAGE_cypress-firmware-43012-sdio is not set\n# CONFIG_PACKAGE_cypress-firmware-43340-sdio is not set\n# CONFIG_PACKAGE_cypress-firmware-43362-sdio is not set\n# CONFIG_PACKAGE_cypress-firmware-4339-sdio is not set\n# CONFIG_PACKAGE_cypress-firmware-43430-sdio is not set\n# CONFIG_PACKAGE_cypress-firmware-43455-sdio is not set\n# CONFIG_PACKAGE_cypress-firmware-4354-sdio is not set\n# CONFIG_PACKAGE_cypress-firmware-4356-pcie is not set\n# CONFIG_PACKAGE_cypress-firmware-4356-sdio is not set\n# CONFIG_PACKAGE_cypress-firmware-43570-pcie is not set\n# CONFIG_PACKAGE_cypress-firmware-4359-pcie is not set\n# CONFIG_PACKAGE_cypress-firmware-4359-sdio is not set\n# CONFIG_PACKAGE_cypress-firmware-4373-sdio is not set\n# CONFIG_PACKAGE_cypress-firmware-4373-usb is not set\n# CONFIG_PACKAGE_cypress-firmware-54591-pcie is not set\n# CONFIG_PACKAGE_cypress-firmware-89459-pcie is not set\n# CONFIG_PACKAGE_e100-firmware is not set\n# CONFIG_PACKAGE_edgeport-firmware is not set\n# CONFIG_PACKAGE_eip197-mini-firmware is not set\n# CONFIG_PACKAGE_ibt-firmware is not set\n# CONFIG_PACKAGE_iwl3945-firmware is not set\n# CONFIG_PACKAGE_iwl4965-firmware is not set\n# CONFIG_PACKAGE_iwlwifi-firmware-ax200 is not set\n# CONFIG_PACKAGE_iwlwifi-firmware-iwl100 is not set\n# CONFIG_PACKAGE_iwlwifi-firmware-iwl1000 is not set\n# CONFIG_PACKAGE_iwlwifi-firmware-iwl105 is not set\n# CONFIG_PACKAGE_iwlwifi-firmware-iwl135 is not set\n# CONFIG_PACKAGE_iwlwifi-firmware-iwl2000 is not set\n# CONFIG_PACKAGE_iwlwifi-firmware-iwl2030 is not set\n# CONFIG_PACKAGE_iwlwifi-firmware-iwl3160 is not set\n# CONFIG_PACKAGE_iwlwifi-firmware-iwl3168 is not set\n# CONFIG_PACKAGE_iwlwifi-firmware-iwl5000 is not set\n# CONFIG_PACKAGE_iwlwifi-firmware-iwl5150 is not set\n# CONFIG_PACKAGE_iwlwifi-firmware-iwl6000g2 is not set\n# CONFIG_PACKAGE_iwlwifi-firmware-iwl6000g2a is not set\n# CONFIG_PACKAGE_iwlwifi-firmware-iwl6000g2b is not set\n# CONFIG_PACKAGE_iwlwifi-firmware-iwl6050 is not set\n# CONFIG_PACKAGE_iwlwifi-firmware-iwl7260 is not set\n# CONFIG_PACKAGE_iwlwifi-firmware-iwl7265 is not set\n# CONFIG_PACKAGE_iwlwifi-firmware-iwl7265d is not set\n# CONFIG_PACKAGE_iwlwifi-firmware-iwl8260c is not set\n# CONFIG_PACKAGE_iwlwifi-firmware-iwl8265 is not set\n# CONFIG_PACKAGE_iwlwifi-firmware-iwl9000 is not set\n# CONFIG_PACKAGE_iwlwifi-firmware-iwl9260 is not set\n# CONFIG_PACKAGE_libertas-sdio-firmware is not set\n# CONFIG_PACKAGE_libertas-spi-firmware is not set\n# CONFIG_PACKAGE_libertas-usb-firmware is not set\n# CONFIG_PACKAGE_mt7601u-firmware is not set\n# CONFIG_PACKAGE_mt7622bt-firmware is not set\n# CONFIG_PACKAGE_mwifiex-pcie-firmware is not set\n# CONFIG_PACKAGE_mwifiex-sdio-firmware is not set\n# CONFIG_PACKAGE_mwl8k-firmware is not set\n# CONFIG_PACKAGE_p54-pci-firmware is not set\n# CONFIG_PACKAGE_p54-spi-firmware is not set\n# CONFIG_PACKAGE_p54-usb-firmware is not set\n# CONFIG_PACKAGE_prism54-firmware is not set\n# CONFIG_PACKAGE_r8169-firmware is not set\n# CONFIG_PACKAGE_radeon-firmware is not set\n# CONFIG_PACKAGE_rs9113-firmware is not set\n# CONFIG_PACKAGE_rt2800-pci-firmware is not set\n# CONFIG_PACKAGE_rt2800-usb-firmware is not set\n# CONFIG_PACKAGE_rt61-pci-firmware is not set\n# CONFIG_PACKAGE_rt73-usb-firmware is not set\nCONFIG_PACKAGE_rtl8188eu-firmware=y\n# CONFIG_PACKAGE_rtl8192ce-firmware is not set\n# CONFIG_PACKAGE_rtl8192cu-firmware is not set\n# CONFIG_PACKAGE_rtl8192de-firmware is not set\n# CONFIG_PACKAGE_rtl8192eu-firmware is not set\n# CONFIG_PACKAGE_rtl8192se-firmware is not set\n# CONFIG_PACKAGE_rtl8192su-firmware is not set\nCONFIG_PACKAGE_rtl8723au-firmware=y\n# CONFIG_PACKAGE_rtl8723bs-firmware is not set\nCONFIG_PACKAGE_rtl8723bu-firmware=y\nCONFIG_PACKAGE_rtl8821ae-firmware=y\n# CONFIG_PACKAGE_rtl8822be-firmware is not set\n# CONFIG_PACKAGE_rtl8822ce-firmware is not set\n# CONFIG_PACKAGE_ti-3410-firmware is not set\n# CONFIG_PACKAGE_ti-5052-firmware is not set\n# CONFIG_PACKAGE_wil6210-firmware is not set\nCONFIG_PACKAGE_wireless-regdb=y\n# CONFIG_PACKAGE_wl12xx-firmware is not set\n# CONFIG_PACKAGE_wl18xx-firmware is not set\n# end of Firmware\n\n#\n# Fonts\n#\n\n#\n# DejaVu\n#\n# CONFIG_PACKAGE_dejavu-fonts-ttf-DejaVuMathTeXGyre is not set\n# CONFIG_PACKAGE_dejavu-fonts-ttf-DejaVuSans is not set\n# CONFIG_PACKAGE_dejavu-fonts-ttf-DejaVuSans-Bold is not set\n# CONFIG_PACKAGE_dejavu-fonts-ttf-DejaVuSans-BoldOblique is not set\n# CONFIG_PACKAGE_dejavu-fonts-ttf-DejaVuSans-ExtraLight is not set\n# CONFIG_PACKAGE_dejavu-fonts-ttf-DejaVuSans-Oblique is not set\n# CONFIG_PACKAGE_dejavu-fonts-ttf-DejaVuSansCondensed is not set\n# CONFIG_PACKAGE_dejavu-fonts-ttf-DejaVuSansCondensed-Bold is not set\n# CONFIG_PACKAGE_dejavu-fonts-ttf-DejaVuSansCondensed-BoldOblique is not set\n# CONFIG_PACKAGE_dejavu-fonts-ttf-DejaVuSansCondensed-Oblique is not set\n# CONFIG_PACKAGE_dejavu-fonts-ttf-DejaVuSansMono is not set\n# CONFIG_PACKAGE_dejavu-fonts-ttf-DejaVuSansMono-Bold is not set\n# CONFIG_PACKAGE_dejavu-fonts-ttf-DejaVuSansMono-BoldOblique is not set\n# CONFIG_PACKAGE_dejavu-fonts-ttf-DejaVuSansMono-Oblique is not set\n# CONFIG_PACKAGE_dejavu-fonts-ttf-DejaVuSerif is not set\n# CONFIG_PACKAGE_dejavu-fonts-ttf-DejaVuSerif-Bold is not set\n# CONFIG_PACKAGE_dejavu-fonts-ttf-DejaVuSerif-BoldItalic is not set\n# CONFIG_PACKAGE_dejavu-fonts-ttf-DejaVuSerif-Italic is not set\n# CONFIG_PACKAGE_dejavu-fonts-ttf-DejaVuSerifCondensed is not set\n# CONFIG_PACKAGE_dejavu-fonts-ttf-DejaVuSerifCondensed-Bold is not set\n# CONFIG_PACKAGE_dejavu-fonts-ttf-DejaVuSerifCondensed-BoldItalic is not set\n# CONFIG_PACKAGE_dejavu-fonts-ttf-DejaVuSerifCondensed-Italic is not set\n# end of DejaVu\n# end of Fonts\n\n#\n# Kernel\n#\n\n#\n# Kernel modules\n#\n\n#\n# Block Devices\n#\n# CONFIG_PACKAGE_kmod-aoe is not set\n# CONFIG_PACKAGE_kmod-ata-ahci is not set\n# CONFIG_PACKAGE_kmod-ata-artop is not set\n# CONFIG_PACKAGE_kmod-ata-core is not set\n# CONFIG_PACKAGE_kmod-ata-marvell-sata is not set\n# CONFIG_PACKAGE_kmod-ata-nvidia-sata is not set\n# CONFIG_PACKAGE_kmod-ata-pdc202xx-old is not set\n# CONFIG_PACKAGE_kmod-ata-piix is not set\n# CONFIG_PACKAGE_kmod-ata-sil is not set\n# CONFIG_PACKAGE_kmod-ata-sil24 is not set\n# CONFIG_PACKAGE_kmod-ata-via-sata is not set\n# CONFIG_PACKAGE_kmod-block2mtd is not set\nCONFIG_PACKAGE_kmod-dax=y\nCONFIG_PACKAGE_kmod-dm=y\n# CONFIG_PACKAGE_kmod-dm-raid is not set\n# CONFIG_PACKAGE_kmod-iosched-bfq is not set\n# CONFIG_PACKAGE_kmod-iscsi-initiator is not set\n# CONFIG_PACKAGE_kmod-loop is not set\n# CONFIG_PACKAGE_kmod-md-mod is not set\n# CONFIG_PACKAGE_kmod-nbd is not set\n# CONFIG_PACKAGE_kmod-scsi-cdrom is not set\n# CONFIG_PACKAGE_kmod-scsi-core is not set\n# CONFIG_PACKAGE_kmod-scsi-generic is not set\n# CONFIG_PACKAGE_kmod-scsi-tape is not set\n# end of Block Devices\n\n#\n# CAN Support\n#\n# CONFIG_PACKAGE_kmod-can is not set\n# end of CAN Support\n\n#\n# Cryptographic API modules\n#\nCONFIG_PACKAGE_kmod-crypto-acompress=y\nCONFIG_PACKAGE_kmod-crypto-aead=y\n# CONFIG_PACKAGE_kmod-crypto-arc4 is not set\n# CONFIG_PACKAGE_kmod-crypto-authenc is not set\nCONFIG_PACKAGE_kmod-crypto-cbc=y\nCONFIG_PACKAGE_kmod-crypto-ccm=y\nCONFIG_PACKAGE_kmod-crypto-cmac=y\nCONFIG_PACKAGE_kmod-crypto-crc32c=y\nCONFIG_PACKAGE_kmod-crypto-ctr=y\n# CONFIG_PACKAGE_kmod-crypto-cts is not set\n# CONFIG_PACKAGE_kmod-crypto-deflate is not set\n# CONFIG_PACKAGE_kmod-crypto-des is not set\n# CONFIG_PACKAGE_kmod-crypto-ecb is not set\n# CONFIG_PACKAGE_kmod-crypto-ecdh is not set\n# CONFIG_PACKAGE_kmod-crypto-echainiv is not set\n# CONFIG_PACKAGE_kmod-crypto-fcrypt is not set\nCONFIG_PACKAGE_kmod-crypto-gcm=y\nCONFIG_PACKAGE_kmod-crypto-gf128=y\nCONFIG_PACKAGE_kmod-crypto-ghash=y\nCONFIG_PACKAGE_kmod-crypto-hash=y\nCONFIG_PACKAGE_kmod-crypto-hmac=y\n# CONFIG_PACKAGE_kmod-crypto-hw-hifn-795x is not set\n# CONFIG_PACKAGE_kmod-crypto-hw-padlock is not set\n# CONFIG_PACKAGE_kmod-crypto-kpp is not set\nCONFIG_PACKAGE_kmod-crypto-lib-blake2s=y\nCONFIG_PACKAGE_kmod-crypto-lib-chacha20=y\nCONFIG_PACKAGE_kmod-crypto-lib-chacha20poly1305=y\nCONFIG_PACKAGE_kmod-crypto-lib-curve25519=y\nCONFIG_PACKAGE_kmod-crypto-lib-poly1305=y\nCONFIG_PACKAGE_kmod-crypto-manager=y\n# CONFIG_PACKAGE_kmod-crypto-md4 is not set\n# CONFIG_PACKAGE_kmod-crypto-md5 is not set\n# CONFIG_PACKAGE_kmod-crypto-michael-mic is not set\n# CONFIG_PACKAGE_kmod-crypto-misc is not set\nCONFIG_PACKAGE_kmod-crypto-null=y\n# CONFIG_PACKAGE_kmod-crypto-pcbc is not set\n# CONFIG_PACKAGE_kmod-crypto-rmd160 is not set\nCONFIG_PACKAGE_kmod-crypto-rng=y\nCONFIG_PACKAGE_kmod-crypto-seqiv=y\nCONFIG_PACKAGE_kmod-crypto-sha1=y\nCONFIG_PACKAGE_kmod-crypto-sha256=y\n# CONFIG_PACKAGE_kmod-crypto-sha512 is not set\n# CONFIG_PACKAGE_kmod-crypto-test is not set\n# CONFIG_PACKAGE_kmod-crypto-user is not set\n# CONFIG_PACKAGE_kmod-crypto-xcbc is not set\n# CONFIG_PACKAGE_kmod-crypto-xts is not set\n# CONFIG_PACKAGE_kmod-cryptodev is not set\n# end of Cryptographic API modules\n\n#\n# Filesystems\n#\n# CONFIG_PACKAGE_kmod-fs-afs is not set\n# CONFIG_PACKAGE_kmod-fs-antfs is not set\n# CONFIG_PACKAGE_kmod-fs-autofs4 is not set\nCONFIG_PACKAGE_kmod-fs-btrfs=y\n# CONFIG_PACKAGE_kmod-fs-cifs is not set\n# CONFIG_PACKAGE_kmod-fs-configfs is not set\n# CONFIG_PACKAGE_kmod-fs-cramfs is not set\n# CONFIG_PACKAGE_kmod-fs-exfat is not set\n# CONFIG_PACKAGE_kmod-fs-exportfs is not set\nCONFIG_PACKAGE_kmod-fs-ext4=y\n# CONFIG_PACKAGE_kmod-fs-f2fs is not set\n# CONFIG_PACKAGE_kmod-fs-fscache is not set\n# CONFIG_PACKAGE_kmod-fs-hfs is not set\n# CONFIG_PACKAGE_kmod-fs-hfsplus is not set\n# CONFIG_PACKAGE_kmod-fs-isofs is not set\n# CONFIG_PACKAGE_kmod-fs-jfs is not set\n# CONFIG_PACKAGE_kmod-fs-ksmbd is not set\n# CONFIG_PACKAGE_kmod-fs-minix is not set\n# CONFIG_PACKAGE_kmod-fs-msdos is not set\n# CONFIG_PACKAGE_kmod-fs-nfs is not set\n# CONFIG_PACKAGE_kmod-fs-nfs-common is not set\n# CONFIG_PACKAGE_kmod-fs-nfs-common-rpcsec is not set\n# CONFIG_PACKAGE_kmod-fs-nfs-v3 is not set\n# CONFIG_PACKAGE_kmod-fs-nfs-v4 is not set\n# CONFIG_PACKAGE_kmod-fs-nfsd is not set\n# CONFIG_PACKAGE_kmod-fs-ntfs is not set\n# CONFIG_PACKAGE_kmod-fs-reiserfs is not set\n# CONFIG_PACKAGE_kmod-fs-squashfs is not set\n# CONFIG_PACKAGE_kmod-fs-udf is not set\nCONFIG_PACKAGE_kmod-fs-vfat=y\n# CONFIG_PACKAGE_kmod-fs-xfs is not set\n# CONFIG_PACKAGE_kmod-fuse is not set\n# end of Filesystems\n\n#\n# FireWire support\n#\n# CONFIG_PACKAGE_kmod-firewire is not set\n# end of FireWire support\n\n#\n# Hardware Monitoring Support\n#\n# CONFIG_PACKAGE_kmod-gl-mifi-mcu is not set\n# CONFIG_PACKAGE_kmod-hwmon-ad7418 is not set\n# CONFIG_PACKAGE_kmod-hwmon-adcxx is not set\n# CONFIG_PACKAGE_kmod-hwmon-adt7410 is not set\n# CONFIG_PACKAGE_kmod-hwmon-adt7475 is not set\n# CONFIG_PACKAGE_kmod-hwmon-core is not set\n# CONFIG_PACKAGE_kmod-hwmon-dme1737 is not set\n# CONFIG_PACKAGE_kmod-hwmon-drivetemp is not set\n# CONFIG_PACKAGE_kmod-hwmon-gpiofan is not set\n# CONFIG_PACKAGE_kmod-hwmon-ina209 is not set\n# CONFIG_PACKAGE_kmod-hwmon-ina2xx is not set\n# CONFIG_PACKAGE_kmod-hwmon-it87 is not set\n# CONFIG_PACKAGE_kmod-hwmon-lm63 is not set\n# CONFIG_PACKAGE_kmod-hwmon-lm75 is not set\n# CONFIG_PACKAGE_kmod-hwmon-lm77 is not set\n# CONFIG_PACKAGE_kmod-hwmon-lm85 is not set\n# CONFIG_PACKAGE_kmod-hwmon-lm90 is not set\n# CONFIG_PACKAGE_kmod-hwmon-lm92 is not set\n# CONFIG_PACKAGE_kmod-hwmon-lm95241 is not set\n# CONFIG_PACKAGE_kmod-hwmon-ltc4151 is not set\n# CONFIG_PACKAGE_kmod-hwmon-mcp3021 is not set\n# CONFIG_PACKAGE_kmod-hwmon-pwmfan is not set\n# CONFIG_PACKAGE_kmod-hwmon-sch5627 is not set\n# CONFIG_PACKAGE_kmod-hwmon-sht21 is not set\n# CONFIG_PACKAGE_kmod-hwmon-tmp102 is not set\n# CONFIG_PACKAGE_kmod-hwmon-tmp103 is not set\n# CONFIG_PACKAGE_kmod-hwmon-tmp421 is not set\n# CONFIG_PACKAGE_kmod-hwmon-vid is not set\n# CONFIG_PACKAGE_kmod-hwmon-w83793 is not set\n# CONFIG_PACKAGE_kmod-pmbus-core is not set\n# CONFIG_PACKAGE_kmod-pmbus-zl6100 is not set\n# end of Hardware Monitoring Support\n\n#\n# I2C support\n#\n# CONFIG_PACKAGE_kmod-i2c-algo-bit is not set\n# CONFIG_PACKAGE_kmod-i2c-algo-pca is not set\n# CONFIG_PACKAGE_kmod-i2c-algo-pcf is not set\n# CONFIG_PACKAGE_kmod-i2c-core is not set\n# CONFIG_PACKAGE_kmod-i2c-designware-pci is not set\n# CONFIG_PACKAGE_kmod-i2c-gpio is not set\n# CONFIG_PACKAGE_kmod-i2c-mux is not set\n# CONFIG_PACKAGE_kmod-i2c-mux-gpio is not set\n# CONFIG_PACKAGE_kmod-i2c-mux-pca9541 is not set\n# CONFIG_PACKAGE_kmod-i2c-mux-pca954x is not set\n# CONFIG_PACKAGE_kmod-i2c-pxa is not set\n# CONFIG_PACKAGE_kmod-i2c-smbus is not set\n# CONFIG_PACKAGE_kmod-i2c-tiny-usb is not set\n# end of I2C support\n\n#\n# Industrial I/O Modules\n#\n# CONFIG_PACKAGE_kmod-iio-ad799x is not set\n# CONFIG_PACKAGE_kmod-iio-ads1015 is not set\n# CONFIG_PACKAGE_kmod-iio-am2315 is not set\n# CONFIG_PACKAGE_kmod-iio-bh1750 is not set\n# CONFIG_PACKAGE_kmod-iio-bme680 is not set\n# CONFIG_PACKAGE_kmod-iio-bme680-i2c is not set\n# CONFIG_PACKAGE_kmod-iio-bme680-spi is not set\n# CONFIG_PACKAGE_kmod-iio-bmp280 is not set\n# CONFIG_PACKAGE_kmod-iio-bmp280-i2c is not set\n# CONFIG_PACKAGE_kmod-iio-bmp280-spi is not set\n# CONFIG_PACKAGE_kmod-iio-ccs811 is not set\n# CONFIG_PACKAGE_kmod-iio-core is not set\n# CONFIG_PACKAGE_kmod-iio-dht11 is not set\n# CONFIG_PACKAGE_kmod-iio-fxas21002c is not set\n# CONFIG_PACKAGE_kmod-iio-fxas21002c-i2c is not set\n# CONFIG_PACKAGE_kmod-iio-fxas21002c-spi is not set\n# CONFIG_PACKAGE_kmod-iio-fxos8700 is not set\n# CONFIG_PACKAGE_kmod-iio-fxos8700-i2c is not set\n# CONFIG_PACKAGE_kmod-iio-fxos8700-spi is not set\n# CONFIG_PACKAGE_kmod-iio-hmc5843 is not set\n# CONFIG_PACKAGE_kmod-iio-htu21 is not set\n# CONFIG_PACKAGE_kmod-iio-kfifo-buf is not set\n# CONFIG_PACKAGE_kmod-iio-lsm6dsx is not set\n# CONFIG_PACKAGE_kmod-iio-lsm6dsx-i2c is not set\n# CONFIG_PACKAGE_kmod-iio-lsm6dsx-spi is not set\n# CONFIG_PACKAGE_kmod-iio-si7020 is not set\n# CONFIG_PACKAGE_kmod-iio-sps30 is not set\n# CONFIG_PACKAGE_kmod-iio-st_accel is not set\n# CONFIG_PACKAGE_kmod-iio-st_accel-i2c is not set\n# CONFIG_PACKAGE_kmod-iio-st_accel-spi is not set\n# CONFIG_PACKAGE_kmod-iio-tsl4531 is not set\n# CONFIG_PACKAGE_kmod-industrialio-triggered-buffer is not set\n# end of Industrial I/O Modules\n\n#\n# Input modules\n#\n# CONFIG_PACKAGE_kmod-hid is not set\n# CONFIG_PACKAGE_kmod-hid-generic is not set\n# CONFIG_PACKAGE_kmod-input-core is not set\n# CONFIG_PACKAGE_kmod-input-evdev is not set\n# CONFIG_PACKAGE_kmod-input-gpio-encoder is not set\n# CONFIG_PACKAGE_kmod-input-gpio-keys is not set\n# CONFIG_PACKAGE_kmod-input-gpio-keys-polled is not set\n# CONFIG_PACKAGE_kmod-input-joydev is not set\n# CONFIG_PACKAGE_kmod-input-matrixkmap is not set\n# CONFIG_PACKAGE_kmod-input-polldev is not set\n# CONFIG_PACKAGE_kmod-input-touchscreen-ads7846 is not set\n# CONFIG_PACKAGE_kmod-input-uinput is not set\n# end of Input modules\n\n#\n# LED modules\n#\n# CONFIG_PACKAGE_kmod-input-leds is not set\n# CONFIG_PACKAGE_kmod-leds-gpio is not set\n# CONFIG_PACKAGE_kmod-leds-pca963x is not set\n# CONFIG_PACKAGE_kmod-leds-uleds is not set\n# CONFIG_PACKAGE_kmod-ledtrig-activity is not set\n# CONFIG_PACKAGE_kmod-ledtrig-audio is not set\n# CONFIG_PACKAGE_kmod-ledtrig-gpio is not set\n# CONFIG_PACKAGE_kmod-ledtrig-oneshot is not set\n# CONFIG_PACKAGE_kmod-ledtrig-pattern is not set\n# CONFIG_PACKAGE_kmod-ledtrig-transient is not set\n# end of LED modules\n\n#\n# Libraries\n#\n# CONFIG_PACKAGE_kmod-lib-cordic is not set\nCONFIG_PACKAGE_kmod-lib-crc-ccitt=y\n# CONFIG_PACKAGE_kmod-lib-crc-itu-t is not set\nCONFIG_PACKAGE_kmod-lib-crc16=y\nCONFIG_PACKAGE_kmod-lib-crc32c=y\n# CONFIG_PACKAGE_kmod-lib-crc7 is not set\n# CONFIG_PACKAGE_kmod-lib-crc8 is not set\n# CONFIG_PACKAGE_kmod-lib-lz4 is not set\nCONFIG_PACKAGE_kmod-lib-lzo=y\nCONFIG_PACKAGE_kmod-lib-raid6=y\n# CONFIG_PACKAGE_kmod-lib-textsearch is not set\nCONFIG_PACKAGE_kmod-lib-xor=y\nCONFIG_PACKAGE_kmod-lib-zlib-deflate=y\nCONFIG_PACKAGE_kmod-lib-zlib-inflate=y\nCONFIG_PACKAGE_kmod-lib-zstd=y\n# end of Libraries\n\n#\n# Native Language Support\n#\nCONFIG_PACKAGE_kmod-nls-base=y\n# CONFIG_PACKAGE_kmod-nls-cp1250 is not set\n# CONFIG_PACKAGE_kmod-nls-cp1251 is not set\nCONFIG_PACKAGE_kmod-nls-cp437=y\n# CONFIG_PACKAGE_kmod-nls-cp775 is not set\n# CONFIG_PACKAGE_kmod-nls-cp850 is not set\n# CONFIG_PACKAGE_kmod-nls-cp852 is not set\n# CONFIG_PACKAGE_kmod-nls-cp862 is not set\n# CONFIG_PACKAGE_kmod-nls-cp864 is not set\n# CONFIG_PACKAGE_kmod-nls-cp866 is not set\n# CONFIG_PACKAGE_kmod-nls-cp932 is not set\n# CONFIG_PACKAGE_kmod-nls-cp936 is not set\n# CONFIG_PACKAGE_kmod-nls-cp950 is not set\nCONFIG_PACKAGE_kmod-nls-iso8859-1=y\n# CONFIG_PACKAGE_kmod-nls-iso8859-13 is not set\n# CONFIG_PACKAGE_kmod-nls-iso8859-15 is not set\n# CONFIG_PACKAGE_kmod-nls-iso8859-2 is not set\n# CONFIG_PACKAGE_kmod-nls-iso8859-6 is not set\n# CONFIG_PACKAGE_kmod-nls-iso8859-8 is not set\n# CONFIG_PACKAGE_kmod-nls-koi8r is not set\nCONFIG_PACKAGE_kmod-nls-utf8=y\n# end of Native Language Support\n\n#\n# Netfilter Extensions\n#\n# CONFIG_PACKAGE_kmod-arptables is not set\nCONFIG_PACKAGE_kmod-br-netfilter=y\n# CONFIG_PACKAGE_kmod-ebtables is not set\n# CONFIG_PACKAGE_kmod-ebtables-ipv4 is not set\n# CONFIG_PACKAGE_kmod-ebtables-ipv6 is not set\n# CONFIG_PACKAGE_kmod-ebtables-watchers is not set\nCONFIG_PACKAGE_kmod-ip6tables=y\n# CONFIG_PACKAGE_kmod-ip6tables-extra is not set\n# CONFIG_PACKAGE_kmod-ipt-account is not set\n# CONFIG_PACKAGE_kmod-ipt-chaos is not set\n# CONFIG_PACKAGE_kmod-ipt-checksum is not set\n# CONFIG_PACKAGE_kmod-ipt-cluster is not set\n# CONFIG_PACKAGE_kmod-ipt-clusterip is not set\n# CONFIG_PACKAGE_kmod-ipt-compat-xtables is not set\n# CONFIG_PACKAGE_kmod-ipt-condition is not set\nCONFIG_PACKAGE_kmod-ipt-conntrack=y\nCONFIG_PACKAGE_kmod-ipt-conntrack-extra=y\n# CONFIG_PACKAGE_kmod-ipt-conntrack-label is not set\nCONFIG_PACKAGE_kmod-ipt-core=y\n# CONFIG_PACKAGE_kmod-ipt-debug is not set\n# CONFIG_PACKAGE_kmod-ipt-delude is not set\n# CONFIG_PACKAGE_kmod-ipt-dhcpmac is not set\n# CONFIG_PACKAGE_kmod-ipt-dnetmap is not set\nCONFIG_PACKAGE_kmod-ipt-extra=y\n# CONFIG_PACKAGE_kmod-ipt-filter is not set\n# CONFIG_PACKAGE_kmod-ipt-fuzzy is not set\n# CONFIG_PACKAGE_kmod-ipt-geoip is not set\n# CONFIG_PACKAGE_kmod-ipt-hashlimit is not set\n# CONFIG_PACKAGE_kmod-ipt-iface is not set\n# CONFIG_PACKAGE_kmod-ipt-ipmark is not set\nCONFIG_PACKAGE_kmod-ipt-ipopt=y\n# CONFIG_PACKAGE_kmod-ipt-ipp2p is not set\n# CONFIG_PACKAGE_kmod-ipt-iprange is not set\n# CONFIG_PACKAGE_kmod-ipt-ipsec is not set\nCONFIG_PACKAGE_kmod-ipt-ipset=y\n# CONFIG_PACKAGE_kmod-ipt-ipv4options is not set\n# CONFIG_PACKAGE_kmod-ipt-led is not set\n# CONFIG_PACKAGE_kmod-ipt-length2 is not set\n# CONFIG_PACKAGE_kmod-ipt-logmark is not set\n# CONFIG_PACKAGE_kmod-ipt-lscan is not set\n# CONFIG_PACKAGE_kmod-ipt-lua is not set\nCONFIG_PACKAGE_kmod-ipt-nat=y\n# CONFIG_PACKAGE_kmod-ipt-nat-extra is not set\n# CONFIG_PACKAGE_kmod-ipt-nat6 is not set\n# CONFIG_PACKAGE_kmod-ipt-nathelper-rtsp is not set\n# CONFIG_PACKAGE_kmod-ipt-nflog is not set\n# CONFIG_PACKAGE_kmod-ipt-nfqueue is not set\nCONFIG_PACKAGE_kmod-ipt-offload=y\n# CONFIG_PACKAGE_kmod-ipt-physdev is not set\n# CONFIG_PACKAGE_kmod-ipt-proto is not set\n# CONFIG_PACKAGE_kmod-ipt-psd is not set\n# CONFIG_PACKAGE_kmod-ipt-quota2 is not set\nCONFIG_PACKAGE_kmod-ipt-raw=y\n# CONFIG_PACKAGE_kmod-ipt-raw6 is not set\n# CONFIG_PACKAGE_kmod-ipt-rpfilter is not set\n# CONFIG_PACKAGE_kmod-ipt-rtpengine is not set\n# CONFIG_PACKAGE_kmod-ipt-sysrq is not set\n# CONFIG_PACKAGE_kmod-ipt-tarpit is not set\n# CONFIG_PACKAGE_kmod-ipt-tee is not set\nCONFIG_PACKAGE_kmod-ipt-tproxy=y\n# CONFIG_PACKAGE_kmod-ipt-u32 is not set\n# CONFIG_PACKAGE_kmod-ipt-ulog is not set\n# CONFIG_PACKAGE_kmod-netatop is not set\nCONFIG_PACKAGE_kmod-nf-conntrack=y\nCONFIG_PACKAGE_kmod-nf-conntrack-netlink=y\nCONFIG_PACKAGE_kmod-nf-conntrack6=y\nCONFIG_PACKAGE_kmod-nf-flow=y\nCONFIG_PACKAGE_kmod-nf-ipt=y\nCONFIG_PACKAGE_kmod-nf-ipt6=y\nCONFIG_PACKAGE_kmod-nf-ipvs=y\n# CONFIG_PACKAGE_kmod-nf-ipvs-ftp is not set\n# CONFIG_PACKAGE_kmod-nf-ipvs-sip is not set\nCONFIG_PACKAGE_kmod-nf-nat=y\n# CONFIG_PACKAGE_kmod-nf-nat6 is not set\n# CONFIG_PACKAGE_kmod-nf-nathelper is not set\n# CONFIG_PACKAGE_kmod-nf-nathelper-extra is not set\nCONFIG_PACKAGE_kmod-nf-reject=y\nCONFIG_PACKAGE_kmod-nf-reject6=y\nCONFIG_PACKAGE_kmod-nfnetlink=y\n# CONFIG_PACKAGE_kmod-nfnetlink-log is not set\n# CONFIG_PACKAGE_kmod-nfnetlink-queue is not set\n# CONFIG_PACKAGE_kmod-nft-arp is not set\n# CONFIG_PACKAGE_kmod-nft-bridge is not set\n# CONFIG_PACKAGE_kmod-nft-core is not set\n# CONFIG_PACKAGE_kmod-nft-fib is not set\n# CONFIG_PACKAGE_kmod-nft-nat is not set\n# CONFIG_PACKAGE_kmod-nft-nat6 is not set\n# CONFIG_PACKAGE_kmod-nft-netdev is not set\n# CONFIG_PACKAGE_kmod-nft-offload is not set\n# CONFIG_PACKAGE_kmod-nft-queue is not set\n# end of Netfilter Extensions\n\n#\n# Network Devices\n#\n# CONFIG_PACKAGE_kmod-3c59x is not set\n# CONFIG_PACKAGE_kmod-8139cp is not set\n# CONFIG_PACKAGE_kmod-8139too is not set\n# CONFIG_PACKAGE_kmod-alx is not set\n# CONFIG_PACKAGE_kmod-atl1 is not set\n# CONFIG_PACKAGE_kmod-atl1c is not set\n# CONFIG_PACKAGE_kmod-atl1e is not set\n# CONFIG_PACKAGE_kmod-atl2 is not set\n# CONFIG_PACKAGE_kmod-b44 is not set\n# CONFIG_PACKAGE_kmod-be2net is not set\n# CONFIG_PACKAGE_kmod-bnx2 is not set\n# CONFIG_PACKAGE_kmod-bnx2x is not set\n# CONFIG_PACKAGE_kmod-dm9000 is not set\n# CONFIG_PACKAGE_kmod-dummy is not set\n# CONFIG_PACKAGE_kmod-e100 is not set\n# CONFIG_PACKAGE_kmod-e1000 is not set\n# CONFIG_PACKAGE_kmod-e1000e is not set\n# CONFIG_PACKAGE_kmod-et131x is not set\n# CONFIG_PACKAGE_kmod-ethoc is not set\n# CONFIG_PACKAGE_kmod-forcedeth is not set\n# CONFIG_PACKAGE_kmod-hfcmulti is not set\n# CONFIG_PACKAGE_kmod-hfcpci is not set\n# CONFIG_PACKAGE_kmod-i40e is not set\n# CONFIG_PACKAGE_kmod-iavf is not set\nCONFIG_PACKAGE_kmod-ifb=y\n# CONFIG_PACKAGE_kmod-igb is not set\n# CONFIG_PACKAGE_kmod-igc is not set\n# CONFIG_PACKAGE_kmod-ipvlan is not set\n# CONFIG_PACKAGE_kmod-ixgbe is not set\n# CONFIG_PACKAGE_kmod-ixgbevf is not set\n# CONFIG_PACKAGE_kmod-libphy is not set\n# CONFIG_PACKAGE_kmod-macvlan is not set\n# CONFIG_PACKAGE_kmod-mdio-gpio is not set\nCONFIG_PACKAGE_kmod-mii=y\n# CONFIG_PACKAGE_kmod-mlx4-core is not set\n# CONFIG_PACKAGE_kmod-mlx5-core is not set\n# CONFIG_PACKAGE_kmod-natsemi is not set\n# CONFIG_PACKAGE_kmod-ne2k-pci is not set\n# CONFIG_PACKAGE_kmod-niu is not set\n# CONFIG_PACKAGE_kmod-of-mdio is not set\n# CONFIG_PACKAGE_kmod-pcnet32 is not set\n# CONFIG_PACKAGE_kmod-phy-bcm84881 is not set\n# CONFIG_PACKAGE_kmod-phy-broadcom is not set\n# CONFIG_PACKAGE_kmod-phy-realtek is not set\n# CONFIG_PACKAGE_kmod-phylink is not set\n# CONFIG_PACKAGE_kmod-qlcnic is not set\n# CONFIG_PACKAGE_kmod-r6040 is not set\n# CONFIG_PACKAGE_kmod-r8169 is not set\n# CONFIG_PACKAGE_kmod-sfc is not set\n# CONFIG_PACKAGE_kmod-sfc-falcon is not set\n# CONFIG_PACKAGE_kmod-sfp is not set\n# CONFIG_PACKAGE_kmod-siit is not set\n# CONFIG_PACKAGE_kmod-sis190 is not set\n# CONFIG_PACKAGE_kmod-sis900 is not set\n# CONFIG_PACKAGE_kmod-skge is not set\n# CONFIG_PACKAGE_kmod-sky2 is not set\n# CONFIG_PACKAGE_kmod-solos-pci is not set\n# CONFIG_PACKAGE_kmod-spi-ks8995 is not set\n# CONFIG_PACKAGE_kmod-swconfig is not set\n# CONFIG_PACKAGE_kmod-switch-bcm53xx is not set\n# CONFIG_PACKAGE_kmod-switch-bcm53xx-mdio is not set\n# CONFIG_PACKAGE_kmod-switch-ip17xx is not set\n# CONFIG_PACKAGE_kmod-switch-rtl8306 is not set\n# CONFIG_PACKAGE_kmod-switch-rtl8366-smi is not set\n# CONFIG_PACKAGE_kmod-switch-rtl8366rb is not set\n# CONFIG_PACKAGE_kmod-switch-rtl8366s is not set\n# CONFIG_PACKAGE_kmod-switch-rtl8367b is not set\n# CONFIG_PACKAGE_kmod-tg3 is not set\n# CONFIG_PACKAGE_kmod-tulip is not set\n# CONFIG_PACKAGE_kmod-via-rhine is not set\n# CONFIG_PACKAGE_kmod-via-velocity is not set\n# CONFIG_PACKAGE_kmod-vmxnet3 is not set\n# end of Network Devices\n\n#\n# Network Support\n#\n# CONFIG_PACKAGE_kmod-atm is not set\n# CONFIG_PACKAGE_kmod-ax25 is not set\n# CONFIG_PACKAGE_kmod-batman-adv is not set\n# CONFIG_PACKAGE_kmod-bonding is not set\n# CONFIG_PACKAGE_kmod-bpf-test is not set\n# CONFIG_PACKAGE_kmod-dnsresolver is not set\n# CONFIG_PACKAGE_kmod-fou is not set\n# CONFIG_PACKAGE_kmod-fou6 is not set\n# CONFIG_PACKAGE_kmod-geneve is not set\n# CONFIG_PACKAGE_kmod-gre is not set\n# CONFIG_PACKAGE_kmod-gre6 is not set\n# CONFIG_PACKAGE_kmod-ip6-tunnel is not set\n# CONFIG_PACKAGE_kmod-ipip is not set\n# CONFIG_PACKAGE_kmod-ipsec is not set\n# CONFIG_PACKAGE_kmod-iptunnel6 is not set\n# CONFIG_PACKAGE_kmod-isdn4linux is not set\n# CONFIG_PACKAGE_kmod-jool is not set\n# CONFIG_PACKAGE_kmod-l2tp is not set\n# CONFIG_PACKAGE_kmod-l2tp-eth is not set\n# CONFIG_PACKAGE_kmod-l2tp-ip is not set\n# CONFIG_PACKAGE_kmod-macremapper is not set\n# CONFIG_PACKAGE_kmod-macsec is not set\n# CONFIG_PACKAGE_kmod-mdio-netlink is not set\n# CONFIG_PACKAGE_kmod-misdn is not set\n# CONFIG_PACKAGE_kmod-mpls is not set\n# CONFIG_PACKAGE_kmod-nat46 is not set\n# CONFIG_PACKAGE_kmod-netem is not set\n# CONFIG_PACKAGE_kmod-netlink-diag is not set\n# CONFIG_PACKAGE_kmod-nlmon is not set\n# CONFIG_PACKAGE_kmod-nsh is not set\n# CONFIG_PACKAGE_kmod-openvswitch is not set\n# CONFIG_PACKAGE_kmod-openvswitch-geneve is not set\n# CONFIG_PACKAGE_kmod-openvswitch-gre is not set\n# CONFIG_PACKAGE_kmod-openvswitch-vxlan is not set\n# CONFIG_PACKAGE_kmod-ovpn-dco is not set\n# CONFIG_PACKAGE_kmod-pf-ring is not set\n# CONFIG_PACKAGE_kmod-pktgen is not set\nCONFIG_PACKAGE_kmod-ppp=y\n# CONFIG_PACKAGE_kmod-mppe is not set\n# CONFIG_PACKAGE_kmod-ppp-synctty is not set\n# CONFIG_PACKAGE_kmod-pppoa is not set\nCONFIG_PACKAGE_kmod-pppoe=y\n# CONFIG_PACKAGE_kmod-pppol2tp is not set\nCONFIG_PACKAGE_kmod-pppox=y\n# CONFIG_PACKAGE_kmod-pptp is not set\n# CONFIG_PACKAGE_kmod-sched is not set\n# CONFIG_PACKAGE_kmod-sched-act-vlan is not set\n# CONFIG_PACKAGE_kmod-sched-bpf is not set\nCONFIG_PACKAGE_kmod-sched-cake=y\nCONFIG_PACKAGE_kmod-sched-connmark=y\nCONFIG_PACKAGE_kmod-sched-core=y\n# CONFIG_PACKAGE_kmod-sched-ctinfo is not set\n# CONFIG_PACKAGE_kmod-sched-flower is not set\n# CONFIG_PACKAGE_kmod-sched-ipset is not set\n# CONFIG_PACKAGE_kmod-sched-mqprio is not set\n# CONFIG_PACKAGE_kmod-sctp is not set\n# CONFIG_PACKAGE_kmod-sit is not set\nCONFIG_PACKAGE_kmod-slhc=y\n# CONFIG_PACKAGE_kmod-slip is not set\n# CONFIG_PACKAGE_kmod-tcp-bbr is not set\n# CONFIG_PACKAGE_kmod-tcp-hybla is not set\n# CONFIG_PACKAGE_kmod-trelay is not set\nCONFIG_PACKAGE_kmod-tun=y\nCONFIG_PACKAGE_kmod-udptunnel4=y\nCONFIG_PACKAGE_kmod-udptunnel6=y\nCONFIG_PACKAGE_kmod-veth=y\n# CONFIG_PACKAGE_kmod-vxlan is not set\nCONFIG_PACKAGE_kmod-wireguard=y\n# end of Network Support\n\n#\n# Other modules\n#\n# CONFIG_PACKAGE_kmod-6lowpan is not set\n# CONFIG_PACKAGE_kmod-ath3k is not set\n# CONFIG_PACKAGE_kmod-bcma is not set\n# CONFIG_PACKAGE_kmod-bluetooth is not set\n# CONFIG_PACKAGE_kmod-bluetooth-6lowpan is not set\n# CONFIG_PACKAGE_kmod-btmrvl is not set\n# CONFIG_PACKAGE_kmod-button-hotplug is not set\n# CONFIG_PACKAGE_kmod-echo is not set\n# CONFIG_PACKAGE_kmod-eeprom-93cx6 is not set\n# CONFIG_PACKAGE_kmod-eeprom-at24 is not set\n# CONFIG_PACKAGE_kmod-eeprom-at25 is not set\n# CONFIG_PACKAGE_kmod-gpio-beeper is not set\nCONFIG_PACKAGE_kmod-gpio-button-hotplug=y\n# CONFIG_PACKAGE_kmod-gpio-mcp23s08 is not set\n# CONFIG_PACKAGE_kmod-gpio-nxp-74hc164 is not set\n# CONFIG_PACKAGE_kmod-gpio-pca953x is not set\n# CONFIG_PACKAGE_kmod-gpio-pcf857x is not set\nCONFIG_PACKAGE_kmod-ikconfig=y\n# CONFIG_PACKAGE_kmod-it87-wdt is not set\n# CONFIG_PACKAGE_kmod-itco-wdt is not set\nCONFIG_PACKAGE_kmod-keys-encrypted=y\nCONFIG_PACKAGE_kmod-keys-trusted=y\n# CONFIG_PACKAGE_kmod-lp is not set\n# CONFIG_PACKAGE_kmod-mmc is not set\n# CONFIG_PACKAGE_kmod-mtd-rw is not set\n# CONFIG_PACKAGE_kmod-mtdoops is not set\n# CONFIG_PACKAGE_kmod-mtdram is not set\n# CONFIG_PACKAGE_kmod-mtdtests is not set\n# CONFIG_PACKAGE_kmod-parport-pc is not set\n# CONFIG_PACKAGE_kmod-ppdev is not set\n# CONFIG_PACKAGE_kmod-pps is not set\n# CONFIG_PACKAGE_kmod-pps-gpio is not set\n# CONFIG_PACKAGE_kmod-pps-ldisc is not set\n# CONFIG_PACKAGE_kmod-ptp is not set\nCONFIG_PACKAGE_kmod-random-core=y\n# CONFIG_PACKAGE_kmod-rtc-ds1307 is not set\n# CONFIG_PACKAGE_kmod-rtc-ds1374 is not set\n# CONFIG_PACKAGE_kmod-rtc-ds1672 is not set\n# CONFIG_PACKAGE_kmod-rtc-em3027 is not set\n# CONFIG_PACKAGE_kmod-rtc-isl1208 is not set\n# CONFIG_PACKAGE_kmod-rtc-pcf2123 is not set\n# CONFIG_PACKAGE_kmod-rtc-pcf2127 is not set\n# CONFIG_PACKAGE_kmod-rtc-pcf8563 is not set\n# CONFIG_PACKAGE_kmod-rtc-pt7c4338 is not set\n# CONFIG_PACKAGE_kmod-rtc-rs5c372a is not set\n# CONFIG_PACKAGE_kmod-rtc-rx8025 is not set\n# CONFIG_PACKAGE_kmod-rtc-s35390a is not set\n# CONFIG_PACKAGE_kmod-sdhci is not set\n# CONFIG_PACKAGE_kmod-serial-8250 is not set\n# CONFIG_PACKAGE_kmod-serial-8250-exar is not set\n# CONFIG_PACKAGE_kmod-softdog is not set\n# CONFIG_PACKAGE_kmod-ssb is not set\nCONFIG_PACKAGE_kmod-tpm=y\n# CONFIG_PACKAGE_kmod-tpm-i2c-atmel is not set\n# CONFIG_PACKAGE_kmod-tpm-i2c-infineon is not set\n# CONFIG_PACKAGE_kmod-w83627hf-wdt is not set\n# CONFIG_PACKAGE_kmod-zram is not set\n# end of Other modules\n\n#\n# PCMCIA support\n#\n# end of PCMCIA support\n\n#\n# SPI Support\n#\n# CONFIG_PACKAGE_kmod-mmc-spi is not set\n# CONFIG_PACKAGE_kmod-spi-bitbang is not set\n# CONFIG_PACKAGE_kmod-spi-dev is not set\n# CONFIG_PACKAGE_kmod-spi-gpio is not set\n# end of SPI Support\n\n#\n# Sound Support\n#\n# CONFIG_PACKAGE_kmod-sound-core is not set\n# end of Sound Support\n\n#\n# USB Support\n#\n# CONFIG_PACKAGE_kmod-chaoskey is not set\n# CONFIG_PACKAGE_kmod-usb-acm is not set\n# CONFIG_PACKAGE_kmod-usb-atm is not set\n# CONFIG_PACKAGE_kmod-usb-cm109 is not set\nCONFIG_PACKAGE_kmod-usb-core=y\n# CONFIG_PACKAGE_kmod-usb-dwc2 is not set\n# CONFIG_PACKAGE_kmod-usb-dwc3 is not set\n# CONFIG_PACKAGE_kmod-usb-gadget-cdc-composite is not set\n# CONFIG_PACKAGE_kmod-usb-gadget-ehci-debug is not set\n# CONFIG_PACKAGE_kmod-usb-gadget-eth is not set\n# CONFIG_PACKAGE_kmod-usb-gadget-hid is not set\n# CONFIG_PACKAGE_kmod-usb-gadget-mass-storage is not set\n# CONFIG_PACKAGE_kmod-usb-gadget-ncm is not set\n# CONFIG_PACKAGE_kmod-usb-gadget-serial is not set\n# CONFIG_PACKAGE_kmod-usb-hid is not set\n# CONFIG_PACKAGE_kmod-usb-hid-cp2112 is not set\n# CONFIG_PACKAGE_kmod-usb-ledtrig-usbport is not set\nCONFIG_PACKAGE_kmod-usb-net=y\n# CONFIG_PACKAGE_kmod-usb-net-aqc111 is not set\n# CONFIG_PACKAGE_kmod-usb-net-asix is not set\n# CONFIG_PACKAGE_kmod-usb-net-asix-ax88179 is not set\n# CONFIG_PACKAGE_kmod-usb-net-cdc-eem is not set\n# CONFIG_PACKAGE_kmod-usb-net-cdc-ether is not set\n# CONFIG_PACKAGE_kmod-usb-net-cdc-mbim is not set\n# CONFIG_PACKAGE_kmod-usb-net-cdc-ncm is not set\n# CONFIG_PACKAGE_kmod-usb-net-cdc-subset is not set\n# CONFIG_PACKAGE_kmod-usb-net-dm9601-ether is not set\n# CONFIG_PACKAGE_kmod-usb-net-hso is not set\n# CONFIG_PACKAGE_kmod-usb-net-huawei-cdc-ncm is not set\n# CONFIG_PACKAGE_kmod-usb-net-ipheth is not set\n# CONFIG_PACKAGE_kmod-usb-net-kalmia is not set\n# CONFIG_PACKAGE_kmod-usb-net-kaweth is not set\n# CONFIG_PACKAGE_kmod-usb-net-mcs7830 is not set\n# CONFIG_PACKAGE_kmod-usb-net-pegasus is not set\n# CONFIG_PACKAGE_kmod-usb-net-pl is not set\n# CONFIG_PACKAGE_kmod-usb-net-qmi-wwan is not set\n# CONFIG_PACKAGE_kmod-usb-net-rndis is not set\n# CONFIG_PACKAGE_kmod-usb-net-rtl8150 is not set\nCONFIG_PACKAGE_kmod-usb-net-rtl8152=y\n# CONFIG_PACKAGE_kmod-usb-net-sierrawireless is not set\n# CONFIG_PACKAGE_kmod-usb-net-smsc75xx is not set\n# CONFIG_PACKAGE_kmod-usb-net-smsc95xx is not set\n# CONFIG_PACKAGE_kmod-usb-net-sr9700 is not set\n# CONFIG_PACKAGE_kmod-usb-net2280 is not set\n# CONFIG_PACKAGE_kmod-usb-ohci is not set\n# CONFIG_PACKAGE_kmod-usb-ohci-pci is not set\n# CONFIG_PACKAGE_kmod-usb-printer is not set\n# CONFIG_PACKAGE_kmod-usb-serial is not set\n# CONFIG_PACKAGE_kmod-usb-serial-ark3116 is not set\n# CONFIG_PACKAGE_kmod-usb-serial-belkin is not set\n# CONFIG_PACKAGE_kmod-usb-serial-ch341 is not set\n# CONFIG_PACKAGE_kmod-usb-serial-cp210x is not set\n# CONFIG_PACKAGE_kmod-usb-serial-cypress-m8 is not set\n# CONFIG_PACKAGE_kmod-usb-serial-edgeport is not set\n# CONFIG_PACKAGE_kmod-usb-serial-ftdi is not set\n# CONFIG_PACKAGE_kmod-usb-serial-garmin is not set\n# CONFIG_PACKAGE_kmod-usb-serial-ipw is not set\n# CONFIG_PACKAGE_kmod-usb-serial-keyspan is not set\n# CONFIG_PACKAGE_kmod-usb-serial-mct is not set\n# CONFIG_PACKAGE_kmod-usb-serial-mos7720 is not set\n# CONFIG_PACKAGE_kmod-usb-serial-mos7840 is not set\n# CONFIG_PACKAGE_kmod-usb-serial-option is not set\n# CONFIG_PACKAGE_kmod-usb-serial-oti6858 is not set\n# CONFIG_PACKAGE_kmod-usb-serial-pl2303 is not set\n# CONFIG_PACKAGE_kmod-usb-serial-qualcomm is not set\n# CONFIG_PACKAGE_kmod-usb-serial-sierrawireless is not set\n# CONFIG_PACKAGE_kmod-usb-serial-simple is not set\n# CONFIG_PACKAGE_kmod-usb-serial-ti-usb is not set\n# CONFIG_PACKAGE_kmod-usb-serial-visor is not set\n# CONFIG_PACKAGE_kmod-usb-storage is not set\n# CONFIG_PACKAGE_kmod-usb-storage-extras is not set\n# CONFIG_PACKAGE_kmod-usb-storage-uas is not set\n# CONFIG_PACKAGE_kmod-usb-uhci is not set\n# CONFIG_PACKAGE_kmod-usb-wdm is not set\n# CONFIG_PACKAGE_kmod-usb-yealink is not set\n# CONFIG_PACKAGE_kmod-usb2 is not set\n# CONFIG_PACKAGE_kmod-usb2-pci is not set\n# CONFIG_PACKAGE_kmod-usb3 is not set\n# CONFIG_PACKAGE_kmod-usbip is not set\n# CONFIG_PACKAGE_kmod-usbip-client is not set\n# CONFIG_PACKAGE_kmod-usbip-server is not set\n# CONFIG_PACKAGE_kmod-usbmon is not set\n# end of USB Support\n\n#\n# Video Support\n#\n# CONFIG_PACKAGE_kmod-backlight-pwm is not set\n# CONFIG_PACKAGE_kmod-drm-kms-helper is not set\n# CONFIG_PACKAGE_kmod-drm-ttm is not set\n# CONFIG_PACKAGE_kmod-fb is not set\n# CONFIG_PACKAGE_kmod-fb-cfb-copyarea is not set\n# CONFIG_PACKAGE_kmod-fb-cfb-fillrect is not set\n# CONFIG_PACKAGE_kmod-fb-cfb-imgblt is not set\n# CONFIG_PACKAGE_kmod-fb-sys-fops is not set\n# CONFIG_PACKAGE_kmod-fb-sys-ram is not set\n# CONFIG_PACKAGE_kmod-fb-tft is not set\n# CONFIG_PACKAGE_kmod-fb-tft-ili9486 is not set\n# CONFIG_PACKAGE_kmod-video-core is not set\n# CONFIG_PACKAGE_kmod-v4l2loopback is not set\n# end of Video Support\n\n#\n# Virtualization\n#\n# end of Virtualization\n\n#\n# Voice over IP\n#\n# CONFIG_PACKAGE_kmod-dahdi is not set\n# end of Voice over IP\n\n#\n# W1 support\n#\n# CONFIG_PACKAGE_kmod-w1 is not set\n# end of W1 support\n\n#\n# WPAN 802.15.4 Support\n#\n# CONFIG_PACKAGE_kmod-at86rf230 is not set\n# CONFIG_PACKAGE_kmod-atusb is not set\n# CONFIG_PACKAGE_kmod-ca8210 is not set\n# CONFIG_PACKAGE_kmod-cc2520 is not set\n# CONFIG_PACKAGE_kmod-fakelb is not set\n# CONFIG_PACKAGE_kmod-ieee802154 is not set\n# CONFIG_PACKAGE_kmod-ieee802154-6lowpan is not set\n# CONFIG_PACKAGE_kmod-mac802154 is not set\n# CONFIG_PACKAGE_kmod-mrf24j40 is not set\n# end of WPAN 802.15.4 Support\n\n#\n# Wireless Drivers\n#\n# CONFIG_PACKAGE_kmod-adm8211 is not set\n# CONFIG_PACKAGE_kmod-ar5523 is not set\n# CONFIG_PACKAGE_kmod-ath is not set\n# CONFIG_PACKAGE_kmod-ath10k is not set\n# CONFIG_PACKAGE_kmod-ath10k-ct is not set\n# CONFIG_PACKAGE_kmod-ath10k-ct-smallbuffers is not set\n# CONFIG_PACKAGE_kmod-ath5k is not set\n# CONFIG_PACKAGE_kmod-ath6kl-sdio is not set\n# CONFIG_PACKAGE_kmod-ath6kl-usb is not set\n# CONFIG_PACKAGE_kmod-ath9k is not set\n# CONFIG_PACKAGE_kmod-ath9k-htc is not set\n# CONFIG_PACKAGE_kmod-b43 is not set\n# CONFIG_PACKAGE_kmod-b43legacy is not set\n# CONFIG_PACKAGE_kmod-brcmfmac is not set\n# CONFIG_PACKAGE_kmod-brcmsmac is not set\n# CONFIG_PACKAGE_kmod-brcmutil is not set\n# CONFIG_PACKAGE_kmod-carl9170 is not set\nCONFIG_PACKAGE_kmod-cfg80211=y\n# CONFIG_PACKAGE_CFG80211_TESTMODE is not set\n# CONFIG_PACKAGE_kmod-hermes is not set\n# CONFIG_PACKAGE_kmod-hermes-pci is not set\n# CONFIG_PACKAGE_kmod-hermes-plx is not set\n# CONFIG_PACKAGE_kmod-ipw2100 is not set\n# CONFIG_PACKAGE_kmod-ipw2200 is not set\n# CONFIG_PACKAGE_kmod-iwl-legacy is not set\n# CONFIG_PACKAGE_kmod-iwl3945 is not set\n# CONFIG_PACKAGE_kmod-iwl4965 is not set\n# CONFIG_PACKAGE_kmod-iwlwifi is not set\n# CONFIG_PACKAGE_kmod-lib80211 is not set\n# CONFIG_PACKAGE_kmod-libertas-sdio is not set\n# CONFIG_PACKAGE_kmod-libertas-spi is not set\n# CONFIG_PACKAGE_kmod-libertas-usb is not set\n# CONFIG_PACKAGE_kmod-libipw is not set\nCONFIG_PACKAGE_kmod-mac80211=y\nCONFIG_PACKAGE_MAC80211_DEBUGFS=y\n# CONFIG_PACKAGE_MAC80211_TRACING is not set\nCONFIG_PACKAGE_MAC80211_MESH=y\n# CONFIG_PACKAGE_kmod-mac80211-hwsim is not set\n# CONFIG_PACKAGE_kmod-mt76 is not set\n# CONFIG_PACKAGE_kmod-mt7601u is not set\n# CONFIG_PACKAGE_kmod-mt7603 is not set\n# CONFIG_PACKAGE_kmod-mt7615-firmware is not set\n# CONFIG_PACKAGE_kmod-mt7615e is not set\n# CONFIG_PACKAGE_kmod-mt7663-firmware-ap is not set\n# CONFIG_PACKAGE_kmod-mt7663-firmware-sta is not set\n# CONFIG_PACKAGE_kmod-mt7663s is not set\n# CONFIG_PACKAGE_kmod-mt7663u is not set\n# CONFIG_PACKAGE_kmod-mt76x0e is not set\n# CONFIG_PACKAGE_kmod-mt76x0u is not set\n# CONFIG_PACKAGE_kmod-mt76x2 is not set\n# CONFIG_PACKAGE_kmod-mt76x2u is not set\n# CONFIG_PACKAGE_kmod-mt7915e is not set\n# CONFIG_PACKAGE_kmod-mt7921e is not set\n# CONFIG_PACKAGE_kmod-mt7921s is not set\n# CONFIG_PACKAGE_kmod-mwifiex-pcie is not set\n# CONFIG_PACKAGE_kmod-mwifiex-sdio is not set\n# CONFIG_PACKAGE_kmod-mwl8k is not set\n# CONFIG_PACKAGE_kmod-net-prism54 is not set\n# CONFIG_PACKAGE_kmod-net-rtl8192su is not set\n# CONFIG_PACKAGE_kmod-owl-loader is not set\n# CONFIG_PACKAGE_kmod-p54-common is not set\n# CONFIG_PACKAGE_kmod-p54-pci is not set\n# CONFIG_PACKAGE_kmod-p54-usb is not set\n# CONFIG_PACKAGE_kmod-rsi91x is not set\n# CONFIG_PACKAGE_kmod-rsi91x-sdio is not set\n# CONFIG_PACKAGE_kmod-rsi91x-usb is not set\n# CONFIG_PACKAGE_kmod-rt2400-pci is not set\n# CONFIG_PACKAGE_kmod-rt2500-pci is not set\n# CONFIG_PACKAGE_kmod-rt2500-usb is not set\n# CONFIG_PACKAGE_kmod-rt2800-pci is not set\n# CONFIG_PACKAGE_kmod-rt2800-usb is not set\n# CONFIG_PACKAGE_kmod-rt2x00-lib is not set\n# CONFIG_PACKAGE_kmod-rt61-pci is not set\n# CONFIG_PACKAGE_kmod-rt73-usb is not set\n# CONFIG_PACKAGE_kmod-rtl8180 is not set\n# CONFIG_PACKAGE_kmod-rtl8187 is not set\n# CONFIG_PACKAGE_kmod-rtl8192ce is not set\n# CONFIG_PACKAGE_kmod-rtl8192cu is not set\n# CONFIG_PACKAGE_kmod-rtl8192de is not set\n# CONFIG_PACKAGE_kmod-rtl8192se is not set\n# CONFIG_PACKAGE_kmod-rtl8723bs is not set\nCONFIG_PACKAGE_kmod-rtl8812au-ct=y\nCONFIG_PACKAGE_kmod-rtl8821ae=y\nCONFIG_PACKAGE_kmod-rtl8xxxu=y\nCONFIG_PACKAGE_kmod-rtlwifi=y\n# CONFIG_PACKAGE_RTLWIFI_DEBUG is not set\nCONFIG_PACKAGE_kmod-rtlwifi-btcoexist=y\nCONFIG_PACKAGE_kmod-rtlwifi-pci=y\n# CONFIG_PACKAGE_kmod-rtw88 is not set\n# CONFIG_PACKAGE_kmod-wil6210 is not set\n# CONFIG_PACKAGE_kmod-wl12xx is not set\n# CONFIG_PACKAGE_kmod-wl18xx is not set\n# CONFIG_PACKAGE_kmod-wlcore is not set\n# CONFIG_PACKAGE_kmod-zd1211rw is not set\n# end of Wireless Drivers\n# end of Kernel modules\n\n#\n# Languages\n#\n\n#\n# Erlang\n#\n# CONFIG_PACKAGE_erlang is not set\n# CONFIG_PACKAGE_erlang-asn1 is not set\n# CONFIG_PACKAGE_erlang-compiler is not set\n# CONFIG_PACKAGE_erlang-crypto is not set\n# CONFIG_PACKAGE_erlang-erl-interface is not set\n# CONFIG_PACKAGE_erlang-hipe is not set\n# CONFIG_PACKAGE_erlang-inets is not set\n# CONFIG_PACKAGE_erlang-mnesia is not set\n# CONFIG_PACKAGE_erlang-os_mon is not set\n# CONFIG_PACKAGE_erlang-public-key is not set\n# CONFIG_PACKAGE_erlang-reltool is not set\n# CONFIG_PACKAGE_erlang-runtime-tools is not set\n# CONFIG_PACKAGE_erlang-snmp is not set\n# CONFIG_PACKAGE_erlang-ssh is not set\n# CONFIG_PACKAGE_erlang-ssl is not set\n# CONFIG_PACKAGE_erlang-syntax-tools is not set\n# CONFIG_PACKAGE_erlang-tools is not set\n# CONFIG_PACKAGE_erlang-xmerl is not set\n# end of Erlang\n\n#\n# Go\n#\n# CONFIG_PACKAGE_golang is not set\n\n#\n# Configuration\n#\nCONFIG_GOLANG_EXTERNAL_BOOTSTRAP_ROOT=\"\"\nCONFIG_GOLANG_BUILD_CACHE_DIR=\"\"\n# CONFIG_GOLANG_MOD_CACHE_WORLD_READABLE is not set\n# end of Configuration\n\n# CONFIG_PACKAGE_golang-doc is not set\n# CONFIG_PACKAGE_golang-github-jedisct1-dnscrypt-proxy2-dev is not set\n# CONFIG_PACKAGE_golang-github-nextdns-nextdns-dev is not set\n# CONFIG_PACKAGE_golang-gitlab-yawning-obfs4-dev is not set\n# CONFIG_PACKAGE_golang-src is not set\n# CONFIG_PACKAGE_golang-torproject-tor-fw-helper-dev is not set\n# end of Go\n\n#\n# Lua\n#\n# CONFIG_PACKAGE_dkjson is not set\n# CONFIG_PACKAGE_json4lua is not set\n# CONFIG_PACKAGE_ldbus is not set\nCONFIG_PACKAGE_libiwinfo-lua=y\n# CONFIG_PACKAGE_linotify is not set\n# CONFIG_PACKAGE_lpeg is not set\n# CONFIG_PACKAGE_lsqlite3 is not set\nCONFIG_PACKAGE_lua=y\n# CONFIG_PACKAGE_lua-argparse is not set\n# CONFIG_PACKAGE_lua-bencode is not set\n# CONFIG_PACKAGE_lua-bit32 is not set\n# CONFIG_PACKAGE_lua-cjson is not set\n# CONFIG_PACKAGE_lua-copas is not set\n# CONFIG_PACKAGE_lua-coxpcall is not set\n# CONFIG_PACKAGE_lua-curl-v3 is not set\n# CONFIG_PACKAGE_lua-ev is not set\n# CONFIG_PACKAGE_lua-examples is not set\n# CONFIG_PACKAGE_lua-libmodbus is not set\n# CONFIG_PACKAGE_lua-lzlib is not set\n# CONFIG_PACKAGE_lua-md5 is not set\n# CONFIG_PACKAGE_lua-mobdebug is not set\n# CONFIG_PACKAGE_lua-mosquitto is not set\n# CONFIG_PACKAGE_lua-openssl is not set\n# CONFIG_PACKAGE_lua-penlight is not set\n# CONFIG_PACKAGE_lua-rings is not set\n# CONFIG_PACKAGE_lua-rs232 is not set\n# CONFIG_PACKAGE_lua-sha2 is not set\n# CONFIG_PACKAGE_lua-wsapi-base is not set\n# CONFIG_PACKAGE_lua-wsapi-xavante is not set\n# CONFIG_PACKAGE_lua-xavante is not set\n# CONFIG_PACKAGE_lua5.3 is not set\n# CONFIG_PACKAGE_luabitop is not set\n# CONFIG_PACKAGE_luac is not set\n# CONFIG_PACKAGE_luac5.3 is not set\n# CONFIG_PACKAGE_luaexpat is not set\n# CONFIG_PACKAGE_luafilesystem is not set\n# CONFIG_PACKAGE_luajit is not set\n# CONFIG_PACKAGE_lualanes is not set\n# CONFIG_PACKAGE_luaossl is not set\n# CONFIG_PACKAGE_luaposix is not set\n# CONFIG_PACKAGE_luarocks is not set\n# CONFIG_PACKAGE_luasec is not set\n# CONFIG_PACKAGE_luasoap is not set\n# CONFIG_PACKAGE_luasocket is not set\n# CONFIG_PACKAGE_luasocket5.3 is not set\n# CONFIG_PACKAGE_luasql-mysql is not set\n# CONFIG_PACKAGE_luasql-pgsql is not set\n# CONFIG_PACKAGE_luasql-sqlite3 is not set\n# CONFIG_PACKAGE_luasrcdiet is not set\n# CONFIG_PACKAGE_luv is not set\n# CONFIG_PACKAGE_lyaml is not set\n# CONFIG_PACKAGE_lzmq is not set\n# CONFIG_PACKAGE_uuid is not set\n# end of Lua\n\n#\n# Node.js\n#\n# CONFIG_PACKAGE_node is not set\n# CONFIG_PACKAGE_node-arduino-firmata is not set\n# CONFIG_PACKAGE_node-cylon is not set\n# CONFIG_PACKAGE_node-cylon-firmata is not set\n# CONFIG_PACKAGE_node-cylon-gpio is not set\n# CONFIG_PACKAGE_node-cylon-i2c is not set\n# CONFIG_PACKAGE_node-hid is not set\n# CONFIG_PACKAGE_node-homebridge is not set\n# CONFIG_PACKAGE_node-javascript-obfuscator is not set\n# CONFIG_PACKAGE_node-npm is not set\n# CONFIG_PACKAGE_node-serialport is not set\n# CONFIG_PACKAGE_node-serialport-bindings is not set\n# end of Node.js\n\n#\n# PHP7\n#\n# CONFIG_PACKAGE_php7 is not set\n# end of PHP7\n\n#\n# PHP8\n#\n# CONFIG_PACKAGE_php8 is not set\n# end of PHP8\n\n#\n# Perl\n#\n# CONFIG_PACKAGE_perl is not set\n# end of Perl\n\n#\n# Python\n#\n# CONFIG_PACKAGE_libpython3 is not set\n# CONFIG_PACKAGE_micropython is not set\n# CONFIG_PACKAGE_micropython-lib is not set\n# CONFIG_PACKAGE_python-pip-conf is not set\n# CONFIG_PACKAGE_python3 is not set\n# CONFIG_PACKAGE_python3-aiohttp is not set\n# CONFIG_PACKAGE_python3-aiohttp-cors is not set\n# CONFIG_PACKAGE_python3-apipkg is not set\n# CONFIG_PACKAGE_python3-apparmor is not set\n# CONFIG_PACKAGE_python3-appdirs is not set\n# CONFIG_PACKAGE_python3-asgiref is not set\n# CONFIG_PACKAGE_python3-asn1crypto is not set\n# CONFIG_PACKAGE_python3-astral is not set\n# CONFIG_PACKAGE_python3-async-timeout is not set\n# CONFIG_PACKAGE_python3-asyncio is not set\n# CONFIG_PACKAGE_python3-atomicwrites is not set\n# CONFIG_PACKAGE_python3-attrs is not set\n# CONFIG_PACKAGE_python3-augeas is not set\n# CONFIG_PACKAGE_python3-automat is not set\n# CONFIG_PACKAGE_python3-awesomeversion is not set\n# CONFIG_PACKAGE_python3-awscli is not set\n# CONFIG_PACKAGE_python3-babel is not set\n# CONFIG_PACKAGE_python3-base is not set\n# CONFIG_PACKAGE_python3-bcrypt is not set\n# CONFIG_PACKAGE_python3-bidict is not set\n# CONFIG_PACKAGE_python3-boto3 is not set\n# CONFIG_PACKAGE_python3-botocore is not set\n# CONFIG_PACKAGE_python3-bottle is not set\n# CONFIG_PACKAGE_python3-cached-property is not set\n# CONFIG_PACKAGE_python3-cachelib is not set\n# CONFIG_PACKAGE_python3-cachetools is not set\n# CONFIG_PACKAGE_python3-certifi is not set\n# CONFIG_PACKAGE_python3-cffi is not set\n# CONFIG_PACKAGE_python3-cgi is not set\n# CONFIG_PACKAGE_python3-cgitb is not set\n# CONFIG_PACKAGE_python3-chardet is not set\n# CONFIG_PACKAGE_python3-ciso8601 is not set\n# CONFIG_PACKAGE_python3-click is not set\n# CONFIG_PACKAGE_python3-click-log is not set\n# CONFIG_PACKAGE_python3-codecs is not set\n# CONFIG_PACKAGE_python3-colorama is not set\n# CONFIG_PACKAGE_python3-constantly is not set\n# CONFIG_PACKAGE_python3-contextlib2 is not set\n# CONFIG_PACKAGE_python3-cryptodome is not set\n# CONFIG_PACKAGE_python3-cryptodomex is not set\n# CONFIG_PACKAGE_python3-cryptography is not set\n# CONFIG_PACKAGE_python3-ctypes is not set\n# CONFIG_PACKAGE_python3-curl is not set\n# CONFIG_PACKAGE_python3-dateutil is not set\n# CONFIG_PACKAGE_python3-dbm is not set\n# CONFIG_PACKAGE_python3-decimal is not set\n# CONFIG_PACKAGE_python3-decorator is not set\n# CONFIG_PACKAGE_python3-defusedxml is not set\n# CONFIG_PACKAGE_python3-dev is not set\n# CONFIG_PACKAGE_python3-distro is not set\n# CONFIG_PACKAGE_python3-distutils is not set\n# CONFIG_PACKAGE_python3-django is not set\n# CONFIG_PACKAGE_python3-django-appconf is not set\n# CONFIG_PACKAGE_python3-django-compressor is not set\n# CONFIG_PACKAGE_python3-django-cors-headers is not set\n# CONFIG_PACKAGE_python3-django-etesync-journal is not set\n# CONFIG_PACKAGE_python3-django-formtools is not set\n# CONFIG_PACKAGE_python3-django-jsonfield is not set\n# CONFIG_PACKAGE_python3-django-jsonfield2 is not set\n# CONFIG_PACKAGE_python3-django-picklefield is not set\n# CONFIG_PACKAGE_python3-django-postoffice is not set\n# CONFIG_PACKAGE_python3-django-ranged-response is not set\n# CONFIG_PACKAGE_python3-django-restframework is not set\n# CONFIG_PACKAGE_python3-django-restframework39 is not set\n# CONFIG_PACKAGE_python3-django-simple-captcha is not set\n# CONFIG_PACKAGE_python3-django-statici18n is not set\n# CONFIG_PACKAGE_python3-django-webpack-loader is not set\n# CONFIG_PACKAGE_python3-django1 is not set\n# CONFIG_PACKAGE_python3-dns is not set\n# CONFIG_PACKAGE_python3-docker is not set\n# CONFIG_PACKAGE_python3-dockerpty is not set\n# CONFIG_PACKAGE_python3-docopt is not set\n# CONFIG_PACKAGE_python3-docutils is not set\n# CONFIG_PACKAGE_python3-dotenv is not set\n# CONFIG_PACKAGE_python3-drf-nested-routers is not set\n# CONFIG_PACKAGE_python3-email is not set\n# CONFIG_PACKAGE_python3-engineio is not set\n# CONFIG_PACKAGE_python3-et_xmlfile is not set\n# CONFIG_PACKAGE_python3-evdev is not set\n# CONFIG_PACKAGE_python3-eventlet is not set\n# CONFIG_PACKAGE_python3-execnet is not set\n# CONFIG_PACKAGE_python3-flask is not set\n# CONFIG_PACKAGE_python3-flask-babel is not set\n# CONFIG_PACKAGE_python3-flask-httpauth is not set\n# CONFIG_PACKAGE_python3-flask-login is not set\n# CONFIG_PACKAGE_python3-flask-seasurf is not set\n# CONFIG_PACKAGE_python3-flask-session is not set\n# CONFIG_PACKAGE_python3-flask-socketio is not set\n# CONFIG_PACKAGE_python3-flup is not set\n# CONFIG_PACKAGE_python3-gmpy2 is not set\n# CONFIG_PACKAGE_python3-gnupg is not set\n# CONFIG_PACKAGE_python3-gpiod is not set\n# CONFIG_PACKAGE_python3-greenlet is not set\n# CONFIG_PACKAGE_python3-hyperlink is not set\n# CONFIG_PACKAGE_python3-idna is not set\n# CONFIG_PACKAGE_python3-ifaddr is not set\n# CONFIG_PACKAGE_python3-incremental is not set\n# CONFIG_PACKAGE_python3-influxdb is not set\n# CONFIG_PACKAGE_python3-iniconfig is not set\n# CONFIG_PACKAGE_python3-intelhex is not set\n# CONFIG_PACKAGE_python3-itsdangerous is not set\n# CONFIG_PACKAGE_python3-jdcal is not set\n# CONFIG_PACKAGE_python3-jinja2 is not set\n# CONFIG_PACKAGE_python3-jmespath is not set\n# CONFIG_PACKAGE_python3-jsonpath-ng is not set\n# CONFIG_PACKAGE_python3-jsonschema is not set\n# CONFIG_PACKAGE_python3-lib2to3 is not set\n# CONFIG_PACKAGE_python3-libmodbus is not set\n# CONFIG_PACKAGE_python3-libselinux is not set\n# CONFIG_PACKAGE_python3-libsemanage is not set\n# CONFIG_PACKAGE_python3-light is not set\n\n#\n# Configuration\n#\n# CONFIG_PYTHON3_HOST_PIP_CACHE_WORLD_READABLE is not set\n# end of Configuration\n\n# CONFIG_PACKAGE_python3-logging is not set\n# CONFIG_PACKAGE_python3-lxml is not set\n# CONFIG_PACKAGE_python3-lzma is not set\n# CONFIG_PACKAGE_python3-mako is not set\n# CONFIG_PACKAGE_python3-markdown is not set\n# CONFIG_PACKAGE_python3-markupsafe is not set\n# CONFIG_PACKAGE_python3-maxminddb is not set\n# CONFIG_PACKAGE_python3-more-itertools is not set\n# CONFIG_PACKAGE_python3-msgpack is not set\n# CONFIG_PACKAGE_python3-multidict is not set\n# CONFIG_PACKAGE_python3-multiprocessing is not set\n# CONFIG_PACKAGE_python3-ncurses is not set\n# CONFIG_PACKAGE_python3-netdisco is not set\n# CONFIG_PACKAGE_python3-netifaces is not set\n# CONFIG_PACKAGE_python3-networkx is not set\n# CONFIG_PACKAGE_python3-newt is not set\n# CONFIG_PACKAGE_python3-numpy is not set\n\n#\n# Configuration\n#\n# CONFIG_NUMPY_OPENBLAS_SUPPORT is not set\n# end of Configuration\n\n# CONFIG_PACKAGE_python3-oauthlib is not set\n# CONFIG_PACKAGE_python3-openpyxl is not set\n# CONFIG_PACKAGE_python3-openssl is not set\n# CONFIG_PACKAGE_python3-packaging is not set\n# CONFIG_PACKAGE_python3-paho-mqtt is not set\n# CONFIG_PACKAGE_python3-paramiko is not set\n# CONFIG_PACKAGE_python3-parsley is not set\n# CONFIG_PACKAGE_python3-passlib is not set\n# CONFIG_PACKAGE_python3-pillow is not set\n# CONFIG_PACKAGE_python3-pip is not set\n# CONFIG_PACKAGE_python3-pkg-resources is not set\n# CONFIG_PACKAGE_python3-pluggy is not set\n# CONFIG_PACKAGE_python3-ply is not set\n# CONFIG_PACKAGE_python3-psutil is not set\n# CONFIG_PACKAGE_python3-psycopg2 is not set\n# CONFIG_PACKAGE_python3-py is not set\n# CONFIG_PACKAGE_python3-pyasn1 is not set\n# CONFIG_PACKAGE_python3-pyasn1-modules is not set\n# CONFIG_PACKAGE_python3-pycparser is not set\n# CONFIG_PACKAGE_python3-pydoc is not set\n# CONFIG_PACKAGE_python3-pyinotify is not set\n# CONFIG_PACKAGE_python3-pyjwt is not set\n# CONFIG_PACKAGE_python3-pymysql is not set\n# CONFIG_PACKAGE_python3-pynacl is not set\n# CONFIG_PACKAGE_python3-pyodbc is not set\n# CONFIG_PACKAGE_python3-pyopenssl is not set\n# CONFIG_PACKAGE_python3-pyotp is not set\n# CONFIG_PACKAGE_python3-pyparsing is not set\n# CONFIG_PACKAGE_python3-pyroute2 is not set\n# CONFIG_PACKAGE_python3-pyrsistent is not set\n# CONFIG_PACKAGE_python3-pyserial is not set\n# CONFIG_PACKAGE_python3-pysocks is not set\n# CONFIG_PACKAGE_python3-pytest is not set\n# CONFIG_PACKAGE_python3-pytest-forked is not set\n# CONFIG_PACKAGE_python3-pytest-xdist is not set\n# CONFIG_PACKAGE_python3-pytz is not set\n# CONFIG_PACKAGE_python3-qrcode is not set\n# CONFIG_PACKAGE_python3-rcssmin is not set\n# CONFIG_PACKAGE_python3-readline is not set\n# CONFIG_PACKAGE_python3-requests is not set\n# CONFIG_PACKAGE_python3-requests-oauthlib is not set\n# CONFIG_PACKAGE_python3-rsa is not set\n# CONFIG_PACKAGE_python3-ruamel-yaml is not set\n# CONFIG_PACKAGE_python3-s3transfer is not set\n# CONFIG_PACKAGE_python3-schedule is not set\n# CONFIG_PACKAGE_python3-schema is not set\n# CONFIG_PACKAGE_python3-seafile-ccnet is not set\n# CONFIG_PACKAGE_python3-seafile-server is not set\n# CONFIG_PACKAGE_python3-searpc is not set\n# CONFIG_PACKAGE_python3-sentry-sdk is not set\n# CONFIG_PACKAGE_python3-sepolgen is not set\n# CONFIG_PACKAGE_python3-sepolicy is not set\n# CONFIG_PACKAGE_python3-service-identity is not set\n# CONFIG_PACKAGE_python3-setuptools is not set\n# CONFIG_PACKAGE_python3-simplejson is not set\n# CONFIG_PACKAGE_python3-six is not set\n# CONFIG_PACKAGE_python3-slugify is not set\n# CONFIG_PACKAGE_python3-smbus is not set\n# CONFIG_PACKAGE_python3-socketio is not set\n# CONFIG_PACKAGE_python3-speedtest-cli is not set\n# CONFIG_PACKAGE_python3-sqlalchemy is not set\n# CONFIG_PACKAGE_python3-sqlite3 is not set\n# CONFIG_PACKAGE_python3-sqlparse is not set\n# CONFIG_PACKAGE_python3-stem is not set\n# CONFIG_PACKAGE_python3-text-unidecode is not set\n# CONFIG_PACKAGE_python3-texttable is not set\n# CONFIG_PACKAGE_python3-toml is not set\n# CONFIG_PACKAGE_python3-tornado is not set\n# CONFIG_PACKAGE_python3-twisted is not set\n# CONFIG_PACKAGE_python3-typing-extensions is not set\n# CONFIG_PACKAGE_python3-ubus is not set\n# CONFIG_PACKAGE_python3-uci is not set\n# CONFIG_PACKAGE_python3-unidecode is not set\n# CONFIG_PACKAGE_python3-unittest is not set\n# CONFIG_PACKAGE_python3-urllib is not set\n# CONFIG_PACKAGE_python3-urllib3 is not set\n# CONFIG_PACKAGE_python3-uuid is not set\n# CONFIG_PACKAGE_python3-vobject is not set\n# CONFIG_PACKAGE_python3-voluptuous is not set\n# CONFIG_PACKAGE_python3-voluptuous-serialize is not set\n# CONFIG_PACKAGE_python3-wcwidth is not set\n# CONFIG_PACKAGE_python3-websocket-client is not set\n# CONFIG_PACKAGE_python3-websockets is not set\n# CONFIG_PACKAGE_python3-werkzeug is not set\n# CONFIG_PACKAGE_python3-xml is not set\n# CONFIG_PACKAGE_python3-xmltodict is not set\n# CONFIG_PACKAGE_python3-yaml is not set\n# CONFIG_PACKAGE_python3-yarl is not set\n# CONFIG_PACKAGE_python3-zeroconf is not set\n# CONFIG_PACKAGE_python3-zipp is not set\n# CONFIG_PACKAGE_python3-zope-interface is not set\n# end of Python\n\n#\n# Ruby\n#\n# CONFIG_PACKAGE_ruby is not set\n# end of Ruby\n\n#\n# Tcl\n#\n# CONFIG_PACKAGE_tcl is not set\n# end of Tcl\n\n# CONFIG_PACKAGE_chicken-scheme-full is not set\n# CONFIG_PACKAGE_chicken-scheme-interpreter is not set\n# CONFIG_PACKAGE_slsh is not set\n# end of Languages\n\n#\n# Libraries\n#\n\n#\n# Compression\n#\nCONFIG_PACKAGE_libbz2=y\n# CONFIG_PACKAGE_liblz4 is not set\n# CONFIG_PACKAGE_liblzma is not set\n# CONFIG_PACKAGE_libunrar is not set\n# CONFIG_PACKAGE_libzip-gnutls is not set\n# CONFIG_PACKAGE_libzip-mbedtls is not set\n# CONFIG_PACKAGE_libzip-nossl is not set\n# CONFIG_PACKAGE_libzip-openssl is not set\n# CONFIG_PACKAGE_libzstd is not set\n# end of Compression\n\n#\n# Database\n#\n# CONFIG_PACKAGE_libmariadb is not set\n# CONFIG_PACKAGE_libpq is not set\n# CONFIG_PACKAGE_libpqxx is not set\nCONFIG_PACKAGE_libsqlite3=y\n\n#\n# Configuration\n#\n# CONFIG_SQLITE3_BATCH_ATOMIC_WRITE is not set\nCONFIG_SQLITE3_DYNAMIC_EXTENSIONS=y\nCONFIG_SQLITE3_FTS3=y\nCONFIG_SQLITE3_FTS4=y\nCONFIG_SQLITE3_FTS5=y\nCONFIG_SQLITE3_JSON1=y\nCONFIG_SQLITE3_RTREE=y\n# CONFIG_SQLITE3_SESSION is not set\n# end of Configuration\n\n# CONFIG_PACKAGE_pgsqlodbc is not set\n# CONFIG_PACKAGE_psqlodbca is not set\n# CONFIG_PACKAGE_psqlodbcw is not set\n# CONFIG_PACKAGE_redis-cli is not set\n# CONFIG_PACKAGE_redis-server is not set\n# CONFIG_PACKAGE_redis-utils is not set\n# CONFIG_PACKAGE_tdb is not set\n# CONFIG_PACKAGE_unixodbc is not set\n# end of Database\n\n#\n# Filesystem\n#\n# CONFIG_PACKAGE_libacl is not set\nCONFIG_PACKAGE_libattr=y\n# CONFIG_PACKAGE_libfuse is not set\n# CONFIG_PACKAGE_libfuse3 is not set\n# CONFIG_PACKAGE_libow is not set\n# CONFIG_PACKAGE_libow-capi is not set\n# CONFIG_PACKAGE_libsysfs is not set\n# end of Filesystem\n\n#\n# Firewall\n#\n# CONFIG_PACKAGE_libfko is not set\nCONFIG_PACKAGE_libip4tc=y\nCONFIG_PACKAGE_libip6tc=y\nCONFIG_PACKAGE_libxtables=y\n# CONFIG_PACKAGE_libxtables-nft is not set\n# end of Firewall\n\n#\n# Instant Messaging\n#\n# CONFIG_PACKAGE_quasselc is not set\n# end of Instant Messaging\n\n#\n# IoT\n#\n# CONFIG_PACKAGE_libmraa is not set\n# CONFIG_PACKAGE_libmraa-python3 is not set\n# CONFIG_PACKAGE_libupm is not set\n# CONFIG_PACKAGE_libupm-a110x is not set\n# CONFIG_PACKAGE_libupm-a110x-python3 is not set\n# CONFIG_PACKAGE_libupm-abp is not set\n# CONFIG_PACKAGE_libupm-abp-python3 is not set\n# CONFIG_PACKAGE_libupm-ad8232 is not set\n# CONFIG_PACKAGE_libupm-ad8232-python3 is not set\n# CONFIG_PACKAGE_libupm-adafruitms1438 is not set\n# CONFIG_PACKAGE_libupm-adafruitms1438-python3 is not set\n# CONFIG_PACKAGE_libupm-adafruitss is not set\n# CONFIG_PACKAGE_libupm-adafruitss-python3 is not set\n# CONFIG_PACKAGE_libupm-adc121c021 is not set\n# CONFIG_PACKAGE_libupm-adc121c021-python3 is not set\n# CONFIG_PACKAGE_libupm-adis16448 is not set\n# CONFIG_PACKAGE_libupm-adis16448-python3 is not set\n# CONFIG_PACKAGE_libupm-ads1x15 is not set\n# CONFIG_PACKAGE_libupm-ads1x15-python3 is not set\n# CONFIG_PACKAGE_libupm-adxl335 is not set\n# CONFIG_PACKAGE_libupm-adxl335-python3 is not set\n# CONFIG_PACKAGE_libupm-adxl345 is not set\n# CONFIG_PACKAGE_libupm-adxl345-python3 is not set\n# CONFIG_PACKAGE_libupm-adxrs610 is not set\n# CONFIG_PACKAGE_libupm-adxrs610-python3 is not set\n# CONFIG_PACKAGE_libupm-am2315 is not set\n# CONFIG_PACKAGE_libupm-am2315-python3 is not set\n# CONFIG_PACKAGE_libupm-apa102 is not set\n# CONFIG_PACKAGE_libupm-apa102-python3 is not set\n# CONFIG_PACKAGE_libupm-apds9002 is not set\n# CONFIG_PACKAGE_libupm-apds9002-python3 is not set\n# CONFIG_PACKAGE_libupm-apds9930 is not set\n# CONFIG_PACKAGE_libupm-apds9930-python3 is not set\n# CONFIG_PACKAGE_libupm-at42qt1070 is not set\n# CONFIG_PACKAGE_libupm-at42qt1070-python3 is not set\n# CONFIG_PACKAGE_libupm-bh1749 is not set\n# CONFIG_PACKAGE_libupm-bh1749-python3 is not set\n# CONFIG_PACKAGE_libupm-bh1750 is not set\n# CONFIG_PACKAGE_libupm-bh1750-python3 is not set\n# CONFIG_PACKAGE_libupm-bh1792 is not set\n# CONFIG_PACKAGE_libupm-bh1792-python3 is not set\n# CONFIG_PACKAGE_libupm-biss0001 is not set\n# CONFIG_PACKAGE_libupm-biss0001-python3 is not set\n# CONFIG_PACKAGE_libupm-bma220 is not set\n# CONFIG_PACKAGE_libupm-bma220-python3 is not set\n# CONFIG_PACKAGE_libupm-bma250e is not set\n# CONFIG_PACKAGE_libupm-bma250e-python3 is not set\n# CONFIG_PACKAGE_libupm-bmg160 is not set\n# CONFIG_PACKAGE_libupm-bmg160-python3 is not set\n# CONFIG_PACKAGE_libupm-bmi160 is not set\n# CONFIG_PACKAGE_libupm-bmi160-python3 is not set\n# CONFIG_PACKAGE_libupm-bmm150 is not set\n# CONFIG_PACKAGE_libupm-bmm150-python3 is not set\n# CONFIG_PACKAGE_libupm-bmp280 is not set\n# CONFIG_PACKAGE_libupm-bmp280-python3 is not set\n# CONFIG_PACKAGE_libupm-bmpx8x is not set\n# CONFIG_PACKAGE_libupm-bmpx8x-python3 is not set\n# CONFIG_PACKAGE_libupm-bmx055 is not set\n# CONFIG_PACKAGE_libupm-bmx055-python3 is not set\n# CONFIG_PACKAGE_libupm-bno055 is not set\n# CONFIG_PACKAGE_libupm-bno055-python3 is not set\n# CONFIG_PACKAGE_libupm-button is not set\n# CONFIG_PACKAGE_libupm-button-python3 is not set\n# CONFIG_PACKAGE_libupm-buzzer is not set\n# CONFIG_PACKAGE_libupm-buzzer-python3 is not set\n# CONFIG_PACKAGE_libupm-cjq4435 is not set\n# CONFIG_PACKAGE_libupm-cjq4435-python3 is not set\n# CONFIG_PACKAGE_libupm-collision is not set\n# CONFIG_PACKAGE_libupm-collision-python3 is not set\n# CONFIG_PACKAGE_libupm-curieimu is not set\n# CONFIG_PACKAGE_libupm-curieimu-python3 is not set\n# CONFIG_PACKAGE_libupm-cwlsxxa is not set\n# CONFIG_PACKAGE_libupm-cwlsxxa-python3 is not set\n# CONFIG_PACKAGE_libupm-dfrec is not set\n# CONFIG_PACKAGE_libupm-dfrec-python3 is not set\n# CONFIG_PACKAGE_libupm-dfrorp is not set\n# CONFIG_PACKAGE_libupm-dfrorp-python3 is not set\n# CONFIG_PACKAGE_libupm-dfrph is not set\n# CONFIG_PACKAGE_libupm-dfrph-python3 is not set\n# CONFIG_PACKAGE_libupm-ds1307 is not set\n# CONFIG_PACKAGE_libupm-ds1307-python3 is not set\n# CONFIG_PACKAGE_libupm-ds1808lc is not set\n# CONFIG_PACKAGE_libupm-ds1808lc-python3 is not set\n# CONFIG_PACKAGE_libupm-ds18b20 is not set\n# CONFIG_PACKAGE_libupm-ds18b20-python3 is not set\n# CONFIG_PACKAGE_libupm-ds2413 is not set\n# CONFIG_PACKAGE_libupm-ds2413-python3 is not set\n# CONFIG_PACKAGE_libupm-ecezo is not set\n# CONFIG_PACKAGE_libupm-ecezo-python3 is not set\n# CONFIG_PACKAGE_libupm-ecs1030 is not set\n# CONFIG_PACKAGE_libupm-ecs1030-python3 is not set\n# CONFIG_PACKAGE_libupm-ehr is not set\n# CONFIG_PACKAGE_libupm-ehr-python3 is not set\n# CONFIG_PACKAGE_libupm-eldriver is not set\n# CONFIG_PACKAGE_libupm-eldriver-python3 is not set\n# CONFIG_PACKAGE_libupm-electromagnet is not set\n# CONFIG_PACKAGE_libupm-electromagnet-python3 is not set\n# CONFIG_PACKAGE_libupm-emg is not set\n# CONFIG_PACKAGE_libupm-emg-python3 is not set\n# CONFIG_PACKAGE_libupm-enc03r is not set\n# CONFIG_PACKAGE_libupm-enc03r-python3 is not set\n# CONFIG_PACKAGE_libupm-flex is not set\n# CONFIG_PACKAGE_libupm-flex-python3 is not set\n# CONFIG_PACKAGE_libupm-gas is not set\n# CONFIG_PACKAGE_libupm-gas-python3 is not set\n# CONFIG_PACKAGE_libupm-gp2y0a is not set\n# CONFIG_PACKAGE_libupm-gp2y0a-python3 is not set\n# CONFIG_PACKAGE_libupm-gprs is not set\n# CONFIG_PACKAGE_libupm-gprs-python3 is not set\n# CONFIG_PACKAGE_libupm-gsr is not set\n# CONFIG_PACKAGE_libupm-gsr-python3 is not set\n# CONFIG_PACKAGE_libupm-guvas12d is not set\n# CONFIG_PACKAGE_libupm-guvas12d-python3 is not set\n# CONFIG_PACKAGE_libupm-h3lis331dl is not set\n# CONFIG_PACKAGE_libupm-h3lis331dl-python3 is not set\n# CONFIG_PACKAGE_libupm-h803x is not set\n# CONFIG_PACKAGE_libupm-h803x-python3 is not set\n# CONFIG_PACKAGE_libupm-hcsr04 is not set\n# CONFIG_PACKAGE_libupm-hcsr04-python3 is not set\n# CONFIG_PACKAGE_libupm-hdc1000 is not set\n# CONFIG_PACKAGE_libupm-hdc1000-python3 is not set\n# CONFIG_PACKAGE_libupm-hdxxvxta is not set\n# CONFIG_PACKAGE_libupm-hdxxvxta-python3 is not set\n# CONFIG_PACKAGE_libupm-hka5 is not set\n# CONFIG_PACKAGE_libupm-hka5-python3 is not set\n# CONFIG_PACKAGE_libupm-hlg150h is not set\n# CONFIG_PACKAGE_libupm-hlg150h-python3 is not set\n# CONFIG_PACKAGE_libupm-hm11 is not set\n# CONFIG_PACKAGE_libupm-hm11-python3 is not set\n# CONFIG_PACKAGE_libupm-hmc5883l is not set\n# CONFIG_PACKAGE_libupm-hmc5883l-python3 is not set\n# CONFIG_PACKAGE_libupm-hmtrp is not set\n# CONFIG_PACKAGE_libupm-hmtrp-python3 is not set\n# CONFIG_PACKAGE_libupm-hp20x is not set\n# CONFIG_PACKAGE_libupm-hp20x-python3 is not set\n# CONFIG_PACKAGE_libupm-ht9170 is not set\n# CONFIG_PACKAGE_libupm-ht9170-python3 is not set\n# CONFIG_PACKAGE_libupm-htu21d is not set\n# CONFIG_PACKAGE_libupm-htu21d-python3 is not set\n# CONFIG_PACKAGE_libupm-hwxpxx is not set\n# CONFIG_PACKAGE_libupm-hwxpxx-python3 is not set\n# CONFIG_PACKAGE_libupm-hx711 is not set\n# CONFIG_PACKAGE_libupm-hx711-python3 is not set\n# CONFIG_PACKAGE_libupm-ili9341 is not set\n# CONFIG_PACKAGE_libupm-ili9341-python3 is not set\n# CONFIG_PACKAGE_libupm-ims is not set\n# CONFIG_PACKAGE_libupm-ims-python3 is not set\n# CONFIG_PACKAGE_libupm-ina132 is not set\n# CONFIG_PACKAGE_libupm-ina132-python3 is not set\n# CONFIG_PACKAGE_libupm-interfaces is not set\n# CONFIG_PACKAGE_libupm-interfaces-python3 is not set\n# CONFIG_PACKAGE_libupm-isd1820 is not set\n# CONFIG_PACKAGE_libupm-isd1820-python3 is not set\n# CONFIG_PACKAGE_libupm-itg3200 is not set\n# CONFIG_PACKAGE_libupm-itg3200-python3 is not set\n# CONFIG_PACKAGE_libupm-jhd1313m1 is not set\n# CONFIG_PACKAGE_libupm-jhd1313m1-python3 is not set\n# CONFIG_PACKAGE_libupm-joystick12 is not set\n# CONFIG_PACKAGE_libupm-joystick12-python3 is not set\n# CONFIG_PACKAGE_libupm-kx122 is not set\n# CONFIG_PACKAGE_libupm-kx122-python3 is not set\n# CONFIG_PACKAGE_libupm-kxcjk1013 is not set\n# CONFIG_PACKAGE_libupm-kxcjk1013-python3 is not set\n# CONFIG_PACKAGE_libupm-kxtj3 is not set\n# CONFIG_PACKAGE_libupm-kxtj3-python3 is not set\n# CONFIG_PACKAGE_libupm-l298 is not set\n# CONFIG_PACKAGE_libupm-l298-python3 is not set\n# CONFIG_PACKAGE_libupm-l3gd20 is not set\n# CONFIG_PACKAGE_libupm-l3gd20-python3 is not set\n# CONFIG_PACKAGE_libupm-lcd is not set\n# CONFIG_PACKAGE_libupm-lcd-python3 is not set\n# CONFIG_PACKAGE_libupm-lcdks is not set\n# CONFIG_PACKAGE_libupm-lcdks-python3 is not set\n# CONFIG_PACKAGE_libupm-lcm1602 is not set\n# CONFIG_PACKAGE_libupm-lcm1602-python3 is not set\n# CONFIG_PACKAGE_libupm-ldt0028 is not set\n# CONFIG_PACKAGE_libupm-ldt0028-python3 is not set\n# CONFIG_PACKAGE_libupm-led is not set\n# CONFIG_PACKAGE_libupm-led-python3 is not set\n# CONFIG_PACKAGE_libupm-lidarlitev3 is not set\n# CONFIG_PACKAGE_libupm-lidarlitev3-python3 is not set\n# CONFIG_PACKAGE_libupm-light is not set\n# CONFIG_PACKAGE_libupm-light-python3 is not set\n# CONFIG_PACKAGE_libupm-linefinder is not set\n# CONFIG_PACKAGE_libupm-linefinder-python3 is not set\n# CONFIG_PACKAGE_libupm-lis2ds12 is not set\n# CONFIG_PACKAGE_libupm-lis2ds12-python3 is not set\n# CONFIG_PACKAGE_libupm-lis3dh is not set\n# CONFIG_PACKAGE_libupm-lis3dh-python3 is not set\n# CONFIG_PACKAGE_libupm-lm35 is not set\n# CONFIG_PACKAGE_libupm-lm35-python3 is not set\n# CONFIG_PACKAGE_libupm-lol is not set\n# CONFIG_PACKAGE_libupm-lol-python3 is not set\n# CONFIG_PACKAGE_libupm-loudness is not set\n# CONFIG_PACKAGE_libupm-loudness-python3 is not set\n# CONFIG_PACKAGE_libupm-lp8860 is not set\n# CONFIG_PACKAGE_libupm-lp8860-python3 is not set\n# CONFIG_PACKAGE_libupm-lpd8806 is not set\n# CONFIG_PACKAGE_libupm-lpd8806-python3 is not set\n# CONFIG_PACKAGE_libupm-lsm303agr is not set\n# CONFIG_PACKAGE_libupm-lsm303agr-python3 is not set\n# CONFIG_PACKAGE_libupm-lsm303d is not set\n# CONFIG_PACKAGE_libupm-lsm303d-python3 is not set\n# CONFIG_PACKAGE_libupm-lsm303dlh is not set\n# CONFIG_PACKAGE_libupm-lsm303dlh-python3 is not set\n# CONFIG_PACKAGE_libupm-lsm6ds3h is not set\n# CONFIG_PACKAGE_libupm-lsm6ds3h-python3 is not set\n# CONFIG_PACKAGE_libupm-lsm6dsl is not set\n# CONFIG_PACKAGE_libupm-lsm6dsl-python3 is not set\n# CONFIG_PACKAGE_libupm-lsm9ds0 is not set\n# CONFIG_PACKAGE_libupm-lsm9ds0-python3 is not set\n# CONFIG_PACKAGE_libupm-m24lr64e is not set\n# CONFIG_PACKAGE_libupm-m24lr64e-python3 is not set\n# CONFIG_PACKAGE_libupm-mag3110 is not set\n# CONFIG_PACKAGE_libupm-mag3110-python3 is not set\n# CONFIG_PACKAGE_libupm-max30100 is not set\n# CONFIG_PACKAGE_libupm-max30100-python3 is not set\n# CONFIG_PACKAGE_libupm-max31723 is not set\n# CONFIG_PACKAGE_libupm-max31723-python3 is not set\n# CONFIG_PACKAGE_libupm-max31855 is not set\n# CONFIG_PACKAGE_libupm-max31855-python3 is not set\n# CONFIG_PACKAGE_libupm-max44000 is not set\n# CONFIG_PACKAGE_libupm-max44000-python3 is not set\n# CONFIG_PACKAGE_libupm-max44009 is not set\n# CONFIG_PACKAGE_libupm-max44009-python3 is not set\n# CONFIG_PACKAGE_libupm-max5487 is not set\n# CONFIG_PACKAGE_libupm-max5487-python3 is not set\n# CONFIG_PACKAGE_libupm-maxds3231m is not set\n# CONFIG_PACKAGE_libupm-maxds3231m-python3 is not set\n# CONFIG_PACKAGE_libupm-maxsonarez is not set\n# CONFIG_PACKAGE_libupm-maxsonarez-python3 is not set\n# CONFIG_PACKAGE_libupm-mb704x is not set\n# CONFIG_PACKAGE_libupm-mb704x-python3 is not set\n# CONFIG_PACKAGE_libupm-mcp2515 is not set\n# CONFIG_PACKAGE_libupm-mcp2515-python3 is not set\n# CONFIG_PACKAGE_libupm-mcp9808 is not set\n# CONFIG_PACKAGE_libupm-mcp9808-python3 is not set\n# CONFIG_PACKAGE_libupm-md is not set\n# CONFIG_PACKAGE_libupm-md-python3 is not set\n# CONFIG_PACKAGE_libupm-mg811 is not set\n# CONFIG_PACKAGE_libupm-mg811-python3 is not set\n# CONFIG_PACKAGE_libupm-mhz16 is not set\n# CONFIG_PACKAGE_libupm-mhz16-python3 is not set\n# CONFIG_PACKAGE_libupm-mic is not set\n# CONFIG_PACKAGE_libupm-mic-python3 is not set\n# CONFIG_PACKAGE_libupm-micsv89 is not set\n# CONFIG_PACKAGE_libupm-micsv89-python3 is not set\n# CONFIG_PACKAGE_libupm-mlx90614 is not set\n# CONFIG_PACKAGE_libupm-mlx90614-python3 is not set\n# CONFIG_PACKAGE_libupm-mma7361 is not set\n# CONFIG_PACKAGE_libupm-mma7361-python3 is not set\n# CONFIG_PACKAGE_libupm-mma7455 is not set\n# CONFIG_PACKAGE_libupm-mma7455-python3 is not set\n# CONFIG_PACKAGE_libupm-mma7660 is not set\n# CONFIG_PACKAGE_libupm-mma7660-python3 is not set\n# CONFIG_PACKAGE_libupm-mma8x5x is not set\n# CONFIG_PACKAGE_libupm-mma8x5x-python3 is not set\n# CONFIG_PACKAGE_libupm-mmc35240 is not set\n# CONFIG_PACKAGE_libupm-mmc35240-python3 is not set\n# CONFIG_PACKAGE_libupm-moisture is not set\n# CONFIG_PACKAGE_libupm-moisture-python3 is not set\n# CONFIG_PACKAGE_libupm-mpl3115a2 is not set\n# CONFIG_PACKAGE_libupm-mpl3115a2-python3 is not set\n# CONFIG_PACKAGE_libupm-mpr121 is not set\n# CONFIG_PACKAGE_libupm-mpr121-python3 is not set\n# CONFIG_PACKAGE_libupm-mpu9150 is not set\n# CONFIG_PACKAGE_libupm-mpu9150-python3 is not set\n# CONFIG_PACKAGE_libupm-mq303a is not set\n# CONFIG_PACKAGE_libupm-mq303a-python3 is not set\n# CONFIG_PACKAGE_libupm-ms5611 is not set\n# CONFIG_PACKAGE_libupm-ms5611-python3 is not set\n# CONFIG_PACKAGE_libupm-ms5803 is not set\n# CONFIG_PACKAGE_libupm-ms5803-python3 is not set\n# CONFIG_PACKAGE_libupm-my9221 is not set\n# CONFIG_PACKAGE_libupm-my9221-python3 is not set\n# CONFIG_PACKAGE_libupm-nlgpio16 is not set\n# CONFIG_PACKAGE_libupm-nlgpio16-python3 is not set\n# CONFIG_PACKAGE_libupm-nmea_gps is not set\n# CONFIG_PACKAGE_libupm-nmea_gps-python3 is not set\n# CONFIG_PACKAGE_libupm-nrf24l01 is not set\n# CONFIG_PACKAGE_libupm-nrf24l01-python3 is not set\n# CONFIG_PACKAGE_libupm-nrf8001 is not set\n# CONFIG_PACKAGE_libupm-nrf8001-python3 is not set\n# CONFIG_PACKAGE_libupm-nunchuck is not set\n# CONFIG_PACKAGE_libupm-nunchuck-python3 is not set\n# CONFIG_PACKAGE_libupm-o2 is not set\n# CONFIG_PACKAGE_libupm-o2-python3 is not set\n# CONFIG_PACKAGE_libupm-otp538u is not set\n# CONFIG_PACKAGE_libupm-otp538u-python3 is not set\n# CONFIG_PACKAGE_libupm-ozw is not set\n# CONFIG_PACKAGE_libupm-ozw-python3 is not set\n# CONFIG_PACKAGE_libupm-p9813 is not set\n# CONFIG_PACKAGE_libupm-p9813-python3 is not set\n# CONFIG_PACKAGE_libupm-pca9685 is not set\n# CONFIG_PACKAGE_libupm-pca9685-python3 is not set\n# CONFIG_PACKAGE_libupm-pn532 is not set\n# CONFIG_PACKAGE_libupm-pn532-python3 is not set\n# CONFIG_PACKAGE_libupm-ppd42ns is not set\n# CONFIG_PACKAGE_libupm-ppd42ns-python3 is not set\n# CONFIG_PACKAGE_libupm-pulsensor is not set\n# CONFIG_PACKAGE_libupm-pulsensor-python3 is not set\n# CONFIG_PACKAGE_libupm-relay is not set\n# CONFIG_PACKAGE_libupm-relay-python3 is not set\n# CONFIG_PACKAGE_libupm-rf22 is not set\n# CONFIG_PACKAGE_libupm-rf22-python3 is not set\n# CONFIG_PACKAGE_libupm-rfr359f is not set\n# CONFIG_PACKAGE_libupm-rfr359f-python3 is not set\n# CONFIG_PACKAGE_libupm-rgbringcoder is not set\n# CONFIG_PACKAGE_libupm-rgbringcoder-python3 is not set\n# CONFIG_PACKAGE_libupm-rhusb is not set\n# CONFIG_PACKAGE_libupm-rhusb-python3 is not set\n# CONFIG_PACKAGE_libupm-rn2903 is not set\n# CONFIG_PACKAGE_libupm-rn2903-python3 is not set\n# CONFIG_PACKAGE_libupm-rotary is not set\n# CONFIG_PACKAGE_libupm-rotary-python3 is not set\n# CONFIG_PACKAGE_libupm-rotaryencoder is not set\n# CONFIG_PACKAGE_libupm-rotaryencoder-python3 is not set\n# CONFIG_PACKAGE_libupm-rpr220 is not set\n# CONFIG_PACKAGE_libupm-rpr220-python3 is not set\n# CONFIG_PACKAGE_libupm-rsc is not set\n# CONFIG_PACKAGE_libupm-rsc-python3 is not set\n# CONFIG_PACKAGE_libupm-scam is not set\n# CONFIG_PACKAGE_libupm-scam-python3 is not set\n# CONFIG_PACKAGE_libupm-sensortemplate is not set\n# CONFIG_PACKAGE_libupm-sensortemplate-python3 is not set\n# CONFIG_PACKAGE_libupm-servo is not set\n# CONFIG_PACKAGE_libupm-servo-python3 is not set\n# CONFIG_PACKAGE_libupm-sht1x is not set\n# CONFIG_PACKAGE_libupm-sht1x-python3 is not set\n# CONFIG_PACKAGE_libupm-si1132 is not set\n# CONFIG_PACKAGE_libupm-si1132-python3 is not set\n# CONFIG_PACKAGE_libupm-si114x is not set\n# CONFIG_PACKAGE_libupm-si114x-python3 is not set\n# CONFIG_PACKAGE_libupm-si7005 is not set\n# CONFIG_PACKAGE_libupm-si7005-python3 is not set\n# CONFIG_PACKAGE_libupm-slide is not set\n# CONFIG_PACKAGE_libupm-slide-python3 is not set\n# CONFIG_PACKAGE_libupm-sm130 is not set\n# CONFIG_PACKAGE_libupm-sm130-python3 is not set\n# CONFIG_PACKAGE_libupm-smartdrive is not set\n# CONFIG_PACKAGE_libupm-smartdrive-python3 is not set\n# CONFIG_PACKAGE_libupm-speaker is not set\n# CONFIG_PACKAGE_libupm-speaker-python3 is not set\n# CONFIG_PACKAGE_libupm-ssd1351 is not set\n# CONFIG_PACKAGE_libupm-ssd1351-python3 is not set\n# CONFIG_PACKAGE_libupm-st7735 is not set\n# CONFIG_PACKAGE_libupm-st7735-python3 is not set\n# CONFIG_PACKAGE_libupm-stepmotor is not set\n# CONFIG_PACKAGE_libupm-stepmotor-python3 is not set\n# CONFIG_PACKAGE_libupm-sx1276 is not set\n# CONFIG_PACKAGE_libupm-sx1276-python3 is not set\n# CONFIG_PACKAGE_libupm-sx6119 is not set\n# CONFIG_PACKAGE_libupm-sx6119-python3 is not set\n# CONFIG_PACKAGE_libupm-t3311 is not set\n# CONFIG_PACKAGE_libupm-t3311-python3 is not set\n# CONFIG_PACKAGE_libupm-t6713 is not set\n# CONFIG_PACKAGE_libupm-t6713-python3 is not set\n# CONFIG_PACKAGE_libupm-ta12200 is not set\n# CONFIG_PACKAGE_libupm-ta12200-python3 is not set\n# CONFIG_PACKAGE_libupm-tca9548a is not set\n# CONFIG_PACKAGE_libupm-tca9548a-python3 is not set\n# CONFIG_PACKAGE_libupm-tcs3414cs is not set\n# CONFIG_PACKAGE_libupm-tcs3414cs-python3 is not set\n# CONFIG_PACKAGE_libupm-tcs37727 is not set\n# CONFIG_PACKAGE_libupm-tcs37727-python3 is not set\n# CONFIG_PACKAGE_libupm-teams is not set\n# CONFIG_PACKAGE_libupm-teams-python3 is not set\n# CONFIG_PACKAGE_libupm-temperature is not set\n# CONFIG_PACKAGE_libupm-temperature-python3 is not set\n# CONFIG_PACKAGE_libupm-tex00 is not set\n# CONFIG_PACKAGE_libupm-tex00-python3 is not set\n# CONFIG_PACKAGE_libupm-th02 is not set\n# CONFIG_PACKAGE_libupm-th02-python3 is not set\n# CONFIG_PACKAGE_libupm-tm1637 is not set\n# CONFIG_PACKAGE_libupm-tm1637-python3 is not set\n# CONFIG_PACKAGE_libupm-tmp006 is not set\n# CONFIG_PACKAGE_libupm-tmp006-python3 is not set\n# CONFIG_PACKAGE_libupm-tsl2561 is not set\n# CONFIG_PACKAGE_libupm-tsl2561-python3 is not set\n# CONFIG_PACKAGE_libupm-ttp223 is not set\n# CONFIG_PACKAGE_libupm-ttp223-python3 is not set\n# CONFIG_PACKAGE_libupm-uartat is not set\n# CONFIG_PACKAGE_libupm-uartat-python3 is not set\n# CONFIG_PACKAGE_libupm-uln200xa is not set\n# CONFIG_PACKAGE_libupm-uln200xa-python3 is not set\n# CONFIG_PACKAGE_libupm-ultrasonic is not set\n# CONFIG_PACKAGE_libupm-ultrasonic-python3 is not set\n# CONFIG_PACKAGE_libupm-urm37 is not set\n# CONFIG_PACKAGE_libupm-urm37-python3 is not set\n# CONFIG_PACKAGE_libupm-utilities is not set\n# CONFIG_PACKAGE_libupm-utilities-python3 is not set\n# CONFIG_PACKAGE_libupm-vcap is not set\n# CONFIG_PACKAGE_libupm-vcap-python3 is not set\n# CONFIG_PACKAGE_libupm-vdiv is not set\n# CONFIG_PACKAGE_libupm-vdiv-python3 is not set\n# CONFIG_PACKAGE_libupm-veml6070 is not set\n# CONFIG_PACKAGE_libupm-veml6070-python3 is not set\n# CONFIG_PACKAGE_libupm-water is not set\n# CONFIG_PACKAGE_libupm-water-python3 is not set\n# CONFIG_PACKAGE_libupm-waterlevel is not set\n# CONFIG_PACKAGE_libupm-waterlevel-python3 is not set\n# CONFIG_PACKAGE_libupm-wfs is not set\n# CONFIG_PACKAGE_libupm-wfs-python3 is not set\n# CONFIG_PACKAGE_libupm-wheelencoder is not set\n# CONFIG_PACKAGE_libupm-wheelencoder-python3 is not set\n# CONFIG_PACKAGE_libupm-wt5001 is not set\n# CONFIG_PACKAGE_libupm-wt5001-python3 is not set\n# CONFIG_PACKAGE_libupm-xbee is not set\n# CONFIG_PACKAGE_libupm-xbee-python3 is not set\n# CONFIG_PACKAGE_libupm-yg1006 is not set\n# CONFIG_PACKAGE_libupm-yg1006-python3 is not set\n# CONFIG_PACKAGE_libupm-zfm20 is not set\n# CONFIG_PACKAGE_libupm-zfm20-python3 is not set\n# end of IoT\n\n#\n# Languages\n#\n# CONFIG_PACKAGE_libyaml is not set\n# end of Languages\n\n#\n# LibElektra\n#\n# CONFIG_PACKAGE_libelektra-core is not set\n# CONFIG_PACKAGE_libelektra-cpp is not set\n# CONFIG_PACKAGE_libelektra-crypto is not set\n# CONFIG_PACKAGE_libelektra-curlget is not set\n# CONFIG_PACKAGE_libelektra-dbus is not set\n# CONFIG_PACKAGE_libelektra-ev is not set\n# CONFIG_PACKAGE_libelektra-extra is not set\n# CONFIG_PACKAGE_libelektra-lua is not set\n# CONFIG_PACKAGE_libelektra-plugins is not set\n# CONFIG_PACKAGE_libelektra-python3 is not set\n# CONFIG_PACKAGE_libelektra-resolvers is not set\n# CONFIG_PACKAGE_libelektra-uv is not set\n# CONFIG_PACKAGE_libelektra-xerces is not set\n# CONFIG_PACKAGE_libelektra-xml is not set\n# CONFIG_PACKAGE_libelektra-yajl is not set\n# CONFIG_PACKAGE_libelektra-yamlcpp is not set\n# CONFIG_PACKAGE_libelektra-zmq is not set\n# end of LibElektra\n\n#\n# Networking\n#\n# CONFIG_PACKAGE_libdcwproto is not set\n# CONFIG_PACKAGE_libdcwsocket is not set\n# CONFIG_PACKAGE_libsctp is not set\n# CONFIG_PACKAGE_libuhttpd-mbedtls is not set\n# CONFIG_PACKAGE_libuhttpd-nossl is not set\n# CONFIG_PACKAGE_libuhttpd-openssl is not set\n# CONFIG_PACKAGE_libuhttpd-wolfssl is not set\n# CONFIG_PACKAGE_libulfius-gnutls is not set\n# CONFIG_PACKAGE_libulfius-nossl is not set\nCONFIG_PACKAGE_libunbound=y\n# CONFIG_PACKAGE_libunbound_dnscrypt is not set\nCONFIG_PACKAGE_libunbound_ipset=y\nCONFIG_PACKAGE_libunbound_libevent=y\nCONFIG_PACKAGE_libunbound_libpthread=y\n# CONFIG_PACKAGE_libunbound_nghttp2 is not set\n# CONFIG_PACKAGE_libunbound_pythonmodule is not set\n# CONFIG_PACKAGE_libunbound_subnet is not set\n# CONFIG_PACKAGE_libunbound_dnstap is not set\n# CONFIG_PACKAGE_libuwsc-mbedtls is not set\n# CONFIG_PACKAGE_libuwsc-nossl is not set\n# CONFIG_PACKAGE_libuwsc-openssl is not set\n# CONFIG_PACKAGE_libuwsc-wolfssl is not set\n# end of Networking\n\n#\n# SSL\n#\nCONFIG_PACKAGE_libgnutls=y\n\n#\n# Configuration\n#\nCONFIG_GNUTLS_DTLS_SRTP=y\nCONFIG_GNUTLS_ALPN=y\nCONFIG_GNUTLS_OCSP=y\n# CONFIG_GNUTLS_CRYPTODEV is not set\nCONFIG_GNUTLS_HEARTBEAT=y\n# CONFIG_GNUTLS_SRP is not set\nCONFIG_GNUTLS_PSK=y\nCONFIG_GNUTLS_ANON=y\n# CONFIG_GNUTLS_TPM is not set\n# CONFIG_GNUTLS_PKCS11 is not set\n# CONFIG_GNUTLS_EXT_LIBTASN1 is not set\n# end of Configuration\n\n# CONFIG_PACKAGE_libgnutls-dane is not set\nCONFIG_PACKAGE_libmbedtls=y\n# CONFIG_LIBMBEDTLS_DEBUG_C is not set\n# CONFIG_LIBMBEDTLS_HKDF_C is not set\n# CONFIG_PACKAGE_libnss is not set\nCONFIG_PACKAGE_libopenssl=y\n\n#\n# Build Options\n#\n# CONFIG_OPENSSL_OPTIMIZE_SPEED is not set\nCONFIG_OPENSSL_WITH_ASM=y\nCONFIG_OPENSSL_WITH_DEPRECATED=y\n# CONFIG_OPENSSL_NO_DEPRECATED is not set\nCONFIG_OPENSSL_WITH_ERROR_MESSAGES=y\n\n#\n# Protocol Support\n#\nCONFIG_OPENSSL_WITH_TLS13=y\n# CONFIG_OPENSSL_WITH_DTLS is not set\n# CONFIG_OPENSSL_WITH_NPN is not set\nCONFIG_OPENSSL_WITH_SRP=y\nCONFIG_OPENSSL_WITH_CMS=y\n\n#\n# Algorithm Selection\n#\n# CONFIG_OPENSSL_WITH_EC2M is not set\nCONFIG_OPENSSL_WITH_CHACHA_POLY1305=y\n# CONFIG_OPENSSL_PREFER_CHACHA_OVER_GCM is not set\nCONFIG_OPENSSL_WITH_PSK=y\n\n#\n# Less commonly used build options\n#\n# CONFIG_OPENSSL_WITH_ARIA is not set\n# CONFIG_OPENSSL_WITH_CAMELLIA is not set\n# CONFIG_OPENSSL_WITH_IDEA is not set\n# CONFIG_OPENSSL_WITH_SEED is not set\n# CONFIG_OPENSSL_WITH_SM234 is not set\n# CONFIG_OPENSSL_WITH_BLAKE2 is not set\n# CONFIG_OPENSSL_WITH_MDC2 is not set\n# CONFIG_OPENSSL_WITH_WHIRLPOOL is not set\n# CONFIG_OPENSSL_WITH_COMPRESSION is not set\n# CONFIG_OPENSSL_WITH_RFC3779 is not set\n\n#\n# Engine/Hardware Support\n#\nCONFIG_OPENSSL_ENGINE=y\n# CONFIG_OPENSSL_ENGINE_BUILTIN is not set\n# CONFIG_PACKAGE_libopenssl-afalg is not set\n# CONFIG_PACKAGE_libopenssl-afalg_sync is not set\nCONFIG_PACKAGE_libopenssl-conf=y\n# CONFIG_PACKAGE_libopenssl-devcrypto is not set\n# CONFIG_PACKAGE_libopenssl-gost_engine is not set\nCONFIG_PACKAGE_libwolfssl=y\nCONFIG_WOLFSSL_HAS_AES_CCM=y\nCONFIG_WOLFSSL_HAS_CHACHA_POLY=y\nCONFIG_WOLFSSL_HAS_DH=y\nCONFIG_WOLFSSL_HAS_ARC4=y\nCONFIG_WOLFSSL_HAS_CERTGEN=y\nCONFIG_WOLFSSL_HAS_TLSV10=y\nCONFIG_WOLFSSL_HAS_TLSV13=y\nCONFIG_WOLFSSL_HAS_SESSION_TICKET=y\n# CONFIG_WOLFSSL_HAS_DTLS is not set\nCONFIG_WOLFSSL_HAS_OCSP=y\nCONFIG_WOLFSSL_HAS_WPAS=y\n# CONFIG_WOLFSSL_HAS_ECC25519 is not set\n# CONFIG_WOLFSSL_HAS_OPENVPN is not set\nCONFIG_WOLFSSL_HAS_NO_HW=y\n# CONFIG_WOLFSSL_HAS_AFALG is not set\n# CONFIG_WOLFSSL_HAS_DEVCRYPTO_CBC is not set\n# CONFIG_WOLFSSL_HAS_DEVCRYPTO_AES is not set\n# CONFIG_WOLFSSL_HAS_DEVCRYPTO_FULL is not set\n# end of SSL\n\n#\n# Sound\n#\n# CONFIG_PACKAGE_alsa-ucm-conf is not set\n# CONFIG_PACKAGE_liblo is not set\n# end of Sound\n\n#\n# Telephony\n#\n# CONFIG_PACKAGE_bcg729 is not set\n# CONFIG_PACKAGE_dahdi-tools-libtonezone is not set\n# CONFIG_PACKAGE_gsmlib is not set\n# CONFIG_PACKAGE_libctb is not set\n# CONFIG_PACKAGE_libfreetdm is not set\n# CONFIG_PACKAGE_libiksemel is not set\n# CONFIG_PACKAGE_libks is not set\n# CONFIG_PACKAGE_libosip2 is not set\n# CONFIG_PACKAGE_libpj is not set\n# CONFIG_PACKAGE_libpjlib-util is not set\n# CONFIG_PACKAGE_libpjmedia is not set\n# CONFIG_PACKAGE_libpjnath is not set\n# CONFIG_PACKAGE_libpjsip is not set\n# CONFIG_PACKAGE_libpjsip-simple is not set\n# CONFIG_PACKAGE_libpjsip-ua is not set\n# CONFIG_PACKAGE_libpjsua is not set\n# CONFIG_PACKAGE_libpjsua2 is not set\n# CONFIG_PACKAGE_libre is not set\n# CONFIG_PACKAGE_librem is not set\n# CONFIG_PACKAGE_libspandsp is not set\n# CONFIG_PACKAGE_libspandsp3 is not set\n# CONFIG_PACKAGE_libsrtp2 is not set\n# CONFIG_PACKAGE_signalwire-client-c is not set\n# CONFIG_PACKAGE_sofia-sip is not set\n# end of Telephony\n\n#\n# libimobiledevice\n#\n# CONFIG_PACKAGE_libimobiledevice is not set\n# CONFIG_PACKAGE_libirecovery is not set\n# CONFIG_PACKAGE_libplist is not set\n# CONFIG_PACKAGE_libusbmuxd is not set\n# end of libimobiledevice\n\n# CONFIG_PACKAGE_acsccid is not set\n# CONFIG_PACKAGE_alsa-lib is not set\n# CONFIG_PACKAGE_argp-standalone is not set\n# CONFIG_PACKAGE_bind-libs is not set\n# CONFIG_PACKAGE_bluez-libs is not set\n# CONFIG_PACKAGE_boost is not set\n# CONFIG_boost-context-exclude is not set\n# CONFIG_boost-coroutine-exclude is not set\n# CONFIG_boost-fiber-exclude is not set\n# CONFIG_PACKAGE_boringssl is not set\n# CONFIG_PACKAGE_cJSON is not set\n# CONFIG_PACKAGE_ccid is not set\n# CONFIG_PACKAGE_check is not set\nCONFIG_PACKAGE_confuse=y\n# CONFIG_PACKAGE_czmq is not set\n# CONFIG_PACKAGE_dtndht is not set\n# CONFIG_PACKAGE_getdns is not set\n# CONFIG_PACKAGE_giflib is not set\n# CONFIG_PACKAGE_glib2 is not set\n# CONFIG_PACKAGE_google-authenticator-libpam is not set\n# CONFIG_PACKAGE_hidapi is not set\n# CONFIG_PACKAGE_ibrcommon is not set\n# CONFIG_PACKAGE_ibrdtn is not set\n# CONFIG_PACKAGE_icu is not set\n# CONFIG_PACKAGE_icu-data-tools is not set\n# CONFIG_PACKAGE_icu-full-data is not set\n# CONFIG_PACKAGE_jansson is not set\n# CONFIG_PACKAGE_json-glib is not set\n# CONFIG_PACKAGE_jsoncpp is not set\n# CONFIG_PACKAGE_knot-libs is not set\n# CONFIG_PACKAGE_knot-libzscanner is not set\n# CONFIG_PACKAGE_libaio is not set\n# CONFIG_PACKAGE_libantlr3c is not set\n# CONFIG_PACKAGE_libao is not set\n# CONFIG_PACKAGE_libapparmor is not set\n# CONFIG_PACKAGE_libapr is not set\n# CONFIG_PACKAGE_libaprutil is not set\n# CONFIG_PACKAGE_libarchive is not set\n# CONFIG_PACKAGE_libarchive-noopenssl is not set\n# CONFIG_PACKAGE_libasm is not set\n# CONFIG_PACKAGE_libassuan is not set\n# CONFIG_PACKAGE_libatasmart is not set\n# CONFIG_PACKAGE_libaudit is not set\n# CONFIG_PACKAGE_libauparse is not set\nCONFIG_PACKAGE_libavahi-client=y\n# CONFIG_PACKAGE_libavahi-compat-libdnssd is not set\nCONFIG_PACKAGE_libavahi-dbus-support=y\n# CONFIG_PACKAGE_libavahi-nodbus-support is not set\n# CONFIG_PACKAGE_libbfd is not set\nCONFIG_PACKAGE_libblkid=y\nCONFIG_PACKAGE_libblobmsg-json=y\n# CONFIG_PACKAGE_libbpf is not set\n# CONFIG_PACKAGE_libbsd is not set\nCONFIG_PACKAGE_libcap=y\n# CONFIG_PACKAGE_libcap-bin is not set\n# CONFIG_PACKAGE_libcap-ng is not set\nCONFIG_PACKAGE_libcares=y\nCONFIG_PACKAGE_libcbor=y\n# CONFIG_PACKAGE_libcgroup is not set\n# CONFIG_PACKAGE_libcharset is not set\n# CONFIG_PACKAGE_libcoap is not set\nCONFIG_PACKAGE_libcomerr=y\n# CONFIG_PACKAGE_libconfig is not set\n# CONFIG_PACKAGE_libctf is not set\nCONFIG_PACKAGE_libcurl=y\n\n#\n# SSL support\n#\n# CONFIG_LIBCURL_MBEDTLS is not set\nCONFIG_LIBCURL_WOLFSSL=y\n# CONFIG_LIBCURL_OPENSSL is not set\n# CONFIG_LIBCURL_GNUTLS is not set\n# CONFIG_LIBCURL_NOSSL is not set\n\n#\n# Supported protocols\n#\n# CONFIG_LIBCURL_DICT is not set\nCONFIG_LIBCURL_FILE=y\nCONFIG_LIBCURL_FTP=y\n# CONFIG_LIBCURL_GOPHER is not set\nCONFIG_LIBCURL_HTTP=y\nCONFIG_LIBCURL_COOKIES=y\n# CONFIG_LIBCURL_IMAP is not set\n# CONFIG_LIBCURL_LDAP is not set\n# CONFIG_LIBCURL_POP3 is not set\n# CONFIG_LIBCURL_RTSP is not set\n# CONFIG_LIBCURL_SSH2 is not set\nCONFIG_LIBCURL_NO_SMB=\"!\"\n# CONFIG_LIBCURL_SMTP is not set\n# CONFIG_LIBCURL_TELNET is not set\n# CONFIG_LIBCURL_TFTP is not set\n# CONFIG_LIBCURL_NGHTTP2 is not set\n\n#\n# Miscellaneous\n#\nCONFIG_LIBCURL_PROXY=y\n# CONFIG_LIBCURL_CRYPTO_AUTH is not set\n# CONFIG_LIBCURL_TLS_SRP is not set\n# CONFIG_LIBCURL_LIBIDN2 is not set\n# CONFIG_LIBCURL_THREADED_RESOLVER is not set\n# CONFIG_LIBCURL_ZLIB is not set\n# CONFIG_LIBCURL_ZSTD is not set\n# CONFIG_LIBCURL_UNIX_SOCKETS is not set\n# CONFIG_LIBCURL_LIBCURL_OPTION is not set\n# CONFIG_LIBCURL_VERBOSE is not set\nCONFIG_PACKAGE_libdaemon=y\n# CONFIG_PACKAGE_libdaq is not set\n# CONFIG_PACKAGE_libdaq3 is not set\n# CONFIG_PACKAGE_libdb47 is not set\n# CONFIG_PACKAGE_libdb47xx is not set\n# CONFIG_PACKAGE_libdbi is not set\nCONFIG_PACKAGE_libdbus=y\nCONFIG_PACKAGE_libdevmapper=y\n# CONFIG_PACKAGE_libdevmapper-selinux is not set\n# CONFIG_PACKAGE_libdmapsharing is not set\n# CONFIG_PACKAGE_libdnet is not set\n# CONFIG_PACKAGE_libdrm is not set\n# CONFIG_PACKAGE_libdw is not set\n# CONFIG_PACKAGE_libecdsautil is not set\n# CONFIG_PACKAGE_libedit is not set\n# CONFIG_PACKAGE_libelf is not set\n# CONFIG_PACKAGE_libesmtp is not set\n# CONFIG_PACKAGE_libestr is not set\nCONFIG_PACKAGE_libev=y\nCONFIG_PACKAGE_libevdev=y\nCONFIG_PACKAGE_libevent2=y\n# CONFIG_PACKAGE_libevent2-core is not set\n# CONFIG_PACKAGE_libevent2-extra is not set\n# CONFIG_PACKAGE_libevent2-openssl is not set\n# CONFIG_PACKAGE_libevent2-pthreads is not set\nCONFIG_PACKAGE_libexif=y\nCONFIG_PACKAGE_libexpat=y\n# CONFIG_PACKAGE_libexslt is not set\nCONFIG_PACKAGE_libext2fs=y\n# CONFIG_PACKAGE_libextractor is not set\nCONFIG_PACKAGE_libf2fs=y\n# CONFIG_PACKAGE_libf2fs-selinux is not set\n# CONFIG_PACKAGE_libfaad2 is not set\n# CONFIG_PACKAGE_libfastjson is not set\nCONFIG_PACKAGE_libfdisk=y\n# CONFIG_PACKAGE_libfdt is not set\n# CONFIG_PACKAGE_libffi is not set\nCONFIG_PACKAGE_libffmpeg-audio-dec=y\n# CONFIG_PACKAGE_libffmpeg-custom is not set\n# CONFIG_PACKAGE_libffmpeg-full is not set\n# CONFIG_PACKAGE_libffmpeg-mini is not set\nCONFIG_PACKAGE_libfido2=y\nCONFIG_PACKAGE_libflac=y\n# CONFIG_PACKAGE_libfmt is not set\n# CONFIG_PACKAGE_libfreetype is not set\n# CONFIG_PACKAGE_libfstrm is not set\n# CONFIG_PACKAGE_libftdi is not set\n# CONFIG_PACKAGE_libftdi1 is not set\n# CONFIG_PACKAGE_libgabe is not set\n# CONFIG_PACKAGE_libgcrypt is not set\nCONFIG_PACKAGE_libgd=y\n# CONFIG_LIBGD_TIFF is not set\n# CONFIG_LIBGD_FREETYPE is not set\n# CONFIG_PACKAGE_libgd-full is not set\n# CONFIG_PACKAGE_libgdbm is not set\n# CONFIG_PACKAGE_libgee is not set\nCONFIG_PACKAGE_libgmp=y\n# CONFIG_PACKAGE_libgnurl is not set\n# CONFIG_PACKAGE_libgpg-error is not set\n# CONFIG_PACKAGE_libgpgme is not set\n# CONFIG_PACKAGE_libgpgmepp is not set\n# CONFIG_PACKAGE_libgphoto2 is not set\n# CONFIG_PACKAGE_libgpiod is not set\n# CONFIG_PACKAGE_libgps is not set\n# CONFIG_PACKAGE_libh2o is not set\n# CONFIG_PACKAGE_libh2o-evloop is not set\n# CONFIG_PACKAGE_libhamlib is not set\n# CONFIG_PACKAGE_libhavege is not set\n# CONFIG_PACKAGE_libhiredis is not set\n# CONFIG_PACKAGE_libhttp-parser is not set\n# CONFIG_PACKAGE_libhwloc is not set\n# CONFIG_PACKAGE_libi2c is not set\n# CONFIG_PACKAGE_libical is not set\n# CONFIG_PACKAGE_libiconv is not set\n# CONFIG_PACKAGE_libiconv-full is not set\nCONFIG_PACKAGE_libid3tag=y\n# CONFIG_PACKAGE_libidn is not set\n# CONFIG_PACKAGE_libidn2 is not set\n# CONFIG_PACKAGE_libiio is not set\n# CONFIG_PACKAGE_libinotifytools is not set\n# CONFIG_PACKAGE_libinput is not set\n# CONFIG_PACKAGE_libintl-full is not set\n# CONFIG_PACKAGE_libipfs-http-client is not set\n# CONFIG_PACKAGE_libiw is not set\nCONFIG_PACKAGE_libiwinfo=y\nCONFIG_PACKAGE_libjpeg-turbo=y\nCONFIG_PACKAGE_libjson-c=y\n# CONFIG_PACKAGE_libkeyutils is not set\n# CONFIG_PACKAGE_libkmod is not set\n# CONFIG_PACKAGE_libksba is not set\n# CONFIG_PACKAGE_libldns is not set\n# CONFIG_PACKAGE_libleptonica is not set\n# CONFIG_PACKAGE_libloragw is not set\nCONFIG_PACKAGE_libltdl=y\nCONFIG_PACKAGE_liblua=y\n# CONFIG_PACKAGE_liblua5.3 is not set\nCONFIG_PACKAGE_liblucihttp=y\nCONFIG_PACKAGE_liblucihttp-lua=y\nCONFIG_PACKAGE_liblzo=y\n# CONFIG_PACKAGE_libmad is not set\n# CONFIG_PACKAGE_libmagic is not set\n# CONFIG_PACKAGE_libmaxminddb is not set\n# CONFIG_PACKAGE_libmbim is not set\n# CONFIG_PACKAGE_libmcrypt is not set\n# CONFIG_PACKAGE_libmicrohttpd-no-ssl is not set\n# CONFIG_PACKAGE_libmicrohttpd-ssl is not set\n# CONFIG_PACKAGE_libmilter-sendmail is not set\nCONFIG_PACKAGE_libminiupnpc=y\n# CONFIG_PACKAGE_libmms is not set\nCONFIG_PACKAGE_libmnl=y\n# CONFIG_PACKAGE_libmodbus is not set\n# CONFIG_PACKAGE_libmosquitto-nossl is not set\n# CONFIG_PACKAGE_libmosquitto-ssl is not set\nCONFIG_PACKAGE_libmount=y\n# CONFIG_PACKAGE_libmpdclient is not set\n# CONFIG_PACKAGE_libmpeg2 is not set\n# CONFIG_PACKAGE_libmpg123 is not set\nCONFIG_PACKAGE_libnatpmp=y\nCONFIG_PACKAGE_libncurses=y\n# CONFIG_PACKAGE_libndpi is not set\n# CONFIG_PACKAGE_libneon is not set\n# CONFIG_PACKAGE_libnet-1.2.x is not set\n# CONFIG_PACKAGE_libnetconf2 is not set\n# CONFIG_PACKAGE_libnetfilter-acct is not set\n# CONFIG_PACKAGE_libnetfilter-conntrack is not set\n# CONFIG_PACKAGE_libnetfilter-cthelper is not set\n# CONFIG_PACKAGE_libnetfilter-cttimeout is not set\n# CONFIG_PACKAGE_libnetfilter-log is not set\n# CONFIG_PACKAGE_libnetfilter-queue is not set\nCONFIG_PACKAGE_libnetsnmp=y\nCONFIG_PACKAGE_libnettle=y\n\n#\n# Configuration\n#\n# CONFIG_LIBNETTLE_MINI is not set\n# end of Configuration\n\n# CONFIG_PACKAGE_libnewt is not set\n# CONFIG_PACKAGE_libnfnetlink is not set\n# CONFIG_PACKAGE_libnftnl is not set\n# CONFIG_PACKAGE_libnghttp2 is not set\n# CONFIG_PACKAGE_libnl is not set\nCONFIG_PACKAGE_libnl-core=y\n# CONFIG_PACKAGE_libnl-genl is not set\n# CONFIG_PACKAGE_libnl-nf is not set\nCONFIG_PACKAGE_libnl-route=y\nCONFIG_PACKAGE_libnl-tiny=y\n# CONFIG_PACKAGE_libnopoll is not set\n# CONFIG_PACKAGE_libnpth is not set\n# CONFIG_PACKAGE_libnpupnp is not set\nCONFIG_PACKAGE_libogg=y\n# CONFIG_PACKAGE_liboil is not set\n# CONFIG_PACKAGE_libopcodes is not set\n# CONFIG_PACKAGE_libopendkim is not set\n# CONFIG_PACKAGE_libopenobex is not set\n# CONFIG_PACKAGE_libopensc is not set\n# CONFIG_PACKAGE_libopenzwave is not set\n# CONFIG_PACKAGE_liboping is not set\n# CONFIG_PACKAGE_libopus is not set\n# CONFIG_PACKAGE_libopusenc is not set\n# CONFIG_PACKAGE_libopusfile is not set\n# CONFIG_PACKAGE_liborcania is not set\n# CONFIG_PACKAGE_libout123 is not set\n# CONFIG_PACKAGE_libowipcalc is not set\n# CONFIG_PACKAGE_libp11 is not set\n# CONFIG_PACKAGE_libpagekite is not set\n# CONFIG_PACKAGE_libpam is not set\n# CONFIG_PACKAGE_libparted is not set\n# CONFIG_PACKAGE_libpbc is not set\nCONFIG_PACKAGE_libpcap=y\n\n#\n# Configuration\n#\n# CONFIG_PCAP_HAS_USB is not set\n# CONFIG_PCAP_HAS_NETFILTER is not set\n# end of Configuration\n\nCONFIG_PACKAGE_libpci=y\n# CONFIG_PACKAGE_libpciaccess is not set\nCONFIG_PACKAGE_libpcre=y\n# CONFIG_PACKAGE_libpcre16 is not set\n# CONFIG_PACKAGE_libpcre2 is not set\n# CONFIG_PACKAGE_libpcre2-16 is not set\n# CONFIG_PACKAGE_libpcre2-32 is not set\n# CONFIG_PACKAGE_libpcre32 is not set\n# CONFIG_PACKAGE_libpcrecpp is not set\n# CONFIG_PACKAGE_libpcsclite is not set\n# CONFIG_PACKAGE_libpfring is not set\n# CONFIG_PACKAGE_libpkcs11-spy is not set\n# CONFIG_PACKAGE_libpkgconf is not set\nCONFIG_PACKAGE_libpng=y\nCONFIG_PACKAGE_libpopt=y\n# CONFIG_PACKAGE_libpri is not set\n# CONFIG_PACKAGE_libprotobuf-c is not set\n# CONFIG_PACKAGE_libpsl is not set\n# CONFIG_PACKAGE_libqmi is not set\n# CONFIG_PACKAGE_libqrencode is not set\n# CONFIG_PACKAGE_libqrtr-glib is not set\n# CONFIG_PACKAGE_libradcli is not set\n# CONFIG_PACKAGE_libradiotap is not set\nCONFIG_PACKAGE_libreadline=y\n# CONFIG_PACKAGE_libredblack is not set\n# CONFIG_PACKAGE_librouteros is not set\n# CONFIG_PACKAGE_libroxml is not set\nCONFIG_PACKAGE_librrd1=y\n# CONFIG_PACKAGE_librtlsdr is not set\n# CONFIG_PACKAGE_libruby is not set\n# CONFIG_PACKAGE_libsamplerate is not set\n# CONFIG_PACKAGE_libsane is not set\n# CONFIG_PACKAGE_libsasl2 is not set\n# CONFIG_PACKAGE_libsasl2-sasldb is not set\n# CONFIG_PACKAGE_libsearpc is not set\nCONFIG_PACKAGE_libseccomp=y\nCONFIG_PACKAGE_libselinux=y\n# CONFIG_PACKAGE_libsemanage is not set\n# CONFIG_PACKAGE_libsensors is not set\nCONFIG_PACKAGE_libsepol=y\n# CONFIG_PACKAGE_libshout is not set\n# CONFIG_PACKAGE_libshout-full is not set\n# CONFIG_PACKAGE_libshout-nossl is not set\n# CONFIG_PACKAGE_libsispmctl is not set\n# CONFIG_PACKAGE_libslang2 is not set\n# CONFIG_PACKAGE_libslang2-mod-base64 is not set\n# CONFIG_PACKAGE_libslang2-mod-chksum is not set\n# CONFIG_PACKAGE_libslang2-mod-csv is not set\n# CONFIG_PACKAGE_libslang2-mod-fcntl is not set\n# CONFIG_PACKAGE_libslang2-mod-fork is not set\n# CONFIG_PACKAGE_libslang2-mod-histogram is not set\n# CONFIG_PACKAGE_libslang2-mod-iconv is not set\n# CONFIG_PACKAGE_libslang2-mod-json is not set\n# CONFIG_PACKAGE_libslang2-mod-onig is not set\n# CONFIG_PACKAGE_libslang2-mod-pcre is not set\n# CONFIG_PACKAGE_libslang2-mod-png is not set\n# CONFIG_PACKAGE_libslang2-mod-rand is not set\n# CONFIG_PACKAGE_libslang2-mod-select is not set\n# CONFIG_PACKAGE_libslang2-mod-slsmg is not set\n# CONFIG_PACKAGE_libslang2-mod-socket is not set\n# CONFIG_PACKAGE_libslang2-mod-stats is not set\n# CONFIG_PACKAGE_libslang2-mod-sysconf is not set\n# CONFIG_PACKAGE_libslang2-mod-termios is not set\n# CONFIG_PACKAGE_libslang2-mod-varray is not set\n# CONFIG_PACKAGE_libslang2-mod-zlib is not set\n# CONFIG_PACKAGE_libslang2-modules is not set\nCONFIG_PACKAGE_libsmartcols=y\n# CONFIG_PACKAGE_libsndfile is not set\n# CONFIG_PACKAGE_libsoc is not set\n# CONFIG_PACKAGE_libsocks is not set\nCONFIG_PACKAGE_libsodium=y\n\n#\n# Configuration\n#\nCONFIG_LIBSODIUM_MINIMAL=y\n# end of Configuration\n\n# CONFIG_PACKAGE_libsoup is not set\n# CONFIG_PACKAGE_libsoxr is not set\n# CONFIG_PACKAGE_libspeex is not set\n# CONFIG_PACKAGE_libspeexdsp is not set\n# CONFIG_PACKAGE_libspice-server is not set\nCONFIG_PACKAGE_libss=y\n# CONFIG_PACKAGE_libssh is not set\n# CONFIG_PACKAGE_libssh2 is not set\n# CONFIG_PACKAGE_libstoken is not set\n# CONFIG_PACKAGE_libstrophe is not set\n# CONFIG_PACKAGE_libsyn123 is not set\n# CONFIG_PACKAGE_libsysrepo is not set\n# CONFIG_PACKAGE_libtalloc is not set\nCONFIG_PACKAGE_libtasn1=y\n# CONFIG_PACKAGE_libtheora is not set\n# CONFIG_PACKAGE_libtiff is not set\n# CONFIG_PACKAGE_libtins is not set\nCONFIG_PACKAGE_libtirpc=y\n# CONFIG_PACKAGE_libtorrent-rasterbar is not set\nCONFIG_PACKAGE_libubox=y\n# CONFIG_PACKAGE_libubox-lua is not set\nCONFIG_PACKAGE_libubus=y\nCONFIG_PACKAGE_libubus-lua=y\nCONFIG_PACKAGE_libuci=y\nCONFIG_PACKAGE_libuci-lua=y\n# CONFIG_PACKAGE_libuci2 is not set\nCONFIG_PACKAGE_libuclient=y\nCONFIG_PACKAGE_libudev-zero=y\n# CONFIG_PACKAGE_libudns is not set\n# CONFIG_PACKAGE_libuecc is not set\n# CONFIG_PACKAGE_libugpio is not set\n# CONFIG_PACKAGE_libunistring is not set\n# CONFIG_PACKAGE_libunwind is not set\n# CONFIG_PACKAGE_libupnp is not set\n# CONFIG_PACKAGE_libupnpp is not set\n# CONFIG_PACKAGE_liburcu is not set\nCONFIG_PACKAGE_liburing=y\n# CONFIG_PACKAGE_libusb-1.0 is not set\n# CONFIG_PACKAGE_libusb-compat is not set\n# CONFIG_PACKAGE_libustream-mbedtls is not set\nCONFIG_PACKAGE_libustream-openssl=y\n# CONFIG_PACKAGE_libustream-wolfssl is not set\nCONFIG_PACKAGE_libuuid=y\nCONFIG_PACKAGE_libuv=y\n# CONFIG_PACKAGE_libuwifi is not set\n# CONFIG_PACKAGE_libv4l is not set\nCONFIG_PACKAGE_libvorbis=y\n# CONFIG_PACKAGE_libvorbisidec is not set\n# CONFIG_PACKAGE_libvpx is not set\nCONFIG_PACKAGE_libwebp=y\nCONFIG_PACKAGE_libwebsockets-full=y\n# CONFIG_PACKAGE_libwebsockets-mbedtls is not set\n# CONFIG_PACKAGE_libwebsockets-openssl is not set\n# CONFIG_PACKAGE_libwrap is not set\n# CONFIG_PACKAGE_libxerces-c is not set\n# CONFIG_PACKAGE_libxerces-c-samples is not set\n# CONFIG_PACKAGE_libxml2 is not set\n# CONFIG_PACKAGE_libxslt is not set\n# CONFIG_PACKAGE_libyaml-cpp is not set\n# CONFIG_PACKAGE_libyang is not set\n# CONFIG_PACKAGE_libyubikey is not set\n# CONFIG_PACKAGE_libzmq-curve is not set\n# CONFIG_PACKAGE_libzmq-nc is not set\n# CONFIG_PACKAGE_linux-atm is not set\n# CONFIG_PACKAGE_lmdb is not set\n# CONFIG_PACKAGE_log4cplus is not set\n# CONFIG_PACKAGE_loudmouth is not set\n# CONFIG_PACKAGE_lttng-ust is not set\n# CONFIG_PACKAGE_minizip is not set\n# CONFIG_PACKAGE_msgpack-c is not set\n# CONFIG_PACKAGE_mtdev is not set\nCONFIG_PACKAGE_musl-fts=y\n# CONFIG_PACKAGE_mxml is not set\n# CONFIG_PACKAGE_nspr is not set\n# CONFIG_PACKAGE_oniguruma is not set\n# CONFIG_PACKAGE_open-isns is not set\n# CONFIG_PACKAGE_openblas is not set\n# CONFIG_PACKAGE_openpgm is not set\n# CONFIG_PACKAGE_p11-kit is not set\n# CONFIG_PACKAGE_pixman is not set\n# CONFIG_PACKAGE_poco is not set\n# CONFIG_PACKAGE_poco-all is not set\n# CONFIG_PACKAGE_protobuf is not set\n# CONFIG_PACKAGE_protobuf-lite is not set\n# CONFIG_PACKAGE_pthsem is not set\n# CONFIG_PACKAGE_re2 is not set\nCONFIG_PACKAGE_rpcd-mod-luci=y\n# CONFIG_PACKAGE_rpcd-mod-rad2-enc is not set\nCONFIG_PACKAGE_rpcd-mod-rrdns=y\n# CONFIG_PACKAGE_sbc is not set\n# CONFIG_PACKAGE_scmp_sys_resolver is not set\n# CONFIG_PACKAGE_serdisplib is not set\n# CONFIG_PACKAGE_taglib is not set\nCONFIG_PACKAGE_terminfo=y\n# CONFIG_PACKAGE_tinycdb is not set\n# CONFIG_PACKAGE_uw-imap is not set\n# CONFIG_PACKAGE_xmlrpc-c is not set\n# CONFIG_PACKAGE_xmlrpc-c-client is not set\n# CONFIG_PACKAGE_xmlrpc-c-server is not set\n# CONFIG_PACKAGE_yajl is not set\n# CONFIG_PACKAGE_yubico-pam is not set\nCONFIG_PACKAGE_zlib=y\n\n#\n# Configuration\n#\n# CONFIG_ZLIB_OPTIMIZE_SPEED is not set\n# end of Configuration\n# end of Libraries\n\n#\n# LuCI\n#\n\n#\n# 1. Collections\n#\nCONFIG_PACKAGE_luci=y\nCONFIG_PACKAGE_luci-lib-docker=y\n# CONFIG_PACKAGE_luci-nginx is not set\n# CONFIG_PACKAGE_luci-ssl is not set\n# CONFIG_PACKAGE_luci-ssl-nginx is not set\nCONFIG_PACKAGE_luci-ssl-openssl=y\n# end of 1. Collections\n\n#\n# 2. Modules\n#\nCONFIG_PACKAGE_luci-base=y\n# CONFIG_LUCI_SRCDIET is not set\nCONFIG_LUCI_JSMIN=y\nCONFIG_LUCI_CSSTIDY=y\n\n#\n# Translations\n#\n# CONFIG_LUCI_LANG_ar is not set\n# CONFIG_LUCI_LANG_bg is not set\n# CONFIG_LUCI_LANG_bn_BD is not set\n# CONFIG_LUCI_LANG_ca is not set\n# CONFIG_LUCI_LANG_cs is not set\n# CONFIG_LUCI_LANG_da is not set\n# CONFIG_LUCI_LANG_de is not set\n# CONFIG_LUCI_LANG_el is not set\n# CONFIG_LUCI_LANG_en is not set\n# CONFIG_LUCI_LANG_es is not set\n# CONFIG_LUCI_LANG_fi is not set\n# CONFIG_LUCI_LANG_fr is not set\n# CONFIG_LUCI_LANG_he is not set\n# CONFIG_LUCI_LANG_hi is not set\n# CONFIG_LUCI_LANG_hu is not set\n# CONFIG_LUCI_LANG_it is not set\n# CONFIG_LUCI_LANG_ja is not set\n# CONFIG_LUCI_LANG_ko is not set\n# CONFIG_LUCI_LANG_mr is not set\n# CONFIG_LUCI_LANG_ms is not set\n# CONFIG_LUCI_LANG_nb_NO is not set\n# CONFIG_LUCI_LANG_nl is not set\n# CONFIG_LUCI_LANG_pl is not set\n# CONFIG_LUCI_LANG_pt is not set\n# CONFIG_LUCI_LANG_pt_BR is not set\n# CONFIG_LUCI_LANG_ro is not set\n# CONFIG_LUCI_LANG_ru is not set\n# CONFIG_LUCI_LANG_sk is not set\n# CONFIG_LUCI_LANG_sv is not set\n# CONFIG_LUCI_LANG_tr is not set\n# CONFIG_LUCI_LANG_uk is not set\n# CONFIG_LUCI_LANG_vi is not set\nCONFIG_LUCI_LANG_zh_Hans=y\n# CONFIG_LUCI_LANG_zh_Hant is not set\n# end of Translations\n\nCONFIG_PACKAGE_luci-compat=y\nCONFIG_PACKAGE_luci-mod-admin-full=y\n# CONFIG_PACKAGE_luci-mod-battstatus is not set\n# CONFIG_PACKAGE_luci-mod-dashboard is not set\nCONFIG_PACKAGE_luci-mod-network=y\nCONFIG_PACKAGE_luci-mod-rpc=y\nCONFIG_PACKAGE_luci-mod-status=y\nCONFIG_PACKAGE_luci-mod-system=y\n# end of 2. Modules\n\n#\n# 3. Applications\n#\n# CONFIG_PACKAGE_luci-app-acl is not set\n# CONFIG_PACKAGE_luci-app-acme is not set\nCONFIG_PACKAGE_luci-app-adblock=y\nCONFIG_PACKAGE_luci-app-advanced-reboot=y\n# CONFIG_PACKAGE_luci-app-ahcp is not set\nCONFIG_PACKAGE_luci-app-aria2=y\n# CONFIG_PACKAGE_luci-app-attendedsysupgrade is not set\n# CONFIG_PACKAGE_luci-app-babeld is not set\nCONFIG_PACKAGE_luci-app-banip=y\n# CONFIG_PACKAGE_luci-app-bcp38 is not set\n# CONFIG_PACKAGE_luci-app-bird1-ipv4 is not set\n# CONFIG_PACKAGE_luci-app-bird1-ipv6 is not set\n# CONFIG_PACKAGE_luci-app-bmx6 is not set\n# CONFIG_PACKAGE_luci-app-bmx7 is not set\n# CONFIG_PACKAGE_luci-app-cjdns is not set\n# CONFIG_PACKAGE_luci-app-clamav is not set\nCONFIG_PACKAGE_luci-app-commands=y\n# CONFIG_PACKAGE_luci-app-cshark is not set\n# CONFIG_PACKAGE_luci-app-dawn is not set\n# CONFIG_PACKAGE_luci-app-dcwapd is not set\nCONFIG_PACKAGE_luci-app-ddns=y\n# CONFIG_PACKAGE_luci-app-diag-core is not set\n# CONFIG_PACKAGE_luci-app-dnscrypt-proxy is not set\nCONFIG_PACKAGE_luci-app-dockerman=y\n# CONFIG_PACKAGE_luci-app-dump1090 is not set\n# CONFIG_PACKAGE_luci-app-dynapoint is not set\n# CONFIG_PACKAGE_luci-app-eoip is not set\n# CONFIG_PACKAGE_luci-app-example is not set\nCONFIG_PACKAGE_luci-app-firewall=y\n# CONFIG_PACKAGE_luci-app-frpc is not set\n# CONFIG_PACKAGE_luci-app-frps is not set\n# CONFIG_PACKAGE_luci-app-fwknopd is not set\n# CONFIG_PACKAGE_luci-app-hd-idle is not set\n# CONFIG_PACKAGE_luci-app-hnet is not set\n# CONFIG_PACKAGE_luci-app-https-dns-proxy is not set\n# CONFIG_PACKAGE_luci-app-ksmbd is not set\n# CONFIG_PACKAGE_luci-app-ledtrig-rssi is not set\n# CONFIG_PACKAGE_luci-app-ledtrig-switch is not set\n# CONFIG_PACKAGE_luci-app-ledtrig-usbport is not set\n# CONFIG_PACKAGE_luci-app-lxc is not set\nCONFIG_PACKAGE_luci-app-minidlna=y\nCONFIG_PACKAGE_luci-app-mjpg-streamer=y\n# CONFIG_PACKAGE_luci-app-mwan3 is not set\n# CONFIG_PACKAGE_luci-app-nextdns is not set\n# CONFIG_PACKAGE_luci-app-nft-qos is not set\nCONFIG_PACKAGE_luci-app-nlbwmon=y\nCONFIG_PACKAGE_luci-app-ntpc=y\n# CONFIG_PACKAGE_luci-app-nut is not set\n# CONFIG_PACKAGE_luci-app-ocserv is not set\n# CONFIG_PACKAGE_luci-app-olsr is not set\n# CONFIG_PACKAGE_luci-app-olsr-services is not set\n# CONFIG_PACKAGE_luci-app-olsr-viz is not set\n# CONFIG_PACKAGE_luci-app-omcproxy is not set\nCONFIG_PACKAGE_luci-app-openvpn=y\nCONFIG_PACKAGE_luci-app-opkg=y\n# CONFIG_PACKAGE_luci-app-p910nd is not set\n# CONFIG_PACKAGE_luci-app-pagekitec is not set\n# CONFIG_PACKAGE_luci-app-polipo is not set\n# CONFIG_PACKAGE_luci-app-privoxy is not set\nCONFIG_PACKAGE_luci-app-qos=y\n# CONFIG_PACKAGE_luci-app-radicale is not set\n# CONFIG_PACKAGE_luci-app-radicale2 is not set\n# CONFIG_PACKAGE_luci-app-rp-pppoe-server is not set\nCONFIG_PACKAGE_luci-app-samba4=y\n# CONFIG_PACKAGE_luci-app-ser2net is not set\nCONFIG_PACKAGE_luci-app-shadowsocks-libev=y\n# CONFIG_PACKAGE_luci-app-shairplay is not set\n# CONFIG_PACKAGE_luci-app-siitwizard is not set\n# CONFIG_PACKAGE_luci-app-simple-adblock is not set\n# CONFIG_PACKAGE_luci-app-smartdns is not set\n# CONFIG_PACKAGE_luci-app-snmpd is not set\n# CONFIG_PACKAGE_luci-app-softether is not set\n# CONFIG_PACKAGE_luci-app-splash is not set\nCONFIG_PACKAGE_luci-app-sqm=y\nCONFIG_PACKAGE_luci-app-squid=y\nCONFIG_PACKAGE_luci-app-statistics=y\n# CONFIG_PACKAGE_luci-app-tinyproxy is not set\nCONFIG_PACKAGE_luci-app-transmission=y\n# CONFIG_PACKAGE_luci-app-travelmate is not set\nCONFIG_PACKAGE_luci-app-ttyd=y\n# CONFIG_PACKAGE_luci-app-udpxy is not set\n# CONFIG_PACKAGE_luci-app-uhttpd is not set\nCONFIG_PACKAGE_luci-app-unbound=y\n# CONFIG_PACKAGE_luci-app-upnp is not set\n# CONFIG_PACKAGE_luci-app-vnstat is not set\nCONFIG_PACKAGE_luci-app-vnstat2=y\n# CONFIG_PACKAGE_luci-app-vpn-policy-routing is not set\n# CONFIG_PACKAGE_luci-app-vpnbypass is not set\nCONFIG_PACKAGE_luci-app-watchcat=y\n# CONFIG_PACKAGE_luci-app-wifischedule is not set\nCONFIG_PACKAGE_luci-app-wireguard=y\n# CONFIG_PACKAGE_luci-app-wol is not set\n# CONFIG_PACKAGE_luci-app-xinetd is not set\n# CONFIG_PACKAGE_luci-app-yggdrasil is not set\n# end of 3. Applications\n\n#\n# 4. Themes\n#\nCONFIG_PACKAGE_luci-theme-bootstrap=y\n# CONFIG_PACKAGE_luci-theme-material is not set\n# CONFIG_PACKAGE_luci-theme-openwrt is not set\n# CONFIG_PACKAGE_luci-theme-openwrt-2020 is not set\n# end of 4. Themes\n\n#\n# 5. Protocols\n#\n# CONFIG_PACKAGE_luci-proto-3g is not set\n# CONFIG_PACKAGE_luci-proto-bonding is not set\n# CONFIG_PACKAGE_luci-proto-gre is not set\n# CONFIG_PACKAGE_luci-proto-hnet is not set\n# CONFIG_PACKAGE_luci-proto-ipip is not set\nCONFIG_PACKAGE_luci-proto-ipv6=y\n# CONFIG_PACKAGE_luci-proto-modemmanager is not set\n# CONFIG_PACKAGE_luci-proto-ncm is not set\n# CONFIG_PACKAGE_luci-proto-openconnect is not set\n# CONFIG_PACKAGE_luci-proto-openfortivpn is not set\nCONFIG_PACKAGE_luci-proto-ppp=y\n# CONFIG_PACKAGE_luci-proto-pppossh is not set\n# CONFIG_PACKAGE_luci-proto-qmi is not set\n# CONFIG_PACKAGE_luci-proto-relay is not set\n# CONFIG_PACKAGE_luci-proto-sstp is not set\n# CONFIG_PACKAGE_luci-proto-vpnc is not set\n# CONFIG_PACKAGE_luci-proto-vxlan is not set\nCONFIG_PACKAGE_luci-proto-wireguard=y\n# end of 5. Protocols\n\n#\n# 6. Libraries\n#\nCONFIG_PACKAGE_luci-lib-base=y\n# CONFIG_PACKAGE_luci-lib-dracula is not set\n# CONFIG_PACKAGE_luci-lib-httpclient is not set\n# CONFIG_PACKAGE_luci-lib-httpprotoutils is not set\nCONFIG_PACKAGE_luci-lib-ip=y\nCONFIG_PACKAGE_luci-lib-ipkg=y\n# CONFIG_PACKAGE_luci-lib-iptparser is not set\n# CONFIG_PACKAGE_luci-lib-jquery-1-4 is not set\nCONFIG_PACKAGE_luci-lib-json=y\nCONFIG_PACKAGE_luci-lib-jsonc=y\nCONFIG_PACKAGE_luci-lib-nixio=y\nCONFIG_PACKAGE_luci-lib-nixio_notls=y\n# CONFIG_PACKAGE_luci-lib-nixio_axtls is not set\n# CONFIG_PACKAGE_luci-lib-nixio_cyassl is not set\n# CONFIG_PACKAGE_luci-lib-nixio_openssl is not set\n# CONFIG_PACKAGE_luci-lib-px5g is not set\n# end of 6. Libraries\n\n# CONFIG_PACKAGE_luci-i18n-adblock-ar is not set\n# CONFIG_PACKAGE_luci-i18n-adblock-bg is not set\n# CONFIG_PACKAGE_luci-i18n-adblock-bn is not set\n# CONFIG_PACKAGE_luci-i18n-adblock-ca is not set\n# CONFIG_PACKAGE_luci-i18n-adblock-cs is not set\n# CONFIG_PACKAGE_luci-i18n-adblock-da is not set\n# CONFIG_PACKAGE_luci-i18n-adblock-de is not set\n# CONFIG_PACKAGE_luci-i18n-adblock-el is not set\n# CONFIG_PACKAGE_luci-i18n-adblock-en is not set\n# CONFIG_PACKAGE_luci-i18n-adblock-es is not set\n# CONFIG_PACKAGE_luci-i18n-adblock-fi is not set\n# CONFIG_PACKAGE_luci-i18n-adblock-fr is not set\n# CONFIG_PACKAGE_luci-i18n-adblock-he is not set\n# CONFIG_PACKAGE_luci-i18n-adblock-hi is not set\n# CONFIG_PACKAGE_luci-i18n-adblock-hu is not set\n# CONFIG_PACKAGE_luci-i18n-adblock-it is not set\n# CONFIG_PACKAGE_luci-i18n-adblock-ja is not set\n# CONFIG_PACKAGE_luci-i18n-adblock-ko is not set\n# CONFIG_PACKAGE_luci-i18n-adblock-mr is not set\n# CONFIG_PACKAGE_luci-i18n-adblock-ms is not set\n# CONFIG_PACKAGE_luci-i18n-adblock-no is not set\n# CONFIG_PACKAGE_luci-i18n-adblock-pl is not set\n# CONFIG_PACKAGE_luci-i18n-adblock-pt is not set\n# CONFIG_PACKAGE_luci-i18n-adblock-pt-br is not set\n# CONFIG_PACKAGE_luci-i18n-adblock-ro is not set\n# CONFIG_PACKAGE_luci-i18n-adblock-ru is not set\n# CONFIG_PACKAGE_luci-i18n-adblock-si is not set\n# CONFIG_PACKAGE_luci-i18n-adblock-sk is not set\n# CONFIG_PACKAGE_luci-i18n-adblock-sv is not set\n# CONFIG_PACKAGE_luci-i18n-adblock-tr is not set\n# CONFIG_PACKAGE_luci-i18n-adblock-uk is not set\n# CONFIG_PACKAGE_luci-i18n-adblock-vi is not set\nCONFIG_PACKAGE_luci-i18n-adblock-zh-cn=y\n# CONFIG_PACKAGE_luci-i18n-adblock-zh-tw is not set\n# CONFIG_PACKAGE_luci-i18n-advanced-reboot-ar is not set\n# CONFIG_PACKAGE_luci-i18n-advanced-reboot-bg is not set\n# CONFIG_PACKAGE_luci-i18n-advanced-reboot-bn is not set\n# CONFIG_PACKAGE_luci-i18n-advanced-reboot-ca is not set\n# CONFIG_PACKAGE_luci-i18n-advanced-reboot-cs is not set\n# CONFIG_PACKAGE_luci-i18n-advanced-reboot-da is not set\n# CONFIG_PACKAGE_luci-i18n-advanced-reboot-de is not set\n# CONFIG_PACKAGE_luci-i18n-advanced-reboot-el is not set\n# CONFIG_PACKAGE_luci-i18n-advanced-reboot-en is not set\n# CONFIG_PACKAGE_luci-i18n-advanced-reboot-es is not set\n# CONFIG_PACKAGE_luci-i18n-advanced-reboot-fi is not set\n# CONFIG_PACKAGE_luci-i18n-advanced-reboot-fr is not set\n# CONFIG_PACKAGE_luci-i18n-advanced-reboot-he is not set\n# CONFIG_PACKAGE_luci-i18n-advanced-reboot-hi is not set\n# CONFIG_PACKAGE_luci-i18n-advanced-reboot-hu is not set\n# CONFIG_PACKAGE_luci-i18n-advanced-reboot-it is not set\n# CONFIG_PACKAGE_luci-i18n-advanced-reboot-ja is not set\n# CONFIG_PACKAGE_luci-i18n-advanced-reboot-ko is not set\n# CONFIG_PACKAGE_luci-i18n-advanced-reboot-mr is not set\n# CONFIG_PACKAGE_luci-i18n-advanced-reboot-ms is not set\n# CONFIG_PACKAGE_luci-i18n-advanced-reboot-no is not set\n# CONFIG_PACKAGE_luci-i18n-advanced-reboot-pl is not set\n# CONFIG_PACKAGE_luci-i18n-advanced-reboot-pt is not set\n# CONFIG_PACKAGE_luci-i18n-advanced-reboot-pt-br is not set\n# CONFIG_PACKAGE_luci-i18n-advanced-reboot-ro is not set\n# CONFIG_PACKAGE_luci-i18n-advanced-reboot-ru is not set\n# CONFIG_PACKAGE_luci-i18n-advanced-reboot-si is not set\n# CONFIG_PACKAGE_luci-i18n-advanced-reboot-sk is not set\n# CONFIG_PACKAGE_luci-i18n-advanced-reboot-sv is not set\n# CONFIG_PACKAGE_luci-i18n-advanced-reboot-tr is not set\n# CONFIG_PACKAGE_luci-i18n-advanced-reboot-uk is not set\n# CONFIG_PACKAGE_luci-i18n-advanced-reboot-vi is not set\nCONFIG_PACKAGE_luci-i18n-advanced-reboot-zh-cn=y\n# CONFIG_PACKAGE_luci-i18n-advanced-reboot-zh-tw is not set\n# CONFIG_PACKAGE_luci-i18n-aria2-ar is not set\n# CONFIG_PACKAGE_luci-i18n-aria2-bg is not set\n# CONFIG_PACKAGE_luci-i18n-aria2-bn is not set\n# CONFIG_PACKAGE_luci-i18n-aria2-ca is not set\n# CONFIG_PACKAGE_luci-i18n-aria2-cs is not set\n# CONFIG_PACKAGE_luci-i18n-aria2-da is not set\n# CONFIG_PACKAGE_luci-i18n-aria2-de is not set\n# CONFIG_PACKAGE_luci-i18n-aria2-el is not set\n# CONFIG_PACKAGE_luci-i18n-aria2-en is not set\n# CONFIG_PACKAGE_luci-i18n-aria2-es is not set\n# CONFIG_PACKAGE_luci-i18n-aria2-fi is not set\n# CONFIG_PACKAGE_luci-i18n-aria2-fr is not set\n# CONFIG_PACKAGE_luci-i18n-aria2-he is not set\n# CONFIG_PACKAGE_luci-i18n-aria2-hi is not set\n# CONFIG_PACKAGE_luci-i18n-aria2-hu is not set\n# CONFIG_PACKAGE_luci-i18n-aria2-it is not set\n# CONFIG_PACKAGE_luci-i18n-aria2-ja is not set\n# CONFIG_PACKAGE_luci-i18n-aria2-ko is not set\n# CONFIG_PACKAGE_luci-i18n-aria2-mr is not set\n# CONFIG_PACKAGE_luci-i18n-aria2-ms is not set\n# CONFIG_PACKAGE_luci-i18n-aria2-no is not set\n# CONFIG_PACKAGE_luci-i18n-aria2-pl is not set\n# CONFIG_PACKAGE_luci-i18n-aria2-pt is not set\n# CONFIG_PACKAGE_luci-i18n-aria2-pt-br is not set\n# CONFIG_PACKAGE_luci-i18n-aria2-ro is not set\n# CONFIG_PACKAGE_luci-i18n-aria2-ru is not set\n# CONFIG_PACKAGE_luci-i18n-aria2-sk is not set\n# CONFIG_PACKAGE_luci-i18n-aria2-sv is not set\n# CONFIG_PACKAGE_luci-i18n-aria2-tr is not set\n# CONFIG_PACKAGE_luci-i18n-aria2-uk is not set\n# CONFIG_PACKAGE_luci-i18n-aria2-vi is not set\nCONFIG_PACKAGE_luci-i18n-aria2-zh-cn=y\n# CONFIG_PACKAGE_luci-i18n-aria2-zh-tw is not set\n# CONFIG_PACKAGE_luci-i18n-banip-ar is not set\n# CONFIG_PACKAGE_luci-i18n-banip-bg is not set\n# CONFIG_PACKAGE_luci-i18n-banip-bn is not set\n# CONFIG_PACKAGE_luci-i18n-banip-ca is not set\n# CONFIG_PACKAGE_luci-i18n-banip-cs is not set\n# CONFIG_PACKAGE_luci-i18n-banip-da is not set\n# CONFIG_PACKAGE_luci-i18n-banip-de is not set\n# CONFIG_PACKAGE_luci-i18n-banip-el is not set\n# CONFIG_PACKAGE_luci-i18n-banip-en is not set\n# CONFIG_PACKAGE_luci-i18n-banip-es is not set\n# CONFIG_PACKAGE_luci-i18n-banip-fi is not set\n# CONFIG_PACKAGE_luci-i18n-banip-fr is not set\n# CONFIG_PACKAGE_luci-i18n-banip-he is not set\n# CONFIG_PACKAGE_luci-i18n-banip-hi is not set\n# CONFIG_PACKAGE_luci-i18n-banip-hu is not set\n# CONFIG_PACKAGE_luci-i18n-banip-it is not set\n# CONFIG_PACKAGE_luci-i18n-banip-ja is not set\n# CONFIG_PACKAGE_luci-i18n-banip-ko is not set\n# CONFIG_PACKAGE_luci-i18n-banip-mr is not set\n# CONFIG_PACKAGE_luci-i18n-banip-ms is not set\n# CONFIG_PACKAGE_luci-i18n-banip-nl is not set\n# CONFIG_PACKAGE_luci-i18n-banip-no is not set\n# CONFIG_PACKAGE_luci-i18n-banip-pl is not set\n# CONFIG_PACKAGE_luci-i18n-banip-pt is not set\n# CONFIG_PACKAGE_luci-i18n-banip-pt-br is not set\n# CONFIG_PACKAGE_luci-i18n-banip-ro is not set\n# CONFIG_PACKAGE_luci-i18n-banip-ru is not set\n# CONFIG_PACKAGE_luci-i18n-banip-sk is not set\n# CONFIG_PACKAGE_luci-i18n-banip-sv is not set\n# CONFIG_PACKAGE_luci-i18n-banip-sw is not set\n# CONFIG_PACKAGE_luci-i18n-banip-tr is not set\n# CONFIG_PACKAGE_luci-i18n-banip-uk is not set\n# CONFIG_PACKAGE_luci-i18n-banip-vi is not set\nCONFIG_PACKAGE_luci-i18n-banip-zh-cn=y\n# CONFIG_PACKAGE_luci-i18n-banip-zh-tw is not set\n# CONFIG_PACKAGE_luci-i18n-base-ar is not set\n# CONFIG_PACKAGE_luci-i18n-base-bg is not set\n# CONFIG_PACKAGE_luci-i18n-base-bn is not set\n# CONFIG_PACKAGE_luci-i18n-base-ca is not set\n# CONFIG_PACKAGE_luci-i18n-base-cs is not set\n# CONFIG_PACKAGE_luci-i18n-base-da is not set\n# CONFIG_PACKAGE_luci-i18n-base-de is not set\n# CONFIG_PACKAGE_luci-i18n-base-el is not set\n# CONFIG_PACKAGE_luci-i18n-base-en is not set\n# CONFIG_PACKAGE_luci-i18n-base-es is not set\n# CONFIG_PACKAGE_luci-i18n-base-fi is not set\n# CONFIG_PACKAGE_luci-i18n-base-fr is not set\n# CONFIG_PACKAGE_luci-i18n-base-he is not set\n# CONFIG_PACKAGE_luci-i18n-base-hi is not set\n# CONFIG_PACKAGE_luci-i18n-base-hu is not set\n# CONFIG_PACKAGE_luci-i18n-base-it is not set\n# CONFIG_PACKAGE_luci-i18n-base-ja is not set\n# CONFIG_PACKAGE_luci-i18n-base-ko is not set\n# CONFIG_PACKAGE_luci-i18n-base-mr is not set\n# CONFIG_PACKAGE_luci-i18n-base-ms is not set\n# CONFIG_PACKAGE_luci-i18n-base-nl is not set\n# CONFIG_PACKAGE_luci-i18n-base-no is not set\n# CONFIG_PACKAGE_luci-i18n-base-pl is not set\n# CONFIG_PACKAGE_luci-i18n-base-pt is not set\n# CONFIG_PACKAGE_luci-i18n-base-pt-br is not set\n# CONFIG_PACKAGE_luci-i18n-base-ro is not set\n# CONFIG_PACKAGE_luci-i18n-base-ru is not set\n# CONFIG_PACKAGE_luci-i18n-base-sk is not set\n# CONFIG_PACKAGE_luci-i18n-base-sv is not set\n# CONFIG_PACKAGE_luci-i18n-base-tr is not set\n# CONFIG_PACKAGE_luci-i18n-base-uk is not set\n# CONFIG_PACKAGE_luci-i18n-base-vi is not set\nCONFIG_PACKAGE_luci-i18n-base-zh-cn=y\n# CONFIG_PACKAGE_luci-i18n-base-zh-tw is not set\n# CONFIG_PACKAGE_luci-i18n-commands-ar is not set\n# CONFIG_PACKAGE_luci-i18n-commands-bg is not set\n# CONFIG_PACKAGE_luci-i18n-commands-bn is not set\n# CONFIG_PACKAGE_luci-i18n-commands-ca is not set\n# CONFIG_PACKAGE_luci-i18n-commands-cs is not set\n# CONFIG_PACKAGE_luci-i18n-commands-da is not set\n# CONFIG_PACKAGE_luci-i18n-commands-de is not set\n# CONFIG_PACKAGE_luci-i18n-commands-el is not set\n# CONFIG_PACKAGE_luci-i18n-commands-en is not set\n# CONFIG_PACKAGE_luci-i18n-commands-es is not set\n# CONFIG_PACKAGE_luci-i18n-commands-fi is not set\n# CONFIG_PACKAGE_luci-i18n-commands-fr is not set\n# CONFIG_PACKAGE_luci-i18n-commands-he is not set\n# CONFIG_PACKAGE_luci-i18n-commands-hi is not set\n# CONFIG_PACKAGE_luci-i18n-commands-hu is not set\n# CONFIG_PACKAGE_luci-i18n-commands-it is not set\n# CONFIG_PACKAGE_luci-i18n-commands-ja is not set\n# CONFIG_PACKAGE_luci-i18n-commands-ko is not set\n# CONFIG_PACKAGE_luci-i18n-commands-mr is not set\n# CONFIG_PACKAGE_luci-i18n-commands-ms is not set\n# CONFIG_PACKAGE_luci-i18n-commands-no is not set\n# CONFIG_PACKAGE_luci-i18n-commands-pl is not set\n# CONFIG_PACKAGE_luci-i18n-commands-pt is not set\n# CONFIG_PACKAGE_luci-i18n-commands-pt-br is not set\n# CONFIG_PACKAGE_luci-i18n-commands-ro is not set\n# CONFIG_PACKAGE_luci-i18n-commands-ru is not set\n# CONFIG_PACKAGE_luci-i18n-commands-sk is not set\n# CONFIG_PACKAGE_luci-i18n-commands-sv is not set\n# CONFIG_PACKAGE_luci-i18n-commands-tr is not set\n# CONFIG_PACKAGE_luci-i18n-commands-uk is not set\n# CONFIG_PACKAGE_luci-i18n-commands-vi is not set\nCONFIG_PACKAGE_luci-i18n-commands-zh-cn=y\n# CONFIG_PACKAGE_luci-i18n-commands-zh-tw is not set\n# CONFIG_PACKAGE_luci-i18n-ddns-ar is not set\n# CONFIG_PACKAGE_luci-i18n-ddns-bg is not set\n# CONFIG_PACKAGE_luci-i18n-ddns-bn is not set\n# CONFIG_PACKAGE_luci-i18n-ddns-ca is not set\n# CONFIG_PACKAGE_luci-i18n-ddns-cs is not set\n# CONFIG_PACKAGE_luci-i18n-ddns-da is not set\n# CONFIG_PACKAGE_luci-i18n-ddns-de is not set\n# CONFIG_PACKAGE_luci-i18n-ddns-el is not set\n# CONFIG_PACKAGE_luci-i18n-ddns-en is not set\n# CONFIG_PACKAGE_luci-i18n-ddns-es is not set\n# CONFIG_PACKAGE_luci-i18n-ddns-fi is not set\n# CONFIG_PACKAGE_luci-i18n-ddns-fr is not set\n# CONFIG_PACKAGE_luci-i18n-ddns-he is not set\n# CONFIG_PACKAGE_luci-i18n-ddns-hi is not set\n# CONFIG_PACKAGE_luci-i18n-ddns-hu is not set\n# CONFIG_PACKAGE_luci-i18n-ddns-it is not set\n# CONFIG_PACKAGE_luci-i18n-ddns-ja is not set\n# CONFIG_PACKAGE_luci-i18n-ddns-ko is not set\n# CONFIG_PACKAGE_luci-i18n-ddns-mr is not set\n# CONFIG_PACKAGE_luci-i18n-ddns-ms is not set\n# CONFIG_PACKAGE_luci-i18n-ddns-no is not set\n# CONFIG_PACKAGE_luci-i18n-ddns-pl is not set\n# CONFIG_PACKAGE_luci-i18n-ddns-pt is not set\n# CONFIG_PACKAGE_luci-i18n-ddns-pt-br is not set\n# CONFIG_PACKAGE_luci-i18n-ddns-ro is not set\n# CONFIG_PACKAGE_luci-i18n-ddns-ru is not set\n# CONFIG_PACKAGE_luci-i18n-ddns-sk is not set\n# CONFIG_PACKAGE_luci-i18n-ddns-sv is not set\n# CONFIG_PACKAGE_luci-i18n-ddns-tr is not set\n# CONFIG_PACKAGE_luci-i18n-ddns-uk is not set\n# CONFIG_PACKAGE_luci-i18n-ddns-vi is not set\nCONFIG_PACKAGE_luci-i18n-ddns-zh-cn=y\n# CONFIG_PACKAGE_luci-i18n-ddns-zh-tw is not set\n# CONFIG_PACKAGE_luci-i18n-dockerman-ar is not set\n# CONFIG_PACKAGE_luci-i18n-dockerman-bg is not set\n# CONFIG_PACKAGE_luci-i18n-dockerman-bn is not set\n# CONFIG_PACKAGE_luci-i18n-dockerman-ca is not set\n# CONFIG_PACKAGE_luci-i18n-dockerman-cs is not set\n# CONFIG_PACKAGE_luci-i18n-dockerman-da is not set\n# CONFIG_PACKAGE_luci-i18n-dockerman-de is not set\n# CONFIG_PACKAGE_luci-i18n-dockerman-el is not set\n# CONFIG_PACKAGE_luci-i18n-dockerman-en is not set\n# CONFIG_PACKAGE_luci-i18n-dockerman-es is not set\n# CONFIG_PACKAGE_luci-i18n-dockerman-fa is not set\n# CONFIG_PACKAGE_luci-i18n-dockerman-fi is not set\n# CONFIG_PACKAGE_luci-i18n-dockerman-fr is not set\n# CONFIG_PACKAGE_luci-i18n-dockerman-he is not set\n# CONFIG_PACKAGE_luci-i18n-dockerman-hi is not set\n# CONFIG_PACKAGE_luci-i18n-dockerman-hu is not set\n# CONFIG_PACKAGE_luci-i18n-dockerman-id is not set\n# CONFIG_PACKAGE_luci-i18n-dockerman-it is not set\n# CONFIG_PACKAGE_luci-i18n-dockerman-ja is not set\n# CONFIG_PACKAGE_luci-i18n-dockerman-ko is not set\n# CONFIG_PACKAGE_luci-i18n-dockerman-lt is not set\n# CONFIG_PACKAGE_luci-i18n-dockerman-mr is not set\n# CONFIG_PACKAGE_luci-i18n-dockerman-ms is not set\n# CONFIG_PACKAGE_luci-i18n-dockerman-no is not set\n# CONFIG_PACKAGE_luci-i18n-dockerman-pl is not set\n# CONFIG_PACKAGE_luci-i18n-dockerman-pt is not set\n# CONFIG_PACKAGE_luci-i18n-dockerman-pt-br is not set\n# CONFIG_PACKAGE_luci-i18n-dockerman-ro is not set\n# CONFIG_PACKAGE_luci-i18n-dockerman-ru is not set\n# CONFIG_PACKAGE_luci-i18n-dockerman-sk is not set\n# CONFIG_PACKAGE_luci-i18n-dockerman-sv is not set\n# CONFIG_PACKAGE_luci-i18n-dockerman-tr is not set\n# CONFIG_PACKAGE_luci-i18n-dockerman-uk is not set\n# CONFIG_PACKAGE_luci-i18n-dockerman-vi is not set\nCONFIG_PACKAGE_luci-i18n-dockerman-zh-cn=y\n# CONFIG_PACKAGE_luci-i18n-dockerman-zh-tw is not set\n# CONFIG_PACKAGE_luci-i18n-firewall-ar is not set\n# CONFIG_PACKAGE_luci-i18n-firewall-bg is not set\n# CONFIG_PACKAGE_luci-i18n-firewall-bn is not set\n# CONFIG_PACKAGE_luci-i18n-firewall-ca is not set\n# CONFIG_PACKAGE_luci-i18n-firewall-cs is not set\n# CONFIG_PACKAGE_luci-i18n-firewall-da is not set\n# CONFIG_PACKAGE_luci-i18n-firewall-de is not set\n# CONFIG_PACKAGE_luci-i18n-firewall-el is not set\n# CONFIG_PACKAGE_luci-i18n-firewall-en is not set\n# CONFIG_PACKAGE_luci-i18n-firewall-es is not set\n# CONFIG_PACKAGE_luci-i18n-firewall-fa is not set\n# CONFIG_PACKAGE_luci-i18n-firewall-fi is not set\n# CONFIG_PACKAGE_luci-i18n-firewall-fr is not set\n# CONFIG_PACKAGE_luci-i18n-firewall-he is not set\n# CONFIG_PACKAGE_luci-i18n-firewall-hi is not set\n# CONFIG_PACKAGE_luci-i18n-firewall-hu is not set\n# CONFIG_PACKAGE_luci-i18n-firewall-id is not set\n# CONFIG_PACKAGE_luci-i18n-firewall-it is not set\n# CONFIG_PACKAGE_luci-i18n-firewall-ja is not set\n# CONFIG_PACKAGE_luci-i18n-firewall-ko is not set\n# CONFIG_PACKAGE_luci-i18n-firewall-mr is not set\n# CONFIG_PACKAGE_luci-i18n-firewall-ms is not set\n# CONFIG_PACKAGE_luci-i18n-firewall-nl is not set\n# CONFIG_PACKAGE_luci-i18n-firewall-no is not set\n# CONFIG_PACKAGE_luci-i18n-firewall-pl is not set\n# CONFIG_PACKAGE_luci-i18n-firewall-pt is not set\n# CONFIG_PACKAGE_luci-i18n-firewall-pt-br is not set\n# CONFIG_PACKAGE_luci-i18n-firewall-ro is not set\n# CONFIG_PACKAGE_luci-i18n-firewall-ru is not set\n# CONFIG_PACKAGE_luci-i18n-firewall-si is not set\n# CONFIG_PACKAGE_luci-i18n-firewall-sk is not set\n# CONFIG_PACKAGE_luci-i18n-firewall-sv is not set\n# CONFIG_PACKAGE_luci-i18n-firewall-tr is not set\n# CONFIG_PACKAGE_luci-i18n-firewall-uk is not set\n# CONFIG_PACKAGE_luci-i18n-firewall-vi is not set\nCONFIG_PACKAGE_luci-i18n-firewall-zh-cn=y\n# CONFIG_PACKAGE_luci-i18n-firewall-zh-tw is not set\n# CONFIG_PACKAGE_luci-i18n-minidlna-ar is not set\n# CONFIG_PACKAGE_luci-i18n-minidlna-bg is not set\n# CONFIG_PACKAGE_luci-i18n-minidlna-bn is not set\n# CONFIG_PACKAGE_luci-i18n-minidlna-ca is not set\n# CONFIG_PACKAGE_luci-i18n-minidlna-cs is not set\n# CONFIG_PACKAGE_luci-i18n-minidlna-da is not set\n# CONFIG_PACKAGE_luci-i18n-minidlna-de is not set\n# CONFIG_PACKAGE_luci-i18n-minidlna-el is not set\n# CONFIG_PACKAGE_luci-i18n-minidlna-en is not set\n# CONFIG_PACKAGE_luci-i18n-minidlna-es is not set\n# CONFIG_PACKAGE_luci-i18n-minidlna-fi is not set\n# CONFIG_PACKAGE_luci-i18n-minidlna-fr is not set\n# CONFIG_PACKAGE_luci-i18n-minidlna-he is not set\n# CONFIG_PACKAGE_luci-i18n-minidlna-hi is not set\n# CONFIG_PACKAGE_luci-i18n-minidlna-hu is not set\n# CONFIG_PACKAGE_luci-i18n-minidlna-it is not set\n# CONFIG_PACKAGE_luci-i18n-minidlna-ja is not set\n# CONFIG_PACKAGE_luci-i18n-minidlna-ko is not set\n# CONFIG_PACKAGE_luci-i18n-minidlna-mr is not set\n# CONFIG_PACKAGE_luci-i18n-minidlna-ms is not set\n# CONFIG_PACKAGE_luci-i18n-minidlna-no is not set\n# CONFIG_PACKAGE_luci-i18n-minidlna-pl is not set\n# CONFIG_PACKAGE_luci-i18n-minidlna-pt is not set\n# CONFIG_PACKAGE_luci-i18n-minidlna-pt-br is not set\n# CONFIG_PACKAGE_luci-i18n-minidlna-ro is not set\n# CONFIG_PACKAGE_luci-i18n-minidlna-ru is not set\n# CONFIG_PACKAGE_luci-i18n-minidlna-sk is not set\n# CONFIG_PACKAGE_luci-i18n-minidlna-sv is not set\n# CONFIG_PACKAGE_luci-i18n-minidlna-tr is not set\n# CONFIG_PACKAGE_luci-i18n-minidlna-uk is not set\n# CONFIG_PACKAGE_luci-i18n-minidlna-vi is not set\nCONFIG_PACKAGE_luci-i18n-minidlna-zh-cn=y\n# CONFIG_PACKAGE_luci-i18n-minidlna-zh-tw is not set\n# CONFIG_PACKAGE_luci-i18n-mjpg-streamer-ar is not set\n# CONFIG_PACKAGE_luci-i18n-mjpg-streamer-bg is not set\n# CONFIG_PACKAGE_luci-i18n-mjpg-streamer-bn is not set\n# CONFIG_PACKAGE_luci-i18n-mjpg-streamer-ca is not set\n# CONFIG_PACKAGE_luci-i18n-mjpg-streamer-cs is not set\n# CONFIG_PACKAGE_luci-i18n-mjpg-streamer-da is not set\n# CONFIG_PACKAGE_luci-i18n-mjpg-streamer-de is not set\n# CONFIG_PACKAGE_luci-i18n-mjpg-streamer-el is not set\n# CONFIG_PACKAGE_luci-i18n-mjpg-streamer-en is not set\n# CONFIG_PACKAGE_luci-i18n-mjpg-streamer-es is not set\n# CONFIG_PACKAGE_luci-i18n-mjpg-streamer-fi is not set\n# CONFIG_PACKAGE_luci-i18n-mjpg-streamer-fr is not set\n# CONFIG_PACKAGE_luci-i18n-mjpg-streamer-he is not set\n# CONFIG_PACKAGE_luci-i18n-mjpg-streamer-hi is not set\n# CONFIG_PACKAGE_luci-i18n-mjpg-streamer-hu is not set\n# CONFIG_PACKAGE_luci-i18n-mjpg-streamer-it is not set\n# CONFIG_PACKAGE_luci-i18n-mjpg-streamer-ja is not set\n# CONFIG_PACKAGE_luci-i18n-mjpg-streamer-ko is not set\n# CONFIG_PACKAGE_luci-i18n-mjpg-streamer-mr is not set\n# CONFIG_PACKAGE_luci-i18n-mjpg-streamer-ms is not set\n# CONFIG_PACKAGE_luci-i18n-mjpg-streamer-no is not set\n# CONFIG_PACKAGE_luci-i18n-mjpg-streamer-pl is not set\n# CONFIG_PACKAGE_luci-i18n-mjpg-streamer-pt is not set\n# CONFIG_PACKAGE_luci-i18n-mjpg-streamer-pt-br is not set\n# CONFIG_PACKAGE_luci-i18n-mjpg-streamer-ro is not set\n# CONFIG_PACKAGE_luci-i18n-mjpg-streamer-ru is not set\n# CONFIG_PACKAGE_luci-i18n-mjpg-streamer-sk is not set\n# CONFIG_PACKAGE_luci-i18n-mjpg-streamer-sv is not set\n# CONFIG_PACKAGE_luci-i18n-mjpg-streamer-tr is not set\n# CONFIG_PACKAGE_luci-i18n-mjpg-streamer-uk is not set\n# CONFIG_PACKAGE_luci-i18n-mjpg-streamer-vi is not set\nCONFIG_PACKAGE_luci-i18n-mjpg-streamer-zh-cn=y\n# CONFIG_PACKAGE_luci-i18n-mjpg-streamer-zh-tw is not set\n# CONFIG_PACKAGE_luci-i18n-nlbwmon-ar is not set\n# CONFIG_PACKAGE_luci-i18n-nlbwmon-bg is not set\n# CONFIG_PACKAGE_luci-i18n-nlbwmon-bn is not set\n# CONFIG_PACKAGE_luci-i18n-nlbwmon-ca is not set\n# CONFIG_PACKAGE_luci-i18n-nlbwmon-cs is not set\n# CONFIG_PACKAGE_luci-i18n-nlbwmon-da is not set\n# CONFIG_PACKAGE_luci-i18n-nlbwmon-de is not set\n# CONFIG_PACKAGE_luci-i18n-nlbwmon-el is not set\n# CONFIG_PACKAGE_luci-i18n-nlbwmon-en is not set\n# CONFIG_PACKAGE_luci-i18n-nlbwmon-es is not set\n# CONFIG_PACKAGE_luci-i18n-nlbwmon-fi is not set\n# CONFIG_PACKAGE_luci-i18n-nlbwmon-fr is not set\n# CONFIG_PACKAGE_luci-i18n-nlbwmon-he is not set\n# CONFIG_PACKAGE_luci-i18n-nlbwmon-hi is not set\n# CONFIG_PACKAGE_luci-i18n-nlbwmon-hu is not set\n# CONFIG_PACKAGE_luci-i18n-nlbwmon-it is not set\n# CONFIG_PACKAGE_luci-i18n-nlbwmon-ja is not set\n# CONFIG_PACKAGE_luci-i18n-nlbwmon-ko is not set\n# CONFIG_PACKAGE_luci-i18n-nlbwmon-mr is not set\n# CONFIG_PACKAGE_luci-i18n-nlbwmon-ms is not set\n# CONFIG_PACKAGE_luci-i18n-nlbwmon-no is not set\n# CONFIG_PACKAGE_luci-i18n-nlbwmon-pl is not set\n# CONFIG_PACKAGE_luci-i18n-nlbwmon-pt is not set\n# CONFIG_PACKAGE_luci-i18n-nlbwmon-pt-br is not set\n# CONFIG_PACKAGE_luci-i18n-nlbwmon-ro is not set\n# CONFIG_PACKAGE_luci-i18n-nlbwmon-ru is not set\n# CONFIG_PACKAGE_luci-i18n-nlbwmon-sk is not set\n# CONFIG_PACKAGE_luci-i18n-nlbwmon-sv is not set\n# CONFIG_PACKAGE_luci-i18n-nlbwmon-tr is not set\n# CONFIG_PACKAGE_luci-i18n-nlbwmon-uk is not set\n# CONFIG_PACKAGE_luci-i18n-nlbwmon-vi is not set\nCONFIG_PACKAGE_luci-i18n-nlbwmon-zh-cn=y\n# CONFIG_PACKAGE_luci-i18n-nlbwmon-zh-tw is not set\n# CONFIG_PACKAGE_luci-i18n-ntpc-ar is not set\n# CONFIG_PACKAGE_luci-i18n-ntpc-bg is not set\n# CONFIG_PACKAGE_luci-i18n-ntpc-bn is not set\n# CONFIG_PACKAGE_luci-i18n-ntpc-bs is not set\n# CONFIG_PACKAGE_luci-i18n-ntpc-ca is not set\n# CONFIG_PACKAGE_luci-i18n-ntpc-cs is not set\n# CONFIG_PACKAGE_luci-i18n-ntpc-da is not set\n# CONFIG_PACKAGE_luci-i18n-ntpc-de is not set\n# CONFIG_PACKAGE_luci-i18n-ntpc-el is not set\n# CONFIG_PACKAGE_luci-i18n-ntpc-en is not set\n# CONFIG_PACKAGE_luci-i18n-ntpc-es is not set\n# CONFIG_PACKAGE_luci-i18n-ntpc-fi is not set\n# CONFIG_PACKAGE_luci-i18n-ntpc-fr is not set\n# CONFIG_PACKAGE_luci-i18n-ntpc-he is not set\n# CONFIG_PACKAGE_luci-i18n-ntpc-hi is not set\n# CONFIG_PACKAGE_luci-i18n-ntpc-hu is not set\n# CONFIG_PACKAGE_luci-i18n-ntpc-it is not set\n# CONFIG_PACKAGE_luci-i18n-ntpc-ja is not set\n# CONFIG_PACKAGE_luci-i18n-ntpc-ko is not set\n# CONFIG_PACKAGE_luci-i18n-ntpc-mr is not set\n# CONFIG_PACKAGE_luci-i18n-ntpc-ms is not set\n# CONFIG_PACKAGE_luci-i18n-ntpc-no is not set\n# CONFIG_PACKAGE_luci-i18n-ntpc-pl is not set\n# CONFIG_PACKAGE_luci-i18n-ntpc-pt is not set\n# CONFIG_PACKAGE_luci-i18n-ntpc-pt-br is not set\n# CONFIG_PACKAGE_luci-i18n-ntpc-ro is not set\n# CONFIG_PACKAGE_luci-i18n-ntpc-ru is not set\n# CONFIG_PACKAGE_luci-i18n-ntpc-sk is not set\n# CONFIG_PACKAGE_luci-i18n-ntpc-sv is not set\n# CONFIG_PACKAGE_luci-i18n-ntpc-tr is not set\n# CONFIG_PACKAGE_luci-i18n-ntpc-uk is not set\n# CONFIG_PACKAGE_luci-i18n-ntpc-vi is not set\nCONFIG_PACKAGE_luci-i18n-ntpc-zh-cn=y\n# CONFIG_PACKAGE_luci-i18n-ntpc-zh-tw is not set\n# CONFIG_PACKAGE_luci-i18n-openvpn-ar is not set\n# CONFIG_PACKAGE_luci-i18n-openvpn-bg is not set\n# CONFIG_PACKAGE_luci-i18n-openvpn-bn is not set\n# CONFIG_PACKAGE_luci-i18n-openvpn-ca is not set\n# CONFIG_PACKAGE_luci-i18n-openvpn-cs is not set\n# CONFIG_PACKAGE_luci-i18n-openvpn-da is not set\n# CONFIG_PACKAGE_luci-i18n-openvpn-de is not set\n# CONFIG_PACKAGE_luci-i18n-openvpn-el is not set\n# CONFIG_PACKAGE_luci-i18n-openvpn-en is not set\n# CONFIG_PACKAGE_luci-i18n-openvpn-es is not set\n# CONFIG_PACKAGE_luci-i18n-openvpn-fa is not set\n# CONFIG_PACKAGE_luci-i18n-openvpn-fi is not set\n# CONFIG_PACKAGE_luci-i18n-openvpn-fr is not set\n# CONFIG_PACKAGE_luci-i18n-openvpn-he is not set\n# CONFIG_PACKAGE_luci-i18n-openvpn-hi is not set\n# CONFIG_PACKAGE_luci-i18n-openvpn-hu is not set\n# CONFIG_PACKAGE_luci-i18n-openvpn-it is not set\n# CONFIG_PACKAGE_luci-i18n-openvpn-ja is not set\n# CONFIG_PACKAGE_luci-i18n-openvpn-ko is not set\n# CONFIG_PACKAGE_luci-i18n-openvpn-mr is not set\n# CONFIG_PACKAGE_luci-i18n-openvpn-ms is not set\n# CONFIG_PACKAGE_luci-i18n-openvpn-no is not set\n# CONFIG_PACKAGE_luci-i18n-openvpn-pl is not set\n# CONFIG_PACKAGE_luci-i18n-openvpn-pt is not set\n# CONFIG_PACKAGE_luci-i18n-openvpn-pt-br is not set\n# CONFIG_PACKAGE_luci-i18n-openvpn-ro is not set\n# CONFIG_PACKAGE_luci-i18n-openvpn-ru is not set\n# CONFIG_PACKAGE_luci-i18n-openvpn-sk is not set\n# CONFIG_PACKAGE_luci-i18n-openvpn-sv is not set\n# CONFIG_PACKAGE_luci-i18n-openvpn-tr is not set\n# CONFIG_PACKAGE_luci-i18n-openvpn-uk is not set\n# CONFIG_PACKAGE_luci-i18n-openvpn-vi is not set\nCONFIG_PACKAGE_luci-i18n-openvpn-zh-cn=y\n# CONFIG_PACKAGE_luci-i18n-openvpn-zh-tw is not set\n# CONFIG_PACKAGE_luci-i18n-opkg-ar is not set\n# CONFIG_PACKAGE_luci-i18n-opkg-bg is not set\n# CONFIG_PACKAGE_luci-i18n-opkg-bn is not set\n# CONFIG_PACKAGE_luci-i18n-opkg-ca is not set\n# CONFIG_PACKAGE_luci-i18n-opkg-cs is not set\n# CONFIG_PACKAGE_luci-i18n-opkg-da is not set\n# CONFIG_PACKAGE_luci-i18n-opkg-de is not set\n# CONFIG_PACKAGE_luci-i18n-opkg-el is not set\n# CONFIG_PACKAGE_luci-i18n-opkg-en is not set\n# CONFIG_PACKAGE_luci-i18n-opkg-es is not set\n# CONFIG_PACKAGE_luci-i18n-opkg-fi is not set\n# CONFIG_PACKAGE_luci-i18n-opkg-fr is not set\n# CONFIG_PACKAGE_luci-i18n-opkg-he is not set\n# CONFIG_PACKAGE_luci-i18n-opkg-hi is not set\n# CONFIG_PACKAGE_luci-i18n-opkg-hu is not set\n# CONFIG_PACKAGE_luci-i18n-opkg-it is not set\n# CONFIG_PACKAGE_luci-i18n-opkg-ja is not set\n# CONFIG_PACKAGE_luci-i18n-opkg-ko is not set\n# CONFIG_PACKAGE_luci-i18n-opkg-mr is not set\n# CONFIG_PACKAGE_luci-i18n-opkg-ms is not set\n# CONFIG_PACKAGE_luci-i18n-opkg-no is not set\n# CONFIG_PACKAGE_luci-i18n-opkg-pl is not set\n# CONFIG_PACKAGE_luci-i18n-opkg-pt is not set\n# CONFIG_PACKAGE_luci-i18n-opkg-pt-br is not set\n# CONFIG_PACKAGE_luci-i18n-opkg-ro is not set\n# CONFIG_PACKAGE_luci-i18n-opkg-ru is not set\n# CONFIG_PACKAGE_luci-i18n-opkg-sk is not set\n# CONFIG_PACKAGE_luci-i18n-opkg-sv is not set\n# CONFIG_PACKAGE_luci-i18n-opkg-tr is not set\n# CONFIG_PACKAGE_luci-i18n-opkg-uk is not set\n# CONFIG_PACKAGE_luci-i18n-opkg-vi is not set\nCONFIG_PACKAGE_luci-i18n-opkg-zh-cn=y\n# CONFIG_PACKAGE_luci-i18n-opkg-zh-tw is not set\n# CONFIG_PACKAGE_luci-i18n-qos-ar is not set\n# CONFIG_PACKAGE_luci-i18n-qos-bg is not set\n# CONFIG_PACKAGE_luci-i18n-qos-bn is not set\n# CONFIG_PACKAGE_luci-i18n-qos-ca is not set\n# CONFIG_PACKAGE_luci-i18n-qos-cs is not set\n# CONFIG_PACKAGE_luci-i18n-qos-da is not set\n# CONFIG_PACKAGE_luci-i18n-qos-de is not set\n# CONFIG_PACKAGE_luci-i18n-qos-el is not set\n# CONFIG_PACKAGE_luci-i18n-qos-en is not set\n# CONFIG_PACKAGE_luci-i18n-qos-es is not set\n# CONFIG_PACKAGE_luci-i18n-qos-fi is not set\n# CONFIG_PACKAGE_luci-i18n-qos-fr is not set\n# CONFIG_PACKAGE_luci-i18n-qos-he is not set\n# CONFIG_PACKAGE_luci-i18n-qos-hi is not set\n# CONFIG_PACKAGE_luci-i18n-qos-hu is not set\n# CONFIG_PACKAGE_luci-i18n-qos-it is not set\n# CONFIG_PACKAGE_luci-i18n-qos-ja is not set\n# CONFIG_PACKAGE_luci-i18n-qos-ko is not set\n# CONFIG_PACKAGE_luci-i18n-qos-mr is not set\n# CONFIG_PACKAGE_luci-i18n-qos-ms is not set\n# CONFIG_PACKAGE_luci-i18n-qos-no is not set\n# CONFIG_PACKAGE_luci-i18n-qos-pl is not set\n# CONFIG_PACKAGE_luci-i18n-qos-pt is not set\n# CONFIG_PACKAGE_luci-i18n-qos-pt-br is not set\n# CONFIG_PACKAGE_luci-i18n-qos-ro is not set\n# CONFIG_PACKAGE_luci-i18n-qos-ru is not set\n# CONFIG_PACKAGE_luci-i18n-qos-sk is not set\n# CONFIG_PACKAGE_luci-i18n-qos-sv is not set\n# CONFIG_PACKAGE_luci-i18n-qos-tr is not set\n# CONFIG_PACKAGE_luci-i18n-qos-uk is not set\n# CONFIG_PACKAGE_luci-i18n-qos-vi is not set\nCONFIG_PACKAGE_luci-i18n-qos-zh-cn=y\n# CONFIG_PACKAGE_luci-i18n-qos-zh-tw is not set\n# CONFIG_PACKAGE_luci-i18n-samba4-ar is not set\n# CONFIG_PACKAGE_luci-i18n-samba4-bg is not set\n# CONFIG_PACKAGE_luci-i18n-samba4-bn is not set\n# CONFIG_PACKAGE_luci-i18n-samba4-ca is not set\n# CONFIG_PACKAGE_luci-i18n-samba4-cs is not set\n# CONFIG_PACKAGE_luci-i18n-samba4-da is not set\n# CONFIG_PACKAGE_luci-i18n-samba4-de is not set\n# CONFIG_PACKAGE_luci-i18n-samba4-el is not set\n# CONFIG_PACKAGE_luci-i18n-samba4-en is not set\n# CONFIG_PACKAGE_luci-i18n-samba4-es is not set\n# CONFIG_PACKAGE_luci-i18n-samba4-fi is not set\n# CONFIG_PACKAGE_luci-i18n-samba4-fr is not set\n# CONFIG_PACKAGE_luci-i18n-samba4-he is not set\n# CONFIG_PACKAGE_luci-i18n-samba4-hi is not set\n# CONFIG_PACKAGE_luci-i18n-samba4-hu is not set\n# CONFIG_PACKAGE_luci-i18n-samba4-it is not set\n# CONFIG_PACKAGE_luci-i18n-samba4-ja is not set\n# CONFIG_PACKAGE_luci-i18n-samba4-ko is not set\n# CONFIG_PACKAGE_luci-i18n-samba4-mr is not set\n# CONFIG_PACKAGE_luci-i18n-samba4-ms is not set\n# CONFIG_PACKAGE_luci-i18n-samba4-nl is not set\n# CONFIG_PACKAGE_luci-i18n-samba4-no is not set\n# CONFIG_PACKAGE_luci-i18n-samba4-pl is not set\n# CONFIG_PACKAGE_luci-i18n-samba4-pt is not set\n# CONFIG_PACKAGE_luci-i18n-samba4-pt-br is not set\n# CONFIG_PACKAGE_luci-i18n-samba4-ro is not set\n# CONFIG_PACKAGE_luci-i18n-samba4-ru is not set\n# CONFIG_PACKAGE_luci-i18n-samba4-sk is not set\n# CONFIG_PACKAGE_luci-i18n-samba4-sv is not set\n# CONFIG_PACKAGE_luci-i18n-samba4-tr is not set\n# CONFIG_PACKAGE_luci-i18n-samba4-uk is not set\n# CONFIG_PACKAGE_luci-i18n-samba4-vi is not set\nCONFIG_PACKAGE_luci-i18n-samba4-zh-cn=y\n# CONFIG_PACKAGE_luci-i18n-samba4-zh-tw is not set\n# CONFIG_PACKAGE_luci-i18n-shadowsocks-libev-ar is not set\n# CONFIG_PACKAGE_luci-i18n-shadowsocks-libev-bg is not set\n# CONFIG_PACKAGE_luci-i18n-shadowsocks-libev-bn is not set\n# CONFIG_PACKAGE_luci-i18n-shadowsocks-libev-ca is not set\n# CONFIG_PACKAGE_luci-i18n-shadowsocks-libev-cs is not set\n# CONFIG_PACKAGE_luci-i18n-shadowsocks-libev-da is not set\n# CONFIG_PACKAGE_luci-i18n-shadowsocks-libev-de is not set\n# CONFIG_PACKAGE_luci-i18n-shadowsocks-libev-el is not set\n# CONFIG_PACKAGE_luci-i18n-shadowsocks-libev-en is not set\n# CONFIG_PACKAGE_luci-i18n-shadowsocks-libev-es is not set\n# CONFIG_PACKAGE_luci-i18n-shadowsocks-libev-fi is not set\n# CONFIG_PACKAGE_luci-i18n-shadowsocks-libev-fr is not set\n# CONFIG_PACKAGE_luci-i18n-shadowsocks-libev-he is not set\n# CONFIG_PACKAGE_luci-i18n-shadowsocks-libev-hi is not set\n# CONFIG_PACKAGE_luci-i18n-shadowsocks-libev-hu is not set\n# CONFIG_PACKAGE_luci-i18n-shadowsocks-libev-it is not set\n# CONFIG_PACKAGE_luci-i18n-shadowsocks-libev-ja is not set\n# CONFIG_PACKAGE_luci-i18n-shadowsocks-libev-ko is not set\n# CONFIG_PACKAGE_luci-i18n-shadowsocks-libev-mr is not set\n# CONFIG_PACKAGE_luci-i18n-shadowsocks-libev-ms is not set\n# CONFIG_PACKAGE_luci-i18n-shadowsocks-libev-no is not set\n# CONFIG_PACKAGE_luci-i18n-shadowsocks-libev-pl is not set\n# CONFIG_PACKAGE_luci-i18n-shadowsocks-libev-pt is not set\n# CONFIG_PACKAGE_luci-i18n-shadowsocks-libev-pt-br is not set\n# CONFIG_PACKAGE_luci-i18n-shadowsocks-libev-ro is not set\n# CONFIG_PACKAGE_luci-i18n-shadowsocks-libev-ru is not set\n# CONFIG_PACKAGE_luci-i18n-shadowsocks-libev-sk is not set\n# CONFIG_PACKAGE_luci-i18n-shadowsocks-libev-sv is not set\n# CONFIG_PACKAGE_luci-i18n-shadowsocks-libev-tr is not set\n# CONFIG_PACKAGE_luci-i18n-shadowsocks-libev-uk is not set\n# CONFIG_PACKAGE_luci-i18n-shadowsocks-libev-vi is not set\nCONFIG_PACKAGE_luci-i18n-shadowsocks-libev-zh-cn=y\n# CONFIG_PACKAGE_luci-i18n-shadowsocks-libev-zh-tw is not set\n# CONFIG_PACKAGE_luci-i18n-sqm-ar is not set\n# CONFIG_PACKAGE_luci-i18n-sqm-bg is not set\n# CONFIG_PACKAGE_luci-i18n-sqm-bn is not set\n# CONFIG_PACKAGE_luci-i18n-sqm-ca is not set\n# CONFIG_PACKAGE_luci-i18n-sqm-cs is not set\n# CONFIG_PACKAGE_luci-i18n-sqm-da is not set\n# CONFIG_PACKAGE_luci-i18n-sqm-de is not set\n# CONFIG_PACKAGE_luci-i18n-sqm-el is not set\n# CONFIG_PACKAGE_luci-i18n-sqm-en is not set\n# CONFIG_PACKAGE_luci-i18n-sqm-es is not set\n# CONFIG_PACKAGE_luci-i18n-sqm-fi is not set\n# CONFIG_PACKAGE_luci-i18n-sqm-fr is not set\n# CONFIG_PACKAGE_luci-i18n-sqm-he is not set\n# CONFIG_PACKAGE_luci-i18n-sqm-hi is not set\n# CONFIG_PACKAGE_luci-i18n-sqm-hu is not set\n# CONFIG_PACKAGE_luci-i18n-sqm-it is not set\n# CONFIG_PACKAGE_luci-i18n-sqm-ja is not set\n# CONFIG_PACKAGE_luci-i18n-sqm-ko is not set\n# CONFIG_PACKAGE_luci-i18n-sqm-mr is not set\n# CONFIG_PACKAGE_luci-i18n-sqm-ms is not set\n# CONFIG_PACKAGE_luci-i18n-sqm-no is not set\n# CONFIG_PACKAGE_luci-i18n-sqm-pl is not set\n# CONFIG_PACKAGE_luci-i18n-sqm-pt is not set\n# CONFIG_PACKAGE_luci-i18n-sqm-pt-br is not set\n# CONFIG_PACKAGE_luci-i18n-sqm-ro is not set\n# CONFIG_PACKAGE_luci-i18n-sqm-ru is not set\n# CONFIG_PACKAGE_luci-i18n-sqm-sk is not set\n# CONFIG_PACKAGE_luci-i18n-sqm-sv is not set\n# CONFIG_PACKAGE_luci-i18n-sqm-tr is not set\n# CONFIG_PACKAGE_luci-i18n-sqm-uk is not set\n# CONFIG_PACKAGE_luci-i18n-sqm-vi is not set\nCONFIG_PACKAGE_luci-i18n-sqm-zh-cn=y\n# CONFIG_PACKAGE_luci-i18n-sqm-zh-tw is not set\n# CONFIG_PACKAGE_luci-i18n-squid-ar is not set\n# CONFIG_PACKAGE_luci-i18n-squid-bg is not set\n# CONFIG_PACKAGE_luci-i18n-squid-bn is not set\n# CONFIG_PACKAGE_luci-i18n-squid-ca is not set\n# CONFIG_PACKAGE_luci-i18n-squid-cs is not set\n# CONFIG_PACKAGE_luci-i18n-squid-da is not set\n# CONFIG_PACKAGE_luci-i18n-squid-de is not set\n# CONFIG_PACKAGE_luci-i18n-squid-el is not set\n# CONFIG_PACKAGE_luci-i18n-squid-en is not set\n# CONFIG_PACKAGE_luci-i18n-squid-es is not set\n# CONFIG_PACKAGE_luci-i18n-squid-fi is not set\n# CONFIG_PACKAGE_luci-i18n-squid-fr is not set\n# CONFIG_PACKAGE_luci-i18n-squid-he is not set\n# CONFIG_PACKAGE_luci-i18n-squid-hi is not set\n# CONFIG_PACKAGE_luci-i18n-squid-hu is not set\n# CONFIG_PACKAGE_luci-i18n-squid-it is not set\n# CONFIG_PACKAGE_luci-i18n-squid-ja is not set\n# CONFIG_PACKAGE_luci-i18n-squid-ko is not set\n# CONFIG_PACKAGE_luci-i18n-squid-mr is not set\n# CONFIG_PACKAGE_luci-i18n-squid-ms is not set\n# CONFIG_PACKAGE_luci-i18n-squid-no is not set\n# CONFIG_PACKAGE_luci-i18n-squid-pl is not set\n# CONFIG_PACKAGE_luci-i18n-squid-pt is not set\n# CONFIG_PACKAGE_luci-i18n-squid-pt-br is not set\n# CONFIG_PACKAGE_luci-i18n-squid-ro is not set\n# CONFIG_PACKAGE_luci-i18n-squid-ru is not set\n# CONFIG_PACKAGE_luci-i18n-squid-sk is not set\n# CONFIG_PACKAGE_luci-i18n-squid-sv is not set\n# CONFIG_PACKAGE_luci-i18n-squid-tr is not set\n# CONFIG_PACKAGE_luci-i18n-squid-uk is not set\n# CONFIG_PACKAGE_luci-i18n-squid-vi is not set\nCONFIG_PACKAGE_luci-i18n-squid-zh-cn=y\n# CONFIG_PACKAGE_luci-i18n-squid-zh-tw is not set\n# CONFIG_PACKAGE_luci-i18n-statistics-ar is not set\n# CONFIG_PACKAGE_luci-i18n-statistics-bg is not set\n# CONFIG_PACKAGE_luci-i18n-statistics-bn is not set\n# CONFIG_PACKAGE_luci-i18n-statistics-bs is not set\n# CONFIG_PACKAGE_luci-i18n-statistics-ca is not set\n# CONFIG_PACKAGE_luci-i18n-statistics-cs is not set\n# CONFIG_PACKAGE_luci-i18n-statistics-da is not set\n# CONFIG_PACKAGE_luci-i18n-statistics-de is not set\n# CONFIG_PACKAGE_luci-i18n-statistics-el is not set\n# CONFIG_PACKAGE_luci-i18n-statistics-en is not set\n# CONFIG_PACKAGE_luci-i18n-statistics-es is not set\n# CONFIG_PACKAGE_luci-i18n-statistics-fi is not set\n# CONFIG_PACKAGE_luci-i18n-statistics-fr is not set\n# CONFIG_PACKAGE_luci-i18n-statistics-he is not set\n# CONFIG_PACKAGE_luci-i18n-statistics-hi is not set\n# CONFIG_PACKAGE_luci-i18n-statistics-hu is not set\n# CONFIG_PACKAGE_luci-i18n-statistics-it is not set\n# CONFIG_PACKAGE_luci-i18n-statistics-ja is not set\n# CONFIG_PACKAGE_luci-i18n-statistics-ko is not set\n# CONFIG_PACKAGE_luci-i18n-statistics-mr is not set\n# CONFIG_PACKAGE_luci-i18n-statistics-ms is not set\n# CONFIG_PACKAGE_luci-i18n-statistics-nl is not set\n# CONFIG_PACKAGE_luci-i18n-statistics-no is not set\n# CONFIG_PACKAGE_luci-i18n-statistics-pl is not set\n# CONFIG_PACKAGE_luci-i18n-statistics-pt is not set\n# CONFIG_PACKAGE_luci-i18n-statistics-pt-br is not set\n# CONFIG_PACKAGE_luci-i18n-statistics-ro is not set\n# CONFIG_PACKAGE_luci-i18n-statistics-ru is not set\n# CONFIG_PACKAGE_luci-i18n-statistics-sk is not set\n# CONFIG_PACKAGE_luci-i18n-statistics-sv is not set\n# CONFIG_PACKAGE_luci-i18n-statistics-tr is not set\n# CONFIG_PACKAGE_luci-i18n-statistics-uk is not set\n# CONFIG_PACKAGE_luci-i18n-statistics-vi is not set\nCONFIG_PACKAGE_luci-i18n-statistics-zh-cn=y\n# CONFIG_PACKAGE_luci-i18n-statistics-zh-tw is not set\n# CONFIG_PACKAGE_luci-i18n-transmission-ar is not set\n# CONFIG_PACKAGE_luci-i18n-transmission-bg is not set\n# CONFIG_PACKAGE_luci-i18n-transmission-bn is not set\n# CONFIG_PACKAGE_luci-i18n-transmission-ca is not set\n# CONFIG_PACKAGE_luci-i18n-transmission-cs is not set\n# CONFIG_PACKAGE_luci-i18n-transmission-da is not set\n# CONFIG_PACKAGE_luci-i18n-transmission-de is not set\n# CONFIG_PACKAGE_luci-i18n-transmission-el is not set\n# CONFIG_PACKAGE_luci-i18n-transmission-en is not set\n# CONFIG_PACKAGE_luci-i18n-transmission-es is not set\n# CONFIG_PACKAGE_luci-i18n-transmission-fi is not set\n# CONFIG_PACKAGE_luci-i18n-transmission-fr is not set\n# CONFIG_PACKAGE_luci-i18n-transmission-he is not set\n# CONFIG_PACKAGE_luci-i18n-transmission-hi is not set\n# CONFIG_PACKAGE_luci-i18n-transmission-hu is not set\n# CONFIG_PACKAGE_luci-i18n-transmission-it is not set\n# CONFIG_PACKAGE_luci-i18n-transmission-ja is not set\n# CONFIG_PACKAGE_luci-i18n-transmission-ko is not set\n# CONFIG_PACKAGE_luci-i18n-transmission-mr is not set\n# CONFIG_PACKAGE_luci-i18n-transmission-ms is not set\n# CONFIG_PACKAGE_luci-i18n-transmission-no is not set\n# CONFIG_PACKAGE_luci-i18n-transmission-pl is not set\n# CONFIG_PACKAGE_luci-i18n-transmission-pt is not set\n# CONFIG_PACKAGE_luci-i18n-transmission-pt-br is not set\n# CONFIG_PACKAGE_luci-i18n-transmission-ro is not set\n# CONFIG_PACKAGE_luci-i18n-transmission-ru is not set\n# CONFIG_PACKAGE_luci-i18n-transmission-sk is not set\n# CONFIG_PACKAGE_luci-i18n-transmission-sv is not set\n# CONFIG_PACKAGE_luci-i18n-transmission-tr is not set\n# CONFIG_PACKAGE_luci-i18n-transmission-uk is not set\n# CONFIG_PACKAGE_luci-i18n-transmission-vi is not set\nCONFIG_PACKAGE_luci-i18n-transmission-zh-cn=y\n# CONFIG_PACKAGE_luci-i18n-transmission-zh-tw is not set\n# CONFIG_PACKAGE_luci-i18n-ttyd-ar is not set\n# CONFIG_PACKAGE_luci-i18n-ttyd-bg is not set\n# CONFIG_PACKAGE_luci-i18n-ttyd-bn is not set\n# CONFIG_PACKAGE_luci-i18n-ttyd-ca is not set\n# CONFIG_PACKAGE_luci-i18n-ttyd-cs is not set\n# CONFIG_PACKAGE_luci-i18n-ttyd-da is not set\n# CONFIG_PACKAGE_luci-i18n-ttyd-de is not set\n# CONFIG_PACKAGE_luci-i18n-ttyd-el is not set\n# CONFIG_PACKAGE_luci-i18n-ttyd-en is not set\n# CONFIG_PACKAGE_luci-i18n-ttyd-es is not set\n# CONFIG_PACKAGE_luci-i18n-ttyd-fi is not set\n# CONFIG_PACKAGE_luci-i18n-ttyd-fr is not set\n# CONFIG_PACKAGE_luci-i18n-ttyd-he is not set\n# CONFIG_PACKAGE_luci-i18n-ttyd-hi is not set\n# CONFIG_PACKAGE_luci-i18n-ttyd-hu is not set\n# CONFIG_PACKAGE_luci-i18n-ttyd-it is not set\n# CONFIG_PACKAGE_luci-i18n-ttyd-ja is not set\n# CONFIG_PACKAGE_luci-i18n-ttyd-ko is not set\n# CONFIG_PACKAGE_luci-i18n-ttyd-mr is not set\n# CONFIG_PACKAGE_luci-i18n-ttyd-ms is not set\n# CONFIG_PACKAGE_luci-i18n-ttyd-no is not set\n# CONFIG_PACKAGE_luci-i18n-ttyd-pl is not set\n# CONFIG_PACKAGE_luci-i18n-ttyd-pt is not set\n# CONFIG_PACKAGE_luci-i18n-ttyd-pt-br is not set\n# CONFIG_PACKAGE_luci-i18n-ttyd-ro is not set\n# CONFIG_PACKAGE_luci-i18n-ttyd-ru is not set\n# CONFIG_PACKAGE_luci-i18n-ttyd-sk is not set\n# CONFIG_PACKAGE_luci-i18n-ttyd-sv is not set\n# CONFIG_PACKAGE_luci-i18n-ttyd-tr is not set\n# CONFIG_PACKAGE_luci-i18n-ttyd-uk is not set\n# CONFIG_PACKAGE_luci-i18n-ttyd-vi is not set\nCONFIG_PACKAGE_luci-i18n-ttyd-zh-cn=y\n# CONFIG_PACKAGE_luci-i18n-ttyd-zh-tw is not set\n# CONFIG_PACKAGE_luci-i18n-unbound-ar is not set\n# CONFIG_PACKAGE_luci-i18n-unbound-bg is not set\n# CONFIG_PACKAGE_luci-i18n-unbound-bn is not set\n# CONFIG_PACKAGE_luci-i18n-unbound-ca is not set\n# CONFIG_PACKAGE_luci-i18n-unbound-cs is not set\n# CONFIG_PACKAGE_luci-i18n-unbound-da is not set\n# CONFIG_PACKAGE_luci-i18n-unbound-de is not set\n# CONFIG_PACKAGE_luci-i18n-unbound-el is not set\n# CONFIG_PACKAGE_luci-i18n-unbound-en is not set\n# CONFIG_PACKAGE_luci-i18n-unbound-es is not set\n# CONFIG_PACKAGE_luci-i18n-unbound-fi is not set\n# CONFIG_PACKAGE_luci-i18n-unbound-fr is not set\n# CONFIG_PACKAGE_luci-i18n-unbound-he is not set\n# CONFIG_PACKAGE_luci-i18n-unbound-hi is not set\n# CONFIG_PACKAGE_luci-i18n-unbound-hu is not set\n# CONFIG_PACKAGE_luci-i18n-unbound-it is not set\n# CONFIG_PACKAGE_luci-i18n-unbound-ja is not set\n# CONFIG_PACKAGE_luci-i18n-unbound-ko is not set\n# CONFIG_PACKAGE_luci-i18n-unbound-mr is not set\n# CONFIG_PACKAGE_luci-i18n-unbound-ms is not set\n# CONFIG_PACKAGE_luci-i18n-unbound-no is not set\n# CONFIG_PACKAGE_luci-i18n-unbound-pl is not set\n# CONFIG_PACKAGE_luci-i18n-unbound-pt is not set\n# CONFIG_PACKAGE_luci-i18n-unbound-pt-br is not set\n# CONFIG_PACKAGE_luci-i18n-unbound-ro is not set\n# CONFIG_PACKAGE_luci-i18n-unbound-ru is not set\n# CONFIG_PACKAGE_luci-i18n-unbound-sk is not set\n# CONFIG_PACKAGE_luci-i18n-unbound-sv is not set\n# CONFIG_PACKAGE_luci-i18n-unbound-tr is not set\n# CONFIG_PACKAGE_luci-i18n-unbound-uk is not set\n# CONFIG_PACKAGE_luci-i18n-unbound-vi is not set\nCONFIG_PACKAGE_luci-i18n-unbound-zh-cn=y\n# CONFIG_PACKAGE_luci-i18n-unbound-zh-tw is not set\n# CONFIG_PACKAGE_luci-i18n-vnstat2-ar is not set\n# CONFIG_PACKAGE_luci-i18n-vnstat2-bg is not set\n# CONFIG_PACKAGE_luci-i18n-vnstat2-bn is not set\n# CONFIG_PACKAGE_luci-i18n-vnstat2-ca is not set\n# CONFIG_PACKAGE_luci-i18n-vnstat2-cs is not set\n# CONFIG_PACKAGE_luci-i18n-vnstat2-da is not set\n# CONFIG_PACKAGE_luci-i18n-vnstat2-de is not set\n# CONFIG_PACKAGE_luci-i18n-vnstat2-el is not set\n# CONFIG_PACKAGE_luci-i18n-vnstat2-en is not set\n# CONFIG_PACKAGE_luci-i18n-vnstat2-es is not set\n# CONFIG_PACKAGE_luci-i18n-vnstat2-fi is not set\n# CONFIG_PACKAGE_luci-i18n-vnstat2-fr is not set\n# CONFIG_PACKAGE_luci-i18n-vnstat2-he is not set\n# CONFIG_PACKAGE_luci-i18n-vnstat2-hi is not set\n# CONFIG_PACKAGE_luci-i18n-vnstat2-hu is not set\n# CONFIG_PACKAGE_luci-i18n-vnstat2-it is not set\n# CONFIG_PACKAGE_luci-i18n-vnstat2-ja is not set\n# CONFIG_PACKAGE_luci-i18n-vnstat2-ko is not set\n# CONFIG_PACKAGE_luci-i18n-vnstat2-mr is not set\n# CONFIG_PACKAGE_luci-i18n-vnstat2-ms is not set\n# CONFIG_PACKAGE_luci-i18n-vnstat2-no is not set\n# CONFIG_PACKAGE_luci-i18n-vnstat2-pl is not set\n# CONFIG_PACKAGE_luci-i18n-vnstat2-pt is not set\n# CONFIG_PACKAGE_luci-i18n-vnstat2-pt-br is not set\n# CONFIG_PACKAGE_luci-i18n-vnstat2-ro is not set\n# CONFIG_PACKAGE_luci-i18n-vnstat2-ru is not set\n# CONFIG_PACKAGE_luci-i18n-vnstat2-sk is not set\n# CONFIG_PACKAGE_luci-i18n-vnstat2-sv is not set\n# CONFIG_PACKAGE_luci-i18n-vnstat2-tr is not set\n# CONFIG_PACKAGE_luci-i18n-vnstat2-uk is not set\n# CONFIG_PACKAGE_luci-i18n-vnstat2-vi is not set\nCONFIG_PACKAGE_luci-i18n-vnstat2-zh-cn=y\n# CONFIG_PACKAGE_luci-i18n-vnstat2-zh-tw is not set\n# CONFIG_PACKAGE_luci-i18n-watchcat-ar is not set\n# CONFIG_PACKAGE_luci-i18n-watchcat-bg is not set\n# CONFIG_PACKAGE_luci-i18n-watchcat-bn is not set\n# CONFIG_PACKAGE_luci-i18n-watchcat-ca is not set\n# CONFIG_PACKAGE_luci-i18n-watchcat-cs is not set\n# CONFIG_PACKAGE_luci-i18n-watchcat-da is not set\n# CONFIG_PACKAGE_luci-i18n-watchcat-de is not set\n# CONFIG_PACKAGE_luci-i18n-watchcat-el is not set\n# CONFIG_PACKAGE_luci-i18n-watchcat-en is not set\n# CONFIG_PACKAGE_luci-i18n-watchcat-es is not set\n# CONFIG_PACKAGE_luci-i18n-watchcat-fi is not set\n# CONFIG_PACKAGE_luci-i18n-watchcat-fr is not set\n# CONFIG_PACKAGE_luci-i18n-watchcat-he is not set\n# CONFIG_PACKAGE_luci-i18n-watchcat-hi is not set\n# CONFIG_PACKAGE_luci-i18n-watchcat-hu is not set\n# CONFIG_PACKAGE_luci-i18n-watchcat-it is not set\n# CONFIG_PACKAGE_luci-i18n-watchcat-ja is not set\n# CONFIG_PACKAGE_luci-i18n-watchcat-ko is not set\n# CONFIG_PACKAGE_luci-i18n-watchcat-mr is not set\n# CONFIG_PACKAGE_luci-i18n-watchcat-ms is not set\n# CONFIG_PACKAGE_luci-i18n-watchcat-no is not set\n# CONFIG_PACKAGE_luci-i18n-watchcat-pl is not set\n# CONFIG_PACKAGE_luci-i18n-watchcat-pt is not set\n# CONFIG_PACKAGE_luci-i18n-watchcat-pt-br is not set\n# CONFIG_PACKAGE_luci-i18n-watchcat-ro is not set\n# CONFIG_PACKAGE_luci-i18n-watchcat-ru is not set\n# CONFIG_PACKAGE_luci-i18n-watchcat-sk is not set\n# CONFIG_PACKAGE_luci-i18n-watchcat-sv is not set\n# CONFIG_PACKAGE_luci-i18n-watchcat-tr is not set\n# CONFIG_PACKAGE_luci-i18n-watchcat-uk is not set\n# CONFIG_PACKAGE_luci-i18n-watchcat-vi is not set\nCONFIG_PACKAGE_luci-i18n-watchcat-zh-cn=y\n# CONFIG_PACKAGE_luci-i18n-watchcat-zh-tw is not set\n# CONFIG_PACKAGE_luci-i18n-wireguard-ar is not set\n# CONFIG_PACKAGE_luci-i18n-wireguard-bg is not set\n# CONFIG_PACKAGE_luci-i18n-wireguard-bn is not set\n# CONFIG_PACKAGE_luci-i18n-wireguard-ca is not set\n# CONFIG_PACKAGE_luci-i18n-wireguard-cs is not set\n# CONFIG_PACKAGE_luci-i18n-wireguard-da is not set\n# CONFIG_PACKAGE_luci-i18n-wireguard-de is not set\n# CONFIG_PACKAGE_luci-i18n-wireguard-el is not set\n# CONFIG_PACKAGE_luci-i18n-wireguard-en is not set\n# CONFIG_PACKAGE_luci-i18n-wireguard-es is not set\n# CONFIG_PACKAGE_luci-i18n-wireguard-fi is not set\n# CONFIG_PACKAGE_luci-i18n-wireguard-fr is not set\n# CONFIG_PACKAGE_luci-i18n-wireguard-he is not set\n# CONFIG_PACKAGE_luci-i18n-wireguard-hi is not set\n# CONFIG_PACKAGE_luci-i18n-wireguard-hu is not set\n# CONFIG_PACKAGE_luci-i18n-wireguard-id is not set\n# CONFIG_PACKAGE_luci-i18n-wireguard-it is not set\n# CONFIG_PACKAGE_luci-i18n-wireguard-ja is not set\n# CONFIG_PACKAGE_luci-i18n-wireguard-ko is not set\n# CONFIG_PACKAGE_luci-i18n-wireguard-mr is not set\n# CONFIG_PACKAGE_luci-i18n-wireguard-ms is not set\n# CONFIG_PACKAGE_luci-i18n-wireguard-no is not set\n# CONFIG_PACKAGE_luci-i18n-wireguard-pl is not set\n# CONFIG_PACKAGE_luci-i18n-wireguard-pt is not set\n# CONFIG_PACKAGE_luci-i18n-wireguard-pt-br is not set\n# CONFIG_PACKAGE_luci-i18n-wireguard-ro is not set\n# CONFIG_PACKAGE_luci-i18n-wireguard-ru is not set\n# CONFIG_PACKAGE_luci-i18n-wireguard-sk is not set\n# CONFIG_PACKAGE_luci-i18n-wireguard-sv is not set\n# CONFIG_PACKAGE_luci-i18n-wireguard-tr is not set\n# CONFIG_PACKAGE_luci-i18n-wireguard-uk is not set\n# CONFIG_PACKAGE_luci-i18n-wireguard-vi is not set\nCONFIG_PACKAGE_luci-i18n-wireguard-zh-cn=y\n# CONFIG_PACKAGE_luci-i18n-wireguard-zh-tw is not set\n# end of LuCI\n\n#\n# Mail\n#\n# CONFIG_PACKAGE_alpine is not set\n# CONFIG_PACKAGE_bogofilter is not set\n# CONFIG_PACKAGE_dovecot is not set\n# CONFIG_PACKAGE_dovecot-pigeonhole is not set\n# CONFIG_PACKAGE_dovecot-utils is not set\n# CONFIG_PACKAGE_emailrelay is not set\n# CONFIG_PACKAGE_exim is not set\n# CONFIG_PACKAGE_exim-gnutls is not set\n# CONFIG_PACKAGE_exim-ldap is not set\n# CONFIG_PACKAGE_exim-openssl is not set\n# CONFIG_PACKAGE_fdm is not set\n# CONFIG_PACKAGE_greyfix is not set\n# CONFIG_PACKAGE_mailsend is not set\n# CONFIG_PACKAGE_mailsend-nossl is not set\n# CONFIG_PACKAGE_mblaze is not set\n# CONFIG_PACKAGE_msmtp is not set\n# CONFIG_PACKAGE_msmtp-mta is not set\n# CONFIG_PACKAGE_msmtp-nossl is not set\n# CONFIG_PACKAGE_msmtp-queue is not set\n# CONFIG_PACKAGE_mutt is not set\n# CONFIG_PACKAGE_nail is not set\n# CONFIG_PACKAGE_opendkim is not set\n# CONFIG_PACKAGE_opendkim-tools is not set\n# CONFIG_PACKAGE_postfix is not set\n# CONFIG_PACKAGE_spamc is not set\n# CONFIG_PACKAGE_spamc-ssl is not set\n# end of Mail\n\n#\n# Multimedia\n#\n\n#\n# Streaming\n#\n# CONFIG_PACKAGE_oggfwd is not set\n# end of Streaming\n\n# CONFIG_PACKAGE_ffmpeg is not set\n# CONFIG_PACKAGE_ffprobe is not set\n# CONFIG_PACKAGE_fswebcam is not set\n# CONFIG_PACKAGE_gerbera is not set\n# CONFIG_PACKAGE_gphoto2 is not set\n# CONFIG_PACKAGE_graphicsmagick is not set\n# CONFIG_PACKAGE_grilo is not set\n# CONFIG_PACKAGE_grilo-plugins is not set\n# CONFIG_PACKAGE_gst1-libav is not set\n# CONFIG_PACKAGE_gstreamer1-libs is not set\n# CONFIG_PACKAGE_gstreamer1-plugins-bad is not set\n# CONFIG_PACKAGE_gstreamer1-plugins-base is not set\n# CONFIG_PACKAGE_gstreamer1-plugins-good is not set\n# CONFIG_PACKAGE_gstreamer1-plugins-ugly is not set\n# CONFIG_PACKAGE_gstreamer1-utils is not set\n# CONFIG_PACKAGE_icecast is not set\n# CONFIG_PACKAGE_imagemagick is not set\n# CONFIG_PACKAGE_lcdgrilo is not set\nCONFIG_PACKAGE_minidlna=y\n# CONFIG_PACKAGE_minisatip is not set\nCONFIG_PACKAGE_mjpg-streamer=y\n# CONFIG_PACKAGE_mjpg-streamer-input-file is not set\n# CONFIG_PACKAGE_mjpg-streamer-input-http is not set\n# CONFIG_PACKAGE_mjpg-streamer-input-uvc is not set\n# CONFIG_PACKAGE_mjpg-streamer-output-file is not set\n# CONFIG_PACKAGE_mjpg-streamer-output-http is not set\n# CONFIG_PACKAGE_mjpg-streamer-output-rtsp is not set\n# CONFIG_PACKAGE_mjpg-streamer-output-zmq is not set\n# CONFIG_PACKAGE_mjpg-streamer-www is not set\n# CONFIG_PACKAGE_mjpg-streamer-www-simple is not set\n# CONFIG_PACKAGE_motion is not set\n# CONFIG_PACKAGE_tvheadend is not set\n# CONFIG_PACKAGE_v4l2rtspserver is not set\n# CONFIG_PACKAGE_v4l2tools is not set\n# CONFIG_PACKAGE_vips is not set\n# CONFIG_PACKAGE_xupnpd is not set\n# CONFIG_PACKAGE_youtube-dl is not set\n# end of Multimedia\n\n#\n# Network\n#\n\n#\n# BitTorrent\n#\n# CONFIG_PACKAGE_mktorrent is not set\n# CONFIG_PACKAGE_opentracker is not set\n# CONFIG_PACKAGE_opentracker6 is not set\n# CONFIG_PACKAGE_rtorrent is not set\n# CONFIG_PACKAGE_rtorrent-rpc is not set\n# CONFIG_PACKAGE_transmission-cli is not set\nCONFIG_PACKAGE_transmission-daemon=y\n# CONFIG_PACKAGE_transmission-remote is not set\n# CONFIG_PACKAGE_transmission-web is not set\n# CONFIG_PACKAGE_transmission-web-control is not set\n# end of BitTorrent\n\n#\n# Captive Portals\n#\n# CONFIG_PACKAGE_apfree-wifidog is not set\n# CONFIG_PACKAGE_coova-chilli is not set\n# CONFIG_PACKAGE_nodogsplash is not set\n# CONFIG_PACKAGE_opennds is not set\n# CONFIG_PACKAGE_wifidog is not set\n# CONFIG_PACKAGE_wifidog-tls is not set\n# end of Captive Portals\n\n#\n# Cloud Manager\n#\n# CONFIG_PACKAGE_cloudreve is not set\n# CONFIG_PACKAGE_rclone-ng is not set\n# CONFIG_PACKAGE_rclone-webui-react is not set\n# end of Cloud Manager\n\n#\n# Dial-in/up\n#\n# CONFIG_PACKAGE_rp-pppoe-common is not set\n# CONFIG_PACKAGE_rp-pppoe-relay is not set\n# CONFIG_PACKAGE_rp-pppoe-server is not set\n# end of Dial-in/up\n\n#\n# Download Manager\n#\nCONFIG_PACKAGE_ariang=y\n# CONFIG_PACKAGE_ariang-nginx is not set\n# CONFIG_PACKAGE_leech is not set\nCONFIG_PACKAGE_webui-aria2=y\n# end of Download Manager\n\n#\n# File Transfer\n#\nCONFIG_PACKAGE_aria2=y\n\n#\n# Aria2 Configuration\n#\nCONFIG_ARIA2_OPENSSL=y\n# CONFIG_ARIA2_GNUTLS is not set\n# CONFIG_ARIA2_NOSSL is not set\n# CONFIG_ARIA2_LIBXML2 is not set\n# CONFIG_ARIA2_EXPAT is not set\nCONFIG_ARIA2_NOXML=y\nCONFIG_ARIA2_BITTORRENT=y\n# CONFIG_ARIA2_SFTP is not set\n# CONFIG_ARIA2_ASYNC_DNS is not set\n# CONFIG_ARIA2_COOKIE is not set\nCONFIG_ARIA2_WEBSOCKET=y\n# end of Aria2 Configuration\n\n# CONFIG_PACKAGE_atftp is not set\n# CONFIG_PACKAGE_atftpd is not set\n# CONFIG_PACKAGE_curl is not set\n# CONFIG_PACKAGE_gnurl is not set\n# CONFIG_PACKAGE_lftp is not set\n# CONFIG_PACKAGE_rclone is not set\n# CONFIG_PACKAGE_rrsync is not set\nCONFIG_PACKAGE_rsync=y\n# CONFIG_RSYNC_xattr is not set\n# CONFIG_RSYNC_acl is not set\n# CONFIG_RSYNC_zstd is not set\nCONFIG_PACKAGE_rsyncd=y\n# CONFIG_PACKAGE_vsftpd is not set\n# CONFIG_PACKAGE_vsftpd-tls is not set\n# CONFIG_PACKAGE_wget-nossl is not set\n# CONFIG_PACKAGE_wget-ssl is not set\n# end of File Transfer\n\n#\n# Filesystem\n#\n# CONFIG_PACKAGE_davfs2 is not set\n# CONFIG_PACKAGE_ksmbd-avahi-service is not set\n# CONFIG_PACKAGE_ksmbd-server is not set\n# CONFIG_PACKAGE_ksmbd-utils is not set\n# CONFIG_PACKAGE_nfs-kernel-server is not set\n# CONFIG_PACKAGE_owftpd is not set\n# CONFIG_PACKAGE_owhttpd is not set\n# CONFIG_PACKAGE_owserver is not set\n# CONFIG_PACKAGE_sshfs is not set\n# end of Filesystem\n\n#\n# Firewall\n#\n# CONFIG_PACKAGE_arptables is not set\n# CONFIG_PACKAGE_conntrack is not set\n# CONFIG_PACKAGE_conntrackd is not set\n# CONFIG_PACKAGE_ebtables is not set\n# CONFIG_PACKAGE_fwknop is not set\n# CONFIG_PACKAGE_fwknopd is not set\nCONFIG_PACKAGE_ip6tables=y\n# CONFIG_PACKAGE_ip6tables-extra is not set\n# CONFIG_PACKAGE_ip6tables-mod-nat is not set\nCONFIG_PACKAGE_iptables=y\n# CONFIG_IPTABLES_CONNLABEL is not set\n# CONFIG_IPTABLES_NFTABLES is not set\n# CONFIG_PACKAGE_iptables-mod-account is not set\n# CONFIG_PACKAGE_iptables-mod-chaos is not set\n# CONFIG_PACKAGE_iptables-mod-checksum is not set\n# CONFIG_PACKAGE_iptables-mod-cluster is not set\n# CONFIG_PACKAGE_iptables-mod-clusterip is not set\n# CONFIG_PACKAGE_iptables-mod-condition is not set\nCONFIG_PACKAGE_iptables-mod-conntrack-extra=y\n# CONFIG_PACKAGE_iptables-mod-delude is not set\n# CONFIG_PACKAGE_iptables-mod-dhcpmac is not set\n# CONFIG_PACKAGE_iptables-mod-dnetmap is not set\nCONFIG_PACKAGE_iptables-mod-extra=y\n# CONFIG_PACKAGE_iptables-mod-filter is not set\n# CONFIG_PACKAGE_iptables-mod-fuzzy is not set\n# CONFIG_PACKAGE_iptables-mod-geoip is not set\n# CONFIG_PACKAGE_iptables-mod-hashlimit is not set\n# CONFIG_PACKAGE_iptables-mod-iface is not set\n# CONFIG_PACKAGE_iptables-mod-ipmark is not set\nCONFIG_PACKAGE_iptables-mod-ipopt=y\n# CONFIG_PACKAGE_iptables-mod-ipp2p is not set\n# CONFIG_PACKAGE_iptables-mod-iprange is not set\n# CONFIG_PACKAGE_iptables-mod-ipsec is not set\n# CONFIG_PACKAGE_iptables-mod-ipv4options is not set\n# CONFIG_PACKAGE_iptables-mod-led is not set\n# CONFIG_PACKAGE_iptables-mod-length2 is not set\n# CONFIG_PACKAGE_iptables-mod-logmark is not set\n# CONFIG_PACKAGE_iptables-mod-lscan is not set\n# CONFIG_PACKAGE_iptables-mod-lua is not set\n# CONFIG_PACKAGE_iptables-mod-nat-extra is not set\n# CONFIG_PACKAGE_iptables-mod-nflog is not set\n# CONFIG_PACKAGE_iptables-mod-nfqueue is not set\n# CONFIG_PACKAGE_iptables-mod-physdev is not set\n# CONFIG_PACKAGE_iptables-mod-proto is not set\n# CONFIG_PACKAGE_iptables-mod-psd is not set\n# CONFIG_PACKAGE_iptables-mod-quota2 is not set\n# CONFIG_PACKAGE_iptables-mod-rpfilter is not set\n# CONFIG_PACKAGE_iptables-mod-rtpengine is not set\n# CONFIG_PACKAGE_iptables-mod-sysrq is not set\n# CONFIG_PACKAGE_iptables-mod-tarpit is not set\n# CONFIG_PACKAGE_iptables-mod-tee is not set\nCONFIG_PACKAGE_iptables-mod-tproxy=y\n# CONFIG_PACKAGE_iptables-mod-trace is not set\n# CONFIG_PACKAGE_iptables-mod-u32 is not set\n# CONFIG_PACKAGE_iptables-mod-ulog is not set\n# CONFIG_PACKAGE_iptaccount is not set\n# CONFIG_PACKAGE_iptgeoip is not set\n\n#\n# Select iptgeoip options\n#\n# CONFIG_IPTGEOIP_PRESERVE is not set\n# end of Select iptgeoip options\n\n# CONFIG_PACKAGE_miniupnpc is not set\n# CONFIG_PACKAGE_miniupnpd is not set\n# CONFIG_PACKAGE_miniupnpd-igdv1 is not set\n# CONFIG_PACKAGE_natpmpc is not set\n# CONFIG_PACKAGE_nftables-json is not set\n# CONFIG_PACKAGE_nftables-nojson is not set\n# CONFIG_PACKAGE_shorewall is not set\n# CONFIG_PACKAGE_shorewall-core is not set\n# CONFIG_PACKAGE_shorewall-lite is not set\n# CONFIG_PACKAGE_shorewall6 is not set\n# CONFIG_PACKAGE_shorewall6-lite is not set\n# CONFIG_PACKAGE_snort is not set\n# CONFIG_PACKAGE_snort3 is not set\n# end of Firewall\n\n#\n# Firewall Tunnel\n#\n# CONFIG_PACKAGE_iodine is not set\n# CONFIG_PACKAGE_iodined is not set\n# end of Firewall Tunnel\n\n#\n# FreeRADIUS (version 3)\n#\n# CONFIG_PACKAGE_freeradius3 is not set\n# CONFIG_PACKAGE_freeradius3-common is not set\n# CONFIG_PACKAGE_freeradius3-utils is not set\n# end of FreeRADIUS (version 3)\n\n#\n# IP Addresses and Names\n#\n# CONFIG_PACKAGE_aggregate is not set\n# CONFIG_PACKAGE_announce is not set\n# CONFIG_PACKAGE_avahi-autoipd is not set\n# CONFIG_PACKAGE_avahi-daemon-service-http is not set\n# CONFIG_PACKAGE_avahi-daemon-service-ssh is not set\nCONFIG_PACKAGE_avahi-dbus-daemon=y\n# CONFIG_PACKAGE_avahi-dnsconfd is not set\n# CONFIG_PACKAGE_avahi-nodbus-daemon is not set\n# CONFIG_PACKAGE_avahi-utils is not set\n# CONFIG_PACKAGE_bind-check is not set\n# CONFIG_PACKAGE_bind-client is not set\n# CONFIG_PACKAGE_bind-dig is not set\n# CONFIG_PACKAGE_bind-dnssec is not set\n# CONFIG_PACKAGE_bind-host is not set\n# CONFIG_PACKAGE_bind-nslookup is not set\n# CONFIG_PACKAGE_bind-rndc is not set\n# CONFIG_PACKAGE_bind-server is not set\n# CONFIG_PACKAGE_bind-tools is not set\nCONFIG_PACKAGE_ddns-scripts=y\n# CONFIG_PACKAGE_ddns-scripts-cloudflare is not set\n# CONFIG_PACKAGE_ddns-scripts-cnkuai is not set\n# CONFIG_PACKAGE_ddns-scripts-digitalocean is not set\n# CONFIG_PACKAGE_ddns-scripts-dnspod is not set\n# CONFIG_PACKAGE_ddns-scripts-freedns is not set\n# CONFIG_PACKAGE_ddns-scripts-gandi is not set\n# CONFIG_PACKAGE_ddns-scripts-godaddy is not set\n# CONFIG_PACKAGE_ddns-scripts-noip is not set\n# CONFIG_PACKAGE_ddns-scripts-nsupdate is not set\n# CONFIG_PACKAGE_ddns-scripts-pdns is not set\n# CONFIG_PACKAGE_ddns-scripts-route53 is not set\nCONFIG_PACKAGE_ddns-scripts-services=y\n# CONFIG_PACKAGE_dhcp-forwarder is not set\n# CONFIG_PACKAGE_dns-over-https is not set\n# CONFIG_PACKAGE_dnscrypt-proxy is not set\n# CONFIG_PACKAGE_dnscrypt-proxy-resolvers is not set\n# CONFIG_PACKAGE_dnsdist is not set\n# CONFIG_PACKAGE_dnslookup is not set\n# CONFIG_PACKAGE_dnsproxy is not set\n# CONFIG_PACKAGE_drill is not set\n# CONFIG_PACKAGE_hostip is not set\n# CONFIG_PACKAGE_idn is not set\n# CONFIG_PACKAGE_idn2 is not set\n# CONFIG_PACKAGE_inadyn is not set\n# CONFIG_PACKAGE_isc-dhcp-client-ipv4 is not set\n# CONFIG_PACKAGE_isc-dhcp-client-ipv6 is not set\n# CONFIG_PACKAGE_isc-dhcp-omshell-ipv4 is not set\n# CONFIG_PACKAGE_isc-dhcp-omshell-ipv6 is not set\n# CONFIG_PACKAGE_isc-dhcp-relay-ipv4 is not set\n# CONFIG_PACKAGE_isc-dhcp-relay-ipv6 is not set\n# CONFIG_PACKAGE_isc-dhcp-server-ipv4 is not set\n# CONFIG_PACKAGE_isc-dhcp-server-ipv6 is not set\n# CONFIG_PACKAGE_kadnode is not set\n# CONFIG_PACKAGE_kea-admin is not set\n# CONFIG_PACKAGE_kea-ctrl is not set\n# CONFIG_PACKAGE_kea-dhcp-ddns is not set\n# CONFIG_PACKAGE_kea-dhcp4 is not set\n# CONFIG_PACKAGE_kea-dhcp6 is not set\n# CONFIG_PACKAGE_kea-hook-ha is not set\n# CONFIG_PACKAGE_kea-hook-lease-cmds is not set\n# CONFIG_PACKAGE_kea-lfc is not set\n# CONFIG_PACKAGE_kea-libs is not set\n# CONFIG_PACKAGE_kea-perfdhcp is not set\n# CONFIG_PACKAGE_kea-shell is not set\n# CONFIG_PACKAGE_knot is not set\n# CONFIG_PACKAGE_knot-dig is not set\n# CONFIG_PACKAGE_knot-host is not set\n# CONFIG_PACKAGE_knot-keymgr is not set\n# CONFIG_PACKAGE_knot-nsupdate is not set\n# CONFIG_PACKAGE_knot-resolver is not set\n\n#\n# Configuration\n#\n# CONFIG_PACKAGE_knot-resolver_dnstap is not set\n# end of Configuration\n\n# CONFIG_PACKAGE_knot-tests is not set\n# CONFIG_PACKAGE_knot-zonecheck is not set\n# CONFIG_PACKAGE_ldns-examples is not set\n# CONFIG_PACKAGE_mdns-utils is not set\n# CONFIG_PACKAGE_mdnsd is not set\n# CONFIG_PACKAGE_mdnsresponder is not set\n# CONFIG_PACKAGE_nsd is not set\n# CONFIG_PACKAGE_nsd-control is not set\n# CONFIG_PACKAGE_nsd-control-setup is not set\n# CONFIG_PACKAGE_nsd-nossl is not set\n# CONFIG_PACKAGE_ohybridproxy is not set\n# CONFIG_PACKAGE_overture is not set\n# CONFIG_PACKAGE_pdns is not set\n# CONFIG_PACKAGE_pdns-ixfrdist is not set\n# CONFIG_PACKAGE_pdns-recursor is not set\n# CONFIG_PACKAGE_pdns-tools is not set\n# CONFIG_PACKAGE_stubby is not set\n# CONFIG_PACKAGE_tor-hs is not set\n# CONFIG_PACKAGE_torsocks is not set\n# CONFIG_PACKAGE_unbound-anchor is not set\n# CONFIG_PACKAGE_unbound-checkconf is not set\n# CONFIG_PACKAGE_unbound-control is not set\n# CONFIG_PACKAGE_unbound-control-setup is not set\nCONFIG_PACKAGE_unbound-daemon=y\n# CONFIG_PACKAGE_unbound-host is not set\nCONFIG_PACKAGE_wsdd2=y\n# CONFIG_PACKAGE_zonestitcher is not set\n# end of IP Addresses and Names\n\n#\n# Instant Messaging\n#\n# CONFIG_PACKAGE_bitlbee is not set\n# CONFIG_PACKAGE_irssi is not set\n# CONFIG_PACKAGE_ngircd is not set\n# CONFIG_PACKAGE_ngircd-nossl is not set\n# CONFIG_PACKAGE_prosody is not set\n# CONFIG_PACKAGE_quassel-irssi is not set\n# CONFIG_PACKAGE_umurmur-mbedtls is not set\n# CONFIG_PACKAGE_umurmur-openssl is not set\n# CONFIG_PACKAGE_znc is not set\n# end of Instant Messaging\n\n#\n# Linux ATM tools\n#\n# CONFIG_PACKAGE_atm-aread is not set\n# CONFIG_PACKAGE_atm-atmaddr is not set\n# CONFIG_PACKAGE_atm-atmdiag is not set\n# CONFIG_PACKAGE_atm-atmdump is not set\n# CONFIG_PACKAGE_atm-atmloop is not set\n# CONFIG_PACKAGE_atm-atmsigd is not set\n# CONFIG_PACKAGE_atm-atmswitch is not set\n# CONFIG_PACKAGE_atm-atmtcp is not set\n# CONFIG_PACKAGE_atm-awrite is not set\n# CONFIG_PACKAGE_atm-bus is not set\n# CONFIG_PACKAGE_atm-debug-tools is not set\n# CONFIG_PACKAGE_atm-diagnostics is not set\n# CONFIG_PACKAGE_atm-esi is not set\n# CONFIG_PACKAGE_atm-ilmid is not set\n# CONFIG_PACKAGE_atm-ilmidiag is not set\n# CONFIG_PACKAGE_atm-lecs is not set\n# CONFIG_PACKAGE_atm-les is not set\n# CONFIG_PACKAGE_atm-mpcd is not set\n# CONFIG_PACKAGE_atm-saaldump is not set\n# CONFIG_PACKAGE_atm-sonetdiag is not set\n# CONFIG_PACKAGE_atm-svc_recv is not set\n# CONFIG_PACKAGE_atm-svc_send is not set\n# CONFIG_PACKAGE_atm-tools is not set\n# CONFIG_PACKAGE_atm-ttcp_atm is not set\n# CONFIG_PACKAGE_atm-zeppelin is not set\n# CONFIG_PACKAGE_br2684ctl is not set\n# end of Linux ATM tools\n\n#\n# LoRaWAN\n#\n# CONFIG_PACKAGE_libloragw-tests is not set\n# CONFIG_PACKAGE_libloragw-utils is not set\n# end of LoRaWAN\n\n#\n# NMAP Suite\n#\n# CONFIG_PACKAGE_ncat is not set\n# CONFIG_PACKAGE_ncat-full is not set\n# CONFIG_PACKAGE_ncat-ssl is not set\n# CONFIG_PACKAGE_ndiff is not set\n# CONFIG_PACKAGE_nmap is not set\n# CONFIG_PACKAGE_nmap-full is not set\n# CONFIG_PACKAGE_nmap-ssl is not set\n# CONFIG_PACKAGE_nping is not set\n# CONFIG_PACKAGE_nping-ssl is not set\n# end of NMAP Suite\n\n#\n# NTRIP\n#\n# CONFIG_PACKAGE_ntripcaster is not set\n# CONFIG_PACKAGE_ntripclient is not set\n# CONFIG_PACKAGE_ntripserver is not set\n# end of NTRIP\n\n#\n# OLSR.org network framework\n#\n# CONFIG_PACKAGE_oonf-dlep-proxy is not set\n# CONFIG_PACKAGE_oonf-dlep-radio is not set\n# CONFIG_PACKAGE_oonf-init-scripts is not set\n# CONFIG_PACKAGE_oonf-olsrd2 is not set\n# end of OLSR.org network framework\n\n#\n# Open vSwitch\n#\n# CONFIG_PACKAGE_openvswitch is not set\n# CONFIG_PACKAGE_openvswitch-ovn-host is not set\n# CONFIG_PACKAGE_openvswitch-ovn-north is not set\n# CONFIG_PACKAGE_openvswitch-python3 is not set\n# CONFIG_PACKAGE_ovsd is not set\n# end of Open vSwitch\n\n#\n# OpenLDAP\n#\n# CONFIG_PACKAGE_libopenldap is not set\nCONFIG_OPENLDAP_DEBUG=y\n# CONFIG_OPENLDAP_CRYPT is not set\n# CONFIG_OPENLDAP_MONITOR is not set\n# CONFIG_OPENLDAP_DB47 is not set\n# CONFIG_OPENLDAP_ICU is not set\n# CONFIG_PACKAGE_openldap-server is not set\n# CONFIG_PACKAGE_openldap-utils is not set\n# end of OpenLDAP\n\n#\n# Printing\n#\n# CONFIG_PACKAGE_p910nd is not set\n# end of Printing\n\n#\n# Routing and Redirection\n#\n# CONFIG_PACKAGE_babel-pinger is not set\n# CONFIG_PACKAGE_babeld is not set\n# CONFIG_PACKAGE_batmand is not set\n# CONFIG_PACKAGE_bcp38 is not set\n# CONFIG_PACKAGE_bfdd is not set\n# CONFIG_PACKAGE_bird1-ipv4 is not set\n# CONFIG_PACKAGE_bird1-ipv4-uci is not set\n# CONFIG_PACKAGE_bird1-ipv6 is not set\n# CONFIG_PACKAGE_bird1-ipv6-uci is not set\n# CONFIG_PACKAGE_bird1c-ipv4 is not set\n# CONFIG_PACKAGE_bird1c-ipv6 is not set\n# CONFIG_PACKAGE_bird1cl-ipv4 is not set\n# CONFIG_PACKAGE_bird1cl-ipv6 is not set\n# CONFIG_PACKAGE_bird2 is not set\n# CONFIG_PACKAGE_bird2c is not set\n# CONFIG_PACKAGE_bird2cl is not set\n# CONFIG_PACKAGE_bmx6 is not set\n# CONFIG_PACKAGE_bmx7 is not set\n# CONFIG_PACKAGE_cjdns is not set\n# CONFIG_PACKAGE_cjdns-tests is not set\n# CONFIG_PACKAGE_dcstad is not set\n# CONFIG_PACKAGE_dcwapd is not set\n# CONFIG_PACKAGE_devlink is not set\n# CONFIG_PACKAGE_frr is not set\n# CONFIG_PACKAGE_genl is not set\n# CONFIG_PACKAGE_igmpproxy is not set\n# CONFIG_PACKAGE_ip-bridge is not set\n# CONFIG_PACKAGE_ip-full is not set\nCONFIG_PACKAGE_ip-tiny=y\n# CONFIG_PACKAGE_lldpd is not set\n# CONFIG_PACKAGE_mcproxy is not set\n# CONFIG_PACKAGE_mrmctl is not set\n# CONFIG_PACKAGE_mwan3 is not set\n# CONFIG_PACKAGE_nstat is not set\n# CONFIG_PACKAGE_olsrd is not set\n# CONFIG_PACKAGE_prince is not set\n# CONFIG_PACKAGE_quagga is not set\n# CONFIG_PACKAGE_rdma is not set\n# CONFIG_PACKAGE_relayd is not set\n# CONFIG_PACKAGE_smcroute is not set\n# CONFIG_PACKAGE_ss is not set\n# CONFIG_PACKAGE_sslh is not set\n# CONFIG_PACKAGE_tc-full is not set\nCONFIG_PACKAGE_tc-mod-iptables=y\nCONFIG_PACKAGE_tc-tiny=y\n# CONFIG_PACKAGE_tcpproxy is not set\n# CONFIG_PACKAGE_udp-broadcast-relay-redux is not set\n# CONFIG_PACKAGE_vis is not set\n# CONFIG_PACKAGE_yggdrasil is not set\n# end of Routing and Redirection\n\n#\n# SSH\n#\n# CONFIG_PACKAGE_autossh is not set\nCONFIG_PACKAGE_openssh-client=y\n# CONFIG_PACKAGE_openssh-client-utils is not set\nCONFIG_PACKAGE_openssh-keygen=y\n# CONFIG_PACKAGE_openssh-moduli is not set\nCONFIG_PACKAGE_openssh-server=y\nCONFIG_OPENSSH_LIBFIDO2=y\n# CONFIG_PACKAGE_openssh-server-pam is not set\nCONFIG_PACKAGE_openssh-sftp-avahi-service=y\nCONFIG_PACKAGE_openssh-sftp-client=y\nCONFIG_PACKAGE_openssh-sftp-server=y\n# CONFIG_PACKAGE_sshtunnel is not set\n# CONFIG_PACKAGE_tmate is not set\n# end of SSH\n\n#\n# THC-IPv6 attack and analyzing toolkit\n#\n# CONFIG_PACKAGE_thc-ipv6-address6 is not set\n# CONFIG_PACKAGE_thc-ipv6-alive6 is not set\n# CONFIG_PACKAGE_thc-ipv6-covert-send6 is not set\n# CONFIG_PACKAGE_thc-ipv6-covert-send6d is not set\n# CONFIG_PACKAGE_thc-ipv6-denial6 is not set\n# CONFIG_PACKAGE_thc-ipv6-detect-new-ip6 is not set\n# CONFIG_PACKAGE_thc-ipv6-detect-sniffer6 is not set\n# CONFIG_PACKAGE_thc-ipv6-dnsdict6 is not set\n# CONFIG_PACKAGE_thc-ipv6-dnsrevenum6 is not set\n# CONFIG_PACKAGE_thc-ipv6-dos-new-ip6 is not set\n# CONFIG_PACKAGE_thc-ipv6-dump-router6 is not set\n# CONFIG_PACKAGE_thc-ipv6-exploit6 is not set\n# CONFIG_PACKAGE_thc-ipv6-fake-advertise6 is not set\n# CONFIG_PACKAGE_thc-ipv6-fake-dhcps6 is not set\n# CONFIG_PACKAGE_thc-ipv6-fake-dns6d is not set\n# CONFIG_PACKAGE_thc-ipv6-fake-dnsupdate6 is not set\n# CONFIG_PACKAGE_thc-ipv6-fake-mipv6 is not set\n# CONFIG_PACKAGE_thc-ipv6-fake-mld26 is not set\n# CONFIG_PACKAGE_thc-ipv6-fake-mld6 is not set\n# CONFIG_PACKAGE_thc-ipv6-fake-mldrouter6 is not set\n# CONFIG_PACKAGE_thc-ipv6-fake-router26 is not set\n# CONFIG_PACKAGE_thc-ipv6-fake-router6 is not set\n# CONFIG_PACKAGE_thc-ipv6-fake-solicitate6 is not set\n# CONFIG_PACKAGE_thc-ipv6-flood-advertise6 is not set\n# CONFIG_PACKAGE_thc-ipv6-flood-dhcpc6 is not set\n# CONFIG_PACKAGE_thc-ipv6-flood-mld26 is not set\n# CONFIG_PACKAGE_thc-ipv6-flood-mld6 is not set\n# CONFIG_PACKAGE_thc-ipv6-flood-mldrouter6 is not set\n# CONFIG_PACKAGE_thc-ipv6-flood-router26 is not set\n# CONFIG_PACKAGE_thc-ipv6-flood-router6 is not set\n# CONFIG_PACKAGE_thc-ipv6-flood-solicitate6 is not set\n# CONFIG_PACKAGE_thc-ipv6-fragmentation6 is not set\n# CONFIG_PACKAGE_thc-ipv6-fuzz-dhcpc6 is not set\n# CONFIG_PACKAGE_thc-ipv6-fuzz-dhcps6 is not set\n# CONFIG_PACKAGE_thc-ipv6-fuzz-ip6 is not set\n# CONFIG_PACKAGE_thc-ipv6-implementation6 is not set\n# CONFIG_PACKAGE_thc-ipv6-implementation6d is not set\n# CONFIG_PACKAGE_thc-ipv6-inverse-lookup6 is not set\n# CONFIG_PACKAGE_thc-ipv6-kill-router6 is not set\n# CONFIG_PACKAGE_thc-ipv6-ndpexhaust6 is not set\n# CONFIG_PACKAGE_thc-ipv6-node-query6 is not set\n# CONFIG_PACKAGE_thc-ipv6-parasite6 is not set\n# CONFIG_PACKAGE_thc-ipv6-passive-discovery6 is not set\n# CONFIG_PACKAGE_thc-ipv6-randicmp6 is not set\n# CONFIG_PACKAGE_thc-ipv6-redir6 is not set\n# CONFIG_PACKAGE_thc-ipv6-rsmurf6 is not set\n# CONFIG_PACKAGE_thc-ipv6-sendpees6 is not set\n# CONFIG_PACKAGE_thc-ipv6-sendpeesmp6 is not set\n# CONFIG_PACKAGE_thc-ipv6-smurf6 is not set\n# CONFIG_PACKAGE_thc-ipv6-thcping6 is not set\n# CONFIG_PACKAGE_thc-ipv6-toobig6 is not set\n# CONFIG_PACKAGE_thc-ipv6-trace6 is not set\n# end of THC-IPv6 attack and analyzing toolkit\n\n#\n# Tcpreplay\n#\n# CONFIG_PACKAGE_tcpbridge is not set\n# CONFIG_PACKAGE_tcpcapinfo is not set\n# CONFIG_PACKAGE_tcpliveplay is not set\n# CONFIG_PACKAGE_tcpprep is not set\n# CONFIG_PACKAGE_tcpreplay is not set\n# CONFIG_PACKAGE_tcpreplay-all is not set\n# CONFIG_PACKAGE_tcpreplay-edit is not set\n# CONFIG_PACKAGE_tcprewrite is not set\n# end of Tcpreplay\n\n#\n# Telephony\n#\n# CONFIG_PACKAGE_asterisk is not set\n# CONFIG_PACKAGE_baresip is not set\n# CONFIG_PACKAGE_freeswitch is not set\n# CONFIG_PACKAGE_kamailio is not set\n# CONFIG_PACKAGE_miax is not set\n# CONFIG_PACKAGE_pcapsipdump is not set\n# CONFIG_PACKAGE_restund is not set\n# CONFIG_PACKAGE_rtpengine is not set\n# CONFIG_PACKAGE_rtpengine-no-transcode is not set\n# CONFIG_PACKAGE_rtpengine-recording is not set\n# CONFIG_PACKAGE_rtpproxy is not set\n# CONFIG_PACKAGE_sipp is not set\n# CONFIG_PACKAGE_siproxd is not set\n# CONFIG_PACKAGE_yate is not set\n# end of Telephony\n\n#\n# Telephony Lantiq\n#\n# end of Telephony Lantiq\n\n#\n# Time Synchronization\n#\n# CONFIG_PACKAGE_chrony is not set\n# CONFIG_PACKAGE_chrony-nts is not set\n# CONFIG_PACKAGE_htpdate is not set\n# CONFIG_PACKAGE_linuxptp is not set\n# CONFIG_PACKAGE_ntp-keygen is not set\n# CONFIG_PACKAGE_ntp-utils is not set\nCONFIG_PACKAGE_ntpclient=y\n# CONFIG_PACKAGE_ntpd is not set\n# CONFIG_PACKAGE_ntpdate is not set\n# end of Time Synchronization\n\n#\n# VPN\n#\n# CONFIG_PACKAGE_chaosvpn is not set\n# CONFIG_PACKAGE_eoip is not set\n# CONFIG_PACKAGE_fastd is not set\n# CONFIG_PACKAGE_libreswan is not set\n# CONFIG_PACKAGE_ocserv is not set\n# CONFIG_PACKAGE_openconnect is not set\n# CONFIG_PACKAGE_openfortivpn is not set\n# CONFIG_PACKAGE_openvpn-easy-rsa is not set\n# CONFIG_PACKAGE_openvpn-mbedtls is not set\n# CONFIG_PACKAGE_openvpn-openssl is not set\n# CONFIG_PACKAGE_openvpn-wolfssl is not set\n# CONFIG_PACKAGE_pptpd is not set\n# CONFIG_PACKAGE_softethervpn-base is not set\n# CONFIG_PACKAGE_softethervpn-bridge is not set\n# CONFIG_PACKAGE_softethervpn-client is not set\n# CONFIG_PACKAGE_softethervpn-server is not set\n# CONFIG_PACKAGE_softethervpn5-bridge is not set\n# CONFIG_PACKAGE_softethervpn5-client is not set\n# CONFIG_PACKAGE_softethervpn5-server is not set\n# CONFIG_PACKAGE_sstp-client is not set\n# CONFIG_PACKAGE_strongswan is not set\n# CONFIG_PACKAGE_tailscale is not set\n# CONFIG_PACKAGE_tailscaled is not set\n# CONFIG_PACKAGE_tinc is not set\n# CONFIG_PACKAGE_uanytun is not set\n# CONFIG_PACKAGE_uanytun-nettle is not set\n# CONFIG_PACKAGE_uanytun-nocrypt is not set\n# CONFIG_PACKAGE_uanytun-sslcrypt is not set\n# CONFIG_PACKAGE_vpnc is not set\n# CONFIG_PACKAGE_vpnc-scripts is not set\nCONFIG_PACKAGE_wireguard-tools=y\n# CONFIG_PACKAGE_xl2tpd is not set\nCONFIG_PACKAGE_zerotier=y\n\n#\n# Configuration\n#\n# CONFIG_ZEROTIER_ENABLE_DEBUG is not set\n# CONFIG_ZEROTIER_ENABLE_SELFTEST is not set\n# end of Configuration\n# end of VPN\n\n#\n# Version Control Systems\n#\n# CONFIG_PACKAGE_git is not set\n# CONFIG_PACKAGE_git-http is not set\n# CONFIG_PACKAGE_subversion-client is not set\n# CONFIG_PACKAGE_subversion-libs is not set\n# CONFIG_PACKAGE_subversion-server is not set\n# end of Version Control Systems\n\n#\n# WWAN\n#\n# CONFIG_PACKAGE_adb-enablemodem is not set\n# CONFIG_PACKAGE_comgt is not set\n# CONFIG_PACKAGE_comgt-directip is not set\n# CONFIG_PACKAGE_comgt-ncm is not set\n# CONFIG_PACKAGE_umbim is not set\n# CONFIG_PACKAGE_uqmi is not set\n# end of WWAN\n\n#\n# Web Servers/Proxies\n#\n# CONFIG_PACKAGE_apache is not set\nCONFIG_PACKAGE_cgi-io=y\n# CONFIG_PACKAGE_clamav is not set\n# CONFIG_PACKAGE_etebase is not set\n# CONFIG_PACKAGE_freshclam is not set\n# CONFIG_PACKAGE_frpc is not set\n# CONFIG_PACKAGE_frps is not set\n# CONFIG_PACKAGE_gateway-go is not set\n# CONFIG_PACKAGE_gunicorn3 is not set\n# CONFIG_PACKAGE_haproxy is not set\n# CONFIG_PACKAGE_haproxy-nossl is not set\n# CONFIG_PACKAGE_kcptun-client is not set\n# CONFIG_PACKAGE_kcptun-config is not set\n# CONFIG_PACKAGE_kcptun-server is not set\n# CONFIG_PACKAGE_lighttpd is not set\n# CONFIG_PACKAGE_nginx-all-module is not set\n# CONFIG_PACKAGE_nginx-mod-luci is not set\n# CONFIG_PACKAGE_nginx-ssl is not set\n# CONFIG_PACKAGE_nginx-ssl-util is not set\n# CONFIG_PACKAGE_nginx-ssl-util-nopcre is not set\n# CONFIG_PACKAGE_polipo is not set\n# CONFIG_PACKAGE_privoxy is not set\n# CONFIG_PACKAGE_python3-gunicorn is not set\n# CONFIG_PACKAGE_radicale is not set\n# CONFIG_PACKAGE_radicale2 is not set\n# CONFIG_PACKAGE_radicale2-examples is not set\nCONFIG_PACKAGE_shadowsocks-libev-config=y\nCONFIG_PACKAGE_shadowsocks-libev-ss-local=y\nCONFIG_PACKAGE_shadowsocks-libev-ss-redir=y\nCONFIG_PACKAGE_shadowsocks-libev-ss-rules=y\nCONFIG_PACKAGE_shadowsocks-libev-ss-server=y\nCONFIG_PACKAGE_shadowsocks-libev-ss-tunnel=y\n# CONFIG_PACKAGE_sockd is not set\n# CONFIG_PACKAGE_socksify is not set\n# CONFIG_PACKAGE_spawn-fcgi is not set\nCONFIG_PACKAGE_squid=y\n\n#\n# Optional features\n#\nCONFIG_SQUID_enable-ipv6=y\n# CONFIG_SQUID_enable-snmp is not set\n# CONFIG_SQUID_enable-icmp is not set\n# CONFIG_SQUID_enable-icap-client is not set\nCONFIG_SQUID_enable-dlmalloc=y\n# CONFIG_SQUID_enable-ssl-crtd is not set\n# CONFIG_SQUID_auth-basic is not set\n# CONFIG_SQUID_auth-digest is not set\n# CONFIG_SQUID_auth-negotiate is not set\n# CONFIG_SQUID_auth-ntlm is not set\n\n#\n# Optional packages\n#\nCONFIG_SQUID_use-openssl=y\n# CONFIG_SQUID_use-gnutls is not set\n# CONFIG_SQUID_with-libcap is not set\n# CONFIG_SQUID_with-nettle is not set\n# CONFIG_SQUID_with-expat is not set\n# CONFIG_SQUID_with-libxml2 is not set\n\n#\n# Additional tools\n#\n# CONFIG_PACKAGE_squid-mod-cachemgr is not set\n# CONFIG_PACKAGE_tinyproxy is not set\n# CONFIG_PACKAGE_trojan-go is not set\nCONFIG_PACKAGE_uhttpd=y\n# CONFIG_PACKAGE_uhttpd-mod-lua is not set\nCONFIG_PACKAGE_uhttpd-mod-ubus=y\n# CONFIG_PACKAGE_uwsgi is not set\n# CONFIG_PACKAGE_v2raya is not set\n# end of Web Servers/Proxies\n\n#\n# Wireless\n#\n# CONFIG_PACKAGE_aircrack-ng is not set\n# CONFIG_PACKAGE_airmon-ng is not set\n# CONFIG_PACKAGE_dynapoint is not set\n# CONFIG_PACKAGE_hcxdumptool is not set\n# CONFIG_PACKAGE_hcxtools is not set\n# CONFIG_PACKAGE_horst is not set\n# CONFIG_PACKAGE_pixiewps is not set\n# CONFIG_PACKAGE_reaver is not set\n# CONFIG_PACKAGE_wavemon is not set\n# CONFIG_PACKAGE_wifischedule is not set\n# end of Wireless\n\n#\n# WirelessAPD\n#\n# CONFIG_PACKAGE_eapol-test is not set\n# CONFIG_PACKAGE_eapol-test-openssl is not set\n# CONFIG_PACKAGE_eapol-test-wolfssl is not set\n# CONFIG_PACKAGE_hostapd is not set\n# CONFIG_PACKAGE_hostapd-basic is not set\n# CONFIG_PACKAGE_hostapd-basic-openssl is not set\n# CONFIG_PACKAGE_hostapd-basic-wolfssl is not set\nCONFIG_PACKAGE_hostapd-common=y\n# CONFIG_PACKAGE_hostapd-mini is not set\n# CONFIG_PACKAGE_hostapd-openssl is not set\n# CONFIG_PACKAGE_hostapd-wolfssl is not set\n# CONFIG_PACKAGE_hs20-client is not set\n# CONFIG_PACKAGE_hs20-common is not set\n# CONFIG_PACKAGE_hs20-server is not set\n# CONFIG_PACKAGE_wpa-cli is not set\nCONFIG_PACKAGE_wpa-supplicant=y\n# CONFIG_WPA_RFKILL_SUPPORT is not set\nCONFIG_WPA_MSG_MIN_PRIORITY=3\n# CONFIG_WPA_WOLFSSL is not set\n# CONFIG_DRIVER_WEXT_SUPPORT is not set\nCONFIG_DRIVER_11N_SUPPORT=y\nCONFIG_DRIVER_11AC_SUPPORT=y\n# CONFIG_DRIVER_11AX_SUPPORT is not set\n# CONFIG_WPA_ENABLE_WEP is not set\n# CONFIG_PACKAGE_wpa-supplicant-basic is not set\n# CONFIG_PACKAGE_wpa-supplicant-mesh-openssl is not set\n# CONFIG_PACKAGE_wpa-supplicant-mesh-wolfssl is not set\n# CONFIG_PACKAGE_wpa-supplicant-mini is not set\n# CONFIG_PACKAGE_wpa-supplicant-openssl is not set\n# CONFIG_PACKAGE_wpa-supplicant-p2p is not set\n# CONFIG_PACKAGE_wpa-supplicant-wolfssl is not set\n# CONFIG_PACKAGE_wpad is not set\n# CONFIG_PACKAGE_wpad-basic is not set\n# CONFIG_PACKAGE_wpad-basic-openssl is not set\n# CONFIG_PACKAGE_wpad-basic-wolfssl is not set\n# CONFIG_PACKAGE_wpad-mesh-openssl is not set\n# CONFIG_PACKAGE_wpad-mesh-wolfssl is not set\n# CONFIG_PACKAGE_wpad-mini is not set\n# CONFIG_PACKAGE_wpad-openssl is not set\n# CONFIG_PACKAGE_wpad-wolfssl is not set\n# end of WirelessAPD\n\n#\n# arp-scan\n#\n# CONFIG_PACKAGE_arp-scan is not set\n# CONFIG_PACKAGE_arp-scan-database is not set\n# end of arp-scan\n\n# CONFIG_PACKAGE_464xlat is not set\n# CONFIG_PACKAGE_6in4 is not set\n# CONFIG_PACKAGE_6rd is not set\n# CONFIG_PACKAGE_6to4 is not set\n# CONFIG_PACKAGE_UDPspeeder is not set\n# CONFIG_PACKAGE_acme is not set\n# CONFIG_PACKAGE_acme-dnsapi is not set\nCONFIG_PACKAGE_adblock=y\n# CONFIG_PACKAGE_addrwatch is not set\n# CONFIG_PACKAGE_addrwatch-mysql is not set\n# CONFIG_PACKAGE_addrwatch-stdout is not set\n# CONFIG_PACKAGE_addrwatch-syslog is not set\n# CONFIG_PACKAGE_adguardhome is not set\n# CONFIG_PACKAGE_ahcpd is not set\n# CONFIG_PACKAGE_alfred is not set\n# CONFIG_PACKAGE_apcupsd is not set\n# CONFIG_PACKAGE_apcupsd-cgi is not set\n# CONFIG_PACKAGE_apinger is not set\n# CONFIG_PACKAGE_atlas-probe is not set\n# CONFIG_PACKAGE_atlas-sw-probe is not set\n# CONFIG_PACKAGE_atlas-sw-probe-rpc is not set\nCONFIG_PACKAGE_banip=y\n# CONFIG_PACKAGE_batctl-default is not set\n# CONFIG_PACKAGE_batctl-full is not set\n# CONFIG_PACKAGE_batctl-tiny is not set\n# CONFIG_PACKAGE_beanstalkd is not set\nCONFIG_PACKAGE_bmon=y\n# CONFIG_PACKAGE_boinc is not set\n# CONFIG_PACKAGE_bpftool-full is not set\n# CONFIG_PACKAGE_bpftool-minimal is not set\n# CONFIG_PACKAGE_bwm-ng is not set\n# CONFIG_PACKAGE_bwping is not set\n# CONFIG_PACKAGE_chat is not set\n# CONFIG_PACKAGE_cifsmount is not set\n# CONFIG_PACKAGE_coap-server is not set\n# CONFIG_PACKAGE_conserver is not set\n# CONFIG_PACKAGE_crowdsec is not set\n# CONFIG_PACKAGE_crowdsec-firewall-bouncer is not set\n# CONFIG_PACKAGE_cshark is not set\n# CONFIG_PACKAGE_daemonlogger is not set\n# CONFIG_PACKAGE_darkstat is not set\n# CONFIG_PACKAGE_dawn is not set\n# CONFIG_PACKAGE_dhcpcd is not set\n# CONFIG_PACKAGE_dmapd is not set\n# CONFIG_PACKAGE_dnscrypt-proxy2 is not set\n# CONFIG_PACKAGE_dnstap is not set\n# CONFIG_PACKAGE_dnstop is not set\n# CONFIG_PACKAGE_ds-lite is not set\n# CONFIG_PACKAGE_esniper is not set\n# CONFIG_PACKAGE_etherwake is not set\n# CONFIG_PACKAGE_etherwake-nfqueue is not set\n# CONFIG_PACKAGE_ethtool is not set\n# CONFIG_PACKAGE_ethtool-full is not set\n# CONFIG_PACKAGE_fail2ban is not set\n# CONFIG_PACKAGE_fakeidentd is not set\n# CONFIG_PACKAGE_fakepop is not set\n# CONFIG_PACKAGE_family-dns is not set\n# CONFIG_PACKAGE_foolsm is not set\n# CONFIG_PACKAGE_fping is not set\n# CONFIG_PACKAGE_generate-ipv6-address is not set\n# CONFIG_PACKAGE_geth is not set\n# CONFIG_PACKAGE_git-lfs is not set\n# CONFIG_PACKAGE_gnunet is not set\n# CONFIG_PACKAGE_gre is not set\n# CONFIG_PACKAGE_hnet-full is not set\n# CONFIG_PACKAGE_hnet-full-l2tp is not set\n# CONFIG_PACKAGE_hnet-full-secure is not set\n# CONFIG_PACKAGE_hnetd-nossl is not set\n# CONFIG_PACKAGE_hnetd-openssl is not set\n# CONFIG_PACKAGE_httping is not set\n# CONFIG_PACKAGE_httping-nossl is not set\n# CONFIG_PACKAGE_https-dns-proxy is not set\n# CONFIG_PACKAGE_httptunnel is not set\n# CONFIG_PACKAGE_i2pd is not set\n# CONFIG_PACKAGE_ibrdtn-tools is not set\n# CONFIG_PACKAGE_ibrdtnd is not set\n# CONFIG_PACKAGE_ieee8021xclient is not set\nCONFIG_PACKAGE_ifstat=y\nCONFIG_IFSTAT_SNMP=y\nCONFIG_PACKAGE_iftop=y\n# CONFIG_PACKAGE_iiod is not set\nCONFIG_PACKAGE_iperf=y\n# CONFIG_IPERF_ENABLE_MULTICAST is not set\nCONFIG_PACKAGE_iperf3=y\n# CONFIG_PACKAGE_iperf3-ssl is not set\n# CONFIG_PACKAGE_ipip is not set\nCONFIG_PACKAGE_ipset=y\n# CONFIG_PACKAGE_ipset-dns is not set\n# CONFIG_PACKAGE_iptraf-ng is not set\n# CONFIG_PACKAGE_iputils-arping is not set\n# CONFIG_PACKAGE_iputils-clockdiff is not set\n# CONFIG_PACKAGE_iputils-ping is not set\n# CONFIG_PACKAGE_iputils-tftpd is not set\n# CONFIG_PACKAGE_iputils-tracepath is not set\n# CONFIG_PACKAGE_ipvsadm is not set\n# CONFIG_PACKAGE_irtt is not set\nCONFIG_PACKAGE_iw=y\n# CONFIG_PACKAGE_iw-full is not set\n# CONFIG_PACKAGE_jool-tools is not set\n# CONFIG_PACKAGE_keepalived is not set\n# CONFIG_PACKAGE_knxd is not set\n# CONFIG_PACKAGE_kplex is not set\n# CONFIG_PACKAGE_krb5-client is not set\n# CONFIG_PACKAGE_krb5-libs is not set\n# CONFIG_PACKAGE_krb5-server is not set\n# CONFIG_PACKAGE_krb5-server-extras is not set\nCONFIG_PACKAGE_libipset=y\n# CONFIG_PACKAGE_libndp is not set\n# CONFIG_PACKAGE_linknx is not set\n# CONFIG_PACKAGE_lynx is not set\n# CONFIG_PACKAGE_mac-telnet-client is not set\n# CONFIG_PACKAGE_mac-telnet-discover is not set\n# CONFIG_PACKAGE_mac-telnet-ping is not set\n# CONFIG_PACKAGE_mac-telnet-server is not set\n# CONFIG_PACKAGE_map is not set\n# CONFIG_PACKAGE_mbusd is not set\n# CONFIG_PACKAGE_mdns-repeater is not set\n# CONFIG_PACKAGE_memcached is not set\n# CONFIG_PACKAGE_mii-tool is not set\n# CONFIG_PACKAGE_mikrotik-btest is not set\n# CONFIG_PACKAGE_mini_snmpd is not set\n# CONFIG_PACKAGE_minimalist-pcproxy is not set\n# CONFIG_PACKAGE_miredo is not set\n# CONFIG_PACKAGE_modemmanager is not set\n# CONFIG_PACKAGE_mosquitto-client-nossl is not set\n# CONFIG_PACKAGE_mosquitto-client-ssl is not set\n# CONFIG_PACKAGE_mosquitto-nossl is not set\n# CONFIG_PACKAGE_mosquitto-ssl is not set\n# CONFIG_PACKAGE_mrd6 is not set\n# CONFIG_PACKAGE_mstpd is not set\n# CONFIG_PACKAGE_mtr is not set\n# CONFIG_PACKAGE_nbd is not set\n# CONFIG_PACKAGE_nbd-server is not set\n# CONFIG_PACKAGE_ncp is not set\n# CONFIG_PACKAGE_ndppd is not set\n# CONFIG_PACKAGE_ndptool is not set\n# CONFIG_PACKAGE_nebula is not set\n# CONFIG_PACKAGE_nebula-cert is not set\n# CONFIG_PACKAGE_net-tools-route is not set\n# CONFIG_PACKAGE_netcat is not set\n# CONFIG_PACKAGE_netdiscover is not set\n# CONFIG_PACKAGE_netifyd is not set\nCONFIG_PACKAGE_netperf=y\n# CONFIG_PACKAGE_netsniff-ng is not set\n# CONFIG_PACKAGE_netstinky is not set\n# CONFIG_PACKAGE_nextdns is not set\n# CONFIG_PACKAGE_nfdump is not set\nCONFIG_PACKAGE_nlbwmon=y\n# CONFIG_PACKAGE_noping is not set\n# CONFIG_PACKAGE_nut is not set\n# CONFIG_PACKAGE_obfs4proxy is not set\nCONFIG_PACKAGE_odhcp6c=y\nCONFIG_PACKAGE_odhcp6c_ext_cer_id=0\n# CONFIG_PACKAGE_odhcpd is not set\nCONFIG_PACKAGE_odhcpd-ipv6only=y\n\n#\n# Configuration\n#\nCONFIG_PACKAGE_odhcpd_ipv6only_ext_cer_id=0\n# end of Configuration\n\n# CONFIG_PACKAGE_ola is not set\n# CONFIG_PACKAGE_omcproxy is not set\n# CONFIG_PACKAGE_onionshare-cli is not set\n# CONFIG_PACKAGE_ooniprobe is not set\n# CONFIG_PACKAGE_oor is not set\n# CONFIG_PACKAGE_open-iscsi is not set\n# CONFIG_PACKAGE_oping is not set\n# CONFIG_PACKAGE_ostiary is not set\n# CONFIG_PACKAGE_pagekitec is not set\n# CONFIG_PACKAGE_pen is not set\n# CONFIG_PACKAGE_phantap is not set\n# CONFIG_PACKAGE_pimbd is not set\n# CONFIG_PACKAGE_pingcheck is not set\n# CONFIG_PACKAGE_port-mirroring is not set\nCONFIG_PACKAGE_ppp=y\n# CONFIG_PACKAGE_ppp-mod-passwordfd is not set\n# CONFIG_PACKAGE_ppp-mod-pppoa is not set\nCONFIG_PACKAGE_ppp-mod-pppoe=y\n# CONFIG_PACKAGE_ppp-mod-pppol2tp is not set\n# CONFIG_PACKAGE_ppp-mod-pptp is not set\n# CONFIG_PACKAGE_ppp-mod-radius is not set\n# CONFIG_PACKAGE_ppp-multilink is not set\n# CONFIG_PACKAGE_pppdump is not set\n# CONFIG_PACKAGE_pppoe-discovery is not set\n# CONFIG_PACKAGE_pppossh is not set\n# CONFIG_PACKAGE_pppstats is not set\n# CONFIG_PACKAGE_proto-bonding is not set\n# CONFIG_PACKAGE_proxychains-ng is not set\n# CONFIG_PACKAGE_ptunnel-ng is not set\n# CONFIG_PACKAGE_radsecproxy is not set\n# CONFIG_PACKAGE_ratched is not set\n# CONFIG_PACKAGE_ratechecker is not set\n# CONFIG_PACKAGE_redsocks is not set\n# CONFIG_PACKAGE_remserial is not set\n# CONFIG_PACKAGE_restic-rest-server is not set\n# CONFIG_PACKAGE_rpcapd is not set\n# CONFIG_PACKAGE_rpcbind is not set\n# CONFIG_PACKAGE_rssileds is not set\n# CONFIG_PACKAGE_safe-search is not set\n# CONFIG_PACKAGE_samba4-admin is not set\n# CONFIG_PACKAGE_samba4-client is not set\nCONFIG_PACKAGE_samba4-libs=y\nCONFIG_PACKAGE_samba4-server=y\nCONFIG_SAMBA4_SERVER_WSDD2=y\nCONFIG_SAMBA4_SERVER_NETBIOS=y\nCONFIG_SAMBA4_SERVER_AVAHI=y\nCONFIG_SAMBA4_SERVER_VFS=y\n# CONFIG_SAMBA4_SERVER_VFSX is not set\n# CONFIG_SAMBA4_SERVER_AD_DC is not set\n# CONFIG_PACKAGE_samba4-utils is not set\n# CONFIG_PACKAGE_samplicator is not set\n# CONFIG_PACKAGE_scapy is not set\n# CONFIG_PACKAGE_sctp-tools is not set\n# CONFIG_PACKAGE_seafile-ccnet is not set\n# CONFIG_PACKAGE_seafile-seahub is not set\n# CONFIG_PACKAGE_seafile-server is not set\n# CONFIG_PACKAGE_seafile-server-fuse is not set\n# CONFIG_PACKAGE_ser2net is not set\n# CONFIG_PACKAGE_simple-adblock is not set\n# CONFIG_PACKAGE_smartdns is not set\n# CONFIG_PACKAGE_smbinfo is not set\n# CONFIG_PACKAGE_snmp-mibs is not set\n# CONFIG_PACKAGE_snmp-utils is not set\n# CONFIG_PACKAGE_snmpd is not set\n# CONFIG_PACKAGE_snmptrapd is not set\n# CONFIG_PACKAGE_socat is not set\n# CONFIG_PACKAGE_softflowd is not set\n# CONFIG_PACKAGE_soloscli is not set\nCONFIG_PACKAGE_speedtest-netperf=y\n# CONFIG_PACKAGE_spoofer is not set\n# CONFIG_PACKAGE_static-neighbor-reports is not set\n# CONFIG_PACKAGE_stunnel is not set\n# CONFIG_PACKAGE_switchdev-poller is not set\n# CONFIG_PACKAGE_tac_plus is not set\n# CONFIG_PACKAGE_tac_plus-pam is not set\n# CONFIG_PACKAGE_tayga is not set\nCONFIG_PACKAGE_tcpdump=y\n# CONFIG_PACKAGE_tcpdump-mini is not set\n# CONFIG_PACKAGE_tgt is not set\n# CONFIG_PACKAGE_tmate-ssh-server is not set\n# CONFIG_PACKAGE_tor is not set\n# CONFIG_PACKAGE_tor-basic is not set\n# CONFIG_PACKAGE_tor-fw-helper is not set\n# CONFIG_PACKAGE_trafficshaper is not set\n# CONFIG_PACKAGE_travelmate is not set\n# CONFIG_PACKAGE_u2pnpd is not set\n# CONFIG_PACKAGE_uacme is not set\nCONFIG_PACKAGE_uclient-fetch=y\n# CONFIG_PACKAGE_udhcpsnoop is not set\n# CONFIG_PACKAGE_udptunnel is not set\n# CONFIG_PACKAGE_udpxy is not set\n# CONFIG_PACKAGE_ulogd is not set\n# CONFIG_PACKAGE_umdns is not set\n# CONFIG_PACKAGE_uradvd is not set\n# CONFIG_PACKAGE_usbip is not set\n# CONFIG_PACKAGE_usteer is not set\n# CONFIG_PACKAGE_ustp is not set\n# CONFIG_PACKAGE_vallumd is not set\n# CONFIG_PACKAGE_vncrepeater is not set\n# CONFIG_PACKAGE_vnstat is not set\nCONFIG_PACKAGE_vnstat2=y\nCONFIG_PACKAGE_vnstati2=y\n# CONFIG_PACKAGE_vpn-policy-routing is not set\n# CONFIG_PACKAGE_vpnbypass is not set\n# CONFIG_PACKAGE_vxlan is not set\n# CONFIG_PACKAGE_wakeonlan is not set\n# CONFIG_PACKAGE_wg-installer-client is not set\n# CONFIG_PACKAGE_wg-installer-server is not set\n# CONFIG_PACKAGE_wpan-tools is not set\n# CONFIG_PACKAGE_wwan is not set\n# CONFIG_PACKAGE_xinetd is not set\n# CONFIG_PACKAGE_xray-core is not set\n# end of Network\n\n#\n# Sound\n#\n# CONFIG_PACKAGE_alsa-utils is not set\n# CONFIG_PACKAGE_alsa-utils-seq is not set\n# CONFIG_PACKAGE_alsa-utils-tests is not set\n# CONFIG_PACKAGE_aserver is not set\n# CONFIG_PACKAGE_espeak is not set\n# CONFIG_PACKAGE_faad2 is not set\n# CONFIG_PACKAGE_fdk-aac is not set\n# CONFIG_PACKAGE_ices is not set\n# CONFIG_PACKAGE_lame is not set\n# CONFIG_PACKAGE_lame-lib is not set\n# CONFIG_PACKAGE_liblo-utils is not set\n# CONFIG_PACKAGE_madplay is not set\n# CONFIG_PACKAGE_moc is not set\n# CONFIG_PACKAGE_mpc is not set\n# CONFIG_PACKAGE_mpd-avahi-service is not set\n# CONFIG_PACKAGE_mpd-full is not set\n# CONFIG_PACKAGE_mpd-mini is not set\n# CONFIG_PACKAGE_mpg123 is not set\n# CONFIG_PACKAGE_opus-tools is not set\n# CONFIG_PACKAGE_owntone is not set\n# CONFIG_PACKAGE_pianod is not set\n# CONFIG_PACKAGE_pianod-client is not set\n# CONFIG_PACKAGE_portaudio is not set\n# CONFIG_PACKAGE_pulseaudio-daemon is not set\n# CONFIG_PACKAGE_pulseaudio-daemon-avahi is not set\n# CONFIG_PACKAGE_shairplay is not set\n# CONFIG_PACKAGE_shairport-sync-mbedtls is not set\n# CONFIG_PACKAGE_shairport-sync-mini is not set\n# CONFIG_PACKAGE_shairport-sync-openssl is not set\n# CONFIG_PACKAGE_shine is not set\n# CONFIG_PACKAGE_sox is not set\n# CONFIG_PACKAGE_squeezelite-full is not set\n# CONFIG_PACKAGE_squeezelite-mini is not set\n# CONFIG_PACKAGE_svox is not set\n# CONFIG_PACKAGE_upmpdcli is not set\n# end of Sound\n\n#\n# Utilities\n#\n\n#\n# AppArmor\n#\n# CONFIG_PACKAGE_apparmor-profiles is not set\n# CONFIG_PACKAGE_apparmor-utils is not set\n# end of AppArmor\n\n#\n# BigClown\n#\n# CONFIG_PACKAGE_bigclown-control-tool is not set\n# CONFIG_PACKAGE_bigclown-firmware-tool is not set\n# CONFIG_PACKAGE_bigclown-gateway is not set\n# CONFIG_PACKAGE_bigclown-mqtt2influxdb is not set\n# end of BigClown\n\n#\n# Boot Loaders\n#\n# CONFIG_PACKAGE_fconfig is not set\nCONFIG_PACKAGE_uboot-envtools=y\n# end of Boot Loaders\n\n#\n# Compression\n#\n# CONFIG_PACKAGE_bsdtar is not set\n# CONFIG_PACKAGE_bsdtar-noopenssl is not set\n# CONFIG_PACKAGE_bzip2 is not set\n# CONFIG_PACKAGE_gzip is not set\n# CONFIG_PACKAGE_lz4 is not set\n# CONFIG_PACKAGE_pigz is not set\n# CONFIG_PACKAGE_unrar is not set\n# CONFIG_PACKAGE_unzip is not set\n# CONFIG_PACKAGE_xz-utils is not set\n# CONFIG_PACKAGE_zipcmp is not set\n# CONFIG_PACKAGE_zipmerge is not set\n# CONFIG_PACKAGE_ziptool is not set\n# CONFIG_PACKAGE_zstd is not set\n# end of Compression\n\n#\n# Database\n#\n# CONFIG_PACKAGE_mariadb-common is not set\n# CONFIG_PACKAGE_pgsql-cli is not set\n# CONFIG_PACKAGE_pgsql-cli-extra is not set\n# CONFIG_PACKAGE_pgsql-server is not set\n# CONFIG_PACKAGE_rrdcgi1 is not set\nCONFIG_PACKAGE_rrdtool1=y\n# CONFIG_PACKAGE_sqlite3-cli is not set\n# CONFIG_PACKAGE_unixodbc-tools is not set\n# end of Database\n\n#\n# Disc\n#\n# CONFIG_PACKAGE_autopart is not set\n# CONFIG_PACKAGE_blkdiscard is not set\nCONFIG_PACKAGE_blkid=y\n# CONFIG_PACKAGE_blockdev is not set\n# CONFIG_PACKAGE_cfdisk is not set\n# CONFIG_PACKAGE_cgdisk is not set\n# CONFIG_PACKAGE_eject is not set\nCONFIG_PACKAGE_fdisk=y\n# CONFIG_PACKAGE_findfs is not set\n# CONFIG_PACKAGE_fio is not set\n# CONFIG_PACKAGE_fixparts is not set\n# CONFIG_PACKAGE_gdisk is not set\n# CONFIG_PACKAGE_hd-idle is not set\n# CONFIG_PACKAGE_hdparm is not set\n# CONFIG_PACKAGE_lsblk is not set\n# CONFIG_PACKAGE_lvm2 is not set\n# CONFIG_PACKAGE_lvm2-selinux is not set\n# CONFIG_PACKAGE_mdadm is not set\n# CONFIG_PACKAGE_mtools is not set\n# CONFIG_PACKAGE_parted is not set\nCONFIG_PACKAGE_partx-utils=y\n# CONFIG_PACKAGE_sfdisk is not set\n# CONFIG_PACKAGE_sgdisk is not set\n# CONFIG_PACKAGE_uvol is not set\n# CONFIG_PACKAGE_wipefs is not set\n# end of Disc\n\n#\n# Editors\n#\n# CONFIG_PACKAGE_joe is not set\n# CONFIG_PACKAGE_joe-extras is not set\n# CONFIG_PACKAGE_jupp is not set\n# CONFIG_PACKAGE_mg is not set\nCONFIG_PACKAGE_nano=y\n# CONFIG_PACKAGE_vim is not set\n# CONFIG_PACKAGE_vim-full is not set\n# CONFIG_PACKAGE_vim-fuller is not set\n# CONFIG_PACKAGE_vim-help is not set\n# CONFIG_PACKAGE_vim-runtime is not set\n# CONFIG_PACKAGE_zile is not set\n# end of Editors\n\n#\n# Encryption\n#\n# CONFIG_PACKAGE_ccrypt is not set\n# CONFIG_PACKAGE_certtool is not set\n# CONFIG_PACKAGE_cryptsetup is not set\n# CONFIG_PACKAGE_cryptsetup-ssh is not set\n# CONFIG_PACKAGE_gnupg is not set\n# CONFIG_PACKAGE_gnupg2 is not set\n# CONFIG_PACKAGE_gnupg2-dirmngr is not set\n# CONFIG_PACKAGE_gnutls-utils is not set\n# CONFIG_PACKAGE_gpgv is not set\n# CONFIG_PACKAGE_gpgv2 is not set\n# CONFIG_PACKAGE_keyctl is not set\n# CONFIG_PACKAGE_keyutils is not set\n# CONFIG_PACKAGE_px5g-mbedtls is not set\n# CONFIG_PACKAGE_px5g-standalone is not set\nCONFIG_PACKAGE_px5g-wolfssl=y\n# CONFIG_PACKAGE_stoken is not set\n# end of Encryption\n\n#\n# Filesystem\n#\n# CONFIG_PACKAGE_acl is not set\n# CONFIG_PACKAGE_afuse is not set\n# CONFIG_PACKAGE_antfs-mount is not set\nCONFIG_PACKAGE_attr=y\n# CONFIG_PACKAGE_badblocks is not set\nCONFIG_PACKAGE_btrfs-progs=y\n# CONFIG_BTRFS_PROGS_ZSTD is not set\n# CONFIG_PACKAGE_chattr is not set\n# CONFIG_PACKAGE_debugfs is not set\n# CONFIG_PACKAGE_dosfstools is not set\n# CONFIG_PACKAGE_dumpe2fs is not set\n# CONFIG_PACKAGE_e2freefrag is not set\nCONFIG_PACKAGE_e2fsprogs=y\n# CONFIG_PACKAGE_e4crypt is not set\n# CONFIG_PACKAGE_exfat-fsck is not set\n# CONFIG_PACKAGE_exfat-mkfs is not set\n# CONFIG_PACKAGE_f2fs-tools is not set\n# CONFIG_PACKAGE_f2fs-tools-selinux is not set\n# CONFIG_PACKAGE_f2fsck is not set\n# CONFIG_PACKAGE_f2fsck-selinux is not set\n# CONFIG_PACKAGE_filefrag is not set\n# CONFIG_PACKAGE_fstrim is not set\n# CONFIG_PACKAGE_fuse-utils is not set\n# CONFIG_PACKAGE_fuse3-utils is not set\n# CONFIG_PACKAGE_hfsfsck is not set\n# CONFIG_PACKAGE_lsattr is not set\nCONFIG_PACKAGE_mkf2fs=y\n# CONFIG_PACKAGE_mkf2fs-selinux is not set\n# CONFIG_PACKAGE_mkhfs is not set\n# CONFIG_PACKAGE_ncdu is not set\n# CONFIG_PACKAGE_nfs-utils is not set\n# CONFIG_PACKAGE_nfs-utils-libs is not set\n# CONFIG_PACKAGE_ntfs-3g is not set\n# CONFIG_PACKAGE_ntfs-3g-low is not set\n# CONFIG_PACKAGE_ntfs-3g-utils is not set\n# CONFIG_PACKAGE_owfs is not set\n# CONFIG_PACKAGE_owshell is not set\n# CONFIG_PACKAGE_resize2fs is not set\n# CONFIG_PACKAGE_squashfs-tools-mksquashfs is not set\n# CONFIG_PACKAGE_squashfs-tools-unsquashfs is not set\n# CONFIG_PACKAGE_swap-utils is not set\n# CONFIG_PACKAGE_sysfsutils is not set\n# CONFIG_PACKAGE_tune2fs is not set\n# CONFIG_PACKAGE_xfs-admin is not set\n# CONFIG_PACKAGE_xfs-fsck is not set\n# CONFIG_PACKAGE_xfs-growfs is not set\n# CONFIG_PACKAGE_xfs-mkfs is not set\n# end of Filesystem\n\n#\n# Image Manipulation\n#\n# CONFIG_PACKAGE_libjpeg-turbo-utils is not set\n# CONFIG_PACKAGE_tiff-utils is not set\n# end of Image Manipulation\n\n#\n# Microcontroller programming\n#\n# CONFIG_PACKAGE_avrdude is not set\n# CONFIG_PACKAGE_dfu-programmer is not set\n# CONFIG_PACKAGE_stm32flash is not set\n# end of Microcontroller programming\n\n#\n# RTKLIB Suite\n#\n# CONFIG_PACKAGE_convbin is not set\n# CONFIG_PACKAGE_pos2kml is not set\n# CONFIG_PACKAGE_rnx2rtkp is not set\n# CONFIG_PACKAGE_rtkrcv is not set\n# CONFIG_PACKAGE_str2str is not set\n# end of RTKLIB Suite\n\n#\n# Shells\n#\n# CONFIG_PACKAGE_bash is not set\n# CONFIG_PACKAGE_fish is not set\n# CONFIG_PACKAGE_klish is not set\n# CONFIG_PACKAGE_mksh is not set\n# CONFIG_PACKAGE_tcsh is not set\n# CONFIG_PACKAGE_zsh is not set\n# end of Shells\n\n#\n# Telephony\n#\n# CONFIG_PACKAGE_dahdi-cfg is not set\n# CONFIG_PACKAGE_dahdi-monitor is not set\n# CONFIG_PACKAGE_gsm-utils is not set\n# CONFIG_PACKAGE_sipgrep is not set\n# CONFIG_PACKAGE_sngrep is not set\n# end of Telephony\n\n#\n# Terminal\n#\n# CONFIG_PACKAGE_agetty is not set\n# CONFIG_PACKAGE_dvtm is not set\n# CONFIG_PACKAGE_minicom is not set\n# CONFIG_PACKAGE_picocom is not set\n# CONFIG_PACKAGE_rtty-mbedtls is not set\n# CONFIG_PACKAGE_rtty-nossl is not set\n# CONFIG_PACKAGE_rtty-openssl is not set\n# CONFIG_PACKAGE_rtty-wolfssl is not set\n# CONFIG_PACKAGE_screen is not set\n# CONFIG_PACKAGE_script-utils is not set\n# CONFIG_PACKAGE_serialconsole is not set\n# CONFIG_PACKAGE_setterm is not set\n# CONFIG_PACKAGE_tio is not set\n# CONFIG_PACKAGE_tmux is not set\nCONFIG_PACKAGE_ttyd=y\n# CONFIG_PACKAGE_wall is not set\n# end of Terminal\n\n#\n# Virtualization\n#\n# end of Virtualization\n\n#\n# Zoneinfo\n#\n# CONFIG_PACKAGE_zoneinfo-africa is not set\n# CONFIG_PACKAGE_zoneinfo-all is not set\n# CONFIG_PACKAGE_zoneinfo-asia is not set\n# CONFIG_PACKAGE_zoneinfo-atlantic is not set\n# CONFIG_PACKAGE_zoneinfo-australia-nz is not set\n# CONFIG_PACKAGE_zoneinfo-core is not set\n# CONFIG_PACKAGE_zoneinfo-europe is not set\n# CONFIG_PACKAGE_zoneinfo-india is not set\n# CONFIG_PACKAGE_zoneinfo-northamerica is not set\n# CONFIG_PACKAGE_zoneinfo-pacific is not set\n# CONFIG_PACKAGE_zoneinfo-poles is not set\n# CONFIG_PACKAGE_zoneinfo-simple is not set\n# CONFIG_PACKAGE_zoneinfo-southamerica is not set\n# end of Zoneinfo\n\n#\n# libimobiledevice\n#\n# CONFIG_PACKAGE_idevicerestore is not set\n# CONFIG_PACKAGE_irecovery is not set\n# CONFIG_PACKAGE_libimobiledevice-utils is not set\n# CONFIG_PACKAGE_libusbmuxd-utils is not set\n# CONFIG_PACKAGE_plistutil is not set\n# CONFIG_PACKAGE_usbmuxd is not set\n# end of libimobiledevice\n\n#\n# libselinux tools\n#\n# CONFIG_PACKAGE_libselinux-avcstat is not set\n# CONFIG_PACKAGE_libselinux-compute_av is not set\n# CONFIG_PACKAGE_libselinux-compute_create is not set\n# CONFIG_PACKAGE_libselinux-compute_member is not set\n# CONFIG_PACKAGE_libselinux-compute_relabel is not set\n# CONFIG_PACKAGE_libselinux-getconlist is not set\n# CONFIG_PACKAGE_libselinux-getdefaultcon is not set\n# CONFIG_PACKAGE_libselinux-getenforce is not set\n# CONFIG_PACKAGE_libselinux-getfilecon is not set\n# CONFIG_PACKAGE_libselinux-getpidcon is not set\n# CONFIG_PACKAGE_libselinux-getsebool is not set\n# CONFIG_PACKAGE_libselinux-getseuser is not set\n# CONFIG_PACKAGE_libselinux-matchpathcon is not set\n# CONFIG_PACKAGE_libselinux-policyvers is not set\n# CONFIG_PACKAGE_libselinux-sefcontext_compile is not set\n# CONFIG_PACKAGE_libselinux-selabel_digest is not set\n# CONFIG_PACKAGE_libselinux-selabel_get_digests_all_partial_matches is not set\n# CONFIG_PACKAGE_libselinux-selabel_lookup is not set\n# CONFIG_PACKAGE_libselinux-selabel_lookup_best_match is not set\n# CONFIG_PACKAGE_libselinux-selabel_partial_match is not set\n# CONFIG_PACKAGE_libselinux-selinux_check_access is not set\n# CONFIG_PACKAGE_libselinux-selinux_check_securetty_context is not set\n# CONFIG_PACKAGE_libselinux-selinuxenabled is not set\n# CONFIG_PACKAGE_libselinux-selinuxexeccon is not set\n# CONFIG_PACKAGE_libselinux-setenforce is not set\n# CONFIG_PACKAGE_libselinux-setfilecon is not set\n# CONFIG_PACKAGE_libselinux-togglesebool is not set\n# CONFIG_PACKAGE_libselinux-validatetrans is not set\n# end of libselinux tools\n\n# CONFIG_PACKAGE_ack is not set\n# CONFIG_PACKAGE_acpid is not set\n# CONFIG_PACKAGE_adb is not set\n# CONFIG_PACKAGE_airos-dfs-reset is not set\n# CONFIG_PACKAGE_ap51-flash is not set\n# CONFIG_PACKAGE_apk is not set\n# CONFIG_PACKAGE_at is not set\n# CONFIG_PACKAGE_atheepmgr is not set\n# CONFIG_PACKAGE_audit is not set\n# CONFIG_PACKAGE_audit-utils is not set\n# CONFIG_PACKAGE_augeas is not set\n# CONFIG_PACKAGE_augeas-lenses is not set\n# CONFIG_PACKAGE_augeas-lenses-tests is not set\n# CONFIG_PACKAGE_bandwidthd is not set\n# CONFIG_PACKAGE_bandwidthd-pgsql is not set\n# CONFIG_PACKAGE_bandwidthd-php is not set\n# CONFIG_PACKAGE_bandwidthd-sqlite is not set\n# CONFIG_PACKAGE_banhostlist is not set\n# CONFIG_PACKAGE_bc is not set\n# CONFIG_PACKAGE_bluelog is not set\n# CONFIG_PACKAGE_bluez-daemon is not set\n# CONFIG_PACKAGE_bluez-utils is not set\n# CONFIG_PACKAGE_bluez-utils-extra is not set\n# CONFIG_PACKAGE_bluld is not set\n# CONFIG_PACKAGE_bonniexx is not set\n# CONFIG_PACKAGE_bossa is not set\n# CONFIG_PACKAGE_bottlerocket is not set\n# CONFIG_PACKAGE_bsdiff is not set\n# CONFIG_PACKAGE_bspatch is not set\n# CONFIG_PACKAGE_byobu is not set\n# CONFIG_PACKAGE_byobu-utils is not set\n# CONFIG_PACKAGE_cache-domains-mbedtls is not set\n# CONFIG_PACKAGE_cache-domains-openssl is not set\n# CONFIG_PACKAGE_cache-domains-wolfssl is not set\n# CONFIG_PACKAGE_cal is not set\n# CONFIG_PACKAGE_canutils is not set\n# CONFIG_PACKAGE_cgroup-tools is not set\n# CONFIG_PACKAGE_cgroupfs-mount is not set\n# CONFIG_PACKAGE_checkpolicy is not set\n# CONFIG_PACKAGE_checksec is not set\n# CONFIG_PACKAGE_checksec_automator is not set\n# CONFIG_PACKAGE_chkcon is not set\n# CONFIG_PACKAGE_clocate is not set\n# CONFIG_PACKAGE_cmdpad is not set\n# CONFIG_PACKAGE_cni is not set\n# CONFIG_PACKAGE_cni-plugins is not set\n# CONFIG_PACKAGE_cni-plugins-nft is not set\n# CONFIG_PACKAGE_coap-client is not set\nCONFIG_PACKAGE_collectd=y\n# CONFIG_PACKAGE_COLLECTD_ENCRYPTED_NETWORK is not set\n# CONFIG_PACKAGE_COLLECTD_DEBUG_OUTPUT_ENABLE is not set\n# CONFIG_PACKAGE_collectd-mod-apache is not set\n# CONFIG_PACKAGE_collectd-mod-apcups is not set\n# CONFIG_PACKAGE_collectd-mod-ascent is not set\n# CONFIG_PACKAGE_collectd-mod-bind is not set\n# CONFIG_PACKAGE_collectd-mod-chrony is not set\n# CONFIG_PACKAGE_collectd-mod-conntrack is not set\n# CONFIG_PACKAGE_collectd-mod-contextswitch is not set\nCONFIG_PACKAGE_collectd-mod-cpu=y\n# CONFIG_PACKAGE_collectd-mod-cpufreq is not set\n# CONFIG_PACKAGE_collectd-mod-csv is not set\n# CONFIG_PACKAGE_collectd-mod-curl is not set\n# CONFIG_PACKAGE_collectd-mod-df is not set\n# CONFIG_PACKAGE_collectd-mod-dhcpleases is not set\n# CONFIG_PACKAGE_collectd-mod-disk is not set\n# CONFIG_PACKAGE_collectd-mod-dns is not set\n# CONFIG_PACKAGE_collectd-mod-email is not set\n# CONFIG_PACKAGE_collectd-mod-entropy is not set\n# CONFIG_PACKAGE_collectd-mod-ethstat is not set\n# CONFIG_PACKAGE_collectd-mod-exec is not set\n# CONFIG_PACKAGE_collectd-mod-filecount is not set\n# CONFIG_PACKAGE_collectd-mod-fscache is not set\nCONFIG_PACKAGE_collectd-mod-interface=y\n# CONFIG_PACKAGE_collectd-mod-ipstatistics is not set\n# CONFIG_PACKAGE_collectd-mod-iptables is not set\n# CONFIG_PACKAGE_collectd-mod-irq is not set\nCONFIG_PACKAGE_collectd-mod-iwinfo=y\nCONFIG_PACKAGE_collectd-mod-load=y\n# CONFIG_PACKAGE_collectd-mod-logfile is not set\n# CONFIG_PACKAGE_collectd-mod-lua is not set\n# CONFIG_PACKAGE_collectd-mod-match-empty-counter is not set\n# CONFIG_PACKAGE_collectd-mod-match-hashed is not set\n# CONFIG_PACKAGE_collectd-mod-match-regex is not set\n# CONFIG_PACKAGE_collectd-mod-match-timediff is not set\n# CONFIG_PACKAGE_collectd-mod-match-value is not set\nCONFIG_PACKAGE_collectd-mod-memory=y\n# CONFIG_PACKAGE_collectd-mod-modbus is not set\n# CONFIG_PACKAGE_collectd-mod-mqtt is not set\n# CONFIG_PACKAGE_collectd-mod-mysql is not set\n# CONFIG_PACKAGE_collectd-mod-netlink is not set\nCONFIG_PACKAGE_collectd-mod-network=y\n# CONFIG_PACKAGE_collectd-mod-nginx is not set\n# CONFIG_PACKAGE_collectd-mod-ntpd is not set\n# CONFIG_PACKAGE_collectd-mod-olsrd is not set\n# CONFIG_PACKAGE_collectd-mod-openvpn is not set\n# CONFIG_PACKAGE_collectd-mod-ping is not set\n# CONFIG_PACKAGE_collectd-mod-postgresql is not set\n# CONFIG_PACKAGE_collectd-mod-powerdns is not set\n# CONFIG_PACKAGE_collectd-mod-processes is not set\n# CONFIG_PACKAGE_collectd-mod-protocols is not set\n# CONFIG_PACKAGE_collectd-mod-routeros is not set\nCONFIG_PACKAGE_collectd-mod-rrdtool=y\n# CONFIG_PACKAGE_collectd-mod-sensors is not set\n# CONFIG_PACKAGE_collectd-mod-smart is not set\n# CONFIG_PACKAGE_collectd-mod-snmp is not set\n# CONFIG_PACKAGE_collectd-mod-snmp6 is not set\n# CONFIG_PACKAGE_collectd-mod-sqm is not set\n# CONFIG_PACKAGE_collectd-mod-swap is not set\n# CONFIG_PACKAGE_collectd-mod-syslog is not set\n# CONFIG_PACKAGE_collectd-mod-table is not set\n# CONFIG_PACKAGE_collectd-mod-tail is not set\n# CONFIG_PACKAGE_collectd-mod-tail-csv is not set\n# CONFIG_PACKAGE_collectd-mod-tcpconns is not set\n# CONFIG_PACKAGE_collectd-mod-teamspeak2 is not set\n# CONFIG_PACKAGE_collectd-mod-ted is not set\n# CONFIG_PACKAGE_collectd-mod-thermal is not set\n# CONFIG_PACKAGE_collectd-mod-threshold is not set\n# CONFIG_PACKAGE_collectd-mod-unixsock is not set\n# CONFIG_PACKAGE_collectd-mod-uptime is not set\n# CONFIG_PACKAGE_collectd-mod-users is not set\n# CONFIG_PACKAGE_collectd-mod-vmem is not set\n# CONFIG_PACKAGE_collectd-mod-wireless is not set\n# CONFIG_PACKAGE_collectd-mod-write-graphite is not set\n# CONFIG_PACKAGE_collectd-mod-write-http is not set\n# CONFIG_PACKAGE_conmon is not set\nCONFIG_PACKAGE_containerd=y\n# CONFIG_PACKAGE_coremark is not set\nCONFIG_PACKAGE_coreutils=y\n# CONFIG_PACKAGE_coreutils-b2sum is not set\n# CONFIG_PACKAGE_coreutils-base32 is not set\n# CONFIG_PACKAGE_coreutils-base64 is not set\n# CONFIG_PACKAGE_coreutils-basename is not set\n# CONFIG_PACKAGE_coreutils-basenc is not set\n# CONFIG_PACKAGE_coreutils-cat is not set\n# CONFIG_PACKAGE_coreutils-chcon is not set\n# CONFIG_PACKAGE_coreutils-chgrp is not set\n# CONFIG_PACKAGE_coreutils-chmod is not set\n# CONFIG_PACKAGE_coreutils-chown is not set\n# CONFIG_PACKAGE_coreutils-chroot is not set\n# CONFIG_PACKAGE_coreutils-cksum is not set\n# CONFIG_PACKAGE_coreutils-comm is not set\n# CONFIG_PACKAGE_coreutils-cp is not set\n# CONFIG_PACKAGE_coreutils-csplit is not set\n# CONFIG_PACKAGE_coreutils-cut is not set\n# CONFIG_PACKAGE_coreutils-date is not set\n# CONFIG_PACKAGE_coreutils-dd is not set\n# CONFIG_PACKAGE_coreutils-df is not set\n# CONFIG_PACKAGE_coreutils-dir is not set\n# CONFIG_PACKAGE_coreutils-dircolors is not set\n# CONFIG_PACKAGE_coreutils-dirname is not set\n# CONFIG_PACKAGE_coreutils-du is not set\n# CONFIG_PACKAGE_coreutils-echo is not set\n# CONFIG_PACKAGE_coreutils-env is not set\n# CONFIG_PACKAGE_coreutils-expand is not set\n# CONFIG_PACKAGE_coreutils-expr is not set\n# CONFIG_PACKAGE_coreutils-factor is not set\n# CONFIG_PACKAGE_coreutils-false is not set\n# CONFIG_PACKAGE_coreutils-fmt is not set\n# CONFIG_PACKAGE_coreutils-fold is not set\n# CONFIG_PACKAGE_coreutils-groups is not set\n# CONFIG_PACKAGE_coreutils-head is not set\n# CONFIG_PACKAGE_coreutils-hostid is not set\n# CONFIG_PACKAGE_coreutils-id is not set\n# CONFIG_PACKAGE_coreutils-install is not set\n# CONFIG_PACKAGE_coreutils-join is not set\n# CONFIG_PACKAGE_coreutils-kill is not set\n# CONFIG_PACKAGE_coreutils-link is not set\n# CONFIG_PACKAGE_coreutils-ln is not set\n# CONFIG_PACKAGE_coreutils-logname is not set\n# CONFIG_PACKAGE_coreutils-ls is not set\n# CONFIG_PACKAGE_coreutils-md5sum is not set\n# CONFIG_PACKAGE_coreutils-mkdir is not set\n# CONFIG_PACKAGE_coreutils-mkfifo is not set\n# CONFIG_PACKAGE_coreutils-mknod is not set\n# CONFIG_PACKAGE_coreutils-mktemp is not set\n# CONFIG_PACKAGE_coreutils-mv is not set\n# CONFIG_PACKAGE_coreutils-nice is not set\n# CONFIG_PACKAGE_coreutils-nl is not set\n# CONFIG_PACKAGE_coreutils-nohup is not set\n# CONFIG_PACKAGE_coreutils-nproc is not set\n# CONFIG_PACKAGE_coreutils-numfmt is not set\n# CONFIG_PACKAGE_coreutils-od is not set\n# CONFIG_PACKAGE_coreutils-paste is not set\n# CONFIG_PACKAGE_coreutils-pathchk is not set\n# CONFIG_PACKAGE_coreutils-pinky is not set\n# CONFIG_PACKAGE_coreutils-pr is not set\n# CONFIG_PACKAGE_coreutils-printenv is not set\n# CONFIG_PACKAGE_coreutils-printf is not set\n# CONFIG_PACKAGE_coreutils-ptx is not set\n# CONFIG_PACKAGE_coreutils-pwd is not set\n# CONFIG_PACKAGE_coreutils-readlink is not set\n# CONFIG_PACKAGE_coreutils-realpath is not set\n# CONFIG_PACKAGE_coreutils-rm is not set\n# CONFIG_PACKAGE_coreutils-rmdir is not set\n# CONFIG_PACKAGE_coreutils-runcon is not set\n# CONFIG_PACKAGE_coreutils-seq is not set\n# CONFIG_PACKAGE_coreutils-sha1sum is not set\n# CONFIG_PACKAGE_coreutils-sha224sum is not set\n# CONFIG_PACKAGE_coreutils-sha256sum is not set\n# CONFIG_PACKAGE_coreutils-sha384sum is not set\n# CONFIG_PACKAGE_coreutils-sha512sum is not set\n# CONFIG_PACKAGE_coreutils-shred is not set\n# CONFIG_PACKAGE_coreutils-shuf is not set\n# CONFIG_PACKAGE_coreutils-sleep is not set\nCONFIG_PACKAGE_coreutils-sort=y\n# CONFIG_PACKAGE_coreutils-split is not set\n# CONFIG_PACKAGE_coreutils-stat is not set\n# CONFIG_PACKAGE_coreutils-stdbuf is not set\n# CONFIG_PACKAGE_coreutils-stty is not set\n# CONFIG_PACKAGE_coreutils-sum is not set\n# CONFIG_PACKAGE_coreutils-sync is not set\n# CONFIG_PACKAGE_coreutils-tac is not set\n# CONFIG_PACKAGE_coreutils-tail is not set\n# CONFIG_PACKAGE_coreutils-tee is not set\n# CONFIG_PACKAGE_coreutils-test is not set\n# CONFIG_PACKAGE_coreutils-timeout is not set\n# CONFIG_PACKAGE_coreutils-touch is not set\n# CONFIG_PACKAGE_coreutils-tr is not set\n# CONFIG_PACKAGE_coreutils-true is not set\n# CONFIG_PACKAGE_coreutils-truncate is not set\n# CONFIG_PACKAGE_coreutils-tsort is not set\n# CONFIG_PACKAGE_coreutils-tty is not set\n# CONFIG_PACKAGE_coreutils-uname is not set\n# CONFIG_PACKAGE_coreutils-unexpand is not set\n# CONFIG_PACKAGE_coreutils-uniq is not set\n# CONFIG_PACKAGE_coreutils-unlink is not set\n# CONFIG_PACKAGE_coreutils-uptime is not set\n# CONFIG_PACKAGE_coreutils-users is not set\n# CONFIG_PACKAGE_coreutils-vdir is not set\n# CONFIG_PACKAGE_coreutils-wc is not set\n# CONFIG_PACKAGE_coreutils-who is not set\n# CONFIG_PACKAGE_coreutils-whoami is not set\n# CONFIG_PACKAGE_coreutils-yes is not set\n# CONFIG_PACKAGE_crconf is not set\n# CONFIG_PACKAGE_crelay is not set\n# CONFIG_PACKAGE_crun is not set\n# CONFIG_PACKAGE_csstidy is not set\n# CONFIG_PACKAGE_ct-bugcheck is not set\n# CONFIG_PACKAGE_ctop is not set\nCONFIG_PACKAGE_dbus=y\n# CONFIG_PACKAGE_dbus-utils is not set\n# CONFIG_PACKAGE_device-observatory is not set\n# CONFIG_PACKAGE_dfu-util is not set\n# CONFIG_PACKAGE_digitemp is not set\n# CONFIG_PACKAGE_digitemp-usb is not set\nCONFIG_PACKAGE_dmesg=y\nCONFIG_PACKAGE_docker=y\n# CONFIG_PACKAGE_docker-compose is not set\nCONFIG_PACKAGE_dockerd=y\n# CONFIG_DOCKER_CGROUP_OPTIONS is not set\n# CONFIG_DOCKER_OPTIONAL_FEATURES is not set\n\n#\n# Network\n#\n# CONFIG_DOCKER_NET_OVERLAY is not set\n# CONFIG_DOCKER_NET_MACVLAN is not set\n# CONFIG_DOCKER_NET_TFTP is not set\n# end of Network\n\n#\n# Storage\n#\n# CONFIG_DOCKER_STO_EXT4 is not set\n# CONFIG_DOCKER_STO_BTRFS is not set\n# end of Storage\n\n# CONFIG_PACKAGE_domoticz is not set\n# CONFIG_PACKAGE_dropbearconvert is not set\n# CONFIG_PACKAGE_dtc is not set\n# CONFIG_PACKAGE_dumb-init is not set\n# CONFIG_PACKAGE_dump1090 is not set\n# CONFIG_PACKAGE_ecdsautils is not set\n# CONFIG_PACKAGE_elektra-kdb is not set\n# CONFIG_PACKAGE_evtest is not set\n# CONFIG_PACKAGE_extract is not set\n# CONFIG_PACKAGE_fbtest is not set\n# CONFIG_PACKAGE_fdt-utils is not set\n# CONFIG_PACKAGE_file is not set\n# CONFIG_PACKAGE_findutils is not set\n# CONFIG_PACKAGE_findutils-find is not set\n# CONFIG_PACKAGE_findutils-locate is not set\n# CONFIG_PACKAGE_findutils-xargs is not set\n# CONFIG_PACKAGE_flashrom is not set\n# CONFIG_PACKAGE_flashrom-pci is not set\n# CONFIG_PACKAGE_flashrom-spi is not set\n# CONFIG_PACKAGE_flashrom-usb is not set\n# CONFIG_PACKAGE_flent-tools is not set\n# CONFIG_PACKAGE_flock is not set\n# CONFIG_PACKAGE_fritz-caldata is not set\n# CONFIG_PACKAGE_fritz-tffs is not set\n# CONFIG_PACKAGE_fritz-tffs-nand is not set\n# CONFIG_PACKAGE_ftdi_eeprom is not set\n# CONFIG_PACKAGE_fuse-overlayfs is not set\n# CONFIG_PACKAGE_gammu is not set\n# CONFIG_PACKAGE_gawk is not set\n# CONFIG_PACKAGE_gddrescue is not set\n# CONFIG_PACKAGE_getopt is not set\n# CONFIG_PACKAGE_giflib-utils is not set\n# CONFIG_PACKAGE_gkermit is not set\n# CONFIG_PACKAGE_gl-puli-mcu is not set\n# CONFIG_PACKAGE_gnuplot is not set\n# CONFIG_PACKAGE_gpioctl-sysfs is not set\n# CONFIG_PACKAGE_gpiod-tools is not set\n# CONFIG_PACKAGE_gpsd is not set\n# CONFIG_PACKAGE_gpsd-clients is not set\n# CONFIG_PACKAGE_gpsd-utils is not set\n# CONFIG_PACKAGE_grep is not set\n# CONFIG_PACKAGE_hamlib is not set\n# CONFIG_PACKAGE_haserl is not set\n# CONFIG_PACKAGE_hashdeep is not set\n# CONFIG_PACKAGE_haveged is not set\n# CONFIG_PACKAGE_hplip-common is not set\n# CONFIG_PACKAGE_hplip-sane is not set\n# CONFIG_PACKAGE_hub-ctrl is not set\n# CONFIG_PACKAGE_hwclock is not set\n# CONFIG_PACKAGE_hwinfo is not set\n# CONFIG_PACKAGE_hwloc-utils is not set\n# CONFIG_PACKAGE_i2c-tools is not set\n# CONFIG_PACKAGE_iconv is not set\n# CONFIG_PACKAGE_iio-utils is not set\n# CONFIG_PACKAGE_inotifywait is not set\n# CONFIG_PACKAGE_inotifywatch is not set\n# CONFIG_PACKAGE_io is not set\n# CONFIG_PACKAGE_ipfs-http-client-tests is not set\n# CONFIG_PACKAGE_irqbalance is not set\n# CONFIG_PACKAGE_iwcap is not set\nCONFIG_PACKAGE_iwinfo=y\n# CONFIG_PACKAGE_jq is not set\nCONFIG_PACKAGE_jshn=y\n# CONFIG_PACKAGE_kmod is not set\n# CONFIG_PACKAGE_lcd4linux-custom is not set\n# CONFIG_PACKAGE_lcdproc-clients is not set\n# CONFIG_PACKAGE_lcdproc-drivers is not set\n# CONFIG_PACKAGE_lcdproc-server is not set\n# CONFIG_PACKAGE_less is not set\nCONFIG_PACKAGE_libjson-script=y\nCONFIG_PACKAGE_libnetwork=y\n# CONFIG_PACKAGE_libucode is not set\n# CONFIG_PACKAGE_libxml2-utils is not set\n# CONFIG_PACKAGE_lm-sensors is not set\n# CONFIG_PACKAGE_lm-sensors-detect is not set\n# CONFIG_PACKAGE_logger is not set\n# CONFIG_PACKAGE_logrotate is not set\n# CONFIG_PACKAGE_lolcat is not set\n# CONFIG_PACKAGE_look is not set\n# CONFIG_PACKAGE_losetup is not set\n# CONFIG_PACKAGE_lrzsz is not set\n# CONFIG_PACKAGE_lscpu is not set\n# CONFIG_PACKAGE_lsof is not set\n# CONFIG_PACKAGE_lxc is not set\n# CONFIG_PACKAGE_maccalc is not set\n# CONFIG_PACKAGE_macchanger is not set\n# CONFIG_PACKAGE_mandoc is not set\n# CONFIG_PACKAGE_mbedtls-util is not set\n# CONFIG_PACKAGE_mbim-utils is not set\n# CONFIG_PACKAGE_mbtools is not set\n# CONFIG_PACKAGE_mc is not set\n# CONFIG_PACKAGE_mc-skins is not set\n# CONFIG_PACKAGE_mcookie is not set\n# CONFIG_PACKAGE_mdio-tools is not set\n# CONFIG_PACKAGE_micrond is not set\n# CONFIG_PACKAGE_miniflux is not set\n# CONFIG_PACKAGE_mmc-utils is not set\n# CONFIG_PACKAGE_more is not set\n# CONFIG_PACKAGE_moreutils is not set\n# CONFIG_PACKAGE_mosh-client is not set\n# CONFIG_PACKAGE_mosh-server is not set\nCONFIG_PACKAGE_mount-utils=y\n# CONFIG_PACKAGE_mpack is not set\n# CONFIG_PACKAGE_mt-st is not set\n# CONFIG_PACKAGE_namei is not set\n# CONFIG_PACKAGE_naywatch is not set\n# CONFIG_PACKAGE_netopeer2-cli is not set\n# CONFIG_PACKAGE_netopeer2-server is not set\n# CONFIG_PACKAGE_netwhere is not set\n# CONFIG_PACKAGE_nnn is not set\n# CONFIG_PACKAGE_nsenter is not set\n# CONFIG_PACKAGE_nss-utils is not set\n# CONFIG_PACKAGE_oath-toolkit is not set\n# CONFIG_PACKAGE_oci-runtime-tool is not set\n# CONFIG_PACKAGE_open-plc-utils is not set\n# CONFIG_PACKAGE_open2300 is not set\n# CONFIG_PACKAGE_openobex is not set\n# CONFIG_PACKAGE_openobex-apps is not set\n# CONFIG_PACKAGE_openocd is not set\n# CONFIG_PACKAGE_opensc-utils is not set\nCONFIG_PACKAGE_openssl-util=y\n# CONFIG_PACKAGE_openzwave is not set\n# CONFIG_PACKAGE_openzwave-config is not set\n# CONFIG_PACKAGE_owipcalc is not set\n# CONFIG_PACKAGE_pciids is not set\n# CONFIG_PACKAGE_pciutils is not set\n# CONFIG_PACKAGE_pcsc-tools is not set\n# CONFIG_PACKAGE_pcscd is not set\n# CONFIG_PACKAGE_podman is not set\n# CONFIG_PACKAGE_podman-selinux is not set\n# CONFIG_PACKAGE_policycoreutils is not set\n# CONFIG_PACKAGE_powertop is not set\n# CONFIG_PACKAGE_pps-tools is not set\n# CONFIG_PACKAGE_prlimit is not set\n# CONFIG_PACKAGE_procps-ng is not set\n# CONFIG_PACKAGE_progress is not set\n# CONFIG_PACKAGE_prometheus is not set\n# CONFIG_PACKAGE_prometheus-node-exporter-lua is not set\n# CONFIG_PACKAGE_prometheus-statsd-exporter is not set\n# CONFIG_PACKAGE_pservice is not set\n# CONFIG_PACKAGE_psmisc is not set\n# CONFIG_PACKAGE_pv is not set\n# CONFIG_PACKAGE_qmi-utils is not set\n# CONFIG_PACKAGE_qrencode is not set\n# CONFIG_PACKAGE_quota is not set\n# CONFIG_PACKAGE_ravpower-mcu is not set\n# CONFIG_PACKAGE_readsb is not set\n# CONFIG_PACKAGE_relayctl is not set\n# CONFIG_PACKAGE_rename is not set\n# CONFIG_PACKAGE_reptyr is not set\n# CONFIG_PACKAGE_restic is not set\n# CONFIG_PACKAGE_rng-tools is not set\n# CONFIG_PACKAGE_rtl-ais is not set\n# CONFIG_PACKAGE_rtl-sdr is not set\n# CONFIG_PACKAGE_rtl_433 is not set\nCONFIG_PACKAGE_runc=y\n# CONFIG_PACKAGE_sane-backends is not set\n# CONFIG_PACKAGE_sane-daemon is not set\n# CONFIG_PACKAGE_sane-frontends is not set\n# CONFIG_PACKAGE_secilc is not set\n# CONFIG_PACKAGE_sed is not set\n# CONFIG_PACKAGE_selinux-audit2allow is not set\n# CONFIG_PACKAGE_selinux-chcat is not set\n# CONFIG_PACKAGE_selinux-semanage is not set\n# CONFIG_PACKAGE_semodule-utils is not set\n# CONFIG_PACKAGE_serdisplib-tools is not set\n# CONFIG_PACKAGE_setools is not set\n# CONFIG_PACKAGE_setserial is not set\n# CONFIG_PACKAGE_shadow-utils is not set\n# CONFIG_PACKAGE_sipcalc is not set\n# CONFIG_PACKAGE_sispmctl is not set\n# CONFIG_PACKAGE_slide-switch is not set\n# CONFIG_PACKAGE_smartd is not set\n# CONFIG_PACKAGE_smartd-mail is not set\n# CONFIG_PACKAGE_smartmontools is not set\n# CONFIG_PACKAGE_smartmontools-drivedb is not set\n# CONFIG_PACKAGE_smstools3 is not set\n# CONFIG_PACKAGE_sockread is not set\n# CONFIG_PACKAGE_spi-tools is not set\n# CONFIG_PACKAGE_spidev-test is not set\n# CONFIG_PACKAGE_ssdeep is not set\n# CONFIG_PACKAGE_sshpass is not set\n# CONFIG_PACKAGE_strace is not set\nCONFIG_STRACE_NONE=y\n# CONFIG_STRACE_LIBDW is not set\n# CONFIG_STRACE_LIBUNWIND is not set\n# CONFIG_PACKAGE_stress is not set\n# CONFIG_PACKAGE_stress-ng is not set\n# CONFIG_PACKAGE_sumo is not set\n# CONFIG_PACKAGE_syncthing is not set\n# CONFIG_PACKAGE_sysrepo is not set\n# CONFIG_PACKAGE_sysrepocfg is not set\n# CONFIG_PACKAGE_sysrepoctl is not set\n# CONFIG_PACKAGE_sysstat is not set\n# CONFIG_PACKAGE_tar is not set\n# CONFIG_PACKAGE_taskwarrior is not set\n# CONFIG_PACKAGE_telegraf is not set\n# CONFIG_PACKAGE_telegraf-full is not set\n# CONFIG_PACKAGE_telldus-core is not set\n# CONFIG_PACKAGE_temperusb is not set\n# CONFIG_PACKAGE_tesseract is not set\nCONFIG_PACKAGE_tini=y\n# CONFIG_PACKAGE_tracertools is not set\n# CONFIG_PACKAGE_tree is not set\n# CONFIG_PACKAGE_triggerhappy is not set\n# CONFIG_PACKAGE_ucode is not set\n# CONFIG_PACKAGE_udns-dnsget is not set\n# CONFIG_PACKAGE_udns-ex-rdns is not set\n# CONFIG_PACKAGE_udns-rblcheck is not set\n# CONFIG_PACKAGE_ugps is not set\n# CONFIG_PACKAGE_uhubctl is not set\n# CONFIG_PACKAGE_uledd is not set\n# CONFIG_PACKAGE_unshare is not set\n# CONFIG_PACKAGE_usb-modeswitch is not set\n# CONFIG_PACKAGE_usbids is not set\n# CONFIG_PACKAGE_usbutils is not set\n# CONFIG_PACKAGE_uuidd is not set\n# CONFIG_PACKAGE_uuidgen is not set\n# CONFIG_PACKAGE_uvcdynctrl is not set\n# CONFIG_PACKAGE_v4l-utils is not set\n# CONFIG_PACKAGE_view1090 is not set\n# CONFIG_PACKAGE_viewadsb is not set\nCONFIG_PACKAGE_watchcat=y\n# CONFIG_PACKAGE_whereis is not set\n# CONFIG_PACKAGE_which is not set\n# CONFIG_PACKAGE_whiptail is not set\n# CONFIG_PACKAGE_whois is not set\n# CONFIG_PACKAGE_wifitoggle is not set\n# CONFIG_PACKAGE_wipe is not set\n# CONFIG_PACKAGE_xsltproc is not set\n# CONFIG_PACKAGE_xxd is not set\n# CONFIG_PACKAGE_yanglint is not set\n# CONFIG_PACKAGE_yara is not set\n# CONFIG_PACKAGE_ykclient is not set\n# CONFIG_PACKAGE_ykpers is not set\n# CONFIG_PACKAGE_yq is not set\n# end of Utilities\n\n#\n# Xorg\n#\n\n#\n# Font-Utils\n#\n# CONFIG_PACKAGE_fontconfig is not set\n# end of Font-Utils\n# end of Xorg\n"
  },
  {
    "path": "feeds.conf.default",
    "content": "src-git-full packages https://git.openwrt.org/feed/packages.git\nsrc-git-full luci https://git.openwrt.org/project/luci.git\nsrc-git-full routing https://git.openwrt.org/feed/routing.git\nsrc-git-full telephony https://git.openwrt.org/feed/telephony.git\n#src-git-full video https://github.com/openwrt/video.git\n#src-git-full targets https://github.com/openwrt/targets.git\n#src-git-full oldpackages http://git.openwrt.org/packages.git\n#src-link custom /usr/src/openwrt/custom-feed\n"
  },
  {
    "path": "include/autotools.mk",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2007-2020 OpenWrt.org\n\nifneq ($(__autotools_inc),1)\n__autotools_inc=1\n\nautoconf_bool = $(patsubst %,$(if $($(1)),--enable,--disable)-%,$(2))\n\n# delete *.la-files from staging_dir - we can not yet remove respective lines within all package\n# Makefiles, since backfire still uses libtool v1.5.x which (may) require those files\ndefine libtool_remove_files\n\tfind $(1) -name '*.la' | $(XARGS) rm -f;\nendef\n\n\nAM_TOOL_PATHS:= \\\n\tAUTOM4TE=$(STAGING_DIR_HOST)/bin/autom4te \\\n\tAUTOCONF=$(STAGING_DIR_HOST)/bin/autoconf \\\n\tAUTOMAKE=$(STAGING_DIR_HOST)/bin/automake \\\n\tACLOCAL=$(STAGING_DIR_HOST)/bin/aclocal \\\n\tAUTOHEADER=$(STAGING_DIR_HOST)/bin/autoheader \\\n\tLIBTOOLIZE=$(STAGING_DIR_HOST)/bin/libtoolize \\\n\tLIBTOOL=$(STAGING_DIR_HOST)/bin/libtool \\\n\tM4=$(STAGING_DIR_HOST)/bin/m4 \\\n\tAUTOPOINT=true\n\n# 1: build dir\n# 2: remove files\n# 3: automake paths\n# 4: libtool paths\n# 5: extra m4 dirs\ndefine autoreconf\n\t(cd $(1); \\\n\t\t$(patsubst %,rm -f %;,$(2)) \\\n\t\t$(foreach p,$(3), \\\n\t\t\tif [ -f $(p)/configure.ac ] || [ -f $(p)/configure.in ]; then \\\n\t\t\t\t[ -d $(p)/autom4te.cache ] && rm -rf $(p)/autom4te.cache; \\\n\t\t\t\t[ -e $(p)/config.rpath ] || \\\n\t\t\t\t\t\tln -s $(SCRIPT_DIR)/config.rpath $(p)/config.rpath; \\\n\t\t\t\ttouch NEWS AUTHORS COPYING ABOUT-NLS ChangeLog; \\\n\t\t\t\t$(AM_TOOL_PATHS) \\\n\t\t\t\t\tLIBTOOLIZE='$(STAGING_DIR_HOST)/bin/libtoolize --install' \\\n\t\t\t\t\t$(STAGING_DIR_HOST)/bin/autoreconf -v -f -i -s \\\n\t\t\t\t\t$(if $(word 2,$(3)),--no-recursive) \\\n\t\t\t\t\t-B $(STAGING_DIR_HOST)/share/aclocal \\\n\t\t\t\t\t$(patsubst %,-I %,$(5)) \\\n\t\t\t\t\t$(patsubst %,-I %,$(4)) $(p) || true; \\\n\t\t\tfi; \\\n\t\t) \\\n\t);\nendef\n\n# 1: build dir\ndefine patch_libtool\n\t@(cd $(1); \\\n\t\tfor lt in $$$$($$(STAGING_DIR_HOST)/bin/find . -name ltmain.sh); do \\\n\t\t\tlt_version=\"$$$$($$(STAGING_DIR_HOST)/bin/sed -ne 's,^[[:space:]]*VERSION=\"\\?\\([0-9]\\.[0-9]\\+\\).*,\\1,p' $$$$lt)\"; \\\n\t\t\tcase \"$$$$lt_version\" in \\\n\t\t\t\t1.5|2.2|2.4) echo \"autotools.mk: Found libtool v$$$$lt_version - applying patch to $$$$lt\"; \\\n\t\t\t\t\t(cd $$$$(dirname $$$$lt) && $$(PATCH) -N -s -p1 < $$(TOPDIR)/tools/libtool/files/libtool-v$$$$lt_version.patch || true) ;; \\\n\t\t\t\t*) echo \"autotools.mk: error: Unsupported libtool version v$$$$lt_version - cannot patch $$$$lt\"; exit 1 ;; \\\n\t\t\tesac; \\\n\t\tdone; \\\n\t);\nendef\n\ndefine set_libtool_abiver\n\tsed -i \\\n\t\t-e 's,^soname_spec=.*,soname_spec=\"\\\\$$$${libname}\\\\$$$${shared_ext}.$(PKG_ABI_VERSION)\",' \\\n\t\t-e 's,^library_names_spec=.*,library_names_spec=\"\\\\$$$${libname}\\\\$$$${shared_ext}.$(PKG_ABI_VERSION) \\\\$$$${libname}\\\\$$$${shared_ext}\",' \\\n\t\t$(PKG_BUILD_DIR)/libtool\nendef\n\nPKG_LIBTOOL_PATHS?=$(CONFIGURE_PATH)\nPKG_AUTOMAKE_PATHS?=$(CONFIGURE_PATH)\nPKG_MACRO_PATHS?=m4\nPKG_REMOVE_FILES?=aclocal.m4\n\nHooks/InstallDev/Post += libtool_remove_files\n\ndefine autoreconf_target\n  $(strip $(call autoreconf, \\\n    $(PKG_BUILD_DIR), $(PKG_REMOVE_FILES), \\\n    $(PKG_AUTOMAKE_PATHS), $(PKG_LIBTOOL_PATHS), \\\n    $(STAGING_DIR)/host/share/aclocal $(STAGING_DIR_HOSTPKG)/share/aclocal $(STAGING_DIR)/usr/share/aclocal $(PKG_MACRO_PATHS)))\nendef\n\ndefine patch_libtool_target\n  $(strip $(call patch_libtool, \\\n    $(PKG_BUILD_DIR)))\nendef\n\ndefine gettext_version_target\n\t(cd $(PKG_BUILD_DIR) && \\\n\t\tGETTEXT_VERSION=$(shell $(STAGING_DIR_HOSTPKG)/bin/gettext -V | $(STAGING_DIR_HOST)/bin/sed -rne '1s/.*\\b([0-9]\\.[0-9]+(\\.[0-9]+)?)\\b.*/\\1/p' ) && \\\n\t\t$(STAGING_DIR_HOST)/bin/sed \\\n\t\t\t-i $(PKG_BUILD_DIR)/configure.ac \\\n\t\t\t-e \"s/AM_GNU_GETTEXT_VERSION(.*)/AM_GNU_GETTEXT_VERSION(\\[$$$$GETTEXT_VERSION\\])/g\" && \\\n\t\t$(STAGING_DIR_HOSTPKG)/bin/autopoint --force \\\n\t);\nendef\n\nifneq ($(filter gettext-version,$(PKG_FIXUP)),)\n  Hooks/Configure/Pre += gettext_version_target\n ifeq ($(filter no-autoreconf,$(PKG_FIXUP)),)\n  Hooks/Configure/Pre += autoreconf_target\n endif\nendif\n\nifneq ($(filter patch-libtool,$(PKG_FIXUP)),)\n  Hooks/Configure/Pre += patch_libtool_target\nendif\n\nifneq ($(filter libtool,$(PKG_FIXUP)),)\n  PKG_BUILD_DEPENDS += libtool libiconv\n ifeq ($(filter no-autoreconf,$(PKG_FIXUP)),)\n  Hooks/Configure/Pre += autoreconf_target\n endif\nendif\n\nifneq ($(filter libtool-abiver,$(PKG_FIXUP)),)\n  Hooks/Configure/Post += set_libtool_abiver\nendif\n\nifneq ($(filter libtool-ucxx,$(PKG_FIXUP)),)\n  PKG_BUILD_DEPENDS += libtool libiconv\n ifeq ($(filter no-autoreconf,$(PKG_FIXUP)),)\n  Hooks/Configure/Pre += autoreconf_target\n endif\nendif\n\nifneq ($(filter autoreconf,$(PKG_FIXUP)),)\n  ifeq ($(filter autoreconf,$(Hooks/Configure/Pre)),)\n    Hooks/Configure/Pre += autoreconf_target\n  endif\nendif\n\n\nHOST_FIXUP?=$(PKG_FIXUP)\nHOST_LIBTOOL_PATHS?=$(if $(PKG_LIBTOOL_PATHS),$(PKG_LIBTOOL_PATHS),.)\nHOST_AUTOMAKE_PATHS?=$(if $(PKG_AUTOMAKE_PATHS),$(PKG_AUTOMAKE_PATHS),.)\nHOST_MACRO_PATHS?=$(if $(PKG_MACRO_PATHS),$(PKG_MACRO_PATHS),m4)\nHOST_REMOVE_FILES?=$(PKG_REMOVE_FILES)\n\ndefine autoreconf_host\n  $(strip $(call autoreconf, \\\n    $(HOST_BUILD_DIR), $(HOST_REMOVE_FILES), \\\n    $(HOST_AUTOMAKE_PATHS), $(HOST_LIBTOOL_PATHS), \\\n    $(HOST_MACRO_PATHS)))\nendef\n\ndefine patch_libtool_host\n  $(strip $(call patch_libtool, \\\n    $(HOST_BUILD_DIR)))\nendef\n\nifneq ($(filter patch-libtool,$(HOST_FIXUP)),)\n  Hooks/HostConfigure/Pre += patch_libtool_host\nendif\n\nifneq ($(filter libtool,$(HOST_FIXUP)),)\n ifeq ($(filter no-autoreconf,$(HOST_FIXUP)),)\n  Hooks/HostConfigure/Pre += autoreconf_host\n endif\nendif\n\nifneq ($(filter libtool-ucxx,$(HOST_FIXUP)),)\n ifeq ($(filter no-autoreconf,$(HOST_FIXUP)),)\n  Hooks/HostConfigure/Pre += autoreconf_host\n endif\nendif\n\nifneq ($(filter autoreconf,$(HOST_FIXUP)),)\n  ifeq ($(filter autoreconf,$(Hooks/HostConfigure/Pre)),)\n    Hooks/HostConfigure/Pre += autoreconf_host\n  endif\nendif\n\nendif #__autotools_inc\n"
  },
  {
    "path": "include/bpf.mk",
    "content": "BPF_DEPENDS := @HAS_BPF_TOOLCHAIN\nLLVM_VER:=\n\nCLANG_MIN_VER:=12\n\nifneq ($(CONFIG_USE_LLVM_HOST),)\n  BPF_TOOLCHAIN_HOST_PATH:=$(call qstrip,$(CONFIG_BPF_TOOLCHAIN_HOST_PATH))\n  ifneq ($(BPF_TOOLCHAIN_HOST_PATH),)\n    BPF_PATH:=$(BPF_TOOLCHAIN_HOST_PATH)/bin:$(PATH)\n  else\n    BPF_PATH:=$(PATH)\n  endif\n  CLANG:=$(firstword $(shell PATH='$(BPF_PATH)' command -v clang clang-13 clang-12 clang-11))\n  LLVM_VER:=$(subst clang,,$(notdir $(CLANG)))\nendif\nifneq ($(CONFIG_USE_LLVM_PREBUILT),)\n  CLANG:=$(TOPDIR)/llvm-bpf/bin/clang\nendif\nifneq ($(CONFIG_USE_LLVM_BUILD),)\n  CLANG:=$(STAGING_DIR_HOST)/llvm-bpf/bin/clang\nendif\n\nLLVM_PATH:=$(dir $(CLANG))\nLLVM_LLC:=$(LLVM_PATH)/llc$(LLVM_VER)\nLLVM_DIS:=$(LLVM_PATH)/llvm-dis$(LLVM_VER)\nLLVM_OPT:=$(LLVM_PATH)/opt$(LLVM_VER)\nLLVM_STRIP:=$(LLVM_PATH)/llvm-strip$(LLVM_VER)\n\nBPF_KARCH:=mips\nBPF_ARCH:=mips$(if $(CONFIG_ARCH_64BIT),64)$(if $(CONFIG_BIG_ENDIAN),,el)\nBPF_TARGET:=bpf$(if $(CONFIG_BIG_ENDIAN),eb,el)\n\nBPF_HEADERS_DIR:=$(STAGING_DIR)/bpf-headers\n\nBPF_KERNEL_INCLUDE := \\\n\t-nostdinc -isystem $(TOOLCHAIN_DIR)/include \\\n\t-I$(BPF_HEADERS_DIR)/arch/$(BPF_KARCH)/include \\\n\t-I$(BPF_HEADERS_DIR)/arch/$(BPF_KARCH)/include/asm/mach-generic \\\n\t-I$(BPF_HEADERS_DIR)/arch/$(BPF_KARCH)/include/generated \\\n\t-I$(BPF_HEADERS_DIR)/include \\\n\t-I$(BPF_HEADERS_DIR)/arch/$(BPF_KARCH)/include/uapi \\\n\t-I$(BPF_HEADERS_DIR)/arch/$(BPF_KARCH)/include/generated/uapi \\\n\t-I$(BPF_HEADERS_DIR)/include/uapi \\\n\t-I$(BPF_HEADERS_DIR)/include/generated/uapi \\\n\t-I$(BPF_HEADERS_DIR)/tools/lib \\\n\t-I$(BPF_HEADERS_DIR)/tools/testing/selftests \\\n\t-I$(BPF_HEADERS_DIR)/samples/bpf \\\n\t-include linux/kconfig.h -include asm_goto_workaround.h\n\nBPF_CFLAGS := \\\n\t$(BPF_KERNEL_INCLUDE) -I$(PKG_BUILD_DIR) \\\n\t-D__KERNEL__ -D__BPF_TRACING__ -DCONFIG_GENERIC_CSUM \\\n\t-D__TARGET_ARCH_${BPF_KARCH} \\\n\t-m$(if $(CONFIG_BIG_ENDIAN),big,little)-endian \\\n\t-fno-stack-protector -Wall \\\n\t-Wno-unused-value -Wno-pointer-sign \\\n\t-Wno-compare-distinct-pointer-types \\\n\t-Wno-gnu-variable-sized-type-not-at-end \\\n\t-Wno-address-of-packed-member -Wno-tautological-compare \\\n\t-Wno-unknown-warning-option \\\n\t-fno-asynchronous-unwind-tables \\\n\t-Wno-uninitialized -Wno-unused-variable \\\n\t-Wno-unused-label \\\n\t-O2 -emit-llvm -Xclang -disable-llvm-passes\n\nifeq ($(DUMP),)\n  CLANG_VER:=$(shell $(CLANG) -dM -E - < /dev/null | grep __clang_major__ | cut -d' ' -f3)\n  CLANG_VER_VALID:=$(shell [ \"$(CLANG_VER)\" -ge \"$(CLANG_MIN_VER)\" ] && echo 1 )\n  ifeq ($(CLANG_VER_VALID),)\n    $(error ERROR: LLVM/clang version too old. Minimum required: $(CLANG_MIN_VER), found: $(CLANG_VER))\n  endif\nendif\n\ndefine CompileBPF\n\t$(CLANG) -g -target $(BPF_ARCH)-linux-gnu $(BPF_CFLAGS) $(2) \\\n\t\t-c $(1) -o $(patsubst %.c,%.bc,$(1))\n\t$(LLVM_OPT) -O2 -mtriple=$(BPF_TARGET) < $(patsubst %.c,%.bc,$(1)) > $(patsubst %.c,%.opt,$(1))\n\t$(LLVM_DIS) < $(patsubst %.c,%.opt,$(1)) > $(patsubst %.c,%.S,$(1))\n\t$(LLVM_LLC) -march=$(BPF_TARGET) -mcpu=v3 -filetype=obj -o $(patsubst %.c,%.o,$(1)) < $(patsubst %.c,%.S,$(1))\n\t$(CP) $(patsubst %.c,%.o,$(1)) $(patsubst %.c,%.debug.o,$(1))\n\t$(LLVM_STRIP) --strip-debug $(patsubst %.c,%.o,$(1))\nendef\n\n"
  },
  {
    "path": "include/cmake.mk",
    "content": "cmake_bool = $(patsubst %,-D%:BOOL=$(if $($(1)),ON,OFF),$(2))\n\nPKG_USE_NINJA ?= 1\nHOST_USE_NINJA ?= 1\nifeq ($(PKG_USE_NINJA),1)\n  PKG_BUILD_PARALLEL ?= 1\nendif\nifeq ($(HOST_USE_NINJA),1)\n  HOST_BUILD_PARALLEL ?= 1\nendif\nPKG_INSTALL:=1\n\nifneq ($(findstring c,$(OPENWRT_VERBOSE)),)\n  MAKE_FLAGS+=VERBOSE=1\n  HOST_MAKE_FLAGS+=VERBOSE=1\nendif\n\nCMAKE_BINARY_DIR = $(PKG_BUILD_DIR)$(if $(CMAKE_BINARY_SUBDIR),/$(CMAKE_BINARY_SUBDIR))\nCMAKE_SOURCE_DIR = $(PKG_BUILD_DIR)$(if $(CMAKE_SOURCE_SUBDIR),/$(CMAKE_SOURCE_SUBDIR))\nHOST_CMAKE_SOURCE_DIR = $(HOST_BUILD_DIR)$(if $(CMAKE_SOURCE_SUBDIR),/$(CMAKE_SOURCE_SUBDIR))\nHOST_CMAKE_BINARY_DIR = $(HOST_BUILD_DIR)$(if $(CMAKE_BINARY_SUBDIR),/$(CMAKE_BINARY_SUBDIR))\nMAKE_PATH = $(firstword $(CMAKE_BINARY_SUBDIR) .)\n\nifeq ($(CONFIG_EXTERNAL_TOOLCHAIN),)\n  cmake_tool=$(TOOLCHAIN_DIR)/bin/$(1)\nelse\n  cmake_tool=$(shell command -v $(1))\nendif\n\nifeq ($(CONFIG_CCACHE),)\n CMAKE_C_COMPILER_LAUNCHER:=\n CMAKE_CXX_COMPILER_LAUNCHER:=\n CMAKE_C_COMPILER:=$(call cmake_tool,$(TARGET_CC))\n CMAKE_CXX_COMPILER:=$(call cmake_tool,$(TARGET_CXX))\n\n CMAKE_HOST_C_COMPILER:=$(HOSTCC)\n CMAKE_HOST_CXX_COMPILER:=$(HOSTCXX)\nelse\n  CCACHE:=$(STAGING_DIR_HOST)/bin/ccache\n  CMAKE_C_COMPILER_LAUNCHER:=$(CCACHE)\n  CMAKE_CXX_COMPILER_LAUNCHER:=$(CCACHE)\n  CMAKE_C_COMPILER:=$(TARGET_CC_NOCACHE)\n  CMAKE_CXX_COMPILER:=$(TARGET_CXX_NOCACHE)\n\n  CMAKE_HOST_C_COMPILER:=$(HOSTCC_NOCACHE)\n  CMAKE_HOST_CXX_COMPILER:=$(HOSTCXX_NOCACHE)\nendif\nCMAKE_AR:=$(call cmake_tool,$(TARGET_AR))\nCMAKE_NM:=$(call cmake_tool,$(TARGET_NM))\nCMAKE_RANLIB:=$(call cmake_tool,$(TARGET_RANLIB))\n\nCMAKE_FIND_ROOT_PATH:=$(STAGING_DIR)/usr;$(TOOLCHAIN_DIR)$(if $(CONFIG_EXTERNAL_TOOLCHAIN),;$(CONFIG_TOOLCHAIN_ROOT))\nCMAKE_HOST_FIND_ROOT_PATH:=$(STAGING_DIR)/host;$(STAGING_DIR_HOSTPKG);$(STAGING_DIR_HOST)\nCMAKE_SHARED_LDFLAGS:=-Wl,-Bsymbolic-functions\nCMAKE_HOST_INSTALL_PREFIX = $(HOST_BUILD_PREFIX)\n\nifeq ($(HOST_USE_NINJA),1)\n  CMAKE_HOST_OPTIONS += -DCMAKE_GENERATOR=\"Ninja\"\n\n  define Host/Compile/Default\n\t+$(NINJA) -C $(HOST_CMAKE_BINARY_DIR) $(1)\n  endef\n\n  define Host/Install/Default\n\t+$(NINJA) -C $(HOST_CMAKE_BINARY_DIR) install\n  endef\n\n  define Host/Uninstall/Default\n\t+$(NINJA) -C $(HOST_CMAKE_BINARY_DIR) uninstall\n  endef\nendif\n\nifeq ($(PKG_USE_NINJA),1)\n  CMAKE_OPTIONS += -DCMAKE_GENERATOR=\"Ninja\"\n\n  define Build/Compile/Default\n\t+$(NINJA) -C $(CMAKE_BINARY_DIR) $(1)\n  endef\n\n  define Build/Install/Default\n\t+DESTDIR=\"$(PKG_INSTALL_DIR)\" $(NINJA) -C $(CMAKE_BINARY_DIR) install\n  endef\nendif\n\ndefine Build/Configure/Default\n\tmkdir -p $(CMAKE_BINARY_DIR)\n\t(cd $(CMAKE_BINARY_DIR); \\\n\t\tCFLAGS=\"$(TARGET_CFLAGS) $(EXTRA_CFLAGS)\" \\\n\t\tCXXFLAGS=\"$(TARGET_CXXFLAGS) $(EXTRA_CXXFLAGS)\" \\\n\t\tLDFLAGS=\"$(TARGET_LDFLAGS) $(EXTRA_LDFLAGS)\" \\\n\t\tcmake \\\n\t\t\t-DCMAKE_SYSTEM_NAME=Linux \\\n\t\t\t-DCMAKE_SYSTEM_VERSION=1 \\\n\t\t\t-DCMAKE_SYSTEM_PROCESSOR=$(ARCH) \\\n\t\t\t-DCMAKE_BUILD_TYPE=Release \\\n\t\t\t-DCMAKE_C_FLAGS_RELEASE=\"-DNDEBUG\" \\\n\t\t\t-DCMAKE_CXX_FLAGS_RELEASE=\"-DNDEBUG\" \\\n\t\t\t-DCMAKE_C_COMPILER_LAUNCHER=\"$(CMAKE_C_COMPILER_LAUNCHER)\" \\\n\t\t\t-DCMAKE_C_COMPILER=\"$(CMAKE_C_COMPILER)\" \\\n\t\t\t-DCMAKE_CXX_COMPILER_LAUNCHER=\"$(CMAKE_CXX_COMPILER_LAUNCHER)\" \\\n\t\t\t-DCMAKE_CXX_COMPILER=\"$(CMAKE_CXX_COMPILER)\" \\\n\t\t\t-DCMAKE_ASM_COMPILER_LAUNCHER=\"$(CMAKE_C_COMPILER_LAUNCHER)\" \\\n\t\t\t-DCMAKE_ASM_COMPILER=\"$(CMAKE_C_COMPILER)\" \\\n\t\t\t-DCMAKE_EXE_LINKER_FLAGS:STRING=\"$(TARGET_LDFLAGS)\" \\\n\t\t\t-DCMAKE_MODULE_LINKER_FLAGS:STRING=\"$(TARGET_LDFLAGS) $(CMAKE_SHARED_LDFLAGS)\" \\\n\t\t\t-DCMAKE_SHARED_LINKER_FLAGS:STRING=\"$(TARGET_LDFLAGS) $(CMAKE_SHARED_LDFLAGS)\" \\\n\t\t\t-DCMAKE_AR=\"$(CMAKE_AR)\" \\\n\t\t\t-DCMAKE_NM=\"$(CMAKE_NM)\" \\\n\t\t\t-DCMAKE_RANLIB=\"$(CMAKE_RANLIB)\" \\\n\t\t\t-DCMAKE_FIND_ROOT_PATH=\"$(CMAKE_FIND_ROOT_PATH)\" \\\n\t\t\t-DCMAKE_FIND_ROOT_PATH_MODE_PROGRAM=BOTH \\\n\t\t\t-DCMAKE_FIND_ROOT_PATH_MODE_LIBRARY=ONLY \\\n\t\t\t-DCMAKE_FIND_ROOT_PATH_MODE_INCLUDE=ONLY \\\n\t\t\t-DCMAKE_STRIP=: \\\n\t\t\t-DCMAKE_INSTALL_PREFIX=/usr \\\n\t\t\t-DDL_LIBRARY=$(STAGING_DIR) \\\n\t\t\t-DCMAKE_PREFIX_PATH=$(STAGING_DIR) \\\n\t\t\t-DCMAKE_SKIP_RPATH=TRUE  \\\n\t\t\t-DCMAKE_EXPORT_PACKAGE_REGISTRY=FALSE \\\n\t\t\t-DCMAKE_EXPORT_NO_PACKAGE_REGISTRY=TRUE \\\n\t\t\t-DCMAKE_FIND_USE_PACKAGE_REGISTRY=FALSE \\\n\t\t\t-DCMAKE_FIND_PACKAGE_NO_PACKAGE_REGISTRY=TRUE \\\n\t\t\t-DCMAKE_FIND_USE_SYSTEM_PACKAGE_REGISTRY=FALSE \\\n\t\t\t-DCMAKE_FIND_PACKAGE_NO_SYSTEM_PACKAGE_REGISTRY=TRUE \\\n\t\t\t$(CMAKE_OPTIONS) \\\n\t\t$(CMAKE_SOURCE_DIR) \\\n\t)\nendef\n\ndefine Build/InstallDev/cmake\n\t$(INSTALL_DIR) $(1)\n\t$(CP) $(PKG_INSTALL_DIR)/* $(1)/\nendef\n\nBuild/InstallDev = $(if $(CMAKE_INSTALL),$(Build/InstallDev/cmake))\n\ndefine Host/Configure/Default\n\tmkdir -p \"$(HOST_CMAKE_BINARY_DIR)\"\n\t(cd $(HOST_CMAKE_BINARY_DIR); \\\n\t\tCFLAGS=\"$(HOST_CFLAGS)\" \\\n\t\tCXXFLAGS=\"$(HOST_CFLAGS)\" \\\n\t\tLDFLAGS=\"$(HOST_LDFLAGS)\" \\\n\t\tcmake \\\n\t\t\t-DCMAKE_BUILD_TYPE=Release \\\n\t\t\t-DCMAKE_C_COMPILER_LAUNCHER=\"$(CMAKE_C_COMPILER_LAUNCHER)\" \\\n\t\t\t-DCMAKE_C_COMPILER=\"$(CMAKE_HOST_C_COMPILER)\" \\\n\t\t\t-DCMAKE_CXX_COMPILER_LAUNCHER=\"$(CMAKE_CXX_COMPILER_LAUNCHER)\" \\\n\t\t\t-DCMAKE_CXX_COMPILER=\"$(CMAKE_HOST_CXX_COMPILER)\" \\\n\t\t\t-DCMAKE_ASM_COMPILER_LAUNCHER=\"$(CMAKE_C_COMPILER_LAUNCHER)\" \\\n\t\t\t-DCMAKE_ASM_COMPILER=\"$(CMAKE_HOST_C_COMPILER)\" \\\n\t\t\t-DCMAKE_C_FLAGS_RELEASE=\"-DNDEBUG\" \\\n\t\t\t-DCMAKE_CXX_FLAGS_RELEASE=\"-DNDEBUG\" \\\n\t\t\t-DCMAKE_EXE_LINKER_FLAGS:STRING=\"$(HOST_LDFLAGS)\" \\\n\t\t\t-DCMAKE_MODULE_LINKER_FLAGS:STRING=\"$(HOST_LDFLAGS)\" \\\n\t\t\t-DCMAKE_SHARED_LINKER_FLAGS:STRING=\"$(HOST_LDFLAGS)\" \\\n\t\t\t-DCMAKE_FIND_ROOT_PATH=\"$(CMAKE_HOST_FIND_ROOT_PATH)\" \\\n\t\t\t-DCMAKE_FIND_ROOT_PATH_MODE_PROGRAM=BOTH \\\n\t\t\t-DCMAKE_FIND_ROOT_PATH_MODE_LIBRARY=ONLY \\\n\t\t\t-DCMAKE_FIND_ROOT_PATH_MODE_INCLUDE=ONLY \\\n\t\t\t-DCMAKE_STRIP=: \\\n\t\t\t-DCMAKE_INSTALL_PREFIX=$(CMAKE_HOST_INSTALL_PREFIX) \\\n\t\t\t-DCMAKE_PREFIX_PATH=$(HOST_BUILD_PREFIX) \\\n\t\t\t-DCMAKE_SKIP_RPATH=TRUE  \\\n\t\t\t-DCMAKE_INSTALL_LIBDIR=lib \\\n\t\t\t-DCMAKE_EXPORT_PACKAGE_REGISTRY=FALSE \\\n\t\t\t-DCMAKE_EXPORT_NO_PACKAGE_REGISTRY=TRUE \\\n\t\t\t-DCMAKE_FIND_USE_PACKAGE_REGISTRY=FALSE \\\n\t\t\t-DCMAKE_FIND_PACKAGE_NO_PACKAGE_REGISTRY=TRUE \\\n\t\t\t-DCMAKE_FIND_USE_SYSTEM_PACKAGE_REGISTRY=FALSE \\\n\t\t\t-DCMAKE_FIND_PACKAGE_NO_SYSTEM_PACKAGE_REGISTRY=TRUE \\\n\t\t\t$(CMAKE_HOST_OPTIONS) \\\n\t\t$(HOST_CMAKE_SOURCE_DIR) \\\n\t)\nendef\n\nMAKE_FLAGS += \\\n\tCMAKE_COMMAND='$$(if $$(CMAKE_DISABLE_$$@),:,$(STAGING_DIR_HOST)/bin/cmake)' \\\n\tCMAKE_DISABLE_cmake_check_build_system=1\n"
  },
  {
    "path": "include/debug.mk",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2007-2020 OpenWrt.org\n\n# debug flags:\n#\n# d: show subdirectory tree\n# t: show added targets\n# l: show legacy targets\n# r: show autorebuild messages\n# v: verbose (no .SILENCE for common targets)\n\nifeq ($(DUMP),)\n  ifeq ($(DEBUG),all)\n    build_debug:=dltvr\n  else\n    build_debug:=$(DEBUG)\n  endif\nendif\n\nifneq ($(DEBUG),)\n\ndefine debug\n$$(findstring $(2),$$(if $$(DEBUG_SCOPE_DIR),$$(if $$(filter $$(DEBUG_SCOPE_DIR)%,$(1)),$(build_debug)),$(build_debug)))\nendef\n\ndefine warn\n$$(if $(call debug,$(1),$(2)),$$(warning $(3)))\nendef\n\ndefine debug_eval\n$$(if $(call debug,$(1),$(2)),$(3))\nendef\n\ndefine warn_eval\n$(call warn,$(1),$(2),$(3)\t$(4))\n$(4)\nendef\n\nelse\n\ndebug:=\nwarn:=\ndebug_eval:=\nwarn_eval = $(4)\n\nendif\n\n"
  },
  {
    "path": "include/depends.mk",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2007-2020 OpenWrt.org\n\n# define a dependency on a subtree\n# parameters:\n#\t1: directories/files\n#\t2: directory dependency\n#\t3: tempfile for file listings\n#\t4: find options\n\nDEP_FINDPARAMS := -x \"*/.svn*\" -x \".*\" -x \"*:*\" -x \"*\\!*\" -x \"* *\" -x \"*\\\\\\#*\" -x \"*/.*_check\" -x \"*/.*.swp\" -x \"*/.pkgdir*\"\n\nfind_md5=find $(wildcard $(1)) -type f $(patsubst -x,-and -not -path,$(DEP_FINDPARAMS) $(2)) -printf \"%p%T@\\n\" | sort | $(MKHASH) md5\n\ndefine rdep\n  .PRECIOUS: $(2)\n  .SILENT: $(2)_check\n\n  $(2): $(2)_check\n  check-depends: $(2)_check\n\nifneq ($(wildcard $(2)),)\n  $(2)_check::\n\t$(if $(3), \\\n\t\t$(call find_md5,$(1),$(4)) > $(3).1; \\\n\t\t{ [ \\! -f \"$(3)\" ] || diff $(3) $(3).1 >/dev/null; } && \\\n\t) \\\n\t{ \\\n\t\t[ -f \"$(2)_check.1\" ] && mv \"$(2)_check.1\"; \\\n\t    $(TOPDIR)/scripts/timestamp.pl $(DEP_FINDPARAMS) $(4) -n $(2) $(1) && { \\\n\t\t\t$(call debug_eval,$(SUBDIR),r,echo \"No need to rebuild $(2)\";) \\\n\t\t\ttouch -r \"$(2)\" \"$(2)_check\"; \\\n\t\t} \\\n\t} || { \\\n\t\t$(call debug_eval,$(SUBDIR),r,echo \"Need to rebuild $(2)\";) \\\n\t\ttouch \"$(2)_check\"; \\\n\t}\n\t$(if $(3), mv $(3).1 $(3))\nelse\n  $(2)_check::\n\t$(if $(3), rm -f $(3) $(3).1)\n\t$(call debug_eval,$(SUBDIR),r,echo \"Target $(2) not built\")\nendif\n\nendef\n\nifeq ($(filter .%,$(MAKECMDGOALS)),$(if $(MAKECMDGOALS),$(MAKECMDGOALS),x))\n  define rdep\n    $(2): $(2)_check\n  endef\nendif\n"
  },
  {
    "path": "include/device_table.txt",
    "content": "# minimal device table file for OpenWrt\n\n#<name>\t\t<type>\t<mode>\t<uid>\t<gid>\t<major>\t<minor>\t<start>\t<inc>\t<count>\n/dev\t\td\t755\t0\t0\t-\t-\t-\t-\t-\n/dev/console\tc\t600\t0\t0\t5\t1\t0\t0\t-\n"
  },
  {
    "path": "include/download.mk",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2006-2012 OpenWrt.org\n# Copyright (C) 2016 LEDE project\n\nPROJECT_GIT = https://git.openwrt.org\n\nOPENWRT_GIT = $(PROJECT_GIT)\nLEDE_GIT = $(PROJECT_GIT)\n\nifdef PKG_SOURCE_VERSION\n  ifndef PKG_VERSION\n    PKG_VERSION := $(if $(PKG_SOURCE_DATE),$(PKG_SOURCE_DATE)-)$(call version_abbrev,$(PKG_SOURCE_VERSION))\n  endif\n  PKG_SOURCE_SUBDIR ?= $(PKG_NAME)-$(PKG_VERSION)\n  PKG_SOURCE ?= $(PKG_SOURCE_SUBDIR).tar.xz\nendif\n\nDOWNLOAD_RDEP=$(STAMP_PREPARED) $(HOST_STAMP_PREPARED)\n\ndefine dl_method_git\n$(if $(filter https://github.com/% git://github.com/%,$(1)),github_archive,git)\nendef\n\n# Try to guess the download method from the URL\ndefine dl_method\n$(strip \\\n  $(if $(filter git,$(2)),$(call dl_method_git,$(1),$(2)),\n    $(if $(2),$(2), \\\n      $(if $(filter @OPENWRT @APACHE/% @DEBIAN/% @GITHUB/% @GNOME/% @GNU/% @KERNEL/% @SF/% @SAVANNAH/% ftp://% http://% https://% file://%,$(1)),default, \\\n        $(if $(filter git://%,$(1)),$(call dl_method_git,$(1),$(2)), \\\n          $(if $(filter svn://%,$(1)),svn, \\\n            $(if $(filter cvs://%,$(1)),cvs, \\\n              $(if $(filter hg://%,$(1)),hg, \\\n                $(if $(filter sftp://%,$(1)),bzr, \\\n                  unknown \\\n                ) \\\n              ) \\\n            ) \\\n          ) \\\n        ) \\\n      ) \\\n    ) \\\n  ) \\\n)\nendef\n\n# code for creating tarballs from cvs/svn/git/bzr/hg/darcs checkouts - useful for mirror support\ndl_pack/bz2=bzip2 -c > $(1)\ndl_pack/gz=gzip -nc > $(1)\ndl_pack/xz=xz -zc -7e > $(1)\ndl_pack/zst=zstd -T0 --ultra -20 -c > $(1)\ndl_pack/unknown=$(error ERROR: Unknown pack format for file $(1))\ndefine dl_pack\n\t$(if $(dl_pack/$(call ext,$(1))),$(dl_pack/$(call ext,$(1))),$(dl_pack/unknown))\nendef\ndefine dl_tar_pack\n\t$(TAR) --numeric-owner --owner=0 --group=0 --mode=a-s --sort=name \\\n\t\t$$$${TAR_TIMESTAMP:+--mtime=\"$$$$TAR_TIMESTAMP\"} -c $(2) | $(call dl_pack,$(1))\nendef\n\ngen_sha256sum = $(shell $(MKHASH) sha256 $(DL_DIR)/$(1))\n\n# Used in Build/CoreTargets and HostBuild/Core as an integrity check for\n# downloaded files.  It will add a FORCE rule if the sha256 hash does not\n# match, so that the download can be more thoroughly handled by download.pl.\ndefine check_download_integrity\n  expected_hash:=$(strip $(if $(filter-out x,$(HASH)),$(HASH),$(MIRROR_HASH)))\n  $$(if $$(and $(FILE),$$(wildcard $(DL_DIR)/$(FILE)), \\\n\t       $$(filter undefined,$$(flavor DownloadChecked/$(FILE)))), \\\n    $$(eval DownloadChecked/$(FILE):=1) \\\n    $$(if $$(filter-out $$(call gen_sha256sum,$(FILE)),$$(expected_hash)), \\\n      $(DL_DIR)/$(FILE): FORCE) \\\n  )\nendef\n\nifdef CHECK\ncheck_escape=$(subst ','\\'',$(1))\n#')\n\n# $(1): suffix of the F_, C_ variables, e.g. hash_deprecated, hash_mismatch, etc.\n# $(2): filename\n# $(3): expected hash value\n# $(4): var name of the the form: {PKG_,Download/<name>:}{,MIRROR_}{HASH,MIRROR_HASH}\ncheck_warn_nofix = $(info $(shell printf \"$(_R)WARNING: %s$(_N)\" '$(call check_escape,$(call C_$(1),$(2),$(3),$(4)))'))\nifndef FIXUP\n  check_warn = $(check_warn_nofix)\nelse\n  check_warn = $(if $(filter-out undefined,$(origin F_$(1))),$(filter ,$(shell $(call F_$(1),$(2),$(3),$(4)) >&2)),$(check_warn_nofix))\nendif\n\nifdef FIXUP\nF_hash_deprecated = $(SCRIPT_DIR)/fixup-makefile.pl $(CURDIR)/Makefile fix-hash $(3) $(call gen_sha256sum,$(1)) $(2)\nF_hash_mismatch = $(F_hash_deprecated)\nF_hash_missing = $(SCRIPT_DIR)/fixup-makefile.pl $(CURDIR)/Makefile add-hash $(3) $(call gen_sha256sum,$(1))\nendif\n\n# $(1): filename\n# $(2): expected hash value\n# $(3): var name of the the form: {PKG_,Download/<name>:}{,MIRROR_}{HASH,MIRROR_HASH}\nC_download_missing = $(1) is missing, please run make download before re-running this check\nC_hash_mismatch = $(3) does not match $(1) hash $(call gen_sha256sum,$(1))\nC_hash_deprecated = $(3) uses deprecated hash, set to $(call gen_sha256sum,$(1))\nC_hash_missing = $(3) is missing, set to $(call gen_sha256sum,$(1))\n\n# $(1): filename\n# $(2): expected hash value\n# $(3): var name of the the form: {PKG_,Download/<name>:}{,MIRROR_}{HASH,MIRROR_HASH}\ncheck_hash = \\\n  $(if $(wildcard $(DL_DIR)/$(1)), \\\n    $(if $(filter-out x,$(2)), \\\n      $(if $(filter 64,$(shell printf '%s' '$(2)' | wc -c)), \\\n        $(if $(filter $(2),$(call gen_sha256sum,$(1))),, \\\n          $(call check_warn,hash_mismatch,$(1),$(2),$(3)) \\\n        ), \\\n        $(call check_warn,hash_deprecated,$(1),$(2),$(3)), \\\n      ), \\\n      $(call check_warn,hash_missing,$(1),$(2),$(3)) \\\n    ), \\\n    $(call check_warn,download_missing,$(1),$(2),$(3)) \\\n  )\n\nifdef FIXUP\nF_md5_deprecated = $(SCRIPT_DIR)/fixup-makefile.pl $(CURDIR)/Makefile rename-var $(2) $(3)\nendif\n\nC_md5_deprecated = Use of $(2) is deprecated, switch to $(3)\n\ncheck_md5 = \\\n  $(if $(filter-out x,$(1)), \\\n    $(call check_warn,md5_deprecated,$(1),$(2),$(3)) \\\n  )\n\nhash_var = $(if $(filter-out x,$(1)),MD5SUM,HASH)\nendif\n\ndefine DownloadMethod/unknown\n\techo \"ERROR: No download method available\"; false\nendef\n\ndefine DownloadMethod/default\n\t$(SCRIPT_DIR)/download.pl \"$(DL_DIR)\" \"$(FILE)\" \"$(HASH)\" \"$(URL_FILE)\" $(foreach url,$(URL),\"$(url)\") \\\n\t$(if $(filter check,$(1)), \\\n\t\t$(call check_hash,$(FILE),$(HASH),$(2)$(call hash_var,$(MD5SUM))) \\\n\t\t$(call check_md5,$(MD5SUM),$(2)MD5SUM,$(2)HASH) \\\n\t)\nendef\n\n# $(1): \"check\"\n# $(2): \"PKG_\" if <name> as in Download/<name> is \"default\", otherwise \"Download/<name>:\"\n# $(3): shell command sequence to do the download\ndefine wrap_mirror\n$(if $(if $(MIRROR),$(filter-out x,$(MIRROR_HASH))),$(SCRIPT_DIR)/download.pl \"$(DL_DIR)\" \"$(FILE)\" \"$(MIRROR_HASH)\" \"\" || ( $(3) ),$(3)) \\\n$(if $(filter check,$(1)), \\\n\t$(call check_hash,$(FILE),$(MIRROR_HASH),$(2)MIRROR_$(call hash_var,$(MIRROR_MD5SUM))) \\\n\t$(call check_md5,$(MIRROR_MD5SUM),$(2)MIRROR_MD5SUM,$(2)MIRROR_HASH) \\\n)\nendef\n\ndefine DownloadMethod/cvs\n\t$(call wrap_mirror,$(1),$(2), \\\n\t\techo \"Checking out files from the cvs repository...\"; \\\n\t\tmkdir -p $(TMP_DIR)/dl && \\\n\t\tcd $(TMP_DIR)/dl && \\\n\t\trm -rf $(SUBDIR) && \\\n\t\t[ \\! -d $(SUBDIR) ] && \\\n\t\tcvs -d $(URL) export $(VERSION) $(SUBDIR) && \\\n\t\techo \"Packing checkout...\" && \\\n\t\t$(call dl_tar_pack,$(TMP_DIR)/dl/$(FILE),$(SUBDIR)) && \\\n\t\tmv $(TMP_DIR)/dl/$(FILE) $(DL_DIR)/ && \\\n\t\trm -rf $(SUBDIR); \\\n\t)\nendef\n\ndefine DownloadMethod/svn\n\t$(call wrap_mirror,$(1),$(2), \\\n\t\techo \"Checking out files from the svn repository...\"; \\\n\t\tmkdir -p $(TMP_DIR)/dl && \\\n\t\tcd $(TMP_DIR)/dl && \\\n\t\trm -rf $(SUBDIR) && \\\n\t\t[ \\! -d $(SUBDIR) ] && \\\n\t\t( svn help export | grep -q trust-server-cert && \\\n\t\tsvn export --non-interactive --trust-server-cert -r$(VERSION) $(URL) $(SUBDIR) || \\\n\t\tsvn export --non-interactive -r$(VERSION) $(URL) $(SUBDIR) ) && \\\n\t\techo \"Packing checkout...\" && \\\n\t\texport TAR_TIMESTAMP=\"\" && \\\n\t\t$(call dl_tar_pack,$(TMP_DIR)/dl/$(FILE),$(SUBDIR)) && \\\n\t\tmv $(TMP_DIR)/dl/$(FILE) $(DL_DIR)/ && \\\n\t\trm -rf $(SUBDIR); \\\n\t)\nendef\n\ndefine DownloadMethod/git\n\t$(call wrap_mirror,$(1),$(2), \\\n\t\t$(call DownloadMethod/rawgit) \\\n\t)\nendef\n\ndefine DownloadMethod/github_archive\n\t$(call wrap_mirror,$(1),$(2), \\\n\t\t$(SCRIPT_DIR)/dl_github_archive.py \\\n\t\t\t--dl-dir=\"$(DL_DIR)\" \\\n\t\t\t--url=\"$(URL)\" \\\n\t\t\t--version=\"$(VERSION)\" \\\n\t\t\t--subdir=\"$(SUBDIR)\" \\\n\t\t\t--source=\"$(FILE)\" \\\n\t\t\t--hash=\"$(MIRROR_HASH)\" \\\n\t\t|| ( $(call DownloadMethod/rawgit) ); \\\n\t)\nendef\n\n# Only intends to be called as a submethod from other DownloadMethod\ndefine DownloadMethod/rawgit\n\techo \"Checking out files from the git repository...\"; \\\n\tmkdir -p $(TMP_DIR)/dl && \\\n\tcd $(TMP_DIR)/dl && \\\n\trm -rf $(SUBDIR) && \\\n\t[ \\! -d $(SUBDIR) ] && \\\n\tgit clone $(OPTS) $(URL) $(SUBDIR) && \\\n\t(cd $(SUBDIR) && git checkout $(VERSION) && \\\n\tgit submodule update --init --recursive) && \\\n\techo \"Packing checkout...\" && \\\n\texport TAR_TIMESTAMP=`cd $(SUBDIR) && git log -1 --format='@%ct'` && \\\n\trm -rf $(SUBDIR)/.git && \\\n\t$(call dl_tar_pack,$(TMP_DIR)/dl/$(FILE),$(SUBDIR)) && \\\n\tmv $(TMP_DIR)/dl/$(FILE) $(DL_DIR)/ && \\\n\trm -rf $(SUBDIR);\nendef\n\ndefine DownloadMethod/bzr\n\t$(call wrap_mirror,$(1),$(2), \\\n\t\techo \"Checking out files from the bzr repository...\"; \\\n\t\tmkdir -p $(TMP_DIR)/dl && \\\n\t\tcd $(TMP_DIR)/dl && \\\n\t\trm -rf $(SUBDIR) && \\\n\t\t[ \\! -d $(SUBDIR) ] && \\\n\t\tbzr export --per-file-timestamps -r$(VERSION) $(SUBDIR) $(URL) && \\\n\t\techo \"Packing checkout...\" && \\\n\t\texport TAR_TIMESTAMP=\"\" && \\\n\t\t$(call dl_tar_pack,$(TMP_DIR)/dl/$(FILE),$(SUBDIR)) && \\\n\t\tmv $(TMP_DIR)/dl/$(FILE) $(DL_DIR)/ && \\\n\t\trm -rf $(SUBDIR); \\\n\t)\nendef\n\ndefine DownloadMethod/hg\n\t$(call wrap_mirror,$(1),$(2), \\\n\t\techo \"Checking out files from the hg repository...\"; \\\n\t\tmkdir -p $(TMP_DIR)/dl && \\\n\t\tcd $(TMP_DIR)/dl && \\\n\t\trm -rf $(SUBDIR) && \\\n\t\t[ \\! -d $(SUBDIR) ] && \\\n\t\thg clone -r $(VERSION) $(URL) $(SUBDIR) && \\\n\t\texport TAR_TIMESTAMP=`cd $(SUBDIR) && hg log --template '@{date}' -l 1` && \\\n\t\tfind $(SUBDIR) -name .hg | xargs rm -rf && \\\n\t\techo \"Packing checkout...\" && \\\n\t\t$(call dl_tar_pack,$(TMP_DIR)/dl/$(FILE),$(SUBDIR)) && \\\n\t\tmv $(TMP_DIR)/dl/$(FILE) $(DL_DIR)/ && \\\n\t\trm -rf $(SUBDIR); \\\n\t)\nendef\n\ndefine DownloadMethod/darcs\n\t$(call wrap_mirror, $(1), $(2), \\\n\t\techo \"Checking out files from the darcs repository...\"; \\\n\t\tmkdir -p $(TMP_DIR)/dl && \\\n\t\tcd $(TMP_DIR)/dl && \\\n\t\trm -rf $(SUBDIR) && \\\n\t\t[ \\! -d $(SUBDIR) ] && \\\n\t\tdarcs get -t $(VERSION) $(URL) $(SUBDIR) && \\\n\t\texport TAR_TIMESTAMP=`cd $(SUBDIR) && LC_ALL=C darcs log --last 1 | sed -ne 's!^Date: \\+!!p'` && \\\n\t\tfind $(SUBDIR) -name _darcs | xargs rm -rf && \\\n\t\techo \"Packing checkout...\" && \\\n\t\t$(call dl_tar_pack,$(TMP_DIR)/dl/$(FILE),$(SUBDIR)) && \\\n\t\tmv $(TMP_DIR)/dl/$(FILE) $(DL_DIR)/ && \\\n\t\trm -rf $(SUBDIR); \\\n\t)\nendef\n\nValidate/cvs=VERSION SUBDIR\nValidate/svn=VERSION SUBDIR\nValidate/git=VERSION SUBDIR\nValidate/bzr=VERSION SUBDIR\nValidate/hg=VERSION SUBDIR\nValidate/darcs=VERSION SUBDIR\n\ndefine Download/Defaults\n  URL:=\n  FILE:=\n  URL_FILE:=\n  PROTO:=\n  HASH=$$(MD5SUM)\n  MD5SUM:=x\n  SUBDIR:=\n  MIRROR:=1\n  MIRROR_HASH=$$(MIRROR_MD5SUM)\n  MIRROR_MD5SUM:=x\n  VERSION:=\n  OPTS:=\nendef\n\ndefine Download/default\n  FILE:=$(PKG_SOURCE)\n  URL:=$(PKG_SOURCE_URL)\n  URL_FILE:=$(PKG_SOURCE_URL_FILE)\n  SUBDIR:=$(PKG_SOURCE_SUBDIR)\n  PROTO:=$(PKG_SOURCE_PROTO)\n  $(if $(PKG_SOURCE_MIRROR),MIRROR:=$(filter 1,$(PKG_MIRROR)))\n  $(if $(PKG_MIRROR_MD5SUM),MIRROR_MD5SUM:=$(PKG_MIRROR_MD5SUM))\n  $(if $(PKG_MIRROR_HASH),MIRROR_HASH:=$(PKG_MIRROR_HASH))\n  VERSION:=$(PKG_SOURCE_VERSION)\n  $(if $(PKG_MD5SUM),MD5SUM:=$(PKG_MD5SUM))\n  $(if $(PKG_HASH),HASH:=$(PKG_HASH))\nendef\n\ndefine Download\n  $(eval $(Download/Defaults))\n  $(eval $(Download/$(1)))\n  $(foreach FIELD,URL FILE $(Validate/$(call dl_method,$(URL),$(PROTO))),\n    ifeq ($($(FIELD)),)\n      $$(error Download/$(1) is missing the $(FIELD) field.)\n    endif\n  )\n\n  $(foreach dep,$(DOWNLOAD_RDEP),\n    $(dep): $(DL_DIR)/$(FILE)\n  )\n  download: $(DL_DIR)/$(FILE)\n\n  $(DL_DIR)/$(FILE):\n\tmkdir -p $(DL_DIR)\n\t$(call locked, \\\n\t\t$(if $(DownloadMethod/$(call dl_method,$(URL),$(PROTO))), \\\n\t\t\t$(call DownloadMethod/$(call dl_method,$(URL),$(PROTO)),check,$(if $(filter default,$(1)),PKG_,Download/$(1):)), \\\n\t\t\t$(DownloadMethod/unknown) \\\n\t\t),\\\n\t\t$(FILE))\n\nendef\n"
  },
  {
    "path": "include/feeds.mk",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2014 OpenWrt.org\n# Copyright (C) 2016 LEDE Project\n\n-include $(TMP_DIR)/.packageauxvars\n\nFEEDS_INSTALLED:=$(notdir $(wildcard $(TOPDIR)/package/feeds/*))\nFEEDS_AVAILABLE:=$(sort $(FEEDS_INSTALLED) $(shell $(SCRIPT_DIR)/feeds list -n 2>/dev/null))\n\nPACKAGE_SUBDIRS=$(PACKAGE_DIR)\nifneq ($(CONFIG_PER_FEED_REPO),)\n  PACKAGE_SUBDIRS += $(OUTPUT_DIR)/packages/$(ARCH_PACKAGES)/base\n  PACKAGE_SUBDIRS += $(foreach FEED,$(FEEDS_AVAILABLE),$(OUTPUT_DIR)/packages/$(ARCH_PACKAGES)/$(FEED))\nendif\n\nopkg_package_files = $(wildcard \\\n\t$(foreach dir,$(PACKAGE_SUBDIRS), \\\n\t  $(foreach pkg,$(1), $(dir)/$(pkg)_*.ipk)))\n\n# 1: package name\ndefine FeedPackageDir\n$(strip $(if $(CONFIG_PER_FEED_REPO), \\\n  $(if $(Package/$(1)/subdir), \\\n    $(abspath $(OUTPUT_DIR)/packages/$(ARCH_PACKAGES)/$(Package/$(1)/subdir)), \\\n    $(PACKAGE_DIR)), \\\n  $(PACKAGE_DIR)))\nendef\n\n# 1: destination file\ndefine FeedSourcesAppend\n( \\\n  echo 'src/gz %d_core %U/targets/%S/packages'; \\\n  $(strip $(if $(CONFIG_PER_FEED_REPO), \\\n\techo 'src/gz %d_base %U/packages/%A/base'; \\\n\t$(if $(filter %SNAPSHOT-y,$(VERSION_NUMBER)-$(CONFIG_BUILDBOT)), \\\n\t\techo 'src/gz %d_kmods %U/targets/%S/kmods/$(LINUX_VERSION)-$(LINUX_RELEASE)-$(LINUX_VERMAGIC)';) \\\n\t$(foreach feed,$(FEEDS_AVAILABLE), \\\n\t\t$(if $(CONFIG_FEED_$(feed)), \\\n\t\t\techo '$(if $(filter m,$(CONFIG_FEED_$(feed))),# )src/gz %d_$(feed) %U/packages/%A/$(feed)';)))) \\\n) >> $(1)\nendef\n\n# 1: package name\ndefine GetABISuffix\n$(if $(ABIV_$(1)),$(ABIV_$(1)),$(call FormatABISuffix,$(1),$(foreach v,$(wildcard $(STAGING_DIR)/pkginfo/$(1).version),$(shell cat $(v)))))\nendef\n\n# 1: package name\n# 2: abi version\ndefine FormatABISuffix\n$(if $(filter-out kmod-%,$(1)),$(if $(2),$(if $(filter %0 %1 %2 %3 %4 %5 %6 %7 %8 %9,$(1)),-)$(2)))\nendef\n"
  },
  {
    "path": "include/hardened-ld-pie.specs",
    "content": "*self_spec:\n+ %{no-pie|static|r|shared:;:-pie}\n"
  },
  {
    "path": "include/hardening.mk",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2015-2020 OpenWrt.org\n\nPKG_CHECK_FORMAT_SECURITY ?= 1\nPKG_ASLR_PIE ?= 1\nPKG_ASLR_PIE_REGULAR ?= 0\nPKG_SSP ?= 1\nPKG_FORTIFY_SOURCE ?= 1\nPKG_RELRO ?= 1\n\nifdef CONFIG_PKG_CHECK_FORMAT_SECURITY\n  ifeq ($(strip $(PKG_CHECK_FORMAT_SECURITY)),1)\n    TARGET_CFLAGS += -Wformat -Werror=format-security\n  endif\nendif\nifdef CONFIG_PKG_ASLR_PIE_ALL\n  ifeq ($(strip $(PKG_ASLR_PIE)),1)\n    TARGET_CFLAGS += $(FPIC)\n    TARGET_LDFLAGS += $(FPIC) -specs=$(INCLUDE_DIR)/hardened-ld-pie.specs\n  endif\nendif\nifdef CONFIG_PKG_ASLR_PIE_REGULAR\n  ifeq ($(strip $(PKG_ASLR_PIE_REGULAR)),1)\n    TARGET_CFLAGS += $(FPIC)\n    TARGET_LDFLAGS += $(FPIC) -specs=$(INCLUDE_DIR)/hardened-ld-pie.specs\n  endif\nendif\nifdef CONFIG_PKG_CC_STACKPROTECTOR_REGULAR\n  ifeq ($(strip $(PKG_SSP)),1)\n    TARGET_CFLAGS += -fstack-protector\n  endif\nendif\nifdef CONFIG_PKG_CC_STACKPROTECTOR_STRONG\n  ifeq ($(strip $(PKG_SSP)),1)\n    TARGET_CFLAGS += -fstack-protector-strong\n  endif\nendif\nifdef CONFIG_PKG_FORTIFY_SOURCE_1\n  ifeq ($(strip $(PKG_FORTIFY_SOURCE)),1)\n    TARGET_CFLAGS += -D_FORTIFY_SOURCE=1\n  endif\nendif\nifdef CONFIG_PKG_FORTIFY_SOURCE_2\n  ifeq ($(strip $(PKG_FORTIFY_SOURCE)),1)\n    TARGET_CFLAGS += -D_FORTIFY_SOURCE=2\n  endif\nendif\nifdef CONFIG_PKG_RELRO_PARTIAL\n  ifeq ($(strip $(PKG_RELRO)),1)\n    TARGET_CFLAGS += -Wl,-z,relro\n    TARGET_LDFLAGS += -zrelro\n  endif\nendif\nifdef CONFIG_PKG_RELRO_FULL\n  ifeq ($(strip $(PKG_RELRO)),1)\n    TARGET_CFLAGS += -Wl,-z,now -Wl,-z,relro\n    TARGET_LDFLAGS += -znow -zrelro\n  endif\nendif\n\n"
  },
  {
    "path": "include/host-build.mk",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2006-2020 OpenWrt.org\n\ninclude $(INCLUDE_DIR)/download.mk\n\nHOST_BUILD_DIR ?= $(BUILD_DIR_HOST)/$(PKG_NAME)$(if $(PKG_VERSION),-$(PKG_VERSION))\nHOST_INSTALL_DIR ?= $(HOST_BUILD_DIR)/host-install\nHOST_BUILD_PARALLEL ?=\n\nHOST_MAKE_J:=$(if $(MAKE_JOBSERVER),$(MAKE_JOBSERVER) $(if $(filter 3.% 4.0 4.1,$(MAKE_VERSION)),-j))\n\nifeq ($(strip $(HOST_BUILD_PARALLEL)),0)\nHOST_JOBS?=-j1\nelse\nHOST_JOBS?=$(if $(HOST_BUILD_PARALLEL),$(HOST_MAKE_J),-j1)\nendif\n\ninclude $(INCLUDE_DIR)/unpack.mk\ninclude $(INCLUDE_DIR)/depends.mk\ninclude $(INCLUDE_DIR)/quilt.mk\n\nBUILD_TYPES += host\nHOST_STAMP_PREPARED=$(HOST_BUILD_DIR)/.prepared$(if $(HOST_QUILT)$(DUMP),,$(shell $(call find_md5,${CURDIR} $(PKG_FILE_DEPENDS),))_$(call confvar,CONFIG_AUTOREMOVE $(HOST_PREPARED_DEPENDS)))\nHOST_STAMP_CONFIGURED:=$(HOST_BUILD_DIR)/.configured\nHOST_STAMP_BUILT:=$(HOST_BUILD_DIR)/.built\nHOST_BUILD_PREFIX?=$(if $(IS_PACKAGE_BUILD),$(STAGING_DIR_HOSTPKG),$(STAGING_DIR_HOST))\nHOST_STAMP_INSTALLED:=$(HOST_BUILD_PREFIX)/stamp/.$(PKG_NAME)_installed\n\noverride MAKEFLAGS=\n\ninclude $(INCLUDE_DIR)/autotools.mk\n\n_host_target:=$(if $(HOST_QUILT),,.)\n\nHost/Patch:=$(Host/Patch/Default)\nifneq ($(strip $(HOST_UNPACK)),)\n  define Host/Prepare/Default\n\t$(HOST_UNPACK)\n\t[ ! -d ./src/ ] || $(CP) ./src/* $(HOST_BUILD_DIR)\n\t$(Host/Patch)\n  endef\nendif\n\ndefine Host/Prepare\n  $(call Host/Prepare/Default)\nendef\n\nHOST_CONFIGURE_VARS = \\\n\tCC=\"$(HOSTCC)\" \\\n\tCFLAGS=\"$(HOST_CFLAGS)\" \\\n\tCXX=\"$(HOSTCXX)\" \\\n\tCPPFLAGS=\"$(HOST_CPPFLAGS)\" \\\n\tCXXFLAGS=\"$(HOST_CXXFLAGS)\" \\\n\tLDFLAGS=\"$(HOST_LDFLAGS)\" \\\n\tCONFIG_SHELL=\"$(SHELL)\"\n\nHOST_CONFIGURE_ARGS = \\\n\t--target=$(GNU_HOST_NAME) \\\n\t--host=$(GNU_HOST_NAME) \\\n\t--build=$(GNU_HOST_NAME) \\\n\t--program-prefix=\"\" \\\n\t--program-suffix=\"\" \\\n\t--prefix=$(HOST_BUILD_PREFIX) \\\n\t--exec-prefix=$(HOST_BUILD_PREFIX) \\\n\t--sysconfdir=$(HOST_BUILD_PREFIX)/etc \\\n\t--localstatedir=$(HOST_BUILD_PREFIX)/var \\\n\t--sbindir=$(HOST_BUILD_PREFIX)/bin\n\nHOST_MAKE_VARS = \\\n\tCFLAGS=\"$(HOST_CFLAGS)\" \\\n\tCPPFLAGS=\"$(HOST_CPPFLAGS)\" \\\n\tCXXFLAGS=\"$(HOST_CXXFLAGS)\" \\\n\tLDFLAGS=\"$(HOST_LDFLAGS)\"\n\nHOST_MAKE_FLAGS =\n\nHOST_CONFIGURE_CMD = $(BASH) ./configure\n\nifeq ($(HOST_OS),Darwin)\n  HOST_CONFIG_SITE:=$(INCLUDE_DIR)/site/darwin\nendif\n\ndefine Host/Configure/Default\n\t$(if $(HOST_CONFIGURE_PARALLEL),+)(cd $(HOST_BUILD_DIR)/$(3); \\\n\t\tif [ -x configure ]; then \\\n\t\t\t$(CP) $(SCRIPT_DIR)/config.{guess,sub} $(HOST_BUILD_DIR)/$(3)/ && \\\n\t\t\t$(HOST_CONFIGURE_VARS) \\\n\t\t\t$(2) \\\n\t\t\t$(HOST_CONFIGURE_CMD) \\\n\t\t\t$(HOST_CONFIGURE_ARGS) \\\n\t\t\t$(1); \\\n\t\tfi \\\n\t)\nendef\n\ndefine Host/Configure\n  $(call Host/Configure/Default)\nendef\n\ndefine Host/Compile/Default\n\t+$(HOST_MAKE_VARS) \\\n\t$(MAKE) $(HOST_JOBS) -C $(HOST_BUILD_DIR) \\\n\t\t$(HOST_MAKE_FLAGS) \\\n\t\t$(1)\nendef\n\ndefine Host/Compile\n  $(call Host/Compile/Default)\nendef\n\ndefine Host/Install/Default\n\t$(call Host/Compile/Default,install)\nendef\n\ndefine Host/Install\n  $(call Host/Install/Default,$(HOST_BUILD_PREFIX))\nendef\n\n\nifneq ($(if $(HOST_QUILT),,$(CONFIG_AUTOREBUILD)),)\n  define HostHost/Autoclean\n    $(call rdep,${CURDIR} $(PKG_FILE_DEPENDS),$(HOST_STAMP_PREPARED))\n    $(if $(if $(Host/Compile),$(filter prepare,$(MAKECMDGOALS)),1),,$(call rdep,$(HOST_BUILD_DIR),$(HOST_STAMP_BUILT)))\n  endef\nendif\n\ndefine Host/Exports/Default\n  $(1) : export ACLOCAL_INCLUDE=$$(foreach p,$$(wildcard $$(STAGING_DIR_HOST)/share/aclocal $$(STAGING_DIR_HOST)/share/aclocal-* $(if $(IS_PACKAGE_BUILD),$$(STAGING_DIR)/host/share/aclocal $$(STAGING_DIR_HOSTPKG)/share/aclocal $$(STAGING_DIR)/host/share/aclocal-*)),-I $$(p))\n  $(1) : export STAGING_PREFIX=$$(HOST_BUILD_PREFIX)\n  $(1) : export PKG_CONFIG_PATH=$$(STAGING_DIR_HOST)/lib/pkgconfig:$$(HOST_BUILD_PREFIX)/lib/pkgconfig\n  $(1) : export PKG_CONFIG_LIBDIR=$$(HOST_BUILD_PREFIX)/lib/pkgconfig\n  $(if $(HOST_CONFIG_SITE),$(1) : export CONFIG_SITE:=$(HOST_CONFIG_SITE))\n  $(if $(IS_PACKAGE_BUILD),$(1) : export PATH=$$(TARGET_PATH_PKG))\nendef\nHost/Exports=$(Host/Exports/Default)\n\n.NOTPARALLEL:\n\nifndef DUMP\n  define HostBuild/Core\n  $(if $(HOST_QUILT),$(Host/Quilt))\n  $(if $(DUMP),,$(call HostHost/Autoclean))\n\n  $(HOST_STAMP_PREPARED):\n\t@-rm -rf $(HOST_BUILD_DIR)\n\t@mkdir -p $(HOST_BUILD_DIR)\n\t$(foreach hook,$(Hooks/HostPrepare/Pre),$(call $(hook))$(sep))\n\t$(call Host/Prepare)\n\t$(foreach hook,$(Hooks/HostPrepare/Post),$(call $(hook))$(sep))\n\ttouch $$@\n\n  $(call Host/Exports,$(HOST_STAMP_CONFIGURED))\n  $(HOST_STAMP_CONFIGURED): $(HOST_STAMP_PREPARED)\n\t$(foreach hook,$(Hooks/HostConfigure/Pre),$(call $(hook))$(sep))\n\t$(call Host/Configure)\n\t$(foreach hook,$(Hooks/HostConfigure/Post),$(call $(hook))$(sep))\n\ttouch $$@\n\n  $(call Host/Exports,$(HOST_STAMP_BUILT))\n  $(HOST_STAMP_BUILT): $(HOST_STAMP_CONFIGURED)\n\t\t$(foreach hook,$(Hooks/HostCompile/Pre),$(call $(hook))$(sep))\n\t\t$(call Host/Compile)\n\t\t$(foreach hook,$(Hooks/HostCompile/Post),$(call $(hook))$(sep))\n\t\ttouch $$@\n\n  $(call Host/Exports,$(HOST_STAMP_INSTALLED))\n  $(HOST_STAMP_INSTALLED): $(HOST_STAMP_BUILT) $(if $(FORCE_HOST_INSTALL),FORCE)\n\t\t$(call Host/Install,$(HOST_BUILD_PREFIX))\n\t\t$(foreach hook,$(Hooks/HostInstall/Post),$(call $(hook))$(sep))\n\t\tmkdir -p $$(shell dirname $$@)\n\t\ttouch $(HOST_STAMP_BUILT)\n\t\ttouch $$@\n\n  $(call DefaultTargets,$(patsubst %,host-%,$(DEFAULT_SUBDIR_TARGETS)))\n  ifndef STAMP_BUILT\n    $(foreach t,$(DEFAULT_SUBDIR_TARGETS),\n      $(t): host-$(t)\n      .$(t): .host-$(t)\n    )\n    clean-build: host-clean-build\n  endif\n\n  $(call check_download_integrity)\n\n  $(_host_target)host-prepare: $(HOST_STAMP_PREPARED)\n  $(_host_target)host-configure: $(HOST_STAMP_CONFIGURED)\n  $(_host_target)host-compile: $(HOST_STAMP_BUILT) $(HOST_STAMP_INSTALLED)\n  host-install: host-compile\n\n  host-clean-build: FORCE\n\t$(call Host/Uninstall)\n\trm -rf $(HOST_BUILD_DIR) $(HOST_STAMP_BUILT)\n\n  host-clean: host-clean-build\n\t$(call Host/Clean)\n\trm -rf $(HOST_STAMP_INSTALLED)\n\n    ifneq ($(CONFIG_AUTOREMOVE),)\n      host-compile:\n\t\t$(FIND) $(HOST_BUILD_DIR) -mindepth 1 -maxdepth 1 -not '(' -type f -and -name '.*' -and -size 0 ')' | \\\n\t\t\t$(XARGS) rm -rf\n    endif\n  endef\nendif\n\ndefine HostBuild\n  $(HostBuild/Core)\n  $(if $(if $(PKG_HOST_ONLY),,$(if $(and $(filter host-%,$(MAKECMDGOALS)),$(PKG_SKIP_DOWNLOAD)),,$(STAMP_PREPARED))),,$(if $(strip $(PKG_SOURCE_URL)),$(call Download,default)))\nendef\n"
  },
  {
    "path": "include/image-commands.mk",
    "content": "# Build commands that can be called from Device/* templates\n\nIMAGE_KERNEL = $(word 1,$^)\nIMAGE_ROOTFS = $(word 2,$^)\n\ndefine ModelNameLimit16\n$(shell expr substr \"$(word 2, $(subst _, ,$(1)))\" 1 16)\nendef\n\ndefine rootfs_align\n$(patsubst %-256k,0x40000,$(patsubst %-128k,0x20000,$(patsubst %-64k,0x10000,$(patsubst squashfs%,0x4,$(patsubst root.%,%,$(1))))))\nendef\n\n\ndefine Build/append-dtb\n\tcat $(KDIR)/image-$(firstword $(DEVICE_DTS)).dtb >> $@\nendef\n\ndefine Build/append-dtb-elf\n\t$(TARGET_CROSS)objcopy \\\n\t\t--set-section-flags=.appended_dtb=alloc,contents \\\n\t\t--update-section \\\n\t\t.appended_dtb=$(KDIR)/image-$(firstword $(DEVICE_DTS)).dtb $@\nendef\n\ndefine Build/append-kernel\n\tdd if=$(IMAGE_KERNEL) >> $@\nendef\n\ndefine Build/package-kernel-ubifs\n\tmkdir $@.kernelubifs\n\tcp $@ $@.kernelubifs/kernel\n\t$(STAGING_DIR_HOST)/bin/mkfs.ubifs \\\n\t\t$(KERNEL_UBIFS_OPTS) \\\n\t\t-r $@.kernelubifs $@\n\trm -r $@.kernelubifs\nendef\n\ndefine Build/append-image\n\tcp \"$(BIN_DIR)/$(DEVICE_IMG_PREFIX)-$(1)\" \"$@.stripmeta\"\n\tfwtool -s /dev/null -t \"$@.stripmeta\" || :\n\tfwtool -i /dev/null -t \"$@.stripmeta\" || :\n\tdd if=\"$@.stripmeta\" >> \"$@\"\n\trm \"$@.stripmeta\"\nendef\n\nifdef IB\ndefine Build/append-image-stage\n\tdd if=$(STAGING_DIR_IMAGE)/$(BOARD)$(if $(SUBTARGET),-$(SUBTARGET))-$(DEVICE_NAME)-$(1) >> $@\nendef\nelse\ndefine Build/append-image-stage\n\tcp \"$(BIN_DIR)/$(DEVICE_IMG_PREFIX)-$(1)\" \"$@.stripmeta\"\n\tfwtool -s /dev/null -t \"$@.stripmeta\" || :\n\tfwtool -i /dev/null -t \"$@.stripmeta\" || :\n\tdd if=\"$@.stripmeta\" of=\"$(STAGING_DIR_IMAGE)/$(BOARD)$(if $(SUBTARGET),-$(SUBTARGET))-$(DEVICE_NAME)-$(1)\"\n\tdd if=\"$@.stripmeta\" >> \"$@\"\n\trm \"$@.stripmeta\"\nendef\nendif\n\n\ncompat_version=$(if $(DEVICE_COMPAT_VERSION),$(DEVICE_COMPAT_VERSION),1.0)\njson_quote=$(subst ','\\'',$(subst \",\\\",$(1)))\n#\")')\n\nlegacy_supported_message=$(SUPPORTED_DEVICES) - Image version mismatch: image $(compat_version), \\\n\tdevice 1.0. Please wipe config during upgrade (force required) or reinstall. \\\n\t$(if $(DEVICE_COMPAT_MESSAGE),Reason: $(DEVICE_COMPAT_MESSAGE),Please check documentation ...)\n\nmetadata_devices=$(if $(1),$(subst \"$(space)\",\"$(comma)\",$(strip $(foreach v,$(1),\"$(call json_quote,$(v))\"))))\nmetadata_json = \\\n\t'{ $(if $(IMAGE_METADATA),$(IMAGE_METADATA)$(comma)) \\\n\t\t\"metadata_version\": \"1.1\", \\\n\t\t\"compat_version\": \"$(call json_quote,$(compat_version))\", \\\n\t\t$(if $(DEVICE_COMPAT_MESSAGE),\"compat_message\": \"$(call json_quote,$(DEVICE_COMPAT_MESSAGE))\"$(comma)) \\\n\t\t$(if $(filter-out 1.0,$(compat_version)),\"new_supported_devices\": \\\n\t\t\t[$(call metadata_devices,$(SUPPORTED_DEVICES))]$(comma) \\\n\t\t\t\"supported_devices\": [\"$(call json_quote,$(legacy_supported_message))\"]$(comma)) \\\n\t\t$(if $(filter 1.0,$(compat_version)),\"supported_devices\":[$(call metadata_devices,$(SUPPORTED_DEVICES))]$(comma)) \\\n\t\t\"version\": { \\\n\t\t\t\"dist\": \"$(call json_quote,$(VERSION_DIST))\", \\\n\t\t\t\"version\": \"$(call json_quote,$(VERSION_NUMBER))\", \\\n\t\t\t\"revision\": \"$(call json_quote,$(REVISION))\", \\\n\t\t\t\"target\": \"$(call json_quote,$(TARGETID))\", \\\n\t\t\t\"board\": \"$(call json_quote,$(if $(BOARD_NAME),$(BOARD_NAME),$(DEVICE_NAME)))\" \\\n\t\t} \\\n\t}'\n\ndefine Build/append-metadata\n\t$(if $(SUPPORTED_DEVICES),-echo $(call metadata_json) | fwtool -I - $@)\n\tsha256sum \"$@\" | cut -d\" \" -f1 > \"$@.sha256sum\"\n\t[ ! -s \"$(BUILD_KEY)\" -o ! -s \"$(BUILD_KEY).ucert\" -o ! -s \"$@\" ] || { \\\n\t\tcp \"$(BUILD_KEY).ucert\" \"$@.ucert\" ;\\\n\t\tusign -S -m \"$@\" -s \"$(BUILD_KEY)\" -x \"$@.sig\" ;\\\n\t\tucert -A -c \"$@.ucert\" -x \"$@.sig\" ;\\\n\t\tfwtool -S \"$@.ucert\" \"$@\" ;\\\n\t}\nendef\n\ndefine Build/append-rootfs\n\tdd if=$(IMAGE_ROOTFS) >> $@\nendef\n\ndefine Build/append-squashfs-fakeroot-be\n\trm -rf $@.fakefs $@.fakesquashfs\n\tmkdir $@.fakefs\n\t$(STAGING_DIR_HOST)/bin/mksquashfs-lzma \\\n\t\t$@.fakefs $@.fakesquashfs \\\n\t\t-noappend -root-owned -be -nopad -b 65536 \\\n\t\t$(if $(SOURCE_DATE_EPOCH),-fixed-time $(SOURCE_DATE_EPOCH))\n\tcat $@.fakesquashfs >> $@\nendef\n\ndefine Build/append-string\n\techo -n $(1) >> $@\nendef\n\ndefine Build/append-ubi\n\tsh $(TOPDIR)/scripts/ubinize-image.sh \\\n\t\t$(if $(UBOOTENV_IN_UBI),--uboot-env) \\\n\t\t$(if $(KERNEL_IN_UBI),--kernel $(IMAGE_KERNEL)) \\\n\t\t$(foreach part,$(UBINIZE_PARTS),--part $(part)) \\\n\t\t--rootfs $(IMAGE_ROOTFS) \\\n\t\t$@.tmp \\\n\t\t-p $(BLOCKSIZE:%k=%KiB) -m $(PAGESIZE) \\\n\t\t$(if $(SUBPAGESIZE),-s $(SUBPAGESIZE)) \\\n\t\t$(if $(VID_HDR_OFFSET),-O $(VID_HDR_OFFSET)) \\\n\t\t$(UBINIZE_OPTS)\n\tcat $@.tmp >> $@\n\trm $@.tmp\nendef\n\ndefine Build/ubinize-kernel\n\tcp $@ $@.tmp\n\tsh $(TOPDIR)/scripts/ubinize-image.sh \\\n\t\t--kernel $@.tmp \\\n\t\t$@ \\\n\t\t-p $(BLOCKSIZE:%k=%KiB) -m $(PAGESIZE) \\\n\t\t$(if $(SUBPAGESIZE),-s $(SUBPAGESIZE)) \\\n\t\t$(if $(VID_HDR_OFFSET),-O $(VID_HDR_OFFSET)) \\\n\t\t$(UBINIZE_OPTS)\n\trm $@.tmp\nendef\n\ndefine Build/append-uboot\n\tdd if=$(UBOOT_PATH) >> $@\nendef\n\n# append a fake/empty uImage header, to fool bootloaders rootfs integrity check\n# for example\ndefine Build/append-uImage-fakehdr\n\t$(eval type=$(word 1,$(1)))\n\t$(eval magic=$(word 2,$(1)))\n\ttouch $@.fakehdr\n\t$(STAGING_DIR_HOST)/bin/mkimage \\\n\t\t-A $(LINUX_KARCH) -O linux -T $(type) -C none \\\n\t\t-n '$(VERSION_DIST) fake $(type)' \\\n\t\t$(if $(magic),-M $(magic)) \\\n\t\t-d $@.fakehdr \\\n\t\t-s \\\n\t\t$@.fakehdr\n\tcat $@.fakehdr >> $@\nendef\n\ndefine Build/buffalo-dhp-image\n\t$(STAGING_DIR_HOST)/bin/mkdhpimg $@ $@.new\n\tmv $@.new $@\nendef\n\ndefine Build/buffalo-enc\n\t$(eval product=$(word 1,$(1)))\n\t$(eval version=$(word 2,$(1)))\n\t$(eval args=$(wordlist 3,$(words $(1)),$(1)))\n\t$(STAGING_DIR_HOST)/bin/buffalo-enc \\\n\t\t-p $(product) -v $(version) $(args) \\\n\t\t-i $@ -o $@.new\n\tmv $@.new $@\nendef\n\ndefine Build/buffalo-enc-tag\n\t$(call Build/buffalo-enc,'' '' -S 152 $(1))\nendef\n\ndefine Build/buffalo-tag-dhp\n\t$(eval product=$(word 1,$(1)))\n\t$(eval region=$(word 2,$(1)))\n\t$(eval language=$(word 3,$(1)))\n\t$(STAGING_DIR_HOST)/bin/buffalo-tag \\\n\t\t-d 0x01000000 -w 1 \\\n\t\t-a $(BUFFALO_TAG_PLATFORM) \\\n\t\t-v $(BUFFALO_TAG_VERSION) -m $(BUFFALO_TAG_MINOR) \\\n\t\t-b $(product) -p $(product) \\\n\t\t-r $(region) -r $(region) -l $(language) \\\n\t\t-I $@ -o $@.new\n\tmv $@.new $@\nendef\n\ndefine Build/check-size\n\t@imagesize=\"$$(stat -c%s $@)\"; \\\n\tlimitsize=\"$$(($(subst k,* 1024,$(subst m, * 1024k,$(if $(1),$(1),$(IMAGE_SIZE))))))\"; \\\n\t[ $$limitsize -ge $$imagesize ] || { \\\n\t\t$(call ERROR_MESSAGE,    WARNING: Image file $@ is too big: $$imagesize > $$limitsize); \\\n\t\trm -f $@; \\\n\t}\nendef\n\ndefine Build/copy-file\n\tcat \"$(1)\" > \"$@\"\nendef\n\ndefine Build/elecom-product-header\n\t$(eval product=$(word 1,$(1)))\n\t$(eval fw=$(if $(word 2,$(1)),$(word 2,$(1)),$@))\n\n\t( \\\n\t\techo -n -e \"ELECOM\\x00\\x00$(product)\" | dd bs=40 count=1 conv=sync; \\\n\t\techo -n \"0.00\" | dd bs=16 count=1 conv=sync; \\\n\t\tdd if=$(fw); \\\n\t) > $(fw).new\n\tmv $(fw).new $(fw)\nendef\n\ndefine Build/elecom-wrc-gs-factory\n\t$(eval product=$(word 1,$(1)))\n\t$(eval version=$(word 2,$(1)))\n\t$(eval hash_opt=$(word 3,$(1)))\n\t$(MKHASH) md5 $(hash_opt) $@ >> $@\n\t( \\\n\t\techo -n \"ELECOM $(product) v$(version)\" | \\\n\t\t\tdd bs=32 count=1 conv=sync; \\\n\t\tdd if=$@; \\\n\t) > $@.new\n\tmv $@.new $@\nendef\n\ndefine Build/elx-header\n\t$(eval hw_id=$(word 1,$(1)))\n\t$(eval xor_pattern=$(word 2,$(1)))\n\t( \\\n\t\techo -ne \"\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x03\" | \\\n\t\t\tdd bs=42 count=1 conv=sync; \\\n\t\thw_id=\"$(hw_id)\"; \\\n\t\techo -ne \"\\x$${hw_id:0:2}\\x$${hw_id:2:2}\\x$${hw_id:4:2}\\x$${hw_id:6:2}\" | \\\n\t\t\tdd bs=20 count=1 conv=sync; \\\n\t\techo -ne \"$$(printf '%08x' $$(stat -c%s $@) | fold -s2 | xargs -I {} echo \\\\x{} | tr -d '\\n')\" | \\\n\t\t\tdd bs=8 count=1 conv=sync; \\\n\t\techo -ne \"$$($(MKHASH) md5 $@ | fold -s2 | xargs -I {} echo \\\\x{} | tr -d '\\n')\" | \\\n\t\t\tdd bs=58 count=1 conv=sync; \\\n\t) > $(KDIR)/tmp/$(DEVICE_NAME).header\n\t$(call Build/xor-image,-p $(xor_pattern) -x)\n\tcat $(KDIR)/tmp/$(DEVICE_NAME).header $@ > $@.new\n\tmv $@.new $@\n\trm -rf $(KDIR)/tmp/$(DEVICE_NAME).header\nendef\n\ndefine Build/eva-image\n\t$(STAGING_DIR_HOST)/bin/lzma2eva $(KERNEL_LOADADDR) $(KERNEL_LOADADDR) $@ $@.new\n\tmv $@.new $@\nendef\n\ndefine Build/initrd_compression\n\t$(if $(CONFIG_TARGET_INITRAMFS_COMPRESSION_BZIP2),.bzip2) \\\n\t$(if $(CONFIG_TARGET_INITRAMFS_COMPRESSION_GZIP),.gzip) \\\n\t$(if $(CONFIG_TARGET_INITRAMFS_COMPRESSION_LZMA),.lzma) \\\n\t$(if $(CONFIG_TARGET_INITRAMFS_COMPRESSION_XZ),.xz) \\\n\t$(if $(CONFIG_TARGET_INITRAMFS_COMPRESSION_ZSTD),.zstd)\nendef\n\ndefine Build/fit\n\t$(TOPDIR)/scripts/mkits.sh \\\n\t\t-D $(DEVICE_NAME) -o $@.its -k $@ \\\n\t\t-C $(word 1,$(1)) $(if $(word 2,$(1)),\\\n\t\t$(if $(DEVICE_DTS_OVERLAY),-d $(KERNEL_BUILD_DIR)/image-$$(basename $(word 2,$(1))),\\\n\t\t\t-d $(word 2,$(1)))) \\\n\t\t$(if $(findstring with-rootfs,$(word 3,$(1))),-r $(IMAGE_ROOTFS)) \\\n\t\t$(if $(findstring with-initrd,$(word 3,$(1))), \\\n\t\t\t$(if $(CONFIG_TARGET_ROOTFS_INITRAMFS_SEPARATE), \\\n\t\t\t\t-i $(KERNEL_BUILD_DIR)/initrd.cpio$(strip $(call Build/initrd_compression)))) \\\n\t\t-a $(KERNEL_LOADADDR) -e $(if $(KERNEL_ENTRY),$(KERNEL_ENTRY),$(KERNEL_LOADADDR)) \\\n\t\t$(if $(DEVICE_FDT_NUM),-n $(DEVICE_FDT_NUM)) \\\n\t\t$(if $(DEVICE_DTS_DELIMITER),-l $(DEVICE_DTS_DELIMITER)) \\\n\t\t$(if $(DEVICE_DTS_OVERLAY),$(foreach dtso,$(DEVICE_DTS_OVERLAY), -O $(dtso):$(KERNEL_BUILD_DIR)/image-$(dtso).dtb)) \\\n\t\t-c $(if $(DEVICE_DTS_CONFIG),$(DEVICE_DTS_CONFIG),\"config-1\") \\\n\t\t-A $(LINUX_KARCH) -v $(LINUX_VERSION)\n\tPATH=$(LINUX_DIR)/scripts/dtc:$(PATH) mkimage $(if $(findstring external,$(word 3,$(1))),\\\n\t\t-E -B 0x1000 $(if $(findstring static,$(word 3,$(1))),-p 0x1000)) -f $@.its $@.new\n\t@mv $@.new $@\nendef\n\ndefine Build/gzip\n\tgzip -f -9n -c $@ $(1) > $@.new\n\t@mv $@.new $@\nendef\n\ndefine Build/install-dtb\n\t$(call locked, \\\n\t\t$(foreach dts,$(DEVICE_DTS), \\\n\t\t\t$(CP) \\\n\t\t\t\t$(DTS_DIR)/$(dts).dtb \\\n\t\t\t\t$(BIN_DIR)/$(IMG_PREFIX)-$(dts).dtb; \\\n\t\t), \\\n\t\tinstall-dtb-$(IMG_PREFIX) \\\n\t)\nendef\n\ndefine Build/iptime-crc32\n\t$(STAGING_DIR_HOST)/bin/iptime-crc32 $(1) $@ $@.new\n\tmv $@.new $@\nendef\n\ndefine Build/iptime-naspkg\n\t$(STAGING_DIR_HOST)/bin/iptime-naspkg $(1) $@ $@.new\n\tmv $@.new $@\nendef\n\ndefine Build/jffs2\n\trm -rf $(KDIR_TMP)/$(DEVICE_NAME)/jffs2 && \\\n\t\tmkdir -p $(KDIR_TMP)/$(DEVICE_NAME)/jffs2/$$(dirname $(1)) && \\\n\t\tcp $@ $(KDIR_TMP)/$(DEVICE_NAME)/jffs2/$(1) && \\\n\t\t$(STAGING_DIR_HOST)/bin/mkfs.jffs2 --pad \\\n\t\t\t$(if $(CONFIG_BIG_ENDIAN),--big-endian,--little-endian) \\\n\t\t\t--squash-uids -v -e $(patsubst %k,%KiB,$(BLOCKSIZE)) \\\n\t\t\t-o $@.new \\\n\t\t\t-d $(KDIR_TMP)/$(DEVICE_NAME)/jffs2 \\\n\t\t\t2>&1 1>/dev/null | awk '/^.+$$$$/' && \\\n\t\t$(STAGING_DIR_HOST)/bin/padjffs2 $@.new -J $(patsubst %k,,$(BLOCKSIZE))\n\t-rm -rf $(KDIR_TMP)/$(DEVICE_NAME)/jffs2/\n\t@mv $@.new $@\nendef\n\ndefine Build/kernel2minor\n\t$(eval temp_file := $(shell mktemp))\n\tcp $@ $(temp_file)\n\tkernel2minor -k $(temp_file) -r $(temp_file).new $(1)\n\tmv $(temp_file).new $@\n\trm -f $(temp_file)\nendef\n\ndefine Build/kernel-bin\n\trm -f $@\n\tcp $< $@\nendef\n\ndefine Build/linksys-image\n\t$(TOPDIR)/scripts/linksys-image.sh \\\n\t\t\"$(call param_get_default,type,$(1),$(DEVICE_NAME))\" \\\n\t\t$@ $@.new\n\t\tmv $@.new $@\nendef\n\ndefine Build/lzma\n\t$(call Build/lzma-no-dict,-lc1 -lp2 -pb2 $(1))\nendef\n\ndefine Build/lzma-no-dict\n\t$(STAGING_DIR_HOST)/bin/lzma e $@ $(1) $@.new\n\t@mv $@.new $@\nendef\n\ndefine Build/netgear-chk\n\t$(STAGING_DIR_HOST)/bin/mkchkimg \\\n\t\t-o $@.new \\\n\t\t-k $@ \\\n\t\t-b $(NETGEAR_BOARD_ID) \\\n\t\t$(if $(NETGEAR_REGION),-r $(NETGEAR_REGION),)\n\tmv $@.new $@\nendef\n\ndefine Build/netgear-dni\n\t$(STAGING_DIR_HOST)/bin/mkdniimg \\\n\t\t-B $(NETGEAR_BOARD_ID) -v $(VERSION_DIST).$(firstword $(subst -, ,$(REVISION))) \\\n\t\t$(if $(NETGEAR_HW_ID),-H $(NETGEAR_HW_ID)) \\\n\t\t-r \"$(1)\" \\\n\t\t-i $@ -o $@.new\n\tmv $@.new $@\nendef\n\ndefine Build/openmesh-image\n\t$(TOPDIR)/scripts/om-fwupgradecfg-gen.sh \\\n\t\t\"$(call param_get_default,ce_type,$(1),$(DEVICE_NAME))\" \\\n\t\t\"$@-fwupgrade.cfg\" \\\n\t\t\"$(call param_get_default,kernel,$(1),$(IMAGE_KERNEL))\" \\\n\t\t\"$(call param_get_default,rootfs,$(1),$@)\"\n\t$(TOPDIR)/scripts/combined-ext-image.sh \\\n\t\t\"$(call param_get_default,ce_type,$(1),$(DEVICE_NAME))\" \"$@\" \\\n\t\t\"$@-fwupgrade.cfg\" \"fwupgrade.cfg\" \\\n\t\t\"$(call param_get_default,kernel,$(1),$(IMAGE_KERNEL))\" \"kernel\" \\\n\t\t\"$(call param_get_default,rootfs,$(1),$@)\" \"rootfs\"\nendef\n\ndefine Build/pad-extra\n\tdd if=/dev/zero bs=$(1) count=1 >> $@\nendef\n\ndefine Build/pad-offset\n\tlet \\\n\t\tsize=\"$$(stat -c%s $@)\" \\\n\t\tpad=\"$(subst k,* 1024,$(word 1, $(1)))\" \\\n\t\toffset=\"$(subst k,* 1024,$(word 2, $(1)))\" \\\n\t\tpad=\"(pad - ((size + offset) % pad)) % pad\" \\\n\t\tnewsize='size + pad'; \\\n\t\tdd if=$@ of=$@.new bs=$$newsize count=1 conv=sync\n\tmv $@.new $@\nendef\n\ndefine Build/pad-rootfs\n\t$(STAGING_DIR_HOST)/bin/padjffs2 $@ $(1) \\\n\t\t$(if $(BLOCKSIZE),$(BLOCKSIZE:%k=%),4 8 16 64 128 256)\nendef\n\ndefine Build/pad-to\n\t$(call Image/pad-to,$@,$(1))\nendef\n\ndefine Build/patch-cmdline\n\t$(STAGING_DIR_HOST)/bin/patch-cmdline $@ '$(CMDLINE)'\nendef\n\n# Convert a raw image into a $1 type image.\n# E.g. | qemu-image vdi <optional extra arguments to qemu-img binary>\ndefine Build/qemu-image\n\tif command -v qemu-img; then \\\n\t\tqemu-img convert -f raw -O $1 $@ $@.new; \\\n\t\tmv $@.new $@; \\\n\telse \\\n\t\techo \"WARNING: Install qemu-img to create VDI/VMDK images\" >&2; exit 1; \\\n\tfi\nendef\n\ndefine Build/qsdk-ipq-factory-nand\n\t$(TOPDIR)/scripts/mkits-qsdk-ipq-image.sh \\\n\t\t$@.its ubi $@\n\tPATH=$(LINUX_DIR)/scripts/dtc:$(PATH) mkimage -f $@.its $@.new\n\t@mv $@.new $@\nendef\n\ndefine Build/qsdk-ipq-factory-nor\n\t$(TOPDIR)/scripts/mkits-qsdk-ipq-image.sh \\\n\t\t$@.its hlos $(IMAGE_KERNEL) rootfs $(IMAGE_ROOTFS)\n\tPATH=$(LINUX_DIR)/scripts/dtc:$(PATH) mkimage -f $@.its $@.new\n\t@mv $@.new $@\nendef\n\ndefine Build/seama\n\t$(STAGING_DIR_HOST)/bin/seama -i $@ \\\n\t\t-m \"dev=/dev/mtdblock/$(SEAMA_MTDBLOCK)\" -m \"type=firmware\"\n\tmv $@.seama $@\nendef\n\ndefine Build/seama-seal\n\t$(STAGING_DIR_HOST)/bin/seama -i $@ -s $@.seama \\\n\t\t-m \"signature=$(SEAMA_SIGNATURE)\"\n\tmv $@.seama $@\nendef\n\ndefine Build/senao-header\n\t$(STAGING_DIR_HOST)/bin/mksenaofw $(1) -e $@ -o $@.new\n\tmv $@.new $@\nendef\n\ndefine Build/sysupgrade-tar\n\tsh $(TOPDIR)/scripts/sysupgrade-tar.sh \\\n\t\t--board $(if $(BOARD_NAME),$(BOARD_NAME),$(DEVICE_NAME)) \\\n\t\t--kernel $(call param_get_default,kernel,$(1),$(IMAGE_KERNEL)) \\\n\t\t--rootfs $(call param_get_default,rootfs,$(1),$(IMAGE_ROOTFS)) \\\n\t\t$@\nendef\n\ndefine Build/tplink-safeloader\n\t-$(STAGING_DIR_HOST)/bin/tplink-safeloader \\\n\t\t-B $(TPLINK_BOARD_ID) \\\n\t\t-V $(REVISION) \\\n\t\t-k $(IMAGE_KERNEL) \\\n\t\t-r $@ \\\n\t\t-o $@.new \\\n\t\t-j \\\n\t\t$(wordlist 2,$(words $(1)),$(1)) \\\n\t\t$(if $(findstring sysupgrade,$(word 1,$(1))),-S) && mv $@.new $@ || rm -f $@\nendef\n\ndefine Build/tplink-v1-header\n\t$(STAGING_DIR_HOST)/bin/mktplinkfw \\\n\t\t-c -H $(TPLINK_HWID) -W $(TPLINK_HWREV) -L $(KERNEL_LOADADDR) \\\n\t\t-E $(if $(KERNEL_ENTRY),$(KERNEL_ENTRY),$(KERNEL_LOADADDR)) \\\n\t\t-m $(TPLINK_HEADER_VERSION) -N \"$(VERSION_DIST)\" -V $(REVISION) \\\n\t\t-k $@ -o $@.new $(1)\n\t@mv $@.new $@\nendef\n\n# combine kernel and rootfs into one image\n# mktplinkfw <type> <optional extra arguments to mktplinkfw binary>\n# <type> is \"sysupgrade\" or \"factory\"\n#\n# -a align the rootfs start on an <align> bytes boundary\n# -j add jffs2 end-of-filesystem markers\n# -s strip padding from end of the image\n# -X reserve <size> bytes in the firmware image (hexval prefixed with 0x)\ndefine Build/tplink-v1-image\n\t-$(STAGING_DIR_HOST)/bin/mktplinkfw \\\n\t\t-H $(TPLINK_HWID) -W $(TPLINK_HWREV) -F $(TPLINK_FLASHLAYOUT) \\\n\t\t-N \"$(VERSION_DIST)\" -V $(REVISION) -m $(TPLINK_HEADER_VERSION) \\\n\t\t-k $(IMAGE_KERNEL) -r $(IMAGE_ROOTFS) -o $@.new -j -X 0x40000 \\\n\t\t-a $(call rootfs_align,$(FILESYSTEM)) \\\n\t\t$(wordlist 2,$(words $(1)),$(1)) \\\n\t\t$(if $(findstring sysupgrade,$(word 1,$(1))),-s) && mv $@.new $@ || rm -f $@\nendef\n\ndefine Build/tplink-v2-header\n\t$(STAGING_DIR_HOST)/bin/mktplinkfw2 \\\n\t\t-c -H $(TPLINK_HWID) -W $(TPLINK_HWREV) -L $(KERNEL_LOADADDR) \\\n\t\t-E $(if $(KERNEL_ENTRY),$(KERNEL_ENTRY),$(KERNEL_LOADADDR))  \\\n\t\t-w $(TPLINK_HWREVADD) -F \"$(TPLINK_FLASHLAYOUT)\" \\\n\t\t-T $(TPLINK_HVERSION) -V \"ver. 2.0\" \\\n\t\t-k $@ -o $@.new $(1)\n\t@mv $@.new $@\nendef\n\ndefine Build/tplink-v2-image\n\t$(STAGING_DIR_HOST)/bin/mktplinkfw2 \\\n\t\t-H $(TPLINK_HWID) -W $(TPLINK_HWREV) \\\n\t\t-w $(TPLINK_HWREVADD) -F \"$(TPLINK_FLASHLAYOUT)\" \\\n\t\t-T $(TPLINK_HVERSION) -V \"ver. 2.0\" -a 0x4 -j \\\n\t\t-k $(IMAGE_KERNEL) -r $(IMAGE_ROOTFS) -o $@.new $(1)\n\tcat $@.new >> $@\n\trm -rf $@.new\nendef\n\ndefine Build/uImage\n\tmkimage \\\n\t\t-A $(LINUX_KARCH) \\\n\t\t-O linux \\\n\t\t-T kernel \\\n\t\t-C $(word 1,$(1)) \\\n\t\t-a $(KERNEL_LOADADDR) \\\n\t\t-e $(if $(KERNEL_ENTRY),$(KERNEL_ENTRY),$(KERNEL_LOADADDR)) \\\n\t\t-n '$(if $(UIMAGE_NAME),$(UIMAGE_NAME),$(call toupper,$(LINUX_KARCH)) $(VERSION_DIST) Linux-$(LINUX_VERSION))' \\\n\t\t$(if $(UIMAGE_MAGIC),-M $(UIMAGE_MAGIC)) \\\n\t\t$(wordlist 2,$(words $(1)),$(1)) \\\n\t\t-d $@ $@.new\n\tmv $@.new $@\nendef\n\ndefine Build/xor-image\n\t$(STAGING_DIR_HOST)/bin/xorimage -i $@ -o $@.xor $(1)\n\tmv $@.xor $@\nendef\n\ndefine Build/zip\n\trm -rf $@.tmp\n\tmkdir $@.tmp\n\tmv $@ $@.tmp/$(word 1,$(1))\n\tTZ=UTC $(STAGING_DIR_HOST)/bin/zip -j -X \\\n\t\t$(wordlist 2,$(words $(1)),$(1)) \\\n\t\t$@ $@.tmp/$(if $(word 1,$(1)),$(word 1,$(1)),$$(basename $@))\n\trm -rf $@.tmp\nendef\n\ndefine Build/zyxel-ras-image\n\tlet \\\n\t\tnewsize=\"$(subst k,* 1024,$(RAS_ROOTFS_SIZE))\"; \\\n\t\t$(STAGING_DIR_HOST)/bin/mkrasimage \\\n\t\t\t-b $(RAS_BOARD) \\\n\t\t\t-v $(RAS_VERSION) \\\n\t\t\t-r $@ \\\n\t\t\t-s $$newsize \\\n\t\t\t-o $@.new \\\n\t\t\t$(if $(findstring separate-kernel,$(word 1,$(1))),-k $(IMAGE_KERNEL)) \\\n\t\t&& mv $@.new $@\nendef\n"
  },
  {
    "path": "include/image.mk",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2006-2020 OpenWrt.org\n\noverride TARGET_BUILD=\ninclude $(INCLUDE_DIR)/prereq.mk\ninclude $(INCLUDE_DIR)/kernel.mk\ninclude $(INCLUDE_DIR)/version.mk\ninclude $(INCLUDE_DIR)/image-commands.mk\n\nifndef IB\n  ifdef CONFIG_TARGET_PER_DEVICE_ROOTFS\n    TARGET_PER_DEVICE_ROOTFS := 1\n  endif\nendif\n\ninclude $(INCLUDE_DIR)/feeds.mk\ninclude $(INCLUDE_DIR)/rootfs.mk\n\noverride MAKE:=$(_SINGLE)$(SUBMAKE)\noverride NO_TRACE_MAKE:=$(_SINGLE)$(NO_TRACE_MAKE)\n\ntarget_params = $(subst +,$(space),$*)\nparam_get = $(patsubst $(1)=%,%,$(filter $(1)=%,$(2)))\nparam_get_default = $(firstword $(call param_get,$(1),$(2)) $(3))\nparam_mangle = $(subst $(space),_,$(strip $(1)))\nparam_unmangle = $(subst _,$(space),$(1))\n\nmkfs_packages_id = $(shell echo $(sort $(1)) | $(MKHASH) md5 | cut -b1-8)\nmkfs_target_dir = $(if $(call param_get,pkg,$(1)),$(KDIR)/target-dir-$(call param_get,pkg,$(1)),$(TARGET_DIR))\n\nKDIR=$(KERNEL_BUILD_DIR)\nKDIR_TMP=$(KDIR)/tmp\nDTS_DIR:=$(LINUX_DIR)/arch/$(LINUX_KARCH)/boot/dts\n\nIMG_PREFIX_EXTRA:=$(if $(EXTRA_IMAGE_NAME),$(call sanitize,$(EXTRA_IMAGE_NAME))-)\nIMG_PREFIX_VERNUM:=$(if $(CONFIG_VERSION_FILENAMES),$(call sanitize,$(VERSION_NUMBER))-)\nIMG_PREFIX_VERCODE:=$(if $(CONFIG_VERSION_CODE_FILENAMES),$(call sanitize,$(VERSION_CODE))-)\n\nIMG_PREFIX:=$(VERSION_DIST_SANITIZED)-$(IMG_PREFIX_VERNUM)$(IMG_PREFIX_VERCODE)$(IMG_PREFIX_EXTRA)$(BOARD)$(if $(SUBTARGET),-$(SUBTARGET))\nIMG_ROOTFS:=$(IMG_PREFIX)-rootfs\nIMG_COMBINED:=$(IMG_PREFIX)-combined\nIMG_PART_SIGNATURE:=$(shell echo $(SOURCE_DATE_EPOCH)$(LINUX_VERMAGIC) | $(MKHASH) md5 | cut -b1-8)\nIMG_PART_DISKGUID:=$(shell echo $(SOURCE_DATE_EPOCH)$(LINUX_VERMAGIC) | $(MKHASH) md5 | sed -E 's/(.{8})(.{4})(.{4})(.{4})(.{10})../\\1-\\2-\\3-\\4-\\500/')\n\nMKFS_DEVTABLE_OPT := -D $(INCLUDE_DIR)/device_table.txt\n\nifneq ($(CONFIG_BIG_ENDIAN),)\n  JFFS2OPTS     :=  --big-endian --squash-uids -v\nelse\n  JFFS2OPTS     :=  --little-endian --squash-uids -v\nendif\n\nifeq ($(CONFIG_JFFS2_RTIME),y)\n  JFFS2OPTS += -X rtime\nendif\nifeq ($(CONFIG_JFFS2_ZLIB),y)\n  JFFS2OPTS += -X zlib\nendif\nifeq ($(CONFIG_JFFS2_LZMA),y)\n  JFFS2OPTS += -X lzma --compression-mode=size\nendif\nifneq ($(CONFIG_JFFS2_RTIME),y)\n  JFFS2OPTS += -x rtime\nendif\nifneq ($(CONFIG_JFFS2_ZLIB),y)\n  JFFS2OPTS += -x zlib\nendif\nifneq ($(CONFIG_JFFS2_LZMA),y)\n  JFFS2OPTS += -x lzma\nendif\n\nJFFS2OPTS += $(MKFS_DEVTABLE_OPT)\n\nSQUASHFS_BLOCKSIZE := $(CONFIG_TARGET_SQUASHFS_BLOCK_SIZE)k\nSQUASHFSOPT := -b $(SQUASHFS_BLOCKSIZE)\nSQUASHFSOPT += -p '/dev d 755 0 0' -p '/dev/console c 600 0 0 5 1'\nSQUASHFSOPT += $(if $(CONFIG_SELINUX),-xattrs,-no-xattrs)\nSQUASHFSCOMP := gzip\nLZMA_XZ_OPTIONS := -Xpreset 9 -Xe -Xlc 0 -Xlp 2 -Xpb 2\nifeq ($(CONFIG_SQUASHFS_XZ),y)\n  ifneq ($(filter arm x86 powerpc sparc,$(LINUX_KARCH)),)\n    BCJ_FILTER:=-Xbcj $(LINUX_KARCH)\n  endif\n  SQUASHFSCOMP := xz $(LZMA_XZ_OPTIONS) $(BCJ_FILTER)\nendif\n\nJFFS2_BLOCKSIZE ?= 64k 128k\n\nfs-types-$(CONFIG_TARGET_ROOTFS_SQUASHFS) += squashfs\nfs-types-$(CONFIG_TARGET_ROOTFS_JFFS2) += $(addprefix jffs2-,$(JFFS2_BLOCKSIZE))\nfs-types-$(CONFIG_TARGET_ROOTFS_JFFS2_NAND) += $(addprefix jffs2-nand-,$(NAND_BLOCKSIZE))\nfs-types-$(CONFIG_TARGET_ROOTFS_EXT4FS) += ext4\nfs-types-$(CONFIG_TARGET_ROOTFS_UBIFS) += ubifs\nfs-subtypes-$(CONFIG_TARGET_ROOTFS_JFFS2) += $(addsuffix -raw,$(addprefix jffs2-,$(JFFS2_BLOCKSIZE)))\n\nTARGET_FILESYSTEMS := $(fs-types-y)\n\nFS_64K := $(filter-out jffs2-%,$(TARGET_FILESYSTEMS)) jffs2-64k\nFS_128K := $(filter-out jffs2-%,$(TARGET_FILESYSTEMS)) jffs2-128k\nFS_256K := $(filter-out jffs2-%,$(TARGET_FILESYSTEMS)) jffs2-256k\n\ndefine add_jffs2_mark\n\techo -ne '\\xde\\xad\\xc0\\xde' >> $(1)\nendef\n\nPROFILE_SANITIZED := $(call tolower,$(subst DEVICE_,,$(subst $(space),-,$(PROFILE))))\n\ndefine split_args\n$(foreach data, \\\n\t$(subst |,$(space),\\\n\t\t$(subst $(space),^,$(1))), \\\n\t$(call $(2),$(strip $(subst ^,$(space),$(data)))))\nendef\n\ndefine build_cmd\n$(if $(Build/$(word 1,$(1))),,$(error Missing Build/$(word 1,$(1))))\n$(call Build/$(word 1,$(1)),$(wordlist 2,$(words $(1)),$(1)))\n\nendef\n\ndefine concat_cmd\n$(call split_args,$(1),build_cmd)\nendef\n\n# pad to 4k, 8k, 16k, 64k, 128k, 256k and add jffs2 end-of-filesystem mark\ndefine prepare_generic_squashfs\n\t$(STAGING_DIR_HOST)/bin/padjffs2 $(1) 4 8 16 64 128 256\nendef\n\ndefine Image/BuildKernel/Initramfs\n\t$(call Image/Build/Initramfs)\nendef\n\ndefine Image/BuildKernel/MkuImage\n\tmkimage -A $(ARCH) -O linux -T kernel -C $(1) -a $(2) -e $(3) \\\n\t\t-n '$(call toupper,$(ARCH)) $(VERSION_DIST) Linux-$(LINUX_VERSION)' -d $(4) $(5)\nendef\n\nifdef CONFIG_TARGET_IMAGES_GZIP\n  define Image/Gzip\n\trm -f $(1).gz\n\tgzip -9n $(1)\n  endef\nendif\n\n\n# Disable noisy checks by default as in upstream\nDTC_FLAGS += \\\n  -Wno-unit_address_vs_reg \\\n  -Wno-simple_bus_reg \\\n  -Wno-unit_address_format \\\n  -Wno-pci_bridge \\\n  -Wno-pci_device_bus_num \\\n  -Wno-pci_device_reg \\\n  -Wno-avoid_unnecessary_addr_size \\\n  -Wno-alias_paths \\\n  -Wno-graph_child_address \\\n  -Wno-graph_port \\\n  -Wno-unique_unit_address\n\ndefine Image/pad-to\n\tdd if=$(1) of=$(1).new bs=$(2) conv=sync\n\tmv $(1).new $(1)\nendef\n\nROOTFS_PARTSIZE=$(shell echo $$(($(CONFIG_TARGET_ROOTFS_PARTSIZE)*1024*1024)))\n\ndefine Image/pad-root-squashfs\n\t$(call Image/pad-to,$(KDIR)/root.squashfs,$(if $(1),$(1),$(ROOTFS_PARTSIZE)))\nendef\n\n# $(1) source dts file\n# $(2) target dtb file\n# $(3) extra CPP flags\n# $(4) extra DTC flags\ndefine Image/BuildDTB\n\t$(TARGET_CROSS)cpp -nostdinc -x assembler-with-cpp \\\n\t\t$(DTS_CPPFLAGS) \\\n\t\t-I$(DTS_DIR) \\\n\t\t-I$(DTS_DIR)/include \\\n\t\t-I$(LINUX_DIR)/include/ \\\n\t\t-undef -D__DTS__ $(3) \\\n\t\t-o $(2).tmp $(1)\n\t$(LINUX_DIR)/scripts/dtc/dtc -O dtb \\\n\t\t-i$(dir $(1)) $(DTC_FLAGS) $(4) \\\n\t$(if $(CONFIG_HAS_DT_OVERLAY_SUPPORT),-@) \\\n\t\t-o $(2) $(2).tmp\n\t$(RM) $(2).tmp\nendef\n\ndefine Image/mkfs/jffs2/sub-raw\n\t$(STAGING_DIR_HOST)/bin/mkfs.jffs2 \\\n\t\t$(2) \\\n\t\t-e $(patsubst %k,%KiB,$(1)) \\\n\t\t-o $@ -d $(call mkfs_target_dir,$(3)) \\\n\t\t-v 2>&1 1>/dev/null | awk '/^.+$$$$/'\nendef\n\ndefine Image/mkfs/jffs2/sub\n\t$(call Image/mkfs/jffs2/sub-raw,$(1),--pad $(2),$(3))\n\t$(call add_jffs2_mark,$@)\nendef\n\ndefine Image/mkfs/jffs2/template\n  Image/mkfs/jffs2-$(1) = $$(call Image/mkfs/jffs2/sub,$(1),$(JFFS2OPTS),$$(1))\n  Image/mkfs/jffs2-$(1)-raw = $$(call Image/mkfs/jffs2/sub-raw,$(1),$(JFFS2OPTS),$$(1))\n\nendef\n\ndefine Image/mkfs/jffs2-nand/template\n  Image/mkfs/jffs2-nand-$(1) = \\\n\t$$(call Image/mkfs/jffs2/sub, \\\n\t\t$(word 2,$(subst -, ,$(1))), \\\n\t\t\t$(JFFS2OPTS) --no-cleanmarkers --pagesize=$(word 1,$(subst -, ,$(1))),$$(1))\n\nendef\n\n$(eval $(foreach S,$(JFFS2_BLOCKSIZE),$(call Image/mkfs/jffs2/template,$(S))))\n$(eval $(foreach S,$(NAND_BLOCKSIZE),$(call Image/mkfs/jffs2-nand/template,$(S))))\n\ndefine Image/mkfs/squashfs-common\n\t$(STAGING_DIR_HOST)/bin/mksquashfs4 $(call mkfs_target_dir,$(1)) $@ \\\n\t\t-nopad -noappend -root-owned \\\n\t\t-comp $(SQUASHFSCOMP) $(SQUASHFSOPT)\nendef\n\nifeq ($(CONFIG_TARGET_ROOTFS_SECURITY_LABELS),y)\ndefine Image/mkfs/squashfs\n\techo \". $(call mkfs_target_dir,$(1))/etc/selinux/config\" > $@.fakeroot-script\n\techo \"$(STAGING_DIR_HOST)/bin/setfiles -r\" \\\n\t     \"$(call mkfs_target_dir,$(1))\" \\\n\t     \"$(call mkfs_target_dir,$(1))/etc/selinux/\\$${SELINUXTYPE}/contexts/files/file_contexts \" \\\n\t     \"$(call mkfs_target_dir,$(1))\" >> $@.fakeroot-script\n\techo \"$(Image/mkfs/squashfs-common)\" >> $@.fakeroot-script\n\tchmod +x $@.fakeroot-script\n\t$(FAKEROOT) \"$@.fakeroot-script\"\nendef\nelse\ndefine Image/mkfs/squashfs\n\t$(call Image/mkfs/squashfs-common,$(1))\nendef\nendif\n\ndefine Image/mkfs/ubifs\n\t$(STAGING_DIR_HOST)/bin/mkfs.ubifs \\\n\t\t$(UBIFS_OPTS) $(call param_unmangle,$(call param_get,fs,$(1))) \\\n\t\t$(if $(CONFIG_TARGET_UBIFS_FREE_SPACE_FIXUP),--space-fixup) \\\n\t\t$(if $(CONFIG_TARGET_UBIFS_COMPRESSION_NONE),--compr=none) \\\n\t\t$(if $(CONFIG_TARGET_UBIFS_COMPRESSION_LZO),--compr=lzo) \\\n\t\t$(if $(CONFIG_TARGET_UBIFS_COMPRESSION_ZLIB),--compr=zlib) \\\n\t\t$(if $(shell echo $(CONFIG_TARGET_UBIFS_JOURNAL_SIZE)),--jrn-size=$(CONFIG_TARGET_UBIFS_JOURNAL_SIZE)) \\\n\t\t--squash-uids \\\n\t\t-o $@ -d $(call mkfs_target_dir,$(1))\nendef\n\ndefine Image/mkfs/ext4\n\t$(STAGING_DIR_HOST)/bin/make_ext4fs -L rootfs \\\n\t\t-l $(ROOTFS_PARTSIZE) -b $(CONFIG_TARGET_EXT4_BLOCKSIZE) \\\n\t\t$(if $(CONFIG_TARGET_EXT4_RESERVED_PCT),-m $(CONFIG_TARGET_EXT4_RESERVED_PCT)) \\\n\t\t$(if $(CONFIG_TARGET_EXT4_JOURNAL),,-J) \\\n\t\t$(if $(SOURCE_DATE_EPOCH),-T $(SOURCE_DATE_EPOCH)) \\\n\t\t$@ $(call mkfs_target_dir,$(1))/\nendef\n\ndefine Image/Manifest\n\t$(call opkg,$(TARGET_DIR_ORIG)) list-installed > \\\n\t\t$(BIN_DIR)/$(IMG_PREFIX)$(if $(PROFILE_SANITIZED),-$(PROFILE_SANITIZED)).manifest\nendef\n\ndefine Image/gzip-ext4-padded-squashfs\n\n  define Image/Build/squashfs\n    $(call Image/pad-root-squashfs)\n  endef\n\n  ifneq ($(CONFIG_TARGET_IMAGES_GZIP),)\n    define Image/Build/gzip/ext4\n      $(call Image/Build/gzip,ext4)\n    endef\n    define Image/Build/gzip/squashfs\n      $(call Image/Build/gzip,squashfs)\n    endef\n  endif\n\nendef\n\nifdef CONFIG_TARGET_ROOTFS_TARGZ\n  define Image/Build/targz\n\t$(TAR) -cp --numeric-owner --owner=0 --group=0 --mode=a-s --sort=name \\\n\t\t$(if $(SOURCE_DATE_EPOCH),--mtime=\"@$(SOURCE_DATE_EPOCH)\") \\\n\t\t-C $(TARGET_DIR)/ . | gzip -9n > $(BIN_DIR)/$(IMG_PREFIX)$(if $(PROFILE_SANITIZED),-$(PROFILE_SANITIZED))-rootfs.tar.gz\n  endef\nendif\n\nifdef CONFIG_TARGET_ROOTFS_CPIOGZ\n  define Image/Build/cpiogz\n\t( cd $(TARGET_DIR); find . | $(STAGING_DIR_HOST)/bin/cpio -o -H newc -R 0:0 | gzip -9n >$(BIN_DIR)/$(IMG_ROOTFS).cpio.gz )\n  endef\nendif\n\nmkfs_packages = $(filter-out @%,$(PACKAGES_$(call param_get,pkg,pkg=$(target_params))))\nmkfs_packages_add = $(foreach pkg,$(filter-out -%,$(mkfs_packages)),$(pkg)$(call GetABISuffix,$(pkg)))\nmkfs_packages_remove = $(foreach pkg,$(patsubst -%,%,$(filter -%,$(mkfs_packages))),$(pkg)$(call GetABISuffix,$(pkg)))\nmkfs_cur_target_dir = $(call mkfs_target_dir,pkg=$(target_params))\n\nopkg_target = \\\n\t$(call opkg,$(mkfs_cur_target_dir)) \\\n\t\t-f $(mkfs_cur_target_dir).conf\n\ntarget-dir-%: FORCE\n\trm -rf $(mkfs_cur_target_dir) $(mkfs_cur_target_dir).opkg\n\t$(CP) $(TARGET_DIR_ORIG) $(mkfs_cur_target_dir)\n\t-mv $(mkfs_cur_target_dir)/etc/opkg $(mkfs_cur_target_dir).opkg\n\techo 'src default file://$(PACKAGE_DIR_ALL)' > $(mkfs_cur_target_dir).conf\n\t$(if $(mkfs_packages_remove), \\\n\t\t-$(call opkg,$(mkfs_cur_target_dir)) remove \\\n\t\t\t$(mkfs_packages_remove))\n\t$(if $(call opkg_package_files,$(mkfs_packages_add)), \\\n\t\t$(opkg_target) update && \\\n\t\t$(opkg_target) install \\\n\t\t\t$(call opkg_package_files,$(mkfs_packages_add)))\n\t-$(CP) -T $(mkfs_cur_target_dir).opkg/ $(mkfs_cur_target_dir)/etc/opkg/\n\trm -rf $(mkfs_cur_target_dir).opkg $(mkfs_cur_target_dir).conf\n\t$(call prepare_rootfs,$(mkfs_cur_target_dir),$(TOPDIR)/files)\n\n$(KDIR)/root.%: kernel_prepare\n\t$(call Image/mkfs/$(word 1,$(target_params)),$(target_params))\n\ndefine Device/InitProfile\n  PROFILES := $(PROFILE)\n  DEVICE_TITLE = $$(DEVICE_VENDOR) $$(DEVICE_MODEL)$$(if $$(DEVICE_VARIANT), $$(DEVICE_VARIANT))\n  DEVICE_ALT0_TITLE = $$(DEVICE_ALT0_VENDOR) $$(DEVICE_ALT0_MODEL)$$(if $$(DEVICE_ALT0_VARIANT), $$(DEVICE_ALT0_VARIANT))\n  DEVICE_ALT1_TITLE = $$(DEVICE_ALT1_VENDOR) $$(DEVICE_ALT1_MODEL)$$(if $$(DEVICE_ALT1_VARIANT), $$(DEVICE_ALT1_VARIANT))\n  DEVICE_ALT2_TITLE = $$(DEVICE_ALT2_VENDOR) $$(DEVICE_ALT2_MODEL)$$(if $$(DEVICE_ALT2_VARIANT), $$(DEVICE_ALT2_VARIANT))\n  DEVICE_VENDOR :=\n  DEVICE_MODEL :=\n  DEVICE_VARIANT :=\n  DEVICE_ALT0_VENDOR :=\n  DEVICE_ALT0_MODEL :=\n  DEVICE_ALT0_VARIANT :=\n  DEVICE_ALT1_VENDOR :=\n  DEVICE_ALT1_MODEL :=\n  DEVICE_ALT1_VARIANT :=\n  DEVICE_ALT2_VENDOR :=\n  DEVICE_ALT2_MODEL :=\n  DEVICE_ALT2_VARIANT :=\n  DEVICE_PACKAGES :=\n  DEVICE_DESCRIPTION = Build firmware images for $$(DEVICE_TITLE)\nendef\n\ndefine Device/Init\n  DEVICE_NAME := $(1)\n  KERNEL:=\n  KERNEL_INITRAMFS = $$(KERNEL)\n  CMDLINE:=\n\n  IMAGES :=\n  ARTIFACTS :=\n  DEVICE_IMG_PREFIX := $(IMG_PREFIX)-$(1)\n  DEVICE_IMG_NAME = $$(DEVICE_IMG_PREFIX)-$$(1)-$$(2)\n  IMAGE_SIZE :=\n  KERNEL_PREFIX = $$(DEVICE_IMG_PREFIX)\n  KERNEL_SUFFIX := -kernel.bin\n  KERNEL_INITRAMFS_SUFFIX = $$(KERNEL_SUFFIX)\n  KERNEL_IMAGE = $$(KERNEL_PREFIX)$$(KERNEL_SUFFIX)\n  KERNEL_INITRAMFS_PREFIX = $$(DEVICE_IMG_PREFIX)-initramfs\n  KERNEL_INITRAMFS_IMAGE = $$(KERNEL_INITRAMFS_PREFIX)$$(KERNEL_INITRAMFS_SUFFIX)\n  KERNEL_INITRAMFS_NAME = $$(KERNEL_NAME)-initramfs\n  KERNEL_INSTALL :=\n  KERNEL_NAME := vmlinux\n  KERNEL_DEPENDS :=\n  KERNEL_SIZE :=\n\n  UBOOTENV_IN_UBI :=\n  KERNEL_IN_UBI :=\n  BLOCKSIZE :=\n  PAGESIZE :=\n  SUBPAGESIZE :=\n  VID_HDR_OFFSET :=\n  UBINIZE_OPTS :=\n  UBINIZE_PARTS :=\n  MKUBIFS_OPTS :=\n\n  FS_OPTIONS/ubifs = $$(MKUBIFS_OPTS)\n\n  DEVICE_DTS :=\n  DEVICE_DTS_CONFIG :=\n  DEVICE_DTS_DELIMITER :=\n  DEVICE_DTS_DIR :=\n  DEVICE_DTS_OVERLAY :=\n  DEVICE_FDT_NUM :=\n  SOC :=\n\n  BOARD_NAME :=\n  UIMAGE_MAGIC :=\n  UIMAGE_NAME :=\n  DEVICE_COMPAT_VERSION := 1.0\n  DEVICE_COMPAT_MESSAGE :=\n  SUPPORTED_DEVICES := $(subst _,$(comma),$(1))\n  IMAGE_METADATA :=\n\n  FILESYSTEMS := $(TARGET_FILESYSTEMS)\n\n  UBOOT_PATH :=  $(STAGING_DIR_IMAGE)/uboot-$(1)\n\n  BROKEN :=\n  DEFAULT :=\nendef\n\nDEFAULT_DEVICE_VARS := \\\n  DEVICE_NAME KERNEL KERNEL_INITRAMFS KERNEL_INITRAMFS_IMAGE KERNEL_SIZE \\\n  CMDLINE UBOOTENV_IN_UBI KERNEL_IN_UBI BLOCKSIZE PAGESIZE SUBPAGESIZE \\\n  VID_HDR_OFFSET UBINIZE_OPTS UBINIZE_PARTS MKUBIFS_OPTS DEVICE_DTS \\\n  DEVICE_DTS_CONFIG DEVICE_DTS_DELIMITER DEVICE_DTS_DIR DEVICE_DTS_OVERLAY \\\n  DEVICE_FDT_NUM DEVICE_IMG_PREFIX SOC BOARD_NAME UIMAGE_MAGIC UIMAGE_NAME \\\n  SUPPORTED_DEVICES IMAGE_METADATA KERNEL_ENTRY KERNEL_LOADADDR \\\n  UBOOT_PATH IMAGE_SIZE \\\n  DEVICE_PACKAGES DEVICE_COMPAT_VERSION DEVICE_COMPAT_MESSAGE \\\n  DEVICE_VENDOR DEVICE_MODEL DEVICE_VARIANT \\\n  DEVICE_ALT0_VENDOR DEVICE_ALT0_MODEL DEVICE_ALT0_VARIANT \\\n  DEVICE_ALT1_VENDOR DEVICE_ALT1_MODEL DEVICE_ALT1_VARIANT \\\n  DEVICE_ALT2_VENDOR DEVICE_ALT2_MODEL DEVICE_ALT2_VARIANT\n\ndefine Device/ExportVar\n  $(1) : $(2):=$$($(2))\n\nendef\ndefine Device/Export\n  $(foreach var,$(DEVICE_VARS) $(DEFAULT_DEVICE_VARS),$(call Device/ExportVar,$(1),$(var)))\n  $(1) : FILESYSTEM:=$(2)\nendef\n\nifdef IB\n  DEVICE_CHECK_PROFILE = $(filter $(1),DEVICE_$(PROFILE) $(PROFILE))\nelse\n  DEVICE_CHECK_PROFILE = $(CONFIG_TARGET_$(if $(CONFIG_TARGET_MULTI_PROFILE),DEVICE_)$(call target_conf,$(BOARD)$(if $(SUBTARGET),_$(SUBTARGET)))_$(1))\nendif\n\nDEVICE_EXTRA_PACKAGES = $(call qstrip,$(CONFIG_TARGET_DEVICE_PACKAGES_$(call target_conf,$(BOARD)$(if $(SUBTARGET),_$(SUBTARGET)))_DEVICE_$(1)))\n\ndefine merge_packages\n  $(1) :=\n  $(foreach pkg,$(2),\n    $(1) := $$(strip $$(filter-out -$$(patsubst -%,%,$(pkg)) $$(patsubst -%,%,$(pkg)),$$($(1))) $(pkg))\n  )\nendef\n\ndefine Device/Check/Common\n  _PROFILE_SET = $$(strip $$(foreach profile,$$(PROFILES) DEVICE_$(1),$$(call DEVICE_CHECK_PROFILE,$$(profile))))\n  DEVICE_PACKAGES += $$(call extra_packages,$$(DEVICE_PACKAGES))\n  ifdef TARGET_PER_DEVICE_ROOTFS\n    $$(eval $$(call merge_packages,_PACKAGES,$$(DEVICE_PACKAGES) $$(call DEVICE_EXTRA_PACKAGES,$(1))))\n    ROOTFS_ID/$(1) := $$(if $$(_PROFILE_SET),$$(call mkfs_packages_id,$$(_PACKAGES)))\n    PACKAGES_$$(ROOTFS_ID/$(1)) := $$(_PACKAGES)\n  endif\nendef\n\ndefine Device/Check\n  $(Device/Check/Common)\n  KDIR_KERNEL_IMAGE := $(KDIR)/$(1)$$(KERNEL_SUFFIX)\n  _TARGET := $$(if $$(_PROFILE_SET),install-images,install-disabled)\n  ifndef IB\n    _COMPILE_TARGET := $$(if $(CONFIG_IB)$$(_PROFILE_SET),compile,compile-disabled)\n  endif\nendef\n\nifndef IB\ndefine Device/Build/initramfs\n  $(call Device/Export,$(KDIR)/tmp/$$(KERNEL_INITRAMFS_IMAGE),$(1))\n  $$(_TARGET): $$(if $$(KERNEL_INITRAMFS),$(BIN_DIR)/$$(KERNEL_INITRAMFS_IMAGE) \\\n\t  $$(if $$(CONFIG_JSON_OVERVIEW_IMAGE_INFO), $(BUILD_DIR)/json_info_files/$$(KERNEL_INITRAMFS_IMAGE).json,))\n\n  $(KDIR)/$$(KERNEL_INITRAMFS_NAME):: image_prepare\n  $(1)-images: $$(if $$(KERNEL_INITRAMFS),$(BIN_DIR)/$$(KERNEL_INITRAMFS_IMAGE))\n  $(BIN_DIR)/$$(KERNEL_INITRAMFS_IMAGE): $(KDIR)/tmp/$$(KERNEL_INITRAMFS_IMAGE)\n\tcp $$^ $$@\n\n  $(KDIR)/tmp/$$(KERNEL_INITRAMFS_IMAGE): $(KDIR)/$$(KERNEL_INITRAMFS_NAME) $(CURDIR)/Makefile $$(KERNEL_DEPENDS) image_prepare\n\t@rm -f $$@\n\t$$(call concat_cmd,$$(KERNEL_INITRAMFS))\n\n  $(call Device/Export,$(BUILD_DIR)/json_info_files/$$(KERNEL_INITRAMFS_IMAGE).json,$(1))\n\n  $(BUILD_DIR)/json_info_files/$$(KERNEL_INITRAMFS_IMAGE).json: $(BIN_DIR)/$$(KERNEL_INITRAMFS_IMAGE)\n\t@mkdir -p $$(shell dirname $$@)\n\tDEVICE_ID=\"$(1)\" \\\n\tSOURCE_DATE_EPOCH=$(SOURCE_DATE_EPOCH) \\\n\tFILE_NAME=\"$$(notdir $$^)\" \\\n\tFILE_DIR=\"$(KDIR)/tmp\" \\\n\tFILE_TYPE=\"kernel\" \\\n\tFILE_FILESYSTEM=\"initramfs\" \\\n\tDEVICE_IMG_PREFIX=\"$$(DEVICE_IMG_PREFIX)\" \\\n\tDEVICE_VENDOR=\"$$(DEVICE_VENDOR)\" \\\n\tDEVICE_MODEL=\"$$(DEVICE_MODEL)\" \\\n\tDEVICE_VARIANT=\"$$(DEVICE_VARIANT)\" \\\n\tDEVICE_ALT0_VENDOR=\"$$(DEVICE_ALT0_VENDOR)\" \\\n\tDEVICE_ALT0_MODEL=\"$$(DEVICE_ALT0_MODEL)\" \\\n\tDEVICE_ALT0_VARIANT=\"$$(DEVICE_ALT0_VARIANT)\" \\\n\tDEVICE_ALT1_VENDOR=\"$$(DEVICE_ALT1_VENDOR)\" \\\n\tDEVICE_ALT1_MODEL=\"$$(DEVICE_ALT1_MODEL)\" \\\n\tDEVICE_ALT1_VARIANT=\"$$(DEVICE_ALT1_VARIANT)\" \\\n\tDEVICE_ALT2_VENDOR=\"$$(DEVICE_ALT2_VENDOR)\" \\\n\tDEVICE_ALT2_MODEL=\"$$(DEVICE_ALT2_MODEL)\" \\\n\tDEVICE_ALT2_VARIANT=\"$$(DEVICE_ALT2_VARIANT)\" \\\n\tDEVICE_TITLE=\"$$(DEVICE_TITLE)\" \\\n\tDEVICE_PACKAGES=\"$$(DEVICE_PACKAGES)\" \\\n\tTARGET=\"$(BOARD)\" \\\n\tSUBTARGET=\"$(if $(SUBTARGET),$(SUBTARGET),generic)\" \\\n\tVERSION_NUMBER=\"$(VERSION_NUMBER)\" \\\n\tVERSION_CODE=\"$(VERSION_CODE)\" \\\n\tSUPPORTED_DEVICES=\"$$(SUPPORTED_DEVICES)\" \\\n\t$(TOPDIR)/scripts/json_add_image_info.py $$@\nendef\nendif\n\ndefine Device/Build/compile\n  $$(_COMPILE_TARGET): $(KDIR)/$(1)\n  $(eval $(call Device/Export,$(KDIR)/$(1)))\n  $(KDIR)/$(1):\n\t$$(call concat_cmd,$(COMPILE/$(1)))\n\nendef\n\nifndef IB\ndefine Device/Build/dtb\n  ifndef BUILD_DTS_$(1)\n  BUILD_DTS_$(1) := 1\n  $(KDIR)/image-$(1).dtb: FORCE\n\t$(call Image/BuildDTB,$(strip $(2))/$(strip $(3)).dts,$$@)\n\n  image_prepare: $(KDIR)/image-$(1).dtb\n  endif\n\nendef\nendif\n\ndefine Device/Build/kernel\n  $$(eval $$(foreach dts,$$(DEVICE_DTS) $$(DEVICE_DTS_OVERLAY), \\\n\t$$(call Device/Build/dtb,$$(notdir $$(dts)), \\\n\t\t$$(if $$(DEVICE_DTS_DIR),$$(DEVICE_DTS_DIR),$$(DTS_DIR)), \\\n\t\t$$(dts) \\\n\t) \\\n  ))\n\n  $(KDIR)/$$(KERNEL_NAME):: image_prepare\n  $$(_TARGET): $$(if $$(KERNEL_INSTALL),$(BIN_DIR)/$$(KERNEL_IMAGE))\n  $(call Device/Export,$$(KDIR_KERNEL_IMAGE),$(1))\n  $(BIN_DIR)/$$(KERNEL_IMAGE): $$(KDIR_KERNEL_IMAGE)\n\tcp $$^ $$@\n  ifndef IB\n    ifdef CONFIG_IB\n      install: $$(KDIR_KERNEL_IMAGE)\n    endif\n    $$(KDIR_KERNEL_IMAGE): $(KDIR)/$$(KERNEL_NAME) $(CURDIR)/Makefile $$(KERNEL_DEPENDS) image_prepare\n\t@rm -f $$@\n\t$$(call concat_cmd,$$(KERNEL))\n\t$$(if $$(KERNEL_SIZE),$$(call Build/check-size,$$(KERNEL_SIZE)))\n  endif\nendef\n\ndefine Device/Build/image\n  GZ_SUFFIX := $(if $(filter %dtb %gz,$(2)),,$(if $(and $(findstring ext4,$(1)),$(CONFIG_TARGET_IMAGES_GZIP)),.gz))\n  $$(_TARGET): $(if $(CONFIG_JSON_OVERVIEW_IMAGE_INFO), \\\n\t  $(BUILD_DIR)/json_info_files/$(call DEVICE_IMG_NAME,$(1),$(2)).json, \\\n\t  $(BIN_DIR)/$(call DEVICE_IMG_NAME,$(1),$(2))$$(GZ_SUFFIX))\n  $(eval $(call Device/Export,$(KDIR)/tmp/$(call DEVICE_IMG_NAME,$(1),$(2)),$(1)))\n  $(3)-images: $(BIN_DIR)/$(call DEVICE_IMG_NAME,$(1),$(2))$$(GZ_SUFFIX)\n\n  ROOTFS/$(1)/$(3) := \\\n\t$(KDIR)/root.$(1)$$(strip \\\n\t\t$$(if $$(FS_OPTIONS/$(1)),+fs=$$(call param_mangle,$$(FS_OPTIONS/$(1)))) \\\n\t)$$(strip \\\n\t\t$(if $(TARGET_PER_DEVICE_ROOTFS),+pkg=$$(ROOTFS_ID/$(3))) \\\n\t)\n  ifndef IB\n    $$(ROOTFS/$(1)/$(3)): $(if $(TARGET_PER_DEVICE_ROOTFS),target-dir-$$(ROOTFS_ID/$(3)))\n  endif\n  $(KDIR)/tmp/$(call DEVICE_IMG_NAME,$(1),$(2)): $$(KDIR_KERNEL_IMAGE) $$(ROOTFS/$(1)/$(3))\n\t@rm -f $$@\n\t[ -f $$(word 1,$$^) -a -f $$(word 2,$$^) ]\n\t$$(call concat_cmd,$(if $(IMAGE/$(2)/$(1)),$(IMAGE/$(2)/$(1)),$(IMAGE/$(2))))\n\n  .IGNORE: $(BIN_DIR)/$(call DEVICE_IMG_NAME,$(1),$(2))\n\n  $(BIN_DIR)/$(call DEVICE_IMG_NAME,$(1),$(2)).gz: $(KDIR)/tmp/$(call DEVICE_IMG_NAME,$(1),$(2))\n\tgzip -c -9n $$^ > $$@\n\n  $(BIN_DIR)/$(call DEVICE_IMG_NAME,$(1),$(2)): $(KDIR)/tmp/$(call DEVICE_IMG_NAME,$(1),$(2))\n\tcp $$^ $$@\n\n  $(BUILD_DIR)/json_info_files/$(call DEVICE_IMG_NAME,$(1),$(2)).json: $(BIN_DIR)/$(call DEVICE_IMG_NAME,$(1),$(2))$$(GZ_SUFFIX)\n\t@mkdir -p $$(shell dirname $$@)\n\tDEVICE_ID=\"$(DEVICE_NAME)\" \\\n\tSOURCE_DATE_EPOCH=$(SOURCE_DATE_EPOCH) \\\n\tFILE_NAME=\"$(DEVICE_IMG_NAME)\" \\\n\tFILE_DIR=\"$(KDIR)/tmp\" \\\n\tFILE_TYPE=$(word 1,$(subst ., ,$(2))) \\\n\tFILE_FILESYSTEM=\"$(1)\" \\\n\tDEVICE_IMG_PREFIX=\"$(DEVICE_IMG_PREFIX)\" \\\n\tDEVICE_VENDOR=\"$(DEVICE_VENDOR)\" \\\n\tDEVICE_MODEL=\"$(DEVICE_MODEL)\" \\\n\tDEVICE_VARIANT=\"$(DEVICE_VARIANT)\" \\\n\tDEVICE_ALT0_VENDOR=\"$(DEVICE_ALT0_VENDOR)\" \\\n\tDEVICE_ALT0_MODEL=\"$(DEVICE_ALT0_MODEL)\" \\\n\tDEVICE_ALT0_VARIANT=\"$(DEVICE_ALT0_VARIANT)\" \\\n\tDEVICE_ALT1_VENDOR=\"$(DEVICE_ALT1_VENDOR)\" \\\n\tDEVICE_ALT1_MODEL=\"$(DEVICE_ALT1_MODEL)\" \\\n\tDEVICE_ALT1_VARIANT=\"$(DEVICE_ALT1_VARIANT)\" \\\n\tDEVICE_ALT2_VENDOR=\"$(DEVICE_ALT2_VENDOR)\" \\\n\tDEVICE_ALT2_MODEL=\"$(DEVICE_ALT2_MODEL)\" \\\n\tDEVICE_ALT2_VARIANT=\"$(DEVICE_ALT2_VARIANT)\" \\\n\tDEVICE_TITLE=\"$(DEVICE_TITLE)\" \\\n\tDEVICE_PACKAGES=\"$(DEVICE_PACKAGES)\" \\\n\tTARGET=\"$(BOARD)\" \\\n\tSUBTARGET=\"$(if $(SUBTARGET),$(SUBTARGET),generic)\" \\\n\tVERSION_NUMBER=\"$(VERSION_NUMBER)\" \\\n\tVERSION_CODE=\"$(VERSION_CODE)\" \\\n\tSUPPORTED_DEVICES=\"$(SUPPORTED_DEVICES)\" \\\n\t$(TOPDIR)/scripts/json_add_image_info.py $$@\n\nendef\n\ndefine Device/Build/artifact\n  $$(_TARGET): $(if $(CONFIG_JSON_OVERVIEW_IMAGE_INFO), \\\n\t  $(BUILD_DIR)/json_info_files/$(DEVICE_IMG_PREFIX)-$(1).json, \\\n\t  $(BIN_DIR)/$(DEVICE_IMG_PREFIX)-$(1))\n  $(eval $(call Device/Export,$(KDIR)/tmp/$(DEVICE_IMG_PREFIX)-$(1)))\n  $(KDIR)/tmp/$(DEVICE_IMG_PREFIX)-$(1): $$(KDIR_KERNEL_IMAGE) $(2)-images\n\t@rm -f $$@\n\t$$(call concat_cmd,$(ARTIFACT/$(1)))\n\n  .IGNORE: $(BIN_DIR)/$(DEVICE_IMG_PREFIX)-$(1)\n\n  $(BIN_DIR)/$(DEVICE_IMG_PREFIX)-$(1): $(KDIR)/tmp/$(DEVICE_IMG_PREFIX)-$(1)\n\tcp $$^ $$@\n\n  $(BUILD_DIR)/json_info_files/$(DEVICE_IMG_PREFIX)-$(1).json: $(BIN_DIR)/$(DEVICE_IMG_PREFIX)-$(1)\n\t@mkdir -p $$(shell dirname $$@)\n\tDEVICE_ID=\"$(DEVICE_NAME)\" \\\n\tSOURCE_DATE_EPOCH=$(SOURCE_DATE_EPOCH) \\\n\tFILE_NAME=\"$(DEVICE_IMG_PREFIX)-$(1)\" \\\n\tFILE_DIR=\"$(KDIR)/tmp\" \\\n\tFILE_TYPE=\"$(1)\" \\\n\tDEVICE_IMG_PREFIX=\"$(DEVICE_IMG_PREFIX)\" \\\n\tDEVICE_VENDOR=\"$(DEVICE_VENDOR)\" \\\n\tDEVICE_MODEL=\"$(DEVICE_MODEL)\" \\\n\tDEVICE_VARIANT=\"$(DEVICE_VARIANT)\" \\\n\tDEVICE_ALT0_VENDOR=\"$(DEVICE_ALT0_VENDOR)\" \\\n\tDEVICE_ALT0_MODEL=\"$(DEVICE_ALT0_MODEL)\" \\\n\tDEVICE_ALT0_VARIANT=\"$(DEVICE_ALT0_VARIANT)\" \\\n\tDEVICE_ALT1_VENDOR=\"$(DEVICE_ALT1_VENDOR)\" \\\n\tDEVICE_ALT1_MODEL=\"$(DEVICE_ALT1_MODEL)\" \\\n\tDEVICE_ALT1_VARIANT=\"$(DEVICE_ALT1_VARIANT)\" \\\n\tDEVICE_ALT2_VENDOR=\"$(DEVICE_ALT2_VENDOR)\" \\\n\tDEVICE_ALT2_MODEL=\"$(DEVICE_ALT2_MODEL)\" \\\n\tDEVICE_ALT2_VARIANT=\"$(DEVICE_ALT2_VARIANT)\" \\\n\tDEVICE_TITLE=\"$(DEVICE_TITLE)\" \\\n\tDEVICE_PACKAGES=\"$(DEVICE_PACKAGES)\" \\\n\tTARGET=\"$(BOARD)\" \\\n\tSUBTARGET=\"$(if $(SUBTARGET),$(SUBTARGET),generic)\" \\\n\tVERSION_NUMBER=\"$(VERSION_NUMBER)\" \\\n\tVERSION_CODE=\"$(VERSION_CODE)\" \\\n\tSUPPORTED_DEVICES=\"$(SUPPORTED_DEVICES)\" \\\n\t$(TOPDIR)/scripts/json_add_image_info.py $$@\n\nendef\n\ndefine Device/Build\n  $(if $(CONFIG_TARGET_ROOTFS_INITRAMFS),$(call Device/Build/initramfs,$(1)))\n  $(call Device/Build/kernel,$(1))\n\n  $$(eval $$(foreach compile,$$(COMPILE), \\\n    $$(call Device/Build/compile,$$(compile),$(1))))\n\n  $$(eval $$(foreach image,$$(IMAGES), \\\n    $$(foreach fs,$$(filter $(TARGET_FILESYSTEMS),$$(FILESYSTEMS)), \\\n      $$(call Device/Build/image,$$(fs),$$(image),$(1)))))\n\n  $$(eval $$(foreach artifact,$$(ARTIFACTS), \\\n    $$(call Device/Build/artifact,$$(artifact),$(1))))\n\nendef\n\ndefine Device/DumpInfo\nTarget-Profile: DEVICE_$(1)\nTarget-Profile-Name: $(DEVICE_DISPLAY)\nTarget-Profile-Packages: $(DEVICE_PACKAGES)\nTarget-Profile-hasImageMetadata: $(if $(foreach image,$(IMAGES),$(findstring append-metadata,$(IMAGE/$(image)))),1,0)\nTarget-Profile-SupportedDevices: $(SUPPORTED_DEVICES)\n$(if $(BROKEN),Target-Profile-Broken: $(BROKEN))\n$(if $(DEFAULT),Target-Profile-Default: $(DEFAULT))\nTarget-Profile-Description:\n$(DEVICE_DESCRIPTION)\n$(if $(strip $(DEVICE_ALT0_TITLE)),Alternative device titles:\n- $(DEVICE_ALT0_TITLE))\n$(if $(strip $(DEVICE_ALT1_TITLE)),- $(DEVICE_ALT1_TITLE))\n$(if $(strip $(DEVICE_ALT2_TITLE)),- $(DEVICE_ALT2_TITLE))\n@@\n\nendef\n\ndefine Device/Dump\nifneq ($$(strip $$(DEVICE_ALT0_TITLE)),)\nDEVICE_DISPLAY = $$(DEVICE_ALT0_TITLE) ($$(DEVICE_TITLE))\n$$(info $$(call Device/DumpInfo,$(1)))\nendif\nifneq ($$(strip $$(DEVICE_ALT1_TITLE)),)\nDEVICE_DISPLAY = $$(DEVICE_ALT1_TITLE) ($$(DEVICE_TITLE))\n$$(info $$(call Device/DumpInfo,$(1)))\nendif\nifneq ($$(strip $$(DEVICE_ALT2_TITLE)),)\nDEVICE_DISPLAY = $$(DEVICE_ALT2_TITLE) ($$(DEVICE_TITLE))\n$$(info $$(call Device/DumpInfo,$(1)))\nendif\nDEVICE_DISPLAY = $$(DEVICE_TITLE)\n$$(eval $$(if $$(DEVICE_TITLE),$$(info $$(call Device/DumpInfo,$(1)))))\nendef\n\ndefine Device\n  $(call Device/InitProfile,$(1))\n  $(call Device/Init,$(1))\n  $(call Device/Default,$(1))\n  $(call Device/$(1),$(1))\n  $(call Device/Check,$(1))\n  $(call Device/$(if $(DUMP),Dump,Build),$(1))\n\nendef\n\ndefine BuildImage\n\n  ifneq ($(DUMP),)\n    all: dumpinfo\n    dumpinfo: FORCE\n\t@true\n  endif\n\n  download:\n  prepare:\n  compile:\n  clean:\n  image_prepare:\n\n  ifeq ($(IB),)\n    .PHONY: download prepare compile clean image_prepare kernel_prepare install install-images\n    compile:\n\t\t$(call Build/Compile)\n\n    clean:\n\t\t$(call Build/Clean)\n\n    image_prepare: compile\n\t\tmkdir -p $(BIN_DIR) $(KDIR)/tmp\n\t\trm -rf $(BUILD_DIR)/json_info_files\n\t\t$(call Image/Prepare)\n\n  else\n    image_prepare:\n\t\tmkdir -p $(BIN_DIR) $(KDIR)/tmp\n  endif\n\n  kernel_prepare: image_prepare\n\t$(call Image/Build/targz)\n\t$(call Image/Build/cpiogz)\n\t$(call Image/BuildKernel)\n\t$(if $(CONFIG_TARGET_ROOTFS_INITRAMFS),$(if $(IB),,$(call Image/BuildKernel/Initramfs)))\n\t$(call Image/InstallKernel)\n\n  $(foreach device,$(TARGET_DEVICES),$(call Device,$(device)))\n\n  install-images: kernel_prepare $(foreach fs,$(filter-out $(if $(UBIFS_OPTS),,ubifs),$(TARGET_FILESYSTEMS) $(fs-subtypes-y)),$(KDIR)/root.$(fs))\n\t$(foreach fs,$(TARGET_FILESYSTEMS),\n\t\t$(call Image/Build,$(fs))\n\t)\n\n  install: install-images\n\t$(call Image/Manifest)\n\nendef\n"
  },
  {
    "path": "include/kernel-5.10",
    "content": "LINUX_VERSION-5.10 = .113\nLINUX_KERNEL_HASH-5.10.113 = 82516a02bb52456f6e8057217dde6e02b78003b1e058117557c2ae9661696dfc\n"
  },
  {
    "path": "include/kernel-5.15",
    "content": "LINUX_VERSION-5.15 = .38\nLINUX_KERNEL_HASH-5.15.38 = 7e415d420990b88bfec038d56e920b9b28f99d54f31dbbd7aa82e66acca11052\n"
  },
  {
    "path": "include/kernel-build.mk",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2006-2020 OpenWrt.org\n\ninclude $(INCLUDE_DIR)/prereq.mk\ninclude $(INCLUDE_DIR)/depends.mk\n\nifneq ($(DUMP),1)\n  all: compile\nendif\n\nKERNEL_FILE_DEPENDS=$(GENERIC_BACKPORT_DIR) $(GENERIC_PATCH_DIR) $(GENERIC_HACK_DIR) $(PATCH_DIR) $(GENERIC_FILES_DIR) $(FILES_DIR)\nSTAMP_PREPARED=$(LINUX_DIR)/.prepared$(if $(QUILT)$(DUMP),,_$(shell $(call find_md5,$(KERNEL_FILE_DEPENDS),)))\nSTAMP_CONFIGURED:=$(LINUX_DIR)/.configured\ninclude $(INCLUDE_DIR)/download.mk\ninclude $(INCLUDE_DIR)/quilt.mk\ninclude $(INCLUDE_DIR)/kernel-defaults.mk\n\ndefine Kernel/Prepare\n\t$(call Kernel/Prepare/Default)\nendef\n\ndefine Kernel/Configure\n\t$(call Kernel/Configure/Default)\nendef\n\ndefine Kernel/CompileModules\n\t$(call Kernel/CompileModules/Default)\nendef\n\ndefine Kernel/CompileImage\n\t$(call Kernel/CompileImage/Default)\n\t$(call Kernel/CompileImage/Initramfs)\nendef\n\ndefine Kernel/Clean\n\t$(call Kernel/Clean/Default)\nendef\n\ndefine Download/kernel\n  URL:=$(LINUX_SITE)\n  FILE:=$(LINUX_SOURCE)\n  HASH:=$(LINUX_KERNEL_HASH)\nendef\n\nKERNEL_GIT_OPTS:=\nifneq ($(strip $(CONFIG_KERNEL_GIT_LOCAL_REPOSITORY)),\"\")\n  KERNEL_GIT_OPTS+=--reference $(CONFIG_KERNEL_GIT_LOCAL_REPOSITORY)\nendif\n\ndefine Download/git-kernel\n  URL:=$(call qstrip,$(CONFIG_KERNEL_GIT_CLONE_URI))\n  PROTO:=git\n  VERSION:=$(CONFIG_KERNEL_GIT_REF)\n  FILE:=$(LINUX_SOURCE)\n  SUBDIR:=linux-$(LINUX_VERSION)\n  OPTS:=$(KERNEL_GIT_OPTS)\nendef\n\nifdef CONFIG_COLLECT_KERNEL_DEBUG\n  define Kernel/CollectDebug\n\trm -rf $(KERNEL_BUILD_DIR)/debug\n\tmkdir -p $(KERNEL_BUILD_DIR)/debug/modules\n\t$(CP) $(LINUX_DIR)/vmlinux $(KERNEL_BUILD_DIR)/debug/\n\t-$(CP) \\\n\t\t$(STAGING_DIR_ROOT)/lib/modules/$(LINUX_VERSION)/* \\\n\t\t$(KERNEL_BUILD_DIR)/debug/modules/\n\t$(FIND) $(KERNEL_BUILD_DIR)/debug -type f | $(XARGS) $(KERNEL_CROSS)strip --only-keep-debug\n\t$(TAR) c -C $(KERNEL_BUILD_DIR) debug \\\n\t\t$(if $(SOURCE_DATE_EPOCH),--mtime=\"@$(SOURCE_DATE_EPOCH)\") \\\n\t\t| zstd -T0 -f -o $(BIN_DIR)/kernel-debug.tar.zst\n  endef\nendif\n\nifeq ($(DUMP)$(filter prereq clean refresh update,$(MAKECMDGOALS)),)\n  ifneq ($(if $(QUILT),,$(CONFIG_AUTOREBUILD)),)\n    define Kernel/Autoclean\n      $(PKG_BUILD_DIR)/.dep_files: $(STAMP_PREPARED)\n      $(call rdep,$(KERNEL_FILE_DEPENDS),$(STAMP_PREPARED),$(PKG_BUILD_DIR)/.dep_files,-x \"*/.dep_*\")\n    endef\n  endif\nendif\n\ndefine BuildKernel\n  $(if $(QUILT),$(Build/Quilt))\n  $(if $(LINUX_SITE),$(call Download,kernel))\n  $(if $(call qstrip,$(CONFIG_KERNEL_GIT_CLONE_URI)),$(call Download,git-kernel))\n\n  .NOTPARALLEL:\n\n  $(Kernel/Autoclean)\n  $(STAMP_PREPARED): $(if $(LINUX_SITE),$(DL_DIR)/$(LINUX_SOURCE))\n\t-rm -rf $(KERNEL_BUILD_DIR)\n\t-mkdir -p $(KERNEL_BUILD_DIR)\n\t$(Kernel/Prepare)\n\ttouch $$@\n\n  $(KERNEL_BUILD_DIR)/symtab.h: FORCE\n\trm -f $(KERNEL_BUILD_DIR)/symtab.h\n\ttouch $(KERNEL_BUILD_DIR)/symtab.h\n\t+$(KERNEL_MAKE) vmlinux\n\tfind $(LINUX_DIR) $(STAGING_DIR_ROOT)/lib/modules -name \\*.ko | \\\n\t\txargs $(TARGET_CROSS)nm | \\\n\t\tawk '$$$$1 == \"U\" { print $$$$2 } ' | \\\n\t\tsort -u > $(KERNEL_BUILD_DIR)/mod_symtab.txt\n\t$(TARGET_CROSS)nm -n $(LINUX_DIR)/vmlinux.o | awk '/^[0-9a-f]+ [rR] __ksymtab_/ {print substr($$$$3,11)}' > $(KERNEL_BUILD_DIR)/kernel_symtab.txt\n\tgrep -Ff $(KERNEL_BUILD_DIR)/mod_symtab.txt $(KERNEL_BUILD_DIR)/kernel_symtab.txt > $(KERNEL_BUILD_DIR)/sym_include.txt\n\tgrep -Fvf $(KERNEL_BUILD_DIR)/mod_symtab.txt $(KERNEL_BUILD_DIR)/kernel_symtab.txt > $(KERNEL_BUILD_DIR)/sym_exclude.txt\n\t( \\\n\t\techo '#define SYMTAB_KEEP \\'; \\\n\t\tcat $(KERNEL_BUILD_DIR)/sym_include.txt | \\\n\t\t\tawk '{print \"KEEP(*(___ksymtab+\" $$$$1 \")) \\\\\" }'; \\\n\t\techo; \\\n\t\techo '#define SYMTAB_KEEP_GPL \\'; \\\n\t\tcat $(KERNEL_BUILD_DIR)/sym_include.txt | \\\n\t\t\tawk '{print \"KEEP(*(___ksymtab_gpl+\" $$$$1 \")) \\\\\" }'; \\\n\t\techo; \\\n\t\techo '#define SYMTAB_DISCARD \\'; \\\n\t\tcat $(KERNEL_BUILD_DIR)/sym_exclude.txt | \\\n\t\t\tawk '{print \"*(___ksymtab+\" $$$$1 \") \\\\\" }'; \\\n\t\techo; \\\n\t\techo '#define SYMTAB_DISCARD_GPL \\'; \\\n\t\tcat $(KERNEL_BUILD_DIR)/sym_exclude.txt | \\\n\t\t\tawk '{print \"*(___ksymtab_gpl+\" $$$$1 \") \\\\\" }'; \\\n\t\techo; \\\n\t) > $$@\n\n  $(STAMP_CONFIGURED): $(STAMP_PREPARED) $(LINUX_KCONFIG_LIST) $(TOPDIR)/.config FORCE\n\t$(Kernel/Configure)\n\ttouch $$@\n\n  $(LINUX_DIR)/.modules: export STAGING_PREFIX=$$(STAGING_DIR_HOST)\n  $(LINUX_DIR)/.modules: export PKG_CONFIG_PATH=$$(STAGING_DIR_HOST)/lib/pkgconfig\n  $(LINUX_DIR)/.modules: export PKG_CONFIG_LIBDIR=$$(STAGING_DIR_HOST)/lib/pkgconfig\n  $(LINUX_DIR)/.modules: export FAIL_ON_UNCONFIGURED=1\n  $(LINUX_DIR)/.modules: $(STAMP_CONFIGURED) $(LINUX_DIR)/.config FORCE\n\t$(Kernel/CompileModules)\n\ttouch $$@\n\n  $(LINUX_DIR)/.image: export STAGING_PREFIX=$$(STAGING_DIR_HOST)\n  $(LINUX_DIR)/.image: export PKG_CONFIG_PATH=$$(STAGING_DIR_HOST)/lib/pkgconfig\n  $(LINUX_DIR)/.image: export PKG_CONFIG_LIBDIR=$$(STAGING_DIR_HOST)/lib/pkgconfig\n  $(LINUX_DIR)/.image: $(STAMP_CONFIGURED) $(if $(CONFIG_STRIP_KERNEL_EXPORTS),$(KERNEL_BUILD_DIR)/symtab.h) FORCE\n\t$(Kernel/CompileImage)\n\t$(Kernel/CollectDebug)\n\ttouch $$@\n\t\n  mostlyclean: FORCE\n\t$(Kernel/Clean)\n\n  define BuildKernel\n  endef\n\n  download: $(if $(LINUX_SITE),$(DL_DIR)/$(LINUX_SOURCE))\n  prepare: $(STAMP_PREPARED)\n  compile: $(LINUX_DIR)/.modules\n\t$(MAKE) -C image compile TARGET_BUILD=\n\n  oldconfig menuconfig nconfig xconfig: $(STAMP_PREPARED) $(STAMP_CHECKED) FORCE\n\trm -f $(LINUX_DIR)/.config.prev\n\trm -f $(STAMP_CONFIGURED)\n\t$(LINUX_RECONF_CMD) > $(LINUX_DIR)/.config\n\t$(_SINGLE)$(KERNEL_MAKE) \\\n\t\t$(if $(findstring Darwin,$(HOST_OS)), \\\n\t\t\tHOST_LOADLIBES=\"-L$(STAGING_DIR_HOST)/lib -lncurses\" \\\n\t\t\tHOSTLDLIBS_mconf=\"-L$(STAGING_DIR_HOST)/lib -lncurses\" \\\n\t\t\tfilechk_conf_cfg=\"\t:\" \\\n\t\t) \\\n\t\tYACC=$(STAGING_DIR_HOST)/bin/bison \\\n\t\t$$@\n\t$(call LINUX_RECONF_DIFF,$(LINUX_DIR)/.config) > $(LINUX_RECONFIG_TARGET)\n\n  install: $(LINUX_DIR)/.image\n\t+$(MAKE) -C image compile install TARGET_BUILD=\n\n  clean: FORCE\n\trm -rf $(KERNEL_BUILD_DIR)\n\n  image-prereq:\n\t@+$(NO_TRACE_MAKE) -s -C image prereq TARGET_BUILD=\n\n  prereq: image-prereq\n\nendef\n"
  },
  {
    "path": "include/kernel-defaults.mk",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2006-2020 OpenWrt.org\n\nifdef CONFIG_STRIP_KERNEL_EXPORTS\n  KERNEL_MAKEOPTS_IMAGE += \\\n\tEXTRA_LDSFLAGS=\"-I$(KERNEL_BUILD_DIR) -include symtab.h\"\nendif\n\nINITRAMFS_EXTRA_FILES ?= $(GENERIC_PLATFORM_DIR)/image/initramfs-base-files.txt\n\nifneq (,$(KERNEL_CC))\n  KERNEL_MAKEOPTS += CC=\"$(KERNEL_CC)\"\nendif\n\nexport HOST_EXTRACFLAGS=-I$(STAGING_DIR_HOST)/include\n\n# defined in quilt.mk\nKernel/Patch:=$(Kernel/Patch/Default)\n\nifneq (,$(findstring .xz,$(LINUX_SOURCE)))\n  LINUX_CAT:=xzcat\nelse\n  LINUX_CAT:=gzip -dc\nendif\n\nifeq ($(strip $(CONFIG_EXTERNAL_KERNEL_TREE)),\"\")\n  ifeq ($(strip $(CONFIG_KERNEL_GIT_CLONE_URI)),\"\")\n    define Kernel/Prepare/Default\n\t$(LINUX_CAT) $(DL_DIR)/$(LINUX_SOURCE) | $(TAR) -C $(KERNEL_BUILD_DIR) $(TAR_OPTIONS)\n\t$(Kernel/Patch)\n\t$(if $(QUILT),touch $(LINUX_DIR)/.quilt_used)\n    endef\n  else\n    define Kernel/Prepare/Default\n\t$(LINUX_CAT) $(DL_DIR)/$(LINUX_SOURCE) | $(TAR) -C $(KERNEL_BUILD_DIR) $(TAR_OPTIONS)\n    endef\n  endif\nelse\n  define Kernel/Prepare/Default\n\tmkdir -p $(KERNEL_BUILD_DIR)\n\tif [ -d $(LINUX_DIR) ]; then \\\n\t\trmdir $(LINUX_DIR); \\\n\tfi\n\tln -s $(CONFIG_EXTERNAL_KERNEL_TREE) $(LINUX_DIR)\n\tif [ -d $(LINUX_DIR)/user_headers ]; then \\\n\t\trm -rf $(LINUX_DIR)/user_headers; \\\n\tfi\n  endef\nendif\n\nifeq ($(CONFIG_TARGET_ROOTFS_INITRAMFS),y)\n  ifeq ($(CONFIG_TARGET_ROOTFS_INITRAMFS_SEPARATE),y)\n    define Kernel/SetInitramfs/PreConfigure\n\tgrep -v -e CONFIG_BLK_DEV_INITRD $(LINUX_DIR)/.config.old > $(LINUX_DIR)/.config\n\techo 'CONFIG_BLK_DEV_INITRD=y' >> $(LINUX_DIR)/.config\n\techo 'CONFIG_INITRAMFS_SOURCE=\"\"' >> $(LINUX_DIR)/.config\n    endef\n  else\n  ifeq ($(strip $(CONFIG_EXTERNAL_CPIO)),\"\")\n    define Kernel/SetInitramfs/PreConfigure\n\tgrep -v -e INITRAMFS -e CONFIG_RD_ -e CONFIG_BLK_DEV_INITRD $(LINUX_DIR)/.config.old > $(LINUX_DIR)/.config\n\techo 'CONFIG_BLK_DEV_INITRD=y' >> $(LINUX_DIR)/.config\n\techo 'CONFIG_INITRAMFS_SOURCE=\"$(strip $(TARGET_DIR) $(INITRAMFS_EXTRA_FILES))\"' >> $(LINUX_DIR)/.config\n    endef\n  else\n    define Kernel/SetInitramfs/PreConfigure\n\tgrep -v INITRAMFS $(LINUX_DIR)/.config.old > $(LINUX_DIR)/.config\n\techo 'CONFIG_INITRAMFS_SOURCE=\"$(call qstrip,$(CONFIG_EXTERNAL_CPIO))\"' >> $(LINUX_DIR)/.config\n    endef\n  endif\nendif\n\n  define Kernel/SetInitramfs\n\trm -f $(LINUX_DIR)/.config.prev\n\tmv $(LINUX_DIR)/.config $(LINUX_DIR)/.config.old\n\t$(call Kernel/SetInitramfs/PreConfigure)\n  ifneq ($(CONFIG_TARGET_ROOTFS_INITRAMFS_SEPARATE),y)\n\techo 'CONFIG_INITRAMFS_ROOT_UID=$(shell id -u)' >> $(LINUX_DIR)/.config\n\techo 'CONFIG_INITRAMFS_ROOT_GID=$(shell id -g)' >> $(LINUX_DIR)/.config\n\techo \"$(if $(CONFIG_TARGET_INITRAMFS_FORCE),CONFIG_INITRAMFS_FORCE=y,# CONFIG_INITRAMFS_FORCE is not set)\" >> $(LINUX_DIR)/.config\n  else\n\techo \"# CONFIG_INITRAMFS_FORCE is not set\" >> $(LINUX_DIR)/.config\n  endif\n\techo \"$(if $(CONFIG_TARGET_INITRAMFS_COMPRESSION_NONE),CONFIG_INITRAMFS_COMPRESSION_NONE=y,# CONFIG_INITRAMFS_COMPRESSION_NONE is not set)\" >> $(LINUX_DIR)/.config\n\techo -e \"$(if $(CONFIG_TARGET_INITRAMFS_COMPRESSION_GZIP),CONFIG_INITRAMFS_COMPRESSION_GZIP=y\\nCONFIG_RD_GZIP=y,# CONFIG_INITRAMFS_COMPRESSION_GZIP is not set\\n# CONFIG_RD_GZIP is not set)\" >> $(LINUX_DIR)/.config\n\techo -e \"$(if $(CONFIG_TARGET_INITRAMFS_COMPRESSION_BZIP2),CONFIG_INITRAMFS_COMPRESSION_BZIP2=y\\nCONFIG_RD_BZIP2=y,# CONFIG_INITRAMFS_COMPRESSION_BZIP2 is not set\\n# CONFIG_RD_BZIP2 is not set)\" >> $(LINUX_DIR)/.config\n\techo -e \"$(if $(CONFIG_TARGET_INITRAMFS_COMPRESSION_LZMA),CONFIG_INITRAMFS_COMPRESSION_LZMA=y\\nCONFIG_RD_LZMA=y,# CONFIG_INITRAMFS_COMPRESSION_LZMA is not set\\n# CONFIG_RD_LZMA is not set)\" >> $(LINUX_DIR)/.config\n\techo -e \"$(if $(CONFIG_TARGET_INITRAMFS_COMPRESSION_LZO),CONFIG_INITRAMFS_COMPRESSION_LZO=y\\nCONFIG_RD_LZO=y,# CONFIG_INITRAMFS_COMPRESSION_LZO is not set\\n# CONFIG_RD_LZO is not set)\" >> $(LINUX_DIR)/.config\n\techo -e \"$(if $(CONFIG_TARGET_INITRAMFS_COMPRESSION_XZ),CONFIG_INITRAMFS_COMPRESSION_XZ=y\\nCONFIG_RD_XZ=y,# CONFIG_INITRAMFS_COMPRESSION_XZ is not set\\n# CONFIG_RD_XZ is not set)\" >> $(LINUX_DIR)/.config\n\techo -e \"$(if $(CONFIG_TARGET_INITRAMFS_COMPRESSION_LZ4),CONFIG_INITRAMFS_COMPRESSION_LZ4=y\\nCONFIG_RD_LZ4=y,# CONFIG_INITRAMFS_COMPRESSION_LZ4 is not set\\n# CONFIG_RD_LZ4 is not set)\" >> $(LINUX_DIR)/.config\n\techo -e \"$(if $(CONFIG_TARGET_INITRAMFS_COMPRESSION_ZSTD),CONFIG_INITRAMFS_COMPRESSION_ZSTD=y\\nCONFIG_RD_ZSTD=y,# CONFIG_INITRAMFS_COMPRESSION_ZSTD is not set\\n# CONFIG_RD_ZSTD is not set)\" >> $(LINUX_DIR)/.config\n  endef\nelse\nendif\n\ndefine Kernel/SetNoInitramfs\n\tmv $(LINUX_DIR)/.config.set $(LINUX_DIR)/.config.old\n\tgrep -v INITRAMFS $(LINUX_DIR)/.config.old > $(LINUX_DIR)/.config.set\n\techo 'CONFIG_INITRAMFS_SOURCE=\"\"' >> $(LINUX_DIR)/.config.set\n\techo '# CONFIG_INITRAMFS_FORCE is not set' >> $(LINUX_DIR)/.config.set\nendef\n\ndefine Kernel/Configure/Default\n\trm -f $(LINUX_DIR)/localversion\n\t$(LINUX_CONF_CMD) > $(LINUX_DIR)/.config.target\n# copy CONFIG_KERNEL_* settings over to .config.target\n\tawk '/^(#[[:space:]]+)?CONFIG_KERNEL/{sub(\"CONFIG_KERNEL_\",\"CONFIG_\");print}' $(TOPDIR)/.config >> $(LINUX_DIR)/.config.target\n\techo \"# CONFIG_KALLSYMS_EXTRA_PASS is not set\" >> $(LINUX_DIR)/.config.target\n\techo \"# CONFIG_KALLSYMS_ALL is not set\" >> $(LINUX_DIR)/.config.target\n\techo \"CONFIG_KALLSYMS_UNCOMPRESSED=y\" >> $(LINUX_DIR)/.config.target\n\t$(SCRIPT_DIR)/package-metadata.pl kconfig $(TMP_DIR)/.packageinfo $(TOPDIR)/.config $(KERNEL_PATCHVER) > $(LINUX_DIR)/.config.override\n\t$(SCRIPT_DIR)/kconfig.pl 'm+' '+' $(LINUX_DIR)/.config.target /dev/null $(LINUX_DIR)/.config.override > $(LINUX_DIR)/.config.set\n\t$(call Kernel/SetNoInitramfs)\n\trm -rf $(KERNEL_BUILD_DIR)/modules\n\tcmp -s $(LINUX_DIR)/.config.set $(LINUX_DIR)/.config.prev || { \\\n\t\tcp $(LINUX_DIR)/.config.set $(LINUX_DIR)/.config; \\\n\t\tcp $(LINUX_DIR)/.config.set $(LINUX_DIR)/.config.prev; \\\n\t}\n\t$(_SINGLE) [ -d $(LINUX_DIR)/user_headers ] || $(KERNEL_MAKE) INSTALL_HDR_PATH=$(LINUX_DIR)/user_headers headers_install\n\tgrep '=[ym]' $(LINUX_DIR)/.config.set | LC_ALL=C sort | $(MKHASH) md5 > $(LINUX_DIR)/.vermagic\nendef\n\ndefine Kernel/Configure/Initramfs\n\t$(call Kernel/SetInitramfs)\nendef\n\ndefine Kernel/CompileModules/Default\n\trm -f $(LINUX_DIR)/vmlinux $(LINUX_DIR)/System.map\n\t+$(KERNEL_MAKE) $(if $(KERNELNAME),$(KERNELNAME),all) modules\n\t# If .config did not change, use the previous timestamp to avoid package rebuilds\n\tcmp -s $(LINUX_DIR)/.config $(LINUX_DIR)/.config.modules.save && \\\n\t\tmv $(LINUX_DIR)/.config.modules.save $(LINUX_DIR)/.config; \\\n\t$(CP) $(LINUX_DIR)/.config $(LINUX_DIR)/.config.modules.save\nendef\n\nOBJCOPY_STRIP = -R .reginfo -R .notes -R .note -R .comment -R .mdebug -R .note.gnu.build-id\n\n# AMD64 shares the location with x86\nifeq ($(LINUX_KARCH),x86_64)\nIMAGES_DIR:=../../x86/boot\nendif\n\ndefine Kernel/CopyImage\n\tcmp -s $(LINUX_DIR)/vmlinux $(KERNEL_BUILD_DIR)/vmlinux$(1).debug || { \\\n\t\t$(KERNEL_CROSS)objcopy -O binary $(OBJCOPY_STRIP) -S $(LINUX_DIR)/vmlinux $(LINUX_KERNEL)$(1); \\\n\t\t$(KERNEL_CROSS)objcopy $(OBJCOPY_STRIP) -S $(LINUX_DIR)/vmlinux $(KERNEL_BUILD_DIR)/vmlinux$(1).elf; \\\n\t\t$(CP) $(LINUX_DIR)/vmlinux $(KERNEL_BUILD_DIR)/vmlinux$(1).debug; \\\n\t\t$(foreach k, \\\n\t\t\t$(if $(KERNEL_IMAGES),$(KERNEL_IMAGES),$(filter-out vmlinux dtbs,$(KERNELNAME))), \\\n\t\t\t$(CP) $(LINUX_DIR)/arch/$(LINUX_KARCH)/boot/$(IMAGES_DIR)/$(k) $(KERNEL_BUILD_DIR)/$(k)$(1); \\\n\t\t) \\\n\t}\nendef\n\n# Always add \"modules\" so a proper Module.symvers file is written that\n# also contains symbols from the kernel modules. Without these symbols\n# external packages that depend on exported symbols from kernel modules\n# will fail to build.\ndefine Kernel/CompileImage/Default\n\trm -f $(TARGET_DIR)/init\n\t+$(KERNEL_MAKE) $(KERNEL_MAKEOPTS_IMAGE) $(if $(KERNELNAME),$(KERNELNAME),all) modules\n\t$(call Kernel/CopyImage)\nendef\n\n# Here as well, always add \"modules\", see comment above.\nifneq ($(CONFIG_TARGET_ROOTFS_INITRAMFS),)\ndefine Kernel/CompileImage/Initramfs\n\t$(call Kernel/Configure/Initramfs)\n\t$(CP) $(GENERIC_PLATFORM_DIR)/other-files/init $(TARGET_DIR)/init\n\t$(if $(SOURCE_DATE_EPOCH),touch -hcd \"@$(SOURCE_DATE_EPOCH)\" $(TARGET_DIR) $(TARGET_DIR)/init)\n\trm -rf $(KERNEL_BUILD_DIR)/linux-$(LINUX_VERSION)/usr/initramfs_data.cpio*\nifeq ($(CONFIG_TARGET_ROOTFS_INITRAMFS_SEPARATE),y)\nifneq ($(qstrip $(CONFIG_EXTERNAL_CPIO)),)\n\t$(CP) $(CONFIG_EXTERNAL_CPIO) $(KERNEL_BUILD_DIR)/initrd.cpio\nelse\n\t( cd $(TARGET_DIR); find . | LC_ALL=C sort | $(STAGING_DIR_HOST)/bin/cpio --reproducible -o -H newc -R 0:0 > $(KERNEL_BUILD_DIR)/initrd.cpio )\nendif\n\t$(if $(SOURCE_DATE_EPOCH),touch -hcd \"@$(SOURCE_DATE_EPOCH)\" $(KERNEL_BUILD_DIR)/initrd.cpio)\n\t$(if $(CONFIG_TARGET_INITRAMFS_COMPRESSION_BZIP2),bzip2 -9 -c < $(KERNEL_BUILD_DIR)/initrd.cpio > $(KERNEL_BUILD_DIR)/initrd.cpio.bzip2)\n\t$(if $(CONFIG_TARGET_INITRAMFS_COMPRESSION_GZIP),gzip -n -f -S .gzip -9n $(KERNEL_BUILD_DIR)/initrd.cpio)\n\t$(if $(CONFIG_TARGET_INITRAMFS_COMPRESSION_LZMA),$(STAGING_DIR_HOST)/bin/lzma e -lc1 -lp2 -pb2 $(KERNEL_BUILD_DIR)/initrd.cpio $(KERNEL_BUILD_DIR)/initrd.cpio.lzma)\n# ?\t$(if $(CONFIG_TARGET_INITRAMFS_COMPRESSION_LZO),)\n\t$(if $(CONFIG_TARGET_INITRAMFS_COMPRESSION_XZ),$(STAGING_DIR_HOST)/bin/xz -T$(if $(filter 1,$(NPROC)),2,0) -9 -fz --check=crc32 $(KERNEL_BUILD_DIR)/initrd.cpio)\n# ?\t$(if $(CONFIG_TARGET_INITRAMFS_COMPRESSION_LZ4),)\n\t$(if $(CONFIG_TARGET_INITRAMFS_COMPRESSION_ZSTD),$(STAGING_DIR_HOST)/bin/zstd -T0 -f -o $(KERNEL_BUILD_DIR)/initrd.cpio.zstd $(KERNEL_BUILD_DIR)/initrd.cpio)\nendif\n\t+$(KERNEL_MAKE) $(KERNEL_MAKEOPTS_IMAGE) $(if $(KERNELNAME),$(KERNELNAME),all) modules\n\t$(call Kernel/CopyImage,-initramfs)\nendef\nelse\ndefine Kernel/CompileImage/Initramfs\nendef\nendif\n\ndefine Kernel/Clean/Default\n\trm -f $(KERNEL_BUILD_DIR)/linux-$(LINUX_VERSION)/.configured\n\trm -f $(LINUX_KERNEL)\n\t$(_SINGLE)$(MAKE) -C $(KERNEL_BUILD_DIR)/linux-$(LINUX_VERSION) clean\nendef\n"
  },
  {
    "path": "include/kernel-version.mk",
    "content": "\n# Use the default kernel version if the Makefile doesn't override it\nLINUX_RELEASE?=1\n\nifdef CONFIG_TESTING_KERNEL\n  KERNEL_PATCHVER:=$(KERNEL_TESTING_PATCHVER)\nendif\n\nKERNEL_DETAILS_FILE=$(INCLUDE_DIR)/kernel-$(KERNEL_PATCHVER)\nifeq ($(wildcard $(KERNEL_DETAILS_FILE)),)\n  $(error Missing kernel version/hash file for $(KERNEL_PATCHVER). Please create $(KERNEL_DETAILS_FILE))\nendif\n\ninclude $(KERNEL_DETAILS_FILE)\n\nremove_uri_prefix=$(subst git://,,$(subst http://,,$(subst https://,,$(1))))\nsanitize_uri=$(call qstrip,$(subst @,_,$(subst :,_,$(subst .,_,$(subst -,_,$(subst /,_,$(1)))))))\n\nifneq ($(call qstrip,$(CONFIG_KERNEL_GIT_CLONE_URI)),)\n  LINUX_VERSION:=$(call sanitize_uri,$(call remove_uri_prefix,$(CONFIG_KERNEL_GIT_CLONE_URI)))\n  ifeq ($(call qstrip,$(CONFIG_KERNEL_GIT_REF)),)\n    CONFIG_KERNEL_GIT_REF:=HEAD\n  endif\n  LINUX_VERSION:=$(LINUX_VERSION)-$(call sanitize_uri,$(CONFIG_KERNEL_GIT_REF))\nelse\nifdef KERNEL_PATCHVER\n  LINUX_VERSION:=$(KERNEL_PATCHVER)$(strip $(LINUX_VERSION-$(KERNEL_PATCHVER)))\nendif\nifdef KERNEL_TESTING_PATCHVER\n  LINUX_TESTING_VERSION:=$(KERNEL_TESTING_PATCHVER)$(strip $(LINUX_VERSION-$(KERNEL_TESTING_PATCHVER)))\nendif\nendif\n\nsplit_version=$(subst ., ,$(1))\nmerge_version=$(subst $(space),.,$(1))\nKERNEL_BASE=$(firstword $(subst -, ,$(LINUX_VERSION)))\nKERNEL=$(call merge_version,$(wordlist 1,2,$(call split_version,$(KERNEL_BASE))))\nKERNEL_PATCHVER ?= $(KERNEL)\n\n# disable the md5sum check for unknown kernel versions\nLINUX_KERNEL_HASH:=$(LINUX_KERNEL_HASH-$(strip $(LINUX_VERSION)))\nLINUX_KERNEL_HASH?=x\n"
  },
  {
    "path": "include/kernel.mk",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2006-2020 OpenWrt.org\n\nifneq ($(filter check,$(MAKECMDGOALS)),)\nCHECK:=1\nDUMP:=1\nendif\n\nifneq ($(SOURCE_DATE_EPOCH),)\n  ifndef DUMP\n    KBUILD_BUILD_TIMESTAMP:=$(shell perl -e 'print scalar gmtime($(SOURCE_DATE_EPOCH))')\n  endif\nendif\n\nifeq ($(__target_inc),)\n  ifndef CHECK\n    include $(INCLUDE_DIR)/target.mk\n  endif\nendif\n\nifeq ($(DUMP),1)\n  KERNEL?=<KERNEL>\n  BOARD?=<BOARD>\n  LINUX_VERSION?=<LINUX_VERSION>\n  LINUX_VERMAGIC?=<LINUX_VERMAGIC>\nelse\n  ifeq ($(CONFIG_EXTERNAL_TOOLCHAIN),)\n    export GCC_HONOUR_COPTS=s\n  endif\n\n  LINUX_KMOD_SUFFIX=ko\n\n  ifneq (,$(findstring uml,$(BOARD)))\n    KERNEL_CC?=$(HOSTCC)\n    KERNEL_CROSS?=\n  else\n    KERNEL_CC?=$(TARGET_CC)\n    KERNEL_CROSS?=$(TARGET_CROSS)\n  endif\n\n  ifeq ($(TARGET_BUILD),1)\n    PATCH_DIR ?= $(CURDIR)/patches$(if $(wildcard ./patches-$(KERNEL_PATCHVER)),-$(KERNEL_PATCHVER))\n    FILES_DIR ?= $(foreach dir,$(wildcard $(CURDIR)/files $(CURDIR)/files-$(KERNEL_PATCHVER)),\"$(dir)\")\n  endif\n  KERNEL_BUILD_DIR ?= $(BUILD_DIR)/linux-$(BOARD)$(if $(SUBTARGET),_$(SUBTARGET))\n  LINUX_DIR ?= $(KERNEL_BUILD_DIR)/linux-$(LINUX_VERSION)\n  LINUX_UAPI_DIR=uapi/\n  LINUX_VERMAGIC:=$(strip $(shell cat $(LINUX_DIR)/.vermagic 2>/dev/null))\n  LINUX_VERMAGIC:=$(if $(LINUX_VERMAGIC),$(LINUX_VERMAGIC),unknown)\n\n  LINUX_UNAME_VERSION:=$(KERNEL_BASE)\n  ifneq ($(findstring -rc,$(LINUX_VERSION)),)\n    LINUX_UNAME_VERSION:=$(LINUX_UNAME_VERSION)-$(strip $(lastword $(subst -, ,$(LINUX_VERSION))))\n  endif\n\n  LINUX_KERNEL:=$(KERNEL_BUILD_DIR)/vmlinux\n\n  ifneq (,$(findstring -rc,$(LINUX_VERSION)))\n      LINUX_SOURCE:=linux-$(LINUX_VERSION).tar.gz\n  else\n      LINUX_SOURCE:=linux-$(LINUX_VERSION).tar.xz\n  endif\n\n  ifneq (,$(findstring -rc,$(LINUX_VERSION)))\n      LINUX_SITE:=https://git.kernel.org/torvalds/t\n  else ifeq ($(call qstrip,$(CONFIG_EXTERNAL_KERNEL_TREE))$(call qstrip,$(CONFIG_KERNEL_GIT_CLONE_URI)),)\n      LINUX_SITE:=@KERNEL/linux/kernel/v$(word 1,$(subst ., ,$(KERNEL_BASE))).x\n  else\n      LINUX_UNAME_VERSION:=$(strip $(shell cat $(LINUX_DIR)/include/config/kernel.release 2>/dev/null))\n  endif\n\n  MODULES_SUBDIR:=lib/modules/$(LINUX_UNAME_VERSION)\n  TARGET_MODULES_DIR:=$(LINUX_TARGET_DIR)/$(MODULES_SUBDIR)\n\n  ifneq ($(TARGET_BUILD),1)\n    PKG_BUILD_DIR ?= $(KERNEL_BUILD_DIR)/$(if $(BUILD_VARIANT),$(PKG_NAME)-$(BUILD_VARIANT)/)$(PKG_NAME)$(if $(PKG_VERSION),-$(PKG_VERSION))\n  endif\nendif\n\nifneq (,$(findstring uml,$(BOARD)))\n  LINUX_KARCH=um\nelse ifneq (,$(findstring $(ARCH) , aarch64 aarch64_be ))\n  LINUX_KARCH := arm64\nelse ifneq (,$(findstring $(ARCH) , arceb ))\n  LINUX_KARCH := arc\nelse ifneq (,$(findstring $(ARCH) , armeb ))\n  LINUX_KARCH := arm\nelse ifneq (,$(findstring $(ARCH) , mipsel mips64 mips64el ))\n  LINUX_KARCH := mips\nelse ifneq (,$(findstring $(ARCH) , powerpc64 ))\n  LINUX_KARCH := powerpc\nelse ifneq (,$(findstring $(ARCH) , sh2 sh3 sh4 ))\n  LINUX_KARCH := sh\nelse ifneq (,$(findstring $(ARCH) , i386 x86_64 ))\n  LINUX_KARCH := x86\nelse\n  LINUX_KARCH := $(ARCH)\nendif\n\nKERNEL_MAKE = $(MAKE) $(KERNEL_MAKEOPTS)\n\nKERNEL_MAKE_FLAGS = \\\n\tKCFLAGS=\"$(call iremap,$(BUILD_DIR),$(notdir $(BUILD_DIR)))\" \\\n\tHOSTCFLAGS=\"$(HOST_CFLAGS) -Wall -Wmissing-prototypes -Wstrict-prototypes\" \\\n\tCROSS_COMPILE=\"$(KERNEL_CROSS)\" \\\n\tARCH=\"$(LINUX_KARCH)\" \\\n\tKBUILD_HAVE_NLS=no \\\n\tKBUILD_BUILD_USER=\"$(call qstrip,$(CONFIG_KERNEL_BUILD_USER))\" \\\n\tKBUILD_BUILD_HOST=\"$(call qstrip,$(CONFIG_KERNEL_BUILD_DOMAIN))\" \\\n\tKBUILD_BUILD_TIMESTAMP=\"$(KBUILD_BUILD_TIMESTAMP)\" \\\n\tKBUILD_BUILD_VERSION=\"0\" \\\n\tHOST_LOADLIBES=\"-L$(STAGING_DIR_HOST)/lib\" \\\n\tKBUILD_HOSTLDLIBS=\"-L$(STAGING_DIR_HOST)/lib\" \\\n\tCONFIG_SHELL=\"$(BASH)\" \\\n\t$(if $(findstring c,$(OPENWRT_VERBOSE)),V=1,V='') \\\n\t$(if $(PKG_BUILD_ID),LDFLAGS_MODULE=--build-id=0x$(PKG_BUILD_ID)) \\\n\tcmd_syscalls= \\\n\t$(if $(__package_mk),KBUILD_EXTRA_SYMBOLS=\"$(wildcard $(PKG_SYMVERS_DIR)/*.symvers)\")\n\nKERNEL_NOSTDINC_FLAGS = \\\n\t-nostdinc $(if $(DUMP),, -isystem $(shell $(TARGET_CC) -print-file-name=include))\n\nifeq ($(call qstrip,$(CONFIG_EXTERNAL_KERNEL_TREE))$(call qstrip,$(CONFIG_KERNEL_GIT_CLONE_URI)),)\n  KERNEL_MAKE_FLAGS += \\\n\tKERNELRELEASE=$(LINUX_VERSION)\nendif\n\nKERNEL_MAKEOPTS := -C $(LINUX_DIR) $(KERNEL_MAKE_FLAGS)\n\nifdef CONFIG_USE_SPARSE\n  KERNEL_MAKEOPTS += C=1 CHECK=$(STAGING_DIR_HOST)/bin/sparse\nendif\n\nifneq ($(HOST_OS),Linux)\n  KERNEL_MAKEOPTS += CONFIG_STACK_VALIDATION=\n  export SKIP_STACK_VALIDATION:=1\nendif\n\nPKG_EXTMOD_SUBDIRS ?= .\n\nPKG_SYMVERS_DIR = $(KERNEL_BUILD_DIR)/symvers\n\ndefine collect_module_symvers\n\tfor subdir in $(PKG_EXTMOD_SUBDIRS); do \\\n\t\trealdir=$$$$(readlink -f $(PKG_BUILD_DIR)); \\\n\t\tgrep -F $(PKG_BUILD_DIR) $(PKG_BUILD_DIR)/$$$$subdir/Module.symvers >> $(PKG_BUILD_DIR)/Module.symvers.tmp; \\\n\t\t[ \"$(PKG_BUILD_DIR)\" = \"$$$$realdir\" ] || \\\n\t\t\tgrep -F $$$$realdir $(PKG_BUILD_DIR)/$$$$subdir/Module.symvers >> $(PKG_BUILD_DIR)/Module.symvers.tmp; \\\n\tdone; \\\n\tsort -u $(PKG_BUILD_DIR)/Module.symvers.tmp > $(PKG_BUILD_DIR)/Module.symvers; \\\n\tmkdir -p $(PKG_SYMVERS_DIR); \\\n\tmv $(PKG_BUILD_DIR)/Module.symvers $(PKG_SYMVERS_DIR)/$(PKG_NAME).symvers\nendef\n\ndefine KernelPackage/hooks\n  ifneq ($(PKG_NAME),kernel)\n    Hooks/Compile/Post += collect_module_symvers\n  endif\n  define KernelPackage/hooks\n  endef\nendef\n\ndefine KernelPackage/Defaults\n  FILES:=\n  AUTOLOAD:=\n  MODPARAMS:=\n  PKGFLAGS+=nonshared\nendef\n\n# 1: name\n# 2: install prefix\n# 3: module priority prefix\n# 4: required for boot\n# 5: module list\ndefine ModuleAutoLoad\n  $(if $(5), \\\n    mkdir -p $(2)/etc/modules.d; \\\n    ($(foreach mod,$(5), \\\n      echo \"$(mod)$(if $(MODPARAMS.$(mod)), $(MODPARAMS.$(mod)),$(if $(MODPARAMS), $(MODPARAMS)))\"; )) > $(2)/etc/modules.d/$(3)$(1); \\\n    $(if $(4), \\\n      mkdir -p $(2)/etc/modules-boot.d; \\\n      ln -sf ../modules.d/$(3)$(1) $(2)/etc/modules-boot.d/;))\nendef\n\nifeq ($(DUMP)$(TARGET_BUILD),)\n  -include $(LINUX_DIR)/.config\nendif\n\ndefine KernelPackage/depends\n  $(STAMP_BUILT): $(LINUX_DIR)/.config\n  define KernelPackage/depends\n  endef\nendef\n\ndefine KernelPackage\n  NAME:=$(1)\n  $(eval $(call Package/Default))\n  $(eval $(call KernelPackage/Defaults))\n  $(eval $(call KernelPackage/$(1)))\n  $(eval $(call KernelPackage/$(1)/$(BOARD)))\n  $(eval $(call KernelPackage/$(1)/$(BOARD)/$(if $(SUBTARGET),$(SUBTARGET),generic)))\n\n  define Package/kmod-$(1)\n    TITLE:=$(TITLE)\n    SECTION:=kernel\n    CATEGORY:=Kernel modules\n    DESCRIPTION:=$(DESCRIPTION)\n    EXTRA_DEPENDS:=kernel (=$(LINUX_VERSION)-$(LINUX_RELEASE)-$(LINUX_VERMAGIC))\n    VERSION:=$(LINUX_VERSION)$(if $(PKG_VERSION),+$(PKG_VERSION))-$(if $(PKG_RELEASE),$(PKG_RELEASE),$(LINUX_RELEASE))\n    PKGFLAGS:=$(PKGFLAGS)\n    $(call KernelPackage/$(1))\n    $(call KernelPackage/$(1)/$(BOARD))\n    $(call KernelPackage/$(1)/$(BOARD)/$(if $(SUBTARGET),$(SUBTARGET),generic))\n  endef\n\n  ifdef KernelPackage/$(1)/conffiles\n    define Package/kmod-$(1)/conffiles\n$(call KernelPackage/$(1)/conffiles)\n    endef\n  endif\n\n  ifdef KernelPackage/$(1)/description\n    define Package/kmod-$(1)/description\n$(call KernelPackage/$(1)/description)\n    endef\n  endif\n\n  ifdef KernelPackage/$(1)/config\n    define Package/kmod-$(1)/config\n$(call KernelPackage/$(1)/config)\n    endef\n  endif\n\n  $(call KernelPackage/depends)\n  $(call KernelPackage/hooks)\n\n  ifneq ($(if $(filter-out %=y %=n %=m,$(KCONFIG)),$(filter m y,$(foreach c,$(filter-out %=y %=n %=m,$(KCONFIG)),$($(c)))),.),)\n    define Package/kmod-$(1)/install\n\t\t  @for mod in $$(call version_filter,$$(FILES)); do \\\n\t\t\tif grep -q \"$$$$$$$${mod##$(LINUX_DIR)/}\" \"$(LINUX_DIR)/modules.builtin\"; then \\\n\t\t\t\techo \"NOTICE: module '$$$$$$$$mod' is built-in.\"; \\\n\t\t\telif [ -e $$$$$$$$mod ]; then \\\n\t\t\t\tmkdir -p $$(1)/$(MODULES_SUBDIR) ; \\\n\t\t\t\t$(CP) -L $$$$$$$$mod $$(1)/$(MODULES_SUBDIR)/ ; \\\n\t\t\telse \\\n\t\t\t\techo \"ERROR: module '$$$$$$$$mod' is missing.\" >&2; \\\n\t\t\t\texit 1; \\\n\t\t\tfi; \\\n\t\t  done;\n\t\t  $(call ModuleAutoLoad,$(1),$$(1),$(filter-out 0-,$(word 1,$(AUTOLOAD))-),$(filter-out 0,$(word 2,$(AUTOLOAD))),$(sort $(wordlist 3,99,$(AUTOLOAD))))\n\t\t  $(call KernelPackage/$(1)/install,$$(1))\n    endef\n  $(if $(CONFIG_PACKAGE_kmod-$(1)),\n    else\n      compile: $(1)-disabled\n      $(1)-disabled:\n\t\t@echo \"WARNING: kmod-$(1) is not available in the kernel config - generating empty package\" >&2\n\n      define Package/kmod-$(1)/install\n\t\ttrue\n      endef\n  )\n  endif\n  $$(eval $$(call BuildPackage,kmod-$(1)))\n\n  $$(IPKG_kmod-$(1)): $$(wildcard $$(call version_filter,$$(FILES)))\n\nendef\n\nversion_filter=$(if $(findstring @,$(1)),$(shell $(SCRIPT_DIR)/package-metadata.pl version_filter $(KERNEL_PATCHVER) $(1)),$(1))\n\n# 1: priority (optional)\n# 2: module list\n# 3: boot flag\ndefine AutoLoad\n  $(if $(1),$(1),0) $(if $(3),1,0) $(call version_filter,$(2))\nendef\n\n# 1: module list\n# 2: boot flag\ndefine AutoProbe\n  $(call AutoLoad,,$(1),$(2))\nendef\n\nversion_field=$(if $(word $(1),$(2)),$(word $(1),$(2)),0)\nkernel_version_merge=$$(( ($(call version_field,1,$(1)) << 24) + ($(call version_field,2,$(1)) << 16) + ($(call version_field,3,$(1)) << 8) + $(call version_field,4,$(1)) ))\n\nifdef DUMP\n  kernel_version_cmp=\nelse\n  kernel_version_cmp=$(shell [ $(call kernel_version_merge,$(call split_version,$(2))) $(1) $(call kernel_version_merge,$(call split_version,$(3))) ] && echo 1 )\nendif\n\nCompareKernelPatchVer=$(if $(call kernel_version_cmp,-$(2),$(1),$(3)),1,0)\n\nkernel_patchver_gt=$(call kernel_version_cmp,-gt,$(KERNEL_PATCHVER),$(1))\nkernel_patchver_ge=$(call kernel_version_cmp,-ge,$(KERNEL_PATCHVER),$(1))\nkernel_patchver_eq=$(call kernel_version_cmp,-eq,$(KERNEL_PATCHVER),$(1))\nkernel_patchver_le=$(call kernel_version_cmp,-le,$(KERNEL_PATCHVER),$(1))\nkernel_patchver_lt=$(call kernel_version_cmp,-lt,$(KERNEL_PATCHVER),$(1))\n\n"
  },
  {
    "path": "include/meson.mk",
    "content": "# To build your package using meson:\n#\n# include $(INCLUDE_DIR)/meson.mk\n# MESON_ARGS+=-Dfoo -Dbar=baz\n#\n# To pass additional environment variables to meson:\n#\n# MESON_VARS+=FOO=bar\n#\n# Default configure/compile/install targets are provided, but can be\n# overwritten if required:\n#\n# define Build/Configure\n#   $(call Build/Configure/Meson)\n#   ...\n# endef\n#\n# same for Build/Compile and Build/Install\n#\n# Host packages are built in the same fashion, just use these vars instead:\n#\n# MESON_HOST_ARGS+=-Dfoo -Dbar=baz\n# MESON_HOST_VARS+=FOO=bar\n\nMESON_DIR:=$(STAGING_DIR_HOST)/lib/meson\n\nMESON_HOST_BUILD_DIR:=$(HOST_BUILD_DIR)/openwrt-build\nMESON_HOST_VARS:=\nMESON_HOST_ARGS:=\n\nMESON_BUILD_DIR:=$(PKG_BUILD_DIR)/openwrt-build\nMESON_VARS:=\nMESON_ARGS:=\n\nifneq ($(findstring i386,$(CONFIG_ARCH)),)\nMESON_ARCH:=\"x86\"\nelse ifneq ($(findstring powerpc64,$(CONFIG_ARCH)),)\nMESON_ARCH:=\"ppc64\"\nelse ifneq ($(findstring powerpc,$(CONFIG_ARCH)),)\nMESON_ARCH:=\"ppc\"\nelse ifneq ($(findstring mips64el,$(CONFIG_ARCH)),)\nMESON_ARCH:=\"mips64\"\nelse ifneq ($(findstring mipsel,$(CONFIG_ARCH)),)\nMESON_ARCH:=\"mips\"\nelse ifneq ($(findstring armeb,$(CONFIG_ARCH)),)\nMESON_ARCH:=\"arm\"\nelse\nMESON_ARCH:=$(CONFIG_ARCH)\nendif\n\n# this is undefined for just x64_64\nifeq ($(origin CPU_TYPE),undefined)\nMESON_CPU:=\"generic\"\nelse\nMESON_CPU:=\"$(CPU_TYPE)$(if $(CPU_SUBTYPE),+$(CPU_SUBTYPE))\"\nendif\n\ndefine Meson\n\t$(2) $(STAGING_DIR_HOST)/bin/$(PYTHON) $(STAGING_DIR_HOST)/bin/meson.py $(1)\nendef\n\ndefine Meson/CreateNativeFile\n\t$(STAGING_DIR_HOST)/bin/sed \\\n\t\t-e \"s|@CC@|$(foreach BIN,$(HOSTCC),'$(BIN)',)|\" \\\n\t\t-e \"s|@CXX@|$(foreach BIN,$(HOSTCXX),'$(BIN)',)|\" \\\n\t\t-e \"s|@PKGCONFIG@|$(PKG_CONFIG)|\" \\\n\t\t-e \"s|@CMAKE@|$(STAGING_DIR_HOST)/bin/cmake|\" \\\n\t\t-e \"s|@PYTHON@|$(STAGING_DIR_HOST)/bin/python3|\" \\\n\t\t-e \"s|@CFLAGS@|$(foreach FLAG,$(HOST_CFLAGS) $(HOST_CPPFLAGS),'$(FLAG)',)|\" \\\n\t\t-e \"s|@CXXFLAGS@|$(foreach FLAG,$(HOST_CXXFLAGS) $(HOST_CPPFLAGS),'$(FLAG)',)|\" \\\n\t\t-e \"s|@LDFLAGS@|$(foreach FLAG,$(HOST_LDFLAGS),'$(FLAG)',)|\" \\\n\t\t-e \"s|@PREFIX@|$(HOST_BUILD_PREFIX)|\" \\\n\t\t< $(MESON_DIR)/openwrt-native.txt.in \\\n\t\t> $(1)\nendef\n\ndefine Meson/CreateCrossFile\n\t$(STAGING_DIR_HOST)/bin/sed \\\n\t\t-e \"s|@CC@|$(foreach BIN,$(TARGET_CC),'$(BIN)',)|\" \\\n\t\t-e \"s|@CXX@|$(foreach BIN,$(TARGET_CXX),'$(BIN)',)|\" \\\n\t\t-e \"s|@AR@|$(TARGET_AR)|\" \\\n\t\t-e \"s|@STRIP@|$(TARGET_CROSS)strip|\" \\\n\t\t-e \"s|@NM@|$(TARGET_NM)|\" \\\n\t\t-e \"s|@PKGCONFIG@|$(PKG_CONFIG)|\" \\\n\t\t-e \"s|@CMAKE@|$(STAGING_DIR_HOST)/bin/cmake|\" \\\n\t\t-e \"s|@PYTHON@|$(STAGING_DIR_HOST)/bin/python3|\" \\\n\t\t-e \"s|@CFLAGS@|$(foreach FLAG,$(TARGET_CFLAGS) $(EXTRA_CFLAGS) $(TARGET_CPPFLAGS) $(EXTRA_CPPFLAGS),'$(FLAG)',)|\" \\\n\t\t-e \"s|@CXXFLAGS@|$(foreach FLAG,$(TARGET_CXXFLAGS) $(EXTRA_CXXFLAGS) $(TARGET_CPPFLAGS) $(EXTRA_CPPFLAGS),'$(FLAG)',)|\" \\\n\t\t-e \"s|@LDFLAGS@|$(foreach FLAG,$(TARGET_LDFLAGS) $(EXTRA_LDFLAGS),'$(FLAG)',)|\" \\\n\t\t-e \"s|@ARCH@|$(MESON_ARCH)|\" \\\n\t\t-e \"s|@CPU@|$(MESON_CPU)|\" \\\n\t\t-e \"s|@ENDIAN@|$(if $(CONFIG_BIG_ENDIAN),big,little)|\" \\\n\t\t< $(MESON_DIR)/openwrt-cross.txt.in \\\n\t\t> $(1)\nendef\n\ndefine Host/Configure/Meson\n\t$(call Meson/CreateNativeFile,$(HOST_BUILD_DIR)/openwrt-native.txt)\n\t$(call Meson, \\\n\t\t--native-file $(HOST_BUILD_DIR)/openwrt-native.txt \\\n\t\t$(MESON_HOST_ARGS) \\\n\t\t$(MESON_HOST_BUILD_DIR) \\\n\t\t$(MESON_HOST_BUILD_DIR)/.., \\\n\t\t$(MESON_HOST_VARS))\nendef\n\ndefine Host/Compile/Meson\n\t+$(NINJA) -C $(MESON_HOST_BUILD_DIR) $(1)\nendef\n\ndefine Host/Install/Meson\n\t+$(NINJA) -C $(MESON_HOST_BUILD_DIR) install\nendef\n\ndefine Host/Uninstall/Meson\n\t+$(NINJA) -C $(MESON_HOST_BUILD_DIR) uninstall || true\nendef\n\ndefine Build/Configure/Meson\n\t$(call Meson/CreateNativeFile,$(PKG_BUILD_DIR)/openwrt-native.txt)\n\t$(call Meson/CreateCrossFile,$(PKG_BUILD_DIR)/openwrt-cross.txt)\n\t$(call Meson, \\\n\t\t--buildtype plain \\\n\t\t--native-file $(PKG_BUILD_DIR)/openwrt-native.txt \\\n\t\t--cross-file $(PKG_BUILD_DIR)/openwrt-cross.txt \\\n\t\t$(MESON_ARGS) \\\n\t\t$(MESON_BUILD_DIR) \\\n\t\t$(MESON_BUILD_DIR)/.., \\\n\t\t$(MESON_VARS))\nendef\n\ndefine Build/Compile/Meson\n\t+$(NINJA) -C $(MESON_BUILD_DIR) $(1)\nendef\n\ndefine Build/Install/Meson\n\t+DESTDIR=\"$(PKG_INSTALL_DIR)\" $(NINJA) -C $(MESON_BUILD_DIR) install\nendef\n\nHost/Configure=$(call Host/Configure/Meson)\nHost/Compile=$(call Host/Compile/Meson)\nHost/Install=$(call Host/Install/Meson)\nHost/Uninstall=$(call Host/Uninstall/Meson)\nBuild/Configure=$(call Build/Configure/Meson)\nBuild/Compile=$(call Build/Compile/Meson)\nBuild/Install=$(call Build/Install/Meson)\n"
  },
  {
    "path": "include/netfilter.mk",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2006-2020 OpenWrt.org\n\nifneq ($(__inc_netfilter),1)\n__inc_netfilter:=1\n\nifeq ($(NF_KMOD),1)\nP_V4:=ipv4/netfilter/\nP_V6:=ipv6/netfilter/\nP_XT:=netfilter/\nP_EBT:=bridge/netfilter/\nendif\n\n# 1: variable\n# 2: kconfig symbols\n# 3: file list\n# 4: version dependency\ndefine nf_add\n $(if $(4),ifeq ($$(strip $$(call CompareKernelPatchVer,$$(KERNEL_PATCHVER),$(firstword $(4)),$(lastword $(4)))),1))\n  $(1)-$$($(2)) += $(3)\n $(if $(4),endif)\n KCONFIG_$(1) = $(filter-out $(2),$(KCONFIG_$(1))) $(2)\nendef\n\n\n# core\n\n# kernel only\n$(eval $(if $(NF_KMOD),$(call nf_add,NF_REJECT,CONFIG_NF_REJECT_IPV4, $(P_V4)nf_reject_ipv4),))\n\n$(eval $(if $(NF_KMOD),$(call nf_add,NF_IPT,CONFIG_IP_NF_IPTABLES, $(P_V4)ip_tables),))\n$(eval $(if $(NF_KMOD),$(call nf_add,NF_IPT,CONFIG_NETFILTER_XTABLES, $(P_XT)x_tables),))\n\n$(eval $(if $(NF_KMOD),$(call nf_add,IPT_CORE,CONFIG_NETFILTER_XTABLES, $(P_XT)xt_tcpudp),))\n$(eval $(if $(NF_KMOD),$(call nf_add,IPT_CORE,CONFIG_IP_NF_FILTER, $(P_V4)iptable_filter),))\n$(eval $(if $(NF_KMOD),$(call nf_add,IPT_CORE,CONFIG_IP_NF_MANGLE, $(P_V4)iptable_mangle),))\n\n# userland only\n$(eval $(if $(NF_KMOD),,$(call nf_add,IPT_CORE,CONFIG_IP_NF_IPTABLES, xt_standard ipt_icmp xt_tcp xt_udp xt_comment xt_set xt_SET)))\n\n$(eval $(call nf_add,IPT_CORE,CONFIG_NETFILTER_XT_MATCH_LIMIT, $(P_XT)xt_limit))\n$(eval $(call nf_add,IPT_CORE,CONFIG_NETFILTER_XT_MATCH_MAC, $(P_XT)xt_mac))\n$(eval $(call nf_add,IPT_CORE,CONFIG_NETFILTER_XT_MATCH_MULTIPORT, $(P_XT)xt_multiport))\n$(eval $(call nf_add,IPT_CORE,CONFIG_NETFILTER_XT_MATCH_COMMENT, $(P_XT)xt_comment))\n\n#cluster\n$(eval $(call nf_add,IPT_CLUSTER,CONFIG_NETFILTER_XT_MATCH_CLUSTER, $(P_XT)xt_cluster))\n\n$(eval $(call nf_add,IPT_CORE,CONFIG_NETFILTER_XT_TARGET_LOG, $(P_XT)xt_LOG))\n$(eval $(call nf_add,IPT_CORE,CONFIG_NETFILTER_XT_TARGET_TCPMSS, $(P_XT)xt_TCPMSS))\n$(eval $(call nf_add,IPT_CORE,CONFIG_IP_NF_TARGET_REJECT, $(P_V4)ipt_REJECT))\n$(eval $(call nf_add,IPT_CORE,CONFIG_NETFILTER_XT_MATCH_TIME, $(P_XT)xt_time))\n$(eval $(call nf_add,IPT_CORE,CONFIG_NETFILTER_XT_MARK, $(P_XT)xt_mark))\n\n# kernel has xt_MARK.ko merged into xt_mark.ko, userspace is still separate\n# userland: xt_MARK.so\n$(eval $(if $(NF_KMOD),,$(call nf_add,IPT_CORE,CONFIG_NETFILTER_XT_MARK, $(P_XT)xt_MARK)))\n\n\n# conntrack\n\n# kernel only\n$(eval $(if $(NF_KMOD),$(call nf_add,NF_CONNTRACK,CONFIG_NF_CONNTRACK, $(P_XT)nf_conntrack),))\n$(eval $(if $(NF_KMOD),$(call nf_add,NF_CONNTRACK,CONFIG_NF_DEFRAG_IPV4, $(P_V4)nf_defrag_ipv4),))\n\n$(eval $(call nf_add,IPT_CONNTRACK,CONFIG_NETFILTER_XT_MATCH_STATE, $(P_XT)xt_state))\n$(eval $(call nf_add,IPT_CONNTRACK,CONFIG_NETFILTER_XT_TARGET_CT, $(P_XT)xt_CT))\n$(eval $(call nf_add,IPT_CONNTRACK,CONFIG_NETFILTER_XT_MATCH_CONNTRACK, $(P_XT)xt_conntrack))\n\n\n# conntrack-extra\n\n$(eval $(call nf_add,IPT_CONNTRACK_EXTRA,CONFIG_NETFILTER_XT_MATCH_CONNBYTES, $(P_XT)xt_connbytes))\n$(eval $(call nf_add,IPT_CONNTRACK_EXTRA,CONFIG_NETFILTER_XT_MATCH_CONNLIMIT, $(P_XT)xt_connlimit))\n$(eval $(call nf_add,IPT_CONNTRACK_EXTRA,CONFIG_NETFILTER_CONNCOUNT, $(P_XT)nf_conncount))\n$(eval $(call nf_add,IPT_CONNTRACK_EXTRA,CONFIG_NETFILTER_XT_CONNMARK, $(P_XT)xt_connmark))\n$(eval $(call nf_add,IPT_CONNTRACK_EXTRA,CONFIG_NETFILTER_XT_MATCH_HELPER, $(P_XT)xt_helper))\n$(eval $(call nf_add,IPT_CONNTRACK_EXTRA,CONFIG_NETFILTER_XT_MATCH_RECENT, $(P_XT)xt_recent))\n\n$(eval $(if $(NF_KMOD),,$(call nf_add,IPT_CONNTRACK_EXTRA,CONFIG_NETFILTER_XT_CONNMARK, $(P_XT)xt_CONNMARK)))\n\n#conntrack-label\n\n$(eval $(call nf_add,IPT_CONNTRACK_LABEL,CONFIG_NETFILTER_XT_MATCH_CONNLABEL, $(P_XT)xt_connlabel))\n\n# extra\n\n$(eval $(call nf_add,IPT_EXTRA,CONFIG_NETFILTER_XT_MATCH_ADDRTYPE, $(if $(NF_KMOD),$(P_XT)xt_addrtype,$(P_XT)ipt_addrtype)))\n$(eval $(call nf_add,IPT_EXTRA,CONFIG_NETFILTER_XT_MATCH_OWNER, $(P_XT)xt_owner))\n$(eval $(call nf_add,IPT_EXTRA,CONFIG_NETFILTER_XT_MATCH_PKTTYPE, $(P_XT)xt_pkttype))\n$(eval $(call nf_add,IPT_EXTRA,CONFIG_NETFILTER_XT_MATCH_QUOTA, $(P_XT)xt_quota))\n$(eval $(call nf_add,IPT_EXTRA,CONFIG_NETFILTER_XT_MATCH_CGROUP, $(P_XT)xt_cgroup))\n\n#$(eval $(call nf_add,IPT_EXTRA,CONFIG_IP_NF_TARGET_ROUTE, $(P_V4)ipt_ROUTE))\n\n# physdev\n\n$(eval $(call nf_add,IPT_PHYSDEV,CONFIG_NETFILTER_XT_MATCH_PHYSDEV, $(P_XT)xt_physdev))\n\n# filter\n\n$(eval $(call nf_add,IPT_FILTER,CONFIG_NETFILTER_XT_MATCH_STRING, $(P_XT)xt_string))\n$(eval $(call nf_add,IPT_FILTER,CONFIG_NETFILTER_XT_MATCH_BPF, $(P_XT)xt_bpf))\n\n\n# ipopt\n\n$(eval $(call nf_add,IPT_IPOPT,CONFIG_NETFILTER_XT_MATCH_DSCP, $(P_XT)xt_dscp))\n$(eval $(call nf_add,IPT_IPOPT,CONFIG_NETFILTER_XT_TARGET_DSCP, $(P_XT)xt_DSCP))\n$(eval $(call nf_add,IPT_HASHLIMIT,CONFIG_NETFILTER_XT_MATCH_HASHLIMIT, $(P_XT)xt_hashlimit))\n$(eval $(call nf_add,IPT_RPFILTER,CONFIG_IP_NF_MATCH_RPFILTER, $(P_V4)ipt_rpfilter))\n$(eval $(call nf_add,IPT_RPFILTER,CONFIG_IP6_NF_MATCH_RPFILTER, $(P_V6)ip6t_rpfilter))\n$(eval $(call nf_add,IPT_IPOPT,CONFIG_NETFILTER_XT_MATCH_LENGTH, $(P_XT)xt_length))\n$(eval $(call nf_add,IPT_IPOPT,CONFIG_NETFILTER_XT_MATCH_STATISTIC, $(P_XT)xt_statistic))\n$(eval $(call nf_add,IPT_IPOPT,CONFIG_NETFILTER_XT_MATCH_TCPMSS, $(P_XT)xt_tcpmss))\n\n$(eval $(call nf_add,IPT_IPOPT,CONFIG_NETFILTER_XT_TARGET_CLASSIFY, $(P_XT)xt_CLASSIFY))\n$(eval $(call nf_add,IPT_IPOPT,CONFIG_IP_NF_TARGET_ECN, $(P_V4)ipt_ECN))\n\n$(eval $(call nf_add,IPT_IPOPT,CONFIG_NETFILTER_XT_MATCH_ECN, $(P_XT)xt_ecn))\n\n# userland only\n$(eval $(if $(NF_KMOD),,$(call nf_add,IPT_IPOPT,CONFIG_NETFILTER_XT_MATCH_DSCP, xt_tos)))\n$(eval $(if $(NF_KMOD),,$(call nf_add,IPT_IPOPT,CONFIG_NETFILTER_XT_TARGET_DSCP, xt_TOS)))\n$(eval $(if $(NF_KMOD),,$(call nf_add,IPT_IPOPT,CONFIG_NETFILTER_XT_MATCH_HL, ipt_ttl)))\n$(eval $(if $(NF_KMOD),,$(call nf_add,IPT_IPOPT,CONFIG_NETFILTER_XT_TARGET_HL, ipt_TTL)))\n\n$(eval $(call nf_add,IPT_IPOPT,CONFIG_NETFILTER_XT_MATCH_HL, $(P_XT)xt_hl))\n$(eval $(call nf_add,IPT_IPOPT,CONFIG_NETFILTER_XT_TARGET_HL, $(P_XT)xt_HL))\n\n# iprange\n$(eval $(call nf_add,IPT_IPRANGE,CONFIG_NETFILTER_XT_MATCH_IPRANGE, $(P_XT)xt_iprange))\n\n#clusterip\n$(eval $(call nf_add,IPT_CLUSTERIP,CONFIG_IP_NF_TARGET_CLUSTERIP, $(P_V4)ipt_CLUSTERIP))\n\n# ipsec\n$(eval $(call nf_add,IPT_IPSEC,CONFIG_IP_NF_MATCH_AH, $(P_V4)ipt_ah))\n$(eval $(call nf_add,IPT_IPSEC,CONFIG_NETFILTER_XT_MATCH_ESP, $(P_XT)xt_esp))\n$(eval $(call nf_add,IPT_IPSEC,CONFIG_NETFILTER_XT_MATCH_POLICY, $(P_XT)xt_policy))\n\n# flow offload support\n$(eval $(call nf_add,IPT_FLOW,CONFIG_NETFILTER_XT_TARGET_FLOWOFFLOAD, $(P_XT)xt_FLOWOFFLOAD))\n\n# IPv6\n\n# kernel only\n$(eval $(if $(NF_KMOD),$(call nf_add,NF_REJECT6,CONFIG_NF_REJECT_IPV6, $(P_V6)nf_reject_ipv6),))\n\n$(eval $(if $(NF_KMOD),$(call nf_add,NF_IPT6,CONFIG_IP6_NF_IPTABLES, $(P_V6)ip6_tables),))\n\n$(eval $(if $(NF_KMOD),$(call nf_add,NF_CONNTRACK,CONFIG_NF_DEFRAG_IPV6, $(P_V6)nf_defrag_ipv6),))\n\n$(eval $(if $(NF_KMOD),$(call nf_add,IPT_IPV6,CONFIG_IP6_NF_FILTER, $(P_V6)ip6table_filter),))\n$(eval $(if $(NF_KMOD),$(call nf_add,IPT_IPV6,CONFIG_IP6_NF_MANGLE, $(P_V6)ip6table_mangle),))\n\n$(eval $(if $(NF_KMOD),,$(call nf_add,IPT_IPV6,CONFIG_IP6_NF_IPTABLES, ip6t_icmp6)))\n\n\n$(eval $(call nf_add,IPT_IPV6,CONFIG_IP6_NF_TARGET_REJECT, $(P_V6)ip6t_REJECT))\n\n# ipv6 extra\n$(eval $(call nf_add,IPT_IPV6_EXTRA,CONFIG_IP6_NF_MATCH_IPV6HEADER, $(P_V6)ip6t_ipv6header))\n$(eval $(call nf_add,IPT_IPV6_EXTRA,CONFIG_IP6_NF_MATCH_AH, $(P_V6)ip6t_ah))\n$(eval $(call nf_add,IPT_IPV6_EXTRA,CONFIG_IP6_NF_MATCH_MH, $(P_V6)ip6t_mh))\n$(eval $(call nf_add,IPT_IPV6_EXTRA,CONFIG_IP6_NF_MATCH_EUI64, $(P_V6)ip6t_eui64))\n$(eval $(call nf_add,IPT_IPV6_EXTRA,CONFIG_IP6_NF_MATCH_OPTS, $(P_V6)ip6t_hbh))\n$(eval $(call nf_add,IPT_IPV6_EXTRA,CONFIG_IP6_NF_MATCH_FRAG, $(P_V6)ip6t_frag))\n$(eval $(call nf_add,IPT_IPV6_EXTRA,CONFIG_IP6_NF_MATCH_RT, $(P_V6)ip6t_rt))\n\n# log\n\n$(eval $(call nf_add,NF_LOG,CONFIG_NF_LOG_COMMON, $(P_XT)nf_log_common, lt 5.13))\n$(eval $(call nf_add,NF_LOG,CONFIG_NF_LOG_IPV4, $(P_V4)nf_log_ipv4, lt 5.13))\n$(eval $(call nf_add,NF_LOG,CONFIG_NF_LOG_SYSLOG, $(P_XT)nf_log_syslog, ge 5.13))\n$(eval $(if $(NF_KMOD),$(call nf_add,NF_LOG6,CONFIG_NF_LOG_IPV6, $(P_V6)nf_log_ipv6,lt 5.13),))\n\n# nat\n\n# kernel only\n$(eval $(if $(NF_KMOD),$(call nf_add,NF_NAT,CONFIG_NF_NAT, $(P_XT)nf_nat),))\n\n$(eval $(if $(NF_KMOD),$(call nf_add,IPT_NAT,CONFIG_NETFILTER_XT_NAT, $(P_XT)xt_nat),))\n$(eval $(if $(NF_KMOD),$(call nf_add,IPT_NAT,CONFIG_IP_NF_NAT, $(P_V4)iptable_nat),))\n$(eval $(if $(NF_KMOD),$(call nf_add,IPT_NAT6,CONFIG_IP6_NF_NAT, $(P_V6)ip6table_nat),))\n$(eval $(if $(NF_KMOD),$(call nf_add,IPT_NAT6,CONFIG_IP6_NF_TARGET_NPT, $(P_V6)ip6t_NPT),))\n\n# userland only\n$(eval $(if $(NF_KMOD),,$(call nf_add,IPT_NAT,CONFIG_NF_NAT, ipt_SNAT ipt_DNAT)))\n$(eval $(if $(NF_KMOD),,$(call nf_add,IPT_NAT6,CONFIG_IP6_NF_TARGET_NPT, ip6t_DNPT ip6t_SNPT)))\n\n$(eval $(call nf_add,IPT_NAT,CONFIG_NETFILTER_XT_TARGET_MASQUERADE, $(P_XT)xt_MASQUERADE))\n$(eval $(call nf_add,IPT_NAT,CONFIG_NETFILTER_XT_TARGET_REDIRECT, $(P_XT)xt_REDIRECT))\n\n\n# nat-extra\n\n$(eval $(call nf_add,IPT_NAT_EXTRA,CONFIG_IP_NF_TARGET_NETMAP, $(P_XT)xt_NETMAP))\n\n\n# nathelper\n\n$(eval $(call nf_add,NF_NATHELPER,CONFIG_NF_CONNTRACK_FTP, $(P_XT)nf_conntrack_ftp))\n$(eval $(call nf_add,NF_NATHELPER,CONFIG_NF_NAT_FTP, $(P_XT)nf_nat_ftp))\n\n\n# nathelper-extra\n\n$(eval $(call nf_add,NF_NATHELPER_EXTRA,CONFIG_NF_CONNTRACK_BROADCAST, $(P_XT)nf_conntrack_broadcast))\n$(eval $(call nf_add,NF_NATHELPER_EXTRA,CONFIG_NF_CONNTRACK_AMANDA, $(P_XT)nf_conntrack_amanda))\n$(eval $(call nf_add,NF_NATHELPER_EXTRA,CONFIG_NF_NAT_AMANDA, $(P_XT)nf_nat_amanda))\n$(eval $(call nf_add,NF_NATHELPER_EXTRA,CONFIG_NF_CONNTRACK_H323, $(P_XT)nf_conntrack_h323))\n$(eval $(call nf_add,NF_NATHELPER_EXTRA,CONFIG_NF_NAT_H323, $(P_V4)nf_nat_h323))\n$(eval $(call nf_add,NF_NATHELPER_EXTRA,CONFIG_NF_CONNTRACK_PPTP, $(P_XT)nf_conntrack_pptp))\n$(eval $(call nf_add,NF_NATHELPER_EXTRA,CONFIG_NF_NAT_PPTP, $(P_V4)nf_nat_pptp))\n$(eval $(call nf_add,NF_NATHELPER_EXTRA,CONFIG_NF_CONNTRACK_SIP, $(P_XT)nf_conntrack_sip))\n$(eval $(call nf_add,NF_NATHELPER_EXTRA,CONFIG_NF_NAT_SIP, $(P_XT)nf_nat_sip))\n$(eval $(call nf_add,NF_NATHELPER_EXTRA,CONFIG_NF_CONNTRACK_SNMP, $(P_XT)nf_conntrack_snmp))\n$(eval $(call nf_add,NF_NATHELPER_EXTRA,CONFIG_NF_NAT_SNMP_BASIC, $(P_V4)nf_nat_snmp_basic))\n$(eval $(call nf_add,NF_NATHELPER_EXTRA,CONFIG_NF_CONNTRACK_TFTP, $(P_XT)nf_conntrack_tftp))\n$(eval $(call nf_add,NF_NATHELPER_EXTRA,CONFIG_NF_NAT_TFTP, $(P_XT)nf_nat_tftp))\n$(eval $(call nf_add,NF_NATHELPER_EXTRA,CONFIG_NF_CONNTRACK_IRC, $(P_XT)nf_conntrack_irc))\n$(eval $(call nf_add,NF_NATHELPER_EXTRA,CONFIG_NF_NAT_IRC, $(P_XT)nf_nat_irc))\n\n\n# ulog\n\n$(eval $(call nf_add,IPT_ULOG,CONFIG_IP_NF_TARGET_ULOG, $(P_V4)ipt_ULOG))\n\n\n# nflog\n\n$(eval $(call nf_add,IPT_NFLOG,CONFIG_NETFILTER_XT_TARGET_NFLOG, $(P_XT)xt_NFLOG))\n\n\n# nfqueue\n\n$(eval $(call nf_add,IPT_NFQUEUE,CONFIG_NETFILTER_XT_TARGET_NFQUEUE, $(P_XT)xt_NFQUEUE))\n\n\n# debugging\n\n$(eval $(call nf_add,IPT_DEBUG,CONFIG_NETFILTER_XT_TARGET_TRACE, $(P_XT)xt_TRACE))\n\n# socket\n$(eval $(call nf_add,NF_SOCKET,CONFIG_NF_SOCKET_IPV4, $(P_V4)nf_socket_ipv4))\n$(eval $(call nf_add,NF_SOCKET,CONFIG_NF_SOCKET_IPV6, $(P_V6)nf_socket_ipv6))\n$(eval $(call nf_add,IPT_SOCKET,CONFIG_NETFILTER_XT_MATCH_SOCKET, $(P_XT)xt_socket))\n\n# tproxy\n$(eval $(call nf_add,NF_TPROXY,CONFIG_NF_TPROXY_IPV4, $(P_V4)nf_tproxy_ipv4))\n$(eval $(call nf_add,NF_TPROXY,CONFIG_NF_TPROXY_IPV6, $(P_V6)nf_tproxy_ipv6))\n$(eval $(call nf_add,IPT_TPROXY,CONFIG_NETFILTER_XT_TARGET_TPROXY, $(P_XT)xt_TPROXY))\n\n# led\n$(eval $(call nf_add,IPT_LED,CONFIG_NETFILTER_XT_TARGET_LED, $(P_XT)xt_LED))\n\n# tee\n\n$(eval $(call nf_add,IPT_TEE,CONFIG_NETFILTER_XT_TARGET_TEE, $(P_XT)xt_TEE))\n$(eval $(if $(NF_KMOD),$(call nf_add,IPT_TEE,CONFIG_NF_DUP_IPV4, $(P_V4)nf_dup_ipv4),))\n$(eval $(if $(NF_KMOD),$(call nf_add,IPT_TEE,CONFIG_NF_DUP_IPV6, $(P_V6)nf_dup_ipv6),))\n\n# u32\n\n$(eval $(call nf_add,IPT_U32,CONFIG_NETFILTER_XT_MATCH_U32, $(P_XT)xt_u32))\n\n# checksum\n\n$(eval $(call nf_add,IPT_CHECKSUM,CONFIG_NETFILTER_XT_TARGET_CHECKSUM, $(P_XT)xt_CHECKSUM))\n\n\n# netlink\n\n$(eval $(call nf_add,NFNETLINK,CONFIG_NETFILTER_NETLINK, $(P_XT)nfnetlink))\n\n# nflog\n\n$(eval $(call nf_add,NFNETLINK_LOG,CONFIG_NETFILTER_NETLINK_LOG, $(P_XT)nfnetlink_log))\n\n# nfqueue\n\n$(eval $(call nf_add,NFNETLINK_QUEUE,CONFIG_NETFILTER_NETLINK_QUEUE, $(P_XT)nfnetlink_queue))\n\n#\n# ebtables\n#\n\n$(eval $(if $(NF_KMOD),$(call nf_add,EBTABLES,CONFIG_BRIDGE_NF_EBTABLES, $(P_EBT)ebtables),))\n\n# ebtables: tables\n$(eval $(call nf_add,EBTABLES,CONFIG_BRIDGE_EBT_BROUTE, $(P_EBT)ebtable_broute))\n$(eval $(call nf_add,EBTABLES,CONFIG_BRIDGE_EBT_T_FILTER, $(P_EBT)ebtable_filter))\n$(eval $(call nf_add,EBTABLES,CONFIG_BRIDGE_EBT_T_NAT, $(P_EBT)ebtable_nat))\n\n# ebtables: matches\n$(eval $(call nf_add,EBTABLES,CONFIG_BRIDGE_EBT_802_3, $(P_EBT)ebt_802_3))\n$(eval $(call nf_add,EBTABLES,CONFIG_BRIDGE_EBT_AMONG, $(P_EBT)ebt_among))\n$(eval $(call nf_add,EBTABLES_IP4,CONFIG_BRIDGE_EBT_ARP, $(P_EBT)ebt_arp))\n$(eval $(call nf_add,EBTABLES_IP4,CONFIG_BRIDGE_EBT_IP, $(P_EBT)ebt_ip))\n$(eval $(call nf_add,EBTABLES_IP6,CONFIG_BRIDGE_EBT_IP6, $(P_EBT)ebt_ip6))\n$(eval $(call nf_add,EBTABLES,CONFIG_BRIDGE_EBT_LIMIT, $(P_EBT)ebt_limit))\n$(eval $(call nf_add,EBTABLES,CONFIG_BRIDGE_EBT_MARK, $(P_EBT)ebt_mark_m))\n$(eval $(call nf_add,EBTABLES,CONFIG_BRIDGE_EBT_PKTTYPE, $(P_EBT)ebt_pkttype))\n$(eval $(call nf_add,EBTABLES,CONFIG_BRIDGE_EBT_STP, $(P_EBT)ebt_stp))\n$(eval $(call nf_add,EBTABLES,CONFIG_BRIDGE_EBT_VLAN, $(P_EBT)ebt_vlan))\n\n# targets\n$(eval $(call nf_add,EBTABLES_IP4,CONFIG_BRIDGE_EBT_ARPREPLY, $(P_EBT)ebt_arpreply))\n$(eval $(call nf_add,EBTABLES,CONFIG_BRIDGE_EBT_MARK_T, $(P_EBT)ebt_mark))\n$(eval $(call nf_add,EBTABLES_IP4,CONFIG_BRIDGE_EBT_DNAT, $(P_EBT)ebt_dnat))\n$(eval $(call nf_add,EBTABLES,CONFIG_BRIDGE_EBT_REDIRECT, $(P_EBT)ebt_redirect))\n$(eval $(call nf_add,EBTABLES_IP4,CONFIG_BRIDGE_EBT_SNAT, $(P_EBT)ebt_snat))\n\n# watchers\n$(eval $(call nf_add,EBTABLES_WATCHERS,CONFIG_BRIDGE_EBT_LOG, $(P_EBT)ebt_log))\n$(eval $(call nf_add,EBTABLES_WATCHERS,CONFIG_BRIDGE_EBT_ULOG, $(P_EBT)ebt_ulog))\n$(eval $(call nf_add,EBTABLES_WATCHERS,CONFIG_BRIDGE_EBT_NFLOG, $(P_EBT)ebt_nflog))\n$(eval $(call nf_add,EBTABLES_WATCHERS,CONFIG_BRIDGE_EBT_NFQUEUE, $(P_EBT)ebt_nfqueue))\n\n# nftables\n$(eval $(if $(NF_KMOD),$(call nf_add,NFT_CORE,CONFIG_NF_TABLES, $(P_XT)nf_tables),))\n$(eval $(if $(NF_KMOD),$(call nf_add,NFT_CORE,CONFIG_NF_TABLES_SET, $(P_XT)nf_tables_set),))\n$(eval $(if $(NF_KMOD),$(call nf_add,NFT_CORE,CONFIG_NFT_COUNTER, $(P_XT)nft_counter),))\n$(eval $(if $(NF_KMOD),$(call nf_add,NFT_CORE,CONFIG_NFT_CT, $(P_XT)nft_ct),))\n$(eval $(if $(NF_KMOD),$(call nf_add,NFT_CORE,CONFIG_NFT_HASH, $(P_XT)nft_hash),))\n$(eval $(if $(NF_KMOD),$(call nf_add,NFT_CORE,CONFIG_NFT_LIMIT, $(P_XT)nft_limit),))\n$(eval $(if $(NF_KMOD),$(call nf_add,NFT_CORE,CONFIG_NFT_LOG, $(P_XT)nft_log),))\n$(eval $(if $(NF_KMOD),$(call nf_add,NFT_CORE,CONFIG_NFT_META, $(P_XT)nft_meta),))\n$(eval $(if $(NF_KMOD),$(call nf_add,NFT_CORE,CONFIG_NFT_NUMGEN, $(P_XT)nft_numgen),))\n$(eval $(if $(NF_KMOD),$(call nf_add,NFT_CORE,CONFIG_NFT_OBJREF, $(P_XT)nft_objref),))\n$(eval $(if $(NF_KMOD),$(call nf_add,NFT_CORE,CONFIG_NFT_QUOTA, $(P_XT)nft_quota),))\n$(eval $(if $(NF_KMOD),$(call nf_add,NFT_CORE,CONFIG_NFT_REDIR, $(P_XT)nft_redir),))\n$(eval $(if $(NF_KMOD),$(call nf_add,NFT_CORE,CONFIG_NFT_REJECT, $(P_XT)nft_reject $(P_V4)nft_reject_ipv4 $(P_V6)nft_reject_ipv6),))\n$(eval $(if $(NF_KMOD),$(call nf_add,NFT_CORE,CONFIG_NFT_REJECT_INET, $(P_XT)nft_reject_inet),))\n\n$(eval $(if $(NF_KMOD),$(call nf_add,NFT_BRIDGE,CONFIG_NFT_BRIDGE_META, $(P_EBT)nft_meta_bridge),))\n$(eval $(if $(NF_KMOD),$(call nf_add,NFT_BRIDGE,CONFIG_NFT_BRIDGE_REJECT, $(P_EBT)nft_reject_bridge),))\n$(eval $(if $(NF_KMOD),$(call nf_add,NFT_BRIDGE,CONFIG_NF_CONNTRACK_BRIDGE, $(P_EBT)nf_conntrack_bridge),))\n\n$(eval $(if $(NF_KMOD),$(call nf_add,NFT_NAT,CONFIG_NFT_NAT, $(P_XT)nft_nat),))\n$(eval $(if $(NF_KMOD),$(call nf_add,NFT_NAT,CONFIG_NFT_NAT, $(P_XT)nft_chain_nat),))\n$(eval $(if $(NF_KMOD),$(call nf_add,NFT_NAT,CONFIG_NFT_REDIR_IPV4, $(P_V4)nft_redir_ipv4),))\n$(eval $(if $(NF_KMOD),$(call nf_add,NFT_NAT,CONFIG_NFT_MASQ, $(P_XT)nft_masq),))\n$(eval $(if $(NF_KMOD),$(call nf_add,NFT_NAT,CONFIG_NFT_MASQ_IPV4, $(P_V4)nft_masq_ipv4),))\n\n$(eval $(if $(NF_KMOD),$(call nf_add,NFT_NAT6,CONFIG_NFT_REDIR_IPV6, $(P_V6)nft_redir_ipv6),))\n$(eval $(if $(NF_KMOD),$(call nf_add,NFT_NAT6,CONFIG_NFT_MASQ_IPV6, $(P_V6)nft_masq_ipv6),))\n\n$(eval $(if $(NF_KMOD),$(call nf_add,NFT_FIB,CONFIG_NFT_FIB, $(P_XT)nft_fib),))\n$(eval $(if $(NF_KMOD),$(call nf_add,NFT_FIB,CONFIG_NFT_FIB_INET, $(P_XT)nft_fib_inet),))\n$(eval $(if $(NF_KMOD),$(call nf_add,NFT_FIB,CONFIG_NFT_FIB_IPV4, $(P_V4)nft_fib_ipv4),))\n$(eval $(if $(NF_KMOD),$(call nf_add,NFT_FIB,CONFIG_NFT_FIB_IPV6, $(P_V6)nft_fib_ipv6),))\n\n$(eval $(if $(NF_KMOD),$(call nf_add,NFT_QUEUE,CONFIG_NFT_QUEUE, $(P_XT)nft_queue),))\n\n$(eval $(if $(NF_KMOD),$(call nf_add,NFT_SOCKET,CONFIG_NFT_SOCKET, $(P_XT)nft_socket),))\n\n$(eval $(if $(NF_KMOD),$(call nf_add,NFT_TPROXY,CONFIG_NFT_TPROXY, $(P_XT)nft_tproxy),))\n\n$(eval $(if $(NF_KMOD),$(call nf_add,NFT_COMPAT,CONFIG_NFT_COMPAT, $(P_XT)nft_compat),))\n\n# userland only\nIPT_BUILTIN += $(NF_IPT-y) $(NF_IPT-m)\nIPT_BUILTIN += $(IPT_CORE-y) $(IPT_CORE-m)\nIPT_BUILTIN += $(NF_CONNTRACK-y)\nIPT_BUILTIN += $(NF_CONNTRACK6-y)\nIPT_BUILTIN += $(IPT_CONNTRACK-y)\nIPT_BUILTIN += $(IPT_CONNTRACK_EXTRA-y)\nIPT_BUILTIN += $(IPT_EXTRA-y)\nIPT_BUILTIN += $(IPT_PHYSDEV-y)\nIPT_BUILTIN += $(IPT_FILTER-y)\nIPT_BUILTIN += $(IPT_FLOW-y) $(IPT_FLOW-m)\nIPT_BUILTIN += $(IPT_IPOPT-y)\nIPT_BUILTIN += $(IPT_IPRANGE-y)\nIPT_BUILTIN += $(IPT_CLUSTER-y)\nIPT_BUILTIN += $(IPT_CLUSTERIP-y)\nIPT_BUILTIN += $(IPT_IPSEC-y)\nIPT_BUILTIN += $(IPT_IPV6-y) $(IPT_IPV6-m)\nIPT_BUILTIN += $(NF_NAT-y)\nIPT_BUILTIN += $(NF_NAT6-y)\nIPT_BUILTIN += $(IPT_NAT-y)\nIPT_BUILTIN += $(IPT_NAT6-y)\nIPT_BUILTIN += $(IPT_NAT_EXTRA-y)\nIPT_BUILTIN += $(NF_NATHELPER-y)\nIPT_BUILTIN += $(NF_NATHELPER_EXTRA-y)\nIPT_BUILTIN += $(IPT_ULOG-y)\nIPT_BUILTIN += $(IPT_TPROXY-y)\nIPT_BUILTIN += $(NFNETLINK-y)\nIPT_BUILTIN += $(NFNETLINK_LOG-y)\nIPT_BUILTIN += $(NFNETLINK_QUEUE-y)\nIPT_BUILTIN += $(EBTABLES-y)\nIPT_BUILTIN += $(EBTABLES_IP4-y)\nIPT_BUILTIN += $(EBTABLES_IP6-y)\nIPT_BUILTIN += $(EBTABLES_WATCHERS-y)\n\nendif # __inc_netfilter\n"
  },
  {
    "path": "include/nls.mk",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2011-2020 OpenWrt.org\n\n# iconv full\nifeq ($(CONFIG_BUILD_NLS),y)\n\tICONV_PREFIX:=$(STAGING_DIR)/usr/lib/libiconv-full\n\tICONV_FULL:=1\n\n\tINTL_PREFIX:=$(STAGING_DIR)/usr/lib/libintl-full\n\tINTL_FULL:=1\n\n# iconv stub\nelse\n\tICONV_PREFIX:=$(STAGING_DIR)/usr/lib/libiconv-stub\n\tICONV_FULL:=\n\n\tINTL_PREFIX:=$(STAGING_DIR)/usr/lib/libintl-stub\n\tINTL_FULL:=\nendif\n\nPKG_CONFIG_DEPENDS += CONFIG_BUILD_NLS\nPKG_BUILD_DEPENDS += !BUILD_NLS:libiconv\n\nICONV_DEPENDS:=+BUILD_NLS:libiconv-full\nICONV_CFLAGS:=-I$(ICONV_PREFIX)/include\nICONV_CPPFLAGS:=-I$(ICONV_PREFIX)/include\nICONV_LDFLAGS:=-L$(ICONV_PREFIX)/lib -Wl,-rpath-link=$(ICONV_PREFIX)/lib\n\nINTL_DEPENDS:=+BUILD_NLS:libintl-full\nINTL_CFLAGS:=-I$(INTL_PREFIX)/include\nINTL_CPPFLAGS:=-I$(INTL_PREFIX)/include\nINTL_LDFLAGS:=-L$(INTL_PREFIX)/lib -Wl,-rpath-link=$(INTL_PREFIX)/lib\n\nTARGET_CFLAGS += $(ICONV_CFLAGS) $(INTL_CFLAGS)\nTARGET_CPPFLAGS += $(ICONV_CPPFLAGS) $(INTL_CPPFLAGS)\nTARGET_LDFLAGS += $(ICONV_LDFLAGS) $(INTL_LDFLAGS)\n"
  },
  {
    "path": "include/openssl-engine.mk",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2022 Enéas Ulir de Queiroz\n\nENGINES_DIR=engines-1.1\n\ndefine Package/openssl/engine/Default\n  SECTION:=libs\n  CATEGORY:=Libraries\n  SUBMENU:=SSL\n  DEPENDS:=libopenssl @OPENSSL_ENGINE +libopenssl-conf\nendef\n\n# 1 = engine name\n# 2 - package name, defaults to libopenssl-$(1)\ndefine Package/openssl/add-engine\n  OSSL_ENG_PKG:=$(if $(2),$(2),libopenssl-$(1))\n  Package/$$(OSSL_ENG_PKG)/conffiles:=/etc/ssl/engines.cnf.d/$(1).cnf\n\n  define Package/$$(OSSL_ENG_PKG)/install\n\t$$(INSTALL_DIR)  $$(1)/usr/lib/$(ENGINES_DIR)\n\t$$(INSTALL_BIN)  $$(PKG_INSTALL_DIR)/usr/lib/$(ENGINES_DIR)/$(1).so \\\n\t\t\t $$(1)/usr/lib/$(ENGINES_DIR)\n\t$$(INSTALL_DIR)  $$(1)/etc/ssl/engines.cnf.d\n\t$$(INSTALL_DATA) ./files/$(1).cnf $$(1)/etc/ssl/engines.cnf.d/\n  endef\n\n  define Package/$$(OSSL_ENG_PKG)/postinst :=\n#!/bin/sh\nOPENSSL_UCI=\"$$$${IPKG_INSTROOT}/etc/config/openssl\"\n\n[ -z \"$$$${IPKG_INSTROOT}\" ] && uci -q get openssl.$(1) >/dev/null && exit 0\n\ncat << EOF >> \"$$$${OPENSSL_UCI}\"\n\nconfig engine '$(1)'\n\toption enabled '1'\nEOF\n\n[ -n \"$$$${IPKG_INSTROOT}\" ] || /etc/init.d/openssl reload\n  endef\n\n  define Package/$$(OSSL_ENG_PKG)/postrm :=\n#!/bin/sh\n[ -n \"$$$${IPKG_INSTROOT}\" ] && exit 0\nuci delete openssl.$(1)\nuci commit openssl\n/etc/init.d/openssl reload\n  endef\nendef\n"
  },
  {
    "path": "include/package-bin.mk",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2007-2020 OpenWrt.org\n\nifeq ($(DUMP),)\n  define BuildTarget/bin\n    TARGET_VARIANT=$(if $(ALL_VARIANTS),$(if $(VARIANT),$(filter-out *,$(VARIANT)),$(firstword $(ALL_VARIANTS))))\n    ifeq ($(if $(TARGET_VARIANT),$(BUILD_VARIANT)),$(TARGET_VARIANT))\n    ifdef Package/$(1)/install\n      ifneq ($(CONFIG_PACKAGE_$(1))$(DEVELOPER),)\n        $(_pkg_target)compile: $(PKG_BUILD_DIR)/.pkgdir/$(1).installed\n        compile: install-bin-$(1)\n      else\n        compile: $(1)-disabled\n        $(1)-disabled:\n\t\t@echo \"WARNING: skipping $(1) -- package not selected\" >&2\n      endif\n    endif\n    endif\n\n    $(PKG_BUILD_DIR)/.pkgdir/$(1).installed: $(STAMP_BUILT)\n\t\trm -rf $(PKG_BUILD_DIR)/.pkgdir/$(1) $$@\n\t\tmkdir -p $(PKG_BUILD_DIR)/.pkgdir/$(1)\n\t\t$(call Package/$(1)/install,$(PKG_BUILD_DIR)/.pkgdir/$(1))\n\t\ttouch $$@\n\n    install-bin-$(1): $(PKG_BUILD_DIR)/.pkgdir/$(1).installed\n\trm -rf $(BIN_DIR)/$(1)\n\t-rmdir $(PKG_BUILD_DIR)/.pkgdir/$(1) >/dev/null 2>/dev/null\n\tif [ -d $(PKG_BUILD_DIR)/.pkgdir/$(1) ]; then \\\n\t\t$(INSTALL_DIR) $(BIN_DIR)/$(1) && \\\n\t\t$(CP) $(PKG_BUILD_DIR)/.pkgdir/$(1)/. $(BIN_DIR)/$(1)/; \\\n\tfi\n\n    clean-$(1):\n\t  rm -rf $(BIN_DIR)/$(1)\n\n    clean: clean-$(1)\n    .PHONY: install-bin-$(1)\n  endef\nendif\n"
  },
  {
    "path": "include/package-defaults.mk",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2006-2020 OpenWrt.org\n\nPKG_DEFAULT_DEPENDS = +libc +USE_GLIBC:librt +USE_GLIBC:libpthread\n\nifneq ($(PKG_NAME),toolchain)\n  PKG_FIXUP_DEPENDS = $(if $(filter kmod-%,$(1)),$(2),$(PKG_DEFAULT_DEPENDS) $(filter-out $(PKG_DEFAULT_DEPENDS),$(2)))\nelse\n  PKG_FIXUP_DEPENDS = $(2)\nendif\n\ndefine Package/Default\n  CONFIGFILE:=\n  SECTION:=opt\n  CATEGORY:=Extra packages\n  DEPENDS:=\n  MDEPENDS:=\n  CONFLICTS:=\n  PROVIDES:=\n  EXTRA_DEPENDS:=\n  MAINTAINER:=$(PKG_MAINTAINER)\n  SOURCE:=$(patsubst $(TOPDIR)/%,%,$(CURDIR))\n  ifneq ($(PKG_VERSION),)\n    ifneq ($(PKG_RELEASE),)\n      VERSION:=$(PKG_VERSION)-$(PKG_RELEASE)\n    else\n      VERSION:=$(PKG_VERSION)\n    endif\n  else\n    VERSION:=$(PKG_RELEASE)\n  endif\n  ABI_VERSION:=\n  ifneq ($(PKG_FLAGS),)\n    PKGFLAGS:=$(PKG_FLAGS)\n  else\n    PKGFLAGS:=\n  endif\n  ifneq ($(ARCH_PACKAGES),)\n    PKGARCH:=$(ARCH_PACKAGES)\n  else\n    PKGARCH:=$(BOARD)\n  endif\n  DEFAULT:=\n  MENU:=\n  SUBMENU:=\n  SUBMENUDEP:=\n  TITLE:=\n  KCONFIG:=\n  BUILDONLY:=\n  HIDDEN:=\n  URL:=\n  VARIANT:=\n  DEFAULT_VARIANT:=\n  USERID:=\n  ALTERNATIVES:=\n  LICENSE:=$(PKG_LICENSE)\n  LICENSE_FILES:=$(PKG_LICENSE_FILES)\n  FILE_MODES:=$(PKG_FILE_MODES)\nendef\n\nBuild/Patch:=$(Build/Patch/Default)\nifneq ($(strip $(PKG_UNPACK)),)\n  define Build/Prepare/Default\n\t$(PKG_UNPACK)\n\t[ ! -d ./src/ ] || $(CP) ./src/. $(PKG_BUILD_DIR)\n\t$(Build/Patch)\n  endef\nendif\n\nEXTRA_CXXFLAGS = $(EXTRA_CFLAGS)\nifeq ($(CONFIG_BUILD_NLS),y)\n    DISABLE_NLS:=\nelse\n    DISABLE_NLS:=--disable-nls\nendif\n\nCONFIGURE_PREFIX:=/usr\nCONFIGURE_ARGS = \\\n\t\t--target=$(GNU_TARGET_NAME) \\\n\t\t--host=$(GNU_TARGET_NAME) \\\n\t\t--build=$(GNU_HOST_NAME) \\\n\t\t--program-prefix=\"\" \\\n\t\t--program-suffix=\"\" \\\n\t\t--prefix=$(CONFIGURE_PREFIX) \\\n\t\t--exec-prefix=$(CONFIGURE_PREFIX) \\\n\t\t--bindir=$(CONFIGURE_PREFIX)/bin \\\n\t\t--sbindir=$(CONFIGURE_PREFIX)/sbin \\\n\t\t--libexecdir=$(CONFIGURE_PREFIX)/lib \\\n\t\t--sysconfdir=/etc \\\n\t\t--datadir=$(CONFIGURE_PREFIX)/share \\\n\t\t--localstatedir=/var \\\n\t\t--mandir=$(CONFIGURE_PREFIX)/man \\\n\t\t--infodir=$(CONFIGURE_PREFIX)/info \\\n\t\t$(DISABLE_NLS) \\\n\t\t$(DISABLE_IPV6)\n\nCONFIGURE_VARS = \\\n\t\t$(TARGET_CONFIGURE_OPTS) \\\n\t\tCFLAGS=\"$(TARGET_CFLAGS) $(EXTRA_CFLAGS)\" \\\n\t\tCXXFLAGS=\"$(TARGET_CXXFLAGS) $(EXTRA_CXXFLAGS)\" \\\n\t\tCPPFLAGS=\"$(TARGET_CPPFLAGS) $(EXTRA_CPPFLAGS)\" \\\n\t\tLDFLAGS=\"$(TARGET_LDFLAGS) $(EXTRA_LDFLAGS)\" \\\n\nCONFIGURE_PATH = .\nCONFIGURE_CMD = ./configure\n\nreplace_script=$(FIND) $(1) -name $(2) | $(XARGS) chmod u+w; \\\n\t       $(FIND) $(1) -name $(2) | $(XARGS) -n1 cp --remove-destination \\\n\t       $(SCRIPT_DIR)/$(2);\n\ndefine Build/Configure/Default\n\t(cd $(PKG_BUILD_DIR)/$(CONFIGURE_PATH)/$(strip $(3)); \\\n\tif [ -x $(CONFIGURE_CMD) ]; then \\\n\t\t$(call replace_script,$(PKG_BUILD_DIR)/$(3),config.guess) \\\n\t\t$(call replace_script,$(PKG_BUILD_DIR)/$(3),config.sub) \\\n\t\t$(CONFIGURE_VARS) \\\n\t\t$(2) \\\n\t\t$(CONFIGURE_CMD) \\\n\t\t$(CONFIGURE_ARGS) \\\n\t\t$(1); \\\n\tfi; \\\n\t)\nendef\n\nMAKE_VARS = \\\n\tCFLAGS=\"$(TARGET_CFLAGS) $(EXTRA_CFLAGS) $(TARGET_CPPFLAGS) $(EXTRA_CPPFLAGS)\" \\\n\tCXXFLAGS=\"$(TARGET_CXXFLAGS) $(EXTRA_CXXFLAGS) $(TARGET_CPPFLAGS) $(EXTRA_CPPFLAGS)\" \\\n\tLDFLAGS=\"$(TARGET_LDFLAGS) $(EXTRA_LDFLAGS)\"\n\nMAKE_FLAGS = \\\n\t$(TARGET_CONFIGURE_OPTS) \\\n\tCROSS=\"$(TARGET_CROSS)\" \\\n\tARCH=\"$(ARCH)\"\n\nMAKE_INSTALL_FLAGS = \\\n\t$(MAKE_FLAGS) \\\n\tDESTDIR=\"$(PKG_INSTALL_DIR)\"\n\nMAKE_PATH ?= .\n\ndefine Build/Compile/Default\n\t+$(MAKE_VARS) \\\n\t$(MAKE) $(PKG_JOBS) -C $(PKG_BUILD_DIR)/$(MAKE_PATH) \\\n\t\t$(MAKE_FLAGS) \\\n\t\t$(1);\nendef\n\ndefine Build/Install/Default\n\t$(MAKE_VARS) \\\n\t$(MAKE) -C $(PKG_BUILD_DIR)/$(MAKE_PATH) \\\n\t\t$(MAKE_INSTALL_FLAGS) \\\n\t\t$(if $(1), $(1), install);\nendef\n\ndefine Build/Dist/Default\n\t$(call Build/Compile/Default, DESTDIR=\"$(PKG_BUILD_DIR)/tmp\" CC=\"$(TARGET_CC)\" dist)\nendef\n\ndefine Build/DistCheck/Default\n\t$(call Build/Compile/Default, DESTDIR=\"$(PKG_BUILD_DIR)/tmp\" CC=\"$(TARGET_CC)\" distcheck)\nendef\n"
  },
  {
    "path": "include/package-dumpinfo.mk",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2006-2020 OpenWrt.org\n\nifneq ($(DUMP),)\n\n\ndefine SOURCE_INFO\n$(if $(PKG_BUILD_DEPENDS),Build-Depends: $(PKG_BUILD_DEPENDS)\n)$(if $(HOST_BUILD_DEPENDS),Build-Depends/host: $(HOST_BUILD_DEPENDS)\n)$(if $(BUILD_TYPES),Build-Types: $(BUILD_TYPES)\n)\n\nendef\n\ndefine Dumpinfo/Package\n$(info $(SOURCE_INFO)Package: $(1)\n$(if $(MENU),Menu: $(MENU)\n)$(if $(SUBMENU),Submenu: $(SUBMENU)\n)$(if $(SUBMENUDEP),Submenu-Depends: $(SUBMENUDEP)\n)$(if $(DEFAULT),Default: $(DEFAULT)\n)$(if $(findstring $(PREREQ_CHECK),1),Prereq-Check: 1\n)Version: $(VERSION)\nDepends: $(call PKG_FIXUP_DEPENDS,$(1),$(DEPENDS))\nConflicts: $(CONFLICTS)\nMenu-Depends: $(MDEPENDS)\nProvides: $(PROVIDES)\n$(if $(VARIANT),Build-Variant: $(VARIANT)\n$(if $(DEFAULT_VARIANT),Default-Variant: $(VARIANT)\n))Section: $(SECTION)\nCategory: $(CATEGORY)\n$(if $(filter nonshared,$(PKGFLAGS)),,Repository: $(if $(FEED),$(FEED),base)\n)Title: $(TITLE)\nMaintainer: $(MAINTAINER)\n$(if $(USERID),Require-User: $(USERID)\n)Source: $(PKG_SOURCE)\n$(if $(LICENSE),License: $(LICENSE)\n)$(if $(LICENSE_FILES),LicenseFiles: $(LICENSE_FILES)\n)Type: $(if $(Package/$(1)/targets),$(Package/$(1)/targets),$(if $(PKG_TARGETS),$(PKG_TARGETS),ipkg))\n$(if $(KCONFIG),Kernel-Config: $(KCONFIG)\n)$(if $(BUILDONLY),Build-Only: $(BUILDONLY)\n)$(if $(HIDDEN),Hidden: $(HIDDEN)\n)Description: $(if $(Package/$(1)/description),$(Package/$(1)/description),$(TITLE))\n$(if $(URL),$(URL)\n)$(MAINTAINER)\n@@\n$(if $(Package/$(1)/config),Config:\n$(Package/$(1)/config)\n@@\n))\nSOURCE_INFO :=\nendef\n\ndumpinfo: FORCE\n\t$(if $(SOURCE_INFO),$(info $(SOURCE_INFO)))\n\nendif\n"
  },
  {
    "path": "include/package-ipkg.mk",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2006-2020 OpenWrt.org\n\nifndef DUMP\n  include $(INCLUDE_DIR)/feeds.mk\nendif\n\nIPKG_REMOVE:= \\\n  $(SCRIPT_DIR)/ipkg-remove\n\nIPKG_STATE_DIR:=$(TARGET_DIR)/usr/lib/opkg\n\n# Generates a make statement to return a wildcard for candidate ipkg files\n# 1: package name\ndefine gen_ipkg_wildcard\n  $(1)$$(if $$(filter -%,$$(ABIV_$(1))),,[^a-z-])*\nendef\n\n# 1: package name\n# 2: candidate ipk files\ndefine remove_ipkg_files\n  $(if $(strip $(2)),$(IPKG_REMOVE) $(1) $(2))\nendef\n\n# 1: package name\n# 2: variable name\n# 3: variable suffix\n# 4: file is a script\ndefine BuildIPKGVariable\nifdef Package/$(1)/$(2)\n  $$(IPKG_$(1)) : VAR_$(2)$(3)=$$(Package/$(1)/$(2))\n  $(call shexport,Package/$(1)/$(2))\n  $(1)_COMMANDS += echo \"$$$$$$$$$(call shvar,Package/$(1)/$(2))\" > $(2)$(3); $(if $(4),chmod 0755 $(2)$(3);)\nendif\nendef\n\nPARENL :=(\nPARENR :=)\n\ndep_split=$(subst :,$(space),$(1))\ndep_rem=$(subst !,,$(subst $(strip $(PARENL)),,$(subst $(strip $(PARENR)),,$(word 1,$(call dep_split,$(1))))))\ndep_and=dep_and_res:=$$(and $(subst $(space),$(comma),$(foreach cond,$(subst &&, ,$(1)),$$(CONFIG_$(cond)))))\ndep_confvar=$(strip $(foreach cond,$(subst ||, ,$(call dep_rem,$(1))),$(eval $(call dep_and,$(cond)))$(dep_and_res)))\ndep_pos=$(if $(call dep_confvar,$(1)),$(call dep_val,$(1)))\ndep_neg=$(if $(call dep_confvar,$(1)),,$(call dep_val,$(1)))\ndep_if=$(if $(findstring !,$(1)),$(call dep_neg,$(1)),$(call dep_pos,$(1)))\ndep_val=$(word 2,$(call dep_split,$(1)))\nstrip_deps=$(strip $(subst +,,$(filter-out @%,$(1))))\nfilter_deps=$(foreach dep,$(call strip_deps,$(1)),$(if $(findstring :,$(dep)),$(call dep_if,$(dep)),$(dep)))\n\ndefine AddDependency\n  $$(if $(1),$$(if $(2),$$(foreach pkg,$(1),$$(IPKG_$$(pkg))): $$(foreach pkg,$(2),$$(IPKG_$$(pkg)))))\nendef\n\ndefine FixupReverseDependencies\n  DEPS := $$(filter %:$(1),$$(IDEPEND))\n  DEPS := $$(patsubst %:$(1),%,$$(DEPS))\n  DEPS := $$(filter $$(DEPS),$$(IPKGS))\n  $(call AddDependency,$$(DEPS),$(1))\nendef\n\ndefine FixupDependencies\n  DEPS := $$(filter $(1):%,$$(IDEPEND))\n  DEPS := $$(patsubst $(1):%,%,$$(DEPS))\n  DEPS := $$(filter $$(DEPS),$$(IPKGS))\n  $(call AddDependency,$(1),$$(DEPS))\nendef\n\nifneq ($(PKG_NAME),toolchain)\n  define CheckDependencies\n\t@( \\\n\t\trm -f $(PKG_INFO_DIR)/$(1).missing; \\\n\t\t( \\\n\t\t\texport \\\n\t\t\t\tREADELF=$(TARGET_CROSS)readelf \\\n\t\t\t\tOBJCOPY=$(TARGET_CROSS)objcopy \\\n\t\t\t\tXARGS=\"$(XARGS)\"; \\\n\t\t\t$(SCRIPT_DIR)/gen-dependencies.sh \"$$(IDIR_$(1))\"; \\\n\t\t) | while read FILE; do \\\n\t\t\tgrep -qxF \"$$$$FILE\" $(PKG_INFO_DIR)/$(1).provides || \\\n\t\t\t\techo \"$$$$FILE\" >> $(PKG_INFO_DIR)/$(1).missing; \\\n\t\tdone; \\\n\t\tif [ -f \"$(PKG_INFO_DIR)/$(1).missing\" ]; then \\\n\t\t\techo \"Package $(1) is missing dependencies for the following libraries:\" >&2; \\\n\t\t\tcat \"$(PKG_INFO_DIR)/$(1).missing\" >&2; \\\n\t\t\tfalse; \\\n\t\tfi; \\\n\t)\n  endef\nendif\n\n_addsep=$(word 1,$(1))$(foreach w,$(wordlist 2,$(words $(1)),$(1)),$(strip $(2) $(w)))\n_cleansep=$(subst $(space)$(2)$(space),$(2)$(space),$(1))\nmergelist=$(call _cleansep,$(call _addsep,$(1),$(comma)),$(comma))\naddfield=$(if $(strip $(2)),$(1): $(2))\n_define=define\n_endef=endef\n\nifeq ($(DUMP),)\n  define BuildTarget/ipkg\n    ABIV_$(1):=$(call FormatABISuffix,$(1),$(ABI_VERSION))\n    PDIR_$(1):=$(call FeedPackageDir,$(1))\n    IPKG_$(1):=$$(PDIR_$(1))/$(1)$$(ABIV_$(1))_$(VERSION)_$(PKGARCH).ipk\n    IDIR_$(1):=$(PKG_BUILD_DIR)/ipkg-$(PKGARCH)/$(1)\n    KEEP_$(1):=$(strip $(call Package/$(1)/conffiles))\n\n    TARGET_VARIANT:=$$(if $(ALL_VARIANTS),$$(if $$(VARIANT),$$(filter-out *,$$(VARIANT)),$(firstword $(ALL_VARIANTS))))\n    ifeq ($(BUILD_VARIANT),$$(if $$(TARGET_VARIANT),$$(TARGET_VARIANT),$(BUILD_VARIANT)))\n    do_install=\n    ifdef Package/$(1)/install\n      do_install=yes\n    endif\n    ifdef Package/$(1)/install-overlay\n      do_install=yes\n    endif\n    ifdef do_install\n      ifneq ($(CONFIG_PACKAGE_$(1))$(DEVELOPER),)\n        IPKGS += $(1)\n        $(_pkg_target)compile: $$(IPKG_$(1)) $(PKG_INFO_DIR)/$(1).provides $(PKG_BUILD_DIR)/.pkgdir/$(1).installed\n        prepare-package-install: $$(IPKG_$(1))\n        compile: $(STAGING_DIR_ROOT)/stamp/.$(1)_installed\n      else\n        $(if $(CONFIG_PACKAGE_$(1)),$$(info WARNING: skipping $(1) -- package not selected))\n      endif\n\n      .PHONY: $(PKG_INSTALL_STAMP).$(1)\n      ifeq ($(CONFIG_PACKAGE_$(1)),y)\n        compile: $(PKG_INSTALL_STAMP).$(1)\n      endif\n      $(PKG_INSTALL_STAMP).$(1): prepare-package-install\n\t\techo \"$(1)\" >> $(PKG_INSTALL_STAMP)\n    else\n      $(if $(CONFIG_PACKAGE_$(1)),$$(warning WARNING: skipping $(1) -- package has no install section))\n    endif\n    endif\n\n    DEPENDS:=$(call PKG_FIXUP_DEPENDS,$(1),$(DEPENDS))\n    IDEPEND_$(1):=$$(call filter_deps,$$(DEPENDS))\n    IDEPEND += $$(patsubst %,$(1):%,$$(IDEPEND_$(1)))\n    $(FixupDependencies)\n    $(FixupReverseDependencies)\n\n    $(eval $(call BuildIPKGVariable,$(1),conffiles))\n    $(eval $(call BuildIPKGVariable,$(1),preinst,,1))\n    $(eval $(call BuildIPKGVariable,$(1),postinst,-pkg,1))\n    $(eval $(call BuildIPKGVariable,$(1),prerm,-pkg,1))\n    $(eval $(call BuildIPKGVariable,$(1),postrm,,1))\n\n    $(PKG_BUILD_DIR)/.pkgdir/$(1).installed : export PATH=$$(TARGET_PATH_PKG)\n    $(PKG_BUILD_DIR)/.pkgdir/$(1).installed: $(STAMP_BUILT)\n\trm -rf $$@ $(PKG_BUILD_DIR)/.pkgdir/$(1)\n\tmkdir -p $(PKG_BUILD_DIR)/.pkgdir/$(1)\n\t$(call Package/$(1)/install,$(PKG_BUILD_DIR)/.pkgdir/$(1))\n\t$(call Package/$(1)/install_lib,$(PKG_BUILD_DIR)/.pkgdir/$(1))\n\ttouch $$@\n\n    $(STAGING_DIR_ROOT)/stamp/.$(1)_installed: $(PKG_BUILD_DIR)/.pkgdir/$(1).installed\n\tmkdir -p $(STAGING_DIR_ROOT)/stamp\n\t$(if $(ABI_VERSION),echo '$(ABI_VERSION)' | cmp -s - $(PKG_INFO_DIR)/$(1).version || { \\\n\t\techo '$(ABI_VERSION)' > $(PKG_INFO_DIR)/$(1).version; \\\n\t\t$(foreach pkg,$(filter-out $(1),$(PROVIDES)), \\\n\t\t\tcp $(PKG_INFO_DIR)/$(1).version $(PKG_INFO_DIR)/$(pkg).version; \\\n\t\t) \\\n\t} )\n\t$(call locked,$(CP) $(PKG_BUILD_DIR)/.pkgdir/$(1)/. $(STAGING_DIR_ROOT)/,root-copy)\n\ttouch $$@\n\n    Package/$(1)/DEPENDS := $$(call mergelist,$$(foreach dep,$$(filter-out @%,$$(IDEPEND_$(1))),$$(dep)$$(call GetABISuffix,$$(dep))))\n    ifneq ($$(EXTRA_DEPENDS),)\n      Package/$(1)/DEPENDS := $$(EXTRA_DEPENDS)$$(if $$(Package/$(1)/DEPENDS),$$(comma) $$(Package/$(1)/DEPENDS))\n    endif\n\n$(_define) Package/$(1)/CONTROL\nPackage: $(1)$$(ABIV_$(1))\nVersion: $(VERSION)\n$$(call addfield,Depends,$$(Package/$(1)/DEPENDS)\n)$$(call addfield,Conflicts,$$(call mergelist,$(CONFLICTS))\n)$$(call addfield,Provides,$$(call mergelist,$$(filter-out $(1)$$(ABIV_$(1)),$(PROVIDES)$$(if $$(ABIV_$(1)), $(1) $(foreach provide,$(PROVIDES),$(provide)$$(ABIV_$(1))))))\n)$$(call addfield,Alternatives,$$(call mergelist,$(ALTERNATIVES))\n)$$(call addfield,Source,$(SOURCE)\n)$$(call addfield,SourceName,$(1)\n)$$(call addfield,License,$(LICENSE)\n)$$(call addfield,LicenseFiles,$(LICENSE_FILES)\n)$$(call addfield,Section,$(SECTION)\n)$$(call addfield,Require-User,$(USERID)\n)$$(call addfield,SourceDateEpoch,$(PKG_SOURCE_DATE_EPOCH)\n)$$(if $$(ABIV_$(1)),ABIVersion: $$(ABIV_$(1))\n)$(if $(PKG_CPE_ID),CPE-ID: $(PKG_CPE_ID)\n)$(if $(filter hold,$(PKG_FLAGS)),Status: unknown hold not-installed\n)$(if $(filter essential,$(PKG_FLAGS)),Essential: yes\n)$(if $(MAINTAINER),Maintainer: $(MAINTAINER)\n)Architecture: $(PKGARCH)\nInstalled-Size: 0\n$(_endef)\n\n    $$(IPKG_$(1)) : export CONTROL=$$(Package/$(1)/CONTROL)\n    $$(IPKG_$(1)) : export DESCRIPTION=$$(Package/$(1)/description)\n    $$(IPKG_$(1)) : export PATH=$$(TARGET_PATH_PKG)\n    $$(IPKG_$(1)) : export PKG_SOURCE_DATE_EPOCH:=$(PKG_SOURCE_DATE_EPOCH)\n    $(PKG_INFO_DIR)/$(1).provides $$(IPKG_$(1)): $(STAMP_BUILT) $(INCLUDE_DIR)/package-ipkg.mk\n\t@rm -rf $$(IDIR_$(1)); \\\n\t\t$$(call remove_ipkg_files,$(1),$$(call opkg_package_files,$(call gen_ipkg_wildcard,$(1))))\n\tmkdir -p $(PACKAGE_DIR) $$(IDIR_$(1))/CONTROL $(PKG_INFO_DIR)\n\t$(call Package/$(1)/install,$$(IDIR_$(1)))\n\t$(if $(Package/$(1)/install-overlay),mkdir -p $(PACKAGE_DIR) $$(IDIR_$(1))/rootfs-overlay)\n\t$(call Package/$(1)/install-overlay,$$(IDIR_$(1))/rootfs-overlay)\n\t-find $$(IDIR_$(1)) -name 'CVS' -o -name '.svn' -o -name '.#*' -o -name '*~'| $(XARGS) rm -rf\n\t@( \\\n\t\tfind $$(IDIR_$(1)) -name lib\\*.so\\* -or -name \\*.ko | awk -F/ '{ print $$$$NF }'; \\\n\t\tfor file in $$(patsubst %,$(PKG_INFO_DIR)/%.provides,$$(IDEPEND_$(1))); do \\\n\t\t\tif [ -f \"$$$$file\" ]; then \\\n\t\t\t\tcat $$$$file; \\\n\t\t\tfi; \\\n\t\tdone; $(Package/$(1)/extra_provides) \\\n\t) | sort -u > $(PKG_INFO_DIR)/$(1).provides\n\t$(if $(PROVIDES),@for pkg in $(filter-out $(1),$(PROVIDES)); do cp $(PKG_INFO_DIR)/$(1).provides $(PKG_INFO_DIR)/$$$$pkg.provides; done)\n\t$(CheckDependencies)\n\n\t$(RSTRIP) $$(IDIR_$(1))\n\n    ifneq ($$(CONFIG_IPK_FILES_CHECKSUMS),)\n\t(cd $$(IDIR_$(1)); \\\n\t\t( \\\n\t\t\tfind . -type f \\! -path ./CONTROL/\\* -exec $(MKHASH) sha256 -n \\{\\} \\; 2> /dev/null | \\\n\t\t\tsed 's|\\([[:blank:]]\\)\\./| \\1/|' > $$(IDIR_$(1))/CONTROL/files-sha256sum \\\n\t\t) || true \\\n\t)\n    endif\n\t(cd $$(IDIR_$(1))/CONTROL; \\\n\t\t( \\\n\t\t\techo \"$$$$CONTROL\"; \\\n\t\t\tprintf \"Description: \"; echo \"$$$$DESCRIPTION\" | sed -e 's,^[[:space:]]*, ,g'; \\\n\t\t) > control; \\\n\t\tchmod 644 control; \\\n\t\t( \\\n\t\t\techo \"#!/bin/sh\"; \\\n\t\t\techo \"[ \\\"\\$$$${IPKG_NO_SCRIPT}\\\" = \\\"1\\\" ] && exit 0\"; \\\n\t\t\techo \"[ -s \"\\$$$${IPKG_INSTROOT}/lib/functions.sh\" ] || exit 0\"; \\\n\t\t\techo \". \\$$$${IPKG_INSTROOT}/lib/functions.sh\"; \\\n\t\t\techo \"default_postinst \\$$$$0 \\$$$$@\"; \\\n\t\t) > postinst; \\\n\t\t( \\\n\t\t\techo \"#!/bin/sh\"; \\\n\t\t\techo \"[ -s \"\\$$$${IPKG_INSTROOT}/lib/functions.sh\" ] || exit 0\"; \\\n\t\t\techo \". \\$$$${IPKG_INSTROOT}/lib/functions.sh\"; \\\n\t\t\techo \"default_prerm \\$$$$0 \\$$$$@\"; \\\n\t\t) > prerm; \\\n\t\tchmod 0755 postinst prerm; \\\n\t\t$($(1)_COMMANDS) \\\n\t)\n\n    ifneq ($$(KEEP_$(1)),)\n\t\t@( \\\n\t\t\tkeepfiles=\"\"; \\\n\t\t\tfor x in $$(KEEP_$(1)); do \\\n\t\t\t\t[ -f \"$$(IDIR_$(1))/$$$$x\" ] || keepfiles=\"$$$${keepfiles:+$$$$keepfiles }$$$$x\"; \\\n\t\t\tdone; \\\n\t\t\t[ -z \"$$$$keepfiles\" ] || { \\\n\t\t\t\tmkdir -p $$(IDIR_$(1))/lib/upgrade/keep.d; \\\n\t\t\t\tfor x in $$$$keepfiles; do echo $$$$x >> $$(IDIR_$(1))/lib/upgrade/keep.d/$(1); done; \\\n\t\t\t}; \\\n\t\t)\n    endif\n\n\t$(INSTALL_DIR) $$(PDIR_$(1))\n\t$(FAKEROOT) $(STAGING_DIR_HOST)/bin/bash $(SCRIPT_DIR)/ipkg-build -m \"$(FILE_MODES)\" $$(IDIR_$(1)) $$(PDIR_$(1))\n\t@[ -f $$(IPKG_$(1)) ]\n\n    $(1)-clean:\n\t$$(call remove_ipkg_files,$(1),$$(call opkg_package_files,$(call gen_ipkg_wildcard,$(1))))\n\n    clean: $(1)-clean\n\n  endef\nendif\n"
  },
  {
    "path": "include/package-seccomp.mk",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2015-2020 OpenWrt.org\n\nPKG_CONFIG_DEPENDS+= CONFIG_KERNEL_SECCOMP\n\nifeq ($(CONFIG_KERNEL_SECCOMP),y)\n  define InstallSeccomp\n\t$(INSTALL_DIR) $(1)/etc/seccomp\n\t$(INSTALL_DATA) $(2) $(1)/etc/seccomp/\n  endef\nendif\n"
  },
  {
    "path": "include/package.mk",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2006-2020 OpenWrt.org\n\n__package_mk:=1\n\nall: $(if $(DUMP),dumpinfo,$(if $(CHECK),check,compile))\n\ninclude $(INCLUDE_DIR)/download.mk\n\nPKG_BUILD_DIR ?= $(BUILD_DIR)/$(if $(BUILD_VARIANT),$(PKG_NAME)-$(BUILD_VARIANT)/)$(PKG_NAME)$(if $(PKG_VERSION),-$(PKG_VERSION))\nPKG_INSTALL_DIR ?= $(PKG_BUILD_DIR)/ipkg-install\nPKG_BUILD_PARALLEL ?=\nPKG_USE_MIPS16 ?= 1\nPKG_IREMAP ?= 1\nPKG_SKIP_DOWNLOAD=$(USE_SOURCE_DIR)$(USE_GIT_TREE)$(USE_GIT_SRC_CHECKOUT)\n\nMAKE_J:=$(if $(MAKE_JOBSERVER),$(MAKE_JOBSERVER) $(if $(filter 3.% 4.0 4.1,$(MAKE_VERSION)),-j))\n\nPKG_SOURCE_DATE_EPOCH:=$(if $(DUMP),,$(shell $(TOPDIR)/scripts/get_source_date_epoch.sh $(CURDIR)))\n\nifeq ($(strip $(PKG_BUILD_PARALLEL)),0)\nPKG_JOBS?=-j1\nelse\nPKG_JOBS?=$(if $(PKG_BUILD_PARALLEL),$(MAKE_J),-j1)\nendif\nifdef CONFIG_USE_MIPS16\n  ifeq ($(strip $(PKG_USE_MIPS16)),1)\n    TARGET_ASFLAGS_DEFAULT = $(filter-out -mips16 -minterlink-mips16,$(TARGET_CFLAGS))\n    TARGET_CFLAGS += -mips16 -minterlink-mips16\n  endif\nendif\nifeq ($(strip $(PKG_IREMAP)),1)\n  IREMAP_CFLAGS = $(call iremap,$(PKG_BUILD_DIR),$(notdir $(PKG_BUILD_DIR)))\n  TARGET_CFLAGS += $(IREMAP_CFLAGS)\nendif\n\ninclude $(INCLUDE_DIR)/hardening.mk\ninclude $(INCLUDE_DIR)/prereq.mk\ninclude $(INCLUDE_DIR)/unpack.mk\ninclude $(INCLUDE_DIR)/depends.mk\n\nifneq ($(wildcard $(TOPDIR)/git-src/$(PKG_NAME)/.git),)\n  USE_GIT_SRC_CHECKOUT:=1\n  QUILT:=1\nendif\nifneq ($(if $(CONFIG_SRC_TREE_OVERRIDE),$(wildcard ./git-src)),)\n  USE_GIT_TREE:=1\n  QUILT:=1\nendif\nifdef USE_SOURCE_DIR\n  QUILT:=1\nendif\nifneq ($(wildcard $(PKG_BUILD_DIR)/.source_dir),)\n  QUILT:=1\nendif\n\ninclude $(INCLUDE_DIR)/quilt.mk\n\nfind_library_dependencies = \\\n\t$(wildcard $(patsubst %,$(STAGING_DIR)/pkginfo/%.version, \\\n\t\t$(filter-out $(BUILD_PACKAGES), $(sort $(foreach dep4, \\\n\t\t\t$(sort $(foreach dep3, \\\n\t\t\t\t$(sort $(foreach dep2, \\\n\t\t\t\t\t$(sort $(foreach dep1, \\\n\t\t\t\t\t\t$(sort $(foreach dep0, \\\n\t\t\t\t\t\t\t$(Package/$(1)/depends), \\\n\t\t\t\t\t\t\t$(Package/$(dep0)/depends) $(dep0) \\\n\t\t\t\t\t\t)), \\\n\t\t\t\t\t\t$(Package/$(dep1)/depends) $(dep1) \\\n\t\t\t\t\t)), \\\n\t\t\t\t\t$(Package/$(dep2)/depends) $(dep2) \\\n\t\t\t\t)), \\\n\t\t\t\t$(Package/$(dep3)/depends) $(dep3) \\\n\t\t\t)), \\\n\t\t\t$(Package/$(dep4)/depends) $(dep4) \\\n\t\t))) \\\n\t))\n\n\nPKG_DIR_NAME:=$(lastword $(subst /,$(space),$(CURDIR)))\nSTAMP_NO_AUTOREBUILD=$(wildcard $(PKG_BUILD_DIR)/.no_autorebuild)\nPREV_STAMP_PREPARED:=$(if $(STAMP_NO_AUTOREBUILD),$(wildcard $(PKG_BUILD_DIR)/.prepared*))\nifneq ($(PREV_STAMP_PREPARED),)\n  STAMP_PREPARED:=$(PREV_STAMP_PREPARED)\n  CONFIG_AUTOREBUILD:=\nelse\n  STAMP_PREPARED=$(PKG_BUILD_DIR)/.prepared$(if $(QUILT)$(DUMP),,_$(shell $(call find_md5,${CURDIR} $(PKG_FILE_DEPENDS),))_$(call confvar,CONFIG_AUTOREMOVE $(PKG_PREPARED_DEPENDS)))\nendif\nSTAMP_CONFIGURED=$(PKG_BUILD_DIR)/.configured$(if $(DUMP),,_$(call confvar,$(PKG_CONFIG_DEPENDS)))\nSTAMP_CONFIGURED_WILDCARD=$(PKG_BUILD_DIR)/.configured_*\nSTAMP_BUILT:=$(PKG_BUILD_DIR)/.built\nSTAMP_INSTALLED:=$(STAGING_DIR)/stamp/.$(PKG_DIR_NAME)$(if $(BUILD_VARIANT),.$(BUILD_VARIANT),)_installed\n\nSTAGING_FILES_LIST:=$(PKG_DIR_NAME)$(if $(BUILD_VARIANT),.$(BUILD_VARIANT),).list\n\ndefine CleanStaging\n\trm -f $(STAMP_INSTALLED)\n\t@-(\\\n\t\tif [ -f $(STAGING_DIR)/packages/$(STAGING_FILES_LIST) ]; then \\\n\t\t\t$(SCRIPT_DIR)/clean-package.sh \\\n\t\t\t\t\"$(STAGING_DIR)/packages/$(STAGING_FILES_LIST)\" \\\n\t\t\t\t\"$(STAGING_DIR)\"; \\\n\t\tfi; \\\n\t)\nendef\n\n\nPKG_INSTALL_STAMP:=$(PKG_INFO_DIR)/$(PKG_DIR_NAME).$(if $(BUILD_VARIANT),$(BUILD_VARIANT),default).install\n\ninclude $(INCLUDE_DIR)/package-defaults.mk\ninclude $(INCLUDE_DIR)/package-dumpinfo.mk\ninclude $(INCLUDE_DIR)/package-ipkg.mk\ninclude $(INCLUDE_DIR)/package-bin.mk\ninclude $(INCLUDE_DIR)/autotools.mk\n\n_pkg_target:=$(if $(QUILT),,.)\n\noverride MAKEFLAGS=\nCONFIG_SITE:=$(INCLUDE_DIR)/site/$(ARCH)\nCUR_MAKEFILE:=$(filter-out Makefile,$(firstword $(MAKEFILE_LIST)))\nSUBMAKE:=$(NO_TRACE_MAKE) $(if $(CUR_MAKEFILE),-f $(CUR_MAKEFILE))\nPKG_CONFIG_PATH=$(STAGING_DIR)/usr/lib/pkgconfig:$(STAGING_DIR)/usr/share/pkgconfig\nunexport QUIET CONFIG_SITE\n\nifeq ($(DUMP)$(filter prereq clean refresh update,$(MAKECMDGOALS)),)\n  ifneq ($(if $(QUILT),,$(CONFIG_AUTOREBUILD)),)\n    define Build/Autoclean\n      $(PKG_BUILD_DIR)/.dep_files: $(STAMP_PREPARED)\n      $(call rdep,${CURDIR} $(PKG_FILE_DEPENDS),$(STAMP_PREPARED),$(PKG_BUILD_DIR)/.dep_files,-x \"*/.dep_*\")\n      $(if $(filter prepare,$(MAKECMDGOALS)),,$(call rdep,$(PKG_BUILD_DIR),$(STAMP_BUILT),,-x \"*/.dep_*\" -x \"*/ipkg*\"))\n    endef\n  endif\nendif\n\nifdef USE_GIT_SRC_CHECKOUT\n  define Build/Prepare/Default\n\tmkdir -p $(PKG_BUILD_DIR)\n\tln -s $(TOPDIR)/git-src/$(PKG_NAME)/.git $(PKG_BUILD_DIR)/.git\n\t( cd $(PKG_BUILD_DIR); \\\n\t\tgit checkout .; \\\n\t\tgit submodule update --recursive; \\\n\t\tgit submodule foreach git config --unset core.worktree; \\\n\t\tgit submodule foreach git checkout .; \\\n\t)\n  endef\nendif\nifdef USE_GIT_TREE\n  define Build/Prepare/Default\n\tmkdir -p $(PKG_BUILD_DIR)\n\tln -s $(CURDIR)/git-src $(PKG_BUILD_DIR)/.git\n\t( cd $(PKG_BUILD_DIR); \\\n\t\tgit checkout .; \\\n\t\tgit submodule update --recursive; \\\n\t\tgit submodule foreach git config --unset core.worktree; \\\n\t\tgit submodule foreach git checkout .; \\\n\t)\n  endef\nendif\nifdef USE_SOURCE_DIR\n  define Build/Prepare/Default\n\trm -rf $(PKG_BUILD_DIR)\n\t$(if $(wildcard $(USE_SOURCE_DIR)/*),,@echo \"Error: USE_SOURCE_DIR=$(USE_SOURCE_DIR) path not found\"; false)\n\tln -snf $(USE_SOURCE_DIR) $(PKG_BUILD_DIR)\n\ttouch $(PKG_BUILD_DIR)/.source_dir\n  endef\nendif\n\ndefine Build/Exports/Default\n  $(1) : export ACLOCAL_INCLUDE=$$(foreach p,$$(wildcard $$(STAGING_DIR)/usr/share/aclocal $$(STAGING_DIR)/usr/share/aclocal-* $$(STAGING_DIR_HOSTPKG)/share/aclocal $$(STAGING_DIR_HOSTPKG)/share/aclocal-* $$(STAGING_DIR)/host/share/aclocal $$(STAGING_DIR)/host/share/aclocal-*),-I $$(p))\n  $(1) : export STAGING_PREFIX=$$(STAGING_DIR)/usr\n  $(1) : export PATH=$$(TARGET_PATH_PKG)\n  $(1) : export CONFIG_SITE:=$$(CONFIG_SITE)\n  $(1) : export PKG_CONFIG_PATH:=$$(PKG_CONFIG_PATH)\n  $(1) : export PKG_CONFIG_LIBDIR:=$$(PKG_CONFIG_PATH)\nendef\nBuild/Exports=$(Build/Exports/Default)\n\ndefine Build/CoreTargets\n  STAMP_PREPARED:=$$(STAMP_PREPARED)\n  STAMP_CONFIGURED:=$$(STAMP_CONFIGURED)\n\n  $(if $(QUILT),$(Build/Quilt))\n  $(call Build/Autoclean)\n  $(call DefaultTargets)\n\n  $(call check_download_integrity)\n\n  download:\n\t$(foreach hook,$(Hooks/Download),\n\t\t$(call $(hook))$(sep)\n\t)\n\n  $(STAMP_PREPARED) : export PATH=$$(TARGET_PATH_PKG)\n  $(STAMP_PREPARED): $(STAMP_PREPARED_DEPENDS)\n\t@-rm -rf $(PKG_BUILD_DIR)\n\t@mkdir -p $(PKG_BUILD_DIR)\n\ttouch $$@_check\n\t$(foreach hook,$(Hooks/Prepare/Pre),$(call $(hook))$(sep))\n\t$(Build/Prepare)\n\t$(foreach hook,$(Hooks/Prepare/Post),$(call $(hook))$(sep))\n\ttouch $$@\n\n  $(call Build/Exports,$(STAMP_CONFIGURED))\n  $(STAMP_CONFIGURED): $(STAMP_PREPARED) $(STAMP_CONFIGURED_DEPENDS)\n\trm -f $(STAMP_CONFIGURED_WILDCARD)\n\t$(CleanStaging)\n\t$(foreach hook,$(Hooks/Configure/Pre),$(call $(hook))$(sep))\n\t$(Build/Configure)\n\t$(foreach hook,$(Hooks/Configure/Post),$(call $(hook))$(sep))\n\ttouch $$@\n\n  $(call Build/Exports,$(STAMP_BUILT))\n  $(STAMP_BUILT): $(STAMP_CONFIGURED) $(STAMP_BUILT_DEPENDS)\n\trm -f $$@\n\ttouch $$@_check\n\t$(foreach hook,$(Hooks/Compile/Pre),$(call $(hook))$(sep))\n\t$(Build/Compile)\n\t$(foreach hook,$(Hooks/Compile/Post),$(call $(hook))$(sep))\n\t$(Build/Install)\n\t$(foreach hook,$(Hooks/Install/Post),$(call $(hook))$(sep))\n\ttouch $$@\n\n  $(STAMP_INSTALLED) : export PATH=$$(TARGET_PATH_PKG)\n  $(STAMP_INSTALLED): $(STAMP_BUILT)\n\trm -rf $(TMP_DIR)/stage-$(PKG_DIR_NAME)\n\tmkdir -p $(TMP_DIR)/stage-$(PKG_DIR_NAME)/host $(STAGING_DIR)/packages\n\t$(foreach hook,$(Hooks/InstallDev/Pre),\\\n\t\t$(call $(hook),$(TMP_DIR)/stage-$(PKG_DIR_NAME),$(TMP_DIR)/stage-$(PKG_DIR_NAME)/host)$(sep)\\\n\t)\n\t$(call Build/InstallDev,$(TMP_DIR)/stage-$(PKG_DIR_NAME),$(TMP_DIR)/stage-$(PKG_DIR_NAME)/host)\n\t$(foreach hook,$(Hooks/InstallDev/Post),\\\n\t\t$(call $(hook),$(TMP_DIR)/stage-$(PKG_DIR_NAME),$(TMP_DIR)/stage-$(PKG_DIR_NAME)/host)$(sep)\\\n\t)\n\tif [ -f $(STAGING_DIR)/packages/$(STAGING_FILES_LIST) ]; then \\\n\t\t$(SCRIPT_DIR)/clean-package.sh \\\n\t\t\t\"$(STAGING_DIR)/packages/$(STAGING_FILES_LIST)\" \\\n\t\t\t\"$(STAGING_DIR)\"; \\\n\tfi\n\tif [ -d $(TMP_DIR)/stage-$(PKG_DIR_NAME) ]; then \\\n\t\t(cd $(TMP_DIR)/stage-$(PKG_DIR_NAME); find ./ > $(TMP_DIR)/stage-$(PKG_DIR_NAME).files); \\\n\t\t$(call locked, \\\n\t\t\tmv $(TMP_DIR)/stage-$(PKG_DIR_NAME).files $(STAGING_DIR)/packages/$(STAGING_FILES_LIST) && \\\n\t\t\t$(CP) $(TMP_DIR)/stage-$(PKG_DIR_NAME)/* $(STAGING_DIR)/; \\\n\t\t,staging-dir); \\\n\tfi\n\trm -rf $(TMP_DIR)/stage-$(PKG_DIR_NAME)\n\ttouch $$@\n\n  ifdef Build/InstallDev\n    $(_pkg_target)compile: $(STAMP_INSTALLED)\n  endif\n\n  $(_pkg_target)prepare: $(STAMP_PREPARED)\n  $(_pkg_target)configure: $(STAMP_CONFIGURED)\n  $(_pkg_target)dist: $(STAMP_CONFIGURED)\n  $(_pkg_target)distcheck: $(STAMP_CONFIGURED)\n\n  ifneq ($(CONFIG_AUTOREMOVE),)\n    compile:\n\t\t-touch -r $(PKG_BUILD_DIR)/.built $(PKG_BUILD_DIR)/.autoremove 2>/dev/null >/dev/null\n\t\t$(FIND) $(PKG_BUILD_DIR) -mindepth 1 -maxdepth 1 -not '(' -type f -and -name '.*' -and -size 0 ')' -and -not -name '.pkgdir' | \\\n\t\t\t$(XARGS) rm -rf\n  endif\nendef\n\ndefine Build/DefaultTargets\n  $(if $(PKG_SKIP_DOWNLOAD),,$(if $(strip $(PKG_SOURCE_URL)),$(call Download,default)))\n  $(if $(DUMP),,$(Build/CoreTargets))\n\n  define Build/DefaultTargets\n  endef\nendef\n\ndefine BuildPackage\n  $(eval $(Package/Default))\n  $(eval $(Package/$(1)))\n\nifdef DESCRIPTION\n$$(error DESCRIPTION:= is obsolete, use Package/PKG_NAME/description)\nendif\n\nifndef Package/$(1)/description\ndefine Package/$(1)/description\n\t$(TITLE)\nendef\nendif\n\n  BUILD_PACKAGES += $(1)\n  $(STAMP_PREPARED): $$(if $(QUILT)$(DUMP),,$(call find_library_dependencies,$(1)))\n\n  $(foreach FIELD, TITLE CATEGORY SECTION VERSION,\n    ifeq ($($(FIELD)),)\n      $$(error Package/$(1) is missing the $(FIELD) field)\n    endif\n  )\n\n  $(if $(DUMP), \\\n    $(if $(CHECK),,$(Dumpinfo/Package)), \\\n    $(foreach target, \\\n      $(if $(Package/$(1)/targets),$(Package/$(1)/targets), \\\n        $(if $(PKG_TARGETS),$(PKG_TARGETS), ipkg) \\\n      ), $(BuildTarget/$(target)) \\\n    ) \\\n  )\n  $(if $(PKG_HOST_ONLY),,$(call Build/DefaultTargets,$(1)))\nendef\n\ndefine pkg_install_files\n\t$(foreach install_file,$(1),$(INSTALL_DIR) $(3)/`dirname $(install_file)`; $(INSTALL_DATA) $(2)/$(install_file) $(3)/`dirname $(install_file)`;)\nendef\n\ndefine pkg_install_bin\n\t$(foreach install_apps,$(1),$(INSTALL_DIR) $(3)/`dirname $(install_apps)`; $(INSTALL_BIN) $(2)/$(install_apps) $(3)/`dirname $(install_apps)`;)\nendef\n\nBuild/Prepare=$(call Build/Prepare/Default,)\nBuild/Configure=$(call Build/Configure/Default,)\nBuild/Compile=$(call Build/Compile/Default,)\nBuild/Install=$(if $(PKG_INSTALL),$(call Build/Install/Default,))\nBuild/Dist=$(call Build/Dist/Default,)\nBuild/DistCheck=$(call Build/DistCheck/Default,)\n\n.NOTPARALLEL:\n\n.PHONY: prepare-package-install\nprepare-package-install:\n\t@mkdir -p $(PKG_INFO_DIR)\n\t@rm -f $(PKG_INSTALL_STAMP)\n\t@echo \"$(filter-out essential nonshared,$(PKG_FLAGS))\" > $(PKG_INSTALL_STAMP).flags\n\n$(PACKAGE_DIR):\n\tmkdir -p $@\n\ncompile:\n.install: .compile\ninstall: compile\n\nforce-clean-build: FORCE\n\trm -rf $(PKG_BUILD_DIR)\n\nclean-build: $(if $(wildcard $(PKG_BUILD_DIR)/.autoremove),force-clean-build)\n\nclean: force-clean-build\n\t$(CleanStaging)\n\t$(call Build/UninstallDev,$(STAGING_DIR),$(STAGING_DIR)/host)\n\t$(Build/Clean)\n\trm -f $(STAGING_DIR)/packages/$(STAGING_FILES_LIST)\n\ndist:\n\t$(Build/Dist)\n\ndistcheck:\n\t$(Build/DistCheck)\n"
  },
  {
    "path": "include/prereq-build.mk",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2006-2020 OpenWrt.org\n\ninclude $(TOPDIR)/rules.mk\ninclude $(INCLUDE_DIR)/prereq.mk\n\nSHELL:=sh\nPKG_NAME:=Build dependency\n\n\n# Required for the toolchain\n$(eval $(call TestHostCommand,working-make, \\\n\tPlease install GNU make v4.1 or later., \\\n\t$(MAKE) -v | grep -E 'Make (4\\.[1-9]|[5-9]\\.)'))\n\n$(eval $(call TestHostCommand,case-sensitive-fs, \\\n\tOpenWrt can only be built on a case-sensitive filesystem, \\\n\trm -f $(TMP_DIR)/test.*; touch $(TMP_DIR)/test.fs; \\\n\t\ttest ! -f $(TMP_DIR)/test.FS))\n\n$(eval $(call TestHostCommand,proper-umask, \\\n\tPlease build with umask 022 - other values produce broken packages, \\\n\tumask | grep -xE 0?0[012][012]))\n\nifndef IB\n$(eval $(call SetupHostCommand,gcc, \\\n\tPlease install the GNU C Compiler (gcc) 6 or later, \\\n\t$(CC) -dumpversion | grep -E '^([6-9]\\.?|1[0-9]\\.?)', \\\n\tgcc -dumpversion | grep -E '^([6-9]\\.?|1[0-9]\\.?)', \\\n\tgcc --version | grep -E 'Apple.(LLVM|clang)' ))\n\n$(eval $(call TestHostCommand,working-gcc, \\\n\tPlease reinstall the GNU C Compiler (6 or later) - \\\n\tit appears to be broken, \\\n\techo 'int main(int argc, char **argv) { return 0; }' | \\\n\t\tgcc -x c -o $(TMP_DIR)/a.out -))\n\n$(eval $(call SetupHostCommand,g++, \\\n\tPlease install the GNU C++ Compiler (g++) 6 or later, \\\n\t$(CXX) -dumpversion | grep -E '^([6-9]\\.?|1[0-9]\\.?)', \\\n\tg++ -dumpversion | grep -E '^([6-9]\\.?|1[0-9]\\.?)', \\\n\tg++ --version | grep -E 'Apple.(LLVM|clang)' ))\n\n$(eval $(call TestHostCommand,working-g++, \\\n\tPlease reinstall the GNU C++ Compiler (6 or later) - \\\n\tit appears to be broken, \\\n\techo 'int main(int argc, char **argv) { return 0; }' | \\\n\t\tg++ -x c++ -o $(TMP_DIR)/a.out - -lstdc++ && \\\n\t\t$(TMP_DIR)/a.out))\n\n$(eval $(call TestHostCommand,ncurses, \\\n\tPlease install ncurses. (Missing libncurses.so or ncurses.h), \\\n\techo 'int main(int argc, char **argv) { initscr(); return 0; }' | \\\n\t\tgcc -include ncurses.h -x c -o $(TMP_DIR)/a.out - -lncurses))\nendif # IB\n\nifeq ($(HOST_OS),Linux)\n  zlib_link_flags := -Wl,-Bstatic -lz -Wl,-Bdynamic\nelse\n  zlib_link_flags := -lz\nendif\n\n$(eval $(call TestHostCommand,perl-data-dumper, \\\n\tPlease install the Perl Data::Dumper module, \\\n\tperl -MData::Dumper -e 1))\n\n$(eval $(call TestHostCommand,perl-findbin, \\\n\tPlease install the Perl FindBin module, \\\n\tperl -MFindBin -e 1))\n\n$(eval $(call TestHostCommand,perl-file-copy, \\\n\tPlease install the Perl File::Copy module, \\\n\tperl -MFile::Copy -e 1))\n\n$(eval $(call TestHostCommand,perl-file-compare, \\\n\tPlease install the Perl File::Compare module, \\\n\tperl -MFile::Compare -e 1))\n\n$(eval $(call TestHostCommand,perl-thread-queue, \\\n\tPlease install the Perl Thread::Queue module, \\\n\tperl -MThread::Queue -e 1))\n\n$(eval $(call SetupHostCommand,tar,Please install GNU 'tar', \\\n\tgtar --version 2>&1 | grep GNU, \\\n\tgnutar --version 2>&1 | grep GNU, \\\n\ttar --version 2>&1 | grep GNU))\n\n$(eval $(call SetupHostCommand,find,Please install GNU 'find', \\\n\tgfind --version 2>&1 | grep GNU, \\\n\tfind --version 2>&1 | grep GNU))\n\n$(eval $(call SetupHostCommand,bash,Please install GNU 'bash', \\\n\tbash --version 2>&1 | grep GNU))\n\n$(eval $(call SetupHostCommand,xargs, \\\n\tPlease install 'xargs' that supports '-r/--no-run-if-empty', \\\n\tgxargs -r --version, \\\n\txargs -r --version))\n\n$(eval $(call SetupHostCommand,patch,Please install GNU 'patch', \\\n\tgpatch --version 2>&1 | grep 'Free Software Foundation', \\\n\tpatch --version 2>&1 | grep 'Free Software Foundation'))\n\n$(eval $(call SetupHostCommand,diff,Please install GNU diffutils, \\\n\tgdiff --version 2>&1 | grep GNU, \\\n\tdiff --version 2>&1 | grep GNU))\n\n$(eval $(call SetupHostCommand,cp,Please install GNU fileutils, \\\n\tgcp --help 2>&1 | grep 'Copy SOURCE', \\\n\tcp --help 2>&1 | grep 'Copy SOURCE'))\n\n$(eval $(call SetupHostCommand,seq,Please install seq, \\\n\tgseq --version, \\\n\tseq --version 2>&1 | grep seq))\n\n$(eval $(call SetupHostCommand,awk,Please install GNU 'awk', \\\n\tgawk --version 2>&1 | grep GNU, \\\n\tawk --version 2>&1 | grep GNU))\n\n$(eval $(call SetupHostCommand,grep,Please install GNU 'grep', \\\n\tggrep --version 2>&1 | grep GNU, \\\n\tgrep --version 2>&1 | grep GNU))\n\n$(eval $(call SetupHostCommand,egrep,Please install GNU 'grep', \\\n\tgegrep --version 2>&1 | grep GNU, \\\n\tegrep --version 2>&1 | grep GNU))\n\n$(eval $(call SetupHostCommand,getopt, \\\n\tPlease install an extended getopt version that supports --long, \\\n\tgnugetopt -o t --long test -- --test | grep '^ *--test *--', \\\n\tgetopt -o t --long test -- --test | grep '^ *--test *--', \\\n\t/usr/local/opt/gnu-getopt/bin/getopt -o t --long test -- --test | grep '^ *--test *--'))\n\n$(eval $(call SetupHostCommand,stat,Cannot find a file stat utility, \\\n\tgnustat -c%s $(TOPDIR)/Makefile, \\\n\tgstat -c%s $(TOPDIR)/Makefile, \\\n\tstat -c%s $(TOPDIR)/Makefile))\n\n$(eval $(call SetupHostCommand,unzip,Please install 'unzip', \\\n\tunzip 2>&1 | grep zipfile, \\\n\tunzip))\n\n$(eval $(call SetupHostCommand,bzip2,Please install 'bzip2', \\\n\tbzip2 --version </dev/null))\n\n$(eval $(call SetupHostCommand,wget,Please install GNU 'wget', \\\n\twget --version | grep GNU))\n\n$(eval $(call SetupHostCommand,install,Please install GNU 'install', \\\n\tinstall --version | grep GNU, \\\n\tginstall --version | grep GNU))\n\n$(eval $(call SetupHostCommand,perl,Please install Perl 5.x, \\\n\tperl --version | grep \"perl.*v5\"))\n\n$(eval $(call CleanupPython2))\n\n$(eval $(call SetupHostCommand,python,Please install Python >= 3.6, \\\n\tpython3.10 -V 2>&1 | grep 'Python 3', \\\n\tpython3.9 -V 2>&1 | grep 'Python 3', \\\n\tpython3.8 -V 2>&1 | grep 'Python 3', \\\n\tpython3.7 -V 2>&1 | grep 'Python 3', \\\n\tpython3.6 -V 2>&1 | grep 'Python 3', \\\n\tpython3 -V 2>&1 | grep -E 'Python 3\\.([6-9]|10)\\.?'))\n\n$(eval $(call SetupHostCommand,python3,Please install Python >= 3.6, \\\n\tpython3.10 -V 2>&1 | grep 'Python 3', \\\n\tpython3.9 -V 2>&1 | grep 'Python 3', \\\n\tpython3.8 -V 2>&1 | grep 'Python 3', \\\n\tpython3.7 -V 2>&1 | grep 'Python 3', \\\n\tpython3.6 -V 2>&1 | grep 'Python 3', \\\n\tpython3 -V 2>&1 | grep -E 'Python 3\\.([6-9]|10)\\.?'))\n\n$(eval $(call TestHostCommand,python3-distutils, \\\n\tPlease install the Python3 distutils module, \\\n\t$(STAGING_DIR_HOST)/bin/python3 -c 'import distutils'))\n\n$(eval $(call SetupHostCommand,git,Please install Git (git-core) >= 1.7.12.2, \\\n\tgit --exec-path | xargs -I % -- grep -q -- --recursive %/git-submodule))\n\n$(eval $(call SetupHostCommand,file,Please install the 'file' package, \\\n\tfile --version 2>&1 | grep file))\n\n$(eval $(call SetupHostCommand,rsync,Please install 'rsync', \\\n\trsync --version </dev/null))\n\n$(eval $(call SetupHostCommand,which,Please install 'which', \\\n\t/usr/bin/which which, \\\n\t/bin/which which, \\\n\twhich which))\n\n$(STAGING_DIR_HOST)/bin/mkhash: $(SCRIPT_DIR)/mkhash.c\n\tmkdir -p $(dir $@)\n\t$(CC) -O2 -I$(TOPDIR)/tools/include -o $@ $<\n\nprereq: $(STAGING_DIR_HOST)/bin/mkhash\n\n# Install ldconfig stub\n$(eval $(call TestHostCommand,ldconfig-stub,Failed to install stub, \\\n\t$(LN) /bin/true $(STAGING_DIR_HOST)/bin/ldconfig))\n"
  },
  {
    "path": "include/prereq.mk",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2006-2020 OpenWrt.org\n\nifneq ($(__prereq_inc),1)\n__prereq_inc:=1\n\nprereq:\n\tif [ -f $(TMP_DIR)/.prereq-error ]; then \\\n\t\techo; \\\n\t\tcat $(TMP_DIR)/.prereq-error; \\\n\t\trm -f $(TMP_DIR)/.prereq-error; \\\n\t\techo; \\\n\t\tfalse; \\\n\tfi\n\n.SILENT: prereq\nendif\n\nPREREQ_PREV=\n\n# 1: display name\n# 2: error message\ndefine Require\n  export PREREQ_CHECK=1\n  ifeq ($$(CHECK_$(1)),)\n    prereq: prereq-$(1)\n\n    prereq-$(1): $(if $(PREREQ_PREV),prereq-$(PREREQ_PREV)) FORCE\n\t\tprintf \"Checking '$(1)'... \"\n\t\tif $(NO_TRACE_MAKE) -f $(firstword $(MAKEFILE_LIST)) check-$(1) >/dev/null 2>/dev/null; then \\\n\t\t\techo 'ok.'; \\\n\t\telse \\\n\t\t\techo 'failed.'; \\\n\t\t\techo \"$(PKG_NAME): $(strip $(2))\" >> $(TMP_DIR)/.prereq-error; \\\n\t\tfi\n\n    check-$(1): FORCE\n\t  $(call Require/$(1))\n    CHECK_$(1):=1\n\n    .SILENT: prereq-$(1) check-$(1)\n    .NOTPARALLEL:\n  endif\n\n  PREREQ_PREV=$(1)\nendef\n\n\ndefine RequireCommand\n  define Require/$(1)\n    command -v $(1)\n  endef\n\n  $$(eval $$(call Require,$(1),$(2)))\nendef\n\ndefine RequireHeader\n  define Require/$(1)\n    [ -e \"$(1)\" ]\n  endef\n\n  $$(eval $$(call Require,$(1),$(2)))\nendef\n\ndefine CleanupPython2\n  define Require/python2-cleanup\n\tif [ -f \"$(STAGING_DIR_HOST)/bin/python\" ] && \\\n\t\t$(STAGING_DIR_HOST)/bin/python -V 2>&1 | \\\n\t\tgrep -q 'Python 2'; then \\\n\t\t\trm $(STAGING_DIR_HOST)/bin/python; \\\n\tfi\n  endef\n\n  $$(eval $$(call Require,python2-cleanup))\nendef\n\ndefine QuoteHostCommand\n'$(subst ','\"'\"',$(strip $(1)))'\nendef\n\n# 1: display name\n# 2: failure message\n# 3: test\ndefine TestHostCommand\n  define Require/$(1)\n\t($(3)) >/dev/null 2>/dev/null\n  endef\n\n  $$(eval $$(call Require,$(1),$(2)))\nendef\n\n# 1: canonical name\n# 2: failure message\n# 3+: candidates\ndefine SetupHostCommand\n  define Require/$(1)\n\t[ -f \"$(STAGING_DIR_HOST)/bin/$(strip $(1))\" ] && exit 0; \\\n\tfor cmd in $(call QuoteHostCommand,$(3)) $(call QuoteHostCommand,$(4)) \\\n\t           $(call QuoteHostCommand,$(5)) $(call QuoteHostCommand,$(6)) \\\n\t           $(call QuoteHostCommand,$(7)) $(call QuoteHostCommand,$(8)) \\\n\t           $(call QuoteHostCommand,$(9)) $(call QuoteHostCommand,$(10)) \\\n\t           $(call QuoteHostCommand,$(11)) $(call QuoteHostCommand,$(12)); do \\\n\t\tif [ -n \"$$$$$$$$cmd\" ]; then \\\n\t\t\tbin=\"$$$$$$$$(PATH=\"$(subst $(space),:,$(filter-out $(STAGING_DIR_HOST)/%,$(subst :,$(space),$(PATH))))\" \\\n\t\t\t\tcommand -v \"$$$$$$$${cmd%% *}\")\"; \\\n\t\t\tif [ -x \"$$$$$$$$bin\" ] && eval \"$$$$$$$$cmd\" >/dev/null 2>/dev/null; then \\\n\t\t\t\tmkdir -p \"$(STAGING_DIR_HOST)/bin\"; \\\n\t\t\t\tln -sf \"$$$$$$$$bin\" \"$(STAGING_DIR_HOST)/bin/$(strip $(1))\"; \\\n\t\t\t\texit 0; \\\n\t\t\tfi; \\\n\t\tfi; \\\n\tdone; \\\n\texit 1\n  endef\n\n  $$(eval $$(call Require,$(1),$(if $(2),$(2),Missing $(1) command)))\nendef\n"
  },
  {
    "path": "include/quilt.mk",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2007-2020 OpenWrt.org\n\nifeq ($(TARGET_BUILD),1)\n  PKG_BUILD_DIR:=$(LINUX_DIR)\nendif\n\nifneq ($(filter host-refresh refresh,$(MAKECMDGOALS)),)\n  override QUILT=1\n  override HOST_QUILT=1\nendif\n\nifneq ($(PKG_BUILD_DIR),)\n  QUILT?=$(if $(wildcard $(PKG_BUILD_DIR)/.quilt_used),y)\n  ifneq ($(QUILT),)\n    STAMP_CHECKED:=$(PKG_BUILD_DIR)/.quilt_checked\n    override CONFIG_AUTOREBUILD=\n    override CONFIG_AUTOREMOVE=\n    quilt-check: $(STAMP_CHECKED)\n  endif\nendif\n\nifneq ($(HOST_BUILD_DIR),)\n  HOST_QUILT?=$(if $(findstring command,$(origin QUILT)),$(QUILT),$(if $(wildcard $(HOST_BUILD_DIR)/.quilt_used),y))\n  ifneq ($(HOST_QUILT),)\n    HOST_STAMP_CHECKED:=$(HOST_BUILD_DIR)/.quilt_checked\n    override CONFIG_AUTOREBUILD=\n    override CONFIG_AUTOREMOVE=\n    host-quilt-check: $(HOST_STAMP_CHECKED)\n  endif\nendif\n\nifneq ($(if $(DUMP),1,$(__quilt_inc)),1)\n__quilt_inc:=1\n\nPATCH_DIR?=./patches\nFILES_DIR?=./files\nHOST_PATCH_DIR?=$(PATCH_DIR)\nHOST_FILES_DIR?=$(FILES_DIR)\n\nQUILT_CMD:=quilt --quiltrc=-\n\ndefine filter_series\nsed -e s,\\\\\\#.*,, $(1) | grep -E \\[a-zA-Z0-9\\]\nendef\n\ndefine PatchDir/Quilt\n\t@mkdir -p \"$(1)/patches$(if $(3),/$(patsubst %/,%,$(3)))\"\n\t@if [ -s \"$(2)/series\" ]; then \\\n\t\tmkdir -p \"$(1)/patches/$(3)\"; \\\n\t\tcp \"$(2)/series\" \"$(1)/patches/$(3)\"; \\\n\tfi\n\t@for patch in $$$$( (cd \"$(2)\" && if [ -f series ]; then $(call filter_series,series); else ls | sort; fi; ) 2>/dev/null ); do ( \\\n\t\tcp \"$(2)/$$$$patch\" \"$(1)/patches/$(3)\"; \\\n\t\techo \"$(3)$$$$patch\" >> \"$(1)/patches/series\"; \\\n\t); done\n\t$(if $(3),@echo $(3) >> \"$(1)/patches/.subdirs\")\nendef\n\ndefine PatchDir/Default\n\t@if [ -d \"$(2)\" ] && [ \"$$$$(ls $(2) | wc -l)\" -gt 0 ]; then \\\n\t\texport PATCH=\"$(PATCH)\"; \\\n\t\tif [ -s \"$(2)/series\" ]; then \\\n\t\t\t$(call filter_series,$(2)/series) | xargs -n1 \\\n\t\t\t\t$(KPATCH) \"$(1)\" \"$(2)\"; \\\n\t\telse \\\n\t\t\t$(KPATCH) \"$(1)\" \"$(2)\"; \\\n\t\tfi; \\\n\tfi\nendef\n\ndefine PatchDir\n$(call PatchDir/$(if $(strip $(QUILT)),Quilt,Default),$(strip $(1)),$(strip $(2)),$(strip $(3)))\nendef\n\ndefine HostPatchDir\n$(call PatchDir/$(if $(strip $(HOST_QUILT)),Quilt,Default),$(strip $(1)),$(strip $(2)),$(strip $(3)))\nendef\n\ndefine Host/Patch/Default\n\t$(if $(HOST_QUILT),rm -rf $(HOST_BUILD_DIR)/patches; mkdir -p $(HOST_BUILD_DIR)/patches)\n\t$(call HostPatchDir,$(HOST_BUILD_DIR),$(HOST_PATCH_DIR),)\n\t$(if $(HOST_QUILT),touch $(HOST_BUILD_DIR)/.quilt_used)\nendef\n\ndefine Build/Patch/Default\n\t$(if $(QUILT),rm -rf $(PKG_BUILD_DIR)/patches; mkdir -p $(PKG_BUILD_DIR)/patches)\n\t$(call PatchDir,$(PKG_BUILD_DIR),$(PATCH_DIR),)\n\t$(if $(QUILT),touch $(PKG_BUILD_DIR)/.quilt_used)\nendef\n\nkernel_files=$(foreach fdir,$(GENERIC_FILES_DIR) $(FILES_DIR),$(fdir)/.)\ndefine Kernel/Patch/Default\n\t$(if $(QUILT),rm -rf $(LINUX_DIR)/patches; mkdir -p $(LINUX_DIR)/patches)\n\t$(if $(kernel_files),$(CP) $(kernel_files) $(LINUX_DIR)/)\n\tfind $(LINUX_DIR)/ -name \\*.rej -or -name \\*.orig | $(XARGS) rm -f\n\tif [ -d $(GENERIC_PLATFORM_DIR)/patches$(if $(wildcard $(GENERIC_PLATFORM_DIR)/patches-$(KERNEL_PATCHVER)),-$(KERNEL_PATCHVER)) ]; then \\\n\t\techo \"generic patches directory is present. please move your patches to the pending directory\" ; \\\n\t\texit 1; \\\n\tfi\n\t$(call PatchDir,$(LINUX_DIR),$(GENERIC_BACKPORT_DIR),generic-backport/)\n\t$(call PatchDir,$(LINUX_DIR),$(GENERIC_PATCH_DIR),generic/)\n\t$(call PatchDir,$(LINUX_DIR),$(GENERIC_HACK_DIR),generic-hack/)\n\t$(call PatchDir,$(LINUX_DIR),$(PATCH_DIR),platform/)\nendef\n\ndefine Quilt/RefreshDir\n\tmkdir -p $(2)\n\t-rm -f $(2)/* 2>/dev/null >/dev/null\n\t@( \\\n\t\tfor patch in $$$$($(if $(3),grep \"^$(3)\",cat) $(1)/patches/series | awk '{print $$$$1}'); do \\\n\t\t\t$(CP) -v \"$(1)/patches/$$$$patch\" $(2); \\\n\t\tdone; \\\n\t)\nendef\n\ndefine Quilt/Refresh/Host\n\t$(call Quilt/RefreshDir,$(HOST_BUILD_DIR),$(HOST_PATCH_DIR))\nendef\n\ndefine Quilt/Refresh/Package\n\t$(call Quilt/RefreshDir,$(PKG_BUILD_DIR),$(PATCH_DIR))\nendef\n\ndefine Quilt/Refresh/Kernel\n\t@[ -z \"$$(grep -v '^generic/' $(PKG_BUILD_DIR)/patches/series | grep -v '^platform/')\" ] || { \\\n\t\techo \"All kernel patches must start with either generic/ or platform/\"; \\\n\t\tfalse; \\\n\t}\n\t$(call Quilt/RefreshDir,$(PKG_BUILD_DIR),$(GENERIC_BACKPORT_DIR),generic-backport/)\n\t$(call Quilt/RefreshDir,$(PKG_BUILD_DIR),$(GENERIC_PATCH_DIR),generic/)\n\t$(call Quilt/RefreshDir,$(PKG_BUILD_DIR),$(GENERIC_HACK_DIR),generic-hack/)\n\t$(call Quilt/RefreshDir,$(PKG_BUILD_DIR),$(PATCH_DIR),platform/)\nendef\n\ndefine Quilt/Template\n  $($(2)STAMP_CONFIGURED): $($(2)STAMP_CHECKED)\n  $(if $(NO_RECONFIGURE),$($(2)STAMP_BUILT),$($(2)STAMP_CONFIGURED)): FORCE\n  $($(2)STAMP_CHECKED): $($(2)STAMP_PREPARED)\n\tif [ -s \"$(1)/patches/series\" ]; then \\\n\t\t(cd \"$(1)\"; \\\n\t\t\tif $(QUILT_CMD) next >/dev/null 2>&1; then \\\n\t\t\t\t$(QUILT_CMD) push -a; \\\n\t\t\telse \\\n\t\t\t\t$(QUILT_CMD) top >/dev/null 2>&1; \\\n\t\t\tfi \\\n\t\t); \\\n\tfi\n\ttouch \"$$@\"\n\n  $(3)quilt-check: $($(2)STAMP_PREPARED) FORCE\n\t@[ -f \"$(1)/.quilt_used\" ] || { \\\n\t\techo \"The source directory was not unpacked using quilt. Please rebuild with QUILT=1\"; \\\n\t\tfalse; \\\n\t}\n\t@[ -f \"$(1)/patches/series\" ] || { \\\n\t\techo \"The source directory contains no quilt patches.\"; \\\n\t\tfalse; \\\n\t}\n\t@[ -n \"$$$$(ls $(1)/patches/series)\" -o \\\n\t   \"$$$$(cat $(1)/patches/series | $(MKHASH) md5)\" = \"$$(sort $(1)/patches/series | $(MKHASH) md5)\" ] || { \\\n\t\techo \"The patches are not sorted in the right order. Please fix.\"; \\\n\t\tfalse; \\\n\t}\n\n  $(3)refresh: $(3)quilt-check\n\t@cd \"$(1)\"; $(QUILT_CMD) pop -a -f >/dev/null 2>/dev/null\n\t@cd \"$(1)\"; while $(QUILT_CMD) next 2>/dev/null >/dev/null && $(QUILT_CMD) push; do \\\n\t\tQUILT_DIFF_OPTS=\"-p\" $(QUILT_CMD) refresh -p ab --no-index --no-timestamps; \\\n\tdone; ! $(QUILT_CMD) next 2>/dev/null >/dev/null\n\t$(Quilt/Refresh/$(4))\n\t\n  $(3)update: $(3)quilt-check\n\t$(Quilt/Refresh/$(4))\nendef\n\nBuild/Quilt=$(call Quilt/Template,$(PKG_BUILD_DIR),,,$(if $(TARGET_BUILD),Kernel,Package))\nHost/Quilt=$(call Quilt/Template,$(HOST_BUILD_DIR),HOST_,host-,Host)\n\nendif\n"
  },
  {
    "path": "include/rootfs.mk",
    "content": "ifdef CONFIG_USE_MKLIBS\n  define mklibs\n\trm -rf $(TMP_DIR)/mklibs-progs $(TMP_DIR)/mklibs-out\n\t# first find all programs and add them to the mklibs list\n\tfind $(STAGING_DIR_ROOT) -type f -perm /100 -exec \\\n\t\tfile -r -N -F '' {} + | \\\n\t\tawk ' /executable.*dynamically/ { print $$1 }' > $(TMP_DIR)/mklibs-progs\n\t# find all loadable objects that are not regular libraries and add them to the list as well\n\tfind $(STAGING_DIR_ROOT) -type f -name \\*.so\\* -exec \\\n\t\tfile -r -N -F '' {} + | \\\n\t\tawk ' /shared object/ { print $$1 }' > $(TMP_DIR)/mklibs-libs\n\tmkdir -p $(TMP_DIR)/mklibs-out\n\t$(STAGING_DIR_HOST)/bin/mklibs -D \\\n\t\t-d $(TMP_DIR)/mklibs-out \\\n\t\t--sysroot $(STAGING_DIR_ROOT) \\\n\t\t`cat $(TMP_DIR)/mklibs-libs | sed 's:/*[^/]\\+/*$$::' | uniq | sed 's:^$(STAGING_DIR_ROOT):-L :'` \\\n\t\t--ldlib $(patsubst $(STAGING_DIR_ROOT)/%,/%,$(firstword $(wildcard \\\n\t\t\t$(foreach name,ld-uClibc.so.* ld-linux.so.* ld-*.so ld-musl-*.so.*, \\\n\t\t\t  $(STAGING_DIR_ROOT)/lib/$(name) \\\n\t\t\t)))) \\\n\t\t--target $(REAL_GNU_TARGET_NAME) \\\n\t\t`cat $(TMP_DIR)/mklibs-progs $(TMP_DIR)/mklibs-libs` 2>&1\n\t$(RSTRIP) $(TMP_DIR)/mklibs-out\n\tfor lib in `ls $(TMP_DIR)/mklibs-out/*.so.* 2>/dev/null`; do \\\n\t\tLIB=\"$${lib##*/}\"; \\\n\t\tDEST=\"`ls \"$(1)/lib/$$LIB\" \"$(1)/usr/lib/$$LIB\" 2>/dev/null`\"; \\\n\t\t[ -n \"$$DEST\" ] || continue; \\\n\t\techo \"Copying stripped library $$lib to $$DEST\"; \\\n\t\tcp \"$$lib\" \"$$DEST\" || exit 1; \\\n\tdone\n  endef\nendif\n\n# where to build (and put) .ipk packages\nopkg = \\\n  IPKG_NO_SCRIPT=1 \\\n  IPKG_INSTROOT=$(1) \\\n  TMPDIR=$(1)/tmp \\\n  $(STAGING_DIR_HOST)/bin/opkg \\\n\t--offline-root $(1) \\\n\t--force-postinstall \\\n\t--add-dest root:/ \\\n\t--add-arch all:100 \\\n\t--add-arch $(if $(ARCH_PACKAGES),$(ARCH_PACKAGES),$(BOARD)):200\n\nTARGET_DIR_ORIG := $(TARGET_ROOTFS_DIR)/root.orig-$(BOARD)\n\nifdef CONFIG_CLEAN_IPKG\n  define clean_ipkg\n\t-find $(1)/usr/lib/opkg/info -type f -and -not -name '*.control' -delete\n\t-sed -i -ne '/^Require-User: /p' $(1)/usr/lib/opkg/info/*.control\n\tawk ' \\\n\t\tBEGIN { conffiles = 0; print \"Conffiles:\" } \\\n\t\t/^Conffiles:/ { conffiles = 1; next } \\\n\t\t!/^ / { conffiles = 0; next } \\\n\t\tconffiles == 1 { print } \\\n\t' $(1)/usr/lib/opkg/status >$(1)/usr/lib/opkg/status.new\n\tmv $(1)/usr/lib/opkg/status.new $(1)/usr/lib/opkg/status\n\t-find $(1)/usr/lib/opkg -empty -delete\n  endef\nendif\n\ndefine prepare_rootfs\n\t$(if $(2),@if [ -d '$(2)' ]; then \\\n\t\t$(call file_copy,$(2)/.,$(1)); \\\n\tfi)\n\t@mkdir -p $(1)/etc/rc.d\n\t@mkdir -p $(1)/var/lock\n\t@( \\\n\t\tcd $(1); \\\n\t\tfor script in ./usr/lib/opkg/info/*.postinst; do \\\n\t\t\tIPKG_INSTROOT=$(1) $$(command -v bash) $$script; \\\n\t\t\tret=$$?; \\\n\t\t\tif [ $$ret -ne 0 ]; then \\\n\t\t\t\techo \"postinst script $$script has failed with exit code $$ret\" >&2; \\\n\t\t\t\texit 1; \\\n\t\t\tfi; \\\n\t\tdone; \\\n\t\tfor script in ./etc/init.d/*; do \\\n\t\t\tgrep '#!/bin/sh /etc/rc.common' $$script >/dev/null || continue; \\\n\t\t\tif ! echo \" $(3) \" | grep -q \" $$(basename $$script) \"; then \\\n\t\t\t\tIPKG_INSTROOT=$(1) $$(command -v bash) ./etc/rc.common $$script enable; \\\n\t\t\t\techo \"Enabling\" $$(basename $$script); \\\n\t\t\telse \\\n\t\t\t\tIPKG_INSTROOT=$(1) $$(command -v bash) ./etc/rc.common $$script disable; \\\n\t\t\t\techo \"Disabling\" $$(basename $$script); \\\n\t\t\tfi; \\\n\t\tdone || true \\\n\t)\n\t$(if $(SOURCE_DATE_EPOCH),sed -i \"s/Installed-Time: .*/Installed-Time: $(SOURCE_DATE_EPOCH)/\" $(1)/usr/lib/opkg/status)\n\t@-find $(1) -name CVS -o -name .svn -o -name .git -o -name '.#*' | $(XARGS) rm -rf\n\trm -rf \\\n\t\t$(1)/boot \\\n\t\t$(1)/tmp/* \\\n\t\t$(1)/usr/lib/opkg/info/*.postinst* \\\n\t\t$(1)/usr/lib/opkg/lists/* \\\n\t\t$(1)/var/lock/*.lock\n\t$(call clean_ipkg,$(1))\n\t$(call mklibs,$(1))\n\t$(if $(SOURCE_DATE_EPOCH),find $(1)/ -mindepth 1 -execdir touch -hcd \"@$(SOURCE_DATE_EPOCH)\" \"{}\" +)\nendef\n"
  },
  {
    "path": "include/scan.awk",
    "content": "BEGIN { FS=\"/\" }\n$1 ~ /^feeds/ { FEEDS[$NF]=$0 }\n$1 !~ /^feeds/ { PKGS[$NF]=$0 }\nEND {\n\t# Filter-out OpenWrt packages which have a feeds equivalent\n\tfor (pkg in PKGS)\n\t\tif (pkg in FEEDS) {\n\t\t\tprint PKGS[pkg] > of\n\t\t\tdelete PKGS[pkg]\n\t\t}\n\tn = asort(PKGS)\n\tfor (i=1; i <= n; i++) {\n\t\tprint PKGS[i]\n\t}\n\tn = asort(FEEDS)\n\tfor (i=1; i <= n; i++){\n\t\tprint FEEDS[i]\n\t}\n}\n"
  },
  {
    "path": "include/scan.mk",
    "content": "include $(TOPDIR)/include/verbose.mk\ninclude $(TOPDIR)/rules.mk\nTMP_DIR:=$(TOPDIR)/tmp\n\nall: $(TMP_DIR)/.$(SCAN_TARGET)\n\nSCAN_TARGET ?= packageinfo\nSCAN_NAME ?= package\nSCAN_DIR ?= package\nTARGET_STAMP:=$(TMP_DIR)/info/.files-$(SCAN_TARGET).stamp\nFILELIST:=$(TMP_DIR)/info/.files-$(SCAN_TARGET)-$(SCAN_COOKIE)\nOVERRIDELIST:=$(TMP_DIR)/info/.overrides-$(SCAN_TARGET)-$(SCAN_COOKIE)\n\nexport PATH:=$(TOPDIR)/staging_dir/host/bin:$(PATH)\n\ndefine feedname\n$(if $(patsubst feeds/%,,$(1)),,$(word 2,$(subst /, ,$(1))))\nendef\n\nifeq ($(SCAN_NAME),target)\n  SCAN_DEPS=image/Makefile profiles/*.mk $(TOPDIR)/include/kernel*.mk $(TOPDIR)/include/target.mk image/*.mk\nelse\n  SCAN_DEPS=$(TOPDIR)/include/package*.mk\nifneq ($(call feedname,$(SCAN_DIR)),)\n  SCAN_DEPS += $(TOPDIR)/feeds/$(call feedname,$(SCAN_DIR))/*.mk\nendif\nendif\n\nifeq ($(IS_TTY),1)\n  ifneq ($(strip $(NO_COLOR)),1)\n    define progress\n\tprintf \"\\033[M\\r$(1)\" >&2;\n    endef\n  else\n    define progress\n\tprintf \"\\r$(1)\" >&2;\n    endef\n  endif\nelse\n  define progress\n\t:;\n  endef\nendif\n\ndefine PackageDir\n  $(TMP_DIR)/.$(SCAN_TARGET): $(TMP_DIR)/info/.$(SCAN_TARGET)-$(1)\n  $(TMP_DIR)/info/.$(SCAN_TARGET)-$(1): $(SCAN_DIR)/$(2)/Makefile $(foreach DEP,$(DEPS_$(SCAN_DIR)/$(2)/Makefile) $(SCAN_DEPS),$(wildcard $(if $(filter /%,$(DEP)),$(DEP),$(SCAN_DIR)/$(2)/$(DEP))))\n\t{ \\\n\t\t$$(call progress,Collecting $(SCAN_NAME) info: $(SCAN_DIR)/$(2)) \\\n\t\techo Source-Makefile: $(SCAN_DIR)/$(2)/Makefile; \\\n\t\t$(if $(3),echo Override: $(3),true); \\\n\t\t$(NO_TRACE_MAKE) --no-print-dir -r DUMP=1 FEED=\"$(call feedname,$(2))\" -C $(SCAN_DIR)/$(2) $(SCAN_MAKEOPTS) 2>/dev/null || { \\\n\t\t\tmkdir -p \"$(TOPDIR)/logs/$(SCAN_DIR)/$(2)\"; \\\n\t\t\t$(NO_TRACE_MAKE) --no-print-dir -r DUMP=1 FEED=\"$(call feedname,$(2))\" -C $(SCAN_DIR)/$(2) $(SCAN_MAKEOPTS) > $(TOPDIR)/logs/$(SCAN_DIR)/$(2)/dump.txt 2>&1; \\\n\t\t\t$$(call progress,ERROR: please fix $(SCAN_DIR)/$(2)/Makefile - see logs/$(SCAN_DIR)/$(2)/dump.txt for details\\n) \\\n\t\t\trm -f $$@; \\\n\t\t}; \\\n\t\techo; \\\n\t} > $$@.tmp\n\tmv $$@.tmp $$@\nendef\n\n$(OVERRIDELIST):\n\trm -f $(TMP_DIR)/info/.overrides-$(SCAN_TARGET)-*\n\ttouch $@\n\nifeq ($(SCAN_NAME),target)\n  GREP_STRING=BuildTarget\nelse\n  GREP_STRING=(Build/DefaultTargets|BuildPackage|KernelPackage)\nendif\n\n$(FILELIST): $(OVERRIDELIST)\n\trm -f $(TMP_DIR)/info/.files-$(SCAN_TARGET)-*\n\tfind -L $(SCAN_DIR) $(SCAN_EXTRA) -mindepth 1 $(if $(SCAN_DEPTH),-maxdepth $(SCAN_DEPTH)) -name Makefile | xargs grep -aHE 'call $(GREP_STRING)' | sed -e 's#^$(SCAN_DIR)/##' -e 's#/Makefile:.*##' | uniq | awk -v of=$(OVERRIDELIST) -f include/scan.awk > $@\n\n$(TMP_DIR)/info/.files-$(SCAN_TARGET).mk: $(FILELIST)\n\t( \\\n\t\tcat $< | awk '{print \"$(SCAN_DIR)/\" $$0 \"/Makefile\" }' | xargs grep -HE '^ *SCAN_DEPS *= *' | awk -F: '{ gsub(/^.*DEPS *= */, \"\", $$2); print \"DEPS_\" $$1 \"=\" $$2 }'; \\\n\t\tawk -F/ -v deps=\"$$DEPS\" -v of=\"$(OVERRIDELIST)\" ' \\\n\t\tBEGIN { \\\n\t\t\twhile (getline < (of)) \\\n\t\t\t\toverride[$$NF]=$$0; \\\n\t\t\tclose(of) \\\n\t\t} \\\n\t\t{ \\\n\t\t\tinfo=$$0; \\\n\t\t\tgsub(/\\//, \"_\", info); \\\n\t\t\tdir=$$0; \\\n\t\t\tpkg=\"\"; \\\n\t\t\tif($$NF in override) \\\n\t\t\t\tpkg=override[$$NF]; \\\n\t\t\tprint \"$$(eval $$(call PackageDir,\" info \",\" dir \",\" pkg \"))\"; \\\n\t\t} ' < $<; \\\n\t\ttrue; \\\n\t) > $@.tmp\n\tmv $@.tmp $@\n\n-include $(TMP_DIR)/info/.files-$(SCAN_TARGET).mk\n\n$(TARGET_STAMP)::\n\t+( \\\n\t\t$(NO_TRACE_MAKE) $(FILELIST); \\\n\t\tMD5SUM=$$(cat $(FILELIST) $(OVERRIDELIST) | $(MKHASH) md5 | awk '{print $$1}'); \\\n\t\t[ -f \"$@.$$MD5SUM\" ] || { \\\n\t\t\trm -f $@.*; \\\n\t\t\ttouch $@.$$MD5SUM; \\\n\t\t\ttouch $@; \\\n\t\t} \\\n\t)\n\n$(TMP_DIR)/.$(SCAN_TARGET): $(TARGET_STAMP)\n\t$(call progress,Collecting $(SCAN_NAME) info: merging...)\n\t-cat $(FILELIST) | awk '{gsub(/\\//, \"_\", $$0);print \"$(TMP_DIR)/info/.$(SCAN_TARGET)-\" $$0}' | xargs cat > $@ 2>/dev/null\n\t$(call progress,Collecting $(SCAN_NAME) info: done)\n\techo\n\nFORCE:\n.PHONY: FORCE\n.NOTPARALLEL:\n"
  },
  {
    "path": "include/shell.sh",
    "content": "getvar() {\n\teval \"echo \\\"\\${$1}\\\"\"\n}\n\nvar2file() {\n\tlocal var\n\teval \"var=\\\"\\${$1}\\\"\"\n\tif [ -n \"$var\" ]; then echo \"$var\" > \"$2\"; fi\n}\n\nisset() {\n\tlocal var\n\teval \"var=\\\"\\${$1}\\\"\"\n\t[ -n \"$var\" ]\n}\n"
  },
  {
    "path": "include/site/aarch64",
    "content": "#!/bin/sh\n. $TOPDIR/include/site/linux\nac_cv_c_littleendian=${ac_cv_c_littleendian=yes}\nac_cv_c_bigendian=${ac_cv_c_bigendian=no}\n\nac_cv_sizeof___int64=8\nac_cv_sizeof_char=1\nac_cv_sizeof_int=4\nac_cv_sizeof_int16_t=2\nac_cv_sizeof_int32_t=4\nac_cv_sizeof_int64_t=8\nac_cv_sizeof_long_int=8\nac_cv_sizeof_long_long=8\nac_cv_sizeof_long=8\nac_cv_sizeof_off_t=8\nac_cv_sizeof_short_int=2\nac_cv_sizeof_short=2\nac_cv_sizeof_size_t=8\nac_cv_sizeof_ssize_t=8\nac_cv_sizeof_u_int16_t=2\nac_cv_sizeof_u_int32_t=4\nac_cv_sizeof_u_int64_t=8\nac_cv_sizeof_uint16_t=2\nac_cv_sizeof_uint32_t=4\nac_cv_sizeof_uint64_t=8\nac_cv_sizeof_unsigned_int=4\nac_cv_sizeof_unsigned_long=8\nac_cv_sizeof_unsigned_long_long=8\nac_cv_sizeof_unsigned_short=2\nac_cv_sizeof_void_p=8\n"
  },
  {
    "path": "include/site/aarch64_be",
    "content": "#!/bin/sh\n. $TOPDIR/include/site/linux\nac_cv_c_littleendian=${ac_cv_c_littleendian=no}\nac_cv_c_bigendian=${ac_cv_c_bigendian=yes}\n\nac_cv_sizeof___int64=8\nac_cv_sizeof_char=1\nac_cv_sizeof_int=4\nac_cv_sizeof_int16_t=2\nac_cv_sizeof_int32_t=4\nac_cv_sizeof_int64_t=8\nac_cv_sizeof_long_int=8\nac_cv_sizeof_long_long=8\nac_cv_sizeof_long=8\nac_cv_sizeof_off_t=8\nac_cv_sizeof_short_int=2\nac_cv_sizeof_short=2\nac_cv_sizeof_size_t=8\nac_cv_sizeof_ssize_t=8\nac_cv_sizeof_u_int16_t=2\nac_cv_sizeof_u_int32_t=4\nac_cv_sizeof_u_int64_t=8\nac_cv_sizeof_uint16_t=2\nac_cv_sizeof_uint32_t=4\nac_cv_sizeof_uint64_t=8\nac_cv_sizeof_unsigned_int=4\nac_cv_sizeof_unsigned_long=8\nac_cv_sizeof_unsigned_long_long=8\nac_cv_sizeof_unsigned_short=2\nac_cv_sizeof_void_p=8\n"
  },
  {
    "path": "include/site/arc",
    "content": "#!/bin/sh\n. $TOPDIR/include/site/linux\nac_cv_c_littleendian=${ac_cv_c_littleendian=yes}\nac_cv_c_bigendian=${ac_cv_c_bigendian=no}\n\nac_cv_sizeof___int64=0\nac_cv_sizeof_char=1\nac_cv_sizeof_int=4\nac_cv_sizeof_int16_t=2\nac_cv_sizeof_int32_t=4\nac_cv_sizeof_int64_t=8\nac_cv_sizeof_long_int=4\nac_cv_sizeof_long_long=8\nac_cv_sizeof_long=4\nac_cv_sizeof_off_t=8\nac_cv_sizeof_short_int=2\nac_cv_sizeof_short=2\nac_cv_sizeof_size_t=4\nac_cv_sizeof_ssize_t=4\nac_cv_sizeof_u_int16_t=2\nac_cv_sizeof_u_int32_t=4\nac_cv_sizeof_u_int64_t=8\nac_cv_sizeof_uint16_t=2\nac_cv_sizeof_uint32_t=4\nac_cv_sizeof_uint64_t=8\nac_cv_sizeof_unsigned_int=4\nac_cv_sizeof_unsigned_long=4\nac_cv_sizeof_unsigned_long_long=8\nac_cv_sizeof_unsigned_short=2\nac_cv_sizeof_void_p=4\n"
  },
  {
    "path": "include/site/arm",
    "content": "#!/bin/sh\n. $TOPDIR/include/site/linux\nac_cv_c_littleendian=${ac_cv_c_littleendian=yes}\nac_cv_c_bigendian=${ac_cv_c_bigendian=no}\n\nac_cv_sizeof___int64=0\nac_cv_sizeof_char=1\nac_cv_sizeof_int=4\nac_cv_sizeof_int16_t=2\nac_cv_sizeof_int32_t=4\nac_cv_sizeof_int64_t=8\nac_cv_sizeof_long_int=4\nac_cv_sizeof_long_long=8\nac_cv_sizeof_long=4\nac_cv_sizeof_off_t=8\nac_cv_sizeof_short_int=2\nac_cv_sizeof_short=2\nac_cv_sizeof_size_t=4\nac_cv_sizeof_ssize_t=4\nac_cv_sizeof_u_int16_t=2\nac_cv_sizeof_u_int32_t=4\nac_cv_sizeof_u_int64_t=8\nac_cv_sizeof_uint16_t=2\nac_cv_sizeof_uint32_t=4\nac_cv_sizeof_uint64_t=8\nac_cv_sizeof_unsigned_int=4\nac_cv_sizeof_unsigned_long=4\nac_cv_sizeof_unsigned_long_long=8\nac_cv_sizeof_unsigned_short=2\nac_cv_sizeof_void_p=4\n"
  },
  {
    "path": "include/site/armeb",
    "content": "#!/bin/sh\n. $TOPDIR/include/site/linux\nac_cv_c_littleendian=${ac_cv_c_littleendian=no}\nac_cv_c_bigendian=${ac_cv_c_bigendian=yes}\n\nac_cv_sizeof___int64=0\nac_cv_sizeof_char=1\nac_cv_sizeof_int=4\nac_cv_sizeof_int16_t=2\nac_cv_sizeof_int32_t=4\nac_cv_sizeof_int64_t=8\nac_cv_sizeof_long_int=4\nac_cv_sizeof_long_long=8\nac_cv_sizeof_long=4\nac_cv_sizeof_off_t=8\nac_cv_sizeof_short_int=2\nac_cv_sizeof_short=2\nac_cv_sizeof_size_t=4\nac_cv_sizeof_ssize_t=4\nac_cv_sizeof_u_int16_t=2\nac_cv_sizeof_u_int32_t=4\nac_cv_sizeof_u_int64_t=8\nac_cv_sizeof_uint16_t=2\nac_cv_sizeof_uint32_t=4\nac_cv_sizeof_uint64_t=8\nac_cv_sizeof_unsigned_int=4\nac_cv_sizeof_unsigned_long=4\nac_cv_sizeof_unsigned_long_long=8\nac_cv_sizeof_unsigned_short=2\nac_cv_sizeof_void_p=4\n"
  },
  {
    "path": "include/site/darwin",
    "content": "ac_cv_func_futimens=no\nac_cv_func_utimensat=no\n"
  },
  {
    "path": "include/site/i386",
    "content": "#!/bin/sh\n. $TOPDIR/include/site/i486\n\n"
  },
  {
    "path": "include/site/i486",
    "content": "#!/bin/sh\n. $TOPDIR/include/site/linux\nac_cv_c_littleendian=${ac_cv_c_littleendian=yes}\nac_cv_c_bigendian=${ac_cv_c_bigendian=no}\n\nac_cv_sizeof___int64=0\nac_cv_sizeof_char=1\nac_cv_sizeof_int=4\nac_cv_sizeof_int16_t=2\nac_cv_sizeof_int32_t=4\nac_cv_sizeof_int64_t=8\nac_cv_sizeof_long_int=4\nac_cv_sizeof_long_long=8\nac_cv_sizeof_long=4\nac_cv_sizeof_off_t=8\nac_cv_sizeof_short_int=2\nac_cv_sizeof_short=2\nac_cv_sizeof_size_t=4\nac_cv_sizeof_ssize_t=4\nac_cv_sizeof_u_int16_t=2\nac_cv_sizeof_u_int32_t=4\nac_cv_sizeof_u_int64_t=8\nac_cv_sizeof_uint16_t=2\nac_cv_sizeof_uint32_t=4\nac_cv_sizeof_uint64_t=8\nac_cv_sizeof_unsigned_int=4\nac_cv_sizeof_unsigned_long=4\nac_cv_sizeof_unsigned_long_long=8\nac_cv_sizeof_unsigned_short=2\nac_cv_sizeof_void_p=4\n"
  },
  {
    "path": "include/site/i686",
    "content": "#!/bin/sh\n. $TOPDIR/include/site/i486\n\n"
  },
  {
    "path": "include/site/linux",
    "content": "ac_atomic_add=yes\nac_atomic_sub=yes\nac_cv_c_gettext_without_libintl=yes\nac_cv_c_long_double=no\nac_cv_conv_longlong_to_float=yes\nac_cv_file__dev_zero=yes\nac_cv_func___va_copy=no\nac_cv_func__exit=yes\nac_cv_func_bcopy=yes\nac_cv_func_bzero=yes\nac_cv_func_bcmp=yes\nac_cv_func_creal=yes\nac_cv_func_cimag=yes\nac_cv_func_fchmod=yes\nac_cv_func_getaddrinfo=yes\nac_cv_func_getcwd=yes\nac_cv_func_getdomainname=yes\nac_cv_func_getpgrp_void=yes\nac_cv_func_getpwuid_r=yes\nac_cv_func_gettimeofday=yes\nac_cv_func_index=yes\nac_cv_func_lstat_dereferences_slashed_symlink=yes\nac_cv_func_lstat_empty_string_bug=no\nac_cv_func_lstat=yes\nac_cv_func_malloc_0_nonnull=yes\nac_cv_func_malloc_works=yes\nac_cv_func_memcmp_clean=yes\nac_cv_func_memcmp_working=yes\nac_cv_func_posix_getgrgid_r=yes\nac_cv_func_posix_getpwuid_r=yes\nac_cv_func_psignal=yes\nac_cv_func_pthread_key_delete=yes\nac_cv_func_realloc_0_nonnull=yes\nac_cv_func_realloc_works=yes\nac_cv_func_rename=yes\nac_cv_func_rindex=yes\nac_cv_func_setlocale=yes\nac_cv_func_setgrent_void=yes\nac_cv_func_setpgrp_void=yes\nac_cv_func_setresuid=no\nac_cv_func_setvbuf_reversed=no\nac_cv_func_stat_empty_string_bug=no\nac_cv_func_stat_ignores_trailing_slash=no\nac_cv_func_strerror=yes\nac_cv_func_strftime=yes\nac_cv_func_utimes=yes\nac_cv_func___adjtimex=yes\nac_cv_func_va_copy=no\nac_cv_func_vsnprintf=yes\nac_cv_have_accrights_in_msghdr=no\nac_cv_have_broken_snprintf=no\nac_cv_have_control_in_msghdr=yes\nac_cv_have_decl_sys_siglist=no\nac_cv_have_openpty_ctty_bug=yes\nac_cv_have_space_d_name_in_struct_dirent=yes\nac_cv_header_netinet_sctp_h=no\nac_cv_header_netinet_sctp_uio_h=no\nac_cv_int64_t=yes\nac_cv_lbl_unaligned_fail=no\nac_cv_linux_kernel_pppoe=yes\nac_cv_linux_vers=2\nac_cv_pack_bitfields_reversed=yes\nac_cv_path_LDCONFIG=\nac_cv_regexec_segfault_emptystr=no\nac_cv_sctp=no\nac_cv_sys_restartable_syscalls=yes\nac_cv_time_r_type=POSIX\nac_cv_type_suseconds_t=yes\nac_cv_uchar=no\nac_cv_uint=yes\nac_cv_uint64_t=yes\nac_cv_ulong=yes\nac_cv_ushort=yes\nac_cv_va_copy=C99\nac_cv_va_val_copy=yes\nas_cv_unaligned_access=yes\nac_cv_func_malloc_0_nonnull=yes\nac_cv_func_realloc_0_nonnull=yes\n"
  },
  {
    "path": "include/site/m68k",
    "content": "#!/bin/sh\n. $TOPDIR/include/site/linux\nac_cv_c_littleendian=${ac_cv_c_littleendian=no}\nac_cv_c_bigendian=${ac_cv_c_bigendian=yes}\n\nac_cv_sizeof___int64=0\nac_cv_sizeof_char=1\nac_cv_sizeof_int=4\nac_cv_sizeof_int16_t=2\nac_cv_sizeof_int32_t=4\nac_cv_sizeof_int64_t=8\nac_cv_sizeof_long_int=4\nac_cv_sizeof_long_long=8\nac_cv_sizeof_long=4\nac_cv_sizeof_off_t=8\nac_cv_sizeof_short_int=2\nac_cv_sizeof_short=2\nac_cv_sizeof_size_t=4\nac_cv_sizeof_u_int16_t=2\nac_cv_sizeof_u_int32_t=4\nac_cv_sizeof_u_int64_t=8\nac_cv_sizeof_uint16_t=2\nac_cv_sizeof_uint32_t=4\nac_cv_sizeof_uint64_t=8\nac_cv_sizeof_unsigned_int=4\nac_cv_sizeof_unsigned_long=4\nac_cv_sizeof_unsigned_short=2\nac_cv_sizeof_void_p=4\n"
  },
  {
    "path": "include/site/mips",
    "content": "#!/bin/sh\n. $TOPDIR/include/site/linux\nac_cv_c_littleendian=${ac_cv_c_littleendian=no}\nac_cv_c_bigendian=${ac_cv_c_bigendian=yes}\n\nac_cv_sizeof___int64=0\nac_cv_sizeof_char=1\nac_cv_sizeof_int=4\nac_cv_sizeof_int16_t=2\nac_cv_sizeof_int32_t=4\nac_cv_sizeof_int64_t=8\nac_cv_sizeof_long_int=4\nac_cv_sizeof_long_long=8\nac_cv_sizeof_long=4\nac_cv_sizeof_off_t=8\nac_cv_sizeof_short_int=2\nac_cv_sizeof_short=2\nac_cv_sizeof_size_t=4\nac_cv_sizeof_ssize_t=4\nac_cv_sizeof_u_int16_t=2\nac_cv_sizeof_u_int32_t=4\nac_cv_sizeof_u_int64_t=8\nac_cv_sizeof_uint16_t=2\nac_cv_sizeof_uint32_t=4\nac_cv_sizeof_uint64_t=8\nac_cv_sizeof_unsigned_int=4\nac_cv_sizeof_unsigned_long=4\nac_cv_sizeof_unsigned_long_long=8\nac_cv_sizeof_unsigned_short=2\nac_cv_sizeof_void_p=4\n"
  },
  {
    "path": "include/site/mips64",
    "content": "#!/bin/sh\n. $TOPDIR/include/site/linux\nac_cv_c_littleendian=${ac_cv_c_littleendian=no}\nac_cv_c_bigendian=${ac_cv_c_bigendian=yes}\n\nac_cv_sizeof___int64=8\nac_cv_sizeof_char=1\nac_cv_sizeof_int=4\nac_cv_sizeof_int16_t=2\nac_cv_sizeof_int32_t=4\nac_cv_sizeof_int64_t=8\nac_cv_sizeof_long_int=8\nac_cv_sizeof_long_long=8\nac_cv_sizeof_long=8\nac_cv_sizeof_off_t=8\nac_cv_sizeof_short_int=2\nac_cv_sizeof_short=2\nac_cv_sizeof_size_t=8\nac_cv_sizeof_ssize_t=8\nac_cv_sizeof_u_int16_t=2\nac_cv_sizeof_u_int32_t=4\nac_cv_sizeof_u_int64_t=8\nac_cv_sizeof_uint16_t=2\nac_cv_sizeof_uint32_t=4\nac_cv_sizeof_uint64_t=8\nac_cv_sizeof_unsigned_int=4\nac_cv_sizeof_unsigned_long=8\nac_cv_sizeof_unsigned_long_long=8\nac_cv_sizeof_unsigned_short=2\nac_cv_sizeof_void_p=8\n"
  },
  {
    "path": "include/site/mips64el",
    "content": "#!/bin/sh\n. $TOPDIR/include/site/linux\nac_cv_c_littleendian=${ac_cv_c_littleendian=yes}\nac_cv_c_bigendian=${ac_cv_c_bigendian=no}\n\nac_cv_sizeof___int64=8\nac_cv_sizeof_char=1\nac_cv_sizeof_int=4\nac_cv_sizeof_int16_t=2\nac_cv_sizeof_int32_t=4\nac_cv_sizeof_int64_t=8\nac_cv_sizeof_long_int=8\nac_cv_sizeof_long_long=8\nac_cv_sizeof_long=8\nac_cv_sizeof_off_t=8\nac_cv_sizeof_short_int=2\nac_cv_sizeof_short=2\nac_cv_sizeof_size_t=8\nac_cv_sizeof_ssize_t=8\nac_cv_sizeof_u_int16_t=2\nac_cv_sizeof_u_int32_t=4\nac_cv_sizeof_u_int64_t=8\nac_cv_sizeof_uint16_t=2\nac_cv_sizeof_uint32_t=4\nac_cv_sizeof_uint64_t=8\nac_cv_sizeof_unsigned_int=4\nac_cv_sizeof_unsigned_long=8\nac_cv_sizeof_unsigned_long_long=8\nac_cv_sizeof_unsigned_short=2\nac_cv_sizeof_void_p=8\n"
  },
  {
    "path": "include/site/mipsel",
    "content": "#!/bin/sh\n. $TOPDIR/include/site/linux\nac_cv_c_littleendian=${ac_cv_c_littleendian=yes}\nac_cv_c_bigendian=${ac_cv_c_bigendian=no}\n\nac_cv_sizeof___int64=0\nac_cv_sizeof_char=1\nac_cv_sizeof_int=4\nac_cv_sizeof_int16_t=2\nac_cv_sizeof_int32_t=4\nac_cv_sizeof_int64_t=8\nac_cv_sizeof_long_int=4\nac_cv_sizeof_long_long=8\nac_cv_sizeof_long=4\nac_cv_sizeof_off_t=8\nac_cv_sizeof_short_int=2\nac_cv_sizeof_short=2\nac_cv_sizeof_size_t=4\nac_cv_sizeof_ssize_t=4\nac_cv_sizeof_u_int16_t=2\nac_cv_sizeof_u_int32_t=4\nac_cv_sizeof_u_int64_t=8\nac_cv_sizeof_uint16_t=2\nac_cv_sizeof_uint32_t=4\nac_cv_sizeof_uint64_t=8\nac_cv_sizeof_unsigned_int=4\nac_cv_sizeof_unsigned_long=4\nac_cv_sizeof_unsigned_long_long=8\nac_cv_sizeof_unsigned_short=2\nac_cv_sizeof_void_p=4\n"
  },
  {
    "path": "include/site/powerpc",
    "content": "#!/bin/sh\n. $TOPDIR/include/site/linux\nac_cv_c_littleendian=${ac_cv_c_littleendian=no}\nac_cv_c_bigendian=${ac_cv_c_bigendian=yes}\n\nac_cv_sizeof___int64=0\nac_cv_sizeof_char=1\nac_cv_sizeof_int=4\nac_cv_sizeof_int16_t=2\nac_cv_sizeof_int32_t=4\nac_cv_sizeof_int64_t=8\nac_cv_sizeof_long_int=4\nac_cv_sizeof_long_long=8\nac_cv_sizeof_long=4\nac_cv_sizeof_off_t=8\nac_cv_sizeof_short_int=2\nac_cv_sizeof_short=2\nac_cv_sizeof_size_t=4\nac_cv_sizeof_ssize_t=4\nac_cv_sizeof_u_int16_t=2\nac_cv_sizeof_u_int32_t=4\nac_cv_sizeof_u_int64_t=8\nac_cv_sizeof_uint16_t=2\nac_cv_sizeof_uint32_t=4\nac_cv_sizeof_uint64_t=8\nac_cv_sizeof_unsigned_int=4\nac_cv_sizeof_unsigned_long=4\nac_cv_sizeof_unsigned_long_long=8\nac_cv_sizeof_unsigned_short=2\nac_cv_sizeof_void_p=4\n"
  },
  {
    "path": "include/site/powerpc64",
    "content": "#!/bin/sh\n. $TOPDIR/include/site/linux\nac_cv_c_littleendian=${ac_cv_c_littleendian=no}\nac_cv_c_bigendian=${ac_cv_c_bigendian=yes}\n\nac_cv_sizeof_char=1\nac_cv_sizeof_char_p=8\nac_cv_sizeof_double=8\nac_cv_sizeof_float=4\nac_cv_sizeof_int=4\nac_cv_sizeof_long=8\nac_cv_sizeof_long_double=16\nac_cv_sizeof_long_int=8\nac_cv_sizeof_long_long=8\nac_cv_sizeof_long_long_int=8\nac_cv_sizeof_short=2\nac_cv_sizeof_short_int=2\nac_cv_sizeof_signed_char=1\nac_cv_sizeof_unsigned_char=1\nac_cv_sizeof_unsigned_int=4\nac_cv_sizeof_unsigned_long=8\nac_cv_sizeof_unsigned_long_int=8\nac_cv_sizeof_unsigned_long_long_int=8\nac_cv_sizeof_unsigned_short=2\nac_cv_sizeof_unsigned_short_int=2\nac_cv_sizeof_void_p=8\n"
  },
  {
    "path": "include/site/sparc",
    "content": "#!/bin/sh\n. $TOPDIR/include/site/linux\nac_cv_c_littleendian=${ac_cv_c_littleendian=no}\nac_cv_c_bigendian=${ac_cv_c_bigendian=yes}\n\nac_cv_sizeof___int64=0\nac_cv_sizeof_char=1\nac_cv_sizeof_int=4\nac_cv_sizeof_int16_t=2\nac_cv_sizeof_int32_t=4\nac_cv_sizeof_int64_t=8\nac_cv_sizeof_long_int=4\nac_cv_sizeof_long_long=8\nac_cv_sizeof_long=4\nac_cv_sizeof_off_t=8\nac_cv_sizeof_short_int=2\nac_cv_sizeof_short=2\nac_cv_sizeof_size_t=4\nac_cv_sizeof_ssize_t=4\nac_cv_sizeof_u_int16_t=2\nac_cv_sizeof_u_int32_t=4\nac_cv_sizeof_u_int64_t=8\nac_cv_sizeof_uint16_t=2\nac_cv_sizeof_uint32_t=4\nac_cv_sizeof_uint64_t=8\nac_cv_sizeof_unsigned_int=4\nac_cv_sizeof_unsigned_long=4\nac_cv_sizeof_unsigned_long_long=8\nac_cv_sizeof_unsigned_short=2\nac_cv_sizeof_void_p=4\n"
  },
  {
    "path": "include/site/x86_64",
    "content": "#!/bin/sh\n. $TOPDIR/include/site/linux\nac_cv_c_littleendian=${ac_cv_c_littleendian=yes}\nac_cv_c_bigendian=${ac_cv_c_bigendian=no}\n\nac_cv_sizeof___int64=0\nac_cv_sizeof_char=1\nac_cv_sizeof_int=4\nac_cv_sizeof_int16_t=2\nac_cv_sizeof_int32_t=4\nac_cv_sizeof_int64_t=8\nac_cv_sizeof_long_int=8\nac_cv_sizeof_long_long=8\nac_cv_sizeof_long=8\nac_cv_sizeof_off_t=8\nac_cv_sizeof_short_int=2\nac_cv_sizeof_short=2\nac_cv_sizeof_size_t=8\nac_cv_sizeof_ssize_t=8\nac_cv_sizeof_u_int16_t=2\nac_cv_sizeof_u_int32_t=4\nac_cv_sizeof_u_int64_t=8\nac_cv_sizeof_uint16_t=2\nac_cv_sizeof_uint32_t=4\nac_cv_sizeof_uint64_t=8\nac_cv_sizeof_unsigned_int=4\nac_cv_sizeof_unsigned_long=8\nac_cv_sizeof_unsigned_long_long=8\nac_cv_sizeof_unsigned_short=2\nac_cv_sizeof_void_p=8\n"
  },
  {
    "path": "include/subdir.mk",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2007-2020 OpenWrt.org\n\nifeq ($(MAKECMDGOALS),prereq)\n  SUBTARGETS:=prereq\n  PREREQ_ONLY:=1\nelse\n  SUBTARGETS:=$(DEFAULT_SUBDIR_TARGETS)\nendif\n\nsubtarget-default = $(filter-out ., \\\n\t$(if $($(1)/builddirs-$(2)),$($(1)/builddirs-$(2)), \\\n\t$(if $($(1)/builddirs-default),$($(1)/builddirs-default), \\\n\t$($(1)/builddirs))))\n\ndefine subtarget\n  $(call warn_eval,$(1),t,T,$(1)/$(2): $($(1)/) $(foreach bd,$(call subtarget-default,$(1),$(2)),$(1)/$(bd)/$(2)))\n\nendef\n\ndefine ERROR\n\t($(call MESSAGE, $(2)); $(if $(BUILD_LOG), echo \"$(2)\" >> $(BUILD_LOG_DIR)/$(1)/error.txt;) $(if $(3),, exit 1;))\nendef\n\nlastdir=$(word $(words $(subst /, ,$(1))),$(subst /, ,$(1)))\ndiralias=$(if $(findstring $(1),$(call lastdir,$(1))),,$(call lastdir,$(1)))\n\nsubdir_make_opts = \\\n\t$(if $(SUBDIR_MAKE_DEBUG),-d) -r -C $(1) \\\n\t\tBUILD_SUBDIR=\"$(1)\" \\\n\t\tBUILD_VARIANT=\"$(4)\" \\\n\t\tALL_VARIANTS=\"$(5)\"\n\n# 1: subdir\n# 2: target\n# 3: build type\n# 4: build variant\n# 5: all variants\nlog_make = \\\n\t $(if $(call debug,$(1),v),,@)+ \\\n\t $(if $(BUILD_LOG), \\\n\t\tset -o pipefail; \\\n\t\tmkdir -p $(BUILD_LOG_DIR)/$(1)$(if $(4),/$(4));) \\\n\t$(SCRIPT_DIR)/time.pl \"time: $(1)$(if $(4),/$(4))/$(if $(3),$(3)-)$(2)\" \\\n\t$$(SUBMAKE) $(subdir_make_opts) $(if $(3),$(3)-)$(2) \\\n\t\t$(if $(BUILD_LOG),SILENT= 2>&1 | tee $(BUILD_LOG_DIR)/$(1)$(if $(4),/$(4))/$(if $(3),$(3)-)$(2).txt)\n\nifdef CONFIG_AUTOREMOVE\nrebuild_check = \\\n\t@-$$(NO_TRACE_MAKE) $(subdir_make_opts) check-depends >/dev/null 2>/dev/null; \\\n\t\t$(if $(BUILD_LOG),mkdir -p $(BUILD_LOG_DIR)/$(1)$(if $(4),/$(4));) \\\n\t\t$$(NO_TRACE_MAKE) $(if $(BUILD_LOG),-d) -q $(subdir_make_opts) .$(if $(3),$(3)-)$(2) \\\n\t\t\t> $(if $(BUILD_LOG),$(BUILD_LOG_DIR)/$(1)$(if $(4),/$(4))/check-$(if $(3),$(3)-)$(2).txt,/dev/null) 2>&1 || \\\n\t\t\t$$(SUBMAKE) $(subdir_make_opts) clean-build >/dev/null 2>/dev/null\n\nendif\n\n# Parameters: <subdir>\ndefine subdir\n  $(call warn,$(1),d,D $(1))\n  $(foreach bd,$($(1)/builddirs),\n    $(call warn,$(1),d,BD $(1)/$(bd))\n    $(foreach target,$(SUBTARGETS) $($(1)/subtargets),\n      $(foreach btype,$(buildtypes-$(bd)),\n        $(call warn_eval,$(1)/$(bd),t,T,$(1)/$(bd)/$(btype)/$(target): $(if $(NO_DEPS)$(QUILT),,$($(1)/$(bd)/$(btype)/$(target)) $(call $(1)//$(btype)/$(target),$(1)/$(bd)/$(btype))))\n\t\t  $(call log_make,$(1)/$(bd),$(target),$(btype),$(filter-out __default,$(variant)),$($(1)/$(bd)/variants)) \\\n\t\t\t|| $(call ERROR,$(2),   ERROR: $(1)/$(bd) [$(btype)] failed to build.,$(findstring $(bd),$($(1)/builddirs-ignore-$(btype)-$(target))))\n        $(if $(call diralias,$(bd)),$(call warn_eval,$(1)/$(bd),l,T,$(1)/$(call diralias,$(bd))/$(btype)/$(target): $(1)/$(bd)/$(btype)/$(target)))\n      )\n      $(call warn_eval,$(1)/$(bd),t,T,$(1)/$(bd)/$(target): $(if $(NO_DEPS)$(QUILT),,$($(1)/$(bd)/$(target)) $(call $(1)//$(target),$(1)/$(bd))))\n        $(foreach variant,$(filter-out *,$(if $(BUILD_VARIANT),$(BUILD_VARIANT),$(if $(strip $($(1)/$(bd)/variants)),$($(1)/$(bd)/variants),$(if $($(1)/$(bd)/default-variant),$($(1)/$(bd)/default-variant),__default)))),\n\t\t\t$(if $(BUILD_LOG),@mkdir -p $(BUILD_LOG_DIR)/$(1)/$(bd)/$(filter-out __default,$(variant)))\n\t\t\t$(if $($(1)/autoremove),$(call rebuild_check,$(1)/$(bd),$(target),,$(filter-out __default,$(variant)),$($(1)/$(bd)/variants)))\n\t\t\t$(call log_make,$(1)/$(bd),$(target),,$(filter-out __default,$(variant)),$($(1)/$(bd)/variants)) \\\n\t\t\t\t|| $(call ERROR,$(1),   ERROR: $(1)/$(bd) failed to build$(if $(filter-out __default,$(variant)), (build variant: $(variant))).,$(findstring $(bd),$($(1)/builddirs-ignore-$(target)))) \n        )\n      $(if $(PREREQ_ONLY)$(DUMP_TARGET_DB),,\n        # aliases\n        $(if $(call diralias,$(bd)),$(call warn_eval,$(1)/$(bd),l,T,$(1)/$(call diralias,$(bd))/$(target): $(1)/$(bd)/$(target)))\n\t  )\n\t)\n  )\n  $(foreach target,$(SUBTARGETS) $($(1)/subtargets),$(call subtarget,$(1),$(target)))\nendef\n\nifndef DUMP_TARGET_DB\n# Parameters: <subdir> <name> <target> <depends> <config options> <stampfile location>\ndefine stampfile\n  $(1)/stamp-$(3):=$(if $(6),$(6),$(STAGING_DIR))/stamp/.$(2)_$(3)$(5)\n  $$($(1)/stamp-$(3)): $(TMP_DIR)/.build $(4)\n\t@+$(SCRIPT_DIR)/timestamp.pl -n $$($(1)/stamp-$(3)) $(1) $(4) || \\\n\t\t$(MAKE) $(if $(QUIET),--no-print-directory) $$($(1)/flags-$(3)) $(1)/$(3)\n\t@mkdir -p $$$$(dirname $$($(1)/stamp-$(3)))\n\t@touch $$($(1)/stamp-$(3))\n\n  $$(if $(call debug,$(1),v),,.SILENT: $$($(1)/stamp-$(3)))\n\n  .PRECIOUS: $$($(1)/stamp-$(3)) # work around a make bug\n\n  $(1)//clean:=$(1)/stamp-$(3)/clean\n  $(1)/stamp-$(3)/clean: FORCE\n\t@rm -f $$($(1)/stamp-$(3))\n\nendef\nendif\n"
  },
  {
    "path": "include/target.mk",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2007-2008 OpenWrt.org\n# Copyright (C) 2016 LEDE Project\n\nifneq ($(__target_inc),1)\n__target_inc=1\n\n# default device type\nDEVICE_TYPE?=router\n\n# Default packages - the really basic set\nDEFAULT_PACKAGES:=\\\n\tbase-files \\\n\tca-bundle \\\n\tdropbear \\\n\tfstools \\\n\tlibc \\\n\tlibgcc \\\n\tlibustream-wolfssl \\\n\tlogd \\\n\tmtd \\\n\tnetifd \\\n\topkg \\\n\tuci \\\n\tuclient-fetch \\\n\turandom-seed \\\n\turngd\n\nifneq ($(CONFIG_SELINUX),)\nDEFAULT_PACKAGES+=busybox-selinux procd-selinux\nelse\nDEFAULT_PACKAGES+=busybox procd\nendif\n\n# include ujail on systems with enough storage\nifeq ($(CONFIG_SMALL_FLASH),)\nDEFAULT_PACKAGES+=procd-ujail\nendif\n\n# include seccomp ld-preload hooks if kernel supports it\nifneq ($(CONFIG_SECCOMP),)\nDEFAULT_PACKAGES+=procd-seccomp\nendif\n\n# For the basic set\nDEFAULT_PACKAGES.basic:=\n# For nas targets\nDEFAULT_PACKAGES.nas:=\\\n\tblock-mount \\\n\tfdisk \\\n\tlsblk \\\n\tmdadm\n# For router targets\nDEFAULT_PACKAGES.router:=\\\n\tdnsmasq \\\n\tfirewall4 \\\n\tnftables \\\n\tkmod-nft-offload \\\n\todhcp6c \\\n\todhcpd-ipv6only \\\n\tppp \\\n\tppp-mod-pppoe\n\nifneq ($(DUMP),)\n  all: dumpinfo\nendif\n\ntarget_conf=$(subst .,_,$(subst -,_,$(subst /,_,$(1))))\nifeq ($(DUMP),)\n  PLATFORM_DIR:=$(TOPDIR)/target/linux/$(BOARD)\n  SUBTARGET:=$(strip $(foreach subdir,$(patsubst $(PLATFORM_DIR)/%/target.mk,%,$(wildcard $(PLATFORM_DIR)/*/target.mk)),$(if $(CONFIG_TARGET_$(call target_conf,$(BOARD)_$(subdir))),$(subdir))))\nelse\n  PLATFORM_DIR:=${CURDIR}\n  ifeq ($(SUBTARGETS),)\n    SUBTARGETS:=$(strip $(patsubst $(PLATFORM_DIR)/%/target.mk,%,$(wildcard $(PLATFORM_DIR)/*/target.mk)))\n  endif\nendif\n\nTARGETID:=$(BOARD)$(if $(SUBTARGET),/$(SUBTARGET))\nPLATFORM_SUBDIR:=$(PLATFORM_DIR)$(if $(SUBTARGET),/$(SUBTARGET))\n\nifneq ($(TARGET_BUILD),1)\n  ifndef DUMP\n    include $(PLATFORM_DIR)/Makefile\n    ifneq ($(PLATFORM_DIR),$(PLATFORM_SUBDIR))\n      include $(PLATFORM_SUBDIR)/target.mk\n    endif\n  endif\nelse\n  ifneq ($(SUBTARGET),)\n    -include ./$(SUBTARGET)/target.mk\n  endif\nendif\n\n# Add device specific packages (here below to allow device type set from subtarget)\nDEFAULT_PACKAGES += $(DEFAULT_PACKAGES.$(DEVICE_TYPE))\n\nfilter_packages = $(filter-out -% $(patsubst -%,%,$(filter -%,$(1))),$(1))\nextra_packages = $(if $(filter wpad wpad-% nas,$(1)),iwinfo)\n\ndefine ProfileDefault\n  NAME:=\n  PRIORITY:=\n  PACKAGES:=\nendef\n\nifndef Profile\ndefine Profile\n  $(eval $(call ProfileDefault))\n  $(eval $(call Profile/$(1)))\n  dumpinfo : $(call shexport,Profile/$(1)/Description)\n  PACKAGES := $(filter-out -%,$(PACKAGES))\n  DUMPINFO += \\\n\techo \"Target-Profile: $(1)\"; \\\n\t$(if $(PRIORITY), echo \"Target-Profile-Priority: $(PRIORITY)\"; ) \\\n\techo \"Target-Profile-Name: $(NAME)\"; \\\n\techo \"Target-Profile-Packages: $(PACKAGES) $(call extra_packages,$(DEFAULT_PACKAGES) $(PACKAGES))\"; \\\n\techo \"Target-Profile-Description:\"; \\\n\techo \"$$$$$$$$$(call shvar,Profile/$(1)/Description)\"; \\\n\techo \"@@\"; \\\n\techo;\nendef\nendif\n\nifneq ($(PLATFORM_DIR),$(PLATFORM_SUBDIR))\n  define IncludeProfiles\n    -include $(sort $(wildcard $(PLATFORM_DIR)/profiles/*.mk))\n    -include $(sort $(wildcard $(PLATFORM_SUBDIR)/profiles/*.mk))\n  endef\nelse\n  define IncludeProfiles\n    -include $(sort $(wildcard $(PLATFORM_DIR)/profiles/*.mk))\n  endef\nendif\n\nPROFILE?=$(call qstrip,$(CONFIG_TARGET_PROFILE))\n\nifeq ($(TARGET_BUILD),1)\n  ifneq ($(DUMP),)\n    $(eval $(call IncludeProfiles))\n  endif\nendif\n\nifneq ($(TARGET_BUILD)$(if $(DUMP),,1),)\n  include $(INCLUDE_DIR)/kernel-version.mk\nendif\n\nGENERIC_PLATFORM_DIR := $(TOPDIR)/target/linux/generic\nGENERIC_BACKPORT_DIR := $(GENERIC_PLATFORM_DIR)/backport$(if $(wildcard $(GENERIC_PLATFORM_DIR)/backport-$(KERNEL_PATCHVER)),-$(KERNEL_PATCHVER))\nGENERIC_PATCH_DIR := $(GENERIC_PLATFORM_DIR)/pending$(if $(wildcard $(GENERIC_PLATFORM_DIR)/pending-$(KERNEL_PATCHVER)),-$(KERNEL_PATCHVER))\nGENERIC_HACK_DIR := $(GENERIC_PLATFORM_DIR)/hack$(if $(wildcard $(GENERIC_PLATFORM_DIR)/hack-$(KERNEL_PATCHVER)),-$(KERNEL_PATCHVER))\nGENERIC_FILES_DIR := $(foreach dir,$(wildcard $(GENERIC_PLATFORM_DIR)/files $(GENERIC_PLATFORM_DIR)/files-$(KERNEL_PATCHVER)),\"$(dir)\")\n\n__config_name_list = $(1)/config-$(KERNEL_PATCHVER) $(1)/config-default\n__config_list = $(firstword $(wildcard $(call __config_name_list,$(1))))\nfind_kernel_config=$(if $(__config_list),$(__config_list),$(lastword $(__config_name_list)))\n\nGENERIC_LINUX_CONFIG = $(call find_kernel_config,$(GENERIC_PLATFORM_DIR))\nLINUX_TARGET_CONFIG = $(call find_kernel_config,$(PLATFORM_DIR))\nifneq ($(PLATFORM_DIR),$(PLATFORM_SUBDIR))\n  LINUX_SUBTARGET_CONFIG = $(call find_kernel_config,$(PLATFORM_SUBDIR))\nendif\n\n# config file list used for compiling\nLINUX_KCONFIG_LIST = $(wildcard $(GENERIC_LINUX_CONFIG) $(LINUX_TARGET_CONFIG) $(LINUX_SUBTARGET_CONFIG) $(TOPDIR)/env/kernel-config)\n\n# default config list for reconfiguring\n# defaults to subtarget if subtarget exists and target does not\n# defaults to target otherwise\nUSE_SUBTARGET_CONFIG = $(if $(wildcard $(LINUX_TARGET_CONFIG)),,$(if $(LINUX_SUBTARGET_CONFIG),1))\n\nLINUX_RECONFIG_LIST = $(wildcard $(GENERIC_LINUX_CONFIG) $(LINUX_TARGET_CONFIG) $(if $(USE_SUBTARGET_CONFIG),$(LINUX_SUBTARGET_CONFIG)))\nLINUX_RECONFIG_TARGET = $(if $(USE_SUBTARGET_CONFIG),$(LINUX_SUBTARGET_CONFIG),$(LINUX_TARGET_CONFIG))\n\nCFG_TARGET = $(CONFIG_TARGET)\nifeq ($(CFG_TARGET),platform)\n  CFG_TARGET = target\n  $(warning Deprecation warning: use CONFIG_TARGET=target instead.)\nelse ifeq ($(CFG_TARGET),subtarget_platform)\n  CFG_TARGET = subtarget_target\n  $(warning Deprecation warning: use CONFIG_TARGET=subtarget_target instead.)\nendif\n\n# select the config file to be changed by kernel_menuconfig/kernel_oldconfig\nifeq ($(CFG_TARGET),target)\n  LINUX_RECONFIG_LIST = $(wildcard $(GENERIC_LINUX_CONFIG) $(LINUX_TARGET_CONFIG))\n  LINUX_RECONFIG_TARGET = $(LINUX_TARGET_CONFIG)\nelse ifeq ($(CFG_TARGET),subtarget)\n  LINUX_RECONFIG_LIST = $(wildcard $(GENERIC_LINUX_CONFIG) $(LINUX_TARGET_CONFIG) $(LINUX_SUBTARGET_CONFIG))\n  LINUX_RECONFIG_TARGET = $(LINUX_SUBTARGET_CONFIG)\nelse ifeq ($(CFG_TARGET),subtarget_target)\n  LINUX_RECONFIG_LIST = $(wildcard $(GENERIC_LINUX_CONFIG) $(LINUX_SUBTARGET_CONFIG) $(LINUX_TARGET_CONFIG))\n  LINUX_RECONFIG_TARGET = $(LINUX_TARGET_CONFIG)\nelse ifeq ($(CFG_TARGET),env)\n  LINUX_RECONFIG_LIST = $(LINUX_KCONFIG_LIST)\n  LINUX_RECONFIG_TARGET = $(TOPDIR)/env/kernel-config\nelse ifneq ($(strip $(CFG_TARGET)),)\n  $(error CONFIG_TARGET=$(CFG_TARGET) is invalid. Valid: target|subtarget|subtarget_target|env)\nendif\n\n__linux_confcmd = $(2) $(patsubst %,+,$(wordlist 2,9999,$(1))) $(1)\n\nLINUX_CONF_CMD = $(SCRIPT_DIR)/kconfig.pl $(call __linux_confcmd,$(LINUX_KCONFIG_LIST))\nLINUX_RECONF_CMD = $(SCRIPT_DIR)/kconfig.pl $(call __linux_confcmd,$(LINUX_RECONFIG_LIST))\nLINUX_RECONF_DIFF = $(SCRIPT_DIR)/kconfig.pl - '>' $(call __linux_confcmd,$(filter-out $(LINUX_RECONFIG_TARGET),$(LINUX_RECONFIG_LIST))) $(1) $(GENERIC_PLATFORM_DIR)/config-filter\n\nifeq ($(DUMP),1)\n  BuildTarget=$(BuildTargets/DumpCurrent)\n\n  CPU_CFLAGS = -Os -pipe\n  ifneq ($(findstring mips,$(ARCH)),)\n    ifneq ($(findstring mips64,$(ARCH)),)\n      CPU_TYPE ?= mips64\n    else\n      CPU_TYPE ?= mips32\n    endif\n    CPU_CFLAGS += -mno-branch-likely\n    CPU_CFLAGS_mips32 = -mips32 -mtune=mips32\n    CPU_CFLAGS_mips64 = -mips64 -mtune=mips64 -mabi=64\n    CPU_CFLAGS_mips64r2 = -mips64r2 -mtune=mips64r2 -mabi=64\n    CPU_CFLAGS_4kec = -mips32r2 -mtune=4kec\n    CPU_CFLAGS_24kc = -mips32r2 -mtune=24kc\n    CPU_CFLAGS_74kc = -mips32r2 -mtune=74kc\n    CPU_CFLAGS_octeonplus = -march=octeon+ -mabi=64\n  endif\n  ifeq ($(ARCH),i386)\n    CPU_TYPE ?= pentium-mmx\n    CPU_CFLAGS_pentium-mmx = -march=pentium-mmx\n    CPU_CFLAGS_pentium4 = -march=pentium4\n  endif\n  ifneq ($(findstring arm,$(ARCH)),)\n    CPU_TYPE ?= xscale\n  endif\n  ifeq ($(ARCH),powerpc)\n    CPU_CFLAGS_603e:=-mcpu=603e\n    CPU_CFLAGS_8540:=-mcpu=8540\n    CPU_CFLAGS_405:=-mcpu=405\n    CPU_CFLAGS_440:=-mcpu=440\n    CPU_CFLAGS_464fp:=-mcpu=464fp\n  endif\n  ifeq ($(ARCH),powerpc64)\n    CPU_TYPE ?= powerpc64\n    CPU_CFLAGS_e5500:=-mcpu=e5500\n    CPU_CFLAGS_powerpc64:=-mcpu=powerpc64\n  endif\n  ifeq ($(ARCH),sparc)\n    CPU_TYPE = sparc\n    CPU_CFLAGS_ultrasparc = -mcpu=ultrasparc\n  endif\n  ifeq ($(ARCH),aarch64)\n    CPU_TYPE ?= generic\n    CPU_CFLAGS_generic = -mcpu=generic\n    CPU_CFLAGS_cortex-a53 = -mcpu=cortex-a53\n  endif\n  ifeq ($(ARCH),arc)\n    CPU_TYPE ?= arc700\n    CPU_CFLAGS += -matomic\n    CPU_CFLAGS_arc700 = -mcpu=arc700\n    CPU_CFLAGS_archs = -mcpu=archs\n  endif\n  ifneq ($(CPU_TYPE),)\n    ifndef CPU_CFLAGS_$(CPU_TYPE)\n      $(warning CPU_TYPE \"$(CPU_TYPE)\" doesn't correspond to a known type)\n    endif\n  endif\n  DEFAULT_CFLAGS=$(strip $(CPU_CFLAGS) $(CPU_CFLAGS_$(CPU_TYPE)) $(CPU_CFLAGS_$(CPU_SUBTYPE)))\n\n  ifneq ($(BOARD),)\n    TMP_CONFIG:=$(TMP_DIR)/.kconfig-$(call target_conf,$(TARGETID))\n    $(TMP_CONFIG): $(LINUX_KCONFIG_LIST)\n\t\t$(LINUX_CONF_CMD) > $@ || rm -f $@\n    -include $(TMP_CONFIG)\n    .SILENT: $(TMP_CONFIG)\n    .PRECIOUS: $(TMP_CONFIG)\n\n    ifdef KERNEL_TESTING_PATCHVER\n      ifneq ($(KERNEL_TESTING_PATCHVER),$(KERNEL_PATCHVER))\n        FEATURES += testing-kernel\n      endif\n    endif\n    ifneq ($(CONFIG_OF),)\n      FEATURES += dt\n    endif\n    ifneq ($(CONFIG_GENERIC_GPIO)$(CONFIG_GPIOLIB),)\n      FEATURES += gpio\n    endif\n    ifneq ($(CONFIG_PCI),)\n      FEATURES += pci\n    endif\n    ifneq ($(CONFIG_PCIEPORTBUS),)\n      FEATURES += pcie\n    endif\n    ifneq ($(CONFIG_USB)$(CONFIG_USB_SUPPORT),)\n      ifneq ($(CONFIG_USB_ARCH_HAS_HCD)$(CONFIG_USB_EHCI_HCD),)\n        FEATURES += usb\n      endif\n    endif\n    ifneq ($(CONFIG_PCMCIA)$(CONFIG_PCCARD),)\n      FEATURES += pcmcia\n    endif\n    ifneq ($(CONFIG_VGA_CONSOLE)$(CONFIG_FB),)\n      FEATURES += display\n    endif\n    ifneq ($(CONFIG_RTC_CLASS),)\n      FEATURES += rtc\n    endif\n    ifneq ($(CONFIG_VIRTIO),)\n      FEATURES += virtio\n    endif\n    ifneq ($(CONFIG_CPU_MIPS32_R2),)\n      FEATURES += mips16\n    endif\n    FEATURES += $(foreach v,6 7,$(if $(CONFIG_CPU_V$(v)),arm_v$(v)))\n\n    # remove duplicates\n    FEATURES:=$(sort $(FEATURES))\n  endif\nendif\n\nCUR_SUBTARGET:=$(SUBTARGET)\nifeq ($(SUBTARGETS),)\n  CUR_SUBTARGET := default\nendif\n\ndefine BuildTargets/DumpCurrent\n  .PHONY: dumpinfo\n  dumpinfo : export DESCRIPTION=$$(Target/Description)\n  dumpinfo:\n\t@echo 'Target: $(TARGETID)'; \\\n\t echo 'Target-Board: $(BOARD)'; \\\n\t echo 'Target-Name: $(BOARDNAME)$(if $(SUBTARGETS),$(if $(SUBTARGET),))'; \\\n\t echo 'Target-Arch: $(ARCH)'; \\\n\t echo 'Target-Arch-Packages: $(if $(ARCH_PACKAGES),$(ARCH_PACKAGES),$(ARCH)$(if $(CPU_TYPE),_$(CPU_TYPE))$(if $(CPU_SUBTYPE),_$(CPU_SUBTYPE)))'; \\\n\t echo 'Target-Features: $(FEATURES)'; \\\n\t echo 'Target-Depends: $(DEPENDS)'; \\\n\t echo 'Target-Optimization: $(if $(CFLAGS),$(CFLAGS),$(DEFAULT_CFLAGS))'; \\\n\t echo 'CPU-Type: $(CPU_TYPE)$(if $(CPU_SUBTYPE),+$(CPU_SUBTYPE))'; \\\n\t echo 'Linux-Version: $(LINUX_VERSION)'; \\\n\t$(if $(LINUX_TESTING_VERSION),echo 'Linux-Testing-Version: $(LINUX_TESTING_VERSION)';) \\\n\t echo 'Linux-Release: $(LINUX_RELEASE)'; \\\n\t echo 'Linux-Kernel-Arch: $(LINUX_KARCH)'; \\\n\t$(if $(SUBTARGET),,$(if $(DEFAULT_SUBTARGET), echo 'Default-Subtarget: $(DEFAULT_SUBTARGET)'; )) \\\n\t echo 'Target-Description:'; \\\n\t echo \"$$$$DESCRIPTION\"; \\\n\t echo '@@'; \\\n\t echo 'Default-Packages: $(DEFAULT_PACKAGES) $(call extra_packages,$(DEFAULT_PACKAGES))'; \\\n\t $(DUMPINFO)\n\t$(if $(CUR_SUBTARGET),$(SUBMAKE) -r --no-print-directory -C image -s DUMP=1 SUBTARGET=$(CUR_SUBTARGET))\n\t$(if $(SUBTARGET),,@$(foreach SUBTARGET,$(SUBTARGETS),$(SUBMAKE) -s DUMP=1 SUBTARGET=$(SUBTARGET); ))\nendef\n\ninclude $(INCLUDE_DIR)/kernel.mk\nifeq ($(TARGET_BUILD),1)\n  include $(INCLUDE_DIR)/kernel-build.mk\n  BuildTarget?=$(BuildKernel)\nendif\n\nendif #__target_inc\n"
  },
  {
    "path": "include/toolchain-build.mk",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2009-2020 OpenWrt.org\n\noverride CONFIG_AUTOREBUILD=\noverride CONFIG_AUTOREMOVE=\n\nHOST_BUILD_PREFIX:=$(TOOLCHAIN_DIR)\nBUILD_DIR_HOST:=$(BUILD_DIR_TOOLCHAIN)\n\ninclude $(INCLUDE_DIR)/host-build.mk\ninclude $(INCLUDE_DIR)/hardening.mk\n\nHOST_STAMP_PREPARED=$(HOST_BUILD_DIR)/.prepared\n\ndefine FixupLibdir\n\tif [ -d $(1)/lib64 -a \\! -L $(1)/lib64 ]; then \\\n\t\tmkdir -p $(1)/lib; \\\n\t\tmv $(1)/lib64/* $(1)/lib/; \\\n\t\trm -rf $(1)/lib64; \\\n\tfi\n\tln -sf lib $(1)/lib64\nendef\n"
  },
  {
    "path": "include/toplevel.mk",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2007-2020 OpenWrt.org\n\nPREP_MK= OPENWRT_BUILD= QUIET=0\n\nexport IS_TTY=$(if $(MAKE_TERMOUT),1,0)\n\ninclude $(TOPDIR)/include/verbose.mk\n\nifeq ($(SDK),1)\n  include $(TOPDIR)/include/version.mk\nelse\n  REVISION:=$(shell $(TOPDIR)/scripts/getver.sh)\n  SOURCE_DATE_EPOCH:=$(shell $(TOPDIR)/scripts/get_source_date_epoch.sh)\nendif\n\nexport REVISION\nexport SOURCE_DATE_EPOCH\nexport GIT_CONFIG_PARAMETERS='core.autocrlf=false'\nexport GIT_ASKPASS:=/bin/true\nexport MAKE_JOBSERVER=$(filter --jobserver%,$(MAKEFLAGS))\nexport GNU_HOST_NAME:=$(shell $(TOPDIR)/scripts/config.guess)\nexport HOST_OS:=$(shell uname)\nexport HOST_ARCH:=$(shell uname -m)\n\nifeq ($(HOST_OS),Darwin)\n  ifneq ($(filter /Applications/Xcode.app/% /Library/Developer/%,$(MAKE)),)\n    $(error Please use a newer version of GNU make. The version shipped by Apple is not supported)\n  endif\nendif\n\n# prevent perforce from messing with the patch utility\nunexport P4PORT P4USER P4CONFIG P4CLIENT\n\n# prevent user defaults for quilt from interfering\nunexport QUILT_PATCHES QUILT_PATCH_OPTS\n\nunexport C_INCLUDE_PATH CROSS_COMPILE ARCH\n\n# prevent distro default LPATH from interfering\nunexport LPATH\n\n# make sure that a predefined CFLAGS variable does not disturb packages\nexport CFLAGS=\nexport LDFLAGS=\n\nempty:=\nspace:= $(empty) $(empty)\npath:=$(subst :,$(space),$(PATH))\npath:=$(filter-out .%,$(path))\npath:=$(subst $(space),:,$(path))\nexport PATH:=$(path)\n\nunexport TAR_OPTIONS\n\nifeq ($(FORCE),)\n  .config scripts/config/conf scripts/config/mconf: staging_dir/host/.prereq-build\nendif\n\nSCAN_COOKIE?=$(shell echo $$$$)\nexport SCAN_COOKIE\n\nSUBMAKE:=umask 022; $(SUBMAKE)\n\nULIMIT_FIX=_limit=`ulimit -n`; [ \"$$_limit\" = \"unlimited\" -o \"$$_limit\" -ge 1024 ] || ulimit -n 1024;\n\nprepare-mk: staging_dir/host/.prereq-build FORCE ;\n\nifdef SDK\n  IGNORE_PACKAGES = linux\nendif\n\n_ignore = $(foreach p,$(IGNORE_PACKAGES),--ignore $(p))\n\nprepare-tmpinfo: FORCE\n\t@+$(MAKE) -r -s staging_dir/host/.prereq-build $(PREP_MK)\n\tmkdir -p tmp/info\n\t$(_SINGLE)$(NO_TRACE_MAKE) -j1 -r -s -f include/scan.mk SCAN_TARGET=\"packageinfo\" SCAN_DIR=\"package\" SCAN_NAME=\"package\" SCAN_DEPTH=5 SCAN_EXTRA=\"\"\n\t$(_SINGLE)$(NO_TRACE_MAKE) -j1 -r -s -f include/scan.mk SCAN_TARGET=\"targetinfo\" SCAN_DIR=\"target/linux\" SCAN_NAME=\"target\" SCAN_DEPTH=3 SCAN_EXTRA=\"\" SCAN_MAKEOPTS=\"TARGET_BUILD=1\"\n\tfor type in package target; do \\\n\t\tf=tmp/.$${type}info; t=tmp/.config-$${type}.in; \\\n\t\t[ \"$$t\" -nt \"$$f\" ] || ./scripts/$${type}-metadata.pl $(_ignore) config \"$$f\" > \"$$t\" || { rm -f \"$$t\"; echo \"Failed to build $$t\"; false; break; }; \\\n\tdone\n\t[ tmp/.config-feeds.in -nt tmp/.packageauxvars ] || ./scripts/feeds feed_config > tmp/.config-feeds.in\n\t./scripts/package-metadata.pl mk tmp/.packageinfo > tmp/.packagedeps || { rm -f tmp/.packagedeps; false; }\n\t./scripts/package-metadata.pl pkgaux tmp/.packageinfo > tmp/.packageauxvars || { rm -f tmp/.packageauxvars; false; }\n\t./scripts/package-metadata.pl usergroup tmp/.packageinfo > tmp/.packageusergroup || { rm -f tmp/.packageusergroup; false; }\n\ttouch $(TOPDIR)/tmp/.build\n\n.config: ./scripts/config/conf $(if $(CONFIG_HAVE_DOT_CONFIG),,prepare-tmpinfo)\n\t@+if [ \\! -e .config ] || ! grep CONFIG_HAVE_DOT_CONFIG .config >/dev/null; then \\\n\t\t[ -e $(HOME)/.openwrt/defconfig ] && cp $(HOME)/.openwrt/defconfig .config; \\\n\t\t$(_SINGLE)$(NO_TRACE_MAKE) menuconfig $(PREP_MK); \\\n\tfi\n\nifeq ($(RECURSIVE_DEP_IS_ERROR),1)\n  KCONF_FLAGS=--fatalrecursive\nendif\nifneq ($(DISTRO_PKG_CONFIG),)\nscripts/config/%onf: export PATH:=$(dir $(DISTRO_PKG_CONFIG)):$(PATH)\nendif\nscripts/config/%onf: CFLAGS+= -O2\nscripts/config/%onf: FORCE\n\t@$(_SINGLE)$(SUBMAKE) $(if $(findstring s,$(OPENWRT_VERBOSE)),,-s) \\\n\t\t-C scripts/config $(notdir $@)\n\n$(eval $(call rdep,scripts/config,scripts/config/mconf))\n\nconfig: scripts/config/conf prepare-tmpinfo FORCE\n\t[ -L .config ] && export KCONFIG_OVERWRITECONFIG=1; \\\n\t\t$< $(KCONF_FLAGS) Config.in\n\nconfig-clean: FORCE\n\t$(_SINGLE)$(NO_TRACE_MAKE) -C scripts/config clean\n\ndefconfig: scripts/config/conf prepare-tmpinfo FORCE\n\ttouch .config\n\t@if [ ! -s .config -a -e $(HOME)/.openwrt/defconfig ]; then cp $(HOME)/.openwrt/defconfig .config; fi\n\t[ -L .config ] && export KCONFIG_OVERWRITECONFIG=1; \\\n\t\t$< $(KCONF_FLAGS) --defconfig=.config Config.in\n\nconfdefault-y=allyes\nconfdefault-m=allmod\nconfdefault-n=allno\nconfdefault:=$(confdefault-$(CONFDEFAULT))\n\noldconfig: scripts/config/conf prepare-tmpinfo FORCE\n\t[ -L .config ] && export KCONFIG_OVERWRITECONFIG=1; \\\n\t\t$< $(KCONF_FLAGS) --$(if $(confdefault),$(confdefault),old)config Config.in\n\nmenuconfig: scripts/config/mconf prepare-tmpinfo FORCE\n\tif [ \\! -e .config -a -e $(HOME)/.openwrt/defconfig ]; then \\\n\t\tcp $(HOME)/.openwrt/defconfig .config; \\\n\tfi\n\t[ -L .config ] && export KCONFIG_OVERWRITECONFIG=1; \\\n\t\t$< Config.in\n\nnconfig: scripts/config/nconf prepare-tmpinfo FORCE\n\tif [ \\! -e .config -a -e $(HOME)/.openwrt/defconfig ]; then \\\n\t\tcp $(HOME)/.openwrt/defconfig .config; \\\n\tfi\n\t[ -L .config ] && export KCONFIG_OVERWRITECONFIG=1; \\\n\t\t$< Config.in\n\nxconfig: scripts/config/qconf prepare-tmpinfo FORCE\n\tif [ \\! -e .config -a -e $(HOME)/.openwrt/defconfig ]; then \\\n\t\tcp $(HOME)/.openwrt/defconfig .config; \\\n\tfi\n\t$< Config.in\n\nprepare_kernel_conf: .config toolchain/install FORCE\n\nifeq ($(wildcard staging_dir/host/bin/quilt),)\n  prepare_kernel_conf:\n\t@+$(SUBMAKE) -r tools/quilt/compile\nelse\n  prepare_kernel_conf: ;\nendif\n\nkernel_oldconfig: prepare_kernel_conf\n\t$(_SINGLE)$(NO_TRACE_MAKE) -C target/linux oldconfig\n\nifneq ($(DISTRO_PKG_CONFIG),)\nkernel_menuconfig: export PATH:=$(dir $(DISTRO_PKG_CONFIG)):$(PATH)\nkernel_nconfig: export PATH:=$(dir $(DISTRO_PKG_CONFIG)):$(PATH)\nkernel_xconfig: export PATH:=$(dir $(DISTRO_PKG_CONFIG)):$(PATH)\nendif\nkernel_menuconfig: prepare_kernel_conf\n\t$(_SINGLE)$(NO_TRACE_MAKE) -C target/linux menuconfig\n\nkernel_nconfig: prepare_kernel_conf\n\t$(_SINGLE)$(NO_TRACE_MAKE) -C target/linux nconfig\n\nkernel_xconfig: prepare_kernel_conf\n\t$(_SINGLE)$(NO_TRACE_MAKE) -C target/linux xconfig\n\nstaging_dir/host/.prereq-build: include/prereq-build.mk\n\tmkdir -p tmp\n\t@$(_SINGLE)$(NO_TRACE_MAKE) -j1 -r -s -f $(TOPDIR)/include/prereq-build.mk prereq 2>/dev/null || { \\\n\t\techo \"Prerequisite check failed. Use FORCE=1 to override.\"; \\\n\t\tfalse; \\\n\t}\n  ifneq ($(realpath $(TOPDIR)/include/prepare.mk),)\n\t@$(_SINGLE)$(NO_TRACE_MAKE) -j1 -r -s -f $(TOPDIR)/include/prepare.mk prepare 2>/dev/null || { \\\n\t\techo \"Preparation failed.\"; \\\n\t\tfalse; \\\n\t}\n  endif\n\ttouch $@\n\nprintdb: FORCE\n\t@$(_SINGLE)$(NO_TRACE_MAKE) -p $@ V=99 DUMP_TARGET_DB=1 2>&1\n\nifndef SDK\n  DOWNLOAD_DIRS = tools/download toolchain/download package/download target/download\nelse\n  DOWNLOAD_DIRS = package/download\nendif\n\ndownload: .config FORCE $(if $(wildcard $(TOPDIR)/staging_dir/host/bin/flock),,tools/flock/compile)\n\t@+$(foreach dir,$(DOWNLOAD_DIRS),$(SUBMAKE) $(dir);)\n\nclean dirclean: .config\n\t@+$(SUBMAKE) -r $@\n\nprereq:: prepare-tmpinfo .config\n\t@+$(NO_TRACE_MAKE) -r -s $@\n\ncheck: .config FORCE\n\t@+$(NO_TRACE_MAKE) -r -s $@ QUIET= V=s\n\nval.%: FORCE\n\t@+$(NO_TRACE_MAKE) -r -s $@ QUIET= V=s\n\nWARN_PARALLEL_ERROR = $(if $(BUILD_LOG),,$(and $(filter -j,$(MAKEFLAGS)),$(findstring s,$(OPENWRT_VERBOSE))))\n\nifeq ($(SDK),1)\n\n%::\n\t@+$(PREP_MK) $(NO_TRACE_MAKE) -r -s prereq\n\t@./scripts/config/conf $(KCONF_FLAGS) --defconfig=.config Config.in\n\t@+$(ULIMIT_FIX) $(SUBMAKE) -r $@\n\nelse\n\n%::\n\t@+$(PREP_MK) $(NO_TRACE_MAKE) -r -s prereq\n\t@( \\\n\t\tcp .config tmp/.config; \\\n\t\t./scripts/config/conf $(KCONF_FLAGS) --defconfig=tmp/.config -w tmp/.config Config.in > /dev/null 2>&1; \\\n\t\tif ./scripts/kconfig.pl '>' .config tmp/.config | grep -q CONFIG; then \\\n\t\t\tprintf \"$(_R)WARNING: your configuration is out of sync. Please run make menuconfig, oldconfig or defconfig!$(_N)\\n\" >&2; \\\n\t\tfi \\\n\t)\n\t@+$(ULIMIT_FIX) $(SUBMAKE) -r $@ $(if $(WARN_PARALLEL_ERROR), || { \\\n\t\tprintf \"$(_R)Build failed - please re-run with -j1 to see the real error message$(_N)\\n\" >&2; \\\n\t\tfalse; \\\n\t} )\n\nendif\n\n# update all feeds, re-create index files, install symlinks\npackage/symlinks:\n\t./scripts/feeds update -a\n\t./scripts/feeds install -a\n\n# re-create index files, install symlinks\npackage/symlinks-install:\n\t./scripts/feeds update -i\n\t./scripts/feeds install -a\n\n# remove all symlinks, don't touch ./feeds\npackage/symlinks-clean:\n\t./scripts/feeds uninstall -a\n\nhelp:\n\tcat README.md\n\ndistclean:\n\trm -rf bin build_dir .ccache .config* dl feeds key-build* logs package/feeds staging_dir tmp\n\t@$(_SINGLE)$(SUBMAKE) -C scripts/config clean\n\nifeq ($(findstring v,$(DEBUG)),)\n  .SILENT: symlinkclean clean dirclean distclean config-clean download help tmpinfo-clean .config scripts/config/mconf scripts/config/conf menuconfig staging_dir/host/.prereq-build tmp/.prereq-package prepare-tmpinfo\nendif\n.PHONY: help FORCE\n.NOTPARALLEL:\n\n"
  },
  {
    "path": "include/trusted-firmware-a.mk",
    "content": "PKG_NAME ?= trusted-firmware-a\nPKG_CPE_ID ?= cpe:/a:arm:arm_trusted_firmware\n\nifndef PKG_SOURCE_PROTO\nPKG_SOURCE = trusted-firmware-a-$(PKG_VERSION).tar.gz\nPKG_SOURCE_URL:=https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/snapshot\nendif\n\nPKG_BUILD_DIR = $(BUILD_DIR)/$(PKG_NAME)-$(BUILD_VARIANT)/$(PKG_NAME)-$(PKG_VERSION)\n\nPKG_TARGETS := bin\nPKG_FLAGS:=nonshared\n\nPKG_LICENSE:=BSD-3-Clause\nPKG_LICENSE_FILES:=docs/license.rst\n\nPKG_BUILD_PARALLEL:=1\n\nexport GCC_HONOUR_COPTS=s\n\ndefine Package/trusted-firmware-a/install/default\n\t$(CP) $(patsubst %,$(PKG_BUILD_DIR)/build/$(PLAT)/release/%,$(TFA_IMAGE)) $(1)/\nendef\n\nPackage/trusted-firmware-a/install = $(Package/trusted-firmware-a/install/default)\n\ndefine Trusted-Firmware-A/Init\n  BUILD_TARGET:=\n  BUILD_SUBTARGET:=\n  BUILD_DEVICES:=\n  NAME:=\n  DEPENDS:=\n  HIDDEN:=\n  DEFAULT:=\n  PLAT:=\n  VARIANT:=$(1)\n  TFA_IMAGE:=\nendef\n\nTARGET_DEP = TARGET_$(BUILD_TARGET)$(if $(BUILD_SUBTARGET),_$(BUILD_SUBTARGET))\n\ndefine Build/Trusted-Firmware-A/Target\n  $(eval $(call Trusted-Firmware-A/Init,$(1)))\n  $(eval $(call Trusted-Firmware-A/Default,$(1)))\n  $(eval $(call Trusted-Firmware-A/$(1),$(1)))\n\n define Package/trusted-firmware-a-$(1)\n    SECTION:=boot\n    CATEGORY:=Boot Loaders\n    TITLE:=Trusted-Firmware-A for $(NAME)\n    VARIANT:=$(VARIANT)\n    DEPENDS:=@!IN_SDK $(DEPENDS)\n    HIDDEN:=$(HIDDEN)\n    ifneq ($(BUILD_TARGET),)\n      DEPENDS += @$(TARGET_DEP)\n      ifneq ($(BUILD_DEVICES),)\n        DEFAULT := y if ($(TARGET_DEP)_Default \\\n\t\t$(patsubst %,|| $(TARGET_DEP)_DEVICE_%,$(BUILD_DEVICES)) \\\n\t\t$(patsubst %,|| $(patsubst TARGET_%,TARGET_DEVICE_%,$(TARGET_DEP))_DEVICE_%,$(BUILD_DEVICES)))\n      endif\n    endif\n    $(if $(DEFAULT),DEFAULT:=$(DEFAULT))\n    URL:=https://www.trustedfirmware.org/projects/tf-a/\n  endef\n\n  define Package/trusted-firmware-a-$(1)/install\n\t$$(Package/trusted-firmware-a/install)\n  endef\nendef\n\ndefine Build/Configure/Trusted-Firmware-A\n\t$(INSTALL_DIR) $(STAGING_DIR)/usr/include\nendef\n\ndefine Build/Compile/Trusted-Firmware-A\n\t+$(MAKE) $(PKG_JOBS) -C $(PKG_BUILD_DIR) \\\n\t\tCROSS_COMPILE=$(TARGET_CROSS) \\\n\t\tOPENSSL_DIR=$(STAGING_DIR_HOST) \\\n\t\tPLAT=$(PLAT) \\\n\t\tBUILD_STRING=\"OpenWrt v$(PKG_VERSION)-$(PKG_RELEASE) ($(VARIANT))\" \\\n\t\t$(TFA_MAKE_FLAGS)\nendef\n\ndefine BuildPackage/Trusted-Firmware-A/Defaults\n  Build/Configure/Default = $$$$(Build/Configure/Trusted-Firmware-A)\n  Build/Compile/Default = $$$$(Build/Compile/Trusted-Firmware-A)\nendef\n\ndefine BuildPackage/Trusted-Firmware-A\n  $(eval $(call BuildPackage/Trusted-Firmware-A/Defaults))\n  $(foreach type,$(if $(DUMP),$(TFA_TARGETS),$(BUILD_VARIANT)), \\\n    $(eval $(call Build/Trusted-Firmware-A/Target,$(type)))\n  )\n  $(eval $(call Build/DefaultTargets))\n  $(foreach type,$(if $(DUMP),$(TFA_TARGETS),$(BUILD_VARIANT)), \\\n    $(call BuildPackage,trusted-firmware-a-$(type))\n  )\nendef\n"
  },
  {
    "path": "include/u-boot.mk",
    "content": "PKG_NAME ?= u-boot\n\nifndef PKG_SOURCE_PROTO\nPKG_SOURCE = $(PKG_NAME)-$(PKG_VERSION).tar.bz2\nPKG_SOURCE_URL = \\\n\thttps://mirror.cyberbits.eu/u-boot \\\n\thttps://ftp.denx.de/pub/u-boot \\\n\tftp://ftp.denx.de/pub/u-boot\nendif\n\nPKG_BUILD_DIR = $(BUILD_DIR)/$(PKG_NAME)-$(BUILD_VARIANT)/$(PKG_NAME)-$(PKG_VERSION)\n\nPKG_TARGETS := bin\nPKG_FLAGS:=nonshared\n\nPKG_LICENSE:=GPL-2.0 GPL-2.0+\nPKG_LICENSE_FILES:=Licenses/README\n\nPKG_BUILD_PARALLEL:=1\n\nexport GCC_HONOUR_COPTS=s\n\ndefine Package/u-boot/install/default\n\t$(CP) $(patsubst %,$(PKG_BUILD_DIR)/%,$(UBOOT_IMAGE)) $(1)/\nendef\n\nPackage/u-boot/install = $(Package/u-boot/install/default)\n\ndefine U-Boot/Init\n  BUILD_TARGET:=\n  BUILD_SUBTARGET:=\n  BUILD_DEVICES:=\n  NAME:=\n  DEPENDS:=\n  HIDDEN:=\n  DEFAULT:=\n  VARIANT:=$(1)\n  UBOOT_CONFIG:=$(1)\n  UBOOT_IMAGE:=u-boot.bin\nendef\n\nTARGET_DEP = TARGET_$(BUILD_TARGET)$(if $(BUILD_SUBTARGET),_$(BUILD_SUBTARGET))\n\nUBOOT_MAKE_FLAGS = \\\n\tHOSTCC=\"$(HOSTCC)\" \\\n\tHOSTCFLAGS=\"$(HOST_CFLAGS) $(HOST_CPPFLAGS) -std=gnu11\" \\\n\tHOSTLDFLAGS=\"$(HOST_LDFLAGS)\" \\\n\tLOCALVERSION=\"-OpenWrt-$(REVISION)\" \\\n\tSTAGING_PREFIX=\"$(STAGING_DIR_HOST)\" \\\n\tPKG_CONFIG_PATH=\"$(STAGING_DIR_HOST)/lib/pkgconfig\" \\\n\tPKG_CONFIG_LIBDIR=\"$(STAGING_DIR_HOST)/lib/pkgconfig\" \\\n\tPKG_CONFIG_EXTRAARGS=\"--static\" \\\n\t$(if $(findstring c,$(OPENWRT_VERBOSE)),V=1,V='')\n\ndefine Build/U-Boot/Target\n  $(eval $(call U-Boot/Init,$(1)))\n  $(eval $(call U-Boot/Default,$(1)))\n  $(eval $(call U-Boot/$(1),$(1)))\n\n define Package/u-boot-$(1)\n    SECTION:=boot\n    CATEGORY:=Boot Loaders\n    TITLE:=U-Boot for $(NAME)\n    VARIANT:=$(VARIANT)\n    DEPENDS:=@!IN_SDK $(DEPENDS)\n    HIDDEN:=$(HIDDEN)\n    ifneq ($(BUILD_TARGET),)\n      DEPENDS += @$(TARGET_DEP)\n      ifneq ($(BUILD_DEVICES),)\n        DEFAULT := y if ($(TARGET_DEP)_Default \\\n\t\t$(patsubst %,|| $(TARGET_DEP)_DEVICE_%,$(BUILD_DEVICES)) \\\n\t\t$(patsubst %,|| $(patsubst TARGET_%,TARGET_DEVICE_%,$(TARGET_DEP))_DEVICE_%,$(BUILD_DEVICES)))\n      endif\n    endif\n    $(if $(DEFAULT),DEFAULT:=$(DEFAULT))\n    URL:=http://www.denx.de/wiki/U-Boot\n  endef\n\n  define Package/u-boot-$(1)/install\n\t$$(Package/u-boot/install)\n  endef\nendef\n\ndefine Build/Configure/U-Boot\n\t+$(MAKE) $(PKG_JOBS) -C $(PKG_BUILD_DIR) $(UBOOT_CONFIGURE_VARS) $(UBOOT_CONFIG)_config\nendef\n\nDTC=$(wildcard $(LINUX_DIR)/scripts/dtc/dtc)\n\ndefine Build/Compile/U-Boot\n\t+$(MAKE) $(PKG_JOBS) -C $(PKG_BUILD_DIR) \\\n\t\tCROSS_COMPILE=$(TARGET_CROSS) \\\n\t\t$(if $(DTC),DTC=\"$(DTC)\") \\\n\t\t$(UBOOT_MAKE_FLAGS)\nendef\n\ndefine BuildPackage/U-Boot/Defaults\n  Build/Configure/Default = $$$$(Build/Configure/U-Boot)\n  Build/Compile/Default = $$$$(Build/Compile/U-Boot)\nendef\n\ndefine BuildPackage/U-Boot\n  $(eval $(call BuildPackage/U-Boot/Defaults))\n  $(foreach type,$(if $(DUMP),$(UBOOT_TARGETS),$(BUILD_VARIANT)), \\\n    $(eval $(call Build/U-Boot/Target,$(type)))\n  )\n  $(eval $(call Build/DefaultTargets))\n  $(foreach type,$(if $(DUMP),$(UBOOT_TARGETS),$(BUILD_VARIANT)), \\\n    $(call BuildPackage,u-boot-$(type))\n  )\nendef\n"
  },
  {
    "path": "include/uclibc++.mk",
    "content": "$(warn uclibc++.mk is deprecated. Please remove it and CXX_DEPENDS)\nCXX_DEPENDS = +libstdcpp\n"
  },
  {
    "path": "include/unpack.mk",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2006-2020 OpenWrt.org\n\nHOST_TAR:=$(TAR)\nTAR_CMD=$(HOST_TAR) -C $(1)/.. $(TAR_OPTIONS)\nUNZIP_CMD=unzip -q -d $(1)/.. $(DL_DIR)/$(PKG_SOURCE)\n\nifeq ($(PKG_SOURCE),)\n  PKG_UNPACK ?= true\nelse\n\nifeq ($(strip $(UNPACK_CMD)),)\n  ifeq ($(strip $(PKG_CAT)),)\n    # try to autodetect file type\n    EXT:=$(call ext,$(PKG_SOURCE))\n    EXT1:=$(EXT)\n\n    ifeq ($(filter gz tgz,$(EXT)),$(EXT))\n      EXT:=$(call ext,$(PKG_SOURCE:.$(EXT)=))\n      DECOMPRESS_CMD:=gzip -dc $(DL_DIR)/$(PKG_SOURCE) |\n    endif\n    ifeq ($(filter bzip2 bz2 bz tbz2 tbz,$(EXT)),$(EXT))\n      EXT:=$(call ext,$(PKG_SOURCE:.$(EXT)=))\n      DECOMPRESS_CMD:=bzcat $(DL_DIR)/$(PKG_SOURCE) |\n    endif\n    ifeq ($(filter xz txz,$(EXT)),$(EXT))\n      EXT:=$(call ext,$(PKG_SOURCE:.$(EXT)=))\n      DECOMPRESS_CMD:=xzcat $(DL_DIR)/$(PKG_SOURCE) |\n    endif\n    ifeq (zst,$(EXT))\n      EXT:=$(call ext,$(PKG_SOURCE:.$(EXT)=))\n      DECOMPRESS_CMD:=zstdcat $(DL_DIR)/$(PKG_SOURCE) |\n    endif\n    ifeq ($(filter tgz tbz tbz2 txz,$(EXT1)),$(EXT1))\n      EXT:=tar\n    endif\n    DECOMPRESS_CMD ?= cat $(DL_DIR)/$(PKG_SOURCE) |\n    ifeq ($(EXT),tar)\n      UNPACK_CMD=$(DECOMPRESS_CMD) $(TAR_CMD)\n    endif\n    ifeq ($(EXT),cpio)\n      UNPACK_CMD=$(DECOMPRESS_CMD) (cd $(1)/..; $(STAGING_DIR_HOST)/bin/cpio -i -d)\n    endif\n    ifeq ($(EXT),zip)\n      UNPACK_CMD=$(UNZIP_CMD)\n    endif\n  endif\n\n  # compatibility code for packages that set PKG_CAT\n  ifeq ($(strip $(UNPACK_CMD)),)\n    # use existing PKG_CAT\n    UNPACK_CMD=$(PKG_CAT) $(DL_DIR)/$(PKG_SOURCE) | $(TAR_CMD)\n    ifeq ($(PKG_CAT),unzip)\n      UNPACK_CMD=$(UNZIP_CMD)\n    endif\n    # replace zcat with $(ZCAT), because some system don't support it properly\n    ifeq ($(PKG_CAT),zcat)\n      UNPACK_CMD=gzip -dc $(DL_DIR)/$(PKG_SOURCE) | $(TAR_CMD)\n    endif\n  endif\nendif\n\nifdef PKG_BUILD_DIR\n  PKG_UNPACK ?= $(SH_FUNC) $(call UNPACK_CMD,$(PKG_BUILD_DIR))\nendif\nifdef HOST_BUILD_DIR\n  HOST_UNPACK ?= $(SH_FUNC) $(call UNPACK_CMD,$(HOST_BUILD_DIR))\nendif\n\nendif # PKG_SOURCE\n\n"
  },
  {
    "path": "include/verbose.mk",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2006-2020 OpenWrt.org\n\nifndef OPENWRT_VERBOSE\n  OPENWRT_VERBOSE:=\nendif\nifeq (\"$(origin V)\", \"command line\")\n  OPENWRT_VERBOSE:=$(V)\nendif\n\nifeq ($(OPENWRT_VERBOSE),1)\n  OPENWRT_VERBOSE:=w\nendif\nifeq ($(OPENWRT_VERBOSE),99)\n  OPENWRT_VERBOSE:=s\nendif\n\nifeq ($(NO_TRACE_MAKE),)\nNO_TRACE_MAKE := $(MAKE) V=s$(OPENWRT_VERBOSE)\nexport NO_TRACE_MAKE\nendif\n\nifeq ($(IS_TTY),1)\n  ifneq ($(strip $(NO_COLOR)),1)\n    _Y:=\\\\033[33m\n    _R:=\\\\033[31m\n    _N:=\\\\033[m\n  endif\nendif\n\ndefine ERROR_MESSAGE\n  printf \"$(_R)%s$(_N)\\n\" \"$(1)\" >&8\nendef\n\nifeq ($(findstring s,$(OPENWRT_VERBOSE)),)\n  define MESSAGE\n\tprintf \"$(_Y)%s$(_N)\\n\" \"$(1)\" >&8\n  endef\n\n  ifeq ($(QUIET),1)\n    ifneq ($(CURDIR),$(TOPDIR))\n      _DIR:=$(patsubst $(TOPDIR)/%,%,${CURDIR})\n    else\n      _DIR:=\n    endif\n    _NULL:=$(if $(MAKECMDGOALS),$(shell \\\n\t\t$(call MESSAGE, make[$(MAKELEVEL)]$(if $(_DIR), -C $(_DIR)) $(MAKECMDGOALS)); \\\n    ))\n    SUBMAKE=$(MAKE)\n  else\n    SILENT:=>/dev/null $(if $(findstring w,$(OPENWRT_VERBOSE)),,2>&1)\n    export QUIET:=1\n    SUBMAKE=cmd() { $(SILENT) $(MAKE) -s \"$$@\" < /dev/null || { echo \"make $$*: build failed. Please re-run make with -j1 V=s or V=sc for a higher verbosity level to see what's going on\"; false; } } 8>&1 9>&2; cmd\n  endif\n\n  .SILENT: $(MAKECMDGOALS)\nelse\n  SUBMAKE=$(MAKE) -w\n  define MESSAGE\n    printf \"%s\\n\" \"$(1)\"\n  endef\nendif\n"
  },
  {
    "path": "include/version.mk",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2012-2015 OpenWrt.org\n# Copyright (C) 2016 LEDE Project\n\n# Substituted by SDK, do not remove\n# REVISION:=x\n# SOURCE_DATE_EPOCH:=x\n\nPKG_CONFIG_DEPENDS += \\\n\tCONFIG_VERSION_HOME_URL \\\n\tCONFIG_VERSION_BUG_URL \\\n\tCONFIG_VERSION_NUMBER \\\n\tCONFIG_VERSION_CODE \\\n\tCONFIG_VERSION_REPO \\\n\tCONFIG_VERSION_DIST \\\n\tCONFIG_VERSION_MANUFACTURER \\\n\tCONFIG_VERSION_MANUFACTURER_URL \\\n\tCONFIG_VERSION_PRODUCT \\\n\tCONFIG_VERSION_SUPPORT_URL \\\n\tCONFIG_VERSION_HWREV \\\n\nsanitize = $(call tolower,$(subst _,-,$(subst $(space),-,$(1))))\n\nVERSION_NUMBER:=$(call qstrip,$(CONFIG_VERSION_NUMBER))\nVERSION_NUMBER:=$(if $(VERSION_NUMBER),$(VERSION_NUMBER),SNAPSHOT)\n\nVERSION_CODE:=$(call qstrip,$(CONFIG_VERSION_CODE))\nVERSION_CODE:=$(if $(VERSION_CODE),$(VERSION_CODE),$(REVISION))\n\nVERSION_REPO:=$(call qstrip,$(CONFIG_VERSION_REPO))\nVERSION_REPO:=$(if $(VERSION_REPO),$(VERSION_REPO),https://downloads.openwrt.org/snapshots)\n\nVERSION_DIST:=$(call qstrip,$(CONFIG_VERSION_DIST))\nVERSION_DIST:=$(if $(VERSION_DIST),$(VERSION_DIST),OpenWrt)\nVERSION_DIST_SANITIZED:=$(call sanitize,$(VERSION_DIST))\n\nVERSION_MANUFACTURER:=$(call qstrip,$(CONFIG_VERSION_MANUFACTURER))\nVERSION_MANUFACTURER:=$(if $(VERSION_MANUFACTURER),$(VERSION_MANUFACTURER),OpenWrt)\n\nVERSION_MANUFACTURER_URL:=$(call qstrip,$(CONFIG_VERSION_MANUFACTURER_URL))\nVERSION_MANUFACTURER_URL:=$(if $(VERSION_MANUFACTURER_URL),$(VERSION_MANUFACTURER_URL),https://openwrt.org/)\n\nVERSION_BUG_URL:=$(call qstrip,$(CONFIG_VERSION_BUG_URL))\nVERSION_BUG_URL:=$(if $(VERSION_BUG_URL),$(VERSION_BUG_URL),https://bugs.openwrt.org/)\n\nVERSION_HOME_URL:=$(call qstrip,$(CONFIG_VERSION_HOME_URL))\nVERSION_HOME_URL:=$(if $(VERSION_HOME_URL),$(VERSION_HOME_URL),https://openwrt.org/)\n\nVERSION_SUPPORT_URL:=$(call qstrip,$(CONFIG_VERSION_SUPPORT_URL))\nVERSION_SUPPORT_URL:=$(if $(VERSION_SUPPORT_URL),$(VERSION_SUPPORT_URL),https://forum.openwrt.org/)\n\nVERSION_PRODUCT:=$(call qstrip,$(CONFIG_VERSION_PRODUCT))\nVERSION_PRODUCT:=$(if $(VERSION_PRODUCT),$(VERSION_PRODUCT),Generic)\n\nVERSION_HWREV:=$(call qstrip,$(CONFIG_VERSION_HWREV))\nVERSION_HWREV:=$(if $(VERSION_HWREV),$(VERSION_HWREV),v0)\n\ndefine taint2sym\n$(CONFIG_$(firstword $(subst :, ,$(subst +,,$(subst -,,$(1))))))\nendef\n\ndefine taint2name\n$(lastword $(subst :, ,$(1)))\nendef\n\nVERSION_TAINT_SPECS := \\\n\t-ALL_KMODS:no-all \\\n\t-IPV6:no-ipv6 \\\n\t+USE_GLIBC:glibc \\\n\t+USE_MKLIBS:mklibs \\\n\t+BUSYBOX_CUSTOM:busybox \\\n\t+OVERRIDE_PKGS:override \\\n\nVERSION_TAINTS := $(strip $(foreach taint,$(VERSION_TAINT_SPECS), \\\n\t$(if $(findstring +,$(taint)), \\\n\t\t$(if $(call taint2sym,$(taint)),$(call taint2name,$(taint))), \\\n\t\t$(if $(call taint2sym,$(taint)),,$(call taint2name,$(taint))) \\\n\t)))\n\nPKG_CONFIG_DEPENDS += $(foreach taint,$(VERSION_TAINT_SPECS),$(call taint2sym,$(taint)))\n\n# escape commas, backslashes, squotes, and ampersands for sed\ndefine sed_escape\n$(subst &,\\&,$(subst $(comma),\\$(comma),$(subst ','\\'',$(subst \\,\\\\,$(1)))))\nendef\n#'\n\nVERSION_SED_SCRIPT:=$(SED) 's,%U,$(call sed_escape,$(VERSION_REPO)),g' \\\n\t-e 's,%V,$(call sed_escape,$(VERSION_NUMBER)),g' \\\n\t-e 's,%v,\\L$(call sed_escape,$(subst $(space),_,$(VERSION_NUMBER))),g' \\\n\t-e 's,%C,$(call sed_escape,$(VERSION_CODE)),g' \\\n\t-e 's,%c,\\L$(call sed_escape,$(subst $(space),_,$(VERSION_CODE))),g' \\\n\t-e 's,%D,$(call sed_escape,$(VERSION_DIST)),g' \\\n\t-e 's,%d,\\L$(call sed_escape,$(subst $(space),_,$(VERSION_DIST))),g' \\\n\t-e 's,%R,$(call sed_escape,$(REVISION)),g' \\\n\t-e 's,%T,$(call sed_escape,$(BOARD)),g' \\\n\t-e 's,%S,$(call sed_escape,$(BOARD)/$(if $(SUBTARGET),$(SUBTARGET),generic)),g' \\\n\t-e 's,%A,$(call sed_escape,$(ARCH_PACKAGES)),g' \\\n\t-e 's,%t,$(call sed_escape,$(VERSION_TAINTS)),g' \\\n\t-e 's,%M,$(call sed_escape,$(VERSION_MANUFACTURER)),g' \\\n\t-e 's,%m,$(call sed_escape,$(VERSION_MANUFACTURER_URL)),g' \\\n\t-e 's,%b,$(call sed_escape,$(VERSION_BUG_URL)),g' \\\n\t-e 's,%u,$(call sed_escape,$(VERSION_HOME_URL)),g' \\\n\t-e 's,%s,$(call sed_escape,$(VERSION_SUPPORT_URL)),g' \\\n\t-e 's,%P,$(call sed_escape,$(VERSION_PRODUCT)),g' \\\n\t-e 's,%h,$(call sed_escape,$(VERSION_HWREV)),g'\n\n"
  },
  {
    "path": "package/Makefile",
    "content": "#\n# Copyright (C) 2006-2010 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ncurdir:=package\n\ninclude $(INCLUDE_DIR)/feeds.mk\ninclude $(INCLUDE_DIR)/rootfs.mk\n\n-include $(TMP_DIR)/.packagedeps\npackage-y += kernel/linux\n$(curdir)/autoremove:=1\n$(curdir)/builddirs:=$(sort $(package-) $(package-y) $(package-m))\n$(curdir)/builddirs-default:=. $(sort $(package-y) $(package-m))\n$(curdir)/builddirs-prereq:=. $(sort $(prereq-y) $(prereq-m))\nifdef CHECK_ALL\n$(curdir)/builddirs-check:=$($(curdir)/builddirs)\n$(curdir)/builddirs-download:=$($(curdir)/builddirs)\nendif\nifneq ($(IGNORE_ERRORS),)\n  package-y-filter := $(package-y)\n  package-m-filter := $(filter-out $(package-y),$(package-m))\n  package-n-filter := $(filter-out $(package-y) $(package-m),$(package-))\n  package-ignore-errors := $(filter n m y,$(IGNORE_ERRORS))\n  package-ignore-errors := $(if $(package-ignore-errors),$(package-ignore-errors),n m)\n  package-ignore-subdirs := $(sort $(foreach m,$(package-ignore-errors),$(package-$(m)-filter)))\n  $(curdir)/builddirs-ignore-download := $(package-ignore-subdirs)\n  $(curdir)/builddirs-ignore-compile := $(package-ignore-subdirs)\n  $(curdir)/builddirs-ignore-host-download := $(package-ignore-subdirs)\n  $(curdir)/builddirs-ignore-host-compile := $(package-ignore-subdirs)\nendif\n\nPACKAGE_INSTALL_FILES:= \\\n\t$(foreach pkg,$(sort $(package-y)), \\\n\t\t$(foreach variant, \\\n\t\t\t$(if $(strip $(package/$(pkg)/variants)), \\\n\t\t\t\t$(package/$(pkg)/variants), \\\n\t\t\t\t$(if $(package/$(pkg)/default-variant), \\\n\t\t\t\t\t$(package/$(pkg)/default-variant), \\\n\t\t\t\t\tdefault \\\n\t\t\t\t) \\\n\t\t\t), \\\n\t\t\t$(PKG_INFO_DIR)/$(lastword $(subst /,$(space),$(pkg))).$(variant).install \\\n\t\t) \\\n\t)\n\n$(curdir)/cleanup: $(TMP_DIR)/.build\n\trm -rf $(STAGING_DIR_ROOT)\n\n$(curdir)/merge:\n\trm -rf $(PACKAGE_DIR_ALL)\n\tmkdir -p $(PACKAGE_DIR_ALL)\n\t-$(foreach pdir,$(PACKAGE_SUBDIRS),$(if $(wildcard $(pdir)/*.ipk),ln -s $(pdir)/*.ipk $(PACKAGE_DIR_ALL);))\n\n$(curdir)/merge-index: $(curdir)/merge\n\t(cd $(PACKAGE_DIR_ALL) && $(SCRIPT_DIR)/ipkg-make-index.sh . 2>&1 > Packages; )\n\nifndef SDK\n  $(curdir)/compile: $(curdir)/system/opkg/host/compile\nendif\n\n$(curdir)/install: $(TMP_DIR)/.build $(curdir)/merge $(if $(CONFIG_TARGET_PER_DEVICE_ROOTFS),$(curdir)/merge-index)\n\t- find $(STAGING_DIR_ROOT) -type d | $(XARGS) chmod 0755\n\trm -rf $(TARGET_DIR) $(TARGET_DIR_ORIG)\n\tmkdir -p $(TARGET_DIR)/tmp\n\t$(file >$(TMP_DIR)/opkg_install_list,\\\n\t  $(call opkg_package_files,\\\n\t    $(foreach pkg,$(shell cat $(PACKAGE_INSTALL_FILES) 2>/dev/null),$(pkg)$(call GetABISuffix,$(pkg)))))\n\t$(call opkg,$(TARGET_DIR)) install $$(cat $(TMP_DIR)/opkg_install_list)\n\t@for file in $(PACKAGE_INSTALL_FILES); do \\\n\t\t[ -s $$file.flags ] || continue; \\\n\t\tfor flag in `cat $$file.flags`; do \\\n\t\t\t$(call opkg,$(TARGET_DIR)) flag $$flag `cat $$file`; \\\n\t\tdone; \\\n\tdone || true\n\n\t$(CP) $(TARGET_DIR) $(TARGET_DIR_ORIG)\n\n\t$(call prepare_rootfs,$(TARGET_DIR),$(TOPDIR)/files)\n\n$(curdir)/index: FORCE\n\t@echo Generating package index...\n\t@for d in $(PACKAGE_SUBDIRS); do ( \\\n\t\tmkdir -p $$d; \\\n\t\tcd $$d || continue; \\\n\t\t$(SCRIPT_DIR)/ipkg-make-index.sh . 2>&1 > Packages.manifest; \\\n\t\tgrep -vE '^(Maintainer|LicenseFiles|Source|SourceName|Require|SourceDateEpoch)' Packages.manifest > Packages; \\\n\t\tcase \"$$(((64 + $$(stat -L -c%s Packages)) % 128))\" in 110|111) \\\n\t\t\t$(call ERROR_MESSAGE,WARNING: Applying padding in $$d/Packages to workaround usign SHA-512 bug!); \\\n\t\t\t{ echo \"\"; echo \"\"; } >> Packages;; \\\n\t\tesac; \\\n\t\tgzip -9nc Packages > Packages.gz; \\\n\t); done\nifdef CONFIG_SIGNED_PACKAGES\n\t@echo Signing package index...\n\t@for d in $(PACKAGE_SUBDIRS); do ( \\\n\t\t[ -d $$d ] && \\\n\t\t\tcd $$d || continue; \\\n\t\t$(STAGING_DIR_HOST)/bin/usign -S -m Packages -s $(BUILD_KEY); \\\n\t); done\nendif\n\n$(curdir)/flags-install:= -j1\n\n$(eval $(call stampfile,$(curdir),package,prereq,.config))\n$(eval $(call stampfile,$(curdir),package,cleanup,$(TMP_DIR)/.build))\n$(eval $(call stampfile,$(curdir),package,compile,$(TMP_DIR)/.build))\n$(eval $(call stampfile,$(curdir),package,install,$(TMP_DIR)/.build))\n$(eval $(call stampfile,$(curdir),package,check,$(TMP_DIR)/.build))\n\n$(eval $(call subdir,$(curdir)))\n"
  },
  {
    "path": "package/base-files/Makefile",
    "content": "#\n# Copyright (C) 2007-2021 OpenWrt.org\n# Copyright (C) 2010 Vertical Communications\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\ninclude $(INCLUDE_DIR)/kernel.mk\ninclude $(INCLUDE_DIR)/version.mk\ninclude $(INCLUDE_DIR)/feeds.mk\n\nPKG_NAME:=base-files\nPKG_FLAGS:=nonshared\nPKG_RELEASE:=$(COMMITCOUNT)\n\nPKG_FILE_DEPENDS:=$(PLATFORM_DIR)/ $(GENERIC_PLATFORM_DIR)/base-files/\nPKG_BUILD_DEPENDS:=usign/host ucert/host\nPKG_LICENSE:=GPL-2.0\n\n# Extend depends from version.mk\nPKG_CONFIG_DEPENDS += \\\n\tCONFIG_SIGNED_PACKAGES CONFIG_TARGET_INIT_PATH CONFIG_TARGET_PREINIT_DISABLE_FAILSAFE \\\n\tCONFIG_NAND_SUPPORT \\\n\tCONFIG_LEGACY_SDCARD_SUPPORT \\\n\tCONFIG_EMMC_SUPPORT \\\n\tCONFIG_CLEAN_IPKG \\\n\tCONFIG_PER_FEED_REPO \\\n\t$(foreach feed,$(FEEDS_AVAILABLE),CONFIG_FEED_$(feed))\n\ninclude $(INCLUDE_DIR)/package.mk\n\nifneq ($(DUMP),1)\n  STAMP_CONFIGURED:=$(strip $(STAMP_CONFIGURED))_$(shell echo $(CONFIG_TARGET_INIT_PATH) | $(MKHASH) md5)\n  TARGET:=-$(BOARD)\nendif\n\ndefine Package/base-files\n  SECTION:=base\n  CATEGORY:=Base system\n  DEPENDS:=+netifd +libc +jsonfilter +SIGNED_PACKAGES:usign +SIGNED_PACKAGES:openwrt-keyring +NAND_SUPPORT:ubi-utils +fstools +fwtool\n  TITLE:=Base filesystem for OpenWrt\n  URL:=http://openwrt.org/\n  VERSION:=$(PKG_RELEASE)-$(REVISION)\nendef\n\ndefine Package/base-files/conffiles\n/etc/config/\n/etc/config/network\n/etc/config/system\n/etc/dropbear/\n/etc/ethers\n/etc/group\n/etc/hosts\n/etc/inittab\n/etc/iproute2/rt_protos\n/etc/iproute2/rt_tables\n/etc/passwd\n/etc/profile\n/etc/profile.d\n/etc/protocols\n/etc/rc.local\n/etc/services\n/etc/shadow\n/etc/shells\n/etc/shinit\n/etc/sysctl.conf\n/etc/sysupgrade.conf\n$(call $(TARGET)/conffiles)\nendef\n\ndefine Package/base-files/description\n This package contains a base filesystem and system scripts for OpenWrt.\nendef\n\ndefine ImageConfigOptions\n\tmkdir -p $(1)/lib/preinit\n\techo 'pi_suppress_stderr=\"$(CONFIG_TARGET_PREINIT_SUPPRESS_STDERR)\"' >$(1)/lib/preinit/00_preinit.conf\n\techo 'fs_failsafe_wait_timeout=$(if $(CONFIG_TARGET_PREINIT_TIMEOUT),$(CONFIG_TARGET_PREINIT_TIMEOUT),2)' >>$(1)/lib/preinit/00_preinit.conf\n\techo 'pi_init_path=\"$(TARGET_INIT_PATH)\"' >>$(1)/lib/preinit/00_preinit.conf\n\techo 'pi_init_env=$(if $(CONFIG_TARGET_INIT_ENV),$(CONFIG_TARGET_INIT_ENV),\"\")' >>$(1)/lib/preinit/00_preinit.conf\n\techo 'pi_init_cmd=$(if $(CONFIG_TARGET_INIT_CMD),$(CONFIG_TARGET_INIT_CMD),\"/sbin/init\")' >>$(1)/lib/preinit/00_preinit.conf\n\techo 'pi_init_suppress_stderr=\"$(CONFIG_TARGET_INIT_SUPPRESS_STDERR)\"' >>$(1)/lib/preinit/00_preinit.conf\n\techo 'pi_ifname=$(if $(CONFIG_TARGET_PREINIT_IFNAME),$(CONFIG_TARGET_PREINIT_IFNAME),\"\")' >>$(1)/lib/preinit/00_preinit.conf\n\techo 'pi_ip=$(if $(CONFIG_TARGET_PREINIT_IP),$(CONFIG_TARGET_PREINIT_IP),\"192.168.1.1\")' >>$(1)/lib/preinit/00_preinit.conf\n\techo 'pi_netmask=$(if $(CONFIG_TARGET_PREINIT_NETMASK),$(CONFIG_TARGET_PREINIT_NETMASK),\"255.255.255.0\")' >>$(1)/lib/preinit/00_preinit.conf\n\techo 'pi_broadcast=$(if $(CONFIG_TARGET_PREINIT_BROADCAST),$(CONFIG_TARGET_PREINIT_BROADCAST),\"192.168.1.255\")' >>$(1)/lib/preinit/00_preinit.conf\n\techo 'pi_preinit_net_messages=\"$(CONFIG_TARGET_PREINIT_SHOW_NETMSG)\"' >>$(1)/lib/preinit/00_preinit.conf\n\techo 'pi_preinit_no_failsafe_netmsg=\"$(CONFIG_TARGET_PREINIT_SUPPRESS_FAILSAFE_NETMSG)\"' >>$(1)/lib/preinit/00_preinit.conf\n\techo 'pi_preinit_no_failsafe=\"$(CONFIG_TARGET_PREINIT_DISABLE_FAILSAFE)\"' >>$(1)/lib/preinit/00_preinit.conf\nendef\n\ndefine Build/Prepare\n\tmkdir -p $(PKG_BUILD_DIR)\nendef\n\ndefine Build/Compile/Default\n\nendef\nBuild/Compile = $(Build/Compile/Default)\n\nifdef CONFIG_SIGNED_PACKAGES\n  define Build/Configure\n\t[ -s $(BUILD_KEY) -a -s $(BUILD_KEY).pub ] || \\\n\t\t$(STAGING_DIR_HOST)/bin/usign -G -s $(BUILD_KEY) -p $(BUILD_KEY).pub -c \"Local build key\"\n\n\t[ -s $(BUILD_KEY).ucert ] || \\\n\t\t$(STAGING_DIR_HOST)/bin/ucert -I -c $(BUILD_KEY).ucert -p $(BUILD_KEY).pub -s $(BUILD_KEY)\n\n  endef\n\nifndef CONFIG_BUILDBOT\n  define Package/base-files/install-key\n\tmkdir -p $(1)/etc/opkg/keys\n\t$(CP) $(BUILD_KEY).pub $(1)/etc/opkg/keys/`$(STAGING_DIR_HOST)/bin/usign -F -p $(BUILD_KEY).pub`\n\n  endef\nendif\nendif\n\nifeq ($(CONFIG_NAND_SUPPORT),)\n  define Package/base-files/nand-support\n\trm -f $(1)/lib/upgrade/nand.sh\n  endef\nendif\n\nifeq ($(CONFIG_EMMC_SUPPORT),)\n  define Package/base-files/emmc-support\n\trm -f $(1)/lib/upgrade/emmc.sh\n  endef\nendif\n\nifeq ($(CONFIG_LEGACY_SDCARD_SUPPORT),)\n  define Package/base-files/legacy-sdcard-support\n\trm -f $(1)/lib/upgrade/legacy-sdcard.sh\n  endef\nendif\n\n\ndefine Package/base-files/install\n\t$(CP) ./files/* $(1)/\n\t$(Package/base-files/install-key)\n\t$(Package/base-files/nand-support)\n\t$(Package/base-files/legacy-sdcard-support)\n\t$(Package/base-files/emmc-support)\n\tif [ -d $(GENERIC_PLATFORM_DIR)/base-files/. ]; then \\\n\t\t$(CP) $(GENERIC_PLATFORM_DIR)/base-files/* $(1)/; \\\n\tfi\n\tif [ -d $(PLATFORM_DIR)/base-files/. ]; then \\\n\t\t$(CP) $(PLATFORM_DIR)/base-files/* $(1)/; \\\n\tfi\n\t$(if $(filter-out $(PLATFORM_DIR),$(PLATFORM_SUBDIR)), \\\n\t\tif [ -d $(PLATFORM_SUBDIR)/base-files/. ]; then \\\n\t\t\t$(CP) $(PLATFORM_SUBDIR)/base-files/* $(1)/; \\\n\t\tfi; \\\n\t)\n\n\t$(VERSION_SED_SCRIPT) \\\n\t\t$(1)/etc/banner \\\n\t\t$(1)/etc/device_info \\\n\t\t$(1)/etc/openwrt_release \\\n\t\t$(1)/etc/openwrt_version \\\n\t\t$(1)/usr/lib/os-release\n\n\n\t$(SED) \"s#%PATH%#$(TARGET_INIT_PATH)#g\" \\\n\t\t$(1)/sbin/hotplug-call \\\n\t\t$(1)/etc/preinit \\\n\t\t$(1)/etc/profile\n\n\tmkdir -p \\\n\t\t$(1)/CONTROL \\\n\t\t$(1)/dev \\\n\t\t$(1)/etc/config \\\n\t\t$(1)/etc/crontabs \\\n\t\t$(1)/etc/rc.d \\\n\t\t$(1)/overlay \\\n\t\t$(1)/lib/firmware \\\n\t\t$(1)/mnt \\\n\t\t$(1)/proc \\\n\t\t$(1)/tmp \\\n\t\t$(1)/usr/lib \\\n\t\t$(1)/usr/bin \\\n\t\t$(1)/sys \\\n\t\t$(1)/www \\\n\t\t$(1)/root\n\n\t$(LN) /proc/mounts $(1)/etc/mtab\n\t$(if $(LIB_SUFFIX),-$(LN) lib $(1)/lib$(LIB_SUFFIX))\n\t$(if $(LIB_SUFFIX),-$(LN) lib $(1)/usr/lib$(LIB_SUFFIX))\n\nifneq ($(CONFIG_TARGET_ROOTFS_PERSIST_VAR),y)\n\trm -f $(1)/var\n\t$(LN) tmp $(1)/var\nelse\n\tmkdir -p $(1)/var\n\t$(LN) /tmp/run $(1)/var/run\nendif\n\t$(LN) /tmp/resolv.conf /tmp/TZ /tmp/localtime $(1)/etc/\n\n\tchmod 0600 $(1)/etc/shadow\n\tchmod 1777 $(1)/tmp\n\n\t$(call ImageConfigOptions,$(1))\n\t$(call Package/base-files/install-target,$(1))\n\tfor conffile in $(1)/etc/config/*; do \\\n\t\tif [ -f \"$$$$conffile\" ]; then \\\n\t\t\tgrep \"$$$${conffile##$(1)}\" $(1)/CONTROL/conffiles || \\\n\t\t\t\techo \"$$$${conffile##$(1)}\" >> $(1)/CONTROL/conffiles; \\\n\t\tfi \\\n\tdone\n\n\t$(if $(CONFIG_INCLUDE_CONFIG), \\\n\t\techo -e \"# Build configuration for board $(BOARD)/$(SUBTARGET)/$(PROFILE)\\n\" >$(1)/etc/build.config; \\\n\t\tcat $(BIN_DIR)/config.buildinfo >>$(1)/etc/build.config; \\\n\t\tcat $(BIN_DIR)/feeds.buildinfo >>$(1)/etc/build.feeds; \\\n\t\tcat $(BIN_DIR)/version.buildinfo >>$(1)/etc/build.version)\n\n\t$(if $(CONFIG_CLEAN_IPKG),, \\\n\t\tmkdir -p $(1)/etc/opkg; \\\n\t\t$(call FeedSourcesAppend,$(1)/etc/opkg/distfeeds.conf); \\\n\t\t$(VERSION_SED_SCRIPT) $(1)/etc/opkg/distfeeds.conf)\n\t$(if $(CONFIG_IPK_FILES_CHECKSUMS),, \\\n\t\trm -f $(1)/sbin/pkg_check)\n\n\t$(if $(CONFIG_TARGET_PREINIT_DISABLE_FAILSAFE), \\\n\t\trm -f $(1)/etc/banner.failsafe,)\nendef\n\nifneq ($(DUMP),1)\n  -include $(PLATFORM_DIR)/base-files.mk\n  -include $(PLATFORM_SUBDIR)/base-files.mk\nendif\n\n$(eval $(call BuildPackage,base-files))\n"
  },
  {
    "path": "package/base-files/files/bin/board_detect",
    "content": "#!/bin/sh\n\nCFG=$1\n\n[ -n \"$CFG\" ] || CFG=/etc/board.json\n\n[ -d \"/etc/board.d/\" -a ! -s \"$CFG\" ] && {\n\tfor a in $(ls /etc/board.d/*); do\n\t\t[ -s $a ] || continue;\n\t\t$(. $a)\n\tdone\n}\n\n[ -s \"$CFG\" ] || return 1\n"
  },
  {
    "path": "package/base-files/files/bin/config_generate",
    "content": "#!/bin/sh\n\nCFG=/etc/board.json\n\n. /usr/share/libubox/jshn.sh\n\n[ -s $CFG ] || /bin/board_detect || exit 1\n[ -s /etc/config/network -a -s /etc/config/system ] && exit 0\n\ngenerate_bridge() {\n\tlocal name=$1\n\tlocal macaddr=$2\n\tuci -q batch <<-EOF\n\t\tset network.$name=device\n\t\tset network.$name.name=$name\n\t\tset network.$name.type=bridge\n\tEOF\n\tif [ -n \"$macaddr\" ]; then\n\t\tuci -q batch <<-EOF\n\t\t\tset network.$name.macaddr=$macaddr\n\t\tEOF\n\tfi\n}\n\nbridge_vlan_id=0\ngenerate_bridge_vlan() {\n\tlocal name=$1_vlan\n\tlocal device=$2\n\tlocal ports=\"$3\"\n\tlocal vlan=\"$4\"\n\tuci -q batch <<-EOF\n\t\tset network.$name=bridge-vlan\n\t\tset network.$name.device='$device'\n\t\tset network.$name.vlan='$vlan'\n\t\tset network.$name.ports='$ports'\n\tEOF\n}\n\ngenerate_static_network() {\n\tuci -q batch <<-EOF\n\t\tdelete network.loopback\n\t\tset network.loopback='interface'\n\t\tset network.loopback.device='lo'\n\t\tset network.loopback.proto='static'\n\t\tset network.loopback.ipaddr='127.0.0.1'\n\t\tset network.loopback.netmask='255.0.0.0'\n\tEOF\n\t\t[ -e /proc/sys/net/ipv6 ] && {\n\t\t\tuci -q batch <<-EOF\n\t\t\t\tdelete network.globals\n\t\t\t\tset network.globals='globals'\n\t\t\t\tset network.globals.ula_prefix='auto'\n\t\t\tEOF\n\t\t}\n\n\tif json_is_a dsl object; then\n\t\tjson_select dsl\n\t\t\tif json_is_a atmbridge object; then\n\t\t\t\tjson_select atmbridge\n\t\t\t\t\tlocal vpi vci encaps payload nameprefix\n\t\t\t\t\tjson_get_vars vpi vci encaps payload nameprefix\n\t\t\t\t\tuci -q batch <<-EOF\n\t\t\t\t\t\tdelete network.atm\n\t\t\t\t\t\tset network.atm='atm-bridge'\n\t\t\t\t\t\tset network.atm.vpi='$vpi'\n\t\t\t\t\t\tset network.atm.vci='$vci'\n\t\t\t\t\t\tset network.atm.encaps='$encaps'\n\t\t\t\t\t\tset network.atm.payload='$payload'\n\t\t\t\t\t\tset network.atm.nameprefix='$nameprefix'\n\t\t\t\t\tEOF\n\t\t\t\tjson_select ..\n\t\t\tfi\n\n\t\t\tif json_is_a modem object; then\n\t\t\t\tjson_select modem\n\t\t\t\t\tlocal type annex firmware tone xfer_mode\n\t\t\t\t\tjson_get_vars type annex firmware tone xfer_mode\n\t\t\t\t\tuci -q batch <<-EOF\n\t\t\t\t\t\tdelete network.dsl\n\t\t\t\t\t\tset network.dsl='dsl'\n\t\t\t\t\t\tset network.dsl.annex='$annex'\n\t\t\t\t\t\tset network.dsl.firmware='$firmware'\n\t\t\t\t\t\tset network.dsl.tone='$tone'\n\t\t\t\t\t\tset network.dsl.xfer_mode='$xfer_mode'\n\t\t\t\t\tEOF\n\t\t\t\tjson_select ..\n\t\t\tfi\n\t\tjson_select ..\n\tfi\n}\n\naddr_offset=2\ngenerate_network() {\n\tlocal ports device macaddr protocol type ipaddr netmask vlan\n\tlocal bridge=$2\n\n\tjson_select network\n\t\tjson_select \"$1\"\n\t\t\tjson_get_vars device macaddr protocol ipaddr netmask vlan\n\t\t\tjson_get_values ports ports\n\t\tjson_select ..\n\tjson_select ..\n\n\t[ -n \"$device\" -o -n \"$ports\" ] || return\n\n\t# Force bridge for \"lan\" as it may have other devices (e.g. wireless)\n\t# bridged\n\t[ \"$1\" = \"lan\" -a -z \"$ports\" ] && {\n\t\tports=\"$device\"\n\t}\n\n\t[ -n \"$ports\" -a -z \"$bridge\" ] && {\n\t\tuci -q batch <<-EOF\n\t\t\tadd network device\n\t\t\tset network.@device[-1].name='br-$1'\n\t\t\tset network.@device[-1].type='bridge'\n\t\tEOF\n\t\tfor port in $ports; do uci add_list network.@device[-1].ports=\"$port\"; done\n\t\t[ -n \"$macaddr\" ] && {\n\t\t\tfor port in $ports; do\n\t\t\t\tuci -q batch <<-EOF\n\t\t\t\t\tadd network device\n\t\t\t\t\tset network.@device[-1].name='$port'\n\t\t\t\t\tset network.@device[-1].macaddr='$macaddr'\n\t\t\t\tEOF\n\t\t\tdone\n\t\t}\n\t\tdevice=br-$1\n\t\ttype=\n\t\tmacaddr=\"\"\n\t}\n\n\t[ -n \"$bridge\" ] && {\n\t\t[ -z \"$ports\" ] && ports=\"$device\"\n\t\tif [ -z \"$vlan\" ]; then\n\t\t\tbridge_vlan_id=$((bridge_vlan_id + 1))\n\t\t\tvlan=$bridge_vlan_id\n\t\tfi\n\t\tgenerate_bridge_vlan $1 $bridge \"$ports\" $vlan\n\t\tdevice=$bridge.$vlan\n\t\ttype=\"\"\n\t}\n\n\tif [ -n \"$macaddr\" ]; then\n\t\tuci -q batch <<-EOF\n\t\t\tadd network device\n\t\t\tset network.@device[-1].name='$device'\n\t\t\tset network.@device[-1].macaddr='$macaddr'\n\t\tEOF\n\tfi\n\n\tuci -q batch <<-EOF\n\t\tdelete network.$1\n\t\tset network.$1='interface'\n\t\tset network.$1.type='$type'\n\t\tset network.$1.device='$device'\n\t\tset network.$1.proto='none'\n\tEOF\n\n\tcase \"$protocol\" in\n\t\tstatic)\n\t\t\tlocal ipad\n\t\t\tcase \"$1\" in\n\t\t\t\tlan) ipad=${ipaddr:-\"192.168.2.1\"} ;;\n\t\t\t\t*) ipad=${ipaddr:-\"192.168.$((addr_offset++)).1\"} ;;\n\t\t\tesac\n\n\t\t\tnetm=${netmask:-\"255.255.255.0\"}\n\n\t\t\tuci -q batch <<-EOF\n\t\t\t\tset network.$1.proto='static'\n\t\t\t\tset network.$1.ipaddr='$ipad'\n\t\t\t\tset network.$1.netmask='$netm'\n\t\t\tEOF\n\t\t\t[ -e /proc/sys/net/ipv6 ] && uci set network.$1.ip6assign='60'\n\t\t;;\n\n\t\tdhcp)\n\t\t\t# fixup IPv6 slave interface if parent is a bridge\n\t\t\t[ \"$type\" = \"bridge\" ] && device=\"br-$1\"\n\n\t\t\tuci set network.$1.proto='dhcp'\n\t\t\t[ -e /proc/sys/net/ipv6 ] && {\n\t\t\t\tuci -q batch <<-EOF\n\t\t\t\t\tdelete network.${1}6\n\t\t\t\t\tset network.${1}6='interface'\n\t\t\t\t\tset network.${1}6.device='$device'\n\t\t\t\t\tset network.${1}6.proto='dhcpv6'\n\t\t\t\tEOF\n\t\t\t}\n\t\t;;\n\n\t\tpppoe)\n\t\t\tuci -q batch <<-EOF\n\t\t\t\tset network.$1.proto='pppoe'\n\t\t\t\tset network.$1.username='username'\n\t\t\t\tset network.$1.password='password'\n\t\t\tEOF\n\t\t\t[ -e /proc/sys/net/ipv6 ] && {\n\t\t\t\tuci -q batch <<-EOF\n\t\t\t\t\tset network.$1.ipv6='1'\n\t\t\t\t\tdelete network.${1}6\n\t\t\t\t\tset network.${1}6='interface'\n\t\t\t\t\tset network.${1}6.device='@${1}'\n\t\t\t\t\tset network.${1}6.proto='dhcpv6'\n\t\t\t\tEOF\n\t\t\t}\n\t\t;;\n\tesac\n}\n\ngenerate_switch_vlans_ports() {\n\tlocal switch=\"$1\"\n\tlocal port ports role roles num attr val\n\n\t#\n\t# autogenerate vlans\n\t#\n\n\tif json_is_a roles array; then\n\t\tjson_get_keys roles roles\n\t\tjson_select roles\n\n\t\tfor role in $roles; do\n\t\t\tjson_select \"$role\"\n\t\t\t\tjson_get_vars ports\n\t\t\tjson_select ..\n\n\t\t\tuci -q batch <<-EOF\n\t\t\t\tadd network switch_vlan\n\t\t\t\tset network.@switch_vlan[-1].device='$switch'\n\t\t\t\tset network.@switch_vlan[-1].vlan='$role'\n\t\t\t\tset network.@switch_vlan[-1].ports='$ports'\n\t\t\tEOF\n\t\tdone\n\n\t\tjson_select ..\n\tfi\n\n\n\t#\n\t# write port specific settings\n\t#\n\n\tif json_is_a ports array; then\n\t\tjson_get_keys ports ports\n\t\tjson_select ports\n\n\t\tfor port in $ports; do\n\t\t\tjson_select \"$port\"\n\t\t\t\tjson_get_vars num\n\n\t\t\t\tif json_is_a attr object; then\n\t\t\t\t\tjson_get_keys attr attr\n\t\t\t\t\tjson_select attr\n\t\t\t\t\t\tuci -q batch <<-EOF\n\t\t\t\t\t\t\tadd network switch_port\n\t\t\t\t\t\t\tset network.@switch_port[-1].device='$switch'\n\t\t\t\t\t\t\tset network.@switch_port[-1].port=$num\n\t\t\t\t\t\tEOF\n\n\t\t\t\t\t\tfor attr in $attr; do\n\t\t\t\t\t\t\tjson_get_var val \"$attr\"\n\t\t\t\t\t\t\tuci -q set network.@switch_port[-1].$attr=\"$val\"\n\t\t\t\t\t\tdone\n\t\t\t\t\tjson_select ..\n\t\t\t\tfi\n\t\t\tjson_select ..\n\t\tdone\n\n\t\tjson_select ..\n\tfi\n}\n\ngenerate_switch() {\n\tlocal key=\"$1\"\n\tlocal vlans\n\n\tjson_select switch\n\tjson_select \"$key\"\n\tjson_get_vars enable reset blinkrate cpu_port \\\n\t\tar8xxx_mib_type ar8xxx_mib_poll_interval\n\n\tuci -q batch <<-EOF\n\t\tadd network switch\n\t\tset network.@switch[-1].name='$key'\n\t\tset network.@switch[-1].reset='$reset'\n\t\tset network.@switch[-1].enable_vlan='$enable'\n\t\tset network.@switch[-1].blinkrate='$blinkrate'\n\t\tset network.@switch[-1].ar8xxx_mib_type='$ar8xxx_mib_type'\n\t\tset network.@switch[-1].ar8xxx_mib_poll_interval='$ar8xxx_mib_poll_interval'\n\tEOF\n\n\tgenerate_switch_vlans_ports \"$1\"\n\n\tjson_select ..\n\tjson_select ..\n}\n\ngenerate_static_system() {\n\tuci -q batch <<-EOF\n\t\tdelete system.@system[0]\n\t\tadd system system\n\t\tset system.@system[-1].hostname='OpenWrt'\n\t\tset system.@system[-1].timezone='UTC'\n\t\tset system.@system[-1].ttylogin='0'\n\t\tset system.@system[-1].log_size='64'\n\t\tset system.@system[-1].urandom_seed='0'\n\n\t\tdelete system.ntp\n\t\tset system.ntp='timeserver'\n\t\tset system.ntp.enabled='1'\n\t\tset system.ntp.enable_server='0'\n\t\tadd_list system.ntp.server='0.openwrt.pool.ntp.org'\n\t\tadd_list system.ntp.server='1.openwrt.pool.ntp.org'\n\t\tadd_list system.ntp.server='2.openwrt.pool.ntp.org'\n\t\tadd_list system.ntp.server='3.openwrt.pool.ntp.org'\n\tEOF\n\n\tif json_is_a system object; then\n\t\tjson_select system\n\t\t\tlocal hostname\n\t\t\tif json_get_var hostname hostname; then\n\t\t\t\tuci -q set \"system.@system[-1].hostname=$hostname\"\n\t\t\tfi\n\n\t\t\tlocal compat_version\n\t\t\tif json_get_var compat_version compat_version; then\n\t\t\t\tuci -q set \"system.@system[-1].compat_version=$compat_version\"\n\t\t\telse\n\t\t\t\tuci -q set \"system.@system[-1].compat_version=1.0\"\n\t\t\tfi\n\n\t\t\tif json_is_a ntpserver array; then\n\t\t\t\tlocal keys key\n\t\t\t\tjson_get_keys keys ntpserver\n\t\t\t\tjson_select ntpserver\n\t\t\t\t\tuci -q delete \"system.ntp.server\"\n\n\t\t\t\t\tfor key in $keys; do\n\t\t\t\t\t\tlocal server\n\t\t\t\t\t\tif json_get_var server \"$key\"; then\n\t\t\t\t\t\t\tuci -q add_list \"system.ntp.server=$server\"\n\t\t\t\t\t\tfi\n\t\t\t\t\tdone\n\t\t\t\tjson_select ..\n\t\t\tfi\n\t\tjson_select ..\n\tfi\n}\n\ngenerate_rssimon() {\n\tlocal key=\"$1\"\n\tlocal cfg=\"rssid_$key\"\n\tlocal refresh threshold\n\n\tjson_select rssimon\n\tjson_select \"$key\"\n\tjson_get_vars refresh threshold\n\tjson_select ..\n\tjson_select ..\n\n\tuci -q batch <<-EOF\n\t\tdelete system.$cfg\n\t\tset system.$cfg='rssid'\n\t\tset system.$cfg.dev='$key'\n\t\tset system.$cfg.refresh='$refresh'\n\t\tset system.$cfg.threshold='$threshold'\n\tEOF\n}\n\ngenerate_led() {\n\tlocal key=\"$1\"\n\tlocal cfg=\"led_$key\"\n\n\tjson_select led\n\tjson_select \"$key\"\n\tjson_get_vars name sysfs type trigger default\n\n\tuci -q batch <<-EOF\n\t\tdelete system.$cfg\n\t\tset system.$cfg='led'\n\t\tset system.$cfg.name='$name'\n\t\tset system.$cfg.sysfs='$sysfs'\n\t\tset system.$cfg.trigger='$trigger'\n\t\tset system.$cfg.default='$default'\n\tEOF\n\n\tcase \"$type\" in\n\t\tgpio)\n\t\t\tlocal gpio inverted\n\t\t\tjson_get_vars gpio inverted\n\t\t\tuci -q batch <<-EOF\n\t\t\t\tset system.$cfg.trigger='gpio'\n\t\t\t\tset system.$cfg.gpio='$gpio'\n\t\t\t\tset system.$cfg.inverted='$inverted'\n\t\t\tEOF\n\t\t;;\n\n\t\tnetdev)\n\t\t\tlocal device mode\n\t\t\tjson_get_vars device mode\n\t\t\tuci -q batch <<-EOF\n\t\t\t\tset system.$cfg.trigger='netdev'\n\t\t\t\tset system.$cfg.mode='$mode'\n\t\t\t\tset system.$cfg.dev='$device'\n\t\t\tEOF\n\t\t;;\n\n\t\tusb)\n\t\t\tlocal device\n\t\t\tjson_get_vars device\n\t\t\tuci -q batch <<-EOF\n\t\t\t\tset system.$cfg.trigger='usbdev'\n\t\t\t\tset system.$cfg.interval='50'\n\t\t\t\tset system.$cfg.dev='$device'\n\t\t\tEOF\n\t\t;;\n\n\t\tusbport)\n\t\t\tlocal ports port\n\t\t\tjson_get_values ports ports\n\t\t\tuci set system.$cfg.trigger='usbport'\n\t\t\tfor port in $ports; do\n\t\t\t\tuci add_list system.$cfg.port=$port\n\t\t\tdone\n\t\t;;\n\n\t\trssi)\n\t\t\tlocal iface minq maxq offset factor\n\t\t\tjson_get_vars iface minq maxq offset factor\n\t\t\tuci -q batch <<-EOF\n\t\t\t\tset system.$cfg.trigger='rssi'\n\t\t\t\tset system.$cfg.iface='rssid_$iface'\n\t\t\t\tset system.$cfg.minq='$minq'\n\t\t\t\tset system.$cfg.maxq='$maxq'\n\t\t\t\tset system.$cfg.offset='$offset'\n\t\t\t\tset system.$cfg.factor='$factor'\n\t\t\tEOF\n\t\t;;\n\n\t\tswitch)\n\t\t\tlocal port_mask speed_mask mode\n\t\t\tjson_get_vars port_mask speed_mask mode\n\t\t\tuci -q batch <<-EOF\n\t\t\t\tset system.$cfg.port_mask='$port_mask'\n\t\t\t\tset system.$cfg.speed_mask='$speed_mask'\n\t\t\t\tset system.$cfg.mode='$mode'\n\t\t\tEOF\n\t\t;;\n\n\t\tportstate)\n\t\t\tlocal port_state\n\t\t\tjson_get_vars port_state\n\t\t\tuci -q batch <<-EOF\n\t\t\t\tset system.$cfg.port_state='$port_state'\n\t\t\tEOF\n\t\t;;\n\n\t\ttimer|oneshot)\n\t\t\tlocal delayon delayoff\n\t\t\tjson_get_vars delayon delayoff\n\t\t\tuci -q batch <<-EOF\n\t\t\t\tset system.$cfg.trigger='$type'\n\t\t\t\tset system.$cfg.delayon='$delayon'\n\t\t\t\tset system.$cfg.delayoff='$delayoff'\n\t\t\tEOF\n\t\t;;\n\tesac\n\n\tjson_select ..\n\tjson_select ..\n}\n\ngenerate_gpioswitch() {\n\tlocal cfg=\"$1\"\n\n\tjson_select gpioswitch\n\t\tjson_select \"$cfg\"\n\t\t\tlocal name pin default\n\t\t\tjson_get_vars name pin default\n\t\t\tuci -q batch <<-EOF\n\t\t\t\tdelete system.$cfg\n\t\t\t\tset system.$cfg='gpio_switch'\n\t\t\t\tset system.$cfg.name='$name'\n\t\t\t\tset system.$cfg.gpio_pin='$pin'\n\t\t\t\tset system.$cfg.value='$default'\n\t\t\tEOF\n\t\tjson_select ..\n\tjson_select ..\n}\n\njson_init\njson_load \"$(cat ${CFG})\"\n\numask 077\n\nif [ ! -s /etc/config/network ]; then\n\tbridge_name=\"\"\n\ttouch /etc/config/network\n\tgenerate_static_network\n\n\tjson_get_vars bridge\n\t[ -n \"$bridge\" ] && {\n\t\tjson_select bridge\n\t\tjson_get_vars name macaddr\n\t\tgenerate_bridge \"$name\" \"$macaddr\"\n\t\tjson_select ..\n\t\tbridge_name=$name\n\t}\n\n\tjson_get_keys keys network\n\tfor key in $keys; do generate_network $key $bridge_name; done\n\n\tjson_get_keys keys switch\n\tfor key in $keys; do generate_switch $key; done\nfi\n\nif [ ! -s /etc/config/system ]; then\n\ttouch /etc/config/system\n\tgenerate_static_system\n\n\tjson_get_keys keys rssimon\n\tfor key in $keys; do generate_rssimon $key; done\n\n\tjson_get_keys keys gpioswitch\n\tfor key in $keys; do generate_gpioswitch $key; done\n\n\tjson_get_keys keys led\n\tfor key in $keys; do generate_led $key; done\nfi\nuci commit\n"
  },
  {
    "path": "package/base-files/files/bin/ipcalc.sh",
    "content": "#!/bin/sh\n\nawk -f - $* <<EOF\nfunction bitcount(c) {\n\tc=and(rshift(c, 1),0x55555555)+and(c,0x55555555)\n\tc=and(rshift(c, 2),0x33333333)+and(c,0x33333333)\n\tc=and(rshift(c, 4),0x0f0f0f0f)+and(c,0x0f0f0f0f)\n\tc=and(rshift(c, 8),0x00ff00ff)+and(c,0x00ff00ff)\n\tc=and(rshift(c,16),0x0000ffff)+and(c,0x0000ffff)\n\treturn c\n}\n\nfunction ip2int(ip) {\n\tfor (ret=0,n=split(ip,a,\"\\.\"),x=1;x<=n;x++) ret=or(lshift(ret,8),a[x])\n\treturn ret\n}\n\nfunction int2ip(ip,ret,x) {\n\tret=and(ip,255)\n\tip=rshift(ip,8)\n\tfor(;x<3;ret=and(ip,255)\".\"ret,ip=rshift(ip,8),x++);\n\treturn ret\n}\n\nfunction compl32(v) {\n\tret=xor(v, 0xffffffff)\n\treturn ret\n}\n\nBEGIN {\n\tslpos=index(ARGV[1],\"/\")\n\tif (slpos == 0) {\n\t\tipaddr=ip2int(ARGV[1])\n\t\tdotpos=index(ARGV[2],\".\")\n\t\tif (dotpos == 0)\n\t\t\tnetmask=compl32(2**(32-int(ARGV[2]))-1)\n\t\telse\n\t\t\tnetmask=ip2int(ARGV[2])\n\t} else {\n\t\tipaddr=ip2int(substr(ARGV[1],0,slpos-1))\n\t\tnetmask=compl32(2**(32-int(substr(ARGV[1],slpos+1)))-1)\n\t\tARGV[4]=ARGV[3]\n\t\tARGV[3]=ARGV[2]\n\t}\n\n\tnetwork=and(ipaddr,netmask)\n\tbroadcast=or(network,compl32(netmask))\n\n\tstart=or(network,and(ip2int(ARGV[3]),compl32(netmask)))\n\tlimit=network+1\n\tif (start<limit) start=limit\n\n\tend=start+ARGV[4]\n\tlimit=or(network,compl32(netmask))-1\n\tif (end>limit) end=limit\n\n\tprint \"IP=\"int2ip(ipaddr)\n\tprint \"NETMASK=\"int2ip(netmask)\n\tprint \"BROADCAST=\"int2ip(broadcast)\n\tprint \"NETWORK=\"int2ip(network)\n\tprint \"PREFIX=\"32-bitcount(compl32(netmask))\n\n\t# range calculations:\n\t# ipcalc <ip> <netmask> <start> <num>\n\n\tif (ARGC > 3) {\n\t\tprint \"START=\"int2ip(start)\n\t\tprint \"END=\"int2ip(end)\n\t}\n}\nEOF\n"
  },
  {
    "path": "package/base-files/files/etc/banner",
    "content": "  _______                     ________        __\n |       |.-----.-----.-----.|  |  |  |.----.|  |_\n |   -   ||  _  |  -__|     ||  |  |  ||   _||   _|\n |_______||   __|_____|__|__||________||__|  |____|\n          |__| W I R E L E S S   F R E E D O M\n -----------------------------------------------------\n %D %V, %C\n -----------------------------------------------------\n"
  },
  {
    "path": "package/base-files/files/etc/banner.failsafe",
    "content": "================= FAILSAFE MODE active ================\nspecial commands:\n* firstboot\t     reset settings to factory defaults\n* mount_root\t mount root-partition with config files\n\nafter mount_root:\n* passwd\t\t\t change root's password\n* /etc/config\t\t    directory with config files\n\nfor more help see:\nhttps://openwrt.org/docs/guide-user/troubleshooting/\n- failsafe_and_factory_reset\n- root_password_reset\n=======================================================\n\n"
  },
  {
    "path": "package/base-files/files/etc/board.d/99-default_network",
    "content": "#\n# Copyright (C) 2013-2015 OpenWrt.org\n#\n\n. /lib/functions/uci-defaults.sh\n\nboard_config_update\n\njson_is_a network object && exit 0\n\nucidef_set_interface_lan 'eth0'\n[ -d /sys/class/net/eth1 ] && ucidef_set_interface_wan 'eth1'\n\nboard_config_flush\n\nexit 0\n"
  },
  {
    "path": "package/base-files/files/etc/device_info",
    "content": "DEVICE_MANUFACTURER='%M'\nDEVICE_MANUFACTURER_URL='%m'\nDEVICE_PRODUCT='%P'\nDEVICE_REVISION='%h'\n"
  },
  {
    "path": "package/base-files/files/etc/diag.sh",
    "content": "#!/bin/sh\n# Copyright (C) 2006-2019 OpenWrt.org\n\n. /lib/functions/leds.sh\n\nboot=\"$(get_dt_led boot)\"\nfailsafe=\"$(get_dt_led failsafe)\"\nrunning=\"$(get_dt_led running)\"\nupgrade=\"$(get_dt_led upgrade)\"\n\nset_led_state() {\n\tstatus_led=\"$boot\"\n\n\tcase \"$1\" in\n\tpreinit)\n\t\tstatus_led_blink_preinit\n\t\t;;\n\tfailsafe)\n\t\tstatus_led_off\n\t\t[ -n \"$running\" ] && {\n\t\t\tstatus_led=\"$running\"\n\t\t\tstatus_led_off\n\t\t}\n\t\tstatus_led=\"$failsafe\"\n\t\tstatus_led_blink_failsafe\n\t\t;;\n\tpreinit_regular)\n\t\tstatus_led_blink_preinit_regular\n\t\t;;\n\tupgrade)\n\t\t[ -n \"$running\" ] && {\n\t\t\tstatus_led=\"$running\"\n\t\t\tstatus_led_off\n\t\t}\n\t\tstatus_led=\"$upgrade\"\n\t\tstatus_led_blink_preinit_regular\n\t\t;;\n\tdone)\n\t\tstatus_led_off\n\t\t[ \"$status_led\" != \"$running\" ] && \\\n\t\t\tstatus_led_restore_trigger \"boot\"\n\t\t[ -n \"$running\" ] && {\n\t\t\tstatus_led=\"$running\"\n\t\t\tstatus_led_on\n\t\t}\n\t\t;;\n\tesac\n}\n\nset_state() {\n\t[ -n \"$boot\" -o -n \"$failsafe\" -o -n \"$running\" -o -n \"$upgrade\" ] && set_led_state \"$1\"\n}\n"
  },
  {
    "path": "package/base-files/files/etc/ethers",
    "content": "#\n#  Lookup man 5 ethers for syntax documentation\n#\n#  Examples :\n#\t02:00:11:22:33:44\tOpenWrt.lan\n#\t02:00:11:22:33:44\t192.168.1.1\n"
  },
  {
    "path": "package/base-files/files/etc/fstab",
    "content": "# <file system> <mount point> <type> <options> <dump> <pass>\n"
  },
  {
    "path": "package/base-files/files/etc/group",
    "content": "root:x:0:\ndaemon:x:1:\nadm:x:4:\nmail:x:8:\ndialout:x:20:\naudio:x:29:\nwww-data:x:33:\nftp:x:55:\nusers:x:100:\nnetwork:x:101:\nnogroup:x:65534:\n"
  },
  {
    "path": "package/base-files/files/etc/hosts",
    "content": "127.0.0.1 localhost\n\n::1     localhost ip6-localhost ip6-loopback\nff02::1 ip6-allnodes\nff02::2 ip6-allrouters\n"
  },
  {
    "path": "package/base-files/files/etc/hotplug.d/net/00-sysctl",
    "content": "#!/bin/sh\n\nif [ \"$ACTION\" = add ]; then\n\tfor CONF in /etc/sysctl.d/*.conf /etc/sysctl.conf; do\n\t\t[ ! -f \"$CONF\" ] && continue;\n\t\tsed -ne \"/^[[:space:]]*net\\..*\\.$DEVICENAME\\./p\" \"$CONF\" | \\\n\t\t\tsysctl -e -p - | logger -t sysctl\n\tdone\nfi\n"
  },
  {
    "path": "package/base-files/files/etc/init.d/boot",
    "content": "#!/bin/sh /etc/rc.common\n# Copyright (C) 2006-2011 OpenWrt.org\n\nSTART=10\nSTOP=90\n\nuci_apply_defaults() {\n\t. /lib/functions/system.sh\n\n\tcd /etc/uci-defaults || return 0\n\tfiles=\"$(ls)\"\n\t[ -z \"$files\" ] && return 0\n\tmkdir -p /tmp/.uci\n\tfor file in $files; do\n\t\t( . \"./$(basename $file)\" ) && rm -f \"$file\"\n\tdone\n\tuci commit\n}\n\nboot() {\n\t[ -f /proc/mounts ] || /sbin/mount_root\n\t[ -f /proc/jffs2_bbc ] && echo \"S\" > /proc/jffs2_bbc\n\n\tmkdir -p /var/lock\n\tchmod 1777 /var/lock\n\tmkdir -p /var/log\n\tmkdir -p /var/run\n\tmkdir -p /var/state\n\tmkdir -p /var/tmp\n\tmkdir -p /tmp/.uci\n\tchmod 0700 /tmp/.uci\n\ttouch /var/log/wtmp\n\ttouch /var/log/lastlog\n\tmkdir -p /tmp/resolv.conf.d\n\ttouch /tmp/resolv.conf.d/resolv.conf.auto\n\tln -sf /tmp/resolv.conf.d/resolv.conf.auto /tmp/resolv.conf\n\tgrep -q debugfs /proc/filesystems && /bin/mount -o noatime -t debugfs debugfs /sys/kernel/debug\n\tgrep -q bpf /proc/filesystems && /bin/mount -o nosuid,nodev,noexec,noatime,mode=0700 -t bpf bpffs /sys/fs/bpf\n\tgrep -q pstore /proc/filesystems && /bin/mount -o noatime -t pstore pstore /sys/fs/pstore\n\t[ \"$FAILSAFE\" = \"true\" ] && touch /tmp/.failsafe\n\n\t/sbin/kmodloader\n\n\t[ ! -f /etc/config/wireless ] && {\n\t\t# compat for bcm47xx and mvebu\n\t\tsleep 1\n\t}\n\n\t/bin/config_generate\n\tuci_apply_defaults\n\tsync\n\t\n\t# temporary hack until configd exists\n\t/sbin/reload_config\n}\n"
  },
  {
    "path": "package/base-files/files/etc/init.d/done",
    "content": "#!/bin/sh /etc/rc.common\n# Copyright (C) 2006 OpenWrt.org\n\nSTART=95\nboot() {\n\tmount_root done\n\trm -f /sysupgrade.tgz && sync\n\n\t# process user commands\n\t[ -f /etc/rc.local ] && {\n\t\tsh /etc/rc.local\n\t}\n\n\t# set leds to normal state\n\t. /etc/diag.sh\n\tset_state done\n}\n"
  },
  {
    "path": "package/base-files/files/etc/init.d/gpio_switch",
    "content": "#!/bin/sh /etc/rc.common\n# Copyright (C) 2015 OpenWrt.org\n\nSTART=94\nSTOP=10\nUSE_PROCD=1\n\n\nload_gpio_switch()\n{\n\tlocal name\n\tlocal gpio_pin\n\tlocal value\n\n\tconfig_get gpio_pin \"$1\" gpio_pin\n\tconfig_get name \"$1\" name\n\tconfig_get value \"$1\" value 0\n\n\t[ -z \"$gpio_pin\" ] && {\n\t\techo >&2 \"Skipping gpio_switch '$name' due to missing gpio_pin\"\n\t\treturn 1\n\t}\n\n\tlocal gpio_path\n\tif [ -n \"$(echo \"$gpio_pin\" | grep -E \"^[0-9]+$\")\" ]; then\n\t\tgpio_path=\"/sys/class/gpio/gpio${gpio_pin}\"\n\n\t\t# export GPIO pin for access\n\t\t[ -d \"$gpio_path\" ] || {\n\t\t\techo \"$gpio_pin\" >/sys/class/gpio/export\n\t\t\t# we need to wait a bit until the GPIO appears\n\t\t\t[ -d \"$gpio_path\" ] || sleep 1\n\t\t}\n\n\t\t# direction attribute only exists if the kernel supports changing the\n\t\t# direction of a GPIO\n\t\tif [ -e \"${gpio_path}/direction\" ]; then\n\t\t\t# set the pin to output with high or low pin value\n\t\t\t{ [ \"$value\" = \"0\" ] && echo \"low\" || echo \"high\"; } \\\n\t\t\t\t>\"$gpio_path/direction\"\n\t\telse\n\t\t\t{ [ \"$value\" = \"0\" ] && echo \"0\" || echo \"1\"; } \\\n\t\t\t\t>\"$gpio_path/value\"\n\t\tfi\n\telse\n\t\tgpio_path=\"/sys/class/gpio/${gpio_pin}\"\n\n\t\t[ -d \"$gpio_path\" ] && {\n\t\t\t{ [ \"$value\" = \"0\" ] && echo \"0\" || echo \"1\"; } \\\n\t\t\t\t>\"$gpio_path/value\"\n\t\t}\n\tfi\n}\n\nservice_triggers()\n{\n\tprocd_add_reload_trigger \"system\"\n}\n\nstart_service()\n{\n\t[ -e /sys/class/gpio/ ] && {\n\t\tconfig_load system\n\t\tconfig_foreach load_gpio_switch gpio_switch\n\t}\n}\n"
  },
  {
    "path": "package/base-files/files/etc/init.d/led",
    "content": "#!/bin/sh /etc/rc.common\n# Copyright (C) 2008 OpenWrt.org\n\nSTART=96\n\nload_led() {\n\tlocal name\n\tlocal sysfs\n\tlocal trigger\n\tlocal dev\n\tlocal ports\n\tlocal mode\n\tlocal default\n\tlocal delayon\n\tlocal delayoff\n\tlocal interval\n\n\tconfig_get sysfs $1 sysfs\n\tconfig_get name $1 name \"$sysfs\"\n\tconfig_get trigger $1 trigger \"none\"\n\tconfig_get dev $1 dev\n\tconfig_get ports $1 port\n\tconfig_get mode $1 mode\n\tconfig_get_bool default $1 default \"0\"\n\tconfig_get delayon $1 delayon\n\tconfig_get delayoff $1 delayoff\n\tconfig_get interval $1 interval \"50\"\n\tconfig_get port_state $1 port_state\n\tconfig_get delay $1 delay \"150\"\n\tconfig_get message $1 message \"\"\n\tconfig_get gpio $1 gpio \"0\"\n\tconfig_get inverted $1 inverted \"0\"\n\n\t# execute application led trigger\n\t[ -f \"/usr/libexec/led-trigger/${trigger}\" ] && {\n\t\t. \"/usr/libexec/led-trigger/${trigger}\"\n\t\treturn 0\n\t}\n\n\t[ \"$trigger\" = \"usbdev\" ] && {\n\t\t# Backward compatibility: translate to the new trigger\n\t\ttrigger=\"usbport\"\n\t\t# Translate port of root hub, e.g. 4-1 -> usb4-port1\n\t\tports=$(echo \"$dev\" | sed -n 's/^\\([0-9]*\\)-\\([0-9]*\\)$/usb\\1-port\\2/p')\n\t\t# Translate port of extra hub, e.g. 2-2.4 -> 2-2-port4\n\t\t[ -z \"$ports\" ] && ports=$(echo \"$dev\" | sed -n 's/\\./-port/p')\n\t}\n\n\t[ -e /sys/class/leds/${sysfs}/brightness ] && {\n\t\techo \"setting up led ${name}\"\n\n\t\tprintf \"%s %s %d\\n\" \\\n\t\t\t\"$sysfs\" \\\n\t\t\t\"$(sed -ne 's/^.*\\[\\(.*\\)\\].*$/\\1/p' /sys/class/leds/${sysfs}/trigger)\" \\\n\t\t\t\"$(cat /sys/class/leds/${sysfs}/brightness)\" \\\n\t\t\t\t>> /var/run/led.state\n\n\t\t[ \"$default\" = 0 ] &&\n\t\t\techo 0 >/sys/class/leds/${sysfs}/brightness\n\n\t\techo $trigger > /sys/class/leds/${sysfs}/trigger 2> /dev/null\n\t\tret=\"$?\"\n\n\t\t[ $default = 1 ] &&\n\t\t\tcat /sys/class/leds/${sysfs}/max_brightness > /sys/class/leds/${sysfs}/brightness\n\n\t\t[ $ret = 0 ] || {\n\t\t\techo >&2 \"Skipping trigger '$trigger' for led '$name' due to missing kernel module\"\n\t\t\treturn 1\n\t\t}\n\t\tcase \"$trigger\" in\n\t\t\"netdev\")\n\t\t\t[ -n \"$dev\" ] && {\n\t\t\t\techo $dev > /sys/class/leds/${sysfs}/device_name\n\t\t\t\tfor m in $mode; do\n\t\t\t\t\t[ -e \"/sys/class/leds/${sysfs}/$m\" ] && \\\n\t\t\t\t\t\techo 1 > /sys/class/leds/${sysfs}/$m\n\t\t\t\tdone\n\t\t\t\techo $interval > /sys/class/leds/${sysfs}/interval\n\t\t\t}\n\t\t\t;;\n\n\t\t\"timer\"|\"oneshot\")\n\t\t\t[ -n \"$delayon\" ] && \\\n\t\t\t\techo $delayon > /sys/class/leds/${sysfs}/delay_on\n\t\t\t[ -n \"$delayoff\" ] && \\\n\t\t\t\techo $delayoff > /sys/class/leds/${sysfs}/delay_off\n\t\t\t;;\n\n\t\t\"usbport\")\n\t\t\tlocal p\n\n\t\t\tfor p in $ports; do\n\t\t\t\techo 1 > /sys/class/leds/${sysfs}/ports/$p\n\t\t\tdone\n\t\t\t;;\n\n\t\t\"port_state\")\n\t\t\t[ -n \"$port_state\" ] && \\\n\t\t\t\techo $port_state > /sys/class/leds/${sysfs}/port_state\n\t\t\t;;\n\n\t\t\"gpio\")\n\t\t\techo $gpio > /sys/class/leds/${sysfs}/gpio\n\t\t\techo $inverted > /sys/class/leds/${sysfs}/inverted\n\t\t\t;;\n\n\t\tswitch[0-9]*)\n\t\t\tlocal port_mask speed_mask\n\n\t\t\tconfig_get port_mask $1 port_mask\n\t\t\t[ -n \"$port_mask\" ] && \\\n\t\t\t\techo $port_mask > /sys/class/leds/${sysfs}/port_mask\n\t\t\tconfig_get speed_mask $1 speed_mask\n\t\t\t[ -n \"$speed_mask\" ] && \\\n\t\t\t\techo $speed_mask > /sys/class/leds/${sysfs}/speed_mask\n\t\t\t[ -n \"$mode\" ] && \\\n\t\t\t\techo \"$mode\" > /sys/class/leds/${sysfs}/mode\n\t\t\t;;\n\t\tesac\n\t}\n}\n\nstart() {\n\t[ -e /sys/class/leds/ ] && {\n\t\t[ -s /var/run/led.state ] && {\n\t\t\tlocal led trigger brightness\n\t\t\twhile read led trigger brightness; do\n\t\t\t\t[ -e \"/sys/class/leds/$led/trigger\" ] && \\\n\t\t\t\t\techo \"$trigger\" > \"/sys/class/leds/$led/trigger\"\n\n\t\t\t\t[ -e \"/sys/class/leds/$led/brightness\" ] && \\\n\t\t\t\t\techo \"$brightness\" > \"/sys/class/leds/$led/brightness\"\n\t\t\tdone < /var/run/led.state\n\t\t\trm /var/run/led.state\n\t\t}\n\n\t\tconfig_load system\n\t\tconfig_foreach load_led led\n\t}\n}\n"
  },
  {
    "path": "package/base-files/files/etc/init.d/sysctl",
    "content": "#!/bin/sh /etc/rc.common\n# Copyright (C) 2006 OpenWrt.org\n\nSTART=11\n\napply_defaults() {\n\tlocal mem=\"$(awk '/^MemTotal:/ {print $2}' /proc/meminfo)\"\n\tlocal min_free frag_low_thresh frag_high_thresh\n\n\tif [ \"$mem\" -gt 65536 ]; then # 128M\n\t\tmin_free=16384\n\telif [ \"$mem\" -gt 32768 ]; then # 64M\n\t\tmin_free=8192\n\telse\n\t\tmin_free=1024\n\t\tfrag_low_thresh=393216\n\t\tfrag_high_thresh=524288\n\tfi\n\n\tsysctl -qw vm.min_free_kbytes=\"$min_free\"\n\n\t[ \"$frag_low_thresh\" ] && sysctl -qw \\\n\t\tnet.ipv4.ipfrag_low_thresh=\"$frag_low_thresh\" \\\n\t\tnet.ipv4.ipfrag_high_thresh=\"$frag_high_thresh\" \\\n\t\tnet.ipv6.ip6frag_low_thresh=\"$frag_low_thresh\" \\\n\t\tnet.ipv6.ip6frag_high_thresh=\"$frag_high_thresh\" \\\n\t\tnet.netfilter.nf_conntrack_frag6_low_thresh=\"$frag_low_thresh\" \\\n\t\tnet.netfilter.nf_conntrack_frag6_high_thresh=\"$frag_high_thresh\"\n\n\t# first set default, then all interfaces to avoid races with appearing interfaces\n\tif [ -d /proc/sys/net/ipv6/conf ]; then\n\t\techo 0 > /proc/sys/net/ipv6/conf/default/accept_ra\n\t\tfor iface in /proc/sys/net/ipv6/conf/*/accept_ra; do\n\t\t\techo 0 > \"$iface\"\n\t\tdone\n\tfi\n}\n\nstart() {\n\tapply_defaults\n\tfor CONF in /etc/sysctl.d/*.conf /etc/sysctl.conf; do\n\t\t[ -f \"$CONF\" ] && sysctl -e -p \"$CONF\" >&-\n\tdone\n}\n"
  },
  {
    "path": "package/base-files/files/etc/init.d/sysfixtime",
    "content": "#!/bin/sh /etc/rc.common\n# Copyright (C) 2013-2014 OpenWrt.org\n\nSTART=00\nSTOP=90\n\nRTC_DEV=/dev/rtc0\nHWCLOCK=/sbin/hwclock\n\nboot() {\n\tstart && exit 0\n\n\tlocal maxtime=\"$(maxtime)\"\n\tlocal curtime=\"$(date +%s)\"\n\t[ $curtime -lt $maxtime ] && date -s @$maxtime\n}\n\nstart() {\n\t[ -e \"$RTC_DEV\" ] && [ -e \"$HWCLOCK\" ] && $HWCLOCK -s -u -f $RTC_DEV\n}\n\nstop() {\n\t[ -e \"$RTC_DEV\" ] && [ -e \"$HWCLOCK\" ] && $HWCLOCK -w -u -f $RTC_DEV && \\\n\t\tlogger -t sysfixtime \"saved '$(date)' to $RTC_DEV\"\n}\n\nmaxtime() {\n\tlocal file newest\n\n\tfor file in $( find /etc -type f ) ; do\n\t\t[ -z \"$newest\" -o \"$newest\" -ot \"$file\" ] && newest=$file\n\tdone\n\t[ \"$newest\" ] && date -r \"$newest\" +%s\n}\n"
  },
  {
    "path": "package/base-files/files/etc/init.d/system",
    "content": "#!/bin/sh /etc/rc.common\n# Copyright (C) 2014 OpenWrt.org\n\nSTART=10\nUSE_PROCD=1\n\nvalidate_system_section() {\n\tuci_load_validate system system \"$1\" \"$2\" \\\n\t\t'hostname:string:OpenWrt' \\\n\t\t'conloglevel:uinteger' \\\n\t\t'buffersize:uinteger' \\\n\t\t'timezone:string:UTC' \\\n\t\t'zonename:string'\n}\n\nsystem_config() {\n\t[ \"$2\" = 0 ] || {\n\t\techo \"validation failed\"\n\t\treturn 1\n\t}\n\n\techo \"$hostname\" > /proc/sys/kernel/hostname\n\t[ -z \"$conloglevel\" -a -z \"$buffersize\" ] || dmesg ${conloglevel:+-n $conloglevel} ${buffersize:+-s $buffersize}\n\techo \"$timezone\" > /tmp/TZ\n\t[ -n \"$zonename\" ] && [ -f \"/usr/share/zoneinfo/${zonename// /_}\" ] \\\n\t\t&& ln -sf \"/usr/share/zoneinfo/${zonename// /_}\" /tmp/localtime \\\n\t\t&& rm -f /tmp/TZ\n\n\t# apply timezone to kernel\n\thwclock -u --systz\n}\n\nreload_service() {\n\tconfig_load system\n\tconfig_foreach validate_system_section system system_config\n}\n\nservice_triggers() {\n\tprocd_add_reload_trigger \"system\"\n\tprocd_add_validation validate_system_section\n}\n\nstart_service() {\n\treload_service\n}\n"
  },
  {
    "path": "package/base-files/files/etc/init.d/umount",
    "content": "#!/bin/sh /etc/rc.common\n# Copyright (C) 2006 OpenWrt.org\n\nSTOP=90\n\nrestart() {\n\t:\n}\n\nstop() {\n\tsync\n\t/bin/umount -a -d -r\n}\n"
  },
  {
    "path": "package/base-files/files/etc/inittab",
    "content": "::sysinit:/etc/init.d/rcS S boot\n::shutdown:/etc/init.d/rcS K shutdown\n::askconsole:/usr/libexec/login.sh\n"
  },
  {
    "path": "package/base-files/files/etc/iproute2/ematch_map",
    "content": "# lookup table for ematch kinds\n1\tcmp\n2\tnbyte\n3\tu32\n4\tmeta\n7\tcanid\n8\tipset\n9\tipt\n"
  },
  {
    "path": "package/base-files/files/etc/iproute2/rt_protos",
    "content": "#\n# Reserved protocols.\n#\n0\tunspec\n1\tredirect\n2\tkernel\n3\tboot\n4\tstatic\n8\tgated\n9\tra\n10\tmrt\n11\tzebra\n12\tbird\n13\tdnrouted\n14\txorp\n15\tntk\n16\tdhcp\n42\tbabel\n"
  },
  {
    "path": "package/base-files/files/etc/iproute2/rt_tables",
    "content": "#\n# reserved values\n#\n128\tprelocal\n255\tlocal\n254\tmain\n253\tdefault\n0\tunspec\n#\n# local\n#\n#1\tinr.ruhep\n"
  },
  {
    "path": "package/base-files/files/etc/openwrt_release",
    "content": "DISTRIB_ID='%D'\nDISTRIB_RELEASE='%V'\nDISTRIB_REVISION='%R'\nDISTRIB_TARGET='%S'\nDISTRIB_ARCH='%A'\nDISTRIB_DESCRIPTION='%D %V %C'\nDISTRIB_TAINTS='%t'\n"
  },
  {
    "path": "package/base-files/files/etc/openwrt_version",
    "content": "%C\n"
  },
  {
    "path": "package/base-files/files/etc/passwd",
    "content": "root:x:0:0:root:/root:/bin/ash\ndaemon:*:1:1:daemon:/var:/bin/false\nftp:*:55:55:ftp:/home/ftp:/bin/false\nnetwork:*:101:101:network:/var:/bin/false\nnobody:*:65534:65534:nobody:/var:/bin/false\n"
  },
  {
    "path": "package/base-files/files/etc/preinit",
    "content": "#!/bin/sh\n# Copyright (C) 2006-2016 OpenWrt.org\n# Copyright (C) 2010 Vertical Communications\n\n[ -z \"$PREINIT\" ] && exec /sbin/init\n\nexport PATH=\"%PATH%\"\n\n. /lib/functions.sh\n. /lib/functions/preinit.sh\n. /lib/functions/system.sh\n\nboot_hook_init preinit_essential\nboot_hook_init preinit_main\nboot_hook_init failsafe\nboot_hook_init initramfs\nboot_hook_init preinit_mount_root\n\nfor pi_source_file in /lib/preinit/*; do\n\t. $pi_source_file\ndone\n\nboot_run_hook preinit_essential\n\npi_mount_skip_next=false\npi_jffs2_mount_success=false\npi_failsafe_net_message=false\n\nboot_run_hook preinit_main\n"
  },
  {
    "path": "package/base-files/files/etc/profile",
    "content": "[ -e /tmp/.failsafe ] && export FAILSAFE=1\n\n[ -f /etc/banner ] && cat /etc/banner\n[ -n \"$FAILSAFE\" ] && cat /etc/banner.failsafe\n\ngrep -Fsq '/ overlay ro,' /proc/mounts && {\n\techo 'Your JFFS2-partition seems full and overlayfs is mounted read-only.'\n\techo 'Please try to remove files from /overlay/upper/... and reboot!'\n}\n\nexport PATH=\"%PATH%\"\nexport HOME=$(grep -e \"^${USER:-root}:\" /etc/passwd | cut -d \":\" -f 6)\nexport HOME=${HOME:-/root}\nexport PS1='\\u@\\h:\\w\\$ '\nexport ENV=/etc/shinit\n\ncase \"$TERM\" in\n\txterm*|rxvt*)\n\t\texport PS1='\\[\\e]0;\\u@\\h: \\w\\a\\]'$PS1\n\t\t;;\nesac\n\n[ -n \"$FAILSAFE\" ] || {\n\tfor FILE in /etc/profile.d/*.sh; do\n\t\t[ -e \"$FILE\" ] && . \"$FILE\"\n\tdone\n\tunset FILE\n}\n\nif ( grep -qs '^root::' /etc/shadow && \\\n     [ -z \"$FAILSAFE\" ] )\nthen\ncat << EOF\n=== WARNING! =====================================\nThere is no root password defined on this device!\nUse the \"passwd\" command to set up a new password\nin order to prevent unauthorized SSH logins.\n--------------------------------------------------\nEOF\nfi\n"
  },
  {
    "path": "package/base-files/files/etc/protocols",
    "content": "# Internet (IP) protocols\n#\n# Updated from http://www.iana.org/assignments/protocol-numbers and other\n# sources.\n# New protocols will be added on request if they have been officially\n# assigned by IANA and are not historical.\n# If you need a huge list of used numbers please install the nmap package.\n\nip\t0\tIP\t\t# internet protocol, pseudo protocol number\n#hopopt\t0\tHOPOPT\t\t# IPv6 Hop-by-Hop Option [RFC1883]\nicmp\t1\tICMP\t\t# internet control message protocol\nigmp\t2\tIGMP\t\t# Internet Group Management\nggp\t3\tGGP\t\t# gateway-gateway protocol\nipencap\t4\tIP-ENCAP\t# IP encapsulated in IP (officially ``IP'')\nst\t5\tST\t\t# ST datagram mode\ntcp\t6\tTCP\t\t# transmission control protocol\negp\t8\tEGP\t\t# exterior gateway protocol\nigp\t9\tIGP\t\t# any private interior gateway (Cisco)\npup\t12\tPUP\t\t# PARC universal packet protocol\nudp\t17\tUDP\t\t# user datagram protocol\nhmp\t20\tHMP\t\t# host monitoring protocol\nxns-idp\t22\tXNS-IDP\t\t# Xerox NS IDP\nrdp\t27\tRDP\t\t# \"reliable datagram\" protocol\niso-tp4\t29\tISO-TP4\t\t# ISO Transport Protocol class 4 [RFC905]\ndccp\t33\tDCCP\t\t# Datagram Congestion Control Protocol [RFC4340]\nxtp\t36\tXTP\t\t# Xpress Transfer Protocol\nddp\t37\tDDP\t\t# Datagram Delivery Protocol\nidpr-cmtp 38\tIDPR-CMTP\t# IDPR Control Message Transport\nipv6\t41\tIPv6\t\t# Internet Protocol, version 6\nipv6-route 43\tIPv6-Route\t# Routing Header for IPv6\nipv6-frag 44\tIPv6-Frag\t# Fragment Header for IPv6\nidrp\t45\tIDRP\t\t# Inter-Domain Routing Protocol\nrsvp\t46\tRSVP\t\t# Reservation Protocol\ngre\t47\tGRE\t\t# General Routing Encapsulation\nesp\t50\tIPSEC-ESP\t# Encap Security Payload [RFC2046]\nah\t51\tIPSEC-AH\t# Authentication Header [RFC2402]\nskip\t57\tSKIP\t\t# SKIP\nipv6-icmp 58\tIPv6-ICMP\t# ICMP for IPv6\nipv6-nonxt 59\tIPv6-NoNxt\t# No Next Header for IPv6\nipv6-opts 60\tIPv6-Opts\t# Destination Options for IPv6\nrspf\t73\tRSPF CPHB\t# Radio Shortest Path First (officially CPHB)\nvmtp\t81\tVMTP\t\t# Versatile Message Transport\neigrp\t88\tEIGRP\t\t# Enhanced Interior Routing Protocol (Cisco)\nospf\t89\tOSPFIGP\t\t# Open Shortest Path First IGP\nax.25\t93\tAX.25\t\t# AX.25 frames\nipip\t94\tIPIP\t\t# IP-within-IP Encapsulation Protocol\netherip\t97\tETHERIP\t\t# Ethernet-within-IP Encapsulation [RFC3378]\nencap\t98\tENCAP\t\t# Yet Another IP encapsulation [RFC1241]\n#\t99\t\t\t# any private encryption scheme\npim\t103\tPIM\t\t# Protocol Independent Multicast\nipcomp\t108\tIPCOMP\t\t# IP Payload Compression Protocol\nvrrp\t112\tVRRP\t\t# Virtual Router Redundancy Protocol\nl2tp\t115\tL2TP\t\t# Layer Two Tunneling Protocol [RFC2661]\nisis\t124\tISIS\t\t# IS-IS over IPv4\nsctp\t132\tSCTP\t\t# Stream Control Transmission Protocol\nfc\t133\tFC\t\t# Fibre Channel\n\n"
  },
  {
    "path": "package/base-files/files/etc/rc.button/failsafe",
    "content": "#!/bin/sh\n\n[ \"${TYPE}\" = \"switch\" ] || echo ${BUTTON} > /tmp/failsafe_button\n\nreturn 0\n"
  },
  {
    "path": "package/base-files/files/etc/rc.button/power",
    "content": "#!/bin/sh\n\n[ \"${ACTION}\" = \"released\" ] || exit 0\n\nexec /sbin/poweroff\n\nreturn 0\n"
  },
  {
    "path": "package/base-files/files/etc/rc.button/reboot",
    "content": "#!/bin/sh\n\n[ \"${ACTION}\" = \"released\" ] || exit 0\n\nif [ \"$SEEN\" -ge 5 ]\nthen\n\techo \"REBOOT\" > /dev/console\n\tsync\n\treboot\nfi\n\nreturn 0\n"
  },
  {
    "path": "package/base-files/files/etc/rc.button/reset",
    "content": "#!/bin/sh\n\n. /lib/functions.sh\n\nOVERLAY=\"$( grep ' /overlay ' /proc/mounts )\"\n\ncase \"$ACTION\" in\npressed)\n\t[ -z \"$OVERLAY\" ] && return 0\n\n\treturn 5\n;;\ntimeout)\n\t. /etc/diag.sh\n\tset_state failsafe\n;;\nreleased)\n\tif [ \"$SEEN\" -lt 1 ]\n\tthen\n\t\techo \"REBOOT\" > /dev/console\n\t\tsync\n\t\treboot\n\telif [ \"$SEEN\" -ge 5 -a -n \"$OVERLAY\" ]\n\tthen\n\t\techo \"FACTORY RESET\" > /dev/console\n\t\tjffs2reset -y && reboot &\n\tfi\n;;\nesac\n\nreturn 0\n"
  },
  {
    "path": "package/base-files/files/etc/rc.button/rfkill",
    "content": "#!/bin/sh\n\n[ \"${ACTION}\" = \"released\" -o -n \"${TYPE}\" ] || exit 0\n\n. /lib/functions.sh\n\nrfkill_state=0\n\nwifi_rfkill_set() {\n\tuci set wireless.$1.disabled=$rfkill_state\n}\n\nwifi_rfkill_check() {\n\tlocal disabled\n\tconfig_get disabled $1 disabled\n\t[ \"$disabled\" = \"1\" ] || rfkill_state=1\n}\n\nconfig_load wireless\ncase \"${TYPE}\" in\n\"switch\")\n\t[ \"${ACTION}\" = \"released\" ] && rfkill_state=1\n\t;;\n*)\n\tconfig_foreach wifi_rfkill_check wifi-device\n\t;;\nesac\nconfig_foreach wifi_rfkill_set wifi-device\nuci commit wireless\nwifi up\n\nreturn 0\n"
  },
  {
    "path": "package/base-files/files/etc/rc.common",
    "content": "#!/bin/sh\n# Copyright (C) 2006-2012 OpenWrt.org\n\n. $IPKG_INSTROOT/lib/functions.sh\n. $IPKG_INSTROOT/lib/functions/service.sh\n\ninitscript=$1\naction=${2:-help}\nshift 2\n\nstart() {\n\treturn 0\n}\n\nstop() {\n\treturn 0\n}\n\nreload() {\n\trestart\n}\n\nrestart() {\n\ttrap '' TERM\n\tstop \"$@\"\n\ttrap - TERM\n\tstart \"$@\"\n}\n\nboot() {\n\tstart \"$@\"\n}\n\nshutdown() {\n\tstop\n}\n\ndisable() {\n\tname=\"$(basename \"${initscript}\")\"\n\trm -f \"$IPKG_INSTROOT\"/etc/rc.d/S??$name\n\trm -f \"$IPKG_INSTROOT\"/etc/rc.d/K??$name\n}\n\nenable() {\n\terr=1\n\tname=\"$(basename \"${initscript}\")\"\n\t[ \"$START\" ] && \\\n\t\tln -sf \"../init.d/$name\" \"$IPKG_INSTROOT/etc/rc.d/S${START}${name##S[0-9][0-9]}\" && \\\n\t\terr=0\n\t[ \"$STOP\" ] && \\\n\t\tln -sf \"../init.d/$name\" \"$IPKG_INSTROOT/etc/rc.d/K${STOP}${name##K[0-9][0-9]}\" && \\\n\t\terr=0\n\treturn $err\n}\n\nenabled() {\n\tname=\"$(basename \"${initscript}\")\"\n\tname=\"${name##[SK][0-9][0-9]}\"\n\t{\n\t\t[ -z \"${START:-}\" ] || [ -L \"$IPKG_INSTROOT/etc/rc.d/S${START}$name\" ]\n\t} && {\n\t\t[ -z \"${STOP:-}\" ] || [ -L \"$IPKG_INSTROOT/etc/rc.d/K${STOP}$name\" ]\n\t}\n}\n\ndepends() {\n\treturn 0\n}\n\nALL_HELP=\"\"\nALL_COMMANDS=\"boot shutdown depends\"\nextra_command() {\n\tlocal cmd=\"$1\"\n\tlocal help=\"$2\"\n\n\tlocal extra=\"$(printf \"%-16s%s\" \"${cmd}\" \"${help}\")\"\n\tALL_HELP=\"${ALL_HELP}\\t${extra}\\n\"\n\tALL_COMMANDS=\"${ALL_COMMANDS} ${cmd}\"\n}\n\nhelp() {\n\tcat <<EOF\nSyntax: $initscript [command]\n\nAvailable commands:\nEOF\n\techo -e \"$ALL_HELP\"\n}\n\n# for procd\nstart_service() {\n\treturn 0\n}\n\nstop_service() {\n\treturn 0\n}\n\nservice_triggers() {\n\treturn 0\n}\n\nservice_data() {\n\treturn 0\n}\n\nservice_running() {\n\tlocal instance=\"${1:-*}\"\n\n\tprocd_running \"$(basename $initscript)\" \"$instance\"\n}\n\n${INIT_TRACE:+set -x}\n\nextra_command \"start\" \"Start the service\"\nextra_command \"stop\" \"Stop the service\"\nextra_command \"restart\" \"Restart the service\"\nextra_command \"reload\" \"Reload configuration files (or restart if service does not implement reload)\"\nextra_command \"enable\" \"Enable service autostart\"\nextra_command \"disable\" \"Disable service autostart\"\nextra_command \"enabled\" \"Check if service is started on boot\"\n\n. \"$initscript\"\n\n[ -n \"$USE_PROCD\" ] && {\n\textra_command \"running\" \"Check if service is running\"\n\textra_command \"status\" \"Service status\"\n\textra_command \"trace\" \"Start with syscall trace\"\n\textra_command \"info\" \"Dump procd service info\"\n\n\t. $IPKG_INSTROOT/lib/functions/procd.sh\n\tbasescript=$(readlink \"$initscript\")\n\trc_procd() {\n\t\tlocal method=\"set\"\n\t\t[ -n \"$2\" ] && method=\"add\"\n\t\tprocd_open_service \"$(basename ${basescript:-$initscript})\" \"$initscript\"\n\t\t\"$@\"\n\t\tprocd_close_service \"$method\"\n\t}\n\n\tstart() {\n\t\trc_procd start_service \"$@\"\n\t\tif eval \"type service_started\" 2>/dev/null >/dev/null; then\n\t\t\tservice_started\n\t\tfi\n\t}\n\n\ttrace() {\n\t\tTRACE_SYSCALLS=1\n\t\tstart \"$@\"\n\t}\n\n\tinfo() {\n\t\tjson_init\n\t\tjson_add_string name \"$(basename ${basescript:-$initscript})\"\n\t\tjson_add_boolean verbose \"1\"\n\t\t_procd_ubus_call list\n\t}\n\n\tstop() {\n\t\tprocd_lock\n\t\tstop_service \"$@\"\n\t\tprocd_kill \"$(basename ${basescript:-$initscript})\" \"$1\"\n\t\tif eval \"type service_stopped\" 2>/dev/null >/dev/null; then\n\t\t\tservice_stopped\n\t\tfi\n\t}\n\n\treload() {\n\t\tif eval \"type reload_service\" 2>/dev/null >/dev/null; then\n\t\t\tprocd_lock\n\t\t\treload_service \"$@\"\n\t\telse\n\t\t\tstart\n\t\tfi\n\t}\n\n\trunning() {\n\t\tservice_running \"$@\"\n\t}\n\n\tstatus() {\n\t\tif eval \"type status_service\" 2>/dev/null >/dev/null; then\n\t\t\tstatus_service \"$@\"\n\t\telse\n\t\t\t_procd_status \"$(basename ${basescript:-$initscript})\" \"$1\"\n\t\tfi\n\t}\n}\n\nALL_COMMANDS=\"${ALL_COMMANDS} ${EXTRA_COMMANDS}\"\nALL_HELP=\"${ALL_HELP}${EXTRA_HELP}\"\nlist_contains ALL_COMMANDS \"$action\" || action=help\n$action \"$@\"\n"
  },
  {
    "path": "package/base-files/files/etc/rc.local",
    "content": "# Put your custom commands here that should be executed once\n# the system init finished. By default this file does nothing.\n\nexit 0\n"
  },
  {
    "path": "package/base-files/files/etc/services",
    "content": "echo\t\t7/tcp\necho\t\t7/udp\ndiscard\t\t9/tcp\ndiscard\t\t9/udp\ndaytime\t\t13/tcp\ndaytime\t\t13/udp\nnetstat\t\t15/tcp\nchargen\t\t19/tcp\nchargen\t\t19/udp\nftp-data\t20/tcp\nftp\t\t21/tcp\nssh\t\t22/tcp\nssh\t\t22/udp\ntelnet\t\t23/tcp\nsmtp\t\t25/tcp\ntime\t\t37/tcp\ntime\t\t37/udp\nwhois\t\t43/tcp\ndomain\t\t53/tcp\ndomain\t\t53/udp\nbootps\t\t67/tcp\nbootps\t\t67/udp\nbootpc\t\t68/tcp\nbootpc\t\t68/udp\ntftp\t\t69/udp\nfinger\t\t79/tcp\nwww\t\t80/tcp\t\thttp\nkerberos\t88/tcp\t\tkerberos5 krb5 kerberos-sec\nkerberos\t88/udp\t\tkerberos5 krb5 kerberos-sec\npop3\t\t110/tcp\npop3\t\t110/udp\nsunrpc\t\t111/tcp\t\trpcbind\nsunrpc\t\t111/udp\t\trpcbind\nauth\t\t113/tcp\t\tident\nsftp\t\t115/tcp\nnntp\t\t119/tcp\nntp\t\t123/tcp\nntp\t\t123/udp\nnetbios-ns\t137/tcp\nnetbios-ns\t137/udp\nnetbios-dgm\t138/tcp\nnetbios-dgm\t138/udp\nnetbios-ssn\t139/tcp\nnetbios-ssn\t139/udp\nimap2\t\t143/tcp\t\timap\nimap2\t\t143/udp\t\timap\nsnmp\t\t161/tcp\nsnmp\t\t161/udp\nsnmp-trap\t162/tcp\t\tsnmptrap\nsnmp-trap\t162/udp\t\tsnmptrap\nxdmcp\t\t177/tcp\nxdmcp\t\t177/udp\nbgp\t\t179/tcp\nbgp\t\t179/udp\nimap3\t\t220/tcp\nimap3\t\t220/udp\nldap\t\t389/tcp\nldap\t\t389/udp\nhttps\t\t443/tcp\nhttps\t\t443/udp\nmicrosoft-ds\t445/tcp\nmicrosoft-ds\t445/udp\nisakmp\t\t500/tcp\nisakmp\t\t500/udp\nrtsp\t\t554/tcp\nrtsp\t\t554/udp\nipp\t\t631/tcp\nipp\t\t631/udp\nsyslog\t\t514/udp\nprinter\t\t515/tcp\t\tspooler\ndhcpv6-client\t546/tcp\ndhcpv6-client\t546/udp\ndhcpv6-server\t547/tcp\ndhcpv6-server\t547/udp\nafpovertcp\t548/tcp\nafpovertcp\t548/udp\nnntps\t\t563/tcp\t\tsnntp\nnntps\t\t563/udp\t\tsnntp\nsubmission\t587/tcp\nsubmission\t587/udp\nldaps\t\t636/tcp\nldaps\t\t636/udp\ntinc\t\t655/tcp\ntinc\t\t655/udp\nrsync\t\t873/tcp\nrsync\t\t873/udp\nftps-data\t989/tcp\nftps\t\t990/tcp\nimaps\t\t993/tcp\nimaps\t\t993/udp\nircs\t\t994/tcp\nircs\t\t994/udp\npop3s\t\t995/tcp\npop3s\t\t995/udp\nsocks\t\t1080/tcp\nsocks\t\t1080/udp\nopenvpn\t\t1194/tcp\nopenvpn\t\t1194/udp\nl2f\t\t1701/tcp\tl2tp\nl2f\t\t1701/udp\tl2tp\nradius\t\t1812/tcp\nradius\t\t1812/udp\nradius-acct\t1813/tcp\tradacct\nradius-acct\t1813/udp\tradacct\nnfs\t\t2049/tcp\nnfs\t\t2049/udp\ndict\t\t2628/tcp\ndict\t\t2628/udp\ngpsd\t\t2947/tcp\ngpsd\t\t2947/udp\nicpv2\t\t3130/tcp\ticp\nicpv2\t\t3130/udp\ticp\nmysql\t\t3306/tcp\nmysql\t\t3306/udp\nnut\t\t3493/tcp\nnut\t\t3493/udp\ndistcc\t\t3632/tcp\ndistcc\t\t3632/udp\ndaap\t\t3689/tcp\ndaap\t\t3689/udp\nsvn\t\t3690/tcp\tsubversion\nsvn\t\t3690/udp\tsubversion\nepmd\t\t4369/tcp\nepmd\t\t4369/udp\niax\t\t4569/tcp\niax\t\t4569/udp\nmtn\t\t4691/tcp\nmtn\t\t4691/udp\nmunin\t\t4949/tcp\nsip\t\t5060/tcp\nsip\t\t5060/udp\nsip-tls\t\t5061/tcp\nsip-tls\t\t5061/udp\nxmpp-client\t5222/tcp\tjabber-client\nxmpp-client\t5222/udp\tjabber-client\nxmpp-server\t5269/tcp\tjabber-server\nxmpp-server\t5269/udp\tjabber-server\nmdns\t\t5353/tcp\nmdns\t\t5353/udp\npostgresql\t5432/tcp\tpostgres\npostgresql\t5432/udp\tpostgres\nx11\t\t6000/tcp\nx11\t\t6000/udp\nmysql-proxy\t6446/tcp\nmysql-proxy\t6446/udp\nbacula-dir\t9101/tcp\nbacula-dir\t9101/udp\nbacula-fd\t9102/tcp\nbacula-fd\t9102/udp\nbacula-sd\t9103/tcp\nbacula-sd\t9103/udp\nnbd\t\t10809/tcp\nzabbix-agent\t10050/tcp\nzabbix-agent\t10050/udp\nzabbix-trapper\t10051/tcp\nzabbix-trapper\t10051/udp\nhkp\t\t11371/tcp\nhkp\t\t11371/udp\nssmtp\t\t465/tcp\t\tsmtps\nspamd\t\t783/tcp\nzebrasrv\t2600/tcp\nzebra\t\t2601/tcp\nripd\t\t2602/tcp\nripngd\t\t2603/tcp\nospfd\t\t2604/tcp\nbgpd\t\t2605/tcp\nospf6d\t\t2606/tcp\nospfapi\t\t2607/tcp\nisisd\t\t2608/tcp\nsane-port\t6566/tcp\tsane saned\nircd\t\t6667/tcp\ngit\t\t9418/tcp\n\n"
  },
  {
    "path": "package/base-files/files/etc/shadow",
    "content": "root:::0:99999:7:::\ndaemon:*:0:0:99999:7:::\nftp:*:0:0:99999:7:::\nnetwork:*:0:0:99999:7:::\nnobody:*:0:0:99999:7:::\n"
  },
  {
    "path": "package/base-files/files/etc/shells",
    "content": "/bin/ash\n"
  },
  {
    "path": "package/base-files/files/etc/shinit",
    "content": "[ -x /bin/more ] || [ -x /usr/bin/more ] || alias more=less\n[ -x /usr/bin/vim ] && alias vi=vim || alias vim=vi\n\nalias ll='ls -alF --color=auto'\n\n[ -z \"$KSH_VERSION\" -o \\! -s /etc/mkshrc ] || . /etc/mkshrc\n\n[ -x /usr/bin/arp -o -x /sbin/arp ] || arp() { cat /proc/net/arp; }\n[ -x /usr/bin/ldd ] || ldd() { LD_TRACE_LOADED_OBJECTS=1 $*; }\n\n[ -n \"$KSH_VERSION\" -o \\! -s \"$HOME/.shinit\" ] || . \"$HOME/.shinit\"\n[ -z \"$KSH_VERSION\" -o \\! -s \"$HOME/.mkshrc\" ] || . \"$HOME/.mkshrc\"\n"
  },
  {
    "path": "package/base-files/files/etc/sysctl.conf",
    "content": "# Defaults are configured in /etc/sysctl.d/* and can be customized in this file\n"
  },
  {
    "path": "package/base-files/files/etc/sysctl.d/10-default.conf",
    "content": "# Do not edit, changes to this file will be lost on upgrades\n# /etc/sysctl.conf can be used to customize sysctl settings\n\nkernel.panic=3\nkernel.core_pattern=/tmp/%e.%t.%p.%s.core\nfs.suid_dumpable=2\n\nfs.protected_hardlinks=1\nfs.protected_symlinks=1\n\nnet.core.bpf_jit_enable=1\n\nnet.ipv4.conf.default.arp_ignore=1\nnet.ipv4.conf.all.arp_ignore=1\nnet.ipv4.ip_forward=1\nnet.ipv4.icmp_echo_ignore_broadcasts=1\nnet.ipv4.icmp_ignore_bogus_error_responses=1\nnet.ipv4.igmp_max_memberships=100\nnet.ipv4.tcp_fin_timeout=30\nnet.ipv4.tcp_keepalive_time=120\nnet.ipv4.tcp_syncookies=1\nnet.ipv4.tcp_timestamps=1\nnet.ipv4.tcp_sack=1\nnet.ipv4.tcp_dsack=1\n\nnet.ipv6.conf.default.forwarding=1\nnet.ipv6.conf.all.forwarding=1\n"
  },
  {
    "path": "package/base-files/files/etc/sysupgrade.conf",
    "content": "## This file contains files and directories that should\n## be preserved during an upgrade.\n\n# /etc/example.conf\n# /etc/openvpn/\n"
  },
  {
    "path": "package/base-files/files/etc/uci-defaults/10_migrate-shadow",
    "content": "ppwd=\"$(sed -ne '/^root:/s/^root:\\([^:]*\\):.*$/\\1/p' /etc/passwd)\"\nspwd=\"$(sed -ne '/^root:/s/^root:\\([^:]*\\):.*$/\\1/p' /etc/shadow)\"\n\nif [ -n \"${ppwd#[\\!x]}\" ] && [ -z \"${spwd#[\\!x]}\" ]; then\n\tlogger -t migrate-shadow \"Moving root password hash into shadow database\"\n\tsed -i -e \"s:^root\\:[^\\:]*\\::root\\:x\\::\"     /etc/passwd\n\tsed -i -e \"s:^root\\:[^\\:]*\\::root\\:$ppwd\\::\" /etc/shadow\nfi\n\nexit 0\n"
  },
  {
    "path": "package/base-files/files/etc/uci-defaults/12_network-generate-ula",
    "content": "[ \"$(uci -q get network.globals.ula_prefix)\" != \"auto\" ] && exit 0\n\nr1=$(dd if=/dev/urandom bs=1 count=1 |hexdump -e '1/1 \"%02x\"')\nr2=$(dd if=/dev/urandom bs=2 count=1 |hexdump -e '2/1 \"%02x\"')\nr3=$(dd if=/dev/urandom bs=2 count=1 |hexdump -e '2/1 \"%02x\"')\n\nuci -q batch <<-EOF >/dev/null\n\tset network.globals.ula_prefix=fd$r1:$r2:$r3::/48\n\tcommit network\nEOF\n\nexit 0\n\n"
  },
  {
    "path": "package/base-files/files/etc/uci-defaults/13_fix-group-user",
    "content": ". /lib/functions.sh\n\nfor file in $(grep -sl Require-User /usr/lib/opkg/info/*.control); do\n\tfile=\"${file##*/}\"\n\tfile=\"${file%.control}\"\n\tadd_group_and_user \"${file}\"\ndone\n\nexit 0\n"
  },
  {
    "path": "package/base-files/files/lib/functions/caldata.sh",
    "content": "# Copyright (C) 2019 OpenWrt.org\n\n. /lib/functions.sh\n. /lib/functions/system.sh\n\ncaldata_dd() {\n\tlocal source=$1\n\tlocal target=$2\n\tlocal count=$(($3))\n\tlocal offset=$(($4))\n\n\tdd if=$source of=$target iflag=skip_bytes,fullblock bs=$count skip=$offset count=1 2>/dev/null\n\treturn $?\n}\n\ncaldata_die() {\n\techo \"caldata: \" \"$*\"\n\texit 1\n}\n\ncaldata_extract() {\n\tlocal part=$1\n\tlocal offset=$(($2))\n\tlocal count=$(($3))\n\tlocal mtd\n\n\tmtd=$(find_mtd_chardev $part)\n\t[ -n \"$mtd\" ] || caldata_die \"no mtd device found for partition $part\"\n\n\tcaldata_dd $mtd /lib/firmware/$FIRMWARE $count $offset || \\\n\t\tcaldata_die \"failed to extract calibration data from $mtd\"\n}\n\ncaldata_extract_ubi() {\n\tlocal part=$1\n\tlocal offset=$(($2))\n\tlocal count=$(($3))\n\tlocal ubidev\n\tlocal ubi\n\n\t. /lib/upgrade/nand.sh\n\n\tubidev=$(nand_find_ubi $CI_UBIPART)\n\tubi=$(nand_find_volume $ubidev $part)\n\t[ -n \"$ubi\" ] || caldata_die \"no UBI volume found for $part\"\n\n\tcaldata_dd /dev/$ubi /lib/firmware/$FIRMWARE $count $offset || \\\n\t\tcaldata_die \"failed to extract calibration data from $ubi\"\n}\n\ncaldata_extract_mmc() {\n\tlocal part=$1\n\tlocal offset=$(($2))\n\tlocal count=$(($3))\n\tlocal mmc_part\n\n\tmmc_part=$(find_mmc_part $part)\n\t[ -n \"$mmc_part\" ] || caldata_die \"no mmc partition found for partition $part\"\n\n\tcaldata_dd $mmc_part /lib/firmware/$FIRMWARE $count $offset || \\\n\t\tcaldata_die \"failed to extract calibration data from $mmc_part\"\n}\n\ncaldata_extract_reverse() {\n\tlocal part=$1\n\tlocal offset=$2\n\tlocal count=$(($3))\n\tlocal mtd\n\tlocal reversed\n\tlocal caldata\n\n\tmtd=$(find_mtd_chardev \"$part\")\n\treversed=$(hexdump -v -s $offset -n $count -e '/1 \"%02x \"' $mtd)\n\n\tfor byte in $reversed; do\n\t\tcaldata=\"\\x${byte}${caldata}\"\n\tdone\n\n\tprintf \"%b\" \"$caldata\" > /lib/firmware/$FIRMWARE\n}\n\ncaldata_from_file() {\n\tlocal source=$1\n\tlocal offset=$(($2))\n\tlocal count=$(($3))\n\tlocal target=$4\n\n\t[ -n \"$target\" ] || target=/lib/firmware/$FIRMWARE\n\n\tcaldata_dd $source $target $count $offset || \\\n\t\tcaldata_die \"failed to extract calibration data from $source\"\n}\n\ncaldata_sysfsload_from_file() {\n\tlocal source=$1\n\tlocal offset=$(($2))\n\tlocal count=$(($3))\n\tlocal target_dir=\"/sys/$DEVPATH\"\n\tlocal target=\"$target_dir/data\"\n\n\t[ -d \"$target_dir\" ] || \\\n\t\tcaldata_die \"no sysfs dir to write: $target\"\n\n\techo 1 > \"$target_dir/loading\"\n\tcaldata_dd $source $target $count $offset\n\tif [ $? != 0 ]; then\n\t\techo 1 > \"$target_dir/loading\"\n\t\tcaldata_die \"failed to extract calibration data from $source\"\n\telse\n\t\techo 0 > \"$target_dir/loading\"\n\tfi\n}\n\ncaldata_valid() {\n\tlocal expected=\"$1\"\n\tlocal target=$2\n\n\t[ -n \"$target\" ] || target=/lib/firmware/$FIRMWARE\n\n\tmagic=$(hexdump -v -n 2 -e '1/1 \"%02x\"' $target)\n\t[ \"$magic\" = \"$expected\" ]\n\treturn $?\n}\n\ncaldata_patch_chksum() {\n\tlocal mac=$1\n\tlocal mac_offset=$(($2))\n\tlocal chksum_offset=$(($3))\n\tlocal target=$4\n\tlocal xor_mac\n\tlocal xor_fw_mac\n\tlocal xor_fw_chksum\n\n\txor_mac=${mac//:/}\n\txor_mac=\"${xor_mac:0:4} ${xor_mac:4:4} ${xor_mac:8:4}\"\n\n\txor_fw_mac=$(hexdump -v -n 6 -s $mac_offset -e '/1 \"%02x\"' /lib/firmware/$FIRMWARE)\n\txor_fw_mac=\"${xor_fw_mac:0:4} ${xor_fw_mac:4:4} ${xor_fw_mac:8:4}\"\n\n\txor_fw_chksum=$(hexdump -v -n 2 -s $chksum_offset -e '/1 \"%02x\"' /lib/firmware/$FIRMWARE)\n\txor_fw_chksum=$(xor $xor_fw_chksum $xor_fw_mac $xor_mac)\n\n\tprintf \"%b\" \"\\x${xor_fw_chksum:0:2}\\x${xor_fw_chksum:2:2}\" | \\\n\t\tdd of=$target conv=notrunc bs=1 seek=$chksum_offset count=2\n}\n\ncaldata_patch_mac() {\n\tlocal mac=$1\n\tlocal mac_offset=$(($2))\n\tlocal chksum_offset=$3\n\tlocal target=$4\n\n\t[ -z \"$mac\" -o -z \"$mac_offset\" ] && return\n\n\t[ -n \"$target\" ] || target=/lib/firmware/$FIRMWARE\n\n\t[ -n \"$chksum_offset\" ] && caldata_patch_chksum \"$mac\" \"$mac_offset\" \"$chksum_offset\" \"$target\"\n\n\tmacaddr_2bin $mac | dd of=$target conv=notrunc oflag=seek_bytes bs=6 seek=$mac_offset count=1 || \\\n\t\tcaldata_die \"failed to write MAC address to eeprom file\"\n}\n\nath9k_patch_mac() {\n\tlocal mac=$1\n\tlocal target=$2\n\n\tcaldata_patch_mac \"$mac\" 0x2 \"\" \"$target\"\n}\n\nath9k_patch_mac_crc() {\n\tlocal mac=$1\n\tlocal mac_offset=$2\n\tlocal chksum_offset=$((mac_offset - 10))\n\tlocal target=$4\n\n\tcaldata_patch_mac \"$mac\" \"$mac_offset\" \"$chksum_offset\" \"$target\"\n}\n\nath10k_patch_mac() {\n\tlocal mac=$1\n\tlocal target=$2\n\n\tcaldata_patch_mac \"$mac\" 0x6 0x2 \"$target\"\n}\n"
  },
  {
    "path": "package/base-files/files/lib/functions/leds.sh",
    "content": "# Copyright (C) 2013 OpenWrt.org\n\nget_dt_led_path() {\n\tlocal ledpath\n\tlocal basepath=\"/proc/device-tree\"\n\tlocal nodepath=\"$basepath/aliases/led-$1\"\n\n\t[ -f \"$nodepath\" ] && ledpath=$(cat \"$nodepath\")\n\t[ -n \"$ledpath\" ] && ledpath=\"$basepath$ledpath\"\n\n\techo \"$ledpath\"\n}\n\nget_dt_led() {\n\tlocal label\n\tlocal ledpath=$(get_dt_led_path $1)\n\n\t[ -n \"$ledpath\" ] && \\\n\t\tlabel=$(cat \"$ledpath/label\" 2>/dev/null) || \\\n\t\tlabel=$(cat \"$ledpath/chan-name\" 2>/dev/null) || \\\n\t\tlabel=$(basename \"$ledpath\")\n\n\techo \"$label\"\n}\n\nled_set_attr() {\n\t[ -f \"/sys/class/leds/$1/$2\" ] && echo \"$3\" > \"/sys/class/leds/$1/$2\"\n}\n\nled_timer() {\n\tled_set_attr $1 \"trigger\" \"timer\"\n\tled_set_attr $1 \"delay_on\" \"$2\"\n\tled_set_attr $1 \"delay_off\" \"$3\"\n}\n\nled_on() {\n\tled_set_attr $1 \"trigger\" \"none\"\n\tled_set_attr $1 \"brightness\" 255\n}\n\nled_off() {\n\tled_set_attr $1 \"trigger\" \"none\"\n\tled_set_attr $1 \"brightness\" 0\n}\n\nstatus_led_restore_trigger() {\n\tlocal trigger\n\tlocal ledpath=$(get_dt_led_path $1)\n\n\t[ -n \"$ledpath\" ] && \\\n\t\ttrigger=$(cat \"$ledpath/linux,default-trigger\" 2>/dev/null)\n\n\t[ -n \"$trigger\" ] && \\\n\t\tled_set_attr \"$(get_dt_led $1)\" \"trigger\" \"$trigger\"\n}\n\nstatus_led_set_timer() {\n\tled_timer $status_led \"$1\" \"$2\"\n\t[ -n \"$status_led2\" ] && led_timer $status_led2 \"$1\" \"$2\"\n}\n\nstatus_led_set_heartbeat() {\n\tled_set_attr $status_led \"trigger\" \"heartbeat\"\n}\n\nstatus_led_on() {\n\tled_on $status_led\n\t[ -n \"$status_led2\" ] && led_on $status_led2\n}\n\nstatus_led_off() {\n\tled_off $status_led\n\t[ -n \"$status_led2\" ] && led_off $status_led2\n}\n\nstatus_led_blink_slow() {\n\tled_timer $status_led 1000 1000\n}\n\nstatus_led_blink_fast() {\n\tled_timer $status_led 100 100\n}\n\nstatus_led_blink_preinit() {\n\tled_timer $status_led 100 100\n}\n\nstatus_led_blink_failsafe() {\n\tled_timer $status_led 50 50\n}\n\nstatus_led_blink_preinit_regular() {\n\tled_timer $status_led 200 200\n}\n"
  },
  {
    "path": "package/base-files/files/lib/functions/migrations.sh",
    "content": ". /lib/functions.sh\n\nmigrate_led_sysfs() {\n\tlocal cfg=\"$1\"; shift\n\tlocal tuples=\"$@\"\n\tlocal sysfs\n\tlocal name\n\n\tconfig_get sysfs ${cfg} sysfs\n\tconfig_get name ${cfg} name\n\n\t[ -z \"${sysfs}\" ] && return\n\n\tfor tuple in ${tuples}; do\n\t\tlocal old=${tuple%=*}\n\t\tlocal new=${tuple#*=}\n\t\tlocal new_sysfs\n\n\t\tnew_sysfs=$(echo ${sysfs} | sed \"s/${old}/${new}/\")\n\n\t\t[ \"${new_sysfs}\" = \"${sysfs}\" ] && continue\n\n\t\tuci set system.${cfg}.sysfs=\"${new_sysfs}\"\n\n\t\tlogger -t led-migration \"sysfs option of LED \\\"${name}\\\" updated to ${new_sysfs}\"\n\tdone;\n}\n\nremove_devicename_led_sysfs() {\n\tlocal cfg=\"$1\"; shift\n\tlocal exceptions=\"$@\"\n\tlocal sysfs\n\tlocal name\n\tlocal new_sysfs\n\n\tconfig_get sysfs ${cfg} sysfs\n\tconfig_get name ${cfg} name\n\n\t# only continue if two or more colons are present\n\techo \"${sysfs}\" | grep -q \":.*:\" || return\n\n\tfor exception in ${exceptions}; do\n\t\t# no change if exceptions provided as argument are found for devicename\n\t\techo \"${sysfs}\" | grep -q \"^${exception}:\" && return\n\tdone\n\n\tnew_sysfs=$(echo ${sysfs} | sed \"s/^[^:]*://\")\n\n\tuci set system.${cfg}.sysfs=\"${new_sysfs}\"\n\n\tlogger -t led-migration \"sysfs option of LED \\\"${name}\\\" updated to ${new_sysfs}\"\n}\n\nmigrate_leds() {\n\tconfig_load system\n\tconfig_foreach migrate_led_sysfs led \"$@\"\n}\n\nremove_devicename_leds() {\n\tconfig_load system\n\tconfig_foreach remove_devicename_led_sysfs led \"$@\"\n}\n\nmigrations_apply() {\n\tlocal realm=\"$1\"\n\t[ -n \"$(uci changes ${realm})\" ] && uci -q commit ${realm}\n}\n"
  },
  {
    "path": "package/base-files/files/lib/functions/network.sh",
    "content": "# 1: destination variable\n# 2: interface\n# 3: path\n# 4: separator\n# 5: limit\n__network_ifstatus() {\n\tlocal __tmp\n\n\t[ -z \"$__NETWORK_CACHE\" ] && {\n\t\t__tmp=\"$(ubus call network.interface dump 2>&1)\"\n\t\tcase \"$?\" in\n\t\t\t4) : ;;\n\t\t\t0) export __NETWORK_CACHE=\"$__tmp\" ;;\n\t\t\t*) echo \"$__tmp\" >&2 ;;\n\t\tesac\n\t}\n\n\t__tmp=\"$(jsonfilter ${4:+-F \"$4\"} ${5:+-l \"$5\"} -s \"${__NETWORK_CACHE:-{}}\" -e \"$1=@.interface${2:+[@.interface='$2']}$3\")\"\n\n\t[ -z \"$__tmp\" ] && \\\n\t\tunset \"$1\" && \\\n\t\treturn 1\n\n\teval \"$__tmp\"\n}\n\n# determine first IPv4 address of given logical interface\n# 1: destination variable\n# 2: interface\nnetwork_get_ipaddr() {\n\t__network_ifstatus \"$1\" \"$2\" \"['ipv4-address'][0].address\";\n}\n\n# determine first IPv6 address of given logical interface\n# 1: destination variable\n# 2: interface\nnetwork_get_ipaddr6() {\n\t__network_ifstatus \"$1\" \"$2\" \"['ipv6-address'][0].address\" || \\\n\t\t__network_ifstatus \"$1\" \"$2\" \"['ipv6-prefix-assignment'][0]['local-address'].address\" || \\\n\t\treturn 1\n}\n\n# determine first IPv4 subnet of given logical interface\n# 1: destination variable\n# 2: interface\nnetwork_get_subnet() {\n\t__network_ifstatus \"$1\" \"$2\" \"['ipv4-address'][0]['address','mask']\" \"/\"\n}\n\n# determine first IPv6 subnet of given logical interface\n# 1: destination variable\n# 2: interface\nnetwork_get_subnet6() {\n\tlocal __nets __addr\n\n\tif network_get_subnets6 __nets \"$2\"; then\n\t\t# Attempt to return first non-fe80::/10, non-fc::/7 range\n\t\tfor __addr in $__nets; do\n\t\t\tcase \"$__addr\" in fe[8ab]?:*|f[cd]??:*)\n\t\t\t\tcontinue\n\t\t\tesac\n\t\t\texport \"$1=$__addr\"\n\t\t\treturn 0\n\t\tdone\n\n\t\t# Attempt to return first non-fe80::/10 range\n\t\tfor __addr in $__nets; do\n\t\t\tcase \"$__addr\" in fe[8ab]?:*)\n\t\t\t\tcontinue\n\t\t\tesac\n\t\t\texport \"$1=$__addr\"\n\t\t\treturn 0\n\t\tdone\n\n\t\t# Return first item\n\t\tfor __addr in $__nets; do\n\t\t\texport \"$1=$__addr\"\n\t\t\treturn 0\n\t\tdone\n\tfi\n\n\tunset \"$1\"\n\treturn 1\n}\n\n# determine first IPv6 prefix of given logical interface\n# 1: destination variable\n# 2: interface\nnetwork_get_prefix6() {\n\t__network_ifstatus \"$1\" \"$2\" \"['ipv6-prefix'][0]['address','mask']\" \"/\"\n}\n\n# determine all IPv4 addresses of given logical interface\n# 1: destination variable\n# 2: interface\nnetwork_get_ipaddrs() {\n\t__network_ifstatus \"$1\" \"$2\" \"['ipv4-address'][*].address\"\n}\n\n# determine all IPv6 addresses of given logical interface\n# 1: destination variable\n# 2: interface\nnetwork_get_ipaddrs6() {\n\tlocal __addr\n\tlocal __list=\"\"\n\n\tif __network_ifstatus \"__addr\" \"$2\" \"['ipv6-address'][*].address\"; then\n\t\tfor __addr in $__addr; do\n\t\t\t__list=\"${__list:+$__list }${__addr}\"\n\t\tdone\n\tfi\n\n\tif __network_ifstatus \"__addr\" \"$2\" \"['ipv6-prefix-assignment'][*]['local-address'].address\"; then\n\t\tfor __addr in $__addr; do\n\t\t\t__list=\"${__list:+$__list }${__addr}\"\n\t\tdone\n\tfi\n\n\tif [ -n \"$__list\" ]; then\n\t\texport \"$1=$__list\"\n\t\treturn 0\n\tfi\n\n\tunset \"$1\"\n\treturn 1\n}\n\n# determine all IP addresses of given logical interface\n# 1: destination variable\n# 2: interface\nnetwork_get_ipaddrs_all() {\n\tlocal __addr __addr6\n\n\tnetwork_get_ipaddrs __addr \"$2\"\n\tnetwork_get_ipaddrs6 __addr6 \"$2\"\n\n\tif [ -n \"$__addr\" -o -n \"$__addr6\" ]; then\n\t\texport \"$1=${__addr:+$__addr }$__addr6\"\n\t\treturn 0\n\tfi\n\n\tunset \"$1\"\n\treturn 1\n}\n\n# determine all IPv4 subnets of given logical interface\n# 1: destination variable\n# 2: interface\nnetwork_get_subnets() {\n\t__network_ifstatus \"$1\" \"$2\" \"['ipv4-address'][*]['address','mask']\" \"/ \"\n}\n\n# determine all IPv6 subnets of given logical interface\n# 1: destination variable\n# 2: interface\nnetwork_get_subnets6() {\n\tlocal __addr __mask\n\tlocal __list=\"\"\n\n\tif __network_ifstatus \"__addr\" \"$2\" \"['ipv6-address'][*]['address','mask']\" \"/ \"; then\n\t\tfor __addr in $__addr; do\n\t\t\t__list=\"${__list:+$__list }${__addr}\"\n\t\tdone\n\tfi\n\n\tif __network_ifstatus \"__addr\" \"$2\" \"['ipv6-prefix-assignment'][*]['local-address'].address\" && \\\n\t   __network_ifstatus \"__mask\" \"$2\" \"['ipv6-prefix-assignment'][*].mask\"; then\n\t\tfor __addr in $__addr; do\n\t\t\t__list=\"${__list:+$__list }${__addr}/${__mask%% *}\"\n\t\t\t__mask=\"${__mask#* }\"\n\t\tdone\n\tfi\n\n\tif [ -n \"$__list\" ]; then\n\t\texport \"$1=$__list\"\n\t\treturn 0\n\tfi\n\n\tunset \"$1\"\n\treturn 1\n}\n\n# determine all IPv6 prefixes of given logical interface\n# 1: destination variable\n# 2: interface\nnetwork_get_prefixes6() {\n\t__network_ifstatus \"$1\" \"$2\" \"['ipv6-prefix'][*]['address','mask']\" \"/ \"\n}\n\n# determine IPv4 gateway of given logical interface\n# 1: destination variable\n# 2: interface\n# 3: consider inactive gateway if \"true\" (optional)\nnetwork_get_gateway() {\n\t__network_ifstatus \"$1\" \"$2\" \".route[@.target='0.0.0.0' && !@.table].nexthop\" \"\" 1 && \\\n\t\treturn 0\n\n\t[ \"$3\" = 1 -o \"$3\" = \"true\" ] && \\\n\t\t__network_ifstatus \"$1\" \"$2\" \".inactive.route[@.target='0.0.0.0' && !@.table].nexthop\" \"\" 1\n}\n\n# determine IPv6 gateway of given logical interface\n# 1: destination variable\n# 2: interface\n# 3: consider inactive gateway if \"true\" (optional)\nnetwork_get_gateway6() {\n\t__network_ifstatus \"$1\" \"$2\" \".route[@.target='::' && !@.table].nexthop\" \"\" 1 && \\\n\t\treturn 0\n\n\t[ \"$3\" = 1 -o \"$3\" = \"true\" ] && \\\n\t\t__network_ifstatus \"$1\" \"$2\" \".inactive.route[@.target='::' && !@.table].nexthop\" \"\" 1\n}\n\n# determine the DNS servers of the given logical interface\n# 1: destination variable\n# 2: interface\n# 3: consider inactive servers if \"true\" (optional)\nnetwork_get_dnsserver() {\n\t__network_ifstatus \"$1\" \"$2\" \"['dns-server'][*]\" && return 0\n\n\t[ \"$3\" = 1 -o \"$3\" = \"true\" ] && \\\n\t\t__network_ifstatus \"$1\" \"$2\" \".inactive['dns-server'][*]\"\n}\n\n# determine the domains of the given logical interface\n# 1: destination variable\n# 2: interface\n# 3: consider inactive domains if \"true\" (optional)\nnetwork_get_dnssearch() {\n\t__network_ifstatus \"$1\" \"$2\" \"['dns-search'][*]\" && return 0\n\n\t[ \"$3\" = 1 -o \"$3\" = \"true\" ] && \\\n\t\t__network_ifstatus \"$1\" \"$2\" \".inactive['dns-search'][*]\"\n}\n\n\n# 1: destination variable\n# 2: addr\n# 3: inactive\n__network_wan()\n{\n\t__network_ifstatus \"$1\" \"\" \\\n\t\t\"[@.route[@.target='$2' && !@.table]].interface\" \"\" 1 && \\\n\t\t\treturn 0\n\n\t[ \"$3\" = 1 -o \"$3\" = \"true\" ] && \\\n\t\t__network_ifstatus \"$1\" \"\" \\\n\t\t\t\"[@.inactive.route[@.target='$2' && !@.table]].interface\" \"\" 1\n}\n\n# find the logical interface which holds the current IPv4 default route\n# 1: destination variable\n# 2: consider inactive default routes if \"true\" (optional)\nnetwork_find_wan() { __network_wan \"$1\" \"0.0.0.0\" \"$2\"; }\n\n# find the logical interface which holds the current IPv6 default route\n# 1: destination variable\n# 2: consider inactive default routes if \"true\" (optional)\nnetwork_find_wan6() { __network_wan \"$1\" \"::\" \"$2\"; }\n\n# test whether the given logical interface is running\n# 1: interface\nnetwork_is_up()\n{\n\tlocal __up\n\t__network_ifstatus \"__up\" \"$1\" \".up\" && [ \"$__up\" = 1 ]\n}\n\n# determine the protocol of the given logical interface\n# 1: destination variable\n# 2: interface\nnetwork_get_protocol() { __network_ifstatus \"$1\" \"$2\" \".proto\"; }\n\n# determine the uptime of the given logical interface\n# 1: destination variable\n# 2: interface\nnetwork_get_uptime() { __network_ifstatus \"$1\" \"$2\" \".uptime\"; }\n\n# determine the metric of the given logical interface\n# 1: destination variable\n# 2: interface\nnetwork_get_metric() { __network_ifstatus \"$1\" \"$2\" \".metric\"; }\n\n# determine the layer 3 linux network device of the given logical interface\n# 1: destination variable\n# 2: interface\nnetwork_get_device() { __network_ifstatus \"$1\" \"$2\" \".l3_device\"; }\n\n# determine the layer 2 linux network device of the given logical interface\n# 1: destination variable\n# 2: interface\nnetwork_get_physdev() { __network_ifstatus \"$1\" \"$2\" \".device\"; }\n\n# defer netifd actions on the given linux network device\n# 1: device name\nnetwork_defer_device()\n{\n\tubus call network.device set_state \\\n\t\t\"$(printf '{ \"name\": \"%s\", \"defer\": true }' \"$1\")\" 2>/dev/null\n}\n\n# continue netifd actions on the given linux network device\n# 1: device name\nnetwork_ready_device()\n{\n\tubus call network.device set_state \\\n\t\t\"$(printf '{ \"name\": \"%s\", \"defer\": false }' \"$1\")\" 2>/dev/null\n}\n\n# flush the internal value cache to force re-reading values from ubus\nnetwork_flush_cache() { unset __NETWORK_CACHE; }\n"
  },
  {
    "path": "package/base-files/files/lib/functions/preinit.sh",
    "content": "# Copyright (C) 2006-2013 OpenWrt.org\n# Copyright (C) 2010 Vertical Communications\n\nboot_hook_splice_start() {\n\texport -n PI_HOOK_SPLICE=1\n}\n\nboot_hook_splice_finish() {\n\tlocal hook\n\tfor hook in $PI_STACK_LIST; do\n\t\tlocal v; eval \"v=\\${${hook}_splice:+\\$${hook}_splice }$hook\"\n\t\texport -n \"${hook}=${v% }\"\n\t\texport -n \"${hook}_splice=\"\n\tdone\n\texport -n PI_HOOK_SPLICE=\n}\n\nboot_hook_init() {\n\tlocal hook=\"${1}_hook\"\n\texport -n \"PI_STACK_LIST=${PI_STACK_LIST:+$PI_STACK_LIST }$hook\"\n\texport -n \"$hook=\"\n}\n\nboot_hook_add() {\n\tlocal hook=\"${1}_hook${PI_HOOK_SPLICE:+_splice}\"\n\tlocal func=\"${2}\"\n\n\t[ -n \"$func\" ] && {\n\t\tlocal v; eval \"v=\\$$hook\"\n\t\texport -n \"$hook=${v:+$v }$func\"\n\t}\n}\n\nboot_hook_shift() {\n\tlocal hook=\"${1}_hook\"\n\tlocal rvar=\"${2}\"\n\n\tlocal v; eval \"v=\\$$hook\"\n\t[ -n \"$v\" ] && {\n\t\tlocal first=\"${v%% *}\"\n\n\t\t[ \"$v\" != \"${v#* }\" ] && \\\n\t\t\texport -n \"$hook=${v#* }\" || \\\n\t\t\texport -n \"$hook=\"\n\n\t\texport -n \"$rvar=$first\"\n\t\treturn 0\n\t}\n\n\treturn 1\n}\n\nboot_run_hook() {\n\tlocal hook=\"$1\"\n\tlocal func\n\n\twhile boot_hook_shift \"$hook\" func; do\n\t\tlocal ran; eval \"ran=\\$PI_RAN_$func\"\n\t\t[ -n \"$ran\" ] || {\n\t\t\texport -n \"PI_RAN_$func=1\"\n\t\t\t$func \"$1\" \"$2\"\n\t\t}\n\tdone\n}\n\npivot() { # <new_root> <old_root>\n\t/bin/mount -o noatime,move /proc $1/proc && \\\n\tpivot_root $1 $1$2 && {\n\t\t/bin/mount -o noatime,move $2/dev /dev\n\t\t/bin/mount -o noatime,move $2/tmp /tmp\n\t\t/bin/mount -o noatime,move $2/sys /sys 2>&-\n\t\t/bin/mount -o noatime,move $2/overlay /overlay 2>&-\n\t\treturn 0\n\t}\n}\n\nfopivot() { # <rw_root> <work_dir> <ro_root> <dupe?>\n\t/bin/mount -o noatime,lowerdir=/,upperdir=$1,workdir=$2 -t overlay \"overlayfs:$1\" /mnt\n\tpivot /mnt $3\n}\n\nramoverlay() {\n\tmkdir -p /tmp/root\n\t/bin/mount -t tmpfs -o noatime,mode=0755 root /tmp/root\n\tmkdir -p /tmp/root/root /tmp/root/work\n\tfopivot /tmp/root/root /tmp/root/work /rom 1\n}\n"
  },
  {
    "path": "package/base-files/files/lib/functions/service.sh",
    "content": "#\n# service: simple wrapper around start-stop-daemon\n#\n# Usage: service ACTION EXEC ARGS...\n#\n# Action:\n#   -C\tcheck if EXEC is alive\n#   -S\tstart EXEC, passing it ARGS as its arguments\n#   -K\tkill EXEC, sending it a TERM signal if not specified otherwise\n#\n# Environment variables exposed:\n#   SERVICE_DAEMONIZE\trun EXEC in background\n#   SERVICE_WRITE_PID\tcreate a pid-file and use it for matching\n#   SERVICE_MATCH_EXEC\tuse EXEC command-line for matching (default)\n#   SERVICE_MATCH_NAME\tuse EXEC process name for matching\n#   SERVICE_USE_PID\tassume EXEC create its own pid-file and use it for matching\n#   SERVICE_NAME\tprocess name to use (default to EXEC file part)\n#   SERVICE_PID_FILE\tpid file to use (default to /var/run/$SERVICE_NAME.pid)\n#   SERVICE_SIG\t\tsignal to send when using -K\n#   SERVICE_SIG_RELOAD\tdefault signal used when reloading\n#   SERVICE_SIG_STOP\tdefault signal used when stopping\n#   SERVICE_STOP_TIME\ttime to wait for a process to stop gracefully before killing it\n#   SERVICE_UID\t\tuser EXEC should be run as\n#   SERVICE_GID\t\tgroup EXEC should be run as\n#\n#   SERVICE_DEBUG\tdon't do anything, but show what would be done\n#   SERVICE_QUIET\tdon't print anything\n#\n\nSERVICE_QUIET=1\nSERVICE_SIG_RELOAD=\"HUP\"\nSERVICE_SIG_STOP=\"TERM\"\nSERVICE_STOP_TIME=5\nSERVICE_MATCH_EXEC=1\n\nservice() {\n\tlocal ssd\n\tlocal exec\n\tlocal name\n\tlocal start\n\tssd=\"${SERVICE_DEBUG:+echo }start-stop-daemon${SERVICE_QUIET:+ -q}\"\n\tcase \"$1\" in\n\t  -C)\n\t\tssd=\"$ssd -K -t\"\n\t\t;;\n\t  -S)\n\t\tssd=\"$ssd -S${SERVICE_DAEMONIZE:+ -b}${SERVICE_WRITE_PID:+ -m}\"\n\t\tstart=1\n\t\t;;\n\t  -K)\n\t\tssd=\"$ssd -K${SERVICE_SIG:+ -s $SERVICE_SIG}\"\n\t\t;;\n\t  *)\n\t\techo \"service: unknown ACTION '$1'\" 1>&2\n\t\treturn 1\n\tesac\n\tshift\n\texec=\"$1\"\n\t[ -n \"$exec\" ] || {\n\t\techo \"service: missing argument\" 1>&2\n\t\treturn 1\n\t}\n\t[ -x \"$exec\" ] || {\n\t\techo \"service: file '$exec' is not executable\" 1>&2\n\t\treturn 1\n\t}\n\tname=\"${SERVICE_NAME:-${exec##*/}}\"\n\t[ -z \"$SERVICE_USE_PID$SERVICE_WRITE_PID$SERVICE_PID_FILE\" ] \\\n\t\t|| ssd=\"$ssd -p ${SERVICE_PID_FILE:-/var/run/$name.pid}\"\n\t[ -z \"$SERVICE_MATCH_NAME\" ] || ssd=\"$ssd -n $name\"\n\tssd=\"$ssd${SERVICE_UID:+ -c $SERVICE_UID${SERVICE_GID:+:$SERVICE_GID}}\"\n\t[ -z \"$SERVICE_MATCH_EXEC$start\" ] || ssd=\"$ssd -x $exec\"\n\tshift\n\t$ssd${1:+ -- \"$@\"}\n}\n\nservice_check() {\n\tservice -C \"$@\"\n}\n\nservice_signal() {\n\tSERVICE_SIG=\"${SERVICE_SIG:-USR1}\" service -K \"$@\"\n}\n\nservice_start() {\n\tservice -S \"$@\"\n}\n\nservice_stop() {\n\tlocal try\n\tSERVICE_SIG=\"${SERVICE_SIG:-$SERVICE_SIG_STOP}\" service -K \"$@\" || return 1\n\twhile [ $((try++)) -lt $SERVICE_STOP_TIME ]; do\n\t\tservice -C \"$@\" || return 0\n\t\tsleep 1\n\tdone\n\tSERVICE_SIG=\"KILL\" service -K \"$@\"\n\tsleep 1\n\t! service -C \"$@\"\n}\n\nservice_reload() {\n\tSERVICE_SIG=\"${SERVICE_SIG:-$SERVICE_SIG_RELOAD}\" service -K \"$@\"\n}\n"
  },
  {
    "path": "package/base-files/files/lib/functions/system.sh",
    "content": "# Copyright (C) 2006-2013 OpenWrt.org\n\n. /lib/functions.sh\n. /usr/share/libubox/jshn.sh\n\nget_mac_binary() {\n\tlocal path=\"$1\"\n\tlocal offset=\"$2\"\n\n\tif ! [ -e \"$path\" ]; then\n\t\techo \"get_mac_binary: file $path not found!\" >&2\n\t\treturn\n\tfi\n\n\thexdump -v -n 6 -s $offset -e '5/1 \"%02x:\" 1/1 \"%02x\"' $path 2>/dev/null\n}\n\nget_mac_label_dt() {\n\tlocal basepath=\"/proc/device-tree\"\n\tlocal macdevice=\"$(cat \"$basepath/aliases/label-mac-device\" 2>/dev/null)\"\n\tlocal macaddr\n\n\t[ -n \"$macdevice\" ] || return\n\n\tmacaddr=$(get_mac_binary \"$basepath/$macdevice/mac-address\" 0 2>/dev/null)\n\t[ -n \"$macaddr\" ] || macaddr=$(get_mac_binary \"$basepath/$macdevice/local-mac-address\" 0 2>/dev/null)\n\n\techo $macaddr\n}\n\nget_mac_label_json() {\n\tlocal cfg=\"/etc/board.json\"\n\tlocal macaddr\n\n\t[ -s \"$cfg\" ] || return\n\n\tjson_init\n\tjson_load \"$(cat $cfg)\"\n\tif json_is_a system object; then\n\t\tjson_select system\n\t\t\tjson_get_var macaddr label_macaddr\n\t\tjson_select ..\n\tfi\n\n\techo $macaddr\n}\n\nget_mac_label() {\n\tlocal macaddr=$(get_mac_label_dt)\n\n\t[ -n \"$macaddr\" ] || macaddr=$(get_mac_label_json)\n\n\techo $macaddr\n}\n\nfind_mtd_chardev() {\n\tlocal INDEX=$(find_mtd_index \"$1\")\n\tlocal PREFIX=/dev/mtd\n\n\t[ -d /dev/mtd ] && PREFIX=/dev/mtd/\n\techo \"${INDEX:+$PREFIX$INDEX}\"\n}\n\nmtd_get_mac_ascii() {\n\tlocal mtdname=\"$1\"\n\tlocal key=\"$2\"\n\tlocal part\n\tlocal mac_dirty\n\n\tpart=$(find_mtd_part \"$mtdname\")\n\tif [ -z \"$part\" ]; then\n\t\techo \"mtd_get_mac_ascii: partition $mtdname not found!\" >&2\n\t\treturn\n\tfi\n\n\tmac_dirty=$(strings \"$part\" | sed -n 's/^'\"$key\"'=//p')\n\n\t# \"canonicalize\" mac\n\t[ -n \"$mac_dirty\" ] && macaddr_canonicalize \"$mac_dirty\"\n}\n\nmtd_get_mac_text() {\n\tlocal mtdname=$1\n\tlocal offset=$(($2))\n\tlocal part\n\tlocal mac_dirty\n\n\tpart=$(find_mtd_part \"$mtdname\")\n\tif [ -z \"$part\" ]; then\n\t\techo \"mtd_get_mac_text: partition $mtdname not found!\" >&2\n\t\treturn\n\tfi\n\n\tif [ -z \"$offset\" ]; then\n\t\techo \"mtd_get_mac_text: offset missing!\" >&2\n\t\treturn\n\tfi\n\n\tmac_dirty=$(dd if=\"$part\" bs=1 skip=\"$offset\" count=17 2>/dev/null)\n\n\t# \"canonicalize\" mac\n\t[ -n \"$mac_dirty\" ] && macaddr_canonicalize \"$mac_dirty\"\n}\n\nmtd_get_mac_binary() {\n\tlocal mtdname=\"$1\"\n\tlocal offset=\"$2\"\n\tlocal part\n\n\tpart=$(find_mtd_part \"$mtdname\")\n\tget_mac_binary \"$part\" \"$offset\"\n}\n\nmtd_get_mac_binary_ubi() {\n\tlocal mtdname=\"$1\"\n\tlocal offset=\"$2\"\n\n\t. /lib/upgrade/nand.sh\n\n\tlocal ubidev=$(nand_find_ubi $CI_UBIPART)\n\tlocal part=$(nand_find_volume $ubidev $1)\n\n\tget_mac_binary \"/dev/$part\" \"$offset\"\n}\n\nmtd_get_part_size() {\n\tlocal part_name=$1\n\tlocal first dev size erasesize name\n\twhile read dev size erasesize name; do\n\t\tname=${name#'\"'}; name=${name%'\"'}\n\t\tif [ \"$name\" = \"$part_name\" ]; then\n\t\t\techo $((0x$size))\n\t\t\tbreak\n\t\tfi\n\tdone < /proc/mtd\n}\n\nmmc_get_mac_binary() {\n\tlocal part_name=\"$1\"\n\tlocal offset=\"$2\"\n\tlocal part\n\n\tpart=$(find_mmc_part \"$part_name\")\n\tget_mac_binary \"$part\" \"$offset\"\n}\n\nmacaddr_add() {\n\tlocal mac=$1\n\tlocal val=$2\n\tlocal oui=${mac%:*:*:*}\n\tlocal nic=${mac#*:*:*:}\n\n\tnic=$(printf \"%06x\" $((0x${nic//:/} + val & 0xffffff)) | sed 's/^\\(.\\{2\\}\\)\\(.\\{2\\}\\)\\(.\\{2\\}\\)/\\1:\\2:\\3/')\n\techo $oui:$nic\n}\n\nmacaddr_geteui() {\n\tlocal mac=$1\n\tlocal sep=$2\n\n\techo ${mac:9:2}$sep${mac:12:2}$sep${mac:15:2}\n}\n\nmacaddr_setbit() {\n\tlocal mac=$1\n\tlocal bit=${2:-0}\n\n\t[ $bit -gt 0 -a $bit -le 48 ] || return\n\n\tprintf \"%012x\" $(( 0x${mac//:/} | 2**(48-bit) )) | sed -e 's/\\(.\\{2\\}\\)/\\1:/g' -e 's/:$//'\n}\n\nmacaddr_unsetbit() {\n\tlocal mac=$1\n\tlocal bit=${2:-0}\n\n\t[ $bit -gt 0 -a $bit -le 48 ] || return\n\n\tprintf \"%012x\" $(( 0x${mac//:/} & ~(2**(48-bit)) )) | sed -e 's/\\(.\\{2\\}\\)/\\1:/g' -e 's/:$//'\n}\n\nmacaddr_setbit_la() {\n\tmacaddr_setbit $1 7\n}\n\nmacaddr_unsetbit_mc() {\n\tlocal mac=$1\n\n\tprintf \"%02x:%s\" $((0x${mac%%:*} & ~0x01)) ${mac#*:}\n}\n\nmacaddr_random() {\n\tlocal randsrc=$(get_mac_binary /dev/urandom 0)\n\t\n\techo \"$(macaddr_unsetbit_mc \"$(macaddr_setbit_la \"${randsrc}\")\")\"\n}\n\nmacaddr_2bin() {\n\tlocal mac=$1\n\n\techo -ne \\\\x${mac//:/\\\\x}\n}\n\nmacaddr_canonicalize() {\n\tlocal mac=\"$1\"\n\tlocal canon=\"\"\n\n\tmac=$(echo -n $mac | tr -d \\\")\n\t[ ${#mac} -gt 17 ] && return\n\t[ -n \"${mac//[a-fA-F0-9\\.: -]/}\" ] && return\n\n\tfor octet in ${mac//[\\.:-]/ }; do\n\t\tcase \"${#octet}\" in\n\t\t1)\n\t\t\toctet=\"0${octet}\"\n\t\t\t;;\n\t\t2)\n\t\t\t;;\n\t\t4)\n\t\t\toctet=\"${octet:0:2} ${octet:2:2}\"\n\t\t\t;;\n\t\t12)\n\t\t\toctet=\"${octet:0:2} ${octet:2:2} ${octet:4:2} ${octet:6:2} ${octet:8:2} ${octet:10:2}\"\n\t\t\t;;\n\t\t*)\n\t\t\treturn\n\t\t\t;;\n\t\tesac\n\t\tcanon=${canon}${canon:+ }${octet}\n\tdone\n\n\t[ ${#canon} -ne 17 ] && return\n\n\tprintf \"%02x:%02x:%02x:%02x:%02x:%02x\" 0x${canon// / 0x} 2>/dev/null\n}\n"
  },
  {
    "path": "package/base-files/files/lib/functions/uci-defaults.sh",
    "content": ". /lib/functions.sh\n. /usr/share/libubox/jshn.sh\n\njson_select_array() {\n\tlocal _json_no_warning=1\n\n\tjson_select \"$1\"\n\t[ $? = 0 ] && return\n\n\tjson_add_array \"$1\"\n\tjson_close_array\n\n\tjson_select \"$1\"\n}\n\njson_select_object() {\n\tlocal _json_no_warning=1\n\n\tjson_select \"$1\"\n\t[ $? = 0 ] && return\n\n\tjson_add_object \"$1\"\n\tjson_close_object\n\n\tjson_select \"$1\"\n}\n\nucidef_set_interface() {\n\tlocal network=$1; shift\n\n\t[ -z \"$network\" ] && return\n\n\tjson_select_object network\n\tjson_select_object \"$network\"\n\n\twhile [ -n \"$1\" ]; do\n\t\tlocal opt=$1; shift\n\t\tlocal val=$1; shift\n\n\t\t[ -n \"$opt\" -a -n \"$val\" ] || break\n\n\t\t[ \"$opt\" = \"device\" -a \"$val\" != \"${val/ //}\" ] && {\n\t\t\tjson_select_array \"ports\"\n\t\t\tfor e in $val; do json_add_string \"\" \"$e\"; done\n\t\t\tjson_close_array\n\t\t} || {\n\t\t\tjson_add_string \"$opt\" \"$val\"\n\t\t}\n\tdone\n\n\tif ! json_is_a protocol string; then\n\t\tcase \"$network\" in\n\t\t\tlan) json_add_string protocol static ;;\n\t\t\twan) json_add_string protocol dhcp ;;\n\t\t\t*) json_add_string protocol none ;;\n\t\tesac\n\tfi\n\n\tjson_select ..\n\tjson_select ..\n}\n\nucidef_set_board_id() {\n\tjson_select_object model\n\tjson_add_string id \"$1\"\n\tjson_select ..\n}\n\nucidef_set_model_name() {\n\tjson_select_object model\n\tjson_add_string name \"$1\"\n\tjson_select ..\n}\n\nucidef_set_compat_version() {\n\tjson_select_object system\n\tjson_add_string compat_version \"${1:-1.0}\"\n\tjson_select ..\n}\n\nucidef_set_interface_lan() {\n\tucidef_set_interface \"lan\" device \"$1\" protocol \"${2:-static}\"\n}\n\nucidef_set_interface_wan() {\n\tucidef_set_interface \"wan\" device \"$1\" protocol \"${2:-dhcp}\"\n}\n\nucidef_set_interfaces_lan_wan() {\n\tlocal lan_if=\"$1\"\n\tlocal wan_if=\"$2\"\n\n\tucidef_set_interface_lan \"$lan_if\"\n\tucidef_set_interface_wan \"$wan_if\"\n}\n\nucidef_set_bridge_device() {\n\tjson_select_object bridge\n\tjson_add_string name \"${1:switch0}\"\n\tjson_select ..\n}\n\nucidef_set_bridge_mac() {\n\tjson_select_object bridge\n\tjson_add_string macaddr \"${1}\"\n\tjson_select ..\n}\n\nucidef_set_network_device_mac() {\n\tjson_select_object \"network-device\"\n\tjson_select_object \"${1}\"\n\tjson_add_string macaddr \"${2}\"\n\tjson_select ..\n\tjson_select ..\n}\n\n_ucidef_add_switch_port() {\n\t# inherited: $num $device $need_tag $want_untag $role $index $prev_role\n\t# inherited: $n_cpu $n_ports $n_vlan $cpu0 $cpu1 $cpu2 $cpu3 $cpu4 $cpu5\n\n\tn_ports=$((n_ports + 1))\n\n\tjson_select_array ports\n\t\tjson_add_object\n\t\t\tjson_add_int num \"$num\"\n\t\t\t[ -n \"$device\"     ] && json_add_string  device     \"$device\"\n\t\t\t[ -n \"$need_tag\"   ] && json_add_boolean need_tag   \"$need_tag\"\n\t\t\t[ -n \"$want_untag\" ] && json_add_boolean want_untag \"$want_untag\"\n\t\t\t[ -n \"$role\"       ] && json_add_string  role       \"$role\"\n\t\t\t[ -n \"$index\"      ] && json_add_int     index      \"$index\"\n\t\tjson_close_object\n\tjson_select ..\n\n\t# record pointer to cpu entry for lookup in _ucidef_finish_switch_roles()\n\t[ -n \"$device\" ] && {\n\t\texport \"cpu$n_cpu=$n_ports\"\n\t\tn_cpu=$((n_cpu + 1))\n\t}\n\n\t# create/append object to role list\n\t[ -n \"$role\" ] && {\n\t\tjson_select_array roles\n\n\t\tif [ \"$role\" != \"$prev_role\" ]; then\n\t\t\tjson_add_object\n\t\t\t\tjson_add_string role \"$role\"\n\t\t\t\tjson_add_string ports \"$num\"\n\t\t\tjson_close_object\n\n\t\t\tprev_role=\"$role\"\n\t\t\tn_vlan=$((n_vlan + 1))\n\t\telse\n\t\t\tjson_select_object \"$n_vlan\"\n\t\t\t\tjson_get_var port ports\n\t\t\t\tjson_add_string ports \"$port $num\"\n\t\t\tjson_select ..\n\t\tfi\n\n\t\tjson_select ..\n\t}\n}\n\n_ucidef_finish_switch_roles() {\n\t# inherited: $name $n_cpu $n_vlan $cpu0 $cpu1 $cpu2 $cpu3 $cpu4 $cpu5\n\tlocal index role roles num device need_tag want_untag port ports\n\n\tjson_select switch\n\t\tjson_select \"$name\"\n\t\t\tjson_get_keys roles roles\n\t\tjson_select ..\n\tjson_select ..\n\n\tfor index in $roles; do\n\t\teval \"port=\\$cpu$(((index - 1) % n_cpu))\"\n\n\t\tjson_select switch\n\t\t\tjson_select \"$name\"\n\t\t\t\tjson_select ports\n\t\t\t\t\tjson_select \"$port\"\n\t\t\t\t\t\tjson_get_vars num device need_tag want_untag\n\t\t\t\t\tjson_select ..\n\t\t\t\tjson_select ..\n\n\t\t\t\tif [ ${need_tag:-0} -eq 1 -o ${want_untag:-0} -ne 1 ]; then\n\t\t\t\t\tnum=\"${num}t\"\n\t\t\t\t\tdevice=\"${device}.${index}\"\n\t\t\t\tfi\n\n\t\t\t\tjson_select roles\n\t\t\t\t\tjson_select \"$index\"\n\t\t\t\t\t\tjson_get_vars role ports\n\t\t\t\t\t\tjson_add_string ports \"$ports $num\"\n\t\t\t\t\t\tjson_add_string device \"$device\"\n\t\t\t\t\tjson_select ..\n\t\t\t\tjson_select ..\n\t\t\tjson_select ..\n\t\tjson_select ..\n\n\t\tjson_select_object network\n\t\t\tlocal devices\n\n\t\t\tjson_select_object \"$role\"\n\t\t\t\t# attach previous interfaces (for multi-switch devices)\n\t\t\t\tjson_get_var devices device\n\t\t\t\tif ! list_contains devices \"$device\"; then\n\t\t\t\t\tdevices=\"${devices:+$devices }$device\"\n\t\t\t\tfi\n\t\t\tjson_select ..\n\t\tjson_select ..\n\n\t\tucidef_set_interface \"$role\" device \"$devices\"\n\tdone\n}\n\nucidef_set_ar8xxx_switch_mib() {\n\tlocal name=\"$1\"\n\tlocal type=\"$2\"\n\tlocal interval=\"$3\"\n\n\tjson_select_object switch\n\t\tjson_select_object \"$name\"\n\t\t\tjson_add_int ar8xxx_mib_type $type\n\t\t\tjson_add_int ar8xxx_mib_poll_interval $interval\n\t\tjson_select ..\n\tjson_select ..\n}\n\nucidef_add_switch() {\n\tlocal name=\"$1\"; shift\n\tlocal port num role device index need_tag prev_role\n\tlocal cpu0 cpu1 cpu2 cpu3 cpu4 cpu5\n\tlocal n_cpu=0 n_vlan=0 n_ports=0\n\n\tjson_select_object switch\n\t\tjson_select_object \"$name\"\n\t\t\tjson_add_boolean enable 1\n\t\t\tjson_add_boolean reset 1\n\n\t\t\tfor port in \"$@\"; do\n\t\t\t\tcase \"$port\" in\n\t\t\t\t\t[0-9]*@*)\n\t\t\t\t\t\tnum=\"${port%%@*}\"\n\t\t\t\t\t\tdevice=\"${port##*@}\"\n\t\t\t\t\t\tneed_tag=0\n\t\t\t\t\t\twant_untag=0\n\t\t\t\t\t\t[ \"${num%t}\" != \"$num\" ] && {\n\t\t\t\t\t\t\tnum=\"${num%t}\"\n\t\t\t\t\t\t\tneed_tag=1\n\t\t\t\t\t\t}\n\t\t\t\t\t\t[ \"${num%u}\" != \"$num\" ] && {\n\t\t\t\t\t\t\tnum=\"${num%u}\"\n\t\t\t\t\t\t\twant_untag=1\n\t\t\t\t\t\t}\n\t\t\t\t\t;;\n\t\t\t\t\t[0-9]*:*:[0-9]*)\n\t\t\t\t\t\tnum=\"${port%%:*}\"\n\t\t\t\t\t\tindex=\"${port##*:}\"\n\t\t\t\t\t\trole=\"${port#[0-9]*:}\"; role=\"${role%:*}\"\n\t\t\t\t\t;;\n\t\t\t\t\t[0-9]*:*)\n\t\t\t\t\t\tnum=\"${port%%:*}\"\n\t\t\t\t\t\trole=\"${port##*:}\"\n\t\t\t\t\t;;\n\t\t\t\tesac\n\n\t\t\t\tif [ -n \"$num\" ] && [ -n \"$device$role\" ]; then\n\t\t\t\t\t_ucidef_add_switch_port\n\t\t\t\tfi\n\n\t\t\t\tunset num device role index need_tag want_untag\n\t\t\tdone\n\t\tjson_select ..\n\tjson_select ..\n\n\t_ucidef_finish_switch_roles\n}\n\nucidef_add_switch_attr() {\n\tlocal name=\"$1\"\n\tlocal key=\"$2\"\n\tlocal val=\"$3\"\n\n\tjson_select_object switch\n\t\tjson_select_object \"$name\"\n\n\t\tcase \"$val\" in\n\t\t\ttrue|false) [ \"$val\" != \"true\" ]; json_add_boolean \"$key\" $? ;;\n\t\t\t[0-9]) json_add_int \"$key\" \"$val\" ;;\n\t\t\t*) json_add_string \"$key\" \"$val\" ;;\n\t\tesac\n\n\t\tjson_select ..\n\tjson_select ..\n}\n\nucidef_add_switch_port_attr() {\n\tlocal name=\"$1\"\n\tlocal port=\"$2\"\n\tlocal key=\"$3\"\n\tlocal val=\"$4\"\n\tlocal ports i num\n\n\tjson_select_object switch\n\tjson_select_object \"$name\"\n\n\tjson_get_keys ports ports\n\tjson_select_array ports\n\n\tfor i in $ports; do\n\t\tjson_select \"$i\"\n\t\tjson_get_var num num\n\n\t\tif [ -n \"$num\" ] && [ $num -eq $port ]; then\n\t\t\tjson_select_object attr\n\n\t\t\tcase \"$val\" in\n\t\t\t\ttrue|false) [ \"$val\" != \"true\" ]; json_add_boolean \"$key\" $? ;;\n\t\t\t\t[0-9]) json_add_int \"$key\" \"$val\" ;;\n\t\t\t\t*) json_add_string \"$key\" \"$val\" ;;\n\t\t\tesac\n\n\t\t\tjson_select ..\n\t\tfi\n\n\t\tjson_select ..\n\tdone\n\n\tjson_select ..\n\tjson_select ..\n\tjson_select ..\n}\n\nucidef_set_interface_macaddr() {\n\tlocal network=\"$1\"\n\tlocal macaddr=\"$2\"\n\n\tucidef_set_interface \"$network\" macaddr \"$macaddr\"\n}\n\nucidef_set_label_macaddr() {\n\tlocal macaddr=\"$1\"\n\n\tjson_select_object system\n\t\tjson_add_string label_macaddr \"$macaddr\"\n\tjson_select ..\n}\n\nucidef_add_atm_bridge() {\n\tlocal vpi=\"$1\"\n\tlocal vci=\"$2\"\n\tlocal encaps=\"$3\"\n\tlocal payload=\"$4\"\n\tlocal nameprefix=\"$5\"\n\n\tjson_select_object dsl\n\t\tjson_select_object atmbridge\n\t\t\tjson_add_int vpi \"$vpi\"\n\t\t\tjson_add_int vci \"$vci\"\n\t\t\tjson_add_string encaps \"$encaps\"\n\t\t\tjson_add_string payload \"$payload\"\n\t\t\tjson_add_string nameprefix \"$nameprefix\"\n\t\tjson_select ..\n\tjson_select ..\n}\n\nucidef_add_adsl_modem() {\n\tlocal annex=\"$1\"\n\tlocal firmware=\"$2\"\n\n\tjson_select_object dsl\n\t\tjson_select_object modem\n\t\t\tjson_add_string type \"adsl\"\n\t\t\tjson_add_string annex \"$annex\"\n\t\t\tjson_add_string firmware \"$firmware\"\n\t\tjson_select ..\n\tjson_select ..\n}\n\nucidef_add_vdsl_modem() {\n\tlocal annex=\"$1\"\n\tlocal tone=\"$2\"\n\tlocal xfer_mode=\"$3\"\n\n\tjson_select_object dsl\n\t\tjson_select_object modem\n\t\t\tjson_add_string type \"vdsl\"\n\t\t\tjson_add_string annex \"$annex\"\n\t\t\tjson_add_string tone \"$tone\"\n\t\t\tjson_add_string xfer_mode \"$xfer_mode\"\n\t\tjson_select ..\n\tjson_select ..\n}\n\nucidef_set_led_ataport() {\n\t_ucidef_set_led_trigger \"$1\" \"$2\" \"$3\" ata\"$4\"\n}\n\n_ucidef_set_led_common() {\n\tlocal cfg=\"led_$1\"\n\tlocal name=\"$2\"\n\tlocal sysfs=\"$3\"\n\n\tjson_select_object led\n\n\tjson_select_object \"$1\"\n\tjson_add_string name \"$name\"\n\tjson_add_string sysfs \"$sysfs\"\n}\n\nucidef_set_led_default() {\n\tlocal default=\"$4\"\n\n\t_ucidef_set_led_common \"$1\" \"$2\" \"$3\"\n\n\tjson_add_string default \"$default\"\n\tjson_select ..\n\n\tjson_select ..\n}\n\nucidef_set_led_heartbeat() {\n\t_ucidef_set_led_common \"$1\" \"$2\" \"$3\"\n\n\tjson_add_string trigger heartbeat\n\tjson_select ..\n\n\tjson_select ..\n}\n\nucidef_set_led_gpio() {\n\tlocal gpio=\"$4\"\n\tlocal inverted=\"$5\"\n\n\t_ucidef_set_led_common \"$1\" \"$2\" \"$3\"\n\n\tjson_add_string trigger \"$trigger\"\n\tjson_add_string type gpio\n\tjson_add_int gpio \"$gpio\"\n\tjson_add_boolean inverted \"$inverted\"\n\tjson_select ..\n\n\tjson_select ..\n}\n\nucidef_set_led_ide() {\n\t_ucidef_set_led_trigger \"$1\" \"$2\" \"$3\" disk-activity\n}\n\nucidef_set_led_netdev() {\n\tlocal dev=\"$4\"\n\tlocal mode=\"${5:-link tx rx}\"\n\n\t_ucidef_set_led_common \"$1\" \"$2\" \"$3\"\n\n\tjson_add_string type netdev\n\tjson_add_string device \"$dev\"\n\tjson_add_string mode \"$mode\"\n\tjson_select ..\n\n\tjson_select ..\n}\n\nucidef_set_led_oneshot() {\n\t_ucidef_set_led_timer $1 $2 $3 \"oneshot\" $4 $5\n}\n\nucidef_set_led_portstate() {\n\tlocal port_state=\"$4\"\n\n\t_ucidef_set_led_common \"$1\" \"$2\" \"$3\"\n\n\tjson_add_string trigger port_state\n\tjson_add_string type portstate\n\tjson_add_string port_state \"$port_state\"\n\tjson_select ..\n\n\tjson_select ..\n}\n\nucidef_set_led_rssi() {\n\tlocal iface=\"$4\"\n\tlocal minq=\"$5\"\n\tlocal maxq=\"$6\"\n\tlocal offset=\"${7:-0}\"\n\tlocal factor=\"${8:-1}\"\n\n\t_ucidef_set_led_common \"$1\" \"$2\" \"$3\"\n\n\tjson_add_string type rssi\n\tjson_add_string name \"$name\"\n\tjson_add_string iface \"$iface\"\n\tjson_add_string minq \"$minq\"\n\tjson_add_string maxq \"$maxq\"\n\tjson_add_string offset \"$offset\"\n\tjson_add_string factor \"$factor\"\n\tjson_select ..\n\n\tjson_select ..\n}\n\nucidef_set_led_switch() {\n\tlocal trigger_name=\"$4\"\n\tlocal port_mask=\"$5\"\n\tlocal speed_mask=\"$6\"\n\tlocal mode=\"$7\"\n\n\t_ucidef_set_led_common \"$1\" \"$2\" \"$3\"\n\n\tjson_add_string trigger \"$trigger_name\"\n\tjson_add_string type switch\n\tjson_add_string mode \"$mode\"\n\tjson_add_string port_mask \"$port_mask\"\n\tjson_add_string speed_mask \"$speed_mask\"\n\tjson_select ..\n\n\tjson_select ..\n}\n\n_ucidef_set_led_timer() {\n\tlocal trigger_name=\"$4\"\n\tlocal delayon=\"$5\"\n\tlocal delayoff=\"$6\"\n\n\t_ucidef_set_led_common \"$1\" \"$2\" \"$3\"\n\n\tjson_add_string type \"$trigger_name\"\n\tjson_add_string trigger \"$trigger_name\"\n\tjson_add_int delayon \"$delayon\"\n\tjson_add_int delayoff \"$delayoff\"\n\tjson_select ..\n\n\tjson_select ..\n}\n\nucidef_set_led_timer() {\n\t_ucidef_set_led_timer $1 $2 $3 \"timer\" $4 $5\n}\n\n_ucidef_set_led_trigger() {\n\tlocal trigger_name=\"$4\"\n\n\t_ucidef_set_led_common \"$1\" \"$2\" \"$3\"\n\n\tjson_add_string trigger \"$trigger_name\"\n\tjson_select ..\n\n\tjson_select ..\n}\n\nucidef_set_led_usbdev() {\n\tlocal dev=\"$4\"\n\n\t_ucidef_set_led_common \"$1\" \"$2\" \"$3\"\n\n\tjson_add_string type usb\n\tjson_add_string device \"$dev\"\n\tjson_select ..\n\n\tjson_select ..\n}\n\nucidef_set_led_usbhost() {\n\t_ucidef_set_led_trigger \"$1\" \"$2\" \"$3\" usb-host\n}\n\nucidef_set_led_usbport() {\n\tlocal obj=\"$1\"\n\tlocal name=\"$2\"\n\tlocal sysfs=\"$3\"\n\tshift\n\tshift\n\tshift\n\n\t_ucidef_set_led_common \"$obj\" \"$name\" \"$sysfs\"\n\n\tjson_add_string type usbport\n\tjson_select_array ports\n\t\tfor port in \"$@\"; do\n\t\t\tjson_add_string port \"$port\"\n\t\tdone\n\tjson_select ..\n\tjson_select ..\n\n\tjson_select ..\n}\n\nucidef_set_led_wlan() {\n\t_ucidef_set_led_trigger \"$1\" \"$2\" \"$3\" \"$4\"\n}\n\nucidef_set_rssimon() {\n\tlocal dev=\"$1\"\n\tlocal refresh=\"$2\"\n\tlocal threshold=\"$3\"\n\n\tjson_select_object rssimon\n\n\tjson_select_object \"$dev\"\n\t[ -n \"$refresh\" ] && json_add_int refresh \"$refresh\"\n\t[ -n \"$threshold\" ] && json_add_int threshold \"$threshold\"\n\tjson_select ..\n\n\tjson_select ..\n}\n\nucidef_add_gpio_switch() {\n\tlocal cfg=\"$1\"\n\tlocal name=\"$2\"\n\tlocal pin=\"$3\"\n\tlocal default=\"${4:-0}\"\n\n\tjson_select_object gpioswitch\n\t\tjson_select_object \"$cfg\"\n\t\t\tjson_add_string name \"$name\"\n\t\t\tjson_add_string pin \"$pin\"\n\t\t\tjson_add_int default \"$default\"\n\t\tjson_select ..\n\tjson_select ..\n}\n\nucidef_set_hostname() {\n\tlocal hostname=\"$1\"\n\n\tjson_select_object system\n\t\tjson_add_string hostname \"$hostname\"\n\tjson_select ..\n}\n\nucidef_set_ntpserver() {\n\tlocal server\n\n\tjson_select_object system\n\t\tjson_select_array ntpserver\n\t\t\tfor server in \"$@\"; do\n\t\t\t\tjson_add_string \"\" \"$server\"\n\t\t\tdone\n\t\tjson_select ..\n\tjson_select ..\n}\n\nboard_config_update() {\n\tjson_init\n\t[ -f ${CFG} ] && json_load \"$(cat ${CFG})\"\n\n\t# auto-initialize model id and name if applicable\n\tif ! json_is_a model object; then\n\t\tjson_select_object model\n\t\t\t[ -f \"/tmp/sysinfo/board_name\" ] && \\\n\t\t\t\tjson_add_string id \"$(cat /tmp/sysinfo/board_name)\"\n\t\t\t[ -f \"/tmp/sysinfo/model\" ] && \\\n\t\t\t\tjson_add_string name \"$(cat /tmp/sysinfo/model)\"\n\t\tjson_select ..\n\tfi\n}\n\nboard_config_flush() {\n\tjson_dump -i -o ${CFG}\n}\n"
  },
  {
    "path": "package/base-files/files/lib/functions.sh",
    "content": "# Copyright (C) 2006-2014 OpenWrt.org\n# Copyright (C) 2006 Fokus Fraunhofer <carsten.tittel@fokus.fraunhofer.de>\n# Copyright (C) 2010 Vertical Communications\n\n\ndebug () {\n\t${DEBUG:-:} \"$@\"\n}\n\n# newline\nN=\"\n\"\n\n_C=0\nNO_EXPORT=1\nLOAD_STATE=1\nLIST_SEP=\" \"\n\n# xor multiple hex values of the same length\nxor() {\n\tlocal val\n\tlocal ret=\"0x$1\"\n\tlocal retlen=${#1}\n\n\tshift\n\twhile [ -n \"$1\" ]; do\n\t\tval=\"0x$1\"\n\t\tret=$((ret ^ val))\n\t\tshift\n\tdone\n\n\tprintf \"%0${retlen}x\" \"$ret\"\n}\n\nappend() {\n\tlocal var=\"$1\"\n\tlocal value=\"$2\"\n\tlocal sep=\"${3:- }\"\n\n\teval \"export ${NO_EXPORT:+-n} -- \\\"$var=\\${$var:+\\${$var}\\${value:+\\$sep}}\\$value\\\"\"\n}\n\nlist_contains() {\n\tlocal var=\"$1\"\n\tlocal str=\"$2\"\n\tlocal val\n\n\teval \"val=\\\" \\${$var} \\\"\"\n\t[ \"${val%% $str *}\" != \"$val\" ]\n}\n\nconfig_load() {\n\t[ -n \"$IPKG_INSTROOT\" ] && return 0\n\tuci_load \"$@\"\n}\n\nreset_cb() {\n\tconfig_cb() { return 0; }\n\toption_cb() { return 0; }\n\tlist_cb() { return 0; }\n}\nreset_cb\n\npackage() {\n\treturn 0\n}\n\nconfig () {\n\tlocal cfgtype=\"$1\"\n\tlocal name=\"$2\"\n\n\texport ${NO_EXPORT:+-n} CONFIG_NUM_SECTIONS=$((CONFIG_NUM_SECTIONS + 1))\n\tname=\"${name:-cfg$CONFIG_NUM_SECTIONS}\"\n\tappend CONFIG_SECTIONS \"$name\"\n\texport ${NO_EXPORT:+-n} CONFIG_SECTION=\"$name\"\n\tconfig_set \"$CONFIG_SECTION\" \"TYPE\" \"${cfgtype}\"\n\t[ -n \"$NO_CALLBACK\" ] || config_cb \"$cfgtype\" \"$name\"\n}\n\noption () {\n\tlocal varname=\"$1\"; shift\n\tlocal value=\"$*\"\n\n\tconfig_set \"$CONFIG_SECTION\" \"${varname}\" \"${value}\"\n\t[ -n \"$NO_CALLBACK\" ] || option_cb \"$varname\" \"$*\"\n}\n\nlist() {\n\tlocal varname=\"$1\"; shift\n\tlocal value=\"$*\"\n\tlocal len\n\n\tconfig_get len \"$CONFIG_SECTION\" \"${varname}_LENGTH\" 0\n\t[ $len = 0 ] && append CONFIG_LIST_STATE \"${CONFIG_SECTION}_${varname}\"\n\tlen=$((len + 1))\n\tconfig_set \"$CONFIG_SECTION\" \"${varname}_ITEM$len\" \"$value\"\n\tconfig_set \"$CONFIG_SECTION\" \"${varname}_LENGTH\" \"$len\"\n\tappend \"CONFIG_${CONFIG_SECTION}_${varname}\" \"$value\" \"$LIST_SEP\"\n\t[ -n \"$NO_CALLBACK\" ] || list_cb \"$varname\" \"$*\"\n}\n\nconfig_unset() {\n\tconfig_set \"$1\" \"$2\" \"\"\n}\n\n# config_get <variable> <section> <option> [<default>]\n# config_get <section> <option>\nconfig_get() {\n\tcase \"$2${3:-$1}\" in\n\t\t*[!A-Za-z0-9_]*) : ;;\n\t\t*)\n\t\t\tcase \"$3\" in\n\t\t\t\t\"\") eval echo \"\\\"\\${CONFIG_${1}_${2}:-\\${4}}\\\"\";;\n\t\t\t\t*)  eval export ${NO_EXPORT:+-n} -- \"${1}=\\${CONFIG_${2}_${3}:-\\${4}}\";;\n\t\t\tesac\n\t\t;;\n\tesac\n}\n\n# get_bool <value> [<default>]\nget_bool() {\n\tlocal _tmp=\"$1\"\n\tcase \"$_tmp\" in\n\t\t1|on|true|yes|enabled) _tmp=1;;\n\t\t0|off|false|no|disabled) _tmp=0;;\n\t\t*) _tmp=\"$2\";;\n\tesac\n\techo -n \"$_tmp\"\n}\n\n# config_get_bool <variable> <section> <option> [<default>]\nconfig_get_bool() {\n\tlocal _tmp\n\tconfig_get _tmp \"$2\" \"$3\" \"$4\"\n\t_tmp=\"$(get_bool \"$_tmp\" \"$4\")\"\n\texport ${NO_EXPORT:+-n} \"$1=$_tmp\"\n}\n\nconfig_set() {\n\tlocal section=\"$1\"\n\tlocal option=\"$2\"\n\tlocal value=\"$3\"\n\n\texport ${NO_EXPORT:+-n} \"CONFIG_${section}_${option}=${value}\"\n}\n\nconfig_foreach() {\n\tlocal ___function=\"$1\"\n\t[ \"$#\" -ge 1 ] && shift\n\tlocal ___type=\"$1\"\n\t[ \"$#\" -ge 1 ] && shift\n\tlocal section cfgtype\n\n\t[ -z \"$CONFIG_SECTIONS\" ] && return 0\n\tfor section in ${CONFIG_SECTIONS}; do\n\t\tconfig_get cfgtype \"$section\" TYPE\n\t\t[ -n \"$___type\" ] && [ \"x$cfgtype\" != \"x$___type\" ] && continue\n\t\teval \"$___function \\\"\\$section\\\" \\\"\\$@\\\"\"\n\tdone\n}\n\nconfig_list_foreach() {\n\t[ \"$#\" -ge 3 ] || return 0\n\tlocal section=\"$1\"; shift\n\tlocal option=\"$1\"; shift\n\tlocal function=\"$1\"; shift\n\tlocal val\n\tlocal len\n\tlocal c=1\n\n\tconfig_get len \"${section}\" \"${option}_LENGTH\"\n\t[ -z \"$len\" ] && return 0\n\twhile [ $c -le \"$len\" ]; do\n\t\tconfig_get val \"${section}\" \"${option}_ITEM$c\"\n\t\teval \"$function \\\"\\$val\\\" \\\"\\$@\\\"\"\n\t\tc=\"$((c + 1))\"\n\tdone\n}\n\ndefault_prerm() {\n\tlocal root=\"${IPKG_INSTROOT}\"\n\tlocal pkgname=\"$(basename ${1%.*})\"\n\tlocal ret=0\n\n\tif [ -f \"$root/usr/lib/opkg/info/${pkgname}.prerm-pkg\" ]; then\n\t\t( . \"$root/usr/lib/opkg/info/${pkgname}.prerm-pkg\" )\n\t\tret=$?\n\tfi\n\n\tlocal shell=\"$(command -v bash)\"\n\tfor i in $(grep -s \"^/etc/init.d/\" \"$root/usr/lib/opkg/info/${pkgname}.list\"); do\n\t\tif [ -n \"$root\" ]; then\n\t\t\t${shell:-/bin/sh} \"$root/etc/rc.common\" \"$root$i\" disable\n\t\telse\n\t\t\tif [ \"$PKG_UPGRADE\" != \"1\" ]; then\n\t\t\t\t\"$i\" disable\n\t\t\tfi\n\t\t\t\"$i\" stop\n\t\tfi\n\tdone\n\n\treturn $ret\n}\n\nadd_group_and_user() {\n\tlocal pkgname=\"$1\"\n\tlocal rusers=\"$(sed -ne 's/^Require-User: *//p' $root/usr/lib/opkg/info/${pkgname}.control 2>/dev/null)\"\n\n\tif [ -n \"$rusers\" ]; then\n\t\tlocal tuple oIFS=\"$IFS\"\n\t\tfor tuple in $rusers; do\n\t\t\tlocal uid gid uname gname addngroups addngroup addngname addngid\n\n\t\t\tIFS=\":\"\n\t\t\tset -- $tuple; uname=\"$1\"; gname=\"$2\"; addngroups=\"$3\"\n\t\t\tIFS=\"=\"\n\t\t\tset -- $uname; uname=\"$1\"; uid=\"$2\"\n\t\t\tset -- $gname; gname=\"$1\"; gid=\"$2\"\n\t\t\tIFS=\"$oIFS\"\n\n\t\t\tif [ -n \"$gname\" ] && [ -n \"$gid\" ]; then\n\t\t\t\tgroup_exists \"$gname\" || group_add \"$gname\" \"$gid\"\n\t\t\telif [ -n \"$gname\" ]; then\n\t\t\t\tgid=\"$(group_add_next \"$gname\")\"\n\t\t\tfi\n\n\t\t\tif [ -n \"$uname\" ]; then\n\t\t\t\tuser_exists \"$uname\" || user_add \"$uname\" \"$uid\" \"$gid\"\n\t\t\tfi\n\n\t\t\tif [ -n \"$uname\" ] && [ -n \"$gname\" ]; then\n\t\t\t\tgroup_add_user \"$gname\" \"$uname\"\n\t\t\tfi\n\n\t\t\tif [ -n \"$uname\" ] &&  [ -n \"$addngroups\" ]; then\n\t\t\t\toIFS=\"$IFS\"\n\t\t\t\tIFS=\",\"\n\t\t\t\tfor addngroup in $addngroups ; do\n\t\t\t\t\tIFS=\"=\"\n\t\t\t\t\tset -- $addngroup; addngname=\"$1\"; addngid=\"$2\"\n\t\t\t\t\tif [ -n \"$addngid\" ]; then\n\t\t\t\t\t\tgroup_exists \"$addngname\" || group_add \"$addngname\" \"$addngid\"\n\t\t\t\t\telse\n\t\t\t\t\t\tgroup_add_next \"$addngname\"\n\t\t\t\t\tfi\n\n\t\t\t\t\tgroup_add_user \"$addngname\" \"$uname\"\n\t\t\t\tdone\n\t\t\t\tIFS=\"$oIFS\"\n\t\t\tfi\n\n\t\t\tunset uid gid uname gname addngroups addngroup addngname addngid\n\t\tdone\n\tfi\n}\n\ndefault_postinst() {\n\tlocal root=\"${IPKG_INSTROOT}\"\n\tlocal pkgname=\"$(basename ${1%.*})\"\n\tlocal filelist=\"/usr/lib/opkg/info/${pkgname}.list\"\n\tlocal ret=0\n\n\tadd_group_and_user \"${pkgname}\"\n\n\tif [ -f \"$root/usr/lib/opkg/info/${pkgname}.postinst-pkg\" ]; then\n\t\t( . \"$root/usr/lib/opkg/info/${pkgname}.postinst-pkg\" )\n\t\tret=$?\n\tfi\n\n\tif [ -d \"$root/rootfs-overlay\" ]; then\n\t\tcp -R $root/rootfs-overlay/. $root/\n\t\trm -fR $root/rootfs-overlay/\n\tfi\n\n\tif [ -z \"$root\" ]; then\n\t\tif grep -m1 -q -s \"^/etc/modules.d/\" \"$filelist\"; then\n\t\t\tkmodloader\n\t\tfi\n\n\t\tif grep -m1 -q -s \"^/etc/sysctl.d/\" \"$filelist\"; then\n\t\t\t/etc/init.d/sysctl restart\n\t\tfi\n\n\t\tif grep -m1 -q -s \"^/etc/uci-defaults/\" \"$filelist\"; then\n\t\t\t[ -d /tmp/.uci ] || mkdir -p /tmp/.uci\n\t\t\tfor i in $(grep -s \"^/etc/uci-defaults/\" \"$filelist\"); do\n\t\t\t\t( [ -f \"$i\" ] && cd \"$(dirname $i)\" && . \"$i\" ) && rm -f \"$i\"\n\t\t\tdone\n\t\t\tuci commit\n\t\tfi\n\n\t\trm -f /tmp/luci-indexcache\n\tfi\n\n\tlocal shell=\"$(command -v bash)\"\n\tfor i in $(grep -s \"^/etc/init.d/\" \"$root$filelist\"); do\n\t\tif [ -n \"$root\" ]; then\n\t\t\t${shell:-/bin/sh} \"$root/etc/rc.common\" \"$root$i\" enable\n\t\telse\n\t\t\tif [ \"$PKG_UPGRADE\" != \"1\" ]; then\n\t\t\t\t\"$i\" enable\n\t\t\tfi\n\t\t\t\"$i\" start\n\t\tfi\n\tdone\n\n\treturn $ret\n}\n\ninclude() {\n\tlocal file\n\n\tfor file in $(ls $1/*.sh 2>/dev/null); do\n\t\t. $file\n\tdone\n}\n\nfind_mtd_index() {\n\tlocal PART=\"$(grep \"\\\"$1\\\"\" /proc/mtd | awk -F: '{print $1}')\"\n\tlocal INDEX=\"${PART##mtd}\"\n\n\techo ${INDEX}\n}\n\nfind_mtd_part() {\n\tlocal INDEX=$(find_mtd_index \"$1\")\n\tlocal PREFIX=/dev/mtdblock\n\n\t[ -d /dev/mtdblock ] && PREFIX=/dev/mtdblock/\n\techo \"${INDEX:+$PREFIX$INDEX}\"\n}\n\nfind_mmc_part() {\n\tlocal DEVNAME PARTNAME ROOTDEV\n\n\tif grep -q \"$1\" /proc/mtd; then\n\t\techo \"\" && return 0\n\tfi\n\n\tif [ -n \"$2\" ]; then\n\t\tROOTDEV=\"$2\"\n\telse\n\t\tROOTDEV=\"mmcblk*\"\n\tfi\n\n\tfor DEVNAME in /sys/block/$ROOTDEV/mmcblk*p*; do\n\t\tPARTNAME=\"$(grep PARTNAME ${DEVNAME}/uevent | cut -f2 -d'=')\"\n\t\t[ \"$PARTNAME\" = \"$1\" ] && echo \"/dev/$(basename $DEVNAME)\" && return 0\n\tdone\n}\n\ngroup_add() {\n\tlocal name=\"$1\"\n\tlocal gid=\"$2\"\n\tlocal rc\n\t[ -f \"${IPKG_INSTROOT}/etc/group\" ] || return 1\n\t[ -n \"$IPKG_INSTROOT\" ] || lock /var/lock/group\n\techo \"${name}:x:${gid}:\" >> ${IPKG_INSTROOT}/etc/group\n\t[ -n \"$IPKG_INSTROOT\" ] || lock -u /var/lock/group\n}\n\ngroup_exists() {\n\tgrep -qs \"^${1}:\" ${IPKG_INSTROOT}/etc/group\n}\n\ngroup_add_next() {\n\tlocal gid gids\n\tgid=$(grep -s \"^${1}:\" ${IPKG_INSTROOT}/etc/group | cut -d: -f3)\n\tif [ -n \"$gid\" ]; then\n\t\techo $gid\n\t\treturn\n\tfi\n\tgids=$(cut -d: -f3 ${IPKG_INSTROOT}/etc/group)\n\tgid=65536\n\twhile echo \"$gids\" | grep -q \"^$gid$\"; do\n\t\tgid=$((gid + 1))\n\tdone\n\tgroup_add $1 $gid\n\techo $gid\n}\n\ngroup_add_user() {\n\tlocal grp delim=\",\"\n\tgrp=$(grep -s \"^${1}:\" ${IPKG_INSTROOT}/etc/group)\n\techo \"$grp\" | cut -d: -f4 | grep -q $2 && return\n\techo \"$grp\" | grep -q \":$\" && delim=\"\"\n\t[ -n \"$IPKG_INSTROOT\" ] || lock /var/lock/passwd\n\tsed -i \"s/$grp/$grp$delim$2/g\" ${IPKG_INSTROOT}/etc/group\n\tif [ -z \"$IPKG_INSTROOT\" ] && [ -x /usr/sbin/selinuxenabled ] && selinuxenabled; then\n\t\trestorecon /etc/group\n\tfi\n\t[ -n \"$IPKG_INSTROOT\" ] || lock -u /var/lock/passwd\n}\n\nuser_add() {\n\tlocal name=\"${1}\"\n\tlocal uid=\"${2}\"\n\tlocal gid=\"${3}\"\n\tlocal desc=\"${4:-$1}\"\n\tlocal home=\"${5:-/var/run/$1}\"\n\tlocal shell=\"${6:-/bin/false}\"\n\tlocal rc\n\t[ -z \"$uid\" ] && {\n\t\tuids=$(cut -d: -f3 ${IPKG_INSTROOT}/etc/passwd)\n\t\tuid=65536\n\t\twhile echo \"$uids\" | grep -q \"^$uid$\"; do\n\t\t\tuid=$((uid + 1))\n\t\tdone\n\t}\n\t[ -z \"$gid\" ] && gid=$uid\n\t[ -f \"${IPKG_INSTROOT}/etc/passwd\" ] || return 1\n\t[ -n \"$IPKG_INSTROOT\" ] || lock /var/lock/passwd\n\techo \"${name}:x:${uid}:${gid}:${desc}:${home}:${shell}\" >> ${IPKG_INSTROOT}/etc/passwd\n\techo \"${name}:x:0:0:99999:7:::\" >> ${IPKG_INSTROOT}/etc/shadow\n\t[ -n \"$IPKG_INSTROOT\" ] || lock -u /var/lock/passwd\n}\n\nuser_exists() {\n\tgrep -qs \"^${1}:\" ${IPKG_INSTROOT}/etc/passwd\n}\n\nboard_name() {\n\t[ -e /tmp/sysinfo/board_name ] && cat /tmp/sysinfo/board_name || echo \"generic\"\n}\n\ncmdline_get_var() {\n\tlocal var=$1\n\tlocal cmdlinevar tmp\n\n\tfor cmdlinevar in $(cat /proc/cmdline); do\n\t\ttmp=${cmdlinevar##${var}}\n\t\t[ \"=\" = \"${tmp:0:1}\" ] && echo ${tmp:1}\n\tdone\n}\n\n[ -z \"$IPKG_INSTROOT\" ] && [ -f /lib/config/uci.sh ] && . /lib/config/uci.sh\n"
  },
  {
    "path": "package/base-files/files/lib/preinit/02_default_set_state",
    "content": "define_default_set_state() {\n\t. /etc/diag.sh\n}\n\nboot_hook_add preinit_main define_default_set_state\n"
  },
  {
    "path": "package/base-files/files/lib/preinit/02_sysinfo",
    "content": "do_sysinfo_generic() {\n\t[ -d /proc/device-tree ] || return\n\tmkdir -p /tmp/sysinfo\n\t[ -e /tmp/sysinfo/board_name ] || \\\n\t\techo \"$(strings /proc/device-tree/compatible | head -1)\" > /tmp/sysinfo/board_name\n\t[ ! -e /tmp/sysinfo/model -a -e /proc/device-tree/model ] && \\\n\t\techo \"$(cat /proc/device-tree/model)\" > /tmp/sysinfo/model\n}\n\nboot_hook_add preinit_main do_sysinfo_generic\n"
  },
  {
    "path": "package/base-files/files/lib/preinit/10_indicate_failsafe",
    "content": "# Copyright (C) 2006 OpenWrt.org\n# Copyright (C) 2010 Vertical Communications\n\n# commands for emitting messages to network in failsafe mode\n\nindicate_failsafe_led () {\n\tset_state failsafe\n}\n\nindicate_failsafe() {\n\t[ \"$pi_preinit_no_failsafe\" = \"y\" ] && return\n\techo \"- failsafe -\"\n\tpreinit_net_echo \"Entering Failsafe!\\n\"\n\tindicate_failsafe_led\n}\n\nboot_hook_add failsafe indicate_failsafe\n"
  },
  {
    "path": "package/base-files/files/lib/preinit/10_indicate_preinit",
    "content": "# Copyright (C) 2006 OpenWrt.org\n# Copyright (C) 2010 Vertical Communications\n\npreinit_ip_config() {\n\tlocal netdev vid\n\n\tnetdev=${1%\\.*}\n\tvid=${1#*\\.}\n\n\tif [ \"$vid\" = \"$netdev\" ]; then\n\t\tvid=\n\tfi\n\n\tgrep -q \"$netdev\" /proc/net/dev || return\n\n\tif [ -n \"$vid\" ]; then\n\t\tip link add link $netdev name $1 type vlan id $vid\n\tfi\n\n\tip link set dev $netdev up\n\tif [ -n \"$vid\" ]; then\n\t\tip link set dev $1 up\n\tfi\n\tip -4 address add $pi_ip/$pi_netmask broadcast $pi_broadcast dev $1\n}\n\npreinit_config_switch() {\n\tlocal role roles ports device enable reset\n\n\tlocal name=$1\n\tlocal lan_if=$2\n\n\tjson_select switch\n\tjson_select $name\n\n\tjson_get_vars enable reset\n\n\tif [ \"$reset\" -eq \"1\" ]; then\n\t\tswconfig dev $name set reset\n\tfi\n\tswconfig dev $name set enable_vlan $enable\n\n\tif json_is_a roles array; then\n\t\tjson_get_keys roles roles\n\t\tjson_select roles\n\n\t\tfor role in $roles; do\n\t\t\tjson_select \"$role\"\n\t\t\tjson_get_vars ports device\n\t\t\tjson_select ..\n\n\t\t\tif [ \"$device\" = \"$lan_if\" ]; then\n\t\t\t\tswconfig dev $name vlan $role set ports \"$ports\"\n\t\t\tfi\n\t\tdone\n\n\t\tjson_select ..\n\tfi\n\n\tswconfig dev $name set apply\n\n\tjson_select ..\n\tjson_select ..\n}\n\npreinit_config_board() {\n\t/bin/board_detect /tmp/board.json\n\n\t[ -f \"/tmp/board.json\" ] || return\n\n\t. /usr/share/libubox/jshn.sh\n\n\tjson_init\n\tjson_load \"$(cat /tmp/board.json)\"\n\n\tjson_select network\n\t\tjson_select \"lan\"\n\t\t\tjson_get_vars device\n\t\t\tjson_get_values ports ports\n\t\tjson_select ..\n\tjson_select ..\n\n\t[ -n \"$device\" -o -n \"$ports\" ] || return\n\n\t# swconfig uses $device and DSA uses ports\n\t[ -z \"$ports\" ] && {\n\t\tports=\"$device\"\n\t}\n\n\t# only use the first one\n\tifname=${ports%% *}\n\n\tif [ -x /sbin/swconfig ]; then\n\t\t# configure the switch, if present\n\n\t\tjson_get_keys keys switch\n\t\tfor key in $keys; do\n\t\t\tpreinit_config_switch $key $ifname\n\t\tdone\n\telse\n\t\t# trim any vlan ids\n\t\tifname=${ifname%\\.*}\n\t\t# trim any vlan modifiers like :t\n\t\tifname=${ifname%\\:*}\n\tfi\n\n\tpi_ifname=$ifname\n\n\tpreinit_ip_config $pi_ifname\n}\n\npreinit_ip() {\n\t[ \"$pi_preinit_no_failsafe\" = \"y\" ] && return\n\n\t# if the preinit interface isn't specified and ifname is set in\n\t# preinit.arch use that interface\n\tif [ -z \"$pi_ifname\" ]; then\n\t\tpi_ifname=$ifname\n\tfi\n\n\tif [ -n \"$pi_ifname\" ]; then\n\t\tpreinit_ip_config $pi_ifname\n\telif [ -d \"/etc/board.d/\" ]; then\n\t\tpreinit_config_board\n\tfi\n\n\tpreinit_net_echo \"Doing OpenWrt Preinit\\n\"\n}\n\npreinit_ip_deconfig() {\n\t[ -n \"$pi_ifname\" ] && grep -q \"$pi_ifname\" /proc/net/dev && {\n\t\tlocal netdev vid\n\n\t\tnetdev=${pi_ifname%\\.*}\n\t\tvid=${pi_ifname#*\\.}\n\n\t\tif [ \"$vid\" = \"$netdev\" ]; then\n\t\t\tvid=\n\t\tfi\n\n\t\tip -4 address flush dev $pi_ifname\n\t\tip link set dev $netdev down\n\n\t\tif [ -n \"$vid\" ]; then\n\t\t\tip link delete $pi_ifname\n\t\tfi\n\t}\n}\n\npreinit_net_echo() {\n\t[ -n \"$pi_ifname\" ] && grep -q \"$pi_ifname\" /proc/net/dev && {\n\t\t{\n\t\t\t[ \"$pi_preinit_net_messages\" = \"y\" ] || {\n\t\t\t\t[ \"$pi_failsafe_net_message\" = \"true\" ] &&\n\t\t\t\t\t[ \"$pi_preinit_no_failsafe_netmsg\" != \"y\" ]\n\t\t\t}\n\t\t} && netmsg $pi_broadcast \"$1\"\n\t}\n}\n\npi_indicate_preinit() {\n\tset_state preinit\n}\n\nboot_hook_add preinit_main preinit_ip\nboot_hook_add preinit_main pi_indicate_preinit\n"
  },
  {
    "path": "package/base-files/files/lib/preinit/30_failsafe_wait",
    "content": "# Copyright (C) 2006-2010 OpenWrt.org\n# Copyright (C) 2010 Vertical Communications\n\nfs_wait_for_key () {\n\tlocal timeout=$3\n\tlocal timer\n\tlocal do_keypress\n\tlocal keypress_true=\"$(mktemp)\"\n\tlocal keypress_wait=\"$(mktemp)\"\n\tlocal keypress_sec=\"$(mktemp)\"\n\tif [ -z \"$keypress_wait\" ]; then\n\t\tkeypress_wait=/tmp/.keypress_wait\n\t\ttouch $keypress_wait\n\tfi\n\tif [ -z \"$keypress_true\" ]; then\n\t\tkeypress_true=/tmp/.keypress_true\n\t\ttouch $keypress_true\n\tfi\n\tif [ -z \"$keypress_sec\" ]; then\n\t\tkeypress_sec=/tmp/.keypress_sec\n\t\ttouch $keypress_sec\n\tfi\n\n\ttrap \"echo 'true' >$keypress_true; lock -u $keypress_wait ; rm -f $keypress_wait\" INT\n\ttrap \"echo 'true' >$keypress_true; lock -u $keypress_wait ; rm -f $keypress_wait\" USR1\n\n\t[ -n \"$timeout\" ] || timeout=1\n\t[ $timeout -ge 1 ] || timeout=1\n\ttimer=$timeout\n\tlock $keypress_wait\n\t{\n\t\twhile [ $timer -gt 0 ]; do\n\t\t\tpi_failsafe_net_message=true \\\n\t\t\t\tpreinit_net_echo \"Please press button now to enter failsafe\"\n\t\t\techo \"$timer\" >$keypress_sec\n\t\t\ttimer=$(($timer - 1))\n\t\t\tsleep 1\n\t\tdone\n\t\tlock -u $keypress_wait\n\t\trm -f $keypress_wait\n\t} &\n\n\t[ \"$pi_preinit_no_failsafe\" != \"y\" ] && echo \"Press the [$1] key and hit [enter] $2\"\n\techo \"Press the [1], [2], [3] or [4] key and hit [enter] to select the debug level\"\n\t# if we're on the console we wait for input\n\t{\n\t\twhile [ -r $keypress_wait ]; do\n\t\t\ttimer=\"$(cat $keypress_sec)\"\n\n\t\t\t[ -n \"$timer\" ] || timer=1\n\t\t\ttimer=\"${timer%%\\ *}\"\n\t\t\t[ $timer -ge 1 ] || timer=1\n\t\t\tdo_keypress=\"\"\n\t\t\t{\n\t\t\t\tread -t \"$timer\" do_keypress\n\t\t\t\tcase \"$do_keypress\" in\n\t\t\t\t$1)\n\t\t\t\t\techo \"true\" >$keypress_true\n\t\t\t\t\t;;\n\t\t\t\t1 | 2 | 3 | 4)\n\t\t\t\t\techo \"$do_keypress\" >/tmp/debug_level\n\t\t\t\t\t;;\n\t\t\t\t*)\n\t\t\t\t\tcontinue;\n\t\t\t\t\t;;\n\t\t\t\tesac\n\t\t\t\tlock -u $keypress_wait\n\t\t\t\trm -f $keypress_wait\n\t\t\t}\n\t\tdone\n\t}\n\tlock -w $keypress_wait\n\n\tkeypressed=1\n\t[ \"$(cat $keypress_true)\" = \"true\" ] && keypressed=0\n\n\trm -f $keypress_true\n\trm -f $keypress_wait\n\trm -f $keypress_sec\n\n\treturn $keypressed\n}\n\nfailsafe_wait() {\n\tFAILSAFE=\n\t[ \"$pi_preinit_no_failsafe\" = \"y\" ] && {\n\t\tfs_wait_for_key \"\" \"\" $fs_failsafe_wait_timeout\n\t\treturn\n\t}\n\tgrep -q 'failsafe=' /proc/cmdline && FAILSAFE=true && export FAILSAFE\n\tif [ \"$FAILSAFE\" != \"true\" ]; then\n\t\tfs_wait_for_key f 'to enter failsafe mode' $fs_failsafe_wait_timeout && FAILSAFE=true\n\t\t[ -f \"/tmp/failsafe_button\" ] && FAILSAFE=true && echo \"- failsafe button \"$(cat /tmp/failsafe_button)\" was pressed -\"\n\t\t[ \"$FAILSAFE\" = \"true\" ] && export FAILSAFE && touch /tmp/failsafe\n\tfi\n}\n\nboot_hook_add preinit_main failsafe_wait\n"
  },
  {
    "path": "package/base-files/files/lib/preinit/40_run_failsafe_hook",
    "content": "# Copyright (C) 2006-2010 OpenWrt.org\n# Copyright (C) 2010 Vertical Communications\n\nrun_failsafe_hook() {\n    [ \"$pi_preinit_no_failsafe\" = \"y\" ] && return\n    if [ \"$FAILSAFE\" = \"true\" ]; then\n\tlock /tmp/.failsafe\n\tboot_run_hook failsafe\n\twhile [ ! -e /tmp/sysupgrade ]; do\n\t    lock -w /tmp/.failsafe\n\tdone\n\texit\n    fi\n}\n\nboot_hook_add preinit_main run_failsafe_hook\n"
  },
  {
    "path": "package/base-files/files/lib/preinit/50_indicate_regular_preinit",
    "content": "# Copyright (C) 2006 OpenWrt.org\n# Copyright (C) 2010 Vertical Communications\n\nindicate_regular_preinit() {\n\tpreinit_net_echo \"Continuing with Regular Preinit\\n\"\n\tset_state preinit_regular\n}\n\nboot_hook_add preinit_main indicate_regular_preinit\n"
  },
  {
    "path": "package/base-files/files/lib/preinit/70_initramfs_test",
    "content": "# Copyright (C) 2006 OpenWrt.org\n# Copyright (C) 2010 Vertical Communications\n\ninitramfs_test() {\n\tif [ -n \"$INITRAMFS\" ]; then\n\t\tboot_run_hook initramfs\n\t\tpreinit_ip_deconfig\n\t\tbreak\n\tfi\n}\n\nboot_hook_add preinit_main initramfs_test\n"
  },
  {
    "path": "package/base-files/files/lib/preinit/80_mount_root",
    "content": "# Copyright (C) 2006 OpenWrt.org\n# Copyright (C) 2010 Vertical Communications\n\nmissing_lines() {\n\tlocal file1 file2 line\n\tfile1=\"$1\"\n\tfile2=\"$2\"\n\toIFS=\"$IFS\"\n\tIFS=\":\"\n\twhile read line; do\n\t\tset -- $line\n\t\tgrep -q \"^$1:\" \"$file2\" || echo \"$*\"\n\tdone < \"$file1\"\n\tIFS=\"$oIFS\"\n}\n\ndo_mount_root() {\n\tmount_root\n\tboot_run_hook preinit_mount_root\n\t[ -f /sysupgrade.tgz -o -f /tmp/sysupgrade.tar ] && {\n\t\techo \"- config restore -\"\n\t\tcp /etc/passwd /etc/group /etc/shadow /tmp\n\t\tcd /\n\t\t[ -f /sysupgrade.tgz ] && tar xzf /sysupgrade.tgz\n\t\t[ -f /tmp/sysupgrade.tar ] && tar xf /tmp/sysupgrade.tar\n\t\tmissing_lines /tmp/passwd /etc/passwd >> /etc/passwd\n\t\tmissing_lines /tmp/group /etc/group >> /etc/group\n\t\tmissing_lines /tmp/shadow /etc/shadow >> /etc/shadow\n\t\trm /tmp/passwd /tmp/group /tmp/shadow\n\t\t# Prevent configuration corruption on a power loss\n\t\tsync\n\t}\n}\n\n[ \"$INITRAMFS\" = \"1\" ] || boot_hook_add preinit_main do_mount_root\n"
  },
  {
    "path": "package/base-files/files/lib/preinit/99_10_failsafe_login",
    "content": "# Copyright (C) 2006-2015 OpenWrt.org\n# Copyright (C) 2010 Vertical Communications\n\nfailsafe_shell() {\n\tlocal console=\"$(sed -e 's/ /\\n/g' /proc/cmdline | grep '^console=' | head -1 | sed -e 's/^console=//' -e 's/,.*//')\"\n\t[ -n \"$console\" ] || console=console\n\t[ -c \"/dev/$console\" ] || return 0\n\twhile true; do\n\t\tash --login <\"/dev/$console\" >\"/dev/$console\" 2>\"/dev/$console\"\n\t\tsleep 1\n\tdone &\n}\n\nboot_hook_add failsafe failsafe_shell\n"
  },
  {
    "path": "package/base-files/files/lib/preinit/99_10_run_init",
    "content": "# Copyright (C) 2006 OpenWrt.org\n# Copyright (C) 2010 Vertical Communications\n\nrun_init() {\n\tpreinit_ip_deconfig\n}\n\nboot_hook_add preinit_main run_init\n"
  },
  {
    "path": "package/base-files/files/lib/upgrade/common.sh",
    "content": "RAM_ROOT=/tmp/root\n\nexport BACKUP_FILE=sysupgrade.tgz\t# file extracted by preinit\n\n[ -x /usr/bin/ldd ] || ldd() { LD_TRACE_LOADED_OBJECTS=1 $*; }\nlibs() { ldd $* 2>/dev/null | sed -E 's/(.* => )?(.*) .*/\\2/'; }\n\ninstall_file() { # <file> [ <file> ... ]\n\tlocal target dest dir\n\tfor file in \"$@\"; do\n\t\tif [ -L \"$file\" ]; then\n\t\t\ttarget=\"$(readlink -f \"$file\")\"\n\t\t\tdest=\"$RAM_ROOT/$file\"\n\t\t\t[ ! -f \"$dest\" ] && {\n\t\t\t\tdir=\"$(dirname \"$dest\")\"\n\t\t\t\tmkdir -p \"$dir\"\n\t\t\t\tln -s \"$target\" \"$dest\"\n\t\t\t}\n\t\t\tfile=\"$target\"\n\t\tfi\n\t\tdest=\"$RAM_ROOT/$file\"\n\t\t[ -f \"$file\" -a ! -f \"$dest\" ] && {\n\t\t\tdir=\"$(dirname \"$dest\")\"\n\t\t\tmkdir -p \"$dir\"\n\t\t\tcp \"$file\" \"$dest\"\n\t\t}\n\tdone\n}\n\ninstall_bin() {\n\tlocal src files\n\tsrc=$1\n\tfiles=$1\n\t[ -x \"$src\" ] && files=\"$src $(libs $src)\"\n\tinstall_file $files\n}\n\nrun_hooks() {\n\tlocal arg=\"$1\"; shift\n\tfor func in \"$@\"; do\n\t\teval \"$func $arg\"\n\tdone\n}\n\nask_bool() {\n\tlocal default=\"$1\"; shift;\n\tlocal answer=\"$default\"\n\n\t[ \"$INTERACTIVE\" -eq 1 ] && {\n\t\tcase \"$default\" in\n\t\t\t0) echo -n \"$* (y/N): \";;\n\t\t\t*) echo -n \"$* (Y/n): \";;\n\t\tesac\n\t\tread answer\n\t\tcase \"$answer\" in\n\t\t\ty*) answer=1;;\n\t\t\tn*) answer=0;;\n\t\t\t*) answer=\"$default\";;\n\t\tesac\n\t}\n\t[ \"$answer\" -gt 0 ]\n}\n\n_v() {\n\t[ -n \"$VERBOSE\" ] && [ \"$VERBOSE\" -ge 1 ] && echo \"$*\" >&2\n}\n\nv() {\n\t_v \"$(date) upgrade: $@\"\n\tlogger -p info -t upgrade \"$@\"\n}\n\njson_string() {\n\tlocal v=\"$1\"\n\tv=\"${v//\\\\/\\\\\\\\}\"\n\tv=\"${v//\\\"/\\\\\\\"}\"\n\techo \"\\\"$v\\\"\"\n}\n\nrootfs_type() {\n\t/bin/mount | awk '($3 ~ /^\\/$/) && ($5 !~ /rootfs/) { print $5 }'\n}\n\nget_image() { # <source> [ <command> ]\n\tlocal from=\"$1\"\n\tlocal cmd=\"$2\"\n\n\tif [ -z \"$cmd\" ]; then\n\t\tlocal magic=\"$(dd if=\"$from\" bs=2 count=1 2>/dev/null | hexdump -n 2 -e '1/1 \"%02x\"')\"\n\t\tcase \"$magic\" in\n\t\t\t1f8b) cmd=\"busybox zcat\";;\n\t\t\t*) cmd=\"cat\";;\n\t\tesac\n\tfi\n\n\t$cmd <\"$from\"\n}\n\nget_image_dd() {\n\tlocal from=\"$1\"; shift\n\n\t(\n\t\texec 3>&2\n\t\t( exec 3>&2; get_image \"$from\" 2>&1 1>&3 | grep -v -F ' Broken pipe'     ) 2>&1 1>&3 \\\n\t\t\t| ( exec 3>&2; dd \"$@\" 2>&1 1>&3 | grep -v -E ' records (in|out)') 2>&1 1>&3\n\t\texec 3>&-\n\t)\n}\n\nget_magic_word() {\n\t(get_image \"$@\" | dd bs=2 count=1 | hexdump -v -n 2 -e '1/1 \"%02x\"') 2>/dev/null\n}\n\nget_magic_long() {\n\t(get_image \"$@\" | dd bs=4 count=1 | hexdump -v -n 4 -e '1/1 \"%02x\"') 2>/dev/null\n}\n\nget_magic_gpt() {\n\t(get_image \"$@\" | dd bs=8 count=1 skip=64) 2>/dev/null\n}\n\nget_magic_vfat() {\n\t(get_image \"$@\" | dd bs=3 count=1 skip=18) 2>/dev/null\n}\n\nget_magic_fat32() {\n\t(get_image \"$@\" | dd bs=1 count=5 skip=82) 2>/dev/null\n}\n\npart_magic_efi() {\n\tlocal magic=$(get_magic_gpt \"$@\")\n\t[ \"$magic\" = \"EFI PART\" ]\n}\n\npart_magic_fat() {\n\tlocal magic=$(get_magic_vfat \"$@\")\n\tlocal magic_fat32=$(get_magic_fat32 \"$@\")\n\t[ \"$magic\" = \"FAT\" ] || [ \"$magic_fat32\" = \"FAT32\" ]\n}\n\nexport_bootdevice() {\n\tlocal cmdline uuid blockdev uevent line class\n\tlocal MAJOR MINOR DEVNAME DEVTYPE\n\tlocal rootpart=\"$(cmdline_get_var root)\"\n\n\tcase \"$rootpart\" in\n\t\tPARTUUID=[a-f0-9][a-f0-9][a-f0-9][a-f0-9][a-f0-9][a-f0-9][a-f0-9][a-f0-9]-[a-f0-9][a-f0-9])\n\t\t\tuuid=\"${rootpart#PARTUUID=}\"\n\t\t\tuuid=\"${uuid%-[a-f0-9][a-f0-9]}\"\n\t\t\tfor blockdev in $(find /dev -type b); do\n\t\t\t\tset -- $(dd if=$blockdev bs=1 skip=440 count=4 2>/dev/null | hexdump -v -e '4/1 \"%02x \"')\n\t\t\t\tif [ \"$4$3$2$1\" = \"$uuid\" ]; then\n\t\t\t\t\tuevent=\"/sys/class/block/${blockdev##*/}/uevent\"\n\t\t\t\t\tbreak\n\t\t\t\tfi\n\t\t\tdone\n\t\t;;\n\t\tPARTUUID=????????-????-????-????-??????????0?/PARTNROFF=1 | \\\n\t\tPARTUUID=????????-????-????-????-??????????02)\n\t\t\tuuid=\"${rootpart#PARTUUID=}\"\n\t\t\tuuid=\"${uuid%/PARTNROFF=1}\"\n\t\t\tuuid=\"${uuid%0?}00\"\n\t\t\tfor disk in $(find /dev -type b); do\n\t\t\t\tset -- $(dd if=$disk bs=1 skip=568 count=16 2>/dev/null | hexdump -v -e '8/1 \"%02x \"\" \"2/1 \"%02x\"\"-\"6/1 \"%02x\"')\n\t\t\t\tif [ \"$4$3$2$1-$6$5-$8$7-$9\" = \"$uuid\" ]; then\n\t\t\t\t\tuevent=\"/sys/class/block/${disk##*/}/uevent\"\n\t\t\t\t\tbreak\n\t\t\t\tfi\n\t\t\tdone\n\t\t;;\n\t\t/dev/*)\n\t\t\tuevent=\"/sys/class/block/${rootpart##*/}/../uevent\"\n\t\t;;\n\t\t0x[a-f0-9][a-f0-9][a-f0-9] | 0x[a-f0-9][a-f0-9][a-f0-9][a-f0-9] | \\\n\t\t[a-f0-9][a-f0-9][a-f0-9] | [a-f0-9][a-f0-9][a-f0-9][a-f0-9])\n\t\t\trootpart=0x${rootpart#0x}\n\t\t\tfor class in /sys/class/block/*; do\n\t\t\t\twhile read line; do\n\t\t\t\t\texport -n \"$line\"\n\t\t\t\tdone < \"$class/uevent\"\n\t\t\t\tif [ $((rootpart/256)) = $MAJOR -a $((rootpart%256)) = $MINOR ]; then\n\t\t\t\t\tuevent=\"$class/../uevent\"\n\t\t\t\tfi\n\t\t\tdone\n\t\t;;\n\tesac\n\n\tif [ -e \"$uevent\" ]; then\n\t\twhile read line; do\n\t\t\texport -n \"$line\"\n\t\tdone < \"$uevent\"\n\t\texport BOOTDEV_MAJOR=$MAJOR\n\t\texport BOOTDEV_MINOR=$MINOR\n\t\treturn 0\n\tfi\n\n\treturn 1\n}\n\nexport_partdevice() {\n\tlocal var=\"$1\" offset=\"$2\"\n\tlocal uevent line MAJOR MINOR DEVNAME DEVTYPE\n\n\tfor uevent in /sys/class/block/*/uevent; do\n\t\twhile read line; do\n\t\t\texport -n \"$line\"\n\t\tdone < \"$uevent\"\n\t\tif [ $BOOTDEV_MAJOR = $MAJOR -a $(($BOOTDEV_MINOR + $offset)) = $MINOR -a -b \"/dev/$DEVNAME\" ]; then\n\t\t\texport \"$var=$DEVNAME\"\n\t\t\treturn 0\n\t\tfi\n\tdone\n\n\treturn 1\n}\n\nhex_le32_to_cpu() {\n\t[ \"$(echo 01 | hexdump -v -n 2 -e '/2 \"%x\"')\" = \"3031\" ] && {\n\t\techo \"${1:0:2}${1:8:2}${1:6:2}${1:4:2}${1:2:2}\"\n\t\treturn\n\t}\n\techo \"$@\"\n}\n\nget_partitions() { # <device> <filename>\n\tlocal disk=\"$1\"\n\tlocal filename=\"$2\"\n\n\tif [ -b \"$disk\" -o -f \"$disk\" ]; then\n\t\tv \"Reading partition table from $filename...\"\n\n\t\tlocal magic=$(dd if=\"$disk\" bs=2 count=1 skip=255 2>/dev/null)\n\t\tif [ \"$magic\" != $'\\x55\\xAA' ]; then\n\t\t\tv \"Invalid partition table on $disk\"\n\t\t\texit\n\t\tfi\n\n\t\trm -f \"/tmp/partmap.$filename\"\n\n\t\tlocal part\n\t\tpart_magic_efi \"$disk\" && {\n\t\t\t#export_partdevice will fail when partition number is greater than 15, as\n\t\t\t#the partition major device number is not equal to the disk major device number\n\t\t\tfor part in 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15; do\n\t\t\t\tset -- $(hexdump -v -n 48 -s \"$((0x380 + $part * 0x80))\" -e '4/4 \"%08x\"\" \"4/4 \"%08x\"\" \"4/4 \"0x%08X \"' \"$disk\")\n\n\t\t\t\tlocal type=\"$1\"\n\t\t\t\tlocal lba=\"$(( $(hex_le32_to_cpu $4) * 0x100000000 + $(hex_le32_to_cpu $3) ))\"\n\t\t\t\tlocal end=\"$(( $(hex_le32_to_cpu $6) * 0x100000000 + $(hex_le32_to_cpu $5) ))\"\n\t\t\t\tlocal num=\"$(( $end - $lba + 1 ))\"\n\n\t\t\t\t[ \"$type\" = \"00000000000000000000000000000000\" ] && continue\n\n\t\t\t\tprintf \"%2d %5d %7d\\n\" $part $lba $num >> \"/tmp/partmap.$filename\"\n\t\t\tdone\n\t\t} || {\n\t\t\tfor part in 1 2 3 4; do\n\t\t\t\tset -- $(hexdump -v -n 12 -s \"$((0x1B2 + $part * 16))\" -e '3/4 \"0x%08X \"' \"$disk\")\n\n\t\t\t\tlocal type=\"$(( $(hex_le32_to_cpu $1) % 256))\"\n\t\t\t\tlocal lba=\"$(( $(hex_le32_to_cpu $2) ))\"\n\t\t\t\tlocal num=\"$(( $(hex_le32_to_cpu $3) ))\"\n\n\t\t\t\t[ $type -gt 0 ] || continue\n\n\t\t\t\tprintf \"%2d %5d %7d\\n\" $part $lba $num >> \"/tmp/partmap.$filename\"\n\t\t\tdone\n\t\t}\n\tfi\n}\n\nindicate_upgrade() {\n\t. /etc/diag.sh\n\tset_state upgrade\n}\n\n# Flash firmware to MTD partition\n#\n# $(1): path to image\n# $(2): (optional) pipe command to extract firmware, e.g. dd bs=n skip=m\ndefault_do_upgrade() {\n\tsync\n\techo 3 > /proc/sys/vm/drop_caches\n\tif [ -n \"$UPGRADE_BACKUP\" ]; then\n\t\tget_image \"$1\" \"$2\" | mtd $MTD_ARGS $MTD_CONFIG_ARGS -j \"$UPGRADE_BACKUP\" write - \"${PART_NAME:-image}\"\n\telse\n\t\tget_image \"$1\" \"$2\" | mtd $MTD_ARGS write - \"${PART_NAME:-image}\"\n\tfi\n\t[ $? -ne 0 ] && exit 1\n}\n"
  },
  {
    "path": "package/base-files/files/lib/upgrade/do_stage2",
    "content": "#!/bin/sh\n\n. /lib/functions.sh\n\ninclude /lib/upgrade\n\nv \"Performing system upgrade...\"\nif type 'platform_do_upgrade' >/dev/null 2>/dev/null; then\n\tplatform_do_upgrade \"$IMAGE\"\nelse\n\tdefault_do_upgrade \"$IMAGE\"\nfi\n\nif [ -n \"$UPGRADE_BACKUP\" ] && type 'platform_copy_config' >/dev/null 2>/dev/null; then\n\tplatform_copy_config\nfi\n\nv \"Upgrade completed\"\nsleep 1\n\nv \"Rebooting system...\"\numount -a\nreboot -f\nsleep 5\necho b 2>/dev/null >/proc/sysrq-trigger\n"
  },
  {
    "path": "package/base-files/files/lib/upgrade/emmc.sh",
    "content": "# Copyright (C) 2021 OpenWrt.org\n#\n\n. /lib/functions.sh\n\nemmc_upgrade_tar() {\n\tlocal tar_file=\"$1\"\n\t[ \"$CI_KERNPART\" -a -z \"$EMMC_KERN_DEV\" ] && export EMMC_KERN_DEV=\"$(find_mmc_part $CI_KERNPART $CI_ROOTDEV)\"\n\t[ \"$CI_ROOTPART\" -a -z \"$EMMC_ROOT_DEV\" ] && export EMMC_ROOT_DEV=\"$(find_mmc_part $CI_ROOTPART $CI_ROOTDEV)\"\n\t[ \"$CI_DATAPART\" -a -z \"$EMMC_DATA_DEV\" ] && export EMMC_DATA_DEV=\"$(find_mmc_part $CI_DATAPART $CI_ROOTDEV)\"\n\tlocal has_kernel\n\tlocal has_rootfs\n\tlocal board_dir=$(tar tf \"$tar_file\" | grep -m 1 '^sysupgrade-.*/$')\n\tboard_dir=${board_dir%/}\n\n\ttar tf \"$tar_file\" ${board_dir}/kernel 1>/dev/null 2>/dev/null && has_kernel=1\n\ttar tf \"$tar_file\" ${board_dir}/root 1>/dev/null 2>/dev/null && has_rootfs=1\n\n\t[ \"$has_kernel\" = 1 -a \"$EMMC_KERN_DEV\" ] &&\n\t\texport EMMC_KERNEL_BLOCKS=$(($(tar xf \"$tar_file\" ${board_dir}/kernel -O | dd of=\"$EMMC_KERN_DEV\" bs=512 2>&1 | grep \"records out\" | cut -d' ' -f1)))\n\n\t[ \"$has_rootfs\" = 1 -a \"$EMMC_ROOT_DEV\" ] && {\n\t\texport EMMC_ROOTFS_BLOCKS=$(($(tar xf \"$tar_file\" ${board_dir}/root -O | dd of=\"$EMMC_ROOT_DEV\" bs=512 2>&1 | grep \"records out\" | cut -d' ' -f1)))\n\t\t# Account for 64KiB ROOTDEV_OVERLAY_ALIGN in libfstools\n\t\tEMMC_ROOTFS_BLOCKS=$(((EMMC_ROOTFS_BLOCKS + 127) & ~127))\n\t}\n\n\tif [ -z \"$UPGRADE_BACKUP\" ]; then\n\t\tif [ \"$EMMC_DATA_DEV\" ]; then\n\t\t\tdd if=/dev/zero of=\"$EMMC_DATA_DEV\" bs=512 count=8\n\t\telif [ \"$EMMC_ROOTFS_BLOCKS\" ]; then\n\t\t\tdd if=/dev/zero of=\"$EMMC_ROOT_DEV\" bs=512 seek=$EMMC_ROOTFS_BLOCKS count=8\n\t\telif [ \"$EMMC_KERNEL_BLOCKS\" ]; then\n\t\t\tdd if=/dev/zero of=\"$EMMC_KERN_DEV\" bs=512 seek=$EMMC_KERNEL_BLOCKS count=8\n\t\tfi\n\tfi\n}\n\nemmc_upgrade_fit() {\n\tlocal fit_file=\"$1\"\n\t[ \"$CI_KERNPART\" -a -z \"$EMMC_KERN_DEV\" ] && export EMMC_KERN_DEV=\"$(find_mmc_part $CI_KERNPART $CI_ROOTDEV)\"\n\n\tif [ \"$EMMC_KERN_DEV\" ]; then\n\t\texport EMMC_KERNEL_BLOCKS=$(($(get_image \"$fit_file\" | fwtool -i /dev/null -T - | dd of=\"$EMMC_KERN_DEV\" bs=512 2>&1 | grep \"records out\" | cut -d' ' -f1)))\n\n\t\t[ -z \"$UPGRADE_BACKUP\" ] && dd if=/dev/zero of=\"$EMMC_KERN_DEV\" bs=512 seek=$EMMC_KERNEL_BLOCKS count=8\n\tfi\n}\n\nemmc_copy_config() {\n\tif [ \"$EMMC_DATA_DEV\" ]; then\n\t\tdd if=\"$UPGRADE_BACKUP\" of=\"$EMMC_DATA_DEV\" bs=512\n\telif [ \"$EMMC_ROOTFS_BLOCKS\" ]; then\n\t\tdd if=\"$UPGRADE_BACKUP\" of=\"$EMMC_ROOT_DEV\" bs=512 seek=$EMMC_ROOTFS_BLOCKS\n\telif [ \"$EMMC_KERNEL_BLOCKS\" ]; then\n\t\tdd if=\"$UPGRADE_BACKUP\" of=\"$EMMC_KERN_DEV\" bs=512 seek=$EMMC_KERNEL_BLOCKS\n\tfi\n}\n\nemmc_do_upgrade() {\n\tlocal file_type=$(identify $1)\n\n\tcase \"$file_type\" in\n\t\t\"fit\")  emmc_upgrade_fit $1;;\n\t\t*)      emmc_upgrade_tar $1;;\n\tesac\n}\n"
  },
  {
    "path": "package/base-files/files/lib/upgrade/fwtool.sh",
    "content": "fwtool_check_signature() {\n\t[ $# -gt 1 ] && return 1\n\n\t[ ! -x /usr/bin/ucert ] && {\n\t\tif [ \"$REQUIRE_IMAGE_SIGNATURE\" = 1 ]; then\n\t\t\treturn 1\n\t\telse\n\t\t\treturn 0\n\t\tfi\n\t}\n\n\tif ! fwtool -q -s /tmp/sysupgrade.ucert \"$1\"; then\n\t\tv \"Image signature not present\"\n\t\t[ \"$REQUIRE_IMAGE_SIGNATURE\" = 1 -a \"$FORCE\" != 1 ] && {\n\t\t\tv \"Use sysupgrade -F to override this check when downgrading or flashing to vendor firmware\"\n\t\t}\n\t\t[ \"$REQUIRE_IMAGE_SIGNATURE\" = 1 ] && return 1\n\t\treturn 0\n\tfi\n\n\tfwtool -q -T -s /dev/null \"$1\" | \\\n\t\tucert -V -m - -c \"/tmp/sysupgrade.ucert\" -P /etc/opkg/keys\n\n\treturn $?\n}\n\nfwtool_check_image() {\n\t[ $# -gt 1 ] && return 1\n\n\t. /usr/share/libubox/jshn.sh\n\n\tif ! fwtool -q -i /tmp/sysupgrade.meta \"$1\"; then\n\t\tv \"Image metadata not present\"\n\t\t[ \"$REQUIRE_IMAGE_METADATA\" = 1 -a \"$FORCE\" != 1 ] && {\n\t\t\tv \"Use sysupgrade -F to override this check when downgrading or flashing to vendor firmware\"\n\t\t}\n\t\t[ \"$REQUIRE_IMAGE_METADATA\" = 1 ] && return 1\n\t\treturn 0\n\tfi\n\n\tjson_load \"$(cat /tmp/sysupgrade.meta)\" || {\n\t\tv \"Invalid image metadata\"\n\t\treturn 1\n\t}\n\n\tdevice=\"$(cat /tmp/sysinfo/board_name)\"\n\tdevicecompat=\"$(uci -q get system.@system[0].compat_version)\"\n\t[ -n \"$devicecompat\" ] || devicecompat=\"1.0\"\n\n\tjson_get_var imagecompat compat_version\n\tjson_get_var compatmessage compat_message\n\t[ -n \"$imagecompat\" ] || imagecompat=\"1.0\"\n\n\t# select correct supported list based on compat_version\n\t# (using this ensures that compatibility check works for devices\n\t#  not knowing about compat-version)\n\tlocal supported=supported_devices\n\t[ \"$imagecompat\" != \"1.0\" ] && supported=new_supported_devices\n\tjson_select $supported || return 1\n\n\tjson_get_keys dev_keys\n\tfor k in $dev_keys; do\n\t\tjson_get_var dev \"$k\"\n\t\tif [ \"$dev\" = \"$device\" ]; then\n\t\t\t# major compat version -> no sysupgrade\n\t\t\tif [ \"${devicecompat%.*}\" != \"${imagecompat%.*}\" ]; then\n\t\t\t\tv \"The device is supported, but this image is incompatible for sysupgrade based on the image version ($devicecompat->$imagecompat).\"\n\t\t\t\t[ -n \"$compatmessage\" ] && v \"$compatmessage\"\n\t\t\t\treturn 1\n\t\t\tfi\n\n\t\t\t# minor compat version -> sysupgrade with -n required\n\t\t\tif [ \"${devicecompat#.*}\" != \"${imagecompat#.*}\" ] && [ \"$SAVE_CONFIG\" = \"1\" ]; then\n\t\t\t\tv \"The device is supported, but the config is incompatible to the new image ($devicecompat->$imagecompat). Please upgrade without keeping config (sysupgrade -n).\"\n\t\t\t\t[ -n \"$compatmessage\" ] && v \"$compatmessage\"\n\t\t\t\treturn 1\n\t\t\tfi\n\n\t\t\treturn 0\n\t\tfi\n\tdone\n\n\tv \"Device $device not supported by this image\"\n\tlocal devices=\"Supported devices:\"\n\tfor k in $dev_keys; do\n\t\tjson_get_var dev \"$k\"\n\t\tdevices=\"$devices $dev\"\n\tdone\n\tv \"$devices\"\n\n\treturn 1\n}\n"
  },
  {
    "path": "package/base-files/files/lib/upgrade/keep.d/base-files-essential",
    "content": "# Essential files that will be always kept\n/etc/hosts\n/etc/inittab\n/etc/group\n/etc/passwd\n/etc/profile\n/etc/shadow\n/etc/shells\n/etc/shinit\n/etc/sysctl.conf\n/etc/rc.local\n"
  },
  {
    "path": "package/base-files/files/lib/upgrade/legacy-sdcard.sh",
    "content": "legacy_sdcard_check_image() {\n\tlocal file=\"$1\"\n\tlocal diskdev partdev diff\n\n\texport_bootdevice && export_partdevice diskdev 0 || {\n\t\tv \"Unable to determine upgrade device\"\n\treturn 1\n\t}\n\n\tget_partitions \"/dev/$diskdev\" bootdisk\n\n\tv \"Extract boot sector from the image\"\n\tget_image_dd \"$1\" of=/tmp/image.bs count=1 bs=512b\n\n\tget_partitions /tmp/image.bs image\n\n\t#compare tables\n\tdiff=\"$(grep -F -x -v -f /tmp/partmap.bootdisk /tmp/partmap.image)\"\n\n\trm -f /tmp/image.bs /tmp/partmap.bootdisk /tmp/partmap.image\n\n\tif [ -n \"$diff\" ]; then\n\t\tv \"Partition layout has changed. Full image will be written.\"\n\t\task_bool 0 \"Abort\" && exit 1\n\t\treturn 0\n\tfi\n}\n\nlegacy_sdcard_do_upgrade() {\n\tlocal board=$(board_name)\n\tlocal diskdev partdev diff\n\n\texport_bootdevice && export_partdevice diskdev 0 || {\n\t\tv \"Unable to determine upgrade device\"\n\treturn 1\n\t}\n\n\tsync\n\n\tif [ \"$UPGRADE_OPT_SAVE_PARTITIONS\" = \"1\" ]; then\n\t\tget_partitions \"/dev/$diskdev\" bootdisk\n\n\t\tv \"Extract boot sector from the image\"\n\t\tget_image_dd \"$1\" of=/tmp/image.bs count=1 bs=512b\n\n\t\tget_partitions /tmp/image.bs image\n\n\t\t#compare tables\n\t\tdiff=\"$(grep -F -x -v -f /tmp/partmap.bootdisk /tmp/partmap.image)\"\n\telse\n\t\tdiff=1\n\tfi\n\n\tif [ -n \"$diff\" ]; then\n\t\tget_image_dd \"$1\" of=\"/dev/$diskdev\" bs=4096 conv=fsync\n\n\t\t# Separate removal and addtion is necessary; otherwise, partition 1\n\t\t# will be missing if it overlaps with the old partition 2\n\t\tpartx -d - \"/dev/$diskdev\"\n\t\tpartx -a - \"/dev/$diskdev\"\n\telse\n\t\tv \"Writing bootloader to /dev/$diskdev\"\n\t\tget_image_dd \"$1\" of=\"$diskdev\" bs=512 skip=1 seek=1 count=2048 conv=fsync\n\t\t#iterate over each partition from the image and write it to the boot disk\n\t\twhile read part start size; do\n\t\t\tif export_partdevice partdev $part; then\n\t\t\t\tv \"Writing image to /dev/$partdev...\"\n\t\t\t\tget_image_dd \"$1\" of=\"/dev/$partdev\" ibs=\"512\" obs=1M skip=\"$start\" count=\"$size\" conv=fsync\n\t\t\telse\n\t\t\t\tv \"Unable to find partition $part device, skipped.\"\n\t\t\tfi\n\t\tdone < /tmp/partmap.image\n\n\t\tv \"Writing new UUID to /dev/$diskdev...\"\n\t\tget_image_dd \"$1\" of=\"/dev/$diskdev\" bs=1 skip=440 count=4 seek=440 conv=fsync\n\tfi\n\n\tsleep 1\n}\n\nlegacy_sdcard_copy_config() {\n\tlocal partdev\n\n\tif export_partdevice partdev 1; then\n\t\tmkdir -p /boot\n\t\t[ -f /boot/kernel.img ] || mount -o rw,noatime /dev/$partdev /boot\n\t\tcp -af \"$UPGRADE_BACKUP\" \"/boot/$BACKUP_FILE\"\n\t\tsync\n\t\tumount /boot\n\tfi\n}\n"
  },
  {
    "path": "package/base-files/files/lib/upgrade/nand.sh",
    "content": "# Copyright (C) 2014 OpenWrt.org\n#\n\n. /lib/functions.sh\n\n# 'kernel' partition or UBI volume on NAND contains the kernel\nCI_KERNPART=\"${CI_KERNPART:-kernel}\"\n\n# 'ubi' partition on NAND contains UBI\nCI_UBIPART=\"${CI_UBIPART:-ubi}\"\n\n# 'rootfs' UBI volume on NAND contains the rootfs\nCI_ROOTPART=\"${CI_ROOTPART:-rootfs}\"\n\nubi_mknod() {\n\tlocal dir=\"$1\"\n\tlocal dev=\"/dev/$(basename $dir)\"\n\n\t[ -e \"$dev\" ] && return 0\n\n\tlocal devid=\"$(cat $dir/dev)\"\n\tlocal major=\"${devid%%:*}\"\n\tlocal minor=\"${devid##*:}\"\n\tmknod \"$dev\" c $major $minor\n}\n\nnand_find_volume() {\n\tlocal ubidevdir ubivoldir\n\tubidevdir=\"/sys/devices/virtual/ubi/$1\"\n\t[ ! -d \"$ubidevdir\" ] && return 1\n\tfor ubivoldir in $ubidevdir/${1}_*; do\n\t\t[ ! -d \"$ubivoldir\" ] && continue\n\t\tif [ \"$( cat $ubivoldir/name )\" = \"$2\" ]; then\n\t\t\tbasename $ubivoldir\n\t\t\tubi_mknod \"$ubivoldir\"\n\t\t\treturn 0\n\t\tfi\n\tdone\n}\n\nnand_find_ubi() {\n\tlocal ubidevdir ubidev mtdnum\n\tmtdnum=\"$( find_mtd_index $1 )\"\n\t[ ! \"$mtdnum\" ] && return 1\n\tfor ubidevdir in /sys/devices/virtual/ubi/ubi*; do\n\t\t[ ! -d \"$ubidevdir\" ] && continue\n\t\tcmtdnum=\"$( cat $ubidevdir/mtd_num )\"\n\t\t[ ! \"$mtdnum\" ] && continue\n\t\tif [ \"$mtdnum\" = \"$cmtdnum\" ]; then\n\t\t\tubidev=$( basename $ubidevdir )\n\t\t\tubi_mknod \"$ubidevdir\"\n\t\t\techo $ubidev\n\t\t\treturn 0\n\t\tfi\n\tdone\n}\n\nnand_get_magic_long() {\n\tdd if=\"$1\" skip=$2 bs=4 count=1 2>/dev/null | hexdump -v -n 4 -e '1/1 \"%02x\"'\n}\n\nget_magic_long_tar() {\n\t( tar xf $1 $2 -O | dd bs=4 count=1 | hexdump -v -n 4 -e '1/1 \"%02x\"') 2> /dev/null\n}\n\nidentify_magic() {\n\tlocal magic=$1\n\tcase \"$magic\" in\n\t\t\"55424923\")\n\t\t\techo \"ubi\"\n\t\t\t;;\n\t\t\"31181006\")\n\t\t\techo \"ubifs\"\n\t\t\t;;\n\t\t\"68737173\")\n\t\t\techo \"squashfs\"\n\t\t\t;;\n\t\t\"d00dfeed\")\n\t\t\techo \"fit\"\n\t\t\t;;\n\t\t\"4349\"*)\n\t\t\techo \"combined\"\n\t\t\t;;\n\t\t*)\n\t\t\techo \"unknown $magic\"\n\t\t\t;;\n\tesac\n}\n\n\nidentify() {\n\tidentify_magic $(nand_get_magic_long \"$1\" \"${2:-0}\")\n}\n\nidentify_tar() {\n\tidentify_magic $(get_magic_long_tar \"$1\" \"$2\")\n}\n\nnand_restore_config() {\n\tlocal ubidev=$( nand_find_ubi \"$CI_UBIPART\" )\n\tlocal ubivol=\"$( nand_find_volume $ubidev rootfs_data )\"\n\tif [ ! \"$ubivol\" ]; then\n\t\tubivol=\"$( nand_find_volume $ubidev \"$CI_ROOTPART\" )\"\n\t\tif [ ! \"$ubivol\" ]; then\n\t\t\techo \"cannot find ubifs data volume\"\n\t\t\treturn 1\n\t\tfi\n\tfi\n\tmkdir /tmp/new_root\n\tif ! mount -t ubifs /dev/$ubivol /tmp/new_root; then\n\t\techo \"cannot mount ubifs volume $ubivol\"\n\t\trmdir /tmp/new_root\n\t\treturn 1\n\tfi\n\tif mv \"$1\" \"/tmp/new_root/$BACKUP_FILE\"; then\n\t\tif umount /tmp/new_root; then\n\t\t\techo \"configuration saved\"\n\t\t\trmdir /tmp/new_root\n\t\t\treturn 0\n\t\tfi\n\telse\n\t\tumount /tmp/new_root\n\tfi\n\techo \"could not save configuration to ubifs volume $ubivol\"\n\trmdir /tmp/new_root\n\treturn 1\n}\n\nnand_remove_ubiblock() {\n\tlocal ubivol=$1\n\tlocal ubiblk=ubiblock${ubivol:3}\n\tif [ -e /dev/$ubiblk ]; then\n\t\techo \"removing $ubiblk\"\n\t\tif ! ubiblock -r /dev/$ubivol; then\n\t\t\techo \"cannot remove $ubiblk\"\n\t\t\treturn 1\n\t\tfi\n\tfi\n}\n\nnand_upgrade_prepare_ubi() {\n\tlocal rootfs_length=\"$1\"\n\tlocal rootfs_type=\"$2\"\n\tlocal rootfs_data_max=\"$(fw_printenv -n rootfs_data_max 2>/dev/null)\"\n\t[ -n \"$rootfs_data_max\" ] && rootfs_data_max=$((rootfs_data_max))\n\n\tlocal kernel_length=\"$3\"\n\tlocal has_env=\"${4:-0}\"\n\n\t[ -n \"$rootfs_length\" -o -n \"$kernel_length\" ] || return 1\n\n\tlocal mtdnum=\"$( find_mtd_index \"$CI_UBIPART\" )\"\n\tif [ ! \"$mtdnum\" ]; then\n\t\techo \"cannot find ubi mtd partition $CI_UBIPART\"\n\t\treturn 1\n\tfi\n\n\tlocal ubidev=\"$( nand_find_ubi \"$CI_UBIPART\" )\"\n\tif [ ! \"$ubidev\" ]; then\n\t\tubiattach -m \"$mtdnum\"\n\t\tubidev=\"$( nand_find_ubi \"$CI_UBIPART\" )\"\n\n\t\tif [ ! \"$ubidev\" ]; then\n\t\t\tubiformat /dev/mtd$mtdnum -y\n\t\t\tubiattach -m \"$mtdnum\"\n\t\t\tubidev=\"$( nand_find_ubi \"$CI_UBIPART\" )\"\n\n\t\t\tif [ ! \"$ubidev\" ]; then\n\t\t\t\techo \"cannot attach ubi mtd partition $CI_UBIPART\"\n\t\t\t\treturn 1\n\t\t\tfi\n\n\t\t\tif [ \"$has_env\" -gt 0 ]; then\n\t\t\t\tubimkvol /dev/$ubidev -n 0 -N ubootenv -s 1MiB\n\t\t\t\tubimkvol /dev/$ubidev -n 1 -N ubootenv2 -s 1MiB\n\t\t\tfi\n\t\tfi\n\tfi\n\n\tlocal kern_ubivol=\"$( nand_find_volume $ubidev \"$CI_KERNPART\" )\"\n\tlocal root_ubivol=\"$( nand_find_volume $ubidev \"$CI_ROOTPART\" )\"\n\tlocal data_ubivol=\"$( nand_find_volume $ubidev rootfs_data )\"\n\t[ \"$root_ubivol\" = \"$kern_ubivol\" ] && root_ubivol=\n\n\t# remove ubiblocks\n\t[ \"$kern_ubivol\" ] && { nand_remove_ubiblock $kern_ubivol || return 1; }\n\t[ \"$root_ubivol\" ] && { nand_remove_ubiblock $root_ubivol || return 1; }\n\t[ \"$data_ubivol\" ] && { nand_remove_ubiblock $data_ubivol || return 1; }\n\n\t# kill volumes\n\t[ \"$kern_ubivol\" ] && ubirmvol /dev/$ubidev -N \"$CI_KERNPART\" || :\n\t[ \"$root_ubivol\" ] && ubirmvol /dev/$ubidev -N \"$CI_ROOTPART\" || :\n\t[ \"$data_ubivol\" ] && ubirmvol /dev/$ubidev -N rootfs_data || :\n\n\t# create kernel vol\n\tif [ -n \"$kernel_length\" ]; then\n\t\tif ! ubimkvol /dev/$ubidev -N \"$CI_KERNPART\" -s $kernel_length; then\n\t\t\techo \"cannot create kernel volume\"\n\t\t\treturn 1;\n\t\tfi\n\tfi\n\n\t# create rootfs vol\n\tif [ -n \"$rootfs_length\" ]; then\n\t\tlocal rootfs_size_param\n\t\tif [ \"$rootfs_type\" = \"ubifs\" ]; then\n\t\t\trootfs_size_param=\"-m\"\n\t\telse\n\t\t\trootfs_size_param=\"-s $rootfs_length\"\n\t\tfi\n\t\tif ! ubimkvol /dev/$ubidev -N \"$CI_ROOTPART\" $rootfs_size_param; then\n\t\t\techo \"cannot create rootfs volume\"\n\t\t\treturn 1;\n\t\tfi\n\tfi\n\n\t# create rootfs_data vol for non-ubifs rootfs\n\tif [ \"$rootfs_type\" != \"ubifs\" ]; then\n\t\tlocal rootfs_data_size_param=\"-m\"\n\t\tif [ -n \"$rootfs_data_max\" ]; then\n\t\t\trootfs_data_size_param=\"-s $rootfs_data_max\"\n\t\tfi\n\t\tif ! ubimkvol /dev/$ubidev -N rootfs_data $rootfs_data_size_param; then\n\t\t\tif ! ubimkvol /dev/$ubidev -N rootfs_data -m; then\n\t\t\t\techo \"cannot initialize rootfs_data volume\"\n\t\t\t\treturn 1\n\t\t\tfi\n\t\tfi\n\tfi\n\n\treturn 0\n}\n\nnand_do_upgrade_success() {\n\tlocal conf_tar=\"/tmp/sysupgrade.tgz\"\n\tif { [ ! -f \"$conf_tar\" ] || nand_restore_config \"$conf_tar\"; } && sync; then\n\t\techo \"sysupgrade successful\"\n\tfi\n\tumount -a\n\treboot -f\n}\n\n# Flash the UBI image to MTD partition\nnand_upgrade_ubinized() {\n\tlocal ubi_file=\"$1\"\n\tlocal mtdnum=\"$(find_mtd_index \"$CI_UBIPART\")\"\n\n\tif [ ! \"$mtdnum\" ]; then\n\t\techo \"cannot find mtd device $CI_UBIPART\"\n\t\tumount -a\n\t\treboot -f\n\tfi\n\n\tlocal mtddev=\"/dev/mtd${mtdnum}\"\n\tubidetach -p \"${mtddev}\" || :\n\tubiformat \"${mtddev}\" -y -f \"${ubi_file}\"\n\tubiattach -p \"${mtddev}\"\n\n\tnand_do_upgrade_success\n}\n\n# Write the UBIFS image to UBI volume\nnand_upgrade_ubifs() {\n\tlocal rootfs_length=$( (cat $1 | wc -c) 2> /dev/null)\n\n\tnand_upgrade_prepare_ubi \"$rootfs_length\" \"ubifs\" \"\" \"\"\n\n\tlocal ubidev=\"$( nand_find_ubi \"$CI_UBIPART\" )\"\n\tlocal root_ubivol=\"$(nand_find_volume $ubidev \"$CI_ROOTPART\")\"\n\tubiupdatevol /dev/$root_ubivol -s $rootfs_length $1\n\n\tnand_do_upgrade_success\n}\n\nnand_upgrade_fit() {\n\tlocal fit_file=\"$1\"\n\tlocal fit_length=\"$(wc -c < \"$fit_file\")\"\n\n\tnand_upgrade_prepare_ubi \"\" \"\" \"$fit_length\" \"1\"\n\n\tlocal fit_ubidev=\"$(nand_find_ubi \"$CI_UBIPART\")\"\n\tlocal fit_ubivol=\"$(nand_find_volume $fit_ubidev \"$CI_KERNPART\")\"\n\tubiupdatevol /dev/$fit_ubivol -s $fit_length $fit_file\n\n\tnand_do_upgrade_success\n}\n\nnand_upgrade_tar() {\n\tlocal tar_file=\"$1\"\n\n\tlocal board_dir=\"$(tar tf \"$tar_file\" | grep -m 1 '^sysupgrade-.*/$')\"\n\tboard_dir=\"${board_dir%/}\"\n\n\tlocal kernel_mtd kernel_length\n\tif [ \"$CI_KERNPART\" != \"none\" ]; then\n\t\tkernel_mtd=\"$(find_mtd_index \"$CI_KERNPART\")\"\n\t\tkernel_length=$( (tar xf \"$tar_file\" \"$board_dir/kernel\" -O | wc -c) 2> /dev/null)\n\t\t[ \"$kernel_length\" = 0 ] && kernel_length=\n\tfi\n\tlocal rootfs_length=$( (tar xf \"$tar_file\" \"$board_dir/root\" -O | wc -c) 2> /dev/null)\n\t[ \"$rootfs_length\" = 0 ] && rootfs_length=\n\tlocal rootfs_type\n\t[ \"$rootfs_length\" ] && rootfs_type=\"$(identify_tar \"$tar_file\" \"$board_dir/root\")\"\n\n\tlocal ubi_kernel_length\n\tif [ \"$kernel_length\" ]; then\n\t\tif [ \"$kernel_mtd\" ]; then\n\t\t\t# On some devices, the raw kernel and ubi partitions overlap.\n\t\t\t# These devices brick if the kernel partition is erased.\n\t\t\t# Hence only invalidate kernel for now.\n\t\t\tdd if=/dev/zero bs=4096 count=1 2>/dev/null | \\\n\t\t\t\tmtd write - \"$CI_KERNPART\"\n\t\telse\n\t\t\tubi_kernel_length=\"$kernel_length\"\n\t\tfi\n\tfi\n\tlocal has_env=0\n\tnand_upgrade_prepare_ubi \"$rootfs_length\" \"$rootfs_type\" \"$ubi_kernel_length\" \"$has_env\"\n\n\tlocal ubidev=\"$( nand_find_ubi \"$CI_UBIPART\" )\"\n\tif [ \"$rootfs_length\" ]; then\n\t\tlocal root_ubivol=\"$( nand_find_volume $ubidev \"$CI_ROOTPART\" )\"\n\t\ttar xf \"$tar_file\" \"$board_dir/root\" -O | \\\n\t\t\tubiupdatevol /dev/$root_ubivol -s $rootfs_length -\n\tfi\n\tif [ \"$kernel_length\" ]; then\n\t\tif [ \"$kernel_mtd\" ]; then\n\t\t\ttar xf \"$tar_file\" \"$board_dir/kernel\" -O | \\\n\t\t\t\tmtd write - \"$CI_KERNPART\"\n\t\telse\n\t\t\tlocal kern_ubivol=\"$( nand_find_volume $ubidev \"$CI_KERNPART\" )\"\n\t\t\ttar xf \"$tar_file\" \"$board_dir/kernel\" -O | \\\n\t\t\t\tubiupdatevol /dev/$kern_ubivol -s $kernel_length -\n\t\tfi\n\tfi\n\n\tnand_do_upgrade_success\n}\n\n# Recognize type of passed file and start the upgrade process\nnand_do_upgrade() {\n\tlocal file_type=$(identify \"$1\")\n\n\t[ ! \"$(find_mtd_index \"$CI_UBIPART\")\" ] && CI_UBIPART=rootfs\n\n\tsync\n\tcase \"$file_type\" in\n\t\t\"fit\")\t\tnand_upgrade_fit \"$1\";;\n\t\t\"ubi\")\t\tnand_upgrade_ubinized \"$1\";;\n\t\t\"ubifs\")\tnand_upgrade_ubifs \"$1\";;\n\t\t*)\t\tnand_upgrade_tar \"$1\";;\n\tesac\n}\n\n# Check if passed file is a valid one for NAND sysupgrade. Currently it accepts\n# 3 types of files:\n# 1) UBI - should contain an ubinized image, header is checked for the proper\n#    MAGIC\n# 2) UBIFS - should contain UBIFS partition that will replace \"rootfs\" volume,\n#    header is checked for the proper MAGIC\n# 3) TAR - archive has to include \"sysupgrade-BOARD\" directory with a non-empty\n#    \"CONTROL\" file (at this point its content isn't verified)\n#\n# You usually want to call this function in platform_check_image.\n#\n# $(1): board name, used in case of passing TAR file\n# $(2): file to be checked\nnand_do_platform_check() {\n\tlocal board_name=\"$1\"\n\tlocal tar_file=\"$2\"\n\tlocal control_length=$( (tar xf $tar_file sysupgrade-$board_name/CONTROL -O | wc -c) 2> /dev/null)\n\tlocal file_type=\"$(identify $2)\"\n\n\t[ \"$control_length\" = 0 -a \"$file_type\" != \"ubi\" -a \"$file_type\" != \"ubifs\" -a \"$file_type\" != \"fit\" ] && {\n\t\techo \"Invalid sysupgrade file.\"\n\t\treturn 1\n\t}\n\n\treturn 0\n}\n"
  },
  {
    "path": "package/base-files/files/lib/upgrade/stage2",
    "content": "#!/bin/sh\n\n. /lib/functions.sh\n. /lib/functions/system.sh\n\nexport IMAGE=\"$1\"\nCOMMAND=\"$2\"\n\nexport INTERACTIVE=0\nexport VERBOSE=1\nexport CONFFILES=/tmp/sysupgrade.conffiles\n\nRAMFS_COPY_BIN=\t\t# extra programs for temporary ramfs root\nRAMFS_COPY_DATA=\t# extra data files\n\ninclude /lib/upgrade\n\n\nsupivot() { # <new_root> <old_root>\n\t/bin/mount | grep \"on $1 type\" 2>&- 1>&- || /bin/mount -o bind $1 $1\n\tmkdir -p $1$2 $1/proc $1/sys $1/dev $1/tmp $1/overlay && \\\n\t/bin/mount -o noatime,move /proc $1/proc && \\\n\tpivot_root $1 $1$2 || {\n\t\t/bin/umount -l $1 $1\n\t\treturn 1\n\t}\n\n\t/bin/mount -o noatime,move $2/sys /sys\n\t/bin/mount -o noatime,move $2/dev /dev\n\t/bin/mount -o noatime,move $2/tmp /tmp\n\t/bin/mount -o noatime,move $2/overlay /overlay 2>&-\n\treturn 0\n}\n\nswitch_to_ramfs() {\n\tRAMFS_COPY_LOSETUP=\"$(command -v /usr/sbin/losetup)\"\n\tRAMFS_COPY_LVM=\"$(command -v lvm)\"\n\n\tfor binary in \\\n\t\t/bin/busybox /bin/ash /bin/sh /bin/mount /bin/umount\t\\\n\t\tpivot_root mount_root reboot sync kill sleep\t\t\\\n\t\tmd5sum hexdump cat zcat dd tar\t\t\t\t\\\n\t\tls basename find cp mv rm mkdir rmdir mknod touch chmod \\\n\t\t'[' printf wc grep awk sed cut\t\t\t\t\\\n\t\tmtd partx losetup mkfs.ext4 nandwrite flash_erase\t\\\n\t\tubiupdatevol ubiattach ubiblock ubiformat\t\t\\\n\t\tubidetach ubirsvol ubirmvol ubimkvol\t\t\t\\\n\t\tsnapshot snapshot_tool date logger\t\t\t\\\n\t\t/usr/sbin/fw_printenv /usr/bin/fwtool\t\t\t\\\n\t\t$RAMFS_COPY_LOSETUP $RAMFS_COPY_LVM\t\t\t\\\n\t\t$RAMFS_COPY_BIN\n\tdo\n\t\tlocal file=\"$(command -v \"$binary\" 2>/dev/null)\"\n\t\t[ -n \"$file\" ] && install_bin \"$file\"\n\tdone\n\tinstall_file /etc/resolv.conf /lib/*.sh /lib/functions/*.sh\t\\\n\t\t/lib/upgrade/*.sh /lib/upgrade/do_stage2 \t\t\\\n\t\t/usr/share/libubox/jshn.sh /usr/sbin/fw_setenv\t\t\\\n\t\t/etc/fw_env.config $RAMFS_COPY_DATA\n\n\tmkdir -p $RAM_ROOT/var/lock\n\n\t[ -L \"/lib64\" ] && ln -s /lib $RAM_ROOT/lib64\n\n\tsupivot $RAM_ROOT /mnt || {\n\t\tv \"Failed to switch over to ramfs. Please reboot.\"\n\t\texit 1\n\t}\n\n\t/bin/mount -o remount,ro /mnt\n\t/bin/umount -l /mnt\n\n\tgrep -e \"^/dev/dm-.*\" -e \"^/dev/loop.*\" /proc/mounts | while read bdev mp _r; do\n\t\tumount $mp\n\tdone\n\n\t[ \"$RAMFS_COPY_LOSETUP\" ] && losetup -D\n\t[ \"$RAMFS_COPY_LVM\" ] && {\n\t\tmkdir -p /tmp/lvm/cache\n\t\t$RAMFS_COPY_LVM vgchange -aln --ignorelockingfailure\n\t}\n\n\tgrep /overlay /proc/mounts > /dev/null && {\n\t\t/bin/mount -o noatime,remount,ro /overlay\n\t\t/bin/umount -l /overlay\n\t}\n}\n\nkill_remaining() { # [ <signal> [ <loop> ] ]\n\tlocal loop_limit=10\n\n\tlocal sig=\"${1:-TERM}\"\n\tlocal loop=\"${2:-0}\"\n\tlocal run=true\n\tlocal stat\n\tlocal proc_ppid=$(cut -d' ' -f4  /proc/$$/stat)\n\n\tv \"Sending $sig to remaining processes ...\"\n\n\twhile $run; do\n\t\trun=false\n\t\tfor stat in /proc/[0-9]*/stat; do\n\t\t\t[ -f \"$stat\" ] || continue\n\n\t\t\tlocal pid name state ppid rest\n\t\t\tread pid rest < $stat\n\t\t\tname=\"${rest#\\(}\" ; rest=\"${name##*\\) }\" ; name=\"${name%\\)*}\"\n\t\t\tset -- $rest ; state=\"$1\" ; ppid=\"$2\"\n\n\t\t\t# Skip PID1, our parent, ourself and our children\n\t\t\t[ $pid -ne 1 -a $pid -ne $proc_ppid -a $pid -ne $$ -a $ppid -ne $$ ] || continue\n\n\t\t\t[ -f \"/proc/$pid/cmdline\" ] || continue\n\n\t\t\tlocal cmdline\n\t\t\tread cmdline < /proc/$pid/cmdline\n\n\t\t\t# Skip kernel threads\n\t\t\t[ -n \"$cmdline\" ] || continue\n\n\t\t\tv \"Sending signal $sig to $name ($pid)\"\n\t\t\tkill -$sig $pid 2>/dev/null\n\n\t\t\t[ $loop -eq 1 ] && run=true\n\t\tdone\n\n\t\tlet loop_limit--\n\t\t[ $loop_limit -eq 0 ] && {\n\t\t\tv \"Failed to kill all processes.\"\n\t\t\texit 1\n\t\t}\n\tdone\n}\n\nindicate_upgrade\n\nwhile read -r a b c; do\n\tcase \"$a\" in\n\t\tMemT*) mem=\"$b\" ;; esac\ndone < /proc/meminfo\n\n[ \"$mem\" -gt 32768 ] && \\\n\tskip_services=\"dnsmasq log network\"\nfor service in /etc/init.d/*; do\n\tservice=${service##*/}\n\n\tcase \" $skip_services \" in\n\t\t*\" $service \"*) continue ;; esac\n\n\tubus call service delete '{ \"name\": \"'\"$service\"'\" }' 2>/dev/null\ndone\n\nkillall -9 telnetd 2>/dev/null\nkillall -9 dropbear 2>/dev/null\nkillall -9 ash 2>/dev/null\n\nkill_remaining TERM\nsleep 4\nkill_remaining KILL 1\n\nsleep 6\n\necho 3 > /proc/sys/vm/drop_caches\n\nif [ -n \"$IMAGE\" ] && type 'platform_pre_upgrade' >/dev/null 2>/dev/null; then\n\tplatform_pre_upgrade \"$IMAGE\"\nfi\n\nif [ -n \"$(rootfs_type)\" ]; then\n\tv \"Switching to ramdisk...\"\n\tswitch_to_ramfs\nfi\n\n# Exec new shell from ramfs\nexec /bin/busybox ash -c \"$COMMAND\"\n"
  },
  {
    "path": "package/base-files/files/rom/note",
    "content": "SQUASHFS USERS:\nAfter firstboot has been run, / will be jffs2 and /rom will be squashfs\n(* except when in failsafe)\n"
  },
  {
    "path": "package/base-files/files/sbin/firstboot",
    "content": "#!/bin/sh\n\n/sbin/jffs2reset $@\n"
  },
  {
    "path": "package/base-files/files/sbin/hotplug-call",
    "content": "#!/bin/sh\n# Copyright (C) 2006-2016 OpenWrt.org\n\nexport HOTPLUG_TYPE=\"$1\"\n\n. /lib/functions.sh\n\nPATH=\"%PATH%\"\nLOGNAME=root\nUSER=root\nexport PATH LOGNAME USER\nexport DEVICENAME=\"${DEVPATH##*/}\"\n\nif [ \\! -z \"$1\" -a -d /etc/hotplug.d/$1 ]; then\n\tfor script in $(ls /etc/hotplug.d/$1/* 2>&-); do (\n\t\t[ -f $script ] && . $script\n\t); done\nfi\n"
  },
  {
    "path": "package/base-files/files/sbin/led.sh",
    "content": "#!/bin/sh\n# (C) 2008 openwrt.org\n\n. /lib/functions.sh\nACTION=$1\nNAME=$2\ndo_led() {\n\tlocal name\n\tlocal sysfs\n\tconfig_get name $1 name\n\tconfig_get sysfs $1 sysfs\n\t[ \"$name\" = \"$NAME\" -o \"$sysfs\" = \"$NAME\" -a -e \"/sys/class/leds/${sysfs}\" ] && {\n\t\t[ \"$ACTION\" = \"set\" ] &&\n\t\t\techo 1 >/sys/class/leds/${sysfs}/brightness \\\n\t\t\t|| echo 0 >/sys/class/leds/${sysfs}/brightness\n\t\texit 0\n\t}\n}\n\n[ \"$1\" = \"clear\" -o \"$1\" = \"set\" ] &&\n\t[ -n \"$2\" ] &&{\n\t\tconfig_load system\n\t\tconfig_foreach do_led\n\t\texit 1\n\t}\n"
  },
  {
    "path": "package/base-files/files/sbin/pkg_check",
    "content": "#!/bin/sh\n#\n# Package checksums checking script\n# (C) 2018 CZ.NIC, z.s.p.o.\n#\n# This program is free software: you can redistribute it and/or modify\n# it under the terms of the GNU General Public License as published by\n# the Free Software Foundation, either version 3 of the License, or\n# (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n# GNU General Public License for more details.\n#\n# You should have received a copy of the GNU General Public License\n# along with this program.  If not, see <http://www.gnu.org/licenses/>.\n\n\nERRFATAL=\"no\"\nQUIET=\"yes\"\nMISSING=\"\"\nSUMMARY=\"\"\nNL=\"\n\"\n\n# Arguments parsing\nwhile expr \"x$1\" : \"x-\" > /dev/null; do\n\tif [ \"x$1\" = \"x-s\" ]; then\n\t\tERRFATAL=\"yes\"\n\t\tshift\n\telif [ \"x$1\" = \"x-v\" ]; then\n\t\tQUIET=\"\tno\"\n\t\tshift\n\telse\n\t\techo \"Usage: $(basename $0) [-s] [-v] [pkg1 pkg2 ...]\"\n\t\techo\n\t\techo \"   -s   Stop on first change\"\n\t\techo \"   -v   Verbose\"\n\t\tif [ \"x$1\" = \"x-h\" ]; then\n\t\t\texit 0\n\t\telse\n\t\t\techo\n\t\t\techo \"ERROR: Unknown option '$1'\"\n\t\t\texit 1\n\t\tfi\n\tfi\ndone\n\n# Check all packages by default\nif [ -z \"$1\" ]; then\n\tset $(cd /usr/lib/opkg/info/; for i in *.files-sha256sum; do basename $i .files-sha256sum; done)\nfi\n\n# Iterate over packages\nwhile [ \"$1\" ]; do\n\tif [ \\! -f \"/usr/lib/opkg/info/$1.files-sha256sum\" ]; then\n\t\tif [ \"$ERRFATAL\" = no ]; then\n\t\t\techo \" * No checksums for $1 - skipping\"\n\t\t\techo\n\t\telse\n\t\t\techo \" * No checksums for $1 - exiting\"\n\t\t\texit 1\n\t\tfi\n\t\tif [ -z \"$MISSING\" ]; then\n\t\t\tMISSING=\"$1\"\n\t\telse\n\t\t\tMISSING=\"$MISSING, $1\"\n\t\tfi\n\t\tshift\n\t\tcontinue\n\tfi\n\t[ $QUIET = yes ] || echo \" * Checking package $1:\"\n\tERR=\"\"\n\tCHECK=\"$(sha256sum -c /usr/lib/opkg/info/$1.files-sha256sum 2> /dev/null)\"\n\n\t# Are the changed files config files?\n\tif [ $? -ne 0 ] && [ \"$(cat \"/usr/lib/opkg/info/$1.files-sha256sum\")\" ]; then\n\t\tNEWCHECK=\"$(echo \"$CHECK\" | grep '^.*: OK$')\"\n\t\tfor i in $(echo \"$CHECK\" | sed -n 's|^\\(.*\\): FAILED$|\\1|p'); do\n\t\t\tif [ \"$(grep \"^$i\\$\" \"/usr/lib/opkg/info/$1.conffiles\" 2> /dev/null)\" ] || \\\n\t\t\t   [ \"$(echo \"$i\" | grep \"^/etc/uci-defaults/\")\" ]; then\n\t\t\t\tNEWCHECK=\"${NEWCHECK}${NL}${i}: CONFIGURED\"\n\t\t\telse\n\t\t\t\tNEWCHECK=\"${NEWCHECK}${NL}${i}: FAILED\"\n\t\t\t\tERR=\"y\"\n\t\t\tfi\n\t\tdone\n\t\tCHECK=\"$NEWCHECK\"\n\tfi\n\n\t# Do we have changed files or not?\n\tif [ -z \"$ERR\" ]; then\n\t\t[ $QUIET = yes ] || [ ! -s \"/usr/lib/opkg/info/$1.files-sha256sum\" ] || echo \"$CHECK\" | sed 's|^|   - |'\n\t\t[ $QUIET = yes ] || echo \" * Package $1 is ok\"\n\t\t[ $QUIET = yes ] || echo\n\telse\n\t\tif [ $QUIET = yes ]; then\n\t\t\techo \" * Changes found in package $1:\"\n\t\t\techo \"$CHECK\" | sed -n 's|^\\(.*:[[:blank:]]*FAILED\\)$|   - \\1|p'\n\t\telse\n\t\t\techo \"$CHECK\" | sed 's|^|   - |'\n\t\t\techo \" * Changes found in package $1!\"\n\t\tfi\n\t\tif [ \"$ERRFATAL\" = yes ]; then\n\t\t\techo\n\t\t\techo \"Exiting on first change found!\"\n\t\t\texit 1\n\t\tfi\n\t\tfor i in $(echo \"$CHECK\" | sed -n 's|^\\(.*\\): FAILED$|\\1|p'); do\n\t\t\tSUMMARY=\"${SUMMARY}${NL} - $1: $i\"\n\t\tdone\n\t\techo\n\tfi\n\tshift\ndone\n\n# If there are changed files, report them\nif [ \"$SUMMARY\" ]; then\n\techo \"Some packages contain changed files!\"\n\techo \"Maybe something worth looking into?\"\n\techo \"Here is the list of packages and changed files:\"\n\techo \"$SUMMARY\"\nfi\nif [ \"$MISSING\" ]; then\n\techo \"Following packages are missing checksums: $MISSING\"\nfi\nif [ \"$MISSING\" ] || [ \"$SUMMARY\" ]; then\n\texit 1\nfi\n"
  },
  {
    "path": "package/base-files/files/sbin/sysupgrade",
    "content": "#!/bin/sh\n\n. /lib/functions.sh\n. /lib/functions/system.sh\n. /usr/share/libubox/jshn.sh\n\n# initialize defaults\nexport MTD_ARGS=\"\"\nexport MTD_CONFIG_ARGS=\"\"\nexport INTERACTIVE=0\nexport VERBOSE=1\nexport SAVE_CONFIG=1\nexport SAVE_OVERLAY=0\nexport SAVE_OVERLAY_PATH=\nexport SAVE_PARTITIONS=1\nexport SAVE_INSTALLED_PKGS=0\nexport SKIP_UNCHANGED=0\nexport CONF_IMAGE=\nexport CONF_BACKUP_LIST=0\nexport CONF_BACKUP=\nexport CONF_RESTORE=\nexport NEED_IMAGE=\nexport HELP=0\nexport FORCE=0\nexport TEST=0\nexport UMOUNT_ETCBACKUP_DIR=0\n\n# parse options\nwhile [ -n \"$1\" ]; do\n\tcase \"$1\" in\n\t\t-i) export INTERACTIVE=1;;\n\t\t-v) export VERBOSE=\"$(($VERBOSE + 1))\";;\n\t\t-q) export VERBOSE=\"$(($VERBOSE - 1))\";;\n\t\t-n) export SAVE_CONFIG=0;;\n\t\t-c) export SAVE_OVERLAY=1 SAVE_OVERLAY_PATH=/etc;;\n\t\t-o) export SAVE_OVERLAY=1 SAVE_OVERLAY_PATH=/;;\n\t\t-p) export SAVE_PARTITIONS=0;;\n\t\t-k) export SAVE_INSTALLED_PKGS=1;;\n\t\t-u) export SKIP_UNCHANGED=1;;\n\t\t-b|--create-backup) export CONF_BACKUP=\"$2\" NEED_IMAGE=1; shift;;\n\t\t-r|--restore-backup) export CONF_RESTORE=\"$2\" NEED_IMAGE=1; shift;;\n\t\t-l|--list-backup) export CONF_BACKUP_LIST=1;;\n\t\t-f) export CONF_IMAGE=\"$2\"; shift;;\n\t\t-F|--force) export FORCE=1;;\n\t\t-T|--test) export TEST=1;;\n\t\t-h|--help) export HELP=1; break;;\n\t\t-*)\n\t\t\techo \"Invalid option: $1\" >&2\n\t\t\texit 1\n\t\t;;\n\t\t*) break;;\n\tesac\n\tshift;\ndone\n\nexport CONFFILES=/tmp/sysupgrade.conffiles\nexport CONF_TAR=/tmp/sysupgrade.tgz\nexport ETCBACKUP_DIR=/etc/backup\nexport INSTALLED_PACKAGES=${ETCBACKUP_DIR}/installed_packages.txt\n\nIMAGE=\"$1\"\n\n[ -z \"$IMAGE\" -a -z \"$NEED_IMAGE\" -a $CONF_BACKUP_LIST -eq 0 -o $HELP -gt 0 ] && {\n\tcat <<EOF\nUsage: $0 [<upgrade-option>...] <image file or URL>\n       $0 [-q] [-i] [-c] [-u] [-o] [-k] <backup-command> <file>\n\nupgrade-option:\n\t-f <config>  restore configuration from .tar.gz (file or url)\n\t-i           interactive mode\n\t-c           attempt to preserve all changed files in /etc/\n\t-o           attempt to preserve all changed files in /, except those\n\t             from packages but including changed confs.\n\t-u           skip from backup files that are equal to those in /rom\n\t-n           do not save configuration over reflash\n\t-p           do not attempt to restore the partition table after flash.\n\t-k           include in backup a list of current installed packages at\n\t             $INSTALLED_PACKAGES\n\t-T | --test\n\t             Verify image and config .tar.gz but do not actually flash.\n\t-F | --force\n\t             Flash image even if image checks fail, this is dangerous!\n\t-q           less verbose\n\t-v           more verbose\n\t-h | --help  display this help\n\nbackup-command:\n\t-b | --create-backup <file>\n\t             create .tar.gz of files specified in sysupgrade.conf\n\t             then exit. Does not flash an image. If file is '-',\n\t             i.e. stdout, verbosity is set to 0 (i.e. quiet).\n\t-r | --restore-backup <file>\n\t             restore a .tar.gz created with sysupgrade -b\n\t             then exit. Does not flash an image. If file is '-',\n\t             the archive is read from stdin.\n\t-l | --list-backup\n\t             list the files that would be backed up when calling\n\t             sysupgrade -b. Does not create a backup file.\n\nEOF\n\texit 1\n}\n\n[ -n \"$IMAGE\" -a -n \"$NEED_IMAGE\" ] && {\n\tcat <<-EOF\n\t\t-b|--create-backup and -r|--restore-backup do not perform a firmware upgrade.\n\t\tDo not specify both -b|-r and a firmware image.\n\tEOF\n\texit 1\n}\n\n# prevent messages from clobbering the tarball when using stdout\n[ \"$CONF_BACKUP\" = \"-\" ] && export VERBOSE=0\n\n\nlist_conffiles() {\n\tawk '\n\t\tBEGIN { conffiles = 0 }\n\t\t/^Conffiles:/ { conffiles = 1; next }\n\t\t!/^ / { conffiles = 0; next }\n\t\tconffiles == 1 { print }\n\t' /usr/lib/opkg/status\n}\n\nlist_changed_conffiles() {\n\t# Cannot handle spaces in filenames - but opkg cannot either...\n\tlist_conffiles | while read file csum; do\n\t\t[ -r \"$file\" ] || continue\n\n\t\techo \"${csum}  ${file}\" | busybox sha256sum -sc - || echo \"$file\"\n\tdone\n}\n\nlist_static_conffiles() {\n\tlocal filter=$1\n\n\tfind $(sed -ne '/^[[:space:]]*$/d; /^#/d; p' \\\n\t\t/etc/sysupgrade.conf /lib/upgrade/keep.d/* 2>/dev/null) \\\n\t\t\\( -type f -o -type l \\) $filter 2>/dev/null\n}\n\nadd_conffiles() {\n\tlocal file=\"$1\"\n\n\t( list_static_conffiles \"$find_filter\"; list_changed_conffiles ) |\n\t\tsort -u > \"$file\"\n\treturn 0\n}\n\nadd_overlayfiles() {\n\tlocal file=\"$1\"\n\n\tlocal packagesfiles=$1.packagesfiles\n\ttouch \"$packagesfiles\"\n\n\tif [ \"$SAVE_OVERLAY_PATH\" = / ]; then\n\t\tlocal conffiles=$1.conffiles\n\t\tlocal keepfiles=$1.keepfiles\n\n\t\tlist_conffiles | cut -f2 -d ' ' | sort -u > \"$conffiles\"\n\n\t\t# backup files from /etc/sysupgrade.conf and /lib/upgrade/keep.d, but\n\t\t# ignore those aready controlled by opkg conffiles\n\t\tlist_static_conffiles | sort -u |\n\t\t\tgrep -h -v -x -F -f $conffiles > \"$keepfiles\"\n\n\t\t# backup conffiles, but only those changed if '-u'\n\t\t[ $SKIP_UNCHANGED = 1 ] &&\n\t\t\tlist_changed_conffiles | sort -u > \"$conffiles\"\n\n\t\t# do not backup files from packages, except those listed\n\t\t# in conffiles and keep.d\n\t\t{\n\t\t\tfind /usr/lib/opkg/info -type f -name \"*.list\" -exec cat {} \\;\n\t\t\tfind /usr/lib/opkg/info -type f -name \"*.control\" -exec sed \\\n\t\t\t\t-ne '/^Alternatives/{s/^Alternatives: //;s/, /\\n/g;p}' {} \\; |\n\t\t\t\tcut -f2 -d:\n\t\t} |  grep -v -x -F -f $conffiles |\n\t\t     grep -v -x -F -f $keepfiles | sort -u > \"$packagesfiles\"\n\t\trm -f \"$keepfiles\" \"$conffiles\"\n\tfi\n\n\t# busybox grep bug when file is empty\n\t[ -s \"$packagesfiles\" ] || echo > $packagesfiles\n\n\t( cd /overlay/upper/; find .$SAVE_OVERLAY_PATH \\( -type f -o -type l \\) $find_filter | sed \\\n\t\t-e 's,^\\.,,' \\\n\t\t-e '\\,^/etc/board.json$,d' \\\n\t\t-e '\\,/[^/]*-opkg$,d' \\\n\t\t-e '\\,^/etc/urandom.seed$,d' \\\n\t\t-e \"\\,^$INSTALLED_PACKAGES$,d\" \\\n\t\t-e '\\,^/usr/lib/opkg/.*,d' \\\n\t) | grep -v -x -F -f $packagesfiles > \"$file\"\n\n\trm -f \"$packagesfiles\"\n\n\treturn 0\n}\n\nif [ $SAVE_OVERLAY = 1 ]; then\n\t[ ! -d /overlay/upper/etc ] && {\n\t\techo \"Cannot find '/overlay/upper/etc', required for '-c'\" >&2\n\t\texit 1\n\t}\n\tsysupgrade_init_conffiles=\"add_overlayfiles\"\nelse\n\tsysupgrade_init_conffiles=\"add_conffiles\"\nfi\n\nfind_filter=\"\"\nif [ $SKIP_UNCHANGED = 1 ]; then\n\t[ ! -d /rom/ ] && {\n\t\techo \"'/rom/' is required by '-u'\"\n\t\texit 1\n\t}\n\tfind_filter='( ( -exec test -e /rom/{} ; -exec cmp -s /{} /rom/{} ; ) -o -print )'\nfi\n\ninclude /lib/upgrade\n\ndo_save_conffiles() {\n\tlocal conf_tar=\"$1\"\n\n\t[ \"$(rootfs_type)\" = \"tmpfs\" ] && {\n\t\techo \"Cannot save config while running from ramdisk.\" >&2\n\t\task_bool 0 \"Abort\" && exit\n\t\trm -f \"$conf_tar\"\n\t\treturn 0\n\t}\n\trun_hooks \"$CONFFILES\" $sysupgrade_init_conffiles\n\task_bool 0 \"Edit config file list\" && vi \"$CONFFILES\"\n\n\tif [ \"$SAVE_INSTALLED_PKGS\" -eq 1 ]; then\n\t\techo \"${INSTALLED_PACKAGES}\" >> \"$CONFFILES\"\n\t\tmkdir -p \"$ETCBACKUP_DIR\"\n\t\t# Avoid touching filesystem on each backup\n\t\tRAMFS=\"$(mktemp -d -t sysupgrade.XXXXXX)\"\n\t\tmkdir -p \"$RAMFS/upper\" \"$RAMFS/work\"\n\t\tmount -t overlay overlay -o lowerdir=$ETCBACKUP_DIR,upperdir=$RAMFS/upper,workdir=$RAMFS/work $ETCBACKUP_DIR &&\n\t\t\tUMOUNT_ETCBACKUP_DIR=1 || {\n\t\t\t\techo \"Cannot mount '$ETCBACKUP_DIR' as tmpfs to avoid touching disk while saving the list of installed packages.\" >&2\n\t\t\t\task_bool 0 \"Abort\" && exit\n\t\t\t}\n\n\t\t# Format: pkg-name<TAB>{rom,overlay,unkown}\n\t\t# rom is used for pkgs in /rom, even if updated later\n\t\tfind /usr/lib/opkg/info -name \"*.control\" \\( \\\n\t\t\t\\( -exec test -f /rom/{} \\; -exec echo {} rom \\; \\) -o \\\n\t\t\t\\( -exec test -f /overlay/upper/{} \\; -exec echo {} overlay \\; \\) -o \\\n\t\t\t\\( -exec echo {} unknown \\; \\) \\\n\t\t\t\\) | sed -e 's,.*/,,;s/\\.control /\\t/' > ${INSTALLED_PACKAGES}\n\tfi\n\n\tv \"Saving config files...\"\n\t[ \"$VERBOSE\" -gt 1 ] && TAR_V=\"v\" || TAR_V=\"\"\n\ttar c${TAR_V}zf \"$conf_tar\" -T \"$CONFFILES\" 2>/dev/null\n\tif [ \"$?\" -ne 0 ]; then\n\t\techo \"Failed to create the configuration backup.\"\n\t\trm -f \"$conf_tar\"\n\t\texit 1\n\tfi\n\n\t[ \"$UMOUNT_ETCBACKUP_DIR\" -eq 1 ] && {\n\t\tumount \"$ETCBACKUP_DIR\"\n\t\trm -rf \"$RAMFS\"\n\t}\n\trm -f \"$CONFFILES\"\n}\n\nif [ $CONF_BACKUP_LIST -eq 1 ]; then\n\trun_hooks \"$CONFFILES\" $sysupgrade_init_conffiles\n\t[ \"$SAVE_INSTALLED_PKGS\" -eq 1 ] && echo ${INSTALLED_PACKAGES} >> \"$CONFFILES\"\n\tcat \"$CONFFILES\"\n\trm -f \"$CONFFILES\"\n\texit 0\nfi\n\nif [ -n \"$CONF_BACKUP\" ]; then\n\tdo_save_conffiles \"$CONF_BACKUP\"\n\texit $?\nfi\n\nif [ -n \"$CONF_RESTORE\" ]; then\n\tif [ \"$CONF_RESTORE\" != \"-\" ] && [ ! -f \"$CONF_RESTORE\" ]; then\n\t\techo \"Backup archive '$CONF_RESTORE' not found.\" >&2\n\t\texit 1\n\tfi\n\n\t[ \"$VERBOSE\" -gt 1 ] && TAR_V=\"v\" || TAR_V=\"\"\n\tv \"Restoring config files...\"\n\ttar -C / -x${TAR_V}zf \"$CONF_RESTORE\"\n\texit $?\nfi\n\ntype platform_check_image >/dev/null 2>/dev/null || {\n\techo \"Firmware upgrade is not implemented for this platform.\" >&2\n\texit 1\n}\n\ncase \"$IMAGE\" in\n\thttp://*|\\\n\thttps://*)\n\t\twget -O/tmp/sysupgrade.img \"$IMAGE\" || exit 1\n\t\tIMAGE=/tmp/sysupgrade.img\n\t\t;;\nesac\n\nIMAGE=\"$(readlink -f \"$IMAGE\")\"\n\ncase \"$IMAGE\" in\n\t'')\n\t\techo \"Image file not found.\" >&2\n\t\texit 1\n\t\t;;\n\t/tmp/*)\t;;\n\t*)\n\t\tv \"Image not in /tmp, copying...\"\n\t\tcp -f \"$IMAGE\" /tmp/sysupgrade.img\n\t\tIMAGE=/tmp/sysupgrade.img\n\t\t;;\nesac\n\njson_load \"$(/usr/libexec/validate_firmware_image \"$IMAGE\")\" || {\n\techo \"Failed to check image\"\n\texit 1\n}\njson_get_var valid \"valid\"\n[ \"$valid\" -eq 0 ] && {\n\tif [ $FORCE -eq 1 ]; then\n\t\techo \"Image check failed but --force given - will update anyway!\" >&2\n\telse\n\t\techo \"Image check failed.\" >&2\n\t\texit 1\n\tfi\n}\n\nif [ -n \"$CONF_IMAGE\" ]; then\n\tcase \"$(get_magic_word $CONF_IMAGE cat)\" in\n\t\t# .gz files\n\t\t1f8b) ;;\n\t\t*)\n\t\t\techo \"Invalid config file. Please use only .tar.gz files\" >&2\n\t\t\texit 1\n\t\t;;\n\tesac\n\tget_image \"$CONF_IMAGE\" \"cat\" > \"$CONF_TAR\"\n\texport SAVE_CONFIG=1\nelif ask_bool $SAVE_CONFIG \"Keep config files over reflash\"; then\n\t[ $TEST -eq 1 ] || do_save_conffiles \"$CONF_TAR\"\n\texport SAVE_CONFIG=1\nelse\n\t[ $TEST -eq 1 ] || rm -f \"$CONF_TAR\"\n\texport SAVE_CONFIG=0\nfi\n\nif [ $TEST -eq 1 ]; then\n\texit 0\nfi\n\ninstall_bin /sbin/upgraded\nv \"Commencing upgrade. Closing all shell sessions.\"\n\nCOMMAND='/lib/upgrade/do_stage2'\n\nif [ -n \"$FAILSAFE\" ]; then\n\tprintf '%s\\x00%s\\x00%s' \"$RAM_ROOT\" \"$IMAGE\" \"$COMMAND\" >/tmp/sysupgrade\n\tlock -u /tmp/.failsafe\nelse\n\tjson_init\n\tjson_add_string prefix \"$RAM_ROOT\"\n\tjson_add_string path \"$IMAGE\"\n\t[ $FORCE -eq 1 ] && json_add_boolean force 1\n\t[ $SAVE_CONFIG -eq 1 ] && json_add_string backup \"$CONF_TAR\"\n\tjson_add_string command \"$COMMAND\"\n\tjson_add_object options\n\tjson_add_int save_partitions \"$SAVE_PARTITIONS\"\n\tjson_close_object\n\n\tubus call system sysupgrade \"$(json_dump)\"\nfi\n"
  },
  {
    "path": "package/base-files/files/sbin/wifi",
    "content": "#!/bin/sh\n# Copyright (C) 2006 OpenWrt.org\n\n. /lib/functions.sh\n. /usr/share/libubox/jshn.sh\n\nusage() {\n\tcat <<EOF\nUsage: $0 [config|up|down|reconf|reload|status]\nenables (default), disables or configures devices not yet configured.\nEOF\n\texit 1\n}\n\nubus_wifi_cmd() {\n\tlocal cmd=\"$1\"\n\tlocal dev=\"$2\"\n\n\tjson_init\n\t[ -n \"$2\" ] && json_add_string device \"$2\"\n\tubus call network.wireless \"$1\" \"$(json_dump)\"\n}\n\nfind_net_config() {(\n\tlocal vif=\"$1\"\n\tlocal cfg\n\tlocal ifname\n\n\tconfig_get cfg \"$vif\" network\n\n\t[ -z \"$cfg\" ] && {\n\t\tinclude /lib/network\n\t\tscan_interfaces\n\n\t\tconfig_get ifname \"$vif\" ifname\n\n\t\tcfg=\"$(find_config \"$ifname\")\"\n\t}\n\t[ -z \"$cfg\" ] && return 0\n\techo \"$cfg\"\n)}\n\n\nbridge_interface() {(\n\tlocal cfg=\"$1\"\n\t[ -z \"$cfg\" ] && return 0\n\n\tinclude /lib/network\n\tscan_interfaces\n\n\tfor cfg in $cfg; do\n\t\tconfig_get iftype \"$cfg\" type\n\t\t[ \"$iftype\" = bridge ] && config_get \"$cfg\" ifname\n\t\tprepare_interface_bridge \"$cfg\"\n\t\treturn $?\n\tdone\n)}\n\nprepare_key_wep() {\n\tlocal key=\"$1\"\n\tlocal hex=1\n\n\techo -n \"$key\" | grep -qE \"[^a-fA-F0-9]\" && hex=0\n\t[ \"${#key}\" -eq 10 -a $hex -eq 1 ] || \\\n\t[ \"${#key}\" -eq 26 -a $hex -eq 1 ] || {\n\t\t[ \"${key:0:2}\" = \"s:\" ] && key=\"${key#s:}\"\n\t\tkey=\"$(echo -n \"$key\" | hexdump -ve '1/1 \"%02x\" \"\"')\"\n\t}\n\techo \"$key\"\n}\n\nwifi_fixup_hwmode() {\n\tlocal device=\"$1\"\n\tlocal default=\"$2\"\n\tlocal hwmode hwmode_11n\n\n\tconfig_get channel \"$device\" channel\n\tconfig_get hwmode \"$device\" hwmode\n\tcase \"$hwmode\" in\n\t\t11bg) hwmode=bg;;\n\t\t11a) hwmode=a;;\n\t\t11ad) hwmode=ad;;\n\t\t11b) hwmode=b;;\n\t\t11g) hwmode=g;;\n\t\t11n*)\n\t\t\thwmode_11n=\"${hwmode##11n}\"\n\t\t\tcase \"$hwmode_11n\" in\n\t\t\t\ta|g) ;;\n\t\t\t\tdefault) hwmode_11n=\"$default\"\n\t\t\tesac\n\t\t\tconfig_set \"$device\" hwmode_11n \"$hwmode_11n\"\n\t\t;;\n\t\t*)\n\t\t\thwmode=\n\t\t\tif [ \"${channel:-0}\" -gt 0 ]; then\n\t\t\t\tif [ \"${channel:-0}\" -gt 14 ]; then\n\t\t\t\t\thwmode=a\n\t\t\t\telse\n\t\t\t\t\thwmode=g\n\t\t\t\tfi\n\t\t\telse\n\t\t\t\thwmode=\"$default\"\n\t\t\tfi\n\t\t;;\n\tesac\n\tconfig_set \"$device\" hwmode \"$hwmode\"\n}\n\n_wifi_updown() {\n\tfor device in ${2:-$DEVICES}; do (\n\t\tconfig_get disabled \"$device\" disabled\n\t\t[ \"$disabled\" = \"1\" ] && {\n\t\t\techo \"'$device' is disabled\"\n\t\t\tset disable\n\t\t}\n\t\tconfig_get iftype \"$device\" type\n\t\tif eval \"type ${1}_$iftype\" 2>/dev/null >/dev/null; then\n\t\t\teval \"scan_$iftype '$device'\"\n\t\t\teval \"${1}_$iftype '$device'\" || echo \"$device($iftype): ${1} failed\"\n\t\telif [ ! -f /lib/netifd/wireless/$iftype.sh ]; then\n\t\t\techo \"$device($iftype): Interface type not supported\"\n\t\tfi\n\t); done\n}\n\nwifi_updown() {\n\tcmd=down\n\t[ enable = \"$1\" ] && {\n\t\t_wifi_updown disable \"$2\"\n\t\tubus_wifi_cmd \"$cmd\" \"$2\"\n\t\tscan_wifi\n\t\tcmd=up\n\t\tubus call network reload\n\t}\n\t[ reconf = \"$1\" ] && {\n\t\tscan_wifi\n\t\tcmd=reconf\n\t\tubus call network reload\n\t}\n\tubus_wifi_cmd \"$cmd\" \"$2\"\n\t_wifi_updown \"$@\"\n}\n\nwifi_reload_legacy() {\n\t_wifi_updown \"disable\" \"$1\"\n\tscan_wifi\n\t_wifi_updown \"enable\" \"$1\"\n}\n\nwifi_reload() {\n\tubus call network reload\n\twifi_reload_legacy\n}\n\nwifi_detect_notice() {\n\t>&2 echo \"WARNING: Wifi detect is deprecated. Use wifi config instead\"\n\t>&2 echo \"For more information, see commit 5f8f8a366136a07df661e31decce2458357c167a\"\n\texit 1\n}\n\nwifi_config() {\n\t[ ! -f /etc/config/wireless ] && touch /etc/config/wireless\n\n\tfor driver in $DRIVERS; do (\n\t\tif eval \"type detect_$driver\" 2>/dev/null >/dev/null; then\n\t\t\teval \"detect_$driver\" || echo \"$driver: Detect failed\" >&2\n\t\telse\n\t\t\techo \"$driver: Hardware detection not supported\" >&2\n\t\tfi\n\t); done\n}\n\nstart_net() {(\n\tlocal iface=\"$1\"\n\tlocal config=\"$2\"\n\tlocal vifmac=\"$3\"\n\n\t[ -f \"/var/run/$iface.pid\" ] && kill \"$(cat /var/run/${iface}.pid)\" 2>/dev/null\n\t[ -z \"$config\" ] || {\n\t\tinclude /lib/network\n\t\tscan_interfaces\n\t\tfor config in $config; do\n\t\t\tsetup_interface \"$iface\" \"$config\" \"\" \"$vifmac\"\n\t\tdone\n\t}\n)}\n\nset_wifi_up() {\n\tlocal cfg=\"$1\"\n\tlocal ifname=\"$2\"\n\tuci_set_state wireless \"$cfg\" up 1\n\tuci_set_state wireless \"$cfg\" ifname \"$ifname\"\n}\n\nset_wifi_down() {\n\tlocal cfg=\"$1\"\n\tlocal vifs vif vifstr\n\n\t[ -f \"/var/run/wifi-${cfg}.pid\" ] &&\n\t\tkill \"$(cat \"/var/run/wifi-${cfg}.pid\")\" 2>/dev/null\n\tuci_revert_state wireless \"$cfg\"\n\tconfig_get vifs \"$cfg\" vifs\n\tfor vif in $vifs; do\n\t\tuci_revert_state wireless \"$vif\"\n\tdone\n}\n\nscan_wifi() {\n\tlocal cfgfile=\"$1\"\n\tDEVICES=\n\tconfig_cb() {\n\t\tlocal type=\"$1\"\n\t\tlocal section=\"$2\"\n\n\t\t# section start\n\t\tcase \"$type\" in\n\t\t\twifi-device)\n\t\t\t\tappend DEVICES \"$section\"\n\t\t\t\tconfig_set \"$section\" vifs \"\"\n\t\t\t\tconfig_set \"$section\" ht_capab \"\"\n\t\t\t;;\n\t\tesac\n\n\t\t# section end\n\t\tconfig_get TYPE \"$CONFIG_SECTION\" TYPE\n\t\tcase \"$TYPE\" in\n\t\t\twifi-iface)\n\t\t\t\tconfig_get device \"$CONFIG_SECTION\" device\n\t\t\t\tconfig_get vifs \"$device\" vifs\n\t\t\t\tappend vifs \"$CONFIG_SECTION\"\n\t\t\t\tconfig_set \"$device\" vifs \"$vifs\"\n\t\t\t;;\n\t\tesac\n\t}\n\tconfig_load \"${cfgfile:-wireless}\"\n}\n\nDEVICES=\nDRIVERS=\ninclude /lib/wifi\nscan_wifi\n\ncase \"$1\" in\n\tdown) wifi_updown \"disable\" \"$2\";;\n\tdetect) wifi_detect_notice ;;\n\tconfig) wifi_config ;;\n\tstatus) ubus_wifi_cmd \"status\" \"$2\";;\n\treload) wifi_reload \"$2\";;\n\treload_legacy) wifi_reload_legacy \"$2\";;\n\t--help|help) usage;;\n\treconf) wifi_updown \"reconf\" \"$2\";;\n\t''|up) wifi_updown \"enable\" \"$2\";;\n\t*) usage; exit 1;;\nesac\n"
  },
  {
    "path": "package/base-files/files/usr/lib/os-release",
    "content": "NAME=\"%D\"\nVERSION=\"%V\"\nID=\"%d\"\nID_LIKE=\"lede openwrt\"\nPRETTY_NAME=\"%D %V\"\nVERSION_ID=\"%v\"\nHOME_URL=\"%u\"\nBUG_URL=\"%b\"\nSUPPORT_URL=\"%s\"\nBUILD_ID=\"%R\"\nOPENWRT_BOARD=\"%S\"\nOPENWRT_ARCH=\"%A\"\nOPENWRT_TAINTS=\"%t\"\nOPENWRT_DEVICE_MANUFACTURER=\"%M\"\nOPENWRT_DEVICE_MANUFACTURER_URL=\"%m\"\nOPENWRT_DEVICE_PRODUCT=\"%P\"\nOPENWRT_DEVICE_REVISION=\"%h\"\nOPENWRT_RELEASE=\"%D %V %C\"\n"
  },
  {
    "path": "package/base-files/files/usr/libexec/login.sh",
    "content": "#!/bin/sh\n\n[ \"$(uci -q get system.@system[0].ttylogin)\" = 1 ] || exec /bin/ash --login\n\nexec /bin/login\n"
  },
  {
    "path": "package/base-files/files/usr/libexec/validate_firmware_image",
    "content": "#!/bin/sh\n\n. /lib/functions.sh\n. /lib/functions/system.sh\n. /usr/share/libubox/jshn.sh\n\ninclude /lib/upgrade\n\nVALID=1\nFORCEABLE=1\nALLOW_BACKUP=1\n\n# Mark image as invalid but still possible to install\nnotify_firmware_invalid() {\n\tVALID=0\n}\n\n# Mark image as broken (impossible to install)\nnotify_firmware_broken() {\n\tVALID=0\n\tFORCEABLE=0\n}\n\n# Mark image as incompatible with preserving a backup\nnotify_firmware_no_backup() {\n\tALLOW_BACKUP=0\n}\n\n# Add result of validation test\nnotify_firmware_test_result() {\n\tlocal old_ns\n\n\tjson_set_namespace validate_firmware_image old_ns\n\tjson_add_boolean \"$1\" \"$2\"\n\tjson_set_namespace $old_ns\n}\n\nerr_to_bool() {\n\t[ \"$1\" -ne 0 ] && echo 0 || echo 1\n}\n\nfwtool_check_signature \"$1\" >&2\nFWTOOL_SIGNATURE=$?\n[ \"$FWTOOL_SIGNATURE\" -ne 0 ] && notify_firmware_invalid\n\nfwtool_check_image \"$1\" >&2\nFWTOOL_DEVICE_MATCH=$?\n[ \"$FWTOOL_DEVICE_MATCH\" -ne 0 ] && notify_firmware_invalid\n\njson_set_namespace validate_firmware_image old_ns\njson_init\n\tjson_add_object \"tests\"\n\t\tjson_add_boolean fwtool_signature \"$(err_to_bool $FWTOOL_SIGNATURE)\"\n\t\tjson_add_boolean fwtool_device_match \"$(err_to_bool $FWTOOL_DEVICE_MATCH)\"\n\n\t\t# Call platform_check_image() here so it can add its test\n\t\t# results and still mark image properly.\n\t\tjson_set_namespace $old_ns\n\t\tplatform_check_image \"$1\" >&2 || notify_firmware_invalid\n\t\tjson_set_namespace validate_firmware_image old_ns\n\tjson_close_object\n\tjson_add_boolean valid \"$VALID\"\n\tjson_add_boolean forceable \"$FORCEABLE\"\n\tjson_add_boolean allow_backup \"$ALLOW_BACKUP\"\njson_dump -i\njson_set_namespace $old_ns\n"
  },
  {
    "path": "package/base-files/image-config.in",
    "content": "# Copyright (C) 2006-2012 OpenWrt.org\n# Copyright (C) 2010 Vertical Communications\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\nmenuconfig PREINITOPT\n\tbool \"Preinit configuration options\" if IMAGEOPT\n\tdefault n\n\thelp\n\t\tThese options are used to control the environment used to initialize\n\t\tthe system before running init (which typically mean /sbin/init which\n\t\tswitches to multiuser mode).\n\nconfig TARGET_PREINIT_SUPPRESS_STDERR\n\tbool \"Suppress stderr messages during preinit\" if PREINITOPT\n\tdefault y\n\thelp\n\t\tSends stderr to null during preinit.  This is the default behaviour\n\t\tin previous versions of OpenWrt.  This also prevents init process\n\t\titself from displaying stderr, however processes launched by init\n\t\tin multiuser through inittab will use the current terminal (e.g.\n\t\tthe ash shell launched by inittab will display stderr).  That's\n\t\tthe same behaviour as seen in previous version of OpenWrt.\n\nconfig TARGET_PREINIT_DISABLE_FAILSAFE\n\tbool\n\tprompt \"Disable failsafe\" if PREINITOPT\n\tdefault n\n\thelp\n\t\tDisable failsafe mode.  While it is very handy while\n\t\texperimenting or developing it really ought to be\n\t\tdisabled in production environments as it is a major\n\t\tsecurity loophole.\n\nconfig TARGET_PREINIT_TIMEOUT\n\tint\n\tprompt \"Failsafe/Debug wait timeout\" if PREINITOPT\n\tdefault 2\n\thelp\n\t\tHow long to wait for failsafe mode to be entered or for\n\t\ta debug option to be pressed before continuing with a\n\t\tregular boot.\n\nconfig TARGET_PREINIT_SHOW_NETMSG\n\tbool\n\tprompt \"Show all preinit network messages\" if PREINITOPT\n\tdefault n\n\thelp\n\t\tShow preinit all network messages (via netmsg broadcast), not only\n\t\tthe message indicating to press reset to enter failsafe.  Note that\n\t\tif the architecture doesn't define an interface, and there is no\n\t\t'Preinit network interface' defined, then no messages will be\n\t\temitted, even if this is set.\n\nconfig TARGET_PREINIT_SUPPRESS_FAILSAFE_NETMSG\n\tbool\n\tprompt \"Suppress network message indicating failsafe\" if ( PREINITOPT && !TARGET_PREINIT_SHOW_NETMSG && !TARGET_PREINIT_DISABLE_FAILSAFE )\n\tdefault n\n\thelp\n\t\tIf \"Show all preinit network messages\" above is not set, then\n\t\tsetting this option suppresses the only message that would be\n\t\temitted otherwise, name the network message to enter failsafe\n\t\t(via netmsg).\n\nconfig TARGET_PREINIT_IFNAME\n\tstring\n\tprompt \"Preinit network interface\" if PREINITOPT\n\tdefault \"\"\n\thelp\n\t\tInterface for sending preinit messages to network, and any other\n\t\tdefault networking in failsafe or preinit.  If empty\n\t\tuses $ifname (if defined in /etc/preinit.arch).\n\nconfig TARGET_PREINIT_IP\n\tstring\n\tprompt \"IP address for preinit network messages\" if PREINITOPT\n\tdefault \"192.168.1.1\"\n\thelp\n\t\tIP address used to configure interface for preinit network\n\t\tmessages, including failsafe messages\n\nconfig TARGET_PREINIT_NETMASK\n\tstring\n\tprompt \"Netmask for preinit network messages\" if PREINITOPT\n\tdefault \"255.255.255.0\"\n\thelp\n\t\tNetmask used to configure interface for preinit network\n\t\tmessages, including failsafes messages\n\nconfig TARGET_PREINIT_BROADCAST\n\tstring\n\tprompt \"Broadcast address for preinit network messages\" if PREINITOPT\n\tdefault \"192.168.1.255\"\n\thelp\n\t\tBroadcast address to which to send preinit network messages, as\n\t\tas failsafe messages\n\n\nmenuconfig INITOPT\n\tbool \"Init configuration options\" if IMAGEOPT\n\tdefault n\n\thelp\n\t\tThese option choose the command that will run as the 'init' command\n\t\t(that is which is responsible for controlling the system once preinit\n\t\ttransfers control to it) as well as some options controlling its\n\t\tbehaviour.  Normally init is /sbin/init.\n\n\tconfig TARGET_INIT_PATH\n\t\tstring\n\t\tprompt \"PATH for regular boot\" if INITOPT\n\t\tdefault \"/usr/sbin:/usr/bin:/sbin:/bin\"\n\t\thelp\n\t\t\tDefault PATH used during normal operation\n\n\tconfig TARGET_INIT_ENV\n\t\tstring\n\t\tprompt \"Environment variables to set when starting init (start with none)\" if INITOPT\n\t\tdefault \"\"\n\t\thelp\n\t\t\tShould be a space separated list of variable assignments.  These\n\t\t\tvariables will be present in the environment.  Spaces may not be\n\t\t\tpresent (including through expansion) even in a quoted string\n\t\t\t(env doesn't understanding quoting).\n\n\tconfig TARGET_INIT_CMD\n\t\tstring\n\t\tprompt \"Init command\" if INITOPT\n\t\tdefault \"/sbin/init\"\n\t\thelp\n\t\t\tThe executable to run as the init process.  Is 'exec'd by\n\t\t\tpreinit (which is the init that the kernel launches on boot).\n\n\tconfig TARGET_INIT_SUPPRESS_STDERR\n\t\tbool\n\t\tprompt \"Suppress stderr messages of init\" if INITOPT\n\t\tdefault y\n\t\thelp\n\t\t\tPrevents showing stderr messages for init command if not already\n\t\t\tsuppressed during preinit.  This is the default behaviour in\n\t\t\tprevious versions of OpenWrt.  Removing this does nothing if\n\t\t\tstderr is suppressed during preinit (which is the default).\n\n\nmenuconfig VERSIONOPT\n\tbool \"Version configuration options\" if IMAGEOPT\n\tdefault n\n\thelp\n\t\tThese options allow to override the version information embedded in\n\t\tthe /etc/openwrt_version, /etc/openwrt_release, /etc/banner,\n\t\t/etc/opkg.conf, and /etc/os-release files. Usually there is no need\n\t\tto set these, but they're useful for release builds or custom OpenWrt\n\t\tredistributions that should carry custom version tags.\n\nif VERSIONOPT\n\n\tconfig VERSION_DIST\n\t\tstring\n\t\tprompt \"Release distribution\"\n\t\tdefault \"OpenWrt\"\n\t\thelp\n\t\t\tThis is the name of the release distribution.\n\t\t\tIf unspecified, it defaults to OpenWrt.\n\n\tconfig VERSION_NUMBER\n\t\tstring\n\t\tprompt \"Release version number\"\n\t\thelp\n\t\t\tThis is the release version number embedded in the image.\n\t\t\tIf unspecified, it defaults to SNAPSHOT for the master branch\n\t\t\tor to ##.##-SNAPSHOT on release branches.\n\n\tconfig VERSION_CODE\n\t\tstring\n\t\tprompt \"Release version code\"\n\t\thelp\n\t\t\tThis is the release version code embedded in the image.\n\t\t\tIf unspecified, it defaults to a revision number describing the\n\t\t\trepository version of the source, e.g. the number of commits\n\t\t\tsince a branch point or a short Git commit ID.\n\n\tconfig VERSION_REPO\n\t\tstring\n\t\tprompt \"Release repository\"\n\t\tdefault \"https://downloads.openwrt.org/snapshots\"\n\t\thelp\n\t\t\tThis is the repository address embedded in the image, it defaults\n\t\t\tto the trunk snapshot repo; the url may contain the following placeholders:\n\t\t\t %R .. Repository revision ID\n\t\t\t %V .. Configured release version number or \"SNAPSHOT\", uppercase\n\t\t\t %v .. Configured release version number or \"snapshot\", lowercase\n\t\t\t %C .. Configured release revision code or value of %R, uppercase\n\t\t\t %c .. Configured release revision code or value of %R, lowercase\n\t\t\t %D .. Distribution name or \"OpenWrt\", uppercase\n\t\t\t %d .. Distribution name or \"openwrt\", lowercase\n\t\t\t %T .. Target name\n\t\t\t %S .. Target/Subtarget name\n\t\t\t %A .. Package architecture\n\t\t\t %t .. Build taint flags, e.g. \"no-all busybox\"\n\t\t\t %M .. Manufacturer name or \"OpenWrt\"\n\t\t\t %P .. Product name or \"Generic\"\n\t\t\t %h .. Hardware revision or \"v0\"\n\n\tconfig VERSION_HOME_URL\n\t\tstring\n\t\tprompt \"Release Homepage\"\n\t\thelp\n\t\t\tThis is the release version homepage\n\n\tconfig VERSION_MANUFACTURER\n\t\tstring\n\t\tprompt \"Manufacturer name\"\n\t\thelp\n\t\t\tThis is the manufacturer name embedded in /etc/device_info\n\t\t\tUseful for OEMs building OpenWrt based firmware\n\n\tconfig VERSION_MANUFACTURER_URL\n\t\tstring\n\t\tprompt \"Manufacturer URL\"\n\t\thelp\n\t\t\tThis is an URL to the manufacturer's website embedded in /etc/device_info\n\t\t\tUseful for OEMs building OpenWrt based firmware\n\n\tconfig VERSION_BUG_URL\n\t\tstring\n\t\tprompt \"Bug reporting URL\"\n\t\thelp\n\t\t\tThis is an URL to provide users for providing bug reports\n\n\tconfig VERSION_SUPPORT_URL\n\t\tstring\n\t\tprompt \"Support URL\"\n\t\thelp\n\t\t\tThis an URL to provide users seeking support\n\n\tconfig VERSION_PRODUCT\n\t\tstring\n\t\tprompt \"Product name\"\n\t\thelp\n\t\t\tThis is the product name embedded in /etc/device_info\n\t\t\tUseful for OEMs building OpenWrt based firmware\n\n\tconfig VERSION_HWREV\n\t\tstring\n\t\tprompt \"Hardware revision\"\n\t\thelp\n\t\t\tThis is the hardware revision string embedded in /etc/device_info\n\t\t\tUseful for OEMs building OpenWrt based firmware\n\n\tconfig VERSION_FILENAMES\n\t\tbool\n\t\tprompt \"Version number in filenames\"\n\t\tdefault y\n\t\thelp\n\t\t\tEnable this to include the version number in firmware image, SDK-\n\t\t\tand Image Builder archive file names\n\n\tconfig VERSION_CODE_FILENAMES\n\t\tbool\n\t\tprompt \"Revision code in filenames\"\n\t\tdefault y\n\t\thelp\n\t\t\tEnable this to include the revision identifier or the configured\n\t\t\tversion code into the firmware image, SDK- and Image Builder archive\n\t\t\tfile names\nendif\n\n\nmenuconfig PER_FEED_REPO\n\tbool \"Separate feed repositories\" if IMAGEOPT\n\tdefault y\n\thelp\n\t\tIf set, a separate repository is generated within bin/*/packages/\n\t\tfor the core packages and each enabled feed.\n\nsource \"tmp/.config-feeds.in\"\n"
  },
  {
    "path": "package/boot/arm-trusted-firmware-bcm63xx/Makefile",
    "content": "# SPDX-License-Identifier: GPL-2.0\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_VERSION:=2.2\nPKG_RELEASE:=$(AUTORELEASE)\n\nPKG_SOURCE_PROTO:=git\nPKG_SOURCE_URL=$(PROJECT_GIT)/project/bcm63xx/atf.git\nPKG_SOURCE_DATE:=2021-12-24\nPKG_SOURCE_VERSION:=e6d46baf3fae79f693f90bf34f7284c3dfc64aef\nPKG_MIRROR_HASH:=9d5d04f572b1b6ddc6eb3064b9cb09f5fe982e82d350790041d35316349af124\n\nPKG_MAINTAINER:=Rafał Miłecki <rafal@milecki.pl>\n\ninclude $(INCLUDE_DIR)/trusted-firmware-a.mk\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine Trusted-Firmware-A/Default\n  PLAT:=bcm\n  DEFAULT:=y\nendef\n\ndefine Trusted-Firmware-A/bcm4908\n  BUILD_TARGET:=bcm4908\n  NAME:=BCM4908\n  BRCM_CHIP=4908\n  TFA_IMAGE:=bl31.bin\nendef\n\nTFA_TARGETS:= \\\n\tbcm4908\n\nTFA_MAKE_FLAGS += \\\n\tBRCM_CHIP=$(BRCM_CHIP)\n\ndefine Package/trusted-firmware-a/install\n\t$(INSTALL_DIR) $(STAGING_DIR_IMAGE)\n\t$(INSTALL_DATA) $(PKG_BUILD_DIR)/build/$(PLAT)/release/$(TFA_IMAGE) $(STAGING_DIR_IMAGE)/\nendef\n\n$(eval $(call BuildPackage/Trusted-Firmware-A))\n"
  },
  {
    "path": "package/boot/arm-trusted-firmware-mediatek/Makefile",
    "content": "#\n# Copyright (C) 2017 Hauke Mehrtens\n# Copyright (C) 2021 Daniel Golle\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=arm-trusted-firmware-mediatek\nPKG_RELEASE:=$(AUTORELEASE)\n\nPKG_SOURCE_PROTO:=git\nPKG_SOURCE_URL=https://github.com/mtk-openwrt/arm-trusted-firmware.git\nPKG_SOURCE_DATE:=2021-05-08\nPKG_SOURCE_VERSION:=d2c75b2139be003887af9cc5a94da5e9bdc59de7\nPKG_MIRROR_HASH:=4af9ce8e11511afee7f588cc982946c06339edbfa47afef6a7f3e2231ac9f34d\n\nPKG_MAINTAINER:=Daniel Golle <daniel@makrotopia.org>\n\ninclude $(INCLUDE_DIR)/trusted-firmware-a.mk\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine Trusted-Firmware-A/Default\n  BUILD_TARGET:=mediatek\n  BUILD_SUBTARGET:=mt7622\n  PLAT:=mt7622\n  TFA_IMAGE:=bl2.img bl31.bin\n  BOOT_DEVICE:=\n  DDR3_FLYBY:=\nendef\n\ndefine Trusted-Firmware-A/mt7622-nor-1ddr\n  NAME:=MediaTek MT7622 (SPI-NOR, 1x DDR3)\n  BOOT_DEVICE:=nor\nendef\n\ndefine Trusted-Firmware-A/mt7622-nor-2ddr\n  NAME:=MediaTek MT7622 (SPI-NOR, 2x DDR3)\n  BOOT_DEVICE:=nor\n  DDR3_FLYBY:=1\nendef\n\ndefine Trusted-Firmware-A/mt7622-snand-1ddr\n  NAME:=MediaTek MT7622 (SPI-NAND, 1x DDR3)\n  BOOT_DEVICE:=snand\nendef\n\ndefine Trusted-Firmware-A/mt7622-snand-2ddr\n  NAME:=MediaTek MT7622 (SPI-NAND, 2x DDR3)\n  BOOT_DEVICE:=snand\n  DDR3_FLYBY:=1\nendef\n\ndefine Trusted-Firmware-A/mt7622-emmc-1ddr\n  NAME:=MediaTek MT7622 (eMMC, 1x DDR3)\n  BOOT_DEVICE:=emmc\nendef\n\ndefine Trusted-Firmware-A/mt7622-emmc-2ddr\n  NAME:=MediaTek MT7622 (eMMC, 2x DDR3)\n  BOOT_DEVICE:=emmc\n  DDR3_FLYBY:=1\nendef\n\ndefine Trusted-Firmware-A/mt7622-sdmmc-1ddr\n  NAME:=MediaTek MT7622 (SDcard, 1x DDR3)\n  BOOT_DEVICE:=sdmmc\nendef\n\ndefine Trusted-Firmware-A/mt7622-sdmmc-2ddr\n  NAME:=MediaTek MT7622 (SDcard, 2x DDR3)\n  BOOT_DEVICE:=sdmmc\n  DDR3_FLYBY:=1\nendef\n\nTFA_TARGETS:= \\\n\tmt7622-nor-1ddr \\\n\tmt7622-nor-2ddr \\\n\tmt7622-snand-1ddr \\\n\tmt7622-snand-2ddr \\\n\tmt7622-emmc-1ddr \\\n\tmt7622-emmc-2ddr \\\n\tmt7622-sdmmc-1ddr \\\n\tmt7622-sdmmc-2ddr\n\nTFA_MAKE_FLAGS += \\\n\tBOOT_DEVICE=$(BOOT_DEVICE) \\\n\tUSE_MKIMAGE=1 MKIMAGE=$(STAGING_DIR_HOST)/bin/mkimage \\\n\t$(if $(DDR3_FLYBY),DDR3_FLYBY=1) \\\n\tall\n\ndefine Package/trusted-firmware-a/install\n\t$(INSTALL_DIR) $(STAGING_DIR_IMAGE)\n\t$(INSTALL_DATA) $(PKG_BUILD_DIR)/build/mt7622/release/bl2.img $(STAGING_DIR_IMAGE)/$(BUILD_VARIANT)-bl2.img\n\t$(INSTALL_DATA) $(PKG_BUILD_DIR)/build/mt7622/release/bl31.bin $(STAGING_DIR_IMAGE)/$(BUILD_VARIANT)-bl31.bin\nendef\n\n$(eval $(call BuildPackage/Trusted-Firmware-A))\n"
  },
  {
    "path": "package/boot/arm-trusted-firmware-mediatek/patches/100-increase-nor-bl3-size.patch",
    "content": "--- a/plat/mediatek/mt7622/bl2_boot_nor.c\n+++ b/plat/mediatek/mt7622/bl2_boot_nor.c\n@@ -12,7 +12,7 @@\n #define MT7622_NOR_MAP_BASE\t\t0x30000000\n \n #define FIP_BASE\t\t\t0x20000\n-#define FIP_SIZE\t\t\t0x80000\n+#define FIP_SIZE\t\t\t0xa0000\n \n const io_block_spec_t mtk_boot_dev_fip_spec = {\n \t.offset\t= MT7622_NOR_MAP_BASE + FIP_BASE,\n"
  },
  {
    "path": "package/boot/arm-trusted-firmware-mvebu/Makefile",
    "content": "#\n# Copyright (C) 2019 Sartura Ltd.\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_VERSION:=2.5\nPKG_RELEASE:=$(AUTORELEASE)\nPKG_HASH:=ad8a2ffcbcd12d919723da07630fc0840c3c2fba7656d1462e45488e42995d7c\n\nPKG_MAINTAINER:=Vladimir Vid <vladimir.vid@sartura.hr>\n\ninclude $(INCLUDE_DIR)/trusted-firmware-a.mk\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine Trusted-Firmware-A/Default\n  BUILD_TARGET:=mvebu\n  BUILD_SUBTARGET:=cortexa53\n  TFA_IMAGE:=flash-image.bin uart-images.tgz.bin\n  UBOOT:=\n  DDR_TOPOLOGY:=\n  CLOCKSPRESET:=\nendef\n\n\ndefine Trusted-Firmware-A/espressobin-512mb\n  NAME:=Marvell ESPRESSObin (512MB)\n  DEPENDS:=+u-boot-espressobin\n  BUILD_DEVICES:=globalscale_espressobin\n  UBOOT:=espressobin\n  DDR_TOPOLOGY:=0\n  CLOCKSPRESET:=CPU_1000_DDR_800\n  PLAT:=a3700\nendef\n\ndefine Trusted-Firmware-A/espressobin-v3-v5-1gb-1cs\n  NAME:=Marvell ESPRESSObin V3-V5 (1GB 1CS)\n  DEPENDS:=+u-boot-espressobin\n  BUILD_DEVICES:=globalscale_espressobin\n  UBOOT:=espressobin\n  DDR_TOPOLOGY:=4\n  CLOCKSPRESET:=CPU_1000_DDR_800\n  PLAT:=a3700\nendef\n\ndefine Trusted-Firmware-A/espressobin-v3-v5-1gb-2cs\n  NAME:=Marvell ESPRESSObin V3-V5 (1GB, 2CS)\n  DEPENDS:=+u-boot-espressobin\n  BUILD_DEVICES:=globalscale_espressobin\n  UBOOT:=espressobin\n  DDR_TOPOLOGY:=2\n  CLOCKSPRESET:=CPU_1000_DDR_800\n  PLAT:=a3700\nendef\n\ndefine Trusted-Firmware-A/espressobin-v3-v5-2gb\n  NAME:=Marvell ESPRESSObin V3-V5 (2GB)\n  DEPENDS:=+u-boot-espressobin\n  BUILD_DEVICES:=globalscale_espressobin\n  UBOOT:=espressobin\n  DDR_TOPOLOGY:=7\n  CLOCKSPRESET:=CPU_1000_DDR_800\n  PLAT:=a3700\nendef\n\ndefine Trusted-Firmware-A/espressobin-v7-1gb\n  NAME:=Marvell ESPRESSObin V7 (1GB)\n  DEPENDS:=+u-boot-espressobin\n  BUILD_DEVICES:=globalscale_espressobin-v7\n  UBOOT:=espressobin\n  DDR_TOPOLOGY:=5\n  CLOCKSPRESET:=CPU_1000_DDR_800\n  PLAT:=a3700\nendef\n\ndefine Trusted-Firmware-A/espressobin-v7-2gb\n  NAME:=Marvell ESPRESSObin V7 (2GB)\n  DEPENDS:=+u-boot-espressobin\n  BUILD_DEVICES:=globalscale_espressobin-v7\n  UBOOT:=espressobin\n  DDR_TOPOLOGY:=6\n  CLOCKSPRESET:=CPU_1000_DDR_800\n  PLAT:=a3700\nendef\n\ndefine Trusted-Firmware-A/udpu\n  NAME:=Methode uDPU\n  DEPENDS:=+u-boot-uDPU\n  BUILD_DEVICES:=methode_udpu\n  UBOOT:=uDPU\n  DDR_TOPOLOGY:=0\n  CLOCKSPRESET:=CPU_1000_DDR_800\n  PLAT:=a3700\nendef\n\n\nTFA_TARGETS:= \\\n\tespressobin-512mb \\\n\tespressobin-v3-v5-1gb-1cs \\\n\tespressobin-v3-v5-1gb-2cs \\\n\tespressobin-v3-v5-2gb \\\n\tespressobin-v7-1gb \\\n\tespressobin-v7-2gb \\\n\tudpu\n\nTFA_MAKE_FLAGS += \\\n\t\tCROSS_CM3=$(STAGING_DIR_IMAGE)/$(CM3_GCC_NAME)-$(CM3_GCC_RELEASE)-$(CM3_GCC_VERSION)/bin/arm-none-eabi- \\\n\t\tBL33=$(STAGING_DIR_IMAGE)/$(UBOOT)-u-boot.bin \\\n\t\tMV_DDR_PATH=$(STAGING_DIR_IMAGE)/$(MV_DDR_NAME) \\\n\t\tWTP=$(STAGING_DIR_IMAGE)/$(A3700_UTILS_NAME) \\\n\t\tWTMI_IMG=$(STAGING_DIR_IMAGE)/$(MOX_BB_NAME)-$(MOX_BB_RELEASE)/wtmi_app.bin \\\n\t\tCRYPTOPP_PATH=$(STAGING_DIR_IMAGE)/$(CRYPTOPP_NAME) \\\n\t\tUSE_COHERENT_MEM=0 \\\n\t\tFIP_ALIGN=0x100 \\\n\t\tDDR_TOPOLOGY=$(DDR_TOPOLOGY) \\\n\t\tCLOCKSPRESET=$(CLOCKSPRESET) \\\n\t\tA3700_UTILS_COMMIT_ID=$(A3700_UTILS_RELEASE) \\\n\t\tMV_DDR_COMMIT_ID=$(MV_DDR_RELEASE) \\\n\t\tall \\\n\t\tmrvl_flash \\\n\t\tmrvl_uart\n\nA3700_UTILS_NAME:=a3700-utils\nA3700_UTILS_RELEASE:=97f01f5f\nA3700_UTILS_SOURCE=$(A3700_UTILS_NAME)-$(A3700_UTILS_RELEASE).tar.bz2\n\ndefine Download/a3700-utils\n  FILE:=$(A3700_UTILS_SOURCE)\n  PROTO:=git\n  URL:=https://github.com/MarvellEmbeddedProcessors/A3700-utils-marvell.git\n  VERSION:=97f01f5feaf9ef6168e2a2096abaf56371939e58\n  MIRROR_HASH:=1e391c4dafb7b3363a17282e229d056a95575c0f4fb2f71e21db8044668aea78\n  SUBDIR:=$(A3700_UTILS_NAME)\nendef\n\nCRYPTOPP_NAME:=cryptopp\nCRYPTOPP_RELEASE:=f210224\nCRYPTOPP_SOURCE=$(CRYPTOPP_NAME)-$(CRYPTOPP_RELEASE).tar.bz2\n\ndefine Download/cryptopp\n  FILE:=$(CRYPTOPP_SOURCE)\n  PROTO:=git\n  URL:=https://github.com/weidai11/cryptopp.git\n  VERSION:=f2102243e6fdd48c0b2a393a0993cca228f20573\n  MIRROR_HASH:=74ec9e48ee04b9f2d9a1d8c4f2392ed0ab52780d7af0f70405d7bbb23d1504fa\n  SUBDIR:=$(CRYPTOPP_NAME)\nendef\n\nMV_DDR_NAME:=mv-ddr-marvell\nMV_DDR_RELEASE:=efcad0e2\nMV_DDR_SOURCE:=$(MV_DDR_NAME)-$(MV_DDR_RELEASE).tar.bz2\n\ndefine Download/mv-ddr-marvell\n  FILE:=$(MV_DDR_SOURCE)\n  PROTO:=git\n  URL:=https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git\n  VERSION:=efcad0e2fae66a8b6f84a4dd2326f5add67569d5\n  MIRROR_HASH:=99363f928ee1239fd42d651b495d163a60cdab00c24770a3c5e192efa7169d62\n  SUBDIR:=$(MV_DDR_NAME)\nendef\n\nMOX_BB_NAME:=mox-boot-builder\nMOX_BB_RELEASE:=v2021.09.07\nMOX_BB_SOURCE:=$(MOX_BB_NAME)-$(MOX_BB_RELEASE).tar.bz2\n\ndefine Download/mox-boot-builder\n  FILE:=$(MOX_BB_SOURCE)\n  URL:=https://gitlab.nic.cz/turris/mox-boot-builder/-/archive/$(MOX_BB_RELEASE)\n  HASH:=fd5fe276a3b0dee3177d61c017907a8eb23cd2169478fa78e9a3a836cfe3a4a8\nendef\n\nCM3_GCC_NAME:=gcc-arm\nCM3_GCC_RELEASE:=10.2-2020.11\nCM3_GCC_VERSION:=$(HOST_ARCH)-arm-none-eabi\nCM3_GCC_SOURCE=$(CM3_GCC_NAME)-$(CM3_GCC_RELEASE)-$(CM3_GCC_VERSION).tar.xz\n\ndefine Download/cm3-gcc\n  FILE:=$(CM3_GCC_SOURCE)\n  URL:=https://developer.arm.com/-/media/Files/downloads/gnu-a/$(CM3_GCC_RELEASE)/binrel\nifeq ($(HOST_ARCH),aarch64)\n  HASH:=1a42eecafa03dc6f32b8ae49ffcd15114dc818efbd72292fa6bab58233940bb9\nelse\n  HASH:=bf7ee185936d22d787b80c8da573f72ead5675695331fb8b590f0133ef1f6bb9\nendif\nendef\n\ndefine Build/Clean\n\trm -rf \\\n\t\t$(STAGING_DIR_IMAGE)/$(CRYPTOPP_NAME) \\\n\t\t$(STAGING_DIR_IMAGE)/$(A3700_UTILS_NAME) \\\n\t\t$(STAGING_DIR_IMAGE)/$(MV_DDR_NAME) \\\n\t\t$(STAGING_DIR_IMAGE)/$(MOX_BB_NAME)-$(MOX_BB_RELEASE) \\\n\t\t$(STAGING_DIR_IMAGE)/$(CM3_GCC_NAME)-$(CM3_GCC_RELEASE)-$(CM3_GCC_VERSION)\nendef\n\ndefine Build/Prepare\n\t# Download sources\n\t$(eval $(call Download,a3700-utils))\n\t$(eval $(call Download,mv-ddr-marvell))\n\t$(eval $(call Download,mox-boot-builder))\n\t$(eval $(call Download,cryptopp))\n\t$(eval $(call Download,cm3-gcc))\n\n\t$(call Build/Prepare/Default,)\n\n\tmkdir -p $(STAGING_DIR_IMAGE)\n\t$(TAR) -C $(STAGING_DIR_IMAGE) -xf $(DL_DIR)/$(CRYPTOPP_SOURCE)\n\t$(TAR) -C $(STAGING_DIR_IMAGE) -xf $(DL_DIR)/$(A3700_UTILS_SOURCE)\n\techo \"master\" > $(STAGING_DIR_IMAGE)/$(A3700_UTILS_NAME)/branch.txt\n\t$(call PatchDir/Default,$(STAGING_DIR_IMAGE)/$(A3700_UTILS_NAME),./patches-a3700-utils)\n\t$(TAR) -C $(STAGING_DIR_IMAGE) -xf $(DL_DIR)/$(MV_DDR_SOURCE)\n\techo \"master\" > $(STAGING_DIR_IMAGE)/$(MV_DDR_NAME)/branch.txt\n\t$(call PatchDir/Default,$(STAGING_DIR_IMAGE)/$(MV_DDR_NAME),./patches-mv-ddr-marvell)\n\t$(TAR) -C $(STAGING_DIR_IMAGE) -xf $(DL_DIR)/$(MOX_BB_SOURCE)\n\t$(call PatchDir/Default,$(STAGING_DIR_IMAGE)/$(MOX_BB_NAME)-$(MOX_BB_RELEASE),./patches-mox-boot-builder)\n\t$(TAR) -C $(STAGING_DIR_IMAGE) -xf $(DL_DIR)/$(CM3_GCC_SOURCE)\nendef\n\ndefine Build/Compile\n\t+$(MAKE) \\\n\t\tCROSS_CM3=$(STAGING_DIR_IMAGE)/$(CM3_GCC_NAME)-$(CM3_GCC_RELEASE)-$(CM3_GCC_VERSION)/bin/arm-none-eabi- \\\n\t\tWTMI_VERSION=$(MOX_BB_RELEASE) \\\n\t\tCRYPTOPP_PATH=$PWD/cryptopp/ \\\n\t\t-C $(STAGING_DIR_IMAGE)/$(MOX_BB_NAME)-$(MOX_BB_RELEASE) \\\n\t\twtmi_app.bin\n\t$(call Build/Compile/Default)\nendef\n\n$(eval $(call BuildPackage/Trusted-Firmware-A))\n"
  },
  {
    "path": "package/boot/arm-trusted-firmware-mvebu/patches/100-fix-plat-marvell-a3720-uart-fix-UART-clock-rate-valu.patch",
    "content": "From 66a7752834382595d26214783ae4698fd1f00bd6 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>\nDate: Thu, 13 May 2021 14:53:44 +0200\nSubject: [PATCH] fix(plat/marvell/a3720/uart): fix UART clock rate value and\n divisor calculation\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nUART parent clock is by default the platform's xtal clock, which is\n25 MHz.\n\nThe value defined in the driver, though, is 25.8048 MHz. This is a hack\nfor the suboptimal divisor calculation\n  Divisor = UART clock / (16 * baudrate)\nwhich does not use rounding division, resulting in a suboptimal value\nfor divisor if the correct parent clock rate was used.\n\nChange the code for divisor calculation to\n  Divisor = Round(UART clock / (16 * baudrate))\nand change the parent clock rate value to 25 MHz.\n\nThe final UART divisor for default baudrate 115200 is not affected by\nthis change.\n\n(Note that the parent clock rate should not be defined via a macro,\nsince the xtal clock can also be 40 MHz. This is outside of the scope of\nthis fix, though.)\n\nSigned-off-by: Pali Rohár <pali@kernel.org>\nChange-Id: Iaa401173df87aec94f2dd1b38a90fb6ed0bf0ec6\n---\n drivers/marvell/uart/a3700_console.S                  | 3 ++-\n plat/marvell/armada/a3k/common/include/platform_def.h | 2 +-\n 2 files changed, 3 insertions(+), 2 deletions(-)\n\n--- a/drivers/marvell/uart/a3700_console.S\n+++ b/drivers/marvell/uart/a3700_console.S\n@@ -45,8 +45,9 @@ func console_a3700_core_init\n \tcbz\tw2, init_fail\n \n \t/* Program the baudrate */\n-\t/* Divisor =  Uart clock / (16 * baudrate) */\n+\t/* Divisor = Round(Uartclock / (16 * baudrate)) */\n \tlsl\tw2, w2, #4\n+\tadd\tw1, w1, w2, lsr #1\n \tudiv\tw2, w1, w2\n \tand\tw2, w2, #0x3ff\n \n--- a/plat/marvell/armada/a3k/common/include/platform_def.h\n+++ b/plat/marvell/armada/a3k/common/include/platform_def.h\n@@ -164,7 +164,7 @@\n  * PL011 related constants\n  */\n #define PLAT_MARVELL_BOOT_UART_BASE\t\t(MVEBU_REGS_BASE + 0x12000)\n-#define PLAT_MARVELL_BOOT_UART_CLK_IN_HZ\t25804800\n+#define PLAT_MARVELL_BOOT_UART_CLK_IN_HZ\t25000000\n \n #define PLAT_MARVELL_CRASH_UART_BASE\t\tPLAT_MARVELL_BOOT_UART_BASE\n #define PLAT_MARVELL_CRASH_UART_CLK_IN_HZ\tPLAT_MARVELL_BOOT_UART_CLK_IN_HZ\n"
  },
  {
    "path": "package/boot/arm-trusted-firmware-mvebu/patches/101-fix-plat-marvell-a3720-uart-fix-configuring-UART-clo.patch",
    "content": "From b9185c75f7ec2b600ebe0d49281e216a2456b764 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>\nDate: Thu, 13 May 2021 15:11:06 +0200\nSubject: [PATCH] fix(plat/marvell/a3720/uart): fix configuring UART clock\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nWhen configuring the UART_BAUD_REG register, the function\nconsole_a3700_core_init() currently only changes the baud divisor field,\nleaving other fields to their previous value.\n\nThis is incorrect, because the baud divisor is computed with the\nassumption that the parent clock rate is 25 MHz, and since the other\nfields in this register configure the parent clock, which could have\nbeen changed by U-Boot or Linux.\n\nFix this function to also configure the other fields so that the UART\nparent clock is selected to be the xtal clock.\n\nFor example without this change TF-A prints only\n\n    ERROR: a3700_system_off needs to be implemented\n\nfollowed by garbage after plat_crash_console_init() is called.\n\nAfter applying this change instead of garbage it also print crash info:\n\n    PANIC at PC : 0x0000000004023800\n\nSigned-off-by: Pali Rohár <pali@kernel.org>\nChange-Id: I72f338355cc60d939b8bb978d9c7fdd576416b81\n---\n drivers/marvell/uart/a3700_console.S | 7 ++-----\n 1 file changed, 2 insertions(+), 5 deletions(-)\n\n--- a/drivers/marvell/uart/a3700_console.S\n+++ b/drivers/marvell/uart/a3700_console.S\n@@ -49,12 +49,9 @@ func console_a3700_core_init\n \tlsl\tw2, w2, #4\n \tadd\tw1, w1, w2, lsr #1\n \tudiv\tw2, w1, w2\n-\tand\tw2, w2, #0x3ff\n+\tand\tw2, w2, #0x3ff /* clear all other bits to use default clock */\n \n-\tldr\tw3, [x0, #UART_BAUD_REG]\n-\tbic\tw3, w3, 0x3ff\n-\torr\tw3, w3, w2\n-\tstr\tw3, [x0, #UART_BAUD_REG]/* set baud rate divisor */\n+\tstr\tw2, [x0, #UART_BAUD_REG]/* set baud rate divisor */\n \n \t/* Set UART to default 16X scheme */\n \tmov\tw3, #0\n"
  },
  {
    "path": "package/boot/arm-trusted-firmware-mvebu/patches/102-refactor-plat-marvell-uart-de-duplicate-PLAT_MARVELL.patch",
    "content": "From 3133625859b74df42deddd80b705578af6fc2fea Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>\nDate: Fri, 14 May 2021 13:21:56 +0200\nSubject: [PATCH] refactor(plat/marvell/uart): de-duplicate PLAT_MARVELL_UART\n macros\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nMacros PLAT_MARVELL_BOOT_UART* and PLAT_MARVELL_CRASH_UART* are defined\nto same values. De-duplicate them into PLAT_MARVELL_UART* macros.\n\nSigned-off-by: Pali Rohár <pali@kernel.org>\nChange-Id: Iae5daf7cad6a971e6f3dbe561df3d0174106ca7f\n---\n plat/marvell/armada/a3k/common/include/platform_def.h     | 7 ++-----\n plat/marvell/armada/a8k/a80x0_puzzle/board/system_power.c | 4 ++--\n plat/marvell/armada/a8k/common/include/platform_def.h     | 7 ++-----\n plat/marvell/armada/common/aarch64/marvell_helpers.S      | 8 ++++----\n plat/marvell/armada/common/marvell_console.c              | 8 ++++----\n 5 files changed, 14 insertions(+), 20 deletions(-)\n\n--- a/plat/marvell/armada/a3k/common/include/platform_def.h\n+++ b/plat/marvell/armada/a3k/common/include/platform_def.h\n@@ -163,11 +163,8 @@\n /*\n  * PL011 related constants\n  */\n-#define PLAT_MARVELL_BOOT_UART_BASE\t\t(MVEBU_REGS_BASE + 0x12000)\n-#define PLAT_MARVELL_BOOT_UART_CLK_IN_HZ\t25000000\n-\n-#define PLAT_MARVELL_CRASH_UART_BASE\t\tPLAT_MARVELL_BOOT_UART_BASE\n-#define PLAT_MARVELL_CRASH_UART_CLK_IN_HZ\tPLAT_MARVELL_BOOT_UART_CLK_IN_HZ\n+#define PLAT_MARVELL_UART_BASE\t\t\t(MVEBU_REGS_BASE + 0x12000)\n+#define PLAT_MARVELL_UART_CLK_IN_HZ\t\t25000000\n \n #define PLAT_MARVELL_BL31_RUN_UART_BASE\t\tPLAT_MARVELL_BOOT_UART_BASE\n #define PLAT_MARVELL_BL31_RUN_UART_CLK_IN_HZ\tPLAT_MARVELL_BOOT_UART_CLK_IN_HZ\n--- a/plat/marvell/armada/a8k/a80x0_puzzle/board/system_power.c\n+++ b/plat/marvell/armada/a8k/a80x0_puzzle/board/system_power.c\n@@ -41,8 +41,8 @@ int system_power_off(void)\n \tlen = sizeof(system_off_now);\n \tsystem_off_now[len - 1] = add_xor_checksum(system_off_now, len);\n \n-\tconsole_16550_register(PLAT_MARVELL_BOOT_UART_BASE + 0x100,\n-\t\tPLAT_MARVELL_BOOT_UART_CLK_IN_HZ, 115200, &console);\n+\tconsole_16550_register(PLAT_MARVELL_UART_BASE + 0x100,\n+\t\tPLAT_MARVELL_UART_CLK_IN_HZ, 115200, &console);\n \n \t/* Send system_off_now to console */\n \tfor (i = 0; i < len; i++) {\n--- a/plat/marvell/armada/a8k/common/include/platform_def.h\n+++ b/plat/marvell/armada/a8k/common/include/platform_def.h\n@@ -168,11 +168,8 @@\n /*\n  * PL011 related constants\n  */\n-#define PLAT_MARVELL_BOOT_UART_BASE\t\t(MVEBU_REGS_BASE + 0x512000)\n-#define PLAT_MARVELL_BOOT_UART_CLK_IN_HZ\t200000000\n-\n-#define PLAT_MARVELL_CRASH_UART_BASE\t\tPLAT_MARVELL_BOOT_UART_BASE\n-#define PLAT_MARVELL_CRASH_UART_CLK_IN_HZ\tPLAT_MARVELL_BOOT_UART_CLK_IN_HZ\n+#define PLAT_MARVELL_UART_BASE\t\t\t(MVEBU_REGS_BASE + 0x512000)\n+#define PLAT_MARVELL_UART_CLK_IN_HZ\t\t200000000\n \n #define PLAT_MARVELL_BL31_RUN_UART_BASE\t\tPLAT_MARVELL_BOOT_UART_BASE\n #define PLAT_MARVELL_BL31_RUN_UART_CLK_IN_HZ\tPLAT_MARVELL_BOOT_UART_CLK_IN_HZ\n--- a/plat/marvell/armada/common/aarch64/marvell_helpers.S\n+++ b/plat/marvell/armada/common/aarch64/marvell_helpers.S\n@@ -63,8 +63,8 @@ endfunc plat_marvell_calc_core_pos\n \t * ---------------------------------------------\n \t */\n func plat_crash_console_init\n-\tmov_imm\tx0, PLAT_MARVELL_CRASH_UART_BASE\n-\tmov_imm\tx1, PLAT_MARVELL_CRASH_UART_CLK_IN_HZ\n+\tmov_imm\tx0, PLAT_MARVELL_UART_BASE\n+\tmov_imm\tx1, PLAT_MARVELL_UART_CLK_IN_HZ\n \tmov_imm\tx2, MARVELL_CONSOLE_BAUDRATE\n #ifdef PLAT_a3700\n \tb\tconsole_a3700_core_init\n@@ -81,7 +81,7 @@ endfunc plat_crash_console_init\n \t * ---------------------------------------------\n \t */\n func plat_crash_console_putc\n-\tmov_imm\tx1, PLAT_MARVELL_CRASH_UART_BASE\n+\tmov_imm\tx1, PLAT_MARVELL_UART_BASE\n #ifdef PLAT_a3700\n \n \tb\tconsole_a3700_core_putc\n@@ -99,7 +99,7 @@ endfunc plat_crash_console_putc\n \t * ---------------------------------------------\n \t */\n func plat_crash_console_flush\n-\tmov_imm\tx0, PLAT_MARVELL_CRASH_UART_BASE\n+\tmov_imm\tx0, PLAT_MARVELL_UART_BASE\n #ifdef PLAT_a3700\n \tb\tconsole_a3700_core_flush\n #else\n--- a/plat/marvell/armada/common/marvell_console.c\n+++ b/plat/marvell/armada/common/marvell_console.c\n@@ -31,8 +31,8 @@ static console_t marvell_runtime_console\n void marvell_console_boot_init(void)\n {\n \tint rc =\n-\tconsole_marvell_register(PLAT_MARVELL_BOOT_UART_BASE,\n-\t\t\t\t PLAT_MARVELL_BOOT_UART_CLK_IN_HZ,\n+\tconsole_marvell_register(PLAT_MARVELL_UART_BASE,\n+\t\t\t\t PLAT_MARVELL_UART_CLK_IN_HZ,\n \t\t\t\t MARVELL_CONSOLE_BAUDRATE,\n \t\t\t\t &marvell_boot_console);\n \tif (rc == 0) {\n@@ -58,8 +58,8 @@ void marvell_console_boot_end(void)\n void marvell_console_runtime_init(void)\n {\n \tint rc =\n-\tconsole_marvell_register(PLAT_MARVELL_BOOT_UART_BASE,\n-\t\t\t\t PLAT_MARVELL_BOOT_UART_CLK_IN_HZ,\n+\tconsole_marvell_register(PLAT_MARVELL_UART_BASE,\n+\t\t\t\t PLAT_MARVELL_UART_CLK_IN_HZ,\n \t\t\t\t MARVELL_CONSOLE_BAUDRATE,\n \t\t\t\t &marvell_runtime_console);\n \tif (rc == 0)\n"
  },
  {
    "path": "package/boot/arm-trusted-firmware-mvebu/patches/103-fix-plat-marvell-a3720-uart-fix-UART-parent-clock-ra.patch",
    "content": "From 5a91c439cbeb1f64b8b9830de91efad5113d3c89 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>\nDate: Fri, 14 May 2021 15:52:11 +0200\nSubject: [PATCH] fix(plat/marvell/a3720/uart): fix UART parent clock rate\n determination\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nThe UART code for the A3K platform assumes that UART parent clock rate\nis always 25 MHz. This is incorrect, because the xtal clock can also run\nat 40 MHz (this is board specific).\n\nThe frequency of the xtal clock is determined by a value on a strapping\npin during SOC reset. The code to determine this frequency is already in\nA3K's comphy driver.\n\nMove the get_ref_clk() function from the comphy driver to a separate\nfile and use it for UART parent clock rate determination.\n\nSigned-off-by: Pali Rohár <pali@kernel.org>\nChange-Id: I8bb18a2d020ef18fe65aa06ffa4ab205c71be92e\n---\n drivers/marvell/comphy/phy-comphy-3700.c      | 24 +------------\n .../marvell/armada/a3k/common/plat_marvell.h  |  2 ++\n .../marvell/armada/a3k/common/a3700_common.mk |  1 +\n .../armada/a3k/common/aarch64/a3700_clock.S   | 35 +++++++++++++++++++\n .../armada/a3k/common/include/platform_def.h  |  1 -\n .../armada/common/aarch64/marvell_helpers.S   | 10 +++++-\n plat/marvell/armada/common/marvell_console.c  |  1 +\n 7 files changed, 49 insertions(+), 25 deletions(-)\n create mode 100644 plat/marvell/armada/a3k/common/aarch64/a3700_clock.S\n\n--- a/drivers/marvell/comphy/phy-comphy-3700.c\n+++ b/drivers/marvell/comphy/phy-comphy-3700.c\n@@ -14,6 +14,7 @@\n \n #include <mvebu.h>\n #include <mvebu_def.h>\n+#include <plat_marvell.h>\n \n #include \"phy-comphy-3700.h\"\n #include \"phy-comphy-common.h\"\n@@ -29,15 +30,6 @@\n #define USB3_GBE1_PHY\t\t(MVEBU_REGS_BASE + 0x5C000)\n #define COMPHY_SD_ADDR\t\t(MVEBU_REGS_BASE + 0x1F000)\n \n-/*\n- * Below address in used only for reading, therefore no problem with concurrent\n- * Linux access.\n- */\n-#define MVEBU_TEST_PIN_LATCH_N (MVEBU_NB_GPIO_REG_BASE + 0x8)\n- #define MVEBU_XTAL_MODE_MASK\t\tBIT(9)\n- #define MVEBU_XTAL_MODE_OFFS\t\t9\n- #define MVEBU_XTAL_CLOCK_25MHZ\t\t0x0\n-\n struct sgmii_phy_init_data_fix {\n \tuint16_t addr;\n \tuint16_t value;\n@@ -125,20 +117,6 @@ static uint16_t sgmii_phy_init[512] = {\n \t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000\t/*1F8 */\n };\n \n-/* returns reference clock in MHz (25 or 40) */\n-static uint32_t get_ref_clk(void)\n-{\n-\tuint32_t val;\n-\n-\tval = (mmio_read_32(MVEBU_TEST_PIN_LATCH_N) & MVEBU_XTAL_MODE_MASK) >>\n-\t\tMVEBU_XTAL_MODE_OFFS;\n-\n-\tif (val == MVEBU_XTAL_CLOCK_25MHZ)\n-\t\treturn 25;\n-\telse\n-\t\treturn 40;\n-}\n-\n /* PHY selector configures with corresponding modes */\n static void mvebu_a3700_comphy_set_phy_selector(uint8_t comphy_index,\n \t\t\t\t\t\tuint32_t comphy_mode)\n--- a/include/plat/marvell/armada/a3k/common/plat_marvell.h\n+++ b/include/plat/marvell/armada/a3k/common/plat_marvell.h\n@@ -100,4 +100,6 @@ void plat_marvell_interconnect_enter_coh\n \n const mmap_region_t *plat_marvell_get_mmap(void);\n \n+uint32_t get_ref_clk(void);\n+\n #endif /* PLAT_MARVELL_H */\n--- a/plat/marvell/armada/a3k/common/a3700_common.mk\n+++ b/plat/marvell/armada/a3k/common/a3700_common.mk\n@@ -38,6 +38,7 @@ PLAT_INCLUDES\t\t:=\t-I$(PLAT_FAMILY_BASE)/\n \t\t\t\t-I$/drivers/arm/gic/common/\n \n PLAT_BL_COMMON_SOURCES\t:=\t$(PLAT_COMMON_BASE)/aarch64/a3700_common.c \\\n+\t\t\t\t$(PLAT_COMMON_BASE)/aarch64/a3700_clock.S \\\n \t\t\t\t$(MARVELL_DRV_BASE)/uart/a3700_console.S\n \n BL1_SOURCES\t\t+=\t$(PLAT_COMMON_BASE)/aarch64/plat_helpers.S \\\n--- /dev/null\n+++ b/plat/marvell/armada/a3k/common/aarch64/a3700_clock.S\n@@ -0,0 +1,35 @@\n+/*\n+ * Copyright (C) 2018 Marvell International Ltd.\n+ *\n+ * SPDX-License-Identifier:\tBSD-3-Clause\n+ * https://spdx.org/licenses\n+ */\n+\n+#include <asm_macros.S>\n+#include <platform_def.h>\n+\n+/*\n+ * Below address in used only for reading, therefore no problem with concurrent\n+ * Linux access.\n+ */\n+#define MVEBU_TEST_PIN_LATCH_N (MVEBU_NB_GPIO_REG_BASE + 0x8)\n+ #define MVEBU_XTAL_MODE_MASK\t\tBIT(9)\n+\n+\t/* -----------------------------------------------------\n+\t * uint32_t get_ref_clk (void);\n+\t *\n+\t * returns reference clock in MHz (25 or 40)\n+\t * -----------------------------------------------------\n+\t */\n+.globl\tget_ref_clk\n+func get_ref_clk\n+\tmov_imm\tx0, MVEBU_TEST_PIN_LATCH_N\n+\tldr\tw0, [x0]\n+\ttst\tw0, #MVEBU_XTAL_MODE_MASK\n+\tbne\t40\n+\tmov\tw0, #25\n+\tret\n+40:\n+\tmov\tw0, #40\n+\tret\n+endfunc get_ref_clk\n--- a/plat/marvell/armada/a3k/common/include/platform_def.h\n+++ b/plat/marvell/armada/a3k/common/include/platform_def.h\n@@ -164,7 +164,6 @@\n  * PL011 related constants\n  */\n #define PLAT_MARVELL_UART_BASE\t\t\t(MVEBU_REGS_BASE + 0x12000)\n-#define PLAT_MARVELL_UART_CLK_IN_HZ\t\t25000000\n \n #define PLAT_MARVELL_BL31_RUN_UART_BASE\t\tPLAT_MARVELL_BOOT_UART_BASE\n #define PLAT_MARVELL_BL31_RUN_UART_CLK_IN_HZ\tPLAT_MARVELL_BOOT_UART_CLK_IN_HZ\n--- a/plat/marvell/armada/common/aarch64/marvell_helpers.S\n+++ b/plat/marvell/armada/common/aarch64/marvell_helpers.S\n@@ -63,8 +63,16 @@ endfunc plat_marvell_calc_core_pos\n \t * ---------------------------------------------\n \t */\n func plat_crash_console_init\n-\tmov_imm\tx0, PLAT_MARVELL_UART_BASE\n+#ifdef PLAT_a3700\n+\tmov\tx1, x30\n+\tbl\tget_ref_clk\n+\tmov\tx30, x1\n+\tmov_imm\tx1, 1000000\n+\tmul\tx1, x0, x1\n+#else\n \tmov_imm\tx1, PLAT_MARVELL_UART_CLK_IN_HZ\n+#endif\n+\tmov_imm\tx0, PLAT_MARVELL_UART_BASE\n \tmov_imm\tx2, MARVELL_CONSOLE_BAUDRATE\n #ifdef PLAT_a3700\n \tb\tconsole_a3700_core_init\n--- a/plat/marvell/armada/common/marvell_console.c\n+++ b/plat/marvell/armada/common/marvell_console.c\n@@ -14,6 +14,7 @@\n \n #ifdef PLAT_a3700\n #include <drivers/marvell/uart/a3700_console.h>\n+#define PLAT_MARVELL_UART_CLK_IN_HZ (get_ref_clk() * 1000000)\n #define console_marvell_register console_a3700_register\n #else\n #include <drivers/ti/uart/uart_16550.h>\n"
  },
  {
    "path": "package/boot/arm-trusted-firmware-mvebu/patches/200-hostssl.patch",
    "content": "--- a/tools/fiptool/Makefile\n+++ b/tools/fiptool/Makefile\n@@ -20,7 +20,7 @@ ifeq (${DEBUG},1)\n else\n   HOSTCCFLAGS += -O2\n endif\n-LDLIBS := -lcrypto\n+LDLIBS := -L${OPENSSL_DIR}/lib -lcrypto\n \n ifeq (${V},0)\n   Q := @\n@@ -28,7 +28,7 @@ else\n   Q :=\n endif\n \n-INCLUDE_PATHS := -I../../include/tools_share\n+INCLUDE_PATHS := -I../../include/tools_share -I${OPENSSL_DIR}/include\n \n HOSTCC ?= gcc\n \n"
  },
  {
    "path": "package/boot/arm-trusted-firmware-mvebu/patches-a3700-utils/001-version.patch",
    "content": "diff --git a/wtmi/sys_init/Makefile b/wtmi/sys_init/Makefile\n--- a/wtmi/sys_init/Makefile\n+++ b/wtmi/sys_init/Makefile\n@@ -51,8 +51,8 @@ ECHO     = @echo\n SED      = @sed\n \n LOCAL_VERSION_STRING\t?= -armada\n-BUILD_STRING\t\t:= $(shell git log -n 1 --pretty=format:\"%h\" && (git diff-index --quiet HEAD || echo -dirty))\n-VERSION_STRING\t\t:= $(LOCAL_VERSION_STRING)-$(BUILD_STRING)\n+A3700_UTILS_COMMIT_ID\t?= $(shell git log -n 1 --pretty=format:\"%h\" && (git diff-index --quiet HEAD || echo -dirty))\n+VERSION_STRING\t\t:= $(LOCAL_VERSION_STRING)-$(A3700_UTILS_COMMIT_ID)\n \n CPUOPTS  = -mthumb -mcpu=cortex-m3 -mlittle-endian\n BINPATH  = build\n"
  },
  {
    "path": "package/boot/arm-trusted-firmware-mvebu/patches-a3700-utils/002-version_mv_ddr_fix.patch",
    "content": "--- a/Makefile\n+++ b/Makefile\n@@ -28,7 +28,7 @@\n \t@cp -f ${MV_DDR_PATH}/a3700_tool $(TIM_DDR_PATH)/ddr_tool\n \n $(TIM_DDR_PATH)/ddr_tool.verstr: $(MV_DDR_PATH)/a3700_tool\n-\t@echo mv_ddr-$(shell sed 's/^mv_ddr-//' $(MV_DDR_PATH)/localversion 2>/dev/null || echo 'unknown')$(if $(shell git -C $(MV_DDR_PATH) rev-parse --git-dir 2>/dev/null),-g$(shell git -C $(MV_DDR_PATH) rev-parse --verify --quiet --short HEAD 2>/dev/null)$(shell git -C $(MV_DDR_PATH) diff-index --quiet HEAD || echo -d)) > $@\n+\t@echo mv_ddr-$(shell sed 's/^mv_ddr-//' $(MV_DDR_PATH)/localversion 2>/dev/null || echo 'unknown')-g$(MV_DDR_COMMIT_ID) > $@\n \n mv_ddr: $(TIM_DDR_PATH)/ddr_tool $(TIM_DDR_PATH)/ddr_tool.verstr\n \n\n"
  },
  {
    "path": "package/boot/arm-trusted-firmware-mvebu/patches-mox-boot-builder/001-version.patch",
    "content": "diff --git a/wtmi/Makefile b/wtmi/Makefile\nindex 75754dc..3602ec3 100644\n--- a/wtmi/Makefile\n+++ b/wtmi/Makefile\n@@ -41,7 +41,6 @@ else\n \tLTO_FLAGS =\n endif\n \n-override WTMI_VERSION = $(shell git describe --always --dirty --tags)\n ifndef WTMI_VERSION\n $(error Repository is without git tags, please do a full git clone again)\n endif\n"
  },
  {
    "path": "package/boot/arm-trusted-firmware-mvebu/patches-mox-boot-builder/002-no-gold.patch",
    "content": "diff --git a/wtmi/Makefile b/wtmi/Makefile\nindex 75754dc..0c6238f 100644\n--- a/wtmi/Makefile\n+++ b/wtmi/Makefile\n@@ -36,7 +36,7 @@ LDSCRIPT = wtmi.ld\n INCLUDE  = -I.\n \n ifeq ($(LTO), 1)\n-\tLTO_FLAGS = -flto -flto-partition=none -Wl,-fuse-ld=gold\n+\tLTO_FLAGS = -flto -flto-partition=none\n else\n \tLTO_FLAGS =\n endif\n"
  },
  {
    "path": "package/boot/arm-trusted-firmware-mvebu/patches-mv-ddr-marvell/001-version.patch",
    "content": "diff --git a/scripts/localversion.sh b/scripts/localversion.sh\n--- a/scripts/localversion.sh\n+++ b/scripts/localversion.sh\n@@ -103,7 +103,7 @@ MV_DDR_ROOT=$1\n MV_DDR_VER_CSRC=$2\n \n # get mv_ddr git commit id\n-MV_DDR_COMMIT_ID=`git -C $MV_DDR_ROOT rev-parse --verify --quiet --short HEAD 2> /dev/null`\n+test -z \"$MV_DDR_COMMIT_ID\" && MV_DDR_COMMIT_ID=`git -C $MV_DDR_ROOT rev-parse --verify --quiet --short HEAD 2> /dev/null`\n \n # check for uncommitted changes in mv_ddr git\n MV_DDR_DIRTY_CHK=`git -C $MV_DDR_ROOT diff-index --name-only HEAD 2> /dev/null`\n"
  },
  {
    "path": "package/boot/arm-trusted-firmware-rk3328/Makefile",
    "content": "#\n# Copyright (C) 2021 ImmortalWrt\n# (https://immortalwrt.org)\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=arm-trusted-firmware-rk3328\nPKG_RELEASE:=1\n\nPKG_SOURCE_PROTO:=git\nPKG_SOURCE_URL=https://github.com/rockchip-linux/rkbin.git\nPKG_SOURCE_DATE:=2021-06-01\nPKG_SOURCE_VERSION:=7d631e0d5b2d373b54d4533580d08fb9bd2eaad4\nPKG_MIRROR_HASH:=73deb217d7f1dc87bb7a32a1b6855f957aeeb21dca86cdd5840c463683dc0f7d\n\nPKG_MAINTAINER:=AmadeusGhost <amadeus@immortalwrt.org>\n\nMAKE_PATH:=$(PKG_NAME)\n\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine Package/arm-trusted-firmware-rk3328\n    SECTION:=boot\n    CATEGORY:=Boot Loaders\n    TITLE:=ARM Trusted Firmware for Rockchip\n    DEPENDS:=@TARGET_rockchip_armv8\nendef\n\ndefine Build/Configure\n\t$(SED) 's,$$$$(PKG_BUILD_DIR),$(PKG_BUILD_DIR),g' $(PKG_BUILD_DIR)/trust.ini\n\t$(call Build/Configure/Default)\nendef\n\ndefine Build/Compile\n\tmkimage -n rk3328 -T rksd -d $(PKG_BUILD_DIR)/bin/rk33/rk3328_ddr_333MHz_v1.17.bin $(PKG_BUILD_DIR)/idbloader.bin\n\tcat $(PKG_BUILD_DIR)/bin/rk33/rk322xh_miniloader_v2.50.bin >> $(PKG_BUILD_DIR)/idbloader.bin\n\t$(PKG_BUILD_DIR)/tools/trust_merger --replace bl31.elf $(PKG_BUILD_DIR)/bin/rk33/rk322xh_bl31_v1.46.elf $(PKG_BUILD_DIR)/trust.ini\nendef\n\ndefine Build/InstallDev\n\t$(INSTALL_DIR) -p $(STAGING_DIR_IMAGE)\n\t$(CP) $(PKG_BUILD_DIR)/bin/rk33/rk322xh_bl31_v1.46.elf $(STAGING_DIR_IMAGE)/\n\t$(CP) $(PKG_BUILD_DIR)/tools/loaderimage $(STAGING_DIR_IMAGE)/\n\t$(CP) $(PKG_BUILD_DIR)/idbloader.bin $(STAGING_DIR_IMAGE)/\n\t$(CP) $(PKG_BUILD_DIR)/trust.bin $(STAGING_DIR_IMAGE)/\nendef\n\ndefine Package/arm-trusted-firmware-rk3328/install\nendef\n\n$(eval $(call BuildPackage,arm-trusted-firmware-rk3328))\n"
  },
  {
    "path": "package/boot/arm-trusted-firmware-rk3328/src/trust.ini",
    "content": "[VERSION]\nMAJOR=1\nMINOR=0\n[BL30_OPTION]\nSEC=0\n[BL31_OPTION]\nSEC=1\nPATH=bl31.elf\nADDR=0x10000\n[BL32_OPTION]\nSEC=0\n[BL33_OPTION]\nSEC=0\n[OUTPUT]\nPATH=$(PKG_BUILD_DIR)/trust.bin\n"
  },
  {
    "path": "package/boot/arm-trusted-firmware-rockchip/Makefile",
    "content": "#\n# Copyright (C) 2020 Tobias Maedel <openwrt@tbspace.de>\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=arm-trusted-firmware-rockchip\nPKG_VERSION:=2.3\nPKG_RELEASE:=1\n\nPKG_SOURCE:=atf-v$(PKG_VERSION).tar.gz\nPKG_SOURCE_URL:=https://github.com/atf-builds/atf/releases/download/v$(PKG_VERSION)/atf-v$(PKG_VERSION).tar.gz?\nPKG_HASH:=bf352298743aed594cf2958dd588e06ab6713fc514bb6f809bf55a85a87134c1\n\nPKG_LICENSE:=BSD-3-Clause\nPKG_LICENSE_FILES:=license.md\n\nPKG_MAINTAINER:=Tobias Maedel <openwrt@tbspace.de>\n\nMAKE_PATH:=$(PKG_NAME)\n\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine Package/arm-trusted-firmware-rockchip\n    SECTION:=boot\n    CATEGORY:=Boot Loaders\n    TITLE:=ARM Trusted Firmware for Rockchip\n    DEPENDS:=@TARGET_rockchip_armv8\nendef\n\ndefine Build/Prepare\n\t$(TAR) -C $(PKG_BUILD_DIR) -xf $(DL_DIR)/$(PKG_SOURCE)\nendef\n\ndefine Build/Compile\nendef\n\ndefine Build/InstallDev\n\t$(INSTALL_DIR) -p $(STAGING_DIR_IMAGE)\n\t$(CP) $(PKG_BUILD_DIR)/rk*.elf $(STAGING_DIR_IMAGE)/\nendef\n\ndefine Package/arm-trusted-firmware-rockchip/install\nendef\n\n$(eval $(call BuildPackage,arm-trusted-firmware-rockchip))\n"
  },
  {
    "path": "package/boot/arm-trusted-firmware-sunxi/Makefile",
    "content": "#\n# Copyright (C) 2017 Hauke Mehrtens\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=arm-trusted-firmware-sunxi\nPKG_RELEASE:=1\n\nPKG_SOURCE_PROTO:=git\nPKG_SOURCE_URL=https://github.com/ARM-software/arm-trusted-firmware\nPKG_SOURCE_DATE:=2020-11-17\nPKG_SOURCE_VERSION:=e2c509a39c6cc4dda8734e6509cdbe6e3603cdfc\nPKG_MIRROR_HASH:=b212d369a5286ebbf6a5616486efa05fa54d4294fd6e9ba2e54fdfae9eda918d\n\nPKG_LICENSE:=BSD-3-Clause\nPKG_LICENSE_FILES:=license.md\n\nPKG_MAINTAINER:=Hauke Mehrtens <hauke@hauke-m.de>\n\ninclude $(INCLUDE_DIR)/trusted-firmware-a.mk\ninclude $(INCLUDE_DIR)/package.mk\n\n\ndefine Package/arm-trusted-firmware-sunxi/Default\n    SECTION:=boot\n    CATEGORY:=Boot Loaders\n    TITLE:=ARM Trusted Firmware for Allwinner\n    DEPENDS:=@TARGET_sunxi_cortexa53\nendef\n\ndefine Package/arm-trusted-firmware-sunxi-a64\n    $(call Package/arm-trusted-firmware-sunxi/Default)\n    VARIANT:=sun50i_a64\nendef\n\ndefine Package/arm-trusted-firmware-sunxi-h6\n    $(call Package/arm-trusted-firmware-sunxi/Default)\n    VARIANT:=sun50i_h6\nendef\n\nexport GCC_HONOUR_COPTS=s\n\nMAKE_VARS = \\\n\tCROSS_COMPILE=\"$(TARGET_CROSS)\"\n\nMAKE_FLAGS += \\\n\tPLAT=$(BUILD_VARIANT) \\\n\tbl31\n\ndefine Build/InstallDev\n\t$(INSTALL_DIR) $(STAGING_DIR_IMAGE)\n\t$(CP) $(PKG_BUILD_DIR)/build/$(BUILD_VARIANT)/release/bl31.bin $(STAGING_DIR_IMAGE)/bl31_$(BUILD_VARIANT).bin\nendef\n\ndefine Package/arm-trusted-firmware-sunxi/install\nendef\n\n$(eval $(call BuildPackage,arm-trusted-firmware-sunxi-a64))\n$(eval $(call BuildPackage,arm-trusted-firmware-sunxi-h6))\n"
  },
  {
    "path": "package/boot/arm-trusted-firmware-tools/Makefile",
    "content": "#\n# Copyright 2021 Daniel Golle\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=arm-trusted-firmware-tools\nPKG_VERSION:=2.4\nPKG_RELEASE:=1\nPKG_HASH:=bf3eb3617a74cddd7fb0e0eacbfe38c3258ee07d4c8ed730deef7a175cc3d55b\n\nPKG_MAINTAINER:=Daniel Golle <daniel@makrotopia.org>\nPKG_HOST_ONLY:=1\n\nHOST_BUILD_DIR:=$(BUILD_DIR_HOST)/trusted-firmware-a-$(PKG_VERSION)\n\ninclude $(INCLUDE_DIR)/trusted-firmware-a.mk\ninclude $(INCLUDE_DIR)/package.mk\ninclude $(INCLUDE_DIR)/host-build.mk\n\ndefine Package/arm-trusted-firmware-tools\n  SECTION:=boot\n  CATEGORY:=Boot Loaders\n  TITLE:=ARM Trusted Firmware tools\n  URL:=https://www.trustedfirmware.org\n  BUILDONLY:=1\nendef\n\ndefine Host/Compile\n\t$(MAKE) -C \\\n\t\t$(HOST_BUILD_DIR)/tools/fiptool \\\n\t\tCPPFLAGS=\"$(HOST_CFLAGS)\" \\\n\t\tLDFLAGS=\"$(HOST_LDFLAGS)\"\n\t$(MAKE) -C \\\n\t\t$(HOST_BUILD_DIR)/tools/sptool \\\n\t\tCPPFLAGS=\"$(HOST_CFLAGS)\" \\\n\t\tLDFLAGS=\"$(HOST_LDFLAGS)\"\nendef\n\ndefine Host/Install\n\t$(INSTALL_DIR) $(STAGING_DIR_HOST)/bin/\n\t$(INSTALL_BIN) $(HOST_BUILD_DIR)/tools/fiptool/fiptool $(STAGING_DIR_HOST)/bin/\n\t$(INSTALL_BIN) $(HOST_BUILD_DIR)/tools/sptool/sptool $(STAGING_DIR_HOST)/bin/\n\t$(INSTALL_BIN) $(HOST_BUILD_DIR)/tools/sptool/sp_mk_generator.py $(STAGING_DIR_HOST)/bin/\nendef\n\ndefine Host/Clean\n\trm -f $(STAGING_DIR_HOST)/bin/fiptool\n\trm -f $(STAGING_DIR_HOST)/bin/sptool\n\trm -f $(STAGING_DIR_HOST)/bin/sp_mk_generator.py\nendef\n\n$(eval $(call BuildPackage,arm-trusted-firmware-tools))\n$(eval $(call HostBuild))\n"
  },
  {
    "path": "package/boot/arm-trusted-firmware-tools/patches/001-respect-LDFLAGS.patch",
    "content": "--- a/tools/fiptool/Makefile\n+++ b/tools/fiptool/Makefile\n@@ -38,7 +38,7 @@\n \n ${PROJECT}: ${OBJECTS} Makefile\n \t@echo \"  HOSTLD  $@\"\n-\t${Q}${HOSTCC} ${OBJECTS} -o $@ ${LDLIBS}\n+\t${Q}${HOSTCC} ${OBJECTS} -o $@ ${LDLIBS} $(LDFLAGS)\n \t@${ECHO_BLANK_LINE}\n \t@echo \"Built $@ successfully\"\n \t@${ECHO_BLANK_LINE}\n"
  },
  {
    "path": "package/boot/at91bootstrap/Makefile",
    "content": "#\n# Copyright (C) 2016 Microchip Technology Inc.\n#     <Sandeepsheriker.mallikarjun@microchip.com>\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=at91bootstrap\nPKG_VERSION:=v4.0.1\nPKG_MIRROR_HASH:=3d45a4bcb52162097d4cdf042b8fe1ccf53e88b512e7541f42a23f2a73692a69\nPKG_SOURCE_VERSION:=4d41296e9ae12379555fb46a941897e7264600a2\nBINARIES_DIR:=build/binaries\n\nAT91BOOTSTRAP_V4=y\nifdef CONFIG_PACKAGE_at91bootstrap-sama5d4_xplaineddf_uboot_secure\n  AT91BOOTSTRAP_V4=n\nelse ifdef CONFIG_TARGET_at91_sam9x\n  ifndef CONFIG_TARGET_at91_sam9x_DEVICE_microchip_sam9x60ek\n    AT91BOOTSTRAP_V4=n\n  endif\nendif\n\nifeq ($(AT91BOOTSTRAP_V4),n)\n  PKG_VERSION=v3.10.4\n  PKG_MIRROR_HASH=6fe61fe90838e785917383bb9e887fa05e1bd061a6725954242f504e38b5c426\n  PKG_SOURCE_VERSION=404846dd283894367a015ca59189bcf927d92e11\n  BINARIES_DIR=binaries\nendif\n\nPKG_RELEASE:=2\n\nPKG_SOURCE_PROTO:=git\nPKG_SOURCE_URL:=https://github.com/linux4sam/at91bootstrap.git\nPKG_BUILD_DIR = \\\n\t$(BUILD_DIR)/$(PKG_NAME)-$(BUILD_VARIANT)/$(PKG_NAME)-$(PKG_VERSION)\n\ninclude at91bootstrap.mk\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine AT91Bootstrap/Default\n  BUILD_TARGET:=at91\n  HIDDEN:=1\n  AT91BOOTSTRAP_IMAGE:=at91bootstrap.bin\nendef\n\ndefine AT91Bootstrap/at91sam9x5eknf_uboot\n  NAME:=AT91Bootstrap for AT91SAM9X5-EK board (NandFlash)\n  BUILD_SUBTARGET:=sam9x\n  BUILD_DEVICES:=atmel_at91sam9x25ek atmel_at91sam9x35ek\nendef\n\ndefine AT91Bootstrap/at91sam9x5eksd_uboot\n  NAME:=AT91Bootstrap for AT91SAM9X5-EK board (SDcard)\n  BUILD_SUBTARGET:=sam9x\n  BUILD_DEVICES:=atmel_at91sam9x25ek atmel_at91sam9x35ek\nendef\n\ndefine AT91Bootstrap/sam9x60eknf_uboot\n  NAME:=AT91Bootstrap for SAM9X60-EK board (NandFlash)\n  BUILD_SUBTARGET:=sam9x\n  BUILD_DEVICES:=microchip_sam9x60ek\nendef\n\ndefine AT91Bootstrap/sam9x60eksd_uboot\n  NAME:=AT91Bootstrap for SAM9X60-EK board (SDcard)\n  BUILD_SUBTARGET:=sam9x\n  BUILD_DEVICES:=microchip_sam9x60ek\nendef\n\ndefine AT91Bootstrap/sama5d2_icpdf_qspi_uboot\n  TITLE:=AT91Bootstrap for SAMA5D2 ICP board (QSPI Flash)\n  BUILD_SUBTARGET:=sama5\n  BUILD_DEVICES:=microchip_sama5d2-icp\nendef\n\ndefine AT91Bootstrap/sama5d2_icpsd_uboot\n  TITLE:=AT91Bootstrap for SAMA5D2 ICP board (SDcard)\n  BUILD_SUBTARGET:=sama5\n  BUILD_DEVICES:=microchip_sama5d2-icp\nendef\n\ndefine AT91Bootstrap/sama5d2_xplaineddf_uboot\n  TITLE:=AT91Bootstrap for SAMA5D2 Xplained board (SPI Flash)\n  BUILD_SUBTARGET:=sama5\n  BUILD_DEVICES:=microchip_sama5d2-xplained\nendef\n\ndefine AT91Bootstrap/sama5d2_xplaineddf_qspi_uboot\n  TITLE:=AT91Bootstrap for SAMA5D2 Xplained board (QSPI Flash)\n  BUILD_SUBTARGET:=sama5\n  BUILD_DEVICES:=microchip_sama5d2-xplained\nendef\n\ndefine AT91Bootstrap/sama5d2_xplainedsd_uboot\n  TITLE:=AT91Bootstrap for SAMA5D2 Xplained board (SDcard/EMMC)\n  BUILD_SUBTARGET:=sama5\n  BUILD_DEVICES:=microchip_sama5d2-xplained\nendef\n\ndefine AT91Bootstrap/sama5d3_xplainednf_uboot\n  TITLE:=AT91Bootstrap for SAMA5D3 Xplained board (Nand Flash)\n  BUILD_SUBTARGET:=sama5\n  BUILD_DEVICES:=microchip_sama5d3-xplained\nendef\n\ndefine AT91Bootstrap/sama5d3_xplainedsd_uboot\n  TITLE:=AT91Bootstrap for SAMA5D3 Xplained board (SDcard)\n  BUILD_SUBTARGET:=sama5\n  BUILD_DEVICES:=microchip_sama5d3-xplained\nendef\n\ndefine AT91Bootstrap/sama5d4_xplainednf_uboot_secure\n  TITLE:=AT91Bootstrap for SAMA5D4 Xplained board (Nand Flash)\n  BUILD_SUBTARGET:=sama5\n  BUILD_DEVICES:=microchip_sama5d4-xplained\nendef\n\ndefine AT91Bootstrap/sama5d4_xplaineddf_uboot_secure\n  TITLE:=AT91Bootstrap for SAMA5D4 Xplained board (SPI Flash)\n  BUILD_SUBTARGET:=sama5\n  BUILD_DEVICES:=microchip_sama5d4-xplained\nendef\n\ndefine AT91Bootstrap/sama5d4_xplainedsd_uboot_secure\n  TITLE:=AT91Bootstrap for SAMA5D4 Xplained board (SDcard)\n  BUILD_SUBTARGET:=sama5\n  BUILD_DEVICES:=microchip_sama5d4-xplained\nendef\n\ndefine AT91Bootstrap/sama5d27_som1_eksd_uboot\n  TITLE:=AT91Bootstrap for SAMA5D27 SOM1 Ek (SDcard0)\n  BUILD_SUBTARGET:=sama5\n  BUILD_DEVICES:=microchip_sama5d27-som1-ek\nendef\n\ndefine AT91Bootstrap/sama5d27_som1_eksd1_uboot\n  TITLE:=AT91Bootstrap for SAMA5D27 SOM1 Ek (SDcard1)\n  BUILD_SUBTARGET:=sama5\n  BUILD_DEVICES:=microchip_sama5d27-som1-ek\nendef\n\ndefine AT91Bootstrap/sama5d27_som1_ekqspi_uboot\n  TITLE:=AT91Bootstrap for SAMA5D27 SOM1 Ek (QSPI Flash)\n  BUILD_SUBTARGET:=sama5\n  BUILD_DEVICES:=microchip_sama5d27-som1-ek\nendef\n\ndefine AT91Bootstrap/sama5d27_wlsom1_eksd_uboot\n  TITLE:=AT91Bootstrap for SAMA5D27 WLSOM1 Ek (SDcard0)\n  BUILD_SUBTARGET:=sama5\n  BUILD_DEVICES:=microchip_sama5d27-wlsom1-ek\nendef\n\ndefine AT91Bootstrap/sama5d27_wlsom1_ekdf_qspi_uboot\n  TITLE:=AT91Bootstrap for SAMA5D27 WLSOM1 Ek (QSPI Flash)\n  BUILD_SUBTARGET:=sama5\n  BUILD_DEVICES:=microchip_sama5d27-wlsom1-ek\nendef\n\ndefine AT91Bootstrap/sama5d2_ptc_eknf_uboot\n  TITLE:=AT91Bootstrap for SAMA5D2 PTC EK (Nand Flash)\n  BUILD_SUBTARGET:=sama5\n  BUILD_DEVICES:=microchip_sama5d2-ptc-ek\nendef\n\ndefine AT91Bootstrap/sama5d2_ptc_eksd_uboot\n  TITLE:=AT91Bootstrap for SAMA5D2 PTC EK (SDCard)\n  BUILD_SUBTARGET:=sama5\n  BUILD_DEVICES:=microchip_sama5d2-ptc-ek\nendef\n\ndefine AT91Bootstrap/sama7g5eksd_uboot\n  TITLE:=AT91Bootstrap for SAMA7G5-EK (SDCard)\n  BUILD_SUBTARGET:=sama7\n  BUILD_DEVICES:=microchip_sama7g5-ek\nendef\n\nAT91BOOTSTRAP_TARGETS := \\\n\tat91sam9x5eknf_uboot \\\n\tat91sam9x5eksd_uboot \\\n\tsam9x60eknf_uboot \\\n\tsam9x60eksd_uboot \\\n\tsama5d2_icpdf_qspi_uboot \\\n\tsama5d2_icpsd_uboot \\\n\tsama5d2_xplaineddf_uboot \\\n\tsama5d2_xplaineddf_qspi_uboot \\\n\tsama5d2_xplainedsd_uboot \\\n\tsama5d3_xplainednf_uboot \\\n\tsama5d3_xplainedsd_uboot \\\n\tsama5d4_xplainednf_uboot_secure \\\n\tsama5d4_xplaineddf_uboot_secure \\\n\tsama5d4_xplainedsd_uboot_secure \\\n\tsama5d27_som1_eksd1_uboot \\\n\tsama5d27_som1_ekqspi_uboot \\\n\tsama5d27_wlsom1_eksd_uboot \\\n\tsama5d27_wlsom1_ekdf_qspi_uboot \\\n\tsama5d2_ptc_eknf_uboot \\\n\tsama5d2_ptc_eksd_uboot \\\n\tsama7g5eksd_uboot\n\ndefine Build/Compile\n\t+$(MAKE) $(PKG_JOBS) -C $(PKG_BUILD_DIR) \\\n\t\tCROSS_COMPILE=$(TARGET_CROSS)\nendef\n\n$(eval $(call BuildPackage/AT91Bootstrap))\n"
  },
  {
    "path": "package/boot/at91bootstrap/at91bootstrap.mk",
    "content": "\nPKG_TARGETS := bin\nPKG_FLAGS:=nonshared\n\nexport GCC_HONOUR_COPTS=s\n\ndefine Package/at91bootstrap/install/default\n\t$(CP) -avL $(PKG_BUILD_DIR)/$(BINARIES_DIR)/at91bootstrap.bin $(1)/\nendef\n\nPackage/at91bootstrap/install = $(Package/at91bootstrap/install/default)\n\ndefine AT91Bootstrap/Init\n  BUILD_TARGET:=\n  BUILD_SUBTARGET:=\n  BUILD_DEVICES:=\n  NAME:=\n  DEPENDS:=\n  HIDDEN:=\n  DEFAULT:=\n  VARIANT:=$(1)\n  AT91BOOTSTRAP_CONFIG:=$(1)\nendef\n\nTARGET_DEP = TARGET_$(BUILD_TARGET)$(if $(BUILD_SUBTARGET),_$(BUILD_SUBTARGET))\n\nAT91BOOTSTRAP_MAKE_FLAGS = \\\n\tHOSTCC=\"$(HOSTCC)\" \\\n\tHOSTCFLAGS=\"$(HOST_CFLAGS) $(HOST_CPPFLAGS)\" \\\n\tHOSTLDFLAGS=\"\"\n\ndefine Build/AT91Bootstrap/Target\n  $(eval $(call AT91Bootstrap/Init,$(1)))\n  $(eval $(call AT91Bootstrap/Default,$(1)))\n  $(eval $(call AT91Bootstrap/$(1),$(1)))\n\n  define Package/at91bootstrap-$(1)\n    SECTION:=boot\n    CATEGORY:=Boot Loaders\n    TITLE:= .$(NAME)\n    VARIANT:=$(VARIANT)\n    DEPENDS:=@!IN_SDK $(DEPENDS)\n    HIDDEN:=$(HIDDEN)\n    ifneq ($(BUILD_TARGET),)\n      DEPENDS += @$(TARGET_DEP)\n      ifneq ($(BUILD_DEVICES),)\n        DEFAULT := y if ($(TARGET_DEP)_Default \\\n          $(patsubst %,|| $(TARGET_DEP)_DEVICE_%,$(BUILD_DEVICES)) \\\n          $(patsubst %,|| $(patsubst TARGET_%,TARGET_DEVICE_%, \\\n          $(TARGET_DEP))_DEVICE_%,$(BUILD_DEVICES)))\n      endif\n    endif\n    $(if $(DEFAULT),DEFAULT:=$(DEFAULT))\n    URL:=https://www.at91.com/linux4sam/bin/view/Linux4SAM/AT91Bootstrap\n  endef\n\n  define Package/at91bootstrap-$(1)/install\n    $$(Package/at91bootstrap/install)\n  endef\nendef\n\ndefine Build/Configure/AT91Bootstrap\n\t+$(MAKE) $(PKG_JOBS) -C $(PKG_BUILD_DIR) \\\n\t\t$(AT91BOOTSTRAP_CONFIG)_defconfig\nendef\n\n\ndefine Build/Compile/AT91Bootstrap\n\t+$(MAKE) $(PKG_JOBS) -C $(PKG_BUILD_DIR) \\\n\t\tCROSS_COMPILE=$(TARGET_CROSS) \\\n\t\t$(AT91BOOTSTRAP_MAKE_FLAGS)\nendef\n\ndefine BuildPackage/AT91Bootstrap/Defaults\n\tBuild/Configure/Default = $$$$(Build/Configure/AT91Bootstrap)\n\tBuild/Compile/Default = $$$$(Build/Compile/AT91Bootstrap)\nendef\n\ndefine BuildPackage/AT91Bootstrap\n\t$(eval $(call BuildPackage/AT91Bootstrap/Defaults))\n\t$(foreach type,$(if $(DUMP),$(AT91BOOTSTRAP_TARGETS),$(BUILD_VARIANT)), \\\n\t\t$(eval $(call Build/AT91Bootstrap/Target,$(type)))\n\t)\n\t$(eval $(call Build/DefaultTargets))\n\t$(foreach type,$(if $(DUMP),$(AT91BOOTSTRAP_TARGETS),$(BUILD_VARIANT)), \\\n\t\t$(call BuildPackage,at91bootstrap-$(type))\n\t)\nendef\n"
  },
  {
    "path": "package/boot/fconfig/Makefile",
    "content": "#\n# Copyright (C) 2006-2008 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=fconfig\nPKG_VERSION:=20080329\nPKG_RELEASE:=1\n\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz\nPKG_SOURCE_URL:=@OPENWRT\nPKG_HASH:=4ff0e8f07e35e46b705c0dbe9d9544ede01ea092a69e3f7db03e55a3f2bb8eb7\n\nPKG_BUILD_DIR:=$(BUILD_DIR)/$(PKG_NAME)\n\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine Package/fconfig\n  SECTION:=utils\n  CATEGORY:=Utilities\n  SUBMENU:=Boot Loaders\n  TITLE:=RedBoot configuration editor\nendef\n\ndefine Package/fconfig/description\n\tdisplays and (if writable) also edits the RedBoot configuration.\nendef\n\ndefine Package/fconfig/install\n\t$(INSTALL_DIR) $(1)/usr/sbin\n\t$(INSTALL_BIN) $(PKG_BUILD_DIR)/fconfig $(1)/usr/sbin/\nendef\n\n$(eval $(call BuildPackage,fconfig))\n"
  },
  {
    "path": "package/boot/grub2/Makefile",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2006-2021 OpenWrt.org\n\ninclude $(TOPDIR)/rules.mk\ninclude $(INCLUDE_DIR)/kernel.mk\n\nPKG_NAME:=grub\nPKG_VERSION:=2.06\nPKG_RELEASE:=$(AUTORELEASE)\n\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz\nPKG_SOURCE_URL:=@GNU/grub\nPKG_HASH:=b79ea44af91b93d17cd3fe80bdae6ed43770678a9a5ae192ccea803ebb657ee1\n\nPKG_LICENSE:=GPL-3.0-or-later\nPKG_CPE_ID:=cpe:/a:gnu:grub2\n\nHOST_BUILD_PARALLEL:=1\nPKG_BUILD_DEPENDS:=grub2/host\n\nifneq ($(BUILD_VARIANT),none)\n  PKG_ASLR_PIE:=0\n  PKG_SSP:=0\nendif\n\nPKG_FLAGS:=nonshared\n\ninclude $(INCLUDE_DIR)/host-build.mk\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine Package/grub2/Default\n  CATEGORY:=Boot Loaders\n  SECTION:=boot\n  TITLE:=GRand Unified Bootloader ($(1))\n  URL:=http://www.gnu.org/software/grub/\n  DEPENDS:=@TARGET_x86\n  VARIANT:=$(1)\nendef\n\nPackage/grub2=$(call Package/grub2/Default,pc)\nPackage/grub2-efi=$(call Package/grub2/Default,efi)\n\ndefine Package/grub2-editenv\n  CATEGORY:=Utilities\n  SECTION:=utils\n  SUBMENU:=Boot Loaders\n  TITLE:=Grub2 Environment editor\n  URL:=http://www.gnu.org/software/grub/\n  DEPENDS:=@TARGET_x86\n  VARIANT:=none\nendef\n\ndefine Package/grub2-editenv/description\n\tEdit grub2 environment files.\nendef\n\ndefine Package/grub2-bios-setup\n  CATEGORY:=Utilities\n  SECTION:=utils\n  SUBMENU:=Boot Loaders\n  TITLE:=Grub2 BIOS boot setup tool\n  URL:=http://www.gnu.org/software/grub/\n  DEPENDS:=@TARGET_x86\n  VARIANT:=none\nendef\n\ndefine Package/grub2-bios-setup/description\n\tSet up images to bootable.\nendef\n\nHOST_BUILD_PREFIX := $(STAGING_DIR_HOST)\n\nCONFIGURE_VARS += \\\n\tgrub_build_mkfont_excuse=\"don't want fonts\"\n\nCONFIGURE_ARGS += \\\n\t--target=$(REAL_GNU_TARGET_NAME) \\\n\t--disable-werror \\\n\t--disable-nls \\\n\t--disable-device-mapper \\\n\t--disable-libzfs \\\n\t--disable-liblzma \\\n\t--disable-grub-mkfont \\\n\t--with-platform=$(BUILD_VARIANT)\n\nHOST_CONFIGURE_VARS += \\\n\tgrub_build_mkfont_excuse=\"don't want fonts\"\n\nHOST_CONFIGURE_ARGS += \\\n\t--disable-grub-mkfont \\\n\t--target=$(REAL_GNU_TARGET_NAME) \\\n\t--sbindir=\"$(STAGING_DIR_HOST)/bin\" \\\n\t--disable-werror \\\n\t--disable-libzfs \\\n\t--disable-nls \\\n\t--with-platform=none\n\nHOST_MAKE_FLAGS += \\\n\tTARGET_RANLIB=$(TARGET_RANLIB) \\\n\tLIBLZMA=$(STAGING_DIR_HOST)/lib/liblzma.a\n\n\nifneq ($(BUILD_VARIANT),none)\n  TARGET_CFLAGS := $(filter-out -O2 -O3 -fno-plt,$(TARGET_CFLAGS))\n  MAKE_PATH := grub-core\nendif\n\ndefine Host/Configure\n\t$(SED) 's,(RANLIB),(TARGET_RANLIB),' $(HOST_BUILD_DIR)/grub-core/Makefile.in\n\t$(Host/Configure/Default)\nendef\n\ndefine Package/grub2/install\n\t$(INSTALL_DIR) $(STAGING_DIR_IMAGE)/grub2\n\t$(CP) $(PKG_BUILD_DIR)/grub-core/boot.img $(STAGING_DIR_IMAGE)/grub2/\n\t$(CP) $(PKG_BUILD_DIR)/grub-core/cdboot.img $(STAGING_DIR_IMAGE)/grub2/\n\tsed 's#msdos1#gpt1#g' ./files/grub-early.cfg >$(PKG_BUILD_DIR)/grub-early.cfg\n\t$(STAGING_DIR_HOST)/bin/grub-mkimage \\\n\t\t-d $(PKG_BUILD_DIR)/grub-core \\\n\t\t-p /boot/grub \\\n\t\t-O i386-pc \\\n\t\t-c $(PKG_BUILD_DIR)/grub-early.cfg \\\n\t\t-o $(STAGING_DIR_IMAGE)/grub2/gpt-core.img \\\n\t\tat_keyboard biosdisk boot chain configfile fat linux ls part_gpt reboot search serial vga\n\t$(STAGING_DIR_HOST)/bin/grub-mkimage \\\n\t\t-d $(PKG_BUILD_DIR)/grub-core \\\n\t\t-p /boot/grub \\\n\t\t-O i386-pc \\\n\t\t-c ./files/grub-early.cfg \\\n\t\t-o $(STAGING_DIR_IMAGE)/grub2/generic-core.img \\\n\t\tat_keyboard biosdisk boot chain configfile ext2 linux ls part_msdos reboot search serial vga\n\t$(STAGING_DIR_HOST)/bin/grub-mkimage \\\n\t\t-d $(PKG_BUILD_DIR)/grub-core \\\n\t\t-p /boot/grub \\\n\t\t-O i386-pc \\\n\t\t-c ./files/grub-early.cfg \\\n\t\t-o $(STAGING_DIR_IMAGE)/grub2/eltorito.img \\\n\t\tat_keyboard biosdisk boot chain configfile iso9660 linux ls part_msdos reboot search serial test vga\n\t$(STAGING_DIR_HOST)/bin/grub-mkimage \\\n\t\t-d $(PKG_BUILD_DIR)/grub-core \\\n\t\t-p /boot/grub \\\n\t\t-O i386-pc \\\n\t\t-c ./files/grub-early.cfg \\\n\t\t-o $(STAGING_DIR_IMAGE)/grub2/legacy-core.img \\\n\t\tbiosdisk boot chain configfile ext2 linux ls part_msdos reboot search serial vga\nendef\n\ndefine Package/grub2-efi/install\n\tsed 's#msdos1#gpt1#g' ./files/grub-early.cfg >$(PKG_BUILD_DIR)/grub-early.cfg\n\t$(STAGING_DIR_HOST)/bin/grub-mkimage \\\n\t\t-d $(PKG_BUILD_DIR)/grub-core \\\n\t\t-p /boot/grub \\\n\t\t-O $(CONFIG_ARCH)-efi \\\n\t\t-c $(PKG_BUILD_DIR)/grub-early.cfg \\\n\t\t-o $(STAGING_DIR_IMAGE)/grub2/boot$(if $(CONFIG_x86_64),x64,ia32).efi \\\n\t\tat_keyboard boot chain configfile fat linux ls part_gpt reboot serial efi_gop efi_uga\n\t$(STAGING_DIR_HOST)/bin/grub-mkimage \\\n\t\t-d $(PKG_BUILD_DIR)/grub-core \\\n\t\t-p /boot/grub \\\n\t\t-O $(CONFIG_ARCH)-efi \\\n\t\t-c ./files/grub-early.cfg \\\n\t\t-o $(STAGING_DIR_IMAGE)/grub2/iso-boot$(if $(CONFIG_x86_64),x64,ia32).efi \\\n\t\tat_keyboard boot chain configfile fat iso9660 linux ls part_msdos part_gpt reboot serial test efi_gop efi_uga\nendef\n\ndefine Package/grub2-editenv/install\n\t$(INSTALL_DIR) $(1)/usr/sbin\n\t$(INSTALL_BIN) $(PKG_BUILD_DIR)/grub-editenv $(1)/usr/sbin/\nendef\n\ndefine Package/grub2-bios-setup/install\n\t$(INSTALL_DIR) $(1)/usr/sbin\n\t$(INSTALL_BIN) $(PKG_BUILD_DIR)/grub-bios-setup $(1)/usr/sbin/\nendef\n\n$(eval $(call HostBuild))\n$(eval $(call BuildPackage,grub2))\n$(eval $(call BuildPackage,grub2-efi))\n$(eval $(call BuildPackage,grub2-editenv))\n$(eval $(call BuildPackage,grub2-bios-setup))\n"
  },
  {
    "path": "package/boot/grub2/files/grub-early.cfg",
    "content": "configfile (hd0,msdos1)/boot/grub/grub.cfg\n"
  },
  {
    "path": "package/boot/grub2/patches/100-grub_setup_root.patch",
    "content": "--- a/include/grub/util/install.h\n+++ b/include/grub/util/install.h\n@@ -198,13 +198,13 @@ grub_install_get_image_target (const cha\n void\n grub_util_bios_setup (const char *dir,\n \t\t      const char *boot_file, const char *core_file,\n-\t\t      const char *dest, int force,\n+\t\t      const char *root, const char *dest, int force,\n \t\t      int fs_probe, int allow_floppy,\n \t\t      int add_rs_codes, int warn_short_mbr_gap);\n void\n grub_util_sparc_setup (const char *dir,\n \t\t       const char *boot_file, const char *core_file,\n-\t\t       const char *dest, int force,\n+\t\t       const char *root, const char *dest, int force,\n \t\t       int fs_probe, int allow_floppy,\n \t\t       int add_rs_codes, int warn_short_mbr_gap);\n \n--- a/util/grub-install.c\n+++ b/util/grub-install.c\n@@ -1721,7 +1721,7 @@ main (int argc, char *argv[])\n \tif (install_bootsector)\n \t  {\n \t    grub_util_bios_setup (platdir, \"boot.img\", \"core.img\",\n-\t\t\t\t  install_drive, force,\n+\t\t\t\t  NULL, install_drive, force,\n \t\t\t\t  fs_probe, allow_floppy, add_rs_codes,\n \t\t\t\t  !grub_install_is_short_mbrgap_supported ());\n \n@@ -1752,7 +1752,7 @@ main (int argc, char *argv[])\n \tif (install_bootsector)\n \t  {\n \t    grub_util_sparc_setup (platdir, \"boot.img\", \"core.img\",\n-\t\t\t\t   install_drive, force,\n+\t\t\t\t   NULL, install_drive, force,\n \t\t\t\t   fs_probe, allow_floppy,\n \t\t\t\t   0 /* unused */, 0 /* unused */ );\n \n--- a/util/grub-setup.c\n+++ b/util/grub-setup.c\n@@ -87,6 +87,8 @@ static struct argp_option options[] = {\n    N_(\"install even if problems are detected\"), 0},\n   {\"skip-fs-probe\",'s',0,      0,\n    N_(\"do not probe for filesystems in DEVICE\"), 0},\n+  {\"root-device\", 'r', N_(\"DEVICE\"), 0,\n+   N_(\"use DEVICE as the root device\"), 0},\n   {\"verbose\",     'v', 0,      0, N_(\"print verbose messages.\"), 0},\n   {\"allow-floppy\", 'a', 0,      0,\n    /* TRANSLATORS: The potential breakage isn't limited to floppies but it's\n@@ -130,6 +132,7 @@ struct arguments\n   char *core_file;\n   char *dir;\n   char *dev_map;\n+  char *root_dev;\n   int  force;\n   int  fs_probe;\n   int allow_floppy;\n@@ -178,6 +181,13 @@ argp_parser (int key, char *arg, struct\n         arguments->dev_map = xstrdup (arg);\n         break;\n \n+      case 'r':\n+        if (arguments->root_dev)\n+          free (arguments->root_dev);\n+\n+        arguments->root_dev = xstrdup (arg);\n+        break;\n+\n       case 'f':\n         arguments->force = 1;\n         break;\n@@ -313,7 +323,7 @@ main (int argc, char *argv[])\n   GRUB_SETUP_FUNC (arguments.dir ? : DEFAULT_DIRECTORY,\n \t\t   arguments.boot_file ? : DEFAULT_BOOT_FILE,\n \t\t   arguments.core_file ? : DEFAULT_CORE_FILE,\n-\t\t   dest_dev, arguments.force,\n+\t\t   arguments.root_dev, dest_dev, arguments.force,\n \t\t   arguments.fs_probe, arguments.allow_floppy,\n \t\t   arguments.add_rs_codes, 0);\n \n--- a/util/setup.c\n+++ b/util/setup.c\n@@ -252,14 +252,13 @@ identify_partmap (grub_disk_t disk __att\n void\n SETUP (const char *dir,\n        const char *boot_file, const char *core_file,\n-       const char *dest, int force,\n+       const char *root, const char *dest, int force,\n        int fs_probe, int allow_floppy,\n        int add_rs_codes __attribute__ ((unused)), /* unused on sparc64 */\n        int warn_small)\n {\n   char *core_path;\n   char *boot_img, *core_img, *boot_path;\n-  char *root = 0;\n   size_t boot_size, core_size;\n   grub_uint16_t core_sectors;\n   grub_device_t root_dev = 0, dest_dev, core_dev;\n@@ -311,7 +310,10 @@ SETUP (const char *dir,\n \n   core_dev = dest_dev;\n \n-  {\n+  if (root)\n+    root_dev = grub_device_open(root);\n+\n+  if (!root_dev) {\n     char **root_devices = grub_guess_root_devices (dir);\n     char **cur;\n     int found = 0;\n@@ -324,6 +326,8 @@ SETUP (const char *dir,\n \tchar *drive;\n \tgrub_device_t try_dev;\n \n+\tif (root_dev)\n+\t  break;\n \tdrive = grub_util_get_grub_dev (*cur);\n \tif (!drive)\n \t  continue;\n"
  },
  {
    "path": "package/boot/imx-bootlets/Makefile",
    "content": "#\n# Copyright (C) 2006 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=imx-bootlets\nPKG_VERSION:=10.05.02\n\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz\nPKG_SOURCE_URL:=http://trabant.uid0.hu/openwrt/\nPKG_HASH:=09ecd81a64db5166a235932146faf08d0689bfc7ac04ac9fcc3a5bd809fba74a\n\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine Package/imx-bootlets\n\tSECTION:=boot\n\tCATEGORY:=Boot Loaders\n\tTITLE:=i.MX23/i.MX28 bootlets\n\tDEPENDS:=@TARGET_mxs\nendef\n\ndefine Package/imx-bootlets/description\n i.MX23/i.MX28 bootlets (for oLinuxino)\nendef\n\ndefine Build/Compile\n\t$(MAKE) -C $(PKG_BUILD_DIR) CROSS_COMPILE=\"$(TARGET_CROSS)\"\nendef\n\ndefine Package/imx-bootlets/install\n\t@echo Copying boot_prep and power_prep into staging - $(STAGING_DIR)\n\t$(INSTALL_BIN) $(PKG_BUILD_DIR)/boot_prep/boot_prep $(STAGING_DIR)/boot_prep\n\t$(INSTALL_BIN) $(PKG_BUILD_DIR)/linux_prep/output-target/linux_prep $(STAGING_DIR)/linux_prep\n\t$(INSTALL_BIN) $(PKG_BUILD_DIR)/power_prep/power_prep $(STAGING_DIR)/power_prep\n\t$(INSTALL_BIN) $(PKG_BUILD_DIR)/linux_prebuilt.db $(STAGING_DIR)/linux_prebuilt.db\nendef\n\n$(eval $(call BuildPackage,imx-bootlets))\n\n"
  },
  {
    "path": "package/boot/imx-bootlets/patches/001-skip_sb_generation.patch",
    "content": "--- a/Makefile\n+++ b/Makefile\n@@ -32,10 +32,11 @@ ifeq \"$(DFT_IMAGE)\" \"$(wildcard $(DFT_IM\n \tsed -i 's,[^ *]image.*;,\\timage=\"$(DFT_UBOOT)\";,' uboot.db\n \telftosb2 -z -c ./uboot.db -o i$(ARCH)_uboot.sb\n else\n-\t@echo \"by using the pre-built kernel\"\n-\telftosb2 -z -c ./linux_prebuilt.db -o i$(ARCH)_linux.sb\n-\t@echo \"generating U-Boot boot stream image\"\n-\telftosb2 -z -c ./uboot_prebuilt.db -o i$(ARCH)_uboot.sb\n+\t@echo \"... not generating any image for now.\"\n+\t#@echo \"by using the pre-built kernel\"\n+\t#elftosb2 -z -c ./linux_prebuilt.db -o i$(ARCH)_linux.sb\n+\t#@echo \"generating U-Boot boot stream image\"\n+\t#elftosb2 -z -c ./uboot_prebuilt.db -o i$(ARCH)_uboot.sb\n endif\n \t#@echo \"generating kernel bootstream file sd_mmc_bootstream.raw\"\n \t#Please use cfimager to burn xxx_linux.sb. The below way will no\n"
  },
  {
    "path": "package/boot/imx-bootlets/patches/002-set_elftosb_config.patch",
    "content": "--- a/linux_prebuilt.db\n+++ b/linux_prebuilt.db\n@@ -4,10 +4,10 @@ options {\n \tflags = 0x01;\n }\n sources {\n-\tpower_prep=\"./power_prep/power_prep\";\n-\tsdram_prep=\"./boot_prep/boot_prep\";\n-\tlinux_prep=\"./linux_prep/output-target/linux_prep\";\n-\tzImage = \"./zImage\";\n+\tpower_prep=\"./power_prep\";\n+\tsdram_prep=\"./boot_prep\";\n+\tlinux_prep=\"./linux_prep\";\n+\tzImage = \"./zImage_dtb\";\n }\n \n section (0) {\n"
  },
  {
    "path": "package/boot/imx-bootlets/patches/003-add-olinuxino.patch",
    "content": "--- /dev/null\n+++ b/linux_prep/board/imx23_olinuxino_dev.c\n@@ -0,0 +1,54 @@\n+/*\n+ * Platform specific data for the IMX23_OLINUXINO development board\n+ *\n+ * Fadil Berisha <fadil.r.berisha@gmail.com>\n+ *\n+ * Copyright 2008 SigmaTel, Inc\n+ * Copyright 2008 Embedded Alley Solutions, Inc\n+ * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.\n+ *\n+ * This file is licensed under the terms of the GNU General Public License\n+ * version 2. This program is licensed \"as is\" without any warranty of any\n+ * kind, whether express or implied.\n+ *\n+ * http://www.opensource.org/licenses/gpl-license.html\n+ * http://www.gnu.org/copyleft/gpl.html\n+ */\n+#include <setup.h>\n+#include <keys.h>\n+#include <lradc_buttons.h>\n+\n+/************************************************\n+ * LRADC keyboard data *\n+ ************************************************/\n+int lradc_keypad_ch = LRADC_CH0;\n+int lradc_vddio_ch = LRADC_CH6;\n+\n+struct lradc_keycode lradc_keycodes[] = {\n+ { 100, KEY4 },\n+ { 306, KEY5 },\n+ { 601, KEY6 },\n+ { 932, KEY7 },\n+ { 1260, KEY8 },\n+ { 1424, KEY9 },\n+ { 1707, KEY10 },\n+ { 2207, KEY11 },\n+ { 2525, KEY12 },\n+ { 2831, KEY13 },\n+ { 3134, KEY14 },\n+ { -1, 0 },\n+};\n+\n+/************************************************\n+ * Magic key combinations for Armadillo *\n+ ************************************************/\n+u32 magic_keys[MAGIC_KEY_NR] = {\n+ [MAGIC_KEY1] = KEY4,\n+ [MAGIC_KEY2] = KEY6,\n+ [MAGIC_KEY3] = KEY10,\n+};\n+\n+/************************************************\n+ * Default command line *\n+ ************************************************/\n+char cmdline_def[] = \"console=ttyAMA0,115200\";\n--- /dev/null\n+++ b/linux_prep/cmdlines/imx23_olinuxino_dev.txt\n@@ -0,0 +1 @@\n+noinitrd console=ttyAMA0,115200 root=/dev/mmcblk0p2 rw rootwait ssp1=mmc\n--- a/linux_prep/core/setup.c\n+++ b/linux_prep/core/setup.c\n@@ -84,6 +84,8 @@ static void *memcpy(void *s1, const void\n #include \"../../mach-mx28/includes/registers/regsrtc.h\"\n #elif defined(STMP378X)\n #include \"../../mach-mx23/includes/registers/regsrtc.h\"\n+#elif defined(IMX23_OLINUXINO)\n+#include \"../../mach-mx23/includes/registers/regsrtc.h\"\n #endif\n \n #define NAND_SECONDARY_BOOT          0x00000002\n--- a/linux_prep/include/mx23/platform.h\n+++ b/linux_prep/include/mx23/platform.h\n@@ -19,6 +19,10 @@\n \n #if defined (BOARD_STMP378X_DEV)\n #define\tMACHINE_ID\t0xa45\n+\n+#elif defined (BOARD_IMX23_OLINUXINO_DEV)\n+#define MACHINE_ID 0x1009\n+\n #else\n #error \"Allocate a machine ID for your board\"\n #endif\n--- a/linux_prep/Makefile\n+++ b/linux_prep/Makefile\n@@ -69,6 +69,11 @@ ARCH = mx28\n HW_OBJS = $(LRADC_OBJS)\n CFLAGS += -DMX28 -DBOARD_MX28_EVK\n endif\n+ifeq ($(BOARD), imx23_olinuxino_dev)\n+ARCH = mx23\n+HW_OBJS = $(LRADC_OBJS)\n+CFLAGS += -DIMX23_OLINUXINO -DBOARD_IMX23_OLINUXINO_DEV\n+endif\n \n # Generic code\n CORE_OBJS = entry.o resume.o cmdlines.o setup.o keys.o\n--- a/Makefile\n+++ b/Makefile\n@@ -3,9 +3,9 @@ MEM_TYPE ?= MEM_DDR1\n export MEM_TYPE\n \n DFT_IMAGE=$(DEV_IMAGE)/boot/zImage\n-DFT_UBOOT=$(DEV_IMAGE)/boot/u-boot\n+DFT_UBOOT=../boot/u-boot\n \n-BOARD ?= stmp378x_dev\n+BOARD ?= imx23_olinuxino_dev\n \n ifeq ($(BOARD), stmp37xx_dev)\n ARCH = 37xx\n@@ -16,6 +16,9 @@ endif\n ifeq ($(BOARD), iMX28_EVK)\n ARCH = mx28\n endif\n+ifeq ($(BOARD), imx23_olinuxino_dev)\n+ARCH = mx23\n+endif\n \n all: build_prep gen_bootstream\n \n@@ -94,6 +97,8 @@ distclean: clean\n clean:\n \t-rm -rf *.sb\n \trm -f sd_mmc_bootstream.raw\n+\trm -f linux_prep/board/*.o\n+\trm -f power_prep/*.o\n \t$(MAKE) -C linux_prep clean ARCH=$(ARCH)\n \t$(MAKE) -C boot_prep clean ARCH=$(ARCH)\n \t$(MAKE) -C power_prep clean ARCH=$(ARCH)\n--- a/uboot.db\n+++ b/uboot.db\n@@ -3,7 +3,7 @@\n sources {\n \tpower_prep=\"./power_prep/power_prep\";\n \tsdram_prep=\"./boot_prep/boot_prep\";\n-\timage=\"/home/b18647/repos/ltib_latest/rootfs/boot/u-boot\";\n+\timage=\"../boot/u-boot\";\n }\n \n section (0) {\n"
  },
  {
    "path": "package/boot/kexec-tools/Config.in",
    "content": "menu \"Configuration\"\n\tdepends on PACKAGE_kexec\n\nconfig KEXEC_ZLIB\n\tbool\n\tprompt \"zlib support\"\n\tdefault y\n\nconfig KEXEC_LZMA\n\tbool\n\tprompt \"lzma support\"\n\tdefault n\n\nendmenu\n"
  },
  {
    "path": "package/boot/kexec-tools/Makefile",
    "content": "#\n# Copyright (C) 2006-2012 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=kexec-tools\nPKG_VERSION:=2.0.21\nPKG_RELEASE:=2\n\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz\nPKG_SOURCE_URL:=@KERNEL/linux/utils/kernel/kexec\nPKG_HASH:=e113142dee891638ad96e0f72cf9277b244477619470b30c41999d312e8e8702\n\nPKG_CONFIG_DEPENDS := CONFIG_KEXEC_ZLIB CONFIG_KEXEC_LZMA\n\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine Package/kexec-tools/Default\n  SECTION:=utils\n  CATEGORY:=Utilities\n  URL:=http://kernel.org/pub/linux/kernel/people/horms/kexec-tools/\nendef\n\ndefine Package/kexec-tools\n  $(call Package/kexec-tools/Default)\n  TITLE:=kexec-tools transition meta package\n  DEPENDS:=+kexec\nendef\n\ndefine Package/kexec-tools/description\n kexec is a set of system calls that allows you to load\n another kernel from the currently executing Linux kernel.\n The kexec utility allows to load and boot another kernel.\nendef\n\ndefine Package/kexec\n  $(call Package/kexec-tools/Default)\n  TITLE:=Kernel boots kernel\n  DEPENDS:=\\\n\t@(armeb||arm||i386||x86_64||powerpc64||mipsel||mips) \\\n\t+KEXEC_ZLIB:zlib +KEXEC_LZMA:liblzma @KERNEL_KEXEC\nendef\n\ndefine Package/kexec/description\n The kexec utility allows to load and boot another kernel.\nendef\n\ndefine Package/kexec/config\n\tsource \"$(SOURCE)/Config.in\"\nendef\n\nKEXEC_TARGET_NAME:=$(ARCH)-linux-$(TARGET_SUFFIX)\n\nCONFIGURE_ARGS = \\\n\t\t--target=$(KEXEC_TARGET_NAME) \\\n\t\t--host=$(REAL_GNU_TARGET_NAME) \\\n\t\t--build=$(GNU_HOST_NAME) \\\n\t\t--program-prefix=\"\" \\\n\t\t--program-suffix=\"\" \\\n\t\t--prefix=/usr \\\n\t\t--exec-prefix=/usr \\\n\t\t--bindir=/usr/bin \\\n\t\t--sbindir=/usr/sbin \\\n\t\t--libexecdir=/usr/lib \\\n\t\t--sysconfdir=/etc \\\n\t\t$(if $(CONFIG_KEXEC_ZLIB),--with,--without)-zlib \\\n\t\t$(if $(CONFIG_KEXEC_LZMA),--with,--without)-lzma \\\n\t\tTARGET_LD=\"$(TARGET_CROSS)ld\"\n\nTARGET_CFLAGS += -ffunction-sections -fdata-sections\nTARGET_LDFLAGS += -Wl,--gc-sections\n\nCONFIGURE_VARS += \\\n\tBUILD_CC=\"$(HOSTCC)\" \\\n\tTARGET_CC=\"$(TARGET_CC)\"\n\ndefine Build/Compile\n\t$(MAKE) -C $(PKG_BUILD_DIR) DESTDIR=\"$(PKG_INSTALL_DIR)\" all install\nendef\n\ndefine Package/kexec-tools/install\n\t:\nendef\n\ndefine Package/kexec/install\n\t$(INSTALL_DIR) $(1)/usr/sbin\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/sbin/kexec $(1)/usr/sbin\n\n# make a link for compatability with other distros\n\t$(INSTALL_DIR) $(1)/sbin\n\t$(LN) ../usr/sbin/kexec $(1)/sbin/kexec\nendef\n\n$(eval $(call BuildPackage,kexec-tools))\n$(eval $(call BuildPackage,kexec))\n"
  },
  {
    "path": "package/boot/kexec-tools/files/kdump.config",
    "content": "\nconfig kdump\n\toption enabled '1'\n\toption save_dmesg '1'\n\toption save_vmcore '0'\n# using an external partition to store vmcore is highly recommended!\n#\toption path '/mnt/crashdump'\n"
  },
  {
    "path": "package/boot/kexec-tools/files/kdump.defaults",
    "content": "#!/bin/sh\n\n# kB disable if mem low than 256MB\nmemtotal=`grep MemTotal /proc/meminfo | awk '{print $2}'`\nif test $memtotal -le 262144; then\n\texit 0\nfi\nKZ=128\nif test $memtotal -ge 8388608; then\n\tKZ=512\nelif test $memtotal -ge 4194304; then\n\tKZ=256\nfi\n\ncase $(uname -m) in\n\ti?86|x86_64)\n\t\tif ! grep -q crashkernel /boot/grub/grub.cfg; then\n\t\t\tmount /boot -o remount,rw\n\t\t\tsed -i \"s/linux.*/& crashkernel=${KZ}M/\" /boot/grub/grub.cfg\n\t\t\tmount /boot -o remount,ro\n\t\tfi\n\t\t;;\nesac\n"
  },
  {
    "path": "package/boot/kexec-tools/files/kdump.init",
    "content": "#!/bin/sh /etc/rc.common\n\nSTART=41\nSTOP=90\n\nBOOT_IMAGE=/boot/vmlinuz\n\nEXTRA_COMMANDS=\"status\"\nEXTRA_HELP=\"        status  Print crashkernel status\"\n\nverify_kdump() {\n\tlocal cfg=\"$1\"\n\tlocal enabled\n\tlocal path\n\tlocal save_vmcore\n\tlocal save_dmesg\n\n\tconfig_get_bool enabled \"$cfg\" enabled 1\n\tconfig_get_bool save_dmesg \"$cfg\" save_dmesg 1\n\tconfig_get_bool save_vmcore \"$cfg\" save_vmcore 0\n\n\t[ \"$enabled\" -gt 0 ] || return 2\n\n\t[ \"$save_dmesg\" -gt 0 ] || [ \"$save_vmcore\" -gt 0 ] || return 2\n\n\tconfig_get path \"$cfg\" path \"/\"\n\n\t[ -d \"$path\" ] || mkdir -p \"$path\" 2>/dev/null || return 1\n}\n\nrun_kdump() {\n\tlocal cfg=\"$1\"\n\tlocal enabled\n\tlocal path\n\tlocal save_vmcore\n\tlocal save_dmesg\n\n\tconfig_get_bool enabled \"$cfg\" enabled 1\n\t[ \"$enabled\" -gt 0 ] || return\n\n\tconfig_get_bool save_dmesg \"$cfg\" save_dmesg 1\n\tconfig_get_bool save_vmcore \"$cfg\" save_vmcore 0\n\tconfig_get path \"$cfg\" path \"/\"\n\n\ttimestamp=$(date \"+%Y%m%dT%H%M%S\")\n\n\tif [ \"$save_vmcore\" -eq 1 ]; then\n\t\techo -n \"Saving vmcore (this may take a while)...\"\n\t\t# would like 'sparse' but busybox doesn't support it\n\t\tdd if=/proc/vmcore of=\"$path/vmcore-$timestamp\" conv=fsync bs=1M\n\t\techo \" done\"\n\tfi\n\n\tif [ \"$save_dmesg\" -eq 1 ]; then\n\t\tvmcore-dmesg /proc/vmcore > \"$path/dmesg-$timestamp\"\n\tfi\n\n\tsync\n\treboot -f\n}\n\nfind_kernel() {\n\t. /lib/functions.sh\n\tlocal kernel\n\n\tkernel=\"$BOOT_IMAGE\"\n\tif [ -r \"$kernel\" ]; then\n\t\techo $kernel\n\t\treturn 0\n\tfi\n\n\tkernel=\"$(find_mtd_part kernel)\"\n\tif [ -r \"$kernel\" ]; then\n\t\techo $kernel\n\t\treturn 0\n\tfi\n\n\tfor voldir in /sys/class/ubi/ubi*_*; do\n\t\t[ ! -e \"$voldir\" ] && continue\n\t\tif [ \"$(cat \"${voldir}/name\")\" = \"kernel\" ]; then\n\t\t\tkernel=\"/dev/$(basename \"$voldir\")\"\n\t\t\techo $kernel\n\t\t\treturn 0\n\t\tfi\n\tdone\n\n\treturn 1\n}\n\nload_crashkernel() {\n\tlocal append_cmdline\n\tlocal kernel\n\n\tkernel=\"$(find_kernel)\"\n\t[ $? -gt 0 ] && return 1\n\n\tcase \"$(uname -m)\" in\n\t\ti?86|x86_64)\n\t\t\tgrep -q \"crashkernel=\" /proc/cmdline || return 1\n\t\t\tappend_cmdline=\"1 irqpoll reset_devices maxcpus=1\"\n\t\t\t;;\n\t\tarm*)\n\t\t\tappend_cmdline=\"1 maxcpus=1 reset_devices\"\n\t\t\t;;\n\tesac\n\tkexec -p \"$kernel\" --reuse-cmdline --append=\"$append_cmdline\"\n\treturn $?\n}\n\nstart() {\n\tlocal retval\n\n\tif [ ! -e /sys/kernel/kexec_crash_loaded ]; then\n\t\treturn 1\n\tfi\n\n\tif [ -e /proc/vmcore ]; then\n\t\tconfig_load kdump\n\t\tconfig_foreach run_kdump kdump\n\telse\n\t\tconfig_load kdump\n\t\tconfig_foreach verify_kdump kdump\n\t\tretval=$?\n\t\t[ $retval = 1 ] && return 1\n\t\t[ $retval = 0 ] && load_crashkernel\n\t\treturn $?\n\tfi\n}\n\nstop() {\n\t[ \"$(cat /sys/kernel/kexec_crash_loaded)\" = \"1\" ] || return\n\n\tif [ -e \"$BOOT_IMAGE\" ]; then\n\t\tkexec -p -u \"$BOOT_IMAGE\"\n\tfi\n}\n\nstatus() {\n\tlocal retval kernel\n\n\tif [ ! -e /sys/kernel/kexec_crash_loaded ]; then\n\t\techo \"crashdump not supported by kernel\"\n\t\treturn\n\tfi\n\n\tif [ $(cat /sys/kernel/kexec_crash_size) -eq 0 ]; then\n\t\techo \"memory for crashdump kernel not reserved!\"\n\t\techo \"check crashkernel= kernel cmdline parameter\"\n\t\techo \"(a reboot is required after installing kdump)\"\n\t\treturn\n\tfi\n\n\tkernel=\"$(find_kernel)\"\n\tif [ $? -gt 0 ]; then\n\t\techo \"cannot find kernel image\"\n\t\treturn\n\telse\n\t\techo \"using kernel image $kernel\"\n\tfi\n\n\techo -n \"kdump configuration is \"\n\tconfig_load kdump\n\tretval=$?\n\tif [ $retval = 0 ]; then\n\t\tif [ \"$(config_foreach echo kdump)\" ]; then\n\t\t\tconfig_foreach verify_kdump kdump\n\t\t\tretval=$?\n\t\telse\n\t\t\tretval=1\n\t\tfi\n\tfi\n\n\tif [ $retval = 0 ]; then\n\t\techo \"valid\"\n\telif [ $retval = 2 ]; then\n\t\techo \"disabled\"\n\telse\n\t\techo \"BROKEN\"\n\tfi\n\n\techo -n \"kexec crash kernel \"\n\tif [ \"$(cat /sys/kernel/kexec_crash_loaded)\" = \"0\" ]; then\n\t\techo -n \"not \"\n\tfi\n\techo \"loaded\"\n}\n"
  },
  {
    "path": "package/boot/kexec-tools/patches/001-arm-do-not-copy-magic-4-bytes-of-appended-DTB-in-zIm.patch",
    "content": "From 9817ec81968a5eec7863902833fb77680544eae4 Mon Sep 17 00:00:00 2001\nFrom: Alexander Egorenkov <egorenar-dev@posteo.net>\nDate: Mon, 12 Apr 2021 13:18:05 +0200\nSubject: [PATCH 1/1] arm: do not copy magic 4 bytes of appended DTB in zImage\n\nIf the passed zImage happens to have a DTB appended, then the magic 4 bytes\nof the DTB are copied together with the kernel image. This leads to\nfailed kexec boots because the decompressor finds the aforementioned\nDTB magic and falsely tries to replace the DTB passed in the register r2\nwith the non-existent appended one.\n\nSigned-off-by: Alexander Egorenkov <egorenar-dev@posteo.net>\nSigned-off-by: Simon Horman <horms@verge.net.au>\n---\n kexec/arch/arm/kexec-zImage-arm.c | 12 +++++++++++-\n 1 file changed, 11 insertions(+), 1 deletion(-)\n\n--- a/kexec/arch/arm/kexec-zImage-arm.c\n+++ b/kexec/arch/arm/kexec-zImage-arm.c\n@@ -382,6 +382,7 @@ int zImage_arm_load(int argc, char **arg\n \tunsigned int atag_offset = 0x1000; /* 4k offset from memory start */\n \tunsigned int extra_size = 0x8000; /* TEXT_OFFSET */\n \tconst struct zimage_tag *tag;\n+\tsize_t kernel_buf_size;\n \tsize_t kernel_mem_size;\n \tconst char *command_line;\n \tchar *modified_cmdline = NULL;\n@@ -538,6 +539,15 @@ int zImage_arm_load(int argc, char **arg\n \t}\n \n \t/*\n+\t * Save the length of the compressed kernel image w/o the appended DTB.\n+\t * This will be required later on when the kernel image contained\n+\t * in the zImage will be loaded into a kernel memory segment.\n+\t * And we want to load ONLY the compressed kernel image from the zImage\n+\t * and discard the appended DTB.\n+\t */\n+\tkernel_buf_size = len;\n+\n+\t/*\n \t * Always extend the zImage by four bytes to ensure that an appended\n \t * DTB image always sees an initialised value after _edata.\n \t */\n@@ -759,7 +769,7 @@ int zImage_arm_load(int argc, char **arg\n \t\tadd_segment(info, dtb_buf, dtb_length, dtb_offset, dtb_length);\n \t}\n \n-\tadd_segment(info, buf, len, kernel_base, kernel_mem_size);\n+\tadd_segment(info, buf, kernel_buf_size, kernel_base, kernel_mem_size);\n \n \tinfo->entry = (void*)kernel_base;\n \n"
  },
  {
    "path": "package/boot/kobs-ng/Makefile",
    "content": "#\n# Copyright (C) 2013-2014 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=kobs-ng\nPKG_VERSION:=5.4\nPKG_RELEASE:=1\n\nPKG_SOURCE:=imx-kobs-$(PKG_VERSION).tar.gz\nPKG_SOURCE_URL:=http://www.freescale.com/lgfiles/NMG/MAD/YOCTO/\nPKG_HASH:=85171b46068ac47c42fedb8104167bf9afd33dd9527ed127e1ca2eb29d7a86bf\nPKG_BUILD_DIR:=$(BUILD_DIR)/imx-kobs-$(PKG_VERSION)\n\nPKG_LICENSE:=GPLv2\nPKG_LICENSE_FILES:=COPYING\n\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine Package/kobs-ng\n  SECTION:=utils\n  CATEGORY:=Utilities\n  TITLE:=Application for writing bootstreams to NAND flash\n  DEPENDS:=@TARGET_imx\nendef\n\ndefine Package/kobs-ng/description\n The kobs-ng application writes a bootstream to NAND flash with the proper\n FCB/DBBT headers and replicated streams.\nendef\n\ndefine Build/Prepare\n\t$(call Build/Prepare/Default)\n\techo \"const char* git_sha = \\\"$(PKG_VERSION)\\\";\" > $(PKG_BUILD_DIR)/autoversion.h\nendef\n\ndefine Package/kobs-ng/install\n\t$(INSTALL_DIR) $(1)/usr/sbin\n\t$(INSTALL_BIN) $(PKG_BUILD_DIR)/src/kobs-ng $(1)/usr/sbin/\nendef\n\n$(eval $(call BuildPackage,kobs-ng))\n"
  },
  {
    "path": "package/boot/kobs-ng/patches/001-compile.patch",
    "content": "--- a/src/mtd.c\n+++ b/src/mtd.c\n@@ -28,6 +28,7 @@\n #include <unistd.h>\n #include <stdlib.h>\n #include <string.h>\n+#include <stddef.h>\n #include <fcntl.h>\n #include <ctype.h>\n #include <errno.h>\n--- a/src/mtd.h\n+++ b/src/mtd.h\n@@ -25,8 +25,11 @@\n #ifndef MTD_H\n #define MTD_H\n \n+#define _GNU_SOURCE\n #include <mtd/mtd-user.h>\n #include <endian.h>\n+#include <stdint.h>\n+#include <fcntl.h>\n \n #include \"BootControlBlocks.h\"\n #include \"rom_nand_hamming_code_ecc.h\"\n"
  },
  {
    "path": "package/boot/kobs-ng/patches/002-add-init-size-param.patch",
    "content": "Add --chip_0_size param to override the size of the mtd partition which is\nrequired if the SPL does not occupy the entire partition. For Gateworks\nVentana boards the 'uboot' partition contains both the SPL and uboot.\n--- a/src/main.c\n+++ b/src/main.c\n@@ -94,6 +94,7 @@ void usage(void)\n \t\"  [KOBS] boot structures config options\\n\"\n \t\"    --chip_0_device_path=<path> .......... Device of boot (default /dev/mtd0)\\n\"\n \t\"    --chip_1_device_path=<path> .......... The second chip in case of multichip NAND\\n\"\n+\t\"    --chip_0_size=<size> ................. Override size of chip_0 device\\n\"\n \t\"    --search_exponent=<value> ............ NCB field (default 2)\\n\"\n \t\"    --data_setup_time=<value> ............ NCB field (default 80)\\n\"\n \t\"    --data_hold_time=<value> ............. NCB field (default 60)\\n\"\n--- a/src/mtd.c\n+++ b/src/mtd.c\n@@ -876,6 +876,11 @@ struct mtd_data *mtd_open(const struct m\n \t\t\tgoto out;\n \t\t}\n \n+\t\t/* override MTD size */\n+\t\tif (md->cfg.chip_0_size) {\n+\t\t\tmiu->size = md->cfg.chip_0_size;\n+\t\t}\n+\n \t\t/* verify it's a nand */\n \t\tif (miu->type != MTD_NANDFLASH\n \t\t\t&& miu->type != MTD_MLCNANDFLASH) {\n@@ -3385,7 +3390,7 @@ static const struct {\n } mtd_int_args[] = {\n \tARG_IGNORE(chip_count),\n \tARG_IGNORE(chip_0_offset),\n-\tARG_IGNORE(chip_0_size),\n+\tARG(chip_0_size),\n \tARG_IGNORE(chip_1_offset),\n \tARG_IGNORE(chip_1_size),\n \tARG(search_exponent),\n@@ -3578,7 +3583,7 @@ void mtd_cfg_dump(struct mtd_config *cfg\n //\tPd(chip_count);\n \tPs(chip_0_device_path);\n //\tPd(chip_0_offset);\n-//\tPd(chip_0_size);\n+\tPd(chip_0_size);\n \tPs(chip_1_device_path);\n //\tPd(chip_1_offset);\n //\tPd(chip_1_size);\n"
  },
  {
    "path": "package/boot/kobs-ng/patches/003-raw-mode.patch",
    "content": "The downstream Freescale vendor kernel has a patch that allows determining\nif raw NAND flash mode is provided via a debugfs file. This is not present\nin upstream kernels, but the raw access support was added in the 3.19\nkernel, so we will check the kernel version if we can't find the file.\n--- a/src/mtd.c\n+++ b/src/mtd.c\n@@ -34,6 +34,7 @@\n #include <errno.h>\n #include <sys/types.h>\n #include <sys/ioctl.h>\n+#include <sys/utsname.h>\n \n #include \"mtd.h\"\n #include \"rand.h\"\n@@ -808,15 +809,27 @@ struct mtd_data *mtd_open(const struct m\n \tmd->cfg = *cfg;\n \n \t/* check if use new raw access mode */\n+\t/* by looking for debugfs from fsl patch */\n+\tmd->raw_mode_flag = 0;\n \tfp = fopen(\"/sys/kernel/debug/gpmi-nand/raw_mode\", \"r\");\n \tif (!fp) {\n-\t\tmd->raw_mode_flag = 0;\n-\t\tvp(md, \"mtd: use legacy raw access mode\\n\");\n+\t\t/* fallback to kernel version: raw access added in 3.19 */\n+\t\tstruct utsname uts;\n+\t\tif (!uname(&uts)) {\n+\t\t\tint major = 0, minor = 0;\n+\t\t\tsscanf(uts.release, \"%d.%d\", &major, &minor);\n+\t\t\tvp(md, \"mtd: Linux %d.%d\\n\", major, minor);\n+\t\t\tif ((major << 8 | minor) > (3 << 8 | 18))\n+\t\t\t\tmd->raw_mode_flag = 1;\n+\t\t}\n \t} else {\n \t\tfclose(fp);\n \t\tmd->raw_mode_flag = 1;\n-\t\tvp(md, \"mtd: use new bch layout raw access mode\\n\");\n \t}\n+\tif (md->raw_mode_flag)\n+\t\tvp(md, \"mtd: use new bch layout raw access mode\\n\");\n+\telse\n+\t\tvp(md, \"mtd: use legacy raw access mode\\n\");\n \n \tif (plat_config_data->m_u32UseMultiBootArea) {\n \n"
  },
  {
    "path": "package/boot/kobs-ng/patches/004-fix-cal_nfc_geometry.patch",
    "content": "The Freescale downstream vendor kernel has a patch that exports the bch\nflash geometry via a debugfs file. This is not available in mainline linux\nkernels so the fallback method calculates the geometry based on known info\nfrom the mtd partition. A bug exists in this funcion where it fails to\nassume that block0 ECC is the same as the other blocks by default.\n--- a/src/mtd.c\n+++ b/src/mtd.c\n@@ -610,7 +610,7 @@ static int cal_nfc_geometry(struct mtd_d\n \t/* The two are fixed, please change them when the driver changes. */\n \tgeo->metadata_size_in_bytes = 10;\n \tgeo->gf_len = 13;\n-\tgeo->ecc_chunkn_size_in_bytes = 512;\n+\tgeo->ecc_chunkn_size_in_bytes = geo->ecc_chunk0_size_in_bytes = 512;\n \n \tif (mtd->oobsize > geo->ecc_chunkn_size_in_bytes) {\n \t\tgeo->gf_len = 14;\n@@ -700,8 +700,9 @@ int parse_nfc_geometry(struct mtd_data *\n \tunsigned int       value;\n \n \tif (!plat_config_data->m_u32UseNfcGeo) {\n+\t\t/* fsl kernel patch provides bch_geometry via debugfs */\n \t\tif (!(node = fopen(dbg_geometry_node_path, \"r\"))) {\n-\t\t\tfprintf(stderr, \"Cannot open BCH geometry node: \\\"%s\\\"\",\n+\t\t\tfprintf(stderr, \"Cannot open BCH geometry node: \\\"%s\\\"\\n\",\n \t\t\t\tdbg_geometry_node_path);\n \t\t\treturn cal_nfc_geometry(md);\n \t\t}\n"
  },
  {
    "path": "package/boot/mt7623n-preloader/Makefile",
    "content": "#\n# Copyright © 2020 David Woodhouse <dwmw2@infradead.org>\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\ninclude $(TOPDIR)/rules.mk\ninclude $(INCLUDE_DIR)/kernel.mk\n\nPKG_NAME:=mt7623n-preloader\nPKG_VERSION:=2020-03-11\nPKG_RELEASE:=b27114e184449a33b5d875fda14198f5e6fee2bb\n\nPKG_MAINTAINER:=David Woodhouse <dwmw2@infradead.org>\n\nPKG_BUILD_DIR:=$(KERNEL_BUILD_DIR)/$(PKG_NAME)/$(PKG_NAME)-$(PKG_RELEASE)\n\nPKG_FLAGS:=nonshared\n\ninclude $(INCLUDE_DIR)/package.mk\n\nBPI_PRELOADER_URL:=@GITHUB/BPI-SINOVOIP/BPI-files/$(PKG_RELEASE)/SD/100MB/\nBPI_PRELOADER_PREFIX:=bpi-preloader-$(PKG_RELEASE)\n\ndefine Download/BPI-R2-preloader-2k.img.gz\n  FILE:=$(BPI_PRELOADER_PREFIX)-BPI-R2-preloader-DDR1600-20191024-2k.img.gz\n  URL:=$(BPI_PRELOADER_URL)\n  URL_FILE:=BPI-R2-preloader-DDR1600-20191024-2k.img.gz\n  HASH:=c731cc166c912c84846e2ed5faf727504e4dec1463754baa6328e9908c84a373\nendef\n$(eval $(call Download,BPI-R2-preloader-2k.img.gz))\n\ndefine Download/BPI-R64-preloader-2k.img.gz\n  FILE:=$(BPI_PRELOADER_PREFIX)-BPI-R64-preloader-2k.img.gz\n  URL:=$(BPI_PRELOADER_URL)\n  URL_FILE:=BPI-R64-preloader-2k.img.gz\n  HASH:=1a4b55da1717190aa4e790ce93850605e9b15aae4c3248bcf8734aac020ab0e4\nendef\n$(eval $(call Download,BPI-R64-preloader-2k.img.gz))\n\n\ndefine Package/mt7623n-preloader\n  SECTION:=boot\n  CATEGORY:=Boot Loaders\n  DEPENDS:=@TARGET_mediatek_mt7623\n  TITLE:=mt7623n-preloader\n  DEFAULT:=y if TARGET_mediatek\nendef\n\ndefine Package/mt7623n-preloader/description\n  Preloader image for mt7623n based boards like Banana Pi R2.\nendef\n\ndefine Build/Prepare\n\trm -rf $(PKG_BUILD_DIR)\n\tmkdir -p $(PKG_BUILD_DIR)\n\tcp $(DL_DIR)/$(BPI_PRELOADER_PREFIX)-BPI-R2-preloader-DDR1600-20191024-2k.img.gz $(PKG_BUILD_DIR)/mt7623n_bpir2-preloader.bin.gz\nendef\n\ndefine Build/Compile\n\ttrue\nendef\n\ndefine Build/InstallDev\n\tmkdir -p $(STAGING_DIR_IMAGE)\n\tgunzip -c $(PKG_BUILD_DIR)/mt7623n_bpir2-preloader.bin.gz > $(STAGING_DIR_IMAGE)/mt7623n_bpir2-preloader.bin\nendef\n\n$(eval $(call BuildPackage,mt7623n-preloader))\n"
  },
  {
    "path": "package/boot/tfa-layerscape/Makefile",
    "content": "#\n# Copyright 2019 NXP\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=tfa-layerscape\nPKG_VERSION:=21.08\nPKG_RELEASE:=$(AUTORELEASE)\n\nPKG_SOURCE_PROTO:=git\nPKG_SOURCE_URL:=https://source.codeaurora.org/external/qoriq/qoriq-components/atf\nPKG_SOURCE_VERSION:=LSDK-21.08\nPKG_MIRROR_HASH:=500da1f5743255b2c301b89fba4df31d05a7dfbc731fbf137a88caf86f5568d0\nPKG_BUILD_DEPENDS:=tfa-layerscape/host\n\ninclude $(INCLUDE_DIR)/host-build.mk\ninclude $(INCLUDE_DIR)/package.mk\n\nHOST_CFLAGS += -Wall -Werror -pedantic -std=c99\ndefine Host/Compile\n\t$(MAKE) -C \\\n\t\t$(HOST_BUILD_DIR)/tools/fiptool \\\n\t\tCFLAGS=\"$(HOST_CFLAGS)\" \\\n\t\tLDFLAGS=\"$(HOST_LDFLAGS)\" \\\n\t\tHOSTCCFLAGS=\"$(HOST_CFLAGS)\"\n\t$(MAKE) -C \\\n\t\t$(HOST_BUILD_DIR)/tools/nxp \\\n\t\tCFLAGS=\"$(HOST_CFLAGS)\"\nendef\n\ndefine Host/Install\n\t$(INSTALL_BIN) $(HOST_BUILD_DIR)/tools/fiptool/fiptool $(STAGING_DIR_HOST)/bin/fiptool-layerscape\n\t$(INSTALL_BIN) $(HOST_BUILD_DIR)/tools/nxp/create_pbl $(STAGING_DIR_HOST)/bin/tfa-create-pbl\n\t$(INSTALL_BIN) $(HOST_BUILD_DIR)/tools/nxp/byte_swap $(STAGING_DIR_HOST)/bin/tfa-byte-swap\nendef\n\ndefine Package/tfa-generic\n  SECTION:=boot\n  CATEGORY:=Boot Loaders\n  DEPENDS:=@TARGET_layerscape_armv8_64b +layerscape-rcw +u-boot-fsl_$(subst tfa-,,$(1))\n  VARIANT:=$(subst tfa-,,$(1))\nendef\n\ndefine Package/tfa-ls1012a-frdm\n  $(Package/tfa-generic)\n  TITLE:=NXP LS1012AFRDM Trusted Firmware\n  PLAT:=ls1012afrdm\n  BOOT_MODE:=qspi\nendef\n\ndefine Package/tfa-ls1012a-rdb\n  $(Package/tfa-generic)\n  TITLE:=NXP LS1012ARDB Trusted Firmware\n  PLAT:=ls1012ardb\n  BOOT_MODE:=qspi\nendef\n\ndefine Package/tfa-ls1012a-frwy-sdboot\n  $(Package/tfa-generic)\n  TITLE:=NXP LS1012AFRWY Trusted Firmware\n  PLAT:=ls1012afrwy\n  BOOT_MODE:=qspi\nendef\n\ndefine Package/tfa-ls1043a-rdb\n  $(Package/tfa-generic)\n  TITLE:=NXP LS1043ARDB Trusted Firmware\n  PLAT:=ls1043ardb\n  BOOT_MODE:=nor\nendef\n\ndefine Package/tfa-ls1043a-rdb-sdboot\n  $(Package/tfa-generic)\n  TITLE:=NXP LS1043ARDB SD Boot Trusted Firmware\n  PLAT:=ls1043ardb\n  BOOT_MODE:=sd\nendef\n\ndefine Package/tfa-ls1046a-frwy\n  $(Package/tfa-generic)\n  TITLE:=NXP LS1046AFRWY Trusted Firmware\n  PLAT:=ls1046afrwy\n  BOOT_MODE:=qspi\nendef\n\ndefine Package/tfa-ls1046a-frwy-sdboot\n  $(Package/tfa-generic)\n  TITLE:=NXP LS1046AFRWY SD Boot Trusted Firmware\n  PLAT:=ls1046afrwy\n  BOOT_MODE:=sd\nendef\n\ndefine Package/tfa-ls1046a-rdb\n  $(Package/tfa-generic)\n  TITLE:=NXP LS1046ARDB Trusted Firmware\n  PLAT:=ls1046ardb\n  BOOT_MODE:=qspi\nendef\n\ndefine Package/tfa-ls1046a-rdb-sdboot\n  $(Package/tfa-generic)\n  TITLE:=NXP LS1046ARDB SD Boot Trusted Firmware\n  PLAT:=ls1046ardb\n  BOOT_MODE:=sd\nendef\n\ndefine Package/tfa-ls1088a-rdb\n  $(Package/tfa-generic)\n  TITLE:=NXP LS1088ARDB Trusted Firmware\n  PLAT:=ls1088ardb\n  BOOT_MODE:=qspi\nendef\n\ndefine Package/tfa-ls1088a-rdb-sdboot\n  $(Package/tfa-generic)\n  TITLE:=NXP LS1088ARDB SD Boot Trusted Firmware\n  PLAT:=ls1088ardb\n  BOOT_MODE:=sd\nendef\n\ndefine Package/tfa-ls2088a-rdb\n  $(Package/tfa-generic)\n  TITLE:=NXP LS2088ARDB Trusted Firmware\n  PLAT:=ls2088ardb\n  BOOT_MODE:=nor\nendef\n\ndefine Package/tfa-lx2160a-rdb\n  $(Package/tfa-generic)\n  TITLE:=NXP LX2160ARDB Trusted Firmware\n  PLAT:=lx2160ardb\n  BOOT_MODE:=flexspi_nor\nendef\n\ndefine Package/tfa-lx2160a-rdb-sdboot\n  $(Package/tfa-generic)\n  TITLE:=NXP LX2160ARDB SD Boot Trusted Firmware\n  PLAT:=lx2160ardb\n  BOOT_MODE:=sd\nendef\n\ndefine Build/InstallDev\n\t$(INSTALL_DIR) $(STAGING_DIR_IMAGE)\n\t$(CP) $(PKG_BUILD_DIR)/build/$(PLAT)/release/bl2_$(BOOT_MODE).pbl \\\n\t\t$(STAGING_DIR_IMAGE)/fsl_$(BUILD_VARIANT)-bl2.pbl\n\t$(CP) $(PKG_BUILD_DIR)/build/$(PLAT)/release/fip.bin \\\n\t\t$(STAGING_DIR_IMAGE)/fsl_$(BUILD_VARIANT)-fip.bin\nendef\n\ndefine Build/Compile\n\t$(eval $(Package/tfa-$(BUILD_VARIANT))) \\\n\t$(MAKE) -C $(PKG_BUILD_DIR) CROSS_COMPILE=$(TARGET_CROSS) \\\n\t\tfip pbl PLAT=$(PLAT) BOOT_MODE=$(BOOT_MODE) \\\n\t\tRCW=$(STAGING_DIR_IMAGE)/fsl_$(BUILD_VARIANT)-rcw.bin \\\n\t\tBL33=$(STAGING_DIR_IMAGE)/fsl_$(BUILD_VARIANT)-uboot.bin \\\n\t\tFIPTOOL=$(STAGING_DIR_HOST)/bin/fiptool-layerscape \\\n\t\tCREATE_PBL=$(STAGING_DIR_HOST)/bin/tfa-create-pbl \\\n\t\tBYTE_SWAP=$(STAGING_DIR_HOST)/bin/tfa-byte-swap\nendef\n\nTFAS := \\\n  ls1012a-frdm \\\n  ls1012a-rdb \\\n  ls1012a-frwy-sdboot \\\n  ls1043a-rdb \\\n  ls1043a-rdb-sdboot \\\n  ls1046a-frwy \\\n  ls1046a-frwy-sdboot \\\n  ls1046a-rdb \\\n  ls1046a-rdb-sdboot \\\n  ls1088a-rdb \\\n  ls1088a-rdb-sdboot \\\n  ls2088a-rdb \\\n  lx2160a-rdb \\\n  lx2160a-rdb-sdboot\n\n$(eval $(call HostBuild))\n$(foreach tfa,$(TFAS), \\\n  $(eval $(call BuildPackage,tfa-$(tfa))) \\\n)\n"
  },
  {
    "path": "package/boot/tfa-layerscape/patches/001-fiptool-hostbuild-fixes.patch",
    "content": "--- a/Makefile\n+++ b/Makefile\n@@ -801,10 +801,6 @@ CRTTOOL\t\t\t?=\t${CRTTOOLPATH}/cert_create$\n ENCTOOLPATH\t\t?=\ttools/encrypt_fw\n ENCTOOL\t\t\t?=\t${ENCTOOLPATH}/encrypt_fw${BIN_EXT}\n \n-# Variables for use with Firmware Image Package\n-FIPTOOLPATH\t\t?=\ttools/fiptool\n-FIPTOOL\t\t\t?=\t${FIPTOOLPATH}/fiptool${BIN_EXT}\n-\n # Variables for use with sptool\n SPTOOLPATH\t\t?=\ttools/sptool\n SPTOOL\t\t\t?=\t${SPTOOLPATH}/sptool${BIN_EXT}\n@@ -1160,13 +1156,6 @@ endif\n clean:\n \t@echo \"  CLEAN\"\n \t$(call SHELL_REMOVE_DIR,${BUILD_PLAT})\n-ifdef UNIX_MK\n-\t${Q}${MAKE} --no-print-directory -C ${FIPTOOLPATH} clean\n-else\n-# Clear the MAKEFLAGS as we do not want\n-# to pass the gnumake flags to nmake.\n-\t${Q}set MAKEFLAGS= && ${MSVC_NMAKE} /nologo /f ${FIPTOOLPATH}/Makefile.msvc FIPTOOLPATH=$(subst /,\\,$(FIPTOOLPATH)) FIPTOOL=$(subst /,\\,$(FIPTOOL)) clean\n-endif\n \t${Q}${MAKE} PLAT=${PLAT} --no-print-directory -C ${CRTTOOLPATH} clean\n \t${Q}${MAKE} PLAT=${PLAT} --no-print-directory -C ${ENCTOOLPATH} clean\n \t${Q}${MAKE} --no-print-directory -C ${ROMLIBPATH} clean\n@@ -1175,13 +1164,6 @@ realclean distclean:\n \t@echo \"  REALCLEAN\"\n \t$(call SHELL_REMOVE_DIR,${BUILD_BASE})\n \t$(call SHELL_DELETE_ALL, ${CURDIR}/cscope.*)\n-ifdef UNIX_MK\n-\t${Q}${MAKE} --no-print-directory -C ${FIPTOOLPATH} clean\n-else\n-# Clear the MAKEFLAGS as we do not want\n-# to pass the gnumake flags to nmake.\n-\t${Q}set MAKEFLAGS= && ${MSVC_NMAKE} /nologo /f ${FIPTOOLPATH}/Makefile.msvc FIPTOOLPATH=$(subst /,\\,$(FIPTOOLPATH)) FIPTOOL=$(subst /,\\,$(FIPTOOL)) realclean\n-endif\n \t${Q}${MAKE} --no-print-directory -C ${SPTOOLPATH} clean\n \t${Q}${MAKE} PLAT=${PLAT} --no-print-directory -C ${CRTTOOLPATH} clean\n \t${Q}${MAKE} PLAT=${PLAT} --no-print-directory -C ${ENCTOOLPATH} realclean\n@@ -1238,7 +1220,7 @@ certificates: ${CRT_DEPS} ${CRTTOOL}\n \t@${ECHO_BLANK_LINE}\n endif\n \n-${BUILD_PLAT}/${FIP_NAME}: ${FIP_DEPS} ${FIPTOOL}\n+${BUILD_PLAT}/${FIP_NAME}: ${FIP_DEPS}\n \t${Q}${FIPTOOL} create ${FIP_ARGS} $@\n \t${Q}${FIPTOOL} info $@\n \t@${ECHO_BLANK_LINE}\n@@ -1254,7 +1236,7 @@ fwu_certificates: ${FWU_CRT_DEPS} ${CRTT\n \t@${ECHO_BLANK_LINE}\n endif\n \n-${BUILD_PLAT}/${FWU_FIP_NAME}: ${FWU_FIP_DEPS} ${FIPTOOL}\n+${BUILD_PLAT}/${FWU_FIP_NAME}: ${FWU_FIP_DEPS}\n \t${Q}${FIPTOOL} create ${FWU_FIP_ARGS} $@\n \t${Q}${FIPTOOL} info $@\n \t@${ECHO_BLANK_LINE}\n@@ -1279,24 +1261,10 @@ ${BUILD_PLAT}/${DDR_FIP_NAME}: ${DDR_FIP\n \t@echo \"Built $@ successfully\"\n \t@${ECHO_BLANK_LINE}\n \n-fiptool: ${FIPTOOL}\n fip: ${BUILD_PLAT}/${FIP_NAME}\n fwu_fip: ${BUILD_PLAT}/${FWU_FIP_NAME}\n fip_ddr: ${BUILD_PLAT}/${DDR_FIP_NAME}\n \n-.PHONY: ${FIPTOOL}\n-${FIPTOOL}:\n-\t@${ECHO_BLANK_LINE}\n-\t@echo \"Building $@\"\n-ifdef UNIX_MK\n-\t${Q}${MAKE} CPPFLAGS=\"-DVERSION='\\\"${VERSION_STRING}\\\"'\" FIPTOOL=${FIPTOOL} --no-print-directory -C ${FIPTOOLPATH}\n-else\n-# Clear the MAKEFLAGS as we do not want\n-# to pass the gnumake flags to nmake.\n-\t${Q}set MAKEFLAGS= && ${MSVC_NMAKE} /nologo /f ${FIPTOOLPATH}/Makefile.msvc FIPTOOLPATH=$(subst /,\\,$(FIPTOOLPATH)) FIPTOOL=$(subst /,\\,$(FIPTOOL))\n-endif\n-\t@${ECHO_BLANK_LINE}\n-\n sptool: ${SPTOOL}\n .PHONY: ${SPTOOL}\n ${SPTOOL}:\n--- a/tools/fiptool/Makefile\n+++ b/tools/fiptool/Makefile\n@@ -38,7 +38,7 @@ all: ${PROJECT}\n \n ${PROJECT}: ${OBJECTS} Makefile\n \t@echo \"  HOSTLD  $@\"\n-\t${Q}${HOSTCC} ${OBJECTS} -o $@ ${LDLIBS}\n+\t${Q}${HOSTCC} ${OBJECTS} -o $@ ${LDLIBS} $(LDFLAGS)\n \t@${ECHO_BLANK_LINE}\n \t@echo \"Built $@ successfully\"\n \t@${ECHO_BLANK_LINE}\n"
  },
  {
    "path": "package/boot/tfa-layerscape/patches/003-plat-nxp-tools-fix-create_pbl-and-byte_swap-host-bui.patch",
    "content": "From 8a458876013991fe2f288bbe4694264b16c3b9e9 Mon Sep 17 00:00:00 2001\nFrom: Biwen Li <biwen.li@nxp.com>\nDate: Fri, 26 Jul 2019 15:44:10 +0800\nSubject: [PATCH 3/3] tools/nxp: fix create_pbl and byte_swap host build\n\nNot compile create_pbl and byte_swap in the process of cross compilation\n\nSigned-off-by: Biwen Li <biwen.li@nxp.com>\n---\n tools/nxp/pbl_ch2.mk | 3 ---\n tools/nxp/pbl_ch3.mk | 5 -----\n 2 files changed, 8 deletions(-)\n\n--- a/tools/nxp/pbl_ch2.mk\n+++ b/tools/nxp/pbl_ch2.mk\n@@ -19,8 +19,6 @@ ifeq ($(RCW),\"\")\n else\n \t# Generate header for bl2.bin\n \t$(Q)$(CST_DIR)/create_hdr_isbc --in ${BUILD_PLAT}/bl2.bin --out ${BUILD_PLAT}/hdr_bl2 ${BL2_INPUT_FILE}\n-\t# Compile create_pbl tool\n-\t${Q}${MAKE} CPPFLAGS=\"-DVERSION='\\\"${VERSION_STRING}\\\"'\" --no-print-directory -C ${PLAT_TOOL_PATH};\\\n \t# Add bl2.bin to RCW\n \t${CREATE_PBL} -r ${RCW} -i ${BUILD_PLAT}/bl2.bin -b ${BOOT_MODE} -c ${SOC_NUM} -d ${BL2_BASE} -e ${BL2_BASE}\\\n \t\t\t-o ${BUILD_PLAT}/bl2_${BOOT_MODE}.pbl ;\\\n@@ -42,7 +40,6 @@ ifeq ($(RCW),\"\")\n \t${Q}echo \"Platform ${PLAT} requires rcw file. Please set RCW to point to the right RCW file for boot mode ${BOOT_MODE}\"\n else\n \t# -a option appends the image for Chassis 3 devices in case of non secure boot\n-\t${Q}${MAKE} CPPFLAGS=\"-DVERSION='\\\"${VERSION_STRING}\\\"'\" --no-print-directory -C ${PLAT_TOOL_PATH};\n \t${CREATE_PBL} -r ${RCW} -i ${BUILD_PLAT}/bl2.bin -b ${BOOT_MODE} -c ${SOC_NUM} -d ${BL2_BASE} -e ${BL2_BASE} \\\n \t-o ${BUILD_PLAT}/bl2_${BOOT_MODE}.pbl ;\n # Swapping of RCW is required for QSPi Chassis 2 devices\n--- a/tools/nxp/pbl_ch3.mk\n+++ b/tools/nxp/pbl_ch3.mk\n@@ -26,9 +26,6 @@ else\n \t# Generate header for bl2.bin\n \t$(Q)$(CST_DIR)/create_hdr_isbc --in ${BUILD_PLAT}/bl2.bin --out ${BUILD_PLAT}/hdr_bl2 ${BL2_INPUT_FILE}\n \n-\t# Compile create_pbl tool\n-\t${Q}${MAKE} CPPFLAGS=\"-DVERSION='\\\"${VERSION_STRING}\\\"'\" --no-print-directory -C ${PLAT_TOOL_PATH};\\\n-\n \t# Add Block Copy command for bl2.bin to RCW\n \t${CREATE_PBL} -r ${RCW} -i ${BUILD_PLAT}/bl2.bin -b ${BOOT_MODE} -c ${SOC_NUM} -d ${BL2_BASE} -e ${BL2_BASE}\\\n \t\t\t-o ${BUILD_PLAT}/bl2_${BOOT_MODE}.pbl -f ${BL2_SRC_OFFSET};\\\n@@ -56,8 +53,6 @@ else  #SECURE_BOOT\n ifeq ($(RCW),\"\")\n \t${Q}echo \"Platform ${PLAT} requires rcw file. Please set RCW to point to the right RCW file for boot mode ${BOOT_MODE}\"\n else\n-\t${Q}${MAKE} CPPFLAGS=\"-DVERSION='\\\"${VERSION_STRING}\\\"'\" --no-print-directory -C ${PLAT_TOOL_PATH};\n-\n \t# Add Block Copy command and populate boot loc ptrfor bl2.bin to RCW\n \t${CREATE_PBL} -r ${RCW} -i ${BUILD_PLAT}/bl2.bin -b ${BOOT_MODE} -c ${SOC_NUM} -d ${BL2_BASE} -e ${BL2_BASE} \\\n \t-o ${BUILD_PLAT}/bl2_${BOOT_MODE}.pbl -f ${BL2_SRC_OFFSET};\n"
  },
  {
    "path": "package/boot/uboot-at91/Makefile",
    "content": "#\n# Copyright (C) 2016 Ben Whitten <ben.whitten@gmail.com>\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_VERSION:=linux4sam-2021.10\nPKG_RELEASE:=$(AUTORELEASE)\n\nPKG_SOURCE_PROTO:=git\nPKG_SOURCE_URL:=https://github.com/linux4sam/u-boot-at91.git\nPKG_MIRROR_HASH:=f1190062f2012b182b45b78263a4cce4ada9b7b8d6f5a66d68fa51437105fc8c\nPKG_SOURCE_VERSION:=39854ce82232cdc05c20158d0439bdbc40991e4a\n\ninclude $(INCLUDE_DIR)/u-boot.mk\ninclude $(INCLUDE_DIR)/package.mk\ninclude $(INCLUDE_DIR)/kernel.mk\n\ndefine U-Boot/Default\n  BUILD_TARGET:=at91\n  HIDDEN:=1\n  UBOOT_IMAGE:=u-boot.bin\nendef\n\ndefine U-Boot/at91sam9m10g45ek_nandflash\n  NAME:=AT91SAM9M10G45-EK board (NandFlash)\n  BUILD_SUBTARGET:=sam9x\n  BUILD_DEVICES:=atmel_at91sam9m10g45ek\nendef\n\ndefine U-Boot/at91sam9x5ek_nandflash\n  NAME:=AT91SAM9X5-EK board (NandFlash)\n  BUILD_SUBTARGET:=sam9x\n  BUILD_DEVICES:=atmel_at91sam9g15ek atmel_at91sam9g25ek \\\n                 atmel_at91sam9g35ek atmel_at91sam9x25ek \\\n                 atmel_at91sam9x35ek\nendef\n\ndefine U-Boot/at91sam9x5ek_mmc\n  NAME:=AT91SAM9X5-EK board (SDcard)\n  BUILD_SUBTARGET:=sam9x\n  BUILD_DEVICES:=atmel_at91sam9g15ek atmel_at91sam9g25ek \\\n                 atmel_at91sam9g35ek atmel_at91sam9x25ek \\\n                 atmel_at91sam9x35ek\nendef\n\ndefine U-Boot/sam9x60ek_nandflash\n  NAME:=SAM9X60-EK board (NandFlash)\n  BUILD_SUBTARGET:=sam9x\n  BUILD_DEVICES:=microchip_sam9x60ek\nendef\n\ndefine U-Boot/sam9x60ek_mmc\n  NAME:=SAM9X60-EK board (SDcard)\n  BUILD_SUBTARGET:=sam9x\n  BUILD_DEVICES:=microchip_sam9x60ek\nendef\n\ndefine U-Boot/sama5d3_xplained_nandflash\n  NAME:=SAMA5D3 Xplained board (NandFlash)\n  BUILD_SUBTARGET:=sama5\n  BUILD_DEVICES:=microchip_sama5d3-xplained\nendef\n\ndefine U-Boot/sama5d3_xplained_mmc\n  NAME:=SAMA5D3 Xplained board (SDcard)\n  BUILD_SUBTARGET:=sama5\n  BUILD_DEVICES:=microchip_sama5d3-xplained\nendef\n\ndefine U-Boot/sama5d2_icp_mmc\n  NAME:=SAMA5D2 ICP board (SDCard)\n  BUILD_SUBTARGET:=sama5\n  BUILD_DEVICES:=microchip_sama5d2-icp\nendef\n\ndefine U-Boot/sama5d2_xplained_spiflash\n  NAME:=SAMA5D2 Xplained board (SPI Flash)\n  BUILD_SUBTARGET:=sama5\n  BUILD_DEVICES:=microchip_sama5d2-xplained\nendef\n\ndefine U-Boot/sama5d2_xplained_mmc\n  NAME:=SAMA5D2 Xplained board (SDcard/EMMC)\n  BUILD_SUBTARGET:=sama5\n  BUILD_DEVICES:=microchip_sama5d2-xplained\nendef\n\ndefine U-Boot/sama5d4_xplained_spiflash\n  NAME:=SAMA5D4 Xplained board (SPI Flash)\n  BUILD_SUBTARGET:=sama5\n  BUILD_DEVICES:=microchip_sama5d4-xplained\nendef\n\ndefine U-Boot/sama5d4_xplained_mmc\n  NAME:=SAMA5D4 Xplained board (SDcard)\n  BUILD_SUBTARGET:=sama5\n  BUILD_DEVICES:=microchip_sama5d4-xplained\nendef\n\ndefine U-Boot/sama5d4_xplained_nandflash\n  NAME:=SAMA5D4 Xplained board (NandFlash)\n  BUILD_SUBTARGET:=sama5\n  BUILD_DEVICES:=microchip_sama5d3-xplained\nendef\n\ndefine U-Boot/sama5d27_som1_ek_mmc1\n  NAME:=SAMA5D27 SOM1 Ek (SDCard1)\n  BUILD_SUBTARGET:=sama5\n  BUILD_DEVICES:=microchip_sama5d27-som1-ek\nendef\n\ndefine U-Boot/sama5d27_som1_ek_qspiflash\n  NAME:=SAMA5D27 SOM1 Ek (QSPI Flash)\n  BUILD_SUBTARGET:=sama5\n  BUILD_DEVICES:=microchip_sama5d27-som1-ek\nendef\n\ndefine U-Boot/sama5d27_wlsom1_ek_mmc\n  NAME:=SAMA5D27 WLSOM1 Ek (SDCard)\n  BUILD_SUBTARGET:=sama5\n  BUILD_DEVICES:=microchip_sama5d27-wlsom1-ek\nendef\n\ndefine U-Boot/sama5d27_wlsom1_ek_qspiflash\n  NAME:=SAMA5D27 WLSOM1 Ek (QSPI Flash)\n  BUILD_SUBTARGET:=sama5\n  BUILD_DEVICES:=microchip_sama5d27-wlsom1-ek\nendef\n\ndefine U-Boot/sama5d2_ptc_ek_nandflash\n  NAME:=SAMA5D2 PTC Ek (Nand Flash)\n  BUILD_SUBTARGET:=sama5\n  BUILD_DEVICES:=microchip_sama5d2-ptc-ek\nendef\n\ndefine U-Boot/sama5d2_ptc_ek_mmc\n  NAME:=SAMA5D2 PTC Ek (SDCard)\n  BUILD_SUBTARGET:=sama5\n  BUILD_DEVICES:=microchip_sama5d2-ptc-ek\nendef\n\ndefine U-Boot/sama7g5ek_mmc1\n  NAME:=SAMA7G5-EK (SDCard)\n  BUILD_SUBTARGET:=sama7\n  BUILD_DEVICES:=microchip_sama7g5-ek\nendef\n\nUBOOT_TARGETS := \\\n\tat91sam9m10g45ek_nandflash \\\n\tat91sam9x5ek_nandflash \\\n\tat91sam9x5ek_mmc \\\n\tsam9x60ek_nandflash \\\n\tsam9x60ek_mmc \\\n\tsama5d3_xplained_nandflash \\\n\tsama5d3_xplained_mmc \\\n\tsama5d2_icp_mmc \\\n\tsama5d2_xplained_mmc \\\n\tsama5d2_xplained_spiflash \\\n\tsama5d4_xplained_mmc \\\n\tsama5d4_xplained_spiflash \\\n\tsama5d4_xplained_nandflash\\\n\tsama5d27_som1_ek_mmc1 \\\n\tsama5d27_som1_ek_qspiflash \\\n\tsama5d27_wlsom1_ek_mmc \\\n\tsama5d27_wlsom1_ek_qspiflash \\\n\tsama5d2_ptc_ek_nandflash \\\n\tsama5d2_ptc_ek_mmc \\\n\tsama7g5ek_mmc1\n\ndefine Build/Compile\n\t+$(MAKE) $(PKG_JOBS) -C $(PKG_BUILD_DIR) \\\n\t\tCROSS_COMPILE=$(TARGET_CROSS) \\\n\t\tDTC=$(PKG_BUILD_DIR)/scripts/dtc/dtc \\\n\t\tKCFLAGS=\"$(filter-out -fstack-protector \\\n\t\t-mfloat-abi=hard, $(TARGET_CFLAGS)) -mfloat-abi=soft\"\nendef\n\n$(eval $(call BuildPackage/U-Boot))\n"
  },
  {
    "path": "package/boot/uboot-at91/patches/001-fix-Wformat-security.patch",
    "content": "From 3b05406c02070df3e7f19399d81ebd35ed6deae5 Mon Sep 17 00:00:00 2001\nFrom: Claudiu Beznea <claudiu.beznea@microchip.com>\nDate: Tue, 12 Oct 2021 17:43:28 +0300\nSubject: [PATCH] fix -Wformat-security\n\nSigned-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>\n---\n cmd/panic.c                      | 2 +-\n cmd/version.c                    | 2 +-\n drivers/pinctrl/pinctrl-uclass.c | 2 +-\n 3 files changed, 3 insertions(+), 3 deletions(-)\n\ndiff --git a/cmd/panic.c b/cmd/panic.c\nindex f13b3f094fab..197e2d0870ff 100644\n--- a/cmd/panic.c\n+++ b/cmd/panic.c\n@@ -11,7 +11,7 @@ static int do_panic(struct cmd_tbl *cmdtp, int flag, int argc,\n {\n \tchar *text = (argc < 2) ? \"\" : argv[1];\n \n-\tpanic(text);\n+\tpanic(\"%s\\n\", text);\n \n \treturn CMD_RET_SUCCESS;\n }\ndiff --git a/cmd/version.c b/cmd/version.c\nindex 3686b8733249..35b52c48171d 100644\n--- a/cmd/version.c\n+++ b/cmd/version.c\n@@ -19,7 +19,7 @@ static int do_version(struct cmd_tbl *cmdtp, int flag, int argc,\n {\n \tchar buf[DISPLAY_OPTIONS_BANNER_LENGTH];\n \n-\tprintf(display_options_get_banner(false, buf, sizeof(buf)));\n+\tprintf(\"%s\", display_options_get_banner(false, buf, sizeof(buf)));\n #ifdef CC_VERSION_STRING\n \tputs(CC_VERSION_STRING \"\\n\");\n #endif\ndiff --git a/drivers/pinctrl/pinctrl-uclass.c b/drivers/pinctrl/pinctrl-uclass.c\nindex b0f30aa1f758..aa62a890609a 100644\n--- a/drivers/pinctrl/pinctrl-uclass.c\n+++ b/drivers/pinctrl/pinctrl-uclass.c\n@@ -371,7 +371,7 @@ int pinctrl_get_pin_name(struct udevice *dev, int selector, char *buf,\n \tif (!ops->get_pin_name)\n \t\treturn -ENOSYS;\n \n-\tsnprintf(buf, size, ops->get_pin_name(dev, selector));\n+\tsnprintf(buf, size, \"%s\", ops->get_pin_name(dev, selector));\n \n \treturn 0;\n }\n-- \n2.33.0\n\n"
  },
  {
    "path": "package/boot/uboot-bcm4908/Makefile",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\ninclude $(TOPDIR)/rules.mk\ninclude $(INCLUDE_DIR)/kernel.mk\n\nPKG_RELEASE:=$(AUTORELEASE)\n\nPKG_SOURCE_PROTO:=git\nPKG_SOURCE_URL:=https://git.openwrt.org/project/bcm63xx/u-boot.git\nPKG_SOURCE_DATE:=2022-03-15\nPKG_SOURCE_VERSION:=0625aad74d1f5b6f9c068955ad3fd7f6df635e50\nPKG_MIRROR_HASH:=0602e0e4f101ead206940eccca832b75191905c1e81290340a89b07dbee7a6ce\n\ninclude $(INCLUDE_DIR)/u-boot.mk\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine U-Boot/Default\n  BUILD_TARGET:=bcm4908\n  UBOOT_IMAGE:=u-boot-nodtb.bin\n  DEFAULT:=y\nendef\n\ndefine U-Boot/bcm4908\n  NAME:=Broadcom's BCM4908\n  UBOOT_CONFIG:=bcm94908\nendef\n\ndefine U-Boot/bcm4912\n  NAME:=Broadcom's BCM4912\n  UBOOT_CONFIG:=bcm94912\nendef\n\nUBOOT_TARGETS := \\\n\tbcm4908 \\\n\tbcm4912\n\ndefine Build/Prepare\n\t$(call Build/Prepare/Default)\n\tmkdir -p $(PKG_BUILD_DIR)/include/generated/\n\t( cd $(PKG_BUILD_DIR)/board/broadcom/bcmbca/httpd/html/ && \\\n\t  $(STAGING_DIR_HOST)/bin/xxd -i index.html > ../../../../../include/generated/index.h && \\\n\t  $(STAGING_DIR_HOST)/bin/xxd -i flashing.html > ../../../../../include/generated/flashing.h && \\\n\t  $(STAGING_DIR_HOST)/bin/xxd -i fail.html > ../../../../../include/generated/fail.h && \\\n\t  $(STAGING_DIR_HOST)/bin/xxd -i 404.html > ../../../../../include/generated/404.h )\nendef\n\ndefine Build/InstallDev\n\t$(INSTALL_DIR) $(STAGING_DIR_IMAGE)/u-boot\n\t$(INSTALL_BIN) $(PKG_BUILD_DIR)/$(UBOOT_IMAGE) $(STAGING_DIR_IMAGE)/u-boot/\n\t$(INSTALL_BIN) $(PKG_BUILD_DIR)/u-boot.dtb $(STAGING_DIR_IMAGE)/u-boot/\n\t$(INSTALL_BIN) $(PKG_BUILD_DIR)/arch/arm/dts/*.dtb $(STAGING_DIR_IMAGE)/u-boot/\nendef\n\n$(eval $(call BuildPackage/U-Boot))\n"
  },
  {
    "path": "package/boot/uboot-bcm4908/patches/100-check-config-allow-to-complete-build-even-with-ad-ho.patch",
    "content": "From: Masahiro Yamada <yamada.masahiro@socionext.com>\nDate: Mon, 26 Sep 2016 13:05:02 +0900\nSubject: [PATCH] check-config: allow to complete build even with ad-hoc CONFIG\n options\n\nCurrently, the check-config.sh terminates the build when unknown\nad-hoc options are detected.  I think it is too much because we may\nwant to patch config headers locally in a build/deployment project.\n\nSo, let's relax check-config.sh to just warn even if it detects\noptions that are not in the whitelist.  Instead, this check can be\ndone at the end of build, along with other checks.  It will catch\nmore attention.\n\nEven with this change, the Buildman tool catches new warnings,\nso Tom can give NACK to new ad-hoc options.\n\nSigned-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>\n---\n scripts/check-config.sh | 3 +--\n 1 file changed, 1 insertion(+), 2 deletions(-)\n\n--- a/scripts/check-config.sh\n+++ b/scripts/check-config.sh\n@@ -50,14 +50,13 @@ cat `find ${srctree} -name \"Kconfig*\"` |sed -n \\\n \t|sort |uniq > ${ok}\n comm -23 ${suspects} ${ok} >${new_adhoc}\n if [ -s ${new_adhoc} ]; then\n-\techo >&2 \"Error: You must add new CONFIG options using Kconfig\"\n+\techo >&2 \"Warning: You must add new CONFIG options using Kconfig\"\n \techo >&2 \"The following new ad-hoc CONFIG options were detected:\"\n \tcat >&2 ${new_adhoc}\n \techo >&2\n \techo >&2 \"Please add these via Kconfig instead. Find a suitable Kconfig\"\n \techo >&2 \"file and add a 'config' or 'menuconfig' option.\"\n \t# Don't delete the temporary files in case they are useful\n-\texit 1\n else\n \trm ${suspects} ${ok} ${new_adhoc}\n fi\n"
  },
  {
    "path": "package/boot/uboot-bcm4908/patches/200-configs-bcm94908-unset-CONFIG_SPL.patch",
    "content": "From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Fri, 4 Mar 2022 09:21:32 +0100\nSubject: [PATCH] configs: bcm94908: unset CONFIG_SPL\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nCompiling SPL is always tricky as it needs to fit limited resources.\nFortunately in most cases there is no need to replace SPL or TPL while\nflashing a new firmware.\n\nCompiling SPL for BCM4908 seems to fail with non-Broadcom toolchain:\naarch64-openwrt-linux-musl-ld.bfd: u-boot-spl section `.u_boot_list' will not fit in region `.sram'\naarch64-openwrt-linux-musl-ld.bfd: section .bss VMA [00000000822b9000,00000000822b93ef] overlaps section .u_boot_list VMA [00000000822b8f60,00000000822b9a87]\naarch64-openwrt-linux-musl-ld.bfd: region `.sram' overflowed by 2696 bytes\n\nIt also requires hashtable.h which has to be generated using some\nBroadcom's custom perl script that isn't integrated as this point.\n\nFor now just disable SPL and use only last-stage U-Boot that must be\nshipped with every firmware.\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\n---\n configs/bcm94908_defconfig | 2 +-\n configs/bcm94912_defconfig | 2 +-\n 2 files changed, 2 insertions(+), 2 deletions(-)\n\n--- a/configs/bcm94908_defconfig\n+++ b/configs/bcm94908_defconfig\n@@ -21,7 +21,7 @@ CONFIG_SPL_SERIAL_SUPPORT=y\n CONFIG_TPL_LIBCOMMON_SUPPORT=y\n CONFIG_TPL_LIBGENERIC_SUPPORT=y\n CONFIG_NR_DRAM_BANKS=1\n-CONFIG_SPL=y\n+# CONFIG_SPL is not set\n CONFIG_SPL_LIBDISK_SUPPORT=y\n CONFIG_ENV_VARS_UBOOT_CONFIG=y\n CONFIG_TPL_SYS_MALLOC_F_LEN=0x11000\n--- a/configs/bcm94912_defconfig\n+++ b/configs/bcm94912_defconfig\n@@ -22,7 +22,7 @@ CONFIG_TPL_LIBCOMMON_SUPPORT=y\n CONFIG_TPL_LIBGENERIC_SUPPORT=y\n CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000\n CONFIG_NR_DRAM_BANKS=2\n-CONFIG_SPL=y\n+# CONFIG_SPL is not set\n CONFIG_SPL_LIBDISK_SUPPORT=y\n CONFIG_ENV_VARS_UBOOT_CONFIG=y\n CONFIG_TPL_SYS_MALLOC_F_LEN=0x10000\n"
  },
  {
    "path": "package/boot/uboot-bcm4908/patches/201-Assume-TPL-support-for-ATF-when-compiling-U-Boot-wit.patch",
    "content": "From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Fri, 4 Mar 2022 09:23:34 +0100\nSubject: [PATCH] Assume TPL support for ATF when compiling U-Boot without TPL\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nBroadcom's U-Boot behaviour depends on compilation time check whether\nTPL was compiled with or without ATF support. There is no proper runtime\ncheck.\n\nWhen compiling just U-Boot (without SPL & TPL) there is no way to tell\nif it's going to work with TPL with or without ATF support.\n\nModify code to blindly assume ATF support in TPL in such cases. It seems\nto be always true for Broadcom and we need some assumption as we don't\ndeal with compiling SPL or TPL.\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\n---\n arch/arm/mach-bcmbca/bcm4908/cpu.c | 2 +-\n arch/arm/mach-bcmbca/bcm4912/cpu.c | 2 +-\n board/broadcom/bcmbca/board.c      | 4 ++--\n 3 files changed, 4 insertions(+), 4 deletions(-)\n\n--- a/arch/arm/mach-bcmbca/bcm4908/cpu.c\n+++ b/arch/arm/mach-bcmbca/bcm4908/cpu.c\n@@ -138,7 +138,7 @@ int get_nr_cpus()\n \treturn nr_cpus;\n }\n \n-#if !defined(CONFIG_TPL_ATF)\n+#if defined(CONFIG_TPL) && !defined(CONFIG_TPL_ATF)\n void boot_secondary_cpu(unsigned long vector)\n {\n \tuint32_t cpu, nr_cpus = QUAD_CPUS;\n--- a/arch/arm/mach-bcmbca/bcm4912/cpu.c\n+++ b/arch/arm/mach-bcmbca/bcm4912/cpu.c\n@@ -174,7 +174,7 @@ int bcmbca_get_boot_device(void)\n \treturn BOOT_DEVICE_NONE;\n }\n \n-#if !defined(CONFIG_TPL_ATF)\n+#if defined(CONFIG_TPL) && !defined(CONFIG_TPL_ATF)\n void boot_secondary_cpu(unsigned long vector)\n {\n \tuint32_t cpu, nr_cpus = 4;\n--- a/board/broadcom/bcmbca/board.c\n+++ b/board/broadcom/bcmbca/board.c\n@@ -103,7 +103,7 @@ void board_spinor_init(void)\n \n int board_init(void)\n {\n-#if !defined(CONFIG_TPL_ATF)\n+#if defined(CONFIG_TPL) && !defined(CONFIG_TPL_ATF)\n \tunsigned long vector;\n #endif\n \tboard_sdk_init_e();\n@@ -121,7 +121,7 @@ int board_init(void)\n \tprintf(\"$Uboot: \"BUILD_TAG\" $\\n\");\n #endif\n \n-#if !defined(CONFIG_TPL_ATF)\n+#if defined(CONFIG_TPL) && !defined(CONFIG_TPL_ATF)\n #if defined(CONFIG_ARM64)\n \tvector  = (unsigned long)&_start;\n #else\n"
  },
  {
    "path": "package/boot/uboot-envtools/Makefile",
    "content": "#\n# Copyright (C) 2006-2014 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=uboot-envtools\nPKG_DISTNAME:=u-boot\nPKG_VERSION:=2022.01\nPKG_RELEASE:=$(AUTORELEASE)\n\nPKG_SOURCE:=$(PKG_DISTNAME)-$(PKG_VERSION).tar.bz2\nPKG_SOURCE_URL:= \\\n    https://ftp.denx.de/pub/u-boot \\\n    https://mirror.cyberbits.eu/u-boot \\\n    ftp://ftp.denx.de/pub/u-boot\nPKG_HASH:=81b4543227db228c03f8a1bf5ddbc813b0bb8f6555ce46064ef721a6fc680413\nPKG_SOURCE_SUBDIR:=$(PKG_DISTNAME)-$(PKG_VERSION)\nPKG_BUILD_DIR:=$(BUILD_DIR)/$(PKG_DISTNAME)-$(PKG_VERSION)\n\nPKG_BUILD_DEPENDS:=fstools\n\nPKG_LICENSE:=GPL-2.0 GPL-2.0+\nPKG_LICENSE_FILES:=Licenses/README\n\nPKG_FLAGS:=nonshared\n\nPKG_BUILD_PARALLEL:=1\n\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine Package/uboot-envtools\n  SECTION:=utils\n  CATEGORY:=Utilities\n  SUBMENU:=Boot Loaders\n  TITLE:=read/modify U-Boot bootloader environment\n  URL:=http://www.denx.de/wiki/U-Boot\nendef\n\ndefine Package/uboot-envtools/description\n This package includes tools to read and modify U-Boot bootloader environment.\nendef\n\ndefine Build/Configure\n\ttouch $(PKG_BUILD_DIR)/include/config.h\n\tmkdir -p $(PKG_BUILD_DIR)/include/config\n\ttouch $(PKG_BUILD_DIR)/include/config/auto.conf\n\tmkdir -p $(PKG_BUILD_DIR)/include/generated\n\ttouch $(PKG_BUILD_DIR)/include/generated/autoconf.h\nendef\n\nMAKE_FLAGS += \\\n\tTARGET_CFLAGS=\"$(TARGET_CFLAGS)\" \\\n\tTARGET_LDFLAGS=\"$(TARGET_LDFLAGS)\" \\\n\tno-dot-config-targets=envtools \\\n\tenvtools\n\ndefine Package/uboot-envtools/conffiles\n/etc/config/ubootenv\n/etc/fw_env.config\n/etc/fw_sys.config\nendef\n\ndefine Package/uboot-envtools/install\n\t$(INSTALL_DIR) $(1)/usr/sbin\n\t$(INSTALL_BIN) $(PKG_BUILD_DIR)/tools/env/fw_printenv $(1)/usr/sbin\n\t$(LN) fw_printenv $(1)/usr/sbin/fw_setenv\n\t$(INSTALL_BIN) ./files/fw_printsys $(1)/usr/sbin\n\t$(INSTALL_BIN) ./files/fw_setsys $(1)/usr/sbin\n\t$(INSTALL_DIR) $(1)/lib\n\t$(INSTALL_DATA) ./files/uboot-envtools.sh $(1)/lib\n\t$(INSTALL_DIR) $(1)/etc/uci-defaults\n\t$(if $(wildcard ./files/$(BOARD)_$(SUBTARGET)), \\\n\t\t$(INSTALL_DATA) ./files/$(BOARD)_$(SUBTARGET) \\\n\t\t$(1)/etc/uci-defaults/30_uboot-envtools, \\\n\t\t$(if $(wildcard ./files/$(BOARD)), \\\n\t\t\t$(INSTALL_DATA) ./files/$(BOARD) \\\n\t\t\t$(1)/etc/uci-defaults/30_uboot-envtools \\\n\t\t) \\\n\t)\nendef\n\n$(eval $(call BuildPackage,uboot-envtools))\n"
  },
  {
    "path": "package/boot/uboot-envtools/files/apm821xx",
    "content": "[ -e /etc/config/ubootenv ] && exit 0\n\ntouch /etc/config/ubootenv\n\n. /lib/uboot-envtools.sh\n. /lib/functions.sh\n\nboard=$(board_name)\n\ncase \"$board\" in\nmeraki,mr24)\n\tubootenv_add_uci_config \"/dev/mtd1\" \"0x0\" \"0x4000\" \"0x4000\" \"4\"\n\tubootenv_add_uci_config \"/dev/mtd2\" \"0x0\" \"0x4000\" \"0x4000\" \"4\"\n\t;;\nmeraki,mx60)\n\tubootenv_add_uci_config \"/dev/mtd1\" \"0x0\" \"0x20000\" \"0x20000\" \"4\"\n\t;;\nnetgear,wndap620|\\\nnetgear,wndap660)\n\tubootenv_add_uci_config \"/dev/mtd1\" \"0x0\" \"0x4000\" \"0x4000\" \"4\"\n\t;;\nesac\n\nconfig_load ubootenv\nconfig_foreach ubootenv_add_app_config ubootenv\n\nexit 0\n"
  },
  {
    "path": "package/boot/uboot-envtools/files/ath79",
    "content": "#\n# Copyright (C) 2011-2014 OpenWrt.org\n#\n\n[ -e /etc/config/ubootenv ] && exit 0\n\ntouch /etc/config/ubootenv\n\n. /lib/uboot-envtools.sh\n. /lib/functions.sh\n\nboard=$(board_name)\n\ncase \"$board\" in\nalfa-network,ap121f|\\\nalfa-network,ap121fe|\\\nalfa-network,n2q|\\\nalfa-network,n5q|\\\nalfa-network,pi-wifi4|\\\nalfa-network,r36a|\\\nalfa-network,tube-2hq|\\\nallnet,all-wap02860ac|\\\naraknis,an-300-ap-i-n|\\\naraknis,an-500-ap-i-ac|\\\naraknis,an-700-ap-i-ac|\\\narduino,yun|\\\nbuffalo,bhr-4grv2|\\\ndevolo,magic-2-wifi|\\\nengenius,eap1200h|\\\nengenius,eap300-v2|\\\nengenius,eap350-v1|\\\nengenius,eap600|\\\nengenius,ecb1200|\\\nengenius,ecb1750|\\\nengenius,ecb350-v1|\\\nengenius,ecb600|\\\nengenius,enh202-v1|\\\nengenius,ens202ext-v1|\\\nengenius,enstationac-v1|\\\netactica,eg200|\\\nglinet,gl-ar750s-nor|\\\nglinet,gl-ar750s-nor-nand|\\\nlibrerouter,librerouter-v1|\\\nnetgear,ex6400|\\\nnetgear,ex7300|\\\nnetgear,ex7300-v2|\\\nnetgear,wndr4300-v2|\\\nnetgear,wndr4500-v3|\\\nnetgear,wnr1000-v2|\\\nnetgear,wnr2000-v3|\\\nnetgear,wnr2200-8m|\\\nnetgear,wnr2200-16m|\\\nnetgear,wnr612-v2|\\\nocedo,koala|\\\nocedo,raccoon|\\\nopenmesh,a40|\\\nopenmesh,a60|\\\nopenmesh,mr600-v1|\\\nopenmesh,mr600-v2|\\\nopenmesh,mr900-v1|\\\nopenmesh,mr900-v2|\\\nopenmesh,mr1750-v1|\\\nopenmesh,mr1750-v2|\\\nopenmesh,om5p|\\\nopenmesh,om5p-an|\\\nopenmesh,om5p-ac-v1|\\\nopenmesh,om5p-ac-v2|\\\nsamsung,wam250|\\\nubnt,nanostation-m|\\\nyuncore,a770|\\\nyuncore,a782|\\\nyuncore,a930|\\\nyuncore,xd3200|\\\nyuncore,xd4200|\\\nziking,cpe46b|\\\nzyxel,nbg6616)\n\tubootenv_add_uci_config \"/dev/mtd1\" \"0x0\" \"0x10000\" \"0x10000\"\n\t;;\nbuffalo,wzr-hp-ag300h)\n\tubootenv_add_uci_config \"/dev/mtd3\" \"0x0\" \"0x10000\" \"0x10000\"\n\t;;\nbuffalo,wzr-hp-g300nh-rb|\\\nbuffalo,wzr-hp-g300nh-s)\n\tubootenv_add_uci_config \"/dev/mtd1\" \"0x0\" \"0x20000\" \"0x20000\"\n\t;;\ndomywifi,dw33d)\n\tubootenv_add_uci_config \"/dev/mtd4\" \"0x0\" \"0x10000\" \"0x10000\"\n\t;;\ndongwon,dw02-412h-64m|\\\ndongwon,dw02-412h-128m|\\\nglinet,gl-ar300m-lite|\\\nglinet,gl-ar300m-nand|\\\nglinet,gl-ar300m-nor|\\\nglinet,gl-ar300m16)\n\tidx=\"$(find_mtd_index u-boot-env)\"\n\t[ -n \"$idx\" ] && \\\n\t\tubootenv_add_uci_config \"/dev/mtd$idx\" \"0x0\" \"0x10000\" \"0x10000\"\n\t;;\nglinet,gl-ar150)\n\tubootenv_add_uci_config \"/dev/mtd1\" \"0x0\" \"0x8000\" \"0x10000\"\n\t;;\nnetgear,wndr3700|\\\nnetgear,wndr3700-v2|\\\nnetgear,wndrmac-v1)\n\tubootenv_add_uci_config \"/dev/mtd1\" \"0x0\" \"0x20000\" \"0x10000\"\n\t;;\nnetgear,wndr3700-v4|\\\nnetgear,wndr4300|\\\nnetgear,wndr4300tn|\\\nnetgear,wndr4300sw)\n\tubootenv_add_uci_config \"/dev/mtd1\" \"0x0\" \"0x40000\" \"0x20000\"\n\t;;\nopenmesh,om2p-v1|\\\nopenmesh,om2p-v2|\\\nopenmesh,om2p-v4|\\\nopenmesh,om2p-hs-v1|\\\nopenmesh,om2p-hs-v2|\\\nopenmesh,om2p-hs-v3|\\\nopenmesh,om2p-hs-v4|\\\nopenmesh,om2p-lc|\\\nplasmacloud,pa300|\\\nplasmacloud,pa300e)\n\tubootenv_add_uci_config \"/dev/mtd1\" \"0x0\" \"0x40000\" \"0x40000\"\n\t;;\nqihoo,c301)\n\tubootenv_add_uci_config \"/dev/mtd9\" \"0x0\" \"0x10000\" \"0x10000\"\n\t;;\nsophos,ap55|\\\nsophos,ap55c|\\\nsophos,ap100|\\\nsophos,ap100c)\n\tubootenv_add_uci_config \"/dev/mtd1\" \"0x0\" \"0x1000\" \"0x10000\"\n\t;;\nwallys,dr531)\n\tubootenv_add_uci_config \"/dev/mtd1\" \"0x0\" \"0xf800\" \"0x10000\"\n\t;;\nzte,mf286|\\\nzte,mf286a|\\\nzte,mf286r)\n\tubootenv_add_uci_config \"/dev/mtd7\" \"0x0\" \"0x20000\" \"0x10000\"\n\t;;\nesac\n\nconfig_load ubootenv\nconfig_foreach ubootenv_add_app_config ubootenv\n\nexit 0\n"
  },
  {
    "path": "package/boot/uboot-envtools/files/cns3xxx",
    "content": "#\n# Copyright (C) 2013 OpenWrt.org\n#\n\n[ -e /etc/config/ubootenv ] && exit 0\n\ntouch /etc/config/ubootenv\n\n. /lib/uboot-envtools.sh\n. /lib/functions.sh\n\nboard=$(board_name)\n\ncase \"$board\" in\nlaguna)\n\t# Laguna uboot env size/erasesize vary depending on NOR vs SPI FLASH\n\tsize=$(grep mtd1 /proc/mtd | awk '{print $2}')\n\terasesize=$(grep mtd1 /proc/mtd | awk '{print $3}')\n\tubootenv_add_uci_config \"/dev/mtd1\" \"0x0\" \"0x$size\" \"0x$erasesize\"\n\t;;\nesac\n\nconfig_load ubootenv\nconfig_foreach ubootenv_add_app_config ubootenv\n\nexit 0\n"
  },
  {
    "path": "package/boot/uboot-envtools/files/fw_printsys",
    "content": "#!/bin/sh\n[ -e /etc/fw_sys.config ] && exec /usr/sbin/fw_printenv -c /etc/fw_sys.config \"$@\"\n"
  },
  {
    "path": "package/boot/uboot-envtools/files/fw_setsys",
    "content": "#!/bin/sh\n[ -e /etc/fw_sys.config ] && exec /usr/sbin/fw_setenv -c /etc/fw_sys.config \"$@\"\n"
  },
  {
    "path": "package/boot/uboot-envtools/files/imx_cortexa9",
    "content": "#\n# Copyright (C) 2013-2014 OpenWrt.org\n#\n\n[ -e /etc/config/ubootenv ] && exit 0\n\ntouch /etc/config/ubootenv\n\n. /lib/imx.sh\n. /lib/uboot-envtools.sh\n. /lib/functions.sh\n\nboard=$(board_name)\n\ncase \"$board\" in\ngw,imx6dl-gw51xx|\\\ngw,imx6dl-gw52xx|\\\ngw,imx6dl-gw53xx|\\\ngw,imx6dl-gw54xx|\\\ngw,imx6dl-gw551x|\\\ngw,imx6dl-gw552x|\\\ngw,imx6dl-gw553x|\\\ngw,imx6dl-gw5904|\\\ngw,imx6dl-gw5907|\\\ngw,imx6dl-gw5910|\\\ngw,imx6dl-gw5912|\\\ngw,imx6dl-gw5913|\\\ngw,imx6q-gw51xx|\\\ngw,imx6q-gw52xx|\\\ngw,imx6q-gw53xx|\\\ngw,imx6q-gw5400-a|\\\ngw,imx6q-gw54xx|\\\ngw,imx6q-gw551x|\\\ngw,imx6q-gw552x|\\\ngw,imx6q-gw553x|\\\ngw,imx6q-gw5904|\\\ngw,imx6q-gw5907|\\\ngw,imx6q-gw5910|\\\ngw,imx6q-gw5912|\\\ngw,imx6q-gw5913)\n\tif [ -c /dev/mtd1 ]; then\n\t\t# board boots from NAND\n\t\tubootenv_add_uci_config /dev/mtd1 0x0 0x20000 0x40000\n\t\tubootenv_add_uci_config /dev/mtd1 0x80000 0x20000 0x40000\n\telse\n\t\t# board boots from microSD\n\t\tubootenv_add_uci_config /dev/mmcblk0 0xb1400 0x20000\n\t\tubootenv_add_uci_config /dev/mmcblk0 0xd1400 0x20000\n\tfi\n\t;;\ntoradex,apalis_imx6q-eval|\\\ntoradex,apalis_imx6q-ixora|\\\ntoradex,apalis_imx6q-ixora-v1.1)\n\tubootenv_add_uci_config $(bootdev_from_uuid)boot0 -0x2200 0x2000 0x200 10\n\t;;\nwand,imx6dl-wandboard)\n\tubootenv_add_uci_config \"/dev/mmcblk0\" \"0x60000\" \"0x2000\" \"0x2000\"\n\t;;\nesac\n\nconfig_load ubootenv\nconfig_foreach ubootenv_add_app_config ubootenv\n\nexit 0\n"
  },
  {
    "path": "package/boot/uboot-envtools/files/ipq40xx",
    "content": "#\n# Copyright (C) 2016 LEDE\n#\n\n[ -e /etc/config/ubootenv ] && exit 0\n\ntouch /etc/config/ubootenv\n\n. /lib/uboot-envtools.sh\n. /lib/functions.sh\n\nboard=$(board_name)\n\nubootenv_mtdinfo () {\n\tUBOOTENV_PART=$(cat /proc/mtd | grep APPSBLENV)\n\tmtd_dev=$(echo $UBOOTENV_PART | awk '{print $1}' | sed 's/:$//')\n\tmtd_size=$(echo $UBOOTENV_PART | awk '{print \"0x\"$2}')\n\tmtd_erase=$(echo $UBOOTENV_PART | awk '{print \"0x\"$3}')\n\tnor_flash=$(find /sys/bus/spi/devices/*/mtd -name ${mtd_dev})\n\n\tif [ -n \"$nor_flash\" ]; then\n\t\tubootenv_size=$mtd_size\n\telse\n\t\t# size is fixed to 0x40000 in u-boot\n\t\tubootenv_size=0x40000\n\tfi\n\n\tsectors=$(( $ubootenv_size / $mtd_erase ))\n\techo /dev/$mtd_dev 0x0 $ubootenv_size $mtd_erase $sectors\n}\n\ncase \"$board\" in\nalfa-network,ap120c-ac|\\\ndevolo,magic-2-wifi-next|\\\nedgecore,ecw5211|\\\nglinet,gl-ap1300|\\\nglinet,gl-b1300|\\\nglinet,gl-b2200|\\\nluma,wrtq-329acn|\\\nnetgear,wac510|\\\nopenmesh,a42|\\\nopenmesh,a62|\\\nplasmacloud,pa1200|\\\nplasmacloud,pa2200)\n\tubootenv_add_uci_config \"/dev/mtd5\" \"0x0\" \"0x10000\" \"0x10000\"\n\t;;\naruba,ap-303)\n\tubootenv_add_uci_config \"/dev/mtd13\" \"0x0\" \"0x10000\" \"0x10000\"\n\t;;\naruba,ap-365)\n\tubootenv_add_uci_config \"/dev/mtd8\" \"0x0\" \"0x10000\" \"0x10000\"\n\t;;\nbuffalo,wtr-m2133hp)\n\tubootenv_add_uci_config \"/dev/mtd8\" \"0x0\" \"0x40000\" \"0x20000\"\n\t;;\nlinksys,ea6350v3)\n\tubootenv_add_uci_config \"/dev/mtd7\" \"0x0\" \"0x20000\" \"0x20000\"\n\t;;\nlinksys,ea8300|\\\nlinksys,mr8300)\n\tubootenv_add_uci_config \"/dev/mtd7\" \"0x0\" \"0x40000\" \"0x20000\"\n\t;;\nzyxel,nbg6617)\n\tubootenv_add_uci_config \"/dev/mtd6\" \"0x0\" \"0x10000\" \"0x10000\"\n\t;;\nesac\n\nconfig_load ubootenv\nconfig_foreach ubootenv_add_app_config ubootenv\n\nexit 0\n"
  },
  {
    "path": "package/boot/uboot-envtools/files/ipq806x",
    "content": "#\n# Copyright (C) 2016 LEDE\n#\n\n[ -e /etc/config/ubootenv ] && exit 0\n\ntouch /etc/config/ubootenv\n\n. /lib/uboot-envtools.sh\n. /lib/functions.sh\n\nboard=$(board_name)\n\nubootenv_mtdinfo () {\n\tUBOOTENV_PART=$(cat /proc/mtd | grep APPSBLENV)\n\tmtd_dev=$(echo $UBOOTENV_PART | awk '{print $1}' | sed 's/:$//')\n\tmtd_size=$(echo $UBOOTENV_PART | awk '{print \"0x\"$2}')\n\tmtd_erase=$(echo $UBOOTENV_PART | awk '{print \"0x\"$3}')\n\tnor_flash=$(find /sys/bus/spi/devices/*/mtd -name ${mtd_dev})\n\n\tif [ -n \"$nor_flash\" ]; then\n\t\tubootenv_size=$mtd_size\n\telse\n\t\t# size is fixed to 0x40000 in u-boot\n\t\tubootenv_size=0x40000\n\tfi\n\n\tsectors=$(( $ubootenv_size / $mtd_erase ))\n\techo /dev/$mtd_dev 0x0 $ubootenv_size $mtd_erase $sectors\n}\n\ncase \"$board\" in\narris,tr4400-v2|\\\naskey,rt4230w-rev6)\n\tubootenv_add_uci_config \"/dev/mtd9\" \"0x0\" \"0x40000\" \"0x20000\"\n\t;;\nedgecore,ecw5410)\n\tubootenv_add_uci_config \"/dev/mtd11\" \"0x0\" \"0x10000\" \"0x10000\"\n\t;;\nlinksys,ea7500-v1|\\\nlinksys,ea8500)\n\tubootenv_add_uci_config \"/dev/mtd10\" \"0x0\" \"0x20000\" \"0x20000\"\n\t;;\nnetgear,r7800)\n\tubootenv_add_uci_config \"/dev/mtd2\" \"0x0\" \"0x040000\" \"0x20000\"\n\t;;\nqcom,ipq8064-ap148|\\\nqcom,ipq8064-db149)\n\tubootenv_add_uci_config $(ubootenv_mtdinfo)\n\t;;\nubnt,unifi-ac-hd|\\\nzyxel,nbg6817)\n\tubootenv_add_uci_config \"/dev/mtdblock9\" \"0x0\" \"0x10000\" \"0x10000\"\n\t;;\nesac\n\nconfig_load ubootenv\nconfig_foreach ubootenv_add_app_config ubootenv\n\nexit 0\n"
  },
  {
    "path": "package/boot/uboot-envtools/files/kirkwood",
    "content": "#\n# Copyright (C) 2012-2014 OpenWrt.org\n#\n\n[ -e /etc/config/ubootenv ] && exit 0\n\ntouch /etc/config/ubootenv\n\n. /lib/uboot-envtools.sh\n. /lib/functions.sh\n\nboard=$(board_name)\n\ncase \"$board\" in\ncheckpoint,l-50|\\\ncloudengines,pogoe02|\\\ncloudengines,pogoplugv4|\\\nglobalscale,sheevaplug|\\\niom,ix2-200|\\\nlinksys,e4200-v2|\\\nlinksys,ea4500|\\\nnetgear,readynas-duo-v2|\\\nraidsonic,ib-nas62x0|\\\nseagate,dockstar|\\\nzyxel,nsa310b|\\\nzyxel,nsa310s|\\\nzyxel,nsa325)\n\tubootenv_add_uci_config \"/dev/mtd1\" \"0x0\" \"0x20000\" \"0x20000\"\n\t;;\nlinksys,ea3500)\n\tubootenv_add_uci_config \"/dev/mtd1\" \"0x0\" \"0x4000\" \"0x4000\"\n\t;;\nesac\n\nconfig_load ubootenv\nconfig_foreach ubootenv_add_app_config ubootenv\n\nexit 0\n"
  },
  {
    "path": "package/boot/uboot-envtools/files/lantiq",
    "content": "#\n# Copyright (C) 2012 OpenWrt.org\n#\n\n[ -e /etc/config/ubootenv ] && exit 0\n\ntouch /etc/config/ubootenv\n\n. /lib/uboot-envtools.sh\n. /lib/functions.sh\n\nboard=$(board_name)\n\ncase \"$board\" in\nbt,homehub-v2b)\n\tubootenv_add_uci_config \"/dev/mtd1\" \"0x0\" \"0x10000\" \"0x10000\" \"1\"\n\t;;\nbt,homehub-v3a)\n\tubootenv_add_uci_config \"/dev/mtd2\" \"0x0\" \"0x4000\" \"0x4000\" \"1\"\n\t;;\nsiemens,gigaset-sx76x)\n\tubootenv_add_uci_config \"/dev/mtd1\" \"0x0\" \"0x10000\" \"0x10000\" \"1\"\n\t;;\nzyxel,p-2812hnu-f1)\n\tubootenv_add_uci_config \"/dev/mtd1\" \"0x0\" \"0x2000\" \"0x20000\" \"1\"\n\t;;\nbuffalo,wbmr-300hpd)\n\tidx=\"$(find_mtd_index u-boot-env)\"\n\t[ -n \"$idx\" ] && \\\n\t\tubootenv_add_uci_config \"/dev/mtd$idx\" \"0x0\" \"0x2000\" \"0x1000\" \"2\"\n\t;;\nesac\n\nconfig_load ubootenv\nconfig_foreach ubootenv_add_app_config ubootenv\n\nexit 0\n"
  },
  {
    "path": "package/boot/uboot-envtools/files/layerscape",
    "content": "#\n# Copyright (C) 2016 LEDE\n#\n\n[ -f /etc/config/ubootenv ] && exit 0\n\ntouch /etc/config/ubootenv\n\n. /lib/uboot-envtools.sh\n. /lib/functions.sh\n\nboard=$(board_name)\n\ncase \"$board\" in\n\ttraverse,ls1043v|\\\n\ttraverse,ls1043s)\n\t\tubootenv_add_uci_config \"/dev/mtd1\" \"0x40000\" \"0x2000\"  \"0x20000\"\n\t;;\nesac\n\nconfig_load ubootenv\nconfig_foreach ubootenv_add_app_config ubootenv\n\nexit 0\n"
  },
  {
    "path": "package/boot/uboot-envtools/files/mediatek_mt7622",
    "content": "#\n# Copyright (C) 2021 OpenWrt.org\n#\n\n[ -e /etc/config/ubootenv ] && exit 0\n\ntouch /etc/config/ubootenv\n\n. /lib/uboot-envtools.sh\n. /lib/functions.sh\n\nboard=$(board_name)\n\ncase \"$board\" in\nlinksys,e8450-ubi)\n\tubootenv_add_uci_config \"/dev/ubi0_0\" \"0x0\" \"0x1f000\" \"0x1f000\" \"1\"\n\tubootenv_add_uci_config \"/dev/ubi0_1\" \"0x0\" \"0x1f000\" \"0x1f000\" \"1\"\n\t;;\nbananapi,bpi-r64)\n\t. /lib/upgrade/common.sh\n\texport_bootdevice\n\texport_partdevice rootdev 0\n\tcase \"$rootdev\" in\n\tmmc*)\n\t\tlocal envdev=$(find_mmc_part \"ubootenv\" $rootdev)\n\t\tubootenv_add_uci_config \"$envdev\" \"0x0\" \"0x80000\" \"0x80000\" \"1\"\n\t\tubootenv_add_uci_config \"$envdev\" \"0x80000\" \"0x80000\" \"0x80000\" \"1\"\n\t\t;;\n\t*)\n\t\tubootenv_add_uci_config \"/dev/ubi0_0\" \"0x0\" \"0x1f000\" \"0x1f000\" \"1\"\n\t\tubootenv_add_uci_config \"/dev/ubi0_1\" \"0x0\" \"0x1f000\" \"0x1f000\" \"1\"\n\t\t;;\n\tesac\n\t;;\nbuffalo,wsr-2533dhp2)\n\tubootenv_add_uci_config \"/dev/mtd3\" \"0x0\" \"0x1000\" \"0x20000\"\n\t;;\nruijie,rg-ew3200gx-pro)\n\tubootenv_add_uci_config \"/dev/mtd3\" \"0x0\" \"0x20000\" \"0x20000\"\n\t;;\nubnt,unifi-6-lr-ubootmod)\n\tubootenv_add_uci_config \"/dev/mtd2\" \"0x0\" \"0x4000\" \"0x10000\"\n\t;;\nxiaomi,redmi-router-ax6s)\n\tubootenv_add_uci_config \"/dev/mtd3\" \"0x0\" \"0x10000\" \"0x40000\"\n\t;;\nesac\n\nconfig_load ubootenv\nconfig_foreach ubootenv_add_app_config ubootenv\n\nexit 0\n"
  },
  {
    "path": "package/boot/uboot-envtools/files/mediatek_mt7623",
    "content": "#\n# Copyright (C) 2021 OpenWrt.org\n#\n\n[ -e /etc/config/ubootenv ] && exit 0\n\ntouch /etc/config/ubootenv\n\n. /lib/uboot-envtools.sh\n. /lib/functions.sh\n\nboard=$(board_name)\n\ncase \"$board\" in\nbananapi,bpi-r2)\n\t. /lib/upgrade/common.sh\n\texport_bootdevice\n\texport_partdevice ubootpart 1\n\tubootenv_add_uci_config \"/dev/$ubootpart\" \"0xb0000\" \"0x10000\" \"0x10000\" \"1\"\n\t;;\nunielec,u7623-02)\n\tubootenv_add_uci_config \"/dev/mmcblk0p1\" \"0xc0000\" \"0x10000\" \"0x10000\" \"1\"\n\t;;\nesac\n\nconfig_load ubootenv\nconfig_foreach ubootenv_add_app_config ubootenv\n\nexit 0\n"
  },
  {
    "path": "package/boot/uboot-envtools/files/mpc85xx",
    "content": "[ -e /etc/config/ubootenv ] && exit 0\n\ntouch /etc/config/ubootenv\n\n. /lib/uboot-envtools.sh\n. /lib/functions.sh\n\nboard=$(board_name)\n\ncase \"$board\" in\nextreme-networks,ws-ap3825i)\n\tubootenv_add_uci_config \"$(find_mtd_part 'cfg1')\" \"0x0\" \"0x10000\" \"0x20000\"\n\tubootenv_add_uci_config \"$(find_mtd_part 'cfg2')\" \"0x0\" \"0x10000\" \"0x20000\"\n\t;;\nocedo,panda)\n\tubootenv_add_uci_config \"/dev/mtd1\" \"0x0\" \"0x20000\" \"0x20000\"\n\tubootenv_add_uci_config \"/dev/mtd2\" \"0x0\" \"0x20000\" \"0x20000\"\n\t;;\naerohive,hiveap-330)\n\tubootenv_add_uci_config \"$(find_mtd_part 'u-boot-env')\" \"0x0\" \"0x20000\" \"0x10000\"\n\t;;\nesac\n\nconfig_load ubootenv\nconfig_foreach ubootenv_add_app_config ubootenv\n\nexit 0\n"
  },
  {
    "path": "package/boot/uboot-envtools/files/mvebu",
    "content": "#\n# Copyright (C) 2014-2016 OpenWrt.org\n# Copyright (C) 2016 LEDE-Project.org\n#\n\n[ -e /etc/config/ubootenv ] && exit 0\n\ntouch /etc/config/ubootenv\n\n. /lib/uboot-envtools.sh\n. /lib/functions.sh\n\nboard=$(board_name)\n\ncase \"$board\" in\nbuffalo,ls421de)\n\tubootenv_add_uci_config \"/dev/mtd3\" \"0x0\" \"0x10000\"\n\t;;\ncznic,turris-omnia)\n\tidx=\"$(find_mtd_index u-boot-env)\"\n\tif [ -n \"$idx\" ]; then\n\t\tubootenv_add_uci_config \"/dev/mtd${idx}\" \"0x0\" \"0x10000\" \"0x10000\"\n\telif grep -q 'U-Boot 2015.10-rc2' /dev/mtd0; then\n\t\tubootenv_add_uci_config \"/dev/mtd0\" \"0xc0000\" \"0x10000\" \"0x40000\"\n\telse\n\t\tubootenv_add_uci_config \"/dev/mtd0\" \"0xf0000\" \"0x10000\" \"0x10000\"\n\tfi\n\t;;\nglinet,gl-mv1000)\n\tubootenv_add_uci_config \"/dev/mtd1\" \"0x0\" \"0x8000\" \"0x8000\" \"1\"\n\t;;\nglobalscale,espressobin|\\\nglobalscale,espressobin-emmc|\\\nglobalscale,espressobin-ultra|\\\nglobalscale,espressobin-v7|\\\nglobalscale,espressobin-v7-emmc|\\\nglobalscale,mochabin)\n\tidx=\"$(find_mtd_index u-boot-env)\"\n\tif [ -n \"$idx\" ]; then\n\t\tubootenv_add_uci_config \"/dev/mtd$idx\" \"0x0\" \"0x10000\" \"0x10000\" \"1\"\n\telse\n\t\tubootenv_add_uci_config \"/dev/mtd0\" \"0x3f0000\" \"0x10000\" \"0x10000\" \"1\"\n\tfi\n\t;;\nmarvell,armada8040-mcbin-doubleshot|\\\nmarvell,armada8040-mcbin-singleshot)\n\tubootenv_add_uci_config \"/dev/mtd0\" \"0x3f0000\" \"0x10000\" \"0x10000\" \"1\"\n\t;;\nlinksys,wrt1200ac|\\\nlinksys,wrt1900ac-v2|\\\nlinksys,wrt1900acs)\n\tubootenv_add_uci_config \"/dev/mtd1\" \"0x0\" \"0x20000\" \"0x40000\"\n\t;;\nlinksys,wrt1900ac-v1)\n\tubootenv_add_uci_config \"/dev/mtd1\" \"0x0\" \"0x40000\" \"0x20000\"\n\t;;\nlinksys,wrt3200acm|\\\nlinksys,wrt32x)\n\tubootenv_add_uci_config \"/dev/mtd1\" \"0x0\" \"0x20000\" \"0x20000\"\n\t;;\nmethode,udpu)\n\tubootenv_add_uci_config \"/dev/mtd0\" \"0x180000\" \"0x10000\" \"0x10000\"\n\t;;\nesac\n\nconfig_load ubootenv\nconfig_foreach ubootenv_add_app_config ubootenv\n\nexit 0\n"
  },
  {
    "path": "package/boot/uboot-envtools/files/mxs",
    "content": "#\n# Copyright (C) 2013 OpenWrt.org\n#\n\n[ -e /etc/config/ubootenv ] && exit 0\n\ntouch /etc/config/ubootenv\n\n. /lib/uboot-envtools.sh\n. /lib/functions.sh\n\nboard=$(board_name)\n\ncase \"$board\" in\ni2se,duckbill)\n\tubootenv_add_uci_config \"/dev/mmcblk0\" \"0x20000\" \"0x20000\"\n\tubootenv_add_uci_config \"/dev/mmcblk0\" \"0x40000\" \"0x20000\"\n\t;;\nolimex,imx23-olinuxino)\n\tubootenv_add_uci_config \"/dev/mmcblk0\" \"0x40000\" \"0x4000\"\n\t;;\nesac\n\nconfig_load ubootenv\nconfig_foreach ubootenv_add_app_config ubootenv\n\nexit 0\n"
  },
  {
    "path": "package/boot/uboot-envtools/files/oxnas",
    "content": "#\n# Copyright (C) 2013 OpenWrt.org\n#\n\n[ -e /etc/config/ubootenv ] && exit 0\n\ntouch /etc/config/ubootenv\n\n. /lib/uboot-envtools.sh\n. /lib/functions.sh\n\nboard=$(board_name)\n\ncase \"$board\" in\n\"cloudengines,pogoplug\"*|\\\n\"shuttle,kd20\")\n\tubootenv_add_uci_config \"/dev/mtd2\" \"0x0\" \"0x2000\" \"0x20000\" \"1\"\n\t;;\n\"mitrastar,stg-212\")\n\tubootenv_add_uci_config \"/dev/mtd2\" \"0x0\" \"0x20000\" \"0x20000\" \"1\"\n\t;;\nesac\n\nconfig_load ubootenv\nconfig_foreach ubootenv_add_app_config ubootenv\n\nexit 0\n"
  },
  {
    "path": "package/boot/uboot-envtools/files/pistachio",
    "content": "#\n# Copyright (C) 2017 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\n[ -e /etc/config/ubootenv ] && exit 0\n\ntouch /etc/config/ubootenv\n\n. /lib/uboot-envtools.sh\n. /lib/functions.sh\n\nboard=$(board_name)\n\ncase \"$board\" in\nimg,pistachio-marduk)\n\tubootenv_add_uci_config \"/dev/mtd2\" \"0x0\" \"0x2000\" \"0x1000\"\n\t;;\nesac\n\nconfig_load ubootenv\nconfig_foreach ubootenv_add_app_config ubootenv\n\nexit 0\n"
  },
  {
    "path": "package/boot/uboot-envtools/files/qoriq",
    "content": "[ -e /etc/config/ubootenv ] && exit 0\n\ntouch /etc/config/ubootenv\n\n. /lib/uboot-envtools.sh\n. /lib/functions.sh\n\nboard=$(board_name)\n\ncase \"$board\" in\nwatchguard,firebox-m300)\n\tubootenv_add_uci_config \"/dev/mtd9\" \"0x0\" \"0x2000\" \"0x10000\"\n\t;;\nesac\n\nconfig_load ubootenv\nconfig_foreach ubootenv_add_app_config ubootenv\n\nexit 0\n"
  },
  {
    "path": "package/boot/uboot-envtools/files/ramips",
    "content": "#\n# Copyright (C) 2011-2012 OpenWrt.org\n#\n\n[ -e /etc/config/ubootenv ] && exit 0\n\ntouch /etc/config/ubootenv\n\n. /lib/uboot-envtools.sh\n. /lib/functions.sh\n\nboard=$(board_name)\n\ncase \"$board\" in\nalfa-network,ac1200rm|\\\nalfa-network,awusfree1|\\\nalfa-network,quad-e4g|\\\nalfa-network,r36m-e4g|\\\nalfa-network,tube-e4g|\\\nengenius,esr600h|\\\nsitecom,wlr-4100-v1-002)\n\tubootenv_add_uci_config \"/dev/mtd1\" \"0x0\" \"0x1000\" \"0x1000\"\n\t;;\nallnet,all0256n-4m|\\\nallnet,all0256n-8m|\\\nallnet,all5002|\\\nyuncore,ax820)\n\tubootenv_add_uci_config \"/dev/mtd1\" \"0x0\" \"0x10000\" \"0x10000\"\n\t;;\nampedwireless,ally-00x19k|\\\nampedwireless,ally-r1900k)\n\tubootenv_add_uci_config \"/dev/mtd1\" \"0x0\" \"0x1000\" \"0x20000\" \"4\"\n\t;;\nbuffalo,wsr-1166dhp|\\\nbuffalo,wsr-600dhp|\\\nmediatek,linkit-smart-7688|\\\nsamknows,whitebox-v8|\\\nxiaomi,mi-router-3g-v2|\\\nxiaomi,mi-router-4a-gigabit|\\\nxiaomi,mi-router-4c|\\\nxiaomi,miwifi-3c|\\\nxiaomi,miwifi-nano|\\\nzbtlink,zbt-wg2626|\\\nzte,mf283plus)\n\tubootenv_add_uci_config \"/dev/mtd1\" \"0x0\" \"0x1000\" \"0x10000\"\n\t;;\nhootoo,ht-tm05|\\\nravpower,rp-wd03)\n\tidx=\"$(find_mtd_index u-boot-env)\"\n\t[ -n \"$idx\" ] && \\\n\t\tubootenv_add_uci_config \"/dev/mtd$idx\" \"0x4000\" \"0x1000\" \"0x1000\"\n\t;;\njcg,q20)\n\tubootenv_add_uci_config \"/dev/mtd1\" \"0x0\" \"0x20000\" \"0x20000\"\n\t;;\nbeeline,smartbox-flash|\\\nlinksys,ea6350-v4|\\\nlinksys,ea7300-v1|\\\nlinksys,ea7300-v2|\\\nlinksys,ea7500-v2|\\\nlinksys,ea8100-v1|\\\nlinksys,ea8100-v2|\\\nxiaomi,mi-router-3g|\\\nxiaomi,mi-router-3-pro|\\\nxiaomi,mi-router-4|\\\nxiaomi,mi-router-ac2100|\\\nxiaomi,redmi-router-ac2100)\n\tubootenv_add_uci_config \"/dev/mtd1\" \"0x0\" \"0x1000\" \"0x20000\"\n\t;;\nzyxel,nr7101)\n\tidx=\"$(find_mtd_index Config)\"\n\t[ -n \"$idx\" ] && \\\n\t\tubootenv_add_uci_config \"/dev/mtd$idx\" \"0x0\" \"0x1000\" \"0x80000\"\n\t;;\nbolt,arion|\\\nxiaomi,mi-router-cr6606|\\\nxiaomi,mi-router-cr6608|\\\nxiaomi,mi-router-cr6609)\n\tubootenv_add_uci_config \"/dev/mtd1\" \"0x0\" \"0x10000\" \"0x20000\"\n\t;;\nesac\n\nconfig_load ubootenv\nconfig_foreach ubootenv_add_app_config ubootenv\n\nexit 0\n"
  },
  {
    "path": "package/boot/uboot-envtools/files/realtek",
    "content": "[ -e /etc/config/ubootenv ] && exit 0\n\ntouch /etc/config/ubootenv\n\n. /lib/uboot-envtools.sh\n. /lib/functions.sh\n\nboard=$(board_name)\n\ncase \"$board\" in\nd-link,dgs-1210-16|\\\nd-link,dgs-1210-28|\\\nd-link,dgs-1210-10p|\\\nzyxel,gs1900-8|\\\nzyxel,gs1900-8hp-v1|\\\nzyxel,gs1900-8hp-v2|\\\nzyxel,gs1900-10hp|\\\nzyxel,gs1900-16|\\\nzyxel,gs1900-24-v1|\\\nzyxel,gs1900-24hp-v1|\\\nzyxel,gs1900-24hp-v2)\n\tidx=\"$(find_mtd_index u-boot-env)\"\n\t[ -n \"$idx\" ] && \\\n\t\tubootenv_add_uci_config \"/dev/mtd$idx\" \"0x0\" \"0x400\" \"0x10000\"\n\tidx2=\"$(find_mtd_index u-boot-env2)\"\n\t[ -n \"$idx2\" ] && \\\n\t\tubootenv_add_uci_sys_config \"/dev/mtd$idx2\" \"0x0\" \"0x1000\" \"0x10000\"\n\t;;\niodata,bsh-g24mb)\n\tidx=\"$(find_mtd_index u-boot-env)\"\n\t[ -n \"$idx\" ] && \\\n\t\tubootenv_add_uci_config \"/dev/mtd$idx\" \"0x0\" \"0x10000\" \"0x10000\"\n\tidx2=\"$(find_mtd_index u-boot-env2)\"\n\t[ -n \"$idx2\" ] && \\\n\t\tubootenv_add_uci_sys_config \"/dev/mtd$idx2\" \"0x0\" \"0x3800\" \"0x10000\"\n\t;;\n*)\n\tidx=\"$(find_mtd_index u-boot-env)\"\n\t[ -n \"$idx\" ] && \\\n\t\tubootenv_add_uci_config \"/dev/mtd$idx\" \"0x0\" \"0x10000\" \"0x10000\"\n\tidx2=\"$(find_mtd_index u-boot-env2)\"\n\t[ -n \"$idx2\" ] && \\\n\t\tubootenv_add_uci_sys_config \"/dev/mtd$idx2\" \"0x0\" \"0x1000\" \"0x10000\"\n\t;;\nesac\n\nconfig_load ubootenv\nconfig_foreach ubootenv_add_app_config\n\nexit 0\n"
  },
  {
    "path": "package/boot/uboot-envtools/files/uboot-envtools.sh",
    "content": "#!/bin/sh\n#\n# Copyright (C) 2011-2012 OpenWrt.org\n#\n\n_ubootenv_add_uci_config() {\n\tlocal cfgtype=$1\n\tlocal dev=$2\n\tlocal offset=$3\n\tlocal envsize=$4\n\tlocal secsize=$5\n\tlocal numsec=$6\n\tuci batch <<EOF\nadd ubootenv $cfgtype\nset ubootenv.@$cfgtype[-1].dev='$dev'\nset ubootenv.@$cfgtype[-1].offset='$offset'\nset ubootenv.@$cfgtype[-1].envsize='$envsize'\nset ubootenv.@$cfgtype[-1].secsize='$secsize'\nset ubootenv.@$cfgtype[-1].numsec='$numsec'\nEOF\n\tuci commit ubootenv\n}\n\nubootenv_add_uci_config() {\n\t_ubootenv_add_uci_config \"ubootenv\" \"$@\"\n}\n\nubootenv_add_uci_sys_config() {\n\t_ubootenv_add_uci_config \"ubootsys\" \"$@\"\n}\n\nubootenv_add_app_config() {\n\tlocal cfgtype\n\tlocal dev\n\tlocal offset\n\tlocal envsize\n\tlocal secsize\n\tlocal numsec\n\tconfig_get cfgtype \"$1\" TYPE\n\tconfig_get dev \"$1\" dev\n\tconfig_get offset \"$1\" offset\n\tconfig_get envsize \"$1\" envsize\n\tconfig_get secsize \"$1\" secsize\n\tconfig_get numsec \"$1\" numsec\n\tgrep -q \"^[[:space:]]*${dev}[[:space:]]*${offset}\" \"/etc/fw_${cfgtype#uboot}.config\" || echo \"$dev $offset $envsize $secsize $numsec\" >>\"/etc/fw_${cfgtype#uboot}.config\"\n}\n"
  },
  {
    "path": "package/boot/uboot-envtools/patches/001-compile.patch",
    "content": "--- a/tools/env/Makefile\n+++ b/tools/env/Makefile\n@@ -8,6 +8,13 @@\n # with \"CC\" here for the maximum code reuse of scripts/Makefile.host.\n override HOSTCC = $(CC)\n \n+ifneq ($(TARGET_CFLAGS),)\n+KBUILD_HOSTCFLAGS = $(TARGET_CFLAGS)\n+endif\n+ifneq ($(TARGET_LDFLAGS),)\n+KBUILD_HOSTLDFLAGS = $(TARGET_LDFLAGS)\n+endif\n+\n # Compile for a hosted environment on the target\n HOST_EXTRACFLAGS  = -I$(srctree)/tools \\\n \t\t$(patsubst -I%,-idirafter%, $(filter -I%, $(UBOOTINCLUDE))) \\\n"
  },
  {
    "path": "package/boot/uboot-fritz4040/Makefile",
    "content": "#\n# Copyright (C) 2013-2014 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\ninclude $(INCLUDE_DIR)/kernel.mk\n\nPKG_SOURCE_URL:=https://github.com/chunkeey/FritzBox-4040-UBOOT\nPKG_SOURCE_PROTO:=git\nPKG_SOURCE_VERSION:=9d89013f9cc963eca25856c61fa066091d35f8de\nPKG_SOURCE_DATE:=2022-05-01\nPKG_MIRROR_HASH:=4f2a3782ba359e6d901b536d1d685026913c14426f8e58ba9673281f20675050\n\nPKG_RELEASE:=$(AUTORELEASE)\n\ninclude $(INCLUDE_DIR)/u-boot.mk\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine U-Boot/Default\n  BUILD_TARGET:=ipq40xx\n  BUILD_SUBTARGET:=generic\n  UBOOT_BOARD:=$(1)\n  UBOOT_IMAGE:=uboot-$(1).bin\nendef\n\ndefine U-Boot/fritz1200\n  NAME:=FritzRepeater 1200\n  BUILD_DEVICES:=avm_fritzrepeater-1200\nendef\n\ndefine U-Boot/fritz3000\n  NAME:=FritzRepeater 3000\n  BUILD_DEVICES:=avm_fritzrepeater-3000\nendef\n\ndefine U-Boot/fritz4040\n  NAME:=FritzBox 4040\n  BUILD_DEVICES:=avm_fritzbox-4040\nendef\n\ndefine U-Boot/fritz7530\n  NAME:=FritzBox 7530\n  BUILD_DEVICES:=avm_fritzbox-7530\nendef\n\nUBOOT_CONFIGURE_VARS += USE_PRIVATE_LIBGCC=yes\nUBOOT_MAKE_FLAGS = USE_PRIVATE_LIBGCC=yes\nexport DTC\n\ndefine Build/Configure\n\t$(Build/Configure/U-Boot)\n\t$(HOSTCC) $(HOST_CFLAGS) $(HOST_LDFLAGS) -o $(PKG_BUILD_DIR)/fritz/lzma2eva $(PKG_BUILD_DIR)/fritz/src/lzma2eva.c -lz\n\t$(HOSTCC) $(HOST_CFLAGS) $(HOST_LDFLAGS) -o $(PKG_BUILD_DIR)/fritz/tichksum $(PKG_BUILD_DIR)/fritz/src/tichksum.c\n\tln -sf $(STAGING_DIR_HOST)/bin/lzma $(PKG_BUILD_DIR)/fritz\nendef\n\ndefine Build/Compile\n\t$(Build/Compile/U-Boot)\n\t(cd $(PKG_BUILD_DIR); ./fritz/fritzcreator.sh $(UBOOT_BOARD);)\nendef\n\ndefine Build/InstallDev\n\t$(INSTALL_DIR) $(STAGING_DIR_IMAGE)\n\t$(CP) $(PKG_BUILD_DIR)/$(UBOOT_IMAGE) $(STAGING_DIR_IMAGE)/$(UBOOT_IMAGE)\nendef\n\ndefine Package/u-boot/install\n\t$(Package/u-boot/install/default)\n\t$(INSTALL_BIN) $(PKG_BUILD_DIR)/upload-to-f4040.sh $(1)/\nendef\n\nUBOOT_TARGETS := fritz1200 fritz3000 fritz4040 fritz7530\n\n$(eval $(call BuildPackage/U-Boot))\n"
  },
  {
    "path": "package/boot/uboot-imx/Makefile",
    "content": "#\n# Copyright (C) 2013-2014 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_VERSION:=2022.01\nPKG_RELEASE:=$(AUTORELEASE)\n\nPKG_HASH:=81b4543227db228c03f8a1bf5ddbc813b0bb8f6555ce46064ef721a6fc680413\n\ninclude $(INCLUDE_DIR)/u-boot.mk\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine U-Boot/Default\n  BUILD_TARGET:=imx\n  UBOOT_IMAGE:=u-boot.imx\nendef\n\ndefine U-Boot/apalis_imx6\n  NAME:=Toradex Apalis\n  UBOOT_IMAGE:=SPL u-boot.img u-boot-with-spl.imx\n  UBOOT_MAKE_FLAGS:=SPL u-boot.img u-boot-with-spl.imx\n  BUILD_SUBTARGET:=cortexa9\n  BUILD_DEVICES:=toradex_apalis\nendef\n\ndefine U-Boot/mx6cuboxi\n  NAME:=SolidRun Cubox-i boards\n  UBOOT_IMAGE:=SPL u-boot-dtb.img\n  UBOOT_MAKE_FLAGS:=SPL u-boot-dtb.img\n  BUILD_SUBTARGET:=cortexa9\n  BUILD_DEVICES:=solidrun_cubox-i\nendef\n\ndefine U-Boot/wandboard\n  NAME:=Wandboard Dual Lite/Quad/Solo\n  BUILD_SUBTARGET:=cortexa9\n  BUILD_DEVICES:=wandboard_dual\nendef\n\nUBOOT_TARGETS := \\\n\tapalis_imx6 \\\n\tmx6cuboxi \\\n\twandboard\n\nUBOOT_MAKE_FLAGS += u-boot.imx\n\ndefine Build/InstallDev\n\t$(INSTALL_DIR) $(STAGING_DIR_IMAGE)\n\t$(foreach img,$(UBOOT_IMAGE), \\\n\t\t$(CP) $(PKG_BUILD_DIR)/$(img) $(STAGING_DIR_IMAGE)/$(BUILD_VARIANT)-$(img); \\\n\t)\nendef\n\n$(eval $(call BuildPackage/U-Boot))\n"
  },
  {
    "path": "package/boot/uboot-imx/patches/0001-apalis_imx6_defconfig-enable-some-useful-commands.patch",
    "content": "From 630b39c46b29de1874149c6b2c18c64966a0fabf Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Petr=20=C5=A0tetiar?= <ynezz@true.cz>\nDate: Sun, 1 Mar 2020 22:47:31 +0100\nSubject: [PATCH] apalis_imx6_defconfig: enable some useful commands\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\npartition table info, EXT4 write support, support for FAT and generic FS\ncommands like load/ls that work for multiple FS types.\n\nSigned-off-by: Petr Štetiar <ynezz@true.cz>\n---\n configs/apalis_imx6_defconfig | 5 +++++\n 1 file changed, 5 insertions(+)\n\n--- a/configs/apalis_imx6_defconfig\n+++ b/configs/apalis_imx6_defconfig\n@@ -60,6 +60,7 @@ CONFIG_CMD_CACHE=y\n CONFIG_CMD_TIME=y\n CONFIG_CMD_PMIC=y\n CONFIG_CMD_REGULATOR=y\n+CONFIG_CMD_EXT4_WRITE=y\n CONFIG_OF_CONTROL=y\n CONFIG_ENV_OVERWRITE=y\n CONFIG_ENV_IS_IN_MMC=y\n"
  },
  {
    "path": "package/boot/uboot-kirkwood/Makefile",
    "content": "#\n# Copyright (C) 2010-2014 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_VERSION:=2020.04\nPKG_RELEASE:=$(AUTORELEASE)\n\nPKG_HASH:=fe732aaf037d9cc3c0909bad8362af366ae964bbdac6913a34081ff4ad565372\n\ninclude $(INCLUDE_DIR)/u-boot.mk\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine U-Boot/Default\n  BUILD_TARGET:=kirkwood\nendef\n\ndefine U-Boot/dockstar\n  NAME:=Seagate DockStar\n  BUILD_DEVICES:=seagate_dockstar\nendef\n\ndefine U-Boot/dockstar_second_stage\n  NAME:=Seagate DockStar (second stage)\n  BUILD_DEVICES:=seagate_dockstar\nendef\n\ndefine U-Boot/goflexhome\n  NAME:=the Seagate GoFlexHome/GoFlexNet\n  BUILD_DEVICES:=seagate_goflexhome seagate_goflexnet\nendef\n\ndefine U-Boot/ib62x0\n  NAME:=RaidSonic ICY BOX NAS6210 and NAS6220\n  BUILD_DEVICES:=raidsonic_ib-nas62x0\nendef\n\ndefine U-Boot/ib62x0_second_stage\n  NAME:=RaidSonic ICY BOX NAS6210 and NAS6220 (second stage)\n  BUILD_DEVICES:=raidsonic_ib-nas62x0\nendef\n\ndefine U-Boot/iconnect\n  NAME:=Iomega iConnect Wireless\n  BUILD_DEVICES:=iom_iconnect-1.1\nendef\n\ndefine U-Boot/iconnect_second_stage\n  NAME:=Iomega iConnect Wireless (second stage)\n  BUILD_DEVICES:=iom_iconnect-1.1\nendef\n\ndefine U-Boot/l-50\n  NAME:=CheckPoint L-50\n  BUILD_DEVICES:=checkpoint_l-50\nendef\n\ndefine U-Boot/nas220\n  NAME:=Seagate Blackarmor NAS220\n  BUILD_DEVICES:=seagate_blackarmor-nas220\nendef\n\ndefine U-Boot/nsa310\n  NAME:=Zyxel NSA310\n  BUILD_DEVICES:=zyxel_nsa310b\nendef\n\ndefine U-Boot/nsa310s\n  NAME:=Zyxel NSA310S\n  BUILD_DEVICES:=zyxel_nsa310s\nendef\n\ndefine U-Boot/nsa325\n  NAME:=Zyxel NSA325v1 and v2\n  BUILD_DEVICES:=zyxel_nsa325\nendef\n\ndefine U-Boot/pogo_e02\n  NAME:=Cloud Engines Pogoplug E02\n  BUILD_DEVICES:=cloudengines_pogoe02\nendef\n\ndefine U-Boot/pogo_e02_second_stage\n  NAME:=Cloud Engines Pogoplug E02 (second stage)\n  BUILD_DEVICES:=cloudengines_pogoe02\nendef\n\ndefine U-Boot/pogoplugv4\n  NAME:=Cloud Engines Pogoplug V4\n  BUILD_DEVICES:=cloudengines_pogoplugv4\nendef\n\ndefine U-Boot/sheevaplug\n  NAME:=Globalscale SheevaPlug\n  BUILD_DEVICES:=globalscale_sheevaplug\nendef\n\nUBOOT_TARGETS := \\\n\tdockstar dockstar_second_stage \\\n\tgoflexhome \\\n\tib62x0 ib62x0_second_stage \\\n\ticonnect iconnect_second_stage \\\n\tl-50 \\\n\tnas220 \\\n\tnsa310 \\\n\tnsa310s \\\n\tnsa325 \\\n\tpogo_e02 pogo_e02_second_stage \\\n\tpogoplugv4 \\\n\tsheevaplug\n\ndefine Build/Configure\n\t$(if $(findstring _second_stage,$(BUILD_VARIANT)),\n\t\t$(CP) \\\n\t\t\t$(PKG_BUILD_DIR)/configs/$(subst _second_stage,,$(BUILD_VARIANT))_defconfig \\\n\t\t\t$(PKG_BUILD_DIR)/configs/$(BUILD_VARIANT)_defconfig\n\t\techo CONFIG_SECOND_STAGE=y >> $(PKG_BUILD_DIR)/configs/$(BUILD_VARIANT)_defconfig\n\t)\n\t+$(MAKE) $(PKG_JOBS) -C $(PKG_BUILD_DIR) \\\n\t\t$(BUILD_VARIANT)_config V=1\nendef\n\ndefine Build/Compile\n\t+$(MAKE) $(PKG_JOBS) -C $(PKG_BUILD_DIR) \\\n\t\tu-boot.kwb \\\n\t\tCROSS_COMPILE=$(TARGET_CROSS)\n\tmkimage -A $(ARCH) -O linux -T kernel -C none \\\n\t\t-a 0x600000 -e 0x600000 \\\n\t\t-n 'U-Boot uImage' \\\n\t\t-d $(PKG_BUILD_DIR)/u-boot.bin $(PKG_BUILD_DIR)/u-boot.img\nendef\n\ndefine Package/u-boot/install\n\t$(CP) \\\n\t\t$(PKG_BUILD_DIR)/u-boot.bin \\\n\t\t$(PKG_BUILD_DIR)/u-boot.kwb \\\n\t\t$(PKG_BUILD_DIR)/u-boot.img \\\n\t\t$(1)/\nendef\n\ndefine Build/InstallDev\n\t$(INSTALL_DIR) $(STAGING_DIR_HOST)/bin\n\t$(INSTALL_BIN) $(PKG_BUILD_DIR)/tools/kwboot $(STAGING_DIR_HOST)/bin/\nendef\n\n$(eval $(call BuildPackage/U-Boot))\n"
  },
  {
    "path": "package/boot/uboot-kirkwood/patches/007-nsa310-uboot-generic.patch",
    "content": "\narm: kirkwood: add ZyXEL NSA310 device\n\nThis patch add ZyXEL NSA310 1-Bay Media Server\n\nThe ZyXEL NSA310 device is a Kirkwood based NAS:\n\n- SoC: Marvell 88F6702 1200Mhz\n- SDRAM memory: 256MB DDR2 400Mhz\n- Gigabit ethernet: PHY Realtek\n- Flash memory: 128MB\n- 1 Power button\n- 1 Power LED (blue)\n- 5 Status LED (green/red)\n- 1 Copy/Sync button\n- 1 Reset button\n- 2 SATA II port (1 internal and 1 external eSata)\n- 2 USB 2.0 ports (1 front and 1 back)\n- Smart fan\n\nSigned-off-by: Alberto Bursi <alberto.bursi@outlook.it>\n\nNOTE: this patch is ready for upstream, LEDE-specific parts are in\n      another patch\n\n--- a/arch/arm/mach-kirkwood/Kconfig\n+++ b/arch/arm/mach-kirkwood/Kconfig\n@@ -53,6 +53,9 @@ config TARGET_GOFLEXHOME\n config TARGET_NAS220\n \tbool \"BlackArmor NAS220\"\n \n+config TARGET_NSA310\n+\tbool \"Zyxel NSA310 Board\"\n+\n config TARGET_NSA310S\n \tbool \"Zyxel NSA310S\"\n \n@@ -86,6 +89,7 @@ source \"board/raidsonic/ib62x0/Kconfig\"\n source \"board/Seagate/dockstar/Kconfig\"\n source \"board/Seagate/goflexhome/Kconfig\"\n source \"board/Seagate/nas220/Kconfig\"\n+source \"board/zyxel/nsa310/Kconfig\"\n source \"board/zyxel/nsa310s/Kconfig\"\n source \"board/alliedtelesis/SBx81LIFKW/Kconfig\"\n source \"board/alliedtelesis/SBx81LIFXCAT/Kconfig\"\n--- /dev/null\n+++ b/board/zyxel/nsa310/Kconfig\n@@ -0,0 +1,12 @@\n+if TARGET_NSA310\n+\n+config SYS_BOARD\n+\tdefault \"nsa310\"\n+\n+config SYS_VENDOR\n+\tdefault \"zyxel\"\n+\n+config SYS_CONFIG_NAME\n+\tdefault \"nsa310\"\n+\n+endif\n--- /dev/null\n+++ b/board/zyxel/nsa310/MAINTAINERS\n@@ -0,0 +1,6 @@\n+NSA310 BOARD\n+M:\tAlberto Bursi <alberto.bursi@outlook.it>\n+S:\tMaintained\n+F:\tboard/zyxel/nsa310/\n+F:\tinclude/configs/nsa310.h\n+F:\tconfigs/nsa310_defconfig\n--- /dev/null\n+++ b/board/zyxel/nsa310/Makefile\n@@ -0,0 +1,12 @@\n+#\n+# (C) Copyright 2015 bodhi <mibodhi@gmail.com>\n+#\n+# Based on\n+# (C) Copyright 2009\n+# Marvell Semiconductor <www.marvell.com>\n+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>\n+#\n+# SPDX-License-Identifier:\tGPL-2.0+\n+#\n+\n+obj-y\t:= nsa310.o\n--- /dev/null\n+++ b/board/zyxel/nsa310/kwbimage.cfg\n@@ -0,0 +1,166 @@\n+#\n+# Copyright (C) 2013  Rafal Kazmierowski\n+#\n+# Based on guruplug.c originally written by\n+# Siddarth Gore <gores@marvell.com>\n+# (C) Copyright 2009\n+# Marvell Semiconductor <www.marvell.com>\n+#\n+# See file CREDITS for list of people who contributed to this\n+# project.\n+#\n+# This program is free software; you can redistribute it and/or\n+# modify it under the terms of the GNU General Public License as\n+# published by the Free Software Foundation; either version 2 of\n+# the License, or (at your option) any later version.\n+#\n+# This program is distributed in the hope that it will be useful,\n+# but WITHOUT ANY WARRANTY; without even the implied warranty of\n+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n+# GNU General Public License for more details.\n+#\n+# You should have received a copy of the GNU General Public License\n+# along with this program; if not, write to the Free Software\n+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,\n+# MA 02110-1301 USA\n+#\n+# Refer docs/README.kwimage for more details about how-to configure\n+# and create kirkwood boot image\n+#\n+\n+# Boot Media configurations\n+BOOT_FROM\tnand\n+#BOOT_FROM\tuart\n+NAND_ECC_MODE\tdefault\n+NAND_PAGE_SIZE\t0x0800\n+\n+# SOC registers configuration using bootrom header extension\n+# Maximum KWBIMAGE_MAX_CONFIG configurations allowed\n+\n+# Configure RGMII-0 interface pad voltage to 1.8V\n+DATA 0xFFD100e0 0x1b1b1b9b\n+\n+#Dram initalization for SINGLE x16 CL=5 @ 400MHz\n+DATA 0xFFD01400 0x43010c30\t# DDR Configuration register\n+# bit13-0:  0xc30 (3120 DDR2 clks refresh rate)\n+# bit23-14: zero\n+# bit24: 1= enable exit self refresh mode on DDR access\n+# bit25: 1 required\n+# bit29-26: zero\n+# bit31-30: 01\n+\n+DATA 0xFFD01404 0x37543000\t# DDR Controller Control Low\n+# bit 4:    0=addr/cmd in smame cycle\n+# bit 5:    0=clk is driven during self refresh, we don't care for APX\n+# bit 6:    0=use recommended falling edge of clk for addr/cmd\n+# bit14:    0=input buffer always powered up\n+# bit18:    1=cpu lock transaction enabled\n+# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0\n+# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM\n+# bit30-28: 3 required\n+# bit31:    0=no additional STARTBURST delay\n+\n+DATA 0xFFD01408 0x22125451\t# DDR Timing (Low) (active cycles value +1)\n+# bit3-0:   TRAS lsbs\n+# bit7-4:   TRCD\n+# bit11- 8: TRP\n+# bit15-12: TWR\n+# bit19-16: TWTR\n+# bit20:    TRAS msb\n+# bit23-21: 0x0\n+# bit27-24: TRRD\n+# bit31-28: TRTP\n+\n+DATA 0xFFD0140C 0x00000a33\t#  DDR Timing (High)\n+# bit6-0:   TRFC\n+# bit8-7:   TR2R\n+# bit10-9:  TR2W\n+# bit12-11: TW2W\n+# bit31-13: zero required\n+\n+DATA 0xFFD01410 0x0000000c\t#  DDR Address Control\n+# bit1-0:   01, Cs0width=x8\n+# bit3-2:   10, Cs0size=1Gb\n+# bit5-4:   01, Cs1width=x8\n+# bit7-6:   10, Cs1size=1Gb\n+# bit9-8:   00, Cs2width=nonexistent\n+# bit11-10: 00, Cs2size =nonexistent\n+# bit13-12: 00, Cs3width=nonexistent\n+# bit15-14: 00, Cs3size =nonexistent\n+# bit16:    0,  Cs0AddrSel\n+# bit17:    0,  Cs1AddrSel\n+# bit18:    0,  Cs2AddrSel\n+# bit19:    0,  Cs3AddrSel\n+# bit31-20: 0 required\n+\n+DATA 0xFFD01414 0x00000000\t#  DDR Open Pages Control\n+# bit0:    0,  OpenPage enabled\n+# bit31-1: 0 required\n+\n+DATA 0xFFD01418 0x00000000\t#  DDR Operation\n+# bit3-0:   0x0, DDR cmd\n+# bit31-4:  0 required\n+\n+DATA 0xFFD0141C 0x00000652\t#  DDR Mode\n+# bit2-0:   2, BurstLen=2 required\n+# bit3:     0, BurstType=0 required\n+# bit6-4:   4, CL=5\n+# bit7:     0, TestMode=0 normal\n+# bit8:     0, DLL reset=0 normal\n+# bit11-9:  6, auto-precharge write recovery ????????????\n+# bit12:    0, PD must be zero\n+# bit31-13: 0 required\n+\n+DATA 0xFFD01420 0x00000004\t#  DDR Extended Mode\n+# bit0:    0,  DDR DLL enabled\n+# bit1:    0,  DDR drive strenght normal\n+# bit2:    0,  DDR ODT control lsd (disabled)\n+# bit5-3:  000, required\n+# bit6:    1,  DDR ODT control msb, (disabled)\n+# bit9-7:  000, required\n+# bit10:   0,  differential DQS enabled\n+# bit11:   0, required\n+# bit12:   0, DDR output buffer enabled\n+# bit31-13: 0 required\n+\n+DATA 0xFFD01424 0x0000F17F\t#  DDR Controller Control High\n+# bit2-0:  111, required\n+# bit3  :  1  , MBUS Burst Chop disabled\n+# bit6-4:  111, required\n+# bit7  :  0\n+# bit8  :  1  , add writepath sample stage, must be 1 for DDR freq >= 300MHz\n+# bit9  :  0  , no half clock cycle addition to dataout\n+# bit10 :  0  , 1/4 clock cycle skew enabled for addr/ctl signals\n+# bit11 :  0  , 1/4 clock cycle skew disabled for write mesh\n+# bit15-12: 1111 required\n+# bit31-16: 0    required\n+\n+DATA 0xFFD01428 0x00085520\t# DDR2 ODT Read Timing (default values)\n+DATA 0xFFD0147C 0x00008552\t# DDR2 ODT Write Timing (default values)\n+\n+\n+DATA 0xFFD01504 0x0FFFFFF1\t# CS[0]n Size\n+#DATA 0xFFD01500 0x00000000\t# CS[0]n Base address to 0x0\n+# bit0:    1,  Window enabled\n+# bit1:    0,  Write Protect disabled\n+# bit3-2:  00, CS0 hit selected\n+# bit23-4: ones, required\n+# bit31-24: 0x0F, Size (i.e. 256MB)\n+\n+DATA 0xFFD01508 0x10000000\t# CS[1]n Base address to 256Mb\n+DATA 0xFFD0150C 0x00000000\t# CS[2]n Size, window disabled        KAZ z 400db\n+DATA 0xFFD01514 0x00000000\t# CS[3]n Size, window disabled\n+\n+DATA 0xFFD0151C 0x00000000\t#  DDR ODT Control (Low)\n+DATA 0xFFD01494 0x00120012\t#  DDR ODT Control (High)              KAZ  z nowy  STATIC_SDRAM_ODT_CTRL_LOW\n+# bit1-0:  00, ODT0 controlled by ODT Control (low) register above\n+# bit3-2:  01, ODT1 active NEVER!\n+# bit31-4: zero, required\n+\n+DATA 0xFFD01498 0x00000000\t# CPU ODT Control                     KAZ STATIC_SDRAM_ODT_CTRL_HI\n+DATA 0xFFD0149C 0x0000E403\t# DDR Initialization Control          KAZ STATIC_SDRAM_DUNIT_ODT_CTRL\n+DATA 0xFFD01480 0x00000001\t# DDR Initialization Control\n+#bit0=1, enable DDR init upon this register write\n+\n+# End of Header extension\n+DATA 0x0 0x0\n--- /dev/null\n+++ b/board/zyxel/nsa310/nsa310.c\n@@ -0,0 +1,190 @@\n+/*\n+ * Copyright (C) 2013 Rafal Kazmierowski\n+ *\n+ * Based on NSA320.c Peter Schildmann <linux@schildmann.info>\n+ * originally written by\n+ * Marvell Semiconductor <www.marvell.com>\n+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>\n+ *\n+ * See file CREDITS for list of people who contributed to this\n+ * project.\n+ *\n+ * This program is free software; you can redistribute it and/or\n+ * modify it under the terms of the GNU General Public License as\n+ * published by the Free Software Foundation; either version 2 of\n+ * the License, or (at your option) any later version.\n+ *\n+ * This program is distributed in the hope that it will be useful,\n+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\n+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n+ * GNU General Public License for more details.\n+ *\n+ * You should have received a copy of the GNU General Public License\n+ * along with this program; if not, write to the Free Software\n+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,\n+ * MA 02110-1301 USA\n+ */\n+\n+#include <common.h>\n+#include <miiphy.h>\n+#include <asm/arch/cpu.h>\n+#include <asm/arch/soc.h>\n+#include <asm/arch/mpp.h>\n+#include <asm/io.h>\n+#include \"nsa310.h\"\n+\n+DECLARE_GLOBAL_DATA_PTR;\n+\n+int board_early_init_f(void)\n+{\n+\t/*\n+\t * default gpio configuration\n+\t * There are maximum 64 gpios controlled through 2 sets of registers\n+\t * the below configuration configures mainly initial LED status\n+\t */\n+\tmvebu_config_gpio(NSA310_VAL_LOW, NSA310_VAL_HIGH,\n+\t\t       NSA310_OE_LOW, NSA310_OE_HIGH);\n+\n+\t/* Multi-Purpose Pins Functionality configuration */\n+\t/* (all LEDs & power off active high) */\n+\tstatic const u32 kwmpp_config[] = {\n+\t\tMPP0_NF_IO2,\n+\t\tMPP1_NF_IO3,\n+\t\tMPP2_NF_IO4,\n+\t\tMPP3_NF_IO5,\n+\t\tMPP4_NF_IO6,\n+\t\tMPP5_NF_IO7,\n+\t\tMPP6_SYSRST_OUTn,\n+\t\tMPP7_GPO,\n+\t\tMPP8_TW_SDA,\t/* PCF8563 RTC chip   */\n+\t\tMPP9_TW_SCK,\t/* connected to TWSI  */\n+\t\tMPP10_UART0_TXD,\n+\t\tMPP11_UART0_RXD,\n+\t\tMPP12_GPO,\t\t/* SATA2 LED (green)  */\n+\t\tMPP13_GPIO,\t\t/* SATA2 LED (red)    */\n+\t\tMPP14_GPIO,\t\t/* MCU DATA pin (in)  */\n+\t\tMPP15_GPIO,\t\t/* USB LED (green)    */\n+\t\tMPP16_GPIO,\t\t/* MCU CLK pin (out)  */\n+\t\tMPP17_GPIO,\t\t/* MCU ACT pin (out)  */\n+\t\tMPP18_NF_IO0,\n+\t\tMPP19_NF_IO1,\n+\t\tMPP20_GPIO,\n+\t\tMPP21_GPIO,\t\t/* USB LED (red)-Power*/\n+\t\tMPP22_GPIO,\n+\t\tMPP23_GPIO,\n+\t\tMPP24_GPIO,\n+\t\tMPP25_GPIO,\n+\t\tMPP26_GPIO,\n+\t\tMPP27_GPIO,\n+\t\tMPP28_GPIO,\t\t/* SYS LED (green)    */\n+\t\tMPP29_GPIO,\t\t/* SYS LED (red)      */\n+\t\tMPP30_GPIO,\n+\t\tMPP31_GPIO,\n+\t\tMPP32_GPIO,\n+\t\tMPP33_GPIO,\n+\t\tMPP34_GPIO,\n+\t\tMPP35_GPIO,\n+\t\tMPP36_GPIO,\t\t/* Reset button       */\n+\t\tMPP37_GPIO,\t\t/* Copy button        */\n+\t\tMPP38_GPIO,\t\t/* VID B0             */\n+\t\tMPP39_GPIO,\t\t/* COPY LED (green)   */\n+\t\tMPP40_GPIO,\t\t/* COPY LED (red)     */\n+\t\tMPP41_GPIO,\t\t/* SATA1 LED (green)  */\n+\t\tMPP42_GPIO,\t\t/* SATA1 LED (red)    */\n+\t\tMPP43_GPIO,\t\t/* HTP pin            */\n+\t\tMPP44_GPIO,\t\t/* Buzzer             */\n+\t\tMPP45_GPIO,\t\t/* VID B1             */\n+\t\tMPP46_GPIO,\t\t/* Power button       */\n+\t\tMPP47_GPIO,\t\t/* Power resume data  */\n+\t\tMPP48_GPIO,\t\t/* Power off          */\n+\t\tMPP49_GPIO,\t\t/* Power resume clock */\n+\t\t0\n+\t};\n+\tkirkwood_mpp_conf(kwmpp_config,NULL);\n+\treturn 0;\n+}\n+\n+int board_init(void)\n+{\n+\t/* address of boot parameters */\n+\tgd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;\n+\n+\treturn 0;\n+}\n+\n+#ifdef CONFIG_RESET_PHY_R\n+/* Configure and enable MV88E1318 PHY */\n+void reset_phy(void)\n+{\n+\tu16 reg;\n+\tu16 devadr;\n+\tchar *name = \"egiga0\";\n+\n+\tif (miiphy_set_current_dev(name))\n+\t\treturn;\n+\n+\t/* command to read PHY dev address */\n+\tif (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {\n+\t\tprintf(\"Err..%s could not read PHY dev address\\n\",\n+\t\t\t__FUNCTION__);\n+\t\treturn;\n+\t}\n+\n+\t/* Set RGMII delay */\n+\tmiiphy_write(name, devadr, MV88E1318_PGADR_REG, 2);\n+\tmiiphy_read(name, devadr, MV88E1318_MAC_CTRL_REG, &reg);\n+\treg |= (MV88E1318_RGMII_RXTM_CTRL | MV88E1318_RGMII_TXTM_CTRL);\n+\tmiiphy_write(name, devadr, MV88E1318_MAC_CTRL_REG, reg);\n+\tmiiphy_write(name, devadr, MV88E1318_PGADR_REG, 0);\n+\n+\t/* reset the phy */\n+\tmiiphy_reset(name, devadr);\n+\n+\tprintf(\"MV88E1318 PHY initialized on %s\\n\", name);\n+}\n+#endif /* CONFIG_RESET_PHY_R */\n+\n+#ifdef CONFIG_SHOW_BOOT_PROGRESS\n+void show_boot_progress(int val)\n+{\n+\tstruct kwgpio_registers *gpio0 = (struct kwgpio_registers *)MVEBU_GPIO0_BASE;\n+\tu32 dout0 = readl(&gpio0->dout);\n+\tu32 blen0 = readl(&gpio0->blink_en);\n+\n+\tstruct kwgpio_registers *gpio1 = (struct kwgpio_registers *)MVEBU_GPIO1_BASE;\n+\tu32 dout1 = readl(&gpio1->dout);\n+\tu32 blen1 = readl(&gpio1->blink_en);\n+\n+\tswitch (val) {\n+\tcase BOOTSTAGE_ID_DECOMP_IMAGE:\n+\t\twritel(blen0 & ~(SYS_GREEN_LED | SYS_RED_LED), &gpio0->blink_en);\n+\t\twritel((dout0 & ~SYS_GREEN_LED) | SYS_RED_LED, &gpio0->dout);\n+\t\tbreak;\n+\tcase BOOTSTAGE_ID_RUN_OS:\n+\t\twritel(dout0 & ~SYS_RED_LED, &gpio0->dout);\n+\t\twritel(blen0 | SYS_GREEN_LED, &gpio0->blink_en);\n+\t\tbreak;\n+\tcase BOOTSTAGE_ID_NET_START:\n+\t\twritel(dout1 & ~COPY_RED_LED, &gpio1->dout);\n+\t\twritel((blen1 & ~COPY_RED_LED) | COPY_GREEN_LED, &gpio1->blink_en);\n+\t\tbreak;\n+\tcase BOOTSTAGE_ID_NET_LOADED:\n+\t\twritel(blen1 & ~(COPY_RED_LED | COPY_GREEN_LED), &gpio1->blink_en);\n+\t\twritel((dout1 & ~COPY_RED_LED) | COPY_GREEN_LED, &gpio1->dout);\n+\t\tbreak;\n+\tcase -BOOTSTAGE_ID_NET_NETLOOP_OK:\n+\tcase -BOOTSTAGE_ID_NET_LOADED:\n+\t\twritel(dout1 & ~COPY_GREEN_LED, &gpio1->dout);\n+\t\twritel((blen1 & ~COPY_GREEN_LED) | COPY_RED_LED, &gpio1->blink_en);\n+\t\tbreak;\n+\tdefault:\n+\t\tif (val < 0) {\n+\t\t\t/* error */\n+\t\t\tprintf(\"Error occured, error code = %d\\n\", -val);\n+\t\t\twritel(dout0 & ~SYS_GREEN_LED, &gpio0->dout);\n+\t\t\twritel(blen0 | SYS_RED_LED, &gpio0->blink_en);\n+\t\t}\n+\t\tbreak;\n+\t}\n+}\n+#endif\n--- /dev/null\n+++ b/board/zyxel/nsa310/nsa310.h\n@@ -0,0 +1,56 @@\n+/*\n+ * Copyright (C) 2013 Rafal Kazmierowski\n+ *\n+ * Based on Peter Schildmann <linux@schildmann.info>\n+ * and  guruplug.h originally written by\n+ * Siddarth Gore <gores@marvell.com>\n+ * (C) Copyright 2009\n+ * Marvell Semiconductor <www.marvell.com>\n+ *\n+ * See file CREDITS for list of people who contributed to this\n+ * project.\n+ *\n+ * This program is free software; you can redistribute it and/or\n+ * modify it under the terms of the GNU General Public License as\n+ * published by the Free Software Foundation; either version 2 of\n+ * the License, or (at your option) any later version.\n+ *\n+ * This program is distributed in the hope that it will be useful,\n+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\n+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n+ * GNU General Public License for more details.\n+ *\n+ * You should have received a copy of the GNU General Public License\n+ * along with this program; if not, write to the Free Software\n+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,\n+ * MA 02110-1301 USA\n+ */\n+\n+#ifndef __NSA310_H\n+#define __NSA310_H\n+\n+/* GPIO's */\n+#define SYS_GREEN_LED\t\t(1 << 28)\n+#define SYS_RED_LED\t\t(1 << 29)\n+#define SATA1_GREEN_LED\t\t(1ULL << 41)\n+#define SATA1_RED_LED\t\t(1ULL << 42)\n+#define SATA2_GREEN_LED\t\t(1 << 12)\n+#define SATA2_RED_LED\t\t(1 << 13)\n+#define USB_GREEN_LED\t\t(1 << 15)\n+#define USB_RED_LED\t\t(1 << 21)\n+#define COPY_GREEN_LED\t\t(1ULL << 39)\n+#define COPY_RED_LED\t\t(1ULL << 40)\n+\n+#define NSA310_OE_LOW   (0)\n+#define NSA310_VAL_LOW    (SYS_GREEN_LED)\n+#define NSA310_OE_HIGH\t\t(((COPY_GREEN_LED | COPY_RED_LED | \\\n+                                   SATA1_GREEN_LED | SATA1_RED_LED)) >> 32UL)\n+#define NSA310_VAL_HIGH\t\t(0)\n+\n+/* PHY related */\n+#define MV88E1318_MAC_CTRL_REG\t\t21\n+#define MV88E1318_PGADR_REG\t\t22\n+#define MV88E1318_RGMII_TXTM_CTRL\t(1 << 4)\n+#define MV88E1318_RGMII_RXTM_CTRL\t(1 << 5)\n+\n+#endif /* __NSA310_H */\n--- /dev/null\n+++ b/configs/nsa310_defconfig\n@@ -0,0 +1,48 @@\n+CONFIG_ARM=y\n+CONFIG_SYS_DCACHE_OFF=y\n+CONFIG_ARCH_CPU_INIT=y\n+CONFIG_KIRKWOOD=y\n+CONFIG_SYS_TEXT_BASE=0x600000\n+CONFIG_TARGET_NSA310=y\n+CONFIG_IDENT_STRING=\"\\nZyXEL NSA310 1-Bay Power Media Server\"\n+CONFIG_NR_DRAM_BANKS=2\n+CONFIG_BOOTDELAY=3\n+CONFIG_SYS_PROMPT=\"NSA310> \"\n+# CONFIG_CMD_IMLS is not set\n+# CONFIG_CMD_FLASH is not set\n+CONFIG_MVGBE=y\n+CONFIG_MII=y\n+CONFIG_SYS_NS16550=y\n+CONFIG_CMD_FDT=y\n+CONFIG_OF_LIBFDT=y\n+CONFIG_CMD_SETEXPR=y\n+CONFIG_CMD_DHCP=y\n+CONFIG_CMD_MII=y\n+CONFIG_CMD_PING=y\n+CONFIG_CMD_DNS=y\n+CONFIG_CMD_SNTP=y\n+CONFIG_CMD_USB=y\n+CONFIG_CMD_DATE=y\n+CONFIG_CMD_EXT2=y\n+CONFIG_CMD_EXT4=y\n+CONFIG_CMD_FAT=y\n+CONFIG_CMD_JFFS2=y\n+CONFIG_MTD=y\n+CONFIG_MTD_RAW_NAND=y\n+CONFIG_MTDPARTS_DEFAULT=\"mtdparts=orion_nand:0x0c0000(uboot),0x80000(uboot_env),0x7ec0000(ubi)\"\n+CONFIG_CMD_MTDPARTS=y\n+CONFIG_CMD_ENV=y\n+CONFIG_CMD_NAND=y\n+CONFIG_EFI_PARTITION=y\n+CONFIG_ENV_IS_IN_NAND=y\n+CONFIG_ENV_SIZE=0x20000\n+CONFIG_ENV_OFFSET=0xC0000\n+CONFIG_ENV_SECT_SIZE=0x20000\n+CONFIG_ENV_ADDR=0xC0000\n+CONFIG_CMD_UBI=y\n+CONFIG_USB=y\n+CONFIG_USB_EHCI_HCD=y\n+CONFIG_USB_STORAGE=y\n+CONFIG_LZMA=y\n+CONFIG_LZO=y\n+CONFIG_SYS_LONGHELP=y\n--- /dev/null\n+++ b/include/configs/nsa310.h\n@@ -0,0 +1,103 @@\n+/* Copyright (C) 2015-2016 bodhi <mibodhi@gmail.com>\n+ *\n+ * Based on\n+ * Copyright (C) 2012  Peter Schildmann <linux@schildmann.info>\n+ *\n+ * Based on guruplug.h originally written by\n+ * Siddarth Gore <gores@marvell.com>\n+ * (C) Copyright 2009\n+ * Marvell Semiconductor <www.marvell.com>\n+ *\n+ * See file CREDITS for list of people who contributed to this\n+ * project.\n+ *\n+ * This program is free software; you can redistribute it and/or\n+ * modify it under the terms of the GNU General Public License as\n+ * published by the Free Software Foundation; either version 2 of\n+ * the License, or (at your option) any later version.\n+ *\n+ * This program is distributed in the hope that it will be useful,\n+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\n+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n+ * GNU General Public License for more details.\n+ *\n+ * You should have received a copy of the GNU General Public License\n+ * along with this program; if not, write to the Free Software\n+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,\n+ * MA 02110-1301 USA\n+ */\n+\n+#ifndef _CONFIG_NSA310_H\n+#define _CONFIG_NSA310_H\n+\n+/*\n+ * High Level Configuration Options (easy to change)\n+ */\n+#define CONFIG_FEROCEON_88FR131\t\t/* CPU Core subversion */\n+#define CONFIG_KW88F6281\t\t/* SOC Name */\n+\n+#define CONFIG_SKIP_LOWLEVEL_INIT\t/* disable board lowlevel_init */\n+\n+/*\n+ * Misc Configuration Options\n+ */\n+#define CONFIG_SHOW_BOOT_PROGRESS 1     /* boot progess display (LED's) */\n+\n+/*\n+ * Commands configuration\n+ */\n+#define CONFIG_PREBOOT\n+\n+/*\n+ * mv-common.h should be defined after CMD configs since it used them\n+ * to enable certain macros\n+ */\n+#include \"mv-common.h\"\n+\n+/*\n+ * Default environment variables\n+ */\n+#define CONFIG_BOOTCOMMAND \\\n+\t\"ubi part ubi; \" \\\n+\t\"ubi read 0x800000 kernel; \" \\\n+\t\"bootm 0x800000\"\n+\n+#define CONFIG_EXTRA_ENV_SETTINGS \\\n+\t\"console=console=ttyS0,115200\\0\"\t\\\n+\t\"mtdids=nand0=orion_nand\\0\"\t\t\\\n+\t\"mtdparts=\"CONFIG_MTDPARTS_DEFAULT \"\\0\"\t\\\n+\t\"bootargs_root=\\0\"\n+\n+/*\n+ * Ethernet Driver configuration\n+ */\n+#ifdef CONFIG_CMD_NET\n+#define CONFIG_NETCONSOLE\n+#define CONFIG_NET_MULTI\n+#define CONFIG_MVGBE_PORTS\t\t{1, 0}\t/* enable port 0 only */\n+#define CONFIG_PHY_BASE_ADR\t\t0x1\n+#define CONFIG_RESET_PHY_R\n+#endif /* CONFIG_CMD_NET */\n+\n+/*\n+ * SATA Driver configuration\n+ */\n+#ifdef CONFIG_MVSATA_IDE\n+#define CONFIG_SYS_ATA_IDE0_OFFSET      MV_SATA_PORT0_OFFSET\n+#define CONFIG_SYS_ATA_IDE1_OFFSET      MV_SATA_PORT1_OFFSET\n+#endif /* CONFIG_MVSATA_IDE */\n+\n+/*\n+ * File system\n+ */\n+#define CONFIG_JFFS2_NAND\n+#define CONFIG_JFFS2_LZO\n+\n+/*\n+ *  Date Time\n+ */\n+#ifdef CONFIG_CMD_DATE\n+#define CONFIG_RTC_MV\n+#endif /* CONFIG_CMD_DATE */\n+\n+#endif /* _CONFIG_NSA310_H */\n"
  },
  {
    "path": "package/boot/uboot-kirkwood/patches/008-nsa325-uboot-generic.patch",
    "content": "--- a/arch/arm/mach-kirkwood/Kconfig\n+++ b/arch/arm/mach-kirkwood/Kconfig\n@@ -68,6 +68,9 @@ config TARGET_SBx81LIFXCAT\n config TARGET_DB_88F6281_BP\n \tbool \"Marvell DB-88F6281-BP\"\n \n+config TARGET_NSA325\n+\tbool \"Zyxel NSA325 board\"\n+\n endchoice\n \n config SYS_SOC\n@@ -91,6 +94,7 @@ source \"board/Seagate/goflexhome/Kconfig\n source \"board/Seagate/nas220/Kconfig\"\n source \"board/zyxel/nsa310/Kconfig\"\n source \"board/zyxel/nsa310s/Kconfig\"\n+source \"board/zyxel/nsa325/Kconfig\"\n source \"board/alliedtelesis/SBx81LIFKW/Kconfig\"\n source \"board/alliedtelesis/SBx81LIFXCAT/Kconfig\"\n source \"board/Marvell/db-88f6281-bp/Kconfig\"\n--- /dev/null\n+++ b/board/zyxel/nsa325/Kconfig\n@@ -0,0 +1,12 @@\n+if TARGET_NSA325\n+\n+config SYS_BOARD\n+\tdefault \"nsa325\"\n+\n+config SYS_VENDOR\n+\tdefault \"zyxel\"\n+\n+config SYS_CONFIG_NAME\n+\tdefault \"nsa325\"\n+\n+endif\n--- /dev/null\n+++ b/board/zyxel/nsa325/MAINTAINERS\n@@ -0,0 +1,6 @@\n+NSA325 BOARD\n+M:\tAlberto Bursi <alberto.bursi@outlook.it>\n+S:\tMaintained\n+F:\tboard/zyxel/nsa325/\n+F:\tinclude/configs/nsa325.h\n+F:\tconfigs/nsa325_defconfig\n--- /dev/null\n+++ b/board/zyxel/nsa325/Makefile\n@@ -0,0 +1,13 @@\n+#\n+# (C) Copyright 2015 bodhi <mibodhi@gmail.com>\n+#\n+# Based on\n+# (C) Copyright 2009\n+# Marvell Semiconductor <www.marvell.com>\n+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>\n+#\n+# SPDX-License-Identifier:\tGPL-2.0+\n+#\n+\n+obj-y\t:= nsa325.o\n+\n--- /dev/null\n+++ b/board/zyxel/nsa325/kwbimage.cfg\n@@ -0,0 +1,78 @@\n+# Copyright (C) 2015 bodhi <mibodhi@gmail.com>\n+#\n+# Extracted from Zyxel GPL source for u-boot-1.1.4_NSA325v2\n+#\n+# See file CREDITS for list of people who contributed to this\n+# project.\n+#\n+# This program is free software; you can redistribute it and/or\n+# modify it under the terms of the GNU General Public License as\n+# published by the Free Software Foundation; either version 2 of\n+# the License, or (at your option) any later version.\n+#\n+# This program is distributed in the hope that it will be useful,\n+# but WITHOUT ANY WARRANTY; without even the implied warranty of\n+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n+# GNU General Public License for more details.\n+#\n+# You should have received a copy of the GNU General Public License\n+# along with this program; if not, write to the Free Software\n+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,\n+# MA 02110-1301 USA\n+#\n+# Refer docs/README.kwimage for more details about how-to configure\n+# and create kirkwood boot image\n+#\n+\n+# Boot Media configurations\n+#BOOT_FROM\tuart\n+BOOT_FROM       nand\n+NAND_ECC_MODE   default\n+NAND_PAGE_SIZE  0x0800\n+\n+# SOC registers configuration using bootrom header extension\n+# Maximum KWBIMAGE_MAX_CONFIG configurations allowed\n+\n+# Configure RGMII-0 interface pad voltage to 1.8V\n+DATA 0xFFD100e0 0x1b1b1b9b\n+\n+#Dram initalization\n+DATA 0xFFD01400 0x4301503E      # DDR Configuration register\n+DATA 0xFFD01404 0xB9843000      # DDR Controller Control Low\n+DATA 0xFFD01408 0x33137777      # DDR Timing (Low)\n+DATA 0xFFD0140C 0x16000C55      # DDR Timing (High)\n+DATA 0xFFD01410 0x04000000      # DDR Address Control\n+DATA 0xFFD01414 0x00000000\t#  DDR Open Pages Control\n+DATA 0xFFD01418 0x00000000\t#  DDR Operation\n+DATA 0xFFD0141C 0x00000672\t#  DDR Mode\n+DATA 0xFFD01420 0x00000004\t#  DDR Extended Mode\n+DATA 0xFFD01424 0x0000F14F\t#  DDR Controller Control High\n+DATA 0xFFD01428 0x000D6720\t# DDR3 ODT Read Timing\n+DATA 0xFFD0147C 0x0000B571\t# DDR2 ODT Write Timing\n+DATA 0xFFD01504 0x1FFFFFF1      # CS[0]n Size\n+DATA 0xFFD01508 0x20000000      # CS[1]n Base address to 512Mb\n+DATA 0xFFD0150C 0x1FFFFFF4      # CS[1]n Size 512Mb Window enabled for CS1\n+DATA 0xFFD01514 0x00000000      # CS[2]n Size, window disabled\n+DATA 0xFFD0151C 0x00000000      # CS[3]n Size, window disabled\n+DATA 0xFFD01494 0x00120000      #  DDR ODT Control (Low)\n+DATA 0xFFD01498 0x00000000      #  DDR ODT Control (High)\n+DATA 0xFFD0149C 0x0000E803      # CPU ODT Control\n+\n+DATA 0xFFD015D0 0x00000630\n+DATA 0xFFD015D4 0x00000046\n+DATA 0xFFD015D8 0x00000008\n+DATA 0xFFD015DC 0x00000000\n+DATA 0xFFD015E0 0x00000023\n+DATA 0xFFD015E4 0x00203C18\n+DATA 0xFFD01620 0x00384800\n+DATA 0xFFD01480 0x00000001\n+DATA 0xFFD20134 0x66666666\n+DATA 0xFFD20138 0x00066666\n+\n+#Disable nsa325 hardware watchdog to allow successful kwbooting\n+DATA 0xFFD10100 0x00004000 # set GPIO 14 to high to disable the watchdog\n+DATA 0xFFD10104 0xFFFFBFFF # set GPIO 14 to output (to block any other input to it)\n+\n+# End of Header extension\n+DATA 0x0 0x0\n+\n--- /dev/null\n+++ b/board/zyxel/nsa325/nsa325.c\n@@ -0,0 +1,265 @@\n+/*\n+ * Copyright (C) 2015 bodhi <mibodhi@gmail.com>\n+ *\n+ * Based on\n+ * Copyright (C) 2014  Jason Plum <jplum@archlinuxarm.org>\n+ *\n+ * Based on nsa320.c originall written by\n+ * Copyright (C) 2012  Peter Schildmann <linux@schildmann.info>\n+ *\n+ * Based on guruplug.c originally written by\n+ * Siddarth Gore <gores@marvell.com>\n+ * (C) Copyright 2009\n+ * Marvell Semiconductor <www.marvell.com>\n+ *\n+ * See file CREDITS for list of people who contributed to this\n+ * project.\n+ *\n+ * This program is free software; you can redistribute it and/or\n+ * modify it under the terms of the GNU General Public License as\n+ * published by the Free Software Foundation; either version 2 of\n+ * the License, or (at your option) any later version.\n+ *\n+ * This program is distributed in the hope that it will be useful,\n+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\n+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n+ * GNU General Public License for more details.\n+ *\n+ * You should have received a copy of the GNU General Public License\n+ * along with this program; if not, write to the Free Software\n+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,\n+ * MA 02110-1301 USA\n+ */\n+\n+#include <common.h>\n+#include <miiphy.h>\n+#include <asm/arch/soc.h>\n+#include <asm/arch/mpp.h>\n+#include <asm/arch/cpu.h>\n+#include <asm/gpio.h>\n+#include <asm/io.h>\n+#include \"nsa325.h\"\n+#include <asm/arch/gpio.h>\n+\n+DECLARE_GLOBAL_DATA_PTR;\n+\n+int board_early_init_f(void)\n+{\n+\t/*\n+\t * default gpio configuration\n+\t * There are maximum 64 gpios controlled through 2 sets of registers\n+\t * the below configuration configures mainly initial LED status\n+\t */\n+\tmvebu_config_gpio(NSA325_VAL_LOW, NSA325_VAL_HIGH,\n+\t\t       NSA325_OE_LOW, NSA325_OE_HIGH);\n+\n+\t/* Multi-Purpose Pins Functionality configuration */\n+\t/* (all LEDs & power off active high) */\n+\tu32 kwmpp_config[] = {\n+\t\tMPP0_NF_IO2,\n+\t\tMPP1_NF_IO3,\n+\t\tMPP2_NF_IO4,\n+\t\tMPP3_NF_IO5,\n+\t\tMPP4_NF_IO6,\n+\t\tMPP5_NF_IO7,\n+\t\tMPP6_SYSRST_OUTn,\n+\t\tMPP7_GPO,\n+\t\tMPP8_TW_SDA,\t\t/* PCF8563 RTC chip   */\n+\t\tMPP9_TW_SCK,\t\t/* connected to TWSI  */\n+\t\tMPP10_UART0_TXD,\n+\t\tMPP11_UART0_RXD,\n+\t\tMPP12_GPO,\t\t/* HDD2 LED (green)   */\n+\t\tMPP13_GPIO,\t\t/* HDD2 LED (red)     */\n+\t\tMPP14_GPIO,\t\t/* MCU DATA pin (in)  */\n+\t\tMPP15_GPIO,\t\t/* USB LED (green)    */\n+\t\tMPP16_GPIO,\t\t/* MCU CLK pin (out)  */\n+\t\tMPP17_GPIO,\t\t/* MCU ACT pin (out)  */\n+\t\tMPP18_NF_IO0,\n+\t\tMPP19_NF_IO1,\n+\t\tMPP20_GPIO,\n+\t\tMPP21_GPIO,\t\t/* USB power          */\n+\t\tMPP22_GPIO,\n+\t\tMPP23_GPIO,\n+\t\tMPP24_GPIO,\n+\t\tMPP25_GPIO,\n+\t\tMPP26_GPIO,\n+\t\tMPP27_GPIO,\n+\t\tMPP28_GPIO,\t\t/* SYS LED (green)    */\n+\t\tMPP29_GPIO,\t\t/* SYS LED (orange)   */\n+\t\tMPP30_GPIO,\n+\t\tMPP31_GPIO,\n+\t\tMPP32_GPIO,\n+\t\tMPP33_GPIO,\n+\t\tMPP34_GPIO,\n+\t\tMPP35_GPIO,\n+\t\tMPP36_GPIO,\t\t/* reset button       */\n+\t\tMPP37_GPIO,\t\t/* copy button        */\n+\t\tMPP38_GPIO,\t\t/* VID B0             */\n+\t\tMPP39_GPIO,\t\t/* COPY LED (green)   */\n+\t\tMPP40_GPIO,\t\t/* COPY LED (red)     */\n+\t\tMPP41_GPIO,\t\t/* HDD1 LED (green)   */\n+\t\tMPP42_GPIO,\t\t/* HDD1 LED (red)     */\n+\t\tMPP43_GPIO,\t\t/* HTP pin            */\n+\t\tMPP44_GPIO,\t\t/* buzzer             */\n+\t\tMPP45_GPIO,\t\t/* VID B1             */\n+\t\tMPP46_GPIO,\t\t/* power button       */\n+\t\tMPP47_GPIO,\t\t/* HDD2 power         */\n+\t\tMPP48_GPIO,\t\t/* power off          */\n+\t\t0\n+\t};\n+\tkirkwood_mpp_conf(kwmpp_config, NULL);\n+\treturn 0;\n+}\n+\n+int board_init(void)\n+{\n+\n+\t/* address of boot parameters */\n+\tgd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;\n+\n+\t/* This disables the hardware watchdog in the mcu on this board. */\n+\tkw_gpio_set_valid(14, 1);\n+\tkw_gpio_direction_output(14, 0);\n+\tkw_gpio_set_value(14, 1);\n+\n+\treturn 0;\n+}\n+\n+#ifdef CONFIG_RESET_PHY_R\n+/* Configure and enable MV88E1318 PHY */\n+void reset_phy(void)\n+{\n+\tu16 reg;\n+\tu16 devadr;\n+\tchar *name = \"egiga0\";\n+\n+\tif (miiphy_set_current_dev(name))\n+\t\treturn;\n+\n+\t/* command to read PHY dev address */\n+\tif (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {\n+\t\tprintf(\"Err..%s could not read PHY dev address\\n\",\n+\t\t\t__FUNCTION__);\n+\t\treturn;\n+\t}\n+\n+\t/* Set RGMII delay */\n+\tmiiphy_write(name, devadr, MV88E1318_PGADR_REG, MV88E1318_MAC_CTRL_PG);\n+\tmiiphy_read(name, devadr, MV88E1318_MAC_CTRL_REG, &reg);\n+\treg |= (MV88E1318_RGMII_RXTM_CTRL | MV88E1318_RGMII_TXTM_CTRL);\n+\tmiiphy_write(name, devadr, MV88E1318_MAC_CTRL_REG, reg);\n+\tmiiphy_write(name, devadr, MV88E1318_PGADR_REG, 0);\n+\n+\t/* reset the phy */\n+\tmiiphy_reset(name, devadr);\n+\n+\t/* The ZyXEL NSA325 uses the 88E1310S Alaska (interface identical to 88E1318) */\n+\t/* and has an MCU attached to the LED[2] via tristate interrupt */\n+\treg = 0;\n+\n+\t/* switch to LED register page */\n+\tmiiphy_write(name, devadr, MV88E1318_PGADR_REG, MV88E1318_LED_PG);\n+\t/* read out LED polarity register */\n+\tmiiphy_read(name, devadr, MV88E1318_LED_POL_REG, &reg);\n+\t/* clear 4, set 5 - LED2 low, tri-state */\n+\treg &= ~(MV88E1318_LED2_4);\n+\treg |= (MV88E1318_LED2_5);\n+\t/* write back LED polarity register */\n+\tmiiphy_write(name, devadr, MV88E1318_LED_POL_REG, reg);\n+\t/* jump back to page 0, per the PHY chip documenation. */\n+\tmiiphy_write(name, devadr, MV88E1318_PGADR_REG, 0);\n+\n+\t/* Set the phy back to auto-negotiation mode. Onboard mcu sets it as 10Mbits/s on poweroff for WoL function */\n+\tmiiphy_write(name, devadr, 0x4, 0x1e1);\n+\tmiiphy_write(name, devadr, 0x9, 0x300);\n+\t/* Downshift */\n+\tmiiphy_write(name, devadr, 0x10, 0x3860);\n+\tmiiphy_write(name, devadr, 0x0, 0x9140);\n+\n+\tprintf(\"MV88E1318 PHY initialized on %s\\n\", name);\n+\n+}\n+#endif /* CONFIG_RESET_PHY_R */\n+\n+#ifdef CONFIG_SHOW_BOOT_PROGRESS\n+void show_boot_progress(int val)\n+{\n+\tstruct kwgpio_registers *gpio0 = (struct kwgpio_registers *)MVEBU_GPIO0_BASE;\n+\tu32 dout0 = readl(&gpio0->dout);\n+\tu32 blen0 = readl(&gpio0->blink_en);\n+\n+\tstruct kwgpio_registers *gpio1 = (struct kwgpio_registers *)MVEBU_GPIO1_BASE;\n+\tu32 dout1 = readl(&gpio1->dout);\n+\tu32 blen1 = readl(&gpio1->blink_en);\n+\n+\tswitch (val) {\n+\tcase BOOTSTAGE_ID_DECOMP_IMAGE:\n+\t\twritel(blen0 & ~(SYS_GREEN_LED | SYS_ORANGE_LED), &gpio0->blink_en);\n+\t\twritel((dout0 & ~SYS_GREEN_LED) | SYS_ORANGE_LED, &gpio0->dout);\n+\t\tbreak;\n+\tcase BOOTSTAGE_ID_RUN_OS:\n+\t\twritel(dout0 & ~SYS_ORANGE_LED, &gpio0->dout);\n+\t\twritel(blen0 | SYS_GREEN_LED, &gpio0->blink_en);\n+\t\tbreak;\n+\tcase BOOTSTAGE_ID_NET_START:\n+\t\twritel(dout1 & ~COPY_RED_LED, &gpio1->dout);\n+\t\twritel((blen1 & ~COPY_RED_LED) | COPY_GREEN_LED, &gpio1->blink_en);\n+\t\tbreak;\n+\tcase BOOTSTAGE_ID_NET_LOADED:\n+\t\twritel(blen1 & ~(COPY_RED_LED | COPY_GREEN_LED), &gpio1->blink_en);\n+\t\twritel((dout1 & ~COPY_RED_LED) | COPY_GREEN_LED, &gpio1->dout);\n+\t\tbreak;\n+\tcase -BOOTSTAGE_ID_NET_NETLOOP_OK:\n+\tcase -BOOTSTAGE_ID_NET_LOADED:\n+\t\twritel(dout1 & ~COPY_GREEN_LED, &gpio1->dout);\n+\t\twritel((blen1 & ~COPY_GREEN_LED) | COPY_RED_LED, &gpio1->blink_en);\n+\t\tbreak;\n+\tdefault:\n+\t\tif (val < 0) {\n+\t\t\t/* error */\n+\t\t\tprintf(\"Error occured, error code = %d\\n\", -val);\n+\t\t\twritel(dout0 & ~SYS_GREEN_LED, &gpio0->dout);\n+\t\t\twritel(blen0 | SYS_ORANGE_LED, &gpio0->blink_en);\n+\t\t}\n+\t\tbreak;\n+\t}\n+}\n+#endif\n+\n+#if defined(CONFIG_KIRKWOOD_GPIO)\n+/* Return GPIO button status */\n+/*\n+un-pressed:\n+ gpio-36 (Reset Button ) in hi (act lo) - IRQ edge (clear )\n+ gpio-37 (Copy Button  ) in hi (act lo) - IRQ edge (clear )\n+ gpio-46 (Power Button ) in lo (act hi) - IRQ edge (clear )\n+pressed\n+ gpio-36 (Reset Button ) in lo (act hi) - IRQ edge (clear )\n+ gpio-37 (Copy Button  ) in lo (act hi) - IRQ edge (clear )\n+ gpio-46 (Power Button ) in hi (act lo) - IRQ edge (clear )\n+*/\n+\n+static int\n+do_read_button(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])\n+{\n+\tif (strcmp(argv[1], \"power\") == 0) {\n+\t\t\tkw_gpio_set_valid(BTN_POWER, GPIO_INPUT_OK);\n+\t\t\tkw_gpio_direction_input(BTN_POWER);\n+\t\t\treturn !kw_gpio_get_value(BTN_POWER);\n+\t}\n+\telse if (strcmp(argv[1], \"reset\") == 0)\n+\t\treturn kw_gpio_get_value(BTN_RESET);\n+\telse if (strcmp(argv[1], \"copy\") == 0)\n+\t\treturn kw_gpio_get_value(BTN_COPY);\n+\telse\n+\t\treturn -1;\n+}\n+\n+\n+U_BOOT_CMD(button, 2, 0, do_read_button,\n+\t   \"Return GPIO button status 0=off 1=on\",\n+\t   \"- button power|reset|copy: test buttons states\\n\"\n+);\n+\n+#endif\n+\n--- /dev/null\n+++ b/board/zyxel/nsa325/nsa325.h\n@@ -0,0 +1,77 @@\n+/*\n+ * Copyright (C) 2014  Jason Plum <jplum@archlinuxarm.org>\n+ *\n+ * Based on nsa320.h originall written by\n+ * Copyright (C) 2012  Peter Schildmann <linux@schildmann.info>\n+ *\n+ * Based on guruplug.h originally written by\n+ * Siddarth Gore <gores@marvell.com>\n+ * (C) Copyright 2009\n+ * Marvell Semiconductor <www.marvell.com>\n+ *\n+ * See file CREDITS for list of people who contributed to this\n+ * project.\n+ *\n+ * This program is free software; you can redistribute it and/or\n+ * modify it under the terms of the GNU General Public License as\n+ * published by the Free Software Foundation; either version 2 of\n+ * the License, or (at your option) any later version.\n+ *\n+ * This program is distributed in the hope that it will be useful,\n+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\n+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n+ * GNU General Public License for more details.\n+ *\n+ * You should have received a copy of the GNU General Public License\n+ * along with this program; if not, write to the Free Software\n+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,\n+ * MA 02110-1301 USA\n+ */\n+\n+#ifndef __NSA325_H\n+#define __NSA325_H\n+\n+/* low GPIO's */\n+#define HDD2_GREEN_LED\t\t(1 << 12)\n+#define HDD2_RED_LED\t\t(1 << 13)\n+#define USB_GREEN_LED\t\t(1 << 15)\n+#define USB_POWER\t\t(1 << 21)\n+#define SYS_GREEN_LED\t\t(1 << 28)\n+#define SYS_ORANGE_LED\t\t(1 << 29)\n+\n+#define PIN_USB_GREEN_LED\t15\n+#define PIN_USB_POWER\t\t21\n+\n+#define NSA325_OE_LOW\t\t(~(HDD2_GREEN_LED | HDD2_RED_LED | \\\n+\t\t\t\t   USB_GREEN_LED | USB_POWER | \\\n+\t\t\t\t   SYS_GREEN_LED | SYS_ORANGE_LED))\n+#define NSA325_VAL_LOW\t\t(SYS_GREEN_LED | USB_POWER)\n+\n+/* high GPIO's */\n+#define COPY_GREEN_LED\t\t(1 << 7)\n+#define COPY_RED_LED\t\t(1 << 8)\n+#define HDD1_GREEN_LED\t\t(1 << 9)\n+#define HDD1_RED_LED\t\t(1 << 10)\n+#define HDD2_POWER          (1 << 15)\n+#define WATCHDOG_SIGNAL     (1 << 14)\n+\n+#define NSA325_OE_HIGH\t\t(~(COPY_GREEN_LED | COPY_RED_LED | \\\n+\t\t\t\t   HDD1_GREEN_LED | HDD1_RED_LED | HDD2_POWER | WATCHDOG_SIGNAL ))\n+#define NSA325_VAL_HIGH\t\t(WATCHDOG_SIGNAL | HDD2_POWER)\n+\n+/* PHY related */\n+#define MV88E1318_PGADR_REG\t\t22\n+#define MV88E1318_MAC_CTRL_PG\t2\n+#define MV88E1318_MAC_CTRL_REG\t21\n+#define MV88E1318_RGMII_TXTM_CTRL\t(1 << 4)\n+#define MV88E1318_RGMII_RXTM_CTRL\t(1 << 5)\n+#define MV88E1318_LED_PG        3\n+#define MV88E1318_LED_POL_REG\t17\n+#define MV88E1318_LED2_4\t    (1 << 4)\n+#define MV88E1318_LED2_5\t    (1 << 5)\n+\n+#define BTN_POWER\t\t\t\t46\n+#define BTN_RESET\t\t\t\t36\n+#define BTN_COPY\t\t\t\t37\n+\n+#endif /* __NSA325_H */\n--- /dev/null\n+++ b/configs/nsa325_defconfig\n@@ -0,0 +1,48 @@\n+CONFIG_ARM=y\n+CONFIG_SYS_DCACHE_OFF=y\n+CONFIG_ARCH_CPU_INIT=y\n+CONFIG_KIRKWOOD=y\n+CONFIG_SYS_TEXT_BASE=0x600000\n+CONFIG_TARGET_NSA325=y\n+CONFIG_IDENT_STRING=\"\\nZyXEL NSA325 2-Bay Power Media Server\"\n+CONFIG_NR_DRAM_BANKS=2\n+CONFIG_BOOTDELAY=3\n+CONFIG_SYS_PROMPT=\"NSA325> \"\n+# CONFIG_CMD_IMLS is not set\n+# CONFIG_CMD_FLASH is not set\n+CONFIG_MVGBE=y\n+CONFIG_MII=y\n+CONFIG_SYS_NS16550=y\n+CONFIG_CMD_FDT=y\n+CONFIG_OF_LIBFDT=y\n+CONFIG_CMD_SETEXPR=y\n+CONFIG_CMD_DHCP=y\n+CONFIG_CMD_MII=y\n+CONFIG_CMD_PING=y\n+CONFIG_CMD_DNS=y\n+CONFIG_CMD_SNTP=y\n+CONFIG_CMD_USB=y\n+CONFIG_USB=y\n+CONFIG_CMD_DATE=y\n+CONFIG_CMD_EXT2=y\n+CONFIG_CMD_EXT4=y\n+CONFIG_CMD_FAT=y\n+CONFIG_CMD_JFFS2=y\n+CONFIG_MTD=y\n+CONFIG_MTD_RAW_NAND=y\n+CONFIG_MTDPARTS_DEFAULT=\"mtdparts=orion_nand:0x0c0000(uboot),0x80000(uboot_env),0x7ec0000(ubi)\"\n+CONFIG_CMD_MTDPARTS=y\n+CONFIG_CMD_ENV=y\n+CONFIG_CMD_NAND=y\n+CONFIG_EFI_PARTITION=y\n+CONFIG_ENV_IS_IN_NAND=y\n+CONFIG_ENV_SIZE=0x20000\n+CONFIG_ENV_OFFSET=0xC0000\n+CONFIG_ENV_SECT_SIZE=0x20000\n+CONFIG_ENV_ADDR=0xC0000\n+CONFIG_CMD_UBI=y\n+CONFIG_USB_EHCI_HCD=y\n+CONFIG_USB_STORAGE=y\n+CONFIG_LZMA=y\n+CONFIG_LZO=y\n+CONFIG_SYS_LONGHELP=y\n--- /dev/null\n+++ b/include/configs/nsa325.h\n@@ -0,0 +1,106 @@\n+/*\n+ * (C) Copyright 2016 bodhi <mibodhi@gmail.com>\n+ *\n+ * Based on\n+ * Copyright (C) 2014 Jason Plum <jplum@archlinuxarm.org>\n+ * Based on\n+ * Copyright (C) 2012  Peter Schildmann <linux@schildmann.info>\n+ *\n+ * Based on guruplug.h originally written by\n+ * Siddarth Gore <gores@marvell.com>\n+ * (C) Copyright 2009\n+ * Marvell Semiconductor <www.marvell.com>\n+ *\n+ * See file CREDITS for list of people who contributed to this\n+ * project.\n+ *\n+ * This program is free software; you can redistribute it and/or\n+ * modify it under the terms of the GNU General Public License as\n+ * published by the Free Software Foundation; either version 2 of\n+ * the License, or (at your option) any later version.\n+ *\n+ * This program is distributed in the hope that it will be useful,\n+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\n+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n+ * GNU General Public License for more details.\n+ *\n+ * You should have received a copy of the GNU General Public License\n+ * along with this program; if not, write to the Free Software\n+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,\n+ * MA 02110-1301 USA\n+ */\n+\n+#ifndef _CONFIG_NSA325_H\n+#define _CONFIG_NSA325_H\n+\n+/*\n+ * High Level Configuration Options (easy to change)\n+ */\n+#define CONFIG_FEROCEON_88FR131\t1\t/* CPU Core subversion */\n+#define CONFIG_KW88F6281\t1\t/* SOC Name */\n+\n+#define CONFIG_SKIP_LOWLEVEL_INIT\t/* disable board lowlevel_init */\n+\n+/*\n+ * Misc Configuration Options\n+ */\n+#define CONFIG_SHOW_BOOT_PROGRESS 1\t/* boot progess display (LED's) */\n+\n+/*\n+ * Commands configuration\n+ */\n+#define CONFIG_PREBOOT\n+\n+/*\n+ * mv-common.h should be defined after CMD configs since it used them\n+ * to enable certain macros\n+ */\n+#include \"mv-common.h\"\n+\n+/*\n+ * Default environment variables\n+ */\n+#define CONFIG_BOOTCOMMAND \\\n+\t\"ubi part ubi; \" \\\n+\t\"ubi read 0x800000 kernel; \" \\\n+\t\"bootm 0x800000\"\n+\n+#define CONFIG_EXTRA_ENV_SETTINGS \\\n+\t\"console=console=ttyS0,115200\\0\"\t\\\n+\t\"mtdids=nand0=orion_nand\\0\"\t\t\\\n+\t\"mtdparts=\"CONFIG_MTDPARTS_DEFAULT \"\\0\"\t\\\n+\t\"bootargs_root=\\0\"\n+\n+/*\n+ * Ethernet Driver configuration\n+ */\n+#ifdef CONFIG_CMD_NET\n+#define CONFIG_MVGBE_PORTS\t\t{1, 0}\t/* enable port 0 only */\n+#define CONFIG_PHY_BASE_ADR\t\t0x1\n+#define CONFIG_NETCONSOLE\n+#endif /* CONFIG_CMD_NET */\n+\n+/*\n+ * SATA Driver configuration\n+ */\n+#ifdef CONFIG_MVSATA_IDE\n+#define CONFIG_SYS_ATA_IDE0_OFFSET      MV_SATA_PORT0_OFFSET\n+#define CONFIG_SYS_ATA_IDE1_OFFSET      MV_SATA_PORT1_OFFSET\n+#endif /* CONFIG_MVSATA_IDE */\n+\n+/*\n+ * File system\n+ */\n+#define CONFIG_JFFS2_NAND\n+#define CONFIG_JFFS2_LZO\n+\n+/*\n+ *  Date Time\n+ */\n+#ifdef CONFIG_CMD_DATE\n+#define CONFIG_RTC_MV\n+#endif /* CONFIG_CMD_DATE */\n+\n+#define CONFIG_KIRKWOOD_GPIO /* Enable GPIO Support */\n+\n+#endif /* _CONFIG_NSA325_H */\n"
  },
  {
    "path": "package/boot/uboot-kirkwood/patches/010-pogoplug_v4.patch",
    "content": "--- a/arch/arm/mach-kirkwood/Kconfig\n+++ b/arch/arm/mach-kirkwood/Kconfig\n@@ -25,6 +25,9 @@ config TARGET_LSXL\n config TARGET_POGO_E02\n \tbool \"pogo_e02 Board\"\n \n+config TARGET_POGOPLUGV4\n+    bool \"Pogoplug V4 Board\"\n+\n config TARGET_DNS325\n \tbool \"dns325 Board\"\n \n@@ -83,6 +86,7 @@ source \"board/Marvell/guruplug/Kconfig\"\n source \"board/Marvell/sheevaplug/Kconfig\"\n source \"board/buffalo/lsxl/Kconfig\"\n source \"board/cloudengines/pogo_e02/Kconfig\"\n+source \"board/cloudengines/pogoplugv4/Kconfig\"\n source \"board/d-link/dns325/Kconfig\"\n source \"board/iomega/iconnect/Kconfig\"\n source \"board/keymile/Kconfig\"\n--- a/arch/arm/mach-kirkwood/include/mach/kw88f6192.h\n+++ b/arch/arm/mach-kirkwood/include/mach/kw88f6192.h\n@@ -15,6 +15,6 @@\n #define KW_REGS_PHY_BASE\t\tKW88F6192_REGS_PHYS_BASE\n \n /* TCLK Core Clock defination */\n-#define CONFIG_SYS_TCLK\t  166000000 /* 166MHz */\n+#define CONFIG_SYS_TCLK\t  166666667 /* 166MHz */\n \n #endif /* _CONFIG_KW88F6192_H */\n--- a/arch/arm/mach-kirkwood/include/mach/mpp.h\n+++ b/arch/arm/mach-kirkwood/include/mach/mpp.h\n@@ -216,10 +216,12 @@\n #define MPP33_GPIO\t\tMPP( 33, 0x0, 1, 1, 0,   1,   1,   1    )\n #define MPP33_TDM_DTX\t\tMPP( 33, 0x2, 0, 1, 0,   0,   1,   1    )\n #define MPP33_GE1_13\t\tMPP( 33, 0x3, 0, 0, 0,   1,   1,   1    )\n+#define MPP33_SATA1_ACTn        MPP( 33, 0x5, 0, 1, 0,   1,   1,   1    )\n \n #define MPP34_GPIO\t\tMPP( 34, 0x0, 1, 1, 0,   1,   1,   1    )\n #define MPP34_TDM_SPI_CS1\tMPP( 34, 0x2, 0, 1, 0,   0,   1,   1    )\n #define MPP34_GE1_14\t\tMPP( 34, 0x3, 0, 0, 0,   1,   1,   1    )\n+#define MPP34_SATA1_ACTn       MPP( 34, 0x5, 0, 1, 0,   1,   1,   1    )\n \n #define MPP35_GPIO\t\tMPP( 35, 0x0, 1, 1, 1,   1,   1,   1    )\n #define MPP35_TDM_CH0_TX_QL\tMPP( 35, 0x2, 0, 1, 0,   0,   1,   1    )\n--- /dev/null\n+++ b/board/cloudengines/pogoplugv4/Kconfig\n@@ -0,0 +1,12 @@\n+if TARGET_POGOPLUGV4\n+\n+config SYS_BOARD\n+\tdefault \"pogoplugv4\"\n+\n+config SYS_VENDOR\n+\tdefault \"cloudengines\"\n+\n+config SYS_CONFIG_NAME\n+\tdefault \"pogoplugv4\"\n+\n+endif\n--- /dev/null\n+++ b/board/cloudengines/pogoplugv4/MAINTAINERS\n@@ -0,0 +1,6 @@\n+POGOPLUGV4 BOARD\n+M:\tAlberto Bursi <alberto.bursi@outlook.it>\n+S:\tMaintained\n+F:\tboard/cloudengines/pogoplugv4/\n+F:\tinclude/configs/pogoplugv4.h\n+F:\tconfigs/pogoplugv4_defconfig\n--- /dev/null\n+++ b/board/cloudengines/pogoplugv4/Makefile\n@@ -0,0 +1,11 @@\n+#\n+# (C) Copyright 2009 bodhi <mibodhi@gmail.com>\n+#\n+# Based on\n+# Marvell Semiconductor <www.marvell.com>\n+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>\n+#\n+# SPDX-License-Identifier:\tGPL-2.0+\n+#\n+\n+obj-y\t:= pogoplugv4.o\n--- /dev/null\n+++ b/board/cloudengines/pogoplugv4/kwbimage.cfg\n@@ -0,0 +1,167 @@\n+#\n+# Copyright (C) 2012\n+# David Purdy <david.c.purdy@gmail.com>\n+#\n+# Based on Kirkwood support:\n+# (C) Copyright 2009\n+# Marvell Semiconductor <www.marvell.com>\n+# Written-by: Prafulla Wadaskar <prafulla <at> marvell.com>\n+#\n+# See file CREDITS for list of people who contributed to this\n+# project.\n+#\n+# This program is free software; you can redistribute it and/or\n+# modify it under the terms of the GNU General Public License as\n+# published by the Free Software Foundation; either version 2 of\n+# the License, or (at your option) any later version.\n+#\n+# This program is distributed in the hope that it will be useful,\n+# but WITHOUT ANY WARRANTY; without even the implied warranty of\n+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n+# GNU General Public License for more details.\n+#\n+# You should have received a copy of the GNU General Public License\n+# along with this program; If not, see <http://www.gnu.org/licenses/>.\n+#\n+# Refer docs/README.kwimage for more details about how-to configure\n+# and create kirkwood boot image\n+#\n+\n+# Boot Media configurations   (DONE)\n+BOOT_FROM\tnand\n+NAND_ECC_MODE\tdefault\n+NAND_PAGE_SIZE\t0x0800\n+\n+# SOC registers configuration using bootrom header extension\n+# Maximum KWBIMAGE_MAX_CONFIG configurations allowed\n+\n+# Configure RGMII-0 interface pad voltage to 1.8V (SHOULD BE SAME)\n+DATA 0xffd100e0 0x1b1b1b9b\n+\n+#Dram initalization for SINGLE x16 CL=3 @ 200MHz   (need CL=3 @ 200MHz?)\n+DATA 0xffd01400 0x43000618\t# DDR Configuration register\n+# bit13-0:  0x200 (200 DDR2 clks refresh rate)\n+# bit23-14: zero\n+# bit24: 1= enable exit self refresh mode on DDR access\n+# bit25: 1 required\n+# bit29-26: zero\n+# bit31-30: 01\n+\n+DATA 0xffd01404 0x34143000\t# DDR Controller Control Low\n+# bit 4:    0=addr/cmd in smame cycle\n+# bit 5:    0=clk is driven during self refresh, we don't care for APX\n+# bit 6:    0=use recommended falling edge of clk for addr/cmd\n+# bit14:    0=input buffer always powered up\n+# bit18:    1=cpu lock transaction enabled\n+# bit23-20: 3=recommended value for CL=3 and STARTBURST_DEL disabled bit31=0\n+# bit27-24: 6= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM\n+# bit30-28: 3 required\n+# bit31:    0=no additional STARTBURST delay\n+\n+DATA 0xffd01408 0x11012227\t# DDR Timing (Low) (active cycles value +1)\n+# bit3-0:   TRAS lsbs\n+# bit7-4:   TRCD\n+# bit11- 8: TRP\n+# bit15-12: TWR\n+# bit19-16: TWTR\n+# bit20:    TRAS msb\n+# bit23-21: 0x0\n+# bit27-24: TRRD\n+# bit31-28: TRTP\n+\n+DATA 0xffd0140c 0x00000819\t#  DDR Timing (High)\n+# bit6-0:   TRFC\n+# bit8-7:   TR2R\n+# bit10-9:  TR2W\n+# bit12-11: TW2W\n+# bit31-13: zero required\n+\n+DATA 0xffd01410 0x00000001\t#  DDR Address Control  (changed to Dockstar vals)\n+# bit1-0:   00, Cs0width=x16\n+# bit3-2:   10, Cs0size=512Mb\n+# bit5-4:   00, Cs2width=nonexistent\n+# bit7-6:   00, Cs1size =nonexistent\n+# bit9-8:   00, Cs2width=nonexistent\n+# bit11-10: 00, Cs2size =nonexistent\n+# bit13-12: 00, Cs3width=nonexistent\n+# bit15-14: 00, Cs3size =nonexistent\n+# bit16:    0,  Cs0AddrSel\n+# bit17:    0,  Cs1AddrSel\n+# bit18:    0,  Cs2AddrSel\n+# bit19:    0,  Cs3AddrSel\n+# bit31-20: 0 required\n+\n+DATA 0xffd01414 0x00000000\t#  DDR Open Pages Control\n+# bit0:    0,  OpenPage enabled\n+# bit31-1: 0 required\n+\n+DATA 0xffd01418 0x00000000\t#  DDR Operation\n+# bit3-0:   0x0, DDR cmd\n+# bit31-4:  0 required\n+\n+DATA 0xffd0141c 0x00000632\t#  DDR Mode\n+# bit2-0:   2, BurstLen=2 required\n+# bit3:     0, BurstType=0 required\n+# bit6-4:   4, CL=5\t\t\t\t(<===== change to CL=3 ?)\n+# bit7:     0, TestMode=0 normal\n+# bit8:     0, DLL reset=0 normal\n+# bit11-9:  6, auto-precharge write recovery ????????????\n+# bit12:    0, PD must be zero\n+# bit31-13: 0 required\n+\n+DATA 0xffd01420 0x00000040\t#  DDR Extended Mode\n+# bit0:    0,  DDR DLL enabled\n+# bit1:    0,  DDR drive strenght normal\n+# bit2:    0,  DDR ODT control lsd (disabled)\n+# bit5-3:  000, required\n+# bit6:    1,  DDR ODT control msb, (disabled)\n+# bit9-7:  000, required\n+# bit10:   0,  differential DQS enabled\n+# bit11:   0, required\n+# bit12:   0, DDR output buffer enabled\n+# bit31-13: 0 required\n+\n+DATA 0xffd01424 0x0000F07F\t#  DDR Controller Control High\n+# bit2-0:  111, required\n+# bit3  :  1  , MBUS Burst Chop disabled\n+# bit6-4:  111, required\n+# bit7  :  0\n+# bit8  :  0  , no sample stage\n+# bit9  :  0  , no half clock cycle addition to dataout\n+# bit10 :  0  , 1/4 clock cycle skew enabled for addr/ctl signals\n+# bit11 :  0  , 1/4 clock cycle skew disabled for write mesh\n+# bit15-12: 1111 required\n+# bit31-16: 0    required\n+\n+DATA 0xffd01428 0x00085520\t# DDR2 ODT Read Timing (default values)\n+DATA 0xffd0147c 0x00008552\t# DDR2 ODT Write Timing (default values)\n+\n+DATA 0xFFD01500 0x00000000\t# CS[0]n Base address to 0x0\n+DATA 0xFFD01504 0x07FFFFF1\t# CS[0]n Size\n+# bit0:    1,  Window enabled\n+# bit1:    0,  Write Protect disabled\n+# bit3-2:  00, CS0 hit selected\n+# bit23-4: ones, required\n+# bit31-24: 0x07, Size (i.e. 128MB)\n+\n+DATA 0xFFD0150C 0x00000000\t# CS[1]n Size, window disabled\n+DATA 0xFFD01514 0x00000000\t# CS[2]n Size, window disabled\n+DATA 0xFFD0151C 0x00000000\t# CS[3]n Size, window disabled\n+\n+DATA 0xffd01494 0x00030000\t#  DDR ODT Control (Low)\t\t (DONE)\n+# bit3-0:  2, ODT0Rd, MODT[0] asserted during read from DRAM CS1\n+# bit7-4:  1, ODT0Rd, MODT[0] asserted during read from DRAM CS0\n+# bit19-16:2, ODT0Wr, MODT[0] asserted during write to DRAM CS1\n+# bit23-20:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0\n+\n+DATA 0xffd01498 0x00000000\t#  DDR ODT Control (High)  (DONE)\n+# bit1-0:  00, ODT0 controlled by ODT Control (low) register above\n+# bit3-2:  01, ODT1 active NEVER!\n+# bit31-4: zero, required\n+\n+DATA 0xffd0149c 0x0000e803\t# CPU ODT Control\t (DONE)\n+DATA 0xffd01480 0x00000001\t# DDR Initialization Control\t (DONE)\n+#bit0=1, enable DDR init upon this register write\n+\n+# End of Header extension\n+DATA 0x0 0x0\n--- /dev/null\n+++ b/board/cloudengines/pogoplugv4/pogoplugv4.c\n@@ -0,0 +1,223 @@\n+/*\n+ * Copyright (C) 2016 bodhi <mibodhi@gmail.com>\n+ * Copyright (C) 2014 bodhi <mibodhi@gmail.com>\n+ *\n+ * Based on\n+ *\n+ * Copyright (C) 2014 <ebbes.ebbes@gmail.com>\n+ *\n+ * Copyright (C) 2012\n+ * David Purdy <david.c.purdy@gmail.com>\n+ *\n+ * Based on Kirkwood support:\n+ * (C) Copyright 2009\n+ * Marvell Semiconductor <www.marvell.com>\n+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>\n+ *\n+ * See file CREDITS for list of people who contributed to this\n+ * project.\n+ *\n+ * This program is free software; you can redistribute it and/or\n+ * modify it under the terms of the GNU General Public License as\n+ * published by the Free Software Foundation; either version 2 of\n+ * the License, or (at your option) any later version.\n+ *\n+ * This program is distributed in the hope that it will be useful,\n+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\n+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n+ * GNU General Public License for more details.\n+ *\n+ * You should have received a copy of the GNU General Public License\n+ * along with this program; If not, see <http://www.gnu.org/licenses/>.\n+ */\n+\n+#include <common.h>\n+#include <miiphy.h>\n+#include <asm/arch/cpu.h>\n+#include <asm/arch/soc.h>\n+#include <asm/arch/mpp.h>\n+#include <asm/io.h>\n+#include \"pogoplugv4.h\"\n+#include <asm/arch/gpio.h>\n+\n+#ifdef CONFIG_KIRKWOOD_MMC\n+#include <kirkwood_mmc.h>\n+#endif /* CONFIG_KIRKWOOD_MMC */\n+\n+\n+DECLARE_GLOBAL_DATA_PTR;\n+\n+int board_early_init_f(void)\n+{\n+\t/*\n+\t * default gpio configuration\n+\t * There are maximum 64 gpios controlled through 2 sets of registers\n+\t * the  below configuration configures mainly initial LED status\n+\t */\n+\tmvebu_config_gpio(POGOPLUGV4_OE_VAL_LOW,\n+\t\t\tPOGOPLUGV4_OE_VAL_HIGH,\n+\t\t\tPOGOPLUGV4_OE_LOW, POGOPLUGV4_OE_HIGH);\n+\n+\t/* Multi-Purpose Pins Functionality configuration */\n+\tu32 kwmpp_config[] = {\n+\t\tMPP0_NF_IO2,\n+\t\tMPP1_NF_IO3,\n+\t\tMPP2_NF_IO4,\n+\t\tMPP3_NF_IO5,\n+\t\tMPP4_NF_IO6,\n+\t\tMPP5_NF_IO7,\n+\t\tMPP6_SYSRST_OUTn,\n+\t\tMPP7_GPO,\n+\t\tMPP8_TW_SDA,\n+\t\tMPP9_TW_SCK,\n+\t\tMPP10_UART0_TXD,\n+\t\tMPP11_UART0_RXD,\n+\t\tMPP12_SD_CLK,\n+\t\tMPP13_SD_CMD,\n+\t\tMPP14_SD_D0,\n+\t\tMPP15_SD_D1,\n+\t\tMPP16_SD_D2,\n+\t\tMPP17_SD_D3,\n+\t\tMPP18_NF_IO0,\n+\t\tMPP19_NF_IO1,\n+\t\tMPP20_SATA1_ACTn,\n+\t\tMPP21_SATA0_ACTn,\n+\t\tMPP22_GPIO,\t/* Green LED */\n+\t\tMPP23_GPIO,\n+\t\tMPP24_GPIO,\t/* Red LED */\n+\t\tMPP25_GPIO,\n+\t\tMPP26_GPIO,\n+\t\tMPP27_GPIO,\n+\t\tMPP28_GPIO,\n+\t\tMPP29_GPIO,\t/* Eject button */\n+\t\tMPP30_GPIO,\n+\t\tMPP31_GPIO,\n+\t\tMPP32_GPIO,\n+\t\tMPP33_GPIO,\n+\t\tMPP34_GPIO,\n+\t\tMPP35_GPIO,\t/* FR6192 has only 36 GPIOs */\n+\t\t0\n+\t};\n+\tkirkwood_mpp_conf(kwmpp_config, NULL);\n+\n+\treturn 0;\n+}\n+\n+int board_init(void)\n+{\n+\t/* Boot parameters address */\n+\tgd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;\n+\n+        kw_gpio_set_valid(20, 1);\n+        kw_gpio_set_valid(21, 1);\n+        kw_gpio_set_valid(22, 1);\n+        kw_gpio_set_valid(24, 1);\n+\n+\treturn 0;\n+}\n+\n+#ifdef CONFIG_RESET_PHY_R\n+/* Configure and initialize PHY */\n+void reset_phy(void)\n+{\n+\tu16 reg;\n+\tu16 devadr;\n+\tchar *name = \"egiga0\";\n+\n+\tif (miiphy_set_current_dev(name))\n+\t\treturn;\n+\n+\t/* command to read PHY dev address */\n+\tif (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {\n+\t\tprintf(\"Err..(%s) could not read PHY dev address\\n\", __func__);\n+\t\treturn;\n+\t}\n+\n+\t/*\n+\t * Enable RGMII delay on Tx and Rx for CPU port\n+\t * Ref: sec 4.7.2 of chip datasheet\n+\t */\n+\tmiiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);\n+\tmiiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg);\n+\treg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);\n+\tmiiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);\n+\tmiiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);\n+\n+\t/* reset the phy */\n+\tmiiphy_reset(name, devadr);\n+\n+\tdebug(\"88E1116 Initialized on %s\\n\", name);\n+}\n+#endif /* CONFIG_RESET_PHY_R */\n+\n+#ifdef CONFIG_KIRKWOOD_MMC\n+int board_mmc_init(bd_t *bis)\n+{\n+       kw_mmc_initialize(bis);\n+       return 0;\n+}\n+#endif /* CONFIG_KIRKWOOD_MMC */\n+\n+\n+#define GREEN_LED\t(1 << 22)\n+#define RED_LED\t\t(1 << 24)\n+#define BOTH_LEDS\t(GREEN_LED | RED_LED)\n+#define NEITHER_LED\t0\n+\n+static void set_leds(u32 leds, u32 blinking)\n+{\n+\tstruct kwgpio_registers *r;\n+\tu32 oe;\n+\tu32 bl;\n+\n+\tr = (struct kwgpio_registers *)MVEBU_GPIO0_BASE;\n+\toe = readl(&r->oe) | BOTH_LEDS;\n+\twritel(oe & ~leds, &r->oe);\t/* active low */\n+\tbl = readl(&r->blink_en) & ~BOTH_LEDS;\n+\twritel(bl | blinking, &r->blink_en);\n+}\n+\n+void show_boot_progress(int val)\n+{\n+\tswitch (val) {\n+\tcase BOOTSTAGE_ID_RUN_OS:\t\t/* booting Linux */\n+\t\tset_leds(BOTH_LEDS, NEITHER_LED);\n+\t\tbreak;\n+\tcase BOOTSTAGE_ID_NET_ETH_START:\t/* Ethernet initialization */\n+\t\tset_leds(GREEN_LED, GREEN_LED);\n+\t\tbreak;\n+\tdefault:\n+\t\tif (val < 0)\t/* error */\n+\t\t\tset_leds(RED_LED, RED_LED);\n+\t\tbreak;\n+\t}\n+}\n+\n+#if defined(CONFIG_KIRKWOOD_GPIO)\n+/* Return GPIO button status */\n+/*\n+un-pressed:\n+ gpio-29 (Eject Button ) in hi (act lo) - IRQ edge (clear )\n+pressed\n+ gpio-29 (Eject Button ) in lo (act hi) - IRQ edge (clear )\n+*/\n+\n+static int\n+do_read_button(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])\n+{\n+\tif (strcmp(argv[1], \"eject\") == 0) {\n+\t\t\tkw_gpio_set_valid(BTN_EJECT, GPIO_INPUT_OK);\n+\t\t\tkw_gpio_direction_input(BTN_EJECT);\n+\t\t\treturn kw_gpio_get_value(BTN_EJECT);\n+\t}\n+\telse\n+\t\treturn -1;\n+}\n+\n+\n+U_BOOT_CMD(button, 2, 0, do_read_button,\n+\t   \"Return GPIO button status 0=off 1=on\",\n+\t   \"- button eject: test buttons states\\n\"\n+);\n+\n+#endif\n--- /dev/null\n+++ b/board/cloudengines/pogoplugv4/pogoplugv4.h\n@@ -0,0 +1,50 @@\n+/*\n+ * Copyright (C) 2016\n+ * bodhi <mibodhi@gmail.com>\n+ *\n+ * Copyright (C) 2012\n+ * David Purdy <david.c.purdy@gmail.com>\n+ *\n+ * Based on Kirkwood support:\n+ * (C) Copyright 2009\n+ * Marvell Semiconductor <www.marvell.com>\n+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>\n+ *\n+ * See file CREDITS for list of people who contributed to this\n+ * project.\n+ *\n+ * This program is free software; you can redistribute it and/or\n+ * modify it under the terms of the GNU General Public License as\n+ * published by the Free Software Foundation; either version 2 of\n+ * the License, or (at your option) any later version.\n+ *\n+ * This program is distributed in the hope that it will be useful,\n+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\n+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n+ * GNU General Public License for more details.\n+ *\n+ * You should have received a copy of the GNU General Public License\n+ * along with this program; If not, see <http://www.gnu.org/licenses/>.\n+ */\n+\n+#ifndef __POGOPLUGV4_H\n+#define __POGOPLUGV4_H\n+\n+/* GPIO configuration */\n+#define POGOPLUGV4_OE_LOW\t\t\t\t(~(0))\n+#define POGOPLUGV4_OE_HIGH\t\t\t\t(~(0))\n+#define POGOPLUGV4_OE_VAL_LOW\t\t\t(1 << 29)\n+#define POGOPLUGV4_OE_VAL_HIGH\t\t\t0\n+\n+/* PHY related */\n+#define MV88E1116_LED_FCTRL_REG\t\t\t10\n+#define MV88E1116_CPRSP_CR3_REG\t\t\t21\n+#define MV88E1116_MAC_CTRL_REG\t\t\t21\n+#define MV88E1116_PGADR_REG\t\t\t22\n+#define MV88E1116_RGMII_TXTM_CTRL\t\t(1 << 4)\n+#define MV88E1116_RGMII_RXTM_CTRL\t\t(1 << 5)\n+\n+/* button */\n+#define BTN_EJECT\t\t\t\t29\n+\n+#endif /* __POGOPLUGV4_H */\n--- /dev/null\n+++ b/configs/pogoplugv4_defconfig\n@@ -0,0 +1,51 @@\n+CONFIG_ARM=y\n+CONFIG_SYS_DCACHE_OFF=y\n+CONFIG_ARCH_CPU_INIT=y\n+CONFIG_KIRKWOOD=y\n+CONFIG_SYS_TEXT_BASE=0x600000\n+CONFIG_TARGET_POGOPLUGV4=y\n+CONFIG_SYS_PROMPT=\"pogoplugv4> \"\n+CONFIG_IDENT_STRING=\"\\nPogoplug V4\"\n+CONFIG_NR_DRAM_BANKS=2\n+CONFIG_BOOTDELAY=3\n+# CONFIG_CMD_IMLS is not set\n+# CONFIG_CMD_FLASH is not set\n+CONFIG_MVGBE=y\n+CONFIG_MII=y\n+CONFIG_SYS_NS16550=y\n+CONFIG_CMD_FDT=y\n+CONFIG_OF_LIBFDT=y\n+CONFIG_OF_BOOTZ=y\n+CONFIG_CMD_SETEXPR=y\n+CONFIG_CMD_DHCP=y\n+CONFIG_CMD_MII=y\n+CONFIG_CMD_PING=y\n+CONFIG_CMD_DNS=y\n+CONFIG_CMD_SNTP=y\n+CONFIG_CMD_USB=y\n+CONFIG_CMD_DATE=y\n+CONFIG_CMD_EXT2=y\n+CONFIG_CMD_EXT4=y\n+CONFIG_CMD_FAT=y\n+CONFIG_CMD_JFFS2=y\n+CONFIG_MTD=y\n+CONFIG_MTD_RAW_NAND=y\n+CONFIG_MTDPARTS_DEFAULT=\"mtdparts=orion_nand:0x1c0000(uboot),0x40000(uboot_env),0x7e00000(ubi)\"\n+CONFIG_CMD_MTDPARTS=y\n+CONFIG_CMD_ENV=y\n+CONFIG_CMD_NAND=y\n+CONFIG_CMD_MMC=y\n+CONFIG_CMD_GPIO=y\n+CONFIG_EFI_PARTITION=y\n+CONFIG_ENV_IS_IN_NAND=y\n+CONFIG_ENV_SIZE=0x20000\n+CONFIG_ENV_OFFSET=0x1C0000\n+CONFIG_ENV_SECT_SIZE=0x20000\n+CONFIG_ENV_ADDR=0x1C0000\n+CONFIG_CMD_UBI=y\n+CONFIG_USB=y\n+CONFIG_USB_EHCI_HCD=y\n+CONFIG_USB_STORAGE=y\n+CONFIG_LZMA=y\n+CONFIG_LZO=y\n+CONFIG_SYS_LONGHELP=y\n--- a/drivers/gpio/kw_gpio.c\n+++ b/drivers/gpio/kw_gpio.c\n@@ -147,3 +147,36 @@ void kw_gpio_set_blink(unsigned pin, int\n \t/* Set blinking. */\n \t__set_blinking(pin, blink);\n }\n+\n+\n+/*\n+ *  Hooks to  GENERIC_GPIO primitives\n+ */\n+\n+int gpio_direction_input(unsigned pin)\n+{\n+       return kw_gpio_direction_input(pin);\n+}\n+\n+int gpio_direction_output(unsigned pin, int value)\n+{\n+        return kw_gpio_direction_output(pin, value);\n+}\n+\n+void gpio_set_value(unsigned pin, int value) {\n+       kw_gpio_set_value(pin, value);\n+}\n+\n+int gpio_get_value(unsigned pin) {\n+       return kw_gpio_get_value(pin);\n+}\n+\n+int gpio_request(unsigned gpio, const char *label)\n+{\n+       return 0;\n+}\n+\n+int gpio_free(unsigned gpio)\n+{\n+       return 0;\n+}\n--- a/drivers/mmc/Makefile\n+++ b/drivers/mmc/Makefile\n@@ -66,6 +66,7 @@ obj-$(CONFIG_MMC_SDHCI_TANGIER)\t\t+= tang\n obj-$(CONFIG_MMC_SDHCI_TEGRA)\t\t+= tegra_mmc.o\n obj-$(CONFIG_MMC_SDHCI_XENON)\t\t+= xenon_sdhci.o\n obj-$(CONFIG_MMC_SDHCI_ZYNQ)\t\t+= zynq_sdhci.o\n+obj-$(CONFIG_KIRKWOOD_MMC)\t\t+= kirkwood_mmc.o\n \n obj-$(CONFIG_MMC_SUNXI)\t\t\t+= sunxi_mmc.o\n obj-$(CONFIG_MMC_UNIPHIER)\t\t+= tmio-common.o uniphier-sd.o\n--- /dev/null\n+++ b/drivers/mmc/kirkwood_mmc.c\n@@ -0,0 +1,482 @@\n+/*\n+ * (C) Copyright 2014 bodhi <mibodhi@gmail.com>\n+ *\n+ * Based on\n+ *\n+ * (C) Copyright 2014 <ebbes.ebbes@gmail.com>\n+ *\n+ * Based on\n+ *\n+ * Driver for Marvell SDIO/MMC controller\n+ *\n+ * (C) Copyright 2012\n+ * Marvell Semiconductor <www.marvell.com>\n+ * Written-by: Gérald Kerma <uboot at doukki.net>\n+ * See file CREDITS for list of people who contributed to this\n+ * project.\n+ *\n+ * This program is free software; you can redistribute it and/or\n+ * modify it under the terms of the GNU General Public License as\n+ * published by the Free Software Foundation; either version 2 of\n+ * the License, or (at your option) any later version.\n+ *\n+ * This program is distributed in the hope that it will be useful,\n+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\n+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n+ * GNU General Public License for more details.\n+ *\n+ * You should have received a copy of the GNU General Public License\n+ * along with this program; if not, write to the Free Software\n+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,\n+ * MA 02111-1307 USA\n+ */\n+\n+#include <common.h>\n+#include <malloc.h>\n+#include <part.h>\n+#include <mmc.h>\n+#include <asm/io.h>\n+#include <asm/arch/cpu.h>\n+#include <asm/arch/soc.h>\n+\n+#include <kirkwood_mmc.h>\n+\n+#define DRIVER_NAME\t\"kwsdio\"\n+\n+static int kw_mmc_setup_data(struct mmc_data *data)\n+{\n+\tu32 ctrl_reg;\n+\n+#ifdef DEBUG\n+\tprintf(\"%s, data %s : blocks=%d blksz=%d\\n\", DRIVER_NAME,\n+\t\t(data->flags & MMC_DATA_READ) ? \"read\" : \"write\",\n+\t\tdata->blocks, data->blocksize);\n+#endif\n+\n+\t/* default to maximum timeout */\n+\tctrl_reg = kwsd_read(SDIO_HOST_CTRL);\n+\tctrl_reg |= SDIO_HOST_CTRL_TMOUT(SDIO_HOST_CTRL_TMOUT_MAX);\n+\tkwsd_write(SDIO_HOST_CTRL, ctrl_reg);\n+\n+\tif (data->flags & MMC_DATA_READ) {\n+\t\tkwsd_write(SDIO_SYS_ADDR_LOW,(u32)data->dest & 0xffff);\n+\t\tkwsd_write(SDIO_SYS_ADDR_HI,(u32)data->dest >> 16);\n+\t} else {\n+\t\tkwsd_write(SDIO_SYS_ADDR_LOW,(u32)data->src & 0xffff);\n+\t\tkwsd_write(SDIO_SYS_ADDR_HI,(u32)data->src >> 16);\n+\t}\n+\n+\tkwsd_write(SDIO_BLK_COUNT, data->blocks);\n+\tkwsd_write(SDIO_BLK_SIZE, data->blocksize);\n+\n+\treturn 0;\n+}\n+\n+static int kw_mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)\n+{\n+\tint\ttimeout = 10;\n+\tint err;\n+\tushort waittype = 0;\n+\tushort resptype = 0;\n+\tushort xfertype = 0;\n+\tushort resp_indx = 0;\n+\n+#ifdef CONFIG_MMC_DEBUG\n+\tprintf(\"cmdidx [0x%x] resp_type[0x%x] cmdarg[0x%x]\\n\", cmd->cmdidx, cmd->resp_type, cmd->cmdarg);\n+#endif\n+\n+\tudelay(10000);\n+\n+#ifdef CONFIG_MMC_DEBUG\n+\tprintf(\"%s: cmd %d (hw state 0x%04x)\\n\", DRIVER_NAME, cmd->cmdidx, kwsd_read(SDIO_HW_STATE));\n+#endif\n+\n+\t/* Checking if card is busy */\n+\twhile ((kwsd_read(SDIO_HW_STATE) & CARD_BUSY)) {\n+\t\tif (timeout == 0) {\n+\t\t\tprintf(\"%s: card busy!\\n\", DRIVER_NAME);\n+\t\t\treturn -1;\n+\t\t}\n+\t\ttimeout--;\n+\t\tudelay(1000);\n+\t}\n+\n+\t/* Set up for a data transfer if we have one */\n+\tif (data) {\n+\t\tif ((err = kw_mmc_setup_data(data)))\n+\t\t\treturn err;\n+\t}\n+\n+\tresptype = SDIO_CMD_INDEX(cmd->cmdidx);\n+\n+\t/* Analyzing resptype/xfertype/waittype for the command */\n+\tif (cmd->resp_type & MMC_RSP_BUSY)\n+\t\tresptype |= SDIO_CMD_RSP_48BUSY;\n+\telse if (cmd->resp_type & MMC_RSP_136)\n+\t\tresptype |= SDIO_CMD_RSP_136;\n+\telse if (cmd->resp_type & MMC_RSP_PRESENT)\n+\t\tresptype |= SDIO_CMD_RSP_48;\n+\telse\n+\t\tresptype |= SDIO_CMD_RSP_NONE;\n+\n+\tif (cmd->resp_type & MMC_RSP_CRC)\n+\t\tresptype |= SDIO_CMD_CHECK_CMDCRC;\n+\n+\tif (cmd->resp_type & MMC_RSP_OPCODE)\n+\t\tresptype |= SDIO_CMD_INDX_CHECK;\n+\n+\tif (cmd->resp_type & MMC_RSP_PRESENT) {\n+\t\tresptype |= SDIO_UNEXPECTED_RESP;\n+\t\twaittype |= SDIO_NOR_UNEXP_RSP;\n+\t}\n+\n+\tif (data) {\n+\t\tresptype |= SDIO_CMD_DATA_PRESENT | SDIO_CMD_CHECK_DATACRC16;\n+\t\txfertype |= SDIO_XFER_MODE_HW_WR_DATA_EN;\n+\t\tif (data->flags & MMC_DATA_READ) {\n+\t\t\txfertype |= SDIO_XFER_MODE_TO_HOST;\n+\t\t\twaittype = SDIO_NOR_DMA_INI;\n+\t\t} else\n+\t\t\twaittype |= SDIO_NOR_XFER_DONE;\n+\t} else\n+\t\twaittype |= SDIO_NOR_CMD_DONE;\n+\n+\t/* Setting cmd arguments */\n+\tkwsd_write(SDIO_ARG_LOW, cmd->cmdarg & 0xffff);\n+\tkwsd_write(SDIO_ARG_HI, cmd->cmdarg >> 16);\n+\n+\t/* Setting Xfer mode */\n+\tkwsd_write(SDIO_XFER_MODE, xfertype);\n+\n+\tkwsd_write(SDIO_NOR_INTR_STATUS, ~SDIO_NOR_CARD_INT);\n+\tkwsd_write(SDIO_ERR_INTR_STATUS, SDIO_POLL_MASK);\n+\n+\t/* Sending command */\n+\tkwsd_write(SDIO_CMD, resptype);\n+/*\n+\tkwsd_write(SDIO_CMD, KW_MMC_MAKE_CMD(cmd->cmdidx, resptype));\n+*/\n+\n+\tkwsd_write(SDIO_NOR_INTR_EN, SDIO_POLL_MASK);\n+\tkwsd_write(SDIO_ERR_INTR_EN, SDIO_POLL_MASK);\n+\n+\t/* Waiting for completion */\n+\ttimeout = 1000000;\n+\n+\twhile (!((kwsd_read(SDIO_NOR_INTR_STATUS)) & waittype)) {\n+\t\tif (kwsd_read(SDIO_NOR_INTR_STATUS) & SDIO_NOR_ERROR) {\n+#ifdef DEBUG\n+\t\t\tprintf(\"%s: kw_mmc_send_cmd: error! cmdidx : %d, err reg: %04x\\n\", DRIVER_NAME, cmd->cmdidx,\n+wsd_read(SDIO_ERR_INTR_STATUS));\n+#endif\n+\t\t\tif (kwsd_read(SDIO_ERR_INTR_STATUS) & (SDIO_ERR_CMD_TIMEOUT | SDIO_ERR_DATA_TIMEOUT)) {\n+\t\t\t\treturn -ETIMEDOUT;\n+\t\t\t}\n+\t\t\treturn -ECOMM;\n+\t\t}\n+\n+\t\ttimeout--;\n+\t\tudelay(1);\n+\t\tif (timeout <= 0) {\n+\t\t\tprintf(\"%s: command timed out\\n\", DRIVER_NAME);\n+\t\t\treturn -ETIMEDOUT;\n+\t\t}\n+\t}\n+\n+\t/* Handling response */\n+\tif (cmd->resp_type & MMC_RSP_136) {\n+\t\tuint response[8];\n+\t\tfor (resp_indx = 0; resp_indx < 8; resp_indx++)\n+\t\t\tresponse[resp_indx] = kwsd_read(SDIO_RSP(resp_indx));\n+\n+\t\tcmd->response[0] =\t\t((response[0] & 0x03ff) << 22) |\n+\t\t\t\t\t\t\t\t((response[1] & 0xffff) << 6) |\n+\t\t\t\t\t\t\t\t((response[2] & 0xfc00) >> 10);\n+\t\tcmd->response[1] =\t\t((response[2] & 0x03ff) << 22) |\n+\t\t\t\t\t\t\t\t((response[3] & 0xffff) << 6) |\n+\t\t\t\t\t\t\t\t((response[4] & 0xfc00) >> 10);\n+\t\tcmd->response[2] =\t\t((response[4] & 0x03ff) << 22) |\n+\t\t\t\t\t\t\t\t((response[5] & 0xffff) << 6) |\n+\t\t\t\t\t\t\t\t((response[6] & 0xfc00) >> 10);\n+\t\tcmd->response[3] =\t\t((response[6] & 0x03ff) << 22) |\n+\t\t\t\t\t\t\t\t((response[7] & 0x3fff) << 8);\n+\t} else if (cmd->resp_type & MMC_RSP_PRESENT) {\n+\t\tuint response[3];\n+\t\tfor (resp_indx = 0; resp_indx < 3; resp_indx++)\n+\t\t\tresponse[resp_indx] = kwsd_read(SDIO_RSP(resp_indx));\n+\n+\t\tcmd->response[0] = \t\t((response[2] & 0x003f) << (8 - 8))\t\t|\n+\t\t\t\t\t\t\t\t((response[1] & 0xffff) << (14 - 8))\t|\n+\t\t\t\t\t\t\t\t((response[0] & 0x03ff) << (30 - 8));\n+\t\tcmd->response[1] = \t\t((response[0] & 0xfc00) >> 10);\n+\t\tcmd->response[2] =\t\t0;\n+\t\tcmd->response[3] =\t\t0;\n+\t}\n+\n+#ifdef CONFIG_MMC_DEBUG\n+\tprintf(\"%s: resp[0x%x] \", DRIVER_NAME, cmd->resp_type);\n+\tprintf(\"[0x%x] \", cmd->response[0]);\n+\tprintf(\"[0x%x] \", cmd->response[1]);\n+\tprintf(\"[0x%x] \", cmd->response[2]);\n+\tprintf(\"[0x%x] \", cmd->response[3]);\n+\tprintf(\"\\n\");\n+#endif\n+\n+\treturn 0;\n+}\n+\n+#if 0\n+/* Disable these three functions as they are not used anyway */\n+\n+static void kwsd_power_up(void)\n+{\n+#ifdef DEBUG\n+\tprintf(\"%s: power up\\n\", DRIVER_NAME);\n+#endif\n+\t/* disable interrupts */\n+\tkwsd_write(SDIO_NOR_INTR_EN, 0);\n+\tkwsd_write(SDIO_ERR_INTR_EN, 0);\n+\n+\t/* SW reset */\n+\tkwsd_write(SDIO_SW_RESET, SDIO_SW_RESET_NOW);\n+\n+\tkwsd_write(SDIO_XFER_MODE, 0);\n+\n+\t/* enable status */\n+\tkwsd_write(SDIO_NOR_STATUS_EN, SDIO_POLL_MASK);\n+\tkwsd_write(SDIO_ERR_STATUS_EN, SDIO_POLL_MASK);\n+\n+\t/* enable interrupts status */\n+\tkwsd_write(SDIO_NOR_INTR_STATUS, SDIO_POLL_MASK);\n+\tkwsd_write(SDIO_ERR_INTR_STATUS, SDIO_POLL_MASK);\n+}\n+\n+static void kwsd_power_down(void)\n+{\n+#ifdef DEBUG\n+\tprintf(\"%s: power down\\n\", DRIVER_NAME);\n+#endif\n+\t/* disable interrupts */\n+\tkwsd_write(SDIO_NOR_INTR_EN, 0);\n+\tkwsd_write(SDIO_ERR_INTR_EN, 0);\n+\n+\t/* SW reset */\n+\tkwsd_write(SDIO_SW_RESET, SDIO_SW_RESET_NOW);\n+\n+\tkwsd_write(SDIO_XFER_MODE, SDIO_XFER_MODE_STOP_CLK);\n+\n+\t/* disable status */\n+\tkwsd_write(SDIO_NOR_STATUS_EN, 0);\n+\tkwsd_write(SDIO_ERR_STATUS_EN, 0);\n+\n+\t/* enable interrupts status */\n+\tkwsd_write(SDIO_NOR_INTR_STATUS, SDIO_POLL_MASK);\n+\tkwsd_write(SDIO_ERR_INTR_STATUS, SDIO_POLL_MASK);\n+}\n+\n+static u32 kw_mmc_get_base_clock(void)\n+{\n+\t/* Original version did a check for board device id and revision id\n+\t * and assigned one of these clocks:\n+\t *   KW_MMC_BASE_FAST_CLK_100 (revid == 0 && devid != MV88F6282_DEV_ID)\n+\t *   KW_MMC_BASE_FAST_CLK_200 (revid != 0 || devid == MV88F6282_DEV_ID)\n+\t * However, this check was disabled and\n+\t *   KW_MMC_BASE_FAST_CLOCK\n+\t * was returned in every case.\n+\t * Therefore, all of the dead logic was removed. */\n+\treturn KW_MMC_BASE_FAST_CLOCK;\n+}\n+#endif /* #if 0 */\n+\n+static inline u32 kw_mmc_get_base_clock(void)\n+{\n+\t/* get MMC base clock. If any logic other than just returning\n+\t * a fixed value is ever used, remove inline modifier. */\n+\n+\t/* Possible values:\n+\t *  - KW_MMC_BASE_FAST_CLOCK   (166 MHz)\n+\t *  - KW_MMC_BASE_FAST_CLK_100 (100 MHz)\n+\t *  - KW_MMC_BASE_FAST_CLK_200 (200 MHz)\n+\t *\n+\t * Tests have shown that 200 MHz is more reliable than\n+\t * 166 MHz, so this value is used. */\n+\treturn KW_MMC_BASE_FAST_CLK_200;\n+}\n+\n+static void kw_mmc_set_clk(unsigned int clock)\n+{\n+\tunsigned int m;\n+\n+\tif (clock == 0) {\n+#ifdef DEBUG\n+\t\tprintf(\"%s: clock off\\n\", DRIVER_NAME);\n+#endif\n+\t\tkwsd_write(SDIO_XFER_MODE, SDIO_XFER_MODE_STOP_CLK);\n+\t\tkwsd_write(SDIO_CLK_DIV, KW_MMC_BASE_DIV_MAX);\n+\t} else {\n+\t\tm = kw_mmc_get_base_clock() / (2 * clock) - 1;\n+\t\tif (m > KW_MMC_BASE_DIV_MAX)\n+\t\t\tm = KW_MMC_BASE_DIV_MAX;\n+#ifdef DEBUG\n+\t\tprintf(\"%s: kw_mmc_set_clk: base = %d dividor = 0x%x clock=%d\\n\", DRIVER_NAME,\n+w_mmc_get_base_clock(), m, clock);\n+#endif\n+\t\tkwsd_write(SDIO_CLK_DIV, m & KW_MMC_BASE_DIV_MAX);\n+\t}\n+\tudelay(10000);\n+}\n+\n+static void kw_mmc_set_bus(unsigned int bus)\n+{\n+\tu32 ctrl_reg = 0;\n+\n+\tctrl_reg = kwsd_read(SDIO_HOST_CTRL);\n+\tctrl_reg &= ~SDIO_HOST_CTRL_DATA_WIDTH_4_BITS;\n+\n+\tswitch (bus) {\n+\t\tcase 4:\n+\t\t\tctrl_reg |= SDIO_HOST_CTRL_DATA_WIDTH_4_BITS;\n+\t\t\tbreak;\n+\t\tcase 1:\n+\t\tdefault:\n+\t\t\tctrl_reg |= SDIO_HOST_CTRL_DATA_WIDTH_1_BIT;\n+\t}\n+\t/* default transfer mode */\n+\tctrl_reg |= SDIO_HOST_CTRL_BIG_ENDIAN;\n+\tctrl_reg &= ~SDIO_HOST_CTRL_LSB_FIRST;\n+\n+\t/* default to maximum timeout */\n+\tctrl_reg |= SDIO_HOST_CTRL_TMOUT(SDIO_HOST_CTRL_TMOUT_MAX);\n+\n+\tctrl_reg |= SDIO_HOST_CTRL_PUSH_PULL_EN;\n+\n+\tctrl_reg |= SDIO_HOST_CTRL_CARD_TYPE_MEM_ONLY;\n+\n+\t/*\n+\t * The HI_SPEED_EN bit is causing trouble with many (but not all)\n+\t * high speed SD, SDHC and SDIO cards.  Not enabling that bit\n+\t * makes all cards work.  So let's just ignore that bit for now\n+\t * and revisit this issue if problems for not enabling this bit\n+\t * are ever reported.\n+\t */\n+#if 0\n+\tif (ios->timing == MMC_TIMING_MMC_HS ||\n+\t    ios->timing == MMC_TIMING_SD_HS)\n+\t\tctrl_reg |= SDIO_HOST_CTRL_HI_SPEED_EN;\n+#endif\n+\n+#ifdef DEBUG\n+\tprintf(\"%s: ctrl 0x%04x: %s %s %s\\n\", DRIVER_NAME, ctrl_reg,\n+\t\t(ctrl_reg & SDIO_HOST_CTRL_PUSH_PULL_EN) ?\n+\t\t\t\"push-pull\" : \"open-drain\",\n+\t\t(ctrl_reg & SDIO_HOST_CTRL_DATA_WIDTH_4_BITS) ?\n+\t\t\t\"4bit-width\" : \"1bit-width\",\n+\t\t(ctrl_reg & SDIO_HOST_CTRL_HI_SPEED_EN) ?\n+\t\t\t\"high-speed\" : \"\");\n+#endif\n+\n+\tkwsd_write(SDIO_HOST_CTRL, ctrl_reg);\n+\tudelay(10000);\n+}\n+\n+static void kw_mmc_set_ios(struct mmc *mmc)\n+{\n+#ifdef DEBUG\n+\tprintf(\"%s: bus[%d] clock[%d]\\n\", DRIVER_NAME, mmc->bus_width, mmc->clock);\n+#endif\n+\tkw_mmc_set_bus(mmc->bus_width);\n+\tkw_mmc_set_clk(mmc->clock);\n+}\n+\n+static int kw_mmc_init(struct mmc *mmc)\n+{\n+#ifdef DEBUG\n+\tprintf(\"%s: kw_mmc_init\\n\", DRIVER_NAME);\n+#endif\n+\n+\t/*\n+\t* Setting host parameters\n+\t* Initial Host Ctrl : Timeout : max , Normal Speed mode, 4-bit data mode\n+\t* Big Endian, SD memory Card, Push_pull CMD Line\n+\t*/\n+\tkwsd_write(SDIO_HOST_CTRL,\n+\t\tSDIO_HOST_CTRL_TMOUT(SDIO_HOST_CTRL_TMOUT_MAX) |\n+\t\tSDIO_HOST_CTRL_DATA_WIDTH_4_BITS |\n+\t\tSDIO_HOST_CTRL_BIG_ENDIAN |\n+\t\tSDIO_HOST_CTRL_PUSH_PULL_EN |\n+\t\tSDIO_HOST_CTRL_CARD_TYPE_MEM_ONLY);\n+\n+\tkwsd_write(SDIO_CLK_CTRL, 0);\n+\n+\t/* enable status */\n+\tkwsd_write(SDIO_NOR_STATUS_EN, SDIO_POLL_MASK);\n+\tkwsd_write(SDIO_ERR_STATUS_EN, SDIO_POLL_MASK);\n+\n+\t/* disable interrupts */\n+\tkwsd_write(SDIO_NOR_INTR_EN, 0);\n+\tkwsd_write(SDIO_ERR_INTR_EN, 0);\n+\n+\t/* SW reset */\n+\tkwsd_write(SDIO_SW_RESET, SDIO_SW_RESET_NOW);\n+\n+\tudelay(10000);\n+\treturn 0;\n+}\n+\n+int kw_mmc_initialize(bd_t *bis)\n+{\n+\tstruct mmc *mmc = NULL;\n+        struct mmc_config *cfg = NULL;\n+        struct mmc_ops *ops = NULL;\n+\tchar *name = NULL;\n+\n+#ifdef DEBUG\n+\tprintf(\"%s: %s base_clock = %d\\n\", DRIVER_NAME, kirkwood_id(), kw_mmc_get_base_clock());\n+#endif\n+\tmmc = malloc(sizeof(struct mmc));\n+\tif (!mmc)\n+\t\treturn -1;\n+        memset(mmc, 0, sizeof(*mmc));\n+\n+        cfg = malloc(sizeof(*cfg));\n+        if (cfg == NULL)\n+                return -1;\n+        memset(cfg, 0, sizeof(*cfg));\n+        mmc->cfg = cfg;   /* provided configuration */\n+\n+        ops = malloc(sizeof(*ops));\n+        if (ops == NULL)\n+                return -1;\n+        memset(ops, 0, sizeof(*ops));\n+        cfg->ops = ops;\n+\n+        name = malloc(sizeof(DRIVER_NAME)+1);\n+        if (name == NULL)\n+                return -1;\n+        cfg->name = name;\n+\n+\tsprintf(cfg->name, DRIVER_NAME);\n+\n+\tops->send_cmd\t= kw_mmc_send_cmd;\n+\tops->set_ios\t= kw_mmc_set_ios;\n+\tops->init\t= kw_mmc_init;\n+\n+\tcfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;\n+\tcfg->host_caps = MMC_MODE_4BIT | MMC_MODE_HS;\n+\n+\tcfg->f_min = kw_mmc_get_base_clock()/KW_MMC_BASE_DIV_MAX;\n+\tcfg->f_max = KW_MMC_CLOCKRATE_MAX;\n+\tcfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;\n+\n+\tmmc = mmc_create (cfg, NULL);\n+\n+        if (mmc == NULL) {\n+\t\tfree(name);\n+\t\tfree(ops);\n+                free(cfg);\n+\t        printf(\"\\nFailed to Initialize MMC\\n\");\n+                return -1;\n+        }\n+\n+\treturn 0;\n+}\n--- a/include/configs/mv-common.h\n+++ b/include/configs/mv-common.h\n@@ -75,4 +75,10 @@\n #define CONFIG_SYS_MAX_NAND_DEVICE     1\n #endif\n \n+/*\n+ * Kirkwood MMC\n+ */\n+#if defined(CONFIG_KIRKWOOD) && defined(CONFIG_CMD_MMC)\n+#define CONFIG_SYS_MMC_BASE KW_SDIO_BASE\n+#endif /* defined(CONFIG_KIRKWOOD) && defined(CONFIG_CMD_MMC) */\n #endif /* _MV_COMMON_H */\n--- /dev/null\n+++ b/include/configs/pogoplugv4.h\n@@ -0,0 +1,113 @@\n+/*\n+ * Copyright (C) 2014-2016 bodhi <mibodhi@gmail.com>\n+ * Based on\n+ *\n+ * Copyright (C) 2012\n+ * David Purdy <david.c.purdy@gmail.com>\n+ *\n+ * Based on Kirkwood support:\n+ * (C) Copyright 2009\n+ * Marvell Semiconductor <www.marvell.com>\n+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>\n+ *\n+ * See file CREDITS for list of people who contributed to this\n+ * project.\n+ *\n+ * This program is free software; you can redistribute it and/or\n+ * modify it under the terms of the GNU General Public License as\n+ * published by the Free Software Foundation; either version 2 of\n+ * the License, or (at your option) any later version.\n+ *\n+ * This program is distributed in the hope that it will be useful,\n+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\n+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n+ * GNU General Public License for more details.\n+ *\n+ * You should have received a copy of the GNU General Public License\n+ * along with this program; If not, see <http://www.gnu.org/licenses/>.\n+ */\n+\n+#ifndef _CONFIG_POGOPLUGV4_H\n+#define _CONFIG_POGOPLUGV4_H\n+\n+/*\n+ * Machine type definition and ID\n+ */\n+#define MACH_TYPE_POGOPLUGV4\t\t3960\n+#define CONFIG_MACH_TYPE\t\tMACH_TYPE_POGOPLUGV4\n+\n+/*\n+ * High Level Configuration Options (easy to change)\n+ */\n+#define CONFIG_FEROCEON_88FR131\t\t/* #define CPU Core subversion */\n+#define CONFIG_KW88F6192\t\t/* SOC Name */\n+#define CONFIG_SKIP_LOWLEVEL_INIT\t/* disable board lowlevel_init */\n+\n+#define CONFIG_FEATURE_COMMAND_EDITING\n+#define CONFIG_SYS_64BIT_LBA\n+\n+/*\n+ * Commands configuration\n+ */\n+\n+#define CONFIG_KIRKWOOD_GPIO\n+#define CONFIG_PREBOOT\n+\n+/*\n+ * mv-common.h should be defined after CMD configs since it used them\n+ * to enable certain macros\n+ */\n+#include \"mv-common.h\"\n+\n+/*\n+ * Default environment variables\n+ */\n+#define CONFIG_BOOTCOMMAND \\\n+\t\"usb reset ; \" \\\n+\t\"fatload usb 0:1 0x2000000 initramfs.bin ; \"\\\n+\t\"bootm 0x2000000 ; \" \\\n+\t\"ubi part ubi; \" \\\n+\t\"ubi read 0x800000 kernel; \" \\\n+\t\"bootm 0x800000\"\n+\n+#define CONFIG_EXTRA_ENV_SETTINGS \\\n+\t\"console=console=ttyS0,115200\\0\"\t\\\n+\t\"mtdids=nand0=orion_nand\\0\"\t\t\\\n+\t\"mtdparts=\"CONFIG_MTDPARTS_DEFAULT \"\\0\"\t\\\n+\t\"bootargs_root=\\0\"\n+\n+/*\n+ * Ethernet Driver configuration\n+ */\n+#ifdef CONFIG_CMD_NET\n+#define CONFIG_NETCONSOLE\n+#define CONFIG_MVGBE_PORTS\t{1, 0}\t/* enable port 0 only */\n+#define CONFIG_PHY_BASE_ADR\t0\n+#endif /* CONFIG_CMD_NET */\n+\n+/*\n+ * File system\n+ */\n+#define CONFIG_JFFS2_NAND\n+#define CONFIG_JFFS2_LZO\n+\n+/*\n+ * SATA\n+ */\n+#ifdef CONFIG_MVSATA_IDE\n+#define CONFIG_SYS_ATA_IDE0_OFFSET\tMV_SATA_PORT0_OFFSET\n+#endif\n+\n+/*\n+ *  Date Time\n+ */\n+#ifdef CONFIG_CMD_DATE\n+#define CONFIG_RTC_MV\n+#endif /* CONFIG_CMD_DATE */\n+\n+/*\n+ * Kirkwood GPIO\n+ */\n+#define CONFIG_KIRKWOOD_GPIO\n+\n+#endif /* _CONFIG_POGOPLUGV4_H */\n--- /dev/null\n+++ b/include/kirkwood_mmc.h\n@@ -0,0 +1,268 @@\n+/*\n+ * (C) Copyright 2014 <ebbes.ebbes@gmail.com>\n+ *\n+ * Based on\n+ *\n+ * (C) Copyright 2012\n+ * Marvell Semiconductor <www.marvell.com>\n+ * Written-by: Gérald Kerma <uboot at doukki.net>\n+ * See file CREDITS for list of people who contributed to this\n+ * project.\n+ *\n+ * This program is free software; you can redistribute it and/or\n+ * modify it under the terms of the GNU General Public License as\n+ * published by the Free Software Foundation; either version 2 of\n+ * the License, or (at your option) any later version.\n+ *\n+ * This program is distributed in the hope that it will be useful,\n+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\n+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n+ * GNU General Public License for more details.\n+ *\n+ * You should have received a copy of the GNU General Public License\n+ * along with this program; if not, write to the Free Software\n+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,\n+ * MA 02111-1307 USA\n+ */\n+\n+#ifndef __KIRKWOOD_MMC_H__\n+#define __KIRKWOOD_MMC_H__\n+\n+/*\n+ * Clock rates\n+ */\n+\n+#define KW_MMC_CLOCKRATE_MAX\t\t\t50000000\n+#define KW_MMC_BASE_DIV_MAX\t\t\t0x7ff\n+#define KW_MMC_BASE_FAST_CLOCK\t\tCONFIG_SYS_TCLK\n+#define KW_MMC_BASE_FAST_CLK_100\t\t100000000\n+#define KW_MMC_BASE_FAST_CLK_200\t\t200000000\n+\n+/*\n+ * Macros\n+ */\n+#define kwsd_write(offs, val)\twritel(val, CONFIG_SYS_MMC_BASE + (offs))\n+#define kwsd_read(offs)\t\t\treadl(CONFIG_SYS_MMC_BASE + (offs))\n+\n+#define KW_MMC_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff))\n+\n+/* SDIO register */\n+#define SDIO_SYS_ADDR_LOW\t\t\t0x000\n+#define SDIO_SYS_ADDR_HI\t\t\t0x004\n+#define SDIO_BLK_SIZE\t\t\t\t0x008\n+#define SDIO_BLK_COUNT\t\t\t\t0x00c\n+#define SDIO_ARG_LOW\t\t\t\t0x010\n+#define SDIO_ARG_HI\t\t\t\t\t0x014\n+#define SDIO_XFER_MODE\t\t\t\t0x018\n+#define SDIO_CMD\t\t\t\t\t0x01c\n+#define SDIO_RSP(i)\t\t\t\t\t(0x020 + ((i)<<2))\n+#define SDIO_RSP0\t\t\t\t\t0x020\n+#define SDIO_RSP1\t\t\t\t\t0x024\n+#define SDIO_RSP2\t\t\t\t\t0x028\n+#define SDIO_RSP3\t\t\t\t\t0x02c\n+#define SDIO_RSP4\t\t\t\t\t0x030\n+#define SDIO_RSP5\t\t\t\t\t0x034\n+#define SDIO_RSP6\t\t\t\t\t0x038\n+#define SDIO_RSP7\t\t\t\t\t0x03c\n+#define SDIO_BUF_DATA_PORT\t\t\t0x040\n+#define SDIO_RSVED\t\t\t\t\t0x044\n+#define SDIO_HW_STATE\t\t\t\t0x048\n+#define SDIO_PRESENT_STATE0\t\t\t0x048\n+#define SDIO_PRESENT_STATE1\t\t\t0x04c\n+#define SDIO_HOST_CTRL\t\t\t\t0x050\n+#define SDIO_BLK_GAP_CTRL\t\t\t0x054\n+#define SDIO_CLK_CTRL\t\t\t\t0x058\n+#define SDIO_SW_RESET\t\t\t\t0x05c\n+#define SDIO_NOR_INTR_STATUS\t\t0x060\n+#define SDIO_ERR_INTR_STATUS\t\t0x064\n+#define SDIO_NOR_STATUS_EN\t\t\t0x068\n+#define SDIO_ERR_STATUS_EN\t\t\t0x06c\n+#define SDIO_NOR_INTR_EN\t\t\t0x070\n+#define SDIO_ERR_INTR_EN\t\t\t0x074\n+#define SDIO_AUTOCMD12_ERR_STATUS\t0x078\n+#define SDIO_CURR_BYTE_LEFT\t\t\t0x07c\n+#define SDIO_CURR_BLK_LEFT\t\t\t0x080\n+#define SDIO_AUTOCMD12_ARG_LOW\t\t0x084\n+#define SDIO_AUTOCMD12_ARG_HI\t\t0x088\n+#define SDIO_AUTOCMD12_INDEX\t\t0x08c\n+#define SDIO_AUTO_RSP(i)\t\t\t(0x090 + ((i)<<2))\n+#define SDIO_AUTO_RSP0\t\t\t\t0x090\n+#define SDIO_AUTO_RSP1\t\t\t\t0x094\n+#define SDIO_AUTO_RSP2\t\t\t\t0x098\n+#define SDIO_CLK_DIV\t\t\t\t0x128\n+\n+#define WINDOW_CTRL(i)\t\t\t\t(0x108 + ((i) << 3))\n+#define WINDOW_BASE(i)\t\t\t\t(0x10c + ((i) << 3))\n+\n+/* SDIO_PRESENT_STATE */\n+#define CARD_BUSY\t\t\t\t(1 << 1)\n+#define CMD_INHIBIT\t\t\t\t(1 << 0)\n+#define CMD_TXACTIVE\t\t\t(1 << 8)\n+#define CMD_RXACTIVE\t\t\t(1 << 9)\n+#define CMD_AUTOCMD12ACTIVE\t\t(1 << 14)\n+#define CMD_BUS_BUSY\t\t\t(CMD_AUTOCMD12ACTIVE |\t\\\n+\t\t\t\t\t\t\t\tCMD_RXACTIVE |\t\\\n+\t\t\t\t\t\t\t\tCMD_TXACTIVE |\t\\\n+\t\t\t\t\t\t\t\tCMD_INHIBIT |\t\\\n+\t\t\t\t\t\t\t\tCARD_BUSY)\n+\n+/*\n+ * SDIO_CMD\n+ */\n+\n+#define SDIO_CMD_RSP_NONE\t\t\t\t(0 << 0)\n+#define SDIO_CMD_RSP_136\t\t\t\t(1 << 0)\n+#define SDIO_CMD_RSP_48\t\t\t\t\t(2 << 0)\n+#define SDIO_CMD_RSP_48BUSY\t\t\t\t(3 << 0)\n+\n+#define SDIO_CMD_CHECK_DATACRC16\t\t(1 << 2)\n+#define SDIO_CMD_CHECK_CMDCRC\t\t\t(1 << 3)\n+#define SDIO_CMD_INDX_CHECK\t\t\t\t(1 << 4)\n+#define SDIO_CMD_DATA_PRESENT\t\t\t(1 << 5)\n+#define SDIO_UNEXPECTED_RESP\t\t\t(1 << 7)\n+\n+#define SDIO_CMD_INDEX(x)\t\t\t\t((x) << 8)\n+\n+/*\n+ * SDIO_XFER_MODE\n+ */\n+\n+#define SDIO_XFER_MODE_STOP_CLK\t\t\t(1 << 5)\n+#define SDIO_XFER_MODE_HW_WR_DATA_EN\t(1 << 1)\n+#define SDIO_XFER_MODE_AUTO_CMD12\t\t(1 << 2)\n+#define SDIO_XFER_MODE_INT_CHK_EN\t\t(1 << 3)\n+#define SDIO_XFER_MODE_TO_HOST\t\t\t(1 << 4)\n+#define SDIO_XFER_MODE_DMA\t\t\t\t(0 << 6)\n+\n+/*\n+ * SDIO_HOST_CTRL\n+ */\n+\n+#define SDIO_HOST_CTRL_PUSH_PULL_EN \t\t(1 << 0)\n+\n+#define SDIO_HOST_CTRL_CARD_TYPE_MEM_ONLY \t(0 << 1)\n+#define SDIO_HOST_CTRL_CARD_TYPE_IO_ONLY \t(1 << 1)\n+#define SDIO_HOST_CTRL_CARD_TYPE_IO_MEM_COMBO \t(2 << 1)\n+#define SDIO_HOST_CTRL_CARD_TYPE_IO_MMC \t(3 << 1)\n+#define SDIO_HOST_CTRL_CARD_TYPE_MASK\t \t(3 << 1)\n+\n+#define SDIO_HOST_CTRL_BIG_ENDIAN \t\t(1 << 3)\n+#define SDIO_HOST_CTRL_LSB_FIRST \t\t(1 << 4)\n+#define SDIO_HOST_CTRL_DATA_WIDTH_1_BIT \t(0 << 9)\n+#define SDIO_HOST_CTRL_DATA_WIDTH_4_BITS \t(1 << 9)\n+#define SDIO_HOST_CTRL_HI_SPEED_EN \t\t(1 << 10)\n+\n+#define SDIO_HOST_CTRL_TMOUT_MAX \t\t0xf\n+#define SDIO_HOST_CTRL_TMOUT_MASK \t\t(0xf << 11)\n+#define SDIO_HOST_CTRL_TMOUT(x) \t\t((x) << 11)\n+#define SDIO_HOST_CTRL_TMOUT_EN \t\t(1 << 15)\n+\n+/*\n+ * SDIO_SW_RESET\n+ */\n+\n+#define SDIO_SW_RESET_NOW\t\t\t(1 << 8)\n+\n+/*\n+ * Normal interrupt status bits\n+ */\n+\n+#define SDIO_NOR_ERROR\t\t\t\t(1 << 15)\n+#define SDIO_NOR_UNEXP_RSP\t\t\t(1 << 14)\n+#define SDIO_NOR_AUTOCMD12_DONE\t\t(1 << 13)\n+#define SDIO_NOR_SUSPEND_ON\t\t\t(1 << 12)\n+#define SDIO_NOR_LMB_FF_8W_AVAIL\t(1 << 11)\n+#define SDIO_NOR_LMB_FF_8W_FILLED\t(1 << 10)\n+#define SDIO_NOR_READ_WAIT_ON\t\t(1 << 9)\n+#define SDIO_NOR_CARD_INT\t\t\t(1 << 8)\n+#define SDIO_NOR_READ_READY\t\t\t(1 << 5)\n+#define SDIO_NOR_WRITE_READY\t\t(1 << 4)\n+#define SDIO_NOR_DMA_INI\t\t\t(1 << 3)\n+#define SDIO_NOR_BLK_GAP_EVT\t\t(1 << 2)\n+#define SDIO_NOR_XFER_DONE\t\t\t(1 << 1)\n+#define SDIO_NOR_CMD_DONE\t\t\t(1 << 0)\n+\n+/*\n+ * Error status bits\n+ */\n+\n+#define SDIO_ERR_CRC_STATUS\t\t\t(1 << 14)\n+#define SDIO_ERR_CRC_STARTBIT\t\t(1 << 13)\n+#define SDIO_ERR_CRC_ENDBIT\t\t\t(1 << 12)\n+#define SDIO_ERR_RESP_TBIT\t\t\t(1 << 11)\n+#define SDIO_ERR_XFER_SIZE\t\t\t(1 << 10)\n+#define SDIO_ERR_CMD_STARTBIT\t\t(1 << 9)\n+#define SDIO_ERR_AUTOCMD12\t\t\t(1 << 8)\n+#define SDIO_ERR_DATA_ENDBIT\t\t(1 << 6)\n+#define SDIO_ERR_DATA_CRC\t\t\t(1 << 5)\n+#define SDIO_ERR_DATA_TIMEOUT\t\t(1 << 4)\n+#define SDIO_ERR_CMD_INDEX\t\t\t(1 << 3)\n+#define SDIO_ERR_CMD_ENDBIT\t\t\t(1 << 2)\n+#define SDIO_ERR_CMD_CRC\t\t\t(1 << 1)\n+#define SDIO_ERR_CMD_TIMEOUT\t\t(1 << 0)\n+#define SDIO_POLL_MASK \t\t\t\t0xffff /* enable all for polling */\n+\n+#define MMC_BLOCK_SIZE                  512\n+\n+/*\n+ * CMD12 error status bits\n+ */\n+\n+#define SDIO_AUTOCMD12_ERR_NOTEXE\t\t(1 << 0)\n+#define SDIO_AUTOCMD12_ERR_TIMEOUT\t\t(1 << 1)\n+#define SDIO_AUTOCMD12_ERR_CRC\t\t\t(1 << 2)\n+#define SDIO_AUTOCMD12_ERR_ENDBIT\t\t(1 << 3)\n+#define SDIO_AUTOCMD12_ERR_INDEX\t\t(1 << 4)\n+#define SDIO_AUTOCMD12_ERR_RESP_T_BIT\t\t(1 << 5)\n+#define SDIO_AUTOCMD12_ERR_RESP_STARTBIT\t(1 << 6)\n+\n+#define MMC_RSP_PRESENT\t(1 << 0)\n+#define MMC_RSP_136\t(1 << 1)\t\t/* 136 bit response */\n+#define MMC_RSP_CRC\t(1 << 2)\t\t/* expect valid crc */\n+#define MMC_RSP_BUSY\t(1 << 3)\t\t/* card may send busy */\n+#define MMC_RSP_OPCODE\t(1 << 4)\t\t/* response contains opcode */\n+\n+#define MMC_BUSMODE_OPENDRAIN\t1\n+#define MMC_BUSMODE_PUSHPULL\t2\n+\n+#define MMC_BUS_WIDTH_1\t\t0\n+#define MMC_BUS_WIDTH_4\t\t2\n+#define MMC_BUS_WIDTH_8\t\t3\n+\n+#define MMC_CAP_4_BIT_DATA\t(1 << 0)\t/* Can the host do 4 bit transfers */\n+#define MMC_CAP_MMC_HIGHSPEED\t(1 << 1)\t/* Can do MMC high-speed timing */\n+#define MMC_CAP_SD_HIGHSPEED\t(1 << 2)\t/* Can do SD high-speed timing */\n+#define MMC_CAP_SDIO_IRQ\t(1 << 3)\t/* Can signal pending SDIO IRQs */\n+#define MMC_CAP_SPI\t\t(1 << 4)\t/* Talks only SPI protocols */\n+#define MMC_CAP_NEEDS_POLL\t(1 << 5)\t/* Needs polling for card-detection */\n+#define MMC_CAP_8_BIT_DATA\t(1 << 6)\t/* Can the host do 8 bit transfers */\n+\n+#define MMC_CAP_NONREMOVABLE\t(1 << 8)\t/* Nonremovable e.g. eMMC */\n+#define MMC_CAP_WAIT_WHILE_BUSY\t(1 << 9)\t/* Waits while card is busy */\n+#define MMC_CAP_ERASE\t\t(1 << 10)\t/* Allow erase/trim commands */\n+#define MMC_CAP_1_8V_DDR\t(1 << 11)\t/* can support */\n+\t\t\t\t\t\t/* DDR mode at 1.8V */\n+#define MMC_CAP_1_2V_DDR\t(1 << 12)\t/* can support */\n+\t\t\t\t\t\t/* DDR mode at 1.2V */\n+#define MMC_CAP_POWER_OFF_CARD\t(1 << 13)\t/* Can power off after boot */\n+#define MMC_CAP_BUS_WIDTH_TEST\t(1 << 14)\t/* CMD14/CMD19 bus width ok */\n+#define MMC_CAP_UHS_SDR12\t(1 << 15)\t/* Host supports UHS SDR12 mode */\n+#define MMC_CAP_UHS_SDR25\t(1 << 16)\t/* Host supports UHS SDR25 mode */\n+#define MMC_CAP_UHS_SDR50\t(1 << 17)\t/* Host supports UHS SDR50 mode */\n+#define MMC_CAP_UHS_SDR104\t(1 << 18)\t/* Host supports UHS SDR104 mode */\n+#define MMC_CAP_UHS_DDR50\t(1 << 19)\t/* Host supports UHS DDR50 mode */\n+#define MMC_CAP_DRIVER_TYPE_A\t(1 << 23)\t/* Host supports Driver Type A */\n+#define MMC_CAP_DRIVER_TYPE_C\t(1 << 24)\t/* Host supports Driver Type C */\n+#define MMC_CAP_DRIVER_TYPE_D\t(1 << 25)\t/* Host supports Driver Type D */\n+#define MMC_CAP_CMD23\t\t(1 << 30)\t/* CMD23 supported. */\n+#define MMC_CAP_HW_RESET\t(1 << 31)\t/* Hardware reset */\n+\n+/*\n+ * Functions prototypes\n+ *\n+ * Original patch had static function declarations in this header file.\n+ * Those should rather not be declared in the header as they only cause compiler warnings.\n+ */\n+int kw_mmc_initialize(bd_t *bis);\n+\n+#endif /* __KIRKWOOD_MMC_H__ */\n"
  },
  {
    "path": "package/boot/uboot-kirkwood/patches/110-dockstar.patch",
    "content": "--- a/include/configs/dockstar.h\n+++ b/include/configs/dockstar.h\n@@ -17,6 +17,7 @@\n #define CONFIG_FEROCEON_88FR131\t1\t/* CPU Core subversion */\n #define CONFIG_KW88F6281\t1\t/* SOC Name */\n #define CONFIG_SKIP_LOWLEVEL_INIT\t/* disable board lowlevel_init */\n+#define CONFIG_SYS_MVFS\n \n /*\n  * mv-common.h should be defined after CMD configs since it used them\n@@ -37,19 +38,15 @@\n  */\n #define CONFIG_BOOTCOMMAND \\\n \t\"setenv bootargs ${console} ${mtdparts} ${bootargs_root}; \"\t\\\n-\t\"ubi part root; \" \\\n-\t\"ubifsmount ubi:root; \" \\\n-\t\"ubifsload 0x800000 ${kernel}; \" \\\n-\t\"ubifsload 0x1100000 ${initrd}; \" \\\n-\t\"bootm 0x800000 0x1100000\"\n+\t\"ubi part ubi; \" \\\n+\t\"ubi read 0x800000 kernel; \" \\\n+\t\"bootm 0x800000\"\n \n #define CONFIG_EXTRA_ENV_SETTINGS \\\n-\t\"console=console=ttyS0,115200\\0\" \\\n-\t\"mtdids=nand0=orion_nand\\0\" \\\n-\t\"mtdparts=\"CONFIG_MTDPARTS_DEFAULT \\\n-\t\"kernel=/boot/uImage\\0\" \\\n-\t\"initrd=/boot/uInitrd\\0\" \\\n-\t\"bootargs_root=ubi.mtd=1 root=ubi0:root rootfstype=ubifs ro\\0\"\n+\t\"console=console=ttyS0,115200\\0\"\t\\\n+\t\"mtdids=nand0=orion_nand\\0\"\t\t\\\n+\t\"mtdparts=\"CONFIG_MTDPARTS_DEFAULT \"\\0\"\t\\\n+\t\"bootargs_root=\\0\"\n \n /*\n  * Ethernet Driver configuration\n--- a/configs/dockstar_defconfig\n+++ b/configs/dockstar_defconfig\n@@ -5,7 +5,7 @@ CONFIG_KIRKWOOD=y\n CONFIG_SYS_TEXT_BASE=0x600000\n CONFIG_TARGET_DOCKSTAR=y\n CONFIG_ENV_SIZE=0x20000\n-CONFIG_ENV_OFFSET=0x80000\n+CONFIG_ENV_OFFSET=0xE0000\n CONFIG_NR_DRAM_BANKS=2\n CONFIG_IDENT_STRING=\"\\nSeagate FreeAgent DockStar\"\n CONFIG_BOOTDELAY=3\n@@ -23,7 +23,7 @@ CONFIG_CMD_EXT2=y\n CONFIG_CMD_FAT=y\n CONFIG_CMD_JFFS2=y\n CONFIG_CMD_MTDPARTS=y\n-CONFIG_MTDPARTS_DEFAULT=\"mtdparts=orion_nand:1m(uboot),-(root)\"\n+CONFIG_MTDPARTS_DEFAULT=\"mtdparts=orion_nand:0xe0000@0x0(uboot),0x20000@0xe0000(uboot_env),0x100000@0x100000(second_stage_uboot),-@0x200000(ubi)\"\n CONFIG_CMD_UBI=y\n CONFIG_ISO_PARTITION=y\n CONFIG_OF_CONTROL=y\n"
  },
  {
    "path": "package/boot/uboot-kirkwood/patches/120-iconnect.patch",
    "content": "--- a/include/configs/iconnect.h\n+++ b/include/configs/iconnect.h\n@@ -44,17 +44,15 @@\n  */\n #define CONFIG_BOOTCOMMAND \\\n \t\"setenv bootargs ${console} ${mtdparts} ${bootargs_root}; \"\t\\\n-\t\"ubi part rootfs; \"\t\t\t\t\t\t\\\n-\t\"ubifsmount ubi:rootfs; \"\t\t\t\t\t\\\n-\t\"ubifsload 0x800000 ${kernel}; \"\t\t\t\t\\\n+\t\"ubi part ubi; \" \\\n+\t\"ubi read 0x800000 kernel; \" \\\n \t\"bootm 0x800000\"\n \n #define CONFIG_EXTRA_ENV_SETTINGS \\\n \t\"console=console=ttyS0,115200\\0\"\t\\\n \t\"mtdids=nand0=orion_nand\\0\"\t\t\\\n-\t\"mtdparts=\"CONFIG_MTDPARTS_DEFAULT\t\\\n-\t\"kernel=/boot/uImage\\0\"\t\t\t\\\n-\t\"bootargs_root=noinitrd ubi.mtd=2 root=ubi0:rootfs rootfstype=ubifs\\0\"\n+\t\"mtdparts=\"CONFIG_MTDPARTS_DEFAULT \"\\0\"\t\\\n+\t\"bootargs_root=\\0\"\n \n /*\n  * Ethernet driver configuration\n--- a/configs/iconnect_defconfig\n+++ b/configs/iconnect_defconfig\n@@ -5,7 +5,7 @@ CONFIG_KIRKWOOD=y\n CONFIG_SYS_TEXT_BASE=0x600000\n CONFIG_TARGET_ICONNECT=y\n CONFIG_ENV_SIZE=0x20000\n-CONFIG_ENV_OFFSET=0x80000\n+CONFIG_ENV_OFFSET=0xE0000\n CONFIG_NR_DRAM_BANKS=2\n CONFIG_IDENT_STRING=\" Iomega iConnect\"\n CONFIG_BOOTDELAY=3\n@@ -16,13 +16,14 @@ CONFIG_SYS_PROMPT=\"iconnect => \"\n CONFIG_CMD_NAND=y\n CONFIG_CMD_USB=y\n # CONFIG_CMD_SETEXPR is not set\n+CONFIG_CMD_DHCP=y\n CONFIG_CMD_MII=y\n CONFIG_CMD_PING=y\n CONFIG_CMD_EXT2=y\n CONFIG_CMD_FAT=y\n CONFIG_CMD_JFFS2=y\n CONFIG_CMD_MTDPARTS=y\n-CONFIG_MTDPARTS_DEFAULT=\"mtdparts=orion_nand:0x80000@0x0(uboot),0x20000@0x80000(uboot_env),-@0xa0000(rootfs)\"\n+CONFIG_MTDPARTS_DEFAULT=\"mtdparts=orion_nand:0xe0000@0x0(uboot),0x20000@0xe0000(uboot_env),0x100000@0x100000(second_stage_uboot),-@0x200000(ubi)\"\n CONFIG_CMD_UBI=y\n CONFIG_ISO_PARTITION=y\n CONFIG_OF_CONTROL=y\n"
  },
  {
    "path": "package/boot/uboot-kirkwood/patches/130-ib62x0.patch",
    "content": "--- a/include/configs/ib62x0.h\n+++ b/include/configs/ib62x0.h\n@@ -39,21 +39,15 @@\n  */\n #define CONFIG_BOOTCOMMAND \\\n \t\"setenv bootargs ${console} ${mtdparts} ${bootargs_root}; \"\t\\\n-\t\"ubi part root; \"\t\t\t\t\t\t\\\n-\t\"ubifsmount ubi:rootfs; \"\t\t\t\t\t\\\n-\t\"ubifsload 0x800000 ${kernel}; \"\t\t\t\t\\\n-\t\"ubifsload 0x700000 ${fdt}; \"\t\t\t\t\t\\\n-\t\"ubifsumount; \"\t\t\t\t\t\t\t\\\n-\t\"fdt addr 0x700000; fdt resize; fdt chosen; \"\t\t\t\\\n-\t\"bootz 0x800000 - 0x700000\"\n+\t\"ubi part ubi; \" \\\n+\t\"ubi read 0x800000 kernel; \" \\\n+\t\"bootm 0x800000\"\n \n #define CONFIG_EXTRA_ENV_SETTINGS \\\n \t\"console=console=ttyS0,115200\\0\"\t\t\t\t\\\n \t\"mtdids=nand0=orion_nand\\0\"\t\t\t\t\t\\\n-\t\"mtdparts=\"CONFIG_MTDPARTS_DEFAULT\t\t\t\\\n-\t\"kernel=/boot/zImage\\0\"\t\t\t\t\t\t\\\n-\t\"fdt=/boot/ib62x0.dtb\\0\"\t\t\t\t\t\\\n-\t\"bootargs_root=ubi.mtd=2 root=ubi0:rootfs rootfstype=ubifs rw\\0\"\n+\t\"mtdparts=\"CONFIG_MTDPARTS_DEFAULT \"\\0\"\t\t\t\\\n+\t\"bootargs_root=\\0\"\n \n /*\n  * Ethernet driver configuration\n--- a/configs/ib62x0_defconfig\n+++ b/configs/ib62x0_defconfig\n@@ -26,7 +26,7 @@ CONFIG_CMD_EXT2=y\n CONFIG_CMD_FAT=y\n CONFIG_CMD_JFFS2=y\n CONFIG_CMD_MTDPARTS=y\n-CONFIG_MTDPARTS_DEFAULT=\"mtdparts=orion_nand:0xe0000@0x0(uboot),0x20000@0xe0000(uboot_env),-@0x100000(root)\"\n+CONFIG_MTDPARTS_DEFAULT=\"mtdparts=orion_nand:0xe0000@0x0(uboot),0x20000@0xe0000(uboot_env),0x100000@0x100000(second_stage_uboot),-@0x200000(ubi)\"\n CONFIG_CMD_UBI=y\n CONFIG_ISO_PARTITION=y\n CONFIG_OF_CONTROL=y\n"
  },
  {
    "path": "package/boot/uboot-kirkwood/patches/140-pogoplug_e02.patch",
    "content": "--- a/include/configs/pogo_e02.h\n+++ b/include/configs/pogo_e02.h\n@@ -42,17 +42,17 @@\n  * Default environment variables\n  */\n #define CONFIG_BOOTCOMMAND \\\n-\t\"setenv bootargs $(bootargs_console); \" \\\n-\t\"run bootcmd_usb; \" \\\n-\t\"bootm 0x00800000 0x01100000\"\n+\t\"setenv bootargs ${console} ${mtdparts} ${bootargs_root}; \"\t\\\n+\t\"ubi part ubi; \"\t\t\t\t\t\t\\\n+\t\"ubifsmount ubi:rootfs; \"\t\t\t\t\t\\\n+\t\"ubi read 0x800000 kernel; \"\t\t\t\t\t\\\n+\t\"bootm 0x800000\"\n \n #define CONFIG_EXTRA_ENV_SETTINGS \\\n-\t\"mtdparts=mtdparts=orion_nand:1M(u-boot),4M(uImage),\" \\\n-\t\"32M(rootfs),-(data)\\0\"\\\n-\t\"mtdids=nand0=orion_nand\\0\"\\\n-\t\"bootargs_console=console=ttyS0,115200\\0\" \\\n-\t\"bootcmd_usb=usb start; ext2load usb 0:1 0x00800000 /uImage; \" \\\n-\t\"ext2load usb 0:1 0x01100000 /uInitrd\\0\"\n+\t\"console=console=ttyS0,115200\\0\"\t\\\n+\t\"mtdids=nand0=orion_nand\\0\"\t\t\\\n+\t\"mtdparts=\"CONFIG_MTDPARTS_DEFAULT \"\\0\"\t\\\n+\t\"bootargs_root=\\0\"\n \n /*\n  * Ethernet Driver configuration\n--- a/configs/pogo_e02_defconfig\n+++ b/configs/pogo_e02_defconfig\n@@ -5,7 +5,7 @@ CONFIG_KIRKWOOD=y\n CONFIG_SYS_TEXT_BASE=0x600000\n CONFIG_TARGET_POGO_E02=y\n CONFIG_ENV_SIZE=0x20000\n-CONFIG_ENV_OFFSET=0x60000\n+CONFIG_ENV_OFFSET=0xE0000\n CONFIG_NR_DRAM_BANKS=2\n CONFIG_IDENT_STRING=\"\\nPogo E02\"\n CONFIG_BOOTDELAY=3\n@@ -23,6 +23,7 @@ CONFIG_CMD_EXT2=y\n CONFIG_CMD_FAT=y\n CONFIG_CMD_JFFS2=y\n CONFIG_CMD_MTDPARTS=y\n+CONFIG_MTDPARTS_DEFAULT=\"mtdparts=orion_nand:0xe0000@0x0(uboot),0x20000@0xe0000(uboot_env),0x100000@0x100000(second_stage_uboot),-@0x200000(ubi)\"\n CONFIG_CMD_UBI=y\n CONFIG_ISO_PARTITION=y\n CONFIG_OF_CONTROL=y\n"
  },
  {
    "path": "package/boot/uboot-kirkwood/patches/150-goflexhome.patch",
    "content": "--- a/include/configs/goflexhome.h\n+++ b/include/configs/goflexhome.h\n@@ -60,17 +60,15 @@\n  */\n #define CONFIG_BOOTCOMMAND \\\n \t\"setenv bootargs ${console} ${mtdparts} ${bootargs_root}; \" \\\n-\t\"ubi part root; \" \\\n-\t\"ubifsmount ubi:root; \" \\\n-\t\"ubifsload 0x800000 ${kernel}; \" \\\n+\t\"ubi part ubi; \" \\\n+\t\"ubi read 0x800000 kernel; \" \\\n \t\"bootm 0x800000\"\n \n #define CONFIG_EXTRA_ENV_SETTINGS \\\n \t\"console=console=ttyS0,115200\\0\" \\\n \t\"mtdids=nand0=orion_nand\\0\" \\\n-\t\"mtdparts=\"CONFIG_MTDPARTS_DEFAULT \\\n-\t\"kernel=/boot/uImage\\0\" \\\n-\t\"bootargs_root=ubi.mtd=root root=ubi0:root rootfstype=ubifs ro\\0\"\n+\t\"mtdparts=\"CONFIG_MTDPARTS_DEFAULT \"\\0\" \\\n+\t\"bootargs_root=\\0\"\n \n /*\n  * Ethernet Driver configuration\n--- a/configs/goflexhome_defconfig\n+++ b/configs/goflexhome_defconfig\n@@ -28,7 +28,7 @@ CONFIG_CMD_FAT=y\n CONFIG_CMD_JFFS2=y\n CONFIG_CMD_MTDPARTS=y\n CONFIG_MTDIDS_DEFAULT=\"nand0=orion_nand\"\n-CONFIG_MTDPARTS_DEFAULT=\"mtdparts=orion_nand:1m(uboot),6M(uImage),-(root)\"\n+CONFIG_MTDPARTS_DEFAULT=\"mtdparts=orion_nand:1m(uboot),255m(ubi)\"\n CONFIG_CMD_UBI=y\n CONFIG_ISO_PARTITION=y\n CONFIG_OF_CONTROL=y\n"
  },
  {
    "path": "package/boot/uboot-kirkwood/patches/151-arm-kirkwood-add-CheckPoint-L-50-device.patch",
    "content": "From 742f780f62ace452b83e2463f1f1afdda4b724ea Mon Sep 17 00:00:00 2001\nFrom: Pawel Dembicki <paweldembicki@gmail.com>\nDate: Sun, 26 Jan 2020 07:27:24 +0100\nSubject: [PATCH] arm: kirkwood: add CheckPoint L-50 device\n\nThis patch adds support for the Check Point L-50 from 600/1100 series\nrouters.\n\nSpecification:\n-CPU: Marvell Kirkwood 88F6821 1200MHz\n-RAM: 512MB\n-Flash: NAND 512MB\n-WiFi: mPCIe card based on Atheros AR9287 b/g/n\n-WAN: 1 Gigabit Port (Marvell 88E1116R PHY)\n-LAN: 9 Gigabit Ports (2x Marvell 88E6171(5+4))\n-USB: 2x USB2.0\n-Express card slot\n-SD card slot\n-Serial console: RJ-45 115200 8n1\n-Unsupported DSL\n\nKnown limitations:\n- In board is used two switches in chain. Second Marvell is not used\n  in u-Boot.\n\nSigned-off-by: Pawel Dembicki <paweldembicki@gmail.com>\n---\n arch/arm/dts/Makefile              |   1 +\n arch/arm/dts/kirkwood-l-50.dts     | 439 +++++++++++++++++++++++++++++\n arch/arm/mach-kirkwood/Kconfig     |   4 +\n board/checkpoint/l-50/Kconfig      |  12 +\n board/checkpoint/l-50/MAINTAINERS  |   6 +\n board/checkpoint/l-50/Makefile     |  11 +\n board/checkpoint/l-50/kwbimage.cfg |  36 +++\n board/checkpoint/l-50/l-50.c       | 172 +++++++++++\n board/checkpoint/l-50/l-50.h       |  29 ++\n configs/l-50_defconfig             |  59 ++++\n include/configs/l-50.h             |  59 ++++\n 11 files changed, 828 insertions(+)\n create mode 100644 arch/arm/dts/kirkwood-l-50.dts\n create mode 100644 board/checkpoint/l-50/Kconfig\n create mode 100644 board/checkpoint/l-50/MAINTAINERS\n create mode 100644 board/checkpoint/l-50/Makefile\n create mode 100644 board/checkpoint/l-50/kwbimage.cfg\n create mode 100644 board/checkpoint/l-50/l-50.c\n create mode 100644 board/checkpoint/l-50/l-50.h\n create mode 100644 configs/l-50_defconfig\n create mode 100644 include/configs/l-50.h\n\n--- a/arch/arm/dts/Makefile\n+++ b/arch/arm/dts/Makefile\n@@ -51,6 +51,7 @@ dtb-$(CONFIG_KIRKWOOD) += \\\n \tkirkwood-iconnect.dtb \\\n \tkirkwood-is2.dtb \\\n \tkirkwood-km_kirkwood.dtb \\\n+\tkirkwood-l-50.dtb \\\n \tkirkwood-lsxhl.dtb \\\n \tkirkwood-lschlv2.dtb \\\n \tkirkwood-net2big.dtb \\\n--- /dev/null\n+++ b/arch/arm/dts/kirkwood-l-50.dts\n@@ -0,0 +1,439 @@\n+// SPDX-License-Identifier: GPL-2.0\n+/*\n+ * Check Point L-50 Board Description\n+ * Copyright 2020 Pawel Dembicki <paweldembicki@gmail.com>\n+ */\n+\n+/dts-v1/;\n+\n+#include \"kirkwood.dtsi\"\n+#include \"kirkwood-6281.dtsi\"\n+\n+/ {\n+\tmodel = \"Check Point L-50\";\n+\tcompatible = \"checkpoint,l-50\", \"marvell,kirkwood-88f6281\", \"marvell,kirkwood\";\n+\n+\tmemory {\n+\t\tdevice_type = \"memory\";\n+\t\treg = <0x00000000 0x20000000>;\n+\t};\n+\n+\tchosen {\n+\t\tbootargs = \"console=ttyS0,115200n8\";\n+\t\tstdout-path = &uart0;\n+\t};\n+\n+\tocp@f1000000 {\n+\t\tpinctrl: pin-controller@10000 {\n+\t\t\tpinctrl-0 = <&pmx_led38 &pmx_sysrst &pmx_button29>;\n+\t\t\tpinctrl-names = \"default\";\n+\n+\t\t\tpmx_sysrst: pmx-sysrst {\n+\t\t\t\tmarvell,pins = \"mpp6\";\n+\t\t\t\tmarvell,function = \"sysrst\";\n+\t\t\t};\n+\n+\t\t\tpmx_button29: pmx_button29 {\n+\t\t\t\tmarvell,pins = \"mpp29\";\n+\t\t\t\tmarvell,function = \"gpio\";\n+\t\t\t};\n+\n+\t\t\tpmx_led38: pmx_led38 {\n+\t\t\t\tmarvell,pins = \"mpp38\";\n+\t\t\t\tmarvell,function = \"gpio\";\n+\t\t\t};\n+\n+\t\t\tpmx_sdio_cd: pmx-sdio-cd {\n+\t\t\t\tmarvell,pins = \"mpp46\";\n+\t\t\t\tmarvell,function = \"gpio\";\n+\t\t\t};\n+\t\t};\n+\n+\t\tserial@12000 {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\n+\t\tmvsdio@90000 {\n+\t\t\tstatus = \"okay\";\n+\t\t\tcd-gpios = <&gpio1 14 9>;\n+\t\t};\n+\n+\t\ti2c@11000 {\n+\t\t\tstatus = \"okay\";\n+\t\t\tclock-frequency = <400000>;\n+\n+\t\t\tgpio2: gpio-expander@20{\n+\t\t\t\t#gpio-cells = <2>;\n+\t\t\t\t#interrupt-cells = <2>;\n+\t\t\t\tcompatible = \"semtech,sx1505q\";\n+\t\t\t\treg = <0x20>;\n+\n+\t\t\t\tgpio-controller;\n+\t\t\t};\n+\n+\t\t\t/* Three GPIOs from 0x21 exp. are undescribed in dts:\n+\t\t\t * 1: DSL module reset (active low)\n+\t\t\t * 5: mPCIE reset (active low)\n+\t\t\t * 6: Express card reset (active low)\n+\t\t\t */\n+\t\t\tgpio3: gpio-expander@21{\n+\t\t\t\t#gpio-cells = <2>;\n+\t\t\t\t#interrupt-cells = <2>;\n+\t\t\t\tcompatible = \"semtech,sx1505q\";\n+\t\t\t\treg = <0x21>;\n+\n+\t\t\t\tgpio-controller;\n+\t\t\t};\n+\n+\t\t\trtc@30 {\n+\t\t\t\tcompatible = \"s35390a\";\n+\t\t\t\treg = <0x30>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tleds {\n+\t\tcompatible = \"gpio-leds\";\n+\n+\t\tstatus_green {\n+\t\t\tlabel = \"l-50:green:status\";\n+\t\t\tgpios = <&gpio1 6 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\n+\t\tstatus_red {\n+\t\t\tlabel = \"l-50:red:status\";\n+\t\t\tgpios = <&gpio3 2 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\n+\t\twifi {\n+\t\t\tlabel = \"l-50:green:wifi\";\n+\t\t\tgpios = <&gpio2 7 GPIO_ACTIVE_LOW>;\n+\t\t\tlinux,default-trigger = \"phy0tpt\";\n+\t\t};\n+\n+\t\tinternet_green {\n+\t\t\tlabel = \"l-50:green:internet\";\n+\t\t\tgpios = <&gpio2 3 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\n+\t\tinternet_red {\n+\t\t\tlabel = \"l-50:red:internet\";\n+\t\t\tgpios = <&gpio2 1 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\n+\t\tusb1_green {\n+\t\t\tlabel = \"l-50:green:usb1\";\n+\t\t\tgpios = <&gpio2 0 GPIO_ACTIVE_LOW>;\n+\t\t\tlinux,default-trigger = \"usbport\";\n+\t\t\ttrigger-sources = <&hub_port3>;\n+\t\t};\n+\n+\t\tusb1_red {\n+\t\t\tlabel = \"l-50:red:usb1\";\n+\t\t\tgpios = <&gpio2 4 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\n+\t\tusb2_green {\n+\t\t\tlabel = \"l-50:green:usb2\";\n+\t\t\tgpios = <&gpio2 2 GPIO_ACTIVE_LOW>;\n+\t\t\tlinux,default-trigger = \"usbport\";\n+\t\t\ttrigger-sources = <&hub_port1>;\n+\t\t};\n+\n+\t\tusb2_red {\n+\t\t\tlabel = \"l-50:red:usb2\";\n+\t\t\tgpios = <&gpio2 5 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\t};\n+\n+\tusb2_pwr {\n+\t\tcompatible = \"regulator-fixed\";\n+\t\tregulator-name = \"usb2_pwr\";\n+\n+\t\tregulator-min-microvolt = <5000000>;\n+\t\tregulator-max-microvolt = <5000000>;\n+\t\tgpio = <&gpio3 3 GPIO_ACTIVE_LOW>;\n+\t\tregulator-always-on;\n+\t};\n+\n+\tusb1_pwr {\n+\t\tcompatible = \"regulator-fixed\";\n+\t\tregulator-name = \"usb1_pwr\";\n+\n+\t\tregulator-min-microvolt = <5000000>;\n+\t\tregulator-max-microvolt = <5000000>;\n+\t\tgpio = <&gpio3 4 GPIO_ACTIVE_LOW>;\n+\t\tregulator-always-on;\n+\t};\n+\n+\tmpcie_pwr {\n+\t\tcompatible = \"regulator-fixed\";\n+\t\tregulator-name = \"mpcie_pwr\";\n+\n+\t\tregulator-min-microvolt = <3300000>;\n+\t\tregulator-max-microvolt = <3300000>;\n+\t\tgpio = <&gpio3 5 GPIO_ACTIVE_HIGH>;\n+\t\tenable-active-high;\n+\t\tregulator-always-on;\n+\t};\n+\n+\texpress_card_pwr {\n+\t\tcompatible = \"regulator-fixed\";\n+\t\tregulator-name = \"express_card_pwr\";\n+\n+\t\tregulator-min-microvolt = <3300000>;\n+\t\tregulator-max-microvolt = <3300000>;\n+\t\tgpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;\n+\t\tenable-active-high;\n+\t\tregulator-always-on;\n+\t};\n+\n+\tkeys {\n+\t\tcompatible = \"gpio-keys\";\n+\n+\t\tfactory_defaults {\n+\t\t\tlabel = \"factory_defaults\";\n+\t\t\tgpios = <&gpio0 29 GPIO_ACTIVE_LOW>;\n+\t\t\tlinux,code = <KEY_RESTART>;\n+\t\t};\n+\t};\n+};\n+\n+&mdio {\n+\tstatus = \"okay\";\n+\n+\tethphy8: ethernet-phy@8 {\n+\t\treg = <0x08>;\n+\t};\n+\n+\tswitch0: switch@10 {\n+\t\tcompatible = \"marvell,mv88e6085\";\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\treg = <0x10>;\n+\t\tdsa,member = <0 0>;\n+\n+\t\tports {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tport@0 {\n+\t\t\t\treg = <0>;\n+\t\t\t\tlabel = \"lan5\";\n+\t\t\t};\n+\n+\t\t\tport@1 {\n+\t\t\t       reg = <1>;\n+\t\t\t       label = \"lan1\";\n+\t\t\t};\n+\n+\t\t\tport@2 {\n+\t\t\t       reg = <2>;\n+\t\t\t       label = \"lan6\";\n+\t\t\t};\n+\n+\t\t\tport@3 {\n+\t\t\t       reg = <3>;\n+\t\t\t       label = \"lan2\";\n+\t\t\t};\n+\n+\t\t\tport@4 {\n+\t\t\t\treg = <4>;\n+\t\t\t\tlabel = \"lan7\";\n+\t\t\t};\n+\n+\t\t\tswitch0port5: port@5 {\n+\t\t\t\treg = <5>;\n+\t\t\t\tphy-mode = \"rgmii-txid\";\n+\t\t\t\tlink = <&switch1port5>;\n+\t\t\t\tfixed-link {\n+\t\t\t\t\tspeed = <1000>;\n+\t\t\t\t\tfull-duplex;\n+\t\t\t\t};\n+\t\t\t};\n+\n+\t\t\tport@6 {\n+\t\t\t\treg = <6>;\n+\t\t\t\tlabel = \"cpu\";\n+\t\t\t\tphy-mode = \"rgmii-id\";\n+\t\t\t\tethernet = <&eth1port>;\n+\t\t\t\tfixed-link {\n+\t\t\t\t\tspeed = <1000>;\n+\t\t\t\t\tfull-duplex;\n+\t\t\t\t};\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tswitch@11 {\n+\t\tcompatible = \"marvell,mv88e6085\";\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\treg = <0x11>;\n+\t\tdsa,member = <0 1>;\n+\n+\t\tports {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tport@0 {\n+\t\t\t\treg = <0>;\n+\t\t\t\tlabel = \"lan3\";\n+\t\t\t};\n+\n+\t\t\tport@1 {\n+\t\t\t       reg = <1>;\n+\t\t\t       label = \"lan8\";\n+\t\t\t};\n+\n+\t\t\tport@2 {\n+\t\t\t       reg = <2>;\n+\t\t\t       label = \"lan4\";\n+\t\t\t};\n+\n+\t\t\tport@3 {\n+\t\t\t       reg = <3>;\n+\t\t\t       label = \"dmz\";\n+\t\t\t};\n+\n+\t\t\tswitch1port5: port@5 {\n+\t\t\t\treg = <5>;\n+\t\t\t\tphy-mode = \"rgmii-txid\";\n+\t\t\t\tlink = <&switch0port5>;\n+\t\t\t\tfixed-link {\n+\t\t\t\t\tspeed = <1000>;\n+\t\t\t\t\tfull-duplex;\n+\t\t\t\t};\n+\t\t\t};\n+\n+\t\t\tport@6 {\n+\t\t\t\treg = <6>;\n+\t\t\t\tlabel = \"dsl\";\n+\t\t\t\tfixed-link {\n+\t\t\t\t\tspeed = <100>;\n+\t\t\t\t\tfull-duplex;\n+\t\t\t\t};\n+\t\t\t};\n+\t\t};\n+\t};\n+};\n+\n+&eth0 {\n+\tstatus = \"okay\";\n+\tethernet0-port@0 {\n+\t\tphy-handle = <&ethphy8>;\n+\t};\n+};\n+\n+&eth1 {\n+\tstatus = \"okay\";\n+\tethernet1-port@0 {\n+\t\tspeed = <1000>;\n+\t\tduplex = <1>;\n+\t\tphy-handle = <&switch0>;\n+\t};\n+};\n+\n+&nand {\n+\tstatus = \"okay\";\n+\tpinctrl-0 = <&pmx_nand>;\n+\tpinctrl-names = \"default\";\n+\n+\tpartition@0 {\n+\t\tlabel = \"u-boot\";\n+\t\treg = <0x00000000 0x000c0000>;\n+\t};\n+\n+\tpartition@a0000 {\n+\t\tlabel = \"bootldr-env\";\n+\t\treg = <0x000c0000 0x00040000>;\n+\t};\n+\n+\tpartition@100000 {\n+\t\tlabel = \"kernel-1\";\n+\t\treg = <0x00100000 0x00800000>;\n+\t};\n+\n+\tpartition@900000 {\n+\t\tlabel = \"rootfs-1\";\n+\t\treg = <0x00900000 0x07100000>;\n+\t};\n+\n+\tpartition@7a00000 {\n+\t\tlabel = \"kernel-2\";\n+\t\treg = <0x07a00000 0x00800000>;\n+\t};\n+\n+\tpartition@8200000 {\n+\t\tlabel = \"rootfs-2\";\n+\t\treg = <0x08200000 0x07100000>;\n+\t};\n+\n+\tpartition@f300000 {\n+\t\tlabel = \"default_sw\";\n+\t\treg = <0x0f300000 0x07900000>;\n+\t};\n+\n+\tpartition@16c00000 {\n+\t\tlabel = \"logs\";\n+\t\treg = <0x16c00000 0x01800000>;\n+\t};\n+\n+\tpartition@18400000 {\n+\t\tlabel = \"preset_cfg\";\n+\t\treg = <0x18400000 0x00100000>;\n+\t};\n+\n+\tpartition@18500000 {\n+\t\tlabel = \"adsl\";\n+\t\treg = <0x18500000 0x00100000>;\n+\t};\n+\n+\tpartition@18600000 {\n+\t\tlabel = \"storage\";\n+\t\treg = <0x18600000 0x07a00000>;\n+\t};\n+};\n+\n+&rtc {\n+\tstatus = \"disabled\";\n+};\n+\n+&pciec {\n+\tstatus = \"okay\";\n+};\n+\n+&pcie0 {\n+\tstatus = \"okay\";\n+};\n+\n+&sata_phy0 {\n+\tstatus = \"disabled\";\n+};\n+\n+&sata_phy1 {\n+\tstatus = \"disabled\";\n+};\n+\n+&usb0 {\n+\t#address-cells = <1>;\n+\t#size-cells = <0>;\n+\tstatus = \"okay\";\n+\n+\tport@1 {\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\treg = <1>;\n+\t\t#trigger-source-cells = <0>;\n+\n+\t\thub_port1: port@1 {\n+\t\t\treg = <1>;\n+\t\t\t#trigger-source-cells = <0>;\n+\t\t};\n+\n+\t\thub_port3: port@3 {\n+\t\t\treg = <3>;\n+\t\t\t#trigger-source-cells = <0>;\n+\t\t};\n+\t};\n+};\n--- a/arch/arm/mach-kirkwood/Kconfig\n+++ b/arch/arm/mach-kirkwood/Kconfig\n@@ -74,6 +74,9 @@ config TARGET_DB_88F6281_BP\n config TARGET_NSA325\n \tbool \"Zyxel NSA325 board\"\n \n+config TARGET_L50\n+\tbool \"Check Point L-50\"\n+\n endchoice\n \n config SYS_SOC\n@@ -102,5 +105,6 @@ source \"board/zyxel/nsa325/Kconfig\"\n source \"board/alliedtelesis/SBx81LIFKW/Kconfig\"\n source \"board/alliedtelesis/SBx81LIFXCAT/Kconfig\"\n source \"board/Marvell/db-88f6281-bp/Kconfig\"\n+source \"board/checkpoint/l-50/Kconfig\"\n \n endif\n--- /dev/null\n+++ b/board/checkpoint/l-50/Kconfig\n@@ -0,0 +1,12 @@\n+if TARGET_L50\n+\n+config SYS_BOARD\n+\tdefault \"l-50\"\n+\n+config SYS_VENDOR\n+\tdefault \"checkpoint\"\n+\n+config SYS_CONFIG_NAME\n+\tdefault \"l-50\"\n+\n+endif\n--- /dev/null\n+++ b/board/checkpoint/l-50/MAINTAINERS\n@@ -0,0 +1,6 @@\n+L50 BOARD\n+M:\tPawel Dembicki <paweldembicki@gmail.com>\n+S:\tMaintained\n+F:\tboard/checkpoint/l-50/\n+F:\tinclude/configs/l-50.h\n+F:\tconfigs/l-50_defconfig\n--- /dev/null\n+++ b/board/checkpoint/l-50/Makefile\n@@ -0,0 +1,11 @@\n+# SPDX-License-Identifier: GPL-2.0+\n+#\n+# (C) Copyright 2020\n+# Pawel Dembicki <paweldembicki@gmail.com>\n+#\n+# Based on Kirkwood support:\n+# (C) Copyright 2009\n+# Marvell Semiconductor <www.marvell.com>\n+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>\n+\n+obj-y\t:= l-50.o\n--- /dev/null\n+++ b/board/checkpoint/l-50/kwbimage.cfg\n@@ -0,0 +1,36 @@\n+# SPDX-License-Identifier: GPL-2.0+\n+#\n+# Values taken from original bootloader source.\n+# Based on:\n+# dramregs_seattle_400rd_A.txt from uboot_src_CP600_1100.\n+\n+# Boot Media configurations\n+BOOT_FROM\tnand\n+NAND_ECC_MODE\tdefault\n+NAND_PAGE_SIZE\t0x0800\n+\n+DATA 0xFFD100e0 0x1b1b1b9b\n+DATA 0xFFD01400 0x43000c30\n+DATA 0xFFD01404 0x39543000\n+DATA 0xFFD01408 0x22125451\n+DATA 0xFFD0140C 0x00000833\n+DATA 0xFFD01410 0x000000cc\n+DATA 0xFFD01414 0x00000000\n+DATA 0xFFD01418 0x00000000\n+DATA 0xFFD0141C 0x00000C52\n+DATA 0xFFD01420 0x00000004\n+DATA 0xFFD01424 0x0000F17F\n+DATA 0xFFD01428 0x00085520\n+DATA 0xFFD0147C 0x00008552\n+DATA 0xFFD01504 0x0FFFFFF1\n+DATA 0xFFD01508 0x10000000\n+DATA 0xFFD0150C 0x0FFFFFF5\n+DATA 0xFFD01514 0x00000000\n+DATA 0xFFD0151C 0x00000000\n+DATA 0xFFD01494 0x00120012\n+DATA 0xFFD01498 0x00000000\n+DATA 0xFFD0149C 0x0000E40F\n+DATA 0xFFD01480 0x00000001\n+DATA 0xFFD20134 0x66666666\n+DATA 0xFFD20138 0x66666666\n+DATA 0x0 0x0\n--- /dev/null\n+++ b/board/checkpoint/l-50/l-50.c\n@@ -0,0 +1,172 @@\n+// SPDX-License-Identifier: GPL-2.0+\n+/*\n+ * Copyright (C) 2020\n+ * Pawel Dembicki <paweldembicki@gmail.com>\n+ *\n+ * Based on Kirkwood support:\n+ * (C) Copyright 2009\n+ * Marvell Semiconductor <www.marvell.com>\n+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>\n+ */\n+\n+#include <common.h>\n+#include <dm.h>\n+#include <i2c.h>\n+#include <miiphy.h>\n+#include <netdev.h>\n+#include <asm/arch/cpu.h>\n+#include <asm/arch/soc.h>\n+#include <asm/arch/mpp.h>\n+#include <asm/arch/gpio.h>\n+#include \"l-50.h\"\n+\n+DECLARE_GLOBAL_DATA_PTR;\n+\n+int board_early_init_f(void)\n+{\n+\t/* Gpio configuration */\n+\tmvebu_config_gpio(L50_OE_VAL_LOW, L50_OE_VAL_HIGH,\n+\t\t\t  L50_OE_LOW, L50_OE_HIGH);\n+\n+\t/* Multi-Purpose Pins Functionality configuration */\n+\tstatic const u32 kwmpp_config[] = {\n+\t\tMPP0_NF_IO2,\n+\t\tMPP1_NF_IO3,\n+\t\tMPP2_NF_IO4,\n+\t\tMPP3_NF_IO5,\n+\t\tMPP4_NF_IO6,\n+\t\tMPP5_NF_IO7,\n+\t\tMPP6_SYSRST_OUTn,\n+\t\tMPP7_SPI_SCn,\n+\t\tMPP8_TW_SDA,\n+\t\tMPP9_TW_SCK,\n+\t\tMPP10_UART0_TXD,\n+\t\tMPP11_UART0_RXD,\n+\t\tMPP12_SD_CLK,\n+\t\tMPP13_SD_CMD,\n+\t\tMPP14_SD_D0,\n+\t\tMPP15_SD_D1,\n+\t\tMPP16_SD_D2,\n+\t\tMPP17_SD_D3,\n+\t\tMPP18_NF_IO0,\n+\t\tMPP19_NF_IO1,\n+\t\tMPP20_GE1_0,\n+\t\tMPP21_GE1_1,\n+\t\tMPP22_GE1_2,\n+\t\tMPP23_GE1_3,\n+\t\tMPP24_GE1_4,\n+\t\tMPP25_GE1_5,\n+\t\tMPP26_GE1_6,\n+\t\tMPP27_GE1_7,\n+\t\tMPP28_GPIO,\n+\t\tMPP29_GPIO,\n+\t\tMPP30_GE1_10,\n+\t\tMPP31_GE1_11,\n+\t\tMPP32_GE1_12,\n+\t\tMPP33_GE1_13,\n+\t\tMPP34_GPIO,\n+\t\tMPP35_GPIO,\n+\t\tMPP36_AUDIO_SPDIFI,\t/* value from stock u-boot */\n+\t\tMPP37_GPIO,\n+\t\tMPP38_GPIO,\n+\t\tMPP39_TDM_SPI_CS0,\n+\t\tMPP40_GPIO,\n+\t\tMPP41_GPIO,\n+\t\tMPP42_TDM_SPI_MOSI,\n+\t\tMPP43_TDM_CODEC_INTn,\n+\t\tMPP44_GPIO,\n+\t\tMPP45_TDM_PCLK,\n+\t\tMPP46_GPIO,\n+\t\tMPP47_TDM_DRX,\n+\t\tMPP48_GPIO,\n+\t\tMPP49_GPIO,\n+\t\t0\n+\t};\n+\tkirkwood_mpp_conf(kwmpp_config, NULL);\n+\n+\treturn 0;\n+}\n+\n+void board_gpio_expander_init(void)\n+{\n+\tstruct udevice *dev0, *dev1;\n+\tuchar data_buffer;\n+\tint ret;\n+\n+\tret = i2c_get_chip_for_busnum(0, L50_GPIO0_I2C_ADDRESS, 1, &dev0);\n+\tif (ret) {\n+\t\tdebug(\"%s: Cannot find I2C GPIO expander chip 0x02%X\\n\",\n+\t\t      __func__, L50_GPIO0_I2C_ADDRESS);\n+\t\treturn;\n+\t}\n+\n+\tret = i2c_get_chip_for_busnum(0, L50_GPIO1_I2C_ADDRESS, 1, &dev1);\n+\tif (ret) {\n+\t\tdebug(\"%s: Cannot find I2C GPIO expander chip 0x02%X\\n\",\n+\t\t      __func__, L50_GPIO1_I2C_ADDRESS);\n+\t\treturn;\n+\t}\n+\n+\t/* Set IO as output */\n+\tdata_buffer = 0x0;\n+\tdm_i2c_write(dev0, 1, &data_buffer, 1);\n+\tdm_i2c_write(dev1, 1, &data_buffer, 1);\n+\n+\t/* Set all leds off, reset asserted, pwr off */\n+\tdata_buffer = 0xbf;\n+\tdm_i2c_write(dev0, 0, &data_buffer, 1);\n+\tdata_buffer = 0x1c;\n+\tdm_i2c_write(dev1, 0, &data_buffer, 1);\n+\n+\tmdelay(100);\n+\n+\t/* Set pwr on */\n+\tdata_buffer = 0xa5;\n+\tdm_i2c_write(dev1, 0, &data_buffer, 1);\n+\n+\tmdelay(100);\n+\n+\t/* Set reset deasserted, status red led enabled*/\n+\tdata_buffer = 0xff;\n+\tdm_i2c_write(dev0, 0, &data_buffer, 1);\n+\tdata_buffer = 0xe3;\n+\tdm_i2c_write(dev1, 0, &data_buffer, 1);\n+}\n+\n+int board_init(void)\n+{\n+\t/* Boot parameters address */\n+\tgd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;\n+\n+\tboard_gpio_expander_init();\n+\n+\treturn 0;\n+}\n+\n+#ifdef CONFIG_RESET_PHY_R\n+/* Configure and initialize PHY */\n+void reset_phy(void)\n+{\n+\tu16 devadr;\n+\tchar *name = \"ethernet-controller@72000\";\n+\n+\tif (miiphy_set_current_dev(name))\n+\t\treturn;\n+\n+\t/* command to read PHY dev address */\n+\tif (miiphy_read(name, 0xEE, 0xEE, (u16 *)&devadr)) {\n+\t\tprintf(\"Err..(%s) could not read PHY dev address\\n\", __func__);\n+\t\treturn;\n+\t}\n+\n+\t/*\n+\t * Fix PHY led configuration\n+\t */\n+\tmiiphy_write(name, devadr, MV88E1116_PGADR_REG, 3);\n+\tmiiphy_write(name, devadr, 0x10, 0x1177);\n+\tmiiphy_write(name, devadr, 0x11, 0x4417);\n+\tmiiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);\n+\n+\tdebug(\"88E1116 Initialized on %s\\n\", name);\n+}\n+#endif /* CONFIG_RESET_PHY_R */\n--- /dev/null\n+++ b/board/checkpoint/l-50/l-50.h\n@@ -0,0 +1,29 @@\n+/* SPDX-License-Identifier: GPL-2.0+ */\n+/*\n+ * Copyright (C) 2020\n+ * Pawel Dembicki <paweldembicki@gmail.com>\n+ *\n+ * Based on Kirkwood support:\n+ * (C) Copyright 2009\n+ * Marvell Semiconductor <www.marvell.com>\n+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>\n+ */\n+\n+#ifndef __L50_H\n+#define __L50_H\n+\n+/* GPIO configuration */\n+#define L50_OE_LOW\t\t\t0x30000000\n+#define L50_OE_HIGH\t\t\t0x0000004c\n+#define L50_OE_VAL_LOW\t\t0x00000000\n+#define L50_OE_VAL_HIGH\t\t0x00000000\n+\n+/* Expander GPIO addresses */\n+\n+#define L50_GPIO0_I2C_ADDRESS\t\t0x20\n+#define L50_GPIO1_I2C_ADDRESS\t\t0x21\n+\n+/* PHY register */\n+#define MV88E1116_PGADR_REG\t\t22\n+\n+#endif /* __L50_H */\n--- /dev/null\n+++ b/configs/l-50_defconfig\n@@ -0,0 +1,59 @@\n+CONFIG_ARM=y\n+CONFIG_SYS_DCACHE_OFF=y\n+CONFIG_ARCH_CPU_INIT=y\n+CONFIG_KIRKWOOD=y\n+CONFIG_SYS_TEXT_BASE=0x600000\n+CONFIG_TARGET_L50=y\n+CONFIG_ENV_SIZE=0x20000\n+CONFIG_ENV_OFFSET=0xC0000\n+CONFIG_ENV_SECT_SIZE=0x20000\n+CONFIG_ENV_ADDR=0xC0000\n+CONFIG_IDENT_STRING=\"\\nCheck Point L-50\"\n+CONFIG_NR_DRAM_BANKS=2\n+# CONFIG_SYS_MALLOC_F is not set\n+CONFIG_BOOTDELAY=1\n+CONFIG_CONSOLE_MUX=y\n+CONFIG_DISPLAY_BOARDINFO=y\n+CONFIG_HUSH_PARSER=y\n+# CONFIG_CMD_FLASH is not set\n+#CONFIG_CMD_IDE=y\n+CONFIG_CMD_I2C=y\n+CONFIG_CMD_NAND=y\n+CONFIG_CMD_USB=y\n+# CONFIG_CMD_SETEXPR is not set\n+CONFIG_CMD_DHCP=y\n+CONFIG_CMD_MII=y\n+CONFIG_CMD_PING=y\n+CONFIG_CMD_EXT2=y\n+CONFIG_CMD_FAT=y\n+CONFIG_CMD_JFFS2=y\n+CONFIG_CMD_MTDPARTS=y\n+CONFIG_MTD=y\n+CONFIG_MTD_RAW_NAND=y\n+CONFIG_MTDIDS_DEFAULT=\"nand0=orion_nand\"\n+CONFIG_MTDPARTS_DEFAULT=\"mtdparts=orion_nand:0xc0000@0x0(u-boot)ro,0x40000@0xc0000(bootldr-env),0x7900000@0x100000(ubi),0x800000@0x7a00000(kernel-2),0x7100000@0x8200000(rootfs-2),0x7900000@0xf300000(default_sw),0x1800000@0x16c00000(logs),0x100000@0x18400000(preset_cfg),0x100000@0x18500000(adsl),-@0x18600000(storage)\"\n+CONFIG_CMD_UBI=y\n+CONFIG_ISO_PARTITION=y\n+CONFIG_OF_CONTROL=y\n+CONFIG_DEFAULT_DEVICE_TREE=\"kirkwood-l-50\"\n+CONFIG_ENV_IS_IN_NAND=y\n+CONFIG_DM=y\n+CONFIG_DM_ETH=y\n+#CONFIG_MVSATA_IDE=y\n+CONFIG_MMC=y\n+CONFIG_MVGBE=y\n+CONFIG_MII=y\n+CONFIG_PHYLIB=y\n+CONFIG_PHY_MARVELL=y\n+CONFIG_MV88E61XX_SWITCH=y\n+CONFIG_MV88E61XX_CPU_PORT=6\n+CONFIG_MV88E61XX_PHY_PORTS=0x01f\n+CONFIG_MV88E61XX_FIXED_PORTS=0\n+#CONFIG_DM_RTC=y\n+#CONFIG_RTC_MV=y\n+CONFIG_SYS_NS16550=y\n+CONFIG_DM_I2C=y\n+CONFIG_SYS_I2C_MVTWSI=y\n+CONFIG_USB=y\n+CONFIG_USB_EHCI_HCD=y\n+CONFIG_USB_STORAGE=y\n--- /dev/null\n+++ b/include/configs/l-50.h\n@@ -0,0 +1,59 @@\n+/* SPDX-License-Identifier: GPL-2.0+ */\n+/*\n+ * Copyright (C) 2020\n+ * Pawel Dembicki <paweldembicki@gmail.com>\n+ *\n+ * Based on Kirkwood support:\n+ * (C) Copyright 2009\n+ * Marvell Semiconductor <www.marvell.com>\n+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>\n+ */\n+\n+#ifndef _CONFIG_L50_H\n+#define _CONFIG_L50_H\n+\n+/*\n+ * High Level Configuration Options (easy to change)\n+ */\n+#define CONFIG_FEROCEON_88FR131\t\t/* CPU Core subversion */\n+#define CONFIG_KW88F6281\t\t/* SOC Name */\n+#define CONFIG_SKIP_LOWLEVEL_INIT\t/* disable board lowlevel_init */\n+\n+/*\n+ * mv-common.h should be defined after CMD configs since it used them\n+ * to enable certain macros\n+ */\n+#include \"mv-common.h\"\n+\n+/* Remove or override few declarations from mv-common.h */\n+\n+/*\n+ * Ethernet Driver configuration\n+ */\n+#ifdef CONFIG_CMD_NET\n+#define CONFIG_MVGBE_PORTS\t\t{1, 1} /* enable port 0 only */\n+#define CONFIG_NETCONSOLE\n+#endif\n+\n+#define CONFIG_MV88E61XX_CPU_PORT_RX_DELAY\n+#define CONFIG_MV88E61XX_CPU_PORT_TX_DELAY\n+\n+/*\n+ * Enable GPI0 support\n+ */\n+#define CONFIG_KIRKWOOD_GPIO\n+\n+/*\n+ * Default environment variables\n+ */\n+#define CONFIG_BOOTCOMMAND \\\n+\t\"ubi part ubi; \" \\\n+\t\"ubi read 0x800000 kernel; \" \\\n+\t\"bootm 0x800000\"\n+\n+#define CONFIG_EXTRA_ENV_SETTINGS \\\n+\t\"bootargs=console=ttyS0,115200\\0\"\t\\\n+\t\"mtdids=\" CONFIG_MTDIDS_DEFAULT \"\\0\"\t\\\n+\t\"mtdparts=\" CONFIG_MTDPARTS_DEFAULT \"\\0\"\t\\\n+\t\"bootargs_root=\\0\"\n+#endif /* _CONFIG_L50_H */\n"
  },
  {
    "path": "package/boot/uboot-kirkwood/patches/160-nsa310s.patch",
    "content": "--- a/configs/nsa310s_defconfig\n+++ b/configs/nsa310s_defconfig\n@@ -5,7 +5,7 @@ CONFIG_KIRKWOOD=y\n CONFIG_SYS_TEXT_BASE=0x600000\n CONFIG_TARGET_NSA310S=y\n CONFIG_ENV_SIZE=0x20000\n-CONFIG_ENV_OFFSET=0xE0000\n+CONFIG_ENV_OFFSET=0xC0000\n CONFIG_NR_DRAM_BANKS=2\n CONFIG_BOOTDELAY=3\n CONFIG_USE_PREBOOT=y\n@@ -25,7 +25,7 @@ CONFIG_CMD_EXT2=y\n CONFIG_CMD_FAT=y\n CONFIG_CMD_JFFS2=y\n CONFIG_CMD_MTDPARTS=y\n-CONFIG_MTDPARTS_DEFAULT=\"mtdparts=orion_nand:0xe0000@0x0(uboot),0x20000@0xe0000(uboot_env),0x100000@0x100000(second_stage_uboot),-@0x200000(root)\"\n+CONFIG_MTDPARTS_DEFAULT=\"mtdparts=orion_nand:0xc0000@0x0(uboot),0x80000@0xc0000(uboot_env),-@0x140000(ubi)\"\n CONFIG_CMD_UBI=y\n CONFIG_ISO_PARTITION=y\n CONFIG_ENV_IS_IN_NAND=y\n--- a/include/configs/nsa310s.h\n+++ b/include/configs/nsa310s.h\n@@ -30,22 +30,17 @@\n \n /* default environment variables */\n #define CONFIG_BOOTCOMMAND \\\n-\t\"setenv bootargs ${console} ${mtdparts} ${bootargs_root}; \" \\\n-\t\"ubi part root; \" \\\n-\t\"ubifsmount ubi:rootfs; \" \\\n-\t\"ubifsload 0x800000 ${kernel}; \" \\\n-\t\"ubifsload 0x700000 ${fdt}; \" \\\n-\t\"ubifsumount; \" \\\n-\t\"fdt addr 0x700000; fdt resize; fdt chosen; \" \\\n-\t\"bootz 0x800000 - 0x700000\"\n+\t\"setenv bootargs ${console} ${mtdparts} ${bootargs_root}; \"\t\\\n+\t\"ubi part ubi; \"\t\t\t\t\t\t\\\n+\t\"ubifsmount ubi:rootfs; \"\t\t\t\t\t\\\n+\t\"ubi read 0x800000 kernel; \"\t\t\t\t\t\\\n+\t\"bootm 0x800000\"\n \n #define CONFIG_EXTRA_ENV_SETTINGS \\\n-\t\"console=console=ttyS0,115200\\0\" \\\n-\t\"mtdids=nand0=orion_nand\\0\" \\\n-\t\"mtdparts=\"CONFIG_MTDPARTS_DEFAULT \\\n-\t\"kernel=/boot/zImage\\0\" \\\n-\t\"fdt=/boot/nsa310s.dtb\\0\" \\\n-\t\"bootargs_root=ubi.mtd=3 root=ubi0:rootfs rootfstype=ubifs rw\\0\"\n+\t\"console=console=ttyS0,115200\\0\"\t\\\n+\t\"mtdids=nand0=orion_nand\\0\"\t\t\\\n+\t\"mtdparts=\"CONFIG_MTDPARTS_DEFAULT \"\\0\"\t\\\n+\t\"bootargs_root=\\0\"\n \n /* Ethernet driver configuration */\n #ifdef CONFIG_CMD_NET\n"
  },
  {
    "path": "package/boot/uboot-kirkwood/patches/170-sheevaplug.patch",
    "content": "--- a/include/configs/sheevaplug.h\n+++ b/include/configs/sheevaplug.h\n@@ -45,15 +45,17 @@\n /*\n  * Default environment variables\n  */\n-#define CONFIG_BOOTCOMMAND\t\t\"${x_bootcmd_kernel}; \"\t\\\n-\t\"setenv bootargs ${x_bootargs} ${x_bootargs_root}; \"\t\\\n-\t\"bootm 0x6400000;\"\n+#define CONFIG_BOOTCOMMAND\t\t\t\t\t\\\n+\t\"setenv bootargs ${console} ${mtdparts} ${bootargs_root}; \"\t\\\n+\t\"ubi part ubi; \" \t\t\t\t\t\t\\\n+\t\"ubi read 0x800000 kernel; \" \t\t\t\\\n+\t\"bootm 0x800000\"\n \n-#define CONFIG_EXTRA_ENV_SETTINGS\t\"x_bootargs=console\"\t\\\n-\t\"=ttyS0,115200 mtdparts=\"CONFIG_MTDPARTS_DEFAULT\t\\\n-\t\"x_bootcmd_kernel=nand read 0x6400000 0x100000 0x400000\\0\" \\\n-\t\"x_bootcmd_usb=usb start\\0\" \\\n-\t\"x_bootargs_root=root=/dev/mtdblock3 rw rootfstype=jffs2\\0\"\n+#define CONFIG_EXTRA_ENV_SETTINGS\t\t\t\\\n+\t\"console=console=ttyS0,115200\\0\"\t\t\\\n+\t\"mtdids=\"CONFIG_MTDIDS_DEFAULT \"\\0\"\t\t\\\n+\t\"mtdparts=\"CONFIG_MTDPARTS_DEFAULT \"\\0\"\t\\\n+\t\"bootargs_root=\\0\"\n \n /*\n  * Ethernet Driver configuration\n--- a/configs/sheevaplug_defconfig\n+++ b/configs/sheevaplug_defconfig\n@@ -30,7 +30,7 @@ CONFIG_CMD_FAT=y\n CONFIG_CMD_JFFS2=y\n CONFIG_CMD_MTDPARTS=y\n CONFIG_MTDIDS_DEFAULT=\"nand0=orion_nand\"\n-CONFIG_MTDPARTS_DEFAULT=\"mtdparts=orion_nand:512K(uboot),512K(env),4M(kernel),-(rootfs)\"\n+CONFIG_MTDPARTS_DEFAULT=\"mtdparts=orion_nand:1M(uboot),-(ubi)\"\n CONFIG_CMD_UBI=y\n CONFIG_ISO_PARTITION=y\n CONFIG_OF_CONTROL=y\n"
  },
  {
    "path": "package/boot/uboot-kirkwood/patches/200-openwrt-config.patch",
    "content": "--- a/arch/arm/mach-kirkwood/Kconfig\n+++ b/arch/arm/mach-kirkwood/Kconfig\n@@ -107,4 +107,7 @@ source \"board/alliedtelesis/SBx81LIFXCAT\n source \"board/Marvell/db-88f6281-bp/Kconfig\"\n source \"board/checkpoint/l-50/Kconfig\"\n \n+config SECOND_STAGE\n+\tbool \"OpenWrt second stage hack\"\n+\n endif\n--- a/include/configs/dockstar.h\n+++ b/include/configs/dockstar.h\n@@ -60,4 +60,6 @@\n  * File system\n  */\n \n+#include \"openwrt-kirkwood-common.h\"\n+\n #endif /* _CONFIG_DOCKSTAR_H */\n--- a/include/configs/ib62x0.h\n+++ b/include/configs/ib62x0.h\n@@ -77,4 +77,6 @@\n #define CONFIG_RTC_MV\n #endif /* CONFIG_CMD_DATE */\n \n+#include \"openwrt-kirkwood-common.h\"\n+\n #endif /* _CONFIG_IB62x0_H */\n--- a/include/configs/iconnect.h\n+++ b/include/configs/iconnect.h\n@@ -67,4 +67,6 @@\n  * File system\n  */\n \n+#include \"openwrt-kirkwood-common.h\"\n+\n #endif /* _CONFIG_ICONNECT_H */\n--- a/include/configs/l-50.h\n+++ b/include/configs/l-50.h\n@@ -12,6 +12,8 @@\n #ifndef _CONFIG_L50_H\n #define _CONFIG_L50_H\n \n+#include \"openwrt-kirkwood-common.h\"\n+\n /*\n  * High Level Configuration Options (easy to change)\n  */\n--- /dev/null\n+++ b/include/configs/openwrt-kirkwood-common.h\n@@ -0,0 +1,31 @@\n+/*\n+ * Copyright (C) 2013 Luka Perkov <luka@openwrt.org>\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#ifndef __OPENWRT_KIRKWOOD_COMMON_H\n+#define __OPENWRT_KIRKWOOD_COMMON_H\n+\n+/* Ethernet */\n+#if defined(CONFIG_CMD_NET)\n+#define CONFIG_SERVERIP\t\t192.168.1.2\n+#define CONFIG_IPADDR\t\t192.168.1.1\n+#endif\n+\n+/* second stage loader */\n+#if defined(CONFIG_SECOND_STAGE)\n+#undef CONFIG_ENV_IS_IN_NAND\n+#undef CONFIG_ENV_SECT_SIZE\n+#define CONFIG_ENV_IS_NOWHERE\n+#endif\n+\n+/* Various */\n+#define CONFIG_BZIP2\n+\n+/* Unnecessary */\n+#undef CONFIG_BOOTM_NETBSD\n+#undef CONFIG_BOOTM_PLAN9\n+#undef CONFIG_BOOTM_RTEMS\n+\n+#endif /* __OPENWRT_KIRKWOOD_COMMON_H */\n--- a/include/configs/pogo_e02.h\n+++ b/include/configs/pogo_e02.h\n@@ -66,4 +66,6 @@\n  * File system\n  */\n \n+#include \"openwrt-kirkwood-common.h\"\n+\n #endif /* _CONFIG_POGO_E02_H */\n--- a/include/configs/goflexhome.h\n+++ b/include/configs/goflexhome.h\n@@ -85,4 +85,6 @@\n #define CONFIG_SYS_ATA_IDE0_OFFSET      MV_SATA_PORT0_OFFSET\n #endif /*CONFIG_MVSATA_IDE*/\n \n+#include \"openwrt-kirkwood-common.h\"\n+\n #endif /* _CONFIG_GOFLEXHOME_H */\n--- a/include/configs/nsa310.h\n+++ b/include/configs/nsa310.h\n@@ -100,4 +100,6 @@\n #define CONFIG_RTC_MV\n #endif /* CONFIG_CMD_DATE */\n \n+#include \"openwrt-kirkwood-common.h\"\n+\n #endif /* _CONFIG_NSA310_H */\n--- a/configs/dockstar_defconfig\n+++ b/configs/dockstar_defconfig\n@@ -38,3 +38,8 @@ CONFIG_SYS_NS16550=y\n CONFIG_USB=y\n CONFIG_USB_EHCI_HCD=y\n CONFIG_USB_STORAGE=y\n+CONFIG_CMD_BOOTZ=y\n+CONFIG_FIT=y\n+CONFIG_FIT_VERBOSE=y\n+CONFIG_LZMA=y\n+CONFIG_LZO=y\n--- a/configs/goflexhome_defconfig\n+++ b/configs/goflexhome_defconfig\n@@ -49,3 +49,8 @@ CONFIG_USB=y\n CONFIG_DM_USB=y\n CONFIG_USB_EHCI_HCD=y\n CONFIG_USB_STORAGE=y\n+CONFIG_CMD_BOOTZ=y\n+CONFIG_FIT=y\n+CONFIG_FIT_VERBOSE=y\n+CONFIG_LZMA=y\n+CONFIG_LZO=y\n--- a/configs/ib62x0_defconfig\n+++ b/configs/ib62x0_defconfig\n@@ -43,4 +43,7 @@ CONFIG_SYS_NS16550=y\n CONFIG_USB=y\n CONFIG_USB_EHCI_HCD=y\n CONFIG_USB_STORAGE=y\n+CONFIG_FIT=y\n+CONFIG_FIT_VERBOSE=y\n CONFIG_LZMA=y\n+CONFIG_LZO=y\n--- a/configs/iconnect_defconfig\n+++ b/configs/iconnect_defconfig\n@@ -39,4 +39,8 @@ CONFIG_SYS_NS16550=y\n CONFIG_USB=y\n CONFIG_USB_EHCI_HCD=y\n CONFIG_USB_STORAGE=y\n+CONFIG_CMD_BOOTZ=y\n+CONFIG_FIT=y\n+CONFIG_FIT_VERBOSE=y\n CONFIG_LZMA=y\n+CONFIG_LZO=y\n--- a/configs/l-50_defconfig\n+++ b/configs/l-50_defconfig\n@@ -57,3 +57,8 @@ CONFIG_SYS_I2C_MVTWSI=y\n CONFIG_USB=y\n CONFIG_USB_EHCI_HCD=y\n CONFIG_USB_STORAGE=y\n+CONFIG_CMD_BOOTZ=y\n+CONFIG_FIT=y\n+CONFIG_FIT_VERBOSE=y\n+CONFIG_LZMA=y\n+CONFIG_LZO=y\n--- a/configs/nsa310_defconfig\n+++ b/configs/nsa310_defconfig\n@@ -43,6 +43,9 @@ CONFIG_CMD_UBI=y\n CONFIG_USB=y\n CONFIG_USB_EHCI_HCD=y\n CONFIG_USB_STORAGE=y\n+CONFIG_CMD_BOOTZ=y\n+CONFIG_FIT=y\n+CONFIG_FIT_VERBOSE=y\n CONFIG_LZMA=y\n CONFIG_LZO=y\n CONFIG_SYS_LONGHELP=y\n--- a/configs/pogo_e02_defconfig\n+++ b/configs/pogo_e02_defconfig\n@@ -39,3 +39,8 @@ CONFIG_SYS_NS16550=y\n CONFIG_USB=y\n CONFIG_USB_EHCI_HCD=y\n CONFIG_USB_STORAGE=y\n+CONFIG_CMD_BOOTZ=y\n+CONFIG_FIT=y\n+CONFIG_FIT_VERBOSE=y\n+CONFIG_LZMA=y\n+CONFIG_LZO=y\n--- a/configs/nsa310s_defconfig\n+++ b/configs/nsa310s_defconfig\n@@ -40,5 +40,8 @@ CONFIG_SYS_NS16550=y\n CONFIG_USB=y\n CONFIG_USB_EHCI_HCD=y\n CONFIG_USB_STORAGE=y\n+CONFIG_FIT=y\n+CONFIG_FIT_VERBOSE=y\n CONFIG_LZMA=y\n+CONFIG_LZO=y\n CONFIG_OF_LIBFDT=y\n--- a/include/configs/nsa310s.h\n+++ b/include/configs/nsa310s.h\n@@ -63,4 +63,6 @@\n #define CONFIG_RTC_MV\n #endif /* CONFIG_CMD_DATE */\n \n+#include \"openwrt-kirkwood-common.h\"\n+\n #endif /* _CONFIG_NSA310S_H */\n--- a/configs/sheevaplug_defconfig\n+++ b/configs/sheevaplug_defconfig\n@@ -49,4 +49,7 @@ CONFIG_USB=y\n CONFIG_DM_USB=y\n CONFIG_USB_EHCI_HCD=y\n CONFIG_USB_STORAGE=y\n+CONFIG_FIT=y\n+CONFIG_FIT_VERBOSE=y\n CONFIG_LZMA=y\n+CONFIG_LZO=y\n"
  },
  {
    "path": "package/boot/uboot-kirkwood/patches/201-blackarmor-nas220.patch",
    "content": "--- a/include/configs/nas220.h\n+++ b/include/configs/nas220.h\n@@ -54,17 +54,22 @@\n /*\n  * Default environment variables\n  */\n-#define CONFIG_BOOTCOMMAND \"\"\n+#define CONFIG_BOOTCOMMAND \\\n+\t\"ubi part ubi; \" \\\n+\t\"ubi read 0x800000 kernel; \" \\\n+\t\"bootm 0x800000\"\n \n #define CONFIG_EXTRA_ENV_SETTINGS \\\n \t\"bootargs=console=ttyS0,115200\\0\" \\\n \t\"mtdparts=mtdparts=orion_nand:0xa0000@0x0(uboot),\"\\\n \t\"0x010000@0xa0000(env),\"\\\n-\t\"0x500000@0xc0000(uimage),\"\\\n-\t\"0x1a40000@0x5c0000(rootfs)\\0\" \\\n+\t\"0x1e80000@0xc0000(ubi)\\0\"\\\n \t\"mtdids=nand0=orion_nand\\0\"\\\n \t\"autostart=no\\0\"\\\n-\t\"autoload=no\\0\"\n+\t\"autoload=no\\0\"\\\n+\t\"ipaddr=10.4.50.165\\0\"\\\n+\t\"serverip=10.4.50.5\\0\"\\\n+\t\"bootdelay=3\"\n \n /*\n  * Ethernet Driver configuration\n"
  },
  {
    "path": "package/boot/uboot-kirkwood/patches/701-phy-mv88e61xx-add-support-for-RGMII-TX-RX-delay.patch",
    "content": "From 940e9a5828480e4185c9a276ad7f35a4069a2393 Mon Sep 17 00:00:00 2001\nFrom: Pawel Dembicki <paweldembicki@gmail.com>\nDate: Thu, 23 Jan 2020 22:04:15 +0100\nSubject: [PATCH 1/2] phy: mv88e61xx: add support for RGMII TX/RX delay\n\nClock delay in RGMII is required for some boards.\nThis patch introduce CONFIG_MV88E61XX_CPU_PORT_TX_DELAY and\nCONFIG_MV88E61XX_CPU_PORT_RX_DELAY defines, which are setting\nproper bits in PORT_REG_PHYS_CTRL register.\n\nCc: Chris Packham <judge.packham@gmail.com>\nCc: Joe Hershberger <joe.hershberger@ni.com>\nCc: Anatolij Gustschin <agust@denx.de>\nCc: Tim Harvey <tharvey@gateworks.com>\nSigned-off-by: Pawel Dembicki <paweldembicki@gmail.com>\n---\n drivers/net/phy/mv88e61xx.c | 11 ++++++++++-\n 1 file changed, 10 insertions(+), 1 deletion(-)\n\n--- a/drivers/net/phy/mv88e61xx.c\n+++ b/drivers/net/phy/mv88e61xx.c\n@@ -94,6 +94,8 @@\n #define PORT_REG_STATUS_CMODE_1000BASE_X\t0x9\n #define PORT_REG_STATUS_CMODE_SGMII\t\t0xa\n \n+#define PORT_REG_PHYS_CTRL_RGMII_RX_DELAY\tBIT(15)\n+#define PORT_REG_PHYS_CTRL_RGMII_TX_DELAY\tBIT(14)\n #define PORT_REG_PHYS_CTRL_PCS_AN_EN\tBIT(10)\n #define PORT_REG_PHYS_CTRL_PCS_AN_RST\tBIT(9)\n #define PORT_REG_PHYS_CTRL_FC_VALUE\tBIT(7)\n@@ -747,9 +749,16 @@ static int mv88e61xx_fixed_port_setup(st\n \t\t       PORT_REG_PHYS_CTRL_SPD1000;\n \t}\n \n-\tif (port == CONFIG_MV88E61XX_CPU_PORT)\n+\tif (port == CONFIG_MV88E61XX_CPU_PORT) {\n \t\tval |= PORT_REG_PHYS_CTRL_LINK_VALUE |\n \t\t       PORT_REG_PHYS_CTRL_LINK_FORCE;\n+#if defined(CONFIG_MV88E61XX_CPU_PORT_RX_DELAY)\n+\t\tval |= PORT_REG_PHYS_CTRL_RGMII_RX_DELAY;\n+#endif\n+#if defined(CONFIG_MV88E61XX_CPU_PORT_TX_DELAY)\n+\t\tval |= PORT_REG_PHYS_CTRL_RGMII_TX_DELAY;\n+#endif\n+\t}\n \n \treturn mv88e61xx_port_write(phydev, port, PORT_REG_PHYS_CTRL,\n \t\t\t\t   val);\n"
  },
  {
    "path": "package/boot/uboot-kirkwood/patches/702-phy-mv88e61xx-add-support-for-MV88E6171.patch",
    "content": "From 7ffab66a99831ce5e3037b608d73565c9d1abd20 Mon Sep 17 00:00:00 2001\nFrom: Pawel Dembicki <paweldembicki@gmail.com>\nDate: Thu, 23 Jan 2020 22:09:51 +0100\nSubject: [PATCH 2/2] phy: mv88e61xx: add support for MV88E6171\n\nThis patch add MV88E6171 id to driver data.\n\nTested on Checkpoint L-50 board.\n\nCc: Chris Packham <judge.packham@gmail.com>\nCc: Joe Hershberger <joe.hershberger@ni.com>\nCc: Anatolij Gustschin <agust@denx.de>\nCc: Tim Harvey <tharvey@gateworks.com>\nSigned-off-by: Pawel Dembicki <paweldembicki@gmail.com>\n---\n drivers/net/phy/mv88e61xx.c | 14 ++++++++++++++\n 1 file changed, 14 insertions(+)\n\n--- a/drivers/net/phy/mv88e61xx.c\n+++ b/drivers/net/phy/mv88e61xx.c\n@@ -180,6 +180,7 @@\n #define PORT_SWITCH_ID_6071\t\t0x0710\n #define PORT_SWITCH_ID_6096\t\t0x0980\n #define PORT_SWITCH_ID_6097\t\t0x0990\n+#define PORT_SWITCH_ID_6171\t\t0x1710\n #define PORT_SWITCH_ID_6172\t\t0x1720\n #define PORT_SWITCH_ID_6176\t\t0x1760\n #define PORT_SWITCH_ID_6220\t\t0x2200\n@@ -997,6 +998,7 @@ static int mv88e61xx_probe(struct phy_de\n \tswitch (priv->id) {\n \tcase PORT_SWITCH_ID_6096:\n \tcase PORT_SWITCH_ID_6097:\n+\tcase PORT_SWITCH_ID_6171:\n \tcase PORT_SWITCH_ID_6172:\n \tcase PORT_SWITCH_ID_6176:\n \tcase PORT_SWITCH_ID_6240:\n@@ -1152,6 +1154,17 @@ static struct phy_driver mv88e61xx_drive\n \t.shutdown = &genphy_shutdown,\n };\n \n+static struct phy_driver mv88e617x_driver = {\n+\t.name = \"Marvell MV88E617x\",\n+\t.uid = 0x01410e70,\n+\t.mask = 0xfffffff0,\n+\t.features = PHY_GBIT_FEATURES,\n+\t.probe = mv88e61xx_probe,\n+\t.config = mv88e61xx_phy_config,\n+\t.startup = mv88e61xx_phy_startup,\n+\t.shutdown = &genphy_shutdown,\n+};\n+\n static struct phy_driver mv88e609x_driver = {\n \t.name = \"Marvell MV88E609x\",\n \t.uid = 0x1410c89,\n@@ -1177,6 +1190,7 @@ static struct phy_driver mv88e6071_drive\n int phy_mv88e61xx_init(void)\n {\n \tphy_register(&mv88e61xx_driver);\n+\tphy_register(&mv88e617x_driver);\n \tphy_register(&mv88e609x_driver);\n \tphy_register(&mv88e6071_driver);\n \n"
  },
  {
    "path": "package/boot/uboot-lantiq/Makefile",
    "content": "#\n# Copyright (C) 2012-2013 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=u-boot\nPKG_VERSION:=2013.10\nPKG_RELEASE:=$(AUTORELEASE)\n\nPKG_HASH:=0d71e62beb952b41ebafb20a7ee4df2f960db64c31b054721ceb79ff14014c55\n\nFIRMWARE_LANTIQ_SOURCE:=$(TOPDIR)/target/linux/lantiq/files/firmware/lantiq\n\ninclude $(INCLUDE_DIR)/u-boot.mk\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine U-Boot/Default\n  BUILD_TARGET:=lantiq\n  DDR_SETTINGS:=\nendef\n\ndefine U-Boot/arv4519pw_ram\n  NAME:=Arcadyan arv4519pw (RAM)\n  BUILD_SUBTARGET:=xway\n  BUILD_DEVICES:=arcadyan_arv4519pw\n  DDR_SETTINGS:=board/arcadyan/arv4519pw/ddr_settings.h\nendef\n\ndefine U-Boot/arv4519pw_nor\n  NAME:=Arcadyan arv4519pw (NOR)\n  BUILD_SUBTARGET:=xway\n  BUILD_DEVICES:=arcadyan_arv4519pw\nendef\n\ndefine U-Boot/arv4519pw_brn\n  NAME:=Arcadyan arv4519pw (BRN)\n  BUILD_SUBTARGET:=xway\n  BUILD_DEVICES:=arcadyan_arv4519pw\nendef\n\ndefine U-Boot/arv7506pw11_ram\n  NAME:=Arcadyan ARV7506PW11 (RAM)\n  BUILD_SUBTARGET:=xway\n  BUILD_DEVICES:=arcadyan_arv7506pw11\n  DDR_SETTINGS:=board/arcadyan/arv7506pw11/ddr_settings.h\nendef\n\ndefine U-Boot/arv7506pw11_nor\n  NAME:=Arcadyan ARV7506PW11 (NOR)\n  BUILD_SUBTARGET:=xway\n  BUILD_DEVICES:=arcadyan_arv7506pw11\nendef\n\ndefine U-Boot/arv7506pw11_brn\n  NAME:=Arcadyan ARV7506PW11 (BRN)\n  BUILD_SUBTARGET:=xway\n  BUILD_DEVICES:=arcadyan_arv7506pw11\nendef\n\ndefine U-Boot/arv7510pw_ram\n  NAME:=Arcadyan arv7510pw (RAM)\n  BUILD_SUBTARGET:=xway\n  BUILD_DEVICES:=arcadyan_arv4510pw\n  DDR_SETTINGS:=board/arcadyan/arv7510pw/ddr_settings.h\nendef\n\ndefine U-Boot/arv7510pw_nor\n  NAME:=Arcadyan arv7510pw (NOR)\n  BUILD_SUBTARGET:=xway\n  BUILD_DEVICES:=arcadyan_arv4510pw\nendef\n\ndefine U-Boot/arv7510pw_brn\n  NAME:=Arcadyan arv7510pw (BRN)\n  BUILD_SUBTARGET:=xway\n  BUILD_DEVICES:=arcadyan_arv4510pw\nendef\n\ndefine U-Boot/arv7510pw22_ram\n  NAME:=Arcadyan arv7510pw22 (RAM)\n  BUILD_SUBTARGET:=xway\n  BUILD_DEVICES:=arcadyan_arv7510pw22\n  DDR_SETTINGS:=board/arcadyan/arv7510pw22/ddr_settings.h\nendef\n\ndefine U-Boot/arv7510pw22_nor\n  NAME:=Arcadyan arv7510pw22 (NOR)\n  BUILD_SUBTARGET:=xway\n  BUILD_DEVICES:=arcadyan_arv7510pw22\nendef\n\ndefine U-Boot/arv7510pw22_brn\n  NAME:=Arcadyan arv7510pw22 (BRN)\n  BUILD_SUBTARGET:=xway\n  BUILD_DEVICES:=arcadyan_arv7510pw22\nendef\n\ndefine U-Boot/arv7518pw_ram\n  NAME:=Arcadyan arv7518pw (RAM)\n  BUILD_SUBTARGET:=xway\n  BUILD_DEVICES:=arcadyan_arv7518pw\n  DDR_SETTINGS:=board/arcadyan/arv7518pw/ddr_settings.h\nendef\n\ndefine U-Boot/arv7518pw_nor\n  NAME:=Arcadyan arv7518pw (NOR)\n  BUILD_SUBTARGET:=xway\n  BUILD_DEVICES:=arcadyan_arv7518pw\nendef\n\ndefine U-Boot/arv7518pw_brn\n  NAME:=Arcadyan arv7518pw (BRN)\n  BUILD_SUBTARGET:=xway\n  BUILD_DEVICES:=arcadyan_arv7518pw\nendef\n\ndefine U-Boot/arv752dpw_ram\n  NAME:=Arcadyan arv752dpw (RAM)\n  BUILD_SUBTARGET:=xway\n  DDR_SETTINGS:=board/arcadyan/arv752dpw/ddr_settings.h\n  BUILD_DEVICES:=arcadyan_arv752dpw\nendef\n\ndefine U-Boot/arv752dpw_nor\n  NAME:=Arcadyan arv752dpw (NOR)\n  BUILD_SUBTARGET:=xway\n  BUILD_DEVICES:=arcadyan_arv752dpw\nendef\n\ndefine U-Boot/arv752dpw_brn\n  NAME:=Arcadyan arv752dpw (BRN)\n  BUILD_SUBTARGET:=xway\n  BUILD_DEVICES:=arcadyan_arv752dpw\nendef\n\ndefine U-Boot/arv752dpw22_ram\n  NAME:=Arcadyan arv752dpw22 (RAM)\n  BUILD_SUBTARGET:=xway\n  BUILD_DEVICES:=arcadyan_arv752dpw22\n  DDR_SETTINGS:=board/arcadyan/arv752dpw22/ddr_settings.h\nendef\n\ndefine U-Boot/arv752dpw22_nor\n  NAME:=Arcadyan arv752dpw22 (NOR)\n  BUILD_SUBTARGET:=xway\n  BUILD_DEVICES:=arcadyan_arv752dpw22\nendef\n\ndefine U-Boot/arv752dpw22_brn\n  NAME:=Arcadyan arv752dpw22 (BRN)\n  BUILD_SUBTARGET:=xway\n  BUILD_DEVICES:=arcadyan_arv752dpw22\nendef\n\ndefine U-Boot/arv8539pw22_ram\n  NAME:=Speedport W 504V Typ A (RAM)\n  BUILD_SUBTARGET:=xway\n  BUILD_DEVICES:=arcadyan_arv8539pw22\n  DDR_SETTINGS:=board/arcadyan/arv8539pw22/ddr_settings.h\nendef\n\ndefine U-Boot/arv8539pw22_nor\n  NAME:=Speedport W 504V Typ A (NOR)\n  BUILD_SUBTARGET:=xway\n  BUILD_DEVICES:=arcadyan_arv8539pw22\nendef\n\ndefine U-Boot/arv8539pw22_brn\n  NAME:=Speedport W 504V Typ A (BRN)\n  BUILD_SUBTARGET:=xway\n  BUILD_DEVICES:=arcadyan_arv8539pw22\nendef\n\ndefine U-Boot/gigasx76x_ram\n  NAME:=Siemens Gigaset sx76x (RAM)\n  BUILD_SUBTARGET:=xway\n  BUILD_DEVICES:=siemens_gigaset-sx76x\n  DDR_SETTINGS:=board/gigaset/sx76x/ddr_settings.h\nendef\n\ndefine U-Boot/gigasx76x_nor\n  NAME:=Siemens Gigaset sx76x (NOR)\n  BUILD_SUBTARGET:=xway\n  BUILD_DEVICES:=siemens_gigaset-sx76x\nendef\n\ndefine U-Boot/acmp252_ram\n  NAME:=AudioCodes MP-252 (RAM)\n  BUILD_SUBTARGET:=xway\n  BUILD_DEVICES:=audiocodes_mp-252\n  DDR_SETTINGS:=board/audiocodes/acmp252/ddr_settings.h\nendef\n\ndefine U-Boot/acmp252_nor\n  NAME:=AudioCodes MP-252 (NOR)\n  BUILD_SUBTARGET:=xway\n  BUILD_DEVICES:=audiocodes_mp-252\nendef\n\ndefine U-Boot/bthomehubv5a_ram\n  NAME:=BT Home Hub 5A (RAM)\n  BUILD_SUBTARGET:=xrx200\n  BUILD_DEVICES:=bt_homehub-v5a\n  DDR_SETTINGS:=board/bt/bthomehubv5a/ddr_settings.h\nendef\n\ndefine U-Boot/easy50712_ram\n  NAME:=Lantiq EASY50712 (RAM)\n  BUILD_SUBTARGET:=xway\n  BUILD_DEVICES:=lantiq_easy50712\n  DDR_SETTINGS:=board/lantiq/easy50712/ddr_settings.h\nendef\n\ndefine U-Boot/easy50712_nor\n  NAME:=Lantiq EASY50712 (NOR)\n  BUILD_SUBTARGET:=xway\n  BUILD_DEVICES:=lantiq_easy50712\nendef\n\ndefine U-Boot/easy50712_norspl\n  NAME:=Lantiq EASY50712 (NOR SPL)\n  BUILD_SUBTARGET:=xway\n  BUILD_DEVICES:=lantiq_easy50712\n  UBOOT_IMAGE:=u-boot.ltq.lzo.norspl\n  DEPENDS+=@BROKEN\nendef\n\ndefine U-Boot/easy80920_ram\n  NAME:=Lantiq EASY80920 (RAM)\n  BUILD_SUBTARGET:=xrx200\n  BUILD_DEVICES:=lantiq_easy80920-nor lantiq_easy80920-nand\n  DDR_SETTINGS:=board/lantiq/easy80920/ddr_settings.h\nendef\n\ndefine U-Boot/easy80920_nor\n  NAME:=Lantiq EASY80920 (NOR)\n  BUILD_DEVICES:=lantiq_easy80920-nor lantiq_easy80920-nand\n  BUILD_SUBTARGET:=xrx200\nendef\n\ndefine U-Boot/easy80920_norspl\n  NAME:=Lantiq EASY80920 (NOR SPL)\n  BUILD_SUBTARGET:=xrx200\n  BUILD_DEVICES:=lantiq_easy80920-nor lantiq_easy80920-nand\n  UBOOT_IMAGE:=u-boot.ltq.lzo.norspl\n  DEPENDS+=@BROKEN\nendef\n\ndefine U-Boot/easy80920_sfspl\n  NAME:=Lantiq EASY80920 (SPI SPL)\n  BUILD_SUBTARGET:=xrx200\n  BUILD_DEVICES:=lantiq_easy80920-nor lantiq_easy80920-nand\n  UBOOT_IMAGE:=u-boot.ltq.lzo.sfspl\n  DEPENDS+=@BROKEN\nendef\n\ndefine U-Boot/fb3370_eva\n  NAME:=AVM FRITZ3370 (EVA)\n  BUILD_SUBTARGET:=xrx200\n  BUILD_DEVICES:=avm_fritz3370\nendef\n\ndefine U-Boot/fb3370_ram\n  NAME:=AVM FRITZ3370 (RAM)\n  BUILD_SUBTARGET:=xrx200\n  BUILD_DEVICES:=avm_fritz3370\n  DDR_SETTINGS:=board/avm/fb3370/ddr_settings.h\nendef\n\ndefine U-Boot/fb3370_sfspl\n  NAME:=AVM FRITZ3370 (SPI SPL)\n  BUILD_SUBTARGET:=xrx200\n  BUILD_DEVICES:=avm_fritz3370\n  UBOOT_IMAGE:=u-boot.ltq.lzo.sfspl\n  DEPENDS+=@BROKEN\nendef\n\ndefine U-Boot/p2812hnufx_ram\n  NAME:=ZyXEL P-2812HNU-Fx (RAM)\n  BUILD_SUBTARGET:=xrx200\n  BUILD_DEVICES:=zyxel_p-2812hnu-f1\n  DDR_SETTINGS:=board/zyxel/p2812hnufx/ddr_settings.h\nendef\n\ndefine U-Boot/p2812hnufx_nandspl\n  NAME:=ZyXEL P-2812HNU-Fx (NAND SPL)\n  BUILD_SUBTARGET:=xrx200\n  BUILD_DEVICES:=zyxel_p-2812hnu-f1\n  UBOOT_IMAGE:=u-boot.ltq.lzo.nandspl\n  DEPENDS+=@BROKEN\nendef\n\ndefine U-Boot/vgv7510kw22_brn\n  NAME:=Arcadyan VGV7510KW22 (BRN)\n  BUILD_SUBTARGET:=xrx200\n  BUILD_DEVICES:=arcadyan_vgv7510kw22-nor\nendef\n\ndefine U-Boot/vgv7510kw22_nor\n  NAME:=Arcadyan VGV7510KW22 (NOR)\n  BUILD_SUBTARGET:=xrx200\n  BUILD_DEVICES:=arcadyan_vgv7510kw22-nor\nendef\n\ndefine U-Boot/vgv7510kw22_ram\n  NAME:=Arcadyan VGV7510KW22 (RAM)\n  BUILD_SUBTARGET:=xrx200\n  BUILD_DEVICES:=arcadyan_vgv7510kw22-nor\n  DDR_SETTINGS:=board/arcadyan/vgv7510kw22/ddr_settings.h\nendef\n\ndefine U-Boot/vgv7519_brn\n  NAME:=Arcadyan VGV7519 (BRN)\n  BUILD_SUBTARGET:=xrx200\n  BUILD_DEVICES:=arcadyan_vgv7519-nor arcadyan_vgv7519-brn\nendef\n\ndefine U-Boot/vgv7519_nor\n  NAME:=Arcadyan VGV7519 (NOR)\n  BUILD_SUBTARGET:=xrx200\n  BUILD_DEVICES:=arcadyan_vgv7519-nor arcadyan_vgv7519-brn\nendef\n\ndefine U-Boot/vgv7519_ram\n  NAME:=Arcadyan VGV7519 (RAM)\n  BUILD_SUBTARGET:=xrx200\n  BUILD_DEVICES:=arcadyan_vgv7519-nor arcadyan_vgv7519-brn\n  DDR_SETTINGS:=board/arcadyan/vgv7519/ddr_settings.h\nendef\n\nUBOOT_TARGETS:= \\\n\tarv4519pw_ram arv4519pw_nor arv4519pw_brn \\\n\tarv7506pw11_ram arv7506pw11_nor arv7506pw11_brn \\\n\tarv7510pw_ram arv7510pw_nor arv7510pw_brn \\\n\tarv7510pw22_ram arv7510pw22_nor arv7510pw22_brn \\\n\tarv7518pw_ram arv7518pw_nor arv7518pw_brn \\\n\tarv752dpw_ram arv752dpw_nor arv752dpw_brn \\\n\tarv752dpw22_ram arv752dpw22_nor arv752dpw22_brn \\\n\tarv8539pw22_brn arv8539pw22_nor arv8539pw22_ram \\\n\tbthomehubv5a_ram \\\n\tgigasx76x_ram gigasx76x_nor \\\n\tacmp252_ram acmp252_nor \\\n\teasy50712_ram easy50712_nor easy50712_norspl \\\n\teasy80920_ram easy80920_nor easy80920_norspl easy80920_sfspl \\\n\tfb3370_eva fb3370_ram fb3370_sfspl \\\n\tp2812hnufx_ram p2812hnufx_nandspl \\\n\tvgv7510kw22_brn vgv7510kw22_nor vgv7510kw22_ram \\\n\tvgv7519_brn vgv7519_nor vgv7519_ram\n\ndefine CompressVR9Firmware\n\t$(STAGING_DIR_HOST)/bin/lzma e \\\n\t\t$(FIRMWARE_LANTIQ_SOURCE)/xrx200_phy$(1)_a$(2)$(3).bin \\\n\t\t$(PKG_BUILD_DIR)/arch/mips/cpu/mips32/vrx200/fw_phy$(1)_a$(2)x.blob\nendef\n\ndefine Build/Prepare\n\t$(call Build/Prepare/Default)\n\tmkdir -p $(PKG_BUILD_DIR)/arch/mips/cpu/mips32/vrx200/\n\t$(call CompressVR9Firmware,11g,1,4)\n\t$(call CompressVR9Firmware,11g,2,2)\n\t$(call CompressVR9Firmware,22f,1,4)\n\t$(call CompressVR9Firmware,22f,2,2)\nendef\n\nUBOOT_MAKE_FLAGS :=\n\nifeq ($(SUBTARGET),xway)\n  SOC:=danube\nelse\n  SOC:=vr9\nendif\n\ndefine Package/u-boot/install/uart\n\tawk -f $(PKG_BUILD_DIR)/tools/lantiq_ram_init_uart.awk \\\n\t\t-v soc=$(SOC) $(PKG_BUILD_DIR)/$(DDR_SETTINGS) \\\n\t\t> $(PKG_BUILD_DIR)/ddr_settings\n\tperl $(PKG_BUILD_DIR)/tools/gct.pl \\\n\t\t$(PKG_BUILD_DIR)/ddr_settings $(PKG_BUILD_DIR)/u-boot.srec \\\n\t\t$(1)/u-boot.asc\nendef\n\ndefine Package/u-boot/install\n\t$(Package/u-boot/install/$(if $(DDR_SETTINGS),uart,default))\nendef\n\n$(eval $(call BuildPackage/U-Boot))\n"
  },
  {
    "path": "package/boot/uboot-lantiq/README",
    "content": "# How to refresh patches\n\n$ git clone git@github.com:danielschwierzeck/u-boot-lantiq.git\n$ mkdir -p $OPENWRT_ROOT/packages/boot/uboot-lantiq/patches\n$ cd u-boot-lantiq.git\n$ git format-patch -p -k --no-renames --no-binary -o $OPENWRT_ROOT/package/boot/uboot-lantiq/patches v2013.10..u-boot-lantiq-v2013.10-openwrtN\n"
  },
  {
    "path": "package/boot/uboot-lantiq/patches/0001-sf-fix-out-of-order-calls-for-spi_claim_bus-and-spi_.patch",
    "content": "From 909840ef844013379e5ec399c1e76c65d1a6eb1d Mon Sep 17 00:00:00 2001\nFrom: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>\nDate: Sat, 12 Oct 2013 21:09:47 +0200\nSubject: sf: fix out-of-order calls for spi_claim_bus and spi_release_bus\n\nSigned-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>\n\n--- a/drivers/mtd/spi/sf_ops.c\n+++ b/drivers/mtd/spi/sf_ops.c\n@@ -132,12 +132,6 @@ int spi_flash_write_common(struct spi_fl\n \tif (buf == NULL)\n \t\ttimeout = SPI_FLASH_PAGE_ERASE_TIMEOUT;\n \n-\tret = spi_claim_bus(flash->spi);\n-\tif (ret) {\n-\t\tdebug(\"SF: unable to claim SPI bus\\n\");\n-\t\treturn ret;\n-\t}\n-\n \tret = spi_flash_cmd_write_enable(flash);\n \tif (ret < 0) {\n \t\tdebug(\"SF: enabling write failed\\n\");\n@@ -158,8 +152,6 @@ int spi_flash_write_common(struct spi_fl\n \t\treturn ret;\n \t}\n \n-\tspi_release_bus(spi);\n-\n \treturn ret;\n }\n \n@@ -175,12 +167,18 @@ int spi_flash_cmd_erase_ops(struct spi_f\n \t\treturn -1;\n \t}\n \n+\tret = spi_claim_bus(flash->spi);\n+\tif (ret) {\n+\t\tdebug(\"SF: unable to claim SPI bus\\n\");\n+\t\treturn ret;\n+\t}\n+\n \tcmd[0] = flash->erase_cmd;\n \twhile (len) {\n #ifdef CONFIG_SPI_FLASH_BAR\n \t\tret = spi_flash_bank(flash, offset);\n \t\tif (ret < 0)\n-\t\t\treturn ret;\n+\t\t\tgoto done;\n #endif\n \t\tspi_flash_addr(offset, cmd);\n \n@@ -190,13 +188,16 @@ int spi_flash_cmd_erase_ops(struct spi_f\n \t\tret = spi_flash_write_common(flash, cmd, sizeof(cmd), NULL, 0);\n \t\tif (ret < 0) {\n \t\t\tdebug(\"SF: erase failed\\n\");\n-\t\t\tbreak;\n+\t\t\tgoto done;\n \t\t}\n \n \t\toffset += erase_size;\n \t\tlen -= erase_size;\n \t}\n \n+done:\n+\tspi_release_bus(flash->spi);\n+\n \treturn ret;\n }\n \n@@ -208,6 +209,12 @@ int spi_flash_cmd_write_ops(struct spi_f\n \tu8 cmd[4];\n \tint ret = -1;\n \n+\tret = spi_claim_bus(flash->spi);\n+\tif (ret) {\n+\t\tdebug(\"SF: unable to claim SPI bus\\n\");\n+\t\treturn ret;\n+\t}\n+\n \tpage_size = flash->page_size;\n \n \tcmd[0] = CMD_PAGE_PROGRAM;\n@@ -215,7 +222,7 @@ int spi_flash_cmd_write_ops(struct spi_f\n #ifdef CONFIG_SPI_FLASH_BAR\n \t\tret = spi_flash_bank(flash, offset);\n \t\tif (ret < 0)\n-\t\t\treturn ret;\n+\t\t\tgoto done;\n #endif\n \t\tbyte_addr = offset % page_size;\n \t\tchunk_len = min(len - actual, page_size - byte_addr);\n@@ -232,12 +239,15 @@ int spi_flash_cmd_write_ops(struct spi_f\n \t\t\t\t\tbuf + actual, chunk_len);\n \t\tif (ret < 0) {\n \t\t\tdebug(\"SF: write failed\\n\");\n-\t\t\tbreak;\n+\t\t\tgoto done;\n \t\t}\n \n \t\toffset += chunk_len;\n \t}\n \n+done:\n+\tspi_release_bus(flash->spi);\n+\n \treturn ret;\n }\n \n@@ -247,20 +257,12 @@ int spi_flash_read_common(struct spi_fla\n \tstruct spi_slave *spi = flash->spi;\n \tint ret;\n \n-\tret = spi_claim_bus(flash->spi);\n-\tif (ret) {\n-\t\tdebug(\"SF: unable to claim SPI bus\\n\");\n-\t\treturn ret;\n-\t}\n-\n \tret = spi_flash_cmd_read(spi, cmd, cmd_len, data, data_len);\n \tif (ret < 0) {\n \t\tdebug(\"SF: read cmd failed\\n\");\n \t\treturn ret;\n \t}\n \n-\tspi_release_bus(spi);\n-\n \treturn ret;\n }\n \n@@ -271,6 +273,12 @@ int spi_flash_cmd_read_ops(struct spi_fl\n \tu32 remain_len, read_len;\n \tint ret = -1;\n \n+\tret = spi_claim_bus(flash->spi);\n+\tif (ret) {\n+\t\tdebug(\"SF: unable to claim SPI bus\\n\");\n+\t\treturn ret;\n+\t}\n+\n \t/* Handle memory-mapped SPI */\n \tif (flash->memory_map) {\n \t\tspi_xfer(flash->spi, 0, NULL, NULL, SPI_XFER_MMAP);\n@@ -289,7 +297,7 @@ int spi_flash_cmd_read_ops(struct spi_fl\n \t\tret = spi_flash_cmd_bankaddr_write(flash, bank_sel);\n \t\tif (ret) {\n \t\t\tdebug(\"SF: fail to set bank%d\\n\", bank_sel);\n-\t\t\treturn ret;\n+\t\t\tgoto done;\n \t\t}\n #endif\n \t\tremain_len = (SPI_FLASH_16MB_BOUN * (bank_sel + 1)) - offset;\n@@ -304,7 +312,7 @@ int spi_flash_cmd_read_ops(struct spi_fl\n \t\t\t\t\t\t\tdata, read_len);\n \t\tif (ret < 0) {\n \t\t\tdebug(\"SF: read failed\\n\");\n-\t\t\tbreak;\n+\t\t\tgoto done;\n \t\t}\n \n \t\toffset += read_len;\n@@ -312,6 +320,9 @@ int spi_flash_cmd_read_ops(struct spi_fl\n \t\tdata += read_len;\n \t}\n \n+done:\n+\tspi_release_bus(flash->spi);\n+\n \treturn ret;\n }\n \n"
  },
  {
    "path": "package/boot/uboot-lantiq/patches/0002-sf-consistently-use-debug-for-warning-error-messages.patch",
    "content": "From bb7df8c6ff30be3786483767d3afb0e77a69a640 Mon Sep 17 00:00:00 2001\nFrom: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>\nDate: Sat, 12 Oct 2013 21:21:18 +0200\nSubject: sf: consistently use debug() for warning/error messages\n\nSigned-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>\n\n--- a/drivers/mtd/spi/sf_probe.c\n+++ b/drivers/mtd/spi/sf_probe.c\n@@ -176,8 +176,8 @@ static struct spi_flash *spi_flash_valid\n \t}\n \n \tif (i == ARRAY_SIZE(spi_flash_params_table)) {\n-\t\tprintf(\"SF: Unsupported flash IDs: \");\n-\t\tprintf(\"manuf %02x, jedec %04x, ext_jedec %04x\\n\",\n+\t\tdebug(\"SF: Unsupported flash IDs: \");\n+\t\tdebug(\"manuf %02x, jedec %04x, ext_jedec %04x\\n\",\n \t\t       idcode[0], jedec, ext_jedec);\n \t\treturn NULL;\n \t}\n@@ -296,7 +296,7 @@ struct spi_flash *spi_flash_probe(unsign\n \t/* Setup spi_slave */\n \tspi = spi_setup_slave(bus, cs, max_hz, spi_mode);\n \tif (!spi) {\n-\t\tprintf(\"SF: Failed to set up slave\\n\");\n+\t\tdebug(\"SF: Failed to set up slave\\n\");\n \t\treturn NULL;\n \t}\n \n@@ -310,7 +310,7 @@ struct spi_flash *spi_flash_probe(unsign\n \t/* Read the ID codes */\n \tret = spi_flash_cmd(spi, CMD_READ_ID, idcode, sizeof(idcode));\n \tif (ret) {\n-\t\tprintf(\"SF: Failed to get idcodes\\n\");\n+\t\tdebug(\"SF: Failed to get idcodes\\n\");\n \t\tgoto err_read_id;\n \t}\n \n@@ -341,8 +341,8 @@ struct spi_flash *spi_flash_probe(unsign\n #endif\n #ifndef CONFIG_SPI_FLASH_BAR\n \tif (flash->size > SPI_FLASH_16MB_BOUN) {\n-\t\tputs(\"SF: Warning - Only lower 16MiB accessible,\");\n-\t\tputs(\" Full access #define CONFIG_SPI_FLASH_BAR\\n\");\n+\t\tdebug(\"SF: Warning - Only lower 16MiB accessible,\");\n+\t\tdebug(\" Full access #define CONFIG_SPI_FLASH_BAR\\n\");\n \t}\n #endif\n \n"
  },
  {
    "path": "package/boot/uboot-lantiq/patches/0003-sf-move-malloc-of-spi_flash-to-spi_flash_probe.patch",
    "content": "From 36b7400465fe2339f1c78274b3fd258ade3a4c00 Mon Sep 17 00:00:00 2001\nFrom: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>\nDate: Sat, 12 Oct 2013 21:30:07 +0200\nSubject: sf: move malloc of spi_flash to spi_flash_probe()\n\nSigned-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>\n\n--- a/drivers/mtd/spi/sf_probe.c\n+++ b/drivers/mtd/spi/sf_probe.c\n@@ -153,11 +153,10 @@ static const struct spi_flash_params spi\n \t */\n };\n \n-static struct spi_flash *spi_flash_validate_params(struct spi_slave *spi,\n+static int spi_flash_validate_params(struct spi_flash *flash,\n \t\tu8 *idcode)\n {\n \tconst struct spi_flash_params *params;\n-\tstruct spi_flash *flash;\n \tint i;\n \tu16 jedec = idcode[1] << 8 | idcode[2];\n \tu16 ext_jedec = idcode[3] << 8 | idcode[4];\n@@ -179,20 +178,12 @@ static struct spi_flash *spi_flash_valid\n \t\tdebug(\"SF: Unsupported flash IDs: \");\n \t\tdebug(\"manuf %02x, jedec %04x, ext_jedec %04x\\n\",\n \t\t       idcode[0], jedec, ext_jedec);\n-\t\treturn NULL;\n-\t}\n-\n-\tflash = malloc(sizeof(*flash));\n-\tif (!flash) {\n-\t\tdebug(\"SF: Failed to allocate spi_flash\\n\");\n-\t\treturn NULL;\n+\t\treturn -1;\n \t}\n-\tmemset(flash, '\\0', sizeof(*flash));\n \n \t/* Assign spi data */\n-\tflash->spi = spi;\n \tflash->name = params->name;\n-\tflash->memory_map = spi->memory_map;\n+\tflash->memory_map = flash->spi->memory_map;\n \n \t/* Assign spi_flash ops */\n \tflash->write = spi_flash_cmd_write_ops;\n@@ -239,7 +230,7 @@ static struct spi_flash *spi_flash_valid\n \t\tif (spi_flash_read_common(flash, &flash->bank_read_cmd, 1,\n \t\t\t\t\t  &curr_bank, 1)) {\n \t\t\tdebug(\"SF: fail to read bank addr register\\n\");\n-\t\t\treturn NULL;\n+\t\t\treturn -1;\n \t\t}\n \t\tflash->bank_curr = curr_bank;\n \t} else {\n@@ -254,7 +245,7 @@ static struct spi_flash *spi_flash_valid\n \t\tspi_flash_cmd_write_status(flash, 0);\n #endif\n \n-\treturn flash;\n+\treturn 0;\n }\n \n #ifdef CONFIG_OF_CONTROL\n@@ -289,15 +280,22 @@ struct spi_flash *spi_flash_probe(unsign\n \t\tunsigned int max_hz, unsigned int spi_mode)\n {\n \tstruct spi_slave *spi;\n-\tstruct spi_flash *flash = NULL;\n+\tstruct spi_flash *flash;\n \tu8 idcode[5];\n \tint ret;\n \n+\tflash = malloc(sizeof(*flash));\n+\tif (!flash) {\n+\t\tdebug(\"SF: Failed to allocate spi_flash\\n\");\n+\t\treturn NULL;\n+\t}\n+\tmemset(flash, 0, sizeof(*flash));\n+\n \t/* Setup spi_slave */\n \tspi = spi_setup_slave(bus, cs, max_hz, spi_mode);\n \tif (!spi) {\n \t\tdebug(\"SF: Failed to set up slave\\n\");\n-\t\treturn NULL;\n+\t\tgoto err_setup;\n \t}\n \n \t/* Claim spi bus */\n@@ -320,8 +318,9 @@ struct spi_flash *spi_flash_probe(unsign\n #endif\n \n \t/* Validate params from spi_flash_params table */\n-\tflash = spi_flash_validate_params(spi, idcode);\n-\tif (!flash)\n+\tflash->spi = spi;\n+\tret = spi_flash_validate_params(flash, idcode);\n+\tif (ret)\n \t\tgoto err_read_id;\n \n #ifdef CONFIG_OF_CONTROL\n@@ -355,6 +354,9 @@ err_read_id:\n \tspi_release_bus(spi);\n err_claim_bus:\n \tspi_free_slave(spi);\n+err_setup:\n+\tfree(flash);\n+\n \treturn NULL;\n }\n \n"
  },
  {
    "path": "package/boot/uboot-lantiq/patches/0004-sf-add-slim-probe-funtions-for-SPL.patch",
    "content": "From da11da943487e2f724f25d409bcaa1f099637c0b Mon Sep 17 00:00:00 2001\nFrom: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>\nDate: Sun, 13 Oct 2013 14:56:45 +0200\nSubject: sf: add slim probe funtions for SPL\n\nSigned-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>\n\n--- a/drivers/mtd/spi/sf_probe.c\n+++ b/drivers/mtd/spi/sf_probe.c\n@@ -365,3 +365,58 @@ void spi_flash_free(struct spi_flash *fl\n \tspi_free_slave(flash->spi);\n \tfree(flash);\n }\n+\n+#ifdef CONFIG_SPI_SPL_SIMPLE\n+int spl_spi_flash_probe(struct spi_flash *flash)\n+{\n+\tstruct spi_slave *spi;\n+\tu8 idcode[5];\n+\tint ret;\n+\n+\t/* Setup spi_slave */\n+\tspi = spi_setup_slave(CONFIG_SPL_SPI_BUS, CONFIG_SPL_SPI_CS,\n+\t\tCONFIG_SPL_SPI_MAX_HZ, CONFIG_SPL_SPI_MODE);\n+\tif (!spi) {\n+\t\tdebug(\"SF: Failed to set up slave\\n\");\n+\t\treturn -1;\n+\t}\n+\n+\t/* Claim spi bus */\n+\tret = spi_claim_bus(spi);\n+\tif (ret) {\n+\t\tdebug(\"SF: Failed to claim SPI bus: %d\\n\", ret);\n+\t\tgoto err_claim_bus;\n+\t}\n+\n+\t/* Read the ID codes */\n+\tret = spi_flash_cmd(spi, CMD_READ_ID, idcode, sizeof(idcode));\n+\tif (ret) {\n+\t\tdebug(\"SF: Failed to get idcodes\\n\");\n+\t\tgoto err_read_id;\n+\t}\n+\n+\t/* Validate params from spi_flash_params table */\n+\tflash->spi = spi;\n+\tret = spi_flash_validate_params(flash, idcode);\n+\tif (ret)\n+\t\tgoto err_read_id;\n+\n+\t/* Release spi bus */\n+\tspi_release_bus(spi);\n+\n+\treturn 0;\n+\n+err_read_id:\n+\tspi_release_bus(spi);\n+err_claim_bus:\n+\tspi_free_slave(spi);\n+\tflash->spi = NULL;\n+\n+\treturn ret;\n+}\n+\n+void spl_spi_flash_free(struct spi_flash *flash)\n+{\n+\tspi_free_slave(flash->spi);\n+}\n+#endif\n--- a/include/spi_flash.h\n+++ b/include/spi_flash.h\n@@ -69,6 +69,9 @@ struct spi_flash *spi_flash_probe(unsign\n \t\tunsigned int max_hz, unsigned int spi_mode);\n void spi_flash_free(struct spi_flash *flash);\n \n+int spl_spi_flash_probe(struct spi_flash *flash);\n+void spl_spi_flash_free(struct spi_flash *flash);\n+\n static inline int spi_flash_read(struct spi_flash *flash, u32 offset,\n \t\tsize_t len, void *buf)\n {\n"
  },
  {
    "path": "package/boot/uboot-lantiq/patches/0005-sf-make-calculatiom-of-address-bytes-completely-conf.patch",
    "content": "From 6fb5f86b094756d94de8abe7425e3d290ff22dd2 Mon Sep 17 00:00:00 2001\nFrom: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>\nDate: Sun, 13 Oct 2013 15:09:28 +0200\nSubject: sf: make calculatiom of address bytes completely configurable\n\nSigned-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>\n\n--- a/drivers/mtd/spi/sf_ops.c\n+++ b/drivers/mtd/spi/sf_ops.c\n@@ -15,12 +15,17 @@\n \n #include \"sf_internal.h\"\n \n-static void spi_flash_addr(u32 addr, u8 *cmd)\n+static void spi_flash_addr(const struct spi_flash *flash, u32 addr, u8 *cmd)\n {\n \t/* cmd[0] is actual command */\n-\tcmd[1] = addr >> 16;\n-\tcmd[2] = addr >> 8;\n-\tcmd[3] = addr >> 0;\n+\tcmd[1] = addr >> (flash->addr_width * 8 - 8);\n+\tcmd[2] = addr >> (flash->addr_width * 8 - 16);\n+\tcmd[3] = addr >> (flash->addr_width * 8 - 24);\n+}\n+\n+static int spi_flash_cmdsz(const struct spi_flash *flash)\n+{\n+\treturn 1 + flash->addr_width;\n }\n \n int spi_flash_cmd_write_status(struct spi_flash *flash, u8 sr)\n@@ -158,7 +163,7 @@ int spi_flash_write_common(struct spi_fl\n int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len)\n {\n \tu32 erase_size;\n-\tu8 cmd[4];\n+\tu8 cmd[4], cmd_len;\n \tint ret = -1;\n \n \terase_size = flash->erase_size;\n@@ -180,12 +185,13 @@ int spi_flash_cmd_erase_ops(struct spi_f\n \t\tif (ret < 0)\n \t\t\tgoto done;\n #endif\n-\t\tspi_flash_addr(offset, cmd);\n+\t\tspi_flash_addr(flash, offset, cmd);\n+\t\tcmd_len = spi_flash_cmdsz(flash);\n \n \t\tdebug(\"SF: erase %2x %2x %2x %2x (%x)\\n\", cmd[0], cmd[1],\n \t\t      cmd[2], cmd[3], offset);\n \n-\t\tret = spi_flash_write_common(flash, cmd, sizeof(cmd), NULL, 0);\n+\t\tret = spi_flash_write_common(flash, cmd, cmd_len, NULL, 0);\n \t\tif (ret < 0) {\n \t\t\tdebug(\"SF: erase failed\\n\");\n \t\t\tgoto done;\n@@ -206,7 +212,7 @@ int spi_flash_cmd_write_ops(struct spi_f\n {\n \tunsigned long byte_addr, page_size;\n \tsize_t chunk_len, actual;\n-\tu8 cmd[4];\n+\tu8 cmd[4], cmd_len;\n \tint ret = -1;\n \n \tret = spi_claim_bus(flash->spi);\n@@ -230,12 +236,13 @@ int spi_flash_cmd_write_ops(struct spi_f\n \t\tif (flash->spi->max_write_size)\n \t\t\tchunk_len = min(chunk_len, flash->spi->max_write_size);\n \n-\t\tspi_flash_addr(offset, cmd);\n+\t\tspi_flash_addr(flash, offset, cmd);\n+\t\tcmd_len = spi_flash_cmdsz(flash);\n \n \t\tdebug(\"PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zu\\n\",\n \t\t      buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len);\n \n-\t\tret = spi_flash_write_common(flash, cmd, sizeof(cmd),\n+\t\tret = spi_flash_write_common(flash, cmd, cmd_len,\n \t\t\t\t\tbuf + actual, chunk_len);\n \t\tif (ret < 0) {\n \t\t\tdebug(\"SF: write failed\\n\");\n@@ -269,7 +276,7 @@ int spi_flash_read_common(struct spi_fla\n int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,\n \t\tsize_t len, void *data)\n {\n-\tu8 cmd[5], bank_sel = 0;\n+\tu8 cmd[5], cmd_len, bank_sel = 0;\n \tu32 remain_len, read_len;\n \tint ret = -1;\n \n@@ -288,7 +295,6 @@ int spi_flash_cmd_read_ops(struct spi_fl\n \t}\n \n \tcmd[0] = CMD_READ_ARRAY_FAST;\n-\tcmd[4] = 0x00;\n \n \twhile (len) {\n #ifdef CONFIG_SPI_FLASH_BAR\n@@ -306,9 +312,11 @@ int spi_flash_cmd_read_ops(struct spi_fl\n \t\telse\n \t\t\tread_len = remain_len;\n \n-\t\tspi_flash_addr(offset, cmd);\n+\t\tspi_flash_addr(flash, offset, cmd);\n+\t\tcmd_len = spi_flash_cmdsz(flash);\n+\t\tcmd[cmd_len] = 0x00;\n \n-\t\tret = spi_flash_read_common(flash, cmd, sizeof(cmd),\n+\t\tret = spi_flash_read_common(flash, cmd, cmd_len + 1,\n \t\t\t\t\t\t\tdata, read_len);\n \t\tif (ret < 0) {\n \t\t\tdebug(\"SF: read failed\\n\");\n--- a/drivers/mtd/spi/sf_probe.c\n+++ b/drivers/mtd/spi/sf_probe.c\n@@ -218,6 +218,9 @@ static int spi_flash_validate_params(str\n \t\tflash->poll_cmd = CMD_FLAG_STATUS;\n #endif\n \n+\t/* Configure default 3-byte addressing */\n+\tflash->addr_width = 3;\n+\n \t/* Configure the BAR - discover bank cmds and read current bank */\n #ifdef CONFIG_SPI_FLASH_BAR\n \tu8 curr_bank = 0;\n--- a/include/spi_flash.h\n+++ b/include/spi_flash.h\n@@ -57,6 +57,7 @@ struct spi_flash {\n #endif\n \tu8 poll_cmd;\n \tu8 erase_cmd;\n+\tu8 addr_width;\n \n \tvoid *memory_map;\n \tint (*read)(struct spi_flash *flash, u32 offset, size_t len, void *buf);\n"
  },
  {
    "path": "package/boot/uboot-lantiq/patches/0006-sf-add-support-for-4-byte-addressing.patch",
    "content": "From 3af3addee645bd81537be1ddee49969f8dfc64ee Mon Sep 17 00:00:00 2001\nFrom: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>\nDate: Sun, 13 Oct 2013 15:24:56 +0200\nSubject: sf: add support for 4-byte addressing\n\nSigned-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>\n\n--- a/drivers/mtd/spi/sf_internal.h\n+++ b/drivers/mtd/spi/sf_internal.h\n@@ -38,12 +38,14 @@\n #define CMD_READ_ID\t\t\t0x9f\n \n /* Bank addr access commands */\n-#ifdef CONFIG_SPI_FLASH_BAR\n-# define CMD_BANKADDR_BRWR\t\t0x17\n-# define CMD_BANKADDR_BRRD\t\t0x16\n-# define CMD_EXTNADDR_WREAR\t\t0xC5\n-# define CMD_EXTNADDR_RDEAR\t\t0xC8\n-#endif\n+#define CMD_BANKADDR_BRWR\t\t0x17\n+#define CMD_BANKADDR_BRRD\t\t0x16\n+#define CMD_EXTNADDR_WREAR\t\t0xC5\n+#define CMD_EXTNADDR_RDEAR\t\t0xC8\n+\n+/* Macronix style 4-byte addressing */\n+#define CMD_EN4B\t\t\t0xb7\n+#define CMD_EX4B\t\t\t0xe9\n \n /* Common status */\n #define STATUS_WIP\t\t\t0x01\n--- a/drivers/mtd/spi/sf_ops.c\n+++ b/drivers/mtd/spi/sf_ops.c\n@@ -21,6 +21,7 @@ static void spi_flash_addr(const struct\n \tcmd[1] = addr >> (flash->addr_width * 8 - 8);\n \tcmd[2] = addr >> (flash->addr_width * 8 - 16);\n \tcmd[3] = addr >> (flash->addr_width * 8 - 24);\n+\tcmd[4] = addr >> (flash->addr_width * 8 - 32);\n }\n \n static int spi_flash_cmdsz(const struct spi_flash *flash)\n@@ -163,7 +164,7 @@ int spi_flash_write_common(struct spi_fl\n int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len)\n {\n \tu32 erase_size;\n-\tu8 cmd[4], cmd_len;\n+\tu8 cmd[5], cmd_len;\n \tint ret = -1;\n \n \terase_size = flash->erase_size;\n@@ -188,8 +189,8 @@ int spi_flash_cmd_erase_ops(struct spi_f\n \t\tspi_flash_addr(flash, offset, cmd);\n \t\tcmd_len = spi_flash_cmdsz(flash);\n \n-\t\tdebug(\"SF: erase %2x %2x %2x %2x (%x)\\n\", cmd[0], cmd[1],\n-\t\t      cmd[2], cmd[3], offset);\n+\t\tdebug(\"SF: erase %2x %2x %2x %2x %2x (%x)\\n\", cmd[0], cmd[1],\n+\t\t      cmd[2], cmd[3], cmd[4], offset);\n \n \t\tret = spi_flash_write_common(flash, cmd, cmd_len, NULL, 0);\n \t\tif (ret < 0) {\n@@ -212,7 +213,7 @@ int spi_flash_cmd_write_ops(struct spi_f\n {\n \tunsigned long byte_addr, page_size;\n \tsize_t chunk_len, actual;\n-\tu8 cmd[4], cmd_len;\n+\tu8 cmd[5], cmd_len;\n \tint ret = -1;\n \n \tret = spi_claim_bus(flash->spi);\n@@ -239,8 +240,8 @@ int spi_flash_cmd_write_ops(struct spi_f\n \t\tspi_flash_addr(flash, offset, cmd);\n \t\tcmd_len = spi_flash_cmdsz(flash);\n \n-\t\tdebug(\"PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zu\\n\",\n-\t\t      buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len);\n+\t\tdebug(\"PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x%02x } chunk_len = %zu\\n\",\n+\t\t      buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], cmd[4], chunk_len);\n \n \t\tret = spi_flash_write_common(flash, cmd, cmd_len,\n \t\t\t\t\tbuf + actual, chunk_len);\n@@ -276,9 +277,13 @@ int spi_flash_read_common(struct spi_fla\n int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,\n \t\tsize_t len, void *data)\n {\n-\tu8 cmd[5], cmd_len, bank_sel = 0;\n-\tu32 remain_len, read_len;\n+\tu8 cmd[6], cmd_len;\n+\tu32 read_len;\n \tint ret = -1;\n+#ifdef CONFIG_SPI_FLASH_BAR\n+\tu8 bank_sel = 0;\n+\tu32 remain_len;\n+#endif\n \n \tret = spi_claim_bus(flash->spi);\n \tif (ret) {\n@@ -305,12 +310,15 @@ int spi_flash_cmd_read_ops(struct spi_fl\n \t\t\tdebug(\"SF: fail to set bank%d\\n\", bank_sel);\n \t\t\tgoto done;\n \t\t}\n-#endif\n+\n \t\tremain_len = (SPI_FLASH_16MB_BOUN * (bank_sel + 1)) - offset;\n \t\tif (len < remain_len)\n \t\t\tread_len = len;\n \t\telse\n \t\t\tread_len = remain_len;\n+#else\n+\t\tread_len = len;\n+#endif\n \n \t\tspi_flash_addr(flash, offset, cmd);\n \t\tcmd_len = spi_flash_cmdsz(flash);\n--- a/drivers/mtd/spi/sf_probe.c\n+++ b/drivers/mtd/spi/sf_probe.c\n@@ -153,6 +153,25 @@ static const struct spi_flash_params spi\n \t */\n };\n \n+int spi_flash_4byte_set(struct spi_flash *flash, u8 idcode0, int enable)\n+{\n+\tu8 cmd, bankaddr;\n+\n+\tswitch (idcode0) {\n+\tcase 0xc2:\n+\tcase 0xef:\n+\tcase 0x1c:\n+\t\t/* Macronix style */\n+\t\tcmd = enable ? CMD_EN4B : CMD_EX4B;\n+\t\treturn spi_flash_cmd(flash->spi, cmd, NULL, 0);\n+\tdefault:\n+\t\t/* Spansion style */\n+\t\tcmd = CMD_BANKADDR_BRWR;\n+\t\tbankaddr = enable << 7;\n+\t\treturn spi_flash_cmd_write(flash->spi, &cmd, 1, &bankaddr, 1);\n+\t}\n+}\n+\n static int spi_flash_validate_params(struct spi_flash *flash,\n \t\tu8 *idcode)\n {\n@@ -218,8 +237,18 @@ static int spi_flash_validate_params(str\n \t\tflash->poll_cmd = CMD_FLAG_STATUS;\n #endif\n \n+#ifndef CONFIG_SPI_FLASH_BAR\n+\t/* enable 4-byte addressing if the device exceeds 16MiB */\n+\tif (flash->size > SPI_FLASH_16MB_BOUN) {\n+\t\tflash->addr_width = 4;\n+\t\tspi_flash_4byte_set(flash, idcode[0], 1);\n+\t} else {\n+\t\tflash->addr_width = 3;\n+\t}\n+#else\n \t/* Configure default 3-byte addressing */\n \tflash->addr_width = 3;\n+#endif\n \n \t/* Configure the BAR - discover bank cmds and read current bank */\n #ifdef CONFIG_SPI_FLASH_BAR\n"
  },
  {
    "path": "package/boot/uboot-lantiq/patches/0007-sf-add-support-for-EN25QH256.patch",
    "content": "From d5aa0d4117a439803a3d074d2745372036d2a1eb Mon Sep 17 00:00:00 2001\nFrom: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>\nDate: Sun, 13 Oct 2013 15:35:34 +0200\nSubject: sf: add support for EN25QH256\n\nSigned-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>\n\n--- a/drivers/mtd/spi/sf_probe.c\n+++ b/drivers/mtd/spi/sf_probe.c\n@@ -53,6 +53,7 @@ static const struct spi_flash_params spi\n \t{\"EN25Q64\",\t   0x1c3017, 0x0,\t64 * 1024,   128,\t       SECT_4K},\n \t{\"EN25Q128B\",\t   0x1c3018, 0x0,       64 * 1024,   256,\t             0},\n \t{\"EN25S64\",\t   0x1c3817, 0x0,\t64 * 1024,   128,\t\t     0},\n+\t{\"EN25QH256\",\t   0x1c7019, 0x0,\t64 * 1024,   512,\t\t     0},\n #endif\n #ifdef CONFIG_SPI_FLASH_GIGADEVICE\t/* GIGADEVICE */\n \t{\"GD25Q64B\",\t   0xc84017, 0x0,\t64 * 1024,   128,\t       SECT_4K},\n"
  },
  {
    "path": "package/boot/uboot-lantiq/patches/0008-sf-fix-sector-layout-of-S25FL256S_256K-and-S25FL512S.patch",
    "content": "From 5a6d8045190c887c7f65e65fb1bfc8854774c458 Mon Sep 17 00:00:00 2001\nFrom: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>\nDate: Sun, 13 Oct 2013 15:40:07 +0200\nSubject: sf: fix sector layout of S25FL256S_256K and S25FL512S_256K\n\nSigned-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>\n\n--- a/drivers/mtd/spi/sf_probe.c\n+++ b/drivers/mtd/spi/sf_probe.c\n@@ -80,9 +80,9 @@ static const struct spi_flash_params spi\n \t{\"S25FL032P\",\t   0x010215, 0x4d00,    64 * 1024,    64,\t             0},\n \t{\"S25FL064P\",\t   0x010216, 0x4d00,    64 * 1024,   128,\t             0},\n \t{\"S25FL128S_64K\",  0x012018, 0x4d01,    64 * 1024,   256,\t\t     0},\n-\t{\"S25FL256S_256K\", 0x010219, 0x4d00,    64 * 1024,   512,\t             0},\n+\t{\"S25FL256S_256K\", 0x010219, 0x4d00,   256 * 1024,   128,\t             0},\n \t{\"S25FL256S_64K\",  0x010219, 0x4d01,    64 * 1024,   512,\t             0},\n-\t{\"S25FL512S_256K\", 0x010220, 0x4d00,    64 * 1024,  1024,\t             0},\n+\t{\"S25FL512S_256K\", 0x010220, 0x4d00,   256 * 1024,   256,\t             0},\n \t{\"S25FL512S_64K\",  0x010220, 0x4d01,    64 * 1024,  1024,\t             0},\n #endif\n #ifdef CONFIG_SPI_FLASH_STMICRO\t\t/* STMICRO */\n"
  },
  {
    "path": "package/boot/uboot-lantiq/patches/0009-net-switchlib-add-framework-for-ethernet-switch-driv.patch",
    "content": "From 0dff8c753c8929a478357abb38db0d1c1a60ec94 Mon Sep 17 00:00:00 2001\nFrom: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>\nDate: Wed, 29 Aug 2012 22:08:15 +0200\nSubject: net: switchlib: add framework for ethernet switch drivers\n\nAdd a generic framework similar to phylib for ethernet switch\ndrivers and devices. This is useful to share the init and\nsetup code for switch devices across different boards.\n\nSigned-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>\nCc: Joe Hershberger <joe.hershberger@gmail.com>\n\n--- a/Makefile\n+++ b/Makefile\n@@ -280,6 +280,7 @@ LIBS-y += drivers/mtd/ubi/libubi.o\n LIBS-y += drivers/mtd/spi/libspi_flash.o\n LIBS-y += drivers/net/libnet.o\n LIBS-y += drivers/net/phy/libphy.o\n+LIBS-y += drivers/net/switch/libswitch.o\n LIBS-y += drivers/pci/libpci.o\n LIBS-y += drivers/pcmcia/libpcmcia.o\n LIBS-y += drivers/power/libpower.o \\\n--- /dev/null\n+++ b/drivers/net/switch/Makefile\n@@ -0,0 +1,30 @@\n+#\n+# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de\n+# Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com\n+#\n+# SPDX-License-Identifier:\tGPL-2.0+\n+#\n+\n+include $(TOPDIR)/config.mk\n+\n+LIB\t:= $(obj)libswitch.o\n+\n+COBJS-$(CONFIG_SWITCH_MULTI) += switch.o\n+\n+COBJS\t:= $(COBJS-y)\n+SRCS\t:= $(COBJS:.o=.c)\n+OBJS\t:= $(addprefix $(obj),$(COBJS))\n+\n+all:\t$(LIB)\n+\n+$(LIB):\t$(obj).depend $(OBJS)\n+\t$(call cmd_link_o_target, $(OBJS))\n+\n+#########################################################################\n+\n+# defines $(obj).depend target\n+include $(SRCTREE)/rules.mk\n+\n+sinclude $(obj).depend\n+\n+#########################################################################\n--- /dev/null\n+++ b/drivers/net/switch/switch.c\n@@ -0,0 +1,62 @@\n+/*\n+ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#include <common.h>\n+#include <netdev.h>\n+#include <miiphy.h>\n+#include <switch.h>\n+\n+static struct list_head switch_drivers;\n+static struct list_head switch_devices;\n+\n+void switch_init(void)\n+{\n+\tINIT_LIST_HEAD(&switch_drivers);\n+\tINIT_LIST_HEAD(&switch_devices);\n+\n+\tboard_switch_init();\n+}\n+\n+void switch_driver_register(struct switch_driver *drv)\n+{\n+\tINIT_LIST_HEAD(&drv->list);\n+\tlist_add_tail(&drv->list, &switch_drivers);\n+}\n+\n+int switch_device_register(struct switch_device *dev)\n+{\n+\tstruct switch_driver *drv;\n+\n+\t/* Add switch device only, if an adequate driver is registered */\n+\tlist_for_each_entry(drv, &switch_drivers, list) {\n+\t\tif (!strcmp(drv->name, dev->name)) {\n+\t\t\tdev->drv = drv;\n+\n+\t\t\tINIT_LIST_HEAD(&dev->list);\n+\t\t\tlist_add_tail(&dev->list, &switch_devices);\n+\n+\t\t\treturn 0;\n+\t\t}\n+\t}\n+\n+\treturn -1;\n+}\n+\n+struct switch_device *switch_connect(struct mii_dev *bus)\n+{\n+\tstruct switch_device *sw;\n+\tint err;\n+\n+\tlist_for_each_entry(sw, &switch_devices, list) {\n+\t\tsw->bus = bus;\n+\n+\t\terr = sw->drv->probe(sw);\n+\t\tif (!err)\n+\t\t\treturn sw;\n+\t}\n+\n+\treturn NULL;\n+}\n--- /dev/null\n+++ b/include/switch.h\n@@ -0,0 +1,102 @@\n+/*\n+ * This file is released under the terms of GPL v2 and any later version.\n+ * See the file COPYING in the root directory of the source tree for details.\n+ *\n+ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com\n+ */\n+\n+#ifndef __SWITCH_H\n+#define __SWITCH_H\n+\n+#include <linux/list.h>\n+\n+#define SWITCH_NAME_SIZE\t32\n+\n+struct switch_device;\n+struct mii_dev;\n+\n+struct switch_driver {\n+\tstruct list_head list;\n+\n+\t/* Switch device name */\n+\tconst char name[SWITCH_NAME_SIZE];\n+\n+\t/*\n+\t * Called to probe the switch chip. Must return 0 if the switch\n+\t * chip matches the given switch device/driver combination. Otherwise\n+\t * 1 must be returned.\n+\t */\n+\tint (*probe) (struct switch_device *dev);\n+\n+\t/*\n+\t * Called to initialize the switch chip.\n+\t */\n+\tvoid (*setup) (struct switch_device *dev);\n+};\n+\n+struct switch_device {\n+\tstruct list_head list;\n+\tstruct switch_driver *drv;\n+\n+\t/* MII bus the switch chip is connected to */\n+\tstruct mii_dev *bus;\n+\n+\t/* Switch device name */\n+\tconst char name[SWITCH_NAME_SIZE];\n+\n+\t/* Bitmask for board specific setup of used switch ports */\n+\tu16 port_mask;\n+\n+\t/* Number of switch port that is connected to host CPU */\n+\tu16 cpu_port;\n+};\n+\n+/*\n+ * Board specific switch initialization.\n+ *\n+ * Called from switch_init to register the board specific switch_device\n+ * structure.\n+ */\n+extern int board_switch_init(void);\n+\n+/* Initialize switch subsystem */\n+#ifdef CONFIG_SWITCH_MULTI\n+extern void switch_init(void);\n+#else\n+static inline void switch_init(void)\n+{\n+}\n+#endif\n+\n+/* Register a switch driver */\n+extern void switch_driver_register(struct switch_driver *drv);\n+\n+/* Register a switch device */\n+extern int switch_device_register(struct switch_device *dev);\n+\n+/*\n+ * Probe the available switch chips and connect the found one\n+ * with the given MII bus\n+ */\n+#ifdef CONFIG_SWITCH_MULTI\n+extern struct switch_device *switch_connect(struct mii_dev *bus);\n+#else\n+static inline struct switch_device *switch_connect(struct mii_dev *bus)\n+{\n+\treturn NULL;\n+}\n+#endif\n+\n+/*\n+ * Setup the given switch device\n+ */\n+static inline void switch_setup(struct switch_device *dev)\n+{\n+\tif (dev->drv->setup)\n+\t\tdev->drv->setup(dev);\n+}\n+\n+/* Init functions for supported Switch drivers */\n+\n+#endif /* __SWITCH_H */\n+\n--- a/net/eth.c\n+++ b/net/eth.c\n@@ -10,6 +10,7 @@\n #include <net.h>\n #include <miiphy.h>\n #include <phy.h>\n+#include <switch.h>\n \n void eth_parse_enetaddr(const char *addr, uchar *enetaddr)\n {\n@@ -287,6 +288,8 @@ int eth_initialize(bd_t *bis)\n \tphy_init();\n #endif\n \n+\tswitch_init();\n+\n \teth_env_init(bis);\n \n \t/*\n"
  },
  {
    "path": "package/boot/uboot-lantiq/patches/0010-net-switchlib-add-driver-for-Lantiq-PSB697X-switch-f.patch",
    "content": "From e2c59cedebf72e4a002134a2932f722b508a5448 Mon Sep 17 00:00:00 2001\nFrom: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>\nDate: Wed, 29 Aug 2012 22:08:15 +0200\nSubject: net: switchlib: add driver for Lantiq PSB697X switch family\n\nSigned-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>\n\n--- a/drivers/net/switch/Makefile\n+++ b/drivers/net/switch/Makefile\n@@ -10,6 +10,7 @@ include $(TOPDIR)/config.mk\n LIB\t:= $(obj)libswitch.o\n \n COBJS-$(CONFIG_SWITCH_MULTI) += switch.o\n+COBJS-$(CONFIG_SWITCH_PSB697X) += psb697x.o\n \n COBJS\t:= $(COBJS-y)\n SRCS\t:= $(COBJS:.o=.c)\n--- /dev/null\n+++ b/drivers/net/switch/psb697x.c\n@@ -0,0 +1,118 @@\n+/*\n+ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#include <common.h>\n+#include <malloc.h>\n+#include <switch.h>\n+#include <miiphy.h>\n+\n+#define PSB697X_CHIPID1\t\t0x2599\n+#define PSB697X_PORT_COUNT\t7\n+\n+#define PSB697X_PORT_BASE(p)\t(p * 0x20)\n+#define PSB697X_REG_PS(p)\t(PSB697X_PORT_BASE(p) + 0x00)\n+#define PSB697X_REG_PBC(p)\t(PSB697X_PORT_BASE(p) + 0x01)\n+#define PSB697X_REG_PEC(p)\t(PSB697X_PORT_BASE(p) + 0x02)\n+\n+#define PSB697X_REG_SGC1\t0x0E0\t/* Switch Global Control Register 1 */\n+#define PSB697X_REG_SGC2\t0x0E1\t/* Switch Global Control Register 2 */\n+#define PSB697X_REG_CMH\t\t0x0E2\t/* CPU Port & Mirror Control */\n+#define PSB697X_REG_MIICR\t0x0F5\t/* MII Port Control */\n+#define PSB697X_REG_CI0\t\t0x100\t/* Chip Identifier 0 */\n+#define PSB697X_REG_CI1\t\t0x101\t/* Chip Identifier 1 */\n+#define PSB697X_REG_MIIAC\t0x120\t/* MII Indirect Access Control */\n+#define PSB697X_REG_MIIWD\t0x121\t/* MII Indirect Write Data */\n+#define PSB697X_REG_MIIRD\t0x122\t/* MII Indirect Read Data */\n+\n+#define PSB697X_REG_PORT_FLP\t(1 << 2)\t/* Force link up */\n+#define PSB697X_REG_PORT_FLD\t(1 << 1)\t/* Force link down */\n+\n+#define PSB697X_REG_SGC2_SE\t(1 << 15)\t/* Switch enable */\n+\n+#define PSB697X_REG_CMH_CPN_MASK\t0x7\n+#define PSB697X_REG_CMH_CPN_SHIFT\t5\n+\n+\n+static inline int psb697x_mii_read(struct mii_dev *bus, u16 reg)\n+{\n+\tint ret;\n+\n+\tret = bus->read(bus, (reg >> 5) & 0x1f, MDIO_DEVAD_NONE, reg & 0x1f);\n+\n+\treturn ret;\n+}\n+\n+static inline int psb697x_mii_write(struct mii_dev *bus, u16 reg, u16 val)\n+{\n+\tint ret;\n+\n+\tret = bus->write(bus, (reg >> 5) & 0x1f, MDIO_DEVAD_NONE,\n+\t\treg & 0x1f, val);\n+\n+\treturn ret;\n+}\n+\n+static int psb697x_probe(struct switch_device *dev)\n+{\n+\tstruct mii_dev *bus = dev->bus;\n+\tint ci1;\n+\n+\tci1 = psb697x_mii_read(bus, PSB697X_REG_CI1);\n+\n+\tif (ci1 == PSB697X_CHIPID1)\n+\t\treturn 0;\n+\n+\treturn 1;\n+}\n+\n+static void psb697x_setup(struct switch_device *dev)\n+{\n+\tstruct mii_dev *bus = dev->bus;\n+\tint i, state;\n+\n+\t/* Enable switch */\n+\tpsb697x_mii_write(bus, PSB697X_REG_SGC2, PSB697X_REG_SGC2_SE);\n+\n+\t/*\n+\t * Force 100 Mbps as default value for CPU ports 5 and 6 to get\n+\t * full speed.\n+\t */\n+\tpsb697x_mii_write(bus, PSB697X_REG_MIICR, 0x0773);\n+\n+\tfor (i = 0; i < PSB697X_PORT_COUNT; i++) {\n+\t\tstate = dev->port_mask & (1 << i);\n+\n+\t\t/*\n+\t\t * Software workaround from Errata Sheet:\n+\t\t * Force link down and reset internal PHY, keep that state\n+\t\t * for all unconnected ports and disable force link down\n+\t\t * for all connected ports\n+\t\t */\n+\t\tpsb697x_mii_write(bus, PSB697X_REG_PBC(i),\n+\t\t\tPSB697X_REG_PORT_FLD);\n+\n+\t\tif (i == dev->cpu_port)\n+\t\t\t/* Force link up for CPU port */\n+\t\t\tpsb697x_mii_write(bus, PSB697X_REG_PBC(i),\n+\t\t\t\tPSB697X_REG_PORT_FLP);\n+\t\telse if (state)\n+\t\t\t/* Disable force link down for active LAN ports */\n+\t\t\tpsb697x_mii_write(bus, PSB697X_REG_PBC(i), 0);\n+\t}\n+}\n+\n+static struct switch_driver psb697x_drv = {\n+\t.name = \"psb697x\",\n+};\n+\n+void switch_psb697x_init(void)\n+{\n+\t/* For archs with manual relocation */\n+\tpsb697x_drv.probe = psb697x_probe;\n+\tpsb697x_drv.setup = psb697x_setup;\n+\n+\tswitch_driver_register(&psb697x_drv);\n+}\n--- a/drivers/net/switch/switch.c\n+++ b/drivers/net/switch/switch.c\n@@ -17,6 +17,10 @@ void switch_init(void)\n \tINIT_LIST_HEAD(&switch_drivers);\n \tINIT_LIST_HEAD(&switch_devices);\n \n+#if defined(CONFIG_SWITCH_PSB697X)\n+\tswitch_psb697x_init();\n+#endif\n+\n \tboard_switch_init();\n }\n \n--- a/include/switch.h\n+++ b/include/switch.h\n@@ -97,6 +97,7 @@ static inline void switch_setup(struct s\n }\n \n /* Init functions for supported Switch drivers */\n+extern void switch_psb697x_init(void);\n \n #endif /* __SWITCH_H */\n \n"
  },
  {
    "path": "package/boot/uboot-lantiq/patches/0011-net-switchlib-add-driver-for-Lantiq-ADM6996I-switch-.patch",
    "content": "From c291443dc97dadcf0c6afd04688a7d9f79a221b5 Mon Sep 17 00:00:00 2001\nFrom: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>\nDate: Wed, 29 Aug 2012 22:08:16 +0200\nSubject: net: switchlib: add driver for Lantiq ADM6996I switch family\n\nSigned-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>\n\n--- a/drivers/net/switch/Makefile\n+++ b/drivers/net/switch/Makefile\n@@ -11,6 +11,7 @@ LIB\t:= $(obj)libswitch.o\n \n COBJS-$(CONFIG_SWITCH_MULTI) += switch.o\n COBJS-$(CONFIG_SWITCH_PSB697X) += psb697x.o\n+COBJS-$(CONFIG_SWITCH_ADM6996I) += adm6996i.o\n \n COBJS\t:= $(COBJS-y)\n SRCS\t:= $(COBJS:.o=.c)\n--- /dev/null\n+++ b/drivers/net/switch/adm6996i.c\n@@ -0,0 +1,115 @@\n+/*\n+ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#include <common.h>\n+#include <malloc.h>\n+#include <switch.h>\n+#include <miiphy.h>\n+\n+#define ADM6996I_CHIPID0\t0x1020\n+#define ADM6996I_CHIPID1\t0x0007\n+#define ADM6996I_PORT_COUNT\t6\n+\n+#define ADM6996I_REG_P0BC\t0x001\t/* P0 Basic Control */\n+#define ADM6996I_REG_P1BC\t0x003\t/* P1 Basic Control */\n+#define ADM6996I_REG_P2BC\t0x005\t/* P2 Basic Control */\n+#define ADM6996I_REG_P3BC\t0x007\t/* P3 Basic Control */\n+#define ADM6996I_REG_P4BC\t0x008\t/* P4 Basic Control */\n+#define ADM6996I_REG_P5BC\t0x009\t/* P5 Basic Control */\n+\n+#define ADM6996I_REG_P0EC\t0x002\t/* P0 Extended Control */\n+#define ADM6996I_REG_P1EC\t0x002\t/* P1 Extended Control */\n+#define ADM6996I_REG_P2EC\t0x004\t/* P2 Extended Control */\n+#define ADM6996I_REG_P3EC\t0x004\t/* P3 Extended Control */\n+#define ADM6996I_REG_P4EC\t0x006\t/* P4 Extended Control */\n+#define ADM6996I_REG_P5EC\t0x006\t/* P5 Extended Control */\n+\n+#define ADM6996I_REG_SC4\t0x012\t/* System Control 4 */\n+\n+#define ADM6996I_REG_CI0\t0xA0\t/* Chip Identifier 0 */\n+#define ADM6996I_REG_CI1\t0xA1\t/* Chip Identifier 1 */\n+\n+#define ADM6996I_REG_PXBC_DEFAULT\t0x040F\n+#define ADM6996I_REG_PXBC_CROSS_EE\t(1 << 15)\n+#define ADM6996I_REG_PXBC_PD\t\t(1 << 5)\n+\n+#define ADM6996I_REG_SC4_DEFAULT\t0x3600\n+#define ADM6996I_REG_SC4_LED_ENABLE\t(1 << 1)\n+\n+#define ADM6996I_REG_CI0_PC_MASK\t0xFFF0\n+#define ADM6996I_REG_CI0_VN_MASK\t0xF\n+#define ADM6996I_REG_CI1_PC_MASK\t0xF\n+\n+\n+static inline int adm6996i_mii_read(struct mii_dev *bus, u16 reg)\n+{\n+\tint ret;\n+\n+\tret = bus->read(bus, (reg >> 5) & 0x1f, MDIO_DEVAD_NONE, reg & 0x1f);\n+\n+\treturn ret;\n+}\n+\n+static inline int adm6996i_mii_write(struct mii_dev *bus, u16 reg, u16 val)\n+{\n+\tint ret;\n+\n+\tret = bus->write(bus, (reg >> 5) & 0x1f, MDIO_DEVAD_NONE,\n+\t\treg & 0x1f, val);\n+\n+\treturn ret;\n+}\n+\n+static int adm6996i_probe(struct switch_device *dev)\n+{\n+\tstruct mii_dev *bus = dev->bus;\n+\tu16 ci0, ci1;\n+\n+\tci0 = adm6996i_mii_read(bus, ADM6996I_REG_CI0);\n+\tci1 = adm6996i_mii_read(bus, ADM6996I_REG_CI1);\n+\n+\tci0 &= ADM6996I_REG_CI0_PC_MASK;\n+\tci1 &= ADM6996I_REG_CI1_PC_MASK;\n+\n+\tif (ci0 == ADM6996I_CHIPID0 && ci1 == ADM6996I_CHIPID1)\n+\t\treturn 0;\n+\n+\treturn 1;\n+}\n+\n+static void adm6996i_setup(struct switch_device *dev)\n+{\n+\tstruct mii_dev *bus = dev->bus;\n+\tu16 val;\n+\n+\t/*\n+\t * Write default values (Port enable, 100 Mbps, Full Duplex,\n+\t * Auto negotiation, Flow control) and enable crossover auto-detect\n+\t */\n+\tval = ADM6996I_REG_PXBC_DEFAULT | ADM6996I_REG_PXBC_CROSS_EE;\n+\tadm6996i_mii_write(bus, ADM6996I_REG_P0BC, val);\n+\tadm6996i_mii_write(bus, ADM6996I_REG_P1BC, val);\n+\tadm6996i_mii_write(bus, ADM6996I_REG_P2BC, val);\n+\tadm6996i_mii_write(bus, ADM6996I_REG_P3BC, val);\n+\tadm6996i_mii_write(bus, ADM6996I_REG_P4BC, val);\n+\tadm6996i_mii_write(bus, ADM6996I_REG_P5BC, val);\n+\n+\tval = ADM6996I_REG_SC4_DEFAULT | ADM6996I_REG_SC4_LED_ENABLE;\n+\tadm6996i_mii_write(bus, ADM6996I_REG_SC4, val);\n+}\n+\n+static struct switch_driver adm6996i_drv = {\n+\t.name = \"adm6996i\",\n+};\n+\n+void switch_adm6996i_init(void)\n+{\n+\t/* For archs with manual relocation */\n+\tadm6996i_drv.probe = adm6996i_probe;\n+\tadm6996i_drv.setup = adm6996i_setup;\n+\n+\tswitch_driver_register(&adm6996i_drv);\n+}\n--- a/drivers/net/switch/switch.c\n+++ b/drivers/net/switch/switch.c\n@@ -20,6 +20,9 @@ void switch_init(void)\n #if defined(CONFIG_SWITCH_PSB697X)\n \tswitch_psb697x_init();\n #endif\n+#if defined(CONFIG_SWITCH_ADM6996I)\n+\tswitch_adm6996i_init();\n+#endif\n \n \tboard_switch_init();\n }\n--- a/include/switch.h\n+++ b/include/switch.h\n@@ -98,6 +98,7 @@ static inline void switch_setup(struct s\n \n /* Init functions for supported Switch drivers */\n extern void switch_psb697x_init(void);\n+extern void switch_adm6996i_init(void);\n \n #endif /* __SWITCH_H */\n \n"
  },
  {
    "path": "package/boot/uboot-lantiq/patches/0012-net-switchlib-add-driver-for-Atheros-AR8216.patch",
    "content": "From 1a1d61a2faf0390033a3766559ce0e758e15894e Mon Sep 17 00:00:00 2001\nFrom: Luka Perkov <openwrt@lukaperkov.net>\nDate: Wed, 29 Aug 2012 22:08:16 +0200\nSubject: net: switchlib: add driver for Atheros AR8216\n\nSigned-off-by: Luka Perkov <openwrt@lukaperkov.net>\nSigned-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>\n\n--- a/drivers/net/switch/Makefile\n+++ b/drivers/net/switch/Makefile\n@@ -12,6 +12,7 @@ LIB\t:= $(obj)libswitch.o\n COBJS-$(CONFIG_SWITCH_MULTI) += switch.o\n COBJS-$(CONFIG_SWITCH_PSB697X) += psb697x.o\n COBJS-$(CONFIG_SWITCH_ADM6996I) += adm6996i.o\n+COBJS-$(CONFIG_SWITCH_AR8216) += ar8216.o\n \n COBJS\t:= $(COBJS-y)\n SRCS\t:= $(COBJS:.o=.c)\n--- /dev/null\n+++ b/drivers/net/switch/ar8216.c\n@@ -0,0 +1,114 @@\n+/*\n+ * Copyright (C) 2012 Luka Perkov <luka@openwrt.org>\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#include <common.h>\n+#include <malloc.h>\n+#include <miiphy.h>\n+#include <switch.h>\n+#include <netdev.h>\n+\n+#define BITS(_s, _n)  (((1UL << (_n)) - 1) << _s)\n+\n+#define AR8216_REG_CTRL\t\t\t0x0000\n+#define   AR8216_CTRL_REVISION\t\tBITS(0, 8)\n+#define   AR8216_CTRL_VERSION\t\tBITS(8, 8)\n+\n+#define AR8216_PROBE_RETRIES\t\t10\n+\n+static void split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page)\n+{\n+\tregaddr >>= 1;\n+\t*r1 = regaddr & 0x1e;\n+\n+\tregaddr >>= 5;\n+\t*r2 = regaddr & 0x7;\n+\n+\tregaddr >>= 3;\n+\t*page = regaddr & 0x1ff;\n+}\n+\n+static int ar8216_mii_read(struct mii_dev *bus, u32 reg)\n+{\n+\tu16 r1, r2, page;\n+\tu16 lo, hi;\n+\n+\tsplit_addr(reg, &r1, &r2, &page);\n+\n+\tbus->write(bus, 0x18, MDIO_DEVAD_NONE, 0, page);\n+\t__udelay(1000);\n+\n+\tlo = bus->read(bus, 0x10 | r2, MDIO_DEVAD_NONE, r1);\n+\thi = bus->read(bus, 0x10 | r2, MDIO_DEVAD_NONE, r1 + 1);\n+\n+\treturn (hi << 16) | lo;\n+}\n+\n+static void ar8216_mii_write(struct mii_dev *bus, u16 reg, u32 val)\n+{\n+\tu16 r1, r2, r3;\n+\tu16 lo, hi;\n+\n+\tsplit_addr((u32) reg, &r1, &r2, &r3);\n+\n+\tbus->write(bus, 0x18, MDIO_DEVAD_NONE, 0, r3);\n+\t__udelay(1000);\n+\n+\tlo = val & 0xffff;\n+\thi = (u16) (val >> 16);\n+\tbus->write(bus, 0x10 | r2, MDIO_DEVAD_NONE, r1 + 1, hi);\n+\tbus->write(bus, 0x10 | r2, MDIO_DEVAD_NONE, r1, lo);\n+}\n+\n+static int ar8216_probe(struct switch_device *dev)\n+{\n+\tstruct mii_dev *bus = dev->bus;\n+\tu32 val;\n+\tu16 id;\n+\n+\tval = ar8216_mii_read(bus, AR8216_REG_CTRL);\n+\tif (val == ~0)\n+\t\treturn 1;\n+\n+\tid = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);\n+\n+\tswitch (id) {\n+\t\tcase 0x0101:\n+\t\t\treturn 0;\n+\t\tdefault:\n+\t\t\treturn 1;\n+\t}\n+}\n+\n+static void ar8216_setup(struct switch_device *dev)\n+{\n+\tstruct mii_dev *bus = dev->bus;\n+\n+\tar8216_mii_write(bus, 0x200, 0x200);\n+\tar8216_mii_write(bus, 0x300, 0x200);\n+\tar8216_mii_write(bus, 0x400, 0x200);\n+\tar8216_mii_write(bus, 0x500, 0x200);\n+\tar8216_mii_write(bus, 0x600, 0x7d);\n+\tar8216_mii_write(bus, 0x38, 0xc000050e);\n+\tar8216_mii_write(bus, 0x104, 0x4004);\n+\tar8216_mii_write(bus, 0x60, 0xffffffff);\n+\tar8216_mii_write(bus, 0x64, 0xaaaaaaaa);\n+\tar8216_mii_write(bus, 0x68, 0x55555555);\n+\tar8216_mii_write(bus, 0x6c, 0x0);\n+\tar8216_mii_write(bus, 0x70, 0x41af);\n+}\n+\n+static struct switch_driver ar8216_drv = {\n+\t.name = \"ar8216\",\n+};\n+\n+void switch_ar8216_init(void)\n+{\n+\t/* for archs with manual relocation */\n+\tar8216_drv.probe = ar8216_probe;\n+\tar8216_drv.setup = ar8216_setup;\n+\n+\tswitch_driver_register(&ar8216_drv);\n+}\n--- a/drivers/net/switch/switch.c\n+++ b/drivers/net/switch/switch.c\n@@ -23,6 +23,9 @@ void switch_init(void)\n #if defined(CONFIG_SWITCH_ADM6996I)\n \tswitch_adm6996i_init();\n #endif\n+#if defined(CONFIG_SWITCH_AR8216)\n+\tswitch_ar8216_init();\n+#endif\n \n \tboard_switch_init();\n }\n--- a/include/switch.h\n+++ b/include/switch.h\n@@ -99,6 +99,7 @@ static inline void switch_setup(struct s\n /* Init functions for supported Switch drivers */\n extern void switch_psb697x_init(void);\n extern void switch_adm6996i_init(void);\n+extern void switch_ar8216_init(void);\n \n #endif /* __SWITCH_H */\n \n"
  },
  {
    "path": "package/boot/uboot-lantiq/patches/0013-net-switchlib-add-driver-for-REALTEK-RTL8306.patch",
    "content": "From 42cb399df978a33539b95d668b3f973d927cb902 Mon Sep 17 00:00:00 2001\nFrom: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>\nDate: Mon, 17 Dec 2012 23:37:57 +0100\nSubject: net: switchlib: add driver for REALTEK RTL8306\n\nSigned-off-by: Oliver Muth <dr.o.muth@gmx.de>\nSigned-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>\n\n--- a/drivers/net/switch/Makefile\n+++ b/drivers/net/switch/Makefile\n@@ -13,6 +13,7 @@ COBJS-$(CONFIG_SWITCH_MULTI) += switch.o\n COBJS-$(CONFIG_SWITCH_PSB697X) += psb697x.o\n COBJS-$(CONFIG_SWITCH_ADM6996I) += adm6996i.o\n COBJS-$(CONFIG_SWITCH_AR8216) += ar8216.o\n+COBJS-$(CONFIG_SWITCH_RTL8306) += rtl8306.o\n \n COBJS\t:= $(COBJS-y)\n SRCS\t:= $(COBJS:.o=.c)\n--- /dev/null\n+++ b/drivers/net/switch/rtl8306.c\n@@ -0,0 +1,332 @@\n+/*\n+ * Based on OpenWrt linux driver\n+ *\n+ * Copyright (C) 2011-2012 Daniel Schwierzeck, daniel.schwierzeck@gmail.com\n+ * Copyright (C) 2009 Felix Fietkau <nbd@nbd.name>\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+#define DEBUG\n+#include <common.h>\n+#include <malloc.h>\n+#include <switch.h>\n+#include <miiphy.h>\n+\n+#define RTL8306_REG_PAGE\t\t16\n+#define RTL8306_REG_PAGE_LO\t\t(1 << 15)\n+#define RTL8306_REG_PAGE_HI\t\t(1 << 1) /* inverted */\n+#define RTL8306_CHIPID\t\t\t0x5988\n+\n+#define RTL8306_NUM_VLANS\t\t16\n+#define RTL8306_NUM_PORTS\t\t6\n+#define RTL8306_PORT_CPU\t\t5\n+#define RTL8306_NUM_PAGES\t\t4\n+#define RTL8306_NUM_REGS\t\t32\n+\n+enum {\n+\tRTL_TYPE_S,\n+\tRTL_TYPE_SD,\n+\tRTL_TYPE_SDM,\n+};\n+\n+struct rtl_reg {\n+\tint page;\n+\tint phy;\n+\tint reg;\n+\tint bits;\n+\tint shift;\n+\tint inverted;\n+};\n+\n+enum rtl_regidx {\n+\tRTL_REG_CHIPID,\n+\tRTL_REG_CHIPVER,\n+\tRTL_REG_CHIPTYPE,\n+\tRTL_REG_CPUPORT,\n+\n+\tRTL_REG_EN_CPUPORT,\n+\tRTL_REG_EN_TAG_OUT,\n+\tRTL_REG_EN_TAG_CLR,\n+\tRTL_REG_EN_TAG_IN,\n+\tRTL_REG_TRAP_CPU,\n+\tRTL_REG_TRUNK_PORTSEL,\n+\tRTL_REG_EN_TRUNK,\n+\tRTL_REG_RESET,\n+\tRTL_REG_PHY_RESET,\n+\tRTL_REG_CPU_LINKUP,\n+\n+\tRTL_REG_VLAN_ENABLE,\n+\tRTL_REG_VLAN_FILTER,\n+\tRTL_REG_VLAN_TAG_ONLY,\n+\tRTL_REG_VLAN_TAG_AWARE,\n+#define RTL_VLAN_ENUM(id) \\\n+\tRTL_REG_VLAN##id##_VID, \\\n+\tRTL_REG_VLAN##id##_PORTMASK\n+\tRTL_VLAN_ENUM(0),\n+\tRTL_VLAN_ENUM(1),\n+\tRTL_VLAN_ENUM(2),\n+\tRTL_VLAN_ENUM(3),\n+\tRTL_VLAN_ENUM(4),\n+\tRTL_VLAN_ENUM(5),\n+\tRTL_VLAN_ENUM(6),\n+\tRTL_VLAN_ENUM(7),\n+\tRTL_VLAN_ENUM(8),\n+\tRTL_VLAN_ENUM(9),\n+\tRTL_VLAN_ENUM(10),\n+\tRTL_VLAN_ENUM(11),\n+\tRTL_VLAN_ENUM(12),\n+\tRTL_VLAN_ENUM(13),\n+\tRTL_VLAN_ENUM(14),\n+\tRTL_VLAN_ENUM(15),\n+#define RTL_PORT_ENUM(id) \\\n+\tRTL_REG_PORT##id##_PVID, \\\n+\tRTL_REG_PORT##id##_NULL_VID_REPLACE, \\\n+\tRTL_REG_PORT##id##_NON_PVID_DISCARD, \\\n+\tRTL_REG_PORT##id##_VID_INSERT, \\\n+\tRTL_REG_PORT##id##_TAG_INSERT, \\\n+\tRTL_REG_PORT##id##_LINK, \\\n+\tRTL_REG_PORT##id##_SPEED, \\\n+\tRTL_REG_PORT##id##_NWAY, \\\n+\tRTL_REG_PORT##id##_NRESTART, \\\n+\tRTL_REG_PORT##id##_DUPLEX, \\\n+\tRTL_REG_PORT##id##_RXEN, \\\n+\tRTL_REG_PORT##id##_TXEN, \\\n+\tRTL_REG_PORT##id##_LRNEN\n+\tRTL_PORT_ENUM(0),\n+\tRTL_PORT_ENUM(1),\n+\tRTL_PORT_ENUM(2),\n+\tRTL_PORT_ENUM(3),\n+\tRTL_PORT_ENUM(4),\n+\tRTL_PORT_ENUM(5),\n+};\n+\n+static const struct rtl_reg rtl_regs[] = {\n+\t[RTL_REG_CHIPID]         = { 0, 4, 30, 16,  0, 0 },\n+\t[RTL_REG_CHIPVER]        = { 0, 4, 31,  8,  0, 0 },\n+\t[RTL_REG_CHIPTYPE]       = { 0, 4, 31,  2,  8, 0 },\n+\n+\t/* CPU port number */\n+\t[RTL_REG_CPUPORT]        = { 2, 4, 21,  3,  0, 0 },\n+\t/* Enable CPU port function */\n+\t[RTL_REG_EN_CPUPORT]     = { 3, 2, 21,  1, 15, 1 },\n+\t/* Enable CPU port tag insertion */\n+\t[RTL_REG_EN_TAG_OUT]     = { 3, 2, 21,  1, 12, 0 },\n+\t/* Enable CPU port tag removal */\n+\t[RTL_REG_EN_TAG_CLR]     = { 3, 2, 21,  1, 11, 0 },\n+\t/* Enable CPU port tag checking */\n+\t[RTL_REG_EN_TAG_IN]      = { 0, 4, 21,  1,  7, 0 },\n+\t[RTL_REG_EN_TRUNK]       = { 0, 0, 19,  1, 11, 1 },\n+\t[RTL_REG_TRUNK_PORTSEL]  = { 0, 0, 16,  1,  6, 1 },\n+\t[RTL_REG_RESET]          = { 0, 0, 16,  1, 12, 0 },\n+\t[RTL_REG_PHY_RESET]\t = { 0, 0,  0,  1, 15, 0 },\n+\t[RTL_REG_CPU_LINKUP]\t = { 0, 6, 22,  1, 15, 0 },\n+\t[RTL_REG_TRAP_CPU]       = { 3, 2, 22,  1,  6, 0 },\n+\n+\t[RTL_REG_VLAN_TAG_ONLY]  = { 0, 0, 16,  1,  8, 1 },\n+\t[RTL_REG_VLAN_FILTER]    = { 0, 0, 16,  1,  9, 1 },\n+\t[RTL_REG_VLAN_TAG_AWARE] = { 0, 0, 16,  1, 10, 1 },\n+\t[RTL_REG_VLAN_ENABLE]    = { 0, 0, 18,  1,  8, 1 },\n+\n+#define RTL_VLAN_REGS(id, phy, page, regofs) \\\n+\t[RTL_REG_VLAN##id##_VID] = { page, phy, 25 + regofs, 12, 0, 0 }, \\\n+\t[RTL_REG_VLAN##id##_PORTMASK] = { page, phy, 24 + regofs, 6, 0, 0 }\n+\tRTL_VLAN_REGS( 0, 0, 0, 0),\n+\tRTL_VLAN_REGS( 1, 1, 0, 0),\n+\tRTL_VLAN_REGS( 2, 2, 0, 0),\n+\tRTL_VLAN_REGS( 3, 3, 0, 0),\n+\tRTL_VLAN_REGS( 4, 4, 0, 0),\n+\tRTL_VLAN_REGS( 5, 0, 1, 2),\n+\tRTL_VLAN_REGS( 6, 1, 1, 2),\n+\tRTL_VLAN_REGS( 7, 2, 1, 2),\n+\tRTL_VLAN_REGS( 8, 3, 1, 2),\n+\tRTL_VLAN_REGS( 9, 4, 1, 2),\n+\tRTL_VLAN_REGS(10, 0, 1, 4),\n+\tRTL_VLAN_REGS(11, 1, 1, 4),\n+\tRTL_VLAN_REGS(12, 2, 1, 4),\n+\tRTL_VLAN_REGS(13, 3, 1, 4),\n+\tRTL_VLAN_REGS(14, 4, 1, 4),\n+\tRTL_VLAN_REGS(15, 0, 1, 6),\n+\n+#define REG_PORT_SETTING(port, phy) \\\n+\t[RTL_REG_PORT##port##_SPEED] = { 0, phy, 0, 1, 13, 0 }, \\\n+\t[RTL_REG_PORT##port##_NWAY] = { 0, phy, 0, 1, 12, 0 }, \\\n+\t[RTL_REG_PORT##port##_NRESTART] = { 0, phy, 0, 1, 9, 0 }, \\\n+\t[RTL_REG_PORT##port##_DUPLEX] = { 0, phy, 0, 1, 8, 0 }, \\\n+\t[RTL_REG_PORT##port##_TXEN] = { 0, phy, 24, 1, 11, 0 }, \\\n+\t[RTL_REG_PORT##port##_RXEN] = { 0, phy, 24, 1, 10, 0 }, \\\n+\t[RTL_REG_PORT##port##_LRNEN] = { 0, phy, 24, 1, 9, 0 }, \\\n+\t[RTL_REG_PORT##port##_LINK] = { 0, phy, 1, 1, 2, 0 }, \\\n+\t[RTL_REG_PORT##port##_NULL_VID_REPLACE] = { 0, phy, 22, 1, 12, 0 }, \\\n+\t[RTL_REG_PORT##port##_NON_PVID_DISCARD] = { 0, phy, 22, 1, 11, 0 }, \\\n+\t[RTL_REG_PORT##port##_VID_INSERT] = { 0, phy, 22, 2, 9, 0 }, \\\n+\t[RTL_REG_PORT##port##_TAG_INSERT] = { 0, phy, 22, 2, 0, 0 }\n+\n+\tREG_PORT_SETTING(0, 0),\n+\tREG_PORT_SETTING(1, 1),\n+\tREG_PORT_SETTING(2, 2),\n+\tREG_PORT_SETTING(3, 3),\n+\tREG_PORT_SETTING(4, 4),\n+\tREG_PORT_SETTING(5, 6),\n+\n+#define REG_PORT_PVID(phy, page, regofs) \\\n+\t{ page, phy, 24 + regofs, 4, 12, 0 }\n+\t[RTL_REG_PORT0_PVID] = REG_PORT_PVID(0, 0, 0),\n+\t[RTL_REG_PORT1_PVID] = REG_PORT_PVID(1, 0, 0),\n+\t[RTL_REG_PORT2_PVID] = REG_PORT_PVID(2, 0, 0),\n+\t[RTL_REG_PORT3_PVID] = REG_PORT_PVID(3, 0, 0),\n+\t[RTL_REG_PORT4_PVID] = REG_PORT_PVID(4, 0, 0),\n+\t[RTL_REG_PORT5_PVID] = REG_PORT_PVID(0, 1, 2),\n+};\n+\n+static void rtl_set_page(struct mii_dev *bus, unsigned int page)\n+{\n+\tu16 pgsel;\n+\n+\tBUG_ON(page > RTL8306_NUM_PAGES);\n+\n+\tpgsel = bus->read(bus, 0, MDIO_DEVAD_NONE, RTL8306_REG_PAGE);\n+\tpgsel &= ~(RTL8306_REG_PAGE_LO | RTL8306_REG_PAGE_HI);\n+\n+\tif (page & (1 << 0))\n+\t\tpgsel |= RTL8306_REG_PAGE_LO;\n+\n+\tif (!(page & (1 << 1))) /* bit is inverted */\n+\t\tpgsel |= RTL8306_REG_PAGE_HI;\n+\n+\tbus->write(bus, 0, MDIO_DEVAD_NONE, RTL8306_REG_PAGE, pgsel);\n+\n+}\n+\n+static __maybe_unused int rtl_w16(struct mii_dev *bus, unsigned int page, unsigned int phy,\n+\t\t\tunsigned int reg, u16 val)\n+{\n+\trtl_set_page(bus, page);\n+\n+\tbus->write(bus, phy, MDIO_DEVAD_NONE, reg, val);\n+\tbus->read(bus, phy, MDIO_DEVAD_NONE, reg); /* flush */\n+\n+\treturn 0;\n+}\n+\n+static int rtl_r16(struct mii_dev *bus, unsigned int page, unsigned int phy,\n+\t\t\tunsigned int reg)\n+{\n+\trtl_set_page(bus, page);\n+\n+\treturn bus->read(bus, phy, MDIO_DEVAD_NONE, reg);\n+}\n+\n+static u16 rtl_rmw(struct mii_dev *bus, unsigned int page, unsigned int phy,\n+\t\t\tunsigned int reg, u16 mask, u16 val)\n+{\n+\tu16 r;\n+\n+\trtl_set_page(bus, page);\n+\n+\tr = bus->read(bus, phy, MDIO_DEVAD_NONE, reg);\n+\tr &= ~mask;\n+\tr |= val;\n+\tbus->write(bus, phy, MDIO_DEVAD_NONE, reg, r);\n+\n+\treturn bus->read(bus, phy, MDIO_DEVAD_NONE, reg); /* flush */\n+}\n+\n+static int rtl_get(struct mii_dev *bus, enum rtl_regidx s)\n+{\n+\tconst struct rtl_reg *r = &rtl_regs[s];\n+\tu16 val;\n+\n+\tBUG_ON(s >= ARRAY_SIZE(rtl_regs));\n+\n+\tif (r->bits == 0) /* unimplemented */\n+\t\treturn 0;\n+\n+\tval = rtl_r16(bus, r->page, r->phy, r->reg);\n+\n+\tif (r->shift > 0)\n+\t\tval >>= r->shift;\n+\n+\tif (r->inverted)\n+\t\tval = ~val;\n+\n+\tval &= (1 << r->bits) - 1;\n+\n+\treturn val;\n+}\n+\n+static __maybe_unused int rtl_set(struct mii_dev *bus, enum rtl_regidx s, unsigned int val)\n+{\n+\tconst struct rtl_reg *r = &rtl_regs[s];\n+\tu16 mask = 0xffff;\n+\n+\tBUG_ON(s >= ARRAY_SIZE(rtl_regs));\n+\n+\tif (r->bits == 0) /* unimplemented */\n+\t\treturn 0;\n+\n+\tif (r->shift > 0)\n+\t\tval <<= r->shift;\n+\n+\tif (r->inverted)\n+\t\tval = ~val;\n+\n+\tif (r->bits != 16) {\n+\t\tmask = (1 << r->bits) - 1;\n+\t\tmask <<= r->shift;\n+\t}\n+\n+\tval &= mask;\n+\n+\treturn rtl_rmw(bus, r->page, r->phy, r->reg, mask, val);\n+}\n+\n+static int rtl8306_probe(struct switch_device *dev)\n+{\n+\tstruct mii_dev *bus = dev->bus;\n+\tunsigned int chipid, chipver, chiptype;\n+\n+\tchipid = rtl_get(bus, RTL_REG_CHIPID);\n+\tchipver = rtl_get(bus, RTL_REG_CHIPVER);\n+\tchiptype = rtl_get(bus, RTL_REG_CHIPTYPE);\n+\n+\tdebug(\"%s: chipid %x, chipver %x, chiptype %x\\n\",\n+\t\t__func__, chipid, chipver, chiptype);\n+\n+\tif (chipid == RTL8306_CHIPID)\n+\t\treturn 0;\n+\n+\treturn 1;\n+}\n+\n+static void rtl8306_setup(struct switch_device *dev)\n+{\n+\tstruct mii_dev *bus = dev->bus;\n+\n+\t/* initialize cpu port settings */\n+\trtl_set(bus, RTL_REG_CPUPORT, dev->cpu_port);\n+\trtl_set(bus, RTL_REG_EN_CPUPORT, 1);\n+\n+\t/* enable phy 5 link status */\n+\trtl_set(bus, RTL_REG_CPU_LINKUP, 1);\n+//\trtl_set(bus, RTL_REG_PORT5_TXEN, 1);\n+//\trtl_set(bus, RTL_REG_PORT5_RXEN, 1);\n+//\trtl_set(bus, RTL_REG_PORT5_LRNEN, 1);\n+#ifdef DEBUG\n+ debug(\"%s: CPU link up: %i\\n\",\n+\t\t__func__, rtl_get(bus, RTL_REG_PORT5_LINK));\n+#endif\n+\n+}\n+\n+static struct switch_driver rtl8306_drv = {\n+\t.name = \"rtl8306\",\n+};\n+\n+void switch_rtl8306_init(void)\n+{\n+\t/* For archs with manual relocation */\n+\trtl8306_drv.probe = rtl8306_probe;\n+\trtl8306_drv.setup = rtl8306_setup;\n+\n+\tswitch_driver_register(&rtl8306_drv);\n+}\n--- a/drivers/net/switch/switch.c\n+++ b/drivers/net/switch/switch.c\n@@ -26,6 +26,9 @@ void switch_init(void)\n #if defined(CONFIG_SWITCH_AR8216)\n \tswitch_ar8216_init();\n #endif\n+#if defined(CONFIG_SWITCH_RTL8306)\n+\tswitch_rtl8306_init();\n+#endif\n \n \tboard_switch_init();\n }\n--- a/include/switch.h\n+++ b/include/switch.h\n@@ -100,6 +100,7 @@ static inline void switch_setup(struct s\n extern void switch_psb697x_init(void);\n extern void switch_adm6996i_init(void);\n extern void switch_ar8216_init(void);\n+extern void switch_rtl8306_init(void);\n \n #endif /* __SWITCH_H */\n \n"
  },
  {
    "path": "package/boot/uboot-lantiq/patches/0014-MIPS-add-support-for-Lantiq-XWAY-SoCs.patch",
    "content": "From 11553b0de8992ded6240d034bd49f561d17bea53 Mon Sep 17 00:00:00 2001\nFrom: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>\nDate: Thu, 13 Jun 2013 01:18:02 +0200\nSubject: MIPS: add support for Lantiq XWAY SoCs\n\nSigned-off-by: Luka Perkov <luka@openwrt.org>\nSigned-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>\n\n--- a/.gitignore\n+++ b/.gitignore\n@@ -49,6 +49,13 @@\n /u-boot.sb\n /u-boot.bd\n /u-boot.geany\n+/u-boot.bin.lzma\n+/u-boot.bin.lzo\n+/u-boot.ltq.lzma.norspl\n+/u-boot.ltq.lzo.norspl\n+/u-boot.ltq.norspl\n+/u-boot.lzma.img\n+/u-boot.lzo.img\n \n #\n # Generated files\n--- a/Makefile\n+++ b/Makefile\n@@ -435,6 +435,12 @@ $(obj)u-boot.bin:\t$(obj)u-boot\n \t\t$(OBJCOPY) ${OBJCFLAGS} -O binary $< $@\n \t\t$(BOARD_SIZE_CHECK)\n \n+$(obj)u-boot.bin.lzma:\t$(obj)u-boot.bin\n+\t\tcat $< | lzma -9 -f - > $@\n+\n+$(obj)u-boot.bin.lzo:\t$(obj)u-boot.bin\n+\t\tcat $< | lzop -9 -f - > $@\n+\n $(obj)u-boot.ldr:\t$(obj)u-boot\n \t\t$(CREATE_LDR_ENV)\n \t\t$(LDR) -T $(CONFIG_BFIN_CPU) -c $@ $< $(LDR_FLAGS)\n@@ -454,13 +460,23 @@ ifndef CONFIG_SYS_UBOOT_START\n CONFIG_SYS_UBOOT_START := 0\n endif\n \n-$(obj)u-boot.img:\t$(obj)u-boot.bin\n-\t\t$(obj)tools/mkimage -A $(ARCH) -T firmware -C none \\\n+define GEN_UBOOT_IMAGE\n+\t\t$(obj)tools/mkimage -A $(ARCH) -T firmware -C $(1) \\\n \t\t-O u-boot -a $(CONFIG_SYS_TEXT_BASE) \\\n \t\t-e $(CONFIG_SYS_UBOOT_START) \\\n \t\t-n $(shell sed -n -e 's/.*U_BOOT_VERSION//p' $(VERSION_FILE) | \\\n \t\t\tsed -e 's/\"[\t ]*$$/ for $(BOARD) board\"/') \\\n \t\t-d $< $@\n+endef\n+\n+$(obj)u-boot.img:\t$(obj)u-boot.bin\n+\t\t$(call GEN_UBOOT_IMAGE,none)\n+\n+$(obj)u-boot.lzma.img:\t$(obj)u-boot.bin.lzma\n+\t\t$(call GEN_UBOOT_IMAGE,lzma)\n+\n+$(obj)u-boot.lzo.img:\t$(obj)u-boot.bin.lzo\n+\t\t$(call GEN_UBOOT_IMAGE,lzo)\n \n $(obj)u-boot.imx: $(obj)u-boot.bin depend\n \t\t$(MAKE) -C $(SRCTREE)/arch/arm/imx-common $(OBJTREE)/u-boot.imx\n@@ -571,6 +587,27 @@ $(obj)u-boot-img-spl-at-end.bin: $(obj)s\n \t\t\tconv=notrunc 2>/dev/null\n \t\tcat $(obj)u-boot-pad.img $(obj)spl/u-boot-spl.bin > $@\n \n+$(obj)u-boot.ltq.sfspl:\t$(obj)u-boot.img $(obj)spl/u-boot-spl.bin\n+\t\t$(obj)tools/ltq-boot-image -t sfspl -e $(CONFIG_SPL_TEXT_BASE) \\\n+\t\t\t-s $(obj)spl/u-boot-spl.bin -u $< -o $@\n+\n+$(obj)u-boot.ltq.lzo.sfspl: $(obj)u-boot.lzo.img $(obj)spl/u-boot-spl.bin\n+\t\t$(obj)tools/ltq-boot-image -t sfspl -e $(CONFIG_SPL_TEXT_BASE) \\\n+\t\t\t-s $(obj)spl/u-boot-spl.bin -u $< -o $@\n+\n+$(obj)u-boot.ltq.lzma.sfspl: $(obj)u-boot.lzma.img $(obj)spl/u-boot-spl.bin\n+\t\t$(obj)tools/ltq-boot-image -t sfspl -e $(CONFIG_SPL_TEXT_BASE) \\\n+\t\t\t-s $(obj)spl/u-boot-spl.bin -u $< -o $@\n+\n+$(obj)u-boot.ltq.norspl: $(obj)u-boot.img $(obj)spl/u-boot-spl.bin\n+\tcat $(obj)spl/u-boot-spl.bin $< > $@\n+\n+$(obj)u-boot.ltq.lzo.norspl: $(obj)u-boot.lzo.img $(obj)spl/u-boot-spl.bin\n+\tcat $(obj)spl/u-boot-spl.bin $< > $@\n+\n+$(obj)u-boot.ltq.lzma.norspl: $(obj)u-boot.lzma.img $(obj)spl/u-boot-spl.bin\n+\tcat $(obj)spl/u-boot-spl.bin $< > $@\n+\n ifeq ($(CONFIG_SANDBOX),y)\n GEN_UBOOT = \\\n \t\tcd $(LNDIR) && $(CC) $(SYMS) -T $(obj)u-boot.lds \\\n--- a/README\n+++ b/README\n@@ -468,6 +468,11 @@ The following options need to be configu\n \t\t\tCONF_CM_CACHABLE_CUW\n \t\t\tCONF_CM_CACHABLE_ACCELERATED\n \n+\t\tCONFIG_SYS_MIPS_CACHE_EXT_INIT\n+\n+\t\tEnable this to use extended cache initialization for recent\n+\t\tMIPS CPU cores.\n+\n \t\tCONFIG_SYS_XWAY_EBU_BOOTCFG\n \n \t\tSpecial option for Lantiq XWAY SoCs for booting from NOR flash.\n--- a/arch/mips/config.mk\n+++ b/arch/mips/config.mk\n@@ -45,9 +45,13 @@ PLATFORM_CPPFLAGS += -DCONFIG_MIPS -D__M\n # On the other hand, we want PIC in the U-Boot code to relocate it from ROM\n # to RAM. $28 is always used as gp.\n #\n-PLATFORM_CPPFLAGS\t\t+= -G 0 -mabicalls -fpic $(ENDIANNESS)\n+PF_ABICALLS\t\t\t?= -mabicalls\n+PF_PIC\t\t\t\t?= -fpic\n+PF_PIE\t\t\t\t?= -pie\n+\n+PLATFORM_CPPFLAGS\t\t+= -G 0 $(PF_ABICALLS) $(PF_PIC) $(ENDIANNESS)\n PLATFORM_CPPFLAGS\t\t+= -msoft-float\n PLATFORM_LDFLAGS\t\t+= -G 0 -static -n -nostdlib $(ENDIANNESS)\n PLATFORM_RELFLAGS\t\t+= -ffunction-sections -fdata-sections\n-LDFLAGS_FINAL\t\t\t+= --gc-sections -pie\n+LDFLAGS_FINAL\t\t\t+= --gc-sections $(PF_PIE)\n OBJCFLAGS\t\t\t+= --remove-section=.dynsym\n--- a/arch/mips/cpu/mips32/cache.S\n+++ b/arch/mips/cpu/mips32/cache.S\n@@ -29,7 +29,11 @@\n  */\n #define MIPS_MAX_CACHE_SIZE\t0x10000\n \n+#ifdef CONFIG_SYS_MIPS_CACHE_EXT_INIT\n+#define INDEX_BASE\t0x9fc00000\n+#else\n #define INDEX_BASE\tCKSEG0\n+#endif\n \n \t.macro\tcache_op op addr\n \t.set\tpush\n@@ -65,7 +69,11 @@\n  */\n LEAF(mips_init_icache)\n \tblez\t\ta1, 9f\n+#ifdef CONFIG_SYS_MIPS_CACHE_EXT_INIT\n+\tmtc0\t\tzero, CP0_ITAGLO\n+#else\n \tmtc0\t\tzero, CP0_TAGLO\n+#endif\n \t/* clear tag to invalidate */\n \tPTR_LI\t\tt0, INDEX_BASE\n \tPTR_ADDU\tt1, t0, a1\n@@ -90,7 +98,11 @@ LEAF(mips_init_icache)\n  */\n LEAF(mips_init_dcache)\n \tblez\t\ta1, 9f\n+#ifdef CONFIG_SYS_MIPS_CACHE_EXT_INIT\n+\tmtc0\t\tzero, CP0_DTAGLO\n+#else\n \tmtc0\t\tzero, CP0_TAGLO\n+#endif\n \t/* clear all tags */\n \tPTR_LI\t\tt0, INDEX_BASE\n \tPTR_ADDU\tt1, t0, a1\n--- /dev/null\n+++ b/arch/mips/cpu/mips32/danube/Makefile\n@@ -0,0 +1,31 @@\n+#\n+# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de\n+#\n+# SPDX-License-Identifier:\tGPL-2.0+\n+#\n+\n+include $(TOPDIR)/config.mk\n+\n+LIB\t= $(obj)lib$(SOC).o\n+\n+COBJS-y\t+= cgu.o chipid.o ebu.o mem.o pmu.o rcu.o\n+SOBJS-y\t+= cgu_init.o mem_init.o\n+\n+COBJS\t:= $(COBJS-y)\n+SOBJS\t:= $(SOBJS-y)\n+SRCS\t:= $(SOBJS:.o=.S) $(COBJS:.o=.c)\n+OBJS\t:= $(addprefix $(obj),$(SOBJS) $(COBJS))\n+\n+all:\t$(LIB)\n+\n+$(LIB):\t$(obj).depend $(OBJS)\n+\t$(call cmd_link_o_target, $(OBJS))\n+\n+#########################################################################\n+\n+# defines $(obj).depend target\n+include $(SRCTREE)/rules.mk\n+\n+sinclude $(obj).depend\n+\n+#########################################################################\n--- /dev/null\n+++ b/arch/mips/cpu/mips32/danube/cgu.c\n@@ -0,0 +1,117 @@\n+/*\n+ * Copyright (C) 2007-2010 Lantiq Deutschland GmbH\n+ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#include <common.h>\n+#include <asm/arch/soc.h>\n+#include <asm/lantiq/clk.h>\n+#include <asm/lantiq/io.h>\n+\n+#define LTQ_CGU_SYS_DDR_MASK\t\t0x0003\n+#define LTQ_CGU_SYS_DDR_SHIFT\t\t0\n+#define LTQ_CGU_SYS_CPU0_MASK\t\t0x000C\n+#define LTQ_CGU_SYS_CPU0_SHIFT\t\t2\n+#define LTQ_CGU_SYS_FPI_MASK\t\t0x0040\n+#define LTQ_CGU_SYS_FPI_SHIFT\t\t6\n+\n+struct ltq_cgu_regs {\n+\tu32\trsvd0;\n+\tu32\tpll0_cfg;\t/* PLL0 config */\n+\tu32\tpll1_cfg;\t/* PLL1 config */\n+\tu32\tpll2_cfg;\t/* PLL2 config */\n+\tu32\tsys;\t\t/* System clock */\n+\tu32\tupdate;\t\t/* CGU update control */\n+\tu32\tif_clk;\t\t/* Interface clock */\n+\tu32\tosc_con;\t/* Update OSC Control */\n+\tu32\tsmd;\t\t/* SDRAM Memory Control */\n+\tu32\trsvd1[3];\n+\tu32\tpcm_cr;\t\t/* PCM control */\n+\tu32\tpci_cr;\t\t/* PCI clock control */\n+};\n+\n+static struct ltq_cgu_regs *ltq_cgu_regs =\n+\t(struct ltq_cgu_regs *) CKSEG1ADDR(LTQ_CGU_BASE);\n+\n+static inline u32 ltq_cgu_sys_readl(u32 mask, u32 shift)\n+{\n+\treturn (ltq_readl(&ltq_cgu_regs->sys) & mask) >> shift;\n+}\n+\n+unsigned long ltq_get_io_region_clock(void)\n+{\n+\tu32 ddr_sel;\n+\tunsigned long clk;\n+\n+\tddr_sel = ltq_cgu_sys_readl(LTQ_CGU_SYS_DDR_MASK,\n+\t\t\t\t\tLTQ_CGU_SYS_DDR_SHIFT);\n+\n+\tswitch (ddr_sel) {\n+\tcase 0:\n+\t\tclk = CLOCK_166_MHZ;\n+\t\tbreak;\n+\tcase 1:\n+\t\tclk = CLOCK_133_MHZ;\n+\t\tbreak;\n+\tcase 2:\n+\t\tclk = CLOCK_111_MHZ;\n+\t\tbreak;\n+\tcase 3:\n+\t\tclk = CLOCK_83_MHZ;\n+\t\tbreak;\n+\tdefault:\n+\t\tclk = 0;\n+\t\tbreak;\n+\t}\n+\n+\treturn clk;\n+}\n+\n+unsigned long ltq_get_cpu_clock(void)\n+{\n+\tu32 cpu0_sel;\n+\tunsigned long clk;\n+\n+\tcpu0_sel = ltq_cgu_sys_readl(LTQ_CGU_SYS_CPU0_MASK,\n+\t\t\t\t\tLTQ_CGU_SYS_CPU0_SHIFT);\n+\n+\tswitch (cpu0_sel) {\n+\t\t/* Same as PLL0 output (333,33 MHz) */\n+\tcase 0:\n+\t\tclk = CLOCK_333_MHZ;\n+\t\tbreak;\n+\t\t/* 1/1 fixed ratio to DDR clock */\n+\tcase 1:\n+\t\tclk = ltq_get_io_region_clock();\n+\t\tbreak;\n+\t\t/* 1/2 fixed ratio to DDR clock */\n+\tcase 2:\n+\t\tclk = ltq_get_io_region_clock() << 1;\n+\t\tbreak;\n+\tdefault:\n+\t\tclk = 0;\n+\t\tbreak;\n+\t}\n+\n+\treturn clk;\n+}\n+\n+unsigned long ltq_get_bus_clock(void)\n+{\n+\tu32 fpi_sel;\n+\tunsigned long clk;\n+\n+\tfpi_sel = ltq_cgu_sys_readl(LTQ_CGU_SYS_FPI_MASK,\n+\t\t\t\t\tLTQ_CGU_SYS_FPI_SHIFT);\n+\n+\tif (fpi_sel)\n+\t\t/* Half the DDR clock */\n+\t\tclk = ltq_get_io_region_clock() >> 1;\n+\telse\n+\t\t/* Same as DDR clock */\n+\t\tclk = ltq_get_io_region_clock();\n+\n+\treturn clk;\n+}\n--- /dev/null\n+++ b/arch/mips/cpu/mips32/danube/cgu_init.S\n@@ -0,0 +1,142 @@\n+/*\n+ * Copyright (C) 2007-2010 Lantiq Deutschland GmbH\n+ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#include <config.h>\n+#include <asm/asm.h>\n+#include <asm/regdef.h>\n+#include <asm/addrspace.h>\n+#include <asm/arch/soc.h>\n+\n+/* RCU module register */\n+#define LTQ_RCU_RST_REQ\t\t\t0x0010\n+#define LTQ_RCU_RST_STAT\t\t0x0014\n+#define LTQ_RCU_RST_REQ_VALUE\t\t0x40000008\n+#define LTQ_RCU_RST_STAT_XTAL_F\t0x20000\n+\n+/* CGU module register */\n+#define LTQ_CGU_PLL0_CFG\t\t0x0004\t/* PLL0 config */\n+#define LTQ_CGU_PLL1_CFG\t\t0x0008\t/* PLL1 config */\n+#define LTQ_CGU_PLL2_CFG\t\t0x000C\t/* PLL2 config */\n+#define LTQ_CGU_SYS\t\t\t0x0010\t/* System clock */\n+\n+/* Valid SYS.CPU0/1 values */\n+#define LTQ_CGU_SYS_CPU0_SHIFT\t\t2\n+#define LTQ_CGU_SYS_CPU1_SHIFT\t\t4\n+#define LTQ_CGU_SYS_CPU_PLL0\t\t0x0\n+#define LTQ_CGU_SYS_CPU_DDR_EQUAL\t0x1\n+#define LTQ_CGU_SYS_CPU_DDR_TWICE\t0x2\n+\n+/* Valid SYS.DDR values */\n+#define LTQ_CGU_SYS_DDR_SHIFT\t\t0\n+#define LTQ_CGU_SYS_DDR_167_MHZ\t0x0\n+#define LTQ_CGU_SYS_DDR_133_MHZ\t0x1\n+#define LTQ_CGU_SYS_DDR_111_MHZ\t0x2\n+#define LTQ_CGU_SYS_DDR_83_MHZ\t\t0x3\n+\n+/* Valid SYS.FPI values */\n+#define LTQ_CGU_SYS_FPI_SHIFT\t\t6\n+#define LTQ_CGU_SYS_FPI_DDR_EQUAL\t0x0\n+#define LTQ_CGU_SYS_FPI_DDR_HALF\t0x1\n+\n+/* Valid SYS.PPE values */\n+#define LTQ_CGU_SYS_PPE_SHIFT\t\t7\n+#define LTQ_CGU_SYS_PPE_266_MHZ\t0x0\n+#define LTQ_CGU_SYS_PPE_240_MHZ\t0x1\n+#define LTQ_CGU_SYS_PPE_222_MHZ\t0x2\n+#define LTQ_CGU_SYS_PPE_133_MHZ\t0x3\n+\n+#if (CONFIG_SYS_CLOCK_MODE == LTQ_CLK_CPU_333_DDR_167)\n+#define LTQ_CGU_SYS_CPU_CONFIG\t\tLTQ_CGU_SYS_CPU_DDR_TWICE\n+#define LTQ_CGU_SYS_DDR_CONFIG\t\tLTQ_CGU_SYS_DDR_167_MHZ\n+#define LTQ_CGU_SYS_FPI_CONFIG\t\tLTQ_CGU_SYS_FPI_DDR_HALF\n+#define LTQ_CGU_SYS_PPE_CONFIG\t\tLTQ_CGU_SYS_PPE_266_MHZ\n+#elif (CONFIG_SYS_CLOCK_MODE == LTQ_CLK_CPU_111_DDR_111)\n+#define LTQ_CGU_SYS_CPU_CONFIG\t\tLTQ_CGU_SYS_CPU_DDR_EQUAL\n+#define LTQ_CGU_SYS_DDR_CONFIG\t\tLTQ_CGU_SYS_DDR_111_MHZ\n+#define LTQ_CGU_SYS_FPI_CONFIG\t\tLTQ_CGU_SYS_FPI_DDR_HALF\n+#define LTQ_CGU_SYS_PPE_CONFIG\t\tLTQ_CGU_SYS_PPE_133_MHZ\n+#else\n+#error \"Invalid system clock configuration!\"\n+#endif\n+\n+/* Build register values */\n+#define LTQ_CGU_SYS_VALUE\t((LTQ_CGU_SYS_PPE_CONFIG << \\\n+\t\t\t\t\tLTQ_CGU_SYS_PPE_SHIFT) | \\\n+\t\t\t\t(LTQ_CGU_SYS_FPI_CONFIG << \\\n+\t\t\t\t\tLTQ_CGU_SYS_FPI_SHIFT) | \\\n+\t\t\t\t(LTQ_CGU_SYS_CPU_CONFIG << \\\n+\t\t\t\t\tLTQ_CGU_SYS_CPU1_SHIFT) | \\\n+\t\t\t\t(LTQ_CGU_SYS_CPU_CONFIG << \\\n+\t\t\t\t\tLTQ_CGU_SYS_CPU0_SHIFT) | \\\n+\t\t\t\tLTQ_CGU_SYS_DDR_CONFIG)\n+\n+/* Reset values for PLL registers for usage with 35.328 MHz crystal */\n+#define PLL0_35MHZ_CONFIG\t0x9D861059\n+#define PLL1_35MHZ_CONFIG\t0x1A260CD9\n+#define PLL2_35MHZ_CONFIG\t0x8000f1e5\n+\n+/* Reset values for PLL registers for usage with 36 MHz crystal */\n+#define PLL0_36MHZ_CONFIG\t0x1000125D\n+#define PLL1_36MHZ_CONFIG\t0x1B1E0C99\n+#define PLL2_36MHZ_CONFIG\t0x8002f2a1\n+\n+LEAF(ltq_cgu_init)\n+\t/* Load current CGU register value */\n+\tli\tt0, (LTQ_CGU_BASE | KSEG1)\n+\tlw\tt1, LTQ_CGU_SYS(t0)\n+\n+\t/* Load target CGU register values */\n+\tli\tt3, LTQ_CGU_SYS_VALUE\n+\n+\t/* Only update registers if values differ */\n+\tbeq\tt1, t3, finished\n+\n+\t/*\n+\t * Check whether the XTAL_F bit in RST_STAT register is set or not.\n+\t * This bit is latched in via pin strapping. If bit is set then\n+\t * clock source is a 36 MHz crystal. Otherwise a 35.328 MHz crystal.\n+\t */\n+\t li\tt1, (LTQ_RCU_BASE | KSEG1)\n+\t lw\tt2, LTQ_RCU_RST_STAT(t1)\n+\t and\tt2, t2, LTQ_RCU_RST_STAT_XTAL_F\n+\t beq\tt2, LTQ_RCU_RST_STAT_XTAL_F, boot_36mhz\n+\n+boot_35mhz:\n+\t/* Configure PLL for 35.328 MHz */\n+\tli\tt2, PLL0_35MHZ_CONFIG\n+\tsw\tt2, LTQ_CGU_PLL0_CFG(t0)\n+\tli\tt2, PLL1_35MHZ_CONFIG\n+\tsw\tt2, LTQ_CGU_PLL1_CFG(t0)\n+\tli\tt2, PLL2_35MHZ_CONFIG\n+\tsw\tt2, LTQ_CGU_PLL2_CFG(t0)\n+\n+\tb\tdo_reset\n+\n+boot_36mhz:\n+\t/* Configure PLL for 36 MHz */\n+\tli\tt2, PLL0_36MHZ_CONFIG\n+\tsw\tt2, LTQ_CGU_PLL0_CFG(t0)\n+\tli\tt2, PLL1_36MHZ_CONFIG\n+\tsw\tt2, LTQ_CGU_PLL1_CFG(t0)\n+\tli\tt2, PLL2_36MHZ_CONFIG\n+\tsw\tt2, LTQ_CGU_PLL2_CFG(t0)\n+\n+do_reset:\n+\t/* Store new clock config */\n+\tsw\tt3, LTQ_CGU_SYS(t0)\n+\n+\t/* Perform software reset to activate new clock config */\n+\tli\tt2, LTQ_RCU_RST_REQ_VALUE\n+\tsw\tt2, LTQ_RCU_RST_REQ(t1)\n+\n+wait_reset:\n+\tb\twait_reset\n+\n+finished:\n+\tjr\tra\n+\n+\tEND(ltq_cgu_init)\n--- /dev/null\n+++ b/arch/mips/cpu/mips32/danube/chipid.c\n@@ -0,0 +1,59 @@\n+/*\n+ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#include <common.h>\n+#include <asm/lantiq/io.h>\n+#include <asm/lantiq/chipid.h>\n+#include <asm/arch/soc.h>\n+\n+#define LTQ_CHIPID_VERSION_SHIFT\t28\n+#define LTQ_CHIPID_VERSION_MASK\t\t(0xF << LTQ_CHIPID_VERSION_SHIFT)\n+#define LTQ_CHIPID_PNUM_SHIFT\t\t12\n+#define LTQ_CHIPID_PNUM_MASK\t\t(0xFFFF << LTQ_CHIPID_PNUM_SHIFT)\n+\n+struct ltq_chipid_regs {\n+\tu32\tmanid;\t\t/* Manufacturer identification */\n+\tu32\tchipid;\t\t/* Chip identification */\n+};\n+\n+static struct ltq_chipid_regs *ltq_chipid_regs =\n+\t(struct ltq_chipid_regs *) CKSEG1ADDR(LTQ_CHIPID_BASE);\n+\n+unsigned int ltq_chip_version_get(void)\n+{\n+\tu32 chipid;\n+\n+\tchipid = ltq_readl(&ltq_chipid_regs->chipid);\n+\n+\treturn (chipid & LTQ_CHIPID_VERSION_MASK) >> LTQ_CHIPID_VERSION_SHIFT;\n+}\n+\n+unsigned int ltq_chip_partnum_get(void)\n+{\n+\tu32 chipid;\n+\n+\tchipid = ltq_readl(&ltq_chipid_regs->chipid);\n+\n+\treturn (chipid & LTQ_CHIPID_PNUM_MASK) >> LTQ_CHIPID_PNUM_SHIFT;\n+}\n+\n+const char *ltq_chip_partnum_str(void)\n+{\n+\tenum ltq_chip_partnum partnum = ltq_chip_partnum_get();\n+\n+\tswitch (partnum) {\n+\tcase LTQ_SOC_DANUBE:\n+\t\treturn \"Danube\";\n+\tcase LTQ_SOC_DANUBE_S:\n+\t\treturn \"Danube-S\";\n+\tcase LTQ_SOC_TWINPASS:\n+\t\treturn \"Twinpass\";\n+\tdefault:\n+\t\tprintf(\"Unknown partnum: %x\\n\", partnum);\n+\t}\n+\n+\treturn \"\";\n+}\n--- /dev/null\n+++ b/arch/mips/cpu/mips32/danube/config.mk\n@@ -0,0 +1,25 @@\n+#\n+# Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com\n+#\n+# SPDX-License-Identifier:\tGPL-2.0+\n+#\n+\n+PF_CPPFLAGS_DANUBE := $(call cc-option,-mtune=24kec,)\n+PLATFORM_CPPFLAGS += $(PF_CPPFLAGS_DANUBE)\n+\n+ifdef CONFIG_SPL_BUILD\n+PF_ABICALLS\t\t:= -mno-abicalls\n+PF_PIC\t\t\t:= -fno-pic\n+PF_PIE\t\t\t:=\n+USE_PRIVATE_LIBGCC\t:= yes\n+endif\n+\n+LIBS-y += $(CPUDIR)/lantiq-common/liblantiq-common.o\n+\n+ifndef CONFIG_SPL_BUILD\n+ifdef CONFIG_SYS_BOOT_NORSPL\n+ALL-y += $(obj)u-boot.ltq.norspl\n+ALL-$(CONFIG_SPL_LZO_SUPPORT) += $(obj)u-boot.ltq.lzo.norspl\n+ALL-$(CONFIG_SPL_LZMA_SUPPORT) += $(obj)u-boot.ltq.lzma.norspl\n+endif\n+endif\n--- /dev/null\n+++ b/arch/mips/cpu/mips32/danube/ebu.c\n@@ -0,0 +1,105 @@\n+/*\n+ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#include <common.h>\n+#include <asm/arch/soc.h>\n+#include <asm/lantiq/io.h>\n+\n+#define EBU_ADDRSEL_MASK(mask)\t\t((mask & 0xf) << 4)\n+#define EBU_ADDRSEL_REGEN\t\t(1 << 0)\n+\n+#define EBU_CON_WRDIS\t\t\t(1 << 31)\n+#define EBU_CON_AGEN_DEMUX\t\t(0x0 << 24)\n+#define EBU_CON_AGEN_MUX\t\t(0x2 << 24)\n+#define EBU_CON_SETUP\t\t\t(1 << 22)\n+#define EBU_CON_WAIT_DIS\t\t(0x0 << 20)\n+#define EBU_CON_WAIT_ASYNC\t\t(0x1 << 20)\n+#define EBU_CON_WAIT_SYNC\t\t(0x2 << 20)\n+#define EBU_CON_WINV\t\t\t(1 << 19)\n+#define EBU_CON_PW_8BIT\t\t\t(0x0 << 16)\n+#define EBU_CON_PW_16BIT\t\t(0x1 << 16)\n+#define EBU_CON_ALEC(cycles)\t\t((cycles & 0x3) << 14)\n+#define EBU_CON_BCGEN_CS\t\t(0x0 << 12)\n+#define EBU_CON_BCGEN_INTEL\t\t(0x1 << 12)\n+#define EBU_CON_BCGEN_MOTOROLA\t\t(0x2 << 12)\n+#define EBU_CON_WAITWRC(cycles)\t\t((cycles & 0x7) << 8)\n+#define EBU_CON_WAITRDC(cycles)\t\t((cycles & 0x3) << 6)\n+#define EBU_CON_HOLDC(cycles)\t\t((cycles & 0x3) << 4)\n+#define EBU_CON_RECOVC(cycles)\t\t((cycles & 0x3) << 2)\n+#define EBU_CON_CMULT_1\t\t\t0x0\n+#define EBU_CON_CMULT_4\t\t\t0x1\n+#define EBU_CON_CMULT_8\t\t\t0x2\n+#define EBU_CON_CMULT_16\t\t0x3\n+\n+#if defined(CONFIG_LTQ_SUPPORT_NOR_FLASH)\n+#define ebu_region0_enable\t\t1\n+#else\n+#define ebu_region0_enable\t\t0\n+#endif\n+\n+#if defined(CONFIG_LTQ_SUPPORT_NAND_FLASH)\n+#define ebu_region1_enable\t\t1\n+#else\n+#define ebu_region1_enable\t\t0\n+#endif\n+\n+struct ltq_ebu_regs {\n+\tu32\tclc;\n+\tu32\trsvd0[3];\n+\tu32\tcon;\n+\tu32\trsvd1[3];\n+\tu32\taddr_sel_0;\n+\tu32\taddr_sel_1;\n+\tu32\trsvd2[14];\n+\tu32\tcon_0;\n+\tu32\tcon_1;\n+};\n+\n+static struct ltq_ebu_regs *ltq_ebu_regs =\n+\t(struct ltq_ebu_regs *) CKSEG1ADDR(LTQ_EBU_BASE);\n+\n+void ltq_ebu_init(void)\n+{\n+\tif (ebu_region0_enable) {\n+\t\t/*\n+\t\t * Map EBU region 0 to range 0x10000000-0x13ffffff and enable\n+\t\t * region control. This supports up to 32 MiB NOR flash in\n+\t\t * bank 0.\n+\t\t */\n+\t\tltq_writel(&ltq_ebu_regs->addr_sel_0, LTQ_EBU_REGION0_BASE |\n+\t\t\tEBU_ADDRSEL_MASK(1) | EBU_ADDRSEL_REGEN);\n+\n+\t\tltq_writel(&ltq_ebu_regs->con_0, EBU_CON_AGEN_DEMUX |\n+\t\t\tEBU_CON_WAIT_DIS | EBU_CON_PW_16BIT |\n+\t\t\tEBU_CON_ALEC(3) | EBU_CON_BCGEN_INTEL |\n+\t\t\tEBU_CON_WAITWRC(7) | EBU_CON_WAITRDC(3) |\n+\t\t\tEBU_CON_HOLDC(3) | EBU_CON_RECOVC(3) |\n+\t\t\tEBU_CON_CMULT_16);\n+\t} else\n+\t\tltq_clrbits(&ltq_ebu_regs->addr_sel_0, EBU_ADDRSEL_REGEN);\n+\n+\tif (ebu_region1_enable) {\n+\t\t/*\n+\t\t * Map EBU region 1 to range 0x14000000-0x13ffffff and enable\n+\t\t * region control. This supports NAND flash in bank 1.\n+\t\t */\n+\t\tltq_writel(&ltq_ebu_regs->addr_sel_1, LTQ_EBU_REGION1_BASE |\n+\t\t\tEBU_ADDRSEL_MASK(3) | EBU_ADDRSEL_REGEN);\n+\n+\t\tltq_writel(&ltq_ebu_regs->con_1, EBU_CON_AGEN_DEMUX |\n+\t\t\tEBU_CON_SETUP | EBU_CON_WAIT_DIS | EBU_CON_PW_8BIT |\n+\t\t\tEBU_CON_ALEC(3) | EBU_CON_BCGEN_INTEL |\n+\t\t\tEBU_CON_WAITWRC(2) | EBU_CON_WAITRDC(2) |\n+\t\t\tEBU_CON_HOLDC(1) | EBU_CON_RECOVC(1) |\n+\t\t\tEBU_CON_CMULT_4);\n+\t} else\n+\t\tltq_clrbits(&ltq_ebu_regs->addr_sel_1, EBU_ADDRSEL_REGEN);\n+}\n+\n+void *flash_swap_addr(unsigned long addr)\n+{\n+\treturn (void *)(addr ^ 2);\n+}\n--- /dev/null\n+++ b/arch/mips/cpu/mips32/danube/mem.c\n@@ -0,0 +1,30 @@\n+/*\n+ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#include <common.h>\n+#include <asm/arch/soc.h>\n+#include <asm/lantiq/io.h>\n+\n+static void *ltq_mc_ddr_base = (void *) CKSEG1ADDR(LTQ_MC_DDR_BASE);\n+\n+static inline u32 ltq_mc_dc_read(u32 index)\n+{\n+\treturn ltq_readl(ltq_mc_ddr_base + LTQ_MC_DDR_DC_OFFSET(index));\n+}\n+\n+phys_size_t initdram(int board_type)\n+{\n+\tu32 col, row, dc04, dc19, dc20;\n+\n+\tdc04 = ltq_mc_dc_read(4);\n+\tdc19 = ltq_mc_dc_read(19);\n+\tdc20 = ltq_mc_dc_read(20);\n+\n+\trow = (dc04 & 0xF) - ((dc19 & 0x700) >> 8);\n+\tcol = ((dc04 & 0xF00) >> 8) - (dc20 & 0x7);\n+\n+\treturn (1 << (row + col)) * 4 * 2;\n+}\n--- /dev/null\n+++ b/arch/mips/cpu/mips32/danube/mem_init.S\n@@ -0,0 +1,114 @@\n+/*\n+ * Copyright (C) 2007-2010 Lantiq Deutschland GmbH\n+ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#include <config.h>\n+#include <asm/asm.h>\n+#include <asm/regdef.h>\n+#include <asm/addrspace.h>\n+#include <asm/arch/soc.h>\n+\n+/* Must be configured in BOARDDIR */\n+#include <ddr_settings.h>\n+\n+#define LTQ_MC_GEN_ERRCAUSE\t\t0x0010\n+#define LTQ_MC_GEN_ERRADDR\t\t0x0020\n+#define LTQ_MC_GEN_CON\t\t\t0x0060\n+#define LTQ_MC_GEN_STAT\t\t\t0x0070\n+#define LTQ_MC_GEN_CON_SRAM_DDR_ENABLE\t0x5\n+#define LTQ_MC_GEN_STAT_DLCK_PWRON\t0xC\n+\n+#define LTQ_MC_DDR_DC03_MC_START\t0x100\n+\n+\t/* Store given value in MC DDR CCRx register */\n+\t.macro dc_sw num, val\n+\tli\tt2, \\val\n+\tsw\tt2, LTQ_MC_DDR_DC_OFFSET(\\num)(t1)\n+\t.endm\n+\n+LEAF(ltq_mem_init)\n+\t/* Load MC General and MC DDR module base */\n+\tli\tt0, (LTQ_MC_GEN_BASE | KSEG1)\n+\tli\tt1, (LTQ_MC_DDR_BASE | KSEG1)\n+\n+\t/* Clear access error log registers */\n+\tsw\tzero, LTQ_MC_GEN_ERRCAUSE(t0)\n+\tsw\tzero, LTQ_MC_GEN_ERRADDR(t0)\n+\n+\t/* Enable DDR and SRAM module in memory controller */\n+\tli\tt2, LTQ_MC_GEN_CON_SRAM_DDR_ENABLE\n+\tsw\tt2, LTQ_MC_GEN_CON(t0)\n+\n+\t/* Clear start bit of DDR memory controller */\n+\tsw\tzero, LTQ_MC_DDR_DC_OFFSET(3)(t1)\n+\n+\t/* Init memory controller registers with values ddr_settings.h */\n+\tdc_sw\t0, MC_DC00_VALUE\n+\tdc_sw\t1, MC_DC01_VALUE\n+\tdc_sw\t2, MC_DC02_VALUE\n+\tdc_sw\t4, MC_DC04_VALUE\n+\tdc_sw\t5, MC_DC05_VALUE\n+\tdc_sw\t6, MC_DC06_VALUE\n+\tdc_sw\t7, MC_DC07_VALUE\n+\tdc_sw\t8, MC_DC08_VALUE\n+\tdc_sw\t9, MC_DC09_VALUE\n+\n+\tdc_sw\t10, MC_DC10_VALUE\n+\tdc_sw\t11, MC_DC11_VALUE\n+\tdc_sw\t12, MC_DC12_VALUE\n+\tdc_sw\t13, MC_DC13_VALUE\n+\tdc_sw\t14, MC_DC14_VALUE\n+\tdc_sw\t15, MC_DC15_VALUE\n+\tdc_sw\t16, MC_DC16_VALUE\n+\tdc_sw\t17, MC_DC17_VALUE\n+\tdc_sw\t18, MC_DC18_VALUE\n+\tdc_sw\t19, MC_DC19_VALUE\n+\n+\tdc_sw\t20, MC_DC20_VALUE\n+\tdc_sw\t21, MC_DC21_VALUE\n+\tdc_sw\t22, MC_DC22_VALUE\n+\tdc_sw\t23, MC_DC23_VALUE\n+\tdc_sw\t24, MC_DC24_VALUE\n+\tdc_sw\t25, MC_DC25_VALUE\n+\tdc_sw\t26, MC_DC26_VALUE\n+\tdc_sw\t27, MC_DC27_VALUE\n+\tdc_sw\t28, MC_DC28_VALUE\n+\tdc_sw\t29, MC_DC29_VALUE\n+\n+\tdc_sw\t30, MC_DC30_VALUE\n+\tdc_sw\t31, MC_DC31_VALUE\n+\tdc_sw\t32, MC_DC32_VALUE\n+\tdc_sw\t33, MC_DC33_VALUE\n+\tdc_sw\t34, MC_DC34_VALUE\n+\tdc_sw\t35, MC_DC35_VALUE\n+\tdc_sw\t36, MC_DC36_VALUE\n+\tdc_sw\t37, MC_DC37_VALUE\n+\tdc_sw\t38, MC_DC38_VALUE\n+\tdc_sw\t39, MC_DC39_VALUE\n+\n+\tdc_sw\t40, MC_DC40_VALUE\n+\tdc_sw\t41, MC_DC41_VALUE\n+\tdc_sw\t42, MC_DC42_VALUE\n+\tdc_sw\t43, MC_DC43_VALUE\n+\tdc_sw\t44, MC_DC44_VALUE\n+\tdc_sw\t45, MC_DC45_VALUE\n+\tdc_sw\t46, MC_DC46_VALUE\n+\n+\t/* Set start bit of DDR memory controller */\n+\tli\tt2, LTQ_MC_DDR_DC03_MC_START\n+\tsw\tt2, LTQ_MC_DDR_DC_OFFSET(3)(t1)\n+\n+\t/* Wait until DLL has locked and core is ready for data transfers */\n+wait_ready:\n+\tlw\tt2, LTQ_MC_GEN_STAT(t0)\n+\tli\tt3, LTQ_MC_GEN_STAT_DLCK_PWRON\n+\tand\tt2, t3\n+\tbne\tt2, t3, wait_ready\n+\n+finished:\n+\tjr\tra\n+\n+\tEND(ltq_mem_init)\n--- /dev/null\n+++ b/arch/mips/cpu/mips32/danube/pmu.c\n@@ -0,0 +1,117 @@\n+/*\n+ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#include <common.h>\n+#include <asm/lantiq/io.h>\n+#include <asm/lantiq/pm.h>\n+#include <asm/arch/soc.h>\n+\n+#define LTQ_PMU_PWDCR_RESERVED\t\t0xFD0C001C\n+\n+#define LTQ_PMU_PWDCR_TDM\t\t(1 << 25)\n+#define LTQ_PMU_PWDCR_PPE_ENET0\t\t(1 << 23)\n+#define LTQ_PMU_PWDCR_PPE_ENET1\t\t(1 << 22)\n+#define LTQ_PMU_PWDCR_PPE_TC\t\t(1 << 21)\n+#define LTQ_PMU_PWDCR_DEU\t\t(1 << 20)\n+#define LTQ_PMU_PWDCR_UART1\t\t(1 << 17)\n+#define LTQ_PMU_PWDCR_SDIO\t\t(1 << 16)\n+#define LTQ_PMU_PWDCR_AHB\t\t(1 << 15)\n+#define LTQ_PMU_PWDCR_FPI0\t\t(1 << 14)\n+#define LTQ_PMU_PWDCR_PPE\t\t(1 << 13)\n+#define LTQ_PMU_PWDCR_GPTC\t\t(1 << 12)\n+#define LTQ_PMU_PWDCR_LEDC\t\t(1 << 11)\n+#define LTQ_PMU_PWDCR_EBU\t\t(1 << 10)\n+#define LTQ_PMU_PWDCR_DSL\t\t(1 << 9)\n+#define LTQ_PMU_PWDCR_SPI\t\t(1 << 8)\n+#define LTQ_PMU_PWDCR_UART0\t\t(1 << 7)\n+#define LTQ_PMU_PWDCR_USB\t\t(1 << 6)\n+#define LTQ_PMU_PWDCR_DMA\t\t(1 << 5)\n+#define LTQ_PMU_PWDCR_FPI1\t\t(1 << 1)\n+#define LTQ_PMU_PWDCR_USB_PHY\t\t(1 << 0)\n+\n+struct ltq_pmu_regs {\n+\tu32\trsvd0[7];\n+\tu32\tpwdcr;\n+\tu32\tsr;\n+\tu32\tpwdcr1;\n+\tu32\tsr1;\n+};\n+\n+static struct ltq_pmu_regs *ltq_pmu_regs =\n+\t(struct ltq_pmu_regs *) CKSEG1ADDR(LTQ_PMU_BASE);\n+\n+u32 ltq_pm_map(enum ltq_pm_modules module)\n+{\n+\tu32 val;\n+\n+\tswitch (module) {\n+\tcase LTQ_PM_CORE:\n+\t\tval = LTQ_PMU_PWDCR_UART1 | LTQ_PMU_PWDCR_FPI0 |\n+\t\t\tLTQ_PMU_PWDCR_LEDC | LTQ_PMU_PWDCR_EBU;\n+\t\tbreak;\n+\tcase LTQ_PM_DMA:\n+\t\tval = LTQ_PMU_PWDCR_DMA;\n+\t\tbreak;\n+\tcase LTQ_PM_ETH:\n+\t\tval = LTQ_PMU_PWDCR_PPE_ENET0 | LTQ_PMU_PWDCR_PPE_TC |\n+\t\t\tLTQ_PMU_PWDCR_PPE;\n+\t\tbreak;\n+\tcase LTQ_PM_SPI:\n+\t\tval = LTQ_PMU_PWDCR_SPI;\n+\t\tbreak;\n+\tdefault:\n+\t\tval = 0;\n+\t\tbreak;\n+\t}\n+\n+\treturn val;\n+}\n+\n+int ltq_pm_enable(enum ltq_pm_modules module)\n+{\n+\tconst unsigned long timeout = 1000;\n+\tunsigned long timebase;\n+\tu32 sr, val;\n+\n+\tval = ltq_pm_map(module);\n+\tif (unlikely(!val))\n+\t\treturn 1;\n+\n+\tltq_clrbits(&ltq_pmu_regs->pwdcr, val);\n+\n+\ttimebase = get_timer(0);\n+\n+\tdo {\n+\t\tsr = ltq_readl(&ltq_pmu_regs->sr);\n+\t\tif (~sr & val)\n+\t\t\treturn 0;\n+\t} while (get_timer(timebase) < timeout);\n+\n+\treturn 1;\n+}\n+\n+int ltq_pm_disable(enum ltq_pm_modules module)\n+{\n+\tu32 val;\n+\n+\tval = ltq_pm_map(module);\n+\tif (unlikely(!val))\n+\t\treturn 1;\n+\n+\tltq_setbits(&ltq_pmu_regs->pwdcr, val);\n+\n+\treturn 0;\n+}\n+\n+void ltq_pmu_init(void)\n+{\n+\tu32 set, clr;\n+\n+\tclr = ltq_pm_map(LTQ_PM_CORE);\n+\tset = ~(LTQ_PMU_PWDCR_RESERVED | clr);\n+\n+\tltq_clrsetbits(&ltq_pmu_regs->pwdcr, clr, set);\n+}\n--- /dev/null\n+++ b/arch/mips/cpu/mips32/danube/rcu.c\n@@ -0,0 +1,125 @@\n+/*\n+ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#include <common.h>\n+#include <asm/lantiq/io.h>\n+#include <asm/lantiq/reset.h>\n+#include <asm/lantiq/cpu.h>\n+#include <asm/arch/soc.h>\n+\n+#define LTQ_RCU_RD_SRST\t\t(1 << 30)\t/* Global SW Reset */\n+#define LTQ_RCU_RD_MC\t\t(1 << 14)\t/* Memory Controller */\n+#define LTQ_RCU_RD_PCI\t\t(1 << 13)\t/* PCI core */\n+#define LTQ_RCU_RD_DFE_AFE\t(1 << 12)\t/* Voice DFE/AFE */\n+#define LTQ_RCU_RD_DSL_AFE\t(1 << 11)\t/* DSL AFE */\n+#define LTQ_RCU_RD_SDIO\t\t(1 << 10)\t/* SDIO core */\n+#define LTQ_RCU_RD_DMA\t\t(1 << 9)\t/* DMA core */\n+#define LTQ_RCU_RD_PPE\t\t(1 << 8)\t/* PPE core */\n+#define LTQ_RCU_RD_ARC_DFE\t(1 << 7)\t/* ARC/DFE core */\n+#define LTQ_RCU_RD_AHB\t\t(1 << 6)\t/* AHB bus */\n+#define LTQ_RCU_RD_ENET_MAC1\t(1 << 5)\t/* Ethernet MAC1 */\n+#define LTQ_RCU_RD_USB\t\t(1 << 4)\t/* USB and Phy core */\n+#define LTQ_RCU_RD_CPU1\t\t(1 << 3)\t/* CPU1 subsystem */\n+#define LTQ_RCU_RD_FPI\t\t(1 << 2)\t/* FPI bus */\n+#define LTQ_RCU_RD_CPU0\t\t(1 << 1)\t/* CPU0 subsystem */\n+#define LTQ_RCU_RD_HRST\t\t(1 << 0)\t/* HW reset via HRST pin */\n+\n+#define LTQ_RCU_STAT_BOOT_SHIFT\t\t18\n+#define LTQ_RCU_STAT_BOOT_MASK\t\t(0x7 << LTQ_RCU_STAT_BOOT_SHIFT)\n+\n+struct ltq_rcu_regs {\n+\tu32\trsvd0[4];\n+\tu32\treq;\t\t/* Reset request */\n+\tu32\tstat;\t\t/* Reset status */\n+\tu32\tusb_cfg;\t/* USB configure */\n+\tu32\trsvd1[2];\n+\tu32\tpci_rdy;\t/* PCI boot ready */\n+};\n+\n+static struct ltq_rcu_regs *ltq_rcu_regs =\n+\t(struct ltq_rcu_regs *) CKSEG1ADDR(LTQ_RCU_BASE);\n+\n+u32 ltq_reset_map(enum ltq_reset_modules module)\n+{\n+\tu32 val;\n+\n+\tswitch (module) {\n+\tcase LTQ_RESET_CORE:\n+\tcase LTQ_RESET_SOFT:\n+\t\tval = LTQ_RCU_RD_SRST | LTQ_RCU_RD_CPU1;\n+\t\tbreak;\n+\tcase LTQ_RESET_DMA:\n+\t\tval = LTQ_RCU_RD_DMA;\n+\t\tbreak;\n+\tcase LTQ_RESET_ETH:\n+\t\tval = LTQ_RCU_RD_PPE;\n+\t\tbreak;\n+\tcase LTQ_RESET_HARD:\n+\t\tval = LTQ_RCU_RD_HRST;\n+\t\tbreak;\n+\tdefault:\n+\t\tval = 0;\n+\t\tbreak;\n+\t}\n+\n+\treturn val;\n+}\n+\n+int ltq_reset_activate(enum ltq_reset_modules module)\n+{\n+\tu32 val;\n+\n+\tval = ltq_reset_map(module);\n+\tif (unlikely(!val))\n+\t\treturn 1;\n+\n+\tltq_setbits(&ltq_rcu_regs->req, val);\n+\n+\treturn 0;\n+}\n+\n+int ltq_reset_deactivate(enum ltq_reset_modules module)\n+{\n+\tu32 val;\n+\n+\tval = ltq_reset_map(module);\n+\tif (unlikely(!val))\n+\t\treturn 1;\n+\n+\tltq_clrbits(&ltq_rcu_regs->req, val);\n+\n+\treturn 0;\n+}\n+\n+enum ltq_boot_select ltq_boot_select(void)\n+{\n+\tu32 stat;\n+\tunsigned int bootstrap;\n+\n+\tstat = ltq_readl(&ltq_rcu_regs->stat);\n+\tbootstrap = (stat & LTQ_RCU_STAT_BOOT_MASK) >> LTQ_RCU_STAT_BOOT_SHIFT;\n+\n+\tswitch (bootstrap) {\n+\tcase 0:\n+\t\treturn BOOT_NOR_NO_BOOTROM;\n+\tcase 1:\n+\t\treturn BOOT_NOR;\n+\tcase 2:\n+\t\treturn BOOT_MII0;\n+\tcase 3:\n+\t\treturn BOOT_PCI;\n+\tcase 4:\n+\t\treturn BOOT_UART;\n+\tcase 5:\n+\t\treturn BOOT_SPI;\n+\tcase 6:\n+\t\treturn BOOT_NAND;\n+\tcase 7:\n+\t\treturn BOOT_RMII0;\n+\tdefault:\n+\t\treturn BOOT_UNKNOWN;\n+\t}\n+}\n--- /dev/null\n+++ b/arch/mips/cpu/mips32/lantiq-common/Makefile\n@@ -0,0 +1,34 @@\n+#\n+# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de\n+#\n+# SPDX-License-Identifier:\tGPL-2.0+\n+#\n+\n+include $(TOPDIR)/config.mk\n+\n+LIB\t= $(obj)liblantiq-common.o\n+\n+START\t= start.o\n+COBJS-y\t= cpu.o pmu.o\n+COBJS-$(CONFIG_SPL_BUILD) += spl.o\n+SOBJS-y\t= lowlevel_init.o\n+\n+COBJS\t:= $(COBJS-y)\n+SOBJS\t:= $(SOBJS-y)\n+SRCS\t:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)\n+OBJS\t:= $(addprefix $(obj),$(SOBJS) $(COBJS))\n+START\t:= $(addprefix $(obj),$(START))\n+\n+all:\t$(LIB)\n+\n+$(LIB):\t$(obj).depend $(OBJS)\n+\t$(call cmd_link_o_target, $(OBJS))\n+\n+#########################################################################\n+\n+# defines $(obj).depend target\n+include $(SRCTREE)/rules.mk\n+\n+sinclude $(obj).depend\n+\n+#########################################################################\n--- /dev/null\n+++ b/arch/mips/cpu/mips32/lantiq-common/cpu.c\n@@ -0,0 +1,59 @@\n+/*\n+ * Copyright (C) 2012-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#include <common.h>\n+#include <asm/lantiq/chipid.h>\n+#include <asm/lantiq/clk.h>\n+#include <asm/lantiq/reset.h>\n+#include <asm/lantiq/cpu.h>\n+\n+static const char ltq_bootsel_strings[][16] = {\n+\t\"NOR\",\n+\t\"NOR w/o BootROM\",\n+\t\"UART\",\n+\t\"UART w/o EEPROM\",\n+\t\"SPI\",\n+\t\"NAND\",\n+\t\"PCI\",\n+\t\"MII0\",\n+\t\"RMII0\",\n+\t\"RGMII1\",\n+\t\"unknown\",\n+};\n+\n+const char *ltq_boot_select_str(void)\n+{\tenum ltq_boot_select bootsel = ltq_boot_select();\n+\n+\tif (bootsel > BOOT_UNKNOWN)\n+\t\tbootsel = BOOT_UNKNOWN;\n+\n+\treturn ltq_bootsel_strings[bootsel];\n+}\n+\n+void ltq_chip_print_info(void)\n+{\n+\tchar buf[32];\n+\n+\tprintf(\"SoC:   Lantiq %s v1.%u\\n\", ltq_chip_partnum_str(),\n+\t\tltq_chip_version_get());\n+\tprintf(\"CPU:   %s MHz\\n\", strmhz(buf, ltq_get_cpu_clock()));\n+\tprintf(\"IO:    %s MHz\\n\", strmhz(buf, ltq_get_io_region_clock()));\n+\tprintf(\"BUS:   %s MHz\\n\", strmhz(buf, ltq_get_bus_clock()));\n+\tprintf(\"BOOT:  %s\\n\", ltq_boot_select_str());\n+}\n+\n+int arch_cpu_init(void)\n+{\n+\tltq_pmu_init();\n+\tltq_ebu_init();\n+\n+\treturn 0;\n+}\n+\n+void _machine_restart(void)\n+{\n+\tltq_reset_activate(LTQ_RESET_CORE);\n+}\n--- /dev/null\n+++ b/arch/mips/cpu/mips32/lantiq-common/lowlevel_init.S\n@@ -0,0 +1,20 @@\n+/*\n+ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#include <asm/asm.h>\n+#include <asm/regdef.h>\n+\n+NESTED(lowlevel_init, 0, ra)\n+\tmove\tt8, ra\n+\n+\tla\tt7, ltq_cgu_init\n+\tjalr\tt7\n+\n+\tla\tt7, ltq_mem_init\n+\tjalr\tt7\n+\n+\tjr\tt8\n+\tEND(lowlevel_init)\n--- /dev/null\n+++ b/arch/mips/cpu/mips32/lantiq-common/pmu.c\n@@ -0,0 +1,9 @@\n+/*\n+ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#include <common.h>\n+#include <asm/lantiq/pm.h>\n+\n--- /dev/null\n+++ b/arch/mips/cpu/mips32/lantiq-common/spl.c\n@@ -0,0 +1,403 @@\n+/*\n+ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#include <common.h>\n+#include <image.h>\n+#include <version.h>\n+#include <spi_flash.h>\n+#include <linux/compiler.h>\n+#include <lzma/LzmaDec.h>\n+#include <linux/lzo.h>\n+#include <asm/mipsregs.h>\n+\n+#if defined(CONFIG_LTQ_SPL_CONSOLE)\n+#define spl_has_console\t\t1\n+\n+#if defined(CONFIG_LTQ_SPL_DEBUG)\n+#define spl_has_debug\t\t1\n+#else\n+#define spl_has_debug\t\t0\n+#endif\n+\n+#else\n+#define spl_has_console\t\t0\n+#define spl_has_debug\t\t0\n+#endif\n+\n+#define spl_debug(fmt, args...)\t\t\t\\\n+\tdo {\t\t\t\t\t\\\n+\t\tif (spl_has_debug)\t\t\\\n+\t\t\tprintf(fmt, ##args);\t\\\n+\t} while (0)\n+\n+#define spl_puts(msg)\t\t\t\t\\\n+\tdo {\t\t\t\t\t\\\n+\t\tif (spl_has_console)\t\t\\\n+\t\t\tputs(msg);\t\t\\\n+\t} while (0)\n+\n+#if defined(CONFIG_LTQ_SUPPORT_SPL_SPI_FLASH) && defined(CONFIG_SYS_BOOT_SFSPL)\n+#define spl_boot_spi_flash\t1\n+#else\n+#define spl_boot_spi_flash\t0\n+#ifndef CONFIG_SPL_SPI_BUS\n+#define CONFIG_SPL_SPI_BUS\t0\n+#endif\n+#ifndef CONFIG_SPL_SPI_CS\n+#define CONFIG_SPL_SPI_CS\t0\n+#endif\n+#ifndef CONFIG_SPL_SPI_MAX_HZ\n+#define CONFIG_SPL_SPI_MAX_HZ\t0\n+#endif\n+#ifndef CONFIG_SPL_SPI_MODE\n+#define CONFIG_SPL_SPI_MODE\t0\n+#endif\n+#endif\n+\n+#if defined(CONFIG_LTQ_SUPPORT_SPL_NOR_FLASH) && defined(CONFIG_SYS_BOOT_NORSPL)\n+#define spl_boot_nor_flash\t1\n+#else\n+#define spl_boot_nor_flash\t0\n+#endif\n+\n+#define spl_sync()\t__asm__ __volatile__(\"sync\");\n+\n+struct spl_image {\n+\tulong data_addr;\n+\tulong entry_addr;\n+\tulong data_size;\n+\tulong entry_size;\n+\tulong data_crc;\n+\tu8 comp;\n+};\n+\n+DECLARE_GLOBAL_DATA_PTR;\n+\n+/* Emulated malloc area needed for LZMA allocator in BSS */\n+static u8 *spl_mem_ptr __maybe_unused;\n+static size_t spl_mem_size __maybe_unused;\n+\n+static int spl_is_comp_lzma(const struct spl_image *spl)\n+{\n+#if defined(CONFIG_LTQ_SPL_COMP_LZMA)\n+\treturn spl->comp == IH_COMP_LZMA;\n+#else\n+\treturn 0;\n+#endif\n+}\n+\n+static int spl_is_comp_lzo(const struct spl_image *spl)\n+{\n+#if defined(CONFIG_LTQ_SPL_COMP_LZO)\n+\treturn spl->comp == IH_COMP_LZO;\n+#else\n+\treturn 0;\n+#endif\n+}\n+\n+static int spl_is_compressed(const struct spl_image *spl)\n+{\n+\tif (spl_is_comp_lzma(spl))\n+\t\treturn 1;\n+\n+\tif (spl_is_comp_lzo(spl))\n+\t\treturn 1;\n+\n+\treturn 0;\n+}\n+\n+static void spl_console_init(void)\n+{\n+\tif (!spl_has_console)\n+\t\treturn;\n+\n+\tgd->flags |= GD_FLG_RELOC;\n+\tgd->baudrate = CONFIG_BAUDRATE;\n+\n+\tserial_init();\n+\n+\tgd->have_console = 1;\n+\n+\tspl_puts(\"\\nU-Boot SPL \" PLAIN_VERSION \" (\" U_BOOT_DATE \" - \" \\\n+\t\tU_BOOT_TIME \")\\n\");\n+}\n+\n+static int spl_parse_image(const image_header_t *hdr, struct spl_image *spl)\n+{\n+\tspl_puts(\"SPL: checking U-Boot image\\n\");\n+\n+\tif (!image_check_magic(hdr)) {\n+\t\tspl_puts(\"SPL: invalid magic\\n\");\n+\t\treturn -1;\n+\t}\n+\n+        if (!image_check_hcrc(hdr)) {\n+\t\tspl_puts(\"SPL: invalid header CRC\\n\");\n+\t\treturn -1;\n+\t}\n+\n+\tspl->data_addr += image_get_header_size();\n+\tspl->entry_addr = image_get_load(hdr);\n+\tspl->data_size = image_get_data_size(hdr);\n+\tspl->data_crc = image_get_dcrc(hdr);\n+\tspl->comp = image_get_comp(hdr);\n+\n+\tspl_debug(\"SPL: data %08lx, size %lu, entry %08lx, comp %u\\n\",\n+\t\tspl->data_addr, spl->data_size, spl->entry_addr, spl->comp);\n+\n+\treturn 0;\n+}\n+\n+static int spl_check_data(const struct spl_image *spl, ulong loadaddr)\n+{\n+\tulong dcrc = crc32(0, (unsigned char *)loadaddr, spl->data_size);\n+\n+\tif (dcrc != spl->data_crc) {\n+\t\tspl_puts(\"SPL: invalid data CRC\\n\");\n+\t\treturn 0;\n+\t}\n+\n+\treturn 1;\n+}\n+\n+static void *spl_lzma_alloc(void *p, size_t size)\n+{\n+\tu8 *ret;\n+\n+\tif (size > spl_mem_size)\n+\t\treturn NULL;\n+\n+\tret = spl_mem_ptr;\n+\tspl_mem_ptr += size;\n+\tspl_mem_size -= size;\n+\n+\treturn ret;\n+}\n+\n+static void spl_lzma_free(void *p, void *addr)\n+{\n+}\n+\n+static int spl_copy_image(struct spl_image *spl)\n+{\n+\tspl_puts(\"SPL: copying U-Boot to RAM\\n\");\n+\n+\tmemcpy((void *) spl->entry_addr, (const void *) spl->data_addr,\n+\t\tspl->data_size);\n+\n+\tspl->entry_size = spl->data_size;\n+\n+\treturn 0;\n+}\n+\n+static int spl_uncompress_lzma(struct spl_image *spl, unsigned long loadaddr)\n+{\n+\tSRes res;\n+\tconst Byte *prop = (const Byte *) loadaddr;\n+\tconst Byte *src = (const Byte *) loadaddr + LZMA_PROPS_SIZE +\n+\t\t\t\t\t\t\tsizeof(uint64_t);\n+\tByte *dest = (Byte *) spl->entry_addr;\n+\tSizeT dest_len = 0xFFFFFFFF;\n+\tSizeT src_len = spl->data_size - LZMA_PROPS_SIZE;\n+\tELzmaStatus status = 0;\n+\tISzAlloc alloc;\n+\n+\tspl_puts(\"SPL: decompressing U-Boot with LZMA\\n\");\n+\n+\talloc.Alloc = spl_lzma_alloc;\n+\talloc.Free = spl_lzma_free;\n+\tspl_mem_ptr = (u8 *) CONFIG_SPL_MALLOC_BASE;\n+\tspl_mem_size = CONFIG_SPL_MALLOC_MAX_SIZE;\n+\n+\tres = LzmaDecode(dest, &dest_len, src, &src_len, prop, LZMA_PROPS_SIZE,\n+\t\tLZMA_FINISH_ANY, &status, &alloc);\n+\tif (res != SZ_OK)\n+\t\treturn 1;\n+\n+\tspl->entry_size = dest_len;\n+\n+\treturn 0;\n+}\n+\n+static int spl_uncompress_lzo(struct spl_image *spl, unsigned long loadaddr)\n+{\n+\tsize_t len = CONFIG_SYS_LOAD_SIZE;\n+\tint ret;\n+\n+\tspl_puts(\"SPL: decompressing U-Boot with LZO\\n\");\n+\n+\tret = lzop_decompress(\n+\t\t(const unsigned char*) loadaddr, spl->data_size,\n+\t\t(unsigned char *) spl->entry_addr, &len);\n+\n+\tspl->entry_size = len;\n+\n+\treturn ret;\n+}\n+\n+static int spl_uncompress(struct spl_image *spl, unsigned long loadaddr)\n+{\n+\tint ret;\n+\n+\tif (spl_is_comp_lzma(spl))\n+\t\tret = spl_uncompress_lzma(spl, loadaddr);\n+\telse if (spl_is_comp_lzo(spl))\n+\t\tret = spl_uncompress_lzo(spl, loadaddr);\n+\telse\n+\t\tret = 1;\n+\n+\treturn ret;\n+}\n+\n+static int spl_load_spi_flash(struct spl_image *spl)\n+{\n+\tstruct spi_flash sf = { 0 };\n+\timage_header_t hdr;\n+\tint ret;\n+\tunsigned long loadaddr;\n+\n+\t/*\n+\t * Image format:\n+\t *\n+\t * - 12 byte non-volatile bootstrap header\n+\t * - SPL binary\n+\t * - 12 byte non-volatile bootstrap header\n+\t * - 64 byte U-Boot mkimage header\n+\t * - U-Boot binary\n+\t */\n+\tspl->data_addr = image_copy_end() - CONFIG_SPL_TEXT_BASE + 24;\n+\n+\tspl_puts(\"SPL: probing SPI flash\\n\");\n+\n+\tspi_init();\n+\tret = spl_spi_flash_probe(&sf);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tspl_debug(\"SPL: reading image header at offset %lx\\n\", spl->data_addr);\n+\n+\tret = spi_flash_read(&sf, spl->data_addr, sizeof(hdr), &hdr);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tspl_debug(\"SPL: checking image header at offset %lx\\n\", spl->data_addr);\n+\n+\tret = spl_parse_image(&hdr, spl);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tif (spl_is_compressed(spl))\n+\t\tloadaddr = CONFIG_LOADADDR;\n+\telse\n+\t\tloadaddr = spl->entry_addr;\n+\n+\tspl_puts(\"SPL: loading U-Boot to RAM\\n\");\n+\n+\tret = spi_flash_read(&sf, spl->data_addr, spl->data_size,\n+\t\t\t\t(void *) loadaddr);\n+\n+\tif (!spl_check_data(spl, loadaddr))\n+\t\treturn -1;\n+\n+\tif (spl_is_compressed(spl))\n+\t\tret = spl_uncompress(spl, loadaddr);\n+\n+\treturn ret;\n+}\n+\n+static int spl_load_nor_flash(struct spl_image *spl)\n+{\n+\tconst image_header_t *hdr;\n+\tint ret;\n+\n+\t/*\n+\t * Image format:\n+\t *\n+\t * - SPL binary\n+\t * - 64 byte U-Boot mkimage header\n+\t * - U-Boot binary\n+\t */\n+\tspl->data_addr = image_copy_end();\n+\thdr = (const image_header_t *) image_copy_end();\n+\n+\tspl_debug(\"SPL: checking image header at address %p\\n\", hdr);\n+\n+\tret = spl_parse_image(hdr, spl);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tif (spl_is_compressed(spl))\n+\t\tret = spl_uncompress(spl, spl->data_addr);\n+\telse\n+\t\tret = spl_copy_image(spl);\n+\n+\treturn ret;\n+}\n+\n+static int spl_load(struct spl_image *spl)\n+{\n+\tint ret;\n+\n+\tif (spl_boot_spi_flash)\n+\t\tret = spl_load_spi_flash(spl);\n+\telse if (spl_boot_nor_flash)\n+\t\tret = spl_load_nor_flash(spl);\n+\telse\n+\t\tret = 1;\n+\n+\treturn ret;\n+}\n+\n+void __noreturn spl_lantiq_init(void)\n+{\n+\tvoid (*uboot)(void) __noreturn;\n+\tstruct spl_image spl;\n+\tgd_t gd_data;\n+\tint ret;\n+\n+\tgd = &gd_data;\n+\tbarrier();\n+\tmemset((void *)gd, 0, sizeof(gd_t));\n+\n+\tspl_console_init();\n+\n+\tspl_debug(\"SPL: initializing\\n\");\n+\n+#if 0\n+\tspl_debug(\"CP0_CONFIG:   %08x\\n\", read_c0_config());\n+\tspl_debug(\"CP0_CONFIG1:  %08x\\n\", read_c0_config1());\n+\tspl_debug(\"CP0_CONFIG2:  %08x\\n\", read_c0_config2());\n+\tspl_debug(\"CP0_CONFIG3:  %08x\\n\", read_c0_config3());\n+\tspl_debug(\"CP0_CONFIG6:  %08x\\n\", read_c0_config6());\n+\tspl_debug(\"CP0_CONFIG7:  %08x\\n\", read_c0_config7());\n+\tspl_debug(\"CP0_STATUS:   %08x\\n\", read_c0_status());\n+\tspl_debug(\"CP0_PRID:     %08x\\n\", read_c0_prid());\n+#endif\n+\n+\tboard_early_init_f();\n+\ttimer_init();\n+\n+\tmemset(&spl, 0, sizeof(spl));\n+\n+\tret = spl_load(&spl);\n+\tif (ret)\n+\t\tgoto hang;\n+\n+\tspl_debug(\"SPL: U-Boot entry %08lx\\n\", spl.entry_addr);\n+\tspl_puts(\"SPL: jumping to U-Boot\\n\");\n+\n+\tflush_cache(spl.entry_addr, spl.entry_size);\n+\tspl_sync();\n+\n+\tuboot = (void *) spl.entry_addr;\n+\tuboot();\n+\n+hang:\n+\tspl_puts(\"SPL: cannot start U-Boot\\n\");\n+\n+\tfor (;;)\n+\t\t;\n+}\n--- /dev/null\n+++ b/arch/mips/cpu/mips32/lantiq-common/start.S\n@@ -0,0 +1,143 @@\n+/*\n+ * Copyright (C) 2010 Lantiq Deutschland GmbH\n+ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#include <config.h>\n+#include <asm/regdef.h>\n+#include <asm/mipsregs.h>\n+\n+#define S_PRIdCoID\t16\t\t/* Company ID (R) */\n+#define M_PRIdCoID\t(0xff << S_PRIdCoID)\n+#define S_PRIdImp\t8\t\t/* Implementation ID (R) */\n+#define M_PRIdImp\t(0xff << S_PRIdImp)\n+\n+#define K_CacheAttrCWTnWA\t0\t/* Cacheable, write-thru, no write allocate */\n+#define K_CacheAttrCWTWA\t1\t/* Cacheable, write-thru, write allocate */\n+#define K_CacheAttrU\t\t2\t/* Uncached */\n+#define K_CacheAttrC\t\t3\t/* Cacheable */\n+#define K_CacheAttrCN\t\t3\t/* Cacheable, non-coherent */\n+#define K_CacheAttrCCE\t\t4\t/* Cacheable, coherent, exclusive */\n+#define K_CacheAttrCCS\t\t5\t/* Cacheable, coherent, shared */\n+#define K_CacheAttrCCU\t\t6\t/* Cacheable, coherent, update */\n+#define K_CacheAttrUA\t\t7\t/* Uncached accelerated */\n+\n+#define S_ConfigK23\t\t28\t/* Kseg2/3 coherency algorithm (FM MMU only) (R/W) */\n+#define M_ConfigK23\t\t(0x7 << S_ConfigK23)\n+#define W_ConfigK23\t\t3\n+#define S_ConfigKU\t\t25\t/* Kuseg coherency algorithm (FM MMU only) (R/W) */\n+#define M_ConfigKU\t\t(0x7 << S_ConfigKU)\n+#define W_ConfigKU\t\t3\n+\n+#define S_ConfigMM\t\t18\t/* Merge mode (implementation specific) */\n+#define M_ConfigMM\t\t(0x1 << S_ConfigMM)\n+\n+#define S_StatusBEV\t\t22\t/* Enable Boot Exception Vectors (R/W) */\n+#define M_StatusBEV\t\t(0x1 << S_StatusBEV)\n+\n+#define S_StatusFR\t\t26\t/* Enable 64-bit FPRs (R/W) */\n+#define M_StatusFR\t\t(0x1 << S_StatusFR)\n+\n+#define S_ConfigK0\t\t0\t/* Kseg0 coherency algorithm (R/W) */\n+#define M_ConfigK0\t\t(0x7 << S_ConfigK0)\n+\n+#define CONFIG0_MIPS32_64_MSK\t0x8000ffff\n+#define STATUS_MIPS32_64_MSK\t0xfffcffff\n+\n+#define STATUS_MIPS24K\t\t0\n+#define CONFIG0_MIPS24K\t\t((K_CacheAttrCN << S_ConfigK23) |\\\n+\t\t\t\t(K_CacheAttrCN << S_ConfigKU)  |\\\n+\t\t\t\t(M_ConfigMM))\n+\n+#define STATUS_MIPS34K\t\t0\n+#define CONFIG0_MIPS34K\t\t((K_CacheAttrCN << S_ConfigK23) |\\\n+\t\t\t\t(K_CacheAttrCN << S_ConfigKU) |\\\n+\t\t\t\t(M_ConfigMM))\n+\n+#define STATUS_MIPS32_64\t(M_StatusBEV | M_StatusFR)\n+#define CONFIG0_MIPS32_64\t(K_CacheAttrCN << S_ConfigK0)\n+\n+#ifdef CONFIG_SOC_XWAY_DANUBE\n+#define CONFIG0_LANTIQ\t\t(CONFIG0_MIPS24K | CONFIG0_MIPS32_64)\n+#define STATUS_LANTIQ\t\t(STATUS_MIPS24K | STATUS_MIPS32_64)\n+#endif\n+\n+#ifdef CONFIG_SOC_XWAY_VRX200\n+#define CONFIG0_LANTIQ\t\t(CONFIG0_MIPS34K | CONFIG0_MIPS32_64)\n+#define STATUS_LANTIQ\t\t(STATUS_MIPS34K | STATUS_MIPS32_64)\n+#endif\n+\n+\n+\t.set noreorder\n+\n+\t.globl _start\n+\t.text\n+_start:\n+\t/* Entry point */\n+\tb\tmain\n+\t nop\n+\n+\t/* Lantiq SoC Boot config word */\n+\t.org\t0x10\n+#ifdef CONFIG_SYS_XWAY_EBU_BOOTCFG\n+\t.word\tCONFIG_SYS_XWAY_EBU_BOOTCFG\n+#else\n+\t.word\t0\n+#endif\n+\t.word\t0\n+\n+\t.align\t4\n+main:\n+\n+\t/* Init Timer */\n+\tmtc0\tzero, CP0_COUNT\n+\tmtc0\tzero, CP0_COMPARE\n+\n+\t/* Setup MIPS24K/MIPS34K specifics (implementation dependent fields) */\n+\tmfc0\tt0, CP0_CONFIG\n+\tli\tt1, CONFIG0_MIPS32_64_MSK\n+\tand\tt0, t1\n+\tli\tt1, CONFIG0_LANTIQ\n+\tor\tt0, t1\n+\tmtc0\tt0, CP0_CONFIG\n+\n+\tmfc0\tt0, CP0_STATUS\n+\tli\tt1, STATUS_MIPS32_64_MSK\n+\tand\tt0, t1\n+\tli\tt1, STATUS_LANTIQ\n+\tor\tt0, t1\n+\tmtc0\tt0, CP0_STATUS\n+\n+\t/* Initialize CGU */\n+\tla\tt9, ltq_cgu_init\n+\tjalr\tt9\n+\t nop\n+\n+\t/* Initialize memory controller */\n+\tla\tt9, ltq_mem_init\n+\tjalr\tt9\n+\t nop\n+\n+\t/* Initialize caches... */\n+\tla\tt9, mips_cache_reset\n+\tjalr\tt9\n+\t nop\n+\n+\t/* Clear BSS */\n+\tla\tt1, __bss_start\n+\tla\tt2, __bss_end\n+\tsub\tt1, 4\n+1:\n+\taddi\tt1, 4\n+\tbltl\tt1, t2, 1b\n+\t sw\tzero, 0(t1)\n+\n+\t/* Setup stack pointer and force alignment on a 16 byte boundary */\n+\tli\tt0, (CONFIG_SPL_STACK_BASE & ~0xF)\n+\tla\tsp, 0(t0)\n+\n+\tla\tt9, spl_lantiq_init\n+\tjr\tt9\n+\t nop\n--- /dev/null\n+++ b/arch/mips/cpu/mips32/lantiq-common/u-boot-spl.lds\n@@ -0,0 +1,48 @@\n+/*\n+ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+MEMORY { .spl_mem : ORIGIN = CONFIG_SPL_TEXT_BASE, \\\n+\t\tLENGTH = CONFIG_SPL_MAX_SIZE }\n+MEMORY { .bss_mem : ORIGIN = CONFIG_SPL_BSS_BASE, \\\n+\t\tLENGTH = CONFIG_SPL_BSS_MAX_SIZE }\n+\n+OUTPUT_FORMAT(\"elf32-tradbigmips\", \"elf32-tradbigmips\", \"elf32-tradlittlemips\")\n+OUTPUT_ARCH(mips)\n+ENTRY(_start)\n+SECTIONS\n+{\n+\t. = ALIGN(4);\n+\t.text : {\n+\t\t*(.text*)\n+\t} > .spl_mem\n+\n+\t. = ALIGN(4);\n+\t.rodata : {\n+\t\t*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))\n+\t} > .spl_mem\n+\n+\t. = ALIGN(4);\n+\t.data : {\n+\t\t*(SORT_BY_ALIGNMENT(.data*))\n+\t\t*(SORT_BY_ALIGNMENT(.sdata*))\n+\t} > .spl_mem\n+\n+\t. = ALIGN(4);\n+\t__image_copy_end = .;\n+\tuboot_end_data = .;\n+\n+\t.bss : {\n+\t\t__bss_start = .;\n+\t\t*(.bss*)\n+\t\t*(.sbss*)\n+\t\t. = ALIGN(4);\n+\t\t__bss_end = .;\n+\t} > .bss_mem\n+\n+\t. = ALIGN(4);\n+\t__end = .;\n+\tuboot_end = .;\n+}\n--- a/arch/mips/cpu/mips32/start.S\n+++ b/arch/mips/cpu/mips32/start.S\n@@ -105,7 +105,7 @@ reset:\n \tmtc0\tzero, CP0_COUNT\n \tmtc0\tzero, CP0_COMPARE\n \n-#ifndef CONFIG_SKIP_LOWLEVEL_INIT\n+#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) || defined(CONFIG_SYS_DISABLE_CACHE)\n \t/* CONFIG0 register */\n \tli\tt0, CONF_CM_UNCACHED\n \tmtc0\tt0, CP0_CONFIG\n--- /dev/null\n+++ b/arch/mips/cpu/mips32/vrx200/Makefile\n@@ -0,0 +1,32 @@\n+#\n+# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de\n+#\n+# SPDX-License-Identifier:\tGPL-2.0+\n+#\n+\n+include $(TOPDIR)/config.mk\n+\n+LIB\t= $(obj)lib$(SOC).o\n+\n+COBJS-y\t+= cgu.o chipid.o dcdc.o ebu.o gphy.o mem.o pmu.o rcu.o\n+SOBJS-y\t+= cgu_init.o mem_init.o\n+SOBJS-y\t+= gphy_fw.o\n+\n+COBJS\t:= $(COBJS-y)\n+SOBJS\t:= $(SOBJS-y)\n+SRCS\t:= $(SOBJS:.o=.S) $(COBJS:.o=.c)\n+OBJS\t:= $(addprefix $(obj),$(SOBJS) $(COBJS))\n+\n+all:\t$(LIB)\n+\n+$(LIB):\t$(obj).depend $(OBJS)\n+\t$(call cmd_link_o_target, $(OBJS))\n+\n+#########################################################################\n+\n+# defines $(obj).depend target\n+include $(SRCTREE)/rules.mk\n+\n+sinclude $(obj).depend\n+\n+#########################################################################\n--- /dev/null\n+++ b/arch/mips/cpu/mips32/vrx200/cgu.c\n@@ -0,0 +1,208 @@\n+/*\n+ * Copyright (C) 2010 Lantiq Deutschland GmbH\n+ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#include <common.h>\n+#include <asm/arch/soc.h>\n+#include <asm/arch/gphy.h>\n+#include <asm/lantiq/clk.h>\n+#include <asm/lantiq/io.h>\n+\n+#define LTQ_CGU_PLL1_PLLN_SHIFT\t\t6\n+#define LTQ_CGU_PLL1_PLLN_MASK\t\t(0x3F << LTQ_CGU_PLL1_PLLN_SHIFT)\n+#define LTQ_CGU_PLL1_PLLM_SHIFT\t\t2\n+#define LTQ_CGU_PLL1_PLLM_MASK\t\t(0xF << LTQ_CGU_PLL1_PLLM_SHIFT)\n+#define LTQ_CGU_PLL1_PLLL\t\t(1 << 1)\n+#define LTQ_CGU_PLL1_PLL_EN\t\t1\n+\n+#define LTQ_CGU_SYS_OCP_SHIFT\t\t0\n+#define LTQ_CGU_SYS_OCP_MASK\t\t(0x3 << LTQ_CGU_SYS_OCP_SHIFT)\n+#define LTQ_CGU_SYS_CPU_SHIFT\t\t4\n+#define LTQ_CGU_SYS_CPU_MASK\t\t(0xF << LTQ_CGU_SYS_CPU_SHIFT)\n+\n+#define LTQ_CGU_UPDATE\t\t\t1\n+\n+#define LTQ_CGU_IFCLK_GPHY_SEL_SHIFT\t2\n+#define LTQ_CGU_IFCLK_GPHY_SEL_MASK\t(0x7 << LTQ_CGU_IFCLK_GPHY_SEL_SHIFT)\n+\n+struct ltq_cgu_regs {\n+\tu32\trsvd0;\n+\tu32\tpll0_cfg;\t/* PLL0 config */\n+\tu32\tpll1_cfg;\t/* PLL1 config */\n+\tu32\tsys;\t\t/* System clock */\n+\tu32\tclk_fsr;\t/* Clock frequency select */\n+\tu32\tclk_gsr;\t/* Clock gating status */\n+\tu32\tclk_gcr0;\t/* Clock gating control 0 */\n+\tu32\tclk_gcr1;\t/* Clock gating control 1 */\n+\tu32\tupdate;\t\t/* CGU update control */\n+\tu32\tif_clk;\t\t/* Interface clock */\n+\tu32\tddr;\t\t/* DDR memory control */\n+\tu32\tct1_sr;\t\t/* CT status 1 */\n+\tu32\tct_kval;\t/* CT K value */\n+\tu32\tpcm_cr;\t\t/* PCM control */\n+\tu32\tpci_cr;\t\t/* PCI clock control */\n+\tu32\trsvd1;\n+\tu32\tgphy1_cfg;\t/* GPHY1 config */\n+\tu32\tgphy0_cfg;\t/* GPHY0 config */\n+\tu32\trsvd2[6];\n+\tu32\tpll2_cfg;\t/* PLL2 config */\n+};\n+\n+static struct ltq_cgu_regs *ltq_cgu_regs =\n+\t(struct ltq_cgu_regs *) CKSEG1ADDR(LTQ_CGU_BASE);\n+\n+static inline u32 ltq_cgu_sys_readl(u32 mask, u32 shift)\n+{\n+\treturn (ltq_readl(&ltq_cgu_regs->sys) & mask) >> shift;\n+}\n+\n+unsigned long ltq_get_io_region_clock(void)\n+{\n+\tunsigned int ocp_sel;\n+\tunsigned long clk, cpu_clk;\n+\n+\tcpu_clk = ltq_get_cpu_clock();\n+\n+\tocp_sel = ltq_cgu_sys_readl(LTQ_CGU_SYS_OCP_MASK,\n+\t\t\tLTQ_CGU_SYS_OCP_SHIFT);\n+\n+\tswitch (ocp_sel) {\n+\tcase 0:\n+\t\t/* OCP ratio 1 */\n+\t\tclk = cpu_clk;\n+\t\tbreak;\n+\tcase 2:\n+\t\t/* OCP ratio 2 */\n+\t\tclk = cpu_clk / 2;\n+\t\tbreak;\n+\tcase 3:\n+\t\t/* OCP ratio 2.5 */\n+\t\tclk = (cpu_clk * 2) / 5;\n+\t\tbreak;\n+\tcase 4:\n+\t\t/* OCP ratio 3 */\n+\t\tclk = cpu_clk / 3;\n+\t\tbreak;\n+\tdefault:\n+\t\tclk = 0;\n+\t\tbreak;\n+\t}\n+\n+\treturn clk;\n+}\n+\n+unsigned long ltq_get_cpu_clock(void)\n+{\n+\tunsigned int cpu_sel;\n+\tunsigned long clk;\n+\n+\tcpu_sel = ltq_cgu_sys_readl(LTQ_CGU_SYS_CPU_MASK,\n+\t\t\tLTQ_CGU_SYS_CPU_SHIFT);\n+\n+\tswitch (cpu_sel) {\n+\tcase 0:\n+\t\tclk = CLOCK_600_MHZ;\n+\t\tbreak;\n+\tcase 1:\n+\t\tclk = CLOCK_500_MHZ;\n+\t\tbreak;\n+\tcase 2:\n+\t\tclk = CLOCK_393_MHZ;\n+\t\tbreak;\n+\tcase 3:\n+\t\tclk = CLOCK_333_MHZ;\n+\t\tbreak;\n+\tcase 5:\n+\tcase 6:\n+\t\tclk = CLOCK_197_MHZ;\n+\t\tbreak;\n+\tcase 7:\n+\t\tclk = CLOCK_166_MHZ;\n+\t\tbreak;\n+\tcase 4:\n+\tcase 8:\n+\tcase 9:\n+\t\tclk = CLOCK_125_MHZ;\n+\t\tbreak;\n+\tdefault:\n+\t\tclk = 0;\n+\t\tbreak;\n+\t}\n+\n+\treturn clk;\n+}\n+\n+unsigned long ltq_get_bus_clock(void)\n+{\n+\treturn ltq_get_io_region_clock();\n+}\n+\n+void ltq_cgu_gphy_clk_src(enum ltq_gphy_clk clk)\n+{\n+\tltq_clrbits(&ltq_cgu_regs->if_clk, LTQ_CGU_IFCLK_GPHY_SEL_MASK);\n+\tltq_setbits(&ltq_cgu_regs->if_clk, clk << LTQ_CGU_IFCLK_GPHY_SEL_SHIFT);\n+}\n+\n+static inline int ltq_cgu_pll1_locked(void)\n+{\n+\tu32 pll1_cfg = ltq_readl(&ltq_cgu_regs->pll1_cfg);\n+\n+\treturn pll1_cfg & LTQ_CGU_PLL1_PLLL;\n+}\n+\n+static inline void ltq_cgu_pll1_restart(unsigned m, unsigned n)\n+{\n+\tu32 pll1_cfg;\n+\n+\tltq_clrbits(&ltq_cgu_regs->pll1_cfg, LTQ_CGU_PLL1_PLL_EN);\n+\tltq_setbits(&ltq_cgu_regs->update, LTQ_CGU_UPDATE);\n+\n+\tpll1_cfg = ltq_readl(&ltq_cgu_regs->pll1_cfg);\n+\tpll1_cfg &= ~(LTQ_CGU_PLL1_PLLN_MASK | LTQ_CGU_PLL1_PLLM_MASK);\n+\tpll1_cfg |= n << LTQ_CGU_PLL1_PLLN_SHIFT;\n+\tpll1_cfg |= m << LTQ_CGU_PLL1_PLLM_SHIFT;\n+\tpll1_cfg |= LTQ_CGU_PLL1_PLL_EN;\n+\tltq_writel(&ltq_cgu_regs->pll1_cfg, pll1_cfg);\n+\tltq_setbits(&ltq_cgu_regs->update, LTQ_CGU_UPDATE);\n+\n+\t__udelay(1000);\n+}\n+\n+/*\n+ * From chapter 9 in errata sheet:\n+ *\n+ * Under certain condition, the PLL1 may failed to enter into lock\n+ * status by hardware default N, M setting.\n+ *\n+ * Since system always starts from PLL0, the system software can run\n+ * and re-program the PLL1 settings.\n+ */\n+static void ltq_cgu_pll1_init(void)\n+{\n+\tunsigned i;\n+\tconst unsigned pll1_m[] = { 1, 2, 3, 4 };\n+\tconst unsigned pll1_n[] = { 21, 32, 43, 54 };\n+\n+\t/* Check if PLL1 has locked with hardware default settings */\n+\tif (ltq_cgu_pll1_locked())\n+\t\treturn;\n+\n+\tfor (i = 0; i < 4; i++) {\n+\t\tltq_cgu_pll1_restart(pll1_m[i], pll1_n[i]);\n+\n+\t\tif (ltq_cgu_pll1_locked())\n+\t\t\tgoto done;\n+\t}\n+\n+done:\n+\t/* Restart with hardware default values M=5, N=64 */\n+\tltq_cgu_pll1_restart(5, 64);\n+}\n+\n+void ltq_pll_init(void)\n+{\n+\tltq_cgu_pll1_init();\n+}\n--- /dev/null\n+++ b/arch/mips/cpu/mips32/vrx200/cgu_init.S\n@@ -0,0 +1,119 @@\n+/*\n+ * Copyright (C) 2010 Lantiq Deutschland GmbH\n+ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#include <config.h>\n+#include <asm/asm.h>\n+#include <asm/regdef.h>\n+#include <asm/addrspace.h>\n+#include <asm/arch/soc.h>\n+\n+/* RCU module register */\n+#define LTQ_RCU_RST_REQ\t\t\t0x0010\t/* Reset request */\n+#define LTQ_RCU_RST_REQ_VALUE\t\t((1 << 14) | (1 << 1))\n+\n+/* CGU module register */\n+#define LTQ_CGU_PLL0_CFG\t\t0x0004\t/* PLL0 config */\n+#define LTQ_CGU_PLL1_CFG\t\t0x0008\t/* PLL1 config */\n+#define LTQ_CGU_PLL2_CFG\t\t0x0060\t/* PLL2 config */\n+#define LTQ_CGU_SYS\t\t\t0x000C\t/* System clock */\n+#define LTQ_CGU_CLK_FSR\t\t\t0x0010\t/* Clock frequency select */\n+#define LTQ_CGU_UPDATE\t\t\t0x0020\t/* Clock update control */\n+\n+/* Valid SYS.CPU values */\n+#define LTQ_CGU_SYS_CPU_SHIFT\t\t4\n+#define LTQ_CGU_SYS_CPU_600_MHZ\t\t0x0\n+#define LTQ_CGU_SYS_CPU_500_MHZ\t\t0x1\n+#define LTQ_CGU_SYS_CPU_393_MHZ\t\t0x2\n+#define LTQ_CGU_SYS_CPU_333_MHZ\t\t0x3\n+#define LTQ_CGU_SYS_CPU_197_MHZ\t\t0x5\n+#define LTQ_CGU_SYS_CPU_166_MHZ\t\t0x7\n+#define LTQ_CGU_SYS_CPU_125_MHZ\t\t0x9\n+\n+/* Valid SYS.OCP values */\n+#define LTQ_CGU_SYS_OCP_SHIFT\t\t0\n+#define LTQ_CGU_SYS_OCP_1\t\t0x0\n+#define LTQ_CGU_SYS_OCP_2\t\t0x2\n+#define LTQ_CGU_SYS_OCP_2_5\t\t0x3\n+#define LTQ_CGU_SYS_OCP_3\t\t0x4\n+\n+/* Valid CLK_FSR.ETH values */\n+#define LTQ_CGU_CLK_FSR_ETH_SHIFT\t24\n+#define LTQ_CGU_CLK_FSR_ETH_50_MHZ\t0x0\n+#define LTQ_CGU_CLK_FSR_ETH_25_MHZ\t0x1\n+#define LTQ_CGU_CLK_FSR_ETH_2_5_MHZ\t0x2\n+#define LTQ_CGU_CLK_FSR_ETH_125_MHZ\t0x3\n+\n+/* Valid CLK_FSR.PPE values */\n+#define LTQ_CGU_CLK_FSR_PPE_SHIFT\t16\n+#define LTQ_CGU_CLK_FSR_PPE_500_MHZ\t0x0\t/* Overclock frequency */\n+#define LTQ_CGU_CLK_FSR_PPE_450_MHZ\t0x1\t/* High frequency */\n+#define LTQ_CGU_CLK_FSR_PPE_400_MHZ\t0x2\t/* Low frequency */\n+\n+#if (CONFIG_SYS_CLOCK_MODE == LTQ_CLK_CPU_500_DDR_250)\n+#define LTQ_CGU_SYS_CPU_CONFIG\t\tLTQ_CGU_SYS_CPU_500_MHZ\n+#define LTQ_CGU_SYS_OCP_CONFIG\t\tLTQ_CGU_SYS_OCP_2\n+#define LTQ_CGU_CLK_FSR_ETH_CONFIG\tLTQ_CGU_CLK_FSR_ETH_125_MHZ\n+#define LTQ_CGU_CLK_FSR_PPE_CONFIG\tLTQ_CGU_CLK_FSR_PPE_450_MHZ\n+#else\n+#error \"Invalid system clock configuration!\"\n+#endif\n+\n+/* Build register values */\n+#define LTQ_CGU_SYS_VALUE\t((LTQ_CGU_SYS_CPU_CONFIG << \\\n+\t\t\t\t\tLTQ_CGU_SYS_CPU_SHIFT) | \\\n+\t\t\t\t\tLTQ_CGU_SYS_OCP_CONFIG)\n+\n+#define LTQ_CGU_CLK_FSR_VALUE\t((LTQ_CGU_CLK_FSR_ETH_CONFIG << \\\n+\t\t\t\t\tLTQ_CGU_CLK_FSR_ETH_SHIFT) | \\\n+\t\t\t\t(LTQ_CGU_CLK_FSR_PPE_CONFIG << \\\n+\t\t\t\t\tLTQ_CGU_CLK_FSR_PPE_SHIFT))\n+\n+\t.set noreorder\n+\n+LEAF(ltq_cgu_init)\n+\t/* Load current CGU register values */\n+\tli\tt0, (LTQ_CGU_BASE | KSEG1)\n+\tlw\tt1, LTQ_CGU_SYS(t0)\n+\tlw\tt2, LTQ_CGU_CLK_FSR(t0)\n+\n+\t/* Load target CGU register values */\n+\tli\tt3, LTQ_CGU_SYS_VALUE\n+\tli\tt4, LTQ_CGU_CLK_FSR_VALUE\n+\n+\t/* Only update registers if values differ */\n+\tbne\tt1, t3, update\n+\t nop\n+\tbeq\tt2, t4, finished\n+\t nop\n+\n+update:\n+\t/* Store target register values */\n+\tsw\tt3, LTQ_CGU_SYS(t0)\n+\tsw\tt4, LTQ_CGU_CLK_FSR(t0)\n+\n+\t/* Perform software reset to activate new clock config */\n+#if 0\n+\tli\tt0, (LTQ_RCU_BASE | KSEG1)\n+\tlw\tt1, LTQ_RCU_RST_REQ(t0)\n+\tor\tt1, LTQ_RCU_RST_REQ_VALUE\n+\tsw\tt1, LTQ_RCU_RST_REQ(t0)\n+#else\n+\tli\tt1, 1\n+\tsw\tt1, LTQ_CGU_UPDATE(t0)\n+#endif\n+\n+#if 0\n+wait_reset:\n+\tb\twait_reset\n+\t nop\n+#endif\n+\n+finished:\n+\tjr\tra\n+\t nop\n+\n+\tEND(ltq_cgu_init)\n--- /dev/null\n+++ b/arch/mips/cpu/mips32/vrx200/chipid.c\n@@ -0,0 +1,62 @@\n+/*\n+ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#include <common.h>\n+#include <asm/lantiq/io.h>\n+#include <asm/lantiq/chipid.h>\n+#include <asm/arch/soc.h>\n+\n+#define LTQ_CHIPID_VERSION_SHIFT\t28\n+#define LTQ_CHIPID_VERSION_MASK\t\t(0x7 << LTQ_CHIPID_VERSION_SHIFT)\n+#define LTQ_CHIPID_PNUM_SHIFT\t\t12\n+#define LTQ_CHIPID_PNUM_MASK\t\t(0xFFFF << LTQ_CHIPID_PNUM_SHIFT)\n+\n+struct ltq_chipid_regs {\n+\tu32\tmanid;\t\t/* Manufacturer identification */\n+\tu32\tchipid;\t\t/* Chip identification */\n+};\n+\n+static struct ltq_chipid_regs *ltq_chipid_regs =\n+\t(struct ltq_chipid_regs *) CKSEG1ADDR(LTQ_CHIPID_BASE);\n+\n+unsigned int ltq_chip_version_get(void)\n+{\n+\tu32 chipid;\n+\n+\tchipid = ltq_readl(&ltq_chipid_regs->chipid);\n+\n+\treturn (chipid & LTQ_CHIPID_VERSION_MASK) >> LTQ_CHIPID_VERSION_SHIFT;\n+}\n+\n+unsigned int ltq_chip_partnum_get(void)\n+{\n+\tu32 chipid;\n+\n+\tchipid = ltq_readl(&ltq_chipid_regs->chipid);\n+\n+\treturn (chipid & LTQ_CHIPID_PNUM_MASK) >> LTQ_CHIPID_PNUM_SHIFT;\n+}\n+\n+const char *ltq_chip_partnum_str(void)\n+{\n+\tenum ltq_chip_partnum partnum = ltq_chip_partnum_get();\n+\n+\tswitch (partnum) {\n+\tcase LTQ_SOC_VRX268:\n+\tcase LTQ_SOC_VRX268_2:\n+\t\treturn \"VRX268\";\n+\tcase LTQ_SOC_VRX288:\n+\tcase LTQ_SOC_VRX288_2:\n+\t\treturn \"VRX288\";\n+\tcase LTQ_SOC_GRX288:\n+\tcase LTQ_SOC_GRX288_2:\n+\t\treturn \"GRX288\";\n+\tdefault:\n+\t\tprintf(\"Unknown partnum: %x\\n\", partnum);\n+\t}\n+\n+\treturn \"\";\n+}\n--- /dev/null\n+++ b/arch/mips/cpu/mips32/vrx200/config.mk\n@@ -0,0 +1,30 @@\n+#\n+# Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com\n+#\n+# SPDX-License-Identifier:\tGPL-2.0+\n+#\n+\n+PF_CPPFLAGS_XRX := $(call cc-option,-mtune=34kc,)\n+PLATFORM_CPPFLAGS += $(PF_CPPFLAGS_XRX)\n+\n+ifdef CONFIG_SPL_BUILD\n+PF_ABICALLS\t\t:= -mno-abicalls\n+PF_PIC\t\t\t:= -fno-pic\n+PF_PIE\t\t\t:=\n+USE_PRIVATE_LIBGCC\t:= yes\n+endif\n+\n+LIBS-y += $(CPUDIR)/lantiq-common/liblantiq-common.o\n+\n+ifndef CONFIG_SPL_BUILD\n+ifdef CONFIG_SYS_BOOT_SFSPL\n+ALL-y += $(obj)u-boot.ltq.sfspl\n+ALL-$(CONFIG_SPL_LZO_SUPPORT) += $(obj)u-boot.ltq.lzo.sfspl\n+ALL-$(CONFIG_SPL_LZMA_SUPPORT) += $(obj)u-boot.ltq.lzma.sfspl\n+endif\n+ifdef CONFIG_SYS_BOOT_NORSPL\n+ALL-y += $(obj)u-boot.ltq.norspl\n+ALL-$(CONFIG_SPL_LZO_SUPPORT) += $(obj)u-boot.ltq.lzo.norspl\n+ALL-$(CONFIG_SPL_LZMA_SUPPORT) += $(obj)u-boot.ltq.lzma.norspl\n+endif\n+endif\n--- /dev/null\n+++ b/arch/mips/cpu/mips32/vrx200/dcdc.c\n@@ -0,0 +1,106 @@\n+/*\n+ * Copyright (C) 2010 Lantiq Deutschland GmbH\n+ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#include <common.h>\n+#include <asm/arch/soc.h>\n+#include <asm/lantiq/io.h>\n+\n+#define LTQ_DCDC_CLK_SET0_CLK_SEL_P\t\t(1 << 6)\n+#define LTQ_DCDC_CLK_SET1_SEL_DIV25\t\t(1 << 5)\n+#define LTQ_DCDC_CONF_TEST_DIG_PID_FREEZE\t(1 << 5)\n+\n+struct ltq_dcdc_regs {\n+\tu8\tb0_coeh;\t\t/* Coefficient b0 */\n+\tu8\tb0_coel;\t\t/* Coefficient b0 */\n+\tu8\tb1_coeh;\t\t/* Coefficient b1 */\n+\tu8\tb1_coel;\t\t/* Coefficient b1 */\n+\tu8\tb2_coeh;\t\t/* Coefficient b2 */\n+\tu8\tb2_coel;\t\t/* Coefficient b2 */\n+\tu8\tclk_set0;\t\t/* Clock setup */\n+\tu8\tclk_set1;\t\t/* Clock setup */\n+\tu8\tpwm_confh;\t\t/* Configure PWM */\n+\tu8\tpwm_confl;\t\t/* Configure PWM */\n+\tu8\tbias_vreg0;\t\t/* Bias and regulator setup */\n+\tu8\tbias_vreg1;\t\t/* Bias and regulator setup */\n+\tu8\tadc_gen0;\t\t/* ADC and general control */\n+\tu8\tadc_gen1;\t\t/* ADC and general control */\n+\tu8\tadc_con0;\t\t/* ADC and general config */\n+\tu8\tadc_con1;\t\t/* ADC and general config */\n+\tu8\tconf_test_ana;\t\t/* not documented */\n+\tu8\tconf_test_dig;\t\t/* not documented */\n+\tu8\tdcdc_status;\t\t/* not documented */\n+\tu8\tpid_status;\t\t/* not documented */\n+\tu8\tduty_cycle;\t\t/* not documented */\n+\tu8\tnon_ov_delay;\t\t/* not documented */\n+\tu8\tanalog_gain;\t\t/* not documented */\n+\tu8\tduty_cycle_max_sat;\t/* not documented */\n+\tu8\tduty_cycle_min_sat;\t/* not documented */\n+\tu8\tduty_cycle_max;\t\t/* not documented */\n+\tu8\tduty_cycle_min;\t\t/* not documented */\n+\tu8\terror_max;\t\t/* not documented */\n+\tu8\terror_read;\t\t/* not documented */\n+\tu8\tdelay_deglitch;\t\t/* not documented */\n+\tu8\tlatch_control;\t\t/* not documented */\n+\tu8\trsvd[240];\n+\tu8\tosc_conf;\t\t/* OSC general config */\n+\tu8\tosc_stat;\t\t/* OSC general status */\n+};\n+\n+static struct ltq_dcdc_regs *ltq_dcdc_regs =\n+\t(struct ltq_dcdc_regs *) CKSEG1ADDR(LTQ_DCDC_BASE);\n+\n+void ltq_dcdc_init(unsigned int dig_ref)\n+{\n+\tu8 dig_ref_cur, val;\n+\n+\t/* Set duty cycle max sat. to 70/90, enable PID freeze */\n+\tltq_writeb(&ltq_dcdc_regs->duty_cycle_max_sat, 0x5A);\n+\tltq_writeb(&ltq_dcdc_regs->duty_cycle_min_sat, 0x46);\n+\tval = ltq_readb(&ltq_dcdc_regs->conf_test_dig);\n+\tval |= LTQ_DCDC_CONF_TEST_DIG_PID_FREEZE;\n+\tltq_writeb(&ltq_dcdc_regs->conf_test_dig, val);\n+\n+\t/* Program new coefficients */\n+\tltq_writeb(&ltq_dcdc_regs->b0_coeh, 0x00);\n+\tltq_writeb(&ltq_dcdc_regs->b0_coel, 0x00);\n+\tltq_writeb(&ltq_dcdc_regs->b1_coeh, 0xFF);\n+\tltq_writeb(&ltq_dcdc_regs->b1_coel, 0xE6);\n+\tltq_writeb(&ltq_dcdc_regs->b2_coeh, 0x00);\n+\tltq_writeb(&ltq_dcdc_regs->b2_coel, 0x1B);\n+\tltq_writeb(&ltq_dcdc_regs->non_ov_delay, 0x8B);\n+\n+\t/* Set duty cycle max sat. to 60/108, disable PID freeze */\n+\tltq_writeb(&ltq_dcdc_regs->duty_cycle_max_sat, 0x6C);\n+\tltq_writeb(&ltq_dcdc_regs->duty_cycle_min_sat, 0x3C);\n+\tval = ltq_readb(&ltq_dcdc_regs->conf_test_dig);\n+\tval &= ~LTQ_DCDC_CONF_TEST_DIG_PID_FREEZE;\n+\tltq_writeb(&ltq_dcdc_regs->conf_test_dig, val);\n+\n+\t/* Init clock and DLL settings */\n+\tval = ltq_readb(&ltq_dcdc_regs->clk_set0);\n+\tval |= LTQ_DCDC_CLK_SET0_CLK_SEL_P;\n+\tltq_writeb(&ltq_dcdc_regs->clk_set0, val);\n+\tval = ltq_readb(&ltq_dcdc_regs->clk_set1);\n+\tval |= LTQ_DCDC_CLK_SET1_SEL_DIV25;\n+\tltq_writeb(&ltq_dcdc_regs->clk_set1, val);\n+\tltq_writeb(&ltq_dcdc_regs->pwm_confh, 0xF9);\n+\n+\twmb();\n+\n+\t/* Adapt value of digital reference of DCDC converter */\n+\tdig_ref_cur = ltq_readb(&ltq_dcdc_regs->bias_vreg1);\n+\n+\twhile (dig_ref_cur != dig_ref) {\n+\t\tif (dig_ref >= dig_ref_cur)\n+\t\t\tdig_ref_cur++;\n+\t\telse if (dig_ref < dig_ref_cur)\n+\t\t\tdig_ref_cur--;\n+\n+\t\tltq_writeb(&ltq_dcdc_regs->bias_vreg1, dig_ref_cur);\n+\t\t__udelay(1000);\n+\t}\n+}\n--- /dev/null\n+++ b/arch/mips/cpu/mips32/vrx200/ebu.c\n@@ -0,0 +1,126 @@\n+/*\n+ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#include <common.h>\n+#include <asm/arch/soc.h>\n+#include <asm/lantiq/io.h>\n+\n+#define EBU_ADDRSEL_MASK(mask)\t\t((mask & 0xf) << 4)\n+#define EBU_ADDRSEL_REGEN\t\t(1 << 0)\n+\n+#define EBU_CON_WRDIS\t\t\t(1 << 31)\n+#define EBU_CON_AGEN_DEMUX\t\t(0x0 << 24)\n+#define EBU_CON_AGEN_MUX\t\t(0x2 << 24)\n+#define EBU_CON_SETUP\t\t\t(1 << 22)\n+#define EBU_CON_WAIT_DIS\t\t(0x0 << 20)\n+#define EBU_CON_WAIT_ASYNC\t\t(0x1 << 20)\n+#define EBU_CON_WAIT_SYNC\t\t(0x2 << 20)\n+#define EBU_CON_WINV\t\t\t(1 << 19)\n+#define EBU_CON_PW_8BIT\t\t\t(0x0 << 16)\n+#define EBU_CON_PW_16BIT\t\t(0x1 << 16)\n+#define EBU_CON_ALEC(cycles)\t\t((cycles & 0x3) << 14)\n+#define EBU_CON_BCGEN_CS\t\t(0x0 << 12)\n+#define EBU_CON_BCGEN_INTEL\t\t(0x1 << 12)\n+#define EBU_CON_BCGEN_MOTOROLA\t\t(0x2 << 12)\n+#define EBU_CON_WAITWRC(cycles)\t\t((cycles & 0x7) << 8)\n+#define EBU_CON_WAITRDC(cycles)\t\t((cycles & 0x3) << 6)\n+#define EBU_CON_HOLDC(cycles)\t\t((cycles & 0x3) << 4)\n+#define EBU_CON_RECOVC(cycles)\t\t((cycles & 0x3) << 2)\n+#define EBU_CON_CMULT_1\t\t\t0x0\n+#define EBU_CON_CMULT_4\t\t\t0x1\n+#define EBU_CON_CMULT_8\t\t\t0x2\n+#define EBU_CON_CMULT_16\t\t0x3\n+\n+#if defined(CONFIG_LTQ_SUPPORT_NOR_FLASH)\n+#define ebu_region0_enable\t\t1\n+#else\n+#define ebu_region0_enable\t\t0\n+#endif\n+\n+#if ((CONFIG_SYS_MAX_FLASH_BANKS == 2) && defined(CONFIG_LTQ_SUPPORT_NOR_FLASH) )\n+#define ebu_region0_addrsel_mask\t3\n+#else\n+#define ebu_region0_addrsel_mask\t1\n+#endif\n+\n+#if defined(CONFIG_LTQ_SUPPORT_NAND_FLASH) || ((CONFIG_SYS_MAX_FLASH_BANKS == 2) && defined(CONFIG_LTQ_SUPPORT_NOR_FLASH) )\n+#define ebu_region1_enable\t\t1\n+#else\n+#define ebu_region1_enable\t\t0\n+#endif\n+\n+struct ltq_ebu_regs {\n+\tu32\tclc;\n+\tu32\trsvd0;\n+\tu32\tid;\n+\tu32\trsvd1;\n+\tu32\tcon;\n+\tu32\trsvd2[3];\n+\tu32\taddr_sel_0;\n+\tu32\taddr_sel_1;\n+\tu32\taddr_sel_2;\n+\tu32\taddr_sel_3;\n+\tu32\trsvd3[12];\n+\tu32\tcon_0;\n+\tu32\tcon_1;\n+\tu32\tcon_2;\n+\tu32\tcon_3;\n+};\n+\n+static struct ltq_ebu_regs *ltq_ebu_regs =\n+\t(struct ltq_ebu_regs *) CKSEG1ADDR(LTQ_EBU_BASE);\n+\n+void ltq_ebu_init(void)\n+{\n+\tif (ebu_region0_enable) {\n+\t\t/*\n+\t\t * Map EBU region 0 to range 0x10000000-0x13ffffff and enable\n+\t\t * region control. This supports up to 32 MiB NOR flash in\n+\t\t * bank 0.\n+\t\t */\n+\t\tltq_writel(&ltq_ebu_regs->addr_sel_0, LTQ_EBU_REGION0_BASE |\n+\t\t\tEBU_ADDRSEL_MASK(ebu_region0_addrsel_mask) | EBU_ADDRSEL_REGEN);\n+\n+\t\tltq_writel(&ltq_ebu_regs->con_0, EBU_CON_AGEN_DEMUX |\n+\t\t\tEBU_CON_WAIT_DIS | EBU_CON_PW_16BIT |\n+\t\t\tEBU_CON_ALEC(3) | EBU_CON_BCGEN_INTEL |\n+\t\t\tEBU_CON_WAITWRC(7) | EBU_CON_WAITRDC(3) |\n+\t\t\tEBU_CON_HOLDC(3) | EBU_CON_RECOVC(3) |\n+\t\t\tEBU_CON_CMULT_16);\n+\t} else\n+\t\tltq_clrbits(&ltq_ebu_regs->addr_sel_0, EBU_ADDRSEL_REGEN);\n+\n+\tif (ebu_region1_enable) {\n+\t\t/*\n+\t\t * Map EBU region 1 to range 0x14000000-0x13ffffff and enable\n+\t\t * region control. This supports NAND flash in bank 1. (and  NOR flash in bank 2)\n+\t\t */\n+\t\tltq_writel(&ltq_ebu_regs->addr_sel_1, LTQ_EBU_REGION1_BASE |\n+\t\t\tEBU_ADDRSEL_MASK(3) | EBU_ADDRSEL_REGEN);\n+\n+\t\tif (ebu_region0_addrsel_mask == 1)\n+\t\t\tltq_writel(&ltq_ebu_regs->con_1, EBU_CON_AGEN_DEMUX |\n+\t\t\t\tEBU_CON_SETUP | EBU_CON_WAIT_DIS | EBU_CON_PW_8BIT |\n+\t\t\t\tEBU_CON_ALEC(3) | EBU_CON_BCGEN_INTEL |\n+\t\t\t\tEBU_CON_WAITWRC(2) | EBU_CON_WAITRDC(2) |\n+\t\t\t\tEBU_CON_HOLDC(1) | EBU_CON_RECOVC(1) |\n+\t\t\t\tEBU_CON_CMULT_4);\n+\n+\t\tif (ebu_region0_addrsel_mask == 3)\n+\t\t\tltq_writel(&ltq_ebu_regs->con_1, EBU_CON_AGEN_DEMUX |\n+\t\t\t\tEBU_CON_WAIT_DIS | EBU_CON_PW_16BIT |\n+\t\t\t\tEBU_CON_ALEC(3) | EBU_CON_BCGEN_INTEL |\n+\t\t\t\tEBU_CON_WAITWRC(7) | EBU_CON_WAITRDC(3) |\n+\t\t\t\tEBU_CON_HOLDC(3) | EBU_CON_RECOVC(3) |\n+\t\t\t\tEBU_CON_CMULT_16);\n+\t} else\n+\t\tltq_clrbits(&ltq_ebu_regs->addr_sel_1, EBU_ADDRSEL_REGEN);\n+}\n+\n+void *flash_swap_addr(unsigned long addr)\n+{\n+\treturn (void *)(addr ^ 2);\n+}\n--- /dev/null\n+++ b/arch/mips/cpu/mips32/vrx200/gphy.c\n@@ -0,0 +1,68 @@\n+/*\n+ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#include <common.h>\n+#include <asm/lantiq/io.h>\n+#include <asm/arch/soc.h>\n+#include <asm/arch/gphy.h>\n+#include <lzma/LzmaTypes.h>\n+#include <lzma/LzmaDec.h>\n+#include <lzma/LzmaTools.h>\n+\n+static inline void ltq_gphy_decompress(const void *fw_start, const void *fw_end,\n+\t\t\t\tulong dst_addr)\n+{\n+\tconst ulong fw_len = (ulong) fw_end - (ulong) fw_start;\n+\tconst ulong addr = CKSEG1ADDR(dst_addr);\n+\n+\tdebug(\"ltq_gphy_decompress: addr %08lx, fw_start %p, fw_end %p\\n\",\n+\t\taddr, fw_start, fw_end);\n+\n+\tSizeT lzma_len = 65536;\n+\tint ret = lzmaBuffToBuffDecompress(\n+\t(unsigned char *)addr, &lzma_len,\n+\t(unsigned char *)fw_start, fw_len);\n+}\n+\n+void ltq_gphy_phy11g_a1x_load(ulong addr)\n+{\n+\textern ulong __ltq_fw_phy11g_a1x_start;\n+\textern ulong __ltq_fw_phy11g_a1x_end;\n+\n+\tltq_gphy_decompress(&__ltq_fw_phy11g_a1x_start,\n+\t\t\t    &__ltq_fw_phy11g_a1x_end,\n+\t\t\t    addr);\n+}\n+\n+void ltq_gphy_phy11g_a2x_load(ulong addr)\n+{\n+\textern ulong __ltq_fw_phy11g_a2x_start;\n+\textern ulong __ltq_fw_phy11g_a2x_end;\n+\n+\tltq_gphy_decompress(&__ltq_fw_phy11g_a2x_start,\n+\t\t\t    &__ltq_fw_phy11g_a2x_end,\n+\t\t\t    addr);\n+}\n+\n+void ltq_gphy_phy22f_a1x_load(ulong addr)\n+{\n+\textern ulong __ltq_fw_phy22f_a1x_start;\n+\textern ulong __ltq_fw_phy22f_a1x_end;\n+\n+\tltq_gphy_decompress(&__ltq_fw_phy22f_a1x_start,\n+\t\t\t    &__ltq_fw_phy22f_a1x_end,\n+\t\t\t    addr);\n+}\n+\n+void ltq_gphy_phy22f_a2x_load(ulong addr)\n+{\n+\textern ulong __ltq_fw_phy22f_a2x_start;\n+\textern ulong __ltq_fw_phy22f_a2x_end;\n+\n+\tltq_gphy_decompress(&__ltq_fw_phy22f_a2x_start,\n+\t\t\t    &__ltq_fw_phy22f_a2x_end,\n+\t\t\t    addr);\n+}\n--- /dev/null\n+++ b/arch/mips/cpu/mips32/vrx200/gphy_fw.S\n@@ -0,0 +1,27 @@\n+/*\n+ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#include <asm/asm.h>\n+\n+\t.section .rodata.__ltq_fw_phy11g_a1x\n+EXPORT(__ltq_fw_phy11g_a1x_start)\n+\t.incbin \"fw_phy11g_a1x.blob\"\n+EXPORT(__ltq_fw_phy11g_a1x_end)\n+\n+\t.section .rodata.__ltq_fw_phy11g_a2x\n+EXPORT(__ltq_fw_phy11g_a2x_start)\n+\t.incbin \"fw_phy11g_a2x.blob\"\n+EXPORT(__ltq_fw_phy11g_a2x_end)\n+\n+\t.section .rodata.__ltq_fw_phy22f_a1x\n+EXPORT(__ltq_fw_phy22f_a1x_start)\n+\t.incbin \"fw_phy22f_a1x.blob\"\n+EXPORT(__ltq_fw_phy22f_a1x_end)\n+\n+\t.section .rodata.__ltq_fw_phy22f_a2x\n+EXPORT(__ltq_fw_phy22f_a2x_start)\n+\t.incbin \"fw_phy22f_a2x.blob\"\n+EXPORT(__ltq_fw_phy22f_a2x_end)\n--- /dev/null\n+++ b/arch/mips/cpu/mips32/vrx200/mem.c\n@@ -0,0 +1,57 @@\n+/*\n+ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#include <common.h>\n+#include <asm/arch/soc.h>\n+#include <asm/lantiq/io.h>\n+\n+#define LTQ_CCR03_EIGHT_BANK_MODE\t(1 << 0)\n+#define LTQ_CCR08_CS_MAP_SHIFT\t\t24\n+#define LTQ_CCR08_CS_MAP_MASK\t\t(0x3 << LTQ_CCR08_CS_MAP_SHIFT)\n+#define LTQ_CCR11_COLUMN_SIZE_SHIFT\t24\n+#define LTQ_CCR11_COLUMN_SIZE_MASK\t(0x7 << LTQ_CCR11_COLUMN_SIZE_SHIFT)\n+#define LTQ_CCR11_ADDR_PINS_MASK\t0x7\n+#define LTQ_CCR15_MAX_COL_REG_SHIFT\t24\n+#define LTQ_CCR15_MAX_COL_REG_MASK\t(0xF << LTQ_CCR15_MAX_COL_REG_SHIFT)\n+#define LTQ_CCR16_MAX_ROW_REG_MASK\t0xF\n+\n+static void *ltq_mc_ddr_base = (void *) CKSEG1ADDR(LTQ_MC_DDR_BASE);\n+\n+static inline u32 ltq_mc_ccr_read(u32 index)\n+{\n+\treturn ltq_readl(ltq_mc_ddr_base + LTQ_MC_DDR_CCR_OFFSET(index));\n+}\n+\n+phys_size_t initdram(int board_type)\n+{\n+\tu32 max_col_reg, max_row_reg, column_size, addr_pins;\n+\tu32 banks, cs_map;\n+\tphys_size_t size;\n+\n+\tbanks = (ltq_mc_ccr_read(3) & LTQ_CCR03_EIGHT_BANK_MODE) ? 8 : 4;\n+\n+\tcs_map = (ltq_mc_ccr_read(8) & LTQ_CCR08_CS_MAP_MASK) >>\n+\t\tLTQ_CCR08_CS_MAP_SHIFT;\n+\n+\tcolumn_size = (ltq_mc_ccr_read(11) & LTQ_CCR11_COLUMN_SIZE_MASK) >>\n+\t\tLTQ_CCR11_COLUMN_SIZE_SHIFT;\n+\n+\taddr_pins = ltq_mc_ccr_read(11) & LTQ_CCR11_ADDR_PINS_MASK;\n+\n+\tmax_col_reg = (ltq_mc_ccr_read(15) & LTQ_CCR15_MAX_COL_REG_MASK) >>\n+\t\tLTQ_CCR15_MAX_COL_REG_SHIFT;\n+\n+\tmax_row_reg = ltq_mc_ccr_read(16) & LTQ_CCR16_MAX_ROW_REG_MASK;\n+\n+\t/*\n+\t * size (bytes) = 2 ^ rowsize * 2 ^ colsize * banks * chipselects\n+\t *                 * datawidth (bytes)\n+\t */\n+\tsize = (2 << (max_col_reg - column_size - 1)) *\n+\t\t(2 << (max_row_reg - addr_pins - 1)) * banks * cs_map * 2;\n+\n+\treturn size;\n+}\n--- /dev/null\n+++ b/arch/mips/cpu/mips32/vrx200/mem_init.S\n@@ -0,0 +1,233 @@\n+/*\n+ * Copyright (C) 2010 Lantiq Deutschland GmbH\n+ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#include <config.h>\n+#include <asm/asm.h>\n+#include <asm/regdef.h>\n+#include <asm/addrspace.h>\n+#include <asm/arch/soc.h>\n+\n+/* Must be configured in BOARDDIR */\n+#include <ddr_settings.h>\n+\n+#define LTQ_MC_DDR_START\t\t(1 << 8)\n+#define LTQ_MC_DDR_DLL_LOCK_IND\t1\n+\n+#define CCS_ALWAYS_LAST\t\t\t0x0430\n+#define CCS_AHBM_CR_BURST_EN\t\t(1 << 2)\n+#define CCS_FPIM_CR_BURST_EN\t\t(1 << 1)\n+\n+#define CCR03_EIGHT_BANK_MODE\t\t(1 << 0)\n+\n+\t/* Store given value in MC DDR CCRx register */\n+\t.macro ccr_sw num, val\n+\tli\tt1, \\val\n+\tsw\tt1, LTQ_MC_DDR_CCR_OFFSET(\\num)(t0)\n+\t.endm\n+\n+LEAF(ltq_mem_init)\n+\t/* Load MC DDR module base */\n+\tli\tt0, (LTQ_MC_DDR_BASE | KSEG1)\n+\n+\t/* Put memory controller in inactive mode */\n+\tsw\tzero, LTQ_MC_DDR_CCR_OFFSET(7)(t0)\n+\n+\t/* Init MC DDR CCR registers with values from ddr_settings.h */\n+\tccr_sw\t0, MC_CCR00_VALUE\n+\tccr_sw\t1, MC_CCR01_VALUE\n+\tccr_sw\t2, MC_CCR02_VALUE\n+\tccr_sw\t3, MC_CCR03_VALUE\n+\tccr_sw\t4, MC_CCR04_VALUE\n+\tccr_sw\t5, MC_CCR05_VALUE\n+\tccr_sw\t6, MC_CCR06_VALUE\n+\tccr_sw\t7, MC_CCR07_VALUE\n+\tccr_sw\t8, MC_CCR08_VALUE\n+\tccr_sw\t9, MC_CCR09_VALUE\n+\n+\tccr_sw\t10, MC_CCR10_VALUE\n+\tccr_sw\t11, MC_CCR11_VALUE\n+\tccr_sw\t12, MC_CCR12_VALUE\n+\tccr_sw\t13, MC_CCR13_VALUE\n+\tccr_sw\t14, MC_CCR14_VALUE\n+\tccr_sw\t15, MC_CCR15_VALUE\n+\tccr_sw\t16, MC_CCR16_VALUE\n+\tccr_sw\t17, MC_CCR17_VALUE\n+\tccr_sw\t18, MC_CCR18_VALUE\n+\tccr_sw\t19, MC_CCR19_VALUE\n+\n+\tccr_sw\t20, MC_CCR20_VALUE\n+\tccr_sw\t21, MC_CCR21_VALUE\n+\tccr_sw\t22, MC_CCR22_VALUE\n+\tccr_sw\t23, MC_CCR23_VALUE\n+\tccr_sw\t24, MC_CCR24_VALUE\n+\tccr_sw\t25, MC_CCR25_VALUE\n+\tccr_sw\t26, MC_CCR26_VALUE\n+\tccr_sw\t27, MC_CCR27_VALUE\n+\tccr_sw\t28, MC_CCR28_VALUE\n+\tccr_sw\t29, MC_CCR29_VALUE\n+\n+\tccr_sw\t30, MC_CCR30_VALUE\n+\tccr_sw\t31, MC_CCR31_VALUE\n+\tccr_sw\t32, MC_CCR32_VALUE\n+\tccr_sw\t33, MC_CCR33_VALUE\n+\tccr_sw\t34, MC_CCR34_VALUE\n+\tccr_sw\t35, MC_CCR35_VALUE\n+\tccr_sw\t36, MC_CCR36_VALUE\n+\tccr_sw\t37, MC_CCR37_VALUE\n+\tccr_sw\t38, MC_CCR38_VALUE\n+\tccr_sw\t39, MC_CCR39_VALUE\n+\n+\tccr_sw\t40, MC_CCR40_VALUE\n+\tccr_sw\t41, MC_CCR41_VALUE\n+\tccr_sw\t42, MC_CCR42_VALUE\n+\tccr_sw\t43, MC_CCR43_VALUE\n+\tccr_sw\t44, MC_CCR44_VALUE\n+\tccr_sw\t45, MC_CCR45_VALUE\n+\tccr_sw\t46, MC_CCR46_VALUE\n+\n+\tccr_sw\t52, MC_CCR52_VALUE\n+\tccr_sw\t53, MC_CCR53_VALUE\n+\tccr_sw\t54, MC_CCR54_VALUE\n+\tccr_sw\t55, MC_CCR55_VALUE\n+\tccr_sw\t56, MC_CCR56_VALUE\n+\tccr_sw\t57, MC_CCR57_VALUE\n+\tccr_sw\t58, MC_CCR58_VALUE\n+\tccr_sw\t59, MC_CCR59_VALUE\n+\n+\tccr_sw\t60, MC_CCR60_VALUE\n+\tccr_sw\t61, MC_CCR61_VALUE\n+\n+\t/* Disable bursts between FPI Master bus and XBAR bus */\n+\tli\tt4, (LTQ_MC_GLOBAL_BASE | KSEG1)\n+\tli\tt5, CCS_AHBM_CR_BURST_EN\n+\tsw\tt5, CCS_ALWAYS_LAST(t4)\n+\n+\t/* Init abort condition for DRAM probe */\n+\tmove\tt4, zero\n+\n+\t/*\n+\t * Put memory controller in active mode and start initialitation\n+\t * sequence for connected DDR-SDRAM device\n+\t */\n+mc_start:\n+\tlw\tt1, LTQ_MC_DDR_CCR_OFFSET(7)(t0)\n+\tli\tt2, LTQ_MC_DDR_START\n+\tor\tt1, t1, t2\n+\tsw\tt1, LTQ_MC_DDR_CCR_OFFSET(7)(t0)\n+\n+\t/*\n+\t * Wait until DLL has locked and core is ready for data transfers.\n+\t * DLL lock indication is in register CCR47 and CCR48\n+\t */\n+wait_ready:\n+\tli\tt1, LTQ_MC_DDR_DLL_LOCK_IND\n+\tlw\tt2, LTQ_MC_DDR_CCR_OFFSET(47)(t0)\n+\tand\tt2, t2, t1\n+\tbne\tt1, t2, wait_ready\n+\n+\tlw\tt2, LTQ_MC_DDR_CCR_OFFSET(48)(t0)\n+\tand\tt2, t2, t1\n+\tbne\tt1, t2, wait_ready\n+\n+#ifdef CONFIG_SYS_DRAM_PROBE\n+dram_probe:\n+\t/* Initialization is finished after the second MC start */\n+\tbnez\tt4, mc_finished\n+\n+\t/*\n+\t * Preload register values for CCR03 and CCR11. Initial settings\n+\t * are 8-bank mode enabled, 14 use address row bits, 10 used\n+\t * column address bits.\n+\t */\n+\tli\tt1, CONFIG_SYS_SDRAM_BASE_UC\n+\tli\tt5, MC_CCR03_VALUE\n+\tli\tt6, MC_CCR11_VALUE\n+\taddi\tt4, t4, 1\n+\n+\t/*\n+\t * Store test values to DRAM at offsets 0 and 2^13 (bit 2 in bank select\n+\t * address BA[3]) and read back the value at offset 0. If the resulting\n+\t * value is equal to 1 we can skip to the next test. Otherwise\n+\t * the 8-bank mode does not work with the current DRAM device,\n+\t * thus we need to clear the according bit in register CCR03.\n+\t */\n+\tli\tt2, 1\n+\tsw\tt2, 0x0(t1)\n+\tli\tt3, (1 << 13)\n+\tadd\tt3, t3, t1\n+\tsw\tzero, 0(t3)\n+\tlw\tt3, 0(t1)\n+\tbnez\tt3, row_col_test\n+\n+\t/* Clear CCR03.EIGHT_BANK_MODE */\n+\tli\tt3, ~CCR03_EIGHT_BANK_MODE\n+\tand\tt5, t5, t3\n+\n+row_col_test:\n+\t/*\n+\t * Store test values to DRAM at offsets 0, 2^27 (bit 13 of row address\n+\t * RA[14]) and 2^26 (bit 12 of RA[14]). The chosen test values\n+\t * represent the difference between max. row address bits (14) and used\n+\t * row address bits. Then the read back value at offset 0 indicates\n+\t * the useable row address bits with the current DRAM device. This\n+\t * value must be set in the CCR11 register.\n+\t */\n+\tsw\tzero, 0(t1)\n+\n+\tli\tt2, 1\n+\tli\tt3, (1 << 27)\n+\tadd\tt3, t3, t1\n+\tsw\tt2, 0(t3)\n+\n+\tli\tt2, 2\n+\tli\tt3, (1 << 26)\n+\tadd\tt3, t3, t1\n+\tsw\tt2, 0(t3)\n+\n+\t/* Update CCR11.ADDR_PINS */\n+\tlw\tt3, 0(t1)\n+\tadd\tt6, t6, t3\n+\n+\t/*\n+\t * Store test values to DRAM at offsets 0, 2^10 (bit 9 of column address\n+\t * CA[10]) and 2^9 (bit 8 of CA[10]). The chosen test values represent\n+\t * the difference between max. column address bits (12) and used\n+\t * column address bits. Then the read back value at offset 0 indicates\n+\t * the useable column address bits with the current DRAM device. This\n+\t * value must be set in the CCR11 register.\n+\t */\n+\tsw\tzero, 0(t1)\n+\n+\tli\tt2, 1\n+\tli\tt3, (1 << 10)\n+\tadd\tt3, t3, t1\n+\tsw\tt2, 0(t3)\n+\n+\tli\tt2, 2\n+\tli\tt3, (1 << 9)\n+\tadd\tt3, t3, t1\n+\tsw\tt2, 0(t3)\n+\n+\t/* Update CCR11.COLUMN_SIZE */\n+\tlw\tt3, 0(t1)\n+\tsll\tt3, t3, 24\n+\tadd\tt6, t6, t3\n+\n+\t/* Put memory controller in inactive mode */\n+\tsw\tzero, LTQ_MC_DDR_CCR_OFFSET(7)(t0)\n+\n+\t/* Update CCR03 and CCR11 and restart memory controller initialiation */\n+\tsw\tt5, LTQ_MC_DDR_CCR_OFFSET(3)(t0)\n+\tsw\tt6, LTQ_MC_DDR_CCR_OFFSET(11)(t0)\n+\tb\tmc_start\n+\n+mc_finished:\n+#endif /* CONFIG_SYS_DRAM_PROBE */\n+\n+\tjr\tra\n+\n+\tEND(ltq_mem_init)\n--- /dev/null\n+++ b/arch/mips/cpu/mips32/vrx200/pmu.c\n@@ -0,0 +1,130 @@\n+/*\n+ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#include <common.h>\n+#include <asm/lantiq/io.h>\n+#include <asm/lantiq/pm.h>\n+#include <asm/arch/soc.h>\n+\n+#define LTQ_PMU_PWDCR_RESERVED\t\t((1 << 13) | (1 << 4))\n+\n+#define LTQ_PMU_PWDCR_PCIELOC_EN\t(1 << 31)\n+#define LTQ_PMU_PWDCR_GPHY\t\t(1 << 30)\n+#define LTQ_PMU_PWDCR_PPE_TOP\t\t(1 << 29)\n+#define LTQ_PMU_PWDCR_SWITCH\t\t(1 << 28)\n+#define LTQ_PMU_PWDCR_USB1\t\t(1 << 27)\n+#define LTQ_PMU_PWDCR_USB1_PHY\t\t(1 << 26)\n+#define LTQ_PMU_PWDCR_TDM\t\t(1 << 25)\n+#define LTQ_PMU_PWDCR_PPE_DPLUS\t\t(1 << 24)\n+#define LTQ_PMU_PWDCR_PPE_DPLUM\t\t(1 << 23)\n+#define LTQ_PMU_PWDCR_PPE_EMA\t\t(1 << 22)\n+#define LTQ_PMU_PWDCR_PPE_TC\t\t(1 << 21)\n+#define LTQ_PMU_PWDCR_DEU\t\t(1 << 20)\n+#define LTQ_PMU_PWDCR_PPE_SLL01\t\t(1 << 19)\n+#define LTQ_PMU_PWDCR_PPE_QSB\t\t(1 << 18)\n+#define LTQ_PMU_PWDCR_UART1\t\t(1 << 17)\n+#define LTQ_PMU_PWDCR_SDIO\t\t(1 << 16)\n+#define LTQ_PMU_PWDCR_AHBM\t\t(1 << 15)\n+#define LTQ_PMU_PWDCR_FPIM\t\t(1 << 14)\n+#define LTQ_PMU_PWDCR_GPTC\t\t(1 << 12)\n+#define LTQ_PMU_PWDCR_LEDC\t\t(1 << 11)\n+#define LTQ_PMU_PWDCR_EBU\t\t(1 << 10)\n+#define LTQ_PMU_PWDCR_DSL\t\t(1 << 9)\n+#define LTQ_PMU_PWDCR_SPI\t\t(1 << 8)\n+#define LTQ_PMU_PWDCR_USIF\t\t(1 << 7)\n+#define LTQ_PMU_PWDCR_USB0\t\t(1 << 6)\n+#define LTQ_PMU_PWDCR_DMA\t\t(1 << 5)\n+#define LTQ_PMU_PWDCR_DFEV1\t\t(1 << 3)\n+#define LTQ_PMU_PWDCR_DFEV0\t\t(1 << 2)\n+#define LTQ_PMU_PWDCR_FPIS\t\t(1 << 1)\n+#define LTQ_PMU_PWDCR_USB0_PHY\t\t(1 << 0)\n+\n+struct ltq_pmu_regs {\n+\tu32\trsvd0[7];\n+\tu32\tpwdcr;\t\t/* Power down control */\n+\tu32\tsr;\t\t/* Power down status */\n+\tu32\tpwdcr1;\t\t/* Power down control 1 */\n+\tu32\tsr1;\t\t/* Power down status 1 */\n+};\n+\n+static struct ltq_pmu_regs *ltq_pmu_regs =\n+\t(struct ltq_pmu_regs *) CKSEG1ADDR(LTQ_PMU_BASE);\n+\n+u32 ltq_pm_map(enum ltq_pm_modules module)\n+{\n+\tu32 val;\n+\n+\tswitch (module) {\n+\tcase LTQ_PM_CORE:\n+\t\tval = LTQ_PMU_PWDCR_UART1 | LTQ_PMU_PWDCR_FPIM |\n+\t\t\tLTQ_PMU_PWDCR_LEDC | LTQ_PMU_PWDCR_EBU;\n+\t\tbreak;\n+\tcase LTQ_PM_DMA:\n+\t\tval = LTQ_PMU_PWDCR_DMA;\n+\t\tbreak;\n+\tcase LTQ_PM_ETH:\n+\t\tval = LTQ_PMU_PWDCR_GPHY | LTQ_PMU_PWDCR_PPE_TOP |\n+\t\t\tLTQ_PMU_PWDCR_SWITCH | LTQ_PMU_PWDCR_PPE_DPLUS |\n+\t\t\tLTQ_PMU_PWDCR_PPE_DPLUM | LTQ_PMU_PWDCR_PPE_EMA |\n+\t\t\tLTQ_PMU_PWDCR_PPE_TC | LTQ_PMU_PWDCR_PPE_SLL01 |\n+\t\t\tLTQ_PMU_PWDCR_PPE_QSB;\n+\t\tbreak;\n+\tcase LTQ_PM_SPI:\n+\t\tval = LTQ_PMU_PWDCR_SPI;\n+\t\tbreak;\n+\tdefault:\n+\t\tval = 0;\n+\t\tbreak;\n+\t}\n+\n+\treturn val;\n+}\n+\n+int ltq_pm_enable(enum ltq_pm_modules module)\n+{\n+\tconst unsigned long timeout = 1000;\n+\tunsigned long timebase;\n+\tu32 sr, val;\n+\n+\tval = ltq_pm_map(module);\n+\tif (unlikely(!val))\n+\t\treturn 1;\n+\n+\tltq_clrbits(&ltq_pmu_regs->pwdcr, val);\n+\n+\ttimebase = get_timer(0);\n+\n+\tdo {\n+\t\tsr = ltq_readl(&ltq_pmu_regs->sr);\n+\t\tif (~sr & val)\n+\t\t\treturn 0;\n+\t} while (get_timer(timebase) < timeout);\n+\n+\treturn 1;\n+}\n+\n+int ltq_pm_disable(enum ltq_pm_modules module)\n+{\n+\tu32 val;\n+\n+\tval = ltq_pm_map(module);\n+\tif (unlikely(!val))\n+\t\treturn 1;\n+\n+\tltq_setbits(&ltq_pmu_regs->pwdcr, val);\n+\n+\treturn 0;\n+}\n+\n+void ltq_pmu_init(void)\n+{\n+\tu32 set, clr;\n+\n+\tclr = ltq_pm_map(LTQ_PM_CORE);\n+\tset = ~(LTQ_PMU_PWDCR_RESERVED | clr);\n+\n+\tltq_clrsetbits(&ltq_pmu_regs->pwdcr, clr, set);\n+}\n--- /dev/null\n+++ b/arch/mips/cpu/mips32/vrx200/rcu.c\n@@ -0,0 +1,194 @@\n+/*\n+ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#include <common.h>\n+#include <asm/lantiq/io.h>\n+#include <asm/lantiq/reset.h>\n+#include <asm/lantiq/cpu.h>\n+#include <asm/arch/soc.h>\n+\n+#define LTQ_RCU_RD_GPHY0\t(1 << 31)\t/* GPHY0 */\n+#define LTQ_RCU_RD_SRST\t\t(1 << 30)\t/* Global SW Reset */\n+#define LTQ_RCU_RD_GPHY1\t(1 << 29)\t/* GPHY1 */\n+#define LTQ_RCU_RD_ENMIP2\t(1 << 28)\t/* Enable NMI of PLL2 */\n+#define LTQ_RCU_RD_REG25_PD\t(1 << 26)\t/* Power down 2.5V regulator */\n+#define LTQ_RCU_RD_ENDINIT\t(1 << 25)\t/* FPI slave bus access */\n+#define LTQ_RCU_RD_PPE_ATM_TC\t(1 << 23)\t/* PPE ATM TC */\n+#define LTQ_RCU_RD_PCIE\t\t(1 << 22)\t/* PCI-E core */\n+#define LTQ_RCU_RD_ETHSW\t(1 << 21)\t/* Ethernet switch */\n+#define LTQ_RCU_RD_DSP_DEN\t(1 << 20)\t/* Enable DSP JTAG */\n+#define LTQ_RCU_RD_TDM\t\t(1 << 19)\t/* TDM module interface */\n+#define LTQ_RCU_RD_ENMIP1\t(1 << 18)\t/* Enable NMI of PLL1 */\n+#define LTQ_RCU_RD_SWBCK\t(1 << 17)\t/* Switch backward compat */\n+#define LTQ_RCU_RD_HSNAND\t(1 << 16)\t/* HSNAND controller */\n+#define LTQ_RCU_RD_ENMIP0\t(1 << 15)\t/* Enable NMI of PLL0 */\n+#define LTQ_RCU_RD_MC\t\t(1 << 14)\t/* Memory Controller */\n+#define LTQ_RCU_RD_PCI\t\t(1 << 13)\t/* PCI core */\n+#define LTQ_RCU_RD_PCIE_PHY\t(1 << 12)\t/* PCI-E Phy */\n+#define LTQ_RCU_RD_DFE_CORE\t(1 << 11)\t/* DFE core */\n+#define LTQ_RCU_RD_SDIO\t\t(1 << 10)\t/* SDIO core */\n+#define LTQ_RCU_RD_DMA\t\t(1 << 9)\t/* DMA core */\n+#define LTQ_RCU_RD_PPE\t\t(1 << 8)\t/* PPE core */\n+#define LTQ_RCU_RD_DFE\t\t(1 << 7)\t/* DFE core */\n+#define LTQ_RCU_RD_AHB\t\t(1 << 6)\t/* AHB bus */\n+#define LTQ_RCU_RD_HRST_CFG\t(1 << 5)\t/* HW reset configuration */\n+#define LTQ_RCU_RD_USB\t\t(1 << 4)\t/* USB and Phy core */\n+#define LTQ_RCU_RD_PPE_DSP\t(1 << 3)\t/* PPE DSP interface */\n+#define LTQ_RCU_RD_FPI\t\t(1 << 2)\t/* FPI bus */\n+#define LTQ_RCU_RD_CPU\t\t(1 << 1)\t/* CPU subsystem */\n+#define LTQ_RCU_RD_HRST\t\t(1 << 0)\t/* HW reset via HRST pin */\n+\n+#define LTQ_RCU_STAT_BOOT_SHIFT\t\t17\n+#define LTQ_RCU_STAT_BOOT_MASK\t\t(0xF << LTQ_RCU_STAT_BOOT_SHIFT)\n+#define LTQ_RCU_STAT_BOOT_H\t\t(1 << 12)\n+\n+#define LTQ_RCU_GP_STRAP_CLOCKSOURCE\t(1 << 15)\n+\n+struct ltq_rcu_regs {\n+\tu32\trsvd0[4];\n+\tu32\treq;\t\t/* Reset request */\n+\tu32\tstat;\t\t/* Reset status */\n+\tu32\tusb0_cfg;\t/* USB0 configure */\n+\tu32\tgp_strap;\t/* GPIO strapping */\n+\tu32\tgfs_add0;\t/* GPHY0 firmware base addr */\n+\tu32\tstat2;\t\t/* SLIC and USB reset status */\n+\tu32\tpci_rdy;\t/* PCI boot ready */\n+\tu32\tppe_conf;\t/* PPE ethernet config */\n+\tu32\tpcie_phy_con;\t/* PCIE PHY config/status */\n+\tu32\tusb1_cfg;\t/* USB1 configure */\n+\tu32\tusb_ana_cfg1a;\t/* USB analog config 1a */\n+\tu32\tusb_ana_cfg1b;\t/* USB analog config 1b */\n+\tu32\trsvd1;\n+\tu32\tgf_mdio_add;\t/* GPHY0/1 MDIO address */\n+\tu32\treq2;\t\t/* SLIC and USB reset request */\n+\tu32\tahb_endian;\t/* AHB bus endianess */\n+\tu32\trsvd2[4];\n+\tu32\tgcc;\t\t/* General CPU config */\n+\tu32\trsvd3;\n+\tu32\tgfs_add1;\t/* GPHY1 firmware base addr */\n+};\n+\n+static struct ltq_rcu_regs *ltq_rcu_regs =\n+\t(struct ltq_rcu_regs *) CKSEG1ADDR(LTQ_RCU_BASE);\n+\n+u32 ltq_reset_map(enum ltq_reset_modules module)\n+{\n+\tu32 val;\n+\n+\tswitch (module) {\n+\tcase LTQ_RESET_CORE:\n+\tcase LTQ_RESET_SOFT:\n+\t\tval = LTQ_RCU_RD_SRST | LTQ_RCU_RD_CPU | LTQ_RCU_RD_ENMIP2 |\n+\t\t\tLTQ_RCU_RD_GPHY1 | LTQ_RCU_RD_GPHY0;\n+\t\tbreak;\n+\tcase LTQ_RESET_DMA:\n+\t\tval = LTQ_RCU_RD_DMA;\n+\t\tbreak;\n+\tcase LTQ_RESET_ETH:\n+\t\tval = LTQ_RCU_RD_PPE | LTQ_RCU_RD_ETHSW;\n+\t\tbreak;\n+\tcase LTQ_RESET_PHY:\n+\t\tval = LTQ_RCU_RD_GPHY1 | LTQ_RCU_RD_GPHY0;\n+\t\tbreak;\n+\tcase LTQ_RESET_HARD:\n+\t\tval = LTQ_RCU_RD_HRST;\n+\t\tbreak;\n+\tdefault:\n+\t\tval = 0;\n+\t\tbreak;\n+\t}\n+\n+\treturn val;\n+}\n+\n+int ltq_reset_activate(enum ltq_reset_modules module)\n+{\n+\tu32 val;\n+\n+\tval = ltq_reset_map(module);\n+\tif (unlikely(!val))\n+\t\treturn 1;\n+\n+\tltq_setbits(&ltq_rcu_regs->req, val);\n+\n+\treturn 0;\n+}\n+\n+int ltq_reset_deactivate(enum ltq_reset_modules module)\n+{\n+\tu32 val;\n+\n+\tval = ltq_reset_map(module);\n+\tif (unlikely(!val))\n+\t\treturn 1;\n+\n+\tltq_clrbits(&ltq_rcu_regs->req, val);\n+\n+\treturn 0;\n+}\n+\n+enum ltq_boot_select ltq_boot_select(void)\n+{\n+\tu32 stat;\n+\tunsigned int bootstrap;\n+\n+\t/*\n+\t * Boot select value is built from bits 20-17 and bit 12.\n+\t * The bit sequence is read as 4-2-1-0-3.\n+\t */\n+\tstat = ltq_readl(&ltq_rcu_regs->stat);\n+\tbootstrap = ((stat & LTQ_RCU_STAT_BOOT_H) << 4) |\n+\t\t((stat & LTQ_RCU_STAT_BOOT_MASK) >> LTQ_RCU_STAT_BOOT_SHIFT);\n+\n+\tswitch (bootstrap) {\n+\tcase 0:\n+\t\treturn BOOT_NOR_NO_BOOTROM;\n+\tcase 1:\n+\t\treturn BOOT_RGMII1;\n+\tcase 2:\n+\t\treturn BOOT_NOR;\n+\tcase 4:\n+\t\treturn BOOT_UART_NO_EEPROM;\n+\tcase 6:\n+\t\treturn BOOT_PCI;\n+\tcase 8:\n+\t\treturn BOOT_UART;\n+\tcase 10:\n+\t\treturn BOOT_SPI;\n+\tcase 12:\n+\t\treturn BOOT_NAND;\n+\tdefault:\n+\t\treturn BOOT_UNKNOWN;\n+\t}\n+}\n+\n+void ltq_rcu_gphy_boot(unsigned int id, ulong addr)\n+{\n+\tu32 module;\n+\tvoid *gfs_add;\n+\n+\tswitch (id) {\n+\tcase 0:\n+\t\tmodule = LTQ_RCU_RD_GPHY0;\n+\t\tgfs_add = &ltq_rcu_regs->gfs_add0;\n+\t\tbreak;\n+\tcase 1:\n+\t\tmodule = LTQ_RCU_RD_GPHY1;\n+\t\tgfs_add = &ltq_rcu_regs->gfs_add1;\n+\t\tbreak;\n+\tdefault:\n+\t\tBUG();\n+\t}\n+\n+\t/* Stop and reset GPHY */\n+\tltq_setbits(&ltq_rcu_regs->req, module);\n+\n+\t/* Configure firmware and boot address */\n+\tltq_writel(gfs_add, CPHYSADDR(addr & 0xFFFFC000));\n+\n+\t/* Start GPHY by releasing reset */\n+\tltq_clrbits(&ltq_rcu_regs->req, module);\n+}\n--- /dev/null\n+++ b/arch/mips/include/asm/arch-danube/config.h\n@@ -0,0 +1,164 @@\n+/*\n+ * Copyright (C) 2007-2010 Lantiq Deutschland GmbH\n+ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ *\n+ * Common board configuration for Lantiq XWAY Danube family\n+ *\n+ * Use following defines in your board config to enable specific features\n+ * and drivers for this SoC:\n+ *\n+ * CONFIG_LTQ_SUPPORT_UART\n+ * - support the Danube ASC/UART interface and console\n+ *\n+ * CONFIG_LTQ_SUPPORT_NOR_FLASH\n+ * - support a parallel NOR flash via the CFI interface in flash bank 0\n+ *\n+ * CONFIG_LTQ_SUPPORT_ETHERNET\n+ * - support the Danube ETOP and MAC interface\n+ *\n+ * CONFIG_LTQ_SUPPORT_SPI_FLASH\n+ * - support the Danube SPI interface and serial flash drivers\n+ * - specific SPI flash drivers must be configured separately\n+ */\n+\n+#ifndef __DANUBE_CONFIG_H__\n+#define __DANUBE_CONFIG_H__\n+\n+/* CPU and SoC type */\n+#define CONFIG_SOC_LANTIQ\n+#define CONFIG_SOC_XWAY_DANUBE\n+\n+/* Cache configuration */\n+#define CONFIG_SYS_MIPS_CACHE_MODE\tCONF_CM_CACHABLE_NONCOHERENT\n+#define CONFIG_SYS_DCACHE_SIZE\t\t(16 * 1024)\n+#define CONFIG_SYS_ICACHE_SIZE\t\t(16 * 1024)\n+#define CONFIG_SYS_CACHELINE_SIZE\t32\n+#define CONFIG_SYS_MIPS_CACHE_EXT_INIT\n+\n+/*\n+ * Supported clock modes\n+ * PLL0 clock output is 333 MHz\n+ * PLL1 clock output is 262.144 MHz\n+ */\n+#define LTQ_CLK_CPU_333_DDR_167\t\t0\t/* Base PLL0, OCP 2 */\n+#define LTQ_CLK_CPU_111_DDR_111\t\t1\t/* Base PLL0, OCP 1 */\n+\n+/* CPU speed */\n+#define CONFIG_SYS_CLOCK_MODE\t\tLTQ_CLK_CPU_333_DDR_167\n+#define CONFIG_SYS_MIPS_TIMER_FREQ\t166666667\n+#define CONFIG_SYS_HZ\t\t\t1000\n+\n+/* RAM */\n+#define CONFIG_NR_DRAM_BANKS\t\t1\n+#define CONFIG_SYS_SDRAM_BASE\t\t0x80000000\n+#define CONFIG_SYS_MEMTEST_START\t0x81000000\n+#define CONFIG_SYS_MEMTEST_END\t\t0x82000000\n+#define CONFIG_SYS_LOAD_ADDR\t\t0x81000000\n+#define CONFIG_SYS_LOAD_SIZE\t\t(2 * 1024 * 1024)\n+#define CONFIG_SYS_INIT_SP_OFFSET\t0x4000\n+\n+/* SRAM */\n+#define CONFIG_SYS_SRAM_BASE\t\t0xBE1A0000\n+#define CONFIG_SYS_SRAM_SIZE\t\t0x10000\n+\n+/* ASC/UART driver and console */\n+#define CONFIG_LANTIQ_SERIAL\n+#define CONFIG_SYS_BAUDRATE_TABLE\t{ 9600, 19200, 38400, 57600, 115200 }\n+\n+/* GPIO */\n+#define CONFIG_LANTIQ_GPIO\n+#define CONFIG_LTQ_GPIO_MAX_BANKS\t2\n+\n+/* FLASH driver */\n+#if defined(CONFIG_LTQ_SUPPORT_NOR_FLASH)\n+#define CONFIG_SYS_MAX_FLASH_BANKS\t1\n+#define CONFIG_SYS_MAX_FLASH_SECT\t256\n+#define CONFIG_SYS_FLASH_BASE\t\t0xB0000000\n+#define CONFIG_FLASH_16BIT\n+#define CONFIG_SYS_FLASH_CFI\n+#define CONFIG_FLASH_CFI_DRIVER\n+#define CONFIG_SYS_FLASH_CFI_WIDTH\tFLASH_CFI_16BIT\n+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE\n+#define CONFIG_FLASH_SHOW_PROGRESS\t50\n+#define CONFIG_SYS_FLASH_PROTECTION\n+#define CONFIG_CFI_FLASH_USE_WEAK_ADDR_SWAP\n+\n+#define CONFIG_CMD_FLASH\n+#else\n+#define CONFIG_SYS_NO_FLASH\n+#endif /* CONFIG_NOR_FLASH */\n+\n+#if defined(CONFIG_LTQ_SUPPORT_SPI_FLASH)\n+#define CONFIG_LANTIQ_SPI\n+#define CONFIG_SPI_FLASH\n+\n+#define CONFIG_CMD_SF\n+#define CONFIG_CMD_SPI\n+#endif\n+\n+#if defined(CONFIG_LTQ_SUPPORT_NAND_FLASH)\n+#define CONFIG_NAND_LANTIQ\n+#define CONFIG_SYS_MAX_NAND_DEVICE\t1\n+#define CONFIG_SYS_NAND_BASE\t\t0xB4000000\n+\n+#define CONFIG_CMD_NAND\n+#endif\n+\n+#if defined(CONFIG_LTQ_SUPPORT_ETHERNET)\n+#define CONFIG_LANTIQ_DMA\n+#define CONFIG_LANTIQ_DANUBE_ETOP\n+\n+#define CONFIG_PHYLIB\n+#define CONFIG_MII\n+\n+#define CONFIG_CMD_MII\n+#define CONFIG_CMD_NET\n+#endif\n+\n+#define CONFIG_SPL_MAX_SIZE\t\t(32 * 1024)\n+#define CONFIG_SPL_BSS_MAX_SIZE\t\t(8 * 1024)\n+#define CONFIG_SPL_STACK_MAX_SIZE\t(8 * 1024)\n+#define CONFIG_SPL_MALLOC_MAX_SIZE\t(32 * 1024)\n+/*#define CONFIG_SPL_STACK_BSS_IN_SRAM*/\n+\n+#if defined(CONFIG_SPL_STACK_BSS_IN_SRAM)\n+#define CONFIG_SPL_STACK_BASE\t\t(CONFIG_SYS_SRAM_BASE + \\\n+\t\t\t\t\tCONFIG_SPL_MAX_SIZE + \\\n+\t\t\t\t\tCONFIG_SPL_STACK_MAX_SIZE - 1)\n+#define CONFIG_SPL_BSS_BASE\t  \t(CONFIG_SPL_STACK_BASE + 1)\n+#define CONFIG_SPL_MALLOC_BASE\t\t(CONFIG_SYS_SDRAM_BASE + \\\n+\t\t\t\t\tCONFIG_SYS_INIT_SP_OFFSET)\n+#else\n+#define CONFIG_SPL_STACK_BASE\t\t(CONFIG_SYS_SDRAM_BASE + \\\n+\t\t\t\t\tCONFIG_SYS_INIT_SP_OFFSET + \\\n+\t\t\t\t\tCONFIG_SPL_STACK_MAX_SIZE - 1)\n+#define CONFIG_SPL_BSS_BASE\t\t(CONFIG_SPL_STACK_BASE + 1)\n+#define CONFIG_SPL_MALLOC_BASE\t\t(CONFIG_SPL_BSS_BASE + \\\n+\t\t\t\t\tCONFIG_SPL_BSS_MAX_SIZE)\n+#endif\n+\n+#if defined(CONFIG_SYS_BOOT_RAM)\n+#define CONFIG_SYS_TEXT_BASE\t\t0xa0100000\n+#define CONFIG_SKIP_LOWLEVEL_INIT\n+#define CONFIG_SYS_DISABLE_CACHE\n+#endif\n+\n+#if defined(CONFIG_SYS_BOOT_NOR)\n+#define CONFIG_SYS_TEXT_BASE\t\t0xB0000000\n+#endif\n+\n+#if defined(CONFIG_SYS_BOOT_NORSPL)\n+#define CONFIG_SYS_TEXT_BASE\t\t0x80100000\n+#define CONFIG_SPL_TEXT_BASE\t\t0xB0000000\n+#endif\n+\n+#if defined(CONFIG_SYS_BOOT_NOR) || defined(CONFIG_SYS_BOOT_NORSPL)\n+#define CONFIG_SYS_XWAY_EBU_BOOTCFG\t0x688C688C\n+#define CONFIG_XWAY_SWAP_BYTES\n+#endif\n+\n+#define\tCONFIG_SYS_MONITOR_BASE\t\tCONFIG_SYS_TEXT_BASE\n+\n+#endif /* __DANUBE_CONFIG_H__ */\n--- /dev/null\n+++ b/arch/mips/include/asm/arch-danube/gpio.h\n@@ -0,0 +1,12 @@\n+/*\n+ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#ifndef __DANUBE_GPIO_H__\n+#define __DANUBE_GPIO_H__\n+\n+#include <asm/lantiq/gpio.h>\n+\n+#endif /* __DANUBE_GPIO_H__ */\n--- /dev/null\n+++ b/arch/mips/include/asm/arch-danube/nand.h\n@@ -0,0 +1,13 @@\n+/*\n+ * Copyright (C) 2012-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#ifndef __DANUBE_NAND_H__\n+#define __DANUBE_NAND_H__\n+\n+struct nand_chip;\n+int ltq_nand_init(struct nand_chip *nand);\n+\n+#endif /* __DANUBE_NAND_H__ */\n--- /dev/null\n+++ b/arch/mips/include/asm/arch-danube/soc.h\n@@ -0,0 +1,38 @@\n+/*\n+ * Copyright (C) 2007-2010 Lantiq Deutschland GmbH\n+ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#ifndef __DANUBE_SOC_H__\n+#define __DANUBE_SOC_H__\n+\n+#define LTQ_ASC0_BASE\t\t\t0x1E100400\n+#define LTQ_SPI_BASE\t\t\t0x1E100800\n+#define LTQ_GPIO_BASE\t\t\t0x1E100B00\n+#define LTQ_SSIO_BASE\t\t\t0x1E100BB0\n+#define LTQ_ASC1_BASE\t\t\t0x1E100C00\n+#define LTQ_DMA_BASE\t\t\t0x1E104100\n+\n+#define LTQ_EBU_BASE\t\t\t0x1E105300\n+#define LTQ_EBU_REGION0_BASE\t\t0x10000000\n+#define LTQ_EBU_REGION1_BASE\t\t0x14000000\n+#define LTQ_EBU_NAND_BASE\t\t(LTQ_EBU_BASE + 0xB0)\n+\n+#define LTQ_PPE_BASE\t\t\t0x1E180000\n+#define LTQ_PPE_ETOP_BASE\t\t(LTQ_PPE_BASE + 0x11800)\n+#define LTQ_PPE_ENET0_BASE\t\t(LTQ_PPE_BASE + 0x11840)\n+\n+#define LTQ_PMU_BASE\t\t\t0x1F102000\n+#define LTQ_CGU_BASE\t\t\t0x1F103000\n+#define LTQ_MPS_BASE\t\t\t0x1F107000\n+#define LTQ_CHIPID_BASE\t\t\t(LTQ_MPS_BASE + 0x340)\n+#define LTQ_RCU_BASE\t\t\t0x1F203000\n+\n+#define LTQ_MC_GEN_BASE\t\t\t0x1F800000\n+#define LTQ_MC_SDR_BASE\t\t\t0x1F800200\n+#define LTQ_MC_DDR_BASE\t\t\t0x1F801000\n+#define LTQ_MC_DDR_DC_OFFSET(x)\t\t(x * 0x10)\n+\n+#endif /* __DANUBE_SOC_H__ */\n--- /dev/null\n+++ b/arch/mips/include/asm/arch-vrx200/config.h\n@@ -0,0 +1,188 @@\n+/*\n+ * Copyright (C) 2010 Lantiq Deutschland GmbH\n+ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ *\n+ * Common board configuration for Lantiq XWAY VRX200 family\n+ *\n+ * Use following defines in your board config to enable specific features\n+ * and drivers for this SoC:\n+ *\n+ * CONFIG_LTQ_SUPPORT_UART\n+ * - support the VRX200 ASC/UART interface and console\n+ *\n+ * CONFIG_LTQ_SUPPORT_NOR_FLASH\n+ * - support a parallel NOR flash via the CFI interface in flash bank 0\n+ *\n+ * CONFIG_LTQ_SUPPORT_ETHERNET\n+ * - support the VRX200 internal switch\n+ *\n+ * CONFIG_LTQ_SUPPORT_SPI_FLASH\n+ * - support the VRX200 SPI interface and serial flash drivers\n+ * - specific SPI flash drivers must be configured separately\n+ *\n+ * CONFIG_LTQ_SUPPORT_SPL_SPI_FLASH\n+ * - build a preloader that runs in the internal SRAM and loads\n+ *   the U-Boot from SPI flash into RAM\n+ */\n+\n+#ifndef __VRX200_CONFIG_H__\n+#define __VRX200_CONFIG_H__\n+\n+/* CPU and SoC type */\n+#define CONFIG_SOC_LANTIQ\n+#define CONFIG_SOC_XWAY_VRX200\n+\n+/* Cache configuration */\n+#define CONFIG_SYS_MIPS_CACHE_MODE\tCONF_CM_CACHABLE_NONCOHERENT\n+#define CONFIG_SYS_DCACHE_SIZE\t\t(32 * 1024)\n+#define CONFIG_SYS_ICACHE_SIZE\t\t(32 * 1024)\n+#define CONFIG_SYS_CACHELINE_SIZE\t32\n+#define CONFIG_SYS_MIPS_CACHE_EXT_INIT\n+\n+/*\n+ * Supported clock modes\n+ * PLL0 clock output is 1000 MHz\n+ * PLL1 clock output is 393.219 MHz\n+ */\n+#define LTQ_CLK_CPU_600_DDR_300\t0\t/* Base PLL0, OCP 2 */\n+#define LTQ_CLK_CPU_600_DDR_200\t1\t/* Base PLL0, OCP 3 */\n+#define LTQ_CLK_CPU_500_DDR_250\t2\t/* Base PLL0, OCP 2 */\n+#define LTQ_CLK_CPU_500_DDR_200\t3\t/* Base PLL0, OCP 2.5 */\n+#define LTQ_CLK_CPU_333_DDR_167\t4\t/* Base PLL0, OCP 2 */\n+#define LTQ_CLK_CPU_167_DDR_167\t5\t/* Base PLL0, OCP 1 */\n+#define LTQ_CLK_CPU_125_DDR_125\t6\t/* Base PLL0, OCP 1 */\n+#define LTQ_CLK_CPU_393_DDR_197\t7\t/* Base PLL1, OCP 2 */\n+#define LTQ_CLK_CPU_197_DDR_197\t8\t/* Base PLL1, OCP 1 */\n+\n+/* CPU speed */\n+#define CONFIG_SYS_CLOCK_MODE\t\tLTQ_CLK_CPU_500_DDR_250\n+#define CONFIG_SYS_MIPS_TIMER_FREQ\t250000000\n+#define CONFIG_SYS_HZ\t\t\t1000\n+\n+/* RAM */\n+#define CONFIG_NR_DRAM_BANKS\t\t1\n+#define CONFIG_SYS_SDRAM_BASE\t\t0x80000000\n+#define CONFIG_SYS_SDRAM_BASE_UC\t0xa0000000\n+#define CONFIG_SYS_MEMTEST_START\t0x81000000\n+#define CONFIG_SYS_MEMTEST_END\t\t0x82000000\n+#define CONFIG_SYS_LOAD_ADDR\t\t0x81000000\n+#define CONFIG_SYS_LOAD_SIZE\t\t(2 * 1024 * 1024)\n+#define CONFIG_SYS_INIT_SP_OFFSET\t(32 * 1024)\n+\n+/* SRAM */\n+#define CONFIG_SYS_SRAM_BASE\t\t0xBE220000\n+#define CONFIG_SYS_SRAM_SIZE\t\t0x10000\n+\n+/* ASC/UART driver and console */\n+#define CONFIG_LANTIQ_SERIAL\n+#define CONFIG_SYS_BAUDRATE_TABLE\t{ 9600, 19200, 38400, 57600, 115200 }\n+\n+/* GPIO */\n+#define CONFIG_LANTIQ_GPIO\n+#define CONFIG_LTQ_GPIO_MAX_BANKS\t3\n+#define CONFIG_LTQ_HAS_GPIO_BANK3\n+\n+/* FLASH driver */\n+#if defined(CONFIG_LTQ_SUPPORT_NOR_FLASH)\n+#ifndef CONFIG_SYS_MAX_FLASH_BANKS\n+#define CONFIG_SYS_MAX_FLASH_BANKS\t1\n+#endif\n+#define CONFIG_SYS_MAX_FLASH_SECT\t256\n+#define CONFIG_SYS_FLASH_BASE\t\t0xB0000000\n+#define CONFIG_SYS_FLASH2_BASE\t\t0xB4000000\n+#define CONFIG_FLASH_16BIT\n+#define CONFIG_SYS_FLASH_CFI\n+#define CONFIG_FLASH_CFI_DRIVER\n+#define CONFIG_SYS_FLASH_CFI_WIDTH\tFLASH_CFI_16BIT\n+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE\n+#define CONFIG_FLASH_SHOW_PROGRESS\t50\n+#define CONFIG_SYS_FLASH_PROTECTION\n+#define CONFIG_CFI_FLASH_USE_WEAK_ADDR_SWAP\n+\n+#define CONFIG_CMD_FLASH\n+#else\n+#define CONFIG_SYS_NO_FLASH\n+#endif /* CONFIG_NOR_FLASH */\n+\n+#if defined(CONFIG_LTQ_SUPPORT_SPI_FLASH)\n+#define CONFIG_LANTIQ_SPI\n+#define CONFIG_SPI_FLASH\n+\n+#define CONFIG_CMD_SF\n+#define CONFIG_CMD_SPI\n+#endif\n+\n+#if defined(CONFIG_LTQ_SUPPORT_NAND_FLASH)\n+#define CONFIG_NAND_LANTIQ\n+#define CONFIG_SYS_MAX_NAND_DEVICE\t1\n+#define CONFIG_SYS_NAND_BASE\t\t0xB4000000\n+\n+#define CONFIG_CMD_NAND\n+#endif\n+\n+#if defined(CONFIG_LTQ_SUPPORT_ETHERNET)\n+#define CONFIG_LANTIQ_DMA\n+#define CONFIG_LANTIQ_VRX200_SWITCH\n+#define CONFIG_PHY_LANTIQ\n+\n+#define CONFIG_SYS_RX_ETH_BUFFER\t8\n+#define CONFIG_PHYLIB\n+#define CONFIG_MII\n+#define CONFIG_UDP_CHECKSUM\n+\n+#define CONFIG_CMD_MII\n+#define CONFIG_CMD_NET\n+#endif\n+\n+#define CONFIG_SPL_MAX_SIZE\t\t(32 * 1024)\n+#define CONFIG_SPL_BSS_MAX_SIZE\t\t(8 * 1024)\n+#define CONFIG_SPL_STACK_MAX_SIZE\t(8 * 1024)\n+#define CONFIG_SPL_MALLOC_MAX_SIZE\t(32 * 1024)\n+#define CONFIG_SPL_STACK_BSS_IN_SRAM\n+\n+#if defined(CONFIG_SPL_STACK_BSS_IN_SRAM)\n+#define CONFIG_SPL_STACK_BASE\t\t(CONFIG_SYS_SRAM_BASE + \\\n+\t\t\t\t\tCONFIG_SPL_MAX_SIZE + \\\n+\t\t\t\t\tCONFIG_SPL_STACK_MAX_SIZE - 1)\n+#define CONFIG_SPL_BSS_BASE\t  \t(CONFIG_SPL_STACK_BASE + 1)\n+#define CONFIG_SPL_MALLOC_BASE\t\t(CONFIG_SYS_SDRAM_BASE + \\\n+\t\t\t\t\tCONFIG_SYS_INIT_SP_OFFSET)\n+#else\n+#define CONFIG_SPL_STACK_BASE\t\t(CONFIG_SYS_SDRAM_BASE + \\\n+\t\t\t\t\tCONFIG_SYS_INIT_SP_OFFSET + \\\n+\t\t\t\t\tCONFIG_SPL_STACK_MAX_SIZE - 1)\n+#define CONFIG_SPL_BSS_BASE\t\t(CONFIG_SPL_STACK_BASE + 1)\n+#define CONFIG_SPL_MALLOC_BASE\t\t(CONFIG_SPL_BSS_BASE + \\\n+\t\t\t\t\tCONFIG_SPL_BSS_MAX_SIZE)\n+#endif\n+\n+#if defined(CONFIG_SYS_BOOT_RAM)\n+#define CONFIG_SYS_TEXT_BASE\t\t0xA0100000\n+#define CONFIG_SKIP_LOWLEVEL_INIT\n+#define CONFIG_SYS_DISABLE_CACHE\n+#endif\n+\n+#if defined(CONFIG_SYS_BOOT_NOR)\n+#define CONFIG_SYS_TEXT_BASE\t\t0xB0000000\n+#endif\n+\n+#if defined(CONFIG_SYS_BOOT_SFSPL)\n+#define CONFIG_SYS_TEXT_BASE\t\t0x80100000\n+#define CONFIG_SPL_TEXT_BASE\t\t0xBE220000\n+#endif\n+\n+#if defined(CONFIG_SYS_BOOT_NORSPL)\n+#define CONFIG_SYS_TEXT_BASE\t\t0x80100000\n+#define CONFIG_SPL_TEXT_BASE\t\t0xB0000000\n+#endif\n+\n+#if defined(CONFIG_SYS_BOOT_NOR) || defined(CONFIG_SYS_BOOT_NORSPL)\n+#define CONFIG_SYS_XWAY_EBU_BOOTCFG\t0x688C688C\n+#define CONFIG_XWAY_SWAP_BYTES\n+#endif\n+\n+#define\tCONFIG_SYS_MONITOR_BASE\t\tCONFIG_SYS_TEXT_BASE\n+\n+#endif /* __VRX200_CONFIG_H__ */\n--- /dev/null\n+++ b/arch/mips/include/asm/arch-vrx200/gphy.h\n@@ -0,0 +1,65 @@\n+/*\n+ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#ifndef __VRX200_GPHY_H__\n+#define __VRX200_GPHY_H__\n+\n+enum ltq_gphy_clk {\n+\t/* XTAL 36 MHz input */\n+\tLTQ_GPHY_CLK_36MHZ_XTAL = 1,\n+\t/* 25 MHz from PLL0 with divider */\n+\tLTQ_GPHY_CLK_25MHZ_PLL0 = 2,\n+\t/* derived from PLL2 output (XTAL is 36 MHz) */\n+\tLTQ_GPHY_CLK_24MHZ_PLL2 = 3,\n+\t/* 25 MHz Clock from Pin GPIO3 */\n+\tLTQ_GPHY_CLK_25MHZ_GPIO3 = 4,\n+};\n+\n+/*\n+ * Load PHY11G firmware for VRX200 v1.1 to given RAM address\n+ *\n+ * Address must be 16k aligned!\n+ */\n+extern void ltq_gphy_phy11g_a1x_load(ulong addr);\n+\n+/*\n+ * Load PHY11G firmware for VRX200 v1.2 to given RAM address\n+ *\n+ * Address must be 16k aligned!\n+ */\n+extern void ltq_gphy_phy11g_a2x_load(ulong addr);\n+\n+/*\n+ * Load PHY22F firmware for VRX200 v1.1 to given RAM address\n+ *\n+ * Address must be 16k aligned!\n+ */\n+extern void ltq_gphy_phy22f_a1x_load(ulong addr);\n+\n+/*\n+ * Load PHY22F firmware for VRX200 v1.2 to given RAM address\n+ *\n+ * Address must be 16k aligned!\n+ */\n+extern void ltq_gphy_phy22f_a2x_load(ulong addr);\n+\n+/*\n+ * Set clock source of internal GPHYs\n+ *\n+ * According registers resides in CGU address space. Thus this function\n+ * is implemented by the CGU driver.\n+ */\n+extern void ltq_cgu_gphy_clk_src(enum ltq_gphy_clk clk);\n+\n+/*\n+ * Boot internal GPHY with id from given RAM address\n+ *\n+ * According registers resides in RCU address space. Thus this function\n+ * is implemented by the RCU driver.\n+ */\n+extern void ltq_rcu_gphy_boot(unsigned int id, ulong addr);\n+\n+#endif /* __VRX200_GPHY_H__ */\n--- /dev/null\n+++ b/arch/mips/include/asm/arch-vrx200/gpio.h\n@@ -0,0 +1,12 @@\n+/*\n+ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#ifndef __VRX200_GPIO_H__\n+#define __VRX200_GPIO_H__\n+\n+#include <asm/lantiq/gpio.h>\n+\n+#endif /* __VRX200_GPIO_H__ */\n--- /dev/null\n+++ b/arch/mips/include/asm/arch-vrx200/nand.h\n@@ -0,0 +1,13 @@\n+/*\n+ * Copyright (C) 2012-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#ifndef __VRX200_NAND_H__\n+#define __VRX200_NAND_H__\n+\n+struct nand_chip;\n+int ltq_nand_init(struct nand_chip *nand);\n+\n+#endif /* __VRX200_NAND_H__ */\n--- /dev/null\n+++ b/arch/mips/include/asm/arch-vrx200/soc.h\n@@ -0,0 +1,45 @@\n+/*\n+ * Copyright (C) 2010 Lantiq Deutschland GmbH\n+ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#ifndef __VRX200_SOC_H__\n+#define __VRX200_SOC_H__\n+\n+#define LTQ_ASC0_BASE\t\t\t0x1E100400\n+#define LTQ_SPI_BASE\t\t\t0x1E100800\n+#define LTQ_GPIO_BASE\t\t\t0x1E100B00\n+#define LTQ_SSIO_BASE\t\t\t0x1E100BB0\n+#define LTQ_ASC1_BASE\t\t\t0x1E100C00\n+#define LTQ_DMA_BASE\t\t\t0x1E104100\n+\n+#define LTQ_EBU_BASE\t\t\t0x1E105300\n+#define LTQ_EBU_REGION0_BASE\t\t0x10000000\n+#define LTQ_EBU_REGION1_BASE\t\t0x14000000\n+#define LTQ_EBU_NAND_BASE\t\t(LTQ_EBU_BASE + 0xB0)\n+\n+#define LTQ_SWITCH_BASE\t\t\t0x1E108000\n+#define LTQ_SWITCH_CORE_BASE\t\tLTQ_SWITCH_BASE\n+#define LTQ_SWITCH_TOP_PDI_BASE\t\tLTQ_SWITCH_CORE_BASE\n+#define LTQ_SWITCH_BM_PDI_BASE\t\t(LTQ_SWITCH_CORE_BASE + 4 * 0x40)\n+#define LTQ_SWITCH_MAC_PDI_0_BASE\t(LTQ_SWITCH_CORE_BASE + 4 * 0x900)\n+#define LTQ_SWITCH_MAC_PDI_X_BASE(x)\t(LTQ_SWITCH_MAC_PDI_0_BASE + x * 0x30)\n+#define LTQ_SWITCH_TOPLEVEL_BASE\t(LTQ_SWITCH_BASE + 4 * 0xC40)\n+#define LTQ_SWITCH_MDIO_PDI_BASE\t(LTQ_SWITCH_TOPLEVEL_BASE)\n+#define LTQ_SWITCH_MII_PDI_BASE\t\t(LTQ_SWITCH_TOPLEVEL_BASE + 4 * 0x36)\n+#define LTQ_SWITCH_PMAC_PDI_BASE\t(LTQ_SWITCH_TOPLEVEL_BASE + 4 * 0x82)\n+\n+#define LTQ_PMU_BASE\t\t\t0x1F102000\n+#define LTQ_CGU_BASE\t\t\t0x1F103000\n+#define LTQ_DCDC_BASE\t\t\t0x1F106A00\n+#define LTQ_MPS_BASE\t\t\t0x1F107000\n+#define LTQ_CHIPID_BASE\t\t\t(LTQ_MPS_BASE + 0x340)\n+#define LTQ_RCU_BASE\t\t\t0x1F203000\n+\n+#define LTQ_MC_GLOBAL_BASE\t\t0x1F400000\n+#define LTQ_MC_DDR_BASE\t\t\t0x1F401000\n+#define LTQ_MC_DDR_CCR_OFFSET(x)\t(x * 0x10)\n+\n+#endif /* __VRX200_SOC_H__ */\n--- /dev/null\n+++ b/arch/mips/include/asm/arch-vrx200/switch.h\n@@ -0,0 +1,502 @@\n+/*\n+ *   Copyright (C) 2012-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com\n+ *\n+ *   SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#ifndef __VRX200_SWITCH_H__\n+#define __VRX200_SWITCH_H__\n+\n+/* Switch core registers */\n+struct vr9_switch_core_regs {\n+\t__be32 swres;\n+\t/* TODO: implement registers */\n+\t__be32 rsvd0[0x3f];\n+};\n+\n+/* Switch buffer management registers */\n+struct vr9_switch_bm_regs {\n+\tstruct bm_core {\n+\t\t__be32 ram_val3;\t/* RAM value 3 */\n+\t\t__be32 ram_val2;\t/* RAM value 2 */\n+\t\t__be32 ram_val1;\t/* RAM value 1 */\n+\t\t__be32 ram_val0;\t/* RAM value 0 */\n+\t\t__be32 ram_addr;\t/* RAM address */\n+\t\t__be32 ram_ctrl;\t/* RAM access control */\n+\t\t__be32 fsqm_gctrl;\t/* Free segment queue global control */\n+\t\t__be32 cons_sel;\t/* Number of consumed segments */\n+\t\t__be32 cons_pkt;\t/* Number of consumed packet pointers */\n+\t\t__be32 gctrl;\t\t/* Global control */\n+\t\t__be32 queue_gctrl;\t/* Queue manager global control */\n+\t\t/* TODO: implement registers */\n+\t\t__be32 rsvd0[0x35];\n+\t} core;\n+\n+\tstruct bm_port {\n+\t\t__be32 pcfg;\t\t/* Port config */\n+\t\t__be32 rmon_ctrl;\t/* RMON control */\n+\t} port[13];\n+\n+\t__be32 rsvd0[0x66];\n+\n+\tstruct bm_queue {\n+\t\t__be32 rsvd0;\n+\t\t__be32 pqm_rs;\t\t/* Packet queue manager rate shape assignment */\n+\t} queue[32];\n+\n+\tstruct bm_shaper {\n+\t\t__be32 ctrl;\t\t/* Rate shaper control */\n+\t\t__be32 cbs;\t\t/* Rate shaper committed burst size */\n+\t\t__be32 ibs;\t\t/* Rate shaper instantaneous burst size */\n+\t\t__be32 cir_ext;\t\t/* Rate shaper rate exponent */\n+\t\t__be32 cir_mant;\t/* Rate shaper rate mantissa */\n+\t} shaper[16];\n+\n+\t__be32 rsvd1[0x2a8];\n+};\n+\n+/* Switch parser and classification engine registers */\n+struct vr9_switch_pce_regs {\n+\tstruct pce_core {\n+\t\t__be32 tbl_key[16];\t/* Table key data */\n+\t\t__be32 tbl_mask;\t/* Table mask */\n+\t\t__be32 tbl_val[5];\t/* Table value */\n+\t\t__be32 tbl_addr;\t/* Table entry address */\n+\t\t__be32 tbl_ctrl;\t/* Table access control */\n+\t\t__be32 tbl_stat;\t/* Table general status */\n+\t\t__be32 age_0;\t\t/* Aging counter config 0 */\n+\t\t__be32 age_1;\t\t/* Aging counter config 1 */\n+\t\t__be32 pmap_1;\t\t/* Port map (monitoring) */\n+\t\t__be32 pmap_2;\t\t/* Port map (multicast) */\n+\t\t__be32 pmap_3;\t\t/* Port map (unknown unicast) */\n+\t\t__be32 gctrl_0;\t\t/* Global control 0 */\n+\t\t__be32 gctrl_1;\t\t/* Global control 1 */\n+\t\t__be32 tcm_gctrl;\t/* Three-color marker global control */\n+\t\t__be32 igmp_ctrl;\t/* IGMP control */\n+\t\t__be32 igmp_drpm;\t/* IGMP default router port map */\n+\t\t__be32 igmp_age_0;\t/* IGMP aging 0 */\n+\t\t__be32 igmp_age_1;\t/* IGMP aging 1 */\n+\t\t__be32 igmp_stat;\t/* IGMP status */\n+\t\t__be32 wol_gctrl;\t/* Wake-on-LAN control */\n+\t\t__be32 wol_da_0;\t/* Wake-on-LAN destination address 0 */\n+\t\t__be32 wol_da_1;\t/* Wake-on-LAN destination address 1 */\n+\t\t__be32 wol_da_2;\t/* Wake-on-LAN destination address 2 */\n+\t\t__be32 wol_pw_0;\t/* Wake-on-LAN password 0 */\n+\t\t__be32 wol_pw_1;\t/* Wake-on-LAN password 1 */\n+\t\t__be32 wol_pw_2;\t/* Wake-on-LAN password 2 */\n+\t\t__be32 ier_0;\t\t/* PCE global interrupt enable 0 */\n+\t\t__be32 ier_1;\t\t/* PCE global interrupt enable 1 */\n+\t\t__be32 isr_0;\t\t/* PCE global interrupt status 0 */\n+\t\t__be32 isr_1;\t\t/* PCE global interrupt status 1 */\n+\t\t__be32 parser_stat;\t/* Parser status */\n+\t\t__be32 rsvd0[0x6];\n+\t} core;\n+\n+\t__be32 rsvd0[0x10];\n+\n+\tstruct pce_port {\n+\t\t__be32 pctrl_0;\t\t/* Port control 0 */\n+\t\t__be32 pctrl_1;\t\t/* Port control 1 */\n+\t\t__be32 pctrl_2;\t\t/* Port control 2 */\n+\t\t__be32 pctrl_3;\t\t/* Port control 3 */\n+\t\t__be32 wol_ctrl;\t/* Wake-on-LAN control */\n+\t\t__be32 vlan_ctrl;\t/* VLAN control */\n+\t\t__be32 def_pvid;\t/* Default port VID */\n+\t\t__be32 pstat;\t\t/* Port status */\n+\t\t__be32 pier;\t\t/* Interrupt enable */\n+\t\t__be32 pisr;\t\t/* Interrupt status */\n+\t} port[13];\n+\n+\t__be32 rsvd1[0x7e];\n+\n+\tstruct pce_meter {\n+\t\t/* TODO: implement registers */\n+\t\t__be32 rsvd0[0x7];\n+\t} meter[8];\n+\n+\t__be32 rsvd2[0x308];\n+};\n+\n+static inline unsigned int to_pce_tbl_key_id(unsigned int id)\n+{\n+\tBUG_ON(id > 15);\n+\n+\treturn 15 - id;\n+}\n+\n+static inline unsigned int to_pce_tbl_value_id(unsigned int id)\n+{\n+\tBUG_ON(id > 4);\n+\n+\treturn 4 - id;\n+}\n+\n+/* Switch ethernet MAC registers */\n+struct vr9_switch_mac_regs {\n+\tstruct mac_core {\n+\t\t__be32 test;\t\t/* MAC test */\n+\t\t__be32 pfad_cfg;\t/* Pause frame source address config */\n+\t\t__be32 pfsa_0;\t\t/* Pause frame source address 0 */\n+\t\t__be32 pfsa_1;\t\t/* Pause frame source address 1 */\n+\t\t__be32 pfsa_2;\t\t/* Pause frame source address 2 */\n+\t\t__be32 flen;\t\t/* Frame length */\n+\t\t__be32 vlan_etype_0;\t/* VLAN ethertype 0 */\n+\t\t__be32 vlan_etype_1;\t/* VLAN ethertype 1 */\n+\t\t__be32 ier;\t\t/* Interrupt enable */\n+\t\t__be32 isr;\t\t/* Interrupt status */\n+\t\t__be32 rsvd0[0x36];\n+\t} core;\n+\n+\tstruct mac_port {\n+\t\t__be32 pstat;\t\t/* Port status */\n+\t\t__be32 pisr;\t\t/* Interrupt status */\n+\t\t__be32 pier;\t\t/* Interrupt enable */\n+\t\t__be32 ctrl_0;\t\t/* Control 0 */\n+\t\t__be32 ctrl_1;\t\t/* Control 1 */\n+\t\t__be32 ctrl_2;\t\t/* Control 2 */\n+\t\t__be32 ctrl_3;\t\t/* Control 3 */\n+\t\t__be32 ctrl_4;\t\t/* Control 4 */\n+\t\t__be32 ctrl_5;\t\t/* Control 5 */\n+\t\t__be32 rsvd0[0x2];\n+\t\t__be32 testen;\t\t/* Test enable */\n+\t} port[13];\n+\n+\t__be32 rsvd0[0xa4];\n+};\n+\n+/* Switch Fetch DMA registers */\n+struct vr9_switch_fdma_regs {\n+\tstruct fdma_core {\n+\t\t__be32 ctrl;\t\t/* FDMA control */\n+\t\t__be32 stetype;\t\t/* Special tag ethertype control */\n+\t\t__be32 vtetype;\t\t/* VLAN tag ethertype control */\n+\t\t__be32 stat;\t\t/* FDMA status */\n+\t\t__be32 ier;\t\t/* FDMA interrupt enable */\n+\t\t__be32 isr;\t\t/* FDMA interrupt status */\n+\t} core;\n+\n+\t__be32 rsvd0[0x3a];\n+\n+\tstruct fdma_port {\n+\t\t__be32 pctrl;\t\t/* Port control */\n+\t\t__be32 prio;\t\t/* Port priority */\n+\t\t__be32 pstat_0;\t\t/* Port status 0 */\n+\t\t__be32 pstat_1;\t\t/* Port status 1 */\n+\t\t__be32 tstamp_0;\t/* Egress time stamp 0 */\n+\t\t__be32 tstamp_1;\t/* Egress time stamp 1 */\n+\t} port[13];\n+\n+\t__be32 rsvd1[0x72];\n+};\n+\n+/* Switch Store DMA registers */\n+struct vr9_switch_sdma_regs {\n+\tstruct sdma_core {\n+\t\t__be32 ctrl;\t\t/* SDMA Control */\n+\t\t__be32 fcthr_1;\t\t/* Flow control threshold 1 */\n+\t\t__be32 rsvd0;\n+\t\t__be32 fcthr_3;\t\t/* Flow control threshold 3 */\n+\t\t__be32 fcthr_4;\t\t/* Flow control threshold 4 */\n+\t\t__be32 fcthr_5;\t\t/* Flow control threshold 5 */\n+\t\t__be32 fcthr_6;\t\t/* Flow control threshold 6 */\n+\t\t__be32 fcthr_7;\t\t/* Flow control threshold 7 */\n+\t\t__be32 stat_0;\t\t/* SDMA status 0 */\n+\t\t__be32 stat_1;\t\t/* SDMA status 1 */\n+\t\t__be32 stat_2;\t\t/* SDMA status 2 */\n+\t\t__be32 ier;\t\t/* SDMA interrupt enable */\n+\t\t__be32 isr;\t\t/* SDMA interrupt status */\n+\t} core;\n+\n+\t__be32 rsvd0[0x73];\n+\n+\tstruct sdma_port {\n+\t\t__be32 pctrl;\t\t/* Port control */\n+\t\t__be32 prio;\t\t/* Port priority */\n+\t\t__be32 pstat_0;\t\t/* Port status 0 */\n+\t\t__be32 pstat_1;\t\t/* Port status 1 */\n+\t\t__be32 tstamp_0;\t/* Ingress time stamp 0 */\n+\t\t__be32 tstamp_1;\t/* Ingress time stamp 1 */\n+\t} port[13];\n+\n+\t__be32 rsvd1[0x32];\n+};\n+\n+/* Switch MDIO control and status registers */\n+struct vr9_switch_mdio_regs {\n+\t__be32 glob_ctrl;\t/* Global control 0 */\n+\t__be32 rsvd0[7];\n+\t__be32 mdio_ctrl;\t/* MDIO control */\n+\t__be32 mdio_read;\t/* MDIO read data */\n+\t__be32 mdio_write;\t/* MDIO write data */\n+\t__be32 mdc_cfg_0;\t/* MDC clock configuration 0 */\n+\t__be32 mdc_cfg_1;\t/* MDC clock configuration 1 */\n+\t__be32 rsvd1[0x3];\n+\t__be32 phy_addr[6];\t/* PHY address port 5..0 */\n+\t__be32 mdio_stat[6];\t/* MDIO PHY polling status port 0..5 */\n+\t__be32 aneg_eee[6];\t/* EEE auto-neg overrides port 0..5 */\n+\t__be32 rsvd2[0x14];\n+};\n+\n+static inline unsigned int to_mdio_phyaddr_id(unsigned int id)\n+{\n+\tBUG_ON(id > 5);\n+\n+\treturn 5 - id;\n+}\n+\n+/* Switch xMII control registers */\n+struct vr9_switch_mii_regs {\n+\t__be32 mii_cfg0;\t/* xMII port 0 configuration */\n+\t__be32 pcdu0;\t\t/* Port 0 clock delay configuration */\n+\t__be32 mii_cfg1;\t/* xMII port 1 configuration */\n+\t__be32 pcdu1;\t\t/* Port 1 clock delay configuration */\n+\t__be32 rsvd0[0x6];\n+\t__be32 mii_cfg5;\t/* xMII port 5 configuration */\n+\t__be32 pcdu5;\t\t/* Port 5 clock delay configuration */\n+\t__be32 rsvd1[0x14];\n+\t__be32 rxb_ctl_0;\t/* Port 0 receive buffer control */\n+\t__be32 rxb_ctl_1;\t/* Port 1 receive buffer control */\n+\t__be32 rxb_ctl_5;\t/* Port 5 receive buffer control */\n+\t__be32 rsvd2[0x28];\n+\t__be32 dbg_ctl;\t\t/* Debug control */\n+};\n+\n+/* Switch Pseudo-MAC registers */\n+struct vr9_switch_pmac_regs {\n+\t__be32 hd_ctl;\t\t/* PMAC header control */\n+\t__be32 tl;\t\t/* PMAC type/length */\n+\t__be32 sa1;\t\t/* PMAC source address 1 */\n+\t__be32 sa2;\t\t/* PMAC source address 2 */\n+\t__be32 sa3;\t\t/* PMAC source address 3 */\n+\t__be32 da1;\t\t/* PMAC destination address 1 */\n+\t__be32 da2;\t\t/* PMAC destination address 2 */\n+\t__be32 da3;\t\t/* PMAC destination address 3 */\n+\t__be32 vlan;\t\t/* PMAC VLAN */\n+\t__be32 rx_ipg;\t\t/* PMAC interpacket gap in RX direction */\n+\t__be32 st_etype;\t/* PMAC special tag ethertype */\n+\t__be32 ewan;\t\t/* PMAC ethernet WAN group */\n+\t__be32 ctl;\t\t/* PMAC control */\n+\t__be32 rsvd0[0x2];\n+};\n+\n+struct vr9_switch_regs {\n+\tstruct vr9_switch_core_regs core;\n+\tstruct vr9_switch_bm_regs bm;\n+\tstruct vr9_switch_pce_regs pce;\n+\tstruct vr9_switch_mac_regs mac;\n+\tstruct vr9_switch_fdma_regs fdma;\n+\tstruct vr9_switch_sdma_regs sdma;\n+\tstruct vr9_switch_mdio_regs mdio;\n+\tstruct vr9_switch_mii_regs mii;\n+\tstruct vr9_switch_pmac_regs pmac;\n+};\n+\n+static inline void *to_pce_tbl_key(struct vr9_switch_regs *regs,\n+\t\t\t\t\t\tunsigned int id)\n+{\n+\treturn &regs->pce.core.tbl_key[to_pce_tbl_key_id(id)];\n+}\n+\n+static inline void *to_pce_tbl_value(struct vr9_switch_regs *regs,\n+\t\t\t\t\t\tunsigned int id)\n+{\n+\treturn &regs->pce.core.tbl_val[to_pce_tbl_value_id(id)];\n+}\n+\n+static inline void *to_mac_ctrl(struct vr9_switch_regs *regs,\n+\t\t\t\t\tunsigned int id, unsigned int ctrl)\n+{\n+\tstruct mac_port *mac = &regs->mac.port[id];\n+\n+\tswitch (ctrl) {\n+\tcase 0:\n+\t\treturn &mac->ctrl_0;\n+\tcase 1:\n+\t\treturn &mac->ctrl_1;\n+\tcase 2:\n+\t\treturn &mac->ctrl_2;\n+\tcase 3:\n+\t\treturn &mac->ctrl_3;\n+\tcase 4:\n+\t\treturn &mac->ctrl_4;\n+\tcase 5:\n+\t\treturn &mac->ctrl_5;\n+\tdefault:\n+\t\treturn NULL;\n+\t}\n+}\n+\n+static inline void *to_mdio_phyaddr(struct vr9_switch_regs *regs,\n+\t\t\t\t\tunsigned int id)\n+{\n+\treturn &regs->mdio.phy_addr[to_mdio_phyaddr_id(id)];\n+}\n+\n+static inline void *to_mii_miicfg(struct vr9_switch_regs *regs,\n+\t\t\t\t\tunsigned int id)\n+{\n+\tswitch (id) {\n+\tcase 0:\n+\t\treturn &regs->mii.mii_cfg0;\n+\tcase 1:\n+\t\treturn &regs->mii.mii_cfg1;\n+\tcase 5:\n+\t\treturn &regs->mii.mii_cfg5;\n+\tdefault:\n+\t\treturn NULL;\n+\t}\n+}\n+\n+static inline void *to_mii_pcdu(struct vr9_switch_regs *regs,\n+\t\t\t\t\tunsigned int id)\n+{\n+\tswitch (id) {\n+\tcase 0:\n+\t\treturn &regs->mii.pcdu0;\n+\tcase 1:\n+\t\treturn &regs->mii.pcdu1;\n+\tcase 5:\n+\t\treturn &regs->mii.pcdu5;\n+\tdefault:\n+\t\treturn NULL;\n+\t}\n+}\n+\n+#define VR9_SWITCH_REG_OFFSET(reg)\t(4 * (reg))\n+\n+#define BUILD_CHECK_VR9_REG(name, offset)\t\\\n+\tBUILD_BUG_ON(offsetof(struct vr9_switch_regs, name) != (4 * offset))\n+\n+static inline void build_check_vr9_registers(void)\n+{\n+\tBUILD_CHECK_VR9_REG(core, 0x0);\n+\tBUILD_CHECK_VR9_REG(bm.core, 0x40);\n+\tBUILD_CHECK_VR9_REG(bm.core.queue_gctrl, 0x4a);\n+\tBUILD_CHECK_VR9_REG(bm.port[0], 0x80);\n+\tBUILD_CHECK_VR9_REG(bm.queue, 0x100);\n+\tBUILD_CHECK_VR9_REG(bm.shaper, 0x140);\n+\tBUILD_CHECK_VR9_REG(pce.core, 0x438);\n+\tBUILD_CHECK_VR9_REG(pce.core.tbl_ctrl, 0x44f);\n+\tBUILD_CHECK_VR9_REG(pce.core.parser_stat, 0x469);\n+\tBUILD_CHECK_VR9_REG(pce.port[0], 0x480);\n+\tBUILD_CHECK_VR9_REG(pce.meter[0], 0x580);\n+\tBUILD_CHECK_VR9_REG(mac.core, 0x8c0);\n+\tBUILD_CHECK_VR9_REG(mac.port[0].pstat, 0x900);\n+\tBUILD_CHECK_VR9_REG(mac.port[0].ctrl_0, 0x903);\n+\tBUILD_CHECK_VR9_REG(mac.port[1].pstat, 0x90c);\n+\tBUILD_CHECK_VR9_REG(mac.port[1].ctrl_0, 0x90f);\n+\tBUILD_CHECK_VR9_REG(mac.port[2].pstat, 0x918);\n+\tBUILD_CHECK_VR9_REG(mac.port[2].ctrl_0, 0x91b);\n+\tBUILD_CHECK_VR9_REG(fdma.core, 0xa40);\n+\tBUILD_CHECK_VR9_REG(fdma.port[0], 0xa80);\n+\tBUILD_CHECK_VR9_REG(sdma.core, 0xb40);\n+\tBUILD_CHECK_VR9_REG(sdma.port[0], 0xbc0);\n+\tBUILD_CHECK_VR9_REG(mdio, 0xc40);\n+\tBUILD_CHECK_VR9_REG(mii, (0xc40 + 0x36));\n+\tBUILD_CHECK_VR9_REG(pmac, (0xc40 + 0x82));\n+}\n+\n+#define BM_GCTRL_F_SRES\t\t1\n+\n+#define MAC_CTRL0_BM\t\t(1 << 12)\n+#define MAC_CTRL0_APADEN\t(1 << 11)\n+#define MAC_CTRL0_VPAD2EN\t(1 << 10)\n+#define MAC_CTRL0_VPADEN\t(1 << 9)\n+#define MAC_CTRL0_PADEN\t\t(1 << 8)\n+#define MAC_CTRL0_FCS\t\t(1 << 7)\n+#define MAC_CTRL0_FCON_SHIFT\t4\n+#define MAC_CTRL0_FCON_AUTO\t(0x0 << MAC_CTRL0_FCON_SHIFT)\n+#define MAC_CTRL0_FCON_RX\t(0x1 << MAC_CTRL0_FCON_SHIFT)\n+#define MAC_CTRL0_FCON_TX\t(0x2 << MAC_CTRL0_FCON_SHIFT)\n+#define MAC_CTRL0_FCON_RXTX\t(0x3 << MAC_CTRL0_FCON_SHIFT)\n+#define MAC_CTRL0_FCON_NONE\t(0x4 << MAC_CTRL0_FCON_SHIFT)\n+#define MAC_CTRL0_FDUP_SHIFT\t2\n+#define MAC_CTRL0_FDUP_AUTO\t(0x0 << MAC_CTRL0_FDUP_SHIFT)\n+#define MAC_CTRL0_FDUP_EN\t(0x1 << MAC_CTRL0_FDUP_SHIFT)\n+#define MAC_CTRL0_FDUP_DIS\t(0x3 << MAC_CTRL0_FDUP_SHIFT)\n+#define MAC_CTRL0_GMII_AUTO\t0x0\n+#define MAC_CTRL0_GMII_MII\t0x1\n+#define MAC_CTRL0_GMII_GMII\t0x2\n+#define MAC_CTRL0_GMII_GMII_2G\t0x3\n+\n+#define MAC_CTRL1_DEFERMODE\t(1 << 15)\n+#define MAC_CTRL1_SHORTPRE\t(1 << 8)\n+\n+#define MAC_CTRL2_MLEN\t\t(1 << 3)\n+#define MAC_CTRL2_LCHKL\t\t(1 << 2)\n+#define MAC_CTRL2_LCHKS_DIS\t0x0\n+#define MAC_CTRL2_LCHKS_UNTAG\t0x1\n+#define MAC_CTRL2_LCHKS_TAG\t0x2\n+\n+#define PHY_ADDR_LNKST_SHIFT\t13\n+#define PHY_ADDR_LNKST_AUTO\t(0x0 << PHY_ADDR_LNKST_SHIFT)\n+#define PHY_ADDR_LNKST_UP\t(0x1 << PHY_ADDR_LNKST_SHIFT)\n+#define PHY_ADDR_LNKST_DOWN\t(0x2 << PHY_ADDR_LNKST_SHIFT)\n+#define PHY_ADDR_SPEED_SHIFT\t11\n+#define PHY_ADDR_SPEED_M10\t(0x0 << PHY_ADDR_SPEED_SHIFT)\n+#define PHY_ADDR_SPEED_M100\t(0x1 << PHY_ADDR_SPEED_SHIFT)\n+#define PHY_ADDR_SPEED_G1\t(0x2 << PHY_ADDR_SPEED_SHIFT)\n+#define PHY_ADDR_SPEED_AUTO\t(0x3 << PHY_ADDR_SPEED_SHIFT)\n+#define PHY_ADDR_FDUP_SHIFT\t9\n+#define PHY_ADDR_FDUP_AUTO\t(0x0 << PHY_ADDR_FDUP_SHIFT)\n+#define PHY_ADDR_FDUP_EN\t(0x1 << PHY_ADDR_FDUP_SHIFT)\n+#define PHY_ADDR_FDUP_DIS\t(0x3 << PHY_ADDR_FDUP_SHIFT)\n+#define PHY_ADDR_FCONTX_SHIFT\t7\n+#define PHY_ADDR_FCONTX_AUTO\t(0x0 << PHY_ADDR_FCONTX_SHIFT)\n+#define PHY_ADDR_FCONTX_EN\t(0x1 << PHY_ADDR_FCONTX_SHIFT)\n+#define PHY_ADDR_FCONTX_DIS\t(0x3 << PHY_ADDR_FCONTX_SHIFT)\n+#define PHY_ADDR_FCONRX_SHIFT\t5\n+#define PHY_ADDR_FCONRX_AUTO\t(0x0 << PHY_ADDR_FCONRX_SHIFT)\n+#define PHY_ADDR_FCONRX_EN\t(0x1 << PHY_ADDR_FCONRX_SHIFT)\n+#define PHY_ADDR_FCONRX_DIS\t(0x3 << PHY_ADDR_FCONRX_SHIFT)\n+\n+#define MII_CFG_RES\t\t(1 << 15)\n+#define MII_CFG_EN\t\t(1 << 14)\n+#define MII_CFG_LDCLKDIS\t(1 << 12)\n+#define MII_CFG_MIIRATE_SHIFT\t4\n+#define MII_CFG_MIIRATE_MASK\t(0x7 << MII_CFG_MIIRATE_SHIFT)\n+#define MII_CFG_MIIRATE_M2P5\t(0x0 << MII_CFG_MIIRATE_SHIFT)\n+#define MII_CFG_MIIRATE_M25\t(0x1 << MII_CFG_MIIRATE_SHIFT)\n+#define MII_CFG_MIIRATE_M125\t(0x2 << MII_CFG_MIIRATE_SHIFT)\n+#define MII_CFG_MIIRATE_M50\t(0x3 << MII_CFG_MIIRATE_SHIFT)\n+#define MII_CFG_MIIRATE_AUTO\t(0x4 << MII_CFG_MIIRATE_SHIFT)\n+#define MII_CFG_MIIMODE_MASK\t0xf\n+#define MII_CFG_MIIMODE_MIIP\t0x0\n+#define MII_CFG_MIIMODE_MIIM\t0x1\n+#define MII_CFG_MIIMODE_RMIIP\t0x2\n+#define MII_CFG_MIIMODE_RMIIM\t0x3\n+#define MII_CFG_MIIMODE_RGMII\t0x4\n+\n+#define PCDU_RXDLY_SHIFT\t7\n+#define PCDU_RXDLY_MASK\t\t(0x7 << PCDU_RXDLY_SHIFT)\n+#define PCDU_TXDLY_MASK\t\t0x7\n+\n+#define PMAC_HD_CTL_FC\t\t(1 << 10)\n+#define PMAC_HD_CTL_CCRC\t(1 << 9)\n+#define PMAC_HD_CTL_RST\t\t(1 << 8)\n+#define PMAC_HD_CTL_AST\t\t(1 << 7)\n+#define PMAC_HD_CTL_RXSH\t(1 << 6)\n+#define PMAC_HD_CTL_RC\t\t(1 << 4)\n+#define PMAC_HD_CTL_AS\t\t(1 << 3)\n+#define PMAC_HD_CTL_AC\t\t(1 << 2)\n+\n+#define PCE_PCTRL_0_IGSTEN\t(1 << 11)\n+\n+#define FDMA_PCTRL_STEN\t\t(1 << 1)\n+#define FDMA_PCTRL_EN\t\t(1 << 0)\n+\n+#define SDMA_PCTRL_EN\t\t(1 << 0)\n+\n+#define MDIO_GLOB_CTRL_SE\t(1 << 15)\n+\n+#define MDIO_MDC_CFG1_RES\t(1 << 15)\n+#define MDIO_MDC_CFG1_MCEN\t(1 << 8)\n+\n+#define MDIO_CTRL_MBUSY\t\t(1 << 12)\n+#define MDIO_CTRL_OP_READ\t(1 << 11)\n+#define MDIO_CTRL_OP_WRITE\t(1 << 10)\n+#define MDIO_CTRL_PHYAD_SHIFT\t5\n+#define MDIO_CTRL_PHYAD_MASK\t(0x1f << MDIO_CTRL_PHYAD_SHIFT)\n+#define MDIO_CTRL_REGAD_MASK\t0x1f\n+\n+#endif /* __VRX200_SWITCH_H__ */\n--- a/arch/mips/include/asm/asm.h\n+++ b/arch/mips/include/asm/asm.h\n@@ -53,6 +53,7 @@\n \t\t.align\t2;                              \\\n \t\t.type\tsymbol, @function;              \\\n \t\t.ent\tsymbol, 0;                      \\\n+\t\t.section .text.symbol,\"x\";              \\\n symbol:\t\t.frame\tsp, 0, ra\n \n /*\n@@ -62,7 +63,8 @@ symbol:\t\t.frame\tsp, 0, ra\n \t\t.globl\tsymbol;                         \\\n \t\t.align\t2;                              \\\n \t\t.type\tsymbol, @function;              \\\n-\t\t.ent\tsymbol, 0;                       \\\n+\t\t.ent\tsymbol, 0;                      \\\n+\t\t.section .text.symbol,\"x\";              \\\n symbol:\t\t.frame\tsp, framesize, rpc\n \n /*\n--- /dev/null\n+++ b/arch/mips/include/asm/gpio.h\n@@ -0,0 +1,6 @@\n+/*\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#include <asm/arch/gpio.h>\n+#include <asm-generic/gpio.h>\n--- /dev/null\n+++ b/arch/mips/include/asm/lantiq/chipid.h\n@@ -0,0 +1,73 @@\n+/*\n+ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#ifndef __LANTIQ_CHIPID_H__\n+#define __LANTIQ_CHIPID_H__\n+\n+enum ltq_chip_partnum {\n+\tLTQ_SOC_UNKNOWN = 0,\n+\tLTQ_SOC_VRX288_2 = 0x000B,\t/* VRX288 v1.2 */\n+\tLTQ_SOC_VRX268_2 = 0x000C,\t/* VRX268 v1.2 */\n+\tLTQ_SOC_GRX288_2 = 0x000D,\t/* GRX288 v1.2 */\n+\tLTQ_SOC_DANUBE = 0x0129,\n+\tLTQ_SOC_DANUBE_S = 0x012B,\n+\tLTQ_SOC_TWINPASS = 0x012D,\n+\tLTQ_SOC_VRX288 = 0x01C0,\t/* VRX288 v1.1 */\n+\tLTQ_SOC_VRX268 = 0x01C2,\t/* VRX268 v1.1 */\n+\tLTQ_SOC_GRX288 = 0x01C9,\t/* GRX288 v1.1 */\n+};\n+\n+extern unsigned int ltq_chip_version_get(void);\n+extern unsigned int ltq_chip_partnum_get(void);\n+extern const char *ltq_chip_partnum_str(void);\n+\n+extern void ltq_chip_print_info(void);\n+\n+#ifdef CONFIG_SOC_XWAY_DANUBE\n+static inline int ltq_soc_is_danube(void)\n+{\n+\treturn 1;\n+}\n+#else\n+static inline int ltq_soc_is_danube(void)\n+{\n+\treturn 0;\n+}\n+#endif\n+\n+#ifdef CONFIG_SOC_XWAY_VRX200\n+static inline int ltq_soc_is_vrx200(void)\n+{\n+\treturn 1;\n+}\n+\n+static inline int ltq_soc_is_vrx200_v1(void)\n+{\n+\treturn ltq_chip_version_get() == 1;\n+}\n+\n+static inline int ltq_soc_is_vrx200_v2(void)\n+{\n+\treturn ltq_chip_version_get() == 2;\n+}\n+#else\n+static inline int ltq_soc_is_vrx200(void)\n+{\n+\treturn 0;\n+}\n+\n+static inline int ltq_soc_is_vrx200_v1(void)\n+{\n+\treturn 0;\n+}\n+\n+static inline int ltq_soc_is_vrx200_v2(void)\n+{\n+\treturn 0;\n+}\n+#endif\n+\n+#endif /* __LANTIQ_CHIPID_H__ */\n--- /dev/null\n+++ b/arch/mips/include/asm/lantiq/clk.h\n@@ -0,0 +1,30 @@\n+/*\n+ * Copyright (C) 2007-2010 Lantiq Deutschland GmbH\n+ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com\n+ * *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#ifndef __LANTIQ_CLK_H__\n+#define __LANTIQ_CLK_H__\n+\n+/* Symbolic clock speeds */\n+enum ltq_clk {\n+\tCLOCK_83_MHZ = 83333333,\n+\tCLOCK_111_MHZ = 111111111,\n+\tCLOCK_125_MHZ = 125000000,\n+\tCLOCK_133_MHZ = 133333333,\n+\tCLOCK_166_MHZ = 166666667,\n+\tCLOCK_197_MHZ = 197000000,\n+\tCLOCK_333_MHZ = 333333333,\n+\tCLOCK_393_MHZ = 393219000,\n+\tCLOCK_500_MHZ = 500000000,\n+\tCLOCK_600_MHZ = 600000000,\n+\tCLOCK_1000_MHZ = 1000000000,\n+};\n+\n+extern unsigned long ltq_get_cpu_clock(void);\n+extern unsigned long ltq_get_bus_clock(void);\n+extern unsigned long ltq_get_io_region_clock(void);\n+\n+#endif /* __LANTIQ_CLK_H__ */\n--- /dev/null\n+++ b/arch/mips/include/asm/lantiq/config.h\n@@ -0,0 +1,164 @@\n+/*\n+ * Copyright (C) 2007-2010 Lantiq Deutschland GmbH\n+ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#ifndef __LANTIQ_CONFIG_H__\n+#define __LANTIQ_CONFIG_H__\n+\n+/* Memory usage */\n+#define CONFIG_SYS_MAXARGS\t\t24\n+#define CONFIG_SYS_MALLOC_LEN\t\t1024*1024\n+#define CONFIG_SYS_BOOTPARAMS_LEN\t128*1024\n+\n+/* Command line */\n+#define CONFIG_SYS_PROMPT\t\tCONFIG_MACH_TYPE \" # \"\n+#define CONFIG_SYS_CBSIZE\t\t512\n+#define CONFIG_SYS_PBSIZE\t\t(CONFIG_SYS_CBSIZE + \\\n+\t\t\t\t\tsizeof(CONFIG_SYS_PROMPT)+16)\n+\n+#define CONFIG_SYS_HUSH_PARSER\n+#define CONFIG_SYS_PROMPT_HUSH_PS2\t\"> \"\n+\n+/*\n+ * Enable advanced console features on demand to reduce\n+ * flash and RAM footprint\n+ */\n+#if defined(CONFIG_LTQ_ADVANCED_CONSOLE)\n+#define CONFIG_SYS_LONGHELP\n+#define CONFIG_AUTO_COMPLETE\n+#define CONFIG_CMDLINE_EDITING\n+#endif\n+\n+/* SPI flash SPL */\n+#if defined(CONFIG_LTQ_SUPPORT_SPL_SPI_FLASH) && defined(CONFIG_SYS_BOOT_SFSPL)\n+#define CONFIG_SPL\n+#define CONFIG_SPL_SPI_SUPPORT\n+#define CONFIG_SPL_SPI_FLASH_SUPPORT\n+#define CONFIG_SPI_SPL_SIMPLE\n+#endif\n+\n+#if defined(CONFIG_LTQ_SUPPORT_SPL_NOR_FLASH) && defined(CONFIG_SYS_BOOT_NORSPL)\n+#define CONFIG_SPL\n+#endif\n+\n+/* Common SPL */\n+#if defined(CONFIG_SPL)\n+#define CONFIG_SKIP_LOWLEVEL_INIT\n+#define CONFIG_SPL_LIBGENERIC_SUPPORT\n+#define CONFIG_SPL_GPIO_SUPPORT\n+#define CONFIG_SPL_START_S_PATH\t\t\\\n+\t\t\"arch/mips/cpu/mips32/lantiq-common\"\n+#define CONFIG_SPL_LDSCRIPT\t\t\\\n+\t\t\"arch/mips/cpu/mips32/lantiq-common/u-boot-spl.lds\"\n+#endif\n+\n+#if defined(CONFIG_LTQ_SPL_CONSOLE)\n+#define CONFIG_SPL_SERIAL_SUPPORT\n+#define CONFIG_SPL_LIBCOMMON_SUPPORT\n+#endif\n+\n+#if defined(CONFIG_LTQ_SPL_COMP_LZMA)\n+#define CONFIG_LZMA\n+#define CONFIG_SPL_LZMA_SUPPORT\n+#endif\n+\n+#if defined(CONFIG_LTQ_SPL_COMP_LZO)\n+#define CONFIG_LZO\n+#define CONFIG_SPL_LZO_SUPPORT\n+#endif\n+\n+/* Basic commands */\n+#define CONFIG_CMD_BDI\n+#define CONFIG_CMD_EDITENV\n+#define CONFIG_CMD_IMI\n+#define CONFIG_CMD_MEMORY\n+#define CONFIG_CMD_RUN\n+#define CONFIG_CMD_SAVEENV\n+#define CONFIG_CMD_LOADB\n+\n+/* Other U-Boot settings */\n+#define CONFIG_TIMESTAMP\n+\n+/* Default environment */\n+#define CONFIG_ENV_CONSOLEDEV\t\t\t\t\t\\\n+\t\"consoledev=\" CONFIG_CONSOLE_DEV \"\\0\"\n+\n+#define CONFIG_ENV_ADDCONSOLE\t\t\t\t\t\\\n+\t\"addconsole=setenv bootargs $bootargs\"\t\t\t\\\n+\t\" console=$consoledev,$baudrate\\0\"\n+\n+#if defined(CONFIG_NET_DEV)\n+#define CONFIG_ENV_NETDEV\t\t\t\t\t\\\n+\t\"netdev=\" CONFIG_NET_DEV \"\\0\"\n+#else\n+#define CONFIG_ENV_NETDEV\t\t\t\t\t\\\n+\t\"netdev=eth0\\0\"\n+#endif\n+\n+#define CONFIG_ENV_ADDIP\t\t\t\t\t\\\n+\t\"addip=setenv bootargs $bootargs\"\t\t\t\\\n+\t\" ip=$ipaddr:$serverip::::$netdev:off\\0\"\n+\n+#define CONFIG_ENV_ADDETH\t\t\t\t\t\\\n+\t\"addeth=setenv bootargs $bootargs\"\t\t\t\\\n+\t\" ethaddr=$ethaddr\\0\"\n+\n+#define CONFIG_ENV_ADDMACHTYPE\t\t\t\t\t\\\n+\t\"addmachtype=setenv bootargs $bootargs\"\t\t\t\\\n+\t\" machtype=\" CONFIG_MACH_TYPE \"\\0\"\n+\n+#if defined(CONFIG_LTQ_SUPPORT_NOR_FLASH)\n+#define CONFIG_ENV_WRITE_UBOOT_NOR\t\t\t\t\t\\\n+\t\"write-uboot-nor=\"\t\t\t\t\t\t\\\n+\t\"protect off \" __stringify(CONFIG_SYS_FLASH_BASE) \" +$filesize && \" \\\n+\t\"erase \" __stringify(CONFIG_SYS_FLASH_BASE) \" +$filesize && \"\t\\\n+\t\"cp.b $fileaddr \" __stringify(CONFIG_SYS_FLASH_BASE) \" $filesize\\0\"\n+\n+#define CONFIG_ENV_LOAD_UBOOT_NOR\t\t\t\t\t\\\n+\t\"load-uboot-nor=tftpboot u-boot.bin\\0\"\t\t\t\t\\\n+\t\"load-uboot-norspl=tftpboot u-boot.ltq.norspl\\0\"\t\t\\\n+\t\"load-uboot-norspl-lzo=tftpboot u-boot.ltq.lzo.norspl\\0\"\t\\\n+\t\"load-uboot-norspl-lzma=tftpboot u-boot.ltq.lzma.norspl\\0\"\n+#else\n+#define CONFIG_ENV_WRITE_UBOOT_NOR\n+#define CONFIG_ENV_LOAD_UBOOT_NOR\n+#endif\n+\n+#if defined(CONFIG_LTQ_SUPPORT_SPI_FLASH)\n+#define CONFIG_ENV_SF_PROBE\t\t\t\t\t\\\n+\t\"sf-probe=sf probe \" __stringify(CONFIG_ENV_SPI_CS) \" \"\t\\\n+\t__stringify(CONFIG_ENV_SPI_MAX_HZ) \" \"\t\t\t\\\n+\t__stringify(CONFIG_ENV_SPI_MODE) \" \\0\"\n+\n+#define CONFIG_ENV_WRITE_UBOOT_SF\t\t\t\t\\\n+\t\"write-uboot-sf=\"\t\t\t\t\t\\\n+\t\"run sf-probe && sf erase 0 +$filesize && \"\t\t\\\n+\t\"sf write $fileaddr 0 $filesize\\0\"\n+\n+#define CONFIG_ENV_LOAD_UBOOT_SF\t\t\t\t\t\\\n+\t\"load-uboot-sfspl=tftpboot u-boot.ltq.sfspl\\0\"\t\t\t\\\n+\t\"load-uboot-sfspl-lzo=tftpboot u-boot.ltq.lzo.sfspl\\0\"\t\t\\\n+\t\"load-uboot-sfspl-lzma=tftpboot u-boot.ltq.lzma.sfspl\\0\"\n+#else\n+#define CONFIG_ENV_SF_PROBE\n+#define CONFIG_ENV_WRITE_UBOOT_SF\n+#define CONFIG_ENV_LOAD_UBOOT_SF\n+#endif\n+\n+#define CONFIG_ENV_LANTIQ_DEFAULTS\t\\\n+\tCONFIG_ENV_CONSOLEDEV\t\t\\\n+\tCONFIG_ENV_ADDCONSOLE\t\t\\\n+\tCONFIG_ENV_NETDEV\t\t\\\n+\tCONFIG_ENV_ADDIP\t\t\\\n+\tCONFIG_ENV_ADDETH\t\t\\\n+\tCONFIG_ENV_ADDMACHTYPE\t\t\\\n+\tCONFIG_ENV_WRITE_UBOOT_NOR\t\\\n+\tCONFIG_ENV_LOAD_UBOOT_NOR\t\\\n+\tCONFIG_ENV_SF_PROBE\t\t\\\n+\tCONFIG_ENV_WRITE_UBOOT_SF\t\\\n+\tCONFIG_ENV_LOAD_UBOOT_SF\n+\n+#endif /* __LANTIQ_CONFIG_H__ */\n--- /dev/null\n+++ b/arch/mips/include/asm/lantiq/cpu.h\n@@ -0,0 +1,34 @@\n+/*\n+ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#ifndef __LANTIQ_CPU_H__\n+#define __LANTIQ_CPU_H__\n+\n+enum ltq_boot_select {\n+\tBOOT_NOR,\n+\tBOOT_NOR_NO_BOOTROM,\n+\tBOOT_UART,\n+\tBOOT_UART_NO_EEPROM,\n+\tBOOT_SPI,\n+\tBOOT_NAND,\n+\tBOOT_PCI,\n+\tBOOT_MII0,\n+\tBOOT_RMII0,\n+\tBOOT_RGMII1,\n+\tBOOT_UNKNOWN,\n+};\n+\n+enum ltq_boot_select ltq_boot_select(void);\n+const char *ltq_boot_select_str(void);\n+\n+void ltq_pmu_init(void);\n+void ltq_ebu_init(void);\n+void ltq_gpio_init(void);\n+\n+void ltq_pll_init(void);\n+void ltq_dcdc_init(unsigned int dig_ref);\n+\n+#endif /* __LANTIQ_CPU_H__ */\n--- /dev/null\n+++ b/arch/mips/include/asm/lantiq/dma.h\n@@ -0,0 +1,94 @@\n+/*\n+ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#ifndef __LANTIQ_DMA_H__\n+#define __LANTIQ_DMA_H__\n+\n+enum ltq_dma_endianess {\n+\tLTQ_DMA_ENDIANESS_B0_B1_B2_B3,\t/* No byte swapping */\n+\tLTQ_DMA_ENDIANESS_B1_B0_B3_B2,\t/* B0B1B2B3 => B1B0B3B2 */\n+\tLTQ_DMA_ENDIANESS_B2_B3_B0_B1,\t/* B0B1B2B3 => B2B3B0B1 */\n+\tLTQ_DMA_ENDIANESS_B3_B2_B1_B0,\t/* B0B1B2B3 => B3B2B1B0 */\n+};\n+\n+enum ltq_dma_burst_len {\n+\tLTQ_DMA_BURST_2WORDS = 1,\n+\tLTQ_DMA_BURST_4WORDS = 2,\n+\tLTQ_DMA_BURST_8WORDS = 3,\n+};\n+\n+struct ltq_dma_desc {\n+\tu32 ctl;\n+\tu32 addr;\n+};\n+\n+struct ltq_dma_channel {\n+\tstruct ltq_dma_device *dev;\n+\tu8 chan_no;\n+\tu8 class;\n+\tu16 num_desc;\n+\tstruct ltq_dma_desc *desc_base;\n+\tvoid *mem_base;\n+\tu32 dma_addr;\n+};\n+\n+struct ltq_dma_device {\n+\tenum ltq_dma_endianess rx_endian_swap;\n+\tenum ltq_dma_endianess tx_endian_swap;\n+\tenum ltq_dma_burst_len rx_burst_len;\n+\tenum ltq_dma_burst_len tx_burst_len;\n+\tstruct ltq_dma_channel rx_chan;\n+\tstruct ltq_dma_channel tx_chan;\n+\tu8 port;\n+};\n+\n+/**\n+ * Initialize DMA hardware and driver\n+ */\n+void ltq_dma_init(void);\n+\n+/**\n+ * Register given DMA client context\n+ *\n+ * @returns 0 on success, negative value otherwise\n+ */\n+int ltq_dma_register(struct ltq_dma_device *dev);\n+\n+/**\n+ * Reset and halt all channels related to given DMA client\n+ */\n+void ltq_dma_reset(struct ltq_dma_device *dev);\n+void ltq_dma_enable(struct ltq_dma_device *dev);\n+void ltq_dma_disable(struct ltq_dma_device *dev);\n+\n+/**\n+ * Map RX DMA descriptor to memory region\n+ *\n+ * @returns 0 on success, negative value otherwise\n+ */\n+int ltq_dma_rx_map(struct ltq_dma_device *dev, int index, void *data, int len);\n+\n+/**\n+ * Check if new data is available.\n+ *\n+ * @returns length of received data, 0 otherwise\n+ */\n+int ltq_dma_rx_poll(struct ltq_dma_device *dev, int index);\n+\n+int ltq_dma_rx_length(struct ltq_dma_device *dev, int index);\n+\n+/**\n+ * Map TX DMA descriptor to memory region\n+ *\n+ * @returns 0 on success, negative value otherwise\n+ */\n+int ltq_dma_tx_map(struct ltq_dma_device *dev, int index, void *data, int len,\n+\t\t\tunsigned long timeout);\n+\n+int ltq_dma_tx_wait(struct ltq_dma_device *dev, int index,\n+\t\t\tunsigned long timeout);\n+\n+#endif /* __LANTIQ_DMA_H__ */\n--- /dev/null\n+++ b/arch/mips/include/asm/lantiq/eth.h\n@@ -0,0 +1,35 @@\n+/*\n+ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#ifndef __LANTIQ_ETH_H__\n+#define __LANTIQ_ETH_H__\n+\n+#include <phy.h>\n+\n+enum LTQ_ETH_PORT_FLAGS {\n+\tLTQ_ETH_PORT_NONE\t= 0,\n+\tLTQ_ETH_PORT_PHY\t= 1,\n+\tLTQ_ETH_PORT_SWITCH\t= (1 << 1),\n+\tLTQ_ETH_PORT_MAC\t= (1 << 2),\n+};\n+\n+struct ltq_eth_port_config {\n+\tu8 num;\n+\tu8 phy_addr;\n+\tu16 flags;\n+\tphy_interface_t phy_if;\n+\tu8 rgmii_rx_delay;\n+\tu8 rgmii_tx_delay;\n+};\n+\n+struct ltq_eth_board_config {\n+\tconst struct ltq_eth_port_config *ports;\n+\tint num_ports;\n+};\n+\n+extern int ltq_eth_initialize(const struct ltq_eth_board_config *board_config);\n+\n+#endif /* __LANTIQ_ETH_H__ */\n--- /dev/null\n+++ b/arch/mips/include/asm/lantiq/gpio.h\n@@ -0,0 +1,50 @@\n+/*\n+ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#ifndef __LANTIQ_GPIO_H__\n+#define __LANTIQ_GPIO_H__\n+\n+enum ltq_gpio_dir {\n+\tGPIO_DIR_IN = 0,\n+\tGPIO_DIR_OUT\n+};\n+\n+enum ltq_gpio_od {\n+\tGPIO_OD_ACTIVE = 0,\n+\tGPIO_OD_NORMAL\n+};\n+\n+enum ltq_gpio_altsel {\n+\tGPIO_ALTSEL_CLR = 0,\n+\tGPIO_ALTSEL_SET\n+};\n+\n+extern int gpio_set_altfunc(unsigned gpio, int altsel0, int altsel1, int dir);\n+extern int gpio_set_opendrain(unsigned gpio, int od);\n+\n+static inline int gpio_to_port(unsigned gpio)\n+{\n+\treturn gpio >> 4;\n+}\n+\n+static inline int gpio_to_pin(unsigned gpio)\n+{\n+\treturn gpio & 0xF;\n+}\n+\n+static inline int gpio_to_bit(unsigned gpio)\n+{\n+\treturn 1 << gpio_to_pin(gpio);\n+}\n+\n+static inline int gpio_to_gpio(unsigned port, unsigned pin)\n+{\n+\treturn (port << 4) | (pin & 0xF);\n+}\n+\n+#include <asm-generic/gpio.h>\n+\n+#endif /* __LANTIQ_GPIO_H__ */\n--- /dev/null\n+++ b/arch/mips/include/asm/lantiq/io.h\n@@ -0,0 +1,37 @@\n+/*\n+ * Copyright (C) 2010 John Crispin <blogic@openwrt.org>\n+ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#ifndef __LANTIQ_IO_H__\n+#define __LANTIQ_IO_H__\n+\n+#include <asm/io.h>\n+\n+#define ltq_readb(a)\t\t__raw_readb(a)\n+#define ltq_writeb(a, v)\t__raw_writeb(v, a)\n+\n+#define ltq_readl(a)\t\t__raw_readl(a)\n+#define ltq_writel(a, v)\t__raw_writel(v, a)\n+\n+#define ltq_clrbits(a, clear) \\\n+\tltq_writel(a, ltq_readl(a) & ~(clear))\n+\n+#define ltq_setbits(a, set) \\\n+\tltq_writel(a, ltq_readl(a) | (set))\n+\n+#define ltq_clrsetbits(a, clear, set) \\\n+\tltq_writel(a, (ltq_readl(a) & ~(clear)) | (set))\n+\n+static inline void ltq_reg_dump(const void *addr, const char *desc)\n+{\n+\tu32 data;\n+\n+\tdata = ltq_readl(addr);\n+\tprintf(\"ltq_reg_dump: %s 0x%p = 0x%08x\\n\",\n+\t\tdesc, addr, data);\n+}\n+\n+#endif /* __LANTIQ_IO_H__ */\n--- /dev/null\n+++ b/arch/mips/include/asm/lantiq/pm.h\n@@ -0,0 +1,21 @@\n+/*\n+ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#ifndef __LANTIQ_PM_H__\n+#define __LANTIQ_PM_H__\n+\n+enum ltq_pm_modules {\n+\tLTQ_PM_CORE,\n+\tLTQ_PM_DMA,\n+\tLTQ_PM_ETH,\n+\tLTQ_PM_SPI,\n+};\n+\n+u32 ltq_pm_map(enum ltq_pm_modules module);\n+int ltq_pm_enable(enum ltq_pm_modules module);\n+int ltq_pm_disable(enum ltq_pm_modules module);\n+\n+#endif /* __LANTIQ_PM_H__ */\n--- /dev/null\n+++ b/arch/mips/include/asm/lantiq/reset.h\n@@ -0,0 +1,37 @@\n+/*\n+ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#ifndef __LANTIQ_RESET_H__\n+#define __LANTIQ_RESET_H__\n+\n+enum ltq_reset_modules {\n+\tLTQ_RESET_CORE,\n+\tLTQ_RESET_DMA,\n+\tLTQ_RESET_ETH,\n+\tLTQ_RESET_PHY,\n+\tLTQ_RESET_HARD,\n+\tLTQ_RESET_SOFT,\n+};\n+\n+extern u32 ltq_reset_map(enum ltq_reset_modules module);\n+extern int ltq_reset_activate(enum ltq_reset_modules module);\n+extern int ltq_reset_deactivate(enum ltq_reset_modules module);\n+\n+static inline int ltq_reset_once(enum ltq_reset_modules module, ulong usec)\n+{\n+\tint ret;\n+\n+\tret = ltq_reset_activate(module);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\t__udelay(usec);\n+\tret = ltq_reset_deactivate(module);\n+\n+\treturn ret;\n+}\n+\n+#endif /* __LANTIQ_RESET_H__ */\n--- a/arch/mips/include/asm/mipsregs.h\n+++ b/arch/mips/include/asm/mipsregs.h\n@@ -46,7 +46,10 @@\n #define CP0_ENTRYLO1 $3\n #define CP0_CONF $3\n #define CP0_CONTEXT $4\n+#define CP0_CONTEXTCONFIG $4,1\n+#define CP0_USERLOCAL $4,1\n #define CP0_PAGEMASK $5\n+#define CP0_PAGEGRAIN $5,1\n #define CP0_WIRED $6\n #define CP0_INFO $7\n #define CP0_BADVADDR $8\n@@ -54,10 +57,19 @@\n #define CP0_ENTRYHI $10\n #define CP0_COMPARE $11\n #define CP0_STATUS $12\n+#define CP0_INTCTL $12,1\n+#define CP0_SRSCTL $12,2\n+#define CP0_SRSMAP $12,3\n+#define CP0_SRSHIGH $12,4\n #define CP0_CAUSE $13\n #define CP0_EPC $14\n #define CP0_PRID $15\n+#define CP0_EBASE $15,1\n #define CP0_CONFIG $16\n+#define CP0_CONFIG1 $16,1\n+#define CP0_CONFIG2 $16,2\n+#define CP0_CONFIG3 $16,3\n+#define CP0_CONFIG7 $16,7\n #define CP0_LLADDR $17\n #define CP0_WATCHLO $18\n #define CP0_WATCHHI $19\n@@ -70,7 +82,17 @@\n #define CP0_ECC $26\n #define CP0_CACHEERR $27\n #define CP0_TAGLO $28\n+#define CP0_ITAGLO $28\n+#define CP0_IDATALO $28,1\n+#define CP0_DTAGLO $28,2\n+#define CP0_DDATALO $28,3\n+#define CP0_L23TAGLO $28,4\n+#define CP0_L23DATALO $28,5\n #define CP0_TAGHI $29\n+#define CP0_IDATAHI $29,1\n+#define CP0_DTAGHI $29,2\n+#define CP0_L23TAGHI $29,4\n+#define CP0_L23DATAHI $29,5\n #define CP0_ERROREPC $30\n #define CP0_DESAVE $31\n \n@@ -395,6 +417,12 @@\n #define  CAUSEF_BD\t\t(_ULCAST_(1)   << 31)\n \n /*\n+ * Bits in the coprocessor 0 EBase register.\n+ */\n+#define EBASEB_CPUNUM\t\t0\n+#define EBASEF_CPUNUM\t\t(_ULCAST_(1023))\n+\n+/*\n  * Bits in the coprocessor 0 config register.\n  */\n /* Generic bits.  */\n--- a/arch/mips/include/asm/u-boot-mips.h\n+++ b/arch/mips/include/asm/u-boot-mips.h\n@@ -23,3 +23,4 @@ static inline unsigned long image_copy_e\n }\n \n extern int incaip_set_cpuclk(void);\n+extern int arch_cpu_init(void);\n--- a/arch/mips/lib/board.c\n+++ b/arch/mips/lib/board.c\n@@ -33,6 +33,16 @@ static char *failed = \"*** failed ***\\n\"\n  */\n const unsigned long mips_io_port_base = -1;\n \n+int __arch_cpu_init(void)\n+{\n+\t/*\n+\t * Nothing to do in this dummy implementation\n+\t */\n+\treturn 0;\n+}\n+int arch_cpu_init(void)\n+\t__attribute__((weak, alias(\"__arch_cpu_init\")));\n+\n int __board_early_init_f(void)\n {\n \t/*\n@@ -106,6 +116,7 @@ static int init_baudrate(void)\n typedef int (init_fnc_t)(void);\n \n init_fnc_t *init_sequence[] = {\n+\tarch_cpu_init,\n \tboard_early_init_f,\n \ttimer_init,\n \tenv_init,\t\t/* initialize environment */\n--- a/drivers/dma/Makefile\n+++ b/drivers/dma/Makefile\n@@ -12,6 +12,7 @@ LIB\t:= $(obj)libdma.o\n COBJS-$(CONFIG_FSLDMAFEC) += MCD_tasksInit.o MCD_dmaApi.o MCD_tasks.o\n COBJS-$(CONFIG_APBH_DMA) += apbh_dma.o\n COBJS-$(CONFIG_FSL_DMA) += fsl_dma.o\n+COBJS-$(CONFIG_LANTIQ_DMA) += lantiq_dma.o\n COBJS-$(CONFIG_OMAP3_DMA) += omap3_dma.o\n \n COBJS\t:= $(COBJS-y)\n--- /dev/null\n+++ b/drivers/dma/lantiq_dma.c\n@@ -0,0 +1,387 @@\n+/*\n+ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#include <common.h>\n+#include <malloc.h>\n+#include <watchdog.h>\n+#include <linux/compiler.h>\n+#include <asm/lantiq/io.h>\n+#include <asm/lantiq/dma.h>\n+#include <asm/lantiq/pm.h>\n+#include <asm/lantiq/reset.h>\n+#include <asm/arch/soc.h>\n+#include <asm/processor.h>\n+\n+#define DMA_CTRL_PKTARB\t\t\t(1 << 31)\n+#define DMA_CTRL_MBRSTARB\t\t(1 << 30)\n+#define DMA_CTRL_MBRSTCNT_SHIFT\t\t16\n+#define DMA_CTRL_MBRSTCNT_MASK\t\t(0x3ff << DMA_CTRL_MBRSTCNT_SHIFT)\n+#define DMA_CTRL_DRB\t\t\t(1 << 8)\n+#define DMA_CTRL_RESET\t\t\t(1 << 0)\n+\n+#define DMA_CPOLL_EN\t\t\t(1 << 31)\n+#define DMA_CPOLL_CNT_SHIFT\t\t4\n+#define DMA_CPOLL_CNT_MASK\t\t(0xFFF << DMA_CPOLL_CNT_SHIFT)\n+\n+#define DMA_CCTRL_TXWGT_SHIFT\t\t16\n+#define DMA_CCTRL_TXWGT_MASK\t\t(0x3 << DMA_CCTRL_TXWGT_SHIFT)\n+#define DMA_CCTRL_CLASS_SHIFT\t\t9\n+#define DMA_CCTRL_CLASS_MASK\t\t(0x3 << DMA_CCTRL_CLASS_SHIFT)\n+#define DMA_CCTRL_RST\t\t\t(1 << 1)\n+#define DMA_CCTRL_ONOFF\t\t\t(1 << 0)\n+\n+#define DMA_PCTRL_TXBL_SHIFT\t\t4\n+#define DMA_PCTRL_TXBL_2WORDS\t\t(1 << DMA_PCTRL_TXBL_SHIFT)\n+#define DMA_PCTRL_TXBL_4WORDS\t\t(2 << DMA_PCTRL_TXBL_SHIFT)\n+#define DMA_PCTRL_TXBL_8WORDS\t\t(3 << DMA_PCTRL_TXBL_SHIFT)\n+#define DMA_PCTRL_RXBL_SHIFT\t\t2\n+#define DMA_PCTRL_RXBL_2WORDS\t\t(1 << DMA_PCTRL_RXBL_SHIFT)\n+#define DMA_PCTRL_RXBL_4WORDS\t\t(2 << DMA_PCTRL_RXBL_SHIFT)\n+#define DMA_PCTRL_RXBL_8WORDS\t\t(3 << DMA_PCTRL_RXBL_SHIFT)\n+#define DMA_PCTRL_TXENDI_SHIFT\t\t10\n+#define DMA_PCTRL_TXENDI_MASK\t\t(0x3 << DMA_PCTRL_TXENDI_SHIFT)\n+#define DMA_PCTRL_RXENDI_SHIFT\t\t8\n+#define DMA_PCTRL_RXENDI_MASK\t\t(0x3 << DMA_PCTRL_RXENDI_SHIFT)\n+\n+#define DMA_DESC_OWN\t\t\t(1 << 31)\n+#define DMA_DESC_C\t\t\t(1 << 30)\n+#define DMA_DESC_SOP\t\t\t(1 << 29)\n+#define DMA_DESC_EOP\t\t\t(1 << 28)\n+#define DMA_DESC_TX_OFFSET(x)\t\t((x & 0x1f) << 23)\n+#define DMA_DESC_RX_OFFSET(x)\t\t((x & 0x3) << 23)\n+#define DMA_DESC_LENGTH(x)\t\t(x & 0xffff)\n+\n+#define PTR_ALIGN(p, a)\t\t((typeof(p))ALIGN((unsigned long)(p), (a)))\n+\n+struct ltq_dma_regs {\n+\tu32\tclc;\t\t/* Clock control */\n+\tu32\trsvd0;\n+\tu32\tid;\t\t/* Identification */\n+\tu32\trsvd1;\n+\tu32\tctrl;\t\t/* Control */\n+\tu32\tcpoll;\t\t/* Channel polling */\n+\tu32\tcs;\t\t/* Channel select */\n+\tu32\tcctrl;\t\t/* Channel control */\n+\tu32\tcdba;\t\t/* Channel descriptor base address */\n+\tu32\tcdlen;\t\t/* Channel descriptor length */\n+\tu32\tcis;\t\t/* Channel interrupt status */\n+\tu32\tcie;\t\t/* Channel interrupt enable */\n+\tu32\tcgbl;\t\t/* Channel global buffer length */\n+\tu32\tcdptnrd;\t/* Current descriptor pointer */\n+\tu32\trsvd2[2];\n+\tu32\tps;\t\t/* Port select */\n+\tu32\tpctrl;\t\t/* Port control */\n+\tu32\trsvd3[43];\n+\tu32\tirnen;\t\t/* Interrupt node enable */\n+\tu32\tirncr;\t\t/* Interrupt node control */\n+\tu32\tirnicr;\t\t/* Interrupt capture */\n+};\n+\n+static struct ltq_dma_regs *ltq_dma_regs =\n+\t(struct ltq_dma_regs *) CKSEG1ADDR(LTQ_DMA_BASE);\n+\n+static inline unsigned long ltq_dma_addr_to_virt(u32 dma_addr)\n+{\n+\treturn KSEG0ADDR(dma_addr);\n+}\n+\n+static inline u32 ltq_virt_to_dma_addr(void *addr)\n+{\n+\treturn CPHYSADDR(addr);\n+}\n+\n+static inline int ltq_dma_burst_align(enum ltq_dma_burst_len burst_len)\n+{\n+\tswitch (burst_len) {\n+\tcase LTQ_DMA_BURST_2WORDS:\n+\t\treturn 2 * 4;\n+\tcase LTQ_DMA_BURST_4WORDS:\n+\t\treturn 4 * 4;\n+\tcase LTQ_DMA_BURST_8WORDS:\n+\t\treturn 8 * 4;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static inline void ltq_dma_sync(void)\n+{\n+\t__asm__ __volatile__(\"sync\");\n+}\n+\n+static inline void ltq_dma_dcache_wb_inv(const void *ptr, size_t size)\n+{\n+\tunsigned long addr = (unsigned long) ptr;\n+\n+\tflush_dcache_range(addr, addr + size);\n+\tltq_dma_sync();\n+}\n+\n+static inline void ltq_dma_dcache_inv(const void *ptr, size_t size)\n+{\n+\tunsigned long addr = (unsigned long) ptr;\n+\n+\tinvalidate_dcache_range(addr, addr + size);\n+}\n+\n+void ltq_dma_init(void)\n+{\n+\t/* Power up DMA */\n+\tltq_pm_enable(LTQ_PM_DMA);\n+\n+\t/* Reset DMA */\n+\tltq_setbits(&ltq_dma_regs->ctrl, DMA_CTRL_RESET);\n+\n+\t/* Disable and clear all interrupts */\n+\tltq_writel(&ltq_dma_regs->irnen, 0);\n+\tltq_writel(&ltq_dma_regs->irncr, 0xFFFFF);\n+\n+#if 0\n+\t/* Enable packet arbitration */\n+\tltq_setbits(&ltq_dma_regs->ctrl, DMA_CTRL_PKTARB);\n+#endif\n+\n+#if 0\n+\t/* Enable descriptor read back */\n+\tltq_setbits(&ltq_dma_regs->ctrl, DMA_CTRL_DRB);\n+#endif\n+\n+\t/* Enable polling for descriptor fetching for all channels */\n+\tltq_writel(&ltq_dma_regs->cpoll, DMA_CPOLL_EN |\n+\t\t(4 << DMA_CPOLL_CNT_SHIFT));\n+}\n+\n+static void ltq_dma_channel_reset(struct ltq_dma_channel *chan)\n+{\n+\tltq_writel(&ltq_dma_regs->cs, chan->chan_no);\n+\tltq_setbits(&ltq_dma_regs->cctrl, DMA_CCTRL_RST);\n+}\n+\n+static void ltq_dma_channel_enable(struct ltq_dma_channel *chan)\n+{\n+\tltq_writel(&ltq_dma_regs->cs, chan->chan_no);\n+\tltq_setbits(&ltq_dma_regs->cctrl, DMA_CCTRL_ONOFF);\n+}\n+\n+static void ltq_dma_channel_disable(struct ltq_dma_channel *chan)\n+{\n+\tltq_writel(&ltq_dma_regs->cs, chan->chan_no);\n+\tltq_clrbits(&ltq_dma_regs->cctrl, DMA_CCTRL_ONOFF);\n+}\n+\n+static void ltq_dma_port_init(struct ltq_dma_device *dev)\n+{\n+\tu32 pctrl;\n+\n+\tpctrl = dev->tx_endian_swap << DMA_PCTRL_TXENDI_SHIFT;\n+\tpctrl |= dev->rx_endian_swap << DMA_PCTRL_RXENDI_SHIFT;\n+\tpctrl |= dev->tx_burst_len << DMA_PCTRL_TXBL_SHIFT;\n+\tpctrl |= dev->rx_burst_len << DMA_PCTRL_RXBL_SHIFT;\n+\n+\tltq_writel(&ltq_dma_regs->ps, dev->port);\n+\tltq_writel(&ltq_dma_regs->pctrl, pctrl);\n+}\n+\n+static int ltq_dma_alloc_descriptors(struct ltq_dma_device *dev,\n+\t\t\t\t\tstruct ltq_dma_channel *chan)\n+{\n+\tsize_t size;\n+\tvoid *desc_base;\n+\n+\tsize = ALIGN(sizeof(struct ltq_dma_desc) * chan->num_desc +\n+\t\t\tARCH_DMA_MINALIGN, ARCH_DMA_MINALIGN);\n+\n+\tchan->mem_base = malloc(size);\n+\tif (!chan->mem_base)\n+\t\treturn 1;\n+\n+\tmemset(chan->mem_base, 0, size);\n+\tltq_dma_dcache_wb_inv(chan->mem_base, size);\n+\n+\tdesc_base = PTR_ALIGN(chan->mem_base, ARCH_DMA_MINALIGN);\n+\n+\tdebug(\"DMA: mem %p, desc %p\\n\", chan->mem_base, desc_base);\n+\n+\t/* Align descriptor base to 8 bytes */\n+\tchan->desc_base = (void *) CKSEG1ADDR(desc_base);\n+\tchan->dma_addr = CPHYSADDR(desc_base);\n+\tchan->dev = dev;\n+\n+\tdebug(\"DMA: desc_base %p, size %u\\n\", chan->desc_base, size);\n+\n+\t/* Configure hardware with location of descriptor list */\n+\tltq_writel(&ltq_dma_regs->cs, chan->chan_no);\n+\tltq_writel(&ltq_dma_regs->cdba, chan->dma_addr);\n+\tltq_writel(&ltq_dma_regs->cdlen, chan->num_desc);\n+\tltq_writel(&ltq_dma_regs->cctrl, (3 << DMA_CCTRL_TXWGT_SHIFT) |\n+\t\t(chan->class << DMA_CCTRL_CLASS_SHIFT));\n+\tltq_writel(&ltq_dma_regs->cctrl, DMA_CCTRL_RST);\n+\n+\treturn 0;\n+}\n+\n+static void ltq_dma_free_descriptors(struct ltq_dma_channel *chan)\n+{\n+\tltq_writel(&ltq_dma_regs->cs, chan->chan_no);\n+\tltq_writel(&ltq_dma_regs->cdba, 0);\n+\tltq_writel(&ltq_dma_regs->cdlen, 0);\n+\n+\tltq_dma_channel_reset(chan);\n+\n+\tfree(chan->mem_base);\n+}\n+\n+int ltq_dma_register(struct ltq_dma_device *dev)\n+{\n+\tint ret;\n+\n+\tltq_dma_port_init(dev);\n+\n+\tret = ltq_dma_alloc_descriptors(dev, &dev->rx_chan);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = ltq_dma_alloc_descriptors(dev, &dev->tx_chan);\n+\tif (ret) {\n+\t\tltq_dma_free_descriptors(&dev->rx_chan);\n+\t\treturn ret;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+void ltq_dma_reset(struct ltq_dma_device *dev)\n+{\n+\tltq_dma_channel_reset(&dev->rx_chan);\n+\tltq_dma_channel_reset(&dev->tx_chan);\n+}\n+\n+void ltq_dma_enable(struct ltq_dma_device *dev)\n+{\n+\tltq_dma_channel_enable(&dev->rx_chan);\n+\tltq_dma_channel_enable(&dev->tx_chan);\n+}\n+\n+void ltq_dma_disable(struct ltq_dma_device *dev)\n+{\n+\tltq_dma_channel_disable(&dev->rx_chan);\n+\tltq_dma_channel_disable(&dev->tx_chan);\n+}\n+\n+int ltq_dma_rx_map(struct ltq_dma_device *dev, int index, void *data, int len)\n+{\n+\tstruct ltq_dma_channel *chan = &dev->rx_chan;\n+\tstruct ltq_dma_desc *desc = &chan->desc_base[index];\n+\tu32 dma_addr = ltq_virt_to_dma_addr(data);\n+\tunsigned int offset;\n+\n+\toffset = dma_addr % ltq_dma_burst_align(dev->rx_burst_len);\n+\n+\tltq_dma_dcache_inv(data, len);\n+\n+#if 0\n+\tprintf(\"%s: index %d, data %p, dma_addr %08x, offset %u, len %d\\n\",\n+\t\t__func__, index, data, dma_addr, offset, len);\n+#endif\n+\n+\n+\tdesc->addr = dma_addr - offset;\n+\tdesc->ctl = DMA_DESC_OWN | DMA_DESC_RX_OFFSET(offset) |\n+\t\t\tDMA_DESC_LENGTH(len);\n+\n+#if 0\n+\tprintf(\"%s: index %d, desc %p, desc->ctl %08x\\n\",\n+\t\t__func__, index, desc, desc->ctl);\n+#endif\n+\n+\treturn 0;\n+}\n+\n+int ltq_dma_rx_poll(struct ltq_dma_device *dev, int index)\n+{\n+\tstruct ltq_dma_channel *chan = &dev->rx_chan;\n+\tstruct ltq_dma_desc *desc = &chan->desc_base[index];\n+\n+#if 0\n+\tprintf(\"%s: index %d, desc %p, desc->ctl %08x\\n\",\n+\t\t__func__, index, desc, desc->ctl);\n+#endif\n+\n+\tif (desc->ctl & DMA_DESC_OWN)\n+\t\treturn 0;\n+\n+\tif (desc->ctl & DMA_DESC_C)\n+\t\treturn 1;\n+\n+\treturn 0;\n+}\n+\n+int ltq_dma_rx_length(struct ltq_dma_device *dev, int index)\n+{\n+\tstruct ltq_dma_channel *chan = &dev->rx_chan;\n+\tstruct ltq_dma_desc *desc = &chan->desc_base[index];\n+\n+\treturn DMA_DESC_LENGTH(desc->ctl);\n+}\n+\n+int ltq_dma_tx_map(struct ltq_dma_device *dev, int index, void *data, int len,\n+\t\t\tunsigned long timeout)\n+{\n+\tstruct ltq_dma_channel *chan = &dev->tx_chan;\n+\tstruct ltq_dma_desc *desc = &chan->desc_base[index];\n+\tunsigned int offset;\n+\tunsigned long timebase = get_timer(0);\n+\tu32 dma_addr = ltq_virt_to_dma_addr(data);\n+\n+\twhile (desc->ctl & DMA_DESC_OWN) {\n+\t\tWATCHDOG_RESET();\n+\n+\t\tif (get_timer(timebase) >= timeout) {\n+#if 0\n+\t\t\tprintf(\"%s: timeout: index %d, desc %p, desc->ctl %08x\\n\",\n+\t\t\t\t__func__, index, desc, desc->ctl);\n+#endif\n+\t\t\treturn -1;\n+\t\t}\n+\t}\n+\n+\toffset = dma_addr % ltq_dma_burst_align(dev->rx_burst_len);\n+\n+#if 0\n+\tprintf(\"%s: index %d, desc %p, data %p, dma_addr %08x, offset %u, len %d\\n\",\n+\t\t__func__, index, desc, data, dma_addr, offset, len);\n+#endif\n+\n+\tltq_dma_dcache_wb_inv(data, len);\n+\n+\tdesc->addr = dma_addr - offset;\n+\tdesc->ctl = DMA_DESC_OWN | DMA_DESC_SOP | DMA_DESC_EOP |\n+\t\t\tDMA_DESC_TX_OFFSET(offset) | DMA_DESC_LENGTH(len);\n+\n+#if 0\n+\tprintf(\"%s: index %d, desc %p, desc->ctl %08x\\n\",\n+\t\t__func__, index, desc, desc->ctl);\n+#endif\n+\n+\treturn 0;\n+}\n+\n+int ltq_dma_tx_wait(struct ltq_dma_device *dev, int index,\n+\t\t\tunsigned long timeout)\n+{\n+\tstruct ltq_dma_channel *chan = &dev->tx_chan;\n+\tstruct ltq_dma_desc *desc = &chan->desc_base[index];\n+\tunsigned long timebase = get_timer(0);\n+\n+\twhile ((desc->ctl & (DMA_DESC_OWN | DMA_DESC_C)) != DMA_DESC_C) {\n+\t\tWATCHDOG_RESET();\n+\n+\t\tif (get_timer(timebase) >= timeout)\n+\t\t\treturn -1;\n+\t}\n+\n+\treturn 0;\n+}\n--- a/drivers/gpio/Makefile\n+++ b/drivers/gpio/Makefile\n@@ -12,6 +12,7 @@ LIB \t:= $(obj)libgpio.o\n COBJS-$(CONFIG_AT91_GPIO)\t+= at91_gpio.o\n COBJS-$(CONFIG_INTEL_ICH6_GPIO)\t+= intel_ich6_gpio.o\n COBJS-$(CONFIG_KIRKWOOD_GPIO)\t+= kw_gpio.o\n+COBJS-$(CONFIG_LANTIQ_GPIO)\t+= lantiq_gpio.o\n COBJS-$(CONFIG_MARVELL_GPIO)\t+= mvgpio.o\n COBJS-$(CONFIG_MARVELL_MFP)\t+= mvmfp.o\n COBJS-$(CONFIG_MXC_GPIO)\t+= mxc_gpio.o\n--- /dev/null\n+++ b/drivers/gpio/lantiq_gpio.c\n@@ -0,0 +1,329 @@\n+/*\n+ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#include <common.h>\n+#include <asm/arch/soc.h>\n+#include <asm/arch/gpio.h>\n+#include <asm/lantiq/io.h>\n+\n+#define SSIO_GPIO_BASE\t\t64\n+\n+#define SSIO_CON0_SWU\t\t(1 << 31)\n+#define SSIO_CON0_RZFL\t\t(1 << 26)\n+#define SSIO_CON0_GPHY1_SHIFT\t27\n+#define SSIO_CON0_GPHY1_CONFIG\t((CONFIG_LTQ_SSIO_GPHY1_MODE & 0x7) << 27)\n+\n+#define SSIO_CON1_US_FPI\t(2 << 30)\n+#define SSIO_CON1_FPID_2HZ\t(0 << 23)\n+#define SSIO_CON1_FPID_4HZ\t(1 << 23)\n+#define SSIO_CON1_FPID_8HZ\t(2 << 23)\n+#define SSIO_CON1_FPID_10HZ\t(3 << 23)\n+#define SSIO_CON1_FPIS_1_2\t(1 << 20)\n+#define SSIO_CON1_FPIS_1_32\t(2 << 20)\n+#define SSIO_CON1_FPIS_1_64\t(3 << 20)\n+\n+#define SSIO_CON1_GPHY2_SHIFT\t15\n+#define SSIO_CON1_GPHY2_CONFIG\t((CONFIG_LTQ_SSIO_GPHY2_MODE & 0x7) << 15)\n+\n+#define SSIO_CON1_GROUP2\t(1 << 2)\n+#define SSIO_CON1_GROUP1\t(1 << 1)\n+#define SSIO_CON1_GROUP0\t(1 << 0)\n+#define SSIO_CON1_GROUP_CONFIG\t(0x3)\n+\n+#ifdef CONFIG_LTQ_SSIO_SHIFT_REGS\n+#define enable_ssio\t1\n+#else\n+#define enable_ssio\t0\n+\n+#define CONFIG_LTQ_SSIO_GPHY1_MODE\t0\n+#define CONFIG_LTQ_SSIO_GPHY2_MODE\t0\n+#define CONFIG_LTQ_SSIO_INIT_VALUE\t0\n+#endif\n+\n+#ifdef CONFIG_LTQ_SSIO_EDGE_FALLING\n+#define SSIO_RZFL_CONFIG\tSSIO_CON0_RZFL\n+#else\n+#define SSIO_RZFL_CONFIG\t0\n+#endif\n+\n+struct ltq_gpio_port_regs {\n+\t__be32\tout;\n+\t__be32\tin;\n+\t__be32\tdir;\n+\t__be32\taltsel0;\n+\t__be32\taltsel1;\n+\t__be32\tod;\n+\t__be32\tstoff;\n+\t__be32\tpudsel;\n+\t__be32\tpuden;\n+\t__be32\trsvd1[3];\n+};\n+\n+struct ltq_gpio_regs {\n+\tu32\t\t\t\trsvd[4];\n+\tstruct ltq_gpio_port_regs\tports[CONFIG_LTQ_GPIO_MAX_BANKS];\n+};\n+\n+struct ltq_gpio3_regs {\n+\tu32\trsvd0[13];\n+\t__be32\tod;\n+\t__be32\tpudsel;\n+\t__be32\tpuden;\n+\tu32\trsvd1[9];\n+\t__be32\taltsel1;\n+\tu32\trsvd2[14];\n+\t__be32\tout;\n+\t__be32\tin;\n+\t__be32\tdir;\n+\t__be32\taltsel0;\n+};\n+\n+struct ltq_ssio_regs {\n+\t__be32\tcon0;\n+\t__be32\tcon1;\n+\t__be32\tcpu0;\n+\t__be32\tcpu1;\n+\t__be32\tar;\n+};\n+\n+static struct ltq_gpio_regs *ltq_gpio_regs =\n+\t(struct ltq_gpio_regs *) CKSEG1ADDR(LTQ_GPIO_BASE);\n+\n+static struct ltq_gpio3_regs *ltq_gpio3_regs =\n+\t(struct ltq_gpio3_regs *) CKSEG1ADDR(LTQ_GPIO_BASE);\n+\n+static struct ltq_ssio_regs *ltq_ssio_regs =\n+\t(struct ltq_ssio_regs *) CKSEG1ADDR(LTQ_SSIO_BASE);\n+\n+static int is_gpio_bank3(unsigned int port)\n+{\n+#ifdef CONFIG_LTQ_HAS_GPIO_BANK3\n+\treturn port == 3;\n+#else\n+\treturn 0;\n+#endif\n+}\n+\n+static int is_gpio_ssio(unsigned int gpio)\n+{\n+#ifdef CONFIG_LTQ_SSIO_SHIFT_REGS\n+\treturn gpio >= SSIO_GPIO_BASE;\n+#else\n+\treturn 0;\n+#endif\n+}\n+\n+static inline int ssio_gpio_to_bit(unsigned gpio)\n+{\n+\treturn 1 << (gpio - SSIO_GPIO_BASE);\n+}\n+\n+int ltq_gpio_init(void)\n+{\n+\tltq_writel(&ltq_ssio_regs->ar, 0);\n+\tltq_writel(&ltq_ssio_regs->cpu0, CONFIG_LTQ_SSIO_INIT_VALUE);\n+\tltq_writel(&ltq_ssio_regs->cpu1, 0);\n+\tltq_writel(&ltq_ssio_regs->con0, SSIO_CON0_SWU);\n+\n+\tif (enable_ssio) {\n+\t\tltq_writel(&ltq_ssio_regs->con0, SSIO_CON0_GPHY1_CONFIG |\n+\t\t\tSSIO_RZFL_CONFIG);\n+\t\tltq_writel(&ltq_ssio_regs->con1, SSIO_CON1_US_FPI |\n+\t\t\tSSIO_CON1_FPID_8HZ | SSIO_CON1_GPHY2_CONFIG |\n+\t\t\tSSIO_CON1_GROUP_CONFIG);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+int gpio_request(unsigned gpio, const char *label)\n+{\n+\treturn 0;\n+}\n+\n+int gpio_free(unsigned gpio)\n+{\n+\treturn 0;\n+}\n+\n+int gpio_direction_input(unsigned gpio)\n+{\n+\tunsigned port = gpio_to_port(gpio);\n+\tconst void *gpio_od = &ltq_gpio_regs->ports[port].od;\n+\tconst void *gpio_altsel0 = &ltq_gpio_regs->ports[port].altsel0;\n+\tconst void *gpio_altsel1 = &ltq_gpio_regs->ports[port].altsel1;\n+\tconst void *gpio_dir = &ltq_gpio_regs->ports[port].dir;\n+\n+\tif (is_gpio_ssio(gpio))\n+\t\treturn 0;\n+\n+\tif (is_gpio_bank3(port)) {\n+\t\tgpio_od = &ltq_gpio3_regs->od;\n+\t\tgpio_altsel0 = &ltq_gpio3_regs->altsel0;\n+\t\tgpio_altsel1 = &ltq_gpio3_regs->altsel1;\n+\t\tgpio_dir = &ltq_gpio3_regs->dir;\n+\t}\n+\n+\t/*\n+\t * Reset open drain and altsel configs to workaround improper\n+\t * reset values or unwanted modifications by BootROM\n+\t */\n+\tltq_clrbits(gpio_od, gpio_to_bit(gpio));\n+\tltq_clrbits(gpio_altsel0, gpio_to_bit(gpio));\n+\tltq_clrbits(gpio_altsel1, gpio_to_bit(gpio));\n+\n+\t/* Switch to input */\n+\tltq_clrbits(gpio_dir, gpio_to_bit(gpio));\n+\n+\treturn 0;\n+}\n+\n+int gpio_direction_output(unsigned gpio, int value)\n+{\n+\tunsigned port = gpio_to_port(gpio);\n+\tconst void *gpio_od = &ltq_gpio_regs->ports[port].od;\n+\tconst void *gpio_altsel0 = &ltq_gpio_regs->ports[port].altsel0;\n+\tconst void *gpio_altsel1 = &ltq_gpio_regs->ports[port].altsel1;\n+\tconst void *gpio_dir = &ltq_gpio_regs->ports[port].dir;\n+\tconst void *gpio_out = &ltq_gpio_regs->ports[port].out;\n+\tu32 data = gpio_to_bit(gpio);\n+\n+\tif (is_gpio_ssio(gpio)) {\n+\t\tdata = ssio_gpio_to_bit(gpio);\n+\t\tif (value)\n+\t\t\tltq_setbits(&ltq_ssio_regs->cpu0, data);\n+\t\telse\n+\t\t\tltq_clrbits(&ltq_ssio_regs->cpu0, data);\n+\n+\t\treturn 0;\n+\t}\n+\n+\tif (is_gpio_bank3(port)) {\n+\t\tgpio_od = &ltq_gpio3_regs->od;\n+\t\tgpio_altsel0 = &ltq_gpio3_regs->altsel0;\n+\t\tgpio_altsel1 = &ltq_gpio3_regs->altsel1;\n+\t\tgpio_dir = &ltq_gpio3_regs->dir;\n+\t\tgpio_out = &ltq_gpio3_regs->out;\n+\t}\n+\n+\t/*\n+\t * Reset open drain and altsel configs to workaround improper\n+\t * reset values or unwanted modifications by BootROM\n+\t */\n+\tltq_setbits(gpio_od, data);\n+\tltq_clrbits(gpio_altsel0, data);\n+\tltq_clrbits(gpio_altsel1, data);\n+\n+\tif (value)\n+\t\tltq_setbits(gpio_out, data);\n+\telse\n+\t\tltq_clrbits(gpio_out, data);\n+\n+\t/* Switch to output */\n+\tltq_setbits(gpio_dir, data);\n+\n+\treturn 0;\n+}\n+\n+int gpio_get_value(unsigned gpio)\n+{\n+\tunsigned port = gpio_to_port(gpio);\n+\tconst void *gpio_in = &ltq_gpio_regs->ports[port].in;\n+\tu32 data = gpio_to_bit(gpio);\n+\tu32 val;\n+\n+\tif (is_gpio_ssio(gpio)) {\n+\t\tgpio_in = &ltq_ssio_regs->cpu0;\n+\t\tdata = ssio_gpio_to_bit(gpio);\n+\t}\n+\n+\tif (is_gpio_bank3(port))\n+\t\tgpio_in = &ltq_gpio3_regs->in;\n+\n+\tval = ltq_readl(gpio_in);\n+\n+\treturn !!(val & data);\n+}\n+\n+int gpio_set_value(unsigned gpio, int value)\n+{\n+\tunsigned port = gpio_to_port(gpio);\n+\tconst void *gpio_out = &ltq_gpio_regs->ports[port].out;\n+\tu32 data = gpio_to_bit(gpio);\n+\n+\tif (is_gpio_ssio(gpio)) {\n+\t\tgpio_out = &ltq_ssio_regs->cpu0;\n+\t\tdata = ssio_gpio_to_bit(gpio);\n+\t}\n+\n+\tif (is_gpio_bank3(port))\n+\t\tgpio_out = &ltq_gpio3_regs->out;\n+\n+\tif (value)\n+\t\tltq_setbits(gpio_out, data);\n+\telse\n+\t\tltq_clrbits(gpio_out, data);\n+\n+\treturn 0;\n+}\n+\n+int gpio_set_altfunc(unsigned gpio, int altsel0, int altsel1, int dir)\n+{\n+\tunsigned port = gpio_to_port(gpio);\n+\tconst void *gpio_od = &ltq_gpio_regs->ports[port].od;\n+\tconst void *gpio_altsel0 = &ltq_gpio_regs->ports[port].altsel0;\n+\tconst void *gpio_altsel1 = &ltq_gpio_regs->ports[port].altsel1;\n+\tconst void *gpio_dir = &ltq_gpio_regs->ports[port].dir;\n+\n+\tif (is_gpio_ssio(gpio))\n+\t\treturn 0;\n+\n+\tif (is_gpio_bank3(port)) {\n+\t\tgpio_od = &ltq_gpio3_regs->od;\n+\t\tgpio_altsel0 = &ltq_gpio3_regs->altsel0;\n+\t\tgpio_altsel1 = &ltq_gpio3_regs->altsel1;\n+\t\tgpio_dir = &ltq_gpio3_regs->dir;\n+\t}\n+\n+\tif (altsel0)\n+\t\tltq_setbits(gpio_altsel0, gpio_to_bit(gpio));\n+\telse\n+\t\tltq_clrbits(gpio_altsel0, gpio_to_bit(gpio));\n+\n+\tif (altsel1)\n+\t\tltq_setbits(gpio_altsel1, gpio_to_bit(gpio));\n+\telse\n+\t\tltq_clrbits(gpio_altsel1, gpio_to_bit(gpio));\n+\n+\tif (dir) {\n+\t\tltq_setbits(gpio_od, gpio_to_bit(gpio));\n+\t\tltq_setbits(gpio_dir, gpio_to_bit(gpio));\n+\t} else {\n+\t\tltq_clrbits(gpio_od, gpio_to_bit(gpio));\n+\t\tltq_clrbits(gpio_dir, gpio_to_bit(gpio));\n+\t}\n+\n+\treturn 0;\n+}\n+\n+int gpio_set_opendrain(unsigned gpio, int od)\n+{\n+\tunsigned port = gpio_to_port(gpio);\n+\tconst void *gpio_od = &ltq_gpio_regs->ports[port].od;\n+\n+\tif (is_gpio_ssio(gpio))\n+\t\treturn 0;\n+\n+\tif (is_gpio_bank3(port))\n+\t\tgpio_od = &ltq_gpio3_regs->od;\n+\n+\tif (od)\n+\t\tltq_setbits(gpio_od, gpio_to_bit(gpio));\n+\telse\n+\t\tltq_clrbits(gpio_od, gpio_to_bit(gpio));\n+\n+\treturn 0;\n+}\n--- a/drivers/mtd/cfi_flash.c\n+++ b/drivers/mtd/cfi_flash.c\n@@ -161,6 +161,18 @@ u64 flash_read64(void *addr)__attribute_\n #define flash_read64\t__flash_read64\n #endif\n \n+static inline void *__flash_swap_addr(unsigned long addr)\n+{\n+\treturn (void *) addr;\n+}\n+\n+#ifdef CONFIG_CFI_FLASH_USE_WEAK_ADDR_SWAP\n+void *flash_swap_addr(unsigned long addr)\n+\t\t__attribute__((weak, alias(\"__flash_swap_addr\")));\n+#else\n+#define flash_swap_addr\t__flash_swap_addr\n+#endif\n+\n /*-----------------------------------------------------------------------\n  */\n #if defined(CONFIG_ENV_IS_IN_FLASH) || defined(CONFIG_ENV_ADDR_REDUND) || (CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE)\n@@ -196,7 +208,7 @@ flash_map (flash_info_t * info, flash_se\n {\n \tunsigned int byte_offset = offset * info->portwidth;\n \n-\treturn (void *)(info->start[sect] + byte_offset);\n+\treturn flash_swap_addr(info->start[sect] + byte_offset);\n }\n \n static inline void flash_unmap(flash_info_t *info, flash_sect_t sect,\n--- a/drivers/mtd/nand/Makefile\n+++ b/drivers/mtd/nand/Makefile\n@@ -53,6 +53,7 @@ COBJS-$(CONFIG_NAND_JZ4740) += jz4740_na\n COBJS-$(CONFIG_NAND_KB9202) += kb9202_nand.o\n COBJS-$(CONFIG_NAND_KIRKWOOD) += kirkwood_nand.o\n COBJS-$(CONFIG_NAND_KMETER1) += kmeter1_nand.o\n+COBJS-$(CONFIG_NAND_LANTIQ) += lantiq_nand.o\n COBJS-$(CONFIG_NAND_MPC5121_NFC) += mpc5121_nfc.o\n COBJS-$(CONFIG_NAND_MXC) += mxc_nand.o\n COBJS-$(CONFIG_NAND_MXS) += mxs_nand.o\n--- /dev/null\n+++ b/drivers/mtd/nand/lantiq_nand.c\n@@ -0,0 +1,126 @@\n+/*\n+ * Copyright (C) 2012-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#include <common.h>\n+#include <linux/mtd/nand.h>\n+#include <linux/compiler.h>\n+#include <asm/arch/soc.h>\n+#include <asm/arch/nand.h>\n+#include <asm/lantiq/io.h>\n+\n+#define NAND_CON_ECC_ON\t\t(1 << 31)\n+#define NAND_CON_LATCH_PRE\t(1 << 23)\n+#define NAND_CON_LATCH_WP\t(1 << 22)\n+#define NAND_CON_LATCH_SE\t(1 << 21)\n+#define NAND_CON_LATCH_CS\t(1 << 20)\n+#define NAND_CON_LATCH_CLE\t(1 << 19)\n+#define NAND_CON_LATCH_ALE\t(1 << 18)\n+#define NAND_CON_OUT_CS1\t(1 << 10)\n+#define NAND_CON_IN_CS1\t\t(1 << 8)\n+#define NAND_CON_PRE_P\t\t(1 << 7)\n+#define NAND_CON_WP_P\t\t(1 << 6)\n+#define NAND_CON_SE_P\t\t(1 << 5)\n+#define NAND_CON_CS_P\t\t(1 << 4)\n+#define NAND_CON_CLE_P\t\t(1 << 3)\n+#define NAND_CON_ALE_P\t\t(1 << 2)\n+#define NAND_CON_CSMUX\t\t(1 << 1)\n+#define NAND_CON_NANDM\t\t(1 << 0)\n+\n+#define NAND_WAIT_WR_C\t\t(1 << 3)\n+#define NAND_WAIT_RDBY\t\t(1 << 0)\n+\n+#define NAND_CMD_ALE\t\t(1 << 2)\n+#define NAND_CMD_CLE\t\t(1 << 3)\n+#define NAND_CMD_CS\t\t(1 << 4)\n+#define NAND_CMD_SE\t\t(1 << 5)\n+#define NAND_CMD_WP\t\t(1 << 6)\n+#define NAND_CMD_PRE\t\t(1 << 7)\n+\n+struct ltq_nand_regs {\n+\t__be32\tcon;\t\t/* NAND controller control */\n+\t__be32\twait;\t\t/* NAND Flash Device RD/BY State */\n+\t__be32\tecc0;\t\t/* NAND Flash ECC Register 0 */\n+\t__be32\tecc_ac;\t\t/* NAND Flash ECC Register address counter */\n+\t__be32\tecc_cr;\t\t/* NAND Flash ECC Comparison */\n+};\n+\n+static struct ltq_nand_regs *ltq_nand_regs =\n+\t(struct ltq_nand_regs *) CKSEG1ADDR(LTQ_EBU_NAND_BASE);\n+\n+static void ltq_nand_wait_ready(void)\n+{\n+\twhile ((ltq_readl(&ltq_nand_regs->wait) & NAND_WAIT_WR_C) == 0)\n+\t\t;\n+}\n+\n+static int ltq_nand_dev_ready(struct mtd_info *mtd)\n+{\n+\tu32 data = ltq_readl(&ltq_nand_regs->wait);\n+\treturn data & NAND_WAIT_RDBY;\n+}\n+\n+static void ltq_nand_select_chip(struct mtd_info *mtd, int chip)\n+{\n+\tif (chip == 0) {\n+\t\tltq_setbits(&ltq_nand_regs->con, NAND_CON_NANDM);\n+\t\tltq_setbits(&ltq_nand_regs->con, NAND_CON_LATCH_CS);\n+\t} else {\n+\t\tltq_clrbits(&ltq_nand_regs->con, NAND_CON_LATCH_CS);\n+\t\tltq_clrbits(&ltq_nand_regs->con, NAND_CON_NANDM);\n+\t}\n+}\n+\n+static void ltq_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)\n+{\n+\tstruct nand_chip *chip = mtd->priv;\n+\tunsigned long addr = (unsigned long) chip->IO_ADDR_W;\n+\n+\tif (ctrl & NAND_CTRL_CHANGE) {\n+\t\tif (ctrl & NAND_ALE)\n+\t\t\taddr |= NAND_CMD_ALE;\n+\t\telse\n+\t\t\taddr &= ~NAND_CMD_ALE;\n+\n+\t\tif (ctrl & NAND_CLE)\n+\t\t\taddr |= NAND_CMD_CLE;\n+\t\telse\n+\t\t\taddr &= ~NAND_CMD_CLE;\n+\n+\t\tchip->IO_ADDR_W = (void __iomem *) addr;\n+\t}\n+\n+\tif (cmd != NAND_CMD_NONE) {\n+\t\twriteb(cmd, chip->IO_ADDR_W);\n+\t\tltq_nand_wait_ready();\n+\t}\n+}\n+\n+int ltq_nand_init(struct nand_chip *nand)\n+{\n+\t/* Enable NAND, set NAND CS to EBU CS1, enable EBU CS mux */\n+\tltq_writel(&ltq_nand_regs->con, NAND_CON_OUT_CS1 | NAND_CON_IN_CS1 |\n+\t\tNAND_CON_PRE_P | NAND_CON_WP_P | NAND_CON_SE_P |\n+\t\tNAND_CON_CS_P | NAND_CON_CSMUX);\n+\n+\tnand->dev_ready = ltq_nand_dev_ready;\n+\tnand->select_chip = ltq_nand_select_chip;\n+\tnand->cmd_ctrl = ltq_nand_cmd_ctrl;\n+\n+\tnand->chip_delay = 30;\n+\tnand->options = 0;\n+\tnand->ecc.mode = NAND_ECC_SOFT;\n+\n+\t/* Enable CS bit in address offset */\n+\tnand->IO_ADDR_R = nand->IO_ADDR_R + NAND_CMD_CS;\n+\tnand->IO_ADDR_W = nand->IO_ADDR_W + NAND_CMD_CS;\n+\n+\treturn 0;\n+}\n+\n+__weak int board_nand_init(struct nand_chip *chip)\n+{\n+\treturn ltq_nand_init(chip);\n+}\n--- a/drivers/net/Makefile\n+++ b/drivers/net/Makefile\n@@ -37,6 +37,8 @@ COBJS-$(CONFIG_INCA_IP_SWITCH) += inca-i\n COBJS-$(CONFIG_DRIVER_KS8695ETH) += ks8695eth.o\n COBJS-$(CONFIG_KS8851_MLL) += ks8851_mll.o\n COBJS-$(CONFIG_LAN91C96) += lan91c96.o\n+COBJS-$(CONFIG_LANTIQ_DANUBE_ETOP) += lantiq_danube_etop.o\n+COBJS-$(CONFIG_LANTIQ_VRX200_SWITCH) += lantiq_vrx200_switch.o\n COBJS-$(CONFIG_MACB) += macb.o\n COBJS-$(CONFIG_MCFFEC) += mcffec.o mcfmii.o\n COBJS-$(CONFIG_MPC5xxx_FEC) += mpc5xxx_fec.o\n--- /dev/null\n+++ b/drivers/net/lantiq_danube_etop.c\n@@ -0,0 +1,410 @@\n+/*\n+ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#include <common.h>\n+#include <malloc.h>\n+#include <netdev.h>\n+#include <miiphy.h>\n+#include <switch.h>\n+#include <asm/lantiq/io.h>\n+#include <asm/lantiq/eth.h>\n+#include <asm/lantiq/pm.h>\n+#include <asm/lantiq/reset.h>\n+#include <asm/lantiq/dma.h>\n+#include <asm/arch/soc.h>\n+\n+#define LTQ_PPE_ETOP_MDIO_ACC_RA\t(1 << 31)\n+#define LTQ_PPE_ETOP_MDIO_CFG_UMM1\t(1 << 2)\n+#define LTQ_PPE_ETOP_MDIO_CFG_UMM0\t(1 << 1)\n+\n+#define LTQ_PPE_ETOP_CFG_TCKINV1\t(1 << 11)\n+#define LTQ_PPE_ETOP_CFG_TCKINV0\t(1 << 10)\n+#define LTQ_PPE_ETOP_CFG_FEN1\t\t(1 << 9)\n+#define LTQ_PPE_ETOP_CFG_FEN0\t\t(1 << 8)\n+#define LTQ_PPE_ETOP_CFG_SEN1\t\t(1 << 7)\n+#define LTQ_PPE_ETOP_CFG_SEN0\t\t(1 << 6)\n+#define LTQ_PPE_ETOP_CFG_TURBO1\t\t(1 << 5)\n+#define LTQ_PPE_ETOP_CFG_REMII1\t\t(1 << 4)\n+#define LTQ_PPE_ETOP_CFG_OFF1\t\t(1 << 3)\n+#define LTQ_PPE_ETOP_CFG_TURBO0\t\t(1 << 2)\n+#define LTQ_PPE_ETOP_CFG_REMII0\t\t(1 << 1)\n+#define LTQ_PPE_ETOP_CFG_OFF0\t\t(1 << 0)\n+\n+#define LTQ_PPE_ENET0_MAC_CFG_CGEN\t(1 << 11)\n+#define LTQ_PPE_ENET0_MAC_CFG_DUPLEX\t(1 << 2)\n+#define LTQ_PPE_ENET0_MAC_CFG_SPEED\t(1 << 1)\n+#define LTQ_PPE_ENET0_MAC_CFG_LINK\t(1 << 0)\n+\n+#define LTQ_PPE_ENETS0_CFG_FTUC\t\t(1 << 28)\n+\n+#define LTQ_ETH_RX_BUFFER_CNT\t\tPKTBUFSRX\n+#define LTQ_ETH_TX_BUFFER_CNT\t\t8\n+#define LTQ_ETH_RX_DATA_SIZE\t\tPKTSIZE_ALIGN\n+#define LTQ_ETH_IP_ALIGN\t\t2\n+\n+#define LTQ_MDIO_DRV_NAME\t\t\"ltq-mdio\"\n+#define LTQ_ETH_DRV_NAME\t\t\"ltq-eth\"\n+\n+struct ltq_ppe_etop_regs {\n+\tu32\tmdio_cfg;\t\t/* MDIO configuration */\n+\tu32\tmdio_acc;\t\t/* MDIO access */\n+\tu32\tcfg;\t\t\t/* ETOP configuration */\n+\tu32\tig_vlan_cos;\t\t/* IG VLAN priority CoS mapping */\n+\tu32\tig_dscp_cos3;\t\t/* IG DSCP CoS mapping 3 */\n+\tu32\tig_dscp_cos2;\t\t/* IG DSCP CoS mapping 2 */\n+\tu32\tig_dscp_cos1;\t\t/* IG DSCP CoS mapping 1 */\n+\tu32\tig_dscp_cos0;\t\t/* IG DSCP CoS mapping 0 */\n+\tu32\tig_plen_ctrl;\t\t/* IG frame length control */\n+\tu32\trsvd0[3];\n+\tu32\tvpid;\t\t\t/* VLAN protocol ID */\n+};\n+\n+struct ltq_ppe_enet_regs {\n+\tu32\tmac_cfg;\t\t/* MAC configuration */\n+\tu32\trsvd0[3];\n+\tu32\tig_cfg;\t\t\t/* Ingress configuration */\n+\tu32\tig_pgcnt;\t\t/* Ingress buffer used page count */\n+\tu32\trsvd1;\n+\tu32\tig_buf_ctrl;\t\t/* Ingress buffer backpressure ctrl */\n+\tu32\tcos_cfg;\t\t/* Classification configuration */\n+\tu32\tig_drop;\t\t/* Total ingress drop frames */\n+\tu32\tig_err;\t\t\t/* Total ingress error frames */\n+\tu32\tmac_da0;\t\t/* Ingress MAC address 0 */\n+\tu32\tmac_da1;\t\t/* Ingress MAC address 1 */\n+\tu32\trsvd2[22];\n+\tu32\tpgcnt;\t\t\t/* Page counter */\n+\tu32\trsvd3;\n+\tu32\thf_ctrl;\t\t/* Half duplex control */\n+\tu32\ttx_ctrl;\t\t/* Transmit control */\n+\tu32\trsvd4;\n+\tu32\tvlcos0;\t\t\t/* VLAN insertion config CoS 0 */\n+\tu32\tvlcos1;\t\t\t/* VLAN insertion config CoS 1 */\n+\tu32\tvlcos2;\t\t\t/* VLAN insertion config CoS 2 */\n+\tu32\tvlcos3;\t\t\t/* VLAN insertion config CoS 3 */\n+\tu32\teg_col;\t\t\t/* Total egress collision frames */\n+\tu32\teg_drop;\t\t/* Total egress drop frames */\n+};\n+\n+struct ltq_eth_priv {\n+\tstruct ltq_dma_device dma_dev;\n+\tstruct mii_dev *bus;\n+\tstruct eth_device *dev;\n+\tint rx_num;\n+\tint tx_num;\n+};\n+\n+struct ltq_mdio_access {\n+\tunion {\n+\t\tstruct {\n+\t\t\tunsigned ra:1;\n+\t\t\tunsigned rw:1;\n+\t\t\tunsigned rsvd:4;\n+\t\t\tunsigned phya:5;\n+\t\t\tunsigned rega:5;\n+\t\t\tunsigned phyd:16;\n+\t\t} reg;\n+\t\tu32 val;\n+\t};\n+};\n+\n+static struct ltq_ppe_etop_regs *ltq_ppe_etop_regs =\n+\t(struct ltq_ppe_etop_regs *) CKSEG1ADDR(LTQ_PPE_ETOP_BASE);\n+\n+static struct ltq_ppe_enet_regs *ltq_ppe_enet0_regs =\n+\t(struct ltq_ppe_enet_regs *) CKSEG1ADDR(LTQ_PPE_ENET0_BASE);\n+\n+static inline int ltq_mdio_poll(void)\n+{\n+\tstruct ltq_mdio_access acc;\n+\tunsigned cnt = 10000;\n+\n+\twhile (likely(cnt--)) {\n+\t\tacc.val = ltq_readl(&ltq_ppe_etop_regs->mdio_acc);\n+\t\tif (!acc.reg.ra)\n+\t\t\treturn 0;\n+\t}\n+\n+\treturn 1;\n+}\n+\n+static int ltq_mdio_read(struct mii_dev *bus, int addr, int dev_addr,\n+\t\t\t\tint regnum)\n+{\n+\tstruct ltq_mdio_access acc;\n+\tint ret;\n+\n+\tacc.val = 0;\n+\tacc.reg.ra = 1;\n+\tacc.reg.rw = 1;\n+\tacc.reg.phya = addr;\n+\tacc.reg.rega = regnum;\n+\n+\tret = ltq_mdio_poll();\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tltq_writel(&ltq_ppe_etop_regs->mdio_acc, acc.val);\n+\n+\tret = ltq_mdio_poll();\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tacc.val = ltq_readl(&ltq_ppe_etop_regs->mdio_acc);\n+\n+\treturn acc.reg.phyd;\n+}\n+\n+static int ltq_mdio_write(struct mii_dev *bus, int addr, int dev_addr,\n+\t\t\t\tint regnum, u16 val)\n+{\n+\tstruct ltq_mdio_access acc;\n+\tint ret;\n+\n+\tacc.val = 0;\n+\tacc.reg.ra = 1;\n+\tacc.reg.rw = 0;\n+\tacc.reg.phya = addr;\n+\tacc.reg.rega = regnum;\n+\tacc.reg.phyd = val;\n+\n+\tret = ltq_mdio_poll();\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tltq_writel(&ltq_ppe_etop_regs->mdio_acc, acc.val);\n+\n+\treturn 0;\n+}\n+\n+static inline void ltq_eth_write_hwaddr(const struct eth_device *dev)\n+{\n+\tu32 da0, da1;\n+\n+\tda0 = (dev->enetaddr[0] << 24) + (dev->enetaddr[1] << 16) +\n+\t\t(dev->enetaddr[2] << 8) + dev->enetaddr[3];\n+\tda1 = (dev->enetaddr[4] << 24) + (dev->enetaddr[5] << 16);\n+\n+\tltq_writel(&ltq_ppe_enet0_regs->mac_da0, da0);\n+\tltq_writel(&ltq_ppe_enet0_regs->mac_da1, da1);\n+}\n+\n+static inline u8 *ltq_eth_rx_packet_align(int rx_num)\n+{\n+\tu8 *packet = (u8 *) NetRxPackets[rx_num];\n+\n+\t/*\n+\t * IP header needs\n+\t */\n+\treturn packet + LTQ_ETH_IP_ALIGN;\n+}\n+\n+static int ltq_eth_init(struct eth_device *dev, bd_t *bis)\n+{\n+\tstruct ltq_eth_priv *priv = dev->priv;\n+\tstruct ltq_dma_device *dma_dev = &priv->dma_dev;\n+\tint i;\n+\n+\tltq_eth_write_hwaddr(dev);\n+\n+\tfor (i = 0; i < LTQ_ETH_RX_BUFFER_CNT; i++)\n+\t\tltq_dma_rx_map(dma_dev, i, ltq_eth_rx_packet_align(i),\n+\t\t\tLTQ_ETH_RX_DATA_SIZE);\n+\n+\tltq_dma_enable(dma_dev);\n+\n+\tpriv->rx_num = 0;\n+\tpriv->tx_num = 0;\n+\n+\treturn 0;\n+}\n+\n+static void ltq_eth_halt(struct eth_device *dev)\n+{\n+\tstruct ltq_eth_priv *priv = dev->priv;\n+\tstruct ltq_dma_device *dma_dev = &priv->dma_dev;\n+\n+\tltq_dma_reset(dma_dev);\n+}\n+\n+static int ltq_eth_send(struct eth_device *dev, void *packet, int length)\n+{\n+\tstruct ltq_eth_priv *priv = dev->priv;\n+\tstruct ltq_dma_device *dma_dev = &priv->dma_dev;\n+\tint err;\n+\n+\t/* Minimum payload length w/ CRC is 60 bytes */\n+\tif (length < 60)\n+\t\tlength = 60;\n+\n+\terr = ltq_dma_tx_map(dma_dev, priv->tx_num, packet, length, 10);\n+\tif (err) {\n+\t\tputs(\"NET: timeout on waiting for TX descriptor\\n\");\n+\t\treturn -1;\n+\t}\n+\n+\tpriv->tx_num = (priv->tx_num + 1) % LTQ_ETH_TX_BUFFER_CNT;\n+\n+\treturn err;\n+}\n+\n+static int ltq_eth_recv(struct eth_device *dev)\n+{\n+\tstruct ltq_eth_priv *priv = dev->priv;\n+\tstruct ltq_dma_device *dma_dev = &priv->dma_dev;\n+\tu8 *packet;\n+\tint len;\n+\n+\tif (!ltq_dma_rx_poll(dma_dev, priv->rx_num))\n+\t\treturn 0;\n+\n+#if 0\n+\tprintf(\"%s: rx_num %d\\n\", __func__, priv->rx_num);\n+#endif\n+\n+\tlen = ltq_dma_rx_length(dma_dev, priv->rx_num);\n+\tpacket = ltq_eth_rx_packet_align(priv->rx_num);\n+\n+#if 0\n+\tprintf(\"%s: received: packet %p, len %u, rx_num %d\\n\",\n+\t\t__func__, packet, len, priv->rx_num);\n+#endif\n+\n+\tif (len)\n+\t\tNetReceive(packet, len);\n+\n+\tltq_dma_rx_map(dma_dev, priv->rx_num, packet,\n+\t\tLTQ_ETH_RX_DATA_SIZE);\n+\n+\tpriv->rx_num = (priv->rx_num + 1) % LTQ_ETH_RX_BUFFER_CNT;\n+\n+\treturn 0;\n+}\n+\n+static void ltq_eth_hw_init(const struct ltq_eth_port_config *port)\n+{\n+\tu32 data;\n+\n+\t/* Power up ethernet subsystems */\n+\tltq_pm_enable(LTQ_PM_ETH);\n+\n+\t/* Reset ethernet subsystems */\n+\tltq_reset_once(LTQ_RESET_ETH, 1);\n+\n+\t/* Disable MDIO auto-detection */\n+\tltq_clrbits(&ltq_ppe_etop_regs->mdio_cfg, LTQ_PPE_ETOP_MDIO_CFG_UMM1 |\n+\t\t\tLTQ_PPE_ETOP_MDIO_CFG_UMM0);\n+\n+\t/* Enable CRC generation, Full Duplex, 100Mbps, Link up */\n+\tltq_writel(&ltq_ppe_enet0_regs->mac_cfg, LTQ_PPE_ENET0_MAC_CFG_CGEN |\n+\t\t\tLTQ_PPE_ENET0_MAC_CFG_DUPLEX |\n+\t\t\tLTQ_PPE_ENET0_MAC_CFG_SPEED |\n+\t\t\tLTQ_PPE_ENET0_MAC_CFG_LINK);\n+\n+\t/* Reset ETOP cfg and disable all */\n+\tdata = LTQ_PPE_ETOP_CFG_OFF0 | LTQ_PPE_ETOP_CFG_OFF1;\n+\n+\t/* Enable ENET0, enable store and fetch */\n+\tdata &= ~LTQ_PPE_ETOP_CFG_OFF0;\n+\tdata |= LTQ_PPE_ETOP_CFG_SEN0 | LTQ_PPE_ETOP_CFG_FEN0;\n+\n+\tif (port->phy_if == PHY_INTERFACE_MODE_RMII)\n+\t\tdata |= LTQ_PPE_ETOP_CFG_REMII0;\n+\telse\n+\t\tdata &= ~LTQ_PPE_ETOP_CFG_REMII0;\n+\n+\tltq_writel(&ltq_ppe_etop_regs->cfg, data);\n+\n+\t/* Set allowed packet length from 64 bytes to 1518 bytes */\n+\tltq_writel(&ltq_ppe_etop_regs->ig_plen_ctrl, (64 << 16) | 1518);\n+\n+\t/* Enable filter for unicast packets */\n+\tltq_setbits(&ltq_ppe_enet0_regs->ig_cfg, LTQ_PPE_ENETS0_CFG_FTUC);\n+}\n+\n+int ltq_eth_initialize(const struct ltq_eth_board_config *board_config)\n+{\n+\tstruct eth_device *dev;\n+\tstruct mii_dev *bus;\n+\tstruct ltq_eth_priv *priv;\n+\tstruct ltq_dma_device *dma_dev;\n+\tconst struct ltq_eth_port_config *port = &board_config->ports[0];\n+\tstruct phy_device *phy;\n+\tstruct switch_device *sw;\n+\tint ret;\n+\n+\tltq_dma_init();\n+\tltq_eth_hw_init(port);\n+\n+\tdev = calloc(1, sizeof(*dev));\n+\tif (!dev)\n+\t\treturn -1;\n+\n+\tpriv = calloc(1, sizeof(*priv));\n+\tif (!priv)\n+\t\treturn -1;\n+\n+\tbus = mdio_alloc();\n+\tif (!bus)\n+\t\treturn -1;\n+\n+\tsprintf(dev->name, LTQ_ETH_DRV_NAME);\n+\tdev->priv = priv;\n+\tdev->init = ltq_eth_init;\n+\tdev->halt = ltq_eth_halt;\n+\tdev->recv = ltq_eth_recv;\n+\tdev->send = ltq_eth_send;\n+\n+\tsprintf(bus->name, LTQ_MDIO_DRV_NAME);\n+\tbus->read = ltq_mdio_read;\n+\tbus->write = ltq_mdio_write;\n+\tbus->priv = priv;\n+\n+\tdma_dev = &priv->dma_dev;\n+\tdma_dev->port = 0;\n+\tdma_dev->rx_chan.chan_no = 6;\n+\tdma_dev->rx_chan.class = 3;\n+\tdma_dev->rx_chan.num_desc = LTQ_ETH_RX_BUFFER_CNT;\n+\tdma_dev->rx_endian_swap = LTQ_DMA_ENDIANESS_B3_B2_B1_B0;\n+\tdma_dev->rx_burst_len = LTQ_DMA_BURST_2WORDS;\n+\tdma_dev->tx_chan.chan_no = 7;\n+\tdma_dev->tx_chan.class = 3;\n+\tdma_dev->tx_chan.num_desc = LTQ_ETH_TX_BUFFER_CNT;\n+\tdma_dev->tx_endian_swap = LTQ_DMA_ENDIANESS_B3_B2_B1_B0;\n+\tdma_dev->tx_burst_len = LTQ_DMA_BURST_2WORDS;\n+\n+\tpriv->bus = bus;\n+\tpriv->dev = dev;\n+\n+\tret = ltq_dma_register(dma_dev);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = mdio_register(bus);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = eth_register(dev);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tif (port->flags & LTQ_ETH_PORT_SWITCH) {\n+\t\tsw = switch_connect(bus);\n+\t\tif (!sw)\n+\t\t\treturn -1;\n+\n+\t\tswitch_setup(sw);\n+\t}\n+\n+\tif (port->flags & LTQ_ETH_PORT_PHY) {\n+\t\tphy = phy_connect(bus, port->phy_addr, dev, port->phy_if);\n+\t\tif (!phy)\n+\t\t\treturn -1;\n+\n+\t\tphy_config(phy);\n+\t}\n+\n+\treturn 0;\n+}\n--- /dev/null\n+++ b/drivers/net/lantiq_vrx200_switch.c\n@@ -0,0 +1,675 @@\n+/*\n+ * Copyright (C) 2010-2011 Lantiq Deutschland GmbH\n+ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#define DEBUG\n+\n+#include <common.h>\n+#include <malloc.h>\n+#include <netdev.h>\n+#include <miiphy.h>\n+#include <linux/compiler.h>\n+#include <asm/gpio.h>\n+#include <asm/processor.h>\n+#include <asm/lantiq/io.h>\n+#include <asm/lantiq/eth.h>\n+#include <asm/lantiq/pm.h>\n+#include <asm/lantiq/reset.h>\n+#include <asm/lantiq/dma.h>\n+#include <asm/arch/soc.h>\n+#include <asm/arch/switch.h>\n+\n+#define LTQ_ETH_RX_BUFFER_CNT\t\tPKTBUFSRX\n+#define LTQ_ETH_TX_BUFFER_CNT\t\t8\n+#define LTQ_ETH_RX_DATA_SIZE\t\tPKTSIZE_ALIGN\n+#define LTQ_ETH_IP_ALIGN\t\t2\n+\n+#define LTQ_MDIO_DRV_NAME\t\t\"ltq-mdio\"\n+#define LTQ_ETH_DRV_NAME\t\t\"ltq-eth\"\n+\n+#define LTQ_ETHSW_MAX_GMAC\t\t6\n+#define LTQ_ETHSW_PMAC\t\t\t6\n+\n+struct ltq_mdio_phy_addr_reg {\n+\tunion {\n+\t\tstruct {\n+\t\t\tunsigned rsvd:1;\n+\t\t\tunsigned lnkst:2;\t/* Link status control */\n+\t\t\tunsigned speed:2;\t/* Speed control */\n+\t\t\tunsigned fdup:2;\t/* Full duplex control */\n+\t\t\tunsigned fcontx:2;\t/* Flow control mode TX */\n+\t\t\tunsigned fconrx:2;\t/* Flow control mode RX */\n+\t\t\tunsigned addr:5;\t/* PHY address */\n+\t\t} bits;\n+\t\tu16 val;\n+\t};\n+};\n+\n+enum ltq_mdio_phy_addr_lnkst {\n+\tLTQ_MDIO_PHY_ADDR_LNKST_AUTO = 0,\n+\tLTQ_MDIO_PHY_ADDR_LNKST_UP = 1,\n+\tLTQ_MDIO_PHY_ADDR_LNKST_DOWN = 2,\n+};\n+\n+enum ltq_mdio_phy_addr_speed {\n+\tLTQ_MDIO_PHY_ADDR_SPEED_M10 = 0,\n+\tLTQ_MDIO_PHY_ADDR_SPEED_M100 = 1,\n+\tLTQ_MDIO_PHY_ADDR_SPEED_G1 = 2,\n+\tLTQ_MDIO_PHY_ADDR_SPEED_AUTO = 3,\n+};\n+\n+enum ltq_mdio_phy_addr_fdup {\n+\tLTQ_MDIO_PHY_ADDR_FDUP_AUTO = 0,\n+\tLTQ_MDIO_PHY_ADDR_FDUP_ENABLE = 1,\n+\tLTQ_MDIO_PHY_ADDR_FDUP_DISABLE = 3,\n+};\n+\n+enum ltq_mdio_phy_addr_fcon {\n+\tLTQ_MDIO_PHY_ADDR_FCON_AUTO = 0,\n+\tLTQ_MDIO_PHY_ADDR_FCON_ENABLE = 1,\n+\tLTQ_MDIO_PHY_ADDR_FCON_DISABLE = 3,\n+};\n+\n+struct ltq_mii_mii_cfg_reg {\n+\tunion {\n+\t\tstruct {\n+\t\t\tunsigned res:1;\t\t/* Hardware reset */\n+\t\t\tunsigned en:1;\t\t/* xMII interface enable */\n+\t\t\tunsigned isol:1;\t/* xMII interface isolate */\n+\t\t\tunsigned ldclkdis:1;\t/* Link down clock disable */\n+\t\t\tunsigned rsvd:1;\n+\t\t\tunsigned crs:2;\t\t/* CRS sensitivity config */\n+\t\t\tunsigned rgmii_ibs:1;\t/* RGMII In Band status */\n+\t\t\tunsigned rmii:1;\t/* RMII ref clock direction */\n+\t\t\tunsigned miirate:3;\t/* xMII interface clock rate */\n+\t\t\tunsigned miimode:4;\t/* xMII interface mode */\n+\t\t} bits;\n+\t\tu16 val;\n+\t};\n+};\n+\n+enum ltq_mii_mii_cfg_miirate {\n+\tLTQ_MII_MII_CFG_MIIRATE_M2P5 = 0,\n+\tLTQ_MII_MII_CFG_MIIRATE_M25 = 1,\n+\tLTQ_MII_MII_CFG_MIIRATE_M125 = 2,\n+\tLTQ_MII_MII_CFG_MIIRATE_M50 = 3,\n+\tLTQ_MII_MII_CFG_MIIRATE_AUTO = 4,\n+};\n+\n+enum ltq_mii_mii_cfg_miimode {\n+\tLTQ_MII_MII_CFG_MIIMODE_MIIP = 0,\n+\tLTQ_MII_MII_CFG_MIIMODE_MIIM = 1,\n+\tLTQ_MII_MII_CFG_MIIMODE_RMIIP = 2,\n+\tLTQ_MII_MII_CFG_MIIMODE_RMIIM = 3,\n+\tLTQ_MII_MII_CFG_MIIMODE_RGMII = 4,\n+};\n+\n+struct ltq_eth_priv {\n+\tstruct ltq_dma_device dma_dev;\n+\tstruct mii_dev *bus;\n+\tstruct eth_device *dev;\n+\tstruct phy_device *phymap[LTQ_ETHSW_MAX_GMAC];\n+\tint rx_num;\n+\tint tx_num;\n+};\n+\n+static struct vr9_switch_regs *switch_regs =\n+\t(struct vr9_switch_regs *) CKSEG1ADDR(LTQ_SWITCH_BASE);\n+\n+static inline void vr9_switch_sync(void)\n+{\n+\t__asm__(\"sync\");\n+}\n+\n+static inline int vr9_switch_mdio_is_busy(void)\n+{\n+\tu32 mdio_ctrl = ltq_readl(&switch_regs->mdio.mdio_ctrl);\n+\n+\treturn mdio_ctrl & MDIO_CTRL_MBUSY;\n+}\n+\n+static inline void vr9_switch_mdio_poll(void)\n+{\n+\twhile (vr9_switch_mdio_is_busy())\n+\t\tcpu_relax();\n+}\n+\n+static int vr9_switch_mdio_read(struct mii_dev *bus, int phyad, int devad,\n+\t\t\t\t\tint regad)\n+{\n+\tu32 mdio_ctrl;\n+\tint retval;\n+\n+\tmdio_ctrl = MDIO_CTRL_OP_READ |\n+\t\t((phyad << MDIO_CTRL_PHYAD_SHIFT) & MDIO_CTRL_PHYAD_MASK) |\n+\t\t(regad & MDIO_CTRL_REGAD_MASK);\n+\n+\tvr9_switch_mdio_poll();\n+\tltq_writel(&switch_regs->mdio.mdio_ctrl, mdio_ctrl);\n+\tvr9_switch_mdio_poll();\n+\tretval = ltq_readl(&switch_regs->mdio.mdio_read);\n+\n+\treturn retval;\n+}\n+\n+static int vr9_switch_mdio_write(struct mii_dev *bus, int phyad, int devad,\n+\t\t\t\t\tint regad, u16 val)\n+{\n+\tu32 mdio_ctrl;\n+\n+\tmdio_ctrl = MDIO_CTRL_OP_WRITE |\n+\t\t((phyad << MDIO_CTRL_PHYAD_SHIFT) & MDIO_CTRL_PHYAD_MASK) |\n+\t\t(regad & MDIO_CTRL_REGAD_MASK);\n+\n+\tvr9_switch_mdio_poll();\n+\tltq_writel(&switch_regs->mdio.mdio_write, val);\n+\tltq_writel(&switch_regs->mdio.mdio_ctrl, mdio_ctrl);\n+\n+\treturn 0;\n+}\n+\n+static void ltq_eth_gmac_update(struct phy_device *phydev, int num)\n+{\n+\tstruct ltq_mdio_phy_addr_reg phy_addr_reg;\n+\tstruct ltq_mii_mii_cfg_reg mii_cfg_reg;\n+\n+\tphy_addr_reg.val = ltq_readl(to_mdio_phyaddr(switch_regs, num));\n+\n+\tswitch (num) {\n+\tcase 0:\n+\tcase 1:\n+\tcase 5:\n+\t\tmii_cfg_reg.val = ltq_readl(to_mii_miicfg(switch_regs, num));\n+\t\tbreak;\n+\tdefault:\n+\t\tmii_cfg_reg.val = 0;\n+\t\tbreak;\n+\t}\n+\n+\tphy_addr_reg.bits.addr = phydev->addr;\n+\n+\tif (phydev->link)\n+\t\tphy_addr_reg.bits.lnkst = LTQ_MDIO_PHY_ADDR_LNKST_UP;\n+\telse\n+\t\tphy_addr_reg.bits.lnkst = LTQ_MDIO_PHY_ADDR_LNKST_DOWN;\n+\n+\tswitch (phydev->speed) {\n+\tcase SPEED_1000:\n+\t\tphy_addr_reg.bits.speed = LTQ_MDIO_PHY_ADDR_SPEED_G1;\n+\t\tmii_cfg_reg.bits.miirate = LTQ_MII_MII_CFG_MIIRATE_M125;\n+\t\tbreak;\n+\tcase SPEED_100:\n+\t\tphy_addr_reg.bits.speed = LTQ_MDIO_PHY_ADDR_SPEED_M100;\n+\t\tswitch (mii_cfg_reg.bits.miimode) {\n+\t\tcase LTQ_MII_MII_CFG_MIIMODE_RMIIM:\n+\t\tcase LTQ_MII_MII_CFG_MIIMODE_RMIIP:\n+\t\t\tmii_cfg_reg.bits.miirate = LTQ_MII_MII_CFG_MIIRATE_M50;\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tmii_cfg_reg.bits.miirate = LTQ_MII_MII_CFG_MIIRATE_M25;\n+\t\t\tbreak;\n+\t\t}\n+\t\tbreak;\n+\tdefault:\n+\t\tphy_addr_reg.bits.speed = LTQ_MDIO_PHY_ADDR_SPEED_M10;\n+\t\tmii_cfg_reg.bits.miirate = LTQ_MII_MII_CFG_MIIRATE_M2P5;\n+\t\tbreak;\n+\t}\n+\n+\tif (phydev->duplex == DUPLEX_FULL)\n+\t\tphy_addr_reg.bits.fdup = LTQ_MDIO_PHY_ADDR_FDUP_ENABLE;\n+\telse\n+\t\tphy_addr_reg.bits.fdup = LTQ_MDIO_PHY_ADDR_FDUP_DISABLE;\n+\n+\tltq_writel(to_mdio_phyaddr(switch_regs, num), phy_addr_reg.val);\n+\n+\tswitch (num) {\n+\tcase 0:\n+\tcase 1:\n+\tcase 5:\n+\t\tltq_writel(to_mii_miicfg(switch_regs, num), mii_cfg_reg.val);\n+\t\tbreak;\n+\tdefault:\n+\t\tbreak;\n+\t}\n+}\n+\n+static inline u8 *ltq_eth_rx_packet_align(int rx_num)\n+{\n+\tu8 *packet = (u8 *) NetRxPackets[rx_num];\n+\n+\t/*\n+\t * IP header needs\n+\t */\n+\treturn packet + LTQ_ETH_IP_ALIGN;\n+}\n+\n+static int ltq_eth_init(struct eth_device *dev, bd_t *bis)\n+{\n+\tstruct ltq_eth_priv *priv = dev->priv;\n+\tstruct ltq_dma_device *dma_dev = &priv->dma_dev;\n+\tstruct phy_device *phydev;\n+\tint i;\n+\n+\tfor (i = 0; i < LTQ_ETHSW_MAX_GMAC; i++) {\n+\t\tphydev = priv->phymap[i];\n+\t\tif (!phydev)\n+\t\t\tcontinue;\n+\n+\t\tphy_startup(phydev);\n+\t\tltq_eth_gmac_update(phydev, i);\n+\t}\n+\n+\tfor (i = 0; i < LTQ_ETH_RX_BUFFER_CNT; i++)\n+\t\tltq_dma_rx_map(dma_dev, i, ltq_eth_rx_packet_align(i),\n+\t\t\tLTQ_ETH_RX_DATA_SIZE);\n+\n+\tltq_dma_enable(dma_dev);\n+\n+\tpriv->rx_num = 0;\n+\tpriv->tx_num = 0;\n+\n+\treturn 0;\n+}\n+\n+static void ltq_eth_halt(struct eth_device *dev)\n+{\n+\tstruct ltq_eth_priv *priv = dev->priv;\n+\tstruct ltq_dma_device *dma_dev = &priv->dma_dev;\n+\tstruct phy_device *phydev;\n+\tint i;\n+\n+\tltq_dma_reset(dma_dev);\n+\n+\tfor (i = 0; i < LTQ_ETHSW_MAX_GMAC; i++) {\n+\t\tphydev = priv->phymap[i];\n+\t\tif (!phydev)\n+\t\t\tcontinue;\n+\n+\t\tphy_shutdown(phydev);\n+\t\tphydev->link = 0;\n+\t\tltq_eth_gmac_update(phydev, i);\n+\t}\n+}\n+\n+static int ltq_eth_send(struct eth_device *dev, void *packet, int length)\n+{\n+\tstruct ltq_eth_priv *priv = dev->priv;\n+\tstruct ltq_dma_device *dma_dev = &priv->dma_dev;\n+\n+#if 0\n+\tprintf(\"%s: packet %p, len %d\\n\", __func__, packet, length);\n+#endif\n+\n+\tltq_dma_tx_map(dma_dev, priv->tx_num, packet, length, 10);\n+\tpriv->tx_num = (priv->tx_num + 1) % LTQ_ETH_TX_BUFFER_CNT;\n+\n+\treturn 0;\n+}\n+\n+static int ltq_eth_recv(struct eth_device *dev)\n+{\n+\tstruct ltq_eth_priv *priv = dev->priv;\n+\tstruct ltq_dma_device *dma_dev = &priv->dma_dev;\n+\tu8 *packet;\n+\tint len;\n+\n+\tif (!ltq_dma_rx_poll(dma_dev, priv->rx_num))\n+\t\treturn 0;\n+\n+#if 0\n+\tprintf(\"%s: rx_num %d\\n\", __func__, priv->rx_num);\n+#endif\n+\n+\tlen = ltq_dma_rx_length(dma_dev, priv->rx_num);\n+\tpacket = ltq_eth_rx_packet_align(priv->rx_num);\n+\n+#if 0\n+\tprintf(\"%s: received: packet %p, len %u, rx_num %d\\n\",\n+\t\t__func__, packet, len, priv->rx_num);\n+#endif\n+\n+\tif (len)\n+\t\tNetReceive(packet, len);\n+\n+\tltq_dma_rx_map(dma_dev, priv->rx_num, packet,\n+\t\tLTQ_ETH_RX_DATA_SIZE);\n+\n+\tpriv->rx_num = (priv->rx_num + 1) % LTQ_ETH_RX_BUFFER_CNT;\n+\n+\treturn 0;\n+}\n+\n+static void ltq_eth_gmac_init(int num)\n+{\n+\tstruct ltq_mdio_phy_addr_reg phy_addr_reg;\n+\tstruct ltq_mii_mii_cfg_reg mii_cfg_reg;\n+\n+\t/* Reset PHY status to link down */\n+\tphy_addr_reg.val = ltq_readl(to_mdio_phyaddr(switch_regs, num));\n+\tphy_addr_reg.bits.addr = num;\n+\tphy_addr_reg.bits.lnkst = LTQ_MDIO_PHY_ADDR_LNKST_DOWN;\n+\tphy_addr_reg.bits.speed = LTQ_MDIO_PHY_ADDR_SPEED_M10;\n+\tphy_addr_reg.bits.fdup = LTQ_MDIO_PHY_ADDR_FDUP_DISABLE;\n+\tltq_writel(to_mdio_phyaddr(switch_regs, num), phy_addr_reg.val);\n+\n+\t/* Reset and disable MII interface */\n+\tswitch (num) {\n+\tcase 0:\n+\tcase 1:\n+\tcase 5:\n+\t\tmii_cfg_reg.val = ltq_readl(to_mii_miicfg(switch_regs, num));\n+\t\tmii_cfg_reg.bits.en = 0;\n+\t\tmii_cfg_reg.bits.res = 1;\n+\t\tmii_cfg_reg.bits.miirate = LTQ_MII_MII_CFG_MIIRATE_M2P5;\n+\t\tltq_writel(to_mii_miicfg(switch_regs, num), mii_cfg_reg.val);\n+\t\tbreak;\n+\tdefault:\n+\t\tbreak;\n+\t}\n+\n+\t/*\n+\t * - enable frame checksum generation\n+\t * - enable padding of short frames\n+\t * - disable flow control\n+\t */\n+\tltq_writel(to_mac_ctrl(switch_regs, num, 0),\n+\t\tMAC_CTRL0_PADEN | MAC_CTRL0_FCS | MAC_CTRL0_FCON_NONE);\n+\n+\tvr9_switch_sync();\n+}\n+\n+static void ltq_eth_pmac_init(void)\n+{\n+\t/*\n+\t * WAR: buffer congestion:\n+\t * - shorten preambel to 1 byte\n+\t * - set TX IPG to 7 bytes\n+\t */\n+#if 1\n+\tltq_writel(to_mac_ctrl(switch_regs, LTQ_ETHSW_PMAC, 1),\n+\t\tMAC_CTRL1_SHORTPRE | 7);\n+#endif\n+\n+\t/*\n+\t * WAR: systematical concept weakness ACM bug\n+\t * - set maximum number of used buffer segments to 254\n+\t * - soft-reset BM FSQM\n+\t */\n+#if 1\n+\tltq_writel(&switch_regs->bm.core.fsqm_gctrl, 253);\n+\tltq_setbits(&switch_regs->bm.core.gctrl, BM_GCTRL_F_SRES);\n+\tltq_clrbits(&switch_regs->bm.core.gctrl, BM_GCTRL_F_SRES);\n+#endif\n+\n+\t/*\n+\t * WAR: switch MAC drop bug\n+\t */\n+#if 1\n+\tltq_writel(to_pce_tbl_key(switch_regs, 0), 0xf);\n+\tltq_writel(to_pce_tbl_value(switch_regs, 0), 0x40);\n+\tltq_writel(&switch_regs->pce.core.tbl_addr, 0x3);\n+\tltq_writel(&switch_regs->pce.core.tbl_ctrl, 0x902f);\n+#endif\n+\n+\t/*\n+\t * Configure frame header control:\n+\t * - enable flow control\n+\t * - enable CRC check for packets from DMA to PMAC\n+\t * - remove special tag from packets from PMAC to DMA\n+\t * - add CRC for packets from DMA to PMAC\n+\t */\n+\tltq_writel(&switch_regs->pmac.hd_ctl, /*PMAC_HD_CTL_FC |*/\n+\t\tPMAC_HD_CTL_CCRC | PMAC_HD_CTL_RST | PMAC_HD_CTL_AC |\n+\t\tPMAC_HD_CTL_RC);\n+\n+#if 1\n+\tltq_writel(&switch_regs->pmac.rx_ipg, 0x8b);\n+#endif\n+\n+\t/*\n+\t * - enable frame checksum generation\n+\t * - enable padding of short frames\n+\t * - disable flow control\n+\t */\n+\tltq_writel(to_mac_ctrl(switch_regs, LTQ_ETHSW_PMAC, 0),\n+\t\tMAC_CTRL0_PADEN | MAC_CTRL0_FCS | MAC_CTRL0_FCON_NONE);\n+\n+\tvr9_switch_sync();\n+}\n+\n+static void ltq_eth_hw_init(void)\n+{\n+\tint i;\n+\n+\t/* Power up ethernet and switch subsystems */\n+\tltq_pm_enable(LTQ_PM_ETH);\n+\n+\t/* Reset ethernet and switch subsystems */\n+#if 0\n+\tltq_reset_once(LTQ_RESET_ETH, 10);\n+#endif\n+\n+\t/* Enable switch macro */\n+\tltq_setbits(&switch_regs->mdio.glob_ctrl, MDIO_GLOB_CTRL_SE);\n+\n+\t/* Disable MDIO auto-polling for all ports */\n+\tltq_writel(&switch_regs->mdio.mdc_cfg_0, 0);\n+\n+\t/*\n+\t * Enable and set MDIO management clock to 2.5 MHz. This is the\n+\t * maximum clock for FE PHYs.\n+\t * Formula for clock is:\n+\t *\n+\t *      50 MHz\n+\t * x = ----------- - 1\n+\t *      2 * f_MDC\n+\t */\n+\tltq_writel(&switch_regs->mdio.mdc_cfg_1, MDIO_MDC_CFG1_RES |\n+\t\tMDIO_MDC_CFG1_MCEN | 5);\n+\n+\tvr9_switch_sync();\n+\n+\t/* Init MAC connected to CPU  */\n+\tltq_eth_pmac_init();\n+\n+\t/* Init MACs connected to external MII interfaces */\n+\tfor (i = 0; i < LTQ_ETHSW_MAX_GMAC; i++)\n+\t\tltq_eth_gmac_init(i);\n+}\n+\n+static void ltq_eth_port_config(struct ltq_eth_priv *priv,\n+\t\t\t\t\tconst struct ltq_eth_port_config *port)\n+{\n+\tstruct ltq_mii_mii_cfg_reg mii_cfg_reg;\n+\tstruct phy_device *phydev;\n+\tint setup_gpio = 0;\n+\n+\tswitch (port->num) {\n+\tcase 0:\t/* xMII0 */\n+\tcase 1:\t/* xMII1 */\n+\t\tmii_cfg_reg.val = ltq_readl(to_mii_miicfg(switch_regs,\n+\t\t\t\t\tport->num));\n+\t\tmii_cfg_reg.bits.en = port->flags ? 1 : 0;\n+\n+\t\tswitch (port->phy_if) {\n+\t\tcase PHY_INTERFACE_MODE_MII:\n+\t\t\tif (port->flags & LTQ_ETH_PORT_PHY)\n+\t\t\t\t/* MII MAC mode, connected to external PHY */\n+\t\t\t\tmii_cfg_reg.bits.miimode =\n+\t\t\t\t\tLTQ_MII_MII_CFG_MIIMODE_MIIM;\n+\t\t\telse\n+\t\t\t\t/* MII PHY mode, connected to external MAC */\n+\t\t\t\tmii_cfg_reg.bits.miimode =\n+\t\t\t\t\tLTQ_MII_MII_CFG_MIIMODE_MIIP;\n+\t\t\tsetup_gpio = 1;\n+\t\t\tbreak;\n+\t\tcase PHY_INTERFACE_MODE_RMII:\n+\t\t\tif (port->flags & LTQ_ETH_PORT_PHY)\n+\t\t\t\t/* RMII MAC mode, connected to external PHY */\n+\t\t\t\tmii_cfg_reg.bits.miimode =\n+\t\t\t\t\tLTQ_MII_MII_CFG_MIIMODE_RMIIM;\n+\t\t\telse\n+\t\t\t\t/* RMII PHY mode, connected to external MAC */\n+\t\t\t\tmii_cfg_reg.bits.miimode =\n+\t\t\t\t\tLTQ_MII_MII_CFG_MIIMODE_RMIIP;\n+\t\t\tsetup_gpio = 1;\n+\t\t\tbreak;\n+\t\tcase PHY_INTERFACE_MODE_RGMII:\n+\t\t\t/* RGMII MAC mode, connected to external PHY */\n+\t\t\tmii_cfg_reg.bits.miimode =\n+\t\t\t\tLTQ_MII_MII_CFG_MIIMODE_RGMII;\n+\t\t\tsetup_gpio = 1;\n+\n+\t\t\t/* RGMII clock delays */\n+\t\t\tltq_writel(to_mii_pcdu(switch_regs, port->num),\n+\t\t\t\tport->rgmii_rx_delay << PCDU_RXDLY_SHIFT |\n+\t\t\t\tport->rgmii_tx_delay);\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\tltq_writel(to_mii_miicfg(switch_regs, port->num),\n+\t\t\tmii_cfg_reg.val);\n+\t\tbreak;\n+\tcase 2:\t/* internal GPHY0 */\n+\tcase 3:\t/* internal GPHY0 */\n+\tcase 4:\t/* internal GPHY1 */\n+\t\tswitch (port->phy_if) {\n+\t\tcase PHY_INTERFACE_MODE_MII:\n+\t\tcase PHY_INTERFACE_MODE_GMII:\n+\t\t\tsetup_gpio = 1;\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tbreak;\n+\t\t}\n+\t\tbreak;\n+\tcase 5:\t/* internal GPHY1 or xMII2 */\n+\t\tmii_cfg_reg.val = ltq_readl(to_mii_miicfg(switch_regs,\n+\t\t\t\t\tport->num));\n+\t\tmii_cfg_reg.bits.en = port->flags ? 1 : 0;\n+\n+\t\tswitch (port->phy_if) {\n+\t\tcase PHY_INTERFACE_MODE_MII:\n+\t\t\t/* MII MAC mode, connected to internal GPHY */\n+\t\t\tmii_cfg_reg.bits.miimode =\n+\t\t\t\tLTQ_MII_MII_CFG_MIIMODE_MIIM;\n+\t\t\tsetup_gpio = 1;\n+\t\t\tbreak;\n+\t\tcase PHY_INTERFACE_MODE_RGMII:\n+\t\t\t/* RGMII MAC mode, connected to external PHY */\n+\t\t\tmii_cfg_reg.bits.miimode =\n+\t\t\t\tLTQ_MII_MII_CFG_MIIMODE_RGMII;\n+\t\t\tsetup_gpio = 1;\n+\n+\t\t\t/* RGMII clock delays */\n+\t\t\tltq_writel(to_mii_pcdu(switch_regs, port->num),\n+\t\t\t\tport->rgmii_rx_delay << PCDU_RXDLY_SHIFT |\n+\t\t\t\tport->rgmii_tx_delay);\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\tltq_writel(to_mii_miicfg(switch_regs, port->num),\n+\t\t\tmii_cfg_reg.val);\n+\t\tbreak;\n+\tdefault:\n+\t\tbreak;\n+\t}\n+\n+\t/* Setup GPIOs for MII with external PHYs/MACs */\n+\tif (setup_gpio) {\n+\t\t/* MII/MDIO */\n+\t\tgpio_set_altfunc(42, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR,\n+\t\t\t\t\tGPIO_DIR_OUT);\n+\t\t/* MII/MDC */\n+\t\tgpio_set_altfunc(43, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR,\n+\t\t\t\t\tGPIO_DIR_OUT);\n+\t}\n+\n+\t/* Connect to internal/external PHYs */\n+\tif (port->flags & LTQ_ETH_PORT_PHY) {\n+\t\tphydev = phy_connect(priv->bus, port->phy_addr, priv->dev,\n+\t\t\t\t\tport->phy_if);\n+\t\tif (phydev)\n+\t\t\tphy_config(phydev);\n+\n+\t\tpriv->phymap[port->num] = phydev;\n+\t}\n+}\n+\n+int ltq_eth_initialize(const struct ltq_eth_board_config *board_config)\n+{\n+\tstruct eth_device *dev;\n+\tstruct mii_dev *bus;\n+\tstruct ltq_eth_priv *priv;\n+\tstruct ltq_dma_device *dma_dev;\n+\tint i, ret;\n+\n+\tbuild_check_vr9_registers();\n+\n+\tltq_dma_init();\n+\tltq_eth_hw_init();\n+\n+\tdev = calloc(1, sizeof(struct eth_device));\n+\tif (!dev)\n+\t\treturn -1;\n+\n+\tpriv = calloc(1, sizeof(struct ltq_eth_priv));\n+\tif (!priv)\n+\t\treturn -1;\n+\n+\tbus = mdio_alloc();\n+\tif (!bus)\n+\t\treturn -1;\n+\n+\tsprintf(dev->name, LTQ_ETH_DRV_NAME);\n+\tdev->priv = priv;\n+\tdev->init = ltq_eth_init;\n+\tdev->halt = ltq_eth_halt;\n+\tdev->recv = ltq_eth_recv;\n+\tdev->send = ltq_eth_send;\n+\n+\tsprintf(bus->name, LTQ_MDIO_DRV_NAME);\n+\tbus->read = vr9_switch_mdio_read;\n+\tbus->write = vr9_switch_mdio_write;\n+\tbus->priv = priv;\n+\n+\tdma_dev = &priv->dma_dev;\n+\tdma_dev->port = 0;\n+\tdma_dev->rx_chan.chan_no = 0;\n+\tdma_dev->rx_chan.class = 0;\n+\tdma_dev->rx_chan.num_desc = LTQ_ETH_RX_BUFFER_CNT;\n+\tdma_dev->rx_endian_swap = LTQ_DMA_ENDIANESS_B3_B2_B1_B0;\n+\tdma_dev->rx_burst_len = LTQ_DMA_BURST_2WORDS;\n+\tdma_dev->tx_chan.chan_no = 1;\n+\tdma_dev->tx_chan.class = 0;\n+\tdma_dev->tx_chan.num_desc = LTQ_ETH_TX_BUFFER_CNT;\n+\tdma_dev->tx_endian_swap = LTQ_DMA_ENDIANESS_B3_B2_B1_B0;\n+\tdma_dev->tx_burst_len = LTQ_DMA_BURST_2WORDS;\n+\n+\tpriv->bus = bus;\n+\tpriv->dev = dev;\n+\n+\tret = ltq_dma_register(dma_dev);\n+\tif (ret)\n+\t\treturn -1;\n+\n+\tret = mdio_register(bus);\n+\tif (ret)\n+\t\treturn -1;\n+\n+\tret = eth_register(dev);\n+\tif (ret)\n+\t\treturn -1;\n+\n+\tfor (i = 0; i < board_config->num_ports; i++)\n+\t\tltq_eth_port_config(priv, &board_config->ports[i]);\n+\n+\treturn 0;\n+}\n--- a/drivers/net/phy/Makefile\n+++ b/drivers/net/phy/Makefile\n@@ -20,6 +20,7 @@ COBJS-$(CONFIG_PHY_BROADCOM) += broadcom\n COBJS-$(CONFIG_PHY_DAVICOM) += davicom.o\n COBJS-$(CONFIG_PHY_ET1011C) += et1011c.o\n COBJS-$(CONFIG_PHY_ICPLUS) += icplus.o\n+COBJS-$(CONFIG_PHY_LANTIQ) += lantiq.o\n COBJS-$(CONFIG_PHY_LXT) += lxt.o\n COBJS-$(CONFIG_PHY_MARVELL) += marvell.o\n COBJS-$(CONFIG_PHY_MICREL) += micrel.o\n--- /dev/null\n+++ b/drivers/net/phy/lantiq.c\n@@ -0,0 +1,238 @@\n+/*\n+ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#define DEBUG\n+\n+#include <common.h>\n+#include <miiphy.h>\n+\n+#define ADVERTIZE_MPD\t\t(1 << 10)\n+\n+DECLARE_GLOBAL_DATA_PTR;\n+\n+/*\n+ * Update link status.\n+ *\n+ * Based on genphy_update_link in phylib.c\n+ */\n+static int ltq_phy_update_link(struct phy_device *phydev)\n+{\n+\tunsigned int mii_reg;\n+\n+\tmii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR);\n+\n+\t/*\n+\t * If we already saw the link up, and it hasn't gone down, then\n+\t * we don't need to wait for autoneg again\n+\t */\n+\tif (phydev->link && mii_reg & BMSR_LSTATUS)\n+\t\treturn 0;\n+\n+\tif ((mii_reg & BMSR_ANEGCAPABLE) && !(mii_reg & BMSR_ANEGCOMPLETE)) {\n+\t\tphydev->link = 0;\n+\t\treturn 0;\n+\t} else {\n+\t\t/* Read the link a second time to clear the latched state */\n+\t\tmii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR);\n+\n+\t\tif (mii_reg & BMSR_LSTATUS)\n+\t\t\tphydev->link = 1;\n+\t\telse\n+\t\t\tphydev->link = 0;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+/*\n+ * Update speed and duplex.\n+ *\n+ * Based on genphy_parse_link in phylib.c\n+ */\n+static int ltq_phy_parse_link(struct phy_device *phydev)\n+{\n+\tunsigned int mii_reg;\n+\n+\tmii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR);\n+\n+\t/* We're using autonegotiation */\n+\tif (mii_reg & BMSR_ANEGCAPABLE) {\n+\t\tu32 lpa = 0;\n+\t\tu32 gblpa = 0;\n+\n+\t\t/* Check for gigabit capability */\n+\t\tif (mii_reg & BMSR_ERCAP) {\n+\t\t\t/* We want a list of states supported by\n+\t\t\t * both PHYs in the link\n+\t\t\t */\n+\t\t\tgblpa = phy_read(phydev, MDIO_DEVAD_NONE, MII_STAT1000);\n+\t\t\tgblpa &= phy_read(phydev,\n+\t\t\t\t\tMDIO_DEVAD_NONE, MII_CTRL1000) << 2;\n+\t\t}\n+\n+\t\t/* Set the baseline so we only have to set them\n+\t\t * if they're different\n+\t\t */\n+\t\tphydev->speed = SPEED_10;\n+\t\tphydev->duplex = DUPLEX_HALF;\n+\n+\t\t/* Check the gigabit fields */\n+\t\tif (gblpa & (PHY_1000BTSR_1000FD | PHY_1000BTSR_1000HD)) {\n+\t\t\tphydev->speed = SPEED_1000;\n+\n+\t\t\tif (gblpa & PHY_1000BTSR_1000FD)\n+\t\t\t\tphydev->duplex = DUPLEX_FULL;\n+\n+\t\t\t/* We're done! */\n+\t\t\treturn 0;\n+\t\t}\n+\n+\t\tlpa = phy_read(phydev, MDIO_DEVAD_NONE, MII_ADVERTISE);\n+\t\tlpa &= phy_read(phydev, MDIO_DEVAD_NONE, MII_LPA);\n+\n+\t\tif (lpa & (LPA_100FULL | LPA_100HALF)) {\n+\t\t\tphydev->speed = SPEED_100;\n+\n+\t\t\tif (lpa & LPA_100FULL)\n+\t\t\t\tphydev->duplex = DUPLEX_FULL;\n+\n+\t\t} else if (lpa & LPA_10FULL)\n+\t\t\tphydev->duplex = DUPLEX_FULL;\n+\t} else {\n+\t\tu32 bmcr = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR);\n+\n+\t\tphydev->speed = SPEED_10;\n+\t\tphydev->duplex = DUPLEX_HALF;\n+\n+\t\tif (bmcr & BMCR_FULLDPLX)\n+\t\t\tphydev->duplex = DUPLEX_FULL;\n+\n+\t\tif (bmcr & BMCR_SPEED1000)\n+\t\t\tphydev->speed = SPEED_1000;\n+\t\telse if (bmcr & BMCR_SPEED100)\n+\t\t\tphydev->speed = SPEED_100;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int ltq_phy_config(struct phy_device *phydev)\n+{\n+\tu16 val;\n+\n+\t/* Advertise as Multi-port device */\n+\tval = phy_read(phydev, MDIO_DEVAD_NONE, MII_CTRL1000);\n+\tval |= ADVERTIZE_MPD;\n+\tphy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, val);\n+\n+\tgenphy_config_aneg(phydev);\n+\n+\treturn 0;\n+}\n+\n+static int ltq_phy_startup(struct phy_device *phydev)\n+{\n+\t/*\n+\t * Update PHY status immediately without any delays as genphy_startup\n+\t * does because VRX200 switch needs to be configured dependent\n+\t * on this information.\n+\t */\n+\tltq_phy_update_link(phydev);\n+\tltq_phy_parse_link(phydev);\n+\n+\tdebug(\"ltq_phy: addr %d, link %d, speed %d, duplex %d\\n\",\n+\t\tphydev->addr, phydev->link, phydev->speed, phydev->duplex);\n+\n+\treturn 0;\n+}\n+\n+static struct phy_driver xrx_11g_13_driver = {\n+\t.name = \"Lantiq XWAY XRX PHY11G v1.3 and earlier\",\n+\t.uid = 0x030260D0,\n+\t.mask = 0xFFFFFFF0,\n+\t.features = PHY_GBIT_FEATURES,\n+\t.config = ltq_phy_config,\n+\t.startup = ltq_phy_startup,\n+\t.shutdown = genphy_shutdown,\n+};\n+\n+static struct phy_driver xrx_11g_14_driver = {\n+\t.name = \"Lantiq XWAY XRX PHY11G v1.4 and later\",\n+\t.uid = 0xd565a408,\n+\t.mask = 0xFFFFFFF8,\n+\t.features = PHY_GBIT_FEATURES,\n+\t.config = ltq_phy_config,\n+\t.startup = ltq_phy_startup,\n+\t.shutdown = genphy_shutdown,\n+};\n+\n+static struct phy_driver xrx_22f_14_driver = {\n+\t.name = \"Lantiq XWAY XRX PHY22F v1.4 and later\",\n+\t.uid = 0xd565a418,\n+\t.mask = 0xFFFFFFF8,\n+\t.features = PHY_BASIC_FEATURES,\n+\t.config = ltq_phy_config,\n+\t.startup = ltq_phy_startup,\n+\t.shutdown = genphy_shutdown,\n+};\n+\n+static struct phy_driver pef7071_driver = {\n+\t.name = \"Lantiq XWAY PEF7071\",\n+\t.uid = 0xd565a400,\n+\t.mask = 0xFFFFFFF8,\n+\t.features = PHY_GBIT_FEATURES,\n+\t.config = ltq_phy_config,\n+\t.startup = ltq_phy_startup,\n+\t.shutdown = genphy_shutdown,\n+};\n+\n+static struct phy_driver xrx_genphy_driver = {\n+\t.name = \"Generic PHY at Lantiq XWAY XRX switch\",\n+\t.uid = 0,\n+\t.mask = 0,\n+\t.features = 0,\n+\t.config = genphy_config,\n+\t.startup = ltq_phy_startup,\n+\t.shutdown = genphy_shutdown,\n+};\n+\n+int phy_lantiq_init(void)\n+{\n+#ifdef CONFIG_NEEDS_MANUAL_RELOC\n+\txrx_11g_13_driver.config = ltq_phy_config;\n+\txrx_11g_13_driver.startup = ltq_phy_startup;\n+\txrx_11g_13_driver.shutdown = genphy_shutdown;\n+\txrx_11g_13_driver.name += gd->reloc_off;\n+\n+\txrx_11g_14_driver.config = ltq_phy_config;\n+\txrx_11g_14_driver.startup = ltq_phy_startup;\n+\txrx_11g_14_driver.shutdown = genphy_shutdown;\n+\txrx_11g_14_driver.name += gd->reloc_off;\n+\n+\txrx_22f_14_driver.config = ltq_phy_config;\n+\txrx_22f_14_driver.startup = ltq_phy_startup;\n+\txrx_22f_14_driver.shutdown = genphy_shutdown;\n+\txrx_22f_14_driver.name += gd->reloc_off;\n+\n+\tpef7071_driver.config = ltq_phy_config;\n+\tpef7071_driver.startup = ltq_phy_startup;\n+\tpef7071_driver.shutdown = genphy_shutdown;\n+\tpef7071_driver.name += gd->reloc_off;\n+\n+\txrx_genphy_driver.config = genphy_config;\n+\txrx_genphy_driver.startup = ltq_phy_startup;\n+\txrx_genphy_driver.shutdown = genphy_shutdown;\n+\txrx_genphy_driver.name += gd->reloc_off;\n+#endif\n+\n+\tphy_register(&xrx_11g_13_driver);\n+\tphy_register(&xrx_11g_14_driver);\n+\tphy_register(&xrx_22f_14_driver);\n+\tphy_register(&pef7071_driver);\n+\tphy_register(&xrx_genphy_driver);\n+\n+\treturn 0;\n+}\n--- a/drivers/net/phy/phy.c\n+++ b/drivers/net/phy/phy.c\n@@ -16,9 +16,10 @@\n #include <command.h>\n #include <miiphy.h>\n #include <phy.h>\n-#include <errno.h>\n #include <linux/err.h>\n \n+DECLARE_GLOBAL_DATA_PTR;\n+\n /* Generic PHY support and helper functions */\n \n /**\n@@ -440,6 +441,16 @@ static LIST_HEAD(phy_drivers);\n \n int phy_init(void)\n {\n+#ifdef CONFIG_NEEDS_MANUAL_RELOC\n+\tINIT_LIST_HEAD(&phy_drivers);\n+\n+\tgenphy_driver.config = genphy_config;\n+\tgenphy_driver.startup = genphy_startup;\n+\tgenphy_driver.shutdown = genphy_shutdown;\n+\n+\tgenphy_driver.name += gd->reloc_off;\n+#endif\n+\n #ifdef CONFIG_PHY_ATHEROS\n \tphy_atheros_init();\n #endif\n@@ -455,6 +466,9 @@ int phy_init(void)\n #ifdef CONFIG_PHY_ICPLUS\n \tphy_icplus_init();\n #endif\n+#ifdef CONFIG_PHY_LANTIQ\n+\tphy_lantiq_init();\n+#endif\n #ifdef CONFIG_PHY_LXT\n \tphy_lxt_init();\n #endif\n--- a/drivers/serial/Makefile\n+++ b/drivers/serial/Makefile\n@@ -24,6 +24,7 @@ COBJS-$(CONFIG_SYS_NS16550_SERIAL) += se\n COBJS-$(CONFIG_IMX_SERIAL) += serial_imx.o\n COBJS-$(CONFIG_IXP_SERIAL) += serial_ixp.o\n COBJS-$(CONFIG_KS8695_SERIAL) += serial_ks8695.o\n+COBJS-$(CONFIG_LANTIQ_SERIAL) += serial_lantiq.o\n COBJS-$(CONFIG_MAX3100_SERIAL) += serial_max3100.o\n COBJS-$(CONFIG_MXC_UART) += serial_mxc.o\n COBJS-$(CONFIG_PL010_SERIAL) += serial_pl01x.o\n--- a/drivers/serial/serial.c\n+++ b/drivers/serial/serial.c\n@@ -160,6 +160,7 @@ serial_initfunc(sa1100_serial_initialize\n serial_initfunc(sh_serial_initialize);\n serial_initfunc(arm_dcc_initialize);\n serial_initfunc(mxs_auart_initialize);\n+serial_initfunc(ltq_serial_initialize);\n \n /**\n  * serial_register() - Register serial driver with serial driver core\n@@ -253,6 +254,7 @@ void serial_initialize(void)\n \tsh_serial_initialize();\n \tarm_dcc_initialize();\n \tmxs_auart_initialize();\n+\tltq_serial_initialize();\n \n \tserial_assign(default_serial_console()->name);\n }\n--- /dev/null\n+++ b/drivers/serial/serial_lantiq.c\n@@ -0,0 +1,263 @@\n+/*\n+ * Copyright (C) 2010 Thomas Langer <thomas.langer@lantiq.com>\n+ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#include <common.h>\n+#include <serial.h>\n+#include <asm/errno.h>\n+#include <asm/arch/soc.h>\n+#include <asm/lantiq/clk.h>\n+#include <asm/lantiq/io.h>\n+\n+#if CONFIG_CONSOLE_ASC == 0\n+#define LTQ_ASC_BASE\t\t\tLTQ_ASC0_BASE\n+#else\n+#define LTQ_ASC_BASE\t\t\tLTQ_ASC1_BASE\n+#endif\n+\n+#define LTQ_ASC_ID_TXFS_SHIFT\t\t24\n+#define LTQ_ASC_ID_TXFS_MASK\t\t(0x3F << LTQ_ASC_ID_TXFS_SHIFT)\n+#define LTQ_ASC_ID_RXFS_SHIFT\t\t16\n+#define LTQ_ASC_ID_RXFS_MASK\t\t(0x3F << LTQ_ASC_ID_RXFS_SHIFT)\n+\n+#define LTQ_ASC_MCON_R\t\t\t(1 << 15)\n+#define LTQ_ASC_MCON_FDE\t\t(1 << 9)\n+\n+#define LTQ_ASC_WHBSTATE_SETREN\t\t(1 << 1)\n+#define LTQ_ASC_WHBSTATE_CLRREN\t\t(1 << 0)\n+\n+#define LTQ_ASC_RXFCON_RXFITL_SHIFT\t8\n+#define LTQ_ASC_RXFCON_RXFITL_MASK\t(0x3F << LTQ_ASC_RXFCON_RXFITL_SHIFT)\n+#define LTQ_ASC_RXFCON_RXFITL_RXFFLU\t(1 << 1)\n+#define LTQ_ASC_RXFCON_RXFITL_RXFEN\t(1 << 0)\n+\n+#define LTQ_ASC_TXFCON_TXFITL_SHIFT\t8\n+#define LTQ_ASC_TXFCON_TXFITL_MASK\t(0x3F << LTQ_ASC_TXFCON_TXFITL_SHIFT)\n+#define LTQ_ASC_TXFCON_TXFITL_TXFFLU\t(1 << 1)\n+#define LTQ_ASC_TXFCON_TXFITL_TXFEN\t(1 << 0)\n+\n+#define LTQ_ASC_FSTAT_TXFREE_SHIFT\t24\n+#define LTQ_ASC_FSTAT_TXFREE_MASK\t(0x3F << LTQ_ASC_FSTAT_TXFREE_SHIFT)\n+#define LTQ_ASC_FSTAT_RXFREE_SHIFT\t16\n+#define LTQ_ASC_FSTAT_RXFREE_MASK\t(0x3F << LTQ_ASC_FSTAT_RXFREE_SHIFT)\n+#define LTQ_ASC_FSTAT_TXFFL_SHIFT\t8\n+#define LTQ_ASC_FSTAT_TXFFL_MASK\t(0x3F << LTQ_ASC_FSTAT_TXFFL_SHIFT)\n+#define LTQ_ASC_FSTAT_RXFFL_MASK\t0x3F\n+\n+#ifdef __BIG_ENDIAN\n+#define LTQ_ASC_RBUF_OFFSET\t\t3\n+#define LTQ_ASC_TBUF_OFFSET\t\t3\n+#else\n+#define LTQ_ASC_RBUF_OFFSET\t\t0\n+#define LTQ_ASC_TBUF_OFFSET\t\t0\n+#endif\n+\n+struct ltq_asc_regs {\n+\tu32\tclc;\n+\tu32\tpisel;\n+\tu32\tid;\n+\tu32\trsvd0;\n+\tu32\tmcon;\n+\tu32\tstate;\n+\tu32\twhbstate;\n+\tu32\trsvd1;\n+\tu8\ttbuf[4];\n+\tu8\trbuf[4];\n+\tu32\trsvd2[2];\n+\tu32\tabcon;\n+\tu32\tabstat;\n+\tu32\twhbabcon;\n+\tu32\twhbabstat;\n+\tu32\trxfcon;\n+\tu32\ttxfcon;\n+\tu32\tfstat;\n+\tu32\trsvd3;\n+\tu32\tbg;\n+\tu32\tbg_timer;\n+\tu32\tfdv;\n+\tu32\tpmw;\n+\tu32\tmodcon;\n+\tu32\tmodstat;\n+};\n+\n+DECLARE_GLOBAL_DATA_PTR;\n+\n+static struct ltq_asc_regs *ltq_asc_regs =\n+\t(struct ltq_asc_regs *) CKSEG1ADDR(LTQ_ASC_BASE);\n+\n+static int ltq_serial_init(void)\n+{\n+\t/* Set clock divider for normal run mode to 1 and enable module */\n+\tltq_writel(&ltq_asc_regs->clc, 0x100);\n+\n+\t/* Reset MCON register */\n+\tltq_writel(&ltq_asc_regs->mcon, 0);\n+\n+\t/* Use Port A as receiver input */\n+\tltq_writel(&ltq_asc_regs->pisel, 0);\n+\n+\t/* Enable and flush RX/TX FIFOs */\n+\tltq_setbits(&ltq_asc_regs->rxfcon,\n+\t\tLTQ_ASC_RXFCON_RXFITL_RXFFLU | LTQ_ASC_RXFCON_RXFITL_RXFEN);\n+\tltq_setbits(&ltq_asc_regs->txfcon,\n+\t\tLTQ_ASC_TXFCON_TXFITL_TXFFLU | LTQ_ASC_TXFCON_TXFITL_TXFEN);\n+\n+\tserial_setbrg();\n+\n+\t/* Disable error flags, enable receiver */\n+\tltq_writel(&ltq_asc_regs->whbstate, LTQ_ASC_WHBSTATE_SETREN);\n+\n+\treturn 0;\n+}\n+\n+/*\n+ *             fdv       asc_clk\n+ * Baudrate = ----- * -------------\n+ *             512    16 * (bg + 1)\n+ */\n+static void ltq_serial_calc_br_fdv(unsigned long asc_clk,\n+\t\t\t\t\tunsigned long baudrate, u16 *fdv,\n+\t\t\t\t\tu16 *bg)\n+{\n+\tconst u32 c = asc_clk / (16 * 512);\n+\tu32 diff1, diff2;\n+\tu32 bg_calc, br_calc, i;\n+\n+\tdiff1 = baudrate;\n+\tfor (i = 512; i > 0; i--) {\n+\t\t/* Calc bg for current fdv value */\n+\t\tbg_calc = i * c / baudrate;\n+\n+\t\t/* Impossible baudrate */\n+\t\tif (!bg_calc)\n+\t\t\treturn;\n+\n+\t\t/*\n+\t\t * Calc diff to target baudrate dependent on current\n+\t\t * bg and fdv values\n+\t\t */\n+\t\tbr_calc = i * c / bg_calc;\n+\t\tif (br_calc > baudrate)\n+\t\t\tdiff2 = br_calc - baudrate;\n+\t\telse\n+\t\t\tdiff2 = baudrate - br_calc;\n+\n+\t\t/* Perfect values found */\n+\t\tif (diff2 == 0) {\n+\t\t\t*fdv = i;\n+\t\t\t*bg = bg_calc - 1;\n+\t\t\treturn;\n+\t\t}\n+\n+\t\tif (diff2 < diff1) {\n+\t\t\t*fdv = i;\n+\t\t\t*bg = bg_calc - 1;\n+\t\t\tdiff1 = diff2;\n+\t\t}\n+\t}\n+}\n+\n+static void ltq_serial_setbrg(void)\n+{\n+\tunsigned long asc_clk, baudrate;\n+\tu16 bg = 0;\n+\tu16 fdv = 511;\n+\n+\t/* ASC clock is same as FPI clock with CLC.RMS = 1 */\n+\tasc_clk = ltq_get_bus_clock();\n+\tbaudrate = gd->baudrate;\n+\n+\t/* Calculate FDV and BG values */\n+\tltq_serial_calc_br_fdv(asc_clk, baudrate, &fdv, &bg);\n+\n+\t/* Disable baudrate generator */\n+\tltq_clrbits(&ltq_asc_regs->mcon, LTQ_ASC_MCON_R);\n+\n+\t/* Enable fractional divider */\n+\tltq_setbits(&ltq_asc_regs->mcon, LTQ_ASC_MCON_FDE);\n+\n+\t/* Set fdv and bg values */\n+\tltq_writel(&ltq_asc_regs->fdv, fdv);\n+\tltq_writel(&ltq_asc_regs->bg, bg);\n+\n+\t/* Enable baudrate generator */\n+\tltq_setbits(&ltq_asc_regs->mcon, LTQ_ASC_MCON_R);\n+}\n+\n+static unsigned int ltq_serial_tx_free(void)\n+{\n+\tunsigned int txfree;\n+\n+\ttxfree = (ltq_readl(&ltq_asc_regs->fstat) &\n+\t\t\tLTQ_ASC_FSTAT_TXFREE_MASK) >>\n+\t\t\tLTQ_ASC_FSTAT_TXFREE_SHIFT;\n+\n+\treturn txfree;\n+}\n+\n+static unsigned int ltq_serial_rx_fill(void)\n+{\n+\tunsigned int rxffl;\n+\n+\trxffl = ltq_readl(&ltq_asc_regs->fstat) & LTQ_ASC_FSTAT_RXFFL_MASK;\n+\n+\treturn rxffl;\n+}\n+\n+static void ltq_serial_tx(const char c)\n+{\n+\tltq_writeb(&ltq_asc_regs->tbuf[LTQ_ASC_TBUF_OFFSET], c);\n+}\n+\n+static u8 ltq_serial_rx(void)\n+{\n+\treturn ltq_readb(&ltq_asc_regs->rbuf[LTQ_ASC_RBUF_OFFSET]);\n+}\n+\n+static void ltq_serial_putc(const char c)\n+{\n+\tif (c == '\\n')\n+\t\tltq_serial_putc('\\r');\n+\n+\twhile (!ltq_serial_tx_free())\n+\t\t;\n+\n+\tltq_serial_tx(c);\n+}\n+\n+static int ltq_serial_getc(void)\n+{\n+\twhile (!ltq_serial_rx_fill())\n+\t\t;\n+\n+\treturn ltq_serial_rx();\n+}\n+\n+static int ltq_serial_tstc(void)\n+{\n+\treturn (0 != ltq_serial_rx_fill());\n+}\n+\n+static struct serial_device ltq_serial_drv = {\n+\t.name\t= \"ltq_serial\",\n+\t.start\t= ltq_serial_init,\n+\t.stop\t= NULL,\n+\t.setbrg\t= ltq_serial_setbrg,\n+\t.putc\t= ltq_serial_putc,\n+\t.puts\t= default_serial_puts,\n+\t.getc\t= ltq_serial_getc,\n+\t.tstc\t= ltq_serial_tstc,\n+};\n+\n+void ltq_serial_initialize(void)\n+{\n+\tserial_register(&ltq_serial_drv);\n+}\n+\n+__weak struct serial_device *default_serial_console(void)\n+{\n+\treturn &ltq_serial_drv;\n+}\n--- a/drivers/spi/Makefile\n+++ b/drivers/spi/Makefile\n@@ -25,6 +25,7 @@ COBJS-$(CONFIG_DAVINCI_SPI) += davinci_s\n COBJS-$(CONFIG_EXYNOS_SPI) += exynos_spi.o\n COBJS-$(CONFIG_ICH_SPI) +=  ich.o\n COBJS-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o\n+COBJS-$(CONFIG_LANTIQ_SPI) += lantiq_spi.o\n COBJS-$(CONFIG_MPC52XX_SPI) += mpc52xx_spi.o\n COBJS-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o\n COBJS-$(CONFIG_MXC_SPI) += mxc_spi.o\n--- /dev/null\n+++ b/drivers/spi/lantiq_spi.c\n@@ -0,0 +1,666 @@\n+/*\n+ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#include <common.h>\n+#include <spi.h>\n+#include <malloc.h>\n+#include <watchdog.h>\n+#include <asm/gpio.h>\n+#include <asm/lantiq/io.h>\n+#include <asm/lantiq/clk.h>\n+#include <asm/lantiq/pm.h>\n+#include <asm/arch/soc.h>\n+\n+#define LTQ_SPI_CLC_RMC_SHIFT\t\t8\n+#define LTQ_SPI_CLC_RMC_MASK\t\t(0xFF << LTQ_SPI_CLC_RMC_SHIFT)\n+#define LTQ_SPI_CLC_DISS\t\t(1 << 1)\n+#define LTQ_SPI_CLC_DISR\t\t1\n+\n+#define LTQ_SPI_ID_TXFS_SHIFT\t\t24\n+#define LTQ_SPI_ID_TXFS_MASK\t\t(0x3F << LTQ_SPI_ID_TXFS_SHIFT)\n+#define LTQ_SPI_ID_RXFS_SHIFT\t\t16\n+#define LTQ_SPI_ID_RXFS_MASK\t\t(0x3F << LTQ_SPI_ID_RXFS_SHIFT)\n+\n+#define LTQ_SPI_CON_ENBV\t\t(1 << 22)\n+#define LTQ_SPI_CON_BM_SHIFT\t\t16\n+#define LTQ_SPI_CON_BM_MASK\t\t(0x1F << LTQ_SPI_CON_BM_SHIFT)\n+#define LTQ_SPI_CON_IDLE\t\t(1 << 23)\n+#define LTQ_SPI_CON_RUEN\t\t(1 << 12)\n+#define LTQ_SPI_CON_AEN\t\t\t(1 << 10)\n+#define LTQ_SPI_CON_REN\t\t\t(1 << 9)\n+#define LTQ_SPI_CON_TEN\t\t\t(1 << 8)\n+#define LTQ_SPI_CON_LB\t\t\t(1 << 7)\n+#define LTQ_SPI_CON_PO\t\t\t(1 << 6)\n+#define LTQ_SPI_CON_PH\t\t\t(1 << 5)\n+#define LTQ_SPI_CON_HB\t\t\t(1 << 4)\n+#define LTQ_SPI_CON_RXOFF\t\t(1 << 1)\n+#define LTQ_SPI_CON_TXOFF\t\t1\n+\n+#define LTQ_SPI_STAT_RXBV_SHIFT\t\t28\n+#define LTQ_SPI_STAT_RXBV_MASK\t\t(0x7 << LTQ_SPI_STAT_RXBV_SHIFT)\n+#define LTQ_SPI_STAT_BSY\t\t(1 << 13)\n+\n+#define LTQ_SPI_WHBSTATE_SETMS\t\t(1 << 3)\n+#define LTQ_SPI_WHBSTATE_CLRMS\t\t(1 << 2)\n+#define LTQ_SPI_WHBSTATE_SETEN\t\t(1 << 1)\n+#define LTQ_SPI_WHBSTATE_CLREN\t\t1\n+#define LTQ_SPI_WHBSTATE_CLR_ERRORS\t0x0F50\n+\n+#define LTQ_SPI_TXFCON_TXFLU\t\t(1 << 1)\n+#define LTQ_SPI_TXFCON_TXFEN\t\t1\n+\n+#define LTQ_SPI_RXFCON_RXFLU\t\t(1 << 1)\n+#define LTQ_SPI_RXFCON_RXFEN\t\t1\n+\n+#define LTQ_SPI_FSTAT_RXFFL_MASK\t0x3f\n+#define LTQ_SPI_FSTAT_TXFFL_SHIFT\t8\n+#define LTQ_SPI_FSTAT_TXFFL_MASK\t(0x3f << LTQ_SPI_FSTAT_TXFFL_SHIFT)\n+\n+#define LTQ_SPI_RXREQ_RXCNT_MASK\t0xFFFF\n+#define LTQ_SPI_RXCNT_TODO_MASK\t\t0xFFFF\n+\n+#define LTQ_SPI_GPIO_DIN\t\t16\n+#define LTQ_SPI_GPIO_DOUT\t\t17\n+#define LTQ_SPI_GPIO_CLK\t\t18\n+\n+struct ltq_spi_regs {\n+\t__be32\tclc;\t\t/* Clock control */\n+\t__be32\tpisel;\t\t/* Port input select */\n+\t__be32\tid;\t\t/* Identification */\n+\t__be32\trsvd0;\n+\t__be32\tcon;\t\t/* Control */\n+\t__be32\tstat;\t\t/* Status */\n+\t__be32\twhbstate;\t/* Write HW modified state */\n+\t__be32\trsvd1;\n+\t__be32\ttb;\t\t/* Transmit buffer */\n+\t__be32\trb;\t\t/* Receive buffer */\n+\t__be32\trsvd2[2];\n+\t__be32\trxfcon;\t\t/* Recevie FIFO control */\n+\t__be32\ttxfcon;\t\t/* Transmit FIFO control */\n+\t__be32\tfstat;\t\t/* FIFO status */\n+\t__be32\trsvd3;\n+\t__be32\tbrt;\t\t/* Baudrate timer */\n+\t__be32\tbrstat;\t\t/* Baudrate timer status */\n+\t__be32\trsvd4[6];\n+\t__be32\tsfcon;\t\t/* Serial frame control */\n+\t__be32\tsfstat;\t\t/* Serial frame status */\n+\t__be32\trsvd5[2];\n+\t__be32\tgpocon;\t\t/* General purpose output control */\n+\t__be32\tgpostat;\t/* General purpose output status */\n+\t__be32\tfgpo;\t\t/* Force general purpose output */\n+\t__be32\trsvd6;\n+\t__be32\trxreq;\t\t/* Receive request */\n+\t__be32\trxcnt;\t\t/* Receive count */\n+\t__be32\trsvd7[25];\n+\t__be32\tdmacon;\t\t/* DMA control */\n+\t__be32\trsvd8;\n+\t__be32\tirnen;\t\t/* Interrupt node enable */\n+\t__be32\tirnicr;\t\t/* Interrupt node interrupt capture */\n+\t__be32\tirncr;\t\t/* Interrupt node control */\n+};\n+\n+struct ltq_spi_drv_data {\n+\tstruct ltq_spi_regs __iomem *regs;\n+\n+\tstruct spi_slave slave;\n+\tunsigned int max_hz;\n+\tunsigned int mode;\n+\tunsigned int tx_todo;\n+\tunsigned int rx_todo;\n+\tunsigned int rx_req;\n+\tunsigned int bits_per_word;\n+\tunsigned int speed_hz;\n+\tconst u8 *tx;\n+\tu8 *rx;\n+\tint status;\n+};\n+\n+static struct ltq_spi_drv_data *to_ltq_spi_slave(struct spi_slave *slave)\n+{\n+\treturn container_of(slave, struct ltq_spi_drv_data, slave);\n+}\n+\n+#ifdef CONFIG_SPL_BUILD\n+/*\n+ * We do not have or want malloc in a SPI flash SPL.\n+ * Neither we have to support multiple SPI slaves. Thus we put the\n+ * SPI slave context in BSS for SPL builds.\n+ */\n+static struct ltq_spi_drv_data ltq_spi_slave;\n+\n+static struct ltq_spi_drv_data *ltq_spi_slave_alloc(unsigned int bus,\n+\t\t\t\t\t\t\tunsigned int cs)\n+{\n+\tltq_spi_slave.slave.bus = bus;\n+\tltq_spi_slave.slave.cs = cs;\n+\n+\treturn &ltq_spi_slave;\n+}\n+\n+static void ltq_spi_slave_free(struct spi_slave *slave)\n+{\n+}\n+#else\n+static struct ltq_spi_drv_data *ltq_spi_slave_alloc(unsigned int bus,\n+\t\t\t\t\t\t\tunsigned int cs)\n+{\n+\treturn spi_alloc_slave(struct ltq_spi_drv_data, bus, cs);\n+}\n+\n+static void ltq_spi_slave_free(struct spi_slave *slave)\n+{\n+\tstruct ltq_spi_drv_data *drv;\n+\n+\tif (slave) {\n+\t\tdrv = to_ltq_spi_slave(slave);\n+\t\tfree(drv);\n+\t}\n+}\n+#endif\n+\n+static unsigned int tx_fifo_size(struct ltq_spi_drv_data *drv)\n+{\n+\tu32 id = ltq_readl(&drv->regs->id);\n+\n+\treturn (id & LTQ_SPI_ID_TXFS_MASK) >> LTQ_SPI_ID_TXFS_SHIFT;\n+}\n+\n+static unsigned int rx_fifo_size(struct ltq_spi_drv_data *drv)\n+{\n+\tu32 id = ltq_readl(&drv->regs->id);\n+\n+\treturn (id & LTQ_SPI_ID_RXFS_MASK) >> LTQ_SPI_ID_RXFS_SHIFT;\n+}\n+\n+static unsigned int tx_fifo_level(struct ltq_spi_drv_data *drv)\n+{\n+\tu32 fstat = ltq_readl(&drv->regs->fstat);\n+\n+\treturn (fstat & LTQ_SPI_FSTAT_TXFFL_MASK) >> LTQ_SPI_FSTAT_TXFFL_SHIFT;\n+}\n+\n+static unsigned int rx_fifo_level(struct ltq_spi_drv_data *drv)\n+{\n+\tu32 fstat = ltq_readl(&drv->regs->fstat);\n+\n+\treturn fstat & LTQ_SPI_FSTAT_RXFFL_MASK;\n+}\n+\n+static unsigned int tx_fifo_free(struct ltq_spi_drv_data *drv)\n+{\n+\treturn tx_fifo_size(drv) - tx_fifo_level(drv);\n+}\n+\n+static void hw_power_on(struct ltq_spi_drv_data *drv)\n+{\n+\tu32 clc;\n+\n+\t/* Power-up mdule */\n+\tltq_pm_enable(LTQ_PM_SPI);\n+\n+\t/*\n+\t * Set clock divider for run mode to 1 to\n+\t * run at same frequency as FPI bus\n+\t */\n+\tclc = (1 << LTQ_SPI_CLC_RMC_SHIFT);\n+\tltq_writel(&drv->regs->clc, clc);\n+}\n+\n+static void hw_reset_fifos(struct ltq_spi_drv_data *drv)\n+{\n+\tu32 val;\n+\n+\tval = LTQ_SPI_TXFCON_TXFEN | LTQ_SPI_TXFCON_TXFLU;\n+\tltq_writel(&drv->regs->txfcon, val);\n+\n+\tval = LTQ_SPI_RXFCON_RXFEN | LTQ_SPI_RXFCON_RXFLU;\n+\tltq_writel(&drv->regs->rxfcon, val);\n+}\n+\n+static int hw_is_busy(struct ltq_spi_drv_data *drv)\n+{\n+\tu32 stat = ltq_readl(&drv->regs->stat);\n+\n+\treturn stat & LTQ_SPI_STAT_BSY;\n+}\n+\n+static void hw_enter_config_mode(struct ltq_spi_drv_data *drv)\n+{\n+\tltq_writel(&drv->regs->whbstate, LTQ_SPI_WHBSTATE_CLREN);\n+}\n+\n+static void hw_enter_active_mode(struct ltq_spi_drv_data *drv)\n+{\n+\tltq_writel(&drv->regs->whbstate, LTQ_SPI_WHBSTATE_SETEN);\n+}\n+\n+static void hw_setup_speed_hz(struct ltq_spi_drv_data *drv,\n+\t\t\t\tunsigned int max_speed_hz)\n+{\n+\tunsigned int spi_hz, speed_hz, brt;\n+\n+\t/*\n+\t * SPI module clock is derived from FPI bus clock dependent on\n+\t * divider value in CLC.RMS which is always set to 1.\n+\t *\n+\t *                 f_SPI\n+\t * baudrate = --------------\n+\t *             2 * (BR + 1)\n+\t */\n+\tspi_hz = ltq_get_bus_clock() / 2;\n+\n+\t/* TODO: optimize baudrate calculation */\n+\tfor (brt = 0; brt < 0xFFFF; brt++) {\n+\t\tspeed_hz = spi_hz / (brt + 1);\n+\t\tif (speed_hz <= max_speed_hz)\n+\t\t\tbreak;\n+\t}\n+\n+\tltq_writel(&drv->regs->brt, brt);\n+}\n+\n+static void hw_setup_bits_per_word(struct ltq_spi_drv_data *drv,\n+\t\t\t\t\tunsigned int bits_per_word)\n+{\n+\tu32 bm;\n+\n+\t/* CON.BM value = bits_per_word - 1 */\n+\tbm = (bits_per_word - 1) << LTQ_SPI_CON_BM_SHIFT;\n+\n+\tltq_clrsetbits(&drv->regs->con, LTQ_SPI_CON_BM_MASK, bm);\n+}\n+\n+static void hw_setup_clock_mode(struct ltq_spi_drv_data *drv, unsigned int mode)\n+{\n+\tu32 con_set = 0, con_clr = 0;\n+\n+\t/*\n+\t * SPI mode mapping in CON register:\n+\t * Mode CPOL CPHA CON.PO CON.PH\n+\t *  0    0    0      0      1\n+\t *  1    0    1      0      0\n+\t *  2    1    0      1      1\n+\t *  3    1    1      1      0\n+\t */\n+\tif (mode & SPI_CPHA)\n+\t\tcon_clr |= LTQ_SPI_CON_PH;\n+\telse\n+\t\tcon_set |= LTQ_SPI_CON_PH;\n+\n+\tif (mode & SPI_CPOL)\n+\t\tcon_set |= LTQ_SPI_CON_PO | LTQ_SPI_CON_IDLE;\n+\telse\n+\t\tcon_clr |= LTQ_SPI_CON_PO | LTQ_SPI_CON_IDLE;\n+\n+\t/* Set heading control */\n+\tif (mode & SPI_LSB_FIRST)\n+\t\tcon_clr |= LTQ_SPI_CON_HB;\n+\telse\n+\t\tcon_set |= LTQ_SPI_CON_HB;\n+\n+\t/* Set loopback mode */\n+\tif (mode & SPI_LOOP)\n+\t\tcon_set |= LTQ_SPI_CON_LB;\n+\telse\n+\t\tcon_clr |= LTQ_SPI_CON_LB;\n+\n+\tltq_clrsetbits(&drv->regs->con, con_clr, con_set);\n+}\n+\n+static void hw_set_rxtx(struct ltq_spi_drv_data *drv)\n+{\n+\tu32 con;\n+\n+\t/* Configure transmitter and receiver */\n+\tcon = ltq_readl(&drv->regs->con);\n+\tif (drv->tx)\n+\t\tcon &= ~LTQ_SPI_CON_TXOFF;\n+\telse\n+\t\tcon |= LTQ_SPI_CON_TXOFF;\n+\n+\tif (drv->rx)\n+\t\tcon &= ~LTQ_SPI_CON_RXOFF;\n+\telse\n+\t\tcon |= LTQ_SPI_CON_RXOFF;\n+\n+\tltq_writel(&drv->regs->con, con);\n+}\n+\n+static void hw_init(struct ltq_spi_drv_data *drv)\n+{\n+\thw_power_on(drv);\n+\n+\t/* Put controller into config mode */\n+\thw_enter_config_mode(drv);\n+\n+\t/* Disable all interrupts */\n+\tltq_writel(&drv->regs->irnen, 0);\n+\n+\t/* Clear error flags */\n+\tltq_clrsetbits(&drv->regs->whbstate, 0, LTQ_SPI_WHBSTATE_CLR_ERRORS);\n+\n+\t/* Enable error checking, disable TX/RX */\n+\tltq_writel(&drv->regs->con, LTQ_SPI_CON_RUEN | LTQ_SPI_CON_AEN |\n+\t\t\tLTQ_SPI_CON_TEN | LTQ_SPI_CON_REN | LTQ_SPI_CON_TXOFF |\n+\t\t\tLTQ_SPI_CON_RXOFF);\n+\n+\t/* Setup default SPI mode */\n+\tdrv->bits_per_word = 8;\n+\tdrv->speed_hz = 0;\n+\thw_setup_bits_per_word(drv, drv->bits_per_word);\n+\thw_setup_clock_mode(drv, SPI_MODE_0);\n+\n+\t/* Enable master mode and clear error flags */\n+\tltq_writel(&drv->regs->whbstate, LTQ_SPI_WHBSTATE_SETMS |\n+\t\t\tLTQ_SPI_WHBSTATE_CLR_ERRORS);\n+\n+\t/* Reset GPIO/CS registers */\n+\tltq_writel(&drv->regs->gpocon, 0);\n+\tltq_writel(&drv->regs->fgpo, 0xFF00);\n+\n+\t/* Enable and flush FIFOs */\n+\thw_reset_fifos(drv);\n+\n+\t/* SPI/DIN input */\n+\tgpio_set_altfunc(16, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_IN);\n+\t/* SPI/DOUT output */\n+\tgpio_set_altfunc(17, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);\n+\t/* SPI/CLK output */\n+\tgpio_set_altfunc(18, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);\n+}\n+\n+static void tx_fifo_write(struct ltq_spi_drv_data *drv)\n+{\n+\tconst u8 *tx8;\n+\tconst u16 *tx16;\n+\tconst u32 *tx32;\n+\tu32 data;\n+\tunsigned int tx_free = tx_fifo_free(drv);\n+\n+\twhile (drv->tx_todo && tx_free) {\n+\t\tswitch (drv->bits_per_word) {\n+\t\tcase 8:\n+\t\t\ttx8 = drv->tx;\n+\t\t\tdata = *tx8;\n+\t\t\tdrv->tx_todo--;\n+\t\t\tdrv->tx++;\n+\t\t\tbreak;\n+\t\tcase 16:\n+\t\t\ttx16 = (u16 *) drv->tx;\n+\t\t\tdata = *tx16;\n+\t\t\tdrv->tx_todo -= 2;\n+\t\t\tdrv->tx += 2;\n+\t\t\tbreak;\n+\t\tcase 32:\n+\t\t\ttx32 = (u32 *) drv->tx;\n+\t\t\tdata = *tx32;\n+\t\t\tdrv->tx_todo -= 4;\n+\t\t\tdrv->tx += 4;\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\treturn;\n+\t\t}\n+\n+\t\tltq_writel(&drv->regs->tb, data);\n+\t\ttx_free--;\n+\t}\n+}\n+\n+static void rx_fifo_read_full_duplex(struct ltq_spi_drv_data *drv)\n+{\n+\tu8 *rx8;\n+\tu16 *rx16;\n+\tu32 *rx32;\n+\tu32 data;\n+\tunsigned int rx_fill = rx_fifo_level(drv);\n+\n+\twhile (rx_fill) {\n+\t\tdata = ltq_readl(&drv->regs->rb);\n+\n+\t\tswitch (drv->bits_per_word) {\n+\t\tcase 8:\n+\t\t\trx8 = drv->rx;\n+\t\t\t*rx8 = data;\n+\t\t\tdrv->rx_todo--;\n+\t\t\tdrv->rx++;\n+\t\t\tbreak;\n+\t\tcase 16:\n+\t\t\trx16 = (u16 *) drv->rx;\n+\t\t\t*rx16 = data;\n+\t\t\tdrv->rx_todo -= 2;\n+\t\t\tdrv->rx += 2;\n+\t\t\tbreak;\n+\t\tcase 32:\n+\t\t\trx32 = (u32 *) drv->rx;\n+\t\t\t*rx32 = data;\n+\t\t\tdrv->rx_todo -= 4;\n+\t\t\tdrv->rx += 4;\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\treturn;\n+\t\t}\n+\n+\t\trx_fill--;\n+\t}\n+}\n+\n+static void rx_fifo_read_half_duplex(struct ltq_spi_drv_data *drv)\n+{\n+\tu32 data, *rx32;\n+\tu8 *rx8;\n+\tunsigned int rxbv, shift;\n+\tunsigned int rx_fill = rx_fifo_level(drv);\n+\n+\t/*\n+\t * In RX-only mode the bits per word value is ignored by HW. A value\n+\t * of 32 is used instead. Thus all 4 bytes per FIFO must be read.\n+\t * If remaining RX bytes are less than 4, the FIFO must be read\n+\t * differently. The amount of received and valid bytes is indicated\n+\t * by STAT.RXBV register value.\n+\t */\n+\twhile (rx_fill) {\n+\t\tif (drv->rx_todo < 4) {\n+\t\t\trxbv = (ltq_readl(&drv->regs->stat) &\n+\t\t\t\tLTQ_SPI_STAT_RXBV_MASK) >>\n+\t\t\t\tLTQ_SPI_STAT_RXBV_SHIFT;\n+\t\t\tdata = ltq_readl(&drv->regs->rb);\n+\n+\t\t\tshift = (rxbv - 1) * 8;\n+\t\t\trx8 = drv->rx;\n+\n+\t\t\twhile (rxbv) {\n+\t\t\t\t*rx8++ = (data >> shift) & 0xFF;\n+\t\t\t\trxbv--;\n+\t\t\t\tshift -= 8;\n+\t\t\t\tdrv->rx_todo--;\n+\t\t\t\tdrv->rx++;\n+\n+\t\t\t\tif (drv->rx_req)\n+\t\t\t\t\tdrv->rx_req --;\n+\t\t\t}\n+\t\t} else {\n+\t\t\tdata = ltq_readl(&drv->regs->rb);\n+\t\t\trx32 = (u32 *) drv->rx;\n+\n+\t\t\t*rx32++ = data;\n+\t\t\tdrv->rx_todo -= 4;\n+\t\t\tdrv->rx += 4;\n+\n+\t\t\tif (drv->rx_req >= 4)\n+\t\t\t\tdrv->rx_req -= 4;\n+\t\t}\n+\t\trx_fill--;\n+\t}\n+}\n+\n+static void rx_request(struct ltq_spi_drv_data *drv)\n+{\n+\tunsigned int rxreq, rxreq_max;\n+\n+\tif (drv->rx_req)\n+\t\treturn;\n+\n+\t/*\n+\t * To avoid receive overflows at high clocks it is better to request\n+\t * only the amount of bytes that fits into all FIFOs. This value\n+\t * depends on the FIFO size implemented in hardware.\n+\t */\n+\trxreq = drv->rx_todo;\n+\trxreq_max = rx_fifo_size(drv) * 4;\n+\tif (rxreq > rxreq_max)\n+\t\trxreq = rxreq_max;\n+\n+\tdrv->rx_req = rxreq;\n+\tltq_writel(&drv->regs->rxreq, rxreq);\n+}\n+\n+void spi_init(void)\n+{\n+}\n+\n+struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,\n+\t\t\t\t  unsigned int max_hz, unsigned int mode)\n+{\n+\tstruct ltq_spi_drv_data *drv;\n+\n+\tif (!spi_cs_is_valid(bus, cs))\n+\t\treturn NULL;\n+\n+\tdrv = ltq_spi_slave_alloc(bus, cs);\n+\tif (!drv)\n+\t\treturn NULL;\n+\n+\tdrv->regs = (struct ltq_spi_regs *) CKSEG1ADDR(LTQ_SPI_BASE);\n+\n+\thw_init(drv);\n+\n+\tdrv->max_hz = max_hz;\n+\tdrv->mode = mode;\n+\n+\treturn &drv->slave;\n+}\n+\n+void spi_free_slave(struct spi_slave *slave)\n+{\n+\tltq_spi_slave_free(slave);\n+}\n+\n+static int ltq_spi_wait_ready(struct ltq_spi_drv_data *drv)\n+{\n+\tconst unsigned long timeout = 20000;\n+\tunsigned long timebase;\n+\n+\ttimebase = get_timer(0);\n+\n+\tdo {\n+\t\tWATCHDOG_RESET();\n+\n+\t\tif (!hw_is_busy(drv))\n+\t\t\treturn 0;\n+\t} while (get_timer(timebase) < timeout);\n+\n+\treturn 1;\n+}\n+\n+int spi_claim_bus(struct spi_slave *slave)\n+{\n+\tstruct ltq_spi_drv_data *drv = to_ltq_spi_slave(slave);\n+\tint ret;\n+\n+\tret = ltq_spi_wait_ready(drv);\n+\tif (ret) {\n+\t\tdebug(\"cannot claim bus\\n\");\n+\t\treturn ret;\n+\t}\n+\n+\thw_enter_config_mode(drv);\n+\thw_setup_clock_mode(drv, drv->mode);\n+\thw_setup_speed_hz(drv, drv->max_hz);\n+\thw_setup_bits_per_word(drv, drv->bits_per_word);\n+\thw_enter_active_mode(drv);\n+\n+\treturn 0;\n+}\n+\n+void spi_release_bus(struct spi_slave *slave)\n+{\n+\tstruct ltq_spi_drv_data *drv = to_ltq_spi_slave(slave);\n+\n+\thw_enter_config_mode(drv);\n+}\n+\n+int spi_xfer(struct spi_slave *slave, unsigned int bitlen,\n+\t\tconst void *dout, void *din, unsigned long flags)\n+{\n+\n+\tstruct ltq_spi_drv_data *drv = to_ltq_spi_slave(slave);\n+\tint ret = 0;\n+\n+\tif (bitlen % 8)\n+\t\treturn 1;\n+\n+\tif (!bitlen) {\n+\t\tret = 0;\n+\t\tgoto done;\n+\t}\n+\n+\tif (flags & SPI_XFER_BEGIN)\n+\t\tspi_cs_activate(slave);\n+\n+\tdrv->tx = dout;\n+\tdrv->tx_todo = 0;\n+\tdrv->rx = din;\n+\tdrv->rx_todo = 0;\n+\thw_set_rxtx(drv);\n+\n+\tif (drv->tx) {\n+\t\tdrv->tx_todo = bitlen / 8;\n+\n+\t\ttx_fifo_write(drv);\n+\t}\n+\n+\tif (drv->rx) {\n+\t\tdrv->rx_todo = bitlen / 8;\n+\n+\t\tif (!drv->tx)\n+\t\t\trx_request(drv);\n+\t}\n+\n+\tfor (;;) {\n+\t\tif (drv->tx) {\n+\t\t\tif (drv->rx && drv->rx_todo)\n+\t\t\t\trx_fifo_read_full_duplex(drv);\n+\n+\t\t\tif (drv->tx_todo)\n+\t\t\t\ttx_fifo_write(drv);\n+\t\t\telse\n+\t\t\t\tgoto done;\n+\t\t} else if (drv->rx) {\n+\t\t\tif (drv->rx_todo) {\n+\t\t\t\trx_fifo_read_half_duplex(drv);\n+\n+\t\t\t\tif (drv->rx_todo)\n+\t\t\t\t\trx_request(drv);\n+\t\t\t\telse\n+\t\t\t\t\tgoto done;\n+\t\t\t} else {\n+\t\t\t\tgoto done;\n+\t\t\t}\n+\t\t}\n+\t}\n+\n+done:\n+\tret = ltq_spi_wait_ready(drv);\n+\n+\tdrv->rx = NULL;\n+\tdrv->tx = NULL;\n+\thw_set_rxtx(drv);\n+\n+\tif (flags & SPI_XFER_END)\n+\t\tspi_cs_deactivate(slave);\n+\n+\treturn ret;\n+}\n--- a/include/phy.h\n+++ b/include/phy.h\n@@ -214,6 +214,7 @@ int phy_atheros_init(void);\n int phy_broadcom_init(void);\n int phy_davicom_init(void);\n int phy_et1011c_init(void);\n+int phy_lantiq_init(void);\n int phy_lxt_init(void);\n int phy_marvell_init(void);\n int phy_micrel_init(void);\n--- a/spl/Makefile\n+++ b/spl/Makefile\n@@ -100,6 +100,8 @@ LIBS-$(CONFIG_SPL_USBETH_SUPPORT) += dri\n LIBS-$(CONFIG_SPL_MUSB_NEW_SUPPORT) += drivers/usb/musb-new/libusb_musb-new.o\n LIBS-$(CONFIG_SPL_USBETH_SUPPORT) += drivers/usb/gadget/libusb_gadget.o\n LIBS-$(CONFIG_SPL_WATCHDOG_SUPPORT) += drivers/watchdog/libwatchdog.o\n+LIBS-$(CONFIG_SPL_LZMA_SUPPORT) += lib/lzma/liblzma.o\n+LIBS-$(CONFIG_SPL_LZO_SUPPORT) += lib/lzo/liblzo.o\n \n ifneq ($(CONFIG_OMAP_COMMON),)\n LIBS-y += $(CPUDIR)/omap-common/libomap-common.o\n--- a/tools/.gitignore\n+++ b/tools/.gitignore\n@@ -2,6 +2,7 @@\n /envcrc\n /gen_eth_addr\n /img2srec\n+/ltq-boot-image\n /kwboot\n /mkenvimage\n /mkimage\n--- a/tools/Makefile\n+++ b/tools/Makefile\n@@ -49,6 +49,7 @@ BIN_FILES-$(CONFIG_VIDEO_LOGO) += bmp_lo\n BIN_FILES-$(CONFIG_BUILD_ENVCRC) += envcrc$(SFX)\n BIN_FILES-$(CONFIG_CMD_NET) += gen_eth_addr$(SFX)\n BIN_FILES-$(CONFIG_CMD_LOADS) += img2srec$(SFX)\n+BIN_FILES-$(CONFIG_SOC_LANTIQ) += ltq-boot-image$(SFX)\n BIN_FILES-$(CONFIG_XWAY_SWAP_BYTES) += xway-swap-bytes$(SFX)\n BIN_FILES-y += mkenvimage$(SFX)\n BIN_FILES-y += mkimage$(SFX)\n@@ -95,6 +96,7 @@ OBJ_FILES-$(CONFIG_MX28) += mxsboot.o\n OBJ_FILES-$(CONFIG_NETCONSOLE) += ncb.o\n OBJ_FILES-$(CONFIG_SHA1_CHECK_UB_IMG) += ubsha1.o\n OBJ_FILES-$(CONFIG_SMDK5250) += mkexynosspl.o\n+OBJ_FILES-$(CONFIG_SOC_LANTIQ) += ltq-boot-image.o\n OBJ_FILES-$(CONFIG_VIDEO_LOGO) += bmp_logo.o\n OBJ_FILES-$(CONFIG_XWAY_SWAP_BYTES) += xway-swap-bytes.o\n \n@@ -195,6 +197,10 @@ $(obj)img2srec$(SFX):\t$(obj)img2srec.o\n \t$(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^\n \t$(HOSTSTRIP) $@\n \n+$(obj)ltq-boot-image$(SFX):\t$(obj)ltq-boot-image.o\n+\t$(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^\n+\t$(HOSTSTRIP) $@\n+\n $(obj)xway-swap-bytes$(SFX):\t$(obj)xway-swap-bytes.o\n \t$(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^\n \t$(HOSTSTRIP) $@\n--- /dev/null\n+++ b/tools/ltq-boot-image.c\n@@ -0,0 +1,315 @@\n+/*\n+ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#include <stdio.h>\n+#include <stdlib.h>\n+#include <string.h>\n+#include <unistd.h>\n+#include <getopt.h>\n+#include <compiler.h>\n+#include <sys/stat.h>\n+\n+enum image_types {\n+\tIMAGE_NONE,\n+\tIMAGE_SFSPL\n+};\n+\n+/* Lantiq non-volatile bootstrap command IDs */\n+enum nvb_cmd_ids {\n+\tNVB_CMD_DEBUG\t= 0x11,\n+\tNVB_CMD_REGCFG\t= 0x22,\n+\tNVB_CMD_IDWNLD\t= 0x33,\n+\tNVB_CMD_CDWNLD\t= 0x44,\n+\tNVB_CMD_DWNLD\t= 0x55,\n+\tNVB_CMD_IFCFG\t= 0x66,\n+\tNVB_CMD_START\t= 0x77\n+};\n+\n+/* Lantiq non-volatile bootstrap command flags */\n+enum nvb_cmd_flags {\n+\tNVB_FLAG_START\t= 1,\n+\tNVB_FLAG_DEC\t= (1 << 1),\n+\tNVB_FLAG_DBG\t= (1 << 2),\n+\tNVB_FLAG_SDBG\t= (1 << 3),\n+\tNVB_FLAG_CFG0\t= (1 << 4),\n+\tNVB_FLAG_CFG1\t= (1 << 5),\n+\tNVB_FLAG_CFG2\t= (1 << 6),\n+\tNVB_FLAG_RST\t= (1 << 7)\n+};\n+\n+struct args {\n+\tenum image_types type;\n+\t__u32\t\tentry_addr;\n+\tconst char\t*uboot_bin;\n+\tconst char\t*spl_bin;\n+\tconst char\t*out_bin;\n+};\n+\n+static void usage_msg(const char *name)\n+{\n+\tfprintf(stderr, \"%s: [-h] -t type -e entry-addr -u uboot-bin [-s spl-bin] -o out-bin\\n\",\n+\t\tname);\n+\tfprintf(stderr, \" Image types:\\n\"\n+\t\t\t\"  sfspl  - SPL + [compressed] U-Boot for SPI flash\\n\");\n+}\n+\n+static enum image_types parse_image_type(const char *type)\n+{\n+\tif (!type)\n+\t\treturn IMAGE_NONE;\n+\n+\tif (!strncmp(type, \"sfspl\", 6))\n+\t\treturn IMAGE_SFSPL;\n+\n+\treturn IMAGE_NONE;\n+}\n+\n+static int parse_args(int argc, char *argv[], struct args *arg)\n+{\n+\tint opt;\n+\n+\tmemset(arg, 0, sizeof(*arg));\n+\n+\twhile ((opt = getopt(argc, argv, \"ht:e:u:s:o:\")) != -1) {\n+\t\tswitch (opt) {\n+\t\tcase 'h':\n+\t\t\tusage_msg(argv[0]);\n+\t\t\treturn 1;\n+\t\tcase 't':\n+\t\t\targ->type = parse_image_type(optarg);\n+\t\t\tbreak;\n+\t\tcase 'e':\n+\t\t\targ->entry_addr = strtoul(optarg, NULL, 16);\n+\t\t\tbreak;\n+\t\tcase 'u':\n+\t\t\targ->uboot_bin = optarg;\n+\t\t\tbreak;\n+\t\tcase 's':\n+\t\t\targ->spl_bin = optarg;\n+\t\t\tbreak;\n+\t\tcase 'o':\n+\t\t\targ->out_bin = optarg;\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tfprintf(stderr, \"Invalid option -%c\\n\", opt);\n+\t\t\tgoto parse_error;\n+\t\t}\n+\t}\n+\n+\tif (arg->type == IMAGE_NONE) {\n+\t\tfprintf(stderr, \"Invalid image type\\n\");\n+\t\tgoto parse_error;\n+\t}\n+\n+\tif (!arg->uboot_bin) {\n+\t\tfprintf(stderr, \"Missing U-Boot binary\\n\");\n+\t\tgoto parse_error;\n+\t}\n+\n+\tif (!arg->out_bin) {\n+\t\tfprintf(stderr, \"Missing output binary\\n\");\n+\t\tgoto parse_error;\n+\t}\n+\n+\tif (arg->type == IMAGE_SFSPL && !arg->spl_bin) {\n+\t\tfprintf(stderr, \"Missing SPL binary\\n\");\n+\t\tgoto parse_error;\n+\t}\n+\n+\treturn 0;\n+\n+parse_error:\n+\tusage_msg(argv[0]);\n+\treturn -1;\n+}\n+\n+static __u32 build_nvb_command(unsigned cmdid, unsigned cmdflags)\n+{\n+\t__u32 cmd;\n+\t__u16 tag;\n+\n+\ttag = (cmdid << 8) | cmdflags;\n+\tcmd = (tag << 16) | (0xFFFF - tag);\n+\n+\treturn cpu_to_be32(cmd);\n+}\n+\n+static int write_header(int fd, const void *hdr, size_t size)\n+{\n+\tssize_t n;\n+\n+\tn = write(fd, hdr, size);\n+\tif (n != size) {\n+\t\tfprintf(stderr, \"Cannot write header: %s\\n\",\n+\t\t\tstrerror(errno));\n+\t\treturn -1;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int write_nvb_dwnld_header(int fd, size_t size, __u32 addr)\n+{\n+\t__u32 hdr[3];\n+\n+\thdr[0] = build_nvb_command(NVB_CMD_DWNLD, NVB_FLAG_START |\n+\t\t\t\t\tNVB_FLAG_SDBG);\n+\thdr[1] = cpu_to_be32(size + 4);\n+\thdr[2] = cpu_to_be32(addr);\n+\n+\treturn write_header(fd, hdr, sizeof(hdr));\n+}\n+\n+static int write_nvb_start_header(int fd, __u32 addr)\n+{\n+\t__u32 hdr[3];\n+\n+\thdr[0] = build_nvb_command(NVB_CMD_START, NVB_FLAG_SDBG);\n+\thdr[1] = cpu_to_be32(4);\n+\thdr[2] = cpu_to_be32(addr);\n+\n+\treturn write_header(fd, hdr, sizeof(hdr));\n+}\n+\n+static int open_input_bin(const char *name, void **ptr, size_t *size)\n+{\n+\tstruct stat sbuf;\n+\tint ret, fd;\n+\n+\tfd = open(name, O_RDONLY | O_BINARY);\n+\tif (0 > fd) {\n+\t\tfprintf(stderr, \"Cannot open %s: %s\\n\", name,\n+\t\t\tstrerror(errno));\n+\t\treturn -1;\n+\t}\n+\n+\tret = fstat(fd, &sbuf);\n+\tif (0 > ret) {\n+\t\tfprintf(stderr, \"Cannot fstat %s: %s\\n\", name,\n+\t\t\tstrerror(errno));\n+\t\treturn -1;\n+\t}\n+\n+\t*ptr = mmap(0, sbuf.st_size, PROT_READ, MAP_SHARED, fd, 0);\n+\tif (*ptr == MAP_FAILED) {\n+\t\tfprintf(stderr, \"Cannot mmap %s: %s\\n\", name,\n+\t\t\tstrerror(errno));\n+\t\treturn -1;\n+\t}\n+\n+\t*size = sbuf.st_size;\n+\n+\treturn fd;\n+}\n+\n+static void close_input_bin(int fd, void *ptr, size_t size)\n+{\n+\tmunmap(ptr, size);\n+\tclose(fd);\n+}\n+\n+static int copy_bin(int fd, void *ptr, size_t size)\n+{\n+\tssize_t n;\n+\n+\tn = write(fd, ptr, size);\n+\tif (n != size) {\n+\t\tfprintf(stderr, \"Cannot copy binary: %s\\n\", strerror(errno));\n+\t\treturn -1;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int open_output_bin(const char *name)\n+{\n+\tint fd;\n+\n+\tfd = open(name, O_RDWR | O_CREAT | O_TRUNC | O_BINARY, 0666);\n+\tif (0 > fd) {\n+\t\tfprintf(stderr, \"Cannot open %s: %s\\n\", name,\n+\t\t\tstrerror(errno));\n+\t\treturn -1;\n+\t}\n+\n+\treturn fd;\n+}\n+\n+static int create_sfspl(const struct args *arg)\n+{\n+\tint out_fd, uboot_fd, spl_fd, ret;\n+\tvoid *uboot_ptr, *spl_ptr;\n+\tsize_t uboot_size, spl_size;\n+\n+\tout_fd = open_output_bin(arg->out_bin);\n+\tif (0 > out_fd)\n+\t\tgoto err;\n+\n+\tspl_fd = open_input_bin(arg->spl_bin, &spl_ptr, &spl_size);\n+\tif (0 > spl_fd)\n+\t\tgoto err_spl;\n+\n+\tuboot_fd = open_input_bin(arg->uboot_bin, &uboot_ptr, &uboot_size);\n+\tif (0 > uboot_fd)\n+\t\tgoto err_uboot;\n+\n+\tret = write_nvb_dwnld_header(out_fd, spl_size, arg->entry_addr);\n+\tif (ret)\n+\t\tgoto err_write;\n+\n+\tret = copy_bin(out_fd, spl_ptr, spl_size);\n+\tif (ret)\n+\t\tgoto err_write;\n+\n+\tret = write_nvb_start_header(out_fd, arg->entry_addr);\n+\tif (ret)\n+\t\tgoto err_write;\n+\n+\tret = copy_bin(out_fd, uboot_ptr, uboot_size);\n+\tif (ret)\n+\t\tgoto err_write;\n+\n+\tclose_input_bin(uboot_fd, uboot_ptr, uboot_size);\n+\tclose_input_bin(spl_fd, spl_ptr, spl_size);\n+\tclose(out_fd);\n+\n+\treturn 0;\n+\n+err_write:\n+\tclose_input_bin(uboot_fd, uboot_ptr, uboot_size);\n+err_uboot:\n+\tclose_input_bin(spl_fd, spl_ptr, spl_size);\n+err_spl:\n+\tclose(out_fd);\n+err:\n+\treturn -1;\n+}\n+\n+int main(int argc, char *argv[])\n+{\n+\tint ret;\n+\tstruct args arg;\n+\n+\tret = parse_args(argc, argv, &arg);\n+\tif (ret)\n+\t\tgoto done;\n+\n+\tswitch (arg.type) {\n+\tcase IMAGE_SFSPL:\n+\t\tret = create_sfspl(&arg);\n+\t\tbreak;\n+\tdefault:\n+\t\tfprintf(stderr, \"Image type not implemented\\n\");\n+\t\tret = -1;\n+\t\tbreak;\n+\t}\n+\n+done:\n+\tif (ret >= 0)\n+\t\treturn EXIT_SUCCESS;\n+\n+\treturn EXIT_FAILURE;\n+}\n"
  },
  {
    "path": "package/boot/uboot-lantiq/patches/0015-MIPS-lantiq-add-support-for-Lantiq-XWAY-ARX100-SoC-f.patch",
    "content": "From 4953294aa8f8b9023e6b5f7f39059706c72d916c Mon Sep 17 00:00:00 2001\nFrom: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>\nDate: Sun, 9 Dec 2012 17:54:56 +0100\nSubject: MIPS: lantiq: add support for Lantiq XWAY ARX100 SoC family\n\nSigned-off-by: Luka Perkov <luka@openwrt.org>\nSigned-off-by: John Crispin <blogic@openwrt.org>\nSigned-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>\n\n--- /dev/null\n+++ b/arch/mips/cpu/mips32/arx100/Makefile\n@@ -0,0 +1,31 @@\n+#\n+# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de\n+#\n+# SPDX-License-Identifier:\tGPL-2.0+\n+#\n+\n+include $(TOPDIR)/config.mk\n+\n+LIB\t= $(obj)lib$(SOC).o\n+\n+COBJS-y\t+= cgu.o chipid.o ebu.o mem.o pmu.o rcu.o\n+SOBJS-y\t+= cgu_init.o mem_init.o\n+\n+COBJS\t:= $(COBJS-y)\n+SOBJS\t:= $(SOBJS-y)\n+SRCS\t:= $(SOBJS:.o=.S) $(COBJS:.o=.c)\n+OBJS\t:= $(addprefix $(obj),$(SOBJS) $(COBJS))\n+\n+all:\t$(LIB)\n+\n+$(LIB):\t$(obj).depend $(OBJS)\n+\t$(call cmd_link_o_target, $(OBJS))\n+\n+#########################################################################\n+\n+# defines $(obj).depend target\n+include $(SRCTREE)/rules.mk\n+\n+sinclude $(obj).depend\n+\n+#########################################################################\n--- /dev/null\n+++ b/arch/mips/cpu/mips32/arx100/cgu.c\n@@ -0,0 +1,109 @@\n+/*\n+ * Copyright (C) 2007-2010 Lantiq Deutschland GmbH\n+ * Copyright (C) 2012 Daniel Schwierzeck, daniel.schwierzeck@gmail.com\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#include <common.h>\n+#include <asm/arch/soc.h>\n+#include <asm/lantiq/clk.h>\n+#include <asm/lantiq/io.h>\n+\n+#define CGU_SYS_DDR_SEL\t\t(1 << 0)\n+#define CGU_SYS_CPU_SEL\t\t(1 << 2)\n+#define CGU_SYS_SYS_SHIFT\t3\n+#define CGU_SYS_SYS_MASK\t(0x3 << CGU_SYS_SYS_SHIFT)\n+#define CGU_SYS_FPI_SEL\t\t(1 << 6)\n+#define CGU_SYS_PPE_SEL\t\t(1 << 7)\n+\n+struct ltq_cgu_regs {\n+\tu32\trsvd0;\n+\t__be32\tpll0_cfg;\t/* PLL0 config */\n+\t__be32\tpll1_cfg;\t/* PLL1 config */\n+\tu32\trsvd2;\n+\t__be32\tsys;\t\t/* System clock */\n+\t__be32\tupdate;\t\t/* CGU update control */\n+\t__be32\tif_clk;\t\t/* Interface clock */\n+\tu32\trsvd3;\n+\t__be32\tsmd;\t\t/* SDRAM Memory Control */\n+\tu32\trsvd4;\n+\t__be32\tct1_sr;\t\t/* CT status 1 */\n+\t__be32\tct_kval;\t/* CT K value */\n+\t__be32\tpcm_cr;\t\t/* PCM control */\n+};\n+\n+static struct ltq_cgu_regs *ltq_cgu_regs =\n+\t(struct ltq_cgu_regs *) CKSEG1ADDR(LTQ_CGU_BASE);\n+\n+static inline u32 ltq_cgu_sys_readl(u32 mask, u32 shift)\n+{\n+\treturn (ltq_readl(&ltq_cgu_regs->sys) & mask) >> shift;\n+}\n+\n+static unsigned long ltq_get_system_clock(void)\n+{\n+\tu32 sys_sel;\n+\tunsigned long clk;\n+\n+\tsys_sel = ltq_cgu_sys_readl(CGU_SYS_SYS_MASK, CGU_SYS_SYS_SHIFT);\n+\n+\tswitch (sys_sel) {\n+\tcase 0:\n+\t\tclk = CLOCK_333_MHZ;\n+\t\tbreak;\n+\tcase 2:\n+\t\tclk = CLOCK_393_MHZ;\n+\t\tbreak;\n+\tdefault:\n+\t\tclk = 0;\n+\t\tbreak;\n+\t}\n+\n+\treturn clk;\n+}\n+\n+unsigned long ltq_get_io_region_clock(void)\n+{\n+\tu32 ddr_sel;\n+\tunsigned long clk;\n+\n+\tddr_sel = ltq_cgu_sys_readl(1, CGU_SYS_DDR_SEL);\n+\n+\tif (ddr_sel)\n+\t\tclk = ltq_get_system_clock() / 3;\n+\telse\n+\t\tclk = ltq_get_system_clock() / 2;\n+\n+\treturn clk;\n+}\n+\n+unsigned long ltq_get_cpu_clock(void)\n+{\n+\tu32 cpu_sel;\n+\tunsigned long clk;\n+\n+\tcpu_sel = ltq_cgu_sys_readl(1, CGU_SYS_CPU_SEL);\n+\n+\tif (cpu_sel)\n+\t\tclk = ltq_get_io_region_clock();\n+\telse\n+\t\tclk = ltq_get_system_clock();\n+\n+\treturn clk;\n+}\n+\n+unsigned long ltq_get_bus_clock(void)\n+{\n+\tu32 fpi_sel;\n+\tunsigned long clk;\n+\n+\tfpi_sel = ltq_cgu_sys_readl(1, CGU_SYS_FPI_SEL);\n+\n+\tif (fpi_sel)\n+\t\tclk = ltq_get_io_region_clock() / 2;\n+\telse\n+\t\tclk = ltq_get_io_region_clock();\n+\n+\treturn clk;\n+}\n--- /dev/null\n+++ b/arch/mips/cpu/mips32/arx100/cgu_init.S\n@@ -0,0 +1,105 @@\n+/*\n+ * Copyright (C) 2007-2010 Lantiq Deutschland GmbH\n+ * Copyright (C) 2012-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#include <config.h>\n+#include <asm/asm.h>\n+#include <asm/regdef.h>\n+#include <asm/addrspace.h>\n+#include <asm/arch/soc.h>\n+\n+/* CGU module register */\n+#define CGU_PLL0_CFG\t\t\t0x0004\t/* PLL0 config */\n+#define CGU_PLL1_CFG\t\t\t0x0008\t/* PLL1 config */\n+#define CGU_SYS\t\t\t\t0x0010\t/* System clock */\n+#define CGU_UPDATE\t\t\t0x0014\t/* Clock update control */\n+\n+/* Valid SYS.PPE_SEL values */\n+#define CGU_SYS_PPESEL_SHIFT\t\t7\n+#define CGU_SYS_PPESEL_250_MHZ\t\t(0x1 << CGU_SYS_PPESEL_SHIFT)\n+\n+/* Valid SYS.SYS_SEL values */\n+#define CGU_SYS_SYSSEL_SHIFT\t\t3\n+#define CGU_SYS_SYSSEL_PLL0_333_MHZ\t(0x0 << CGU_SYS_SYSSEL_SHIFT)\n+#define CGU_SYS_SYSSEL_PLL1_393_MHZ\t(0x2 << CGU_SYS_SYSSEL_SHIFT)\n+\n+/* Valid SYS.CPU_SEL values */\n+#define CGU_SYS_CPUSEL_SHIFT\t\t2\n+#define CGU_SYS_CPUSEL_EQUAL_SYSCLK\t(0x0 << CGU_SYS_CPUSEL_SHIFT)\n+#define CGU_SYS_CPUSEL_EQUAL_DDRCLK\t(0x1 << CGU_SYS_CPUSEL_SHIFT)\n+\n+/* Valid SYS.DDR_SEL values */\n+#define CGU_SYS_DDRSEL_HALF_SYSCLK\t0x0\n+#define CGU_SYS_DDRSEL_THIRD_SYSCLK\t0x1\n+\n+#define CGU_UPDATE_UPD\t\t\t0x1\n+\n+#if (CONFIG_SYS_CLOCK_MODE == LTQ_CLK_CPU_393_DDR_197)\n+#define CGU_SYS_PPESEL_CONFIG\t\tCGU_SYS_PPESEL_250_MHZ\n+#define CGU_SYS_SYSSEL_CONFIG\t\tCGU_SYS_SYSSEL_PLL1_393_MHZ\n+#define CGU_SYS_CPUSEL_CONFIG\t\tCGU_SYS_CPUSEL_EQUAL_SYSCLK\n+#define CGU_SYS_DDRSEL_CONFIG\t\tCGU_SYS_DDRSEL_HALF_SYSCLK\n+#elif (CONFIG_SYS_CLOCK_MODE == LTQ_CLK_CPU_197_DDR_197)\n+#define CGU_SYS_PPESEL_CONFIG\t\tCGU_SYS_PPESEL_250_MHZ\n+#define CGU_SYS_SYSSEL_CONFIG\t\tCGU_SYS_SYSSEL_PLL1_393_MHZ\n+#define CGU_SYS_CPUSEL_CONFIG\t\tCGU_SYS_CPUSEL_EQUAL_DDRCLK\n+#define CGU_SYS_DDRSEL_CONFIG\t\tCGU_SYS_DDRSEL_HALF_SYSCLK\n+#elif (CONFIG_SYS_CLOCK_MODE == LTQ_CLK_CPU_333_DDR_167)\n+#define CGU_SYS_PPESEL_CONFIG\t\tCGU_SYS_PPESEL_250_MHZ\n+#define CGU_SYS_SYSSEL_CONFIG\t\tCGU_SYS_SYSSEL_PLL0_333_MHZ\n+#define CGU_SYS_CPUSEL_CONFIG\t\tCGU_SYS_CPUSEL_EQUAL_SYSCLK\n+#define CGU_SYS_DDRSEL_CONFIG\t\tCGU_SYS_DDRSEL_HALF_SYSCLK\n+#elif (CONFIG_SYS_CLOCK_MODE == LTQ_CLK_CPU_167_DDR_167)\n+#define CGU_SYS_PPESEL_CONFIG\t\tCGU_SYS_PPESEL_250_MHZ\n+#define CGU_SYS_SYSSEL_CONFIG\t\tCGU_SYS_SYSSEL_PLL0_333_MHZ\n+#define CGU_SYS_CPUSEL_CONFIG\t\tCGU_SYS_CPUSEL_EQUAL_DDRCLK\n+#define CGU_SYS_DDRSEL_CONFIG\t\tCGU_SYS_DDRSEL_HALF_SYSCLK\n+#elif (CONFIG_SYS_CLOCK_MODE == LTQ_CLK_CPU_131_DDR_131)\n+#define CGU_SYS_PPESEL_CONFIG\t\tCGU_SYS_PPESEL_250_MHZ\n+#define CGU_SYS_SYSSEL_CONFIG\t\tCGU_SYS_SYSSEL_PLL1_393_MHZ\n+#define CGU_SYS_CPUSEL_CONFIG\t\tCGU_SYS_CPUSEL_EQUAL_DDRCLK\n+#define CGU_SYS_DDRSEL_CONFIG\t\tCGU_SYS_DDRSEL_THIRD_SYSCLK\n+#elif (CONFIG_SYS_CLOCK_MODE == LTQ_CLK_CPU_111_DDR_111)\n+#define CGU_SYS_PPESEL_CONFIG\t\tCGU_SYS_PPESEL_250_MHZ\n+#define CGU_SYS_SYSSEL_CONFIG\t\tCGU_SYS_SYSSEL_PLL0_333_MHZ\n+#define CGU_SYS_CPUSEL_CONFIG\t\tCGU_SYS_CPUSEL_EQUAL_DDRCLK\n+#define CGU_SYS_DDRSEL_CONFIG\t\tCGU_SYS_DDRSEL_THIRD_SYSCLK\n+#else\n+#error \"Invalid system clock configuration!\"\n+#endif\n+\n+/* Build register values */\n+#define CGU_SYS_VALUE\t\t(CGU_SYS_PPESEL_CONFIG | \\\n+\t\t\t\tCGU_SYS_SYSSEL_CONFIG | \\\n+\t\t\t\tCGU_SYS_CPUSEL_CONFIG | \\\n+\t\t\t\tCGU_SYS_DDRSEL_CONFIG)\n+\n+\t.set noreorder\n+\n+LEAF(ltq_cgu_init)\n+\t/* Load current CGU register value */\n+\tli\tt0, (LTQ_CGU_BASE | KSEG1)\n+\tlw\tt1, CGU_SYS(t0)\n+\n+\t/* Load target CGU register values */\n+\tli\tt2, CGU_SYS_VALUE\n+\n+\t/* Only update registers if values differ */\n+\tbeq\tt1, t2, finished\n+\t nop\n+\n+\t/* Store target register values */\n+\tsw\tt2, CGU_SYS(t0)\n+\n+\t/* Trigger CGU update */\n+\tli\tt1, CGU_UPDATE_UPD\n+\tsw\tt1, CGU_UPDATE(t0)\n+\n+finished:\n+\tjr\tra\n+\t nop\n+\n+\tEND(ltq_cgu_init)\n--- /dev/null\n+++ b/arch/mips/cpu/mips32/arx100/chipid.c\n@@ -0,0 +1,60 @@\n+/*\n+ * Copyright (C) 2012 Daniel Schwierzeck, daniel.schwierzeck@gmail.com\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#include <common.h>\n+#include <asm/lantiq/io.h>\n+#include <asm/lantiq/chipid.h>\n+#include <asm/arch/soc.h>\n+\n+#define LTQ_CHIPID_VERSION_SHIFT\t28\n+#define LTQ_CHIPID_VERSION_MASK\t\t(0xF << LTQ_CHIPID_VERSION_SHIFT)\n+#define LTQ_CHIPID_PNUM_SHIFT\t\t12\n+#define LTQ_CHIPID_PNUM_MASK\t\t(0xFFFF << LTQ_CHIPID_PNUM_SHIFT)\n+\n+struct ltq_chipid_regs {\n+\tu32\tmanid;\t\t/* Manufacturer identification */\n+\tu32\tchipid;\t\t/* Chip identification */\n+};\n+\n+static struct ltq_chipid_regs *ltq_chipid_regs =\n+\t(struct ltq_chipid_regs *) CKSEG1ADDR(LTQ_CHIPID_BASE);\n+\n+unsigned int ltq_chip_version_get(void)\n+{\n+\tu32 chipid;\n+\n+\tchipid = ltq_readl(&ltq_chipid_regs->chipid);\n+\n+\treturn (chipid & LTQ_CHIPID_VERSION_MASK) >> LTQ_CHIPID_VERSION_SHIFT;\n+}\n+\n+unsigned int ltq_chip_partnum_get(void)\n+{\n+\tu32 chipid;\n+\n+\tchipid = ltq_readl(&ltq_chipid_regs->chipid);\n+\n+\treturn (chipid & LTQ_CHIPID_PNUM_MASK) >> LTQ_CHIPID_PNUM_SHIFT;\n+}\n+\n+const char *ltq_chip_partnum_str(void)\n+{\n+\tenum ltq_chip_partnum partnum = ltq_chip_partnum_get();\n+\n+\tswitch (partnum) {\n+\tcase LTQ_SOC_ARX188:\n+\t\treturn \"ARX188\";\n+\tcase LTQ_SOC_ARX186:\n+\tcase LTQ_SOC_ARX186_2:\n+\t\treturn \"ARX186\";\n+\tcase LTQ_SOC_ARX182:\n+\t\treturn \"ARX182\";\n+\tdefault:\n+\t\tprintf(\"Unknown partnum: %x\\n\", partnum);\n+\t}\n+\n+\treturn \"\";\n+}\n--- /dev/null\n+++ b/arch/mips/cpu/mips32/arx100/config.mk\n@@ -0,0 +1,30 @@\n+#\n+# Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com\n+#\n+# SPDX-License-Identifier:\tGPL-2.0+\n+#\n+\n+PF_CPPFLAGS_XRX := $(call cc-option,-mtune=34kc,)\n+PLATFORM_CPPFLAGS += $(PF_CPPFLAGS_XRX)\n+\n+ifdef CONFIG_SPL_BUILD\n+PF_ABICALLS\t\t:= -mno-abicalls\n+PF_PIC\t\t\t:= -fno-pic\n+PF_PIE\t\t\t:=\n+USE_PRIVATE_LIBGCC\t:= yes\n+endif\n+\n+LIBS-y += $(CPUDIR)/lantiq-common/liblantiq-common.o\n+\n+ifndef CONFIG_SPL_BUILD\n+ifdef CONFIG_SYS_BOOT_SFSPL\n+ALL-y += $(obj)u-boot.ltq.sfspl\n+ALL-$(CONFIG_SPL_LZO_SUPPORT) += $(obj)u-boot.ltq.lzo.sfspl\n+ALL-$(CONFIG_SPL_LZMA_SUPPORT) += $(obj)u-boot.ltq.lzma.sfspl\n+endif\n+ifdef CONFIG_SYS_BOOT_NORSPL\n+ALL-y += $(obj)u-boot.ltq.norspl\n+ALL-$(CONFIG_SPL_LZO_SUPPORT) += $(obj)u-boot.ltq.lzo.norspl\n+ALL-$(CONFIG_SPL_LZMA_SUPPORT) += $(obj)u-boot.ltq.lzma.norspl\n+endif\n+endif\n--- /dev/null\n+++ b/arch/mips/cpu/mips32/arx100/ebu.c\n@@ -0,0 +1,111 @@\n+/*\n+ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#include <common.h>\n+#include <asm/arch/soc.h>\n+#include <asm/lantiq/io.h>\n+\n+#define EBU_ADDRSEL_MASK(mask)\t\t((mask & 0xf) << 4)\n+#define EBU_ADDRSEL_REGEN\t\t(1 << 0)\n+\n+#define EBU_CON_WRDIS\t\t\t(1 << 31)\n+#define EBU_CON_AGEN_DEMUX\t\t(0x0 << 24)\n+#define EBU_CON_AGEN_MUX\t\t(0x2 << 24)\n+#define EBU_CON_SETUP\t\t\t(1 << 22)\n+#define EBU_CON_WAIT_DIS\t\t(0x0 << 20)\n+#define EBU_CON_WAIT_ASYNC\t\t(0x1 << 20)\n+#define EBU_CON_WAIT_SYNC\t\t(0x2 << 20)\n+#define EBU_CON_WINV\t\t\t(1 << 19)\n+#define EBU_CON_PW_8BIT\t\t\t(0x0 << 16)\n+#define EBU_CON_PW_16BIT\t\t(0x1 << 16)\n+#define EBU_CON_ALEC(cycles)\t\t((cycles & 0x3) << 14)\n+#define EBU_CON_BCGEN_CS\t\t(0x0 << 12)\n+#define EBU_CON_BCGEN_INTEL\t\t(0x1 << 12)\n+#define EBU_CON_BCGEN_MOTOROLA\t\t(0x2 << 12)\n+#define EBU_CON_WAITWRC(cycles)\t\t((cycles & 0x7) << 8)\n+#define EBU_CON_WAITRDC(cycles)\t\t((cycles & 0x3) << 6)\n+#define EBU_CON_HOLDC(cycles)\t\t((cycles & 0x3) << 4)\n+#define EBU_CON_RECOVC(cycles)\t\t((cycles & 0x3) << 2)\n+#define EBU_CON_CMULT_1\t\t\t0x0\n+#define EBU_CON_CMULT_4\t\t\t0x1\n+#define EBU_CON_CMULT_8\t\t\t0x2\n+#define EBU_CON_CMULT_16\t\t0x3\n+\n+#if defined(CONFIG_LTQ_SUPPORT_NOR_FLASH)\n+#define ebu_region0_enable\t\t1\n+#else\n+#define ebu_region0_enable\t\t0\n+#endif\n+\n+#if defined(CONFIG_LTQ_SUPPORT_NAND_FLASH)\n+#define ebu_region1_enable\t\t1\n+#else\n+#define ebu_region1_enable\t\t0\n+#endif\n+\n+struct ltq_ebu_regs {\n+\tu32\tclc;\n+\tu32\trsvd0;\n+\tu32\tid;\n+\tu32\trsvd1;\n+\tu32\tcon;\n+\tu32\trsvd2[3];\n+\tu32\taddr_sel_0;\n+\tu32\taddr_sel_1;\n+\tu32\taddr_sel_2;\n+\tu32\taddr_sel_3;\n+\tu32\trsvd3[12];\n+\tu32\tcon_0;\n+\tu32\tcon_1;\n+\tu32\tcon_2;\n+\tu32\tcon_3;\n+};\n+\n+static struct ltq_ebu_regs *ltq_ebu_regs =\n+\t(struct ltq_ebu_regs *) CKSEG1ADDR(LTQ_EBU_BASE);\n+\n+void ltq_ebu_init(void)\n+{\n+\tif (ebu_region0_enable) {\n+\t\t/*\n+\t\t * Map EBU region 0 to range 0x10000000-0x13ffffff and enable\n+\t\t * region control. This supports up to 32 MiB NOR flash in\n+\t\t * bank 0.\n+\t\t */\n+\t\tltq_writel(&ltq_ebu_regs->addr_sel_0, LTQ_EBU_REGION0_BASE |\n+\t\t\tEBU_ADDRSEL_MASK(1) | EBU_ADDRSEL_REGEN);\n+\n+\t\tltq_writel(&ltq_ebu_regs->con_0, EBU_CON_AGEN_DEMUX |\n+\t\t\tEBU_CON_WAIT_DIS | EBU_CON_PW_16BIT |\n+\t\t\tEBU_CON_ALEC(3) | EBU_CON_BCGEN_INTEL |\n+\t\t\tEBU_CON_WAITWRC(7) | EBU_CON_WAITRDC(3) |\n+\t\t\tEBU_CON_HOLDC(3) | EBU_CON_RECOVC(3) |\n+\t\t\tEBU_CON_CMULT_16);\n+\t} else\n+\t\tltq_clrbits(&ltq_ebu_regs->addr_sel_0, EBU_ADDRSEL_REGEN);\n+\n+\tif (ebu_region1_enable) {\n+\t\t/*\n+\t\t * Map EBU region 1 to range 0x14000000-0x13ffffff and enable\n+\t\t * region control. This supports NAND flash in bank 1.\n+\t\t */\n+\t\tltq_writel(&ltq_ebu_regs->addr_sel_1, LTQ_EBU_REGION1_BASE |\n+\t\t\tEBU_ADDRSEL_MASK(3) | EBU_ADDRSEL_REGEN);\n+\n+\t\tltq_writel(&ltq_ebu_regs->con_1, EBU_CON_AGEN_DEMUX |\n+\t\t\tEBU_CON_SETUP | EBU_CON_WAIT_DIS | EBU_CON_PW_8BIT |\n+\t\t\tEBU_CON_ALEC(3) | EBU_CON_BCGEN_INTEL |\n+\t\t\tEBU_CON_WAITWRC(2) | EBU_CON_WAITRDC(2) |\n+\t\t\tEBU_CON_HOLDC(1) | EBU_CON_RECOVC(1) |\n+\t\t\tEBU_CON_CMULT_4);\n+\t} else\n+\t\tltq_clrbits(&ltq_ebu_regs->addr_sel_1, EBU_ADDRSEL_REGEN);\n+}\n+\n+void *flash_swap_addr(unsigned long addr)\n+{\n+\treturn (void *)(addr ^ 2);\n+}\n--- /dev/null\n+++ b/arch/mips/cpu/mips32/arx100/mem.c\n@@ -0,0 +1,30 @@\n+/*\n+ * Copyright (C) 2012 Daniel Schwierzeck, daniel.schwierzeck@gmail.com\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#include <common.h>\n+#include <asm/arch/soc.h>\n+#include <asm/lantiq/io.h>\n+\n+static void *ltq_mc_ddr_base = (void *) CKSEG1ADDR(LTQ_MC_DDR_BASE);\n+\n+static inline u32 ltq_mc_dc_read(u32 index)\n+{\n+\treturn ltq_readl(ltq_mc_ddr_base + LTQ_MC_DDR_DC_OFFSET(index));\n+}\n+\n+phys_size_t initdram(int board_type)\n+{\n+\tu32 col, row, dc04, dc19, dc20;\n+\n+\tdc04 = ltq_mc_dc_read(4);\n+\tdc19 = ltq_mc_dc_read(19);\n+\tdc20 = ltq_mc_dc_read(20);\n+\n+\trow = (dc04 & 0xF) - ((dc19 & 0x700) >> 8);\n+\tcol = ((dc04 & 0xF00) >> 8) - (dc20 & 0x7);\n+\n+\treturn (1 << (row + col)) * 4 * 2;\n+}\n--- /dev/null\n+++ b/arch/mips/cpu/mips32/arx100/mem_init.S\n@@ -0,0 +1,114 @@\n+/*\n+ * Copyright (C) 2007-2010 Lantiq Deutschland GmbH\n+ * Copyright (C) 2012 Daniel Schwierzeck, daniel.schwierzeck@gmail.com\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#include <config.h>\n+#include <asm/asm.h>\n+#include <asm/regdef.h>\n+#include <asm/addrspace.h>\n+#include <asm/arch/soc.h>\n+\n+/* Must be configured in BOARDDIR */\n+#include <ddr_settings.h>\n+\n+#define LTQ_MC_GEN_ERRCAUSE\t\t0x0010\n+#define LTQ_MC_GEN_ERRADDR\t\t0x0020\n+#define LTQ_MC_GEN_CON\t\t\t0x0060\n+#define LTQ_MC_GEN_STAT\t\t\t0x0070\n+#define LTQ_MC_GEN_CON_SRAM_DDR_ENABLE\t0xD\n+#define LTQ_MC_GEN_STAT_DLCK_PWRON\t0xC\n+\n+#define LTQ_MC_DDR_DC03_MC_START\t0x100\n+\n+\t/* Store given value in MC DDR CCRx register */\n+\t.macro dc_sw num, val\n+\tli\tt2, \\val\n+\tsw\tt2, LTQ_MC_DDR_DC_OFFSET(\\num)(t1)\n+\t.endm\n+\n+LEAF(ltq_mem_init)\n+\t/* Load MC General and MC DDR module base */\n+\tli\tt0, (LTQ_MC_GEN_BASE | KSEG1)\n+\tli\tt1, (LTQ_MC_DDR_BASE | KSEG1)\n+\n+\t/* Clear access error log registers */\n+\tsw\tzero, LTQ_MC_GEN_ERRCAUSE(t0)\n+\tsw\tzero, LTQ_MC_GEN_ERRADDR(t0)\n+\n+\t/* Enable DDR and SRAM module in memory controller */\n+\tli\tt2, LTQ_MC_GEN_CON_SRAM_DDR_ENABLE\n+\tsw\tt2, LTQ_MC_GEN_CON(t0)\n+\n+\t/* Clear start bit of DDR memory controller */\n+\tsw\tzero, LTQ_MC_DDR_DC_OFFSET(3)(t1)\n+\n+\t/* Init memory controller registers with values ddr_settings.h */\n+\tdc_sw\t0, MC_DC00_VALUE\n+\tdc_sw\t1, MC_DC01_VALUE\n+\tdc_sw\t2, MC_DC02_VALUE\n+\tdc_sw\t4, MC_DC04_VALUE\n+\tdc_sw\t5, MC_DC05_VALUE\n+\tdc_sw\t6, MC_DC06_VALUE\n+\tdc_sw\t7, MC_DC07_VALUE\n+\tdc_sw\t8, MC_DC08_VALUE\n+\tdc_sw\t9, MC_DC09_VALUE\n+\n+\tdc_sw\t10, MC_DC10_VALUE\n+\tdc_sw\t11, MC_DC11_VALUE\n+\tdc_sw\t12, MC_DC12_VALUE\n+\tdc_sw\t13, MC_DC13_VALUE\n+\tdc_sw\t14, MC_DC14_VALUE\n+\tdc_sw\t15, MC_DC15_VALUE\n+\tdc_sw\t16, MC_DC16_VALUE\n+\tdc_sw\t17, MC_DC17_VALUE\n+\tdc_sw\t18, MC_DC18_VALUE\n+\tdc_sw\t19, MC_DC19_VALUE\n+\n+\tdc_sw\t20, MC_DC20_VALUE\n+\tdc_sw\t21, MC_DC21_VALUE\n+\tdc_sw\t22, MC_DC22_VALUE\n+\tdc_sw\t23, MC_DC23_VALUE\n+\tdc_sw\t24, MC_DC24_VALUE\n+\tdc_sw\t25, MC_DC25_VALUE\n+\tdc_sw\t26, MC_DC26_VALUE\n+\tdc_sw\t27, MC_DC27_VALUE\n+\tdc_sw\t28, MC_DC28_VALUE\n+\tdc_sw\t29, MC_DC29_VALUE\n+\n+\tdc_sw\t30, MC_DC30_VALUE\n+\tdc_sw\t31, MC_DC31_VALUE\n+\tdc_sw\t32, MC_DC32_VALUE\n+\tdc_sw\t33, MC_DC33_VALUE\n+\tdc_sw\t34, MC_DC34_VALUE\n+\tdc_sw\t35, MC_DC35_VALUE\n+\tdc_sw\t36, MC_DC36_VALUE\n+\tdc_sw\t37, MC_DC37_VALUE\n+\tdc_sw\t38, MC_DC38_VALUE\n+\tdc_sw\t39, MC_DC39_VALUE\n+\n+\tdc_sw\t40, MC_DC40_VALUE\n+\tdc_sw\t41, MC_DC41_VALUE\n+\tdc_sw\t42, MC_DC42_VALUE\n+\tdc_sw\t43, MC_DC43_VALUE\n+\tdc_sw\t44, MC_DC44_VALUE\n+\tdc_sw\t45, MC_DC45_VALUE\n+\tdc_sw\t46, MC_DC46_VALUE\n+\n+\t/* Set start bit of DDR memory controller */\n+\tli\tt2, LTQ_MC_DDR_DC03_MC_START\n+\tsw\tt2, LTQ_MC_DDR_DC_OFFSET(3)(t1)\n+\n+\t/* Wait until DLL has locked and core is ready for data transfers */\n+wait_ready:\n+\tlw\tt2, LTQ_MC_GEN_STAT(t0)\n+\tli\tt3, LTQ_MC_GEN_STAT_DLCK_PWRON\n+\tand\tt2, t3\n+\tbne\tt2, t3, wait_ready\n+\n+finished:\n+\tjr\tra\n+\n+\tEND(ltq_mem_init)\n--- /dev/null\n+++ b/arch/mips/cpu/mips32/arx100/pmu.c\n@@ -0,0 +1,120 @@\n+/*\n+ * Copyright (C) 2012 Daniel Schwierzeck, daniel.schwierzeck@gmail.com\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#include <common.h>\n+#include <asm/lantiq/io.h>\n+#include <asm/lantiq/pm.h>\n+#include <asm/arch/soc.h>\n+\n+#define LTQ_PMU_PWDCR_RESERVED\t\t0xE00C200C\n+\n+#define LTQ_PMU_PWDCR_SWITCH\t\t(1 << 28)\n+#define LTQ_PMU_PWDCR_USB1\t\t(1 << 27)\n+#define LTQ_PMU_PWDCR_USB1_PHY\t\t(1 << 26)\n+#define LTQ_PMU_PWDCR_TDM\t\t(1 << 25)\n+#define LTQ_PMU_PWDCR_DDR_MEM\t\t(1 << 24)\n+#define LTQ_PMU_PWDCR_PPE_DP\t\t(1 << 23)\n+#define LTQ_PMU_PWDCR_PPE_EMA\t\t(1 << 22)\n+#define LTQ_PMU_PWDCR_PPE_TC\t\t(1 << 21)\n+#define LTQ_PMU_PWDCR_DEU\t\t(1 << 20)\n+#define LTQ_PMU_PWDCR_UART1\t\t(1 << 17)\n+#define LTQ_PMU_PWDCR_SDIO\t\t(1 << 16)\n+#define LTQ_PMU_PWDCR_AHB\t\t(1 << 15)\n+#define LTQ_PMU_PWDCR_FPI0\t\t(1 << 14)\n+#define LTQ_PMU_PWDCR_GPTC\t\t(1 << 12)\n+#define LTQ_PMU_PWDCR_LEDC\t\t(1 << 11)\n+#define LTQ_PMU_PWDCR_EBU\t\t(1 << 10)\n+#define LTQ_PMU_PWDCR_DSL\t\t(1 << 9)\n+#define LTQ_PMU_PWDCR_SPI\t\t(1 << 8)\n+#define LTQ_PMU_PWDCR_UART0\t\t(1 << 7)\n+#define LTQ_PMU_PWDCR_USB\t\t(1 << 6)\n+#define LTQ_PMU_PWDCR_DMA\t\t(1 << 5)\n+#define LTQ_PMU_PWDCR_PCI\t\t(1 << 4)\n+#define LTQ_PMU_PWDCR_FPI1\t\t(1 << 1)\n+#define LTQ_PMU_PWDCR_USB0_PHY\t\t(1 << 0)\n+\n+struct ltq_pmu_regs {\n+\tu32\trsvd0[7];\n+\t__be32\tpwdcr;\n+\t__be32\tsr;\n+};\n+\n+static struct ltq_pmu_regs *ltq_pmu_regs =\n+\t(struct ltq_pmu_regs *) CKSEG1ADDR(LTQ_PMU_BASE);\n+\n+u32 ltq_pm_map(enum ltq_pm_modules module)\n+{\n+\tu32 val;\n+\n+\tswitch (module) {\n+\tcase LTQ_PM_CORE:\n+\t\tval = LTQ_PMU_PWDCR_DDR_MEM | LTQ_PMU_PWDCR_UART1 |\n+\t\t\tLTQ_PMU_PWDCR_FPI0 | LTQ_PMU_PWDCR_LEDC |\n+\t\t\tLTQ_PMU_PWDCR_EBU;\n+\t\tbreak;\n+\tcase LTQ_PM_DMA:\n+\t\tval = LTQ_PMU_PWDCR_DMA;\n+\t\tbreak;\n+\tcase LTQ_PM_ETH:\n+\t\tval = LTQ_PMU_PWDCR_SWITCH | LTQ_PMU_PWDCR_PPE_DP |\n+\t\t\tLTQ_PMU_PWDCR_PPE_EMA | LTQ_PMU_PWDCR_PPE_TC;\n+\t\tbreak;\n+\tcase LTQ_PM_SPI:\n+\t\tval = LTQ_PMU_PWDCR_SPI;\n+\t\tbreak;\n+\tdefault:\n+\t\tval = 0;\n+\t\tbreak;\n+\t}\n+\n+\treturn val;\n+}\n+\n+int ltq_pm_enable(enum ltq_pm_modules module)\n+{\n+\tconst unsigned long timeout = 1000;\n+\tunsigned long timebase;\n+\tu32 sr, val;\n+\n+\tval = ltq_pm_map(module);\n+\tif (unlikely(!val))\n+\t\treturn 1;\n+\n+\tltq_clrbits(&ltq_pmu_regs->pwdcr, val);\n+\n+\ttimebase = get_timer(0);\n+\n+\tdo {\n+\t\tsr = ltq_readl(&ltq_pmu_regs->sr);\n+\t\tif (~sr & val)\n+\t\t\treturn 0;\n+\t} while (get_timer(timebase) < timeout);\n+\n+\treturn 1;\n+}\n+\n+int ltq_pm_disable(enum ltq_pm_modules module)\n+{\n+\tu32 val;\n+\n+\tval = ltq_pm_map(module);\n+\tif (unlikely(!val))\n+\t\treturn 1;\n+\n+\tltq_setbits(&ltq_pmu_regs->pwdcr, val);\n+\n+\treturn 0;\n+}\n+\n+void ltq_pmu_init(void)\n+{\n+\tu32 set, clr;\n+\n+\tclr = ltq_pm_map(LTQ_PM_CORE);\n+\tset = ~(LTQ_PMU_PWDCR_RESERVED | clr);\n+\n+\tltq_clrsetbits(&ltq_pmu_regs->pwdcr, clr, set);\n+}\n--- /dev/null\n+++ b/arch/mips/cpu/mips32/arx100/rcu.c\n@@ -0,0 +1,130 @@\n+/*\n+ * Copyright (C) 2012 Daniel Schwierzeck, daniel.schwierzeck@gmail.com\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#include <common.h>\n+#include <asm/lantiq/io.h>\n+#include <asm/lantiq/reset.h>\n+#include <asm/lantiq/cpu.h>\n+#include <asm/arch/soc.h>\n+\n+#define LTQ_RCU_RD_SRST\t\t(1 << 30)\t/* Global SW Reset */\n+#define LTQ_RCU_RD_USB1\t\t(1 << 28)\t/* USB1 MAC and PHY */\n+#define LTQ_RCU_RD_REG25_PD\t(1 << 26)\t/* Power down 2.5V regulator */\n+#define LTQ_RCU_RD_PPE_ATM_TC\t(1 << 22)\t/* PPE ATM TC */\n+#define LTQ_RCU_RD_ETHSW\t(1 << 21)\t/* Ethernet switch */\n+#define LTQ_RCU_RD_DSP_DEN\t(1 << 20)\t/* Enable DSP JTAG */\n+#define LTQ_RCU_RD_TDM\t\t(1 << 19)\t/* TDM module interface */\n+#define LTQ_RCU_RD_MC\t\t(1 << 14)\t/* Memory Controller */\n+#define LTQ_RCU_RD_PCI\t\t(1 << 13)\t/* PCI core */\n+#define LTQ_RCU_RD_SDIO\t\t(1 << 10)\t/* SDIO core */\n+#define LTQ_RCU_RD_DMA\t\t(1 << 9)\t/* DMA core */\n+#define LTQ_RCU_RD_PPE\t\t(1 << 8)\t/* PPE core */\n+#define LTQ_RCU_RD_ARC_DFE\t(1 << 7)\t/* ARC/DFE core */\n+#define LTQ_RCU_RD_AHB\t\t(1 << 6)\t/* AHB bus */\n+#define LTQ_RCU_RD_USB\t\t(1 << 4)\t/* USB and Phy core */\n+#define LTQ_RCU_RD_FPI\t\t(1 << 2)\t/* FPI bus */\n+#define LTQ_RCU_RD_CPU0\t\t(1 << 1)\t/* CPU0 subsystem */\n+#define LTQ_RCU_RD_HRST\t\t(1 << 0)\t/* HW reset via HRST pin */\n+\n+#define LTQ_RCU_STAT_BOOT_SHIFT\t\t17\n+#define LTQ_RCU_STAT_BOOT_MASK\t\t(0xf << LTQ_RCU_STAT_BOOT_SHIFT)\n+\n+struct ltq_rcu_regs {\n+\tu32\trsvd0[4];\n+\t__be32\treq;\t\t/* Reset request */\n+\t__be32\tstat;\t\t/* Reset status */\n+\t__be32\tusb0_cfg;\t/* USB0 config */\n+\tu32\trsvd1[2];\n+\t__be32\tpci_rdy;\t/* PCI boot ready */\n+\t__be32\tppe_conf;\t/* PPE config */\n+\tu32\trsvd2;\n+\t__be32\tusb1_cfg;\t/* USB1 config */\n+};\n+\n+static struct ltq_rcu_regs *ltq_rcu_regs =\n+\t(struct ltq_rcu_regs *) CKSEG1ADDR(LTQ_RCU_BASE);\n+\n+u32 ltq_reset_map(enum ltq_reset_modules module)\n+{\n+\tu32 val;\n+\n+\tswitch (module) {\n+\tcase LTQ_RESET_CORE:\n+\tcase LTQ_RESET_SOFT:\n+\t\tval = LTQ_RCU_RD_SRST | LTQ_RCU_RD_CPU0;\n+\t\tbreak;\n+\tcase LTQ_RESET_DMA:\n+\t\tval = LTQ_RCU_RD_DMA;\n+\t\tbreak;\n+\tcase LTQ_RESET_ETH:\n+\t\tval = LTQ_RCU_RD_PPE | LTQ_RCU_RD_ETHSW;\n+\t\tbreak;\n+\tcase LTQ_RESET_HARD:\n+\t\tval = LTQ_RCU_RD_HRST;\n+\t\tbreak;\n+\tdefault:\n+\t\tval = 0;\n+\t\tbreak;\n+\t}\n+\n+\treturn val;\n+}\n+\n+int ltq_reset_activate(enum ltq_reset_modules module)\n+{\n+\tu32 val;\n+\n+\tval = ltq_reset_map(module);\n+\tif (unlikely(!val))\n+\t\treturn 1;\n+\n+\tltq_setbits(&ltq_rcu_regs->req, val);\n+\n+\treturn 0;\n+}\n+\n+int ltq_reset_deactivate(enum ltq_reset_modules module)\n+{\n+\tu32 val;\n+\n+\tval = ltq_reset_map(module);\n+\tif (unlikely(!val))\n+\t\treturn 1;\n+\n+\tltq_clrbits(&ltq_rcu_regs->req, val);\n+\n+\treturn 0;\n+}\n+\n+enum ltq_boot_select ltq_boot_select(void)\n+{\n+\tu32 stat;\n+\tunsigned int bootstrap;\n+\n+\tstat = ltq_readl(&ltq_rcu_regs->stat);\n+\tbootstrap = (stat & LTQ_RCU_STAT_BOOT_MASK) >> LTQ_RCU_STAT_BOOT_SHIFT;\n+\n+\tswitch (bootstrap) {\n+\tcase 0:\n+\t\treturn BOOT_NOR_NO_BOOTROM;\n+\tcase 1:\n+\t\treturn BOOT_RGMII0;\n+\tcase 2:\n+\t\treturn BOOT_NOR;\n+\tcase 3:\n+\t\treturn BOOT_MII0;\n+\tcase 5:\n+\t\treturn BOOT_RMII0;\n+\tcase 6:\n+\t\treturn BOOT_PCI;\n+\tcase 8:\n+\t\treturn BOOT_UART;\n+\tcase 10:\n+\t\treturn BOOT_SPI;\n+\tdefault:\n+\t\treturn BOOT_UNKNOWN;\n+\t}\n+}\n--- a/arch/mips/cpu/mips32/lantiq-common/cpu.c\n+++ b/arch/mips/cpu/mips32/lantiq-common/cpu.c\n@@ -20,6 +20,7 @@ static const char ltq_bootsel_strings[][\n \t\"PCI\",\n \t\"MII0\",\n \t\"RMII0\",\n+\t\"RGMII0\",\n \t\"RGMII1\",\n \t\"unknown\",\n };\n--- a/arch/mips/cpu/mips32/lantiq-common/start.S\n+++ b/arch/mips/cpu/mips32/lantiq-common/start.S\n@@ -64,6 +64,11 @@\n #define STATUS_LANTIQ\t\t(STATUS_MIPS24K | STATUS_MIPS32_64)\n #endif\n \n+#ifdef CONFIG_SOC_XWAY_ARX100\n+#define CONFIG0_LANTIQ\t\t(CONFIG0_MIPS34K | CONFIG0_MIPS32_64)\n+#define STATUS_LANTIQ\t\t(STATUS_MIPS34K | STATUS_MIPS32_64)\n+#endif\n+\n #ifdef CONFIG_SOC_XWAY_VRX200\n #define CONFIG0_LANTIQ\t\t(CONFIG0_MIPS34K | CONFIG0_MIPS32_64)\n #define STATUS_LANTIQ\t\t(STATUS_MIPS34K | STATUS_MIPS32_64)\n--- /dev/null\n+++ b/arch/mips/include/asm/arch-arx100/config.h\n@@ -0,0 +1,176 @@\n+/*\n+ * Copyright (C) 2007-2010 Lantiq Deutschland GmbH\n+ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ *\n+ * Common board configuration for Lantiq XWAY ARX100 family\n+ *\n+ * Use following defines in your board config to enable specific features\n+ * and drivers for this SoC:\n+ *\n+ * CONFIG_LTQ_SUPPORT_UART\n+ * - support the Danube ASC/UART interface and console\n+ *\n+ * CONFIG_LTQ_SUPPORT_NOR_FLASH\n+ * - support a parallel NOR flash via the CFI interface in flash bank 0\n+ *\n+ * CONFIG_LTQ_SUPPORT_ETHERNET\n+ * - support the Danube ETOP and MAC interface\n+ *\n+ * CONFIG_LTQ_SUPPORT_SPI_FLASH\n+ * - support the Danube SPI interface and serial flash drivers\n+ * - specific SPI flash drivers must be configured separately\n+ */\n+\n+#ifndef __ARX100_CONFIG_H__\n+#define __ARX100_CONFIG_H__\n+\n+/* CPU and SoC type */\n+#define CONFIG_SOC_LANTIQ\n+#define CONFIG_SOC_XWAY_ARX100\n+\n+/* Cache configuration */\n+#define CONFIG_SYS_MIPS_CACHE_MODE\tCONF_CM_CACHABLE_NONCOHERENT\n+#define CONFIG_SYS_DCACHE_SIZE\t\t(16 * 1024)\n+#define CONFIG_SYS_ICACHE_SIZE\t\t(32 * 1024)\n+#define CONFIG_SYS_CACHELINE_SIZE\t32\n+#define CONFIG_SYS_MIPS_CACHE_EXT_INIT\n+\n+/*\n+ * Supported clock modes\n+ * PLL0: rational PLL running at 500 MHz\n+ * PLL1: fractional PLL running at 393.219 MHz\n+ */\n+#define LTQ_CLK_CPU_393_DDR_197\t\t0\n+#define LTQ_CLK_CPU_197_DDR_197\t\t1\n+#define LTQ_CLK_CPU_333_DDR_167\t\t2\n+#define LTQ_CLK_CPU_167_DDR_167\t\t3\n+#define LTQ_CLK_CPU_131_DDR_131\t\t4\n+#define LTQ_CLK_CPU_111_DDR_111\t\t5\n+\n+/* CPU speed */\n+#define CONFIG_SYS_CLOCK_MODE\t\tLTQ_CLK_CPU_333_DDR_167\n+#define CONFIG_SYS_MIPS_TIMER_FREQ\t166666667\n+#define CONFIG_SYS_HZ\t\t\t1000\n+\n+/* RAM */\n+#define CONFIG_NR_DRAM_BANKS\t\t1\n+#define CONFIG_SYS_SDRAM_BASE\t\t0x80000000\n+#define CONFIG_SYS_SDRAM_BASE_UC\t0xa0000000\n+#define CONFIG_SYS_MEMTEST_START\t0x81000000\n+#define CONFIG_SYS_MEMTEST_END\t\t0x82000000\n+#define CONFIG_SYS_LOAD_ADDR\t\t0x81000000\n+#define CONFIG_SYS_LOAD_SIZE\t\t(2 * 1024 * 1024)\n+#define CONFIG_SYS_INIT_SP_OFFSET\t(32 * 1024)\n+\n+/* SRAM */\n+#define CONFIG_SYS_SRAM_BASE\t\t0xBE1A0000\n+#define CONFIG_SYS_SRAM_SIZE\t\t0x10000\n+\n+/* ASC/UART driver and console */\n+#define CONFIG_LANTIQ_SERIAL\n+#define CONFIG_SYS_BAUDRATE_TABLE\t{ 9600, 19200, 38400, 57600, 115200 }\n+\n+/* GPIO */\n+#define CONFIG_LANTIQ_GPIO\n+#define CONFIG_LTQ_GPIO_MAX_BANKS\t3\n+#define CONFIG_LTQ_HAS_GPIO_BANK3\n+\n+/* FLASH driver */\n+#if defined(CONFIG_LTQ_SUPPORT_NOR_FLASH)\n+#define CONFIG_SYS_MAX_FLASH_BANKS\t1\n+#define CONFIG_SYS_MAX_FLASH_SECT\t256\n+#define CONFIG_SYS_FLASH_BASE\t\t0xB0000000\n+#define CONFIG_FLASH_16BIT\n+#define CONFIG_SYS_FLASH_CFI\n+#define CONFIG_FLASH_CFI_DRIVER\n+#define CONFIG_SYS_FLASH_CFI_WIDTH\tFLASH_CFI_16BIT\n+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE\n+#define CONFIG_FLASH_SHOW_PROGRESS\t50\n+#define CONFIG_SYS_FLASH_PROTECTION\n+#define CONFIG_CFI_FLASH_USE_WEAK_ADDR_SWAP\n+\n+#define CONFIG_CMD_FLASH\n+#else\n+#define CONFIG_SYS_NO_FLASH\n+#endif /* CONFIG_NOR_FLASH */\n+\n+#if defined(CONFIG_LTQ_SUPPORT_SPI_FLASH)\n+#define CONFIG_LANTIQ_SPI\n+#define CONFIG_SPI_FLASH\n+\n+#define CONFIG_CMD_SF\n+#define CONFIG_CMD_SPI\n+#endif\n+\n+#if defined(CONFIG_LTQ_SUPPORT_NAND_FLASH)\n+#define CONFIG_NAND_LANTIQ\n+#define CONFIG_SYS_MAX_NAND_DEVICE\t1\n+#define CONFIG_SYS_NAND_BASE\t\t0xB4000000\n+\n+#define CONFIG_CMD_NAND\n+#endif\n+\n+#if defined(CONFIG_LTQ_SUPPORT_ETHERNET)\n+#define CONFIG_LANTIQ_DMA\n+#define CONFIG_LANTIQ_ARX100_SWITCH\n+\n+#define CONFIG_PHYLIB\n+#define CONFIG_MII\n+#define CONFIG_UDP_CHECKSUM\n+\n+#define CONFIG_CMD_MII\n+#define CONFIG_CMD_NET\n+#endif\n+\n+#define CONFIG_SPL_MAX_SIZE\t\t(32 * 1024)\n+#define CONFIG_SPL_BSS_MAX_SIZE\t\t(8 * 1024)\n+#define CONFIG_SPL_STACK_MAX_SIZE\t(8 * 1024)\n+#define CONFIG_SPL_MALLOC_MAX_SIZE\t(32 * 1024)\n+#define CONFIG_SPL_STACK_BSS_IN_SRAM\n+\n+#if defined(CONFIG_SPL_STACK_BSS_IN_SRAM)\n+#define CONFIG_SPL_STACK_BASE\t\t(CONFIG_SYS_SRAM_BASE + \\\n+\t\t\t\t\tCONFIG_SPL_MAX_SIZE + \\\n+\t\t\t\t\tCONFIG_SPL_STACK_MAX_SIZE - 1)\n+#define CONFIG_SPL_BSS_BASE\t  \t(CONFIG_SPL_STACK_BASE + 1)\n+#define CONFIG_SPL_MALLOC_BASE\t\t(CONFIG_SYS_SDRAM_BASE + \\\n+\t\t\t\t\tCONFIG_SYS_INIT_SP_OFFSET)\n+#else\n+#define CONFIG_SPL_STACK_BASE\t\t(CONFIG_SYS_SDRAM_BASE + \\\n+\t\t\t\t\tCONFIG_SYS_INIT_SP_OFFSET + \\\n+\t\t\t\t\tCONFIG_SPL_STACK_MAX_SIZE - 1)\n+#define CONFIG_SPL_BSS_BASE\t\t(CONFIG_SPL_STACK_BASE + 1)\n+#define CONFIG_SPL_MALLOC_BASE\t\t(CONFIG_SPL_BSS_BASE + \\\n+\t\t\t\t\tCONFIG_SPL_BSS_MAX_SIZE)\n+#endif\n+\n+#if defined(CONFIG_SYS_BOOT_RAM)\n+#define CONFIG_SYS_TEXT_BASE\t\t0xA0100000\n+#define CONFIG_SKIP_LOWLEVEL_INIT\n+#define CONFIG_SYS_DISABLE_CACHE\n+#endif\n+\n+#if defined(CONFIG_SYS_BOOT_NOR)\n+#define CONFIG_SYS_TEXT_BASE\t\t0xB0000000\n+#endif\n+\n+#if defined(CONFIG_SYS_BOOT_SFSPL) || defined(CONFIG_SYS_BOOT_NANDSPL)\n+#define CONFIG_SYS_TEXT_BASE\t\t0x80100000\n+#define CONFIG_SPL_TEXT_BASE\t\t0xBE1A0000\n+#endif\n+\n+#if defined(CONFIG_SYS_BOOT_NORSPL)\n+#define CONFIG_SYS_TEXT_BASE\t\t0x80100000\n+#define CONFIG_SPL_TEXT_BASE\t\t0xB0000000\n+#endif\n+\n+#if defined(CONFIG_SYS_BOOT_NOR) || defined(CONFIG_SYS_BOOT_NORSPL)\n+#define CONFIG_SYS_XWAY_EBU_BOOTCFG\t0x688C688C\n+#define CONFIG_XWAY_SWAP_BYTES\n+#endif\n+\n+#define\tCONFIG_SYS_MONITOR_BASE\t\tCONFIG_SYS_TEXT_BASE\n+\n+#endif /* __ARX100_CONFIG_H__ */\n--- /dev/null\n+++ b/arch/mips/include/asm/arch-arx100/gpio.h\n@@ -0,0 +1,12 @@\n+/*\n+ * Copyright (C) 2012 Daniel Schwierzeck, daniel.schwierzeck@gmail.com\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#ifndef __ARX100_GPIO_H__\n+#define __ARX100_GPIO_H__\n+\n+#include <asm/lantiq/gpio.h>\n+\n+#endif /* __ARX100_GPIO_H__ */\n--- /dev/null\n+++ b/arch/mips/include/asm/arch-arx100/nand.h\n@@ -0,0 +1,13 @@\n+/*\n+ * Copyright (C) 2012-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#ifndef __VRX200_NAND_H__\n+#define __VRX200_NAND_H__\n+\n+struct nand_chip;\n+int ltq_nand_init(struct nand_chip *nand);\n+\n+#endif /* __VRX200_NAND_H__ */\n--- /dev/null\n+++ b/arch/mips/include/asm/arch-arx100/soc.h\n@@ -0,0 +1,37 @@\n+/*\n+ * Copyright (C) 2007-2010 Lantiq Deutschland GmbH\n+ * Copyright (C) 2012 Daniel Schwierzeck, daniel.schwierzeck@gmail.com\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#ifndef __ARX100_SOC_H__\n+#define __ARX100_SOC_H__\n+\n+#define LTQ_ASC0_BASE\t\t\t0x1E100400\n+#define LTQ_SPI_BASE\t\t\t0x1E100800\n+#define LTQ_GPIO_BASE\t\t\t0x1E100B00\n+#define LTQ_SSIO_BASE\t\t\t0x1E100BB0\n+#define LTQ_ASC1_BASE\t\t\t0x1E100C00\n+#define LTQ_DMA_BASE\t\t\t0x1E104100\n+\n+#define LTQ_EBU_BASE\t\t\t0x1E105300\n+#define LTQ_EBU_REGION0_BASE\t\t0x10000000\n+#define LTQ_EBU_REGION1_BASE\t\t0x14000000\n+#define LTQ_EBU_NAND_BASE\t\t(LTQ_EBU_BASE + 0xB0)\n+\n+#define LTQ_PPE_BASE\t\t\t0x1E180000\n+#define LTQ_SWITCH_BASE\t\t\t0x1E108000\n+\n+#define LTQ_PMU_BASE\t\t\t0x1F102000\n+#define LTQ_CGU_BASE\t\t\t0x1F103000\n+#define LTQ_MPS_BASE\t\t\t0x1F107000\n+#define LTQ_CHIPID_BASE\t\t\t(LTQ_MPS_BASE + 0x340)\n+#define LTQ_RCU_BASE\t\t\t0x1F203000\n+\n+#define LTQ_MC_GEN_BASE\t\t\t0x1F800000\n+#define LTQ_MC_SDR_BASE\t\t\t0x1F800200\n+#define LTQ_MC_DDR_BASE\t\t\t0x1F801000\n+#define LTQ_MC_DDR_DC_OFFSET(x)\t\t(x * 0x10)\n+\n+#endif /* __ARX100_SOC_H__ */\n--- a/arch/mips/include/asm/lantiq/chipid.h\n+++ b/arch/mips/include/asm/lantiq/chipid.h\n@@ -15,6 +15,10 @@ enum ltq_chip_partnum {\n \tLTQ_SOC_DANUBE = 0x0129,\n \tLTQ_SOC_DANUBE_S = 0x012B,\n \tLTQ_SOC_TWINPASS = 0x012D,\n+\tLTQ_SOC_ARX188 = 0x016C,\t/* ARX188 */\n+\tLTQ_SOC_ARX186 = 0x016D,\t/* ARX186 v1.1 */\n+\tLTQ_SOC_ARX186_2 = 0x016E,\t/* ARX186 v1.2 */\n+\tLTQ_SOC_ARX182 = 0x016F,\t/* ARX182 */\n \tLTQ_SOC_VRX288 = 0x01C0,\t/* VRX288 v1.1 */\n \tLTQ_SOC_VRX268 = 0x01C2,\t/* VRX268 v1.1 */\n \tLTQ_SOC_GRX288 = 0x01C9,\t/* GRX288 v1.1 */\n@@ -36,6 +40,38 @@ static inline int ltq_soc_is_danube(void\n {\n \treturn 0;\n }\n+#endif\n+\n+#ifdef CONFIG_SOC_XWAY_ARX100\n+static inline int ltq_soc_is_arx100(void)\n+{\n+\treturn 1;\n+}\n+\n+static inline int ltq_soc_is_arx100_v1(void)\n+{\n+\treturn ltq_chip_version_get() == 1;\n+}\n+\n+static inline int ltq_soc_is_arx100_v2(void)\n+{\n+\treturn ltq_chip_version_get() == 2;\n+}\n+#else\n+static inline int ltq_soc_is_arx100(void)\n+{\n+\treturn 0;\n+}\n+\n+static inline int ltq_soc_is_arx100_v1(void)\n+{\n+\treturn 0;\n+}\n+\n+static inline int ltq_soc_is_arx100_v2(void)\n+{\n+\treturn 0;\n+}\n #endif\n \n #ifdef CONFIG_SOC_XWAY_VRX200\n--- a/arch/mips/include/asm/lantiq/clk.h\n+++ b/arch/mips/include/asm/lantiq/clk.h\n@@ -13,9 +13,10 @@ enum ltq_clk {\n \tCLOCK_83_MHZ = 83333333,\n \tCLOCK_111_MHZ = 111111111,\n \tCLOCK_125_MHZ = 125000000,\n+\tCLOCK_131_MHZ = 131073000,\n \tCLOCK_133_MHZ = 133333333,\n \tCLOCK_166_MHZ = 166666667,\n-\tCLOCK_197_MHZ = 197000000,\n+\tCLOCK_197_MHZ = 196609500,\n \tCLOCK_333_MHZ = 333333333,\n \tCLOCK_393_MHZ = 393219000,\n \tCLOCK_500_MHZ = 500000000,\n--- a/arch/mips/include/asm/lantiq/cpu.h\n+++ b/arch/mips/include/asm/lantiq/cpu.h\n@@ -17,6 +17,7 @@ enum ltq_boot_select {\n \tBOOT_PCI,\n \tBOOT_MII0,\n \tBOOT_RMII0,\n+\tBOOT_RGMII0,\n \tBOOT_RGMII1,\n \tBOOT_UNKNOWN,\n };\n"
  },
  {
    "path": "package/boot/uboot-lantiq/patches/0016-net-add-driver-for-Lantiq-XWAY-ARX100-switch.patch",
    "content": "From 7288414298b34dcda1216fee1fe38d05ea0027a2 Mon Sep 17 00:00:00 2001\nFrom: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>\nDate: Mon, 17 Dec 2012 23:32:39 +0100\nSubject: net: add driver for Lantiq XWAY ARX100 switch\n\nSigned-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>\n\n--- a/arch/mips/include/asm/arch-arx100/config.h\n+++ b/arch/mips/include/asm/arch-arx100/config.h\n@@ -10,17 +10,21 @@\n  * and drivers for this SoC:\n  *\n  * CONFIG_LTQ_SUPPORT_UART\n- * - support the Danube ASC/UART interface and console\n+ * - support the ARX100 ASC/UART interface and console\n  *\n  * CONFIG_LTQ_SUPPORT_NOR_FLASH\n  * - support a parallel NOR flash via the CFI interface in flash bank 0\n  *\n  * CONFIG_LTQ_SUPPORT_ETHERNET\n- * - support the Danube ETOP and MAC interface\n+ * - support the ARX100 ETOP and MAC interface\n  *\n  * CONFIG_LTQ_SUPPORT_SPI_FLASH\n- * - support the Danube SPI interface and serial flash drivers\n+ * - support the ARX100 SPI interface and serial flash drivers\n  * - specific SPI flash drivers must be configured separately\n+ *\n+ * CONFIG_LTQ_SUPPORT_SPL_SPI_FLASH\n+ * - build a preloader that runs in the internal SRAM and loads\n+ *   the U-Boot from SPI flash into RAM\n  */\n \n #ifndef __ARX100_CONFIG_H__\n--- /dev/null\n+++ b/arch/mips/include/asm/arch-arx100/switch.h\n@@ -0,0 +1,86 @@\n+/*\n+ *   Copyright (C) 2012-2013 Daniel Schwierzeck <daniel.schwierzeck@gmail.com>\n+ *\n+ *   SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#ifndef __ARX100_SWITCH_H__\n+#define __ARX100_SWITCH_H__\n+\n+struct ar9_switch_regs {\n+\t__be32\tps;\t\t/* Port status*/\n+\t__be32\tp0_ctl;\t\t/* Port 0 control */\n+\t__be32\tp1_ctl;\t\t/* Port 1 control */\n+\t__be32\tp2_ctl;\t\t/* Port 2 control */\n+\t__be32\tp0_vlan;\t/* Port 0 VLAN control */\n+\t__be32\tp1_vlan;\t/* Port 1 VLAN control */\n+\t__be32\tp2_vlan;\t/* Port 2 VLAN control */\n+\t__be32\tp0_inctl;\t/* Port 0 ingress control */\n+\t__be32\tp1_inctl;\t/* Port 1 ingress control */\n+\t__be32\tp2_inctl;\t/* Port 2 ingress control */\n+\tu32\trsvd0[16];\n+\t__be32\tsw_gctl0;\t/* Switch global control 0 */\n+\t__be32\tsw_gctl1;\t/* Switch global control 1 */\n+\t__be32\tarp;\t\t/* ARP/RARP */\n+\t__be32\tstrm_ctl;\t/* Storm control */\n+\t__be32\trgmii_ctl;\t/* RGMII/GMII port control */\n+\tu32\trsvd1[4];\n+\t__be32\tpmac_hd_ctl;\t/* PMAC header control */\n+\tu32\trsvd2[15];\n+\t__be32\tmdio_ctrl;\t/* MDIO indirect access control */\n+\t__be32\tmdio_data;\t/* MDIO indirect read data */\n+};\n+\n+#define BUILD_CHECK_AR9_REG(name, offset)\t\\\n+\tBUILD_BUG_ON(offsetof(struct ar9_switch_regs, name) != (offset))\n+\n+static inline void build_check_ar9_registers(void)\n+{\n+\tBUILD_CHECK_AR9_REG(sw_gctl0, 0x68);\n+\tBUILD_CHECK_AR9_REG(rgmii_ctl, 0x78);\n+\tBUILD_CHECK_AR9_REG(pmac_hd_ctl, 0x8c);\n+\tBUILD_CHECK_AR9_REG(mdio_ctrl, 0xcc);\n+\tBUILD_CHECK_AR9_REG(mdio_data, 0xd0);\n+}\n+\n+#define P0_CTL_FLP\t\t(1 << 18)\n+#define P0_CTL_FLD\t\t(1 << 17)\n+\n+#define SW_GCTL0_SE\t\t(1 << 31)\n+\n+#define RGMII_CTL_P1_SHIFT\t10\n+#define RGMII_CTL_P1_MASK\t(0x3FF << RGMII_CTL_P1_SHIFT)\n+#define RGMII_CTL_P0_MASK\t0x3FF\n+#define RGMII_CTL_P0IS_SHIFT\t8\n+#define RGMII_CTL_P0IS_RGMII\t(0x0 << RGMII_CTL_P0IS_SHIFT)\n+#define RGMII_CTL_P0IS_MII\t(0x1 << RGMII_CTL_P0IS_SHIFT)\n+#define RGMII_CTL_P0IS_REVMII\t(0x2 << RGMII_CTL_P0IS_SHIFT)\n+#define RGMII_CTL_P0IS_RMII\t(0x3 << RGMII_CTL_P0IS_SHIFT)\n+#define RGMII_CTL_P0RDLY_SHIFT\t6\n+#define RGMII_CTL_P0RDLY_0_0\t(0x0 << RGMII_CTL_P0RDLY_SHIFT)\n+#define RGMII_CTL_P0RDLY_1_5\t(0x1 << RGMII_CTL_P0RDLY_SHIFT)\n+#define RGMII_CTL_P0RDLY_1_75\t(0x2 << RGMII_CTL_P0RDLY_SHIFT)\n+#define RGMII_CTL_P0RDLY_2_0\t(0x3 << RGMII_CTL_P0RDLY_SHIFT)\n+#define RGMII_CTL_P0TDLY_SHIFT\t4\n+#define RGMII_CTL_P0TDLY_0_0\t(0x0 << RGMII_CTL_P0TDLY_SHIFT)\n+#define RGMII_CTL_P0TDLY_1_5\t(0x1 << RGMII_CTL_P0TDLY_SHIFT)\n+#define RGMII_CTL_P0TDLY_1_75\t(0x2 << RGMII_CTL_P0TDLY_SHIFT)\n+#define RGMII_CTL_P0TDLY_2_0\t(0x3 << RGMII_CTL_P0TDLY_SHIFT)\n+#define RGMII_CTL_P0SPD_SHIFT\t2\n+#define RGMII_CTL_P0SPD_10\t(0x0 << RGMII_CTL_P0SPD_SHIFT)\n+#define RGMII_CTL_P0SPD_100\t(0x1 << RGMII_CTL_P0SPD_SHIFT)\n+#define RGMII_CTL_P0SPD_1000\t(0x2 << RGMII_CTL_P0SPD_SHIFT)\n+#define RGMII_CTL_P0DUP_FULL\t(1 << 1)\n+#define RGMII_CTL_P0FCE_EN\t(1 << 0)\n+\n+#define PMAC_HD_CTL_AC\t\t(1 << 18)\n+\n+#define MDIO_CTRL_WD_SHIFT\t16\n+#define MDIO_CTRL_MBUSY\t\t(1 << 15)\n+#define MDIO_CTRL_OP_READ\t(1 << 11)\n+#define MDIO_CTRL_OP_WRITE\t(1 << 10)\n+#define MDIO_CTRL_PHYAD_SHIFT\t5\n+#define MDIO_CTRL_PHYAD_MASK\t(0x1f << MDIO_CTRL_PHYAD_SHIFT)\n+#define MDIO_CTRL_REGAD_MASK\t0x1f\n+\n+#endif /* __ARX100_SWITCH_H__ */\n--- a/drivers/net/Makefile\n+++ b/drivers/net/Makefile\n@@ -38,6 +38,7 @@ COBJS-$(CONFIG_DRIVER_KS8695ETH) += ks86\n COBJS-$(CONFIG_KS8851_MLL) += ks8851_mll.o\n COBJS-$(CONFIG_LAN91C96) += lan91c96.o\n COBJS-$(CONFIG_LANTIQ_DANUBE_ETOP) += lantiq_danube_etop.o\n+COBJS-$(CONFIG_LANTIQ_ARX100_SWITCH) += lantiq_arx100_switch.o\n COBJS-$(CONFIG_LANTIQ_VRX200_SWITCH) += lantiq_vrx200_switch.o\n COBJS-$(CONFIG_MACB) += macb.o\n COBJS-$(CONFIG_MCFFEC) += mcffec.o mcfmii.o\n--- /dev/null\n+++ b/drivers/net/lantiq_arx100_switch.c\n@@ -0,0 +1,410 @@\n+/*\n+ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+#define DEBUG\n+#include <common.h>\n+#include <malloc.h>\n+#include <netdev.h>\n+#include <miiphy.h>\n+#include <switch.h>\n+#include <linux/compiler.h>\n+#include <asm/gpio.h>\n+#include <asm/processor.h>\n+#include <asm/lantiq/io.h>\n+#include <asm/lantiq/eth.h>\n+#include <asm/lantiq/pm.h>\n+#include <asm/lantiq/reset.h>\n+#include <asm/lantiq/dma.h>\n+#include <asm/arch/soc.h>\n+#include <asm/arch/switch.h>\n+\n+#define LTQ_ETH_RX_BUFFER_CNT\t\tPKTBUFSRX\n+#define LTQ_ETH_TX_BUFFER_CNT\t\t8\n+#define LTQ_ETH_RX_DATA_SIZE\t\tPKTSIZE_ALIGN\n+#define LTQ_ETH_IP_ALIGN\t\t2\n+\n+#define LTQ_MDIO_DRV_NAME\t\t\"ltq-mdio\"\n+#define LTQ_ETH_DRV_NAME\t\t\"ltq-eth\"\n+\n+#define LTQ_ETHSW_MAX_GMAC\t\t2\n+#define LTQ_ETHSW_PMAC\t\t\t2\n+\n+struct ltq_eth_priv {\n+\tstruct ltq_dma_device dma_dev;\n+\tstruct mii_dev *bus;\n+\tstruct eth_device *dev;\n+\tstruct phy_device *phymap[LTQ_ETHSW_MAX_GMAC];\n+\tint rx_num;\n+\tint tx_num;\n+};\n+\n+static struct ar9_switch_regs *switch_regs =\n+\t(struct ar9_switch_regs *) CKSEG1ADDR(LTQ_SWITCH_BASE);\n+\n+static int ltq_mdio_is_busy(void)\n+{\n+\tu32 mdio_ctrl = ltq_readl(&switch_regs->mdio_ctrl);\n+\n+\treturn mdio_ctrl & MDIO_CTRL_MBUSY;\n+}\n+\n+static void ltq_mdio_poll(void)\n+{\n+\twhile (ltq_mdio_is_busy())\n+\t\tcpu_relax();\n+\n+\t__udelay(1000);\n+}\n+\n+static int ltq_mdio_read(struct mii_dev *bus, int phyad, int devad,\n+\t\t\t\t\tint regad)\n+{\n+\tu32 mdio_ctrl;\n+\tint retval;\n+\n+\tmdio_ctrl = MDIO_CTRL_MBUSY | MDIO_CTRL_OP_READ |\n+\t\t((phyad << MDIO_CTRL_PHYAD_SHIFT) & MDIO_CTRL_PHYAD_MASK) |\n+\t\t(regad & MDIO_CTRL_REGAD_MASK);\n+\n+\tltq_mdio_poll();\n+\tltq_writel(&switch_regs->mdio_ctrl, mdio_ctrl);\n+\tltq_mdio_poll();\n+\tretval = ltq_readl(&switch_regs->mdio_data);\n+\tltq_writel(&switch_regs->mdio_data, 0xFFFF);\n+\n+\tdebug(\"%s: phyad %02x, regad %02x, val %02x\\n\", __func__, phyad, regad, retval);\n+\n+\treturn retval;\n+}\n+\n+static int ltq_mdio_write(struct mii_dev *bus, int phyad, int devad,\n+\t\t\t\t\tint regad, u16 val)\n+{\n+\tu32 mdio_ctrl;\n+\n+\tdebug(\"%s: phyad %02x, regad %02x, val %02x\\n\", __func__, phyad, regad, val);\n+\n+\tmdio_ctrl = (val << MDIO_CTRL_WD_SHIFT) | MDIO_CTRL_MBUSY |\n+\t\tMDIO_CTRL_OP_WRITE |\n+\t\t((phyad << MDIO_CTRL_PHYAD_SHIFT) & MDIO_CTRL_PHYAD_MASK) |\n+\t\t(regad & MDIO_CTRL_REGAD_MASK);\n+\n+\tltq_mdio_poll();\n+\tltq_writel(&switch_regs->mdio_ctrl, mdio_ctrl);\n+\n+\treturn 0;\n+}\n+\n+static void ltq_eth_gmac_update(struct phy_device *phydev, int num)\n+{\n+}\n+\n+static inline u8 *ltq_eth_rx_packet_align(int rx_num)\n+{\n+\tu8 *packet = (u8 *) NetRxPackets[rx_num];\n+\n+\t/*\n+\t * IP header needs\n+\t */\n+\treturn packet + LTQ_ETH_IP_ALIGN;\n+}\n+\n+static int ltq_eth_init(struct eth_device *dev, bd_t *bis)\n+{\n+\tstruct ltq_eth_priv *priv = dev->priv;\n+\tstruct ltq_dma_device *dma_dev = &priv->dma_dev;\n+\tstruct phy_device *phydev;\n+\tint i;\n+\n+\tfor (i = 0; i < LTQ_ETHSW_MAX_GMAC; i++) {\n+\t\tphydev = priv->phymap[i];\n+\t\tif (!phydev)\n+\t\t\tcontinue;\n+\n+\t\tphy_startup(phydev);\n+\t\tltq_eth_gmac_update(phydev, i);\n+\t}\n+\n+\tfor (i = 0; i < LTQ_ETH_RX_BUFFER_CNT; i++)\n+\t\tltq_dma_rx_map(dma_dev, i, ltq_eth_rx_packet_align(i),\n+\t\t\tLTQ_ETH_RX_DATA_SIZE);\n+\n+\tltq_dma_enable(dma_dev);\n+\n+\tpriv->rx_num = 0;\n+\tpriv->tx_num = 0;\n+\n+\treturn 0;\n+}\n+\n+static void ltq_eth_halt(struct eth_device *dev)\n+{\n+\tstruct ltq_eth_priv *priv = dev->priv;\n+\tstruct ltq_dma_device *dma_dev = &priv->dma_dev;\n+\tstruct phy_device *phydev;\n+\tint i;\n+\n+\tltq_dma_reset(dma_dev);\n+\n+\tfor (i = 0; i < LTQ_ETHSW_MAX_GMAC; i++) {\n+\t\tphydev = priv->phymap[i];\n+\t\tif (!phydev)\n+\t\t\tcontinue;\n+\n+\t\tphy_shutdown(phydev);\n+\t\tphydev->link = 0;\n+\t\tltq_eth_gmac_update(phydev, i);\n+\t}\n+}\n+\n+static int ltq_eth_send(struct eth_device *dev, void *packet, int length)\n+{\n+\tstruct ltq_eth_priv *priv = dev->priv;\n+\tstruct ltq_dma_device *dma_dev = &priv->dma_dev;\n+\tint err;\n+\n+\terr = ltq_dma_tx_map(dma_dev, priv->tx_num, packet, length, 10);\n+\tif (err) {\n+\t\tputs(\"NET: timeout on waiting for TX descriptor\\n\");\n+\t\treturn -1;\n+\t}\n+\n+\tpriv->tx_num = (priv->tx_num + 1) % LTQ_ETH_TX_BUFFER_CNT;\n+\n+\treturn err;\n+}\n+\n+static int ltq_eth_recv(struct eth_device *dev)\n+{\n+\tstruct ltq_eth_priv *priv = dev->priv;\n+\tstruct ltq_dma_device *dma_dev = &priv->dma_dev;\n+\tu8 *packet;\n+\tint len;\n+\n+\tif (!ltq_dma_rx_poll(dma_dev, priv->rx_num))\n+\t\treturn 0;\n+\n+#if 0\n+\tprintf(\"%s: rx_num %d\\n\", __func__, priv->rx_num);\n+#endif\n+\n+\tlen = ltq_dma_rx_length(dma_dev, priv->rx_num);\n+\tpacket = ltq_eth_rx_packet_align(priv->rx_num);\n+\n+#if 0\n+\tprintf(\"%s: received: packet %p, len %u, rx_num %d\\n\",\n+\t\t__func__, packet, len, priv->rx_num);\n+#endif\n+\n+\tif (len)\n+\t\tNetReceive(packet, len);\n+\n+\tltq_dma_rx_map(dma_dev, priv->rx_num, packet,\n+\t\tLTQ_ETH_RX_DATA_SIZE);\n+\n+\tpriv->rx_num = (priv->rx_num + 1) % LTQ_ETH_RX_BUFFER_CNT;\n+\n+\treturn 0;\n+}\n+\n+static void ltq_eth_pmac_init(void)\n+{\n+\t/* Add CRC to packets from DMA to PMAC */\n+\tltq_setbits(&switch_regs->pmac_hd_ctl, PMAC_HD_CTL_AC);\n+\n+\t/* Force link up */\n+\tltq_setbits(&switch_regs->p2_ctl, P0_CTL_FLP);\n+}\n+\n+static void ltq_eth_hw_init(const struct ltq_eth_port_config *port)\n+{\n+\t/* Power up ethernet subsystems */\n+\tltq_pm_enable(LTQ_PM_ETH);\n+\n+\t/* Enable switch core */\n+\tltq_setbits(&switch_regs->sw_gctl0, SW_GCTL0_SE);\n+\n+\t/* MII/MDIO */\n+\tgpio_set_altfunc(42, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);\n+\t/* MII/MDC */\n+\tgpio_set_altfunc(43, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);\n+\n+\tltq_eth_pmac_init();\n+}\n+\n+static void ltq_eth_port_config(struct ltq_eth_priv *priv,\n+\t\t\t\tconst struct ltq_eth_port_config *port)\n+{\n+\tstruct phy_device *phydev;\n+\tstruct switch_device *sw;\n+\tu32 rgmii_ctl;\n+\tunsigned int port_ctl, port_xmii = 0;\n+\n+\tif (port->num > 1)\n+\t\treturn;\n+\n+\trgmii_ctl = ltq_readl(&switch_regs->rgmii_ctl);\n+\n+\tif (port->num == 1)\n+\t\tport_ctl = ltq_readl(&switch_regs->p1_ctl);\n+\telse\n+\t\tport_ctl = ltq_readl(&switch_regs->p0_ctl);\n+\n+\tswitch (port->phy_if) {\n+\tcase PHY_INTERFACE_MODE_RGMII:\n+\t\tport_xmii = RGMII_CTL_P0IS_RGMII;\n+\n+\t\tswitch (port->rgmii_tx_delay) {\n+\t\tcase 1:\n+\t\t\tport_xmii |= RGMII_CTL_P0TDLY_1_5;\n+\t\t\tbreak;\n+\t\tcase 2:\n+\t\t\tport_xmii |= RGMII_CTL_P0TDLY_1_75;\n+\t\t\tbreak;\n+\t\tcase 3:\n+\t\t\tport_xmii |= RGMII_CTL_P0TDLY_2_0;\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\tswitch (port->rgmii_rx_delay) {\n+\t\tcase 1:\n+\t\t\tport_xmii |= RGMII_CTL_P0RDLY_1_5;\n+\t\t\tbreak;\n+\t\tcase 2:\n+\t\t\tport_xmii |= RGMII_CTL_P0RDLY_1_75;\n+\t\t\tbreak;\n+\t\tcase 3:\n+\t\t\tport_xmii |= RGMII_CTL_P0RDLY_2_0;\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\tif (!(port->flags & LTQ_ETH_PORT_PHY)) {\n+\t\t\tport_xmii |= (RGMII_CTL_P0SPD_1000 |\n+\t\t\t\t\tRGMII_CTL_P0DUP_FULL);\n+\t\t\tport_ctl |= P0_CTL_FLP;\n+\t\t}\n+\n+\t\tbreak;\n+\tcase PHY_INTERFACE_MODE_MII:\n+\t\tport_xmii = RGMII_CTL_P0IS_MII;\n+\n+\t\tif (!(port->flags & LTQ_ETH_PORT_PHY)) {\n+\t\t\tport_xmii |= (RGMII_CTL_P0SPD_100 |\n+\t\t\t\t\tRGMII_CTL_P0DUP_FULL);\n+\t\t\tport_ctl |= P0_CTL_FLP;\n+\t\t}\n+\n+\t\tbreak;\n+\tdefault:\n+\t\tbreak;\n+\t}\n+\n+\tif (port->num == 1) {\n+\t\tltq_writel(&switch_regs->p1_ctl, port_ctl);\n+\n+\t\trgmii_ctl &= ~RGMII_CTL_P1_MASK;\n+\t\trgmii_ctl |= (port_xmii << RGMII_CTL_P1_SHIFT);\n+\t} else {\n+\t\tltq_writel(&switch_regs->p0_ctl, port_ctl);\n+\n+\t\trgmii_ctl &= ~RGMII_CTL_P0_MASK;\n+\t\trgmii_ctl |= port_xmii;\n+\t}\n+\n+\tltq_writel(&switch_regs->rgmii_ctl, rgmii_ctl);\n+\n+\t/* Connect to external switch */\n+\tif (port->flags & LTQ_ETH_PORT_SWITCH) {\n+\t\tsw = switch_connect(priv->bus);\n+\t\tif (sw)\n+\t\t\tswitch_setup(sw);\n+\t}\n+\n+\t/* Connect to internal/external PHYs */\n+\tif (port->flags & LTQ_ETH_PORT_PHY) {\n+\t\tphydev = phy_connect(priv->bus, port->phy_addr, priv->dev,\n+\t\t\t\t\tport->phy_if);\n+\t\tif (phydev)\n+\t\t\tphy_config(phydev);\n+\n+\t\tpriv->phymap[port->num] = phydev;\n+\t}\n+}\n+\n+int ltq_eth_initialize(const struct ltq_eth_board_config *board_config)\n+{\n+\tstruct eth_device *dev;\n+\tstruct mii_dev *bus;\n+\tstruct ltq_eth_priv *priv;\n+\tstruct ltq_dma_device *dma_dev;\n+\tconst struct ltq_eth_port_config *port = &board_config->ports[0];\n+\tint i, ret;\n+\n+\tbuild_check_ar9_registers();\n+\n+\tltq_dma_init();\n+\tltq_eth_hw_init(port);\n+\n+\tdev = calloc(1, sizeof(*dev));\n+\tif (!dev)\n+\t\treturn -1;\n+\n+\tpriv = calloc(1, sizeof(*priv));\n+\tif (!priv)\n+\t\treturn -1;\n+\n+\tbus = mdio_alloc();\n+\tif (!bus)\n+\t\treturn -1;\n+\n+\tsprintf(dev->name, LTQ_ETH_DRV_NAME);\n+\tdev->priv = priv;\n+\tdev->init = ltq_eth_init;\n+\tdev->halt = ltq_eth_halt;\n+\tdev->recv = ltq_eth_recv;\n+\tdev->send = ltq_eth_send;\n+\n+\tsprintf(bus->name, LTQ_MDIO_DRV_NAME);\n+\tbus->read = ltq_mdio_read;\n+\tbus->write = ltq_mdio_write;\n+\tbus->priv = priv;\n+\n+\tdma_dev = &priv->dma_dev;\n+\tdma_dev->port = 0;\n+\tdma_dev->rx_chan.chan_no = 0;\n+\tdma_dev->rx_chan.class = 0;\n+\tdma_dev->rx_chan.num_desc = LTQ_ETH_RX_BUFFER_CNT;\n+\tdma_dev->rx_endian_swap = LTQ_DMA_ENDIANESS_B3_B2_B1_B0;\n+\tdma_dev->rx_burst_len = LTQ_DMA_BURST_2WORDS;\n+\tdma_dev->tx_chan.chan_no = 1;\n+\tdma_dev->tx_chan.class = 0;\n+\tdma_dev->tx_chan.num_desc = LTQ_ETH_TX_BUFFER_CNT;\n+\tdma_dev->tx_endian_swap = LTQ_DMA_ENDIANESS_B3_B2_B1_B0;\n+\tdma_dev->tx_burst_len = LTQ_DMA_BURST_2WORDS;\n+\n+\tpriv->bus = bus;\n+\tpriv->dev = dev;\n+\n+\tret = ltq_dma_register(dma_dev);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = mdio_register(bus);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = eth_register(dev);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tfor (i = 0; i < board_config->num_ports; i++)\n+\t\tltq_eth_port_config(priv, &board_config->ports[i]);\n+\n+\treturn 0;\n+}\n"
  },
  {
    "path": "package/boot/uboot-lantiq/patches/0017-tools-add-some-helper-tools-for-Lantiq-SoCs.patch",
    "content": "From 1da5479d59b39d7931a2b0efabdfa314f6788b6d Mon Sep 17 00:00:00 2001\nFrom: Luka Perkov <luka@openwrt.org>\nDate: Sat, 2 Mar 2013 23:34:00 +0100\nSubject: tools: add some helper tools for Lantiq SoCs\n\nSigned-off-by: Luka Perkov Luka Perkov <luka@openwrt.org>\nSigned-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>\n\n--- /dev/null\n+++ b/tools/gct.pl\n@@ -0,0 +1,155 @@\n+#!/usr/bin/perl\n+\n+#use strict;\n+#use Cwd;\n+#use Env;\n+\n+my $aline;\n+my $lineid;\n+my $length;\n+my $address;\n+my @bytes;\n+my $addstr;\n+my $chsum=0;\n+my $count=0;\n+my $firstime=1;\n+my $i;\n+my $currentaddr;\n+my $tmp;\n+my $holder=\"\";\n+my $loadaddr;\n+\n+if(@ARGV < 2){\n+\tdie(\"\\n Syntax: perl gct.pl uart_ddr_settings.conf u-boot.srec u-boot.asc\\n\");\n+}\n+\n+open(IN_UART_DDR_SETTINGS, \"<$ARGV[0]\") || die(\"failed to open uart_ddr_settings.conf\\n\");\n+open(IN_UART_SREC, \"<$ARGV[1]\") || die(\"failed to open u-boot.srec\\n\");\n+open(OUT_UBOOT_ASC, \">$ARGV[2]\") || die(\"failed to open u-boot.asc\\n\");\n+\n+$i=0;\n+while ($line = <IN_UART_DDR_SETTINGS>){\n+\tif($line=~/\\w/){\n+\t\tif($line!~/[;#\\*]/){\n+\t\t\tif($i eq 0){\n+\t\t\t\tprintf OUT_UBOOT_ASC (\"33333333\");\n+\t\t\t}\n+\t\t\tchomp($line);\n+\t\t\t$line=~s/\\t//;\n+\t\t\t@array=split(/ +/,$line);\n+\t\t\t$j=0;\n+\t\t\twhile(@array[$j]!~/\\w/){\n+\t\t\t\t$j=$j+1;\n+\t\t\t}\n+\t\t\t$addr=@array[$j];\n+\t\t\t$regval=@array[$j+1];\n+\t\t\t$addr=~s/0x//;\n+\t\t\t$regval=~s/0x//;\n+\t\t\tprintf OUT_UBOOT_ASC (\"%08x%08x\",hex($addr),hex($regval));\n+\t\t\t$i=$i+1;\n+\t\t\tif($i eq 8){\n+\t\t\t\t$i=0;\n+\t\t\t\tprintf OUT_UBOOT_ASC (\"\\n\");\n+\t\t\t}\n+\t\t}\n+\t}\n+}\n+\n+while($i lt 8 && $i gt 0){\n+\tprintf OUT_UBOOT_ASC \"00\"x8;\n+\t$i=$i+1;\n+}\n+\n+if($i eq 8){\n+\tprintf OUT_UBOOT_ASC (\"\\n\");\n+}\n+\n+while($aline=<IN_UART_SREC>){\n+\t$aline=uc($aline);\n+\tchomp($aline);\n+\tnext if(($aline=~/^S0/) || ($aline=~/^S7/));\n+\t($lineid, $length, $address, @bytes) = unpack\"A2A2A8\".\"A2\"x300, $aline;\n+\t$length = hex($length);\n+\t$address = hex($address);\n+\t$length -=5;\n+\t$i=0;\n+\n+\twhile($length>0){\n+\t\tif($firstime==1){\n+\t\t\t$addstr = sprintf(\"%x\", $address);\n+\t\t\t$addstr = \"0\"x(8-length($addstr)).$addstr;\n+\t\t\tprint OUT_UBOOT_ASC $addstr;\n+\t\t\taddchsum($addstr);\n+\t\t\t$firstime=0;\n+\t\t\t$currentaddr=$address;\n+\t\t\t$loadaddr = $addstr;\n+\t\t}\n+\t\telse{\n+\t\t\tif($count==64){\n+\t\t\t\t$addstr = sprintf(\"%x\", $currentaddr);\n+\t\t\t\t$addstr = \"0\"x(8-length($addstr)).$addstr;\n+\t\t\t\tprint OUT_UBOOT_ASC $addstr;\n+\t\t\t\taddchsum($addstr);\n+\t\t\t\t$count=0;\n+\t\t\t}\n+#printf(\"*** %x != %x\\n\", $address, $currentaddr) if $address != $currentaddr;\n+\t\t}\n+\t\tif($currentaddr < $address) {\n+\t\t\tprint OUT_UBOOT_ASC \"00\";\n+\t\t\taddchsum(\"00\");\n+\t\t\t$count++;\n+\t\t\t$currentaddr++;\n+\t\t}\n+\t\telse {\n+\t\t\twhile($count<64){\n+\t\t\t\t$bytes[$i]=~tr/ABCDEF/abcdef/;\n+\t\t\t\tprint OUT_UBOOT_ASC \"$bytes[$i]\";\n+\t\t\t\taddchsum($bytes[$i]);\n+\t\t\t\t$i++;\n+\t\t\t\t$count++;\n+\t\t\t\t$currentaddr++;\n+\t\t\t\t$length--;\n+\t\t\t\tlast if($length==0);\n+\t\t\t}\n+\t\t}\n+\t\tif($count==64){\n+\t\t\tprint OUT_UBOOT_ASC \"\\n\";\n+\t\t}\n+\t}\n+}\n+if($count != 64){\n+\t$tmp = \"00\";\n+\tfor($i=0;$i<(64-$count);$i++){\n+\t\tprint OUT_UBOOT_ASC \"00\";\n+\t\taddchsum($tmp);\n+\t}\n+\tprint OUT_UBOOT_ASC \"\\n\";\n+}\n+\n+\n+print OUT_UBOOT_ASC \"11\"x4;\n+use integer;\n+$chsum=$chsum & 0xffffffff;\n+$chsum = sprintf(\"%X\", $chsum);\n+$chsum = \"0\"x(8-length($chsum)).$chsum;\n+$chsum =~tr/ABCDEF/abcdef/;\n+print OUT_UBOOT_ASC $chsum;\n+print OUT_UBOOT_ASC \"00\"x60;\n+print OUT_UBOOT_ASC \"\\n\";\n+\n+print OUT_UBOOT_ASC \"99\"x4;\n+print OUT_UBOOT_ASC $loadaddr;\n+print OUT_UBOOT_ASC \"00\"x60;\n+print OUT_UBOOT_ASC \"\\n\";\n+\n+close OUT_UBOOT_ASC;\n+\n+sub addchsum{\n+\tmy $cc=$_[0];\n+\t$holder=$holder.$cc;\n+\tif(length($holder)==8){\n+\t\t$holder = hex($holder);\n+\t\t$chsum+=$holder;\n+\t\t$holder=\"\";\n+\t}\n+}\n--- /dev/null\n+++ b/tools/lantiq_bdi_conf.awk\n@@ -0,0 +1,116 @@\n+#!/usr/bin/awk -f\n+#\n+# Copyright (C) 2013 Luka Perkov <luka@openwrt.org>\n+# Copyright (C) 2013 Daniel Schwierzeck <daniel.schwierzeck@gmail.com>\n+#\n+# Usage:\n+#  awk -f lantiq_bdi_conf.awk -v soc=ar9 board=<name> PATH_TO_BOARD/ddr_settings.h\n+#\n+# Additional information:\n+#  http://www.abatron.ch/fileadmin/user_upload/products/pdf/ManGDBR4K-3000.pdf\n+#\n+# SPDX-License-Identifier:\tGPL-2.0+\n+#\n+\n+function print_header()\n+{\n+\tprint \";                                                                         \"\n+\tprint \"; Copyright (C) 2013 Luka Perkov <luka@openwrt.org>                       \"\n+\tprint \"; Copyright (C) 2013 Daniel Schwierzeck <daniel.schwierzeck@gmail.com>    \"\n+\tprint \";                                                                         \"\n+\tprint \"; This file has been generated with lantiq_bdi_conf.awk script.           \"\n+\tprint \";                                                                         \"\n+\tprint \"; SPDX-License-Identifier:\tGPL-2.0+                                 \"\n+\tprint \";                                                                         \"\n+\tprint \"\"\n+}\n+\n+function init_ar9_prologue()\n+{\n+\tprint \"WM32 0xBF103010 0x80\t\t; CGU for CPU 333Mhz, DDR 167Mhz\"\n+\tprint \"WM32 0xBF103014 0x01\t\t; CGU update\"\n+\tprint \"WM32 0xBF800010 0x0\t\t; Clear error access log register\"\n+\tprint \"WM32 0xBF800020 0x0\t\t; Clear error access log register\"\n+\tprint \"WM32 0xBF800060 0xD\t\t; Enable FPI, DDR and SRAM module in memory controller\"\n+\tprint \"WM32 0xBF801030 0x0\t\t; Clear start bit of DDR memory controller\"\n+}\n+\n+function init_ar9_epilogue()\n+{\n+\tprint \"WM32 0xBE105360 0x4001D7FF\t; EBU setup\"\n+}\n+\n+function init_ddr1_epilogue()\n+{\n+\tprint \"WM32 0xBF801030 0x100\t\t; Set start bit of DDR memory controller\"\n+}\n+\n+function ar9_target()\n+{\n+\tprint \"CPUTYPE\t\tM34K\"\n+\tprint \"ENDIAN\t\tBIG\"\n+\tprint \"JTAGCLOCK\t1\"\n+\tprint \"BDIMODE\t\tAGENT\t\t; [ LOADONLY, AGENT ]\"\n+\tprint \"RESET\t\tJTAG\t\t; [ NONE, JTAG, HARD ]\"\n+\tprint \"POWERUP\t\t100\"\n+\tprint \"WAKEUP\t\t100\"\n+\tprint \"BREAKMODE\tHARD\t\t; [ SOFT, HARD ]\"\n+\tprint  \"STEPMODE\tSWBP\t\t; [ JTAG, HWBP, SWBP ]\"\n+\tprint \"VECTOR\t\tCATCH\"\n+\tprint  \"SCANSUCC\t1 5\"\n+}\n+\n+function flash_p2601hnfx()\n+{\n+\tprint \"CHIPTYPE\tMIRRORX16\"\n+\tprint \"CHIPSIZE\t0x1000000\"\n+\tprint \"BUSWIDTH\t16\"\n+}\n+\n+BEGIN {\n+\tswitch (soc) {\n+\tcase \"ar9\":\n+\t\treg_base = 0xbf801000\n+\t\tprint_header()\n+\t\tprint \"[INIT]\"\n+\t\tinit_ar9_prologue()\n+\t\tbreak\n+\tdefault:\n+\t\tprint \"Invalid or no value for SoC specified!\"\n+\t\texit 1\n+\t}\n+}\n+\n+/^#define/ {\n+\t/* DC03 contains MC enable bit and must not be set here */\n+\tif (tolower($2) != \"mc_dc03_value\")\n+\t\tprintf(\"WM32 0x%x %s\\n\", reg_base, tolower($3))\n+\n+\treg_base += 0x10\n+}\n+\n+END {\n+\tswitch (soc) {\n+\tcase \"ar9\":\n+\t\tinit_ddr1_epilogue()\n+\t\tinit_ar9_epilogue()\n+\t\tprint \"\"\n+\t\tprint \"[TARGET]\"\n+\t\tar9_target()\n+\t\tprint \"\"\n+\t\tprint \"[HOST]\"\n+\t\tprint \"PROMPT\t\t\\\"ar9> \\\"\"\n+\t\tprint \"\"\n+\t\tbreak\n+\tdefault:\n+\t}\n+\n+\tswitch (board) {\n+\tcase \"p2601hnfx\":\n+\t\tprint \"[FLASH]\"\n+\t\tflash_p2601hnfx()\n+\t\tprint \"\"\n+\t\tbreak\n+\tdefault:\n+\t}\n+}\n--- /dev/null\n+++ b/tools/lantiq_ram_extract_magic.awk\n@@ -0,0 +1,69 @@\n+#\n+# Copyright (C) 2011-2013 Luka Perkov <luka@openwrt.org>\n+#\n+# Usage:\n+# mips-openwrt-linux-objdump -EB -b binary -m mips:isa32r2 -D YOUR_IMAGE_DUMP | awk -f lantiq_ram_extract_magic.awk\n+#\n+# SPDX-License-Identifier:\tGPL-2.0+\n+#\n+\n+BEGIN {\n+\tprint \"/*                                                                            \"\n+\tprint \" * Copyright (C) 2011-2013 Luka Perkov <luka@openwrt.org>                     \"\n+\tprint \" *                                                                            \"\n+\tprint \" * This file has been generated with lantiq_ram_extract_magic.awk script.     \"\n+\tprint \" *                                                                            \"\n+\tprint \" * SPDX-License-Identifier:\tGPL-2.0+                                     \"\n+\tprint \" */                                                                           \"\n+\tprint \"\"\n+\n+\tmc_dc_value=0\n+\tmc_dc_number=0\n+\tright_section=0\n+\tmc_dc_value_print=0\n+\tmc_dc_number_print=0\n+}\n+\n+/t2,[0-9]+$/ {\n+\tif (right_section) {\n+\t\tsplit($4, tmp, \",\")\n+\t\tmc_dc_value=sprintf(\"%X\", tmp[2])\n+\t\tmc_dc_value_print=1\n+\t}\n+}\n+\n+/t2,0x[0-9a-f]+$/ {\n+\tif (right_section) {\n+\t\tsplit($4, tmp, \",0x\")\n+\t\tmc_dc_value=sprintf(\"%s\", tmp[2])\n+\t\tmc_dc_value=toupper(mc_dc_value)\n+\t\tmc_dc_value_print=1\n+\t}\n+}\n+\n+/t2,[0-9]+\\(t1\\)$/ {\n+\tif (right_section) {\n+\t\tsplit($4, tmp, \",\")\n+\t\tsplit(tmp[2], tmp, \"(\")\n+\t\tmc_dc_number=tmp[1]/16\n+\t\tmc_dc_number_print=1\n+\t}\n+}\n+\n+{\n+\tif (right_section && mc_dc_number_print && mc_dc_value_print) {\n+\t\tif (mc_dc_number < 10)\n+\t\t\tprint \"#define MC_DC0\" mc_dc_number \"_VALUE\\t0x\" mc_dc_value\n+\t\telse\n+\t\t\tprint \"#define MC_DC\" mc_dc_number \"_VALUE\\t0x\" mc_dc_value\n+\t\tmc_dc_value_print=0\n+\t\tmc_dc_number_print=0\n+\t}\n+\n+\tif ($4 == \"t1,t1,0x1000\")\n+\t\tright_section=1\n+\n+\n+\tif ($4 == \"t2,736(t1)\")\n+\t\tright_section=0\n+}\n--- /dev/null\n+++ b/tools/lantiq_ram_init_uart.awk\n@@ -0,0 +1,117 @@\n+#!/usr/bin/awk -f\n+#\n+# Copyright (C) 2011-2012 Luka Perkov <luka@openwrt.org>\n+# Copyright (C) 2012 Daniel Schwierzeck <daniel.schwierzeck@gmail.com>\n+#\n+# Usage:\n+# awk -f lantiq_ram_init_uart.awk -v soc=<danube|ar9|vr9> PATH_TO_BOARD/ddr_settings.h\n+#\n+# SPDX-License-Identifier:\tGPL-2.0+\n+#\n+\n+function print_header()\n+{\n+\tprint \";                                                                            \"\n+\tprint \"; Copyright (C) 2011-2013 Luka Perkov <luka@openwrt.org>                     \"\n+\tprint \"; Copyright (C) 2012-2013 Daniel Schwierzeck <daniel.schwierzeck@gmail.com>  \"\n+\tprint \";                                                                            \"\n+\tprint \"; This file has been generated with lantiq_ram_init_uart.awk script.         \"\n+\tprint \";                                                                            \"\n+\tprint \"; SPDX-License-Identifier:\tGPL-2.0+                                    \"\n+\tprint \"\"\n+}\n+\n+function mc_danube_prologue()\n+{\n+\t/* Clear access error log registers */\n+\tprint \"0xbf800010\", \"0x0\"\n+\tprint \"0xbf800020\", \"0x0\"\n+\n+\t/* Enable DDR and SRAM module in memory controller */\n+\tprint \"0xbf800060\", \"0x5\"\n+\n+\t/* Clear start bit of DDR memory controller */\n+\tprint \"0xbf801030\", \"0x0\"\n+}\n+\n+function mc_ar9_prologue()\n+{\n+\t/* Clear access error log registers */\n+\tprint \"0xbf800010\", \"0x0\"\n+\tprint \"0xbf800020\", \"0x0\"\n+\n+\t/* Enable FPI, DDR and SRAM module in memory controller */\n+\tprint \"0xbf800060\", \"0xD\"\n+\n+\t/* Clear start bit of DDR memory controller */\n+\tprint \"0xbf801030\", \"0x0\"\n+}\n+\n+function mc_ddr1_epilogue()\n+{\n+\t/* Set start bit of DDR memory controller */\n+\tprint \"0xbf801030\", \"0x100\"\n+}\n+\n+function mc_ddr2_prologue()\n+{\n+\t/* Put memory controller in inactive mode */\n+\tprint \"0xbf401070\", \"0x0\"\n+}\n+\n+function mc_ddr2_epilogue(mc_ccr07_value)\n+{\n+\t/* Put memory controller in active mode */\n+\tmc_ccr07_value = or(mc_ccr07_value, 0x100)\n+\tprintf(\"0xbf401070 0x%x\\n\", mc_ccr07_value)\n+}\n+\n+BEGIN {\n+\tswitch (soc) {\n+\tcase \"danube\":\n+\t\treg_base = 0xbf801000\n+\t\tprint_header()\n+\t\tmc_danube_prologue()\n+\t\tbreak\n+\tcase \"ar9\":\n+\t\treg_base = 0xbf801000\n+\t\tprint_header()\n+\t\tmc_ar9_prologue()\n+\t\tbreak\n+\tcase \"vr9\":\n+\t\treg_base = 0xbf401000\n+\t\tprint_header()\n+\t\tmc_ddr2_prologue()\n+\t\tbreak\n+\tdefault:\n+\t\tprint \"Invalid or no value for soc specified!\"\n+\t\texit 1\n+\t}\n+\n+\tmc_ccr07_value = 0\n+}\n+\n+/^#define/ {\n+\t/* CCR07 contains MC enable bit and must not be set here */\n+\tif (tolower($2) == \"mc_ccr07_value\")\n+\t\tmc_ccr07_value = strtonum($3)\n+\tif (tolower($2) == \"mc_dc03_value\")\n+\t\t/* CCR07 contains MC enable bit and must not be set here */\n+\telse\n+\t\tprintf(\"0x%x %s\\n\", reg_base, tolower($3))\n+\n+\treg_base += 0x10\n+}\n+\n+END {\n+\tswitch (soc) {\n+\tcase \"danube\":\n+\tcase \"ar9\":\n+\t\tmc_ddr1_epilogue()\n+\t\tbreak\n+\tcase \"vr9\":\n+\t\tmc_ddr2_epilogue(mc_ccr07_value)\n+\t\tbreak\n+\tdefault:\n+\t}\n+}\n"
  },
  {
    "path": "package/boot/uboot-lantiq/patches/0018-tools-lantiq-add-NAND-SPL-support.patch",
    "content": "From 43b9a7c9b903302c56d0a1d292a146dbf4de8e49 Mon Sep 17 00:00:00 2001\nFrom: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>\nDate: Mon, 12 Aug 2013 01:17:08 +0200\nSubject: tools: lantiq: add NAND SPL support\n\nSigned-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>\n\n--- a/tools/ltq-boot-image.c\n+++ b/tools/ltq-boot-image.c\n@@ -14,7 +14,8 @@\n \n enum image_types {\n \tIMAGE_NONE,\n-\tIMAGE_SFSPL\n+\tIMAGE_SFSPL,\n+\tIMAGE_NANDSPL\n };\n \n /* Lantiq non-volatile bootstrap command IDs */\n@@ -43,6 +44,8 @@ enum nvb_cmd_flags {\n struct args {\n \tenum image_types type;\n \t__u32\t\tentry_addr;\n+\toff_t\t\tuboot_offset;\n+\tunsigned int\tpage_size;\n \tconst char\t*uboot_bin;\n \tconst char\t*spl_bin;\n \tconst char\t*out_bin;\n@@ -50,10 +53,11 @@ struct args {\n \n static void usage_msg(const char *name)\n {\n-\tfprintf(stderr, \"%s: [-h] -t type -e entry-addr -u uboot-bin [-s spl-bin] -o out-bin\\n\",\n+\tfprintf(stderr, \"%s: [-h] -t type -e entry-addr [-x uboot-offset] [-p page-size] -u uboot-bin [-s spl-bin] -o out-bin\\n\",\n \t\tname);\n \tfprintf(stderr, \" Image types:\\n\"\n-\t\t\t\"  sfspl  - SPL + [compressed] U-Boot for SPI flash\\n\");\n+\t\t\t\"  sfspl   - SPL + [compressed] U-Boot for SPI flash\\n\"\n+\t\t\t\"  nandspl - SPL + [compressed] U-Boot for NAND flash\\n\");\n }\n \n static enum image_types parse_image_type(const char *type)\n@@ -64,6 +68,9 @@ static enum image_types parse_image_type\n \tif (!strncmp(type, \"sfspl\", 6))\n \t\treturn IMAGE_SFSPL;\n \n+\tif (!strncmp(type, \"nandspl\", 6))\n+\t\treturn IMAGE_NANDSPL;\n+\n \treturn IMAGE_NONE;\n }\n \n@@ -73,7 +80,7 @@ static int parse_args(int argc, char *ar\n \n \tmemset(arg, 0, sizeof(*arg));\n \n-\twhile ((opt = getopt(argc, argv, \"ht:e:u:s:o:\")) != -1) {\n+\twhile ((opt = getopt(argc, argv, \"ht:e:x:p:u:s:o:\")) != -1) {\n \t\tswitch (opt) {\n \t\tcase 'h':\n \t\t\tusage_msg(argv[0]);\n@@ -84,6 +91,12 @@ static int parse_args(int argc, char *ar\n \t\tcase 'e':\n \t\t\targ->entry_addr = strtoul(optarg, NULL, 16);\n \t\t\tbreak;\n+\t\tcase 'x':\n+\t\t\targ->uboot_offset = strtoul(optarg, NULL, 16);\n+\t\t\tbreak;\n+\t\tcase 'p':\n+\t\t\targ->page_size = strtoul(optarg, NULL, 10);\n+\t\t\tbreak;\n \t\tcase 'u':\n \t\t\targ->uboot_bin = optarg;\n \t\t\tbreak;\n@@ -114,11 +127,22 @@ static int parse_args(int argc, char *ar\n \t\tgoto parse_error;\n \t}\n \n-\tif (arg->type == IMAGE_SFSPL && !arg->spl_bin) {\n+\tif ((arg->type == IMAGE_SFSPL || arg->type == IMAGE_NANDSPL) &&\n+\t\t!arg->spl_bin) {\n \t\tfprintf(stderr, \"Missing SPL binary\\n\");\n \t\tgoto parse_error;\n \t}\n \n+\tif (arg->type == IMAGE_NANDSPL && !arg->uboot_offset) {\n+\t\tfprintf(stderr, \"Missing U-Boot offset\\n\");\n+\t\tgoto parse_error;\n+\t}\n+\n+\tif (arg->type == IMAGE_NANDSPL && !arg->page_size) {\n+\t\tfprintf(stderr, \"Missing NAND page size\\n\");\n+\t\tgoto parse_error;\n+\t}\n+\n \treturn 0;\n \n parse_error:\n@@ -174,6 +198,19 @@ static int write_nvb_start_header(int fd\n \treturn write_header(fd, hdr, sizeof(hdr));\n }\n \n+#if 0\n+static int write_nvb_regcfg_header(int fd, __u32 addr)\n+{\n+\t__u32 hdr[2];\n+\n+\thdr[0] = build_nvb_command(NVB_CMD_REGCFG, NVB_FLAG_SDBG |\n+\t\t\t\t\tNVB_FLAG_DBG);\n+\thdr[1] = cpu_to_be32(addr);\n+\n+\treturn write_header(fd, hdr, sizeof(hdr));\n+}\n+#endif\n+\n static int open_input_bin(const char *name, void **ptr, size_t *size)\n {\n \tstruct stat sbuf;\n@@ -238,9 +275,37 @@ static int open_output_bin(const char *n\n \treturn fd;\n }\n \n-static int create_sfspl(const struct args *arg)\n+static int pad_to_offset(int fd, off_t offset)\n {\n-\tint out_fd, uboot_fd, spl_fd, ret;\n+\toff_t pos;\n+\tsize_t size;\n+\tssize_t n;\n+\t__u8 *buf;\n+\n+\tpos = lseek(fd, 0, SEEK_CUR);\n+\tsize = offset - pos;\n+\n+\tbuf = malloc(size);\n+\tif (!buf) {\n+\t\tfprintf(stderr, \"Failed to malloc buffer\\n\");\n+\t\treturn -1;\n+\t}\n+\n+\tmemset(buf, 0xff, size);\n+\tn = write(fd, buf, size);\n+\tfree(buf);\n+\n+\tif (n != size) {\n+\t\tfprintf(stderr, \"Failed to write pad bytes\\n\");\n+\t\treturn -1;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int create_spl_image(const struct args *arg)\n+{\n+\tint out_fd, uboot_fd, spl_fd, ret = 0;\n \tvoid *uboot_ptr, *spl_ptr;\n \tsize_t uboot_size, spl_size;\n \n@@ -256,9 +321,22 @@ static int create_sfspl(const struct arg\n \tif (0 > uboot_fd)\n \t\tgoto err_uboot;\n \n+#if 0\n+\tret = write_nvb_regcfg_header(out_fd, 0);\n+\tif (ret)\n+\t\tgoto err_write;\n+#endif\n+\n \tret = write_nvb_dwnld_header(out_fd, spl_size, arg->entry_addr);\n \tif (ret)\n \t\tgoto err_write;\n+#if 0\n+\tif (arg->page_size) {\n+\t\tret = pad_to_offset(out_fd, arg->page_size);\n+\t\tif (ret)\n+\t\t\tgoto err_write;\n+\t}\n+#endif\n \n \tret = copy_bin(out_fd, spl_ptr, spl_size);\n \tif (ret)\n@@ -268,16 +346,16 @@ static int create_sfspl(const struct arg\n \tif (ret)\n \t\tgoto err_write;\n \n+\tif (arg->uboot_offset) {\n+\t\tret = pad_to_offset(out_fd, arg->uboot_offset);\n+\t\tif (ret)\n+\t\t\tgoto err_write;\n+\t}\n+\n \tret = copy_bin(out_fd, uboot_ptr, uboot_size);\n \tif (ret)\n \t\tgoto err_write;\n \n-\tclose_input_bin(uboot_fd, uboot_ptr, uboot_size);\n-\tclose_input_bin(spl_fd, spl_ptr, spl_size);\n-\tclose(out_fd);\n-\n-\treturn 0;\n-\n err_write:\n \tclose_input_bin(uboot_fd, uboot_ptr, uboot_size);\n err_uboot:\n@@ -285,7 +363,7 @@ err_uboot:\n err_spl:\n \tclose(out_fd);\n err:\n-\treturn -1;\n+\treturn ret;\n }\n \n int main(int argc, char *argv[])\n@@ -299,7 +377,8 @@ int main(int argc, char *argv[])\n \n \tswitch (arg.type) {\n \tcase IMAGE_SFSPL:\n-\t\tret = create_sfspl(&arg);\n+\tcase IMAGE_NANDSPL:\n+\t\tret = create_spl_image(&arg);\n \t\tbreak;\n \tdefault:\n \t\tfprintf(stderr, \"Image type not implemented\\n\");\n"
  },
  {
    "path": "package/boot/uboot-lantiq/patches/0019-Makefile-add-Lantiq-NAND-SPL-images.patch",
    "content": "From 2e01dc015bc8bb9ca45f369025c342ede990863e Mon Sep 17 00:00:00 2001\nFrom: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>\nDate: Mon, 12 Aug 2013 01:16:09 +0200\nSubject: Makefile: add Lantiq NAND SPL images\n\nSigned-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>\n\n--- a/.gitignore\n+++ b/.gitignore\n@@ -54,6 +54,9 @@\n /u-boot.ltq.lzma.norspl\n /u-boot.ltq.lzo.norspl\n /u-boot.ltq.norspl\n+/u-boot.ltq.lzma.nandspl\n+/u-boot.ltq.lzo.nandspl\n+/u-boot.ltq.nandspl\n /u-boot.lzma.img\n /u-boot.lzo.img\n \n--- a/Makefile\n+++ b/Makefile\n@@ -599,6 +599,24 @@ $(obj)u-boot.ltq.lzma.sfspl: $(obj)u-boo\n \t\t$(obj)tools/ltq-boot-image -t sfspl -e $(CONFIG_SPL_TEXT_BASE) \\\n \t\t\t-s $(obj)spl/u-boot-spl.bin -u $< -o $@\n \n+$(obj)u-boot.ltq.nandspl:\t$(obj)u-boot.img $(obj)spl/u-boot-spl.bin\n+\t\t$(obj)tools/ltq-boot-image -t nandspl -e $(CONFIG_SPL_TEXT_BASE) \\\n+\t\t\t-x $(CONFIG_SYS_NAND_U_BOOT_OFFS) \\\n+\t\t\t-p $(CONFIG_SYS_NAND_PAGE_SIZE) \\\n+\t\t\t-s $(obj)spl/u-boot-spl.bin -u $< -o $@\n+\n+$(obj)u-boot.ltq.lzo.nandspl: $(obj)u-boot.lzo.img $(obj)spl/u-boot-spl.bin\n+\t\t$(obj)tools/ltq-boot-image -t nandspl -e $(CONFIG_SPL_TEXT_BASE) \\\n+\t\t\t-x $(CONFIG_SYS_NAND_U_BOOT_OFFS) \\\n+\t\t\t-p $(CONFIG_SYS_NAND_PAGE_SIZE) \\\n+\t\t\t-s $(obj)spl/u-boot-spl.bin -u $< -o $@\n+\n+$(obj)u-boot.ltq.lzma.nandspl: $(obj)u-boot.lzma.img $(obj)spl/u-boot-spl.bin\n+\t\t$(obj)tools/ltq-boot-image -t nandspl -e $(CONFIG_SPL_TEXT_BASE) \\\n+\t\t\t-x $(CONFIG_SYS_NAND_U_BOOT_OFFS) \\\n+\t\t\t-p $(CONFIG_SYS_NAND_PAGE_SIZE) \\\n+\t\t\t-s $(obj)spl/u-boot-spl.bin -u $< -o $@\n+\n $(obj)u-boot.ltq.norspl: $(obj)u-boot.img $(obj)spl/u-boot-spl.bin\n \tcat $(obj)spl/u-boot-spl.bin $< > $@\n \n"
  },
  {
    "path": "package/boot/uboot-lantiq/patches/0020-MIPS-lantiq-add-NAND-SPL-support.patch",
    "content": "From e17398316e82d8b28217232b4fd6030c65138e74 Mon Sep 17 00:00:00 2001\nFrom: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>\nDate: Mon, 12 Aug 2013 01:18:00 +0200\nSubject: MIPS: lantiq: add NAND SPL support\n\nSigned-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>\n\n--- a/arch/mips/cpu/mips32/lantiq-common/spl.c\n+++ b/arch/mips/cpu/mips32/lantiq-common/spl.c\n@@ -8,6 +8,7 @@\n #include <image.h>\n #include <version.h>\n #include <spi_flash.h>\n+#include <nand.h>\n #include <linux/compiler.h>\n #include <lzma/LzmaDec.h>\n #include <linux/lzo.h>\n@@ -63,6 +64,18 @@\n #define spl_boot_nor_flash\t0\n #endif\n \n+#if defined(CONFIG_LTQ_SUPPORT_SPL_NAND_FLASH) && defined(CONFIG_SYS_BOOT_NANDSPL)\n+#define spl_boot_nand_flash\t1\n+#else\n+#define spl_boot_nand_flash\t0\n+#ifndef CONFIG_SYS_NAND_U_BOOT_OFFS\n+#define CONFIG_SYS_NAND_U_BOOT_OFFS\t0\n+#endif\n+#ifndef CONFIG_SYS_NAND_PAGE_SIZE\n+#define CONFIG_SYS_NAND_PAGE_SIZE\t0\n+#endif\n+#endif\n+\n #define spl_sync()\t__asm__ __volatile__(\"sync\");\n \n struct spl_image {\n@@ -337,6 +350,58 @@ static int spl_load_nor_flash(struct spl\n \treturn ret;\n }\n \n+static int spl_load_nand_flash(struct spl_image *spl)\n+{\n+\timage_header_t *hdr;\n+\tint ret;\n+\tunsigned long loadaddr;\n+\n+\t/*\n+\t * Image format:\n+\t *\n+\t * - 12 byte non-volatile bootstrap header\n+\t * - SPL binary\n+\t * - 12 byte non-volatile bootstrap header\n+\t * - padding bytes up to CONFIG_SYS_NAND_U_BOOT_OFFS\n+\t * - 64 byte U-Boot mkimage header\n+\t * - U-Boot binary\n+\t */\n+\tspl->data_addr = CONFIG_SYS_NAND_U_BOOT_OFFS;\n+\n+\tspl_puts(\"SPL: initializing NAND flash\\n\");\n+\tnand_init();\n+\n+\tspl_debug(\"SPL: reading image header at page offset %lx\\n\",\n+\t\t  spl->data_addr);\n+\n+\thdr = (image_header_t *) CONFIG_LOADADDR;\n+\tret = nand_spl_load_image(spl->data_addr,\n+\t\t\t\t  CONFIG_SYS_NAND_PAGE_SIZE, hdr);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tspl_debug(\"SPL: checking image header at address %p\\n\", hdr);\n+\n+\tret = spl_parse_image(hdr, spl);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tif (spl_is_compressed(spl))\n+\t\tloadaddr = CONFIG_LOADADDR;\n+\telse\n+\t\tloadaddr = spl->entry_addr;\n+\n+\tspl_puts(\"SPL: loading U-Boot to RAM\\n\");\n+\n+\tret = nand_spl_load_image(spl->data_addr, spl->data_size,\n+\t\t\t\t  (void *) loadaddr);\n+\n+\tif (spl_is_compressed(spl))\n+\t\tret = spl_uncompress(spl, loadaddr);\n+\n+\treturn ret;\n+}\n+\n static int spl_load(struct spl_image *spl)\n {\n \tint ret;\n@@ -345,6 +410,8 @@ static int spl_load(struct spl_image *sp\n \t\tret = spl_load_spi_flash(spl);\n \telse if (spl_boot_nor_flash)\n \t\tret = spl_load_nor_flash(spl);\n+\telse if (spl_boot_nand_flash)\n+\t\tret = spl_load_nand_flash(spl);\n \telse\n \t\tret = 1;\n \n--- a/arch/mips/include/asm/lantiq/config.h\n+++ b/arch/mips/include/asm/lantiq/config.h\n@@ -40,6 +40,26 @@\n #define CONFIG_SPI_SPL_SIMPLE\n #endif\n \n+/*\n+ * NAND flash SPL\n+ * BOOT CFG 06 only (address cycle based probing, 2KB or 512B page size)\n+ */\n+#if defined(CONFIG_LTQ_SUPPORT_SPL_NAND_FLASH) && defined(CONFIG_SYS_BOOT_NANDSPL)\n+#define CONFIG_SPL\n+#define CONFIG_SPL_NAND_SUPPORT\n+#define CONFIG_SPL_NAND_DRIVERS\n+#define CONFIG_SPL_NAND_SIMPLE\n+#define CONFIG_SPL_NAND_ECC\n+\n+/* use software ECC until driver supports HW ECC */\n+#define CONFIG_SPL_NAND_SOFTECC\n+#define CONFIG_SYS_NAND_ECCSIZE\t\t256\n+#define CONFIG_SYS_NAND_ECCBYTES\t3\n+#define CONFIG_SYS_NAND_ECCPOS\t\t{40, 41, 42, 43, 44, 45, 46, 47, \\\n+\t\t\t\t\t48, 49, 50, 51, 52, 53, 54, 55, \\\n+\t\t\t\t\t56, 57, 58, 59, 60, 61, 62, 63}\n+#endif\n+\n #if defined(CONFIG_LTQ_SUPPORT_SPL_NOR_FLASH) && defined(CONFIG_SYS_BOOT_NORSPL)\n #define CONFIG_SPL\n #endif\n@@ -148,6 +168,21 @@\n #define CONFIG_ENV_LOAD_UBOOT_SF\n #endif\n \n+#if defined(CONFIG_LTQ_SUPPORT_NAND_FLASH)\n+#define CONFIG_ENV_WRITE_UBOOT_NAND\t\t\t\t\\\n+\t\"write-uboot-nand=\"\t\t\t\t\t\\\n+\t\"nand erase 0 $filesize && \"\t\t\t\t\\\n+\t\"nand write $fileaddr 0 $filesize\\0\"\n+\n+#define CONFIG_ENV_LOAD_UBOOT_NAND\t\t\t\t\t\t\\\n+\t\"load-uboot-nandspl=tftpboot u-boot.ltq.nandspl\\0\"\t\t\t\\\n+\t\"load-uboot-nandspl-lzo=tftpboot u-boot.ltq.lzo.nandspl\\0\"\t\t\\\n+\t\"load-uboot-nandspl-lzma=tftpboot u-boot.ltq.lzma.nandspl\\0\"\n+#else\n+#define CONFIG_ENV_WRITE_UBOOT_NAND\n+#define CONFIG_ENV_LOAD_UBOOT_NAND\n+#endif\n+\n #define CONFIG_ENV_LANTIQ_DEFAULTS\t\\\n \tCONFIG_ENV_CONSOLEDEV\t\t\\\n \tCONFIG_ENV_ADDCONSOLE\t\t\\\n@@ -159,6 +194,8 @@\n \tCONFIG_ENV_LOAD_UBOOT_NOR\t\\\n \tCONFIG_ENV_SF_PROBE\t\t\\\n \tCONFIG_ENV_WRITE_UBOOT_SF\t\\\n-\tCONFIG_ENV_LOAD_UBOOT_SF\n+\tCONFIG_ENV_LOAD_UBOOT_SF\t\\\n+\tCONFIG_ENV_WRITE_UBOOT_NAND\t\\\n+\tCONFIG_ENV_LOAD_UBOOT_NAND\n \n #endif /* __LANTIQ_CONFIG_H__ */\n"
  },
  {
    "path": "package/boot/uboot-lantiq/patches/0021-MIPS-vrx200-add-NAND-SPL-support.patch",
    "content": "From 7361581a1baaec43058f5b9350c32c7ac4e58064 Mon Sep 17 00:00:00 2001\nFrom: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>\nDate: Mon, 12 Aug 2013 00:11:16 +0200\nSubject: MIPS: vrx200: add NAND SPL support\n\nSigned-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>\n\n--- a/arch/mips/cpu/mips32/vrx200/config.mk\n+++ b/arch/mips/cpu/mips32/vrx200/config.mk\n@@ -27,4 +27,9 @@ ALL-y += $(obj)u-boot.ltq.norspl\n ALL-$(CONFIG_SPL_LZO_SUPPORT) += $(obj)u-boot.ltq.lzo.norspl\n ALL-$(CONFIG_SPL_LZMA_SUPPORT) += $(obj)u-boot.ltq.lzma.norspl\n endif\n+ifdef CONFIG_SYS_BOOT_NANDSPL\n+ALL-y += $(obj)u-boot.ltq.nandspl\n+ALL-$(CONFIG_SPL_LZO_SUPPORT) += $(obj)u-boot.ltq.lzo.nandspl\n+ALL-$(CONFIG_SPL_LZMA_SUPPORT) += $(obj)u-boot.ltq.lzma.nandspl\n+endif\n endif\n--- a/arch/mips/include/asm/arch-vrx200/config.h\n+++ b/arch/mips/include/asm/arch-vrx200/config.h\n@@ -167,7 +167,7 @@\n #define CONFIG_SYS_TEXT_BASE\t\t0xB0000000\n #endif\n \n-#if defined(CONFIG_SYS_BOOT_SFSPL)\n+#if defined(CONFIG_SYS_BOOT_SFSPL) || defined(CONFIG_SYS_BOOT_NANDSPL)\n #define CONFIG_SYS_TEXT_BASE\t\t0x80100000\n #define CONFIG_SPL_TEXT_BASE\t\t0xBE220000\n #endif\n"
  },
  {
    "path": "package/boot/uboot-lantiq/patches/0022-MIPS-lantiq-add-default-openwrt-config.patch",
    "content": "From 8f584936adad0fca8beece5f55eadcdcd02fad0a Mon Sep 17 00:00:00 2001\nFrom: Luka Perkov <luka@openwrt.org>\nDate: Sat, 17 Aug 2013 03:44:46 +0200\nSubject: MIPS: lantiq: add default openwrt config\n\nSigned-off-by: Luka Perkov <luka@openwrt.org>\nSigned-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>\n\n--- /dev/null\n+++ b/include/configs/openwrt-lantiq-common.h\n@@ -0,0 +1,40 @@\n+/*\n+ * Copyright (C) 2013 Luka Perkov <luka@openwrt.org>\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#ifndef __OPENWRT_LANTIQ_COMMON_H\n+#define __OPENWRT_LANTIQ_COMMON_H\n+\n+/* Commands */\n+#if defined(CONFIG_LTQ_SUPPORT_ETHERNET)\n+#define CONFIG_CMD_PING\n+#define CONFIG_CMD_TFTPPUT\n+#endif\n+\n+/* Compression */\n+#define CONFIG_LZMA\n+\n+/* Auto boot */\n+#define CONFIG_BOOTDELAY\t2\n+\n+/* Environment */\n+#if !defined(CONFIG_SYS_BOOT_RAM)\n+#define CONFIG_BOOTCOMMAND \\\n+\t\"bootm ${kernel_addr}\"\n+#endif\n+\n+/* Ethernet */\n+#if defined(CONFIG_LTQ_SUPPORT_ETHERNET)\n+#define CONFIG_ETHADDR\t\t00:01:02:03:04:05\n+#define CONFIG_SERVERIP\t\t192.168.1.2\n+#define CONFIG_IPADDR\t\t192.168.1.1\n+#endif\n+\n+/* Unnecessary */\n+#undef CONFIG_BOOTM_NETBSD\n+#undef CONFIG_BOOTM_PLAN9\n+#undef CONFIG_BOOTM_RTEMS\n+\n+#endif /* __OPENWRT_LANTIQ_COMMON_H */\n"
  },
  {
    "path": "package/boot/uboot-lantiq/patches/0023-lzma-fixup.patch",
    "content": "From: Antonios Vamporakis <ant@area128.com>\nDate: Tue, 31 Dec 2013 01:05:42 +0100\nSubject: [PATCH] lzma: fix buffer bound check error\n\nVariable uncompressedSize references the space available, while outSizeFull is\nthe actual expected uncompressed size. Using the wrong value causes LzmaDecode\nto return SZ_ERROR_INPUT_EOF. Problem was introduced in commit afca294. While\nat it add additional debug message.\n\nSigned-off-by: Antonios Vamporakis <ant@area128.com>\nCC: Kees Cook <keescook@chromium.org>\nCC: Simon Glass <sjg@chromium.org>\nCC: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>\nCC: Luka Perkov <luka@openwrt.org>\n---\n lib/lzma/LzmaTools.c | 5 ++++-\n 1 file changed, 4 insertions(+), 1 deletion(-)\n\n--- a/lib/lzma/LzmaTools.c\n+++ b/lib/lzma/LzmaTools.c\n@@ -102,7 +102,7 @@ int lzmaBuffToBuffDecompress (unsigned c\n         return SZ_ERROR_OUTPUT_EOF;\n \n     /* Decompress */\n-    outProcessed = *uncompressedSize;\n+    outProcessed = outSizeFull;\n \n     WATCHDOG_RESET();\n \n@@ -111,6 +111,9 @@ int lzmaBuffToBuffDecompress (unsigned c\n         inStream + LZMA_DATA_OFFSET, &compressedSize,\n         inStream, LZMA_PROPS_SIZE, LZMA_FINISH_END, &state, &g_Alloc);\n     *uncompressedSize = outProcessed;\n+\n+    debug(\"LZMA: Uncompresed ................ 0x%zx\\n\", outProcessed);\n+\n     if (res != SZ_OK)  {\n         return res;\n     }\n"
  },
  {
    "path": "package/boot/uboot-lantiq/patches/0024-Makefile-prepare-u-boot-lantiq-v2013.10-openwrt4.patch",
    "content": "From 7e2f79bc40b572763a4a1ed69f63aa2eaa6df254 Mon Sep 17 00:00:00 2001\nFrom: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>\nDate: Sun, 20 Oct 2013 19:39:17 +0200\nSubject: Makefile: prepare u-boot-lantiq-v2013.10-openwrt4\n\nSigned-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>\n\n--- a/Makefile\n+++ b/Makefile\n@@ -8,7 +8,7 @@\n VERSION = 2013\n PATCHLEVEL = 10\n SUBLEVEL =\n-EXTRAVERSION =\n+EXTRAVERSION = -openwrt4\n ifneq \"$(SUBLEVEL)\" \"\"\n U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)\n else\n"
  },
  {
    "path": "package/boot/uboot-lantiq/patches/0025-arx100-cgu-fixes.patch",
    "content": "From patchwork Tue Jan 20 11:28:45 2015\nContent-Type: text/plain; charset=\"utf-8\"\nMIME-Version: 1.0\nContent-Transfer-Encoding: 7bit\nSubject: [OpenWrt-Devel] uboot-lantiq cgu settings for ramboot image\nFrom: Ben Mulvihill <ben.mulvihill@gmail.com>\nX-Patchwork-Id: 431024\nMessage-Id: <1421753325.25187.58.camel@merveille.lan>\nTo: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>\nCc: OpenWrt Development List <openwrt-devel@lists.openwrt.org>\nDate: Tue, 20 Jan 2015 12:28:45 +0100\n\nOn Tue, 2015-01-20 at 00:39 +0100, Ben Mulvihill wrote:\n> On Mon, 2015-01-19 at 19:21 +0100, Ben Mulvihill wrote:\n> > On Mon, 2015-01-19 at 16:47 +0100, Daniel Schwierzeck wrote:\n> > > 2015-01-19 15:44 GMT+01:00 Ben Mulvihill <ben.mulvihill@gmail.com>:\n> > > > On Mon, 2015-01-19 at 11:51 +0000, Conor O'Gorman wrote:\n> > > >> On 19/01/15 10:46, Ben Mulvihill wrote:\n> > > >> > Hello,\n> > > >> >\n> > > >> > I am trying to build uboot-lantiq for the BT Home Hub 3A (lantiq\n> > > >> > ar9), and am wondering where to initialise the cgu, in the case\n> > > >> > of a ramboot image for uart booting. Normally the cgu is initialised\n> > > >> > in lowlevel_init, but that code is bypassed in ramboot images. The\n> > > >> > result is that the board boots with the wrong cgu settings, which\n> > > >> > sends the console haywire. So far I have tried two solutions:\n> > > >>\n> > > >> Another option is to try and not change anything. The console is already\n> > > >> configured and running. The ram does need config.\n> > > >>\n> > > >> I was used to seeing the ramboot version running at half clock speed, at\n> > > >> least on danube, previous to ar9.\n> > > >>\n> > > >> Conor\n> > > >\n> > > > Hi Conor,\n> > > >\n> > > > Thanks for the reply. But with the latest uboot-lantiq, not changing\n> > > > anything means that I don't get a usable console. With an older\n> > > > version I do at least get a uboot console, but no linux console when\n> > > > I boot openwrt. Correcting the cgu settings solves both problems.\n> > > >\n> > > \n> > > could you try this?\n> > > \n> > > diff --git a/arch/mips/cpu/mips32/arx100/cgu.c\n> > > b/arch/mips/cpu/mips32/arx100/cgu.c\n> > > index 6e71ee7..e0afbda 100644\n> > > --- a/arch/mips/cpu/mips32/arx100/cgu.c\n> > > +++ b/arch/mips/cpu/mips32/arx100/cgu.c\n> > > @@ -95,15 +95,5 @@ unsigned long ltq_get_cpu_clock(void)\n> > > \n> > >  unsigned long ltq_get_bus_clock(void)\n> > >  {\n> > > -       u32 fpi_sel;\n> > > -       unsigned long clk;\n> > > -\n> > > -       fpi_sel = ltq_cgu_sys_readl(1, CGU_SYS_FPI_SEL);\n> > > -\n> > > -       if (fpi_sel)\n> > > -               clk = ltq_get_io_region_clock() / 2;\n> > > -       else\n> > > -               clk = ltq_get_io_region_clock();\n> > > -\n> > > -       return clk;\n> > > +       return ltq_get_io_region_clock();\n> > >  }\n> > > \n> > > the UART driver calculates the baudrate from the FPI bus clock, but\n> > > FPI_SEL is not available on AR9. FPI bus clock is always the same as\n> > > DDR clock, Obviously a copy&paste error from VR9 code ;)\n> > > \n> > \n> > No, even with this patch, I still don't get a working console I'm\n> > afraid. If I don't set anything explicitly, the board comes up with\n> > CGU_SYS set to 0x05, ie CGU_SYS_SYSSEL_PLL0_333_MHZ |\n> > CGU_SYS_CPUSEL_EQUAL_DDRCLK | CGU_SYS_DDRSEL_THIRD_SYSCLK.\n> > Is this a valid combination without CGU_SYS_PPESEL_250_MHZ ?\n> > I don't understand what CGU_SYS_PPESEL_250_MHZ does?\n> > The \"right setting\", as set by the stock uboot, is 0x80.\n> \n> P.S. There also seems to be a discrepancy between the uboot and\n> linux code. I take it from what you say above that fpi clock, ddr\n> clock and io region clock are all the same. Now if the least \n> significant bit of CGU_SYS is set, then according to the uboot\n> code - function ltq_get_bus_clock() - their value is one\n> third of the system clock. But according to the linux code\n> - function ltq_ar9_fpi_hz() in arch/mips/lantiq/xway/clk.c -\n> their value in this case is equal to the system clock.\n> \n> Or am I getting muddled? It's past my bedtime!\n> \n> \n\nSome of the bitshifting in arch/mips/cpu/mips32/arx100/cgu.c is 1\nout. A patch along these lines should fix it:\n\n--- a/arch/mips/cpu/mips32/arx100/cgu.c\n+++ b/arch/mips/cpu/mips32/arx100/cgu.c\n@@ -10,12 +10,17 @@\n #include <asm/lantiq/clk.h>\n #include <asm/lantiq/io.h>\n \n-#define CGU_SYS_DDR_SEL\t\t(1 << 0)\n-#define CGU_SYS_CPU_SEL\t\t(1 << 2)\n+#define CGU_SYS_DDR_SHIFT\t0\n+#define CGU_SYS_CPU_SHIFT\t2\n #define CGU_SYS_SYS_SHIFT\t3\n+#define CGU_SYS_FPI_SHIFT\t6\n+#define CGU_SYS_PPE_SHIFT\t7\n+\n+#define CGU_SYS_DDR_MASK\t(1 << CGU_SYS_DDR_SHIFT)\n+#define CGU_SYS_CPU_MASK\t(1 << CGU_SYS_CPU_SHIFT)\n #define CGU_SYS_SYS_MASK\t(0x3 << CGU_SYS_SYS_SHIFT)\n-#define CGU_SYS_FPI_SEL\t\t(1 << 6)\n-#define CGU_SYS_PPE_SEL\t\t(1 << 7)\n+#define CGU_SYS_FPI_MASK\t(1 << CGU_SYS_FPI_SHIFT)\n+#define CGU_SYS_PPE_MASK\t(1 << CGU_SYS_PPE_SHIFT)\n \n struct ltq_cgu_regs {\n \tu32\trsvd0;\n@@ -68,7 +73,7 @@ unsigned long ltq_get_io_region_clock(vo\n \tu32 ddr_sel;\n \tunsigned long clk;\n \n-\tddr_sel = ltq_cgu_sys_readl(1, CGU_SYS_DDR_SEL);\n+\tddr_sel = ltq_cgu_sys_readl(CGU_SYS_DDR_MASK, CGU_SYS_DDR_SHIFT);\n \n \tif (ddr_sel)\n \t\tclk = ltq_get_system_clock() / 3;\n@@ -83,7 +88,7 @@ unsigned long ltq_get_cpu_clock(void)\n \tu32 cpu_sel;\n \tunsigned long clk;\n \n-\tcpu_sel = ltq_cgu_sys_readl(1, CGU_SYS_CPU_SEL);\n+\tcpu_sel = ltq_cgu_sys_readl(CGU_SYS_CPU_MASK, CGU_SYS_CPU_SHIFT);\n \n \tif (cpu_sel)\n \t\tclk = ltq_get_io_region_clock();\n@@ -98,7 +103,7 @@ unsigned long ltq_get_bus_clock(void)\n \tu32 fpi_sel;\n \tunsigned long clk;\n \n-\tfpi_sel = ltq_cgu_sys_readl(1, CGU_SYS_FPI_SEL);\n+\tfpi_sel = ltq_cgu_sys_readl(CGU_SYS_FPI_MASK, CGU_SYS_FPI_SHIFT);\n \n \tif (fpi_sel)\n \t\tclk = ltq_get_io_region_clock() / 2;\n"
  },
  {
    "path": "package/boot/uboot-lantiq/patches/0026-no_extern_inline.patch",
    "content": "From b11c5d1dc29e81326d1215011d19377737082aeb Mon Sep 17 00:00:00 2001\nFrom: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>\nDate: Wed, 1 Jul 2015 16:36:43 +0200\nSubject: [PATCH] MIPS: change 'extern inline' to 'static inline'\n\nThe kernel changed it a long time ago. Also this is now broken\non gcc-5.x.\n\nReported-by: Andy Kennedy <andy.kennedy@adtran.com>\nSigned-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>\n---\n arch/mips/include/asm/io.h     | 12 ++++++------\n arch/mips/include/asm/system.h |  6 +++---\n 2 files changed, 9 insertions(+), 9 deletions(-)\n\n--- a/arch/mips/include/asm/io.h\n+++ b/arch/mips/include/asm/io.h\n@@ -118,7 +118,7 @@ static inline void set_io_port_base(unsi\n  * Change virtual addresses to physical addresses and vv.\n  * These are trivial on the 1:1 Linux/MIPS mapping\n  */\n-extern inline phys_addr_t virt_to_phys(volatile void * address)\n+static inline phys_addr_t virt_to_phys(volatile void * address)\n {\n #ifndef CONFIG_64BIT\n \treturn CPHYSADDR(address);\n@@ -127,7 +127,7 @@ extern inline phys_addr_t virt_to_phys(v\n #endif\n }\n \n-extern inline void * phys_to_virt(unsigned long address)\n+static inline void * phys_to_virt(unsigned long address)\n {\n #ifndef CONFIG_64BIT\n \treturn (void *)KSEG0ADDR(address);\n@@ -139,7 +139,7 @@ extern inline void * phys_to_virt(unsign\n /*\n  * IO bus memory addresses are also 1:1 with the physical address\n  */\n-extern inline unsigned long virt_to_bus(volatile void * address)\n+static inline unsigned long virt_to_bus(volatile void * address)\n {\n #ifndef CONFIG_64BIT\n \treturn CPHYSADDR(address);\n@@ -148,7 +148,7 @@ extern inline unsigned long virt_to_bus(\n #endif\n }\n \n-extern inline void * bus_to_virt(unsigned long address)\n+static inline void * bus_to_virt(unsigned long address)\n {\n #ifndef CONFIG_64BIT\n \treturn (void *)KSEG0ADDR(address);\n@@ -166,12 +166,12 @@ extern unsigned long isa_slot_offset;\n extern void * __ioremap(unsigned long offset, unsigned long size, unsigned long flags);\n \n #if 0\n-extern inline void *ioremap(unsigned long offset, unsigned long size)\n+static inline void *ioremap(unsigned long offset, unsigned long size)\n {\n \treturn __ioremap(offset, size, _CACHE_UNCACHED);\n }\n \n-extern inline void *ioremap_nocache(unsigned long offset, unsigned long size)\n+static inline void *ioremap_nocache(unsigned long offset, unsigned long size)\n {\n \treturn __ioremap(offset, size, _CACHE_UNCACHED);\n }\n--- a/arch/mips/include/asm/system.h\n+++ b/arch/mips/include/asm/system.h\n@@ -23,7 +23,7 @@\n #include <linux/kernel.h>\n #endif\n \n-extern __inline__ void\n+static __inline__ void\n __sti(void)\n {\n \t__asm__ __volatile__(\n@@ -47,7 +47,7 @@ __sti(void)\n  * R4000/R4400 need three nops, the R4600 two nops and the R10000 needs\n  * no nops at all.\n  */\n-extern __inline__ void\n+static __inline__ void\n __cli(void)\n {\n \t__asm__ __volatile__(\n@@ -208,7 +208,7 @@ do { \\\n  * For 32 and 64 bit operands we can take advantage of ll and sc.\n  * FIXME: This doesn't work for R3000 machines.\n  */\n-extern __inline__ unsigned long xchg_u32(volatile int * m, unsigned long val)\n+static __inline__ unsigned long xchg_u32(volatile int * m, unsigned long val)\n {\n #ifdef CONFIG_CPU_HAS_LLSC\n \tunsigned long dummy;\n"
  },
  {
    "path": "package/boot/uboot-lantiq/patches/0027-no_weak_alias.patch",
    "content": "From 3422299dc28fa8257677d03cc1253e3c9bf17e9f Mon Sep 17 00:00:00 2001\nFrom: Jeroen Hofstee <jeroen@myspectrum.nl>\nDate: Thu, 26 Jun 2014 20:18:31 +0200\nSubject: [PATCH] common: main.c: make show_boot_progress __weak\n\nThis not only looks a bit better it also prevents a\nwarning with W=1 (no previous prototype).\n\nSigned-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>\nAcked-by: Simon Glass <sjg@chromium.org>\n---\n common/main.c | 3 +--\n 1 file changed, 1 insertion(+), 2 deletions(-)\n\n--- a/common/main.c\n+++ b/common/main.c\n@@ -27,8 +27,7 @@ DECLARE_GLOBAL_DATA_PTR;\n /*\n  * Board-specific Platform code can reimplement show_boot_progress () if needed\n  */\n-void inline __show_boot_progress (int val) {}\n-void show_boot_progress (int val) __attribute__((weak, alias(\"__show_boot_progress\")));\n+__weak void show_boot_progress(int val) {}\n \n #define MAX_DELAY_STOP_STR 32\n \n"
  },
  {
    "path": "package/boot/uboot-lantiq/patches/0028-gcc-compat.patch",
    "content": "From 9b2c282b348dfe966bbba967dc7a45ce817cce50 Mon Sep 17 00:00:00 2001\nFrom: Tom Rini <trini@konsulko.com>\nDate: Mon, 29 Feb 2016 11:34:15 -0500\nSubject: [PATCH] compiler*.h: sync include/linux/compiler*.h with Linux\n 4.5-rc6\n\nCopy these from Linux v4.5-rc6 tag.\n\nThis is needed so that we can keep up with newer gcc versions.  Note\nthat we don't have the uapi/ hierarchy from the kernel so continue to\nuse <linux/types.h>\n\nSigned-off-by: Tom Rini <trini@konsulko.com>\n---\n include/linux/compiler-gcc.h   | 266 ++++++++++++++++++++++++++++++++++------\n include/linux/compiler-gcc3.h  |  21 ----\n include/linux/compiler-gcc4.h  |  63 ----------\n include/linux/compiler-intel.h |  45 +++++++\n include/linux/compiler.h       | 270 +++++++++++++++++++++++++++++++++++++++--\n 5 files changed, 534 insertions(+), 131 deletions(-)\n delete mode 100644 include/linux/compiler-gcc3.h\n delete mode 100644 include/linux/compiler-gcc4.h\n create mode 100644 include/linux/compiler-intel.h\n\ndiff --git a/include/linux/compiler-gcc.h b/include/linux/compiler-gcc.h\nindex 9896e54..22ab246 100644\n--- a/include/linux/compiler-gcc.h\n+++ b/include/linux/compiler-gcc.h\n@@ -5,11 +5,28 @@\n /*\n  * Common definitions for all gcc versions go here.\n  */\n-\n+#define GCC_VERSION (__GNUC__ * 10000\t\t\\\n+\t\t     + __GNUC_MINOR__ * 100\t\\\n+\t\t     + __GNUC_PATCHLEVEL__)\n \n /* Optimization barrier */\n+\n /* The \"volatile\" is due to gcc bugs */\n #define barrier() __asm__ __volatile__(\"\": : :\"memory\")\n+/*\n+ * This version is i.e. to prevent dead stores elimination on @ptr\n+ * where gcc and llvm may behave differently when otherwise using\n+ * normal barrier(): while gcc behavior gets along with a normal\n+ * barrier(), llvm needs an explicit input variable to be assumed\n+ * clobbered. The issue is as follows: while the inline asm might\n+ * access any memory it wants, the compiler could have fit all of\n+ * @ptr into memory registers instead, and since @ptr never escaped\n+ * from that, it proofed that the inline asm wasn't touching any of\n+ * it. This version works well with both compilers, i.e. we're telling\n+ * the compiler that the inline asm absolutely may see the contents\n+ * of @ptr. See also: https://llvm.org/bugs/show_bug.cgi?id=15495\n+ */\n+#define barrier_data(ptr) __asm__ __volatile__(\"\": :\"r\"(ptr) :\"memory\")\n \n /*\n  * This macro obfuscates arithmetic on a variable address so that gcc\n@@ -29,41 +46,63 @@\n  * the inline assembly constraint from =g to =r, in this particular\n  * case either is valid.\n  */\n-#define RELOC_HIDE(ptr, off)\t\t\t\t\t\\\n-  ({ unsigned long __ptr;\t\t\t\t\t\\\n-    __asm__ (\"\" : \"=r\"(__ptr) : \"0\"(ptr));\t\t\\\n-    (typeof(ptr)) (__ptr + (off)); })\n+#define RELOC_HIDE(ptr, off)\t\t\t\t\t\t\\\n+({\t\t\t\t\t\t\t\t\t\\\n+\tunsigned long __ptr;\t\t\t\t\t\t\\\n+\t__asm__ (\"\" : \"=r\"(__ptr) : \"0\"(ptr));\t\t\t\t\\\n+\t(typeof(ptr)) (__ptr + (off));\t\t\t\t\t\\\n+})\n+\n+/* Make the optimizer believe the variable can be manipulated arbitrarily. */\n+#define OPTIMIZER_HIDE_VAR(var)\t\t\t\t\t\t\\\n+\t__asm__ (\"\" : \"=r\" (var) : \"0\" (var))\n \n+#ifdef __CHECKER__\n+#define __must_be_array(a)\t0\n+#else\n /* &a[0] degrades to a pointer: a different type from an array */\n-#define __must_be_array(a) \\\n-  BUILD_BUG_ON_ZERO(__builtin_types_compatible_p(typeof(a), typeof(&a[0])))\n+#define __must_be_array(a)\tBUILD_BUG_ON_ZERO(__same_type((a), &(a)[0]))\n+#endif\n \n /*\n  * Force always-inline if the user requests it so via the .config,\n  * or if gcc is too old:\n  */\n-#if !defined(CONFIG_ARCH_SUPPORTS_OPTIMIZED_INLINING) || \\\n+#if !defined(CONFIG_ARCH_SUPPORTS_OPTIMIZED_INLINING) ||\t\t\\\n     !defined(CONFIG_OPTIMIZE_INLINING) || (__GNUC__ < 4)\n-# define inline\t\tinline\t\t__attribute__((always_inline))\n-# define __inline__\t__inline__\t__attribute__((always_inline))\n-# define __inline\t__inline\t__attribute__((always_inline))\n+#define inline\t\tinline\t\t__attribute__((always_inline)) notrace\n+#define __inline__\t__inline__\t__attribute__((always_inline)) notrace\n+#define __inline\t__inline\t__attribute__((always_inline)) notrace\n+#else\n+/* A lot of inline functions can cause havoc with function tracing */\n+#define inline\t\tinline\t\tnotrace\n+#define __inline__\t__inline__\tnotrace\n+#define __inline\t__inline\tnotrace\n #endif\n \n-#define __deprecated\t\t\t__attribute__((deprecated))\n-#ifndef __packed\n-# define __packed\t\t\t__attribute__((packed))\n-#endif\n-#define __weak\t\t\t\t__attribute__((weak))\n+#define __always_inline\tinline __attribute__((always_inline))\n+#define  noinline\t__attribute__((noinline))\n+\n+#define __deprecated\t__attribute__((deprecated))\n+#define __packed\t__attribute__((packed))\n+#define __weak\t\t__attribute__((weak))\n+#define __alias(symbol)\t__attribute__((alias(#symbol)))\n \n /*\n- * it doesn't make sense on ARM (currently the only user of __naked) to trace\n- * naked functions because then mcount is called without stack and frame pointer\n- * being set up and there is no chance to restore the lr register to the value\n- * before mcount was called.\n+ * it doesn't make sense on ARM (currently the only user of __naked)\n+ * to trace naked functions because then mcount is called without\n+ * stack and frame pointer being set up and there is no chance to\n+ * restore the lr register to the value before mcount was called.\n+ *\n+ * The asm() bodies of naked functions often depend on standard calling\n+ * conventions, therefore they must be noinline and noclone.\n+ *\n+ * GCC 4.[56] currently fail to enforce this, so we must do so ourselves.\n+ * See GCC PR44290.\n  */\n-#define __naked\t\t\t\t__attribute__((naked)) notrace\n+#define __naked\t\t__attribute__((naked)) noinline __noclone notrace\n \n-#define __noreturn\t\t\t__attribute__((noreturn))\n+#define __noreturn\t__attribute__((noreturn))\n \n /*\n  * From the GCC manual:\n@@ -75,19 +114,170 @@\n  * would be.\n  * [...]\n  */\n-#ifndef __pure\n-# define __pure\t\t\t\t__attribute__((pure))\n-#endif\n-#ifndef __aligned\n-# define __aligned(x)\t\t\t__attribute__((aligned(x)))\n-#endif\n-#define __printf(a,b)\t\t\t__attribute__((format(printf,a,b)))\n-#define  noinline\t\t\t__attribute__((noinline))\n-#define __attribute_const__\t\t__attribute__((__const__))\n-#define __maybe_unused\t\t\t__attribute__((unused))\n-#define __always_unused\t\t\t__attribute__((unused))\n-\n-#define __gcc_header(x) #x\n-#define _gcc_header(x) __gcc_header(linux/compiler-gcc##x.h)\n-#define gcc_header(x) _gcc_header(x)\n-#include gcc_header(__GNUC__)\n+#define __pure\t\t\t__attribute__((pure))\n+#define __aligned(x)\t\t__attribute__((aligned(x)))\n+#define __printf(a, b)\t\t__attribute__((format(printf, a, b)))\n+#define __scanf(a, b)\t\t__attribute__((format(scanf, a, b)))\n+#define __attribute_const__\t__attribute__((__const__))\n+#define __maybe_unused\t\t__attribute__((unused))\n+#define __always_unused\t\t__attribute__((unused))\n+\n+/* gcc version specific checks */\n+\n+#if GCC_VERSION < 30200\n+# error Sorry, your compiler is too old - please upgrade it.\n+#endif\n+\n+#if GCC_VERSION < 30300\n+# define __used\t\t\t__attribute__((__unused__))\n+#else\n+# define __used\t\t\t__attribute__((__used__))\n+#endif\n+\n+#ifdef CONFIG_GCOV_KERNEL\n+# if GCC_VERSION < 30400\n+#   error \"GCOV profiling support for gcc versions below 3.4 not included\"\n+# endif /* __GNUC_MINOR__ */\n+#endif /* CONFIG_GCOV_KERNEL */\n+\n+#if GCC_VERSION >= 30400\n+#define __must_check\t\t__attribute__((warn_unused_result))\n+#endif\n+\n+#if GCC_VERSION >= 40000\n+\n+/* GCC 4.1.[01] miscompiles __weak */\n+#ifdef __KERNEL__\n+# if GCC_VERSION >= 40100 &&  GCC_VERSION <= 40101\n+#  error Your version of gcc miscompiles the __weak directive\n+# endif\n+#endif\n+\n+#define __used\t\t\t__attribute__((__used__))\n+#define __compiler_offsetof(a, b)\t\t\t\t\t\\\n+\t__builtin_offsetof(a, b)\n+\n+#if GCC_VERSION >= 40100 && GCC_VERSION < 40600\n+# define __compiletime_object_size(obj) __builtin_object_size(obj, 0)\n+#endif\n+\n+#if GCC_VERSION >= 40300\n+/* Mark functions as cold. gcc will assume any path leading to a call\n+ * to them will be unlikely.  This means a lot of manual unlikely()s\n+ * are unnecessary now for any paths leading to the usual suspects\n+ * like BUG(), printk(), panic() etc. [but let's keep them for now for\n+ * older compilers]\n+ *\n+ * Early snapshots of gcc 4.3 don't support this and we can't detect this\n+ * in the preprocessor, but we can live with this because they're unreleased.\n+ * Maketime probing would be overkill here.\n+ *\n+ * gcc also has a __attribute__((__hot__)) to move hot functions into\n+ * a special section, but I don't see any sense in this right now in\n+ * the kernel context\n+ */\n+#define __cold\t\t\t__attribute__((__cold__))\n+\n+#define __UNIQUE_ID(prefix) __PASTE(__PASTE(__UNIQUE_ID_, prefix), __COUNTER__)\n+\n+#ifndef __CHECKER__\n+# define __compiletime_warning(message) __attribute__((warning(message)))\n+# define __compiletime_error(message) __attribute__((error(message)))\n+#endif /* __CHECKER__ */\n+#endif /* GCC_VERSION >= 40300 */\n+\n+#if GCC_VERSION >= 40500\n+/*\n+ * Mark a position in code as unreachable.  This can be used to\n+ * suppress control flow warnings after asm blocks that transfer\n+ * control elsewhere.\n+ *\n+ * Early snapshots of gcc 4.5 don't support this and we can't detect\n+ * this in the preprocessor, but we can live with this because they're\n+ * unreleased.  Really, we need to have autoconf for the kernel.\n+ */\n+#define unreachable() __builtin_unreachable()\n+\n+/* Mark a function definition as prohibited from being cloned. */\n+#define __noclone\t__attribute__((__noclone__))\n+\n+#endif /* GCC_VERSION >= 40500 */\n+\n+#if GCC_VERSION >= 40600\n+/*\n+ * When used with Link Time Optimization, gcc can optimize away C functions or\n+ * variables which are referenced only from assembly code.  __visible tells the\n+ * optimizer that something else uses this function or variable, thus preventing\n+ * this.\n+ */\n+#define __visible\t__attribute__((externally_visible))\n+#endif\n+\n+\n+#if GCC_VERSION >= 40900 && !defined(__CHECKER__)\n+/*\n+ * __assume_aligned(n, k): Tell the optimizer that the returned\n+ * pointer can be assumed to be k modulo n. The second argument is\n+ * optional (default 0), so we use a variadic macro to make the\n+ * shorthand.\n+ *\n+ * Beware: Do not apply this to functions which may return\n+ * ERR_PTRs. Also, it is probably unwise to apply it to functions\n+ * returning extra information in the low bits (but in that case the\n+ * compiler should see some alignment anyway, when the return value is\n+ * massaged by 'flags = ptr & 3; ptr &= ~3;').\n+ */\n+#define __assume_aligned(a, ...) __attribute__((__assume_aligned__(a, ## __VA_ARGS__)))\n+#endif\n+\n+/*\n+ * GCC 'asm goto' miscompiles certain code sequences:\n+ *\n+ *   http://gcc.gnu.org/bugzilla/show_bug.cgi?id=58670\n+ *\n+ * Work it around via a compiler barrier quirk suggested by Jakub Jelinek.\n+ *\n+ * (asm goto is automatically volatile - the naming reflects this.)\n+ */\n+#define asm_volatile_goto(x...)\tdo { asm goto(x); asm (\"\"); } while (0)\n+\n+#ifdef CONFIG_ARCH_USE_BUILTIN_BSWAP\n+#if GCC_VERSION >= 40400\n+#define __HAVE_BUILTIN_BSWAP32__\n+#define __HAVE_BUILTIN_BSWAP64__\n+#endif\n+#if GCC_VERSION >= 40800 || (defined(__powerpc__) && GCC_VERSION >= 40600)\n+#define __HAVE_BUILTIN_BSWAP16__\n+#endif\n+#endif /* CONFIG_ARCH_USE_BUILTIN_BSWAP */\n+\n+#if GCC_VERSION >= 50000\n+#define KASAN_ABI_VERSION 4\n+#elif GCC_VERSION >= 40902\n+#define KASAN_ABI_VERSION 3\n+#endif\n+\n+#if GCC_VERSION >= 40902\n+/*\n+ * Tell the compiler that address safety instrumentation (KASAN)\n+ * should not be applied to that function.\n+ * Conflicts with inlining: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67368\n+ */\n+#define __no_sanitize_address __attribute__((no_sanitize_address))\n+#endif\n+\n+#endif\t/* gcc version >= 40000 specific checks */\n+\n+#if !defined(__noclone)\n+#define __noclone\t/* not needed */\n+#endif\n+\n+#if !defined(__no_sanitize_address)\n+#define __no_sanitize_address\n+#endif\n+\n+/*\n+ * A trick to suppress uninitialized variable warning without generating any\n+ * code\n+ */\n+#define uninitialized_var(x) x = x\ndiff --git a/include/linux/compiler-gcc3.h b/include/linux/compiler-gcc3.h\ndeleted file mode 100644\nindex 2befe65..0000000\n--- a/include/linux/compiler-gcc3.h\n+++ /dev/null\n@@ -1,21 +0,0 @@\n-#ifndef __LINUX_COMPILER_H\n-#error \"Please don't include <linux/compiler-gcc3.h> directly, include <linux/compiler.h> instead.\"\n-#endif\n-\n-#if __GNUC_MINOR__ >= 3\n-# define __used\t\t\t__attribute__((__used__))\n-#else\n-# define __used\t\t\t__attribute__((__unused__))\n-#endif\n-\n-#if __GNUC_MINOR__ >= 4\n-#define __must_check\t\t__attribute__((warn_unused_result))\n-#endif\n-\n-/*\n- * A trick to suppress uninitialized variable warning without generating any\n- * code\n- */\n-#define uninitialized_var(x) x = x\n-\n-#define __always_inline\t\tinline __attribute__((always_inline))\ndiff --git a/include/linux/compiler-gcc4.h b/include/linux/compiler-gcc4.h\ndeleted file mode 100644\nindex 27d11ca..0000000\n--- a/include/linux/compiler-gcc4.h\n+++ /dev/null\n@@ -1,63 +0,0 @@\n-#ifndef __LINUX_COMPILER_H\n-#error \"Please don't include <linux/compiler-gcc4.h> directly, include <linux/compiler.h> instead.\"\n-#endif\n-\n-/* GCC 4.1.[01] miscompiles __weak */\n-#ifdef __KERNEL__\n-# if __GNUC_MINOR__ == 1 && __GNUC_PATCHLEVEL__ <= 1\n-#  error Your version of gcc miscompiles the __weak directive\n-# endif\n-#endif\n-\n-#define __used\t\t\t__attribute__((__used__))\n-#define __must_check \t\t__attribute__((warn_unused_result))\n-#define __compiler_offsetof(a,b) __builtin_offsetof(a,b)\n-#ifndef __always_inline\n-# define __always_inline\t\tinline __attribute__((always_inline))\n-#endif\n-\n-/*\n- * A trick to suppress uninitialized variable warning without generating any\n- * code\n- */\n-#define uninitialized_var(x) x = x\n-\n-#if __GNUC_MINOR__ >= 3\n-/* Mark functions as cold. gcc will assume any path leading to a call\n-   to them will be unlikely.  This means a lot of manual unlikely()s\n-   are unnecessary now for any paths leading to the usual suspects\n-   like BUG(), printk(), panic() etc. [but let's keep them for now for\n-   older compilers]\n-\n-   Early snapshots of gcc 4.3 don't support this and we can't detect this\n-   in the preprocessor, but we can live with this because they're unreleased.\n-   Maketime probing would be overkill here.\n-\n-   gcc also has a __attribute__((__hot__)) to move hot functions into\n-   a special section, but I don't see any sense in this right now in\n-   the kernel context */\n-#define __cold\t\t\t__attribute__((__cold__))\n-\n-\n-#if __GNUC_MINOR__ >= 5\n-/*\n- * Mark a position in code as unreachable.  This can be used to\n- * suppress control flow warnings after asm blocks that transfer\n- * control elsewhere.\n- *\n- * Early snapshots of gcc 4.5 don't support this and we can't detect\n- * this in the preprocessor, but we can live with this because they're\n- * unreleased.  Really, we need to have autoconf for the kernel.\n- */\n-#define unreachable() __builtin_unreachable()\n-#endif\n-\n-#endif\n-\n-#if __GNUC_MINOR__ > 0\n-#define __compiletime_object_size(obj) __builtin_object_size(obj, 0)\n-#endif\n-#if __GNUC_MINOR__ >= 4\n-#define __compiletime_warning(message) __attribute__((warning(message)))\n-#define __compiletime_error(message) __attribute__((error(message)))\n-#endif\ndiff --git a/include/linux/compiler-intel.h b/include/linux/compiler-intel.h\nnew file mode 100644\nindex 0000000..d4c7113\n--- /dev/null\n+++ b/include/linux/compiler-intel.h\n@@ -0,0 +1,45 @@\n+#ifndef __LINUX_COMPILER_H\n+#error \"Please don't include <linux/compiler-intel.h> directly, include <linux/compiler.h> instead.\"\n+#endif\n+\n+#ifdef __ECC\n+\n+/* Some compiler specific definitions are overwritten here\n+ * for Intel ECC compiler\n+ */\n+\n+#include <asm/intrinsics.h>\n+\n+/* Intel ECC compiler doesn't support gcc specific asm stmts.\n+ * It uses intrinsics to do the equivalent things.\n+ */\n+#undef barrier\n+#undef barrier_data\n+#undef RELOC_HIDE\n+#undef OPTIMIZER_HIDE_VAR\n+\n+#define barrier() __memory_barrier()\n+#define barrier_data(ptr) barrier()\n+\n+#define RELOC_HIDE(ptr, off)\t\t\t\t\t\\\n+  ({ unsigned long __ptr;\t\t\t\t\t\\\n+     __ptr = (unsigned long) (ptr);\t\t\t\t\\\n+    (typeof(ptr)) (__ptr + (off)); })\n+\n+/* This should act as an optimization barrier on var.\n+ * Given that this compiler does not have inline assembly, a compiler barrier\n+ * is the best we can do.\n+ */\n+#define OPTIMIZER_HIDE_VAR(var) barrier()\n+\n+/* Intel ECC compiler doesn't support __builtin_types_compatible_p() */\n+#define __must_be_array(a) 0\n+\n+#endif\n+\n+#ifndef __HAVE_BUILTIN_BSWAP16__\n+/* icc has this, but it's called _bswap16 */\n+#define __HAVE_BUILTIN_BSWAP16__\n+#define __builtin_bswap16 _bswap16\n+#endif\n+\ndiff --git a/include/linux/compiler.h b/include/linux/compiler.h\nindex 5be3dab..020ad16 100644\n--- a/include/linux/compiler.h\n+++ b/include/linux/compiler.h\n@@ -5,16 +5,24 @@\n \n #ifdef __CHECKER__\n # define __user\t\t__attribute__((noderef, address_space(1)))\n-# define __kernel\t/* default address space */\n+# define __kernel\t__attribute__((address_space(0)))\n # define __safe\t\t__attribute__((safe))\n # define __force\t__attribute__((force))\n # define __nocast\t__attribute__((nocast))\n # define __iomem\t__attribute__((noderef, address_space(2)))\n+# define __must_hold(x)\t__attribute__((context(x,1,1)))\n # define __acquires(x)\t__attribute__((context(x,0,1)))\n # define __releases(x)\t__attribute__((context(x,1,0)))\n # define __acquire(x)\t__context__(x,1)\n # define __release(x)\t__context__(x,-1)\n # define __cond_lock(x,c)\t((c) ? ({ __acquire(x); 1; }) : 0)\n+# define __percpu\t__attribute__((noderef, address_space(3)))\n+# define __pmem\t\t__attribute__((noderef, address_space(5)))\n+#ifdef CONFIG_SPARSE_RCU_POINTER\n+# define __rcu\t\t__attribute__((noderef, address_space(4)))\n+#else\n+# define __rcu\n+#endif\n extern void __chk_user_ptr(const volatile void __user *);\n extern void __chk_io_ptr(const volatile void __iomem *);\n #else\n@@ -27,20 +35,32 @@ extern void __chk_io_ptr(const volatile void __iomem *);\n # define __chk_user_ptr(x) (void)0\n # define __chk_io_ptr(x) (void)0\n # define __builtin_warning(x, y...) (1)\n+# define __must_hold(x)\n # define __acquires(x)\n # define __releases(x)\n # define __acquire(x) (void)0\n # define __release(x) (void)0\n # define __cond_lock(x,c) (c)\n+# define __percpu\n+# define __rcu\n+# define __pmem\n #endif\n \n+/* Indirect macros required for expanded argument pasting, eg. __LINE__. */\n+#define ___PASTE(a,b) a##b\n+#define __PASTE(a,b) ___PASTE(a,b)\n+\n #ifdef __KERNEL__\n \n #ifdef __GNUC__\n #include <linux/compiler-gcc.h>\n #endif\n \n+#if defined(CC_USING_HOTPATCH) && !defined(__CHECKER__)\n+#define notrace __attribute__((hotpatch(0,0)))\n+#else\n #define notrace __attribute__((no_instrument_function))\n+#endif\n \n /* Intel compiler defines __GNUC__. So we will overwrite implementations\n  * coming from above header files here\n@@ -49,6 +69,13 @@ extern void __chk_io_ptr(const volatile void __iomem *);\n # include <linux/compiler-intel.h>\n #endif\n \n+/* Clang compiler defines __GNUC__. So we will overwrite implementations\n+ * coming from above header files here\n+ */\n+#ifdef __clang__\n+#include <linux/compiler-clang.h>\n+#endif\n+\n /*\n  * Generic compiler-dependent macros required for kernel\n  * build go below this comment. Actual compiler/compiler version\n@@ -117,7 +144,7 @@ void ftrace_likely_update(struct ftrace_branch_data *f, int val, int expect);\n  */\n #define if(cond, ...) __trace_if( (cond , ## __VA_ARGS__) )\n #define __trace_if(cond) \\\n-\tif (__builtin_constant_p((cond)) ? !!(cond) :\t\t\t\\\n+\tif (__builtin_constant_p(!!(cond)) ? !!(cond) :\t\t\t\\\n \t({\t\t\t\t\t\t\t\t\\\n \t\tint ______r;\t\t\t\t\t\t\\\n \t\tstatic struct ftrace_branch_data\t\t\t\\\n@@ -144,6 +171,10 @@ void ftrace_likely_update(struct ftrace_branch_data *f, int val, int expect);\n # define barrier() __memory_barrier()\n #endif\n \n+#ifndef barrier_data\n+# define barrier_data(ptr) barrier()\n+#endif\n+\n /* Unreachable code */\n #ifndef unreachable\n # define unreachable() do { } while (1)\n@@ -156,6 +187,135 @@ void ftrace_likely_update(struct ftrace_branch_data *f, int val, int expect);\n     (typeof(ptr)) (__ptr + (off)); })\n #endif\n \n+#ifndef OPTIMIZER_HIDE_VAR\n+#define OPTIMIZER_HIDE_VAR(var) barrier()\n+#endif\n+\n+/* Not-quite-unique ID. */\n+#ifndef __UNIQUE_ID\n+# define __UNIQUE_ID(prefix) __PASTE(__PASTE(__UNIQUE_ID_, prefix), __LINE__)\n+#endif\n+\n+#include <linux/types.h>\n+\n+#define __READ_ONCE_SIZE\t\t\t\t\t\t\\\n+({\t\t\t\t\t\t\t\t\t\\\n+\tswitch (size) {\t\t\t\t\t\t\t\\\n+\tcase 1: *(__u8 *)res = *(volatile __u8 *)p; break;\t\t\\\n+\tcase 2: *(__u16 *)res = *(volatile __u16 *)p; break;\t\t\\\n+\tcase 4: *(__u32 *)res = *(volatile __u32 *)p; break;\t\t\\\n+\tcase 8: *(__u64 *)res = *(volatile __u64 *)p; break;\t\t\\\n+\tdefault:\t\t\t\t\t\t\t\\\n+\t\tbarrier();\t\t\t\t\t\t\\\n+\t\t__builtin_memcpy((void *)res, (const void *)p, size);\t\\\n+\t\tbarrier();\t\t\t\t\t\t\\\n+\t}\t\t\t\t\t\t\t\t\\\n+})\n+\n+static __always_inline\n+void __read_once_size(const volatile void *p, void *res, int size)\n+{\n+\t__READ_ONCE_SIZE;\n+}\n+\n+#ifdef CONFIG_KASAN\n+/*\n+ * This function is not 'inline' because __no_sanitize_address confilcts\n+ * with inlining. Attempt to inline it may cause a build failure.\n+ * \thttps://gcc.gnu.org/bugzilla/show_bug.cgi?id=67368\n+ * '__maybe_unused' allows us to avoid defined-but-not-used warnings.\n+ */\n+static __no_sanitize_address __maybe_unused\n+void __read_once_size_nocheck(const volatile void *p, void *res, int size)\n+{\n+\t__READ_ONCE_SIZE;\n+}\n+#else\n+static __always_inline\n+void __read_once_size_nocheck(const volatile void *p, void *res, int size)\n+{\n+\t__READ_ONCE_SIZE;\n+}\n+#endif\n+\n+static __always_inline void __write_once_size(volatile void *p, void *res, int size)\n+{\n+\tswitch (size) {\n+\tcase 1: *(volatile __u8 *)p = *(__u8 *)res; break;\n+\tcase 2: *(volatile __u16 *)p = *(__u16 *)res; break;\n+\tcase 4: *(volatile __u32 *)p = *(__u32 *)res; break;\n+\tcase 8: *(volatile __u64 *)p = *(__u64 *)res; break;\n+\tdefault:\n+\t\tbarrier();\n+\t\t__builtin_memcpy((void *)p, (const void *)res, size);\n+\t\tbarrier();\n+\t}\n+}\n+\n+/*\n+ * Prevent the compiler from merging or refetching reads or writes. The\n+ * compiler is also forbidden from reordering successive instances of\n+ * READ_ONCE, WRITE_ONCE and ACCESS_ONCE (see below), but only when the\n+ * compiler is aware of some particular ordering.  One way to make the\n+ * compiler aware of ordering is to put the two invocations of READ_ONCE,\n+ * WRITE_ONCE or ACCESS_ONCE() in different C statements.\n+ *\n+ * In contrast to ACCESS_ONCE these two macros will also work on aggregate\n+ * data types like structs or unions. If the size of the accessed data\n+ * type exceeds the word size of the machine (e.g., 32 bits or 64 bits)\n+ * READ_ONCE() and WRITE_ONCE()  will fall back to memcpy and print a\n+ * compile-time warning.\n+ *\n+ * Their two major use cases are: (1) Mediating communication between\n+ * process-level code and irq/NMI handlers, all running on the same CPU,\n+ * and (2) Ensuring that the compiler does not  fold, spindle, or otherwise\n+ * mutilate accesses that either do not require ordering or that interact\n+ * with an explicit memory barrier or atomic instruction that provides the\n+ * required ordering.\n+ */\n+\n+#define __READ_ONCE(x, check)\t\t\t\t\t\t\\\n+({\t\t\t\t\t\t\t\t\t\\\n+\tunion { typeof(x) __val; char __c[1]; } __u;\t\t\t\\\n+\tif (check)\t\t\t\t\t\t\t\\\n+\t\t__read_once_size(&(x), __u.__c, sizeof(x));\t\t\\\n+\telse\t\t\t\t\t\t\t\t\\\n+\t\t__read_once_size_nocheck(&(x), __u.__c, sizeof(x));\t\\\n+\t__u.__val;\t\t\t\t\t\t\t\\\n+})\n+#define READ_ONCE(x) __READ_ONCE(x, 1)\n+\n+/*\n+ * Use READ_ONCE_NOCHECK() instead of READ_ONCE() if you need\n+ * to hide memory access from KASAN.\n+ */\n+#define READ_ONCE_NOCHECK(x) __READ_ONCE(x, 0)\n+\n+#define WRITE_ONCE(x, val) \\\n+({\t\t\t\t\t\t\t\\\n+\tunion { typeof(x) __val; char __c[1]; } __u =\t\\\n+\t\t{ .__val = (__force typeof(x)) (val) }; \\\n+\t__write_once_size(&(x), __u.__c, sizeof(x));\t\\\n+\t__u.__val;\t\t\t\t\t\\\n+})\n+\n+/**\n+ * smp_cond_acquire() - Spin wait for cond with ACQUIRE ordering\n+ * @cond: boolean expression to wait for\n+ *\n+ * Equivalent to using smp_load_acquire() on the condition variable but employs\n+ * the control dependency of the wait to reduce the barrier on many platforms.\n+ *\n+ * The control dependency provides a LOAD->STORE order, the additional RMB\n+ * provides LOAD->LOAD order, together they provide LOAD->{LOAD,STORE} order,\n+ * aka. ACQUIRE.\n+ */\n+#define smp_cond_acquire(cond)\tdo {\t\t\\\n+\twhile (!(cond))\t\t\t\t\\\n+\t\tcpu_relax();\t\t\t\\\n+\tsmp_rmb(); /* ctrl + rmb := acquire */\t\\\n+} while (0)\n+\n #endif /* __KERNEL__ */\n \n #endif /* __ASSEMBLY__ */\n@@ -228,7 +388,7 @@ void ftrace_likely_update(struct ftrace_branch_data *f, int val, int expect);\n \n /*\n  * Rather then using noinline to prevent stack consumption, use\n- * noinline_for_stack instead.  For documentaiton reasons.\n+ * noinline_for_stack instead.  For documentation reasons.\n  */\n #define noinline_for_stack noinline\n \n@@ -270,11 +430,28 @@ void ftrace_likely_update(struct ftrace_branch_data *f, int val, int expect);\n # define __section(S) __attribute__ ((__section__(#S)))\n #endif\n \n+#ifndef __visible\n+#define __visible\n+#endif\n+\n+/*\n+ * Assume alignment of return value.\n+ */\n+#ifndef __assume_aligned\n+#define __assume_aligned(a, ...)\n+#endif\n+\n+\n /* Are two types/vars the same type (ignoring qualifiers)? */\n #ifndef __same_type\n # define __same_type(a, b) __builtin_types_compatible_p(typeof(a), typeof(b))\n #endif\n \n+/* Is this type a native word size -- useful for atomic operations */\n+#ifndef __native_word\n+# define __native_word(t) (sizeof(t) == sizeof(char) || sizeof(t) == sizeof(short) || sizeof(t) == sizeof(int) || sizeof(t) == sizeof(long))\n+#endif\n+\n /* Compile time object size, -1 for unknown */\n #ifndef __compiletime_object_size\n # define __compiletime_object_size(obj) -1\n@@ -284,7 +461,48 @@ void ftrace_likely_update(struct ftrace_branch_data *f, int val, int expect);\n #endif\n #ifndef __compiletime_error\n # define __compiletime_error(message)\n+/*\n+ * Sparse complains of variable sized arrays due to the temporary variable in\n+ * __compiletime_assert. Unfortunately we can't just expand it out to make\n+ * sparse see a constant array size without breaking compiletime_assert on old\n+ * versions of GCC (e.g. 4.2.4), so hide the array from sparse altogether.\n+ */\n+# ifndef __CHECKER__\n+#  define __compiletime_error_fallback(condition) \\\n+\tdo { ((void)sizeof(char[1 - 2 * condition])); } while (0)\n+# endif\n #endif\n+#ifndef __compiletime_error_fallback\n+# define __compiletime_error_fallback(condition) do { } while (0)\n+#endif\n+\n+#define __compiletime_assert(condition, msg, prefix, suffix)\t\t\\\n+\tdo {\t\t\t\t\t\t\t\t\\\n+\t\tbool __cond = !(condition);\t\t\t\t\\\n+\t\textern void prefix ## suffix(void) __compiletime_error(msg); \\\n+\t\tif (__cond)\t\t\t\t\t\t\\\n+\t\t\tprefix ## suffix();\t\t\t\t\\\n+\t\t__compiletime_error_fallback(__cond);\t\t\t\\\n+\t} while (0)\n+\n+#define _compiletime_assert(condition, msg, prefix, suffix) \\\n+\t__compiletime_assert(condition, msg, prefix, suffix)\n+\n+/**\n+ * compiletime_assert - break build and emit msg if condition is false\n+ * @condition: a compile-time constant condition to check\n+ * @msg:       a message to emit if condition is false\n+ *\n+ * In tradition of POSIX assert, this macro will break the build if the\n+ * supplied condition is *false*, emitting the supplied error message if the\n+ * compiler has support to do so.\n+ */\n+#define compiletime_assert(condition, msg) \\\n+\t_compiletime_assert(condition, msg, __compiletime_assert_, __LINE__)\n+\n+#define compiletime_assert_atomic_type(t)\t\t\t\t\\\n+\tcompiletime_assert(__native_word(t),\t\t\t\t\\\n+\t\t\"Need native word sized stores/loads for atomicity.\")\n \n /*\n  * Prevent the compiler from merging or refetching accesses.  The compiler\n@@ -293,11 +511,45 @@ void ftrace_likely_update(struct ftrace_branch_data *f, int val, int expect);\n  * to make the compiler aware of ordering is to put the two invocations of\n  * ACCESS_ONCE() in different C statements.\n  *\n- * This macro does absolutely -nothing- to prevent the CPU from reordering,\n- * merging, or refetching absolutely anything at any time.  Its main intended\n- * use is to mediate communication between process-level code and irq/NMI\n- * handlers, all running on the same CPU.\n+ * ACCESS_ONCE will only work on scalar types. For union types, ACCESS_ONCE\n+ * on a union member will work as long as the size of the member matches the\n+ * size of the union and the size is smaller than word size.\n+ *\n+ * The major use cases of ACCESS_ONCE used to be (1) Mediating communication\n+ * between process-level code and irq/NMI handlers, all running on the same CPU,\n+ * and (2) Ensuring that the compiler does not  fold, spindle, or otherwise\n+ * mutilate accesses that either do not require ordering or that interact\n+ * with an explicit memory barrier or atomic instruction that provides the\n+ * required ordering.\n+ *\n+ * If possible use READ_ONCE()/WRITE_ONCE() instead.\n  */\n-#define ACCESS_ONCE(x) (*(volatile typeof(x) *)&(x))\n-\n+#define __ACCESS_ONCE(x) ({ \\\n+\t __maybe_unused typeof(x) __var = (__force typeof(x)) 0; \\\n+\t(volatile typeof(x) *)&(x); })\n+#define ACCESS_ONCE(x) (*__ACCESS_ONCE(x))\n+\n+/**\n+ * lockless_dereference() - safely load a pointer for later dereference\n+ * @p: The pointer to load\n+ *\n+ * Similar to rcu_dereference(), but for situations where the pointed-to\n+ * object's lifetime is managed by something other than RCU.  That\n+ * \"something other\" might be reference counting or simple immortality.\n+ */\n+#define lockless_dereference(p) \\\n+({ \\\n+\ttypeof(p) _________p1 = READ_ONCE(p); \\\n+\tsmp_read_barrier_depends(); /* Dependency order vs. p above. */ \\\n+\t(_________p1); \\\n+})\n+\n+/* Ignore/forbid kprobes attach on very low level functions marked by this attribute: */\n+#ifdef CONFIG_KPROBES\n+# define __kprobes\t__attribute__((__section__(\".kprobes.text\")))\n+# define nokprobe_inline\t__always_inline\n+#else\n+# define __kprobes\n+# define nokprobe_inline\tinline\n+#endif\n #endif /* __LINUX_COMPILER_H */\n-- \n2.7.4\n\n"
  },
  {
    "path": "package/boot/uboot-lantiq/patches/0029-net-Use_packed_structures-for_networking.patch",
    "content": "From 704f3acfcf55343043bbed01c5fb0a0094a68e8a Mon Sep 17 00:00:00 2001\nFrom: Denis Pynkin <denis.pynkin@collabora.com>\nDate: Fri, 21 Jul 2017 19:28:42 +0300\nSubject: [PATCH] net: Use packed structures for networking\n\nPXE boot is broken with GCC 7.1 due option '-fstore-merging' enabled\nby default for '-O2':\n\nBOOTP broadcast 1\ndata abort\npc : [<8ff8bb30>]          lr : [<00004f1f>]\nreloc pc : [<17832b30>]    lr : [<878abf1f>]\nsp : 8f558bc0  ip : 00000000     fp : 8ffef5a4\nr10: 8ffed248  r9 : 8f558ee0     r8 : 8ffef594\nr7 : 0000000e  r6 : 8ffed700     r5 : 00000000  r4 : 8ffed74e\nr3 : 00060101  r2 : 8ffed230     r1 : 8ffed706  r0 : 00000ddd\nFlags: nzcv  IRQs off  FIQs off  Mode SVC_32\nResetting CPU ...\n\nCore reason is usage of structures for network headers without packed\nattribute.\n\nReviewed-by: Yauheni Kaliuta <yauheni.kaliuta@redhat.com>\nSigned-off-by: Denis Pynkin <denis.pynkin@collabora.com>\nAcked-by: Joe Hershberger <joe.hershberger@ni.com>\n---\n include/net.h | 14 +++++++-------\n net/bootp.h   |  2 +-\n net/dns.h     |  2 +-\n net/nfs.h     |  2 +-\n net/sntp.h    |  2 +-\n 5 files changed, 11 insertions(+), 11 deletions(-)\n\n--- a/include/net.h\n+++ b/include/net.h\n@@ -203,7 +203,7 @@ struct ethernet_hdr {\n \tuchar\t\tet_dest[6];\t/* Destination node\t\t*/\n \tuchar\t\tet_src[6];\t/* Source node\t\t\t*/\n \tushort\t\tet_protlen;\t/* Protocol or length\t\t*/\n-};\n+} __attribute__((packed));\n \n /* Ethernet header size */\n #define ETHER_HDR_SIZE\t(sizeof(struct ethernet_hdr))\n@@ -219,7 +219,7 @@ struct e802_hdr {\n \tuchar\t\tet_snap2;\n \tuchar\t\tet_snap3;\n \tushort\t\tet_prot;\t/* 802 protocol\t\t\t*/\n-};\n+} __attribute__((packed));\n \n /* 802 + SNAP + ethernet header size */\n #define E802_HDR_SIZE\t(sizeof(struct e802_hdr))\n@@ -233,7 +233,7 @@ struct vlan_ethernet_hdr {\n \tushort\t\tvet_vlan_type;\t/* PROT_VLAN\t\t\t*/\n \tushort\t\tvet_tag;\t/* TAG of VLAN\t\t\t*/\n \tushort\t\tvet_type;\t/* protocol type\t\t*/\n-};\n+} __attribute__((packed));\n \n /* VLAN Ethernet header size */\n #define VLAN_ETHER_HDR_SIZE\t(sizeof(struct vlan_ethernet_hdr))\n@@ -260,7 +260,7 @@ struct ip_hdr {\n \tushort\t\tip_sum;\t\t/* checksum\t\t\t*/\n \tIPaddr_t\tip_src;\t\t/* Source IP address\t\t*/\n \tIPaddr_t\tip_dst;\t\t/* Destination IP address\t*/\n-};\n+} __attribute__((packed));\n \n #define IP_OFFS\t\t0x1fff /* ip offset *= 8 */\n #define IP_FLAGS\t0xe000 /* first 3 bits */\n@@ -288,7 +288,7 @@ struct ip_udp_hdr {\n \tushort\t\tudp_dst;\t/* UDP destination port\t\t*/\n \tushort\t\tudp_len;\t/* Length of UDP packet\t\t*/\n \tushort\t\tudp_xsum;\t/* Checksum\t\t\t*/\n-};\n+} __attribute__((packed));\n \n #define IP_UDP_HDR_SIZE\t\t(sizeof(struct ip_udp_hdr))\n #define UDP_HDR_SIZE\t\t(IP_UDP_HDR_SIZE - IP_HDR_SIZE)\n@@ -327,7 +327,7 @@ struct arp_hdr {\n \tuchar\t\tar_tha[];\t/* Target hardware address\t*/\n \tuchar\t\tar_tpa[];\t/* Target protocol address\t*/\n #endif /* 0 */\n-};\n+} __attribute__((packed));\n \n #define ARP_HDR_SIZE\t(8+20)\t\t/* Size assuming ethernet\t*/\n \n@@ -362,7 +362,7 @@ struct icmp_hdr {\n \t\t} frag;\n \t\tuchar data[0];\n \t} un;\n-};\n+} __attribute__((packed));\n \n #define ICMP_HDR_SIZE\t\t(sizeof(struct icmp_hdr))\n #define IP_ICMP_HDR_SIZE\t(IP_HDR_SIZE + ICMP_HDR_SIZE)\n--- a/net/bootp.h\n+++ b/net/bootp.h\n@@ -49,7 +49,7 @@ struct Bootp_t {\n \tchar\t\tbp_sname[64];\t/* Server host name\t\t*/\n \tchar\t\tbp_file[128];\t/* Boot file name\t\t*/\n \tchar\t\tbp_vend[OPT_FIELD_SIZE]; /* Vendor information\t*/\n-};\n+} __attribute__((packed));\n \n #define BOOTP_HDR_SIZE\tsizeof(struct Bootp_t)\n \n--- a/net/dns.h\n+++ b/net/dns.h\n@@ -29,7 +29,7 @@ struct header {\n \tuint16_t\tnauth;\t\t/* Authority PRs */\n \tuint16_t\tnother;\t\t/* Other PRs */\n \tunsigned char\tdata[1];\t/* Data, variable length */\n-};\n+} __attribute__((packed));\n \n extern void DnsStart(void);\t\t/* Begin DNS */\n \n--- a/net/sntp.h\n+++ b/net/sntp.h\n@@ -51,7 +51,7 @@ struct sntp_pkt_t {\n \tunsigned long long originate_timestamp;\n \tunsigned long long receive_timestamp;\n \tunsigned long long transmit_timestamp;\n-};\n+} __attribute__((packed));\n \n extern void SntpStart(void);\t/* Begin SNTP */\n \n--- a/net/nfs.h\n+++ b/net/nfs.h\n@@ -68,7 +68,7 @@ struct rpc_t {\n \t\t\tuint32_t data[19];\n \t\t} reply;\n \t} u;\n-};\n+} __attribute__((packed));\n extern void NfsStart(void);\t/* Begin NFS */\n \n \n"
  },
  {
    "path": "package/boot/uboot-lantiq/patches/0030-lzma-force-8bit-reads.patch",
    "content": "From a40a6e16ed76e5e26a0f60226b64c311d4a62c9f Mon Sep 17 00:00:00 2001\nFrom: Mathias Kresin <dev@kresin.me>\nDate: Sun, 31 Oct 2021 23:04:54 +0100\nSubject: [PATCH] lzma: force 8bit reads\n\nAt least since gcc 7.3.0 (OpenWrt 18.06) lwr/lwl are used in the\nassembly of LzmaProps_Decode. While the decission made by the compiler\nlooks perfect fine, it triggers some obscure hang on lantiq danube-s\nv1.5 with MX29LV640EB NOR flash chips.\n\nOnly if the offset 1 is used, the hang can be observed. Using any other\noffset works fine:\n\n  lwl s0,0(a1) - s0 == 0x6d000080\n  lwl s0,1(a1) - hangs\n  lwl s0,2(a1) - s0 == 0x0080xxxx\n  lwl s0,3(a1) - s0 == 0x80xxxxxx\n\nIt isn't clear whether it is a limitation of the flash chip, the EBU or\nsomething else.\n\nForce 8bit reads to prevent gcc optimizing the read with lwr/lwl\ninstructions.\n\nSigned-off-by: Mathias Kresin <dev@kresin.me>\n---\n lib/lzma/LzmaDec.c | 3 ++-\n 1 file changed, 2 insertions(+), 1 deletion(-)\n\n--- a/lib/lzma/LzmaDec.c\n+++ b/lib/lzma/LzmaDec.c\n@@ -7,6 +7,7 @@\n #include \"LzmaDec.h\"\n \n #include <linux/string.h>\n+#include <asm/io.h>\n \n #define kNumTopBits 24\n #define kTopValue ((UInt32)1 << kNumTopBits)\n@@ -703,7 +704,7 @@ static ELzmaDummy LzmaDec_TryDummy(const\n \n static void LzmaDec_InitRc(CLzmaDec *p, const Byte *data)\n {\n-  p->code = ((UInt32)data[1] << 24) | ((UInt32)data[2] << 16) | ((UInt32)data[3] << 8) | ((UInt32)data[4]);\n+  p->code = ((UInt32)readb(&data[1]) << 24) | ((UInt32)readb(&data[2]) << 16) | ((UInt32)readb(&data[3]) << 8) | ((UInt32)readb(&data[4]));\n   p->range = 0xFFFFFFFF;\n   p->needFlush = 0;\n }\n@@ -929,7 +930,7 @@ SRes LzmaProps_Decode(CLzmaProps *p, con\n   if (size < LZMA_PROPS_SIZE)\n     return SZ_ERROR_UNSUPPORTED;\n   else\n-    dicSize = data[1] | ((UInt32)data[2] << 8) | ((UInt32)data[3] << 16) | ((UInt32)data[4] << 24);\n+    dicSize = readb(&data[1]) | ((UInt32)readb(&data[2]) << 8) | ((UInt32)readb(&data[3]) << 16) | ((UInt32)readb(&data[4]) << 24);\n \n   if (dicSize < LZMA_DIC_MIN)\n     dicSize = LZMA_DIC_MIN;\n"
  },
  {
    "path": "package/boot/uboot-lantiq/patches/0031-dma-lantiq-fix-out-of-bounds-cache-invalidate.patch",
    "content": "From d9527989b2d63749d6c6678fa3a1b658eb26c225 Mon Sep 17 00:00:00 2001\nFrom: Mathias Kresin <dev@kresin.me>\nDate: Tue, 2 Nov 2021 21:24:29 +0100\nSubject: [PATCH] dma: lantiq: fix out of bounds cache invalidate\n\nWith gcc10 the variables are placed more tightly to each other, which\nuncovers a long existing bug in the lantiq DMA code. It can be observed\nwhen using tftpboot with the filename parameter, which gets reset during\nthe tftpboot execution.\n\nNetRxPackets[] points to cache line size aligned addresses. In\nltq_eth_rx_packet_align() the address NetRxPackets[] points to is\nincreased by LTQ_ETH_IP_ALIGN and the resulting not cache aligned\naddress is used further on. While doing so, the length/size is never\nupdated.\n\nThe \"not cache aligned address\" + len/size for a cache aligned address\nis passed to invalidate_dcache_range(). Hence, invalidate_dcache_range()\ninvalidates the next 32 bit as well, which flashes the BootFile variable\nas well.\n\n   variable BootFile is at address: 0x83ffe12c\n   NetRxPackets[] points to 0x83ffdb20 (len is 0x600)\n   data points to: 0x83ffdb22 (len is 0x600)\n\n   ltq_dma_dcache_inv: 0x83ffdb22 (for len 0x600)\n   invalidate_dcache_range: 0x83ffdb20 to 0x83ffe120 (size: 32)\n   invalidate_dcache_range: 0x83ffdb20 to 0x83ffdb40 (Bootfile: a.bin)\n   ...\n   invalidate_dcache_range: 0x83ffe100 to 0x83ffe120 (Bootfile: a.bin)\n   invalidate_dcache_range: 0x83ffe120 to 0x83ffe140 (Bootfile: )\n\nIn ltq_dma_tx_map() and ltq_dma_rx_map() the start address passed to\nltq_dma_dcache_wb_inv() is incorrect. By considering the offset, the\nstart address passed to flush_dcache_range() is always aligned to 32, 64\nor 128 bytes dependent on configured DMA burst size.\n\nSigned-off-by: Mathias Kresin <dev@kresin.me>\n---\n drivers/dma/lantiq_dma.c | 4 ++--\n 1 file changed, 2 insertions(+), 2 deletions(-)\n\n--- a/drivers/dma/lantiq_dma.c\n+++ b/drivers/dma/lantiq_dma.c\n@@ -280,7 +280,7 @@ int ltq_dma_rx_map(struct ltq_dma_device\n \n \toffset = dma_addr % ltq_dma_burst_align(dev->rx_burst_len);\n \n-\tltq_dma_dcache_inv(data, len);\n+\tltq_dma_dcache_inv(data - offset, len);\n \n #if 0\n \tprintf(\"%s: index %d, data %p, dma_addr %08x, offset %u, len %d\\n\",\n@@ -355,7 +355,7 @@ int ltq_dma_tx_map(struct ltq_dma_device\n \t\t__func__, index, desc, data, dma_addr, offset, len);\n #endif\n \n-\tltq_dma_dcache_wb_inv(data, len);\n+\tltq_dma_dcache_wb_inv(data - offset, len);\n \n \tdesc->addr = dma_addr - offset;\n \tdesc->ctl = DMA_DESC_OWN | DMA_DESC_SOP | DMA_DESC_EOP |\n"
  },
  {
    "path": "package/boot/uboot-lantiq/patches/0032-MIPS-lantiq-danube-fix-SPL-boot.patch",
    "content": "From 65f1f160139c2bac83650c9c7c4aee4e5fd74c7c Mon Sep 17 00:00:00 2001\nFrom: Mathias Kresin <dev@kresin.me>\nDate: Sun, 2 May 2021 02:03:05 +0200\nSubject: [PATCH] MIPS: lantiq: danube: fix SPL boot\n\nOn danube we only have 0x6800 bytes of usable SRAM. Everything behind\ncan't be written to and a SPL u-boot locks up during boot.\n\nSigned-off-by: Mathias Kresin <dev@kresin.me>\nReviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>\n---\n arch/mips/include/asm/arch-danube/config.h | 4 ++--\n 1 file changed, 2 insertions(+), 2 deletions(-)\n\n--- a/arch/mips/include/asm/arch-danube/config.h\n+++ b/arch/mips/include/asm/arch-danube/config.h\n@@ -61,7 +61,7 @@\n \n /* SRAM */\n #define CONFIG_SYS_SRAM_BASE\t\t0xBE1A0000\n-#define CONFIG_SYS_SRAM_SIZE\t\t0x10000\n+#define CONFIG_SYS_SRAM_SIZE\t\t0x6800\n \n /* ASC/UART driver and console */\n #define CONFIG_LANTIQ_SERIAL\n@@ -117,7 +117,7 @@\n #define CONFIG_CMD_NET\n #endif\n \n-#define CONFIG_SPL_MAX_SIZE\t\t(32 * 1024)\n+#define CONFIG_SPL_MAX_SIZE\t\t(18 * 1024)\n #define CONFIG_SPL_BSS_MAX_SIZE\t\t(8 * 1024)\n #define CONFIG_SPL_STACK_MAX_SIZE\t(8 * 1024)\n #define CONFIG_SPL_MALLOC_MAX_SIZE\t(32 * 1024)\n"
  },
  {
    "path": "package/boot/uboot-lantiq/patches/0033-MIPS-lantiq-reduce-stack-size.patch",
    "content": "From ad739ffebf689abdbcddbe4e1b0bf847d7931a92 Mon Sep 17 00:00:00 2001\nFrom: Mathias Kresin <dev@kresin.me>\nDate: Fri, 20 Jan 2017 13:59:53 +0100\nSubject: [PATCH] MIPS: lantiq: reduce stack size\n\nOn lantiq a lot of stuff expects to be loaded to and executed at\n0x80002000, including our own second stage bootloader.\n\nFor all build u-boots, the initial stack pointer is at 0x80008000. After\nloading data to 0x80002000, every further stack operation corrupts the\nloaded code.\n\nSet the initial stack pointer to 0x80002000, to not overwrite code\nloaded in memory. A stack of 0x2000 bytes has been proven as enough in\nall done tests.\n\nSigned-off-by: Mathias Kresin <dev@kresin.me>\n---\n arch/mips/include/asm/arch-arx100/config.h | 2 +-\n arch/mips/include/asm/arch-danube/config.h | 2 +-\n arch/mips/include/asm/arch-vrx200/config.h | 2 +-\n 3 files changed, 3 insertions(+), 3 deletions(-)\n\n--- a/arch/mips/include/asm/arch-arx100/config.h\n+++ b/arch/mips/include/asm/arch-arx100/config.h\n@@ -66,7 +66,7 @@\n #define CONFIG_SYS_MEMTEST_END\t\t0x82000000\n #define CONFIG_SYS_LOAD_ADDR\t\t0x81000000\n #define CONFIG_SYS_LOAD_SIZE\t\t(2 * 1024 * 1024)\n-#define CONFIG_SYS_INIT_SP_OFFSET\t(32 * 1024)\n+#define CONFIG_SYS_INIT_SP_OFFSET\t0x2000\n \n /* SRAM */\n #define CONFIG_SYS_SRAM_BASE\t\t0xBE1A0000\n--- a/arch/mips/include/asm/arch-danube/config.h\n+++ b/arch/mips/include/asm/arch-danube/config.h\n@@ -57,7 +57,7 @@\n #define CONFIG_SYS_MEMTEST_END\t\t0x82000000\n #define CONFIG_SYS_LOAD_ADDR\t\t0x81000000\n #define CONFIG_SYS_LOAD_SIZE\t\t(2 * 1024 * 1024)\n-#define CONFIG_SYS_INIT_SP_OFFSET\t0x4000\n+#define CONFIG_SYS_INIT_SP_OFFSET\t0x2000\n \n /* SRAM */\n #define CONFIG_SYS_SRAM_BASE\t\t0xBE1A0000\n--- a/arch/mips/include/asm/arch-vrx200/config.h\n+++ b/arch/mips/include/asm/arch-vrx200/config.h\n@@ -69,7 +69,7 @@\n #define CONFIG_SYS_MEMTEST_END\t\t0x82000000\n #define CONFIG_SYS_LOAD_ADDR\t\t0x81000000\n #define CONFIG_SYS_LOAD_SIZE\t\t(2 * 1024 * 1024)\n-#define CONFIG_SYS_INIT_SP_OFFSET\t(32 * 1024)\n+#define CONFIG_SYS_INIT_SP_OFFSET\t0x2000\n \n /* SRAM */\n #define CONFIG_SYS_SRAM_BASE\t\t0xBE220000\n"
  },
  {
    "path": "package/boot/uboot-lantiq/patches/0100-MIPS-add-board-support-for-Easy-50712.patch",
    "content": "--- /dev/null\n+++ b/board/lantiq/easy50712/Makefile\n@@ -0,0 +1,27 @@\n+#\n+# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de\n+#\n+# SPDX-License-Identifier:\tGPL-2.0+\n+#\n+\n+include $(TOPDIR)/config.mk\n+\n+LIB\t= $(obj)lib$(BOARD).o\n+\n+COBJS\t= $(BOARD).o\n+\n+SRCS\t:= $(SOBJS:.o=.S) $(COBJS:.o=.c)\n+OBJS\t:= $(addprefix $(obj),$(COBJS))\n+SOBJS\t:= $(addprefix $(obj),$(SOBJS))\n+\n+$(LIB):\t$(obj).depend $(OBJS) $(SOBJS)\n+\t$(call cmd_link_o_target, $(OBJS) $(SOBJS))\n+\n+#########################################################################\n+\n+# defines $(obj).depend target\n+include $(SRCTREE)/rules.mk\n+\n+sinclude $(obj).depend\n+\n+#########################################################################\n--- /dev/null\n+++ b/board/lantiq/easy50712/config.mk\n@@ -0,0 +1,7 @@\n+#\n+# Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com\n+#\n+# SPDX-License-Identifier:\tGPL-2.0+\n+#\n+\n+PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR)\n--- /dev/null\n+++ b/board/lantiq/easy50712/ddr_settings.h\n@@ -0,0 +1,54 @@\n+/*\n+ * Copyright (C) 2007-2010 Lantiq Deutschland GmbH\n+ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#define MC_DC00_VALUE\t0x1B1B\n+#define MC_DC01_VALUE\t0x0\n+#define MC_DC02_VALUE\t0x0\n+#define MC_DC03_VALUE\t0x0\n+#define MC_DC04_VALUE\t0x0\n+#define MC_DC05_VALUE\t0x200\n+#define MC_DC06_VALUE\t0x605\n+#define MC_DC07_VALUE\t0x303\n+#define MC_DC08_VALUE\t0x102\n+#define MC_DC09_VALUE\t0x70a\n+#define MC_DC10_VALUE\t0x203\n+#define MC_DC11_VALUE\t0xc02\n+#define MC_DC12_VALUE\t0x1C8\n+#define MC_DC13_VALUE\t0x1\n+#define MC_DC14_VALUE\t0x0\n+#define MC_DC15_VALUE\t0x13c\n+#define MC_DC16_VALUE\t0xC800\n+#define MC_DC17_VALUE\t0xd\n+#define MC_DC18_VALUE\t0x300\n+#define MC_DC19_VALUE\t0x200\n+#define MC_DC20_VALUE\t0xA04\n+#define MC_DC21_VALUE\t0xd00\n+#define MC_DC22_VALUE\t0xd0d\n+#define MC_DC23_VALUE\t0x0\n+#define MC_DC24_VALUE\t0x62\n+#define MC_DC25_VALUE\t0x0\n+#define MC_DC26_VALUE\t0x0\n+#define MC_DC27_VALUE\t0x0\n+#define MC_DC28_VALUE\t0x510\n+#define MC_DC29_VALUE\t0x2d89\n+#define MC_DC30_VALUE\t0x8300\n+#define MC_DC31_VALUE\t0x0\n+#define MC_DC32_VALUE\t0x0\n+#define MC_DC33_VALUE\t0x0\n+#define MC_DC34_VALUE\t0x0\n+#define MC_DC35_VALUE\t0x0\n+#define MC_DC36_VALUE\t0x0\n+#define MC_DC37_VALUE\t0x0\n+#define MC_DC38_VALUE\t0x0\n+#define MC_DC39_VALUE\t0x0\n+#define MC_DC40_VALUE\t0x0\n+#define MC_DC41_VALUE\t0x0\n+#define MC_DC42_VALUE\t0x0\n+#define MC_DC43_VALUE\t0x0\n+#define MC_DC44_VALUE\t0x0\n+#define MC_DC45_VALUE\t0x500\n+#define MC_DC46_VALUE\t0x0\n--- /dev/null\n+++ b/board/lantiq/easy50712/easy50712.c\n@@ -0,0 +1,112 @@\n+/*\n+ * Copyright (C) 2010 Thomas Langer <thomas.langer@lantiq.com>\n+ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#include <common.h>\n+#include <switch.h>\n+#include <spi.h>\n+#include <asm/gpio.h>\n+#include <asm/lantiq/eth.h>\n+#include <asm/lantiq/reset.h>\n+#include <asm/lantiq/chipid.h>\n+\n+static void gpio_init(void)\n+{\n+\t/* SPI/CS output (low-active) for serial flash */\n+\tgpio_direction_output(22, 1);\n+\n+\t/* EBU.FL_CS1 as output for NAND CE */\n+\tgpio_set_altfunc(23, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);\n+\t/* EBU.FL_A23 as output for NAND CLE */\n+\tgpio_set_altfunc(24, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);\n+\t/* EBU.FL_A24 as output for NAND ALE */\n+\tgpio_set_altfunc(13, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);\n+\n+\t/* enable CLK_OUT2 for external switch */\n+\tgpio_set_altfunc(3, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);\n+}\n+\n+int board_early_init_f(void)\n+{\n+\tgpio_init();\n+\n+\treturn 0;\n+}\n+\n+int checkboard(void)\n+{\n+\tputs(\"Board: \" CONFIG_BOARD_NAME \"\\n\");\n+\tltq_chip_print_info();\n+\n+\treturn 0;\n+}\n+\n+static const struct ltq_eth_port_config eth_port_config[] = {\n+\t/* MAC0: Lantiq ADM6996I switch */\n+\t{ 0, 0x0, LTQ_ETH_PORT_SWITCH, PHY_INTERFACE_MODE_RMII },\n+};\n+\n+static const struct ltq_eth_board_config eth_board_config = {\n+\t.ports = eth_port_config,\n+\t.num_ports = ARRAY_SIZE(eth_port_config),\n+};\n+\n+int board_eth_init(bd_t *bis)\n+{\n+\treturn ltq_eth_initialize(&eth_board_config);\n+}\n+\n+static struct switch_device adm6996i_dev = {\n+\t.name = \"adm6996i\",\n+\t.cpu_port = 5,\n+\t.port_mask = 0xF,\n+};\n+\n+int board_switch_init(void)\n+{\n+\t/* Deactivate HRST line to release reset of ADM6996I switch */\n+\tltq_reset_once(LTQ_RESET_HARD, 200000);\n+\n+\t/* ADM6996I needs some time to come out of reset */\n+\t__udelay(50000);\n+\n+\treturn switch_device_register(&adm6996i_dev);\n+}\n+\n+int spi_cs_is_valid(unsigned int bus, unsigned int cs)\n+{\n+\tif (bus)\n+\t\treturn 0;\n+\n+\tswitch (cs) {\n+\tcase 2:\n+\t\treturn 1;\n+\tdefault:\n+\t\treturn 0;\n+\t}\n+}\n+\n+void spi_cs_activate(struct spi_slave *slave)\n+{\n+\tswitch (slave->cs) {\n+\tcase 2:\n+\t\tgpio_set_value(22, 0);\n+\t\tbreak;\n+\tdefault:\n+\t\tbreak;\n+\t}\n+}\n+\n+void spi_cs_deactivate(struct spi_slave *slave)\n+{\n+\tswitch (slave->cs) {\n+\tcase 2:\n+\t\tgpio_set_value(22, 1);\n+\t\tbreak;\n+\tdefault:\n+\t\tbreak;\n+\t}\n+}\n--- a/boards.cfg\n+++ b/boards.cfg\n@@ -502,6 +502,9 @@ Active  mips        mips32         au1x0\n Active  mips        mips32         au1x00      -               dbau1x00            dbau1550                             dbau1x00:DBAU1550                                                                                                                 Thomas Lange <thomas@corelatus.se>\n Active  mips        mips32         au1x00      -               dbau1x00            dbau1550_el                          dbau1x00:DBAU1550,SYS_LITTLE_ENDIAN                                                                                               Thomas Lange <thomas@corelatus.se>\n Active  mips        mips32         au1x00      -               pb1x00              pb1000                               pb1x00:PB1000                                                                                                                     -\n+Active  mips        mips32         danube      lantiq          easy50712           easy50712_nor                        easy50712:SYS_BOOT_NOR                                                                                                            Daniel Schwierzeck <daniel.schwierzeck@gmail.com>\n+Active  mips        mips32         danube      lantiq          easy50712           easy50712_norspl                     easy50712:SYS_BOOT_NORSPL                                                                                                         Daniel Schwierzeck <daniel.schwierzeck@gmail.com>\n+Active  mips        mips32         danube      lantiq          easy50712           easy50712_ram                        easy50712:SYS_BOOT_RAM                                                                                                            Daniel Schwierzeck <daniel.schwierzeck@gmail.com>\n Active  mips        mips32         incaip      -               incaip              incaip                               -                                                                                                                                 Wolfgang Denk <wd@denx.de>\n Active  mips        mips32         incaip      -               incaip              incaip_100MHz                        incaip:CPU_CLOCK_RATE=100000000                                                                                                   Wolfgang Denk <wd@denx.de>\n Active  mips        mips32         incaip      -               incaip              incaip_133MHz                        incaip:CPU_CLOCK_RATE=133000000                                                                                                   Wolfgang Denk <wd@denx.de>\n--- /dev/null\n+++ b/include/configs/easy50712.h\n@@ -0,0 +1,79 @@\n+/*\n+ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#ifndef __CONFIG_H\n+#define __CONFIG_H\n+\n+#define CONFIG_MACH_TYPE\t\"EASY50712\"\n+#define CONFIG_IDENT_STRING\t\" \"CONFIG_MACH_TYPE\n+#define CONFIG_BOARD_NAME\t\"Lantiq EASY50712 Danube Reference Board\"\n+\n+/* Configure SoC */\n+#define CONFIG_LTQ_SUPPORT_UART\t\t/* Enable ASC and UART */\n+\n+#define CONFIG_LTQ_SUPPORT_ETHERNET\t/* Enable ethernet */\n+\n+#define CONFIG_LTQ_SUPPORT_NOR_FLASH\t/* Have a parallel NOR flash */\n+\n+#define CONFIG_LTQ_SUPPORT_SPI_FLASH\n+#define CONFIG_SPI_FLASH_ATMEL\t\t/* Have an AT45DB321D serial flash */\n+\n+#define CONFIG_LTQ_SUPPORT_NAND_FLASH\n+\n+#define CONFIG_LTQ_SUPPORT_SPL_NOR_FLASH\t/* Build NOR flash SPL */\n+\n+#define CONFIG_LTQ_SPL_COMP_LZO\n+#define CONFIG_LTQ_SPL_CONSOLE\n+\n+/* Switch devices */\n+#define CONFIG_SWITCH_MULTI\n+#define CONFIG_SWITCH_ADM6996I\n+\n+/* Environment */\n+#define CONFIG_ENV_SPI_BUS\t\t0\n+#define CONFIG_ENV_SPI_CS\t\t2\n+#define CONFIG_ENV_SPI_MAX_HZ\t\t20000000\n+#define CONFIG_ENV_SPI_MODE\t\t0\n+\n+#if defined(CONFIG_SYS_BOOT_NOR)\n+#define CONFIG_ENV_IS_IN_FLASH\n+#define CONFIG_ENV_OVERWRITE\n+#define CONFIG_ENV_OFFSET\t\t(256 * 1024)\n+#define CONFIG_ENV_SECT_SIZE\t\t(64 * 1024)\n+#elif defined(CONFIG_SYS_BOOT_NORSPL)\n+#define CONFIG_ENV_IS_IN_FLASH\n+#define CONFIG_ENV_OVERWRITE\n+#define CONFIG_ENV_OFFSET\t\t(128 * 1024)\n+#define CONFIG_ENV_SECT_SIZE\t\t(64 * 1024)\n+#else\n+#define CONFIG_ENV_IS_NOWHERE\n+#endif\n+\n+#define CONFIG_ENV_SIZE\t\t\t(8 * 1024)\n+\n+#define CONFIG_LOADADDR\t\t\tCONFIG_SYS_LOAD_ADDR\n+\n+/* Console */\n+#define CONFIG_LTQ_ADVANCED_CONSOLE\n+#define CONFIG_BAUDRATE\t\t\t115200\n+#define CONFIG_CONSOLE_ASC\t\t1\n+#define CONFIG_CONSOLE_DEV\t\t\"ttyLTQ1\"\n+\n+/* Pull in default board configs for Lantiq XWAY Danube */\n+#include <asm/lantiq/config.h>\n+#include <asm/arch/config.h>\n+\n+/* Pull in default OpenWrt configs for Lantiq SoC */\n+#include \"openwrt-lantiq-common.h\"\n+\n+#define CONFIG_ENV_UPDATE_UBOOT_NOR\t\t\t\t\t\\\n+\t\"update-uboot-nor=run load-uboot-norspl-lzo write-uboot-nor\\0\"\n+\n+#define CONFIG_EXTRA_ENV_SETTINGS\t\\\n+\tCONFIG_ENV_LANTIQ_DEFAULTS\t\\\n+\tCONFIG_ENV_UPDATE_UBOOT_NOR\n+\n+#endif /* __CONFIG_H */\n"
  },
  {
    "path": "package/boot/uboot-lantiq/patches/0101-MIPS-add-board-support-for-Easy-80920.patch",
    "content": "--- /dev/null\n+++ b/board/lantiq/easy80920/Makefile\n@@ -0,0 +1,27 @@\n+#\n+# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de\n+#\n+# SPDX-License-Identifier:\tGPL-2.0+\n+#\n+\n+include $(TOPDIR)/config.mk\n+\n+LIB\t= $(obj)lib$(BOARD).o\n+\n+COBJS\t= $(BOARD).o\n+\n+SRCS\t:= $(SOBJS:.o=.S) $(COBJS:.o=.c)\n+OBJS\t:= $(addprefix $(obj),$(COBJS))\n+SOBJS\t:= $(addprefix $(obj),$(SOBJS))\n+\n+$(LIB):\t$(obj).depend $(OBJS) $(SOBJS)\n+\t$(call cmd_link_o_target, $(OBJS) $(SOBJS))\n+\n+#########################################################################\n+\n+# defines $(obj).depend target\n+include $(SRCTREE)/rules.mk\n+\n+sinclude $(obj).depend\n+\n+#########################################################################\n--- /dev/null\n+++ b/board/lantiq/easy80920/config.mk\n@@ -0,0 +1,7 @@\n+#\n+# Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com\n+#\n+# SPDX-License-Identifier:\tGPL-2.0+\n+#\n+\n+PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR)\n--- /dev/null\n+++ b/board/lantiq/easy80920/ddr_settings.h\n@@ -0,0 +1,69 @@\n+/*\n+ * Copyright (C) 2007-2010 Lantiq Deutschland GmbH\n+ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#define\tMC_CCR00_VALUE\t0x101\n+#define\tMC_CCR01_VALUE\t0x1000100\n+#define\tMC_CCR02_VALUE\t0x1010000\n+#define\tMC_CCR03_VALUE\t0x101\n+#define\tMC_CCR04_VALUE\t0x1000000\n+#define\tMC_CCR05_VALUE\t0x1000101\n+#define\tMC_CCR06_VALUE\t0x1000100\n+#define\tMC_CCR07_VALUE\t0x1010000\n+#define\tMC_CCR08_VALUE\t0x1000101\n+#define\tMC_CCR09_VALUE\t0x0\n+#define\tMC_CCR10_VALUE\t0x2000100\n+#define\tMC_CCR11_VALUE\t0x2000300\n+#define\tMC_CCR12_VALUE\t0x30000\n+#define\tMC_CCR13_VALUE\t0x202\n+#define\tMC_CCR14_VALUE\t0x7080A0F\n+#define\tMC_CCR15_VALUE\t0x2040F\n+#define\tMC_CCR16_VALUE\t0x40000\n+#define\tMC_CCR17_VALUE\t0x70102\n+#define\tMC_CCR18_VALUE\t0x4020002\n+#define\tMC_CCR19_VALUE\t0x30302\n+#define\tMC_CCR20_VALUE\t0x8000700\n+#define\tMC_CCR21_VALUE\t0x40F020A\n+#define\tMC_CCR22_VALUE\t0x0\n+#define\tMC_CCR23_VALUE\t0xC020000\n+#define\tMC_CCR24_VALUE\t0x4401B04\n+#define\tMC_CCR25_VALUE\t0x0\n+#define\tMC_CCR26_VALUE\t0x0\n+#define\tMC_CCR27_VALUE\t0x6420000\n+#define\tMC_CCR28_VALUE\t0x0\n+#define\tMC_CCR29_VALUE\t0x0\n+#define\tMC_CCR30_VALUE\t0x798\n+#define\tMC_CCR31_VALUE\t0x0\n+#define\tMC_CCR32_VALUE\t0x0\n+#define\tMC_CCR33_VALUE\t0x650000\n+#define\tMC_CCR34_VALUE\t0x200C8\n+#define\tMC_CCR35_VALUE\t0x1D445D\n+#define\tMC_CCR36_VALUE\t0xC8\n+#define\tMC_CCR37_VALUE\t0xC351\n+#define\tMC_CCR38_VALUE\t0x0\n+#define\tMC_CCR39_VALUE\t0x141F04\n+#define\tMC_CCR40_VALUE\t0x142704\n+#define\tMC_CCR41_VALUE\t0x141b42\n+#define\tMC_CCR42_VALUE\t0x141b42\n+#define\tMC_CCR43_VALUE\t0x566504\n+#define\tMC_CCR44_VALUE\t0x566504\n+#define\tMC_CCR45_VALUE\t0x565F17\n+#define\tMC_CCR46_VALUE\t0x565F17\n+#define\tMC_CCR47_VALUE\t0x0\n+#define\tMC_CCR48_VALUE\t0x0\n+#define\tMC_CCR49_VALUE\t0x0\n+#define\tMC_CCR50_VALUE\t0x0\n+#define\tMC_CCR51_VALUE\t0x0\n+#define\tMC_CCR52_VALUE\t0x133\n+#define\tMC_CCR53_VALUE\t0xF3014B27\n+#define\tMC_CCR54_VALUE\t0xF3014B27\n+#define\tMC_CCR55_VALUE\t0xF3014B27\n+#define\tMC_CCR56_VALUE\t0xF3014B27\n+#define\tMC_CCR57_VALUE\t0x7800301\n+#define\tMC_CCR58_VALUE\t0x7800301\n+#define\tMC_CCR59_VALUE\t0x7800301\n+#define\tMC_CCR60_VALUE\t0x7800301\n+#define\tMC_CCR61_VALUE\t0x4\n--- /dev/null\n+++ b/board/lantiq/easy80920/easy80920.c\n@@ -0,0 +1,138 @@\n+/*\n+ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#include <common.h>\n+#include <spi.h>\n+#include <asm/gpio.h>\n+#include <asm/lantiq/eth.h>\n+#include <asm/lantiq/chipid.h>\n+#include <asm/lantiq/cpu.h>\n+#include <asm/arch/gphy.h>\n+\n+#if defined(CONFIG_SPL_BUILD)\n+#define do_gpio_init\t1\n+#define do_pll_init\t1\n+#define do_dcdc_init\t0\n+#elif defined(CONFIG_SYS_BOOT_RAM)\n+#define do_gpio_init\t1\n+#define do_pll_init\t0\n+#define do_dcdc_init\t1\n+#elif defined(CONFIG_SYS_BOOT_NOR)\n+#define do_gpio_init\t1\n+#define do_pll_init\t1\n+#define do_dcdc_init\t1\n+#else\n+#define do_gpio_init\t0\n+#define do_pll_init\t0\n+#define do_dcdc_init\t1\n+#endif\n+\n+static void gpio_init(void)\n+{\n+\t/* SPI CS 0.4 to serial flash */\n+\tgpio_direction_output(10, 1);\n+\n+\t/* EBU.FL_CS1 as output for NAND CE */\n+\tgpio_set_altfunc(23, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);\n+\t/* EBU.FL_A23 as output for NAND CLE */\n+\tgpio_set_altfunc(24, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);\n+\t/* EBU.FL_A24 as output for NAND ALE */\n+\tgpio_set_altfunc(13, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);\n+\t/* GPIO 3.0 as input for NAND Ready Busy */\n+\tgpio_set_altfunc(48, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_IN);\n+\t/* GPIO 3.1 as output for NAND Read */\n+\tgpio_set_altfunc(49, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);\n+}\n+\n+int board_early_init_f(void)\n+{\n+\tif (do_gpio_init)\n+\t\tgpio_init();\n+\n+\tif (do_pll_init)\n+\t\tltq_pll_init();\n+\n+\tif (do_dcdc_init)\n+\t\tltq_dcdc_init(0x7F);\n+\n+\treturn 0;\n+}\n+\n+int checkboard(void)\n+{\n+\tputs(\"Board: \" CONFIG_BOARD_NAME \"\\n\");\n+\tltq_chip_print_info();\n+\n+\treturn 0;\n+}\n+\n+static const struct ltq_eth_port_config eth_port_config[] = {\n+\t/* GMAC0: external Lantiq PEF7071 10/100/1000 PHY for LAN port 0 */\n+\t{ 0, 0x0, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_RGMII },\n+\t/* GMAC1: external Lantiq PEF7071 10/100/1000 PHY for LAN port 1 */\n+\t{ 1, 0x1, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_RGMII },\n+\t/* GMAC2: internal GPHY0 with 10/100/1000 firmware for LAN port 2 */\n+\t{ 2, 0x11, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_GMII },\n+\t/* GMAC3: unused */\n+\t{ 3, 0x0, LTQ_ETH_PORT_NONE, PHY_INTERFACE_MODE_NONE },\n+\t/* GMAC4: internal GPHY1 with 10/100/1000 firmware for LAN port 3 */\n+\t{ 4, 0x13, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_GMII },\n+\t/* GMAC5: external Lantiq PEF7071 10/100/1000 PHY for WANoE port */\n+\t{ 5, 0x5, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_RGMII },\n+};\n+\n+static const struct ltq_eth_board_config eth_board_config = {\n+\t.ports = eth_port_config,\n+\t.num_ports = ARRAY_SIZE(eth_port_config),\n+};\n+\n+int board_eth_init(bd_t * bis)\n+{\n+\tconst enum ltq_gphy_clk clk = LTQ_GPHY_CLK_25MHZ_PLL0;\n+\tconst ulong fw_addr = 0x80FF0000;\n+\n+\tltq_gphy_phy11g_a1x_load(fw_addr);\n+\n+\tltq_cgu_gphy_clk_src(clk);\n+\n+\tltq_rcu_gphy_boot(0, fw_addr);\n+\tltq_rcu_gphy_boot(1, fw_addr);\n+\n+\treturn ltq_eth_initialize(&eth_board_config);\n+}\n+\n+int spi_cs_is_valid(unsigned int bus, unsigned int cs)\n+{\n+\tif (bus)\n+\t\treturn 0;\n+\n+\tif (cs == 4)\n+\t\treturn 1;\n+\n+\treturn 0;\n+}\n+\n+void spi_cs_activate(struct spi_slave *slave)\n+{\n+\tswitch (slave->cs) {\n+\tcase 4:\n+\t\tgpio_set_value(10, 0);\n+\t\tbreak;\n+\tdefault:\n+\t\tbreak;\n+\t}\n+}\n+\n+void spi_cs_deactivate(struct spi_slave *slave)\n+{\n+\tswitch (slave->cs) {\n+\tcase 4:\n+\t\tgpio_set_value(10, 1);\n+\t\tbreak;\n+\tdefault:\n+\t\tbreak;\n+\t}\n+}\n--- a/boards.cfg\n+++ b/boards.cfg\n@@ -509,6 +509,11 @@ Active  mips        mips32         incai\n Active  mips        mips32         incaip      -               incaip              incaip_100MHz                        incaip:CPU_CLOCK_RATE=100000000                                                                                                   Wolfgang Denk <wd@denx.de>\n Active  mips        mips32         incaip      -               incaip              incaip_133MHz                        incaip:CPU_CLOCK_RATE=133000000                                                                                                   Wolfgang Denk <wd@denx.de>\n Active  mips        mips32         incaip      -               incaip              incaip_150MHz                        incaip:CPU_CLOCK_RATE=150000000                                                                                                   Wolfgang Denk <wd@denx.de>\n+Active  mips        mips32         vrx200      lantiq          easy80920           easy80920_nandspl                    easy80920:SYS_BOOT_NANDSPL                                                                                                        Daniel Schwierzeck <daniel.schwierzeck@gmail.com>\n+Active  mips        mips32         vrx200      lantiq          easy80920           easy80920_nor                        easy80920:SYS_BOOT_NOR                                                                                                            Daniel Schwierzeck <daniel.schwierzeck@gmail.com>\n+Active  mips        mips32         vrx200      lantiq          easy80920           easy80920_norspl                     easy80920:SYS_BOOT_NORSPL                                                                                                         Daniel Schwierzeck <daniel.schwierzeck@gmail.com>\n+Active  mips        mips32         vrx200      lantiq          easy80920           easy80920_ram                        easy80920:SYS_BOOT_RAM                                                                                                            Daniel Schwierzeck <daniel.schwierzeck@gmail.com>\n+Active  mips        mips32         vrx200      lantiq          easy80920           easy80920_sfspl                      easy80920:SYS_BOOT_SFSPL                                                                                                          Daniel Schwierzeck <daniel.schwierzeck@gmail.com>\n Active  mips        mips64         -           -               qemu-mips           qemu_mips64                          qemu-mips64:SYS_BIG_ENDIAN                                                                                                        -\n Active  mips        mips64         -           -               qemu-mips           qemu_mips64el                        qemu-mips64:SYS_LITTLE_ENDIAN                                                                                                     -\n Active  nds32       n1213          ag101       AndesTech       adp-ag101           adp-ag101                            -                                                                                                                                 Andes <uboot@andestech.com>\n--- /dev/null\n+++ b/include/configs/easy80920.h\n@@ -0,0 +1,109 @@\n+/*\n+ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#ifndef __CONFIG_H\n+#define __CONFIG_H\n+\n+#define CONFIG_MACH_TYPE\t\"EASY80920\"\n+#define CONFIG_IDENT_STRING\t\" \"CONFIG_MACH_TYPE\n+#define CONFIG_BOARD_NAME\t\"Lantiq EASY80920 VRX200 Family Board\"\n+\n+/* Configure SoC */\n+#define CONFIG_LTQ_SUPPORT_UART\t\t/* Enable ASC and UART */\n+\n+#define CONFIG_LTQ_SUPPORT_ETHERNET\t/* Enable ethernet */\n+\n+#define CONFIG_LTQ_SUPPORT_NOR_FLASH\t/* Have a parallel NOR flash */\n+\n+#define CONFIG_LTQ_SUPPORT_SPI_FLASH\n+#define CONFIG_SPI_FLASH_MACRONIX\t/* Have a MX29LV620 serial flash */\n+\n+#define CONFIG_LTQ_SUPPORT_NAND_FLASH\n+\n+#define CONFIG_LTQ_SUPPORT_SPL_SPI_FLASH\t/* Build SPI flash SPL */\n+#define CONFIG_SPL_SPI_BUS\t\t0\n+#define CONFIG_SPL_SPI_CS\t\t4\n+#define CONFIG_SPL_SPI_MAX_HZ\t\t25000000\n+#define CONFIG_SPL_SPI_MODE\t\t0\n+\n+#define CONFIG_LTQ_SUPPORT_SPL_NOR_FLASH\t/* Build NOR flash SPL */\n+\n+#define CONFIG_LTQ_SUPPORT_SPL_NAND_FLASH\t/* Build NAND flash SPL */\n+#define CONFIG_SYS_NAND_PAGE_COUNT\t128\n+#define CONFIG_SYS_NAND_PAGE_SIZE\t2048\n+#define CONFIG_SYS_NAND_OOBSIZE\t\t64\n+#define CONFIG_SYS_NAND_BLOCK_SIZE\t(256 * 1024)\n+#define CONFIG_SYS_NAND_BAD_BLOCK_POS\tNAND_LARGE_BADBLOCK_POS\n+#define CONFIG_SYS_NAND_U_BOOT_OFFS\t0x4000\n+\n+#define CONFIG_LTQ_SPL_COMP_LZO\n+#define CONFIG_LTQ_SPL_CONSOLE\n+\n+#define CONFIG_SYS_DRAM_PROBE\n+\n+/* Environment */\n+#define CONFIG_ENV_SPI_BUS\t\tCONFIG_SPL_SPI_BUS\n+#define CONFIG_ENV_SPI_CS\t\tCONFIG_SPL_SPI_CS\n+#define CONFIG_ENV_SPI_MAX_HZ\t\tCONFIG_SPL_SPI_MAX_HZ\n+#define CONFIG_ENV_SPI_MODE\t\tCONFIG_SPL_SPI_MODE\n+\n+#if defined(CONFIG_SYS_BOOT_NOR)\n+#define CONFIG_ENV_IS_IN_FLASH\n+#define CONFIG_ENV_OVERWRITE\n+#define CONFIG_ENV_OFFSET\t\t(384 * 1024)\n+#define CONFIG_ENV_SECT_SIZE\t\t(64 * 1024)\n+#elif defined(CONFIG_SYS_BOOT_NORSPL)\n+#define CONFIG_ENV_IS_IN_FLASH\n+#define CONFIG_ENV_OVERWRITE\n+#define CONFIG_ENV_OFFSET\t\t(192 * 1024)\n+#define CONFIG_ENV_SECT_SIZE\t\t(64 * 1024)\n+#elif defined(CONFIG_SYS_BOOT_SFSPL)\n+#define CONFIG_ENV_IS_IN_SPI_FLASH\n+#define CONFIG_ENV_OVERWRITE\n+#define CONFIG_ENV_OFFSET\t\t(192 * 1024)\n+#define CONFIG_ENV_SECT_SIZE\t\t(64 * 1024)\n+#elif defined(CONFIG_SYS_BOOT_NANDSPL)\n+#define CONFIG_ENV_IS_IN_NAND\n+#define CONFIG_ENV_OVERWRITE\n+#define CONFIG_ENV_OFFSET\t\t(256 * 1024)\n+#define CONFIG_ENV_SECT_SIZE\t\t(256 * 1024)\n+#else\n+#define CONFIG_ENV_IS_NOWHERE\n+#endif\n+\n+#define CONFIG_ENV_SIZE\t\t\t(8 * 1024)\n+\n+#define CONFIG_LOADADDR\t\t\tCONFIG_SYS_LOAD_ADDR\n+\n+/* Console */\n+#define CONFIG_LTQ_ADVANCED_CONSOLE\n+#define CONFIG_BAUDRATE\t\t\t115200\n+#define CONFIG_CONSOLE_ASC\t\t1\n+#define CONFIG_CONSOLE_DEV\t\t\"ttyLTQ1\"\n+\n+/* Pull in default board configs for Lantiq XWAY VRX200 */\n+#include <asm/lantiq/config.h>\n+#include <asm/arch/config.h>\n+\n+/* Pull in default OpenWrt configs for Lantiq SoC */\n+#include \"openwrt-lantiq-common.h\"\n+\n+#define CONFIG_ENV_UPDATE_UBOOT_NOR\t\t\t\t\t\\\n+\t\"update-uboot-nor=run load-uboot-norspl-lzo write-uboot-nor\\0\"\n+\n+#define CONFIG_ENV_UPDATE_UBOOT_SF\t\t\t\t\t\\\n+\t\"update-uboot-sf=run load-uboot-sfspl-lzo write-uboot-sf\\0\"\n+\n+#define CONFIG_ENV_UPDATE_UBOOT_NAND\t\t\t\t\t\\\n+\t\"update-uboot-nand=run load-uboot-nandspl-lzo write-uboot-nand\\0\"\n+\n+#define CONFIG_EXTRA_ENV_SETTINGS\t\\\n+\tCONFIG_ENV_LANTIQ_DEFAULTS\t\\\n+\tCONFIG_ENV_UPDATE_UBOOT_NOR\t\\\n+\tCONFIG_ENV_UPDATE_UBOOT_SF\t\\\n+\tCONFIG_ENV_UPDATE_UBOOT_NAND\n+\n+#endif /* __CONFIG_H */\n"
  },
  {
    "path": "package/boot/uboot-lantiq/patches/0102-MIPS-add-board-support-for-Arcadyan-ARV4519PW.patch",
    "content": "From 9f915cf9550a6234adecaf3031c2b279835e14af Mon Sep 17 00:00:00 2001\nFrom: Luka Perkov <luka@openwrt.org>\nDate: Sat, 2 Mar 2013 23:34:00 +0100\nSubject: MIPS: add board support for Arcadyan ARV4519\n\nSigned-off-by: Luka Perkov <luka@openwrt.org>\nSigned-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>\n\n--- /dev/null\n+++ b/board/arcadyan/arv4519pw/Makefile\n@@ -0,0 +1,27 @@\n+#\n+# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de\n+#\n+# SPDX-License-Identifier:\tGPL-2.0+\n+#\n+\n+include $(TOPDIR)/config.mk\n+\n+LIB\t= $(obj)lib$(BOARD).o\n+\n+COBJS\t= $(BOARD).o\n+\n+SRCS\t:= $(SOBJS:.o=.S) $(COBJS:.o=.c)\n+OBJS\t:= $(addprefix $(obj),$(COBJS))\n+SOBJS\t:= $(addprefix $(obj),$(SOBJS))\n+\n+$(LIB):\t$(obj).depend $(OBJS) $(SOBJS)\n+\t$(call cmd_link_o_target, $(OBJS) $(SOBJS))\n+\n+#########################################################################\n+\n+# defines $(obj).depend target\n+include $(SRCTREE)/rules.mk\n+\n+sinclude $(obj).depend\n+\n+#########################################################################\n--- /dev/null\n+++ b/board/arcadyan/arv4519pw/arv4519pw.c\n@@ -0,0 +1,51 @@\n+/*\n+ * Copyright (C) 2012 Luka Perkov <luka@openwrt.org>\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#include <common.h>\n+#include <switch.h>\n+#include <asm/gpio.h>\n+#include <asm/lantiq/eth.h>\n+#include <asm/lantiq/reset.h>\n+#include <asm/lantiq/chipid.h>\n+\n+int board_early_init_f(void)\n+{\n+\treturn 0;\n+}\n+\n+int checkboard(void)\n+{\n+\tputs(\"Board: \" CONFIG_BOARD_NAME \"\\n\");\n+\tltq_chip_print_info();\n+\n+\treturn 0;\n+}\n+\n+static const struct ltq_eth_port_config eth_port_config[] = {\n+\t/* MAC0: Atheros ar8216 switch */\n+\t{ 0, 0x0, LTQ_ETH_PORT_SWITCH, PHY_INTERFACE_MODE_NONE },\n+};\n+\n+static const struct ltq_eth_board_config eth_board_config = {\n+\t.ports = eth_port_config,\n+\t.num_ports = ARRAY_SIZE(eth_port_config),\n+};\n+\n+int board_eth_init(bd_t *bis)\n+{\n+\treturn ltq_eth_initialize(&eth_board_config);\n+}\n+\n+static struct switch_device ar8216_dev = {\n+\t.name = \"ar8216\",\n+\t.cpu_port = 0,\n+\t.port_mask = 0xF,\n+};\n+\n+int board_switch_init(void)\n+{\n+\treturn switch_device_register(&ar8216_dev);\n+}\n--- /dev/null\n+++ b/board/arcadyan/arv4519pw/config.mk\n@@ -0,0 +1,7 @@\n+#\n+# Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com\n+#\n+# SPDX-License-Identifier:\tGPL-2.0+\n+#\n+\n+PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR)\n--- /dev/null\n+++ b/board/arcadyan/arv4519pw/ddr_settings.h\n@@ -0,0 +1,55 @@\n+/*\n+ * Copyright (C) 2012-2013 Luka Perkov <luka@openwrt.org>\n+ *\n+ * This file has been generated with lantiq_ram_extract_magic.awk script.\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#define MC_DC00_VALUE\t0x1B1B\n+#define MC_DC01_VALUE\t0x0\n+#define MC_DC02_VALUE\t0x0\n+#define MC_DC03_VALUE\t0x0\n+#define MC_DC04_VALUE\t0x0\n+#define MC_DC05_VALUE\t0x200\n+#define MC_DC06_VALUE\t0x605\n+#define MC_DC07_VALUE\t0x303\n+#define MC_DC08_VALUE\t0x102\n+#define MC_DC09_VALUE\t0x70A\n+#define MC_DC10_VALUE\t0x203\n+#define MC_DC11_VALUE\t0xC02\n+#define MC_DC12_VALUE\t0x1C8\n+#define MC_DC13_VALUE\t0x1\n+#define MC_DC14_VALUE\t0x0\n+#define MC_DC15_VALUE\t0x131\n+#define MC_DC16_VALUE\t0xC800\n+#define MC_DC17_VALUE\t0xD\n+#define MC_DC18_VALUE\t0x301\n+#define MC_DC19_VALUE\t0x200\n+#define MC_DC20_VALUE\t0xA04\n+#define MC_DC21_VALUE\t0x1700\n+#define MC_DC22_VALUE\t0x1717\n+#define MC_DC23_VALUE\t0x0\n+#define MC_DC24_VALUE\t0x5A\n+#define MC_DC25_VALUE\t0x0\n+#define MC_DC26_VALUE\t0x0\n+#define MC_DC27_VALUE\t0x0\n+#define MC_DC28_VALUE\t0x510\n+#define MC_DC29_VALUE\t0x4E20\n+#define MC_DC30_VALUE\t0x8235\n+#define MC_DC31_VALUE\t0x0\n+#define MC_DC32_VALUE\t0x0\n+#define MC_DC33_VALUE\t0x0\n+#define MC_DC34_VALUE\t0x0\n+#define MC_DC35_VALUE\t0x0\n+#define MC_DC36_VALUE\t0x0\n+#define MC_DC37_VALUE\t0x0\n+#define MC_DC38_VALUE\t0x0\n+#define MC_DC39_VALUE\t0x0\n+#define MC_DC40_VALUE\t0x0\n+#define MC_DC41_VALUE\t0x0\n+#define MC_DC42_VALUE\t0x0\n+#define MC_DC43_VALUE\t0x0\n+#define MC_DC44_VALUE\t0x0\n+#define MC_DC45_VALUE\t0x500\n+#define MC_DC46_VALUE\t0x0\n--- a/boards.cfg\n+++ b/boards.cfg\n@@ -502,6 +502,9 @@ Active  mips        mips32         au1x0\n Active  mips        mips32         au1x00      -               dbau1x00            dbau1550                             dbau1x00:DBAU1550                                                                                                                 Thomas Lange <thomas@corelatus.se>\n Active  mips        mips32         au1x00      -               dbau1x00            dbau1550_el                          dbau1x00:DBAU1550,SYS_LITTLE_ENDIAN                                                                                               Thomas Lange <thomas@corelatus.se>\n Active  mips        mips32         au1x00      -               pb1x00              pb1000                               pb1x00:PB1000                                                                                                                     -\n+Active  mips        mips32         danube      arcadyan        arv4519pw           arv4519pw_brn                        arv4519pw:SYS_BOOT_BRN                                                                                                            Luka Perkov <luka@openwrt.org>\n+Active  mips        mips32         danube      arcadyan        arv4519pw           arv4519pw_nor                        arv4519pw:SYS_BOOT_NOR                                                                                                            Luka Perkov <luka@openwrt.org>\n+Active  mips        mips32         danube      arcadyan        arv4519pw           arv4519pw_ram                        arv4519pw:SYS_BOOT_RAM                                                                                                            Luka Perkov <luka@openwrt.org>\n Active  mips        mips32         danube      lantiq          easy50712           easy50712_nor                        easy50712:SYS_BOOT_NOR                                                                                                            Daniel Schwierzeck <daniel.schwierzeck@gmail.com>\n Active  mips        mips32         danube      lantiq          easy50712           easy50712_norspl                     easy50712:SYS_BOOT_NORSPL                                                                                                         Daniel Schwierzeck <daniel.schwierzeck@gmail.com>\n Active  mips        mips32         danube      lantiq          easy50712           easy50712_ram                        easy50712:SYS_BOOT_RAM                                                                                                            Daniel Schwierzeck <daniel.schwierzeck@gmail.com>\n--- /dev/null\n+++ b/include/configs/arv4519pw.h\n@@ -0,0 +1,69 @@\n+/*\n+ * Copyright (C) 2012-2013 Luka Perkov <luka@openwrt.org>\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#ifndef __CONFIG_H\n+#define __CONFIG_H\n+\n+#define CONFIG_MACH_TYPE\t\"ARV4519PW\"\n+#define CONFIG_IDENT_STRING\t\" \"CONFIG_MACH_TYPE\n+#define CONFIG_BOARD_NAME\t\"Arcadyan ARV4519PW\"\n+\n+/* Configure SoC */\n+#define CONFIG_LTQ_SUPPORT_UART\t\t/* Enable ASC and UART */\n+\n+#define CONFIG_LTQ_SUPPORT_ETHERNET\t/* Enable ethernet */\n+\n+#define CONFIG_LTQ_SUPPORT_NOR_FLASH\t/* Have a parallel NOR flash */\n+\n+#define CONFIG_SYS_BOOTM_LEN\t\t0x1000000\t/* 16 MB */\n+\n+/* Switch devices */\n+#define CONFIG_SWITCH_MULTI\n+#define CONFIG_SWITCH_AR8216\n+\n+/* Environment */\n+#if defined(CONFIG_SYS_BOOT_NOR)\n+#define CONFIG_ENV_IS_IN_FLASH\n+#define CONFIG_ENV_OVERWRITE\n+#define CONFIG_ENV_OFFSET\t\t(192 * 1024)\n+#define CONFIG_ENV_SECT_SIZE\t\t(64 * 1024)\n+#else\n+#define CONFIG_ENV_IS_NOWHERE\n+#endif\n+\n+#define CONFIG_ENV_SIZE\t\t\t(8 * 1024)\n+#define CONFIG_LOADADDR\t\t\tCONFIG_SYS_LOAD_ADDR\n+\n+/* Brnboot loadable image */\n+#if defined(CONFIG_SYS_BOOT_BRN)\n+#define CONFIG_SYS_TEXT_BASE\t\t0x80002000\n+#define CONFIG_SKIP_LOWLEVEL_INIT\n+#define CONFIG_SYS_DISABLE_CACHE\n+#define CONFIG_ENV_OVERWRITE 1\n+#endif\n+\n+/* Console */\n+#define CONFIG_LTQ_ADVANCED_CONSOLE\n+#define CONFIG_BAUDRATE\t\t\t115200\n+#define CONFIG_CONSOLE_ASC\t\t1\n+#define CONFIG_CONSOLE_DEV\t\t\"ttyLTQ1\"\n+\n+/* Pull in default board configs for Lantiq XWAY Danube */\n+#include <asm/lantiq/config.h>\n+#include <asm/arch/config.h>\n+\n+/* Pull in default OpenWrt configs for Lantiq SoC */\n+#include \"openwrt-lantiq-common.h\"\n+\n+#define CONFIG_ENV_UPDATE_UBOOT_NOR\t\t\\\n+\t\"update-uboot-nor=run load-uboot-nor write-uboot-nor\\0\"\n+\n+#define CONFIG_EXTRA_ENV_SETTINGS\t\\\n+\tCONFIG_ENV_LANTIQ_DEFAULTS\t\\\n+\tCONFIG_ENV_UPDATE_UBOOT_NOR\t\\\n+\t\"kernel_addr=0xB0040000\\0\"\n+\n+#endif /* __CONFIG_H */\n"
  },
  {
    "path": "package/boot/uboot-lantiq/patches/0103-MIPS-add-board-support-for-Arcadyan-ARV7518PW.patch",
    "content": "From 54a31b334162e8dc2ea891057ddeab42978db8b3 Mon Sep 17 00:00:00 2001\nFrom: Luka Perkov <luka@openwrt.org>\nDate: Sat, 2 Mar 2013 23:34:00 +0100\nSubject: MIPS: add board support for Arcadyan ARV7518\n\nSigned-off-by: Luka Perkov <luka@openwrt.org>\nSigned-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>\n\n--- /dev/null\n+++ b/board/arcadyan/arv7518pw/Makefile\n@@ -0,0 +1,27 @@\n+#\n+# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de\n+#\n+# SPDX-License-Identifier:\tGPL-2.0+\n+#\n+\n+include $(TOPDIR)/config.mk\n+\n+LIB\t= $(obj)lib$(BOARD).o\n+\n+COBJS\t= $(BOARD).o\n+\n+SRCS\t:= $(SOBJS:.o=.S) $(COBJS:.o=.c)\n+OBJS\t:= $(addprefix $(obj),$(COBJS))\n+SOBJS\t:= $(addprefix $(obj),$(SOBJS))\n+\n+$(LIB):\t$(obj).depend $(OBJS) $(SOBJS)\n+\t$(call cmd_link_o_target, $(OBJS) $(SOBJS))\n+\n+#########################################################################\n+\n+# defines $(obj).depend target\n+include $(SRCTREE)/rules.mk\n+\n+sinclude $(obj).depend\n+\n+#########################################################################\n--- /dev/null\n+++ b/board/arcadyan/arv7518pw/arv7518pw.c\n@@ -0,0 +1,51 @@\n+/*\n+ * Copyright (C) 2012 Luka Perkov <luka@openwrt.org>\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#include <common.h>\n+#include <switch.h>\n+#include <asm/gpio.h>\n+#include <asm/lantiq/eth.h>\n+#include <asm/lantiq/reset.h>\n+#include <asm/lantiq/chipid.h>\n+\n+int board_early_init_f(void)\n+{\n+\treturn 0;\n+}\n+\n+int checkboard(void)\n+{\n+\tputs(\"Board: \" CONFIG_BOARD_NAME \"\\n\");\n+\tltq_chip_print_info();\n+\n+\treturn 0;\n+}\n+\n+static const struct ltq_eth_port_config eth_port_config[] = {\n+\t/* MAC0: Atheros ar8216 switch */\n+\t{ 0, 0x0, LTQ_ETH_PORT_SWITCH, PHY_INTERFACE_MODE_NONE },\n+};\n+\n+static const struct ltq_eth_board_config eth_board_config = {\n+\t.ports = eth_port_config,\n+\t.num_ports = ARRAY_SIZE(eth_port_config),\n+};\n+\n+int board_eth_init(bd_t *bis)\n+{\n+\treturn ltq_eth_initialize(&eth_board_config);\n+}\n+\n+static struct switch_device ar8216_dev = {\n+\t.name = \"ar8216\",\n+\t.cpu_port = 0,\n+\t.port_mask = 0xF,\n+};\n+\n+int board_switch_init(void)\n+{\n+\treturn switch_device_register(&ar8216_dev);\n+}\n--- /dev/null\n+++ b/board/arcadyan/arv7518pw/config.mk\n@@ -0,0 +1,7 @@\n+#\n+# Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com\n+#\n+# SPDX-License-Identifier:\tGPL-2.0+\n+#\n+\n+PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR)\n--- /dev/null\n+++ b/board/arcadyan/arv7518pw/ddr_settings.h\n@@ -0,0 +1,55 @@\n+/*\n+ * Copyright (C) 2012-2013 Luka Perkov <luka@openwrt.org>\n+ *\n+ * This file has been generated with lantiq_ram_extract_magic.awk script.\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#define MC_DC00_VALUE\t0x1B1B\n+#define MC_DC01_VALUE\t0x0\n+#define MC_DC02_VALUE\t0x0\n+#define MC_DC03_VALUE\t0x0\n+#define MC_DC04_VALUE\t0x0\n+#define MC_DC05_VALUE\t0x200\n+#define MC_DC06_VALUE\t0x605\n+#define MC_DC07_VALUE\t0x303\n+#define MC_DC08_VALUE\t0x102\n+#define MC_DC09_VALUE\t0x70A\n+#define MC_DC10_VALUE\t0x203\n+#define MC_DC11_VALUE\t0xC02\n+#define MC_DC12_VALUE\t0x1C8\n+#define MC_DC13_VALUE\t0x1\n+#define MC_DC14_VALUE\t0x0\n+#define MC_DC15_VALUE\t0x134\n+#define MC_DC16_VALUE\t0xC800\n+#define MC_DC17_VALUE\t0xD\n+#define MC_DC18_VALUE\t0x301\n+#define MC_DC19_VALUE\t0x200\n+#define MC_DC20_VALUE\t0xA03\n+#define MC_DC21_VALUE\t0x1400\n+#define MC_DC22_VALUE\t0x1414\n+#define MC_DC23_VALUE\t0x0\n+#define MC_DC24_VALUE\t0x5B\n+#define MC_DC25_VALUE\t0x0\n+#define MC_DC26_VALUE\t0x0\n+#define MC_DC27_VALUE\t0x0\n+#define MC_DC28_VALUE\t0x510\n+#define MC_DC29_VALUE\t0x4E20\n+#define MC_DC30_VALUE\t0x8235\n+#define MC_DC31_VALUE\t0x0\n+#define MC_DC32_VALUE\t0x0\n+#define MC_DC33_VALUE\t0x0\n+#define MC_DC34_VALUE\t0x0\n+#define MC_DC35_VALUE\t0x0\n+#define MC_DC36_VALUE\t0x0\n+#define MC_DC37_VALUE\t0x0\n+#define MC_DC38_VALUE\t0x0\n+#define MC_DC39_VALUE\t0x0\n+#define MC_DC40_VALUE\t0x0\n+#define MC_DC41_VALUE\t0x0\n+#define MC_DC42_VALUE\t0x0\n+#define MC_DC43_VALUE\t0x0\n+#define MC_DC44_VALUE\t0x0\n+#define MC_DC45_VALUE\t0x500\n+#define MC_DC46_VALUE\t0x0\n--- a/boards.cfg\n+++ b/boards.cfg\n@@ -505,6 +505,9 @@ Active  mips        mips32         au1x0\n Active  mips        mips32         danube      arcadyan        arv4519pw           arv4519pw_brn                        arv4519pw:SYS_BOOT_BRN                                                                                                            Luka Perkov <luka@openwrt.org>\n Active  mips        mips32         danube      arcadyan        arv4519pw           arv4519pw_nor                        arv4519pw:SYS_BOOT_NOR                                                                                                            Luka Perkov <luka@openwrt.org>\n Active  mips        mips32         danube      arcadyan        arv4519pw           arv4519pw_ram                        arv4519pw:SYS_BOOT_RAM                                                                                                            Luka Perkov <luka@openwrt.org>\n+Active  mips        mips32         danube      arcadyan        arv7518pw           arv7518pw_brn                        arv7518pw:SYS_BOOT_BRN                                                                                                            Luka Perkov <luka@openwrt.org>\n+Active  mips        mips32         danube      arcadyan        arv7518pw           arv7518pw_nor                        arv7518pw:SYS_BOOT_NOR                                                                                                            Luka Perkov <luka@openwrt.org>\n+Active  mips        mips32         danube      arcadyan        arv7518pw           arv7518pw_ram                        arv7518pw:SYS_BOOT_RAM                                                                                                            Luka Perkov <luka@openwrt.org>\n Active  mips        mips32         danube      lantiq          easy50712           easy50712_nor                        easy50712:SYS_BOOT_NOR                                                                                                            Daniel Schwierzeck <daniel.schwierzeck@gmail.com>\n Active  mips        mips32         danube      lantiq          easy50712           easy50712_norspl                     easy50712:SYS_BOOT_NORSPL                                                                                                         Daniel Schwierzeck <daniel.schwierzeck@gmail.com>\n Active  mips        mips32         danube      lantiq          easy50712           easy50712_ram                        easy50712:SYS_BOOT_RAM                                                                                                            Daniel Schwierzeck <daniel.schwierzeck@gmail.com>\n--- /dev/null\n+++ b/include/configs/arv7518pw.h\n@@ -0,0 +1,69 @@\n+/*\n+ * Copyright (C) 2012-2013 Luka Perkov <luka@openwrt.org>\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#ifndef __CONFIG_H\n+#define __CONFIG_H\n+\n+#define CONFIG_MACH_TYPE\t\"ARV7518PW\"\n+#define CONFIG_IDENT_STRING\t\" \"CONFIG_MACH_TYPE\n+#define CONFIG_BOARD_NAME\t\"Arcadyan ARV7518PW\"\n+\n+/* Configure SoC */\n+#define CONFIG_LTQ_SUPPORT_UART\t\t/* Enable ASC and UART */\n+\n+#define CONFIG_LTQ_SUPPORT_ETHERNET\t/* Enable ethernet */\n+\n+#define CONFIG_LTQ_SUPPORT_NOR_FLASH\t/* Have a parallel NOR flash */\n+\n+#define CONFIG_SYS_BOOTM_LEN\t\t0x1000000\t/* 16 MB */\n+\n+/* Switch devices */\n+#define CONFIG_SWITCH_MULTI\n+#define CONFIG_SWITCH_AR8216\n+\n+/* Environment */\n+#if defined(CONFIG_SYS_BOOT_NOR)\n+#define CONFIG_ENV_IS_IN_FLASH\n+#define CONFIG_ENV_OVERWRITE\n+#define CONFIG_ENV_OFFSET\t\t(192 * 1024)\n+#define CONFIG_ENV_SECT_SIZE\t\t(64 * 1024)\n+#else\n+#define CONFIG_ENV_IS_NOWHERE\n+#endif\n+\n+#define CONFIG_ENV_SIZE\t\t\t(8 * 1024)\n+#define CONFIG_LOADADDR\t\t\tCONFIG_SYS_LOAD_ADDR\n+\n+/* Brnboot loadable image */\n+#if defined(CONFIG_SYS_BOOT_BRN)\n+#define CONFIG_SYS_TEXT_BASE\t\t0x80002000\n+#define CONFIG_SKIP_LOWLEVEL_INIT\n+#define CONFIG_SYS_DISABLE_CACHE\n+#define CONFIG_ENV_OVERWRITE 1\n+#endif\n+\n+/* Console */\n+#define CONFIG_LTQ_ADVANCED_CONSOLE\n+#define CONFIG_BAUDRATE\t\t\t115200\n+#define CONFIG_CONSOLE_ASC\t\t1\n+#define CONFIG_CONSOLE_DEV\t\t\"ttyLTQ1\"\n+\n+/* Pull in default board configs for Lantiq XWAY Danube */\n+#include <asm/lantiq/config.h>\n+#include <asm/arch/config.h>\n+\n+/* Pull in default OpenWrt configs for Lantiq SoC */\n+#include \"openwrt-lantiq-common.h\"\n+\n+#define CONFIG_ENV_UPDATE_UBOOT_NOR\t\t\\\n+\t\"update-uboot-nor=run load-uboot-nor write-uboot-nor\\0\"\n+\n+#define CONFIG_EXTRA_ENV_SETTINGS\t\\\n+\tCONFIG_ENV_LANTIQ_DEFAULTS\t\\\n+\tCONFIG_ENV_UPDATE_UBOOT_NOR\t\\\n+\t\"kernel_addr=0xB0040000\\0\"\n+\n+#endif /* __CONFIG_H */\n"
  },
  {
    "path": "package/boot/uboot-lantiq/patches/0104-MIPS-add-board-support-for-AudioCodes-MP-252.patch",
    "content": "From 4bacfc80eae768be45f9ddf7588ec55281354648 Mon Sep 17 00:00:00 2001\nFrom: Daniel Golle <daniel.golle@gmail.com>\nDate: Fri, 8 Mar 2013 13:29:04 +0200\nSubject: MIPS: add board support for AudioCodes MP-252\n\nSigned-off-by: Daniel Golle <dgolle@allnet.de>\n\n--- /dev/null\n+++ b/board/audiocodes/acmp252/Makefile\n@@ -0,0 +1,27 @@\n+#\n+# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de\n+#\n+# SPDX-License-Identifier:\tGPL-2.0+\n+#\n+\n+include $(TOPDIR)/config.mk\n+\n+LIB\t= $(obj)lib$(BOARD).o\n+\n+COBJS\t= $(BOARD).o\n+\n+SRCS\t:= $(SOBJS:.o=.S) $(COBJS:.o=.c)\n+OBJS\t:= $(addprefix $(obj),$(COBJS))\n+SOBJS\t:= $(addprefix $(obj),$(SOBJS))\n+\n+$(LIB):\t$(obj).depend $(OBJS) $(SOBJS)\n+\t$(call cmd_link_o_target, $(OBJS) $(SOBJS))\n+\n+#########################################################################\n+\n+# defines $(obj).depend target\n+include $(SRCTREE)/rules.mk\n+\n+sinclude $(obj).depend\n+\n+#########################################################################\n--- /dev/null\n+++ b/board/audiocodes/acmp252/acmp252.c\n@@ -0,0 +1,66 @@\n+/*\n+ * Copyright (C) 2013 Daniel Golle <daniel.golle@gmail.com>\n+ * Copyright (C) 2011 Luka Perkov <luka@openwrt.org>\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#include <common.h>\n+#include <switch.h>\n+#include <asm/gpio.h>\n+#include <asm/lantiq/eth.h>\n+#include <asm/lantiq/reset.h>\n+#include <asm/lantiq/chipid.h>\n+\n+static void gpio_init(void)\n+{\n+\t/* Activate reset line of ADM6996I switch */\n+\tgpio_direction_output(19, 0);\n+}\n+\n+int board_early_init_f(void)\n+{\n+\tgpio_init();\n+\n+\treturn 0;\n+}\n+\n+int checkboard(void)\n+{\n+\tputs(\"Board: \" CONFIG_BOARD_NAME \"\\n\");\n+\tltq_chip_print_info();\n+\n+\treturn 0;\n+}\n+\n+static const struct ltq_eth_port_config eth_port_config[] = {\n+\t/* MAC0: Lantiq ADM6996I switch */\n+\t{ 0, 0x0, LTQ_ETH_PORT_SWITCH, PHY_INTERFACE_MODE_RMII },\n+};\n+\n+static const struct ltq_eth_board_config eth_board_config = {\n+\t.ports = eth_port_config,\n+\t.num_ports = ARRAY_SIZE(eth_port_config),\n+};\n+\n+int board_eth_init(bd_t *bis)\n+{\n+\treturn ltq_eth_initialize(&eth_board_config);\n+}\n+\n+static struct switch_device adm6996i_dev = {\n+\t.name = \"adm6996i\",\n+\t.cpu_port = 5,\n+\t.port_mask = 0xF,\n+};\n+\n+int board_switch_init(void)\n+{\n+\t/* Deactivate reset line of ADM6996I switch */\n+\tgpio_set_value(19, 1);\n+\n+\t/* ADM6996I needs some time to come out of reset */\n+\t__udelay(50000);\n+\n+\treturn switch_device_register(&adm6996i_dev);\n+}\n--- /dev/null\n+++ b/board/audiocodes/acmp252/config.mk\n@@ -0,0 +1,7 @@\n+#\n+# Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com\n+#\n+# SPDX-License-Identifier:\tGPL-2.0+\n+#\n+\n+PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR)\n--- /dev/null\n+++ b/board/audiocodes/acmp252/ddr_settings.h\n@@ -0,0 +1,55 @@\n+/*\n+ * Copyright (C) 2011-2013 Luka Perkov <luka@openwrt.org>\n+ *\n+ * This file has been generated with lantiq_ram_extract_magic.awk script.\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#define MC_DC00_VALUE\t0x1B1B\n+#define MC_DC01_VALUE\t0x0\n+#define MC_DC02_VALUE\t0x0\n+#define MC_DC03_VALUE\t0x0\n+#define MC_DC04_VALUE\t0x0\n+#define MC_DC05_VALUE\t0x200\n+#define MC_DC06_VALUE\t0x605\n+#define MC_DC07_VALUE\t0x403\n+#define MC_DC08_VALUE\t0x103\n+#define MC_DC09_VALUE\t0x80B\n+#define MC_DC10_VALUE\t0x304\n+#define MC_DC11_VALUE\t0xD03\n+#define MC_DC12_VALUE\t0x2C8\n+#define MC_DC13_VALUE\t0x1\n+#define MC_DC14_VALUE\t0x0\n+#define MC_DC15_VALUE\t0x13C\n+#define MC_DC16_VALUE\t0xC800\n+#define MC_DC17_VALUE\t0xD\n+#define MC_DC18_VALUE\t0x402\n+#define MC_DC19_VALUE\t0x200\n+#define MC_DC20_VALUE\t0xA03\n+#define MC_DC21_VALUE\t0x1700\n+#define MC_DC22_VALUE\t0x1717\n+#define MC_DC23_VALUE\t0x0\n+#define MC_DC24_VALUE\t0x5C\n+#define MC_DC25_VALUE\t0x0\n+#define MC_DC26_VALUE\t0x0\n+#define MC_DC27_VALUE\t0x0\n+#define MC_DC28_VALUE\t0x510\n+#define MC_DC29_VALUE\t0x2D93\n+#define MC_DC30_VALUE\t0x8300\n+#define MC_DC31_VALUE\t0x0\n+#define MC_DC32_VALUE\t0x0\n+#define MC_DC33_VALUE\t0x0\n+#define MC_DC34_VALUE\t0x0\n+#define MC_DC35_VALUE\t0x0\n+#define MC_DC36_VALUE\t0x0\n+#define MC_DC37_VALUE\t0x0\n+#define MC_DC38_VALUE\t0x0\n+#define MC_DC39_VALUE\t0x0\n+#define MC_DC40_VALUE\t0x0\n+#define MC_DC41_VALUE\t0x0\n+#define MC_DC42_VALUE\t0x0\n+#define MC_DC43_VALUE\t0x0\n+#define MC_DC44_VALUE\t0x0\n+#define MC_DC45_VALUE\t0x500\n+#define MC_DC46_VALUE\t0x0\n--- a/boards.cfg\n+++ b/boards.cfg\n@@ -508,6 +508,8 @@ Active  mips        mips32         danub\n Active  mips        mips32         danube      arcadyan        arv7518pw           arv7518pw_brn                        arv7518pw:SYS_BOOT_BRN                                                                                                            Luka Perkov <luka@openwrt.org>\n Active  mips        mips32         danube      arcadyan        arv7518pw           arv7518pw_nor                        arv7518pw:SYS_BOOT_NOR                                                                                                            Luka Perkov <luka@openwrt.org>\n Active  mips        mips32         danube      arcadyan        arv7518pw           arv7518pw_ram                        arv7518pw:SYS_BOOT_RAM                                                                                                            Luka Perkov <luka@openwrt.org>\n+Active  mips        mips32         danube      audiocodes      acmp252             acmp252_nor                          acmp252:SYS_BOOT_NOR                                                                                                              Daniel Golle <daniel.golle@gmail.com>\n+Active  mips        mips32         danube      audiocodes      acmp252             acmp252_ram                          acmp252:SYS_BOOT_RAM                                                                                                              Daniel Golle <daniel.golle@gmail.com>\n Active  mips        mips32         danube      lantiq          easy50712           easy50712_nor                        easy50712:SYS_BOOT_NOR                                                                                                            Daniel Schwierzeck <daniel.schwierzeck@gmail.com>\n Active  mips        mips32         danube      lantiq          easy50712           easy50712_norspl                     easy50712:SYS_BOOT_NORSPL                                                                                                         Daniel Schwierzeck <daniel.schwierzeck@gmail.com>\n Active  mips        mips32         danube      lantiq          easy50712           easy50712_ram                        easy50712:SYS_BOOT_RAM                                                                                                            Daniel Schwierzeck <daniel.schwierzeck@gmail.com>\n--- /dev/null\n+++ b/include/configs/acmp252.h\n@@ -0,0 +1,62 @@\n+/*\n+ * Copyright (C) 2013 Daniel Golle <daniel.golle@gmail.com>\n+ * Copyright (C) 2011 Luka Perkov <luka@openwrt.org>\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#ifndef __CONFIG_H\n+#define __CONFIG_H\n+\n+#define CONFIG_MACH_TYPE\t\"ACMP252\"\n+#define CONFIG_IDENT_STRING\t\" \"CONFIG_MACH_TYPE\n+#define CONFIG_BOARD_NAME\t\"AudioCodes MP-252\"\n+\n+/* Configure SoC */\n+#define CONFIG_LTQ_SUPPORT_UART\t\t/* Enable ASC and UART */\n+\n+#define CONFIG_LTQ_SUPPORT_ETHERNET\t/* Enable ethernet */\n+\n+#define CONFIG_LTQ_SUPPORT_NOR_FLASH\t/* Have a parallel NOR flash */\n+\n+#define CONFIG_SYS_BOOTM_LEN\t\t0x1000000\t/* 16 MB */\n+\n+/* Switch devices */\n+#define CONFIG_SWITCH_MULTI\n+#define CONFIG_SWITCH_ADM6996I\n+\n+/* Environment */\n+#if defined(CONFIG_SYS_BOOT_NOR)\n+#define CONFIG_ENV_IS_IN_FLASH\n+#define CONFIG_ENV_OVERWRITE\n+#define CONFIG_ENV_OFFSET\t\t(256 * 1024)\n+#define CONFIG_ENV_SECT_SIZE\t\t(128 * 1024)\n+#else\n+#define CONFIG_ENV_IS_NOWHERE\n+#endif\n+\n+#define CONFIG_ENV_SIZE\t\t\t(8 * 1024)\n+#define CONFIG_LOADADDR\t\t\tCONFIG_SYS_LOAD_ADDR\n+\n+/* Console */\n+#define CONFIG_LTQ_ADVANCED_CONSOLE\n+#define CONFIG_BAUDRATE\t\t\t115200\n+#define CONFIG_CONSOLE_ASC\t\t1\n+#define CONFIG_CONSOLE_DEV\t\t\"ttyLTQ1\"\n+\n+/* Pull in default board configs for Lantiq XWAY Danube */\n+#include <asm/lantiq/config.h>\n+#include <asm/arch/config.h>\n+\n+/* Pull in default OpenWrt configs for Lantiq SoC */\n+#include \"openwrt-lantiq-common.h\"\n+\n+#define CONFIG_ENV_UPDATE_UBOOT_NOR\t\t\\\n+\t\"update-uboot-nor=run load-uboot-nor write-uboot-nor\\0\"\n+\n+#define CONFIG_EXTRA_ENV_SETTINGS\t\\\n+\tCONFIG_ENV_LANTIQ_DEFAULTS\t\\\n+\tCONFIG_ENV_UPDATE_UBOOT_NOR\t\\\n+\t\"kernel_addr=0xB0040000\\0\"\n+\n+#endif /* __CONFIG_H */\n"
  },
  {
    "path": "package/boot/uboot-lantiq/patches/0105-MIPS-add-board-support-for-AVM-FritzBox-3370.patch",
    "content": "From 37a95ae4ba75407a26862ece6f48fa68aa6c5c78 Mon Sep 17 00:00:00 2001\nFrom: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>\nDate: Sat, 2 Mar 2013 23:34:00 +0100\nSubject: MIPS: add board support for AVM FritzBox 3370\n\nSigned-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>\n\n--- /dev/null\n+++ b/board/avm/fb3370/Makefile\n@@ -0,0 +1,28 @@\n+#\n+# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de\n+# Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com\n+#\n+# SPDX-License-Identifier:\tGPL-2.0+\n+#\n+\n+include $(TOPDIR)/config.mk\n+\n+LIB\t= $(obj)lib$(BOARD).o\n+\n+COBJS\t= $(BOARD).o\n+\n+SRCS\t:= $(SOBJS:.o=.S) $(COBJS:.o=.c)\n+OBJS\t:= $(addprefix $(obj),$(COBJS))\n+SOBJS\t:= $(addprefix $(obj),$(SOBJS))\n+\n+$(LIB):\t$(obj).depend $(OBJS) $(SOBJS)\n+\t$(call cmd_link_o_target, $(OBJS) $(SOBJS))\n+\n+#########################################################################\n+\n+# defines $(obj).depend target\n+include $(SRCTREE)/rules.mk\n+\n+sinclude $(obj).depend\n+\n+#########################################################################\n--- /dev/null\n+++ b/board/avm/fb3370/config.mk\n@@ -0,0 +1,7 @@\n+#\n+# Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com\n+#\n+# SPDX-License-Identifier:\tGPL-2.0+\n+#\n+\n+PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR)\n--- /dev/null\n+++ b/board/avm/fb3370/ddr_settings.h\n@@ -0,0 +1,69 @@\n+/*\n+ * Copyright (C) 2007-2010 Lantiq Deutschland GmbH\n+ * Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#define\tMC_CCR00_VALUE\t0x101\n+#define\tMC_CCR01_VALUE\t0x1000100\n+#define\tMC_CCR02_VALUE\t0x1010000\n+#define\tMC_CCR03_VALUE\t0x101\n+#define\tMC_CCR04_VALUE\t0x1000000\n+#define\tMC_CCR05_VALUE\t0x1000101\n+#define\tMC_CCR06_VALUE\t0x1000100\n+#define\tMC_CCR07_VALUE\t0x1010000\n+#define\tMC_CCR08_VALUE\t0x1000101\n+#define\tMC_CCR09_VALUE\t0x0\n+#define\tMC_CCR10_VALUE\t0x2000100\n+#define\tMC_CCR11_VALUE\t0x2000300\n+#define\tMC_CCR12_VALUE\t0x30000\n+#define\tMC_CCR13_VALUE\t0x202\n+#define\tMC_CCR14_VALUE\t0x7080A0F\n+#define\tMC_CCR15_VALUE\t0x2040F\n+#define\tMC_CCR16_VALUE\t0x40000\n+#define\tMC_CCR17_VALUE\t0x70102\n+#define\tMC_CCR18_VALUE\t0x4020002\n+#define\tMC_CCR19_VALUE\t0x30302\n+#define\tMC_CCR20_VALUE\t0x8000700\n+#define\tMC_CCR21_VALUE\t0x40F020A\n+#define\tMC_CCR22_VALUE\t0x0\n+#define\tMC_CCR23_VALUE\t0xC020000\n+#define\tMC_CCR24_VALUE\t0x4401B04\n+#define\tMC_CCR25_VALUE\t0x0\n+#define\tMC_CCR26_VALUE\t0x0\n+#define\tMC_CCR27_VALUE\t0x6420000\n+#define\tMC_CCR28_VALUE\t0x0\n+#define\tMC_CCR29_VALUE\t0x0\n+#define\tMC_CCR30_VALUE\t0x798\n+#define\tMC_CCR31_VALUE\t0x0\n+#define\tMC_CCR32_VALUE\t0x0\n+#define\tMC_CCR33_VALUE\t0x650000\n+#define\tMC_CCR34_VALUE\t0x200C8\n+#define\tMC_CCR35_VALUE\t0x1D445D\n+#define\tMC_CCR36_VALUE\t0xC8\n+#define\tMC_CCR37_VALUE\t0xC351\n+#define\tMC_CCR38_VALUE\t0x0\n+#define\tMC_CCR39_VALUE\t0x141F04\n+#define\tMC_CCR40_VALUE\t0x142704\n+#define\tMC_CCR41_VALUE\t0x141B42\n+#define\tMC_CCR42_VALUE\t0x141B42\n+#define\tMC_CCR43_VALUE\t0x566504\n+#define\tMC_CCR44_VALUE\t0x566504\n+#define\tMC_CCR45_VALUE\t0x565F17\n+#define\tMC_CCR46_VALUE\t0x565F17\n+#define\tMC_CCR47_VALUE\t0x0\n+#define\tMC_CCR48_VALUE\t0x0\n+#define\tMC_CCR49_VALUE\t0x0\n+#define\tMC_CCR50_VALUE\t0x0\n+#define\tMC_CCR51_VALUE\t0x0\n+#define\tMC_CCR52_VALUE\t0x133\n+#define\tMC_CCR53_VALUE\t0xF3014B27\n+#define\tMC_CCR54_VALUE\t0xF3014B27\n+#define\tMC_CCR55_VALUE\t0xF3014B27\n+#define\tMC_CCR56_VALUE\t0xF3014B27\n+#define\tMC_CCR57_VALUE\t0x7800301\n+#define\tMC_CCR58_VALUE\t0x7800301\n+#define\tMC_CCR59_VALUE\t0x7800301\n+#define\tMC_CCR60_VALUE\t0x7800301\n+#define\tMC_CCR61_VALUE\t0x4\n--- /dev/null\n+++ b/board/avm/fb3370/fb3370.c\n@@ -0,0 +1,138 @@\n+/*\n+ * Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#include <common.h>\n+#include <spi.h>\n+#include <asm/gpio.h>\n+#include <asm/lantiq/eth.h>\n+#include <asm/lantiq/chipid.h>\n+#include <asm/lantiq/cpu.h>\n+#include <asm/arch/gphy.h>\n+\n+#if defined(CONFIG_SPL_BUILD)\n+#define do_gpio_init\t1\n+#define do_pll_init\t1\n+#define do_dcdc_init\t0\n+#elif defined(CONFIG_SYS_BOOT_RAM)\n+#define do_gpio_init\t1\n+#define do_pll_init\t0\n+#define do_dcdc_init\t1\n+#elif defined(CONFIG_SYS_BOOT_NOR)\n+#define do_gpio_init\t1\n+#define do_pll_init\t1\n+#define do_dcdc_init\t1\n+#else\n+#define do_gpio_init\t0\n+#define do_pll_init\t0\n+#define do_dcdc_init\t1\n+#endif\n+\n+static void gpio_init(void)\n+{\n+\t/* SPI CS 0.4 to serial flash */\n+\tgpio_direction_output(10, 1);\n+\n+\t/* EBU.FL_CS1 as output for NAND CE */\n+\tgpio_set_altfunc(23, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);\n+\t/* EBU.FL_A23 as output for NAND CLE */\n+\tgpio_set_altfunc(24, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);\n+\t/* EBU.FL_A24 as output for NAND ALE */\n+\tgpio_set_altfunc(13, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);\n+\t/* GPIO 3.0 as input for NAND Ready Busy */\n+\tgpio_set_altfunc(48, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_IN);\n+\t/* GPIO 3.1 as output for NAND Read */\n+\tgpio_set_altfunc(49, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);\n+}\n+\n+int board_early_init_f(void)\n+{\n+\tif (do_gpio_init)\n+\t\tgpio_init();\n+\n+\tif (do_pll_init)\n+\t\tltq_pll_init();\n+\n+\tif (do_dcdc_init)\n+\t\tltq_dcdc_init(0x7F);\n+\n+\treturn 0;\n+}\n+\n+int checkboard(void)\n+{\n+\tputs(\"Board: \" CONFIG_BOARD_NAME \"\\n\");\n+\tltq_chip_print_info();\n+\n+\treturn 0;\n+}\n+\n+static const struct ltq_eth_port_config eth_port_config[] = {\n+\t/* GMAC0: external Lantiq PEF7071 10/100/1000 PHY for LAN port 0 */\n+\t{ 0, 0x0, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_RGMII },\n+\t/* GMAC1: external Lantiq PEF7071 10/100/1000 PHY for LAN port 1 */\n+\t{ 1, 0x1, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_RGMII },\n+\t/* GMAC2: internal GPHY0 with 10/100/1000 firmware for LAN port 2 */\n+\t{ 2, 0x11, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_GMII },\n+\t/* GMAC3: unused */\n+\t{ 3, 0x0, LTQ_ETH_PORT_NONE, PHY_INTERFACE_MODE_NONE },\n+\t/* GMAC4: internal GPHY1 with 10/100/1000 firmware for LAN port 3 */\n+\t{ 4, 0x13, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_GMII },\n+\t/* GMAC5: external Lantiq PEF7071 10/100/1000 PHY for WANoE port */\n+\t{ 5, 0x5, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_RGMII },\n+};\n+\n+static const struct ltq_eth_board_config eth_board_config = {\n+\t.ports = eth_port_config,\n+\t.num_ports = ARRAY_SIZE(eth_port_config),\n+};\n+\n+int board_eth_init(bd_t * bis)\n+{\n+\tconst enum ltq_gphy_clk clk = LTQ_GPHY_CLK_25MHZ_PLL0;\n+\tconst ulong fw_addr = 0x80FF0000;\n+\n+\tltq_gphy_phy11g_a1x_load(fw_addr);\n+\n+\tltq_cgu_gphy_clk_src(clk);\n+\n+\tltq_rcu_gphy_boot(0, fw_addr);\n+\tltq_rcu_gphy_boot(1, fw_addr);\n+\n+\treturn ltq_eth_initialize(&eth_board_config);\n+}\n+\n+int spi_cs_is_valid(unsigned int bus, unsigned int cs)\n+{\n+\tif (bus)\n+\t\treturn 0;\n+\n+\tif (cs == 4)\n+\t\treturn 1;\n+\n+\treturn 0;\n+}\n+\n+void spi_cs_activate(struct spi_slave *slave)\n+{\n+\tswitch (slave->cs) {\n+\tcase 4:\n+\t\tgpio_set_value(10, 0);\n+\t\tbreak;\n+\tdefault:\n+\t\tbreak;\n+\t}\n+}\n+\n+void spi_cs_deactivate(struct spi_slave *slave)\n+{\n+\tswitch (slave->cs) {\n+\tcase 4:\n+\t\tgpio_set_value(10, 1);\n+\t\tbreak;\n+\tdefault:\n+\t\tbreak;\n+\t}\n+}\n--- a/boards.cfg\n+++ b/boards.cfg\n@@ -517,6 +517,9 @@ Active  mips        mips32         incai\n Active  mips        mips32         incaip      -               incaip              incaip_100MHz                        incaip:CPU_CLOCK_RATE=100000000                                                                                                   Wolfgang Denk <wd@denx.de>\n Active  mips        mips32         incaip      -               incaip              incaip_133MHz                        incaip:CPU_CLOCK_RATE=133000000                                                                                                   Wolfgang Denk <wd@denx.de>\n Active  mips        mips32         incaip      -               incaip              incaip_150MHz                        incaip:CPU_CLOCK_RATE=150000000                                                                                                   Wolfgang Denk <wd@denx.de>\n+Active  mips        mips32         vrx200      avm             fb3370              fb3370_eva                           fb3370:SYS_BOOT_EVA                                                                                                               Daniel Schwierzeck <daniel.schwierzeck@gmail.com>\n+Active  mips        mips32         vrx200      avm             fb3370              fb3370_ram                           fb3370:SYS_BOOT_RAM                                                                                                               Daniel Schwierzeck <daniel.schwierzeck@gmail.com>\n+Active  mips        mips32         vrx200      avm             fb3370              fb3370_sfspl                         fb3370:SYS_BOOT_SFSPL                                                                                                             Daniel Schwierzeck <daniel.schwierzeck@gmail.com>\n Active  mips        mips32         vrx200      lantiq          easy80920           easy80920_nandspl                    easy80920:SYS_BOOT_NANDSPL                                                                                                        Daniel Schwierzeck <daniel.schwierzeck@gmail.com>\n Active  mips        mips32         vrx200      lantiq          easy80920           easy80920_nor                        easy80920:SYS_BOOT_NOR                                                                                                            Daniel Schwierzeck <daniel.schwierzeck@gmail.com>\n Active  mips        mips32         vrx200      lantiq          easy80920           easy80920_norspl                     easy80920:SYS_BOOT_NORSPL                                                                                                         Daniel Schwierzeck <daniel.schwierzeck@gmail.com>\n--- /dev/null\n+++ b/include/configs/fb3370.h\n@@ -0,0 +1,80 @@\n+/*\n+ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#ifndef __CONFIG_H\n+#define __CONFIG_H\n+\n+#define CONFIG_MACH_TYPE\t\"FB3370\"\n+#define CONFIG_IDENT_STRING\t\" \"CONFIG_MACH_TYPE\n+#define CONFIG_BOARD_NAME\t\"AVM FritzBox 3370\"\n+\n+/* Configure SoC */\n+#define CONFIG_LTQ_SUPPORT_UART\t\t\t/* Enable ASC and UART */\n+\n+#define CONFIG_LTQ_SUPPORT_ETHERNET\t\t/* Enable ethernet */\n+\n+#define CONFIG_LTQ_SUPPORT_SPI_FLASH\n+#define CONFIG_SPI_FLASH_MACRONIX\t\t/* Have a MX29LV620 serial flash */\n+\n+#define CONFIG_LTQ_SUPPORT_NAND_FLASH\n+\n+#define CONFIG_LTQ_SUPPORT_SPL_SPI_FLASH\t/* Build SPI flash SPL */\n+#define CONFIG_LTQ_SPL_COMP_LZO\t\t\t/* Compress SPL with LZO */\n+#define CONFIG_LTQ_SPL_CONSOLE\t\t\t/* Enable SPL console */\n+\n+#define CONFIG_SPL_SPI_BUS\t\t0\n+#define CONFIG_SPL_SPI_CS\t\t4\n+#define CONFIG_SPL_SPI_MAX_HZ\t\t25000000\n+#define CONFIG_SPL_SPI_MODE\t\t0\n+\n+#define CONFIG_SYS_DRAM_PROBE\n+\n+#define CONFIG_SYS_BOOTM_LEN          0x1000000       /* 16 MB */\n+\n+/* Environment */\n+#define CONFIG_ENV_SPI_BUS\t\tCONFIG_SPL_SPI_BUS\n+#define CONFIG_ENV_SPI_CS\t\tCONFIG_SPL_SPI_CS\n+#define CONFIG_ENV_SPI_MAX_HZ\t\tCONFIG_SPL_SPI_MAX_HZ\n+#define CONFIG_ENV_SPI_MODE\t\tCONFIG_SPL_SPI_MODE\n+\n+#if defined(CONFIG_SYS_BOOT_SFSPL)\n+#define CONFIG_ENV_IS_IN_SPI_FLASH\n+#define CONFIG_ENV_OVERWRITE\n+#define CONFIG_ENV_OFFSET\t\t(192 * 1024)\n+#define CONFIG_ENV_SECT_SIZE\t\t(64 * 1024)\n+#else\n+#define CONFIG_ENV_IS_NOWHERE\n+#endif\n+\n+#define CONFIG_ENV_SIZE\t\t\t(8 * 1024)\n+#define CONFIG_LOADADDR\t\t\tCONFIG_SYS_LOAD_ADDR\n+\n+#if defined(CONFIG_SYS_BOOT_EVA)\n+#define CONFIG_SYS_TEXT_BASE\t\t0x80100000\n+#define CONFIG_SKIP_LOWLEVEL_INIT\n+#endif\n+\n+/* Console */\n+#define CONFIG_LTQ_ADVANCED_CONSOLE\n+#define CONFIG_BAUDRATE\t\t\t115200\n+#define CONFIG_CONSOLE_ASC\t\t1\n+#define CONFIG_CONSOLE_DEV\t\t\"ttyLTQ1\"\n+\n+/* Pull in default board configs for Lantiq XWAY VRX200 */\n+#include <asm/lantiq/config.h>\n+#include <asm/arch/config.h>\n+\n+/* Pull in default OpenWrt configs for Lantiq SoC */\n+#include \"openwrt-lantiq-common.h\"\n+\n+#define CONFIG_ENV_UPDATE_UBOOT_SF\t\t\t\t\t\\\n+\t\"update-uboot-sf=run load-uboot-sfspl-lzo write-uboot-sf\\0\"\n+\n+#define CONFIG_EXTRA_ENV_SETTINGS\t\\\n+\tCONFIG_ENV_LANTIQ_DEFAULTS\t\\\n+\tCONFIG_ENV_UPDATE_UBOOT_SF\n+\n+#endif /* __CONFIG_H */\n"
  },
  {
    "path": "package/boot/uboot-lantiq/patches/0106-MIPS-add-board-support-for-Gigaset-SX76X.patch",
    "content": "From 9e9dec563e4d061e7b34d2d59a89eb05c60f43a7 Mon Sep 17 00:00:00 2001\nFrom: Luka Perkov <luka@openwrt.org>\nDate: Sat, 2 Mar 2013 23:34:00 +0100\nSubject: MIPS: add board support for Gigaset SX76X\n\nSigned-off-by: Luka Perkov <luka@openwrt.org>\nSigned-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>\n\n--- /dev/null\n+++ b/board/gigaset/sx76x/Makefile\n@@ -0,0 +1,27 @@\n+#\n+# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de\n+#\n+# SPDX-License-Identifier:\tGPL-2.0+\n+#\n+\n+include $(TOPDIR)/config.mk\n+\n+LIB\t= $(obj)lib$(BOARD).o\n+\n+COBJS\t= $(BOARD).o\n+\n+SRCS\t:= $(SOBJS:.o=.S) $(COBJS:.o=.c)\n+OBJS\t:= $(addprefix $(obj),$(COBJS))\n+SOBJS\t:= $(addprefix $(obj),$(SOBJS))\n+\n+$(LIB):\t$(obj).depend $(OBJS) $(SOBJS)\n+\t$(call cmd_link_o_target, $(OBJS) $(SOBJS))\n+\n+#########################################################################\n+\n+# defines $(obj).depend target\n+include $(SRCTREE)/rules.mk\n+\n+sinclude $(obj).depend\n+\n+#########################################################################\n--- /dev/null\n+++ b/board/gigaset/sx76x/config.mk\n@@ -0,0 +1,7 @@\n+#\n+# Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com\n+#\n+# SPDX-License-Identifier:\tGPL-2.0+\n+#\n+\n+PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR)\n--- /dev/null\n+++ b/board/gigaset/sx76x/ddr_settings.h\n@@ -0,0 +1,55 @@\n+/*\n+ * Copyright (C) 2011-2013 Luka Perkov <luka@openwrt.org>\n+ *\n+ * This file has been generated with lantiq_ram_extract_magic.awk script.\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#define MC_DC00_VALUE\t0x1B1B\n+#define MC_DC01_VALUE\t0x0\n+#define MC_DC02_VALUE\t0x0\n+#define MC_DC03_VALUE\t0x0\n+#define MC_DC04_VALUE\t0x0\n+#define MC_DC05_VALUE\t0x200\n+#define MC_DC06_VALUE\t0x605\n+#define MC_DC07_VALUE\t0x303\n+#define MC_DC08_VALUE\t0x202\n+#define MC_DC09_VALUE\t0x70A\n+#define MC_DC10_VALUE\t0x203\n+#define MC_DC11_VALUE\t0xC02\n+#define MC_DC12_VALUE\t0x1C8\n+#define MC_DC13_VALUE\t0x1\n+#define MC_DC14_VALUE\t0x0\n+#define MC_DC15_VALUE\t0xF3E\n+#define MC_DC16_VALUE\t0xC800\n+#define MC_DC17_VALUE\t0xD\n+#define MC_DC18_VALUE\t0x300\n+#define MC_DC19_VALUE\t0x200\n+#define MC_DC20_VALUE\t0xA04\n+#define MC_DC21_VALUE\t0xF00\n+#define MC_DC22_VALUE\t0xF0F\n+#define MC_DC23_VALUE\t0x0\n+#define MC_DC24_VALUE\t0x63\n+#define MC_DC25_VALUE\t0x0\n+#define MC_DC26_VALUE\t0x100\n+#define MC_DC27_VALUE\t0x0\n+#define MC_DC28_VALUE\t0x514\n+#define MC_DC29_VALUE\t0x2D89\n+#define MC_DC30_VALUE\t0x8300\n+#define MC_DC31_VALUE\t0x2002\n+#define MC_DC32_VALUE\t0x0\n+#define MC_DC33_VALUE\t0x0\n+#define MC_DC34_VALUE\t0x0\n+#define MC_DC35_VALUE\t0x0\n+#define MC_DC36_VALUE\t0x0\n+#define MC_DC37_VALUE\t0x0\n+#define MC_DC38_VALUE\t0x0\n+#define MC_DC39_VALUE\t0x0\n+#define MC_DC40_VALUE\t0x0\n+#define MC_DC41_VALUE\t0x0\n+#define MC_DC42_VALUE\t0x0\n+#define MC_DC43_VALUE\t0x0\n+#define MC_DC44_VALUE\t0x0\n+#define MC_DC45_VALUE\t0x500\n+#define MC_DC46_VALUE\t0x0\n--- /dev/null\n+++ b/board/gigaset/sx76x/sx76x.c\n@@ -0,0 +1,65 @@\n+/*\n+ * Copyright (C) 2011 Luka Perkov <luka@openwrt.org>\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#include <common.h>\n+#include <switch.h>\n+#include <asm/gpio.h>\n+#include <asm/lantiq/eth.h>\n+#include <asm/lantiq/reset.h>\n+#include <asm/lantiq/chipid.h>\n+\n+static void gpio_init(void)\n+{\n+\t/* Activate reset line of ADM6996I switch */\n+\tgpio_direction_output(19, 0);\n+}\n+\n+int board_early_init_f(void)\n+{\n+\tgpio_init();\n+\n+\treturn 0;\n+}\n+\n+int checkboard(void)\n+{\n+\tputs(\"Board: \" CONFIG_BOARD_NAME \"\\n\");\n+\tltq_chip_print_info();\n+\n+\treturn 0;\n+}\n+\n+static const struct ltq_eth_port_config eth_port_config[] = {\n+\t/* MAC0: Lantiq ADM6996I switch */\n+\t{ 0, 0x0, LTQ_ETH_PORT_SWITCH, PHY_INTERFACE_MODE_RMII },\n+};\n+\n+static const struct ltq_eth_board_config eth_board_config = {\n+\t.ports = eth_port_config,\n+\t.num_ports = ARRAY_SIZE(eth_port_config),\n+};\n+\n+int board_eth_init(bd_t *bis)\n+{\n+\treturn ltq_eth_initialize(&eth_board_config);\n+}\n+\n+static struct switch_device adm6996i_dev = {\n+\t.name = \"adm6996i\",\n+\t.cpu_port = 5,\n+\t.port_mask = 0xF,\n+};\n+\n+int board_switch_init(void)\n+{\n+\t/* Deactivate reset line of ADM6996I switch */\n+\tgpio_set_value(19, 1);\n+\n+\t/* ADM6996I needs some time to come out of reset */\n+\t__udelay(50000);\n+\n+\treturn switch_device_register(&adm6996i_dev);\n+}\n--- a/boards.cfg\n+++ b/boards.cfg\n@@ -510,6 +510,8 @@ Active  mips        mips32         danub\n Active  mips        mips32         danube      arcadyan        arv7518pw           arv7518pw_ram                        arv7518pw:SYS_BOOT_RAM                                                                                                            Luka Perkov <luka@openwrt.org>\n Active  mips        mips32         danube      audiocodes      acmp252             acmp252_nor                          acmp252:SYS_BOOT_NOR                                                                                                              Daniel Golle <daniel.golle@gmail.com>\n Active  mips        mips32         danube      audiocodes      acmp252             acmp252_ram                          acmp252:SYS_BOOT_RAM                                                                                                              Daniel Golle <daniel.golle@gmail.com>\n+Active  mips        mips32         danube      gigaset         sx76x               gigasx76x_nor                        sx76x:SYS_BOOT_NOR                                                                                                                Luka Perkov <luka@openwrt.org>\n+Active  mips        mips32         danube      gigaset         sx76x               gigasx76x_ram                        sx76x:SYS_BOOT_RAM                                                                                                                Luka Perkov <luka@openwrt.org>\n Active  mips        mips32         danube      lantiq          easy50712           easy50712_nor                        easy50712:SYS_BOOT_NOR                                                                                                            Daniel Schwierzeck <daniel.schwierzeck@gmail.com>\n Active  mips        mips32         danube      lantiq          easy50712           easy50712_norspl                     easy50712:SYS_BOOT_NORSPL                                                                                                         Daniel Schwierzeck <daniel.schwierzeck@gmail.com>\n Active  mips        mips32         danube      lantiq          easy50712           easy50712_ram                        easy50712:SYS_BOOT_RAM                                                                                                            Daniel Schwierzeck <daniel.schwierzeck@gmail.com>\n--- /dev/null\n+++ b/include/configs/sx76x.h\n@@ -0,0 +1,61 @@\n+/*\n+ * Copyright (C) 2011-2013 Luka Perkov <luka@openwrt.org>\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#ifndef __CONFIG_H\n+#define __CONFIG_H\n+\n+#define CONFIG_MACH_TYPE\t\"GIGASX76X\"\n+#define CONFIG_IDENT_STRING\t\" \"CONFIG_MACH_TYPE\n+#define CONFIG_BOARD_NAME\t\"Gigaset sx76x\"\n+\n+/* Configure SoC */\n+#define CONFIG_LTQ_SUPPORT_UART\t\t/* Enable ASC and UART */\n+\n+#define CONFIG_LTQ_SUPPORT_ETHERNET\t/* Enable ethernet */\n+\n+#define CONFIG_LTQ_SUPPORT_NOR_FLASH\t/* Have a parallel NOR flash */\n+\n+#define CONFIG_SYS_BOOTM_LEN\t\t0x1000000\t/* 16 MB */\n+\n+/* Switch devices */\n+#define CONFIG_SWITCH_MULTI\n+#define CONFIG_SWITCH_ADM6996I\n+\n+/* Environment */\n+#if defined(CONFIG_SYS_BOOT_NOR)\n+#define CONFIG_ENV_IS_IN_FLASH\n+#define CONFIG_ENV_OVERWRITE\n+#define CONFIG_ENV_OFFSET\t\t(256 * 1024)\n+#define CONFIG_ENV_SECT_SIZE\t\t(64 * 1024)\n+#else\n+#define CONFIG_ENV_IS_NOWHERE\n+#endif\n+\n+#define CONFIG_ENV_SIZE\t\t\t(8 * 1024)\n+#define CONFIG_LOADADDR\t\t\tCONFIG_SYS_LOAD_ADDR\n+\n+/* Console */\n+#define CONFIG_LTQ_ADVANCED_CONSOLE\n+#define CONFIG_BAUDRATE\t\t\t115200\n+#define CONFIG_CONSOLE_ASC\t\t1\n+#define CONFIG_CONSOLE_DEV\t\t\"ttyLTQ1\"\n+\n+/* Pull in default board configs for Lantiq XWAY Danube */\n+#include <asm/lantiq/config.h>\n+#include <asm/arch/config.h>\n+\n+/* Pull in default OpenWrt configs for Lantiq SoC */\n+#include \"openwrt-lantiq-common.h\"\n+\n+#define CONFIG_ENV_UPDATE_UBOOT_NOR\t\t\\\n+\t\"update-uboot-nor=run load-uboot-nor write-uboot-nor\\0\"\n+\n+#define CONFIG_EXTRA_ENV_SETTINGS\t\\\n+\tCONFIG_ENV_LANTIQ_DEFAULTS\t\\\n+\tCONFIG_ENV_UPDATE_UBOOT_NOR\t\\\n+\t\"kernel_addr=0xB0040000\\0\"\n+\n+#endif /* __CONFIG_H */\n"
  },
  {
    "path": "package/boot/uboot-lantiq/patches/0107-MIPS-add-board-support-for-ZyXEL-P-2812HNU-Fx.patch",
    "content": "From 3f7be04a148d23cdb5fd320e0e2923983f8bd1f4 Mon Sep 17 00:00:00 2001\nFrom: Luka Perkov <luka@openwrt.org>\nDate: Tue, 6 Aug 2013 22:51:00 +0200\nSubject: MIPS: add board support for ZyXEL P-2812HNU-Fx\n\nSigned-off-by: Luka Perkov <luka@openwrt.org>\n\n--- /dev/null\n+++ b/board/zyxel/p2812hnufx/Makefile\n@@ -0,0 +1,27 @@\n+#\n+# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de\n+#\n+# SPDX-License-Identifier:\tGPL-2.0+\n+#\n+\n+include $(TOPDIR)/config.mk\n+\n+LIB\t= $(obj)lib$(BOARD).o\n+\n+COBJS\t= $(BOARD).o\n+\n+SRCS\t:= $(SOBJS:.o=.S) $(COBJS:.o=.c)\n+OBJS\t:= $(addprefix $(obj),$(COBJS))\n+SOBJS\t:= $(addprefix $(obj),$(SOBJS))\n+\n+$(LIB):\t$(obj).depend $(OBJS) $(SOBJS)\n+\t$(call cmd_link_o_target, $(OBJS) $(SOBJS))\n+\n+#########################################################################\n+\n+# defines $(obj).depend target\n+include $(SRCTREE)/rules.mk\n+\n+sinclude $(obj).depend\n+\n+#########################################################################\n--- /dev/null\n+++ b/board/zyxel/p2812hnufx/config.mk\n@@ -0,0 +1,7 @@\n+#\n+# Copyright (C) 2012-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com\n+#\n+# SPDX-License-Identifier:\tGPL-2.0+\n+#\n+\n+PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR)\n--- /dev/null\n+++ b/board/zyxel/p2812hnufx/ddr_settings.h\n@@ -0,0 +1,70 @@\n+/*\n+ * Copyright (C) 2013 Luka Perkov <luka@openwrt.org>\n+ *\n+ * The values have been extracted from original ZyXEL U-Boot.\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#define\tMC_CCR00_VALUE\t0x101\n+#define\tMC_CCR01_VALUE\t0x1000100\n+#define\tMC_CCR02_VALUE\t0x1010000\n+#define\tMC_CCR03_VALUE\t0x101\n+#define\tMC_CCR04_VALUE\t0x1000000\n+#define\tMC_CCR05_VALUE\t0x1000101\n+#define\tMC_CCR06_VALUE\t0x1000100\n+#define\tMC_CCR07_VALUE\t0x1010000\n+#define\tMC_CCR08_VALUE\t0x1000101\n+#define\tMC_CCR09_VALUE\t0x0\n+#define\tMC_CCR10_VALUE\t0x2000100\n+#define\tMC_CCR11_VALUE\t0x2000300\n+#define\tMC_CCR12_VALUE\t0x30000\n+#define\tMC_CCR13_VALUE\t0x202\n+#define\tMC_CCR14_VALUE\t0x7080A0F\n+#define\tMC_CCR15_VALUE\t0x2040F\n+#define\tMC_CCR16_VALUE\t0x40000\n+#define\tMC_CCR17_VALUE\t0x70102\n+#define\tMC_CCR18_VALUE\t0x4020002\n+#define\tMC_CCR19_VALUE\t0x30302\n+#define\tMC_CCR20_VALUE\t0x8000700\n+#define\tMC_CCR21_VALUE\t0x40F020A\n+#define\tMC_CCR22_VALUE\t0x0\n+#define\tMC_CCR23_VALUE\t0xC020000\n+#define\tMC_CCR24_VALUE\t0x4401B04\n+#define\tMC_CCR25_VALUE\t0x0\n+#define\tMC_CCR26_VALUE\t0x0\n+#define\tMC_CCR27_VALUE\t0x6420000\n+#define\tMC_CCR28_VALUE\t0x0\n+#define\tMC_CCR29_VALUE\t0x0\n+#define\tMC_CCR30_VALUE\t0x798\n+#define\tMC_CCR31_VALUE\t0x0\n+#define\tMC_CCR32_VALUE\t0x0\n+#define\tMC_CCR33_VALUE\t0x650000\n+#define\tMC_CCR34_VALUE\t0x200C8\n+#define\tMC_CCR35_VALUE\t0x1D445D\n+#define\tMC_CCR36_VALUE\t0xC8\n+#define\tMC_CCR37_VALUE\t0xC351\n+#define\tMC_CCR38_VALUE\t0x0\n+#define\tMC_CCR39_VALUE\t0x141F04\n+#define\tMC_CCR40_VALUE\t0x142704\n+#define\tMC_CCR41_VALUE\t0x141B42\n+#define\tMC_CCR42_VALUE\t0x141B42\n+#define\tMC_CCR43_VALUE\t0x566504\n+#define\tMC_CCR44_VALUE\t0x566504\n+#define\tMC_CCR45_VALUE\t0x565F17\n+#define\tMC_CCR46_VALUE\t0x565F17\n+#define\tMC_CCR47_VALUE\t0x0\n+#define\tMC_CCR48_VALUE\t0x0\n+#define\tMC_CCR49_VALUE\t0x0\n+#define\tMC_CCR50_VALUE\t0x0\n+#define\tMC_CCR51_VALUE\t0x0\n+#define\tMC_CCR52_VALUE\t0x133\n+#define\tMC_CCR53_VALUE\t0xF3014B27\n+#define\tMC_CCR54_VALUE\t0xF3014B27\n+#define\tMC_CCR55_VALUE\t0xF3014B27\n+#define\tMC_CCR56_VALUE\t0xF3014B27\n+#define\tMC_CCR57_VALUE\t0x7800301\n+#define\tMC_CCR58_VALUE\t0x7800301\n+#define\tMC_CCR59_VALUE\t0x7800301\n+#define\tMC_CCR60_VALUE\t0x7800301\n+#define\tMC_CCR61_VALUE\t0x4\n--- /dev/null\n+++ b/board/zyxel/p2812hnufx/p2812hnufx.c\n@@ -0,0 +1,97 @@\n+/*\n+ * Copyright (C) 2013 Luka Perkov <luka@openwrt.org>\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#include <common.h>\n+#include <asm/gpio.h>\n+#include <asm/lantiq/eth.h>\n+#include <asm/lantiq/chipid.h>\n+#include <asm/lantiq/cpu.h>\n+#include <asm/arch/gphy.h>\n+\n+#if defined(CONFIG_SPL_BUILD)\n+#define do_gpio_init\t1\n+#define do_pll_init\t1\n+#define do_dcdc_init\t0\n+#elif defined(CONFIG_SYS_BOOT_RAM)\n+#define do_gpio_init\t1\n+#define do_pll_init\t0\n+#define do_dcdc_init\t1\n+#else\n+#define do_gpio_init\t0\n+#define do_pll_init\t0\n+#define do_dcdc_init\t1\n+#endif\n+\n+static void gpio_init(void)\n+{\n+\t/* EBU.FL_CS1 as output for NAND CE */\n+\tgpio_set_altfunc(23, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);\n+\t/* EBU.FL_A23 as output for NAND CLE */\n+\tgpio_set_altfunc(24, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);\n+\t/* EBU.FL_A24 as output for NAND ALE */\n+\tgpio_set_altfunc(13, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);\n+\t/* GPIO 3.0 as input for NAND Ready Busy */\n+\tgpio_set_altfunc(48, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_IN);\n+\t/* GPIO 3.1 as output for NAND Read */\n+\tgpio_set_altfunc(49, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);\n+}\n+\n+int board_early_init_f(void)\n+{\n+\tif (do_gpio_init)\n+\t\tgpio_init();\n+\n+\tif (do_pll_init)\n+\t\tltq_pll_init();\n+\n+\tif (do_dcdc_init)\n+\t\tltq_dcdc_init(0x7F);\n+\n+\treturn 0;\n+}\n+\n+int checkboard(void)\n+{\n+\tputs(\"Board: \" CONFIG_BOARD_NAME \"\\n\");\n+\tltq_chip_print_info();\n+\n+\treturn 0;\n+}\n+\n+static const struct ltq_eth_port_config eth_port_config[] = {\n+\t/* GMAC0: external Lantiq PEF7071 10/100/1000 PHY for LAN port 0 */\n+\t{ 0, 0x0, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_RGMII },\n+\t/* GMAC1: external Lantiq PEF7071 10/100/1000 PHY for LAN port 1 */\n+\t{ 1, 0x1, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_RGMII },\n+\t/* GMAC2: internal GPHY0 with 10/100/1000 firmware for LAN port 2 */\n+\t{ 2, 0x11, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_GMII },\n+\t/* GMAC3: unused */\n+\t{ 3, 0x0, LTQ_ETH_PORT_NONE, PHY_INTERFACE_MODE_NONE },\n+\t/* GMAC4: internal GPHY1 with 10/100/1000 firmware for LAN port 3 */\n+\t{ 4, 0x13, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_GMII },\n+\t/* GMAC5: external Lantiq PEF7071 10/100/1000 PHY for WANoE port */\n+\t{ 5, 0x5, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_RGMII },\n+};\n+\n+static const struct ltq_eth_board_config eth_board_config = {\n+\t.ports = eth_port_config,\n+\t.num_ports = ARRAY_SIZE(eth_port_config),\n+};\n+\n+int board_eth_init(bd_t * bis)\n+{\n+\tconst enum ltq_gphy_clk clk = LTQ_GPHY_CLK_25MHZ_PLL0;\n+\tconst ulong fw_addr = 0x80FF0000;\n+\n+\tltq_gphy_phy11g_a1x_load(fw_addr);\n+\n+\tltq_cgu_gphy_clk_src(clk);\n+\n+\tltq_rcu_gphy_boot(0, fw_addr);\n+\tltq_rcu_gphy_boot(1, fw_addr);\n+\n+\treturn ltq_eth_initialize(&eth_board_config);\n+}\n--- a/boards.cfg\n+++ b/boards.cfg\n@@ -527,6 +527,8 @@ Active  mips        mips32         vrx20\n Active  mips        mips32         vrx200      lantiq          easy80920           easy80920_norspl                     easy80920:SYS_BOOT_NORSPL                                                                                                         Daniel Schwierzeck <daniel.schwierzeck@gmail.com>\n Active  mips        mips32         vrx200      lantiq          easy80920           easy80920_ram                        easy80920:SYS_BOOT_RAM                                                                                                            Daniel Schwierzeck <daniel.schwierzeck@gmail.com>\n Active  mips        mips32         vrx200      lantiq          easy80920           easy80920_sfspl                      easy80920:SYS_BOOT_SFSPL                                                                                                          Daniel Schwierzeck <daniel.schwierzeck@gmail.com>\n+Active  mips        mips32         vrx200      zyxel           p2812hnufx          p2812hnufx_nandspl                   p2812hnufx:SYS_BOOT_NANDSPL                                                                                                       Luka Perkov <luka@openwrt.org>\n+Active  mips        mips32         vrx200      zyxel           p2812hnufx          p2812hnufx_ram                       p2812hnufx:SYS_BOOT_RAM                                                                                                           Luka Perkov <luka@openwrt.org>\n Active  mips        mips64         -           -               qemu-mips           qemu_mips64                          qemu-mips64:SYS_BIG_ENDIAN                                                                                                        -\n Active  mips        mips64         -           -               qemu-mips           qemu_mips64el                        qemu-mips64:SYS_LITTLE_ENDIAN                                                                                                     -\n Active  nds32       n1213          ag101       AndesTech       adp-ag101           adp-ag101                            -                                                                                                                                 Andes <uboot@andestech.com>\n--- /dev/null\n+++ b/include/configs/p2812hnufx.h\n@@ -0,0 +1,69 @@\n+/*\n+ * Copyright (C) 2013 Luka Perkov <luka@openwrt.org>\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#ifndef __CONFIG_H\n+#define __CONFIG_H\n+\n+#define CONFIG_MACH_TYPE\t\"P-2812HNU-Fx\"\n+#define CONFIG_IDENT_STRING\t\" \"CONFIG_MACH_TYPE\n+#define CONFIG_BOARD_NAME\t\"ZyXEL P-2812HNU-Fx\"\n+\n+/* Configure SoC */\n+#define CONFIG_LTQ_SUPPORT_UART\t\t\t/* Enable ASC and UART */\n+\n+#define CONFIG_LTQ_SUPPORT_ETHERNET\t\t/* Enable ethernet */\n+\n+#define CONFIG_LTQ_SUPPORT_NAND_FLASH\t\t/* Have a K9F1G08U0D NAND flash */\n+\n+#define CONFIG_LTQ_SUPPORT_SPL_NAND_FLASH\t/* Build NAND flash SPL */\n+#define CONFIG_LTQ_SPL_COMP_LZO\t\t\t/* Compress SPL with LZO */\n+#define CONFIG_LTQ_SPL_CONSOLE\t\t\t/* Enable SPL console */\n+\n+#define CONFIG_SYS_NAND_PAGE_COUNT\t64\n+#define CONFIG_SYS_NAND_PAGE_SIZE\t2048\n+#define CONFIG_SYS_NAND_OOBSIZE\t\t64\n+#define CONFIG_SYS_NAND_BLOCK_SIZE\t(128 * 1024)\n+#define CONFIG_SYS_NAND_BAD_BLOCK_POS\tNAND_LARGE_BADBLOCK_POS\n+#define CONFIG_SYS_NAND_U_BOOT_OFFS\t0x4000\n+\n+#define CONFIG_SYS_DRAM_PROBE\n+\n+#define CONFIG_SYS_BOOTM_LEN          0x1000000       /* 16 MB */\n+\n+/* Environment */\n+#if defined(CONFIG_SYS_BOOT_NANDSPL)\n+#define CONFIG_ENV_IS_IN_NAND\n+#define CONFIG_ENV_OVERWRITE\n+#define CONFIG_ENV_OFFSET\t\t(256 * 1024)\n+#define CONFIG_ENV_SECT_SIZE\t\t(128 * 1024)\n+#else\n+#define CONFIG_ENV_IS_NOWHERE\n+#endif\n+\n+#define CONFIG_ENV_SIZE\t\t\t(8 * 1024)\n+#define CONFIG_LOADADDR\t\t\tCONFIG_SYS_LOAD_ADDR\n+\n+/* Console */\n+#define CONFIG_LTQ_ADVANCED_CONSOLE\n+#define CONFIG_BAUDRATE\t\t\t115200\n+#define CONFIG_CONSOLE_ASC\t\t1\n+#define CONFIG_CONSOLE_DEV\t\t\"ttyLTQ1\"\n+\n+/* Pull in default board configs for Lantiq XWAY VRX200 */\n+#include <asm/lantiq/config.h>\n+#include <asm/arch/config.h>\n+\n+/* Pull in default OpenWrt configs for Lantiq SoC */\n+#include \"openwrt-lantiq-common.h\"\n+\n+#define CONFIG_ENV_UPDATE_UBOOT_NAND\t\t\t\t\t\\\n+\t\"update-uboot-nand=run load-uboot-nandspl-lzo write-uboot-nand\\0\"\n+\n+#define CONFIG_EXTRA_ENV_SETTINGS\t\\\n+\tCONFIG_ENV_LANTIQ_DEFAULTS\t\\\n+\tCONFIG_ENV_UPDATE_UBOOT_NAND\n+\n+#endif /* __CONFIG_H */\n"
  },
  {
    "path": "package/boot/uboot-lantiq/patches/0108-MIPS-add-board-support-for-Arcadyan-ARV752DPW.patch",
    "content": "From fbdbf2ddf2b34d675d53de679c179788b0604c1a Mon Sep 17 00:00:00 2001\nFrom: Oliver Muth <dr.o.muth@gmx.de>\nDate: Sat, 12 Oct 2013 16:49:53 +0200\nSubject: MIPS: add board support for Arcadyan ARV752DPW\n\nSigned-off-by: Oliver Muth <dr.o.muth@gmx.de>\nSigned-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>\n\n--- /dev/null\n+++ b/board/arcadyan/arv752dpw/Makefile\n@@ -0,0 +1,27 @@\n+#\n+# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de\n+#\n+# SPDX-License-Identifier:\tGPL-2.0+\n+#\n+\n+include $(TOPDIR)/config.mk\n+\n+LIB\t= $(obj)lib$(BOARD).o\n+\n+COBJS\t= $(BOARD).o\n+\n+SRCS\t:= $(SOBJS:.o=.S) $(COBJS:.o=.c)\n+OBJS\t:= $(addprefix $(obj),$(COBJS))\n+SOBJS\t:= $(addprefix $(obj),$(SOBJS))\n+\n+$(LIB):\t$(obj).depend $(OBJS) $(SOBJS)\n+\t$(call cmd_link_o_target, $(OBJS) $(SOBJS))\n+\n+#########################################################################\n+\n+# defines $(obj).depend target\n+include $(SRCTREE)/rules.mk\n+\n+sinclude $(obj).depend\n+\n+#########################################################################\n--- /dev/null\n+++ b/board/arcadyan/arv752dpw/arv752dpw.c\n@@ -0,0 +1,51 @@\n+/*\n+ * Copyright (C) 2012 Luka Perkov <luka@openwrt.org>\n+ * Copyright (C) 2013 Oliver Muth <dr.o.muth@gmx.de>\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#include <common.h>\n+#include <switch.h>\n+#include <asm/gpio.h>\n+#include <asm/lantiq/eth.h>\n+#include <asm/lantiq/reset.h>\n+#include <asm/lantiq/chipid.h>\n+\n+int board_early_init_f(void)\n+{\n+\treturn 0;\n+}\n+\n+int checkboard(void)\n+{\n+\tputs(\"Board: \" CONFIG_BOARD_NAME \"\\n\");\n+\tltq_chip_print_info();\n+\n+\treturn 0;\n+}\n+\n+static const struct ltq_eth_port_config eth_port_config[] = {\n+\t/* MAC0: Realtek rtl8306 switch */\n+\t{ 0, 0x0, LTQ_ETH_PORT_SWITCH, PHY_INTERFACE_MODE_RMII },\n+};\n+\n+static const struct ltq_eth_board_config eth_board_config = {\n+\t.ports = eth_port_config,\n+\t.num_ports = ARRAY_SIZE(eth_port_config),\n+};\n+\n+int board_eth_init(bd_t *bis)\n+{\n+\treturn ltq_eth_initialize(&eth_board_config);\n+}\n+static struct switch_device rtl8306_dev = {\n+\t.name = \"rtl8306\",\n+\t.cpu_port = 5,\n+\t.port_mask = 0xF,\n+};\n+\n+int board_switch_init(void)\n+{\n+\treturn switch_device_register(&rtl8306_dev);\n+}\n--- /dev/null\n+++ b/board/arcadyan/arv752dpw/config.mk\n@@ -0,0 +1,7 @@\n+#\n+# Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com\n+#\n+# SPDX-License-Identifier:\tGPL-2.0+\n+#\n+\n+PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR)\n--- /dev/null\n+++ b/board/arcadyan/arv752dpw/ddr_settings.h\n@@ -0,0 +1,55 @@\n+/*\n+ * Copyright (C) 2011-2013 Luka Perkov <luka@openwrt.org>\n+ *\n+ * This file has been generated with lantiq_ram_extract_magic.awk script.     \n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#define MC_DC00_VALUE\t0x1B1B\n+#define MC_DC01_VALUE\t0x0\n+#define MC_DC02_VALUE\t0x0\n+#define MC_DC03_VALUE\t0x0\n+#define MC_DC04_VALUE\t0x0\n+#define MC_DC05_VALUE\t0x200\n+#define MC_DC06_VALUE\t0x605\n+#define MC_DC07_VALUE\t0x303\n+#define MC_DC08_VALUE\t0x102\n+#define MC_DC09_VALUE\t0x70A\n+#define MC_DC10_VALUE\t0x203\n+#define MC_DC11_VALUE\t0xC02\n+#define MC_DC12_VALUE\t0x1C8\n+#define MC_DC13_VALUE\t0x1\n+#define MC_DC14_VALUE\t0x0\n+#define MC_DC15_VALUE\t0x134\n+#define MC_DC16_VALUE\t0xC800\n+#define MC_DC17_VALUE\t0xD\n+#define MC_DC18_VALUE\t0x301\n+#define MC_DC19_VALUE\t0x200\n+#define MC_DC20_VALUE\t0xA03\n+#define MC_DC21_VALUE\t0x1400\n+#define MC_DC22_VALUE\t0x1414\n+#define MC_DC23_VALUE\t0x0\n+#define MC_DC24_VALUE\t0x5B\n+#define MC_DC25_VALUE\t0x0\n+#define MC_DC26_VALUE\t0x0\n+#define MC_DC27_VALUE\t0x0\n+#define MC_DC28_VALUE\t0x510\n+#define MC_DC29_VALUE\t0x4E20\n+#define MC_DC30_VALUE\t0x8235\n+#define MC_DC31_VALUE\t0x0\n+#define MC_DC32_VALUE\t0x0\n+#define MC_DC33_VALUE\t0x0\n+#define MC_DC34_VALUE\t0x0\n+#define MC_DC35_VALUE\t0x0\n+#define MC_DC36_VALUE\t0x0\n+#define MC_DC37_VALUE\t0x0\n+#define MC_DC38_VALUE\t0x0\n+#define MC_DC39_VALUE\t0x0\n+#define MC_DC40_VALUE\t0x0\n+#define MC_DC41_VALUE\t0x0\n+#define MC_DC42_VALUE\t0x0\n+#define MC_DC43_VALUE\t0x0\n+#define MC_DC44_VALUE\t0x0\n+#define MC_DC45_VALUE\t0x500\n+#define MC_DC46_VALUE\t0x0\n--- a/boards.cfg\n+++ b/boards.cfg\n@@ -508,6 +508,9 @@ Active  mips        mips32         danub\n Active  mips        mips32         danube      arcadyan        arv7518pw           arv7518pw_brn                        arv7518pw:SYS_BOOT_BRN                                                                                                            Luka Perkov <luka@openwrt.org>\n Active  mips        mips32         danube      arcadyan        arv7518pw           arv7518pw_nor                        arv7518pw:SYS_BOOT_NOR                                                                                                            Luka Perkov <luka@openwrt.org>\n Active  mips        mips32         danube      arcadyan        arv7518pw           arv7518pw_ram                        arv7518pw:SYS_BOOT_RAM                                                                                                            Luka Perkov <luka@openwrt.org>\n+Active  mips        mips32         danube      arcadyan        arv752dpw           arv752dpw_brn                        arv752dpw:SYS_BOOT_BRN                                                                                                            -\n+Active  mips        mips32         danube      arcadyan        arv752dpw           arv752dpw_nor                        arv752dpw:SYS_BOOT_NOR                                                                                                            -\n+Active  mips        mips32         danube      arcadyan        arv752dpw           arv752dpw_ram                        arv752dpw:SYS_BOOT_RAM                                                                                                            -\n Active  mips        mips32         danube      audiocodes      acmp252             acmp252_nor                          acmp252:SYS_BOOT_NOR                                                                                                              Daniel Golle <daniel.golle@gmail.com>\n Active  mips        mips32         danube      audiocodes      acmp252             acmp252_ram                          acmp252:SYS_BOOT_RAM                                                                                                              Daniel Golle <daniel.golle@gmail.com>\n Active  mips        mips32         danube      gigaset         sx76x               gigasx76x_nor                        sx76x:SYS_BOOT_NOR                                                                                                                Luka Perkov <luka@openwrt.org>\n--- /dev/null\n+++ b/include/configs/arv752dpw.h\n@@ -0,0 +1,69 @@\n+/*\n+ * Copyright (C) 2012-2013 Luka Perkov <luka@openwrt.org>\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#ifndef __CONFIG_H\n+#define __CONFIG_H\n+\n+#define CONFIG_MACH_TYPE\t\"ARV752DPW\"\n+#define CONFIG_IDENT_STRING\t\" \"CONFIG_MACH_TYPE\n+#define CONFIG_BOARD_NAME\t\"Arcadyan ARV752DPW\"\n+\n+/* Configure SoC */\n+#define CONFIG_LTQ_SUPPORT_UART\t\t/* Enable ASC and UART */\n+\n+#define CONFIG_LTQ_SUPPORT_ETHERNET\t/* Enable ethernet */\n+\n+#define CONFIG_LTQ_SUPPORT_NOR_FLASH\t/* Have a parallel NOR flash */\n+\n+#define CONFIG_SYS_BOOTM_LEN\t\t0x1000000\t/* 16 MB */\n+\n+/* Switch devices */\n+#define CONFIG_SWITCH_MULTI\n+#define CONFIG_SWITCH_RTL8306\n+\n+/* Environment */\n+#if defined(CONFIG_SYS_BOOT_NOR)\n+#define CONFIG_ENV_IS_IN_FLASH\n+#define CONFIG_ENV_OVERWRITE\n+#define CONFIG_ENV_OFFSET\t\t(192 * 1024)\n+#define CONFIG_ENV_SECT_SIZE\t\t(64 * 1024)\n+#else\n+#define CONFIG_ENV_IS_NOWHERE\n+#endif\n+\n+#define CONFIG_ENV_SIZE\t\t\t(8 * 1024)\n+#define CONFIG_LOADADDR\t\t\tCONFIG_SYS_LOAD_ADDR\n+\n+/* Brnboot loadable image */\n+#if defined(CONFIG_SYS_BOOT_BRN)\n+#define CONFIG_SYS_TEXT_BASE\t\t0x80002000\n+#define CONFIG_SKIP_LOWLEVEL_INIT\n+#define CONFIG_SYS_DISABLE_CACHE\n+#define CONFIG_ENV_OVERWRITE 1\n+#endif\n+\n+/* Console */\n+#define CONFIG_LTQ_ADVANCED_CONSOLE\n+#define CONFIG_BAUDRATE\t\t\t115200\n+#define CONFIG_CONSOLE_ASC\t\t1\n+#define CONFIG_CONSOLE_DEV\t\t\"ttyLTQ1\"\n+\n+/* Pull in default board configs for Lantiq XWAY Danube */\n+#include <asm/lantiq/config.h>\n+#include <asm/arch/config.h>\n+\n+/* Pull in default OpenWrt configs for Lantiq SoC */\n+#include \"openwrt-lantiq-common.h\"\n+\n+#define CONFIG_ENV_UPDATE_UBOOT_NOR\t\t\\\n+\t\"update-uboot-nor=run load-uboot-nor write-uboot-nor\\0\"\n+\n+#define CONFIG_EXTRA_ENV_SETTINGS\t\\\n+\tCONFIG_ENV_LANTIQ_DEFAULTS\t\\\n+\tCONFIG_ENV_UPDATE_UBOOT_NOR\t\\\n+\t\"kernel_addr=0xB0040000\\0\"\n+\n+#endif /* __CONFIG_H */\n"
  },
  {
    "path": "package/boot/uboot-lantiq/patches/0109-MIPS-add-board-support-for-Arcadyan-ARV752DPW22.patch",
    "content": "From 09f411b4d10f10a62f147264121bb853b4649c3e Mon Sep 17 00:00:00 2001\nFrom: Oliver Muth <dr.o.muth@gmx.de>\nDate: Sat, 12 Oct 2013 16:49:53 +0200\nSubject: MIPS: add board support for Arcadyan ARV752DPW22\n\nSigned-off-by: Oliver Muth <dr.o.muth@gmx.de>\nSigned-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>\n\n--- /dev/null\n+++ b/board/arcadyan/arv752dpw22/Makefile\n@@ -0,0 +1,27 @@\n+#\n+# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de\n+#\n+# SPDX-License-Identifier:\tGPL-2.0+\n+#\n+\n+include $(TOPDIR)/config.mk\n+\n+LIB\t= $(obj)lib$(BOARD).o\n+\n+COBJS\t= $(BOARD).o\n+\n+SRCS\t:= $(SOBJS:.o=.S) $(COBJS:.o=.c)\n+OBJS\t:= $(addprefix $(obj),$(COBJS))\n+SOBJS\t:= $(addprefix $(obj),$(SOBJS))\n+\n+$(LIB):\t$(obj).depend $(OBJS) $(SOBJS)\n+\t$(call cmd_link_o_target, $(OBJS) $(SOBJS))\n+\n+#########################################################################\n+\n+# defines $(obj).depend target\n+include $(SRCTREE)/rules.mk\n+\n+sinclude $(obj).depend\n+\n+#########################################################################\n--- /dev/null\n+++ b/board/arcadyan/arv752dpw22/arv752dpw22.c\n@@ -0,0 +1,52 @@\n+/*\n+ * Copyright (C) 2012 Luka Perkov <luka@openwrt.org>\n+ * Copyright (C) 2013 Oliver Muth <dr.o.muth@gmx.de>\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#include <common.h>\n+#include <switch.h>\n+#include <asm/gpio.h>\n+#include <asm/lantiq/eth.h>\n+#include <asm/lantiq/reset.h>\n+#include <asm/lantiq/chipid.h>\n+\n+int board_early_init_f(void)\n+{\n+\treturn 0;\n+}\n+\n+int checkboard(void)\n+{\n+\tputs(\"Board: \" CONFIG_BOARD_NAME \"\\n\");\n+\tltq_chip_print_info();\n+\n+\treturn 0;\n+}\n+\n+static const struct ltq_eth_port_config eth_port_config[] = {\n+\t/* MAC0: Atheros ar8216 switch */\n+\t{ 0, 0x0, LTQ_ETH_PORT_SWITCH, PHY_INTERFACE_MODE_MII },\n+};\n+\n+static const struct ltq_eth_board_config eth_board_config = {\n+\t.ports = eth_port_config,\n+\t.num_ports = ARRAY_SIZE(eth_port_config),\n+};\n+\n+int board_eth_init(bd_t *bis)\n+{\n+\treturn ltq_eth_initialize(&eth_board_config);\n+}\n+\n+static struct switch_device ar8216_dev = {\n+\t.name = \"ar8216\",\n+\t.cpu_port = 0,\n+\t.port_mask = 0xF,\n+};\n+\n+int board_switch_init(void)\n+{\n+\treturn switch_device_register(&ar8216_dev);\n+}\n--- /dev/null\n+++ b/board/arcadyan/arv752dpw22/config.mk\n@@ -0,0 +1,7 @@\n+#\n+# Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com\n+#\n+# SPDX-License-Identifier:\tGPL-2.0+\n+#\n+\n+PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR)\n--- /dev/null\n+++ b/board/arcadyan/arv752dpw22/ddr_settings.h\n@@ -0,0 +1,55 @@\n+/*\n+ * Copyright (C) 2011-2013 Luka Perkov <luka@openwrt.org>\n+ *\n+ * This file has been generated with lantiq_ram_extract_magic.awk script.     \n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#define MC_DC00_VALUE\t0x1B1B\n+#define MC_DC01_VALUE\t0x0\n+#define MC_DC02_VALUE\t0x0\n+#define MC_DC03_VALUE\t0x0\n+#define MC_DC04_VALUE\t0x0\n+#define MC_DC05_VALUE\t0x200\n+#define MC_DC06_VALUE\t0x605\n+#define MC_DC07_VALUE\t0x303\n+#define MC_DC08_VALUE\t0x102\n+#define MC_DC09_VALUE\t0x70A\n+#define MC_DC10_VALUE\t0x203\n+#define MC_DC11_VALUE\t0xC02\n+#define MC_DC12_VALUE\t0x1C8\n+#define MC_DC13_VALUE\t0x1\n+#define MC_DC14_VALUE\t0x0\n+#define MC_DC15_VALUE\t0x134\n+#define MC_DC16_VALUE\t0xC800\n+#define MC_DC17_VALUE\t0xD\n+#define MC_DC18_VALUE\t0x301\n+#define MC_DC19_VALUE\t0x200\n+#define MC_DC20_VALUE\t0xA03\n+#define MC_DC21_VALUE\t0x1400\n+#define MC_DC22_VALUE\t0x1414\n+#define MC_DC23_VALUE\t0x0\n+#define MC_DC24_VALUE\t0x5B\n+#define MC_DC25_VALUE\t0x0\n+#define MC_DC26_VALUE\t0x0\n+#define MC_DC27_VALUE\t0x0\n+#define MC_DC28_VALUE\t0x510\n+#define MC_DC29_VALUE\t0x4E20\n+#define MC_DC30_VALUE\t0x8235\n+#define MC_DC31_VALUE\t0x0\n+#define MC_DC32_VALUE\t0x0\n+#define MC_DC33_VALUE\t0x0\n+#define MC_DC34_VALUE\t0x0\n+#define MC_DC35_VALUE\t0x0\n+#define MC_DC36_VALUE\t0x0\n+#define MC_DC37_VALUE\t0x0\n+#define MC_DC38_VALUE\t0x0\n+#define MC_DC39_VALUE\t0x0\n+#define MC_DC40_VALUE\t0x0\n+#define MC_DC41_VALUE\t0x0\n+#define MC_DC42_VALUE\t0x0\n+#define MC_DC43_VALUE\t0x0\n+#define MC_DC44_VALUE\t0x0\n+#define MC_DC45_VALUE\t0x500\n+#define MC_DC46_VALUE\t0x0\n--- a/boards.cfg\n+++ b/boards.cfg\n@@ -511,6 +511,9 @@ Active  mips        mips32         danub\n Active  mips        mips32         danube      arcadyan        arv752dpw           arv752dpw_brn                        arv752dpw:SYS_BOOT_BRN                                                                                                            -\n Active  mips        mips32         danube      arcadyan        arv752dpw           arv752dpw_nor                        arv752dpw:SYS_BOOT_NOR                                                                                                            -\n Active  mips        mips32         danube      arcadyan        arv752dpw           arv752dpw_ram                        arv752dpw:SYS_BOOT_RAM                                                                                                            -\n+Active  mips        mips32         danube      arcadyan        arv752dpw22         arv752dpw22_brn                      arv752dpw22:SYS_BOOT_BRN                                                                                                          -\n+Active  mips        mips32         danube      arcadyan        arv752dpw22         arv752dpw22_nor                      arv752dpw22:SYS_BOOT_NOR                                                                                                          -\n+Active  mips        mips32         danube      arcadyan        arv752dpw22         arv752dpw22_ram                      arv752dpw22:SYS_BOOT_RAM                                                                                                          -\n Active  mips        mips32         danube      audiocodes      acmp252             acmp252_nor                          acmp252:SYS_BOOT_NOR                                                                                                              Daniel Golle <daniel.golle@gmail.com>\n Active  mips        mips32         danube      audiocodes      acmp252             acmp252_ram                          acmp252:SYS_BOOT_RAM                                                                                                              Daniel Golle <daniel.golle@gmail.com>\n Active  mips        mips32         danube      gigaset         sx76x               gigasx76x_nor                        sx76x:SYS_BOOT_NOR                                                                                                                Luka Perkov <luka@openwrt.org>\n--- /dev/null\n+++ b/include/configs/arv752dpw22.h\n@@ -0,0 +1,70 @@\n+/*\n+ * Copyright (C) 2012-2013 Luka Perkov <luka@openwrt.org>\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#ifndef __CONFIG_H\n+#define __CONFIG_H\n+\n+#define CONFIG_MACH_TYPE\t\"ARV752DPW22\"\n+#define CONFIG_IDENT_STRING\t\" \"CONFIG_MACH_TYPE\n+#define CONFIG_BOARD_NAME\t\"Arcadyan ARV752DPW22\"\n+\n+/* Configure SoC */\n+#define CONFIG_LTQ_SUPPORT_UART\t\t/* Enable ASC and UART */\n+\n+#define CONFIG_LTQ_SUPPORT_ETHERNET\t/* Enable ethernet */\n+\n+#define CONFIG_LTQ_SUPPORT_NOR_FLASH\t/* Have a parallel NOR flash */\n+\n+#define CONFIG_SYS_BOOTM_LEN\t\t0x1000000\t/* 16 MB */\n+\n+/* Switch devices */\n+#define CONFIG_SWITCH_MULTI\n+#define CONFIG_SWITCH_AR8216\n+\n+/* Environment */\n+#if defined(CONFIG_SYS_BOOT_NOR)\n+#define CONFIG_ENV_IS_IN_FLASH\n+#define CONFIG_ENV_OVERWRITE\n+#define CONFIG_ENV_OFFSET\t\t(192 * 1024)\n+#define CONFIG_ENV_SECT_SIZE\t\t(64 * 1024)\n+#else\n+#define CONFIG_ENV_IS_NOWHERE\n+#endif\n+\n+#define CONFIG_ENV_SIZE\t\t\t(8 * 1024)\n+#define CONFIG_LOADADDR\t\t\tCONFIG_SYS_LOAD_ADDR\n+\n+/* Burnboot loadable image */\n+#if defined(CONFIG_SYS_BOOT_BRN)\n+#define CONFIG_SYS_TEXT_BASE\t\t0x80002000\n+#define CONFIG_SKIP_LOWLEVEL_INIT\n+#define CONFIG_SYS_DISABLE_CACHE\n+#define CONFIG_ENV_OVERWRITE 1\n+#endif\n+\n+\n+/* Console */\n+#define CONFIG_LTQ_ADVANCED_CONSOLE\n+#define CONFIG_BAUDRATE\t\t\t115200\n+#define CONFIG_CONSOLE_ASC\t\t1\n+#define CONFIG_CONSOLE_DEV\t\t\"ttyLTQ1\"\n+\n+/* Pull in default board configs for Lantiq XWAY Danube */\n+#include <asm/lantiq/config.h>\n+#include <asm/arch/config.h>\n+\n+/* Pull in default OpenWrt configs for Lantiq SoC */\n+#include \"openwrt-lantiq-common.h\"\n+\n+#define CONFIG_ENV_UPDATE_UBOOT_NOR\t\t\\\n+\t\"update-uboot-nor=run load-uboot-nor write-uboot-nor\\0\"\n+\n+#define CONFIG_EXTRA_ENV_SETTINGS\t\\\n+\tCONFIG_ENV_LANTIQ_DEFAULTS\t\\\n+\tCONFIG_ENV_UPDATE_UBOOT_NOR\t\\\n+\t\"kernel_addr=0xB0040000\\0\"\n+\n+#endif /* __CONFIG_H */\n"
  },
  {
    "path": "package/boot/uboot-lantiq/patches/0110-MIPS-add-board-support-for-Arcadyan-ARV7510PW.patch",
    "content": "From ba27086a5174130d138d645c2f4a49b08c3f2386 Mon Sep 17 00:00:00 2001\nFrom: Matti Laakso <malaakso@elisanet.fi>\nDate: Sat, 2 Mar 2013 23:34:00 +0100\nSubject: MIPS: add board support for Arcadyan ARV7510\n\nSigned-off-by: Matti Laakso <malaakso@elisanet.fi>\nSigned-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>\n\n--- /dev/null\n+++ b/board/arcadyan/arv7510pw/Makefile\n@@ -0,0 +1,27 @@\n+#\n+# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de\n+#\n+# SPDX-License-Identifier:\tGPL-2.0+\n+#\n+\n+include $(TOPDIR)/config.mk\n+\n+LIB\t= $(obj)lib$(BOARD).o\n+\n+COBJS\t= $(BOARD).o\n+\n+SRCS\t:= $(SOBJS:.o=.S) $(COBJS:.o=.c)\n+OBJS\t:= $(addprefix $(obj),$(COBJS))\n+SOBJS\t:= $(addprefix $(obj),$(SOBJS))\n+\n+$(LIB):\t$(obj).depend $(OBJS) $(SOBJS)\n+\t$(call cmd_link_o_target, $(OBJS) $(SOBJS))\n+\n+#########################################################################\n+\n+# defines $(obj).depend target\n+include $(SRCTREE)/rules.mk\n+\n+sinclude $(obj).depend\n+\n+#########################################################################\n--- /dev/null\n+++ b/board/arcadyan/arv7510pw/arv7510pw.c\n@@ -0,0 +1,72 @@\n+/*\n+ * Copyright (C) 2013 Matti Laakso <malaakso@elisanet.fi>\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#include <common.h>\n+#include <switch.h>\n+#include <asm/gpio.h>\n+#include <asm/lantiq/eth.h>\n+#include <asm/lantiq/reset.h>\n+#include <asm/lantiq/chipid.h>\n+#include <asm/lantiq/cpu.h>\n+\n+static void gpio_init(void)\n+{\n+\t/* Initialize SSIO GPIOs */\n+\tgpio_set_altfunc(4, 1, 0, 1);\n+\tgpio_set_altfunc(5, 1, 0, 1);\n+\tgpio_set_altfunc(6, 1, 0, 1);\n+\tltq_gpio_init();\n+\n+\t/* Power led on */\n+\tgpio_direction_output(76, 1);\n+}\n+\n+int board_early_init_f(void)\n+{\n+\tgpio_init();\n+\n+\treturn 0;\n+}\n+\n+int checkboard(void)\n+{\n+\tputs(\"Board: \" CONFIG_BOARD_NAME \"\\n\");\n+\tltq_chip_print_info();\n+\n+\treturn 0;\n+}\n+\n+static const struct ltq_eth_port_config eth_port_config[] = {\n+\t/* MAC0: ADM6996I */\n+\t{ 0, 0x0, LTQ_ETH_PORT_SWITCH, PHY_INTERFACE_MODE_RMII },\n+};\n+\n+static const struct ltq_eth_board_config eth_board_config = {\n+\t.ports = eth_port_config,\n+\t.num_ports = ARRAY_SIZE(eth_port_config),\n+};\n+\n+int board_eth_init(bd_t *bis)\n+{\n+\treturn ltq_eth_initialize(&eth_board_config);\n+}\n+\n+static struct switch_device adm6996i_dev = {\n+\t.name = \"adm6996i\",\n+\t.cpu_port = 5,\n+\t.port_mask = 0xF,\n+};\n+\n+int board_switch_init(void)\n+{\n+\t/* Deactivate HRST line to release reset of ADM6996I switch */\n+\tltq_reset_once(LTQ_RESET_HARD, 200000);\n+\n+\t/* ADM6996I needs some time to come out of reset */\n+\t__udelay(50000);\n+\n+\treturn switch_device_register(&adm6996i_dev);\n+}\n--- /dev/null\n+++ b/board/arcadyan/arv7510pw/config.mk\n@@ -0,0 +1,7 @@\n+#\n+# Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com\n+#\n+# SPDX-License-Identifier:\tGPL-2.0+\n+#\n+\n+PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR)\n--- /dev/null\n+++ b/board/arcadyan/arv7510pw/ddr_settings.h\n@@ -0,0 +1,53 @@\n+/*\n+ * Copyright (C) 2013 Matti Laakso <malaakso@elisanet.fi>\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#define MC_DC00_VALUE\t0x1B1B\n+#define MC_DC01_VALUE\t0x0\n+#define MC_DC02_VALUE\t0x0\n+#define MC_DC03_VALUE\t0x0\n+#define MC_DC04_VALUE\t0x0\n+#define MC_DC05_VALUE\t0x200\n+#define MC_DC06_VALUE\t0x605\n+#define MC_DC07_VALUE\t0x303\n+#define MC_DC08_VALUE\t0x102\n+#define MC_DC09_VALUE\t0x70A\n+#define MC_DC10_VALUE\t0x203\n+#define MC_DC11_VALUE\t0xC02\n+#define MC_DC12_VALUE\t0x1C8\n+#define MC_DC13_VALUE\t0x1\n+#define MC_DC14_VALUE\t0x0\n+#define MC_DC15_VALUE\t0x120\n+#define MC_DC16_VALUE\t0xC800\n+#define MC_DC17_VALUE\t0xD\n+#define MC_DC18_VALUE\t0x301\n+#define MC_DC19_VALUE\t0x200\n+#define MC_DC20_VALUE\t0xA04\n+#define MC_DC21_VALUE\t0x1700\n+#define MC_DC22_VALUE\t0x1717\n+#define MC_DC23_VALUE\t0x0\n+#define MC_DC24_VALUE\t0x52\n+#define MC_DC25_VALUE\t0x0\n+#define MC_DC26_VALUE\t0x0\n+#define MC_DC27_VALUE\t0x0\n+#define MC_DC28_VALUE\t0x510\n+#define MC_DC29_VALUE\t0x4E20\n+#define MC_DC30_VALUE\t0x8235\n+#define MC_DC31_VALUE\t0x0\n+#define MC_DC32_VALUE\t0x0\n+#define MC_DC33_VALUE\t0x0\n+#define MC_DC34_VALUE\t0x0\n+#define MC_DC35_VALUE\t0x0\n+#define MC_DC36_VALUE\t0x0\n+#define MC_DC37_VALUE\t0x0\n+#define MC_DC38_VALUE\t0x0\n+#define MC_DC39_VALUE\t0x0\n+#define MC_DC40_VALUE\t0x0\n+#define MC_DC41_VALUE\t0x0\n+#define MC_DC42_VALUE\t0x0\n+#define MC_DC43_VALUE\t0x0\n+#define MC_DC44_VALUE\t0x0\n+#define MC_DC45_VALUE\t0x500\n+#define MC_DC46_VALUE\t0x0\n--- a/boards.cfg\n+++ b/boards.cfg\n@@ -505,6 +505,9 @@ Active  mips        mips32         au1x0\n Active  mips        mips32         danube      arcadyan        arv4519pw           arv4519pw_brn                        arv4519pw:SYS_BOOT_BRN                                                                                                            Luka Perkov <luka@openwrt.org>\n Active  mips        mips32         danube      arcadyan        arv4519pw           arv4519pw_nor                        arv4519pw:SYS_BOOT_NOR                                                                                                            Luka Perkov <luka@openwrt.org>\n Active  mips        mips32         danube      arcadyan        arv4519pw           arv4519pw_ram                        arv4519pw:SYS_BOOT_RAM                                                                                                            Luka Perkov <luka@openwrt.org>\n+Active  mips        mips32         danube      arcadyan        arv7510pw           arv7510pw_brn                        arv7510pw:SYS_BOOT_BRN                                                                                                            Luka Perkov <luka@openwrt.org>\n+Active  mips        mips32         danube      arcadyan        arv7510pw           arv7510pw_nor                        arv7510pw:SYS_BOOT_NOR                                                                                                            Luka Perkov <luka@openwrt.org>\n+Active  mips        mips32         danube      arcadyan        arv7510pw           arv7510pw_ram                        arv7510pw:SYS_BOOT_RAM                                                                                                            Luka Perkov <luka@openwrt.org>\n Active  mips        mips32         danube      arcadyan        arv7518pw           arv7518pw_brn                        arv7518pw:SYS_BOOT_BRN                                                                                                            Luka Perkov <luka@openwrt.org>\n Active  mips        mips32         danube      arcadyan        arv7518pw           arv7518pw_nor                        arv7518pw:SYS_BOOT_NOR                                                                                                            Luka Perkov <luka@openwrt.org>\n Active  mips        mips32         danube      arcadyan        arv7518pw           arv7518pw_ram                        arv7518pw:SYS_BOOT_RAM                                                                                                            Luka Perkov <luka@openwrt.org>\n--- /dev/null\n+++ b/include/configs/arv7510pw.h\n@@ -0,0 +1,77 @@\n+/*\n+ * Copyright (C) 2013 Matti Laakso <malaakso@elisanet.fi>\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#ifndef __CONFIG_H\n+#define __CONFIG_H\n+\n+#define CONFIG_MACH_TYPE\t\"ARV7510PW\"\n+#define CONFIG_IDENT_STRING\t\" \"CONFIG_MACH_TYPE\n+#define CONFIG_BOARD_NAME\t\"Arcadyan ARV7510PW\"\n+\n+/* Configure SoC */\n+#define CONFIG_LTQ_SUPPORT_UART\t\t/* Enable ASC and UART */\n+#define CONFIG_LTQ_SUPPORT_ETHERNET\t/* Enable ethernet */\n+#define CONFIG_LTQ_SUPPORT_NOR_FLASH\t/* Have a parallel NOR flash */\n+\n+#define CONFIG_SYS_BOOTM_LEN\t\t0x1000000\t/* 16 MB */\n+\n+/* Switch devices */\n+#define CONFIG_SWITCH_MULTI\n+#define CONFIG_SWITCH_ADM6996I\n+\n+/* SSIO */\n+#define CONFIG_LTQ_SSIO_SHIFT_REGS\n+#define CONFIG_LTQ_SSIO_EDGE_FALLING\n+#define CONFIG_LTQ_SSIO_GPHY1_MODE\t0\n+#define CONFIG_LTQ_SSIO_GPHY2_MODE\t0\n+#define CONFIG_LTQ_SSIO_INIT_VALUE\t0\n+\n+/* Environment */\n+#if defined(CONFIG_SYS_BOOT_NOR)\n+#define CONFIG_ENV_IS_IN_FLASH\n+#define CONFIG_ENV_OVERWRITE\n+#define CONFIG_ENV_OFFSET\t\t(256 * 1024)\n+#define CONFIG_ENV_SECT_SIZE\t\t(128 * 1024)\n+#else\n+#define CONFIG_ENV_IS_NOWHERE\n+#endif\n+\n+#define CONFIG_ENV_SIZE\t\t\t(8 * 1024)\n+#define CONFIG_LOADADDR\t\t\tCONFIG_SYS_LOAD_ADDR\n+\n+/* Brnboot loadable image */\n+#if defined(CONFIG_SYS_BOOT_BRN)\n+#define CONFIG_SYS_TEXT_BASE\t\t0x80002000\n+#define CONFIG_SKIP_LOWLEVEL_INIT\n+#define CONFIG_SYS_DISABLE_CACHE\n+#define CONFIG_ENV_OVERWRITE 1\n+#endif\n+\n+/* Console */\n+#define CONFIG_LTQ_ADVANCED_CONSOLE\n+#define CONFIG_BAUDRATE\t\t\t115200\n+#define CONFIG_CONSOLE_ASC\t\t1\n+#define CONFIG_CONSOLE_DEV\t\t\"ttyLTQ1\"\n+\n+/* Pull in default board configs for Lantiq XWAY Danube */\n+#include <asm/lantiq/config.h>\n+#include <asm/arch/config.h>\n+\n+/* Buffered write broken in ARV7510PW */\n+#undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE\n+\n+/* Pull in default OpenWrt configs for Lantiq SoC */\n+#include \"openwrt-lantiq-common.h\"\n+\n+#define CONFIG_ENV_UPDATE_UBOOT_NOR\t\t\\\n+\t\"update-uboot-nor=run load-uboot-nor write-uboot-nor\\0\"\n+\n+#define CONFIG_EXTRA_ENV_SETTINGS\t\t\\\n+\tCONFIG_ENV_LANTIQ_DEFAULTS\t\t\\\n+\tCONFIG_ENV_UPDATE_UBOOT_NOR\t\t\\\n+\t\"kernel_addr=0xB0060000\\0\"\n+\n+#endif /* __CONFIG_H */\n"
  },
  {
    "path": "package/boot/uboot-lantiq/patches/0111-MIPS-add-board-support-for-Arcadyan-ARV7510PW22.patch",
    "content": "--- /dev/null\n+++ b/board/arcadyan/arv7510pw22/arv7510pw22.c\n@@ -0,0 +1,55 @@\n+/*\n+ * Copyright (C) 2014 Álvaro Fernández Rojas <noltari@gmail.com>\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#include <common.h>\n+#include <switch.h>\n+#include <asm/gpio.h>\n+#include <asm/lantiq/eth.h>\n+#include <asm/lantiq/reset.h>\n+#include <asm/lantiq/chipid.h>\n+\n+int board_early_init_f(void)\n+{\n+\t/* Switch on Power LED */\n+\tgpio_direction_output(2, 0);\n+\tgpio_set_value(2, 0);\n+\n+\treturn 0;\n+}\n+\n+int checkboard(void)\n+{\n+\tputs(\"Board: \" CONFIG_BOARD_NAME \"\\n\");\n+\tltq_chip_print_info();\n+\n+\treturn 0;\n+}\n+\n+static const struct ltq_eth_port_config eth_port_config[] = {\n+\t/* MAC0: Atheros ar8216 switch */\n+\t{ 0, 0x0, LTQ_ETH_PORT_SWITCH, PHY_INTERFACE_MODE_NONE },\n+};\n+\n+static const struct ltq_eth_board_config eth_board_config = {\n+\t.ports = eth_port_config,\n+\t.num_ports = ARRAY_SIZE(eth_port_config),\n+};\n+\n+int board_eth_init(bd_t *bis)\n+{\n+\treturn ltq_eth_initialize(&eth_board_config);\n+}\n+\n+static struct switch_device ar8216_dev = {\n+\t.name = \"ar8216\",\n+\t.cpu_port = 0,\n+\t.port_mask = 0xF,\n+};\n+\n+int board_switch_init(void)\n+{\n+\treturn switch_device_register(&ar8216_dev);\n+}\n--- /dev/null\n+++ b/board/arcadyan/arv7510pw22/config.mk\n@@ -0,0 +1,7 @@\n+#\n+# Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com\n+#\n+# SPDX-License-Identifier:\tGPL-2.0+\n+#\n+\n+PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR)\n--- /dev/null\n+++ b/board/arcadyan/arv7510pw22/ddr_settings.h\n@@ -0,0 +1,55 @@\n+/*\n+ * Copyright (C) 2014 Álvaro Fernández Rojas <noltari@gmail.com>\n+ *\n+ * This file has been generated with lantiq_ram_extract_magic.awk script.     \n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#define MC_DC00_VALUE\t0x1B1B\n+#define MC_DC01_VALUE\t0x0\n+#define MC_DC02_VALUE\t0x0\n+#define MC_DC03_VALUE\t0x0\n+#define MC_DC04_VALUE\t0x0\n+#define MC_DC05_VALUE\t0x200\n+#define MC_DC06_VALUE\t0x605\n+#define MC_DC07_VALUE\t0x303\n+#define MC_DC08_VALUE\t0x102\n+#define MC_DC09_VALUE\t0x70A\n+#define MC_DC10_VALUE\t0x203\n+#define MC_DC11_VALUE\t0xC02\n+#define MC_DC12_VALUE\t0x1C8\n+#define MC_DC13_VALUE\t0x1\n+#define MC_DC14_VALUE\t0x0\n+#define MC_DC15_VALUE\t0x134\n+#define MC_DC16_VALUE\t0xC800\n+#define MC_DC17_VALUE\t0xD\n+#define MC_DC18_VALUE\t0x301\n+#define MC_DC19_VALUE\t0x200\n+#define MC_DC20_VALUE\t0xA03\n+#define MC_DC21_VALUE\t0x1400\n+#define MC_DC22_VALUE\t0x1414\n+#define MC_DC23_VALUE\t0x0\n+#define MC_DC24_VALUE\t0x5B\n+#define MC_DC25_VALUE\t0x0\n+#define MC_DC26_VALUE\t0x0\n+#define MC_DC27_VALUE\t0x0\n+#define MC_DC28_VALUE\t0x510\n+#define MC_DC29_VALUE\t0x4E20\n+#define MC_DC30_VALUE\t0x8235\n+#define MC_DC31_VALUE\t0x0\n+#define MC_DC32_VALUE\t0x0\n+#define MC_DC33_VALUE\t0x0\n+#define MC_DC34_VALUE\t0x0\n+#define MC_DC35_VALUE\t0x0\n+#define MC_DC36_VALUE\t0x0\n+#define MC_DC37_VALUE\t0x0\n+#define MC_DC38_VALUE\t0x0\n+#define MC_DC39_VALUE\t0x0\n+#define MC_DC40_VALUE\t0x0\n+#define MC_DC41_VALUE\t0x0\n+#define MC_DC42_VALUE\t0x0\n+#define MC_DC43_VALUE\t0x0\n+#define MC_DC44_VALUE\t0x0\n+#define MC_DC45_VALUE\t0x500\n+#define MC_DC46_VALUE\t0x0\n--- /dev/null\n+++ b/board/arcadyan/arv7510pw22/Makefile\n@@ -0,0 +1,27 @@\n+#\n+# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de\n+#\n+# SPDX-License-Identifier:\tGPL-2.0+\n+#\n+\n+include $(TOPDIR)/config.mk\n+\n+LIB\t= $(obj)lib$(BOARD).o\n+\n+COBJS\t= $(BOARD).o\n+\n+SRCS\t:= $(SOBJS:.o=.S) $(COBJS:.o=.c)\n+OBJS\t:= $(addprefix $(obj),$(COBJS))\n+SOBJS\t:= $(addprefix $(obj),$(SOBJS))\n+\n+$(LIB):\t$(obj).depend $(OBJS) $(SOBJS)\n+\t$(call cmd_link_o_target, $(OBJS) $(SOBJS))\n+\n+#########################################################################\n+\n+# defines $(obj).depend target\n+include $(SRCTREE)/rules.mk\n+\n+sinclude $(obj).depend\n+\n+#########################################################################\n--- a/boards.cfg\n+++ b/boards.cfg\n@@ -508,6 +508,9 @@ Active  mips        mips32         danub\n Active  mips        mips32         danube      arcadyan        arv7510pw           arv7510pw_brn                        arv7510pw:SYS_BOOT_BRN                                                                                                            Luka Perkov <luka@openwrt.org>\n Active  mips        mips32         danube      arcadyan        arv7510pw           arv7510pw_nor                        arv7510pw:SYS_BOOT_NOR                                                                                                            Luka Perkov <luka@openwrt.org>\n Active  mips        mips32         danube      arcadyan        arv7510pw           arv7510pw_ram                        arv7510pw:SYS_BOOT_RAM                                                                                                            Luka Perkov <luka@openwrt.org>\n+Active  mips        mips32         danube      arcadyan        arv7510pw22         arv7510pw22_brn                        arv7510pw22:SYS_BOOT_BRN                                                                                                          Álvaro Fernández Rojas <noltari@gmail.com>\n+Active  mips        mips32         danube      arcadyan        arv7510pw22         arv7510pw22_nor                        arv7510pw22:SYS_BOOT_NOR                                                                                                          Álvaro Fernández Rojas <noltari@gmail.com>\n+Active  mips        mips32         danube      arcadyan        arv7510pw22         arv7510pw22_ram                        arv7510pw22:SYS_BOOT_RAM                                                                                                          Álvaro Fernández Rojas <noltari@gmail.com>\n Active  mips        mips32         danube      arcadyan        arv7518pw           arv7518pw_brn                        arv7518pw:SYS_BOOT_BRN                                                                                                            Luka Perkov <luka@openwrt.org>\n Active  mips        mips32         danube      arcadyan        arv7518pw           arv7518pw_nor                        arv7518pw:SYS_BOOT_NOR                                                                                                            Luka Perkov <luka@openwrt.org>\n Active  mips        mips32         danube      arcadyan        arv7518pw           arv7518pw_ram                        arv7518pw:SYS_BOOT_RAM                                                                                                            Luka Perkov <luka@openwrt.org>\n--- /dev/null\n+++ b/include/configs/arv7510pw22.h\n@@ -0,0 +1,69 @@\n+/*\n+ * Copyright (C) 2014 Álvaro Fernández Rojas <noltari@gmail.com>\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#ifndef __CONFIG_H\n+#define __CONFIG_H\n+\n+#define CONFIG_MACH_TYPE\t\"ARV7510PW22\"\n+#define CONFIG_IDENT_STRING\t\" \"CONFIG_MACH_TYPE\n+#define CONFIG_BOARD_NAME\t\"Arcadyan ARV7510PW22\"\n+\n+/* Configure SoC */\n+#define CONFIG_LTQ_SUPPORT_UART\t\t/* Enable ASC and UART */\n+\n+#define CONFIG_LTQ_SUPPORT_ETHERNET\t/* Enable ethernet */\n+\n+#define CONFIG_LTQ_SUPPORT_NOR_FLASH\t/* Have a parallel NOR flash */\n+\n+#define CONFIG_SYS_BOOTM_LEN\t\t0x1000000\t/* 16 MB */\n+\n+/* Switch devices */\n+#define CONFIG_SWITCH_MULTI\n+#define CONFIG_SWITCH_AR8216\n+\n+/* Environment */\n+#if defined(CONFIG_SYS_BOOT_NOR)\n+#define CONFIG_ENV_IS_IN_FLASH\n+#define CONFIG_ENV_OVERWRITE\n+#define CONFIG_ENV_OFFSET\t\t(256 * 1024)\n+#define CONFIG_ENV_SECT_SIZE\t\t(128 * 1024)\n+#else\n+#define CONFIG_ENV_IS_NOWHERE\n+#endif\n+\n+#define CONFIG_ENV_SIZE\t\t\t(8 * 1024)\n+#define CONFIG_LOADADDR\t\t\tCONFIG_SYS_LOAD_ADDR\n+\n+/* Burnboot loadable image */\n+#if defined(CONFIG_SYS_BOOT_BRN)\n+#define CONFIG_SYS_TEXT_BASE\t\t0x80002000\n+#define CONFIG_SKIP_LOWLEVEL_INIT\n+#define CONFIG_SYS_DISABLE_CACHE\n+#define CONFIG_ENV_OVERWRITE 1\n+#endif\n+\n+/* Console */\n+#define CONFIG_LTQ_ADVANCED_CONSOLE\n+#define CONFIG_BAUDRATE\t\t\t115200\n+#define CONFIG_CONSOLE_ASC\t\t1\n+#define CONFIG_CONSOLE_DEV\t\t\"ttyLTQ1\"\n+\n+/* Pull in default board configs for Lantiq XWAY Danube */\n+#include <asm/lantiq/config.h>\n+#include <asm/arch/config.h>\n+\n+/* Pull in default OpenWrt configs for Lantiq SoC */\n+#include \"openwrt-lantiq-common.h\"\n+\n+#define CONFIG_ENV_UPDATE_UBOOT_NOR\t\t\\\n+\t\"update-uboot-nor=run load-uboot-nor write-uboot-nor\\0\"\n+\n+#define CONFIG_EXTRA_ENV_SETTINGS\t\\\n+\tCONFIG_ENV_LANTIQ_DEFAULTS\t\\\n+\tCONFIG_ENV_UPDATE_UBOOT_NOR\t\\\n+\t\"kernel_addr=0xB0060000\\0\"\n+\n+#endif /* __CONFIG_H */\n"
  },
  {
    "path": "package/boot/uboot-lantiq/patches/0112-MIPS-add-board-support-for-Arcadyan-VGV7510KW22.patch",
    "content": "--- /dev/null\n+++ b/board/arcadyan/vgv7510kw22/Makefile\n@@ -0,0 +1,27 @@\n+#\n+# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de\n+#\n+# SPDX-License-Identifier:\tGPL-2.0+\n+#\n+\n+include $(TOPDIR)/config.mk\n+\n+LIB\t= $(obj)lib$(BOARD).o\n+\n+COBJS\t= $(BOARD).o\n+\n+SRCS\t:= $(SOBJS:.o=.S) $(COBJS:.o=.c)\n+OBJS\t:= $(addprefix $(obj),$(COBJS))\n+SOBJS\t:= $(addprefix $(obj),$(SOBJS))\n+\n+$(LIB):\t$(obj).depend $(OBJS) $(SOBJS)\n+\t$(call cmd_link_o_target, $(OBJS) $(SOBJS))\n+\n+#########################################################################\n+\n+# defines $(obj).depend target\n+include $(SRCTREE)/rules.mk\n+\n+sinclude $(obj).depend\n+\n+#########################################################################\n--- /dev/null\n+++ b/board/arcadyan/vgv7510kw22/vgv7510kw22.c\n@@ -0,0 +1,116 @@\n+/*\n+ * Copyright (C) 2015 Martin Blumenstingl <martin.blumenstingl@googlemail.com>\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#include <common.h>\n+#include <asm/gpio.h>\n+#include <asm/lantiq/eth.h>\n+#include <asm/lantiq/chipid.h>\n+#include <asm/lantiq/cpu.h>\n+#include <asm/arch/gphy.h>\n+\n+#if defined(CONFIG_SYS_BOOT_RAM)\n+#define do_gpio_init\t1\n+#define do_pll_init\t0\n+#define do_dcdc_init\t1\n+#elif defined(CONFIG_SYS_BOOT_NOR)\n+#define do_gpio_init\t1\n+#define do_pll_init\t1\n+#define do_dcdc_init\t1\n+#else\n+#define do_gpio_init\t0\n+#define do_pll_init\t0\n+#define do_dcdc_init\t1\n+#endif\n+\n+#define GPIO_POWER_GREEN\t14\n+#define GPIO_POWER_RED\t28\n+\n+static void gpio_init(void)\n+{\n+\t/* Turn on the green power LED */\n+\tgpio_direction_output(GPIO_POWER_GREEN, 0);\n+\n+\t/* Turn off the red power LED */\n+\tgpio_direction_output(GPIO_POWER_RED, 1);\n+}\n+\n+int board_early_init_f(void)\n+{\n+\tif (do_gpio_init)\n+\t\tgpio_init();\n+\n+\tif (do_pll_init)\n+\t\tltq_pll_init();\n+\n+\tif (do_dcdc_init)\n+\t\tltq_dcdc_init(0x7F);\n+\n+\treturn 0;\n+}\n+\n+int checkboard(void)\n+{\n+\tputs(\"Board: \" CONFIG_BOARD_NAME \"\\n\");\n+\tltq_chip_print_info();\n+\n+\treturn 0;\n+}\n+\n+void show_boot_progress(int arg)\n+{\n+\tif (!do_gpio_init)\n+\t\treturn 0;\n+\n+\tif (arg >= 0) {\n+\t\t/* Success - turn off the red power LED and turn on the green power LED */\n+\t\tgpio_set_value(GPIO_POWER_RED, 1);\n+\t\tgpio_set_value(GPIO_POWER_GREEN, 0);\n+\t} else {\n+\t\t/* Failure - turn off green power LED and turn on red power LED */\n+\t\tgpio_set_value(GPIO_POWER_GREEN, 1);\n+\t\tgpio_set_value(GPIO_POWER_RED, 0);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static const struct ltq_eth_port_config eth_port_config[] = {\n+\t/* unused */\n+\t{ 0, 0x0, LTQ_ETH_PORT_NONE, PHY_INTERFACE_MODE_NONE },\n+\t/* unused */\n+\t{ 1, 0x0, LTQ_ETH_PORT_NONE, PHY_INTERFACE_MODE_NONE },\n+\t/* Internal GPHY0 with 10/100 firmware for LAN port 2 */\n+\t{ 2, 0x11, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_MII },\n+\t/* Internal GPHY0 with 10/100 firmware for LAN port 1 */\n+\t{ 3, 0x12, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_MII },\n+\t/* Internal GPHY1 with 10/100 firmware for LAN port 4 */\n+\t{ 4, 0x13, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_MII },\n+\t/* Internal GPHY1 with 10/100 firmware for LAN port 3 */\n+\t{ 5, 0x14, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_MII },\n+};\n+\n+static const struct ltq_eth_board_config eth_board_config = {\n+\t.ports = eth_port_config,\n+\t.num_ports = ARRAY_SIZE(eth_port_config),\n+};\n+\n+int board_eth_init(bd_t * bis)\n+{\n+\tconst enum ltq_gphy_clk clk = LTQ_GPHY_CLK_25MHZ_PLL0;\n+\tconst ulong fw_addr = 0x80FF0000;\n+\n+\tif (ltq_chip_version_get() == 1)\n+\t\tltq_gphy_phy22f_a1x_load(fw_addr);\n+\telse\n+\t\tltq_gphy_phy22f_a2x_load(fw_addr);\n+\n+\tltq_cgu_gphy_clk_src(clk);\n+\n+\tltq_rcu_gphy_boot(0, fw_addr);\n+\tltq_rcu_gphy_boot(1, fw_addr);\n+\n+\treturn ltq_eth_initialize(&eth_board_config);\n+}\n--- /dev/null\n+++ b/board/arcadyan/vgv7510kw22/config.mk\n@@ -0,0 +1,7 @@\n+#\n+# Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com\n+#\n+# SPDX-License-Identifier:\tGPL-2.0+\n+#\n+\n+PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR)\n--- /dev/null\n+++ b/board/arcadyan/vgv7510kw22/ddr_settings.h\n@@ -0,0 +1,71 @@\n+/*\n+ * Copyright (C) 2015 Martin Blumenstingl <martin.blumenstingl@googlemail.com>\n+ * Copyright (C) 2016 Mathias Kresin <dev@kresin.me>\n+ *\n+ * The values have been extracted from original brnboot.\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#define\tMC_CCR00_VALUE\t0x101\n+#define\tMC_CCR01_VALUE\t0x1000100\n+#define\tMC_CCR02_VALUE\t0x1010000\n+#define\tMC_CCR03_VALUE\t0x100\n+#define\tMC_CCR04_VALUE\t0x1000000\n+#define\tMC_CCR05_VALUE\t0x1000101\n+#define\tMC_CCR06_VALUE\t0x1000100\n+#define\tMC_CCR07_VALUE\t0x1010000\n+#define\tMC_CCR08_VALUE\t0x1000101\n+#define\tMC_CCR09_VALUE\t0x0\n+#define\tMC_CCR10_VALUE\t0x2000100\n+#define\tMC_CCR11_VALUE\t0x2000401\n+#define\tMC_CCR12_VALUE\t0x30000\n+#define\tMC_CCR13_VALUE\t0x202\n+#define\tMC_CCR14_VALUE\t0x7080A0F\n+#define\tMC_CCR15_VALUE\t0x2040F\n+#define\tMC_CCR16_VALUE\t0x40000\n+#define\tMC_CCR17_VALUE\t0x70102\n+#define\tMC_CCR18_VALUE\t0x4020002\n+#define\tMC_CCR19_VALUE\t0x30302\n+#define\tMC_CCR20_VALUE\t0x8000700\n+#define\tMC_CCR21_VALUE\t0x40F020A\n+#define\tMC_CCR22_VALUE\t0x0\n+#define\tMC_CCR23_VALUE\t0xC020000\n+#define\tMC_CCR24_VALUE\t0x4401B04\n+#define\tMC_CCR25_VALUE\t0x0\n+#define\tMC_CCR26_VALUE\t0x0\n+#define\tMC_CCR27_VALUE\t0x6420000\n+#define\tMC_CCR28_VALUE\t0x0\n+#define\tMC_CCR29_VALUE\t0x0\n+#define\tMC_CCR30_VALUE\t0x798\n+#define\tMC_CCR31_VALUE\t0x2040F\n+#define\tMC_CCR32_VALUE\t0x0\n+#define\tMC_CCR33_VALUE\t0x650000\n+#define\tMC_CCR34_VALUE\t0x200C8\n+#define\tMC_CCR35_VALUE\t0x1D445D\n+#define\tMC_CCR36_VALUE\t0xC8\n+#define\tMC_CCR37_VALUE\t0xC351\n+#define\tMC_CCR38_VALUE\t0x0\n+#define\tMC_CCR39_VALUE\t0x141F04\n+#define\tMC_CCR40_VALUE\t0x142704\n+#define\tMC_CCR41_VALUE\t0x141B42\n+#define\tMC_CCR42_VALUE\t0x141B42\n+#define\tMC_CCR43_VALUE\t0x566504\n+#define\tMC_CCR44_VALUE\t0x566504\n+#define\tMC_CCR45_VALUE\t0x565F17\n+#define\tMC_CCR46_VALUE\t0x565F17\n+#define\tMC_CCR47_VALUE\t0x2040F\n+#define\tMC_CCR48_VALUE\t0x0\n+#define\tMC_CCR49_VALUE\t0x0\n+#define\tMC_CCR50_VALUE\t0x0\n+#define\tMC_CCR51_VALUE\t0x0\n+#define\tMC_CCR52_VALUE\t0x133\n+#define\tMC_CCR53_VALUE\t0xF3014B27\n+#define\tMC_CCR54_VALUE\t0xF3014B27\n+#define\tMC_CCR55_VALUE\t0xF3014B27\n+#define\tMC_CCR56_VALUE\t0xF3014B27\n+#define\tMC_CCR57_VALUE\t0x7800301\n+#define\tMC_CCR58_VALUE\t0x7800301\n+#define\tMC_CCR59_VALUE\t0x7800301\n+#define\tMC_CCR60_VALUE\t0x7800301\n+#define\tMC_CCR61_VALUE\t0x4\n--- a/boards.cfg\n+++ b/boards.cfg\n@@ -531,6 +531,9 @@ Active  mips        mips32         incai\n Active  mips        mips32         incaip      -               incaip              incaip_100MHz                        incaip:CPU_CLOCK_RATE=100000000                                                                                                   Wolfgang Denk <wd@denx.de>\n Active  mips        mips32         incaip      -               incaip              incaip_133MHz                        incaip:CPU_CLOCK_RATE=133000000                                                                                                   Wolfgang Denk <wd@denx.de>\n Active  mips        mips32         incaip      -               incaip              incaip_150MHz                        incaip:CPU_CLOCK_RATE=150000000                                                                                                   Wolfgang Denk <wd@denx.de>\n+Active  mips        mips32         vrx200      arcadyan        vgv7510kw22         vgv7510kw22_brn                      vgv7510kw22:SYS_BOOT_BRN                                                                                                           Martin Blumenstingl <martin.blumenstingl@googlemail.com>\n+Active  mips        mips32         vrx200      arcadyan        vgv7510kw22         vgv7510kw22_nor                      vgv7510kw22:SYS_BOOT_NOR                                                                                                           Martin Blumenstingl <martin.blumenstingl@googlemail.com>\n+Active  mips        mips32         vrx200      arcadyan        vgv7510kw22         vgv7510kw22_ram                      vgv7510kw22:SYS_BOOT_RAM                                                                                                           Martin Blumenstingl <martin.blumenstingl@googlemail.com>\n Active  mips        mips32         vrx200      avm             fb3370              fb3370_eva                           fb3370:SYS_BOOT_EVA                                                                                                               Daniel Schwierzeck <daniel.schwierzeck@gmail.com>\n Active  mips        mips32         vrx200      avm             fb3370              fb3370_ram                           fb3370:SYS_BOOT_RAM                                                                                                               Daniel Schwierzeck <daniel.schwierzeck@gmail.com>\n Active  mips        mips32         vrx200      avm             fb3370              fb3370_sfspl                         fb3370:SYS_BOOT_SFSPL                                                                                                             Daniel Schwierzeck <daniel.schwierzeck@gmail.com>\n--- /dev/null\n+++ b/include/configs/vgv7510kw22.h\n@@ -0,0 +1,59 @@\n+/*\n+ * Copyright (C) 2015 Martin Blumenstingl <martin.blumenstingl@googlemail.com>\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#ifndef __CONFIG_H\n+#define __CONFIG_H\n+\n+#define CONFIG_MACH_TYPE\t\"VGV7510KW22\"\n+#define CONFIG_IDENT_STRING\t\" \"CONFIG_MACH_TYPE\n+#define CONFIG_BOARD_NAME\t\"Arcadyan VGV7510KW22\"\n+\n+/* Configure SoC */\n+#define CONFIG_LTQ_SUPPORT_UART\t\t\t/* Enable ASC and UART */\n+\n+#define CONFIG_LTQ_SUPPORT_ETHERNET\t\t/* Enable ethernet */\n+\n+#define CONFIG_LTQ_SUPPORT_NOR_FLASH\t\t/* Have a parallel NOR flash */\n+\n+#define CONFIG_SYS_BOOTM_LEN\t\t0x1000000\t/* 16 MB */\n+\n+#if defined(CONFIG_SYS_BOOT_BRN)\n+#define CONFIG_SYS_TEXT_BASE\t\t0x80002000\n+#define CONFIG_SKIP_LOWLEVEL_INIT\n+#define CONFIG_SYS_DISABLE_CACHE\n+#define CONFIG_ENV_IS_NOWHERE\n+#define CONFIG_ENV_OVERWRITE\t\t1\n+#elif defined(CONFIG_SYS_BOOT_NOR)\n+#define CONFIG_ENV_IS_IN_FLASH\n+#define CONFIG_ENV_OVERWRITE\n+#define CONFIG_ENV_OFFSET\t\t(384 * 1024)\n+#define CONFIG_ENV_SECT_SIZE\t\t(128 * 1024)\n+#else\n+#define CONFIG_ENV_IS_NOWHERE\n+#endif\n+\n+#define CONFIG_ENV_SIZE\t\t\t(128 * 1024)\n+\n+#define CONFIG_LOADADDR\t\t\tCONFIG_SYS_LOAD_ADDR\n+\n+/* Console */\n+#define CONFIG_LTQ_ADVANCED_CONSOLE\n+#define CONFIG_BAUDRATE\t\t\t115200\n+#define CONFIG_CONSOLE_ASC\t\t1\n+#define CONFIG_CONSOLE_DEV\t\t\"ttyLTQ1\"\n+\n+/* Pull in default board configs for Lantiq XWAY VRX200 */\n+#include <asm/lantiq/config.h>\n+#include <asm/arch/config.h>\n+\n+/* Pull in default OpenWrt configs for Lantiq SoC */\n+#include \"openwrt-lantiq-common.h\"\n+\n+#define CONFIG_EXTRA_ENV_SETTINGS\t\\\n+\tCONFIG_ENV_LANTIQ_DEFAULTS\t\\\n+\t\"kernel_addr=0xB0080000\\0\"\n+\n+#endif /* __CONFIG_H */\n"
  },
  {
    "path": "package/boot/uboot-lantiq/patches/0113-MIPS-add-board-support-for-Arcadyan-ARV8539PW22.patch",
    "content": "--- /dev/null\n+++ b/board/arcadyan/arv8539pw22/Makefile\n@@ -0,0 +1,28 @@\n+#\n+# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de\n+#\n+# SPDX-License-Identifier:     GPL-2.0+\n+#\n+\n+include $(TOPDIR)/config.mk\n+\n+LIB    = $(obj)lib$(BOARD).o\n+\n+COBJS  = $(BOARD).o\n+\n+SRCS   := $(SOBJS:.o=.S) $(COBJS:.o=.c)\n+OBJS   := $(addprefix $(obj),$(COBJS))\n+SOBJS  := $(addprefix $(obj),$(SOBJS))\n+\n+$(LIB):        $(obj).depend $(OBJS) $(SOBJS)\n+\t$(call cmd_link_o_target, $(OBJS) $(SOBJS))\n+\n+#########################################################################\n+\n+# defines $(obj).depend target\n+include $(SRCTREE)/rules.mk\n+\n+sinclude $(obj).depend\n+\n+#########################################################################\n+\n--- /dev/null\n+++ b/board/arcadyan/arv8539pw22/arv8539pw22.c\n@@ -0,0 +1,53 @@\n+/*\n+ * Copyright (C) 2012 Luka Perkov <luka@openwrt.org>\n+ * Copyright (C) 2013 Oliver Muth <dr.o.muth@gmx.de>\n+ *\n+ * SPDX-License-Identifier:    GPL-2.0+\n+ */\n+\n+#include <common.h>\n+#include <switch.h>\n+#include <asm/gpio.h>\n+#include <asm/lantiq/eth.h>\n+#include <asm/lantiq/reset.h>\n+#include <asm/lantiq/chipid.h>\n+\n+int board_early_init_f(void)\n+{\n+       return 0;\n+}\n+\n+int checkboard(void)\n+{\n+       puts(\"Board: \" CONFIG_BOARD_NAME \"\\n\");\n+       ltq_chip_print_info();\n+\n+       return 0;\n+}\n+\n+static const struct ltq_eth_port_config eth_port_config[] = {\n+       /* MAC0: Atheros ar8216 switch */\n+       { 0, 0x0, LTQ_ETH_PORT_SWITCH, PHY_INTERFACE_MODE_MII },\n+};\n+\n+static const struct ltq_eth_board_config eth_board_config = {\n+       .ports = eth_port_config,\n+       .num_ports = ARRAY_SIZE(eth_port_config),\n+};\n+\n+int board_eth_init(bd_t *bis)\n+{\n+       return ltq_eth_initialize(&eth_board_config);\n+}\n+\n+static struct switch_device ar8216_dev = {\n+       .name = \"ar8216\",\n+       .cpu_port = 0,\n+       .port_mask = 0xF,\n+};\n+\n+int board_switch_init(void)\n+{\n+       return switch_device_register(&ar8216_dev);\n+}\n+\n--- /dev/null\n+++ b/board/arcadyan/arv8539pw22/config.mk\n@@ -0,0 +1,8 @@\n+#\n+# Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com\n+#\n+# SPDX-License-Identifier:     GPL-2.0+\n+#\n+\n+PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR)\n+\n--- /dev/null\n+++ b/board/arcadyan/arv8539pw22/ddr_settings.h\n@@ -0,0 +1,55 @@\n+/*\n+ * Copyright (C) 2011-2013 Luka Perkov <luka@openwrt.org>\n+ *\n+ * This file has been generated with lantiq_ram_extract_magic.awk script.     \n+ *\n+ * SPDX-License-Identifier:    GPL-2.0+\n+ */\n+\n+#define MC_DC00_VALUE  0x1B1B\n+#define MC_DC01_VALUE  0x0\n+#define MC_DC02_VALUE  0x0\n+#define MC_DC03_VALUE  0x0\n+#define MC_DC04_VALUE  0x0\n+#define MC_DC05_VALUE  0x200\n+#define MC_DC06_VALUE  0x605\n+#define MC_DC07_VALUE  0x303\n+#define MC_DC08_VALUE  0x102\n+#define MC_DC09_VALUE  0x70A\n+#define MC_DC10_VALUE  0x203\n+#define MC_DC11_VALUE  0xC02\n+#define MC_DC12_VALUE  0x1C8\n+#define MC_DC13_VALUE  0x1\n+#define MC_DC14_VALUE  0x0\n+#define MC_DC15_VALUE  0x134\n+#define MC_DC16_VALUE  0xC800\n+#define MC_DC17_VALUE  0xD\n+#define MC_DC18_VALUE  0x301\n+#define MC_DC19_VALUE  0x200\n+#define MC_DC20_VALUE  0xA03\n+#define MC_DC21_VALUE  0x1400\n+#define MC_DC22_VALUE  0x1414\n+#define MC_DC23_VALUE  0x0\n+#define MC_DC24_VALUE  0x5B\n+#define MC_DC25_VALUE  0x0\n+#define MC_DC26_VALUE  0x0\n+#define MC_DC27_VALUE  0x0\n+#define MC_DC28_VALUE  0x510\n+#define MC_DC29_VALUE  0x4E20\n+#define MC_DC30_VALUE  0x8235\n+#define MC_DC31_VALUE  0x0\n+#define MC_DC32_VALUE  0x0\n+#define MC_DC33_VALUE  0x0\n+#define MC_DC34_VALUE  0x0\n+#define MC_DC35_VALUE  0x0\n+#define MC_DC36_VALUE  0x0\n+#define MC_DC37_VALUE  0x0\n+#define MC_DC38_VALUE  0x0\n+#define MC_DC39_VALUE  0x0\n+#define MC_DC40_VALUE  0x0\n+#define MC_DC41_VALUE  0x0\n+#define MC_DC42_VALUE  0x0\n+#define MC_DC43_VALUE  0x0\n+#define MC_DC44_VALUE  0x0\n+#define MC_DC45_VALUE  0x500\n+#define MC_DC46_VALUE  0x0\n--- a/boards.cfg\n+++ b/boards.cfg\n@@ -520,6 +520,9 @@ Active  mips        mips32         danub\n Active  mips        mips32         danube      arcadyan        arv752dpw22         arv752dpw22_brn                      arv752dpw22:SYS_BOOT_BRN                                                                                                          -\n Active  mips        mips32         danube      arcadyan        arv752dpw22         arv752dpw22_nor                      arv752dpw22:SYS_BOOT_NOR                                                                                                          -\n Active  mips        mips32         danube      arcadyan        arv752dpw22         arv752dpw22_ram                      arv752dpw22:SYS_BOOT_RAM                                                                                                          -\n+Active  mips        mips32         danube      arcadyan        arv8539pw22         arv8539pw22_brn                      arv8539pw22:SYS_BOOT_BRN                                                                                                          -\n+Active  mips        mips32         danube      arcadyan        arv8539pw22         arv8539pw22_nor                      arv8539pw22:SYS_BOOT_NOR                                                                                                          -\n+Active  mips        mips32         danube      arcadyan        arv8539pw22         arv8539pw22_ram                      arv8539pw22:SYS_BOOT_RAM                                                                                                          -\n Active  mips        mips32         danube      audiocodes      acmp252             acmp252_nor                          acmp252:SYS_BOOT_NOR                                                                                                              Daniel Golle <daniel.golle@gmail.com>\n Active  mips        mips32         danube      audiocodes      acmp252             acmp252_ram                          acmp252:SYS_BOOT_RAM                                                                                                              Daniel Golle <daniel.golle@gmail.com>\n Active  mips        mips32         danube      gigaset         sx76x               gigasx76x_nor                        sx76x:SYS_BOOT_NOR                                                                                                                Luka Perkov <luka@openwrt.org>\n--- /dev/null\n+++ b/include/configs/arv8539pw22.h\n@@ -0,0 +1,70 @@\n+/*\n+ * Copyright (C) 2012-2013 Luka Perkov <luka@openwrt.org>\n+ *\n+ * SPDX-License-Identifier:    GPL-2.0+\n+ */\n+\n+#ifndef __CONFIG_H\n+#define __CONFIG_H\n+\n+#define CONFIG_MACH_TYPE       \"ARV8539PW22\"\n+#define CONFIG_IDENT_STRING    \" \"CONFIG_MACH_TYPE\n+#define CONFIG_BOARD_NAME      \"Speedport W 504V Typ A\"\n+\n+/* Configure SoC */\n+#define CONFIG_LTQ_SUPPORT_UART                /* Enable ASC and UART */\n+\n+#define CONFIG_LTQ_SUPPORT_ETHERNET    /* Enable ethernet */\n+\n+#define CONFIG_LTQ_SUPPORT_NOR_FLASH   /* Have a parallel NOR flash */\n+\n+#define CONFIG_SYS_BOOTM_LEN\t\t0x1000000\t/* 16 MB */\n+\n+/* Switch devices */\n+#define CONFIG_SWITCH_MULTI\n+#define CONFIG_SWITCH_AR8216\n+\n+/* Environment */\n+#if defined(CONFIG_SYS_BOOT_NOR)\n+#define CONFIG_ENV_IS_IN_FLASH\n+#define CONFIG_ENV_OVERWRITE\n+#define CONFIG_ENV_OFFSET              (192 * 1024)\n+#define CONFIG_ENV_SECT_SIZE           (64 * 1024)\n+#else\n+#define CONFIG_ENV_IS_NOWHERE\n+#endif\n+\n+#define CONFIG_ENV_SIZE                        (8 * 1024)\n+#define CONFIG_LOADADDR                        CONFIG_SYS_LOAD_ADDR\n+\n+/* Burnboot loadable image */\n+#if defined(CONFIG_SYS_BOOT_BRN)\n+#define CONFIG_SYS_TEXT_BASE           0x80002000\n+#define CONFIG_SKIP_LOWLEVEL_INIT\n+#define CONFIG_SYS_DISABLE_CACHE\n+#define CONFIG_ENV_OVERWRITE 1\n+#endif\n+\n+\n+/* Console */\n+#define CONFIG_LTQ_ADVANCED_CONSOLE\n+#define CONFIG_BAUDRATE                        115200\n+#define CONFIG_CONSOLE_ASC             1\n+#define CONFIG_CONSOLE_DEV             \"ttyS1\"\n+\n+/* Pull in default board configs for Lantiq XWAY Danube */\n+#include <asm/lantiq/config.h>\n+#include <asm/arch/config.h>\n+\n+/* Pull in default OpenWrt configs for Lantiq SoC */\n+#include \"openwrt-lantiq-common.h\"\n+\n+#define CONFIG_ENV_UPDATE_UBOOT_NOR            \\\n+       \"update-uboot-nor=run load-uboot-nor write-uboot-nor\\0\"\n+\n+#define CONFIG_EXTRA_ENV_SETTINGS      \\\n+       CONFIG_ENV_LANTIQ_DEFAULTS      \\\n+       CONFIG_ENV_UPDATE_UBOOT_NOR     \\\n+       \"kernel_addr=0xB0040000\\0\"\n+\n+#endif /* __CONFIG_H */\n"
  },
  {
    "path": "package/boot/uboot-lantiq/patches/0114-MIPS-add-board-support-for-Arcadyan-VGV7519.patch",
    "content": "--- /dev/null\n+++ b/board/arcadyan/vgv7519/Makefile\n@@ -0,0 +1,27 @@\n+#\n+# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de\n+#\n+# SPDX-License-Identifier:\tGPL-2.0+\n+#\n+\n+include $(TOPDIR)/config.mk\n+\n+LIB\t= $(obj)lib$(BOARD).o\n+\n+COBJS\t= $(BOARD).o\n+\n+SRCS\t:= $(SOBJS:.o=.S) $(COBJS:.o=.c)\n+OBJS\t:= $(addprefix $(obj),$(COBJS))\n+SOBJS\t:= $(addprefix $(obj),$(SOBJS))\n+\n+$(LIB):\t$(obj).depend $(OBJS) $(SOBJS)\n+\t$(call cmd_link_o_target, $(OBJS) $(SOBJS))\n+\n+#########################################################################\n+\n+# defines $(obj).depend target\n+include $(SRCTREE)/rules.mk\n+\n+sinclude $(obj).depend\n+\n+#########################################################################\n--- /dev/null\n+++ b/board/arcadyan/vgv7519/config.mk\n@@ -0,0 +1,7 @@\n+#\n+# Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com\n+#\n+# SPDX-License-Identifier:\tGPL-2.0+\n+#\n+\n+PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR)\n--- /dev/null\n+++ b/board/arcadyan/vgv7519/ddr_settings.h\n@@ -0,0 +1,70 @@\n+/*\n+ * Copyright (C) 2016 Mathias Kresin <dev@kresin.me>\n+ *\n+ * The values have been extracted from original brnboot.\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#define\tMC_CCR00_VALUE\t0x101\n+#define\tMC_CCR01_VALUE\t0x1000100\n+#define\tMC_CCR02_VALUE\t0x1010000\n+#define\tMC_CCR03_VALUE\t0x100\n+#define\tMC_CCR04_VALUE\t0x1000000\n+#define\tMC_CCR05_VALUE\t0x1000101\n+#define\tMC_CCR06_VALUE\t0x1000100\n+#define\tMC_CCR07_VALUE\t0x1010000\n+#define\tMC_CCR08_VALUE\t0x1000101\n+#define\tMC_CCR09_VALUE\t0x0\n+#define\tMC_CCR10_VALUE\t0x2000100\n+#define\tMC_CCR11_VALUE\t0x2000401\n+#define\tMC_CCR12_VALUE\t0x30000\n+#define\tMC_CCR13_VALUE\t0x202\n+#define\tMC_CCR14_VALUE\t0x7080A0F\n+#define\tMC_CCR15_VALUE\t0x2040F\n+#define\tMC_CCR16_VALUE\t0x40000\n+#define\tMC_CCR17_VALUE\t0x70102\n+#define\tMC_CCR18_VALUE\t0x4020002\n+#define\tMC_CCR19_VALUE\t0x30302\n+#define\tMC_CCR20_VALUE\t0x8000700\n+#define\tMC_CCR21_VALUE\t0x40F020A\n+#define\tMC_CCR22_VALUE\t0x0\n+#define\tMC_CCR23_VALUE\t0xC020000\n+#define\tMC_CCR24_VALUE\t0x4401B04\n+#define\tMC_CCR25_VALUE\t0x0\n+#define\tMC_CCR26_VALUE\t0x0\n+#define\tMC_CCR27_VALUE\t0x6420000\n+#define\tMC_CCR28_VALUE\t0x0\n+#define\tMC_CCR29_VALUE\t0x0\n+#define\tMC_CCR30_VALUE\t0x798\n+#define\tMC_CCR31_VALUE\t0x2040F\n+#define\tMC_CCR32_VALUE\t0x0\n+#define\tMC_CCR33_VALUE\t0x650000\n+#define\tMC_CCR34_VALUE\t0x200C8\n+#define\tMC_CCR35_VALUE\t0x1D445D\n+#define\tMC_CCR36_VALUE\t0xC8\n+#define\tMC_CCR37_VALUE\t0xC351\n+#define\tMC_CCR38_VALUE\t0x0\n+#define\tMC_CCR39_VALUE\t0x141F04\n+#define\tMC_CCR40_VALUE\t0x142704\n+#define\tMC_CCR41_VALUE\t0x141B42\n+#define\tMC_CCR42_VALUE\t0x141B42\n+#define\tMC_CCR43_VALUE\t0x566504\n+#define\tMC_CCR44_VALUE\t0x566504\n+#define\tMC_CCR45_VALUE\t0x565F17\n+#define\tMC_CCR46_VALUE\t0x565F17\n+#define\tMC_CCR47_VALUE\t0x2040F\n+#define\tMC_CCR48_VALUE\t0x0\n+#define\tMC_CCR49_VALUE\t0x0\n+#define\tMC_CCR50_VALUE\t0x0\n+#define\tMC_CCR51_VALUE\t0x0\n+#define\tMC_CCR52_VALUE\t0x133\n+#define\tMC_CCR53_VALUE\t0xF3014B27\n+#define\tMC_CCR54_VALUE\t0xF3014B27\n+#define\tMC_CCR55_VALUE\t0xF3014B27\n+#define\tMC_CCR56_VALUE\t0xF3014B27\n+#define\tMC_CCR57_VALUE\t0x7800301\n+#define\tMC_CCR58_VALUE\t0x7800301\n+#define\tMC_CCR59_VALUE\t0x7800301\n+#define\tMC_CCR60_VALUE\t0x7800301\n+#define\tMC_CCR61_VALUE\t0x4\n--- /dev/null\n+++ b/board/arcadyan/vgv7519/vgv7519.c\n@@ -0,0 +1,95 @@\n+/*\n+ * This file is released under the terms of GPL v2 and any later version.\n+ * See the file COPYING in the root directory of the source tree for details.\n+ *\n+ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com\n+ */\n+\n+#include <common.h>\n+#include <asm/gpio.h>\n+#include <asm/lantiq/eth.h>\n+#include <asm/lantiq/chipid.h>\n+#include <asm/lantiq/cpu.h>\n+#include <asm/arch/gphy.h>\n+\n+#if defined(CONFIG_SYS_BOOT_RAM)\n+#define do_gpio_init\t1\n+#define do_pll_init\t0\n+#define do_dcdc_init\t1\n+#elif defined(CONFIG_SYS_BOOT_NOR)\n+#define do_gpio_init\t1\n+#define do_pll_init\t1\n+#define do_dcdc_init\t1\n+#else\n+#define do_gpio_init\t0\n+#define do_pll_init\t0\n+#define do_dcdc_init\t1\n+#endif\n+\n+#define GPIO_GPHY_RESET\t47\n+\n+static void gpio_init(void)\n+{\n+\t/* Disable reset on external eth PHY */\n+\tgpio_direction_output(GPIO_GPHY_RESET, 1);\n+}\n+\n+int board_early_init_f(void)\n+{\n+\tif (do_gpio_init)\n+\t\tgpio_init();\n+\n+\tif (do_pll_init)\n+\t\tltq_pll_init();\n+\n+\tif (do_dcdc_init)\n+\t\tltq_dcdc_init(0x7F);\n+\n+\treturn 0;\n+}\n+\n+int checkboard(void)\n+{\n+\tputs(\"Board: \" CONFIG_BOARD_NAME \"\\n\");\n+\tltq_chip_print_info();\n+\n+\treturn 0;\n+}\n+\n+static const struct ltq_eth_port_config eth_port_config[] = {\n+\t/* GMAC0: external Lantiq PEF7071 10/100/1000 PHY for LAN port 0 */\n+\t{ 0, 0x0, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_RGMII },\n+\t/* GMAC1: external Lantiq PEF7071 10/100/1000 PHY for LAN port 1 */\n+\t{ 1, 0x1, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_RGMII },\n+\t/* GMAC2: internal GPHY0 with 10/100/1000 firmware for LAN port 2 */\n+\t{ 2, 0x11, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_GMII },\n+\t/* GMAC3: unused */\n+\t{ 3, 0x0, LTQ_ETH_PORT_NONE, PHY_INTERFACE_MODE_NONE },\n+\t/* GMAC4: internal GPHY1 with 10/100/1000 firmware for LAN port 3 */\n+\t{ 4, 0x13, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_GMII },\n+\t/* GMAC5: external Lantiq PEF7071 10/100/1000 PHY for WANoE port */\n+\t{ 5, 0x5, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_RGMII },\n+};\n+\n+static const struct ltq_eth_board_config eth_board_config = {\n+\t.ports = eth_port_config,\n+\t.num_ports = ARRAY_SIZE(eth_port_config),\n+};\n+\n+int board_eth_init(bd_t * bis)\n+{\n+\tconst enum ltq_gphy_clk clk = LTQ_GPHY_CLK_25MHZ_PLL0;\n+\tconst ulong fw_addr = 0x80FF0000;\n+\n+\tif (ltq_chip_version_get() == 1)\n+\t\tltq_gphy_phy22f_a1x_load(fw_addr);\n+\telse\n+\t\tltq_gphy_phy22f_a2x_load(fw_addr);\n+\n+\tltq_cgu_gphy_clk_src(clk);\n+\n+\tltq_rcu_gphy_boot(0, fw_addr);\n+\tltq_rcu_gphy_boot(1, fw_addr);\n+\n+\treturn ltq_eth_initialize(&eth_board_config);\n+}\n--- a/boards.cfg\n+++ b/boards.cfg\n@@ -537,6 +537,9 @@ Active  mips        mips32         incai\n Active  mips        mips32         vrx200      arcadyan        vgv7510kw22         vgv7510kw22_brn                      vgv7510kw22:SYS_BOOT_BRN                                                                                                           Martin Blumenstingl <martin.blumenstingl@googlemail.com>\n Active  mips        mips32         vrx200      arcadyan        vgv7510kw22         vgv7510kw22_nor                      vgv7510kw22:SYS_BOOT_NOR                                                                                                           Martin Blumenstingl <martin.blumenstingl@googlemail.com>\n Active  mips        mips32         vrx200      arcadyan        vgv7510kw22         vgv7510kw22_ram                      vgv7510kw22:SYS_BOOT_RAM                                                                                                           Martin Blumenstingl <martin.blumenstingl@googlemail.com>\n+Active  mips        mips32         vrx200      arcadyan        vgv7519             vgv7519_brn                          vgv7519:SYS_BOOT_BRN                                                                                                              Mathias Kresin <dev@kresin.me>\n+Active  mips        mips32         vrx200      arcadyan        vgv7519             vgv7519_nor                          vgv7519:SYS_BOOT_NOR                                                                                                              Eddi De Pieri <eddi@depieri.net>\n+Active  mips        mips32         vrx200      arcadyan        vgv7519             vgv7519_ram                          vgv7519:SYS_BOOT_RAM                                                                                                              Eddi De Pieri <eddi@depieri.net>\n Active  mips        mips32         vrx200      avm             fb3370              fb3370_eva                           fb3370:SYS_BOOT_EVA                                                                                                               Daniel Schwierzeck <daniel.schwierzeck@gmail.com>\n Active  mips        mips32         vrx200      avm             fb3370              fb3370_ram                           fb3370:SYS_BOOT_RAM                                                                                                               Daniel Schwierzeck <daniel.schwierzeck@gmail.com>\n Active  mips        mips32         vrx200      avm             fb3370              fb3370_sfspl                         fb3370:SYS_BOOT_SFSPL                                                                                                             Daniel Schwierzeck <daniel.schwierzeck@gmail.com>\n--- /dev/null\n+++ b/include/configs/vgv7519.h\n@@ -0,0 +1,64 @@\n+/*\n+ * This file is released under the terms of GPL v2 and any later version.\n+ * See the file COPYING in the root directory of the source tree for details.\n+ *\n+ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com\n+ */\n+\n+#ifndef __CONFIG_H\n+#define __CONFIG_H\n+\n+#define CONFIG_MACH_TYPE\t\"VGV7519\"\n+#define CONFIG_IDENT_STRING\t\" \"CONFIG_MACH_TYPE\n+#define CONFIG_BOARD_NAME\t\"Arcadyan VGV7519\"\n+\n+/* Configure SoC */\n+#define CONFIG_LTQ_SUPPORT_UART\t\t/* Enable ASC and UART */\n+\n+#define CONFIG_LTQ_SUPPORT_ETHERNET\t/* Enable ethernet */\n+\n+#define CONFIG_LTQ_SUPPORT_NOR_FLASH\t/* Have a parallel NOR flash */\n+\n+#define CONFIG_SYS_BOOTM_LEN\t\t0x1000000\t/* 16 MB */\n+\n+#define CONFIG_SYS_MAX_FLASH_BANKS\t2\t/* max number of memory banks */\n+#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH2_BASE }\n+\n+/* Environment */\n+#if defined(CONFIG_SYS_BOOT_BRN)\n+#define CONFIG_SYS_TEXT_BASE\t\t0x80002000\n+#define CONFIG_SKIP_LOWLEVEL_INIT\n+#define CONFIG_SYS_DISABLE_CACHE\n+#define CONFIG_ENV_IS_NOWHERE\n+#define CONFIG_ENV_OVERWRITE\t\t1\n+#elif defined(CONFIG_SYS_BOOT_NOR)\n+#define CONFIG_ENV_IS_IN_FLASH\n+#define CONFIG_ENV_OVERWRITE\n+#define CONFIG_ENV_OFFSET\t\t(384 * 1024)\n+#define CONFIG_ENV_SECT_SIZE\t\t(64 * 1024)\n+#else\n+#define CONFIG_ENV_IS_NOWHERE\n+#endif\n+\n+#define CONFIG_ENV_SIZE\t\t\t(8 * 1024)\n+\n+#define CONFIG_LOADADDR\t\t\tCONFIG_SYS_LOAD_ADDR\n+\n+/* Console */\n+#define CONFIG_LTQ_ADVANCED_CONSOLE\n+#define CONFIG_BAUDRATE\t\t\t115200\n+#define CONFIG_CONSOLE_ASC\t\t1\n+#define CONFIG_CONSOLE_DEV\t\t\"ttyLTQ1\"\n+\n+/* Pull in default board configs for Lantiq XWAY VRX200 */\n+#include <asm/lantiq/config.h>\n+#include <asm/arch/config.h>\n+\n+/* Pull in default OpenWrt configs for Lantiq SoC */\n+#include \"openwrt-lantiq-common.h\"\n+\n+#define CONFIG_EXTRA_ENV_SETTINGS\t\\\n+\tCONFIG_ENV_LANTIQ_DEFAULTS \\\n+\t\"kernel_addr=0xB0080000\\0\"\n+\n+#endif /* __CONFIG_H */\n"
  },
  {
    "path": "package/boot/uboot-lantiq/patches/0115-MIPS-add-board-support-for-Arcadyan-ARV7506PW11.patch",
    "content": "--- /dev/null\n+++ b/board/arcadyan/arv7506pw11/Makefile\n@@ -0,0 +1,27 @@\n+#\n+# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de\n+#\n+# SPDX-License-Identifier:\tGPL-2.0+\n+#\n+\n+include $(TOPDIR)/config.mk\n+\n+LIB\t= $(obj)lib$(BOARD).o\n+\n+COBJS\t= $(BOARD).o\n+\n+SRCS\t:= $(SOBJS:.o=.S) $(COBJS:.o=.c)\n+OBJS\t:= $(addprefix $(obj),$(COBJS))\n+SOBJS\t:= $(addprefix $(obj),$(SOBJS))\n+\n+$(LIB):\t$(obj).depend $(OBJS) $(SOBJS)\n+\t$(call cmd_link_o_target, $(OBJS) $(SOBJS))\n+\n+#########################################################################\n+\n+# defines $(obj).depend target\n+include $(SRCTREE)/rules.mk\n+\n+sinclude $(obj).depend\n+\n+#########################################################################\n--- /dev/null\n+++ b/board/arcadyan/arv7506pw11/arv7506pw11.c\n@@ -0,0 +1,97 @@\n+/*\n+ * Copyright (C) 2016 Mathias Kresin <dev@kresin.me>\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#include <common.h>\n+#include <switch.h>\n+#include <asm/gpio.h>\n+#include <asm/lantiq/eth.h>\n+#include <asm/lantiq/reset.h>\n+#include <asm/lantiq/chipid.h>\n+\n+#if defined(CONFIG_SYS_BOOT_RAM)\n+#define do_gpio_init\t1\n+#elif defined(CONFIG_SYS_BOOT_NOR)\n+#define do_gpio_init\t1\n+#else\n+#define do_gpio_init\t0\n+#endif\n+\n+#define GPIO_POWER_GREEN\t3\n+#define GPIO_POWER_RED\t6\n+#define GPIO_GPHY_RESET 19\n+\n+static void gpio_init(void)\n+{\n+\t/* Reset switch to have him in a clean state on reboot */\n+\tgpio_direction_output(GPIO_GPHY_RESET, 0);\n+\tudelay(20);\n+\tgpio_direction_output(GPIO_GPHY_RESET, 1);\n+\n+\t/* Turn on the green power LED */\n+\tgpio_direction_output(GPIO_POWER_GREEN, 0);\n+\n+\t/* Turn off the red power LED */\n+\tgpio_direction_output(GPIO_POWER_RED, 1);\n+}\n+\n+int board_early_init_f(void)\n+{\n+\tif (do_gpio_init)\n+\t\tgpio_init();\n+\n+\treturn 0;\n+}\n+\n+int checkboard(void)\n+{\n+\tputs(\"Board: \" CONFIG_BOARD_NAME \"\\n\");\n+\tltq_chip_print_info();\n+\n+\treturn 0;\n+}\n+\n+void show_boot_progress(int arg)\n+{\n+\tif (!do_gpio_init)\n+\t\treturn 0;\n+\n+\tif (arg >= 0) {\n+\t\t/* Success - turn off the red power LED and turn on the green power LED */\n+\t\tgpio_set_value(GPIO_POWER_RED, 1);\n+\t\tgpio_set_value(GPIO_POWER_GREEN, 0);\n+\t} else {\n+\t\t/* Failure - turn off green power LED and turn on red power LED */\n+\t\tgpio_set_value(GPIO_POWER_GREEN, 1);\n+\t\tgpio_set_value(GPIO_POWER_RED, 0);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static const struct ltq_eth_port_config eth_port_config[] = {\n+\t/* MAC0: Realtek rtl8306 switch */\n+\t{ 0, 0x0, LTQ_ETH_PORT_SWITCH, PHY_INTERFACE_MODE_RMII },\n+};\n+\n+static const struct ltq_eth_board_config eth_board_config = {\n+\t.ports = eth_port_config,\n+\t.num_ports = ARRAY_SIZE(eth_port_config),\n+};\n+\n+int board_eth_init(bd_t *bis)\n+{\n+\treturn ltq_eth_initialize(&eth_board_config);\n+}\n+static struct switch_device rtl8306_dev = {\n+\t.name = \"rtl8306\",\n+\t.cpu_port = 5,\n+\t.port_mask = 0xF,\n+};\n+\n+int board_switch_init(void)\n+{\n+\treturn switch_device_register(&rtl8306_dev);\n+}\n--- /dev/null\n+++ b/board/arcadyan/arv7506pw11/config.mk\n@@ -0,0 +1,7 @@\n+#\n+# Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com\n+#\n+# SPDX-License-Identifier:\tGPL-2.0+\n+#\n+\n+PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR)\n--- /dev/null\n+++ b/board/arcadyan/arv7506pw11/ddr_settings.h\n@@ -0,0 +1,55 @@\n+/*\n+ * Copyright (C) 2011-2013 Luka Perkov <luka@openwrt.org>\n+ *\n+ * This file has been generated with lantiq_ram_extract_magic.awk script. \n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#define MC_DC00_VALUE\t0x1B1B\n+#define MC_DC01_VALUE\t0x0\n+#define MC_DC02_VALUE\t0x0\n+#define MC_DC03_VALUE\t0x0\n+#define MC_DC04_VALUE\t0x0\n+#define MC_DC05_VALUE\t0x200\n+#define MC_DC06_VALUE\t0x605\n+#define MC_DC07_VALUE\t0x303\n+#define MC_DC08_VALUE\t0x102\n+#define MC_DC09_VALUE\t0x70A\n+#define MC_DC10_VALUE\t0x203\n+#define MC_DC11_VALUE\t0xC02\n+#define MC_DC12_VALUE\t0x1C8\n+#define MC_DC13_VALUE\t0x1\n+#define MC_DC14_VALUE\t0x0\n+#define MC_DC15_VALUE\t0x142\n+#define MC_DC16_VALUE\t0xC800\n+#define MC_DC17_VALUE\t0xD\n+#define MC_DC18_VALUE\t0x301\n+#define MC_DC19_VALUE\t0x200\n+#define MC_DC20_VALUE\t0xA03\n+#define MC_DC21_VALUE\t0x1300\n+#define MC_DC22_VALUE\t0x1313\n+#define MC_DC23_VALUE\t0x0\n+#define MC_DC24_VALUE\t0x68\n+#define MC_DC25_VALUE\t0x0\n+#define MC_DC26_VALUE\t0x0\n+#define MC_DC27_VALUE\t0x0\n+#define MC_DC28_VALUE\t0x510\n+#define MC_DC29_VALUE\t0x4E20\n+#define MC_DC30_VALUE\t0x8235\n+#define MC_DC31_VALUE\t0x0\n+#define MC_DC32_VALUE\t0x0\n+#define MC_DC33_VALUE\t0x0\n+#define MC_DC34_VALUE\t0x0\n+#define MC_DC35_VALUE\t0x0\n+#define MC_DC36_VALUE\t0x0\n+#define MC_DC37_VALUE\t0x0\n+#define MC_DC38_VALUE\t0x0\n+#define MC_DC39_VALUE\t0x0\n+#define MC_DC40_VALUE\t0x0\n+#define MC_DC41_VALUE\t0x0\n+#define MC_DC42_VALUE\t0x0\n+#define MC_DC43_VALUE\t0x0\n+#define MC_DC44_VALUE\t0x0\n+#define MC_DC45_VALUE\t0x500\n+#define MC_DC46_VALUE\t0x0\n--- a/boards.cfg\n+++ b/boards.cfg\n@@ -505,6 +505,9 @@ Active  mips        mips32         au1x0\n Active  mips        mips32         danube      arcadyan        arv4519pw           arv4519pw_brn                        arv4519pw:SYS_BOOT_BRN                                                                                                            Luka Perkov <luka@openwrt.org>\n Active  mips        mips32         danube      arcadyan        arv4519pw           arv4519pw_nor                        arv4519pw:SYS_BOOT_NOR                                                                                                            Luka Perkov <luka@openwrt.org>\n Active  mips        mips32         danube      arcadyan        arv4519pw           arv4519pw_ram                        arv4519pw:SYS_BOOT_RAM                                                                                                            Luka Perkov <luka@openwrt.org>\n+Active  mips        mips32         danube      arcadyan        arv7506pw11         arv7506pw11_brn                      arv7506pw11:SYS_BOOT_BRN                                                                                                          Mathias Kresin <dev@kresin.me>\n+Active  mips        mips32         danube      arcadyan        arv7506pw11         arv7506pw11_nor                      arv7506pw11:SYS_BOOT_NOR                                                                                                          Mathias Kresin <dev@kresin.me>\n+Active  mips        mips32         danube      arcadyan        arv7506pw11         arv7506pw11_ram                      arv7506pw11:SYS_BOOT_RAM                                                                                                          Mathias Kresin <dev@kresin.me>\n Active  mips        mips32         danube      arcadyan        arv7510pw           arv7510pw_brn                        arv7510pw:SYS_BOOT_BRN                                                                                                            Luka Perkov <luka@openwrt.org>\n Active  mips        mips32         danube      arcadyan        arv7510pw           arv7510pw_nor                        arv7510pw:SYS_BOOT_NOR                                                                                                            Luka Perkov <luka@openwrt.org>\n Active  mips        mips32         danube      arcadyan        arv7510pw           arv7510pw_ram                        arv7510pw:SYS_BOOT_RAM                                                                                                            Luka Perkov <luka@openwrt.org>\n--- /dev/null\n+++ b/include/configs/arv7506pw11.h\n@@ -0,0 +1,64 @@\n+/*\n+ * Copyright (C) 2016 Mathias Kresin <dev@kresin.me>\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#ifndef __CONFIG_H\n+#define __CONFIG_H\n+\n+#define CONFIG_MACH_TYPE\t\"ARV7506PW11\"\n+#define CONFIG_IDENT_STRING\t\" \"CONFIG_MACH_TYPE\n+#define CONFIG_BOARD_NAME\t\"Arcadyan ARV7506PW11\"\n+\n+/* Configure SoC */\n+#define CONFIG_LTQ_SUPPORT_UART\t\t/* Enable ASC and UART */\n+\n+#define CONFIG_LTQ_SUPPORT_ETHERNET\t/* Enable ethernet */\n+\n+#define CONFIG_LTQ_SUPPORT_NOR_FLASH\t/* Have a parallel NOR flash */\n+\n+#define CONFIG_SYS_BOOTM_LEN\t\t0x1000000\t/* 16 MB */\n+\n+/* Switch devices */\n+#define CONFIG_SWITCH_MULTI\n+#define CONFIG_SWITCH_RTL8306\n+\n+/* Environment */\n+#if defined(CONFIG_SYS_BOOT_BRN)\n+#define CONFIG_SYS_TEXT_BASE\t\t0x80002000\n+#define CONFIG_SKIP_LOWLEVEL_INIT\n+#define CONFIG_SYS_DISABLE_CACHE\n+#define CONFIG_ENV_IS_NOWHERE\n+#define CONFIG_ENV_OVERWRITE 1\n+#elif defined(CONFIG_SYS_BOOT_NOR)\n+#define CONFIG_ENV_IS_IN_FLASH\n+#define CONFIG_ENV_OVERWRITE\n+#define CONFIG_ENV_OFFSET\t\t(256 * 1024)\n+#define CONFIG_ENV_SECT_SIZE\t\t(64 * 1024)\n+#else\n+#define CONFIG_ENV_IS_NOWHERE\n+#endif\n+\n+#define CONFIG_ENV_SIZE\t\t\t(64 * 1024)\n+\n+#define CONFIG_LOADADDR\t\t\tCONFIG_SYS_LOAD_ADDR\n+\n+/* Console */\n+#define CONFIG_LTQ_ADVANCED_CONSOLE\n+#define CONFIG_BAUDRATE\t\t\t115200\n+#define CONFIG_CONSOLE_ASC\t\t1\n+#define CONFIG_CONSOLE_DEV\t\t\"ttyLTQ1\"\n+\n+/* Pull in default board configs for Lantiq XWAY Danube */\n+#include <asm/lantiq/config.h>\n+#include <asm/arch/config.h>\n+\n+/* Pull in default OpenWrt configs for Lantiq SoC */\n+#include \"openwrt-lantiq-common.h\"\n+\n+#define CONFIG_EXTRA_ENV_SETTINGS\t\\\n+\tCONFIG_ENV_LANTIQ_DEFAULTS\t\\\n+\t\"kernel_addr=0xB0050000\\0\"\n+\n+#endif /* __CONFIG_H */\n"
  },
  {
    "path": "package/boot/uboot-lantiq/patches/0116-MIPS-add-board-support-for-BT-Home-Hub-5A.patch",
    "content": "--- /dev/null\n+++ b/board/bt/bthomehubv5a/Makefile\n@@ -0,0 +1,27 @@\n+#\n+# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de\n+#\n+# SPDX-License-Identifier:\tGPL-2.0+\n+#\n+\n+include $(TOPDIR)/config.mk\n+\n+LIB\t= $(obj)lib$(BOARD).o\n+\n+COBJS\t= $(BOARD).o\n+\n+SRCS\t:= $(SOBJS:.o=.S) $(COBJS:.o=.c)\n+OBJS\t:= $(addprefix $(obj),$(COBJS))\n+SOBJS\t:= $(addprefix $(obj),$(SOBJS))\n+\n+$(LIB):\t$(obj).depend $(OBJS) $(SOBJS)\n+\t$(call cmd_link_o_target, $(OBJS) $(SOBJS))\n+\n+#########################################################################\n+\n+# defines $(obj).depend target\n+include $(SRCTREE)/rules.mk\n+\n+sinclude $(obj).depend\n+\n+#########################################################################\n--- /dev/null\n+++ b/board/bt/bthomehubv5a/bthomehubv5a.c\n@@ -0,0 +1,125 @@\n+/*\n+ * Copyright (C) 2015 Martin Blumenstingl <martin.blumenstingl@googlemail.com>\n+ * Based on p2812hnufx.c: (C) 2013 Luka Perkov <luka@openwrt.org>\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#include <common.h>\n+#include <asm/gpio.h>\n+#include <asm/lantiq/eth.h>\n+#include <asm/lantiq/chipid.h>\n+#include <asm/lantiq/cpu.h>\n+#include <asm/arch/gphy.h>\n+\n+#if defined(CONFIG_SPL_BUILD)\n+#define do_gpio_init\t1\n+#define do_pll_init\t1\n+#define do_dcdc_init\t0\n+#elif defined(CONFIG_SYS_BOOT_RAM)\n+#define do_gpio_init\t1\n+#define do_pll_init\t0\n+#define do_dcdc_init\t1\n+#else\n+#define do_gpio_init\t0\n+#define do_pll_init\t0\n+#define do_dcdc_init\t1\n+#endif\n+\n+#define GPIO_POWER_GREEN\t14\n+#define GPIO_POWER_RED\t12\n+\n+static void gpio_init(void)\n+{\n+\t/* EBU.FL_CS1 as output for NAND CE */\n+\tgpio_set_altfunc(23, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);\n+\t/* EBU.FL_A23 as output for NAND CLE */\n+\tgpio_set_altfunc(24, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);\n+\t/* EBU.FL_A24 as output for NAND ALE */\n+\tgpio_set_altfunc(13, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);\n+\t/* GPIO 3.0 as input for NAND Ready Busy */\n+\tgpio_set_altfunc(48, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_IN);\n+\t/* GPIO 3.1 as output for NAND Read */\n+\tgpio_set_altfunc(49, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);\n+\n+\t/* Turn on the green power LED */\n+\tgpio_direction_output(GPIO_POWER_GREEN, 0);\n+\n+\t/* Turn off the red power LED */\n+\tgpio_direction_output(GPIO_POWER_RED, 1);\n+}\n+\n+int board_early_init_f(void)\n+{\n+\tif (do_gpio_init)\n+\t\tgpio_init();\n+\n+\tif (do_pll_init)\n+\t\tltq_pll_init();\n+\n+\tif (do_dcdc_init)\n+\t\tltq_dcdc_init(0x7F);\n+\n+\treturn 0;\n+}\n+\n+int checkboard(void)\n+{\n+\tputs(\"Board: \" CONFIG_BOARD_NAME \"\\n\");\n+\tltq_chip_print_info();\n+\n+\treturn 0;\n+}\n+\n+void show_boot_progress(int arg)\n+{\n+\tif (!do_gpio_init)\n+\t\treturn 0;\n+\n+\tif (arg >= 0) {\n+\t\t/* Success - turn off the red power LED and turn on the green power LED */\n+\t\tgpio_set_value(GPIO_POWER_RED, 1);\n+\t\tgpio_set_value(GPIO_POWER_GREEN, 0);\n+\t} else {\n+\t\t/* Failure - turn off green power LED and turn on red power LED */\n+\t\tgpio_set_value(GPIO_POWER_GREEN, 1);\n+\t\tgpio_set_value(GPIO_POWER_RED, 0);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static const struct ltq_eth_port_config eth_port_config[] = {\n+\t/* GMAC0: external Lantiq PEF7071 10/100/1000 PHY for LAN port 3 */\n+\t{ 0, 0x0, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_RGMII },\n+\t/* GMAC1: external Lantiq PEF7071 10/100/1000 PHY for LAN port 4 */\n+\t{ 1, 0x1, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_RGMII },\n+\t/* GMAC2: internal GPHY0 with 10/100/1000 firmware for LAN port 2 */\n+\t{ 2, 0x11, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_GMII },\n+\t/* GMAC3: unused */\n+\t{ 3, 0x0, LTQ_ETH_PORT_NONE, PHY_INTERFACE_MODE_NONE },\n+\t/* GMAC4: internal GPHY1 with 10/100/1000 firmware for LAN port 1 */\n+\t{ 4, 0x13, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_GMII },\n+\t/* GMAC5: external Lantiq PEF7071 10/100/1000 PHY for WANoE port */\n+\t{ 5, 0x5, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_RGMII },\n+};\n+\n+static const struct ltq_eth_board_config eth_board_config = {\n+\t.ports = eth_port_config,\n+\t.num_ports = ARRAY_SIZE(eth_port_config),\n+};\n+\n+int board_eth_init(bd_t * bis)\n+{\n+\tconst enum ltq_gphy_clk clk = LTQ_GPHY_CLK_25MHZ_PLL0;\n+\tconst ulong fw_addr = 0x80FE0000;\n+\n+\tltq_gphy_phy11g_a2x_load(fw_addr);\n+\n+\tltq_cgu_gphy_clk_src(clk);\n+\n+\tltq_rcu_gphy_boot(0, fw_addr);\n+\tltq_rcu_gphy_boot(1, fw_addr);\n+\n+\treturn ltq_eth_initialize(&eth_board_config);\n+}\n--- /dev/null\n+++ b/board/bt/bthomehubv5a/config.mk\n@@ -0,0 +1,7 @@\n+#\n+# Copyright (C) 2012-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com\n+#\n+# SPDX-License-Identifier:\tGPL-2.0+\n+#\n+\n+PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR)\n--- /dev/null\n+++ b/board/bt/bthomehubv5a/ddr_settings.h\n@@ -0,0 +1,70 @@\n+/*\n+ * Copyright (C) 2015 Martin Blumenstingl <martin.blumenstingl@googlemail.com>\n+ *\n+ * The values have been taken from the HH5A GPL source.\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#define\tMC_CCR00_VALUE\t0x101\n+#define\tMC_CCR01_VALUE\t0x1000101\n+#define\tMC_CCR02_VALUE\t0x1010000\n+#define\tMC_CCR03_VALUE\t0x101\n+#define\tMC_CCR04_VALUE\t0x1000000\n+#define\tMC_CCR05_VALUE\t0x1000101\n+#define\tMC_CCR06_VALUE\t0x1000100\n+#define\tMC_CCR07_VALUE\t0x1010000\n+#define\tMC_CCR08_VALUE\t0x1000101\n+#define\tMC_CCR09_VALUE\t0x0\n+#define\tMC_CCR10_VALUE\t0x2000100\n+#define\tMC_CCR11_VALUE\t0x2000401\n+#define\tMC_CCR12_VALUE\t0x30000\n+#define\tMC_CCR13_VALUE\t0x202\n+#define\tMC_CCR14_VALUE\t0x7080A0F\n+#define\tMC_CCR15_VALUE\t0x2040F\n+#define\tMC_CCR16_VALUE\t0x40000\n+#define\tMC_CCR17_VALUE\t0x70102\n+#define\tMC_CCR18_VALUE\t0x4020002\n+#define\tMC_CCR19_VALUE\t0x30302\n+#define\tMC_CCR20_VALUE\t0x8000700\n+#define\tMC_CCR21_VALUE\t0x40F020A\n+#define\tMC_CCR22_VALUE\t0x0\n+#define\tMC_CCR23_VALUE\t0xC020000\n+#define\tMC_CCR24_VALUE\t0x4401B04\n+#define\tMC_CCR25_VALUE\t0x0\n+#define\tMC_CCR26_VALUE\t0x0\n+#define\tMC_CCR27_VALUE\t0x6420000\n+#define\tMC_CCR28_VALUE\t0x0\n+#define\tMC_CCR29_VALUE\t0x0\n+#define\tMC_CCR30_VALUE\t0x798\n+#define\tMC_CCR31_VALUE\t0x0\n+#define\tMC_CCR32_VALUE\t0x0\n+#define\tMC_CCR33_VALUE\t0x650000\n+#define\tMC_CCR34_VALUE\t0x200C8\n+#define\tMC_CCR35_VALUE\t0x1D445D\n+#define\tMC_CCR36_VALUE\t0xC8\n+#define\tMC_CCR37_VALUE\t0xC351\n+#define\tMC_CCR38_VALUE\t0x0\n+#define\tMC_CCR39_VALUE\t0x141F04\n+#define\tMC_CCR40_VALUE\t0x142704\n+#define\tMC_CCR41_VALUE\t0x141b42\n+#define\tMC_CCR42_VALUE\t0x141b42\n+#define\tMC_CCR43_VALUE\t0x566504\n+#define\tMC_CCR44_VALUE\t0x566504\n+#define\tMC_CCR45_VALUE\t0x565F17\n+#define\tMC_CCR46_VALUE\t0x565F17\n+#define\tMC_CCR47_VALUE\t0x0\n+#define\tMC_CCR48_VALUE\t0x0\n+#define\tMC_CCR49_VALUE\t0x0\n+#define\tMC_CCR50_VALUE\t0x0\n+#define\tMC_CCR51_VALUE\t0x0\n+#define\tMC_CCR52_VALUE\t0x133\n+#define\tMC_CCR53_VALUE\t0xF3014B27\n+#define\tMC_CCR54_VALUE\t0xF3014B27\n+#define\tMC_CCR55_VALUE\t0xF3014B27\n+#define\tMC_CCR56_VALUE\t0xF3014B27\n+#define\tMC_CCR57_VALUE\t0x7800301\n+#define\tMC_CCR58_VALUE\t0x7800301\n+#define\tMC_CCR59_VALUE\t0x7800301\n+#define\tMC_CCR60_VALUE\t0x7800301\n+#define\tMC_CCR61_VALUE\t0x4\n--- a/boards.cfg\n+++ b/boards.cfg\n@@ -546,6 +546,8 @@ Active  mips        mips32         vrx20\n Active  mips        mips32         vrx200      avm             fb3370              fb3370_eva                           fb3370:SYS_BOOT_EVA                                                                                                               Daniel Schwierzeck <daniel.schwierzeck@gmail.com>\n Active  mips        mips32         vrx200      avm             fb3370              fb3370_ram                           fb3370:SYS_BOOT_RAM                                                                                                               Daniel Schwierzeck <daniel.schwierzeck@gmail.com>\n Active  mips        mips32         vrx200      avm             fb3370              fb3370_sfspl                         fb3370:SYS_BOOT_SFSPL                                                                                                             Daniel Schwierzeck <daniel.schwierzeck@gmail.com>\n+Active  mips        mips32         vrx200      bt              bthomehubv5a        bthomehubv5a_nandspl                 bthomehubv5a:SYS_BOOT_NANDSPL                                                                                                     Martin Blumenstingl <martin.blumenstingl@googlemail.com>\n+Active  mips        mips32         vrx200      bt              bthomehubv5a        bthomehubv5a_ram                     bthomehubv5a:SYS_BOOT_RAM                                                                                                         Martin Blumenstingl <martin.blumenstingl@googlemail.com>\n Active  mips        mips32         vrx200      lantiq          easy80920           easy80920_nandspl                    easy80920:SYS_BOOT_NANDSPL                                                                                                        Daniel Schwierzeck <daniel.schwierzeck@gmail.com>\n Active  mips        mips32         vrx200      lantiq          easy80920           easy80920_nor                        easy80920:SYS_BOOT_NOR                                                                                                            Daniel Schwierzeck <daniel.schwierzeck@gmail.com>\n Active  mips        mips32         vrx200      lantiq          easy80920           easy80920_norspl                     easy80920:SYS_BOOT_NORSPL                                                                                                         Daniel Schwierzeck <daniel.schwierzeck@gmail.com>\n--- /dev/null\n+++ b/include/configs/bthomehubv5a.h\n@@ -0,0 +1,89 @@\n+/*\n+ * Copyright (C) 2016 Mathias Kresin <openwrt@kresin.me>\n+ * Copyright (C) 2015 Martin Blumenstingl <martin.blumenstingl@googlemail.com>\n+ * Based on p2812hnufx.h: (C) 2013 Luka Perkov <luka@openwrt.org>\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#ifndef __CONFIG_H\n+#define __CONFIG_H\n+\n+#define CONFIG_MACH_TYPE\t\"BTHOMEHUBV5A\"\n+#define CONFIG_IDENT_STRING\t\" \"CONFIG_MACH_TYPE\n+#define CONFIG_BOARD_NAME\t\"BT Home Hub 5A\"\n+\n+/* Configure SoC */\n+#define CONFIG_LTQ_SUPPORT_UART\t\t\t/* Enable ASC and UART */\n+\n+#define CONFIG_LTQ_SUPPORT_ETHERNET\t\t/* Enable ethernet */\n+\n+#define CONFIG_LTQ_SUPPORT_NAND_FLASH\t\t/* Have a ML01G100BHI00 NAND flash */\n+#define CONFIG_SYS_NAND_USE_FLASH_BBT\n+\n+#define CONFIG_LTQ_SUPPORT_SPL_NAND_FLASH\t/* Build NAND flash SPL */\n+#define CONFIG_SYS_NAND_PAGE_COUNT\t64\n+#define CONFIG_SYS_NAND_PAGE_SIZE\t2048\n+#define CONFIG_SYS_NAND_OOBSIZE\t\t64\n+#define CONFIG_SYS_NAND_BLOCK_SIZE\t(128 * 1024)\n+#define CONFIG_SYS_NAND_5_ADDR_CYCLE\n+\n+#define CONFIG_LTQ_SPL_COMP_LZO\t\t\t/* Compress SPL with LZO */\n+#define CONFIG_LTQ_SPL_CONSOLE\t\t\t/* Enable SPL console */\n+#define CONFIG_LTQ_SPL_MC_TUNE\n+\n+#define CONFIG_SYS_BOOTM_LEN\t\t0x1000000\t/* 16 MB */\n+\n+/* MTD devices */\n+#define CONFIG_MTD_PARTITIONS\n+#define CONFIG_MTD_DEVICE\n+#define CONFIG_CMD_MTDPARTS\n+#define MTDIDS_DEFAULT\t\t\t\"nand0=nand-xway\"\n+#define MTDPARTS_DEFAULT\t\t\"mtdparts=nand-xway:0x07e80000@0x100000(UBI)\"\n+\n+/* UBI */\n+#define CONFIG_RBTREE\n+#define CONFIG_CMD_UBI\n+#define CONFIG_CMD_UBIFS\n+\n+/* Environment */\n+#if defined(CONFIG_SYS_BOOT_NANDSPL)\n+#define CONFIG_SPL_TPL_OFFS\t\t0x800\n+#define CONFIG_SPL_TPL_SIZE\t\t0x5000\n+#define CONFIG_SPL_MC_TUNE_OFFS\t\t0x5800\n+#define CONFIG_SPL_U_BOOT_OFFS\t\t0x6000\n+#define CONFIG_SPL_U_BOOT_SIZE\t\t0x3a000\n+\n+#define CONFIG_ENV_IS_IN_NAND\n+#define CONFIG_ENV_OVERWRITE\n+#define CONFIG_ENV_OFFSET\t\t(640 * 1024)\n+#define CONFIG_ENV_SECT_SIZE\t\t(128 * 1024)\n+#else\n+#define CONFIG_ENV_IS_NOWHERE\n+#endif\n+\n+#define CONFIG_ENV_SIZE\t\t\t(128 * 1024)\n+\n+#define CONFIG_LOADADDR\t\t\tCONFIG_SYS_LOAD_ADDR\n+\n+/* Console */\n+#define CONFIG_LTQ_ADVANCED_CONSOLE\n+#define CONFIG_BAUDRATE\t\t\t115200\n+#define CONFIG_CONSOLE_ASC\t\t1\n+#define CONFIG_CONSOLE_DEV\t\t\"ttyLTQ1\"\n+\n+/* Pull in default board configs for Lantiq XWAY VRX200 */\n+#include <asm/lantiq/config.h>\n+#include <asm/arch/config.h>\n+\n+/* Pull in default OpenWrt configs for Lantiq SoC */\n+#include \"openwrt-lantiq-common.h\"\n+\n+#undef CONFIG_BOOTCOMMAND\n+#define CONFIG_BOOTCOMMAND \\\n+\t\"mtdparts default; ubi part UBI; ubi read ${loadaddr} kernel; bootm ${loadaddr}\"\n+\n+#define CONFIG_EXTRA_ENV_SETTINGS\t\\\n+\tCONFIG_ENV_LANTIQ_DEFAULTS\n+\n+#endif /* __CONFIG_H */\n"
  },
  {
    "path": "package/boot/uboot-lantiq/patches/100-portability.patch",
    "content": "--- a/include/image.h\n+++ b/include/image.h\n@@ -17,7 +17,6 @@\n #define __IMAGE_H__\n \n #include \"compiler.h\"\n-#include <asm/byteorder.h>\n \n /* Define this to avoid #ifdefs later on */\n struct lmb;\n@@ -36,6 +35,7 @@ struct lmb;\n \n #include <lmb.h>\n #include <asm/u-boot.h>\n+#include <asm/byteorder.h>\n #include <command.h>\n \n /* Take notice of the 'ignore' property for hashes */\n"
  },
  {
    "path": "package/boot/uboot-lantiq/patches/101-fix-crypt-header-clash.patch",
    "content": "Fix header clash with system /usr/include/sha1.h and sha256.h when libmd\nis installed.\n\nBackport of u-boot commit \"includes: move openssl headers to include/u-boot\"\nhttps://github.com/u-boot/u-boot/commit/2b9912e6a7df7b1f60beb7942bd0e6fa5f9d0167\n\n--- a/board/gdsys/p1022/controlcenterd-id.c\n+++ b/board/gdsys/p1022/controlcenterd-id.c\n@@ -30,7 +30,7 @@\n #include <i2c.h>\n #include <mmc.h>\n #include <tpm.h>\n-#include <sha1.h>\n+#include <u-boot/sha1.h>\n #include <asm/byteorder.h>\n #include <asm/unaligned.h>\n #include <pca9698.h>\n--- a/board/pcs440ep/pcs440ep.c\n+++ b/board/pcs440ep/pcs440ep.c\n@@ -13,7 +13,7 @@\n #include <asm/processor.h>\n #include <spd_sdram.h>\n #include <status_led.h>\n-#include <sha1.h>\n+#include <u-boot/sha1.h>\n #include <asm/io.h>\n #include <net.h>\n #include <ata.h>\n--- a/common/cmd_sha1sum.c\n+++ b/common/cmd_sha1sum.c\n@@ -11,7 +11,7 @@\n #include <common.h>\n #include <command.h>\n #include <hash.h>\n-#include <sha1.h>\n+#include <u-boot/sha1.h>\n \n int do_sha1sum(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])\n {\n--- a/common/hash.c\n+++ b/common/hash.c\n@@ -14,8 +14,8 @@\n #include <command.h>\n #include <hw_sha.h>\n #include <hash.h>\n-#include <sha1.h>\n-#include <sha256.h>\n+#include <u-boot/sha1.h>\n+#include <u-boot/sha256.h>\n #include <asm/io.h>\n #include <asm/errno.h>\n \n--- a/common/image-fit.c\n+++ b/common/image-fit.c\n@@ -21,7 +21,7 @@ DECLARE_GLOBAL_DATA_PTR;\n #endif /* !USE_HOSTCC*/\n \n #include <bootstage.h>\n-#include <sha1.h>\n+#include <u-boot/sha1.h>\n #include <u-boot/crc.h>\n #include <u-boot/md5.h>\n \n--- a/common/image.c\n+++ b/common/image.c\n@@ -34,7 +34,7 @@\n #endif\n \n #include <u-boot/md5.h>\n-#include <sha1.h>\n+#include <u-boot/sha1.h>\n #include <asm/errno.h>\n #include <asm/io.h>\n \n--- a/drivers/crypto/ace_sha.c\n+++ b/drivers/crypto/ace_sha.c\n@@ -5,8 +5,8 @@\n  * SPDX-License-Identifier:\tGPL-2.0+\n  */\n #include <common.h>\n-#include <sha256.h>\n-#include <sha1.h>\n+#include <u-boot/sha256.h>\n+#include <u-boot/sha1.h>\n #include <asm/errno.h>\n #include \"ace_sha.h\"\n \n--- /dev/null\n+++ b/include/u-boot/sha1.h\n@@ -0,0 +1 @@\n+#include \"../sha1.h\"\n--- /dev/null\n+++ b/include/u-boot/sha256.h\n@@ -0,0 +1 @@\n+#include \"../sha256.h\"\n--- a/lib/rsa/rsa-verify.c\n+++ b/lib/rsa/rsa-verify.c\n@@ -7,7 +7,7 @@\n #include <common.h>\n #include <fdtdec.h>\n #include <rsa.h>\n-#include <sha1.h>\n+#include <u-boot/sha1.h>\n #include <asm/byteorder.h>\n #include <asm/errno.h>\n #include <asm/unaligned.h>\n--- a/lib/sha1.c\n+++ b/lib/sha1.c\n@@ -36,7 +36,7 @@\n #include <string.h>\n #endif /* USE_HOSTCC */\n #include <watchdog.h>\n-#include \"sha1.h\"\n+#include <u-boot/sha1.h>\n \n /*\n  * 32-bit integer manipulation macros (big endian)\n--- a/lib/sha256.c\n+++ b/lib/sha256.c\n@@ -11,7 +11,7 @@\n #endif /* USE_HOSTCC */\n #include <watchdog.h>\n #include <linux/string.h>\n-#include <sha256.h>\n+#include <u-boot/sha256.h>\n \n /*\n  * 32-bit integer manipulation macros (big endian)\n--- a/lib/tpm.c\n+++ b/lib/tpm.c\n@@ -7,7 +7,7 @@\n \n #include <common.h>\n #include <stdarg.h>\n-#include <sha1.h>\n+#include <u-boot/sha1.h>\n #include <tpm.h>\n #include <asm/unaligned.h>\n \n--- a/tools/imls/imls.c\n+++ b/tools/imls/imls.c\n@@ -24,7 +24,7 @@\n #include <mtd/mtd-user.h>\n #endif\n \n-#include <sha1.h>\n+#include <u-boot/sha1.h>\n #include <libfdt.h>\n #include <fdt_support.h>\n #include <image.h>\n--- a/tools/mkimage.h\n+++ b/tools/mkimage.h\n@@ -18,7 +18,7 @@\n #include <sys/stat.h>\n #include <time.h>\n #include <unistd.h>\n-#include <sha1.h>\n+#include <u-boot/sha1.h>\n #include \"fdt_host.h\"\n \n #undef MKIMAGE_DEBUG\n--- a/tools/ubsha1.c\n+++ b/tools/ubsha1.c\n@@ -13,7 +13,7 @@\n #include <errno.h>\n #include <string.h>\n #include <sys/stat.h>\n-#include \"sha1.h\"\n+#include <u-boot/sha1.h>\n \n int main (int argc, char **argv)\n {\n"
  },
  {
    "path": "package/boot/uboot-lantiq/patches/200-fix-dtc-header-guard.patch",
    "content": "--- a/include/libfdt_env.h\n+++ b/include/libfdt_env.h\n@@ -8,6 +8,7 @@\n \n #ifndef _LIBFDT_ENV_H\n #define _LIBFDT_ENV_H\n+#define LIBFDT_ENV_H\n \n #include \"compiler.h\"\n #include \"linux/types.h\"\n--- a/include/libfdt.h\n+++ b/include/libfdt.h\n@@ -1,5 +1,6 @@\n #ifndef _LIBFDT_H\n #define _LIBFDT_H\n+#define LIBFDT_H\n /*\n  * libfdt - Flat Device Tree manipulation\n  * Copyright (C) 2006 David Gibson, IBM Corporation.\n"
  },
  {
    "path": "package/boot/uboot-layerscape/Makefile",
    "content": "#\n# Copyright (C) 2016 Jiang Yutang <jiangyutang1978@gmail.com>\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=uboot-layerscape\nPKG_VERSION:=21.08\nPKG_RELEASE:=$(AUTORELEASE)\n\nPKG_SOURCE_PROTO:=git\nPKG_SOURCE_URL:=https://source.codeaurora.org/external/qoriq/qoriq-components/u-boot\nPKG_SOURCE_VERSION:=LSDK-21.08\nPKG_MIRROR_HASH:=874e871755ef84ebbf35cc247f0979ec18ed1946e4dca71006a83463b2899db1\n\ninclude $(INCLUDE_DIR)/u-boot.mk\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine U-Boot/Default\n  BUILD_TARGET:=layerscape\n  BUILD_SUBTARGET:=armv8_64b\n  BUILD_DEVICES:=$(1)\n  UBOOT_IMAGE:=u-boot-dtb.bin\n  ENV_SIZE:=0x2000\nendef\n\ndefine U-Boot/fsl_ls1012a-frdm\n  NAME:=NXP LS1012AFRDM\n  UBOOT_CONFIG:=ls1012afrdm_tfa\n  ENV_SIZE:=0x40000\nendef\n\ndefine U-Boot/fsl_ls1012a-rdb\n  NAME:=NXP LS1012ARDB\n  UBOOT_CONFIG:=ls1012ardb_tfa\n  ENV_SIZE:=0x40000\nendef\n\ndefine U-Boot/fsl_ls1012a-frwy-sdboot\n  NAME:=NXP LS1012AFRWY\n  UBOOT_CONFIG:=ls1012afrwy_tfa\n  ENV_SIZE:=0x10000\nendef\n\ndefine U-Boot/fsl_ls1043a-rdb\n  NAME:=NXP LS1043ARDB\n  UBOOT_CONFIG:=ls1043ardb_tfa\nendef\n\ndefine U-Boot/fsl_ls1043a-rdb-sdboot\n  NAME:=NXP LS1043ARDB SD Card Boot\n  UBOOT_CONFIG:=ls1043ardb_tfa\nendef\n\ndefine U-Boot/fsl_ls1046a-frwy\n  NAME:=NXP LS1046AFRWY\n  UBOOT_CONFIG:=ls1046afrwy_tfa\nendef\n\ndefine U-Boot/fsl_ls1046a-frwy-sdboot\n  NAME:=NXP LS1046AFRWY SD Card Boot\n  UBOOT_CONFIG:=ls1046afrwy_tfa\nendef\n\ndefine U-Boot/fsl_ls1046a-rdb\n  NAME:=NXP LS1046ARDB\n  UBOOT_CONFIG:=ls1046ardb_tfa\nendef\n\ndefine U-Boot/fsl_ls1046a-rdb-sdboot\n  NAME:=NXP LS1046ARDB SD Card Boot\n  UBOOT_CONFIG:=ls1046ardb_tfa\nendef\n\ndefine U-Boot/fsl_ls1088a-rdb\n  NAME:=NXP LS1088ARDB\n  UBOOT_CONFIG:=ls1088ardb_tfa\nendef\n\ndefine U-Boot/fsl_ls1088a-rdb-sdboot\n  NAME:=NXP LS1088ARDB SD Card Boot\n  UBOOT_CONFIG:=ls1088ardb_tfa\nendef\n\ndefine U-Boot/fsl_ls2088a-rdb\n  NAME:=NXP LS2088ARDB\n  UBOOT_CONFIG:=ls2088ardb_tfa\nendef\n\ndefine U-Boot/fsl_lx2160a-rdb\n  NAME:=NXP LX2160ARDB\n  UBOOT_CONFIG:=lx2160ardb_tfa\nendef\n\ndefine U-Boot/fsl_lx2160a-rdb-sdboot\n  NAME:=NXP LX2160ARDB SD Card Boot\n  UBOOT_CONFIG:=lx2160ardb_tfa\nendef\n\ndefine U-Boot/fsl_ls1021a-twr\n  NAME:=NXP LS1021ATWR\n  BUILD_SUBTARGET:=armv7\n  UBOOT_CONFIG:=ls1021atwr_nor\n  ENV_SIZE:=0x20000\nendef\n\ndefine U-Boot/fsl_ls1021a-twr-sdboot\n  NAME:=NXP LS1021ATWR SD Card Boot\n  BUILD_SUBTARGET:=armv7\n  UBOOT_CONFIG:=ls1021atwr_sdcard_ifc\n  UBOOT_IMAGE:=u-boot-with-spl-pbl.bin\n  ENV_SIZE:=0x20000\nendef\n\ndefine U-Boot/fsl_ls1021a-iot-sdboot\n  NAME:=NXP LS1021AIOT SD Card Boot\n  BUILD_SUBTARGET:=armv7\n  UBOOT_CONFIG:=ls1021aiot_sdcard\n  UBOOT_IMAGE:=u-boot-with-spl-pbl.bin\n  ENV_SIZE:=0x2000\nendef\n\nUBOOT_TARGETS := \\\n  fsl_ls1012a-frdm \\\n  fsl_ls1012a-rdb \\\n  fsl_ls1012a-frwy-sdboot \\\n  fsl_ls1043a-rdb \\\n  fsl_ls1043a-rdb-sdboot \\\n  fsl_ls1046a-frwy \\\n  fsl_ls1046a-frwy-sdboot \\\n  fsl_ls1046a-rdb \\\n  fsl_ls1046a-rdb-sdboot \\\n  fsl_ls1088a-rdb \\\n  fsl_ls1088a-rdb-sdboot \\\n  fsl_ls2088a-rdb \\\n  fsl_lx2160a-rdb \\\n  fsl_lx2160a-rdb-sdboot \\\n  fsl_ls1021a-twr \\\n  fsl_ls1021a-twr-sdboot \\\n  fsl_ls1021a-iot-sdboot\n\ndefine Build/InstallDev\n\t$(INSTALL_DIR) $(STAGING_DIR_IMAGE)\n\t$(INSTALL_DATA) $(PKG_BUILD_DIR)/$(UBOOT_IMAGE) \\\n\t\t$(STAGING_DIR_IMAGE)/$(BUILD_VARIANT)-uboot.bin\n\t$(PKG_BUILD_DIR)/tools/mkenvimage -s $(ENV_SIZE) \\\n\t\t-o $(STAGING_DIR_IMAGE)/$(BUILD_VARIANT)-uboot-env.bin \\\n\t\tfiles/$(BUILD_VARIANT)-uEnv.txt\nendef\n\ndefine Package/u-boot/install/default\nendef\n\n$(eval $(call BuildPackage/U-Boot))\n"
  },
  {
    "path": "package/boot/uboot-layerscape/files/fsl_ls1012a-frdm-uEnv.txt",
    "content": "fdtaddr=0x8f000000\nloadaddr=0x81000000\nfdt_high=0x8fffffff\ninitrd_high=0xffffffffffffffff\nqspi_boot=sf probe 0:0;sf read $loadaddr 1000000 2800000;bootm $loadaddr\nbootargs=rootfstype=squashfs,jffs2 noinitrd earlycon=uart8250,mmio,0x21c0500 console=ttyS0,115200 mtdparts=1550000.spi:1m(bl2),4m(fip),1m(u-boot-env),4m(reserved-1),3m(pfe),2m(reserved-2),1m(dtb),-(firmware)\nbootcmd=echo starting OpenWrt ...;pfe stop;run qspi_boot\nbootdelay=3\nfsl_bootcmd_mcinitcmd_set=y\n"
  },
  {
    "path": "package/boot/uboot-layerscape/files/fsl_ls1012a-frwy-sdboot-uEnv.txt",
    "content": "fdtaddr=0x8f000000\nloadaddr=0x81000000\nfdt_high=0x8fffffff\ninitrd_high=0xffffffffffffffff\nsd_boot=ext4load mmc 0:1 $loadaddr fitImage;bootm $loadaddr\nbootargs=root=/dev/mmcblk0p2 rw rootwait rootfstype=squashfs,f2fs noinitrd earlycon=uart8250,mmio,0x21c0500 console=ttyS0,115200\nbootcmd=echo starting openwrt ...;pfe stop;run sd_boot\nbootdelay=3\nfsl_bootcmd_mcinitcmd_set=y\n"
  },
  {
    "path": "package/boot/uboot-layerscape/files/fsl_ls1012a-rdb-uEnv.txt",
    "content": "fdtaddr=0x8f000000\nloadaddr=0x81000000\nbootm_size=0x10000000\nqspi_boot=sf probe 0:0;sf read $fdtaddr f00000 100000;sf read $loadaddr 1000000 1000000;bootm $loadaddr - $fdtaddr\nbootargs=root=/dev/mtdblock8 rootfstype=squashfs,jffs2 noinitrd earlycon=uart8250,mmio,0x21c0500 console=ttyS0,115200 mtdparts=1550000.spi:1m(bl2),4m(fip),1m(u-boot-env),4m(reserved-1),3m(pfe),2m(reserved-2),1m(dtb),16m(kernel),32m(rootfs),49m@0xf00000(firmware)\nbootcmd=echo starting openwrt ...;pfe stop;run qspi_boot\nbootdelay=3\nfsl_bootcmd_mcinitcmd_set=y\n"
  },
  {
    "path": "package/boot/uboot-layerscape/files/fsl_ls1021a-iot-sdboot-uEnv.txt",
    "content": "fdtaddr=0x8f000000\nloadaddr=0x81000000\nfdt_high=0x8fffffff\ninitrd_high=0xffffffff\nsd_boot=ext4load mmc 0:1 $loadaddr fitImage;bootm $loadaddr\nbootargs=root=/dev/mmcblk0p2 rw rootwait rootfstype=squashfs,f2fs noinitrd earlycon=uart8250,mmio,0x21c0500 console=ttyS0,115200\nbootcmd=echo starting openwrt ...;run sd_boot\nbootdelay=3\nfsl_bootcmd_mcinitcmd_set=y\n"
  },
  {
    "path": "package/boot/uboot-layerscape/files/fsl_ls1021a-twr-sdboot-uEnv.txt",
    "content": "fdtaddr=0x8f000000\nloadaddr=0x81000000\nfdt_high=0x8fffffff\ninitrd_high=0xffffffff\nsd_boot=ext4load mmc 0:1 $loadaddr fitImage;bootm $loadaddr\nbootargs=root=/dev/mmcblk0p2 rw rootwait rootfstype=squashfs,f2fs noinitrd earlycon=uart8250,mmio,0x21c0500 console=ttyS0,115200\nbootcmd=echo starting openwrt ...;run sd_boot\nbootdelay=3\nfsl_bootcmd_mcinitcmd_set=y\n"
  },
  {
    "path": "package/boot/uboot-layerscape/files/fsl_ls1021a-twr-uEnv.txt",
    "content": "fdtaddr=0x8f000000\nloadaddr=0x81000000\nbootm_size=0x10000000\nnor_boot=cp.b 60f00000 $fdtaddr 100000;cp.b 61000000 $loadaddr 1000000;bootm $loadaddr - $fdtaddr\nbootargs=root=/dev/mtdblock6 rootfstype=squashfs,jffs2 noinitrd earlycon=uart8250,mmio,0x21c0500 console=ttyS0,115200 mtdparts=60000000.nor:1m(rcw),2m(u-boot),1m(u-boot-env),11m(reserved-1),1m(dtb),16m(kernel),32m(rootfs),49m@0xf00000(firmware) cma=64M@0x0-0xb0000000\nbootcmd=echo starting openwrt ...;run nor_boot\nbootdelay=3\nfsl_bootcmd_mcinitcmd_set=y\n"
  },
  {
    "path": "package/boot/uboot-layerscape/files/fsl_ls1043a-rdb-sdboot-uEnv.txt",
    "content": "fdtaddr=0x8f000000\nloadaddr=0x81000000\nfdt_high=0x8fffffff\ninitrd_high=0xffffffffffffffff\nhwconfig=fsl_ddr:bank_intlv=auto\nsd_boot=ext4load mmc 0:1 $loadaddr fitImage;bootm $loadaddr\nbootargs=root=/dev/mmcblk0p2 rw rootwait rootfstype=squashfs,f2fs noinitrd earlycon=uart8250,mmio,0x21c0500 console=ttyS0,115200\nbootcmd=echo starting openwrt ...;run sd_boot\nbootdelay=3\nfsl_bootcmd_mcinitcmd_set=y\n"
  },
  {
    "path": "package/boot/uboot-layerscape/files/fsl_ls1043a-rdb-uEnv.txt",
    "content": "fdtaddr=0x8f000000\nloadaddr=0x81000000\nbootm_size=0x10000000\nhwconfig=fsl_ddr:bank_intlv=auto\nnor_boot=cp.b 60f00000 $fdtaddr 100000;cp.b 61000000 $loadaddr 1000000;bootm $loadaddr - $fdtaddr\nbootargs=root=/dev/mtdblock8 rootfstype=squashfs,jffs2 noinitrd earlycon=uart8250,mmio,0x21c0500 console=ttyS0,115200 mtdparts=60000000.nor:1m(bl2),4m(fip),1m(u-boot-env),3m(reserved-1),256k(fman),5888k(reserved-2),1m(dtb),16m(kernel),32m(rootfs),49m@0xf00000(firmware)\nbootcmd=echo starting openwrt ...;run nor_boot\nbootdelay=3\nfsl_bootcmd_mcinitcmd_set=y\n"
  },
  {
    "path": "package/boot/uboot-layerscape/files/fsl_ls1046a-frwy-sdboot-uEnv.txt",
    "content": "fdtaddr=0x8f000000\nloadaddr=0x81000000\nbootm_size=0x10000000\nhwconfig=fsl_ddr:bank_intlv=auto\nsd_boot=ext4load mmc 0:1 ${loadaddr} fitImage;bootm ${loadaddr}\nbootargs=root=/dev/mmcblk0p2 rw rootwait rootfstype=squashfs,f2fs noinitrd earlycon=uart8250,mmio,0x21c0500 console=ttyS0,115200\nbootcmd=echo starting openwrt ...;run sd_boot\nbootdelay=3\nfsl_bootcmd_mcinitcmd_set=y\n"
  },
  {
    "path": "package/boot/uboot-layerscape/files/fsl_ls1046a-frwy-uEnv.txt",
    "content": "fdtaddr=0x8f000000\nloadaddr=0x81000000\nbootm_size=0x10000000\nhwconfig=fsl_ddr:bank_intlv=auto\nqspi_boot=sf probe 0:0;sf read $fdtaddr f00000 100000;sf read $loadaddr 1000000 1000000;bootm $loadaddr - $fdtaddr\nbootargs=root=/dev/mtdblock9 rootfstype=squashfs,jffs2 noinitrd earlycon=uart8250,mmio,0x21c0500 console=ttyS0,115200 mtdparts=1550000.spi:1m(bl2),4m(fip),1m(u-boot-env),3m(reserved-1),256k(fman),5888k(reserved-2),1m(dtb),16m(kernel),32m(rootfs),49m@0xf00000(firmware)\nbootcmd=echo starting openwrt ...;run qspi_boot\nbootdelay=3\nfsl_bootcmd_mcinitcmd_set=y\n"
  },
  {
    "path": "package/boot/uboot-layerscape/files/fsl_ls1046a-rdb-sdboot-uEnv.txt",
    "content": "fdtaddr=0x8f000000\nloadaddr=0x81000000\nfdt_high=0x8fffffff\ninitrd_high=0xffffffffffffffff\nhwconfig=fsl_ddr:bank_intlv=auto\nsd_boot=ext4load mmc 0:1 $loadaddr fitImage;bootm $loadaddr\nbootargs=root=/dev/mmcblk0p2 rw rootwait rootfstype=squashfs,f2fs noinitrd earlycon=uart8250,mmio,0x21c0500 console=ttyS0,115200\nbootcmd=echo starting openwrt ...;run sd_boot\nbootdelay=3\nfsl_bootcmd_mcinitcmd_set=y\n"
  },
  {
    "path": "package/boot/uboot-layerscape/files/fsl_ls1046a-rdb-uEnv.txt",
    "content": "fdtaddr=0x8f000000\nloadaddr=0x81000000\nbootm_size=0x10000000\nhwconfig=fsl_ddr:bank_intlv=auto\nqspi_boot=sf probe 0:0;sf read $fdtaddr f00000 100000;sf read $loadaddr 1000000 1000000;bootm $loadaddr - $fdtaddr\nbootargs=root=/dev/mtdblock9 rootfstype=squashfs,jffs2 noinitrd earlycon=uart8250,mmio,0x21c0500 console=ttyS0,115200 mtdparts=1550000.spi-0:1m(bl2),4m(fip),1m(u-boot-env),3m(reserved-1),256k(fman),5888k(reserved-2),1m(dtb),16m(kernel),32m(rootfs),49m@0xf00000(firmware)\nbootcmd=echo starting openwrt ...;run qspi_boot\nbootdelay=3\nfsl_bootcmd_mcinitcmd_set=y\n"
  },
  {
    "path": "package/boot/uboot-layerscape/files/fsl_ls1088a-rdb-sdboot-uEnv.txt",
    "content": "fdtaddr=0x8f000000\nloadaddr=0x81000000\nfdt_high=0xa0000000\ninitrd_high=0xffffffffffffffff\nhwconfig=fsl_ddr:bank_intlv=auto\nmc_init=mmc read 80000000 5000 1800;mmc read 80300000 7000 800;fsl_mc start mc 80000000 80300000;mmc read 80400000 6800 800;fsl_mc apply dpl 80400000\nsd_boot=ext4load mmc 0:1 $loadaddr fitImage;bootm $loadaddr\nbootargs=root=/dev/mmcblk0p2 rw rootwait rootfstype=squashfs,f2fs noinitrd earlycon=uart8250,mmio,0x21c0500 console=ttyS0,115200\nbootcmd=echo starting openwrt ...;run mc_init;run sd_boot\nbootdelay=3\nfsl_bootcmd_mcinitcmd_set=y\n"
  },
  {
    "path": "package/boot/uboot-layerscape/files/fsl_ls1088a-rdb-uEnv.txt",
    "content": "fdtaddr=0x8f000000\nloadaddr=0x81000000\nfdt_high=0xa0000000\ninitrd_high=0xffffffffffffffff\nhwconfig=fsl_ddr:bank_intlv=auto\nmc_init=sf probe 0:0;sf read 80000000 a00000 300000;sf read 80300000 e00000 100000;fsl_mc start mc 80000000 80300000;sf read 80400000 d00000 100000;fsl_mc apply dpl 80400000\nqspi_boot=sf probe 0:0;sf read $fdtaddr f00000 100000;sf read $loadaddr 1000000 1000000;bootm $loadaddr - $fdtaddr\nbootargs=root=/dev/mtdblock10 rootfstype=squashfs,jffs2 noinitrd earlycon=uart8250,mmio,0x21c0500 console=ttyS0,115200 mtdparts=20c0000.spi-0:1m(bl2),4m(fip),1m(u-boot-env),4m(reserved-1),3m(mc),1m(dpl),1m(dpc),1m(dtb),16m(kernel),32m(rootfs),49m@0xf00000(firmware)\nbootcmd=echo starting openwrt ...;run mc_init;run qspi_boot\nbootdelay=3\nfsl_bootcmd_mcinitcmd_set=y\n"
  },
  {
    "path": "package/boot/uboot-layerscape/files/fsl_ls2088a-rdb-uEnv.txt",
    "content": "fdtaddr=0x8f000000\nloadaddr=0x81000000\nfdt_high=0xa0000000\ninitrd_high=0xffffffffffffffff\nhwconfig=fsl_ddr:bank_intlv=auto\nmc_init=fsl_mc start mc 580a00000 580e00000;fsl_mc apply dpl 580d00000\nnor_boot=cp.b 580f00000 $fdtaddr 100000;cp.b 581000000 $loadaddr 1000000;bootm $loadaddr - $fdtaddr\nbootargs=root=/dev/mtdblock9 rootfstype=squashfs,jffs2 noinitrd earlycon=uart8250,mmio,0x21c0500 console=ttyS1,115200 mtdparts=580000000.nor:1m(bl2),4m(fip),1m(u-boot-env),4m(reserved-1),3m(mc),1m(dpl),1m(dpc),1m(dtb),16m(kernel),32m(rootfs),49m@0xf00000(firmware)\nbootcmd=echo starting openwrt ...;run mc_init;run nor_boot\nbootdelay=3\nfsl_bootcmd_mcinitcmd_set=y\n"
  },
  {
    "path": "package/boot/uboot-layerscape/files/fsl_lx2160a-rdb-sdboot-uEnv.txt",
    "content": "fdtaddr=0x8f000000\nloadaddr=0x81000000\nbootm_size=0x10000000\nhwconfig=fsl_ddr:bank_intlv=auto\nmc_init=mmc read 80000000 5000 1800;mmc read 80300000 7000 800;fsl_mc start mc 80000000 80300000;mmc read 80400000 6800 800;fsl_mc apply dpl 80400000\nsd_boot=ext4load mmc 0:1 ${loadaddr} fitImage;bootm ${loadaddr}\nbootargs=root=/dev/mmcblk0p2 rw rootwait rootfstype=squashfs,f2fs noinitrd earlycon=pl011,mmio32,0x21c0000 console=ttyAMA0,115200\nbootcmd=echo starting openwrt ...;run mc_init;run sd_boot\nbootdelay=3\nfsl_bootcmd_mcinitcmd_set=y\n"
  },
  {
    "path": "package/boot/uboot-layerscape/files/fsl_lx2160a-rdb-uEnv.txt",
    "content": "fdtaddr=0x8f000000\nloadaddr=0x81000000\nbootm_size=0x10000000\nhwconfig=fsl_ddr:bank_intlv=auto\nmc_init=sf probe 0:0;sf read 80000000 a00000 300000;sf read 80300000 e00000 100000;fsl_mc start mc 80000000 80300000;sf read 80400000 d00000 100000;fsl_mc apply dpl 80400000\nxspi_boot=sf probe 0:0;sf read $fdtaddr f00000 100000;sf read $loadaddr 1000000 1000000;bootm $loadaddr - $fdtaddr\nbootargs=root=/dev/mtdblock9 rootfstype=squashfs,jffs2 noinitrd earlycon=pl011,mmio32,0x21c0000 console=ttyAMA0,115200 mtdparts=20c0000.spi-0:1m(bl2),4m(fip),1m(u-boot-env),4m(reserved-1),3m(mc),1m(dpl),1m(dpc),1m(dtb),16m(kernel),32m(rootfs),49m@0xf00000(firmware)\nbootcmd=echo starting openwrt ...;run mc_init;run xspi_boot\nbootdelay=3\nfsl_bootcmd_mcinitcmd_set=y\n"
  },
  {
    "path": "package/boot/uboot-layerscape/patches/0001-board-ls1046ardb-force-PCI-device-enumeration.patch",
    "content": "From 089b90b11008ec95a56da12e31d11e3f31a9bb26 Mon Sep 17 00:00:00 2001\nFrom: Martin Schiller <ms@dev.tdt.de>\nDate: Wed, 17 Nov 2021 07:29:55 +0100\nSubject: [PATCH] board: ls1046ardb: force PCI device enumeration\n\nCommit 045ecf899252 (\"configs: enable DM_ETH support for LS1046ARDB\")\nresulted in the PCI bus no longer being implicitly enumerated.\n\nHowever, this is necessary for the fdt pcie fixups to work.\n\nTherefore, similar to commit 8b6558bd4187 (\"board: ls1088ardb:\ntransition to DM_ETH\"), pci_init() is now called in the board_init()\nroutine when CONFIG_DM_ETH is active.\n\nSigned-off-by: Martin Schiller <ms@dev.tdt.de>\nCC: Priyanka Jain <priyanka.jain@nxp.com>\n---\n board/freescale/ls1046ardb/ls1046ardb.c | 4 ++++\n 1 file changed, 4 insertions(+)\n\n--- a/board/freescale/ls1046ardb/ls1046ardb.c\n+++ b/board/freescale/ls1046ardb/ls1046ardb.c\n@@ -88,6 +88,10 @@ int board_init(void)\n \tppa_init();\n #endif\n \n+#if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH)\n+\tpci_init();\n+#endif\n+\n \t/* invert AQR105 IRQ pins polarity */\n \tout_be32(&scfg->intpcr, AQR105_IRQ_MASK);\n \n"
  },
  {
    "path": "package/boot/uboot-layerscape/patches/0002-board-ls1043ardb-force-PCI-device-enumeration.patch",
    "content": "From 64d2dffa8b51c1beb7e472690dcac965ac0f7ac4 Mon Sep 17 00:00:00 2001\nFrom: Martin Schiller <ms@dev.tdt.de>\nDate: Tue, 23 Nov 2021 07:24:19 +0100\nSubject: [PATCH] board: ls1043ardb: force PCI device enumeration\n\nCommit eb1986804d1d (\"configs: enable DM_ETH support for LS1043ARDB\")\nresulted in the PCI bus no longer being implicitly enumerated.\n\nHowever, this is necessary for the fdt pcie fixups to work.\n\nTherefore, similar to commit 8b6558bd4187 (\"board: ls1088ardb:\ntransition to DM_ETH\"), pci_init() is now called in the board_init()\nroutine when CONFIG_DM_ETH is active.\n\nSigned-off-by: Martin Schiller <ms@dev.tdt.de>\nCC: Priyanka Jain <priyanka.jain@nxp.com>\nCC: Camelia Groza <camelia.groza@nxp.com>\n---\n board/freescale/ls1043ardb/ls1043ardb.c | 4 ++++\n 1 file changed, 4 insertions(+)\n\n--- a/board/freescale/ls1043ardb/ls1043ardb.c\n+++ b/board/freescale/ls1043ardb/ls1043ardb.c\n@@ -214,6 +214,10 @@ int board_init(void)\n \tppa_init();\n #endif\n \n+#if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH)\n+\tpci_init();\n+#endif\n+\n #ifdef CONFIG_U_QE\n \tu_qe_init();\n #endif\n"
  },
  {
    "path": "package/boot/uboot-mediatek/Makefile",
    "content": "include $(TOPDIR)/rules.mk\ninclude $(INCLUDE_DIR)/kernel.mk\n\nPKG_VERSION:=2022.01\nPKG_HASH:=81b4543227db228c03f8a1bf5ddbc813b0bb8f6555ce46064ef721a6fc680413\nPKG_BUILD_DEPENDS:=arm-trusted-firmware-tools/host\n\ninclude $(INCLUDE_DIR)/u-boot.mk\ninclude $(INCLUDE_DIR)/package.mk\ninclude $(INCLUDE_DIR)/host-build.mk\n\ndefine U-Boot/Default\n  BUILD_TARGET:=mediatek\n  UBOOT_IMAGE:=u-boot-mtk.bin\nendef\n\ndefine U-Boot/mt7622_rfb1\n  NAME:=MT7622 Reference Board 1\n  UBOOT_CONFIG:=mt7622_rfb\n  BUILD_DEVICES:=mediatek_mt7622-rfb1 mediatek_mt7622-rfb1-ubi\n  BUILD_SUBTARGET:=mt7622\nendef\n\ndefine U-Boot/mt7622_linksys_e8450\n  NAME:=Linksys E8450\n  UBOOT_CONFIG:=mt7622_linksys_e8450\n  BUILD_DEVICES:=linksys_e8450-ubi\n  BUILD_SUBTARGET:=mt7622\n  UBOOT_IMAGE:=u-boot.fip\n  BL2_BOOTDEV:=snand\n  BL2_DDRBLOB:=1\n  DEPENDS:=+trusted-firmware-a-mt7622-snand-1ddr\nendef\n\ndefine U-Boot/mt7622_bananapi_bpi-r64-emmc\n  NAME:=BananaPi R64 (eMMC)\n  UBOOT_CONFIG:=mt7622_bananapi_bpi-r64-emmc\n  BUILD_DEVICES:=bananapi_bpi-r64\n  BUILD_SUBTARGET:=mt7622\n  UBOOT_IMAGE:=u-boot.fip\n  BL2_BOOTDEV:=emmc\n  BL2_DDRBLOB:=2\n  DEPENDS:=+trusted-firmware-a-mt7622-emmc-2ddr\nendef\n\ndefine U-Boot/mt7622_bananapi_bpi-r64-sdmmc\n  NAME:=BananaPi R64 (SDMMC)\n  UBOOT_CONFIG:=mt7622_bananapi_bpi-r64-sdmmc\n  BUILD_DEVICES:=bananapi_bpi-r64\n  BUILD_SUBTARGET:=mt7622\n  UBOOT_IMAGE:=u-boot.fip\n  BL2_BOOTDEV:=sdmmc\n  BL2_DDRBLOB:=2\n  DEPENDS:=+trusted-firmware-a-mt7622-sdmmc-2ddr\nendef\n\ndefine U-Boot/mt7622_bananapi_bpi-r64-snand\n  NAME:=BananaPi R64 (SNAND)\n  UBOOT_CONFIG:=mt7622_bananapi_bpi-r64-snand\n  BUILD_DEVICES:=bananapi_bpi-r64\n  BUILD_SUBTARGET:=mt7622\n  UBOOT_IMAGE:=u-boot.fip\n  BL2_BOOTDEV:=snand\n  BL2_DDRBLOB:=2\n  DEPENDS:=+trusted-firmware-a-mt7622-snand-2ddr\nendef\n\ndefine U-Boot/mt7622_ubnt_unifi-6-lr\n  NAME:=Ubiquiti UniFi 6 LR\n  UBOOT_CONFIG:=mt7622_ubnt_unifi-6-lr\n  BUILD_DEVICES:=ubnt_unifi-6-lr-ubootmod\n  BUILD_SUBTARGET:=mt7622\n  UBOOT_IMAGE:=u-boot.fip\n  BL2_BOOTDEV:=nor\n  BL2_DDRBLOB:=2\n  DEPENDS:=+trusted-firmware-a-mt7622-nor-2ddr\nendef\n\ndefine U-Boot/mt7623a_unielec_u7623\n  NAME:=UniElec U7623 (mt7623)\n  BUILD_DEVICES:=unielec_u7623-02\n  BUILD_SUBTARGET:=mt7623\n  UBOOT_CONFIG:=mt7623a_unielec_u7623_02\nendef\n\ndefine U-Boot/mt7623n_bpir2\n  NAME:=Banana Pi R2 (mt7623)\n  BUILD_DEVICES:=bananapi_bpi-r2\n  BUILD_SUBTARGET:=mt7623\n  UBOOT_IMAGE:=u-boot.bin\n  UBOOT_CONFIG:=mt7623n_bpir2\nendef\n\ndefine U-Boot/mt7629_rfb\n  NAME:=MT7629 Reference Board\n  BUILD_SUBTARGET:=mt7629\n  BUILD_DEVICES:=mediatek_mt7629-rfb\n  UBOOT_CONFIG:=mt7629_rfb\nendef\n\nUBOOT_TARGETS := \\\n\tmt7622_bananapi_bpi-r64-emmc \\\n\tmt7622_bananapi_bpi-r64-sdmmc \\\n\tmt7622_bananapi_bpi-r64-snand \\\n\tmt7622_linksys_e8450 \\\n\tmt7622_rfb1 \\\n\tmt7622_ubnt_unifi-6-lr \\\n\tmt7623n_bpir2 \\\n\tmt7623a_unielec_u7623 \\\n\tmt7629_rfb\n\nUBOOT_MAKE_FLAGS += $(UBOOT_IMAGE:.fip=.bin)\n\ndefine Build/fip-image\n\t$(STAGING_DIR_HOST)/bin/fiptool create \\\n\t\t--soc-fw $(STAGING_DIR_IMAGE)/$(BUILD_SUBTARGET)-$(BL2_BOOTDEV)-$(BL2_DDRBLOB)ddr-bl31.bin \\\n\t\t--nt-fw $(PKG_BUILD_DIR)/u-boot.bin \\\n\t\t$(PKG_BUILD_DIR)/u-boot.fip\nendef\n\ndefine Build/Configure\n\t$(call Build/Configure/U-Boot)\n\tsed -i 's/CONFIG_TOOLS_LIBCRYPTO=y/# CONFIG_TOOLS_LIBCRYPTO is not set/' $(PKG_BUILD_DIR)/.config\nendef\n\ndefine Build/Compile\n\t$(call Build/Compile/U-Boot)\nifeq ($(UBOOT_IMAGE),u-boot.fip))\n\t$(call Build/fip-image)\nendif\nendef\n\n# don't stage files to bindir, let target/linux/mediatek/image/*.mk do that\ndefine Package/u-boot/install\nendef\n\ndefine Build/InstallDev\n\t$(INSTALL_DIR) $(STAGING_DIR_IMAGE)\n\t$(INSTALL_DATA) $(PKG_BUILD_DIR)/$(UBOOT_IMAGE) $(STAGING_DIR_IMAGE)/$(BUILD_VARIANT)-$(UBOOT_IMAGE)\nendef\n\n$(eval $(call BuildPackage/U-Boot))\n"
  },
  {
    "path": "package/boot/uboot-mediatek/patches/000-mtk-01-Revert-clk-Add-debugging-for-return-values.patch",
    "content": "From 34ed9f6d3018d32c7c015e57c9985d3c4c07b706 Mon Sep 17 00:00:00 2001\nFrom: Daniel Golle <daniel@makrotopia.org>\nDate: Thu, 11 Mar 2021 10:28:53 +0000\nSubject: [PATCH 01/12] Revert \"clk: Add debugging for return values\"\n\nThis reverts commit 5c5992cb90cf9ca4d51e38d9a95a13c293904df5.\n---\n drivers/clk/clk-uclass.c | 16 +++++-----------\n 1 file changed, 5 insertions(+), 11 deletions(-)\n\n--- a/drivers/clk/clk-uclass.c\n+++ b/drivers/clk/clk-uclass.c\n@@ -88,7 +88,7 @@ static int clk_get_by_index_tail(int ret\n \tif (ret) {\n \t\tdebug(\"%s: uclass_get_device_by_of_offset failed: err=%d\\n\",\n \t\t      __func__, ret);\n-\t\treturn log_msg_ret(\"get\", ret);\n+\t\treturn ret;\n \t}\n \n \tclk->dev = dev_clk;\n@@ -101,15 +101,14 @@ static int clk_get_by_index_tail(int ret\n \t\tret = clk_of_xlate_default(clk, args);\n \tif (ret) {\n \t\tdebug(\"of_xlate() failed: %d\\n\", ret);\n-\t\treturn log_msg_ret(\"xlate\", ret);\n+\t\treturn ret;\n \t}\n \n \treturn clk_request(dev_clk, clk);\n err:\n \tdebug(\"%s: Node '%s', property '%s', failed to request CLK index %d: %d\\n\",\n \t      __func__, ofnode_get_name(node), list_name, index, ret);\n-\n-\treturn log_msg_ret(\"prop\", ret);\n+\treturn ret;\n }\n \n static int clk_get_by_indexed_prop(struct udevice *dev, const char *prop_name,\n@@ -128,7 +127,7 @@ static int clk_get_by_indexed_prop(struc\n \tif (ret) {\n \t\tdebug(\"%s: fdtdec_parse_phandle_with_args failed: err=%d\\n\",\n \t\t      __func__, ret);\n-\t\treturn log_ret(ret);\n+\t\treturn ret;\n \t}\n \n \n@@ -501,7 +500,6 @@ int clk_free(struct clk *clk)\n ulong clk_get_rate(struct clk *clk)\n {\n \tconst struct clk_ops *ops;\n-\tint ret;\n \n \tdebug(\"%s(clk=%p)\\n\", __func__, clk);\n \tif (!clk_valid(clk))\n@@ -511,11 +509,7 @@ ulong clk_get_rate(struct clk *clk)\n \tif (!ops->get_rate)\n \t\treturn -ENOSYS;\n \n-\tret = ops->get_rate(clk);\n-\tif (ret)\n-\t\treturn log_ret(ret);\n-\n-\treturn 0;\n+\treturn ops->get_rate(clk);\n }\n \n struct clk *clk_get_parent(struct clk *clk)\n"
  },
  {
    "path": "package/boot/uboot-mediatek/patches/000-mtk-09-board-mediatek-add-more-network-configurations.patch",
    "content": "From 938ba7ed996a86c9cc7af08b69df57b8b4c09510 Mon Sep 17 00:00:00 2001\nFrom: Weijie Gao <weijie.gao@mediatek.com>\nDate: Tue, 2 Mar 2021 15:47:45 +0800\nSubject: [PATCH 02/12] board: mediatek: add more network configurations\n\nMake the network configurations uniform for mediatek boards\n\nSigned-off-by: Weijie Gao <weijie.gao@mediatek.com>\n---\n include/configs/mt7622.h | 3 ++-\n include/configs/mt7623.h | 1 +\n include/configs/mt7629.h | 1 +\n 3 files changed, 4 insertions(+), 1 deletion(-)\n\n--- a/include/configs/mt7622.h\n+++ b/include/configs/mt7622.h\n@@ -30,6 +30,7 @@\n \n /* Ethernet */\n #define CONFIG_IPADDR\t\t\t192.168.1.1\n-#define CONFIG_SERVERIP\t\t\t192.168.1.3\n+#define CONFIG_SERVERIP\t\t\t192.168.1.2\n+#define CONFIG_NETMASK\t\t\t255.255.255.0\n \n #endif\n--- a/include/configs/mt7623.h\n+++ b/include/configs/mt7623.h\n@@ -45,6 +45,7 @@\n /* Ethernet */\n #define CONFIG_IPADDR\t\t\t192.168.1.1\n #define CONFIG_SERVERIP\t\t\t192.168.1.2\n+#define CONFIG_NETMASK\t\t\t255.255.255.0\n \n #ifdef CONFIG_DISTRO_DEFAULTS\n \n--- a/include/configs/mt7629.h\n+++ b/include/configs/mt7629.h\n@@ -45,5 +45,6 @@\n /* Ethernet */\n #define CONFIG_IPADDR\t\t\t192.168.1.1\n #define CONFIG_SERVERIP\t\t\t192.168.1.2\n+#define CONFIG_NETMASK\t\t\t255.255.255.0\n \n #endif\n"
  },
  {
    "path": "package/boot/uboot-mediatek/patches/000-mtk-10-mmc-mtk-sd-increase-the-minimum-bus-frequency.patch",
    "content": "From 1d4fcea788e579934a1ad0a90cecd6e1761127d1 Mon Sep 17 00:00:00 2001\nFrom: Weijie Gao <weijie.gao@mediatek.com>\nDate: Tue, 2 Mar 2021 15:56:17 +0800\nSubject: [PATCH 03/12] mmc: mtk-sd: increase the minimum bus frequency\n\nWith a 48MHz input clock, the lowest bus frequency can be as low as\n48000000 / (4 * 4095) = 2930Hz. Such an extremely low frequency will cause\nthe mmc framework take seconds to finish the initialization.\n\nLimiting the minimum bus frequency to a slightly higher value can solve the\nissue without any side effects.\n\nSigned-off-by: Weijie Gao <weijie.gao@mediatek.com>\n---\n drivers/mmc/mtk-sd.c | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/drivers/mmc/mtk-sd.c\n+++ b/drivers/mmc/mtk-sd.c\n@@ -232,7 +232,7 @@\n \n #define SCLK_CYCLES_SHIFT\t\t20\n \n-#define MIN_BUS_CLK\t\t\t200000\n+#define MIN_BUS_CLK\t\t\t260000\n \n #define CMD_INTS_MASK\t\\\n \t(MSDC_INT_CMDRDY | MSDC_INT_RSPCRCERR | MSDC_INT_CMDTMO)\n"
  },
  {
    "path": "package/boot/uboot-mediatek/patches/000-mtk-14-drivers-mtd-add-support-for-MediaTek-SPI-NAND-flash-.patch",
    "content": "From d6c5309185aae3d9ecf80eae8b248522d11a6136 Mon Sep 17 00:00:00 2001\nFrom: Weijie Gao <weijie.gao@mediatek.com>\nDate: Tue, 2 Mar 2021 16:58:01 +0800\nSubject: [PATCH 04/12] drivers: mtd: add support for MediaTek SPI-NAND flash\n controller\n\nAdd mtd driver for MediaTek SPI-NAND flash controller\n\nThis driver is written from scratch, and uses standard mtd framework, not\nthe nand framework which only applies for raw parallel nand flashes so that\nthis driver can have a smaller size in binary.\n\nSigned-off-by: Weijie Gao <weijie.gao@mediatek.com>\n---\n drivers/mtd/Kconfig                   |    2 +\n drivers/mtd/Makefile                  |    2 +\n drivers/mtd/mtk-snand/Kconfig         |   21 +\n drivers/mtd/mtk-snand/Makefile        |   11 +\n drivers/mtd/mtk-snand/mtk-snand-def.h |  266 ++++\n drivers/mtd/mtk-snand/mtk-snand-ecc.c |  264 ++++\n drivers/mtd/mtk-snand/mtk-snand-ids.c |  511 +++++++\n drivers/mtd/mtk-snand/mtk-snand-mtd.c |  526 ++++++++\n drivers/mtd/mtk-snand/mtk-snand-os.c  |   39 +\n drivers/mtd/mtk-snand/mtk-snand-os.h  |  120 ++\n drivers/mtd/mtk-snand/mtk-snand.c     | 1776 +++++++++++++++++++++++++\n drivers/mtd/mtk-snand/mtk-snand.h     |   77 ++\n 12 files changed, 3615 insertions(+)\n create mode 100644 drivers/mtd/mtk-snand/Kconfig\n create mode 100644 drivers/mtd/mtk-snand/Makefile\n create mode 100644 drivers/mtd/mtk-snand/mtk-snand-def.h\n create mode 100644 drivers/mtd/mtk-snand/mtk-snand-ecc.c\n create mode 100644 drivers/mtd/mtk-snand/mtk-snand-ids.c\n create mode 100644 drivers/mtd/mtk-snand/mtk-snand-mtd.c\n create mode 100644 drivers/mtd/mtk-snand/mtk-snand-os.c\n create mode 100644 drivers/mtd/mtk-snand/mtk-snand-os.h\n create mode 100644 drivers/mtd/mtk-snand/mtk-snand.c\n create mode 100644 drivers/mtd/mtk-snand/mtk-snand.h\n\n--- a/drivers/mtd/Kconfig\n+++ b/drivers/mtd/Kconfig\n@@ -116,6 +116,8 @@ config STM32_FLASH\n \t This is the driver of embedded flash for some STMicroelectronics\n \t STM32 MCU.\n \n+source \"drivers/mtd/mtk-snand/Kconfig\"\n+\n source \"drivers/mtd/nand/Kconfig\"\n \n config SYS_NAND_MAX_CHIPS\n--- a/drivers/mtd/Makefile\n+++ b/drivers/mtd/Makefile\n@@ -39,3 +39,5 @@ obj-$(CONFIG_$(SPL_TPL_)SPI_FLASH_SUPPOR\n obj-$(CONFIG_SPL_UBI) += ubispl/\n \n endif\n+\n+obj-$(CONFIG_MTK_SPI_NAND) += mtk-snand/\n--- /dev/null\n+++ b/drivers/mtd/mtk-snand/Kconfig\n@@ -0,0 +1,21 @@\n+#\n+# Copyright (C) 2020 MediaTek Inc. All rights reserved.\n+# Author: Weijie Gao <weijie.gao@mediatek.com>\n+#\n+# SPDX-License-Identifier: GPL-2.0\n+#\n+\n+config MTK_SPI_NAND\n+\ttristate \"MediaTek SPI NAND flash controller driver\"\n+\tdepends on !MTD_SPI_NAND\n+\thelp\n+\t  This option enables access to SPI-NAND flashes through the\n+\t  MediaTek SPI NAND Flash Controller\n+\n+config MTK_SPI_NAND_MTD\n+\ttristate \"MTD support for MediaTek SPI NAND flash controller\"\n+\tdepends on DM_MTD\n+\tdepends on MTK_SPI_NAND\n+\thelp\n+\t  This option enables access to SPI-NAND flashes through the\n+\t  MTD interface of MediaTek SPI NAND Flash Controller\n--- /dev/null\n+++ b/drivers/mtd/mtk-snand/Makefile\n@@ -0,0 +1,11 @@\n+#\n+# Copyright (C) 2020 MediaTek Inc. All rights reserved.\n+# Author: Weijie Gao <weijie.gao@mediatek.com>\n+#\n+# SPDX-License-Identifier: GPL-2.0\n+#\n+\n+obj-y += mtk-snand.o mtk-snand-ecc.o mtk-snand-ids.o mtk-snand-os.o\n+obj-$(CONFIG_MTK_SPI_NAND_MTD) += mtk-snand-mtd.o\n+\n+ccflags-y += -DPRIVATE_MTK_SNAND_HEADER\n--- /dev/null\n+++ b/drivers/mtd/mtk-snand/mtk-snand-def.h\n@@ -0,0 +1,266 @@\n+/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */\n+/*\n+ * Copyright (C) 2020 MediaTek Inc. All Rights Reserved.\n+ *\n+ * Author: Weijie Gao <weijie.gao@mediatek.com>\n+ */\n+\n+#ifndef _MTK_SNAND_DEF_H_\n+#define _MTK_SNAND_DEF_H_\n+\n+#include \"mtk-snand-os.h\"\n+\n+#ifdef PRIVATE_MTK_SNAND_HEADER\n+#include \"mtk-snand.h\"\n+#else\n+#include <mtk-snand.h>\n+#endif\n+\n+struct mtk_snand_plat_dev;\n+\n+enum snand_flash_io {\n+\tSNAND_IO_1_1_1,\n+\tSNAND_IO_1_1_2,\n+\tSNAND_IO_1_2_2,\n+\tSNAND_IO_1_1_4,\n+\tSNAND_IO_1_4_4,\n+\n+\t__SNAND_IO_MAX\n+};\n+\n+#define SPI_IO_1_1_1\t\t\tBIT(SNAND_IO_1_1_1)\n+#define SPI_IO_1_1_2\t\t\tBIT(SNAND_IO_1_1_2)\n+#define SPI_IO_1_2_2\t\t\tBIT(SNAND_IO_1_2_2)\n+#define SPI_IO_1_1_4\t\t\tBIT(SNAND_IO_1_1_4)\n+#define SPI_IO_1_4_4\t\t\tBIT(SNAND_IO_1_4_4)\n+\n+struct snand_opcode {\n+\tuint8_t opcode;\n+\tuint8_t dummy;\n+};\n+\n+struct snand_io_cap {\n+\tuint8_t caps;\n+\tstruct snand_opcode opcodes[__SNAND_IO_MAX];\n+};\n+\n+#define SNAND_OP(_io, _opcode, _dummy) [_io] = { .opcode = (_opcode), \\\n+\t\t\t\t\t\t .dummy = (_dummy) }\n+\n+#define SNAND_IO_CAP(_name, _caps, ...) \\\n+\tstruct snand_io_cap _name = { .caps = (_caps), \\\n+\t\t\t\t      .opcodes = { __VA_ARGS__ } }\n+\n+#define SNAND_MAX_ID_LEN\t\t4\n+\n+enum snand_id_type {\n+\tSNAND_ID_DYMMY,\n+\tSNAND_ID_ADDR = SNAND_ID_DYMMY,\n+\tSNAND_ID_DIRECT,\n+\n+\t__SNAND_ID_TYPE_MAX\n+};\n+\n+struct snand_id {\n+\tuint8_t type;\t/* enum snand_id_type */\n+\tuint8_t len;\n+\tuint8_t id[SNAND_MAX_ID_LEN];\n+};\n+\n+#define SNAND_ID(_type, ...) \\\n+\t{ .type = (_type), .id = { __VA_ARGS__ }, \\\n+\t  .len = sizeof((uint8_t[]) { __VA_ARGS__ }) }\n+\n+struct snand_mem_org {\n+\tuint16_t pagesize;\n+\tuint16_t sparesize;\n+\tuint16_t pages_per_block;\n+\tuint16_t blocks_per_die;\n+\tuint16_t planes_per_die;\n+\tuint16_t ndies;\n+};\n+\n+#define SNAND_MEMORG(_ps, _ss, _ppb, _bpd, _ppd, _nd) \\\n+\t{ .pagesize = (_ps), .sparesize = (_ss), .pages_per_block = (_ppb), \\\n+\t  .blocks_per_die = (_bpd), .planes_per_die = (_ppd), .ndies = (_nd) }\n+\n+typedef int (*snand_select_die_t)(struct mtk_snand *snf, uint32_t dieidx);\n+\n+struct snand_flash_info {\n+\tconst char *model;\n+\tstruct snand_id id;\n+\tconst struct snand_mem_org memorg;\n+\tconst struct snand_io_cap *cap_rd;\n+\tconst struct snand_io_cap *cap_pl;\n+\tsnand_select_die_t select_die;\n+};\n+\n+#define SNAND_INFO(_model, _id, _memorg, _cap_rd, _cap_pl, ...) \\\n+\t{ .model = (_model), .id = _id, .memorg = _memorg, \\\n+\t  .cap_rd = (_cap_rd), .cap_pl = (_cap_pl), __VA_ARGS__ }\n+\n+const struct snand_flash_info *snand_flash_id_lookup(enum snand_id_type type,\n+\t\t\t\t\t\t     const uint8_t *id);\n+\n+struct mtk_snand_soc_data {\n+\tuint16_t sector_size;\n+\tuint16_t max_sectors;\n+\tuint16_t fdm_size;\n+\tuint16_t fdm_ecc_size;\n+\tuint16_t fifo_size;\n+\n+\tbool bbm_swap;\n+\tbool empty_page_check;\n+\tuint32_t mastersta_mask;\n+\n+\tconst uint8_t *spare_sizes;\n+\tuint32_t num_spare_size;\n+};\n+\n+enum mtk_ecc_regs {\n+\tECC_DECDONE,\n+};\n+\n+struct mtk_ecc_soc_data {\n+\tconst uint8_t *ecc_caps;\n+\tuint32_t num_ecc_cap;\n+\tconst uint32_t *regs;\n+\tuint16_t mode_shift;\n+\tuint8_t errnum_bits;\n+\tuint8_t errnum_shift;\n+};\n+\n+struct mtk_snand {\n+\tstruct mtk_snand_plat_dev *pdev;\n+\n+\tvoid __iomem *nfi_base;\n+\tvoid __iomem *ecc_base;\n+\n+\tenum mtk_snand_soc soc;\n+\tconst struct mtk_snand_soc_data *nfi_soc;\n+\tconst struct mtk_ecc_soc_data *ecc_soc;\n+\tbool snfi_quad_spi;\n+\tbool quad_spi_op;\n+\n+\tconst char *model;\n+\tuint64_t size;\n+\tuint64_t die_size;\n+\tuint32_t erasesize;\n+\tuint32_t writesize;\n+\tuint32_t oobsize;\n+\n+\tuint32_t num_dies;\n+\tsnand_select_die_t select_die;\n+\n+\tuint8_t opcode_rfc;\n+\tuint8_t opcode_pl;\n+\tuint8_t dummy_rfc;\n+\tuint8_t mode_rfc;\n+\tuint8_t mode_pl;\n+\n+\tuint32_t writesize_mask;\n+\tuint32_t writesize_shift;\n+\tuint32_t erasesize_mask;\n+\tuint32_t erasesize_shift;\n+\tuint64_t die_mask;\n+\tuint32_t die_shift;\n+\n+\tuint32_t spare_per_sector;\n+\tuint32_t raw_sector_size;\n+\tuint32_t ecc_strength;\n+\tuint32_t ecc_steps;\n+\tuint32_t ecc_bytes;\n+\tuint32_t ecc_parity_bits;\n+\n+\tuint8_t *page_cache;\t/* Used by read/write page */\n+\tuint8_t *buf_cache;\t/* Used by block bad/markbad & auto_oob */\n+};\n+\n+enum mtk_snand_log_category {\n+\tSNAND_LOG_NFI,\n+\tSNAND_LOG_SNFI,\n+\tSNAND_LOG_ECC,\n+\tSNAND_LOG_CHIP,\n+\n+\t__SNAND_LOG_CAT_MAX\n+};\n+\n+int mtk_ecc_setup(struct mtk_snand *snf, void *fmdaddr, uint32_t max_ecc_bytes,\n+\t\t  uint32_t msg_size);\n+int mtk_snand_ecc_encoder_start(struct mtk_snand *snf);\n+void mtk_snand_ecc_encoder_stop(struct mtk_snand *snf);\n+int mtk_snand_ecc_decoder_start(struct mtk_snand *snf);\n+void mtk_snand_ecc_decoder_stop(struct mtk_snand *snf);\n+int mtk_ecc_wait_decoder_done(struct mtk_snand *snf);\n+int mtk_ecc_check_decode_error(struct mtk_snand *snf, uint32_t page);\n+\n+int mtk_snand_mac_io(struct mtk_snand *snf, const uint8_t *out, uint32_t outlen,\n+\t\t     uint8_t *in, uint32_t inlen);\n+int mtk_snand_set_feature(struct mtk_snand *snf, uint32_t addr, uint32_t val);\n+\n+int mtk_snand_log(struct mtk_snand_plat_dev *pdev,\n+\t\t  enum mtk_snand_log_category cat, const char *fmt, ...);\n+\n+#define snand_log_nfi(pdev, fmt, ...) \\\n+\tmtk_snand_log(pdev, SNAND_LOG_NFI, fmt, ##__VA_ARGS__)\n+\n+#define snand_log_snfi(pdev, fmt, ...) \\\n+\tmtk_snand_log(pdev, SNAND_LOG_SNFI, fmt, ##__VA_ARGS__)\n+\n+#define snand_log_ecc(pdev, fmt, ...) \\\n+\tmtk_snand_log(pdev, SNAND_LOG_ECC, fmt, ##__VA_ARGS__)\n+\n+#define snand_log_chip(pdev, fmt, ...) \\\n+\tmtk_snand_log(pdev, SNAND_LOG_CHIP, fmt, ##__VA_ARGS__)\n+\n+/* ffs64 */\n+static inline int mtk_snand_ffs64(uint64_t x)\n+{\n+\tif (!x)\n+\t\treturn 0;\n+\n+\tif (!(x & 0xffffffff))\n+\t\treturn ffs((uint32_t)(x >> 32)) + 32;\n+\n+\treturn ffs((uint32_t)(x & 0xffffffff));\n+}\n+\n+/* NFI dummy commands */\n+#define NFI_CMD_DUMMY_READ\t\t0x00\n+#define NFI_CMD_DUMMY_WRITE\t\t0x80\n+\n+/* SPI-NAND opcodes */\n+#define SNAND_CMD_RESET\t\t\t0xff\n+#define SNAND_CMD_BLOCK_ERASE\t\t0xd8\n+#define SNAND_CMD_READ_FROM_CACHE_QUAD\t0xeb\n+#define SNAND_CMD_WINBOND_SELECT_DIE\t0xc2\n+#define SNAND_CMD_READ_FROM_CACHE_DUAL\t0xbb\n+#define SNAND_CMD_READID\t\t0x9f\n+#define SNAND_CMD_READ_FROM_CACHE_X4\t0x6b\n+#define SNAND_CMD_READ_FROM_CACHE_X2\t0x3b\n+#define SNAND_CMD_PROGRAM_LOAD_X4\t0x32\n+#define SNAND_CMD_SET_FEATURE\t\t0x1f\n+#define SNAND_CMD_READ_TO_CACHE\t\t0x13\n+#define SNAND_CMD_PROGRAM_EXECUTE\t0x10\n+#define SNAND_CMD_GET_FEATURE\t\t0x0f\n+#define SNAND_CMD_READ_FROM_CACHE\t0x0b\n+#define SNAND_CMD_WRITE_ENABLE\t\t0x06\n+#define SNAND_CMD_PROGRAM_LOAD\t\t0x02\n+\n+/* SPI-NAND feature addresses */\n+#define SNAND_FEATURE_MICRON_DIE_ADDR\t0xd0\n+#define SNAND_MICRON_DIE_SEL_1\t\tBIT(6)\n+\n+#define SNAND_FEATURE_STATUS_ADDR\t0xc0\n+#define SNAND_STATUS_OIP\t\tBIT(0)\n+#define SNAND_STATUS_WEL\t\tBIT(1)\n+#define SNAND_STATUS_ERASE_FAIL\t\tBIT(2)\n+#define SNAND_STATUS_PROGRAM_FAIL\tBIT(3)\n+\n+#define SNAND_FEATURE_CONFIG_ADDR\t0xb0\n+#define SNAND_FEATURE_QUAD_ENABLE\tBIT(0)\n+#define SNAND_FEATURE_ECC_EN\t\tBIT(4)\n+\n+#define SNAND_FEATURE_PROTECT_ADDR\t0xa0\n+\n+#endif /* _MTK_SNAND_DEF_H_ */\n--- /dev/null\n+++ b/drivers/mtd/mtk-snand/mtk-snand-ecc.c\n@@ -0,0 +1,264 @@\n+// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause\n+/*\n+ * Copyright (C) 2020 MediaTek Inc. All Rights Reserved.\n+ *\n+ * Author: Weijie Gao <weijie.gao@mediatek.com>\n+ */\n+\n+#include \"mtk-snand-def.h\"\n+\n+/* ECC registers */\n+#define ECC_ENCCON\t\t\t0x000\n+#define ENC_EN\t\t\t\tBIT(0)\n+\n+#define ECC_ENCCNFG\t\t\t0x004\n+#define ENC_MS_S\t\t\t16\n+#define ENC_BURST_EN\t\t\tBIT(8)\n+#define ENC_TNUM_S\t\t\t0\n+\n+#define ECC_ENCIDLE\t\t\t0x00c\n+#define ENC_IDLE\t\t\tBIT(0)\n+\n+#define ECC_DECCON\t\t\t0x100\n+#define DEC_EN\t\t\t\tBIT(0)\n+\n+#define ECC_DECCNFG\t\t\t0x104\n+#define DEC_EMPTY_EN\t\t\tBIT(31)\n+#define DEC_CS_S\t\t\t16\n+#define DEC_CON_S\t\t\t12\n+#define   DEC_CON_CORRECT\t\t3\n+#define DEC_BURST_EN\t\t\tBIT(8)\n+#define DEC_TNUM_S\t\t\t0\n+\n+#define ECC_DECIDLE\t\t\t0x10c\n+#define DEC_IDLE\t\t\tBIT(0)\n+\n+#define ECC_DECENUM0\t\t\t0x114\n+#define ECC_DECENUM(n)\t\t\t(ECC_DECENUM0 + (n) * 4)\n+\n+/* ECC_ENCIDLE & ECC_DECIDLE */\n+#define ECC_IDLE\t\t\tBIT(0)\n+\n+/* ENC_MODE & DEC_MODE */\n+#define ECC_MODE_NFI\t\t\t1\n+\n+#define ECC_TIMEOUT\t\t\t500000\n+\n+static const uint8_t mt7622_ecc_caps[] = { 4, 6, 8, 10, 12 };\n+\n+static const uint8_t mt7986_ecc_caps[] = {\n+\t4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24\n+};\n+\n+static const uint32_t mt7622_ecc_regs[] = {\n+\t[ECC_DECDONE] = 0x11c,\n+};\n+\n+static const uint32_t mt7986_ecc_regs[] = {\n+\t[ECC_DECDONE] = 0x124,\n+};\n+\n+static const struct mtk_ecc_soc_data mtk_ecc_socs[__SNAND_SOC_MAX] = {\n+\t[SNAND_SOC_MT7622] = {\n+\t\t.ecc_caps = mt7622_ecc_caps,\n+\t\t.num_ecc_cap = ARRAY_SIZE(mt7622_ecc_caps),\n+\t\t.regs = mt7622_ecc_regs,\n+\t\t.mode_shift = 4,\n+\t\t.errnum_bits = 5,\n+\t\t.errnum_shift = 5,\n+\t},\n+\t[SNAND_SOC_MT7629] = {\n+\t\t.ecc_caps = mt7622_ecc_caps,\n+\t\t.num_ecc_cap = ARRAY_SIZE(mt7622_ecc_caps),\n+\t\t.regs = mt7622_ecc_regs,\n+\t\t.mode_shift = 4,\n+\t\t.errnum_bits = 5,\n+\t\t.errnum_shift = 5,\n+\t},\n+\t[SNAND_SOC_MT7986] = {\n+\t\t.ecc_caps = mt7986_ecc_caps,\n+\t\t.num_ecc_cap = ARRAY_SIZE(mt7986_ecc_caps),\n+\t\t.regs = mt7986_ecc_regs,\n+\t\t.mode_shift = 5,\n+\t\t.errnum_bits = 5,\n+\t\t.errnum_shift = 8,\n+\t},\n+};\n+\n+static inline uint32_t ecc_read32(struct mtk_snand *snf, uint32_t reg)\n+{\n+\treturn readl(snf->ecc_base + reg);\n+}\n+\n+static inline void ecc_write32(struct mtk_snand *snf, uint32_t reg,\n+\t\t\t       uint32_t val)\n+{\n+\twritel(val, snf->ecc_base + reg);\n+}\n+\n+static inline void ecc_write16(struct mtk_snand *snf, uint32_t reg,\n+\t\t\t       uint16_t val)\n+{\n+\twritew(val, snf->ecc_base + reg);\n+}\n+\n+static int mtk_ecc_poll(struct mtk_snand *snf, uint32_t reg, uint32_t bits)\n+{\n+\tuint32_t val;\n+\n+\treturn read16_poll_timeout(snf->ecc_base + reg, val, (val & bits), 0,\n+\t\t\t\t   ECC_TIMEOUT);\n+}\n+\n+static int mtk_ecc_wait_idle(struct mtk_snand *snf, uint32_t reg)\n+{\n+\tint ret;\n+\n+\tret = mtk_ecc_poll(snf, reg, ECC_IDLE);\n+\tif (ret) {\n+\t\tsnand_log_ecc(snf->pdev, \"ECC engine is busy\\n\");\n+\t\treturn -EBUSY;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+int mtk_ecc_setup(struct mtk_snand *snf, void *fmdaddr, uint32_t max_ecc_bytes,\n+\t\t  uint32_t msg_size)\n+{\n+\tuint32_t i, val, ecc_msg_bits, ecc_strength;\n+\tint ret;\n+\n+\tsnf->ecc_soc = &mtk_ecc_socs[snf->soc];\n+\n+\tsnf->ecc_parity_bits = fls(1 + 8 * msg_size);\n+\tecc_strength = max_ecc_bytes * 8 / snf->ecc_parity_bits;\n+\n+\tfor (i = snf->ecc_soc->num_ecc_cap - 1; i >= 0; i--) {\n+\t\tif (snf->ecc_soc->ecc_caps[i] <= ecc_strength)\n+\t\t\tbreak;\n+\t}\n+\n+\tif (unlikely(i < 0)) {\n+\t\tsnand_log_ecc(snf->pdev, \"Page size %u+%u is not supported\\n\",\n+\t\t\t      snf->writesize, snf->oobsize);\n+\t\treturn -ENOTSUPP;\n+\t}\n+\n+\tsnf->ecc_strength = snf->ecc_soc->ecc_caps[i];\n+\tsnf->ecc_bytes = DIV_ROUND_UP(snf->ecc_strength * snf->ecc_parity_bits,\n+\t\t\t\t      8);\n+\n+\t/* Encoder config */\n+\tecc_write16(snf, ECC_ENCCON, 0);\n+\tret = mtk_ecc_wait_idle(snf, ECC_ENCIDLE);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tecc_msg_bits = msg_size * 8;\n+\tval = (ecc_msg_bits << ENC_MS_S) |\n+\t      (ECC_MODE_NFI << snf->ecc_soc->mode_shift) | i;\n+\tecc_write32(snf, ECC_ENCCNFG, val);\n+\n+\t/* Decoder config */\n+\tecc_write16(snf, ECC_DECCON, 0);\n+\tret = mtk_ecc_wait_idle(snf, ECC_DECIDLE);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tecc_msg_bits += snf->ecc_strength * snf->ecc_parity_bits;\n+\tval = DEC_EMPTY_EN | (ecc_msg_bits << DEC_CS_S) |\n+\t      (DEC_CON_CORRECT << DEC_CON_S) |\n+\t      (ECC_MODE_NFI << snf->ecc_soc->mode_shift) | i;\n+\tecc_write32(snf, ECC_DECCNFG, val);\n+\n+\treturn 0;\n+}\n+\n+int mtk_snand_ecc_encoder_start(struct mtk_snand *snf)\n+{\n+\tint ret;\n+\n+\tret = mtk_ecc_wait_idle(snf, ECC_ENCIDLE);\n+\tif (ret) {\n+\t\tecc_write16(snf, ECC_ENCCON, 0);\n+\t\tmtk_ecc_wait_idle(snf, ECC_ENCIDLE);\n+\t}\n+\n+\tecc_write16(snf, ECC_ENCCON, ENC_EN);\n+\n+\treturn 0;\n+}\n+\n+void mtk_snand_ecc_encoder_stop(struct mtk_snand *snf)\n+{\n+\tmtk_ecc_wait_idle(snf, ECC_ENCIDLE);\n+\tecc_write16(snf, ECC_ENCCON, 0);\n+}\n+\n+int mtk_snand_ecc_decoder_start(struct mtk_snand *snf)\n+{\n+\tint ret;\n+\n+\tret = mtk_ecc_wait_idle(snf, ECC_DECIDLE);\n+\tif (ret) {\n+\t\tecc_write16(snf, ECC_DECCON, 0);\n+\t\tmtk_ecc_wait_idle(snf, ECC_DECIDLE);\n+\t}\n+\n+\tecc_write16(snf, ECC_DECCON, DEC_EN);\n+\n+\treturn 0;\n+}\n+\n+void mtk_snand_ecc_decoder_stop(struct mtk_snand *snf)\n+{\n+\tmtk_ecc_wait_idle(snf, ECC_DECIDLE);\n+\tecc_write16(snf, ECC_DECCON, 0);\n+}\n+\n+int mtk_ecc_wait_decoder_done(struct mtk_snand *snf)\n+{\n+\tuint16_t val, step_mask = (1 << snf->ecc_steps) - 1;\n+\tuint32_t reg = snf->ecc_soc->regs[ECC_DECDONE];\n+\tint ret;\n+\n+\tret = read16_poll_timeout(snf->ecc_base + reg, val,\n+\t\t\t\t  (val & step_mask) == step_mask, 0,\n+\t\t\t\t  ECC_TIMEOUT);\n+\tif (ret)\n+\t\tsnand_log_ecc(snf->pdev, \"ECC decoder is busy\\n\");\n+\n+\treturn ret;\n+}\n+\n+int mtk_ecc_check_decode_error(struct mtk_snand *snf, uint32_t page)\n+{\n+\tuint32_t i, regi, fi, errnum;\n+\tuint32_t errnum_shift = snf->ecc_soc->errnum_shift;\n+\tuint32_t errnum_mask = (1 << snf->ecc_soc->errnum_bits) - 1;\n+\tint ret = 0;\n+\n+\tfor (i = 0; i < snf->ecc_steps; i++) {\n+\t\tregi = i / 4;\n+\t\tfi = i % 4;\n+\n+\t\terrnum = ecc_read32(snf, ECC_DECENUM(regi));\n+\t\terrnum = (errnum >> (fi * errnum_shift)) & errnum_mask;\n+\t\tif (!errnum)\n+\t\t\tcontinue;\n+\n+\t\tif (errnum <= snf->ecc_strength) {\n+\t\t\tif (ret >= 0)\n+\t\t\t\tret += errnum;\n+\t\t\tcontinue;\n+\t\t}\n+\n+\t\tsnand_log_ecc(snf->pdev,\n+\t\t\t      \"Uncorrectable bitflips in page %u sect %u\\n\",\n+\t\t\t      page, i);\n+\t\tret = -EBADMSG;\n+\t}\n+\n+\treturn ret;\n+}\n--- /dev/null\n+++ b/drivers/mtd/mtk-snand/mtk-snand-ids.c\n@@ -0,0 +1,511 @@\n+// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause\n+/*\n+ * Copyright (C) 2020 MediaTek Inc. All Rights Reserved.\n+ *\n+ * Author: Weijie Gao <weijie.gao@mediatek.com>\n+ */\n+\n+#include \"mtk-snand-def.h\"\n+\n+static int mtk_snand_winbond_select_die(struct mtk_snand *snf, uint32_t dieidx);\n+static int mtk_snand_micron_select_die(struct mtk_snand *snf, uint32_t dieidx);\n+\n+#define SNAND_MEMORG_512M_2K_64\t\tSNAND_MEMORG(2048, 64, 64, 512, 1, 1)\n+#define SNAND_MEMORG_1G_2K_64\t\tSNAND_MEMORG(2048, 64, 64, 1024, 1, 1)\n+#define SNAND_MEMORG_2G_2K_64\t\tSNAND_MEMORG(2048, 64, 64, 2048, 1, 1)\n+#define SNAND_MEMORG_2G_2K_120\t\tSNAND_MEMORG(2048, 120, 64, 2048, 1, 1)\n+#define SNAND_MEMORG_4G_2K_64\t\tSNAND_MEMORG(2048, 64, 64, 4096, 1, 1)\n+#define SNAND_MEMORG_1G_2K_120\t\tSNAND_MEMORG(2048, 120, 64, 1024, 1, 1)\n+#define SNAND_MEMORG_1G_2K_128\t\tSNAND_MEMORG(2048, 128, 64, 1024, 1, 1)\n+#define SNAND_MEMORG_2G_2K_128\t\tSNAND_MEMORG(2048, 128, 64, 2048, 1, 1)\n+#define SNAND_MEMORG_4G_2K_128\t\tSNAND_MEMORG(2048, 128, 64, 4096, 1, 1)\n+#define SNAND_MEMORG_4G_4K_240\t\tSNAND_MEMORG(4096, 240, 64, 2048, 1, 1)\n+#define SNAND_MEMORG_4G_4K_256\t\tSNAND_MEMORG(4096, 256, 64, 2048, 1, 1)\n+#define SNAND_MEMORG_8G_4K_256\t\tSNAND_MEMORG(4096, 256, 64, 4096, 1, 1)\n+#define SNAND_MEMORG_2G_2K_64_2P\tSNAND_MEMORG(2048, 64, 64, 2048, 2, 1)\n+#define SNAND_MEMORG_2G_2K_64_2D\tSNAND_MEMORG(2048, 64, 64, 1024, 1, 2)\n+#define SNAND_MEMORG_2G_2K_128_2P\tSNAND_MEMORG(2048, 128, 64, 2048, 2, 1)\n+#define SNAND_MEMORG_4G_2K_64_2P\tSNAND_MEMORG(2048, 64, 64, 4096, 2, 1)\n+#define SNAND_MEMORG_4G_2K_128_2P_2D\tSNAND_MEMORG(2048, 128, 64, 2048, 2, 2)\n+#define SNAND_MEMORG_8G_4K_256_2D\tSNAND_MEMORG(4096, 256, 64, 2048, 1, 2)\n+\n+static const SNAND_IO_CAP(snand_cap_read_from_cache_quad,\n+\tSPI_IO_1_1_1 | SPI_IO_1_1_2 | SPI_IO_1_2_2 | SPI_IO_1_1_4 |\n+\tSPI_IO_1_4_4,\n+\tSNAND_OP(SNAND_IO_1_1_1, SNAND_CMD_READ_FROM_CACHE, 8),\n+\tSNAND_OP(SNAND_IO_1_1_2, SNAND_CMD_READ_FROM_CACHE_X2, 8),\n+\tSNAND_OP(SNAND_IO_1_2_2, SNAND_CMD_READ_FROM_CACHE_DUAL, 4),\n+\tSNAND_OP(SNAND_IO_1_1_4, SNAND_CMD_READ_FROM_CACHE_X4, 8),\n+\tSNAND_OP(SNAND_IO_1_4_4, SNAND_CMD_READ_FROM_CACHE_QUAD, 4));\n+\n+static const SNAND_IO_CAP(snand_cap_read_from_cache_quad_q2d,\n+\tSPI_IO_1_1_1 | SPI_IO_1_1_2 | SPI_IO_1_2_2 | SPI_IO_1_1_4 |\n+\tSPI_IO_1_4_4,\n+\tSNAND_OP(SNAND_IO_1_1_1, SNAND_CMD_READ_FROM_CACHE, 8),\n+\tSNAND_OP(SNAND_IO_1_1_2, SNAND_CMD_READ_FROM_CACHE_X2, 8),\n+\tSNAND_OP(SNAND_IO_1_2_2, SNAND_CMD_READ_FROM_CACHE_DUAL, 4),\n+\tSNAND_OP(SNAND_IO_1_1_4, SNAND_CMD_READ_FROM_CACHE_X4, 8),\n+\tSNAND_OP(SNAND_IO_1_4_4, SNAND_CMD_READ_FROM_CACHE_QUAD, 2));\n+\n+static const SNAND_IO_CAP(snand_cap_read_from_cache_quad_a8d,\n+\tSPI_IO_1_1_1 | SPI_IO_1_1_2 | SPI_IO_1_2_2 | SPI_IO_1_1_4 |\n+\tSPI_IO_1_4_4,\n+\tSNAND_OP(SNAND_IO_1_1_1, SNAND_CMD_READ_FROM_CACHE, 8),\n+\tSNAND_OP(SNAND_IO_1_1_2, SNAND_CMD_READ_FROM_CACHE_X2, 8),\n+\tSNAND_OP(SNAND_IO_1_2_2, SNAND_CMD_READ_FROM_CACHE_DUAL, 8),\n+\tSNAND_OP(SNAND_IO_1_1_4, SNAND_CMD_READ_FROM_CACHE_X4, 8),\n+\tSNAND_OP(SNAND_IO_1_4_4, SNAND_CMD_READ_FROM_CACHE_QUAD, 8));\n+\n+static const SNAND_IO_CAP(snand_cap_read_from_cache_x4,\n+\tSPI_IO_1_1_1 | SPI_IO_1_1_2 | SPI_IO_1_1_4,\n+\tSNAND_OP(SNAND_IO_1_1_1, SNAND_CMD_READ_FROM_CACHE, 8),\n+\tSNAND_OP(SNAND_IO_1_1_2, SNAND_CMD_READ_FROM_CACHE_X2, 8),\n+\tSNAND_OP(SNAND_IO_1_1_4, SNAND_CMD_READ_FROM_CACHE_X4, 8));\n+\n+static const SNAND_IO_CAP(snand_cap_read_from_cache_x4_only,\n+\tSPI_IO_1_1_1 | SPI_IO_1_1_4,\n+\tSNAND_OP(SNAND_IO_1_1_1, SNAND_CMD_READ_FROM_CACHE, 8),\n+\tSNAND_OP(SNAND_IO_1_1_4, SNAND_CMD_READ_FROM_CACHE_X4, 8));\n+\n+static const SNAND_IO_CAP(snand_cap_program_load_x1,\n+\tSPI_IO_1_1_1,\n+\tSNAND_OP(SNAND_IO_1_1_1, SNAND_CMD_PROGRAM_LOAD, 0));\n+\n+static const SNAND_IO_CAP(snand_cap_program_load_x4,\n+\tSPI_IO_1_1_1 | SPI_IO_1_1_4,\n+\tSNAND_OP(SNAND_IO_1_1_1, SNAND_CMD_PROGRAM_LOAD, 0),\n+\tSNAND_OP(SNAND_IO_1_1_4, SNAND_CMD_PROGRAM_LOAD_X4, 0));\n+\n+static const struct snand_flash_info snand_flash_ids[] = {\n+\tSNAND_INFO(\"W25N512GV\", SNAND_ID(SNAND_ID_DYMMY, 0xef, 0xaa, 0x20),\n+\t\t   SNAND_MEMORG_512M_2K_64,\n+\t\t   &snand_cap_read_from_cache_quad,\n+\t\t   &snand_cap_program_load_x4),\n+\tSNAND_INFO(\"W25N01GV\", SNAND_ID(SNAND_ID_DYMMY, 0xef, 0xaa, 0x21),\n+\t\t   SNAND_MEMORG_1G_2K_64,\n+\t\t   &snand_cap_read_from_cache_quad,\n+\t\t   &snand_cap_program_load_x4),\n+\tSNAND_INFO(\"W25M02GV\", SNAND_ID(SNAND_ID_DYMMY, 0xef, 0xab, 0x21),\n+\t\t   SNAND_MEMORG_2G_2K_64_2D,\n+\t\t   &snand_cap_read_from_cache_quad,\n+\t\t   &snand_cap_program_load_x4,\n+\t\t   mtk_snand_winbond_select_die),\n+\tSNAND_INFO(\"W25N02KV\", SNAND_ID(SNAND_ID_DYMMY, 0xef, 0xaa, 0x22),\n+\t\t   SNAND_MEMORG_2G_2K_128,\n+\t\t   &snand_cap_read_from_cache_quad,\n+\t\t   &snand_cap_program_load_x4),\n+\n+\tSNAND_INFO(\"GD5F1GQ4UAWxx\", SNAND_ID(SNAND_ID_ADDR, 0xc8, 0x10),\n+\t\t   SNAND_MEMORG_1G_2K_64,\n+\t\t   &snand_cap_read_from_cache_quad_q2d,\n+\t\t   &snand_cap_program_load_x4),\n+\tSNAND_INFO(\"GD5F1GQ4UExIG\", SNAND_ID(SNAND_ID_ADDR, 0xc8, 0xd1),\n+\t\t   SNAND_MEMORG_1G_2K_128,\n+\t\t   &snand_cap_read_from_cache_quad_q2d,\n+\t\t   &snand_cap_program_load_x4),\n+\tSNAND_INFO(\"GD5F1GQ4UExxH\", SNAND_ID(SNAND_ID_ADDR, 0xc8, 0xd9),\n+\t\t   SNAND_MEMORG_1G_2K_64,\n+\t\t   &snand_cap_read_from_cache_quad_q2d,\n+\t\t   &snand_cap_program_load_x4),\n+\tSNAND_INFO(\"GD5F1GQ4xAYIG\", SNAND_ID(SNAND_ID_ADDR, 0xc8, 0xf1),\n+\t\t   SNAND_MEMORG_1G_2K_64,\n+\t\t   &snand_cap_read_from_cache_quad_q2d,\n+\t\t   &snand_cap_program_load_x4),\n+\tSNAND_INFO(\"GD5F2GQ4UExIG\", SNAND_ID(SNAND_ID_ADDR, 0xc8, 0xd2),\n+\t\t   SNAND_MEMORG_2G_2K_128,\n+\t\t   &snand_cap_read_from_cache_quad_q2d,\n+\t\t   &snand_cap_program_load_x4),\n+\tSNAND_INFO(\"GD5F2GQ5UExxH\", SNAND_ID(SNAND_ID_ADDR, 0xc8, 0x32),\n+\t\t   SNAND_MEMORG_2G_2K_64,\n+\t\t   &snand_cap_read_from_cache_quad_a8d,\n+\t\t   &snand_cap_program_load_x4),\n+\tSNAND_INFO(\"GD5F2GQ4xAYIG\", SNAND_ID(SNAND_ID_ADDR, 0xc8, 0xf2),\n+\t\t   SNAND_MEMORG_2G_2K_64,\n+\t\t   &snand_cap_read_from_cache_quad_q2d,\n+\t\t   &snand_cap_program_load_x4),\n+\tSNAND_INFO(\"GD5F4GQ4UBxIG\", SNAND_ID(SNAND_ID_ADDR, 0xc8, 0xd4),\n+\t\t   SNAND_MEMORG_4G_4K_256,\n+\t\t   &snand_cap_read_from_cache_quad_q2d,\n+\t\t   &snand_cap_program_load_x4),\n+\tSNAND_INFO(\"GD5F4GQ4xAYIG\", SNAND_ID(SNAND_ID_ADDR, 0xc8, 0xf4),\n+\t\t   SNAND_MEMORG_4G_2K_64,\n+\t\t   &snand_cap_read_from_cache_quad_q2d,\n+\t\t   &snand_cap_program_load_x4),\n+\tSNAND_INFO(\"GD5F2GQ5UExxG\", SNAND_ID(SNAND_ID_DYMMY, 0xc8, 0x52),\n+\t\t   SNAND_MEMORG_2G_2K_128,\n+\t\t   &snand_cap_read_from_cache_quad_q2d,\n+\t\t   &snand_cap_program_load_x4),\n+\tSNAND_INFO(\"GD5F4GQ4UCxIG\", SNAND_ID(SNAND_ID_DYMMY, 0xc8, 0xb4),\n+\t\t   SNAND_MEMORG_4G_4K_256,\n+\t\t   &snand_cap_read_from_cache_quad_q2d,\n+\t\t   &snand_cap_program_load_x4),\n+\n+\tSNAND_INFO(\"MX35LF1GE4AB\", SNAND_ID(SNAND_ID_DYMMY, 0xc2, 0x12),\n+\t\t   SNAND_MEMORG_1G_2K_64,\n+\t\t   &snand_cap_read_from_cache_x4,\n+\t\t   &snand_cap_program_load_x4),\n+\tSNAND_INFO(\"MX35LF1G24AD\", SNAND_ID(SNAND_ID_DYMMY, 0xc2, 0x14),\n+\t\t   SNAND_MEMORG_1G_2K_128,\n+\t\t   &snand_cap_read_from_cache_quad,\n+\t\t   &snand_cap_program_load_x4),\n+\tSNAND_INFO(\"MX31LF1GE4BC\", SNAND_ID(SNAND_ID_DYMMY, 0xc2, 0x1e),\n+\t\t   SNAND_MEMORG_1G_2K_64,\n+\t\t   &snand_cap_read_from_cache_x4,\n+\t\t   &snand_cap_program_load_x4),\n+\tSNAND_INFO(\"MX35LF2GE4AB\", SNAND_ID(SNAND_ID_DYMMY, 0xc2, 0x22),\n+\t\t   SNAND_MEMORG_2G_2K_64,\n+\t\t   &snand_cap_read_from_cache_x4,\n+\t\t   &snand_cap_program_load_x4),\n+\tSNAND_INFO(\"MX35LF2G24AD\", SNAND_ID(SNAND_ID_DYMMY, 0xc2, 0x24),\n+\t\t   SNAND_MEMORG_2G_2K_128,\n+\t\t   &snand_cap_read_from_cache_quad,\n+\t\t   &snand_cap_program_load_x4),\n+\tSNAND_INFO(\"MX35LF2GE4AD\", SNAND_ID(SNAND_ID_DYMMY, 0xc2, 0x26),\n+\t\t   SNAND_MEMORG_2G_2K_128,\n+\t\t   &snand_cap_read_from_cache_x4,\n+\t\t   &snand_cap_program_load_x4),\n+\tSNAND_INFO(\"MX35LF2G14AC\", SNAND_ID(SNAND_ID_DYMMY, 0xc2, 0x20),\n+\t\t   SNAND_MEMORG_2G_2K_64,\n+\t\t   &snand_cap_read_from_cache_x4,\n+\t\t   &snand_cap_program_load_x4),\n+\tSNAND_INFO(\"MX35LF4G24AD\", SNAND_ID(SNAND_ID_DYMMY, 0xc2, 0x35),\n+\t\t   SNAND_MEMORG_4G_4K_256,\n+\t\t   &snand_cap_read_from_cache_quad,\n+\t\t   &snand_cap_program_load_x4),\n+\tSNAND_INFO(\"MX35LF4GE4AD\", SNAND_ID(SNAND_ID_DYMMY, 0xc2, 0x37),\n+\t\t   SNAND_MEMORG_4G_4K_256,\n+\t\t   &snand_cap_read_from_cache_x4,\n+\t\t   &snand_cap_program_load_x4),\n+\n+\tSNAND_INFO(\"MT29F1G01AAADD\", SNAND_ID(SNAND_ID_DYMMY, 0x2c, 0x12),\n+\t\t   SNAND_MEMORG_1G_2K_64,\n+\t\t   &snand_cap_read_from_cache_x4,\n+\t\t   &snand_cap_program_load_x1),\n+\tSNAND_INFO(\"MT29F1G01ABAFD\", SNAND_ID(SNAND_ID_DYMMY, 0x2c, 0x14),\n+\t\t   SNAND_MEMORG_1G_2K_128,\n+\t\t   &snand_cap_read_from_cache_quad,\n+\t\t   &snand_cap_program_load_x4),\n+\tSNAND_INFO(\"MT29F2G01AAAED\", SNAND_ID(SNAND_ID_DYMMY, 0x2c, 0x9f),\n+\t\t   SNAND_MEMORG_2G_2K_64_2P,\n+\t\t   &snand_cap_read_from_cache_x4,\n+\t\t   &snand_cap_program_load_x1),\n+\tSNAND_INFO(\"MT29F2G01ABAGD\", SNAND_ID(SNAND_ID_DYMMY, 0x2c, 0x24),\n+\t\t   SNAND_MEMORG_2G_2K_128_2P,\n+\t\t   &snand_cap_read_from_cache_quad,\n+\t\t   &snand_cap_program_load_x4),\n+\tSNAND_INFO(\"MT29F4G01AAADD\", SNAND_ID(SNAND_ID_DYMMY, 0x2c, 0x32),\n+\t\t   SNAND_MEMORG_4G_2K_64_2P,\n+\t\t   &snand_cap_read_from_cache_x4,\n+\t\t   &snand_cap_program_load_x1),\n+\tSNAND_INFO(\"MT29F4G01ABAFD\", SNAND_ID(SNAND_ID_DYMMY, 0x2c, 0x34),\n+\t\t   SNAND_MEMORG_4G_4K_256,\n+\t\t   &snand_cap_read_from_cache_quad,\n+\t\t   &snand_cap_program_load_x4),\n+\tSNAND_INFO(\"MT29F4G01ADAGD\", SNAND_ID(SNAND_ID_DYMMY, 0x2c, 0x36),\n+\t\t   SNAND_MEMORG_4G_2K_128_2P_2D,\n+\t\t   &snand_cap_read_from_cache_quad,\n+\t\t   &snand_cap_program_load_x4,\n+\t\t   mtk_snand_micron_select_die),\n+\tSNAND_INFO(\"MT29F8G01ADAFD\", SNAND_ID(SNAND_ID_DYMMY, 0x2c, 0x46),\n+\t\t   SNAND_MEMORG_8G_4K_256_2D,\n+\t\t   &snand_cap_read_from_cache_quad,\n+\t\t   &snand_cap_program_load_x4,\n+\t\t   mtk_snand_micron_select_die),\n+\n+\tSNAND_INFO(\"TC58CVG0S3HRAIG\", SNAND_ID(SNAND_ID_DYMMY, 0x98, 0xc2),\n+\t\t   SNAND_MEMORG_1G_2K_128,\n+\t\t   &snand_cap_read_from_cache_x4,\n+\t\t   &snand_cap_program_load_x1),\n+\tSNAND_INFO(\"TC58CVG1S3HRAIG\", SNAND_ID(SNAND_ID_DYMMY, 0x98, 0xcb),\n+\t\t   SNAND_MEMORG_2G_2K_128,\n+\t\t   &snand_cap_read_from_cache_x4,\n+\t\t   &snand_cap_program_load_x1),\n+\tSNAND_INFO(\"TC58CVG2S0HRAIG\", SNAND_ID(SNAND_ID_DYMMY, 0x98, 0xcd),\n+\t\t   SNAND_MEMORG_4G_4K_256,\n+\t\t   &snand_cap_read_from_cache_x4,\n+\t\t   &snand_cap_program_load_x1),\n+\tSNAND_INFO(\"TC58CVG0S3HRAIJ\", SNAND_ID(SNAND_ID_DYMMY, 0x98, 0xe2),\n+\t\t   SNAND_MEMORG_1G_2K_128,\n+\t\t   &snand_cap_read_from_cache_x4,\n+\t\t   &snand_cap_program_load_x4),\n+\tSNAND_INFO(\"TC58CVG1S3HRAIJ\", SNAND_ID(SNAND_ID_DYMMY, 0x98, 0xeb),\n+\t\t   SNAND_MEMORG_2G_2K_128,\n+\t\t   &snand_cap_read_from_cache_x4,\n+\t\t   &snand_cap_program_load_x4),\n+\tSNAND_INFO(\"TC58CVG2S0HRAIJ\", SNAND_ID(SNAND_ID_DYMMY, 0x98, 0xed),\n+\t\t   SNAND_MEMORG_4G_4K_256,\n+\t\t   &snand_cap_read_from_cache_x4,\n+\t\t   &snand_cap_program_load_x4),\n+\tSNAND_INFO(\"TH58CVG3S0HRAIJ\", SNAND_ID(SNAND_ID_DYMMY, 0x98, 0xe4),\n+\t\t   SNAND_MEMORG_8G_4K_256,\n+\t\t   &snand_cap_read_from_cache_x4,\n+\t\t   &snand_cap_program_load_x4),\n+\n+\tSNAND_INFO(\"F50L512M41A\", SNAND_ID(SNAND_ID_DYMMY, 0xc8, 0x20),\n+\t\t   SNAND_MEMORG_512M_2K_64,\n+\t\t   &snand_cap_read_from_cache_x4,\n+\t\t   &snand_cap_program_load_x4),\n+\tSNAND_INFO(\"F50L1G41A\", SNAND_ID(SNAND_ID_DYMMY, 0xc8, 0x21),\n+\t\t   SNAND_MEMORG_1G_2K_64,\n+\t\t   &snand_cap_read_from_cache_x4,\n+\t\t   &snand_cap_program_load_x4),\n+\tSNAND_INFO(\"F50L1G41LB\", SNAND_ID(SNAND_ID_DYMMY, 0xc8, 0x01),\n+\t\t   SNAND_MEMORG_1G_2K_64,\n+\t\t   &snand_cap_read_from_cache_quad,\n+\t\t   &snand_cap_program_load_x4),\n+\tSNAND_INFO(\"F50L2G41LB\", SNAND_ID(SNAND_ID_DYMMY, 0xc8, 0x0a),\n+\t\t   SNAND_MEMORG_2G_2K_64_2D,\n+\t\t   &snand_cap_read_from_cache_quad,\n+\t\t   &snand_cap_program_load_x4,\n+\t\t   mtk_snand_winbond_select_die),\n+\n+\tSNAND_INFO(\"CS11G0T0A0AA\", SNAND_ID(SNAND_ID_DYMMY, 0x6b, 0x00),\n+\t\t   SNAND_MEMORG_1G_2K_128,\n+\t\t   &snand_cap_read_from_cache_quad_q2d,\n+\t\t   &snand_cap_program_load_x4),\n+\tSNAND_INFO(\"CS11G0G0A0AA\", SNAND_ID(SNAND_ID_DYMMY, 0x6b, 0x10),\n+\t\t   SNAND_MEMORG_1G_2K_128,\n+\t\t   &snand_cap_read_from_cache_quad_q2d,\n+\t\t   &snand_cap_program_load_x4),\n+\tSNAND_INFO(\"CS11G0S0A0AA\", SNAND_ID(SNAND_ID_DYMMY, 0x6b, 0x20),\n+\t\t   SNAND_MEMORG_1G_2K_64,\n+\t\t   &snand_cap_read_from_cache_quad_q2d,\n+\t\t   &snand_cap_program_load_x4),\n+\tSNAND_INFO(\"CS11G1T0A0AA\", SNAND_ID(SNAND_ID_DYMMY, 0x6b, 0x01),\n+\t\t   SNAND_MEMORG_2G_2K_128,\n+\t\t   &snand_cap_read_from_cache_quad_q2d,\n+\t\t   &snand_cap_program_load_x4),\n+\tSNAND_INFO(\"CS11G1S0A0AA\", SNAND_ID(SNAND_ID_DYMMY, 0x6b, 0x21),\n+\t\t   SNAND_MEMORG_2G_2K_64,\n+\t\t   &snand_cap_read_from_cache_quad_q2d,\n+\t\t   &snand_cap_program_load_x4),\n+\tSNAND_INFO(\"CS11G2T0A0AA\", SNAND_ID(SNAND_ID_DYMMY, 0x6b, 0x02),\n+\t\t   SNAND_MEMORG_4G_2K_128,\n+\t\t   &snand_cap_read_from_cache_quad_q2d,\n+\t\t   &snand_cap_program_load_x4),\n+\tSNAND_INFO(\"CS11G2S0A0AA\", SNAND_ID(SNAND_ID_DYMMY, 0x6b, 0x22),\n+\t\t   SNAND_MEMORG_4G_2K_64,\n+\t\t   &snand_cap_read_from_cache_quad_q2d,\n+\t\t   &snand_cap_program_load_x4),\n+\n+\tSNAND_INFO(\"EM73B044VCA\", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x01),\n+\t\t   SNAND_MEMORG_512M_2K_64,\n+\t\t   &snand_cap_read_from_cache_quad_q2d,\n+\t\t   &snand_cap_program_load_x4),\n+\tSNAND_INFO(\"EM73C044SNB\", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x11),\n+\t\t   SNAND_MEMORG_1G_2K_120,\n+\t\t   &snand_cap_read_from_cache_quad_q2d,\n+\t\t   &snand_cap_program_load_x4),\n+\tSNAND_INFO(\"EM73C044SNF\", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x09),\n+\t\t   SNAND_MEMORG_1G_2K_128,\n+\t\t   &snand_cap_read_from_cache_quad_q2d,\n+\t\t   &snand_cap_program_load_x4),\n+\tSNAND_INFO(\"EM73C044VCA\", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x18),\n+\t\t   SNAND_MEMORG_1G_2K_64,\n+\t\t   &snand_cap_read_from_cache_quad_q2d,\n+\t\t   &snand_cap_program_load_x4),\n+\tSNAND_INFO(\"EM73C044SNA\", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x19),\n+\t\t   SNAND_MEMORG(2048, 64, 128, 512, 1, 1),\n+\t\t   &snand_cap_read_from_cache_quad_q2d,\n+\t\t   &snand_cap_program_load_x4),\n+\tSNAND_INFO(\"EM73C044VCD\", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x1c),\n+\t\t   SNAND_MEMORG_1G_2K_64,\n+\t\t   &snand_cap_read_from_cache_quad_q2d,\n+\t\t   &snand_cap_program_load_x4),\n+\tSNAND_INFO(\"EM73C044SND\", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x1d),\n+\t\t   SNAND_MEMORG_1G_2K_64,\n+\t\t   &snand_cap_read_from_cache_quad_q2d,\n+\t\t   &snand_cap_program_load_x4),\n+\tSNAND_INFO(\"EM73D044SND\", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x1e),\n+\t\t   SNAND_MEMORG_2G_2K_64,\n+\t\t   &snand_cap_read_from_cache_quad_q2d,\n+\t\t   &snand_cap_program_load_x4),\n+\tSNAND_INFO(\"EM73C044VCC\", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x22),\n+\t\t   SNAND_MEMORG_1G_2K_64,\n+\t\t   &snand_cap_read_from_cache_quad_q2d,\n+\t\t   &snand_cap_program_load_x4),\n+\tSNAND_INFO(\"EM73C044VCF\", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x25),\n+\t\t   SNAND_MEMORG_1G_2K_64,\n+\t\t   &snand_cap_read_from_cache_quad_q2d,\n+\t\t   &snand_cap_program_load_x4),\n+\tSNAND_INFO(\"EM73C044SNC\", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x31),\n+\t\t   SNAND_MEMORG_1G_2K_128,\n+\t\t   &snand_cap_read_from_cache_quad_q2d,\n+\t\t   &snand_cap_program_load_x4),\n+\tSNAND_INFO(\"EM73D044SNC\", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x0a),\n+\t\t   SNAND_MEMORG_2G_2K_120,\n+\t\t   &snand_cap_read_from_cache_quad_q2d,\n+\t\t   &snand_cap_program_load_x4),\n+\tSNAND_INFO(\"EM73D044SNA\", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x12),\n+\t\t   SNAND_MEMORG_2G_2K_128,\n+\t\t   &snand_cap_read_from_cache_quad_q2d,\n+\t\t   &snand_cap_program_load_x4),\n+\tSNAND_INFO(\"EM73D044SNF\", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x10),\n+\t\t   SNAND_MEMORG_2G_2K_128,\n+\t\t   &snand_cap_read_from_cache_quad_q2d,\n+\t\t   &snand_cap_program_load_x4),\n+\tSNAND_INFO(\"EM73D044VCA\", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x13),\n+\t\t   SNAND_MEMORG_2G_2K_128,\n+\t\t   &snand_cap_read_from_cache_quad_q2d,\n+\t\t   &snand_cap_program_load_x4),\n+\tSNAND_INFO(\"EM73D044VCB\", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x14),\n+\t\t   SNAND_MEMORG_2G_2K_64,\n+\t\t   &snand_cap_read_from_cache_quad_q2d,\n+\t\t   &snand_cap_program_load_x4),\n+\tSNAND_INFO(\"EM73D044VCD\", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x17),\n+\t\t   SNAND_MEMORG_2G_2K_128,\n+\t\t   &snand_cap_read_from_cache_quad_q2d,\n+\t\t   &snand_cap_program_load_x4),\n+\tSNAND_INFO(\"EM73D044VCH\", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x1b),\n+\t\t   SNAND_MEMORG_2G_2K_64,\n+\t\t   &snand_cap_read_from_cache_quad_q2d,\n+\t\t   &snand_cap_program_load_x4),\n+\tSNAND_INFO(\"EM73D044SND\", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x1d),\n+\t\t   SNAND_MEMORG_2G_2K_64,\n+\t\t   &snand_cap_read_from_cache_quad_q2d,\n+\t\t   &snand_cap_program_load_x4),\n+\tSNAND_INFO(\"EM73D044VCG\", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x1f),\n+\t\t   SNAND_MEMORG_2G_2K_64,\n+\t\t   &snand_cap_read_from_cache_quad_q2d,\n+\t\t   &snand_cap_program_load_x4),\n+\tSNAND_INFO(\"EM73D044VCE\", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x20),\n+\t\t   SNAND_MEMORG_2G_2K_64,\n+\t\t   &snand_cap_read_from_cache_quad_q2d,\n+\t\t   &snand_cap_program_load_x4),\n+\tSNAND_INFO(\"EM73D044VCL\", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x2e),\n+\t\t   SNAND_MEMORG_2G_2K_128,\n+\t\t   &snand_cap_read_from_cache_quad_q2d,\n+\t\t   &snand_cap_program_load_x4),\n+\tSNAND_INFO(\"EM73D044SNB\", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x32),\n+\t\t   SNAND_MEMORG_2G_2K_128,\n+\t\t   &snand_cap_read_from_cache_quad_q2d,\n+\t\t   &snand_cap_program_load_x4),\n+\tSNAND_INFO(\"EM73E044SNA\", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x03),\n+\t\t   SNAND_MEMORG_4G_4K_256,\n+\t\t   &snand_cap_read_from_cache_quad_q2d,\n+\t\t   &snand_cap_program_load_x4),\n+\tSNAND_INFO(\"EM73E044SND\", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x0b),\n+\t\t   SNAND_MEMORG_4G_4K_240,\n+\t\t   &snand_cap_read_from_cache_quad_q2d,\n+\t\t   &snand_cap_program_load_x4),\n+\tSNAND_INFO(\"EM73E044SNB\", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x23),\n+\t\t   SNAND_MEMORG_4G_4K_256,\n+\t\t   &snand_cap_read_from_cache_quad_q2d,\n+\t\t   &snand_cap_program_load_x4),\n+\tSNAND_INFO(\"EM73E044VCA\", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x2c),\n+\t\t   SNAND_MEMORG_4G_4K_256,\n+\t\t   &snand_cap_read_from_cache_quad_q2d,\n+\t\t   &snand_cap_program_load_x4),\n+\tSNAND_INFO(\"EM73E044VCB\", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x2f),\n+\t\t   SNAND_MEMORG_4G_2K_128,\n+\t\t   &snand_cap_read_from_cache_quad_q2d,\n+\t\t   &snand_cap_program_load_x4),\n+\tSNAND_INFO(\"EM73F044SNA\", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x24),\n+\t\t   SNAND_MEMORG_8G_4K_256,\n+\t\t   &snand_cap_read_from_cache_quad_q2d,\n+\t\t   &snand_cap_program_load_x4),\n+\tSNAND_INFO(\"EM73F044VCA\", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x2d),\n+\t\t   SNAND_MEMORG_8G_4K_256,\n+\t\t   &snand_cap_read_from_cache_quad_q2d,\n+\t\t   &snand_cap_program_load_x4),\n+\tSNAND_INFO(\"EM73E044SNE\", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x0e),\n+\t\t   SNAND_MEMORG_8G_4K_256,\n+\t\t   &snand_cap_read_from_cache_quad_q2d,\n+\t\t   &snand_cap_program_load_x4),\n+\tSNAND_INFO(\"EM73C044SNG\", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x0c),\n+\t\t   SNAND_MEMORG_1G_2K_120,\n+\t\t   &snand_cap_read_from_cache_quad_q2d,\n+\t\t   &snand_cap_program_load_x4),\n+\tSNAND_INFO(\"EM73D044VCN\", SNAND_ID(SNAND_ID_DYMMY, 0xd5, 0x0f),\n+\t\t   SNAND_MEMORG_2G_2K_64,\n+\t\t   &snand_cap_read_from_cache_quad_q2d,\n+\t\t   &snand_cap_program_load_x4),\n+\n+\tSNAND_INFO(\"FM35Q1GA\", SNAND_ID(SNAND_ID_DYMMY, 0xe5, 0x71),\n+\t\t   SNAND_MEMORG_1G_2K_64,\n+\t\t   &snand_cap_read_from_cache_x4,\n+\t\t   &snand_cap_program_load_x4),\n+\n+\tSNAND_INFO(\"PN26G01A\", SNAND_ID(SNAND_ID_DYMMY, 0xa1, 0xe1),\n+\t\t   SNAND_MEMORG_1G_2K_128,\n+\t\t   &snand_cap_read_from_cache_quad_q2d,\n+\t\t   &snand_cap_program_load_x4),\n+\tSNAND_INFO(\"PN26G02A\", SNAND_ID(SNAND_ID_DYMMY, 0xa1, 0xe2),\n+\t\t   SNAND_MEMORG_2G_2K_128,\n+\t\t   &snand_cap_read_from_cache_quad_q2d,\n+\t\t   &snand_cap_program_load_x4),\n+\n+\tSNAND_INFO(\"IS37SML01G1\", SNAND_ID(SNAND_ID_DYMMY, 0xc8, 0x21),\n+\t\t   SNAND_MEMORG_1G_2K_64,\n+\t\t   &snand_cap_read_from_cache_x4,\n+\t\t   &snand_cap_program_load_x4),\n+\n+\tSNAND_INFO(\"ATO25D1GA\", SNAND_ID(SNAND_ID_DYMMY, 0x9b, 0x12),\n+\t\t   SNAND_MEMORG_1G_2K_64,\n+\t\t   &snand_cap_read_from_cache_x4_only,\n+\t\t   &snand_cap_program_load_x4),\n+\n+\tSNAND_INFO(\"HYF1GQ4U\", SNAND_ID(SNAND_ID_DYMMY, 0xc9, 0x51),\n+\t\t   SNAND_MEMORG_1G_2K_128,\n+\t\t   &snand_cap_read_from_cache_quad_q2d,\n+\t\t   &snand_cap_program_load_x4),\n+\tSNAND_INFO(\"HYF2GQ4U\", SNAND_ID(SNAND_ID_DYMMY, 0xc9, 0x52),\n+\t\t   SNAND_MEMORG_2G_2K_128,\n+\t\t   &snand_cap_read_from_cache_quad_q2d,\n+\t\t   &snand_cap_program_load_x4),\n+};\n+\n+static int mtk_snand_winbond_select_die(struct mtk_snand *snf, uint32_t dieidx)\n+{\n+\tuint8_t op[2];\n+\n+\tif (dieidx > 1) {\n+\t\tsnand_log_chip(snf->pdev, \"Invalid die index %u\\n\", dieidx);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\top[0] = SNAND_CMD_WINBOND_SELECT_DIE;\n+\top[1] = (uint8_t)dieidx;\n+\n+\treturn mtk_snand_mac_io(snf, op, sizeof(op), NULL, 0);\n+}\n+\n+static int mtk_snand_micron_select_die(struct mtk_snand *snf, uint32_t dieidx)\n+{\n+\tint ret;\n+\n+\tif (dieidx > 1) {\n+\t\tsnand_log_chip(snf->pdev, \"Invalid die index %u\\n\", dieidx);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tret = mtk_snand_set_feature(snf, SNAND_FEATURE_MICRON_DIE_ADDR,\n+\t\t\t\t    SNAND_MICRON_DIE_SEL_1);\n+\tif (ret) {\n+\t\tsnand_log_chip(snf->pdev,\n+\t\t\t       \"Failed to set die selection feature\\n\");\n+\t\treturn ret;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+const struct snand_flash_info *snand_flash_id_lookup(enum snand_id_type type,\n+\t\t\t\t\t\t     const uint8_t *id)\n+{\n+\tconst struct snand_id *fid;\n+\tuint32_t i;\n+\n+\tfor (i = 0; i < ARRAY_SIZE(snand_flash_ids); i++) {\n+\t\tif (snand_flash_ids[i].id.type != type)\n+\t\t\tcontinue;\n+\n+\t\tfid = &snand_flash_ids[i].id;\n+\t\tif (memcmp(fid->id, id, fid->len))\n+\t\t\tcontinue;\n+\n+\t\treturn &snand_flash_ids[i];\n+\t}\n+\n+\treturn NULL;\n+}\n--- /dev/null\n+++ b/drivers/mtd/mtk-snand/mtk-snand-mtd.c\n@@ -0,0 +1,524 @@\n+// SPDX-License-Identifier: GPL-2.0\n+/*\n+ * Copyright (C) 2020 MediaTek Inc. All Rights Reserved.\n+ *\n+ * Author: Weijie Gao <weijie.gao@mediatek.com>\n+ */\n+\n+#include <common.h>\n+#include <dm.h>\n+#include <malloc.h>\n+#include <mapmem.h>\n+#include <linux/mtd/mtd.h>\n+#include <watchdog.h>\n+\n+#include \"mtk-snand.h\"\n+\n+struct mtk_snand_mtd {\n+\tstruct udevice *dev;\n+\tstruct mtk_snand *snf;\n+\tstruct mtk_snand_chip_info cinfo;\n+\tuint8_t *page_cache;\n+};\n+\n+static const char snand_mtd_name_prefix[] = \"spi-nand\";\n+\n+static u32 snandidx;\n+\n+static inline struct mtk_snand_mtd *mtd_to_msm(struct mtd_info *mtd)\n+{\n+\treturn mtd->priv;\n+}\n+\n+static int mtk_snand_mtd_erase(struct mtd_info *mtd, struct erase_info *instr)\n+{\n+\tstruct mtk_snand_mtd *msm = mtd_to_msm(mtd);\n+\tu64 start_addr, end_addr;\n+\tint ret;\n+\n+\t/* Do not allow write past end of device */\n+\tif ((instr->addr + instr->len) > mtd->size) {\n+\t\tpr_debug(\"%s: attempt to erase beyond end of device\\n\",\n+\t\t\t __func__);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tstart_addr = instr->addr & (~mtd->erasesize_mask);\n+\tend_addr = instr->addr + instr->len;\n+\tif (end_addr & mtd->erasesize_mask) {\n+\t\tend_addr = (end_addr + mtd->erasesize_mask) &\n+\t\t\t   (~mtd->erasesize_mask);\n+\t}\n+\n+\tinstr->state = MTD_ERASING;\n+\n+\twhile (start_addr < end_addr) {\n+\t\tWATCHDOG_RESET();\n+\n+\t\tif (mtk_snand_block_isbad(msm->snf, start_addr)) {\n+\t\t\tif (!instr->scrub) {\n+\t\t\t\tinstr->fail_addr = start_addr;\n+\t\t\t\tret = -EIO;\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t}\n+\n+\t\tret = mtk_snand_erase_block(msm->snf, start_addr);\n+\t\tif (ret) {\n+\t\t\tinstr->fail_addr = start_addr;\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\tstart_addr += mtd->erasesize;\n+\t}\n+\n+\tif (ret)\n+\t\tinstr->state = MTD_ERASE_FAILED;\n+\telse\n+\t\tinstr->state = MTD_ERASE_DONE;\n+\n+\tif (ret)\n+\t\tret = -EIO;\n+\n+\treturn ret;\n+}\n+\n+static int mtk_snand_mtd_read_data(struct mtk_snand_mtd *msm, uint64_t addr,\n+\t\t\t\t   struct mtd_oob_ops *ops)\n+{\n+\tstruct mtd_info *mtd = dev_get_uclass_priv(msm->dev);\n+\tsize_t len, ooblen, maxooblen, chklen;\n+\tuint32_t col, ooboffs;\n+\tuint8_t *datcache, *oobcache;\n+\tbool raw = ops->mode == MTD_OPS_RAW ? true : false;\n+\tint ret;\n+\n+\tcol = addr & mtd->writesize_mask;\n+\taddr &= ~mtd->writesize_mask;\n+\tmaxooblen = mtd_oobavail(mtd, ops);\n+\tooboffs = ops->ooboffs;\n+\tooblen = ops->ooblen;\n+\tlen = ops->len;\n+\n+\tdatcache = len ? msm->page_cache : NULL;\n+\toobcache = ooblen ? msm->page_cache + mtd->writesize : NULL;\n+\n+\tops->oobretlen = 0;\n+\tops->retlen = 0;\n+\n+\twhile (len || ooblen) {\n+\t\tWATCHDOG_RESET();\n+\n+\t\tif (ops->mode == MTD_OPS_AUTO_OOB)\n+\t\t\tret = mtk_snand_read_page_auto_oob(msm->snf, addr,\n+\t\t\t\tdatcache, oobcache, maxooblen, NULL, raw);\n+\t\telse\n+\t\t\tret = mtk_snand_read_page(msm->snf, addr, datcache,\n+\t\t\t\toobcache, raw);\n+\n+\t\tif (ret < 0)\n+\t\t\treturn ret;\n+\n+\t\tif (len) {\n+\t\t\t/* Move data */\n+\t\t\tchklen = mtd->writesize - col;\n+\t\t\tif (chklen > len)\n+\t\t\t\tchklen = len;\n+\n+\t\t\tmemcpy(ops->datbuf + ops->retlen, datcache + col,\n+\t\t\t       chklen);\n+\t\t\tlen -= chklen;\n+\t\t\tcol = 0; /* (col + chklen) %  */\n+\t\t\tops->retlen += chklen;\n+\t\t}\n+\n+\t\tif (ooblen) {\n+\t\t\t/* Move oob */\n+\t\t\tchklen = maxooblen - ooboffs;\n+\t\t\tif (chklen > ooblen)\n+\t\t\t\tchklen = ooblen;\n+\n+\t\t\tmemcpy(ops->oobbuf + ops->oobretlen, oobcache + ooboffs,\n+\t\t\t       chklen);\n+\t\t\tooblen -= chklen;\n+\t\t\tooboffs = 0; /* (ooboffs + chklen) % maxooblen; */\n+\t\t\tops->oobretlen += chklen;\n+\t\t}\n+\n+\t\taddr += mtd->writesize;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int mtk_snand_mtd_read_oob(struct mtd_info *mtd, loff_t from,\n+\t\t\t\t  struct mtd_oob_ops *ops)\n+{\n+\tstruct mtk_snand_mtd *msm = mtd_to_msm(mtd);\n+\tuint32_t maxooblen;\n+\n+\tif (!ops->oobbuf && !ops->datbuf) {\n+\t\tif (ops->ooblen || ops->len)\n+\t\t\treturn -EINVAL;\n+\n+\t\treturn 0;\n+\t}\n+\n+\tswitch (ops->mode) {\n+\tcase MTD_OPS_PLACE_OOB:\n+\tcase MTD_OPS_AUTO_OOB:\n+\tcase MTD_OPS_RAW:\n+\t\tbreak;\n+\tdefault:\n+\t\tpr_debug(\"%s: unsupported oob mode: %u\\n\", __func__, ops->mode);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tmaxooblen = mtd_oobavail(mtd, ops);\n+\n+\t/* Do not allow read past end of device */\n+\tif (ops->datbuf && (from + ops->len) > mtd->size) {\n+\t\tpr_debug(\"%s: attempt to read beyond end of device\\n\",\n+\t\t\t __func__);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (unlikely(ops->ooboffs >= maxooblen)) {\n+\t\tpr_debug(\"%s: attempt to start read outside oob\\n\",\n+\t\t\t __func__);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (unlikely(from >= mtd->size ||\n+\t    ops->ooboffs + ops->ooblen > ((mtd->size >> mtd->writesize_shift) -\n+\t    (from >> mtd->writesize_shift)) * maxooblen)) {\n+\t\tpr_debug(\"%s: attempt to read beyond end of device\\n\",\n+\t\t\t __func__);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\treturn mtk_snand_mtd_read_data(msm, from, ops);\n+}\n+\n+static int mtk_snand_mtd_write_data(struct mtk_snand_mtd *msm, uint64_t addr,\n+\t\t\t\t    struct mtd_oob_ops *ops)\n+{\n+\tstruct mtd_info *mtd = dev_get_uclass_priv(msm->dev);\n+\tsize_t len, ooblen, maxooblen, chklen, oobwrlen;\n+\tuint32_t col, ooboffs;\n+\tuint8_t *datcache, *oobcache;\n+\tbool raw = ops->mode == MTD_OPS_RAW ? true : false;\n+\tint ret;\n+\n+\tcol = addr & mtd->writesize_mask;\n+\taddr &= ~mtd->writesize_mask;\n+\tmaxooblen = mtd_oobavail(mtd, ops);\n+\tooboffs = ops->ooboffs;\n+\tooblen = ops->ooblen;\n+\tlen = ops->len;\n+\n+\tdatcache = len ? msm->page_cache : NULL;\n+\toobcache = ooblen ? msm->page_cache + mtd->writesize : NULL;\n+\n+\tops->oobretlen = 0;\n+\tops->retlen = 0;\n+\n+\twhile (len || ooblen) {\n+\t\tWATCHDOG_RESET();\n+\n+\t\tif (len) {\n+\t\t\t/* Move data */\n+\t\t\tchklen = mtd->writesize - col;\n+\t\t\tif (chklen > len)\n+\t\t\t\tchklen = len;\n+\n+\t\t\tmemset(datcache, 0xff, col);\n+\t\t\tmemcpy(datcache + col, ops->datbuf + ops->retlen,\n+\t\t\t       chklen);\n+\t\t\tmemset(datcache + col + chklen, 0xff,\n+\t\t\t       mtd->writesize - col - chklen);\n+\t\t\tlen -= chklen;\n+\t\t\tcol = 0; /* (col + chklen) %  */\n+\t\t\tops->retlen += chklen;\n+\t\t}\n+\n+\t\toobwrlen = 0;\n+\t\tif (ooblen) {\n+\t\t\t/* Move oob */\n+\t\t\tchklen = maxooblen - ooboffs;\n+\t\t\tif (chklen > ooblen)\n+\t\t\t\tchklen = ooblen;\n+\n+\t\t\tmemset(oobcache, 0xff, ooboffs);\n+\t\t\tmemcpy(oobcache + ooboffs,\n+\t\t\t       ops->oobbuf + ops->oobretlen, chklen);\n+\t\t\tmemset(oobcache + ooboffs + chklen, 0xff,\n+\t\t\t       mtd->oobsize - ooboffs - chklen);\n+\t\t\toobwrlen = chklen + ooboffs;\n+\t\t\tooblen -= chklen;\n+\t\t\tooboffs = 0; /* (ooboffs + chklen) % maxooblen; */\n+\t\t\tops->oobretlen += chklen;\n+\t\t}\n+\n+\t\tif (ops->mode == MTD_OPS_AUTO_OOB)\n+\t\t\tret = mtk_snand_write_page_auto_oob(msm->snf, addr,\n+\t\t\t\tdatcache, oobcache, oobwrlen, NULL, raw);\n+\t\telse\n+\t\t\tret = mtk_snand_write_page(msm->snf, addr, datcache,\n+\t\t\t\toobcache, raw);\n+\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\n+\t\taddr += mtd->writesize;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int mtk_snand_mtd_write_oob(struct mtd_info *mtd, loff_t to,\n+\t\t\t\t   struct mtd_oob_ops *ops)\n+{\n+\tstruct mtk_snand_mtd *msm = mtd_to_msm(mtd);\n+\tuint32_t maxooblen;\n+\n+\tif (!ops->oobbuf && !ops->datbuf) {\n+\t\tif (ops->ooblen || ops->len)\n+\t\t\treturn -EINVAL;\n+\n+\t\treturn 0;\n+\t}\n+\n+\tswitch (ops->mode) {\n+\tcase MTD_OPS_PLACE_OOB:\n+\tcase MTD_OPS_AUTO_OOB:\n+\tcase MTD_OPS_RAW:\n+\t\tbreak;\n+\tdefault:\n+\t\tpr_debug(\"%s: unsupported oob mode: %u\\n\", __func__, ops->mode);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tmaxooblen = mtd_oobavail(mtd, ops);\n+\n+\t/* Do not allow write past end of device */\n+\tif (ops->datbuf && (to + ops->len) > mtd->size) {\n+\t\tpr_debug(\"%s: attempt to write beyond end of device\\n\",\n+\t\t\t __func__);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (unlikely(ops->ooboffs >= maxooblen)) {\n+\t\tpr_debug(\"%s: attempt to start write outside oob\\n\",\n+\t\t\t __func__);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (unlikely(to >= mtd->size ||\n+\t    ops->ooboffs + ops->ooblen > ((mtd->size >> mtd->writesize_shift) -\n+\t    (to >> mtd->writesize_shift)) * maxooblen)) {\n+\t\tpr_debug(\"%s: attempt to write beyond end of device\\n\",\n+\t\t\t __func__);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\treturn mtk_snand_mtd_write_data(msm, to, ops);\n+}\n+\n+static int mtk_snand_mtd_read(struct mtd_info *mtd, loff_t from, size_t len,\n+\t\t\t      size_t *retlen, u_char *buf)\n+{\n+\tstruct mtd_oob_ops ops = {\n+\t\t.mode = MTD_OPS_PLACE_OOB,\n+\t\t.datbuf = buf,\n+\t\t.len = len,\n+\t};\n+\tint ret;\n+\n+\tret = mtk_snand_mtd_read_oob(mtd, from, &ops);\n+\n+\tif (retlen)\n+\t\t*retlen = ops.retlen;\n+\n+\treturn ret;\n+}\n+\n+static int mtk_snand_mtd_write(struct mtd_info *mtd, loff_t to, size_t len,\n+\t\t\t       size_t *retlen, const u_char *buf)\n+{\n+\tstruct mtd_oob_ops ops = {\n+\t\t.mode = MTD_OPS_PLACE_OOB,\n+\t\t.datbuf = (void *)buf,\n+\t\t.len = len,\n+\t};\n+\tint ret;\n+\n+\tret = mtk_snand_mtd_write_oob(mtd, to, &ops);\n+\n+\tif (retlen)\n+\t\t*retlen = ops.retlen;\n+\n+\treturn ret;\n+}\n+\n+static int mtk_snand_mtd_block_isbad(struct mtd_info *mtd, loff_t offs)\n+{\n+\tstruct mtk_snand_mtd *msm = mtd_to_msm(mtd);\n+\n+\treturn mtk_snand_block_isbad(msm->snf, offs);\n+}\n+\n+static int mtk_snand_mtd_block_markbad(struct mtd_info *mtd, loff_t offs)\n+{\n+\tstruct mtk_snand_mtd *msm = mtd_to_msm(mtd);\n+\n+\treturn mtk_snand_block_markbad(msm->snf, offs);\n+}\n+\n+static int mtk_snand_ooblayout_ecc(struct mtd_info *mtd, int section,\n+\t\t\t\t   struct mtd_oob_region *oobecc)\n+{\n+\tstruct mtk_snand_mtd *msm = mtd_to_msm(mtd);\n+\n+\tif (section)\n+\t\treturn -ERANGE;\n+\n+\toobecc->offset = msm->cinfo.fdm_size * msm->cinfo.num_sectors;\n+\toobecc->length = mtd->oobsize - oobecc->offset;\n+\n+\treturn 0;\n+}\n+\n+static int mtk_snand_ooblayout_free(struct mtd_info *mtd, int section,\n+\t\t\t\t    struct mtd_oob_region *oobfree)\n+{\n+\tstruct mtk_snand_mtd *msm = mtd_to_msm(mtd);\n+\n+\tif (section >= msm->cinfo.num_sectors)\n+\t\treturn -ERANGE;\n+\n+\toobfree->length = msm->cinfo.fdm_size - 1;\n+\toobfree->offset = section * msm->cinfo.fdm_size + 1;\n+\n+\treturn 0;\n+}\n+\n+static const struct mtd_ooblayout_ops mtk_snand_ooblayout = {\n+\t.ecc = mtk_snand_ooblayout_ecc,\n+\t.rfree = mtk_snand_ooblayout_free,\n+};\n+\n+static int mtk_snand_mtd_probe(struct udevice *dev)\n+{\n+\tstruct mtk_snand_mtd *msm = dev_get_priv(dev);\n+\tstruct mtd_info *mtd = dev_get_uclass_priv(dev);\n+\tstruct mtk_snand_platdata mtk_snand_pdata = {};\n+\tsize_t namelen;\n+\tfdt_addr_t base;\n+\tint ret;\n+\n+\tbase = dev_read_addr_name(dev, \"nfi\");\n+\tif (base == FDT_ADDR_T_NONE)\n+\t\treturn -EINVAL;\n+\tmtk_snand_pdata.nfi_base = map_sysmem(base, 0);\n+\n+\tbase = dev_read_addr_name(dev, \"ecc\");\n+\tif (base == FDT_ADDR_T_NONE)\n+\t\treturn -EINVAL;\n+\tmtk_snand_pdata.ecc_base = map_sysmem(base, 0);\n+\n+\tmtk_snand_pdata.soc = dev_get_driver_data(dev);\n+\tmtk_snand_pdata.quad_spi = dev_read_bool(dev, \"quad-spi\");\n+\n+\tret = mtk_snand_init(NULL, &mtk_snand_pdata, &msm->snf);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tmtk_snand_get_chip_info(msm->snf, &msm->cinfo);\n+\n+\tmsm->page_cache = malloc(msm->cinfo.pagesize + msm->cinfo.sparesize);\n+\tif (!msm->page_cache) {\n+\t\tprintf(\"%s: failed to allocate memory for page cache\\n\",\n+\t\t       __func__);\n+\t\tret = -ENOMEM;\n+\t\tgoto errout1;\n+\t}\n+\n+\tnamelen = sizeof(snand_mtd_name_prefix) + 12;\n+\n+\tmtd->name = malloc(namelen);\n+\tif (!mtd->name) {\n+\t\tprintf(\"%s: failed to allocate memory for MTD name\\n\",\n+\t\t       __func__);\n+\t\tret = -ENOMEM;\n+\t\tgoto errout2;\n+\t}\n+\n+\tmsm->dev = dev;\n+\n+\tsnprintf(mtd->name, namelen, \"%s%u\", snand_mtd_name_prefix, snandidx++);\n+\n+\tmtd->priv = msm;\n+\tmtd->dev = dev;\n+\tmtd->type = MTD_NANDFLASH;\n+\tmtd->flags = MTD_CAP_NANDFLASH;\n+\n+\tmtd->size = msm->cinfo.chipsize;\n+\tmtd->erasesize = msm->cinfo.blocksize;\n+\tmtd->writesize = msm->cinfo.pagesize;\n+\tmtd->writebufsize = mtd->writesize;\n+\tmtd->oobsize = msm->cinfo.sparesize;\n+\tmtd->oobavail = msm->cinfo.num_sectors * (msm->cinfo.fdm_size - 1);\n+\n+\tmtd->ooblayout = &mtk_snand_ooblayout;\n+\n+\tmtd->ecc_strength = msm->cinfo.ecc_strength * msm->cinfo.num_sectors;\n+\tmtd->bitflip_threshold = (mtd->ecc_strength * 3) / 4;\n+\tmtd->ecc_step_size = msm->cinfo.sector_size;\n+\n+\tmtd->_read = mtk_snand_mtd_read;\n+\tmtd->_write = mtk_snand_mtd_write;\n+\tmtd->_erase = mtk_snand_mtd_erase;\n+\tmtd->_read_oob = mtk_snand_mtd_read_oob;\n+\tmtd->_write_oob = mtk_snand_mtd_write_oob;\n+\tmtd->_block_isbad = mtk_snand_mtd_block_isbad;\n+\tmtd->_block_markbad = mtk_snand_mtd_block_markbad;\n+\n+\tret = add_mtd_device(mtd);\n+\tif (ret) {\n+\t\tprintf(\"%s: failed to add SPI-NAND MTD device\\n\", __func__);\n+\t\tret = -ENODEV;\n+\t\tgoto errout3;\n+\t}\n+\n+\tprintf(\"SPI-NAND: %s (%lluMB)\\n\", msm->cinfo.model,\n+\t       msm->cinfo.chipsize >> 20);\n+\n+\treturn 0;\n+\n+errout3:\n+\tfree(mtd->name);\n+\n+errout2:\n+\tfree(msm->page_cache);\n+\n+errout1:\n+\tmtk_snand_cleanup(msm->snf);\n+\n+\treturn ret;\n+}\n+\n+static const struct udevice_id mtk_snand_ids[] = {\n+\t{ .compatible = \"mediatek,mt7622-snand\", .data = SNAND_SOC_MT7622 },\n+\t{ .compatible = \"mediatek,mt7629-snand\", .data = SNAND_SOC_MT7629 },\n+\t{ .compatible = \"mediatek,mt7986-snand\", .data = SNAND_SOC_MT7986 },\n+\t{ /* sentinel */ },\n+};\n+\n+U_BOOT_DRIVER(spinand) = {\n+\t.name = \"mtk-snand\",\n+\t.id = UCLASS_MTD,\n+\t.of_match = mtk_snand_ids,\n+\t.priv_auto = sizeof(struct mtk_snand_mtd),\n+\t.probe = mtk_snand_mtd_probe,\n+};\n--- /dev/null\n+++ b/drivers/mtd/mtk-snand/mtk-snand-os.c\n@@ -0,0 +1,39 @@\n+// SPDX-License-Identifier: GPL-2.0\n+/*\n+ * Copyright (C) 2020 MediaTek Inc. All Rights Reserved.\n+ *\n+ * Author: Weijie Gao <weijie.gao@mediatek.com>\n+ */\n+\n+#include \"mtk-snand-def.h\"\n+\n+int mtk_snand_log(struct mtk_snand_plat_dev *pdev,\n+\t\t  enum mtk_snand_log_category cat, const char *fmt, ...)\n+{\n+\tconst char *catname = \"\";\n+\tva_list ap;\n+\tint ret;\n+\n+\tswitch (cat) {\n+\tcase SNAND_LOG_NFI:\n+\t\tcatname = \"NFI: \";\n+\t\tbreak;\n+\tcase SNAND_LOG_SNFI:\n+\t\tcatname = \"SNFI: \";\n+\t\tbreak;\n+\tcase SNAND_LOG_ECC:\n+\t\tcatname = \"ECC: \";\n+\t\tbreak;\n+\tdefault:\n+\t\tbreak;\n+\t}\n+\n+\tputs(\"SPI-NAND: \");\n+\tputs(catname);\n+\n+\tva_start(ap, fmt);\n+\tret = vprintf(fmt, ap);\n+\tva_end(ap);\n+\n+\treturn ret;\n+}\n--- /dev/null\n+++ b/drivers/mtd/mtk-snand/mtk-snand-os.h\n@@ -0,0 +1,120 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+/*\n+ * Copyright (C) 2020 MediaTek Inc. All Rights Reserved.\n+ *\n+ * Author: Weijie Gao <weijie.gao@mediatek.com>\n+ */\n+\n+#ifndef _MTK_SNAND_OS_H_\n+#define _MTK_SNAND_OS_H_\n+\n+#include <common.h>\n+#include <cpu_func.h>\n+#include <errno.h>\n+#include <div64.h>\n+#include <malloc.h>\n+#include <stdbool.h>\n+#include <stdarg.h>\n+#include <linux/types.h>\n+#include <asm/io.h>\n+#include <linux/bitops.h>\n+#include <linux/sizes.h>\n+#include <linux/iopoll.h>\n+\n+#ifndef ARCH_DMA_MINALIGN\n+#define ARCH_DMA_MINALIGN\t\t64\n+#endif\n+\n+struct mtk_snand_plat_dev {\n+\tulong unused;\n+};\n+\n+/* Polling helpers */\n+#define read16_poll_timeout(addr, val, cond, sleep_us, timeout_us) \\\n+\treadw_poll_timeout((addr), (val), (cond), (timeout_us))\n+\n+#define read32_poll_timeout(addr, val, cond, sleep_us, timeout_us) \\\n+\treadl_poll_timeout((addr), (val), (cond), (timeout_us))\n+\n+/* Timer helpers */\n+typedef uint64_t mtk_snand_time_t;\n+\n+static inline mtk_snand_time_t timer_get_ticks(void)\n+{\n+\treturn get_ticks();\n+}\n+\n+static inline mtk_snand_time_t timer_time_to_tick(uint32_t timeout_us)\n+{\n+\treturn usec_to_tick(timeout_us);\n+}\n+\n+static inline bool timer_is_timeout(mtk_snand_time_t start_tick,\n+\t\t\t\t    mtk_snand_time_t timeout_tick)\n+{\n+\treturn get_ticks() - start_tick > timeout_tick;\n+}\n+\n+/* Memory helpers */\n+static inline void *generic_mem_alloc(struct mtk_snand_plat_dev *pdev,\n+\t\t\t\t      size_t size)\n+{\n+\treturn calloc(1, size);\n+}\n+\n+static inline void generic_mem_free(struct mtk_snand_plat_dev *pdev, void *ptr)\n+{\n+\tfree(ptr);\n+}\n+\n+static inline void *dma_mem_alloc(struct mtk_snand_plat_dev *pdev, size_t size)\n+{\n+\treturn memalign(ARCH_DMA_MINALIGN, size);\n+}\n+\n+static inline void dma_mem_free(struct mtk_snand_plat_dev *pdev, void *ptr)\n+{\n+\tfree(ptr);\n+}\n+\n+static inline int dma_mem_map(struct mtk_snand_plat_dev *pdev, void *vaddr,\n+\t\t\t      uintptr_t *dma_addr, size_t size, bool to_device)\n+{\n+\tsize_t cachelen = roundup(size, ARCH_DMA_MINALIGN);\n+\tuintptr_t endaddr = (uintptr_t)vaddr + cachelen;\n+\n+\tif (to_device)\n+\t\tflush_dcache_range((uintptr_t)vaddr, endaddr);\n+\telse\n+\t\tinvalidate_dcache_range((uintptr_t)vaddr, endaddr);\n+\n+\t*dma_addr = (uintptr_t)vaddr;\n+\n+\treturn 0;\n+}\n+\n+static inline void dma_mem_unmap(struct mtk_snand_plat_dev *pdev,\n+\t\t\t\t uintptr_t dma_addr, size_t size,\n+\t\t\t\t bool to_device)\n+{\n+}\n+\n+/* Interrupt helpers */\n+static inline void irq_completion_done(struct mtk_snand_plat_dev *pdev)\n+{\n+}\n+\n+static inline void irq_completion_init(struct mtk_snand_plat_dev *pdev)\n+{\n+}\n+\n+static inline int irq_completion_wait(struct mtk_snand_plat_dev *pdev,\n+\t\t\t\t      void __iomem *reg, uint32_t bit,\n+\t\t\t\t      uint32_t timeout_us)\n+{\n+\tuint32_t val;\n+\n+\treturn read32_poll_timeout(reg, val, val & bit, 0, timeout_us);\n+}\n+\n+#endif /* _MTK_SNAND_OS_H_ */\n--- /dev/null\n+++ b/drivers/mtd/mtk-snand/mtk-snand.c\n@@ -0,0 +1,1776 @@\n+// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause\n+/*\n+ * Copyright (C) 2020 MediaTek Inc. All Rights Reserved.\n+ *\n+ * Author: Weijie Gao <weijie.gao@mediatek.com>\n+ */\n+\n+#include \"mtk-snand-def.h\"\n+\n+/* NFI registers */\n+#define NFI_CNFG\t\t\t0x000\n+#define CNFG_OP_MODE_S\t\t\t12\n+#define   CNFG_OP_MODE_CUST\t\t6\n+#define   CNFG_OP_MODE_PROGRAM\t\t3\n+#define CNFG_AUTO_FMT_EN\t\tBIT(9)\n+#define CNFG_HW_ECC_EN\t\t\tBIT(8)\n+#define CNFG_DMA_BURST_EN\t\tBIT(2)\n+#define CNFG_READ_MODE\t\t\tBIT(1)\n+#define CNFG_DMA_MODE\t\t\tBIT(0)\n+\n+#define NFI_PAGEFMT\t\t\t0x0004\n+#define NFI_SPARE_SIZE_LS_S\t\t16\n+#define NFI_FDM_ECC_NUM_S\t\t12\n+#define NFI_FDM_NUM_S\t\t\t8\n+#define NFI_SPARE_SIZE_S\t\t4\n+#define NFI_SEC_SEL_512\t\t\tBIT(2)\n+#define NFI_PAGE_SIZE_S\t\t\t0\n+#define   NFI_PAGE_SIZE_512_2K\t\t0\n+#define   NFI_PAGE_SIZE_2K_4K\t\t1\n+#define   NFI_PAGE_SIZE_4K_8K\t\t2\n+#define   NFI_PAGE_SIZE_8K_16K\t\t3\n+\n+#define NFI_CON\t\t\t\t0x008\n+#define CON_SEC_NUM_S\t\t\t12\n+#define CON_BWR\t\t\t\tBIT(9)\n+#define CON_BRD\t\t\t\tBIT(8)\n+#define CON_NFI_RST\t\t\tBIT(1)\n+#define CON_FIFO_FLUSH\t\t\tBIT(0)\n+\n+#define NFI_INTR_EN\t\t\t0x010\n+#define NFI_INTR_STA\t\t\t0x014\n+#define NFI_IRQ_INTR_EN\t\t\tBIT(31)\n+#define NFI_IRQ_CUS_READ\t\tBIT(8)\n+#define NFI_IRQ_CUS_PG\t\t\tBIT(7)\n+\n+#define NFI_CMD\t\t\t\t0x020\n+\n+#define NFI_STRDATA\t\t\t0x040\n+#define STR_DATA\t\t\tBIT(0)\n+\n+#define NFI_STA\t\t\t\t0x060\n+#define NFI_NAND_FSM\t\t\tGENMASK(28, 24)\n+#define NFI_FSM\t\t\t\tGENMASK(19, 16)\n+#define READ_EMPTY\t\t\tBIT(12)\n+\n+#define NFI_FIFOSTA\t\t\t0x064\n+#define FIFO_WR_REMAIN_S\t\t8\n+#define FIFO_RD_REMAIN_S\t\t0\n+\n+#define NFI_STRADDR\t\t\t0x080\n+\n+#define NFI_FDM0L\t\t\t0x0a0\n+#define NFI_FDM0M\t\t\t0x0a4\n+#define NFI_FDML(n)\t\t\t(NFI_FDM0L + (n) * 8)\n+#define NFI_FDMM(n)\t\t\t(NFI_FDM0M + (n) * 8)\n+\n+#define NFI_DEBUG_CON1\t\t\t0x220\n+#define WBUF_EN\t\t\t\tBIT(2)\n+\n+#define NFI_MASTERSTA\t\t\t0x224\n+#define MAS_ADDR\t\t\tGENMASK(11, 9)\n+#define MAS_RD\t\t\t\tGENMASK(8, 6)\n+#define MAS_WR\t\t\t\tGENMASK(5, 3)\n+#define MAS_RDDLY\t\t\tGENMASK(2, 0)\n+#define NFI_MASTERSTA_MASK_7622\t\t(MAS_ADDR | MAS_RD | MAS_WR | MAS_RDDLY)\n+#define AHB_BUS_BUSY\t\t\tBIT(1)\n+#define BUS_BUSY\t\t\tBIT(0)\n+#define NFI_MASTERSTA_MASK_7986\t\t(AHB_BUS_BUSY | BUS_BUSY)\n+\n+/* SNFI registers */\n+#define SNF_MAC_CTL\t\t\t0x500\n+#define MAC_XIO_SEL\t\t\tBIT(4)\n+#define SF_MAC_EN\t\t\tBIT(3)\n+#define SF_TRIG\t\t\t\tBIT(2)\n+#define WIP_READY\t\t\tBIT(1)\n+#define WIP\t\t\t\tBIT(0)\n+\n+#define SNF_MAC_OUTL\t\t\t0x504\n+#define SNF_MAC_INL\t\t\t0x508\n+\n+#define SNF_RD_CTL2\t\t\t0x510\n+#define DATA_READ_DUMMY_S\t\t8\n+#define DATA_READ_CMD_S\t\t\t0\n+\n+#define SNF_RD_CTL3\t\t\t0x514\n+\n+#define SNF_PG_CTL1\t\t\t0x524\n+#define PG_LOAD_CMD_S\t\t\t8\n+\n+#define SNF_PG_CTL2\t\t\t0x528\n+\n+#define SNF_MISC_CTL\t\t\t0x538\n+#define SW_RST\t\t\t\tBIT(28)\n+#define FIFO_RD_LTC_S\t\t\t25\n+#define PG_LOAD_X4_EN\t\t\tBIT(20)\n+#define DATA_READ_MODE_S\t\t16\n+#define DATA_READ_MODE\t\t\tGENMASK(18, 16)\n+#define   DATA_READ_MODE_X1\t\t0\n+#define   DATA_READ_MODE_X2\t\t1\n+#define   DATA_READ_MODE_X4\t\t2\n+#define   DATA_READ_MODE_DUAL\t\t5\n+#define   DATA_READ_MODE_QUAD\t\t6\n+#define PG_LOAD_CUSTOM_EN\t\tBIT(7)\n+#define DATARD_CUSTOM_EN\t\tBIT(6)\n+#define CS_DESELECT_CYC_S\t\t0\n+\n+#define SNF_MISC_CTL2\t\t\t0x53c\n+#define PROGRAM_LOAD_BYTE_NUM_S\t\t16\n+#define READ_DATA_BYTE_NUM_S\t\t11\n+\n+#define SNF_DLY_CTL3\t\t\t0x548\n+#define SFCK_SAM_DLY_S\t\t\t0\n+\n+#define SNF_STA_CTL1\t\t\t0x550\n+#define CUS_PG_DONE\t\t\tBIT(28)\n+#define CUS_READ_DONE\t\t\tBIT(27)\n+#define SPI_STATE_S\t\t\t0\n+#define SPI_STATE\t\t\tGENMASK(3, 0)\n+\n+#define SNF_CFG\t\t\t\t0x55c\n+#define SPI_MODE\t\t\tBIT(0)\n+\n+#define SNF_GPRAM\t\t\t0x800\n+#define SNF_GPRAM_SIZE\t\t\t0xa0\n+\n+#define SNFI_POLL_INTERVAL\t\t1000000\n+\n+static const uint8_t mt7622_spare_sizes[] = { 16, 26, 27, 28 };\n+\n+static const uint8_t mt7986_spare_sizes[] = {\n+\t16, 26, 27, 28, 32, 36, 40, 44, 48, 49, 50, 51, 52, 62, 61, 63, 64,\n+\t67, 74\n+};\n+\n+static const struct mtk_snand_soc_data mtk_snand_socs[__SNAND_SOC_MAX] = {\n+\t[SNAND_SOC_MT7622] = {\n+\t\t.sector_size = 512,\n+\t\t.max_sectors = 8,\n+\t\t.fdm_size = 8,\n+\t\t.fdm_ecc_size = 1,\n+\t\t.fifo_size = 32,\n+\t\t.bbm_swap = false,\n+\t\t.empty_page_check = false,\n+\t\t.mastersta_mask = NFI_MASTERSTA_MASK_7622,\n+\t\t.spare_sizes = mt7622_spare_sizes,\n+\t\t.num_spare_size = ARRAY_SIZE(mt7622_spare_sizes)\n+\t},\n+\t[SNAND_SOC_MT7629] = {\n+\t\t.sector_size = 512,\n+\t\t.max_sectors = 8,\n+\t\t.fdm_size = 8,\n+\t\t.fdm_ecc_size = 1,\n+\t\t.fifo_size = 32,\n+\t\t.bbm_swap = true,\n+\t\t.empty_page_check = false,\n+\t\t.mastersta_mask = NFI_MASTERSTA_MASK_7622,\n+\t\t.spare_sizes = mt7622_spare_sizes,\n+\t\t.num_spare_size = ARRAY_SIZE(mt7622_spare_sizes)\n+\t},\n+\t[SNAND_SOC_MT7986] = {\n+\t\t.sector_size = 1024,\n+\t\t.max_sectors = 16,\n+\t\t.fdm_size = 8,\n+\t\t.fdm_ecc_size = 1,\n+\t\t.fifo_size = 64,\n+\t\t.bbm_swap = true,\n+\t\t.empty_page_check = true,\n+\t\t.mastersta_mask = NFI_MASTERSTA_MASK_7986,\n+\t\t.spare_sizes = mt7986_spare_sizes,\n+\t\t.num_spare_size = ARRAY_SIZE(mt7986_spare_sizes)\n+\t},\n+};\n+\n+static inline uint32_t nfi_read32(struct mtk_snand *snf, uint32_t reg)\n+{\n+\treturn readl(snf->nfi_base + reg);\n+}\n+\n+static inline void nfi_write32(struct mtk_snand *snf, uint32_t reg,\n+\t\t\t       uint32_t val)\n+{\n+\twritel(val, snf->nfi_base + reg);\n+}\n+\n+static inline void nfi_write16(struct mtk_snand *snf, uint32_t reg,\n+\t\t\t       uint16_t val)\n+{\n+\twritew(val, snf->nfi_base + reg);\n+}\n+\n+static inline void nfi_rmw32(struct mtk_snand *snf, uint32_t reg, uint32_t clr,\n+\t\t\t     uint32_t set)\n+{\n+\tuint32_t val;\n+\n+\tval = readl(snf->nfi_base + reg);\n+\tval &= ~clr;\n+\tval |= set;\n+\twritel(val, snf->nfi_base + reg);\n+}\n+\n+static void nfi_write_data(struct mtk_snand *snf, uint32_t reg,\n+\t\t\t   const uint8_t *data, uint32_t len)\n+{\n+\tuint32_t i, val = 0, es = sizeof(uint32_t);\n+\n+\tfor (i = reg; i < reg + len; i++) {\n+\t\tval |= ((uint32_t)*data++) << (8 * (i % es));\n+\n+\t\tif (i % es == es - 1 || i == reg + len - 1) {\n+\t\t\tnfi_write32(snf, i & ~(es - 1), val);\n+\t\t\tval = 0;\n+\t\t}\n+\t}\n+}\n+\n+static void nfi_read_data(struct mtk_snand *snf, uint32_t reg, uint8_t *data,\n+\t\t\t  uint32_t len)\n+{\n+\tuint32_t i, val = 0, es = sizeof(uint32_t);\n+\n+\tfor (i = reg; i < reg + len; i++) {\n+\t\tif (i == reg || i % es == 0)\n+\t\t\tval = nfi_read32(snf, i & ~(es - 1));\n+\n+\t\t*data++ = (uint8_t)(val >> (8 * (i % es)));\n+\t}\n+}\n+\n+static inline void do_bm_swap(uint8_t *bm1, uint8_t *bm2)\n+{\n+\tuint8_t tmp = *bm1;\n+\t*bm1 = *bm2;\n+\t*bm2 = tmp;\n+}\n+\n+static void mtk_snand_bm_swap_raw(struct mtk_snand *snf)\n+{\n+\tuint32_t fdm_bbm_pos;\n+\n+\tif (!snf->nfi_soc->bbm_swap || snf->ecc_steps == 1)\n+\t\treturn;\n+\n+\tfdm_bbm_pos = (snf->ecc_steps - 1) * snf->raw_sector_size +\n+\t\t      snf->nfi_soc->sector_size;\n+\tdo_bm_swap(&snf->page_cache[fdm_bbm_pos],\n+\t\t   &snf->page_cache[snf->writesize]);\n+}\n+\n+static void mtk_snand_bm_swap(struct mtk_snand *snf)\n+{\n+\tuint32_t buf_bbm_pos, fdm_bbm_pos;\n+\n+\tif (!snf->nfi_soc->bbm_swap || snf->ecc_steps == 1)\n+\t\treturn;\n+\n+\tbuf_bbm_pos = snf->writesize -\n+\t\t      (snf->ecc_steps - 1) * snf->spare_per_sector;\n+\tfdm_bbm_pos = snf->writesize +\n+\t\t      (snf->ecc_steps - 1) * snf->nfi_soc->fdm_size;\n+\tdo_bm_swap(&snf->page_cache[fdm_bbm_pos],\n+\t\t   &snf->page_cache[buf_bbm_pos]);\n+}\n+\n+static void mtk_snand_fdm_bm_swap_raw(struct mtk_snand *snf)\n+{\n+\tuint32_t fdm_bbm_pos1, fdm_bbm_pos2;\n+\n+\tif (!snf->nfi_soc->bbm_swap || snf->ecc_steps == 1)\n+\t\treturn;\n+\n+\tfdm_bbm_pos1 = snf->nfi_soc->sector_size;\n+\tfdm_bbm_pos2 = (snf->ecc_steps - 1) * snf->raw_sector_size +\n+\t\t       snf->nfi_soc->sector_size;\n+\tdo_bm_swap(&snf->page_cache[fdm_bbm_pos1],\n+\t\t   &snf->page_cache[fdm_bbm_pos2]);\n+}\n+\n+static void mtk_snand_fdm_bm_swap(struct mtk_snand *snf)\n+{\n+\tuint32_t fdm_bbm_pos1, fdm_bbm_pos2;\n+\n+\tif (!snf->nfi_soc->bbm_swap || snf->ecc_steps == 1)\n+\t\treturn;\n+\n+\tfdm_bbm_pos1 = snf->writesize;\n+\tfdm_bbm_pos2 = snf->writesize +\n+\t\t       (snf->ecc_steps - 1) * snf->nfi_soc->fdm_size;\n+\tdo_bm_swap(&snf->page_cache[fdm_bbm_pos1],\n+\t\t   &snf->page_cache[fdm_bbm_pos2]);\n+}\n+\n+static int mtk_nfi_reset(struct mtk_snand *snf)\n+{\n+\tuint32_t val, fifo_mask;\n+\tint ret;\n+\n+\tnfi_write32(snf, NFI_CON, CON_FIFO_FLUSH | CON_NFI_RST);\n+\n+\tret = read16_poll_timeout(snf->nfi_base + NFI_MASTERSTA, val,\n+\t\t\t\t  !(val & snf->nfi_soc->mastersta_mask), 0,\n+\t\t\t\t  SNFI_POLL_INTERVAL);\n+\tif (ret) {\n+\t\tsnand_log_nfi(snf->pdev,\n+\t\t\t      \"NFI master is still busy after reset\\n\");\n+\t\treturn ret;\n+\t}\n+\n+\tret = read32_poll_timeout(snf->nfi_base + NFI_STA, val,\n+\t\t\t\t  !(val & (NFI_FSM | NFI_NAND_FSM)), 0,\n+\t\t\t\t  SNFI_POLL_INTERVAL);\n+\tif (ret) {\n+\t\tsnand_log_nfi(snf->pdev, \"Failed to reset NFI\\n\");\n+\t\treturn ret;\n+\t}\n+\n+\tfifo_mask = ((snf->nfi_soc->fifo_size - 1) << FIFO_RD_REMAIN_S) |\n+\t\t    ((snf->nfi_soc->fifo_size - 1) << FIFO_WR_REMAIN_S);\n+\tret = read16_poll_timeout(snf->nfi_base + NFI_FIFOSTA, val,\n+\t\t\t\t  !(val & fifo_mask), 0, SNFI_POLL_INTERVAL);\n+\tif (ret) {\n+\t\tsnand_log_nfi(snf->pdev, \"NFI FIFOs are not empty\\n\");\n+\t\treturn ret;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int mtk_snand_mac_reset(struct mtk_snand *snf)\n+{\n+\tint ret;\n+\tuint32_t val;\n+\n+\tnfi_rmw32(snf, SNF_MISC_CTL, 0, SW_RST);\n+\n+\tret = read32_poll_timeout(snf->nfi_base + SNF_STA_CTL1, val,\n+\t\t\t\t  !(val & SPI_STATE), 0, SNFI_POLL_INTERVAL);\n+\tif (ret)\n+\t\tsnand_log_snfi(snf->pdev, \"Failed to reset SNFI MAC\\n\");\n+\n+\tnfi_write32(snf, SNF_MISC_CTL, (2 << FIFO_RD_LTC_S) |\n+\t\t    (10 << CS_DESELECT_CYC_S));\n+\n+\treturn ret;\n+}\n+\n+static int mtk_snand_mac_trigger(struct mtk_snand *snf, uint32_t outlen,\n+\t\t\t\t uint32_t inlen)\n+{\n+\tint ret;\n+\tuint32_t val;\n+\n+\tnfi_write32(snf, SNF_MAC_CTL, SF_MAC_EN);\n+\tnfi_write32(snf, SNF_MAC_OUTL, outlen);\n+\tnfi_write32(snf, SNF_MAC_INL, inlen);\n+\n+\tnfi_write32(snf, SNF_MAC_CTL, SF_MAC_EN | SF_TRIG);\n+\n+\tret = read32_poll_timeout(snf->nfi_base + SNF_MAC_CTL, val,\n+\t\t\t\t  val & WIP_READY, 0, SNFI_POLL_INTERVAL);\n+\tif (ret) {\n+\t\tsnand_log_snfi(snf->pdev, \"Timed out waiting for WIP_READY\\n\");\n+\t\tgoto cleanup;\n+\t}\n+\n+\tret = read32_poll_timeout(snf->nfi_base + SNF_MAC_CTL, val,\n+\t\t\t\t  !(val & WIP), 0, SNFI_POLL_INTERVAL);\n+\tif (ret) {\n+\t\tsnand_log_snfi(snf->pdev,\n+\t\t\t       \"Timed out waiting for WIP cleared\\n\");\n+\t}\n+\n+cleanup:\n+\tnfi_write32(snf, SNF_MAC_CTL, 0);\n+\n+\treturn ret;\n+}\n+\n+int mtk_snand_mac_io(struct mtk_snand *snf, const uint8_t *out, uint32_t outlen,\n+\t\t     uint8_t *in, uint32_t inlen)\n+{\n+\tint ret;\n+\n+\tif (outlen + inlen > SNF_GPRAM_SIZE)\n+\t\treturn -EINVAL;\n+\n+\tmtk_snand_mac_reset(snf);\n+\n+\tnfi_write_data(snf, SNF_GPRAM, out, outlen);\n+\n+\tret = mtk_snand_mac_trigger(snf, outlen, inlen);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tif (!inlen)\n+\t\treturn 0;\n+\n+\tnfi_read_data(snf, SNF_GPRAM + outlen, in, inlen);\n+\n+\treturn 0;\n+}\n+\n+static int mtk_snand_get_feature(struct mtk_snand *snf, uint32_t addr)\n+{\n+\tuint8_t op[2], val;\n+\tint ret;\n+\n+\top[0] = SNAND_CMD_GET_FEATURE;\n+\top[1] = (uint8_t)addr;\n+\n+\tret = mtk_snand_mac_io(snf, op, sizeof(op), &val, 1);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\treturn val;\n+}\n+\n+int mtk_snand_set_feature(struct mtk_snand *snf, uint32_t addr, uint32_t val)\n+{\n+\tuint8_t op[3];\n+\n+\top[0] = SNAND_CMD_SET_FEATURE;\n+\top[1] = (uint8_t)addr;\n+\top[2] = (uint8_t)val;\n+\n+\treturn mtk_snand_mac_io(snf, op, sizeof(op), NULL, 0);\n+}\n+\n+static int mtk_snand_poll_status(struct mtk_snand *snf, uint32_t wait_us)\n+{\n+\tint val;\n+\tmtk_snand_time_t time_start, tmo;\n+\n+\ttime_start = timer_get_ticks();\n+\ttmo = timer_time_to_tick(wait_us);\n+\n+\tdo {\n+\t\tval = mtk_snand_get_feature(snf, SNAND_FEATURE_STATUS_ADDR);\n+\t\tif (!(val & SNAND_STATUS_OIP))\n+\t\t\treturn val & (SNAND_STATUS_ERASE_FAIL |\n+\t\t\t\t      SNAND_STATUS_PROGRAM_FAIL);\n+\t} while (!timer_is_timeout(time_start, tmo));\n+\n+\treturn -ETIMEDOUT;\n+}\n+\n+int mtk_snand_chip_reset(struct mtk_snand *snf)\n+{\n+\tuint8_t op = SNAND_CMD_RESET;\n+\tint ret;\n+\n+\tret = mtk_snand_mac_io(snf, &op, 1, NULL, 0);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = mtk_snand_poll_status(snf, SNFI_POLL_INTERVAL);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\treturn 0;\n+}\n+\n+static int mtk_snand_config_feature(struct mtk_snand *snf, uint8_t clr,\n+\t\t\t\t    uint8_t set)\n+{\n+\tint val, newval;\n+\tint ret;\n+\n+\tval = mtk_snand_get_feature(snf, SNAND_FEATURE_CONFIG_ADDR);\n+\tif (val < 0) {\n+\t\tsnand_log_chip(snf->pdev,\n+\t\t\t       \"Failed to get configuration feature\\n\");\n+\t\treturn val;\n+\t}\n+\n+\tnewval = (val & (~clr)) | set;\n+\n+\tif (newval == val)\n+\t\treturn 0;\n+\n+\tret = mtk_snand_set_feature(snf, SNAND_FEATURE_CONFIG_ADDR,\n+\t\t\t\t    (uint8_t)newval);\n+\tif (val < 0) {\n+\t\tsnand_log_chip(snf->pdev,\n+\t\t\t       \"Failed to set configuration feature\\n\");\n+\t\treturn ret;\n+\t}\n+\n+\tval = mtk_snand_get_feature(snf, SNAND_FEATURE_CONFIG_ADDR);\n+\tif (val < 0) {\n+\t\tsnand_log_chip(snf->pdev,\n+\t\t\t       \"Failed to get configuration feature\\n\");\n+\t\treturn val;\n+\t}\n+\n+\tif (newval != val)\n+\t\treturn -ENOTSUPP;\n+\n+\treturn 0;\n+}\n+\n+static int mtk_snand_ondie_ecc_control(struct mtk_snand *snf, bool enable)\n+{\n+\tint ret;\n+\n+\tif (enable)\n+\t\tret = mtk_snand_config_feature(snf, 0, SNAND_FEATURE_ECC_EN);\n+\telse\n+\t\tret = mtk_snand_config_feature(snf, SNAND_FEATURE_ECC_EN, 0);\n+\n+\tif (ret) {\n+\t\tsnand_log_chip(snf->pdev, \"Failed to %s On-Die ECC engine\\n\",\n+\t\t\t       enable ? \"enable\" : \"disable\");\n+\t}\n+\n+\treturn ret;\n+}\n+\n+static int mtk_snand_qspi_control(struct mtk_snand *snf, bool enable)\n+{\n+\tint ret;\n+\n+\tif (enable) {\n+\t\tret = mtk_snand_config_feature(snf, 0,\n+\t\t\t\t\t       SNAND_FEATURE_QUAD_ENABLE);\n+\t} else {\n+\t\tret = mtk_snand_config_feature(snf,\n+\t\t\t\t\t       SNAND_FEATURE_QUAD_ENABLE, 0);\n+\t}\n+\n+\tif (ret) {\n+\t\tsnand_log_chip(snf->pdev, \"Failed to %s quad spi\\n\",\n+\t\t\t       enable ? \"enable\" : \"disable\");\n+\t}\n+\n+\treturn ret;\n+}\n+\n+static int mtk_snand_unlock(struct mtk_snand *snf)\n+{\n+\tint ret;\n+\n+\tret = mtk_snand_set_feature(snf, SNAND_FEATURE_PROTECT_ADDR, 0);\n+\tif (ret) {\n+\t\tsnand_log_chip(snf->pdev, \"Failed to set protection feature\\n\");\n+\t\treturn ret;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int mtk_snand_write_enable(struct mtk_snand *snf)\n+{\n+\tuint8_t op = SNAND_CMD_WRITE_ENABLE;\n+\tint ret, val;\n+\n+\tret = mtk_snand_mac_io(snf, &op, 1, NULL, 0);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tval = mtk_snand_get_feature(snf, SNAND_FEATURE_STATUS_ADDR);\n+\tif (val < 0)\n+\t\treturn ret;\n+\n+\tif (val & SNAND_STATUS_WEL)\n+\t\treturn 0;\n+\n+\tsnand_log_chip(snf->pdev, \"Failed to send write-enable command\\n\");\n+\n+\treturn -ENOTSUPP;\n+}\n+\n+static int mtk_snand_select_die(struct mtk_snand *snf, uint32_t dieidx)\n+{\n+\tif (!snf->select_die)\n+\t\treturn 0;\n+\n+\treturn snf->select_die(snf, dieidx);\n+}\n+\n+static uint64_t mtk_snand_select_die_address(struct mtk_snand *snf,\n+\t\t\t\t\t     uint64_t addr)\n+{\n+\tuint32_t dieidx;\n+\n+\tif (!snf->select_die)\n+\t\treturn addr;\n+\n+\tdieidx = addr >> snf->die_shift;\n+\n+\tmtk_snand_select_die(snf, dieidx);\n+\n+\treturn addr & snf->die_mask;\n+}\n+\n+static uint32_t mtk_snand_get_plane_address(struct mtk_snand *snf,\n+\t\t\t\t\t    uint32_t page)\n+{\n+\tuint32_t pages_per_block;\n+\n+\tpages_per_block = 1 << (snf->erasesize_shift - snf->writesize_shift);\n+\n+\tif (page & pages_per_block)\n+\t\treturn 1 << (snf->writesize_shift + 1);\n+\n+\treturn 0;\n+}\n+\n+static int mtk_snand_page_op(struct mtk_snand *snf, uint32_t page, uint8_t cmd)\n+{\n+\tuint8_t op[4];\n+\n+\top[0] = cmd;\n+\top[1] = (page >> 16) & 0xff;\n+\top[2] = (page >> 8) & 0xff;\n+\top[3] = page & 0xff;\n+\n+\treturn mtk_snand_mac_io(snf, op, sizeof(op), NULL, 0);\n+}\n+\n+static void mtk_snand_read_fdm(struct mtk_snand *snf, uint8_t *buf)\n+{\n+\tuint32_t vall, valm;\n+\tuint8_t *oobptr = buf;\n+\tint i, j;\n+\n+\tfor (i = 0; i < snf->ecc_steps; i++) {\n+\t\tvall = nfi_read32(snf, NFI_FDML(i));\n+\t\tvalm = nfi_read32(snf, NFI_FDMM(i));\n+\n+\t\tfor (j = 0; j < snf->nfi_soc->fdm_size; j++)\n+\t\t\toobptr[j] = (j >= 4 ? valm : vall) >> ((j % 4) * 8);\n+\n+\t\toobptr += snf->nfi_soc->fdm_size;\n+\t}\n+}\n+\n+static int mtk_snand_read_cache(struct mtk_snand *snf, uint32_t page, bool raw)\n+{\n+\tuint32_t coladdr, rwbytes, mode, len;\n+\tuintptr_t dma_addr;\n+\tint ret;\n+\n+\t/* Column address with plane bit */\n+\tcoladdr = mtk_snand_get_plane_address(snf, page);\n+\n+\tmtk_snand_mac_reset(snf);\n+\tmtk_nfi_reset(snf);\n+\n+\t/* Command and dummy cycles */\n+\tnfi_write32(snf, SNF_RD_CTL2,\n+\t\t    ((uint32_t)snf->dummy_rfc << DATA_READ_DUMMY_S) |\n+\t\t    (snf->opcode_rfc << DATA_READ_CMD_S));\n+\n+\t/* Column address */\n+\tnfi_write32(snf, SNF_RD_CTL3, coladdr);\n+\n+\t/* Set read mode */\n+\tmode = (uint32_t)snf->mode_rfc << DATA_READ_MODE_S;\n+\tnfi_rmw32(snf, SNF_MISC_CTL, DATA_READ_MODE, mode | DATARD_CUSTOM_EN);\n+\n+\t/* Set bytes to read */\n+\trwbytes = snf->ecc_steps * snf->raw_sector_size;\n+\tnfi_write32(snf, SNF_MISC_CTL2, (rwbytes << PROGRAM_LOAD_BYTE_NUM_S) |\n+\t\t    rwbytes);\n+\n+\t/* NFI read prepare */\n+\tmode = raw ? 0 : CNFG_HW_ECC_EN | CNFG_AUTO_FMT_EN;\n+\tnfi_write16(snf, NFI_CNFG, (CNFG_OP_MODE_CUST << CNFG_OP_MODE_S) |\n+\t\t    CNFG_DMA_BURST_EN | CNFG_READ_MODE | CNFG_DMA_MODE | mode);\n+\n+\tnfi_write32(snf, NFI_CON, (snf->ecc_steps << CON_SEC_NUM_S));\n+\n+\t/* Prepare for DMA read */\n+\tlen = snf->writesize + snf->oobsize;\n+\tret = dma_mem_map(snf->pdev, snf->page_cache, &dma_addr, len, false);\n+\tif (ret) {\n+\t\tsnand_log_nfi(snf->pdev,\n+\t\t\t      \"DMA map from device failed with %d\\n\", ret);\n+\t\treturn ret;\n+\t}\n+\n+\tnfi_write32(snf, NFI_STRADDR, (uint32_t)dma_addr);\n+\n+\tif (!raw)\n+\t\tmtk_snand_ecc_decoder_start(snf);\n+\n+\t/* Prepare for custom read interrupt */\n+\tnfi_write32(snf, NFI_INTR_EN, NFI_IRQ_INTR_EN | NFI_IRQ_CUS_READ);\n+\tirq_completion_init(snf->pdev);\n+\n+\t/* Trigger NFI into custom mode */\n+\tnfi_write16(snf, NFI_CMD, NFI_CMD_DUMMY_READ);\n+\n+\t/* Start DMA read */\n+\tnfi_rmw32(snf, NFI_CON, 0, CON_BRD);\n+\tnfi_write16(snf, NFI_STRDATA, STR_DATA);\n+\n+\t/* Wait for operation finished */\n+\tret = irq_completion_wait(snf->pdev, snf->nfi_base + SNF_STA_CTL1,\n+\t\t\t\t  CUS_READ_DONE, SNFI_POLL_INTERVAL);\n+\tif (ret) {\n+\t\tsnand_log_nfi(snf->pdev,\n+\t\t\t      \"DMA timed out for reading from cache\\n\");\n+\t\tgoto cleanup;\n+\t}\n+\n+\tif (!raw) {\n+\t\tret = mtk_ecc_wait_decoder_done(snf);\n+\t\tif (ret)\n+\t\t\tgoto cleanup;\n+\n+\t\tmtk_snand_read_fdm(snf, snf->page_cache + snf->writesize);\n+\n+\t\t/*\n+\t\t * For new IPs, ecc error may occur on empty pages.\n+\t\t * Use an specific indication bit to check empty page.\n+\t\t */\n+\t\tif (snf->nfi_soc->empty_page_check &&\n+\t\t    (nfi_read32(snf, NFI_STA) & READ_EMPTY))\n+\t\t\tret = 0;\n+\t\telse\n+\t\t\tret = mtk_ecc_check_decode_error(snf, page);\n+\n+\t\tmtk_snand_ecc_decoder_stop(snf);\n+\t}\n+\n+cleanup:\n+\t/* DMA cleanup */\n+\tdma_mem_unmap(snf->pdev, dma_addr, len, false);\n+\n+\t/* Stop read */\n+\tnfi_write32(snf, NFI_CON, 0);\n+\n+\t/* Clear SNF done flag */\n+\tnfi_rmw32(snf, SNF_STA_CTL1, 0, CUS_READ_DONE);\n+\tnfi_write32(snf, SNF_STA_CTL1, 0);\n+\n+\t/* Disable interrupt */\n+\tnfi_read32(snf, NFI_INTR_STA);\n+\tnfi_write32(snf, NFI_INTR_EN, 0);\n+\n+\tnfi_rmw32(snf, SNF_MISC_CTL, DATARD_CUSTOM_EN, 0);\n+\n+\treturn ret;\n+}\n+\n+static void mtk_snand_from_raw_page(struct mtk_snand *snf, void *buf, void *oob)\n+{\n+\tuint32_t i, ecc_bytes = snf->spare_per_sector - snf->nfi_soc->fdm_size;\n+\tuint8_t *eccptr = oob + snf->ecc_steps * snf->nfi_soc->fdm_size;\n+\tuint8_t *bufptr = buf, *oobptr = oob, *raw_sector;\n+\n+\tfor (i = 0; i < snf->ecc_steps; i++) {\n+\t\traw_sector = snf->page_cache + i * snf->raw_sector_size;\n+\n+\t\tif (buf) {\n+\t\t\tmemcpy(bufptr, raw_sector, snf->nfi_soc->sector_size);\n+\t\t\tbufptr += snf->nfi_soc->sector_size;\n+\t\t}\n+\n+\t\traw_sector += snf->nfi_soc->sector_size;\n+\n+\t\tif (oob) {\n+\t\t\tmemcpy(oobptr, raw_sector, snf->nfi_soc->fdm_size);\n+\t\t\toobptr += snf->nfi_soc->fdm_size;\n+\t\t\traw_sector += snf->nfi_soc->fdm_size;\n+\n+\t\t\tmemcpy(eccptr, raw_sector, ecc_bytes);\n+\t\t\teccptr += ecc_bytes;\n+\t\t}\n+\t}\n+}\n+\n+static int mtk_snand_do_read_page(struct mtk_snand *snf, uint64_t addr,\n+\t\t\t\t  void *buf, void *oob, bool raw, bool format)\n+{\n+\tuint64_t die_addr;\n+\tuint32_t page;\n+\tint ret;\n+\n+\tdie_addr = mtk_snand_select_die_address(snf, addr);\n+\tpage = die_addr >> snf->writesize_shift;\n+\n+\tret = mtk_snand_page_op(snf, page, SNAND_CMD_READ_TO_CACHE);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = mtk_snand_poll_status(snf, SNFI_POLL_INTERVAL);\n+\tif (ret < 0) {\n+\t\tsnand_log_chip(snf->pdev, \"Read to cache command timed out\\n\");\n+\t\treturn ret;\n+\t}\n+\n+\tret = mtk_snand_read_cache(snf, page, raw);\n+\tif (ret < 0 && ret != -EBADMSG)\n+\t\treturn ret;\n+\n+\tif (raw) {\n+\t\tif (format) {\n+\t\t\tmtk_snand_bm_swap_raw(snf);\n+\t\t\tmtk_snand_fdm_bm_swap_raw(snf);\n+\t\t\tmtk_snand_from_raw_page(snf, buf, oob);\n+\t\t} else {\n+\t\t\tif (buf)\n+\t\t\t\tmemcpy(buf, snf->page_cache, snf->writesize);\n+\n+\t\t\tif (oob) {\n+\t\t\t\tmemset(oob, 0xff, snf->oobsize);\n+\t\t\t\tmemcpy(oob, snf->page_cache + snf->writesize,\n+\t\t\t\t       snf->ecc_steps * snf->spare_per_sector);\n+\t\t\t}\n+\t\t}\n+\t} else {\n+\t\tmtk_snand_bm_swap(snf);\n+\t\tmtk_snand_fdm_bm_swap(snf);\n+\n+\t\tif (buf)\n+\t\t\tmemcpy(buf, snf->page_cache, snf->writesize);\n+\n+\t\tif (oob) {\n+\t\t\tmemset(oob, 0xff, snf->oobsize);\n+\t\t\tmemcpy(oob, snf->page_cache + snf->writesize,\n+\t\t\t       snf->ecc_steps * snf->nfi_soc->fdm_size);\n+\t\t}\n+\t}\n+\n+\treturn ret;\n+}\n+\n+int mtk_snand_read_page(struct mtk_snand *snf, uint64_t addr, void *buf,\n+\t\t\tvoid *oob, bool raw)\n+{\n+\tif (!snf || (!buf && !oob))\n+\t\treturn -EINVAL;\n+\n+\tif (addr >= snf->size)\n+\t\treturn -EINVAL;\n+\n+\treturn mtk_snand_do_read_page(snf, addr, buf, oob, raw, true);\n+}\n+\n+static void mtk_snand_write_fdm(struct mtk_snand *snf, const uint8_t *buf)\n+{\n+\tuint32_t vall, valm, fdm_size = snf->nfi_soc->fdm_size;\n+\tconst uint8_t *oobptr = buf;\n+\tint i, j;\n+\n+\tfor (i = 0; i < snf->ecc_steps; i++) {\n+\t\tvall = 0;\n+\t\tvalm = 0;\n+\n+\t\tfor (j = 0; j < 8; j++) {\n+\t\t\tif (j < 4)\n+\t\t\t\tvall |= (j < fdm_size ? oobptr[j] : 0xff)\n+\t\t\t\t\t\t<< (j * 8);\n+\t\t\telse\n+\t\t\t\tvalm |= (j < fdm_size ? oobptr[j] : 0xff)\n+\t\t\t\t\t\t<< ((j - 4) * 8);\n+\t\t}\n+\n+\t\tnfi_write32(snf, NFI_FDML(i), vall);\n+\t\tnfi_write32(snf, NFI_FDMM(i), valm);\n+\n+\t\toobptr += fdm_size;\n+\t}\n+}\n+\n+static int mtk_snand_program_load(struct mtk_snand *snf, uint32_t page,\n+\t\t\t\t  bool raw)\n+{\n+\tuint32_t coladdr, rwbytes, mode, len;\n+\tuintptr_t dma_addr;\n+\tint ret;\n+\n+\t/* Column address with plane bit */\n+\tcoladdr = mtk_snand_get_plane_address(snf, page);\n+\n+\tmtk_snand_mac_reset(snf);\n+\tmtk_nfi_reset(snf);\n+\n+\t/* Write FDM registers if necessary */\n+\tif (!raw)\n+\t\tmtk_snand_write_fdm(snf, snf->page_cache + snf->writesize);\n+\n+\t/* Command */\n+\tnfi_write32(snf, SNF_PG_CTL1, (snf->opcode_pl << PG_LOAD_CMD_S));\n+\n+\t/* Column address */\n+\tnfi_write32(snf, SNF_PG_CTL2, coladdr);\n+\n+\t/* Set write mode */\n+\tmode = snf->mode_pl ? PG_LOAD_X4_EN : 0;\n+\tnfi_rmw32(snf, SNF_MISC_CTL, PG_LOAD_X4_EN, mode | PG_LOAD_CUSTOM_EN);\n+\n+\t/* Set bytes to write */\n+\trwbytes = snf->ecc_steps * snf->raw_sector_size;\n+\tnfi_write32(snf, SNF_MISC_CTL2, (rwbytes << PROGRAM_LOAD_BYTE_NUM_S) |\n+\t\t    rwbytes);\n+\n+\t/* NFI write prepare */\n+\tmode = raw ? 0 : CNFG_HW_ECC_EN | CNFG_AUTO_FMT_EN;\n+\tnfi_write16(snf, NFI_CNFG, (CNFG_OP_MODE_PROGRAM << CNFG_OP_MODE_S) |\n+\t\t    CNFG_DMA_BURST_EN | CNFG_DMA_MODE | mode);\n+\n+\tnfi_write32(snf, NFI_CON, (snf->ecc_steps << CON_SEC_NUM_S));\n+\n+\t/* Prepare for DMA write */\n+\tlen = snf->writesize + snf->oobsize;\n+\tret = dma_mem_map(snf->pdev, snf->page_cache, &dma_addr, len, true);\n+\tif (ret) {\n+\t\tsnand_log_nfi(snf->pdev,\n+\t\t\t      \"DMA map to device failed with %d\\n\", ret);\n+\t\treturn ret;\n+\t}\n+\n+\tnfi_write32(snf, NFI_STRADDR, (uint32_t)dma_addr);\n+\n+\tif (!raw)\n+\t\tmtk_snand_ecc_encoder_start(snf);\n+\n+\t/* Prepare for custom write interrupt */\n+\tnfi_write32(snf, NFI_INTR_EN, NFI_IRQ_INTR_EN | NFI_IRQ_CUS_PG);\n+\tirq_completion_init(snf->pdev);\n+\n+\t/* Trigger NFI into custom mode */\n+\tnfi_write16(snf, NFI_CMD, NFI_CMD_DUMMY_WRITE);\n+\n+\t/* Start DMA write */\n+\tnfi_rmw32(snf, NFI_CON, 0, CON_BWR);\n+\tnfi_write16(snf, NFI_STRDATA, STR_DATA);\n+\n+\t/* Wait for operation finished */\n+\tret = irq_completion_wait(snf->pdev, snf->nfi_base + SNF_STA_CTL1,\n+\t\t\t\t  CUS_PG_DONE, SNFI_POLL_INTERVAL);\n+\tif (ret) {\n+\t\tsnand_log_nfi(snf->pdev,\n+\t\t\t      \"DMA timed out for program load\\n\");\n+\t\tgoto cleanup;\n+\t}\n+\n+\tif (!raw)\n+\t\tmtk_snand_ecc_encoder_stop(snf);\n+\n+cleanup:\n+\t/* DMA cleanup */\n+\tdma_mem_unmap(snf->pdev, dma_addr, len, true);\n+\n+\t/* Stop write */\n+\tnfi_write16(snf, NFI_CON, 0);\n+\n+\t/* Clear SNF done flag */\n+\tnfi_rmw32(snf, SNF_STA_CTL1, 0, CUS_PG_DONE);\n+\tnfi_write32(snf, SNF_STA_CTL1, 0);\n+\n+\t/* Disable interrupt */\n+\tnfi_read32(snf, NFI_INTR_STA);\n+\tnfi_write32(snf, NFI_INTR_EN, 0);\n+\n+\tnfi_rmw32(snf, SNF_MISC_CTL, PG_LOAD_CUSTOM_EN, 0);\n+\n+\treturn ret;\n+}\n+\n+static void mtk_snand_to_raw_page(struct mtk_snand *snf,\n+\t\t\t\t  const void *buf, const void *oob,\n+\t\t\t\t  bool empty_ecc)\n+{\n+\tuint32_t i, ecc_bytes = snf->spare_per_sector - snf->nfi_soc->fdm_size;\n+\tconst uint8_t *eccptr = oob + snf->ecc_steps * snf->nfi_soc->fdm_size;\n+\tconst uint8_t *bufptr = buf, *oobptr = oob;\n+\tuint8_t *raw_sector;\n+\n+\tmemset(snf->page_cache, 0xff, snf->writesize + snf->oobsize);\n+\tfor (i = 0; i < snf->ecc_steps; i++) {\n+\t\traw_sector = snf->page_cache + i * snf->raw_sector_size;\n+\n+\t\tif (buf) {\n+\t\t\tmemcpy(raw_sector, bufptr, snf->nfi_soc->sector_size);\n+\t\t\tbufptr += snf->nfi_soc->sector_size;\n+\t\t}\n+\n+\t\traw_sector += snf->nfi_soc->sector_size;\n+\n+\t\tif (oob) {\n+\t\t\tmemcpy(raw_sector, oobptr, snf->nfi_soc->fdm_size);\n+\t\t\toobptr += snf->nfi_soc->fdm_size;\n+\t\t\traw_sector += snf->nfi_soc->fdm_size;\n+\n+\t\t\tif (empty_ecc)\n+\t\t\t\tmemset(raw_sector, 0xff, ecc_bytes);\n+\t\t\telse\n+\t\t\t\tmemcpy(raw_sector, eccptr, ecc_bytes);\n+\t\t\teccptr += ecc_bytes;\n+\t\t}\n+\t}\n+}\n+\n+static bool mtk_snand_is_empty_page(struct mtk_snand *snf, const void *buf,\n+\t\t\t\t    const void *oob)\n+{\n+\tconst uint8_t *p = buf;\n+\tuint32_t i, j;\n+\n+\tif (buf) {\n+\t\tfor (i = 0; i < snf->writesize; i++) {\n+\t\t\tif (p[i] != 0xff)\n+\t\t\t\treturn false;\n+\t\t}\n+\t}\n+\n+\tif (oob) {\n+\t\tfor (j = 0; j < snf->ecc_steps; j++) {\n+\t\t\tp = oob + j * snf->nfi_soc->fdm_size;\n+\n+\t\t\tfor (i = 0; i < snf->nfi_soc->fdm_ecc_size; i++) {\n+\t\t\t\tif (p[i] != 0xff)\n+\t\t\t\t\treturn false;\n+\t\t\t}\n+\t\t}\n+\t}\n+\n+\treturn true;\n+}\n+\n+static int mtk_snand_do_write_page(struct mtk_snand *snf, uint64_t addr,\n+\t\t\t\t   const void *buf, const void *oob,\n+\t\t\t\t   bool raw, bool format)\n+{\n+\tuint64_t die_addr;\n+\tbool empty_ecc = false;\n+\tuint32_t page;\n+\tint ret;\n+\n+\tdie_addr = mtk_snand_select_die_address(snf, addr);\n+\tpage = die_addr >> snf->writesize_shift;\n+\n+\tif (!raw && mtk_snand_is_empty_page(snf, buf, oob)) {\n+\t\t/*\n+\t\t * If the data in the page to be ecc-ed is full 0xff,\n+\t\t * change to raw write mode\n+\t\t */\n+\t\traw = true;\n+\t\tformat = true;\n+\n+\t\t/* fill ecc parity code region with 0xff */\n+\t\tempty_ecc = true;\n+\t}\n+\n+\tif (raw) {\n+\t\tif (format) {\n+\t\t\tmtk_snand_to_raw_page(snf, buf, oob, empty_ecc);\n+\t\t\tmtk_snand_fdm_bm_swap_raw(snf);\n+\t\t\tmtk_snand_bm_swap_raw(snf);\n+\t\t} else {\n+\t\t\tmemset(snf->page_cache, 0xff,\n+\t\t\t       snf->writesize + snf->oobsize);\n+\n+\t\t\tif (buf)\n+\t\t\t\tmemcpy(snf->page_cache, buf, snf->writesize);\n+\n+\t\t\tif (oob) {\n+\t\t\t\tmemcpy(snf->page_cache + snf->writesize, oob,\n+\t\t\t\t       snf->ecc_steps * snf->spare_per_sector);\n+\t\t\t}\n+\t\t}\n+\t} else {\n+\t\tmemset(snf->page_cache, 0xff, snf->writesize + snf->oobsize);\n+\t\tif (buf)\n+\t\t\tmemcpy(snf->page_cache, buf, snf->writesize);\n+\n+\t\tif (oob) {\n+\t\t\tmemcpy(snf->page_cache + snf->writesize, oob,\n+\t\t\t       snf->ecc_steps * snf->nfi_soc->fdm_size);\n+\t\t}\n+\n+\t\tmtk_snand_fdm_bm_swap(snf);\n+\t\tmtk_snand_bm_swap(snf);\n+\t}\n+\n+\tret = mtk_snand_write_enable(snf);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = mtk_snand_program_load(snf, page, raw);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = mtk_snand_page_op(snf, page, SNAND_CMD_PROGRAM_EXECUTE);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = mtk_snand_poll_status(snf, SNFI_POLL_INTERVAL);\n+\tif (ret < 0) {\n+\t\tsnand_log_chip(snf->pdev,\n+\t\t\t       \"Page program command timed out on page %u\\n\",\n+\t\t\t       page);\n+\t\treturn ret;\n+\t}\n+\n+\tif (ret & SNAND_STATUS_PROGRAM_FAIL) {\n+\t\tsnand_log_chip(snf->pdev,\n+\t\t\t       \"Page program failed on page %u\\n\", page);\n+\t\treturn -EIO;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+int mtk_snand_write_page(struct mtk_snand *snf, uint64_t addr, const void *buf,\n+\t\t\t const void *oob, bool raw)\n+{\n+\tif (!snf || (!buf && !oob))\n+\t\treturn -EINVAL;\n+\n+\tif (addr >= snf->size)\n+\t\treturn -EINVAL;\n+\n+\treturn mtk_snand_do_write_page(snf, addr, buf, oob, raw, true);\n+}\n+\n+int mtk_snand_erase_block(struct mtk_snand *snf, uint64_t addr)\n+{\n+\tuint64_t die_addr;\n+\tuint32_t page, block;\n+\tint ret;\n+\n+\tif (!snf)\n+\t\treturn -EINVAL;\n+\n+\tif (addr >= snf->size)\n+\t\treturn -EINVAL;\n+\n+\tdie_addr = mtk_snand_select_die_address(snf, addr);\n+\tblock = die_addr >> snf->erasesize_shift;\n+\tpage = block << (snf->erasesize_shift - snf->writesize_shift);\n+\n+\tret = mtk_snand_write_enable(snf);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = mtk_snand_page_op(snf, page, SNAND_CMD_BLOCK_ERASE);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = mtk_snand_poll_status(snf, SNFI_POLL_INTERVAL);\n+\tif (ret < 0) {\n+\t\tsnand_log_chip(snf->pdev,\n+\t\t\t       \"Block erase command timed out on block %u\\n\",\n+\t\t\t       block);\n+\t\treturn ret;\n+\t}\n+\n+\tif (ret & SNAND_STATUS_ERASE_FAIL) {\n+\t\tsnand_log_chip(snf->pdev,\n+\t\t\t       \"Block erase failed on block %u\\n\", block);\n+\t\treturn -EIO;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int mtk_snand_block_isbad_std(struct mtk_snand *snf, uint64_t addr)\n+{\n+\tint ret;\n+\n+\tret = mtk_snand_do_read_page(snf, addr, NULL, snf->buf_cache, true,\n+\t\t\t\t     false);\n+\tif (ret && ret != -EBADMSG)\n+\t\treturn ret;\n+\n+\treturn snf->buf_cache[0] != 0xff;\n+}\n+\n+static int mtk_snand_block_isbad_mtk(struct mtk_snand *snf, uint64_t addr)\n+{\n+\tint ret;\n+\n+\tret = mtk_snand_do_read_page(snf, addr, NULL, snf->buf_cache, true,\n+\t\t\t\t     true);\n+\tif (ret && ret != -EBADMSG)\n+\t\treturn ret;\n+\n+\treturn snf->buf_cache[0] != 0xff;\n+}\n+\n+int mtk_snand_block_isbad(struct mtk_snand *snf, uint64_t addr)\n+{\n+\tif (!snf)\n+\t\treturn -EINVAL;\n+\n+\tif (addr >= snf->size)\n+\t\treturn -EINVAL;\n+\n+\taddr &= ~snf->erasesize_mask;\n+\n+\tif (snf->nfi_soc->bbm_swap)\n+\t\treturn mtk_snand_block_isbad_std(snf, addr);\n+\n+\treturn mtk_snand_block_isbad_mtk(snf, addr);\n+}\n+\n+static int mtk_snand_block_markbad_std(struct mtk_snand *snf, uint64_t addr)\n+{\n+\t/* Standard BBM position */\n+\tmemset(snf->buf_cache, 0xff, snf->oobsize);\n+\tsnf->buf_cache[0] = 0;\n+\n+\treturn mtk_snand_do_write_page(snf, addr, NULL, snf->buf_cache, true,\n+\t\t\t\t       false);\n+}\n+\n+static int mtk_snand_block_markbad_mtk(struct mtk_snand *snf, uint64_t addr)\n+{\n+\t/* Write the whole page with zeros */\n+\tmemset(snf->buf_cache, 0, snf->writesize + snf->oobsize);\n+\n+\treturn mtk_snand_do_write_page(snf, addr, snf->buf_cache,\n+\t\t\t\t       snf->buf_cache + snf->writesize, true,\n+\t\t\t\t       true);\n+}\n+\n+int mtk_snand_block_markbad(struct mtk_snand *snf, uint64_t addr)\n+{\n+\tif (!snf)\n+\t\treturn -EINVAL;\n+\n+\tif (addr >= snf->size)\n+\t\treturn -EINVAL;\n+\n+\taddr &= ~snf->erasesize_mask;\n+\n+\tif (snf->nfi_soc->bbm_swap)\n+\t\treturn mtk_snand_block_markbad_std(snf, addr);\n+\n+\treturn mtk_snand_block_markbad_mtk(snf, addr);\n+}\n+\n+int mtk_snand_fill_oob(struct mtk_snand *snf, uint8_t *oobraw,\n+\t\t       const uint8_t *oobbuf, size_t ooblen)\n+{\n+\tsize_t len = ooblen, sect_fdm_len;\n+\tconst uint8_t *oob = oobbuf;\n+\tuint32_t step = 0;\n+\n+\tif (!snf || !oobraw || !oob)\n+\t\treturn -EINVAL;\n+\n+\twhile (len && step < snf->ecc_steps) {\n+\t\tsect_fdm_len = snf->nfi_soc->fdm_size - 1;\n+\t\tif (sect_fdm_len > len)\n+\t\t\tsect_fdm_len = len;\n+\n+\t\tmemcpy(oobraw + step * snf->nfi_soc->fdm_size + 1, oob,\n+\t\t       sect_fdm_len);\n+\n+\t\tlen -= sect_fdm_len;\n+\t\toob += sect_fdm_len;\n+\t\tstep++;\n+\t}\n+\n+\treturn len;\n+}\n+\n+int mtk_snand_transfer_oob(struct mtk_snand *snf, uint8_t *oobbuf,\n+\t\t\t   size_t ooblen, const uint8_t *oobraw)\n+{\n+\tsize_t len = ooblen, sect_fdm_len;\n+\tuint8_t *oob = oobbuf;\n+\tuint32_t step = 0;\n+\n+\tif (!snf || !oobraw || !oob)\n+\t\treturn -EINVAL;\n+\n+\twhile (len && step < snf->ecc_steps) {\n+\t\tsect_fdm_len = snf->nfi_soc->fdm_size - 1;\n+\t\tif (sect_fdm_len > len)\n+\t\t\tsect_fdm_len = len;\n+\n+\t\tmemcpy(oob, oobraw + step * snf->nfi_soc->fdm_size + 1,\n+\t\t       sect_fdm_len);\n+\n+\t\tlen -= sect_fdm_len;\n+\t\toob += sect_fdm_len;\n+\t\tstep++;\n+\t}\n+\n+\treturn len;\n+}\n+\n+int mtk_snand_read_page_auto_oob(struct mtk_snand *snf, uint64_t addr,\n+\t\t\t\t void *buf, void *oob, size_t ooblen,\n+\t\t\t\t size_t *actualooblen, bool raw)\n+{\n+\tint ret, oobremain;\n+\n+\tif (!snf)\n+\t\treturn -EINVAL;\n+\n+\tif (!oob)\n+\t\treturn mtk_snand_read_page(snf, addr, buf, NULL, raw);\n+\n+\tret = mtk_snand_read_page(snf, addr, buf, snf->buf_cache, raw);\n+\tif (ret && ret != -EBADMSG) {\n+\t\tif (actualooblen)\n+\t\t\t*actualooblen = 0;\n+\t\treturn ret;\n+\t}\n+\n+\toobremain = mtk_snand_transfer_oob(snf, oob, ooblen, snf->buf_cache);\n+\tif (actualooblen)\n+\t\t*actualooblen = ooblen - oobremain;\n+\n+\treturn ret;\n+}\n+\n+int mtk_snand_write_page_auto_oob(struct mtk_snand *snf, uint64_t addr,\n+\t\t\t\t  const void *buf, const void *oob,\n+\t\t\t\t  size_t ooblen, size_t *actualooblen, bool raw)\n+{\n+\tint oobremain;\n+\n+\tif (!snf)\n+\t\treturn -EINVAL;\n+\n+\tif (!oob)\n+\t\treturn mtk_snand_write_page(snf, addr, buf, NULL, raw);\n+\n+\tmemset(snf->buf_cache, 0xff, snf->oobsize);\n+\toobremain = mtk_snand_fill_oob(snf, snf->buf_cache, oob, ooblen);\n+\tif (actualooblen)\n+\t\t*actualooblen = ooblen - oobremain;\n+\n+\treturn mtk_snand_write_page(snf, addr, buf, snf->buf_cache, raw);\n+}\n+\n+int mtk_snand_get_chip_info(struct mtk_snand *snf,\n+\t\t\t    struct mtk_snand_chip_info *info)\n+{\n+\tif (!snf || !info)\n+\t\treturn -EINVAL;\n+\n+\tinfo->model = snf->model;\n+\tinfo->chipsize = snf->size;\n+\tinfo->blocksize = snf->erasesize;\n+\tinfo->pagesize = snf->writesize;\n+\tinfo->sparesize = snf->oobsize;\n+\tinfo->spare_per_sector = snf->spare_per_sector;\n+\tinfo->fdm_size = snf->nfi_soc->fdm_size;\n+\tinfo->fdm_ecc_size = snf->nfi_soc->fdm_ecc_size;\n+\tinfo->num_sectors = snf->ecc_steps;\n+\tinfo->sector_size = snf->nfi_soc->sector_size;\n+\tinfo->ecc_strength = snf->ecc_strength;\n+\tinfo->ecc_bytes = snf->ecc_bytes;\n+\n+\treturn 0;\n+}\n+\n+int mtk_snand_irq_process(struct mtk_snand *snf)\n+{\n+\tuint32_t sta, ien;\n+\n+\tif (!snf)\n+\t\treturn -EINVAL;\n+\n+\tsta = nfi_read32(snf, NFI_INTR_STA);\n+\tien = nfi_read32(snf, NFI_INTR_EN);\n+\n+\tif (!(sta & ien))\n+\t\treturn 0;\n+\n+\tnfi_write32(snf, NFI_INTR_EN, 0);\n+\tirq_completion_done(snf->pdev);\n+\n+\treturn 1;\n+}\n+\n+static int mtk_snand_select_spare_per_sector(struct mtk_snand *snf)\n+{\n+\tuint32_t spare_per_step = snf->oobsize / snf->ecc_steps;\n+\tint i, mul = 1;\n+\n+\t/*\n+\t * If we're using the 1KB sector size, HW will automatically\n+\t * double the spare size. So we should only use half of the value.\n+\t */\n+\tif (snf->nfi_soc->sector_size == 1024)\n+\t\tmul = 2;\n+\n+\tspare_per_step /= mul;\n+\n+\tfor (i = snf->nfi_soc->num_spare_size - 1; i >= 0; i--) {\n+\t\tif (snf->nfi_soc->spare_sizes[i] <= spare_per_step) {\n+\t\t\tsnf->spare_per_sector = snf->nfi_soc->spare_sizes[i];\n+\t\t\tsnf->spare_per_sector *= mul;\n+\t\t\treturn i;\n+\t\t}\n+\t}\n+\n+\tsnand_log_nfi(snf->pdev,\n+\t\t      \"Page size %u+%u is not supported\\n\", snf->writesize,\n+\t\t      snf->oobsize);\n+\n+\treturn -1;\n+}\n+\n+static int mtk_snand_pagefmt_setup(struct mtk_snand *snf)\n+{\n+\tuint32_t spare_size_idx, spare_size_shift, pagesize_idx;\n+\tuint32_t sector_size_512;\n+\n+\tif (snf->nfi_soc->sector_size == 512) {\n+\t\tsector_size_512 = NFI_SEC_SEL_512;\n+\t\tspare_size_shift = NFI_SPARE_SIZE_S;\n+\t} else {\n+\t\tsector_size_512 = 0;\n+\t\tspare_size_shift = NFI_SPARE_SIZE_LS_S;\n+\t}\n+\n+\tswitch (snf->writesize) {\n+\tcase SZ_512:\n+\t\tpagesize_idx = NFI_PAGE_SIZE_512_2K;\n+\t\tbreak;\n+\tcase SZ_2K:\n+\t\tif (snf->nfi_soc->sector_size == 512)\n+\t\t\tpagesize_idx = NFI_PAGE_SIZE_2K_4K;\n+\t\telse\n+\t\t\tpagesize_idx = NFI_PAGE_SIZE_512_2K;\n+\t\tbreak;\n+\tcase SZ_4K:\n+\t\tif (snf->nfi_soc->sector_size == 512)\n+\t\t\tpagesize_idx = NFI_PAGE_SIZE_4K_8K;\n+\t\telse\n+\t\t\tpagesize_idx = NFI_PAGE_SIZE_2K_4K;\n+\t\tbreak;\n+\tcase SZ_8K:\n+\t\tif (snf->nfi_soc->sector_size == 512)\n+\t\t\tpagesize_idx = NFI_PAGE_SIZE_8K_16K;\n+\t\telse\n+\t\t\tpagesize_idx = NFI_PAGE_SIZE_4K_8K;\n+\t\tbreak;\n+\tcase SZ_16K:\n+\t\tpagesize_idx = NFI_PAGE_SIZE_8K_16K;\n+\t\tbreak;\n+\tdefault:\n+\t\tsnand_log_nfi(snf->pdev, \"Page size %u is not supported\\n\",\n+\t\t\t      snf->writesize);\n+\t\treturn -ENOTSUPP;\n+\t}\n+\n+\tspare_size_idx = mtk_snand_select_spare_per_sector(snf);\n+\tif (unlikely(spare_size_idx < 0))\n+\t\treturn -ENOTSUPP;\n+\n+\tsnf->raw_sector_size = snf->nfi_soc->sector_size +\n+\t\t\t       snf->spare_per_sector;\n+\n+\t/* Setup page format */\n+\tnfi_write32(snf, NFI_PAGEFMT,\n+\t\t    (snf->nfi_soc->fdm_ecc_size << NFI_FDM_ECC_NUM_S) |\n+\t\t    (snf->nfi_soc->fdm_size << NFI_FDM_NUM_S) |\n+\t\t    (spare_size_idx << spare_size_shift) |\n+\t\t    (pagesize_idx << NFI_PAGE_SIZE_S) |\n+\t\t    sector_size_512);\n+\n+\treturn 0;\n+}\n+\n+static enum snand_flash_io mtk_snand_select_opcode(struct mtk_snand *snf,\n+\t\t\t\t   uint32_t snfi_caps, uint8_t *opcode,\n+\t\t\t\t   uint8_t *dummy,\n+\t\t\t\t   const struct snand_io_cap *op_cap)\n+{\n+\tuint32_t i, caps;\n+\n+\tcaps = snfi_caps & op_cap->caps;\n+\n+\ti = fls(caps);\n+\tif (i > 0) {\n+\t\t*opcode = op_cap->opcodes[i - 1].opcode;\n+\t\tif (dummy)\n+\t\t\t*dummy = op_cap->opcodes[i - 1].dummy;\n+\t\treturn i - 1;\n+\t}\n+\n+\treturn __SNAND_IO_MAX;\n+}\n+\n+static int mtk_snand_select_opcode_rfc(struct mtk_snand *snf,\n+\t\t\t\t       uint32_t snfi_caps,\n+\t\t\t\t       const struct snand_io_cap *op_cap)\n+{\n+\tenum snand_flash_io idx;\n+\n+\tstatic const uint8_t rfc_modes[__SNAND_IO_MAX] = {\n+\t\t[SNAND_IO_1_1_1] = DATA_READ_MODE_X1,\n+\t\t[SNAND_IO_1_1_2] = DATA_READ_MODE_X2,\n+\t\t[SNAND_IO_1_2_2] = DATA_READ_MODE_DUAL,\n+\t\t[SNAND_IO_1_1_4] = DATA_READ_MODE_X4,\n+\t\t[SNAND_IO_1_4_4] = DATA_READ_MODE_QUAD,\n+\t};\n+\n+\tidx = mtk_snand_select_opcode(snf, snfi_caps, &snf->opcode_rfc,\n+\t\t\t\t      &snf->dummy_rfc, op_cap);\n+\tif (idx >= __SNAND_IO_MAX) {\n+\t\tsnand_log_snfi(snf->pdev,\n+\t\t\t       \"No capable opcode for read from cache\\n\");\n+\t\treturn -ENOTSUPP;\n+\t}\n+\n+\tsnf->mode_rfc = rfc_modes[idx];\n+\n+\tif (idx == SNAND_IO_1_1_4 || idx == SNAND_IO_1_4_4)\n+\t\tsnf->quad_spi_op = true;\n+\n+\treturn 0;\n+}\n+\n+static int mtk_snand_select_opcode_pl(struct mtk_snand *snf, uint32_t snfi_caps,\n+\t\t\t\t      const struct snand_io_cap *op_cap)\n+{\n+\tenum snand_flash_io idx;\n+\n+\tstatic const uint8_t pl_modes[__SNAND_IO_MAX] = {\n+\t\t[SNAND_IO_1_1_1] = 0,\n+\t\t[SNAND_IO_1_1_4] = 1,\n+\t};\n+\n+\tidx = mtk_snand_select_opcode(snf, snfi_caps, &snf->opcode_pl,\n+\t\t\t\t      NULL, op_cap);\n+\tif (idx >= __SNAND_IO_MAX) {\n+\t\tsnand_log_snfi(snf->pdev,\n+\t\t\t       \"No capable opcode for program load\\n\");\n+\t\treturn -ENOTSUPP;\n+\t}\n+\n+\tsnf->mode_pl = pl_modes[idx];\n+\n+\tif (idx == SNAND_IO_1_1_4)\n+\t\tsnf->quad_spi_op = true;\n+\n+\treturn 0;\n+}\n+\n+static int mtk_snand_setup(struct mtk_snand *snf,\n+\t\t\t   const struct snand_flash_info *snand_info)\n+{\n+\tconst struct snand_mem_org *memorg = &snand_info->memorg;\n+\tuint32_t i, msg_size, snfi_caps;\n+\tint ret;\n+\n+\t/* Calculate flash memory organization */\n+\tsnf->model = snand_info->model;\n+\tsnf->writesize = memorg->pagesize;\n+\tsnf->oobsize = memorg->sparesize;\n+\tsnf->erasesize = snf->writesize * memorg->pages_per_block;\n+\tsnf->die_size = (uint64_t)snf->erasesize * memorg->blocks_per_die;\n+\tsnf->size = snf->die_size * memorg->ndies;\n+\tsnf->num_dies = memorg->ndies;\n+\n+\tsnf->writesize_mask = snf->writesize - 1;\n+\tsnf->erasesize_mask = snf->erasesize - 1;\n+\tsnf->die_mask = snf->die_size - 1;\n+\n+\tsnf->writesize_shift = ffs(snf->writesize) - 1;\n+\tsnf->erasesize_shift = ffs(snf->erasesize) - 1;\n+\tsnf->die_shift = mtk_snand_ffs64(snf->die_size) - 1;\n+\n+\tsnf->select_die = snand_info->select_die;\n+\n+\t/* Determine opcodes for read from cache/program load */\n+\tsnfi_caps = SPI_IO_1_1_1 | SPI_IO_1_1_2 | SPI_IO_1_2_2;\n+\tif (snf->snfi_quad_spi)\n+\t\tsnfi_caps |= SPI_IO_1_1_4 | SPI_IO_1_4_4;\n+\n+\tret = mtk_snand_select_opcode_rfc(snf, snfi_caps, snand_info->cap_rd);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = mtk_snand_select_opcode_pl(snf, snfi_caps, snand_info->cap_pl);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\t/* ECC and page format */\n+\tsnf->ecc_steps = snf->writesize / snf->nfi_soc->sector_size;\n+\tif (snf->ecc_steps > snf->nfi_soc->max_sectors) {\n+\t\tsnand_log_nfi(snf->pdev, \"Page size %u is not supported\\n\",\n+\t\t\t      snf->writesize);\n+\t\treturn -ENOTSUPP;\n+\t}\n+\n+\tret = mtk_snand_pagefmt_setup(snf);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tmsg_size = snf->nfi_soc->sector_size + snf->nfi_soc->fdm_ecc_size;\n+\tret = mtk_ecc_setup(snf, snf->nfi_base + NFI_FDM0L,\n+\t\t\t    snf->spare_per_sector - snf->nfi_soc->fdm_size,\n+\t\t\t    msg_size);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tnfi_write16(snf, NFI_CNFG, 0);\n+\n+\t/* Tuning options */\n+\tnfi_write16(snf, NFI_DEBUG_CON1, WBUF_EN);\n+\tnfi_write32(snf, SNF_DLY_CTL3, (40 << SFCK_SAM_DLY_S));\n+\n+\t/* Interrupts */\n+\tnfi_read32(snf, NFI_INTR_STA);\n+\tnfi_write32(snf, NFI_INTR_EN, 0);\n+\n+\t/* Clear SNF done flag */\n+\tnfi_rmw32(snf, SNF_STA_CTL1, 0, CUS_READ_DONE | CUS_PG_DONE);\n+\tnfi_write32(snf, SNF_STA_CTL1, 0);\n+\n+\t/* Initialization on all dies */\n+\tfor (i = 0; i < snf->num_dies; i++) {\n+\t\tmtk_snand_select_die(snf, i);\n+\n+\t\t/* Disable On-Die ECC engine */\n+\t\tret = mtk_snand_ondie_ecc_control(snf, false);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\n+\t\t/* Disable block protection */\n+\t\tmtk_snand_unlock(snf);\n+\n+\t\t/* Enable/disable quad-spi */\n+\t\tmtk_snand_qspi_control(snf, snf->quad_spi_op);\n+\t}\n+\n+\tmtk_snand_select_die(snf, 0);\n+\n+\treturn 0;\n+}\n+\n+static int mtk_snand_id_probe(struct mtk_snand *snf,\n+\t\t\t      const struct snand_flash_info **snand_info)\n+{\n+\tuint8_t id[4], op[2];\n+\tint ret;\n+\n+\t/* Read SPI-NAND JEDEC ID, OP + dummy/addr + ID */\n+\top[0] = SNAND_CMD_READID;\n+\top[1] = 0;\n+\tret = mtk_snand_mac_io(snf, op, 2, id, sizeof(id));\n+\tif (ret)\n+\t\treturn ret;\n+\n+\t*snand_info = snand_flash_id_lookup(SNAND_ID_DYMMY, id);\n+\tif (*snand_info)\n+\t\treturn 0;\n+\n+\t/* Read SPI-NAND JEDEC ID, OP + ID */\n+\top[0] = SNAND_CMD_READID;\n+\tret = mtk_snand_mac_io(snf, op, 1, id, sizeof(id));\n+\tif (ret)\n+\t\treturn ret;\n+\n+\t*snand_info = snand_flash_id_lookup(SNAND_ID_DYMMY, id);\n+\tif (*snand_info)\n+\t\treturn 0;\n+\n+\tsnand_log_chip(snf->pdev,\n+\t\t       \"Unrecognized SPI-NAND ID: %02x %02x %02x %02x\\n\",\n+\t\t       id[0], id[1], id[2], id[3]);\n+\n+\treturn -EINVAL;\n+}\n+\n+int mtk_snand_init(void *dev, const struct mtk_snand_platdata *pdata,\n+\t\t   struct mtk_snand **psnf)\n+{\n+\tconst struct snand_flash_info *snand_info;\n+\tstruct mtk_snand tmpsnf, *snf;\n+\tuint32_t rawpage_size;\n+\tint ret;\n+\n+\tif (!pdata || !psnf)\n+\t\treturn -EINVAL;\n+\n+\tif (pdata->soc >= __SNAND_SOC_MAX) {\n+\t\tsnand_log_chip(dev, \"Invalid SOC %u for MTK-SNAND\\n\",\n+\t\t\t       pdata->soc);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\t/* Dummy instance only for initial reset and id probe */\n+\ttmpsnf.nfi_base = pdata->nfi_base;\n+\ttmpsnf.ecc_base = pdata->ecc_base;\n+\ttmpsnf.soc = pdata->soc;\n+\ttmpsnf.nfi_soc = &mtk_snand_socs[pdata->soc];\n+\ttmpsnf.pdev = dev;\n+\n+\t/* Switch to SNFI mode */\n+\twritel(SPI_MODE, tmpsnf.nfi_base + SNF_CFG);\n+\n+\t/* Reset SNFI & NFI */\n+\tmtk_snand_mac_reset(&tmpsnf);\n+\tmtk_nfi_reset(&tmpsnf);\n+\n+\t/* Reset SPI-NAND chip */\n+\tret = mtk_snand_chip_reset(&tmpsnf);\n+\tif (ret) {\n+\t\tsnand_log_chip(dev, \"Failed to reset SPI-NAND chip\\n\");\n+\t\treturn ret;\n+\t}\n+\n+\t/* Probe SPI-NAND flash by JEDEC ID */\n+\tret = mtk_snand_id_probe(&tmpsnf, &snand_info);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\trawpage_size = snand_info->memorg.pagesize +\n+\t\t       snand_info->memorg.sparesize;\n+\n+\t/* Allocate memory for instance and cache */\n+\tsnf = generic_mem_alloc(dev, sizeof(*snf) + rawpage_size);\n+\tif (!snf) {\n+\t\tsnand_log_chip(dev, \"Failed to allocate memory for instance\\n\");\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\tsnf->buf_cache = (uint8_t *)((uintptr_t)snf + sizeof(*snf));\n+\n+\t/* Allocate memory for DMA buffer */\n+\tsnf->page_cache = dma_mem_alloc(dev, rawpage_size);\n+\tif (!snf->page_cache) {\n+\t\tgeneric_mem_free(dev, snf);\n+\t\tsnand_log_chip(dev,\n+\t\t\t       \"Failed to allocate memory for DMA buffer\\n\");\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\t/* Fill up instance */\n+\tsnf->pdev = dev;\n+\tsnf->nfi_base = pdata->nfi_base;\n+\tsnf->ecc_base = pdata->ecc_base;\n+\tsnf->soc = pdata->soc;\n+\tsnf->nfi_soc = &mtk_snand_socs[pdata->soc];\n+\tsnf->snfi_quad_spi = pdata->quad_spi;\n+\n+\t/* Initialize SNFI & ECC engine */\n+\tret = mtk_snand_setup(snf, snand_info);\n+\tif (ret) {\n+\t\tdma_mem_free(dev, snf->page_cache);\n+\t\tgeneric_mem_free(dev, snf);\n+\t\treturn ret;\n+\t}\n+\n+\t*psnf = snf;\n+\n+\treturn 0;\n+}\n+\n+int mtk_snand_cleanup(struct mtk_snand *snf)\n+{\n+\tif (!snf)\n+\t\treturn 0;\n+\n+\tdma_mem_free(snf->pdev, snf->page_cache);\n+\tgeneric_mem_free(snf->pdev, snf);\n+\n+\treturn 0;\n+}\n--- /dev/null\n+++ b/drivers/mtd/mtk-snand/mtk-snand.h\n@@ -0,0 +1,77 @@\n+/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */\n+/*\n+ * Copyright (C) 2020 MediaTek Inc. All Rights Reserved.\n+ *\n+ * Author: Weijie Gao <weijie.gao@mediatek.com>\n+ */\n+\n+#ifndef _MTK_SNAND_H_\n+#define _MTK_SNAND_H_\n+\n+#ifndef PRIVATE_MTK_SNAND_HEADER\n+#include <stddef.h>\n+#include <stdint.h>\n+#include <stdbool.h>\n+#endif\n+\n+enum mtk_snand_soc {\n+\tSNAND_SOC_MT7622,\n+\tSNAND_SOC_MT7629,\n+\tSNAND_SOC_MT7986,\n+\n+\t__SNAND_SOC_MAX\n+};\n+\n+struct mtk_snand_platdata {\n+\tvoid *nfi_base;\n+\tvoid *ecc_base;\n+\tenum mtk_snand_soc soc;\n+\tbool quad_spi;\n+};\n+\n+struct mtk_snand_chip_info {\n+\tconst char *model;\n+\tuint64_t chipsize;\n+\tuint32_t blocksize;\n+\tuint32_t pagesize;\n+\tuint32_t sparesize;\n+\tuint32_t spare_per_sector;\n+\tuint32_t fdm_size;\n+\tuint32_t fdm_ecc_size;\n+\tuint32_t num_sectors;\n+\tuint32_t sector_size;\n+\tuint32_t ecc_strength;\n+\tuint32_t ecc_bytes;\n+};\n+\n+struct mtk_snand;\n+struct snand_flash_info;\n+\n+int mtk_snand_init(void *dev, const struct mtk_snand_platdata *pdata,\n+\t\t   struct mtk_snand **psnf);\n+int mtk_snand_cleanup(struct mtk_snand *snf);\n+\n+int mtk_snand_chip_reset(struct mtk_snand *snf);\n+int mtk_snand_read_page(struct mtk_snand *snf, uint64_t addr, void *buf,\n+\t\t\tvoid *oob, bool raw);\n+int mtk_snand_write_page(struct mtk_snand *snf, uint64_t addr, const void *buf,\n+\t\t\t const void *oob, bool raw);\n+int mtk_snand_erase_block(struct mtk_snand *snf, uint64_t addr);\n+int mtk_snand_block_isbad(struct mtk_snand *snf, uint64_t addr);\n+int mtk_snand_block_markbad(struct mtk_snand *snf, uint64_t addr);\n+int mtk_snand_fill_oob(struct mtk_snand *snf, uint8_t *oobraw,\n+\t\t       const uint8_t *oobbuf, size_t ooblen);\n+int mtk_snand_transfer_oob(struct mtk_snand *snf, uint8_t *oobbuf,\n+\t\t\t   size_t ooblen, const uint8_t *oobraw);\n+int mtk_snand_read_page_auto_oob(struct mtk_snand *snf, uint64_t addr,\n+\t\t\t\t void *buf, void *oob, size_t ooblen,\n+\t\t\t\t size_t *actualooblen, bool raw);\n+int mtk_snand_write_page_auto_oob(struct mtk_snand *snf, uint64_t addr,\n+\t\t\t\t  const void *buf, const void *oob,\n+\t\t\t\t  size_t ooblen, size_t *actualooblen,\n+\t\t\t\t  bool raw);\n+int mtk_snand_get_chip_info(struct mtk_snand *snf,\n+\t\t\t    struct mtk_snand_chip_info *info);\n+int mtk_snand_irq_process(struct mtk_snand *snf);\n+\n+#endif /* _MTK_SNAND_H_ */\n"
  },
  {
    "path": "package/boot/uboot-mediatek/patches/000-mtk-15-mtd-mtk-snand-add-support-for-SPL.patch",
    "content": "From b7fb0e0674db12bcf53df4b107a17c80758ee5d3 Mon Sep 17 00:00:00 2001\nFrom: Weijie Gao <weijie.gao@mediatek.com>\nDate: Wed, 3 Mar 2021 08:57:29 +0800\nSubject: [PATCH 05/12] mtd: mtk-snand: add support for SPL\n\nAdd support to initialize SPI-NAND in SPL.\nAdd implementation for SPL NAND loader.\n\nSigned-off-by: Weijie Gao <weijie.gao@mediatek.com>\n---\n drivers/mtd/mtk-snand/Kconfig         |   6 ++\n drivers/mtd/mtk-snand/Makefile        |   4 +\n drivers/mtd/mtk-snand/mtk-snand-spl.c | 132 ++++++++++++++++++++++++++\n 3 files changed, 142 insertions(+)\n create mode 100644 drivers/mtd/mtk-snand/mtk-snand-spl.c\n\n--- a/drivers/mtd/mtk-snand/Kconfig\n+++ b/drivers/mtd/mtk-snand/Kconfig\n@@ -19,3 +19,9 @@ config MTK_SPI_NAND_MTD\n \thelp\n \t  This option enables access to SPI-NAND flashes through the\n \t  MTD interface of MediaTek SPI NAND Flash Controller\n+\n+config SPL_MTK_SPI_NAND\n+\ttristate \"SPL support for MediaTek SPI NAND flash controller\"\n+\tdepends on MTK_SPI_NAND\n+\thelp\n+\t  This option enables access to SPI-NAND flashes in the SPL stage\n--- a/drivers/mtd/mtk-snand/Makefile\n+++ b/drivers/mtd/mtk-snand/Makefile\n@@ -8,4 +8,8 @@\n obj-y += mtk-snand.o mtk-snand-ecc.o mtk-snand-ids.o mtk-snand-os.o\n obj-$(CONFIG_MTK_SPI_NAND_MTD) += mtk-snand-mtd.o\n \n+ifdef CONFIG_SPL_BUILD\n+obj-$(CONFIG_SPL_MTK_SPI_NAND) += mtk-snand-spl.o\n+endif\n+\n ccflags-y += -DPRIVATE_MTK_SNAND_HEADER\n--- /dev/null\n+++ b/drivers/mtd/mtk-snand/mtk-snand-spl.c\n@@ -0,0 +1,132 @@\n+// SPDX-License-Identifier: GPL-2.0\n+/*\n+ * Copyright (C) 2020 MediaTek Inc. All Rights Reserved.\n+ *\n+ * Author: Weijie Gao <weijie.gao@mediatek.com>\n+ */\n+\n+#include <common.h>\n+#include <dm.h>\n+#include <dm/uclass.h>\n+#include <malloc.h>\n+#include <mapmem.h>\n+#include <mtd.h>\n+#include <watchdog.h>\n+\n+#include \"mtk-snand.h\"\n+\n+static struct mtk_snand *snf;\n+static struct mtk_snand_chip_info cinfo;\n+static u32 oobavail;\n+\n+static u8 *page_cache;\n+\n+int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst)\n+{\n+\tu32 sizeremain = size, chunksize, leading;\n+\tuint32_t off = offs, writesize_mask = cinfo.pagesize - 1;\n+\tuint8_t *ptr = dst;\n+\tint ret;\n+\n+\tif (!snf)\n+\t\treturn -ENODEV;\n+\n+\twhile (sizeremain) {\n+\t\tWATCHDOG_RESET();\n+\n+\t\tleading = off & writesize_mask;\n+\t\tchunksize = cinfo.pagesize - leading;\n+\t\tif (chunksize > sizeremain)\n+\t\t\tchunksize = sizeremain;\n+\n+\t\tif (chunksize == cinfo.pagesize) {\n+\t\t\tret = mtk_snand_read_page(snf, off - leading, ptr,\n+\t\t\t\t\t\t  NULL, false);\n+\t\t\tif (ret)\n+\t\t\t\tbreak;\n+\t\t} else {\n+\t\t\tret = mtk_snand_read_page(snf, off - leading,\n+\t\t\t\t\t\t  page_cache, NULL, false);\n+\t\t\tif (ret)\n+\t\t\t\tbreak;\n+\n+\t\t\tmemcpy(ptr, page_cache + leading, chunksize);\n+\t\t}\n+\n+\t\toff += chunksize;\n+\t\tptr += chunksize;\n+\t\tsizeremain -= chunksize;\n+\t}\n+\n+\treturn ret;\n+}\n+\n+void nand_init(void)\n+{\n+\tstruct mtk_snand_platdata mtk_snand_pdata = {};\n+\tstruct udevice *dev;\n+\tfdt_addr_t base;\n+\tint ret;\n+\n+\tret = uclass_get_device_by_driver(UCLASS_MTD, DM_DRIVER_GET(mtk_snand),\n+\t\t\t\t\t  &dev);\n+\tif (ret) {\n+\t\tprintf(\"mtk-snand-spl: Device instance not found!\\n\");\n+\t\treturn;\n+\t}\n+\n+\tbase = dev_read_addr_name(dev, \"nfi\");\n+\tif (base == FDT_ADDR_T_NONE) {\n+\t\tprintf(\"mtk-snand-spl: NFI base not set\\n\");\n+\t\treturn;\n+\t}\n+\tmtk_snand_pdata.nfi_base = map_sysmem(base, 0);\n+\n+\tbase = dev_read_addr_name(dev, \"ecc\");\n+\tif (base == FDT_ADDR_T_NONE) {\n+\t\tprintf(\"mtk-snand-spl: ECC base not set\\n\");\n+\t\treturn;\n+\t}\n+\tmtk_snand_pdata.ecc_base = map_sysmem(base, 0);\n+\n+\tmtk_snand_pdata.soc = dev_get_driver_data(dev);\n+\tmtk_snand_pdata.quad_spi = dev_read_bool(dev, \"quad-spi\");\n+\n+\tret = mtk_snand_init(NULL, &mtk_snand_pdata, &snf);\n+\tif (ret) {\n+\t\tprintf(\"mtk-snand-spl: failed to initialize SPI-NAND\\n\");\n+\t\treturn;\n+\t}\n+\n+\tmtk_snand_get_chip_info(snf, &cinfo);\n+\n+\toobavail = cinfo.num_sectors * (cinfo.fdm_size - 1);\n+\n+\tprintf(\"SPI-NAND: %s (%uMB)\\n\", cinfo.model,\n+\t       (u32)(cinfo.chipsize >> 20));\n+\n+\tpage_cache = malloc(cinfo.pagesize + cinfo.sparesize);\n+\tif (!page_cache) {\n+\t\tmtk_snand_cleanup(snf);\n+\t\tprintf(\"mtk-snand-spl: failed to allocate page cache\\n\");\n+\t}\n+}\n+\n+void nand_deselect(void)\n+{\n+\n+}\n+\n+static const struct udevice_id mtk_snand_ids[] = {\n+\t{ .compatible = \"mediatek,mt7622-snand\", .data = SNAND_SOC_MT7622 },\n+\t{ .compatible = \"mediatek,mt7629-snand\", .data = SNAND_SOC_MT7629 },\n+\t{ .compatible = \"mediatek,mt7986-snand\", .data = SNAND_SOC_MT7986 },\n+\t{ /* sentinel */ },\n+};\n+\n+U_BOOT_DRIVER(mtk_snand) = {\n+\t.name = \"mtk-snand\",\n+\t.id = UCLASS_MTD,\n+\t.of_match = mtk_snand_ids,\n+\t.flags = DM_FLAG_PRE_RELOC,\n+};\n"
  },
  {
    "path": "package/boot/uboot-mediatek/patches/000-mtk-16-env-add-support-for-generic-MTD-device.patch",
    "content": "From a26620ec83fa3077f0c261046e82091f7455736f Mon Sep 17 00:00:00 2001\nFrom: Weijie Gao <weijie.gao@mediatek.com>\nDate: Wed, 3 Mar 2021 10:11:32 +0800\nSubject: [PATCH 06/12] env: add support for generic MTD device\n\nAdd an env driver for generic MTD device.\n\nSigned-off-by: Weijie Gao <weijie.gao@mediatek.com>\n---\n cmd/nvedit.c           |   3 +-\n env/Kconfig            |  37 +++++-\n env/Makefile           |   1 +\n env/env.c              |   3 +\n env/mtd.c              | 256 +++++++++++++++++++++++++++++++++++++++++\n include/env_internal.h |   1 +\n tools/Makefile         |   1 +\n 7 files changed, 299 insertions(+), 3 deletions(-)\n create mode 100644 env/mtd.c\n\n--- a/cmd/nvedit.c\n+++ b/cmd/nvedit.c\n@@ -48,6 +48,7 @@ DECLARE_GLOBAL_DATA_PTR;\n \tdefined(CONFIG_ENV_IS_IN_MMC)\t\t|| \\\n \tdefined(CONFIG_ENV_IS_IN_FAT)\t\t|| \\\n \tdefined(CONFIG_ENV_IS_IN_EXT4)\t\t|| \\\n+\tdefined(CONFIG_ENV_IS_IN_MTD)\t\t|| \\\n \tdefined(CONFIG_ENV_IS_IN_NAND)\t\t|| \\\n \tdefined(CONFIG_ENV_IS_IN_NVRAM)\t\t|| \\\n \tdefined(CONFIG_ENV_IS_IN_ONENAND)\t|| \\\n@@ -62,7 +63,7 @@ DECLARE_GLOBAL_DATA_PTR;\n \n #if\t!defined(ENV_IS_IN_DEVICE)\t\t&& \\\n \t!defined(CONFIG_ENV_IS_NOWHERE)\n-# error Define one of CONFIG_ENV_IS_IN_{EEPROM|FLASH|MMC|FAT|EXT4|\\\n+# error Define one of CONFIG_ENV_IS_IN_{EEPROM|FLASH|MMC|FAT|EXT4|MTD|\\\n NAND|NVRAM|ONENAND|SATA|SPI_FLASH|REMOTE|UBI} or CONFIG_ENV_IS_NOWHERE\n #endif\n \n--- a/env/Kconfig\n+++ b/env/Kconfig\n@@ -19,7 +19,7 @@ config ENV_IS_NOWHERE\n \t\t     !ENV_IS_IN_MMC && !ENV_IS_IN_NAND && \\\n \t\t     !ENV_IS_IN_NVRAM && !ENV_IS_IN_ONENAND && \\\n \t\t     !ENV_IS_IN_REMOTE && !ENV_IS_IN_SPI_FLASH && \\\n-\t\t     !ENV_IS_IN_UBI\n+\t\t     !ENV_IS_IN_UBI && !ENV_IS_IN_MTD\n \thelp\n \t  Define this if you don't want to or can't have an environment stored\n \t  on a storage medium. In this case the environment will still exist\n@@ -208,6 +208,27 @@ config ENV_IS_IN_MMC\n \t  This value is also in units of bytes, but must also be aligned to\n \t  an MMC sector boundary.\n \n+config ENV_IS_IN_MTD\n+\tbool \"Environment in a MTD device\"\n+\tdepends on !CHAIN_OF_TRUST\n+\tdepends on MTD\n+\thelp\n+\t  Define this if you have a MTD device which you want to use for\n+\t  the environment.\n+\n+\t  - CONFIG_ENV_MTD_NAME:\n+\t  - CONFIG_ENV_OFFSET:\n+\t  - CONFIG_ENV_SIZE:\n+\n+\t  These three #defines specify the MTD device where the environment\n+\t  is stored, offset and size of the environment area within the MTD\n+\t  device. CONFIG_ENV_OFFSET must be aligned to an erase block boundary.\n+\n+\t  - CONFIG_ENV_SIZE_REDUND:\n+\n+\t  This #define specify the maximum size allowed for read/write/erase\n+\t  with skipped bad blocks starting from ENV_OFFSET.\n+\n config ENV_IS_IN_NAND\n \tbool \"Environment in a NAND device\"\n \tdepends on !CHAIN_OF_TRUST\n@@ -535,10 +556,16 @@ config ENV_ADDR_REDUND\n \t  Offset from the start of the device (or partition) of the redundant\n \t  environment location.\n \n+config ENV_MTD_NAME\n+\tstring \"Name of the MTD device storing the environment\"\n+\tdepends on ENV_IS_IN_MTD\n+\thelp\n+\t  Name of the MTD device that stores the environment\n+\n config ENV_OFFSET\n \thex \"Environment offset\"\n \tdepends on ENV_IS_IN_EEPROM || ENV_IS_IN_MMC || ENV_IS_IN_NAND || \\\n-\t\t    ENV_IS_IN_SPI_FLASH\n+\t\t    ENV_IS_IN_SPI_FLASH || ENV_IS_IN_MTD\n \tdefault 0x3f8000 if ARCH_ROCKCHIP && ENV_IS_IN_MMC\n \tdefault 0x140000 if ARCH_ROCKCHIP && ENV_IS_IN_SPI_FLASH\n \tdefault 0x88000 if ARCH_SUNXI\n@@ -583,6 +610,12 @@ config ENV_SECT_SIZE\n \thelp\n \t  Size of the sector containing the environment.\n \n+config ENV_SIZE_REDUND\n+\thex \"Redundant environment size\"\n+\tdepends on ENV_IS_IN_MTD\n+\thelp\n+\t  The maximum size allowed for read/write/erase with skipped bad blocks.\n+\n config ENV_UBI_PART\n \tstring \"UBI partition name\"\n \tdepends on ENV_IS_IN_UBI\n--- a/env/Makefile\n+++ b/env/Makefile\n@@ -26,6 +26,7 @@ obj-$(CONFIG_$(SPL_TPL_)ENV_IS_NOWHERE)\n obj-$(CONFIG_$(SPL_TPL_)ENV_IS_IN_MMC) += mmc.o\n obj-$(CONFIG_$(SPL_TPL_)ENV_IS_IN_FAT) += fat.o\n obj-$(CONFIG_$(SPL_TPL_)ENV_IS_IN_EXT4) += ext4.o\n+obj-$(CONFIG_$(SPL_TPL_)ENV_IS_IN_MTD) += mtd.o\n obj-$(CONFIG_$(SPL_TPL_)ENV_IS_IN_NAND) += nand.o\n obj-$(CONFIG_$(SPL_TPL_)ENV_IS_IN_SPI_FLASH) += sf.o\n obj-$(CONFIG_$(SPL_TPL_)ENV_IS_IN_FLASH) += flash.o\n--- a/env/env.c\n+++ b/env/env.c\n@@ -69,6 +69,9 @@ static enum env_location env_locations[]\n #ifdef CONFIG_ENV_IS_IN_MMC\n \tENVL_MMC,\n #endif\n+#ifdef CONFIG_ENV_IS_IN_MTD\n+\tENVL_MTD,\n+#endif\n #ifdef CONFIG_ENV_IS_IN_NAND\n \tENVL_NAND,\n #endif\n--- /dev/null\n+++ b/env/mtd.c\n@@ -0,0 +1,256 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+/*\n+ * Copyright (C) 2021 MediaTek Inc. All Rights Reserved.\n+ *\n+ * Author: Weijie Gao <weijie.gao@mediatek.com>\n+ */\n+\n+#include <command.h>\n+#include <env.h>\n+#include <env_internal.h>\n+#include <errno.h>\n+#include <linux/kernel.h>\n+#include <linux/stddef.h>\n+#include <linux/types.h>\n+#include <linux/mtd/mtd.h>\n+#include <malloc.h>\n+#include <memalign.h>\n+#include <mtd.h>\n+#include <search.h>\n+\n+#if CONFIG_ENV_SIZE_REDUND < CONFIG_ENV_SIZE\n+#undef CONFIG_ENV_SIZE_REDUND\n+#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE\n+#endif\n+\n+#if defined(ENV_IS_EMBEDDED)\n+env_t *env_ptr = &environment;\n+#else /* ! ENV_IS_EMBEDDED */\n+env_t *env_ptr;\n+#endif /* ENV_IS_EMBEDDED */\n+\n+DECLARE_GLOBAL_DATA_PTR;\n+\n+static int env_mtd_init(void)\n+{\n+#if defined(ENV_IS_EMBEDDED)\n+\tint crc1_ok = 0, crc2_ok = 0;\n+\tenv_t *tmp_env1;\n+\n+\ttmp_env1 = env_ptr;\n+\tcrc1_ok = crc32(0, tmp_env1->data, ENV_SIZE) == tmp_env1->crc;\n+\n+\tif (!crc1_ok && !crc2_ok) {\n+\t\tgd->env_addr\t= 0;\n+\t\tgd->env_valid\t= ENV_INVALID;\n+\n+\t\treturn 0;\n+\t} else if (crc1_ok && !crc2_ok) {\n+\t\tgd->env_valid = ENV_VALID;\n+\t}\n+\n+\tif (gd->env_valid == ENV_VALID)\n+\t\tenv_ptr = tmp_env1;\n+\n+\tgd->env_addr = (ulong)env_ptr->data;\n+\n+#else /* ENV_IS_EMBEDDED */\n+\tgd->env_addr\t= (ulong)&default_environment[0];\n+\tgd->env_valid\t= ENV_VALID;\n+#endif /* ENV_IS_EMBEDDED */\n+\n+\treturn 0;\n+}\n+\n+static struct mtd_info *env_mtd_get_dev(void)\n+{\n+\tstruct mtd_info *mtd;\n+\n+\tmtd_probe_devices();\n+\n+\tmtd = get_mtd_device_nm(CONFIG_ENV_MTD_NAME);\n+\tif (IS_ERR(mtd) || !mtd) {\n+\t\tprintf(\"MTD device '%s' not found\\n\", CONFIG_ENV_MTD_NAME);\n+\t\treturn NULL;\n+\t}\n+\n+\treturn mtd;\n+}\n+\n+static inline bool mtd_addr_is_block_aligned(struct mtd_info *mtd, u64 addr)\n+{\n+\treturn (addr & mtd->erasesize_mask) == 0;\n+}\n+\n+static int mtd_io_skip_bad(struct mtd_info *mtd, bool read, loff_t offset,\n+\t\t\t   size_t length, size_t redund, u8 *buffer)\n+{\n+\tstruct mtd_oob_ops io_op = {};\n+\tsize_t remaining = length;\n+\tloff_t off, end;\n+\tint ret;\n+\n+\tio_op.mode = MTD_OPS_PLACE_OOB;\n+\tio_op.len = mtd->writesize;\n+\tio_op.datbuf = (void *)buffer;\n+\n+\t/* Search for the first good block after the given offset */\n+\toff = offset;\n+\tend = (off + redund) | (mtd->erasesize - 1);\n+\twhile (mtd_block_isbad(mtd, off) && off < end)\n+\t\toff += mtd->erasesize;\n+\n+\t/* Reached end position */\n+\tif (off >= end)\n+\t\treturn -EIO;\n+\n+\t/* Loop over the pages to do the actual read/write */\n+\twhile (remaining) {\n+\t\t/* Skip the block if it is bad */\n+\t\tif (mtd_addr_is_block_aligned(mtd, off) &&\n+\t\t    mtd_block_isbad(mtd, off)) {\n+\t\t\toff += mtd->erasesize;\n+\t\t\tcontinue;\n+\t\t}\n+\n+\t\tif (read)\n+\t\t\tret = mtd_read_oob(mtd, off, &io_op);\n+\t\telse\n+\t\t\tret = mtd_write_oob(mtd, off, &io_op);\n+\n+\t\tif (ret) {\n+\t\t\tprintf(\"Failure while %s at offset 0x%llx\\n\",\n+\t\t\t       read ? \"reading\" : \"writing\", off);\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\toff += io_op.retlen;\n+\t\tremaining -= io_op.retlen;\n+\t\tio_op.datbuf += io_op.retlen;\n+\t\tio_op.oobbuf += io_op.oobretlen;\n+\n+\t\t/* Reached end position */\n+\t\tif (off >= end)\n+\t\t\treturn -EIO;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+#ifdef CONFIG_CMD_SAVEENV\n+static int mtd_erase_skip_bad(struct mtd_info *mtd, loff_t offset,\n+\t\t\t      size_t length, size_t redund)\n+{\n+\tstruct erase_info erase_op = {};\n+\tloff_t end = (offset + redund) | (mtd->erasesize - 1);\n+\tint ret;\n+\n+\terase_op.mtd = mtd;\n+\terase_op.addr = offset;\n+\terase_op.len = length;\n+\n+\twhile (erase_op.len) {\n+\t\tret = mtd_erase(mtd, &erase_op);\n+\n+\t\t/* Abort if its not a bad block error */\n+\t\tif (ret != -EIO)\n+\t\t\treturn ret;\n+\n+\t\tprintf(\"Skipping bad block at 0x%08llx\\n\", erase_op.fail_addr);\n+\n+\t\t/* Skip bad block and continue behind it */\n+\t\terase_op.len -= erase_op.fail_addr - erase_op.addr;\n+\t\terase_op.len -= mtd->erasesize;\n+\t\terase_op.addr = erase_op.fail_addr + mtd->erasesize;\n+\n+\t\t/* Reached end position */\n+\t\tif (erase_op.addr >= end)\n+\t\t\treturn -EIO;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int env_mtd_save(void)\n+{\n+\tALLOC_CACHE_ALIGN_BUFFER(env_t, env_new, 1);\n+\tstruct mtd_info *mtd;\n+\tint ret = 0;\n+\n+\tret = env_export(env_new);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tmtd = env_mtd_get_dev();\n+\tif (!mtd)\n+\t\treturn 1;\n+\n+\tprintf(\"Erasing on MTD device '%s'... \", mtd->name);\n+\n+\tret = mtd_erase_skip_bad(mtd, CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,\n+\t\t\t\t CONFIG_ENV_SIZE_REDUND);\n+\n+\tputs(ret ? \"FAILED\\n\" : \"OK\\n\");\n+\n+\tif (ret) {\n+\t\tput_mtd_device(mtd);\n+\t\treturn 1;\n+\t}\n+\n+\tprintf(\"Writing to MTD device '%s'... \", mtd->name);\n+\n+\tret = mtd_io_skip_bad(mtd, false, CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,\n+\t\t\t      CONFIG_ENV_SIZE_REDUND, (u8 *)env_new);\n+\n+\tputs(ret ? \"FAILED\\n\" : \"OK\\n\");\n+\n+\tput_mtd_device(mtd);\n+\n+\treturn !!ret;\n+}\n+#endif /* CONFIG_CMD_SAVEENV */\n+\n+static int readenv(size_t offset, u_char *buf)\n+{\n+\tstruct mtd_info *mtd;\n+\tint ret;\n+\n+\tmtd = env_mtd_get_dev();\n+\tif (!mtd)\n+\t\treturn 1;\n+\n+\tret = mtd_io_skip_bad(mtd, true, offset, CONFIG_ENV_SIZE,\n+\t\t\t      CONFIG_ENV_SIZE_REDUND, buf);\n+\n+\tput_mtd_device(mtd);\n+\n+\treturn !!ret;\n+}\n+\n+static int env_mtd_load(void)\n+{\n+#if !defined(ENV_IS_EMBEDDED)\n+\tALLOC_CACHE_ALIGN_BUFFER(char, buf, CONFIG_ENV_SIZE);\n+\tint ret;\n+\n+\tret = readenv(CONFIG_ENV_OFFSET, (u_char *)buf);\n+\tif (ret) {\n+\t\tenv_set_default(\"readenv() failed\", 0);\n+\t\treturn -EIO;\n+\t}\n+\n+\treturn env_import(buf, 1, H_EXTERNAL);\n+#endif /* ! ENV_IS_EMBEDDED */\n+\n+\treturn 0;\n+}\n+\n+U_BOOT_ENV_LOCATION(mtd) = {\n+\t.location\t= ENVL_MTD,\n+\tENV_NAME(\"MTD\")\n+\t.load\t\t= env_mtd_load,\n+#if defined(CONFIG_CMD_SAVEENV)\n+\t.save\t\t= env_save_ptr(env_mtd_save),\n+#endif\n+\t.init\t\t= env_mtd_init,\n+};\n--- a/include/env_internal.h\n+++ b/include/env_internal.h\n@@ -130,6 +130,7 @@ enum env_location {\n \tENVL_FAT,\n \tENVL_FLASH,\n \tENVL_MMC,\n+\tENVL_MTD,\n \tENVL_NAND,\n \tENVL_NVRAM,\n \tENVL_ONENAND,\n--- a/tools/Makefile\n+++ b/tools/Makefile\n@@ -41,6 +41,7 @@ ENVCRC-$(CONFIG_ENV_IS_EMBEDDED) = y\n ENVCRC-$(CONFIG_ENV_IS_IN_EEPROM) = y\n ENVCRC-$(CONFIG_ENV_IS_IN_FLASH) = y\n ENVCRC-$(CONFIG_ENV_IS_IN_ONENAND) = y\n+ENVCRC-$(CONFIG_ENV_IS_IN_MTD) = y\n ENVCRC-$(CONFIG_ENV_IS_IN_NAND) = y\n ENVCRC-$(CONFIG_ENV_IS_IN_NVRAM) = y\n ENVCRC-$(CONFIG_ENV_IS_IN_SPI_FLASH) = y\n"
  },
  {
    "path": "package/boot/uboot-mediatek/patches/000-mtk-17-board-mt7629-add-support-for-booting-from-SPI-NAND.patch",
    "content": "From 3757223c3354b9feeffcbe916eb18eb8873bd133 Mon Sep 17 00:00:00 2001\nFrom: Weijie Gao <weijie.gao@mediatek.com>\nDate: Wed, 3 Mar 2021 10:48:53 +0800\nSubject: [PATCH 07/12] board: mt7629: add support for booting from SPI-NAND\n\nAdd support for mt7629 to boot from SPI-NAND.\nAdd a new defconfig for mt7629+spi-nand configuration.\n\nSigned-off-by: Weijie Gao <weijie.gao@mediatek.com>\n---\n arch/arm/dts/mt7629-rfb-u-boot.dtsi |   8 ++\n arch/arm/dts/mt7629-rfb.dts         |  10 +++\n arch/arm/dts/mt7629.dtsi            |  16 ++++\n board/mediatek/mt7629/Kconfig       |  35 ++++++++-\n configs/mt7629_nand_rfb_defconfig   | 111 ++++++++++++++++++++++++++++\n include/configs/mt7629.h            |   7 ++\n 6 files changed, 186 insertions(+), 1 deletion(-)\n create mode 100644 configs/mt7629_nand_rfb_defconfig\n\n--- a/arch/arm/dts/mt7629-rfb-u-boot.dtsi\n+++ b/arch/arm/dts/mt7629-rfb-u-boot.dtsi\n@@ -40,3 +40,11 @@\n &snfi {\n \tu-boot,dm-pre-reloc;\n };\n+\n+&pinctrl {\n+\tu-boot,dm-pre-reloc;\n+};\n+\n+&snand {\n+\tu-boot,dm-pre-reloc;\n+};\n--- a/arch/arm/dts/mt7629-rfb.dts\n+++ b/arch/arm/dts/mt7629-rfb.dts\n@@ -47,9 +47,12 @@\n \t};\n \n \tsnfi_pins: snfi-pins {\n+\t\tu-boot,dm-pre-reloc;\n+\n \t\tmux {\n \t\t\tfunction = \"flash\";\n \t\t\tgroups = \"snfi\";\n+\t\t\tu-boot,dm-pre-reloc;\n \t\t};\n \t};\n \n@@ -102,6 +105,13 @@\n \t};\n };\n \n+&snand {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&snfi_pins>;\n+\tstatus = \"okay\";\n+\tquad-spi;\n+};\n+\n &uart0 {\n \tpinctrl-names = \"default\";\n \tpinctrl-0 = <&uart0_pins>;\n--- a/arch/arm/dts/mt7629.dtsi\n+++ b/arch/arm/dts/mt7629.dtsi\n@@ -229,6 +229,22 @@\n \t\t#size-cells = <0>;\n \t};\n \n+\tsnand: snand@1100d000 {\n+\t\tcompatible = \"mediatek,mt7629-snand\";\n+\t\treg = <0x1100d000 0x1000>,\n+\t\t      <0x1100e000 0x1000>;\n+\t\treg-names = \"nfi\", \"ecc\";\n+\t\tclocks = <&pericfg CLK_PERI_NFI_PD>,\n+\t\t\t <&pericfg CLK_PERI_SNFI_PD>,\n+\t\t\t <&pericfg CLK_PERI_NFIECC_PD>;\n+\t\tclock-names = \"nfi_clk\", \"pad_clk\", \"ecc_clk\";\n+\t\tassigned-clocks = <&topckgen CLK_TOP_AXI_SEL>,\n+\t\t\t\t  <&topckgen CLK_TOP_NFI_INFRA_SEL>;\n+\t\tassigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>,\n+\t\t\t\t\t <&topckgen CLK_TOP_UNIVPLL2_D8>;\n+\t\tstatus = \"disabled\";\n+\t};\n+\n \tsnor: snor@11014000 {\n \t\tcompatible = \"mediatek,mtk-snor\";\n \t\treg = <0x11014000 0x1000>;\n--- /dev/null\n+++ b/configs/mt7629_nand_rfb_defconfig\n@@ -0,0 +1,111 @@\n+CONFIG_ARM=y\n+CONFIG_SYS_ARCH_TIMER=y\n+CONFIG_SYS_THUMB_BUILD=y\n+CONFIG_ARCH_MEDIATEK=y\n+CONFIG_SYS_TEXT_BASE=0x41e00000\n+CONFIG_SYS_MALLOC_F_LEN=0x4000\n+CONFIG_NR_DRAM_BANKS=1\n+CONFIG_ENV_SIZE=0x20000\n+CONFIG_ENV_OFFSET=0x100000\n+CONFIG_SPL_TEXT_BASE=0x201000\n+CONFIG_TARGET_MT7629=y\n+CONFIG_BOOT_FROM_SNAND_2K_64=y\n+CONFIG_SPL_SERIAL_SUPPORT=y\n+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y\n+CONFIG_SPL_STACK_R_ADDR=0x40800000\n+CONFIG_SPL_PAYLOAD=\"u-boot.img\"\n+CONFIG_BUILD_TARGET=\"u-boot-mtk.bin\"\n+CONFIG_DEFAULT_DEVICE_TREE=\"mt7629-rfb\"\n+CONFIG_SPL_IMAGE=\"spl/u-boot-spl-mtk.bin\"\n+CONFIG_FIT=y\n+CONFIG_FIT_VERBOSE=y\n+CONFIG_BOOTDELAY=3\n+CONFIG_DEFAULT_FDT_FILE=\"mt7629-rfb\"\n+CONFIG_SYS_CONSOLE_IS_IN_ENV=y\n+CONFIG_SYS_STDIO_DEREGISTER=y\n+# CONFIG_DISPLAY_BOARDINFO is not set\n+CONFIG_SPL_SYS_MALLOC_SIMPLE=y\n+CONFIG_SPL_STACK_R=y\n+CONFIG_SPL_MTD_SUPPORT=y\n+CONFIG_SPL_NAND_SUPPORT=y\n+CONFIG_SPL_WATCHDOG_SUPPORT=y\n+CONFIG_HUSH_PARSER=y\n+CONFIG_SYS_PROMPT=\"U-Boot> \"\n+CONFIG_CMD_BOOTMENU=y\n+# CONFIG_BOOTM_NETBSD is not set\n+# CONFIG_BOOTM_PLAN9 is not set\n+# CONFIG_BOOTM_RTEMS is not set\n+# CONFIG_BOOTM_VXWORKS is not set\n+# CONFIG_CMD_ELF is not set\n+# CONFIG_CMD_XIMG is not set\n+CONFIG_CMD_BIND=y\n+CONFIG_CMD_DM=y\n+# CONFIG_CMD_FLASH is not set\n+CONFIG_CMD_GPIO=y\n+CONFIG_CMD_MTD=y\n+CONFIG_CMD_USB=y\n+# CONFIG_CMD_SETEXPR is not set\n+# CONFIG_CMD_NFS is not set\n+CONFIG_CMD_PING=y\n+CONFIG_CMD_FAT=y\n+CONFIG_CMD_FS_GENERIC=y\n+CONFIG_CMD_LOG=y\n+CONFIG_EFI_PARTITION=y\n+# CONFIG_SPL_PARTITION_UUIDS is not set\n+CONFIG_PARTITION_TYPE_GUID=y\n+CONFIG_OF_SPL_REMOVE_PROPS=\"interrupt-parent assigned-clocks assigned-clock-parents\"\n+CONFIG_ENV_OVERWRITE=y\n+CONFIG_ENV_IS_IN_MTD=y\n+CONFIG_ENV_MTD_NAME=\"spi-nand0\"\n+CONFIG_ENV_SIZE_REDUND=0x40000\n+CONFIG_SYS_RELOC_GD_ENV_ADDR=y\n+CONFIG_NET_RANDOM_ETHADDR=y\n+CONFIG_SPL_DM_SEQ_ALIAS=y\n+CONFIG_REGMAP=y\n+CONFIG_SPL_REGMAP=y\n+CONFIG_SYSCON=y\n+CONFIG_SPL_SYSCON=y\n+CONFIG_BLK=y\n+CONFIG_CLK=y\n+CONFIG_SPL_CLK=y\n+# CONFIG_MMC is not set\n+CONFIG_MTD=y\n+CONFIG_DM_MTD=y\n+CONFIG_MTK_SPI_NAND=y\n+CONFIG_MTK_SPI_NAND_MTD=y\n+CONFIG_SPL_MTK_SPI_NAND=y\n+CONFIG_DM_ETH=y\n+CONFIG_MEDIATEK_ETH=y\n+CONFIG_PHY=y\n+CONFIG_PHY_MTK_TPHY=y\n+CONFIG_PINCTRL=y\n+CONFIG_PINCONF=y\n+CONFIG_SPL_PINCTRL=y\n+CONFIG_SPL_PINCONF=y\n+CONFIG_PINCTRL_MT7629=y\n+CONFIG_POWER_DOMAIN=y\n+CONFIG_MTK_POWER_DOMAIN=y\n+CONFIG_DM_REGULATOR=y\n+CONFIG_DM_REGULATOR_FIXED=y\n+CONFIG_RAM=y\n+CONFIG_SPL_RAM=y\n+CONFIG_DM_SERIAL=y\n+CONFIG_MTK_SERIAL=y\n+CONFIG_SPI=y\n+CONFIG_DM_SPI=y\n+CONFIG_SPI_MEM=y\n+CONFIG_MTK_SNFI_SPI=y\n+CONFIG_SYSRESET=y\n+CONFIG_SPL_SYSRESET=y\n+CONFIG_SYSRESET_WATCHDOG=y\n+CONFIG_USB=y\n+CONFIG_DM_USB=y\n+# CONFIG_SPL_DM_USB is not set\n+CONFIG_USB_XHCI_HCD=y\n+CONFIG_USB_XHCI_MTK=y\n+CONFIG_USB_STORAGE=y\n+CONFIG_WDT_MTK=y\n+CONFIG_FAT_WRITE=y\n+CONFIG_LZMA=y\n+CONFIG_SPL_LZMA=y\n+# CONFIG_EFI_LOADER is not set\n--- a/include/configs/mt7629.h\n+++ b/include/configs/mt7629.h\n@@ -25,12 +25,19 @@\n \n /* Defines for SPL */\n #define CONFIG_SPL_STACK\t\t0x106000\n+#ifdef CONFIG_MT7629_BOOT_FROM_SNAND\n+#define CONFIG_SPL_MAX_SIZE\t\tSZ_128K\n+#define CONFIG_SPL_MAX_FOOTPRINT\tSZ_128K\n+#define CONFIG_SPL_PAD_TO\t\t0x20000\n+#define CONFIG_SYS_NAND_U_BOOT_OFFS\tCONFIG_SPL_PAD_TO\n+#else\n #define CONFIG_SPL_MAX_SIZE\t\tSZ_64K\n #define CONFIG_SPL_MAX_FOOTPRINT\tSZ_64K\n #define CONFIG_SPL_PAD_TO\t\t0x10000\n \n #define CONFIG_SPI_ADDR\t\t\t0x30000000\n #define CONFIG_SYS_UBOOT_BASE\t\t(CONFIG_SPI_ADDR + CONFIG_SPL_PAD_TO)\n+#endif\n \n /* SPL -> Uboot */\n #define CONFIG_SYS_INIT_SP_ADDR\t\t(CONFIG_SYS_TEXT_BASE + SZ_2M - \\\n"
  },
  {
    "path": "package/boot/uboot-mediatek/patches/000-mtk-18-board-mt7622-use-new-spi-nand-driver.patch",
    "content": "From 6bcd65ed47844e747ff6db066b092632f1760256 Mon Sep 17 00:00:00 2001\nFrom: Weijie Gao <weijie.gao@mediatek.com>\nDate: Wed, 3 Mar 2021 10:51:43 +0800\nSubject: [PATCH 08/12] board: mt7622: use new spi-nand driver\n\nEnable new spi-nand driver support for mt7622_rfb_defconfig\n\nSigned-off-by: Weijie Gao <weijie.gao@mediatek.com>\n---\n arch/arm/dts/mt7622-rfb.dts  |  7 +++++++\n arch/arm/dts/mt7622.dtsi     | 16 ++++++++++++++++\n configs/mt7622_rfb_defconfig |  5 +++++\n 3 files changed, 28 insertions(+)\n\n--- a/arch/arm/dts/mt7622-rfb.dts\n+++ b/arch/arm/dts/mt7622-rfb.dts\n@@ -188,6 +188,13 @@\n \t};\n };\n \n+&snand {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&snfi_pins>;\n+\tstatus = \"okay\";\n+\tquad-spi;\n+};\n+\n &uart0 {\n \tpinctrl-names = \"default\";\n \tpinctrl-0 = <&uart0_pins>;\n--- a/arch/arm/dts/mt7622.dtsi\n+++ b/arch/arm/dts/mt7622.dtsi\n@@ -53,6 +53,22 @@\n \t\t#size-cells = <0>;\n \t};\n \n+\tsnand: snand@1100d000 {\n+\t\tcompatible = \"mediatek,mt7622-snand\";\n+\t\treg = <0x1100d000 0x1000>,\n+\t\t      <0x1100e000 0x1000>;\n+\t\treg-names = \"nfi\", \"ecc\";\n+\t\tclocks = <&pericfg CLK_PERI_NFI_PD>,\n+\t\t\t <&pericfg CLK_PERI_SNFI_PD>,\n+\t\t\t <&pericfg CLK_PERI_NFIECC_PD>;\n+\t\tclock-names = \"nfi_clk\", \"pad_clk\", \"ecc_clk\";\n+\t\tassigned-clocks = <&topckgen CLK_TOP_AXI_SEL>,\n+\t\t\t\t  <&topckgen CLK_TOP_NFI_INFRA_SEL>;\n+\t\tassigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>,\n+\t\t\t\t\t <&topckgen CLK_TOP_UNIVPLL2_D8>;\n+\t\tstatus = \"disabled\";\n+\t};\n+\n \tsnor: snor@11014000 {\n \t\tcompatible = \"mediatek,mtk-snor\";\n \t\treg = <0x11014000 0x1000>;\n--- a/configs/mt7622_rfb_defconfig\n+++ b/configs/mt7622_rfb_defconfig\n@@ -16,6 +16,7 @@ CONFIG_LOG=y\n CONFIG_SYS_PROMPT=\"MT7622> \"\n CONFIG_CMD_BOOTMENU=y\n CONFIG_CMD_MMC=y\n+CONFIG_CMD_MTD=y\n CONFIG_CMD_PCI=y\n CONFIG_CMD_SF_TEST=y\n CONFIG_CMD_PING=y\n@@ -28,6 +29,10 @@ CONFIG_SYSCON=y\n CONFIG_CLK=y\n CONFIG_MMC_HS200_SUPPORT=y\n CONFIG_MMC_MTK=y\n+CONFIG_MTD=y\n+CONFIG_DM_MTD=y\n+CONFIG_MTK_SPI_NAND=y\n+CONFIG_MTK_SPI_NAND_MTD=y\n CONFIG_DM_SPI_FLASH=y\n CONFIG_SPI_FLASH_EON=y\n CONFIG_SPI_FLASH_GIGADEVICE=y\n"
  },
  {
    "path": "package/boot/uboot-mediatek/patches/000-mtk-19-configs-mt7629-remove-unused-options-and-add-dm-comm.patch",
    "content": "From 632f09f140610cf45da1dba25c66e9ca79a70a15 Mon Sep 17 00:00:00 2001\nFrom: Weijie Gao <weijie.gao@mediatek.com>\nDate: Wed, 3 Mar 2021 12:12:39 +0800\nSubject: [PATCH 09/12] configs: mt7629: remove unused options and add dm\n command\n\nRemove unused bootm options\nAdd dm command\n\nSigned-off-by: Weijie Gao <weijie.gao@mediatek.com>\n---\n configs/mt7629_rfb_defconfig | 5 +++++\n 1 file changed, 5 insertions(+)\n\n--- a/configs/mt7629_rfb_defconfig\n+++ b/configs/mt7629_rfb_defconfig\n@@ -29,9 +29,14 @@ CONFIG_SPL_WATCHDOG=y\n CONFIG_HUSH_PARSER=y\n CONFIG_SYS_PROMPT=\"U-Boot> \"\n CONFIG_CMD_BOOTMENU=y\n+# CONFIG_BOOTM_NETBSD is not set\n+# CONFIG_BOOTM_PLAN9 is not set\n+# CONFIG_BOOTM_RTEMS is not set\n+# CONFIG_BOOTM_VXWORKS is not set\n # CONFIG_CMD_ELF is not set\n # CONFIG_CMD_XIMG is not set\n CONFIG_CMD_BIND=y\n+CONFIG_CMD_DM=y\n # CONFIG_CMD_FLASH is not set\n CONFIG_CMD_GPIO=y\n CONFIG_CMD_SF_TEST=y\n"
  },
  {
    "path": "package/boot/uboot-mediatek/patches/000-mtk-20-configs-mt7622-enable-environment-for-mt7622_rfb.patch",
    "content": "From 93d7086edb0db4b05149dfea21a2a82d8f160944 Mon Sep 17 00:00:00 2001\nFrom: Weijie Gao <weijie.gao@mediatek.com>\nDate: Sat, 6 Mar 2021 16:29:33 +0800\nSubject: [PATCH 10/12] configs: mt7622: enable environment for mt7622_rfb\n\nEnable environment vairables for mt7622_rfb\n\nSigned-off-by: Weijie Gao <weijie.gao@mediatek.com>\n---\n configs/mt7622_rfb_defconfig | 5 +++++\n 1 file changed, 5 insertions(+)\n\n--- a/configs/mt7622_rfb_defconfig\n+++ b/configs/mt7622_rfb_defconfig\n@@ -5,6 +5,8 @@ CONFIG_SYS_TEXT_BASE=0x41e00000\n CONFIG_SYS_MALLOC_F_LEN=0x4000\n CONFIG_NR_DRAM_BANKS=1\n CONFIG_DEFAULT_DEVICE_TREE=\"mt7622-rfb\"\n+CONFIG_ENV_SIZE=0x20000\n+CONFIG_ENV_OFFSET=0x280000\n CONFIG_DEBUG_UART_BASE=0x11002000\n CONFIG_DEBUG_UART_CLOCK=25000000\n CONFIG_DEBUG_UART=y\n@@ -22,6 +24,9 @@ CONFIG_CMD_SF_TEST=y\n CONFIG_CMD_PING=y\n CONFIG_CMD_SMC=y\n CONFIG_ENV_OVERWRITE=y\n+CONFIG_ENV_IS_IN_MTD=y\n+CONFIG_ENV_MTD_NAME=\"spi-nand0\"\n+CONFIG_ENV_SIZE_REDUND=0x40000\n CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y\n CONFIG_NET_RANDOM_ETHADDR=y\n CONFIG_REGMAP=y\n"
  },
  {
    "path": "package/boot/uboot-mediatek/patches/050-mt7622-enable-pstore.patch",
    "content": "--- a/arch/arm/dts/mt7622.dtsi\n+++ b/arch/arm/dts/mt7622.dtsi\n@@ -37,6 +37,30 @@\n \t\t};\n \t};\n \n+\tpsci {\n+\t\tcompatible  = \"arm,psci-1.0\";\n+\t\tmethod      = \"smc\";\n+\t};\n+\n+\treserved-memory {\n+\t\t#address-cells = <2>;\n+\t\t#size-cells = <2>;\n+\t\tranges;\n+\n+\t\t/* 64 KiB reserved for ramoops/pstore */\n+\t\tramoops@42ff0000 {\n+\t\t\tcompatible = \"ramoops\";\n+\t\t\treg = <0 0x42ff0000 0 0x10000>;\n+\t\t\trecord-size = <0x1000>;\n+\t\t};\n+\n+\t\t/* 192 KiB reserved for ARM Trusted Firmware (BL31) */\n+\t\tsecmon_reserved: secmon@43000000 {\n+\t\t\treg = <0 0x43000000 0 0x30000>;\n+\t\t\tno-map;\n+\t\t};\n+\t};\n+\n \tsnfi: snfi@1100d000 {\n \t\tcompatible = \"mediatek,mtk-snfi-spi\";\n \t\treg = <0x1100d000 0x2000>;\n"
  },
  {
    "path": "package/boot/uboot-mediatek/patches/100-scripts-remove-dependency-on-swig.patch",
    "content": "From 12de602dc824bcb821287500fba831225cff5392 Mon Sep 17 00:00:00 2001\nFrom: David Bauer <mail@david-bauer.net>\nDate: Mon, 13 Jul 2020 23:37:37 +0200\nSubject: [PATCH 11/12] scripts: remove dependency on swig\n\nDon't build the libfdt tool, as it has a dependency on swig (which\nOpenWrt does not ship).\n\nThis requires more hacks, as of-platdata generation does not work\nwithout it.\n\nSigned-off-by: David Bauer <mail@david-bauer.net>\n---\n scripts/dtc/Makefile | 2 --\n 1 file changed, 2 deletions(-)\n\n--- a/scripts/dtc/Makefile\n+++ b/scripts/dtc/Makefile\n@@ -18,5 +18,3 @@ HOSTCFLAGS_dtc-parser.tab.o := -I$(src)\n # dependencies on generated files need to be listed explicitly\n $(obj)/dtc-lexer.lex.o: $(obj)/dtc-parser.tab.h\n \n-# Added for U-Boot\n-subdir-$(CONFIG_PYLIBFDT) += pylibfdt\n"
  },
  {
    "path": "package/boot/uboot-mediatek/patches/110-no-kwbimage.patch",
    "content": "--- a/tools/Makefile\n+++ b/tools/Makefile\n@@ -119,7 +119,6 @@ dumpimage-mkimage-objs := aisimage.o \\\n \t\t\timximage.o \\\n \t\t\timx8image.o \\\n \t\t\timx8mimage.o \\\n-\t\t\tkwbimage.o \\\n \t\t\tlib/md5.o \\\n \t\t\tlpc32xximage.o \\\n \t\t\tmxsimage.o \\\n"
  },
  {
    "path": "package/boot/uboot-mediatek/patches/120-use-xz-instead-of-lzma.patch",
    "content": "--- a/Makefile\n+++ b/Makefile\n@@ -1045,7 +1045,7 @@ quiet_cmd_pad_cat = CAT     $@\n cmd_pad_cat = $(cmd_objcopy) && $(append) || { rm -f $@; false; }\n \n quiet_cmd_lzma = LZMA    $@\n-cmd_lzma = lzma -c -z -k -9 $< > $@\n+cmd_lzma = xz --format=lzma -c -z -k -9 $< > $@\n \n cfg: u-boot.cfg\n \n"
  },
  {
    "path": "package/boot/uboot-mediatek/patches/200-cmd-add-imsz-and-imszb.patch",
    "content": "--- a/cmd/bootm.c\n+++ b/cmd/bootm.c\n@@ -228,6 +228,65 @@ U_BOOT_CMD(\n /* iminfo - print header info for a requested image */\n /*******************************************************************/\n #if defined(CONFIG_CMD_IMI)\n+#define SECTOR_SHIFT 9\n+static int image_totalsize(struct cmd_tbl *cmdtp, int flag, int argc,\n+\t\t\t   char *const argv[], short int in_blocks)\n+{\n+\tulong addr;\n+\tvoid *fit;\n+\tint bsize, tsize;\n+\tchar buf[16];\n+\n+\tif (argc >= 2)\n+\t\taddr = simple_strtoul(argv[1], NULL, 16);\n+\telse\n+\t\taddr = image_load_addr;\n+\n+\tfit = (void *)map_sysmem(addr, 0);\n+\ttsize = fit_get_totalsize(fit);\n+\tunmap_sysmem(fit);\n+\tif (tsize == 0)\n+\t\treturn 1;\n+\n+\tbsize = (tsize >> SECTOR_SHIFT) + ((tsize & ((1 << SECTOR_SHIFT) - 1))?1:0);\n+\n+\tif (!in_blocks)\n+\t\tsnprintf(buf, sizeof(buf), \"%x\", tsize);\n+\telse\n+\t\tsnprintf(buf, sizeof(buf), \"%x\", bsize);\n+\n+\tif (argc >= 3)\n+\t\treturn env_set(argv[2], buf);\n+\telse\n+\t\tprintf(\"%s\\n\", buf);\n+\n+\treturn 0;\n+}\n+\n+static int do_imsz(struct cmd_tbl *cmdtp, int flag, int argc,\n+\t\t     char *const argv[])\n+{\n+\treturn image_totalsize(cmdtp, flag, argc, argv, 0);\n+}\n+\n+static int do_imszb(struct cmd_tbl *cmdtp, int flag, int argc,\n+\t\t     char *const argv[])\n+{\n+\treturn image_totalsize(cmdtp, flag, argc, argv, 1);\n+}\n+\n+U_BOOT_CMD(\n+\timsz,\tCONFIG_SYS_MAXARGS,\t1,\tdo_imsz,\n+\t\"get image total size (in bytes)\",\n+\t\"addr [maxhdrlen] [varname]\\n\"\n+);\n+\n+U_BOOT_CMD(\n+\timszb,\tCONFIG_SYS_MAXARGS,\t1,\tdo_imszb,\n+\t\"get image total size (in blocks)\",\n+\t\"addr [maxhdrlen] [varname]\\n\"\n+);\n+\n static int do_iminfo(struct cmd_tbl *cmdtp, int flag, int argc,\n \t\t     char *const argv[])\n {\n--- a/boot/image-fit.c\n+++ b/boot/image-fit.c\n@@ -1993,6 +1993,51 @@ static const char *fit_get_image_type_pr\n \treturn \"unknown\";\n }\n \n+size_t fit_get_totalsize(const void *fit)\n+{\n+\tint ret, ndepth, noffset, images_noffset;\n+\tsize_t data_size, hdrsize, img_total, max_size = 0;\n+\tconst void *data;\n+\n+\tret = fdt_check_header(fit);\n+\tif (ret) {\n+\t\tdebug(\"Wrong FIT format: not a flattened device tree (err=%d)\\n\",\n+\t\t\t  ret);\n+\t\treturn 0;\n+\t}\n+\n+\thdrsize = fdt_totalsize(fit);\n+\n+\t/* simple FIT with internal images */\n+\tif (hdrsize > 0x1000)\n+\t\treturn hdrsize;\n+\n+\timages_noffset = fdt_path_offset(fit, FIT_IMAGES_PATH);\n+\tif (images_noffset < 0) {\n+\t\tprintf(\"Can't find images parent node '%s' (%s)\\n\",\n+\t\tFIT_IMAGES_PATH, fdt_strerror(images_noffset));\n+\t\treturn 0;\n+\t}\n+\n+\tfor (ndepth = 0,\n+\t     noffset = fdt_next_node(fit, images_noffset, &ndepth);\n+\t     (noffset >= 0) && (ndepth > 0);\n+\t     noffset = fdt_next_node(fit, noffset, &ndepth)) {\n+\t\tif (ndepth == 1) {\n+\t\t\tret = fit_image_get_data_and_size(fit, noffset, &data, &data_size);\n+\t\t\tif (ret)\n+\t\t\t\treturn 0;\n+\n+\t\t\timg_total = data_size + (data - fit);\n+\n+\t\t\tmax_size = (max_size > img_total) ? max_size : img_total;\n+\t\t}\n+\t}\n+\n+\treturn max_size;\n+}\n+\n+\n int fit_image_load(bootm_headers_t *images, ulong addr,\n \t\t   const char **fit_unamep, const char **fit_uname_configp,\n \t\t   int arch, int image_type, int bootstage_id,\n--- a/include/image.h\n+++ b/include/image.h\n@@ -952,6 +952,7 @@ int fit_parse_subimage(const char *spec,\n \t\tulong *addr, const char **image_name);\n \n int fit_get_subimage_count(const void *fit, int images_noffset);\n+size_t fit_get_totalsize(const void *fit);\n void fit_print_contents(const void *fit);\n void fit_image_print(const void *fit, int noffset, const char *p);\n \n"
  },
  {
    "path": "package/boot/uboot-mediatek/patches/210-cmd-bootmenu-add-ability-to-select-item-by-shortkey.patch",
    "content": "From afea25576fc92d562b248b783cf03564eb4521da Mon Sep 17 00:00:00 2001\nFrom: Weijie Gao <weijie.gao@mediatek.com>\nDate: Tue, 19 Jan 2021 10:58:48 +0800\nSubject: [PATCH 12/12] cmd: bootmenu: add ability to select item by shortkey\n\nAdd ability to use shortkey to select item for bootmenu command\n\nSigned-off-by: Weijie Gao <weijie.gao@mediatek.com>\n---\n cmd/bootmenu.c | 77 +++++++++++++++++++++++++++++++++++++++++++++-----\n 1 file changed, 70 insertions(+), 7 deletions(-)\n\n--- a/cmd/bootmenu.c\n+++ b/cmd/bootmenu.c\n@@ -11,6 +11,7 @@\n #include <menu.h>\n #include <watchdog.h>\n #include <malloc.h>\n+#include <linux/ctype.h>\n #include <linux/delay.h>\n #include <linux/string.h>\n \n@@ -38,6 +39,7 @@ struct bootmenu_data {\n \tint active;\t\t\t/* active menu entry */\n \tint count;\t\t\t/* total count of menu entries */\n \tstruct bootmenu_entry *first;\t/* first menu entry */\n+\tbool last_choiced;\n };\n \n enum bootmenu_key {\n@@ -46,8 +48,27 @@ enum bootmenu_key {\n \tKEY_DOWN,\n \tKEY_SELECT,\n \tKEY_QUIT,\n+\tKEY_CHOICE,\n };\n \n+static const char choice_chars[] = {\n+\t'1', '2', '3', '4', '5', '6', '7', '8', '9',\n+\t'a', 'b', 'c', 'd', 'e', 'f', 'g', 'h', 'i', 'j',\n+\t'k', 'l', 'm', 'n', 'o', 'p', 'q', 'r', 's', 't',\n+\t'u', 'v', 'w', 'x', 'y', 'z'\n+};\n+\n+static int find_choice(char choice)\n+{\n+\tint i;\n+\n+\tfor (i = 0; i < ARRAY_SIZE(choice_chars); i++)\n+\t\tif (tolower(choice) == choice_chars[i])\n+\t\t\treturn i;\n+\n+\treturn -1;\n+}\n+\n static char *bootmenu_getoption(unsigned short int n)\n {\n \tchar name[MAX_ENV_SIZE];\n@@ -82,7 +103,7 @@ static void bootmenu_print_entry(void *d\n }\n \n static void bootmenu_autoboot_loop(struct bootmenu_data *menu,\n-\t\t\t\tenum bootmenu_key *key, int *esc)\n+\t\t\t\tenum bootmenu_key *key, int *esc, int *choice)\n {\n \tint i, c;\n \n@@ -115,6 +136,19 @@ static void bootmenu_autoboot_loop(struc\n \t\t\t\tbreak;\n \t\t\tdefault:\n \t\t\t\t*key = KEY_NONE;\n+\t\t\t\tif (*esc)\n+\t\t\t\t\tbreak;\n+\n+\t\t\t\t*choice = find_choice(c);\n+\t\t\t\tif ((*choice >= 0 &&\n+\t\t\t\t     *choice < menu->count - 1)) {\n+\t\t\t\t\t*key = KEY_CHOICE;\n+\t\t\t\t} else if (c == '0') {\n+\t\t\t\t\t*choice = menu->count - 1;\n+\t\t\t\t\t*key = KEY_CHOICE;\n+\t\t\t\t} else {\n+\t\t\t\t\t*key = KEY_NONE;\n+\t\t\t\t}\n \t\t\t\tbreak;\n \t\t\t}\n \n@@ -136,10 +170,16 @@ static void bootmenu_autoboot_loop(struc\n }\n \n static void bootmenu_loop(struct bootmenu_data *menu,\n-\t\tenum bootmenu_key *key, int *esc)\n+\t\tenum bootmenu_key *key, int *esc, int *choice)\n {\n \tint c;\n \n+\tif (menu->last_choiced) {\n+\t\tmenu->last_choiced = false;\n+\t\t*key = KEY_SELECT;\n+\t\treturn;\n+\t}\n+\n \tif (*esc == 1) {\n \t\tif (tstc()) {\n \t\t\tc = getchar();\n@@ -165,6 +205,14 @@ static void bootmenu_loop(struct bootmen\n \t\tif (c == '\\e') {\n \t\t\t*esc = 1;\n \t\t\t*key = KEY_NONE;\n+\t\t} else {\n+\t\t\t*choice = find_choice(c);\n+\t\t\tif ((*choice >= 0 && *choice < menu->count - 1)) {\n+\t\t\t\t*key = KEY_CHOICE;\n+\t\t\t} else if (c == '0') {\n+\t\t\t\t*choice = menu->count - 1;\n+\t\t\t\t*key = KEY_CHOICE;\n+\t\t\t}\n \t\t}\n \t\tbreak;\n \tcase 1:\n@@ -216,16 +264,17 @@ static char *bootmenu_choice_entry(void\n \tstruct bootmenu_data *menu = data;\n \tstruct bootmenu_entry *iter;\n \tenum bootmenu_key key = KEY_NONE;\n+\tint choice = -1;\n \tint esc = 0;\n \tint i;\n \n \twhile (1) {\n \t\tif (menu->delay >= 0) {\n \t\t\t/* Autoboot was not stopped */\n-\t\t\tbootmenu_autoboot_loop(menu, &key, &esc);\n+\t\t\tbootmenu_autoboot_loop(menu, &key, &esc, &choice);\n \t\t} else {\n \t\t\t/* Some key was pressed, so autoboot was stopped */\n-\t\t\tbootmenu_loop(menu, &key, &esc);\n+\t\t\tbootmenu_loop(menu, &key, &esc, &choice);\n \t\t}\n \n \t\tswitch (key) {\n@@ -239,6 +288,12 @@ static char *bootmenu_choice_entry(void\n \t\t\t\t++menu->active;\n \t\t\t/* no menu key selected, regenerate menu */\n \t\t\treturn NULL;\n+\t\tcase KEY_CHOICE:\n+\t\t\tmenu->active = choice;\n+\t\t\tif (!menu->last_choiced) {\n+\t\t\t\tmenu->last_choiced = true;\n+\t\t\t\treturn NULL;\n+\t\t\t}\n \t\tcase KEY_SELECT:\n \t\t\titer = menu->first;\n \t\t\tfor (i = 0; i < menu->active; ++i)\n@@ -294,6 +349,7 @@ static struct bootmenu_data *bootmenu_cr\n \tmenu->delay = delay;\n \tmenu->active = 0;\n \tmenu->first = NULL;\n+\tmenu->last_choiced = false;\n \n \tdefault_str = env_get(\"bootmenu_default\");\n \tif (default_str)\n@@ -311,12 +367,19 @@ static struct bootmenu_data *bootmenu_cr\n \t\t\tgoto cleanup;\n \n \t\tlen = sep-option;\n-\t\tentry->title = malloc(len + 1);\n+\t\tentry->title = malloc(len + 4);\n \t\tif (!entry->title) {\n \t\t\tfree(entry);\n \t\t\tgoto cleanup;\n \t\t}\n-\t\tmemcpy(entry->title, option, len);\n+\n+\t\tif (i < ARRAY_SIZE(choice_chars)) {\n+\t\t\tlen = sprintf(entry->title, \"%c. %.*s\", choice_chars[i],\n+\t\t\t\t      len, option);\n+\t\t} else {\n+\t\t\tlen = sprintf(entry->title, \"   %.*s\", len, option);\n+\t\t}\n+\n \t\tentry->title[len] = 0;\n \n \t\tlen = strlen(sep + 1);\n@@ -353,7 +416,7 @@ static struct bootmenu_data *bootmenu_cr\n \t\tif (!entry)\n \t\t\tgoto cleanup;\n \n-\t\tentry->title = strdup(\"U-Boot console\");\n+\t\tentry->title = strdup(\"0. U-Boot console\");\n \t\tif (!entry->title) {\n \t\t\tfree(entry);\n \t\t\tgoto cleanup;\n"
  },
  {
    "path": "package/boot/uboot-mediatek/patches/211-cmd-bootmenu-custom-title.patch",
    "content": "--- a/cmd/bootmenu.c\n+++ b/cmd/bootmenu.c\n@@ -39,6 +39,7 @@ struct bootmenu_data {\n \tint active;\t\t\t/* active menu entry */\n \tint count;\t\t\t/* total count of menu entries */\n \tstruct bootmenu_entry *first;\t/* first menu entry */\n+\tchar *mtitle;\t\t\t/* custom menu title */\n \tbool last_choiced;\n };\n \n@@ -471,7 +472,12 @@ static void menu_display_statusline(stru\n \tprintf(ANSI_CURSOR_POSITION, 1, 1);\n \tputs(ANSI_CLEAR_LINE);\n \tprintf(ANSI_CURSOR_POSITION, 2, 1);\n-\tputs(\"  *** U-Boot Boot Menu ***\");\n+\n+\tif (menu->mtitle)\n+\t\tputs(menu->mtitle);\n+\telse\n+\t\tputs(\"  *** U-Boot Boot Menu ***\");\n+\n \tputs(ANSI_CLEAR_LINE_TO_END);\n \tprintf(ANSI_CURSOR_POSITION, 3, 1);\n \tputs(ANSI_CLEAR_LINE);\n@@ -525,6 +531,7 @@ static void bootmenu_show(int delay)\n \t\treturn;\n \t}\n \n+\tbootmenu->mtitle = env_get(\"bootmenu_title\");\n \tfor (iter = bootmenu->first; iter; iter = iter->next) {\n \t\tif (!menu_item_add(menu, iter->key, iter))\n \t\t\tgoto cleanup;\n"
  },
  {
    "path": "package/boot/uboot-mediatek/patches/220-cmd-env-readmem.patch",
    "content": "--- a/cmd/Kconfig\n+++ b/cmd/Kconfig\n@@ -483,6 +483,12 @@ config CMD_ENV_EXISTS\n \t  Check if a variable is defined in the environment for use in\n \t  shell scripting.\n \n+config CMD_ENV_READMEM\n+\tbool \"env readmem\"\n+\tdefault y\n+\thelp\n+\t  Store memory content into environment variable.\n+\n config CMD_ENV_CALLBACK\n \tbool \"env callbacks - print callbacks and their associated variables\"\n \thelp\n--- a/cmd/nvedit.c\n+++ b/cmd/nvedit.c\n@@ -408,6 +408,60 @@ int do_env_ask(struct cmd_tbl *cmdtp, in\n }\n #endif\n \n+#if defined(CONFIG_CMD_ENV_READMEM)\n+int do_env_readmem(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])\n+{\n+\tchar varstr[CONFIG_SYS_CBSIZE];\n+\tconst void *buf;\n+\tchar *local_args[4];\n+\tulong addr, bytes = 6;\n+\tint hexdump = 0;\n+\n+\t/*\n+\t * Check the syntax:\n+\t *\n+\t * readmem [-b] name address [size]\n+\t */\n+\tif (argc < 3)\n+\t\treturn CMD_RET_USAGE;\n+\n+\tlocal_args[0] = argv[0];\n+\n+\tif (!strncmp(argv[1], \"-b\", 3))\n+\t\thexdump = 1;\n+\n+\tlocal_args[1] = argv[hexdump + 1];\n+\tlocal_args[2] = varstr;\n+\tlocal_args[3] = NULL;\n+\n+\taddr = simple_strtoul(argv[hexdump + 2], NULL, 16);\n+\n+\tif (!hexdump)\n+\t\tbytes = simple_strtoul(argv[hexdump + 3], NULL, 16);\n+\n+\tif (bytes < 1)\n+\t\treturn 1;\n+\n+\tif ((hexdump * 3) * bytes >= CONFIG_SYS_CBSIZE)\n+\t\treturn 1;\n+\n+\tbuf = map_sysmem(addr, bytes);\n+\tif (!buf)\n+\t\treturn 1;\n+\n+\tif (hexdump) {\n+\t\tsprintf(varstr, \"%pM\", buf);\n+\t} else {\n+\t\tmemcpy(varstr, buf, bytes);\n+\t\tvarstr[bytes] = '\\0';\n+\t}\n+\tunmap_sysmem(buf);\n+\n+\t/* Continue calling setenv code */\n+\treturn _do_env_set(flag, 3, local_args, H_INTERACTIVE);\n+}\n+#endif\n+\n #if defined(CONFIG_CMD_ENV_CALLBACK)\n static int print_static_binding(const char *var_name, const char *callback_name,\n \t\t\t\tvoid *priv)\n@@ -1189,6 +1243,9 @@ static struct cmd_tbl cmd_env_sub[] = {\n \tU_BOOT_CMD_MKENT(load, 1, 0, do_env_load, \"\", \"\"),\n #endif\n \tU_BOOT_CMD_MKENT(print, CONFIG_SYS_MAXARGS, 1, do_env_print, \"\", \"\"),\n+#if defined(CONFIG_CMD_ENV_READMEM)\n+\tU_BOOT_CMD_MKENT(readmem, CONFIG_SYS_MAXARGS, 3, do_env_readmem, \"\", \"\"),\n+#endif\n #if defined(CONFIG_CMD_RUN)\n \tU_BOOT_CMD_MKENT(run, CONFIG_SYS_MAXARGS, 1, do_run, \"\", \"\"),\n #endif\n@@ -1277,6 +1334,9 @@ static char env_help_text[] =\n #if defined(CONFIG_CMD_NVEDIT_EFI)\n \t\"env print -e [-guid guid] [-n] [name ...] - print UEFI environment\\n\"\n #endif\n+#if defined(CONFIG_CMD_ENV_READMEM)\n+\t\"env readmem [-b] name address size - read variable from memory\\n\"\n+#endif\n #if defined(CONFIG_CMD_RUN)\n \t\"env run var [...] - run commands in an environment variable\\n\"\n #endif\n@@ -1386,6 +1446,17 @@ U_BOOT_CMD(\n );\n #endif\n \n+#if defined(CONFIG_CMD_ENV_READMEM)\n+U_BOOT_CMD_COMPLETE(\n+\treadmem,\tCONFIG_SYS_MAXARGS,\t3,\tdo_env_readmem,\n+\t\"get environment variable from memory address\",\n+\t\"name [-b] address size\\n\"\n+\t\"    - store memory address to env variable\\n\"\n+\t\"      \\\"-b\\\": read binary ethaddr\",\n+\tvar_complete\n+);\n+#endif\n+\n #if defined(CONFIG_CMD_RUN)\n U_BOOT_CMD_COMPLETE(\n \trun,\tCONFIG_SYS_MAXARGS,\t1,\tdo_run,\n"
  },
  {
    "path": "package/boot/uboot-mediatek/patches/230-cmd-add-pstore-check.patch",
    "content": "--- a/cmd/pstore.c\n+++ b/cmd/pstore.c\n@@ -207,6 +207,58 @@ static int pstore_set(struct cmd_tbl *cm\n }\n \n /**\n+ * pstore_check() - Check for pstore records\n+ * @cmdtp: Command data struct pointer\n+ * @flag: Command flag\n+ * @argc: Command-line argument count\n+ * @argv: Array of command-line arguments\n+ *\n+ * Return: 0 if there are records in pstore, 1 otherwise\n+ */\n+static int pstore_check(struct cmd_tbl *cmdtp, int flag,  int argc,\n+\t\t\tchar * const argv[])\n+{\n+\tphys_addr_t ptr;\n+\tchar *buffer;\n+\tu32 size;\n+\tint header_len = 0;\n+\tbool compressed;\n+\n+\tif (pstore_length == 0) {\n+\t\tprintf(\"Please set PStore configuration\\n\");\n+\t\treturn CMD_RET_USAGE;\n+\t}\n+\n+\tif (buffer_size == 0)\n+\t\tpstore_init_buffer_size();\n+\n+\tbuffer = malloc_cache_aligned(buffer_size);\n+\n+\tptr = pstore_addr;\n+\tphys_addr_t ptr_end = ptr + pstore_length - pstore_pmsg_size\n+\t\t\t- pstore_ftrace_size - pstore_console_size;\n+\n+\twhile (ptr < ptr_end) {\n+\t\tsize = pstore_get_buffer(PERSISTENT_RAM_SIG, ptr,\n+\t\t\t\t\t pstore_record_size, buffer);\n+\t\tptr += pstore_record_size;\n+\n+\t\tif (size == 0)\n+\t\t\tcontinue;\n+\n+\t\theader_len = pstore_read_kmsg_hdr(buffer, &compressed);\n+\t\tif (header_len == 0)\n+\t\t\tcontinue;\n+\n+\t\tfree(buffer);\n+\t\treturn 0;\n+\t}\n+\n+\tfree(buffer);\n+\treturn 1;\n+}\n+\n+/**\n  * pstore_print_buffer() - Print buffer\n  * @type: buffer type\n  * @buffer: buffer to print\n@@ -458,6 +510,7 @@ static int pstore_save(struct cmd_tbl *c\n \n static struct cmd_tbl cmd_pstore_sub[] = {\n \tU_BOOT_CMD_MKENT(set, 8, 0, pstore_set, \"\", \"\"),\n+\tU_BOOT_CMD_MKENT(check, 1, 0, pstore_check, \"\", \"\"),\n \tU_BOOT_CMD_MKENT(display, 3, 0, pstore_display, \"\", \"\"),\n \tU_BOOT_CMD_MKENT(save, 4, 0, pstore_save, \"\", \"\"),\n };\n@@ -531,6 +584,8 @@ U_BOOT_CMD(pstore, 10, 0, do_pstore,\n \t   \"  'pmsg-size' is the size of the user space logs record.\\n\"\n \t   \"  'ecc-size' enables/disables ECC support and specifies ECC buffer size in\\n\"\n \t   \"  bytes (0 disables it, 1 is a special value, means 16 bytes ECC).\\n\"\n+\t   \"pstore check\\n\"\n+\t   \"- Returns true if there are records in pstore.\\n\"\n \t   \"pstore display [record-type] [nb]\\n\"\n \t   \"- Display existing records in pstore reserved memory. A 'record-type' can\\n\"\n \t   \"  be given to only display records of this kind. 'record-type' can be one\\n\"\n"
  },
  {
    "path": "package/boot/uboot-mediatek/patches/260-add-missing-type-u64.patch",
    "content": "--- a/include/linux/types.h\n+++ b/include/linux/types.h\n@@ -1,6 +1,7 @@\n #ifndef _LINUX_TYPES_H\n #define _LINUX_TYPES_H\n \n+typedef unsigned long long __u64;\n #include <linux/posix_types.h>\n #include <asm/types.h>\n #include <stdbool.h>\n"
  },
  {
    "path": "package/boot/uboot-mediatek/patches/280-image-fdt-save-name-of-FIT-configuration-in-chosen-node.patch",
    "content": "From 5f2d5915f8ea4785bc2b8a26955e176a7898c15b Mon Sep 17 00:00:00 2001\nFrom: Daniel Golle <daniel@makrotopia.org>\nDate: Tue, 12 Apr 2022 21:00:43 +0100\nSubject: [PATCH] image-fdt: save name of FIT configuration in '/chosen' node\n\nIt can be useful for the OS (Linux) to know which configuration has\nbeen chosen by U-Boot when launching a FIT image.\nStore the name of the FIT configuration node used in a new string\nproperty called 'u-boot,bootconf' in the '/chosen' node in device tree.\n\nSigned-off-by: Daniel Golle <daniel@makrotopia.org>\nReviewed-by: Tom Rini <trini@konsulko.com>\n---\n boot/image-fdt.c | 6 ++++++\n 1 file changed, 6 insertions(+)\n\ndiff --git a/boot/image-fdt.c b/boot/image-fdt.c\nindex 692a9ad3e4..fdb69926a2 100644\n--- a/boot/image-fdt.c\n+++ b/boot/image-fdt.c\n@@ -601,6 +601,12 @@ int image_setup_libfdt(bootm_headers_t *images, void *blob,\n \t\tgoto err;\n \t}\n \n+\t/* Store name of configuration node as u-boot,bootconf in /chosen node */\n+\tif (images->fit_uname_cfg)\n+\t\tfdt_find_and_setprop(blob, \"/chosen\", \"u-boot,bootconf\",\n+\t\t\t\t\timages->fit_uname_cfg,\n+\t\t\t\t\tstrlen(images->fit_uname_cfg) + 1, 1);\n+\n \t/* Update ethernet nodes */\n \tfdt_fixup_ethernet(blob);\n #if CONFIG_IS_ENABLED(CMD_PSTORE)\n-- \n2.35.3\n\n"
  },
  {
    "path": "package/boot/uboot-mediatek/patches/300-mt7622-generic-reset-button-ignore-env.patch",
    "content": "--- a/board/mediatek/mt7622/mt7622_rfb.c\n+++ b/board/mediatek/mt7622/mt7622_rfb.c\n@@ -6,9 +6,16 @@\n \n #include <common.h>\n #include <config.h>\n+#include <dm.h>\n+#include <button.h>\n #include <env.h>\n #include <init.h>\n #include <asm/global_data.h>\n+#include <linux/delay.h>\n+\n+#ifndef CONFIG_RESET_BUTTON_LABEL\n+#define CONFIG_RESET_BUTTON_LABEL \"reset\"\n+#endif\n \n DECLARE_GLOBAL_DATA_PTR;\n \n@@ -20,7 +27,19 @@ int board_init(void)\n \n int board_late_init(void)\n {\n-\tgd->env_valid = 1; //to load environment variable from persistent store\n+\tstruct udevice *dev;\n+\n+\tif (!button_get_by_label(CONFIG_RESET_BUTTON_LABEL, &dev)) {\n+\t\tputs(\"reset button found\\n\");\n+#ifdef CONFIG_RESET_BUTTON_SETTLE_DELAY\n+\t\tmdelay(CONFIG_RESET_BUTTON_SETTLE_DELAY);\n+#endif\n+\t\tif (button_get_state(dev) == BUTTON_ON) {\n+\t\t\tputs(\"button pushed, resetting environment\\n\");\n+\t\t\tgd->env_valid = ENV_INVALID;\n+\t\t}\n+\t}\n+\n \tenv_relocate();\n \treturn 0;\n }\n--- a/arch/arm/mach-mediatek/Kconfig\n+++ b/arch/arm/mach-mediatek/Kconfig\n@@ -115,4 +115,8 @@ config MTK_BROM_HEADER_INFO\n \tdefault \"media=emmc\" if TARGET_MT8516 || TARGET_MT8365 || TARGET_MT8183\n \tdefault \"lk=1\" if TARGET_MT7623\n \n+config RESET_BUTTON_LABEL\n+\tstring \"Button to trigger factory reset\"\n+\tdefault \"reset\"\n+\n endif\n"
  },
  {
    "path": "package/boot/uboot-mediatek/patches/301-mt7623-generic-reset-button-ignore-env.patch",
    "content": "--- a/board/mediatek/mt7623/mt7623_rfb.c\n+++ b/board/mediatek/mt7623/mt7623_rfb.c\n@@ -4,8 +4,17 @@\n  */\n \n #include <common.h>\n+#include <dm.h>\n+#include <button.h>\n+#include <env.h>\n+#include <init.h>\n #include <mmc.h>\n #include <asm/global_data.h>\n+#include <linux/delay.h>\n+\n+#ifndef CONFIG_RESET_BUTTON_LABEL\n+#define CONFIG_RESET_BUTTON_LABEL \"reset\"\n+#endif\n \n DECLARE_GLOBAL_DATA_PTR;\n \n@@ -41,3 +50,22 @@ int mmc_get_env_dev(void)\n \treturn mmc_get_boot_dev();\n }\n #endif\n+\n+int board_late_init(void)\n+{\n+\tstruct udevice *dev;\n+\n+\tif (!button_get_by_label(CONFIG_RESET_BUTTON_LABEL, &dev)) {\n+\t\tputs(\"reset button found\\n\");\n+#ifdef CONFIG_RESET_BUTTON_SETTLE_DELAY\n+\t\tmdelay(CONFIG_RESET_BUTTON_SETTLE_DELAY);\n+#endif\n+\t\tif (button_get_state(dev) == BUTTON_ON) {\n+\t\t\tputs(\"button pushed, resetting environment\\n\");\n+\t\t\tgd->env_valid = ENV_INVALID;\n+\t\t}\n+\t}\n+\n+\tenv_relocate();\n+\treturn 0;\n+}\n"
  },
  {
    "path": "package/boot/uboot-mediatek/patches/350-add-support-for-Winbond-W25Q512JV.patch",
    "content": "--- a/drivers/mtd/spi/spi-nor-ids.c\n+++ b/drivers/mtd/spi/spi-nor-ids.c\n@@ -369,6 +369,8 @@ const struct flash_info spi_nor_ids[] =\n \t\t\tSPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)\n \t},\n \t{ INFO(\"w25q256\", 0xef4019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },\n+\t{ INFO(\"w25q512jv\", 0xef4020, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_DUAL_READ |\n+\t\t\tSPI_NOR_HAS_TB | SPI_NOR_HAS_LOCK) },\n \t{ INFO(\"w25m512jw\", 0xef6119, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },\n \t{ INFO(\"w25m512jv\", 0xef7119, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },\n #endif\n"
  },
  {
    "path": "package/boot/uboot-mediatek/patches/400-update-bpir2-defconfig.patch",
    "content": "--- a/configs/mt7623n_bpir2_defconfig\n+++ b/configs/mt7623n_bpir2_defconfig\n@@ -4,53 +4,138 @@ CONFIG_ARCH_MEDIATEK=y\n CONFIG_SYS_TEXT_BASE=0x81e00000\n CONFIG_SYS_MALLOC_F_LEN=0x4000\n CONFIG_NR_DRAM_BANKS=1\n-CONFIG_ENV_SIZE=0x1000\n+CONFIG_ENV_SIZE=0x10000\n CONFIG_ENV_OFFSET=0x100000\n-CONFIG_DEFAULT_DEVICE_TREE=\"mt7623n-bananapi-bpi-r2\"\n CONFIG_TARGET_MT7623=y\n+CONFIG_DEFAULT_DEVICE_TREE=\"mt7623n-bananapi-bpi-r2\"\n+CONFIG_USE_DEFAULT_ENV_FILE=y\n CONFIG_DISTRO_DEFAULTS=y\n CONFIG_SYS_LOAD_ADDR=0x84000000\n CONFIG_FIT=y\n-CONFIG_FIT_VERBOSE=y\n+CONFIG_FIT_ENABLE_SHA256_SUPPORT=y\n+CONFIG_LED=y\n+CONFIG_LED_BLINK=y\n+CONFIG_LED_GPIO=y\n+CONFIG_LOGLEVEL=7\n+CONFIG_LOG=y\n+CONFIG_AUTOBOOT_KEYED=y\n+CONFIG_AUTOBOOT_MENU_SHOW=y\n+CONFIG_BOARD_LATE_INIT=y\n CONFIG_BOOTDELAY=3\n+CONFIG_BOOTP_SEND_HOSTNAME=y\n CONFIG_DEFAULT_FDT_FILE=\"mt7623n-bananapi-bpi-r2.dtb\"\n CONFIG_SYS_CONSOLE_IS_IN_ENV=y\n+CONFIG_DEFAULT_ENV_FILE=\"bananapi_bpi-r2_env\"\n+CONFIG_BUTTON=y\n+CONFIG_BUTTON_GPIO=y\n+CONFIG_RESET_BUTTON_LABEL=\"factory\"\n+CONFIG_CFB_CONSOLE_ANSI=y\n+CONFIG_CMD_ENV_FLAGS=y\n # CONFIG_DISPLAY_BOARDINFO is not set\n-CONFIG_SYS_PROMPT=\"U-Boot> \"\n+CONFIG_SYS_PROMPT=\"MT7623> \"\n CONFIG_CMD_BOOTMENU=y\n+CONFIG_CMD_BOOTP=y\n+CONFIG_CMD_BUTTON=y\n+CONFIG_CMD_CACHE=y\n+CONFIG_CMD_CDP=y\n+CONFIG_CMD_DHCP=y\n+CONFIG_CMD_DM=y\n+CONFIG_CMD_DNS=y\n+CONFIG_CMD_ECHO=y\n+CONFIG_CMD_ENV_READMEM=y\n+CONFIG_CMD_ERASEENV=y\n+CONFIG_CMD_EXT4=y\n+CONFIG_CMD_FAT=y\n+CONFIG_CMD_FS_GENERIC=y\n+CONFIG_CMD_FS_UUID=y\n # CONFIG_CMD_ELF is not set\n # CONFIG_CMD_XIMG is not set\n CONFIG_CMD_GPIO=y\n-CONFIG_CMD_GPT=y\n+# CONFIG_CMD_GPT is not set\n+CONFIG_CMD_HASH=y\n+CONFIG_CMD_ITEST=y\n+CONFIG_CMD_LED=y\n+CONFIG_CMD_LICENSE=y\n+CONFIG_CMD_LINK_LOCAL=y\n+CONFIG_CMD_MBR=y\n CONFIG_CMD_MMC=y\n-CONFIG_CMD_READ=y\n-# CONFIG_CMD_SETEXPR is not set\n+CONFIG_CMD_MTD=y\n # CONFIG_CMD_NFS is not set\n+CONFIG_CMD_PCI=y\n+CONFIG_CMD_SF_TEST=y\n+CONFIG_CMD_PING=y\n+CONFIG_CMD_PXE=y\n+CONFIG_CMD_PWM=y\n+CONFIG_CMD_SMC=y\n+CONFIG_CMD_TFTPBOOT=y\n+CONFIG_CMD_TFTPSRV=y\n+CONFIG_CMD_ASKENV=y\n+CONFIG_CMD_PART=y\n+CONFIG_CMD_RARP=y\n+CONFIG_CMD_SATA=y\n+CONFIG_CMD_SETEXPR=y\n+CONFIG_CMD_SLEEP=y\n+CONFIG_CMD_SNTP=y\n+CONFIG_CMD_SOURCE=y\n+CONFIG_CMD_STRINGS=y\n+CONFIG_CMD_USB=y\n+CONFIG_CMD_UUID=y\n+CONFIG_CMD_MMC=y\n+CONFIG_CMD_READ=y\n+CONFIG_CMD_SCSI=y\n+CONFIG_DISPLAY_CPUINFO=y\n+CONFIG_DM_ETH=y\n+CONFIG_DM_GPIO=y\n+CONFIG_DM_SCSI=y\n+CONFIG_DM_MMC=y\n+CONFIG_DM_MTD=y\n+CONFIG_DM_REGULATOR=y\n+CONFIG_DM_REGULATOR_FIXED=y\n+CONFIG_DM_SERIAL=y\n+CONFIG_DM_REGULATOR_GPIO=y\n+CONFIG_DM_USB=y\n+CONFIG_DM_PCI=y\n+CONFIG_DM_PWM=y\n+CONFIG_AHCI=y\n+CONFIG_AHCI_PCI=y\n+CONFIG_SCSI_AHCI=y\n+CONFIG_SCSI=y\n+CONFIG_PWM_MTK=y\n+CONFIG_HUSH_PARSER=y\n+CONFIG_SYS_RELOC_GD_ENV_ADDR=y\n CONFIG_ENV_OVERWRITE=y\n CONFIG_ENV_IS_IN_MMC=y\n CONFIG_SYS_RELOC_GD_ENV_ADDR=y\n CONFIG_NET_RANDOM_ETHADDR=y\n+CONFIG_NETCONSOLE=y\n CONFIG_REGMAP=y\n CONFIG_SYSCON=y\n CONFIG_CLK=y\n+CONFIG_LZMA=y\n+CONFIG_MEDIATEK_ETH=y\n # CONFIG_MMC_QUIRKS is not set\n CONFIG_SUPPORT_EMMC_BOOT=y\n CONFIG_MMC_HS400_SUPPORT=y\n CONFIG_MMC_MTK=y\n+CONFIG_MTK_AHCI=y\n+CONFIG_MTK_POWER_DOMAIN=y\n+CONFIG_MTK_SERIAL=y\n+CONFIG_MTK_TIMER=y\n+CONFIG_OF_LIBFDT_OVERLAY=y\n+CONFIG_PARTITION_UUIDS=y\n+CONFIG_PCI=y\n+CONFIG_PCIE_MEDIATEK=y\n+CONFIG_PHY=y\n CONFIG_PHY_FIXED=y\n-CONFIG_DM_ETH=y\n-CONFIG_MEDIATEK_ETH=y\n CONFIG_PINCTRL=y\n CONFIG_PINCONF=y\n CONFIG_PINCTRL_MT7623=y\n CONFIG_POWER_DOMAIN=y\n-CONFIG_MTK_POWER_DOMAIN=y\n-CONFIG_DM_SERIAL=y\n-CONFIG_MTK_SERIAL=y\n+CONFIG_RANDOM_UUID=y\n+CONFIG_REGEX=y\n CONFIG_SYSRESET=y\n CONFIG_SYSRESET_WATCHDOG=y\n CONFIG_TIMER=y\n-CONFIG_MTK_TIMER=y\n+CONFIG_VERSION_VARIABLE=y\n CONFIG_WDT_MTK=y\n-CONFIG_LZMA=y\n # CONFIG_EFI_GRUB_ARM32_WORKAROUND is not set\n--- /dev/null\n+++ b/bananapi_bpi-r2_env\n@@ -0,0 +1,70 @@\n+ipaddr=192.168.1.1\n+serverip=192.168.1.254\n+loadaddr=0x88000000\n+dtaddr=0x83f00000\n+console=earlycon=uart8250,mmio32,0x11004000 console=ttyS2,115200 console=tty1\n+initrd_high=0xafffffff\n+part_default=3\n+part_recovery=2\n+bootcmd=run boot_mmc\n+bootdelay=0\n+bootfile=openwrt-mediatek-mt7623-bananapi_bpi-r2-initramfs-recovery.itb\n+bootfile_upg=openwrt-mediatek-mt7623-bananapi_bpi-r2-squashfs-sysupgrade.itb\n+bootled_pwr=bpi-r2:pio:green\n+bootled_rec=bpi-r2:pio:blue\n+bootmenu_confirm_return=askenv - Press ENTER to return to menu ; bootmenu 60\n+bootmenu_default=0\n+bootmenu_delay=0\n+bootmenu_title=      \u001b[0;34m( ( ( \u001b[1;39mOpenWrt\u001b[0;34m ) ) )\n+bootmenu_0=Initialize environment.=run _firstboot\n+bootmenu_0d=Run default boot command.=run boot_default\n+bootmenu_1=Boot system via TFTP.=run boot_tftp ; run bootmenu_confirm_return\n+boot_default=if env exists flag_recover ; then else run bootcmd ; fi ; run boot_recovery ; setenv replacevol 1 ; run boot_tftp_forever\n+boot_first=if button factory ; then led $bootled_rec on ; run boot_tftp_recovery ; setenv flag_recover 1 ; run boot_default ; fi ; bootmenu\n+boot_tftp_forever=led bpi-r2:pio:blue on ; while true ; do run boot_tftp_recovery ; sleep 1 ; done\n+boot_tftp_production=tftpboot $loadaddr $bootfile_upg && env exists replacevol && iminfo $loadaddr && run mmc_write_production ; if env exists noboot ; then else bootm $loadaddr ; fi\n+boot_tftp_recovery=tftpboot $loadaddr $bootfile && env exists replacevol && iminfo $loadaddr && run mmc_write_recovery ; if env exists noboot ; then else bootm $loadaddr ; fi\n+boot_tftp=tftpboot $loadaddr $bootfile && bootm $loadaddr\n+boot_mmc=run boot_production ; run boot_recovery\n+emmc_init=run emmc_init_bl && run emmc_init_openwrt ; env default bootcmd ; saveenv\n+emmc_init_bl=run sdmmc_read_emmc_hdr && run emmc_write_hdr && run sdmmc_read_preloader && run emmc_write_preloader && run sdmmc_read_uboot && run emmc_write_uboot\n+emmc_init_openwrt=run sdmmc_read_recovery && run emmc_write_recovery ; run sdmmc_read_production && run emmc_write_production\n+emmc_write_hdr=mmc dev 0 0 ; mmc erase 0x0 0x2000 ; mmc write $loadaddr 0x0 0x4 ; mmc dev 0 1 ; mmc partconf 0 1 1 1 ; mmc erase 0x0 0x400 ; mmc write $loadaddr 0x0 0x4 ; mmc partconf 0 1 1 0\n+emmc_write_preloader=mmc dev 0 1 ; mmc partconf 0 1 1 1 ; mmc write $loadaddr 0x4 0x100 ; mmc partconf 0 1 1 0\n+emmc_write_uboot=mmc dev 0 0 ; part size mmc 0 1 part_size && part start mmc 0 1 part_addr && mmc write $loadaddr $part_addr 0x400\n+emmc_write_production=mmc dev 0 0 ; iminfo $loadaddr && part start mmc 0 $part_default part_addr && part size mmc 0 $part_default part_size && run mmc_write_vol\n+emmc_write_recovery=mmc dev 0 0 ; iminfo $loadaddr && part start mmc 0 $part_recovery part_addr && part size mmc 0 $part_recovery part_size && run mmc_write_vol\n+emmc_read_production=mmc dev 0 0 ; part start mmc 0 $part_default part_addr && part size mmc 0 $part_default part_size && run mmc_read_vol\n+emmc_read_recovery=mmc dev 0 0 ; part start mmc 0 $part_recovery part_addr && part size mmc 0 $part_recovery part_size && run mmc_read_vol\n+mmc_write_production=if test \"$bootedfrom\" = \"SD\" ; then run sdmmc_write_production ; else run emmc_write_production ; fi\n+mmc_write_recovery=if test \"$bootedfrom\" = \"SD\" ; run sdmmc_write_recovery ; else run emmc_write_recovery ; fi\n+mmc_write_vol=imszb $loadaddr image_size && test 0x$image_size -le 0x$part_size && mmc erase 0x$part_addr 0x$part_size && mmc write $loadaddr 0x$part_addr 0x$image_size\n+mmc_read_vol=mmc read $loadaddr $part_addr 0x8 && imszb $loadaddr image_size && test 0x$image_size -le 0x$part_size && mmc read $loadaddr 0x$part_addr 0x$image_size && setexpr filesize $image_size * 0x200\n+reset_factory=eraseenv && reset\n+sdmmc_read_emmc_hdr=mmc dev 1 && mmc read $loadaddr 0x1ff8 0x8\n+sdmmc_read_preloader=mmc dev 1 && mmc read $loadaddr 0x4 0x100\n+sdmmc_read_uboot=mmc dev 1 ; part start mmc 1 1 part_addr && part size mmc 1 1 part_size && mmc read $loadaddr $part_addr $part_size\n+sdmmc_read_production=mmc dev 1 ; part start mmc 1 $part_default part_addr && part size mmc 1 $part_default part_size && run mmc_read_vol\n+sdmmc_read_recovery=mmc dev 1 ; part start mmc 1 $part_recovery part_addr && part size mmc 1 $part_recovery part_size && run mmc_read_vol\n+sdmmc_write_production=iminfo $fileaddr && mmc dev 1 && part start mmc 1 $part_default part_addr && part size mmc 1 $part_default part_size && run mmc_write_vol\n+sdmmc_write_recovery=iminfo $fileaddr && mmc dev 1 && part start mmc 1 $part_recovery part_addr && part size mmc 1 $part_recovery part_size && run mmc_write_vol\n+_checkbootedfrom=setenv _checkbootedfrom ; if itest.l *81dffff0 == 434d4d65 ; then setenv bootedfrom eMMC ; else setenv bootedfrom SD ; fi\n+_init_env=setenv _init_env ; setenv _create_env ; saveenv ; saveenv\n+_firstboot=setenv _firstboot ; led $bootled_pwr off ;led $bootled_rec on ; run _checkbootedfrom _switch_to_menu _update_bootdev _update_bootcmd _update_bootcmd2 _init_env boot_first\n+_set_bootcmd_sdmmc=setenv boot_production \"led $bootled_rec off ; led $bootled_pwr on ; run sdmmc_read_production && bootm $loadaddr ; led $bootled_pwr off\"\n+_set_bootcmd_emmc=setenv boot_production \"led $bootled_rec off ; led $bootled_pwr on ; run emmc_read_production && bootm $loadaddr ; led $bootled_pwr off\"\n+_update_bootcmd=setenv _update_bootcmd ; if test \"$bootedfrom\" = \"SD\" ; then run _set_bootcmd_sdmmc ; else run _set_bootcmd_emmc ; fi ; setenv _set_bootcmd_sdmmc ; setenv _set_bootcmd_emmc\n+_set_bootcmd2_sdmmc=setenv boot_recovery \"led $bootled_pwr off ; led $bootled_rec on ; run sdmmc_read_recovery && bootm $loadaddr ; led $bootled_rec off\"\n+_set_bootcmd2_emmc=setenv boot_recovery \"led $bootled_pwr off ; led $bootled_rec on ; run emmc_read_recovery && bootm $loadaddr ; led $bootled_rec off\"\n+_update_bootcmd2=setenv _update_bootcmd2 ; if test \"$bootedfrom\" = \"SD\" ; then run _set_bootcmd2_sdmmc ; else run _set_bootcmd2_emmc ; fi ; setenv _set_bootcmd2_sdmmc ; setenv _set_bootcmd2_emmc\n+_update_bootdev=setenv _update_bootdev ; if test \"$bootedfrom\" = \"SD\" ; then setenv bootargs \"$console root=/dev/mmcblk1p65\" ; else setenv bootargs \"$console root=/dev/mmcblk0p65\" ; fi\n+_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title\n+_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title \"$bootmenu_title  \u001b[0;36m[$bootedfrom]\u001b[0m    \u001b[33m$ver\u001b[0m\" ; run _set_bm2\n+_set_bm2=setenv _set_bm2 ; setenv bootmenu_2 \"Boot production system from $bootedfrom.=run boot_production ; run bootmenu_confirm_return\" ; run _set_bm3\n+_set_bm3=setenv _set_bm3 ; setenv bootmenu_3 \"Boot recovery system from $bootedfrom.=run boot_recovery ; run bootmenu_confirm_return\" ; run _set_bm4\n+_set_bm4=setenv _set_bm4 ; setenv bootmenu_4 \"Load production system via TFTP then write to $bootedfrom.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_production ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return\" ; run _set_bm5\n+_set_bm5=setenv _set_bm5 ; setenv bootmenu_5 \"Load recovery system via TFTP then write to $bootedfrom.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_recovery ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return\" ; run _set_bm5a\n+_set_bm5a=setenv _set_bm5a ; if test \"$bootedfrom\" = \"SD\" ; then run _set_bm6 ; else setenv _set_bm6 ; setenv _menu_next 6 ; fi ; run _set_bmr\n+_set_bm6=setenv _set_bm6 ; setenv bootmenu_6 \"\u001b[31mInstall bootloader, recovery and production to eMMC.\u001b[0m=run emmc_init ; run bootmenu_confirm_return\" ; setenv _menu_next 7\n+_set_bmr=setenv _set_bmr ; setenv bootmenu_${_menu_next} \"Reboot.=reset\" ; setexpr _menu_next ${_menu_next} + 1 ; run _set_bmf\n+_set_bmf=setenv _set_bmf ; setenv bootmenu_${_menu_next} \"Reset all settings to factory defaults.=run reset_factory ; reset\" ; setenv _menu_next\n--- a/arch/arm/dts/mt7623n-bananapi-bpi-r2.dts\n+++ b/arch/arm/dts/mt7623n-bananapi-bpi-r2.dts\n@@ -66,6 +66,15 @@\n \t\t\tdefault-state = \"off\";\n \t\t};\n \t};\n+\n+\tgpio-keys {\n+\t\tcompatible = \"gpio-keys\";\n+\n+\t\tfactory {\n+\t\t\tlabel = \"factory\";\n+\t\t\tgpios = <&gpio 256 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\t};\n };\n \n &eth {\n"
  },
  {
    "path": "package/boot/uboot-mediatek/patches/401-update-u7623-defconfig.patch",
    "content": "--- a/configs/mt7623a_unielec_u7623_02_defconfig\n+++ b/configs/mt7623a_unielec_u7623_02_defconfig\n@@ -4,51 +4,135 @@ CONFIG_ARCH_MEDIATEK=y\n CONFIG_SYS_TEXT_BASE=0x81e00000\n CONFIG_SYS_MALLOC_F_LEN=0x4000\n CONFIG_NR_DRAM_BANKS=1\n-CONFIG_ENV_SIZE=0x1000\n+CONFIG_ENV_SIZE=0x10000\n CONFIG_ENV_OFFSET=0x100000\n CONFIG_DEFAULT_DEVICE_TREE=\"mt7623a-unielec-u7623-02-emmc\"\n+CONFIG_USE_DEFAULT_ENV_FILE=y\n CONFIG_TARGET_MT7623=y\n CONFIG_DISTRO_DEFAULTS=y\n CONFIG_SYS_LOAD_ADDR=0x84000000\n CONFIG_FIT=y\n-CONFIG_FIT_VERBOSE=y\n+CONFIG_FIT_ENABLE_SHA256_SUPPORT=y\n+CONFIG_LED=y\n+CONFIG_LED_BLINK=y\n+CONFIG_LED_GPIO=y\n+CONFIG_LOGLEVEL=7\n+CONFIG_LOG=y\n+CONFIG_AUTOBOOT_KEYED=y\n+CONFIG_AUTOBOOT_MENU_SHOW=y\n+CONFIG_BOARD_LATE_INIT=y\n CONFIG_BOOTDELAY=3\n+CONFIG_BOOTP_SEND_HOSTNAME=y\n CONFIG_DEFAULT_FDT_FILE=\"mt7623a-unielec-u7623-02-emmc.dtb\"\n CONFIG_SYS_CONSOLE_IS_IN_ENV=y\n+CONFIG_DEFAULT_ENV_FILE=\"unielec_u7623-02_env\"\n+CONFIG_BUTTON=y\n+CONFIG_BUTTON_GPIO=y\n+CONFIG_RESET_BUTTON_LABEL=\"factory\"\n+CONFIG_CFB_CONSOLE_ANSI=y\n+CONFIG_CMD_ENV_FLAGS=y\n # CONFIG_DISPLAY_BOARDINFO is not set\n-CONFIG_SYS_PROMPT=\"U-Boot> \"\n+CONFIG_SYS_PROMPT=\"MT7623> \"\n CONFIG_CMD_BOOTMENU=y\n+CONFIG_CMD_BOOTP=y\n+CONFIG_CMD_BOOTZ=y\n+CONFIG_CMD_BUTTON=y\n+CONFIG_CMD_CACHE=y\n+CONFIG_CMD_CDP=y\n+CONFIG_CMD_DHCP=y\n+CONFIG_CMD_DM=y\n+CONFIG_CMD_DNS=y\n+CONFIG_CMD_ECHO=y\n+CONFIG_CMD_ENV_READMEM=y\n+CONFIG_CMD_ERASEENV=y\n+CONFIG_CMD_EXT4=y\n+CONFIG_CMD_FAT=y\n+CONFIG_CMD_FS_GENERIC=y\n+CONFIG_CMD_FS_UUID=y\n # CONFIG_CMD_ELF is not set\n # CONFIG_CMD_XIMG is not set\n CONFIG_CMD_GPIO=y\n-CONFIG_CMD_GPT=y\n+# CONFIG_CMD_GPT is not set\n+CONFIG_CMD_HASH=y\n+CONFIG_CMD_ITEST=y\n+CONFIG_CMD_LED=y\n+CONFIG_CMD_LICENSE=y\n+CONFIG_CMD_LINK_LOCAL=y\n+CONFIG_CMD_MBR=y\n CONFIG_CMD_MMC=y\n-CONFIG_CMD_READ=y\n-# CONFIG_CMD_SETEXPR is not set\n # CONFIG_CMD_NFS is not set\n-CONFIG_ENV_IS_IN_MMC=y\n+CONFIG_CMD_PCI=y\n+CONFIG_CMD_SF_TEST=y\n+CONFIG_CMD_PING=y\n+CONFIG_CMD_PXE=y\n+CONFIG_CMD_PWM=y\n+CONFIG_CMD_SMC=y\n+CONFIG_CMD_TFTPBOOT=y\n+CONFIG_CMD_TFTPSRV=y\n+CONFIG_CMD_ASKENV=y\n+CONFIG_CMD_PART=y\n+CONFIG_CMD_RARP=y\n+CONFIG_CMD_SATA=y\n+CONFIG_CMD_SETEXPR=y\n+CONFIG_CMD_SLEEP=y\n+CONFIG_CMD_SNTP=y\n+CONFIG_CMD_SOURCE=y\n+CONFIG_CMD_STRINGS=y\n+CONFIG_CMD_USB=y\n+CONFIG_CMD_UUID=y\n+CONFIG_CMD_READ=y\n+CONFIG_CMD_SCSI=y\n+CONFIG_DISPLAY_CPUINFO=y\n+CONFIG_DM_ETH=y\n+CONFIG_DM_GPIO=y\n+CONFIG_DM_SCSI=y\n+CONFIG_DM_MMC=y\n+CONFIG_DM_MTD=y\n+CONFIG_DM_REGULATOR=y\n+CONFIG_DM_REGULATOR_FIXED=y\n+CONFIG_DM_SERIAL=y\n+CONFIG_DM_REGULATOR_GPIO=y\n+CONFIG_DM_USB=y\n+CONFIG_DM_PCI=y\n+CONFIG_DM_PWM=y\n+CONFIG_AHCI=y\n+CONFIG_AHCI_PCI=y\n+CONFIG_SCSI_AHCI=y\n+CONFIG_SCSI=y\n+CONFIG_PWM_MTK=y\n+CONFIG_HUSH_PARSER=y\n CONFIG_SYS_RELOC_GD_ENV_ADDR=y\n+CONFIG_SYS_MMC_ENV_DEV=0\n+CONFIG_ENV_OVERWRITE=y\n+CONFIG_ENV_IS_IN_MMC=y\n CONFIG_NET_RANDOM_ETHADDR=y\n+CONFIG_NETCONSOLE=y\n CONFIG_REGMAP=y\n CONFIG_SYSCON=y\n CONFIG_CLK=y\n+CONFIG_LZMA=y\n+CONFIG_MEDIATEK_ETH=y\n # CONFIG_MMC_QUIRKS is not set\n CONFIG_SUPPORT_EMMC_BOOT=y\n CONFIG_MMC_HS400_SUPPORT=y\n CONFIG_MMC_MTK=y\n+CONFIG_MTK_POWER_DOMAIN=y\n+CONFIG_MTK_SERIAL=y\n+CONFIG_MTK_TIMER=y\n+CONFIG_OF_LIBFDT_OVERLAY=y\n+CONFIG_PARTITION_UUIDS=y\n+CONFIG_PCI=y\n+CONFIG_PCIE_MEDIATEK=y\n+CONFIG_PHY=y\n CONFIG_PHY_FIXED=y\n-CONFIG_DM_ETH=y\n-CONFIG_MEDIATEK_ETH=y\n CONFIG_PINCTRL=y\n CONFIG_PINCONF=y\n CONFIG_PINCTRL_MT7623=y\n CONFIG_POWER_DOMAIN=y\n-CONFIG_MTK_POWER_DOMAIN=y\n-CONFIG_DM_SERIAL=y\n-CONFIG_MTK_SERIAL=y\n+CONFIG_RANDOM_UUID=y\n+CONFIG_REGEX=y\n CONFIG_SYSRESET=y\n CONFIG_SYSRESET_WATCHDOG=y\n CONFIG_TIMER=y\n-CONFIG_MTK_TIMER=y\n+CONFIG_VERSION_VARIABLE=y\n CONFIG_WDT_MTK=y\n-CONFIG_LZMA=y\n--- /dev/null\n+++ b/unielec_u7623-02_env\n@@ -0,0 +1,47 @@\n+ipaddr=192.168.1.1\n+serverip=192.168.1.254\n+loadaddr=0x88000000\n+dtaddr=0x83f00000\n+console=earlycon=uart8250,mmio32,0x11004000 console=ttyS0,115200\n+initrd_high=0xafffffff\n+part_default=3\n+part_recovery=2\n+bootcmd=run boot_mmc\n+bootdelay=0\n+bootfile=openwrt-mediatek-mt7623-unielec_u7623-02-initramfs-recovery.itb\n+bootfile_upg=openwrt-mediatek-mt7623-unielec_u7623-02-squashfs-sysupgrade.itb\n+bootled_rec=u7623-01:green:led3\n+bootmenu_confirm_return=askenv - Press ENTER to return to menu ; bootmenu 60\n+bootmenu_default=0\n+bootmenu_delay=0\n+bootmenu_title=      \u001b[0;34m( ( ( \u001b[1;39mOpenWrt\u001b[0;34m ) ) )\n+bootmenu_0=Initialize environment.=run _firstboot\n+bootmenu_0d=Run default boot command.=run boot_default\n+bootmenu_1=Boot system via TFTP.=run boot_tftp ; run bootmenu_confirm_return\n+bootmenu_2=Boot production system from eMMC.=run boot_production ; run bootmenu_confirm_return\n+bootmenu_3=Boot recovery system from eMMC.=run boot_recovery ; run bootmenu_confirm_return\n+bootmenu_4=Load production system via TFTP then write to eMMC.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_production ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return\n+bootmenu_5=Load recovery system via TFTP then write to eMMC.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_recovery ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return\n+bootmenu_6=Reboot.=reset\n+bootmenu_7=Reset all settings to factory defaults.=run reset_factory ; reset\n+boot_default=if env exists flag_recover ; then else run bootcmd ; fi ; run boot_recovery ; setenv replacevol 1 ; run boot_tftp_forever\n+boot_first=if button factory ; then led $bootled_rec on ; run boot_tftp_recovery ; setenv flag_recover 1 ; run boot_default ; fi ; bootmenu\n+boot_production=run emmc_read_production && bootm $loadaddr\n+boot_recovery=run emmc_read_recovery && bootm $loadaddr\n+boot_tftp_forever=led bpi-r64:pio:blue on ; while true ; do run boot_tftp_recovery ; sleep 1 ; done\n+boot_tftp_production=tftpboot $loadaddr $bootfile_upg && env exists replacevol && iminfo $loadaddr && run emmc_write_production ; if env exists noboot ; then else bootm $loadaddr ; fi\n+boot_tftp_recovery=tftpboot $loadaddr $bootfile && env exists replacevol && iminfo $loadaddr && run emmc_write_recovery ; if env exists noboot ; then else bootm $loadaddr ; fi\n+boot_tftp=tftpboot $loadaddr $bootfile && bootm $loadaddr\n+boot_mmc=run boot_production ; run boot_recovery\n+emmc_write_production=mmc dev 0 0 ; iminfo $loadaddr && part start mmc 0 $part_default part_addr && part size mmc 0 $part_default part_size && run mmc_write_vol\n+emmc_write_recovery=mmc dev 0 0 ; iminfo $loadaddr && part start mmc 0 $part_recovery part_addr && part size mmc 0 $part_recovery part_size && run mmc_write_vol\n+emmc_read_production=mmc dev 0 0 ; part start mmc 0 $part_default part_addr && part size mmc 0 $part_default part_size && run mmc_read_vol\n+emmc_read_recovery=mmc dev 0 0 ; part start mmc 0 $part_recovery part_addr && part size mmc 0 $part_recovery part_size && run mmc_read_vol\n+mmc_write_vol=imszb $loadaddr image_size && test 0x$image_size -le 0x$part_size && mmc erase 0x$part_addr 0x$part_size && mmc write $loadaddr 0x$part_addr 0x$image_size\n+mmc_read_vol=mmc read $loadaddr $part_addr 0x8 && imszb $loadaddr image_size && test 0x$image_size -le 0x$part_size && mmc read $loadaddr 0x$part_addr 0x$image_size && setexpr filesize $image_size * 0x200\n+reset_factory=eraseenv && reset\n+_init_env=setenv _init_env ; saveenv ; saveenv\n+_firstboot=setenv _firstboot ; run _switch_to_menu _update_bootdev _init_env boot_first\n+_update_bootdev=setenv _update_bootdev ; setenv bootargs \"$console root=/dev/mmcblk0p65\"\n+_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title\n+_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title \"$bootmenu_title                \u001b[33m$ver\u001b[0m\"\n"
  },
  {
    "path": "package/boot/uboot-mediatek/patches/402-update-bananapi-bpi-r64-device-tree.patch",
    "content": "--- a/arch/arm/dts/mt7622-bananapi-bpi-r64.dts\n+++ b/arch/arm/dts/mt7622-bananapi-bpi-r64.dts\n@@ -20,6 +20,7 @@\n \n \taliases {\n \t\tspi0 = &snfi;\n+\t\tethernet0 = &eth;\n \t};\n \n \tmemory@40000000 {\n@@ -27,6 +28,42 @@\n \t\treg = <0x40000000 0x40000000>;\n \t};\n \n+\tgpio-keys {\n+\t\tcompatible = \"gpio-keys\";\n+\n+\t\treset {\n+\t\t\tlabel = \"reset\";\n+\t\t\tgpios = <&gpio 0 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\n+\t\twps {\n+\t\t\tlabel = \"wps\";\n+\t\t\tgpios = <&gpio 102 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\t};\n+\n+\tleds {\n+\t\tcompatible = \"gpio-leds\";\n+/*\n+ *\t\tred {\n+ *\t\t\tlabel = \"bpi-r64:pio:red\";\n+ *\t\t\tgpios = <&gpio 88 GPIO_ACTIVE_HIGH>;\n+ *\t\t\tdefault-state = \"off\";\n+ *\t\t};\n+ */\n+\t\tgreen {\n+\t\t\tlabel = \"bpi-r64:pio:green\";\n+\t\t\tgpios = <&gpio 89 GPIO_ACTIVE_HIGH>;\n+\t\t\tdefault-state = \"off\";\n+\t\t};\n+\n+\t\tblue {\n+\t\t\tlabel = \"bpi-r64:pio:blue\";\n+\t\t\tgpios = <&gpio 85 GPIO_ACTIVE_LOW>;\n+\t\t\tdefault-state = \"off\";\n+\t\t};\n+\t};\n+\n \treg_1p8v: regulator-1p8v {\n \t\tcompatible = \"regulator-fixed\";\n \t\tregulator-name = \"fixed-1.8V\";\n@@ -199,7 +236,7 @@\n \tstatus = \"okay\";\n \tbus-width = <8>;\n \tmax-frequency = <50000000>;\n-\tcap-sd-highspeed;\n+\tcap-mmc-highspeed;\n \tvmmc-supply = <&reg_3p3v>;\n \tvqmmc-supply = <&reg_3p3v>;\n \tnon-removable;\n@@ -210,7 +247,7 @@\n \tpinctrl-0 = <&mmc1_pins_default>;\n \tstatus = \"okay\";\n \tbus-width = <4>;\n-\tmax-frequency = <50000000>;\n+\tmax-frequency = <12000000>;\n \tcap-sd-highspeed;\n \tr_smpl = <1>;\n \tvmmc-supply = <&reg_3p3v>;\n"
  },
  {
    "path": "package/boot/uboot-mediatek/patches/403-add-bananapi_bpi-r64-snand.patch",
    "content": "--- a/arch/arm/dts/mt7622-bananapi-bpi-r64.dts\n+++ b/arch/arm/dts/mt7622-bananapi-bpi-r64.dts\n@@ -19,7 +19,7 @@\n \t};\n \n \taliases {\n-\t\tspi0 = &snfi;\n+\t\tspi0 = &snand;\n \t\tethernet0 = &eth;\n \t};\n \n@@ -205,17 +205,11 @@\n \t};\n };\n \n-&snfi {\n-\tpinctrl-names = \"default\", \"snfi\";\n-\tpinctrl-0 = <&snor_pins>;\n-\tpinctrl-1 = <&snfi_pins>;\n+&snand {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&snfi_pins>;\n \tstatus = \"okay\";\n-\n-\tspi-flash@0{\n-\t\tcompatible = \"jedec,spi-nor\";\n-\t\treg = <0>;\n-\t\tu-boot,dm-pre-reloc;\n-\t};\n+\tquad-spi;\n };\n \n &uart0 {\n"
  },
  {
    "path": "package/boot/uboot-mediatek/patches/404-add-bananapi_bpi-r64_defconfigs.patch",
    "content": "--- /dev/null\n+++ b/configs/mt7622_bananapi_bpi-r64-sdmmc_defconfig\n@@ -0,0 +1,159 @@\n+CONFIG_ARM=y\n+CONFIG_POSITION_INDEPENDENT=y\n+CONFIG_ARCH_MEDIATEK=y\n+CONFIG_TARGET_MT7622=y\n+CONFIG_SYS_TEXT_BASE=0x41e00000\n+CONFIG_SYS_MALLOC_F_LEN=0x4000\n+CONFIG_SYS_LOAD_ADDR=0x40080000\n+CONFIG_USE_DEFAULT_ENV_FILE=y\n+CONFIG_BOARD_LATE_INIT=y\n+CONFIG_BOOTP_SEND_HOSTNAME=y\n+CONFIG_NR_DRAM_BANKS=1\n+CONFIG_DEBUG_UART_BASE=0x11002000\n+CONFIG_DEBUG_UART_CLOCK=25000000\n+CONFIG_DEFAULT_DEVICE_TREE=\"mt7622-bananapi-bpi-r64\"\n+CONFIG_OF_LIBFDT_OVERLAY=y\n+CONFIG_DEBUG_UART=y\n+CONFIG_DEFAULT_ENV_FILE=\"bananapi_bpi-r64-sdmmc_env\"\n+CONFIG_NET_RANDOM_ETHADDR=y\n+CONFIG_SMBIOS_PRODUCT_NAME=\"\"\n+CONFIG_AUTOBOOT_KEYED=y\n+CONFIG_BOOTDELAY=30\n+CONFIG_AUTOBOOT_MENU_SHOW=y\n+CONFIG_CFB_CONSOLE_ANSI=y\n+CONFIG_BUTTON=y\n+CONFIG_BUTTON_GPIO=y\n+CONFIG_GPIO_HOG=y\n+CONFIG_CMD_ENV_FLAGS=y\n+CONFIG_FIT=y\n+CONFIG_FIT_ENABLE_SHA256_SUPPORT=y\n+CONFIG_LED=y\n+CONFIG_LED_BLINK=y\n+CONFIG_LED_GPIO=y\n+CONFIG_LOGLEVEL=7\n+CONFIG_LOG=y\n+CONFIG_DEFAULT_FDT_FILE=\"mediatek/mt7622-bananapi-bpi-r64.dtb\"\n+CONFIG_SYS_PROMPT=\"MT7622> \"\n+CONFIG_CMD_BOOTMENU=y\n+CONFIG_CMD_BOOTP=y\n+CONFIG_CMD_BUTTON=y\n+CONFIG_CMD_CACHE=y\n+CONFIG_CMD_CDP=y\n+CONFIG_CMD_DHCP=y\n+CONFIG_CMD_DM=y\n+CONFIG_CMD_DNS=y\n+CONFIG_CMD_ECHO=y\n+CONFIG_CMD_ENV_READMEM=y\n+CONFIG_CMD_ERASEENV=y\n+CONFIG_CMD_EXT4=y\n+CONFIG_CMD_FAT=y\n+CONFIG_CMD_FS_GENERIC=y\n+CONFIG_CMD_FS_UUID=y\n+CONFIG_CMD_GPIO=y\n+CONFIG_CMD_GPT=y\n+CONFIG_CMD_HASH=y\n+CONFIG_CMD_ITEST=y\n+CONFIG_CMD_LED=y\n+CONFIG_CMD_LICENSE=y\n+CONFIG_CMD_LINK_LOCAL=y\n+# CONFIG_CMD_MBR is not set\n+CONFIG_CMD_MMC=y\n+CONFIG_CMD_MTD=y\n+CONFIG_CMD_PCI=y\n+CONFIG_CMD_SF_TEST=y\n+CONFIG_CMD_PING=y\n+CONFIG_CMD_PXE=y\n+CONFIG_CMD_PWM=y\n+CONFIG_CMD_SMC=y\n+CONFIG_CMD_TFTPBOOT=y\n+CONFIG_CMD_TFTPSRV=y\n+CONFIG_CMD_UBI=y\n+CONFIG_CMD_UBI_RENAME=y\n+CONFIG_CMD_UBIFS=y\n+CONFIG_CMD_ASKENV=y\n+CONFIG_CMD_PART=y\n+CONFIG_CMD_PSTORE=y\n+CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000\n+CONFIG_CMD_RARP=y\n+CONFIG_CMD_SETEXPR=y\n+CONFIG_CMD_SLEEP=y\n+CONFIG_CMD_SNTP=y\n+CONFIG_CMD_SOURCE=y\n+CONFIG_CMD_STRINGS=y\n+CONFIG_CMD_USB=y\n+CONFIG_CMD_UUID=y\n+CONFIG_DISPLAY_CPUINFO=y\n+CONFIG_DM_MMC=y\n+CONFIG_DM_MTD=y\n+CONFIG_DM_REGULATOR=y\n+CONFIG_DM_REGULATOR_FIXED=y\n+CONFIG_DM_REGULATOR_GPIO=y\n+CONFIG_DM_USB=y\n+CONFIG_DM_PWM=y\n+CONFIG_PWM_MTK=y\n+CONFIG_HUSH_PARSER=y\n+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y\n+CONFIG_SYS_RELOC_GD_ENV_ADDR=y\n+CONFIG_ENV_IS_IN_MMC=y\n+CONFIG_SYS_MMC_ENV_DEV=1\n+CONFIG_ENV_OFFSET=0x400000\n+CONFIG_ENV_OFFSET_REDUND=0x480000\n+CONFIG_ENV_SIZE=0x80000\n+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y\n+CONFIG_VERSION_VARIABLE=y\n+CONFIG_PARTITION_UUIDS=y\n+CONFIG_NETCONSOLE=y\n+CONFIG_REGMAP=y\n+CONFIG_SYSCON=y\n+CONFIG_CLK=y\n+CONFIG_DM_GPIO=y\n+CONFIG_DM_SCSI=y\n+CONFIG_AHCI=y\n+CONFIG_AHCI_PCI=y\n+CONFIG_SCSI_AHCI=y\n+CONFIG_SCSI=y\n+CONFIG_CMD_SCSI=y\n+CONFIG_PHY=y\n+CONFIG_PHY_MTK_TPHY=y\n+CONFIG_PHY_FIXED=y\n+CONFIG_MTK_AHCI=y\n+CONFIG_DM_ETH=y\n+CONFIG_MEDIATEK_ETH=y\n+CONFIG_PCI=y\n+CONFIG_MTD=y\n+CONFIG_MTD_UBI_FASTMAP=y\n+CONFIG_MTDPARTS_DEFAULT=\"mtdparts=spi-nand0:512k(bl2),2048k(fip),-(ubi)\"\n+CONFIG_DM_PCI=y\n+CONFIG_PCIE_MEDIATEK=y\n+CONFIG_PINCTRL=y\n+CONFIG_PINCONF=y\n+CONFIG_PINCTRL_MT7622=y\n+CONFIG_POWER_DOMAIN=y\n+CONFIG_PRE_CONSOLE_BUFFER=y\n+CONFIG_PRE_CON_BUF_ADDR=0x4007EF00\n+CONFIG_MTK_POWER_DOMAIN=y\n+CONFIG_RAM=y\n+CONFIG_DM_SERIAL=y\n+CONFIG_MTK_SERIAL=y\n+CONFIG_MMC=y\n+CONFIG_MMC_DEFAULT_DEV=1\n+CONFIG_MMC_HS200_SUPPORT=y\n+CONFIG_MMC_MTK=y\n+CONFIG_MMC_SUPPORTS_TUNING=y\n+CONFIG_SUPPORT_EMMC_BOOT=y\n+CONFIG_SPI=y\n+CONFIG_DM_SPI=y\n+CONFIG_MTK_SPI_NAND=y\n+CONFIG_MTK_SPI_NAND_MTD=y\n+CONFIG_SYSRESET_WATCHDOG=y\n+CONFIG_WDT_MTK=y\n+CONFIG_LZO=y\n+CONFIG_ZSTD=y\n+CONFIG_HEXDUMP=y\n+CONFIG_RANDOM_UUID=y\n+CONFIG_REGEX=y\n+CONFIG_USB=y\n+CONFIG_USB_HOST=y\n+CONFIG_USB_XHCI_HCD=y\n+CONFIG_USB_XHCI_MTK=y\n+CONFIG_USB_STORAGE=y\n--- /dev/null\n+++ b/bananapi_bpi-r64-sdmmc_env\n@@ -0,0 +1,82 @@\n+ipaddr=192.168.1.1\n+serverip=192.168.1.254\n+loadaddr=0x48000000\n+bootargs=root=/dev/mmcblk1p65\n+bootcmd=if pstore check ; then run boot_recovery ; else run boot_sdmmc ; fi\n+bootconf=config-mt7622-bananapi-bpi-r64-pcie1\n+bootconf_pcie=config-mt7622-bananapi-bpi-r64-pcie1\n+bootconf_sata=config-mt7622-bananapi-bpi-r64-sata\n+bootdelay=0\n+bootfile=openwrt-mediatek-mt7622-bananapi_bpi-r64-initramfs-recovery.itb\n+bootfile_emmcbl2=openwrt-mediatek-mt7622-bananapi_bpi-r64-emmc-preloader.bin\n+bootfile_emmcbl3=openwrt-mediatek-mt7622-bananapi_bpi-r64-emmc-bl31-uboot.fip\n+bootfile_upg=openwrt-mediatek-mt7622-bananapi_bpi-r64-squashfs-sysupgrade.itb\n+bootled_pwr=bpi-r64:pio:green\n+bootled_rec=bpi-r64:pio:blue\n+bootmenu_confirm_return=askenv - Press ENTER to return to menu ; bootmenu 60\n+bootmenu_default=0\n+bootmenu_delay=0\n+bootmenu_title=      \u001b[0;34m( ( ( \u001b[1;39mOpenWrt\u001b[0;34m ) ) )  \u001b[0;36m[SD card]\u001b[0m\n+bootmenu_0=Initialize environment.=run _firstboot\n+bootmenu_0d=Run default boot command.=run boot_default\n+bootmenu_1=Boot system via TFTP.=run boot_tftp ; run bootmenu_confirm_return\n+bootmenu_2=Boot production system from SD card.=run boot_production ; run bootmenu_confirm_return\n+bootmenu_3=Boot recovery system from SD card.=run boot_recovery ; run bootmenu_confirm_return\n+bootmenu_4=Load production system via TFTP then write to SD card.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_production ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return\n+bootmenu_5=Load recovery system via TFTP then write to SD card.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_recovery ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return\n+bootmenu_6=\u001b[31mInstall bootloader, recovery and production to eMMC.\u001b[0m=run emmc_init ; run bootmenu_confirm_return\n+bootmenu_7=\u001b[31mInstall bootloader, recovery and production to NAND.\u001b[0m=run ubi_init ; run bootmenu_confirm_return\n+bootmenu_8=Reboot.=reset\n+bootmenu_9=Reset all settings to factory defaults.=run reset_factory ; reset\n+boot_first=if button reset ; then led $bootled_rec on ; run boot_tftp_recovery ; setenv flag_recover 1 ; run boot_default ; fi ; bootmenu\n+boot_default=if env exists flag_recover ; then else run bootcmd ; fi ; run boot_recovery ; setenv replacevol 1 ; run boot_tftp_forever\n+boot_production=led $bootled_pwr on ; run sdmmc_read_production && bootm $loadaddr#$bootconf ; led $bootled_pwr off\n+boot_recovery=led $bootled_rec on ; run sdmmc_read_recovery && bootm $loadaddr#$bootconf ; led $bootled_rec off\n+boot_sdmmc=run boot_production ; run boot_recovery\n+boot_tftp_forever=led $bootled_rec on ; while true ; do run boot_tftp_recovery ; sleep 1 ; done\n+boot_tftp_production=tftpboot $loadaddr $bootfile_upg && env exists replacevol && iminfo $loadaddr && run sdmmc_write_production ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi\n+boot_tftp_recovery=tftpboot $loadaddr $bootfile && env exists replacevol && iminfo $loadaddr && run sdmmc_write_recovery ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi\n+boot_tftp=tftpboot $loadaddr $bootfile && bootm $loadaddr\n+boot_ubi=ubi part ubi && setenv bootargs && run boot_ubi_production ; run boot_ubi_recovery\n+boot_ubi_production=led $bootled_pwr on ; run ubi_read_production && bootm $loadaddr ; led $bootled_pwr off\n+boot_ubi_recovery=led $bootled_rec on ; run ubi_read_recovery ; bootm $loadaddr#$bootconf ; ubi remove recovery ; led $bootled_rec off\n+check_ubi=ubi part ubi || run ubi_format\n+emmc_init=run emmc_init_bl && run emmc_init_openwrt ; env default bootcmd ; saveenv ; saveenv\n+emmc_init_bl=run sdmmc_read_emmc_bl2 && run emmc_write_bl2 && run sdmmc_read_emmc_hdr && run emmc_write_hdr && run sdmmc_read_emmc_fip && run emmc_write_fip\n+emmc_init_openwrt=run sdmmc_read_recovery && iminfo $loadaddr && run emmc_write_recovery ; run sdmmc_read_production && iminfo $loadaddr && run emmc_write_production\n+emmc_write_bl2=mmc dev 0 1 && mmc partconf 0 1 1 1 && mmc erase 0x0 0x400 && mmc write $loadaddr 0x0 0x100 ; mmc partconf 0 1 1 0\n+emmc_write_fip=mmc dev 0 0 && mmc erase 0x1000 0x1000 && mmc write $loadaddr 0x1000 0x1000 && mmc erase 0x2000 0x800\n+emmc_write_hdr=mmc dev 0 0 && mmc erase 0x0 0x40 && mmc write $loadaddr 0x0 0x40\n+emmc_write_production=mmc dev 0 && part start mmc 0 $part_default part_addr && part size mmc 0 $part_default part_size && run mmc_write_vol\n+emmc_write_recovery=mmc dev 0 && part start mmc 0 $part_recovery part_addr && part size mmc 0 $part_recovery part_size && run mmc_write_vol\n+mmc_write_vol=imszb $loadaddr image_size && test 0x$image_size -le 0x$part_size && mmc erase 0x$part_addr 0x$part_size && mmc write $loadaddr 0x$part_addr 0x$image_size\n+mmc_read_vol=mmc read $loadaddr $part_addr 0x8 && imszb $loadaddr image_size && test 0x$image_size -le 0x$part_size && mmc read $loadaddr 0x$part_addr 0x$image_size && setexpr filesize $image_size * 0x200\n+part_default=production\n+part_recovery=recovery\n+reset_factory=eraseenv && reset\n+sdmmc_read_emmc_hdr=mmc dev 1 && part start mmc 1 install part_addr && mmc read $loadaddr $part_addr 0x40\n+sdmmc_read_emmc_bl2=mmc dev 1 && part start mmc 1 install part_addr && setexpr offset $part_addr + 0x400 && mmc read $loadaddr $offset 0x400\n+sdmmc_read_emmc_fip=mmc dev 1 && part start mmc 1 install part_addr && setexpr offset $part_addr + 0x1000 && mmc read $loadaddr $offset 0x1000\n+sdmmc_read_production=mmc dev 1 && part start mmc 1 $part_default part_addr && part size mmc 1 $part_default part_size && run mmc_read_vol\n+sdmmc_read_recovery=mmc dev 1 && part start mmc 1 $part_recovery part_addr && part size mmc 1 $part_recovery part_size && run mmc_read_vol\n+sdmmc_read_snand_bl2=mmc dev 1 && part start mmc 1 install part_addr && setexpr offset $part_addr + 0x2000 && mmc read $loadaddr $offset 0x400\n+sdmmc_read_snand_fip=mmc dev 1 && part start mmc 1 install part_addr && setexpr offset $part_addr + 0x2400 && mmc read $loadaddr $offset 0x1000\n+sdmmc_write_production=mmc dev 1 && part start mmc 1 $part_default part_addr && part size mmc 1 $part_default part_size && run mmc_write_vol\n+sdmmc_write_recovery=mmc dev 1 && part start mmc 1 $part_recovery part_addr && part size mmc 1 $part_recovery part_size && run mmc_write_vol\n+snand_write_fip=mtd erase fip && mtd write fip $loadaddr\n+snand_write_bl2=mtd erase bl2 && mtd write bl2 $loadaddr\n+ubi_create_env=ubi create ubootenv 0x100000 dynamic 0 ; ubi create ubootenv2 0x100000 dynamic 1 ; ubi create fit 0x100000 dynamic 2 ; ubi create recovery 0x100000 dynamic 3\n+ubi_format=ubi detach ; mtd erase ubi && ubi part ubi ; reset\n+ubi_init=run ubi_init_bl && ubi detach && mtd erase ubi && ubi part ubi && run ubi_create_env && run ubi_init_openwrt\n+ubi_init_openwrt=run sdmmc_read_recovery && iminfo $loadaddr && run ubi_write_recovery ; run sdmmc_read_production && iminfo $loadaddr && run ubi_write_production\n+ubi_init_bl=run sdmmc_read_snand_bl2 && run snand_write_bl2 && run sdmmc_read_snand_fip && run snand_write_fip\n+ubi_prepare_rootfs=if ubi check rootfs_data ; then else if env exists rootfs_data_max ; then ubi create rootfs_data $rootfs_data_max dynamic || ubi create rootfs_data - dynamic ; else ubi create rootfs_data - dynamic ; fi ; fi\n+ubi_read_production=ubi read $loadaddr fit && iminfo $loadaddr && run ubi_prepare_rootfs\n+ubi_read_recovery=ubi check recovery && ubi read $loadaddr recovery\n+ubi_remove_rootfs=ubi check rootfs_data && ubi remove rootfs_data\n+ubi_write_production=ubi check fit && ubi remove fit ; run ubi_remove_rootfs ; ubi create fit $filesize dynamic 2 && ubi write $loadaddr fit $filesize\n+ubi_write_recovery=ubi check recovery && ubi remove recovery ; run ubi_remove_rootfs ; ubi create recovery $filesize dynamic 3 && ubi write $loadaddr recovery $filesize\n+_init_env=setenv _init_env ; setenv _create_env ; saveenv ; saveenv\n+_firstboot=setenv _firstboot ; run _switch_to_menu ; run _init_env ; run boot_first\n+_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title\n+_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title \"$bootmenu_title       \u001b[33m$ver\u001b[0m\"\n--- /dev/null\n+++ b/configs/mt7622_bananapi_bpi-r64-emmc_defconfig\n@@ -0,0 +1,146 @@\n+CONFIG_ARM=y\n+CONFIG_POSITION_INDEPENDENT=y\n+CONFIG_ARCH_MEDIATEK=y\n+CONFIG_TARGET_MT7622=y\n+CONFIG_SYS_TEXT_BASE=0x41e00000\n+CONFIG_SYS_MALLOC_F_LEN=0x4000\n+CONFIG_SYS_LOAD_ADDR=0x40080000\n+CONFIG_USE_DEFAULT_ENV_FILE=y\n+CONFIG_BOARD_LATE_INIT=y\n+CONFIG_BOOTP_SEND_HOSTNAME=y\n+CONFIG_NR_DRAM_BANKS=1\n+CONFIG_DEBUG_UART_BASE=0x11002000\n+CONFIG_DEBUG_UART_CLOCK=25000000\n+CONFIG_DEFAULT_DEVICE_TREE=\"mt7622-bananapi-bpi-r64\"\n+CONFIG_OF_LIBFDT_OVERLAY=y\n+CONFIG_DEBUG_UART=y\n+CONFIG_DEFAULT_ENV_FILE=\"bananapi_bpi-r64-emmc_env\"\n+CONFIG_NET_RANDOM_ETHADDR=y\n+CONFIG_SMBIOS_PRODUCT_NAME=\"\"\n+CONFIG_AUTOBOOT_KEYED=y\n+CONFIG_BOOTDELAY=30\n+CONFIG_AUTOBOOT_MENU_SHOW=y\n+CONFIG_CFB_CONSOLE_ANSI=y\n+CONFIG_BUTTON=y\n+CONFIG_BUTTON_GPIO=y\n+CONFIG_GPIO_HOG=y\n+CONFIG_CMD_ENV_FLAGS=y\n+CONFIG_FIT=y\n+CONFIG_FIT_ENABLE_SHA256_SUPPORT=y\n+CONFIG_LED=y\n+CONFIG_LED_BLINK=y\n+CONFIG_LED_GPIO=y\n+CONFIG_LOGLEVEL=7\n+CONFIG_LOG=y\n+CONFIG_DEFAULT_FDT_FILE=\"mt7622-bananapi-bpi-r64\"\n+CONFIG_SYS_PROMPT=\"MT7622> \"\n+CONFIG_CMD_BOOTMENU=y\n+CONFIG_CMD_BOOTP=y\n+CONFIG_CMD_BUTTON=y\n+CONFIG_CMD_CACHE=y\n+CONFIG_CMD_CDP=y\n+CONFIG_CMD_DHCP=y\n+CONFIG_CMD_DNS=y\n+CONFIG_CMD_ECHO=y\n+CONFIG_CMD_ENV_READMEM=y\n+CONFIG_CMD_ERASEENV=y\n+CONFIG_CMD_EXT4=y\n+CONFIG_CMD_FAT=y\n+CONFIG_CMD_FS_GENERIC=y\n+CONFIG_CMD_FS_UUID=y\n+CONFIG_CMD_GPIO=y\n+CONFIG_CMD_GPT=y\n+CONFIG_CMD_HASH=y\n+CONFIG_CMD_ITEST=y\n+CONFIG_CMD_LED=y\n+CONFIG_CMD_LICENSE=y\n+CONFIG_CMD_LINK_LOCAL=y\n+# CONFIG_CMD_MBR is not set\n+CONFIG_CMD_MMC=y\n+CONFIG_CMD_PCI=y\n+CONFIG_CMD_SF_TEST=y\n+CONFIG_CMD_PING=y\n+CONFIG_CMD_PXE=y\n+CONFIG_CMD_PWM=y\n+CONFIG_CMD_SMC=y\n+CONFIG_CMD_TFTPBOOT=y\n+CONFIG_CMD_TFTPSRV=y\n+CONFIG_CMD_ASKENV=y\n+CONFIG_CMD_PART=y\n+CONFIG_CMD_PSTORE=y\n+CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000\n+CONFIG_CMD_RARP=y\n+CONFIG_CMD_SETEXPR=y\n+CONFIG_CMD_SLEEP=y\n+CONFIG_CMD_SNTP=y\n+CONFIG_CMD_SOURCE=y\n+CONFIG_CMD_STRINGS=y\n+CONFIG_CMD_USB=y\n+CONFIG_CMD_UUID=y\n+CONFIG_DISPLAY_CPUINFO=y\n+CONFIG_DM_MMC=y\n+CONFIG_DM_REGULATOR=y\n+CONFIG_DM_REGULATOR_FIXED=y\n+CONFIG_DM_REGULATOR_GPIO=y\n+CONFIG_DM_USB=y\n+CONFIG_DM_PWM=y\n+CONFIG_PWM_MTK=y\n+CONFIG_HUSH_PARSER=y\n+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y\n+CONFIG_SYS_RELOC_GD_ENV_ADDR=y\n+CONFIG_ENV_IS_IN_MMC=y\n+CONFIG_SYS_MMC_ENV_DEV=0\n+CONFIG_ENV_OFFSET=0x400000\n+CONFIG_ENV_OFFSET_REDUND=0x480000\n+CONFIG_ENV_SIZE=0x80000\n+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y\n+CONFIG_VERSION_VARIABLE=y\n+CONFIG_PARTITION_UUIDS=y\n+CONFIG_NETCONSOLE=y\n+CONFIG_REGMAP=y\n+CONFIG_SYSCON=y\n+CONFIG_CLK=y\n+CONFIG_DM_GPIO=y\n+CONFIG_DM_SCSI=y\n+CONFIG_AHCI=y\n+CONFIG_AHCI_PCI=y\n+CONFIG_SCSI_AHCI=y\n+CONFIG_SCSI=y\n+CONFIG_CMD_SCSI=y\n+CONFIG_PHY=y\n+CONFIG_PHY_MTK_TPHY=y\n+CONFIG_PHY_FIXED=y\n+CONFIG_MTK_AHCI=y\n+CONFIG_DM_ETH=y\n+CONFIG_MEDIATEK_ETH=y\n+CONFIG_PCI=y\n+CONFIG_DM_PCI=y\n+CONFIG_PCIE_MEDIATEK=y\n+CONFIG_PINCTRL=y\n+CONFIG_PINCONF=y\n+CONFIG_PINCTRL_MT7622=y\n+CONFIG_POWER_DOMAIN=y\n+CONFIG_PRE_CONSOLE_BUFFER=y\n+CONFIG_PRE_CON_BUF_ADDR=0x4007EF00\n+CONFIG_MTK_POWER_DOMAIN=y\n+CONFIG_RAM=y\n+CONFIG_DM_SERIAL=y\n+CONFIG_MTK_SERIAL=y\n+CONFIG_MMC=y\n+CONFIG_MMC_DEFAULT_DEV=0\n+CONFIG_MMC_HS200_SUPPORT=y\n+CONFIG_MMC_MTK=y\n+CONFIG_MMC_SUPPORTS_TUNING=y\n+CONFIG_SUPPORT_EMMC_BOOT=y\n+CONFIG_SYSRESET_WATCHDOG=y\n+CONFIG_WDT_MTK=y\n+CONFIG_LZO=y\n+CONFIG_ZSTD=y\n+CONFIG_HEXDUMP=y\n+CONFIG_RANDOM_UUID=y\n+CONFIG_REGEX=y\n+CONFIG_USB=y\n+CONFIG_USB_HOST=y\n+CONFIG_USB_XHCI_HCD=y\n+CONFIG_USB_XHCI_MTK=y\n+CONFIG_USB_STORAGE=y\n--- /dev/null\n+++ b/bananapi_bpi-r64-emmc_env\n@@ -0,0 +1,56 @@\n+ipaddr=192.168.1.1\n+serverip=192.168.1.254\n+loadaddr=0x48000000\n+bootcmd=if pstore check ; then run boot_recovery ; else run boot_emmc ; fi\n+bootargs=root=/dev/mmcblk0p65\n+bootconf=config-mt7622-bananapi-bpi-r64-pcie1\n+bootconf_pcie=config-mt7622-bananapi-bpi-r64-pcie1\n+bootconf_sata=config-mt7622-bananapi-bpi-r64-sata\n+bootdelay=0\n+bootfile=openwrt-mediatek-mt7622-bananapi_bpi-r64-initramfs-recovery.itb\n+bootfile_upg=openwrt-mediatek-mt7622-bananapi_bpi-r64-squashfs-sysupgrade.itb\n+bootfile_bl2=openwrt-mediatek-mt7622-bananapi_bpi-r64-emmc-preloader.bin\n+bootfile_fip=openwrt-mediatek-mt7622-bananapi_bpi-r64-emmc-bl31-uboot.fip\n+bootled_pwr=bpi-r64:pio:green\n+bootled_rec=bpi-r64:pio:blue\n+bootmenu_confirm_return=askenv - Press ENTER to return to menu ; bootmenu 60\n+bootmenu_default=0\n+bootmenu_delay=0\n+bootmenu_title=      \u001b[0;34m( ( ( \u001b[1;39mOpenWrt\u001b[0;34m ) ) )  \u001b[0;36m[eMMC]\u001b[0m\n+bootmenu_0=Initialize environment.=run _firstboot\n+bootmenu_0d=Run default boot command.=run boot_default\n+bootmenu_1=Boot system via TFTP.=run boot_tftp ; run bootmenu_confirm_return\n+bootmenu_2=Boot production system from eMMC.=run boot_production ; run bootmenu_confirm_return\n+bootmenu_3=Boot recovery system from eMMC.=run boot_recovery ; run bootmenu_confirm_return\n+bootmenu_4=Load production system via TFTP then write to eMMC.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_production ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return\n+bootmenu_5=Load recovery system via TFTP then write to eMMC.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_recovery ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return\n+bootmenu_6=\u001b[31mLoad BL31+U-Boot FIP via TFTP then write to eMMC.\u001b[0m=run boot_tftp_write_fip ; run bootmenu_confirm_return\n+bootmenu_7=\u001b[31mLoad BL2 preloader via TFTP then write to eMMC.\u001b[0m=run boot_tftp_write_bl2 ; run bootmenu_confirm_return\n+bootmenu_8=Reboot.=reset\n+bootmenu_9=Reset all settings to factory defaults.=run reset_factory ; reset\n+boot_first=if button reset ; then led $bootled_rec on ; run boot_tftp_recovery ; setenv flag_recover 1 ; run boot_default ; fi ; bootmenu\n+boot_default=if env exists flag_recover ; then else run bootcmd ; fi ; run boot_recovery ; setenv replacevol 1 ; run boot_tftp_forever\n+boot_production=led $bootled_pwr on ; run emmc_read_production && bootm $loadaddr#$bootconf ; led $bootled_pwr off\n+boot_recovery=led $bootled_rec on ; run emmc_read_recovery && bootm $loadaddr#$bootconf ; led $bootled_rec off\n+boot_emmc=run boot_production ; run boot_recovery\n+boot_tftp_forever=led $bootled_rec on ; while true ; do run boot_tftp_recovery ; sleep 1 ; done\n+boot_tftp_production=tftpboot $loadaddr $bootfile_upg && env exists replacevol && iminfo $loadaddr && run emmc_write_production ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi\n+boot_tftp_recovery=tftpboot $loadaddr $bootfile && env exists replacevol && iminfo $loadaddr && run emmc_write_recovery ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi\n+boot_tftp_write_bl2=tftpboot $loadaddr $bootfile_bl2 && run emmc_write_bl2\n+boot_tftp_write_fip=tftpboot $loadaddr $bootfile_fip && run emmc_write_fip\n+boot_tftp=tftpboot $loadaddr $bootfile && bootm $loadaddr\n+emmc_write_production=mmc dev 0 && part start mmc 0 $part_default part_addr && part size mmc 0 $part_default part_size && run mmc_write_vol\n+emmc_write_recovery=mmc dev 0 && part start mmc 0 $part_recovery part_addr && part size mmc 0 $part_recovery part_size && run mmc_write_vol\n+emmc_write_bl2=mmc dev 0 1 && mmc partconf 0 1 1 1 && mmc erase 0x0 0x400 && mmc write $loadaddr 0x0 0x100 ; mmc partconf 0 1 1 0\n+emmc_write_fip=mmc dev 0 0 && mmc erase 0x1000 0x1000 && mmc write $loadaddr 0x1000 0x1000 && mmc erase 0x2000 0x800\n+emmc_read_production=mmc dev 0 && part start mmc 0 $part_default part_addr && part size mmc 0 $part_default part_size && run mmc_read_vol\n+emmc_read_recovery=mmc dev 0 && part start mmc 0 $part_recovery part_addr && part size mmc 0 $part_recovery part_size && run mmc_read_vol\n+mmc_write_vol=imszb $fileaddr image_size && test 0x$image_size -le 0x$part_size && mmc erase 0x$part_addr 0x$part_size && mmc write $fileaddr 0x$part_addr 0x$image_size\n+mmc_read_vol=mmc read $loadaddr $part_addr 0x8 && imszb $loadaddr image_size && test 0x$image_size -le 0x$part_size && mmc read $loadaddr 0x$part_addr 0x$image_size\n+part_default=production\n+part_recovery=recovery\n+reset_factory=eraseenv && reset\n+_init_env=setenv _init_env ; setenv _create_env ; saveenv ; saveenv\n+_firstboot=setenv _firstboot ; run _switch_to_menu ; run _init_env ; run boot_first\n+_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title\n+_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title \"$bootmenu_title       \u001b[33m$ver\u001b[0m\"\n--- /dev/null\n+++ b/configs/mt7622_bananapi_bpi-r64-snand_defconfig\n@@ -0,0 +1,140 @@\n+CONFIG_ARM=y\n+CONFIG_POSITION_INDEPENDENT=y\n+CONFIG_ARCH_MEDIATEK=y\n+CONFIG_SYS_TEXT_BASE=0x41e00000\n+CONFIG_SYS_MALLOC_F_LEN=0x4000\n+CONFIG_SYS_LOAD_ADDR=0x40080000\n+CONFIG_USE_DEFAULT_ENV_FILE=y\n+CONFIG_BOARD_LATE_INIT=y\n+CONFIG_BOOTP_SEND_HOSTNAME=y\n+CONFIG_NR_DRAM_BANKS=1\n+CONFIG_DEBUG_UART_BASE=0x11002000\n+CONFIG_DEBUG_UART_CLOCK=25000000\n+CONFIG_DEFAULT_DEVICE_TREE=\"mt7622-bananapi-bpi-r64\"\n+CONFIG_OF_LIBFDT_OVERLAY=y\n+CONFIG_DEBUG_UART=y\n+CONFIG_DEFAULT_ENV_FILE=\"bananapi_bpi-r64-snand_env\"\n+CONFIG_DISTRO_DEFAULTS=y\n+CONFIG_NET_RANDOM_ETHADDR=y\n+CONFIG_SMBIOS_PRODUCT_NAME=\"\"\n+CONFIG_AUTOBOOT_KEYED=y\n+CONFIG_BOOTDELAY=30\n+CONFIG_AUTOBOOT_MENU_SHOW=y\n+CONFIG_CFB_CONSOLE_ANSI=y\n+CONFIG_BUTTON=y\n+CONFIG_BUTTON_GPIO=y\n+CONFIG_CMD_ENV_FLAGS=y\n+CONFIG_FIT=y\n+CONFIG_FIT_ENABLE_SHA256_SUPPORT=y\n+CONFIG_LED=y\n+CONFIG_LED_BLINK=y\n+CONFIG_LED_GPIO=y\n+CONFIG_LOGLEVEL=7\n+CONFIG_LOG=y\n+CONFIG_DEFAULT_FDT_FILE=\"mediatek/mt7622-bananapi-bpi-r64.dtb\"\n+CONFIG_SYS_PROMPT=\"MT7622> \"\n+CONFIG_CMD_BOOTMENU=y\n+CONFIG_CMD_BOOTP=y\n+CONFIG_CMD_BUTTON=y\n+CONFIG_CMD_CDP=y\n+CONFIG_CMD_DHCP=y\n+CONFIG_CMD_DM=y\n+CONFIG_CMD_DNS=y\n+CONFIG_CMD_ECHO=y\n+CONFIG_CMD_EFIDEBUG=y\n+CONFIG_CMD_ENV_READMEM=y\n+CONFIG_CMD_ERASEENV=y\n+CONFIG_CMD_EXT4=y\n+CONFIG_CMD_FAT=y\n+CONFIG_CMD_FS_GENERIC=y\n+CONFIG_CMD_FS_UUID=y\n+CONFIG_CMD_GPIO=y\n+CONFIG_CMD_GPT=y\n+CONFIG_CMD_HASH=y\n+CONFIG_CMD_ITEST=y\n+CONFIG_CMD_LED=y\n+CONFIG_CMD_LICENSE=y\n+CONFIG_CMD_LINK_LOCAL=y\n+# CONFIG_CMD_MBR is not set\n+CONFIG_CMD_MMC=y\n+CONFIG_CMD_MTD=y\n+CONFIG_CMD_PCI=y\n+CONFIG_CMD_PING=y\n+CONFIG_CMD_PXE=y\n+CONFIG_CMD_SMC=y\n+CONFIG_CMD_TFTPBOOT=y\n+CONFIG_CMD_TFTPSRV=y\n+CONFIG_CMD_UBI=y\n+CONFIG_CMD_UBI_RENAME=y\n+CONFIG_CMD_UBIFS=y\n+CONFIG_CMD_ASKENV=y\n+CONFIG_CMD_PART=y\n+CONFIG_CMD_PSTORE=y\n+CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000\n+CONFIG_CMD_RARP=y\n+CONFIG_CMD_SETEXPR=y\n+CONFIG_CMD_SLEEP=y\n+CONFIG_CMD_SNTP=y\n+CONFIG_CMD_SOURCE=y\n+CONFIG_CMD_USB=y\n+CONFIG_CMD_UUID=y\n+CONFIG_DISPLAY_CPUINFO=y\n+CONFIG_DM_MMC=y\n+CONFIG_DM_MTD=y\n+CONFIG_DM_REGULATOR=y\n+CONFIG_DM_REGULATOR_FIXED=y\n+CONFIG_DM_REGULATOR_GPIO=y\n+CONFIG_DM_USB=y\n+CONFIG_HUSH_PARSER=y\n+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y\n+CONFIG_SYS_RELOC_GD_ENV_ADDR=y\n+CONFIG_ENV_IS_IN_UBI=y\n+CONFIG_ENV_UBI_PART=\"ubi\"\n+CONFIG_ENV_UBI_VOLUME=\"ubootenv\"\n+CONFIG_ENV_UBI_VOLUME_REDUND=\"ubootenv2\"\n+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y\n+CONFIG_VERSION_VARIABLE=y\n+CONFIG_PARTITION_UUIDS=y\n+CONFIG_NETCONSOLE=y\n+CONFIG_REGMAP=y\n+CONFIG_SYSCON=y\n+CONFIG_CLK=y\n+CONFIG_PHY_FIXED=y\n+CONFIG_DM_ETH=y\n+CONFIG_MEDIATEK_ETH=y\n+CONFIG_PCI=y\n+CONFIG_MTD=y\n+CONFIG_MTD_UBI_FASTMAP=y\n+CONFIG_MTDPARTS_DEFAULT=\"mtdparts=spi-nand0:512k(bl2),2048k(fip),-(ubi)\"\n+CONFIG_DM_PCI=y\n+CONFIG_PCIE_MEDIATEK=y\n+CONFIG_PINCTRL=y\n+CONFIG_PINCONF=y\n+CONFIG_PINCTRL_MT7622=y\n+CONFIG_POWER_DOMAIN=y\n+CONFIG_PRE_CONSOLE_BUFFER=y\n+CONFIG_PRE_CON_BUF_ADDR=0x4007EF00\n+CONFIG_MTK_POWER_DOMAIN=y\n+CONFIG_RAM=y\n+CONFIG_DM_SERIAL=y\n+CONFIG_MTK_SERIAL=y\n+CONFIG_MMC=y\n+CONFIG_MMC_DEFAULT_DEV=1\n+CONFIG_MMC_MTK=y\n+CONFIG_SUPPORT_EMMC_BOOT=y\n+CONFIG_SPI=y\n+CONFIG_DM_SPI=y\n+CONFIG_MTK_SPI_NAND=y\n+CONFIG_MTK_SPI_NAND_MTD=y\n+CONFIG_SYSRESET_WATCHDOG=y\n+CONFIG_WDT_MTK=y\n+CONFIG_LZO=y\n+CONFIG_ZSTD=y\n+CONFIG_HEXDUMP=y\n+CONFIG_RANDOM_UUID=y\n+CONFIG_REGEX=y\n+CONFIG_USB=y\n+CONFIG_USB_HOST=y\n+CONFIG_USB_XHCI_HCD=y\n+CONFIG_USB_XHCI_MTK=y\n+CONFIG_USB_STORAGE=y\n--- /dev/null\n+++ b/bananapi_bpi-r64-snand_env\n@@ -0,0 +1,57 @@\n+ipaddr=192.168.1.1\n+serverip=192.168.1.254\n+loadaddr=0x48000000\n+bootargs=root=/dev/ubiblock0_2p1\n+bootcmd=if pstore check ; then run boot_recovery ; else run boot_ubi ; fi\n+bootconf=config-mt7622-bananapi-bpi-r64-pcie1\n+bootconf_pcie=config-mt7622-bananapi-bpi-r64-pcie1\n+bootconf_sata=config-mt7622-bananapi-bpi-r64-sata\n+bootdelay=0\n+bootfile=openwrt-mediatek-mt7622-bananapi_bpi-r64-initramfs-recovery.itb\n+bootfile_fip=openwrt-mediatek-mt7622-bananapi_bpi-r64-snand-bl31-uboot.fip\n+bootfile_bl2=openwrt-mediatek-mt7622-bananapi_bpi-r64-snand-preloader.bin\n+bootfile_upg=openwrt-mediatek-mt7622-bananapi_bpi-r64-squashfs-sysupgrade.itb\n+bootled_pwr=bpi-r64:pio:green\n+bootled_rec=bpi-r64:pio:blue\n+bootmenu_confirm_return=askenv - Press ENTER to return to menu ; bootmenu 60\n+bootmenu_default=0\n+bootmenu_delay=0\n+bootmenu_title=      \u001b[0;34m( ( ( \u001b[1;39mOpenWrt\u001b[0;34m ) ) )  \u001b[0;36m[SPI-NAND]\u001b[0m\n+bootmenu_0=Initialize environment.=run _firstboot\n+bootmenu_0d=Run default boot command.=run boot_default\n+bootmenu_1=Boot system via TFTP.=run boot_tftp ; run bootmenu_confirm_return\n+bootmenu_2=Boot production system from NAND.=run boot_production ; run bootmenu_confirm_return\n+bootmenu_3=Boot recovery system from NAND.=run boot_recovery ; run bootmenu_confirm_return\n+bootmenu_4=Load production system via TFTP then write to NAND.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_production ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return\n+bootmenu_5=Load recovery system via TFTP then write to NAND.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_recovery ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return\n+bootmenu_6=\u001b[31mLoad BL31+U-Boot FIP via TFTP then write to NAND.\u001b[0m=run boot_tftp_write_fip ; run bootmenu_confirm_return\n+bootmenu_7=\u001b[31mLoad BL2 preloader via TFTP then write to NAND.\u001b[0m=run boot_tftp_write_bl2 ; run bootmenu_confirm_return\n+bootmenu_8=Reboot.=reset\n+bootmenu_9=Reset all settings to factory defaults.=run reset_factory ; reset\n+boot_first=if button reset ; then led $bootled_rec on ; run boot_tftp_recovery ; setenv flag_recover 1 ; run boot_default ; fi ; bootmenu\n+boot_default=if env exists flag_recover ; then else run bootcmd ; fi ; run boot_recovery ; setenv replacevol 1 ; run boot_tftp_forever\n+boot_production=led $bootled_pwr on ; run ubi_read_production && bootm $loadaddr#$bootconf ; led $bootled_pwr off\n+boot_recovery=led $bootled_rec on ; run ubi_read_recovery ; bootm $loadaddr#$bootconf ; ubi remove recovery ; led $bootled_rec off\n+boot_tftp=tftpboot $loadaddr $bootfile && bootm $loadaddr#$bootconf\n+boot_tftp_forever=led $bootled_rec on ; while true ; do run boot_tftp_recovery ; sleep 1 ; done\n+boot_tftp_production=tftpboot $loadaddr $bootfile_upg && iminfo $loadaddr && ubi part ubi && run ubi_write_production ubi_prepare_rootfs ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi\n+boot_tftp_recovery=tftpboot $loadaddr $bootfile && iminfo $loadaddr && ubi part ubi && run ubi_write_recovery ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi\n+boot_tftp_write_bl2=tftpboot $loadaddr $bootfile_bl2 && run boot_write_bl2\n+boot_tftp_write_fip=tftpboot $loadaddr $bootfile_fip && run boot_write_fip\n+boot_ubi=ubi part ubi && run boot_production ; run boot_recovery\n+boot_write_bl2=mtd erase bl2 && mtd write spi-nand0 $loadaddr 0x0 0x20000 && mtd write spi-nand0 $loadaddr 0x20000 0x20000 && mtd write spi-nand0 $loadaddr 0x40000 0x20000 && mtd write spi-nand0 $loadaddr 0x60000 0x20000\n+boot_write_fip=mtd erase fip && mtd write fip $loadaddr\n+check_ubi=ubi part ubi || run ubi_format\n+reset_factory=ubi part ubi ; ubi write 0x0 ubootenv 0x0 ; ubi write 0x0 ubootenv2 0x0 ; ubi remove rootfs_data\n+ubi_format=ubi detach ; mtd erase ubi && ubi part ubi ; reset\n+ubi_prepare_rootfs=if ubi check rootfs_data ; then else if env exists rootfs_data_max ; then ubi create rootfs_data $rootfs_data_max dynamic || ubi create rootfs_data - dynamic ; else ubi create rootfs_data - dynamic ; fi ; fi\n+ubi_read_production=ubi read $loadaddr fit && iminfo $loadaddr && run ubi_prepare_rootfs\n+ubi_read_recovery=ubi check recovery && ubi read $loadaddr recovery\n+ubi_remove_rootfs=ubi check rootfs_data && ubi remove rootfs_data\n+ubi_write_production=ubi check fit && env exists replacevol && ubi remove fit ; if ubi check fit ; then else run ubi_remove_rootfs ; ubi create fit $filesize dynamic 2 && ubi write $loadaddr fit $filesize ; fi\n+ubi_write_recovery=ubi check recovery && env exists replacevol && ubi remove recovery ; if ubi check recovery ; then else run ubi_remove_rootfs ; ubi create recovery $filesize dynamic 3 && ubi write $loadaddr recovery $filesize ; fi\n+_create_env=ubi create ubootenv 0x100000 dynamic 0 ; ubi create ubootenv2 0x100000 dynamic 1 ; ubi create fit 0x100000 dynamic 2 ; ubi create recovery 0x100000 dynamic 3\n+_init_env=setenv _init_env ; if ubi check ubootenv && ubi check ubootenv2 ; then else run _create_env ; fi ; setenv _create_env ; saveenv || run ubi_format ; saveenv || run ubi_format\n+_firstboot=setenv _firstboot ; run _switch_to_menu ; run check_ubi ; run _init_env ; run boot_first\n+_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title\n+_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title \"$bootmenu_title       \u001b[33m$ver\u001b[0m\"\n"
  },
  {
    "path": "package/boot/uboot-mediatek/patches/405-dts-mt7623n-bpi-r2-fix-leds.patch",
    "content": "--- a/arch/arm/dts/mt7623n-bananapi-bpi-r2.dts\n+++ b/arch/arm/dts/mt7623n-bananapi-bpi-r2.dts\n@@ -50,19 +50,19 @@\n \n \t\tblue {\n \t\t\tlabel = \"bpi-r2:pio:blue\";\n-\t\t\tgpios = <&gpio 241 GPIO_ACTIVE_HIGH>;\n+\t\t\tgpios = <&gpio 240 GPIO_ACTIVE_LOW>;\n \t\t\tdefault-state = \"off\";\n \t\t};\n \n \t\tgreen {\n \t\t\tlabel = \"bpi-r2:pio:green\";\n-\t\t\tgpios = <&gpio 240 GPIO_ACTIVE_HIGH>;\n+\t\t\tgpios = <&gpio 241 GPIO_ACTIVE_LOW>;\n \t\t\tdefault-state = \"off\";\n \t\t};\n \n \t\tred {\n \t\t\tlabel = \"bpi-r2:pio:red\";\n-\t\t\tgpios = <&gpio 239 GPIO_ACTIVE_HIGH>;\n+\t\t\tgpios = <&gpio 239 GPIO_ACTIVE_LOW>;\n \t\t\tdefault-state = \"off\";\n \t\t};\n \t};\n"
  },
  {
    "path": "package/boot/uboot-mediatek/patches/410-add-linksys-e8450.patch",
    "content": "--- /dev/null\n+++ b/configs/mt7622_linksys_e8450_defconfig\n@@ -0,0 +1,136 @@\n+CONFIG_ARM=y\n+CONFIG_POSITION_INDEPENDENT=y\n+CONFIG_ARCH_MEDIATEK=y\n+CONFIG_TARGET_MT7622=y\n+CONFIG_SYS_TEXT_BASE=0x41e00000\n+CONFIG_SYS_MALLOC_F_LEN=0x4000\n+CONFIG_SYS_LOAD_ADDR=0x40080000\n+CONFIG_USE_DEFAULT_ENV_FILE=y\n+CONFIG_BOARD_LATE_INIT=y\n+CONFIG_BOOTP_SEND_HOSTNAME=y\n+CONFIG_DEFAULT_ENV_FILE=\"linksys_e8450_env\"\n+CONFIG_NR_DRAM_BANKS=1\n+CONFIG_DEBUG_UART_BASE=0x11002000\n+CONFIG_DEBUG_UART_CLOCK=25000000\n+CONFIG_DEFAULT_DEVICE_TREE=\"mt7622-linksys-e8450-ubi\"\n+CONFIG_DEBUG_UART=y\n+CONFIG_MTDPARTS_DEFAULT=\"mtdparts=spi-nand0:512k(bl2),1280k(fip),1024k(factory),256k(reserved),-(ubi)\"\n+CONFIG_SMBIOS_PRODUCT_NAME=\"\"\n+CONFIG_AUTOBOOT_KEYED=y\n+CONFIG_BOOTDELAY=30\n+CONFIG_AUTOBOOT_MENU_SHOW=y\n+CONFIG_CFB_CONSOLE_ANSI=y\n+CONFIG_BUTTON=y\n+CONFIG_BUTTON_GPIO=y\n+CONFIG_GPIO_HOG=y\n+CONFIG_CMD_ENV_FLAGS=y\n+CONFIG_FIT=y\n+CONFIG_FIT_ENABLE_SHA256_SUPPORT=y\n+CONFIG_LED=y\n+CONFIG_LED_BLINK=y\n+CONFIG_LED_GPIO=y\n+CONFIG_LOGLEVEL=7\n+CONFIG_LOG=y\n+CONFIG_DEFAULT_FDT_FILE=\"mt7622-linksys-e8450\"\n+CONFIG_SYS_PROMPT=\"MT7622> \"\n+CONFIG_CMD_BOOTMENU=y\n+CONFIG_CMD_BOOTP=y\n+CONFIG_CMD_BUTTON=y\n+CONFIG_CMD_CDP=y\n+CONFIG_CMD_DHCP=y\n+CONFIG_CMD_DNS=y\n+CONFIG_CMD_ECHO=y\n+CONFIG_CMD_ENV_READMEM=y\n+CONFIG_CMD_ERASEENV=y\n+CONFIG_CMD_EXT4=y\n+CONFIG_CMD_FAT=y\n+CONFIG_CMD_FS_GENERIC=y\n+CONFIG_CMD_FS_UUID=y\n+CONFIG_CMD_GPIO=y\n+CONFIG_CMD_GPT=y\n+CONFIG_CMD_HASH=y\n+CONFIG_CMD_ITEST=y\n+CONFIG_CMD_LED=y\n+CONFIG_CMD_LICENSE=y\n+CONFIG_CMD_LINK_LOCAL=y\n+# CONFIG_CMD_MBR is not set\n+CONFIG_CMD_MTD=y\n+CONFIG_CMD_MTDPART=y\n+CONFIG_CMD_PCI=y\n+CONFIG_CMD_SF_TEST=y\n+CONFIG_CMD_PING=y\n+CONFIG_CMD_PXE=y\n+CONFIG_CMD_SMC=y\n+CONFIG_CMD_TFTPBOOT=y\n+CONFIG_CMD_TFTPSRV=y\n+CONFIG_CMD_UBI=y\n+CONFIG_CMD_UBI_RENAME=y\n+CONFIG_CMD_UBIFS=y\n+CONFIG_CMD_ASKENV=y\n+CONFIG_CMD_PART=y\n+CONFIG_CMD_PSTORE=y\n+CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000\n+CONFIG_CMD_RARP=y\n+CONFIG_CMD_SETEXPR=y\n+CONFIG_CMD_SLEEP=y\n+CONFIG_CMD_SNTP=y\n+CONFIG_CMD_SOURCE=y\n+CONFIG_CMD_USB=y\n+CONFIG_CMD_UUID=y\n+CONFIG_DISPLAY_CPUINFO=y\n+CONFIG_DM_REGULATOR=y\n+CONFIG_DM_REGULATOR_FIXED=y\n+CONFIG_DM_REGULATOR_GPIO=y\n+CONFIG_DM_USB=y\n+CONFIG_HUSH_PARSER=y\n+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y\n+CONFIG_SYS_RELOC_GD_ENV_ADDR=y\n+CONFIG_ENV_IS_IN_UBI=y\n+CONFIG_ENV_UBI_PART=\"ubi\"\n+CONFIG_ENV_UBI_VOLUME=\"ubootenv\"\n+CONFIG_ENV_UBI_VOLUME_REDUND=\"ubootenv2\"\n+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y\n+CONFIG_VERSION_VARIABLE=y\n+CONFIG_PARTITION_UUIDS=y\n+CONFIG_NETCONSOLE=y\n+CONFIG_REGMAP=y\n+CONFIG_SYSCON=y\n+CONFIG_CLK=y\n+CONFIG_DM_MTD=y\n+CONFIG_DM_GPIO=y\n+CONFIG_PHY=y\n+CONFIG_PHY_MTK_TPHY=y\n+CONFIG_PHY_FIXED=y\n+CONFIG_DM_ETH=y\n+CONFIG_MEDIATEK_ETH=y\n+CONFIG_PCI=y\n+CONFIG_MTD=y\n+CONFIG_MTD_UBI_FASTMAP=y\n+CONFIG_DM_PCI=y\n+CONFIG_PCIE_MEDIATEK=y\n+CONFIG_PINCTRL=y\n+CONFIG_PINCONF=y\n+CONFIG_PINCTRL_MT7622=y\n+CONFIG_POWER_DOMAIN=y\n+CONFIG_PRE_CONSOLE_BUFFER=y\n+CONFIG_PRE_CON_BUF_ADDR=0x4007EF00\n+CONFIG_MTK_POWER_DOMAIN=y\n+CONFIG_RAM=y\n+CONFIG_DM_SERIAL=y\n+CONFIG_MTK_SERIAL=y\n+CONFIG_SPI=y\n+CONFIG_DM_SPI=y\n+CONFIG_MTK_SPI_NAND=y\n+CONFIG_MTK_SPI_NAND_MTD=y\n+CONFIG_SYSRESET_WATCHDOG=y\n+CONFIG_WDT_MTK=y\n+CONFIG_LZO=y\n+CONFIG_ZSTD=y\n+CONFIG_HEXDUMP=y\n+CONFIG_RANDOM_UUID=y\n+CONFIG_REGEX=y\n+CONFIG_USB=y\n+CONFIG_USB_HOST=y\n+CONFIG_USB_XHCI_HCD=y\n+CONFIG_USB_XHCI_MTK=y\n+CONFIG_USB_STORAGE=y\n--- /dev/null\n+++ b/arch/arm/dts/mt7622-linksys-e8450-ubi.dts\n@@ -0,0 +1,195 @@\n+// SPDX-License-Identifier: GPL-2.0\n+/*\n+ * Copyright (c) 2019 MediaTek Inc.\n+ * Author: Sam Shih <sam.shih@mediatek.com>\n+ */\n+\n+/dts-v1/;\n+#include \"mt7622.dtsi\"\n+#include \"mt7622-u-boot.dtsi\"\n+\n+/ {\n+\t#address-cells = <1>;\n+\t#size-cells = <1>;\n+\tmodel = \"mt7622-linksys-e8450-ubi\";\n+\tcompatible = \"mediatek,mt7622\", \"linksys,e8450-ubi\";\n+\tchosen {\n+\t\tstdout-path = &uart0;\n+\t\ttick-timer = &timer0;\n+\t};\n+\n+\taliases {\n+\t\tspi0 = &snand;\n+\t};\n+\n+\tgpio-keys {\n+\t\tcompatible = \"gpio-keys\";\n+\n+\t\tfactory {\n+\t\t\tlabel = \"reset\";\n+\t\t\tgpios = <&gpio 0 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\n+\t\twps {\n+\t\t\tlabel = \"wps\";\n+\t\t\tgpios = <&gpio 102 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\t};\n+\n+\tgpio-leds {\n+\t\tcompatible = \"gpio-leds\";\n+\n+\t\tled_power: power_blue {\n+\t\t\tlabel = \"power:blue\";\n+\t\t\tgpios = <&gpio 95 GPIO_ACTIVE_LOW>;\n+\t\t\tdefault-state = \"on\";\n+\t\t};\n+\n+\t\tpower_orange {\n+\t\t\tlabel = \"power:orange\";\n+\t\t\tgpios = <&gpio 96 GPIO_ACTIVE_LOW>;\n+\t\t\tdefault-state = \"off\";\n+\t\t};\n+\n+\t\tinet_blue {\n+\t\t\tlabel = \"inet:blue\";\n+\t\t\tgpios = <&gpio 97 GPIO_ACTIVE_LOW>;\n+\t\t\tdefault-state = \"off\";\n+\t\t};\n+\n+\t\tinet_orange {\n+\t\t\tlabel = \"inet:orange\";\n+\t\t\tgpios = <&gpio 98 GPIO_ACTIVE_LOW>;\n+\t\t\tdefault-state = \"off\";\n+\t\t};\n+\t};\n+\n+\tmemory@40000000 {\n+\t\tdevice_type = \"memory\";\n+\t\treg = <0x40000000 0x20000000>;\n+\t};\n+\n+\treg_1p8v: regulator-1p8v {\n+\t\tcompatible = \"regulator-fixed\";\n+\t\tregulator-name = \"fixed-1.8V\";\n+\t\tregulator-min-microvolt = <1800000>;\n+\t\tregulator-max-microvolt = <1800000>;\n+\t\tregulator-boot-on;\n+\t\tregulator-always-on;\n+\t};\n+\n+\treg_3p3v: regulator-3p3v {\n+\t\tcompatible = \"regulator-fixed\";\n+\t\tregulator-name = \"fixed-3.3V\";\n+\t\tregulator-min-microvolt = <3300000>;\n+\t\tregulator-max-microvolt = <3300000>;\n+\t\tregulator-boot-on;\n+\t\tregulator-always-on;\n+\t};\n+\n+\treg_5v: regulator-5v {\n+\t\tcompatible = \"regulator-fixed\";\n+\t\tregulator-name = \"fixed-5V\";\n+\t\tregulator-min-microvolt = <5000000>;\n+\t\tregulator-max-microvolt = <5000000>;\n+\t\tregulator-boot-on;\n+\t\tregulator-always-on;\n+\t};\n+};\n+\n+&pcie {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pcie0_pins>, <&pcie1_pins>;\n+\tstatus = \"okay\";\n+\n+\tpcie@0,0 {\n+\t\tstatus = \"okay\";\n+\t};\n+\n+\tpcie@1,0 {\n+\t\tstatus = \"okay\";\n+\t};\n+};\n+\n+&pinctrl {\n+\tpcie0_pins: pcie0-pins {\n+\t\tmux {\n+\t\t\tfunction = \"pcie\";\n+\t\t\tgroups = \"pcie0_pad_perst\",\n+\t\t\t\t \"pcie0_1_waken\",\n+\t\t\t\t \"pcie0_1_clkreq\";\n+\t\t};\n+\t};\n+\n+\tpcie1_pins: pcie1-pins {\n+\t\tmux {\n+\t\t\tfunction = \"pcie\";\n+\t\t\tgroups = \"pcie1_pad_perst\",\n+\t\t\t\t \"pcie1_0_waken\",\n+\t\t\t\t \"pcie1_0_clkreq\";\n+\t\t};\n+\t};\n+\n+\tsnfi_pins: snfi-pins {\n+\t\tmux {\n+\t\t\tfunction = \"flash\";\n+\t\t\tgroups = \"snfi\";\n+\t\t};\n+\t};\n+\n+\tuart0_pins: uart0 {\n+\t\tmux {\n+\t\t\tfunction = \"uart\";\n+\t\t\tgroups = \"uart0_0_tx_rx\" ;\n+\t\t};\n+\t};\n+\n+\twatchdog_pins: watchdog-default {\n+\t\tmux {\n+\t\t\tfunction = \"watchdog\";\n+\t\t\tgroups = \"watchdog\";\n+\t\t};\n+\t};\n+};\n+\n+&snand {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&snfi_pins>;\n+\tstatus = \"okay\";\n+\tquad-spi;\n+};\n+\n+&uart0 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&uart0_pins>;\n+\tstatus = \"okay\";\n+};\n+\n+&watchdog {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&watchdog_pins>;\n+\tstatus = \"okay\";\n+};\n+\n+&eth {\n+\tstatus = \"okay\";\n+\tmediatek,gmac-id = <0>;\n+\tphy-mode = \"sgmii\";\n+\tmediatek,switch = \"mt7531\";\n+\treset-gpios = <&gpio 54 GPIO_ACTIVE_HIGH>;\n+\n+\tfixed-link {\n+\t\tspeed = <1000>;\n+\t\tfull-duplex;\n+\t};\n+};\n+\n+&ssusb {\n+\tvusb33-supply = <&reg_3p3v>;\n+\tvbus-supply = <&reg_5v>;\n+\tstatus = \"okay\";\n+};\n+\n+&u3phy {\n+\tstatus = \"okay\";\n+};\n--- a/arch/arm/dts/Makefile\n+++ b/arch/arm/dts/Makefile\n@@ -1133,6 +1133,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \\\n \tmt7622-rfb.dtb \\\n \tmt7623a-unielec-u7623-02-emmc.dtb \\\n \tmt7622-bananapi-bpi-r64.dtb \\\n+\tmt7622-linksys-e8450-ubi.dtb \\\n \tmt7623n-bananapi-bpi-r2.dtb \\\n \tmt7629-rfb.dtb \\\n \tmt8183-pumpkin.dtb \\\n--- /dev/null\n+++ b/linksys_e8450_env\n@@ -0,0 +1,57 @@\n+ethaddr_factory=mtd read spi-nand0 0x40080000 0x220000 0x20000 && env readmem -b ethaddr 0x4009fff4 0x6 ; setenv ethaddr_factory\n+ipaddr=192.168.1.1\n+serverip=192.168.1.254\n+loadaddr=0x48000000\n+bootcmd=if pstore check ; then run boot_recovery ; else run boot_ubi ; fi\n+bootconf=config-1\n+bootdelay=0\n+bootfile=openwrt-mediatek-mt7622-linksys_e8450-ubi-initramfs-recovery.itb\n+bootfile_bl2=openwrt-mediatek-mt7622-linksys_e8450-ubi-preloader.bin\n+bootfile_fip=openwrt-mediatek-mt7622-linksys_e8450-ubi-bl31-uboot.fip\n+bootfile_upg=openwrt-mediatek-mt7622-linksys_e8450-ubi-squashfs-sysupgrade.itb\n+bootled_pwr=power:blue\n+bootled_rec=inet:orange on\n+bootmenu_confirm_return=askenv - Press ENTER to return to menu ; bootmenu 60\n+bootmenu_default=0\n+bootmenu_delay=0\n+bootmenu_title=      \u001b[0;34m( ( ( \u001b[1;39mOpenWrt\u001b[0;34m ) ) )\u001b[0m\n+bootmenu_0=Initialize environment.=run _firstboot\n+bootmenu_0d=Run default boot command.=run boot_default\n+bootmenu_1=Boot system via TFTP.=run boot_tftp ; run bootmenu_confirm_return\n+bootmenu_2=Boot production system from flash.=run boot_production ; run bootmenu_confirm_return\n+bootmenu_3=Boot recovery system from flash.=run boot_recovery ; run bootmenu_confirm_return\n+bootmenu_4=Load production system via TFTP then write to flash.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_production ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return\n+bootmenu_5=Load recovery system via TFTP then write to flash.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_recovery ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return\n+bootmenu_6=\u001b[31mLoad BL31+U-Boot FIP via TFTP then write to flash.\u001b[0m=run boot_tftp_write_fip ; run bootmenu_confirm_return\n+bootmenu_7=\u001b[31mLoad BL2 preloader via TFTP then write to flash.\u001b[0m=run boot_tftp_write_bl2 ; run bootmenu_confirm_return\n+bootmenu_8=Reboot.=reset\n+bootmenu_9=Reset all settings to factory defaults.=run reset_factory ; reset\n+boot_first=if button reset ; then led $bootled_rec on ; run boot_tftp_recovery ; setenv flag_recover 1 ; run boot_default ; fi ; bootmenu\n+boot_default=if env exists flag_recover ; then else run bootcmd ; fi ; run boot_recovery ; setenv replacevol 1 ; run boot_tftp_forever\n+boot_production=led $bootled_pwr on ; run ubi_read_production && bootm $loadaddr#$bootconf ; led $bootled_pwr off\n+boot_recovery=led $bootled_rec on ; run ubi_read_recovery ; bootm $loadaddr#$bootconf ; ubi remove recovery ; led $bootled_rec off\n+boot_serial_write_bl2=loadx $loadaddr 115200 && run boot_write_bl2\n+boot_serial_write_fip=loadx $loadaddr 115200 && run boot_write_fip\n+boot_tftp=tftpboot $loadaddr $bootfile && bootm $loadaddr#$bootconf\n+boot_tftp_forever=led $bootled_rec on ; while true ; do run boot_tftp_recovery ; sleep 1 ; done\n+boot_tftp_production=tftpboot $loadaddr $bootfile_upg && iminfo $loadaddr && ubi part ubi && run ubi_write_production ubi_prepare_rootfs ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi\n+boot_tftp_recovery=tftpboot $loadaddr $bootfile && iminfo $loadaddr && ubi part ubi && run ubi_write_recovery ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi\n+boot_tftp_write_bl2=tftpboot $loadaddr $bootfile_bl2 && run boot_write_bl2\n+boot_tftp_write_fip=tftpboot $loadaddr $bootfile_fip && run boot_write_fip\n+boot_ubi=ubi part ubi && run boot_production ; run boot_recovery\n+boot_write_bl2=mtd erase bl2 && mtd write spi-nand0 $loadaddr 0x0 0x20000 && mtd write spi-nand0 $loadaddr 0x20000 0x20000 && mtd write spi-nand0 $loadaddr 0x40000 0x20000 && mtd write spi-nand0 $loadaddr 0x60000 0x20000\n+boot_write_fip=mtd erase fip && mtd write fip $loadaddr\n+check_ubi=ubi part ubi || run ubi_format\n+reset_factory=ubi part ubi ; ubi write 0x0 ubootenv 0x0 ; ubi write 0x0 ubootenv2 0x0 ; ubi remove rootfs_data\n+ubi_format=ubi detach ; mtd erase ubi && ubi part ubi ; reset\n+ubi_prepare_rootfs=if ubi check rootfs_data ; then else if env exists rootfs_data_max ; then ubi create rootfs_data $rootfs_data_max dynamic || ubi create rootfs_data - dynamic ; else ubi create rootfs_data - dynamic ; fi ; fi\n+ubi_read_production=ubi read $loadaddr fit && iminfo $loadaddr && run ubi_prepare_rootfs\n+ubi_read_recovery=ubi check recovery && ubi read $loadaddr recovery\n+ubi_remove_rootfs=ubi check rootfs_data && ubi remove rootfs_data\n+ubi_write_production=ubi check fit && env exists replacevol && ubi remove fit ; if ubi check fit ; then else run ubi_remove_rootfs ; ubi create fit $filesize dynamic && ubi write $loadaddr fit $filesize ; fi\n+ubi_write_recovery=ubi check recovery && env exists replacevol && ubi remove recovery ; if ubi check recovery ; then else run ubi_remove_rootfs ; ubi create recovery $filesize dynamic && ubi write $loadaddr recovery $filesize ; fi\n+_create_env=ubi create ubootenv 0x100000 dynamic ; ubi create ubootenv2 0x100000 dynamic\n+_init_env=setenv _init_env ; if ubi check ubootenv && ubi check ubootenv2 ; then else run _create_env ; fi ; setenv _create_env ; saveenv || run ubi_format ; saveenv || run ubi_format\n+_firstboot=setenv _firstboot ; run _switch_to_menu ; run ethaddr_factory ; run check_ubi ; run _init_env ; run boot_first\n+_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title\n+_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title \"$bootmenu_title       \u001b[33m$ver\u001b[0m\"\n"
  },
  {
    "path": "package/boot/uboot-mediatek/patches/412-add-ubnt-unifi-6-lr.patch",
    "content": "--- /dev/null\n+++ b/configs/mt7622_ubnt_unifi-6-lr_defconfig\n@@ -0,0 +1,141 @@\n+CONFIG_ARM=y\n+CONFIG_POSITION_INDEPENDENT=y\n+CONFIG_ARCH_MEDIATEK=y\n+CONFIG_TARGET_MT7622=y\n+CONFIG_SYS_TEXT_BASE=0x41e00000\n+CONFIG_SYS_MALLOC_F_LEN=0x4000\n+CONFIG_SYS_LOAD_ADDR=0x40080000\n+CONFIG_USE_DEFAULT_ENV_FILE=y\n+CONFIG_MTDPARTS_DEFAULT=\"mtdparts=nor0:128k(bl2),640k(fip),64k(u-boot-env),256k(factory),64k(eeprom),15232k(recovery),-(firmware)\"\n+CONFIG_ENV_IS_IN_MTD=y\n+CONFIG_ENV_MTD_NAME=\"nor0\"\n+CONFIG_ENV_SIZE_REDUND=0x4000\n+CONFIG_ENV_SIZE=0x4000\n+CONFIG_ENV_OFFSET=0xc0000\n+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y\n+CONFIG_BOARD_LATE_INIT=y\n+CONFIG_RESET_BUTTON_SETTLE_DELAY=400\n+CONFIG_BOOTP_SEND_HOSTNAME=y\n+CONFIG_DEFAULT_ENV_FILE=\"ubnt_unifi-6-lr_env\"\n+CONFIG_DEBUG_UART_BASE=0x11002000\n+CONFIG_DEBUG_UART_CLOCK=25000000\n+CONFIG_DEFAULT_DEVICE_TREE=\"mt7622-ubnt-unifi-6-lr\"\n+CONFIG_DEBUG_UART=y\n+CONFIG_SMBIOS_PRODUCT_NAME=\"\"\n+CONFIG_AUTOBOOT_KEYED=y\n+CONFIG_BOOTDELAY=30\n+CONFIG_AUTOBOOT_MENU_SHOW=y\n+CONFIG_CFB_CONSOLE_ANSI=y\n+CONFIG_BUTTON=y\n+CONFIG_BUTTON_GPIO=y\n+CONFIG_GPIO_HOG=y\n+CONFIG_CMD_ENV_FLAGS=y\n+CONFIG_FIT=y\n+CONFIG_FIT_ENABLE_SHA256_SUPPORT=y\n+CONFIG_LOGLEVEL=7\n+CONFIG_LOG=y\n+CONFIG_DEFAULT_FDT_FILE=\"mt7622-ubnt-unifi-6-lr\"\n+CONFIG_SYS_PROMPT=\"MT7622> \"\n+# CONFIG_LEGACY_IMAGE_FORMAT is not set\n+# CONFIG_BOOTM_PLAN9 is not set\n+# CONFIG_BOOTM_RTEMS is not set\n+# CONFIG_BOOTM_VXWORKS is not set\n+# CONFIG_EFI is not set\n+# CONFIG_EFI_LOADER is not set\n+CONFIG_CMD_BOOTMENU=y\n+# CONFIG_CMD_BOOTEFI is not set\n+CONFIG_CMD_BOOTP=y\n+CONFIG_CMD_BUTTON=y\n+CONFIG_CMD_CDP=y\n+CONFIG_CMD_DHCP=y\n+CONFIG_CMD_DNS=y\n+CONFIG_CMD_ECHO=y\n+# CONFIG_CMD_ELF is not set\n+# CONFIG_CMD_BOOTEFI_BOOTMGR is not set\n+CONFIG_CMD_ENV_READMEM=y\n+CONFIG_CMD_ERASEENV=y\n+CONFIG_CMD_GPIO=y\n+CONFIG_CMD_HASH=y\n+CONFIG_CMD_ITEST=y\n+CONFIG_CMD_LED=y\n+CONFIG_CMD_LINK_LOCAL=y\n+# CONFIG_CMD_MBR is not set\n+CONFIG_CMD_MTD=y\n+CONFIG_CMD_MTDPART=y\n+# CONFIG_CMD_PCI is not set\n+CONFIG_CMD_SF_TEST=y\n+CONFIG_CMD_PING=y\n+CONFIG_CMD_PXE=y\n+CONFIG_CMD_SMC=y\n+CONFIG_CMD_TFTPBOOT=y\n+CONFIG_CMD_TFTPSRV=y\n+# CONFIG_CMD_UNLZ4 is not set\n+CONFIG_CMD_ASKENV=y\n+CONFIG_CMD_PSTORE=y\n+CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000\n+CONFIG_CMD_RARP=y\n+CONFIG_CMD_SETEXPR=y\n+CONFIG_CMD_SLEEP=y\n+CONFIG_CMD_SOURCE=y\n+CONFIG_CMD_UUID=y\n+CONFIG_DISPLAY_CPUINFO=y\n+CONFIG_DM_ETH=y\n+CONFIG_DM_ETH_PHY=y\n+CONFIG_DM_GPIO=y\n+CONFIG_DM_MDIO=y\n+CONFIG_DM_MTD=y\n+CONFIG_DM_REGULATOR=y\n+CONFIG_DM_REGULATOR_FIXED=y\n+CONFIG_DM_REGULATOR_GPIO=y\n+# CONFIG_DM_MMC is not set\n+CONFIG_DM_SERIAL=y\n+CONFIG_DM_SPI=y\n+CONFIG_DM_SPI_FLASH=y\n+CONFIG_HUSH_PARSER=y\n+# CONFIG_PARTITION_UUIDS is not set\n+CONFIG_SYS_RELOC_GD_ENV_ADDR=y\n+# CONFIG_LED is not set\n+# CONFIG_LZ4 is not set\n+CONFIG_VERSION_VARIABLE=y\n+CONFIG_NETCONSOLE=y\n+CONFIG_REGMAP=y\n+CONFIG_SYSCON=y\n+CONFIG_CLK=y\n+CONFIG_PHY=y\n+CONFIG_PHY_FIXED=y\n+CONFIG_PHYLIB_10G=y\n+CONFIG_PHY_AQUANTIA=y\n+CONFIG_PHY_ADDR_ENABLE=y\n+CONFIG_PHY_ADDR=8\n+CONFIG_MEDIATEK_ETH=y\n+CONFIG_MTD=y\n+# CONFIG_MMC is not set\n+CONFIG_PINCTRL=y\n+CONFIG_PINCONF=y\n+CONFIG_PINCTRL_MT7622=y\n+CONFIG_POWER_DOMAIN=y\n+CONFIG_PRE_CONSOLE_BUFFER=y\n+CONFIG_PRE_CON_BUF_ADDR=0x4007EF00\n+CONFIG_MTK_POWER_DOMAIN=y\n+CONFIG_RAM=y\n+CONFIG_MTK_SERIAL=y\n+CONFIG_SPI=y\n+CONFIG_MTK_SNFI_SPI=y\n+CONFIG_MTK_SNOR=y\n+CONFIG_SYSRESET_WATCHDOG=y\n+CONFIG_WDT_MTK=y\n+CONFIG_HEXDUMP=y\n+CONFIG_RANDOM_UUID=y\n+CONFIG_REGEX=y\n+CONFIG_SPI_FLASH=y\n+CONFIG_SPI_FLASH_BAR=y\n+CONFIG_SPI_FLASH_MTD=y\n+CONFIG_SPI_FLASH_UNLOCK_ALL=y\n+CONFIG_SPI_FLASH_EON=y\n+CONFIG_SPI_FLASH_GIGADEVICE=y\n+CONFIG_SPI_FLASH_MACRONIX=y\n+CONFIG_SPI_FLASH_SPANSION=y\n+CONFIG_SPI_FLASH_STMICRO=y\n+CONFIG_SPI_FLASH_SST=y\n+CONFIG_SPI_FLASH_WINBOND=y\n+CONFIG_SPI_FLASH_XMC=y\n--- /dev/null\n+++ b/arch/arm/dts/mt7622-ubnt-unifi-6-lr.dts\n@@ -0,0 +1,202 @@\n+// SPDX-License-Identifier: GPL-2.0\n+/*\n+ * Copyright (c) 2019 MediaTek Inc.\n+ * Author: Sam Shih <sam.shih@mediatek.com>\n+ */\n+\n+/dts-v1/;\n+#include \"mt7622.dtsi\"\n+#include \"mt7622-u-boot.dtsi\"\n+\n+/ {\n+\t#address-cells = <1>;\n+\t#size-cells = <1>;\n+\tmodel = \"mt7622-ubnt-unifi-6-lr\";\n+\tcompatible = \"mediatek,mt7622\", \"ubnt,unifi-6-lr\";\n+\n+\tchosen {\n+\t\tstdout-path = &uart0;\n+\t\ttick-timer = &timer0;\n+\t};\n+\n+\taliases {\n+\t\tspi0 = &snor;\n+\t};\n+\n+\tgpio-keys {\n+\t\tcompatible = \"gpio-keys\";\n+\t\tu-boot,dm-pre-reloc;\n+\n+\t\treset {\n+\t\t\tlabel = \"reset\";\n+\t\t\tgpios = <&gpio 62 GPIO_ACTIVE_LOW>;\n+\t\t\tu-boot,dm-pre-reloc;\n+\t\t};\n+\t};\n+\n+\tmemory@40000000 {\n+\t\tdevice_type = \"memory\";\n+\t\treg = <0x40000000 0x20000000>;\n+\t};\n+\n+\treg_1p8v: regulator-1p8v {\n+\t\tcompatible = \"regulator-fixed\";\n+\t\tregulator-name = \"fixed-1.8V\";\n+\t\tregulator-min-microvolt = <1800000>;\n+\t\tregulator-max-microvolt = <1800000>;\n+\t\tregulator-boot-on;\n+\t\tregulator-always-on;\n+\t};\n+\n+\treg_3p3v: regulator-3p3v {\n+\t\tcompatible = \"regulator-fixed\";\n+\t\tregulator-name = \"fixed-3.3V\";\n+\t\tregulator-min-microvolt = <3300000>;\n+\t\tregulator-max-microvolt = <3300000>;\n+\t\tregulator-boot-on;\n+\t\tregulator-always-on;\n+\t};\n+\n+\treg_5v: regulator-5v {\n+\t\tcompatible = \"regulator-fixed\";\n+\t\tregulator-name = \"fixed-5V\";\n+\t\tregulator-min-microvolt = <5000000>;\n+\t\tregulator-max-microvolt = <5000000>;\n+\t\tregulator-boot-on;\n+\t\tregulator-always-on;\n+\t};\n+};\n+\n+&pcie {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pcie0_pins>, <&pcie1_pins>;\n+\tstatus = \"okay\";\n+\n+\tpcie@0,0 {\n+\t\tstatus = \"okay\";\n+\t};\n+\n+\tpcie@1,0 {\n+\t\tstatus = \"okay\";\n+\t};\n+};\n+\n+&pinctrl {\n+\teth_pins: eth-pins {\n+\t\tmux {\n+\t\t\tfunction = \"eth\";\n+\t\t\tgroups = \"mdc_mdio\", \"rgmii_via_gmac2\";\n+\t\t};\n+\t};\n+\n+\tpcie0_pins: pcie0-pins {\n+\t\tmux {\n+\t\t\tfunction = \"pcie\";\n+\t\t\tgroups = \"pcie0_pad_perst\",\n+\t\t\t\t \"pcie0_1_waken\",\n+\t\t\t\t \"pcie0_1_clkreq\";\n+\t\t};\n+\t};\n+\n+\tpcie1_pins: pcie1-pins {\n+\t\tmux {\n+\t\t\tfunction = \"pcie\";\n+\t\t\tgroups = \"pcie1_pad_perst\",\n+\t\t\t\t \"pcie1_0_waken\",\n+\t\t\t\t \"pcie1_0_clkreq\";\n+\t\t};\n+\t};\n+\n+\tsnfi_pins: snfi-pins {\n+\t\tmux {\n+\t\t\tfunction = \"flash\";\n+\t\t\tgroups = \"snfi\";\n+\t\t};\n+\t};\n+\n+\tsnor_pins: snor-pins {\n+\t\tmux {\n+\t\t\tfunction = \"flash\";\n+\t\t\tgroups = \"spi_nor\";\n+\t\t};\n+\t};\n+\n+\tuart0_pins: uart0 {\n+\t\tmux {\n+\t\t\tfunction = \"uart\";\n+\t\t\tgroups = \"uart0_0_tx_rx\" ;\n+\t\t};\n+\t};\n+\n+\twatchdog_pins: watchdog-default {\n+\t\tmux {\n+\t\t\tfunction = \"watchdog\";\n+\t\t\tgroups = \"watchdog\";\n+\t\t};\n+\t};\n+};\n+\n+&snfi {\n+\tpinctrl-names = \"default\", \"snfi\";\n+\tpinctrl-0 = <&snor_pins>;\n+\tpinctrl-1 = <&snfi_pins>;\n+\tstatus = \"okay\";\n+\n+\tspi-flash@0 {\n+\t\tcompatible = \"jedec,spi-nor\";\n+\t\treg = <0>;\n+\t\tu-boot,dm-pre-reloc;\n+\t};\n+};\n+\n+&snor {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&snor_pins>;\n+\tstatus = \"okay\";\n+\n+\tspi-flash@0 {\n+\t\tcompatible = \"jedec,spi-nor\";\n+\t\treg = <0>;\n+\t\tspi-tx-bus-width = <1>;\n+\t\tspi-rx-bus-width = <4>;\n+\t\tu-boot,dm-pre-reloc;\n+\t};\n+};\n+\n+&uart0 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&uart0_pins>;\n+\tstatus = \"okay\";\n+};\n+\n+&watchdog {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&watchdog_pins>;\n+\tstatus = \"okay\";\n+};\n+\n+&eth {\n+\tstatus = \"okay\";\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&eth_pins>;\n+\n+\tmediatek,gmac-id = <0>;\n+\tphy-mode = \"sgmii\";\n+\tphy-handle = <&gphy>;\n+\n+\tfixed-link {\n+\t\tspeed = <1000>;\n+\t\tfull-duplex;\n+\t};\n+\n+\tmdio-bus {\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\n+\t\tgphy: ethernet-phy@8 {\n+\t\t\t/* Marvell AQRate AQR112W - no driver */\n+\t\t\tcompatible = \"ethernet-phy-ieee802.3-c45\";\n+\t\t\treg = <0x8>;\n+\t\t};\n+\t};\n+};\n--- a/arch/arm/dts/Makefile\n+++ b/arch/arm/dts/Makefile\n@@ -1134,6 +1134,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \\\n \tmt7623a-unielec-u7623-02-emmc.dtb \\\n \tmt7622-bananapi-bpi-r64.dtb \\\n \tmt7622-linksys-e8450-ubi.dtb \\\n+\tmt7622-ubnt-unifi-6-lr.dtb \\\n \tmt7623n-bananapi-bpi-r2.dtb \\\n \tmt7629-rfb.dtb \\\n \tmt8183-pumpkin.dtb \\\n--- /dev/null\n+++ b/ubnt_unifi-6-lr_env\n@@ -0,0 +1,50 @@\n+ethaddr_factory=mtd read nor0 $loadaddr 0x110000 0x10000 && env readmem -b ethaddr $loadaddr 0x6 ; setenv ethaddr_factory\n+ipaddr=192.168.1.1\n+serverip=192.168.1.254\n+loadaddr=0x48000000\n+bootcmd=if pstore check ; then run boot_recovery ; else run boot_nor ; fi\n+bootdelay=0\n+bootfile=openwrt-mediatek-mt7622-ubnt_unifi-6-lr-ubootmod-initramfs-recovery.itb\n+bootfile_bl2=openwrt-mediatek-mt7622-ubnt_unifi-6-lr-ubootmod-preloader.bin\n+bootfile_fip=openwrt-mediatek-mt7622-ubnt_unifi-6-lr-ubootmod-bl31-uboot.fip\n+bootfile_upg=openwrt-mediatek-mt7622-ubnt_unifi-6-lr-ubootmod-squashfs-sysupgrade.itb\n+bootmenu_confirm_return=askenv - Press ENTER to return to menu ; bootmenu 60\n+bootmenu_default=0\n+bootmenu_delay=0\n+bootmenu_title=      \u001b[0;34m( ( ( \u001b[1;39mOpenWrt\u001b[0;34m ) ) )\u001b[0m\n+bootmenu_0=Initialize environment.=run _firstboot\n+bootmenu_0d=Run default boot command.=run boot_default\n+bootmenu_1=Boot system via TFTP.=run boot_tftp ; run bootmenu_confirm_return\n+bootmenu_2=Boot production system from flash.=run boot_production ; run bootmenu_confirm_return\n+bootmenu_3=Boot recovery system from flash.=run boot_recovery ; run bootmenu_confirm_return\n+bootmenu_4=Load production system via TFTP then write to flash.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_production ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return\n+bootmenu_5=Load recovery system via TFTP then write to flash.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_recovery ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return\n+bootmenu_6=\u001b[31mLoad BL31+U-Boot FIP via TFTP then write to flash.\u001b[0m=run boot_tftp_write_fip ; run bootmenu_confirm_return\n+bootmenu_7=\u001b[31mLoad BL2 preloader via TFTP then write to flash.\u001b[0m=run boot_tftp_write_preloader ; run bootmenu_confirm_return\n+bootmenu_8=Reboot.=reset\n+bootmenu_9=Reset all settings to factory defaults.=run reset_factory ; reset\n+boot_first=if button reset ; then run boot_tftp_recovery ; setenv flag_recover 1 ; run boot_default ; fi ; bootmenu\n+boot_default=if env exists flag_recover ; then else run bootcmd ; fi ; run boot_recovery ; setenv replacevol 1 ; run boot_tftp_forever\n+boot_production=run nor_read_production && bootm $loadaddr\n+boot_recovery=run nor_read_recovery ; bootm $loadaddr\n+boot_serial_write_fip=loadx $loadaddr 115200 && run boot_write_fip\n+boot_serial_write_preloader=loadx $loadaddr 115200 && run boot_write_preloader\n+boot_tftp_forever=while true ; do run boot_tftp_recovery ; sleep 1 ; done\n+boot_tftp_production=tftpboot $loadaddr $bootfile_upg && env exists replacevol && iminfo $loadaddr && run nor_write_production ; if env exists noboot ; then else bootm $loadaddr ; fi\n+boot_tftp_recovery=tftpboot $loadaddr $bootfile && env exists replacevol && iminfo $loadaddr && run nor_write_recovery ; if env exists noboot ; then else bootm $loadaddr ; fi\n+boot_tftp=tftpboot $loadaddr $bootfile && bootm $loadaddr\n+boot_tftp_write_fip=tftpboot $loadaddr $bootfile_fip && run boot_write_fip\n+boot_tftp_write_preloader=tftpboot $loadaddr $bootfile_bl2 && run boot_write_preloader\n+boot_nor=run boot_production ; run boot_recovery\n+boot_write_fip=mtd erase nor0 0x20000 0x80000 && mtd write nor0 $loadaddr 0x20000 0x80000\n+boot_write_preloader=mtd erase nor0 0x0 0x20000 && mtd write nor0 $loadaddr 0x0 0x20000\n+reset_factory=mtd erase nor0 0xc0000 0x10000 && reset\n+nor_read_production=mtd read nor0 $loadaddr 0x1000000 0x1000 && imsz $loadaddr image_size && mtd read nor0 $loadaddr 0x1000000 $image_size\n+nor_read_recovery=mtd read nor0 $loadaddr 0x120000 0x1000 && imsz $loadaddr image_size && mtd read nor0 $loadaddr 0x120000 $image_size\n+nor_pad_size=imsz $loadaddr image_size ; setexpr image_eb $image_size / 0x1000 ; setexpr tmp1 image_size % 0x1000 ; test 0x$tmp1 -gt 0 && setexpr image_eb $image_eb + 1 ; setexpr image_eb $image_eb * 0x1000\n+nor_write_production=run nor_pad_size ; test 0x$image_eb -le 0x3000000 && mtd erase nor0 0x1000000 0x$image_eb && mtd write nor0 $loadaddr 0x1000000 $filesize\n+nor_write_recovery=run nor_pad_size ; test 0x$image_eb -le 0xee0000 && mtd erase nor0 0x120000 0x$image_eb && mtd write nor0 $loadaddr 0x120000 $filesize\n+_init_env=setenv _init_env ; saveenv\n+_firstboot=setenv _firstboot ; run _switch_to_menu ; run ethaddr_factory ; run _init_env ; run boot_first\n+_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title\n+_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title \"$bootmenu_title       \u001b[33m$ver\u001b[0m\"\n--- a/common/board_r.c\n+++ b/common/board_r.c\n@@ -78,6 +78,7 @@\n #ifdef CONFIG_EFI_SETUP_EARLY\n #include <efi_loader.h>\n #endif\n+#include <spi_flash.h>\n \n DECLARE_GLOBAL_DATA_PTR;\n \n@@ -417,6 +418,21 @@ static int initr_onenand(void)\n }\n #endif\n \n+#if defined(CONFIG_SPI_FLASH)\n+/* probe SPI FLASH */\n+static int initr_spiflash(void)\n+{\n+\tstruct udevice *new;\n+\n+\tspi_flash_probe_bus_cs(CONFIG_SF_DEFAULT_BUS,\n+\t\t\t\tCONFIG_SF_DEFAULT_CS,\n+\t\t\t\tCONFIG_SF_DEFAULT_SPEED,\n+\t\t\t\tCONFIG_SF_DEFAULT_MODE,\n+\t\t\t\t&new);\n+\treturn 0;\n+}\n+#endif\n+\n #ifdef CONFIG_MMC\n static int initr_mmc(void)\n {\n@@ -705,6 +721,9 @@ static init_fnc_t init_sequence_r[] = {\n #ifdef CONFIG_CMD_ONENAND\n \tinitr_onenand,\n #endif\n+#ifdef CONFIG_SPI_FLASH\n+\tinitr_spiflash,\n+#endif\n #ifdef CONFIG_MMC\n \tinitr_mmc,\n #endif\n"
  },
  {
    "path": "package/boot/uboot-mediatek/patches/500-board-mt7623-fix-mmc-detect.patch",
    "content": "--- a/board/mediatek/mt7623/mt7623_rfb.c\n+++ b/board/mediatek/mt7623/mt7623_rfb.c\n@@ -9,6 +9,7 @@\n #include <env.h>\n #include <init.h>\n #include <mmc.h>\n+#include <part.h>\n #include <asm/global_data.h>\n #include <linux/delay.h>\n \n@@ -31,8 +32,9 @@ int mmc_get_boot_dev(void)\n {\n \tint g_mmc_devid = -1;\n \tchar *uflag = (char *)0x81DFFFF0;\n+\tstruct blk_desc *desc;\n \n-\tif (!find_mmc_device(1))\n+\tif (blk_get_device_by_str(\"mmc\", \"1\", &desc) < 0)\n \t\treturn 0;\n \n \tif (strncmp(uflag,\"eMMC\",4)==0) {\n"
  },
  {
    "path": "package/boot/uboot-mvebu/Makefile",
    "content": "#\n# Copyright (C) 2016 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\ninclude $(INCLUDE_DIR)/kernel.mk\n\nPKG_VERSION:=2022.04\nPKG_RELEASE:=$(AUTORELEASE)\n\nPKG_HASH:=68e065413926778e276ec3abd28bb32fa82abaa4a6898d570c1f48fbdb08bcd0\n\ninclude $(INCLUDE_DIR)/u-boot.mk\ninclude $(INCLUDE_DIR)/package.mk\ninclude $(INCLUDE_DIR)/host-build.mk\n\ndefine U-Boot/Default\n  BUILD_TARGET:=mvebu\n  HIDDEN:=1\nendef\n\ndefine U-Boot/clearfog\n  NAME:=SolidRun ClearFog A1\n  BUILD_DEVICES:=solidrun_clearfog-base-a1 solidrun_clearfog-pro-a1\n  BUILD_SUBTARGET:=cortexa9\n  UBOOT_IMAGE:=u-boot-spl.kwb\nendef\n\ndefine U-Boot/helios4\n  NAME:=Kobol Helios 4\n  BUILD_DEVICES:=kobol_helios4\n  BUILD_SUBTARGET:=cortexa9\n  UBOOT_IMAGE:=u-boot-spl.kwb\nendef\n\ndefine U-Boot/omnia\n  NAME:=Turris Omnia\n  BUILD_DEVICES:=cznic_turris-omnia\n  BUILD_SUBTARGET:=cortexa9\n  UBOOT_CONFIG:=turris_omnia\n  UBOOT_IMAGE:=u-boot-spl.kwb\nendef\n\ndefine U-Boot/espressobin\n  NAME:=Marvell ESPRESSObin\n  BUILD_SUBTARGET:=cortexa53\n  UBOOT_CONFIG:=mvebu_espressobin-88f3720\nendef\n\ndefine U-Boot/uDPU\n  NAME:=Methode uDPU\n  BUILD_SUBTARGET:=cortexa53\nendef\n\nUBOOT_TARGETS:= \\\n\tclearfog \\\n\thelios4 \\\n\tomnia \\\n\tespressobin \\\n\tuDPU\n\ndefine Package/u-boot/install\n\t$(if $(findstring cortexa53,$(BUILD_SUBTARGET)),,$(Package/u-boot/install/default))\nendef\n\ndefine Build/InstallDev\n\t$(INSTALL_DIR) $(STAGING_DIR_IMAGE)\n\t$(CP) $(PKG_BUILD_DIR)/$(UBOOT_IMAGE) $(STAGING_DIR_IMAGE)/$(BUILD_VARIANT)-$(UBOOT_IMAGE)\nendef\n\n$(eval $(call BuildPackage/U-Boot))\n"
  },
  {
    "path": "package/boot/uboot-mvebu/patches/103-arm-mvebu-clearfog_defconfig-enable-setexpr-command.patch",
    "content": "From 40a67a9403deafdac05564b7350af49a71e12373 Mon Sep 17 00:00:00 2001\nFrom: Josef Schlehofer <pepe.schlehofer@gmail.com>\nDate: Fri, 29 Apr 2022 17:34:53 +0200\nSubject: [PATCH] arm: mvebu: clearfog_defconfig: enable setexpr command\n\nThis command is useful in U-boot scripts and it is being used by\nOpenWrt bootscript for this board [1]. Otherwise shell scripting\ncommands are enabled by default in cmd/Kconfig.\n\n[1] https://github.com/openwrt/openwrt/blob/852126680e21edc71c0c66561ae5a6d7479dcc67/target/linux/mvebu/image/clearfog.bootscript#L7\n\n[2] https://source.denx.de/u-boot/u-boot/-/blob/e95afa56753cebcd20a5114b6d121f281b789006/cmd/Kconfig#L1504\n\nFixes: 0299c90f396c5b2971a4bac596339f4b03661c27 (\"arm: mvebu: Add\nSolidRun ClearFog Armada 38x initial support\")\n\nSigned-off-by: Josef Schlehofer <pepe.schlehofer@gmail.com>\n---\n configs/clearfog_defconfig | 1 -\n 1 file changed, 1 deletion(-)\n\n--- a/configs/clearfog_defconfig\n+++ b/configs/clearfog_defconfig\n@@ -35,7 +35,6 @@ CONFIG_CMD_MMC=y\n CONFIG_CMD_PCI=y\n CONFIG_CMD_SPI=y\n CONFIG_CMD_USB=y\n-# CONFIG_CMD_SETEXPR is not set\n CONFIG_CMD_TFTPPUT=y\n CONFIG_CMD_CACHE=y\n CONFIG_CMD_TIME=y\n"
  },
  {
    "path": "package/boot/uboot-mxs/Makefile",
    "content": "#\n# Copyright (C) 2013-2016 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\ninclude $(INCLUDE_DIR)/kernel.mk\n\nPKG_VERSION:=2020.04\nPKG_RELEASE:=$(AUTORELEASE)\n\nPKG_HASH:=fe732aaf037d9cc3c0909bad8362af366ae964bbdac6913a34081ff4ad565372\n\ninclude $(INCLUDE_DIR)/u-boot.mk\ninclude $(INCLUDE_DIR)/package.mk\ninclude $(INCLUDE_DIR)/host-build.mk\n\ndefine U-Boot/Default\n  BUILD_TARGET:=mxs\n  UBOOT_IMAGE:=u-boot.sb\n  DEFAULT:=y\n  HIDDEN:=1\nendef\n\ndefine U-Boot/mx23_olinuxino\n  NAME:=Olinuxino i.MX233\nendef\n\ndefine U-Boot/duckbill\n  NAME:=I2SE Duckbill\nendef\n\nUBOOT_TARGETS := \\\n\tmx23_olinuxino \\\n\tduckbill\n\nUBOOT_MAKE_FLAGS += $(UBOOT_IMAGE)\n\ndefine Build/InstallDev\n\t$(INSTALL_DIR) $(STAGING_DIR_IMAGE)\n\t$(INSTALL_BIN) $(PKG_BUILD_DIR)/$(UBOOT_IMAGE) $(STAGING_DIR_IMAGE)/$(BUILD_VARIANT)-$(UBOOT_IMAGE)\nendef\n\n$(eval $(call BuildPackage/U-Boot))\n"
  },
  {
    "path": "package/boot/uboot-mxs/patches/001-add-i2se-duckbill.patch",
    "content": "From 83ee930c18b068c9a16b66c01aaa5d6e06570152 Mon Sep 17 00:00:00 2001\nFrom: Michael Heimpold <mhei@heimpold.de>\nDate: Sun, 19 Apr 2020 02:46:46 +0200\nSubject: [PATCH] arm: mxs: add support for I2SE's Duckbill boards\n\nThe Duckbill devices are small, pen-drive sized boards based on\nNXP's i.MX28 SoC. While the initial variants (Duckbill series) were\nequipped with a micro SD card slot only, the latest generation\n(Duckbill 2 series) have an additional internal eMMC onboard.\n\nBoth device generations consist of four \"family members\":\n\n- Duckbill/Duckbill 2: generic board, intended to be used as\n  baseboard for custom designs and/or as development board\n\n- Duckbill EnOcean/Duckbill 2 EnOcean: come with an EnOcean\n  daugther board equipped with the popular TCM310 module\n\n- Duckbill 485/Duckbill 2 485: as the name implies, these\n  devices are intended to be used as Ethernet - RS485 converters\n\n- Duckbill SPI/Duckbill 2 SPI: not sold separately, but used\n  in I2SE's development kits for Green PHY HomePlug Powerline\n  communication\n\nSigned-off-by: Michael Heimpold <mhei@heimpold.de>\nSigned-off-by: Stefan Wahren <stefan.wahren@i2se.com>\n---\n arch/arm/mach-imx/mxs/Kconfig   |   5 +\n board/i2se/duckbill/Kconfig     |  15 +++\n board/i2se/duckbill/MAINTAINERS |   6 +\n board/i2se/duckbill/Makefile    |  10 ++\n board/i2se/duckbill/duckbill.c  | 189 ++++++++++++++++++++++++++++++++\n board/i2se/duckbill/iomux.c     | 157 ++++++++++++++++++++++++++\n configs/duckbill_defconfig      |  43 ++++++++\n include/configs/duckbill.h      | 172 +++++++++++++++++++++++++++++\n 8 files changed, 597 insertions(+)\n create mode 100644 board/i2se/duckbill/Kconfig\n create mode 100644 board/i2se/duckbill/MAINTAINERS\n create mode 100644 board/i2se/duckbill/Makefile\n create mode 100644 board/i2se/duckbill/duckbill.c\n create mode 100644 board/i2se/duckbill/iomux.c\n create mode 100644 configs/duckbill_defconfig\n create mode 100644 include/configs/duckbill.h\n\ndiff --git a/arch/arm/mach-imx/mxs/Kconfig b/arch/arm/mach-imx/mxs/Kconfig\nindex b90d7b6e41..e7d8bc6792 100644\n--- a/arch/arm/mach-imx/mxs/Kconfig\n+++ b/arch/arm/mach-imx/mxs/Kconfig\n@@ -50,6 +50,10 @@ config TARGET_APX4DEVKIT\n config TARGET_BG0900\n \tbool \"Support bg0900\"\n \n+config TARGET_DUCKBILL\n+\tbool \"Support duckbill\"\n+\tselect BOARD_EARLY_INIT_F\n+\n config TARGET_MX28EVK\n \tbool \"Support mx28evk\"\n \tselect BOARD_EARLY_INIT_F\n@@ -70,6 +74,7 @@ config SYS_SOC\n \n source \"board/bluegiga/apx4devkit/Kconfig\"\n source \"board/freescale/mx28evk/Kconfig\"\n+source \"board/i2se/duckbill/Kconfig\"\n source \"board/liebherr/xea/Kconfig\"\n source \"board/ppcag/bg0900/Kconfig\"\n source \"board/schulercontrol/sc_sps_1/Kconfig\"\ndiff --git a/board/i2se/duckbill/Kconfig b/board/i2se/duckbill/Kconfig\nnew file mode 100644\nindex 0000000000..98c1e4689f\n--- /dev/null\n+++ b/board/i2se/duckbill/Kconfig\n@@ -0,0 +1,15 @@\n+if TARGET_DUCKBILL\n+\n+config SYS_BOARD\n+\tdefault \"duckbill\"\n+\n+config SYS_VENDOR\n+\tdefault \"i2se\"\n+\n+config SYS_SOC\n+\tdefault \"mxs\"\n+\n+config SYS_CONFIG_NAME\n+\tdefault \"duckbill\"\n+\n+endif\ndiff --git a/board/i2se/duckbill/MAINTAINERS b/board/i2se/duckbill/MAINTAINERS\nnew file mode 100644\nindex 0000000000..5496baa330\n--- /dev/null\n+++ b/board/i2se/duckbill/MAINTAINERS\n@@ -0,0 +1,6 @@\n+I2SE DUCKBILL BOARD\n+M:\tMichael Heimpold <mhei@heimpold.de>\n+S:\tMaintained\n+F:\tboard/i2se/duckbill/\n+F:\tinclude/configs/duckbill.h\n+F:\tconfigs/duckbill_defconfig\ndiff --git a/board/i2se/duckbill/Makefile b/board/i2se/duckbill/Makefile\nnew file mode 100644\nindex 0000000000..11bac98e4c\n--- /dev/null\n+++ b/board/i2se/duckbill/Makefile\n@@ -0,0 +1,10 @@\n+# SPDX-License-Identifier: GPL-2.0+\n+#\n+# (C) Copyright 2014-2020\n+# Michael Heimpold, mhei@heimpold.de.\n+\n+ifndef\tCONFIG_SPL_BUILD\n+obj-y\t:= duckbill.o\n+else\n+obj-y\t:= iomux.o\n+endif\ndiff --git a/board/i2se/duckbill/duckbill.c b/board/i2se/duckbill/duckbill.c\nnew file mode 100644\nindex 0000000000..93defc6c28\n--- /dev/null\n+++ b/board/i2se/duckbill/duckbill.c\n@@ -0,0 +1,189 @@\n+// SPDX-License-Identifier: GPL-2.0+\n+/*\n+ * I2SE Duckbill board\n+ *\n+ * Copyright (C) 2014-2020 Michael Heimpold <mhei@heimpold.de>\n+ */\n+\n+#include <common.h>\n+#include <asm/gpio.h>\n+#include <asm/io.h>\n+#include <asm/arch/imx-regs.h>\n+#include <asm/arch/iomux-mx28.h>\n+#include <asm/arch/clock.h>\n+#include <asm/arch/sys_proto.h>\n+#include <asm/setup.h>\n+#include <fdt_support.h>\n+#include <linux/mii.h>\n+#include <miiphy.h>\n+#include <netdev.h>\n+#include <errno.h>\n+#include <fuse.h>\n+\n+DECLARE_GLOBAL_DATA_PTR;\n+\n+static u32 system_rev;\n+static u32 serialno;\n+\n+/*\n+ * Functions\n+ */\n+int board_early_init_f(void)\n+{\n+\t/* IO0 clock at 480MHz */\n+\tmxs_set_ioclk(MXC_IOCLK0, 480000);\n+\t/* IO1 clock at 480MHz */\n+\tmxs_set_ioclk(MXC_IOCLK1, 480000);\n+\n+\t/* SSP0 clock at 96MHz */\n+\tmxs_set_sspclk(MXC_SSPCLK0, 96000, 0);\n+\n+\treturn 0;\n+}\n+\n+int dram_init(void)\n+{\n+\treturn mxs_dram_init();\n+}\n+\n+int board_init(void)\n+{\n+\t/* Adress of boot parameters */\n+\tgd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;\n+\n+\treturn 0;\n+}\n+\n+#ifdef CONFIG_CMD_MMC\n+int board_mmc_init(bd_t *bis)\n+{\n+\treturn mxsmmc_initialize(bis, 0, NULL, NULL);\n+}\n+#endif\n+\n+#ifdef CONFIG_CMD_NET\n+int board_eth_init(bd_t *bis)\n+{\n+\tunsigned int reset_gpio;\n+\tint ret;\n+\n+\tret = cpu_eth_init(bis);\n+\n+\tif (system_rev == 1)\n+\t\treset_gpio = MX28_PAD_SSP0_DATA7__GPIO_2_7;\n+\telse\n+\t\treset_gpio = MX28_PAD_GPMI_ALE__GPIO_0_26;\n+\n+\t/* Reset PHY */\n+\tgpio_request(reset_gpio, \"enet0_phy_rst\");\n+\tgpio_direction_output(reset_gpio, 0);\n+\tudelay(200);\n+\tgpio_set_value(reset_gpio, 1);\n+\n+\t/* give PHY some time to get out of the reset */\n+\tudelay(10000);\n+\n+\tret = fecmxc_initialize_multi(bis, 0, 0, MXS_ENET0_BASE);\n+\tif (ret) {\n+\t\tputs(\"FEC MXS: Unable to init FEC\\n\");\n+\t\treturn ret;\n+\t}\n+\n+\treturn ret;\n+}\n+\n+void mx28_adjust_mac(int dev_id, unsigned char *mac)\n+{\n+\tmac[0] = 0x00;\n+\tmac[1] = 0x01;\n+\tmac[2] = 0x87;\n+}\n+#endif\n+\n+#ifdef CONFIG_OF_BOARD_SETUP\n+int ft_board_setup(void *blob, bd_t *bd)\n+{\n+\tuint8_t enetaddr[6];\n+\tu32 mac = 0;\n+\n+#ifdef CONFIG_MXS_OCOTP\n+\t/* only Duckbill SPI has a MAC for the QCA7k */\n+\tfuse_read(0, 1, &mac);\n+#endif\n+\n+\tif (mac != 0) {\n+\t\tenetaddr[0] = 0x00;\n+\t\tenetaddr[1] = 0x01;\n+\t\tenetaddr[2] = 0x87;\n+\t\tenetaddr[3] = (mac >> 16) & 0xff;\n+\t\tenetaddr[4] = (mac >>  8) & 0xff;\n+\t\tenetaddr[5] =  mac        & 0xff;\n+\n+\t\tfdt_find_and_setprop(blob, \"spi1/ethernet@0\",\n+\t\t                     \"local-mac-address\", enetaddr, 6, 1);\n+\t}\n+\n+\treturn 0;\n+}\n+#endif\n+\n+#ifdef CONFIG_REVISION_TAG\n+u32 get_board_rev(void)\n+{\n+\treturn system_rev;\n+}\n+#endif\n+\n+#ifdef CONFIG_SERIAL_TAG\n+void get_board_serial(struct tag_serialnr *serialnr)\n+{\n+\tserialnr->low = serialno;\n+\tserialnr->high = 0;\n+}\n+#endif\n+\n+int misc_init_r(void)\n+{\n+\tunsigned int led_red_gpio;\n+\tchar *s;\n+\n+\t/* Board revision detection */\n+\tgpio_request(MX28_PAD_LCD_D17__GPIO_1_17, \"board_revision\");\n+\tgpio_direction_input(MX28_PAD_LCD_D17__GPIO_1_17);\n+\n+\t/* MX28_PAD_LCD_D17__GPIO_1_17: v1 = pull-down, v2 = pull-up */\n+\tsystem_rev =\n+\t\tgpio_get_value(MX28_PAD_LCD_D17__GPIO_1_17);\n+\tsystem_rev += 1;\n+\n+\t/* guess DT blob if not set in environment */\n+\tif (!env_get(\"fdt_file\")) {\n+\t\tif (system_rev == 1)\n+\t\t\tenv_set(\"fdt_file\", \"imx28-duckbill.dtb\");\n+\t\telse\n+\t\t\tenv_set(\"fdt_file\", \"imx28-duckbill-2.dtb\");\n+\t}\n+\n+\t/* enable red LED to indicate a running bootloader */\n+\tif (system_rev == 1)\n+\t\tled_red_gpio = MX28_PAD_AUART1_RX__GPIO_3_4;\n+\telse\n+\t\tled_red_gpio = MX28_PAD_SAIF0_LRCLK__GPIO_3_21;\n+\tgpio_request(led_red_gpio, \"led_red\");\n+\tgpio_direction_output(led_red_gpio, 1);\n+\n+\tif (system_rev == 1)\n+\t\tputs(\"Board: I2SE Duckbill\\n\");\n+\telse\n+\t\tputs(\"Board: I2SE Duckbill 2\\n\");\n+\n+\tserialno = env_get_ulong(\"serial#\", 10, 0);\n+\ts = env_get(\"serial#\");\n+\tif (s && s[0]) {\n+\t\tputs(\"Serial: \");\n+\t\tputs(s);\n+\t\tputc('\\n');\n+\t}\n+\n+\treturn 0;\n+}\ndiff --git a/board/i2se/duckbill/iomux.c b/board/i2se/duckbill/iomux.c\nnew file mode 100644\nindex 0000000000..c6cc211181\n--- /dev/null\n+++ b/board/i2se/duckbill/iomux.c\n@@ -0,0 +1,157 @@\n+// SPDX-License-Identifier: GPL-2.0+\n+/*\n+ * I2SE Duckbill IOMUX setup\n+ *\n+ * Copyright (C) 2013-2020 Michael Heimpold <mhei@heimpold.de>\n+ */\n+\n+#include <common.h>\n+#include <config.h>\n+#include <asm/io.h>\n+#include <asm/gpio.h>\n+#include <asm/arch/iomux-mx28.h>\n+#include <asm/arch/imx-regs.h>\n+#include <asm/arch/sys_proto.h>\n+\n+#define\tMUX_CONFIG_SSP0\t(MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)\n+#define\tMUX_CONFIG_ENET\t(MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)\n+#define\tMUX_CONFIG_EMI\t(MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL)\n+\n+/* For all revisions */\n+const iomux_cfg_t iomux_setup[] = {\n+\t/* DUART */\n+\tMX28_PAD_PWM0__DUART_RX,\n+\tMX28_PAD_PWM1__DUART_TX,\n+\n+\t/* eMMC (v2) or SD card (v1) */\n+\tMX28_PAD_SSP0_DATA0__SSP0_D0 | MUX_CONFIG_SSP0,\n+\tMX28_PAD_SSP0_DATA1__SSP0_D1 | MUX_CONFIG_SSP0,\n+\tMX28_PAD_SSP0_DATA2__SSP0_D2 | MUX_CONFIG_SSP0,\n+\tMX28_PAD_SSP0_DATA3__SSP0_D3 | MUX_CONFIG_SSP0,\n+\tMX28_PAD_SSP0_CMD__SSP0_CMD | MUX_CONFIG_SSP0,\n+\tMX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT |\n+\t\t(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),\n+\tMX28_PAD_SSP0_SCK__SSP0_SCK |\n+\t\t(MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),\n+\n+\t/* Ethernet */\n+\tMX28_PAD_ENET0_MDC__ENET0_MDC | MUX_CONFIG_ENET,\n+\tMX28_PAD_ENET0_MDIO__ENET0_MDIO | MUX_CONFIG_ENET,\n+\tMX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MUX_CONFIG_ENET,\n+\tMX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MUX_CONFIG_ENET,\n+\tMX28_PAD_ENET0_RXD0__ENET0_RXD0 | MUX_CONFIG_ENET,\n+\tMX28_PAD_ENET0_RXD1__ENET0_RXD1 | MUX_CONFIG_ENET,\n+\tMX28_PAD_ENET0_TXD0__ENET0_TXD0 | MUX_CONFIG_ENET,\n+\tMX28_PAD_ENET0_TXD1__ENET0_TXD1 | MUX_CONFIG_ENET,\n+\tMX28_PAD_ENET_CLK__CLKCTRL_ENET | MUX_CONFIG_ENET,\n+\n+\t/* EMI */\n+\tMX28_PAD_EMI_D00__EMI_DATA0 | MUX_CONFIG_EMI,\n+\tMX28_PAD_EMI_D01__EMI_DATA1 | MUX_CONFIG_EMI,\n+\tMX28_PAD_EMI_D02__EMI_DATA2 | MUX_CONFIG_EMI,\n+\tMX28_PAD_EMI_D03__EMI_DATA3 | MUX_CONFIG_EMI,\n+\tMX28_PAD_EMI_D04__EMI_DATA4 | MUX_CONFIG_EMI,\n+\tMX28_PAD_EMI_D05__EMI_DATA5 | MUX_CONFIG_EMI,\n+\tMX28_PAD_EMI_D06__EMI_DATA6 | MUX_CONFIG_EMI,\n+\tMX28_PAD_EMI_D07__EMI_DATA7 | MUX_CONFIG_EMI,\n+\tMX28_PAD_EMI_D08__EMI_DATA8 | MUX_CONFIG_EMI,\n+\tMX28_PAD_EMI_D09__EMI_DATA9 | MUX_CONFIG_EMI,\n+\tMX28_PAD_EMI_D10__EMI_DATA10 | MUX_CONFIG_EMI,\n+\tMX28_PAD_EMI_D11__EMI_DATA11 | MUX_CONFIG_EMI,\n+\tMX28_PAD_EMI_D12__EMI_DATA12 | MUX_CONFIG_EMI,\n+\tMX28_PAD_EMI_D13__EMI_DATA13 | MUX_CONFIG_EMI,\n+\tMX28_PAD_EMI_D14__EMI_DATA14 | MUX_CONFIG_EMI,\n+\tMX28_PAD_EMI_D15__EMI_DATA15 | MUX_CONFIG_EMI,\n+\tMX28_PAD_EMI_ODT0__EMI_ODT0 | MUX_CONFIG_EMI,\n+\tMX28_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI,\n+\tMX28_PAD_EMI_ODT1__EMI_ODT1 | MUX_CONFIG_EMI,\n+\tMX28_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI,\n+\tMX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK | MUX_CONFIG_EMI,\n+\tMX28_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI,\n+\tMX28_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI,\n+\tMX28_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI,\n+\tMX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN | MUX_CONFIG_EMI,\n+\n+\tMX28_PAD_EMI_A00__EMI_ADDR0 | MUX_CONFIG_EMI,\n+\tMX28_PAD_EMI_A01__EMI_ADDR1 | MUX_CONFIG_EMI,\n+\tMX28_PAD_EMI_A02__EMI_ADDR2 | MUX_CONFIG_EMI,\n+\tMX28_PAD_EMI_A03__EMI_ADDR3 | MUX_CONFIG_EMI,\n+\tMX28_PAD_EMI_A04__EMI_ADDR4 | MUX_CONFIG_EMI,\n+\tMX28_PAD_EMI_A05__EMI_ADDR5 | MUX_CONFIG_EMI,\n+\tMX28_PAD_EMI_A06__EMI_ADDR6 | MUX_CONFIG_EMI,\n+\tMX28_PAD_EMI_A07__EMI_ADDR7 | MUX_CONFIG_EMI,\n+\tMX28_PAD_EMI_A08__EMI_ADDR8 | MUX_CONFIG_EMI,\n+\tMX28_PAD_EMI_A09__EMI_ADDR9 | MUX_CONFIG_EMI,\n+\tMX28_PAD_EMI_A10__EMI_ADDR10 | MUX_CONFIG_EMI,\n+\tMX28_PAD_EMI_A11__EMI_ADDR11 | MUX_CONFIG_EMI,\n+\tMX28_PAD_EMI_A12__EMI_ADDR12 | MUX_CONFIG_EMI,\n+\tMX28_PAD_EMI_A13__EMI_ADDR13 | MUX_CONFIG_EMI,\n+\tMX28_PAD_EMI_A14__EMI_ADDR14 | MUX_CONFIG_EMI,\n+\tMX28_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI,\n+\tMX28_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI,\n+\tMX28_PAD_EMI_BA2__EMI_BA2 | MUX_CONFIG_EMI,\n+\tMX28_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI,\n+\tMX28_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI,\n+\tMX28_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI,\n+\tMX28_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI,\n+\tMX28_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI,\n+\tMX28_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI,\n+\n+\t/* Revision pin(s) */\n+\tMX28_PAD_LCD_D17__GPIO_1_17,\n+};\n+\n+/* For revision 1 only */\n+const iomux_cfg_t iomux_setup_v1[] = {\n+\t/* PHY reset */\n+\tMX28_PAD_SSP0_DATA7__GPIO_2_7 |\n+\t\t(MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),\n+\n+\t/* LEDs */\n+\tMX28_PAD_AUART1_RX__GPIO_3_4,\n+\tMX28_PAD_AUART1_TX__GPIO_3_5,\n+};\n+\n+/* For revision 2 only */\n+const iomux_cfg_t iomux_setup_v2[] = {\n+\t/* eMMC (v2) */\n+\tMX28_PAD_SSP0_DATA4__SSP0_D4 | MUX_CONFIG_SSP0,\n+\tMX28_PAD_SSP0_DATA5__SSP0_D5 | MUX_CONFIG_SSP0,\n+\tMX28_PAD_SSP0_DATA6__SSP0_D6 | MUX_CONFIG_SSP0,\n+\tMX28_PAD_SSP0_DATA7__SSP0_D7 | MUX_CONFIG_SSP0,\n+\n+\t/* PHY reset */\n+\tMX28_PAD_GPMI_ALE__GPIO_0_26 |\n+\t\t(MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),\n+\n+\t/* LEDs */\n+\tMX28_PAD_SAIF0_LRCLK__GPIO_3_21,\n+\tMX28_PAD_SAIF0_MCLK__GPIO_3_20,\n+};\n+\n+#define HW_DRAM_CTL29\t(0x74 >> 2)\n+#define CS_MAP\t\t0xf\n+#define COLUMN_SIZE\t0x2\n+#define ADDR_PINS\t0x1\n+#define APREBIT\t\t0xa\n+\n+#define HW_DRAM_CTL29_CONFIG\t(CS_MAP << 24 | COLUMN_SIZE << 16 | \\\n+\t\t\t\t\tADDR_PINS << 8 | APREBIT)\n+\n+void mxs_adjust_memory_params(uint32_t *dram_vals)\n+{\n+\tdram_vals[HW_DRAM_CTL29] = HW_DRAM_CTL29_CONFIG;\n+}\n+\n+void board_init_ll(const uint32_t arg, const uint32_t *resptr)\n+{\n+\tmxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup));\n+\n+\tgpio_request(MX28_PAD_LCD_D17__GPIO_1_17, \"board_revision\");\n+\tgpio_direction_input(MX28_PAD_LCD_D17__GPIO_1_17);\n+\n+\tif (gpio_get_value(MX28_PAD_LCD_D17__GPIO_1_17))\n+\t\tmxs_iomux_setup_multiple_pads(iomux_setup_v2, ARRAY_SIZE(iomux_setup_v2));\n+\telse\n+\t\tmxs_iomux_setup_multiple_pads(iomux_setup_v1, ARRAY_SIZE(iomux_setup_v1));\n+}\ndiff --git a/configs/duckbill_defconfig b/configs/duckbill_defconfig\nnew file mode 100644\nindex 0000000000..b2d7fbcf77\n--- /dev/null\n+++ b/configs/duckbill_defconfig\n@@ -0,0 +1,43 @@\n+CONFIG_ARM=y\n+CONFIG_ARCH_MX28=y\n+CONFIG_SYS_TEXT_BASE=0x40002000\n+CONFIG_SPL_GPIO_SUPPORT=y\n+CONFIG_SPL_LIBCOMMON_SUPPORT=y\n+CONFIG_SPL_LIBGENERIC_SUPPORT=y\n+CONFIG_TARGET_DUCKBILL=y\n+CONFIG_SPL_SERIAL_SUPPORT=y\n+CONFIG_ENV_SIZE=0x20000\n+CONFIG_ENV_OFFSET=0x20000\n+CONFIG_NR_DRAM_BANKS=1\n+CONFIG_SPL=y\n+CONFIG_SPL_TEXT_BASE=0x00001000\n+CONFIG_BOOTDELAY=1\n+CONFIG_SYS_CONSOLE_IS_IN_ENV=y\n+CONFIG_VERSION_VARIABLE=y\n+# CONFIG_DISPLAY_BOARDINFO is not set\n+CONFIG_ARCH_MISC_INIT=y\n+# CONFIG_SPL_FRAMEWORK is not set\n+CONFIG_HUSH_PARSER=y\n+CONFIG_CMD_BOOTZ=y\n+# CONFIG_CMD_ELF is not set\n+CONFIG_CMD_UNZIP=y\n+CONFIG_CMD_FUSE=y\n+CONFIG_CMD_GPIO=y\n+CONFIG_CMD_MMC=y\n+CONFIG_CMD_MMC_SWRITE=y\n+CONFIG_CMD_DHCP=y\n+CONFIG_CMD_MII=y\n+CONFIG_CMD_PING=y\n+CONFIG_CMD_EXT4=y\n+CONFIG_CMD_EXT4_WRITE=y\n+CONFIG_CMD_FS_GENERIC=y\n+CONFIG_DOS_PARTITION=y\n+CONFIG_ENV_IS_IN_MMC=y\n+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y\n+CONFIG_ENV_OFFSET_REDUND=0x40000\n+CONFIG_SYS_RELOC_GD_ENV_ADDR=y\n+CONFIG_MXS_GPIO=y\n+CONFIG_MMC_MXS=y\n+CONFIG_MII=y\n+CONFIG_CONS_INDEX=0\n+CONFIG_OF_LIBFDT=y\ndiff --git a/include/configs/duckbill.h b/include/configs/duckbill.h\nnew file mode 100644\nindex 0000000000..565d8c58b7\n--- /dev/null\n+++ b/include/configs/duckbill.h\n@@ -0,0 +1,172 @@\n+/* SPDX-License-Identifier: GPL-2.0+ */\n+/*\n+ * Copyright (C) 2014-2020 Michael Heimpold <mhei@heimpold.de>\n+ *\n+ */\n+#ifndef __CONFIGS_DUCKBILL_H__\n+#define __CONFIGS_DUCKBILL_H__\n+\n+/* System configurations */\n+#define CONFIG_MACH_TYPE\tMACH_TYPE_DUCKBILL\n+\n+#define CONFIG_MISC_INIT_R\n+\n+#define CONFIG_SYS_MXS_VDD5V_ONLY\n+\n+/* Memory configuration */\n+#define PHYS_SDRAM_1\t\t\t0x40000000\t/* Base address */\n+#define PHYS_SDRAM_1_SIZE\t\t0x40000000\t/* Max 1 GB RAM */\n+#define CONFIG_SYS_SDRAM_BASE\t\tPHYS_SDRAM_1\n+\n+/* Environment is in MMC */\n+#define CONFIG_ENV_OVERWRITE\n+#define CONFIG_SYS_MMC_ENV_DEV\t\t0\n+\n+/* FEC Ethernet on SoC */\n+#ifdef CONFIG_CMD_NET\n+#define CONFIG_FEC_MXC\n+#define CONFIG_MX28_FEC_MAC_IN_OCOTP\n+#define CONFIG_FEC_MXC_MDIO_BASE\tMXS_ENET0_BASE\n+#endif\n+\n+#define CONFIG_IPADDR\t\t192.168.1.10\n+#define CONFIG_SERVERIP\t\t192.168.1.1\n+#define CONFIG_NETMASK\t\t255.255.255.0\n+#define CONFIG_GATEWAYIP\t192.168.1.254\n+\n+/* Boot Linux */\n+#define CONFIG_BOOTDELAY\t1\n+#define CONFIG_BOOTFILE\t\t\"zImage\"\n+#define CONFIG_LOADADDR\t\t0x42000000\n+#define CONFIG_SYS_LOAD_ADDR\tCONFIG_LOADADDR\n+#define CONFIG_REVISION_TAG\n+#define CONFIG_SERIAL_TAG\n+#define CONFIG_OF_BOARD_SETUP\n+#define CONFIG_BOOT_RETRY_TIME\t\t120\t/* retry autoboot after 120 seconds */\n+#define CONFIG_AUTOBOOT_KEYED\n+#define CONFIG_AUTOBOOT_PROMPT\t\t\"Autobooting in %d seconds, \" \\\n+\t\t\t\t\t\"press <c> to stop\\n\"\n+#define CONFIG_AUTOBOOT_DELAY_STR\t\"\\x63\"\t/* allows retry after retry time */\n+#define CONFIG_AUTOBOOT_STOP_STR\t\" \"\t/* stop autoboot with <Space> */\n+#define CONFIG_RESET_TO_RETRY\t\t\t/* reset board to retry booting */\n+\n+/* Extra Environment */\n+#define CONFIG_EXTRA_ENV_SETTINGS \\\n+\t\"mmc_part2_offset=1000\\0\" \\\n+\t\"mmc_part3_offset=19000\\0\" \\\n+\t\"update_openwrt_firmware_filename=openwrt-mxs-root.ext4\\0\" \\\n+\t\"update_openwrt_firmware=\" \\\n+\t\t\"if mmc rescan; then \" \\\n+\t\t\t\"if tftp ${update_openwrt_firmware_filename}; then \" \\\n+\t\t\t\t\"setexpr fw_sz ${filesize} + 1ff; \" \\\n+\t\t\t\t\"setexpr fw_sz ${fw_sz} / 200; \" \\\n+\t\t\t\t\"mmc write ${loadaddr} ${mmc_part2_offset} ${fw_sz}; \" \\\n+\t\t\t\t\"mmc write ${loadaddr} ${mmc_part3_offset} ${fw_sz}; \" \\\n+\t\t\t\"fi; \" \\\n+\t\t\"fi\\0\" \\\n+\t\"update_fw_filename_prefix=emmc.img.\\0\" \\\n+\t\"update_fw_filename_suffix=.gz\\0\" \\\n+\t\"update_fw_parts=0x6\\0\" \\\n+\t\"update_fw_fsize_uncompressed=4000000\\0\" \\\n+\t\"gzwrite_wbuf=100000\\0\" \\\n+\t\"update_emmc_firmware=\" \\\n+\t\t\"setexpr i ${update_fw_parts}; setexpr error 0; \" \\\n+\t\t\"while itest ${i} -gt 0; do \" \\\n+\t\t\t\"echo Transfering firmware image part ${i} of ${update_fw_parts}; \" \\\n+\t\t\t\"if itest ${i} -le f; then \" \\\n+\t\t\t\t\"setenv j 0${i}; \" \\\n+\t\t\t\"else \" \\\n+\t\t\t\t\"setenv j ${i}; \" \\\n+\t\t\t\"fi; \" \\\n+\t\t\t\"if tftp ${loadaddr} ${update_fw_basedir}${update_fw_filename_prefix}${j}${update_fw_filename_suffix}; then \" \\\n+\t\t\t\t\"setexpr k ${i} - 1; \" \\\n+\t\t\t\t\"setexpr offset ${update_fw_fsize_uncompressed} * ${k}; \" \\\n+\t\t\t\t\"if gzwrite mmc ${mmcdev} ${loadaddr} ${filesize} ${gzwrite_wbuf} ${offset}; then \" \\\n+\t\t\t\t\t\"setexpr i ${i} - 1; \" \\\n+\t\t\t\t\"else \" \\\n+\t\t\t\t\t\"setexpr i 0; \" \\\n+\t\t\t\t\t\"setexpr error 1; \" \\\n+\t\t\t\t\"fi; \" \\\n+\t\t\t\"else \" \\\n+\t\t\t\t\"setexpr i 0; \" \\\n+\t\t\t\t\"setexpr error 1; \" \\\n+\t\t\t\"fi; \" \\\n+\t\t\"done; setenv i; setenv j; setenv k; setenv fsize; setenv filesize; setenv offset; \" \\\n+\t\t\"if test ${error} -eq 1; then \" \\\n+\t\t\t\"echo Firmware Update FAILED; \" \\\n+\t\t\"else \" \\\n+\t\t\t\"echo Firmware Update OK; \" \\\n+\t\t\"fi; setenv error\\0\" \\\n+\t\"image=zImage\\0\" \\\n+\t\"console=ttyAMA0\\0\" \\\n+\t\"fdt_addr=0x41000000\\0\" \\\n+\t\"boot_fdt=try\\0\" \\\n+\t\"ip_dyn=yes\\0\" \\\n+\t\"bootsys=1\\0\" \\\n+\t\"mmcdev=0\\0\" \\\n+\t\"mmcpart=2\\0\" \\\n+\t\"mmcroot=/dev/mmcblk0p2\\0\" \\\n+\t\"mmcargs=setenv bootargs console=${console},${baudrate} \" \\\n+\t\t\"root=${mmcroot} \" \\\n+\t\t\"rootwait bootsys=${bootsys} panic=1 ${extraargs}\\0\" \\\n+\t\"loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} /boot/${image}\\0\" \\\n+\t\"loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} /boot/${fdt_file}\\0\" \\\n+\t\"mmcboot=echo Booting from mmc ...; \" \\\n+\t\t\"setexpr mmcpart 1 + ${bootsys}; \" \\\n+\t\t\"setenv mmcroot /dev/mmcblk0p${mmcpart}; \" \\\n+\t\t\"run mmcargs; \" \\\n+\t\t\"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then \" \\\n+\t\t\t\"if run loadfdt; then \" \\\n+\t\t\t\t\"bootz ${loadaddr} - ${fdt_addr}; \" \\\n+\t\t\t\"else \" \\\n+\t\t\t\t\"if test ${boot_fdt} = try; then \" \\\n+\t\t\t\t\t\"bootz; \" \\\n+\t\t\t\t\"else \" \\\n+\t\t\t\t\t\"echo WARN: Cannot load the DT; \" \\\n+\t\t\t\t\"fi; \" \\\n+\t\t\t\"fi; \" \\\n+\t\t\"else \" \\\n+\t\t\t\"bootz; \" \\\n+\t\t\"fi\\0\" \\\n+\t\"nfsroot=/\\0\" \\\n+\t\"netargs=setenv bootargs console=${console},${baudrate} \" \\\n+\t\t\"root=/dev/nfs \" \\\n+\t\t\"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp ${extraargs}\\0\" \\\n+\t\"netboot=echo Booting from net ...; \" \\\n+\t\t\"run netargs; \"\t\\\n+\t\t\"if test ${ip_dyn} = yes; then \" \\\n+\t\t\t\"setenv get_cmd dhcp; \" \\\n+\t\t\"else \" \\\n+\t\t\t\"setenv get_cmd tftp; \" \\\n+\t\t\"fi; \" \\\n+\t\t\"${get_cmd} ${image}; \" \\\n+\t\t\"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then \" \\\n+\t\t\t\"if ${get_cmd} ${fdt_addr} ${fdt_file}; then \" \\\n+\t\t\t\t\"bootz ${loadaddr} - ${fdt_addr}; \" \\\n+\t\t\t\"else \" \\\n+\t\t\t\t\"if test ${boot_fdt} = try; then \" \\\n+\t\t\t\t\t\"bootz; \" \\\n+\t\t\t\t\"else \" \\\n+\t\t\t\t\t\"echo WARN: Cannot load the DT; \" \\\n+\t\t\t\t\"fi;\" \\\n+\t\t\t\"fi; \" \\\n+\t\t\"else \" \\\n+\t\t\t\"bootz; \" \\\n+\t\t\"fi\\0\"\n+\n+#define CONFIG_BOOTCOMMAND \\\n+\t\"mmc dev ${mmcdev}; \" \\\n+\t\"if mmc rescan; then \" \\\n+\t\t\"if run loadimage; then \" \\\n+\t\t\t\"run mmcboot; \" \\\n+\t\t\"else \" \\\n+\t\t\t\"run netboot; \" \\\n+\t\t\"fi; \" \\\n+\t\"else \" \\\n+\t\t\"run netboot; \" \\\n+\t\"fi\"\n+\n+/* The rest of the configuration is shared */\n+#include <configs/mxs.h>\n+\n+#endif /* __CONFIGS_DUCKBILL_H__ */\n-- \n2.17.1\n\n"
  },
  {
    "path": "package/boot/uboot-omap/Makefile",
    "content": "#\n# Copyright (C) 2012-2013 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\ninclude $(INCLUDE_DIR)/kernel.mk\n\nPKG_VERSION:=2021.07\nPKG_RELEASE:=$(AUTORELEASE)\n\nPKG_HASH:=312b7eeae44581d1362c3a3f02c28d806647756c82ba8c72241c7cdbe68ba77e\n\ninclude $(INCLUDE_DIR)/u-boot.mk\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine U-Boot/Default\n  BUILD_TARGET:=omap\n  UBOOT_IMAGE:=u-boot.img MLO\nendef\n\ndefine U-Boot/omap4_panda\n  NAME:=Pandaboard\n  BUILD_DEVICES:=ti_omap4-panda\nendef\n\ndefine U-Boot/am335x_evm\n  NAME:=AM335x EVM\n  BUILD_DEVICES:=ti_am335x-evm ti_am335x-bone-black\nendef\n\ndefine U-Boot/omap3_beagle\n  NAME:=BeagleBoard\n  BUILD_DEVICES:=ti_omap3-beagle\nendef\n\nUBOOT_TARGETS:=omap4_panda am335x_evm omap3_beagle\n\ndefine Build/InstallDev\n\t$(foreach device,$(BUILD_DEVICES), \\\n\t\t$(INSTALL_DIR) $(STAGING_DIR_IMAGE)/$(device)\n\t)\n\t$(foreach device,$(BUILD_DEVICES), \\\n\t\t$(CP) $(patsubst %,$(PKG_BUILD_DIR)/%,$(UBOOT_IMAGE)) $(STAGING_DIR_IMAGE)/$(device)/\n\t)\n\t$(foreach device,$(BUILD_DEVICES), \\\n\t\tmkimage -C none -A arm -T script -d ./files/boot.scr.txt \\\n\t\t\t$(STAGING_DIR_IMAGE)/$(device)/boot.scr\n\t)\nendef\n\n$(eval $(call BuildPackage/U-Boot))\n"
  },
  {
    "path": "package/boot/uboot-omap/files/boot.scr.txt",
    "content": "if test -z \"${devnum}\"; then\n\tsetenv devnum 0\nfi\n\nsetenv bootargs console=${console} root=/dev/mmcblk${devnum}p2 rootwait\n\nload mmc ${devnum}:1 ${loadaddr} /zImage \\\n&& load mmc ${devnum}:1 ${fdtaddr} /dtbs/${fdtfile} \\\n&& bootz ${loadaddr} - ${fdtaddr}\n"
  },
  {
    "path": "package/boot/uboot-oxnas/Makefile",
    "content": "#\n# Copyright (C) 2012 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\ninclude $(INCLUDE_DIR)/kernel.mk\n\nPKG_VERSION:=2014.10\nPKG_RELEASE:=$(AUTORELEASE)\n\nPKG_HASH:=d3b132a7a9b3f3182b7aad71c2dfbd4fc15bea83e12c76134eb3ffefc07d1c71\n\ninclude $(INCLUDE_DIR)/u-boot.mk\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine U-Boot/Default\n  BUILD_TARGET:=oxnas\n  BUILD_DEVICES:=Default\n  HIDDEN:=y\nendef\n\ndefine U-Boot/ox820\n  NAME:=Oxford/PLX NAS7820\nendef\n\nUBOOT_TARGETS:=ox820\n\ndefine Build/InstallDev\n\t$(INSTALL_DIR) $(STAGING_DIR_IMAGE)\n\t$(CP) $(PKG_BUILD_DIR)/u-boot.bin $(STAGING_DIR_IMAGE)/u-boot.bin\nendef\n\n$(eval $(call BuildPackage/U-Boot))\n"
  },
  {
    "path": "package/boot/uboot-oxnas/patches/010-capacity-is-unsigned.patch",
    "content": "From df9fb90120423c4c55b66a5dc09af23f605a406b Mon Sep 17 00:00:00 2001\nFrom: Daniel Golle <daniel@makrotopia.org>\nDate: Mon, 1 Dec 2014 21:37:25 +0100\nSubject: [PATCH] disk/part.c: use unsigned format when printing capacity\nTo: u-boot@lists.denx.de\n\nLarge disks otherwise produce highly unplausible output such as\n        Capacity: 1907729.0 MB = 1863.0 GB (-387938128 x 512)\n\nAs supposedly all size-related decimals are unsigned, use unsigned\nformat in printf statement, resulting in a correct capacity being\ndisplayed:\n        Capacity: 1907729.0 MB = 1863.0 GB (3907029168 x 512)\n\nSigned-off-by: Daniel Golle <daniel@makrotopia.org>\n---\n disk/part.c | 4 ++--\n 1 file changed, 2 insertions(+), 2 deletions(-)\n\n--- a/disk/part.c\n+++ b/disk/part.c\n@@ -229,13 +229,13 @@ void dev_print (block_dev_desc_t *dev_de\n \t\t\tprintf (\"            Supports 48-bit addressing\\n\");\n #endif\n #if defined(CONFIG_SYS_64BIT_LBA)\n-\t\tprintf (\"            Capacity: %ld.%ld MB = %ld.%ld GB (%Ld x %ld)\\n\",\n+\t\tprintf (\"            Capacity: %lu.%lu MB = %lu.%lu GB (%Lu x %lu)\\n\",\n \t\t\tmb_quot, mb_rem,\n \t\t\tgb_quot, gb_rem,\n \t\t\tlba,\n \t\t\tdev_desc->blksz);\n #else\n-\t\tprintf (\"            Capacity: %ld.%ld MB = %ld.%ld GB (%ld x %ld)\\n\",\n+\t\tprintf (\"            Capacity: %lu.%lu MB = %lu.%lu GB (%lu x %lu)\\n\",\n \t\t\tmb_quot, mb_rem,\n \t\t\tgb_quot, gb_rem,\n \t\t\t(ulong)lba,\n"
  },
  {
    "path": "package/boot/uboot-oxnas/patches/020-socfpgaimage_portability.patch",
    "content": "--- a/tools/socfpgaimage.c\n+++ b/tools/socfpgaimage.c\n@@ -74,12 +74,12 @@ static uint16_t hdr_checksum(struct socf\n static void build_header(uint8_t *buf, uint8_t version, uint8_t flags,\n \t\t\t uint16_t length_bytes)\n {\n-\theader.validation = htole32(VALIDATION_WORD);\n+\theader.validation = cpu_to_le32(VALIDATION_WORD);\n \theader.version = version;\n \theader.flags = flags;\n-\theader.length_u32 = htole16(length_bytes/4);\n+\theader.length_u32 = cpu_to_le16(length_bytes/4);\n \theader.zero = 0;\n-\theader.checksum = htole16(hdr_checksum(&header));\n+\theader.checksum = cpu_to_le16(hdr_checksum(&header));\n \n \tmemcpy(buf, &header, sizeof(header));\n }\n@@ -92,12 +92,12 @@ static int verify_header(const uint8_t *\n {\n \tmemcpy(&header, buf, sizeof(header));\n \n-\tif (le32toh(header.validation) != VALIDATION_WORD)\n+\tif (le32_to_cpu(header.validation) != VALIDATION_WORD)\n \t\treturn -1;\n-\tif (le16toh(header.checksum) != hdr_checksum(&header))\n+\tif (le16_to_cpu(header.checksum) != hdr_checksum(&header))\n \t\treturn -1;\n \n-\treturn le16toh(header.length_u32) * 4;\n+\treturn le16_to_cpu(header.length_u32) * 4;\n }\n \n /* Sign the buffer and return the signed buffer size */\n@@ -116,7 +116,7 @@ static int sign_buffer(uint8_t *buf,\n \t/* Calculate and apply the CRC */\n \tcalc_crc = ~pbl_crc32(0, (char *)buf, len);\n \n-\t*((uint32_t *)(buf + len)) = htole32(calc_crc);\n+\t*((uint32_t *)(buf + len)) = cpu_to_le32(calc_crc);\n \n \tif (!pad_64k)\n \t\treturn len + 4;\n@@ -150,7 +150,7 @@ static int verify_buffer(const uint8_t *\n \n \tcalc_crc = ~pbl_crc32(0, (const char *)buf, len);\n \n-\tbuf_crc = le32toh(*((uint32_t *)(buf + len)));\n+\tbuf_crc = le32_to_cpu(*((uint32_t *)(buf + len)));\n \n \tif (buf_crc != calc_crc) {\n \t\tfprintf(stderr, \"CRC32 does not match (%08x != %08x)\\n\",\n"
  },
  {
    "path": "package/boot/uboot-oxnas/patches/150-spl-block.patch",
    "content": "--- a/common/spl/Makefile\n+++ b/common/spl/Makefile\n@@ -19,4 +19,5 @@ obj-$(CONFIG_SPL_MMC_SUPPORT) += spl_mmc\n obj-$(CONFIG_SPL_USB_SUPPORT) += spl_usb.o\n obj-$(CONFIG_SPL_FAT_SUPPORT) += spl_fat.o\n obj-$(CONFIG_SPL_SATA_SUPPORT) += spl_sata.o\n+obj-$(CONFIG_SPL_BLOCK_SUPPORT) += spl_block.o\n endif\n--- a/common/spl/spl.c\n+++ b/common/spl/spl.c\n@@ -191,6 +191,14 @@ void board_init_r(gd_t *dummy1, ulong du\n \t\tspl_spi_load_image();\n \t\tbreak;\n #endif\n+#ifdef CONFIG_SPL_BLOCK_SUPPORT\n+\tcase BOOT_DEVICE_BLOCK:\n+\t{\n+\t\textern void spl_block_load_image(void);\n+\t\tspl_block_load_image();\n+\t\tbreak;\n+\t}\n+#endif\n #ifdef CONFIG_SPL_ETH_SUPPORT\n \tcase BOOT_DEVICE_CPGMAC:\n #ifdef CONFIG_SPL_ETH_DEVICE\n--- a/common/cmd_nvedit.c\n+++ b/common/cmd_nvedit.c\n@@ -49,6 +49,7 @@ DECLARE_GLOBAL_DATA_PTR;\n \t!defined(CONFIG_ENV_IS_IN_SPI_FLASH)\t&& \\\n \t!defined(CONFIG_ENV_IS_IN_REMOTE)\t&& \\\n \t!defined(CONFIG_ENV_IS_IN_UBI)\t\t&& \\\n+\t!defined(CONFIG_ENV_IS_IN_EXT4)\t\t&& \\\n \t!defined(CONFIG_ENV_IS_NOWHERE)\n # error Define one of CONFIG_ENV_IS_IN_{EEPROM|FLASH|DATAFLASH|ONENAND|\\\n SPI_FLASH|NVRAM|MMC|FAT|REMOTE|UBI} or CONFIG_ENV_IS_NOWHERE\n--- a/common/Makefile\n+++ b/common/Makefile\n@@ -63,6 +63,7 @@ obj-$(CONFIG_ENV_IS_IN_ONENAND) += env_o\n obj-$(CONFIG_ENV_IS_IN_SPI_FLASH) += env_sf.o\n obj-$(CONFIG_ENV_IS_IN_REMOTE) += env_remote.o\n obj-$(CONFIG_ENV_IS_IN_UBI) += env_ubi.o\n+obj-$(CONFIG_ENV_IS_IN_EXT4) += env_ext4.o\n obj-$(CONFIG_ENV_IS_NOWHERE) += env_nowhere.o\n \n # command\n@@ -213,6 +214,8 @@ obj-$(CONFIG_UPDATE_TFTP) += update.o\n obj-$(CONFIG_USB_KEYBOARD) += usb_kbd.o\n obj-$(CONFIG_CMD_DFU) += cmd_dfu.o\n obj-$(CONFIG_CMD_GPT) += cmd_gpt.o\n+else\n+obj-$(CONFIG_SPL_BLOCK_SUPPORT) += cmd_ide.o\n endif\n \n ifdef CONFIG_SPL_BUILD\n"
  },
  {
    "path": "package/boot/uboot-oxnas/patches/200-icplus-phy.patch",
    "content": "From e719404ee1241af679a51879eaad291bc27e4817 Mon Sep 17 00:00:00 2001\nFrom: Daniel Golle <daniel@makrotopia.org>\nDate: Tue, 2 Dec 2014 14:46:05 +0100\nSubject: [PATCH] net/phy: add back icplus driver\n\nIC+ phy driver was removed due to the lack of users some time ago.\nAdd it back, so we can use it.\n---\n drivers/net/phy/Makefile |  1 +\n drivers/net/phy/icplus.c | 80 ++++++++++++++++++++++++++++++++++++++++++++++++\n drivers/net/phy/phy.c    |  3 ++\n 3 files changed, 84 insertions(+)\n create mode 100644 drivers/net/phy/icplus.c\n\n--- a/drivers/net/phy/Makefile\n+++ b/drivers/net/phy/Makefile\n@@ -15,6 +15,7 @@ obj-$(CONFIG_PHY_ATHEROS) += atheros.o\n obj-$(CONFIG_PHY_BROADCOM) += broadcom.o\n obj-$(CONFIG_PHY_DAVICOM) += davicom.o\n obj-$(CONFIG_PHY_ET1011C) += et1011c.o\n+obj-$(CONFIG_PHY_ICPLUS) += icplus.o\n obj-$(CONFIG_PHY_LXT) += lxt.o\n obj-$(CONFIG_PHY_MARVELL) += marvell.o\n obj-$(CONFIG_PHY_MICREL) += micrel.o\n--- /dev/null\n+++ b/drivers/net/phy/icplus.c\n@@ -0,0 +1,93 @@\n+/*\n+ * ICPlus PHY drivers\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ *\n+ * Copyright (c) 2007 Freescale Semiconductor, Inc.\n+ */\n+#include <phy.h>\n+\n+/* IP101A/G - IP1001 */\n+#define IP10XX_SPEC_CTRL_STATUS         16      /* Spec. Control Register */\n+#define IP1001_SPEC_CTRL_STATUS_2       20      /* IP1001 Spec. Control Reg 2 */\n+#define IP1001_PHASE_SEL_MASK           3       /* IP1001 RX/TXPHASE_SEL */\n+#define IP1001_APS_ON                   11      /* IP1001 APS Mode  bit */\n+#define IP101A_G_APS_ON                 2       /* IP101A/G APS Mode bit */\n+#define IP101A_G_IRQ_CONF_STATUS        0x11    /* Conf Info IRQ & Status Reg */\n+#define IP101A_G_IRQ_PIN_USED           (1<<15) /* INTR pin used */\n+#define IP101A_G_IRQ_DEFAULT            IP101A_G_IRQ_PIN_USED\n+#define IP1001LF_DRIVE_MASK     (15 << 5)\n+#define IP1001LF_RXCLKDRIVE_HI  (2  << 5)\n+#define IP1001LF_RXDDRIVE_HI    (2  << 7)\n+#define IP1001LF_RXCLKDRIVE_M   (1  << 5)\n+#define IP1001LF_RXDDRIVE_M     (1  << 7)\n+#define IP1001LF_RXCLKDRIVE_L   (0  << 5)\n+#define IP1001LF_RXDDRIVE_L     (0  << 7)\n+#define IP1001LF_RXCLKDRIVE_VL  (3  << 5)\n+#define IP1001LF_RXDDRIVE_VL    (3  << 7)\n+\n+static int ip1001_config(struct phy_device *phydev)\n+{\n+\tint c;\n+\n+\t/* Enable Auto Power Saving mode */\n+\tc = phy_read(phydev, MDIO_DEVAD_NONE, IP1001_SPEC_CTRL_STATUS_2);\n+\tif (c < 0)\n+\t\treturn c;\n+\tc |= IP1001_APS_ON;\n+\tc = phy_write(phydev, MDIO_DEVAD_NONE, IP1001_SPEC_CTRL_STATUS_2, c);\n+\tif (c < 0)\n+\t\treturn c;\n+\n+\t/* INTR pin used: speed/link/duplex will cause an interrupt */\n+\tc = phy_write(phydev, MDIO_DEVAD_NONE, IP101A_G_IRQ_CONF_STATUS,\n+\t\t      IP101A_G_IRQ_DEFAULT);\n+\tif (c < 0)\n+\t\treturn c;\n+\n+\tif (phydev->interface == PHY_INTERFACE_MODE_RGMII) {\n+\t\t/*\n+\t\t * Additional delay (2ns) used to adjust RX clock phase\n+\t\t * at RGMII interface\n+\t\t */\n+\t\tc = phy_read(phydev, MDIO_DEVAD_NONE, IP10XX_SPEC_CTRL_STATUS);\n+\t\tif (c < 0)\n+\t\t\treturn c;\n+\n+\t\tc |= IP1001_PHASE_SEL_MASK;\n+\t\t/* adjust digtial drive strength */\n+\t\tc &= ~IP1001LF_DRIVE_MASK;\n+\t\tc |=  IP1001LF_RXCLKDRIVE_M;\n+\t\tc |=  IP1001LF_RXDDRIVE_M;\n+\t\tc = phy_write(phydev, MDIO_DEVAD_NONE, IP10XX_SPEC_CTRL_STATUS,\n+\t\t\t      c);\n+\t\tif (c < 0)\n+\t\t\treturn c;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int ip1001_startup(struct phy_device *phydev)\n+{\n+\tgenphy_update_link(phydev);\n+\tgenphy_parse_link(phydev);\n+\n+\treturn 0;\n+}\n+static struct phy_driver IP1001_driver = {\n+\t.name = \"ICPlus IP1001\",\n+\t.uid = 0x02430d90,\n+\t.mask = 0x0ffffff0,\n+\t.features = PHY_GBIT_FEATURES,\n+\t.config = &ip1001_config,\n+\t.startup = &ip1001_startup,\n+\t.shutdown = &genphy_shutdown,\n+};\n+\n+int phy_icplus_init(void)\n+{\n+\tphy_register(&IP1001_driver);\n+\n+\treturn 0;\n+}\n--- a/drivers/net/phy/phy.c\n+++ b/drivers/net/phy/phy.c\n@@ -454,6 +454,9 @@ int phy_init(void)\n #ifdef CONFIG_PHY_ET1011C\n \tphy_et1011c_init();\n #endif\n+#ifdef CONFIG_PHY_ICPLUS\n+\tphy_icplus_init();\n+#endif\n #ifdef CONFIG_PHY_LXT\n \tphy_lxt_init();\n #endif\n--- a/include/phy.h\n+++ b/include/phy.h\n@@ -225,6 +225,7 @@ int phy_atheros_init(void);\n int phy_broadcom_init(void);\n int phy_davicom_init(void);\n int phy_et1011c_init(void);\n+int phy_icplus_init(void);\n int phy_lxt_init(void);\n int phy_marvell_init(void);\n int phy_micrel_init(void);\n"
  },
  {
    "path": "package/boot/uboot-oxnas/patches/300-oxnas-target.patch",
    "content": "--- a/arch/arm/include/asm/mach-types.h\n+++ b/arch/arm/include/asm/mach-types.h\n@@ -212,6 +212,7 @@ extern unsigned int __machine_arch_type;\n #define MACH_TYPE_EDB9307A             1128\n #define MACH_TYPE_OMAP_3430SDP         1138\n #define MACH_TYPE_VSTMS                1140\n+#define MACH_TYPE_OXNAS                1152\n #define MACH_TYPE_MICRO9M              1169\n #define MACH_TYPE_BUG                  1179\n #define MACH_TYPE_AT91SAM9263EK        1202\n--- a/drivers/block/Makefile\n+++ b/drivers/block/Makefile\n@@ -21,3 +21,4 @@ obj-$(CONFIG_IDE_SIL680) += sil680.o\n obj-$(CONFIG_SANDBOX) += sandbox.o\n obj-$(CONFIG_SCSI_SYM53C8XX) += sym53c8xx.o\n obj-$(CONFIG_SYSTEMACE) += systemace.o\n+obj-$(CONFIG_IDE_PLX) += plxsata_ide.o\n--- a/drivers/usb/host/Makefile\n+++ b/drivers/usb/host/Makefile\n@@ -33,6 +33,7 @@ obj-$(CONFIG_USB_EHCI_MX6) += ehci-mx6.o\n obj-$(CONFIG_USB_EHCI_OMAP) += ehci-omap.o\n obj-$(CONFIG_USB_EHCI_PPC4XX) += ehci-ppc4xx.o\n obj-$(CONFIG_USB_EHCI_MARVELL) += ehci-marvell.o\n+obj-$(CONFIG_USB_EHCI_OXNAS) += ehci-oxnas.o\n obj-$(CONFIG_USB_EHCI_PCI) += ehci-pci.o\n obj-$(CONFIG_USB_EHCI_SPEAR) += ehci-spear.o\n obj-$(CONFIG_USB_EHCI_SUNXI) += ehci-sunxi.o\n--- a/tools/.gitignore\n+++ b/tools/.gitignore\n@@ -9,6 +9,7 @@\n /mkenvimage\n /mkimage\n /mkexynosspl\n+/mkox820crc\n /mpc86x_clk\n /mxsboot\n /mksunxiboot\n--- a/tools/Makefile\n+++ b/tools/Makefile\n@@ -143,6 +143,12 @@ hostprogs-$(CONFIG_KIRKWOOD) += kwboot\n hostprogs-y += proftool\n hostprogs-$(CONFIG_STATIC_RELA) += relocate-rela\n \n+\n+hostprogs-$(CONFIG_OX820) += mkox820crc$(SFX)\n+\n+mkox820crc$(SFX)-objs := mkox820crc.o lib/crc32.o\n+\n+\n # We build some files with extra pedantic flags to try to minimize things\n # that won't build on some weird host compiler -- though there are lots of\n # exceptions for files that aren't complaint.\n--- a/drivers/serial/ns16550.c\n+++ b/drivers/serial/ns16550.c\n@@ -118,6 +118,14 @@ int ns16550_calc_divisor(NS16550_t port,\n \t}\n \tport->osc_12m_sel = 0;\t\t\t/* clear if previsouly set */\n #endif\n+#ifdef CONFIG_OX820\n+\t{\n+\t\t/* with additional 3 bit fractional */\n+\t\tu32 div = (CONFIG_SYS_NS16550_CLK + baudrate) / (baudrate * 2);\n+\t\tport->reg9 = (div & 7) << 5;\n+\t\treturn (div >> 3);\n+\t}\n+#endif\n \n \treturn DIV_ROUND_CLOSEST(clock, mode_x_div * baudrate);\n }\n--- a/scripts/Makefile.spl\n+++ b/scripts/Makefile.spl\n@@ -202,6 +202,9 @@ OBJCOPYFLAGS_$(SPL_BIN).bin = $(SPL_OBJC\n \n $(obj)/$(SPL_BIN).bin: $(obj)/$(SPL_BIN) FORCE\n \t$(call if_changed,objcopy)\n+ifdef CONFIG_OX820\n+\t$(OBJTREE)/tools/mkox820crc $@\n+endif\n \n LDFLAGS_$(SPL_BIN) += -T u-boot-spl.lds $(LDFLAGS_FINAL)\n ifneq ($(CONFIG_SPL_TEXT_BASE),)\n--- a/arch/arm/Kconfig\n+++ b/arch/arm/Kconfig\n@@ -488,6 +488,9 @@ config TARGET_BALLOON3\n config TARGET_H2200\n \tbool \"Support h2200\"\n \n+config TARGET_OX820\n+\tbool \"Support ox820\"\n+\n config TARGET_PALMLD\n \tbool \"Support palmld\"\n \n@@ -650,6 +653,7 @@ source \"board/logicpd/imx27lite/Kconfig\"\n source \"board/logicpd/imx31_litekit/Kconfig\"\n source \"board/mpl/vcma9/Kconfig\"\n source \"board/olimex/mx23_olinuxino/Kconfig\"\n+source \"board/ox820/Kconfig\"\n source \"board/palmld/Kconfig\"\n source \"board/palmtc/Kconfig\"\n source \"board/palmtreo680/Kconfig\"\n"
  },
  {
    "path": "package/boot/uboot-oxnas/patches/400-gcc-5-compiler.patch",
    "content": "From: Hans de Goede <hdegoede@redhat.com>\nDate: Sat, 7 Feb 2015 21:52:40 +0000 (+0100)\nSubject: Add linux/compiler-gcc5.h to fix builds with gcc5\nX-Git-Tag: v2015.04-rc2~31\nX-Git-Url: http://git.denx.de/?p=u-boot.git;a=commitdiff_plain;h=478b02f1a7043b673565075ea5016376f3293b23\n\nAdd linux/compiler-gcc5.h to fix builds with gcc5\n\nAdd linux/compiler-gcc5/h from the kernel sources at:\n\ncommit 5631b8fba640a4ab2f8a954f63a603fa34eda96b\nAuthor: Steven Noonan <steven@uplinklabs.net>\nDate:   Sat Oct 25 15:09:42 2014 -0700\n\n    compiler/gcc4+: Remove inaccurate comment about 'asm goto' miscompiles\n\nSigned-off-by: Hans de Goede <hdegoede@redhat.com>\n---\n\n--- /dev/null\n+++ b/include/linux/compiler-gcc5.h\n@@ -0,0 +1,65 @@\n+#ifndef __LINUX_COMPILER_H\n+#error \"Please don't include <linux/compiler-gcc5.h> directly, include <linux/compiler.h> instead.\"\n+#endif\n+\n+#define __used\t\t\t\t__attribute__((__used__))\n+#define __must_check\t\t\t__attribute__((warn_unused_result))\n+#define __compiler_offsetof(a, b)\t__builtin_offsetof(a, b)\n+\n+/* Mark functions as cold. gcc will assume any path leading to a call\n+   to them will be unlikely.  This means a lot of manual unlikely()s\n+   are unnecessary now for any paths leading to the usual suspects\n+   like BUG(), printk(), panic() etc. [but let's keep them for now for\n+   older compilers]\n+\n+   Early snapshots of gcc 4.3 don't support this and we can't detect this\n+   in the preprocessor, but we can live with this because they're unreleased.\n+   Maketime probing would be overkill here.\n+\n+   gcc also has a __attribute__((__hot__)) to move hot functions into\n+   a special section, but I don't see any sense in this right now in\n+   the kernel context */\n+#define __cold\t\t\t__attribute__((__cold__))\n+\n+#define __UNIQUE_ID(prefix) __PASTE(__PASTE(__UNIQUE_ID_, prefix), __COUNTER__)\n+\n+#ifndef __CHECKER__\n+# define __compiletime_warning(message) __attribute__((warning(message)))\n+# define __compiletime_error(message) __attribute__((error(message)))\n+#endif /* __CHECKER__ */\n+\n+/*\n+ * Mark a position in code as unreachable.  This can be used to\n+ * suppress control flow warnings after asm blocks that transfer\n+ * control elsewhere.\n+ *\n+ * Early snapshots of gcc 4.5 don't support this and we can't detect\n+ * this in the preprocessor, but we can live with this because they're\n+ * unreleased.  Really, we need to have autoconf for the kernel.\n+ */\n+#define unreachable() __builtin_unreachable()\n+\n+/* Mark a function definition as prohibited from being cloned. */\n+#define __noclone\t__attribute__((__noclone__))\n+\n+/*\n+ * Tell the optimizer that something else uses this function or variable.\n+ */\n+#define __visible __attribute__((externally_visible))\n+\n+/*\n+ * GCC 'asm goto' miscompiles certain code sequences:\n+ *\n+ *   http://gcc.gnu.org/bugzilla/show_bug.cgi?id=58670\n+ *\n+ * Work it around via a compiler barrier quirk suggested by Jakub Jelinek.\n+ *\n+ * (asm goto is automatically volatile - the naming reflects this.)\n+ */\n+#define asm_volatile_goto(x...)\tdo { asm goto(x); asm (\"\"); } while (0)\n+\n+#ifdef CONFIG_ARCH_USE_BUILTIN_BSWAP\n+#define __HAVE_BUILTIN_BSWAP32__\n+#define __HAVE_BUILTIN_BSWAP64__\n+#define __HAVE_BUILTIN_BSWAP16__\n+#endif /* CONFIG_ARCH_USE_BUILTIN_BSWAP */\n"
  },
  {
    "path": "package/boot/uboot-oxnas/patches/410-gcc-6-compiler.patch",
    "content": "From: Hans de Goede <hdegoede@redhat.com>\nDate: Sat, 7 Feb 2015 21:52:40 +0000 (+0100)\nSubject: Add linux/compiler-gcc6.h to fix builds with gcc6\nX-Git-Tag: v2015.04-rc2~31\nX-Git-Url: http://git.denx.de/?p=u-boot.git;a=commitdiff_plain;h=478b02f1a7043b673565075ea5016376f3293b23\n\nAdd linux/compiler-gcc6.h to fix builds with gcc6\n\nAdd linux/compiler-gcc6/h from the kernel sources at:\n\ncommit 5631b8fba640a4ab2f8a954f63a603fa34eda96b\nAuthor: Steven Noonan <steven@uplinklabs.net>\nDate:   Sat Oct 25 15:09:42 2014 -0700\n\n    compiler/gcc4+: Remove inaccurate comment about 'asm goto' miscompiles\n\nSigned-off-by: Hans de Goede <hdegoede@redhat.com>\n---\n\n--- /dev/null\n+++ b/include/linux/compiler-gcc6.h\n@@ -0,0 +1,284 @@\n+#ifndef __LINUX_COMPILER_H\n+#error \"Please don't include <linux/compiler-gcc.h> directly, include <linux/compiler.h> instead.\"\n+#endif\n+\n+/*\n+ * Common definitions for all gcc versions go here.\n+ */\n+#define GCC_VERSION (__GNUC__ * 10000\t\t\\\n+\t\t     + __GNUC_MINOR__ * 100\t\\\n+\t\t     + __GNUC_PATCHLEVEL__)\n+\n+/* Optimization barrier */\n+\n+/* The \"volatile\" is due to gcc bugs */\n+#define barrier() __asm__ __volatile__(\"\": : :\"memory\")\n+/*\n+ * This version is i.e. to prevent dead stores elimination on @ptr\n+ * where gcc and llvm may behave differently when otherwise using\n+ * normal barrier(): while gcc behavior gets along with a normal\n+ * barrier(), llvm needs an explicit input variable to be assumed\n+ * clobbered. The issue is as follows: while the inline asm might\n+ * access any memory it wants, the compiler could have fit all of\n+ * @ptr into memory registers instead, and since @ptr never escaped\n+ * from that, it proofed that the inline asm wasn't touching any of\n+ * it. This version works well with both compilers, i.e. we're telling\n+ * the compiler that the inline asm absolutely may see the contents\n+ * of @ptr. See also: https://llvm.org/bugs/show_bug.cgi?id=15495\n+ */\n+#define barrier_data(ptr) __asm__ __volatile__(\"\": :\"r\"(ptr) :\"memory\")\n+\n+/*\n+ * This macro obfuscates arithmetic on a variable address so that gcc\n+ * shouldn't recognize the original var, and make assumptions about it.\n+ *\n+ * This is needed because the C standard makes it undefined to do\n+ * pointer arithmetic on \"objects\" outside their boundaries and the\n+ * gcc optimizers assume this is the case. In particular they\n+ * assume such arithmetic does not wrap.\n+ *\n+ * A miscompilation has been observed because of this on PPC.\n+ * To work around it we hide the relationship of the pointer and the object\n+ * using this macro.\n+ *\n+ * Versions of the ppc64 compiler before 4.1 had a bug where use of\n+ * RELOC_HIDE could trash r30. The bug can be worked around by changing\n+ * the inline assembly constraint from =g to =r, in this particular\n+ * case either is valid.\n+ */\n+#define RELOC_HIDE(ptr, off)\t\t\t\t\t\t\\\n+({\t\t\t\t\t\t\t\t\t\\\n+\tunsigned long __ptr;\t\t\t\t\t\t\\\n+\t__asm__ (\"\" : \"=r\"(__ptr) : \"0\"(ptr));\t\t\t\t\\\n+\t(typeof(ptr)) (__ptr + (off));\t\t\t\t\t\\\n+})\n+\n+/* Make the optimizer believe the variable can be manipulated arbitrarily. */\n+#define OPTIMIZER_HIDE_VAR(var)\t\t\t\t\t\t\\\n+\t__asm__ (\"\" : \"=r\" (var) : \"0\" (var))\n+\n+#ifdef __CHECKER__\n+#define __must_be_array(a)\t0\n+#else\n+/* &a[0] degrades to a pointer: a different type from an array */\n+#define __must_be_array(a)\tBUILD_BUG_ON_ZERO(__same_type((a), &(a)[0]))\n+#endif\n+\n+/*\n+ * Force always-inline if the user requests it so via the .config,\n+ * or if gcc is too old:\n+ */\n+#if !defined(CONFIG_ARCH_SUPPORTS_OPTIMIZED_INLINING) ||\t\t\\\n+    !defined(CONFIG_OPTIMIZE_INLINING) || (__GNUC__ < 4)\n+#define inline\t\tinline\t\t__attribute__((always_inline)) notrace\n+#define __inline__\t__inline__\t__attribute__((always_inline)) notrace\n+#define __inline\t__inline\t__attribute__((always_inline)) notrace\n+#else\n+/* A lot of inline functions can cause havoc with function tracing */\n+#define inline\t\tinline\t\tnotrace\n+#define __inline__\t__inline__\tnotrace\n+#define __inline\t__inline\tnotrace\n+#endif\n+\n+#define __always_inline\tinline __attribute__((always_inline))\n+#define  noinline\t__attribute__((noinline))\n+\n+#define __deprecated\t__attribute__((deprecated))\n+#define __packed\t__attribute__((packed))\n+#define __weak\t\t__attribute__((weak))\n+#define __alias(symbol)\t__attribute__((alias(#symbol)))\n+\n+/*\n+ * it doesn't make sense on ARM (currently the only user of __naked)\n+ * to trace naked functions because then mcount is called without\n+ * stack and frame pointer being set up and there is no chance to\n+ * restore the lr register to the value before mcount was called.\n+ *\n+ * The asm() bodies of naked functions often depend on standard calling\n+ * conventions, therefore they must be noinline and noclone.\n+ *\n+ * GCC 4.[56] currently fail to enforce this, so we must do so ourselves.\n+ * See GCC PR44290.\n+ */\n+#define __naked\t\t__attribute__((naked)) noinline __noclone notrace\n+\n+#define __noreturn\t__attribute__((noreturn))\n+\n+/*\n+ * From the GCC manual:\n+ *\n+ * Many functions have no effects except the return value and their\n+ * return value depends only on the parameters and/or global\n+ * variables.  Such a function can be subject to common subexpression\n+ * elimination and loop optimization just as an arithmetic operator\n+ * would be.\n+ * [...]\n+ */\n+#define __pure\t\t\t__attribute__((pure))\n+#define __aligned(x)\t\t__attribute__((aligned(x)))\n+#define __printf(a, b)\t\t__attribute__((format(printf, a, b)))\n+#define __scanf(a, b)\t\t__attribute__((format(scanf, a, b)))\n+#define __attribute_const__\t__attribute__((__const__))\n+#define __maybe_unused\t\t__attribute__((unused))\n+#define __always_unused\t\t__attribute__((unused))\n+\n+/* gcc version specific checks */\n+\n+#if GCC_VERSION < 30200\n+# error Sorry, your compiler is too old - please upgrade it.\n+#endif\n+\n+#if GCC_VERSION < 30300\n+# define __used\t\t\t__attribute__((__unused__))\n+#else\n+# define __used\t\t\t__attribute__((__used__))\n+#endif\n+\n+#ifdef CONFIG_GCOV_KERNEL\n+# if GCC_VERSION < 30400\n+#   error \"GCOV profiling support for gcc versions below 3.4 not included\"\n+# endif /* __GNUC_MINOR__ */\n+#endif /* CONFIG_GCOV_KERNEL */\n+\n+#if GCC_VERSION >= 30400\n+#define __must_check\t\t__attribute__((warn_unused_result))\n+#define __malloc\t\t__attribute__((__malloc__))\n+#endif\n+\n+#if GCC_VERSION >= 40000\n+\n+/* GCC 4.1.[01] miscompiles __weak */\n+#ifdef __KERNEL__\n+# if GCC_VERSION >= 40100 &&  GCC_VERSION <= 40101\n+#  error Your version of gcc miscompiles the __weak directive\n+# endif\n+#endif\n+\n+#define __used\t\t\t__attribute__((__used__))\n+#define __compiler_offsetof(a, b)\t\t\t\t\t\\\n+\t__builtin_offsetof(a, b)\n+\n+#if GCC_VERSION >= 40100 && GCC_VERSION < 40600\n+# define __compiletime_object_size(obj) __builtin_object_size(obj, 0)\n+#endif\n+\n+#if GCC_VERSION >= 40300\n+/* Mark functions as cold. gcc will assume any path leading to a call\n+ * to them will be unlikely.  This means a lot of manual unlikely()s\n+ * are unnecessary now for any paths leading to the usual suspects\n+ * like BUG(), printk(), panic() etc. [but let's keep them for now for\n+ * older compilers]\n+ *\n+ * Early snapshots of gcc 4.3 don't support this and we can't detect this\n+ * in the preprocessor, but we can live with this because they're unreleased.\n+ * Maketime probing would be overkill here.\n+ *\n+ * gcc also has a __attribute__((__hot__)) to move hot functions into\n+ * a special section, but I don't see any sense in this right now in\n+ * the kernel context\n+ */\n+#define __cold\t\t\t__attribute__((__cold__))\n+\n+#define __UNIQUE_ID(prefix) __PASTE(__PASTE(__UNIQUE_ID_, prefix), __COUNTER__)\n+\n+#ifndef __CHECKER__\n+# define __compiletime_warning(message) __attribute__((warning(message)))\n+# define __compiletime_error(message) __attribute__((error(message)))\n+#endif /* __CHECKER__ */\n+#endif /* GCC_VERSION >= 40300 */\n+\n+#if GCC_VERSION >= 40500\n+/*\n+ * Mark a position in code as unreachable.  This can be used to\n+ * suppress control flow warnings after asm blocks that transfer\n+ * control elsewhere.\n+ *\n+ * Early snapshots of gcc 4.5 don't support this and we can't detect\n+ * this in the preprocessor, but we can live with this because they're\n+ * unreleased.  Really, we need to have autoconf for the kernel.\n+ */\n+#define unreachable() __builtin_unreachable()\n+\n+/* Mark a function definition as prohibited from being cloned. */\n+#define __noclone\t__attribute__((__noclone__, __optimize__(\"no-tracer\")))\n+\n+#endif /* GCC_VERSION >= 40500 */\n+\n+#if GCC_VERSION >= 40600\n+/*\n+ * When used with Link Time Optimization, gcc can optimize away C functions or\n+ * variables which are referenced only from assembly code.  __visible tells the\n+ * optimizer that something else uses this function or variable, thus preventing\n+ * this.\n+ */\n+#define __visible\t__attribute__((externally_visible))\n+#endif\n+\n+\n+#if GCC_VERSION >= 40900 && !defined(__CHECKER__)\n+/*\n+ * __assume_aligned(n, k): Tell the optimizer that the returned\n+ * pointer can be assumed to be k modulo n. The second argument is\n+ * optional (default 0), so we use a variadic macro to make the\n+ * shorthand.\n+ *\n+ * Beware: Do not apply this to functions which may return\n+ * ERR_PTRs. Also, it is probably unwise to apply it to functions\n+ * returning extra information in the low bits (but in that case the\n+ * compiler should see some alignment anyway, when the return value is\n+ * massaged by 'flags = ptr & 3; ptr &= ~3;').\n+ */\n+#define __assume_aligned(a, ...) __attribute__((__assume_aligned__(a, ## __VA_ARGS__)))\n+#endif\n+\n+/*\n+ * GCC 'asm goto' miscompiles certain code sequences:\n+ *\n+ *   http://gcc.gnu.org/bugzilla/show_bug.cgi?id=58670\n+ *\n+ * Work it around via a compiler barrier quirk suggested by Jakub Jelinek.\n+ *\n+ * (asm goto is automatically volatile - the naming reflects this.)\n+ */\n+#define asm_volatile_goto(x...)\tdo { asm goto(x); asm (\"\"); } while (0)\n+\n+#ifdef CONFIG_ARCH_USE_BUILTIN_BSWAP\n+#if GCC_VERSION >= 40400\n+#define __HAVE_BUILTIN_BSWAP32__\n+#define __HAVE_BUILTIN_BSWAP64__\n+#endif\n+#if GCC_VERSION >= 40800\n+#define __HAVE_BUILTIN_BSWAP16__\n+#endif\n+#endif /* CONFIG_ARCH_USE_BUILTIN_BSWAP */\n+\n+#if GCC_VERSION >= 50000\n+#define KASAN_ABI_VERSION 4\n+#elif GCC_VERSION >= 40902\n+#define KASAN_ABI_VERSION 3\n+#endif\n+\n+#if GCC_VERSION >= 40902\n+/*\n+ * Tell the compiler that address safety instrumentation (KASAN)\n+ * should not be applied to that function.\n+ * Conflicts with inlining: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67368\n+ */\n+#define __no_sanitize_address __attribute__((no_sanitize_address))\n+#endif\n+\n+#endif\t/* gcc version >= 40000 specific checks */\n+\n+#if !defined(__noclone)\n+#define __noclone\t/* not needed */\n+#endif\n+\n+#if !defined(__no_sanitize_address)\n+#define __no_sanitize_address\n+#endif\n+\n+/*\n+ * A trick to suppress uninitialized variable warning without generating any\n+ * code\n+ */\n+#define uninitialized_var(x) x = x\n"
  },
  {
    "path": "package/boot/uboot-oxnas/patches/420-gcc-7-compiler.patch",
    "content": "--- /dev/null\n+++ b/include/linux/compiler-gcc7.h\n@@ -0,0 +1,284 @@\n+#ifndef __LINUX_COMPILER_H\n+#error \"Please don't include <linux/compiler-gcc.h> directly, include <linux/compiler.h> instead.\"\n+#endif\n+\n+/*\n+ * Common definitions for all gcc versions go here.\n+ */\n+#define GCC_VERSION (__GNUC__ * 10000\t\t\\\n+\t\t     + __GNUC_MINOR__ * 100\t\\\n+\t\t     + __GNUC_PATCHLEVEL__)\n+\n+/* Optimization barrier */\n+\n+/* The \"volatile\" is due to gcc bugs */\n+#define barrier() __asm__ __volatile__(\"\": : :\"memory\")\n+/*\n+ * This version is i.e. to prevent dead stores elimination on @ptr\n+ * where gcc and llvm may behave differently when otherwise using\n+ * normal barrier(): while gcc behavior gets along with a normal\n+ * barrier(), llvm needs an explicit input variable to be assumed\n+ * clobbered. The issue is as follows: while the inline asm might\n+ * access any memory it wants, the compiler could have fit all of\n+ * @ptr into memory registers instead, and since @ptr never escaped\n+ * from that, it proofed that the inline asm wasn't touching any of\n+ * it. This version works well with both compilers, i.e. we're telling\n+ * the compiler that the inline asm absolutely may see the contents\n+ * of @ptr. See also: https://llvm.org/bugs/show_bug.cgi?id=15495\n+ */\n+#define barrier_data(ptr) __asm__ __volatile__(\"\": :\"r\"(ptr) :\"memory\")\n+\n+/*\n+ * This macro obfuscates arithmetic on a variable address so that gcc\n+ * shouldn't recognize the original var, and make assumptions about it.\n+ *\n+ * This is needed because the C standard makes it undefined to do\n+ * pointer arithmetic on \"objects\" outside their boundaries and the\n+ * gcc optimizers assume this is the case. In particular they\n+ * assume such arithmetic does not wrap.\n+ *\n+ * A miscompilation has been observed because of this on PPC.\n+ * To work around it we hide the relationship of the pointer and the object\n+ * using this macro.\n+ *\n+ * Versions of the ppc64 compiler before 4.1 had a bug where use of\n+ * RELOC_HIDE could trash r30. The bug can be worked around by changing\n+ * the inline assembly constraint from =g to =r, in this particular\n+ * case either is valid.\n+ */\n+#define RELOC_HIDE(ptr, off)\t\t\t\t\t\t\\\n+({\t\t\t\t\t\t\t\t\t\\\n+\tunsigned long __ptr;\t\t\t\t\t\t\\\n+\t__asm__ (\"\" : \"=r\"(__ptr) : \"0\"(ptr));\t\t\t\t\\\n+\t(typeof(ptr)) (__ptr + (off));\t\t\t\t\t\\\n+})\n+\n+/* Make the optimizer believe the variable can be manipulated arbitrarily. */\n+#define OPTIMIZER_HIDE_VAR(var)\t\t\t\t\t\t\\\n+\t__asm__ (\"\" : \"=r\" (var) : \"0\" (var))\n+\n+#ifdef __CHECKER__\n+#define __must_be_array(a)\t0\n+#else\n+/* &a[0] degrades to a pointer: a different type from an array */\n+#define __must_be_array(a)\tBUILD_BUG_ON_ZERO(__same_type((a), &(a)[0]))\n+#endif\n+\n+/*\n+ * Force always-inline if the user requests it so via the .config,\n+ * or if gcc is too old:\n+ */\n+#if !defined(CONFIG_ARCH_SUPPORTS_OPTIMIZED_INLINING) ||\t\t\\\n+    !defined(CONFIG_OPTIMIZE_INLINING) || (__GNUC__ < 4)\n+#define inline\t\tinline\t\t__attribute__((always_inline)) notrace\n+#define __inline__\t__inline__\t__attribute__((always_inline)) notrace\n+#define __inline\t__inline\t__attribute__((always_inline)) notrace\n+#else\n+/* A lot of inline functions can cause havoc with function tracing */\n+#define inline\t\tinline\t\tnotrace\n+#define __inline__\t__inline__\tnotrace\n+#define __inline\t__inline\tnotrace\n+#endif\n+\n+#define __always_inline\tinline __attribute__((always_inline))\n+#define  noinline\t__attribute__((noinline))\n+\n+#define __deprecated\t__attribute__((deprecated))\n+#define __packed\t__attribute__((packed))\n+#define __weak\t\t__attribute__((weak))\n+#define __alias(symbol)\t__attribute__((alias(#symbol)))\n+\n+/*\n+ * it doesn't make sense on ARM (currently the only user of __naked)\n+ * to trace naked functions because then mcount is called without\n+ * stack and frame pointer being set up and there is no chance to\n+ * restore the lr register to the value before mcount was called.\n+ *\n+ * The asm() bodies of naked functions often depend on standard calling\n+ * conventions, therefore they must be noinline and noclone.\n+ *\n+ * GCC 4.[56] currently fail to enforce this, so we must do so ourselves.\n+ * See GCC PR44290.\n+ */\n+#define __naked\t\t__attribute__((naked)) noinline __noclone notrace\n+\n+#define __noreturn\t__attribute__((noreturn))\n+\n+/*\n+ * From the GCC manual:\n+ *\n+ * Many functions have no effects except the return value and their\n+ * return value depends only on the parameters and/or global\n+ * variables.  Such a function can be subject to common subexpression\n+ * elimination and loop optimization just as an arithmetic operator\n+ * would be.\n+ * [...]\n+ */\n+#define __pure\t\t\t__attribute__((pure))\n+#define __aligned(x)\t\t__attribute__((aligned(x)))\n+#define __printf(a, b)\t\t__attribute__((format(printf, a, b)))\n+#define __scanf(a, b)\t\t__attribute__((format(scanf, a, b)))\n+#define __attribute_const__\t__attribute__((__const__))\n+#define __maybe_unused\t\t__attribute__((unused))\n+#define __always_unused\t\t__attribute__((unused))\n+\n+/* gcc version specific checks */\n+\n+#if GCC_VERSION < 30200\n+# error Sorry, your compiler is too old - please upgrade it.\n+#endif\n+\n+#if GCC_VERSION < 30300\n+# define __used\t\t\t__attribute__((__unused__))\n+#else\n+# define __used\t\t\t__attribute__((__used__))\n+#endif\n+\n+#ifdef CONFIG_GCOV_KERNEL\n+# if GCC_VERSION < 30400\n+#   error \"GCOV profiling support for gcc versions below 3.4 not included\"\n+# endif /* __GNUC_MINOR__ */\n+#endif /* CONFIG_GCOV_KERNEL */\n+\n+#if GCC_VERSION >= 30400\n+#define __must_check\t\t__attribute__((warn_unused_result))\n+#define __malloc\t\t__attribute__((__malloc__))\n+#endif\n+\n+#if GCC_VERSION >= 40000\n+\n+/* GCC 4.1.[01] miscompiles __weak */\n+#ifdef __KERNEL__\n+# if GCC_VERSION >= 40100 &&  GCC_VERSION <= 40101\n+#  error Your version of gcc miscompiles the __weak directive\n+# endif\n+#endif\n+\n+#define __used\t\t\t__attribute__((__used__))\n+#define __compiler_offsetof(a, b)\t\t\t\t\t\\\n+\t__builtin_offsetof(a, b)\n+\n+#if GCC_VERSION >= 40100 && GCC_VERSION < 40600\n+# define __compiletime_object_size(obj) __builtin_object_size(obj, 0)\n+#endif\n+\n+#if GCC_VERSION >= 40300\n+/* Mark functions as cold. gcc will assume any path leading to a call\n+ * to them will be unlikely.  This means a lot of manual unlikely()s\n+ * are unnecessary now for any paths leading to the usual suspects\n+ * like BUG(), printk(), panic() etc. [but let's keep them for now for\n+ * older compilers]\n+ *\n+ * Early snapshots of gcc 4.3 don't support this and we can't detect this\n+ * in the preprocessor, but we can live with this because they're unreleased.\n+ * Maketime probing would be overkill here.\n+ *\n+ * gcc also has a __attribute__((__hot__)) to move hot functions into\n+ * a special section, but I don't see any sense in this right now in\n+ * the kernel context\n+ */\n+#define __cold\t\t\t__attribute__((__cold__))\n+\n+#define __UNIQUE_ID(prefix) __PASTE(__PASTE(__UNIQUE_ID_, prefix), __COUNTER__)\n+\n+#ifndef __CHECKER__\n+# define __compiletime_warning(message) __attribute__((warning(message)))\n+# define __compiletime_error(message) __attribute__((error(message)))\n+#endif /* __CHECKER__ */\n+#endif /* GCC_VERSION >= 40300 */\n+\n+#if GCC_VERSION >= 40500\n+/*\n+ * Mark a position in code as unreachable.  This can be used to\n+ * suppress control flow warnings after asm blocks that transfer\n+ * control elsewhere.\n+ *\n+ * Early snapshots of gcc 4.5 don't support this and we can't detect\n+ * this in the preprocessor, but we can live with this because they're\n+ * unreleased.  Really, we need to have autoconf for the kernel.\n+ */\n+#define unreachable() __builtin_unreachable()\n+\n+/* Mark a function definition as prohibited from being cloned. */\n+#define __noclone\t__attribute__((__noclone__, __optimize__(\"no-tracer\")))\n+\n+#endif /* GCC_VERSION >= 40500 */\n+\n+#if GCC_VERSION >= 40600\n+/*\n+ * When used with Link Time Optimization, gcc can optimize away C functions or\n+ * variables which are referenced only from assembly code.  __visible tells the\n+ * optimizer that something else uses this function or variable, thus preventing\n+ * this.\n+ */\n+#define __visible\t__attribute__((externally_visible))\n+#endif\n+\n+\n+#if GCC_VERSION >= 40900 && !defined(__CHECKER__)\n+/*\n+ * __assume_aligned(n, k): Tell the optimizer that the returned\n+ * pointer can be assumed to be k modulo n. The second argument is\n+ * optional (default 0), so we use a variadic macro to make the\n+ * shorthand.\n+ *\n+ * Beware: Do not apply this to functions which may return\n+ * ERR_PTRs. Also, it is probably unwise to apply it to functions\n+ * returning extra information in the low bits (but in that case the\n+ * compiler should see some alignment anyway, when the return value is\n+ * massaged by 'flags = ptr & 3; ptr &= ~3;').\n+ */\n+#define __assume_aligned(a, ...) __attribute__((__assume_aligned__(a, ## __VA_ARGS__)))\n+#endif\n+\n+/*\n+ * GCC 'asm goto' miscompiles certain code sequences:\n+ *\n+ *   http://gcc.gnu.org/bugzilla/show_bug.cgi?id=58670\n+ *\n+ * Work it around via a compiler barrier quirk suggested by Jakub Jelinek.\n+ *\n+ * (asm goto is automatically volatile - the naming reflects this.)\n+ */\n+#define asm_volatile_goto(x...)\tdo { asm goto(x); asm (\"\"); } while (0)\n+\n+#ifdef CONFIG_ARCH_USE_BUILTIN_BSWAP\n+#if GCC_VERSION >= 40400\n+#define __HAVE_BUILTIN_BSWAP32__\n+#define __HAVE_BUILTIN_BSWAP64__\n+#endif\n+#if GCC_VERSION >= 40800\n+#define __HAVE_BUILTIN_BSWAP16__\n+#endif\n+#endif /* CONFIG_ARCH_USE_BUILTIN_BSWAP */\n+\n+#if GCC_VERSION >= 50000\n+#define KASAN_ABI_VERSION 4\n+#elif GCC_VERSION >= 40902\n+#define KASAN_ABI_VERSION 3\n+#endif\n+\n+#if GCC_VERSION >= 40902\n+/*\n+ * Tell the compiler that address safety instrumentation (KASAN)\n+ * should not be applied to that function.\n+ * Conflicts with inlining: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67368\n+ */\n+#define __no_sanitize_address __attribute__((no_sanitize_address))\n+#endif\n+\n+#endif\t/* gcc version >= 40000 specific checks */\n+\n+#if !defined(__noclone)\n+#define __noclone\t/* not needed */\n+#endif\n+\n+#if !defined(__no_sanitize_address)\n+#define __no_sanitize_address\n+#endif\n+\n+/*\n+ * A trick to suppress uninitialized variable warning without generating any\n+ * code\n+ */\n+#define uninitialized_var(x) x = x\n"
  },
  {
    "path": "package/boot/uboot-oxnas/patches/800-fix-bootm-assertion.patch",
    "content": "--- a/common/cmd_bootm.c\n+++ b/common/cmd_bootm.c\n@@ -77,7 +77,7 @@ static int do_bootm_subcommand(cmd_tbl_t\n \t\treturn CMD_RET_USAGE;\n \t}\n \n-\tif (state != BOOTM_STATE_START && images.state >= state) {\n+\tif (!(state & BOOTM_STATE_START) && images.state >= state) {\n \t\tprintf(\"Trying to execute a command out of order\\n\");\n \t\treturn CMD_RET_USAGE;\n \t}\n"
  },
  {
    "path": "package/boot/uboot-oxnas/src/arch/arm/cpu/arm1136/nas782x/Makefile",
    "content": "#\n# (C) Copyright 2000-2006\n# Wolfgang Denk, DENX Software Engineering, wd@denx.de.\n#\n# (C) Copyright 2008-2009 Freescale Semiconductor, Inc.\n#\n# SPDX-License-Identifier:\tGPL-2.0+\n#\n\nobj-y\t+= reset.o\nobj-y\t+= timer.o\nobj-y\t+= clock.o\nobj-y\t+= pinmux.o\n"
  },
  {
    "path": "package/boot/uboot-oxnas/src/arch/arm/cpu/arm1136/nas782x/clock.c",
    "content": "#include <common.h>\n#include <asm/arch/sysctl.h>\n#include <asm/arch/cpu.h>\n#include <asm/arch/clock.h>\n\ntypedef struct {\n\tunsigned short mhz;\n\tunsigned char refdiv;\n\tunsigned char outdiv;\n\tunsigned int fbdiv;\n\tunsigned short bwadj;\n\tunsigned short sfreq;\n\tunsigned int sslope;\n} PLL_CONFIG;\n\nconst PLL_CONFIG C_PLL_CONFIG[] = {\n\t{ 500, 1, 2, 3932160, 119, 208, 189 }, //  500 MHz\n\t{ 525, 2, 1, 4128768, 125, 139, 297 }, //  525 MHz\n\t{ 550, 2, 1, 4325376, 131, 139, 311 }, //  550 MHz\n\t{ 575, 2, 1, 4521984, 137, 139, 326 }, //  575 MHz\n\t{ 600, 2, 1, 4718592, 143, 138, 339 }, //  600 MHz\n\t{ 625, 1, 1, 3276800, 99, 208, 157 }, //  625 MHz\n\t{ 650, 1, 1, 3407872, 103, 208, 164 }, //  650 MHz\n\t{ 675, 1, 1, 3538944, 107, 208, 170 }, //  675 MHz\n\t{ 700, 0, 0, 917504, 27, 416, 22 }, //  700 MHz\n\t{ 725, 1, 1, 3801088, 115, 208, 182 }, //  725 MHz\n\t{ 750, 0, 0, 983040, 29, 416, 23 }, //  750 MHz\n\t{ 775, 3, 0, 4063232, 123, 104, 390 }, //  775 MHz\n\t{ 800, 3, 0, 4194304, 127, 104, 403 }, //  800 MHz\n\t{ 825, 3, 0, 4325376, 131, 104, 415 }, //  825 MHz\n\t{ 850, 2, 0, 3342336, 101, 139, 241 }, //  850 MHz\n\t{ 875, 2, 0, 3440640, 104, 139, 248 }, //  875 MHz\n\t{ 900, 2, 0, 3538944, 107, 139, 255 }, //  900 MHz\n\t{ 925, 2, 0, 3637248, 110, 139, 262 }, //  925 MHz\n\t{ 950, 2, 0, 3735552, 113, 139, 269 }, //  950 MHz\n\t{ 975, 2, 0, 3833856, 116, 139, 276 }, //  975 MHz\n\t{ 1000, 2, 0, 3932160, 119, 139, 283 }, // 1000 MHz\n};\n\n#define PLL_BYPASS (1<<1)\n#define SAT_ENABLE (1<<3)\n\n#define PLL_OUTDIV_SHIFT\t4\n#define PLL_REFDIV_SHIFT\t8\n#define PLL_BWADJ_SHIFT\t\t16\n\n#define PLL_LOW_FREQ\t500\n#define PLL_FREQ_STEP\t25\nstatic void plla_configure(int outdiv, int refdiv, int fbdiv, int bwadj,\n                           int sfreq, int sslope)\n{\n\tsetbits_le32(SYS_CTRL_PLLA_CTRL0, PLL_BYPASS);\n\tudelay(10);\n\treset_block(SYS_CTRL_RST_PLLA, 1);\n\tudelay(10);\n\n\twritel((refdiv << PLL_REFDIV_SHIFT) | (outdiv << PLL_OUTDIV_SHIFT) |\n\t       SAT_ENABLE | PLL_BYPASS,\n\t       SYS_CTRL_PLLA_CTRL0);\n\n\twritel(fbdiv, SYS_CTRL_PLLA_CTRL1);\n\twritel((bwadj << PLL_BWADJ_SHIFT) | sfreq, SYS_CTRL_PLLA_CTRL2);\n\twritel(sslope, SYS_CTRL_PLLA_CTRL3);\n\n\tudelay(10); // 5us delay required (from TCI datasheet), use 10us\n\n\treset_block(SYS_CTRL_RST_PLLA, 0);\n\n\tudelay(100); // Delay for PLL to lock\n\n\tprintf(\"  plla_ctrl0 : %08x\\n\", readl(SYS_CTRL_PLLA_CTRL0));\n\tprintf(\"  plla_ctrl1 : %08x\\n\", readl(SYS_CTRL_PLLA_CTRL1));\n\tprintf(\"  plla_ctrl2 : %08x\\n\", readl(SYS_CTRL_PLLA_CTRL2));\n\tprintf(\"  plla_ctrl3 : %08x\\n\", readl(SYS_CTRL_PLLA_CTRL3));\n\n\tclrbits_le32(SYS_CTRL_PLLA_CTRL0, PLL_BYPASS); // Take PLL out of bypass\n\tputs(\"\\nPLLA Set\\n\");\n}\n\nint plla_set_config(int mhz)\n{\n\tint index = (mhz - PLL_LOW_FREQ) / PLL_FREQ_STEP;\n\tconst PLL_CONFIG *cfg;\n\n\tif (index < 0 || index > ARRAY_SIZE(C_PLL_CONFIG)) {\n\t\tdebug(\"Freq %d MHz out of range, default to lowest\\n\", mhz);\n\t\tindex = 0;\n\t}\n\tcfg = &C_PLL_CONFIG[index];\n\n\tprintf(\"Attempting to set PLLA to %d MHz ...\\n\", (unsigned) cfg->mhz);\n\tplla_configure(cfg->outdiv, cfg->refdiv, cfg->fbdiv, cfg->bwadj,\n\t               cfg->sfreq, cfg->sslope);\n\n\treturn cfg->mhz;\n}\n\n"
  },
  {
    "path": "package/boot/uboot-oxnas/src/arch/arm/cpu/arm1136/nas782x/pinmux.c",
    "content": "#include <common.h>\n#include <asm/arch/pinmux.h>\n\nvoid pinmux_set(int bank, int pin, int func)\n{\n\tu32 reg;\n\tu32 base;\n\t/* TODO: check parameters */\n\n\tif (bank == PINMUX_BANK_MFA)\n\t\tbase = SYS_CONTROL_BASE;\n\telse\n\t\tbase = SEC_CONTROL_BASE;\n\n\tclrbits_le32(base + PINMUX_SECONDARY_SEL, BIT(pin));\n\tclrbits_le32(base + PINMUX_TERTIARY_SEL, BIT(pin));\n\tclrbits_le32(base + PINMUX_QUATERNARY_SEL, BIT(pin));\n\tclrbits_le32(base + PINMUX_DEBUG_SEL, BIT(pin));\n\tclrbits_le32(base + PINMUX_ALTERNATIVE_SEL, BIT(pin));\n\n\tswitch (func) {\n\tcase PINMUX_GPIO:\n\tdefault:\n\t\treturn;\n\t\tbreak;\n\tcase PINMUX_2:\n\t\treg = base + PINMUX_SECONDARY_SEL;\n\t\tbreak;\n\tcase PINMUX_3:\n\t\treg = base + PINMUX_TERTIARY_SEL;\n\t\tbreak;\n\tcase PINMUX_4:\n\t\treg = base + PINMUX_QUATERNARY_SEL;\n\t\tbreak;\n\tcase PINMUX_DEBUG:\n\t\treg = base + PINMUX_DEBUG_SEL;\n\t\tbreak;\n\tcase PINMUX_ALT:\n\t\treg = base + PINMUX_ALTERNATIVE_SEL;\n\t\tbreak;\n\t}\n\tsetbits_le32(reg, BIT(pin));\n}\n"
  },
  {
    "path": "package/boot/uboot-oxnas/src/arch/arm/cpu/arm1136/nas782x/reset.c",
    "content": "#include <common.h>\n#include <asm/arch/sysctl.h>\n#include <asm/arch/pinmux.h>\n#include <asm/arch/clock.h>\n\nvoid reset_cpu(ulong addr)\n{\n\tu32 value;\n\n\t// Assert reset to cores as per power on defaults\n\t// Don't touch the DDR interface as things will come to an impromptu stop\n\t// NB Possibly should be asserting reset for PLLB, but there are timing\n\t//    concerns here according to the docs\n\n\tvalue =\n\t\tBIT(SYS_CTRL_RST_COPRO     ) |\n\t\tBIT(SYS_CTRL_RST_USBHS     ) |\n\t\tBIT(SYS_CTRL_RST_USBHSPHYA ) |\n\t\tBIT(SYS_CTRL_RST_MACA      ) |\n\t\tBIT(SYS_CTRL_RST_PCIEA     ) |\n\t\tBIT(SYS_CTRL_RST_SGDMA     ) |\n\t\tBIT(SYS_CTRL_RST_CIPHER    ) |\n\t\tBIT(SYS_CTRL_RST_SATA      ) |\n\t\tBIT(SYS_CTRL_RST_SATA_LINK ) |\n\t\tBIT(SYS_CTRL_RST_SATA_PHY  ) |\n\t\tBIT(SYS_CTRL_RST_PCIEPHY   ) |\n\t\tBIT(SYS_CTRL_RST_STATIC    ) |\n\t\tBIT(SYS_CTRL_RST_UART1     ) |\n\t\tBIT(SYS_CTRL_RST_UART2     ) |\n\t\tBIT(SYS_CTRL_RST_MISC      ) |\n\t\tBIT(SYS_CTRL_RST_I2S       ) |\n\t\tBIT(SYS_CTRL_RST_SD        ) |\n\t\tBIT(SYS_CTRL_RST_MACB      ) |\n\t\tBIT(SYS_CTRL_RST_PCIEB     ) |\n\t\tBIT(SYS_CTRL_RST_VIDEO     ) |\n\t\tBIT(SYS_CTRL_RST_USBHSPHYB ) |\n\t\tBIT(SYS_CTRL_RST_USBDEV    );\n\n\twritel(value, SYS_CTRL_RST_SET_CTRL);\n\n\t// Release reset to cores as per power on defaults\n\twritel(BIT(SYS_CTRL_RST_GPIO), SYS_CTRL_RST_CLR_CTRL);\n\n\t// Disable clocks to cores as per power-on defaults - must leave DDR\n\t// related clocks enabled otherwise we'll stop rather abruptly.\n\tvalue =\n\t\tBIT(SYS_CTRL_CLK_COPRO) \t|\n\t\tBIT(SYS_CTRL_CLK_DMA)   \t|\n\t\tBIT(SYS_CTRL_CLK_CIPHER)\t|\n\t\tBIT(SYS_CTRL_CLK_SD)  \t\t|\n\t\tBIT(SYS_CTRL_CLK_SATA)  \t|\n\t\tBIT(SYS_CTRL_CLK_I2S)   \t|\n\t\tBIT(SYS_CTRL_CLK_USBHS) \t|\n\t\tBIT(SYS_CTRL_CLK_MAC)   \t|\n\t\tBIT(SYS_CTRL_CLK_PCIEA)   \t|\n\t\tBIT(SYS_CTRL_CLK_STATIC)\t|\n\t\tBIT(SYS_CTRL_CLK_MACB)\t\t|\n\t\tBIT(SYS_CTRL_CLK_PCIEB)\t\t|\n\t\tBIT(SYS_CTRL_CLK_REF600)\t|\n\t\tBIT(SYS_CTRL_CLK_USBDEV);\n\n\twritel(value, SYS_CTRL_CLK_CLR_CTRL);\n\n\t// Enable clocks to cores as per power-on defaults\n\n\t// Set sys-control pin mux'ing as per power-on defaults\n\n\twritel(0, SYS_CONTROL_BASE + PINMUX_SECONDARY_SEL);\n\twritel(0, SYS_CONTROL_BASE + PINMUX_TERTIARY_SEL);\n\twritel(0, SYS_CONTROL_BASE + PINMUX_QUATERNARY_SEL);\n\twritel(0, SYS_CONTROL_BASE + PINMUX_DEBUG_SEL);\n\twritel(0, SYS_CONTROL_BASE + PINMUX_ALTERNATIVE_SEL);\n\twritel(0, SYS_CONTROL_BASE + PINMUX_PULLUP_SEL);\n\n\twritel(0, SEC_CONTROL_BASE + PINMUX_SECONDARY_SEL);\n\twritel(0, SEC_CONTROL_BASE + PINMUX_TERTIARY_SEL);\n\twritel(0, SEC_CONTROL_BASE + PINMUX_QUATERNARY_SEL);\n\twritel(0, SEC_CONTROL_BASE + PINMUX_DEBUG_SEL);\n\twritel(0, SEC_CONTROL_BASE + PINMUX_ALTERNATIVE_SEL);\n\twritel(0, SEC_CONTROL_BASE + PINMUX_PULLUP_SEL);\n\n\t// No need to save any state, as the ROM loader can determine whether reset\n\t// is due to power cycling or programatic action, just hit the (self-\n\t// clearing) CPU reset bit of the block reset register\n\tvalue =\n\t\tBIT(SYS_CTRL_RST_SCU) |\n\t\tBIT(SYS_CTRL_RST_ARM0) |\n\t\tBIT(SYS_CTRL_RST_ARM1);\n\n\twritel(value, SYS_CTRL_RST_SET_CTRL);\n}\n"
  },
  {
    "path": "package/boot/uboot-oxnas/src/arch/arm/cpu/arm1136/nas782x/timer.c",
    "content": "/*\n * (C) Copyright 2004\n * Texas Instruments\n * Richard Woodruff <r-woodruff2@ti.com>\n *\n * (C) Copyright 2002\n * Sysgo Real-Time Solutions, GmbH <www.elinos.com>\n * Marius Groeger <mgroeger@sysgo.de>\n * Alex Zuepke <azu@sysgo.de>\n *\n * (C) Copyright 2002\n * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>\n *\n * See file CREDITS for list of people who contributed to this\n * project.\n *\n * This program is free software; you can redistribute it and/or\n * modify it under the terms of the GNU General Public License as\n * published by the Free Software Foundation; either version 2 of\n * the License, or (at your option) any later version.\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n * GNU General Public License for more details.\n *\n * You should have received a copy of the GNU General Public License\n * along with this program; if not, write to the Free Software\n * Foundation, Inc., 59 Temple Place, Suite 330, Boston,\n * MA 02111-1307 USA\n */\n\n#include <common.h>\n#include <asm/io.h>\n\n#define TIMER_CLOCK\t(CONFIG_SYS_CLK_FREQ / (1 << (CONFIG_TIMER_PRESCALE * 4)))\n#define TIMER_LOAD_VAL 0xFFFFFF\n\n/* macro to read the 32 bit timer */\n#define READ_TIMER\t(TIMER_LOAD_VAL - readl(CONFIG_SYS_TIMERBASE + TIMER_CURR)) \\\n\t\t\t/ (TIMER_CLOCK / CONFIG_SYS_HZ)\n\n#define READ_TIMER_HW\t(TIMER_LOAD_VAL - readl(CONFIG_SYS_TIMERBASE + TIMER_CURR))\n\nDECLARE_GLOBAL_DATA_PTR;\n\nint timer_init (void)\n{\n\tint32_t val;\n\n\t/* Start the counter ticking up */\n\twritel(TIMER_LOAD_VAL, CONFIG_SYS_TIMERBASE + TIMER_LOAD);\t/* reload value on overflow*/\n\n\tval = (CONFIG_TIMER_PRESCALE << TIMER_PRESCALE_SHIFT) |\n\t\t\t(TIMER_MODE_PERIODIC << TIMER_MODE_SHIFT) |\n\t\t\t(TIMER_ENABLE << TIMER_ENABLE_SHIFT);\t\t/* mask to enable timer*/\n\twritel(val, CONFIG_SYS_TIMERBASE + TIMER_CTRL);\t/* start timer */\n\n\t/* reset time */\n\tgd->arch.lastinc = READ_TIMER;\t/* capture current incrementer value */\n\tgd->arch.tbl = 0;\t\t/* start \"advancing\" time stamp */\n\n\treturn(0);\n}\n/*\n * timer without interrupts\n */\nulong get_timer (ulong base)\n{\n\treturn get_timer_masked () - base;\n}\n\n/* delay x useconds AND preserve advance timestamp value */\nvoid __udelay (unsigned long usec)\n{\n\tulong tmo, tmp;\n\n\tif (usec > 100000) {\t\t/* if \"big\" number, spread normalization to seconds */\n\t\ttmo = usec / 1000;\t/* start to normalize for usec to ticks per sec */\n\t\ttmo *= CONFIG_SYS_HZ;\t/* find number of \"ticks\" to wait to achieve target */\n\t\ttmo /= 1000;\t\t/* finish normalize. */\n\n\t\ttmp = get_timer (0);\t\t/* get current timestamp */\n\t\twhile (get_timer (tmp) < tmo)/* loop till event */\n\t\t\t/*NOP*/;\n\t} else {\t\t\t/* else small number, convert to hw ticks */\n\t\ttmo = usec * (TIMER_CLOCK / 1000) / 1000;\n\t\t/* timeout is no more than 0.1s, and the hw timer will roll over at most once */\n\t\ttmp = READ_TIMER_HW;\n\t\twhile (((READ_TIMER_HW -tmp) & TIMER_LOAD_VAL) < tmo)/* loop till event */\n\t\t\t/*NOP*/;\n\t}\n}\n\nulong get_timer_masked (void)\n{\n\tulong now = READ_TIMER;\t\t/* current tick value */\n\n\tif (now >= gd->arch.lastinc) {\t\t/* normal mode (non roll) */\n\t\t/* move stamp fordward with absoulte diff ticks */\n\t\tgd->arch.tbl += (now - gd->arch.lastinc);\n\t} else {\n\t\t/* we have rollover of incrementer */\n\t\tgd->arch.tbl += ((TIMER_LOAD_VAL / (TIMER_CLOCK / CONFIG_SYS_HZ))\n\t\t\t\t - gd->arch.lastinc) + now;\n\t}\n\tgd->arch.lastinc = now;\n\treturn gd->arch.tbl;\n}\n\n\n/*\n * This function is derived from PowerPC code (read timebase as long long).\n * On ARM it just returns the timer value.\n */\nunsigned long long get_ticks(void)\n{\n\treturn get_timer(0);\n}\n/*\n * This function is derived from PowerPC code (timebase clock frequency).\n * On ARM it returns the number of timer ticks per second.\n */\nulong get_tbclk (void)\n{\n\tulong tbclk;\n\ttbclk = CONFIG_SYS_HZ;\n\treturn tbclk;\n}\n"
  },
  {
    "path": "package/boot/uboot-oxnas/src/arch/arm/include/asm/arch-nas782x/clock.h",
    "content": "#ifndef _NAS782X_CLOCK_H\n#define _NAS782X_CLOCK_H\n\n#include <asm/arch/sysctl.h>\n#include <asm/arch/cpu.h>\n\n/* bit numbers of clock control register */\n#define SYS_CTRL_CLK_COPRO  0\n#define SYS_CTRL_CLK_DMA    1\n#define SYS_CTRL_CLK_CIPHER 2\n#define SYS_CTRL_CLK_SD     3\n#define SYS_CTRL_CLK_SATA   4\n#define SYS_CTRL_CLK_I2S    5\n#define SYS_CTRL_CLK_USBHS  6\n#define SYS_CTRL_CLK_MACA   7\n#define SYS_CTRL_CLK_MAC   SYS_CTRL_CLK_MACA\n#define SYS_CTRL_CLK_PCIEA  8\n#define SYS_CTRL_CLK_STATIC 9\n#define SYS_CTRL_CLK_MACB   10\n#define SYS_CTRL_CLK_PCIEB  11\n#define SYS_CTRL_CLK_REF600 12\n#define SYS_CTRL_CLK_USBDEV 13\n#define SYS_CTRL_CLK_DDR    14\n#define SYS_CTRL_CLK_DDRPHY 15\n#define SYS_CTRL_CLK_DDRCK  16\n\n/* bit numbers of reset control register */\n#define SYS_CTRL_RST_SCU          0\n#define SYS_CTRL_RST_COPRO        1\n#define SYS_CTRL_RST_ARM0         2\n#define SYS_CTRL_RST_ARM1         3\n#define SYS_CTRL_RST_USBHS        4\n#define SYS_CTRL_RST_USBHSPHYA    5\n#define SYS_CTRL_RST_MACA         6\n#define SYS_CTRL_RST_MAC\tSYS_CTRL_RST_MACA\n#define SYS_CTRL_RST_PCIEA        7\n#define SYS_CTRL_RST_SGDMA        8\n#define SYS_CTRL_RST_CIPHER       9\n#define SYS_CTRL_RST_DDR          10\n#define SYS_CTRL_RST_SATA         11\n#define SYS_CTRL_RST_SATA_LINK    12\n#define SYS_CTRL_RST_SATA_PHY     13\n#define SYS_CTRL_RST_PCIEPHY      14\n#define SYS_CTRL_RST_STATIC       15\n#define SYS_CTRL_RST_GPIO         16\n#define SYS_CTRL_RST_UART1        17\n#define SYS_CTRL_RST_UART2        18\n#define SYS_CTRL_RST_MISC         19\n#define SYS_CTRL_RST_I2S          20\n#define SYS_CTRL_RST_SD           21\n#define SYS_CTRL_RST_MACB         22\n#define SYS_CTRL_RST_PCIEB        23\n#define SYS_CTRL_RST_VIDEO        24\n#define SYS_CTRL_RST_DDR_PHY      25\n#define SYS_CTRL_RST_USBHSPHYB    26\n#define SYS_CTRL_RST_USBDEV       27\n#define SYS_CTRL_RST_ARMDBG       29\n#define SYS_CTRL_RST_PLLA         30\n#define SYS_CTRL_RST_PLLB         31\n\nstatic inline void reset_block(int block, int reset)\n{\n\tu32 reg;\n\tif (reset)\n\t\treg = SYS_CTRL_RST_SET_CTRL;\n\telse\n\t\treg = SYS_CTRL_RST_CLR_CTRL;\n\n\twritel(BIT(block), reg);\n}\n\nstatic inline void enable_clock(int block)\n{\n\twritel(BIT(block), SYS_CTRL_CLK_SET_CTRL);\n}\n\nstatic inline void disable_clock(int block)\n{\n\twritel(BIT(block), SYS_CTRL_CLK_CLR_CTRL);\n}\n\nint plla_set_config(int idx);\n\n#endif /* _NAS782X_CLOCK_H */\n"
  },
  {
    "path": "package/boot/uboot-oxnas/src/arch/arm/include/asm/arch-nas782x/cpu.h",
    "content": "#ifndef _NAS782X_CPU_H\n#define _NAS782X_CPU_H\n\n#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))\n#include <asm/types.h>\n#include <asm/io.h>\n#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */\n\n#include <asm/arch/hardware.h>\n#include <asm/arch/timer.h>\n\n#ifndef __KERNEL_STRICT_NAMES\n#ifndef __ASSEMBLY__\n\n#define BIT(x)                  (1 << (x))\n\n/* fix \"implicit declaration of function\" warnning */\nvoid *memalign(size_t alignment, size_t bytes);\nvoid free(void* mem);\nvoid *malloc(size_t bytes);\nvoid *calloc(size_t n, size_t elem_size);\n\n#endif /* __ASSEMBLY__ */\n#endif /* __KERNEL_STRICT_NAMES */\n\n#endif /* _NAS782X_CPU_H */\n"
  },
  {
    "path": "package/boot/uboot-oxnas/src/arch/arm/include/asm/arch-nas782x/hardware.h",
    "content": "#ifndef _NAS782X_HARDWARE_H\n#define _NAS782X_HARDWARE_H\n\n/* Core addresses */\n#define USB_HOST_BASE\t\t0x40200000\n#define MACA_BASE\t\t0x40400000\n#define MACB_BASE\t\t0x40800000\n#define MAC_BASE\t\tMACA_BASE\n#define STATIC_CS0_BASE\t\t0x41000000\n#define STATIC_CS1_BASE\t\t0x41400000\n#define STATIC_CONTROL_BASE\t0x41C00000\n#define SATA_DATA_BASE\t\t0x42000000 /* non-functional, DMA just needs an address */\n#define GPIO_1_BASE\t\t0x44000000\n#define GPIO_2_BASE\t\t0x44100000\n#define UART_1_BASE\t\t0x44200000\n#define UART_2_BASE\t\t0x44300000\n#define SYS_CONTROL_BASE\t0x44e00000\n#define SEC_CONTROL_BASE\t0x44f00000\n#define RPSA_BASE\t\t0x44400000\n#define RPSC_BASE\t\t0x44500000\n#define DDR_BASE\t\t0x44700000\n\n#define SATA_BASE\t\t0x45900000\n#define SATA_0_REGS_BASE\t0x45900000\n#define SATA_1_REGS_BASE\t0x45910000\n#define SATA_DMA_REGS_BASE\t0x459a0000\n#define SATA_SGDMA_REGS_BASE\t0x459b0000\n#define SATA_HOST_REGS_BASE\t0x459e0000\n\n#endif /* _NAS782X_HARDWARE_H */\n"
  },
  {
    "path": "package/boot/uboot-oxnas/src/arch/arm/include/asm/arch-nas782x/pinmux.h",
    "content": "#ifndef _NAS782X_PINMUX_H\n#define _NAS782X_PINMUX_H\n\n#include <asm/arch/cpu.h>\n\n#define PINMUX_GPIO\t\t0\n#define PINMUX_2\t\t1\n#define PINMUX_3\t\t2\n#define PINMUX_4\t\t3\n#define PINMUX_DEBUG\t\t4\n#define PINMUX_ALT\t\t5\n\n#define PINMUX_BANK_MFA\t\t0\n#define PINMUX_BANK_MFB\t\t1\n\n/* System control multi-function pin function selection */\n#define PINMUX_SECONDARY_SEL\t\t0x14\n#define PINMUX_TERTIARY_SEL\t\t0x8c\n#define PINMUX_QUATERNARY_SEL\t\t0x94\n#define PINMUX_DEBUG_SEL\t\t0x9c\n#define PINMUX_ALTERNATIVE_SEL\t\t0xa4\n#define PINMUX_PULLUP_SEL\t\t0xac\n\n#define PINMUX_UARTA_SIN\t\tPINMUX_ALT\n#define PINMUX_UARTA_SOUT\t\tPINMUX_ALT\n\n#define PINMUX_STATIC_DATA0\t\tPINMUX_2\n#define PINMUX_STATIC_DATA1\t\tPINMUX_2\n#define PINMUX_STATIC_DATA2\t\tPINMUX_2\n#define PINMUX_STATIC_DATA3\t\tPINMUX_2\n#define PINMUX_STATIC_DATA4\t\tPINMUX_2\n#define PINMUX_STATIC_DATA5\t\tPINMUX_2\n#define PINMUX_STATIC_DATA6\t\tPINMUX_2\n#define PINMUX_STATIC_DATA7\t\tPINMUX_2\n#define PINMUX_STATIC_NWE\t\tPINMUX_2\n#define PINMUX_STATIC_NOE\t\tPINMUX_2\n#define PINMUX_STATIC_NCS\t\tPINMUX_2\n#define PINMUX_STATIC_ADDR18\t\tPINMUX_2\n#define PINMUX_STATIC_ADDR19\t\tPINMUX_2\n\n#define PINMUX_MACA_MDC\t\t\tPINMUX_2\n#define PINMUX_MACA_MDIO\t\tPINMUX_2\n\nextern void pinmux_set(int bank, int pin, int func);\n\n#endif /* _NAS782X_PINMUX_H */\n"
  },
  {
    "path": "package/boot/uboot-oxnas/src/arch/arm/include/asm/arch-nas782x/spl.h",
    "content": "#ifndef _NAS782X_SPL_H\n#define _NAS782X_SPL_H\n\n#include <asm/arch/cpu.h>\n\n#endif /* _NAS782X_SPL_H */\n"
  },
  {
    "path": "package/boot/uboot-oxnas/src/arch/arm/include/asm/arch-nas782x/sysctl.h",
    "content": "#ifndef _NAS782X_SYSCTL_H\n#define _NAS782X_SYSCTL_H\n\n#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))\n#include <asm/types.h>\n#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */\n\n#include <asm/arch/hardware.h>\n\n/**\n * System block reset and clock control\n */\n#define SYS_CTRL_PCI_STAT\t\t(SYS_CONTROL_BASE + 0x20)\n#define SYS_CTRL_CLK_SET_CTRL\t\t(SYS_CONTROL_BASE + 0x2C)\n#define SYS_CTRL_CLK_CLR_CTRL\t\t(SYS_CONTROL_BASE + 0x30)\n#define SYS_CTRL_RST_SET_CTRL\t\t(SYS_CONTROL_BASE + 0x34)\n#define SYS_CTRL_RST_CLR_CTRL\t\t(SYS_CONTROL_BASE + 0x38)\n#define SYS_CTRL_PLLSYS_CTRL\t\t(SYS_CONTROL_BASE + 0x48)\n#define SYS_CTRL_PLLSYS_KEY_CTRL\t(SYS_CONTROL_BASE + 0x6C)\n#define SYS_CTRL_GMAC_CTRL\t\t(SYS_CONTROL_BASE + 0x78)\n\n/* Scratch registers */\n#define SYS_CTRL_SCRATCHWORD0\t\t(SYS_CONTROL_BASE + 0xc4)\n#define SYS_CTRL_SCRATCHWORD1\t\t(SYS_CONTROL_BASE + 0xc8)\n#define SYS_CTRL_SCRATCHWORD2\t\t(SYS_CONTROL_BASE + 0xcc)\n#define SYS_CTRL_SCRATCHWORD3\t\t(SYS_CONTROL_BASE + 0xd0)\n\n#define SYS_CTRL_PLLA_CTRL0\t\t(SYS_CONTROL_BASE + 0x1F0)\n#define SYS_CTRL_PLLA_CTRL1\t\t(SYS_CONTROL_BASE + 0x1F4)\n#define SYS_CTRL_PLLA_CTRL2\t\t(SYS_CONTROL_BASE + 0x1F8)\n#define SYS_CTRL_PLLA_CTRL3\t\t(SYS_CONTROL_BASE + 0x1FC)\n\n#define SYS_CTRL_GMAC_AUTOSPEED\t\t3\n#define SYS_CTRL_GMAC_RGMII\t\t2\n#define SYS_CTRL_GMAC_SIMPLE_MUX\t1\n#define SYS_CTRL_GMAC_CKEN_GTX\t\t0\n\n#define SYS_CTRL_CKCTRL_CTRL_ADDR\t(SYS_CONTROL_BASE + 0x64)\n\n#define SYS_CTRL_CKCTRL_PCI_DIV_BIT\t0\n#define SYS_CTRL_CKCTRL_SLOW_BIT\t8\n\n\n#define SYS_CTRL_USBHSMPH_CTRL\t\t(SYS_CONTROL_BASE + 0x40)\n#define SYS_CTRL_USBHSMPH_STAT\t\t(SYS_CONTROL_BASE + 0x44)\n#define SYS_CTRL_REF300_DIV\t\t(SYS_CONTROL_BASE + 0xF8)\n#define SYS_CTRL_USBHSPHY_CTRL\t\t(SYS_CONTROL_BASE + 0x84)\n#define SYS_CTRL_USB_CTRL\t\t(SYS_CONTROL_BASE + 0x90)\n\n/* System control multi-function pin function selection */\n#define SYS_CTRL_SECONDARY_SEL\t\t(SYS_CONTROL_BASE + 0x14)\n#define SYS_CTRL_TERTIARY_SEL\t\t(SYS_CONTROL_BASE + 0x8c)\n#define SYS_CTRL_QUATERNARY_SEL\t\t(SYS_CONTROL_BASE + 0x94)\n#define SYS_CTRL_DEBUG_SEL\t\t(SYS_CONTROL_BASE + 0x9c)\n#define SYS_CTRL_ALTERNATIVE_SEL\t(SYS_CONTROL_BASE + 0xa4)\n#define SYS_CTRL_PULLUP_SEL\t\t(SYS_CONTROL_BASE + 0xac)\n\n/* Secure control multi-function pin function selection */\n#define SEC_CTRL_SECONDARY_SEL\t\t(SEC_CONTROL_BASE + 0x14)\n#define SEC_CTRL_TERTIARY_SEL\t\t(SEC_CONTROL_BASE + 0x8c)\n#define SEC_CTRL_QUATERNARY_SEL\t\t(SEC_CONTROL_BASE + 0x94)\n#define SEC_CTRL_DEBUG_SEL\t\t(SEC_CONTROL_BASE + 0x9c)\n#define SEC_CTRL_ALTERNATIVE_SEL\t(SEC_CONTROL_BASE + 0xa4)\n#define SEC_CTRL_PULLUP_SEL\t\t(SEC_CONTROL_BASE + 0xac)\n\n#define SEC_CTRL_COPRO_CTRL\t\t(SEC_CONTROL_BASE + 0x68)\n#define SEC_CTRL_SECURE_CTRL\t\t(SEC_CONTROL_BASE + 0x98)\n#define SEC_CTRL_LEON_DEBUG\t\t(SEC_CONTROL_BASE + 0xF0)\n#define SEC_CTRL_PLLB_DIV_CTRL\t\t(SEC_CONTROL_BASE + 0xF8)\n#define SEC_CTRL_PLLB_CTRL0\t\t(SEC_CONTROL_BASE + 0x1F0)\n#define SEC_CTRL_PLLB_CTRL1\t\t(SEC_CONTROL_BASE + 0x1F4)\n#define SEC_CTRL_PLLB_CTRL8\t\t(SEC_CONTROL_BASE + 0x1F4)\n\n#define REF300_DIV_INT_SHIFT\t\t8\n#define REF300_DIV_FRAC_SHIFT\t\t0\n#define REF300_DIV_INT(val)\t\t((val) << REF300_DIV_INT_SHIFT)\n#define REF300_DIV_FRAC(val)\t\t((val) << REF300_DIV_FRAC_SHIFT)\n\n#define USBHSPHY_SUSPENDM_MANUAL_ENABLE\t\t16\n#define USBHSPHY_SUSPENDM_MANUAL_STATE\t\t15\n#define USBHSPHY_ATE_ESET\t\t\t14\n#define USBHSPHY_TEST_DIN\t\t\t6\n#define USBHSPHY_TEST_ADD\t\t\t2\n#define USBHSPHY_TEST_DOUT_SEL\t\t\t1\n#define USBHSPHY_TEST_CLK\t\t\t0\n\n#define USB_CTRL_USBAPHY_CKSEL_SHIFT\t5\n#define USB_CLK_XTAL0_XTAL1\t\t(0 << USB_CTRL_USBAPHY_CKSEL_SHIFT)\n#define USB_CLK_XTAL0\t\t\t(1 << USB_CTRL_USBAPHY_CKSEL_SHIFT)\n#define USB_CLK_INTERNAL\t\t(2 << USB_CTRL_USBAPHY_CKSEL_SHIFT)\n\n#define USBAMUX_DEVICE\t\t\tBIT(4)\n\n#define USBPHY_REFCLKDIV_SHIFT\t\t2\n#define USB_PHY_REF_12MHZ\t\t(0 << USBPHY_REFCLKDIV_SHIFT)\n#define USB_PHY_REF_24MHZ\t\t(1 << USBPHY_REFCLKDIV_SHIFT)\n#define USB_PHY_REF_48MHZ\t\t(2 << USBPHY_REFCLKDIV_SHIFT)\n\n#define USB_CTRL_USB_CKO_SEL_BIT\t0\n\n#define USB_INT_CLK_XTAL \t\t0\n#define USB_INT_CLK_REF300\t\t2\n#define USB_INT_CLK_PLLB\t\t3\n\n#define SYS_CTRL_GMAC_AUTOSPEED\t\t3\n#define SYS_CTRL_GMAC_RGMII\t\t2\n#define SYS_CTRL_GMAC_SIMPLE_MUX\t1\n#define SYS_CTRL_GMAC_CKEN_GTX\t\t0\n\n\n#define PLLB_ENSAT\t\t\t3\n#define PLLB_OUTDIV\t\t\t4\n#define PLLB_REFDIV\t\t\t8\n#define PLLB_DIV_INT_SHIFT\t\t8\n#define PLLB_DIV_FRAC_SHIFT\t\t0\n#define PLLB_DIV_INT(val)\t\t((val) << PLLB_DIV_INT_SHIFT)\n#define PLLB_DIV_FRAC(val)\t\t((val) << PLLB_DIV_FRAC_SHIFT)\n\n#ifndef __KERNEL_STRICT_NAMES\n#ifndef __ASSEMBLY__\n\n#endif /* __ASSEMBLY__ */\n#endif /* __KERNEL_STRICT_NAMES */\n\n#endif /* _NAS782X_SYSCTL_H */\n"
  },
  {
    "path": "package/boot/uboot-oxnas/src/arch/arm/include/asm/arch-nas782x/timer.h",
    "content": "#ifndef _NAS782X_TIMER_H\n#define _NAS782X_TIMER_H\n\n#define TIMER1_BASE\t\t(RPSA_BASE + 0x200)\n#define TIMER2_BASE\t\t(RPSA_BASE + 0x220)\n\n#define TIMER_LOAD\t\t0\n#define TIMER_CURR\t\t4\n#define TIMER_CTRL\t\t8\n#define\tTIMER_INTR\t\t0x0C\n\n#define TIMER_PRESCALE_SHIFT\t\t2\n#define TIMER_PRESCALE_1\t\t0\n#define TIMER_PRESCALE_16\t\t1\n#define TIMER_PRESCALE_256\t\t2\n#define TIMER_MODE_SHIFT\t\t6\n#define TIMER_MODE_FREE_RUNNING\t\t0\n#define TIMER_MODE_PERIODIC\t\t1\n#define TIMER_ENABLE_SHIFT\t\t7\n#define TIMER_DISABLE\t\t\t0\n#define TIMER_ENABLE\t\t\t1\n\n#endif /* _NAS782X_TIMER_H */\n"
  },
  {
    "path": "package/boot/uboot-oxnas/src/board/ox820/Kconfig",
    "content": "if TARGET_OX820\n\nconfig SYS_CPU\n\tdefault \"arm1136\"\n\nconfig SYS_SOC\n\tdefault \"nas782x\"\n\nconfig SYS_BOARD\n\tdefault \"ox820\"\n\nconfig SYS_CONFIG_NAME\n\tdefault \"ox820\"\n\nendif\n"
  },
  {
    "path": "package/boot/uboot-oxnas/src/board/ox820/MAINTAINERS",
    "content": "SHEEVAPLUG BOARD\nM:\tDaniel Golle <daniel@makrotopia.org>\nS:\tMaintained\nF:\tboard/ox820/\nF:\tinclude/configs/ox820.h\nF:\tconfigs/ox820_defconfig\n"
  },
  {
    "path": "package/boot/uboot-oxnas/src/board/ox820/Makefile",
    "content": "#\n# (C) Copyright 2000-2006\n# Wolfgang Denk, DENX Software Engineering, wd@denx.de.\n#\n# (C) Copyright 2008-2009 Freescale Semiconductor, Inc.\n#\n# SPDX-License-Identifier:\tGPL-2.0+\n#\n\nobj-y += ox820.o\nobj-y += lowlevel_init.o\n\nobj-$(CONFIG_SPL_BUILD) += spl_start.o\nobj-$(CONFIG_SPL_BUILD) += ddr.o\n\n"
  },
  {
    "path": "package/boot/uboot-oxnas/src/board/ox820/ddr.c",
    "content": "/*******************************************************************\n *\n * File:            ddr_oxsemi.c\n *\n * Description:     Declarations for DDR routines and data objects\n *\n * Author:          Julien Margetts\n *\n * Copyright:       Oxford Semiconductor Ltd, 2009\n */\n#include <common.h>\n#include <asm/arch/clock.h>\n\n#include \"ddr.h\"\n\ntypedef unsigned int UINT;\n\n// DDR TIMING PARAMETERS\ntypedef struct {\n\tunsigned int holdoff_cmd_A;\n\tunsigned int holdoff_cmd_ARW;\n\tunsigned int holdoff_cmd_N;\n\tunsigned int holdoff_cmd_LM;\n\tunsigned int holdoff_cmd_R;\n\tunsigned int holdoff_cmd_W;\n\tunsigned int holdoff_cmd_PC;\n\tunsigned int holdoff_cmd_RF;\n\tunsigned int holdoff_bank_R;\n\tunsigned int holdoff_bank_W;\n\tunsigned int holdoff_dir_RW;\n\tunsigned int holdoff_dir_WR;\n\tunsigned int holdoff_FAW;\n\tunsigned int latency_CAS;\n\tunsigned int latency_WL;\n\tunsigned int recovery_WR;\n\tunsigned int width_update;\n\tunsigned int odt_offset;\n\tunsigned int odt_drive_all;\n\tunsigned int use_fixed_re;\n\tunsigned int delay_wr_to_re;\n\tunsigned int wr_slave_ratio;\n\tunsigned int rd_slave_ratio0;\n\tunsigned int rd_slave_ratio1;\n} T_DDR_TIMING_PARAMETERS;\n\n// DDR CONFIG PARAMETERS\n\ntypedef struct {\n\tunsigned int ddr_mode;\n\tunsigned int width;\n\tunsigned int blocs;\n\tunsigned int banks8;\n\tunsigned int rams;\n\tunsigned int asize;\n\tunsigned int speed;\n\tunsigned int cmd_mode_wr_cl_bl;\n} T_DDR_CONFIG_PARAMETERS;\n\n//cmd_mode_wr_cl_bl\n//when SDR : cmd_mode_wr_cl_bl = 0x80200002 + (latency_CAS_RAM * 16) + (recovery_WR - 1) * 512; -- Sets write rec XX, CL=XX; BL=8\n//else       cmd_mode_wr_cl_bl = 0x80200003 + (latency_CAS_RAM * 16) + (recovery_WR - 1) * 512; -- Sets write rec XX, CL=XX; BL=8\n\n//                                                            cmd_                    bank_ dir_     lat_  rec_ width_ odt_   odt_ fix delay     ratio\n//                                                                A                                F  C         update offset all  re  re_to_we  w  r0  r1\n//                                                                R     L        P  R        R  W  A  A  W  W\n//Timing Parameters                                            A  W  N  M  R  W  C  F  R  W  W  R  W  S  L  R\nstatic const T_DDR_TIMING_PARAMETERS C_TP_DDR2_25E_CL5_1GB = { 4, 5, 0, 2, 4, 4,\n\t5, 51, 23, 24, 9, 11, 18, 5, 4, 6, 3, 2, 0, 1, 2, 75, 56, 56 }; //elida device.\nstatic const T_DDR_TIMING_PARAMETERS C_TP_DDR2_25E_CL5_2GB = { 4, 5, 0, 2, 4, 4,\n\t5, 79, 22, 24, 9, 11, 20, 5, 4, 6, 3, 2, 0, 1, 2, 75, 56, 56 };\nstatic const T_DDR_TIMING_PARAMETERS C_TP_DDR2_25_CL6_1GB = { 4, 5, 0, 2, 4, 4,\n\t4, 51, 22, 26, 10, 12, 18, 6, 5, 6, 3, 2, 0, 1, 2, 75, 56, 56 }; // 400MHz, Speedgrade 25 timings (1Gb parts)\n\n//                                                          D     B  B  R  A   S\n//                                                          D  W  L  K  A  S   P\n//Config Parameters                                         R  D  C  8  M  Z   D CMD_MODE\n//static const T_DDR_CONFIG_PARAMETERS C_CP_DDR2_25E_CL5  = { 2,16, 1, 0, 1, 32,25,0x80200A53}; // 64 MByte\nstatic const T_DDR_CONFIG_PARAMETERS C_CP_DDR2_25E_CL5 = { 2, 16, 1, 1, 1, 64,\n\t25, 0x80200A53 }; // 128 MByte\nstatic const T_DDR_CONFIG_PARAMETERS C_CP_DDR2_25_CL6 = { 2, 16, 1, 1, 1, 128,\n\t25, 0x80200A63 }; // 256 MByte\n\nstatic void ddr_phy_poll_until_locked(void)\n{\n\tvolatile UINT reg_tmp = 0;\n\tvolatile UINT locked = 0;\n\n\t//Extra read to put in delay before starting to poll...\n\treg_tmp = *(volatile UINT *) C_DDR_REG_PHY2;      // read\n\n\t//POLL C_DDR_PHY2_REG register until clock and flock\n\t//!!! Ideally have a timeout on this.\n\twhile (locked == 0) {\n\t\treg_tmp = *(volatile UINT *) C_DDR_REG_PHY2;      // read\n\n\t\t//locked when bits 30 and 31 are set\n\t\tif (reg_tmp & 0xC0000000) {\n\t\t\tlocked = 1;\n\t\t}\n\t}\n}\n\nstatic void ddr_poll_until_not_busy(void)\n{\n\tvolatile UINT reg_tmp = 0;\n\tvolatile UINT busy = 1;\n\n\t//Extra read to put in delay before starting to poll...\n\treg_tmp = *(volatile UINT *) C_DDR_STAT_REG;      // read\n\n\t//POLL DDR_STAT register until no longer busy\n\t//!!! Ideally have a timeout on this.\n\twhile (busy == 1) {\n\t\treg_tmp = *(volatile UINT *) C_DDR_STAT_REG;      // read\n\n\t\t//when bit 31 is clear - core is no longer busy\n\t\tif ((reg_tmp & 0x80000000) == 0x00000000) {\n\t\t\tbusy = 0;\n\t\t}\n\t}\n}\n\nstatic void ddr_issue_command(int commmand)\n{\n\t*(volatile UINT *) C_DDR_CMD_REG = commmand;\n\tddr_poll_until_not_busy();\n}\n\nstatic void ddr_timing_initialisation(\n\tconst T_DDR_TIMING_PARAMETERS *ddr_timing_parameters)\n{\n\tvolatile UINT reg_tmp = 0;\n\t/* update the DDR controller registers for timing parameters */\n\treg_tmp = (ddr_timing_parameters->holdoff_cmd_A << 0);\n\treg_tmp = reg_tmp + (ddr_timing_parameters->holdoff_cmd_ARW << 4);\n\treg_tmp = reg_tmp + (ddr_timing_parameters->holdoff_cmd_N << 8);\n\treg_tmp = reg_tmp + (ddr_timing_parameters->holdoff_cmd_LM << 12);\n\treg_tmp = reg_tmp + (ddr_timing_parameters->holdoff_cmd_R << 16);\n\treg_tmp = reg_tmp + (ddr_timing_parameters->holdoff_cmd_W << 20);\n\treg_tmp = reg_tmp + (ddr_timing_parameters->holdoff_cmd_PC << 24);\n\t*(volatile UINT *) C_DDR_REG_TIMING0 = reg_tmp;\n\n\treg_tmp = (ddr_timing_parameters->holdoff_cmd_RF << 0);\n\treg_tmp = reg_tmp + (ddr_timing_parameters->holdoff_bank_R << 8);\n\treg_tmp = reg_tmp + (ddr_timing_parameters->holdoff_bank_W << 16);\n\treg_tmp = reg_tmp + (ddr_timing_parameters->holdoff_dir_RW << 24);\n\treg_tmp = reg_tmp + (ddr_timing_parameters->holdoff_dir_WR << 28);\n\t*(volatile UINT *) C_DDR_REG_TIMING1 = reg_tmp;\n\n\treg_tmp = (ddr_timing_parameters->latency_CAS << 0);\n\treg_tmp = reg_tmp + (ddr_timing_parameters->latency_WL << 4);\n\treg_tmp = reg_tmp + (ddr_timing_parameters->holdoff_FAW << 8);\n\treg_tmp = reg_tmp + (ddr_timing_parameters->width_update << 16);\n\treg_tmp = reg_tmp + (ddr_timing_parameters->odt_offset << 21);\n\treg_tmp = reg_tmp + (ddr_timing_parameters->odt_drive_all << 24);\n\n\t*(volatile UINT *) C_DDR_REG_TIMING2 = reg_tmp;\n\n\t/* Program the timing parameters in the PHY too */\n\treg_tmp = (ddr_timing_parameters->use_fixed_re << 16)\n\t\t\t| (ddr_timing_parameters->delay_wr_to_re << 8)\n\t\t\t| (ddr_timing_parameters->latency_WL << 4)\n\t\t\t| (ddr_timing_parameters->latency_CAS << 0);\n\n\t*(volatile UINT *) C_DDR_REG_PHY_TIMING = reg_tmp;\n\n\treg_tmp = ddr_timing_parameters->wr_slave_ratio;\n\n\t*(volatile UINT *) C_DDR_REG_PHY_WR_RATIO = reg_tmp;\n\n\treg_tmp = ddr_timing_parameters->rd_slave_ratio0;\n\treg_tmp += ddr_timing_parameters->rd_slave_ratio1 << 8;\n\n\t*(volatile UINT *) C_DDR_REG_PHY_RD_RATIO = reg_tmp;\n\n}\n\nstatic void ddr_normal_initialisation(\n\tconst T_DDR_CONFIG_PARAMETERS *ddr_config_parameters, int mhz)\n{\n\tint i;\n\tvolatile UINT tmp = 0;\n\tvolatile UINT reg_tmp = 0;\n\tvolatile UINT emr_cmd = 0;\n\tUINT refresh;\n\n\t//Total size of memory in Mbits...\n\ttmp = ddr_config_parameters->rams * ddr_config_parameters->asize\n\t\t* ddr_config_parameters->width;\n\t//Deduce value to program into DDR_CFG register...\n\tswitch (tmp) {\n\tcase 16:\n\t\treg_tmp = 0x00020000 * 1;\n\t\tbreak;\n\tcase 32:\n\t\treg_tmp = 0x00020000 * 2;\n\t\tbreak;\n\tcase 64:\n\t\treg_tmp = 0x00020000 * 3;\n\t\tbreak;\n\tcase 128:\n\t\treg_tmp = 0x00020000 * 4;\n\t\tbreak;\n\tcase 256:\n\t\treg_tmp = 0x00020000 * 5;\n\t\tbreak;\n\tcase 512:\n\t\treg_tmp = 0x00020000 * 6;\n\t\tbreak;\n\tcase 1024:\n\t\treg_tmp = 0x00020000 * 7;\n\t\tbreak;\n\tcase 2048:\n\t\treg_tmp = 0x00020000 * 8;\n\t\tbreak;\n\tdefault:\n\t\treg_tmp = 0; //forces sims not to work if badly configured\n\t}\n\n\t//Memory width\n\ttmp = ddr_config_parameters->rams * ddr_config_parameters->width;\n\tswitch (tmp) {\n\tcase 8:\n\t\treg_tmp = reg_tmp + 0x00400000;\n\t\tbreak;\n\tcase 16:\n\t\treg_tmp = reg_tmp + 0x00200000;\n\t\tbreak;\n\tcase 32:\n\t\treg_tmp = reg_tmp + 0x00000000;\n\t\tbreak;\n\tdefault:\n\t\treg_tmp = 0; //forces sims not to work if badly configured\n\t}\n\n\t//Setup DDR Mode\n\tswitch (ddr_config_parameters->ddr_mode) {\n\tcase 0:\n\t\treg_tmp = reg_tmp + 0x00000000;\n\t\tbreak;   //SDR\n\tcase 1:\n\t\treg_tmp = reg_tmp + 0x40000000;\n\t\tbreak;   //DDR\n\tcase 2:\n\t\treg_tmp = reg_tmp + 0x80000000;\n\t\tbreak;   //DDR2\n\tdefault:\n\t\treg_tmp = 0; //forces sims not to work if badly configured\n\t}\n\n\t//Setup Banks\n\tif (ddr_config_parameters->banks8 == 1) {\n\t\treg_tmp = reg_tmp + 0x00800000;\n\t}\n\n\t//Program DDR_CFG register...\n\t*(volatile UINT *) C_DDR_CFG_REG = reg_tmp;\n\n\t//Configure PHY0 reg - se_mode is bit 1,\n\t//needs to be 1 for DDR (single_ended drive)\n\tswitch (ddr_config_parameters->ddr_mode) {\n\tcase 0:\n\t\treg_tmp = 2 + (0 << 4);\n\t\tbreak;   //SDR\n\tcase 1:\n\t\treg_tmp = 2 + (4 << 4);\n\t\tbreak;   //DDR\n\tcase 2:\n\t\treg_tmp = 0 + (4 << 4);\n\t\tbreak;   //DDR2\n\tdefault:\n\t\treg_tmp = 0;\n\t}\n\n\t//Program DDR_PHY0 register...\n\t*(volatile UINT *) C_DDR_REG_PHY0 = reg_tmp;\n\n\t//Read DDR_PHY* registers to exercise paths for vcd\n\treg_tmp = *(volatile UINT *) C_DDR_REG_PHY3;\n\treg_tmp = *(volatile UINT *) C_DDR_REG_PHY2;\n\treg_tmp = *(volatile UINT *) C_DDR_REG_PHY1;\n\treg_tmp = *(volatile UINT *) C_DDR_REG_PHY0;\n\n\t//Start up sequences - Different dependant on DDR mode\n\tswitch (ddr_config_parameters->ddr_mode) {\n\tcase 2:   //DDR2\n\t\t//Start-up sequence: follows procedure described in Micron datasheet.\n\t\t//start up DDR PHY DLL\n\t\treg_tmp = 0x00022828;       // dll on, start point and inc = h28\n\t\t*(volatile UINT *) C_DDR_REG_PHY2 = reg_tmp;\n\n\t\treg_tmp = 0x00032828; // start on, dll on, start point and inc = h28\n\t\t*(volatile UINT *) C_DDR_REG_PHY2 = reg_tmp;\n\n\t\tddr_phy_poll_until_locked();\n\n\t\tudelay(200);   //200us\n\n\t\t//Startup SDRAM...\n\t\t//!!! Software: CK should be running for 200us before wake-up\n\t\tddr_issue_command( C_CMD_WAKE_UP);\n\t\tddr_issue_command( C_CMD_NOP);\n\t\tddr_issue_command( C_CMD_PRECHARGE_ALL);\n\t\tddr_issue_command( C_CMD_DDR2_EMR2);\n\t\tddr_issue_command( C_CMD_DDR2_EMR3);\n\n\t\temr_cmd = C_CMD_DDR2_EMR1 + C_CMD_ODT_75 + C_CMD_REDUCED_DRIVE\n\t\t\t+ C_CMD_ENABLE_DLL;\n\n\t\tddr_issue_command(emr_cmd);\n\t\t//Sets CL=3; BL=8 but also reset DLL to trigger a DLL initialisation...\n\t\tudelay(1);   //1us\n\t\tddr_issue_command(\n\t\t\tddr_config_parameters->cmd_mode_wr_cl_bl\n\t\t\t+ C_CMD_RESET_DLL);\n\t\tudelay(1);   //1us\n\n\t\t//!!! Software: Wait 200 CK cycles before...\n\t\t//for(i=1; i<=2; i++) {\n\t\tddr_issue_command(C_CMD_PRECHARGE_ALL);\n\t\t// !!! Software: Wait here at least 8 CK cycles\n\t\t//}\n\t\t//need a wait here to ensure PHY DLL lock before the refresh is issued\n\t\tudelay(1);   //1us\n\t\tfor (i = 1; i <= 2; i++) {\n\t\t\tddr_issue_command( C_CMD_AUTO_REFRESH);\n\t\t\t//!!! Software: Wait here at least 8 CK cycles to satify tRFC\n\t\t\tudelay(1);   //1us\n\t\t}\n\t\t//As before but without 'RESET_DLL' bit set...\n\t\tddr_issue_command(ddr_config_parameters->cmd_mode_wr_cl_bl);\n\t\tudelay(1);   //1us\n\t\t// OCD commands\n\t\tddr_issue_command(emr_cmd + C_CMD_MODE_DDR2_OCD_DFLT);\n\t\tddr_issue_command(emr_cmd + C_CMD_MODE_DDR2_OCD_EXIT);\n\t\tbreak;\n\n\tdefault:\n\t\tbreak;  //Do nothing\n\t}\n\n\t//Enable auto-refresh\n\n\t// 8192 Refreshes required every 64ms, so maximum refresh period is 7.8125 us\n\t// We have a 400 MHz DDR clock (2.5ns period) so max period is 3125 cycles\n\t// Our core now does 8 refreshes in a go, so we multiply this period by 8\n\n\trefresh = (64000 * mhz) / 8192; // Refresh period in clocks\n\n\treg_tmp = *(volatile UINT *) C_DDR_CFG_REG;      // read\n#ifdef BURST_REFRESH_ENABLE\n\treg_tmp |= C_CFG_REFRESH_ENABLE | (refresh * 8);\n\treg_tmp |= C_CFG_BURST_REFRESH_ENABLE;\n#else\n\treg_tmp |= C_CFG_REFRESH_ENABLE | (refresh * 1);\n\treg_tmp &= ~C_CFG_BURST_REFRESH_ENABLE;\n#endif\n\t*(volatile UINT *) C_DDR_CFG_REG = reg_tmp;\n\n\t//Verify register contents\n\treg_tmp = *(volatile UINT *) C_DDR_REG_PHY2;      // read\n\t//printf(\"Warning XXXXXXXXXXXXXXXXXXXXXX - get bad read data from C_DDR_PHY2_REG, though it looks OK on bus XXXXXXXXXXXXXXXXXX\");\n\t//TBD   Check_data (read_data,  dll_reg, \"Error: bad C_DDR_PHY2_REG read\", tb_pass);\n\treg_tmp = *(volatile UINT *) C_DDR_CFG_REG;      // read\n\t//TBD   Check_data (read_data,  cfg_reg, \"Error: bad DDR_CFG read\", tb_pass);\n\n\t//disable optimised wrapping\n\tif (ddr_config_parameters->ddr_mode == 2) {\n\t\treg_tmp = 0xFFFF0000;\n\t\t*(volatile UINT *) C_DDR_REG_IGNORE = reg_tmp;\n\t}\n\n\t//enable midbuffer followon\n\treg_tmp = *(volatile UINT *) C_DDR_ARB_REG;      // read\n\treg_tmp = 0xFFFF0000 | reg_tmp;\n\t*(volatile UINT *) C_DDR_ARB_REG = reg_tmp;\n\n\t// Enable write behind coherency checking for all clients\n\n\treg_tmp = 0xFFFF0000;\n\t*(volatile UINT *) C_DDR_AHB4_REG = reg_tmp;\n\n\t//Wait for 200 clock cycles for SDRAM DLL to lock...\n\tudelay(1);   //1us\n}\n\n// Function used to Setup DDR core\n\nvoid ddr_setup(int mhz)\n{\n\tstatic const T_DDR_TIMING_PARAMETERS *ddr_timing_parameters =\n\t\t&C_TP_DDR2_25_CL6_1GB;\n\tstatic const T_DDR_CONFIG_PARAMETERS *ddr_config_parameters =\n\t\t&C_CP_DDR2_25_CL6;\n\n\t//Bring core out of Reset\n\t*(volatile UINT *) C_DDR_BLKEN_REG = C_BLKEN_DDR_ON;\n\n\t//DDR TIMING INITIALISTION\n\tddr_timing_initialisation(ddr_timing_parameters);\n\n\t//DDR NORMAL INITIALISATION\n\tddr_normal_initialisation(ddr_config_parameters, mhz);\n\n\t// route all writes through one client\n\t*(volatile UINT *) C_DDR_TRANSACTION_ROUTING = (0\n\t\t<< DDR_ROUTE_CPU0_INSTR_SHIFT)\n\t\t| (1 << DDR_ROUTE_CPU0_RDDATA_SHIFT)\n\t\t| (3 << DDR_ROUTE_CPU0_WRDATA_SHIFT)\n\t\t| (2 << DDR_ROUTE_CPU1_INSTR_SHIFT)\n\t\t| (3 << DDR_ROUTE_CPU1_RDDATA_SHIFT)\n\t\t| (3 << DDR_ROUTE_CPU1_WRDATA_SHIFT);\n\n\t//Bring all clients out of reset\n\t*(volatile UINT *) C_DDR_BLKEN_REG = C_BLKEN_DDR_ON + 0x0000FFFF;\n\n}\n\nvoid set_ddr_timing(unsigned int w, unsigned int i)\n{\n\tunsigned int reg;\n\tunsigned int wnow = 16;\n\tunsigned int inow = 32;\n\n\t/* reset all timing controls to known value (31) */\n\twritel(DDR_PHY_TIMING_W_RST | DDR_PHY_TIMING_I_RST, DDR_PHY_TIMING);\n\twritel(DDR_PHY_TIMING_W_RST | DDR_PHY_TIMING_I_RST | DDR_PHY_TIMING_CK,\n\t       DDR_PHY_TIMING);\n\twritel(DDR_PHY_TIMING_W_RST | DDR_PHY_TIMING_I_RST, DDR_PHY_TIMING);\n\n\t/* step up or down read delay to the requested value */\n\twhile (wnow != w) {\n\t\tif (wnow < w) {\n\t\t\treg = DDR_PHY_TIMING_INC;\n\t\t\twnow++;\n\t\t} else {\n\t\t\treg = 0;\n\t\t\twnow--;\n\t\t}\n\t\twritel(DDR_PHY_TIMING_W_CE | reg, DDR_PHY_TIMING);\n\t\twritel(DDR_PHY_TIMING_CK | DDR_PHY_TIMING_W_CE | reg,\n\t\t       DDR_PHY_TIMING);\n\t\twritel(DDR_PHY_TIMING_W_CE | reg, DDR_PHY_TIMING);\n\t}\n\n\t/* now write delay */\n\twhile (inow != i) {\n\t\tif (inow < i) {\n\t\t\treg = DDR_PHY_TIMING_INC;\n\t\t\tinow++;\n\t\t} else {\n\t\t\treg = 0;\n\t\t\tinow--;\n\t\t}\n\t\twritel(DDR_PHY_TIMING_I_CE | reg, DDR_PHY_TIMING);\n\t\twritel(DDR_PHY_TIMING_CK | DDR_PHY_TIMING_I_CE | reg,\n\t\t       DDR_PHY_TIMING);\n\t\twritel(DDR_PHY_TIMING_I_CE | reg, DDR_PHY_TIMING);\n\t}\n}\n\n//Function used to Setup SDRAM in DDR/SDR mode\nvoid init_ddr(int mhz)\n{\n\t/* start clocks */\n\tenable_clock(SYS_CTRL_CLK_DDRPHY);\n\tenable_clock(SYS_CTRL_CLK_DDR);\n\tenable_clock(SYS_CTRL_CLK_DDRCK);\n\n\t/* bring phy and core out of reset */\n\treset_block(SYS_CTRL_RST_DDR_PHY, 0);\n\treset_block(SYS_CTRL_RST_DDR, 0);\n\n\t/* DDR runs at half the speed of the CPU */\n\tddr_setup(mhz >> 1);\n\treturn;\n}\n"
  },
  {
    "path": "package/boot/uboot-oxnas/src/board/ox820/ddr.h",
    "content": "/*******************************************************************\n*\n* File:\t\t\tddr_oxsemi.h\n*\n* Description:\t\tDeclarations for DDR routines and data objects\n*\n* Author:\t\tJulien Margetts\n*\n* Copyright:\t\tOxford Semiconductor Ltd, 2009\n*/\n\nvoid ddr_oxsemi_setup(int mhz);\n\n/* define to refresh in bursts of 8 */\n#define BURST_REFRESH_ENABLE\n\n#define DDR_BASE\t\t\t0x44700000\n\n#define C_DDR_CFG_REG\t\t\t(DDR_BASE + 0x00)\n#define C_CFG_DDR\t\t\t0x80000000\n#define C_CFG_SDR\t\t\t0x00000000\n#define C_CFG_WIDTH8\t\t\t0x00200000\n#define C_CFG_WIDTH16\t\t\t0x00100000\n#define C_CFG_WIDTH32\t\t\t0x00000000\n#define C_CFG_SIZE_FACTOR\t\t0x00020000\n#define C_CFG_REFRESH_ENABLE\t\t0x00010000\n#define C_CFG_BURST_REFRESH_ENABLE\t0x01000000\n#define C_CFG_SIZE(x)\t\t\t(x << 17)\n#define CFG_SIZE_2MB\t\t\t1\n#define CFG_SIZE_4MB\t\t\t2\n#define CFG_SIZE_8MB\t\t\t3\n#define CFG_SIZE_16MB\t\t\t4\n#define CFG_SIZE_32MB\t\t\t5\n#define CFG_SIZE_64MB\t\t\t6\n#define CFG_SIZE_128MB\t\t\t7\n\n#define C_DDR_BLKEN_REG\t\t\t(DDR_BASE + 0x04)\n#define C_BLKEN_DDR_ON\t\t\t0x80000000\n\n#define C_DDR_STAT_REG\t\t\t(DDR_BASE + 0x08)\n\n#define C_DDR_CMD_REG\t\t\t(DDR_BASE + 0x0C)\n#define C_CMD_SEND_COMMAND\t\t(1UL << 31) | (1 << 21) // RAS/CAS/WE/CS all low(active), CKE High, indicates\n#define C_CMD_WAKE_UP\t\t\t0x80FC0000 // Asserts CKE\n#define C_CMD_MODE_SDR\t\t\t0x80200022 // Sets CL=2 BL=4\n#define C_CMD_MODE_DDR\t\t\t0x80200063 // Sets CL=2.5 BL=8\n#define C_CMD_RESET_DLL\t\t\t0x00000100 // A8=1 Use in conjunction with C_CMD_MODE_DDR\n#define C_CMD_PRECHARGE_ALL\t\t0x80280400\n#define C_CMD_AUTO_REFRESH\t\t0x80240000\n#define C_CMD_SELF_REFRESH\t\t0x80040000 // As AUTO-REFRESH but with CKE low\n#define C_CMD_NOP\t\t\t0x803C0000 // NOP just to insert guaranteed delay\n#define C_CMD_DDR2_EMR1\t\t\t0x80210000 // Load extended mode register 1 with zeros (for init), CKE still set\n//#define C_CMD_DDR2_EMR1\t\t0x80210400 // Load extended mode register 1 with zeros (for init), CKE still set\n#define C_CMD_ENABLE_DLL\t\t0x00000000 // Values used in conjuction with C_CMD_DDR2_EMR1\n#define C_CMD_DISABLE_DLL\t\t0x00000001\n#define C_CMD_REDUCED_DRIVE\t\t0x00000002\n#define C_CMD_ODT_DISABLED\t\t0x00000000\n#define C_CMD_ODT_50\t\t\t0x00000044\n#define C_CMD_ODT_75\t\t\t0x00000004\n#define C_CMD_ODT_150\t\t\t0x00000040\n#define C_CMD_MODE_DDR2_OCD_DFLT\t0x00000380\n#define C_CMD_MODE_DDR2_OCD_EXIT\t0x00000000\n\n#define C_CMD_DDR2_EMR2\t\t\t0x80220000 // Load extended mode register 2 with zeros (for init), CKE still set\n#define C_CMD_DDR2_EMR3\t\t\t0x80230000 // Load extended mode register 3 with zeros (for init), CKE still set\n\n#define C_DDR_AHB_REG\t\t\t(DDR_BASE + 0x10)\n#define C_AHB_NO_RCACHES\t\t0xFFFF0000\n#define C_AHB_FLUSH_ALL_RCACHES\t\t0x0000FFFF\n#define C_AHB_FLUSH_AHB0_RCACHE\t\t0x00000001\n#define C_AHB_FLUSH_AHB1_RCACHE\t\t0x00000002\n\n#define C_DDR_DLL_REG\t\t\t(DDR_BASE + 0x14)\n#define C_DLL_DISABLED\t\t\t0x00000000\n#define C_DLL_MANUAL\t\t\t0x80000000\n#define C_DLL_AUTO_OFFSET\t\t0xA0000000\n#define C_DLL_AUTO_IN_REFRESH\t\t0xC0000000\n#define C_DLL_AUTOMATIC\t\t\t0xE0000000\n\n#define C_DDR_MON_REG\t\t\t(DDR_BASE + 0x18)\n#define C_MON_ALL\t\t\t0x00000010\n#define C_MON_CLIENT\t\t\t0x00000000\n\n#define C_DDR_DIAG_REG\t\t\t(DDR_BASE + 0x1C)\n#define C_DDR_DIAG2_REG\t\t\t(DDR_BASE + 0x20)\n\n#define C_DDR_IOC_REG\t\t\t(DDR_BASE + 0x24)\n#define C_DDR_IOC_PWR_DWN\t\t(1 << 10)\n#define C_DDR_IOC_SEL_SSTL\t\t(1 << 9)\n#define C_DDR_IOC_CK_DRIVE(x)\t\t((x) << 6)\n#define C_DDR_IOC_DQ_DRIVE(x)\t\t((x) << 3)\n#define C_DDR_IOC_XX_DRIVE(x)\t\t((x) << 0)\n\n#define C_DDR_ARB_REG\t\t\t(DDR_BASE + 0x28)\n#define C_DDR_ARB_MIDBUF\t\t(1 << 4)\n#define C_DDR_ARB_LRUBANK\t\t(1 << 3)\n#define C_DDR_ARB_REQAGE\t\t(1 << 2)\n#define C_DDR_ARB_DATDIR\t\t(1 << 1)\n#define C_DDR_ARB_DATDIR_NC\t\t(1 << 0)\n\n#define C_TOP_ADDRESS_BIT_TEST\t\t22\n#define C_MEM_BASE\t\t\tC_SDRAM_BASE\n\n#define C_MEM_TEST_BASE\t\t\t0\n#define C_MEM_TEST_LEN\t\t\t1920\n#define C_MAX_RAND_ACCESS_LEN\t\t16\n\n#define C_DDR_REG_IGNORE\t\t(DDR_BASE + 0x2C)\n#define C_DDR_AHB4_REG\t\t\t(DDR_BASE + 0x44)\n\n#define C_DDR_REG_TIMING0\t\t(DDR_BASE + 0x34)\n#define C_DDR_REG_TIMING1\t\t(DDR_BASE + 0x38)\n#define C_DDR_REG_TIMING2\t\t(DDR_BASE + 0x3C)\n\n#define C_DDR_REG_PHY0\t\t\t(DDR_BASE + 0x48)\n#define C_DDR_REG_PHY1\t\t\t(DDR_BASE + 0x4C)\n#define C_DDR_REG_PHY2\t\t\t(DDR_BASE + 0x50)\n#define C_DDR_REG_PHY3\t\t\t(DDR_BASE + 0x54)\n\n#define C_DDR_REG_GENERIC\t\t(DDR_BASE + 0x60)\n\n#define C_OXSEMI_DDRC_SIGNATURE\t\t0x054415AA\n\n#define DDR_PHY_BASE\t\t\t(DDR_BASE + 0x80000)\n#define DDR_PHY_TIMING\t\t\t(DDR_PHY_BASE + 0x48)\n#define DDR_PHY_TIMING_CK\t\t(1 << 12)\n#define DDR_PHY_TIMING_INC\t\t(1 << 13)\n#define DDR_PHY_TIMING_W_CE\t\t(1 << 14)\n#define DDR_PHY_TIMING_W_RST\t\t(1 << 15)\n#define DDR_PHY_TIMING_I_CE\t\t(1 << 16)\n#define DDR_PHY_TIMING_I_RST\t\t(1 << 17)\n\n#define C_DDR_REG_PHY_TIMING\t\t(DDR_PHY_BASE + 0x50)\n#define C_DDR_REG_PHY_WR_RATIO\t\t(DDR_PHY_BASE + 0x74)\n#define C_DDR_REG_PHY_RD_RATIO\t\t(DDR_PHY_BASE + 0x78)\n\n#define C_DDR_TRANSACTION_ROUTING\t(DDR_PHY_BASE + 0xC8)\n#define DDR_ROUTE_CPU0_INSTR_SHIFT\t0\n#define DDR_ROUTE_CPU0_RDDATA_SHIFT\t4\n#define DDR_ROUTE_CPU0_WRDATA_SHIFT\t6\n#define DDR_ROUTE_CPU1_INSTR_SHIFT\t8\n#define DDR_ROUTE_CPU1_RDDATA_SHIFT\t12\n#define DDR_ROUTE_CPU1_WRDATA_SHIFT\t14\n\nunsigned int ddrc_signature(void);\nvoid set_ddr_timing(unsigned int w, unsigned int i);\nint pause(unsigned int us);\nvoid set_ddr_sel(int val);\n"
  },
  {
    "path": "package/boot/uboot-oxnas/src/board/ox820/lowlevel_init.S",
    "content": "#include <config.h>\n#ifndef CONFIG_SPL_BUILD\n\n.globl lowlevel_init\nlowlevel_init:\n\t/*\n\t * Copy exception table to relocated address in internal SRAM\n\t */\n\tldr\tr0, src\t\t/* Address of exception table in flash */\n\tldr\tr1, dest\t/* Relocated address of exception table */\n\tldmia\tr0!, {r3-r10}\t/* Copy exception table and jump values from */\n\tstmia\tr1!, {r3-r10}\t/* FLASH to relocated address */\n\tldmia\tr0!, {r3-r10}\n\tstmia\tr1!, {r3-r10}\n\tmov\tpc, lr\n\nsrc:\t.word CONFIG_SYS_TEXT_BASE\ndest:\t.word CONFIG_SRAM_BASE\n\n#endif"
  },
  {
    "path": "package/boot/uboot-oxnas/src/board/ox820/ox820.c",
    "content": "#include <common.h>\n#include <spl.h>\n#include <phy.h>\n#include <netdev.h>\n#include <ide.h>\n#include <nand.h>\n#include <asm/arch/spl.h>\n#include <asm/arch/pinmux.h>\n#include <asm/arch/clock.h>\n#include <asm/arch/sysctl.h>\n\nDECLARE_GLOBAL_DATA_PTR;\n\n#ifdef CONFIG_SPL_BUILD\n\n#ifdef DEBUG\n#define DILIGENCE (1048576/4)\nstatic int test_memory(u32 memory)\n{\n\tvolatile u32 *read;\n\tvolatile u32 *write;\n\tconst u32 INIT_PATTERN = 0xAA55AA55;\n\tconst u32 INC_PATTERN = 0x01030507;\n\tu32 pattern;\n\tint check;\n\tint i;\n\n\tcheck = 0;\n\tread = write = (volatile u32 *) memory;\n\tpattern = INIT_PATTERN;\n\tfor (i = 0; i < DILIGENCE; i++) {\n\t\t*write++ = pattern;\n\t\tpattern += INC_PATTERN;\n\t}\n\tputs(\"testing\\n\");\n\tpattern = INIT_PATTERN;\n\tfor (i = 0; i < DILIGENCE; i++) {\n\t\tcheck += (pattern == *read++) ? 1 : 0;\n\t\tpattern += INC_PATTERN;\n\t}\n\treturn (check == DILIGENCE) ? 0 : -1;\n}\n#endif\n\nvoid uart_init(void)\n{\n\t/* Reset UART1 */\n\treset_block(SYS_CTRL_RST_UART1, 1);\n\tudelay(100);\n\treset_block(SYS_CTRL_RST_UART1, 0);\n\tudelay(100);\n\n\t/* Setup pin mux'ing for UART1 */\n\tpinmux_set(PINMUX_BANK_MFA, 30, PINMUX_UARTA_SIN);\n\tpinmux_set(PINMUX_BANK_MFA, 31, PINMUX_UARTA_SOUT);\n}\n\nextern void init_ddr(int mhz);\n\nvoid board_inithw(void)\n{\n\tint plla_freq;\n#ifdef DEBUG\n\tint i;\n#endif\t/* DEBUG */\n\n\ttimer_init();\n\tuart_init();\n\tpreloader_console_init();\n\n\tplla_freq = plla_set_config(CONFIG_PLLA_FREQ_MHZ);\n\tinit_ddr(plla_freq);\n\n#ifdef DEBUG\n\tif(test_memory(CONFIG_SYS_SDRAM_BASE)) {\n\t\tputs(\"memory test failed\\n\");\n\t} else {\n\t\tputs(\"memory test done\\n\");\n\t}\n#endif /* DEBUG */\n#ifdef CONFIG_SPL_BSS_DRAM_START\n\textern char __bss_dram_start[];\n\textern char __bss_dram_end[];\n\tmemset(&__bss_dram_start, 0, __bss_dram_end - __bss_dram_start);\n#endif\n}\n\nvoid board_init_f(ulong dummy)\n{\n\t/* Set the stack pointer. */\n\tasm volatile(\"mov sp, %0\\n\" : : \"r\"(CONFIG_SPL_STACK));\n\n\t/* Clear the BSS. */\n\tmemset(__bss_start, 0, __bss_end - __bss_start);\n\n\t/* Set global data pointer. */\n\tgd = &gdata;\n\n\tboard_inithw();\n\n\tboard_init_r(NULL, 0);\n}\n\nu32 spl_boot_device(void)\n{\n\treturn CONFIG_SPL_BOOT_DEVICE;\n}\n\n#ifdef CONFIG_SPL_BLOCK_SUPPORT\nvoid spl_block_device_init(void)\n{\n\tide_init();\n}\n#endif\n\n#ifdef CONFIG_SPL_OS_BOOT\nint spl_start_uboot(void)\n{\n        /* break into full u-boot on 'c' */\n        return (serial_tstc() && serial_getc() == 'c');\n}\n#endif\n\nvoid spl_display_print(void)\n{\n\t/* print a hint, so that we will not use the wrong SPL by mistake */\n\tputs(\"  Boot device: \" BOOT_DEVICE_TYPE \"\\n\" );\n}\n\nvoid lowlevel_init(void)\n{\n}\n\n#ifdef USE_DL_PREFIX\n/* quick and dirty memory allocation */\nstatic ulong next_mem = CONFIG_SPL_MALLOC_START;\n\nvoid *memalign(size_t alignment, size_t bytes)\n{\n\tulong mem = ALIGN(next_mem, alignment);\n\n\tnext_mem = mem + bytes;\n\n\tif (next_mem > CONFIG_SYS_SDRAM_BASE + CONFIG_MIN_SDRAM_SIZE) {\n\t\tprintf(\"spl: out of memory\\n\");\n\t\thang();\n\t}\n\n\treturn (void *)mem;\n}\n\nvoid free(void* mem)\n{\n}\n#endif\n\n#endif /* CONFIG_SPL_BUILD */\n\nint board_early_init_f(void)\n{\n\treturn 0;\n}\n\n#define STATIC_CTL_BANK0\t\t(STATIC_CONTROL_BASE + 4)\n#define STATIC_READ_CYCLE_SHIFT\t\t0\n#define STATIC_DELAYED_OE\t\t(1 << 7)\n#define STATIC_WRITE_CYCLE_SHIFT\t8\n#define STATIC_WRITE_PULSE_SHIFT\t16\n#define STATIC_WRITE_BURST_EN\t\t(1 << 23)\n#define STATIC_TURN_AROUND_SHIFT\t24\n#define STATIC_BUFFER_PRESENT\t\t(1 << 28)\n#define STATIC_READ_BURST_EN\t\t(1 << 29)\n#define STATIC_BUS_WIDTH8\t\t(0 << 30)\n#define STATIC_BUS_WIDTH16\t\t(1 << 30)\n#define STATIC_BUS_WIDTH32\t\t(2 << 30)\n\nvoid nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)\n{\n\tstruct nand_chip *this = mtd->priv;\n\tunsigned long nandaddr = (unsigned long) this->IO_ADDR_W;\n\n\tif (ctrl & NAND_CTRL_CHANGE) {\n\t\tnandaddr &= ~(BIT(NAND_ALE_ADDR_PIN) | BIT(NAND_CLE_ADDR_PIN));\n\t\tif (ctrl & NAND_CLE)\n\t\t\tnandaddr |= BIT(NAND_CLE_ADDR_PIN);\n\t\telse if (ctrl & NAND_ALE)\n\t\t\tnandaddr |= BIT(NAND_ALE_ADDR_PIN);\n\t\tthis->IO_ADDR_W = (void __iomem *) nandaddr;\n\t}\n\n\tif (cmd != NAND_CMD_NONE)\n\t\twriteb(cmd, (void __iomem *) nandaddr);\n}\n\n#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_BOOT_FROM_NAND)\n\nint nand_dev_ready(struct mtd_info *mtd)\n{\n\tstruct nand_chip *chip = mtd->priv;\n\n\tudelay(chip->chip_delay);\n\n\treturn 1;\n}\n\nvoid nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)\n{\n\tint i;\n\tstruct nand_chip *chip = mtd->priv;\n\n\tfor (i = 0; i < len; i++)\n\t\tbuf[i] = readb(chip->IO_ADDR_R);\n}\n\nvoid nand_dev_reset(struct nand_chip *chip)\n{\n\twriteb(NAND_CMD_RESET, chip->IO_ADDR_W + BIT(NAND_CLE_ADDR_PIN));\n\tudelay(chip->chip_delay);\n\twriteb(NAND_CMD_STATUS, chip->IO_ADDR_W + BIT(NAND_CLE_ADDR_PIN));\n\twhile (!(readb(chip->IO_ADDR_R) & NAND_STATUS_READY)) {\n\t\t;\n\t}\n}\n\n#else\n\n#define nand_dev_reset(chip)\t/* framework will reset the chip anyway */\n#define nand_read_buf\t\tNULL /* framework will provide a default one */\n#define nand_dev_ready\t\tNULL /* dev_ready is optional */\n\n#endif\n\nint board_nand_init(struct nand_chip *chip)\n{\n\t/* Block reset Static core */\n\treset_block(SYS_CTRL_RST_STATIC, 1);\n\treset_block(SYS_CTRL_RST_STATIC, 0);\n\n\t/* Enable clock to Static core */\n\tenable_clock(SYS_CTRL_CLK_STATIC);\n\n\t/* enable flash support on static bus.\n\t * Enable static bus onto GPIOs, only CS0 */\n\tpinmux_set(PINMUX_BANK_MFA, 12, PINMUX_STATIC_DATA0);\n\tpinmux_set(PINMUX_BANK_MFA, 13, PINMUX_STATIC_DATA1);\n\tpinmux_set(PINMUX_BANK_MFA, 14, PINMUX_STATIC_DATA2);\n\tpinmux_set(PINMUX_BANK_MFA, 15, PINMUX_STATIC_DATA3);\n\tpinmux_set(PINMUX_BANK_MFA, 16, PINMUX_STATIC_DATA4);\n\tpinmux_set(PINMUX_BANK_MFA, 17, PINMUX_STATIC_DATA5);\n\tpinmux_set(PINMUX_BANK_MFA, 18, PINMUX_STATIC_DATA6);\n\tpinmux_set(PINMUX_BANK_MFA, 19, PINMUX_STATIC_DATA7);\n\n\tpinmux_set(PINMUX_BANK_MFA, 20, PINMUX_STATIC_NWE);\n\tpinmux_set(PINMUX_BANK_MFA, 21, PINMUX_STATIC_NOE);\n\tpinmux_set(PINMUX_BANK_MFA, 22, PINMUX_STATIC_NCS);\n\tpinmux_set(PINMUX_BANK_MFA, 23, PINMUX_STATIC_ADDR18);\n\tpinmux_set(PINMUX_BANK_MFA, 24, PINMUX_STATIC_ADDR19);\n\n\t/* Setup the static bus CS0 to access FLASH */\n\n\twritel((0x3f << STATIC_READ_CYCLE_SHIFT)\n\t\t\t| (0x3f << STATIC_WRITE_CYCLE_SHIFT)\n\t\t\t| (0x1f << STATIC_WRITE_PULSE_SHIFT)\n\t\t\t| (0x03 << STATIC_TURN_AROUND_SHIFT) |\n\t\t\tSTATIC_BUS_WIDTH16,\n\t\tSTATIC_CTL_BANK0);\n\n\tchip->cmd_ctrl = nand_hwcontrol;\n\tchip->ecc.mode = NAND_ECC_SOFT;\n\tchip->chip_delay = 30;\n\tchip->dev_ready = nand_dev_ready;\n\tchip->read_buf = nand_read_buf;\n\n\tnand_dev_reset(chip);\n\n\treturn 0;\n}\n\nint board_init(void)\n{\n\tgd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;\n\tgd->bd->bi_arch_number = MACH_TYPE_OXNAS;\n\n\t/* assume uart is already initialized by SPL */\n\n#if defined(CONFIG_START_IDE)\n\tputs(\"IDE:   \");\n\tide_init();\n#endif\n\n\treturn 0;\n}\n\n/* copied from board/evb64260/sdram_init.c */\n/*\n * Check memory range for valid RAM. A simple memory test determines\n * the actually available RAM size between addresses `base' and\n * `base + maxsize'. Some (not all) hardware errors are detected:\n * - short between address lines\n * - short between data lines\n */\nstatic long int dram_size (long int *base, long int maxsize)\n{\n\tvolatile long int *addr, *b = base;\n\tlong int cnt, val, save1, save2;\n\n#define STARTVAL (CONFIG_MIN_SDRAM_SIZE / 2)\t/* start test at half size */\n\tfor (cnt = STARTVAL / sizeof (long); cnt < maxsize / sizeof (long);\n\t     cnt <<= 1) {\n\t\taddr = base + cnt;\t/* pointer arith! */\n\n\t\tsave1 = *addr;\t/* save contents of addr */\n\t\tsave2 = *b;\t/* save contents of base */\n\n\t\t*addr = cnt;\t/* write cnt to addr */\n\t\t*b = 0;\t\t/* put null at base */\n\n\t\t/* check at base address */\n\t\tif ((*b) != 0) {\n\t\t\t*addr = save1;\t/* restore *addr */\n\t\t\t*b = save2;\t/* restore *b */\n\t\t\treturn (0);\n\t\t}\n\t\tval = *addr;\t/* read *addr */\n\n\t\t*addr = save1;\n\t\t*b = save2;\n\n\t\tif (val != cnt) {\n\t\t\t/* fix boundary condition.. STARTVAL means zero */\n\t\t\tif (cnt == STARTVAL / sizeof (long))\n\t\t\t\tcnt = 0;\n\t\t\treturn (cnt * sizeof (long));\n\t\t}\n\t}\n\treturn maxsize;\n}\n\nint dram_init(void)\n{\n\tgd->ram_size = dram_size((long int *)CONFIG_SYS_SDRAM_BASE,\n\t\t\t\t\tCONFIG_MAX_SDRAM_SIZE);\n\treturn 0;\n}\n\nint board_eth_init(bd_t *bis)\n{\n\tu32 value;\n\n\t/* set the pin multiplexers to enable talking to Ethernent Phys */\n\tpinmux_set(PINMUX_BANK_MFA, 3, PINMUX_MACA_MDC);\n\tpinmux_set(PINMUX_BANK_MFA, 4, PINMUX_MACA_MDIO);\n\n\t// Ensure the MAC block is properly reset\n\treset_block(SYS_CTRL_RST_MAC, 1);\n\tudelay(10);\n\treset_block(SYS_CTRL_RST_MAC, 0);\n\n\t// Enable the clock to the MAC block\n\tenable_clock(SYS_CTRL_CLK_MAC);\n\n\tvalue = readl(SYS_CTRL_GMAC_CTRL);\n\t/* Use simple mux for 25/125 Mhz clock switching */\n\tvalue |= BIT(SYS_CTRL_GMAC_SIMPLE_MUX);\n\t/* Enable GMII_GTXCLK to follow GMII_REFCLK - required for gigabit PHY */\n\tvalue |= BIT(SYS_CTRL_GMAC_CKEN_GTX);\n\t/* set auto tx speed */\n\tvalue |= BIT(SYS_CTRL_GMAC_AUTOSPEED);\n\n\twritel(value, SYS_CTRL_GMAC_CTRL);\n\n\treturn designware_initialize(MAC_BASE, PHY_INTERFACE_MODE_RGMII);\n}\n\n"
  },
  {
    "path": "package/boot/uboot-oxnas/src/board/ox820/spl_start.S",
    "content": ".section .init\n.globl _spl_start\n_spl_start:\n\tb\t_start\n\tb\t_start+0x4\n\tb\t_start+0x8\n\tb\t_start+0xc\n\tb\t_start+0x10\n\tb\t_start+0x14\n\tb\t_start+0x18\n\tb\t_start+0x1c\n\t.space\t0x30 - (. - _spl_start)\n\t.ascii\t\"BOOT\"\t\t/* 0x30 signature*/\n\t.word\t0x50\t\t/* 0x34 header size itself */\n\t.word\t0\t\t/* 0x38 */\n\t.word\t0x5000f000\t/* boot report location */\n\t.word\t_start\t\t/* 0x40 */\n\nmain_crc_size:\t.word\tcode_size\t/* 0x44 filled by linker */\nmain_crc:\t.word\t0\t\t/* 0x48 fill later */\nheader_crc:\t.word\t0\t\t/* 0x4C header crc*/\n"
  },
  {
    "path": "package/boot/uboot-oxnas/src/board/ox820/u-boot-spl.lds",
    "content": "/*\n * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>\n * on behalf of DENX Software Engineering GmbH\n *\n * January 2004 - Changed to support H4 device\n * Copyright (c) 2004-2008 Texas Instruments\n *\n * (C) Copyright 2002\n * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>\n *\n * See file CREDITS for list of people who contributed to this\n * project.\n *\n * This program is free software; you can redistribute it and/or\n * modify it under the terms of the GNU General Public License as\n * published by the Free Software Foundation; either version 2 of\n * the License, or (at your option) any later version.\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n * GNU General Public License for more details.\n *\n * You should have received a copy of the GNU General Public License\n * along with this program; if not, write to the Free Software\n * Foundation, Inc., 59 Temple Place, Suite 330, Boston,\n * MA 02111-1307 USA\n */\n\nMEMORY\n{\n\t sram (rwx) : ORIGIN = CONFIG_SPL_TEXT_BASE, LENGTH = CONFIG_SPL_MAX_SIZE\n\t dram : ORIGIN = CONFIG_SPL_BSS_DRAM_START, LENGTH = CONFIG_SPL_BSS_DRAM_SIZE\n}\n\nOUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-littlearm\", \"elf32-littlearm\")\nOUTPUT_ARCH(arm)\nENTRY(_spl_start)\nSECTIONS\n{\n\t.text.0\t:\n\t{\n\t\t*(.init*)\n\t}\n\n\n\t/* Start of the rest of the SPL */\n\tcode_start = . ;\n\n\t.text.1\t:\n\t{\n\t\t*(.text*)\n\t}\n\n\t. = ALIGN(4);\n\t.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }\n\n\t. = ALIGN(4);\n\t.data : {\n\t\t*(.data*)\n\t}\n\n\t. = ALIGN(4);\n\n\t__image_copy_end = .;\n\tcode_size = . - code_start;\n\n\t.rel.dyn : {\n\t\t__rel_dyn_start = .;\n\t\t*(.rel*)\n\t\t__rel_dyn_end = .;\n\t}\n\n\t. = ALIGN(0x800);\n\n\t_end = .;\n\n\t.bss.sram __rel_dyn_start (OVERLAY) : {\n\t\t__bss_start = .;\n\t\t*(.bss.stdio_devices)\n\t\t*(.bss.serial_current)\n\t\t . = ALIGN(4);\n\t\t__bss_end = .;\n\t}\n\n\t.bss : {\n\t\t__bss_dram_start = .;\n\t\t*(.bss*)\n\t\t__bss_dram_end = .;\n\t} > dram\n\n\t/DISCARD/ : { *(.bss*) }\n\t/DISCARD/ : { *(.dynsym) }\n\t/DISCARD/ : { *(.dynstr*) }\n\t/DISCARD/ : { *(.dynsym*) }\n\t/DISCARD/ : { *(.dynamic*) }\n\t/DISCARD/ : { *(.hash*) }\n\t/DISCARD/ : { *(.plt*) }\n\t/DISCARD/ : { *(.interp*) }\n\t/DISCARD/ : { *(.gnu*) }\n}\n"
  },
  {
    "path": "package/boot/uboot-oxnas/src/common/env_ext4.c",
    "content": "/*\n * (c) Copyright 2011 by Tigris Elektronik GmbH\n *\n * Author:\n *  Maximilian Schwerin <mvs@tigris.de>\n *\n * SPDX-License-Identifier:\tGPL-2.0+\n */\n\n#include <common.h>\n\n#include <command.h>\n#include <environment.h>\n#include <linux/stddef.h>\n#include <malloc.h>\n#include <search.h>\n#include <errno.h>\n#include <ext4fs.h>\n\nchar *env_name_spec = \"EXT4\";\n\nenv_t *env_ptr;\n\nDECLARE_GLOBAL_DATA_PTR;\n\nint env_init(void)\n{\n\t/* use default */\n\tgd->env_addr = (ulong)&default_environment[0];\n\tgd->env_valid = 1;\n\n\treturn 0;\n}\n\n#ifdef CONFIG_CMD_SAVEENV\nint saveenv(void)\n{\n\tenv_t\tenv_new;\n\tssize_t\tlen;\n\tchar\t*res;\n\tblock_dev_desc_t *dev_desc = NULL;\n\tint dev = EXT4_ENV_DEVICE;\n\tint part = EXT4_ENV_PART;\n\tint err;\n\n\tres = (char *)&env_new.data;\n\tlen = hexport_r(&env_htab, '\\0', 0, &res, ENV_SIZE, 0, NULL);\n\tif (len < 0) {\n\t\terror(\"Cannot export environment: errno = %d\\n\", errno);\n\t\treturn 1;\n\t}\n\n\tdev_desc = get_dev(EXT4_ENV_INTERFACE, dev);\n\tif (dev_desc == NULL) {\n\t\tprintf(\"Failed to find %s%d\\n\",\n\t\t\tEXT4_ENV_INTERFACE, dev);\n\t\treturn 1;\n\t}\n\n\terr = ext4_register_device(dev_desc, part);\n\tif (err) {\n\t\tprintf(\"Failed to register %s%d:%d\\n\",\n\t\t\tEXT4_ENV_INTERFACE, dev, part);\n\t\treturn 1;\n\t}\n\n\tenv_new.crc = crc32(0, env_new.data, ENV_SIZE);\n\terr = ext4fs_write(EXT4_ENV_FILE, (void *)&env_new, sizeof(env_t));\n\text4fs_close();\n\tif (err == -1) {\n\t\tprintf(\"\\n** Unable to write \\\"%s\\\" from %s%d:%d **\\n\",\n\t\t\tEXT4_ENV_FILE, EXT4_ENV_INTERFACE, dev, part);\n\t\treturn 1;\n\t}\n\n\tputs(\"done\\n\");\n\treturn 0;\n}\n#endif /* CONFIG_CMD_SAVEENV */\n\nvoid env_relocate_spec(void)\n{\n\tchar buf[CONFIG_ENV_SIZE];\n\tblock_dev_desc_t *dev_desc = NULL;\n\tint dev = EXT4_ENV_DEVICE;\n\tint part = EXT4_ENV_PART;\n\tint err;\n\n\tdev_desc = get_dev(EXT4_ENV_INTERFACE, dev);\n\tif (dev_desc == NULL) {\n\t\tprintf(\"Failed to find %s%d\\n\",\n\t\t\tEXT4_ENV_INTERFACE, dev);\n\t\tset_default_env(NULL);\n\t\treturn;\n\t}\n\n\terr = ext4_register_device(dev_desc, part);\n\tif (err) {\n\t\tprintf(\"Failed to register %s%d:%d\\n\",\n\t\t\tEXT4_ENV_INTERFACE, dev, part);\n\t\tset_default_env(NULL);\n\t\treturn;\n\t}\n\n\terr = ext4_read_file(EXT4_ENV_FILE, (uchar *)&buf, 0, CONFIG_ENV_SIZE);\n\text4fs_close();\n\n\tif (err == -1) {\n\t\tprintf(\"\\n** Unable to read \\\"%s\\\" from %s%d:%d **\\n\",\n\t\t\tEXT4_ENV_FILE, EXT4_ENV_INTERFACE, dev, part);\n\t\tset_default_env(NULL);\n\t\treturn;\n\t}\n\n\tenv_import(buf, 1);\n}\n"
  },
  {
    "path": "package/boot/uboot-oxnas/src/common/spl/spl_block.c",
    "content": "/*\n * (C) Copyright 2013\n *\n * Ma Haijun <mahaijuns@gmail.com>\n *\n * See file CREDITS for list of people who contributed to this\n * project.\n *\n * This program is free software; you can redistribute it and/or\n * modify it under the terms of the GNU General Public License as\n * published by the Free Software Foundation; either version 2 of\n * the License, or (at your option) any later version.\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n * GNU General Public License for more details.\n *\n * You should have received a copy of the GNU General Public License\n * along with this program; if not, write to the Free Software\n * Foundation, Inc., 59 Temple Place, Suite 330, Boston,\n * MA 02111-1307 USA\n */\n#include <common.h>\n#include <spl.h>\n#include <asm/u-boot.h>\n#include <asm/utils.h>\n#include <version.h>\n#include <part.h>\n#include <fat.h>\n#include <ext4fs.h>\n\n/* should be implemented by board */\nextern void spl_block_device_init(void);\n\nblock_dev_desc_t * spl_get_block_device(void)\n{\n\tblock_dev_desc_t * device;\n\n\tspl_block_device_init();\n\n\tdevice = get_dev(CONFIG_SPL_BLOCKDEV_INTERFACE, CONFIG_SPL_BLOCKDEV_ID);\n\tif (!device) {\n\t\tprintf(\"blk device %s%d not exists\\n\",\n\t\t\tCONFIG_SPL_BLOCKDEV_INTERFACE,\n\t\t\tCONFIG_SPL_BLOCKDEV_ID);\n\t\thang();\n\t}\n\n\treturn device;\n}\n\n#ifdef CONFIG_SPL_FAT_SUPPORT\nstatic int block_load_image_fat(const char *filename)\n{\n\tint err;\n\tstruct image_header *header;\n\n\theader = (struct image_header *)(CONFIG_SYS_TEXT_BASE -\n\t\t\t\t\t\tsizeof(struct image_header));\n\n\terr = file_fat_read(filename, header, sizeof(struct image_header));\n\tif (err <= 0)\n\t\tgoto end;\n\n\tspl_parse_image_header(header);\n\n\terr = file_fat_read(filename, (u8 *)spl_image.load_addr, 0);\n\nend:\n\tif (err <= 0)\n\t\tprintf(\"spl: error reading image %s, err - %d\\n\",\n\t\t       filename, err);\n\n\treturn (err <= 0);\n}\n\n#ifdef CONFIG_SPL_OS_BOOT\nstatic int block_load_image_fat_os(void)\n{\n\tint err;\n\n\terr = file_fat_read(CONFIG_SPL_FAT_LOAD_ARGS_NAME,\n\t\t\t    (void *)CONFIG_SYS_SPL_ARGS_ADDR, 0);\n\tif (err <= 0) {\n\t\treturn -1;\n\t}\n\n\treturn block_load_image_fat(CONFIG_SPL_FAT_LOAD_KERNEL_NAME);\n}\n#endif\n\nvoid spl_block_load_image(void)\n{\n\tint err;\n\tblock_dev_desc_t * device;\n\n\tdevice = spl_get_block_device();\n\terr = fat_register_device(device, CONFIG_BLOCKDEV_FAT_BOOT_PARTITION);\n\tif (err) {\n\t\tprintf(\"spl: fat register err - %d\\n\", err);\n\t\thang();\n\t}\n#ifdef CONFIG_SPL_OS_BOOT\n\tif (spl_start_uboot() || block_load_image_fat_os())\n#endif\n\t{\n\t\terr = block_load_image_fat(CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME);\n\t\tif (err)\n\t\t\thang();\n\t}\n}\n#elif defined(CONFIG_SPL_EXT4_SUPPORT) /* end CONFIG_SPL_FAT_SUPPORT */\nstatic int block_load_image_ext4(const char *filename)\n{\n\tint err;\n\tstruct image_header *header;\n\n\theader = (struct image_header *)(CONFIG_SYS_TEXT_BASE -\n\t\t\t\t\t\tsizeof(struct image_header));\n\n\terr = ext4_read_file(filename, header, 0, sizeof(struct image_header));\n\tif (err <= 0)\n\t\tgoto end;\n\n\tspl_parse_image_header(header);\n\n\terr = ext4_read_file(filename, (u8 *)spl_image.load_addr, 0, 0);\n\nend:\n\treturn (err <= 0);\n}\n\n#ifdef CONFIG_SPL_OS_BOOT\nstatic int block_load_image_ext4_os(void)\n{\n\tint err;\n\n\terr = ext4_read_file(CONFIG_SPL_EXT4_LOAD_ARGS_NAME,\n\t\t\t    (void *)CONFIG_SYS_SPL_ARGS_ADDR, 0, 0);\n\tif (err <= 0) {\n\t\treturn -1;\n\t}\n\n\treturn block_load_image_ext4(CONFIG_SPL_EXT4_LOAD_KERNEL_NAME);\n}\n#endif\n\nvoid spl_block_load_image(void)\n{\n\tint err;\n\tblock_dev_desc_t * device;\n\n\tdevice = spl_get_block_device();\n\terr = ext4_register_device(device, CONFIG_BLOCKDEV_EXT4_BOOT_PARTITION);\n\tif (err) {\n\t\thang();\n\t}\n#ifdef CONFIG_SPL_OS_BOOT\n\tif (spl_start_uboot() || block_load_image_ext4_os())\n#endif\n\t{\n\t\terr = block_load_image_ext4(CONFIG_SPL_EXT4_LOAD_PAYLOAD_NAME);\n\t\tif (err)\n\t\t\thang();\n\t}\n}\n#else /* end CONFIG_SPL_EXT4_SUPPORT */\nstatic int block_load_image_raw(block_dev_desc_t * device, lbaint_t sector)\n{\n\tint n;\n\tu32 image_size_sectors;\n\tstruct image_header *header;\n\n\theader = (struct image_header *)(CONFIG_SYS_TEXT_BASE -\n\t\t\t\t\t\tsizeof(struct image_header));\n\n\t/* read image header to find the image size & load address */\n\tn = device->block_read(device->dev, sector, 1, header);\n\n\tif (n != 1) {\n\t\tprintf(\"spl: blk read err\\n\");\n\t\treturn 1;\n\t}\n\n\tspl_parse_image_header(header);\n\n\t/* convert size to sectors - round up */\n\timage_size_sectors = (spl_image.size + 512 - 1) / 512;\n\tn = device->block_read(device->dev, sector, image_size_sectors,\n\t\t\t\t\t(void *)spl_image.load_addr);\n\n\tif (n != image_size_sectors) {\n\t\tprintf(\"spl: blk read err\\n\");\n\t\treturn 1;\n\t}\n\treturn 0;\n}\n\n#ifdef CONFIG_SPL_OS_BOOT\nstatic int block_load_image_raw_os(block_dev_desc_t * device)\n{\n\tint n;\n\n\tn = device->block_read(device->dev, CONFIG_SYS_BLOCK_RAW_MODE_ARGS_SECTOR,\n\t\t\t\t\tCONFIG_SYS_BLOCK_RAW_MODE_ARGS_SECTORS,\n\t\t\t\t\t(u32 *)CONFIG_SYS_SPL_ARGS_ADDR);\n\t/* flush cache after read */\n\tflush_cache(addr, CONFIG_SYS_BLOCK_RAW_MODE_ARGS_SECTORS * 512);\n\n\tif (n != CONFIG_SYS_BLOCK_RAW_MODE_ARGS_SECTORS) {\n\t\tprintf(\"args blk read error\\n\");\n\t\treturn -1;\n\t}\n\n\treturn block_load_image_raw(device, CONFIG_SYS_BLOCK_RAW_MODE_KERNEL_SECTOR);\n}\n#endif\n\nvoid spl_block_load_image(void)\n{\n\tint err;\n\tblock_dev_desc_t * device;\n\n\tdevice = spl_get_block_device();\n#ifdef CONFIG_SPL_OS_BOOT\n\tif (spl_start_uboot() || block_load_image_raw_os(device))\n#endif\n\t{\n\t\terr = block_load_image_raw(device,\n\t\t\t\t\t CONFIG_SYS_BLOCK_RAW_MODE_U_BOOT_SECTOR);\n\t\tif (err)\n\t\t\thang();\n\t}\n}\n#endif /* CONFIG_SPL_FAT_SUPPORT */\n"
  },
  {
    "path": "package/boot/uboot-oxnas/src/configs/ox820_defconfig",
    "content": "CONFIG_ARM=y\nCONFIG_OX820=y\nCONFIG_TARGET_OX820=y\n"
  },
  {
    "path": "package/boot/uboot-oxnas/src/drivers/block/plxsata_ide.c",
    "content": "/*\n * (C) Copyright 2005\n * Oxford Semiconductor Ltd\n *\n * See file CREDITS for list of people who contributed to this\n * project.\n *\n * This program is free software; you can redistribute it and/or\n * modify it under the terms of the GNU General Public License as\n * published by the Free Software Foundation; either version 2 of\n * the License, or (at your option) any later version.\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n * GNU General Public License for more details.\n *\n * You should have received a copy of the GNU General Public License\n * along with this program; if not, write to the Free Software\n * Foundation, Inc., 59 Temple Place, Suite 330, Boston,`\n * MA 02111-1307 USA\n */\n#include <common.h>\n#include <asm/arch/clock.h>\n\n/**\n * SATA related definitions\n */\n#define ATA_PORT_CTL        0\n#define ATA_PORT_FEATURE    1\n#define ATA_PORT_NSECT      2\n#define ATA_PORT_LBAL       3\n#define ATA_PORT_LBAM       4\n#define ATA_PORT_LBAH       5\n#define ATA_PORT_DEVICE     6\n#define ATA_PORT_COMMAND    7\n\n/* The offsets to the SATA registers */\n#define SATA_ORB1_OFF           0\n#define SATA_ORB2_OFF           1\n#define SATA_ORB3_OFF           2\n#define SATA_ORB4_OFF           3\n#define SATA_ORB5_OFF           4\n\n#define SATA_FIS_ACCESS         11\n#define SATA_INT_STATUS_OFF     12  /* Read only */\n#define SATA_INT_CLR_OFF        12  /* Write only */\n#define SATA_INT_ENABLE_OFF     13  /* Read only */\n#define SATA_INT_ENABLE_SET_OFF 13  /* Write only */\n#define SATA_INT_ENABLE_CLR_OFF 14  /* Write only */\n#define SATA_VERSION_OFF        15\n#define SATA_CONTROL_OFF        23\n#define SATA_COMMAND_OFF        24\n#define SATA_PORT_CONTROL_OFF   25\n#define SATA_DRIVE_CONTROL_OFF  26\n\n/* The offsets to the link registers that are access in an asynchronous manner */\n#define SATA_LINK_DATA     28\n#define SATA_LINK_RD_ADDR  29\n#define SATA_LINK_WR_ADDR  30\n#define SATA_LINK_CONTROL  31\n\n/* SATA interrupt status register fields */\n#define SATA_INT_STATUS_EOC_RAW_BIT     ( 0 + 16)\n#define SATA_INT_STATUS_ERROR_BIT       ( 2 + 16)\n#define SATA_INT_STATUS_EOADT_RAW_BIT   ( 1 + 16)\n\n/* SATA core command register commands */\n#define SATA_CMD_WRITE_TO_ORB_REGS              2\n#define SATA_CMD_WRITE_TO_ORB_REGS_NO_COMMAND   4\n\n#define SATA_CMD_BUSY_BIT 7\n\n#define SATA_SCTL_CLR_ERR 0x00000316UL\n\n#define SATA_LBAL_BIT    0\n#define SATA_LBAM_BIT    8\n#define SATA_LBAH_BIT    16\n#define SATA_HOB_LBAH_BIT 24\n#define SATA_DEVICE_BIT  24\n#define SATA_NSECT_BIT   0\n#define SATA_HOB_NSECT_BIT   8\n#define SATA_LBA32_BIT       0\n#define SATA_LBA40_BIT       8\n#define SATA_FEATURE_BIT 16\n#define SATA_COMMAND_BIT 24\n#define SATA_CTL_BIT     24\n\n/* ATA status (7) register field definitions */\n#define ATA_STATUS_BSY_BIT     7\n#define ATA_STATUS_DRDY_BIT    6\n#define ATA_STATUS_DF_BIT      5\n#define ATA_STATUS_DRQ_BIT     3\n#define ATA_STATUS_ERR_BIT     0\n\n/* ATA device (6) register field definitions */\n#define ATA_DEVICE_FIXED_MASK 0xA0\n#define ATA_DEVICE_DRV_BIT 4\n#define ATA_DEVICE_DRV_NUM_BITS 1\n#define ATA_DEVICE_LBA_BIT 6\n\n/* ATA Command register initiated commands */\n#define ATA_CMD_INIT    0x91\n#define ATA_CMD_IDENT   0xEC\n\n#define SATA_STD_ASYNC_REGS_OFF 0x20\n#define SATA_SCR_STATUS      0\n#define SATA_SCR_ERROR       1\n#define SATA_SCR_CONTROL     2\n#define SATA_SCR_ACTIVE      3\n#define SATA_SCR_NOTIFICAION 4\n\n#define SATA_BURST_BUF_FORCE_EOT_BIT        0\n#define SATA_BURST_BUF_DATA_INJ_ENABLE_BIT  1\n#define SATA_BURST_BUF_DIR_BIT              2\n#define SATA_BURST_BUF_DATA_INJ_END_BIT     3\n#define SATA_BURST_BUF_FIFO_DIS_BIT         4\n#define SATA_BURST_BUF_DIS_DREQ_BIT         5\n#define SATA_BURST_BUF_DREQ_BIT             6\n\n#define SATA_OPCODE_MASK 0x3\n\n#define SATA_DMA_CHANNEL 0\n\n#define DMA_CTRL_STATUS      (0x0)\n#define DMA_BASE_SRC_ADR     (0x4)\n#define DMA_BASE_DST_ADR     (0x8)\n#define DMA_BYTE_CNT         (0xC)\n#define DMA_CURRENT_SRC_ADR  (0x10)\n#define DMA_CURRENT_DST_ADR  (0x14)\n#define DMA_CURRENT_BYTE_CNT (0x18)\n#define DMA_INTR_ID          (0x1C)\n#define DMA_INTR_CLEAR_REG   (DMA_CURRENT_SRC_ADR)\n\n#define DMA_CALC_REG_ADR(channel, register) ((volatile u32*)(DMA_BASE + ((channel) << 5) + (register)))\n\n#define DMA_CTRL_STATUS_FAIR_SHARE_ARB            (1 << 0)\n#define DMA_CTRL_STATUS_IN_PROGRESS               (1 << 1)\n#define DMA_CTRL_STATUS_SRC_DREQ_MASK             (0x0000003C)\n#define DMA_CTRL_STATUS_SRC_DREQ_SHIFT            (2)\n#define DMA_CTRL_STATUS_DEST_DREQ_MASK            (0x000003C0)\n#define DMA_CTRL_STATUS_DEST_DREQ_SHIFT           (6)\n#define DMA_CTRL_STATUS_INTR                      (1 << 10)\n#define DMA_CTRL_STATUS_NXT_FREE                  (1 << 11)\n#define DMA_CTRL_STATUS_RESET                     (1 << 12)\n#define DMA_CTRL_STATUS_DIR_MASK                  (0x00006000)\n#define DMA_CTRL_STATUS_DIR_SHIFT                 (13)\n#define DMA_CTRL_STATUS_SRC_ADR_MODE              (1 << 15)\n#define DMA_CTRL_STATUS_DEST_ADR_MODE             (1 << 16)\n#define DMA_CTRL_STATUS_TRANSFER_MODE_A           (1 << 17)\n#define DMA_CTRL_STATUS_TRANSFER_MODE_B           (1 << 18)\n#define DMA_CTRL_STATUS_SRC_WIDTH_MASK            (0x00380000)\n#define DMA_CTRL_STATUS_SRC_WIDTH_SHIFT           (19)\n#define DMA_CTRL_STATUS_DEST_WIDTH_MASK           (0x01C00000)\n#define DMA_CTRL_STATUS_DEST_WIDTH_SHIFT          (22)\n#define DMA_CTRL_STATUS_PAUSE                     (1 << 25)\n#define DMA_CTRL_STATUS_INTERRUPT_ENABLE          (1 << 26)\n#define DMA_CTRL_STATUS_SOURCE_ADDRESS_FIXED      (1 << 27)\n#define DMA_CTRL_STATUS_DESTINATION_ADDRESS_FIXED (1 << 28)\n#define DMA_CTRL_STATUS_STARVE_LOW_PRIORITY       (1 << 29)\n#define DMA_CTRL_STATUS_INTR_CLEAR_ENABLE         (1 << 30)\n\n#define DMA_BYTE_CNT_MASK        ((1 << 21) - 1)\n#define DMA_BYTE_CNT_WR_EOT_MASK (1 << 30)\n#define DMA_BYTE_CNT_RD_EOT_MASK (1 << 31)\n#define DMA_BYTE_CNT_BURST_MASK  (1 << 28)\n\n#define MAKE_FIELD(value, num_bits, bit_num) (((value) & ((1 << (num_bits)) - 1)) << (bit_num))\n\ntypedef enum oxnas_dma_mode {\n\tOXNAS_DMA_MODE_FIXED, OXNAS_DMA_MODE_INC\n} oxnas_dma_mode_t;\n\ntypedef enum oxnas_dma_direction {\n\tOXNAS_DMA_TO_DEVICE, OXNAS_DMA_FROM_DEVICE\n} oxnas_dma_direction_t;\n\n/* The available buses to which the DMA controller is attached */\ntypedef enum oxnas_dma_transfer_bus {\n\tOXNAS_DMA_SIDE_A, OXNAS_DMA_SIDE_B\n} oxnas_dma_transfer_bus_t;\n\n/* Direction of data flow between the DMA controller's pair of interfaces */\ntypedef enum oxnas_dma_transfer_direction {\n\tOXNAS_DMA_A_TO_A, OXNAS_DMA_B_TO_A, OXNAS_DMA_A_TO_B, OXNAS_DMA_B_TO_B\n} oxnas_dma_transfer_direction_t;\n\n/* The available data widths */\ntypedef enum oxnas_dma_transfer_width {\n\tOXNAS_DMA_TRANSFER_WIDTH_8BITS,\n\tOXNAS_DMA_TRANSFER_WIDTH_16BITS,\n\tOXNAS_DMA_TRANSFER_WIDTH_32BITS\n} oxnas_dma_transfer_width_t;\n\n/* The mode of the DMA transfer */\ntypedef enum oxnas_dma_transfer_mode {\n\tOXNAS_DMA_TRANSFER_MODE_SINGLE, OXNAS_DMA_TRANSFER_MODE_BURST\n} oxnas_dma_transfer_mode_t;\n\n/* The available transfer targets */\ntypedef enum oxnas_dma_dreq {\n\tOXNAS_DMA_DREQ_SATA = 0, OXNAS_DMA_DREQ_MEMORY = 15\n} oxnas_dma_dreq_t;\n\ntypedef struct oxnas_dma_device_settings {\n\tunsigned long address_;\n\tunsigned fifo_size_; // Chained transfers must take account of FIFO offset at end of previous transfer\n\tunsigned char dreq_;\n\tunsigned read_eot_ :1;\n\tunsigned read_final_eot_ :1;\n\tunsigned write_eot_ :1;\n\tunsigned write_final_eot_ :1;\n\tunsigned bus_ :1;\n\tunsigned width_ :2;\n\tunsigned transfer_mode_ :1;\n\tunsigned address_mode_ :1;\n\tunsigned address_really_fixed_ :1;\n} oxnas_dma_device_settings_t;\n\nstatic const int MAX_NO_ERROR_LOOPS = 100000; /* 1 second in units of 10uS */\nstatic const int MAX_DMA_XFER_LOOPS = 300000; /* 30 seconds in units of 100uS */\nstatic const int MAX_DMA_ABORT_LOOPS = 10000; /* 0.1 second in units of 10uS */\nstatic const int MAX_SRC_READ_LOOPS = 10000; /* 0.1 second in units of 10uS */\nstatic const int MAX_SRC_WRITE_LOOPS = 10000; /* 0.1 second in units of 10uS */\nstatic const int MAX_NOT_BUSY_LOOPS = 10000; /* 1 second in units of 100uS */\n\n/* The internal SATA drive on which we should attempt to find partitions */\nstatic volatile u32* sata_regs_base[2] = { (volatile u32*) SATA_0_REGS_BASE,\n\t\t(volatile u32*) SATA_1_REGS_BASE,\n\n};\nstatic u32 wr_sata_orb1[2] = { 0, 0 };\nstatic u32 wr_sata_orb2[2] = { 0, 0 };\nstatic u32 wr_sata_orb3[2] = { 0, 0 };\nstatic u32 wr_sata_orb4[2] = { 0, 0 };\n\n#ifdef CONFIG_LBA48\n/* need keeping a record of NSECT LBAL LBAM LBAH ide_outb values for lba48 support */\n#define OUT_HISTORY_BASE\tATA_PORT_NSECT\n#define OUT_HISTORY_MAX\t\tATA_PORT_LBAH\nstatic unsigned char out_history[2][OUT_HISTORY_MAX - OUT_HISTORY_BASE + 1] = {};\n#endif\n\nstatic oxnas_dma_device_settings_t oxnas_sata_dma_settings = { .address_ =\n\tSATA_DATA_BASE, .fifo_size_ = 16, .dreq_ = OXNAS_DMA_DREQ_SATA,\n\t\t.read_eot_ = 0, .read_final_eot_ = 1, .write_eot_ = 0,\n\t\t.write_final_eot_ = 1, .bus_ = OXNAS_DMA_SIDE_B, .width_ =\n\t\t\tOXNAS_DMA_TRANSFER_WIDTH_32BITS, .transfer_mode_ =\n\t\t\tOXNAS_DMA_TRANSFER_MODE_BURST, .address_mode_ =\n\t\t\tOXNAS_DMA_MODE_FIXED, .address_really_fixed_ = 0 };\n\noxnas_dma_device_settings_t oxnas_ram_dma_settings = { .address_ = 0,\n\t\t.fifo_size_ = 0, .dreq_ = OXNAS_DMA_DREQ_MEMORY, .read_eot_ = 1,\n\t\t.read_final_eot_ = 1, .write_eot_ = 1, .write_final_eot_ = 1,\n\t\t.bus_ = OXNAS_DMA_SIDE_A, .width_ =\n\t\t\tOXNAS_DMA_TRANSFER_WIDTH_32BITS, .transfer_mode_ =\n\t\t\tOXNAS_DMA_TRANSFER_MODE_BURST, .address_mode_ =\n\t\t\tOXNAS_DMA_MODE_FIXED, .address_really_fixed_ = 1 };\n\nstatic void xfer_wr_shadow_to_orbs(int device)\n{\n\t*(sata_regs_base[device] + SATA_ORB1_OFF) = wr_sata_orb1[device];\n\t*(sata_regs_base[device] + SATA_ORB2_OFF) = wr_sata_orb2[device];\n\t*(sata_regs_base[device] + SATA_ORB3_OFF) = wr_sata_orb3[device];\n\t*(sata_regs_base[device] + SATA_ORB4_OFF) = wr_sata_orb4[device];\n}\n\nstatic inline void device_select(int device)\n{\n\t/* master/slave has no meaning to SATA core */\n}\n\nstatic int disk_present[CONFIG_SYS_IDE_MAXDEVICE];\n\n#include <ata.h>\n\nunsigned char ide_inb(int device, int port)\n{\n\tunsigned char val = 0;\n\n\t/* Only permit accesses to disks found to be present during ide_preinit() */\n\tif (!disk_present[device]) {\n\t\treturn ATA_STAT_FAULT;\n\t}\n\n\tdevice_select(device);\n\n\tswitch (port) {\n\tcase ATA_PORT_CTL:\n\t\tval = (*(sata_regs_base[device] + SATA_ORB4_OFF)\n\t\t\t& (0xFFUL << SATA_CTL_BIT)) >> SATA_CTL_BIT;\n\t\tbreak;\n\tcase ATA_PORT_FEATURE:\n\t\tval = (*(sata_regs_base[device] + SATA_ORB2_OFF)\n\t\t\t& (0xFFUL << SATA_FEATURE_BIT)) >> SATA_FEATURE_BIT;\n\t\tbreak;\n\tcase ATA_PORT_NSECT:\n\t\tval = (*(sata_regs_base[device] + SATA_ORB2_OFF)\n\t\t\t& (0xFFUL << SATA_NSECT_BIT)) >> SATA_NSECT_BIT;\n\t\tbreak;\n\tcase ATA_PORT_LBAL:\n\t\tval = (*(sata_regs_base[device] + SATA_ORB3_OFF)\n\t\t\t& (0xFFUL << SATA_LBAL_BIT)) >> SATA_LBAL_BIT;\n\t\tbreak;\n\tcase ATA_PORT_LBAM:\n\t\tval = (*(sata_regs_base[device] + SATA_ORB3_OFF)\n\t\t\t& (0xFFUL << SATA_LBAM_BIT)) >> SATA_LBAM_BIT;\n\t\tbreak;\n\tcase ATA_PORT_LBAH:\n\t\tval = (*(sata_regs_base[device] + SATA_ORB3_OFF)\n\t\t\t& (0xFFUL << SATA_LBAH_BIT)) >> SATA_LBAH_BIT;\n\t\tbreak;\n\tcase ATA_PORT_DEVICE:\n\t\tval = (*(sata_regs_base[device] + SATA_ORB3_OFF)\n\t\t\t& (0xFFUL << SATA_HOB_LBAH_BIT)) >> SATA_HOB_LBAH_BIT;\n\t\tval |= (*(sata_regs_base[device] + SATA_ORB1_OFF)\n\t\t\t& (0xFFUL << SATA_DEVICE_BIT)) >> SATA_DEVICE_BIT;\n\t\tbreak;\n\tcase ATA_PORT_COMMAND:\n\t\tval = (*(sata_regs_base[device] + SATA_ORB2_OFF)\n\t\t\t& (0xFFUL << SATA_COMMAND_BIT)) >> SATA_COMMAND_BIT;\n\t\tval |= ATA_STAT_DRQ;\n\t\tbreak;\n\tdefault:\n\t\tprintf(\"ide_inb() Unknown port = %d\\n\", port);\n\t\tbreak;\n\t}\n\n\t//    printf(\"inb: %d:%01x => %02x\\n\", device, port, val);\n\n\treturn val;\n}\n\n/**\n * Possible that ATA status will not become no-error, so must have timeout\n * @returns An int which is zero on error\n */\nstatic inline int wait_no_error(int device)\n{\n\tint status = 0;\n\n\t/* Check for ATA core error */\n\tif (*(sata_regs_base[device] + SATA_INT_STATUS_OFF)\n\t\t& (1 << SATA_INT_STATUS_ERROR_BIT)) {\n\t\tprintf(\"wait_no_error() SATA core flagged error\\n\");\n\t} else {\n\t\tint loops = MAX_NO_ERROR_LOOPS;\n\t\tdo {\n\t\t\t/* Check for ATA device error */\n\t\t\tif (!(ide_inb(device, ATA_PORT_COMMAND)\n\t\t\t\t& (1 << ATA_STATUS_ERR_BIT))) {\n\t\t\t\tstatus = 1;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\tudelay(10);\n\t\t} while (--loops);\n\n\t\tif (!loops) {\n\t\t\tprintf(\"wait_no_error() Timed out of wait for SATA no-error condition\\n\");\n\t\t}\n\t}\n\n\treturn status;\n}\n\n/**\n * Expect SATA command to always finish, perhaps with error\n * @returns An int which is zero on error\n */\nstatic inline int wait_sata_command_not_busy(int device)\n{\n\t/* Wait for data to be available */\n\tint status = 0;\n\tint loops = MAX_NOT_BUSY_LOOPS;\n\tdo {\n\t\tif (!(*(sata_regs_base[device] + SATA_COMMAND_OFF)\n\t\t\t& (1 << SATA_CMD_BUSY_BIT))) {\n\t\t\tstatus = 1;\n\t\t\tbreak;\n\t\t}\n\t\tudelay(100);\n\t} while (--loops);\n\n\tif (!loops) {\n\t\tprintf(\"wait_sata_command_not_busy() Timed out of wait for SATA command to finish\\n\");\n\t}\n\n\treturn status;\n}\n\nvoid ide_outb(int device, int port, unsigned char val)\n{\n\ttypedef enum send_method {\n\t\tSEND_NONE, SEND_SIMPLE, SEND_CMD, SEND_CTL,\n\t} send_method_t;\n\n\t/* Only permit accesses to disks found to be present during ide_preinit() */\n\tif (!disk_present[device]) {\n\t\treturn;\n\t}\n\n\t//    printf(\"outb: %d:%01x <= %02x\\n\", device, port, val);\n\n\tdevice_select(device);\n\n#ifdef CONFIG_LBA48\n\tif (port >= OUT_HISTORY_BASE && port <= OUT_HISTORY_MAX) {\n\t\tout_history[0][port - OUT_HISTORY_BASE] =\n\t\t\tout_history[1][port - OUT_HISTORY_BASE];\n\t\tout_history[1][port - OUT_HISTORY_BASE] = val;\n\t}\n#endif\n\tsend_method_t send_regs = SEND_NONE;\n\tswitch (port) {\n\tcase ATA_PORT_CTL:\n\t\twr_sata_orb4[device] &= ~(0xFFUL << SATA_CTL_BIT);\n\t\twr_sata_orb4[device] |= (val << SATA_CTL_BIT);\n\t\tsend_regs = SEND_CTL;\n\t\tbreak;\n\tcase ATA_PORT_FEATURE:\n\t\twr_sata_orb2[device] &= ~(0xFFUL << SATA_FEATURE_BIT);\n\t\twr_sata_orb2[device] |= (val << SATA_FEATURE_BIT);\n\t\tsend_regs = SEND_SIMPLE;\n\t\tbreak;\n\tcase ATA_PORT_NSECT:\n\t\twr_sata_orb2[device] &= ~(0xFFUL << SATA_NSECT_BIT);\n\t\twr_sata_orb2[device] |= (val << SATA_NSECT_BIT);\n\t\tsend_regs = SEND_SIMPLE;\n\t\tbreak;\n\tcase ATA_PORT_LBAL:\n\t\twr_sata_orb3[device] &= ~(0xFFUL << SATA_LBAL_BIT);\n\t\twr_sata_orb3[device] |= (val << SATA_LBAL_BIT);\n\t\tsend_regs = SEND_SIMPLE;\n\t\tbreak;\n\tcase ATA_PORT_LBAM:\n\t\twr_sata_orb3[device] &= ~(0xFFUL << SATA_LBAM_BIT);\n\t\twr_sata_orb3[device] |= (val << SATA_LBAM_BIT);\n\t\tsend_regs = SEND_SIMPLE;\n\t\tbreak;\n\tcase ATA_PORT_LBAH:\n\t\twr_sata_orb3[device] &= ~(0xFFUL << SATA_LBAH_BIT);\n\t\twr_sata_orb3[device] |= (val << SATA_LBAH_BIT);\n\t\tsend_regs = SEND_SIMPLE;\n\t\tbreak;\n\tcase ATA_PORT_DEVICE:\n\t\twr_sata_orb1[device] &= ~(0xFFUL << SATA_DEVICE_BIT);\n\t\twr_sata_orb1[device] |= (val << SATA_DEVICE_BIT);\n\t\tsend_regs = SEND_SIMPLE;\n\t\tbreak;\n\tcase ATA_PORT_COMMAND:\n\t\twr_sata_orb2[device] &= ~(0xFFUL << SATA_COMMAND_BIT);\n\t\twr_sata_orb2[device] |= (val << SATA_COMMAND_BIT);\n\t\tsend_regs = SEND_CMD;\n#ifdef CONFIG_LBA48\n\t\tif (val == ATA_CMD_READ_EXT || val == ATA_CMD_WRITE_EXT)\n\t\t{\n\t\t\t/* fill high bytes of LBA48 && NSECT */\n\t\t\twr_sata_orb2[device] &= ~(0xFFUL << SATA_HOB_NSECT_BIT);\n\t\t\twr_sata_orb2[device] |=\n\t\t\t\t(out_history[0][ATA_PORT_NSECT - OUT_HISTORY_BASE] << SATA_HOB_NSECT_BIT);\n\n\t\t\twr_sata_orb3[device] &= ~(0xFFUL << SATA_HOB_LBAH_BIT);\n\t\t\twr_sata_orb3[device] |=\n\t\t\t\t(out_history[0][ATA_PORT_LBAL - OUT_HISTORY_BASE] << SATA_HOB_LBAH_BIT);\n\n\t\t\twr_sata_orb4[device] &= ~(0xFFUL << SATA_LBA32_BIT);\n\t\t\twr_sata_orb4[device] |=\n\t\t\t\t(out_history[0][ATA_PORT_LBAM - OUT_HISTORY_BASE] << SATA_LBA32_BIT);\n\n\t\t\twr_sata_orb4[device] &= ~(0xFFUL << SATA_LBA40_BIT);\n\t\t\twr_sata_orb4[device] |=\n\t\t\t\t(out_history[0][ATA_PORT_LBAH - OUT_HISTORY_BASE] << SATA_LBA40_BIT);\n\t\t}\n#endif\n\t\tbreak;\n\tdefault:\n\t\tprintf(\"ide_outb() Unknown port = %d\\n\", port);\n\t}\n\n\tu32 command;\n\tswitch (send_regs) {\n\tcase SEND_CMD:\n\t\twait_sata_command_not_busy(device);\n\t\tcommand = *(sata_regs_base[device] + SATA_COMMAND_OFF);\n\t\tcommand &= ~SATA_OPCODE_MASK;\n\t\tcommand |= SATA_CMD_WRITE_TO_ORB_REGS;\n\t\txfer_wr_shadow_to_orbs(device);\n\t\twait_sata_command_not_busy(device);\n\t\t*(sata_regs_base[device] + SATA_COMMAND_OFF) = command;\n\t\tif (!wait_no_error(device)) {\n\t\t\tprintf(\"ide_outb() Wait for ATA no-error timed-out\\n\");\n\t\t}\n\t\tbreak;\n\tcase SEND_CTL:\n\t\twait_sata_command_not_busy(device);\n\t\tcommand = *(sata_regs_base[device] + SATA_COMMAND_OFF);\n\t\tcommand &= ~SATA_OPCODE_MASK;\n\t\tcommand |= SATA_CMD_WRITE_TO_ORB_REGS_NO_COMMAND;\n\t\txfer_wr_shadow_to_orbs(device);\n\t\twait_sata_command_not_busy(device);\n\t\t*(sata_regs_base[device] + SATA_COMMAND_OFF) = command;\n\t\tif (!wait_no_error(device)) {\n\t\t\tprintf(\"ide_outb() Wait for ATA no-error timed-out\\n\");\n\t\t}\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n}\n\nstatic u32 encode_start(u32 ctrl_status)\n{\n\treturn ctrl_status & ~DMA_CTRL_STATUS_PAUSE;\n}\n\n/* start a paused DMA transfer in channel 0 of the SATA DMA core */\nstatic void dma_start(void)\n{\n\tunsigned int reg;\n\treg = readl(SATA_DMA_REGS_BASE + DMA_CTRL_STATUS);\n\treg = encode_start(reg);\n\twritel(reg, SATA_DMA_REGS_BASE + DMA_CTRL_STATUS);\n}\n\nstatic unsigned long encode_control_status(\n\toxnas_dma_device_settings_t* src_settings,\n\toxnas_dma_device_settings_t* dst_settings)\n{\n\tunsigned long ctrl_status;\n\toxnas_dma_transfer_direction_t direction;\n\n\tctrl_status = DMA_CTRL_STATUS_PAUSE;                           // Paused\n\tctrl_status |= DMA_CTRL_STATUS_FAIR_SHARE_ARB;          // High priority\n\tctrl_status |= (src_settings->dreq_ << DMA_CTRL_STATUS_SRC_DREQ_SHIFT); // Dreq\n\tctrl_status |= (dst_settings->dreq_ << DMA_CTRL_STATUS_DEST_DREQ_SHIFT); // Dreq\n\tctrl_status &= ~DMA_CTRL_STATUS_RESET;                         // !RESET\n\n\t// Use new interrupt clearing register\n\tctrl_status |= DMA_CTRL_STATUS_INTR_CLEAR_ENABLE;\n\n\t// Setup the transfer direction and burst/single mode for the two DMA busses\n\tif (src_settings->bus_ == OXNAS_DMA_SIDE_A) {\n\t\t// Set the burst/single mode for bus A based on src device's settings\n\t\tif (src_settings->transfer_mode_\n\t\t\t== OXNAS_DMA_TRANSFER_MODE_BURST) {\n\t\t\tctrl_status |= DMA_CTRL_STATUS_TRANSFER_MODE_A;\n\t\t} else {\n\t\t\tctrl_status &= ~DMA_CTRL_STATUS_TRANSFER_MODE_A;\n\t\t}\n\n\t\tif (dst_settings->bus_ == OXNAS_DMA_SIDE_A) {\n\t\t\tdirection = OXNAS_DMA_A_TO_A;\n\t\t} else {\n\t\t\tdirection = OXNAS_DMA_A_TO_B;\n\n\t\t\t// Set the burst/single mode for bus B based on dst device's settings\n\t\t\tif (dst_settings->transfer_mode_\n\t\t\t\t== OXNAS_DMA_TRANSFER_MODE_BURST) {\n\t\t\t\tctrl_status |= DMA_CTRL_STATUS_TRANSFER_MODE_B;\n\t\t\t} else {\n\t\t\t\tctrl_status &= ~DMA_CTRL_STATUS_TRANSFER_MODE_B;\n\t\t\t}\n\t\t}\n\t} else {\n\t\t// Set the burst/single mode for bus B based on src device's settings\n\t\tif (src_settings->transfer_mode_\n\t\t\t== OXNAS_DMA_TRANSFER_MODE_BURST) {\n\t\t\tctrl_status |= DMA_CTRL_STATUS_TRANSFER_MODE_B;\n\t\t} else {\n\t\t\tctrl_status &= ~DMA_CTRL_STATUS_TRANSFER_MODE_B;\n\t\t}\n\n\t\tif (dst_settings->bus_ == OXNAS_DMA_SIDE_A) {\n\t\t\tdirection = OXNAS_DMA_B_TO_A;\n\n\t\t\t// Set the burst/single mode for bus A based on dst device's settings\n\t\t\tif (dst_settings->transfer_mode_\n\t\t\t\t== OXNAS_DMA_TRANSFER_MODE_BURST) {\n\t\t\t\tctrl_status |= DMA_CTRL_STATUS_TRANSFER_MODE_A;\n\t\t\t} else {\n\t\t\t\tctrl_status &= ~DMA_CTRL_STATUS_TRANSFER_MODE_A;\n\t\t\t}\n\t\t} else {\n\t\t\tdirection = OXNAS_DMA_B_TO_B;\n\t\t}\n\t}\n\tctrl_status |= (direction << DMA_CTRL_STATUS_DIR_SHIFT);\n\n\t// Setup source address mode fixed or increment\n\tif (src_settings->address_mode_ == OXNAS_DMA_MODE_FIXED) {\n\t\t// Fixed address\n\t\tctrl_status &= ~(DMA_CTRL_STATUS_SRC_ADR_MODE);\n\n\t\t// Set up whether fixed address is _really_ fixed\n\t\tif (src_settings->address_really_fixed_) {\n\t\t\tctrl_status |= DMA_CTRL_STATUS_SOURCE_ADDRESS_FIXED;\n\t\t} else {\n\t\t\tctrl_status &= ~DMA_CTRL_STATUS_SOURCE_ADDRESS_FIXED;\n\t\t}\n\t} else {\n\t\t// Incrementing address\n\t\tctrl_status |= DMA_CTRL_STATUS_SRC_ADR_MODE;\n\t\tctrl_status &= ~DMA_CTRL_STATUS_SOURCE_ADDRESS_FIXED;\n\t}\n\n\t// Setup destination address mode fixed or increment\n\tif (dst_settings->address_mode_ == OXNAS_DMA_MODE_FIXED) {\n\t\t// Fixed address\n\t\tctrl_status &= ~(DMA_CTRL_STATUS_DEST_ADR_MODE);\n\n\t\t// Set up whether fixed address is _really_ fixed\n\t\tif (dst_settings->address_really_fixed_) {\n\t\t\tctrl_status |=\n\t\t\t\tDMA_CTRL_STATUS_DESTINATION_ADDRESS_FIXED;\n\t\t} else {\n\t\t\tctrl_status &=\n\t\t\t\t~DMA_CTRL_STATUS_DESTINATION_ADDRESS_FIXED;\n\t\t}\n\t} else {\n\t\t// Incrementing address\n\t\tctrl_status |= DMA_CTRL_STATUS_DEST_ADR_MODE;\n\t\tctrl_status &= ~DMA_CTRL_STATUS_DESTINATION_ADDRESS_FIXED;\n\t}\n\n\t// Set up the width of the transfers on the DMA buses\n\tctrl_status |=\n\t\t(src_settings->width_ << DMA_CTRL_STATUS_SRC_WIDTH_SHIFT);\n\tctrl_status |=\n\t\t(dst_settings->width_ << DMA_CTRL_STATUS_DEST_WIDTH_SHIFT);\n\n\t// Setup the priority arbitration scheme\n\tctrl_status &= ~DMA_CTRL_STATUS_STARVE_LOW_PRIORITY; // !Starve low priority\n\n\treturn ctrl_status;\n}\n\nstatic u32 encode_final_eot(oxnas_dma_device_settings_t* src_settings,\n\t\t\t\toxnas_dma_device_settings_t* dst_settings,\n\t\t\t\tunsigned long length)\n{\n\t// Write the length, with EOT configuration for a final transfer\n\tunsigned long encoded = length;\n\tif (dst_settings->write_final_eot_) {\n\t\tencoded |= DMA_BYTE_CNT_WR_EOT_MASK;\n\t} else {\n\t\tencoded &= ~DMA_BYTE_CNT_WR_EOT_MASK;\n\t}\n\tif (src_settings->read_final_eot_) {\n\t\tencoded |= DMA_BYTE_CNT_RD_EOT_MASK;\n\t} else {\n\t\tencoded &= ~DMA_BYTE_CNT_RD_EOT_MASK;\n\t}\n\t/*    if((src_settings->transfer_mode_) ||\n\t (src_settings->transfer_mode_)) {\n\t encoded |= DMA_BYTE_CNT_BURST_MASK;\n\t } else {\n\t encoded &= ~DMA_BYTE_CNT_BURST_MASK;\n\t }*/\n\treturn encoded;\n}\n\nstatic void dma_start_write(const ulong* buffer, int num_bytes)\n{\n\t// Assemble complete memory settings\n\toxnas_dma_device_settings_t mem_settings = oxnas_ram_dma_settings;\n\tmem_settings.address_ = (unsigned long) buffer;\n\tmem_settings.address_mode_ = OXNAS_DMA_MODE_INC;\n\n\twritel(encode_control_status(&mem_settings, &oxnas_sata_dma_settings),\n\t\tSATA_DMA_REGS_BASE + DMA_CTRL_STATUS);\n\twritel(mem_settings.address_, SATA_DMA_REGS_BASE + DMA_BASE_SRC_ADR);\n\twritel(oxnas_sata_dma_settings.address_,\n\t\tSATA_DMA_REGS_BASE + DMA_BASE_DST_ADR);\n\twritel(encode_final_eot(&mem_settings, &oxnas_sata_dma_settings,\n\t\t\t\tnum_bytes),\n\t\tSATA_DMA_REGS_BASE + DMA_BYTE_CNT);\n\n\tdma_start();\n}\n\nstatic void dma_start_read(ulong* buffer, int num_bytes)\n{\n\t// Assemble complete memory settings\n\toxnas_dma_device_settings_t mem_settings = oxnas_ram_dma_settings;\n\tmem_settings.address_ = (unsigned long) buffer;\n\tmem_settings.address_mode_ = OXNAS_DMA_MODE_INC;\n\n\twritel(encode_control_status(&oxnas_sata_dma_settings, &mem_settings),\n\t\tSATA_DMA_REGS_BASE + DMA_CTRL_STATUS);\n\twritel(oxnas_sata_dma_settings.address_,\n\t\tSATA_DMA_REGS_BASE + DMA_BASE_SRC_ADR);\n\twritel(mem_settings.address_, SATA_DMA_REGS_BASE + DMA_BASE_DST_ADR);\n\twritel(encode_final_eot(&oxnas_sata_dma_settings, &mem_settings,\n\t\t\t\tnum_bytes),\n\t\tSATA_DMA_REGS_BASE + DMA_BYTE_CNT);\n\n\tdma_start();\n}\n\nstatic inline int dma_busy(void)\n{\n\treturn readl(SATA_DMA_REGS_BASE + DMA_CTRL_STATUS)\n\t\t& DMA_CTRL_STATUS_IN_PROGRESS;\n}\n\nstatic int wait_dma_not_busy(int device)\n{\n\tunsigned int cleanup_required = 0;\n\n\t/* Poll for DMA completion */\n\tint loops = MAX_DMA_XFER_LOOPS;\n\tdo {\n\t\tif (!dma_busy()) {\n\t\t\tbreak;\n\t\t}\n\t\tudelay(100);\n\t} while (--loops);\n\n\tif (!loops) {\n\t\tprintf(\"wait_dma_not_busy() Timed out of wait for DMA not busy\\n\");\n\t\tcleanup_required = 1;\n\t}\n\n\tif (cleanup_required) {\n\t\t/* Abort DMA to make sure it has finished. */\n\t\tunsigned int ctrl_status = readl(\n\t\t\tSATA_DMA_CHANNEL + DMA_CTRL_STATUS);\n\t\tctrl_status |= DMA_CTRL_STATUS_RESET;\n\t\twritel(ctrl_status, SATA_DMA_CHANNEL + DMA_CTRL_STATUS);\n\n\t\t// Wait for the channel to become idle - should be quick as should\n\t\t// finish after the next AHB single or burst transfer\n\t\tloops = MAX_DMA_ABORT_LOOPS;\n\t\tdo {\n\t\t\tif (!dma_busy()) {\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\tudelay(10);\n\t\t} while (--loops);\n\n\t\tif (!loops) {\n\t\t\tprintf(\"wait_dma_not_busy() Timed out of wait for DMA channel abort\\n\");\n\t\t} else {\n\t\t\t/* Successfully cleanup the DMA channel */\n\t\t\tcleanup_required = 0;\n\t\t}\n\n\t\t// Deassert reset for the channel\n\t\tctrl_status = readl(SATA_DMA_CHANNEL + DMA_CTRL_STATUS);\n\t\tctrl_status &= ~DMA_CTRL_STATUS_RESET;\n\t\twritel(ctrl_status, SATA_DMA_CHANNEL + DMA_CTRL_STATUS);\n\t}\n\n\treturn !cleanup_required;\n}\n\n/**\n * Possible that ATA status will not become not-busy, so must have timeout\n */\nstatic unsigned int wait_not_busy(int device, unsigned long timeout_secs)\n{\n\tint busy = 1;\n\tunsigned long loops = (timeout_secs * 1000) / 50;\n\tdo {\n\t\t// Test the ATA status register BUSY flag\n\t\tif (!((*(sata_regs_base[device] + SATA_ORB2_OFF)\n\t\t\t>> SATA_COMMAND_BIT) & (1UL << ATA_STATUS_BSY_BIT))) {\n\t\t\t/* Not busy, so stop polling */\n\t\t\tbusy = 0;\n\t\t\tbreak;\n\t\t}\n\n\t\t// Wait for 50mS before sampling ATA status register again\n\t\tudelay(50000);\n\t} while (--loops);\n\n\treturn busy;\n}\n\nvoid ide_output_data(int device, const ulong *sect_buf, int words)\n{\n\t/* Only permit accesses to disks found to be present during ide_preinit() */\n\tif (!disk_present[device]) {\n\t\treturn;\n\t}\n\n\t/* Select the required internal SATA drive */\n\tdevice_select(device);\n\n\t/* Start the DMA channel sending data from the passed buffer to the SATA core */\n\tdma_start_write(sect_buf, words << 2);\n\n\t/* Don't know why we need this delay, but without it the wait for DMA not\n\t busy times soemtimes out, e.g. when saving environment to second disk */\n\tudelay(1000);\n\n\t/* Wait for DMA to finish */\n\tif (!wait_dma_not_busy(device)) {\n\t\tprintf(\"Timed out of wait for DMA channel for SATA device %d to have in-progress clear\\n\",\n\t\t\tdevice);\n\t}\n\n\t/* Sata core should finish after DMA */\n\tif (wait_not_busy(device, 30)) {\n\t\tprintf(\"Timed out of wait for SATA device %d to have BUSY clear\\n\",\n\t\t\tdevice);\n\t}\n\tif (!wait_no_error(device)) {\n\t\tprintf(\"oxnas_sata_output_data() Wait for ATA no-error timed-out\\n\");\n\t}\n}\n\n\n#define SATA_DM_DBG1\t\t\t(SATA_HOST_REGS_BASE + 0)\n#define SATA_DATACOUNT_PORT0\t\t(SATA_HOST_REGS_BASE + 0x10)\n#define SATA_DATACOUNT_PORT1\t\t(SATA_HOST_REGS_BASE + 0x14)\n#define SATA_DATA_MUX_RAM0\t\t(SATA_HOST_REGS_BASE + 0x8000)\n#define SATA_DATA_MUX_RAM1\t\t(SATA_HOST_REGS_BASE + 0xA000)\n/* Sata core debug1 register bits */\n#define SATA_CORE_PORT0_DATA_DIR_BIT\t20\n#define SATA_CORE_PORT1_DATA_DIR_BIT\t21\n#define SATA_CORE_PORT0_DATA_DIR\t(1 << SATA_CORE_PORT0_DATA_DIR_BIT)\n#define SATA_CORE_PORT1_DATA_DIR\t(1 << SATA_CORE_PORT1_DATA_DIR_BIT)\n\n/**\n * Ref bug-6320\n *\n * This code is a work around for a DMA hardware bug that will repeat the\n * penultimate 8-bytes on some reads. This code will check that the amount\n * of data transferred is a multiple of 512 bytes, if not the in it will\n * fetch the correct data from a buffer in the SATA core and copy it into\n * memory.\n *\n */\nstatic void sata_bug_6320_workaround(int port, ulong *candidate)\n{\n\tint is_read;\n\tint quads_transferred;\n\tint remainder;\n\tint sector_quads_remaining;\n\n\t/* Only want to apply fix to reads */\n\tis_read = !(*((unsigned long*) SATA_DM_DBG1)\n\t\t& (port ? SATA_CORE_PORT1_DATA_DIR : SATA_CORE_PORT0_DATA_DIR));\n\n\t/* Check for an incomplete transfer, i.e. not a multiple of 512 bytes\n\t transferred (datacount_port register counts quads transferred) */\n\tquads_transferred = *((unsigned long*) (\n\t\tport ? SATA_DATACOUNT_PORT1 : SATA_DATACOUNT_PORT0));\n\n\tremainder = quads_transferred & 0x7f;\n\tsector_quads_remaining = remainder ? (0x80 - remainder) : 0;\n\n\tif (is_read && (sector_quads_remaining == 2)) {\n\t\tdebug(\"SATA read fixup, only transfered %d quads, \"\n\t\t\t\"sector_quads_remaining %d, port %d\\n\",\n\t\t\tquads_transferred, sector_quads_remaining, port);\n\n\t\tint total_len = ATA_SECT_SIZE;\n\t\tulong *sata_data_ptr = (void*) (\n\t\t\tport ? SATA_DATA_MUX_RAM1 : SATA_DATA_MUX_RAM0)\n\t\t\t+ ((total_len - 8) % 2048);\n\n\t\t*candidate = *sata_data_ptr;\n\t\t*(candidate + 1) = *(sata_data_ptr + 1);\n\t}\n}\n\n\nvoid ide_input_data(int device, ulong *sect_buf, int words)\n{\n\t/* Only permit accesses to disks found to be present during ide_preinit() */\n\tif (!disk_present[device]) {\n\t\treturn;\n\t}\n\n\t/* Select the required internal SATA drive */\n\tdevice_select(device);\n\n\t/* Start the DMA channel receiving data from the SATA core into the passed buffer */\n\tdma_start_read(sect_buf, words << 2);\n\n\t/* Sata core should finish before DMA */\n\tif (wait_not_busy(device, 30)) {\n\t\tprintf(\"Timed out of wait for SATA device %d to have BUSY clear\\n\",\n\t\t\tdevice);\n\t}\n\tif (!wait_no_error(device)) {\n\t\tprintf(\"oxnas_sata_output_data() Wait for ATA no-error timed-out\\n\");\n\t}\n\n\t/* Wait for DMA to finish */\n\tif (!wait_dma_not_busy(device)) {\n\t\tprintf(\"Timed out of wait for DMA channel for SATA device %d to have in-progress clear\\n\",\n\t\t\tdevice);\n\t}\n\n\tif (words == ATA_SECTORWORDS)\n\t\tsata_bug_6320_workaround(device, sect_buf + words - 2);\n}\n\nstatic u32 scr_read(int device, unsigned int sc_reg)\n{\n\t/* Setup adr of required register. std regs start eight into async region */\n\t*(sata_regs_base[device] + SATA_LINK_RD_ADDR) = sc_reg\n\t\t* 4+ SATA_STD_ASYNC_REGS_OFF;\n\n\t/* Wait for data to be available */\n\tint loops = MAX_SRC_READ_LOOPS;\n\tdo {\n\t\tif (*(sata_regs_base[device] + SATA_LINK_CONTROL) & 1UL) {\n\t\t\tbreak;\n\t\t}\n\t\tudelay(10);\n\t} while (--loops);\n\n\tif (!loops) {\n\t\tprintf(\"scr_read() Timed out of wait for read completion\\n\");\n\t}\n\n\t/* Read the data from the async register */\n\treturn *(sata_regs_base[device] + SATA_LINK_DATA);\n}\n\nstatic void scr_write(int device, unsigned int sc_reg, u32 val)\n{\n\t/* Setup the data for the write */\n\t*(sata_regs_base[device] + SATA_LINK_DATA) = val;\n\n\t/* Setup adr of required register. std regs start eight into async region */\n\t*(sata_regs_base[device] + SATA_LINK_WR_ADDR) = sc_reg\n\t\t* 4+ SATA_STD_ASYNC_REGS_OFF;\n\n\t/* Wait for data to be written */\n\tint loops = MAX_SRC_WRITE_LOOPS;\n\tdo {\n\t\tif (*(sata_regs_base[device] + SATA_LINK_CONTROL) & 1UL) {\n\t\t\tbreak;\n\t\t}\n\t\tudelay(10);\n\t} while (--loops);\n\n\tif (!loops) {\n\t\tprintf(\"scr_write() Timed out of wait for write completion\\n\");\n\t}\n}\nextern void workaround5458(void);\n\n#define PHY_LOOP_COUNT  25  /* Wait for upto 5 seconds for PHY to be found */\n#define LOS_AND_TX_LVL   0x2988\n#define TX_ATTEN         0x55629\n\nstatic int phy_reset(int device)\n{\n\tint phy_status = 0;\n\tint loops = 0;\n\n\tscr_write(device, (0x60 - SATA_STD_ASYNC_REGS_OFF) / 4, LOS_AND_TX_LVL);\n\tscr_write(device, (0x70 - SATA_STD_ASYNC_REGS_OFF) / 4, TX_ATTEN);\n\n\t/* limit it to Gen-1 SATA (1.5G) */\n\tscr_write(device, SATA_SCR_CONTROL, 0x311); /* Issue phy wake & core reset */\n\tscr_read(device, SATA_SCR_STATUS); /* Dummy read; flush */\n\tudelay(1000);\n\tscr_write(device, SATA_SCR_CONTROL, 0x310); /* Issue phy wake & clear core reset */\n\n\t/* Wait for upto 5 seconds for PHY to become ready */\n\tdo {\n\t\tudelay(200000);\n\t\tif ((scr_read(device, SATA_SCR_STATUS) & 0xf) == 3) {\n\t\t\tscr_write(device, SATA_SCR_ERROR, ~0);\n\t\t\tphy_status = 1;\n\t\t\tbreak;\n\t\t}\n\t\t//printf(\"No SATA PHY found status:0x%x\\n\", scr_read(device, SATA_SCR_STATUS));\n\t} while (++loops < PHY_LOOP_COUNT);\n\n\tif (phy_status) {\n\t\tudelay(500000); /* wait half a second */\n\t}\n\n\treturn phy_status;\n}\n\n#define FIS_LOOP_COUNT  25  /* Wait for upto 5 seconds for FIS to be received */\nstatic int wait_FIS(int device)\n{\n\tint status = 0;\n\tint loops = 0;\n\n\tdo {\n\t\tudelay(200000);\n\t\tif (ide_inb(device, ATA_PORT_NSECT) > 0) {\n\t\t\tstatus = 1;\n\t\t\tbreak;\n\t\t}\n\t} while (++loops < FIS_LOOP_COUNT);\n\n\treturn status;\n}\n\n\n#define SATA_PHY_ASIC_STAT  (0x44900000)\n#define SATA_PHY_ASIC_DATA  (0x44900004)\n\n/**\n * initialise functions and macros for ASIC implementation\n */\n#define PH_GAIN         2\n#define FR_GAIN         3\n#define PH_GAIN_OFFSET  6\n#define FR_GAIN_OFFSET  8\n#define PH_GAIN_MASK  (0x3 << PH_GAIN_OFFSET)\n#define FR_GAIN_MASK  (0x3 << FR_GAIN_OFFSET)\n#define USE_INT_SETTING  (1<<5)\n\n#define CR_READ_ENABLE  (1<<16)\n#define CR_WRITE_ENABLE (1<<17)\n#define CR_CAP_DATA     (1<<18)\n\nstatic void wait_cr_ack(void)\n{\n\twhile ((readl(SATA_PHY_ASIC_STAT) >> 16) & 0x1f)\n\t\t/* wait for an ack bit to be set */;\n}\n\nstatic unsigned short read_cr(unsigned short address)\n{\n\twritel(address, SATA_PHY_ASIC_STAT);\n\twait_cr_ack();\n\twritel(CR_READ_ENABLE, SATA_PHY_ASIC_DATA);\n\twait_cr_ack();\n\treturn readl(SATA_PHY_ASIC_STAT);\n}\n\nstatic void write_cr(unsigned short data, unsigned short address)\n{\n\twritel(address, SATA_PHY_ASIC_STAT);\n\twait_cr_ack();\n\twritel((data | CR_CAP_DATA), SATA_PHY_ASIC_DATA);\n\twait_cr_ack();\n\twritel(CR_WRITE_ENABLE, SATA_PHY_ASIC_DATA);\n\twait_cr_ack();\n\treturn;\n}\n\nvoid workaround5458(void)\n{\n\tunsigned i;\n\n\tfor (i = 0; i < 2; i++) {\n\t\tunsigned short rx_control = read_cr(0x201d + (i << 8));\n\t\trx_control &= ~(PH_GAIN_MASK | FR_GAIN_MASK);\n\t\trx_control |= PH_GAIN << PH_GAIN_OFFSET;\n\t\trx_control |= FR_GAIN << FR_GAIN_OFFSET;\n\t\trx_control |= USE_INT_SETTING;\n\t\twrite_cr(rx_control, 0x201d + (i << 8));\n\t}\n}\n\nint ide_preinit(void)\n{\n\tint num_disks_found = 0;\n\n\t/* Initialise records of which disks are present to all present */\n\tint i;\n\tfor (i = 0; i < CONFIG_SYS_IDE_MAXDEVICE; i++) {\n\t\tdisk_present[i] = 1;\n\t}\n\n\t/* Block reset SATA and DMA cores */\n\treset_block(SYS_CTRL_RST_SATA, 1);\n\treset_block(SYS_CTRL_RST_SATA_LINK, 1);\n\treset_block(SYS_CTRL_RST_SATA_PHY, 1);\n\treset_block(SYS_CTRL_RST_SGDMA, 1);\n\n\t/* Enable clocks to SATA and DMA cores */\n\tenable_clock(SYS_CTRL_CLK_SATA);\n\tenable_clock(SYS_CTRL_CLK_DMA);\n\n\tudelay(5000);\n\treset_block(SYS_CTRL_RST_SATA_PHY, 0);\n\tudelay(50);\n\treset_block(SYS_CTRL_RST_SATA, 0);\n\treset_block(SYS_CTRL_RST_SATA_LINK, 0);\n\tudelay(50);\n\treset_block(SYS_CTRL_RST_SGDMA, 0);\n\tudelay(100);\n\t/* Apply the Synopsis SATA PHY workarounds */\n\tworkaround5458();\n\tudelay(10000);\n\n\t/* disable and clear core interrupts */\n\t*((unsigned long*) SATA_HOST_REGS_BASE + SATA_INT_ENABLE_CLR_OFF) =\n\t\t~0UL;\n\t*((unsigned long*) SATA_HOST_REGS_BASE + SATA_INT_CLR_OFF) = ~0UL;\n\n\tint device;\n\tfor (device = 0; device < CONFIG_SYS_IDE_MAXDEVICE; device++) {\n\t\tint found = 0;\n\t\tint retries = 1;\n\n\t\t/* Disable SATA interrupts */\n\t\t*(sata_regs_base[device] + SATA_INT_ENABLE_CLR_OFF) = ~0UL;\n\n\t\t/* Clear any pending SATA interrupts */\n\t\t*(sata_regs_base[device] + SATA_INT_CLR_OFF) = ~0UL;\n\n\t\tdo {\n\t\t\t/* clear sector count register for FIS detection */\n\t\t\tide_outb(device, ATA_PORT_NSECT, 0);\n\n\t\t\t/* Get the PHY working */\n\t\t\tif (!phy_reset(device)) {\n\t\t\t\tprintf(\"SATA PHY not ready for device %d\\n\",\n\t\t\t\t\tdevice);\n\t\t\t\tbreak;\n\t\t\t}\n\n\t\t\tif (!wait_FIS(device)) {\n\t\t\t\tprintf(\"No FIS received from device %d\\n\",\n\t\t\t\t\tdevice);\n\t\t\t} else {\n\t\t\t\tif ((scr_read(device, SATA_SCR_STATUS) & 0xf)\n\t\t\t\t\t== 0x3) {\n\t\t\t\t\tif (wait_not_busy(device, 30)) {\n\t\t\t\t\t\tprintf(\"Timed out of wait for SATA device %d to have BUSY clear\\n\",\n\t\t\t\t\t\t\tdevice);\n\t\t\t\t\t} else {\n\t\t\t\t\t\t++num_disks_found;\n\t\t\t\t\t\tfound = 1;\n\t\t\t\t\t}\n\t\t\t\t} else {\n\t\t\t\t\tprintf(\"No SATA device %d found, PHY status = 0x%08x\\n\",\n\t\t\t\t\t\tdevice,\n\t\t\t\t\t\tscr_read(\n\t\t\t\t\t\t\tdevice,\n\t\t\t\t\t\t\tSATA_SCR_STATUS));\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\t}\n\t\t} while (retries--);\n\n\t\t/* Record whether disk is present, so won't attempt to access it later */\n\t\tdisk_present[device] = found;\n\t}\n\n\t/* post disk detection clean-up */\n\tfor (device = 0; device < CONFIG_SYS_IDE_MAXDEVICE; device++) {\n\t\tif (disk_present[device]) {\n\t\t\t/* set as ata-5 (28-bit) */\n\t\t\t*(sata_regs_base[device] + SATA_DRIVE_CONTROL_OFF) =\n\t\t\t\t0UL;\n\n\t\t\t/* clear phy/link errors */\n\t\t\tscr_write(device, SATA_SCR_ERROR, ~0);\n\n\t\t\t/* clear host errors */\n\t\t\t*(sata_regs_base[device] + SATA_CONTROL_OFF) |=\n\t\t\t\tSATA_SCTL_CLR_ERR;\n\n\t\t\t/* clear interrupt register as this clears the error bit in the IDE\n\t\t\t status register */\n\t\t\t*(sata_regs_base[device] + SATA_INT_CLR_OFF) = ~0UL;\n\t\t}\n\t}\n\n\treturn !num_disks_found;\n}\n\n"
  },
  {
    "path": "package/boot/uboot-oxnas/src/drivers/usb/host/ehci-oxnas.c",
    "content": "/*\n * drivers/usb/host/ehci-oxnas.c\n *\n * Tzachi Perelstein <tzachi@marvell.com>\n *\n * This file is licensed under  the terms of the GNU General Public\n * License version 2. This program is licensed \"as is\" without any\n * warranty of any kind, whether express or implied.\n */\n#include <common.h>\n#include <asm/arch/hardware.h>\n#include <asm/arch/sysctl.h>\n#include <asm/arch/clock.h>\n\n#include \"ehci.h\"\n\nstatic struct ehci_hcor *ghcor;\n\nstatic int start_oxnas_usb_ehci(void)\n{\n#ifdef CONFIG_USB_PLLB_CLK\n\treset_block(SYS_CTRL_RST_PLLB, 0);\n\tenable_clock(SYS_CTRL_CLK_REF600);\n\n\twritel((1 << PLLB_ENSAT) | (1 << PLLB_OUTDIV) | (2 << PLLB_REFDIV),\n\t\t\tSEC_CTRL_PLLB_CTRL0);\n\t/* 600MHz pllb divider for 12MHz */\n\twritel(PLLB_DIV_INT(50) | PLLB_DIV_FRAC(0), SEC_CTRL_PLLB_DIV_CTRL);\n#else\n\t/* ref 300 divider for 12MHz */\n\twritel(REF300_DIV_INT(25) | REF300_DIV_FRAC(0), SYS_CTRL_REF300_DIV);\n#endif\n\n\t/* Ensure the USB block is properly reset */\n\treset_block(SYS_CTRL_RST_USBHS, 1);\n\treset_block(SYS_CTRL_RST_USBHS, 0);\n\n\treset_block(SYS_CTRL_RST_USBHSPHYA, 1);\n\treset_block(SYS_CTRL_RST_USBHSPHYA, 0);\n\n\treset_block(SYS_CTRL_RST_USBHSPHYB, 1);\n\treset_block(SYS_CTRL_RST_USBHSPHYB, 0);\n\n\t/* Force the high speed clock to be generated all the time, via serial\n\t programming of the USB HS PHY */\n\twritel((2UL << USBHSPHY_TEST_ADD) |\n\t\t   (0xe0UL << USBHSPHY_TEST_DIN), SYS_CTRL_USBHSPHY_CTRL);\n\n\twritel((1UL << USBHSPHY_TEST_CLK) |\n\t\t   (2UL << USBHSPHY_TEST_ADD) |\n\t\t   (0xe0UL << USBHSPHY_TEST_DIN), SYS_CTRL_USBHSPHY_CTRL);\n\n\twritel((0xfUL << USBHSPHY_TEST_ADD) |\n\t\t   (0xaaUL << USBHSPHY_TEST_DIN), SYS_CTRL_USBHSPHY_CTRL);\n\n\twritel((1UL << USBHSPHY_TEST_CLK) |\n\t\t   (0xfUL << USBHSPHY_TEST_ADD) |\n\t\t   (0xaaUL << USBHSPHY_TEST_DIN), SYS_CTRL_USBHSPHY_CTRL);\n\n#ifdef CONFIG_USB_PLLB_CLK /* use pllb clock */\n\t\twritel(USB_CLK_INTERNAL | USB_INT_CLK_PLLB, SYS_CTRL_USB_CTRL);\n#else /* use ref300 derived clock */\n\t\twritel(USB_CLK_INTERNAL | USB_INT_CLK_REF300, SYS_CTRL_USB_CTRL);\n#endif\n\t/* Enable the clock to the USB block */\n\tenable_clock(SYS_CTRL_CLK_USBHS);\n\n\treturn 0;\n}\nint ehci_hcd_init(int index, enum usb_init_type init, struct ehci_hccr **hccr,\n\t\t  struct ehci_hcor **hcor)\n{\n\tstart_oxnas_usb_ehci();\n\t*hccr = (struct ehci_hccr *)(USB_HOST_BASE + 0x100);\n\t*hcor = (struct ehci_hcor *)((uint32_t)*hccr +\n\t\t\tHC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));\n\tghcor = *hcor;\n\treturn 0;\n}\n\nint ehci_hcd_stop(int index)\n{\n\treset_block(SYS_CTRL_RST_USBHS, 1);\n\tdisable_clock(SYS_CTRL_CLK_USBHS);\n\treturn 0;\n}\n\nextern void __ehci_set_usbmode(int index);\nvoid ehci_set_usbmode(int index)\n{\n\t#define  or_txttfill_tuning\t_reserved_1_[0]\n\tu32 tmp;\n\n\t__ehci_set_usbmode(index);\n\n\ttmp = ehci_readl(&ghcor->or_txfilltuning);\n\ttmp &= ~0x00ff0000;\n\ttmp |= 0x003f0000; /* set burst pre load count to 0x40 (63 * 4 bytes)  */\n\ttmp |= 0x16; /* set sheduler overhead to 22 * 1.267us (HS) or 22 * 6.33us (FS/LS)*/\n\tehci_writel(&ghcor->or_txfilltuning, tmp);\n\n\ttmp = ehci_readl(&ghcor->or_txttfill_tuning);\n\ttmp |= 0x2; /* set sheduler overhead to 2 * 6.333us */\n\tehci_writel(&ghcor->or_txttfill_tuning, tmp);\n}\n"
  },
  {
    "path": "package/boot/uboot-oxnas/src/include/configs/ox820.h",
    "content": "#ifndef __CONFIG_H\n#define __CONFIG_H\n\n/* High Level Configuration Options */\n#define CONFIG_ARM1136\n#define CONFIG_OX820\n#define CONFIG_SYS_GENERIC_BOARD\n#define CONFIG_BOARD_EARLY_INIT_F\n\n#include <asm/arch/cpu.h>\t/* get chip and board defs */\n\n/* make cmd_ide.c quiet when compile */\n#define __io\n\n/*#define CONFIG_ARCH_CPU_INIT*/\n/*#define CONFIG_DISPLAY_CPUINFO*/\n/*#define CONFIG_DISPLAY_BOARDINFO*/\n/*#define CONFIG_BOARD_EARLY_INIT_F*/\n/*#define CONFIG_SKIP_LOWLEVEL_INIT*/\n\n/* mem */\n#define CONFIG_SYS_SDRAM_BASE\t\t0x60000000\n#define CONFIG_NR_DRAM_BANKS\t\t1\n#define CONFIG_MIN_SDRAM_SIZE\t\t(128 * 1024 * 1024)\t/* 128 MB */\n#define CONFIG_MAX_SDRAM_SIZE\t\t(512 * 1024 * 1024)\t/* 512 MB */\n#define CONFIG_SRAM_BASE\t\t0x50000000\n#define CONFIG_SRAM_SIZE\t\t(64 * 1024)\n\n/* need do dma so better keep dcache off */\n#define CONFIG_SYS_DCACHE_OFF\n\n/* clock */\n#define CONFIG_PLLA_FREQ_MHZ\t\t800\n#define CONFIG_RPSCLK\t\t\t6250000\n#define CONFIG_SYS_HZ\t\t\t1000\n#define CONFIG_SYS_CLK_FREQ\t\tCONFIG_RPSCLK\n#define CONFIG_SYS_TIMERBASE\t\tTIMER1_BASE\n#define CONFIG_TIMER_PRESCALE\t\tTIMER_PRESCALE_16\n\n/* serial */\n#define CONFIG_SYS_NS16550\n#define CONFIG_SYS_NS16550_SERIAL\n#define CONFIG_SYS_NS16550_CLK\t\tCONFIG_RPSCLK\n#define CONFIG_SYS_NS16550_REG_SIZE\t1\n#define CONFIG_BAUDRATE\t\t\t115200\n#define CONFIG_SYS_NS16550_COM1\t\tUART_1_BASE\n#define CONFIG_CONS_INDEX\t\t1\n\n/* ide */\n#define CONFIG_SYS_ATA_BASE_ADDR\t0\n#define CONFIG_SYS_ATA_DATA_OFFSET\t0\n#define CONFIG_SYS_ATA_REG_OFFSET\t0\n#define CONFIG_SYS_ATA_ALT_OFFSET\t0\n#define CONFIG_IDE_PLX\n#define CONFIG_SYS_IDE_MAXDEVICE\t2\n#define CONFIG_SYS_IDE_MAXBUS\t\t1\n#define CONFIG_IDE_PREINIT\n#define CONFIG_LBA48\n\n/* nand */\n#define CONFIG_NAND\n#define CONFIG_SYS_MAX_NAND_DEVICE\t1\n#define CONFIG_SYS_NAND_BASE\t\tSTATIC_CS0_BASE\n#define NAND_CLE_ADDR_PIN\t\t19\n#define NAND_ALE_ADDR_PIN\t\t18\n#define MTDPARTS_DEFAULT\t\t\"mtdparts=41000000.nand:\" \\\n\t\t\t\t\t\t\"14m(boot),\" \\\n                                                \"-(ubi)\"\n#define MTDIDS_DEFAULT\t\t\t\"nand0=41000000.nand\"\n#define UBIPART_DEFAULT\t\t\t\"ubi\"\n\n/* net */\n#define CONFIG_DESIGNWARE_ETH\n#define CONFIG_DW_ALTDESCRIPTOR\n#define CONFIG_MII\n#define CONFIG_CMD_MII\n#define CONFIG_PHYLIB\n#define CONFIG_PHY_REALTEK\n#define CONFIG_PHY_ICPLUS\n\n/* spl */\n#ifdef CONFIG_SPL_BUILD\n#define USE_DL_PREFIX\t/* rename malloc free etc, so we can override them */\n#endif\n\n#if defined(CONFIG_BOOT_FROM_NAND) || defined(CONFIG_BOOT_FROM_SATA)\n#define CONFIG_SPL\n#define CONFIG_SPL_FRAMEWORK\n#define CONFIG_SPL_LIBCOMMON_SUPPORT\n#define CONFIG_SPL_SERIAL_SUPPORT\n#define CONFIG_SPL_LIBGENERIC_SUPPORT\n#define CONFIG_SPL_TEXT_BASE\t\t\t0x50000000\n#define CONFIG_SPL_STACK\t\t\t(CONFIG_SRAM_BASE + (48 * 1024))\n#define CONFIG_SPL_DISPLAY_PRINT\n#define CONFIG_SPL_BSS_DRAM_START\t\t\t0x65000000\n#define CONFIG_SPL_BSS_DRAM_SIZE\t\t\t0x01000000\n#define CONFIG_SPL_MALLOC_START\t\t\t\t0x66000000\n#endif\n\n#if defined(CONFIG_BOOT_FROM_NAND)\n#define CONFIG_SPL_NAND_SUPPORT\n#define BOOT_DEVICE_TYPE\t\t\t\"NAND\"\n#define BOOT_DEVICE_NAND\t\t\t0xfeedbacc\n#define CONFIG_SPL_BOOT_DEVICE\t\t\tBOOT_DEVICE_NAND\n#define CONFIG_SPL_NAND_SIMPLE\n#define CONFIG_SPL_NAND_ECC\n#define CONFIG_SPL_NAND_SOFTECC\n#define CONFIG_SYS_NAND_ECCSIZE\t\t\t512\n#define CONFIG_SYS_NAND_ECCBYTES\t\t6\n#define CONFIG_SYS_NAND_ECCPOS\t\t\t{40, 41, 42, 43, 44, 45, 46, 47, \\\n\t\t\t\t\t\t48, 49, 50, 51, 52, 53, 54, 55, \\\n\t\t\t\t\t\t56, 57, 58, 59, 60, 61, 62, 63}\n#define CONFIG_SYS_NAND_PAGE_SIZE\t\t2048\n#define CONFIG_SYS_NAND_OOBSIZE\t\t\t64\n#define CONFIG_SYS_NAND_BLOCK_SIZE\t\t(128 * 1024)\n#define CONFIG_SYS_NAND_BAD_BLOCK_POS\t\t0\n/* pages per erase block */\n#define CONFIG_SYS_NAND_PAGE_COUNT\t\t(CONFIG_SYS_NAND_BLOCK_SIZE / CONFIG_SYS_NAND_PAGE_SIZE)\n/* nand spl use 1 erase block, and use bit to byte encode for reliability */\n#define CONFIG_SPL_MAX_SIZE\t\t\t(128 * 1024 / 8)\n#define CONFIG_SYS_NAND_U_BOOT_OFFS\t\t0x00040000\n/* spl kernel load is not enabled */\n#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS\t\t0x00200000\n#define CONFIG_CMD_SPL_NAND_OFS\t\t\t0\n#define CONFIG_CMD_SPL_WRITE_SIZE\t\t1024\n#define CONFIG_SYS_SPL_ARGS_ADDR\t\t(CONFIG_SYS_SDRAM_BASE + 0x100)\n/* CONFIG_BOOT_FROM_NAND end */\n\n#elif defined(CONFIG_BOOT_FROM_SATA)\n#define CONFIG_SPL_BLOCK_SUPPORT\n#define BOOT_DEVICE_TYPE\t\t\t\t\"SATA\"\n#define BOOT_DEVICE_BLOCK\t\t\t\t860202\n#define CONFIG_SPL_BOOT_DEVICE\t\t\t\tBOOT_DEVICE_BLOCK\n#define CONFIG_SPL_MAX_SIZE\t\t\t\t(36 * 1024)\n#define CONFIG_SPL_LIBDISK_SUPPORT\n#define CONFIG_SPL_BLOCKDEV_INTERFACE\t\t\t\"ide\"\n#define CONFIG_SPL_BLOCKDEV_ID\t\t\t\t0\n\n#ifdef CONFIG_BOOT_FROM_FAT /* u-boot in fat partition */\n\n#define CONFIG_SPL_FAT_SUPPORT\n\n#define CONFIG_BLOCKDEV_FAT_BOOT_PARTITION\t\t1 /* first partition */\n#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME\t\t\"u-boot.img\" /* u-boot file name */\n/* enable U-Boot Falcon Mode */\n#define CONFIG_CMD_SPL\n#define CONFIG_SPL_OS_BOOT\n#define CONFIG_SPL_FAT_LOAD_ARGS_NAME\t\t\t\"bootargs.bin\" /* boot parameters */\n#define CONFIG_SPL_FAT_LOAD_KERNEL_NAME\t\t\t\"falcon.img\" /* kernel */\n#define CONFIG_SYS_SPL_ARGS_ADDR\t\t\t(CONFIG_SYS_SDRAM_BASE + 0x100)\n\n#elif CONFIG_BOOT_FROM_EXT4\n\n#define CONFIG_SPL_EXT4_SUPPORT\n#define CONFIG_BLOCKDEV_EXT4_BOOT_PARTITION\t\t1 /* first partition */\n#define CONFIG_SPL_EXT4_LOAD_PAYLOAD_NAME\t\t\"/boot/u-boot.img\" /* u-boot file name */\n/* enable U-Boot Falcon Mode */\n#define CONFIG_CMD_SPL\n#define CONFIG_SPL_OS_BOOT\n#define CONFIG_SPL_EXT4_LOAD_ARGS_NAME\t\t\t\"/boot/bootargs.bin\" /* boot parameters */\n#define CONFIG_SPL_EXT4_LOAD_KERNEL_NAME\t\t\"/boot/falcon.img\" /* kernel */\n#define CONFIG_SYS_SPL_ARGS_ADDR\t\t\t(CONFIG_SYS_SDRAM_BASE + 0x100)\n\n#else /* u-boot in raw sectors */\n\n#define CONFIG_SYS_BLOCK_RAW_MODE_U_BOOT_SECTOR\t\t1024\n/* spl kernel load is not enabled */\n#define CONFIG_SYS_BLOCK_RAW_MODE_KERNEL_SECTOR\t\t4096\n#define CONFIG_SYS_BLOCK_RAW_MODE_ARGS_SECTOR\t\t0\n#define CONFIG_SYS_BLOCK_RAW_MODE_ARGS_SECTORS\t\t(1024 / 512)\n#define CONFIG_SYS_SPL_ARGS_ADDR\t\t\t(CONFIG_SYS_SDRAM_BASE + 0x100)\n\n#endif /* CONFIG_BOOT_FROM_FAT */\n/* CONFIG_BOOT_FROM_SATA end */\n\n#else\n/* generic, no spl support */\n#endif\n\n/* boot */\n#define CONFIG_IDENT_STRING\t\t\" for OXNAS\"\n#define CONFIG_MACH_TYPE\t\tMACH_TYPE_OXNAS\n#ifndef CONFIG_SPL_BUILD\n/* Enable devicetree support */\n#define CONFIG_OF_LIBFDT\n#endif\n#define CONFIG_SETUP_MEMORY_TAGS\n#define CONFIG_CMDLINE_TAG\n#define CONFIG_INITRD_TAG\n#define CONFIG_BOOTDELAY\t\t1\n#define CONFIG_ZERO_BOOTDELAY_CHECK\n#define CONFIG_DEFAULT_CONSOLE_PARM\t\"console=ttyS0,115200n8 earlyprintk=serial\"\n/* Boot Argument Buffer Size */\n#define CONFIG_SYS_BARGSIZE\t\tCONFIG_SYS_CBSIZE\n/* memtest works on */\n#define CONFIG_SYS_LOAD_ADDR\t\t(CONFIG_SYS_SDRAM_BASE)\n#define CONFIG_SYS_AUTOLOAD\t\t\"no\"\n\n#define CONFIG_DEFAULT_CONSOLE\t\tCONFIG_DEFAULT_CONSOLE_PARM \"\\0\"\n#define CONFIG_BOOTARGS\t\t\tCONFIG_DEFAULT_CONSOLE_PARM\n#define CONFIG_BOOTCOMMAND\t\t\"run nandboot\"\n#define CONFIG_BOOT_RETRY_TIME\t\t-1\n#define CONFIG_RESET_TO_RETRY\t\t60\n\n#define CONFIG_NETCONSOLE\n#define CONFIG_IPADDR\t\t\t192.168.50.100\n#define CONFIG_SERVERIP\t\t\t192.168.50.59\n\n/* A sane default configuration...\n * When booting without a valid environment in ubi, first to loading and booting\n * the kernel image directly above U-Boot, maybe both were loaded there by\n * another bootloader.\n * Also use that same offset (0x90000) to load the rescue image later on (by\n * adding it onto the flash address where U-Boot is supposed to be stored by\n * the legacy loader, 0x440000, resulting in offset 0x4d0000 on the flash).\n * When coming up with a valid environment in ubi, first try to load the\n * kernel from a ubi volume kernel, if that fails, fallback to the rescue\n * image stored in boot partition. As a last resort try booting via\n * DHCP/TFTP.\n * In case there is no valid environment, first probe for a uimage in ram left\n * behind by the first bootloader on a tftp boot.\n * If that fails, switch to normal boot order and save environment.\n * The loader is supposed to be written to flash at offset 0x440000 and loaded to\n * RAM at 0x64000000\n */\n#define CONFIG_EXTRA_ENV_SETTINGS\t\\\n\t\"load_kernel_ubi=ubi readvol 0x62000000 kernel;\\0\" \\\n\t\"load_kernel_rescue=nand read 0x62000000 0x4e0000 0x400000;\\0\" \\\n\t\"load_kernel_dhcp=dhcp 0x62000000 oxnas-rescue.bin;\\0\" \\\n\t\"boot_kernel=bootm 0x62000000;\\0\" \\\n\t\"boot_ubi=run load_kernel_ubi && run boot_kernel;\\0\" \\\n\t\"boot_rescue=run load_kernel_rescue && run boot_kernel;\\0\" \\\n\t\"boot_dhcp=run load_kernel_dhcp && run boot_kernel;\\0\" \\\n\t\"normalboot=run boot_ubi; run boot_rescue; run boot_dhcp;\\0\" \\\n\t\"firstboot=bootm 0x640a0000; setenv bootcmd run normalboot; \" \\\n\t\"setenv firstboot; saveenv; run bootcmd; \\0\" \\\n\t\"bootcmd=run firstboot; \\0\" \\\n\t\"console=\" CONFIG_DEFAULT_CONSOLE \\\n\t\"bootargs=\" CONFIG_BOOTARGS \"\\0\" \\\n\t\"mtdids=\" MTDIDS_DEFAULT \"\\0\" \\\n\t\"mtdparts=\" MTDPARTS_DEFAULT \"\\0\" \\\n\n/* env */\n#if defined(CONFIG_BOOT_FROM_NAND)\n#define CONFIG_ENV_IS_IN_NAND\n#define CONFIG_ENV_OFFSET\t\t0x000C0000\n#define CONFIG_ENV_SIZE\t\t\t0x00020000\n#define CONFIG_ENV_OFFSET_REDUND\t0x00100000\n#define CONFIG_ENV_SIZE_REDUND\t\t0x00020000\n#define CONFIG_ENV_RANGE\t\t(CONFIG_ENV_SIZE * 2)\n/* CONFIG_BOOT_FROM_NAND end */\n\n#elif defined(CONFIG_BOOT_FROM_SATA)\n#ifdef CONFIG_BOOT_FROM_EXT4\n#define CONFIG_ENV_IS_IN_EXT4\n#define CONFIG_START_IDE\n#define EXT4_ENV_INTERFACE \t\t\"ide\"\n#define EXT4_ENV_DEVICE\t\t\t0\n#define EXT4_ENV_PART\t\t\t1\n#define EXT4_ENV_FILE\t\t\t\"/boot/u-boot.env\"\n#define CONFIG_ENV_SIZE\t\t\t(16 * 1024)\n#else\n#define CONFIG_ENV_IS_IN_FAT\n#define CONFIG_START_IDE\n#define FAT_ENV_INTERFACE \t\t\"ide\"\n#define FAT_ENV_DEVICE\t\t\t0\n#define FAT_ENV_PART\t\t\t1\n#define FAT_ENV_FILE\t\t\t\"u-boot.env\"\n#define CONFIG_ENV_SIZE\t\t\t(16 * 1024)\n#endif\n/* CONFIG_BOOT_FROM_SATA end */\n#elif defined(CONFIG_BOOT_FROM_SATA)\n\n#else\n/* generic */\n#define CONFIG_ENV_IS_IN_UBI\t\t1\n#define CONFIG_ENV_UBI_PART\t\tUBIPART_DEFAULT\n#define CONFIG_ENV_UBI_VOLUME\t\t\"ubootenv\"\n#define CONFIG_ENV_UBI_VOLUME_REDUND\t\"ubootenv2\"\n#define CONFIG_ENV_SIZE\t\t\t(16 * 1024)\n#endif\n\n/* allow to overwrite serial and ethaddr */\n#define CONFIG_ENV_OVERWRITE\n\n#define CONFIG_SYS_MONITOR_LEN\t\t(512 * 1024)\n#define CONFIG_SYS_TEXT_BASE\t\t0x64000000\n#define CONFIG_SYS_INIT_SP_ADDR\t\t0x65000000\n/* Size of malloc() pool */\n#define CONFIG_SYS_MALLOC_LEN\t\t(1 * 1024 * 1024)\n\n/* Miscellaneous configurable options */\n#define CONFIG_SYS_LONGHELP\t\t/* undef to save memory */\n#define CONFIG_SYS_HUSH_PARSER\t\t/* use \"hush\" command parser\t*/\n#define CONFIG_SYS_PROMPT\t\t\"OX820 # \"\n#define CONFIG_SYS_CBSIZE\t\t1024\t/* Console I/O Buffer Size*/\n#define CONFIG_SYS_PBSIZE\t\t1024\t/* Print Buffer Size */\n#define CONFIG_SYS_MAXARGS\t\t32\t/* max number of command args */\n#define CONFIG_CMDLINE_EDITING\n#define CONFIG_AUTO_COMPLETE\n\n/* usb */\n#define CONFIG_USB_MAX_CONTROLLER_COUNT\t1\n#define CONFIG_USB_EHCI\n#define CONFIG_EHCI_IS_TDI\n/* #define CONFIG_USB_EHCI_TXFIFO_THRESH\t0x3F */\n#define CONFIG_USB_PLLB_CLK\n#define CONFIG_USB_EHCI_OXNAS\n#ifndef CONFIG_SPL_BUILD\n#define CONFIG_USB_STORAGE\n#endif\n#define CONFIG_CMD_USB\n\n/* cmds */\n#define CONFIG_SYS_NO_FLASH\n#include <config_cmd_default.h>\n\n#define CONFIG_CMD_SAVEENV\n#define CONFIG_CMD_ASKENV\n#define CONFIG_CMD_GREPENV\n#define CONFIG_CMD_ENV_FLAGS\n\n#define CONFIG_CMD_NET\n#define CONFIG_CMD_DHCP\n#define CONFIG_CMD_NFS\n#define CONFIG_CMD_PING\n#define CONFIG_CMD_PXE\n\n#define CONFIG_CMD_NAND\n#define CONFIG_CMD_MTDPARTS\n#define CONFIG_CMD_UBI\n#define CONFIG_CMD_UBIFS\n\n#define CONFIG_CMD_IDE\n#define CONFIG_CMD_FAT\n#define CONFIG_FAT_WRITE\n#define CONFIG_CMD_EXT2\n#define CONFIG_CMD_EXT4\n#ifndef CONFIG_SPL_BUILD\n#define CONFIG_CMD_EXT4_WRITE\n#endif\n\n#define CONFIG_CMD_ZIP\n#define CONFIG_CMD_UNZIP\n#define CONFIG_CMD_TIME\n#define CONFIG_CMD_SETEXPR\n#define CONFIG_CMD_MD5SUM\n#define CONFIG_CMD_HASH\n#define CONFIG_CMD_INI\n#define CONFIG_CMD_GETTIME\n#define CONFIG_CMD_BOOTMENU\n#define CONFIG_CMD_ELF\n#define CONFIG_CMD_BOOTZ\n\n#define CONFIG_DOS_PARTITION\n#define CONFIG_EFI_PARTITION\n\n/* for CONFIG_CMD_MTDPARTS */\n#define CONFIG_MTD_DEVICE\n/* for CONFIG_CMD_UBI */\n#define CONFIG_MTD_PARTITIONS\n/* for CONFIG_CMD_UBI */\n#define CONFIG_RBTREE\n\n/* optional, for CONFIG_CMD_BOOTM & required by CONFIG_CMD_UBIFS */\n#define CONFIG_LZO\n#define CONFIG_LZMA\n#define CONFIG_BZIP2\n\n/* for CONFIG_CMD_ZIP */\n#define CONFIG_GZIP_COMPRESSED\n/* for CONFIG_CMD_MD5SUM */\n#define CONFIG_MD5\n#define CONFIG_MD5SUM_VERIFY\n/* enable CONFIG_CMD_HASH's verification feature */\n#define CONFIG_HASH_VERIFY\n#define CONFIG_REGEX\n/* for CONFIG_CMD_BOOTMENU & CONFIG_CMD_PXE */\n#define CONFIG_MENU\n\n/* for new FIT uImage format generated in OpenWrt */\n#define CONFIG_FIT\n\n#endif\t/* __CONFIG_H */\n"
  },
  {
    "path": "package/boot/uboot-oxnas/src/tools/mkox820crc.c",
    "content": "/* J J Larworthy 27 September 2006 */\n\n/* file to read the boot sector of a dis and the loaded image and report\n * if the boot rom would accept the data as intact and suitable for use\n */\n\n#include <sys/types.h>\n#include <sys/stat.h>\n#include <sys/errno.h>\n\n#include <fcntl.h>\n#include <unistd.h>\n#include <stdio.h>\n#include <stdlib.h>\n#include <string.h>\n#include <assert.h>\n\nextern uint32_t crc32(uint32_t, const unsigned char *, unsigned int);\n\n#define NUMBER_VECTORS   12\nstruct {\n\tunsigned int start_vector[NUMBER_VECTORS];\n\tchar code[4];\n\tunsigned int header_length;\n\tunsigned int reserved[3];\n\tunsigned int length;\n\tunsigned int img_CRC;\n\tunsigned int CRC;\n} img_header;\n\nvoid print_usage(void)\n{\n\tprintf(\"update_header file.bin\\n\");\n}\n\nvoid print_header(void)\n{\n\tint i;\n\n\tprintf(\"vectors in header\\n\");\n\tfor (i = 0; i < NUMBER_VECTORS; i++) {\n\t\tprintf(\"%d:0x%08x\\n\", i, img_header.start_vector[i]);\n\t}\n\tprintf(\"length:%8x\\nimg_CRC:0x%08x\\nHeader CRC:0x%08x\\n\",\n\t\timg_header.length, img_header.img_CRC, img_header.CRC);\n}\n\nint main(int argc, char **argv)\n{\n\tint in_file;\n\tint status;\n\tint unsigned crc;\n\tint file_length;\n\tint len;\n\n\tstruct stat file_stat;\n\n\tvoid *executable;\n\n\tin_file = open(argv[1], O_RDWR);\n\n\tif (in_file < 0) {\n\t\tprintf(\"failed to open file:%s\\n\", argv[optind]);\n\t\treturn -ENOENT;\n\t}\n\n\tstatus = fstat(in_file, &file_stat);\n\n\t/* read header and obtain size of image */\n\tstatus = read(in_file, &img_header, sizeof(img_header));\n\n\tfile_length = file_stat.st_size - sizeof(img_header);\n\n\tif (img_header.length != file_length) {\n\t\tprintf(\"size in header:%d, size of file: %d\\n\",\n\t\t\timg_header.length, file_length);\n\t}\n\timg_header.length = file_length;\n\n\t/* read working image and CRC */\n\texecutable = malloc(file_length);\n\n\tstatus = read(in_file, executable, file_length);\n\n\tif (status != file_length) {\n\t\tprintf(\"Failed to load image\\n\");\n\t\tfree(executable);\n\t\treturn -ENOENT;\n\t}\n\n\t/* verify image CRC */\n\tcrc = crc32(0, (const unsigned char *) executable, img_header.length);\n\n\tif (crc != img_header.img_CRC) {\n\t\tprintf(\"New Image CRC:0x%08x, hdr:0x%08x\\n\", crc,\n\t\t\timg_header.img_CRC);\n\t\timg_header.img_CRC = crc;\n\t}\n\tmemcpy(img_header.code, \"BOOT\", 4);\n\timg_header.header_length = sizeof(img_header);\n\n\t/* check header CRC */\n\tcrc = crc32(0, (const unsigned char *) &img_header,\n\t\t\tsizeof(img_header) - sizeof(unsigned int));\n\tif (crc != img_header.CRC) {\n\t\tprintf(\"New header CRC - crc:0x%08x hdr:0x%08x\\n\", crc,\n\t\t\timg_header.CRC);\n\t\timg_header.CRC = crc;\n\t}\n\n\t/* re-write the file */\n\tstatus = lseek(in_file, 0, SEEK_SET);\n\tif (status != 0) {\n\t\tprintf(\"failed to rewind\\n\");\n\t\tfree(executable);\n\t\treturn 1;\n\t}\n\tlen = write(in_file, &img_header, sizeof(img_header));\n\tassert(len == sizeof(img_header));\n\tlen = write(in_file, executable, file_length);\n\tassert(len == file_length);\n\tclose(in_file);\n\tfree(executable);\n\n\treturn 0;\n}\n"
  },
  {
    "path": "package/boot/uboot-ramips/Makefile",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n\ninclude $(TOPDIR)/rules.mk\ninclude $(INCLUDE_DIR)/kernel.mk\n\nPKG_VERSION:=2020.04\nPKG_RELEASE:=$(AUTORELEASE)\n\nPKG_HASH:=fe732aaf037d9cc3c0909bad8362af366ae964bbdac6913a34081ff4ad565372\n\ninclude $(INCLUDE_DIR)/u-boot.mk\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine U-Boot/Default\n  BUILD_TARGET:=ramips\n  UBOOT_IMAGE:=u-boot.bin\nendef\n\ndefine U-Boot/ravpower_rp-wd009\n  BUILD_DEVICES:=ravpower_rp-wd009\n  BUILD_SUBTARGET:=mt76x8\n  NAME:=RAVPower RP-WD009\n  UBOOT_CONFIG:=ravpower-rp-wd009-ram\nendef\n\nUBOOT_TARGETS := \\\n\travpower_rp-wd009\n\ndefine Build/InstallDev\n\t$(INSTALL_DIR) $(STAGING_DIR_IMAGE)\n\t$(INSTALL_BIN) $(PKG_BUILD_DIR)/$(UBOOT_IMAGE) $(STAGING_DIR_IMAGE)/$(VARIANT)-$(UBOOT_IMAGE)\nendef\n\n$(eval $(call BuildPackage/U-Boot))\n"
  },
  {
    "path": "package/boot/uboot-ramips/patches/0001-add-support-for-RAVPower-RP-WD009.patch",
    "content": "From 593db38363297247df731566c2aa307a5d795005 Mon Sep 17 00:00:00 2001\nFrom: David Bauer <mail@david-bauer.net>\nDate: Thu, 18 Jun 2020 00:13:11 +0200\nSubject: [PATCH] add support for RAVPower RP-WD009\n\n---\n arch/mips/dts/Makefile                  |  3 +-\n arch/mips/dts/ravpower-rp-wd009.dts     | 50 +++++++++++++++++++++\n arch/mips/mach-mtmips/Kconfig           |  9 ++++\n board/ravpower/rp-wd009/Kconfig         | 12 +++++\n board/ravpower/rp-wd009/Makefile        |  3 ++\n board/ravpower/rp-wd009/board.c         | 16 +++++++\n configs/ravpower-rp-wd009-ram_defconfig | 59 +++++++++++++++++++++++++\n include/configs/ravpower-rp-wd009.h     | 48 ++++++++++++++++++++\n 8 files changed, 199 insertions(+), 1 deletion(-)\n create mode 100644 arch/mips/dts/ravpower-rp-wd009.dts\n create mode 100644 board/ravpower/rp-wd009/Kconfig\n create mode 100644 board/ravpower/rp-wd009/Makefile\n create mode 100644 board/ravpower/rp-wd009/board.c\n create mode 100644 configs/ravpower-rp-wd009-ram_defconfig\n create mode 100644 include/configs/ravpower-rp-wd009.h\n\ndiff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile\nindex c9d75596f2..23868ae1d2 100644\n--- a/arch/mips/dts/Makefile\n+++ b/arch/mips/dts/Makefile\n@@ -2,7 +2,8 @@\n \n dtb-$(CONFIG_ARCH_MTMIPS) += \\\n \tgardena-smart-gateway-mt7688.dtb \\\n-\tlinkit-smart-7688.dtb\n+\tlinkit-smart-7688.dtb \\\n+\travpower-rp-wd009.dtb\n dtb-$(CONFIG_TARGET_AP121) += ap121.dtb\n dtb-$(CONFIG_TARGET_AP143) += ap143.dtb\n dtb-$(CONFIG_TARGET_AP152) += ap152.dtb\ndiff --git a/arch/mips/dts/ravpower-rp-wd009.dts b/arch/mips/dts/ravpower-rp-wd009.dts\nnew file mode 100644\nindex 0000000000..b271d5bfbc\n--- /dev/null\n+++ b/arch/mips/dts/ravpower-rp-wd009.dts\n@@ -0,0 +1,50 @@\n+// SPDX-License-Identifier: GPL-2.0\n+/*\n+ * Copyright (C) 2018 Stefan Roese <sr@denx.de>\n+ */\n+\n+/dts-v1/;\n+\n+#include \"mt7628a.dtsi\"\n+#include <dt-bindings/gpio/gpio.h>\n+\n+/ {\n+\tcompatible = \"ravpower,rp-wd009\", \"ralink,mt7628a-soc\";\n+\tmodel = \"RAVPower RP-WD009\";\n+\n+\taliases {\n+\t\tserial0 = &uart0;\n+\t\tspi0 = &spi0;\n+\t};\n+\n+\tmemory@0 {\n+\t\tdevice_type = \"memory\";\n+\t\treg = <0x0 0x4000000>;\n+\t};\n+\n+\tchosen {\n+\t\tstdout-path = \"serial0:115200n8\";\n+\t};\n+};\n+\n+&uart0 {\n+\tstatus = \"okay\";\n+};\n+\n+&spi0 {\n+\tstatus = \"okay\";\n+\tnum-cs = <2>;\n+\n+\tspi-flash@0 {\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <1>;\n+\t\tcompatible = \"jedec,spi-nor\";\n+\t\tspi-max-frequency = <40000000>;\n+\t\treg = <0>;\n+\t};\n+};\n+\n+&eth {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&ephy_router_mode>;\n+};\ndiff --git a/arch/mips/mach-mtmips/Kconfig b/arch/mips/mach-mtmips/Kconfig\nindex c8dcf19c0d..85ac8878ab 100644\n--- a/arch/mips/mach-mtmips/Kconfig\n+++ b/arch/mips/mach-mtmips/Kconfig\n@@ -32,6 +32,14 @@ config BOARD_GARDENA_SMART_GATEWAY_MT7688\n \t  GARDENA smart Gateway boards have a MT7688 SoC with 128 MiB of RAM\n \t  and 8 MiB of flash (SPI NOR) and additional SPI NAND storage.\n \n+config BOARD_RAVPOWER_RP_WD009\n+\tbool \"RAVPower RP-WD009\"\n+\tdepends on SOC_MT7628\n+\tselect BOARD_LATE_INIT\n+\tselect SUPPORTS_BOOT_RAM\n+\thelp\n+\t  RAVPower RP-WD009\n+\n config BOARD_LINKIT_SMART_7688\n \tbool \"LinkIt Smart 7688\"\n \tdepends on SOC_MT7628\n@@ -133,6 +141,7 @@ config SUPPORTS_BOOT_RAM\n \tbool\n \n source \"board/gardena/smart-gateway-mt7688/Kconfig\"\n+source \"board/ravpower/rp-wd009/Kconfig\"\n source \"board/seeed/linkit-smart-7688/Kconfig\"\n \n endmenu\ndiff --git a/board/ravpower/rp-wd009/Kconfig b/board/ravpower/rp-wd009/Kconfig\nnew file mode 100644\nindex 0000000000..111f8e4478\n--- /dev/null\n+++ b/board/ravpower/rp-wd009/Kconfig\n@@ -0,0 +1,12 @@\n+if BOARD_RAVPOWER_RP_WD009\n+\n+config SYS_BOARD\n+\tdefault \"rp-wd009\"\n+\n+config SYS_VENDOR\n+\tdefault \"ravpower\"\n+\n+config SYS_CONFIG_NAME\n+\tdefault \"ravpower-rp-wd009\"\n+\n+endif\ndiff --git a/board/ravpower/rp-wd009/Makefile b/board/ravpower/rp-wd009/Makefile\nnew file mode 100644\nindex 0000000000..70cd7a8e56\n--- /dev/null\n+++ b/board/ravpower/rp-wd009/Makefile\n@@ -0,0 +1,3 @@\n+# SPDX-License-Identifier: GPL-2.0+\n+\n+obj-y += board.o\ndiff --git a/board/ravpower/rp-wd009/board.c b/board/ravpower/rp-wd009/board.c\nnew file mode 100644\nindex 0000000000..eabcf85735\n--- /dev/null\n+++ b/board/ravpower/rp-wd009/board.c\n@@ -0,0 +1,16 @@\n+// SPDX-License-Identifier: GPL-2.0+\n+/*\n+ * Copyright (C) 2018 Stefan Roese <sr@denx.de>\n+ */\n+\n+\n+int board_early_init_f(void)\n+{\n+\treturn 0;\n+}\n+\n+\n+int board_late_init(void)\n+{\n+\treturn 0;\n+}\ndiff --git a/configs/ravpower-rp-wd009-ram_defconfig b/configs/ravpower-rp-wd009-ram_defconfig\nnew file mode 100644\nindex 0000000000..08cbf40638\n--- /dev/null\n+++ b/configs/ravpower-rp-wd009-ram_defconfig\n@@ -0,0 +1,59 @@\n+CONFIG_MIPS=y\n+CONFIG_SYS_TEXT_BASE=0x80010000\n+CONFIG_NR_DRAM_BANKS=1\n+CONFIG_ARCH_MTMIPS=y\n+CONFIG_MIPS_BOOT_FDT=y\n+CONFIG_LEGACY_IMAGE_FORMAT=y\n+CONFIG_OF_STDOUT_VIA_ALIAS=y\n+CONFIG_USE_BOOTCOMMAND=y\n+CONFIG_BOOTCOMMAND=\"sf probe && mtd read firmware 82000000 && bootm 82000000\"\n+CONFIG_USE_PREBOOT=y\n+CONFIG_SYS_CONSOLE_INFO_QUIET=y\n+CONFIG_VERSION_VARIABLE=y\n+CONFIG_BOARD_RAVPOWER_RP_WD009=y\n+CONFIG_BOARD_EARLY_INIT_F=y\n+CONFIG_HUSH_PARSER=y\n+CONFIG_CMD_LICENSE=y\n+# CONFIG_CMD_ELF is not set\n+# CONFIG_CMD_XIMG is not set\n+CONFIG_CMD_MEMINFO=y\n+# CONFIG_CMD_FLASH is not set\n+CONFIG_CMD_GPIO=y\n+# CONFIG_CMD_LOADS is not set\n+CONFIG_CMD_MTD=y\n+CONFIG_CMD_SPI=y\n+CONFIG_CMD_WDT=y\n+CONFIG_CMD_DHCP=y\n+CONFIG_CMD_MII=y\n+CONFIG_CMD_PING=y\n+CONFIG_CMD_TIME=y\n+CONFIG_CMD_UUID=y\n+CONFIG_CMD_MTDPARTS=y\n+CONFIG_MTDIDS_DEFAULT=\"nor0=spi0.0\"\n+CONFIG_MTDPARTS_DEFAULT=\"spi0.0:192k(factory-uboot),64k(config),64k(factory),1536k(loader),64k(params),64k(user_backup),64k(user),14272k(firmware),64k(mode)\"\n+CONFIG_DEFAULT_DEVICE_TREE=\"ravpower-rp-wd009\"\n+CONFIG_NET_RANDOM_ETHADDR=y\n+# CONFIG_DM_DEVICE_REMOVE is not set\n+CONFIG_HAVE_BLOCK_DEVICE=y\n+CONFIG_LED=y\n+CONFIG_LED_BLINK=y\n+CONFIG_LED_GPIO=y\n+CONFIG_MTD=y\n+CONFIG_DM_MTD=y\n+CONFIG_SPI_FLASH_GIGADEVICE=y\n+CONFIG_SPI_FLASH_MACRONIX=y\n+CONFIG_SPI_FLASH_SPANSION=y\n+CONFIG_SPI_FLASH_STMICRO=y\n+CONFIG_SPI_FLASH_WINBOND=y\n+CONFIG_SPI_FLASH_XMC=y\n+CONFIG_SPI_FLASH_MTD=y\n+CONFIG_MTD_UBI_BEB_LIMIT=22\n+CONFIG_MT7628_ETH=y\n+CONFIG_PHY=y\n+CONFIG_SPI=y\n+CONFIG_MT7621_SPI=y\n+CONFIG_SYSRESET_SYSCON=y\n+CONFIG_WDT=y\n+CONFIG_WDT_MT7621=y\n+CONFIG_LZMA=y\n+CONFIG_BAUDRATE=57600\ndiff --git a/include/configs/ravpower-rp-wd009.h b/include/configs/ravpower-rp-wd009.h\nnew file mode 100644\nindex 0000000000..bb4145197c\n--- /dev/null\n+++ b/include/configs/ravpower-rp-wd009.h\n@@ -0,0 +1,48 @@\n+/* SPDX-License-Identifier: GPL-2.0+ */\n+/*\n+ * Copyright (C) 2018 Stefan Roese <sr@denx.de>\n+ */\n+\n+#ifndef __CONFIG_RAVPOWER_RP_WD009_H\n+#define __CONFIG_RAVPOWER_RP_WD009_H\n+\n+/* CPU */\n+#define CONFIG_SYS_MIPS_TIMER_FREQ\t290000000\n+\n+/* RAM */\n+#define CONFIG_SYS_SDRAM_BASE\t\t0x80000000\n+\n+#define CONFIG_SYS_LOAD_ADDR\t\tCONFIG_SYS_SDRAM_BASE + 0x100000\n+\n+#define CONFIG_SYS_INIT_SP_OFFSET\t0x400000\n+\n+#ifdef CONFIG_BOOT_RAM\n+#define CONFIG_SKIP_LOWLEVEL_INIT\n+#endif\n+\n+/* UART */\n+#define CONFIG_SYS_BAUDRATE_TABLE\t{ 9600, 19200, 38400, 57600, 115200, \\\n+\t\t\t\t\t  230400, 460800, 921600 }\n+\n+/* RAM */\n+#define CONFIG_SYS_MEMTEST_START\t0x80100000\n+#define CONFIG_SYS_MEMTEST_END\t\t0x80400000\n+\n+/* Memory usage */\n+#define CONFIG_SYS_MAXARGS\t\t64\n+#define CONFIG_SYS_MALLOC_LEN\t\t(16 * 1024 * 1024)\n+#define CONFIG_SYS_BOOTPARAMS_LEN\t(128 * 1024)\n+#define CONFIG_SYS_CBSIZE\t\t512\n+\n+/* U-Boot */\n+#define CONFIG_SYS_MONITOR_BASE\t\tCONFIG_SYS_TEXT_BASE\n+\n+/* Environment settings */\n+\n+/*\n+ * Environment is right behind U-Boot in flash. Make sure U-Boot\n+ * doesn't grow into the environment area.\n+ */\n+#define CONFIG_BOARD_SIZE_LIMIT\t\tCONFIG_ENV_OFFSET\n+\n+#endif /* __CONFIG_RAVPOWER_RP_WD009_H */\n-- \n2.27.0\n\n"
  },
  {
    "path": "package/boot/uboot-rockchip/Makefile",
    "content": "#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\ninclude $(TOPDIR)/rules.mk\ninclude $(INCLUDE_DIR)/kernel.mk\n\nPKG_VERSION:=2021.07\nPKG_RELEASE:=$(AUTORELEASE)\n\nPKG_HASH:=312b7eeae44581d1362c3a3f02c28d806647756c82ba8c72241c7cdbe68ba77e\n\nPKG_MAINTAINER:=Tobias Maedel <openwrt@tbspace.de>\n\ninclude $(INCLUDE_DIR)/u-boot.mk\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine U-Boot/Default\n  BUILD_TARGET:=rockchip\n  UENV:=default\n  HIDDEN:=1\nendef\n\n\n# RK3328 boards\n\ndefine U-Boot/orangepi-r1-plus-rk3328\n  BUILD_SUBTARGET:=armv8\n  NAME:=OrangePi R1 Plus\n  BUILD_DEVICES:= \\\n    xunlong_orangepi-r1-plus\n  DEPENDS:=+PACKAGE_u-boot-orangepi-r1-plus-rk3328:arm-trusted-firmware-rk3328\n  PKG_BUILD_DEPENDS:=arm-trusted-firmware-rk3328\n  ATF:=rk322xh_bl31_v1.46.elf\n  OF_PLATDATA:=$(1)\n  USE_RKBIN:=1\nendef\n\ndefine U-Boot/orangepi-r1-plus-lts-rk3328\n  BUILD_SUBTARGET:=armv8\n  NAME:=OrangePi R1 Plus LTS\n  BUILD_DEVICES:= \\\n    xunlong_orangepi-r1-plus-lts\n  DEPENDS:=+PACKAGE_u-boot-orangepi-r1-plus-lts-rk3328:arm-trusted-firmware-rk3328\n  PKG_BUILD_DEPENDS:=arm-trusted-firmware-rk3328\n  ATF:=rk322xh_bl31_v1.46.elf\n  OF_PLATDATA:=$(1)\n  USE_RKBIN:=1\nendef\n\ndefine U-Boot/nanopi-r2s-rk3328\n  BUILD_SUBTARGET:=armv8\n  NAME:=NanoPi R2S\n  BUILD_DEVICES:= \\\n    friendlyarm_nanopi-r2s\n  DEPENDS:=+PACKAGE_u-boot-nanopi-r2s-rk3328:arm-trusted-firmware-rk3328\n  PKG_BUILD_DEPENDS:=arm-trusted-firmware-rk3328\n  ATF:=rk322xh_bl31_v1.46.elf\n  OF_PLATDATA:=$(1)\n  USE_RKBIN:=1\nendef\n\n\n# RK3399 boards\n\ndefine U-Boot/nanopi-r4s-rk3399\n  BUILD_SUBTARGET:=armv8\n  NAME:=NanoPi R4S\n  BUILD_DEVICES:= \\\n    friendlyarm_nanopi-r4s\n  DEPENDS:=+PACKAGE_u-boot-nanopi-r4s-rk3399:arm-trusted-firmware-rockchip\n  PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip\n  ATF:=rk3399_bl31.elf\nendef\n\ndefine U-Boot/rock-pi-4-rk3399\n  BUILD_SUBTARGET:=armv8\n  NAME:=Rock Pi 4\n  BUILD_DEVICES:= \\\n    radxa_rock-pi-4a\n  DEPENDS:=+PACKAGE_u-boot-rock-pi-4-rk3399:arm-trusted-firmware-rockchip\n  PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip\n  ATF:=rk3399_bl31.elf\nendef\n\ndefine U-Boot/rockpro64-rk3399\n  BUILD_SUBTARGET:=armv8\n  NAME:=RockPro64\n  BUILD_DEVICES:= \\\n    pine64_rockpro64\n  DEPENDS:=+PACKAGE_u-boot-rockpro64-rk3399:arm-trusted-firmware-rockchip\n  PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip\n  ATF:=rk3399_bl31.elf\nendef\n\nUBOOT_TARGETS := \\\n  nanopi-r4s-rk3399 \\\n  rock-pi-4-rk3399 \\\n  rockpro64-rk3399 \\\n  nanopi-r2s-rk3328 \\\n  orangepi-r1-plus-rk3328 \\\n  orangepi-r1-plus-lts-rk3328\n\nUBOOT_CONFIGURE_VARS += USE_PRIVATE_LIBGCC=yes\n\nUBOOT_MAKE_FLAGS += \\\n  BL31=$(STAGING_DIR_IMAGE)/$(ATF)\n\ndefine Build/Configure\n\t$(call Build/Configure/U-Boot)\n\nifneq ($(OF_PLATDATA),)\n\tmkdir -p $(PKG_BUILD_DIR)/tpl/dts\n\tmkdir -p $(PKG_BUILD_DIR)/include/generated\n\n\t$(CP) $(PKG_BUILD_DIR)/of-platdata/$(OF_PLATDATA)/dt-plat.c $(PKG_BUILD_DIR)/tpl/dts/dt-plat.c\n\t$(CP) $(PKG_BUILD_DIR)/of-platdata/$(OF_PLATDATA)/dt-structs-gen.h $(PKG_BUILD_DIR)/include/generated/dt-structs-gen.h\n\t$(CP) $(PKG_BUILD_DIR)/of-platdata/$(OF_PLATDATA)/dt-decl.h $(PKG_BUILD_DIR)/include/generated/dt-decl.h\nendif\n\n\t$(SED) 's#CONFIG_MKIMAGE_DTC_PATH=.*#CONFIG_MKIMAGE_DTC_PATH=\"$(PKG_BUILD_DIR)/scripts/dtc/dtc\"#g' $(PKG_BUILD_DIR)/.config\n\techo 'CONFIG_IDENT_STRING=\" OpenWrt\"' >> $(PKG_BUILD_DIR)/.config\nendef\n\ndefine Build/InstallDev\n\t$(INSTALL_DIR) $(STAGING_DIR_IMAGE)\nifneq ($(USE_RKBIN),)\n\t$(STAGING_DIR_IMAGE)/loaderimage --pack --uboot $(PKG_BUILD_DIR)/u-boot-dtb.bin $(PKG_BUILD_DIR)/uboot.img 0x200000\n\t$(CP) $(PKG_BUILD_DIR)/uboot.img $(STAGING_DIR_IMAGE)/$(BUILD_VARIANT)-uboot.img\n\t$(CP) $(STAGING_DIR_IMAGE)/idbloader.bin $(STAGING_DIR_IMAGE)/$(BUILD_VARIANT)-idbloader.bin\n\t$(CP) $(STAGING_DIR_IMAGE)/trust.bin $(STAGING_DIR_IMAGE)/$(BUILD_VARIANT)-trust.bin\nelse\n\t$(CP) $(PKG_BUILD_DIR)/idbloader.img $(STAGING_DIR_IMAGE)/$(BUILD_VARIANT)-idbloader.img\n\t$(CP) $(PKG_BUILD_DIR)/u-boot.itb $(STAGING_DIR_IMAGE)/$(BUILD_VARIANT)-u-boot.itb\nendif\nendef\n\ndefine Package/u-boot/install/default\nendef\n\n$(eval $(call BuildPackage/U-Boot))\n"
  },
  {
    "path": "package/boot/uboot-rockchip/patches/001-scripts-remove-dependency-on-swig.patch",
    "content": "From b137ca16b54c67d76714ea5a0138741959b0dc29 Mon Sep 17 00:00:00 2001\nFrom: David Bauer <mail@david-bauer.net>\nDate: Mon, 13 Jul 2020 23:37:37 +0200\nSubject: [PATCH] scripts: remove dependency on swig\n\nDon't build the libfdt tool, as it has a dependency on swig (which\nOpenWrt does not ship).\n\nThis requires more hacks, as of-platdata generation does not work\nwithout it.\n\nSigned-off-by: David Bauer <mail@david-bauer.net>\n---\n scripts/dtc/Makefile | 2 --\n 1 file changed, 2 deletions(-)\n\n--- a/scripts/dtc/Makefile\n+++ b/scripts/dtc/Makefile\n@@ -18,5 +18,3 @@ HOSTCFLAGS_dtc-parser.tab.o := -I$(src)\n # dependencies on generated files need to be listed explicitly\n $(obj)/dtc-lexer.lex.o: $(obj)/dtc-parser.tab.h\n \n-# Added for U-Boot\n-subdir-$(CONFIG_PYLIBFDT) += pylibfdt\n"
  },
  {
    "path": "package/boot/uboot-rockchip/patches/002-spl-remove-dtoc-of-pdata-generation.patch",
    "content": "From 55273cf6079ddd3b006da69f0113c2c66c03f17e Mon Sep 17 00:00:00 2001\nFrom: David Bauer <mail@david-bauer.net>\nDate: Tue, 14 Jul 2020 22:44:22 +0200\nSubject: [PATCH] spl: remove dtoc of-pdata generation\n\nRemove the dtoc of-pdata generation. This generation is dependant on\nlibpython-dev. As OpenWrt does not ship with this dependency, use\npre-generated pdata files and remove the generation from the\nbuild-process.\n\nThis only affects RK3328 boards.\n\nSigned-off-by: David Bauer <mail@david-bauer.net>\n---\n scripts/Makefile.spl | 6 ------\n 1 file changed, 6 deletions(-)\n\n--- a/scripts/Makefile.spl\n+++ b/scripts/Makefile.spl\n@@ -354,8 +354,6 @@ $(platdata-hdr) $(u-boot-spl-platdata_c)\n \t@# of OF_PLATDATA_INST and this might change between builds. Leaving old\n \t@# ones around is confusing and it is possible that switching the\n \t@# setting again will use the old one instead of regenerating it.\n-\t@rm -f $(u-boot-spl-all-platdata_c) $(u-boot-spl-all-platdata)\n-\t$(call if_changed,dtoc)\n \n ifdef CONFIG_SAMSUNG\n ifdef CONFIG_VAR_SIZE_SPL\n"
  },
  {
    "path": "package/boot/uboot-rockchip/patches/101-rock64pro-disable-CONFIG_USE_PREBOOT.patch",
    "content": "From 2114d68b3c755ec8043ae9e43ac8e9753e0cec84 Mon Sep 17 00:00:00 2001\nFrom: Marty Jones <mj8263788@gmail.com>\nDate: Sun, 17 Jan 2021 15:26:09 -0500\nSubject: [PATCH] rockpro64: disable CONFIG_USE_PREBOOT\n\nOn commit https://github.com/u-boot/u-boot/commit/f81f9f0ebac596bae7f27db095f4f0272b606cc3\nCONFIG_USE_PREBOOT was enabled on the RockPro64.\n\nWhen the board is booting, U-Boot hangs as soon as it disables the USB\ncontroller. This is a workaround until a final solution is deployed\nupstream.\n\nSigned-off-by: Marty Jones <mj8263788@gmail.com>\n---\n configs/rockpro64-rk3399_defconfig | 1 -\n 1 file changed, 1 deletion(-)\n\n--- a/configs/rockpro64-rk3399_defconfig\n+++ b/configs/rockpro64-rk3399_defconfig\n@@ -12,7 +12,6 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y\n CONFIG_SPL_SPI_SUPPORT=y\n CONFIG_DEFAULT_DEVICE_TREE=\"rk3399-rockpro64\"\n CONFIG_DEBUG_UART=y\n-CONFIG_USE_PREBOOT=y\n CONFIG_DEFAULT_FDT_FILE=\"rockchip/rk3399-rockpro64.dtb\"\n CONFIG_DISPLAY_BOARDINFO_LATE=y\n CONFIG_MISC_INIT_R=y\n"
  },
  {
    "path": "package/boot/uboot-rockchip/patches/200-rockchip-rk3328-Add-support-for-Orangepi-R1-Plus.patch",
    "content": "--- a/arch/arm/dts/Makefile\n+++ b/arch/arm/dts/Makefile\n@@ -109,6 +109,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3308) += \\\n dtb-$(CONFIG_ROCKCHIP_RK3328) += \\\n \trk3328-evb.dtb \\\n \trk3328-nanopi-r2s.dtb \\\n+\trk3328-orangepi-r1-plus.dtb \\\n \trk3328-roc-cc.dtb \\\n \trk3328-rock64.dtb \\\n \trk3328-rock-pi-e.dtb\n--- /dev/null\n+++ b/arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi\n@@ -0,0 +1,1 @@\n+#include \"rk3328-nanopi-r2s-u-boot.dtsi\"\n--- /dev/null\n+++ b/arch/arm/dts/rk3328-orangepi-r1-plus.dts\n@@ -0,0 +1,38 @@\n+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)\n+#include \"rk3328-nanopi-r2s.dts\"\n+\n+/ {\n+\tmodel = \"Xunlong Orange Pi R1 Plus\";\n+\tcompatible = \"xunlong,orangepi-r1-plus\", \"rockchip,rk3328\";\n+};\n+\n+&lan_led {\n+\tlabel = \"orangepi-r1-plus:green:lan\";\n+};\n+\n+&spi0 {\n+\tstatus = \"okay\";\n+\n+\tflash@0 {\n+\t\tcompatible = \"jedec,spi-nor\";\n+\t\treg = <0>;\n+\t\tspi-max-frequency = <10000000>;\n+\t};\n+};\n+\n+&sys_led {\n+\tgpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;\n+\tlabel = \"orangepi-r1-plus:red:sys\";\n+};\n+\n+&sys_led_pin {\n+\trockchip,pins = <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;\n+};\n+\n+&uart1 {\n+\tstatus = \"okay\";\n+};\n+\n+&wan_led {\n+\tlabel = \"orangepi-r1-plus:green:wan\";\n+};\n--- a/board/rockchip/evb_rk3328/MAINTAINERS\n+++ b/board/rockchip/evb_rk3328/MAINTAINERS\n@@ -12,6 +12,13 @@ F:      configs/nanopi-r2s-rk3328_defconfig\n F:      arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi\n F:      arch/arm/dts/rk3328-nanopi-r2s.dts\n \n+ORANGEPI-R1-PLUS-RK3328\n+M:      Shenzhen Xunlong Software CO.,Limited <zhao_steven@263.net>\n+S:      Maintained\n+F:      configs/orangepi-r1-plus-rk3328_defconfig\n+F:      arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi\n+F:      arch/arm/dts/rk3328-orangepi-r1-plus.dts\n+\n ROC-RK3328-CC\n M:      Loic Devulder <ldevulder@suse.com>\n M:      Chen-Yu Tsai <wens@csie.org>\n--- /dev/null\n+++ b/configs/orangepi-r1-plus-rk3328_defconfig\n@@ -0,0 +1,98 @@\n+CONFIG_ARM=y\n+CONFIG_ARCH_ROCKCHIP=y\n+CONFIG_SYS_TEXT_BASE=0x00200000\n+CONFIG_SPL_GPIO_SUPPORT=y\n+CONFIG_ENV_OFFSET=0x3F8000\n+CONFIG_ROCKCHIP_RK3328=y\n+CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y\n+CONFIG_TPL_LIBCOMMON_SUPPORT=y\n+CONFIG_TPL_LIBGENERIC_SUPPORT=y\n+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y\n+CONFIG_SPL_STACK_R_ADDR=0x600000\n+CONFIG_NR_DRAM_BANKS=1\n+CONFIG_DEBUG_UART_BASE=0xFF130000\n+CONFIG_DEBUG_UART_CLOCK=24000000\n+CONFIG_SYSINFO=y\n+CONFIG_DEBUG_UART=y\n+CONFIG_TPL_SYS_MALLOC_F_LEN=0x800\n+# CONFIG_ANDROID_BOOT_IMAGE is not set\n+CONFIG_FIT=y\n+CONFIG_FIT_VERBOSE=y\n+CONFIG_SPL_LOAD_FIT=y\n+CONFIG_DEFAULT_FDT_FILE=\"rockchip/rk3328-orangepi-r1-plus.dtb\"\n+CONFIG_MISC_INIT_R=y\n+# CONFIG_DISPLAY_CPUINFO is not set\n+CONFIG_DISPLAY_BOARDINFO_LATE=y\n+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set\n+CONFIG_TPL_SYS_MALLOC_SIMPLE=y\n+CONFIG_SPL_STACK_R=y\n+CONFIG_SPL_I2C_SUPPORT=y\n+CONFIG_SPL_POWER_SUPPORT=y\n+CONFIG_SPL_ATF=y\n+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y\n+CONFIG_CMD_BOOTZ=y\n+CONFIG_CMD_GPT=y\n+CONFIG_CMD_MMC=y\n+CONFIG_CMD_USB=y\n+# CONFIG_CMD_SETEXPR is not set\n+CONFIG_CMD_TIME=y\n+CONFIG_SPL_OF_CONTROL=y\n+CONFIG_TPL_OF_CONTROL=y\n+CONFIG_DEFAULT_DEVICE_TREE=\"rk3328-orangepi-r1-plus\"\n+CONFIG_OF_SPL_REMOVE_PROPS=\"clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents\"\n+CONFIG_TPL_OF_PLATDATA=y\n+CONFIG_ENV_IS_IN_MMC=y\n+CONFIG_SYS_RELOC_GD_ENV_ADDR=y\n+CONFIG_NET_RANDOM_ETHADDR=y\n+CONFIG_TPL_DM=y\n+CONFIG_REGMAP=y\n+CONFIG_SPL_REGMAP=y\n+CONFIG_TPL_REGMAP=y\n+CONFIG_SYSCON=y\n+CONFIG_SPL_SYSCON=y\n+CONFIG_TPL_SYSCON=y\n+CONFIG_CLK=y\n+CONFIG_SPL_CLK=y\n+CONFIG_FASTBOOT_BUF_ADDR=0x800800\n+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y\n+CONFIG_ROCKCHIP_GPIO=y\n+CONFIG_SYS_I2C_ROCKCHIP=y\n+CONFIG_MMC_DW=y\n+CONFIG_MMC_DW_ROCKCHIP=y\n+CONFIG_SF_DEFAULT_SPEED=20000000\n+CONFIG_DM_ETH=y\n+CONFIG_ETH_DESIGNWARE=y\n+CONFIG_GMAC_ROCKCHIP=y\n+CONFIG_PINCTRL=y\n+CONFIG_SPL_PINCTRL=y\n+CONFIG_DM_PMIC=y\n+CONFIG_PMIC_RK8XX=y\n+CONFIG_SPL_DM_REGULATOR=y\n+CONFIG_REGULATOR_PWM=y\n+CONFIG_DM_REGULATOR_FIXED=y\n+CONFIG_SPL_DM_REGULATOR_FIXED=y\n+CONFIG_REGULATOR_RK8XX=y\n+CONFIG_PWM_ROCKCHIP=y\n+CONFIG_RAM=y\n+CONFIG_SPL_RAM=y\n+CONFIG_TPL_RAM=y\n+CONFIG_DM_RESET=y\n+CONFIG_BAUDRATE=1500000\n+CONFIG_DEBUG_UART_SHIFT=2\n+CONFIG_SYSRESET=y\n+# CONFIG_TPL_SYSRESET is not set\n+CONFIG_USB=y\n+CONFIG_USB_XHCI_HCD=y\n+CONFIG_USB_XHCI_DWC3=y\n+CONFIG_USB_EHCI_HCD=y\n+CONFIG_USB_EHCI_GENERIC=y\n+CONFIG_USB_OHCI_HCD=y\n+CONFIG_USB_OHCI_GENERIC=y\n+CONFIG_USB_DWC2=y\n+CONFIG_USB_DWC3=y\n+# CONFIG_USB_DWC3_GADGET is not set\n+CONFIG_USB_GADGET=y\n+CONFIG_USB_GADGET_DWC2_OTG=y\n+CONFIG_SPL_TINY_MEMSET=y\n+CONFIG_TPL_TINY_MEMSET=y\n+CONFIG_ERRNO_STR=y\n"
  },
  {
    "path": "package/boot/uboot-rockchip/patches/201-Add-support-for-Orangepi-R1-Plus-LTS.patch",
    "content": "From 68836b81f7d6328a1a5a6cce5a00bf4010f742e5 Mon Sep 17 00:00:00 2001\nFrom: baiywt <baiywt_gj@163.com>\nDate: Wed, 24 Nov 2021 19:59:38 +0800\nSubject: [PATCH] Add support for Orangepi R1 Plus LTS\n\n---\n arch/arm/dts/Makefile                         |  1 +\n arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts  |  7 ++\n configs/orangepi-r1-plus-lts-rk3328_defconfig | 98 +++++++++++++++++++\n 3 files changed, 106 insertions(+)\n create mode 100644 arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts\n create mode 100644 configs/orangepi-r1-plus-lts-rk3328_defconfig\n\ndiff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile\nindex adfe6c3f..3d4e0f59 100644\n--- a/arch/arm/dts/Makefile\n+++ b/arch/arm/dts/Makefile\n@@ -110,6 +110,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3328) += \\\n \trk3328-evb.dtb \\\n \trk3328-nanopi-r2s.dtb \\\n \trk3328-orangepi-r1-plus.dtb \\\n+\trk3328-orangepi-r1-plus-lts.dtb \\\n \trk3328-roc-cc.dtb \\\n \trk3328-rock64.dtb \\\n \trk3328-rock-pi-e.dtb\ndiff --git a/arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts b/arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts\nnew file mode 100644\nindex 00000000..e6225b0c\n--- /dev/null\n+++ b/arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts\n@@ -0,0 +1,7 @@\n+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)\n+#include \"rk3328-orangepi-r1-plus.dts\"\n+\n+/ {\n+\tmodel = \"Xunlong Orange Pi R1 Plus LTS\";\n+\tcompatible = \"xunlong,orangepi-r1-plus-lts\", \"rockchip,rk3328\";\n+};\ndiff --git a/configs/orangepi-r1-plus-lts-rk3328_defconfig b/configs/orangepi-r1-plus-lts-rk3328_defconfig\nnew file mode 100644\nindex 00000000..3cb3b5c3\n--- /dev/null\n+++ b/configs/orangepi-r1-plus-lts-rk3328_defconfig\n@@ -0,0 +1,98 @@\n+CONFIG_ARM=y\n+CONFIG_ARCH_ROCKCHIP=y\n+CONFIG_SYS_TEXT_BASE=0x00200000\n+CONFIG_SPL_GPIO_SUPPORT=y\n+CONFIG_ENV_OFFSET=0x3F8000\n+CONFIG_ROCKCHIP_RK3328=y\n+CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y\n+CONFIG_TPL_LIBCOMMON_SUPPORT=y\n+CONFIG_TPL_LIBGENERIC_SUPPORT=y\n+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y\n+CONFIG_SPL_STACK_R_ADDR=0x600000\n+CONFIG_NR_DRAM_BANKS=1\n+CONFIG_DEBUG_UART_BASE=0xFF130000\n+CONFIG_DEBUG_UART_CLOCK=24000000\n+CONFIG_SYSINFO=y\n+CONFIG_DEBUG_UART=y\n+CONFIG_TPL_SYS_MALLOC_F_LEN=0x800\n+# CONFIG_ANDROID_BOOT_IMAGE is not set\n+CONFIG_FIT=y\n+CONFIG_FIT_VERBOSE=y\n+CONFIG_SPL_LOAD_FIT=y\n+CONFIG_DEFAULT_FDT_FILE=\"rockchip/rk3328-orangepi-r1-plus-lts.dtb\"\n+CONFIG_MISC_INIT_R=y\n+# CONFIG_DISPLAY_CPUINFO is not set\n+CONFIG_DISPLAY_BOARDINFO_LATE=y\n+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set\n+CONFIG_TPL_SYS_MALLOC_SIMPLE=y\n+CONFIG_SPL_STACK_R=y\n+CONFIG_SPL_I2C_SUPPORT=y\n+CONFIG_SPL_POWER_SUPPORT=y\n+CONFIG_SPL_ATF=y\n+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y\n+CONFIG_CMD_BOOTZ=y\n+CONFIG_CMD_GPT=y\n+CONFIG_CMD_MMC=y\n+CONFIG_CMD_USB=y\n+# CONFIG_CMD_SETEXPR is not set\n+CONFIG_CMD_TIME=y\n+CONFIG_SPL_OF_CONTROL=y\n+CONFIG_TPL_OF_CONTROL=y\n+CONFIG_DEFAULT_DEVICE_TREE=\"rk3328-orangepi-r1-plus-lts\"\n+CONFIG_OF_SPL_REMOVE_PROPS=\"clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents\"\n+CONFIG_TPL_OF_PLATDATA=y\n+CONFIG_ENV_IS_IN_MMC=y\n+CONFIG_SYS_RELOC_GD_ENV_ADDR=y\n+CONFIG_NET_RANDOM_ETHADDR=y\n+CONFIG_TPL_DM=y\n+CONFIG_REGMAP=y\n+CONFIG_SPL_REGMAP=y\n+CONFIG_TPL_REGMAP=y\n+CONFIG_SYSCON=y\n+CONFIG_SPL_SYSCON=y\n+CONFIG_TPL_SYSCON=y\n+CONFIG_CLK=y\n+CONFIG_SPL_CLK=y\n+CONFIG_FASTBOOT_BUF_ADDR=0x800800\n+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y\n+CONFIG_ROCKCHIP_GPIO=y\n+CONFIG_SYS_I2C_ROCKCHIP=y\n+CONFIG_MMC_DW=y\n+CONFIG_MMC_DW_ROCKCHIP=y\n+CONFIG_SF_DEFAULT_SPEED=20000000\n+CONFIG_DM_ETH=y\n+CONFIG_ETH_DESIGNWARE=y\n+CONFIG_GMAC_ROCKCHIP=y\n+CONFIG_PINCTRL=y\n+CONFIG_SPL_PINCTRL=y\n+CONFIG_DM_PMIC=y\n+CONFIG_PMIC_RK8XX=y\n+CONFIG_SPL_DM_REGULATOR=y\n+CONFIG_REGULATOR_PWM=y\n+CONFIG_DM_REGULATOR_FIXED=y\n+CONFIG_SPL_DM_REGULATOR_FIXED=y\n+CONFIG_REGULATOR_RK8XX=y\n+CONFIG_PWM_ROCKCHIP=y\n+CONFIG_RAM=y\n+CONFIG_SPL_RAM=y\n+CONFIG_TPL_RAM=y\n+CONFIG_DM_RESET=y\n+CONFIG_BAUDRATE=1500000\n+CONFIG_DEBUG_UART_SHIFT=2\n+CONFIG_SYSRESET=y\n+# CONFIG_TPL_SYSRESET is not set\n+CONFIG_USB=y\n+CONFIG_USB_XHCI_HCD=y\n+CONFIG_USB_XHCI_DWC3=y\n+CONFIG_USB_EHCI_HCD=y\n+CONFIG_USB_EHCI_GENERIC=y\n+CONFIG_USB_OHCI_HCD=y\n+CONFIG_USB_OHCI_GENERIC=y\n+CONFIG_USB_DWC2=y\n+CONFIG_USB_DWC3=y\n+# CONFIG_USB_DWC3_GADGET is not set\n+CONFIG_USB_GADGET=y\n+CONFIG_USB_GADGET_DWC2_OTG=y\n+CONFIG_SPL_TINY_MEMSET=y\n+CONFIG_TPL_TINY_MEMSET=y\n+CONFIG_ERRNO_STR=y\n-- \n2.25.1\n\n"
  },
  {
    "path": "package/boot/uboot-rockchip/src/of-platdata/nanopi-r2s-rk3328/dt-decl.h",
    "content": "/*\n * DO NOT MODIFY\n *\n * Declares externs for all device/uclass instances.\n * This was generated by dtoc from a .dtb (device tree binary) file.\n */\n\n#include <dm/device-internal.h>\n#include <dm/uclass-internal.h>\n\n/* driver declarations - these allow DM_DRIVER_GET() to be used */\nextern U_BOOT_DRIVER(rockchip_rk3328_cru);\nextern U_BOOT_DRIVER(rockchip_rk3328_dmc);\nextern U_BOOT_DRIVER(rockchip_rk3288_dw_mshc);\nextern U_BOOT_DRIVER(ns16550_serial);\nextern U_BOOT_DRIVER(rockchip_rk3328_grf);\n\n/* uclass driver declarations - needed for DM_UCLASS_DRIVER_REF() */\nextern UCLASS_DRIVER(clk);\nextern UCLASS_DRIVER(mmc);\nextern UCLASS_DRIVER(ram);\nextern UCLASS_DRIVER(serial);\nextern UCLASS_DRIVER(syscon);\n"
  },
  {
    "path": "package/boot/uboot-rockchip/src/of-platdata/nanopi-r2s-rk3328/dt-plat.c",
    "content": "/*\n * DO NOT MODIFY\n *\n * Declares the U_BOOT_DRIVER() records and platform data.\n * This was generated by dtoc from a .dtb (device tree binary) file.\n */\n\n/* Allow use of U_BOOT_DRVINFO() in this file */\n#define DT_PLAT_C\n\n#include <common.h>\n#include <dm.h>\n#include <dt-structs.h>\n\n/*\n * driver_info declarations, ordered by 'struct driver_info' linker_list idx:\n *\n * idx  driver_info          driver\n * ---  -------------------- --------------------\n *   0: clock_controller_at_ff440000 rockchip_rk3328_cru\n *   1: dmc                  rockchip_rk3328_dmc\n *   2: mmc_at_ff500000      rockchip_rk3288_dw_mshc\n *   3: serial_at_ff130000   ns16550_serial\n *   4: syscon_at_ff100000   rockchip_rk3328_grf\n * ---  -------------------- --------------------\n */\n\n/*\n * Node /clock-controller@ff440000 index 0\n * driver rockchip_rk3328_cru parent None\n */\nstatic struct dtd_rockchip_rk3328_cru dtv_clock_controller_at_ff440000 = {\n\t.reg\t\t\t= {0xff440000, 0x1000},\n\t.rockchip_grf\t\t= 0x3a,\n};\nU_BOOT_DRVINFO(clock_controller_at_ff440000) = {\n\t.name\t\t= \"rockchip_rk3328_cru\",\n\t.plat\t\t= &dtv_clock_controller_at_ff440000,\n\t.plat_size\t= sizeof(dtv_clock_controller_at_ff440000),\n\t.parent_idx\t= -1,\n};\n\n/*\n * Node /dmc index 1\n * driver rockchip_rk3328_dmc parent None\n */\nstatic struct dtd_rockchip_rk3328_dmc dtv_dmc = {\n\t.reg\t\t\t= {0xff400000, 0x1000, 0xff780000, 0x3000, 0xff100000, 0x1000, 0xff440000, 0x1000,\n\t\t0xff720000, 0x1000, 0xff798000, 0x1000},\n\t.rockchip_sdram_params\t= {0x1, 0xa, 0x2, 0x1, 0x0, 0x0, 0x11, 0x0,\n\t\t0x11, 0x0, 0x0, 0x94291288, 0x0, 0x27, 0x462, 0x15,\n\t\t0x242, 0xff, 0x14d, 0x0, 0x1, 0x0, 0x0, 0x0,\n\t\t0x43049010, 0x64, 0x28003b, 0xd0, 0x20053, 0xd4, 0x220000, 0xd8,\n\t\t0x100, 0xdc, 0x40000, 0xe0, 0x0, 0xe4, 0x110000, 0xe8,\n\t\t0x420, 0xec, 0x400, 0xf4, 0xf011f, 0x100, 0x9060b06, 0x104,\n\t\t0x20209, 0x108, 0x505040a, 0x10c, 0x40400c, 0x110, 0x5030206, 0x114,\n\t\t0x3030202, 0x120, 0x3030b03, 0x124, 0x20208, 0x180, 0x1000040, 0x184,\n\t\t0x0, 0x190, 0x7030003, 0x198, 0x5001100, 0x1a0, 0xc0400003, 0x240,\n\t\t0x6000604, 0x244, 0x201, 0x250, 0xf00, 0x490, 0x1, 0xffffffff,\n\t\t0xffffffff, 0xffffffff, 0xffffffff, 0x4, 0xc, 0x28, 0xa, 0x2c,\n\t\t0x0, 0x30, 0x9, 0xffffffff, 0xffffffff, 0x77, 0x88, 0x79,\n\t\t0x79, 0x87, 0x97, 0x87, 0x78, 0x77, 0x78, 0x87,\n\t\t0x88, 0x87, 0x87, 0x77, 0x78, 0x78, 0x78, 0x78,\n\t\t0x78, 0x78, 0x78, 0x78, 0x78, 0x69, 0x9, 0x77,\n\t\t0x78, 0x77, 0x78, 0x77, 0x78, 0x77, 0x78, 0x77,\n\t\t0x79, 0x9, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78,\n\t\t0x78, 0x78, 0x78, 0x69, 0x9, 0x77, 0x78, 0x77,\n\t\t0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x79, 0x9,\n\t\t0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78,\n\t\t0x78, 0x69, 0x9, 0x77, 0x78, 0x77, 0x78, 0x77,\n\t\t0x78, 0x77, 0x78, 0x77, 0x79, 0x9, 0x78, 0x78,\n\t\t0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x69,\n\t\t0x9, 0x77, 0x78, 0x77, 0x77, 0x77, 0x77, 0x77,\n\t\t0x77, 0x77, 0x79, 0x9},\n};\nU_BOOT_DRVINFO(dmc) = {\n\t.name\t\t= \"rockchip_rk3328_dmc\",\n\t.plat\t\t= &dtv_dmc,\n\t.plat_size\t= sizeof(dtv_dmc),\n\t.parent_idx\t= -1,\n};\n\n/*\n * Node /mmc@ff500000 index 2\n * driver rockchip_rk3288_dw_mshc parent None\n */\nstatic struct dtd_rockchip_rk3288_dw_mshc dtv_mmc_at_ff500000 = {\n\t.bus_width\t\t= 0x4,\n\t.cap_sd_highspeed\t= true,\n\t.clocks\t\t\t= {\n\t\t\t{0, {317}},\n\t\t\t{0, {33}},\n\t\t\t{0, {74}},\n\t\t\t{0, {78}},},\n\t.disable_wp\t\t= true,\n\t.fifo_depth\t\t= 0x100,\n\t.interrupts\t\t= {0x0, 0xc, 0x4},\n\t.max_frequency\t\t= 0x8f0d180,\n\t.pinctrl_0\t\t= {0x47, 0x48, 0x49, 0x4a},\n\t.pinctrl_names\t\t= \"default\",\n\t.reg\t\t\t= {0xff500000, 0x4000},\n\t.sd_uhs_sdr104\t\t= true,\n\t.sd_uhs_sdr12\t\t= true,\n\t.sd_uhs_sdr25\t\t= true,\n\t.sd_uhs_sdr50\t\t= true,\n\t.u_boot_spl_fifo_mode\t= true,\n\t.vmmc_supply\t\t= 0x4b,\n\t.vqmmc_supply\t\t= 0x1e,\n};\nU_BOOT_DRVINFO(mmc_at_ff500000) = {\n\t.name\t\t= \"rockchip_rk3288_dw_mshc\",\n\t.plat\t\t= &dtv_mmc_at_ff500000,\n\t.plat_size\t= sizeof(dtv_mmc_at_ff500000),\n\t.parent_idx\t= -1,\n};\n\n/*\n * Node /serial@ff130000 index 3\n * driver ns16550_serial parent None\n */\nstatic struct dtd_ns16550_serial dtv_serial_at_ff130000 = {\n\t.clock_frequency\t= 0x16e3600,\n\t.clocks\t\t\t= {\n\t\t\t{0, {40}},\n\t\t\t{0, {212}},},\n\t.dma_names\t\t= {\"tx\", \"rx\"},\n\t.dmas\t\t\t= {0x10, 0x6, 0x10, 0x7},\n\t.interrupts\t\t= {0x0, 0x39, 0x4},\n\t.pinctrl_0\t\t= 0x26,\n\t.pinctrl_names\t\t= \"default\",\n\t.reg\t\t\t= {0xff130000, 0x100},\n\t.reg_io_width\t\t= 0x4,\n\t.reg_shift\t\t= 0x2,\n};\nU_BOOT_DRVINFO(serial_at_ff130000) = {\n\t.name\t\t= \"ns16550_serial\",\n\t.plat\t\t= &dtv_serial_at_ff130000,\n\t.plat_size\t= sizeof(dtv_serial_at_ff130000),\n\t.parent_idx\t= -1,\n};\n\n/*\n * Node /syscon@ff100000 index 4\n * driver rockchip_rk3328_grf parent None\n */\nstatic struct dtd_rockchip_rk3328_grf dtv_syscon_at_ff100000 = {\n\t.reg\t\t\t= {0xff100000, 0x1000},\n};\nU_BOOT_DRVINFO(syscon_at_ff100000) = {\n\t.name\t\t= \"rockchip_rk3328_grf\",\n\t.plat\t\t= &dtv_syscon_at_ff100000,\n\t.plat_size\t= sizeof(dtv_syscon_at_ff100000),\n\t.parent_idx\t= -1,\n};\n\n"
  },
  {
    "path": "package/boot/uboot-rockchip/src/of-platdata/nanopi-r2s-rk3328/dt-structs-gen.h",
    "content": "/*\n * DO NOT MODIFY\n *\n * Defines the structs used to hold devicetree data.\n * This was generated by dtoc from a .dtb (device tree binary) file.\n */\n\n#include <stdbool.h>\n#include <linux/libfdt.h>\nstruct dtd_ns16550_serial {\n\tfdt32_t\t\tclock_frequency;\n\tstruct phandle_1_arg clocks[2];\n\tconst char *\tdma_names[2];\n\tfdt32_t\t\tdmas[4];\n\tfdt32_t\t\tinterrupts[3];\n\tfdt32_t\t\tpinctrl_0;\n\tconst char *\tpinctrl_names;\n\tfdt64_t\t\treg[2];\n\tfdt32_t\t\treg_io_width;\n\tfdt32_t\t\treg_shift;\n};\nstruct dtd_rockchip_rk3288_dw_mshc {\n\tfdt32_t\t\tbus_width;\n\tbool\t\tcap_sd_highspeed;\n\tstruct phandle_1_arg clocks[4];\n\tbool\t\tdisable_wp;\n\tfdt32_t\t\tfifo_depth;\n\tfdt32_t\t\tinterrupts[3];\n\tfdt32_t\t\tmax_frequency;\n\tfdt32_t\t\tpinctrl_0[4];\n\tconst char *\tpinctrl_names;\n\tfdt64_t\t\treg[2];\n\tbool\t\tsd_uhs_sdr104;\n\tbool\t\tsd_uhs_sdr12;\n\tbool\t\tsd_uhs_sdr25;\n\tbool\t\tsd_uhs_sdr50;\n\tbool\t\tu_boot_spl_fifo_mode;\n\tfdt32_t\t\tvmmc_supply;\n\tfdt32_t\t\tvqmmc_supply;\n};\nstruct dtd_rockchip_rk3328_cru {\n\tfdt64_t\t\treg[2];\n\tfdt32_t\t\trockchip_grf;\n};\nstruct dtd_rockchip_rk3328_dmc {\n\tfdt64_t\t\treg[12];\n\tfdt32_t\t\trockchip_sdram_params[196];\n};\nstruct dtd_rockchip_rk3328_grf {\n\tfdt64_t\t\treg[2];\n};\n"
  },
  {
    "path": "package/boot/uboot-rockchip/src/of-platdata/orangepi-r1-plus-lts-rk3328/dt-decl.h",
    "content": "/*\n * DO NOT MODIFY\n *\n * Declares externs for all device/uclass instances.\n * This was generated by dtoc from a .dtb (device tree binary) file.\n */\n\n#include <dm/device-internal.h>\n#include <dm/uclass-internal.h>\n\n/* driver declarations - these allow DM_DRIVER_GET() to be used */\nextern U_BOOT_DRIVER(rockchip_rk3328_cru);\nextern U_BOOT_DRIVER(rockchip_rk3328_dmc);\nextern U_BOOT_DRIVER(rockchip_rk3288_dw_mshc);\nextern U_BOOT_DRIVER(ns16550_serial);\nextern U_BOOT_DRIVER(rockchip_rk3328_grf);\n\n/* uclass driver declarations - needed for DM_UCLASS_DRIVER_REF() */\nextern UCLASS_DRIVER(clk);\nextern UCLASS_DRIVER(mmc);\nextern UCLASS_DRIVER(ram);\nextern UCLASS_DRIVER(serial);\nextern UCLASS_DRIVER(syscon);\n"
  },
  {
    "path": "package/boot/uboot-rockchip/src/of-platdata/orangepi-r1-plus-lts-rk3328/dt-plat.c",
    "content": "/*\n * DO NOT MODIFY\n *\n * Declares the U_BOOT_DRIVER() records and platform data.\n * This was generated by dtoc from a .dtb (device tree binary) file.\n */\n\n/* Allow use of U_BOOT_DRVINFO() in this file */\n#define DT_PLAT_C\n\n#include <common.h>\n#include <dm.h>\n#include <dt-structs.h>\n\n/*\n * driver_info declarations, ordered by 'struct driver_info' linker_list idx:\n *\n * idx  driver_info          driver\n * ---  -------------------- --------------------\n *   0: clock_controller_at_ff440000 rockchip_rk3328_cru\n *   1: dmc                  rockchip_rk3328_dmc\n *   2: mmc_at_ff500000      rockchip_rk3288_dw_mshc\n *   3: serial_at_ff130000   ns16550_serial\n *   4: syscon_at_ff100000   rockchip_rk3328_grf\n * ---  -------------------- --------------------\n */\n\n/*\n * Node /clock-controller@ff440000 index 0\n * driver rockchip_rk3328_cru parent None\n */\nstatic struct dtd_rockchip_rk3328_cru dtv_clock_controller_at_ff440000 = {\n\t.reg\t\t\t= {0xff440000, 0x1000},\n\t.rockchip_grf\t\t= 0x3a,\n};\nU_BOOT_DRVINFO(clock_controller_at_ff440000) = {\n\t.name\t\t= \"rockchip_rk3328_cru\",\n\t.plat\t\t= &dtv_clock_controller_at_ff440000,\n\t.plat_size\t= sizeof(dtv_clock_controller_at_ff440000),\n\t.parent_idx\t= -1,\n};\n\n/*\n * Node /dmc index 1\n * driver rockchip_rk3328_dmc parent None\n */\nstatic struct dtd_rockchip_rk3328_dmc dtv_dmc = {\n\t.reg\t\t\t= {0xff400000, 0x1000, 0xff780000, 0x3000, 0xff100000, 0x1000, 0xff440000, 0x1000,\n\t\t0xff720000, 0x1000, 0xff798000, 0x1000},\n\t.rockchip_sdram_params\t= {0x1, 0xa, 0x2, 0x1, 0x0, 0x0, 0x11, 0x0,\n\t\t0x11, 0x0, 0x0, 0x94291288, 0x0, 0x27, 0x462, 0x15,\n\t\t0x242, 0xff, 0x14d, 0x0, 0x1, 0x0, 0x0, 0x0,\n\t\t0x43049010, 0x64, 0x28003b, 0xd0, 0x20053, 0xd4, 0x220000, 0xd8,\n\t\t0x100, 0xdc, 0x40000, 0xe0, 0x0, 0xe4, 0x110000, 0xe8,\n\t\t0x420, 0xec, 0x400, 0xf4, 0xf011f, 0x100, 0x9060b06, 0x104,\n\t\t0x20209, 0x108, 0x505040a, 0x10c, 0x40400c, 0x110, 0x5030206, 0x114,\n\t\t0x3030202, 0x120, 0x3030b03, 0x124, 0x20208, 0x180, 0x1000040, 0x184,\n\t\t0x0, 0x190, 0x7030003, 0x198, 0x5001100, 0x1a0, 0xc0400003, 0x240,\n\t\t0x6000604, 0x244, 0x201, 0x250, 0xf00, 0x490, 0x1, 0xffffffff,\n\t\t0xffffffff, 0xffffffff, 0xffffffff, 0x4, 0xc, 0x28, 0xa, 0x2c,\n\t\t0x0, 0x30, 0x9, 0xffffffff, 0xffffffff, 0x77, 0x88, 0x79,\n\t\t0x79, 0x87, 0x97, 0x87, 0x78, 0x77, 0x78, 0x87,\n\t\t0x88, 0x87, 0x87, 0x77, 0x78, 0x78, 0x78, 0x78,\n\t\t0x78, 0x78, 0x78, 0x78, 0x78, 0x69, 0x9, 0x77,\n\t\t0x78, 0x77, 0x78, 0x77, 0x78, 0x77, 0x78, 0x77,\n\t\t0x79, 0x9, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78,\n\t\t0x78, 0x78, 0x78, 0x69, 0x9, 0x77, 0x78, 0x77,\n\t\t0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x79, 0x9,\n\t\t0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78,\n\t\t0x78, 0x69, 0x9, 0x77, 0x78, 0x77, 0x78, 0x77,\n\t\t0x78, 0x77, 0x78, 0x77, 0x79, 0x9, 0x78, 0x78,\n\t\t0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x69,\n\t\t0x9, 0x77, 0x78, 0x77, 0x77, 0x77, 0x77, 0x77,\n\t\t0x77, 0x77, 0x79, 0x9},\n};\nU_BOOT_DRVINFO(dmc) = {\n\t.name\t\t= \"rockchip_rk3328_dmc\",\n\t.plat\t\t= &dtv_dmc,\n\t.plat_size\t= sizeof(dtv_dmc),\n\t.parent_idx\t= -1,\n};\n\n/*\n * Node /mmc@ff500000 index 2\n * driver rockchip_rk3288_dw_mshc parent None\n */\nstatic struct dtd_rockchip_rk3288_dw_mshc dtv_mmc_at_ff500000 = {\n\t.bus_width\t\t= 0x4,\n\t.cap_sd_highspeed\t= true,\n\t.clocks\t\t\t= {\n\t\t\t{0, {317}},\n\t\t\t{0, {33}},\n\t\t\t{0, {74}},\n\t\t\t{0, {78}},},\n\t.disable_wp\t\t= true,\n\t.fifo_depth\t\t= 0x100,\n\t.interrupts\t\t= {0x0, 0xc, 0x4},\n\t.max_frequency\t\t= 0x8f0d180,\n\t.pinctrl_0\t\t= {0x47, 0x48, 0x49, 0x4a},\n\t.pinctrl_names\t\t= \"default\",\n\t.reg\t\t\t= {0xff500000, 0x4000},\n\t.sd_uhs_sdr104\t\t= true,\n\t.sd_uhs_sdr12\t\t= true,\n\t.sd_uhs_sdr25\t\t= true,\n\t.sd_uhs_sdr50\t\t= true,\n\t.u_boot_spl_fifo_mode\t= true,\n\t.vmmc_supply\t\t= 0x4b,\n\t.vqmmc_supply\t\t= 0x1e,\n};\nU_BOOT_DRVINFO(mmc_at_ff500000) = {\n\t.name\t\t= \"rockchip_rk3288_dw_mshc\",\n\t.plat\t\t= &dtv_mmc_at_ff500000,\n\t.plat_size\t= sizeof(dtv_mmc_at_ff500000),\n\t.parent_idx\t= -1,\n};\n\n/*\n * Node /serial@ff130000 index 3\n * driver ns16550_serial parent None\n */\nstatic struct dtd_ns16550_serial dtv_serial_at_ff130000 = {\n\t.clock_frequency\t= 0x16e3600,\n\t.clocks\t\t\t= {\n\t\t\t{0, {40}},\n\t\t\t{0, {212}},},\n\t.dma_names\t\t= {\"tx\", \"rx\"},\n\t.dmas\t\t\t= {0x10, 0x6, 0x10, 0x7},\n\t.interrupts\t\t= {0x0, 0x39, 0x4},\n\t.pinctrl_0\t\t= 0x26,\n\t.pinctrl_names\t\t= \"default\",\n\t.reg\t\t\t= {0xff130000, 0x100},\n\t.reg_io_width\t\t= 0x4,\n\t.reg_shift\t\t= 0x2,\n};\nU_BOOT_DRVINFO(serial_at_ff130000) = {\n\t.name\t\t= \"ns16550_serial\",\n\t.plat\t\t= &dtv_serial_at_ff130000,\n\t.plat_size\t= sizeof(dtv_serial_at_ff130000),\n\t.parent_idx\t= -1,\n};\n\n/*\n * Node /syscon@ff100000 index 4\n * driver rockchip_rk3328_grf parent None\n */\nstatic struct dtd_rockchip_rk3328_grf dtv_syscon_at_ff100000 = {\n\t.reg\t\t\t= {0xff100000, 0x1000},\n};\nU_BOOT_DRVINFO(syscon_at_ff100000) = {\n\t.name\t\t= \"rockchip_rk3328_grf\",\n\t.plat\t\t= &dtv_syscon_at_ff100000,\n\t.plat_size\t= sizeof(dtv_syscon_at_ff100000),\n\t.parent_idx\t= -1,\n};\n\n"
  },
  {
    "path": "package/boot/uboot-rockchip/src/of-platdata/orangepi-r1-plus-lts-rk3328/dt-structs-gen.h",
    "content": "/*\n * DO NOT MODIFY\n *\n * Defines the structs used to hold devicetree data.\n * This was generated by dtoc from a .dtb (device tree binary) file.\n */\n\n#include <stdbool.h>\n#include <linux/libfdt.h>\nstruct dtd_ns16550_serial {\n\tfdt32_t\t\tclock_frequency;\n\tstruct phandle_1_arg clocks[2];\n\tconst char *\tdma_names[2];\n\tfdt32_t\t\tdmas[4];\n\tfdt32_t\t\tinterrupts[3];\n\tfdt32_t\t\tpinctrl_0;\n\tconst char *\tpinctrl_names;\n\tfdt64_t\t\treg[2];\n\tfdt32_t\t\treg_io_width;\n\tfdt32_t\t\treg_shift;\n};\nstruct dtd_rockchip_rk3288_dw_mshc {\n\tfdt32_t\t\tbus_width;\n\tbool\t\tcap_sd_highspeed;\n\tstruct phandle_1_arg clocks[4];\n\tbool\t\tdisable_wp;\n\tfdt32_t\t\tfifo_depth;\n\tfdt32_t\t\tinterrupts[3];\n\tfdt32_t\t\tmax_frequency;\n\tfdt32_t\t\tpinctrl_0[4];\n\tconst char *\tpinctrl_names;\n\tfdt64_t\t\treg[2];\n\tbool\t\tsd_uhs_sdr104;\n\tbool\t\tsd_uhs_sdr12;\n\tbool\t\tsd_uhs_sdr25;\n\tbool\t\tsd_uhs_sdr50;\n\tbool\t\tu_boot_spl_fifo_mode;\n\tfdt32_t\t\tvmmc_supply;\n\tfdt32_t\t\tvqmmc_supply;\n};\nstruct dtd_rockchip_rk3328_cru {\n\tfdt64_t\t\treg[2];\n\tfdt32_t\t\trockchip_grf;\n};\nstruct dtd_rockchip_rk3328_dmc {\n\tfdt64_t\t\treg[12];\n\tfdt32_t\t\trockchip_sdram_params[196];\n};\nstruct dtd_rockchip_rk3328_grf {\n\tfdt64_t\t\treg[2];\n};\n"
  },
  {
    "path": "package/boot/uboot-rockchip/src/of-platdata/orangepi-r1-plus-rk3328/dt-decl.h",
    "content": "/*\n * DO NOT MODIFY\n *\n * Declares externs for all device/uclass instances.\n * This was generated by dtoc from a .dtb (device tree binary) file.\n */\n\n#include <dm/device-internal.h>\n#include <dm/uclass-internal.h>\n\n/* driver declarations - these allow DM_DRIVER_GET() to be used */\nextern U_BOOT_DRIVER(rockchip_rk3328_cru);\nextern U_BOOT_DRIVER(rockchip_rk3328_dmc);\nextern U_BOOT_DRIVER(rockchip_rk3288_dw_mshc);\nextern U_BOOT_DRIVER(ns16550_serial);\nextern U_BOOT_DRIVER(rockchip_rk3328_grf);\n\n/* uclass driver declarations - needed for DM_UCLASS_DRIVER_REF() */\nextern UCLASS_DRIVER(clk);\nextern UCLASS_DRIVER(mmc);\nextern UCLASS_DRIVER(ram);\nextern UCLASS_DRIVER(serial);\nextern UCLASS_DRIVER(syscon);\n"
  },
  {
    "path": "package/boot/uboot-rockchip/src/of-platdata/orangepi-r1-plus-rk3328/dt-plat.c",
    "content": "/*\n * DO NOT MODIFY\n *\n * Declares the U_BOOT_DRIVER() records and platform data.\n * This was generated by dtoc from a .dtb (device tree binary) file.\n */\n\n/* Allow use of U_BOOT_DRVINFO() in this file */\n#define DT_PLAT_C\n\n#include <common.h>\n#include <dm.h>\n#include <dt-structs.h>\n\n/*\n * driver_info declarations, ordered by 'struct driver_info' linker_list idx:\n *\n * idx  driver_info          driver\n * ---  -------------------- --------------------\n *   0: clock_controller_at_ff440000 rockchip_rk3328_cru\n *   1: dmc                  rockchip_rk3328_dmc\n *   2: mmc_at_ff500000      rockchip_rk3288_dw_mshc\n *   3: serial_at_ff130000   ns16550_serial\n *   4: syscon_at_ff100000   rockchip_rk3328_grf\n * ---  -------------------- --------------------\n */\n\n/*\n * Node /clock-controller@ff440000 index 0\n * driver rockchip_rk3328_cru parent None\n */\nstatic struct dtd_rockchip_rk3328_cru dtv_clock_controller_at_ff440000 = {\n\t.reg\t\t\t= {0xff440000, 0x1000},\n\t.rockchip_grf\t\t= 0x3a,\n};\nU_BOOT_DRVINFO(clock_controller_at_ff440000) = {\n\t.name\t\t= \"rockchip_rk3328_cru\",\n\t.plat\t\t= &dtv_clock_controller_at_ff440000,\n\t.plat_size\t= sizeof(dtv_clock_controller_at_ff440000),\n\t.parent_idx\t= -1,\n};\n\n/*\n * Node /dmc index 1\n * driver rockchip_rk3328_dmc parent None\n */\nstatic struct dtd_rockchip_rk3328_dmc dtv_dmc = {\n\t.reg\t\t\t= {0xff400000, 0x1000, 0xff780000, 0x3000, 0xff100000, 0x1000, 0xff440000, 0x1000,\n\t\t0xff720000, 0x1000, 0xff798000, 0x1000},\n\t.rockchip_sdram_params\t= {0x1, 0xa, 0x2, 0x1, 0x0, 0x0, 0x11, 0x0,\n\t\t0x11, 0x0, 0x0, 0x94291288, 0x0, 0x27, 0x462, 0x15,\n\t\t0x242, 0xff, 0x14d, 0x0, 0x1, 0x0, 0x0, 0x0,\n\t\t0x43049010, 0x64, 0x28003b, 0xd0, 0x20053, 0xd4, 0x220000, 0xd8,\n\t\t0x100, 0xdc, 0x40000, 0xe0, 0x0, 0xe4, 0x110000, 0xe8,\n\t\t0x420, 0xec, 0x400, 0xf4, 0xf011f, 0x100, 0x9060b06, 0x104,\n\t\t0x20209, 0x108, 0x505040a, 0x10c, 0x40400c, 0x110, 0x5030206, 0x114,\n\t\t0x3030202, 0x120, 0x3030b03, 0x124, 0x20208, 0x180, 0x1000040, 0x184,\n\t\t0x0, 0x190, 0x7030003, 0x198, 0x5001100, 0x1a0, 0xc0400003, 0x240,\n\t\t0x6000604, 0x244, 0x201, 0x250, 0xf00, 0x490, 0x1, 0xffffffff,\n\t\t0xffffffff, 0xffffffff, 0xffffffff, 0x4, 0xc, 0x28, 0xa, 0x2c,\n\t\t0x0, 0x30, 0x9, 0xffffffff, 0xffffffff, 0x77, 0x88, 0x79,\n\t\t0x79, 0x87, 0x97, 0x87, 0x78, 0x77, 0x78, 0x87,\n\t\t0x88, 0x87, 0x87, 0x77, 0x78, 0x78, 0x78, 0x78,\n\t\t0x78, 0x78, 0x78, 0x78, 0x78, 0x69, 0x9, 0x77,\n\t\t0x78, 0x77, 0x78, 0x77, 0x78, 0x77, 0x78, 0x77,\n\t\t0x79, 0x9, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78,\n\t\t0x78, 0x78, 0x78, 0x69, 0x9, 0x77, 0x78, 0x77,\n\t\t0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x79, 0x9,\n\t\t0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78,\n\t\t0x78, 0x69, 0x9, 0x77, 0x78, 0x77, 0x78, 0x77,\n\t\t0x78, 0x77, 0x78, 0x77, 0x79, 0x9, 0x78, 0x78,\n\t\t0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x69,\n\t\t0x9, 0x77, 0x78, 0x77, 0x77, 0x77, 0x77, 0x77,\n\t\t0x77, 0x77, 0x79, 0x9},\n};\nU_BOOT_DRVINFO(dmc) = {\n\t.name\t\t= \"rockchip_rk3328_dmc\",\n\t.plat\t\t= &dtv_dmc,\n\t.plat_size\t= sizeof(dtv_dmc),\n\t.parent_idx\t= -1,\n};\n\n/*\n * Node /mmc@ff500000 index 2\n * driver rockchip_rk3288_dw_mshc parent None\n */\nstatic struct dtd_rockchip_rk3288_dw_mshc dtv_mmc_at_ff500000 = {\n\t.bus_width\t\t= 0x4,\n\t.cap_sd_highspeed\t= true,\n\t.clocks\t\t\t= {\n\t\t\t{0, {317}},\n\t\t\t{0, {33}},\n\t\t\t{0, {74}},\n\t\t\t{0, {78}},},\n\t.disable_wp\t\t= true,\n\t.fifo_depth\t\t= 0x100,\n\t.interrupts\t\t= {0x0, 0xc, 0x4},\n\t.max_frequency\t\t= 0x8f0d180,\n\t.pinctrl_0\t\t= {0x47, 0x48, 0x49, 0x4a},\n\t.pinctrl_names\t\t= \"default\",\n\t.reg\t\t\t= {0xff500000, 0x4000},\n\t.sd_uhs_sdr104\t\t= true,\n\t.sd_uhs_sdr12\t\t= true,\n\t.sd_uhs_sdr25\t\t= true,\n\t.sd_uhs_sdr50\t\t= true,\n\t.u_boot_spl_fifo_mode\t= true,\n\t.vmmc_supply\t\t= 0x4b,\n\t.vqmmc_supply\t\t= 0x1e,\n};\nU_BOOT_DRVINFO(mmc_at_ff500000) = {\n\t.name\t\t= \"rockchip_rk3288_dw_mshc\",\n\t.plat\t\t= &dtv_mmc_at_ff500000,\n\t.plat_size\t= sizeof(dtv_mmc_at_ff500000),\n\t.parent_idx\t= -1,\n};\n\n/*\n * Node /serial@ff130000 index 3\n * driver ns16550_serial parent None\n */\nstatic struct dtd_ns16550_serial dtv_serial_at_ff130000 = {\n\t.clock_frequency\t= 0x16e3600,\n\t.clocks\t\t\t= {\n\t\t\t{0, {40}},\n\t\t\t{0, {212}},},\n\t.dma_names\t\t= {\"tx\", \"rx\"},\n\t.dmas\t\t\t= {0x10, 0x6, 0x10, 0x7},\n\t.interrupts\t\t= {0x0, 0x39, 0x4},\n\t.pinctrl_0\t\t= 0x26,\n\t.pinctrl_names\t\t= \"default\",\n\t.reg\t\t\t= {0xff130000, 0x100},\n\t.reg_io_width\t\t= 0x4,\n\t.reg_shift\t\t= 0x2,\n};\nU_BOOT_DRVINFO(serial_at_ff130000) = {\n\t.name\t\t= \"ns16550_serial\",\n\t.plat\t\t= &dtv_serial_at_ff130000,\n\t.plat_size\t= sizeof(dtv_serial_at_ff130000),\n\t.parent_idx\t= -1,\n};\n\n/*\n * Node /syscon@ff100000 index 4\n * driver rockchip_rk3328_grf parent None\n */\nstatic struct dtd_rockchip_rk3328_grf dtv_syscon_at_ff100000 = {\n\t.reg\t\t\t= {0xff100000, 0x1000},\n};\nU_BOOT_DRVINFO(syscon_at_ff100000) = {\n\t.name\t\t= \"rockchip_rk3328_grf\",\n\t.plat\t\t= &dtv_syscon_at_ff100000,\n\t.plat_size\t= sizeof(dtv_syscon_at_ff100000),\n\t.parent_idx\t= -1,\n};\n\n"
  },
  {
    "path": "package/boot/uboot-rockchip/src/of-platdata/orangepi-r1-plus-rk3328/dt-structs-gen.h",
    "content": "/*\n * DO NOT MODIFY\n *\n * Defines the structs used to hold devicetree data.\n * This was generated by dtoc from a .dtb (device tree binary) file.\n */\n\n#include <stdbool.h>\n#include <linux/libfdt.h>\nstruct dtd_ns16550_serial {\n\tfdt32_t\t\tclock_frequency;\n\tstruct phandle_1_arg clocks[2];\n\tconst char *\tdma_names[2];\n\tfdt32_t\t\tdmas[4];\n\tfdt32_t\t\tinterrupts[3];\n\tfdt32_t\t\tpinctrl_0;\n\tconst char *\tpinctrl_names;\n\tfdt64_t\t\treg[2];\n\tfdt32_t\t\treg_io_width;\n\tfdt32_t\t\treg_shift;\n};\nstruct dtd_rockchip_rk3288_dw_mshc {\n\tfdt32_t\t\tbus_width;\n\tbool\t\tcap_sd_highspeed;\n\tstruct phandle_1_arg clocks[4];\n\tbool\t\tdisable_wp;\n\tfdt32_t\t\tfifo_depth;\n\tfdt32_t\t\tinterrupts[3];\n\tfdt32_t\t\tmax_frequency;\n\tfdt32_t\t\tpinctrl_0[4];\n\tconst char *\tpinctrl_names;\n\tfdt64_t\t\treg[2];\n\tbool\t\tsd_uhs_sdr104;\n\tbool\t\tsd_uhs_sdr12;\n\tbool\t\tsd_uhs_sdr25;\n\tbool\t\tsd_uhs_sdr50;\n\tbool\t\tu_boot_spl_fifo_mode;\n\tfdt32_t\t\tvmmc_supply;\n\tfdt32_t\t\tvqmmc_supply;\n};\nstruct dtd_rockchip_rk3328_cru {\n\tfdt64_t\t\treg[2];\n\tfdt32_t\t\trockchip_grf;\n};\nstruct dtd_rockchip_rk3328_dmc {\n\tfdt64_t\t\treg[12];\n\tfdt32_t\t\trockchip_sdram_params[196];\n};\nstruct dtd_rockchip_rk3328_grf {\n\tfdt64_t\t\treg[2];\n};\n"
  },
  {
    "path": "package/boot/uboot-sunxi/Makefile",
    "content": "#\n# Copyright (C) 2013-2016 OpenWrt.org\n# Copyright (C) 2017 Yousong Zhou\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\ninclude $(INCLUDE_DIR)/kernel.mk\n\nPKG_VERSION:=2020.04\n\nPKG_HASH:=fe732aaf037d9cc3c0909bad8362af366ae964bbdac6913a34081ff4ad565372\n\nPKG_MAINTAINER:=Zoltan HERPAI <wigyori@uid0.hu>\n\ninclude $(INCLUDE_DIR)/u-boot.mk\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine U-Boot/Default\n  BUILD_TARGET:=sunxi\n  UBOOT_IMAGE:=u-boot-sunxi-with-spl.bin\n  UENV:=default\n  HIDDEN:=1\nendef\n\ndefine U-Boot/a64-olinuxino\n  BUILD_SUBTARGET:=cortexa53\n  NAME:=Olimex A64-OLinuXino\n  BUILD_DEVICES:=olimex_a64-olinuxino\n  DEPENDS:=+PACKAGE_u-boot-olimex_a64-olinuxino:arm-trusted-firmware-sunxi-a64\n  UENV:=a64\n  ATF:=a64\nendef\n\ndefine U-Boot/a64-olinuxino-emmc\n  BUILD_SUBTARGET:=cortexa53\n  NAME:=Olimex A64-OLinuXino eMMC\n  BUILD_DEVICES:=olimex_a64-olinuxino-emmc\n  DEPENDS:=+PACKAGE_u-boot-olimex_a64-olinuxino-emmc:arm-trusted-firmware-sunxi-a64\n  UENV:=a64\n  ATF:=a64\nendef\n\ndefine U-Boot/A10-OLinuXino-Lime\n  BUILD_SUBTARGET:=cortexa8\n  NAME:=A10 OLinuXino LIME\n  BUILD_DEVICES:=olimex_a10-olinuxino-lime\nendef\n\ndefine U-Boot/A13-OLinuXino\n  BUILD_SUBTARGET:=cortexa8\n  NAME:=A13 OlinuXino\n  BUILD_DEVICES:=olimex_a13-olinuxino\nendef\n\ndefine U-Boot/A20-OLinuXino-Lime\n  BUILD_SUBTARGET:=cortexa7\n  NAME:=A20 OLinuXino LIME\n  BUILD_DEVICES:=olimex_a20-olinuxino-lime\nendef\n\ndefine U-Boot/A20-OLinuXino-Lime2\n  BUILD_SUBTARGET:=cortexa7\n  NAME:=A20 OLinuXino LIME2\n  BUILD_DEVICES:=olimex_a20-olinuxino-lime2\nendef\n\ndefine U-Boot/A20-OLinuXino-Lime2-eMMC\n  BUILD_SUBTARGET:=cortexa7\n  NAME:=A20 OLinuXino LIME2 eMMC\n  BUILD_DEVICES:=olimex_a20-olinuxino-lime2-emmc\nendef\n\ndefine U-Boot/A20-OLinuXino_MICRO\n  BUILD_SUBTARGET:=cortexa7\n  NAME:=A20 OLinuXino MICRO\n  BUILD_DEVICES:=olimex_a20-olinuxino-micro\nendef\n\ndefine U-Boot/Bananapi\n  BUILD_SUBTARGET:=cortexa7\n  NAME:=Bananapi\n  BUILD_DEVICES:=lemaker_bananapi\nendef\n\ndefine U-Boot/Bananapro\n  BUILD_SUBTARGET:=cortexa7\n  NAME:=Bananapro\n  BUILD_DEVICES:=lemaker_bananapro\nendef\n\ndefine U-Boot/Cubieboard\n  BUILD_SUBTARGET:=cortexa8\n  NAME:=Cubieboard\n  BUILD_DEVICES:=cubietech_a10-cubieboard\nendef\n\ndefine U-Boot/Cubieboard2\n  BUILD_SUBTARGET:=cortexa7\n  NAME:=Cubieboard2\n  BUILD_DEVICES:=cubietech_cubieboard2\nendef\n\ndefine U-Boot/Cubietruck\n  BUILD_SUBTARGET:=cortexa7\n  NAME:=Cubietruck\n  BUILD_DEVICES:=cubietech_cubietruck\nendef\n\ndefine U-Boot/Hummingbird_A31\n  BUILD_SUBTARGET:=cortexa7\n  NAME:=Hummingbird A31 board\nendef\n\ndefine U-Boot/Marsboard_A10\n  BUILD_SUBTARGET:=cortexa8\n  NAME:=Marsboard\n  BUILD_DEVICES:=marsboard_a10-marsboard\nendef\n\ndefine U-Boot/Mele_M9\n  BUILD_SUBTARGET:=cortexa7\n  NAME:=Mele M9 (A31)\n  BUILD_DEVICES:=mele_m9\nendef\n\ndefine U-Boot/OLIMEX_A13_SOM\n  BUILD_SUBTARGET:=cortexa8\n  NAME:=Olimex A13 SOM\n  BUILD_DEVICES:=olimex_a13-olimex-som\nendef\n\ndefine U-Boot/Linksprite_pcDuino\n  BUILD_SUBTARGET:=cortexa8\n  NAME:=Linksprite pcDuino\n  BUILD_DEVICES:=linksprite_a10-pcduino\nendef\n\ndefine U-Boot/Linksprite_pcDuino3\n  BUILD_SUBTARGET:=cortexa7\n  NAME:=Linksprite pcDuino3\n  BUILD_DEVICES:=linksprite_pcduino3\nendef\n\ndefine U-Boot/Linksprite_pcDuino3_Nano\n  BUILD_SUBTARGET:=cortexa7\n  NAME:=Linksprite pcDuino3 Nano\n  BUILD_DEVICES:=linksprite_pcduino3-nano\nendef\n\ndefine U-Boot/Lamobo_R1\n  BUILD_SUBTARGET:=cortexa7\n  NAME:=Lamobo R1\n  BUILD_DEVICES:=lamobo_lamobo-r1\nendef\n\ndefine U-Boot/nanopi_m1_plus\n  BUILD_SUBTARGET:=cortexa7\n  NAME:=NanoPi M1 Plus (H3)\n  BUILD_DEVICES:=friendlyarm_nanopi-m1-plus\nendef\n\ndefine U-Boot/zeropi\n  BUILD_SUBTARGET:=cortexa7\n  NAME:=ZeroPi (H3)\n  BUILD_DEVICES:=friendlyarm_zeropi\nendef\n\ndefine U-Boot/nanopi_neo_air\n  BUILD_SUBTARGET:=cortexa7\n  NAME:=U-Boot for NanoPi NEO Air (H3)\n  BUILD_DEVICES:=friendlyarm_nanopi-neo-air\nendef\n\ndefine U-Boot/nanopi_neo\n  BUILD_SUBTARGET:=cortexa7\n  NAME:=U-Boot for NanoPi NEO (H3)\n  BUILD_DEVICES:=friendlyarm_nanopi-neo\nendef\n\ndefine U-Boot/nanopi_r1\n  BUILD_SUBTARGET:=cortexa7\n  NAME:=U-Boot for NanoPi R1 (H3)\n  BUILD_DEVICES:=friendlyarm_nanopi-r1\nendef\n\ndefine U-Boot/orangepi_r1\n  BUILD_SUBTARGET:=cortexa7\n  NAME:=Orange Pi R1 (H2+)\n  BUILD_DEVICES:=xunlong_orangepi-r1\nendef\n\ndefine U-Boot/orangepi_zero\n  BUILD_SUBTARGET:=cortexa7\n  NAME:=Orange Pi Zero (H2+)\n  BUILD_DEVICES:=xunlong_orangepi-zero\nendef\n\ndefine U-Boot/orangepi_one\n  BUILD_SUBTARGET:=cortexa7\n  NAME:=Orange Pi One (H3)\n  BUILD_DEVICES:=xunlong_orangepi-one\nendef\n\ndefine U-Boot/orangepi_one_plus\n  BUILD_SUBTARGET:=cortexa53\n  NAME:=Orange Pi One Plus (H6)\n  DEPENDS:=+PACKAGE_u-boot-orangepi_one_plus:arm-trusted-firmware-sunxi-h6\n  BUILD_DEVICES:=xunlong_orangepi-one-plus\n  UENV:=h6\n  ATF:=h6\nendef\n\ndefine U-Boot/orangepi_pc\n  BUILD_SUBTARGET:=cortexa7\n  NAME:=Orange Pi PC (H3)\n  BUILD_DEVICES:=xunlong_orangepi-pc\nendef\n\ndefine U-Boot/orangepi_pc_plus\n  BUILD_SUBTARGET:=cortexa7\n  NAME:=Orange Pi PC Plus (H3)\n  BUILD_DEVICES:=xunlong_orangepi-pc-plus\nendef\n\ndefine U-Boot/orangepi_plus\n  BUILD_SUBTARGET:=cortexa7\n  NAME:=Orange Pi Plus (H3)\n  BUILD_DEVICES:=xunlong_orangepi-plus\nendef\n\ndefine U-Boot/orangepi_2\n  BUILD_SUBTARGET:=cortexa7\n  NAME:=Orange Pi 2 (H3)\n  BUILD_DEVICES:=xunlong_orangepi-2\nendef\n\ndefine U-Boot/pangolin\n  BUILD_SUBTARGET:=cortexa7\n  NAME:=Theobroma A31-yQ7 devboard\n  UENV:=pangolin\nendef\n\ndefine U-Boot/libretech_all_h3_cc_h5\n  BUILD_SUBTARGET:=cortexa53\n  NAME:=Libre Computer ALL-H3-CC H5\n  BUILD_DEVICES:=libretech_all-h3-cc-h5\n  DEPENDS:=+PACKAGE_u-boot-libretech_all_h3_cc_h5:arm-trusted-firmware-sunxi-a64\n  UENV:=a64\n  ATF:=a64\nendef\n\ndefine U-Boot/nanopi_neo_plus2\n  BUILD_SUBTARGET:=cortexa53\n  NAME:=NanoPi NEO Plus2 (H5)\n  BUILD_DEVICES:=friendlyarm_nanopi-neo-plus2\n  DEPENDS:=+PACKAGE_u-boot-nanopi_neo_plus2:arm-trusted-firmware-sunxi-a64\n  UENV:=a64\n  ATF:=a64\nendef\n\ndefine U-Boot/nanopi_neo2\n  BUILD_SUBTARGET:=cortexa53\n  NAME:=NanoPi NEO2 (H5)\n  BUILD_DEVICES:=friendlyarm_nanopi-neo2\n  DEPENDS:=+PACKAGE_u-boot-nanopi_neo2:arm-trusted-firmware-sunxi-a64\n  UENV:=a64\n  ATF:=a64\nendef\n\ndefine U-Boot/nanopi_r1s_h5\n  BUILD_SUBTARGET:=cortexa53\n  NAME:=NanoPi R1S (H5)\n  BUILD_DEVICES:=friendlyarm_nanopi-r1s-h5\n  DEPENDS:=+PACKAGE_u-boot-nanopi_r1s_h5:arm-trusted-firmware-sunxi-a64\n  UENV:=a64\n  ATF:=a64\nendef\n\ndefine U-Boot/pine64_plus\n  BUILD_SUBTARGET:=cortexa53\n  NAME:=Pine64 Plus A64\n  BUILD_DEVICES:=pine64_pine64-plus\n  DEPENDS:=+PACKAGE_u-boot-pine64_plus:arm-trusted-firmware-sunxi-a64\n  UENV:=a64\n  ATF:=a64\nendef\n\ndefine U-Boot/bananapi_m2_plus_h3\n  BUILD_SUBTARGET:=cortexa7\n  NAME:=Bananapi M2 Plus H3\n  BUILD_DEVICES:=sinovoip_bananapi-m2-plus\nendef\n\ndefine U-Boot/sopine_baseboard\n  BUILD_SUBTARGET:=cortexa53\n  NAME:=Sopine Baseboard\n  BUILD_DEVICES:=pine64_sopine-baseboard\n  DEPENDS:=+PACKAGE_u-boot-sopine_baseboard:arm-trusted-firmware-sunxi-a64\n  UENV:=a64\n  ATF:=a64\nendef\n\n\ndefine U-Boot/orangepi_zero_plus\n  BUILD_SUBTARGET:=cortexa53\n  NAME:=Xunlong Orange Pi Zero Plus\n  BUILD_DEVICES:=xunlong_orangepi-zero-plus\n  DEPENDS:=+PACKAGE_u-boot-orangepi_zero_plus:arm-trusted-firmware-sunxi-a64\n  UENV:=a64\n  ATF:=a64\nendef\n\ndefine U-Boot/orangepi_pc2\n  BUILD_SUBTARGET:=cortexa53\n  NAME:=Xunlong Orange Pi PC2\n  BUILD_DEVICES:=xunlong_orangepi-pc2\n  DEPENDS:=+PACKAGE_u-boot-orangepi_pc2:arm-trusted-firmware-sunxi-a64\n  UENV:=a64\n  ATF:=a64\nendef\n\ndefine U-Boot/Bananapi_M2_Ultra\n  BUILD_SUBTARGET:=cortexa7\n  NAME:=Bananapi M2 Ultra\n  BUILD_DEVICES:=sinovoip_bananapi-m2-ultra\nendef\n\ndefine U-Boot/bananapi_m2_berry\n  BUILD_SUBTARGET:=cortexa7\n  NAME:=Bananapi M2 Berry\n  BUILD_DEVICES:=sinovoip_bananapi-m2-berry\nendef\n\nUBOOT_TARGETS := \\\n\ta64-olinuxino \\\n\ta64-olinuxino-emmc \\\n\tA10-OLinuXino-Lime \\\n\tA13-OLinuXino \\\n\tA20-OLinuXino-Lime \\\n\tA20-OLinuXino-Lime2 \\\n\tA20-OLinuXino-Lime2-eMMC \\\n\tA20-OLinuXino_MICRO \\\n\tbananapi_m2_plus_h3 \\\n\tBananapi \\\n\tbananapi_m2_berry \\\n\tBananapi_M2_Ultra \\\n\tBananapro \\\n\tCubieboard \\\n\tCubieboard2 \\\n\tCubietruck \\\n\tHummingbird_A31 \\\n\tMarsboard_A10 \\\n\tMele_M9 \\\n\tOLIMEX_A13_SOM \\\n\tLinksprite_pcDuino \\\n\tLinksprite_pcDuino3 \\\n\tLinksprite_pcDuino3_Nano \\\n\tLamobo_R1 \\\n\tnanopi_m1_plus \\\n\tzeropi \\\n\tnanopi_neo \\\n\tnanopi_neo_air \\\n\tnanopi_neo_plus2 \\\n\tnanopi_neo2 \\\n\tnanopi_r1 \\\n\tnanopi_r1s_h5 \\\n\torangepi_zero \\\n\torangepi_r1 \\\n\torangepi_one \\\n\torangepi_one_plus \\\n\torangepi_pc \\\n\torangepi_pc_plus \\\n\torangepi_plus \\\n\torangepi_2 \\\n\torangepi_pc2 \\\n\tpangolin \\\n\tpine64_plus \\\n\tsopine_baseboard \\\n\torangepi_zero_plus \\\n\tlibretech_all_h3_cc_h5\n\nUBOOT_CONFIGURE_VARS += USE_PRIVATE_LIBGCC=yes\n\nUBOOT_MAKE_FLAGS += \\\n\tBL31=$(STAGING_DIR_IMAGE)/bl31_sun50i_$(ATF).bin\n\ndefine Build/InstallDev\n\t$(INSTALL_DIR) $(STAGING_DIR_IMAGE)\n\t$(CP) $(PKG_BUILD_DIR)/$(UBOOT_IMAGE) $(STAGING_DIR_IMAGE)/$(BUILD_DEVICES)-u-boot-with-spl.bin\n\tmkimage -C none -A arm -T script -d uEnv-$(UENV).txt \\\n\t\t$(STAGING_DIR_IMAGE)/$(BUILD_DEVICES)-boot.scr\nendef\n\ndefine Package/u-boot/install/default\nendef\n\n$(eval $(call BuildPackage/U-Boot))\n"
  },
  {
    "path": "package/boot/uboot-sunxi/patches/002-add-olimex-a13-som.patch",
    "content": "--- /dev/null\n+++ b/configs/OLIMEX_A13_SOM_defconfig\n@@ -0,0 +1,17 @@\n+CONFIG_SPL=y\n+CONFIG_DEFAULT_DEVICE_TREE=\"sun5i-a13-olinuxino\"\n+CONFIG_ARM=y\n+CONFIG_ARCH_SUNXI=y\n+CONFIG_MACH_SUN5I=y\n+CONFIG_DRAM_CLK=408\n+CONFIG_DRAM_ZQ=123\n+CONFIG_DRAM_EMR1=0\n+# CONFIG_CMD_IMLS is not set\n+# CONFIG_CMD_FLASH is not set\n+# CONFIG_CMD_FPGA is not set\n+CONFIG_DM_SERIAL=y\n+CONFIG_USB=y\n+CONFIG_DM_USB=y\n+CONFIG_SYS_NS16550=y\n+CONFIG_SUNXI_NO_PMIC=y\n+CONFIG_USB_EHCI_HCD=y\n"
  },
  {
    "path": "package/boot/uboot-sunxi/patches/003-add-theobroma-a31-pangolin.patch",
    "content": "--- a/arch/arm/dts/Makefile\n+++ b/arch/arm/dts/Makefile\n@@ -455,6 +455,7 @@ dtb-$(CONFIG_MACH_SUN6I) += \\\n \tsun6i-a31-m9.dtb \\\n \tsun6i-a31-mele-a1000g-quad.dtb \\\n \tsun6i-a31-mixtile-loftq.dtb \\\n+\tsun6i-a31-pangolin.dtb \\\n \tsun6i-a31s-colorfly-e708-q1.dtb \\\n \tsun6i-a31s-cs908.dtb \\\n \tsun6i-a31s-inet-q972.dtb \\\n--- a/arch/arm/dts/sun6i-a31.dtsi\n+++ b/arch/arm/dts/sun6i-a31.dtsi\n@@ -641,6 +641,11 @@\n \t\t\t\tfunction = \"lcd0\";\n \t\t\t};\n \n+\t\t\ti2c3_pins_a: i2c3@0 {\n+\t\t\t\tallwinner,pins = \"PB5\", \"PB6\";\n+\t\t\t\tallwinner,function = \"i2c3\";\n+\t\t\t};\n+\n \t\t\tmmc0_pins_a: mmc0@0 {\n \t\t\t\tpins = \"PF0\", \"PF1\", \"PF2\",\n \t\t\t\t\t\t \"PF3\", \"PF4\", \"PF5\";\n--- /dev/null\n+++ b/arch/arm/dts/sun6i-a31-pangolin.dts\n@@ -0,0 +1,292 @@\n+/*\n+ * Copyright 2015, Theobroma Systems Design und Consulting GmbH\n+ *\n+ * This file is dual-licensed: you can use it either under the terms\n+ * of the GPL or the X11 license, at your option. Note that this dual\n+ * licensing only applies to this file, and not this project as a\n+ * whole.\n+ *\n+ *  a) This file is free software; you can redistribute it and/or\n+ *     modify it under the terms of the GNU General Public License as\n+ *     published by the Free Software Foundation; either version 2 of the\n+ *     License, or (at your option) any later version.\n+ *\n+ *     This file is distributed in the hope that it will be useful,\n+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of\n+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n+ *     GNU General Public License for more details.\n+ *\n+ * Or, alternatively,\n+ *\n+ *  b) Permission is hereby granted, free of charge, to any person\n+ *     obtaining a copy of this software and associated documentation\n+ *     files (the \"Software\"), to deal in the Software without\n+ *     restriction, including without limitation the rights to use,\n+ *     copy, modify, merge, publish, distribute, sublicense, and/or\n+ *     sell copies of the Software, and to permit persons to whom the\n+ *     Software is furnished to do so, subject to the following\n+ *     conditions:\n+ *\n+ *     The above copyright notice and this permission notice shall be\n+ *     included in all copies or substantial portions of the Software.\n+ *\n+ *     THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n+ *     OTHER DEALINGS IN THE SOFTWARE.\n+ */\n+\n+/dts-v1/;\n+#include \"sun6i-a31.dtsi\"\n+#include \"sunxi-common-regulators.dtsi\"\n+\n+#include <dt-bindings/gpio/gpio.h>\n+#include <dt-bindings/pinctrl/sun4i-a10.h>\n+\n+/ {\n+\tmodel = \"Theobroma Systems A31 Pangolin\";\n+\tcompatible = \"tsd,a31-pangolin\", \"allwinner,sun6i-a31\";\n+\n+\taliases {\n+\t\tserial0 = &uart0;\n+\t\tserial2 = &uart2;\n+\t\tspi0 = &spi0;\n+\t\tspi1 = &spi1;\n+\t\tspi2 = &spi2;\n+\t\tspi3 = &spi3;\n+\t};\n+\n+\tchosen {\n+\t\tstdout-path = \"serial2:115200n8\";\n+\t};\n+};\n+\n+&ehci0 {\n+\tstatus = \"okay\";\n+};\n+\n+&ohci0 {\n+\tstatus = \"okay\";\n+};\n+\n+&ehci1 {\n+\tstatus = \"okay\";\n+};\n+\n+&ohci1 {\n+\tstatus = \"okay\";\n+};\n+\n+&ohci2 {\n+\tstatus = \"okay\";\n+};\n+\n+&gmac {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&gmac_pins_rgmii_a>;\n+\tphy = <&phy1>;\n+\tphy-mode = \"rgmii\";\n+\tsnps,reset-gpio = <&pio 0 7 GPIO_ACTIVE_LOW>;\n+\tsnps,reset-active-low;\n+\tsnps,reset-delays-us = <0 10000 30000>;\n+\tstatus = \"okay\";\n+\n+\tphy1: ethernet-phy@4 {\n+\t\treg = <4>;\n+\t};\n+};\n+\n+&i2c0 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&i2c0_pins_a>;\n+\tstatus = \"okay\";\n+};\n+\n+&i2c1 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&i2c1_pins_a>;\n+\tstatus = \"okay\";\n+};\n+\n+&i2c2 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&i2c2_pins_a>;\n+\tstatus = \"okay\";\n+};\n+\n+&i2c3 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&i2c3_pins_a>;\n+\tstatus = \"okay\";\n+\n+\trtc_twi: rtc@6f {\n+\t compatible = \"isil,isl1208\";\n+\t reg = <0x6f>;\n+\t};\n+\tfan: fan@18 {\n+\t\tcompatible = \"ti,amc6821\";\n+\t\treg = <0x18>;\n+\t\tcooling-min-state = <0>;\n+\t\tcooling-max-state = <9>;\n+\t\t#cooling-cells = <2>;\n+\t};\n+};\n+\n+&spi0 {\n+\tstatus = \"okay\";\n+\n+\tflash: flash@0 {\n+\t\tcompatible = \"spansion,m25p40\";\n+\t\tspi-max-frequency = <16000000>;\n+\t\tspi-cpol;\n+\t\tspi-cpha;\n+\t};\n+};\n+\n+&spi1 {\n+\tstatus = \"okay\";\n+};\n+\n+&ir {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&ir_pins_a>;\n+\tstatus = \"okay\";\n+};\n+\n+&mmc0 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_pangolin>;\n+\tvmmc-supply = <&reg_vcc3v0>;\n+\tbus-width = <4>;\n+\tcd-gpios = <&pio 2 19 GPIO_ACTIVE_LOW>; /* PC19 */\n+\tstatus = \"okay\";\n+};\n+\n+&mmc0_pins_a {\n+\t/* external pull-ups missing for some pins */\n+\tallwinner,pull = <SUN4I_PINCTRL_PULL_UP>;\n+};\n+\n+&mmc2 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&mmc2_pins_a>;\n+\tvmmc-supply = <&reg_vcc3v0>;\n+\tbus-width = <8>;\n+\tnon-removable;\n+\tstatus = \"okay\";\n+};\n+\n+&pio {\n+\tmmc0_cd_pin_pangolin: mmc0_cd_pin@0 {\n+\t\tallwinner,pins = \"PC19\";\n+\t\tallwinner,function = \"gpio_in\";\n+\t\tallwinner,drive = <SUN4I_PINCTRL_10_MA>;\n+\t\tallwinner,pull = <SUN4I_PINCTRL_PULL_UP>;\n+\t};\n+\n+\tleds_pins_pangolin: led_pins@0 {\n+\t\tallwinner,pins = \"PH7\", \"PC16\";\n+\t\tallwinner,function = \"gpio_out\";\n+\t\tallwinner,drive = <SUN4I_PINCTRL_20_MA>;\n+\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n+\t};\n+\n+\tmmc2_pins_a: mmc2@0 {\n+\t\tallwinner,pins = \"PC6\",\"PC7\",\"PC8\",\"PC9\",\"PC10\",\"PC11\",\n+\t\t\t\t\"PC12\",\"PC13\",\"PC14\",\"PC15\";\n+\t\tallwinner,function = \"mmc2\";\n+\t\tallwinner,drive = <SUN4I_PINCTRL_30_MA>;\n+\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n+\t};\n+};\n+\n+&p2wi {\n+\tstatus = \"okay\";\n+\n+\taxp221: pmic@68 {\n+\t\tcompatible = \"x-powers,axp221\";\n+\t\treg = <0x68>;\n+\t\tinterrupt-parent = <&nmi_intc>;\n+\t\tinterrupts = <0 IRQ_TYPE_LEVEL_LOW>;\n+\t\tinterrupt-controller;\n+\t\t#interrupt-cells = <1>;\n+\t\tdcdc1-supply = <&vcc_3v0>;\n+\t\tdcdc5-supply = <&vcc_dram>;\n+\n+\t\tregulators {\n+\t\t\tx-powers,dcdc-freq = <3000>;\n+\n+\t\t\tvcc_3v0: dcdc1 {\n+\t\t\t\tregulator-always-on;\n+\t\t\t\tregulator-min-microvolt = <3000000>;\n+\t\t\t\tregulator-max-microvolt = <3000000>;\n+\t\t\t\tregulator-name = \"vcc-3v0\";\n+\t\t\t};\n+\n+\t\t\tvdd_cpu: dcdc2 {\n+\t\t\t\tregulator-always-on;\n+\t\t\t\tregulator-min-microvolt = <700000>;\n+\t\t\t\tregulator-max-microvolt = <1320000>;\n+\t\t\t\tregulator-name = \"vdd-cpu\";\n+\t\t\t};\n+\n+\t\t\tvdd_gpu: dcdc3 {\n+\t\t\t\tregulator-always-on;\n+\t\t\t\tregulator-min-microvolt = <700000>;\n+\t\t\t\tregulator-max-microvolt = <1320000>;\n+\t\t\t\tregulator-name = \"vdd-gpu\";\n+\t\t\t};\n+\n+\t\t\tvdd_sys_dll: dcdc4 {\n+\t\t\t\tregulator-always-on;\n+\t\t\t\tregulator-min-microvolt = <1100000>;\n+\t\t\t\tregulator-max-microvolt = <1100000>;\n+\t\t\t\tregulator-name = \"vdd-sys-dll\";\n+\t\t\t};\n+\n+\t\t\tvcc_dram: dcdc5 {\n+\t\t\t\tregulator-always-on;\n+\t\t\t\tregulator-min-microvolt = <1500000>;\n+\t\t\t\tregulator-max-microvolt = <1500000>;\n+\t\t\t\tregulator-name = \"vcc-dram\";\n+\t\t\t};\n+\n+\t\t\tvcc_wifi: aldo1 {\n+\t\t\t\tregulator-min-microvolt = <3300000>;\n+\t\t\t\tregulator-max-microvolt = <3300000>;\n+\t\t\t\tregulator-name = \"vcc_wifi\";\n+\t\t\t};\n+\n+\t\t\tavcc: aldo3 {\n+\t\t\t\tregulator-always-on;\n+\t\t\t\tregulator-min-microvolt = <3000000>;\n+\t\t\t\tregulator-max-microvolt = <3000000>;\n+\t\t\t\tregulator-name = \"avcc\";\n+\t\t\t};\n+\t\t};\n+\t};\n+};\n+\n+&uart0 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&uart0_pins_a>;\n+\tstatus = \"okay\";\n+};\n+\n+&usb1_vbus_pin_a {\n+\tallwinner,pins = \"PD23\";\n+};\n+\n+&reg_usb1_vbus {\n+\tgpio = <&pio 3 23 GPIO_ACTIVE_HIGH>; /* PD 23 */\n+\tstatus = \"okay\";\n+};\n+\n+&usbphy {\n+\tstatus = \"okay\";\n+\tusb1_vbus-supply = <&reg_usb1_vbus>;\n+};\n--- /dev/null\n+++ b/configs/pangolin_defconfig\n@@ -0,0 +1,36 @@\n+CONFIG_SUNXI_PANGOLIN=y\n+CONFIG_SPL=y\n+CONFIG_SYS_EXTRA_OPTIONS=\"USB_EHCI,SUNXI_GMAC,RGMII\"\n+CONFIG_DEFAULT_DEVICE_TREE=\"sun6i-a31-pangolin\"\n+CONFIG_VIDEO_VGA_VIA_LCD=y\n+CONFIG_VIDEO_VGA_EXTERNAL_DAC_EN=\"PH25\"\n+CONFIG_ARM=y\n+CONFIG_ARCH_SUNXI=y\n+CONFIG_MACH_SUN6I=y\n+CONFIG_DRAM_CHANNELS=1\n+CONFIG_DRAM_CLK=360\n+CONFIG_DRAM_ZQ=70\n+CONFIG_AXP_DCDC1_VOLT=3300\n+CONFIG_AXP_ALDO1_VOLT=0\n+CONFIG_AXP_ALDO2_VOLT=1800\n+CONFIG_AXP_ALDO3_VOLT=3000\n+CONFIG_AXP_DLDO4_VOLT=3300\n+CONFIG_AXP_ELDO1_VOLT=1200\n+CONFIG_AXP_ELDO2_VOLT=2500\n+CONFIG_AXP_ELDO3_VOLT=3300\n+CONFIG_MMC_SUNXI_SLOT_EXTRA=2\n+CONFIG_CONS_INDEX=3\n+# Vbus gpio for usb1\n+CONFIG_USB1_VBUS_PIN=\"\"\n+# No Vbus gpio for usb2\n+CONFIG_USB2_VBUS_PIN=\"\"\n+CONFIG_USB=y\n+CONFIG_DM_USB=y\n+CONFIG_USB_EHCI=y\n+CONFIG_USB_KEYBOARD=y\n+CONFIG_DM_ETH=y\n+CONFIG_CMD_IMLS=n\n+CONFIG_ETH_DESIGNWARE=y\n+CONFIG_DM_SPI=y\n+CONFIG_DM_SPI_FLASH=y\n+CONFIG_SUNXI_SPI=y\n--- a/arch/arm/mach-sunxi/Kconfig\n+++ b/arch/arm/mach-sunxi/Kconfig\n@@ -896,6 +896,14 @@ config VIDEO_LCD_PANEL_I2C_SCL\n \tSet the SCL pin for the LCD i2c interface. This takes a string in the\n \tformat understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.\n \n+choice\n+\tprompt \"Sunxi Board Variant\"\n+\toptional\n+\n+config SUNXI_PANGOLIN\n+\tbool \"Theobroma A31 uQ7 Board\"\n+\n+endchoice\n \n # Note only one of these may be selected at a time! But hidden choices are\n # not supported by Kconfig\n"
  },
  {
    "path": "package/boot/uboot-sunxi/patches/062-A20-improve-gmac-upload.patch",
    "content": "  GNU nano 2.7.4                                                    File: 062-A20-improve-gmac-upload.patch\n\n--- a/configs/A20-OLinuXino-Lime2_defconfig\n+++ b/configs/A20-OLinuXino-Lime2_defconfig\n@@ -22,6 +22,7 @@ CONFIG_ETH_DESIGNWARE=y\n CONFIG_RGMII=y\n CONFIG_MII=y\n CONFIG_SUN7I_GMAC=y\n+CONFIG_GMAC_TX_DELAY=1\n CONFIG_AXP_ALDO3_VOLT=2800\n CONFIG_AXP_ALDO3_VOLT_SLOPE_08=y\n CONFIG_AXP_ALDO3_INRUSH_QUIRK=y\n"
  },
  {
    "path": "package/boot/uboot-sunxi/patches/063-fix-lime2-revK-add-micrel-PHY.patch",
    "content": "--- a/configs/A20-OLinuXino-Lime2-eMMC_defconfig\n+++ b/configs/A20-OLinuXino-Lime2-eMMC_defconfig\n@@ -8,6 +8,8 @@ CONFIG_MMC_SUNXI_SLOT_EXTRA=2\n CONFIG_USB0_VBUS_PIN=\"PC17\"\n CONFIG_USB0_VBUS_DET=\"PH5\"\n CONFIG_I2C1_ENABLE=y\n+CONFIG_PHY_MICREL=y\n+CONFIG_PHY_MICREL_KSZ90X1=y\n CONFIG_SATAPWR=\"PC3\"\n CONFIG_SPL_SPI_SUNXI=y\n CONFIG_AHCI=y\n--- a/configs/A20-OLinuXino-Lime2_defconfig\n+++ b/configs/A20-OLinuXino-Lime2_defconfig\n@@ -7,6 +7,8 @@ CONFIG_MMC0_CD_PIN=\"PH1\"\n CONFIG_USB0_VBUS_PIN=\"PC17\"\n CONFIG_USB0_VBUS_DET=\"PH5\"\n CONFIG_I2C1_ENABLE=y\n+CONFIG_PHY_MICREL=y\n+CONFIG_PHY_MICREL_KSZ90X1=y\n CONFIG_SATAPWR=\"PC3\"\n CONFIG_AHCI=y\n # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set\n--- a/drivers/net/phy/micrel_ksz90x1.c\n+++ b/drivers/net/phy/micrel_ksz90x1.c\n@@ -14,6 +14,8 @@\n #include <errno.h>\n #include <micrel.h>\n #include <phy.h>\n+#include <asm/io.h>\n+#include <asm/arch/clock.h>\n \n /*\n  * KSZ9021 - KSZ9031 common\n@@ -344,6 +346,10 @@ static int ksz9031_phy_extwrite(struct p\n static int ksz9031_config(struct phy_device *phydev)\n {\n \tint ret;\n+\tstruct sunxi_ccm_reg *const ccm =\n+\t\t(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;\n+\n+\tsetbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_DELAY(4));\n \n \tret = ksz9031_of_config(phydev);\n \tif (ret)\n"
  },
  {
    "path": "package/boot/uboot-sunxi/patches/091-sun6i-sync-PLL1-multdiv-with-Boot1.patch",
    "content": "From a58eb20fb80f478038243e9e0f30f6984725e265 Mon Sep 17 00:00:00 2001\nFrom: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>\nDate: Tue, 6 Jan 2015 15:47:18 +0100\nSubject: sun6i: Sync PLL1 multipliers/dividers with Boot1\n\nThis change syncs up the multipliers and dividers used to initialize\nPLL1 (i.e. the fast clock driving the ARM cores) with the values used\nin Allwinner's Boot1 on sun6i.\n\nMore specifically, the following settings are now used:\n * up to 768MHz:  mul=2, div=2 (was: mul=1, div=1)\n * up to 1152MHz: mul=3, div=2 (unchanged)\n * above 1152MHz: mul=4, div=2 (was: mul=2, div=1)\n\n--- a/arch/arm/mach-sunxi/clock_sun6i.c\n+++ b/arch/arm/mach-sunxi/clock_sun6i.c\n@@ -112,11 +112,12 @@ void clock_set_pll1(unsigned int clk)\n \tstruct sunxi_ccm_reg * const ccm =\n \t\t(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;\n \tconst int p = 0;\n-\tint k = 1;\n-\tint m = 1;\n+\tint k = 2;\n+\tint m = 2;\n \n \tif (clk > 1152000000) {\n-\t\tk = 2;\n+\t\tk = 4;\n+\t\tm = 2;\n \t} else if (clk > 768000000) {\n \t\tk = 4;\n \t\tm = 2;\n"
  },
  {
    "path": "package/boot/uboot-sunxi/patches/093-sun6i-fix-PLL-LDO-voltselect.patch",
    "content": "From b2b385df5095fff80b4655142f58a2a6801e6c80 Mon Sep 17 00:00:00 2001\nFrom: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>\nDate: Tue, 6 Jan 2015 21:26:44 +0100\nSubject: sun6i: Fix and document PLL LDO voltage selection\n\nThe PRCM_PLL_CTRL_LDO_OUT_L and PRCM_PLL_CTRL_LDO_OUT_H macros had\ntheir meaning reversed. This is fixed by this change-set. With this\nchanged, the PRCM_PLL_CTRL_LDO_OUT_L(1370) now becomes self-evident\nas setting the voltage to 1.37v (which it had done all along, even\nthough stating a different target voltage).\n\nAfter changing the PLL LDO setting, it will take a little while for\nthe voltage output to settle. A sdelay()-based loop waits the same\norder of magnitude as Boot1.\n\nFurthermore, a bit of documentation is added to clarify that the\nrequired setting for the PLL LDO is 1.37v as per the A31 manual.\n\n--- a/arch/arm/mach-sunxi/clock_sun6i.c\n+++ b/arch/arm/mach-sunxi/clock_sun6i.c\n@@ -25,13 +25,26 @@ void clock_init_safe(void)\n \tstruct sunxi_prcm_reg * const prcm =\n \t\t(struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;\n \n-\t/* Set PLL ldo voltage without this PLL6 does not work properly */\n+\t/* Set PLL ldo voltage without this PLL6 does not work properly.\n+\t *\n+\t * As the A31 manual states, that \"before enable PLL, PLLVDD\n+\t * LDO should be set to 1.37v\", we need to configure this to 2.5v\n+\t * in the \"PLL Input Power Select\" (0 << 15) and (7 << 16).\n+\t */\n \tclrsetbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK,\n \t\t\tPRCM_PLL_CTRL_LDO_KEY);\n \tclrsetbits_le32(&prcm->pll_ctrl1, ~PRCM_PLL_CTRL_LDO_KEY_MASK,\n \t\tPRCM_PLL_CTRL_LDO_DIGITAL_EN | PRCM_PLL_CTRL_LDO_ANALOG_EN |\n-\t\tPRCM_PLL_CTRL_EXT_OSC_EN | PRCM_PLL_CTRL_LDO_OUT_L(1140));\n+\t\tPRCM_PLL_CTRL_EXT_OSC_EN | PRCM_PLL_CTRL_LDO_OUT_L(1370));\n \tclrbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK);\n+\n+\t/* Give the PLL LDO voltage setting some time to take hold.\n+\t * Notes:\n+\t *   1) We need to use sdelay() as the timers aren't set up yet.\n+\t *   2) The 100k iterations come from Boot1, which spin's for 100k\n+\t *      iterations through a loop.\n+\t */\n+\tsdelay(100000);\n #endif\n \n #if defined(CONFIG_MACH_SUN8I_R40) || defined(CONFIG_MACH_SUN50I)\n--- a/arch/arm/include/asm/arch-sunxi/prcm.h\n+++ b/arch/arm/include/asm/arch-sunxi/prcm.h\n@@ -110,13 +110,13 @@\n #define PRCM_PLL_CTRL_LDO_OUT_MASK \\\n \t__PRCM_PLL_CTRL_LDO_OUT(0x7)\n /* When using the low voltage 20 mV steps, and high voltage 30 mV steps */\n-#define PRCM_PLL_CTRL_LDO_OUT_L(n) \\\n-\t__PRCM_PLL_CTRL_VDD_LDO_OUT((((n) - 1000) / 20) & 0x7)\n #define PRCM_PLL_CTRL_LDO_OUT_H(n) \\\n+\t__PRCM_PLL_CTRL_VDD_LDO_OUT((((n) - 1000) / 20) & 0x7)\n+#define PRCM_PLL_CTRL_LDO_OUT_L(n) \\\n \t__PRCM_PLL_CTRL_VDD_LDO_OUT((((n) - 1160) / 30) & 0x7)\n-#define PRCM_PLL_CTRL_LDO_OUT_LV(n) \\\n-\t__PRCM_PLL_CTRL_VDD_LDO_OUT((((n) & 0x7) * 20) + 1000)\n #define PRCM_PLL_CTRL_LDO_OUT_HV(n) \\\n+\t__PRCM_PLL_CTRL_VDD_LDO_OUT((((n) & 0x7) * 20) + 1000)\n+#define PRCM_PLL_CTRL_LDO_OUT_LV(n) \\\n \t__PRCM_PLL_CTRL_VDD_LDO_OUT((((n) & 0x7) * 30) + 1160)\n #define PRCM_PLL_CTRL_LDO_KEY (0xa7 << 24)\n #define PRCM_PLL_CTRL_LDO_KEY_MASK (0xff << 24)\n"
  },
  {
    "path": "package/boot/uboot-sunxi/patches/100-sun6i-alternate-on-UART2.patch",
    "content": "From d7311b6e7cdd1fc0e92665188e650934718cb2b1 Mon Sep 17 00:00:00 2001\nFrom: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>\nDate: Tue, 16 Jun 2015 10:52:01 +0200\nSubject: sun6i: define alternate-function for UART2 on GPG\n\n\n--- a/arch/arm/include/asm/arch-sunxi/gpio.h\n+++ b/arch/arm/include/asm/arch-sunxi/gpio.h\n@@ -190,6 +190,7 @@ enum sunxi_gpio_number {\n #define SUN6I_GPG_SDC1\t\t2\n #define SUN8I_GPG_SDC1\t\t2\n #define SUN6I_GPG_TWI3\t\t2\n+#define SUN6I_GPG_UART2         2\n #define SUN5I_GPG_UART1\t\t4\n \n #define SUN6I_GPH_PWM\t\t2\n"
  },
  {
    "path": "package/boot/uboot-sunxi/patches/101-sun6i-support-console-on-UART2.patch",
    "content": "From c058dfb69136d62f88ae8b121104bdb7ce2df03f Mon Sep 17 00:00:00 2001\nFrom: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>\nDate: Tue, 16 Jun 2015 10:53:11 +0200\nSubject: ARM: sun6i: Support console on UART2 (GPG6/GPG7)\n\n\n--- a/arch/arm/mach-sunxi/board.c\n+++ b/arch/arm/mach-sunxi/board.c\n@@ -129,6 +129,10 @@ static int gpio_init(void)\n \tsunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG_UART1);\n \tsunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG_UART1);\n \tsunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP);\n+#elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN6I)\n+\tsunxi_gpio_set_cfgpin(SUNXI_GPG(6), SUN6I_GPG_UART2);\n+\tsunxi_gpio_set_cfgpin(SUNXI_GPG(7), SUN6I_GPG_UART2);\n+\tsunxi_gpio_set_pull(SUNXI_GPG(7), SUNXI_GPIO_PULL_UP);\n #elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I)\n \tsunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_GPB_UART2);\n \tsunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_GPB_UART2);\n--- a/include/configs/sunxi-common.h\n+++ b/include/configs/sunxi-common.h\n@@ -244,6 +244,8 @@ extern int soft_i2c_gpio_scl;\n #endif\n #elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I)\n #define OF_STDOUT_PATH\t\t\"/soc@01c00000/serial@01c28400:115200\"\n+#elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN6I)\n+#define OF_STDOUT_PATH          \"/soc@01c00000/serial@01c28800:115200\"\n #elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I)\n #define OF_STDOUT_PATH\t\t\"/soc@01c00000/serial@01c28800:115200\"\n #elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I)\n"
  },
  {
    "path": "package/boot/uboot-sunxi/patches/102-sunxi-make_CONS_INDEX-configurable.patch",
    "content": "From 78d5fab8e345b1273ec8c22d06f1a1d27670b518 Mon Sep 17 00:00:00 2001\nFrom: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>\nDate: Tue, 16 Jun 2015 10:59:38 +0200\nSubject: ARM: sunxi: Make CONS_INDEX configurable\n\n\n--- a/arch/arm/mach-sunxi/Kconfig\n+++ b/arch/arm/mach-sunxi/Kconfig\n@@ -559,6 +559,14 @@ config SYS_BOARD\n config SYS_SOC\n \tdefault \"sunxi\"\n \n+config CONS_INDEX\n+        int \"UART used for console\"\n+        range 1 5\n+        default 1\n+        ---help---\n+        Defines the UART port used for serial output. It starts at 1 so UART0 is 1,\n+        UART1 is 2 and so on.\n+\n config UART0_PORT_F\n \tbool \"UART0 on MicroSD breakout board\"\n \tdefault n\n"
  },
  {
    "path": "package/boot/uboot-sunxi/patches/200-mkimage-check-environment-for-dtc-binary-location.patch",
    "content": "From 637800493945ffed2f454756300437a4ec86e3b1 Mon Sep 17 00:00:00 2001\nFrom: Hauke Mehrtens <hauke@hauke-m.de>\nDate: Wed, 19 Jul 2017 22:23:15 +0200\nSubject: mkimage: check environment for dtc binary location\n\nCurrently mkimage assumes the dtc binary is in the path and fails\notherwise. This patch makes it check the DTC environment variable first\nfor the dtc binary and then fall back to the default path. This makes\nit possible to call the u-boot build with make DTC=... and build a fit\nimage with the dtc binary not being the the default path.\n\nSigned-off-by: Hauke Mehrtens <hauke@hauke-m.de>\nCc: Simon Glass <sjg@chromium.org>\n---\n tools/fit_image.c | 7 ++++++-\n 1 file changed, 6 insertions(+), 1 deletion(-)\n\n--- a/tools/fit_image.c\n+++ b/tools/fit_image.c\n@@ -726,9 +726,14 @@ static int fit_handle_file(struct image_\n \t\t}\n \t\t*cmd = '\\0';\n \t} else if (params->datafile) {\n+\t\tconst char* dtc = getenv(\"DTC\");\n+\n+\t\tif (!dtc)\n+\t\t\tdtc = MKIMAGE_DTC;\n+\n \t\t/* dtc -I dts -O dtb -p 500 -o tmpfile datafile */\n \t\tsnprintf(cmd, sizeof(cmd), \"%s %s -o \\\"%s\\\" \\\"%s\\\"\",\n-\t\t\t MKIMAGE_DTC, params->dtc, tmpfile, params->datafile);\n+\t\t\t dtc, params->dtc, tmpfile, params->datafile);\n \t\tdebug(\"Trying to execute \\\"%s\\\"\\n\", cmd);\n \t} else {\n \t\tsnprintf(cmd, sizeof(cmd), \"cp \\\"%s\\\" \\\"%s\\\"\",\n"
  },
  {
    "path": "package/boot/uboot-sunxi/patches/210-sunxi-deactivate-binman.patch",
    "content": "From def280c4792262a368c8861312dc6b376181021f Mon Sep 17 00:00:00 2001\nFrom: Hauke Mehrtens <hauke@hauke-m.de>\nDate: Mon, 1 Jan 2018 23:10:56 +0100\nSubject: sunxi: deactivate binman\n\nUse the old way to generate the images instead of binman.\nbinman needs python with swig to avoid this host tool dependency use the\nold way of generating images.\n---\n Makefile | 7 ++++---\n 1 file changed, 4 insertions(+), 3 deletions(-)\n\n--- a/Makefile\n+++ b/Makefile\n@@ -1555,8 +1555,10 @@ endif\n \n ifneq ($(CONFIG_ARCH_SUNXI),)\n ifeq ($(CONFIG_ARM64),)\n-u-boot-sunxi-with-spl.bin: spl/sunxi-spl.bin u-boot.img u-boot.dtb FORCE\n-\t$(call if_changed,binman)\n+OBJCOPYFLAGS_u-boot-sunxi-with-spl.bin = -I binary -O binary \\\n+\t\t\t\t--pad-to=$(CONFIG_SPL_PAD_TO) --gap-fill=0xff\n+u-boot-sunxi-with-spl.bin: spl/sunxi-spl.bin u-boot.img FORCE\n+\t$(call if_changed,pad_cat)\n else\n u-boot-sunxi-with-spl.bin: spl/sunxi-spl.bin u-boot.itb FORCE\n \t$(call if_changed,cat)\n--- a/arch/arm/Kconfig\n+++ b/arch/arm/Kconfig\n@@ -962,7 +962,6 @@ config ARCH_SOCFPGA\n \n config ARCH_SUNXI\n \tbool \"Support sunxi (Allwinner) SoCs\"\n-\tselect BINMAN\n \tselect CMD_GPIO\n \tselect CMD_MMC if MMC\n \tselect CMD_USB if DISTRO_DEFAULTS\n"
  },
  {
    "path": "package/boot/uboot-sunxi/patches/230-disable-axp209-on-a13-olinuxino.diff",
    "content": "--- a/configs/A13-OLinuXino_defconfig\n+++ b/configs/A13-OLinuXino_defconfig\n@@ -7,7 +7,6 @@ CONFIG_DRAM_EMR1=0\n CONFIG_MMC0_CD_PIN=\"PG0\"\n CONFIG_USB0_VBUS_DET=\"PG1\"\n CONFIG_USB1_VBUS_PIN=\"PG11\"\n-CONFIG_AXP_GPIO=y\n # CONFIG_VIDEO_HDMI is not set\n CONFIG_VIDEO_VGA_VIA_LCD=y\n CONFIG_VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH=y\n@@ -21,7 +20,7 @@ CONFIG_CMD_USB_MASS_STORAGE=y\n CONFIG_DEFAULT_DEVICE_TREE=\"sun5i-a13-olinuxino\"\n CONFIG_DFU_RAM=y\n CONFIG_FASTBOOT_CMD_OEM_FORMAT=y\n-CONFIG_AXP_ALDO3_VOLT=3300\n+CONFIG_SUNXI_NO_PMIC=y\n CONFIG_CONS_INDEX=2\n CONFIG_USB_EHCI_HCD=y\n CONFIG_USB_OHCI_HCD=y\n"
  },
  {
    "path": "package/boot/uboot-sunxi/patches/250-sun8i-h3-zeropi-add-device-tree.patch",
    "content": "--- a/arch/arm/dts/Makefile\n+++ b/arch/arm/dts/Makefile\n@@ -539,7 +539,8 @@ dtb-$(CONFIG_MACH_SUN8I_H3) += \\\n \tsun8i-h3-orangepi-plus.dtb \\\n \tsun8i-h3-orangepi-plus2e.dtb \\\n \tsun8i-h3-orangepi-zero-plus2.dtb \\\n-\tsun8i-h3-rervision-dvk.dtb\n+\tsun8i-h3-rervision-dvk.dtb \\\n+\tsun8i-h3-zeropi.dtb\n dtb-$(CONFIG_MACH_SUN8I_R40) += \\\n \tsun8i-r40-bananapi-m2-ultra.dtb \\\n \tsun8i-v40-bananapi-m2-berry.dtb\n--- /dev/null\n+++ b/arch/arm/dts/sun8i-h3-zeropi.dts\n@@ -0,0 +1,66 @@\n+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n+\n+#include \"sun8i-h3-nanopi.dtsi\"\n+\n+/ {\n+\tmodel = \"FriendlyElec ZeroPi\";\n+\tcompatible = \"friendlyarm,zeropi\", \"allwinner,sun8i-h3\";\n+\n+\taliases {\n+\t\tethernet0 = &emac;\n+\t};\n+\n+\treg_gmac_3v3: gmac-3v3 {\n+\t\tcompatible = \"regulator-fixed\";\n+\t\tpinctrl-names = \"default\";\n+\t\tpinctrl-0 = <&gmac_power_pin_nanopi>;\n+\t\tregulator-name = \"gmac-3v3\";\n+\t\tregulator-min-microvolt = <3300000>;\n+\t\tregulator-max-microvolt = <3300000>;\n+\t\tstartup-delay-us = <100000>;\n+\t\tenable-active-high;\n+\t\tgpio = <&pio 3 6 GPIO_ACTIVE_HIGH>;\n+\t};\n+};\n+\n+&ehci0 {\n+\tstatus = \"okay\";\n+};\n+\n+&ohci0 {\n+\tstatus = \"okay\";\n+};\n+\n+&pio {\n+\tgmac_power_pin_nanopi: gmac_power_pin@0 {\n+\t\tpins = \"PD6\";\n+\t\tfunction = \"gpio_out\";\n+\t};\n+};\n+\n+&external_mdio {\n+\text_rgmii_phy: ethernet-phy@1 {\n+\t\tcompatible = \"ethernet-phy-ieee802.3-c22\";\n+\t\treg = <7>;\n+\t};\n+};\n+\n+&emac {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&emac_rgmii_pins>;\n+\tphy-supply = <&reg_gmac_3v3>;\n+\tphy-handle = <&ext_rgmii_phy>;\n+\tphy-mode = \"rgmii\";\n+\n+\tallwinner,leds-active-low;\n+\tstatus = \"okay\";\n+};\n+\n+&usb_otg {\n+\tstatus = \"okay\";\n+\tdr_mode = \"peripheral\";\n+};\n+\n+&usbphy {\n+\tusb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */\n+};\n"
  },
  {
    "path": "package/boot/uboot-sunxi/patches/251-sun8i-h3-zeropi-add-defconfig.patch",
    "content": "--- /dev/null\n+++ b/configs/zeropi_defconfig\n@@ -0,0 +1,21 @@\n+CONFIG_ARM=y\n+CONFIG_ARCH_SUNXI=y\n+CONFIG_MACH_SUN8I_H3=y\n+CONFIG_DRAM_CLK=408\n+CONFIG_DRAM_ZQ=3881979\n+CONFIG_DRAM_ODT_EN=y\n+CONFIG_MACPWR=\"PD6\"\n+# CONFIG_VIDEO_DE2 is not set\n+CONFIG_NR_DRAM_BANKS=1\n+CONFIG_DEFAULT_DEVICE_TREE=\"sun8i-h3-zeropi\"\n+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set\n+CONFIG_CONSOLE_MUX=y\n+CONFIG_SPL=y\n+CONFIG_SYS_CLK_FREQ=480000000\n+# CONFIG_CMD_IMLS is not set\n+# CONFIG_CMD_FLASH is not set\n+# CONFIG_CMD_FPGA is not set\n+CONFIG_SUN8I_EMAC=y\n+CONFIG_USB_EHCI_HCD=y\n+CONFIG_USB_EHCI_HCD=y\n+CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y\n"
  },
  {
    "path": "package/boot/uboot-sunxi/patches/252-sunxi-h3-add-support-for-nanopi-r1.patch",
    "content": "From 0e8043aff1aae95d1f7b7422b91b57d9569860d3 Mon Sep 17 00:00:00 2001\nFrom: Jayantajit Gogoi <jayanta.gogoi525@gmail.com>\nDate: Mon, 12 Oct 2020 18:39:53 +0000\nSubject: [PATCH] sunxi: add support for FriendlyARM NanoPi R1\n\nSigned-off-by: Jayantajit Gogoi <jayanta.gogoi525@gmail.com>\n---\n arch/arm/dts/Makefile               |   1 +\n arch/arm/dts/sun8i-h3-nanopi-r1.dts | 146 ++++++++++++++++++++++++++++\n configs/nanopi_r1_defconfig         |  22 +++++\n 3 files changed, 169 insertions(+)\n create mode 100644 arch/arm/dts/sun8i-h3-nanopi-r1.dts\n create mode 100644 configs/nanopi_r1_defconfig\n\n--- a/arch/arm/dts/Makefile\n+++ b/arch/arm/dts/Makefile\n@@ -531,6 +531,7 @@ dtb-$(CONFIG_MACH_SUN8I_H3) += \\\n \tsun8i-h3-nanopi-m1-plus.dtb \\\n \tsun8i-h3-nanopi-neo.dtb \\\n \tsun8i-h3-nanopi-neo-air.dtb \\\n+\tsun8i-h3-nanopi-r1.dtb \\\n \tsun8i-h3-orangepi-2.dtb \\\n \tsun8i-h3-orangepi-lite.dtb \\\n \tsun8i-h3-orangepi-one.dtb \\\n--- /dev/null\n+++ b/arch/arm/dts/sun8i-h3-nanopi-r1.dts\n@@ -0,0 +1,146 @@\n+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)\n+/*\n+ * Copyright (C) 2019 Igor Pecovnik <igor@armbian.com>\n+ * Copyright (C) 2020 Jayantajit Gogoi <jayanta.gogoi525@gmail.com>\n+ */\n+\n+/* NanoPi R1 is based on the NanoPi-H3 design from FriendlyARM */\n+#include \"sun8i-h3-nanopi.dtsi\"\n+\n+/ {\n+\tmodel = \"FriendlyARM NanoPi R1\";\n+\tcompatible = \"friendlyarm,nanopi-r1\", \"allwinner,sun8i-h3\";\n+\n+\treg_gmac_3v3: gmac-3v3 {\n+\t\tcompatible = \"regulator-fixed\";\n+\t\tregulator-name = \"gmac-3v3\";\n+\t\tregulator-min-microvolt = <3300000>;\n+\t\tregulator-max-microvolt = <3300000>;\n+\t\tstartup-delay-us = <100000>;\n+\t\tenable-active-high;\n+\t\tgpio = <&pio 3 6 GPIO_ACTIVE_HIGH>;\n+\t};\n+\n+\tvdd_cpux: gpio-regulator {\n+\t\tcompatible = \"regulator-gpio\";\n+\t\tpinctrl-names = \"default\";\n+\t\tregulator-name = \"vdd-cpux\";\n+\t\tregulator-type = \"voltage\";\n+\t\tregulator-boot-on;\n+\t\tregulator-always-on;\n+\t\tregulator-min-microvolt = <1100000>;\n+\t\tregulator-max-microvolt = <1300000>;\n+\t\tregulator-ramp-delay = <50>;\n+\t\tgpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>;\n+\t\tgpios-states = <0x1>;\n+\t\tstates = <1100000 0x0\n+\t\t\t  1300000 0x1>;\n+\t};\n+\n+\twifi_pwrseq: wifi_pwrseq {\n+\t\tcompatible = \"mmc-pwrseq-simple\";\n+\t\tpinctrl-names = \"default\";\n+\t\treset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>;\n+\t};\n+\n+\tleds {\n+\t\t/delete-node/ pwr;\n+\t\tstatus {\n+\t\t\tlabel = \"nanopi:red:status\";\n+\t\t\tgpios = <&pio 0 10 GPIO_ACTIVE_HIGH>;\n+\t\t\tlinux,default-trigger = \"heartbeat\";\n+\t\t};\n+\n+\t\twan {\n+\t\t\tlabel = \"nanopi:green:wan\";\n+\t\t\tgpios = <&pio 6 11 GPIO_ACTIVE_HIGH>;\n+\t\t};\n+\n+\t\tlan {\n+\t\t\tlabel = \"nanopi:green:lan\";\n+\t\t\tgpios = <&pio 0 9 GPIO_ACTIVE_HIGH>;\n+\t\t};\n+\t};\n+\n+\tr_gpio_keys {\n+\t\tpinctrl-names = \"default\";\n+\t\tpinctrl-0 = <&sw_r_npi>;\n+\n+\t\t/delete-node/ k1;\n+\t\treset {\n+\t\t\tlabel = \"reset\";\n+\t\t\tlinux,code = <KEY_RESTART>;\n+\t\t\tgpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\t};\n+};\n+\n+&cpu0 {\n+\tcpu-supply = <&vdd_cpux>;\n+};\n+\n+&ehci1 {\n+\tstatus = \"okay\";\n+};\n+\n+&ehci2 {\n+\tstatus = \"okay\";\n+};\n+\n+&emac {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&emac_rgmii_pins>;\n+\tphy-supply = <&reg_gmac_3v3>;\n+\tphy-handle = <&ext_rgmii_phy>;\n+\tphy-mode = \"rgmii\";\n+\tstatus = \"okay\";\n+};\n+\n+&external_mdio {\n+\text_rgmii_phy: ethernet-phy@1 {\n+\t\tcompatible = \"ethernet-phy-ieee802.3-c22\";\n+\t\treg = <7>;\n+\t};\n+};\n+\n+&mmc1 {\n+\tvmmc-supply = <&reg_vcc3v3>;\n+\tvqmmc-supply = <&reg_vcc3v3>;\n+\tmmc-pwrseq = <&wifi_pwrseq>;\n+\tbus-width = <4>;\n+\tnon-removable;\n+\tstatus = \"okay\";\n+\n+\tsdio_wifi: sdio_wifi@1 {\n+\t\treg = <1>;\n+\t\tcompatible = \"brcm,bcm4329-fmac\";\n+\t\tinterrupt-parent = <&pio>;\n+\t\tinterrupts = <6 10 IRQ_TYPE_LEVEL_LOW>;\n+\t\tinterrupt-names = \"host-wake\";\n+\t};\n+};\n+\n+&mmc2 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&mmc2_8bit_pins>;\n+\tvmmc-supply = <&reg_vcc3v3>;\n+\tvqmmc-supply = <&reg_vcc3v3>;\n+\tbus-width = <8>;\n+\tnon-removable;\n+\tstatus = \"okay\";\n+};\n+\n+&ohci1 {\n+\tstatus = \"okay\";\n+};\n+\n+&ohci2 {\n+\tstatus = \"okay\";\n+};\n+\n+&r_pio {\n+\tsw_r_npi: key_pins {\n+\t\tpins = \"PL3\";\n+\t\tfunction = \"gpio_in\";\n+\t};\n+};\n--- /dev/null\n+++ b/configs/nanopi_r1_defconfig\n@@ -0,0 +1,22 @@\n+CONFIG_ARM=y\n+CONFIG_ARCH_SUNXI=y\n+CONFIG_SPL=y\n+CONFIG_MACH_SUN8I_H3=y\n+CONFIG_DRAM_CLK=408\n+CONFIG_DRAM_ZQ=3881979\n+CONFIG_DRAM_ODT_EN=y\n+CONFIG_MACPWR=\"PD6\"\n+# CONFIG_VIDEO_DE2 is not set\n+CONFIG_NR_DRAM_BANKS=1\n+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set\n+CONFIG_CONSOLE_MUX=y\n+CONFIG_SYS_CLK_FREQ=480000000\n+# CONFIG_CMD_FLASH is not set\n+# CONFIG_SPL_DOS_PARTITION is not set\n+# CONFIG_SPL_EFI_PARTITION is not set\n+CONFIG_DEFAULT_DEVICE_TREE=\"sun8i-h3-nanopi-r1\"\n+CONFIG_SUN8I_EMAC=y\n+CONFIG_USB_EHCI_HCD=y\n+CONFIG_USB_OHCI_HCD=y\n+CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y\n+CONFIG_MMC_SUNXI_SLOT_EXTRA=2\n"
  },
  {
    "path": "package/boot/uboot-sunxi/patches/253-sunxi-h5-add-support-for-nanopi-r1s-h5.patch",
    "content": "From e7510d24cab4741f72489b9d67c2d42b18fe5374 Mon Sep 17 00:00:00 2001\nFrom: Chukun Pan <amadeus@jmu.edu.cn>\nDate: Sun, 10 Oct 2021 21:36:57 +0800\nSubject: [PATCH] sunxi: Add support for FriendlyARM NanoPi R1S H5\n\nThis adds support for the NanoPi R1S H5 board.\n\nAllwinner H5 SoC\n512MB DDR3 RAM\n10/100/1000M Ethernet x 2\nRTL8189ETV WiFi 802.11b/g/n\nUSB 2.0 host port (A)\nMicroSD Slot\nReset button\nSerial Debug Port\nWAN - LAN - SYS LED\n\nSigned-off-by: Chukun Pan <amadeus@jmu.edu.cn>\n---\n arch/arm/dts/Makefile                    |   1 +\n arch/arm/dts/sun50i-h5-nanopi-r1s-h5.dts | 195 +++++++++++++++++++++++\n board/sunxi/MAINTAINERS                  |   5 +\n configs/nanopi_r1s_h5_defconfig          |  14 ++\n 4 files changed, 215 insertions(+)\n create mode 100644 arch/arm/dts/sun50i-h5-nanopi-r1s-h5.dts\n create mode 100644 configs/nanopi_r1s_h5_defconfig\n\ndiff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile\nindex b8a382d1539..ed3d360bb10 100644\n--- a/arch/arm/dts/Makefile\n+++ b/arch/arm/dts/Makefile\n@@ -638,6 +638,7 @@ dtb-$(CONFIG_MACH_SUN50I_H5) += \\\n \tsun50i-h5-libretech-all-h5-cc.dtb \\\n \tsun50i-h5-nanopi-neo2.dtb \\\n \tsun50i-h5-nanopi-neo-plus2.dtb \\\n+\tsun50i-h5-nanopi-r1s-h5.dtb \\\n \tsun50i-h5-orangepi-zero-plus.dtb \\\n \tsun50i-h5-orangepi-pc2.dtb \\\n \tsun50i-h5-orangepi-prime.dtb \\\ndiff --git a/arch/arm/dts/sun50i-h5-nanopi-r1s-h5.dts b/arch/arm/dts/sun50i-h5-nanopi-r1s-h5.dts\nnew file mode 100644\nindex 00000000000..55bcdf8d1a0\n--- /dev/null\n+++ b/arch/arm/dts/sun50i-h5-nanopi-r1s-h5.dts\n@@ -0,0 +1,190 @@\n+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)\n+/*\n+ * Copyright (C) 2021 Chukun Pan <amadeus@jmu.edu.cn>\n+ *\n+ * Based on sun50i-h5-nanopi-neo-plus2.dts, which is:\n+ *   Copyright (C) 2017 Antony Antony <antony@phenome.org>\n+ *   Copyright (C) 2016 ARM Ltd.\n+ */\n+\n+/dts-v1/;\n+#include \"sun50i-h5.dtsi\"\n+\n+#include <dt-bindings/gpio/gpio.h>\n+#include <dt-bindings/input/input.h>\n+\n+/ {\n+\tmodel = \"FriendlyARM NanoPi R1S H5\";\n+\tcompatible = \"friendlyarm,nanopi-r1s-h5\", \"allwinner,sun50i-h5\";\n+\n+\taliases {\n+\t\tethernet0 = &emac;\n+\t\tethernet1 = &rtl8189etv;\n+\t\tserial0 = &uart0;\n+\t};\n+\n+\tchosen {\n+\t\tstdout-path = \"serial0:115200n8\";\n+\t};\n+\n+\tleds {\n+\t\tcompatible = \"gpio-leds\";\n+\n+\t\tsys {\n+\t\t\tlabel = \"nanopi:red:sys\";\n+\t\t\tgpios = <&pio 0 10 GPIO_ACTIVE_HIGH>;\n+\t\t\tlinux,default-trigger = \"heartbeat\";\n+\t\t};\n+\n+\t\tlan {\n+\t\t\tlabel = \"nanopi:green:lan\";\n+\t\t\tgpios = <&pio 0 9 GPIO_ACTIVE_HIGH>;\n+\t\t};\n+\n+\t\twan {\n+\t\t\tlabel = \"nanopi:green:wan\";\n+\t\t\tgpios = <&pio 6 11 GPIO_ACTIVE_HIGH>;\n+\t\t};\n+\t};\n+\n+\tr-gpio-keys {\n+\t\tcompatible = \"gpio-keys\";\n+\n+\t\treset {\n+\t\t\tlabel = \"reset\";\n+\t\t\tlinux,code = <KEY_RESTART>;\n+\t\t\tgpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\t};\n+\n+\treg_gmac_3v3: gmac-3v3 {\n+\t\tcompatible = \"regulator-fixed\";\n+\t\tregulator-name = \"gmac-3v3\";\n+\t\tregulator-min-microvolt = <3300000>;\n+\t\tregulator-max-microvolt = <3300000>;\n+\t\tstartup-delay-us = <100000>;\n+\t\tenable-active-high;\n+\t\tgpio = <&pio 3 6 GPIO_ACTIVE_HIGH>;\n+\t};\n+\n+\treg_vcc3v3: vcc3v3 {\n+\t\tcompatible = \"regulator-fixed\";\n+\t\tregulator-name = \"vcc3v3\";\n+\t\tregulator-min-microvolt = <3300000>;\n+\t\tregulator-max-microvolt = <3300000>;\n+\t};\n+\n+\treg_usb0_vbus: usb0-vbus {\n+\t\tcompatible = \"regulator-fixed\";\n+\t\tregulator-name = \"usb0-vbus\";\n+\t\tregulator-min-microvolt = <5000000>;\n+\t\tregulator-max-microvolt = <5000000>;\n+\t\tenable-active-high;\n+\t\tgpio = <&r_pio 0 2 GPIO_ACTIVE_HIGH>; /* PL2 */\n+\t\tstatus = \"okay\";\n+\t};\n+\n+\tvdd_cpux: gpio-regulator {\n+\t\tcompatible = \"regulator-gpio\";\n+\t\tregulator-name = \"vdd-cpux\";\n+\t\tregulator-type = \"voltage\";\n+\t\tregulator-boot-on;\n+\t\tregulator-always-on;\n+\t\tregulator-min-microvolt = <1100000>;\n+\t\tregulator-max-microvolt = <1300000>;\n+\t\tregulator-ramp-delay = <50>; /* 4ms */\n+\t\tgpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>;\n+\t\tgpios-states = <0x1>;\n+\t\tstates = <1100000 0x0>, <1300000 0x1>;\n+\t};\n+\n+\twifi_pwrseq: wifi_pwrseq {\n+\t\tcompatible = \"mmc-pwrseq-simple\";\n+\t\treset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */\n+\t\tpost-power-on-delay-ms = <200>;\n+\t};\n+};\n+\n+&cpu0 {\n+\tcpu-supply = <&vdd_cpux>;\n+};\n+\n+&ehci1 {\n+\tstatus = \"okay\";\n+};\n+\n+&ehci2 {\n+\tstatus = \"okay\";\n+};\n+\n+&emac {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&emac_rgmii_pins>;\n+\tphy-supply = <&reg_gmac_3v3>;\n+\tphy-handle = <&ext_rgmii_phy>;\n+\tphy-mode = \"rgmii-id\";\n+\tstatus = \"okay\";\n+};\n+\n+&external_mdio {\n+\text_rgmii_phy: ethernet-phy@7 {\n+\t\tcompatible = \"ethernet-phy-ieee802.3-c22\";\n+\t\treg = <7>;\n+\t};\n+};\n+\n+&i2c0 {\n+\tstatus = \"okay\";\n+\n+\teeprom@51 {\n+\t\tcompatible = \"microchip,24c02\";\n+\t\treg = <0x51>;\n+\t\tpagesize = <16>;\n+\t};\n+};\n+\n+&mmc0 {\n+\tvmmc-supply = <&reg_vcc3v3>;\n+\tbus-width = <4>;\n+\tcd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */\n+\tstatus = \"okay\";\n+};\n+\n+&mmc1 {\n+\tvmmc-supply = <&reg_vcc3v3>;\n+\tvqmmc-supply = <&reg_vcc3v3>;\n+\tmmc-pwrseq = <&wifi_pwrseq>;\n+\tbus-width = <4>;\n+\tnon-removable;\n+\tstatus = \"okay\";\n+\n+\trtl8189etv: sdio_wifi@1 {\n+\t\treg = <1>;\n+\t};\n+};\n+\n+&ohci1 {\n+\tstatus = \"okay\";\n+};\n+\n+&ohci2 {\n+\tstatus = \"okay\";\n+};\n+\n+&uart0 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&uart0_pa_pins>;\n+\tstatus = \"okay\";\n+};\n+\n+&usb_otg {\n+\tdr_mode = \"peripheral\";\n+\tstatus = \"okay\";\n+};\n+\n+&usbphy {\n+\t/* USB Type-A port's VBUS is always on */\n+\tusb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */\n+\tusb0_vbus-supply = <&reg_usb0_vbus>;\n+\tstatus = \"okay\";\n+};\ndiff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS\nindex 2543c94de79..56a0ee3689b 100644\n--- a/board/sunxi/MAINTAINERS\n+++ b/board/sunxi/MAINTAINERS\n@@ -358,6 +358,11 @@ M:\tJelle van der Waa <jelle@vdwaa.nl>\n S:\tMaintained\n F:\tconfigs/nanopi_neo_air_defconfig\n \n+NANOPI-R1S-H5 BOARD\n+M:\tChukun Pan <amadeus@jmu.edu.cn>\n+S:\tMaintained\n+F:\tconfigs/nanopi_r1s_h5_defconfig\n+\n NANOPI-A64 BOARD\n M:\tJagan Teki <jagan@amarulasolutions.com>\n S:\tMaintained\ndiff --git a/configs/nanopi_r1s_h5_defconfig b/configs/nanopi_r1s_h5_defconfig\nnew file mode 100644\nindex 00000000000..27cf172d72a\n--- /dev/null\n+++ b/configs/nanopi_r1s_h5_defconfig\n@@ -0,0 +1,14 @@\n+CONFIG_ARM=y\n+CONFIG_ARCH_SUNXI=y\n+CONFIG_SPL=y\n+CONFIG_MACH_SUN50I_H5=y\n+CONFIG_DRAM_CLK=672\n+CONFIG_DRAM_ZQ=3881977\n+# CONFIG_DRAM_ODT_EN is not set\n+CONFIG_MACPWR=\"PD6\"\n+CONFIG_MMC_SUNXI_SLOT_EXTRA=2\n+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set\n+CONFIG_DEFAULT_DEVICE_TREE=\"sun50i-h5-nanopi-r1s-h5\"\n+CONFIG_SUN8I_EMAC=y\n+CONFIG_USB_EHCI_HCD=y\n+CONFIG_USB_OHCI_HCD=y\n"
  },
  {
    "path": "package/boot/uboot-sunxi/patches/260-add-missing-type-u64.patch",
    "content": "--- a/include/linux/types.h\n+++ b/include/linux/types.h\n@@ -1,6 +1,7 @@\n #ifndef _LINUX_TYPES_H\n #define _LINUX_TYPES_H\n \n+typedef unsigned long long __u64;\n #include <linux/posix_types.h>\n #include <asm/types.h>\n #include <stdbool.h>\n"
  },
  {
    "path": "package/boot/uboot-sunxi/uEnv-a64.txt",
    "content": "setenv mmc_rootpart 2\npart uuid mmc ${mmc_bootdev}:${mmc_rootpart} uuid\nsetenv loadkernel fatload mmc \\$mmc_bootdev \\$kernel_addr_r uImage\nsetenv loaddtb fatload mmc \\$mmc_bootdev \\$fdt_addr_r dtb\nsetenv bootargs console=ttyS0,115200 earlyprintk root=PARTUUID=${uuid} rootwait earlycon=uart,mmio32,0x01c28000\nsetenv uenvcmd run loadkernel \\&\\& run loaddtb \\&\\& booti \\$kernel_addr_r - \\$fdt_addr_r\nrun uenvcmd\n"
  },
  {
    "path": "package/boot/uboot-sunxi/uEnv-default.txt",
    "content": "setenv fdt_high ffffffff\nsetenv loadkernel fatload mmc 0 \\$kernel_addr_r uImage\nsetenv loaddtb fatload mmc 0 \\$fdt_addr_r dtb\nsetenv bootargs console=ttyS0,115200 earlyprintk root=/dev/mmcblk0p2 rootwait\nsetenv uenvcmd run loadkernel \\&\\& run loaddtb \\&\\& bootm \\$kernel_addr_r - \\$fdt_addr_r\nrun uenvcmd\n"
  },
  {
    "path": "package/boot/uboot-sunxi/uEnv-h6.txt",
    "content": "setenv mmc_rootpart 2\npart uuid mmc ${mmc_bootdev}:${mmc_rootpart} uuid\nsetenv loadkernel fatload mmc \\$mmc_bootdev \\$kernel_addr_r uImage\nsetenv loaddtb fatload mmc \\$mmc_bootdev \\$fdt_addr_r dtb\nsetenv bootargs console=ttyS0,115200 earlyprintk root=PARTUUID=${uuid} rootwait\nsetenv uenvcmd run loadkernel \\&\\& run loaddtb \\&\\& booti \\$kernel_addr_r - \\$fdt_addr_r\nrun uenvcmd\n"
  },
  {
    "path": "package/boot/uboot-sunxi/uEnv-pangolin.txt",
    "content": "setenv fdt_high ffffffff\nsetenv loadkernel fatload mmc 0 \\$kernel_addr_r uImage\nsetenv loaddtb fatload mmc 0 \\$fdt_addr_r dtb\nsetenv bootargs console=ttyS2,115200 earlyprintk root=/dev/mmcblk0p2 rootwait\nsetenv uenvcmd run loadkernel \\&\\& run loaddtb \\&\\& bootm \\$kernel_addr_r - \\$fdt_addr_r\nrun uenvcmd\n"
  },
  {
    "path": "package/boot/uboot-tegra/Makefile",
    "content": "#\n# Copyright (C) 2017-2019 Tomasz Maciej Nowak <tmn505@gmail.com>\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\ninclude $(TOPDIR)/rules.mk\n\nPKG_VERSION := 2020.04\nPKG_RELEASE:=$(AUTORELEASE)\n\nPKG_HASH := fe732aaf037d9cc3c0909bad8362af366ae964bbdac6913a34081ff4ad565372\n\nPKG_MAINTAINER := Tomasz Maciej Nowak <tmn505@gmail.com>\n\ninclude $(INCLUDE_DIR)/u-boot.mk\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine U-Boot/Default\n  BUILD_TARGET := tegra\n  HIDDEN := y\nendef\n\ndefine U-Boot/trimslice\n  NAME := CompuLab TrimSlice\n  BUILD_DEVICES := compulab_trimslice\n  UBOOT_IMAGE := trimslice-mmc.img trimslice-spi.img\n  SOC := tegra20\n  VENDOR := compulab\nendef\n\nUBOOT_TARGETS := trimslice\n\ndefine Build/bct-image\n\t$(CP) $(PKG_BUILD_DIR)/u-boot-dtb-tegra.bin $(PKG_BUILD_DIR)/u-boot.bin\n\t$(foreach bct,$(basename $(UBOOT_IMAGE)), \\\n\t\tcd $(PKG_BUILD_DIR); \\\n\t\tcbootimage -s $(SOC) -gbct \\\n\t\t\t$(STAGING_DIR_HOST)/share/cbootimage-configs/$(SOC)/$(VENDOR)/$(VARIANT)/$(bct).bct.cfg \\\n\t\t\t$(bct).bct; \\\n\t\tcbootimage -s $(SOC) \\\n\t\t\t$(STAGING_DIR_HOST)/share/cbootimage-configs/$(SOC)/$(VENDOR)/$(VARIANT)/$(bct).img.cfg \\\n\t\t\t$(PKG_BUILD_DIR)/$(bct).img; \\\n\t\trm -f $(bct).bct; \\\n\t)\nendef\n\ndefine Build/Configure\n\tsed '/select BINMAN/d' -i $(PKG_BUILD_DIR)/arch/arm/mach-tegra/Kconfig\n\t$(call Build/Configure/U-Boot)\nendef\n\ndefine Build/Compile\n\t$(call Build/Compile/U-Boot)\n\t$(call Build/bct-image)\nendef\n\ndefine Build/InstallDev\n\t$(INSTALL_DIR) $(STAGING_DIR_IMAGE)\n\t$(foreach img,$(UBOOT_IMAGE), \\\n\t\t$(CP) $(PKG_BUILD_DIR)/$(img) $(STAGING_DIR_IMAGE)/;)\nendef\n\n$(eval $(call BuildPackage/U-Boot))\n"
  },
  {
    "path": "package/boot/uboot-zynq/Makefile",
    "content": "#\n# Copyright (C) 2015 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_VERSION:=2019.07\n\nPKG_HASH:=bff4fa77e8da17521c030ca4c5b947a056c1b1be4d3e6ee8637020b8d50251d0\n\ninclude $(INCLUDE_DIR)/kernel.mk\ninclude $(INCLUDE_DIR)/u-boot.mk\ninclude $(INCLUDE_DIR)/package.mk\ninclude $(INCLUDE_DIR)/host-build.mk\n\ndefine U-Boot/Default\n  BUILD_TARGET:=zynq\n  UBOOT_IMAGE:=spl/boot.bin u-boot.img\n  UBOOT_CONFIG:=zynq_$(1)\n  UENV:=default\n  HIDDEN:=1\nendef\n\ndefine U-Boot/zc702\n  NAME:=Xilinx ZC702 Dev Board\n  BUILD_DEVICES:=xlnx_zynq-zc702\nendef\n\ndefine U-Boot/zed\n  NAME:=Avnet Digilent ZedBoard Dev Board\n  BUILD_DEVICES:=avnet_zynq-zed\nendef\n\ndefine U-Boot/zybo\n  NAME:=Digilent Zybo Dev Board\n  BUILD_DEVICES:=digilent_zynq-zybo\nendef\n\ndefine U-Boot/zybo_z7\n  NAME:=Digilent Zybo Z7 board\n  BUILD_DEVICES:=digilent_zynq-zybo-z7\nendef\n\nUBOOT_TARGETS := \\\n\tzc702 \\\n\tzed \\\n\tzybo \\\n\tzybo_z7\n\ndefine Build/InstallDev\n\t$(INSTALL_DIR) $(STAGING_DIR_IMAGE)\n\t$(CP) $(PKG_BUILD_DIR)/spl/boot.bin $(STAGING_DIR_IMAGE)/$(BUILD_DEVICES)-boot.bin\n\t$(CP) $(PKG_BUILD_DIR)/u-boot.img $(STAGING_DIR_IMAGE)/$(BUILD_DEVICES)-u-boot.img\n\t$(CP) ./files/uEnv-$(UENV).txt $(STAGING_DIR_IMAGE)/$(BUILD_DEVICES)-uEnv.txt\nendef\n\ndefine Package/u-boot/install/default\nendef\n\n$(eval $(call BuildPackage/U-Boot))\n"
  },
  {
    "path": "package/boot/uboot-zynq/files/uEnv-default.txt",
    "content": "bootargs=console=ttyPS0,115200n8 root=/dev/mmcblk0p2 rootwait earlyprintk\n"
  },
  {
    "path": "package/boot/uboot-zynq/patches/010-fix_dtc_compilation_on_host_gcc10.patch",
    "content": "From e33a814e772cdc36436c8c188d8c42d019fda639 Mon Sep 17 00:00:00 2001\nFrom: Dirk Mueller <dmueller@suse.com>\nDate: Tue, 14 Jan 2020 18:53:41 +0100\nSubject: [PATCH] scripts/dtc: Remove redundant YYLOC global declaration\n\ngcc 10 will default to -fno-common, which causes this error at link\ntime:\n\n  (.text+0x0): multiple definition of `yylloc'; dtc-lexer.lex.o (symbol from plugin):(.text+0x0): first defined here\n\nThis is because both dtc-lexer as well as dtc-parser define the same\nglobal symbol yyloc. Before with -fcommon those were merged into one\ndefintion. The proper solution would be to to mark this as \"extern\",\nhowever that leads to:\n\n  dtc-lexer.l:26:16: error: redundant redeclaration of 'yylloc' [-Werror=redundant-decls]\n   26 | extern YYLTYPE yylloc;\n      |                ^~~~~~\nIn file included from dtc-lexer.l:24:\ndtc-parser.tab.h:127:16: note: previous declaration of 'yylloc' was here\n  127 | extern YYLTYPE yylloc;\n      |                ^~~~~~\ncc1: all warnings being treated as errors\n\nwhich means the declaration is completely redundant and can just be\ndropped.\n\nSigned-off-by: Dirk Mueller <dmueller@suse.com>\nSigned-off-by: David Gibson <david@gibson.dropbear.id.au>\n[robh: cherry-pick from upstream]\nCc: stable@vger.kernel.org\nSigned-off-by: Rob Herring <robh@kernel.org>\n---\n scripts/dtc/dtc-lexer.l | 1 -\n 1 file changed, 1 deletion(-)\n\ndiff --git a/scripts/dtc/dtc-lexer.l b/scripts/dtc/dtc-lexer.l\nindex 5c6c3fd557d7f..b3b7270300de5 100644\n--- a/scripts/dtc/dtc-lexer.l\n+++ b/scripts/dtc/dtc-lexer.l\n@@ -38,7 +38,6 @@ LINECOMMENT\t\"//\".*\\n\n #include \"srcpos.h\"\n #include \"dtc-parser.tab.h\"\n \n-YYLTYPE yylloc;\n extern bool treesource_error;\n \n /* CAUTION: this will stop working if we ever use yyless() or yyunput() */\n"
  },
  {
    "path": "package/boot/uboot-zynq/patches/110-zybo-z7-read-mac-address-from-SPI-flash-memory.patch",
    "content": "From 67db0da72eb7ed87ebaaeb8a26891cb2cf916500 Mon Sep 17 00:00:00 2001\nFrom: Luis Araneda <luaraneda@gmail.com>\nDate: Sun, 21 Jul 2019 23:24:12 -0400\nSubject: [U-Boot] [PATCH] arm: zynq: read mac address from SPI flash memory\n\nImplement a method for reading the MAC address from an\nSPI flash memory.\nIn particular, this method is used by the Zybo Z7 board\nto read the MAC address from the OTP region in the SPI NOR\nmemory\n\nSigned-off-by: Luis Araneda <luaraneda@gmail.com>\n---\nAs of 2019-08-18, this patch has not been accepted by upstream U-Boot.\nKeep this patch until an alternative is accepted by upstream.\n---\n board/xilinx/common/board.c    | 28 ++++++++++++++++++++++++++++\n configs/zynq_zybo_z7_defconfig |  3 +++\n drivers/misc/Kconfig           | 17 +++++++++++++++++\n 3 files changed, 48 insertions(+)\n\n--- a/board/xilinx/common/board.c\n+++ b/board/xilinx/common/board.c\n@@ -6,7 +6,10 @@\n \n #include <common.h>\n #include <dm/uclass.h>\n+#include <dm/device.h>\n+#include <dm/device-internal.h>\n #include <i2c.h>\n+#include <spi_flash.h>\n \n int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)\n {\n@@ -34,5 +37,30 @@ int zynq_board_read_rom_ethaddr(unsigned\n \t\tdebug(\"%s: I2C EEPROM MAC %pM\\n\", __func__, ethaddr);\n #endif\n \n+#if defined(CONFIG_MAC_ADDR_IN_SPI_FLASH)\n+\tstruct spi_flash *flash;\n+\tstruct udevice *dev;\n+\n+\tret = spi_flash_probe_bus_cs(CONFIG_SF_DEFAULT_BUS,\n+\t\t\t\t     CONFIG_SF_DEFAULT_CS,\n+\t\t\t\t     0, 0, &dev);\n+\tif (ret) {\n+\t\tprintf(\"SPI(bus:%u cs:%u) probe failed\\n\",\n+\t\t       CONFIG_SF_DEFAULT_BUS,\n+\t\t       CONFIG_SF_DEFAULT_CS);\n+\t\treturn 0;\n+\t}\n+\n+\tflash = dev_get_uclass_priv(dev);\n+\tflash->read_opcode = CONFIG_MAC_ADDR_SPI_FLASH_READ_CMD;\n+\n+\tif (spi_flash_read_dm(dev,\n+\t\t\t      CONFIG_MAC_ADDR_SPI_FLASH_DATA_OFFSET,\n+\t\t\t      6, ethaddr))\n+\t\tprintf(\"SPI MAC address read failed\\n\");\n+\n+\tdevice_remove(dev, DM_REMOVE_NORMAL);\n+#endif\n+\n \treturn ret;\n }\n--- a/configs/zynq_zybo_z7_defconfig\n+++ b/configs/zynq_zybo_z7_defconfig\n@@ -42,6 +42,9 @@ CONFIG_DFU_RAM=y\n CONFIG_FPGA_XILINX=y\n CONFIG_FPGA_ZYNQPL=y\n CONFIG_DM_GPIO=y\n+CONFIG_MAC_ADDR_IN_SPI_FLASH=y\n+CONFIG_MAC_ADDR_SPI_FLASH_READ_CMD=0x4b\n+CONFIG_MAC_ADDR_SPI_FLASH_DATA_OFFSET=0x20\n CONFIG_MMC_SDHCI=y\n CONFIG_MMC_SDHCI_ZYNQ=y\n CONFIG_SPI_FLASH=y\n--- a/drivers/misc/Kconfig\n+++ b/drivers/misc/Kconfig\n@@ -366,6 +366,23 @@ config SYS_I2C_EEPROM_ADDR_OVERFLOW\n \n endif\n \n+config MAC_ADDR_IN_SPI_FLASH\n+\tbool \"MAC address in SPI flash\"\n+\thelp\n+\t  Read MAC address from an SPI flash memory\n+\n+if MAC_ADDR_IN_SPI_FLASH\n+\n+config MAC_ADDR_SPI_FLASH_READ_CMD\n+\thex \"Read command for the SPI flash memory\"\n+\tdefault 0\n+\n+config MAC_ADDR_SPI_FLASH_DATA_OFFSET\n+\thex \"Offset of MAC data in SPI flash memory\"\n+\tdefault 0\n+\n+endif\n+\n config GDSYS_RXAUI_CTRL\n \tbool \"Enable gdsys RXAUI control driver\"\n \tdepends on MISC\n"
  },
  {
    "path": "package/devel/binutils/Makefile",
    "content": "#\n# Copyright (C) 2006-2013 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=binutils\nPKG_VERSION:=2.37\nPKG_RELEASE:=2\n\nPKG_SOURCE_URL:=@GNU/binutils\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz\nPKG_VERSION:=$(PKG_VERSION)\nPKG_HASH:=820d9724f020a3e69cb337893a0b63c2db161dadcb0e06fc11dc29eb1e84a32c\n\nPKG_FIXUP:=patch-libtool\nPKG_LIBTOOL_PATHS:=. gas bfd opcodes gprof binutils ld libiberty gold intl\nPKG_REMOVE_FILES:=libtool.m4\nPKG_INSTALL:=1\n\nPKG_MAINTAINER:=Felix Fietkau <nbd@nbd.name>\nPKG_LICENSE:=GPL-3.0+\nPKG_CPE_ID:=cpe:/a:gnu:binutils\nPKG_BUILD_PARALLEL:=1\nPKG_USE_MIPS16:=0\n\ninclude $(INCLUDE_DIR)/nls.mk\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine Package/libbfd\n  SECTION:=libs\n  CATEGORY:=Libraries\n  TITLE:=libbfd\n  DEPENDS:=+zlib $(INTL_DEPENDS)\nendef\n\ndefine Package/libctf\n  SECTION:=libs\n  CATEGORY:=Libraries\n  TITLE:=libctf\n  DEPENDS:=+libbfd\nendef\n\ndefine Package/libopcodes\n  SECTION:=libs\n  CATEGORY:=Libraries\n  TITLE:=libopcodes\n  DEPENDS:=+libbfd\nendef\n\ndefine Package/binutils\n  SECTION:=devel\n  CATEGORY:=Development\n  TITLE:=binutils\n  DEPENDS:=+objdump +ar\n  ALTERNATIVES:=200:/usr/bin/strings:/usr/bin/binutils-strings\nendef\n\ndefine Package/objdump\n  SECTION:=devel\n  CATEGORY:=Development\n  TITLE:=objdump\n  DEPENDS:=+libopcodes +libctf\nendef\n\ndefine Package/ar\n  SECTION:=devel\n  CATEGORY:=Development\n  TITLE:=ar\n  DEPENDS:=+zlib +libbfd\nendef\n\ndefine Package/binutils/description\n  The Binutils package contains a linker, an assembler, and other tools for handling object files\nendef\n\nTARGET_CFLAGS += $(FPIC) -Wno-unused-value\n\nTARGET_LDFLAGS += $(if $(INTL_FULL),-lintl)\n\nCONFIGURE_ARGS += \\\n\t--host=$(REAL_GNU_TARGET_NAME) \\\n\t--target=$(REAL_GNU_TARGET_NAME) \\\n\t--enable-shared \\\n\t--enable-install-libiberty \\\n\t--enable-install-libbfd \\\n\t--enable-install-libctf\n\ndefine Build/Install\n\t$(call Build/Install/Default)\n\t$(MAKE) -C $(PKG_BUILD_DIR)/libiberty \\\n\t\ttarget_header_dir=libiberty \\\n\t\tDESTDIR=\"$(PKG_INSTALL_DIR)\" \\\n\t\tMULTIOSDIR=\"\" \\\n\t\tinstall\nendef\n\ndefine Build/InstallDev\n\t$(CP) $(PKG_INSTALL_DIR)/* $(1)/\nendef\n\ndefine Package/libbfd/install\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/libbfd*.so* $(1)/usr/lib/\nendef\n\ndefine Package/libctf/install\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/libctf*.so* $(1)/usr/lib/\nendef\n\ndefine Package/libopcodes/install\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/libopcodes*.so $(1)/usr/lib/\nendef\n\ndefine Package/objdump/install\n\t$(INSTALL_DIR) $(1)/usr/bin\n\t$(CP) $(PKG_INSTALL_DIR)/usr/bin/objdump $(1)/usr/bin/\nendef\n\ndefine Package/ar/install\n\t$(INSTALL_DIR) $(1)/usr/bin\n\t$(CP) $(PKG_INSTALL_DIR)/usr/bin/ar $(1)/usr/bin/\nendef\n\ndefine Package/binutils/install\n\t$(INSTALL_DIR) $(1)/usr $(1)/bin\n\t$(CP) $(PKG_INSTALL_DIR)/usr/bin/ $(1)/usr/\n\tmv $(1)/usr/bin/strings $(1)/usr/bin/binutils-strings\n\trm -f $(1)/usr/bin/objdump\n\trm -f $(1)/usr/bin/ar\nendef\n\n$(eval $(call BuildPackage,libbfd))\n$(eval $(call BuildPackage,libctf))\n$(eval $(call BuildPackage,libopcodes))\n$(eval $(call BuildPackage,binutils))\n$(eval $(call BuildPackage,objdump))\n$(eval $(call BuildPackage,ar))\n"
  },
  {
    "path": "package/devel/gdb/Makefile",
    "content": "#\n# Copyright (C) 2006-2016 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=gdb\nPKG_VERSION:=11.2\nPKG_RELEASE:=$(AUTORELEASE)\n\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz\nPKG_SOURCE_URL:=@GNU/gdb\nPKG_HASH:=1497c36a71881b8671a9a84a0ee40faab788ca30d7ba19d8463c3cc787152e32\n\nPKG_BUILD_PARALLEL:=1\nPKG_INSTALL:=1\nPKG_LICENSE:=GPL-3.0+\nPKG_CPE_ID:=cpe:/a:gnu:gdb\n\ninclude $(INCLUDE_DIR)/package.mk\ninclude $(INCLUDE_DIR)/nls.mk\n\ndefine Package/gdb/Default\n  SECTION:=devel\n  CATEGORY:=Development\n  DEPENDS:=+!USE_MUSL:libthread-db $(ICONV_DEPENDS) $(INTL_DEPENDS)\n  URL:=https://www.gnu.org/software/gdb/\nendef\n\ndefine Package/gdb\n$(call Package/gdb/Default)\n  TITLE:=GNU Debugger\n  DEPENDS+=+libreadline +libncurses +zlib +libgmp\nendef\n\ndefine Package/gdb/description\nGDB, the GNU Project debugger, allows you to see what is going on `inside'\nanother program while it executes -- or what another program was doing at the\nmoment it crashed.\nendef\n\ndefine Package/gdbserver\n$(call Package/gdb/Default)\n  TITLE:=Remote server for GNU Debugger\nendef\n\ndefine Package/gdbserver/description\nGDBSERVER is a program that allows you to run GDB on a different machine than the\none which is running the program being debugged.\nendef\n\n# XXX: add --disable-werror to prevent build failure with arm\nCONFIGURE_ARGS+= \\\n\t--with-system-readline \\\n\t--with-system-zlib \\\n\t--without-expat \\\n\t--without-lzma \\\n\t--disable-unit-tests \\\n\t--disable-ubsan \\\n\t--disable-sim \\\n\t--disable-werror \\\n\t--disable-source-highlight \\\n\t--without-mpc \\\n\t--without-mpfr \\\n\t--without-isl \\\n\t--with-libgmp-prefix=$(STAGING_DIR)/usr\n\nCONFIGURE_VARS+= \\\n\tac_cv_search_tgetent=\"$(TARGET_LDFLAGS) -lncurses -lreadline\"\n\nTARGET_LDFLAGS+= \\\n\t$(INTL_LDFLAGS) $(if $(INTL_FULL),-lintl) \\\n\t-static-libstdc++ \\\n\t-Wl,--gc-sections\n\ndefine Build/Install\n\t$(MAKE) -C $(PKG_BUILD_DIR) \\\n\t\tDESTDIR=\"$(PKG_INSTALL_DIR)\" \\\n\t\tCPPFLAGS=\"$(TARGET_CPPFLAGS)\" \\\n\t\tinstall-gdb install-gdbserver\nendef\n\ndefine Package/gdb/install\n\t$(INSTALL_DIR) $(1)/usr/bin\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/bin/gdb $(1)/usr/bin/\nendef\n\ndefine Package/gdbserver/install\n\t$(INSTALL_DIR) $(1)/usr/bin\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/bin/gdbserver $(1)/usr/bin/\nendef\n\n$(eval $(call BuildPackage,gdb))\n$(eval $(call BuildPackage,gdbserver))\n"
  },
  {
    "path": "package/devel/gdb/patches/001-gdb-pr14523-mips-signal-number.patch",
    "content": "See http://sourceware.org/bugzilla/show_bug.cgi?id=14523\n\n--- a/gdbsupport/signals.cc\n+++ b/gdbsupport/signals.cc\n@@ -348,6 +348,11 @@ gdb_signal_from_host (int hostsig)\n       else if (64 <= hostsig && hostsig <= 127)\n \treturn (enum gdb_signal)\n \t  (hostsig - 64 + (int) GDB_SIGNAL_REALTIME_64);\n+      else if (hostsig == 128)\n+\t/* Some platforms, such as Linux MIPS, have NSIG == 128, in which case\n+\t   signal 128 is the highest realtime signal. There is no constant for\n+\t   that though. */\n+\treturn GDB_SIGNAL_UNKNOWN;\n       else\n \terror (_(\"GDB bug: target.c (gdb_signal_from_host): \"\n \t       \"unrecognized real-time signal\"));\n"
  },
  {
    "path": "package/devel/gdb/patches/110-shared_libgcc.patch",
    "content": "--- a/configure.ac\n+++ b/configure.ac\n@@ -1300,13 +1300,13 @@ if test -z \"$LD\"; then\n   fi\n fi\n \n-# Check whether -static-libstdc++ -static-libgcc is supported.\n+# Check whether -static-libstdc++ is supported.\n have_static_libs=no\n if test \"$GCC\" = yes; then\n   saved_LDFLAGS=\"$LDFLAGS\"\n \n-  LDFLAGS=\"$LDFLAGS -static-libstdc++ -static-libgcc\"\n-  AC_MSG_CHECKING([whether g++ accepts -static-libstdc++ -static-libgcc])\n+  LDFLAGS=\"$LDFLAGS -static-libstdc++\"\n+  AC_MSG_CHECKING([whether g++ accepts -static-libstdc++])\n   AC_LANG_PUSH(C++)\n   AC_LINK_IFELSE([AC_LANG_SOURCE([\n #if (__GNUC__ < 4) || (__GNUC__ == 4 && __GNUC_MINOR__ < 5)\n@@ -1705,7 +1705,7 @@ AC_ARG_WITH(stage1-ldflags,\n  # trust that they are doing what they want.\n  if test \"$with_static_standard_libraries\" = yes -a \"$stage1_libs\" = \"\" \\\n      -a \"$have_static_libs\" = yes; then\n-   stage1_ldflags=\"-static-libstdc++ -static-libgcc\"\n+   stage1_ldflags=\"-static-libstdc++\"\n  fi])\n AC_SUBST(stage1_ldflags)\n \n@@ -1734,7 +1734,7 @@ AC_ARG_WITH(boot-ldflags,\n  # statically.  But if the user explicitly specified the libraries to\n  # use, trust that they are doing what they want.\n  if test \"$poststage1_libs\" = \"\"; then\n-   poststage1_ldflags=\"-static-libstdc++ -static-libgcc\"\n+   poststage1_ldflags=\"-static-libstdc++\"\n  fi])\n AC_SUBST(poststage1_ldflags)\n \n--- a/configure\n+++ b/configure\n@@ -5257,14 +5257,14 @@ if test -z \"$LD\"; then\n   fi\n fi\n \n-# Check whether -static-libstdc++ -static-libgcc is supported.\n+# Check whether -static-libstdc++ is supported.\n have_static_libs=no\n if test \"$GCC\" = yes; then\n   saved_LDFLAGS=\"$LDFLAGS\"\n \n-  LDFLAGS=\"$LDFLAGS -static-libstdc++ -static-libgcc\"\n-  { $as_echo \"$as_me:${as_lineno-$LINENO}: checking whether g++ accepts -static-libstdc++ -static-libgcc\" >&5\n-$as_echo_n \"checking whether g++ accepts -static-libstdc++ -static-libgcc... \" >&6; }\n+  LDFLAGS=\"$LDFLAGS -static-libstdc++\"\n+  { $as_echo \"$as_me:${as_lineno-$LINENO}: checking whether g++ accepts -static-libstdc++\" >&5\n+$as_echo_n \"checking whether g++ accepts -static-libstdc++... \" >&6; }\n   ac_ext=cpp\n ac_cpp='$CXXCPP $CPPFLAGS'\n ac_compile='$CXX -c $CXXFLAGS $CPPFLAGS conftest.$ac_ext >&5'\n@@ -6149,7 +6149,7 @@ else\n  # trust that they are doing what they want.\n  if test \"$with_static_standard_libraries\" = yes -a \"$stage1_libs\" = \"\" \\\n      -a \"$have_static_libs\" = yes; then\n-   stage1_ldflags=\"-static-libstdc++ -static-libgcc\"\n+   stage1_ldflags=\"-static-libstdc++\"\n  fi\n fi\n \n@@ -6185,7 +6185,7 @@ else\n  # statically.  But if the user explicitly specified the libraries to\n  # use, trust that they are doing what they want.\n  if test \"$poststage1_libs\" = \"\"; then\n-   poststage1_ldflags=\"-static-libstdc++ -static-libgcc\"\n+   poststage1_ldflags=\"-static-libstdc++\"\n  fi\n fi\n \n"
  },
  {
    "path": "package/devel/gdb/patches/120-sigprocmask-invalid-call.patch",
    "content": "From 56893a61aa4f0270fa8d1197b9848247f90fce0d Mon Sep 17 00:00:00 2001\nFrom: Yousong Zhou <yszhou4tech@gmail.com>\nDate: Fri, 24 Mar 2017 10:36:03 +0800\nSubject: [PATCH] Fix invalid sigprocmask call\n\nThe POSIX document says\n\n    The pthread_sigmask() and sigprocmask() functions shall fail if:\n\n    [EINVAL]\n    The value of the how argument is not equal to one of the defined values.\n\nand this is how musl-libc is currently doing.  Fix the call to be safe\nand correct\n\n [1] http://pubs.opengroup.org/onlinepubs/9699919799/functions/pthread_sigmask.html\n\ngdb/ChangeLog:\n2017-03-24  Yousong Zhou  <yszhou4tech@gmail.com>\n\n    * common/signals-state-save-restore.c (save_original_signals_state):\n    Fix invalid sigprocmask call.\n---\n gdb/ChangeLog                           | 5 +++++\n gdb/common/signals-state-save-restore.c | 2 +-\n 2 files changed, 6 insertions(+), 1 deletion(-)\n\n--- a/gdbsupport/signals-state-save-restore.cc\n+++ b/gdbsupport/signals-state-save-restore.cc\n@@ -38,7 +38,7 @@ save_original_signals_state (bool quiet)\n   int i;\n   int res;\n \n-  res = gdb_sigmask (0,  NULL, &original_signal_mask);\n+  res = gdb_sigmask (SIG_BLOCK,  NULL, &original_signal_mask);\n   if (res == -1)\n     perror_with_name ((\"sigprocmask\"));\n \n"
  },
  {
    "path": "package/devel/gdb/patches/130-gdb-ctrl-c.patch",
    "content": "From 63df98fa78c8a6e12b40ebdc5c155838d2bf8b5f Mon Sep 17 00:00:00 2001\nFrom: Khem Raj <raj.khem@gmail.com>\nDate: Thu, 29 Nov 2018 18:00:23 -0800\nSubject: [PATCH 11/11] gdbserver ctrl-c handling\n\nThis problem was created by the upstream commit 78708b7c8c\nAfter applying the commit, it will send SIGINT to the process\ngroup(-signal_pid).\nBut if we use gdbserver send SIGINT, and the attached process is not a\nprocess\ngroup leader, then the \"kill (-signal_pid, SIGINT)\" returns error and\nfails  to\ninterrupt the attached process.\n\nUpstream-Status: Submitted\n[https://sourceware.org/bugzilla/show_bug.cgi?id=18945]\n\nAuthor: Josh Gao\nSigned-off-by: Zhixiong Chi <zhixiong.chi@windriver.com>\nSigned-off-by: Khem Raj <raj.khem@gmail.com>\n---\n gdbserver/linux-low.cc | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/gdbserver/linux-low.cc\n+++ b/gdbserver/linux-low.cc\n@@ -5733,7 +5733,7 @@ linux_process_target::request_interrupt\n {\n   /* Send a SIGINT to the process group.  This acts just like the user\n      typed a ^C on the controlling terminal.  */\n-  ::kill (-signal_pid, SIGINT);\n+  ::kill (signal_pid, SIGINT);\n }\n \n bool\n"
  },
  {
    "path": "package/devel/gdb/patches/140-sgidefs.patch",
    "content": "From 677b5b56135141c0d259e370aacd0e11c810aa15 Mon Sep 17 00:00:00 2001\nFrom: Andre McCurdy <armccurdy@gmail.com>\nDate: Fri, 5 Feb 2016 14:00:00 -0800\nSubject: [PATCH] use <asm/sgidefs.h>\n\nBuild fix for MIPS with musl libc\n\nThe MIPS specific header <sgidefs.h> is provided by glibc and uclibc\nbut not by musl. Regardless of the libc, the kernel headers provide\n<asm/sgidefs.h> which provides the same definitions, so use that\ninstead.\n\nUpstream-Status: Pending\n\nSigned-off-by: Andre McCurdy <armccurdy@gmail.com>\n---\n gdb/mips-linux-nat.c | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/gdb/mips-linux-nat.c\n+++ b/gdb/mips-linux-nat.c\n@@ -31,7 +31,7 @@\n #include \"gdb_proc_service.h\"\n #include \"gregset.h\"\n \n-#include <sgidefs.h>\n+#include <asm/sgidefs.h>\n #include \"nat/gdb_ptrace.h\"\n #include <asm/ptrace.h>\n #include \"inf-ptrace.h\"\n"
  },
  {
    "path": "package/devel/gdb/patches/150-mips64.patch",
    "content": "From e92f8932ef488de2a56db4299131ce6a4eb170bd Mon Sep 17 00:00:00 2001\nFrom: Khem Raj <raj.khem@gmail.com>\nDate: Wed, 23 Mar 2016 06:30:09 +0000\nSubject: [PATCH] mips-linux-nat: Define _ABIO32 if not defined\n\nThis helps building gdb on mips64 on musl, since\nmusl does not provide sgidefs.h this define is\nonly defined when GCC is using o32 ABI, in that\ncase gcc emits it as built-in define and hence\nit works ok for mips32\n\nSigned-off-by: Khem Raj <raj.khem@gmail.com>\n---\nUpstream-Status: Pending\n\n gdb/mips-linux-nat.c | 5 +++++\n 1 file changed, 5 insertions(+)\n\n--- a/gdb/mips-linux-nat.c\n+++ b/gdb/mips-linux-nat.c\n@@ -42,6 +42,11 @@\n #define PTRACE_GET_THREAD_AREA 25\n #endif\n \n+/* musl does not define and relies on compiler built-in macros for it   */\n+#ifndef _ABIO32\n+#define _ABIO32 1\n+#endif\n+\n class mips_linux_nat_target final : public linux_nat_trad_target\n {\n public:\n"
  },
  {
    "path": "package/devel/perf/Makefile",
    "content": "#\n# Copyright (C) 2011-2013 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\ninclude $(INCLUDE_DIR)/kernel.mk\n\nPKG_NAME:=perf\nPKG_VERSION:=$(LINUX_VERSION)\nPKG_RELEASE:=4\n\nPKG_USE_MIPS16:=0\nPKG_BUILD_PARALLEL:=1\nPKG_MAINTAINER:=Felix Fietkau <nbd@nbd.name>\nPKG_FLAGS:=nonshared\n\n# Perf's makefile and headers are not relocatable and must be built from the\n# Linux sources directory\nPKG_BUILD_DIR:=$(LINUX_DIR)/tools/perf-$(TARGET_DIR_NAME)\n\ninclude $(INCLUDE_DIR)/package.mk\ninclude $(INCLUDE_DIR)/nls.mk\n\ndefine Package/perf\n  SECTION:=devel\n  CATEGORY:=Development\n  DEPENDS:= +libelf +libdw +PACKAGE_libunwind:libunwind +libpthread +librt +objdump @!IN_SDK @KERNEL_PERF_EVENTS \\\n\t    +PACKAGE_libbfd:libbfd +PACKAGE_libopcodes:libopcodes\n  TITLE:=Linux performance monitoring tool\n  VERSION:=$(LINUX_VERSION)-$(PKG_RELEASE)\n  URL:=http://www.kernel.org\nendef\n\ndefine Package/perf/description\n  perf is the Linux performance monitoring tool\nendef\n\nHOST_CFLAGS += -I$(LINUX_DIR)/tools/include\n\nTARGET_LDFLAGS += $(INTL_LDFLAGS)\n\nMAKE_FLAGS = \\\n\tARCH=\"$(LINUX_KARCH)\" \\\n\tNO_LIBPERL=1 \\\n\tNO_LIBPYTHON=1 \\\n\tNO_NEWT=1 \\\n\tNO_LZMA=1 \\\n\tNO_BACKTRACE=1 \\\n\tNO_LIBNUMA=1 \\\n\tNO_GTK2=1 \\\n\tNO_LIBAUDIT=1 \\\n\tNO_LIBCRYPTO=1 \\\n\tNO_LIBUNWIND=1 \\\n\tNO_LIBZSTD=1 \\\n\tNO_LIBCAP=1 \\\n\tCROSS_COMPILE=\"$(TARGET_CROSS)\" \\\n\tCC=\"$(TARGET_CC)\" \\\n\tLD=\"$(TARGET_CROSS)ld\" \\\n\tEXTRA_CFLAGS=\"$(TARGET_CFLAGS) $(TARGET_CPPFLAGS)\" \\\n\tLDFLAGS=\"$(TARGET_LDFLAGS)\" \\\n\tKBUILD_HOSTCFLAGS=\"$(HOST_CFLAGS)\" \\\n\t$(if $(findstring c,$(OPENWRT_VERBOSE)),V=1,V='') \\\n\tWERROR=0 \\\n\tO=$(PKG_BUILD_DIR) \\\n\tprefix=/usr\n\ndefine Build/Compile\n\t+$(MAKE_FLAGS) $(MAKE) $(PKG_JOBS) \\\n\t\t--no-print-directory \\\n\t\t-C $(LINUX_DIR)/tools/perf\nendef\n\ndefine Package/perf/install\n\t$(INSTALL_DIR) $(1)/usr/bin\n\t$(INSTALL_BIN) $(PKG_BUILD_DIR)/perf $(1)/usr/bin/\nendef\n\n$(eval $(call BuildPackage,perf))\n"
  },
  {
    "path": "package/devel/strace/Makefile",
    "content": "#\n# Copyright (C) 2006-2016 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\ninclude $(INCLUDE_DIR)/kernel.mk\n\nPKG_NAME:=strace\nPKG_VERSION:=5.16\nPKG_RELEASE:=1\n\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz\nPKG_SOURCE_URL:=https://strace.io/files/$(PKG_VERSION)\nPKG_HASH:=dc7db230ff3e57c249830ba94acab2b862da1fcaac55417e9b85041a833ca285\n\nPKG_MAINTAINER:=Felix Fietkau <nbd@nbd.name>\nPKG_LICENSE:=LGPL-2.1-or-later\nPKG_LICENSE_FILES:=COPYING\nPKG_CPE_ID:=cpe:/a:paul_kranenburg:strace\n\nPKG_FIXUP:=autoreconf\nPKG_INSTALL:=1\n\nPKG_CONFIG_DEPENDS := \\\n\tCONFIG_STRACE_LIBDW \\\n\tCONFIG_STRACE_LIBUNWIND\n\ninclude $(INCLUDE_DIR)/package.mk\n\nHOST_CFLAGS += -I$(LINUX_DIR)/user_headers/include\n\nCONFIGURE_VARS+= \\\n\tLDFLAGS_FOR_BUILD=\"$(HOST_LDFLAGS)\" \\\n\tCPPFLAGS_FOR_BUILD=\"$(HOST_CPPFLAGS)\" \\\n\tCFLAGS_FOR_BUILD=\"$(HOST_CFLAGS)\" \\\n\tCC_FOR_BUILD=\"$(HOST_CC)\"\n\ndefine Package/strace\n  SECTION:=utils\n  CATEGORY:=Utilities\n  TITLE:=System call tracer\n  URL:=https://strace.io/\n  DEPENDS:=+STRACE_LIBDW:libdw +STRACE_LIBUNWIND:libunwind\nendef\n\ndefine Package/strace/description\n  A useful diagnostic, instructional, and debugging tool. Allows you to track what\n  system calls a program makes while it is running.\nendef\n\ndefine Package/strace/config\nchoice\n\tprompt \"stack tracing support\"\n\tdefault STRACE_NONE\n\n\tconfig STRACE_NONE\n\t\tbool \"None\"\n\n\tconfig STRACE_LIBDW\n\t\tbool \"libdw\"\n\n\tconfig STRACE_LIBUNWIND\n\t\tbool \"libunwind (experimental)\"\nendchoice\nendef\n\nCONFIGURE_ARGS += \\\n\t--with-libdw=$(if $(CONFIG_STRACE_LIBDW),yes,no) \\\n\t--with-libunwind=$(if $(CONFIG_STRACE_LIBUNWIND),yes,no) \\\n\t--enable-mpers=no \\\n\t--without-libselinux\n\nMAKE_FLAGS := \\\n\tCCOPT=\"$(TARGET_CFLAGS)\"\n\ndefine Package/strace/install\n\t$(INSTALL_DIR) $(1)/usr/bin\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/bin/strace $(1)/usr/bin/\nendef\n\n$(eval $(call BuildPackage,strace))\n"
  },
  {
    "path": "package/devel/strace/patches/010-m4.patch",
    "content": "--- a/Makefile.am\n+++ b/Makefile.am\n@@ -21,7 +21,6 @@ man_MANS = doc/strace.1 doc/strace-log-m\n \n ACLOCAL_AMFLAGS = -I m4 -I src/xlat\n \n-@CODE_COVERAGE_RULES@\n CODE_COVERAGE_BRANCH_COVERAGE = 1\n CODE_COVERAGE_GENHTML_OPTIONS = $(CODE_COVERAGE_GENHTML_OPTIONS_DEFAULT) \\\n \t--title \"$(PACKAGE_NAME)-$(PACKAGE_VERSION)\" \\\n"
  },
  {
    "path": "package/devel/trace-cmd/Makefile",
    "content": "include $(TOPDIR)/rules.mk\n\nPKG_NAME:=trace-cmd\nPKG_VERSION:=v2.9.1\nPKG_RELEASE:=1\n\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz\nPKG_SOURCE_URL:=https://git.kernel.org/pub/scm/linux/kernel/git/rostedt/trace-cmd.git/snapshot/\nPKG_HASH:=9404fc3cf540ea795304608068c9db6cdb38b90584c7f3c43249785913d54b38\n\nPKG_LICENSE:=GPL-2.0-only\nPKG_LICENSE_FILES:=COPYING\n\nPKG_INSTALL:=1\nPKG_USE_MIPS16:=0\nPKG_BUILD_PARALLEL:=1\n\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine Package/trace-cmd\n  SECTION:=devel\n  CATEGORY:=Development\n  TITLE:=Linux trace command line utility\n  DEPENDS:=\nendef\n\ndefine Package/trace-cmd-extra\n  SECTION:=devel\n  CATEGORY:=Development\n  TITLE:=Extra plugins for trace-cmd\n  DEPENDS:=\nendef\n\nMAKE_FLAGS += \\\n\tNO_PYTHON=1 \\\n\tNO_AUDIT=1 \\\n\tprefix=/usr\n\nPLUGINS_DIR := $(PKG_INSTALL_DIR)/usr/lib/traceevent/plugins\nPLUGINS_MAIN := function hrtimer mac80211 sched_switch\n\nTARGET_CFLAGS += --std=gnu99 -D_GNU_SOURCE\n\ndefine Package/trace-cmd/install\n\t$(INSTALL_DIR) $(1)/usr/bin $(1)/usr/lib/traceevent/plugins\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/bin/trace-cmd $(1)/usr/bin/\n\t$(CP) \\\n\t\t$(patsubst %,$(PLUGINS_DIR)/plugin_%.so,$(PLUGINS_MAIN)) \\\n\t\t$(1)/usr/lib/traceevent/plugins\nendef\n\ndefine Package/trace-cmd-extra/install\n\t$(INSTALL_DIR) $(1)/usr/lib/traceevent/plugins\n\t$(CP) \\\n\t\t$$(patsubst %,$(PLUGINS_DIR)/plugin_%.so, \\\n\t\t\t$$(filter-out $(PLUGINS_MAIN), \\\n\t\t\t\t$$(patsubst $(PLUGINS_DIR)/plugin_%.so,%, \\\n\t\t\t\t\t$$(wildcard $(PLUGINS_DIR)/plugin_*.so)))) \\\n\t\t$(1)/usr/lib/traceevent/plugins\nendef\n\n$(eval $(call BuildPackage,trace-cmd))\n$(eval $(call BuildPackage,trace-cmd-extra))\n"
  },
  {
    "path": "package/devel/trace-cmd/patches/100-musl.patch",
    "content": "From 1a000636c1828eecdcec5360a51623ef4ffbff04 Mon Sep 17 00:00:00 2001\nFrom: Beniamin Sandu <beniaminsandu@gmail.com>\nDate: Mon, 30 Nov 2020 14:27:55 +0200\nSubject: trace-cmd: make it build against musl C library\n\n* add some missing headers and macros\n* set pthread affinity using pthread_setaffinity_np after creating the thread\ninstead of pthread_attr_setaffinity_np (which seems to not be implemented\nin musl)\n\nTested using https://musl.cc/x86_64-linux-musl-native.tgz\n\nLink: https://lore.kernel.org/linux-trace-devel/20201130122755.31000-1-beniaminsandu@gmail.com\n\nReviewed-by: Tzvetomir Stoyanov (VMware) <tz.stoyanov@gmail.com>\nSigned-off-by: Beniamin Sandu <beniaminsandu@gmail.com>\n[ Fixed a whitespace issue ]\nSigned-off-by: Steven Rostedt (VMware) <rostedt@goodmis.org>\n---\n include/trace-cmd/trace-cmd.h                     |  1 +\n lib/trace-cmd/include/trace-cmd-local.h           |  1 +\n lib/tracefs/tracefs-events.c                      |  1 +\n tracecmd/include/trace-local.h                    |  1 +\n tracecmd/trace-tsync.c                            | 16 +++++++++++-----\n 5 files changed, 20 insertions(+), 5 deletions(-)\n\n--- a/include/trace-cmd/trace-cmd.h\n+++ b/include/trace-cmd/trace-cmd.h\n@@ -6,6 +6,7 @@\n #ifndef _TRACE_CMD_H\n #define _TRACE_CMD_H\n \n+#include <pthread.h>\n #include \"traceevent/event-parse.h\"\n \n #define TRACECMD_MAGIC { 23, 8, 68 }\n--- a/lib/trace-cmd/include/trace-cmd-local.h\n+++ b/lib/trace-cmd/include/trace-cmd-local.h\n@@ -26,5 +26,6 @@ void warning(const char *fmt, ...);\n #endif\n #endif\n \n+#include <byteswap.h>\n \n #endif /* _TRACE_CMD_LOCAL_H */\n--- a/lib/tracefs/tracefs-events.c\n+++ b/lib/tracefs/tracefs-events.c\n@@ -13,6 +13,7 @@\n #include <errno.h>\n #include <sys/stat.h>\n #include <fcntl.h>\n+#include <limits.h>\n \n #include \"kbuffer.h\"\n #include \"tracefs.h\"\n--- a/tracecmd/include/trace-local.h\n+++ b/tracecmd/include/trace-local.h\n@@ -8,6 +8,7 @@\n \n #include <sys/types.h>\n #include <dirent.h>\t/* for DIR */\n+#include <limits.h>\n \n #include \"trace-cmd.h\"\n #include \"event-utils.h\"\n--- a/tracecmd/trace-tsync.c\n+++ b/tracecmd/trace-tsync.c\n@@ -104,13 +104,16 @@ int tracecmd_host_tsync(struct buffer_in\n \n \tpthread_attr_init(&attrib);\n \tpthread_attr_setdetachstate(&attrib, PTHREAD_CREATE_JOINABLE);\n-\tif (!get_first_cpu(&pin_mask, &mask_size))\n-\t\tpthread_attr_setaffinity_np(&attrib, mask_size, pin_mask);\n \n \tret = pthread_create(&instance->tsync_thread, &attrib,\n \t\t\t     tsync_host_thread, &instance->tsync);\n-\tif (!ret)\n+\n+\tif (!ret) {\n+\t\tif (!get_first_cpu(&pin_mask, &mask_size))\n+\t\t\tpthread_setaffinity_np(instance->tsync_thread, mask_size, pin_mask);\n \t\tinstance->tsync_thread_running = true;\n+\t}\n+\n \tif (pin_mask)\n \t\tCPU_FREE(pin_mask);\n \tpthread_attr_destroy(&attrib);\n@@ -243,11 +246,14 @@ unsigned int tracecmd_guest_tsync(char *\n \tpthread_attr_init(&attrib);\n \ttsync->sync_proto = proto;\n \tpthread_attr_setdetachstate(&attrib, PTHREAD_CREATE_JOINABLE);\n-\tif (!get_first_cpu(&pin_mask, &mask_size))\n-\t\tpthread_attr_setaffinity_np(&attrib, mask_size, pin_mask);\n \n \tret = pthread_create(thr_id, &attrib, tsync_agent_thread, tsync);\n \n+\tif (!ret) {\n+\t\tif (!get_first_cpu(&pin_mask, &mask_size))\n+\t\t\tpthread_setaffinity_np(*thr_id, mask_size, pin_mask);\n+\t}\n+\n \tif (pin_mask)\n \t\tCPU_FREE(pin_mask);\n \tpthread_attr_destroy(&attrib);\n"
  },
  {
    "path": "package/devel/trace-cmd/patches/110-mac80211_tracepoint.patch",
    "content": "--- a/lib/traceevent/plugins/plugin_mac80211.c\n+++ b/lib/traceevent/plugins/plugin_mac80211.c\n@@ -165,12 +165,15 @@ static int drv_config(struct trace_seq *\n \t\t{ 2, \"IDLE\" },\n \t\t{ 3, \"QOS\"},\n \t);\n-\ttep_print_num_field(s, \" chan:%d/\", event, \"center_freq\", record, 1);\n-\tprint_enum(s, event, \"channel_type\", data,\n-\t\t{ 0, \"noht\" },\n-\t\t{ 1, \"ht20\" },\n-\t\t{ 2, \"ht40-\" },\n-\t\t{ 3, \"ht40+\" });\n+\ttep_print_num_field(s, \" chan:%d@\", event, \"control_freq\", record, 1);\n+\tprint_enum(s, event, \"chan_width\", data,\n+\t\t{ 0, \"20_noht\" },\n+\t\t{ 1, \"20\" },\n+\t\t{ 2, \"40\" },\n+\t\t{ 3, \"80\" },\n+\t\t{ 4, \"80p80\" },\n+\t\t{ 5, \"160\" });\n+\n \ttrace_seq_putc(s, ' ');\n \tSF(\"power_level\");\n \n"
  },
  {
    "path": "package/devel/valgrind/Makefile",
    "content": "#\n# Copyright (C) 2006-2013 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=valgrind\nPKG_VERSION:=3.18.1\nPKG_RELEASE:=1\n\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.bz2\nPKG_SOURCE_URL:=http://sourceware.org/pub/valgrind/\nPKG_HASH:=00859aa13a772eddf7822225f4b46ee0d39afbe071d32778da4d99984081f7f5\n\nPKG_MAINTAINER:=Felix Fietkau <nbd@nbd.name>\nPKG_LICENSE:=GPL-2.0+\nPKG_CPE_ID:=cpe:/a:valgrind:valgrind\n\nPKG_FIXUP = autoreconf\nPKG_INSTALL := 1\nPKG_BUILD_PARALLEL := 1\nPKG_USE_MIPS16:=0\nPKG_SSP:=0\n\nSTRIP:=:\n\ninclude $(INCLUDE_DIR)/package.mk\ninclude $(INCLUDE_DIR)/kernel.mk\n\ndefine Package/valgrind\n  SECTION:=devel\n  CATEGORY:=Development\n  DEPENDS:=@mips||mipsel||mips64||mips64el||i386||x86_64||powerpc||arm_v7||aarch64 +libpthread +librt\n  TITLE:=debugging and profiling tools for Linux\n  URL:=http://www.valgrind.org\nendef\n\ndefine Package/valgrind/default\n  $(Package/valgrind)\n  DEPENDS := valgrind\nendef\n\ndefine Package/valgrind-cachegrind\n  $(Package/valgrind/default)\n  TITLE += (cache profiling)\nendef\n\ndefine Package/valgrind-callgrind\n  $(Package/valgrind/default)\n  TITLE += (callgraph profiling)\nendef\n\ndefine Package/valgrind-drd\n  $(Package/valgrind/default)\n  TITLE += (thread error detection)\nendef\n\ndefine Package/valgrind-massif\n  $(Package/valgrind/default)\n  TITLE += (heap profiling)\nendef\n\ndefine Package/valgrind-helgrind\n  $(Package/valgrind/default)\n  TITLE += (thread debugging)\nendef\n\ndefine Package/valgrind-vgdb\n  $(Package/valgrind/default)\n  TITLE += (GDB interface)\nendef\n\ndefine Package/valgrind/description\n\tValgrind is an award-winning suite of tools for debugging and\n\tprofiling Linux programs. With the tools that come with Valgrind,\n\tyou can automatically detect many memory management and threading\n\tbugs, avoiding hours of frustrating bug-hunting, making your\n\tprograms more stable. You can also perform detailed profiling,\n\tto speed up and reduce memory use of your programs.\nendef\n\nCPU := $(patsubst x86_64,amd64,$(patsubst x86,i386,$(patsubst um,$(ARCH),$(LINUX_KARCH))))\n\nCONFIGURE_VARS += \\\n\tUNAME_R=$(LINUX_VERSION)\n\nifeq ($(CONFIG_ARCH_64BIT),y)\n\tCONFIGURE_ARGS += \\\n\t\t--enable-only64bit\n\tBITS := 64bit\nelse\n\tCONFIGURE_ARGS += \\\n\t\t--enable-only32bit\n\tBITS := 32bit\nendif\n\nCONFIGURE_ARGS += \\\n\t--enable-lto \\\n\t--enable-tls \\\n\t--without-x \\\n\t--without-mpicc \\\n\t--without-uiout \\\n\t--disable-valgrindmi \\\n\t--disable-tui \\\n\t--disable-valgrindtk \\\n\t--without-included-gettext \\\n\t--with-pagesize=4 \\\n\ndefine Package/valgrind/install\n\t$(INSTALL_DIR) $(1)/usr/bin\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/bin/valgrind* $(1)/usr/bin/\n\t$(INSTALL_DIR) $(1)/usr/lib/valgrind\n\t$(CP) \\\n\t\t./files/default.supp \\\n\t\t$(PKG_INSTALL_DIR)/usr/lib/valgrind/none-* \\\n\t\t$(PKG_INSTALL_DIR)/usr/lib/valgrind/vgpreload_core*.so \\\n\t\t$(PKG_INSTALL_DIR)/usr/lib/valgrind/$(BITS)-core*.xml \\\n\t\t$(PKG_INSTALL_DIR)/usr/lib/valgrind/$(BITS)-linux*.xml \\\n\t\t$(PKG_INSTALL_DIR)/usr/lib/valgrind/memcheck-* \\\n\t\t$(PKG_INSTALL_DIR)/usr/lib/valgrind/vgpreload_memcheck*.so \\\n\t\t$(1)/usr/lib/valgrind/\n\nifneq ($(ARCH),aarch64)\n\t$(CP) \\\n\t\t$(PKG_INSTALL_DIR)/usr/lib/valgrind/$(CPU)-*.xml \\\n\t\t$(1)/usr/lib/valgrind/\nendif\n\t$(patsubst STRIP=%,STRIP=\"$(TARGET_CROSS)strip\",$(RSTRIP)) $(PKG_INSTALL_DIR)/usr/bin\n\t$(patsubst STRIP=%,STRIP=\"$(TARGET_CROSS)strip -g\",$(RSTRIP)) \\\n\t\t$(PKG_INSTALL_DIR)/usr/lib/valgrind/none-* \\\n\t\t$(PKG_INSTALL_DIR)/usr/lib/valgrind/memcheck-*\nendef\n\ndefine Package/valgrind-cachegrind/install\n\t$(INSTALL_DIR) $(1)/usr/bin\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/bin/cg_* $(1)/usr/bin/\n\t$(INSTALL_DIR) $(1)/usr/lib/valgrind\n\t$(CP) \\\n\t\t$(PKG_INSTALL_DIR)/usr/lib/valgrind/cachegrind-* \\\n\t\t$(1)/usr/lib/valgrind/\n\t$(patsubst STRIP=%,STRIP=\"$(TARGET_CROSS)strip\",$(RSTRIP)) $(PKG_INSTALL_DIR)/usr/bin\n\t$(patsubst STRIP=%,STRIP=\"$(TARGET_CROSS)strip -g\",$(RSTRIP)) $(PKG_INSTALL_DIR)/usr/lib/valgrind/cachegrind-*\nendef\n\ndefine Package/valgrind-callgrind/install\n\t$(INSTALL_DIR) $(1)/usr/bin\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/bin/callgrind* $(1)/usr/bin/\n\t$(INSTALL_DIR) $(1)/usr/lib/valgrind\n\t$(CP) \\\n\t\t$(PKG_INSTALL_DIR)/usr/lib/valgrind/callgrind-* \\\n\t\t$(1)/usr/lib/valgrind/\n\t$(patsubst STRIP=%,STRIP=\"$(TARGET_CROSS)strip\",$(RSTRIP)) $(PKG_INSTALL_DIR)/usr/bin\n\t$(patsubst STRIP=%,STRIP=\"$(TARGET_CROSS)strip -g\",$(RSTRIP)) $(PKG_INSTALL_DIR)/usr/lib/valgrind/callgrind-*\nendef\n\ndefine Package/valgrind-drd/install\n\t$(INSTALL_DIR) $(1)/usr/lib/valgrind\n\t$(CP) \\\n\t\t$(PKG_INSTALL_DIR)/usr/lib/valgrind/drd-* \\\n\t\t$(PKG_INSTALL_DIR)/usr/lib/valgrind/vgpreload_drd*.so \\\n\t\t$(1)/usr/lib/valgrind/\n\t$(patsubst STRIP=%,STRIP=\"$(TARGET_CROSS)strip\",$(RSTRIP)) $(PKG_INSTALL_DIR)/usr/bin\n\t$(patsubst STRIP=%,STRIP=\"$(TARGET_CROSS)strip -g\",$(RSTRIP)) $(PKG_INSTALL_DIR)/usr/lib/valgrind/drd-*\nendef\n\ndefine Package/valgrind-massif/install\n\t$(INSTALL_DIR) $(1)/usr/bin\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/bin/ms_print $(1)/usr/bin/\n\t$(INSTALL_DIR) $(1)/usr/lib/valgrind\n\t$(CP) \\\n\t\t$(PKG_INSTALL_DIR)/usr/lib/valgrind/massif-* \\\n\t\t$(PKG_INSTALL_DIR)/usr/lib/valgrind/vgpreload_massif*.so \\\n\t\t$(1)/usr/lib/valgrind/\n\t$(patsubst STRIP=%,STRIP=\"$(TARGET_CROSS)strip\",$(RSTRIP)) $(PKG_INSTALL_DIR)/usr/bin\n\t$(patsubst STRIP=%,STRIP=\"$(TARGET_CROSS)strip -g\",$(RSTRIP)) $(PKG_INSTALL_DIR)/usr/lib/valgrind/massif-*\nendef\n\ndefine Package/valgrind-helgrind/install\n\t$(INSTALL_DIR) $(1)/usr/lib/valgrind\n\t$(CP) \\\n\t\t$(PKG_INSTALL_DIR)/usr/lib/valgrind/helgrind-* \\\n\t\t$(PKG_INSTALL_DIR)/usr/lib/valgrind/vgpreload_helgrind*.so \\\n\t\t$(1)/usr/lib/valgrind/\n\t$(patsubst STRIP=%,STRIP=\"$(TARGET_CROSS)strip\",$(RSTRIP)) $(PKG_INSTALL_DIR)/usr/bin\n\t$(patsubst STRIP=%,STRIP=\"$(TARGET_CROSS)strip -g\",$(RSTRIP)) $(PKG_INSTALL_DIR)/usr/lib/valgrind/helgrind-*\nendef\n\ndefine Package/valgrind-vgdb/install\n\t$(INSTALL_DIR) $(1)/usr/bin\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/bin/vgdb $(1)/usr/bin/\n\t$(patsubst STRIP=%,STRIP=\"$(TARGET_CROSS)strip\",$(RSTRIP)) $(PKG_INSTALL_DIR)/usr/bin\nendef\n\n$(eval $(call BuildPackage,valgrind))\n$(eval $(call BuildPackage,valgrind-cachegrind))\n$(eval $(call BuildPackage,valgrind-callgrind))\n$(eval $(call BuildPackage,valgrind-drd))\n$(eval $(call BuildPackage,valgrind-massif))\n$(eval $(call BuildPackage,valgrind-helgrind))\n$(eval $(call BuildPackage,valgrind-vgdb))\n"
  },
  {
    "path": "package/devel/valgrind/files/default.supp",
    "content": "{\n   ld(Addr1)\n   Memcheck:Addr1\n   fun:*\n   obj:/lib/ld-*\n}\n{\n   ld(Addr2)\n   Memcheck:Addr2\n   fun:*\n   obj:/lib/ld-*\n}\n{\n   ld(Addr4)\n   Memcheck:Addr4\n   fun:*\n   obj:/lib/ld-*\n}\n{\n   ld(Cond)\n   Memcheck:Cond\n   fun:*\n   obj:/lib/ld-*\n}\n{\n\tstrlen(Cond)\n\tMemcheck:Cond\n\tfun:strlen\n\tfun:*\n}\n{\n\tstrnlen(Cond)\n\tMemcheck:Cond\n\tfun:strnlen\n\tfun:*\n}\n{\n\tindex(Cond)\n\tMemcheck:Cond\n\tfun:index\n\tfun:*\n}\n"
  },
  {
    "path": "package/devel/valgrind/patches/010-mips-Fix-new-syscall-numbers.patch",
    "content": "From 86ab9452bd10f08dbfa22d94e1155838f6f9f2e0 Mon Sep 17 00:00:00 2001\nFrom: Hauke Mehrtens <hauke@hauke-m.de>\nDate: Sun, 31 Oct 2021 23:11:11 +0100\nSubject: [PATCH] mips: Fix new syscall numbers\n\nThe MIPS32 and MIPS64 O32 ABI are adding 4000 to all syscall numbers.\nThe MIPS64 N64 ABI adds 5000 to each syscall and the MIPS64 N32 ABI adds\n6000 to each syscall number. We can not sue the shared file for MIPS and\nhave to define this for each sycall separately.\n\nWithout this change valgrind is not able to detect new syscalls like\nclock_gettime64 correctly.\n\nSigned-off-by: Hauke Mehrtens <hauke@hauke-m.de>\n---\n include/pub_tool_vkiscnums_asm.h      |  3 ---\n include/vki/vki-scnums-mips32-linux.h | 36 +++++++++++++++++++++++++++\n include/vki/vki-scnums-mips64-linux.h | 32 ++++++++++++++++++++++++\n 3 files changed, 68 insertions(+), 3 deletions(-)\n\n--- a/include/pub_tool_vkiscnums_asm.h\n+++ b/include/pub_tool_vkiscnums_asm.h\n@@ -63,15 +63,12 @@\n #  include \"vki/vki-scnums-arm64-linux.h\"\n \n #elif defined(VGP_mips32_linux)\n-#  include \"vki/vki-scnums-shared-linux.h\"\n-#  include \"vki/vki-scnums-32bit-linux.h\"\n #  include \"vki/vki-scnums-mips32-linux.h\"\n \n #elif defined(VGP_nanomips_linux)\n #  include \"vki/vki-scnums-nanomips-linux.h\"\n \n #elif defined(VGP_mips64_linux)\n-#  include \"vki/vki-scnums-shared-linux.h\"\n #  include \"vki/vki-scnums-mips64-linux.h\"\n \n #elif defined(VGP_x86_freebsd) || defined(VGP_amd64_freebsd)\n--- a/include/vki/vki-scnums-mips32-linux.h\n+++ b/include/vki/vki-scnums-mips32-linux.h\n@@ -401,6 +401,42 @@\n #define __NR_pkey_free\t\t\t(__NR_Linux + 365)\n #define __NR_statx\t\t\t(__NR_Linux + 366)\n \n+#define __NR_clock_gettime64\t\t(__NR_Linux + 403)\n+#define __NR_clock_settime64\t\t(__NR_Linux + 404)\n+#define __NR_clock_adjtime64\t\t(__NR_Linux + 405)\n+#define __NR_clock_getres_time64\t(__NR_Linux + 406)\n+#define __NR_clock_nanosleep_time64\t(__NR_Linux + 407)\n+#define __NR_timer_gettime64\t\t(__NR_Linux + 408)\n+#define __NR_timer_settime64\t\t(__NR_Linux + 409)\n+#define __NR_timerfd_gettime64\t\t(__NR_Linux + 410)\n+#define __NR_timerfd_settime64\t\t(__NR_Linux + 411)\n+#define __NR_utimensat_time64\t\t(__NR_Linux + 412)\n+#define __NR_pselect6_time64\t\t(__NR_Linux + 413)\n+#define __NR_ppoll_time64\t\t(__NR_Linux + 414)\n+#define __NR_io_pgetevents_time64\t(__NR_Linux + 416)\n+#define __NR_recvmmsg_time64\t\t(__NR_Linux + 417)\n+#define __NR_mq_timedsend_time64\t(__NR_Linux + 418)\n+#define __NR_mq_timedreceive_time64\t(__NR_Linux + 419)\n+#define __NR_semtimedop_time64\t\t(__NR_Linux + 420)\n+#define __NR_rt_sigtimedwait_time64\t(__NR_Linux + 421)\n+#define __NR_futex_time64\t\t(__NR_Linux + 422)\n+#define __NR_sched_rr_get_interval_time64\t(__NR_Linux + 423)\n+#define __NR_pidfd_send_signal\t\t(__NR_Linux + 424)\n+#define __NR_io_uring_setup\t\t(__NR_Linux + 425)\n+#define __NR_io_uring_enter\t\t(__NR_Linux + 426)\n+#define __NR_io_uring_register\t\t(__NR_Linux + 427)\n+#define __NR_open_tree\t\t\t(__NR_Linux + 428)\n+#define __NR_move_mount\t\t\t(__NR_Linux + 429)\n+#define __NR_fsopen\t\t\t(__NR_Linux + 430)\n+#define __NR_fsconfig\t\t\t(__NR_Linux + 431)\n+#define __NR_fsmount\t\t\t(__NR_Linux + 432)\n+#define __NR_fspick\t\t\t(__NR_Linux + 433)\n+\n+#define __NR_clone3\t\t\t(__NR_Linux + 435)\n+#define __NR_close_range\t\t(__NR_Linux + 436)\n+\n+#define __NR_faccessat2\t\t\t(__NR_Linux + 439)\n+\n /*\n  * Offset of the last Linux o32 flavoured syscall\n  */\n--- a/include/vki/vki-scnums-mips64-linux.h\n+++ b/include/vki/vki-scnums-mips64-linux.h\n@@ -363,6 +363,22 @@\n #define __NR_pkey_free              (__NR_Linux + 325)\n #define __NR_statx                  (__NR_Linux + 326)\n \n+#define __NR_pidfd_send_signal       (__NR_Linux + 424)\n+#define __NR_io_uring_setup          (__NR_Linux + 425)\n+#define __NR_io_uring_enter          (__NR_Linux + 426)\n+#define __NR_io_uring_register       (__NR_Linux + 427)\n+#define __NR_open_tree               (__NR_Linux + 428)\n+#define __NR_move_mount              (__NR_Linux + 429)\n+#define __NR_fsopen                  (__NR_Linux + 430)\n+#define __NR_fsconfig                (__NR_Linux + 431)\n+#define __NR_fsmount                 (__NR_Linux + 432)\n+#define __NR_fspick                  (__NR_Linux + 433)\n+\n+#define __NR_clone3                  (__NR_Linux + 435)\n+#define __NR_close_range             (__NR_Linux + 436)\n+\n+#define __NR_faccessat2              (__NR_Linux + 439)\n+\n #elif defined(VGABI_N32)\n \n /*\n@@ -702,6 +718,22 @@\n #define __NR_pkey_free               (__NR_Linux + 329)\n #define __NR_statx                   (__NR_Linux + 330)\n \n+#define __NR_pidfd_send_signal       (__NR_Linux + 424)\n+#define __NR_io_uring_setup          (__NR_Linux + 425)\n+#define __NR_io_uring_enter          (__NR_Linux + 426)\n+#define __NR_io_uring_register       (__NR_Linux + 427)\n+#define __NR_open_tree               (__NR_Linux + 428)\n+#define __NR_move_mount              (__NR_Linux + 429)\n+#define __NR_fsopen                  (__NR_Linux + 430)\n+#define __NR_fsconfig                (__NR_Linux + 431)\n+#define __NR_fsmount                 (__NR_Linux + 432)\n+#define __NR_fspick                  (__NR_Linux + 433)\n+\n+#define __NR_clone3                  (__NR_Linux + 435)\n+#define __NR_close_range             (__NR_Linux + 436)\n+\n+#define __NR_faccessat2              (__NR_Linux + 439)\n+\n #else\n #error unknown mips64 abi\n #endif\n"
  },
  {
    "path": "package/devel/valgrind/patches/100-fix_configure_check.patch",
    "content": "--- a/configure.ac\n+++ b/configure.ac\n@@ -345,7 +345,7 @@ case \"${host_os}\" in\n         # Ok, this is linux. Check the kernel version\n         AC_MSG_CHECKING([for the kernel version])\n \n-        kernel=`uname -r`\n+        kernel=${UNAME_R:-`uname -r`}\n \n         case \"${kernel}\" in\n              0.*|1.*|2.0.*|2.1.*|2.2.*|2.3.*|2.4.*|2.5.*) \n"
  },
  {
    "path": "package/devel/valgrind/patches/130-fix_arm_arch_detection.patch",
    "content": "Description: Fix FTBFS on armhf by correctly detecting the architecture\nOrigin: vendor\nBug-Debian: http://bugs.debian.org/730844\nAuthor: Alessandro Ghedini <ghedo@debian.org>\nLast-Update: 2013-11-30\n\n--- a/configure.ac\n+++ b/configure.ac\n@@ -252,7 +252,7 @@ case \"${host_cpu}\" in\n         ARCH_MAX=\"s390x\"\n         ;;\n \n-     armv7*)\n+     arm*)\n \tAC_MSG_RESULT([ok (${host_cpu})])\n \tARCH_MAX=\"arm\"\n \t;;\n"
  },
  {
    "path": "package/devel/valgrind/patches/130-mips_fix_soft_float.patch",
    "content": "Disable the valgrind helpers which use MIPS floating point operations \nwhen floating point support is deactivated in the toolchain.\n\nThe fix from this commit is not sufficient any more:\nhttps://sourceware.org/git/?p=valgrind.git;a=commitdiff;h=869fcf2f6739f17b4eff36ec68f8dca826c8afeb\n\nThis fixes the following error message when compiling with a GCC 10 MIPS BE 32:\n---------------------------------------------------------\n../VEX/priv/guest_mips_helpers.c: In function 'mips_dirtyhelper_calculate_FCSR_fp32':\n../VEX/priv/guest_mips_helpers.c:640:10: error: the register '$f21' cannot be clobbered in 'asm' for the current target\n  640 |          ASM_VOLATILE_UNARY32_DOUBLE(round.w.d)\n      |          ^\n---------------------------------------------------------\n\n--- a/VEX/priv/guest_mips_helpers.c\n+++ b/VEX/priv/guest_mips_helpers.c\n@@ -616,6 +616,7 @@ extern UInt mips_dirtyhelper_calculate_F\n                                                    flt_op inst )\n {\n    UInt ret = 0;\n+#ifndef __mips_soft_float\n #if defined(__mips__)\n    VexGuestMIPS32State* guest_state = (VexGuestMIPS32State*)gs;\n    UInt loFsVal, hiFsVal, loFtVal, hiFtVal;\n@@ -698,6 +699,7 @@ extern UInt mips_dirtyhelper_calculate_F\n          break;\n    }\n #endif\n+#endif\n    return ret;\n }\n \n@@ -707,6 +709,7 @@ extern UInt mips_dirtyhelper_calculate_F\n                                                    flt_op inst )\n {\n    UInt ret = 0;\n+#ifndef __mips_soft_float\n #if defined(__mips__) && ((__mips == 64) ||                                  \\\n                           (defined(__mips_isa_rev) && (__mips_isa_rev >= 2)))\n #if defined(VGA_mips32)\n@@ -859,6 +862,7 @@ extern UInt mips_dirtyhelper_calculate_F\n          break;\n    }\n #endif\n+#endif\n    return ret;\n }\n \n--- a/coregrind/m_machine.c\n+++ b/coregrind/m_machine.c\n@@ -2103,6 +2103,7 @@ Bool VG_(machine_get_hwcaps)( void )\n            we are using alternative way to determine FP mode */\n         ULong result = 0;\n \n+#ifndef __mips_soft_float\n         if (!VG_MINIMAL_SETJMP(env_unsup_insn)) {\n            __asm__ volatile (\n               \".set push\\n\\t\"\n@@ -2120,6 +2121,9 @@ Bool VG_(machine_get_hwcaps)( void )\n \n            fpmode = (result != 0x3FF0000000000000ull);\n         }\n+#else\n+\tfpmode = 0;\n+#endif\n      }\n \n      if (fpmode != 0)\n"
  },
  {
    "path": "package/firmware/ath10k-ct-firmware/Makefile",
    "content": "include $(TOPDIR)/rules.mk\n\nPKG_NAME:=ath10k-ct-firmware\nPKG_VERSION:=2020-11-08\nPKG_RELEASE:=1\n\ninclude $(INCLUDE_DIR)/package.mk\n\nCT_FIRMWARE_FILE = $(1)-$($(1)_FIRMWARE_FILE_CT)\nCT_FIRMWARE_FILE_FULL_HTT = $(1)-$($(1)_FIRMWARE_FILE_CT_FULL_HTT)\nCT_FIRMWARE_FILE_HTT = $(1)-$($(1)_FIRMWARE_FILE_CT_HTT)\n\ndefine Download/ct-firmware\n  URL:=https://www.candelatech.com/downloads/$(2)\n  FILE:=$(call CT_FIRMWARE_FILE,$(1))\n  URL_FILE:=$($(1)_FIRMWARE_FILE_CT)\nendef\n\ndefine Download/ct-firmware-full-htt\n  URL:=https://www.candelatech.com/downloads/$(2)\n  FILE:=$(call CT_FIRMWARE_FILE_FULL_HTT,$(1))\n  URL_FILE:=$($(1)_FIRMWARE_FILE_CT_FULL_HTT)\nendef\n\ndefine Download/ct-firmware-htt\n  URL:=https://www.candelatech.com/downloads/$(2)\n  FILE:=$(call CT_FIRMWARE_FILE_HTT,$(1))\n  URL_FILE:=$($(1)_FIRMWARE_FILE_CT_HTT)\nendef\n\nQCA988X_FIRMWARE_FILE_CT:=firmware-2-ct-full-community-22.bin.lede.022\ndefine Download/ath10k-firmware-qca988x-ct\n  $(call Download/ct-firmware,QCA988X,)\n  HASH:=398e4380e7e55105f3da0f78af29d1e437404ed3a82597aa4b6daaa7dce1a38e\nendef\n$(eval $(call Download,ath10k-firmware-qca988x-ct))\n\nQCA988X_FIRMWARE_FILE_CT_FULL_HTT:=firmware-2-ct-full-htt-mgt-community-22.bin.lede.022\ndefine Download/ath10k-firmware-qca988x-ct-full-htt\n  $(call Download/ct-firmware-full-htt,QCA988X,)\n  HASH:=990d9cbf79dd81f141257a289f89808bd7726406c9ed845a7e49e5167002ffde\nendef\n$(eval $(call Download,ath10k-firmware-qca988x-ct-full-htt))\n\n\nQCA9887_FIRMWARE_FILE_CT:=firmware-2-ct-full-community-22.bin.lede.022\ndefine Download/ath10k-firmware-qca9887-ct\n  $(call Download/ct-firmware,QCA9887,ath10k-9887)\n  HASH:=a526cb44560da569781e10bf608194b1eff29b250e9887dba6d4d9a15c921c1e\nendef\n$(eval $(call Download,ath10k-firmware-qca9887-ct))\n\nQCA9887_FIRMWARE_FILE_CT_FULL_HTT:=firmware-2-ct-full-htt-mgt-community-22.bin.lede.022\ndefine Download/ath10k-firmware-qca9887-ct-full-htt\n  $(call Download/ct-firmware-full-htt,QCA9887,ath10k-9887)\n  HASH:=0b60fc558b773e9cbd5c2df903c894a030872fdb96390b0cca4b23b7fc7b881f\nendef\n$(eval $(call Download,ath10k-firmware-qca9887-ct-full-htt))\n\n\nQCA99X0_FIRMWARE_FILE_CT:=firmware-5-ct-full-community-12.bin-lede.022\ndefine Download/ath10k-firmware-qca99x0-ct\n  $(call Download/ct-firmware,QCA99X0,ath10k-10-4b)\n  HASH:=578ad67976b61a393eb820a05e8eae70ec95f6b803bedbe952b8ff573eb09abe\nendef\n$(eval $(call Download,ath10k-firmware-qca99x0-ct))\n\nQCA99X0_FIRMWARE_FILE_CT_FULL_HTT:=firmware-5-ct-full-htt-mgt-community-12.bin-lede.022\ndefine Download/ath10k-firmware-qca99x0-ct-full-htt\n  $(call Download/ct-firmware-full-htt,QCA99X0,ath10k-10-4b)\n  HASH:=8ea5c9f27c048796d406706a9c8471cd070f5aeb768622bb334a04853d557a4d\nendef\n$(eval $(call Download,ath10k-firmware-qca99x0-ct-full-htt))\n\nQCA99X0_FIRMWARE_FILE_CT_HTT:=firmware-5-ct-htt-mgt-community-12.bin-lede.022\ndefine Download/ath10k-firmware-qca99x0-ct-htt\n  $(call Download/ct-firmware-htt,QCA99X0,ath10k-10-4b)\n  HASH:=7b0b7545114e8dc0f2c70dc8a43a5a48d84d37f2a4673977a692c5f3361445c6\nendef\n$(eval $(call Download,ath10k-firmware-qca99x0-ct-htt))\n\n\nQCA9984_FIRMWARE_FILE_CT:=firmware-5-ct-full-community-12.bin-lede.022\ndefine Download/ath10k-firmware-qca9984-ct\n  $(call Download/ct-firmware,QCA9984,ath10k-9984-10-4b)\n  HASH:=7bfe5bf7c38532fa57db62ebc56ec625583928d5d4736475d5dec4d4ae031154\nendef\n$(eval $(call Download,ath10k-firmware-qca9984-ct))\n\nQCA9984_FIRMWARE_FILE_CT_FULL_HTT:=firmware-5-ct-full-htt-mgt-community-12.bin-lede.022\ndefine Download/ath10k-firmware-qca9984-ct-full-htt\n  $(call Download/ct-firmware-full-htt,QCA9984,ath10k-9984-10-4b)\n  HASH:=672be40c4d987d7e8e309341262a37cda7baf925416d1dc651284b6d2bd30969\nendef\n$(eval $(call Download,ath10k-firmware-qca9984-ct-full-htt))\n\nQCA9984_FIRMWARE_FILE_CT_HTT:=firmware-5-ct-htt-mgt-community-12.bin-lede.022\ndefine Download/ath10k-firmware-qca9984-ct-htt\n  $(call Download/ct-firmware-htt,QCA9984,ath10k-9984-10-4b)\n  HASH:=a24e887f13aca4358ab2b6a42a7212d066e4d19e29b00bb26f9681b1dc8d0eb0\nendef\n$(eval $(call Download,ath10k-firmware-qca9984-ct-htt))\n\n\nQCA4019_FIRMWARE_FILE_CT:=firmware-5-ct-full-community-12.bin-lede.022\ndefine Download/ath10k-firmware-qca4019-ct\n  $(call Download/ct-firmware,QCA4019,ath10k-4019-10-4b)\n  HASH:=503956d9bf09d603e4cf36ac080fa5b5a22032166204e3c15ae898647bc50df3\nendef\n$(eval $(call Download,ath10k-firmware-qca4019-ct))\n\nQCA4019_FIRMWARE_FILE_CT_FULL_HTT:=firmware-5-ct-full-htt-mgt-community-12.bin-lede.022\ndefine Download/ath10k-firmware-qca4019-ct-full-htt\n  $(call Download/ct-firmware-full-htt,QCA4019,ath10k-4019-10-4b)\n  HASH:=591bf9ed00fb540d7ba034453f17696e8dd91a4b7d81f7cc1ec41f447fa74831\nendef\n$(eval $(call Download,ath10k-firmware-qca4019-ct-full-htt))\n\nQCA4019_FIRMWARE_FILE_CT_HTT:=firmware-5-ct-htt-mgt-community-12.bin-lede.022\ndefine Download/ath10k-firmware-qca4019-ct-htt\n  $(call Download/ct-firmware-htt,QCA4019,ath10k-4019-10-4b)\n  HASH:=06e58a283ff90d021ff7cb58684cbf39750bd71cf91c56b32add64253133929c\nendef\n$(eval $(call Download,ath10k-firmware-qca4019-ct-htt))\n\n\nQCA9888_FIRMWARE_FILE_CT:=firmware-5-ct-full-community-12.bin-lede.022\ndefine Download/ath10k-firmware-qca9888-ct\n  $(call Download/ct-firmware,QCA9888,ath10k-9888-10-4b)\n  HASH:=82ff5afcf0c9dcdb03b0b40c6eddc81e11b18e4f522f681935b5ec42537972ee\nendef\n$(eval $(call Download,ath10k-firmware-qca9888-ct))\n\nQCA9888_FIRMWARE_FILE_CT_FULL_HTT:=firmware-5-ct-full-htt-mgt-community-12.bin-lede.022\ndefine Download/ath10k-firmware-qca9888-ct-full-htt\n  $(call Download/ct-firmware-full-htt,QCA9888,ath10k-9888-10-4b)\n  HASH:=1a741f2cf43fbea24ed831b4e76cbb114b525d1ee9b917ce0000916cbcc42f92\nendef\n$(eval $(call Download,ath10k-firmware-qca9888-ct-full-htt))\n\nQCA9888_FIRMWARE_FILE_CT_HTT:=firmware-5-ct-htt-mgt-community-12.bin-lede.022\ndefine Download/ath10k-firmware-qca9888-ct-htt\n  $(call Download/ct-firmware-htt,QCA9888,ath10k-9888-10-4b)\n  HASH:=34bf07912a2f3fce4a5887c690848bb06d339bd1c86541b0b57b9c45eccc88e4\nendef\n$(eval $(call Download,ath10k-firmware-qca9888-ct-htt))\n\n\ndefine Package/ath10k-ct-firmware-default\n  SECTION:=firmware\n  CATEGORY:=Firmware\n  URL:=https://www.candelatech.com/ath10k.php\n  DEPENDS:=\nendef\n\ndefine Package/ath10k-firmware-qca988x-ct\n$(Package/ath10k-ct-firmware-default)\n  TITLE:=ath10k CT 10.1 firmware for QCA988x devices\n  SECTION:=firmware\n  CATEGORY:=Firmware\n  PROVIDES:=ath10k-firmware-qca988x\n  CONFLICTS:=ath10k-firmware-qca988x\n  DEPENDS:=+ath10k-board-qca988x\nendef\ndefine Package/ath10k-firmware-qca988x-ct-full-htt\n$(Package/ath10k-ct-firmware-default)\n  TITLE:=ath10k CT 10.1 full-htt-mgt fw for QCA988x\n  SECTION:=firmware\n  CATEGORY:=Firmware\n  PROVIDES:=\\\n    ath10k-firmware-qca988x \\\n    ath10k-firmware-qca988x-ct\n  CONFLICTS:=\\\n    ath10k-firmware-qca988x \\\n    ath10k-firmware-qca988x-ct\n  DEPENDS:=\\\n    +ath10k-board-qca988x \\\n    +!PACKAGE_kmod-ath10k-ct-smallbuffers:kmod-ath10k-ct\nendef\n\ndefine Package/ath10k-firmware-qca9887-ct\n$(Package/ath10k-ct-firmware-default)\n  TITLE:=ath10k CT 10.1 firmware for QCA9887 devices\n  SECTION:=firmware\n  CATEGORY:=Firmware\n  PROVIDES:=ath10k-firmware-qca9887\n  CONFLICTS:=ath10k-firmware-qca9887\n  DEPENDS:=+ath10k-board-qca9887\nendef\ndefine Package/ath10k-firmware-qca9887-ct-full-htt\n$(Package/ath10k-ct-firmware-default)\n  TITLE:=ath10k CT 10.1 full-htt-mgt fw for QCA9887\n  SECTION:=firmware\n  CATEGORY:=Firmware\n  PROVIDES:=\\\n    ath10k-firmware-qca9887 \\\n    ath10k-firmware-qca9887-ct\n  CONFLICTS:=\\\n    ath10k-firmware-qca9887 \\\n    ath10k-firmware-qca9887-ct\n  DEPENDS:=\\\n    +ath10k-board-qca9887 \\\n    +!PACKAGE_kmod-ath10k-ct-smallbuffers:kmod-ath10k-ct\nendef\n\ndefine Package/ath10k-firmware-qca99x0-ct\n$(Package/ath10k-ct-firmware-default)\n  TITLE:=ath10k CT 10.4 firmware for QCA99x0 devices\n  SECTION:=firmware\n  CATEGORY:=Firmware\n  PROVIDES:=ath10k-firmware-qca99x0\n  CONFLICTS:=ath10k-firmware-qca99x0\n  DEPENDS:=+ath10k-board-qca99x0\nendef\ndefine Package/ath10k-firmware-qca99x0-ct-full-htt\n$(Package/ath10k-ct-firmware-default)\n  TITLE:=ath10k CT 10.4 full-htt-mgt fw for QCA99x0\n  SECTION:=firmware\n  CATEGORY:=Firmware\n  PROVIDES:=\\\n    ath10k-firmware-qca99x0 \\\n    ath10k-firmware-qca99x0-ct\n  CONFLICTS:=\\\n    ath10k-firmware-qca99x0 \\\n    ath10k-firmware-qca99x0-ct \\\n    ath10k-firmware-qca99x0-ct-htt\n  DEPENDS:=\\\n    +ath10k-board-qca99x0 \\\n    +!PACKAGE_kmod-ath10k-ct-smallbuffers:kmod-ath10k-ct\nendef\ndefine Package/ath10k-firmware-qca99x0-ct-htt\n$(Package/ath10k-firmware-default)\n  TITLE:=ath10k CT 10.4 htt-mgt fw for QCA99x0\n  SECTION:=firmware\n  CATEGORY:=Firmware\n  PROVIDES:=\\\n    ath10k-firmware-qca99x0 \\\n    ath10k-firmware-qca99x0-ct\n  CONFLICTS:=\\\n    ath10k-firmware-qca99x0 \\\n    ath10k-firmware-qca99x0-ct\n  DEPENDS:=\\\n    +ath10k-board-qca99x0 \\\n    +!PACKAGE_kmod-ath10k-ct-smallbuffers:kmod-ath10k-ct\nendef\n\ndefine Package/ath10k-firmware-qca9984-ct\n$(Package/ath10k-ct-firmware-default)\n  TITLE:=ath10k CT 10.4 firmware for QCA9984 devices\n  SECTION:=firmware\n  CATEGORY:=Firmware\n  PROVIDES:=ath10k-firmware-qca9984\n  CONFLICTS:=ath10k-firmware-qca9984\n  DEPENDS:=+ath10k-board-qca9984\nendef\ndefine Package/ath10k-firmware-qca9984-ct-full-htt\n$(Package/ath10k-ct-firmware-default)\n  TITLE:=ath10k CT 10.4 full-htt-mgt fw for QCA9984\n  SECTION:=firmware\n  CATEGORY:=Firmware\n  PROVIDES:=\\\n    ath10k-firmware-qca9984 \\\n    ath10k-firmware-qca9984-ct\n  CONFLICTS:=\\\n    ath10k-firmware-qca9984 \\\n    ath10k-firmware-qca9984-ct \\\n    ath10k-firmware-qca9984-ct-htt\n  DEPENDS:=\\\n    +ath10k-board-qca9984 \\\n    +!PACKAGE_kmod-ath10k-ct-smallbuffers:kmod-ath10k-ct\nendef\ndefine Package/ath10k-firmware-qca9984-ct-htt\n$(Package/ath10k-firmware-default)\n  TITLE:=ath10k CT 10.4 htt-mgt fw for QCA9984\n  SECTION:=firmware\n  CATEGORY:=Firmware\n  PROVIDES:=\\\n    ath10k-firmware-qca9984 \\\n    ath10k-firmware-qca9984-ct\n  CONFLICTS:=\\\n    ath10k-firmware-qca9984 \\\n    ath10k-firmware-qca9984-ct\n  DEPENDS:=\\\n    +ath10k-board-qca9984 \\\n    +!PACKAGE_kmod-ath10k-ct-smallbuffers:kmod-ath10k-ct\nendef\n\ndefine Package/ath10k-firmware-qca4019-ct\n$(Package/ath10k-ct-firmware-default)\n  TITLE:=ath10k CT 10.4 firmware for QCA4018/9\n  SECTION:=firmware\n  CATEGORY:=Firmware\n  PROVIDES:=ath10k-firmware-qca4019\n  CONFLICTS:=ath10k-firmware-qca4019\nendef\ndefine Package/ath10k-firmware-qca4019-ct-full-htt\n$(Package/ath10k-ct-firmware-default)\n  TITLE:=ath10k CT 10.4 full-htt-mgt for QCA4018/9\n  SECTION:=firmware\n  CATEGORY:=Firmware\n  PROVIDES:=\\\n    ath10k-firmware-qca4019 \\\n    ath10k-firmware-qca4019-ct\n  CONFLICTS:=\\\n    ath10k-firmware-qca4019 \\\n    ath10k-firmware-qca4019-ct \\\n    ath10k-firmware-qca4019-ct-htt\n  DEPENDS:=\\\n    +!PACKAGE_kmod-ath10k-ct-smallbuffers:kmod-ath10k-ct\nendef\ndefine Package/ath10k-firmware-qca4019-ct-htt\n$(Package/ath10k-firmware-default)\n  TITLE:=ath10k CT 10.4 htt-mgt for QCA4018/9\n  SECTION:=firmware\n  CATEGORY:=Firmware\n  PROVIDES:=\\\n    ath10k-firmware-qca4019 \\\n    ath10k-firmware-qca4019-ct\n  CONFLICTS:=\\\n    ath10k-firmware-qca4019 \\\n    ath10k-firmware-qca4019-ct\n  DEPENDS:=\\\n    +!PACKAGE_kmod-ath10k-ct-smallbuffers:kmod-ath10k-ct\nendef\n\ndefine Package/ath10k-firmware-qca9888-ct\n$(Package/ath10k-ct-firmware-default)\n  TITLE:=ath10k CT 10.4 fw for QCA9886/8 devices\n  SECTION:=firmware\n  CATEGORY:=Firmware\n  PROVIDES:=ath10k-firmware-qca9888\n  CONFLICTS:=ath10k-firmware-qca9888\n  DEPENDS:=+ath10k-board-qca9888\nendef\ndefine Package/ath10k-firmware-qca9888-ct-full-htt\n$(Package/ath10k-ct-firmware-default)\n  TITLE:=ath10k CT 10.4 full-htt-mgt fw for QCA9886/8\n  SECTION:=firmware\n  CATEGORY:=Firmware\n  PROVIDES:=\\\n    ath10k-firmware-qca9888 \\\n    ath10k-firmware-qca9888-ct\n  CONFLICTS:=\\\n    ath10k-firmware-qca9888 \\\n    ath10k-firmware-qca9888-ct \\\n    ath10k-firmware-qca9888-ct-htt\n  DEPENDS:=\\\n    +ath10k-board-qca9888 \\\n    +!PACKAGE_kmod-ath10k-ct-smallbuffers:kmod-ath10k-ct\nendef\ndefine Package/ath10k-firmware-qca9888-ct-htt\n$(Package/ath10k-firmware-default)\n  TITLE:=ath10k CT 10.4 htt-mgt fw for QCA9886/8\n  SECTION:=firmware\n  CATEGORY:=Firmware\n  PROVIDES:=\\\n    ath10k-firmware-qca9888 \\\n    ath10k-firmware-qca9888-ct\n  CONFLICTS:=\\\n    ath10k-firmware-qca9888 \\\n    ath10k-firmware-qca9888-ct\n  DEPENDS:=\\\n    +ath10k-board-qca9888 \\\n    +!PACKAGE_kmod-ath10k-ct-smallbuffers:kmod-ath10k-ct\nendef\n\n\ndefine Package/ath10k-firmware-qca9887-ct/description\nAlternative ath10k firmware for QCA9887 from Candela Technologies.\nEnables IBSS and other features.  See:\nhttp://www.candelatech.com/ath10k-10.1.php\nThis firmware conflicts with the standard 9887 firmware, so select only\none.\nendef\ndefine Package/ath10k-firmware-qca9887-ct-full-htt/description\nAlternative ath10k firmware for QCA9887 from Candela Technologies.\nUses normal HTT TX data path for management frames, which improves\nstability in busy networks and fixes .11r authentication.\nEnables IBSS and other features.  See:\nhttp://www.candelatech.com/ath10k-10.1.php\nThis firmware selects and requires the ath10k-ct driver.\nendef\n\ndefine Package/ath10k-firmware-qca988x-ct/description\nAlternative ath10k firmware for QCA988X from Candela Technologies.\nEnables IBSS and other features.  See:\nhttp://www.candelatech.com/ath10k-10.1.php\nThis firmware will NOT be used unless the standard ath10k-firmware-qca988x\nis un-selected since the driver will try to load firmware-5.bin before\nfirmware-2.bin\nendef\ndefine Package/ath10k-firmware-qca988x-ct-full-htt/description\nAlternative ath10k firmware for QCA988X from Candela Technologies.\nUses normal HTT TX data path for management frames, which improves\nstability in busy networks and fixes .11r authentication.\nEnables IBSS and other features.  See:\nhttp://www.candelatech.com/ath10k-10.1.php\nThis firmware selects and requires the ath10k-ct driver.\nendef\n\ndefine Package/ath10k-firmware-qca99x0-ct/description\nAlternative ath10k firmware for QCA99x0 from Candela Technologies.\nEnables IBSS and other features.  See:\nhttp://www.candelatech.com/ath10k-10.4.php\nThis firmware conflicts with the standard 99x0 firmware, so select only\none.\nendef\ndefine Package/ath10k-firmware-qca99x0-ct-full-htt/description\nAlternative ath10k firmware for QCA99x0 from Candela Technologies.\nUses normal HTT TX data path for management frames, which improves\nstability in busy networks and may be required for .11r authentication.\nEnables IBSS and other features.  See:\nhttp://www.candelatech.com/ath10k-10.4.php\nThis firmware selects and requires the ath10k-ct driver.\nendef\ndefine Package/ath10k-firmware-qca99x0-ct-htt/description\nAlternative ath10k firmware for QCA99x0 from Candela Technologies.\nUses normal HTT TX data path for management frames, which improves\nstability in busy networks and may be required for .11r authentication.\nThis firmware lacks a lot of features that ath10k does not use, saving\na lot of resources.\nEnables IBSS and other features.  See:\nhttp://www.candelatech.com/ath10k-10.4.php\nThis firmware selects and requires the ath10k-ct driver.\nendef\n\ndefine Package/ath10k-firmware-qca9984-ct/description\nAlternative ath10k firmware for QCA9984 from Candela Technologies.\nEnables IBSS and other features.  See:\nhttp://www.candelatech.com/ath10k-10.4.php\nThis firmware conflicts with the standard 9984 firmware, so select only\none.\nendef\ndefine Package/ath10k-firmware-qca9984-ct-full-htt/description\nAlternative ath10k firmware for QCA9984 from Candela Technologies.\nUses normal HTT TX data path for management frames, which improves\nstability in busy networks and may be required for .11r authentication.\nEnables IBSS and other features.  See:\nhttp://www.candelatech.com/ath10k-10.4.php\nThis firmware selects and requires the ath10k-ct driver.\nendef\ndefine Package/ath10k-firmware-qca9984-ct-htt/description\nAlternative ath10k firmware for QCA9984 from Candela Technologies.\nUses normal HTT TX data path for management frames, which improves\nstability in busy networks and may be required for .11r authentication.\nThis firmware lacks a lot of features that ath10k does not use, saving\na lot of resources.\nEnables IBSS and other features.  See:\nhttp://www.candelatech.com/ath10k-10.4.php\nThis firmware selects and requires the ath10k-ct driver.\nendef\n\ndefine Package/ath10k-firmware-qca4019-ct/description\nAlternative ath10k firmware for IPQ4019 radio from Candela Technologies.\nEnables IBSS and other features.  Works with standard or ath10k-ct driver.\nSee:  http://www.candelatech.com/ath10k-10.4.php\nendef\ndefine Package/ath10k-firmware-qca4019-ct-full-htt/description\nAlternative ath10k firmware for IPQ4019 radio from Candela Technologies.\nUses normal HTT TX data path for management frames, which improves\nstability in busy networks and may be required for .11r authentication.\nEnables IBSS and other features.\nSee:  http://www.candelatech.com/ath10k-10.4.php\nThis firmware selects and requires the ath10k-ct driver.\nendef\ndefine Package/ath10k-firmware-qca4019-ct-htt/description\nAlternative ath10k firmware for IPQ4019 radio from Candela Technologies.\nUses normal HTT TX data path for management frames, which improves\nstability in busy networks and may be required for .11r authentication.\nThis firmware lacks a lot of features that ath10k does not use, saving\na lot of resources.\nEnables IBSS and other features.\nSee:  http://www.candelatech.com/ath10k-10.4.php\nThis firmware selects and requires the ath10k-ct driver.\nendef\n\ndefine Package/ath10k-firmware-qca9888-ct/description\nAlternative ath10k firmware for QCA9886 and QCA9888 from Candela Technologies.\nEnables IBSS and other features.  See:\nhttp://www.candelatech.com/ath10k-10.4.php\nThis firmware conflicts with the standard 9886 and 9888 firmware, so select only\none.\nendef\ndefine Package/ath10k-firmware-qca9888-ct-full-htt/description\nAlternative ath10k firmware for QCA9886 and QCA9888 from Candela Technologies.\nUses normal HTT TX data path for management frames, which improves\nstability in busy networks and may be required for .11r authentication.\nEnables IBSS and other features.  See:\nhttp://www.candelatech.com/ath10k-10.4.php\nThis firmware selects and requires the ath10k-ct driver.\nendef\ndefine Package/ath10k-firmware-qca9888-ct-htt/description\nAlternative ath10k firmware for QCA9886 and QCA9888 from Candela Technologies.\nUses normal HTT TX data path for management frames, which improves\nstability in busy networks and may be required for .11r authentication.\nThis firmware lacks a lot of features that ath10k does not use, saving\na lot of resources.\nEnables IBSS and other features.  See:\nhttp://www.candelatech.com/ath10k-10.4.php\nThis firmware selects and requires the ath10k-ct driver.\nendef\n\n\ndefine Build/Compile\n\nendef\n\n\ndefine Package/ath10k-firmware-qca9887-ct/install\n\t$(INSTALL_DIR) $(1)/lib/firmware/ath10k/QCA9887/hw1.0\n\t$(INSTALL_DATA) \\\n\t\t$(DL_DIR)/$(call CT_FIRMWARE_FILE,QCA9887) \\\n\t\t$(1)/lib/firmware/ath10k/QCA9887/hw1.0/firmware-2.bin\nendef\ndefine Package/ath10k-firmware-qca9887-ct-full-htt/install\n\t$(INSTALL_DIR) $(1)/lib/firmware/ath10k/QCA9887/hw1.0\n\t$(INSTALL_DATA) \\\n\t\t$(DL_DIR)/$(call CT_FIRMWARE_FILE_FULL_HTT,QCA9887) \\\n\t\t$(1)/lib/firmware/ath10k/QCA9887/hw1.0/ct-firmware-2.bin\nendef\n\ndefine Package/ath10k-firmware-qca988x-ct/install\n\t$(INSTALL_DIR) $(1)/lib/firmware/ath10k/QCA988X/hw2.0\n\t$(INSTALL_DATA) \\\n\t\t$(DL_DIR)/$(call CT_FIRMWARE_FILE,QCA988X) \\\n\t\t$(1)/lib/firmware/ath10k/QCA988X/hw2.0/firmware-2.bin\nendef\ndefine Package/ath10k-firmware-qca988x-ct-full-htt/install\n\t$(INSTALL_DIR) $(1)/lib/firmware/ath10k/QCA988X/hw2.0\n\t$(INSTALL_DATA) \\\n\t\t$(DL_DIR)/$(call CT_FIRMWARE_FILE_FULL_HTT,QCA988X) \\\n\t\t$(1)/lib/firmware/ath10k/QCA988X/hw2.0/ct-firmware-2.bin\nendef\n\ndefine Package/ath10k-firmware-qca99x0-ct/install\n\t$(INSTALL_DIR) $(1)/lib/firmware/ath10k/QCA99X0/hw2.0\n\t$(INSTALL_DATA) \\\n\t\t$(DL_DIR)/$(call CT_FIRMWARE_FILE,QCA99X0) \\\n\t\t$(1)/lib/firmware/ath10k/QCA99X0/hw2.0/firmware-5.bin\nendef\ndefine Package/ath10k-firmware-qca99x0-ct-full-htt/install\n\t$(INSTALL_DIR) $(1)/lib/firmware/ath10k/QCA99X0/hw2.0\n\t$(INSTALL_DATA) \\\n\t\t$(DL_DIR)/$(call CT_FIRMWARE_FILE_FULL_HTT,QCA99X0) \\\n\t\t$(1)/lib/firmware/ath10k/QCA99X0/hw2.0/ct-firmware-5.bin\nendef\ndefine Package/ath10k-firmware-qca99x0-ct-htt/install\n\t$(INSTALL_DIR) $(1)/lib/firmware/ath10k/QCA99X0/hw2.0\n\t$(INSTALL_DATA) \\\n\t\t$(DL_DIR)/$(call CT_FIRMWARE_FILE_HTT,QCA99X0) \\\n\t\t$(1)/lib/firmware/ath10k/QCA99X0/hw2.0/ct-firmware-5.bin\nendef\n\ndefine Package/ath10k-firmware-qca9984-ct/install\n\t$(INSTALL_DIR) $(1)/lib/firmware/ath10k/QCA9984/hw1.0\n\t$(INSTALL_DATA) \\\n\t\t$(DL_DIR)/$(call CT_FIRMWARE_FILE,QCA9984) \\\n\t\t$(1)/lib/firmware/ath10k/QCA9984/hw1.0/firmware-5.bin\nendef\ndefine Package/ath10k-firmware-qca9984-ct-full-htt/install\n\t$(INSTALL_DIR) $(1)/lib/firmware/ath10k/QCA9984/hw1.0\n\t$(INSTALL_DATA) \\\n\t\t$(DL_DIR)/$(call CT_FIRMWARE_FILE_FULL_HTT,QCA9984) \\\n\t\t$(1)/lib/firmware/ath10k/QCA9984/hw1.0/ct-firmware-5.bin\nendef\ndefine Package/ath10k-firmware-qca9984-ct-htt/install\n\t$(INSTALL_DIR) $(1)/lib/firmware/ath10k/QCA9984/hw1.0\n\t$(INSTALL_DATA) \\\n\t\t$(DL_DIR)/$(call CT_FIRMWARE_FILE_HTT,QCA9984) \\\n\t\t$(1)/lib/firmware/ath10k/QCA9984/hw1.0/ct-firmware-5.bin\nendef\n\ndefine Package/ath10k-firmware-qca4019-ct/install\n\t$(INSTALL_DIR) $(1)/lib/firmware/ath10k/QCA4019/hw1.0\n\t$(INSTALL_DATA) \\\n\t\t$(DL_DIR)/$(call CT_FIRMWARE_FILE,QCA4019) \\\n\t\t$(1)/lib/firmware/ath10k/QCA4019/hw1.0/firmware-5.bin\nendef\ndefine Package/ath10k-firmware-qca4019-ct-full-htt/install\n\t$(INSTALL_DIR) $(1)/lib/firmware/ath10k/QCA4019/hw1.0\n\t$(INSTALL_DATA) \\\n\t\t$(DL_DIR)/$(call CT_FIRMWARE_FILE_FULL_HTT,QCA4019) \\\n\t\t$(1)/lib/firmware/ath10k/QCA4019/hw1.0/ct-firmware-5.bin\nendef\ndefine Package/ath10k-firmware-qca4019-ct-htt/install\n\t$(INSTALL_DIR) $(1)/lib/firmware/ath10k/QCA4019/hw1.0\n\t$(INSTALL_DATA) \\\n\t\t$(DL_DIR)/$(call CT_FIRMWARE_FILE_HTT,QCA4019) \\\n\t\t$(1)/lib/firmware/ath10k/QCA4019/hw1.0/ct-firmware-5.bin\nendef\n\ndefine Package/ath10k-firmware-qca9888-ct/install\n\t$(INSTALL_DIR) $(1)/lib/firmware/ath10k/QCA9888/hw2.0\n\tln -s \\\n\t\t../../cal-pci-0000:01:00.0.bin \\\n\t\t$(1)/lib/firmware/ath10k/QCA9888/hw2.0/board.bin\n\t$(INSTALL_DATA) \\\n\t\t$(DL_DIR)/$(call CT_FIRMWARE_FILE,QCA9888) \\\n\t\t$(1)/lib/firmware/ath10k/QCA9888/hw2.0/firmware-5.bin\nendef\ndefine Package/ath10k-firmware-qca9888-ct-full-htt/install\n\t$(INSTALL_DIR) $(1)/lib/firmware/ath10k/QCA9888/hw2.0\n\tln -s \\\n\t\t../../cal-pci-0000:01:00.0.bin \\\n\t\t$(1)/lib/firmware/ath10k/QCA9888/hw2.0/board.bin\n\t$(INSTALL_DATA) \\\n\t\t$(DL_DIR)/$(call CT_FIRMWARE_FILE_FULL_HTT,QCA9888) \\\n\t\t$(1)/lib/firmware/ath10k/QCA9888/hw2.0/ct-firmware-5.bin\nendef\ndefine Package/ath10k-firmware-qca9888-ct-htt/install\n\t$(INSTALL_DIR) $(1)/lib/firmware/ath10k/QCA9888/hw2.0\n\tln -s \\\n\t\t../../cal-pci-0000:01:00.0.bin \\\n\t\t$(1)/lib/firmware/ath10k/QCA9888/hw2.0/board.bin\n\t$(INSTALL_DATA) \\\n\t\t$(DL_DIR)/$(call CT_FIRMWARE_FILE_HTT,QCA9888) \\\n\t\t$(1)/lib/firmware/ath10k/QCA9888/hw2.0/ct-firmware-5.bin\nendef\n\n\n$(eval $(call BuildPackage,ath10k-firmware-qca9887-ct))\n$(eval $(call BuildPackage,ath10k-firmware-qca9887-ct-full-htt))\n$(eval $(call BuildPackage,ath10k-firmware-qca988x-ct))\n$(eval $(call BuildPackage,ath10k-firmware-qca988x-ct-full-htt))\n$(eval $(call BuildPackage,ath10k-firmware-qca99x0-ct))\n$(eval $(call BuildPackage,ath10k-firmware-qca99x0-ct-full-htt))\n$(eval $(call BuildPackage,ath10k-firmware-qca99x0-ct-htt))\n$(eval $(call BuildPackage,ath10k-firmware-qca9984-ct))\n$(eval $(call BuildPackage,ath10k-firmware-qca9984-ct-full-htt))\n$(eval $(call BuildPackage,ath10k-firmware-qca9984-ct-htt))\n$(eval $(call BuildPackage,ath10k-firmware-qca4019-ct))\n$(eval $(call BuildPackage,ath10k-firmware-qca4019-ct-full-htt))\n$(eval $(call BuildPackage,ath10k-firmware-qca4019-ct-htt))\n$(eval $(call BuildPackage,ath10k-firmware-qca9888-ct))\n$(eval $(call BuildPackage,ath10k-firmware-qca9888-ct-full-htt))\n$(eval $(call BuildPackage,ath10k-firmware-qca9888-ct-htt))\n"
  },
  {
    "path": "package/firmware/b43legacy-firmware/Makefile",
    "content": "#\n# Copyright (C) 2016 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=b43legacy-firmware\nPKG_VERSION:=3.130.20.0\nPKG_RELEASE:=1\n\nPKG_SOURCE:=wl_apsta-$(PKG_VERSION).o\nPKG_SOURCE_URL:=@OPENWRT\nPKG_HASH:=7dba610b1d96dd14e901bcbce14cd6ecd1b1ac6f5c0035b0d6b6dc46a7c3ef90\n\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine Package/b43legacy-firmware\n  SECTION:=firmware\n  CATEGORY:=Firmware\n  URL:=$(PKG_SOURCE_URL)\n  TITLE:=Broadcom bcm43xx b43legacy firmware\nendef\n\ndefine Package/b43legacy-firmware/config\n  if PACKAGE_b43legacy-firmware\n\n\tconfig B43LEGACY_FW_SQUASH\n\t\tbool \"Remove unnecessary firmware files\"\n\t\tdefault y\n\t\thelp\n\t\t  This options allows you to remove unnecessary b43legacy firmware files\n\t\t  from the final rootfs image. This can reduce the rootfs size by\n\t\t  up to 50k.\n\n\t\t  If unsure, say Y.\n\n\tconfig B43LEGACY_FW_SQUASH_COREREVS\n\t\tstring \"Core revisions to include\"\n\t\tdepends on B43LEGACY_FW_SQUASH\n\t\tdefault \"1,2,3,4\"\n\t\thelp\n\t\t  This is a comma separated list of core revision numbers.\n\n\t\t  Example (keep files for rev4 only):\n\t\t    4\n\n\t\t  Example (keep files for rev2 and rev4):\n\t\t    2,4\n\n  endif\nendef\n\ndefine Build/Prepare\n\tmkdir -p $(PKG_BUILD_DIR)\nendef\n\ndefine Build/Compile\n\nendef\n\ndefine Package/b43legacy-firmware/install\n\t$(INSTALL_DIR) $(1)/lib/firmware\n\tb43-fwcutter --unsupported -w $(1)/lib/firmware/ $(DL_DIR)/$(PKG_SOURCE)\n  ifneq ($(CONFIG_B43LEGACY_FW_SQUASH),)\n\tb43-fwsquash.py \"G\" \"$(CONFIG_B43LEGACY_FW_SQUASH_COREREVS)\" \"$(1)/lib/firmware/b43legacy\"\n  endif\nendef\n\n$(eval $(call BuildPackage,b43legacy-firmware))\n"
  },
  {
    "path": "package/firmware/cypress-firmware/Makefile",
    "content": "#\n# Copyright (C) 2019-2020 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=cypress-firmware\nPKG_VERSION:=5.4.18-2021_0812\nPKG_RELEASE:=1\n\nPKG_SOURCE_PROTO:=git\nPKG_SOURCE_URL:=https://github.com/Infineon/ifx-linux-firmware/\nPKG_MIRROR_HASH:=ac882b482dd401b53cdecc6004cd2bd3d65e888c19206dcf10931a28033ada4d\nPKG_SOURCE_VERSION:=release-v$(PKG_VERSION)\n\nPKG_MAINTAINER:=Álvaro Fernández Rojas <noltari@gmail.com>\nPKG_LICENSE_FILES:=LICENCE\n\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine Package/cypress-firmware-default\n  SECTION:=firmware\n  CATEGORY:=Firmware\n  URL:=https://community.infineon.com/\nendef\n\ndefine Build/Compile\n\ttrue\nendef\n\n# Cypress 43012 SDIO Firmware\ndefine Package/cypress-firmware-43012-sdio\n  $(Package/cypress-firmware-default)\n  TITLE:=CYW43012 FullMac SDIO firmware\nendef\n\ndefine Package/cypress-firmware-43012-sdio/install\n\t$(INSTALL_DIR) $(1)/lib/firmware/brcm\n\t$(INSTALL_DATA) \\\n\t\t$(PKG_BUILD_DIR)/firmware/cyfmac43012-sdio.bin \\\n\t\t$(1)/lib/firmware/brcm/brcmfmac43012-sdio.bin\n\t$(INSTALL_DATA) \\\n\t\t$(PKG_BUILD_DIR)/firmware/cyfmac43012-sdio.clm_blob \\\n\t\t$(1)/lib/firmware/brcm/brcmfmac43012-sdio.clm_blob\nendef\n\n$(eval $(call BuildPackage,cypress-firmware-43012-sdio))\n\n# Cypress 43340 SDIO Firmware\ndefine Package/cypress-firmware-43340-sdio\n  $(Package/cypress-firmware-default)\n  TITLE:=CYW43340 FullMac SDIO firmware\nendef\n\ndefine Package/cypress-firmware-43340-sdio/install\n\t$(INSTALL_DIR) $(1)/lib/firmware/brcm\n\t$(INSTALL_DATA) \\\n\t\t$(PKG_BUILD_DIR)/firmware/cyfmac43340-sdio.bin \\\n\t\t$(1)/lib/firmware/brcm/brcmfmac43340-sdio.bin\nendef\n\n$(eval $(call BuildPackage,cypress-firmware-43340-sdio))\n\n# Cypress 43362 SDIO Firmware\ndefine Package/cypress-firmware-43362-sdio\n  $(Package/cypress-firmware-default)\n  TITLE:=CYW43362 FullMac SDIO firmware\n  PROVIDES:=brcmfmac-firmware-43362-sdio\n  CONFLICTS:=brcmfmac-firmware-43362-sdio\nendef\n\ndefine Package/cypress-firmware-43362-sdio/install\n\t$(INSTALL_DIR) $(1)/lib/firmware/brcm\n\t$(INSTALL_DATA) \\\n\t\t$(PKG_BUILD_DIR)/firmware/cyfmac43362-sdio.bin \\\n\t\t$(1)/lib/firmware/brcm/brcmfmac43362-sdio.bin\nendef\n\n$(eval $(call BuildPackage,cypress-firmware-43362-sdio))\n\n# Cypress 4339 SDIO Firmware\ndefine Package/cypress-firmware-4339-sdio\n  $(Package/cypress-firmware-default)\n  TITLE:=CYW4339 FullMac SDIO firmware\nendef\n\ndefine Package/cypress-firmware-4339-sdio/install\n\t$(INSTALL_DIR) $(1)/lib/firmware/brcm\n\t$(INSTALL_DATA) \\\n\t\t$(PKG_BUILD_DIR)/firmware/cyfmac4339-sdio.bin \\\n\t\t$(1)/lib/firmware/brcm/brcmfmac4339-sdio.bin\nendef\n\n$(eval $(call BuildPackage,cypress-firmware-4339-sdio))\n\n# Cypress 43430 SDIO Firmware\ndefine Package/cypress-firmware-43430-sdio\n  $(Package/cypress-firmware-default)\n  TITLE:=CYW43430 FullMac SDIO firmware\n  PROVIDES:=brcmfmac-firmware-43430-sdio\n  CONFLICTS:=brcmfmac-firmware-43430-sdio\nendef\n\ndefine Package/cypress-firmware-43430-sdio/install\n\t$(INSTALL_DIR) $(1)/lib/firmware/brcm\n\t$(INSTALL_DATA) \\\n\t\t$(PKG_BUILD_DIR)/firmware/cyfmac43430-sdio.bin \\\n\t\t$(1)/lib/firmware/brcm/brcmfmac43430-sdio.bin\n\t$(INSTALL_DATA) \\\n\t\t$(PKG_BUILD_DIR)/firmware/cyfmac43430-sdio.clm_blob \\\n\t\t$(1)/lib/firmware/brcm/brcmfmac43430-sdio.clm_blob\nendef\n\n$(eval $(call BuildPackage,cypress-firmware-43430-sdio))\n\n# Cypress 43455 SDIO Firmware\ndefine Package/cypress-firmware-43455-sdio\n  $(Package/cypress-firmware-default)\n  TITLE:=CYW43455 FullMac SDIO firmware\n  PROVIDES:=brcmfmac-firmware-43455-sdio\n  CONFLICTS:=brcmfmac-firmware-43455-sdio\nendef\n\ndefine Package/cypress-firmware-43455-sdio/install\n\t$(INSTALL_DIR) $(1)/lib/firmware/brcm\n\t$(INSTALL_DATA) \\\n\t\t$(PKG_BUILD_DIR)/firmware/cyfmac43455-sdio.bin \\\n\t\t$(1)/lib/firmware/brcm/brcmfmac43455-sdio.bin\n\t$(INSTALL_DATA) \\\n\t\t$(PKG_BUILD_DIR)/firmware/cyfmac43455-sdio.clm_blob \\\n\t\t$(1)/lib/firmware/brcm/brcmfmac43455-sdio.clm_blob\nendef\n\n$(eval $(call BuildPackage,cypress-firmware-43455-sdio))\n\n# Cypress 4354 SDIO Firmware\ndefine Package/cypress-firmware-4354-sdio\n  $(Package/cypress-firmware-default)\n  TITLE:=CYW4354 FullMac SDIO firmware\nendef\n\ndefine Package/cypress-firmware-4354-sdio/install\n\t$(INSTALL_DIR) $(1)/lib/firmware/brcm\n\t$(INSTALL_DATA) \\\n\t\t$(PKG_BUILD_DIR)/firmware/cyfmac4354-sdio.bin \\\n\t\t$(1)/lib/firmware/brcm/brcmfmac4354-sdio.bin\n\t$(INSTALL_DATA) \\\n\t\t$(PKG_BUILD_DIR)/firmware/cyfmac4354-sdio.clm_blob \\\n\t\t$(1)/lib/firmware/brcm/brcmfmac4354-sdio.clm_blob\nendef\n\n$(eval $(call BuildPackage,cypress-firmware-4354-sdio))\n\n# Cypress 4356 PCIe Firmware\ndefine Package/cypress-firmware-4356-pcie\n  $(Package/cypress-firmware-default)\n  TITLE:=CYW4356 FullMac PCIe firmware\nendef\n\ndefine Package/cypress-firmware-4356-pcie/install\n\t$(INSTALL_DIR) $(1)/lib/firmware/brcm\n\t$(INSTALL_DATA) \\\n\t\t$(PKG_BUILD_DIR)/firmware/cyfmac4356-pcie.bin \\\n\t\t$(1)/lib/firmware/brcm/brcmfmac4356-pcie.bin\n\t$(INSTALL_DATA) \\\n\t\t$(PKG_BUILD_DIR)/firmware/cyfmac4356-pcie.clm_blob \\\n\t\t$(1)/lib/firmware/brcm/brcmfmac4356-pcie.clm_blob\nendef\n\n$(eval $(call BuildPackage,cypress-firmware-4356-pcie))\n\n# Cypress 4356 SDIO Firmware\ndefine Package/cypress-firmware-4356-sdio\n  $(Package/cypress-firmware-default)\n  TITLE:=CYW4356 FullMac SDIO firmware\nendef\n\ndefine Package/cypress-firmware-4356-sdio/install\n\t$(INSTALL_DIR) $(1)/lib/firmware/brcm\n\t$(INSTALL_DATA) \\\n\t\t$(PKG_BUILD_DIR)/firmware/cyfmac4356-sdio.bin \\\n\t\t$(1)/lib/firmware/brcm/brcmfmac4356-sdio.bin\n\t$(INSTALL_DATA) \\\n\t\t$(PKG_BUILD_DIR)/firmware/cyfmac4356-sdio.clm_blob \\\n\t\t$(1)/lib/firmware/brcm/brcmfmac4356-sdio.clm_blob\nendef\n\n$(eval $(call BuildPackage,cypress-firmware-4356-sdio))\n\n# Cypress 43570 PCIe Firmware\ndefine Package/cypress-firmware-43570-pcie\n  $(Package/cypress-firmware-default)\n  TITLE:=CYW43570 FullMac PCIe firmware\nendef\n\ndefine Package/cypress-firmware-43570-pcie/install\n\t$(INSTALL_DIR) $(1)/lib/firmware/brcm\n\t$(INSTALL_DATA) \\\n\t\t$(PKG_BUILD_DIR)/firmware/cyfmac43570-pcie.bin \\\n\t\t$(1)/lib/firmware/brcm/brcmfmac43570-pcie.bin\n\t$(INSTALL_DATA) \\\n\t\t$(PKG_BUILD_DIR)/firmware/cyfmac43570-pcie.clm_blob \\\n\t\t$(1)/lib/firmware/brcm/brcmfmac43570-pcie.clm_blob\nendef\n\n$(eval $(call BuildPackage,cypress-firmware-43570-pcie))\n\n# Cypress 4373 SDIO Firmware\ndefine Package/cypress-firmware-4373-sdio\n  $(Package/cypress-firmware-default)\n  TITLE:=CYW4373 FullMac SDIO firmware\nendef\n\ndefine Package/cypress-firmware-4373-sdio/install\n\t$(INSTALL_DIR) $(1)/lib/firmware/brcm\n\t$(INSTALL_DATA) \\\n\t\t$(PKG_BUILD_DIR)/firmware/cyfmac4373-sdio.bin \\\n\t\t$(1)/lib/firmware/brcm/brcmfmac4373-sdio.bin\n\t$(INSTALL_DATA) \\\n\t\t$(PKG_BUILD_DIR)/firmware/cyfmac4373-sdio.clm_blob \\\n\t\t$(1)/lib/firmware/brcm/brcmfmac4373-sdio.clm_blob\nendef\n\n$(eval $(call BuildPackage,cypress-firmware-4373-sdio))\n\n# Cypress 4373 USB Firmware\ndefine Package/cypress-firmware-4373-usb\n  $(Package/cypress-firmware-default)\n  TITLE:=CYW4373 FullMac USB firmware\nendef\n\ndefine Package/cypress-firmware-4373-usb/install\n\t$(INSTALL_DIR) $(1)/lib/firmware/brcm\n\t$(INSTALL_DATA) \\\n\t\t$(PKG_BUILD_DIR)/firmware/cyfmac4373-usb.bin \\\n\t\t$(1)/lib/firmware/brcm/brcmfmac4373-usb.bin\n\t$(INSTALL_DATA) \\\n\t\t$(PKG_BUILD_DIR)/firmware/cyfmac4373.clm_blob \\\n\t\t$(1)/lib/firmware/brcm/brcmfmac4373.clm_blob\nendef\n\n$(eval $(call BuildPackage,cypress-firmware-4373-usb))\n\n# Cypress 54591 PCIe Firmware\ndefine Package/cypress-firmware-54591-pcie\n  $(Package/cypress-firmware-default)\n  TITLE:=CYW54591 FullMac PCIe firmware\nendef\n\ndefine Package/cypress-firmware-54591-pcie/install\n\t$(INSTALL_DIR) $(1)/lib/firmware/brcm\n\t$(INSTALL_DATA) \\\n\t\t$(PKG_BUILD_DIR)/firmware/cyfmac54591-pcie.bin \\\n\t\t$(1)/lib/firmware/brcm/brcmfmac54591-pcie.bin\n\t$(INSTALL_DATA) \\\n\t\t$(PKG_BUILD_DIR)/firmware/cyfmac54591-pcie.clm_blob \\\n\t\t$(1)/lib/firmware/brcm/brcmfmac54591-pcie.clm_blob\nendef\n\n$(eval $(call BuildPackage,cypress-firmware-54591-pcie))\n"
  },
  {
    "path": "package/firmware/cypress-nvram/Makefile",
    "content": "#\n# Copyright (C) 2019 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=cypress-nvram\nPKG_SOURCE_DATE:=2019-09-03\nPKG_SOURCE_VERSION:=e7b78df22f2a0c5f56abb7b5880661611de35e5f\nPKG_MIRROR_HASH:=1cb20a749696852be0a512d51961365dd9c031362af0af1a2b9f5a3fb894885f\nPKG_RELEASE:=2\n\nPKG_SOURCE_PROTO:=git\nPKG_SOURCE_URL:=https://github.com/openwrt/cypress-nvram.git\n\nPKG_MAINTAINER:=Álvaro Fernández Rojas <noltari@gmail.com>\n\nPKG_FLAGS:=nonshared\n\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine Package/cypress-nvram-default\n  SECTION:=firmware\n  CATEGORY:=Firmware\n  URL:=https://community.cypress.com/community/linux\nendef\n\ndefine Build/Compile\n\ttrue\nendef\n\n# Cypress 43430 SDIO Raspberry Pi 3B NVRAM\ndefine Package/cypress-nvram-43430-sdio-rpi-3b\n  $(Package/cypress-nvram-default)\n  TITLE:=CYW43430 NVRAM for Raspberry Pi 3B\n  DEPENDS:=@TARGET_bcm27xx\n  PROVIDES:=brcmfmac-firmware-43430-sdio-rpi-3b\n  CONFLICTS:=brcmfmac-firmware-43430-sdio-rpi-3b\nendef\n\ndefine Package/cypress-nvram-43430-sdio-rpi-3b/install\n\t$(INSTALL_DIR) $(1)/lib/firmware/brcm\n\t$(INSTALL_DATA) \\\n\t\t$(PKG_BUILD_DIR)/brcmfmac43430-sdio.raspberrypi,3-model-b.txt \\\n\t\t$(1)/lib/firmware/brcm/brcmfmac43430-sdio.raspberrypi,3-model-b.txt\nendef\n\n$(eval $(call BuildPackage,cypress-nvram-43430-sdio-rpi-3b))\n\n# Cypress 43430 SDIO Raspberry Pi Zero W NVRAM\ndefine Package/cypress-nvram-43430-sdio-rpi-zero-w\n  $(Package/cypress-nvram-default)\n  TITLE:=CYW43430 NVRAM for Raspberry Pi Zero W\n  DEPENDS:=@TARGET_bcm27xx\n  PROVIDES:=brcmfmac-firmware-43430-sdio-rpi-zero-w\n  CONFLICTS:=brcmfmac-firmware-43430-sdio-rpi-zero-w\nendef\n\ndefine Package/cypress-nvram-43430-sdio-rpi-zero-w/install\n\t$(INSTALL_DIR) $(1)/lib/firmware/brcm\n\t$(INSTALL_DATA) \\\n\t\t$(PKG_BUILD_DIR)/brcmfmac43430-sdio.raspberrypi,model-zero-w.txt \\\n\t\t$(1)/lib/firmware/brcm/brcmfmac43430-sdio.raspberrypi,model-zero-w.txt\nendef\n\n$(eval $(call BuildPackage,cypress-nvram-43430-sdio-rpi-zero-w))\n\n# Cypress 43455 SDIO Raspberry Pi 3B+ NVRAM\ndefine Package/cypress-nvram-43455-sdio-rpi-3b-plus\n  $(Package/cypress-nvram-default)\n  TITLE:=CYW43455 NVRAM for Raspberry Pi 3B+\n  DEPENDS:=@TARGET_bcm27xx\n  PROVIDES:=brcmfmac-firmware-43455-sdio-rpi-3b-plus\n  CONFLICTS:=brcmfmac-firmware-43455-sdio-rpi-3b-plus\nendef\n\ndefine Package/cypress-nvram-43455-sdio-rpi-3b-plus/install\n\t$(INSTALL_DIR) $(1)/lib/firmware/brcm\n\t$(INSTALL_DATA) \\\n\t\t$(PKG_BUILD_DIR)/brcmfmac43455-sdio.raspberrypi,3-model-b-plus.txt \\\n\t\t$(1)/lib/firmware/brcm/brcmfmac43455-sdio.raspberrypi,3-model-b-plus.txt\nendef\n\n$(eval $(call BuildPackage,cypress-nvram-43455-sdio-rpi-3b-plus))\n\n# Cypress 43455 SDIO Raspberry Pi 4B NVRAM\ndefine Package/cypress-nvram-43455-sdio-rpi-4b\n  $(Package/cypress-nvram-default)\n  TITLE:=CYW43455 NVRAM for Raspberry Pi 4B\n  DEPENDS:=@TARGET_bcm27xx\n  PROVIDES:=brcmfmac-firmware-43455-sdio-rpi-4b\n  CONFLICTS:=brcmfmac-firmware-43455-sdio-rpi-4b\nendef\n\ndefine Package/cypress-nvram-43455-sdio-rpi-4b/install\n\t$(INSTALL_DIR) $(1)/lib/firmware/brcm\n\t$(INSTALL_DATA) \\\n\t\t$(PKG_BUILD_DIR)/brcmfmac43455-sdio.raspberrypi,4-model-b.txt \\\n\t\t$(1)/lib/firmware/brcm/brcmfmac43455-sdio.raspberrypi,4-model-b.txt\n\t$(INSTALL_DATA) \\\n\t\t$(PKG_BUILD_DIR)/brcmfmac43455-sdio.raspberrypi,4-model-b.txt \\\n\t\t$(1)/lib/firmware/brcm/brcmfmac43455-sdio.raspberrypi,4-compute-module.txt\nendef\n\n$(eval $(call BuildPackage,cypress-nvram-43455-sdio-rpi-4b))\n"
  },
  {
    "path": "package/firmware/intel-microcode/Makefile",
    "content": "#\n# Copyright (C) 2018 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=intel-microcode\nPKG_VERSION:=20220207\nPKG_RELEASE:=1\n\nPKG_SOURCE:=intel-microcode_3.$(PKG_VERSION).1.tar.xz\nPKG_SOURCE_URL:=@DEBIAN/pool/non-free/i/intel-microcode/\nPKG_HASH:=42f2ab3c14bda745ec64008cde5c0f416f32f40e838a9df04cf5ddf5fc87498b\nPKG_BUILD_DIR:=$(BUILD_DIR)/intel-microcode-3.$(PKG_VERSION).1\n\nPKG_BUILD_DEPENDS:=iucode-tool/host\n\nifdef CONFIG_TARGET_x86_64\n\tMICROCODE:=\"intel-microcode-64\"\nelse\n\tMICROCODE:=\"intel-microcode\"\nendif\n\nPKG_FLAGS:=nonshared\n\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine Package/intel-microcode\n  SECTION:=firmware\n  CATEGORY:=Firmware\n  URL:=$(PKG_SOURCE_URL)\n  DEPENDS:=@TARGET_x86\n  TITLE:=Intel x86 CPU microcode\nendef\n\ndefine Build/Compile\n\tIUCODE_TOOL=$(STAGING_DIR)/../host/bin/iucode_tool $(MAKE) -C $(PKG_BUILD_DIR)\n\tmkdir $(PKG_BUILD_DIR)/intel-ucode-ipkg\n\t$(STAGING_DIR)/../host/bin/iucode_tool -q \\\n\t\t--write-firmware=$(PKG_BUILD_DIR)/intel-ucode-ipkg $(PKG_BUILD_DIR)/$(MICROCODE).bin\nendef\n\ndefine Package/intel-microcode/install\n\t$(INSTALL_DIR) $(1)/lib/firmware/intel-ucode\n\t$(INSTALL_DATA) $(PKG_BUILD_DIR)/intel-ucode-ipkg/* $(1)/lib/firmware/intel-ucode\nendef\n\n$(eval $(call BuildPackage,intel-microcode))\n"
  },
  {
    "path": "package/firmware/ipq-wifi/Makefile",
    "content": "include $(TOPDIR)/rules.mk\ninclude $(INCLUDE_DIR)/version.mk\n\nPKG_NAME:=ipq-wifi\nPKG_RELEASE:=1\nPKG_FLAGS:=nonshared\n\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine Build/Prepare\n\tmkdir -p $(PKG_BUILD_DIR)\nendef\n\ndefine Build/Compile\nendef\n\n# Use ath10k-bdencoder from https://github.com/qca/qca-swiss-army-knife.git\n# to generate the board-* files here.\n#\n# This is intended to be used on an interim basis until device-specific\n# board data for new devices is available through the upstream compilation\n#\n# Please send a mail with your device-specific board files upstream.\n# You can find instructions and examples on the linux-wireless wiki:\n# <https://wireless.wiki.kernel.org/en/users/drivers/ath10k/boardfiles>\n\nALLWIFIBOARDS:= \\\n\tdevolo_magic-2-wifi-next \\\n\tedgecore_ecw5410 \\\n\tedgecore_oap100 \\\n\tglinet_gl-ap1300 \\\n\tglinet_gl-b2200 \\\n\tglinet_gl-s1300 \\\n\tlinksys_ea8300 \\\n\tmikrotik_cap-ac \\\n\tmikrotik_hap-ac2 \\\n\tmikrotik_hap-ac3 \\\n\tmikrotik_sxtsq-5-ac \\\n\tp2w_r619ac \\\n\tqxwlan_e2600ac-c1 \\\n\tqxwlan_e2600ac-c2 \\\n\tteltonika_rutx\n\nALLWIFIPACKAGES:=$(foreach BOARD,$(ALLWIFIBOARDS),ipq-wifi-$(BOARD))\n\ndefine Package/ipq-wifi-default\n  SUBMENU:=ath10k Board-Specific Overrides\n  SECTION:=firmware\n  CATEGORY:=Firmware\n  DEPENDS:=@(TARGET_ipq40xx||TARGET_ipq806x)\n  TITLE:=Custom Board\nendef\n\ndefine ipq-wifi-install-one-to\n  $(INSTALL_DIR)  $(2)/lib/firmware/ath10k/$(3)/\n  $(INSTALL_DATA) $(1) $(2)/lib/firmware/ath10k/$(3)/board-2.bin\nendef\n\ndefine ipq-wifi-install-one\n  $(if $(filter $(suffix $(1)),.QCA4019 .qca4019),\\\n    $(call ipq-wifi-install-one-to,$(1),$(2),QCA4019/hw1.0),\\\n  $(if $(filter $(suffix $(1)),.QCA9888 .qca9888),\\\n    $(call ipq-wifi-install-one-to,$(1),$(2),QCA9888/hw2.0),\\\n  $(if $(filter $(suffix $(1)),.QCA9984 .qca9984),\\\n    $(call ipq-wifi-install-one-to,$(1),$(2),QCA9984/hw1.0),\\\n    $(error Unrecognized board-file suffix '$(suffix $(1))' for '$(1)')\\\n  )))\n\nendef\n# Blank line required at end of above define due to foreach context\n\ndefine generate-ipq-wifi-package\n  define Package/ipq-wifi-$(1)\n    $(call Package/ipq-wifi-default)\n    TITLE:=board-2.bin Overrides for $(2)\n    CONFLICTS:=$(PREV_BOARD)\n  endef\n\n  define Package/ipq-wifi-$(1)/description\nThe $(2) requires board-specific, reference (\"cal\") data\nthat is not yet present in the upstream wireless firmware distribution.\n\nThis package supplies board-2.bin file(s) that, in the interim,\noverwrite those supplied by the ath10k-firmware-* packages.\n\nThis is package is only necessary for the $(2).\n\nDo not install it for any other device!\n  endef\n\n  define Package/ipq-wifi-$(1)/install-overlay\n    $$$$(foreach IPQ_WIFI_BOARD_FILE,$$$$(wildcard board-$(1).*),\\\n      $$$$(call ipq-wifi-install-one,$$$$(IPQ_WIFI_BOARD_FILE),$$(1)))\n  endef\n\n  PREV_BOARD+=ipq-wifi-$(1)\nendef\n\n# Add board name to ALLWIFIBOARDS\n# Place files in this directory as board-<devicename>.<qca4019|qca9888|qca9984>\n# Add $(eval $(call generate-ipq-wifi-package,<devicename>,<display name>))\n\n$(eval $(call generate-ipq-wifi-package,devolo_magic-2-wifi-next,devolo Magic 2 WiFi next))\n$(eval $(call generate-ipq-wifi-package,edgecore_ecw5410,Edgecore ECW5410))\n$(eval $(call generate-ipq-wifi-package,edgecore_oap100,Edgecore OAP100))\n$(eval $(call generate-ipq-wifi-package,glinet_gl-ap1300,GL.iNet GL-AP1300))\n$(eval $(call generate-ipq-wifi-package,glinet_gl-b2200,GL.iNet GL-B2200))\n$(eval $(call generate-ipq-wifi-package,glinet_gl-s1300,GL.iNet GL-S1300))\n$(eval $(call generate-ipq-wifi-package,linksys_ea8300,Linksys EA8300))\n$(eval $(call generate-ipq-wifi-package,mikrotik_cap-ac,Mikrotik cAP ac))\n$(eval $(call generate-ipq-wifi-package,mikrotik_hap-ac2,Mikrotik hAP ac2))\n$(eval $(call generate-ipq-wifi-package,mikrotik_hap-ac3,Mikrotik hAP ac3))\n$(eval $(call generate-ipq-wifi-package,mikrotik_sxtsq-5-ac,MikroTik SXTsq 5 ac))\n$(eval $(call generate-ipq-wifi-package,p2w_r619ac,P&W R619AC))\n$(eval $(call generate-ipq-wifi-package,qxwlan_e2600ac-c1,Qxwlan E2600AC C1))\n$(eval $(call generate-ipq-wifi-package,qxwlan_e2600ac-c2,Qxwlan E2600AC C2))\n$(eval $(call generate-ipq-wifi-package,teltonika_rutx,Teltonika RUTX))\n\n$(foreach PACKAGE,$(ALLWIFIPACKAGES),$(eval $(call BuildPackage,$(PACKAGE))))\n"
  },
  {
    "path": "package/firmware/lantiq/dsl-vrx200-firmware-xdsl/Makefile",
    "content": "# Copyright (C) 2015 OpenWrt.org\n# Copyright (C) 2015-2016 Lantiq Beteiligungs GmbH & Co KG.\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=dsl_vr9_firmware_xdsl\nPKG_VERSION:=05.08.01.08.01.06_05.08.00.0B.01.01_osc\nPKG_RELEASE:=1\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz\nPKG_SOURCE_URL:=@OPENWRT\nPKG_HASH:=44cd94130571fe42dfa8f0f9d44597d104e9e77962617fe38646b7a0b4184a2b\nPKG_BUILD_DEPENDS:=bsdiff/host\n\nPKG_FLAGS:=nonshared\n\ninclude $(INCLUDE_DIR)/package.mk\n\nPKG_B_NAME:=dsl_vr9_firmware_xdsl\nPKG_B_VERSION:=05.07.09.09.00.06_05.07.04.04.00.02_osc\nPKG_B_SOURCE:=$(PKG_B_NAME)-$(PKG_B_VERSION).tar.gz\n\nANNEX_A_VER:=581816_580B11\nANNEX_B_VER:=579906_574402\n\ndefine Download/dsl_vr9_firmware_xdsl_b\n  FILE:=$(PKG_B_SOURCE)\n  URL:=$(PKG_SOURCE_URL)\n  HASH:=275c55e870205a5a75510d3ef3d3fb6b60010effebf4b2d1fbc72ffd46e855c0\nendef\n$(eval $(call Download,dsl_vr9_firmware_xdsl_b))\n\n\ndefine Package/dsl-vrx200-firmware-xdsl-a\n  SECTION:=firmware\n  CATEGORY:=Firmware\n  TITLE:=VRX200 / VR9 CPE xDSL Annex A firmware\n  URL:=http://www.lantiq.com/\n  DEPENDS:=@TARGET_lantiq_xrx200\nendef\n\ndefine Package/dsl-vrx200-firmware-xdsl-a/description\n\tVRX200 / VR9 CPE VDSL and ADSL Annex A firmware\nendef\n\ndefine Package/dsl-vrx200-firmware-xdsl-b\n  SECTION:=firmware\n  CATEGORY:=Firmware\n  TITLE:=VRX200 / VR9 CPE xDSL Annex B firmware\n  URL:=http://www.lantiq.com/\n  DEPENDS:=@TARGET_lantiq_xrx200\nendef\n\ndefine Package/dsl-vrx200-firmware-xdsl-b/description\n\tVRX200 / VR9 CPE VDSL and ADSL Annex B firmware\nendef\n\ndefine Package/dsl-vrx200-firmware-xdsl-a-patch\n  SECTION:=firmware\n  CATEGORY:=Firmware\n  TITLE:=VRX200 / VR9 CPE xDSL Annex B to Annex A firmware patch\n  URL:=http://www.lantiq.com/\n  DEPENDS:=@TARGET_lantiq_xrx200 +dsl-vrx200-firmware-xdsl-b +bspatch\nendef\n\ndefine Package/dsl-vrx200-firmware-xdsl-a-patch/description\n\tPatch which between the Annex A and Annex B firmware to create the Annex A firmware.\nendef\n\ndefine Package/dsl-vrx200-firmware-xdsl-b-patch\n  SECTION:=firmware\n  CATEGORY:=Firmware\n  TITLE:=VRX200 / VR9 CPE xDSL Annex A to Annex B firmware patch\n  URL:=http://www.lantiq.com/\n  DEPENDS:=@TARGET_lantiq_xrx200 +dsl-vrx200-firmware-xdsl-a +bspatch\nendef\n\ndefine Package/dsl-vrx200-firmware-xdsl-b-patch/description\n\tPatch which between the Annex A and Annex B firmware to create the Annex B firmware.\nendef\n\ndefine Build/Prepare\n\trm -rf $(PKG_BUILD_DIR)\n\tmkdir -p $(PKG_BUILD_DIR)\n\t$(TAR) -C $(PKG_BUILD_DIR) -xzf $(DL_DIR)/$(PKG_SOURCE)\n\t$(TAR) -C $(PKG_BUILD_DIR) -xzf $(DL_DIR)/$(PKG_B_SOURCE)\nendef\n\ndefine Build/Compile\n\tbsdiff \\\n\t\t$(PKG_BUILD_DIR)/xcpe_$(ANNEX_A_VER).bin \\\n\t\t$(PKG_BUILD_DIR)/xcpe_$(ANNEX_B_VER).bin \\\n\t\t$(PKG_BUILD_DIR)/xcpe_$(ANNEX_A_VER)_to_$(ANNEX_B_VER).bspatch\n\tbsdiff \\\n\t\t$(PKG_BUILD_DIR)/xcpe_$(ANNEX_B_VER).bin \\\n\t\t$(PKG_BUILD_DIR)/xcpe_$(ANNEX_A_VER).bin \\\n\t\t$(PKG_BUILD_DIR)/xcpe_$(ANNEX_B_VER)_to_$(ANNEX_A_VER).bspatch\nendef\n\ndefine Package/dsl-vrx200-firmware-xdsl-a/install\n\t$(INSTALL_DIR) $(1)/lib/firmware/\n\t$(INSTALL_DATA) $(PKG_BUILD_DIR)/LICENSE $(1)/lib/firmware/xcpe_$(ANNEX_A_VER).LICENSE\n\t$(INSTALL_DATA) $(PKG_BUILD_DIR)/xcpe_$(ANNEX_A_VER).bin $(1)/lib/firmware/\n\tln -s xcpe_$(ANNEX_A_VER).bin $(1)/lib/firmware/lantiq-vrx200-a.bin\nendef\n\ndefine Package/dsl-vrx200-firmware-xdsl-b/install\n\t$(INSTALL_DIR) $(1)/lib/firmware/\n\t$(INSTALL_DATA) $(PKG_BUILD_DIR)/LICENSE $(1)/lib/firmware/xcpe_$(ANNEX_B_VER).LICENSE\n\t$(INSTALL_DATA) $(PKG_BUILD_DIR)/xcpe_$(ANNEX_B_VER).bin $(1)/lib/firmware/\n\tln -s xcpe_$(ANNEX_B_VER).bin $(1)/lib/firmware/lantiq-vrx200-b.bin\nendef\n\ndefine Package/dsl-vrx200-firmware-xdsl-a-patch/install\n\t$(INSTALL_DIR) $(1)/lib/firmware/\n\t$(INSTALL_DATA) $(PKG_BUILD_DIR)/xcpe_$(ANNEX_B_VER)_to_$(ANNEX_A_VER).bspatch $(1)/lib/firmware/\n\tln -s xcpe_$(ANNEX_B_VER)_to_$(ANNEX_A_VER).bspatch $(1)/lib/firmware/lantiq-vrx200-b-to-a.bspatch\nendef\n\ndefine Package/dsl-vrx200-firmware-xdsl-b-patch/install\n\t$(INSTALL_DIR) $(1)/lib/firmware/\n\t$(INSTALL_DATA) $(PKG_BUILD_DIR)/xcpe_$(ANNEX_A_VER)_to_$(ANNEX_B_VER).bspatch $(1)/lib/firmware/\n\tln -s xcpe_$(ANNEX_A_VER)_to_$(ANNEX_B_VER).bspatch $(1)/lib/firmware/lantiq-vrx200-a-to-b.bspatch\nendef\n\n$(eval $(call BuildPackage,dsl-vrx200-firmware-xdsl-a))\n$(eval $(call BuildPackage,dsl-vrx200-firmware-xdsl-b))\n$(eval $(call BuildPackage,dsl-vrx200-firmware-xdsl-a-patch))\n$(eval $(call BuildPackage,dsl-vrx200-firmware-xdsl-b-patch))\n"
  },
  {
    "path": "package/firmware/layerscape/fman-ucode/Makefile",
    "content": "#\n# Copyright (C) 2016 Jiang Yutang <jiangyutang1978@gmail.com>\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=fman-ucode\nPKG_VERSION:=21.08\nPKG_RELEASE:=$(AUTORELEASE)\n\nPKG_SOURCE_PROTO:=git\nPKG_SOURCE_URL:=https://github.com/NXP/qoriq-fm-ucode.git\nPKG_SOURCE_VERSION:=LSDK-21.08\nPKG_MIRROR_HASH:=dc905ebe71cde24e9ebbe10a7b1f08cd2ecf142e39fe1535aa5fe3f349b031b9\n\nPKG_FLAGS:=nonshared\n\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine Package/layerscape-fman\n  SECTION:=firmware\n  CATEGORY:=Firmware\n  TITLE:=NXP FMan ucode\n  DEPENDS:=@TARGET_layerscape\nendef\n\ndefine Build/Compile\nendef\n\ndefine Build/InstallDev\n\t$(INSTALL_DIR) $(STAGING_DIR_IMAGE)\n\t$(CP) $(PKG_BUILD_DIR)/fsl_fman_ucode_ls1043_r1.1_106_4_18.bin \\\n\t\t$(STAGING_DIR_IMAGE)/fsl_ls1043a-rdb-fman.bin\n\t$(CP) $(PKG_BUILD_DIR)/fsl_fman_ucode_ls1046_r1.0_106_4_18.bin \\\n\t\t$(STAGING_DIR_IMAGE)/fsl_ls1046a-rdb-fman.bin\nendef\n\n$(eval $(call BuildPackage,layerscape-fman))\n"
  },
  {
    "path": "package/firmware/layerscape/ls-ddr-phy/Makefile",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n#\n# Copyright 2020 NXP\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=ls-ddr-phy\nPKG_VERSION:=21.08\nPKG_RELEASE:=$(AUTORELEASE)\n\nPKG_SOURCE_PROTO:=git\nPKG_SOURCE_URL:=https://github.com/NXP/ddr-phy-binary.git\nPKG_SOURCE_VERSION:=LSDK-21.08\nPKG_MIRROR_HASH:=6ad8bba23a70ed50716c56093a4ee7eef3153f8c3b7446c4520412c83799bb08\nPKG_BUILD_DEPENDS:=tfa-layerscape/host\n\nPKG_LICENSE:=EULA\nPKG_LICENSE_FILES:=NXP-Binary-EULA.txt\n\nPKG_FLAGS:=nonshared\n\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine Package/layerscape-ddr-phy\n  SECTION:=firmware\n  CATEGORY:=Firmware\n  TITLE:=NXP Layerscape DDR PHY firmware\n  DEPENDS:=@TARGET_layerscape\nendef\n\ndefine Build/Compile\n\tcd $(PKG_BUILD_DIR)/lx2160a/ && \\\n\tfiptool-layerscape create \\\n\t\t--ddr-immem-udimm-1d ddr4_pmu_train_imem.bin \\\n\t\t--ddr-immem-udimm-2d ddr4_2d_pmu_train_imem.bin \\\n\t\t--ddr-dmmem-udimm-1d ddr4_pmu_train_dmem.bin \\\n\t\t--ddr-dmmem-udimm-2d ddr4_2d_pmu_train_dmem.bin \\\n\t\t--ddr-immem-rdimm-1d ddr4_rdimm_pmu_train_imem.bin \\\n\t\t--ddr-immem-rdimm-2d ddr4_rdimm2d_pmu_train_imem.bin \\\n\t\t--ddr-dmmem-rdimm-1d ddr4_rdimm_pmu_train_dmem.bin \\\n\t\t--ddr-dmmem-rdimm-2d ddr4_rdimm2d_pmu_train_dmem.bin \\\n\t\tfip_ddr_all.bin\nendef\n\ndefine Build/InstallDev\n\t$(INSTALL_DIR) $(STAGING_DIR_IMAGE)\n\t$(CP) $(PKG_BUILD_DIR)/lx2160a/fip_ddr_all.bin \\\n\t\t$(STAGING_DIR_IMAGE)/fsl_lx2160a-rdb-fip_ddr_all.bin\nendef\n\n$(eval $(call BuildPackage,layerscape-ddr-phy))\n"
  },
  {
    "path": "package/firmware/layerscape/ls-dpl/Makefile",
    "content": "#\n# Copyright 2017 NXP\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=ls-dpl\nPKG_VERSION:=21.08\nPKG_RELEASE:=$(AUTORELEASE)\n\nPKG_SOURCE_PROTO:=git\nPKG_SOURCE_URL:=https://source.codeaurora.org/external/qoriq/qoriq-components/mc-utils\nPKG_SOURCE_VERSION:=LSDK-21.08\nPKG_MIRROR_HASH:=56ea7db52c1bee43c2823cff0cabc64d76b24296dfa347c9a95bc4a9542d4ed8\n\nPKG_FLAGS:=nonshared\n\ninclude $(INCLUDE_DIR)/package.mk\ninclude $(INCLUDE_DIR)/kernel.mk\n\ndefine Package/layerscape-dpl\n  SECTION:=firmware\n  CATEGORY:=Firmware\n  TITLE:=NXP DPL firmware\n  DEPENDS:=@TARGET_layerscape\nendef\n\nMAKE_PATH:=config\nMAKE_VARS+= \\\n\tPATH=$(LINUX_DIR)/scripts/dtc:$(PATH)\n\ndefine Build/InstallDev\n\t$(INSTALL_DIR) $(STAGING_DIR_IMAGE)\n\t$(CP) $(PKG_BUILD_DIR)/config/ls1088a/LS1088A-RDB/dpl-eth.0x1D_0x0D.dtb \\\n\t\t$(STAGING_DIR_IMAGE)/fsl_ls1088a-rdb-dpl.dtb\n\t$(CP) $(PKG_BUILD_DIR)/config/ls1088a/LS1088A-RDB/dpc.0x1D-0x0D.dtb \\\n\t\t$(STAGING_DIR_IMAGE)/fsl_ls1088a-rdb-dpc.dtb\n\t$(CP) $(PKG_BUILD_DIR)/config/ls2088a/LS2088A-RDB/dpl-eth.0x2A_0x41.dtb \\\n\t\t$(STAGING_DIR_IMAGE)/fsl_ls2088a-rdb-dpl.dtb\n\t$(CP) $(PKG_BUILD_DIR)/config/ls2088a/LS2088A-RDB/dpc.0x2A_0x41.dtb \\\n\t\t$(STAGING_DIR_IMAGE)/fsl_ls2088a-rdb-dpc.dtb\n\t$(CP) $(PKG_BUILD_DIR)/config/lx2160a/LX2160A-RDB/dpl-eth.19.dtb \\\n\t\t$(STAGING_DIR_IMAGE)/fsl_lx2160a-rdb-dpl.dtb\n\t$(CP) $(PKG_BUILD_DIR)/config/lx2160a/LX2160A-RDB/dpc-usxgmii.dtb \\\n\t\t$(STAGING_DIR_IMAGE)/fsl_lx2160a-rdb-dpc.dtb\nendef\n\n$(eval $(call BuildPackage,layerscape-dpl))\n"
  },
  {
    "path": "package/firmware/layerscape/ls-mc/Makefile",
    "content": "#\n# Copyright 2017 NXP\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=ls-mc\nPKG_VERSION:=21.08\nPKG_RELEASE:=$(AUTORELEASE)\n\nPKG_SOURCE_PROTO:=git\nPKG_SOURCE_URL:=https://github.com/NXP/qoriq-mc-binary.git\nPKG_SOURCE_VERSION:=LSDK-21.08\nPKG_MIRROR_HASH:=a8b2398f7958bfc3d45b239d33e0ecd27bd46e8f34693d545590a870be22ca2b\n\nPKG_FLAGS:=nonshared\n\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine Package/layerscape-mc\n  SECTION:=firmware\n  CATEGORY:=Firmware\n  TITLE:=NXP MC firmware\n  DEPENDS:=@TARGET_layerscape\nendef\n\ndefine Build/Compile\nendef\n\ndefine Build/InstallDev\n\t$(INSTALL_DIR) $(STAGING_DIR_IMAGE)\n\t$(CP) $(PKG_BUILD_DIR)/ls1088a/mc_ls1088a_10.28.1.itb \\\n\t\t$(STAGING_DIR_IMAGE)/fsl_ls1088a-rdb-mc.itb\n\t$(CP) $(PKG_BUILD_DIR)/ls2088a/mc_ls2088a_10.28.1.itb \\\n\t\t$(STAGING_DIR_IMAGE)/fsl_ls2088a-rdb-mc.itb\n\t$(CP) $(PKG_BUILD_DIR)/lx216xa/mc_lx2160a_10.28.1.itb \\\n\t\t$(STAGING_DIR_IMAGE)/fsl_lx2160a-rdb-mc.itb\nendef\n\n$(eval $(call BuildPackage,layerscape-mc))\n"
  },
  {
    "path": "package/firmware/layerscape/ls-rcw/Makefile",
    "content": "#\n# Copyright (C) 2016 Jiang Yutang <jiangyutang1978@gmail.com>\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=ls-rcw\nPKG_VERSION:=21.08\nPKG_RELEASE:=$(AUTORELEASE)\n\nPKG_SOURCE_PROTO:=git\nPKG_SOURCE_URL:=https://source.codeaurora.org/external/qoriq/qoriq-components/rcw\nPKG_SOURCE_VERSION:=LSDK-21.08\nPKG_MIRROR_HASH:=c0202d07223bb5ab43d0c0145c0d83e2b8c34c559bba0ec3c2c2aa562623f546\n\nPKG_FLAGS:=nonshared\n\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine Package/layerscape-rcw\n  SECTION:=firmware\n  CATEGORY:=Firmware\n  TITLE:=NXP Layerscape RCW binaries\n  DEPENDS:=@TARGET_layerscape\nendef\n\nBOARDS := \\\n  ls1012a-rdb \\\n  ls1012a-frdm \\\n  ls1012a-frwy-sdboot \\\n  ls1043a-rdb \\\n  ls1043a-rdb-sdboot \\\n  ls1046a-frwy \\\n  ls1046a-frwy-sdboot \\\n  ls1046a-rdb \\\n  ls1046a-rdb-sdboot \\\n  ls1088a-rdb \\\n  ls1088a-rdb-sdboot \\\n  ls2088a-rdb \\\n  lx2160a-rdb \\\n  lx2160a-rdb-sdboot \\\n  ls1021a-twr\n\nRCW_ls1012a-rdb         :=ls1012ardb/R_SPNH_3508/rcw_1000_default.bin\nRCW_ls1012a-frdm        :=ls1012afrdm/N_SSNP_3305/rcw_800.bin\nRCW_ls1012a-frwy-sdboot :=ls1012afrwy/N_SSNP_3305/rcw_1000_default.bin\nRCW_ls1043a-rdb         :=ls1043ardb/RR_FQPP_1455/rcw_1600.bin\nRCW_ls1043a-rdb-sdboot  :=ls1043ardb/RR_FQPP_1455/rcw_1600_sdboot.bin\nRCW_ls1046a-frwy        :=ls1046afrwy/NN_NNQNNPNP_3040_0506/rcw_1600_qspiboot.bin\nRCW_ls1046a-frwy-sdboot :=ls1046afrwy/NN_NNQNNPNP_3040_0506/rcw_1600_sdboot.bin\nRCW_ls1046a-rdb         :=ls1046ardb/RR_FFSSPPPH_1133_5559/rcw_1800_qspiboot.bin\nRCW_ls1046a-rdb-sdboot  :=ls1046ardb/RR_FFSSPPPH_1133_5559/rcw_1800_sdboot.bin\nRCW_ls1088a-rdb         :=ls1088ardb/FCQQQQQQQQ_PPP_H_0x1d_0x0d/rcw_1600_qspi.bin\nRCW_ls1088a-rdb-sdboot  :=ls1088ardb/FCQQQQQQQQ_PPP_H_0x1d_0x0d/rcw_1600_sd.bin\nRCW_ls2088a-rdb         :=ls2088ardb/FFFFFFFF_PP_HH_0x2a_0x41/rcw_1800.bin\nRCW_lx2160a-rdb         :=lx2160ardb_rev2/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2900_19_5_2.bin\nRCW_lx2160a-rdb-sdboot  :=lx2160ardb_rev2/XGGFF_PP_HHHH_RR_19_5_2/rcw_2000_700_2900_19_5_2.bin\nRCW_ls1021a-twr         :=ls1021atwr/SSR_PNS_30/rcw_1200.bin\n\ndefine Build/InstallDev\n\t$(INSTALL_DIR) $(STAGING_DIR_IMAGE)\n\t$(foreach board,$(BOARDS), \\\n\t\t$(CP) $(PKG_BUILD_DIR)/$(RCW_$(board)) $(STAGING_DIR_IMAGE)/fsl_$(board)-rcw.bin;)\nendef\n\n$(eval $(call BuildPackage,layerscape-rcw))\n"
  },
  {
    "path": "package/firmware/layerscape/ls-rcw/patches/0002-fix_rcw_for_ls1012a-frdm.patch",
    "content": "--- a/ls1012afrdm/N_SSNP_3305/rcw_800.rcw\n+++ b/ls1012afrdm/N_SSNP_3305/rcw_800.rcw\n@@ -41,8 +41,8 @@ EC1_EXT_SAI2_RX=1\n EC1_BASE=0\n UART1_BASE=1\n SDHC1_BASE=1\n-SDHC2_BASE_DAT321=1\n-SDHC2_BASE_BASE=1\n+SDHC2_BASE_DAT321=3\n+SDHC2_BASE_BASE=3\n UART2_BASE_DATA=1\n EMI1_BASE=1\n CLK_OUT_BASE=1\n"
  },
  {
    "path": "package/firmware/layerscape/ppfe-firmware/Makefile",
    "content": "#\n# Copyright (C) 2016 Jiang Yutang <jiangyutang1978@gmail.com>\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=ppfe\nPKG_VERSION:=21.08\nPKG_RELEASE:=$(AUTORELEASE)\n\nPKG_SOURCE_PROTO:=git\nPKG_SOURCE_URL:=https://github.com/NXP/qoriq-engine-pfe-bin.git\nPKG_SOURCE_VERSION:=LSDK-21.08\nPKG_MIRROR_HASH:=ba524b8a56c66cf8e7ebb8e742b0d6b66f9177b6fa821c405a09b6c8919e3db0\n\nPKG_FLAGS:=nonshared\n\ninclude $(INCLUDE_DIR)/package.mk\n\nRSTRIP:=:\nSTRIP:=:\n\ndefine Package/layerscape-ppfe\n  SECTION:=firmware\n  CATEGORY:=Firmware\n  TITLE:=NXP Layerscape PPFE firmware\n  DEPENDS:=@TARGET_layerscape\n  CONFIG_FW:=ls1012a/u-boot/pfe_fw_sbl.itb\n  CONFIG_BIN1:=ls1012a/slow_path/ppfe_class_ls1012a.elf\n  CONFIG_BIN2:=ls1012a/slow_path/ppfe_tmu_ls1012a.elf\n  CONFIG_LIC:=NXP-Binary-EULA.txt\nendef\n\ndefine Build/Compile\nendef\n\ndefine Package/layerscape-ppfe/install\n\t$(INSTALL_DIR) $(STAGING_DIR_IMAGE)\n\t$(INSTALL_DATA) $(PKG_BUILD_DIR)/$(CONFIG_FW) \\\n\t\t$(STAGING_DIR_IMAGE)/pfe.itb\n\t$(INSTALL_DIR) $(1)/lib/firmware/\n\t$(INSTALL_DATA) \\\n\t\t$(PKG_BUILD_DIR)/$(CONFIG_BIN1) \\\n\t\t$(PKG_BUILD_DIR)/$(CONFIG_BIN2) \\\n\t\t$(PKG_BUILD_DIR)/$(CONFIG_LIC) \\\n\t\t$(1)/lib/firmware/\nendef\n\n$(eval $(call BuildPackage,layerscape-ppfe))\n"
  },
  {
    "path": "package/firmware/linux-firmware/Makefile",
    "content": "#\n# Copyright (C) 2014 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=linux-firmware\nPKG_VERSION:=20220509\nPKG_RELEASE:=1\n\nPKG_SOURCE_URL:=@KERNEL/linux/kernel/firmware\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz\nPKG_HASH:=376e0b3d7b4f8aaa2abf7f5ab74803dcf14b06b94e3d841b1467cd9a2848255e\n\nPKG_MAINTAINER:=Felix Fietkau <nbd@nbd.name>\n\nSCAN_DEPS = *.mk\n\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine Package/firmware-default\n  SECTION:=firmware\n  CATEGORY:=Firmware\n  URL:=http://git.kernel.org/cgit/linux/kernel/git/firmware/linux-firmware.git\n  TITLE:=$(1)\n  DEPENDS:=$(2)\nendef\n\ndefine Build/Compile\n\nendef\n\ninclude $(wildcard ./*.mk)\n#$(eval $(call BuildPackage,linux-firmware))\n"
  },
  {
    "path": "package/firmware/linux-firmware/amd.mk",
    "content": "Package/amd64-microcode = $(call Package/firmware-default,AMD64 CPU microcode,@TARGET_x86)\ndefine Package/amd64-microcode/install\n\t$(INSTALL_DIR) $(1)/lib/firmware/amd-ucode\n\t$(CP) \\\n\t\t$(PKG_BUILD_DIR)/amd-ucode/*.bin \\\n\t\t$(1)/lib/firmware/amd-ucode\nendef\n\n$(eval $(call BuildPackage,amd64-microcode))\n\nPackage/amdgpu-firmware = $(call Package/firmware-default,AMDGPU Video Driver firmware)\ndefine Package/amdgpu-firmware/install\n\t$(INSTALL_DIR) $(1)/lib/firmware/amdgpu\n\t$(CP) \\\n\t\t$(PKG_BUILD_DIR)/amdgpu/*.bin \\\n\t\t$(1)/lib/firmware/amdgpu\nendef\n\n$(eval $(call BuildPackage,amdgpu-firmware))\n\nPackage/radeon-firmware = $(call Package/firmware-default,Radeon Video Driver firmware)\ndefine Package/radeon-firmware/install\n\t$(INSTALL_DIR) $(1)/lib/firmware/radeon\n\t$(CP) \\\n\t\t$(PKG_BUILD_DIR)/radeon/*.bin \\\n\t\t$(1)/lib/firmware/radeon\nendef\n\n$(eval $(call BuildPackage,radeon-firmware))\n"
  },
  {
    "path": "package/firmware/linux-firmware/broadcom.mk",
    "content": "Package/brcmfmac-firmware-43602a1-pcie = $(call Package/firmware-default,Broadcom 43602a1 FullMAC PCIe firmware)\ndefine Package/brcmfmac-firmware-43602a1-pcie/install\n\t$(INSTALL_DIR) $(1)/lib/firmware/brcm\n\t$(INSTALL_DATA) \\\n\t\t$(PKG_BUILD_DIR)/brcm/brcmfmac43602-pcie.ap.bin \\\n\t\t$(1)/lib/firmware/brcm/brcmfmac43602-pcie.bin\nendef\n$(eval $(call BuildPackage,brcmfmac-firmware-43602a1-pcie))\n\nPackage/brcmfmac-firmware-4366b1-pcie = $(call Package/firmware-default,Broadcom 4366b1 FullMAC PCIe firmware)\ndefine Package/brcmfmac-firmware-4366b1-pcie/install\n\t$(INSTALL_DIR) $(1)/lib/firmware/brcm\n\t$(INSTALL_DATA) \\\n\t\t$(PKG_BUILD_DIR)/brcm/brcmfmac4366b-pcie.bin \\\n\t\t$(1)/lib/firmware/brcm/\nendef\n$(eval $(call BuildPackage,brcmfmac-firmware-4366b1-pcie))\n\nPackage/brcmfmac-firmware-4366c0-pcie = $(call Package/firmware-default,Broadcom 4366c0 FullMAC PCIe firmware)\ndefine Package/brcmfmac-firmware-4366c0-pcie/install\n\t$(INSTALL_DIR) $(1)/lib/firmware/brcm\n\t$(INSTALL_DATA) \\\n\t\t$(PKG_BUILD_DIR)/brcm/brcmfmac4366c-pcie.bin \\\n\t\t$(1)/lib/firmware/brcm/\nendef\n$(eval $(call BuildPackage,brcmfmac-firmware-4366c0-pcie))\n\nPackage/brcmfmac-firmware-4329-sdio = $(call Package/firmware-default,Broadcom BCM4329 FullMac SDIO firmware)\ndefine Package/brcmfmac-firmware-4329-sdio/install\n\t$(INSTALL_DIR) $(1)/lib/firmware/brcm\n\t$(INSTALL_DATA) \\\n\t\t$(PKG_BUILD_DIR)/brcm/brcmfmac4329-sdio.bin \\\n\t\t$(1)/lib/firmware/brcm/brcmfmac4329-sdio.bin\nendef\n$(eval $(call BuildPackage,brcmfmac-firmware-4329-sdio))\n\nPackage/brcmfmac-firmware-43430-sdio-rpi-3b = $(call Package/firmware-default,Broadcom BCM43430 NVRAM for Raspberry Pi 3B)\ndefine Package/brcmfmac-firmware-43430-sdio-rpi-3b/install\n\t$(INSTALL_DIR) $(1)/lib/firmware/brcm\n\t$(INSTALL_DATA) \\\n\t\t$(PKG_BUILD_DIR)/brcm/brcmfmac43430-sdio.raspberrypi,3-model-b.txt \\\n\t\t$(1)/lib/firmware/brcm/brcmfmac43430-sdio.raspberrypi,3-model-b.txt\nendef\n$(eval $(call BuildPackage,brcmfmac-firmware-43430-sdio-rpi-3b))\n\nPackage/brcmfmac-firmware-43430-sdio-rpi-zero-w = $(call Package/firmware-default,Broadcom BCM43430 NVRAM for Raspberry Pi Zero W)\ndefine Package/brcmfmac-firmware-43430-sdio-rpi-zero-w/install\n\t$(INSTALL_DIR) $(1)/lib/firmware/brcm\n\t$(INSTALL_DATA) \\\n\t\t$(PKG_BUILD_DIR)/brcm/brcmfmac43430-sdio.raspberrypi,3-model-b.txt \\\n\t\t$(1)/lib/firmware/brcm/brcmfmac43430-sdio.raspberrypi,model-zero-w.txt\nendef\n$(eval $(call BuildPackage,brcmfmac-firmware-43430-sdio-rpi-zero-w))\n\nPackage/brcmfmac-firmware-43430a0-sdio = $(call Package/firmware-default,Broadcom BCM43430a0 FullMac SDIO firmware)\ndefine Package/brcmfmac-firmware-43430a0-sdio/install\n\t$(INSTALL_DIR) $(1)/lib/firmware/brcm\n\t$(INSTALL_DATA) \\\n\t\t$(PKG_BUILD_DIR)/brcm/brcmfmac43430a0-sdio.bin \\\n\t\t$(1)/lib/firmware/brcm/brcmfmac43430a0-sdio.bin\nendef\n$(eval $(call BuildPackage,brcmfmac-firmware-43430a0-sdio))\n\nPackage/brcmfmac-firmware-43455-sdio-rpi-3b-plus = $(call Package/firmware-default,Broadcom BCM43455 NVRAM for Raspberry Pi 3B+)\ndefine Package/brcmfmac-firmware-43455-sdio-rpi-3b-plus/install\n\t$(INSTALL_DIR) $(1)/lib/firmware/brcm\n\t$(INSTALL_DATA) \\\n\t\t$(PKG_BUILD_DIR)/brcm/brcmfmac43455-sdio.raspberrypi,3-model-b-plus.txt \\\n\t\t$(1)/lib/firmware/brcm/brcmfmac43455-sdio.raspberrypi,3-model-b-plus.txt\nendef\n$(eval $(call BuildPackage,brcmfmac-firmware-43455-sdio-rpi-3b-plus))\n\nPackage/brcmfmac-firmware-43455-sdio-rpi-4b = $(call Package/firmware-default,Broadcom BCM43455 NVRAM for Raspberry Pi 4B)\ndefine Package/brcmfmac-firmware-43455-sdio-rpi-4b/install\n\t$(INSTALL_DIR) $(1)/lib/firmware/brcm\n\t$(INSTALL_DATA) \\\n\t\t$(PKG_BUILD_DIR)/brcm/brcmfmac43455-sdio.raspberrypi,4-model-b.txt \\\n\t\t$(1)/lib/firmware/brcm/brcmfmac43455-sdio.raspberrypi,4-model-b.txt\nendef\n$(eval $(call BuildPackage,brcmfmac-firmware-43455-sdio-rpi-4b))\n\nPackage/brcmfmac-firmware-usb = $(call Package/firmware-default,Broadcom BCM43xx fullmac USB firmware)\ndefine Package/brcmfmac-firmware-usb/install\n\t$(INSTALL_DIR) $(1)/lib/firmware/brcm\n\t$(INSTALL_DATA) \\\n\t\t$(PKG_BUILD_DIR)/brcm/brcmfmac43236b.bin \\\n\t\t$(1)/lib/firmware/brcm/\n\t$(INSTALL_DATA) \\\n\t\t$(PKG_BUILD_DIR)/brcm/brcmfmac43143.bin \\\n\t\t$(1)/lib/firmware/brcm/\nendef\n$(eval $(call BuildPackage,brcmfmac-firmware-usb))\n\nPackage/brcmsmac-firmware = $(call Package/firmware-default,Broadcom BCM43xx softmac PCIe firmware)\ndefine Package/brcmsmac-firmware/install\n\t$(INSTALL_DIR) $(1)/lib/firmware/brcm\n\t$(INSTALL_DATA) \\\n\t\t$(PKG_BUILD_DIR)/$(PKG_LINUX_FIRMWARE_SUBDIR)/brcm/bcm43xx-0.fw \\\n\t\t$(PKG_BUILD_DIR)/$(PKG_LINUX_FIRMWARE_SUBDIR)/brcm/bcm43xx_hdr-0.fw \\\n\t\t$(1)/lib/firmware/brcm/\nendef\n$(eval $(call BuildPackage,brcmsmac-firmware))\n\nPackage/bnx2-firmware = $(call Package/firmware-default,Broadcom BCM5706/5708/5709/5716 firmware)\ndefine Package/bnx2-firmware/install\n\t$(INSTALL_DIR) $(1)/lib/firmware/bnx2\n\t$(INSTALL_DATA) \\\n\t\t$(PKG_BUILD_DIR)/bnx2/* \\\n\t\t$(1)/lib/firmware/bnx2/\nendef\n$(eval $(call BuildPackage,bnx2-firmware))\n\nPackage/bnx2x-firmware = $(call Package/firmware-default,=QLogic 5771x/578xx firmware)\ndefine Package/bnx2x-firmware/install\n\t$(INSTALL_DIR) $(1)/lib/firmware/bnx2x\n\t$(INSTALL_DATA) \\\n\t\t$(PKG_BUILD_DIR)/bnx2x/* \\\n\t\t$(1)/lib/firmware/bnx2x/\nendef\n$(eval $(call BuildPackage,bnx2x-firmware))\n"
  },
  {
    "path": "package/firmware/linux-firmware/cis.mk",
    "content": "Package/aircard-pcmcia-firmware = $(call Package/firmware-default,Sierra Wireless Aircard 555/7xx/8x0 firmware)\ndefine Package/aircard-pcmcia-firmware/install\n\t$(INSTALL_DIR) $(1)/lib/firmware/cis\n\t$(INSTALL_DATA) \\\n\t\t$(PKG_BUILD_DIR)/cis/SW_555_SER.cis \\\n\t\t$(PKG_BUILD_DIR)/cis/SW_7xx_SER.cis \\\n\t\t$(PKG_BUILD_DIR)/cis/SW_8xx_SER.cis \\\n\t\t$(1)/lib/firmware/cis\nendef\n$(eval $(call BuildPackage,aircard-pcmcia-firmware))\n"
  },
  {
    "path": "package/firmware/linux-firmware/edgeport.mk",
    "content": "Package/edgeport-firmware = $(call Package/firmware-default,USB Inside Out Edgeport Serial Driver firmware)\ndefine Package/edgeport-firmware/install\n\t$(INSTALL_DIR) $(1)/lib/firmware/edgeport\n\t$(INSTALL_DATA) \\\n\t\t$(PKG_BUILD_DIR)/edgeport/boot.fw \\\n\t\t$(PKG_BUILD_DIR)/edgeport/boot2.fw \\\n\t\t$(PKG_BUILD_DIR)/edgeport/down.fw \\\n\t\t$(PKG_BUILD_DIR)/edgeport/down2.fw \\\n\t\t$(1)/lib/firmware/edgeport\nendef\n\n$(eval $(call BuildPackage,edgeport-firmware))\n"
  },
  {
    "path": "package/firmware/linux-firmware/intel.mk",
    "content": "Package/ibt-firmware = $(call Package/firmware-default,Intel bluetooth firmware)\ndefine Package/ibt-firmware/install\n\t$(INSTALL_DIR) $(1)/lib/firmware/intel\n\t$(CP) \\\n\t\t$(PKG_BUILD_DIR)/intel/*.bseq \\\n\t\t$(1)/lib/firmware/intel\nendef\n$(eval $(call BuildPackage,ibt-firmware))\n\nPackage/iwl3945-firmware = $(call Package/firmware-default,Intel IWL3945 firmware)\ndefine Package/iwl3945-firmware/install\n\t$(INSTALL_DIR) $(1)/lib/firmware\n\t$(INSTALL_DATA) $(PKG_BUILD_DIR)/iwlwifi-3945-2.ucode $(1)/lib/firmware\nendef\n$(eval $(call BuildPackage,iwl3945-firmware))\n\nPackage/iwl4965-firmware = $(call Package/firmware-default,Intel IWL4965 firmware)\ndefine Package/iwl4965-firmware/install\n\t$(INSTALL_DIR) $(1)/lib/firmware\n\t$(INSTALL_DATA) $(PKG_BUILD_DIR)/iwlwifi-4965-2.ucode $(1)/lib/firmware\nendef\n$(eval $(call BuildPackage,iwl4965-firmware))\n\nPackage/iwlwifi-firmware-iwl100 = $(call Package/firmware-default,Intel Centrino Wireless-N 100 firmware)\ndefine Package/iwlwifi-firmware-iwl100/install\n\t$(INSTALL_DIR) $(1)/lib/firmware\n\t$(INSTALL_DATA) $(PKG_BUILD_DIR)/iwlwifi-100-5.ucode $(1)/lib/firmware\nendef\n$(eval $(call BuildPackage,iwlwifi-firmware-iwl100))\n\nPackage/iwlwifi-firmware-iwl1000 = $(call Package/firmware-default,Intel Centrino Wireless-N 1000 firmware)\ndefine Package/iwlwifi-firmware-iwl1000/install\n\t$(INSTALL_DIR) $(1)/lib/firmware\n\t$(INSTALL_DATA) $(PKG_BUILD_DIR)/iwlwifi-1000-5.ucode $(1)/lib/firmware\nendef\n$(eval $(call BuildPackage,iwlwifi-firmware-iwl1000))\n\nPackage/iwlwifi-firmware-iwl105 = $(call Package/firmware-default,Intel Centrino Wireless-N 105 firmware)\ndefine Package/iwlwifi-firmware-iwl105/install\n\t$(INSTALL_DIR) $(1)/lib/firmware\n\t$(INSTALL_DATA) $(PKG_BUILD_DIR)/iwlwifi-105-6.ucode $(1)/lib/firmware\nendef\n$(eval $(call BuildPackage,iwlwifi-firmware-iwl105))\n\nPackage/iwlwifi-firmware-iwl135 = $(call Package/firmware-default,Intel Centrino Wireless-N 135 firmware)\ndefine Package/iwlwifi-firmware-iwl135/install\n\t$(INSTALL_DIR) $(1)/lib/firmware\n\t$(INSTALL_DATA) $(PKG_BUILD_DIR)/iwlwifi-135-6.ucode $(1)/lib/firmware\nendef\n$(eval $(call BuildPackage,iwlwifi-firmware-iwl135))\n\nPackage/iwlwifi-firmware-iwl2000 = $(call Package/firmware-default,Intel Centrino Wireless-N 2200 firmware)\ndefine Package/iwlwifi-firmware-iwl2000/install\n\t$(INSTALL_DIR) $(1)/lib/firmware\n\t$(INSTALL_DATA) $(PKG_BUILD_DIR)/iwlwifi-2000-6.ucode $(1)/lib/firmware\nendef\n$(eval $(call BuildPackage,iwlwifi-firmware-iwl2000))\n\nPackage/iwlwifi-firmware-iwl2030 = $(call Package/firmware-default,Intel Centrino Wireless-N 2230 firmware)\ndefine Package/iwlwifi-firmware-iwl2030/install\n\t$(INSTALL_DIR) $(1)/lib/firmware\n\t$(INSTALL_DATA) $(PKG_BUILD_DIR)/iwlwifi-2030-6.ucode $(1)/lib/firmware\nendef\n$(eval $(call BuildPackage,iwlwifi-firmware-iwl2030))\n\nPackage/iwlwifi-firmware-iwl3160 = $(call Package/firmware-default,Intel Wireless 3160 firmware)\ndefine Package/iwlwifi-firmware-iwl3160/install\n\t$(INSTALL_DIR) $(1)/lib/firmware\n\t$(INSTALL_DATA) $(PKG_BUILD_DIR)/iwlwifi-3160-17.ucode $(1)/lib/firmware\nendef\n$(eval $(call BuildPackage,iwlwifi-firmware-iwl3160))\n\nPackage/iwlwifi-firmware-iwl3168 = $(call Package/firmware-default,Intel Wireless 3168 firmware)\ndefine Package/iwlwifi-firmware-iwl3168/install\n\t$(INSTALL_DIR) $(1)/lib/firmware\n\t$(INSTALL_DATA) $(PKG_BUILD_DIR)/iwlwifi-3168-29.ucode $(1)/lib/firmware\nendef\n$(eval $(call BuildPackage,iwlwifi-firmware-iwl3168))\n\nPackage/iwlwifi-firmware-iwl5000 = $(call Package/firmware-default,Intel Wireless 5100AGN 5300AGN and 5350AGN firmware)\ndefine Package/iwlwifi-firmware-iwl5000/install\n\t$(INSTALL_DIR) $(1)/lib/firmware\n\t$(INSTALL_DATA) $(PKG_BUILD_DIR)/iwlwifi-5000-5.ucode $(1)/lib/firmware\nendef\n$(eval $(call BuildPackage,iwlwifi-firmware-iwl5000))\n\nPackage/iwlwifi-firmware-iwl5150 = $(call Package/firmware-default,Intel Wireless Wi-Fi 5150AGN firmware)\ndefine Package/iwlwifi-firmware-iwl5150/install\n\t$(INSTALL_DIR) $(1)/lib/firmware\n\t$(INSTALL_DATA) $(PKG_BUILD_DIR)/iwlwifi-5150-2.ucode $(1)/lib/firmware\nendef\n$(eval $(call BuildPackage,iwlwifi-firmware-iwl5150))\n\nPackage/iwlwifi-firmware-iwl6000g2 = $(call Package/firmware-default,Intel Centrino 6300 and 6200 firmware)\ndefine Package/iwlwifi-firmware-iwl6000g2/install\n\t$(INSTALL_DIR) $(1)/lib/firmware\n\t$(INSTALL_DATA) $(PKG_BUILD_DIR)/iwlwifi-6000-4.ucode $(1)/lib/firmware\nendef\n$(eval $(call BuildPackage,iwlwifi-firmware-iwl6000g2))\n\nPackage/iwlwifi-firmware-iwl6000g2a = $(call Package/firmware-default,Intel Centrino 6205 firmware)\ndefine Package/iwlwifi-firmware-iwl6000g2a/install\n\t$(INSTALL_DIR) $(1)/lib/firmware\n\t$(INSTALL_DATA) $(PKG_BUILD_DIR)/iwlwifi-6000g2a-6.ucode $(1)/lib/firmware\nendef\n$(eval $(call BuildPackage,iwlwifi-firmware-iwl6000g2a))\n\nPackage/iwlwifi-firmware-iwl6000g2b = $(call Package/firmware-default,Intel Centrino 6230 1030 130 and 6235 firmware)\ndefine Package/iwlwifi-firmware-iwl6000g2b/install\n\t$(INSTALL_DIR) $(1)/lib/firmware\n\t$(INSTALL_DATA) $(PKG_BUILD_DIR)/iwlwifi-6000g2b-6.ucode $(1)/lib/firmware\nendef\n$(eval $(call BuildPackage,iwlwifi-firmware-iwl6000g2b))\n\nPackage/iwlwifi-firmware-iwl6050 = $(call Package/firmware-default,Intel Centrino 6150 and 6250 firmware)\ndefine Package/iwlwifi-firmware-iwl6050/install\n\t$(INSTALL_DIR) $(1)/lib/firmware\n\t$(INSTALL_DATA) $(PKG_BUILD_DIR)/iwlwifi-6050-5.ucode $(1)/lib/firmware\nendef\n$(eval $(call BuildPackage,iwlwifi-firmware-iwl6050))\n\nPackage/iwlwifi-firmware-iwl7260 = $(call Package/firmware-default,Intel Wireless 7260 firmware)\ndefine Package/iwlwifi-firmware-iwl7260/install\n\t$(INSTALL_DIR) $(1)/lib/firmware\n\t$(INSTALL_DATA) $(PKG_BUILD_DIR)/iwlwifi-7260-17.ucode $(1)/lib/firmware\nendef\n$(eval $(call BuildPackage,iwlwifi-firmware-iwl7260))\n\nPackage/iwlwifi-firmware-iwl7265 = $(call Package/firmware-default,Intel Wireless 7265 firmware)\ndefine Package/iwlwifi-firmware-iwl7265/install\n\t$(INSTALL_DIR) $(1)/lib/firmware\n\t$(INSTALL_DATA) $(PKG_BUILD_DIR)/iwlwifi-7265-17.ucode $(1)/lib/firmware\nendef\n$(eval $(call BuildPackage,iwlwifi-firmware-iwl7265))\n\nPackage/iwlwifi-firmware-iwl7265d = $(call Package/firmware-default,Intel Wireless 7265D and 3165 firmware)\ndefine Package/iwlwifi-firmware-iwl7265d/install\n\t$(INSTALL_DIR) $(1)/lib/firmware\n\t$(INSTALL_DATA) $(PKG_BUILD_DIR)/iwlwifi-7265D-29.ucode $(1)/lib/firmware\nendef\n$(eval $(call BuildPackage,iwlwifi-firmware-iwl7265d))\n\nPackage/iwlwifi-firmware-iwl8260c = $(call Package/firmware-default,Intel Wireless 8260 and 4165 firmware)\ndefine Package/iwlwifi-firmware-iwl8260c/install\n\t$(INSTALL_DIR) $(1)/lib/firmware\n\t$(INSTALL_DATA) $(PKG_BUILD_DIR)/iwlwifi-8000C-36.ucode $(1)/lib/firmware\nendef\n$(eval $(call BuildPackage,iwlwifi-firmware-iwl8260c))\n\nPackage/iwlwifi-firmware-iwl8265 = $(call Package/firmware-default,Intel Wireless 8265 firmware)\ndefine Package/iwlwifi-firmware-iwl8265/install\n\t$(INSTALL_DIR) $(1)/lib/firmware\n\t$(INSTALL_DATA) $(PKG_BUILD_DIR)/iwlwifi-8265-36.ucode $(1)/lib/firmware\nendef\n$(eval $(call BuildPackage,iwlwifi-firmware-iwl8265))\n\nPackage/iwlwifi-firmware-iwl9000 = $(call Package/firmware-default,Intel Wireless 9000 firmware)\ndefine Package/iwlwifi-firmware-iwl9000/install\n\t$(INSTALL_DIR) $(1)/lib/firmware\n\t$(INSTALL_DATA) $(PKG_BUILD_DIR)/iwlwifi-9000-pu-b0-jf-b0-46.ucode $(1)/lib/firmware\nendef\n$(eval $(call BuildPackage,iwlwifi-firmware-iwl9000))\n\nPackage/iwlwifi-firmware-iwl9260 = $(call Package/firmware-default,Intel Wireless 9260 firmware)\ndefine Package/iwlwifi-firmware-iwl9260/install\n\t$(INSTALL_DIR) $(1)/lib/firmware\n\t$(INSTALL_DATA) $(PKG_BUILD_DIR)/iwlwifi-9260-th-b0-jf-b0-46.ucode $(1)/lib/firmware\nendef\n$(eval $(call BuildPackage,iwlwifi-firmware-iwl9260))\n\nPackage/iwlwifi-firmware-ax200 = $(call Package/firmware-default,Intel AX200 firmware)\ndefine Package/iwlwifi-firmware-ax200/install\n\t$(INSTALL_DIR) $(1)/lib/firmware\n\t$(INSTALL_DATA) $(PKG_BUILD_DIR)/iwlwifi-cc-a0-66.ucode $(1)/lib/firmware\nendef\n$(eval $(call BuildPackage,iwlwifi-firmware-ax200))\n\nPackage/iwlwifi-firmware-ax210 = $(call Package/firmware-default,Intel AX210 firmware)\ndefine Package/iwlwifi-firmware-ax210/install\n\t$(INSTALL_DIR) $(1)/lib/firmware\n\t$(INSTALL_DATA) $(PKG_BUILD_DIR)/iwlwifi-ty-a0-gf-a0-66.ucode $(1)/lib/firmware\n\t$(INSTALL_DATA) $(PKG_BUILD_DIR)/iwlwifi-ty-a0-gf-a0.pnvm $(1)/lib/firmware\nendef\n$(eval $(call BuildPackage,iwlwifi-firmware-ax210))\n\nPackage/e100-firmware = $(call Package/firmware-default,Intel e100)\ndefine Package/e100-firmware/install\n\t$(INSTALL_DIR) $(1)/lib/firmware/e100\n\t$(INSTALL_DATA) $(PKG_BUILD_DIR)/e100/d101m_ucode.bin $(1)/lib/firmware/e100/\n\t$(INSTALL_DATA) $(PKG_BUILD_DIR)/e100/d101s_ucode.bin $(1)/lib/firmware/e100/\n\t$(INSTALL_DATA) $(PKG_BUILD_DIR)/e100/d102e_ucode.bin $(1)/lib/firmware/e100/\nendef\n$(eval $(call BuildPackage,e100-firmware))\n"
  },
  {
    "path": "package/firmware/linux-firmware/marvell.mk",
    "content": "Package/mwl8k-firmware = $(call Package/firmware-default,Marvell 8366/8687 firmware)\ndefine Package/mwl8k-firmware/install\n\t$(INSTALL_DIR) $(1)/lib/firmware/mwl8k\n\t$(INSTALL_DATA) \\\n\t\t$(PKG_BUILD_DIR)/mwl8k/fmimage_8366_ap-3.fw \\\n\t\t$(PKG_BUILD_DIR)/mwl8k/fmimage_8366.fw \\\n\t\t$(PKG_BUILD_DIR)/mwl8k/helper_8366.fw \\\n\t\t$(PKG_BUILD_DIR)/mwl8k/fmimage_8687.fw \\\n\t\t$(PKG_BUILD_DIR)/mwl8k/helper_8687.fw \\\n\t\t$(1)/lib/firmware/mwl8k/\nendef\n$(eval $(call BuildPackage,mwl8k-firmware))\n\nPackage/mwifiex-pcie-firmware = $(call Package/firmware-default,Marvell 8897 firmware)\ndefine Package/mwifiex-pcie-firmware/install\n\t$(INSTALL_DIR) $(1)/lib/firmware/mrvl\n\t$(INSTALL_DATA) \\\n\t\t$(PKG_BUILD_DIR)/mrvl/pcie8897_uapsta.bin \\\n\t\t$(1)/lib/firmware/mrvl/\nendef\n$(eval $(call BuildPackage,mwifiex-pcie-firmware))\n\nPackage/mwifiex-sdio-firmware = $(call Package/firmware-default,Marvell 8887/8997 firmware)\ndefine Package/mwifiex-sdio-firmware/install\n\t$(INSTALL_DIR) $(1)/lib/firmware/mrvl\n\t$(INSTALL_DATA) \\\n\t\t$(PKG_BUILD_DIR)/mrvl/sd8887_uapsta.bin \\\n\t\t$(PKG_BUILD_DIR)/mrvl/sdsd8997_combo_v4.bin \\\n\t\t$(1)/lib/firmware/mrvl/\n\tln -s ../mrvl/sdsd8997_combo_v4.bin $(1)/lib/firmware/mrvl/sd8997_uapsta.bin\nendef\n$(eval $(call BuildPackage,mwifiex-sdio-firmware))\n\nPackage/libertas-usb-firmware = $(call Package/firmware-default,Marvell 8388/8682 USB firmware)\ndefine Package/libertas-usb-firmware/install\n\t$(INSTALL_DIR) $(1)/lib/firmware/libertas\n\t$(INSTALL_DATA) \\\n\t\t$(PKG_BUILD_DIR)/libertas/usb8388_v9.bin \\\n\t\t$(PKG_BUILD_DIR)/libertas/usb8682.bin \\\n\t\t$(1)/lib/firmware/libertas/\nendef\n$(eval $(call BuildPackage,libertas-usb-firmware))\n\nPackage/libertas-sdio-firmware = $(call Package/firmware-default,Marvell 8385/8686/8688 SDIO firmware)\ndefine Package/libertas-sdio-firmware/install\n\t$(INSTALL_DIR) $(1)/lib/firmware/libertas\n\t$(INSTALL_DATA) \\\n\t\t$(PKG_BUILD_DIR)/libertas/sd8385_helper.bin \\\n\t\t$(PKG_BUILD_DIR)/libertas/sd8385.bin \\\n\t\t$(PKG_BUILD_DIR)/libertas/sd8686_v9_helper.bin \\\n\t\t$(PKG_BUILD_DIR)/libertas/sd8686_v9.bin \\\n\t\t$(1)/lib/firmware/libertas\n\t$(INSTALL_DIR) $(1)/lib/firmware/mrvl\n\t$(INSTALL_DATA) \\\n\t\t$(PKG_BUILD_DIR)/mrvl/sd8688_helper.bin \\\n\t\t$(PKG_BUILD_DIR)/mrvl/sd8688.bin \\\n\t\t$(1)/lib/firmware/mrvl\n\tln -s ../mrvl/sd8688_helper.bin $(1)/lib/firmware/libertas/sd8688_helper.bin\n\tln -s ../mrvl/sd8688.bin $(1)/lib/firmware/libertas/sd8688.bin\nendef\n$(eval $(call BuildPackage,libertas-sdio-firmware))\n\nPackage/libertas-spi-firmware = $(call Package/firmware-default,Marvell 8686 SPI firmware)\ndefine Package/libertas-spi-firmware/install\n\t$(INSTALL_DIR) $(1)/lib/firmware/libertas\n\t$(INSTALL_DATA) \\\n\t\t$(PKG_BUILD_DIR)/libertas/gspi8686_v9_helper.bin \\\n\t\t$(PKG_BUILD_DIR)/libertas/gspi8686_v9.bin \\\n\t\t$(1)/lib/firmware/libertas\nendef\n$(eval $(call BuildPackage,libertas-spi-firmware))\n\n"
  },
  {
    "path": "package/firmware/linux-firmware/mediatek.mk",
    "content": "Package/mt7601u-firmware = $(call Package/firmware-default,MediaTek MT7601U firmware)\ndefine Package/mt7601u-firmware/install\n\t$(INSTALL_DIR) $(1)/lib/firmware\n\t$(INSTALL_DATA) \\\n\t\t$(PKG_BUILD_DIR)/mt7601u.bin \\\n\t\t$(1)/lib/firmware\nendef\n$(eval $(call BuildPackage,mt7601u-firmware))\n\nPackage/rt2800-pci-firmware = $(call Package/firmware-default,Ralink RT28xx/3xxx PCI/SoC firmware)\ndefine Package/rt2800-pci-firmware/install\n\t$(INSTALL_DIR) $(1)/lib/firmware\n\t$(INSTALL_DATA) \\\n\t\t$(PKG_BUILD_DIR)/rt2860.bin \\\n\t\t$(PKG_BUILD_DIR)/rt3290.bin \\\n\t\t$(1)/lib/firmware\nendef\n$(eval $(call BuildPackage,rt2800-pci-firmware))\n\nPackage/rt2800-usb-firmware = $(call Package/firmware-default,Ralink RT28xx/3xxx USB firmware)\ndefine Package/rt2800-usb-firmware/install\n\t$(INSTALL_DIR) $(1)/lib/firmware\n\t$(INSTALL_DATA) $(PKG_BUILD_DIR)/rt2870.bin $(1)/lib/firmware/\nendef\n$(eval $(call BuildPackage,rt2800-usb-firmware))\n\nPackage/rt61-pci-firmware = $(call Package/firmware-default,Ralink RT2561 firmware)\ndefine Package/rt61-pci-firmware/install\n\t$(INSTALL_DIR) $(1)/lib/firmware\n\t$(INSTALL_DATA) \\\n\t\t$(PKG_BUILD_DIR)/rt2561.bin \\\n\t\t$(PKG_BUILD_DIR)/rt2561s.bin \\\n\t\t$(PKG_BUILD_DIR)/rt2661.bin \\\n\t\t$(1)/lib/firmware/\nendef\n$(eval $(call BuildPackage,rt61-pci-firmware))\n\nPackage/rt73-usb-firmware = $(call Package/firmware-default,Ralink RT2573 firmware)\ndefine Package/rt73-usb-firmware/install\n\t$(INSTALL_DIR) $(1)/lib/firmware\n\t$(INSTALL_DATA) $(PKG_BUILD_DIR)/rt73.bin $(1)/lib/firmware/\nendef\n$(eval $(call BuildPackage,rt73-usb-firmware))\n\nPackage/mt7622bt-firmware = $(call Package/firmware-default,mt7622bt firmware)\ndefine Package/mt7622bt-firmware/install\n\t$(INSTALL_DIR) $(1)/lib/firmware/mediatek\n\t$(INSTALL_DATA) \\\n\t\t$(PKG_BUILD_DIR)/mediatek/mt7622pr2h.bin \\\n\t\t$(1)/lib/firmware/mediatek\nendef\n$(eval $(call BuildPackage,mt7622bt-firmware))\n"
  },
  {
    "path": "package/firmware/linux-firmware/misc.mk",
    "content": "Package/eip197-mini-firmware = $(call Package/firmware-default,Inside Secure EIP197 mini firmware)\ndefine Package/eip197-mini-firmware/install\n\t$(INSTALL_DIR) $(1)/lib/firmware/inside-secure/eip197_minifw\n\t$(INSTALL_DATA) \\\n\t\t$(PKG_BUILD_DIR)/inside-secure/eip197_minifw/ifpp.bin \\\n\t\t$(PKG_BUILD_DIR)/inside-secure/eip197_minifw/ipue.bin \\\n\t\t$(1)/lib/firmware/inside-secure/eip197_minifw\nendef\n$(eval $(call BuildPackage,eip197-mini-firmware))\n"
  },
  {
    "path": "package/firmware/linux-firmware/qca.mk",
    "content": "Package/ar3k-firmware = $(call Package/firmware-default,ath3k firmware)\ndefine Package/ar3k-firmware/install\n\t$(INSTALL_DIR) $(1)/lib/firmware/ar3k\n\t$(CP) \\\n\t\t$(PKG_BUILD_DIR)/ar3k/*.dfu \\\n\t\t$(1)/lib/firmware/ar3k\n\t$(INSTALL_DIR) $(1)/lib/firmware/qca\n\t$(CP) \\\n\t\t$(PKG_BUILD_DIR)/qca/*.bin \\\n\t\t$(1)/lib/firmware/qca\nendef\n$(eval $(call BuildPackage,ar3k-firmware))\n\n\nPackage/ath6k-firmware = $(call Package/firmware-default,AR600X firmware)\ndefine Package/ath6k-firmware/install\n\t$(INSTALL_DIR) $(1)/lib/firmware/ath6k\n\t$(CP) \\\n\t\t$(PKG_BUILD_DIR)/ath6k/* \\\n\t\t$(1)/lib/firmware/ath6k\nendef\n$(eval $(call BuildPackage,ath6k-firmware))\n\nPackage/ath9k-htc-firmware = $(call Package/firmware-default,AR9271/AR7010 firmware)\ndefine Package/ath9k-htc-firmware/install\n\t$(INSTALL_DIR) $(1)/lib/firmware/ath9k_htc\n\t$(INSTALL_DATA) \\\n\t\t$(PKG_BUILD_DIR)/ath9k_htc/htc_9271-1.4.0.fw \\\n\t\t$(PKG_BUILD_DIR)/ath9k_htc/htc_7010-1.4.0.fw \\\n\t\t$(1)/lib/firmware/ath9k_htc\nendef\n$(eval $(call BuildPackage,ath9k-htc-firmware))\n\nPackage/carl9170-firmware = $(call Package/firmware-default,AR9170 firmware)\ndefine Package/carl9170-firmware/install\n\t$(INSTALL_DIR) $(1)/lib/firmware\n\t$(INSTALL_DATA) $(PKG_BUILD_DIR)/carl9170-1.fw $(1)/lib/firmware\nendef\n$(eval $(call BuildPackage,carl9170-firmware))\n\nPackage/wil6210-firmware = $(call Package/firmware-default,wil6210 firmware)\ndefine Package/wil6210-firmware/install\n\t$(INSTALL_DIR) $(1)/lib/firmware\n\t$(INSTALL_DATA) $(PKG_BUILD_DIR)/wil6210.fw $(1)/lib/firmware\n\t$(INSTALL_DATA) $(PKG_BUILD_DIR)/wil6210.brd $(1)/lib/firmware\nendef\n$(eval $(call BuildPackage,wil6210-firmware))\n"
  },
  {
    "path": "package/firmware/linux-firmware/qca_ath10k.mk",
    "content": "Package/ath10k-board-qca4019 = $(call Package/firmware-default,ath10k qca4019 board firmware)\ndefine Package/ath10k-board-qca4019/install\n\t$(INSTALL_DIR) $(1)/lib/firmware/ath10k/QCA4019/hw1.0\n\t$(INSTALL_DATA) \\\n\t\t$(PKG_BUILD_DIR)/ath10k/QCA4019/hw1.0/board-2.bin \\\n\t\t$(1)/lib/firmware/ath10k/QCA4019/hw1.0/\nendef\n$(eval $(call BuildPackage,ath10k-board-qca4019))\nPackage/ath10k-firmware-qca4019 = $(call Package/firmware-default,ath10k qca4019 firmware)\ndefine Package/ath10k-firmware-qca4019/install\n\t$(INSTALL_DIR) $(1)/lib/firmware/ath10k/QCA4019/hw1.0\n\t$(INSTALL_DATA) \\\n\t\t$(PKG_BUILD_DIR)/ath10k/QCA4019/hw1.0/firmware-5.bin \\\n\t\t$(1)/lib/firmware/ath10k/QCA4019/hw1.0/firmware-5.bin\nendef\n$(eval $(call BuildPackage,ath10k-firmware-qca4019))\n\nPackage/ath10k-board-qca9377 = $(call Package/firmware-default,ath10k qca9377 board firmware)\ndefine Package/ath10k-board-qca9377/install\n\t$(INSTALL_DIR) $(1)/lib/firmware/ath10k/QCA9377/hw1.0\n\t$(INSTALL_DATA) \\\n\t\t$(PKG_BUILD_DIR)/ath10k/QCA9377/hw1.0/board-2.bin \\\n\t\t$(1)/lib/firmware/ath10k/QCA9377/hw1.0/\nendef\n$(eval $(call BuildPackage,ath10k-board-qca9377))\nPackage/ath10k-firmware-qca9377 = $(call Package/firmware-default,ath10k qca9377 firmware,+ath10k-board-qca9377)\ndefine Package/ath10k-firmware-qca9377/install\n\t$(INSTALL_DIR) $(1)/lib/firmware/ath10k/QCA9377/hw1.0\n\t$(INSTALL_DATA) \\\n\t\t$(PKG_BUILD_DIR)/ath10k/QCA9377/hw1.0/firmware-6.bin \\\n\t\t$(1)/lib/firmware/ath10k/QCA9377/hw1.0/firmware-6.bin\nendef\n$(eval $(call BuildPackage,ath10k-firmware-qca9377))\n\nPackage/ath10k-board-qca9887 = $(call Package/firmware-default,ath10k qca9887 board firmware)\ndefine Package/ath10k-board-qca9887/install\n\t$(INSTALL_DIR) $(1)/lib/firmware/ath10k/QCA9887/hw1.0\n\t$(INSTALL_DATA) \\\n\t\t$(PKG_BUILD_DIR)/ath10k/QCA9887/hw1.0/board.bin \\\n\t\t$(1)/lib/firmware/ath10k/QCA9887/hw1.0/board.bin\nendef\n$(eval $(call BuildPackage,ath10k-board-qca9887))\nPackage/ath10k-firmware-qca9887 = $(call Package/firmware-default,ath10k qca9887 firmware,+ath10k-board-qca9887)\ndefine Package/ath10k-firmware-qca9887/install\n\t$(INSTALL_DIR) $(1)/lib/firmware/ath10k/QCA9887/hw1.0\n\t$(INSTALL_DATA) \\\n\t\t$(PKG_BUILD_DIR)/ath10k/QCA9887/hw1.0/firmware-5.bin \\\n\t\t$(1)/lib/firmware/ath10k/QCA9887/hw1.0/firmware-5.bin\nendef\n$(eval $(call BuildPackage,ath10k-firmware-qca9887))\n\nPackage/ath10k-board-qca9888 = $(call Package/firmware-default,ath10k qca9888 board firmware)\ndefine Package/ath10k-board-qca9888/install\n\t$(INSTALL_DIR) $(1)/lib/firmware/ath10k/QCA9888/hw2.0\n\t$(INSTALL_DATA) \\\n\t\t$(PKG_BUILD_DIR)/ath10k/QCA9888/hw2.0/board-2.bin \\\n\t\t$(1)/lib/firmware/ath10k/QCA9888/hw2.0/board-2.bin\nendef\n$(eval $(call BuildPackage,ath10k-board-qca9888))\nPackage/ath10k-firmware-qca9888 = $(call Package/firmware-default,ath10k qca9888 firmware,+ath10k-board-qca9888)\ndefine Package/ath10k-firmware-qca9888/install\n\t$(INSTALL_DIR) $(1)/lib/firmware/ath10k/QCA9888/hw2.0\n\t$(INSTALL_DATA) \\\n\t\t$(PKG_BUILD_DIR)/ath10k/QCA9888/hw2.0/firmware-5.bin \\\n\t\t$(1)/lib/firmware/ath10k/QCA9888/hw2.0/firmware-5.bin\nendef\n$(eval $(call BuildPackage,ath10k-firmware-qca9888))\n\nPackage/ath10k-board-qca988x = $(call Package/firmware-default,ath10k qca988x board firmware)\ndefine Package/ath10k-board-qca988x/install\n\t$(INSTALL_DIR) $(1)/lib/firmware/ath10k/QCA988X/hw2.0\n\t$(INSTALL_DATA) \\\n\t\t$(PKG_BUILD_DIR)/ath10k/QCA988X/hw2.0/board.bin \\\n\t\t$(1)/lib/firmware/ath10k/QCA988X/hw2.0/\nendef\n$(eval $(call BuildPackage,ath10k-board-qca988x))\nPackage/ath10k-firmware-qca988x = $(call Package/firmware-default,ath10k qca988x firmware,+ath10k-board-qca988x)\ndefine Package/ath10k-firmware-qca988x/install\n\t$(INSTALL_DIR) $(1)/lib/firmware/ath10k/QCA988X/hw2.0\n\t$(INSTALL_DATA) \\\n\t\t$(PKG_BUILD_DIR)/ath10k/QCA988X/hw2.0/firmware-5.bin \\\n\t\t$(1)/lib/firmware/ath10k/QCA988X/hw2.0/firmware-5.bin\nendef\n$(eval $(call BuildPackage,ath10k-firmware-qca988x))\n\nPackage/ath10k-firmware-qca6174 = $(call Package/firmware-default,ath10k qca6174 firmware)\ndefine Package/ath10k-firmware-qca6174/install\n\t$(INSTALL_DIR) $(1)/lib/firmware/ath10k/QCA6174/hw2.1\n\t$(INSTALL_DATA) \\\n\t\t$(PKG_BUILD_DIR)/ath10k/QCA6174/hw2.1/board-2.bin \\\n\t\t$(1)/lib/firmware/ath10k/QCA6174/hw2.1/\n\t$(INSTALL_DATA) \\\n\t\t$(PKG_BUILD_DIR)/ath10k/QCA6174/hw2.1/firmware-5.bin \\\n\t\t$(1)/lib/firmware/ath10k/QCA6174/hw2.1/firmware-5.bin\n\t$(INSTALL_DIR) $(1)/lib/firmware/ath10k/QCA6174/hw3.0\n\t$(INSTALL_DATA) \\\n\t\t$(PKG_BUILD_DIR)/ath10k/QCA6174/hw3.0/board-2.bin \\\n\t\t$(1)/lib/firmware/ath10k/QCA6174/hw3.0/\n\t$(INSTALL_DATA) \\\n\t\t$(PKG_BUILD_DIR)/ath10k/QCA6174/hw3.0/firmware-6.bin \\\n\t\t$(1)/lib/firmware/ath10k/QCA6174/hw3.0/firmware-6.bin\nendef\n$(eval $(call BuildPackage,ath10k-firmware-qca6174))\n\nPackage/ath10k-board-qca99x0 = $(call Package/firmware-default,ath10k qca99x0 board firmware)\ndefine Package/ath10k-board-qca99x0/install\n\t$(INSTALL_DIR) $(1)/lib/firmware/ath10k/QCA99X0/hw2.0\n\t$(INSTALL_DATA) \\\n\t\t$(PKG_BUILD_DIR)/ath10k/QCA99X0/hw2.0/board-2.bin \\\n\t\t$(1)/lib/firmware/ath10k/QCA99X0/hw2.0/board-2.bin\nendef\n$(eval $(call BuildPackage,ath10k-board-qca99x0))\n\nPackage/ath10k-firmware-qca99x0 = $(call Package/firmware-default,ath10k qca99x0 firmware,+ath10k-board-qca99x0)\ndefine Package/ath10k-firmware-qca99x0/install\n\t$(INSTALL_DIR) $(1)/lib/firmware/ath10k/QCA99X0/hw2.0\n\t$(INSTALL_DATA) \\\n\t\t$(PKG_BUILD_DIR)/ath10k/QCA99X0/hw2.0/firmware-5.bin \\\n\t\t$(1)/lib/firmware/ath10k/QCA99X0/hw2.0/firmware-5.bin\nendef\n$(eval $(call BuildPackage,ath10k-firmware-qca99x0))\n\nPackage/ath10k-board-qca9984 = $(call Package/firmware-default,ath10k qca9984 board firmware)\ndefine Package/ath10k-board-qca9984/install\n\t$(INSTALL_DIR) $(1)/lib/firmware/ath10k/QCA9984/hw1.0\n\t$(INSTALL_DATA) \\\n\t\t$(PKG_BUILD_DIR)/ath10k/QCA9984/hw1.0/board-2.bin \\\n\t\t$(1)/lib/firmware/ath10k/QCA9984/hw1.0/board-2.bin\nendef\n$(eval $(call BuildPackage,ath10k-board-qca9984))\nPackage/ath10k-firmware-qca9984 = $(call Package/firmware-default,ath10k qca9984 firmware,+ath10k-board-qca9984)\ndefine Package/ath10k-firmware-qca9984/install\n\t$(INSTALL_DIR) $(1)/lib/firmware/ath10k/QCA9984/hw1.0\n\t$(INSTALL_DATA) \\\n\t\t$(PKG_BUILD_DIR)/ath10k/QCA9984/hw1.0/firmware-5.bin \\\n\t\t$(1)/lib/firmware/ath10k/QCA9984/hw1.0/firmware-5.bin\nendef\n$(eval $(call BuildPackage,ath10k-firmware-qca9984))\n"
  },
  {
    "path": "package/firmware/linux-firmware/realtek.mk",
    "content": "Package/r8152-firmware = $(call Package/firmware-default,RealTek RTL8152 firmware)\ndefine Package/r8152-firmware/install\n\t$(INSTALL_DIR) $(1)/lib/firmware/rtl_nic\n\t$(CP) \\\n\t\t$(PKG_BUILD_DIR)/rtl_nic/rtl8153* \\\n\t\t$(PKG_BUILD_DIR)/rtl_nic/rtl8156* \\\n\t\t$(1)/lib/firmware/rtl_nic\nendef\n$(eval $(call BuildPackage,r8152-firmware))\n\nPackage/r8169-firmware = $(call Package/firmware-default,RealTek RTL8169 firmware)\ndefine Package/r8169-firmware/install\n\t$(INSTALL_DIR) $(1)/lib/firmware/rtl_nic\n\t$(CP) \\\n\t\t$(PKG_BUILD_DIR)/rtl_nic/rtl810* \\\n\t\t$(PKG_BUILD_DIR)/rtl_nic/rtl8125* \\\n\t\t$(PKG_BUILD_DIR)/rtl_nic/rtl8168* \\\n\t\t$(PKG_BUILD_DIR)/rtl_nic/rtl84* \\\n\t\t$(1)/lib/firmware/rtl_nic\nendef\n$(eval $(call BuildPackage,r8169-firmware))\n\nPackage/rtl8188eu-firmware = $(call Package/firmware-default,RealTek RTL8188EU firmware)\ndefine Package/rtl8188eu-firmware/install\n\t$(INSTALL_DIR) $(1)/lib/firmware/rtlwifi\n\t$(CP) \\\n\t\t$(PKG_BUILD_DIR)/rtlwifi/rtl8188eufw.bin \\\n\t\t$(1)/lib/firmware/rtlwifi\nendef\n$(eval $(call BuildPackage,rtl8188eu-firmware))\n\nPackage/rtl8192ce-firmware = $(call Package/firmware-default,RealTek RTL8192CE firmware)\ndefine Package/rtl8192ce-firmware/install\n\t$(INSTALL_DIR) $(1)/lib/firmware/rtlwifi\n\t$(INSTALL_DATA) $(PKG_BUILD_DIR)/rtlwifi/rtl8192cfw.bin $(1)/lib/firmware/rtlwifi\n\t$(INSTALL_DATA) $(PKG_BUILD_DIR)/rtlwifi/rtl8192cfwU.bin $(1)/lib/firmware/rtlwifi\n\t$(INSTALL_DATA) $(PKG_BUILD_DIR)/rtlwifi/rtl8192cfwU_B.bin $(1)/lib/firmware/rtlwifi\nendef\n$(eval $(call BuildPackage,rtl8192ce-firmware))\n\nPackage/rtl8192cu-firmware = $(call Package/firmware-default,RealTek RTL8192CU firmware)\ndefine Package/rtl8192cu-firmware/install\n\t$(INSTALL_DIR) $(1)/lib/firmware/rtlwifi\n\t$(INSTALL_DATA) $(PKG_BUILD_DIR)/rtlwifi/rtl8192cufw.bin $(1)/lib/firmware/rtlwifi\n\t$(INSTALL_DATA) $(PKG_BUILD_DIR)/rtlwifi/rtl8192cufw_A.bin $(1)/lib/firmware/rtlwifi\n\t$(INSTALL_DATA) $(PKG_BUILD_DIR)/rtlwifi/rtl8192cufw_B.bin $(1)/lib/firmware/rtlwifi\n\t$(INSTALL_DATA) $(PKG_BUILD_DIR)/rtlwifi/rtl8192cufw_TMSC.bin $(1)/lib/firmware/rtlwifi\nendef\n$(eval $(call BuildPackage,rtl8192cu-firmware))\n\nPackage/rtl8192de-firmware = $(call Package/firmware-default,RealTek RTL8192DE firmware)\ndefine Package/rtl8192de-firmware/install\n\t$(INSTALL_DIR) $(1)/lib/firmware/rtlwifi\n\t$(INSTALL_DATA) $(PKG_BUILD_DIR)/rtlwifi/rtl8192defw.bin $(1)/lib/firmware/rtlwifi\nendef\n$(eval $(call BuildPackage,rtl8192de-firmware))\n\nPackage/rtl8192eu-firmware = $(call Package/firmware-default,RealTek RTL8192EU firmware)\ndefine Package/rtl8192eu-firmware/install\n\t$(INSTALL_DIR) $(1)/lib/firmware/rtlwifi\n\t$(INSTALL_DATA) $(PKG_BUILD_DIR)/rtlwifi/rtl8192eu_nic.bin $(1)/lib/firmware/rtlwifi\nendef\n$(eval $(call BuildPackage,rtl8192eu-firmware))\n\nPackage/rtl8192se-firmware = $(call Package/firmware-default,RealTek RTL8192SE firmware)\ndefine Package/rtl8192se-firmware/install\n\t$(INSTALL_DIR) $(1)/lib/firmware/rtlwifi\n\t$(INSTALL_DATA) $(PKG_BUILD_DIR)/rtlwifi/rtl8192sefw.bin $(1)/lib/firmware/rtlwifi\nendef\n$(eval $(call BuildPackage,rtl8192se-firmware))\n\nPackage/rtl8192su-firmware = $(call Package/firmware-default,RealTek RTL8192SU firmware)\ndefine Package/rtl8192su-firmware/install\n\t$(INSTALL_DIR) $(1)/lib/firmware/rtlwifi\n\t$(INSTALL_DATA) $(PKG_BUILD_DIR)/rtlwifi/rtl8712u.bin $(1)/lib/firmware/rtlwifi\nendef\n$(eval $(call BuildPackage,rtl8192su-firmware))\n\nPackage/rtl8723au-firmware = $(call Package/firmware-default,RealTek RTL8723AU firmware)\ndefine Package/rtl8723au-firmware/install\n\t$(INSTALL_DIR) $(1)/lib/firmware/rtlwifi\n\t$(INSTALL_DATA) $(PKG_BUILD_DIR)/rtlwifi/rtl8723aufw_A.bin $(1)/lib/firmware/rtlwifi\n\t$(INSTALL_DATA) $(PKG_BUILD_DIR)/rtlwifi/rtl8723aufw_B.bin $(1)/lib/firmware/rtlwifi\n\t$(INSTALL_DATA) $(PKG_BUILD_DIR)/rtlwifi/rtl8723aufw_B_NoBT.bin $(1)/lib/firmware/rtlwifi\nendef\n$(eval $(call BuildPackage,rtl8723au-firmware))\n\nPackage/rtl8723bu-firmware = $(call Package/firmware-default,RealTek RTL8723BU firmware)\ndefine Package/rtl8723bu-firmware/install\n\t$(INSTALL_DIR) $(1)/lib/firmware/rtlwifi\n\t$(INSTALL_DATA) $(PKG_BUILD_DIR)/rtlwifi/rtl8723bu_nic.bin $(1)/lib/firmware/rtlwifi\n\tln -s rtl8723bu_nic.bin $(1)/lib/firmware/rtlwifi/rtl8723bs_nic.bin\nendef\n$(eval $(call BuildPackage,rtl8723bu-firmware))\n\nPackage/rtl8821ae-firmware = $(call Package/firmware-default,RealTek RTL8821AE firmware)\ndefine Package/rtl8821ae-firmware/install\n\t$(INSTALL_DIR) $(1)/lib/firmware/rtlwifi\n\t$(INSTALL_DATA) $(PKG_BUILD_DIR)/rtlwifi/rtl8821aefw.bin $(1)/lib/firmware/rtlwifi\n\t$(INSTALL_DATA) $(PKG_BUILD_DIR)/rtlwifi/rtl8821aefw_wowlan.bin $(1)/lib/firmware/rtlwifi\nendef\n$(eval $(call BuildPackage,rtl8821ae-firmware))\n\nPackage/rtl8822be-firmware = $(call Package/firmware-default,RealTek RTL8822BE firmware)\ndefine Package/rtl8822be-firmware/install\n\t$(INSTALL_DIR) $(1)/lib/firmware/rtw88\n\t$(INSTALL_DATA) $(PKG_BUILD_DIR)/rtw88/rtw8822b_fw.bin $(1)/lib/firmware/rtw88\nendef\n$(eval $(call BuildPackage,rtl8822be-firmware))\n\nPackage/rtl8822ce-firmware = $(call Package/firmware-default,RealTek RTL8822CE firmware)\ndefine Package/rtl8822ce-firmware/install\n\t$(INSTALL_DIR) $(1)/lib/firmware/rtw88\n\t$(INSTALL_DATA) $(PKG_BUILD_DIR)/rtw88/rtw8822c_fw.bin $(1)/lib/firmware/rtw88\n\t$(INSTALL_DATA) $(PKG_BUILD_DIR)/rtw88/rtw8822c_wow_fw.bin $(1)/lib/firmware/rtw88\nendef\n$(eval $(call BuildPackage,rtl8822ce-firmware))\n"
  },
  {
    "path": "package/firmware/linux-firmware/rsi.mk",
    "content": "Package/rs9113-firmware = $(call Package/firmware-default,RedPine Signals rs9113 firmware)\ndefine Package/rs9113-firmware/install\n\t$(INSTALL_DIR) $(1)/lib/firmware/rsi\n\t$(INSTALL_DATA) $(PKG_BUILD_DIR)/rsi/rs9113_wlan_qspi.rps $(1)/lib/firmware/rsi\nendef\n$(eval $(call BuildPackage,rs9113-firmware))\n"
  },
  {
    "path": "package/firmware/linux-firmware/ti.mk",
    "content": "Package/wl12xx-firmware = $(call Package/firmware-default,TI WL12xx firmware)\ndefine Package/wl12xx-firmware/install\n\t$(INSTALL_DIR) $(1)/lib/firmware/ti-connectivity\n\t$(INSTALL_DATA) \\\n\t\t$(PKG_BUILD_DIR)/ti-connectivity/wl127x-fw-5-mr.bin \\\n\t\t$(PKG_BUILD_DIR)/ti-connectivity/wl127x-fw-5-plt.bin \\\n\t\t$(PKG_BUILD_DIR)/ti-connectivity/wl127x-fw-5-sr.bin \\\n\t\t$(PKG_BUILD_DIR)/ti-connectivity/wl127x-nvs.bin \\\n\t\t$(PKG_BUILD_DIR)/ti-connectivity/wl128x-fw-5-mr.bin \\\n\t\t$(PKG_BUILD_DIR)/ti-connectivity/wl128x-fw-5-plt.bin \\\n\t\t$(PKG_BUILD_DIR)/ti-connectivity/wl128x-fw-5-sr.bin \\\n\t\t$(PKG_BUILD_DIR)/ti-connectivity/wl128x-nvs.bin \\\n\t\t$(1)/lib/firmware/ti-connectivity\n\tln -s wl127x-nvs.bin $(1)/lib/firmware/ti-connectivity/wl1271-nvs.bin\nendef\n$(eval $(call BuildPackage,wl12xx-firmware))\n\nPackage/wl18xx-firmware = $(call Package/firmware-default,TI WL18xx firmware)\ndefine Package/wl18xx-firmware/install\n\t$(INSTALL_DIR) $(1)/lib/firmware/ti-connectivity\n\t$(INSTALL_DATA) \\\n\t\t$(PKG_BUILD_DIR)/ti-connectivity/wl18xx-fw-4.bin \\\n\t\t$(1)/lib/firmware/ti-connectivity\nendef\n$(eval $(call BuildPackage,wl18xx-firmware))\n\nPackage/ti-3410-firmware = $(call Package/firmware-default,TI 3410 firmware)\ndefine Package/ti-3410-firmware/install\n\t$(INSTALL_DIR) $(1)/lib/firmware\n\t$(INSTALL_DATA) $(PKG_BUILD_DIR)/ti_3410.fw $(1)/lib/firmware\nendef\n$(eval $(call BuildPackage,ti-3410-firmware))\n\nPackage/ti-5052-firmware = $(call Package/firmware-default,TI 5052 firmware)\ndefine Package/ti-5052-firmware/install\n\t$(INSTALL_DIR) $(1)/lib/firmware\n\t$(INSTALL_DATA) $(PKG_BUILD_DIR)/ti_5052.fw $(1)/lib/firmware\nendef\n$(eval $(call BuildPackage,ti-5052-firmware))\n"
  },
  {
    "path": "package/firmware/prism54-firmware/Makefile",
    "content": "#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=prism54-firmware\nPKG_RELEASE:=1\n\n# Prism54 FullMAC firmware (jbnore.free.fr seems to be rather slow, so we use daemonizer.de)\nPRG_URL:=https://daemonizer.de/prism54/prism54-fw/\n\ninclude $(INCLUDE_DIR)/package.mk\n\n\n# PRISM54/P54 firmwares\nPRISM54FW:=1.0.4.3.arm\nP54USBFW:=2.13.24.0.lm87.arm\nP54PCIFW:=2.13.12.0.arm\nP54SPIFW:=2.13.0.0.a.13.14.arm\n\ndefine Download/prism54-firmware\n  FILE:=$(PRISM54FW)\n  URL:=$(PRG_URL)/fw-fullmac\n  HASH:=dce24156c57234dba131429fbe8cd1de8ba818c9481ddc33cf7e5af9d57a737c\nendef\n$(eval $(call Download,prism54-firmware))\n\ndefine Download/p54-usb-firmware\n  FILE:=$(P54USBFW)\n  URL:=$(PRG_URL)/fw-usb\n  HASH:=b59793e00a042b2bd5e883a15847778db90f49a9a4bdd1368a6b4021e6c93979\nendef\n$(eval $(call Download,p54-usb-firmware))\n\ndefine Download/p54-pci-firmware\n  FILE:=$(P54PCIFW)\n  URL:=$(PRG_URL)/fw-softmac\n  HASH:=3e62fe0c55fe4138dd10ef8fe8b4841908609d2cb2386ef71d3d0508b627170b\nendef\n$(eval $(call Download,p54-pci-firmware))\n\ndefine Download/p54-spi-firmware\n  FILE:=$(P54SPIFW)\n  URL:=$(PRG_URL)/stlc4560\n  HASH:=7fffaceb008b9beb5a1da4744c9a6d31c8d9eff54e3461cba925785f2ae1648d\nendef\n$(eval $(call Download,p54-spi-firmware))\n\n\ndefine Package/prism54-firmware-default\n  SECTION:=firmware\n  CATEGORY:=Firmware\n  URL:=https://daemonizer.de/prism54/prism54-fw\nendef\n\ndefine Package/prism54-firmware\n$(Package/prism54-firmware-default)\n  TITLE:=prism54 firmware\nendef\n\ndefine Package/p54-usb-firmware\n$(Package/prism54-firmware-default)\n  TITLE:=p54-usb firmware\nendef\n\ndefine Package/p54-pci-firmware\n$(Package/prism54-firmware-default)\n  TITLE:=p54-pci firmware\nendef\n\ndefine Package/p54-spi-firmware\n$(Package/prism54-firmware-default)\n  TITLE:=p54-spi firmware\nendef\n\n\ndefine Build/Prepare\n\tmkdir -p $(PKG_BUILD_DIR)\nendef\n\ndefine Build/Compile\n\nendef\n\ndefine Package/prism54-firmware/install\n\t$(INSTALL_DIR) $(1)/lib/firmware\n\t$(INSTALL_DATA) $(DL_DIR)/$(PRISM54FW) $(1)/lib/firmware/isl3890\nendef\n\ndefine Package/p54-usb-firmware/install\n\t$(INSTALL_DIR) $(1)/lib/firmware\n\t$(INSTALL_DATA) $(DL_DIR)/$(P54USBFW) $(1)/lib/firmware/isl3887usb\nendef\n\ndefine Package/p54-pci-firmware/install\n\t$(INSTALL_DIR) $(1)/lib/firmware\n\t$(INSTALL_DATA) $(DL_DIR)/$(P54PCIFW) $(1)/lib/firmware/isl3886pci\nendef\n\ndefine Package/p54-spi-firmware/install\n\t$(INSTALL_DIR) $(1)/lib/firmware\n\t$(INSTALL_DATA) $(DL_DIR)/$(P54SPIFW) $(1)/lib/firmware/3826.arm\nendef\n\n\n$(eval $(call BuildPackage,prism54-firmware))\n$(eval $(call BuildPackage,p54-usb-firmware))\n$(eval $(call BuildPackage,p54-pci-firmware))\n$(eval $(call BuildPackage,p54-spi-firmware))\n"
  },
  {
    "path": "package/firmware/wireless-regdb/Makefile",
    "content": "include $(TOPDIR)/rules.mk\n\nPKG_NAME:=wireless-regdb\nPKG_VERSION:=2022.02.18\nPKG_RELEASE:=1\n\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz\nPKG_SOURCE_URL:=@KERNEL/software/network/wireless-regdb/\nPKG_HASH:=8828c25a4ee25020044004f57374bb9deac852809fad70f8d3d01770bf9ac97f\n\nPKG_MAINTAINER:=Felix Fietkau <nbd@nbd.name>\n\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine Package/wireless-regdb\n  PKGARCH:=all\n  SECTION:=firmware\n  CATEGORY:=Firmware\n  URL:=https://git.kernel.org/pub/scm/linux/kernel/git/sforshee/wireless-regdb.git/\n  TITLE:=Wireless Regulatory Database\nendef\n\ndefine Build/Compile\n\t$(STAGING_DIR_HOST)/bin/$(PYTHON) $(PKG_BUILD_DIR)/db2fw.py $(PKG_BUILD_DIR)/regulatory.db $(PKG_BUILD_DIR)/db.txt\nendef\n\ndefine Package/wireless-regdb/install\n\t$(INSTALL_DIR) $(1)/lib/firmware\n\t$(CP) $(PKG_BUILD_DIR)/regulatory.db $(1)/lib/firmware/\nendef\n\n$(eval $(call BuildPackage,wireless-regdb))\n"
  },
  {
    "path": "package/firmware/wireless-regdb/patches/500-world-regd-5GHz.patch",
    "content": "Remove the NO-IR flag from channels 36-48 on the World domain,\nto make it usable for AP mode.\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n--- a/db.txt\n+++ b/db.txt\n@@ -16,7 +16,7 @@ country 00:\n \t# Channel 14. Only JP enables this and for 802.11b only\n \t(2474 - 2494 @ 20), (20), NO-IR, NO-OFDM\n \t# Channel 36 - 48\n-\t(5170 - 5250 @ 80), (20), NO-IR, AUTO-BW\n+\t(5170 - 5250 @ 80), (20), AUTO-BW\n \t# Channel 52 - 64\n \t(5250 - 5330 @ 80), (20), NO-IR, DFS, AUTO-BW\n \t# Channel 100 - 144\n"
  },
  {
    "path": "package/kernel/acx-mac80211/Makefile",
    "content": "#\n# Copyright (C) 2007-2012 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\ninclude $(INCLUDE_DIR)/kernel.mk\n\nPKG_NAME:=acx-mac80211\nPKG_RELEASE:=1\n\nPKG_SOURCE_URL:=http://git.code.sf.net/p/acx100/acx-mac80211\nPKG_SOURCE_PROTO:=git\nPKG_SOURCE_DATE:=2014-02-16\nPKG_SOURCE_VERSION:=b6fc31491020cb01d2cd1acc170cfa03ced7e726\nPKG_MIRROR_HASH:=58590245715f0e5fb4b57aab6d91071dfb6a97d3273f5aee0b97b1edee030ed0\n\nPKG_CONFIG_DEPENDS:= \\\n\tCONFIG_PACKAGE_MAC80211_DEBUGFS \\\n\tCONFIG_PACKAGE_MAC80211_MESH \\\n\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine KernelPackage/acx-mac80211\n  SUBMENU:=Wireless Drivers\n  TITLE:=ACX1xx mac80211 driver\n  DEPENDS:=@PCI_SUPPORT @mipsel +kmod-mac80211\n  FILES:=$(PKG_BUILD_DIR)/acx-mac80211.ko\n  AUTOLOAD:=$(call AutoProbe,acx-mac80211)\n  MENU:=1\nendef\n\ndefine KernelPackage/acx-mac80211/config\n\tmenu \"Configuration\"\n\t\tdepends on PACKAGE_kmod-acx-mac80211\n\n\tconfig ACX_ID_0D\n\t\tbool \"ACX1xx Radio ID 0D firmware\"\n\t\thelp\n\t\t  Download and install firmware for:\n\t\t    ACX1xx cards with Radio ID 0D into /lib/firmware.\n\n\tconfig ACX_ID_11\n\t\tbool \"ACX1xx Radio ID 11 firmware\"\n\t\thelp\n\t\t  Download and install firmware for:\n\t\t    ACX1xx cards with Radio ID 11 into /lib/firmware.\n\n\tconfig ACX_ID_15\n\t\tbool \"ACX1xx Radio ID 15 firmware\"\n\t\thelp\n\t\t  Download and install firmware for:\n\t\t    ACX1xx cards with Radio ID 15 into /lib/firmware.\n\n\tconfig ACX_ID_16\n\t\tbool \"ACX1xx Radio ID 16 firmware\"\n\t\tdefault y\n\t\thelp\n\t\t  Download and install firmware for:\n\t\t    ACX1xx cards with Radio ID 16 into /lib/firmware.\n\n\tchoice\n\t\tprompt \"ACX111 firmware version\"\n\t\tdepends on ACX_ID_16\n\t\tdefault ACX_DEFAULT\n\t\thelp\n\t\t  This option allows you to select the version of the acx firmware.\n\n\tconfig ACX_DEFAULT\n\t\tbool \"Default\"\n\t\thelp\n\t\t  Default firmware for ACX111 devices.\n\n\t\t  If unsure, select this.\n\n\tconfig ACX_1_2_1_34\n\t\tbool \"1.2.1_34\"\n\t\thelp\n\t\t  1.2.1_34 firmware for ACX111 devices. Works with Zyxel P-334WT.\n\n\t\t  If unsure, select the \"default\" firmware.\n\n\tendchoice\n\n\tconfig ACX_ID_17\n\t\tbool \"ACX1xx Radio ID 17 firmware\"\n\t\thelp\n\t\t  Download and install firmware for:\n\t\t    ACX1xx cards with Radio ID 17 into /lib/firmware.\n\n\tconfig ACX_ID_19\n\t\tbool \"ACX1xx Radio ID 19 firmware\"\n\t\tdefault y\n\t\thelp\n\t\t  Download and install firmware for:\n\t\t    ACX1xx cards with Radio ID 19 into /lib/firmware.\n\n\tconfig ACX_ID_1B\n\t\tbool \"ACX1xx Radio ID 1B firmware\"\n\t\thelp\n\t\t  Download and install firmware for:\n\t\t    ACX1xx cards with Radio ID 1b into /lib/firmware.\n\n\tendmenu\nendef\n\ndefine KernelPackage/acx-mac80211/description\n\tDriver for acx111 cards (mac80211 version)\nendef\n\ndefine Download/tiacx100\n\tFILE:=tiacx100\n\tURL:=@OPENWRT\n\tHASH:=4f05913c940c2455b267545b12d93ad81fa5eebb0cbee22a2c7588c50525b4f0\nendef\n\ndefine Download/tiacx100r0d\n\tFILE:=tiacx100r0D\n\tURL:=@OPENWRT\n\tHASH:=6a4a7fbb24a328a88261bc2a507b2a0bf63c91e831e3f1a8caa4f6599b2215e6\nendef\n\ndefine Download/tiacx100r11\n\tFILE:=tiacx100r11\n\tURL:=@OPENWRT\n\tHASH:=e005a93a0b463e01edba2b79038b54c29a7932efee61c851a2ac644b8a4e5dd4\nendef\n\ndefine Download/tiacx100r15\n\tFILE:=tiacx100r15\n\tURL:=@OPENWRT\n\tHASH:=c6f40bead5ef45720e2d72bbe4d998367c2c7857eb7716234aedeb2ad98bcdde\nendef\n\ndefine Download/tiacx111c16\n\tFILE:=tiacx111c16\n\tURL:=@OPENWRT\n\tHASH:=cc6108d577ebc55b924ff6bab44eeee3456d284c63819277cb5460338b2f1bd7\nendef\n\ndefine Download/tiacx111c16_1\n\tFILE:=tiacx111c16_1.2.1_34\n\tURL:=@OPENWRT\n\tHASH:=672ed9d02565ab44da450c52f0ced3be99a3a3901f73454455da8e1f98ada220\nendef\n\ndefine Download/tiacx111c17\n\tFILE:=tiacx111c17\n\tURL:=@OPENWRT\n\tHASH:=2bb900a5886dbea2d3504623d9f3ac8abbb2e9fdfcf0fe233e77951dff748a40\nendef\n\ndefine Download/tiacx111c19\n\tFILE:=tiacx111c19\n\tURL:=@OPENWRT\n\tHASH:=383d86a8cfddf92400d661b4e43a9b855350fa656edd4f75b4aff7fab2d00e90\nendef\n\ndefine Download/tiacx111usbc1b\n\tFILE:=tiacx111usbc1B\n\tURL:=@OPENWRT\n\tHASH:=f3c9e574de7073014ab6eef9a0f6412c53ae521b67723360af753c41401ed4d5\nendef\n\nPKG_EXTRA_KCONFIG:= \\\n\tCONFIG_ACX_MAC80211=m \\\n\tCONFIG_ACX_MAC80211_PCI=m \\\n\nPKG_EXTRA_CFLAGS:= \\\n\t$(patsubst CONFIG_%, -DCONFIG_%=1, $(patsubst %=m,%,$(filter %=m,$(PKG_EXTRA_KCONFIG)))) \\\n\t$(patsubst CONFIG_%, -DCONFIG_%=1, $(patsubst %=y,%,$(filter %=y,$(PKG_EXTRA_KCONFIG)))) \\\n\t$(if $(CONFIG_LEDS_TRIGGERS), -DCONFIG_MAC80211_LEDS -DCONFIG_LEDS_TRIGGERS) \\\n\t$(if $(CONFIG_PACKAGE_MAC80211_DEBUGFS), -DCONFIG_CFG80211_DEBUGFS -DCONFIG_MAC80211_DEBUGFS) \\\n\t$(if $(CONFIG_PACKAGE_MAC80211_MESH), -DCONFIG_MAC80211_MESH) \\\n\t-DBACKPORTED_KERNEL_NAME=\\\\\\\"$(PKG_SOURCE)\\\\\\\" \\\n\t-DBACKPORTED_KERNEL_VERSION=\\\\\\\"$(PKG_SOURCE_VERSION)\\\\\\\" \\\n\t-DBACKPORTS_VERSION=\\\\\\\"unknown\\\\\\\" \\\n\ndefine Build/Compile\n\t$(MAKE) -C \"$(LINUX_DIR)\" \\\n\t\t$(KERNEL_MAKE_FLAGS) \\\n\t\tM=\"$(PKG_BUILD_DIR)\" \\\n\t\t$(PKG_EXTRA_KCONFIG) \\\n\t\tEXTRA_CFLAGS=\"$(PKG_EXTRA_CFLAGS) -DCONFIG_ACX_MAC80211_VERSION=\\\"KERNEL_VERSION(4,2,0)\\\"\" \\\n\t\tLINUXINCLUDE=\"-I$(STAGING_DIR)/usr/include/mac80211-backport/uapi -I$(STAGING_DIR)/usr/include/mac80211-backport \\\n\t\t\t-I$(STAGING_DIR)/usr/include/mac80211/uapi -I$(STAGING_DIR)/usr/include/mac80211 \\\n\t\t\t-I$(LINUX_DIR)/include -I$(LINUX_DIR)/include/$(LINUX_UAPI_DIR) \\\n\t\t\t-I$(LINUX_DIR)/include/generated/uapi/ -Iarch/$(LINUX_KARCH)/include \\\n\t\t\t-Iarch/$(LINUX_KARCH)/include/$(LINUX_UAPI_DIR) \\\n\t\t\t-Iarch/$(LINUX_KARCH)/include/generated \\\n\t\t\t-Iarch/$(LINUX_KARCH)/include/generated/$(LINUX_UAPI_DIR) \\\n\t\t\t-include generated/autoconf.h \\\n\t\t\t-include backport/backport.h \" \\\n\t\tV=\"$(V)\" \\\n\t\tmodules\nendef\n\ndefine Build/Configure\nendef\n\ndefine KernelPackage/acx-mac80211/install\n\t$(INSTALL_DIR) $(1)/lib/firmware\n\nifneq ($(CONFIG_ACX_ID_0D)$(CONFIG_ACX_ID_11)$(CONFIG_ACX_ID_15),)\n\t$(INSTALL_DATA) $(DL_DIR)/tiacx100 $(1)/lib/firmware/\nendif\n\nifneq ($(CONFIG_ACX_ID_0D),)\n\t$(INSTALL_DATA) $(DL_DIR)/tiacx100r0D $(1)/lib/firmware/\nendif\n\nifneq ($(CONFIG_ACX_ID_11),)\n\t$(INSTALL_DATA) $(DL_DIR)/tiacx100r11 $(1)/lib/firmware/\nendif\n\nifneq ($(CONFIG_ACX_ID_15),)\n\t$(INSTALL_DATA) $(DL_DIR)/tiacx100r15 $(1)/lib/firmware/\nendif\n\nifneq ($(CONFIG_ACX_DEFAULT),)\n\t$(INSTALL_DATA) $(DL_DIR)/tiacx111c16 $(1)/lib/firmware/\nendif\n\nifneq ($(CONFIG_ACX_1_2_1_34),)\n\t$(INSTALL_DATA)\t$(DL_DIR)/tiacx111c16_1.2.1_34 $(1)/lib/firmware/tiacx111c16\nendif\n\nifneq ($(CONFIG_ACX_ID_17),)\n\t$(INSTALL_DATA) $(DL_DIR)/tiacx111c17 $(1)/lib/firmware/\nendif\n\nifneq ($(CONFIG_ACX_ID_19),)\n\t$(INSTALL_DATA) $(DL_DIR)/tiacx111c19 $(1)/lib/firmware/\nendif\n\nifneq ($(CONFIG_ACX_ID_1B),)\n\t$(INSTALL_DATA) $(DL_DIR)/tiacx111usbc1B $(1)/lib/firmware/\nendif\n\nendef\n\n$(eval $(call KernelPackage,acx-mac80211))\n$(eval $(call Download,tiacx100))\n$(eval $(call Download,tiacx100r0d))\n$(eval $(call Download,tiacx100r11))\n$(eval $(call Download,tiacx100r15))\n$(eval $(call Download,tiacx111c16))\n$(eval $(call Download,tiacx111c16_1))\n$(eval $(call Download,tiacx111c17))\n$(eval $(call Download,tiacx111c19))\n$(eval $(call Download,tiacx111usbc1b))\n"
  },
  {
    "path": "package/kernel/acx-mac80211/patches/100-compat.patch",
    "content": "diff --git a/pci.c b/pci.c\nindex ae07f5a..72d542f 100644\n--- a/pci.c\n+++ b/pci.c\n@@ -1495,7 +1495,11 @@ static struct acxpci_device_info acxpci_info_tbl[] __devinitdata = {\n #endif\n \n #ifdef CONFIG_PCI\n+#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 8, 0)\n static DEFINE_PCI_DEVICE_TABLE(acxpci_id_tbl) = {\n+#else\n+static const struct pci_device_id acxpci_id_tbl[] = {\n+#endif\n \t{ PCI_VDEVICE(TI, PCI_DEVICE_ID_TI_TNETW1100A),\n \t  .driver_data = CHIPTYPE_ACX100,\n \t},\n"
  },
  {
    "path": "package/kernel/acx-mac80211/patches/200-initial-macaddr.patch",
    "content": "--- a/cardsetting.c\n+++ b/cardsetting.c\n@@ -715,10 +715,25 @@ int acx1xx_get_station_id(acx_device_t *\n \tu8 *stationID = adev->ie_cmd_buf;\n \tconst u8 *paddr;\n \tint i, res;\n+\tconst char *prom_addr;\n+\tchar *prom_getenv(const char *name);\n \n \tres = acx_interrogate(adev, stationID, ACX1xx_IE_DOT11_STATION_ID);\n \tpaddr = &stationID[4];\n-\tfor (i = 0; i < ETH_ALEN; i++) {\n+\tprom_addr = NULL;\n+#ifdef CONFIG_VLYNQ\n+\tprom_addr = prom_getenv(\"macwlan\");\n+\tif (prom_addr == NULL)\n+\t\tprom_addr = prom_getenv(\"mac_ap\");\n+#endif\n+\tif (prom_addr)\n+\t\tsscanf(prom_addr, \"%hhx:%hhx:%hhx:%hhx:%hhx:%hhx\", adev->dev_addr,\n+\t\t\t\tadev->dev_addr + 1,\n+\t\t\t\tadev->dev_addr + 2,\n+\t\t\t\tadev->dev_addr + 3,\n+\t\t\t\tadev->dev_addr + 4,\n+\t\t\t\tadev->dev_addr + 5);\n+\telse for (i = 0; i < ETH_ALEN; i++) {\n \t\t/* we copy the MAC address (reversed in the card) to\n \t\t * the netdevice's MAC address, and on ifup it will be\n \t\t * copied into iwadev->dev_addr */\n"
  },
  {
    "path": "package/kernel/acx-mac80211/patches/300-api_sync.patch",
    "content": "--- a/main.c\n+++ b/main.c\n@@ -497,7 +497,7 @@ int acx_free_mechanics(acx_device_t *ade\n \n int acx_init_ieee80211(acx_device_t *adev, struct ieee80211_hw *hw)\n {\n-\thw->flags &= ~IEEE80211_HW_RX_INCLUDES_FCS;\n+\t__clear_bit(IEEE80211_HW_RX_INCLUDES_FCS, hw->flags);\n \thw->queues = 1;\n \thw->wiphy->max_scan_ssids = 1;\n \n@@ -525,14 +525,14 @@ int acx_init_ieee80211(acx_device_t *ade\n \t/* We base signal quality on winlevel approach of previous driver\n \t * TODO OW 20100615 This should into a common init code\n \t */\n-\thw->flags |= IEEE80211_HW_SIGNAL_UNSPEC;\n+\t__set_bit(IEEE80211_HW_SIGNAL_UNSPEC, hw->flags);\n \thw->max_signal = 100;\n \n \tif (IS_ACX100(adev)) {\n-\t\tadev->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =\n+\t\tadev->hw->wiphy->bands[NL80211_BAND_2GHZ] =\n \t\t\t&acx100_band_2GHz;\n \t} else if (IS_ACX111(adev))\n-\t\tadev->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =\n+\t\tadev->hw->wiphy->bands[NL80211_BAND_2GHZ] =\n \t\t\t&acx111_band_2GHz;\n \telse {\n \t\tlog(L_ANY, \"Error: Unknown device\");\n@@ -945,8 +945,8 @@ void acx_op_configure_filter(struct ieee\n \t\tchanged_flags, *total_flags);\n \n \t/* OWI TODO: Set also FIF_PROBE_REQ ? */\n-\t*total_flags &= (FIF_PROMISC_IN_BSS | FIF_ALLMULTI | FIF_FCSFAIL\n-\t\t\t| FIF_CONTROL | FIF_OTHER_BSS);\n+\t*total_flags &= (FIF_ALLMULTI | FIF_FCSFAIL | FIF_CONTROL\n+\t\t\t| FIF_OTHER_BSS);\n \n \tlogf1(L_DEBUG, \"2: *total_flags=0x%08x\\n\", *total_flags);\n \n@@ -1045,9 +1045,10 @@ void acx_op_tx(struct ieee80211_hw *hw,\n }\n \n int acx_op_hw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif,\n-                   struct cfg80211_scan_request *req)\n+                   struct ieee80211_scan_request *hw_req)\n {\n \tacx_device_t *adev = hw2adev(hw);\n+\tstruct cfg80211_scan_request *req = &hw_req->req;\n \tstruct sk_buff *skb;\n \tsize_t ssid_len = 0;\n \tu8 *ssid = NULL;\n@@ -1082,7 +1083,7 @@ int acx_op_hw_scan(struct ieee80211_hw *\n \t\tgoto out;\n \t}\n #else\n-\tskb = ieee80211_probereq_get(adev->hw, adev->vif, ssid, ssid_len,\n+\tskb = ieee80211_probereq_get(adev->hw, vif->addr, ssid, ssid_len,\n \t\treq->ie_len);\n \tif (!skb) {\n \t\tret = -ENOMEM;\n--- a/main.h\n+++ b/main.h\n@@ -62,7 +62,7 @@ void acx_op_tx(struct ieee80211_hw *hw,\n #endif\n \n int acx_op_hw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif,\n-                   struct cfg80211_scan_request *req);\n+                   struct ieee80211_scan_request *req);\n \n int acx_recover_hw(acx_device_t *adev);\n \n--- a/cardsetting.c\n+++ b/cardsetting.c\n@@ -159,7 +159,7 @@ int acx_set_channel(acx_device_t *adev,\n \tint res = 0;\n \n \tadev->rx_status.freq = freq;\n-\tadev->rx_status.band = IEEE80211_BAND_2GHZ;\n+\tadev->rx_status.band = NL80211_BAND_2GHZ;\n \n \tadev->channel = channel;\n \n--- a/merge.c\n+++ b/merge.c\n@@ -2776,7 +2776,10 @@ void acx_irq_work(struct work_struct *wo\n \t\t/* HOST_INT_SCAN_COMPLETE */\n \t\tif (irqmasked & HOST_INT_SCAN_COMPLETE) {\n \t\t\tif (test_bit(ACX_FLAG_SCANNING, &adev->flags)) {\n-\t\t\t\tieee80211_scan_completed(adev->hw, false);\n+\t\t\t\tstruct cfg80211_scan_info info = {\n+\t\t\t\t\t.aborted = false\n+\t\t\t\t};\n+\t\t\t\tieee80211_scan_completed(adev->hw, &info);\n \t\t\t\tlog(L_INIT, \"scan completed\\n\");\n \t\t\t\tclear_bit(ACX_FLAG_SCANNING, &adev->flags);\n \t\t\t}\n@@ -3138,10 +3141,13 @@ int acx_op_start(struct ieee80211_hw *hw\n \n void acx_stop(acx_device_t *adev)\n {\n+\tstruct cfg80211_scan_info info = {\n+\t\t.aborted = true\n+\t};\n \tacxmem_lock_flags;\n \n \tif (test_bit(ACX_FLAG_SCANNING, &adev->flags)) {\n-\t\tieee80211_scan_completed(adev->hw, true);\n+\t\tieee80211_scan_completed(adev->hw, &info);\n \t\tacx_issue_cmd(adev, ACX1xx_CMD_STOP_SCAN, NULL, 0);\n \t\tclear_bit(ACX_FLAG_SCANNING, &adev->flags);\n \t}\n"
  },
  {
    "path": "package/kernel/ath10k-ct/Makefile",
    "content": "include $(TOPDIR)/rules.mk\n\nPKG_NAME:=ath10k-ct\nPKG_RELEASE:=$(AUTORELEASE)\n\nPKG_LICENSE:=GPLv2\nPKG_LICENSE_FILES:=\n\nPKG_SOURCE_URL:=https://github.com/greearb/ath10k-ct.git\nPKG_SOURCE_PROTO:=git\nPKG_SOURCE_DATE:=2021-11-28\nPKG_SOURCE_VERSION:=dc350bbf41d987c5b2db54405bcc9ef3cd66d5db\nPKG_MIRROR_HASH:=92422485c7b92be840a40bf8d157bb6731d14d3811907b6cb4e4cfab0777b60d\n\n# Build the 5.15 ath10k-ct driver version.\n# Probably this should match as closely as\n# possible to whatever mac80211 backports version is being used.\nCT_KVER=\"-5.15\"\n\nPKG_MAINTAINER:=Ben Greear <greearb@candelatech.com>\nPKG_BUILD_PARALLEL:=1\nPKG_EXTMOD_SUBDIRS:=ath10k$(CT_KVER)\n\nSTAMP_CONFIGURED_DEPENDS := $(STAGING_DIR)/usr/include/mac80211-backport/backport/autoconf.h\n\ninclude $(INCLUDE_DIR)/kernel.mk\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine KernelPackage/ath10k-ct\n  SUBMENU:=Wireless Drivers\n  TITLE:=ath10k-ct driver optimized for CT ath10k firmware\n  DEPENDS:=+kmod-mac80211 +kmod-ath +@DRIVER_11N_SUPPORT +@DRIVER_11AC_SUPPORT @PCI_SUPPORT +kmod-hwmon-core\n  FILES:=\\\n\t$(PKG_BUILD_DIR)/ath10k$(CT_KVER)/ath10k_pci.ko \\\n\t$(PKG_BUILD_DIR)/ath10k$(CT_KVER)/ath10k_core.ko\n  AUTOLOAD:=$(call AutoProbe,ath10k_pci)\n  PROVIDES:=kmod-ath10k\n  VARIANT:=regular\nendef\n\ndefine KernelPackage/ath10k-ct/config\n\n       config ATH10K-CT_LEDS\n               bool \"Enable LED support\"\n               default y\n               depends on PACKAGE_kmod-ath10k-ct || PACKAGE_kmod-ath10k-ct-smallbuffers\nendef\n\ndefine KernelPackage/ath10k-ct-smallbuffers\n$(call KernelPackage/ath10k-ct)\n  TITLE+= (small buffers for low-RAM devices)\n  VARIANT:=smallbuffers\nendef\n\nNOSTDINC_FLAGS := \\\n\t$(KERNEL_NOSTDINC_FLAGS) \\\n\t-I$(PKG_BUILD_DIR) \\\n\t-I$(STAGING_DIR)/usr/include/mac80211-backport/uapi \\\n\t-I$(STAGING_DIR)/usr/include/mac80211-backport \\\n\t-I$(STAGING_DIR)/usr/include/mac80211/uapi \\\n\t-I$(STAGING_DIR)/usr/include/mac80211 \\\n\t-include backport/autoconf.h \\\n\t-include backport/backport.h\n\nifdef CONFIG_PACKAGE_MAC80211_MESH\n  NOSTDINC_FLAGS += -DCONFIG_MAC80211_MESH\nendif\n\nCT_MAKEDEFS += CONFIG_ATH10K=m CONFIG_ATH10K_PCI=m CONFIG_ATH10K_CE=y\n\n# This AHB logic is needed for IPQ4019 radios\nCT_MAKEDEFS += CONFIG_ATH10K_AHB=m\nNOSTDINC_FLAGS += -DCONFIG_ATH10K_AHB\n\nNOSTDINC_FLAGS += -DSTANDALONE_CT\n\nifdef CONFIG_PACKAGE_MAC80211_DEBUGFS\n  CT_MAKEDEFS += CONFIG_ATH10K_DEBUGFS=y CONFIG_MAC80211_DEBUGFS=y\n  NOSTDINC_FLAGS += -DCONFIG_MAC80211_DEBUGFS\n  NOSTDINC_FLAGS += -DCONFIG_ATH10K_DEBUGFS\nendif\n\nifdef CONFIG_PACKAGE_ATH_DEBUG\n  NOSTDINC_FLAGS += -DCONFIG_ATH10K_DEBUG\nendif\n\nifdef CONFIG_PACKAGE_ATH_DFS\n  NOSTDINC_FLAGS += -DCONFIG_ATH10K_DFS_CERTIFIED\nendif\n\nifdef CONFIG_PACKAGE_ATH_SPECTRAL\n  CT_MAKEDEFS += CONFIG_ATH10K_SPECTRAL=y\n  NOSTDINC_FLAGS += -DCONFIG_ATH10K_SPECTRAL\nendif\n\nifeq ($(CONFIG_ATH10K-CT_LEDS),y)\n  CT_MAKEDEFS += CONFIG_ATH10K_LEDS=y\n  NOSTDINC_FLAGS += -DCONFIG_ATH10K_LEDS\nendif\n\nifeq ($(BUILD_VARIANT),smallbuffers)\n  NOSTDINC_FLAGS += -DCONFIG_ATH10K_SMALLBUFFERS\nendif\n\ndefine Build/Configure\n\tcp $(STAGING_DIR)/usr/include/mac80211/ath/*.h $(PKG_BUILD_DIR)\nendef\n\nifneq ($(findstring c,$(OPENWRT_VERBOSE)),)\n  CT_MAKEDEFS += V=1\nendif\n\ndefine Build/Compile\n\t+$(MAKE) $(CT_MAKEDEFS) $(PKG_JOBS) -C \"$(LINUX_DIR)\" \\\n\t\t$(KERNEL_MAKE_FLAGS) \\\n\t\tM=\"$(PKG_BUILD_DIR)/ath10k$(CT_KVER)\" \\\n\t\tNOSTDINC_FLAGS=\"$(NOSTDINC_FLAGS)\" \\\n\t\tmodules\nendef\n\n$(eval $(call KernelPackage,ath10k-ct))\n$(eval $(call KernelPackage,ath10k-ct-smallbuffers))\n"
  },
  {
    "path": "package/kernel/ath10k-ct/patches/120-ath10k-fetch-calibration-data-via-nvmem-subsystem.patch",
    "content": "From e2333703373e8b81294da5d1c73c30154f75b082 Mon Sep 17 00:00:00 2001\nFrom: Christian Lamparter <chunkeey@gmail.com>\nDate: Fri, 15 Oct 2021 18:56:33 +0200\nSubject: [PATCH] ath10k: fetch (pre-)calibration data via nvmem subsystem\n\nOn most embedded ath10k devices (like range extenders,\nrouters, accesspoints, ...) the calibration data is\nstored in a easily accessible MTD partitions named\n\"ART\", \"caldata\", \"calibration\", etc...\n\nSince commit 4b361cfa8624 (\"mtd: core: add OTP nvmem provider support\"):\nMTD partitions and portions of them can be specified\nas potential nvmem-cells which are accessible through\nthe nvmem subsystem.\n\nThis feature - together with an nvmem cell definition either\nin the platform data or via device-tree allows drivers to get\nthe (pre-)calibration data which is required for initializing\nthe WIFI.\n\nTested with Netgear EX6150v2 (IPQ4018)\n\nCc: Robert Marko <robimarko@gmail.com>\nCc: Thibaut Varene <hacks@slashdirt.org>\nSigned-off-by: Christian Lamparter <chunkeey@gmail.com>\n---\n--- a/ath10k-5.15/core.c\n+++ b/ath10k-5.15/core.c\n@@ -13,6 +13,7 @@\n #include <linux/dmi.h>\n #include <linux/ctype.h>\n #include <linux/pm_qos.h>\n+#include <linux/nvmem-consumer.h>\n #include <asm/byteorder.h>\n #include <linux/ctype.h>\n \n@@ -988,7 +989,8 @@ static int ath10k_core_get_board_id_from\n \t}\n \n \tif (ar->cal_mode == ATH10K_PRE_CAL_MODE_DT ||\n-\t    ar->cal_mode == ATH10K_PRE_CAL_MODE_FILE)\n+\t    ar->cal_mode == ATH10K_PRE_CAL_MODE_FILE ||\n+\t    ar->cal_mode == ATH10K_PRE_CAL_MODE_NVMEM)\n \t\tbmi_board_id_param = BMI_PARAM_GET_FLASH_BOARD_ID;\n \telse\n \t\tbmi_board_id_param = BMI_PARAM_GET_EEPROM_BOARD_ID;\n@@ -2087,7 +2089,8 @@ static int ath10k_download_and_run_otp(s\n \n \t/* As of now pre-cal is valid for 10_4 variants */\n \tif (ar->cal_mode == ATH10K_PRE_CAL_MODE_DT ||\n-\t    ar->cal_mode == ATH10K_PRE_CAL_MODE_FILE)\n+\t    ar->cal_mode == ATH10K_PRE_CAL_MODE_FILE ||\n+\t    ar->cal_mode == ATH10K_PRE_CAL_MODE_NVMEM)\n \t\tbmi_otp_exe_param = BMI_PARAM_FLASH_SECTION_ALL;\n \n \tret = ath10k_bmi_execute(ar, address, bmi_otp_exe_param, &result);\n@@ -2221,6 +2224,39 @@ struct ath10k_bss_rom_ie {\n \t__le32 rom_len;\n } __packed;\n \n+static int ath10k_download_cal_nvmem(struct ath10k *ar, const char *cell_name)\n+{\n+\tstruct nvmem_cell *cell;\n+\tvoid *buf;\n+\tsize_t len;\n+\tint ret;\n+\n+\tcell = devm_nvmem_cell_get(ar->dev, cell_name);\n+\tif (IS_ERR(cell)) {\n+\t\tret = PTR_ERR(cell);\n+\t\treturn ret;\n+\t}\n+\n+\tbuf = nvmem_cell_read(cell, &len);\n+\tif (IS_ERR(buf))\n+\t\treturn PTR_ERR(buf);\n+\n+\tif (ar->hw_params.cal_data_len != len) {\n+\t\tkfree(buf);\n+\t\tath10k_warn(ar, \"invalid calibration data length in nvmem-cell '%s': %zu != %u\\n\",\n+\t\t\t    cell_name, len, ar->hw_params.cal_data_len);\n+\t\treturn -EMSGSIZE;\n+\t}\n+\n+\tret = ath10k_download_board_data(ar, buf, len);\n+\tkfree(buf);\n+\tif (ret)\n+\t\tath10k_warn(ar, \"failed to download calibration data from nvmem-cell '%s': %d\\n\",\n+\t\t\t    cell_name, ret);\n+\n+\treturn ret;\n+}\n+\n int ath10k_core_fetch_firmware_api_n(struct ath10k *ar, const char *name,\n \t\t\t\t     struct ath10k_fw_file *fw_file)\n {\n@@ -2597,6 +2633,18 @@ static int ath10k_core_pre_cal_download(\n {\n \tint ret;\n \n+\tret = ath10k_download_cal_nvmem(ar, \"pre-calibration\");\n+\tif (ret == 0) {\n+\t\tar->cal_mode = ATH10K_PRE_CAL_MODE_NVMEM;\n+\t\tgoto success;\n+\t} else if (ret == -EPROBE_DEFER) {\n+\t\treturn ret;\n+\t}\n+\n+\tath10k_dbg(ar, ATH10K_DBG_BOOT,\n+\t\t   \"boot did not find a pre-calibration nvmem-cell, try file next: %d\\n\",\n+\t\t   ret);\n+\n \tret = ath10k_download_cal_file(ar, ar->pre_cal_file);\n \tif (ret == 0) {\n \t\tar->cal_mode = ATH10K_PRE_CAL_MODE_FILE;\n@@ -2663,6 +2711,18 @@ static int ath10k_download_cal_data(stru\n \t\t   \"pre cal download procedure failed, try cal file: %d\\n\",\n \t\t   ret);\n \n+\tret = ath10k_download_cal_nvmem(ar, \"calibration\");\n+\tif (ret == 0) {\n+\t\tar->cal_mode = ATH10K_CAL_MODE_NVMEM;\n+\t\tgoto done;\n+\t} else if (ret == -EPROBE_DEFER) {\n+\t\treturn ret;\n+\t}\n+\n+\tath10k_dbg(ar, ATH10K_DBG_BOOT,\n+\t\t   \"boot did not find a calibration nvmem-cell, try file next: %d\\n\",\n+\t\t   ret);\n+\n \tret = ath10k_download_cal_file(ar, ar->cal_file);\n \tif (ret == 0) {\n \t\tar->cal_mode = ATH10K_CAL_MODE_FILE;\n--- a/ath10k-5.15/core.h\n+++ b/ath10k-5.15/core.h\n@@ -1109,8 +1109,10 @@ enum ath10k_cal_mode {\n \tATH10K_CAL_MODE_FILE,\n \tATH10K_CAL_MODE_OTP,\n \tATH10K_CAL_MODE_DT,\n+\tATH10K_CAL_MODE_NVMEM,\n \tATH10K_PRE_CAL_MODE_FILE,\n \tATH10K_PRE_CAL_MODE_DT,\n+\tATH10K_PRE_CAL_MODE_NVMEM,\n \tATH10K_CAL_MODE_EEPROM,\n };\n \n@@ -1130,10 +1132,14 @@ static inline const char *ath10k_cal_mod\n \t\treturn \"otp\";\n \tcase ATH10K_CAL_MODE_DT:\n \t\treturn \"dt\";\n+\tcase ATH10K_CAL_MODE_NVMEM:\n+\t\treturn \"nvmem\";\n \tcase ATH10K_PRE_CAL_MODE_FILE:\n \t\treturn \"pre-cal-file\";\n \tcase ATH10K_PRE_CAL_MODE_DT:\n \t\treturn \"pre-cal-dt\";\n+\tcase ATH10K_PRE_CAL_MODE_NVMEM:\n+\t\treturn \"pre-cal-nvmem\";\n \tcase ATH10K_CAL_MODE_EEPROM:\n \t\treturn \"eeprom\";\n \t}\n"
  },
  {
    "path": "package/kernel/ath10k-ct/patches/201-ath10k-add-LED-and-GPIO-controlling-support-for-various-chipsets.patch",
    "content": "From: Sebastian Gottschall <s.gottschall@newmedia-net.de>\n\nAdds LED and GPIO Control support for 988x, 9887, 9888, 99x0, 9984 based\nchipsets with on chipset connected led's using WMI Firmware API.  The LED\ndevice will get available named as \"ath10k-phyX\" at sysfs and can be controlled\nwith various triggers.  adds also debugfs interface for gpio control.\n\nThis patch is specific for OpenWRt base, as is use old backported package\nwith old wireless source. Support for QCA9984 is removed.\nReworked to use ath10k-ct custom source\n\n\nSigned-off-by: Sebastian Gottschall <s.gottschall@dd-wrt.com>\nReviewed-by: Steve deRosier <derosier@cal-sierra.com>\n[kvalo: major reorg and cleanup]\nSigned-off-by: Kalle Valo <kvalo@codeaurora.org>\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\n---\n\nv13:\n\n* only compile tested!\n\n* fix all checkpatch warnings\n\n* fix commit log\n\n* sizeof(struct ath10k_gpiocontrol) -> sizeof(*gpio)\n\n* unsigned -> unsigned int\n\n* remove GPIOLIB code, that should be added in a separate patch\n\n* rename gpio.c to leds.c\n\n* add leds.h\n\n* rename some functions:\n\n  ath10k_attach_led() -> ath10k_leds_register()\n  ath10k_unregister_led() -> ath10k_leds_unregister()\n  ath10k_reset_led_pin() -> ath10k_leds_start()\n\n* call ath10k_leds_unregister() before ath10k_thermal_unregister() to preserve ordering\n\n* call ath10k_leds_start() only from ath10k_core_start() and not from mac.c\n\n* rename struct ath10k_gpiocontrol as anonymous function under struct\n  ath10k::leds, no need for memory allocation\n\n* merge ath10k_add_led() to ath10k_attach_led(), which is it's only caller\n\n* remove #if IS_ENABLED() checks from most of places, memory savings from those were not worth it\n\n* Kconfig help text improvement and move it lower in the menu, also don't enable it by default\n\n* switch to set_brightness_blocking() so that the callback can sleep,\n  then no need to use ath10k_wmi_cmd_send_nowait() and can take mutex\n  to access ar->state\n\n* don't touch ath10k_wmi_pdev_get_temperature()\n\n* as QCA6174/QCA9377 are not (yet) supported don't add the command to WMI-TLV interface\n\n* remove debugfs interface, that should be added in another patch\n\n* cleanup includes\n\n ath10k-5.15/Kconfig   |  10 +++\n ath10k-5.15/Makefile  |   1 +\n ath10k-5.15/core.c    |  22 +++++++\n ath10k-5.15/core.h    |   9 ++-\n ath10k-5.15/hw.h      |   1 +\n ath10k-5.15/leds.c    | 103 ++++++++++++++++++++++++++++++\n ath10k-5.15/leds.h    |  45 +++++++++++++\n ath10k-5.15/mac.c     |   1 +\n ath10k-5.15/wmi-ops.h |  32 ++++++++++\n ath10k-5.15/wmi-tlv.c |   2 +\n ath10k-5.15/wmi.c     |  54 ++++++++++++++++\n ath10k-5.15/wmi.h     |  35 ++++++++++\n 12 files changed, 314 insertions(+), 1 deletion(-)\n create mode 100644 ath10k-5.15/leds.c\n create mode 100644 ath10k-5.15/leds.h\n\n--- a/ath10k-5.15/Kconfig\n+++ b/ath10k-5.15/Kconfig\n@@ -66,6 +66,16 @@ config ATH10K_DEBUGFS\n \n \t  If unsure, say Y to make it easier to debug problems.\n \n+config ATH10K_LEDS\n+\tbool \"Atheros ath10k LED support\"\n+\tdepends on ATH10K\n+\tselect MAC80211_LEDS\n+\tselect LEDS_CLASS\n+\tselect NEW_LEDS\n+\tdefault y\n+\t---help---\n+\t  This option is necessary, if you want LED support for chipset connected led pins. If unsure, say N.\n+\n config ATH10K_SPECTRAL\n \tbool \"Atheros ath10k spectral scan support\"\n \tdepends on ATH10K_DEBUGFS\n--- a/ath10k-5.15/Makefile\n+++ b/ath10k-5.15/Makefile\n@@ -20,6 +20,7 @@ ath10k_core-$(CONFIG_ATH10K_SPECTRAL) +=\n ath10k_core-$(CONFIG_NL80211_TESTMODE) += testmode.o\n ath10k_core-$(CONFIG_ATH10K_TRACING) += trace.o\n ath10k_core-$(CONFIG_THERMAL) += thermal.o\n+ath10k_core-$(CONFIG_ATH10K_LEDS) += leds.o\n ath10k_core-$(CONFIG_MAC80211_DEBUGFS) += debugfs_sta.o\n ath10k_core-$(CONFIG_PM) += wow.o\n ath10k_core-$(CONFIG_ATH10K_CE) += ce.o\n--- a/ath10k-5.15/core.c\n+++ b/ath10k-5.15/core.c\n@@ -28,6 +28,7 @@\n #include \"testmode.h\"\n #include \"wmi-ops.h\"\n #include \"coredump.h\"\n+#include \"leds.h\"\n \n /* Disable ath10k-ct DBGLOG output by default */\n unsigned int ath10k_debug_mask = ATH10K_DBG_NO_DBGLOG;\n@@ -70,6 +71,7 @@ static const struct ath10k_hw_params ath\n \t\t.dev_id = QCA988X_2_0_DEVICE_ID,\n \t\t.bus = ATH10K_BUS_PCI,\n \t\t.name = \"qca988x hw2.0\",\n+\t\t.led_pin = 1,\n \t\t.patch_load_addr = QCA988X_HW_2_0_PATCH_LOAD_ADDR,\n \t\t.uart_pin = 7,\n \t\t.cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_ALL,\n@@ -141,6 +143,7 @@ static const struct ath10k_hw_params ath\n \t\t.dev_id = QCA9887_1_0_DEVICE_ID,\n \t\t.bus = ATH10K_BUS_PCI,\n \t\t.name = \"qca9887 hw1.0\",\n+\t\t.led_pin = 1,\n \t\t.patch_load_addr = QCA9887_HW_1_0_PATCH_LOAD_ADDR,\n \t\t.uart_pin = 7,\n \t\t.cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_ALL,\n@@ -352,6 +355,7 @@ static const struct ath10k_hw_params ath\n \t\t.dev_id = QCA99X0_2_0_DEVICE_ID,\n \t\t.bus = ATH10K_BUS_PCI,\n \t\t.name = \"qca99x0 hw2.0\",\n+\t\t.led_pin = 17,\n \t\t.patch_load_addr = QCA99X0_HW_2_0_PATCH_LOAD_ADDR,\n \t\t.uart_pin = 7,\n \t\t.otp_exe_param = 0x00000700,\n@@ -393,6 +397,7 @@ static const struct ath10k_hw_params ath\n \t\t.dev_id = QCA9984_1_0_DEVICE_ID,\n \t\t.bus = ATH10K_BUS_PCI,\n \t\t.name = \"qca9984/qca9994 hw1.0\",\n+\t\t.led_pin = 17,\n \t\t.patch_load_addr = QCA9984_HW_1_0_PATCH_LOAD_ADDR,\n \t\t.uart_pin = 7,\n \t\t.cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_EACH,\n@@ -441,6 +446,7 @@ static const struct ath10k_hw_params ath\n \t\t.dev_id = QCA9888_2_0_DEVICE_ID,\n \t\t.bus = ATH10K_BUS_PCI,\n \t\t.name = \"qca9888 hw2.0\",\n+\t\t.led_pin = 17,\n \t\t.patch_load_addr = QCA9888_HW_2_0_PATCH_LOAD_ADDR,\n \t\t.uart_pin = 7,\n \t\t.cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_EACH,\n@@ -3942,6 +3948,10 @@ int ath10k_core_start(struct ath10k *ar,\n \t\t\tath10k_wmi_check_apply_board_power_ctl_table(ar);\n \t}\n \n+\tstatus = ath10k_leds_start(ar);\n+\tif (status)\n+\t\tgoto err_hif_stop;\n+\n \treturn 0;\n \n err_hif_stop:\n@@ -4203,9 +4213,18 @@ static void ath10k_core_register_work(st\n \t\tgoto err_spectral_destroy;\n \t}\n \n+\tstatus = ath10k_leds_register(ar);\n+\tif (status) {\n+\t\tath10k_err(ar, \"could not register leds: %d\\n\",\n+\t\t\t   status);\n+\t\tgoto err_thermal_unregister;\n+\t}\n+\n \tset_bit(ATH10K_FLAG_CORE_REGISTERED, &ar->dev_flags);\n \treturn;\n \n+err_thermal_unregister:\n+\tath10k_thermal_unregister(ar);\n err_spectral_destroy:\n \tath10k_spectral_destroy(ar);\n err_debug_destroy:\n@@ -4265,6 +4284,8 @@ void ath10k_core_unregister(struct ath10\n \tif (!test_bit(ATH10K_FLAG_CORE_REGISTERED, &ar->dev_flags))\n \t\treturn;\n \n+\tath10k_leds_unregister(ar);\n+\n \tath10k_thermal_unregister(ar);\n \t/* Stop spectral before unregistering from mac80211 to remove the\n \t * relayfs debugfs file cleanly. Otherwise the parent debugfs tree\n--- a/ath10k-5.15/core.h\n+++ b/ath10k-5.15/core.h\n@@ -14,6 +14,7 @@\n #include <linux/pci.h>\n #include <linux/uuid.h>\n #include <linux/time.h>\n+#include <linux/leds.h>\n \n #include \"htt.h\"\n #include \"htc.h\"\n@@ -1577,6 +1578,13 @@ struct ath10k {\n \t} testmode;\n \n \tstruct {\n+\t\tstruct gpio_led wifi_led;\n+\t\tstruct led_classdev cdev;\n+\t\tchar label[48];\n+\t\tu32 gpio_state_pin;\n+\t} leds;\n+\n+\tstruct {\n \t\t/* protected by data_lock */\n \t\tu32 rx_crc_err_drop;\n \t\tu32 fw_crash_counter;\n--- a/ath10k-5.15/hw.h\n+++ b/ath10k-5.15/hw.h\n@@ -521,6 +521,7 @@ struct ath10k_hw_params {\n \tconst char *name;\n \tu32 patch_load_addr;\n \tint uart_pin;\n+\tint led_pin;\n \tu32 otp_exe_param;\n \n \t/* Type of hw cycle counter wraparound logic, for more info\n--- /dev/null\n+++ b/ath10k-5.15/leds.c\n@@ -0,0 +1,103 @@\n+/*\n+ * Copyright (c) 2005-2011 Atheros Communications Inc.\n+ * Copyright (c) 2011-2017 Qualcomm Atheros, Inc.\n+ * Copyright (c) 2018 Sebastian Gottschall <s.gottschall@dd-wrt.com>\n+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.\n+ *\n+ * Permission to use, copy, modify, and/or distribute this software for any\n+ * purpose with or without fee is hereby granted, provided that the above\n+ * copyright notice and this permission notice appear in all copies.\n+ *\n+ * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n+ */\n+\n+#include <linux/leds.h>\n+\n+#include \"core.h\"\n+#include \"wmi.h\"\n+#include \"wmi-ops.h\"\n+\n+#include \"leds.h\"\n+\n+static int ath10k_leds_set_brightness_blocking(struct led_classdev *led_cdev,\n+\t\t\t\t\t       enum led_brightness brightness)\n+{\n+\tstruct ath10k *ar = container_of(led_cdev, struct ath10k,\n+\t\t\t\t\t leds.cdev);\n+\tstruct gpio_led *led = &ar->leds.wifi_led;\n+\n+\tmutex_lock(&ar->conf_mutex);\n+\n+\tif (ar->state != ATH10K_STATE_ON)\n+\t\tgoto out;\n+\n+\tar->leds.gpio_state_pin = (brightness != LED_OFF) ^ led->active_low;\n+\tath10k_wmi_gpio_output(ar, led->gpio, ar->leds.gpio_state_pin);\n+\n+out:\n+\tmutex_unlock(&ar->conf_mutex);\n+\n+\treturn 0;\n+}\n+\n+int ath10k_leds_start(struct ath10k *ar)\n+{\n+\tif (ar->hw_params.led_pin == 0)\n+\t\t/* leds not supported */\n+\t\treturn 0;\n+\n+\t/* under some circumstances, the gpio pin gets reconfigured\n+\t * to default state by the firmware, so we need to\n+\t * reconfigure it this behaviour has only ben seen on\n+\t * QCA9984 and QCA99XX devices so far\n+\t */\n+\tath10k_wmi_gpio_config(ar, ar->hw_params.led_pin, 0,\n+\t\t\t       WMI_GPIO_PULL_NONE, WMI_GPIO_INTTYPE_DISABLE);\n+\tath10k_wmi_gpio_output(ar, ar->hw_params.led_pin, 1);\n+\n+\treturn 0;\n+}\n+\n+int ath10k_leds_register(struct ath10k *ar)\n+{\n+\tint ret;\n+\n+\tif (ar->hw_params.led_pin == 0)\n+\t\t/* leds not supported */\n+\t\treturn 0;\n+\n+\tsnprintf(ar->leds.label, sizeof(ar->leds.label), \"ath10k-%s\",\n+\t\t wiphy_name(ar->hw->wiphy));\n+\tar->leds.wifi_led.active_low = 1;\n+\tar->leds.wifi_led.gpio = ar->hw_params.led_pin;\n+\tar->leds.wifi_led.name = ar->leds.label;\n+\tar->leds.wifi_led.default_state = LEDS_GPIO_DEFSTATE_KEEP;\n+\n+\tar->leds.cdev.name = ar->leds.label;\n+\tar->leds.cdev.brightness_set_blocking = ath10k_leds_set_brightness_blocking;\n+\n+\t/* FIXME: this assignment doesn't make sense as it's NULL, remove it? */\n+\tar->leds.cdev.default_trigger = ar->leds.wifi_led.default_trigger;\n+\n+\tret = led_classdev_register(wiphy_dev(ar->hw->wiphy), &ar->leds.cdev);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\treturn 0;\n+}\n+\n+void ath10k_leds_unregister(struct ath10k *ar)\n+{\n+\tif (ar->hw_params.led_pin == 0)\n+\t\t/* leds not supported */\n+\t\treturn;\n+\n+\tled_classdev_unregister(&ar->leds.cdev);\n+}\n+\n--- /dev/null\n+++ b/ath10k-5.15/leds.h\n@@ -0,0 +1,41 @@\n+/*\n+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.\n+ *\n+ * Permission to use, copy, modify, and/or distribute this software for any\n+ * purpose with or without fee is hereby granted, provided that the above\n+ * copyright notice and this permission notice appear in all copies.\n+ *\n+ * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n+ */\n+#ifndef _LEDS_H_\n+#define _LEDS_H_\n+\n+#include \"core.h\"\n+\n+#ifdef CONFIG_ATH10K_LEDS\n+void ath10k_leds_unregister(struct ath10k *ar);\n+int ath10k_leds_start(struct ath10k *ar);\n+int ath10k_leds_register(struct ath10k *ar);\n+#else\n+static inline void ath10k_leds_unregister(struct ath10k *ar)\n+{\n+}\n+\n+static inline int ath10k_leds_start(struct ath10k *ar)\n+{\n+\treturn 0;\n+}\n+\n+static inline int ath10k_leds_register(struct ath10k *ar)\n+{\n+\treturn 0;\n+}\n+\n+#endif\n+#endif /* _LEDS_H_ */\n--- a/ath10k-5.15/mac.c\n+++ b/ath10k-5.15/mac.c\n@@ -25,6 +25,7 @@\n #include \"wmi-tlv.h\"\n #include \"wmi-ops.h\"\n #include \"wow.h\"\n+#include \"leds.h\"\n \n /*********/\n /* Rates */\n--- a/ath10k-5.15/wmi-ops.h\n+++ b/ath10k-5.15/wmi-ops.h\n@@ -228,7 +228,10 @@ struct wmi_ops {\n \t\t\t const struct wmi_bb_timing_cfg_arg *arg);\n \tstruct sk_buff *(*gen_per_peer_per_tid_cfg)(struct ath10k *ar,\n \t\t\t\t\t\t    const struct wmi_per_peer_per_tid_cfg_arg *arg);\n+\tstruct sk_buff *(*gen_gpio_config)(struct ath10k *ar, u32 gpio_num,\n+\t\t\t\t\t   u32 input, u32 pull_type, u32 intr_mode);\n \n+\tstruct sk_buff *(*gen_gpio_output)(struct ath10k *ar, u32 gpio_num, u32 set);\n };\n \n int ath10k_wmi_cmd_send(struct ath10k *ar, struct sk_buff *skb, u32 cmd_id);\n@@ -1147,6 +1150,35 @@ ath10k_wmi_force_fw_hang(struct ath10k *\n \treturn ath10k_wmi_cmd_send(ar, skb, ar->wmi.cmd->force_fw_hang_cmdid);\n }\n \n+static inline int ath10k_wmi_gpio_config(struct ath10k *ar, u32 gpio_num,\n+\t\t\t\t\t u32 input, u32 pull_type, u32 intr_mode)\n+{\n+\tstruct sk_buff *skb;\n+\n+\tif (!ar->wmi.ops->gen_gpio_config)\n+\t\treturn -EOPNOTSUPP;\n+\n+\tskb = ar->wmi.ops->gen_gpio_config(ar, gpio_num, input, pull_type, intr_mode);\n+\tif (IS_ERR(skb))\n+\t\treturn PTR_ERR(skb);\n+\n+\treturn ath10k_wmi_cmd_send(ar, skb, ar->wmi.cmd->gpio_config_cmdid);\n+}\n+\n+static inline int ath10k_wmi_gpio_output(struct ath10k *ar, u32 gpio_num, u32 set)\n+{\n+\tstruct sk_buff *skb;\n+\n+\tif (!ar->wmi.ops->gen_gpio_config)\n+\t\treturn -EOPNOTSUPP;\n+\n+\tskb = ar->wmi.ops->gen_gpio_output(ar, gpio_num, set);\n+\tif (IS_ERR(skb))\n+\t\treturn PTR_ERR(skb);\n+\n+\treturn ath10k_wmi_cmd_send(ar, skb, ar->wmi.cmd->gpio_output_cmdid);\n+}\n+\n static inline int\n ath10k_wmi_dbglog_cfg(struct ath10k *ar, u64 module_enable, u32 log_level)\n {\n--- a/ath10k-5.15/wmi-tlv.c\n+++ b/ath10k-5.15/wmi-tlv.c\n@@ -4594,6 +4594,8 @@ static const struct wmi_ops wmi_tlv_ops\n \t.gen_echo = ath10k_wmi_tlv_op_gen_echo,\n \t.gen_vdev_spectral_conf = ath10k_wmi_tlv_op_gen_vdev_spectral_conf,\n \t.gen_vdev_spectral_enable = ath10k_wmi_tlv_op_gen_vdev_spectral_enable,\n+\t/* .gen_gpio_config not implemented */\n+\t/* .gen_gpio_output not implemented */\n };\n \n static const struct wmi_peer_flags_map wmi_tlv_peer_flags_map = {\n--- a/ath10k-5.15/wmi.c\n+++ b/ath10k-5.15/wmi.c\n@@ -8409,6 +8409,49 @@ ath10k_wmi_op_gen_peer_set_param(struct\n \treturn skb;\n }\n \n+static struct sk_buff *ath10k_wmi_op_gen_gpio_config(struct ath10k *ar,\n+\t\t\t\t\t\t     u32 gpio_num, u32 input,\n+\t\t\t\t\t\t     u32 pull_type, u32 intr_mode)\n+{\n+\tstruct wmi_gpio_config_cmd *cmd;\n+\tstruct sk_buff *skb;\n+\n+\tskb = ath10k_wmi_alloc_skb(ar, sizeof(*cmd));\n+\tif (!skb)\n+\t\treturn ERR_PTR(-ENOMEM);\n+\n+\tcmd = (struct wmi_gpio_config_cmd *)skb->data;\n+\tcmd->pull_type = __cpu_to_le32(pull_type);\n+\tcmd->gpio_num = __cpu_to_le32(gpio_num);\n+\tcmd->input = __cpu_to_le32(input);\n+\tcmd->intr_mode = __cpu_to_le32(intr_mode);\n+\n+\tath10k_dbg(ar, ATH10K_DBG_WMI, \"wmi gpio_config gpio_num 0x%08x input 0x%08x pull_type 0x%08x intr_mode 0x%08x\\n\",\n+\t\t   gpio_num, input, pull_type, intr_mode);\n+\n+\treturn skb;\n+}\n+\n+static struct sk_buff *ath10k_wmi_op_gen_gpio_output(struct ath10k *ar,\n+\t\t\t\t\t\t     u32 gpio_num, u32 set)\n+{\n+\tstruct wmi_gpio_output_cmd *cmd;\n+\tstruct sk_buff *skb;\n+\n+\tskb = ath10k_wmi_alloc_skb(ar, sizeof(*cmd));\n+\tif (!skb)\n+\t\treturn ERR_PTR(-ENOMEM);\n+\n+\tcmd = (struct wmi_gpio_output_cmd *)skb->data;\n+\tcmd->gpio_num = __cpu_to_le32(gpio_num);\n+\tcmd->set = __cpu_to_le32(set);\n+\n+\tath10k_dbg(ar, ATH10K_DBG_WMI, \"wmi gpio_output gpio_num 0x%08x set 0x%08x\\n\",\n+\t\t   gpio_num, set);\n+\n+\treturn skb;\n+}\n+\n static struct sk_buff *\n ath10k_wmi_op_gen_set_psmode(struct ath10k *ar, u32 vdev_id,\n \t\t\t     enum wmi_sta_ps_mode psmode)\n@@ -10240,6 +10283,9 @@ static const struct wmi_ops wmi_ops = {\n \t.fw_stats_fill = ath10k_wmi_main_op_fw_stats_fill,\n \t.get_vdev_subtype = ath10k_wmi_op_get_vdev_subtype,\n \t.gen_echo = ath10k_wmi_op_gen_echo,\n+\t.gen_gpio_config = ath10k_wmi_op_gen_gpio_config,\n+\t.gen_gpio_output = ath10k_wmi_op_gen_gpio_output,\n+\n \t/* .gen_bcn_tmpl not implemented */\n \t/* .gen_prb_tmpl not implemented */\n \t/* .gen_p2p_go_bcn_ie not implemented */\n@@ -10310,6 +10356,8 @@ static const struct wmi_ops wmi_10_1_ops\n \t.fw_stats_fill = ath10k_wmi_10x_op_fw_stats_fill,\n \t.get_vdev_subtype = ath10k_wmi_op_get_vdev_subtype,\n \t.gen_echo = ath10k_wmi_op_gen_echo,\n+\t.gen_gpio_config = ath10k_wmi_op_gen_gpio_config,\n+\t.gen_gpio_output = ath10k_wmi_op_gen_gpio_output,\n \t/* .gen_bcn_tmpl not implemented */\n \t/* .gen_prb_tmpl not implemented */\n \t/* .gen_p2p_go_bcn_ie not implemented */\n@@ -10389,6 +10437,8 @@ static const struct wmi_ops wmi_10_2_ops\n \t.gen_delba_send = ath10k_wmi_op_gen_delba_send,\n \t.fw_stats_fill = ath10k_wmi_10x_op_fw_stats_fill,\n \t.get_vdev_subtype = ath10k_wmi_op_get_vdev_subtype,\n+\t.gen_gpio_config = ath10k_wmi_op_gen_gpio_config,\n+\t.gen_gpio_output = ath10k_wmi_op_gen_gpio_output,\n \t/* .gen_pdev_enable_adaptive_cca not implemented */\n };\n \n@@ -10460,6 +10510,8 @@ static const struct wmi_ops wmi_10_2_4_o\n \t\tath10k_wmi_op_gen_pdev_enable_adaptive_cca,\n \t.get_vdev_subtype = ath10k_wmi_10_2_4_op_get_vdev_subtype,\n \t.gen_bb_timing = ath10k_wmi_10_2_4_op_gen_bb_timing,\n+\t.gen_gpio_config = ath10k_wmi_op_gen_gpio_config,\n+\t.gen_gpio_output = ath10k_wmi_op_gen_gpio_output,\n \t/* .gen_bcn_tmpl not implemented */\n \t/* .gen_prb_tmpl not implemented */\n \t/* .gen_p2p_go_bcn_ie not implemented */\n@@ -10542,6 +10594,8 @@ static const struct wmi_ops wmi_10_4_ops\n \t.gen_pdev_bss_chan_info_req = ath10k_wmi_10_2_op_gen_pdev_bss_chan_info,\n \t.gen_echo = ath10k_wmi_op_gen_echo,\n \t.gen_pdev_get_tpc_config = ath10k_wmi_10_2_4_op_gen_pdev_get_tpc_config,\n+\t.gen_gpio_config = ath10k_wmi_op_gen_gpio_config,\n+\t.gen_gpio_output = ath10k_wmi_op_gen_gpio_output,\n };\n \n int ath10k_wmi_attach(struct ath10k *ar)\n--- a/ath10k-5.15/wmi.h\n+++ b/ath10k-5.15/wmi.h\n@@ -3133,6 +3133,41 @@ enum wmi_10_4_feature_mask {\n \n };\n \n+/* WMI_GPIO_CONFIG_CMDID */\n+enum {\n+\tWMI_GPIO_PULL_NONE,\n+\tWMI_GPIO_PULL_UP,\n+\tWMI_GPIO_PULL_DOWN,\n+};\n+\n+enum {\n+\tWMI_GPIO_INTTYPE_DISABLE,\n+\tWMI_GPIO_INTTYPE_RISING_EDGE,\n+\tWMI_GPIO_INTTYPE_FALLING_EDGE,\n+\tWMI_GPIO_INTTYPE_BOTH_EDGE,\n+\tWMI_GPIO_INTTYPE_LEVEL_LOW,\n+\tWMI_GPIO_INTTYPE_LEVEL_HIGH\n+};\n+\n+/* WMI_GPIO_CONFIG_CMDID */\n+struct wmi_gpio_config_cmd {\n+\t__le32 gpio_num;             /* GPIO number to be setup */\n+\t__le32 input;                /* 0 - Output/ 1 - Input */\n+\t__le32 pull_type;            /* Pull type defined above */\n+\t__le32 intr_mode;            /* Interrupt mode defined above (Input) */\n+} __packed;\n+\n+/* WMI_GPIO_OUTPUT_CMDID */\n+struct wmi_gpio_output_cmd {\n+\t__le32 gpio_num;    /* GPIO number to be setup */\n+\t__le32 set;         /* Set the GPIO pin*/\n+} __packed;\n+\n+/* WMI_GPIO_INPUT_EVENTID */\n+struct wmi_gpio_input_event {\n+\t__le32 gpio_num;    /* GPIO number which changed state */\n+} __packed;\n+\n struct wmi_ext_resource_config_10_4_cmd {\n \t/* contains enum wmi_host_platform_type */\n \t__le32 host_platform_config;\n"
  },
  {
    "path": "package/kernel/ath10k-ct/patches/202-ath10k-use-tpt-trigger-by-default.patch",
    "content": "From 79c9d7aabae1d1da9eea97d83b61e1517a8a2221 Mon Sep 17 00:00:00 2001\nFrom: Mathias Kresin <dev@kresin.me>\nDate: Fri, 22 Jun 2018 18:59:44 +0200\nSubject: [PATCH] ath10k: use tpt LED trigger by default\n\nUse the tpt LED trigger for each created phy led. Ths way LEDs attached\nto the ath10k GPIO pins are indicating the phy status and blink on\ntraffic.\n\nSigned-off-by: Mathias Kresin <dev@kresin.me>\n---\n ath10k-5.15/core.h | 4 ++++\n ath10k-5.15/leds.c | 4 +---\n ath10k-5.15/mac.c  | 2 +-\n 3 files changed, 6 insertions(+), 4 deletions(-)\n\n--- a/ath10k-5.15/core.h\n+++ b/ath10k-5.15/core.h\n@@ -1692,6 +1692,10 @@ struct ath10k {\n \tu8 csi_data[4096];\n \tu16 csi_data_len;\n \n+#ifdef CPTCFG_MAC80211_LEDS\n+\tconst char *led_default_trigger;\n+#endif\n+\n \t/* must be last */\n \tu8 drv_priv[] __aligned(sizeof(void *));\n };\n--- a/ath10k-5.15/leds.c\n+++ b/ath10k-5.15/leds.c\n@@ -81,9 +81,7 @@ int ath10k_leds_register(struct ath10k *\n \n \tar->leds.cdev.name = ar->leds.label;\n \tar->leds.cdev.brightness_set_blocking = ath10k_leds_set_brightness_blocking;\n-\n-\t/* FIXME: this assignment doesn't make sense as it's NULL, remove it? */\n-\tar->leds.cdev.default_trigger = ar->leds.wifi_led.default_trigger;\n+\tar->leds.cdev.default_trigger = ar->led_default_trigger;\n \n \tret = led_classdev_register(wiphy_dev(ar->hw->wiphy), &ar->leds.cdev);\n \tif (ret)\n--- a/ath10k-5.15/mac.c\n+++ b/ath10k-5.15/mac.c\n@@ -11521,7 +11521,7 @@ int ath10k_mac_register(struct ath10k *a\n \tar->hw->weight_multiplier = ATH10K_AIRTIME_WEIGHT_MULTIPLIER;\n \n #ifdef CPTCFG_MAC80211_LEDS\n-\tieee80211_create_tpt_led_trigger(ar->hw,\n+\tar->led_default_trigger = ieee80211_create_tpt_led_trigger(ar->hw,\n \t\tIEEE80211_TPT_LEDTRIG_FL_RADIO, ath10k_tpt_blink,\n \t\tARRAY_SIZE(ath10k_tpt_blink));\n #endif\n"
  },
  {
    "path": "package/kernel/ath10k-ct/patches/300-ath10k-ct-Fix-spectral-scan-NULL-pointer.patch",
    "content": "From 0d2e335d780bda1432a9ba719c8200f796d27854 Mon Sep 17 00:00:00 2001\nFrom: Robert Marko <robimarko@gmail.com>\nDate: Mon, 29 Nov 2021 12:27:12 +0100\nSubject: [PATCH] ath10k-ct: Fix spectral scan NULL pointer\n\nIf spectral scan support is enabled then ath10k-ct will cause a NULL\npointer due to relay_open() being called with a const callback struct\nwhich is only supported in kernel 5.11 and later.\n\nSo, simply check the kernel version and if 5.11 and newer use the const\ncallback struct, otherwise use the regular struct.\n\nFixes: 553a3ac (\"ath10k-ct: use 5.15 version\")\nSigned-off-by: Robert Marko <robimarko@gmail.com>\n---\n ath10k-5.15/spectral.c | 4 ++++\n 1 file changed, 4 insertions(+)\n\n--- a/ath10k-5.15/spectral.c\n+++ b/ath10k-5.15/spectral.c\n@@ -497,7 +497,11 @@ static int remove_buf_file_handler(struc\n \treturn 0;\n }\n \n+#if LINUX_VERSION_IS_GEQ(5,11,0)\n static const struct rchan_callbacks rfs_spec_scan_cb = {\n+#else\n+static struct rchan_callbacks rfs_spec_scan_cb = {\n+#endif\n \t.create_buf_file = create_buf_file_handler,\n \t.remove_buf_file = remove_buf_file_handler,\n };\n"
  },
  {
    "path": "package/kernel/ath10k-ct/patches/960-0010-ath10k-limit-htt-rx-ring-size.patch",
    "content": "--- a/ath10k-5.15/htt.h\n+++ b/ath10k-5.15/htt.h\n@@ -237,7 +237,11 @@ enum htt_rx_ring_flags {\n };\n \n #define HTT_RX_RING_SIZE_MIN 128\n+#ifndef CONFIG_ATH10K_SMALLBUFFERS\n #define HTT_RX_RING_SIZE_MAX 2048\n+#else\n+#define HTT_RX_RING_SIZE_MAX 512\n+#endif\n #define HTT_RX_RING_SIZE HTT_RX_RING_SIZE_MAX\n #define HTT_RX_RING_FILL_LEVEL (((HTT_RX_RING_SIZE) / 2) - 1)\n #define HTT_RX_RING_FILL_LEVEL_DUAL_MAC (HTT_RX_RING_SIZE - 1)\n"
  },
  {
    "path": "package/kernel/ath10k-ct/patches/960-0011-ath10k-limit-pci-buffer-size.patch",
    "content": "--- a/ath10k-5.15/pci.c\n+++ b/ath10k-5.15/pci.c\n@@ -131,7 +131,11 @@ static const struct ce_attr pci_host_ce_\n \t\t.flags = CE_ATTR_FLAGS,\n \t\t.src_nentries = 0,\n \t\t.src_sz_max = 2048,\n+#ifndef CONFIG_ATH10K_SMALLBUFFERS\n \t\t.dest_nentries = 512,\n+#else\n+\t\t.dest_nentries = 128,\n+#endif\n \t\t.recv_cb = ath10k_pci_htt_htc_rx_cb,\n \t},\n \n@@ -140,7 +144,11 @@ static const struct ce_attr pci_host_ce_\n \t\t.flags = CE_ATTR_FLAGS,\n \t\t.src_nentries = 0,\n \t\t.src_sz_max = 2048,\n+#ifndef CONFIG_ATH10K_SMALLBUFFERS\n \t\t.dest_nentries = 128,\n+#else\n+\t\t.dest_nentries = 64,\n+#endif\n \t\t.recv_cb = ath10k_pci_htc_rx_cb,\n \t},\n \n@@ -167,7 +175,11 @@ static const struct ce_attr pci_host_ce_\n \t\t.flags = CE_ATTR_FLAGS,\n \t\t.src_nentries = 0,\n \t\t.src_sz_max = 512,\n+#ifndef CONFIG_ATH10K_SMALLBUFFERS\n \t\t.dest_nentries = 512,\n+#else\n+\t\t.dest_nentries = 128,\n+#endif\n \t\t.recv_cb = ath10k_pci_htt_rx_cb,\n \t},\n \n@@ -192,7 +204,11 @@ static const struct ce_attr pci_host_ce_\n \t\t.flags = CE_ATTR_FLAGS,\n \t\t.src_nentries = 0,\n \t\t.src_sz_max = 2048,\n+#ifndef CONFIG_ATH10K_SMALLBUFFERS\n \t\t.dest_nentries = 128,\n+#else\n+\t\t.dest_nentries = 96,\n+#endif\n \t\t.recv_cb = ath10k_pci_pktlog_rx_cb,\n \t},\n \n"
  },
  {
    "path": "package/kernel/bcm27xx-gpu-fw/Makefile",
    "content": "include $(TOPDIR)/rules.mk\ninclude $(INCLUDE_DIR)/kernel.mk\n\nPKG_NAME:=bcm27xx-gpu-fw\nPKG_VERSION:=2021-08-19\nPKG_RELEASE:=25e2b597ebfb2495eab4816a276758dcc6ea21f1\n\nPKG_BUILD_DIR:=$(KERNEL_BUILD_DIR)/$(PKG_NAME)/rpi-firmware-$(PKG_RELEASE)\n\nPKG_FLAGS:=nonshared\n\ninclude $(INCLUDE_DIR)/package.mk\n\nRPI_FIRMWARE_URL:=@GITHUB/raspberrypi/firmware/$(PKG_RELEASE)/boot/\nRPI_FIRMWARE_FILE:=rpi-firmware-$(PKG_RELEASE)\n\ndefine Download/LICENCE_broadcom\n  FILE:=$(RPI_FIRMWARE_FILE)-LICENCE.broadcom\n  URL:=$(RPI_FIRMWARE_URL)\n  URL_FILE:=LICENCE.broadcom\n  HASH:=c7283ff51f863d93a275c66e3b4cb08021a5dd4d8c1e7acc47d872fbe52d3d6b\nendef\n$(eval $(call Download,LICENCE_broadcom))\n\ndefine Download/bootcode_bin\n  FILE:=$(RPI_FIRMWARE_FILE)-bootcode.bin\n  URL:=$(RPI_FIRMWARE_URL)\n  URL_FILE:=bootcode.bin\n  HASH:=36fba28838867f26670a0cd1de340da62e13171cfdec0e7822737e849b3c0681\nendef\n$(eval $(call Download,bootcode_bin))\n\ndefine Download/fixup_dat\n  FILE:=$(RPI_FIRMWARE_FILE)-fixup.dat\n  URL:=$(RPI_FIRMWARE_URL)\n  URL_FILE:=fixup.dat\n  HASH:=b06aa43aa668d6982de66044299d1b0dd6b449ec321dd83742aa1eb68774e15b\nendef\n$(eval $(call Download,fixup_dat))\n\ndefine Download/fixup_cd_dat\n  FILE:=$(RPI_FIRMWARE_FILE)-fixup_cd.dat\n  URL:=$(RPI_FIRMWARE_URL)\n  URL_FILE:=fixup_cd.dat\n  HASH:=fff4fd9fbb691100be46269f554acd866eac8cfef39082e03ac12f70fbfe9d95\nendef\n$(eval $(call Download,fixup_cd_dat))\n\ndefine Download/fixup_x_dat\n  FILE:=$(RPI_FIRMWARE_FILE)-fixup_x.dat\n  URL:=$(RPI_FIRMWARE_URL)\n  URL_FILE:=fixup_x.dat\n  HASH:=d74f97ae37cd476e6d4c8e466c3013be49e891e63b9aabc0c9b7637d85068cd0\nendef\n$(eval $(call Download,fixup_x_dat))\n\ndefine Download/fixup4_dat\n  FILE:=$(RPI_FIRMWARE_FILE)-fixup4.dat\n  URL:=$(RPI_FIRMWARE_URL)\n  URL_FILE:=fixup4.dat\n  HASH:=a607f4dc3000c188f8daaa3417c70a9e5ecc039fae36ba46807c00294f89cd24\nendef\n$(eval $(call Download,fixup4_dat))\n\ndefine Download/fixup4cd_dat\n  FILE:=$(RPI_FIRMWARE_FILE)-fixup4cd.dat\n  URL:=$(RPI_FIRMWARE_URL)\n  URL_FILE:=fixup4cd.dat\n  HASH:=fff4fd9fbb691100be46269f554acd866eac8cfef39082e03ac12f70fbfe9d95\nendef\n$(eval $(call Download,fixup4cd_dat))\n\ndefine Download/fixup4x_dat\n  FILE:=$(RPI_FIRMWARE_FILE)-fixup4x.dat\n  URL:=$(RPI_FIRMWARE_URL)\n  URL_FILE:=fixup4x.dat\n  HASH:=14ba09cba83d82a158481a7267fad06ada73c26c3a27dfd34694955f11ba6e27\nendef\n$(eval $(call Download,fixup4x_dat))\n\ndefine Download/start_elf\n  FILE:=$(RPI_FIRMWARE_FILE)-start.elf\n  URL:=$(RPI_FIRMWARE_URL)\n  URL_FILE:=start.elf\n  HASH:=8bee170c56529bf1666ad4afdd18ae18c7123e7a2fd30e2992cd0d9a01fa63ee\nendef\n$(eval $(call Download,start_elf))\n\ndefine Download/start_cd_elf\n  FILE:=$(RPI_FIRMWARE_FILE)-start_cd.elf\n  URL:=$(RPI_FIRMWARE_URL)\n  URL_FILE:=start_cd.elf\n  HASH:=27d9354ff1af79a521527a288fe736f7337f91bca12bbc177c80e29dbbef0ffd\nendef\n$(eval $(call Download,start_cd_elf))\n\ndefine Download/start_x_elf\n  FILE:=$(RPI_FIRMWARE_FILE)-start_x.elf\n  URL:=$(RPI_FIRMWARE_URL)\n  URL_FILE:=start_x.elf\n  HASH:=499bfdf3deba7bb0a033d2a4487b7f05bce45de2692c7c6dabc4a456237fd438\nendef\n$(eval $(call Download,start_x_elf))\n\ndefine Download/start4_elf\n  FILE:=$(RPI_FIRMWARE_FILE)-start4.elf\n  URL:=$(RPI_FIRMWARE_URL)\n  URL_FILE:=start4.elf\n  HASH:=158bf783090223626cf45794bf679a3fadbf64bba55b76e3349b94e01be34202\nendef\n$(eval $(call Download,start4_elf))\n\ndefine Download/start4cd_elf\n  FILE:=$(RPI_FIRMWARE_FILE)-start4cd.elf\n  URL:=$(RPI_FIRMWARE_URL)\n  URL_FILE:=start4cd.elf\n  HASH:=c4912701f620cdd9e44bbacbfc4adb4be1b6fb7ccf81f6029ce2115511970cc0\nendef\n$(eval $(call Download,start4cd_elf))\n\ndefine Download/start4x_elf\n  FILE:=$(RPI_FIRMWARE_FILE)-start4x.elf\n  URL:=$(RPI_FIRMWARE_URL)\n  URL_FILE:=start4x.elf\n  HASH:=3eb1adb5dfef21da0a16679ef65314a64196a67c6fca3422df8bc721d6b6fa94\nendef\n$(eval $(call Download,start4x_elf))\n\ndefine Package/bcm27xx-gpu-fw\n  SECTION:=boot\n  CATEGORY:=Boot Loaders\n  DEPENDS:=@TARGET_bcm27xx\n  TITLE:=bcm27xx-gpu-fw\n  DEFAULT:=y if TARGET_bcm27xx\nendef\n\ndefine Package/bcm27xx-gpu-fw/description\n GPU and kernel boot firmware for bcm27xx.\nendef\n\ndefine Build/Prepare\n\trm -rf $(PKG_BUILD_DIR)\n\tmkdir -p $(PKG_BUILD_DIR)\n\t$(CP) $(DL_DIR)/$(RPI_FIRMWARE_FILE)-LICENCE.broadcom $(PKG_BUILD_DIR)/LICENCE.broadcom\n\t$(CP) $(DL_DIR)/$(RPI_FIRMWARE_FILE)-bootcode.bin $(PKG_BUILD_DIR)/bootcode.bin\n\t$(CP) $(DL_DIR)/$(RPI_FIRMWARE_FILE)-fixup.dat $(PKG_BUILD_DIR)/fixup.dat\n\t$(CP) $(DL_DIR)/$(RPI_FIRMWARE_FILE)-fixup_cd.dat $(PKG_BUILD_DIR)/fixup_cd.dat\n\t$(CP) $(DL_DIR)/$(RPI_FIRMWARE_FILE)-fixup_x.dat $(PKG_BUILD_DIR)/fixup_x.dat\n\t$(CP) $(DL_DIR)/$(RPI_FIRMWARE_FILE)-fixup4.dat $(PKG_BUILD_DIR)/fixup4.dat\n\t$(CP) $(DL_DIR)/$(RPI_FIRMWARE_FILE)-fixup4cd.dat $(PKG_BUILD_DIR)/fixup4cd.dat\n\t$(CP) $(DL_DIR)/$(RPI_FIRMWARE_FILE)-fixup4x.dat $(PKG_BUILD_DIR)/fixup4x.dat\n\t$(CP) $(DL_DIR)/$(RPI_FIRMWARE_FILE)-start.elf $(PKG_BUILD_DIR)/start.elf\n\t$(CP) $(DL_DIR)/$(RPI_FIRMWARE_FILE)-start_cd.elf $(PKG_BUILD_DIR)/start_cd.elf\n\t$(CP) $(DL_DIR)/$(RPI_FIRMWARE_FILE)-start_x.elf $(PKG_BUILD_DIR)/start_x.elf\n\t$(CP) $(DL_DIR)/$(RPI_FIRMWARE_FILE)-start4.elf $(PKG_BUILD_DIR)/start4.elf\n\t$(CP) $(DL_DIR)/$(RPI_FIRMWARE_FILE)-start4cd.elf $(PKG_BUILD_DIR)/start4cd.elf\n\t$(CP) $(DL_DIR)/$(RPI_FIRMWARE_FILE)-start4x.elf $(PKG_BUILD_DIR)/start4x.elf\nendef\n\ndefine Build/Compile\n\ttrue\nendef\n\ndefine Package/bcm27xx-gpu-fw/install\n\ttrue\nendef\n\ndefine Build/InstallDev\n\t$(CP) $(PKG_BUILD_DIR)/bootcode.bin $(KERNEL_BUILD_DIR)\n\t$(CP) $(PKG_BUILD_DIR)/LICENCE.broadcom $(KERNEL_BUILD_DIR)\n\t$(CP) $(PKG_BUILD_DIR)/start.elf $(KERNEL_BUILD_DIR)\n\t$(CP) $(PKG_BUILD_DIR)/start_cd.elf $(KERNEL_BUILD_DIR)\n\t$(CP) $(PKG_BUILD_DIR)/start_x.elf $(KERNEL_BUILD_DIR)\n\t$(CP) $(PKG_BUILD_DIR)/start4.elf $(KERNEL_BUILD_DIR)\n\t$(CP) $(PKG_BUILD_DIR)/start4cd.elf $(KERNEL_BUILD_DIR)\n\t$(CP) $(PKG_BUILD_DIR)/start4x.elf $(KERNEL_BUILD_DIR)\n\t$(CP) $(PKG_BUILD_DIR)/fixup.dat $(KERNEL_BUILD_DIR)\n\t$(CP) $(PKG_BUILD_DIR)/fixup_cd.dat $(KERNEL_BUILD_DIR)\n\t$(CP) $(PKG_BUILD_DIR)/fixup_x.dat $(KERNEL_BUILD_DIR)\n\t$(CP) $(PKG_BUILD_DIR)/fixup4.dat $(KERNEL_BUILD_DIR)\n\t$(CP) $(PKG_BUILD_DIR)/fixup4cd.dat $(KERNEL_BUILD_DIR)\n\t$(CP) $(PKG_BUILD_DIR)/fixup4x.dat $(KERNEL_BUILD_DIR)\nendef\n\n$(eval $(call BuildPackage,bcm27xx-gpu-fw))\n"
  },
  {
    "path": "package/kernel/bcm63xx-cfe/Makefile",
    "content": "include $(TOPDIR)/rules.mk\ninclude $(INCLUDE_DIR)/kernel.mk\n\nPKG_NAME:=bcm63xx-cfe\nPKG_RELEASE:=1\n\nPKG_SOURCE_URL:=https://github.com/openwrt/bcm63xx-cfe.git\nPKG_SOURCE_PROTO:=git\nPKG_SOURCE_DATE:=2021-06-22\nPKG_SOURCE_VERSION:=e5050f37150b34deb547b50feccd0e7439cb5bd7\nPKG_MIRROR_HASH:=85fed9f4bdf23cf7d33a02f549ffe9073666890f786d5ffa484c0368552b75ae\n\nPKG_FLAGS:=nonshared\n\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine Package/bcm63xx-cfe\n  SECTION:=boot\n  CATEGORY:=Boot Loaders\n  DEPENDS:=@(TARGET_bcm4908||TARGET_bcm63xx||TARGET_bmips)\n  TITLE:=bcm63xx-cfe\n  DEFAULT:=y\nendef\n\ndefine Package/bcm63xx-cfe/description\n  CFE RAM binaries for bcm63xx.\nendef\n\ndefine Build/Compile\n\ttrue\nendef\n\ndefine Package/bcm63xx-cfe/install\n\ttrue\nendef\n\ndefine Build/InstallDev\n\trm -rf $(KERNEL_BUILD_DIR)/$(PKG_NAME)\n\tmkdir -p $(KERNEL_BUILD_DIR)/$(PKG_NAME)\n\t$(CP) -r $(PKG_BUILD_DIR)/* $(KERNEL_BUILD_DIR)/$(PKG_NAME)\nendef\n\n$(eval $(call BuildPackage,bcm63xx-cfe))\n"
  },
  {
    "path": "package/kernel/bpf-headers/Makefile",
    "content": "#\n# Copyright (C) 2006-2009 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\ninclude $(TOPDIR)/rules.mk\n\noverride QUILT:=\noverride HOST_QUILT:=\n\ninclude $(INCLUDE_DIR)/kernel.mk\n\n\nPKG_NAME:=linux\nPKG_PATCHVER:=5.15\n# Manually include kernel version and hash from kernel details file\ninclude $(INCLUDE_DIR)/kernel-$(PKG_PATCHVER)\n\nPKG_VERSION:=$(PKG_PATCHVER)$(strip $(LINUX_VERSION-$(PKG_PATCHVER)))\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz\nPKG_SOURCE_URL:=$(LINUX_SITE)\nPKG_HASH:=$(LINUX_KERNEL_HASH-$(strip $(PKG_VERSION)))\nPKG_BUILD_DIR:=$(KERNEL_BUILD_DIR)/bpf-headers/$(PKG_NAME)-$(PKG_VERSION)\n\nGENERIC_PLATFORM_DIR := $(CURDIR)/../../../target/linux/generic\nGENERIC_BACKPORT_DIR := $(GENERIC_PLATFORM_DIR)/backport$(if $(wildcard $(GENERIC_PLATFORM_DIR)/backport-$(PKG_PATCHVER)),-$(PKG_PATCHVER))\nGENERIC_PATCH_DIR := $(GENERIC_PLATFORM_DIR)/pending$(if $(wildcard $(GENERIC_PLATFORM_DIR)/pending-$(PKG_PATCHVER)),-$(PKG_PATCHVER))\nGENERIC_HACK_DIR := $(GENERIC_PLATFORM_DIR)/hack$(if $(wildcard $(GENERIC_PLATFORM_DIR)/hack-$(PKG_PATCHVER)),-$(PKG_PATCHVER))\nGENERIC_FILES_DIR := $(foreach dir,$(wildcard $(GENERIC_PLATFORM_DIR)/files $(GENERIC_PLATFORM_DIR)/files-$(PKG_PATCHVER)),\"$(dir)\")\nPATCH_DIR := $(CURDIR)/patches\nFILES_DIR :=\n\nREAL_LINUX_DIR := $(LINUX_DIR)\nLINUX_DIR := $(PKG_BUILD_DIR)\n\ninclude $(INCLUDE_DIR)/bpf.mk\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine Package/bpf-headers\n  SECTION:=kernel\n  CATEGORY:=Kernel\n  TITLE:=eBPF kernel headers\n  BUILDONLY:=1\n  HIDDEN:=1\nendef\n\nPKG_CONFIG_PATH:=\n\nexport HOST_EXTRACFLAGS=-I$(STAGING_DIR_HOST)/include\n\nKERNEL_MAKE := \\\n\t$(MAKE) -C $(PKG_BUILD_DIR) \\\n\t\tARCH=$(BPF_KARCH) \\\n\t\tCROSS_COMPILE=$(BPF_ARCH)-linux- \\\n\t\tLLVM=1 CC=\"$(CLANG)\" LD=\"$(TARGET_CROSS)ld\" \\\n\t\tHOSTCC=\"$(HOSTCC)\" \\\n\t\tHOSTCXX=\"$(HOSTCXX)\" \\\n\t\tHOST_LOADLIBES=\"-L$(STAGING_DIR_HOST)/lib\" \\\n\t\tKBUILD_HOSTLDLIBS=\"-L$(STAGING_DIR_HOST)/lib\" \\\n\t\tCONFIG_SHELL=\"$(BASH)\" \\\n\t\tINSTALL_HDR_PATH=\"$(PKG_BUILD_DIR)/user_headers\"\n\ndefine Build/Patch\n\t$(Kernel/Patch/Default)\nendef\n\nBPF_DOC = $(PKG_BUILD_DIR)/scripts/bpf_doc.py\n\ndefine Build/Configure/64\n\techo 'CONFIG_CPU_MIPS64_R2=y' >> $(PKG_BUILD_DIR)/.config\n\techo 'CONFIG_64BIT=y' >> $(PKG_BUILD_DIR)/.config\nendef\n\ndefine Build/Configure\n\tgrep -vE 'CONFIG_(CPU_.*ENDIAN|HZ)' $(PKG_BUILD_DIR)/arch/mips/configs/generic_defconfig > $(PKG_BUILD_DIR)/.config\n\techo 'CONFIG_CPU_$(if $(CONFIG_BIG_ENDIAN),BIG,LITTLE)_ENDIAN=y' >> $(PKG_BUILD_DIR)/.config\n\t$(if $(CONFIG_ARCH_64BIT),$(Build/Configure/64))\n\tgrep CONFIG_HZ $(REAL_LINUX_DIR)/.config >> $(PKG_BUILD_DIR)/.config\n\tyes '' | $(KERNEL_MAKE) oldconfig\n\tgrep 'CONFIG_HZ=' $(REAL_LINUX_DIR)/.config | \\\n\t\tcut -d= -f2 | \\\n\t\tbc -q $(LINUX_DIR)/kernel/time/timeconst.bc \\\n\t\t> $(LINUX_DIR)/include/generated/timeconst.h\n\t$(BPF_DOC) --header \\\n\t\t--file $(LINUX_DIR)/tools/include/uapi/linux/bpf.h \\\n\t\t> $(PKG_BUILD_DIR)/tools/lib/bpf/bpf_helper_defs.h\nendef\n\ndefine Build/Compile\n\t$(KERNEL_MAKE) archprepare headers_install\nendef\n\ndefine Build/InstallDev\n\tmkdir -p $(1)/bpf-headers/arch $(1)/bpf-headers/tools\n\t$(CP) \\\n\t\t$(PKG_BUILD_DIR)/arch/$(BPF_KARCH) \\\n\t\t$(1)/bpf-headers/arch/\n\t$(CP) \\\n\t\t$(PKG_BUILD_DIR)/tools/lib \\\n\t\t$(PKG_BUILD_DIR)/tools/testing \\\n\t\t$(1)/bpf-headers/tools/\n\t$(CP) \\\n\t\t$(PKG_BUILD_DIR)/include \\\n\t\t$(PKG_BUILD_DIR)/samples \\\n\t\t$(PKG_BUILD_DIR)/scripts \\\n\t\t$(PKG_BUILD_DIR)/user_headers \\\n\t\t$(1)/bpf-headers\n\t$(CP) \\\n\t\t$(CURDIR)/files/stdarg.h \\\n\t\t$(1)/bpf-headers/include\nendef\n\n$(eval $(call BuildPackage,bpf-headers))\n"
  },
  {
    "path": "package/kernel/bpf-headers/files/stdarg.h",
    "content": "#ifndef _STDARG_H\n#define _STDARG_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\ntypedef __builtin_va_list va_list;\n\n#define va_start(v,l)   __builtin_va_start(v,l)\n#define va_end(v)       __builtin_va_end(v)\n#define va_arg(v,l)     __builtin_va_arg(v,l)\n#define va_copy(d,s)    __builtin_va_copy(d,s)\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif\n"
  },
  {
    "path": "package/kernel/bpf-headers/patches/100-support_hz_300.patch",
    "content": "--- a/arch/mips/Kconfig\n+++ b/arch/mips/Kconfig\n@@ -2988,6 +2988,9 @@ choice\n \tconfig HZ_256\n \t\tbool \"256 HZ\" if SYS_SUPPORTS_256HZ || SYS_SUPPORTS_ARBIT_HZ\n \n+\tconfig HZ_300\n+\t\tbool \"300 HZ\" if SYS_SUPPORTS_ARBIT_HZ\n+\n \tconfig HZ_1000\n \t\tbool \"1000 HZ\" if SYS_SUPPORTS_1000HZ || SYS_SUPPORTS_ARBIT_HZ\n \n@@ -3039,6 +3042,7 @@ config HZ\n \tdefault 128 if HZ_128\n \tdefault 250 if HZ_250\n \tdefault 256 if HZ_256\n+\tdefault 300 if HZ_300\n \tdefault 1000 if HZ_1000\n \tdefault 1024 if HZ_1024\n \n"
  },
  {
    "path": "package/kernel/bpf-headers/src/include/generated/bounds.h",
    "content": "#ifndef __LINUX_BOUNDS_H__\n#define __LINUX_BOUNDS_H__\n/*\n * DO NOT MODIFY.\n *\n * This file was generated by Kbuild\n */\n\n#define NR_PAGEFLAGS 23 /* __NR_PAGEFLAGS */\n#define MAX_NR_ZONES 4 /* __MAX_NR_ZONES */\n#define NR_CPUS_BITS 1 /* ilog2(CONFIG_NR_CPUS) */\n#define SPINLOCK_SIZE 64 /* sizeof(spinlock_t) */\n\n#endif\n"
  },
  {
    "path": "package/kernel/broadcom-wl/Makefile",
    "content": "#\n# Copyright (C) 2006-2014 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\ninclude $(INCLUDE_DIR)/kernel.mk\n\nPKG_NAME:=broadcom-wl\nPKG_VERSION:=5.10.56.27.3\nPKG_RELEASE:=10\n\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION)_$(ARCH).tar.bz2\nPKG_SOURCE_URL:=@OPENWRT\n\nifeq ($(ARCH),mipsel)\nPKG_HASH:=26a8c370f48fc129d0731cfd751c36cae1419b0bc8ca35781126744e60eae009\nendif\nifeq ($(ARCH),mips)\nPKG_HASH:=ca6a86ca3e3e9c85b6dbb665b35bcbf338c37829c1b2f1994487d55664886045\nendif\n\nPKG_EXTMOD_SUBDIRS:=driver driver-mini glue\n\nPKG_USE_MIPS16:=0\nPKG_FLAGS:=nonshared\n\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine Package/broadcom-wl/Default\n  SECTION:=kernel\n  CATEGORY:=Kernel modules\n  DEPENDS:=@(PACKAGE_kmod-brcm-wl||PACKAGE_kmod-brcm-wl-mini)\n  SUBMENU:=Proprietary BCM43xx WiFi driver\n  SUBMENUDEP:=(TARGET_bcm47xx||TARGET_bcm63xx)\nendef\n\ndefine KernelPackage/brcm-wl/Default\n  $(call Package/broadcom-wl/Default)\n  SECTION:=kernel\n  DEPENDS:=@(TARGET_bcm47xx||TARGET_bcm63xx) +wireless-tools\n  TITLE:=Kernel driver for BCM43xx chipsets\n  FILES:=$(PKG_BUILD_DIR)/driver$(1)/wl.ko $(PKG_BUILD_DIR)/glue/wl_glue.ko\n  AUTOLOAD:=$(call AutoProbe,wl)\nendef\n\ndefine KernelPackage/brcm-wl/Default/description\n This package contains the proprietary wireless driver for the Broadcom \n BCM43xx chipset.\nendef\n\ndefine KernelPackage/brcm-wl\n$(call KernelPackage/brcm-wl/Default,)\n  TITLE+= (normal version)\nendef\n\ndefine KernelPackage/brcm-wl/description\n$(call KernelPackage/brcm-wl/Default/description)\nendef\n\ndefine KernelPackage/brcm-wl-mini\n$(call KernelPackage/brcm-wl/Default,-mini)\n  TITLE+= (Legacy version)\nendef\n\ndefine KernelPackage/brcm-wl-mini/description\n$(call KernelPackage/brcm-wl/Default/description)\nendef\n\ndefine Package/wlc\n$(call Package/broadcom-wl/Default)\n  TITLE:=wl driver setup utility\nendef\n\ndefine Package/wlc/description\n This package contains an utility for initializing the proprietary Broadcom \n wl driver.\nendef\n\ndefine Package/wl\n$(call Package/broadcom-wl/Default)\n  TITLE:=Proprietary Broadcom wl driver config utility\nendef\n\ndefine Package/wl/description\n This package contains the proprietary utility (wl) for configuring the \n proprietary Broadcom wl driver.\nendef\n\ndefine Package/nas\n$(call Package/broadcom-wl/Default)\n  TITLE:=Proprietary Broadcom WPA/WPA2 authenticator\nendef\n\ndefine Package/nas/description\n This package contains the proprietary WPA/WPA2 authenticator (nas) for the \n proprietary Broadcom wl driver.\nendef\n\nMAKE_KMOD := $(MAKE) -C \"$(LINUX_DIR)\" \\\n\t\t$(KERNEL_MAKE_FLAGS) \\\n\t\tPATH=\"$(TARGET_PATH)\" \\\n\t\tM=\"$(PKG_BUILD_DIR)/kmod\" \\\n\ndefine Build/Prepare\n\t$(call Build/Prepare/Default)\n\t$(CP) $(PKG_BUILD_DIR)/driver $(PKG_BUILD_DIR)/driver-mini\n\t$(CP) ./src/glue $(PKG_BUILD_DIR)/glue\nendef\n\ndefine Build/Compile\n\t# Compile glue driver\n\t$(MAKE_KMOD) -C \"$(LINUX_DIR)\" \\\n\t\tM=\"$(PKG_BUILD_DIR)/glue\" \\\n\t\tmodules\n\n\t# Compile the kernel part\n\t$(MAKE_KMOD) \\\n\t\tM=\"$(PKG_BUILD_DIR)/driver\" \\\n\t\tMODFLAGS=\"-DMODULE -mlong-calls\" \\\n\t\tKBUILD_EXTRA_SYMBOLS=\"$(PKG_BUILD_DIR)/glue/Module.symvers\" \\\n\t\tmodules\n\n\t$(MAKE_KMOD) \\\n\t\tM=\"$(PKG_BUILD_DIR)/driver-mini\" \\\n\t\tMODFLAGS=\"-DMODULE -mlong-calls\" \\\n\t\tBUILD_TYPE=\"wl_apsta_mini\" \\\n\t\tKBUILD_EXTRA_SYMBOLS=\"$(PKG_BUILD_DIR)/glue/Module.symvers\" \\\n\t\tmodules\n\n\t# Compile libshared\n\t$(MAKE) -C $(PKG_BUILD_DIR)/shared \\\n\t\t$(TARGET_CONFIGURE_OPTS) \\\n\t\tCFLAGS=\"$(TARGET_CFLAGS) -I. -I$(PKG_BUILD_DIR)/driver/include\" \\\n\t\tall\n\n\t$(TARGET_CC) -o $(PKG_BUILD_DIR)/wlc \\\n\t\t-I$(PKG_BUILD_DIR)/shared -I$(PKG_BUILD_DIR)/driver/include \\\n\t\t./src/wlc.c $(PKG_BUILD_DIR)/shared/libshared.a\n\n\t$(TARGET_CC) -o $(PKG_BUILD_DIR)/nas \\\n\t\t$(PKG_BUILD_DIR)/nas_exe.o \\\n\t\t$(PKG_BUILD_DIR)/shared/libshared.a\n\n\t$(TARGET_CC) -o $(PKG_BUILD_DIR)/wl \\\n\t\t$(PKG_BUILD_DIR)/wl_exe.o \\\n\t\t$(PKG_BUILD_DIR)/shared/libshared.a\nendef\n\ndefine Build/InstallDev\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(CP) $(PKG_BUILD_DIR)/shared/libshared.a $(1)/usr/lib/\nendef\n\ndefine Package/wlc/install\n\t$(CP) ./files/* $(1)/\n\t$(INSTALL_DIR) $(1)/sbin\n\t$(INSTALL_BIN) $(PKG_BUILD_DIR)/wlc $(1)/sbin/\nendef\n\ndefine Package/wlc/postinst\n#!/bin/sh\n[ -n \"$${IPKG_INSTROOT}\" ] || /etc/init.d/wlunbind enable || true\nendef\n\ndefine Package/wl/install\n\t$(INSTALL_DIR) $(1)/usr/sbin\n\t$(INSTALL_BIN) $(PKG_BUILD_DIR)/wl $(1)/usr/sbin/\nendef\n\ndefine Package/nas/install\n\t$(INSTALL_DIR) $(1)/usr/sbin\n\t$(INSTALL_BIN) $(PKG_BUILD_DIR)/nas $(1)/usr/sbin/\n\t$(LN) nas $(1)/usr/sbin/nas4not\n\t$(LN) nas $(1)/usr/sbin/nas4wds\nendef\n\n$(eval $(call KernelPackage,brcm-wl))\n$(eval $(call KernelPackage,brcm-wl-mini))\n$(eval $(call BuildPackage,wlc))\n$(eval $(call BuildPackage,wl))\n$(eval $(call BuildPackage,nas))\n"
  },
  {
    "path": "package/kernel/broadcom-wl/files/etc/hotplug.d/net/00-broadcom-wifi-detect",
    "content": "#!/bin/sh\n\n[ \"${ACTION}\" = \"add\" ] && [ \"${INTERFACE%%[0-9]}\" = \"wl\" ] && {\n\t/sbin/wifi config\n}\n"
  },
  {
    "path": "package/kernel/broadcom-wl/files/etc/hotplug.d/net/20-broadcom_wds",
    "content": "include /lib/wifi\n\nsetup_broadcom_wds() {\n\tlocal iface=\"$1\"\n\tlocal remote=\"$(wlc ifname \"$iface\" wdsmac)\"\n\n\t[ -z \"$remote\" ] && return\n\t\n\tconfig_cb() {\n\t\t[ -z \"$CONFIG_SECTION\" ] && return\n\t\n\t\tconfig_get type \"$CONFIG_SECTION\" TYPE\n\t\t[ \"$type\" = \"wifi-iface\" ] || return\n\t\t\n\t\tconfig_get network \"$CONFIG_SECTION\" network\n\t\t[ -z \"$network\" ] && return\n\t\t\n\t\tconfig_get addr \"$CONFIG_SECTION\" bssid\n\t\taddr=$(echo \"$addr\" | tr 'A-F' 'a-f')\n\t\t[ \"$addr\" = \"$remote\" ] && {\n\t\t\tlocal cfg=\"$CONFIG_SECTION\"\n\t\t\t\n\t\t\tinclude /lib/network\n\t\t\tscan_interfaces\n\n\t\t\tfor network in $network; do\n\t\t\t\tsetup_interface \"$iface\" \"$network\"\n\t\t\tdone\n\t\t\t\n\t\t\tconfig_get encryption \"$cfg\" encryption\n\t\t\tconfig_get key \"$cfg\" key\n\t\t\tconfig_get ssid \"$cfg\" ssid\n\t\t\n\t\t\t[ \"$encryption\" != \"none\" ] && {\n\t\t\t\tsleep 5\n\t\t\t\tcase \"$encryption\" in\n\t\t\t\t\tpsk|PSK)\n\t\t\t\t\t\tnas4not \"$network\" \"$iface\" up auto tkip psk \"$key\" \"$ssid\"\n\t\t\t\t\t\t;;\n\t\t\t\t\tpsk2|PSK2)\n\t\t\t\t\t\tnas4not \"$network\" \"$iface\" up auto aes psk \"$key\" \"$ssid\"\n\t\t\t\t\t\t;;\n\t\t\t\t\tpsk+psk2|psk2+psk|PSK+PSK2|PSK2+PSK)\n\t\t\t\t\t\tnas4not \"$network\" \"$iface\" up auto aes+tkip psk \"$key\" \"$ssid\"\n\t\t\t\t\t\t;;\n\t\t\t\t\t*)\n\t\t\t\t\t\tnas4not lan \"$iface\" up auto aes \"$encryption\" \"$key\" \"$ssid\"\n\t\t\t\t\t\t;;\n\t\t\t\t\tesac\n\t\t\t}\n\t\t}\n\t}\n\n\tconfig_load wireless\n}\n\ncase \"$ACTION\" in\n\tadd|register)\n\t\t[ \"${INTERFACE%%[0-1]-*}\" = wds ] && setup_broadcom_wds \"$INTERFACE\"\n\t;;\nesac\n"
  },
  {
    "path": "package/kernel/broadcom-wl/files/etc/init.d/wlunbind",
    "content": "#!/bin/sh /etc/rc.common\n# Copyright (C) 2010-2011 OpenWrt.org\n\nSTART=09\n\nunbind_driver() {\n\tlocal driver=\"$1\"\n\tlocal sysfs=\"/sys/bus/pci/drivers/$driver\"\n\tif [ -d \"$sysfs\" ]; then\n\t\tlocal lnk\n\t\tfor lnk in $sysfs/*; do\n\t\t\t[ -h \"$lnk\" ] || continue\n\t\t\tcase \"${lnk##*/}\" in\n\t\t\t\t*:*:*.*)\n\t\t\t\t\tlogger \"Unbinding WL PCI device ${lnk##*/} from $driver\"\n\t\t\t\t\techo -n \"${lnk##*/}\" > \"$sysfs/unbind\"\n\t\t\t\t;;\n\t\t\tesac\n\t\tdone\n\tfi\n}\n\nboot() {\n\tunbind_driver b43-pci-bridge\n\tunbind_driver bcma-pci-bridge\n}\n\nstart() { :; }\nstop() { :; }\n"
  },
  {
    "path": "package/kernel/broadcom-wl/files/lib/wifi/broadcom.sh",
    "content": "append DRIVERS \"broadcom\"\n\nscan_broadcom() {\n\tlocal device=\"$1\"\n\tlocal vif vifs wds\n\tlocal adhoc sta apmode mon disabled\n\tlocal adhoc_if sta_if ap_if mon_if\n\n\tconfig_get vifs \"$device\" vifs\n\tfor vif in $vifs; do\n\t\tconfig_get_bool disabled \"$vif\" disabled 0\n\t\t[ $disabled -eq 0 ] || continue\n\n\t\tlocal mode\n\t\tconfig_get mode \"$vif\" mode\n\t\tcase \"$mode\" in\n\t\t\tadhoc)\n\t\t\t\tadhoc=1\n\t\t\t\tadhoc_if=\"$vif\"\n\t\t\t;;\n\t\t\tsta)\n\t\t\t\tsta=1\n\t\t\t\tsta_if=\"$vif\"\n\t\t\t;;\n\t\t\tap)\n\t\t\t\tapmode=1\n\t\t\t\tap_if=\"${ap_if:+$ap_if }$vif\"\n\t\t\t;;\n\t\t\twds)\n\t\t\t\tlocal addr\n\t\t\t\tconfig_get addr \"$vif\" bssid\n\t\t\t\t[ -z \"$addr\" ] || {\n\t\t\t\t\taddr=$(echo \"$addr\" | tr 'A-F' 'a-f')\n\t\t\t\t\tappend wds \"$addr\"\n\t\t\t\t}\n\t\t\t;;\n\t\t\tmonitor)\n\t\t\t\tmon=1\n\t\t\t\tmon_if=\"$vif\"\n\t\t\t;;\n\t\t\t*) echo \"$device($vif): Invalid mode\";;\n\t\tesac\n\tdone\n\tconfig_set \"$device\" wds \"$wds\"\n\n\tlocal _c=\n\tfor vif in ${adhoc_if:-$sta_if $ap_if $mon_if}; do\n\t\tconfig_set \"$vif\" ifname \"${device}${_c:+-$_c}\"\n\t\t_c=$((${_c:-0} + 1))\n\tdone\n\tconfig_set \"$device\" vifs \"${adhoc_if:-$sta_if $ap_if $mon_if}\"\n\n\tap=1\n\tinfra=1\n\tif [ \"$_c\" -gt 1 ]; then\n\t\tmssid=1\n\telse\n\t\tmssid=\n\tfi\n\tapsta=0\n\tradio=1\n\tmonitor=0\n\tcase \"$adhoc:$sta:$apmode:$mon\" in\n\t\t1*)\n\t\t\tap=0\n\t\t\tmssid=\n\t\t\tinfra=0\n\t\t;;\n\t\t:1:1:)\n\t\t\tapsta=1\n\t\t\twet=1\n\t\t;;\n\t\t:1::)\n\t\t\twet=1\n\t\t\tap=0\n\t\t\tmssid=\n\t\t;;\n\t\t:::1)\n\t\t\twet=1\n\t\t\tap=0\n\t\t\tmssid=\n\t\t\tmonitor=1\n\t\t;;\n\t\t::)\n\t\t\tradio=0\n\t\t;;\n\tesac\n}\n\ndisable_broadcom() {\n\tlocal device=\"$1\"\n\tset_wifi_down \"$device\"\n\t(\n\t\tinclude /lib/network\n\n\t\tlocal pid_file=/var/run/nas.$device.pid\n\t\t[ -e $pid_file ] && start-stop-daemon -K -q -s SIGKILL -p $pid_file && rm $pid_file\n\n\t\t# make sure the interfaces are down and removed from all bridges\n\t\tlocal dev ifname\n\t\tfor dev in /sys/class/net/wds${device##wl}-* /sys/class/net/${device}-* /sys/class/net/${device}; do\n\t\t\tif [ -e \"$dev\" ]; then\n\t\t\t\tifname=${dev##/sys/class/net/}\n\t\t\t\tip link set dev \"$ifname\" down\n\t\t\t\tunbridge \"$ifname\"\n\t\t\tfi\n\t\tdone\n\n\t\t# make sure all of the devices are disabled in the driver\n\t\tlocal ifdown=\n\t\tlocal bssmax=$(wlc ifname \"$device\" bssmax)\n\t\tlocal vif=$((${bssmax:-4} - 1))\n\t\tappend ifdown \"down\" \"$N\"\n\t\tappend ifdown \"wds none\" \"$N\"\n\t\twhile [ $vif -ge 0 ]; do\n\t\t\tappend ifdown \"vif $vif\" \"$N\"\n\t\t\tappend ifdown \"enabled 0\" \"$N\"\n\t\t\tvif=$(($vif - 1))\n\t\tdone\n\n\t\twlc ifname \"$device\" stdin <<EOF\n$ifdown\nleddc 0xffff\nEOF\n\t)\n\ttrue\n}\n\nenable_broadcom() {\n\tlocal device=\"$1\"\n\tlocal channel country maxassoc wds vifs distance slottime rxantenna txantenna\n\tlocal frameburst macfilter maclist macaddr txpower frag rts hwmode htmode\n\tconfig_get channel \"$device\" channel\n\tconfig_get country \"$device\" country\n\tconfig_get maxassoc \"$device\" maxassoc\n\tconfig_get wds \"$device\" wds\n\tconfig_get vifs \"$device\" vifs\n\tconfig_get distance \"$device\" distance\n\tconfig_get slottime \"$device\" slottime\n\tconfig_get rxantenna \"$device\" rxantenna\n\tconfig_get txantenna \"$device\" txantenna\n\tconfig_get_bool frameburst \"$device\" frameburst\n\tconfig_get macfilter \"$device\" macfilter\n\tconfig_get maclist \"$device\" maclist\n\tconfig_get macaddr \"$device\" macaddr $(wlc ifname \"$device\" default_bssid)\n\tconfig_get txpower \"$device\" txpower\n\tconfig_get frag \"$device\" frag\n\tconfig_get rts \"$device\" rts\n\tconfig_get hwmode \"$device\" hwmode\n\tconfig_get htmode \"$device\" htmode\n\tlocal doth=0\n\tlocal wmm=1\n\n\t[ -z \"$slottime\" ] && {\n\t\t[ -n \"$distance\" ] && {\n\t\t\t# slottime = 9 + (distance / 150) + (distance % 150 ? 1 : 0)\n\t\t\tslottime=\"$((9 + ($distance / 150) + 1 - (150 - ($distance % 150)) / 150 ))\"\n\t\t}\n\t} || {\n\t\tslottime=\"${slottime:--1}\"\n\t}\n\n\tcase \"$macfilter\" in\n\t\tallow|2)\n\t\t\tmacfilter=2;\n\t\t;;\n\t\tdeny|1)\n\t\t\tmacfilter=1;\n\t\t;;\n\t\tdisable|none|0)\n\t\t\tmacfilter=0;\n\t\t;;\n\tesac\n\n\tlocal gmode=2 nmode=0 nreqd=\n\tcase \"$hwmode\" in\n\t\t*a)\tgmode=;;\n\t\t*b)\tgmode=0;;\n\t\t*bg)\tgmode=1;;\n\t\t*g)\tgmode=2;;\n\t\t*gst)\tgmode=4;;\n\t\t*lrs)\tgmode=5;;\n\t\t*)\tnmode=1; nreqd=0;;\n\tesac\n\n\tcase \"$hwmode\" in\n\t\tn|11n)\tnmode=1; nreqd=1;;\n\t\t*n*)\tnmode=1; nreqd=0;;\n\tesac\n\n        # Use 'nmode' for N-Phy only\n\t[ \"$(wlc ifname \"$device\" phytype)\" = 4 ] || nmode=\n\n\tlocal band chanspec\n\t[ ${channel:-0} -ge 1 -a ${channel:-0} -le 14 ] && band=2\n\t[ ${channel:-0} -ge 36 ] && {\n\t\tband=1\n\t\tgmode=\n\t}\n\n\t# Use 'chanspec' instead of 'channel' for 'N' modes (See bcmwifi.h)\n\t[ -n \"$nmode\" -a -n \"$band\" -a -n \"$channel\" ] && {\n\t\tcase \"$htmode\" in\n\t\t\tHT40)\n\t\t\t\tif [ -n \"$gmode\" ]; then\n\t\t\t\t\t[ $channel -lt 7 ] && htmode=\"HT40+\" || htmode=\"HT40-\"\n\t\t\t\telse\n\t\t\t\t\t[ $(( ($channel / 4) % 2 )) -eq 1 ] && htmode=\"HT40+\" || htmode=\"HT40-\"\n\t\t\t\tfi\n\t\t\t;;\n\t\tesac\n\t\tcase \"$htmode\" in\n\t\t\tHT40-)\tchanspec=$(printf 0x%x%x%02x $band 0xe $(($channel - 2))); nmode=1; channel=;;\n\t\t\tHT40+)\tchanspec=$(printf 0x%x%x%02x $band 0xd $(($channel + 2))); nmode=1; channel=;;\n\t\t\tHT20)\tchanspec=$(printf 0x%x%x%02x $band 0xb $channel); nmode=1; channel=;;\n\t\t\t*) ;;\n\t\tesac\n\t}\n\n\tlocal leddc=$(wlc ifname \"$device\" leddc)\n\t[ $((leddc)) -eq $((0xffff)) ] && {\n\t\tleddc=0x005a000a;\n\t}\n\n\tlocal _c=0\n\tlocal nas=\"$(command -v nas)\"\n\tlocal if_pre_up if_up nas_cmd\n\tlocal vif vif_pre_up vif_post_up vif_do_up vif_txpower\n\tlocal bssmax=$(wlc ifname \"$device\" bssmax)\n\tbssmax=${bssmax:-4}\n\n\tfor vif in $vifs; do\n\t\t[ $_c -ge $bssmax ] && break\n\n\t\tconfig_get vif_txpower \"$vif\" txpower\n\n\t\tlocal mode\n\t\tconfig_get mode \"$vif\" mode\n\t\tappend vif_pre_up \"vif $_c\" \"$N\"\n\t\tappend vif_post_up \"vif $_c\" \"$N\"\n\t\tappend vif_do_up \"vif $_c\" \"$N\"\n\n\t\tconfig_get_bool wmm \"$vif\" wmm \"$wmm\"\n\t\tconfig_get_bool doth \"$vif\" doth \"$doth\"\n\n\t\t[ \"$mode\" = \"sta\" ] || {\n\t\t\tlocal hidden isolate\n\t\t\tconfig_get_bool hidden \"$vif\" hidden 0\n\t\t\tappend vif_pre_up \"closed $hidden\" \"$N\"\n\t\t\tconfig_get_bool isolate \"$vif\" isolate 0\n\t\t\tappend vif_pre_up \"ap_isolate $isolate\" \"$N\"\n\t\t}\n\n\t\tlocal wsec_r=0\n\t\tlocal eap_r=0\n\t\tlocal wsec=0\n\t\tlocal auth=0\n\t\tlocal nasopts=\n\t\tlocal enc key rekey\n\n\t\tconfig_get enc \"$vif\" encryption\n\t\tcase \"$enc\" in\n\t\t\t*wep*)\n\t\t\t\tlocal def defkey k knr\n\t\t\t\twsec_r=1\n\t\t\t\twsec=1\n\t\t\t\tdefkey=1\n\t\t\t\tconfig_get key \"$vif\" key\n\t\t\t\tcase \"$enc\" in\n\t\t\t\t\t*shared*) append vif_do_up \"wepauth 1\" \"$N\";;\n\t\t\t\t\t*) append vif_do_up \"wepauth 0\" \"$N\";;\n\t\t\t\tesac\n\t\t\t\tcase \"$key\" in\n\t\t\t\t\t[1234])\n\t\t\t\t\t\tdefkey=\"$key\"\n\t\t\t\t\t\tfor knr in 1 2 3 4; do\n\t\t\t\t\t\t\tconfig_get k \"$vif\" key$knr\n\t\t\t\t\t\t\t[ -n \"$k\" ] || continue\n\t\t\t\t\t\t\t[ \"$defkey\" = \"$knr\" ] && def=\"=\" || def=\"\"\n\t\t\t\t\t\t\tappend vif_do_up \"wepkey $def$knr,$k\" \"$N\"\n\t\t\t\t\t\tdone\n\t\t\t\t\t;;\n\t\t\t\t\t\"\");;\n\t\t\t\t\t*) append vif_do_up \"wepkey =1,$key\" \"$N\";;\n\t\t\t\tesac\n\t\t\t;;\n\t\t\t*psk*)\n\t\t\t\twsec_r=1\n\t\t\t\tconfig_get key \"$vif\" key\n\n\t\t\t\t# psk version + default cipher\n\t\t\t\tcase \"$enc\" in\n\t\t\t\t\t*mixed*|*psk+psk2*) auth=132; wsec=6;;\n\t\t\t\t\t*psk2*) auth=128; wsec=4;;\n\t\t\t\t\t*) auth=4; wsec=2;;\n\t\t\t\tesac\n\n\t\t\t\t# cipher override\n\t\t\t\tcase \"$enc\" in\n\t\t\t\t\t*tkip+aes*|*tkip+ccmp*|*aes+tkip*|*ccmp+tkip*) wsec=6;;\n\t\t\t\t\t*aes*|*ccmp*) wsec=4;;\n\t\t\t\t\t*tkip*) wsec=2;;\n\t\t\t\tesac\n\n\t\t\t\t# group rekey interval\n\t\t\t\tconfig_get rekey \"$vif\" wpa_group_rekey\n\n\t\t\t\teval \"${vif}_key=\\\"\\$key\\\"\"\n\t\t\t\tnasopts=\"-k \\\"\\$${vif}_key\\\"${rekey:+ -g $rekey}\"\n\t\t\t;;\n\t\t\t*wpa*)\n\t\t\t\tlocal auth_port auth_secret auth_server\n\t\t\t\twsec_r=1\n\t\t\t\teap_r=1\n\t\t\t\tconfig_get auth_server \"$vif\" auth_server\n\t\t\t\t[ -z \"$auth_server\" ] && config_get auth_server \"$vif\" server\n\t\t\t\tconfig_get auth_port \"$vif\" auth_port\n\t\t\t\t[ -z \"$auth_port\" ] && config_get auth_port \"$vif\" port\n\t\t\t\tconfig_get auth_secret \"$vif\" auth_secret\n\t\t\t\t[ -z \"$auth_secret\" ] && config_get auth_secret \"$vif\" key\n\n\t\t\t\t# wpa version + default cipher\n\t\t\t\tcase \"$enc\" in\n\t\t\t\t\t*mixed*|*wpa+wpa2*) auth=66; wsec=6;;\n\t\t\t\t\t*wpa2*) auth=64; wsec=4;;\n\t\t\t\t\t*) auth=2; wsec=2;;\n\t\t\t\tesac\n\n\t\t\t\t# cipher override\n\t\t\t\tcase \"$enc\" in\n\t\t\t\t\t*tkip+aes*|*tkip+ccmp*|*aes+tkip*|*ccmp+tkip*) wsec=6;;\n\t\t\t\t\t*aes*|*ccmp*) wsec=4;;\n\t\t\t\t\t*tkip*) wsec=2;;\n\t\t\t\tesac\n\n\t\t\t\t# group rekey interval\n\t\t\t\tconfig_get rekey \"$vif\" wpa_group_rekey\n\n\t\t\t\teval \"${vif}_key=\\\"\\$auth_secret\\\"\"\n\t\t\t\tnasopts=\"-r \\\"\\$${vif}_key\\\" -h $auth_server -p ${auth_port:-1812}${rekey:+ -g $rekey}\"\n\t\t\t;;\n\t\tesac\n\t\tappend vif_do_up \"wsec $wsec\" \"$N\"\n\t\tappend vif_do_up \"wpa_auth $auth\" \"$N\"\n\t\tappend vif_do_up \"wsec_restrict $wsec_r\" \"$N\"\n\t\tappend vif_do_up \"eap_restrict $eap_r\" \"$N\"\n\n\t\tlocal ssid\n\t\tconfig_get ssid \"$vif\" ssid\n\t\tappend vif_post_up \"vlan_mode 0\" \"$N\"\n\t\tappend vif_pre_up \"ssid $ssid\" \"$N\"\n\n\t\t[ \"$mode\" = \"monitor\" ] && {\n\t\t\tappend vif_post_up \"monitor $monitor\" \"$N\"\n\t\t}\n\n\t\t[ \"$mode\" = \"adhoc\" ] && {\n\t\t\tlocal bssid\n\t\t\tconfig_get bssid \"$vif\" bssid\n\t\t\t[ -n \"$bssid\" ] && {\n\t\t\t\tappend vif_pre_up \"bssid $bssid\" \"$N\"\n\t\t\t\tappend vif_pre_up \"ibss_merge 0\" \"$N\"\n\t\t\t} || {\n\t\t\t\tappend vif_pre_up \"ibss_merge 1\" \"$N\"\n\t\t\t}\n\t\t}\n\n\t\tappend vif_post_up \"enabled 1\" \"$N\"\n\n\t\tlocal ifname\n\t\tconfig_get ifname \"$vif\" ifname\n\t\tlocal if_cmd=\"if_pre_up\"\n\t\t[ \"$ifname\" != \"${ifname##${device}-}\" ] && if_cmd=\"if_up\"\n\t\tappend $if_cmd \"macaddr=\\$(wlc ifname '$ifname' cur_etheraddr)\" \";$N\"\n\t\tappend $if_cmd \"ip link set dev '$ifname' address \\$macaddr\" \";$N\"\n\t\tappend if_up \"ip link set dev '$ifname' up\" \";$N\"\n\n\t\tlocal net_cfg=\"$(find_net_config \"$vif\")\"\n\t\t[ -z \"$net_cfg\" ] || {\n\t\t\tubus -t 30 wait_for network.interface.\"$net_cfg\"\n\t\t\tappend if_up \"set_wifi_up '$vif' '$ifname'\" \";$N\"\n\t\t\tappend if_up \"start_net '$ifname' '$net_cfg'\" \";$N\"\n\t\t}\n\t\t[ -z \"$nas\" -o -z \"$nasopts\" ] || {\n\t\t\teval \"${vif}_ssid=\\\"\\$ssid\\\"\"\n\t\t\tlocal nas_mode=\"-A\"\n\t\t\t[ \"$mode\" = \"sta\" ] && nas_mode=\"-S\"\n\t\t\t[ -z \"$nas_cmd\" ] && {\n\t\t\t\tlocal pid_file=/var/run/nas.$device.pid\n\t\t\t\tnas_cmd=\"start-stop-daemon -S -b -p $pid_file -x $nas -- -P $pid_file -H 34954\"\n\t\t\t}\n\t\t\tappend nas_cmd \"-i $ifname $nas_mode -m $auth -w $wsec -s \\\"\\$${vif}_ssid\\\" -g 3600 -F $nasopts\"\n\t\t}\n\t\t_c=$(($_c + 1))\n\tdone\n\twlc ifname \"$device\" stdin <<EOF\n${macaddr:+bssid $macaddr}\n${macaddr:+cur_etheraddr $macaddr}\nband ${band:-0}\n${nmode:+nmode $nmode}\n${nmode:+${nreqd:+nreqd $nreqd}}\n${gmode:+gmode $gmode}\nleddc $leddc\napsta $apsta\nap $ap\n${mssid:+mssid $mssid}\ninfra $infra\n${wet:+wet 1}\n802.11d 0\n802.11h ${doth:-0}\nwme ${wmm:-1}\nrxant ${rxantenna:-3}\ntxant ${txantenna:-3}\nfragthresh ${frag:-2346}\nrtsthresh ${rts:-2347}\nmonitor ${monitor:-0}\n\nradio ${radio:-1}\nmacfilter ${macfilter:-0}\nmaclist ${maclist:-none}\n${wds:+wds $wds}\ncountry ${country:-US}\n${channel:+channel $channel}\n${chanspec:+chanspec $chanspec}\nmaxassoc ${maxassoc:-128}\nslottime ${slottime:--1}\n${frameburst:+frameburst $frameburst}\n\n$vif_pre_up\nEOF\n\teval \"$if_pre_up\"\n\twlc ifname \"$device\" stdin <<EOF\nup\n$vif_post_up\nEOF\n\teval \"$if_up\"\n\twlc ifname \"$device\" stdin <<EOF\n$vif_do_up\nEOF\n\n\t# use vif_txpower (from last wifi-iface) instead of txpower (from\n\t# wifi-device) if the latter does not exist\n\ttxpower=${txpower:-$vif_txpower}\n\t[ -z \"$txpower\" ] || iwconfig $device txpower ${txpower}dBm\n\n\t# fd 1000 is an inherited lock file descriptor for preventing concurrent\n\t# init script executions. Close it here to prevent the nas daemon from\n\t# inheriting it further to avoid holding the lock indefinitely.\n\teval \"$nas_cmd 1000>&-\"\n}\n\n\ndetect_broadcom() {\n\tlocal i=-1\n\n\twhile grep -qs \"^ *wl$((++i)):\" /proc/net/dev; do\n\t\tlocal channel type\n\n\t\tconfig_get type wl${i} type\n\t\t[ \"$type\" = broadcom ] && continue\n\t\tchannel=`wlc ifname wl${i} channel`\n\n\t\tuci -q batch <<-EOF\n\t\t\tset wireless.wl${i}=wifi-device\n\t\t\tset wireless.wl${i}.type=broadcom\n\t\t\tset wireless.wl${i}.channel=${channel:-11}\n\t\t\tset wireless.wl${i}.txantenna=3\n\t\t\tset wireless.wl${i}.rxantenna=3\n\t\t\tset wireless.wl${i}.disabled=1\n\n\t\t\tset wireless.default_wl${i}=wifi-iface\n\t\t\tset wireless.default_wl${i}.device=wl${i}\n\t\t\tset wireless.default_wl${i}.network=lan\n\t\t\tset wireless.default_wl${i}.mode=ap\n\t\t\tset wireless.default_wl${i}.ssid=OpenWrt${i#0}\n\t\t\tset wireless.default_wl${i}.encryption=none\nEOF\n\t\tuci -q commit wireless\n\tdone\n}\n"
  },
  {
    "path": "package/kernel/broadcom-wl/patches/003-compat-2.6.35.patch",
    "content": "--- a/driver/wl_linux.c\n+++ b/driver/wl_linux.c\n@@ -2082,7 +2082,11 @@ static void\n _wl_set_multicast_list(struct net_device *dev)\n {\n \twl_info_t *wl;\n+#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,34)\n \tstruct dev_mc_list *mclist;\n+#else\n+\tstruct netdev_hw_addr *ha;\n+#endif\n \tint i;\n \n \tif (!dev)\n@@ -2098,14 +2102,24 @@ _wl_set_multicast_list(struct net_device\n \t\twl->pub->allmulti = (dev->flags & IFF_ALLMULTI)? TRUE: FALSE;\n \n \t\t/* copy the list of multicasts into our private table */\n+#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,34)\n \t\tfor (i = 0, mclist = dev->mc_list; mclist && (i < dev->mc_count);\n \t\t\ti++, mclist = mclist->next) {\n+#else\n+\t\ti = 0;\n+\t\tnetdev_for_each_mc_addr(ha, dev) {\n+#endif\n \t\t\tif (i >= MAXMULTILIST) {\n \t\t\t\twl->pub->allmulti = TRUE;\n \t\t\t\ti = 0;\n \t\t\t\tbreak;\n \t\t\t}\n+#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,34)\n \t\t\twl->pub->multicast[i] = *((struct ether_addr*) mclist->dmi_addr);\n+#else\n+\t\t\twl->pub->multicast[i] = *((struct ether_addr*) ha->addr);\n+\t\t\ti++;\n+#endif\n \t\t}\n \t\twl->pub->nmulticast = i;\n \t\twlc_set(wl->wlc, WLC_SET_PROMISC, (dev->flags & IFF_PROMISC));\n"
  },
  {
    "path": "package/kernel/broadcom-wl/patches/004-remove-pcmcia.patch",
    "content": "--- a/driver/include/linuxver.h\n+++ b/driver/include/linuxver.h\n@@ -111,7 +111,7 @@ typedef irqreturn_t(*FN_ISR) (int irq, v\n #endif /* not SANDGATE2G */\n #endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(2, 5, 67) */\n \n-#if defined(CONFIG_PCMCIA) || defined(CONFIG_PCMCIA_MODULE)\n+#if 0\n \n #include <pcmcia/cs_types.h>\n #include <pcmcia/cs.h>\n--- a/driver/linux_osl.c\n+++ b/driver/linux_osl.c\n@@ -62,7 +62,7 @@ struct osl_info {\n };\n \n /* PCMCIA attribute space access macros */\n-#if defined(CONFIG_PCMCIA) || defined(CONFIG_PCMCIA_MODULE)\n+#if 0\n struct pcmcia_dev {\n \tdev_link_t link;\t/* PCMCIA device pointer */\n \tdev_node_t node;\t/* PCMCIA node structure */\n"
  },
  {
    "path": "package/kernel/broadcom-wl/patches/005-fix-mem-leak-on-unload.patch",
    "content": "From: George Kashperko <george@znau.edu.ua>\n\nRelease nvram variables buffer.\nPrevent block reserved by alloc_etherdev from being freed.\nSigned-off-by: George Kashperko <george@znau.edu.ua>\n---\n---\n--- a/driver/siutils.c\n+++ b/driver/siutils.c\n@@ -647,7 +647,10 @@ si_detach(si_t *sih)\n #if !defined(BCMBUSTYPE) || (BCMBUSTYPE == SI_BUS)\n \tif (sii != &ksii)\n #endif\t/* !BCMBUSTYPE || (BCMBUSTYPE == SI_BUS) */\n-\t\tMFREE(sii->osh, sii, sizeof(si_info_t));\n+\t\tdo {\n+\t\t\tMFREE(sii->osh, sii, sizeof(si_info_t));\n+\t\t\tnvram_exit((void *)&(sii->pub));\n+\t\t} while (0);\n }\n \n void *\n--- a/driver/wl_linux.c\n+++ b/driver/wl_linux.c\n@@ -1477,7 +1477,6 @@ wl_free_if(wl_info_t *wl, wl_if_t *wlif)\n \t\tfree_netdev(wlif->dev);\n #endif\n \t}\n-\tMFREE(wl->osh, wlif, sizeof(wl_if_t));\n }\n \n #ifdef AP\n"
  },
  {
    "path": "package/kernel/broadcom-wl/patches/006-generic-dma-api.patch",
    "content": "From: George Kashperko <george@znau.edu.ua>\n\nbroadcom-wl driver bound to ssb device with ssb driver probe\nhave osh handle struct pdev pointer value initialized with\nssb_device pointer. Later on pdev is used with legacy pci\ndma api as pci_dev thus causing oops sometimes.\n\nThe patch replaces legacy pci dma api and pass relevant\ndevice struct pointer to avoid crashes.\nSigned-off-by: George Kashperko <george@znau.edu.ua>\n---\n driver/linux_osl.c |   28 +++++++++++++++++++++++-----\n 1 file changed, 23 insertions(+), 5 deletions(-)\n--- a/driver/linux_osl.c\n+++ b/driver/linux_osl.c\n@@ -25,6 +25,9 @@\n #include <asm/paccess.h>\n #endif /* mips */\n #include <pcicfg.h>\n+#ifdef CONFIG_SSB\n+#include <linux/ssb/ssb.h>\n+#endif\n \n #define PCI_CFG_RETRY \t\t10\n \n@@ -364,12 +367,27 @@ osl_dma_consistent_align(void)\n \treturn (PAGE_SIZE);\n }\n \n+static struct device *\n+osl_get_dmadev(osl_t *osh)\n+{\n+#ifdef CONFIG_SSB\n+\tif (osh->bustype == SI_BUS) {\n+\t\t/* This can be SiliconBackplane emulated as pci with Broadcom or\n+\t\t * ssb device. Less harmful is to check for pci_bus_type and if\n+\t\t * no match then assume we got ssb */\n+\t\tif (((struct pci_dev *)osh->pdev)->dev.bus != &pci_bus_type)\n+\t\t\treturn ((struct ssb_device *)osh->pdev)->dma_dev;\n+\t}\n+#endif\n+\treturn &((struct pci_dev *)osh->pdev)->dev;\n+}\n+\n void*\n osl_dma_alloc_consistent(osl_t *osh, uint size, ulong *pap)\n {\n \tASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));\n \n-\treturn (pci_alloc_consistent(osh->pdev, size, (dma_addr_t*)pap));\n+\treturn (dma_alloc_coherent(osl_get_dmadev(osh), size, (dma_addr_t*)pap, GFP_ATOMIC));\n }\n \n void\n@@ -377,7 +395,7 @@ osl_dma_free_consistent(osl_t *osh, void\n {\n \tASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));\n \n-\tpci_free_consistent(osh->pdev, size, va, (dma_addr_t)pa);\n+\tdma_free_coherent(osl_get_dmadev(osh), size, va, (dma_addr_t)pa);\n }\n \n uint BCMFASTPATH\n@@ -386,13 +404,13 @@ osl_dma_map(osl_t *osh, void *va, uint s\n \tASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));\n \n \tif (direction == DMA_TX)\n-\t\treturn (pci_map_single(osh->pdev, va, size, PCI_DMA_TODEVICE));\n+\t\treturn (dma_map_single(osl_get_dmadev(osh), va, size, PCI_DMA_TODEVICE));\n \telse {\n #ifdef mips\n \t\tdma_cache_inv((uint)va, size);\n \t\treturn (virt_to_phys(va));\n #else /* mips */\n-\t\treturn (pci_map_single(osh->pdev, va, size, PCI_DMA_FROMDEVICE));\n+\t\treturn (dma_map_single(osl_get_dmadev(osh), va, size, PCI_DMA_FROMDEVICE));\n #endif /* mips */\n \t}\n }\n@@ -404,7 +422,7 @@ osl_dma_unmap(osl_t *osh, uint pa, uint\n \n \tASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));\n \tdir = (direction == DMA_TX)? PCI_DMA_TODEVICE: PCI_DMA_FROMDEVICE;\n-\tpci_unmap_single(osh->pdev, (uint32)pa, size, dir);\n+\tdma_unmap_single(osl_get_dmadev(osh), (uint32)pa, size, dir);\n }\n \n \n"
  },
  {
    "path": "package/kernel/broadcom-wl/patches/007-use-glue-driver.patch",
    "content": "--- a/driver/wl_linux.c\n+++ b/driver/wl_linux.c\n@@ -85,10 +85,9 @@ typedef void wlc_hw_info_t;\n #include <bcmjtag.h>\n #endif\t/* BCMJTAG */\n \n-\n-#ifdef CONFIG_SSB\n-#include <linux/ssb/ssb.h>\n-#endif\n+#if defined(CONFIG_SSB) || defined(CONFIG_BCMA)\n+#include <wl_glue.h>\n+#endif /* defined(CONFIG_SSB) || defined(CONFIG_BCMA) */\n \n /* Linux wireless extension support */\n #ifdef CONFIG_WIRELESS_EXT\n@@ -997,62 +996,32 @@ static struct pci_driver wl_pci_driver =\n #endif\t/* CONFIG_PCI */\n #endif  \n \n+#ifdef BCMJTAG\n+static bcmjtag_driver_t wl_jtag_driver = {\n+\t\twl_jtag_probe,\n+\t\twl_jtag_detach,\n+\t\twl_jtag_poll,\n+\t\t};\n+#endif\t/* BCMJTAG */\n \n-static int wl_ssb_probe(struct ssb_device *dev, const struct ssb_device_id *id)\n+#if defined(CONFIG_SSB) || defined(CONFIG_BCMA)\n+static void * glue_attach_cb(u16 vendor, u16 device,\n+                                ulong mmio, void *dev, u32 irq)\n {\n-\twl_info_t *wl;\n-\tvoid *mmio;\n-\n-\tif (dev->bus->bustype != SSB_BUSTYPE_SSB) {\n-\t\tprintk(\"Attaching to SSB behind PCI is not supported. Please remove the b43 ssb bridge\\n\");\n-\t\treturn -EINVAL;\n-\t}\n-\n-\tmmio = (void *) 0x18000000 + dev->core_index * 0x1000;\n-\twl = wl_attach(id->vendor, id->coreid, (ulong) mmio, SI_BUS, dev, dev->irq);\n-\tif (!wl) {\n-\t\tprintk(\"wl_attach failed\\n\");\n-\t\treturn -ENODEV;\n-\t}\n-\n-\tssb_set_drvdata(dev, wl);\n-\n-\treturn 0;\n+\treturn wl_attach(vendor, device, mmio, SI_BUS, dev, irq);\n }\n \n-static void wl_ssb_remove(struct ssb_device *dev)\n+static void glue_remove_cb(void *wldev)\n {\n-\twl_info_t *wl = (wl_info_t *) ssb_get_drvdata(dev);\n+\twl_info_t *wl = (wl_info_t *)wldev;\n \n \tWL_LOCK(wl);\n \tWL_APSTA_UPDN((\"wl%d (%s): wl_remove() -> wl_down()\\n\", wl->pub->unit, wl->dev->name));\n \twl_down(wl);\n \tWL_UNLOCK(wl);\n \twl_free(wl);\n-\tssb_set_drvdata(dev, NULL);\n }\n-\n-static const struct ssb_device_id wl_ssb_tbl[] = {\n-\tSSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, SSB_ANY_REV),\n-\tSSB_DEVTABLE_END\n-};\n-\n-#ifdef CONFIG_SSB\n-static struct ssb_driver wl_ssb_driver = {\n-\t.name\t= KBUILD_MODNAME,\n-\t.id_table = wl_ssb_tbl,\n-\t.probe = wl_ssb_probe,\n-\t.remove = wl_ssb_remove,\n-};\n-#endif\n-\n-#ifdef BCMJTAG\n-static bcmjtag_driver_t wl_jtag_driver = {\n-\t\twl_jtag_probe,\n-\t\twl_jtag_detach,\n-\t\twl_jtag_poll,\n-\t\t};\n-#endif\t/* BCMJTAG */\n+#endif/* defined(CONFIG_SSB) || defined(CONFIG_BCMA) */\n \n \n /** \n@@ -1067,11 +1036,13 @@ wl_module_init(void)\n {\n \tint error = -ENODEV;\n \n-#ifdef CONFIG_SSB\n-\terror = ssb_driver_register(&wl_ssb_driver);\n+#if defined(CONFIG_SSB) || defined(CONFIG_BCMA)\n+\twl_glue_set_attach_callback(&glue_attach_cb);\n+\twl_glue_set_remove_callback(&glue_remove_cb);\n+\terror = wl_glue_register();\n \tif (error)\n \t\treturn error;\n-#endif\t/* CONFIG_SSB */\n+#endif /* defined(CONFIG_SSB) || defined(CONFIG_BCMA) */\n \n #ifdef CONFIG_PCI\n \terror = pci_register_driver(&wl_pci_driver);\n@@ -1082,7 +1053,11 @@ wl_module_init(void)\n \treturn 0;\n \n error_pci:\n-\tssb_driver_unregister(&wl_ssb_driver);\n+#if defined(CONFIG_SSB) || defined(CONFIG_BCMA)\n+\twl_glue_unregister();\n+\twl_glue_set_attach_callback(NULL);\n+\twl_glue_set_remove_callback(NULL);\n+#endif /* defined(CONFIG_SSB) || defined(CONFIG_BCMA) */\n \treturn error;\n }\n \n@@ -1099,9 +1074,11 @@ wl_module_exit(void)\n #ifdef CONFIG_PCI\n \tpci_unregister_driver(&wl_pci_driver);\n #endif\t/* CONFIG_PCI */\n-#ifdef CONFIG_SSB\n-\tssb_driver_unregister(&wl_ssb_driver);\n-#endif\t/* CONFIG_SSB */\n+#if defined(CONFIG_SSB) || defined(CONFIG_BCMA)\n+\twl_glue_unregister();\n+\twl_glue_set_attach_callback(NULL);\n+\twl_glue_set_remove_callback(NULL);\n+#endif /* defined(CONFIG_SSB) || defined(CONFIG_BCMA) */\n }\n \n module_init(wl_module_init);\n--- a/driver/linux_osl.c\n+++ b/driver/linux_osl.c\n@@ -25,9 +25,9 @@\n #include <asm/paccess.h>\n #endif /* mips */\n #include <pcicfg.h>\n-#ifdef CONFIG_SSB\n-#include <linux/ssb/ssb.h>\n-#endif\n+#if defined(CONFIG_SSB) || defined(CONFIG_BCMA)\n+#include <wl_glue.h>\n+#endif /* defined(CONFIG_SSB) || defined(CONFIG_BCMA) */\n \n #define PCI_CFG_RETRY \t\t10\n \n@@ -370,15 +370,17 @@ osl_dma_consistent_align(void)\n static struct device *\n osl_get_dmadev(osl_t *osh)\n {\n-#ifdef CONFIG_SSB\n+#if defined(CONFIG_SSB) || defined(CONFIG_BCMA)\n \tif (osh->bustype == SI_BUS) {\n-\t\t/* This can be SiliconBackplane emulated as pci with Broadcom or\n-\t\t * ssb device. Less harmful is to check for pci_bus_type and if\n-\t\t * no match then assume we got ssb */\n+\t\t/* This can be SiliconBackplane emulated as pci with Broadcom,\n+\t\t * ssb or bcma device. Less harmful is to check for pci_bus_type and if\n+\t\t * no match then assume we got either ssb or bcma */\n \t\tif (((struct pci_dev *)osh->pdev)->dev.bus != &pci_bus_type)\n-\t\t\treturn ((struct ssb_device *)osh->pdev)->dma_dev;\n+\t\t{\n+\t\t\treturn wl_glue_get_dmadev(osh->pdev);\n+\t\t}\n \t}\n-#endif\n+#endif /* defined(CONFIG_SSB) || defined(CONFIG_BCMA) */\n \treturn &((struct pci_dev *)osh->pdev)->dev;\n }\n \n--- a/driver/Makefile\n+++ b/driver/Makefile\n@@ -1,7 +1,7 @@\n BUILD_TYPE=wl_apsta\n include $(src)/$(BUILD_TYPE)/buildflags.mk\n \n-EXTRA_CFLAGS += -I$(src)/include -I$(src) -DBCMDRIVER $(WLFLAGS)\n+EXTRA_CFLAGS += -I$(src)/include -I$(src) -I$(realpath $(src)/../glue) -DBCMDRIVER $(WLFLAGS)\n \n wl-objs := $(BUILD_TYPE)/wl_prebuilt.o wl_iw.o wl_linux.o linux_osl.o siutils.o aiutils.o hndpmu.o bcmutils.o sbutils.o nicpci.o hnddma.o bcmsrom.o nvram_stub.o\n \n"
  },
  {
    "path": "package/kernel/broadcom-wl/patches/008-fix_virtual_interfaces.patch",
    "content": "--- a/driver/wl_linux.c\n+++ b/driver/wl_linux.c\n@@ -354,6 +354,7 @@ static int wl_read_proc(char *buffer, ch\n static int wl_dump(wl_info_t *wl, struct bcmstrbuf *b);\n #endif /* BCMDBG */\n struct wl_if *wl_alloc_if(wl_info_t *wl, int iftype, uint unit, struct wlc_if* wlc_if);\n+static void wl_link_if(wl_info_t *wl, wl_if_t *wlif);\n static void wl_free_if(wl_info_t *wl, wl_if_t *wlif);\n \n \n@@ -566,6 +567,9 @@ wl_attach(uint16 vendor, uint16 device,\n \twl->dev = dev;\n \twl_if_setup(dev);\n \n+\t/* add the interface to the interface linked list */\n+\twl_link_if(wl, wlif);\n+\n \t/* map chip registers (47xx: and sprom) */\n \tdev->base_addr = regs;\n \n@@ -1106,10 +1110,14 @@ wl_free(wl_info_t *wl)\n \t\t\tfree_irq(wl->dev->irq, wl);\n \t}\n \n-\tif (wl->dev) {\n-\t\twl_free_if(wl, WL_DEV_IF(wl->dev));\n-\t\twl->dev = NULL;\n+\t/* free all interfaces */\n+\twhile (wl->if_list) {\n+        \tif ((wl->if_list->dev != wl->dev) || wl->if_list->next == NULL)\n+\t\t\twl_free_if(wl, wl->if_list);\n+\t\telse\n+\t\t\twl_free_if(wl, wl->if_list->next);\n \t}\n+\twl->dev = NULL;\n \n #ifdef TOE\n \twl_toe_detach(wl->toei);\n@@ -1355,10 +1363,12 @@ wl_txflowcontrol(wl_info_t *wl, bool sta\n \n \tASSERT(prio == ALLPRIO);\n \tfor (wlif = wl->if_list; wlif != NULL; wlif = wlif->next) {\n-\t\tif (state == ON)\n-\t\t\tnetif_stop_queue(wlif->dev);\n-\t\telse\n-\t\t\tnetif_wake_queue(wlif->dev);\n+\t\tif (wlif->dev_registed) {\n+\t\t\tif (state == ON)\n+\t\t\t\tnetif_stop_queue(wlif->dev);\n+\t\t\telse\n+\t\t\t\tnetif_wake_queue(wlif->dev);\n+\t\t}\n \t}\n }\n \n@@ -1398,7 +1408,6 @@ wl_alloc_if(wl_info_t *wl, int iftype, u\n {\n \tstruct net_device *dev;\n \twl_if_t *wlif;\n-\twl_if_t *p;\n \n \tdev = alloc_etherdev(sizeof(wl_if_t));\n \twlif = netdev_priv(dev);\n@@ -1411,9 +1420,13 @@ wl_alloc_if(wl_info_t *wl, int iftype, u\n \twlif->wlcif = wlcif;\n \twlif->subunit = subunit;\n \n-\t/* match current flow control state */\n-\tif (iftype != WL_IFTYPE_MON && wl->dev && netif_queue_stopped(wl->dev))\n-\t\tnetif_stop_queue(dev);\n+\treturn wlif;\n+}\n+\n+static void\n+wl_link_if(wl_info_t *wl, wl_if_t *wlif)\n+{\n+\twl_if_t *p;\n \n \t/* add the interface to the interface linked list */\n \tif (wl->if_list == NULL)\n@@ -1424,7 +1437,6 @@ wl_alloc_if(wl_info_t *wl, int iftype, u\n \t\t\tp = p->next;\n \t\tp->next = wlif;\n \t}\n-\treturn wlif;\n }\n \n static void\n@@ -1504,6 +1516,9 @@ _wl_add_if(wl_task_t *task)\n \twl_info_t *wl = wlif->wl;\n \tstruct net_device *dev = wlif->dev;\n \n+\t/* add the interface to the interface linked list */\n+\twl_link_if(wl, wlif);\n+\n \tif (wlif->type == WL_IFTYPE_WDS)\n \t\tdev->netdev_ops = &wl_wds_ops;\n \n@@ -1516,6 +1531,14 @@ _wl_add_if(wl_task_t *task)\n \t}\n \twlif->dev_registed = TRUE;\n \n+\t/* match current flow control state */\n+\tif (wl->dev) {\n+\t\tif (netif_queue_stopped(wl->dev))\n+\t\t\tnetif_stop_queue(dev);\n+\t\telse\n+\t\t\tnetif_wake_queue(dev);\n+\t}\n+\n done:\n \tMFREE(wl->osh, task, sizeof(wl_task_t));\n \tatomic_dec(&wl->callbacks);\n@@ -1545,6 +1568,8 @@ wl_add_if(wl_info_t *wl, struct wlc_if*\n \t\treturn NULL;\n \t}\n \n+\twl_if_setup(wlif->dev);\n+\n \tsprintf(wlif->dev->name, \"%s%d.%d\", devname, wl->pub->unit, wlif->subunit);\n \tif (remote)\n \t\tbcopy(remote, &wlif->remote, ETHER_ADDR_LEN);\n@@ -2778,6 +2803,9 @@ wl_add_monitor(wl_task_t *task)\n \tdev = wlif->dev;\n \twl->monitor = dev;\n \n+\t/* add the interface to the interface linked list */\n+\twl_link_if(wl, wlif);\n+\n \t/* override some fields */\n \tsprintf(dev->name, \"prism%d\", wl->pub->unit);\n \tbcopy(wl->dev->dev_addr, dev->dev_addr, ETHER_ADDR_LEN);\n"
  },
  {
    "path": "package/kernel/broadcom-wl/patches/009-fix_compile_3_2.patch",
    "content": "--- a/driver/wl_linux.c\n+++ b/driver/wl_linux.c\n@@ -463,6 +463,16 @@ wl_schedule_fn(wl_info_t *wl, void (*fn)\n }\n #endif /* DSLCPE_DELAY */\n \n+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 2, 0)\n+#define WL_DEFAULT_OPS \\\n+\t.ndo_open = wl_open, \\\n+\t.ndo_stop = wl_close, \\\n+\t.ndo_start_xmit = wl_start, \\\n+\t.ndo_get_stats = wl_get_stats, \\\n+\t.ndo_set_mac_address = wl_set_mac_address, \\\n+\t.ndo_set_rx_mode = wl_set_multicast_list, \\\n+\t.ndo_do_ioctl = wl_ioctl\n+#else\n #define WL_DEFAULT_OPS \\\n \t.ndo_open = wl_open, \\\n \t.ndo_stop = wl_close, \\\n@@ -471,6 +481,7 @@ wl_schedule_fn(wl_info_t *wl, void (*fn)\n \t.ndo_set_mac_address = wl_set_mac_address, \\\n \t.ndo_set_multicast_list = wl_set_multicast_list, \\\n \t.ndo_do_ioctl = wl_ioctl\n+#endif\n \n static const struct net_device_ops wl_ops = {\n \tWL_DEFAULT_OPS,\n"
  },
  {
    "path": "package/kernel/broadcom-wl/patches/010-remove_irqf_samble_random.patch",
    "content": "--- a/driver/wl_linux.c\n+++ b/driver/wl_linux.c\n@@ -695,7 +695,7 @@ wl_attach(uint16 vendor, uint16 device,\n \tif (wl->bustype != JTAG_BUS)\n #endif\t/* BCMJTAG */\n \t{\n-\t\tif (request_irq(irq, wl_isr, IRQF_SHARED|IRQF_SAMPLE_RANDOM, dev->name, wl)) {\n+\t\tif (request_irq(irq, wl_isr, IRQF_SHARED, dev->name, wl)) {\n \t\t\tWL_ERROR((\"wl%d: request_irq() failed\\n\", unit));\n \t\t\tgoto fail;\n \t\t}\n"
  },
  {
    "path": "package/kernel/broadcom-wl/patches/011-fix_compile_3_4.patch",
    "content": "--- a/driver/wl_linux.c\n+++ b/driver/wl_linux.c\n@@ -49,7 +49,9 @@\n #include <linux/ieee80211.h>\n #endif\n \n+#if LINUX_VERSION_CODE < KERNEL_VERSION(3,4,0)\n #include <asm/system.h>\n+#endif\n #include <asm/io.h>\n #include <asm/irq.h>\n #include <asm/pgtable.h>\n"
  },
  {
    "path": "package/kernel/broadcom-wl/patches/012-compat-3.10.patch",
    "content": "--- a/driver/wl_linux.c\n+++ b/driver/wl_linux.c\n@@ -349,7 +349,7 @@ static void wl_mic_error(wl_info_t *wl,\n \tdefined(WL_MONITOR)\n static int wl_schedule_task(wl_info_t *wl, void (*fn)(struct wl_task *), void *context);\n #endif\n-#if defined(CONFIG_PROC_FS)\n+#if defined(CONFIG_PROC_FS) && (LINUX_VERSION_CODE < KERNEL_VERSION(3,10,0))\n static int wl_read_proc(char *buffer, char **start, off_t offset, int length, int *eof, void *data);\n #endif /* defined(CONFIG_PROC_FS) */\n #ifdef BCMDBG\n@@ -517,7 +517,7 @@ wl_attach(uint16 vendor, uint16 device,\n \tstruct net_device *dev;\n \twl_if_t *wlif;\n \twl_info_t *wl;\n-#if defined(CONFIG_PROC_FS)\n+#if defined(CONFIG_PROC_FS) && (LINUX_VERSION_CODE < KERNEL_VERSION(3,10,0))\n \tchar tmp[128];\n #endif\n \tosl_t *osh;\n@@ -664,7 +664,7 @@ wl_attach(uint16 vendor, uint16 device,\n \t\t\tWL_ERROR((\"wl%d: Error setting MPC variable to 0\\n\", unit));\n \t\t}\n \t}\n-#if defined(CONFIG_PROC_FS)\n+#if defined(CONFIG_PROC_FS) && (LINUX_VERSION_CODE < KERNEL_VERSION(3,10,0))\n \t/* create /proc/net/wl<unit> */\n \tsprintf(tmp, \"net/wl%d\", wl->pub->unit);\n \tcreate_proc_read_entry(tmp, 0, 0, wl_read_proc, (void*)wl);\n@@ -810,7 +810,7 @@ wl_dbus_disconnect_cb(void *arg)\n }\n #endif /* BCMDBUS */\n \n-#if defined(CONFIG_PROC_FS)\n+#if defined(CONFIG_PROC_FS) && (LINUX_VERSION_CODE < KERNEL_VERSION(3,10,0))\n static int\n wl_read_proc(char *buffer, char **start, off_t offset, int length, int *eof, void *data)\n {\n@@ -1149,7 +1149,7 @@ wl_free(wl_info_t *wl)\n \n \t/* free common resources */\n \tif (wl->wlc) {\n-#if defined(CONFIG_PROC_FS)\n+#if defined(CONFIG_PROC_FS) && (LINUX_VERSION_CODE < KERNEL_VERSION(3,10,0))\n \t\tchar tmp[128];\n \t\t/* remove /proc/net/wl<unit> */\n \t\tsprintf(tmp, \"net/wl%d\", wl->pub->unit);\n"
  },
  {
    "path": "package/kernel/broadcom-wl/patches/013-interface-name.patch",
    "content": "--- a/driver/wl_linux.c\n+++ b/driver/wl_linux.c\n@@ -1583,7 +1583,7 @@ wl_add_if(wl_info_t *wl, struct wlc_if*\n \n \twl_if_setup(wlif->dev);\n \n-\tsprintf(wlif->dev->name, \"%s%d.%d\", devname, wl->pub->unit, wlif->subunit);\n+\tsprintf(wlif->dev->name, \"%s%d-%d\", devname, wl->pub->unit, wlif->subunit);\n \tif (remote)\n \t\tbcopy(remote, &wlif->remote, ETHER_ADDR_LEN);\n \n"
  },
  {
    "path": "package/kernel/broadcom-wl/patches/014-fix-band-reporting.patch",
    "content": "--- a/driver/wl_iw.c\n+++ b/driver/wl_iw.c\n@@ -314,7 +314,7 @@ wl_iw_get_name(\n )\n {\n \tint phytype, err;\n-\tuint band[3];\n+\tuint i, band[3], bands;\n \tchar cap[5];\n \n \tWL_TRACE((\"%s: SIOCGIWNAME\\n\", dev->name));\n@@ -335,16 +335,20 @@ wl_iw_get_name(\n \t\t\tbreak;\n \t\tcase WLC_PHY_TYPE_LP:\n \t\tcase WLC_PHY_TYPE_G:\n-\t\t\tif (band[0] >= 2)\n-\t\t\t\tstrcpy(cap, \"abg\");\n-\t\t\telse\n-\t\t\t\tstrcpy(cap, \"bg\");\n-\t\t\tbreak;\n \t\tcase WLC_PHY_TYPE_N:\n-\t\t\tif (band[0] >= 2)\n-\t\t\t\tstrcpy(cap, \"abgn\");\n-\t\t\telse\n-\t\t\t\tstrcpy(cap, \"bgn\");\n+\t\t\tbands = 0;\n+\t\t\tfor (i = 1; i <= band[0]; i++) {\n+\t\t\t\tbands |= dtoh32(band[i]);\n+\t\t\t}\n+\t\t\tstrcpy(cap, \"\");\n+\t\t\tif (bands & WLC_BAND_5G)\n+\t\t\t\tstrcat(cap, \"a\");\n+\t\t\tif (bands & WLC_BAND_2G)\n+\t\t\t\tstrcat(cap, \"bg\");\n+\t\t\tif (phytype == WLC_PHY_TYPE_N)\n+\t\t\t\tstrcat(cap, \"n\");\n+\t\t\tbreak;\n+\t\tdefault:\n \t\t\tbreak;\n \t}\n done:\n"
  },
  {
    "path": "package/kernel/broadcom-wl/patches/015-support-probe-of-wds-interfaces.patch",
    "content": "--- a/shared/wl.c\n+++ b/shared/wl.c\n@@ -27,7 +27,7 @@ wl_probe(char *name)\n {\n \tint ret, val;\n \n-\tif ((name[0] != 'w') || (name[1] != 'l'))\n+\tif ((name[0] != 'w') || ((name[1] != 'l') && ((name[1] != 'd') || (name[2] != 's'))))\n \t\treturn -1;\n \n \t/* Check interface */\n"
  },
  {
    "path": "package/kernel/broadcom-wl/patches/020-musl-fixes.patch",
    "content": "--- a/shared/wl_linux.c\n+++ b/shared/wl_linux.c\n@@ -13,6 +13,7 @@\n  */\n \n #include <stdio.h>\n+#include <stdint.h>\n #include <unistd.h>\n #include <string.h>\n #include <errno.h>\n@@ -20,10 +21,10 @@\n #include <net/if.h>\n #include <linux/types.h>\n \n-typedef u_int64_t u64;\n-typedef u_int32_t u32;\n-typedef u_int16_t u16;\n-typedef u_int8_t u8;\n+typedef uint64_t u64;\n+typedef uint32_t u32;\n+typedef uint16_t u16;\n+typedef uint8_t u8;\n #include <linux/sockios.h>\n #include <linux/ethtool.h>\n \n--- a/shared/linux_timer.c\n+++ b/shared/linux_timer.c\n@@ -125,7 +125,7 @@ void unblock_timer();\n \n static struct event *event_queue = NULL;\n static struct event *event_freelist;\n-static uint g_granularity;\n+static unsigned int g_granularity;\n static int g_maxevents = 0;\n \n uclock_t uclock()\n--- a/shared/wl.c\n+++ b/shared/wl.c\n@@ -14,6 +14,7 @@\n #include <typedefs.h>\n #include <string.h>\n #include <stdio.h>\n+#include <stdlib.h>\n #include <unistd.h>\n #include <errno.h>\n #include <sys/ioctl.h>\n@@ -263,3 +264,28 @@ wl_printlasterror(char *name)\n \t\tfprintf(stderr, err_buf);\n }\n */\n+\n+static int in_assert;\t\t\t/* bss inits to 0. */\n+\n+void __assert(const char *assertion, const char * filename,\n+\t      unsigned int linenumber, register const char * function)\n+{\n+\tif (!in_assert) {\n+\t\tin_assert = 1;\n+\n+\t\tfprintf(stderr,\n+#ifdef ASSERT_SHOW_PROGNAME\n+\t\t\t\t\"%s: %s: %d: %s: Assertion `%s' failed.\\n\", __uclibc_progname,\n+#else\n+\t\t\t\t\"%s: %d: %s: Assertion `%s' failed.\\n\",\n+#endif\n+\t\t\t\tfilename,\n+\t\t\t\tlinenumber,\n+\t\t\t\t/* Function name isn't available with some compilers. */\n+\t\t\t\t((function == NULL) ? \"?function?\" : function),\n+\t\t\t\tassertion\n+\t\t\t\t);\n+\t}\n+\t/* shouldn't we? fflush(stderr); */\n+\tabort();\n+}\n"
  },
  {
    "path": "package/kernel/broadcom-wl/patches/030-remove_devinit_devexit.patch",
    "content": "--- a/driver/include/linuxver.h\n+++ b/driver/include/linuxver.h\n@@ -139,22 +139,6 @@ typedef\tstruct pcmcia_device dev_link_t;\n \n #endif /* CONFIG_PCMCIA */\n \n-#ifndef __exit\n-#define __exit\n-#endif\n-#ifndef __devexit\n-#define __devexit\n-#endif\n-#ifndef __devinit\n-#define __devinit\t__init\n-#endif\n-#ifndef __devinitdata\n-#define __devinitdata\n-#endif\n-#ifndef __devexit_p\n-#define __devexit_p(x)\tx\n-#endif\n-\n #if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 0))\n \n #define pci_get_drvdata(dev)\t\t(dev)->sysdata\n--- a/driver/wl_linux.c\n+++ b/driver/wl_linux.c\n@@ -854,7 +854,7 @@ wl_read_proc(char *buffer, char **start,\n  */\n #if !defined(BCMJTAG)\n #ifdef CONFIG_PCI\n-static void __devexit wl_remove(struct pci_dev *pdev);\n+static void wl_remove(struct pci_dev *pdev);\n /** \n  * determines if a device is a WL device, and if so, attaches it.\n  *\n@@ -862,7 +862,7 @@ static void __devexit wl_remove(struct p\n  * and if so, performs a wl_attach() on it.\n  *\n  */\n-int __devinit\n+int\n wl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)\n {\n \tint rc;\n@@ -976,7 +976,7 @@ wl_resume(struct pci_dev *pdev)\n }\n #endif /* LINUXSTA_PS */\n \n-static void __devexit\n+static void\n wl_remove(struct pci_dev *pdev)\n {\n \twl_info_t *wl = (wl_info_t *) pci_get_drvdata(pdev);\n@@ -1007,7 +1007,7 @@ static struct pci_driver wl_pci_driver =\n \tsuspend:\twl_suspend,\n \tresume:\t\twl_resume,\n #endif /* LINUXSTA_PS */\n-\tremove:\t\t__devexit_p(wl_remove),\n+\tremove:\t\twl_remove,\n \tid_table:\twl_id_table,\n \t};\n #endif\t/* CONFIG_PCI */\n--- a/driver/wl_linux.h\n+++ b/driver/wl_linux.h\n@@ -33,7 +33,7 @@ extern irqreturn_t wl_isr(int irq, void\n extern irqreturn_t wl_isr(int irq, void *dev_id, struct pt_regs *ptregs);\n #endif\n \n-extern int __devinit wl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent);\n+extern int wl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent);\n extern void wl_free(wl_info_t *wl);\n extern int  wl_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd);\n extern struct net_device * wl_netdev_get(wl_info_t *wl);\n"
  },
  {
    "path": "package/kernel/broadcom-wl/patches/040-remove_last_rx_usage.patch",
    "content": "--- broadcom-wl-5.10.56.27.3/driver/wl_linux.c.orig\t2018-01-13 18:25:14.944667645 +0100\n+++ broadcom-wl-5.10.56.27.3/driver/wl_linux.c\t2018-01-13 18:25:25.836667888 +0100\n@@ -2762,7 +2762,6 @@\n \tbcopy(oskb->data + D11_PHY_HDR_LEN, pdata, oskb->len - D11_PHY_HDR_LEN);\n \n \tskb->dev = wl->monitor;\n-\tskb->dev->last_rx = jiffies;\n #if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 22)\n \tskb_reset_mac_header(skb);\n #else\n"
  },
  {
    "path": "package/kernel/broadcom-wl/patches/100-fix_nvram_two_devices.patch",
    "content": "--- a/driver/nvram_stub.c\n+++ b/driver/nvram_stub.c\n@@ -22,6 +22,7 @@ typedef struct _vars {\n #define\tVARS_T_OH\tsizeof(vars_t)\n \n static vars_t *vars = NULL;\n+static int nvram_init_done = 0;\n extern char *nvram_buf[];\n \n int\n@@ -33,6 +34,10 @@ BCMATTACHFN(nvram_init)(void *si)\n \tuint nvs, bufsz;\n \tvars_t *new;\n \n+\tnvram_init_done++;\n+\tif (nvram_init_done != 1)\n+\t\treturn 0;\n+\n \tosh = si_osh(sih);\n \n \tnvs = R_REG(osh, &nvh->len) - sizeof(struct nvram_header);\n@@ -79,6 +84,10 @@ BCMATTACHFN(nvram_exit)(void *si)\n \tvars_t *this, *next;\n \tsi_t *sih;\n \n+\tnvram_init_done--;\n+\tif (nvram_init_done != 0)\n+\t\treturn;\n+\n \tsih = (si_t *)si;\n \tthis = vars;\n \twhile (this) {\n"
  },
  {
    "path": "package/kernel/broadcom-wl/patches/110-add_number_to_dev_name.patch",
    "content": "--- a/driver/wl_linux.c\n+++ b/driver/wl_linux.c\n@@ -1425,7 +1425,7 @@ wl_alloc_if(wl_info_t *wl, int iftype, u\n \tdev = alloc_etherdev(sizeof(wl_if_t));\n \twlif = netdev_priv(dev);\n \tbzero(wlif, sizeof(wl_if_t));\n-\tstrncpy(dev->name, name, IFNAMSIZ);\n+\tsnprintf(dev->name, IFNAMSIZ, name, subunit);\n \n \twlif->type = iftype;\n \twlif->dev = dev;\n"
  },
  {
    "path": "package/kernel/broadcom-wl/patches/120-fixup-mac-addresses.patch",
    "content": "--- a/driver/nvram_stub.c\n+++ b/driver/nvram_stub.c\n@@ -5,6 +5,8 @@\n #include <siutils.h>\n #include <bcmendian.h>\n #include <bcmnvram.h>\n+#include <proto/ethernet.h>\n+#include <linux/errno.h>\n \n #ifdef BCMDBG_ERR\n #define NVR_MSG(x) printf x\n@@ -24,6 +26,7 @@ typedef struct _vars {\n static vars_t *vars = NULL;\n static int nvram_init_done = 0;\n extern char *nvram_buf[];\n+static void fixup_mac_addr(vars_t *new);\n \n int\n BCMATTACHFN(nvram_init)(void *si)\n@@ -55,6 +58,7 @@ BCMATTACHFN(nvram_init)(void *si)\n \tvars = new;\n \n \tbcopy((char *)(&nvh[1]), new->vars, nvs);\n+\tfixup_mac_addr(new);\n \treturn 0;\n }\n \n@@ -164,3 +168,65 @@ nvram_getall(char *buf, int count)\n \t*buf = '\\0';\n \treturn 0;\n }\n+\n+static bool nvram_is_valid_mac(struct ether_addr *mac)\n+{\n+\treturn mac && !(mac->octet[0] == 0x00 && mac->octet[1] == 0x90 && mac->octet[2] == 0x4c);\n+}\n+\n+static int nvram_increase_mac_addr(struct ether_addr *mac, u8 num)\n+{\n+\tu8 *oui = mac->octet + ETHER_ADDR_LEN/2 - 1;\n+\tu8 *p = mac->octet + ETHER_ADDR_LEN - 1;\n+\n+\tdo {\n+\t\t(*p) += num;\n+\t\tif (*p > num)\n+\t\t\tbreak;\n+\t\tp--;\n+\t\tnum = 1;\n+\t} while (p != oui);\n+\n+\tif (p == oui) {\n+\t\tpr_err(\"unable to fetch mac address\\n\");\n+\t\treturn -ENOENT;\n+\t}\n+\treturn 0;\n+}\n+\n+static void nvram_change_mac_addr(vars_t *new, struct ether_addr *valid, const char *name)\n+{\n+\tchar *macaddr_c;\n+\tstruct ether_addr macaddr;\n+\n+\tmacaddr_c = findvar(new->vars, new->vars + new->size, name);\n+\tif (!macaddr_c)\n+\t\treturn;\n+\n+\tbcm_ether_atoe(macaddr_c, &macaddr);\n+\tif (nvram_is_valid_mac(&macaddr))\n+\t\treturn;\n+\tnvram_increase_mac_addr(valid, 1);\n+\tbcm_ether_ntoa(valid, macaddr_c);\n+}\n+\n+static void fixup_mac_addr(vars_t *new)\n+{\n+\tchar *macaddr_base_c;\n+\tstruct ether_addr macaddr_base;\n+\n+\tmacaddr_base_c = findvar(new->vars, new->vars + new->size, \"et0macaddr\");\n+\tif (!macaddr_base_c)\n+\t\treturn;\n+\n+\tbcm_ether_atoe(macaddr_base_c, &macaddr_base);\n+\tif (!nvram_is_valid_mac(&macaddr_base))\n+\t\treturn;\n+\n+\t/* jump over the first free address so it can be used for wan */\n+\tnvram_increase_mac_addr(&macaddr_base, 1);\n+\tnvram_change_mac_addr(new, &macaddr_base, \"sb/1/macaddr\");\n+\tnvram_change_mac_addr(new, &macaddr_base, \"pci/1/1/macaddr\");\n+\tnvram_change_mac_addr(new, &macaddr_base, \"pci/1/2/macaddr\");\n+\tnvram_change_mac_addr(new, &macaddr_base, \"pci/2/1/macaddr\");\n+}\n"
  },
  {
    "path": "package/kernel/broadcom-wl/patches/200-add_bcm_a8xx_support.patch",
    "content": "--- a/driver/wl_linux.c\n+++ b/driver/wl_linux.c\n@@ -876,7 +876,8 @@ wl_pci_probe(struct pci_dev *pdev, const\n \n \tif ((pdev->vendor != PCI_VENDOR_ID_BROADCOM) ||\n \t    (((pdev->device & 0xff00) != 0x4300) &&\n-\t     ((pdev->device & 0xff00) != 0x4700)))\n+\t     ((pdev->device & 0xff00) != 0x4700) &&\n+\t     ((pdev->device & 0xff00) != 0xa800)))\n \t\treturn (-ENODEV);\n \n \trc = pci_enable_device(pdev);\n"
  },
  {
    "path": "package/kernel/broadcom-wl/patches/910-fallback-sprom.patch",
    "content": "--- a/driver/bcmsrom.c\n+++ b/driver/bcmsrom.c\n@@ -39,6 +39,11 @@\n #include <sbsdpcmdev.h>\n #endif \n \n+#if defined(CONFIG_SSB_PCIHOST) && defined(CONFIG_BOARD_BCM963XX)\n+#include <linux/ssb/ssb.h>\n+extern int bcm63xx_get_fallback_sprom(uint pci_bus, uint pci_slot, struct ssb_sprom *out);\n+#endif\n+\n #ifdef WLTEST\n #include <sbsprom.h>\n #endif /* WLTEST */\n@@ -2120,6 +2125,63 @@ BCMATTACHFN(initvars_srom_pci)(si_t *sih\n \t\t\tgoto varscont;\n \t\t}\n \n+#if defined(CONFIG_SSB_PCIHOST) && defined(CONFIG_BOARD_BCM963XX)\n+\t\tbase = vp = MALLOC(osh, MAXSZ_NVRAM_VARS);\n+\n+\t\tif( base != NULL )\n+\t\t{\n+\t\t\tchar eabuf[18];\n+\t\t\tstruct ssb_sprom bcm63xx_sprom;\n+\t\t\tuint pci_bus = osl_pci_bus(osh), pci_slot = osl_pci_slot(osh);\n+\n+\t\t\tbcm63xx_get_fallback_sprom(pci_bus, pci_slot, &bcm63xx_sprom);\n+\t\t\tprintk(\"BCM%X(%02x:%02x) using sprom version %i\\n\", sih->chip, pci_bus, pci_slot, bcm63xx_sprom.revision);\n+\n+\t\t\tvarbuf_init(&b, base, MAXSZ_NVRAM_VARS);\n+\n+\t\t\tvarbuf_append(&b, vstr_sromrev, bcm63xx_sprom.revision);\n+\t\t\tvarbuf_append(&b, vstr_boardrev, bcm63xx_sprom.board_rev);\n+\n+\t\t\t/* ToDo: map bcm63xx_sprom.country_code */\n+\t\t\tvarbuf_append(&b, vstr_noccode);\n+\n+\t\t\tvarbuf_append(&b, vstr_aa2g, bcm63xx_sprom.ant_available_bg);\n+\n+\t\t\tvarbuf_append(&b, vstr_pa0b[0], bcm63xx_sprom.pa0b0);\n+\t\t\tvarbuf_append(&b, vstr_pa1b[0], bcm63xx_sprom.pa1b0);\n+\t\t\tvarbuf_append(&b, vstr_pa0b[1], bcm63xx_sprom.pa0b1);\n+\t\t\tvarbuf_append(&b, vstr_pa1b[1], bcm63xx_sprom.pa1b1);\n+\t\t\tvarbuf_append(&b, vstr_pa0b[2], bcm63xx_sprom.pa0b2);\n+\t\t\tvarbuf_append(&b, vstr_pa1b[2], bcm63xx_sprom.pa1b2);\n+\n+\t\t\tvarbuf_append(&b, vstr_pa0maxpwr, bcm63xx_sprom.maxpwr_bg);\n+\t\t\tvarbuf_append(&b, vstr_pa0itssit, bcm63xx_sprom.itssi_bg);\n+\n+\t\t\tvarbuf_append(&b, vstr_boardflags, (bcm63xx_sprom.boardflags_hi << 16) | bcm63xx_sprom.boardflags_lo);\n+\t\t\tvarbuf_append(&b, vstr_boardflags2, (bcm63xx_sprom.boardflags2_hi << 16) | bcm63xx_sprom.boardflags2_lo);\n+\n+\t\t\tsnprintf(eabuf, sizeof(eabuf), \"%02x:%02x:%02x:%02x:%02x:%02x\",\n+\t\t\t\tbcm63xx_sprom.il0mac[0], bcm63xx_sprom.il0mac[1], bcm63xx_sprom.il0mac[2],\n+\t\t\t\tbcm63xx_sprom.il0mac[3], bcm63xx_sprom.il0mac[4], bcm63xx_sprom.il0mac[5]\n+\t\t\t);\n+\n+\t\t\tvarbuf_append(&b, vstr_macaddr, eabuf);\n+\n+\t\t\t/* final nullbyte terminator */\n+\t\t\tASSERT(b.size >= 1);\n+\t\t\tvp = b.buf;\n+\t\t\t*vp++ = '\\0';\n+\n+\t\t\tASSERT((vp - base) <= MAXSZ_NVRAM_VARS);\n+\t\t\tgoto varsdone;\n+\t\t}\n+\t\telse\n+\t\t{\n+\t\t\terr = -2;\n+\t\t\tgoto errout;\n+\t\t}\n+#endif\n+\n \t\tBS_ERROR((\"SROM CRC Error\\n\"));\n \n #if defined(WLTEST)\n"
  },
  {
    "path": "package/kernel/broadcom-wl/patches/912-pci-bus-nvram-hack.patch",
    "content": "--- a/driver/siutils.c\n+++ b/driver/siutils.c\n@@ -1859,7 +1859,7 @@ BCMINITFN(si_devpath)(si_t *sih, char *p\n \tcase PCI_BUS:\n \t\tASSERT((SI_INFO(sih))->osh != NULL);\n \t\tslen = snprintf(path, (size_t)size, \"pci/%u/%u/\",\n-\t\t                OSL_PCI_BUS((SI_INFO(sih))->osh),\n+\t\t                OSL_PCI_BUS((SI_INFO(sih))->osh) + 1,\n \t\t                OSL_PCI_SLOT((SI_INFO(sih))->osh));\n \t\tbreak;\n \tcase PCMCIA_BUS:\n"
  },
  {
    "path": "package/kernel/broadcom-wl/patches/913-avoid-dbe-on-ifs_ctl-readw-hack.patch",
    "content": "--- a/driver/linux_osl.c\n+++ b/driver/linux_osl.c\n@@ -723,6 +723,9 @@ osl_readl(volatile uint32 *r)\n uint16\n osl_readw(volatile uint16 *r)\n {\n+\tuint32 addr = (uintptr)r & 0xffff3fff;\n+\tif (addr == 0xa8000688)\t/* ifs_ctl */\n+\t\treadl(r);\n \treturn (readw(r));\n }\n \n"
  },
  {
    "path": "package/kernel/broadcom-wl/patches/914-eliminate-date-time-error.patch",
    "content": "--- a/driver/wl_linux.c\n+++ b/driver/wl_linux.c\n@@ -762,7 +762,7 @@ wl_attach(uint16 vendor, uint16 device,\n \t\tdev->name, device);\n \n #ifdef BCMDBG\n-\tprintf(\" (Compiled in \" SRCBASE \" at \" __TIME__ \" on \" __DATE__ \")\");\n+\tprintf(\" (Compiled in \" SRCBASE \")\");\n #endif /* BCMDBG */\n \tprintf(\"\\n\");\n \n@@ -2298,8 +2298,7 @@ wl_sendup(wl_info_t *wl, wl_if_t *wlif,\n void\n wl_dump_ver(wl_info_t *wl, struct bcmstrbuf *b)\n {\n-\tbcm_bprintf(b, \"wl%d: %s %s version %s\\n\", wl->pub->unit,\n-\t\t__DATE__, __TIME__, EPI_VERSION_STR);\n+\tbcm_bprintf(b, \"wl%d: version %s\\n\", wl->pub->unit, EPI_VERSION_STR);\n }\n \n #ifdef BCMDBG\n"
  },
  {
    "path": "package/kernel/broadcom-wl/patches/915-fix-wl_timer-for-4_15.patch",
    "content": "--- a/driver/wl_linux.c\n+++ b/driver/wl_linux.c\n@@ -235,7 +235,11 @@\n \n };\n \n+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 15, 0)\n+static void wl_timer(struct timer_list *tl);\n+#else\n static void wl_timer(ulong data);\n+#endif\n static void _wl_timer(wl_timer_t *t);\n \n #ifdef WLC_HIGH_ONLY\n@@ -2512,6 +2517,18 @@\n }\n #endif /* WLC_HIGH_ONLY */\n \n+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 15, 0)\n+static void\n+wl_timer(struct timer_list *tl)\n+{\n+\twl_timer_t *t = from_timer(t, tl, timer);\n+#ifndef WLC_HIGH_ONLY\n+\t_wl_timer(t);\n+#else\n+\twl_schedule_task(t->wl, wl_timer_task, t);\n+#endif /* WLC_HIGH_ONLY */\n+}\n+#else\n static void\n wl_timer(ulong data)\n {\n@@ -2522,6 +2539,7 @@\n \twl_schedule_task(t->wl, wl_timer_task, t);\n #endif /* WLC_HIGH_ONLY */\n }\n+#endif /* linux >= 4.15.0 */\n \n static void\n _wl_timer(wl_timer_t *t)\n@@ -2573,9 +2591,13 @@\n \n \tbzero(t, sizeof(wl_timer_t));\n \n+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 15, 0)\n+\ttimer_setup(&t->timer, wl_timer, 0);\n+#else\n \tinit_timer(&t->timer);\n \tt->timer.data = (ulong) t;\n \tt->timer.function = wl_timer;\n+#endif\n \tt->wl = wl;\n \tt->fn = fn;\n \tt->arg = arg;\n"
  },
  {
    "path": "package/kernel/broadcom-wl/patches/916-fix-compilation-for-5_4.patch",
    "content": "--- a/driver/wl_iw.c\n+++ b/driver/wl_iw.c\n@@ -112,10 +112,14 @@\n \tifr.ifr_data = (caddr_t) &ioc;\n \n \t/* Must be up for virtually all useful ioctls */\n+#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 0, 0)\n+\tdev_open(dev, NULL);\n+#else\n \tdev_open(dev);\n+#endif\n \n \tfs = get_fs();\n-\tset_fs(get_ds());\n+\tset_fs(KERNEL_DS);\n \tret = dev->netdev_ops->ndo_do_ioctl(dev, &ifr, SIOCDEVPRIVATE);\n \tset_fs(fs);\n \n"
  },
  {
    "path": "package/kernel/broadcom-wl/src/glue/Makefile",
    "content": "#\n# Makefile for wl_glue driver\n#\n# Copyright (C) 2011 Jo-Philipp Wich <jo@mein.io>\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License\n# as published by the Free Software Foundation; either version\n# 2 of the License, or (at your option) any later version.\n#\n\nobj-m := wl_glue.o\n\nifeq ($(MAKING_MODULES),1)\n-include $(TOPDIR)/Rules.make\nendif\n\n"
  },
  {
    "path": "package/kernel/broadcom-wl/src/glue/wl_glue.c",
    "content": "/*\n * wl_glue.c: Broadcom WL support module providing a unified SSB/BCMA handling.\n * Copyright (C) 2011 Jo-Philipp Wich <jo@mein.io>\n */\n\n#include \"wl_glue.h\"\n\n#include <linux/kernel.h>\n#include <linux/module.h>\n#include <linux/init.h>\n\n#ifdef CONFIG_BCM47XX\n#include <bcm47xx.h>\n#endif\n\n#ifdef CONFIG_SSB\n#include <linux/ssb/ssb.h>\n#endif\n\n#ifdef CONFIG_BCMA\n#include <linux/bcma/bcma.h>\n#endif\n\nMODULE_AUTHOR(\"Jo-Philipp Wich (jo@mein.io)\");\nMODULE_DESCRIPTION(\"Broadcom WL SSB/BCMA compatibility layer\");\nMODULE_LICENSE(\"GPL\");\n\nstatic wl_glue_attach_cb_t attach_cb = NULL;\nstatic wl_glue_remove_cb_t remove_cb = NULL;\nstatic enum wl_glue_bus_type active_bus_type = WL_GLUE_BUS_TYPE_UNSPEC;\nstatic int wl_glue_attached = 0;\n\n\n#ifdef CONFIG_SSB\nstatic int wl_glue_ssb_probe(struct ssb_device *dev, const struct ssb_device_id *id)\n{\n\tvoid *mmio;\n\tvoid *wldev;\n\n\tif (!attach_cb)\n\t{\n\t\tpr_err(\"No attach callback registered\\n\");\n\t\treturn -ENOSYS;\n\t}\n\n\tif (dev->bus->bustype != SSB_BUSTYPE_SSB)\n\t{\n\t\tpr_err(\"Attaching to SSB behind PCI is not supported. Please remove the b43 ssb bridge\\n\");\n\t\treturn -EINVAL;\n\t}\n\n\tmmio = (void *) 0x18000000 + dev->core_index * 0x1000;\n\twldev = attach_cb(id->vendor, id->coreid, (ulong)mmio, dev, dev->irq);\n\n\tif (!wldev)\n\t{\n\t\tpr_err(\"The attach callback failed, SSB probe aborted\\n\");\n\t\treturn -ENODEV;\n\t}\n\n\tssb_set_drvdata(dev, wldev);\n\treturn 0;\n}\n\nstatic void wl_glue_ssb_remove(struct ssb_device *dev)\n{\n\tvoid *wldev = ssb_get_drvdata(dev);\n\n\tif (remove_cb)\n\t\tremove_cb(wldev);\n\n\tssb_set_drvdata(dev, NULL);\n}\n\nstatic const struct ssb_device_id wl_glue_ssb_tbl[] = {\n\tSSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, SSB_ANY_REV),\n\t{},\n};\n\nstatic struct ssb_driver wl_glue_ssb_driver = {\n\t.name     = KBUILD_MODNAME,\n\t.id_table = wl_glue_ssb_tbl,\n\t.probe    = wl_glue_ssb_probe,\n\t.remove   = wl_glue_ssb_remove,\n};\n#endif /* CONFIG_SSB */\n\n#ifdef CONFIG_BCMA\nstatic int wl_glue_bcma_probe(struct bcma_device *dev)\n{\n\tvoid *wldev;\n\n\tif (!attach_cb)\n\t{\n\t\tpr_err(\"No attach callback registered\\n\");\n\t\treturn -ENOSYS;\n\t}\n\n\tif (dev->bus->hosttype != BCMA_HOSTTYPE_SOC)\n\t{\n\t\tpr_err(\"Unsupported BCMA bus type %d\\n\", dev->bus->hosttype);\n\t\treturn -EINVAL;\n\t}\n\n\t/*\n\t * NB:\n\t * 0x18000000 = BCMA_ADDR_BASE\n\t * 0x1000     = BCMA_CORE_SIZE\n\t */\n\n\twldev = attach_cb(dev->id.manuf, dev->id.id, (ulong)dev->addr, dev, dev->irq);\n\n\tif (!wldev)\n\t{\n\t\tpr_err(\"The attach callback failed, BCMA probe aborted\\n\");\n\t\treturn -ENODEV;\n\t}\n\n\tbcma_set_drvdata(dev, wldev);\n\treturn 0;\n}\n\nstatic void wl_glue_bcma_remove(struct bcma_device *dev)\n{\n\tvoid *wldev = bcma_get_drvdata(dev);\n\n\tif (remove_cb)\n\t\tremove_cb(wldev);\n\n\tbcma_set_drvdata(dev, NULL);\n}\n\nstatic const struct bcma_device_id wl_glue_bcma_tbl[] = {\n\tBCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, BCMA_ANY_REV, BCMA_ANY_CLASS),\n\t{},\n};\n\nstatic struct bcma_driver wl_glue_bcma_driver = {\n\t.name     = KBUILD_MODNAME,\n\t.id_table = wl_glue_bcma_tbl,\n\t.probe    = wl_glue_bcma_probe,\n\t.remove   = wl_glue_bcma_remove,\n};\n#endif /* CONFIG_BCMA */\n\n\nvoid wl_glue_set_attach_callback(wl_glue_attach_cb_t cb)\n{\n\tattach_cb = cb;\n}\nEXPORT_SYMBOL(wl_glue_set_attach_callback);\n\nvoid wl_glue_set_remove_callback(wl_glue_remove_cb_t cb)\n{\n\tremove_cb = cb;\n}\nEXPORT_SYMBOL(wl_glue_set_remove_callback);\n\nint wl_glue_register(void)\n{\n\tint err;\n\n\tswitch(active_bus_type)\n\t{\n#ifdef CONFIG_SSB\n\tcase WL_GLUE_BUS_TYPE_SSB:\n\t\terr = ssb_driver_register(&wl_glue_ssb_driver);\n\t\tbreak;\n#endif /* CONFIG_SSB */\n\n#ifdef CONFIG_BCMA\n\tcase WL_GLUE_BUS_TYPE_BCMA:\n\t\terr = bcma_driver_register(&wl_glue_bcma_driver);\n\t\tbreak;\n#endif /* CONFIG_BCMA */\n\n\tdefault:\n\t\tpr_err(\"Not attaching through glue driver due to unsupported bus\\n\");\n\t\terr = -ENOSYS;\n\t\tbreak;\n\t}\n\n\tif (!err)\n\t{\n\t\tpr_info(\"SSB/BCMA glue driver successfully attached\\n\");\n\t\twl_glue_attached = 1;\n\t}\n\n\treturn err;\n}\nEXPORT_SYMBOL(wl_glue_register);\n\nint wl_glue_unregister(void)\n{\n\tint err;\n\n\tif (!wl_glue_attached)\n\t\treturn -ENOSYS;\n\n\tswitch (active_bus_type)\n\t{\n#ifdef CONFIG_SSB\n\tcase WL_GLUE_BUS_TYPE_SSB:\n\t\tssb_driver_unregister(&wl_glue_ssb_driver);\n\t\terr = 0;\n\t\tbreak;\n#endif /* CONFIG_SSB */\n\n#ifdef CONFIG_BCMA\n\tcase WL_GLUE_BUS_TYPE_BCMA:\n\t\tbcma_driver_unregister(&wl_glue_bcma_driver);\n\t\terr = 0;\n\t\tbreak;\n#endif /* CONFIG_BCMA */\n\n\tdefault:\n\t\tpr_err(\"Not removing glue driver due to unsupported bus\\n\");\n\t\terr = -ENOSYS;\n\t\tbreak;\n\t}\n\n\tif (!err)\n\t{\n\t\tpr_info(\"SSB/BCMA glue driver successfully detached\\n\");\n\t\twl_glue_attached = 0;\n\t}\n\n\treturn err;\n}\nEXPORT_SYMBOL(wl_glue_unregister);\n\nstruct device * wl_glue_get_dmadev(void *dev)\n{\n\tstruct device *dma_dev;\n\n\tswitch (active_bus_type)\n\t{\n#ifdef CONFIG_SSB\n\tcase WL_GLUE_BUS_TYPE_SSB:\n\t\tdma_dev = ((struct ssb_device *)dev)->dma_dev;\n\t\tbreak;\n#endif /* CONFIG_SSB */\n\n#ifdef CONFIG_BCMA\n\tcase WL_GLUE_BUS_TYPE_BCMA:\n\t\tdma_dev = ((struct bcma_device *)dev)->dma_dev;\n\t\tbreak;\n#endif /* CONFIG_BCMA */\n\n\tdefault:\n\t\tBUG();\n\t\tdma_dev = NULL;\n\t\tbreak;\n\t}\n\n\treturn dma_dev;\n}\nEXPORT_SYMBOL(wl_glue_get_dmadev);\n\n\nstatic int __init wl_glue_init(void)\n{\n#ifdef CONFIG_BCM47XX\n\t/*\n\t * BCM47xx currently supports either SSB or BCMA bus,\n\t * determine the used one from the info set by the\n\t * platform setup code.\n\t */\n\tswitch (bcm47xx_bus_type)\n\t{\n#ifdef CONFIG_BCM47XX_SSB\n\tcase BCM47XX_BUS_TYPE_SSB:\n\t\tactive_bus_type = WL_GLUE_BUS_TYPE_SSB;\n\t\tbreak;\n#endif /* CONFIG_BCM47XX_SSB */\n\n#ifdef CONFIG_BCM47XX_BCMA\n\tcase BCM47XX_BUS_TYPE_BCMA:\n\t\tactive_bus_type = WL_GLUE_BUS_TYPE_BCMA;\n\t\tbreak;\n#endif /* CONFIG_BCM47XX_BCMA */\n\t}\n#endif /* CONFIG_BCM47XX */\n\n#ifdef CONFIG_BCM63XX\n#ifdef CONFIG_SSB\n\t/*\n\t * BCM63xx currently only uses SSB, so assume that.\n\t */\n\tactive_bus_type = WL_GLUE_BUS_TYPE_SSB;\n#endif /* CONFIG_SSB */\n#endif /* CONFIG_BCM63XX */\n\n\t/* do not fail here, let wl_glue_register() return -ENOSYS later */\n\tif (active_bus_type == WL_GLUE_BUS_TYPE_UNSPEC)\n\t\tpr_err(\"Unable to determine used system bus type\\n\");\n\n\treturn 0;\n}\n\nstatic void __exit wl_glue_exit(void)\n{\n\tif (wl_glue_attached)\n\t{\n\t\tif (wl_glue_unregister())\n\t\t\tpr_err(\"Failed to unregister glue driver\\n\");\n\n\t\twl_glue_attached = 0;\n\t}\n\n\treturn;\n}\n\nmodule_init(wl_glue_init);\nmodule_exit(wl_glue_exit);\n"
  },
  {
    "path": "package/kernel/broadcom-wl/src/glue/wl_glue.h",
    "content": "/*\n * wl_glue.h: Broadcom WL support module providing a unified SSB/BCMA handling.\n * Copyright (C) 2011 Jo-Philipp Wich <jo@mein.io>\n */\n\n#include <linux/types.h>\n\ntypedef void * (*wl_glue_attach_cb_t)(u16, u16, ulong, void *, u32);\ntypedef void (*wl_glue_remove_cb_t)(void *);\n\nenum wl_glue_bus_type {\n\tWL_GLUE_BUS_TYPE_UNSPEC,\n\tWL_GLUE_BUS_TYPE_SSB,\n\tWL_GLUE_BUS_TYPE_BCMA\n};\n\nextern void wl_glue_set_attach_callback(wl_glue_attach_cb_t cb);\nextern void wl_glue_set_remove_callback(wl_glue_remove_cb_t cb);\nextern int wl_glue_register(void);\nextern int wl_glue_unregister(void);\nextern struct device * wl_glue_get_dmadev(void *);\n\n"
  },
  {
    "path": "package/kernel/broadcom-wl/src/wlc.c",
    "content": "/*\n * wlc - Broadcom Wireless Driver Control Utility\n *\n * Copyright (C) 2006 Felix Fietkau <nbd@nbd.name>\n *\n * This program is free software; you can redistribute it and/or\n * modify it under the terms of the GNU General Public License\n * as published by the Free Software Foundation; either version 2\n * of the License, or (at your option) any later version.\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n * GNU General Public License for more details.\n */\n\n#include <sys/types.h>\n#include <sys/stat.h>\n#include <unistd.h>\n#include <stdio.h>\n#include <stdlib.h>\n#include <string.h>\n#include <fcntl.h>\n#include <glob.h>\n#include <ctype.h>\n\n#include <typedefs.h>\n#include <wlutils.h>\n#include <proto/802.11.h>\n\n#define VERSION \"0.1\"\n#define BUFSIZE 8192\n#define PTABLE_MAGIC 0xbadc0ded\n#define PTABLE_SLT1 1\n#define PTABLE_SLT2 2\n#define PTABLE_ACKW 3\n#define PTABLE_ADHM 4\n#define PTABLE_END 0xffffffff\n\n/* \n * Copy each token in wordlist delimited by space into word \n * Taken from Broadcom shutils.h\n */\n#define foreach(word, wordlist, next) \\\n\tfor (next = &wordlist[strspn(wordlist, \" \")], \\\n\t\t strncpy(word, next, sizeof(word)), \\\n\t\t word[strcspn(word, \" \")] = '\\0', \\\n\t\t word[sizeof(word) - 1] = '\\0', \\\n\t\t next = strchr(next, ' '); \\\n\t\t strlen(word); \\\n\t\t next = next ? &next[strspn(next, \" \")] : \"\", \\\n\t\t strncpy(word, next, sizeof(word)), \\\n\t\t word[strcspn(word, \" \")] = '\\0', \\\n\t\t word[sizeof(word) - 1] = '\\0', \\\n\t\t next = strchr(next, ' '))\n\nstatic char wlbuf[8192];\nstatic char interface[16] = \"wl0\";\nstatic unsigned long kmem_offset = 0;\nstatic int vif = 0, debug = 1, fromstdin = 0;\n\ntypedef enum {\n\tNONE =   0x00,\n\n\t/* types */\n\tPARAM_TYPE =    0x00f,\n\tINT =    0x001,\n\tSTRING = 0x002,\n\tMAC =    0x003,\n\n\t/* options */\n\tPARAM_OPTIONS = 0x0f0,\n\tNOARG =  0x010,\n\n\t/* modes */\n\tPARAM_MODE =    0xf00,\n\tGET =    0x100,\n\tSET =    0x200,\n} wlc_param;\n\nstruct wlc_call {\n\tconst char *name;\n\twlc_param param;\n\tint (*handler)(wlc_param param, void *data, void *value);\n\tunion {\n\t\tint num;\n\t\tchar *str;\n\t\tvoid *ptr;\n\t} data;\n\tconst char *desc;\n};\n\n/* can't use the system include because of the stupid broadcom header files */\nextern struct ether_addr *ether_aton(const char *asc);\nstatic inline int my_ether_ntoa(unsigned char *ea, char *buf)\n{\n\treturn sprintf(buf, \"%02x:%02x:%02x:%02x:%02x:%02x\",\n\t\tea[0], ea[1], ea[2], ea[3], ea[4], ea[5]);\n}\n\nstatic int wlc_ioctl(wlc_param param, void *data, void *value)\n{\n\tunsigned int *var = ((unsigned int *) data);\n\tunsigned int ioc = *var;\n\n\tif (param & NOARG) {\n\t\treturn wl_ioctl(interface, ioc, NULL, 0);\n\t}\n\tswitch(param & PARAM_TYPE) {\n\t\tcase MAC:\n\t\t\treturn wl_ioctl(interface, ((param & SET) ? (ioc) : (ioc >> 16)) & 0xffff, value, 6);\n\t\tcase INT:\n\t\t\treturn wl_ioctl(interface, ((param & SET) ? (ioc) : (ioc >> 16)) & 0xffff, value, sizeof(int));\n\t\tcase STRING:\n\t\t\treturn wl_ioctl(interface, ((param & SET) ? (ioc) : (ioc >> 16)) & 0xffff, value, BUFSIZE);\n\t}\n\treturn 0;\n}\n\nstatic int wlc_iovar(wlc_param param, void *data, void *value)\n{\n\tint *val = (int *) value;\n\tchar *iov = *((char **) data);\n\tint ret = 0;\n\t\n\tif (param & SET) {\n\t\tswitch(param & PARAM_TYPE) {\n\t\t\tcase INT:\n\t\t\t\tret = wl_iovar_setint(interface, iov, *val);\n\t\t\t\tbreak;\n\t\t\tcase MAC:\n\t\t\t\tret = wl_iovar_set(interface, iov, value, 6);\n\t\t\t\tbreak;\n\t\t}\n\t}\n\tif (param & GET) {\n\t\tswitch(param & PARAM_TYPE) {\n\t\t\tcase INT:\n\t\t\t\tret = wl_iovar_get(interface, iov, val, sizeof(int));\n\t\t\t\tbreak;\n\t\t\tcase MAC:\n\t\t\t\tret = wl_iovar_get(interface, iov, value, 6);\n\t\t\t\tbreak;\n\t\t}\n\t}\n\n\treturn ret;\n}\n\nstatic int wlc_bssiovar(wlc_param param, void *data, void *value)\n{\n\tint *val = (int *) value;\n\tchar *iov = *((char **) data);\n\tint ret = 0;\n\t\n\tif (param & SET) {\n\t\tswitch(param & PARAM_TYPE) {\n\t\t\tcase INT:\n\t\t\t\tret = wl_bssiovar_setint(interface, iov, vif, *val);\n\t\t}\n\t}\n\tif (param & GET) {\n\t\tswitch(param & PARAM_TYPE) {\n\t\t\tcase INT:\n\t\t\t\tret = wl_bssiovar_get(interface, iov, vif, val, sizeof(int));\n\t\t}\n\t}\n\n\treturn ret;\n}\n\nstatic int wlc_vif_enabled(wlc_param param, void *data, void *value)\n{\n\tint *val = (int *) value;\n\tint buf[3];\n\tint ret = 0;\n\t\n\tsprintf((char *) buf, \"bss\");\n\tbuf[1] = vif;\n\tif (param & SET) {\n\t\tbuf[2] = (*val ? 1 : 0);\n\t\tret = wl_ioctl(interface, WLC_SET_VAR, buf, sizeof(buf));\n\t} else if (param & GET) {\n\t\tret = wl_ioctl(interface, WLC_GET_VAR, buf, sizeof(buf));\n\t\t*val = buf[0];\n\t}\n\n\treturn ret;\n}\n\nstatic int wlc_ssid(wlc_param param, void *data, void *value)\n{\n\tint ret = -1, ret2 = -1;\n\tchar *dest = (char *) value;\n\twlc_ssid_t ssid;\n\t\n\tif ((param & PARAM_MODE) == GET) {\n\t\tret = wl_bssiovar_get(interface, \"ssid\", vif, &ssid, sizeof(ssid));\n\n\t\tif (ret)\n\t\t\t/* if we can't get the ssid through the bssiovar, try WLC_GET_SSID */\n\t\t\tret = wl_ioctl(interface, WLC_GET_SSID, &ssid, sizeof(ssid));\n\t\t\n\t\tif (!ret) {\n\t\t\tmemcpy(dest, ssid.SSID, ssid.SSID_len);\n\t\t\tdest[ssid.SSID_len] = 0;\n\t\t}\n\t} else if ((param & PARAM_MODE) == SET) {\n\t\tstrncpy(ssid.SSID, value, 32);\n\t\tssid.SSID_len = strlen(value);\n\t\t\n\t\tif (ssid.SSID_len > 32)\n\t\t\tssid.SSID_len = 32;\n\t\t\n\t\tif (vif == 0) {\n\t\t\t/* for the main interface, also try the WLC_SET_SSID call */\n\t\t\tret2 = wl_ioctl(interface, WLC_SET_SSID, &ssid, sizeof(ssid));\n\t\t}\n\t\t\n\t\tret = wl_bssiovar_set(interface, \"ssid\", vif, &ssid, sizeof(ssid));\n\t\tret = (!ret2 ? 0 : ret);\n\t}\n\t\n\treturn ret;\n}\n\nstatic int wlc_int(wlc_param param, void *data, void *value)\n{\n\tint *var = *((int **) data);\n\tint *val = (int *) value;\n\n\tif ((param & PARAM_MODE) == SET) {\n\t\t*var = *val;\n\t} else if ((param & PARAM_MODE) == GET) {\n\t\t*val = *var;\n\t}\n\n\treturn 0;\n}\n\nstatic int wlc_flag(wlc_param param, void *data, void *value)\n{\n\tint *var = *((int **) data);\n\n\t*var = 1;\n\n\treturn 0;\n}\n\nstatic int wlc_string(wlc_param param, void *data, void *value)\n{\n\tchar *var = *((char **) data);\n\t\n\tif ((param & PARAM_MODE) == GET) {\n\t\tstrcpy(value, var);\n\t}\n\n\treturn 0;\n}\n\nstatic int wlc_afterburner(wlc_param param, void *data, void *value)\n{\n\tint *val = (int *) value;\n\tint ret = 0;\n\n\tif ((param & PARAM_MODE) == GET) {\n\t\tret = wl_iovar_get(interface, \"afterburner\", val, sizeof(int));\n\t} else {\n\t\twl_iovar_setint(interface, \"wlfeatureflag\", (*val ? 3 : 0));\n\t\tret = wl_iovar_setint(interface, \"afterburner\", (*val ? 1 : 0));\n\t\twl_iovar_setint(interface, \"afterburner_override\", *val);\n\t}\n\n\treturn ret;\n}\n\nstatic int wlc_maclist(wlc_param param, void *data, void *value)\n{\n\tunsigned int *var = ((unsigned int *) data);\n\tunsigned int ioc = *var;\n\tint limit = (sizeof(wlbuf) - 4) / sizeof(struct ether_addr);\n\tstruct maclist *list = (struct maclist *) wlbuf;\n\tchar *str = (char *) value;\n\tchar astr[30], *p;\n\tstruct ether_addr *addr;\n\tint isset = 0;\n\tint ret;\n\n\tif ((param & PARAM_MODE) == GET) {\n\t\tlist->count = limit;\n\t\tret = wl_ioctl(interface, (ioc >> 16) & 0xffff, wlbuf, sizeof(wlbuf));\n\t\t\n\t\tif (!ret) \n\t\t\twhile (list->count) {\n\t\t\t\tstr += sprintf(str, \"%s\", ((((char *) value) == str) ? \"\" : \" \"));\n\t\t\t\tstr += my_ether_ntoa((unsigned char *) &list->ea[list->count-- - 1], str);\n\t\t\t}\n\t\t\n\t\treturn ret;\n\t} else {\n\t\twhile (*str && isspace(*str))\n\t\t\t*str++;\n\t\t\n\t\tif (*str == '+') {\n\t\t\tstr++;\n\n\t\t\tlist->count = limit;\n\t\t\tif (wl_ioctl(interface, (ioc >> 16) & 0xffff, wlbuf, sizeof(wlbuf)) == 0)\n\t\t\t\tisset = 1;\n\n\t\t\twhile (*str && isspace(*str))\n\t\t\t\tstr++;\n\t\t}\n\t\t\n\t\tif (!isset)\n\t\t\tmemset(wlbuf, 0, sizeof(wlbuf));\n\t\t\n\t\tforeach(astr, str, p) {\n\t\t\tif (list->count >= limit)\n\t\t\t\tbreak;\n\t\t\t\n\t\t\tif ((addr = ether_aton(astr)) != NULL)\n\t\t\t\tmemcpy(&list->ea[list->count++], addr, sizeof(struct ether_addr));\n\t\t}\n\n\t\treturn wl_ioctl(interface, ioc & 0xffff, wlbuf, sizeof(wlbuf));\n\t}\n}\n\nstatic int wlc_radio(wlc_param param, void *data, void *value)\n{\n\tint *val = (int *) value;\n\tint ret;\n\n\tif ((param & PARAM_MODE) == GET) {\n\t\tret = wl_ioctl(interface, WLC_GET_RADIO, val, sizeof(int));\n\t\t*val = ((*val & 1) ? 0 : 1);\n\t} else {\n\t\t*val = (1 << 16) | (*val ? 0 : 1); \n\t\tret = wl_ioctl(interface, WLC_SET_RADIO, val, sizeof(int));\n\t}\n\n\treturn ret;\n}\n\nstatic int wlc_wsec_key(wlc_param param, void *null, void *value)\n{\n\twl_wsec_key_t wsec_key;\n\tunsigned char *index = value;\n\tunsigned char *key;\n\tunsigned char *data;\n\tunsigned char hex[3];\n\t\n\tif ((param & PARAM_MODE) != SET)\n\t\treturn 0;\n\n\tmemset(&wsec_key, 0, sizeof(wsec_key));\n\tif (index[0] == '=') {\n\t\twsec_key.flags = WL_PRIMARY_KEY;\n\t\tindex++;\n\t}\n\t\n\tif ((index[0] < '1') || (index[0] > '4') || (index[1] != ','))\n\t\treturn -1;\n\t\n\tkey = index + 2;\n\tif (strncmp(key, \"d:\", 2) == 0) { /* delete key */\n\t} else if (strncmp(key, \"s:\", 2) == 0) { /* ascii key */\n\t\tkey += 2;\n\t\twsec_key.len = strlen(key);\n\n\t\tif ((wsec_key.len != 5) && (wsec_key.len != 13))\n\t\t\treturn -1;\n\t\t\n\t\tstrcpy(wsec_key.data, key);\n\t} else { /* hex key */\n\t\twsec_key.len = strlen(key);\n\t\tif ((wsec_key.len != 10) && (wsec_key.len != 26))\n\t\t\treturn -1;\n\t\t\n\t\twsec_key.len /= 2;\n\t\tdata = wsec_key.data;\n\t\thex[2] = 0;\n\t\tdo {\n\t\t\thex[0] = *(key++);\n\t\t\thex[1] = *(key++);\n\t\t\t*(data++) = (unsigned char) strtoul(hex, NULL, 16);\n\t\t} while (*key != 0);\n\t}\n\n\treturn wl_bssiovar_set(interface, \"wsec_key\", vif, &wsec_key, sizeof(wsec_key));\n}\n\nstatic int wlc_cap(wlc_param param, void *data, void *value)\n{\n\tchar *iov = *((char **) data);\n\n\tif (param & GET)\n\t\treturn wl_iovar_get(interface, iov, value, BUFSIZE);\n\n\treturn -1;\n}\n\nstatic int wlc_bssmax(wlc_param param, void *data, void *value)\n{\n\tint *val = (int *) value;\n\tchar *iov = *((char **) data);\n\tint ret = -1;\n\n\tif (param & GET) {\n\t\tret = wl_iovar_get(interface, iov, wlbuf, BUFSIZE);\n\t\tif (!ret) {\n\t\t\tif (strstr(wlbuf, \"mbss4\"))\n\t\t\t\t*val = 4;\n\t\t\telse if (strstr(wlbuf, \"mbss16\"))\n\t\t\t\t*val = 16;\n\t\t\telse\n\t\t\t\t*val = 1;\n\t\t}\n\t}\n\n\treturn ret;\n}\n\nstatic inline int cw2ecw(int cw)\n{\n\tint i;\t\n\tfor (cw++, i = 0; cw; i++) cw >>=1;\n\treturn i - 1;\n}\n\nstatic int wlc_wme_ac(wlc_param param, void *data, void *value)\n{\n\tchar *type = *((char **) data);\n\tchar *settings = (char *) value;\n\tchar cmd[100], *p, *val;\n\tedcf_acparam_t params[AC_COUNT];\n\tint ret;\n\tint intval;\n\tint cur = -1;\n\tchar *buf = wlbuf;\n\n\tif ((param & PARAM_MODE) != SET)\n\t\treturn -1;\n\t\n\tmemset(params, 0, sizeof(params));\n\tret = wl_iovar_get(interface, type, params, sizeof(params));\n\tmemset(buf, 0, BUFSIZE);\n\tstrcpy(buf, type);\n\tbuf += strlen(buf) + 1;\n\t\n\tforeach(cmd, settings, p) {\n\t\tval = strchr(cmd, '=');\n\t\tif (val == NULL) {\n\t\t\tif (strcmp(cmd, \"be\") == 0)\n\t\t\t\tcur = AC_BE;\n\t\t\telse if (strcmp(cmd, \"bk\") == 0)\n\t\t\t\tcur = AC_BK;\n\t\t\telse if (strcmp(cmd, \"vi\") == 0)\n\t\t\t\tcur = AC_VI;\n\t\t\telse if (strcmp(cmd, \"vo\") == 0)\n\t\t\t\tcur = AC_VO;\n\t\t\telse\n\t\t\t\treturn -1;\n\n\t\t\t/* just in case */\n\t\t\tparams[cur].ACI = (params[cur].ACI & (0x3 << 5)) | (cur << 5);\n\t\t} else {\n\t\t\t*(val++) = 0;\n\t\t\t\n\t\t\tintval = strtoul(val, NULL, 10);\n\t\t\tif (strcmp(cmd, \"cwmin\") == 0)\n\t\t\t\tparams[cur].ECW = (params[cur].ECW & ~(0xf)) | cw2ecw(intval);\n\t\t\telse if (strcmp(cmd, \"ecwmin\") == 0)\n\t\t\t\tparams[cur].ECW = (params[cur].ECW & ~(0xf)) | (intval & 0xf);\n\t\t\telse if (strcmp(cmd, \"cwmax\") == 0)\n\t\t\t\tparams[cur].ECW = (params[cur].ECW & ~(0xf << 4)) | (cw2ecw(intval) << 4);\n\t\t\telse if (strcmp(cmd, \"ecwmax\") == 0)\n\t\t\t\tparams[cur].ECW = (params[cur].ECW & ~(0xf << 4)) | ((intval & 0xf) << 4);\n\t\t\telse if (strcmp(cmd, \"aifsn\") == 0)\n\t\t\t\tparams[cur].ACI = (params[cur].ACI & ~(0xf)) | (intval & 0xf);\n\t\t\telse if (strcmp(cmd, \"txop\") == 0)\n\t\t\t\tparams[cur].TXOP = intval >> 5;\n\t\t\telse if (strcmp(cmd, \"force\") == 0)\n\t\t\t\tparams[cur].ACI = (params[cur].ACI & ~(1 << 4)) | ((intval) ? (1 << 4) : 0);\n\t\t\telse return -1;\n\t\t\t\n\t\t\tmemcpy(buf, &params[cur], sizeof(edcf_acparam_t));\n\t\t\twl_ioctl(interface, WLC_SET_VAR, wlbuf, BUFSIZE);\n\t\t}\n\t}\n\treturn ret;\n}\n\nstatic int wlc_ifname(wlc_param param, void *data, void *value)\n{\n\tchar *val = (char *) value;\n\tint ret = 0;\n\t\n\tif (param & SET) {\n\t\tif (strlen(val) < 16)\n\t\t\tstrcpy(interface, val);\n\t\telse ret = -1;\n\t}\n\tif (param & GET) {\n\t\tstrcpy(val, interface);\n\t}\n\n\treturn ret;\n}\n\nstatic int wlc_wdsmac(wlc_param param, void *data, void *value)\n{\n\tunsigned char mac[6];\n\tint ret = 0;\n\t\n\tret = wl_ioctl(interface, WLC_WDS_GET_REMOTE_HWADDR, &mac, 6);\n\tif (ret == 0)\n\t\tmy_ether_ntoa(mac, value);\n\n\treturn ret;\n}\n\nstatic int wlc_pmk(wlc_param param, void *data, void *value)\n{\n\tint ret = -1;\n\tchar *str = (char *) value;\n\twsec_pmk_t pmk;\n\t\n\t/* driver doesn't support GET */\n\n\tif ((param & PARAM_MODE) == SET) {\n\t\tstrncpy(pmk.key, str, WSEC_MAX_PSK_LEN);\n\t\tpmk.key_len = strlen(str);\n\n\t\tif (pmk.key_len > WSEC_MAX_PSK_LEN)\n\t\t\tpmk.key_len = WSEC_MAX_PSK_LEN;\n\n\t\tpmk.flags = WSEC_PASSPHRASE;\n\n\t\tret = wl_ioctl(interface, WLC_SET_WSEC_PMK, &pmk, sizeof(pmk));\n\t}\n\t\n\treturn ret;\n}\n\nstatic const struct wlc_call wlc_calls[] = {\n\t{\n\t\t.name = \"version\",\n\t\t.param = STRING|NOARG,\n\t\t.handler = wlc_string,\n\t\t.data.str = VERSION,\n\t\t.desc = \"Version of this program\"\n\t},\n\t{\n\t\t.name = \"debug\",\n\t\t.param = INT,\n\t\t.handler = wlc_int,\n\t\t.data.ptr = &debug,\n\t\t.desc = \"wlc debug level\"\n\t},\n\t{\n\t\t.name = \"stdin\",\n\t\t.param = NOARG,\n\t\t.handler = wlc_flag,\n\t\t.data.ptr = &fromstdin,\n\t\t.desc = \"Accept input from stdin\"\n\t},\n\t{\n\t\t.name = \"ifname\",\n\t\t.param = STRING,\n\t\t.handler = wlc_ifname,\n\t\t.desc = \"interface to send commands to\"\n\t},\n\t{\n\t\t.name = \"up\",\n\t\t.param = NOARG,\n\t\t.handler = wlc_ioctl,\n\t\t.data.num = WLC_UP,\n\t\t.desc = \"Bring the interface up\"\n\t},\n\t{\n\t\t.name = \"down\",\n\t\t.param = NOARG,\n\t\t.handler = wlc_ioctl,\n\t\t.data.num = WLC_DOWN,\n\t\t.desc = \"Bring the interface down\"\n\t},\n\t{\n\t\t.name = \"radio\",\n\t\t.param = INT,\n\t\t.handler = wlc_radio,\n\t\t.desc = \"Radio enabled flag\"\n\t},\n\t{\n\t\t.name = \"ap\",\n\t\t.param = INT,\n\t\t.handler = wlc_ioctl,\n\t\t.data.num = ((WLC_GET_AP << 16) | WLC_SET_AP),\n\t\t.desc = \"Access Point mode\"\n\t},\n\t{\n\t\t.name = \"mssid\",\n\t\t.param = INT,\n\t\t.handler = wlc_iovar,\n\t\t.data.str = \"mbss\",\n\t\t.desc = \"Multi-ssid mode\"\n\t},\n\t{\n\t\t.name = \"apsta\",\n\t\t.param = INT,\n\t\t.handler = wlc_iovar,\n\t\t.data.str = \"apsta\",\n\t\t.desc = \"AP+STA mode\"\n\t},\n\t{\n\t\t.name = \"infra\",\n\t\t.param = INT,\n\t\t.handler = wlc_ioctl,\n\t\t.data.num = ((WLC_GET_INFRA << 16) | WLC_SET_INFRA),\n\t\t.desc = \"Infrastructure mode\"\n\t},\n\t{\n\t\t.name = \"wet\",\n\t\t.param = INT,\n\t\t.handler = wlc_ioctl,\n\t\t.data.num = ((WLC_GET_WET << 16) | WLC_SET_WET),\n\t\t.desc = \"Wireless repeater mode\",\n\t},\n\t{\n\t\t.name = \"statimeout\",\n\t\t.param = INT,\n\t\t.handler = wlc_iovar,\n\t\t.data.str = \"sta_retry_time\",\n\t\t.desc = \"STA connection timeout\"\n\t},\n\t{\n\t\t.name = \"country\",\n\t\t.param = STRING,\n\t\t.handler = wlc_ioctl,\n\t\t.data.num = ((WLC_GET_COUNTRY << 16) | WLC_SET_COUNTRY),\n\t\t.desc = \"Country code\"\n\t},\n\t{\n\t\t.name = \"channel\",\n\t\t.param = INT,\n\t\t.handler = wlc_ioctl,\n\t\t.data.num = ((WLC_GET_CHANNEL << 16) | WLC_SET_CHANNEL),\n\t\t.desc = \"Channel\",\n\t},\n\t{\n\t\t.name = \"vlan_mode\",\n\t\t.param = INT,\n\t\t.handler = wlc_bssiovar,\n\t\t.data.str = \"vlan_mode\",\n\t\t.desc = \"Parse 802.1Q tags\",\n\t},\n\t{\n\t\t.name = \"vif\",\n\t\t.param = INT,\n\t\t.handler = wlc_int,\n\t\t.data.ptr = &vif,\n\t\t.desc = \"Current vif index\"\n\t},\n\t{\n\t\t.name = \"enabled\",\n\t\t.param = INT,\n\t\t.handler = wlc_vif_enabled,\n\t\t.desc = \"vif enabled flag\"\n\t},\n\t{\n\t\t.name = \"ssid\",\n\t\t.param = STRING,\n\t\t.handler = wlc_ssid,\n\t\t.desc = \"Interface ESSID\"\n\t},\n\t{\n\t\t.name = \"closed\",\n\t\t.param = INT,\n\t\t.handler = wlc_bssiovar,\n\t\t.data.str = \"closednet\",\n\t\t.desc = \"Hidden ESSID flag\"\n\t},\n\t{\n\t\t.name = \"wsec\",\n\t\t.param = INT,\n\t\t.handler = wlc_bssiovar,\n\t\t.data.str = \"wsec\",\n\t\t.desc = \"Security mode flags\"\n\t},\n\t{\n\t\t.name = \"wepkey\",\n\t\t.param = STRING,\n\t\t.handler = wlc_wsec_key,\n\t\t.desc = \"Set/Remove WEP keys\"\n\t},\n\t{\n\t\t.name = \"wepauth\",\n\t\t.param = INT,\n\t\t.handler = wlc_ioctl,\n\t\t.data.num = ((WLC_GET_AUTH << 16) | WLC_SET_AUTH),\n\t\t.desc = \"WEP authentication type. 0 = OpenSystem, 1 = SharedKey\"\n\t},\n\t{\n\t\t.name = \"wsec_restrict\",\n\t\t.param = INT,\n\t\t.handler = wlc_bssiovar,\n\t\t.data.str = \"wsec_restrict\",\n\t\t.desc = \"Drop unencrypted traffic\"\n\t},\n\t{\n\t\t.name = \"eap_restrict\",\n\t\t.param = INT,\n\t\t.handler = wlc_bssiovar,\n\t\t.data.str = \"eap_restrict\",\n\t\t.desc = \"Only allow 802.1X traffic until 802.1X authorized\"\n\t},\n\t{\n\t\t.name = \"wpa_auth\",\n\t\t.param = INT,\n\t\t.handler = wlc_bssiovar,\n\t\t.data.str = \"wpa_auth\",\n\t\t.desc = \"WPA authentication modes\"\n\t},\n\t{\n\t\t.name = \"ap_isolate\",\n\t\t.param = INT,\n\t\t.handler = wlc_bssiovar,\n\t\t.data.str = \"ap_isolate\",\n\t\t.desc = \"Isolate connected clients\"\n\t},\n\t{\n\t\t.name = \"supplicant\",\n\t\t.param = INT,\n\t\t.handler = wlc_iovar,\n\t\t.data.str = \"sup_wpa\",\n\t\t.desc = \"Built-in WPA supplicant\"\n\t},\n\t{\n\t\t.name = \"passphrase\",\n\t\t.param = STRING,\n\t\t.handler = wlc_pmk,\n\t\t.desc = \"Passphrase for built-in WPA supplicant\",\n\t},\n\t{\n\t\t.name = \"maxassoc\",\n\t\t.param = INT,\n\t\t.handler = wlc_iovar,\n\t\t.data.str = \"maxassoc\",\n\t\t.desc = \"Max. number of associated clients\",\n\t},\n\t{\n\t\t.name = \"wme\",\n\t\t.param = INT,\n\t\t.handler = wlc_iovar,\n\t\t.data.str = \"wme\",\n\t\t.desc = \"WME enabled\"\n\t},\n\t{\n\t\t.name = \"wme_ac_ap\",\n\t\t.param = STRING,\n\t\t.handler = wlc_wme_ac,\n\t\t.data.str = \"wme_ac_ap\",\n\t\t.desc = \"Set WME AC options for AP mode\",\n\t},\n\t{\n\t\t.name = \"wme_ac_sta\",\n\t\t.param = STRING,\n\t\t.handler = wlc_wme_ac,\n\t\t.data.str = \"wme_ac_sta\",\n\t\t.desc = \"Set WME AC options for STA mode\",\n\t},\n\t{\n\t\t.name = \"wme_noack\",\n\t\t.param = INT,\n\t\t.handler = wlc_iovar,\n\t\t.data.str = \"wme_noack\",\n\t\t.desc = \"WME ACK disable request\",\n\t},\n\t{\n\t\t.name = \"802.11d\",\n\t\t.param = INT,\n\t\t.handler = wlc_ioctl,\n\t\t.data.num = ((WLC_GET_REGULATORY << 16) | WLC_SET_REGULATORY),\n\t\t.desc = \"Enable/disable 802.11d regulatory management\",\n\t},\n\t{\n\t\t.name = \"802.11h\",\n\t\t.param = INT,\n\t\t.handler = wlc_ioctl,\n\t\t.data.num = ((WLC_GET_SPECT_MANAGMENT << 16) | WLC_SET_SPECT_MANAGMENT),\n\t\t.desc = \"Enable/disable 802.11h spectrum management\",\n\t},\n\t{\n\t\t.name = \"fragthresh\",\n\t\t.param = INT,\n\t\t.handler = wlc_iovar,\n\t\t.data.str = \"fragthresh\",\n\t\t.desc = \"Fragmentation threshold\",\n\t},\n\t{\n\t\t.name = \"rtsthresh\",\n\t\t.param = INT,\n\t\t.handler = wlc_iovar,\n\t\t.data.str = \"rtsthresh\",\n\t\t.desc = \"RTS threshold\"\n\t},\n\t{\n\t\t.name = \"slottime\",\n\t\t.param = INT,\n\t\t.handler = wlc_iovar,\n\t\t.data.str = \"acktiming\",\n\t\t.desc = \"Slot time\"\n\t},\n\t{\n\t\t.name = \"rxant\",\n\t\t.param = INT,\n\t\t.handler = wlc_ioctl,\n\t\t.data.num = ((WLC_GET_ANTDIV << 16) | WLC_SET_ANTDIV),\n\t\t.desc = \"Rx antenna selection\"\n\t},\n\t{\n\t\t.name = \"txant\",\n\t\t.param = INT,\n\t\t.handler = wlc_ioctl,\n\t\t.data.num = ((WLC_GET_TXANT << 16) | WLC_SET_TXANT),\n\t\t.desc = \"Tx antenna selection\"\n\t},\n\t{\n\t\t.name = \"dtim\",\n\t\t.param = INT,\n\t\t.handler = wlc_ioctl,\n\t\t.data.num = ((WLC_GET_DTIMPRD << 16) | WLC_SET_DTIMPRD),\n\t\t.desc = \"DTIM period\",\n\t},\n\t{\n\t\t.name = \"bcn\",\n\t\t.param = INT,\n\t\t.handler = wlc_ioctl,\n\t\t.data.num = ((WLC_GET_BCNPRD << 16) | WLC_SET_BCNPRD),\n\t\t.desc = \"Beacon interval\"\n\t},\n\t{\n\t\t.name = \"frameburst\",\n\t\t.param = INT,\n\t\t.handler = wlc_ioctl,\n\t\t.data.num = ((WLC_GET_FAKEFRAG << 16) | WLC_SET_FAKEFRAG),\n\t\t.desc = \"Framebursting\"\n\t},\n\t{\n\t\t.name = \"monitor\",\n\t\t.param = INT,\n\t\t.handler = wlc_ioctl,\n\t\t.data.num = ((WLC_GET_MONITOR << 16) | WLC_SET_MONITOR),\n\t\t.desc = \"Monitor mode\"\n\t},\n\t{\n\t\t.name = \"passive_scan\",\n\t\t.param = INT,\n\t\t.handler = wlc_ioctl,\n\t\t.data.num = ((WLC_GET_PASSIVE_SCAN << 16) | WLC_SET_PASSIVE_SCAN),\n\t\t.desc = \"Passive scan mode\"\n\t},\n\t{\n\t\t.name = \"macfilter\",\n\t\t.param = INT,\n\t\t.handler = wlc_ioctl,\n\t\t.data.num = ((WLC_GET_MACMODE << 16) | WLC_SET_MACMODE),\n\t\t.desc = \"MAC filter mode (0:disabled, 1:deny, 2:allow)\"\n\t},\n\t{\n\t\t.name = \"maclist\",\n\t\t.param = STRING,\n\t\t.data.num = ((WLC_GET_MACLIST << 16) | WLC_SET_MACLIST),\n\t\t.handler = wlc_maclist,\n\t\t.desc = \"MAC filter list\"\n\t},\n\t{\n\t\t.name = \"autowds\",\n\t\t.param = INT,\n\t\t.handler = wlc_ioctl,\n\t\t.data.num = ((WLC_GET_LAZYWDS << 16) | WLC_SET_LAZYWDS),\n\t\t.desc = \"Automatic WDS\"\n\t},\n\t{\n\t\t.name = \"wds\",\n\t\t.param = STRING,\n\t\t.data.num = ((WLC_GET_WDSLIST << 16) | WLC_SET_WDSLIST),\n\t\t.handler = wlc_maclist,\n\t\t.desc = \"WDS connection list\"\n\t},\n\t{\n\t\t.name = \"wdstimeout\",\n\t\t.param = INT,\n\t\t.handler = wlc_iovar,\n\t\t.data.str = \"wdstimeout\",\n\t\t.desc = \"WDS link detection timeout\"\n\t},\n\t{\n\t\t.name = \"wdsmac\",\n\t\t.param = STRING|NOARG,\n\t\t.handler = wlc_wdsmac,\n\t\t.desc = \"MAC of the remote WDS endpoint (only with wds0.* interfaces)\"\n\t},\n\t{\n\t\t.name = \"afterburner\",\n\t\t.param = INT,\n\t\t.handler = wlc_afterburner,\n\t\t.desc = \"Broadcom Afterburner\"\n\t},\n\t{\n\t\t.name = \"ibss_merge\",\n\t\t.param = INT,\n\t\t.handler = wlc_iovar,\n\t\t.data.str = \"ibss_coalesce_allowed\",\n\t\t.desc = \"Allow IBSS merges\"\n\t},\n\t{\n\t\t.name = \"bssid\",\n\t\t.param = MAC,\n\t\t.handler = wlc_ioctl,\n\t\t.data.num = ((WLC_GET_BSSID << 16) | WLC_SET_BSSID),\n\t\t.desc = \"BSSID\"\n\t},\n\t{\n\t\t.name = \"cur_etheraddr\",\n\t\t.param = MAC,\n\t\t.handler = wlc_iovar,\n\t\t.data.str = \"cur_etheraddr\",\n\t\t.desc = \"Current MAC Address\"\n\t},\n\t{\n\t\t.name = \"default_bssid\",\n\t\t.param = MAC,\n\t\t.handler = wlc_iovar,\n\t\t.data.str = \"perm_etheraddr\",\n\t\t.desc = \"Default BSSID (read-only)\"\n\t},\n\t{\n\t\t.name = \"assoclist\",\n\t\t.param = STRING,\n\t\t.data.num = (WLC_GET_ASSOCLIST << 16),\n\t\t.handler = wlc_maclist,\n\t\t.desc = \"MACs of associated stations\"\n\t},\n\t{\n\t\t.name = \"gmode\",\n\t\t.param = INT,\n\t\t.data.num = ((WLC_GET_GMODE << 16) | WLC_SET_GMODE),\n\t\t.handler = wlc_ioctl,\n\t\t.desc = \"G Mode\"\n\t},\n\t{\n\t\t.name = \"phytype\",\n\t\t.param = INT,\n\t\t.data.num = (WLC_GET_PHYTYPE << 16),\n\t\t.handler = wlc_ioctl,\n\t\t.desc = \"PHY Type (read-only)\"\n\t},\n\t{\n\t\t.name = \"nmode\",\n\t\t.param = INT,\n\t\t.handler = wlc_iovar,\n\t\t.data.str = \"nmode\",\n\t\t.desc = \"N Mode\"\n\t},\n\t{\n\t\t.name = \"nreqd\",\n\t\t.param = INT,\n\t\t.handler = wlc_iovar,\n\t\t.data.str = \"nreqd\",\n\t\t.desc = \"N Mode required\"\n\t},\n\t{\n\t\t.name = \"chanspec\",\n\t\t.param = INT,\n\t\t.handler = wlc_iovar,\n\t\t.data.str = \"chanspec\",\n\t\t.desc = \"Channel Spec (See bcmwifi.h)\"\n\t},\n\t{\n\t\t.name = \"band\",\n\t\t.param = INT,\n\t\t.data.num = ((WLC_GET_BAND << 16) | WLC_SET_BAND),\n\t\t.handler = wlc_ioctl,\n\t\t.desc = \"Band (0=auto, 1=5Ghz, 2=2.4GHz)\"\n\t},\n\t{\n\t\t.name = \"cap\",\n\t\t.param = STRING|NOARG,\n\t\t.handler = wlc_cap,\n\t\t.data.str = \"cap\",\n\t\t.desc = \"Capabilities\"\n\t},\n\t{\n\t\t.name = \"bssmax\",\n\t\t.param = INT|NOARG,\n\t\t.handler = wlc_bssmax,\n\t\t.data.str = \"cap\",\n\t\t.desc = \"Number of VIF's supported\"\n\t},\n\t{\n\t\t.name = \"leddc\",\n\t\t.param = INT,\n\t\t.handler = wlc_iovar,\n\t\t.data.str = \"leddc\",\n\t\t.desc = \"LED Duty Cycle\"\n\t},\n\t\n};\n#define wlc_calls_size (sizeof(wlc_calls) / sizeof(struct wlc_call))\n\nstatic void usage(char *cmd)\n{\n\tint i;\n\tfprintf(stderr, \"Usage: %s <command> [<argument> ...]\\n\"\n\t\t\t\t\t\"\\n\"\n\t\t\t\t\t\"Available commands:\\n\", cmd);\n\tfor (i = 0; i < wlc_calls_size; i++) {\n\t\tfprintf(stderr, \"\\t%-16s\\t%s\\n\", wlc_calls[i].name ?: \"\", wlc_calls[i].desc ?: \"\");\n\t}\n\tfprintf(stderr, \"\\n\");\n\texit(1);\n}\n\nstatic int do_command(const struct wlc_call *cmd, char *arg)\n{\n\tstatic char buf[BUFSIZE];\n\tint set;\n\tint ret = 0;\n\tchar *format, *end;\n\tint intval;\n\tvoid *ptr = (void *) buf;\n\n\tif (debug >= 10) {\n\t\tfprintf(stderr, \"do_command %-16s\\t'%s'\\n\", cmd->name, arg);\n\t}\n\t\n\tif ((arg == NULL) && ((cmd->param & PARAM_TYPE) != NONE)) {\n\t\tset = 0;\n\t\tret = cmd->handler(cmd->param | GET, (void *) &cmd->data, (void *) buf);\n\t\tif (ret == 0) {\n\t\t\tswitch(cmd->param & PARAM_TYPE) {\n\t\t\t\tcase INT:\n\t\t\t\t\tintval = *((int *) buf);\n\t\t\t\t\t\n\t\t\t\t\tif (intval > 65535)\n\t\t\t\t\t\tformat = \"0x%08x\\n\";\n\t\t\t\t\telse if (intval > 255)\n\t\t\t\t\t\tformat = \"0x%04x\\n\";\n\t\t\t\t\telse\n\t\t\t\t\t\tformat = \"%d\\n\";\n\t\t\t\t\t\n\t\t\t\t\tfprintf(stdout, format, intval);\n\t\t\t\t\tbreak;\n\t\t\t\tcase STRING:\n\t\t\t\t\tfprintf(stdout, \"%s\\n\", buf);\n\t\t\t\t\tbreak;\n\t\t\t\tcase MAC:\n\t\t\t\t\tmy_ether_ntoa(buf, buf + 6);\n\t\t\t\t\tfprintf(stdout, \"%s\\n\", buf + 6);\n\t\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t} else { /* SET */\n\t\tset = 1;\n\t\tswitch(cmd->param & PARAM_TYPE) {\n\t\t\tcase INT:\n\t\t\t\tintval = strtoul(arg, &end, 0);\n\t\t\t\tif (end && !(*end)) {\n\t\t\t\t\tmemcpy(buf, &intval, sizeof(intval));\n\t\t\t\t} else {\n\t\t\t\t\tfprintf(stderr, \"%s: Invalid argument\\n\", cmd->name);\n\t\t\t\t\treturn -1;\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase STRING:\n\t\t\t\tstrncpy(buf, arg, BUFSIZE);\n\t\t\t\tbuf[BUFSIZE - 1] = 0;\n\t\t\t\tbreak;\n\t\t\tcase MAC:\n\t\t\t\tptr = ether_aton(arg);\n\t\t\t\tif (!ptr) {\n\t\t\t\t\tfprintf(stderr, \"%s: Invalid mac address '%s'\\n\", cmd->name, arg);\n\t\t\t\t\treturn -1;\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t}\n\n\t\tret = cmd->handler(cmd->param | SET, (void *) &cmd->data, ptr);\n\t}\n\t\n\tif ((debug > 0) && (ret != 0)) \n\t\tfprintf(stderr, \"Command '%s %s' failed: %d\\n\", (set == 1 ? \"set\" : \"get\"), cmd->name, ret);\n\t\n\treturn ret;\n}\n\nstatic struct wlc_call *find_cmd(char *name)\n{\n\tint found = 0, i = 0;\n\n\twhile (!found && (i < wlc_calls_size)) {\n\t\tif (strcmp(name, wlc_calls[i].name) == 0)\n\t\t\tfound = 1;\n\t\telse\n\t\t\ti++;\n\t}\n\n\treturn (struct wlc_call *) (found ? &wlc_calls[i] : NULL);\n}\n\nint main(int argc, char **argv)\n{\n\tstatic char buf[BUFSIZE];\n\tchar *s, *s2;\n\tchar *cmd = argv[0];\n\tstruct wlc_call *call;\n\tint ret = 0;\n\n\tif (argc < 2)\n\t\tusage(argv[0]);\n\n\tfor(interface[2] = '0'; (interface[2] < '3') && (wl_probe(interface) != 0); interface[2]++);\n\tif (interface[2] == '3') {\n\t\tfprintf(stderr, \"No Broadcom wl interface found!\\n\");\n\t\treturn -1;\n\t}\n\n\targv++;\n\targc--;\n\twhile ((argc > 0) && (argv[0] != NULL)) {\n\t\tif ((call = find_cmd(argv[0])) == NULL) {\n\t\t\tfprintf(stderr, \"Invalid command: %s\\n\\n\", argv[0]);\n\t\t\tusage(cmd);\n\t\t}\n\t\tif ((argc > 1) && (!(call->param & NOARG))) {\n\t\t\tret = do_command(call, argv[1]);\n\t\t\targv += 2;\n\t\t\targc -= 2;\n\t\t} else {\n\t\t\tret = do_command(call, NULL);\n\t\t\targv++;\n\t\t\targc--;\n\t\t}\n\t}\n\n\twhile (fromstdin && !feof(stdin)) {\n\t\t*buf = 0;\n\t\tfgets(buf, BUFSIZE - 1, stdin);\n\t\t\n\t\tif (*buf == 0)\n\t\t\tcontinue;\n\t\t\n\t\tif ((s = strchr(buf, '\\r')) != NULL)\n\t\t\t*s = 0;\n\t\tif ((s = strchr(buf, '\\n')) != NULL)\n\t\t\t*s = 0;\n\n\t\ts = buf;\n\t\twhile (isspace(*s))\n\t\t\ts++;\n\n\t\tif (!*s)\n\t\t\tcontinue;\n\t\n\t\tif ((s2 = strchr(s, ' ')) != NULL)\n\t\t\t*(s2++) = 0;\n\t\t\n\t\twhile (s2 && isspace(*s2))\n\t\t\ts2++;\n\t\t\n\t\tif ((call = find_cmd(s)) == NULL) {\n\t\t\tfprintf(stderr, \"Invalid command: %s\\n\", s);\n\t\t\tret = -1;\n\t\t} else\n\t\t\tret = do_command(call, ((call->param & NOARG) ? NULL : s2));\n\t}\n\n\treturn ret;\n}\n"
  },
  {
    "path": "package/kernel/button-hotplug/Makefile",
    "content": "#\n# Copyright (C) 2008-2010 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\ninclude $(INCLUDE_DIR)/kernel.mk\n\nPKG_NAME:=button-hotplug\nPKG_RELEASE:=3\nPKG_LICENSE:=GPL-2.0\n\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine KernelPackage/button-hotplug\n  SUBMENU:=Other modules\n  TITLE:=Button Hotplug driver\n  DEPENDS:=+kmod-input-core\n  FILES:=$(PKG_BUILD_DIR)/button-hotplug.ko\n  AUTOLOAD:=$(call AutoLoad,30,button-hotplug,1)\n  KCONFIG:=\nendef\n\ndefine KernelPackage/button-hotplug/description\n  Kernel module to generate button uevent-s from input subsystem events.\n  If your device uses GPIO buttons, see gpio-button-hotplug.\nendef\n\nEXTRA_KCONFIG:= \\\n\tCONFIG_BUTTON_HOTPLUG=m\n\nEXTRA_CFLAGS:= \\\n\t$(patsubst CONFIG_%, -DCONFIG_%=1, $(patsubst %=m,%,$(filter %=m,$(EXTRA_KCONFIG)))) \\\n\t$(patsubst CONFIG_%, -DCONFIG_%=1, $(patsubst %=y,%,$(filter %=y,$(EXTRA_KCONFIG)))) \\\n\nMAKE_OPTS:= \\\n\t$(KERNEL_MAKE_FLAGS) \\\n\tM=\"$(PKG_BUILD_DIR)\" \\\n\tEXTRA_CFLAGS=\"$(EXTRA_CFLAGS)\" \\\n\t$(EXTRA_KCONFIG)\n\ndefine Build/Compile\n\t$(MAKE) -C \"$(LINUX_DIR)\" \\\n\t\t$(MAKE_OPTS) \\\n\t\tmodules\nendef\n\n$(eval $(call KernelPackage,button-hotplug))\n"
  },
  {
    "path": "package/kernel/button-hotplug/src/Kconfig",
    "content": "config BUTTON_HOTPLUG\n\ttristate \"Button Hotplug driver\"\n"
  },
  {
    "path": "package/kernel/button-hotplug/src/Makefile",
    "content": "obj-${CONFIG_BUTTON_HOTPLUG}\t+= button-hotplug.o"
  },
  {
    "path": "package/kernel/button-hotplug/src/button-hotplug.c",
    "content": "/*\n *  Button Hotplug driver\n *\n *  Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>\n *\n *  Based on the diag.c - GPIO interface driver for Broadcom boards\n *    Copyright (C) 2006 Mike Baker <mbm@openwrt.org>,\n *    Copyright (C) 2006-2007 Felix Fietkau <nbd@nbd.name>\n *    Copyright (C) 2008 Andy Boyett <agb@openwrt.org>\n *\n *  This program is free software; you can redistribute it and/or modify it\n *  under the terms of the GNU General Public License version 2 as published\n *  by the Free Software Foundation.\n */\n\n#include <linux/module.h>\n#include <linux/version.h>\n#include <linux/kmod.h>\n#include <linux/input.h>\n\n#include <linux/workqueue.h>\n#include <linux/skbuff.h>\n#include <linux/netlink.h>\n#include <linux/kobject.h>\n\n#define DRV_NAME\t\"button-hotplug\"\n#define DRV_VERSION\t\"0.4.1\"\n#define DRV_DESC\t\"Button Hotplug driver\"\n\n#define BH_SKB_SIZE\t2048\n\n#define PFX\tDRV_NAME \": \"\n\n#undef BH_DEBUG\n\n#ifdef BH_DEBUG\n#define BH_DBG(fmt, args...) printk(KERN_DEBUG \"%s: \" fmt, DRV_NAME, ##args )\n#else\n#define BH_DBG(fmt, args...) do {} while (0)\n#endif\n\n#define BH_ERR(fmt, args...) printk(KERN_ERR \"%s: \" fmt, DRV_NAME, ##args )\n\n#ifndef BIT_MASK\n#define BIT_MASK(nr)            (1UL << ((nr) % BITS_PER_LONG))\n#endif\n\nstruct bh_priv {\n\tunsigned long\t\t*seen;\n\tstruct input_handle\thandle;\n};\n\nstruct bh_event {\n\tconst char\t\t*name;\n\tchar\t\t\t*action;\n\tunsigned long\t\tseen;\n\n\tstruct sk_buff\t\t*skb;\n\tstruct work_struct\twork;\n};\n\nstruct bh_map {\n\tunsigned int\tcode;\n\tconst char\t*name;\n};\n\nextern u64 uevent_next_seqnum(void);\n\n#define BH_MAP(_code, _name)\t\t\\\n\t{\t\t\t\t\\\n\t\t.code = (_code),\t\\\n\t\t.name = (_name),\t\\\n\t}\n\nstatic struct bh_map button_map[] = {\n\tBH_MAP(BTN_0,\t\t\"BTN_0\"),\n\tBH_MAP(BTN_1,\t\t\"BTN_1\"),\n\tBH_MAP(BTN_2,\t\t\"BTN_2\"),\n\tBH_MAP(BTN_3,\t\t\"BTN_3\"),\n\tBH_MAP(BTN_4,\t\t\"BTN_4\"),\n\tBH_MAP(BTN_5,\t\t\"BTN_5\"),\n\tBH_MAP(BTN_6,\t\t\"BTN_6\"),\n\tBH_MAP(BTN_7,\t\t\"BTN_7\"),\n\tBH_MAP(BTN_8,\t\t\"BTN_8\"),\n\tBH_MAP(BTN_9,\t\t\"BTN_9\"),\n\tBH_MAP(KEY_RESTART,\t\"reset\"),\n\tBH_MAP(KEY_POWER,\t\"power\"),\n\tBH_MAP(KEY_POWER2,\t\"reboot\"),\n\tBH_MAP(KEY_RFKILL,\t\"rfkill\"),\n\tBH_MAP(KEY_WPS_BUTTON,\t\"wps\"),\n\tBH_MAP(KEY_WIMAX,\t\"wwan\"),\n};\n\n/* -------------------------------------------------------------------------*/\n\nstatic int bh_event_add_var(struct bh_event *event, int argv,\n\t\tconst char *format, ...)\n{\n\tstatic char buf[128];\n\tchar *s;\n\tva_list args;\n\tint len;\n\n\tif (argv)\n\t\treturn 0;\n\n\tva_start(args, format);\n\tlen = vsnprintf(buf, sizeof(buf), format, args);\n\tva_end(args);\n\n\tif (len >= sizeof(buf)) {\n\t\tBH_ERR(\"buffer size too small\\n\");\n\t\tWARN_ON(1);\n\t\treturn -ENOMEM;\n\t}\n\n\ts = skb_put(event->skb, len + 1);\n\tstrcpy(s, buf);\n\n\tBH_DBG(\"added variable '%s'\\n\", s);\n\n\treturn 0;\n}\n\nstatic int button_hotplug_fill_event(struct bh_event *event)\n{\n\tint ret;\n\n\tret = bh_event_add_var(event, 0, \"HOME=%s\", \"/\");\n\tif (ret)\n\t\treturn ret;\n\n\tret = bh_event_add_var(event, 0, \"PATH=%s\",\n\t\t\t\t\t\"/sbin:/bin:/usr/sbin:/usr/bin\");\n\tif (ret)\n\t\treturn ret;\n\n\tret = bh_event_add_var(event, 0, \"SUBSYSTEM=%s\", \"button\");\n\tif (ret)\n\t\treturn ret;\n\n\tret = bh_event_add_var(event, 0, \"ACTION=%s\", event->action);\n\tif (ret)\n\t\treturn ret;\n\n\tret = bh_event_add_var(event, 0, \"BUTTON=%s\", event->name);\n\tif (ret)\n\t\treturn ret;\n\n\tret = bh_event_add_var(event, 0, \"SEEN=%ld\", event->seen);\n\tif (ret)\n\t\treturn ret;\n\n\tret = bh_event_add_var(event, 0, \"SEQNUM=%llu\", uevent_next_seqnum());\n\n\treturn ret;\n}\n\nstatic void button_hotplug_work(struct work_struct *work)\n{\n\tstruct bh_event *event = container_of(work, struct bh_event, work);\n\tint ret = 0;\n\n\tevent->skb = alloc_skb(BH_SKB_SIZE, GFP_KERNEL);\n\tif (!event->skb)\n\t\tgoto out_free_event;\n\n\tret = bh_event_add_var(event, 0, \"%s@\", event->action);\n\tif (ret)\n\t\tgoto out_free_skb;\n\n\tret = button_hotplug_fill_event(event);\n\tif (ret)\n\t\tgoto out_free_skb;\n\n\tNETLINK_CB(event->skb).dst_group = 1;\n\tbroadcast_uevent(event->skb, 0, 1, GFP_KERNEL);\n\n out_free_skb:\n\tif (ret) {\n\t\tBH_ERR(\"work error %d\\n\", ret);\n\t\tkfree_skb(event->skb);\n\t}\n out_free_event:\n\tkfree(event);\n}\n\nstatic int button_hotplug_create_event(const char *name, unsigned long seen,\n\t\tint pressed)\n{\n\tstruct bh_event *event;\n\n\tBH_DBG(\"create event, name=%s, seen=%lu, pressed=%d\\n\",\n\t\tname, seen, pressed);\n\n\tevent = kzalloc(sizeof(*event), GFP_KERNEL);\n\tif (!event)\n\t\treturn -ENOMEM;\n\n\tevent->name = name;\n\tevent->seen = seen;\n\tevent->action = pressed ? \"pressed\" : \"released\";\n\n\tINIT_WORK(&event->work, (void *)(void *)button_hotplug_work);\n\tschedule_work(&event->work);\n\n\treturn 0;\n}\n\n/* -------------------------------------------------------------------------*/\n\nstatic int button_get_index(unsigned int code)\n{\n\tint i;\n\n\tfor (i = 0; i < ARRAY_SIZE(button_map); i++)\n\t\tif (button_map[i].code == code)\n\t\t\treturn i;\n\n\treturn -1;\n}\nstatic void button_hotplug_event(struct input_handle *handle,\n\t\t\t   unsigned int type, unsigned int code, int value)\n{\n\tstruct bh_priv *priv = handle->private;\n\tunsigned long seen = jiffies;\n\tint btn;\n\n\tBH_DBG(\"event type=%u, code=%u, value=%d\\n\", type, code, value);\n\n\tif (type != EV_KEY)\n\t\treturn;\n\n\tbtn = button_get_index(code);\n\tif (btn < 0)\n\t\treturn;\n\n\tbutton_hotplug_create_event(button_map[btn].name,\n\t\t\t(seen - priv->seen[btn]) / HZ, value);\n\tpriv->seen[btn] = seen;\n}\n\nstatic int button_hotplug_connect(struct input_handler *handler,\n\t\tstruct input_dev *dev, const struct input_device_id *id)\n{\n\tstruct bh_priv *priv;\n\tint ret;\n\tint i;\n\n\tfor (i = 0; i < ARRAY_SIZE(button_map); i++)\n\t\tif (test_bit(button_map[i].code, dev->keybit))\n\t\t\tbreak;\n\n\tif (i == ARRAY_SIZE(button_map))\n\t\treturn -ENODEV;\n\n\tpriv = kzalloc(sizeof(*priv) +\n\t\t       (sizeof(unsigned long) * ARRAY_SIZE(button_map)),\n\t\t       GFP_KERNEL);\n\tif (!priv)\n\t\treturn -ENOMEM;\n\n\tpriv->seen = (unsigned long *) &priv[1];\n\tpriv->handle.private = priv;\n\tpriv->handle.dev = dev;\n\tpriv->handle.handler = handler;\n\tpriv->handle.name = DRV_NAME;\n\n\tret = input_register_handle(&priv->handle);\n\tif (ret)\n\t\tgoto err_free_priv;\n\n\tret = input_open_device(&priv->handle);\n\tif (ret)\n\t\tgoto err_unregister_handle;\n\n\tBH_DBG(\"connected to %s\\n\", dev->name);\n\n\treturn 0;\n\n err_unregister_handle:\n\tinput_unregister_handle(&priv->handle);\n\n err_free_priv:\n\tkfree(priv);\n\treturn ret;\n}\n\nstatic void button_hotplug_disconnect(struct input_handle *handle)\n{\n\tstruct bh_priv *priv = handle->private;\n\n\tinput_close_device(handle);\n\tinput_unregister_handle(handle);\n\n\tkfree(priv);\n}\n\nstatic const struct input_device_id button_hotplug_ids[] = {\n\t{\n                .flags = INPUT_DEVICE_ID_MATCH_EVBIT,\n                .evbit = { BIT_MASK(EV_KEY) },\n        },\n\t{\n\t\t/* Terminating entry */\n\t},\n};\n\nMODULE_DEVICE_TABLE(input, button_hotplug_ids);\n\nstatic struct input_handler button_hotplug_handler = {\n\t.event =\tbutton_hotplug_event,\n\t.connect =\tbutton_hotplug_connect,\n\t.disconnect =\tbutton_hotplug_disconnect,\n\t.name =\t\tDRV_NAME,\n\t.id_table =\tbutton_hotplug_ids,\n};\n\n/* -------------------------------------------------------------------------*/\n\nstatic int __init button_hotplug_init(void)\n{\n\tint ret;\n\n\tprintk(KERN_INFO DRV_DESC \" version \" DRV_VERSION \"\\n\");\n\tret = input_register_handler(&button_hotplug_handler);\n\tif (ret)\n\t\tBH_ERR(\"unable to register input handler\\n\");\n\n\treturn ret;\n}\nmodule_init(button_hotplug_init);\n\nstatic void __exit button_hotplug_exit(void)\n{\n\tinput_unregister_handler(&button_hotplug_handler);\n}\nmodule_exit(button_hotplug_exit);\n\nMODULE_DESCRIPTION(DRV_DESC);\nMODULE_VERSION(DRV_VERSION);\nMODULE_AUTHOR(\"Gabor Juhos <juhosg@openwrt.org>\");\nMODULE_LICENSE(\"GPL v2\");\n\n"
  },
  {
    "path": "package/kernel/cryptodev-linux/Makefile",
    "content": "#\n# Copyright (C) 2014 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n# $Id$\n\ninclude $(TOPDIR)/rules.mk\ninclude $(INCLUDE_DIR)/kernel.mk\n\nPKG_NAME:=cryptodev-linux\nPKG_VERSION:=1.12\nPKG_RELEASE:=$(AUTORELEASE)\n\nPKG_SOURCE_URL:=https://codeload.github.com/$(PKG_NAME)/$(PKG_NAME)/tar.gz/$(PKG_NAME)-$(PKG_VERSION)?\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz\nPKG_HASH:=f51c2254749233b1b1d7ec9445158bd709f124f88e1c650fe2faac83c3a81938\nPKG_LICENSE:=GPL-2.0\nPKG_LICENSE_FILES:=COPYING\n\nPKG_MAINTAINER:=Ansuel Smith <ansuelsmth@gmail.com>\n\nPKG_BUILD_DIR:=$(KERNEL_BUILD_DIR)/$(PKG_NAME)-$(PKG_NAME)-$(PKG_VERSION)\n\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine KernelPackage/cryptodev\n  SUBMENU:=Cryptographic API modules\n  TITLE:=Driver for cryptographic acceleration\n  URL:=http://cryptodev-linux.org/\n  VERSION:=$(LINUX_VERSION)+$(PKG_VERSION)-$(BOARD)-$(PKG_RELEASE)\n  DEPENDS:=+kmod-crypto-authenc +kmod-crypto-hash\n  FILES:=$(PKG_BUILD_DIR)/cryptodev.$(LINUX_KMOD_SUFFIX)\n  AUTOLOAD:=$(call AutoLoad,50,cryptodev)\n  MODPARAMS.cryptodev:=cryptodev_verbosity=-1\nendef\n\ndefine KernelPackage/cryptodev/description\n  This is a driver for that allows to use the Linux kernel supported\n  hardware ciphers by user-space applications.\nendef\n\ndefine Build/Configure\nendef\n\ndefine Build/Compile\n\t$(MAKE) -C $(PKG_BUILD_DIR) \\\n\t\t$(KERNEL_MAKE_FLAGS) \\\n\t\tKERNEL_DIR=\"$(LINUX_DIR)\"\nendef\n\ndefine Build/InstallDev\n\t$(INSTALL_DIR) $(STAGING_DIR)/usr/include/crypto\n\t$(CP) $(PKG_BUILD_DIR)/crypto/cryptodev.h $(STAGING_DIR)/usr/include/crypto/\nendef\n\n$(eval $(call KernelPackage,cryptodev))\n"
  },
  {
    "path": "package/kernel/dtc/patches/0001-scripts-dtc-Update-to-version-with-overlays.patch",
    "content": "From 5f84cb93eef9f8a8ff7f49d593893f252744d0fe Mon Sep 17 00:00:00 2001\nFrom: Pantelis Antoniou <pantelis.antoniou@konsulko.com>\nDate: Wed, 26 Aug 2015 18:28:08 +0300\nSubject: [PATCH] scripts/dtc: Update to version with overlays\n\nUpdate to mainline dtc with overlay support\n\nSigned-off-by: Pantelis Antoniou <pantelis.antoniou@konsulko.com>\n---\n checks.c     |  20 +++++-\n dtc-lexer.l  |   5 ++\n dtc-parser.y |  54 ++++++++++++++--\n dtc.c        |  83 ++++++++++++++++++++++--\n dtc.h        |  13 +++-\n livetree.c   | 202 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\n treesource.c |   3 +\n util.c       |   2 +-\n 8 files changed, 367 insertions(+), 15 deletions(-)\n\ndiff --git a/checks.c b/checks.c\nindex 3bf0fa4..af25c2b 100644\n--- a/checks.c\n+++ b/checks.c\n@@ -465,8 +465,12 @@ static void fixup_phandle_references(struct check *c, struct node *dt,\n \n \t\trefnode = get_node_by_ref(dt, m->ref);\n \t\tif (! refnode) {\n-\t\t\tFAIL(c, \"Reference to non-existent node or label \\\"%s\\\"\\n\",\n-\t\t\t     m->ref);\n+\t\t\tif (!source_is_plugin)\n+\t\t\t\tFAIL(c, \"Reference to non-existent node or \"\n+\t\t\t\t\t\t\"label \\\"%s\\\"\\n\", m->ref);\n+\t\t\telse /* mark the entry as unresolved */\n+\t\t\t\t*((cell_t *)(prop->val.val + m->offset)) =\n+\t\t\t\t\tcpu_to_fdt32(0xffffffff);\n \t\t\tcontinue;\n \t\t}\n \n@@ -559,7 +563,7 @@ static void check_reg_format(struct check *c, struct node *dt,\n \tsize_cells = node_size_cells(node->parent);\n \tentrylen = (addr_cells + size_cells) * sizeof(cell_t);\n \n-\tif ((prop->val.len % entrylen) != 0)\n+\tif (!entrylen || (prop->val.len % entrylen) != 0)\n \t\tFAIL(c, \"\\\"reg\\\" property in %s has invalid length (%d bytes) \"\n \t\t     \"(#address-cells == %d, #size-cells == %d)\",\n \t\t     node->fullpath, prop->val.len, addr_cells, size_cells);\n@@ -651,6 +655,15 @@ static void check_obsolete_chosen_interrupt_controller(struct check *c,\n }\n TREE_WARNING(obsolete_chosen_interrupt_controller, NULL);\n \n+static void check_deprecated_plugin_syntax(struct check *c,\n+\t\t\t\t\t   struct node *dt)\n+{\n+\tif (deprecated_plugin_syntax_warning)\n+\t\tFAIL(c, \"Use '/dts-v1/ /plugin/'; syntax. /dts-v1/; /plugin/; \"\n+\t\t\t\t\"is going to be removed in next versions\");\n+}\n+TREE_WARNING(deprecated_plugin_syntax, NULL);\n+\n static struct check *check_table[] = {\n \t&duplicate_node_names, &duplicate_property_names,\n \t&node_name_chars, &node_name_format, &property_name_chars,\n@@ -668,6 +681,7 @@ static struct check *check_table[] = {\n \n \t&avoid_default_addr_size,\n \t&obsolete_chosen_interrupt_controller,\n+\t&deprecated_plugin_syntax,\n \n \t&always_fail,\n };\ndiff --git a/dtc-lexer.l b/dtc-lexer.l\nindex 0ee1caf..dd44ba2 100644\n--- a/dtc-lexer.l\n+++ b/dtc-lexer.l\n@@ -113,6 +113,11 @@ static void lexical_error(const char *fmt, ...);\n \t\t\treturn DT_V1;\n \t\t}\n \n+<*>\"/plugin/\"\t{\n+\t\t\tDPRINT(\"Keyword: /plugin/\\n\");\n+\t\t\treturn DT_PLUGIN;\n+\t\t}\n+\n <*>\"/memreserve/\"\t{\n \t\t\tDPRINT(\"Keyword: /memreserve/\\n\");\n \t\t\tBEGIN_DEFAULT();\ndiff --git a/dtc-parser.y b/dtc-parser.y\nindex ea57e0a..7d9652d 100644\n--- a/dtc-parser.y\n+++ b/dtc-parser.y\n@@ -19,6 +19,7 @@\n  */\n %{\n #include <stdio.h>\n+#include <inttypes.h>\n \n #include \"dtc.h\"\n #include \"srcpos.h\"\n@@ -52,9 +53,11 @@ extern bool treesource_error;\n \tstruct node *nodelist;\n \tstruct reserve_info *re;\n \tuint64_t integer;\n+\tbool is_plugin;\n }\n \n %token DT_V1\n+%token DT_PLUGIN\n %token DT_MEMRESERVE\n %token DT_LSHIFT DT_RSHIFT DT_LE DT_GE DT_EQ DT_NE DT_AND DT_OR\n %token DT_BITS\n@@ -71,6 +74,7 @@ extern bool treesource_error;\n \n %type <data> propdata\n %type <data> propdataprefix\n+%type <is_plugin> plugindecl\n %type <re> memreserve\n %type <re> memreserves\n %type <array> arrayprefix\n@@ -101,10 +105,39 @@ extern bool treesource_error;\n %%\n \n sourcefile:\n-\t  DT_V1 ';' memreserves devicetree\n+\t    basesource\n+\t  | pluginsource\n+\t  ;\n+\n+basesource:\n+\t  DT_V1 ';' plugindecl memreserves devicetree\n+\t\t{\n+\t\t\tsource_is_plugin = $3;\n+\t\t\tif (source_is_plugin)\n+\t\t\t\tdeprecated_plugin_syntax_warning = true;\n+\t\t\tthe_boot_info = build_boot_info($4, $5,\n+\t\t\t\t\t\t\tguess_boot_cpuid($5));\n+\t\t}\n+\t;\n+\n+plugindecl:\n+\t/* empty */\n+\t\t{\n+\t\t\t$$ = false;\n+\t\t}\n+\t| DT_PLUGIN ';'\n+\t\t{\n+\t\t\t$$ = true;\n+\t\t}\n+\t;\n+\n+pluginsource:\n+\tDT_V1 DT_PLUGIN ';' memreserves devicetree\n \t\t{\n-\t\t\tthe_boot_info = build_boot_info($3, $4,\n-\t\t\t\t\t\t\tguess_boot_cpuid($4));\n+\t\t\tsource_is_plugin = true;\n+\t\t\tdeprecated_plugin_syntax_warning = false;\n+\t\t\tthe_boot_info = build_boot_info($4, $5,\n+\t\t\t\t\t\t\tguess_boot_cpuid($5));\n \t\t}\n \t;\n \n@@ -144,10 +177,14 @@ devicetree:\n \t\t{\n \t\t\tstruct node *target = get_node_by_ref($1, $2);\n \n-\t\t\tif (target)\n+\t\t\tif (target) {\n \t\t\t\tmerge_nodes(target, $3);\n-\t\t\telse\n-\t\t\t\tERROR(&@2, \"Label or path %s not found\", $2);\n+\t\t\t} else {\n+\t\t\t\tif (symbol_fixup_support)\n+\t\t\t\t\tadd_orphan_node($1, $3, $2);\n+\t\t\t\telse\n+\t\t\t\t\tERROR(&@2, \"Label or path %s not found\", $2);\n+\t\t\t}\n \t\t\t$$ = $1;\n \t\t}\n \t| devicetree DT_DEL_NODE DT_REF ';'\n@@ -162,6 +199,11 @@ devicetree:\n \n \t\t\t$$ = $1;\n \t\t}\n+\t| /* empty */\n+\t\t{\n+\t\t\t/* build empty node */\n+\t\t\t$$ = name_node(build_node(NULL, NULL), \"\");\n+\t\t}\n \t;\n \n nodedef:\ndiff --git a/dtc.c b/dtc.c\nindex 8c4add6..ee37be9 100644\n--- a/dtc.c\n+++ b/dtc.c\n@@ -18,6 +18,8 @@\n  *                                                                   USA\n  */\n \n+#include <sys/stat.h>\n+\n #include \"dtc.h\"\n #include \"srcpos.h\"\n \n@@ -29,6 +31,8 @@ int reservenum;\t\t/* Number of memory reservation slots */\n int minsize;\t\t/* Minimum blob size */\n int padsize;\t\t/* Additional padding to blob */\n int phandle_format = PHANDLE_BOTH;\t/* Use linux,phandle or phandle properties */\n+int symbol_fixup_support;\n+int auto_label_aliases;\n \n static void fill_fullpaths(struct node *tree, const char *prefix)\n {\n@@ -51,7 +55,7 @@ static void fill_fullpaths(struct node *tree, const char *prefix)\n #define FDT_VERSION(version)\t_FDT_VERSION(version)\n #define _FDT_VERSION(version)\t#version\n static const char usage_synopsis[] = \"dtc [options] <input file>\";\n-static const char usage_short_opts[] = \"qI:O:o:V:d:R:S:p:fb:i:H:sW:E:hv\";\n+static const char usage_short_opts[] = \"qI:O:o:V:d:R:S:p:fb:i:H:sW:E:@Ahv\";\n static struct option const usage_long_opts[] = {\n \t{\"quiet\",            no_argument, NULL, 'q'},\n \t{\"in-format\",         a_argument, NULL, 'I'},\n@@ -69,6 +73,8 @@ static struct option const usage_long_opts[] = {\n \t{\"phandle\",           a_argument, NULL, 'H'},\n \t{\"warning\",           a_argument, NULL, 'W'},\n \t{\"error\",             a_argument, NULL, 'E'},\n+\t{\"symbols\",\t     no_argument, NULL, '@'},\n+\t{\"auto-alias\",       no_argument, NULL, 'A'},\n \t{\"help\",             no_argument, NULL, 'h'},\n \t{\"version\",          no_argument, NULL, 'v'},\n \t{NULL,               no_argument, NULL, 0x0},\n@@ -99,16 +105,63 @@ static const char * const usage_opts_help[] = {\n \t \"\\t\\tboth   - Both \\\"linux,phandle\\\" and \\\"phandle\\\" properties\",\n \t\"\\n\\tEnable/disable warnings (prefix with \\\"no-\\\")\",\n \t\"\\n\\tEnable/disable errors (prefix with \\\"no-\\\")\",\n+\t\"\\n\\tEnable symbols/fixup support\",\n+\t\"\\n\\tEnable auto-alias of labels\",\n \t\"\\n\\tPrint this help and exit\",\n \t\"\\n\\tPrint version and exit\",\n \tNULL,\n };\n \n+static const char *guess_type_by_name(const char *fname, const char *fallback)\n+{\n+\tconst char *s;\n+\n+\ts = strrchr(fname, '.');\n+\tif (s == NULL)\n+\t\treturn fallback;\n+\tif (!strcasecmp(s, \".dts\"))\n+\t\treturn \"dts\";\n+\tif (!strcasecmp(s, \".dtb\"))\n+\t\treturn \"dtb\";\n+\treturn fallback;\n+}\n+\n+static const char *guess_input_format(const char *fname, const char *fallback)\n+{\n+\tstruct stat statbuf;\n+\tuint32_t magic;\n+\tFILE *f;\n+\n+\tif (stat(fname, &statbuf) != 0)\n+\t\treturn fallback;\n+\n+\tif (S_ISDIR(statbuf.st_mode))\n+\t\treturn \"fs\";\n+\n+\tif (!S_ISREG(statbuf.st_mode))\n+\t\treturn fallback;\n+\n+\tf = fopen(fname, \"r\");\n+\tif (f == NULL)\n+\t\treturn fallback;\n+\tif (fread(&magic, 4, 1, f) != 1) {\n+\t\tfclose(f);\n+\t\treturn fallback;\n+\t}\n+\tfclose(f);\n+\n+\tmagic = fdt32_to_cpu(magic);\n+\tif (magic == FDT_MAGIC)\n+\t\treturn \"dtb\";\n+\n+\treturn guess_type_by_name(fname, fallback);\n+}\n+\n int main(int argc, char *argv[])\n {\n \tstruct boot_info *bi;\n-\tconst char *inform = \"dts\";\n-\tconst char *outform = \"dts\";\n+\tconst char *inform = NULL;\n+\tconst char *outform = NULL;\n \tconst char *outname = \"-\";\n \tconst char *depname = NULL;\n \tbool force = false, sort = false;\n@@ -186,7 +239,12 @@ int main(int argc, char *argv[])\n \t\tcase 'E':\n \t\t\tparse_checks_option(false, true, optarg);\n \t\t\tbreak;\n-\n+\t\tcase '@':\n+\t\t\tsymbol_fixup_support = 1;\n+\t\t\tbreak;\n+\t\tcase 'A':\n+\t\t\tauto_label_aliases = 1;\n+\t\t\tbreak;\n \t\tcase 'h':\n \t\t\tusage(NULL);\n \t\tdefault:\n@@ -213,6 +271,17 @@ int main(int argc, char *argv[])\n \t\tfprintf(depfile, \"%s:\", outname);\n \t}\n \n+\tif (inform == NULL)\n+\t\tinform = guess_input_format(arg, \"dts\");\n+\tif (outform == NULL) {\n+\t\toutform = guess_type_by_name(outname, NULL);\n+\t\tif (outform == NULL) {\n+\t\t\tif (streq(inform, \"dts\"))\n+\t\t\t\toutform = \"dtb\";\n+\t\t\telse\n+\t\t\t\toutform = \"dts\";\n+\t\t}\n+\t}\n \tif (streq(inform, \"dts\"))\n \t\tbi = dt_from_source(arg);\n \telse if (streq(inform, \"fs\"))\n@@ -236,6 +305,12 @@ int main(int argc, char *argv[])\n \tif (sort)\n \t\tsort_tree(bi);\n \n+\tif (symbol_fixup_support || auto_label_aliases)\n+\t\tgenerate_label_node(bi->dt, bi->dt);\n+\n+\tif (symbol_fixup_support)\n+\t\tgenerate_fixups_node(bi->dt, bi->dt);\n+\n \tif (streq(outname, \"-\")) {\n \t\toutf = stdout;\n \t} else {\ndiff --git a/dtc.h b/dtc.h\nindex 56212c8..d025111 100644\n--- a/dtc.h\n+++ b/dtc.h\n@@ -20,7 +20,7 @@\n  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307\n  *                                                                   USA\n  */\n-\n+#define _GNU_SOURCE\n #include <stdio.h>\n #include <string.h>\n #include <stdlib.h>\n@@ -54,6 +54,14 @@ extern int reservenum;\t\t/* Number of memory reservation slots */\n extern int minsize;\t\t/* Minimum blob size */\n extern int padsize;\t\t/* Additional padding to blob */\n extern int phandle_format;\t/* Use linux,phandle or phandle properties */\n+extern int symbol_fixup_support;/* enable symbols & fixup support */\n+extern int auto_label_aliases;\t/* auto generate labels -> aliases */\n+\n+/*\n+ * Tree source globals\n+ */\n+extern bool source_is_plugin;\n+extern bool deprecated_plugin_syntax_warning;\n \n #define PHANDLE_LEGACY\t0x1\n #define PHANDLE_EPAPR\t0x2\n@@ -194,6 +202,7 @@ struct node *build_node_delete(void);\n struct node *name_node(struct node *node, char *name);\n struct node *chain_node(struct node *first, struct node *list);\n struct node *merge_nodes(struct node *old_node, struct node *new_node);\n+void add_orphan_node(struct node *old_node, struct node *new_node, char *ref);\n \n void add_property(struct node *node, struct property *prop);\n void delete_property_by_name(struct node *node, char *name);\n@@ -244,6 +253,8 @@ struct boot_info {\n struct boot_info *build_boot_info(struct reserve_info *reservelist,\n \t\t\t\t  struct node *tree, uint32_t boot_cpuid_phys);\n void sort_tree(struct boot_info *bi);\n+void generate_label_node(struct node *node, struct node *dt);\n+void generate_fixups_node(struct node *node, struct node *dt);\n \n /* Checks */\n \ndiff --git a/livetree.c b/livetree.c\nindex e229b84..1ef9fc4 100644\n--- a/livetree.c\n+++ b/livetree.c\n@@ -216,6 +216,34 @@ struct node *merge_nodes(struct node *old_node, struct node *new_node)\n \treturn old_node;\n }\n \n+void add_orphan_node(struct node *dt, struct node *new_node, char *ref)\n+{\n+\tstatic unsigned int next_orphan_fragment = 0;\n+\tstruct node *ovl = xmalloc(sizeof(*ovl));\n+\tstruct property *p;\n+\tstruct data d = empty_data;\n+\tchar *name;\n+\tint ret;\n+\n+\tmemset(ovl, 0, sizeof(*ovl));\n+\n+\td = data_add_marker(d, REF_PHANDLE, ref);\n+\td = data_append_integer(d, 0xffffffff, 32);\n+\n+\tp = build_property(\"target\", d);\n+\tadd_property(ovl, p);\n+\n+\tret = asprintf(&name, \"fragment@%u\",\n+\t\t\tnext_orphan_fragment++);\n+\tif (ret == -1)\n+\t\tdie(\"asprintf() failed\\n\");\n+\tname_node(ovl, name);\n+\tname_node(new_node, \"__overlay__\");\n+\n+\tadd_child(dt, ovl);\n+\tadd_child(ovl, new_node);\n+}\n+\n struct node *chain_node(struct node *first, struct node *list)\n {\n \tassert(first->next_sibling == NULL);\n@@ -709,3 +737,177 @@ void sort_tree(struct boot_info *bi)\n \tsort_reserve_entries(bi);\n \tsort_node(bi->dt);\n }\n+\n+void generate_label_node(struct node *node, struct node *dt)\n+{\n+\tstruct node *c, *an;\n+\tstruct property *p;\n+\tstruct label *l;\n+\tint has_label;\n+\tchar *gen_node_name;\n+\n+\tif (auto_label_aliases)\n+\t\tgen_node_name = \"aliases\";\n+\telse\n+\t\tgen_node_name = \"__symbols__\";\n+\n+\t/* Make sure the label isn't already there */\n+\thas_label = 0;\n+\tfor_each_label(node->labels, l) {\n+\t\thas_label = 1;\n+\t\tbreak;\n+\t}\n+\n+\tif (has_label) {\n+\n+\t\t/* an is the aliases/__symbols__ node */\n+\t\tan = get_subnode(dt, gen_node_name);\n+\t\t/* if no node exists, create it */\n+\t\tif (!an) {\n+\t\t\tan = build_node(NULL, NULL);\n+\t\t\tname_node(an, gen_node_name);\n+\t\t\tadd_child(dt, an);\n+\t\t}\n+\n+\t\t/* now add the label in the node */\n+\t\tfor_each_label(node->labels, l) {\n+\t\t\t/* check whether the label already exists */\n+\t\t\tp = get_property(an, l->label);\n+\t\t\tif (p) {\n+\t\t\t\tfprintf(stderr, \"WARNING: label %s already\"\n+\t\t\t\t\t\" exists in /%s\", l->label,\n+\t\t\t\t\tgen_node_name);\n+\t\t\t\tcontinue;\n+\t\t\t}\n+\n+\t\t\t/* insert it */\n+\t\t\tp = build_property(l->label,\n+\t\t\t\tdata_copy_escape_string(node->fullpath,\n+\t\t\t\t\t\tstrlen(node->fullpath)));\n+\t\t\tadd_property(an, p);\n+\t\t}\n+\n+\t\t/* force allocation of a phandle for this node */\n+\t\tif (symbol_fixup_support)\n+\t\t\t(void)get_node_phandle(dt, node);\n+\t}\n+\n+\tfor_each_child(node, c)\n+\t\tgenerate_label_node(c, dt);\n+}\n+\n+static void add_fixup_entry(struct node *dt, struct node *node,\n+\t\tstruct property *prop, struct marker *m)\n+{\n+\tstruct node *fn;\t/* local fixup node */\n+\tstruct property *p;\n+\tchar *fixups_name = \"__fixups__\";\n+\tstruct data d;\n+\tchar *entry;\n+\tint ret;\n+\n+\t/* fn is the node we're putting entries in */\n+\tfn = get_subnode(dt, fixups_name);\n+\t/* if no node exists, create it */\n+\tif (!fn) {\n+\t\tfn = build_node(NULL, NULL);\n+\t\tname_node(fn, fixups_name);\n+\t\tadd_child(dt, fn);\n+\t}\n+\n+\tret = asprintf(&entry, \"%s:%s:%u\",\n+\t\t\tnode->fullpath, prop->name, m->offset);\n+\tif (ret == -1)\n+\t\tdie(\"asprintf() failed\\n\");\n+\n+\tp = get_property(fn, m->ref);\n+\td = data_append_data(p ? p->val : empty_data, entry, strlen(entry) + 1);\n+\tif (!p)\n+\t\tadd_property(fn, build_property(m->ref, d));\n+\telse\n+\t\tp->val = d;\n+}\n+\n+static void add_local_fixup_entry(struct node *dt, struct node *node,\n+\t\tstruct property *prop, struct marker *m,\n+\t\tstruct node *refnode)\n+{\n+\tstruct node *lfn, *wn, *nwn;\t/* local fixup node, walk node, new */\n+\tstruct property *p;\n+\tstruct data d;\n+\tchar *local_fixups_name = \"__local_fixups__\";\n+\tchar *s, *e, *comp;\n+\tint len;\n+\n+\t/* fn is the node we're putting entries in */\n+\tlfn = get_subnode(dt, local_fixups_name);\n+\t/* if no node exists, create it */\n+\tif (!lfn) {\n+\t\tlfn = build_node(NULL, NULL);\n+\t\tname_node(lfn, local_fixups_name);\n+\t\tadd_child(dt, lfn);\n+\t}\n+\n+\t/* walk the path components creating nodes if they don't exist */\n+\tcomp = NULL;\n+\t/* start skipping the first / */\n+\ts = node->fullpath + 1;\n+\twn = lfn;\n+\twhile (*s) {\n+\t\t/* retrieve path component */\n+\t\te = strchr(s, '/');\n+\t\tif (e == NULL)\n+\t\t\te = s + strlen(s);\n+\t\tlen = e - s;\n+\t\tcomp = xrealloc(comp, len + 1);\n+\t\tmemcpy(comp, s, len);\n+\t\tcomp[len] = '\\0';\n+\n+\t\t/* if no node exists, create it */\n+\t\tnwn = get_subnode(wn, comp);\n+\t\tif (!nwn) {\n+\t\t\tnwn = build_node(NULL, NULL);\n+\t\t\tname_node(nwn, strdup(comp));\n+\t\t\tadd_child(wn, nwn);\n+\t\t}\n+\t\twn = nwn;\n+\n+\t\t/* last path component */\n+\t\tif (!*e)\n+\t\t\tbreak;\n+\n+\t\t/* next path component */\n+\t\ts = e + 1;\n+\t}\n+\tfree(comp);\n+\n+\tp = get_property(wn, prop->name);\n+\td = data_append_cell(p ? p->val : empty_data, (cell_t)m->offset);\n+\tif (!p)\n+\t\tadd_property(wn, build_property(prop->name, d));\n+\telse\n+\t\tp->val = d;\n+}\n+\n+void generate_fixups_node(struct node *node, struct node *dt)\n+{\n+\tstruct node *c;\n+\tstruct property *prop;\n+\tstruct marker *m;\n+\tstruct node *refnode;\n+\n+\tfor_each_property(node, prop) {\n+\t\tm = prop->val.markers;\n+\t\tfor_each_marker_of_type(m, REF_PHANDLE) {\n+\t\t\trefnode = get_node_by_ref(dt, m->ref);\n+\t\t\tif (!refnode)\n+\t\t\t\tadd_fixup_entry(dt, node, prop, m);\n+\t\t\telse\n+\t\t\t\tadd_local_fixup_entry(dt, node, prop, m,\n+\t\t\t\t\t\trefnode);\n+\t\t}\n+\t}\n+\n+\tfor_each_child(node, c)\n+\t\tgenerate_fixups_node(c, dt);\n+}\ndiff --git a/treesource.c b/treesource.c\nindex a55d1d1..e1d6657 100644\n--- a/treesource.c\n+++ b/treesource.c\n@@ -28,6 +28,9 @@ extern YYLTYPE yylloc;\n struct boot_info *the_boot_info;\n bool treesource_error;\n \n+bool source_is_plugin;\n+bool deprecated_plugin_syntax_warning;\n+\n struct boot_info *dt_from_source(const char *fname)\n {\n \tthe_boot_info = NULL;\ndiff --git a/util.c b/util.c\nindex 9d65226..cbb945b 100644\n--- a/util.c\n+++ b/util.c\n@@ -349,7 +349,6 @@ int utilfdt_decode_type(const char *fmt, int *type, int *size)\n void utilfdt_print_data(const char *data, int len)\n {\n \tint i;\n-\tconst char *p = data;\n \tconst char *s;\n \n \t/* no data, don't print */\n@@ -376,6 +375,7 @@ void utilfdt_print_data(const char *data, int len)\n \t\t\t       i < (len - 1) ? \" \" : \"\");\n \t\tprintf(\">\");\n \t} else {\n+\t\tconst unsigned char *p = (const unsigned char *)data;\n \t\tprintf(\" = [\");\n \t\tfor (i = 0; i < len; i++)\n \t\t\tprintf(\"%02x%s\", *p++, i < len - 1 ? \" \" : \"\");\n-- \n2.7.0\n\n"
  },
  {
    "path": "package/kernel/gpio-button-hotplug/Makefile",
    "content": "#\n# Copyright (C) 2008-2012 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\ninclude $(INCLUDE_DIR)/kernel.mk\n\nPKG_NAME:=gpio-button-hotplug\nPKG_RELEASE:=3\nPKG_LICENSE:=GPL-2.0\n\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine KernelPackage/gpio-button-hotplug\n  SUBMENU:=Other modules\n  TITLE:=Simple GPIO Button Hotplug driver\n  FILES:=$(PKG_BUILD_DIR)/gpio-button-hotplug.ko\n  AUTOLOAD:=$(call AutoLoad,30,gpio-button-hotplug,1)\n  KCONFIG:=\nendef\n\ndefine KernelPackage/gpio-button-hotplug/description\n This is a replacement for the following in-kernel drivers:\n 1) gpio_keys (KEYBOARD_GPIO)\n 2) gpio_keys_polled (KEYBOARD_GPIO_POLLED)\n\n Instead of generating input events (like in-kernel drivers do) it generates\n uevent-s and broadcasts them. This allows disabling input subsystem which is\n an overkill for OpenWrt simple needs.\nendef\n\nMAKE_OPTS:= \\\n\t$(KERNEL_MAKE_FLAGS) \\\n\tM=\"$(PKG_BUILD_DIR)\"\n\ndefine Build/Compile\n\t$(MAKE) -C \"$(LINUX_DIR)\" \\\n\t\t$(MAKE_OPTS) \\\n\t\tmodules\nendef\n\n$(eval $(call KernelPackage,gpio-button-hotplug))\n"
  },
  {
    "path": "package/kernel/gpio-button-hotplug/src/Makefile",
    "content": "obj-m += gpio-button-hotplug.o\n"
  },
  {
    "path": "package/kernel/gpio-button-hotplug/src/gpio-button-hotplug.c",
    "content": "/*\n *  GPIO Button Hotplug driver\n *\n *  Copyright (C) 2012 Felix Fietkau <nbd@nbd.name>\n *  Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>\n *\n *  Based on the diag.c - GPIO interface driver for Broadcom boards\n *    Copyright (C) 2006 Mike Baker <mbm@openwrt.org>,\n *    Copyright (C) 2006-2007 Felix Fietkau <nbd@nbd.name>\n *    Copyright (C) 2008 Andy Boyett <agb@openwrt.org>\n *\n *  This program is free software; you can redistribute it and/or modify it\n *  under the terms of the GNU General Public License version 2 as published\n *  by the Free Software Foundation.\n */\n\n#include <linux/module.h>\n#include <linux/version.h>\n#include <linux/kmod.h>\n\n#include <linux/workqueue.h>\n#include <linux/skbuff.h>\n#include <linux/netlink.h>\n#include <linux/kobject.h>\n#include <linux/input.h>\n#include <linux/interrupt.h>\n#include <linux/platform_device.h>\n#include <linux/of_gpio.h>\n#include <linux/of_irq.h>\n#include <linux/gpio_keys.h>\n#include <linux/gpio/consumer.h>\n\n#define BH_SKB_SIZE\t2048\n\n#define DRV_NAME\t\"gpio-keys\"\n#define PFX\tDRV_NAME \": \"\n\nstruct bh_event {\n\tconst char\t\t*name;\n\tunsigned int\t\ttype;\n\tchar\t\t\t*action;\n\tunsigned long\t\tseen;\n\n\tstruct sk_buff\t\t*skb;\n\tstruct work_struct\twork;\n};\n\nstruct bh_map {\n\tunsigned int\tcode;\n\tconst char\t*name;\n};\n\nstruct gpio_keys_button_data {\n\tstruct delayed_work work;\n\tunsigned long seen;\n\tint map_entry;\n\tint last_state;\n\tint count;\n\tint threshold;\n\tint can_sleep;\n\tint irq;\n\tunsigned int software_debounce;\n\tstruct gpio_desc *gpiod;\n\tconst struct gpio_keys_button *b;\n};\n\nextern u64 uevent_next_seqnum(void);\n\n#define BH_MAP(_code, _name)\t\t\\\n\t{\t\t\t\t\\\n\t\t.code = (_code),\t\\\n\t\t.name = (_name),\t\\\n\t}\n\nstatic struct bh_map button_map[] = {\n\tBH_MAP(BTN_0,\t\t\t\"BTN_0\"),\n\tBH_MAP(BTN_1,\t\t\t\"BTN_1\"),\n\tBH_MAP(BTN_2,\t\t\t\"BTN_2\"),\n\tBH_MAP(BTN_3,\t\t\t\"BTN_3\"),\n\tBH_MAP(BTN_4,\t\t\t\"BTN_4\"),\n\tBH_MAP(BTN_5,\t\t\t\"BTN_5\"),\n\tBH_MAP(BTN_6,\t\t\t\"BTN_6\"),\n\tBH_MAP(BTN_7,\t\t\t\"BTN_7\"),\n\tBH_MAP(BTN_8,\t\t\t\"BTN_8\"),\n\tBH_MAP(BTN_9,\t\t\t\"BTN_9\"),\n\tBH_MAP(KEY_BRIGHTNESS_ZERO,\t\"brightness_zero\"),\n\tBH_MAP(KEY_CONFIG,\t\t\"config\"),\n\tBH_MAP(KEY_COPY,\t\t\"copy\"),\n\tBH_MAP(KEY_EJECTCD,\t\t\"eject\"),\n\tBH_MAP(KEY_HELP,\t\t\"help\"),\n\tBH_MAP(KEY_LIGHTS_TOGGLE,\t\"lights_toggle\"),\n\tBH_MAP(KEY_PHONE,\t\t\"phone\"),\n\tBH_MAP(KEY_POWER,\t\t\"power\"),\n\tBH_MAP(KEY_POWER2,\t\t\"reboot\"),\n\tBH_MAP(KEY_RESTART,\t\t\"reset\"),\n\tBH_MAP(KEY_RFKILL,\t\t\"rfkill\"),\n\tBH_MAP(KEY_VIDEO,\t\t\"video\"),\n\tBH_MAP(KEY_VOLUMEDOWN,\t\t\"volume_down\"),\n\tBH_MAP(KEY_VOLUMEUP,\t\t\"volume_up\"),\n\tBH_MAP(KEY_WIMAX,\t\t\"wwan\"),\n\tBH_MAP(KEY_WLAN,\t\t\"wlan\"),\n\tBH_MAP(KEY_WPS_BUTTON,\t\t\"wps\"),\n};\n\n/* -------------------------------------------------------------------------*/\n\nstatic __printf(3, 4)\nint bh_event_add_var(struct bh_event *event, int argv, const char *format, ...)\n{\n\tchar buf[128];\n\tchar *s;\n\tva_list args;\n\tint len;\n\n\tif (argv)\n\t\treturn 0;\n\n\tva_start(args, format);\n\tlen = vsnprintf(buf, sizeof(buf), format, args);\n\tva_end(args);\n\n\tif (len >= sizeof(buf)) {\n\t\tWARN(1, \"buffer size too small\");\n\t\treturn -ENOMEM;\n\t}\n\n\ts = skb_put(event->skb, len + 1);\n\tstrcpy(s, buf);\n\n\tpr_debug(PFX \"added variable '%s'\\n\", s);\n\n\treturn 0;\n}\n\nstatic int button_hotplug_fill_event(struct bh_event *event)\n{\n\tint ret;\n\n\tret = bh_event_add_var(event, 0, \"HOME=%s\", \"/\");\n\tif (ret)\n\t\treturn ret;\n\n\tret = bh_event_add_var(event, 0, \"PATH=%s\",\n\t\t\t\t\t\"/sbin:/bin:/usr/sbin:/usr/bin\");\n\tif (ret)\n\t\treturn ret;\n\n\tret = bh_event_add_var(event, 0, \"SUBSYSTEM=%s\", \"button\");\n\tif (ret)\n\t\treturn ret;\n\n\tret = bh_event_add_var(event, 0, \"ACTION=%s\", event->action);\n\tif (ret)\n\t\treturn ret;\n\n\tret = bh_event_add_var(event, 0, \"BUTTON=%s\", event->name);\n\tif (ret)\n\t\treturn ret;\n\n\tif (event->type == EV_SW) {\n\t\tret = bh_event_add_var(event, 0, \"TYPE=%s\", \"switch\");\n\t\tif (ret)\n\t\t\treturn ret;\n\t}\n\n\tret = bh_event_add_var(event, 0, \"SEEN=%ld\", event->seen);\n\tif (ret)\n\t\treturn ret;\n\n\tret = bh_event_add_var(event, 0, \"SEQNUM=%llu\", uevent_next_seqnum());\n\n\treturn ret;\n}\n\nstatic void button_hotplug_work(struct work_struct *work)\n{\n\tstruct bh_event *event = container_of(work, struct bh_event, work);\n\tint ret = 0;\n\n\tevent->skb = alloc_skb(BH_SKB_SIZE, GFP_KERNEL);\n\tif (!event->skb)\n\t\tgoto out_free_event;\n\n\tret = bh_event_add_var(event, 0, \"%s@\", event->action);\n\tif (ret)\n\t\tgoto out_free_skb;\n\n\tret = button_hotplug_fill_event(event);\n\tif (ret)\n\t\tgoto out_free_skb;\n\n\tNETLINK_CB(event->skb).dst_group = 1;\n\tbroadcast_uevent(event->skb, 0, 1, GFP_KERNEL);\n\n out_free_skb:\n\tif (ret) {\n\t\tpr_err(PFX \"work error %d\\n\", ret);\n\t\tkfree_skb(event->skb);\n\t}\n out_free_event:\n\tkfree(event);\n}\n\nstatic int button_hotplug_create_event(const char *name, unsigned int type,\n\t\tunsigned long seen, int pressed)\n{\n\tstruct bh_event *event;\n\n\tpr_debug(PFX \"create event, name=%s, seen=%lu, pressed=%d\\n\",\n\t\t name, seen, pressed);\n\n\tevent = kzalloc(sizeof(*event), GFP_KERNEL);\n\tif (!event)\n\t\treturn -ENOMEM;\n\n\tevent->name = name;\n\tevent->type = type;\n\tevent->seen = seen;\n\tevent->action = pressed ? \"pressed\" : \"released\";\n\n\tINIT_WORK(&event->work, (void *)(void *)button_hotplug_work);\n\tschedule_work(&event->work);\n\n\treturn 0;\n}\n\n/* -------------------------------------------------------------------------*/\n\nstatic int button_get_index(unsigned int code)\n{\n\tint i;\n\n\tfor (i = 0; i < ARRAY_SIZE(button_map); i++)\n\t\tif (button_map[i].code == code)\n\t\t\treturn i;\n\n\treturn -1;\n}\n\nstatic int gpio_button_get_value(struct gpio_keys_button_data *bdata)\n{\n\tint val;\n\n\tif (bdata->can_sleep)\n\t\tval = !!gpiod_get_value_cansleep(bdata->gpiod);\n\telse\n\t\tval = !!gpiod_get_value(bdata->gpiod);\n\n\treturn val;\n}\n\nstatic void gpio_keys_handle_button(struct gpio_keys_button_data *bdata)\n{\n\tunsigned int type = bdata->b->type ?: EV_KEY;\n\tint state = gpio_button_get_value(bdata);\n\tunsigned long seen = jiffies;\n\n\tpr_debug(PFX \"event type=%u, code=%u, pressed=%d\\n\",\n\t\t type, bdata->b->code, state);\n\n\t/* is this the initialization state? */\n\tif (bdata->last_state == -1) {\n\t\t/*\n\t\t * Don't advertise unpressed buttons on initialization.\n\t\t * Just save their state and continue otherwise this\n\t\t * can cause OpenWrt to enter failsafe.\n\t\t */\n\t\tif (type == EV_KEY && state == 0)\n\t\t\tgoto set_state;\n\t\t/*\n\t\t * But we are very interested in pressed buttons and\n\t\t * initial switch state. These will be reported to\n\t\t * userland.\n\t\t */\n\t} else if (bdata->last_state == state) {\n\t\t/* reset asserted counter (only relevant for polled keys) */\n\t\tbdata->count = 0;\n\t\treturn;\n\t}\n\n\tif (bdata->count < bdata->threshold) {\n\t\tbdata->count++;\n\t\treturn;\n\t}\n\n\tif (bdata->seen == 0)\n\t\tbdata->seen = seen;\n\n\tbutton_hotplug_create_event(button_map[bdata->map_entry].name, type,\n\t\t\t\t    (seen - bdata->seen) / HZ, state);\n\tbdata->seen = seen;\n\nset_state:\n\tbdata->last_state = state;\n\tbdata->count = 0;\n}\n\nstruct gpio_keys_button_dev {\n\tint polled;\n\tstruct delayed_work work;\n\n\tstruct device *dev;\n\tstruct gpio_keys_platform_data *pdata;\n\tstruct gpio_keys_button_data data[0];\n};\n\nstatic void gpio_keys_polled_queue_work(struct gpio_keys_button_dev *bdev)\n{\n\tstruct gpio_keys_platform_data *pdata = bdev->pdata;\n\tunsigned long delay = msecs_to_jiffies(pdata->poll_interval);\n\n\tif (delay >= HZ)\n\t\tdelay = round_jiffies_relative(delay);\n\tschedule_delayed_work(&bdev->work, delay);\n}\n\nstatic void gpio_keys_polled_poll(struct work_struct *work)\n{\n\tstruct gpio_keys_button_dev *bdev =\n\t\tcontainer_of(work, struct gpio_keys_button_dev, work.work);\n\tint i;\n\n\tfor (i = 0; i < bdev->pdata->nbuttons; i++) {\n\t\tstruct gpio_keys_button_data *bdata = &bdev->data[i];\n\n\t\tif (bdata->gpiod)\n\t\t\tgpio_keys_handle_button(bdata);\n\t}\n\tgpio_keys_polled_queue_work(bdev);\n}\n\nstatic void gpio_keys_polled_close(struct gpio_keys_button_dev *bdev)\n{\n\tstruct gpio_keys_platform_data *pdata = bdev->pdata;\n\n\tcancel_delayed_work_sync(&bdev->work);\n\n\tif (pdata->disable)\n\t\tpdata->disable(bdev->dev);\n}\n\nstatic void gpio_keys_irq_work_func(struct work_struct *work)\n{\n\tstruct gpio_keys_button_data *bdata = container_of(work,\n\t\tstruct gpio_keys_button_data, work.work);\n\n\tgpio_keys_handle_button(bdata);\n}\n\nstatic irqreturn_t button_handle_irq(int irq, void *_bdata)\n{\n\tstruct gpio_keys_button_data *bdata =\n\t\t(struct gpio_keys_button_data *) _bdata;\n\n\tmod_delayed_work(system_wq, &bdata->work,\n\t\t\t msecs_to_jiffies(bdata->software_debounce));\n\n\treturn IRQ_HANDLED;\n}\n\n#ifdef CONFIG_OF\nstatic struct gpio_keys_platform_data *\ngpio_keys_get_devtree_pdata(struct device *dev)\n{\n\tstruct device_node *node, *pp;\n\tstruct gpio_keys_platform_data *pdata;\n\tstruct gpio_keys_button *button;\n\tint nbuttons;\n\tint i = 0;\n\n\tnode = dev->of_node;\n\tif (!node)\n\t\treturn NULL;\n\n\tnbuttons = of_get_child_count(node);\n\tif (nbuttons == 0)\n\t\treturn ERR_PTR(-EINVAL);\n\n\tpdata = devm_kzalloc(dev, sizeof(*pdata) + nbuttons * (sizeof *button),\n\t\tGFP_KERNEL);\n\tif (!pdata)\n\t\treturn ERR_PTR(-ENOMEM);\n\n\tpdata->buttons = (struct gpio_keys_button *)(pdata + 1);\n\tpdata->nbuttons = nbuttons;\n\n\tpdata->rep = !!of_get_property(node, \"autorepeat\", NULL);\n\tof_property_read_u32(node, \"poll-interval\", &pdata->poll_interval);\n\n\tfor_each_child_of_node(node, pp) {\n\t\tbutton = (struct gpio_keys_button *)(&pdata->buttons[i++]);\n\n\t\tif (of_property_read_u32(pp, \"linux,code\", &button->code)) {\n\t\t\tdev_err(dev, \"Button node '%s' without keycode\\n\",\n\t\t\t\tpp->full_name);\n\t\t\tof_node_put(pp);\n\t\t\treturn ERR_PTR(-EINVAL);\n\t\t}\n\n\t\tbutton->desc = of_get_property(pp, \"label\", NULL);\n\n\t\tif (of_property_read_u32(pp, \"linux,input-type\", &button->type))\n\t\t\tbutton->type = EV_KEY;\n\n\t\tbutton->wakeup = !!of_get_property(pp, \"gpio-key,wakeup\", NULL);\n\n\t\tif (of_property_read_u32(pp, \"debounce-interval\",\n\t\t\t\t\t&button->debounce_interval))\n\t\t\tbutton->debounce_interval = 5;\n\n\t\tbutton->irq = irq_of_parse_and_map(pp, 0);\n\t\tbutton->gpio = -ENOENT; /* mark this as device-tree */\n\t}\n\n\treturn pdata;\n}\n\nstatic struct of_device_id gpio_keys_of_match[] = {\n\t{ .compatible = \"gpio-keys\", },\n\t{ },\n};\nMODULE_DEVICE_TABLE(of, gpio_keys_of_match);\n\nstatic struct of_device_id gpio_keys_polled_of_match[] = {\n\t{ .compatible = \"gpio-keys-polled\", },\n\t{ },\n};\nMODULE_DEVICE_TABLE(of, gpio_keys_polled_of_match);\n\n#else\n\nstatic inline struct gpio_keys_platform_data *\ngpio_keys_get_devtree_pdata(struct device *dev)\n{\n\treturn NULL;\n}\n#endif\n\nstatic int gpio_keys_button_probe(struct platform_device *pdev,\n\t\tstruct gpio_keys_button_dev **_bdev, int polled)\n{\n\tstruct device *dev = &pdev->dev;\n\tstruct gpio_keys_platform_data *pdata = dev_get_platdata(dev);\n\tstruct gpio_keys_button_dev *bdev;\n\tstruct gpio_keys_button *buttons;\n\tstruct device_node *prev = NULL;\n\tint error = 0;\n\tint i;\n\n\tif (!pdata) {\n\t\tpdata = gpio_keys_get_devtree_pdata(dev);\n\t\tif (IS_ERR(pdata))\n\t\t\treturn PTR_ERR(pdata);\n\t\tif (!pdata) {\n\t\t\tdev_err(dev, \"missing platform data\\n\");\n\t\t\treturn -EINVAL;\n\t\t}\n\t}\n\n\tif (polled && !pdata->poll_interval) {\n\t\tdev_err(dev, \"missing poll_interval value\\n\");\n\t\treturn -EINVAL;\n\t}\n\n\tbuttons = devm_kzalloc(dev, pdata->nbuttons * sizeof(struct gpio_keys_button),\n\t\t       GFP_KERNEL);\n\tif (!buttons) {\n\t\tdev_err(dev, \"no memory for button data\\n\");\n\t\treturn -ENOMEM;\n\t}\n\tmemcpy(buttons, pdata->buttons, pdata->nbuttons * sizeof(struct gpio_keys_button));\n\n\tbdev = devm_kzalloc(dev, sizeof(struct gpio_keys_button_dev) +\n\t\t       pdata->nbuttons * sizeof(struct gpio_keys_button_data),\n\t\t       GFP_KERNEL);\n\tif (!bdev) {\n\t\tdev_err(dev, \"no memory for private data\\n\");\n\t\treturn -ENOMEM;\n\t}\n\n\tbdev->polled = polled;\n\n\tfor (i = 0; i < pdata->nbuttons; i++) {\n\t\tstruct gpio_keys_button *button = &buttons[i];\n\t\tstruct gpio_keys_button_data *bdata = &bdev->data[i];\n\t\tconst char *desc = button->desc ? button->desc : DRV_NAME;\n\n\t\tif (button->wakeup) {\n\t\t\tdev_err(dev, \"does not support wakeup\\n\");\n\t\t\terror = -EINVAL;\n\t\t\tgoto out;\n\t\t}\n\n\t\tbdata->map_entry = button_get_index(button->code);\n\t\tif (bdata->map_entry < 0) {\n\t\t\tdev_err(dev, \"does not support key code:%u\\n\",\n\t\t\t\tbutton->code);\n\t\t\terror = -EINVAL;\n\t\t\tgoto out;\n\t\t}\n\n\t\tif (!(button->type == 0 || button->type == EV_KEY ||\n\t\t      button->type == EV_SW)) {\n\t\t\tdev_err(dev, \"only supports buttons or switches\\n\");\n\t\t\terror = -EINVAL;\n\t\t\tgoto out;\n\t\t}\n\n\t\tif (gpio_is_valid(button->gpio)) {\n\t\t\t/* legacy platform data... but is it the lookup table? */\n\t\t\tbdata->gpiod = devm_gpiod_get_index(dev, desc, i,\n\t\t\t\t\t\t\t    GPIOD_IN);\n\t\t\tif (IS_ERR(bdata->gpiod)) {\n\t\t\t\t/* or the legacy (button->gpio is good) way? */\n\t\t\t\terror = devm_gpio_request_one(dev,\n\t\t\t\t\tbutton->gpio, GPIOF_IN | (\n\t\t\t\t\tbutton->active_low ? GPIOF_ACTIVE_LOW :\n\t\t\t\t\t0), desc);\n\t\t\t\tif (error) {\n\t\t\t\t\tif (error != -EPROBE_DEFER) {\n\t\t\t\t\t\tdev_err(dev, \"unable to claim gpio %d, err=%d\\n\",\n\t\t\t\t\t\t\tbutton->gpio, error);\n\t\t\t\t\t}\n\t\t\t\t\tgoto out;\n\t\t\t\t}\n\n\t\t\t\tbdata->gpiod = gpio_to_desc(button->gpio);\n\t\t\t}\n\t\t} else {\n\t\t\t/* Device-tree */\n\t\t\tstruct device_node *child =\n\t\t\t\tof_get_next_child(dev->of_node, prev);\n\n\t\t\tbdata->gpiod = devm_gpiod_get_from_of_node(dev,\n\t\t\t\tchild, \"gpios\", 0, GPIOD_IN, desc);\n\n\t\t\tprev = child;\n\t\t}\n\n\t\tif (IS_ERR_OR_NULL(bdata->gpiod)) {\n\t\t\terror = IS_ERR(bdata->gpiod) ? PTR_ERR(bdata->gpiod) :\n\t\t\t\t-EINVAL;\n\t\t\tgoto out;\n\t\t}\n\n\t\tbdata->can_sleep = gpiod_cansleep(bdata->gpiod);\n\t\tbdata->last_state = -1; /* Unknown state on boot */\n\n\t\tif (bdev->polled) {\n\t\t\tbdata->threshold = DIV_ROUND_UP(button->debounce_interval,\n\t\t\t\t\t\t\tpdata->poll_interval);\n\t\t} else {\n\t\t\t/* bdata->threshold = 0; already initialized */\n\n\t\t\tif (button->debounce_interval) {\n\t\t\t\terror = gpiod_set_debounce(bdata->gpiod,\n\t\t\t\t\tbutton->debounce_interval * 1000);\n\t\t\t\t/*\n\t\t\t\t * use timer if gpiolib doesn't provide\n\t\t\t\t * debounce.\n\t\t\t\t */\n\t\t\t\tif (error < 0) {\n\t\t\t\t\tbdata->software_debounce =\n\t\t\t\t\t\tbutton->debounce_interval;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n\t\tbdata->b = &pdata->buttons[i];\n\t}\n\n\tbdev->dev = &pdev->dev;\n\tbdev->pdata = pdata;\n\tplatform_set_drvdata(pdev, bdev);\n\n\t*_bdev = bdev;\n\terror = 0;\n\nout:\n\tof_node_put(prev);\n\treturn error;\n}\n\nstatic int gpio_keys_probe(struct platform_device *pdev)\n{\n\tstruct gpio_keys_platform_data *pdata;\n\tstruct gpio_keys_button_dev *bdev;\n\tint ret, i;\n\n\tret = gpio_keys_button_probe(pdev, &bdev, 0);\n\tif (ret)\n\t\treturn ret;\n\n\tpdata = bdev->pdata;\n\tfor (i = 0; i < pdata->nbuttons; i++) {\n\t\tconst struct gpio_keys_button *button = &pdata->buttons[i];\n\t\tstruct gpio_keys_button_data *bdata = &bdev->data[i];\n\t\tunsigned long irqflags = IRQF_ONESHOT;\n\n\t\tINIT_DELAYED_WORK(&bdata->work, gpio_keys_irq_work_func);\n\n\t\tif (!button->irq) {\n\t\t\tbdata->irq = gpiod_to_irq(bdata->gpiod);\n\t\t\tif (bdata->irq < 0) {\n\t\t\t\tdev_err(&pdev->dev, \"failed to get irq for gpio:%d\\n\",\n\t\t\t\t\tbutton->gpio);\n\t\t\t\tcontinue;\n\t\t\t}\n\n\t\t\tirqflags |= IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING;\n\t\t} else {\n\t\t\tbdata->irq = button->irq;\n\t\t}\n\n\t\tschedule_delayed_work(&bdata->work,\n\t\t\t\t      msecs_to_jiffies(bdata->software_debounce));\n\n\t\tret = devm_request_threaded_irq(&pdev->dev,\n\t\t\tbdata->irq, NULL, button_handle_irq,\n\t\t\tirqflags, dev_name(&pdev->dev), bdata);\n\t\tif (ret < 0) {\n\t\t\tbdata->irq = 0;\n\t\t\tdev_err(&pdev->dev, \"failed to request irq:%d for gpio:%d\\n\",\n\t\t\t\tbdata->irq, button->gpio);\n\t\t\tcontinue;\n\t\t} else {\n\t\t\tdev_dbg(&pdev->dev, \"gpio:%d has irq:%d\\n\",\n\t\t\t\tbutton->gpio, bdata->irq);\n\t\t}\n\t}\n\n\treturn 0;\n}\n\nstatic int gpio_keys_polled_probe(struct platform_device *pdev)\n{\n\tstruct gpio_keys_platform_data *pdata;\n\tstruct gpio_keys_button_dev *bdev;\n\tint ret;\n\n\tret = gpio_keys_button_probe(pdev, &bdev, 1);\n\tif (ret)\n\t\treturn ret;\n\n\tINIT_DELAYED_WORK(&bdev->work, gpio_keys_polled_poll);\n\n\tpdata = bdev->pdata;\n\tif (pdata->enable)\n\t\tpdata->enable(bdev->dev);\n\n\tgpio_keys_polled_queue_work(bdev);\n\n\treturn ret;\n}\n\nstatic void gpio_keys_irq_close(struct gpio_keys_button_dev *bdev)\n{\n\tstruct gpio_keys_platform_data *pdata = bdev->pdata;\n\tsize_t i;\n\n\tfor (i = 0; i < pdata->nbuttons; i++) {\n\t\tstruct gpio_keys_button_data *bdata = &bdev->data[i];\n\n\t\tdisable_irq(bdata->irq);\n\t\tcancel_delayed_work_sync(&bdata->work);\n\t}\n}\n\nstatic int gpio_keys_remove(struct platform_device *pdev)\n{\n\tstruct gpio_keys_button_dev *bdev = platform_get_drvdata(pdev);\n\n\tplatform_set_drvdata(pdev, NULL);\n\n\tif (bdev->polled)\n\t\tgpio_keys_polled_close(bdev);\n\telse\n\t\tgpio_keys_irq_close(bdev);\n\n\treturn 0;\n}\n\nstatic struct platform_driver gpio_keys_driver = {\n\t.probe\t= gpio_keys_probe,\n\t.remove\t= gpio_keys_remove,\n\t.driver\t= {\n\t\t.name\t= \"gpio-keys\",\n\t\t.owner\t= THIS_MODULE,\n\t\t.of_match_table = of_match_ptr(gpio_keys_of_match),\n\t},\n};\n\nstatic struct platform_driver gpio_keys_polled_driver = {\n\t.probe\t= gpio_keys_polled_probe,\n\t.remove\t= gpio_keys_remove,\n\t.driver\t= {\n\t\t.name\t= \"gpio-keys-polled\",\n\t\t.owner\t= THIS_MODULE,\n\t\t.of_match_table = of_match_ptr(gpio_keys_polled_of_match),\n\t},\n};\n\nstatic int __init gpio_button_init(void)\n{\n\tint ret;\n\n\tret = platform_driver_register(&gpio_keys_driver);\n\tif (ret)\n\t\treturn ret;\n\n\tret = platform_driver_register(&gpio_keys_polled_driver);\n\tif (ret)\n\t\tplatform_driver_unregister(&gpio_keys_driver);\n\n\treturn ret;\n}\n\nstatic void __exit gpio_button_exit(void)\n{\n\tplatform_driver_unregister(&gpio_keys_driver);\n\tplatform_driver_unregister(&gpio_keys_polled_driver);\n}\n\nmodule_init(gpio_button_init);\nmodule_exit(gpio_button_exit);\n\nMODULE_AUTHOR(\"Gabor Juhos <juhosg@openwrt.org>\");\nMODULE_AUTHOR(\"Felix Fietkau <nbd@nbd.name>\");\nMODULE_DESCRIPTION(\"Polled GPIO Buttons hotplug driver\");\nMODULE_LICENSE(\"GPL v2\");\nMODULE_ALIAS(\"platform:\" DRV_NAME);\n"
  },
  {
    "path": "package/kernel/gpio-nct5104d/Makefile",
    "content": "#\n# Copyright (C) 2017 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\ninclude $(INCLUDE_DIR)/kernel.mk\n\nPKG_NAME:=gpio-nct5104d\nPKG_RELEASE:=1\n\nPKG_MAINTAINER:=Florian Eckert <Eckert.Florian@googlemail.com>\nPKG_LICENSE:=GPL-2.0\n\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine KernelPackage/gpio-nct5104d\n  SUBMENU:=Other modules\n  TITLE:= GPIO nct5104d support\n  DEPENDS:= @GPIO_SUPPORT @TARGET_x86\n  FILES:=$(PKG_BUILD_DIR)/gpio-nct5104d.ko\n  AUTOLOAD:=$(call AutoLoad,30,gpio-nct5104d,1)\n  KCONFIG:=\nendef\n\ndefine KernelPackage/gpio-nct5104d/description\n  Support for GPIO functionality of NCT5104D super I/O chip.\nendef\n\nEXTRA_KCONFIG:= \\\n\tCONFIG_GPIO_NCT5104D=m\n\nEXTRA_CFLAGS:= \\\n\t$(patsubst CONFIG_%, -DCONFIG_%=1, $(patsubst %=m,%,$(filter %=m,$(EXTRA_KCONFIG)))) \\\n\t$(patsubst CONFIG_%, -DCONFIG_%=1, $(patsubst %=y,%,$(filter %=y,$(EXTRA_KCONFIG)))) \\\n\nMAKE_OPTS:= \\\n\t$(KERNEL_MAKE_FLAGS) \\\n\tM=\"$(PKG_BUILD_DIR)\" \\\n\tEXTRA_CFLAGS=\"$(EXTRA_CFLAGS)\" \\\n\t$(EXTRA_KCONFIG)\n\ndefine Build/Compile\n\t $(MAKE) -C \"$(LINUX_DIR)\" \\\n\t\t$(MAKE_OPTS) \\\n\t\tmodules\nendef\n\n$(eval $(call KernelPackage,gpio-nct5104d))\n"
  },
  {
    "path": "package/kernel/gpio-nct5104d/src/Kconfig",
    "content": "config GPIO_NCT5104D\n        tristate \"NCT5104D GPIO support\"\n        depends on GENERIC_GPIO\n        help\n          Say yes here to support GPIO functionality of NCT5104D super I/O chip\n"
  },
  {
    "path": "package/kernel/gpio-nct5104d/src/Makefile",
    "content": "obj-${CONFIG_GPIO_NCT5104D}    += gpio-nct5104d.o\n"
  },
  {
    "path": "package/kernel/gpio-nct5104d/src/gpio-nct5104d.c",
    "content": "/*\n * GPIO driver for NCT5104D\n *\n * Author: Tasanakorn Phaipool <tasanakorn@gmail.com>\n *\n * This program is free software; you can redistribute it and/or modify\n * it under the terms of the GNU General Public License as published by\n * the Free Software Foundation; either version 2 of the License, or\n * (at your option) any later version.\n */\n\n#include <linux/module.h>\n#include <linux/init.h>\n#include <linux/platform_device.h>\n#include <linux/io.h>\n#include <linux/gpio.h>\n#include <linux/version.h>\n#include <linux/dmi.h>\n#include <linux/string.h>\n\n#define DRVNAME \"gpio-nct5104d\"\n\n/*\n * Super-I/O registers\n */\n#define SIO_LDSEL\t\t0x07\t/* Logical device select */\n#define SIO_CHIPID\t\t0x20\t/* Chaip ID (2 bytes) */\n#define SIO_GPIO_ENABLE\t0x30\t/* GPIO enable */\n#define SIO_GPIO1_MODE\t\t0xE0\t/* GPIO1 Mode OpenDrain/Push-Pull */\n#define SIO_GPIO2_MODE\t\t0xE1\t/* GPIO2 Mode OpenDrain/Push-Pull */\n\n#define SIO_LD_GPIO\t\t0x07\t/* GPIO logical device */\n#define SIO_LD_GPIO_MODE\t0x0F\t/* GPIO mode control device */\n#define SIO_UNLOCK_KEY\t\t0x87\t/* Key to enable Super-I/O */\n#define SIO_LOCK_KEY\t\t0xAA\t/* Key to disable Super-I/O */\n\n#define SIO_NCT5104D_ID\t\t\t\t\t0x1061\t/* Chip ID */\n#define SIO_PCENGINES_APU_NCT5104D_ID1\t0xc452\t/* Chip ID */\n#define SIO_PCENGINES_APU_NCT5104D_ID2\t0xc453\t/* Chip ID */\n\nenum chips { nct5104d };\n\nstatic const char * const nct5104d_names[] = {\n\t\"nct5104d\"\n};\n\nstruct nct5104d_sio {\n\tint addr;\n\tenum chips type;\n};\n\nstruct nct5104d_gpio_bank {\n\tstruct gpio_chip chip;\n\tunsigned int regbase;\n\tstruct nct5104d_gpio_data *data;\n};\n\nstruct nct5104d_gpio_data {\n\tstruct nct5104d_sio *sio;\n\tint nr_bank;\n\tstruct nct5104d_gpio_bank *bank;\n};\n\n/*\n * Super-I/O functions.\n */\n\nstatic inline int superio_inb(int base, int reg)\n{\n\toutb(reg, base);\n\treturn inb(base + 1);\n}\n\nstatic int superio_inw(int base, int reg)\n{\n\tint val;\n\n\toutb(reg++, base);\n\tval = inb(base + 1) << 8;\n\toutb(reg, base);\n\tval |= inb(base + 1);\n\n\treturn val;\n}\n\nstatic inline void superio_outb(int base, int reg, int val)\n{\n\toutb(reg, base);\n\toutb(val, base + 1);\n}\n\nstatic inline int superio_enter(int base)\n{\n\t/* Don't step on other drivers' I/O space by accident. */\n\tif (!request_muxed_region(base, 2, DRVNAME)) {\n\t\tpr_err(DRVNAME \"I/O address 0x%04x already in use\\n\", base);\n\t\treturn -EBUSY;\n\t}\n\n\t/* According to the datasheet the key must be send twice. */\n\toutb(SIO_UNLOCK_KEY, base);\n\toutb(SIO_UNLOCK_KEY, base);\n\n\treturn 0;\n}\n\nstatic inline void superio_select(int base, int ld)\n{\n\toutb(SIO_LDSEL, base);\n\toutb(ld, base + 1);\n}\n\nstatic inline void superio_exit(int base)\n{\n\toutb(SIO_LOCK_KEY, base);\n\trelease_region(base, 2);\n}\n\n/*\n * GPIO chip.\n */\n\nstatic int nct5104d_gpio_direction_in(struct gpio_chip *chip, unsigned offset);\nstatic int nct5104d_gpio_get(struct gpio_chip *chip, unsigned offset);\nstatic int nct5104d_gpio_direction_out(struct gpio_chip *chip,\n\t\t\t\t     unsigned offset, int value);\nstatic void nct5104d_gpio_set(struct gpio_chip *chip, unsigned offset, int value);\n\n#define NCT5104D_GPIO_BANK(_base, _ngpio, _regbase)\t\t\t\\\n\t{\t\t\t\t\t\t\t\t\\\n\t\t.chip = {\t\t\t\t\t\t\\\n\t\t\t.label            = DRVNAME,\t\t\t\\\n\t\t\t.owner            = THIS_MODULE,\t\t\\\n\t\t\t.direction_input  = nct5104d_gpio_direction_in,\t\\\n\t\t\t.get              = nct5104d_gpio_get,\t\t\\\n\t\t\t.direction_output = nct5104d_gpio_direction_out,\t\\\n\t\t\t.set              = nct5104d_gpio_set,\t\t\\\n\t\t\t.base             = _base,\t\t\t\\\n\t\t\t.ngpio            = _ngpio,\t\t\t\\\n\t\t\t.can_sleep        = true,\t\t\t\\\n\t\t},\t\t\t\t\t\t\t\\\n\t\t.regbase = _regbase,\t\t\t\t\t\\\n\t}\n\n#define gpio_dir(base) (base + 0)\n#define gpio_data(base) (base + 1)\n\nstatic struct nct5104d_gpio_bank nct5104d_gpio_bank[] = {\n\tNCT5104D_GPIO_BANK(0 , 8, 0xE0),\n\tNCT5104D_GPIO_BANK(10, 8, 0xE4)\n};\n\nstatic int nct5104d_gpio_direction_in(struct gpio_chip *chip, unsigned offset)\n{\n\tint err;\n\tstruct nct5104d_gpio_bank *bank =\n\t\tcontainer_of(chip, struct nct5104d_gpio_bank, chip);\n\tstruct nct5104d_sio *sio = bank->data->sio;\n\tu8 dir;\n\n\terr = superio_enter(sio->addr);\n\tif (err)\n\t\treturn err;\n\tsuperio_select(sio->addr, SIO_LD_GPIO);\n\n\tdir = superio_inb(sio->addr, gpio_dir(bank->regbase));\n\tdir |= (1 << offset);\n\tsuperio_outb(sio->addr, gpio_dir(bank->regbase), dir);\n\n\tsuperio_exit(sio->addr);\n\n\treturn 0;\n}\n\nstatic int nct5104d_gpio_get(struct gpio_chip *chip, unsigned offset)\n{\n\tint err;\n\tstruct nct5104d_gpio_bank *bank =\n\t\tcontainer_of(chip, struct nct5104d_gpio_bank, chip);\n\tstruct nct5104d_sio *sio = bank->data->sio;\n\tu8 data;\n\n\terr = superio_enter(sio->addr);\n\tif (err)\n\t\treturn err;\n\tsuperio_select(sio->addr, SIO_LD_GPIO);\n\n\tdata = superio_inb(sio->addr, gpio_data(bank->regbase));\n\n\tsuperio_exit(sio->addr);\n\n\treturn !!(data & 1 << offset);\n}\n\nstatic int nct5104d_gpio_direction_out(struct gpio_chip *chip,\n\t\t\t\t     unsigned offset, int value)\n{\n\tint err;\n\tstruct nct5104d_gpio_bank *bank =\n\t\tcontainer_of(chip, struct nct5104d_gpio_bank, chip);\n\tstruct nct5104d_sio *sio = bank->data->sio;\n\tu8 dir, data_out;\n\n\terr = superio_enter(sio->addr);\n\tif (err)\n\t\treturn err;\n\tsuperio_select(sio->addr, SIO_LD_GPIO);\n\n\tdata_out = superio_inb(sio->addr, gpio_data(bank->regbase));\n\tif (value)\n\t\tdata_out |= (1 << offset);\n\telse\n\t\tdata_out &= ~(1 << offset);\n\tsuperio_outb(sio->addr, gpio_data(bank->regbase), data_out);\n\n\tdir = superio_inb(sio->addr, gpio_dir(bank->regbase));\n\tdir &= ~(1 << offset);\n\tsuperio_outb(sio->addr, gpio_dir(bank->regbase), dir);\n\n\tsuperio_exit(sio->addr);\n\n\treturn 0;\n}\n\nstatic void nct5104d_gpio_set(struct gpio_chip *chip, unsigned offset, int value)\n{\n\tint err;\n\tstruct nct5104d_gpio_bank *bank =\n\t\tcontainer_of(chip, struct nct5104d_gpio_bank, chip);\n\tstruct nct5104d_sio *sio = bank->data->sio;\n\tu8 data_out;\n\n\terr = superio_enter(sio->addr);\n\tif (err)\n\t\treturn;\n\tsuperio_select(sio->addr, SIO_LD_GPIO);\n\n\tdata_out = superio_inb(sio->addr, gpio_data(bank->regbase));\n\tif (value)\n\t\tdata_out |= (1 << offset);\n\telse\n\t\tdata_out &= ~(1 << offset);\n\tsuperio_outb(sio->addr, gpio_data(bank->regbase), data_out);\n\n\tsuperio_exit(sio->addr);\n}\n\n/*\n * Platform device and driver.\n */\n\nstatic int nct5104d_gpio_probe(struct platform_device *pdev)\n{\n\tint err;\n\tint i;\n\tstruct nct5104d_sio *sio = pdev->dev.platform_data;\n\tstruct nct5104d_gpio_data *data;\n\n\tdata = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);\n\tif (!data)\n\t\treturn -ENOMEM;\n\n\tswitch (sio->type) {\n\tcase nct5104d:\n\t\tdata->nr_bank = ARRAY_SIZE(nct5104d_gpio_bank);\n\t\tdata->bank = nct5104d_gpio_bank;\n\t\tbreak;\n\tdefault:\n\t\treturn -ENODEV;\n\t}\n\tdata->sio = sio;\n\n\tplatform_set_drvdata(pdev, data);\n\n\t/* For each GPIO bank, register a GPIO chip. */\n\tfor (i = 0; i < data->nr_bank; i++) {\n\t\tstruct nct5104d_gpio_bank *bank = &data->bank[i];\n\n\t\tbank->chip.parent = &pdev->dev;\n\t\tbank->data = data;\n\n\t\terr = gpiochip_add(&bank->chip);\n\t\tif (err) {\n\t\t\tdev_err(&pdev->dev,\n\t\t\t\t\"Failed to register gpiochip %d: %d\\n\",\n\t\t\t\ti, err);\n\t\t\tgoto err_gpiochip;\n\t\t}\n\t}\n\n\treturn 0;\n\nerr_gpiochip:\n\tfor (i = i - 1; i >= 0; i--) {\n\t\tstruct nct5104d_gpio_bank *bank = &data->bank[i];\n\n\t\tgpiochip_remove (&bank->chip);\n\t}\n\n\treturn err;\n}\n\nstatic int nct5104d_gpio_remove(struct platform_device *pdev)\n{\n\tint i;\n\tstruct nct5104d_gpio_data *data = platform_get_drvdata(pdev);\n\n\tfor (i = 0; i < data->nr_bank; i++) {\n\t\tstruct nct5104d_gpio_bank *bank = &data->bank[i];\n\n\t\tgpiochip_remove (&bank->chip);\n\t}\n\n\treturn 0;\n}\n\nstatic int __init nct5104d_find(int addr, struct nct5104d_sio *sio)\n{\n\tint err;\n\tu16 devid;\n\tu8 gpio_cfg;\n\n\terr = superio_enter(addr);\n\tif (err)\n\t\treturn err;\n\n\terr = -ENODEV;\n\n\tdevid = superio_inw(addr, SIO_CHIPID);\n\tswitch (devid) {\n\tcase SIO_NCT5104D_ID:\n\tcase SIO_PCENGINES_APU_NCT5104D_ID1:\n\tcase SIO_PCENGINES_APU_NCT5104D_ID2:\n\t\tsio->type = nct5104d;\n\t\t/* enable GPIO0 and GPIO1 */\n\t\tsuperio_select(addr, SIO_LD_GPIO);\n\t\tgpio_cfg = superio_inb(addr, SIO_GPIO_ENABLE);\n\t\tgpio_cfg |= 0x03;\n\t\tsuperio_outb(addr, SIO_GPIO_ENABLE, gpio_cfg);\n\t\tbreak;\n\tdefault:\n\t\tpr_info(DRVNAME \": Unsupported device 0x%04x\\n\", devid);\n\t\tgoto err;\n\t}\n\tsio->addr = addr;\n\terr = 0;\n\n\tpr_info(DRVNAME \": Found %s at %#x chip id 0x%04x\\n\",\n\t\tnct5104d_names[sio->type],\n\t\t(unsigned int) addr,\n\t\t(int) superio_inw(addr, SIO_CHIPID));\n\n        superio_select(sio->addr, SIO_LD_GPIO_MODE);\n        superio_outb(sio->addr, SIO_GPIO1_MODE, 0x0);\n        superio_outb(sio->addr, SIO_GPIO2_MODE, 0x0);\n\nerr:\n\tsuperio_exit(addr);\n\treturn err;\n}\n\nstatic struct platform_device *nct5104d_gpio_pdev;\n\nstatic int __init\nnct5104d_gpio_device_add(const struct nct5104d_sio *sio)\n{\n\tint err;\n\n\tnct5104d_gpio_pdev = platform_device_alloc(DRVNAME, -1);\n\tif (!nct5104d_gpio_pdev)\n\t\tpr_err(DRVNAME \": Error platform_device_alloc\\n\");\n\tif (!nct5104d_gpio_pdev)\n\t\treturn -ENOMEM;\n\n\terr = platform_device_add_data(nct5104d_gpio_pdev,\n\t\t\t\t       sio, sizeof(*sio));\n\tif (err) {\n\t\tpr_err(DRVNAME \"Platform data allocation failed\\n\");\n\t\tgoto err;\n\t}\n\n\terr = platform_device_add(nct5104d_gpio_pdev);\n\tif (err) {\n\t\tpr_err(DRVNAME \"Device addition failed\\n\");\n\t\tgoto err;\n\t}\n\tpr_info(DRVNAME \": Device added\\n\");\n\treturn 0;\n\nerr:\n\tplatform_device_put(nct5104d_gpio_pdev);\n\n\treturn err;\n}\n\n/*\n */\n\nstatic struct platform_driver nct5104d_gpio_driver = {\n\t.driver = {\n\t\t.owner\t= THIS_MODULE,\n\t\t.name\t= DRVNAME,\n\t},\n\t.probe\t\t= nct5104d_gpio_probe,\n\t.remove\t\t= nct5104d_gpio_remove,\n};\n\nstatic int __init nct5104d_gpio_init(void)\n{\n\tint err;\n\tstruct nct5104d_sio sio;\n\tconst char *board_vendor = dmi_get_system_info(DMI_BOARD_VENDOR);\n\tconst char *board_name = dmi_get_system_info(DMI_BOARD_NAME);\n\n\tif (nct5104d_find(0x2e, &sio) &&\n\t    nct5104d_find(0x4e, &sio))\n\t\treturn -ENODEV;\n\n\terr = platform_driver_register(&nct5104d_gpio_driver);\n\tif (!err) {\n\t\tpr_info(DRVNAME \": platform_driver_register\\n\");\n\t\terr = nct5104d_gpio_device_add(&sio);\n\t\tif (err)\n\t\t\tplatform_driver_unregister(&nct5104d_gpio_driver);\n\t}\n\n\treturn err;\n}\nsubsys_initcall(nct5104d_gpio_init);\n\nstatic void __exit nct5104d_gpio_exit(void)\n{\n\tplatform_device_unregister(nct5104d_gpio_pdev);\n\tplatform_driver_unregister(&nct5104d_gpio_driver);\n}\nmodule_exit(nct5104d_gpio_exit);\n\nMODULE_DESCRIPTION(\"GPIO driver for Super-I/O chips NCT5104D\");\nMODULE_AUTHOR(\"Tasanakorn Phaipool <tasanakorn@gmail.com>\");\nMODULE_LICENSE(\"GPL\");\n"
  },
  {
    "path": "package/kernel/hwmon-gsc/Makefile",
    "content": "include $(TOPDIR)/rules.mk\ninclude $(INCLUDE_DIR)/kernel.mk\n\nPKG_NAME:=hwmon-gsc\nPKG_RELEASE:=1\n\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine KernelPackage/hwmon-gsc\n  SUBMENU:=Hardware Monitoring Support\n  DEPENDS:=@TARGET_imx +kmod-hwmon-core +kmod-i2c-core\n  TITLE:=Driver for the Gateworks System Controller\n  AUTOLOAD:=$(call AutoLoad,60,gsc)\n  FILES:=$(PKG_BUILD_DIR)/gsc.ko\nendef\n\ndefine KernelPackage/hwmon-gsc/description\n  Kernel module for the Gateworks System Controller chips.\nendef\n\ndefine Build/Compile\n\t$(MAKE) -C \"$(LINUX_DIR)\" \\\n\t\t$(KERNEL_MAKE_FLAGS) \\\n\t\tM=\"$(PKG_BUILD_DIR)\" \\\n\t\tEXTRA_CFLAGS=\"$(BUILDFLAGS)\" \\\n\t\tmodules\nendef\n\n$(eval $(call KernelPackage,hwmon-gsc))\n"
  },
  {
    "path": "package/kernel/hwmon-gsc/src/Makefile",
    "content": "obj-m := gsc.o\n"
  },
  {
    "path": "package/kernel/hwmon-gsc/src/gsc.c",
    "content": "/*\n * A hwmon driver for the Gateworks System Controller \n * Copyright (C) 2009 Gateworks Corporation\n *\n * Author: Chris Lang <clang@gateworks.com>\n *\n * This program is free software; you can redistribute it and/or modify\n * it under the terms of the GNU General Public License,\n * as published by the Free Software Foundation - version 2.\n */\n\n#include <linux/module.h>\n#include <linux/i2c.h>\n#include <linux/hwmon.h>\n#include <linux/hwmon-sysfs.h>\n#include <linux/err.h>\n#include <linux/slab.h>\n\n#define DRV_VERSION \"0.2\"\n\nenum chips { gsp };\n\n/* AD7418 registers */\n#define GSP_REG_TEMP_IN\t\t0x00\n#define GSP_REG_VIN\t\t0x02\n#define GSP_REG_3P3\t\t0x05\n#define GSP_REG_BAT\t\t0x08\n#define GSP_REG_5P0\t\t0x0b\n#define GSP_REG_CORE\t\t0x0e\n#define GSP_REG_CPU1\t\t0x11\n#define GSP_REG_CPU2\t\t0x14\n#define GSP_REG_DRAM\t\t0x17\n#define GSP_REG_EXT_BAT\t\t0x1a\n#define GSP_REG_IO1\t\t0x1d\n#define GSP_REG_IO2 \t\t0x20\n#define GSP_REG_PCIE\t\t0x23\n#define GSP_REG_CURRENT\t\t0x26\n#define GSP_FAN_0\t\t0x2C\n#define GSP_FAN_1\t\t0x2E\n#define GSP_FAN_2\t\t0x30\n#define GSP_FAN_3\t\t0x32\n#define GSP_FAN_4\t\t0x34\n#define GSP_FAN_5\t\t0x36\n\nstruct gsp_sensor_info {\n\tconst char* name;\n\tint reg;\n};\n\nstatic const struct gsp_sensor_info gsp_sensors[] = {\n\t{\"temp\", GSP_REG_TEMP_IN},\n\t{\"vin\", GSP_REG_VIN},\n\t{\"3p3\", GSP_REG_3P3},\n\t{\"bat\", GSP_REG_BAT},\n\t{\"5p0\", GSP_REG_5P0},\n\t{\"core\", GSP_REG_CORE},\n\t{\"cpu1\", GSP_REG_CPU1},\n\t{\"cpu2\", GSP_REG_CPU2},\n\t{\"dram\", GSP_REG_DRAM},\n\t{\"ext_bat\", GSP_REG_EXT_BAT},\n\t{\"io1\", GSP_REG_IO1},\n\t{\"io2\", GSP_REG_IO2},\n\t{\"pci2\", GSP_REG_PCIE},\n\t{\"current\", GSP_REG_CURRENT},\n\t{\"fan_point0\", GSP_FAN_0},\n\t{\"fan_point1\", GSP_FAN_1},\n\t{\"fan_point2\", GSP_FAN_2},\n\t{\"fan_point3\", GSP_FAN_3},\n\t{\"fan_point4\", GSP_FAN_4},\n\t{\"fan_point5\", GSP_FAN_5},\n};\n\nstruct gsp_data {\n\tstruct device\t\t*hwmon_dev;\n\tstruct attribute_group\tattrs;\n\tenum chips\t\ttype;\n};\n\nstatic int gsp_probe(struct i2c_client *client,\n\t\t\tconst struct i2c_device_id *id);\nstatic int gsp_remove(struct i2c_client *client);\n\nstatic const struct i2c_device_id gsp_id[] = {\n\t{ \"gsp\", 0 },\n\t{ }\n};\nMODULE_DEVICE_TABLE(i2c, gsp_id);\n\nstatic struct i2c_driver gsp_driver = {\n\t.driver = {\n\t\t.name\t= \"gsp\",\n\t},\n\t.probe\t\t= gsp_probe,\n\t.remove\t\t= gsp_remove,\n\t.id_table\t= gsp_id,\n};\n\n/* All registers are word-sized, except for the configuration registers.\n * AD7418 uses a high-byte first convention. Do NOT use those functions to\n * access the configuration registers CONF and CONF2, as they are byte-sized.\n */\nstatic inline int gsp_read(struct i2c_client *client, u8 reg)\n{\n\tunsigned int adc = 0;\n\tif (reg == GSP_REG_TEMP_IN || reg > GSP_REG_CURRENT)\n\t{\n\t\tadc |= i2c_smbus_read_byte_data(client, reg);\n\t\tadc |= i2c_smbus_read_byte_data(client, reg + 1) << 8;\n\t\treturn adc;\n\t}\n\telse\n\t{\n\t\tadc |= i2c_smbus_read_byte_data(client, reg);\n\t\tadc |= i2c_smbus_read_byte_data(client, reg + 1) << 8;\n\t\tadc |= i2c_smbus_read_byte_data(client, reg + 2) << 16;\n\t\treturn adc;\n\t}\n}\n\nstatic inline int gsp_write(struct i2c_client *client, u8 reg, u16 value)\n{\n\ti2c_smbus_write_byte_data(client, reg, value & 0xff);\n\ti2c_smbus_write_byte_data(client, reg + 1, ((value >> 8) & 0xff));\n\treturn 1;\n}\n\nstatic ssize_t show_adc(struct device *dev, struct device_attribute *devattr,\n\t\t\tchar *buf)\n{\n\tstruct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);\n\tstruct i2c_client *client = to_i2c_client(dev);\n\treturn sprintf(buf, \"%d\\n\", gsp_read(client, gsp_sensors[attr->index].reg));\n}\n\nstatic ssize_t show_label(struct device *dev,\n\t\t\tstruct device_attribute *devattr, char *buf)\n{\n\tstruct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);\n\n\treturn sprintf(buf, \"%s\\n\", gsp_sensors[attr->index].name);\n}\n\nstatic ssize_t store_fan(struct device *dev,\n\t\t\tstruct device_attribute *devattr, const char *buf, size_t count)\n{\n\tu16 val;\n\tstruct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);\n\tstruct i2c_client *client = to_i2c_client(dev);\n\tval = simple_strtoul(buf, NULL, 10);\n\tgsp_write(client, gsp_sensors[attr->index].reg, val);\n\treturn count;\n}\n\nstatic SENSOR_DEVICE_ATTR(temp0_input, S_IRUGO, show_adc, NULL, 0);\nstatic SENSOR_DEVICE_ATTR(temp0_label, S_IRUGO, show_label, NULL, 0);\n\nstatic SENSOR_DEVICE_ATTR(in0_input, S_IRUGO, show_adc, NULL, 1);\nstatic SENSOR_DEVICE_ATTR(in0_label, S_IRUGO, show_label, NULL, 1);\nstatic SENSOR_DEVICE_ATTR(in1_input, S_IRUGO, show_adc, NULL, 2);\nstatic SENSOR_DEVICE_ATTR(in1_label, S_IRUGO, show_label, NULL, 2);\nstatic SENSOR_DEVICE_ATTR(in2_input, S_IRUGO, show_adc, NULL, 3);\nstatic SENSOR_DEVICE_ATTR(in2_label, S_IRUGO, show_label, NULL, 3);\nstatic SENSOR_DEVICE_ATTR(in3_input, S_IRUGO, show_adc, NULL, 4);\nstatic SENSOR_DEVICE_ATTR(in3_label, S_IRUGO, show_label, NULL, 4);\nstatic SENSOR_DEVICE_ATTR(in4_input, S_IRUGO, show_adc, NULL, 5);\nstatic SENSOR_DEVICE_ATTR(in4_label, S_IRUGO, show_label, NULL, 5);\nstatic SENSOR_DEVICE_ATTR(in5_input, S_IRUGO, show_adc, NULL, 6);\nstatic SENSOR_DEVICE_ATTR(in5_label, S_IRUGO, show_label, NULL, 6);\nstatic SENSOR_DEVICE_ATTR(in6_input, S_IRUGO, show_adc, NULL, 7);\nstatic SENSOR_DEVICE_ATTR(in6_label, S_IRUGO, show_label, NULL, 7);\nstatic SENSOR_DEVICE_ATTR(in7_input, S_IRUGO, show_adc, NULL, 8);\nstatic SENSOR_DEVICE_ATTR(in7_label, S_IRUGO, show_label, NULL, 8);\nstatic SENSOR_DEVICE_ATTR(in8_input, S_IRUGO, show_adc, NULL, 9);\nstatic SENSOR_DEVICE_ATTR(in8_label, S_IRUGO, show_label, NULL, 9);\nstatic SENSOR_DEVICE_ATTR(in9_input, S_IRUGO, show_adc, NULL, 10);\nstatic SENSOR_DEVICE_ATTR(in9_label, S_IRUGO, show_label, NULL, 10);\nstatic SENSOR_DEVICE_ATTR(in10_input, S_IRUGO, show_adc, NULL, 11);\nstatic SENSOR_DEVICE_ATTR(in10_label, S_IRUGO, show_label, NULL, 11);\nstatic SENSOR_DEVICE_ATTR(in11_input, S_IRUGO, show_adc, NULL, 12);\nstatic SENSOR_DEVICE_ATTR(in11_label, S_IRUGO, show_label, NULL, 12);\nstatic SENSOR_DEVICE_ATTR(in12_input, S_IRUGO, show_adc, NULL, 13);\nstatic SENSOR_DEVICE_ATTR(in12_label, S_IRUGO, show_label, NULL, 13);\n\nstatic SENSOR_DEVICE_ATTR(fan0_point0, S_IRUGO | S_IWUSR, show_adc, store_fan, 14);\nstatic SENSOR_DEVICE_ATTR(fan0_point1, S_IRUGO | S_IWUSR, show_adc, store_fan, 15);\nstatic SENSOR_DEVICE_ATTR(fan0_point2, S_IRUGO | S_IWUSR, show_adc, store_fan, 16);\nstatic SENSOR_DEVICE_ATTR(fan0_point3, S_IRUGO | S_IWUSR, show_adc, store_fan, 17);\nstatic SENSOR_DEVICE_ATTR(fan0_point4, S_IRUGO | S_IWUSR, show_adc, store_fan, 18);\nstatic SENSOR_DEVICE_ATTR(fan0_point5, S_IRUGO | S_IWUSR, show_adc, store_fan, 19);\n\nstatic struct attribute *gsp_attributes[] = {\n\t&sensor_dev_attr_temp0_input.dev_attr.attr,\n\t&sensor_dev_attr_in0_input.dev_attr.attr,\n\t&sensor_dev_attr_in1_input.dev_attr.attr,\n\t&sensor_dev_attr_in2_input.dev_attr.attr,\n\t&sensor_dev_attr_in3_input.dev_attr.attr,\n\t&sensor_dev_attr_in4_input.dev_attr.attr,\n\t&sensor_dev_attr_in5_input.dev_attr.attr,\n\t&sensor_dev_attr_in6_input.dev_attr.attr,\n\t&sensor_dev_attr_in7_input.dev_attr.attr,\n\t&sensor_dev_attr_in8_input.dev_attr.attr,\n\t&sensor_dev_attr_in9_input.dev_attr.attr,\n\t&sensor_dev_attr_in10_input.dev_attr.attr,\n\t&sensor_dev_attr_in11_input.dev_attr.attr,\n\t&sensor_dev_attr_in12_input.dev_attr.attr,\n\n\t&sensor_dev_attr_temp0_label.dev_attr.attr,\n\t&sensor_dev_attr_in0_label.dev_attr.attr,\n\t&sensor_dev_attr_in1_label.dev_attr.attr,\n\t&sensor_dev_attr_in2_label.dev_attr.attr,\n\t&sensor_dev_attr_in3_label.dev_attr.attr,\n\t&sensor_dev_attr_in4_label.dev_attr.attr,\n\t&sensor_dev_attr_in5_label.dev_attr.attr,\n\t&sensor_dev_attr_in6_label.dev_attr.attr,\n\t&sensor_dev_attr_in7_label.dev_attr.attr,\n\t&sensor_dev_attr_in8_label.dev_attr.attr,\n\t&sensor_dev_attr_in9_label.dev_attr.attr,\n\t&sensor_dev_attr_in10_label.dev_attr.attr,\n\t&sensor_dev_attr_in11_label.dev_attr.attr,\n\t&sensor_dev_attr_in12_label.dev_attr.attr,\n\n\t&sensor_dev_attr_fan0_point0.dev_attr.attr,\n\t&sensor_dev_attr_fan0_point1.dev_attr.attr,\n\t&sensor_dev_attr_fan0_point2.dev_attr.attr,\n\t&sensor_dev_attr_fan0_point3.dev_attr.attr,\n\t&sensor_dev_attr_fan0_point4.dev_attr.attr,\n\t&sensor_dev_attr_fan0_point5.dev_attr.attr,\n\tNULL\n};\n\n\nstatic int gsp_probe(struct i2c_client *client,\n\t\t\t const struct i2c_device_id *id)\n{\n\tstruct i2c_adapter *adapter = client->adapter;\n\tstruct gsp_data *data;\n\tint err;\n\n\tif (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA |\n\t\t\t\t\tI2C_FUNC_SMBUS_WORD_DATA)) {\n\t\terr = -EOPNOTSUPP;\n\t\tgoto exit;\n\t}\n\n\tif (!(data = kzalloc(sizeof(struct gsp_data), GFP_KERNEL))) {\n\t\terr = -ENOMEM;\n\t\tgoto exit;\n\t}\n\n\ti2c_set_clientdata(client, data);\n\n\tdata->type = id->driver_data;\n\n\tswitch (data->type) {\n\tcase 0:\n\t\tdata->attrs.attrs = gsp_attributes;\n\t\tbreak;\n\t}\n\n\tdev_info(&client->dev, \"%s chip found\\n\", client->name);\n\n\t/* Register sysfs hooks */\n\tif ((err = sysfs_create_group(&client->dev.kobj, &data->attrs)))\n\t\tgoto exit_free;\n\n\tdata->hwmon_dev = hwmon_device_register(&client->dev);\n\tif (IS_ERR(data->hwmon_dev)) {\n\t\terr = PTR_ERR(data->hwmon_dev);\n\t\tgoto exit_remove;\n\t}\n\n\treturn 0;\n\nexit_remove:\n\tsysfs_remove_group(&client->dev.kobj, &data->attrs);\nexit_free:\n\tkfree(data);\nexit:\n\treturn err;\n}\n\nstatic int gsp_remove(struct i2c_client *client)\n{\n\tstruct gsp_data *data = i2c_get_clientdata(client);\n\thwmon_device_unregister(data->hwmon_dev);\n\tsysfs_remove_group(&client->dev.kobj, &data->attrs);\n\tkfree(data);\n\treturn 0;\n}\n\nstatic int __init gsp_init(void)\n{\n\treturn i2c_add_driver(&gsp_driver);\n}\n\nstatic void __exit gsp_exit(void)\n{\n\ti2c_del_driver(&gsp_driver);\n}\n\nmodule_init(gsp_init);\nmodule_exit(gsp_exit);\n\nMODULE_AUTHOR(\"Chris Lang <clang@gateworks.com>\");\nMODULE_DESCRIPTION(\"GSC HWMON driver\");\nMODULE_LICENSE(\"GPL\");\nMODULE_VERSION(DRV_VERSION);\n\n"
  },
  {
    "path": "package/kernel/ksmbd/Makefile",
    "content": "include $(TOPDIR)/rules.mk\n\nPKG_NAME:=ksmbd\nPKG_VERSION:=3.4.3\nPKG_RELEASE:=$(AUTORELEASE)\n\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz\nPKG_SOURCE_URL:=https://codeload.github.com/cifsd-team/cifsd/tar.gz/$(PKG_VERSION)?\nPKG_HASH:=a910c55d9e6924775e00504eddd00b49788603af29d0772cb9fb6722c189f628\n\nPKG_LICENSE:=GPL-2.0-or-later\nPKG_LICENSE_FILES:=COPYING\n\ninclude $(INCLUDE_DIR)/kernel.mk\ninclude $(INCLUDE_DIR)/package.mk\n\nTAR_OPTIONS+= --strip-components 1\nTAR_CMD=$(HOST_TAR) -C $(1) $(TAR_OPTIONS)\n\ndefine KernelPackage/fs-ksmbd\n\tSUBMENU:=Filesystems\n\tTITLE:=SMB kernel server support\n\tURL:=https://github.com/cifsd-team/cifsd\n\tFILES:=$(PKG_BUILD_DIR)/ksmbd.ko\n\tDEPENDS:= \\\n\t\t+kmod-nls-base \\\n\t\t+kmod-nls-utf8 \\\n\t\t+kmod-crypto-md4 \\\n\t\t+kmod-crypto-md5 \\\n\t\t+kmod-crypto-hmac \\\n\t\t+kmod-crypto-ecb \\\n\t\t+kmod-crypto-des \\\n\t\t+kmod-crypto-sha256 \\\n\t\t+kmod-crypto-cmac \\\n\t\t+kmod-crypto-sha512 \\\n\t\t+kmod-crypto-aead \\\n\t\t+kmod-crypto-ccm \\\n\t\t+kmod-crypto-gcm \\\n\t\t+kmod-asn1-decoder \\\n\t\t+kmod-oid-registry\nendef\n\n# The last two DEPENDS are hacks in order to get CONFIG_ASN1 and CONFIG_OID_REGISTRY\n# which it seems can't be selected independently. Some bug in either base or upstream.\n\ndefine KernelPackage/fs-ksmbd/description\n  Ksmbd is an In-kernel SMBv(1)2/3 fileserver.\n  It's an implementation of the SMB protocol in kernel space for sharing files and IPC services over network.\nendef\n\ndefine KernelPackage/fs-ksmbd/config\nconfig KSMBD_SMB_INSECURE_SERVER\n\tbool \"Support for insecure SMB1/CIFS and SMB2.0 protocols\"\n\tdepends on PACKAGE_kmod-fs-ksmbd\n\thelp\n\t\tThis enables deprecated insecure protocols dialects: SMB1/CIFS and SMB2.0.\n\tdefault y\nendef\n\nifeq ($(CONFIG_KSMBD_SMB_INSECURE_SERVER),y)\nPKG_EXTRA_KCONFIG:=CONFIG_SMB_INSECURE_SERVER=y\nEXTRA_CFLAGS += -DCONFIG_SMB_INSECURE_SERVER=1\nendif\n\ndefine Build/Compile\n\t$(KERNEL_MAKE) M=\"$(PKG_BUILD_DIR)\" \\\n\tEXTRA_CFLAGS=\"$(EXTRA_CFLAGS)\" \\\n\t$(PKG_EXTRA_KCONFIG) \\\n\tCONFIG_SMB_SERVER=m \\\n\tmodules\nendef\n\n$(eval $(call KernelPackage,fs-ksmbd))\n"
  },
  {
    "path": "package/kernel/ksmbd/patches/01-keep_kmod_metadata.patch",
    "content": "--- a/glob.h\n+++ b/glob.h\n@@ -7,6 +7,8 @@\n #ifndef __KSMBD_GLOB_H\n #define __KSMBD_GLOB_H\n \n+#undef CONFIG_MODULE_STRIPPED\n+\n #include <linux/ctype.h>\n \n #include \"unicode.h\"\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-adsl/Config.in",
    "content": "config LANTIQ_ADSL_DEBUG\n\tbool \"verbose debugging\"\n\tdepends on PACKAGE_kmod-ltq-adsl\n\thelp\n\t  Say Y, if you need ltq-adsl to display debug messages.\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-adsl/Makefile",
    "content": "#\n# Copyright (C) 2011 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\ninclude $(INCLUDE_DIR)/kernel.mk\n\nPKG_NAME:=ltq-adsl\nPKG_VERSION:=3.24.4.4\nPKG_RELEASE:=4\nPKG_SOURCE:=drv_dsl_cpe_api_danube-$(PKG_VERSION).tar.gz\nPKG_BUILD_DIR:=$(KERNEL_BUILD_DIR)/ltq-dsl-$(BUILD_VARIANT)/drv_dsl_cpe_api-$(PKG_VERSION)\nPKG_SOURCE_URL:=@OPENWRT\nPKG_HASH:=eb2ed59715d3bf4e8a1460bbbe2f1660039e0a9f9d72afb1b2b16590094eb33c\nPKG_MAINTAINER:=John Crispin <john@phrozen.org>\n\nPKG_CHECK_FORMAT_SECURITY:=0\nPKG_FIXUP:=autoreconf\n\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine KernelPackage/ltq-adsl-template\n  SECTION:=sys\n  CATEGORY:=Kernel modules\n  SUBMENU:=Network Devices\n  TITLE:=adsl driver for $(1)\n  URL:=http://www.lantiq.com/\n  VARIANT:=$(1)\n  DEPENDS:=@$(2) +kmod-ltq-adsl-$(1)-mei\n  FILES:=$(PKG_BUILD_DIR)/src/drv_dsl_cpe_api.ko\n  AUTOLOAD:=$(call AutoLoad,51,drv_dsl_cpe_api)\nendef\n\nKernelPackage/ltq-adsl-danube=$(call KernelPackage/ltq-adsl-template,danube,(TARGET_lantiq_xway||TARGET_lantiq_xway_legacy))\nKernelPackage/ltq-adsl-ar9=$(call KernelPackage/ltq-adsl-template,ar9,TARGET_lantiq_xway)\nKernelPackage/ltq-adsl-ase=$(call KernelPackage/ltq-adsl-template,ase,TARGET_lantiq_ase)\n\ndefine KernelPackage/ltq-adsl/config\n\tsource \"$(SOURCE)/Config.in\"\nendef\n\nIFX_DSL_MAX_DEVICE=1\nIFX_DSL_LINES_PER_DEVICE=1\nIFX_DSL_CHANNELS_PER_LINE=1\n\nMAKE_FLAGS += \\\n\t$(KERNEL_MAKE_FLAGS)\n\nCONFIGURE_ARGS += --enable-kernel-include=\"$(LINUX_DIR)/include\" \\\n\t--with-max-device=\"$(IFX_DSL_MAX_DEVICE)\" \\\n\t--with-lines-per-device=\"$(IFX_DSL_LINES_PER_DEVICE)\" \\\n\t--with-channels-per-line=\"$(IFX_DSL_CHANNELS_PER_LINE)\" \\\n\t--disable-dsl-delt-static \\\n\t--disable-adsl-led \\\n\t--enable-dsl-ceoc \\\n\t--enable-dsl-pm \\\n\t--enable-dsl-pm-total \\\n\t--enable-dsl-pm-history \\\n\t--enable-dsl-pm-showtime \\\n\t--enable-dsl-pm-channel-counters \\\n\t--enable-dsl-pm-datapath-counters \\\n\t--enable-dsl-pm-line-counters \\\n\t--enable-dsl-pm-channel-thresholds \\\n\t--enable-dsl-pm-datapath-thresholds \\\n\t--enable-dsl-pm-line-thresholds \\\n\t--enable-dsl-pm-optional-parameters \\\n\t--enable-linux-26 \\\n\t--enable-kernelbuild=\"$(LINUX_DIR)\" \\\n\tARCH=$(LINUX_KARCH)\n\nCONFIG_TAG_danube:=DANUBE\nCONFIG_TAG_ase:=AMAZON_SE\nCONFIG_TAG_ar9:=AR9\nCONFIGURE_ARGS += --enable-add-drv-cflags=\"-DMODULE -DCONFIG_$(CONFIG_TAG_$(BUILD_VARIANT))\"\n\nCONFIGURE_ARGS += --enable-danube\n\nifeq ($(CONFIG_LANTIQ_ADSL_DEBUG),y)\nCONFIGURE_ARGS += \\\n\t--enable-debug=yes \\\n\t--enable-debug-prints=yes\nEXTRA_CFLAGS += -DDEBUG\nendif\n\ndefine Build/InstallDev\n\t$(INSTALL_DIR) $(1)/usr/include/adsl\n\t$(CP) $(PKG_BUILD_DIR)/src/include/drv_dsl_cpe_*.h $(1)/usr/include/adsl/\nendef\n\n$(eval $(call KernelPackage,ltq-adsl-danube))\n$(eval $(call KernelPackage,ltq-adsl-ase))\n$(eval $(call KernelPackage,ltq-adsl-ar9))\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-adsl/patches/020-not-leak-cflags.patch",
    "content": "--- a/src/Makefile.am\n+++ b/src/Makefile.am\n@@ -253,10 +253,7 @@ else\n drv_dsl_cpe_api_common_mod_cflags =\n endif\n \n-drv_dsl_cpe_api_common_cflags = -DLINUX -D__LINUX__ -D__KERNEL__ -DEXPORT_SYMTAB \\\n-    -pipe -Wall -Wformat -Wimplicit -Wunused -Wswitch -Wcomment -Winline \\\n-    -Wuninitialized -Wparentheses -Wsign-compare -Wreturn-type \\\n-    -Wstrict-prototypes -Wno-trigraphs -fno-strict-aliasing -fno-common\n+drv_dsl_cpe_api_common_cflags = -DLINUX -D__LINUX__ -D__KERNEL__ -DEXPORT_SYMTAB\n \n if DSL_DBG_MAX_LEVEL_SET\n drv_dsl_cpe_api_common_cflags += -DDSL_DBG_MAX_LEVEL=$(DSL_DBG_MAX_LEVEL_PRE)\n@@ -266,7 +263,7 @@ endif\n drv_dsl_cpe_api_target_cflags = $(ADD_DRV_CFLAGS)\n \n # compile cflags\n-drv_dsl_cpe_api_compile_cflags = $(EXTRA_DRV_CFLAGS)\n+drv_dsl_cpe_api_compile_cflags =\n \n if !KERNEL_2_6\n # the headerfile of linux kernels 2.6.x contain to much arithmetic\n@@ -314,7 +311,7 @@ drv_dsl_cpe_api.ko: $(drv_dsl_cpe_api_SO\n \t@echo -e \"# drv_dsl_cpe_api: Generated to build Linux 2.6.x kernel object\" > $(PWD)/Kbuild\n \t@echo -e \"obj-m := $(subst .ko,.o,$@)\"\t\t\t>> $(PWD)/Kbuild\n \t@echo -e \"$(subst .ko,,$@)-y := $(drv_dsl_cpe_api_OBJS)\"\t>> $(PWD)/Kbuild\n-\t@echo -e \"EXTRA_CFLAGS := $(CFLAGS) -DHAVE_CONFIG_H $(drv_dsl_cpe_api_CFLAGS) $(DSL_DRIVER_INCL_PATH) $(IFXOS_INCLUDE_PATH) -I@abs_srcdir@/include -I$(PWD)/include\"\t>> $(PWD)/Kbuild\n+\t@echo -e \"EXTRA_CFLAGS := -DHAVE_CONFIG_H $(drv_dsl_cpe_api_CFLAGS) $(DSL_DRIVER_INCL_PATH) $(IFXOS_INCLUDE_PATH) -I@abs_srcdir@/include -I$(PWD)/include\"\t>> $(PWD)/Kbuild\n \t$(MAKE) ARCH=@KERNEL_ARCH@ -C @KERNEL_BUILD_PATH@ O=@KERNEL_BUILD_PATH@ M=$(PWD) modules\n \n clean-generic:\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-adsl/patches/100-dsl_compat.patch",
    "content": "--- a/src/include/drv_dsl_cpe_device_danube.h\n+++ b/src/include/drv_dsl_cpe_device_danube.h\n@@ -24,7 +24,7 @@\n    #include \"drv_dsl_cpe_simulator_danube.h\"\n #else\n /* Include for the low level driver interface header file */\n-#include \"asm/ifx/ifx_mei_bsp.h\"\n+#include \"ifxmips_mei_interface.h\"\n #endif /* defined(DSL_CPE_SIMULATOR_DRIVER) && defined(WIN32)*/\n \n #define DSL_MAX_LINE_NUMBER 1\n--- a/src/common/drv_dsl_cpe_os_linux.c\n+++ b/src/common/drv_dsl_cpe_os_linux.c\n@@ -11,6 +11,7 @@\n #ifdef __LINUX__\n \n #define DSL_INTERN\n+#include <linux/device.h>\n \n #include \"drv_dsl_cpe_api.h\"\n #include \"drv_dsl_cpe_api_ioctl.h\"\n@@ -34,9 +35,13 @@ static const char* dsl_cpe_api_version =\n static DSL_ssize_t DSL_DRV_Write(DSL_DRV_file_t *pFile, const DSL_char_t * pBuf,\n                                  DSL_DRV_size_t nSize, DSL_DRV_offset_t * pLoff);\n \n+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,36))\n static DSL_int_t DSL_DRV_Ioctls(DSL_DRV_inode_t * pINode, DSL_DRV_file_t * pFile,\n                          DSL_uint_t nCommand, unsigned long nArg);\n-\n+#else\n+static DSL_int_t DSL_DRV_Ioctls(DSL_DRV_file_t * pFile,\n+                         DSL_uint_t nCommand, unsigned long nArg);\n+#endif\n static int DSL_DRV_Open(DSL_DRV_inode_t * ino, DSL_DRV_file_t * fil);\n \n static int DSL_DRV_Release(DSL_DRV_inode_t * ino, DSL_DRV_file_t * fil);\n@@ -72,7 +77,11 @@ static struct file_operations dslCpeApiO\n    open:    DSL_DRV_Open,\n    release: DSL_DRV_Release,\n    write:   DSL_DRV_Write,\n+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,36))\n    ioctl:   DSL_DRV_Ioctls,\n+#else\n+   unlocked_ioctl:   DSL_DRV_Ioctls,\n+#endif\n    poll:    DSL_DRV_Poll\n };\n #else\n@@ -168,10 +177,17 @@ static DSL_ssize_t DSL_DRV_Write(DSL_DRV\n    \\return  Success or failure.\n    \\ingroup Internal\n */\n+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,36))\n static DSL_int_t DSL_DRV_Ioctls(DSL_DRV_inode_t * pINode,\n    DSL_DRV_file_t * pFile,\n    DSL_uint_t nCommand,\n    unsigned long nArg)\n+#else\n+static DSL_int_t DSL_DRV_Ioctls(\n+   DSL_DRV_file_t * pFile,\n+   DSL_uint_t nCommand,\n+   unsigned long nArg)\n+#endif\n {\n    DSL_int_t nErr=0;\n    DSL_boolean_t bIsInKernel;\n@@ -216,16 +232,7 @@ static DSL_int_t DSL_DRV_Ioctls(DSL_DRV_\n          }\n       }\n    }\n-\n-   if (pINode == DSL_NULL)\n-   {\n-      bIsInKernel = DSL_TRUE;\n-   }\n-   else\n-   {\n-      bIsInKernel = DSL_FALSE;\n-   }\n-\n+   bIsInKernel = DSL_FALSE;\n    if ( (_IOC_TYPE(nCommand) == DSL_IOC_MAGIC_CPE_API) ||\n         (_IOC_TYPE(nCommand) == DSL_IOC_MAGIC_CPE_API_G997) ||\n         (_IOC_TYPE(nCommand) == DSL_IOC_MAGIC_CPE_API_PM) ||\n@@ -828,12 +835,19 @@ DSL_int32_t DSL_DRV_ThreadShutdown(\n \n DSL_uint32_t DSL_DRV_SysTimeGet(DSL_uint32_t nOffset)\n {\n-   struct timeval tv;\n    DSL_uint32_t nTime = 0;\n+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 0, 0))\n+   struct timeval tv;\n \n    memset(&tv, 0, sizeof(tv));\n    do_gettimeofday(&tv);\n    nTime = (DSL_uint32_t)tv.tv_sec;\n+#else\n+   struct timespec64 now;\n+\n+   ktime_get_real_ts64(&now);\n+   nTime = (DSL_uint32_t)now.tv_sec;\n+#endif\n \n    if ( (nOffset == 0) || (nOffset > nTime) )\n    {\n@@ -1058,6 +1072,7 @@ static void DSL_DRV_DebugInit(void)\n /* Entry point of driver */\n int __init DSL_ModuleInit(void)\n {\n+   struct class *dsl_class;\n    DSL_int_t i;\n \n    printk(DSL_DRV_CRLF DSL_DRV_CRLF \"Infineon CPE API Driver version: %s\" DSL_DRV_CRLF,\n@@ -1104,7 +1119,8 @@ int __init DSL_ModuleInit(void)\n    }\n \n    DSL_DRV_DevNodeInit();\n-\n+   dsl_class = class_create(THIS_MODULE, \"dsl_cpe_api\");\n+   device_create(dsl_class, NULL, MKDEV(DRV_DSL_CPE_API_DEV_MAJOR, 0), NULL, \"dsl_cpe_api\");\n    return 0;\n }\n \n--- a/src/include/drv_dsl_cpe_os_linux.h\n+++ b/src/include/drv_dsl_cpe_os_linux.h\n@@ -16,18 +16,18 @@\n    extern \"C\" {\n #endif\n \n-#include <asm/ioctl.h>\n-#include <linux/autoconf.h>\n #include <linux/module.h>\n #include <linux/kernel.h>\n #include <linux/init.h>\n #include <linux/ctype.h>\n #include <linux/version.h>\n #include <linux/spinlock.h>\n+#include <linux/sched.h>\n \n-\n-#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,17))\n-   #include <linux/utsrelease.h>\n+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,33))\n+#include <linux/utsrelease.h>\n+#else\n+#include <generated/utsrelease.h>\n #endif\n \n #include <linux/types.h>\n@@ -39,7 +39,8 @@\n #include <linux/delay.h>\n #include <linux/poll.h>\n #include <asm/uaccess.h>\n-#include <linux/smp_lock.h>\n+//#include <linux/smp_lock.h>\n+#include <asm/ioctl.h>\n \n #ifdef INCLUDE_DSL_CPE_API_IFXOS_SUPPORT\n /** IFXOS includes*/\n--- /dev/null\n+++ b/src/include/ifxmips_mei_interface.h\n@@ -0,0 +1,702 @@\n+/******************************************************************************\n+\n+                               Copyright (c) 2009\n+                            Infineon Technologies AG\n+                     Am Campeon 1-12; 81726 Munich, Germany\n+\n+  For licensing information, see the file 'LICENSE' in the root folder of\n+  this software module.\n+\n+******************************************************************************/\n+\n+#ifndef IFXMIPS_MEI_H\n+#define IFXMIPS_MEI_H\n+\n+//#define CONFIG_AMAZON_SE 1\n+//#define CONFIG_DANUBE 1\n+//#define CONFIG_AR9 1\n+\n+#if !defined(CONFIG_DANUBE) && !defined(CONFIG_AMAZON_SE) && !defined(CONFIG_AR9) && !defined(CONFIG_VR9)\n+#error Platform undefined!!!\n+#endif\n+\n+#ifdef IFX_MEI_BSP\n+/** This is the character datatype. */\n+typedef char            DSL_char_t;\n+/** This is the unsigned 8-bit datatype. */\n+typedef unsigned char   DSL_uint8_t;\n+/** This is the signed 8-bit datatype. */\n+typedef signed char     DSL_int8_t;\n+/** This is the unsigned 16-bit datatype. */\n+typedef unsigned short  DSL_uint16_t;\n+/** This is the signed 16-bit datatype. */\n+typedef signed short    DSL_int16_t;\n+/** This is the unsigned 32-bit datatype. */\n+typedef unsigned long   DSL_uint32_t;\n+/** This is the signed 32-bit datatype. */\n+typedef signed long     DSL_int32_t;\n+/** This is the float datatype. */\n+typedef float           DSL_float_t;\n+/** This is the void datatype. */\n+typedef void            DSL_void_t;\n+/** integer type, width is depending on processor arch */\n+typedef int             DSL_int_t;\n+/** unsigned integer type, width is depending on processor arch */\n+typedef unsigned int    DSL_uint_t;\n+typedef struct file DSL_DRV_file_t;\n+typedef struct inode DSL_DRV_inode_t;\n+\n+/**\n+ *    Defines all possible CMV groups\n+ *    */\n+typedef enum {\n+   DSL_CMV_GROUP_CNTL = 1,\n+   DSL_CMV_GROUP_STAT = 2,\n+   DSL_CMV_GROUP_INFO = 3,\n+   DSL_CMV_GROUP_TEST = 4,\n+   DSL_CMV_GROUP_OPTN = 5,\n+   DSL_CMV_GROUP_RATE = 6,\n+   DSL_CMV_GROUP_PLAM = 7,\n+   DSL_CMV_GROUP_CNFG = 8\n+} DSL_CmvGroup_t;\n+/**\n+ *    Defines all opcode types\n+ *    */\n+typedef enum {\n+   H2D_CMV_READ = 0x00,\n+   H2D_CMV_WRITE = 0x04,\n+   H2D_CMV_INDICATE_REPLY = 0x10,\n+   H2D_ERROR_OPCODE_UNKNOWN =0x20,\n+   H2D_ERROR_CMV_UNKNOWN =0x30,\n+\n+   D2H_CMV_READ_REPLY =0x01,\n+   D2H_CMV_WRITE_REPLY = 0x05,\n+   D2H_CMV_INDICATE = 0x11,\n+   D2H_ERROR_OPCODE_UNKNOWN = 0x21,\n+   D2H_ERROR_CMV_UNKNOWN = 0x31,\n+   D2H_ERROR_CMV_READ_NOT_AVAILABLE = 0x41,\n+   D2H_ERROR_CMV_WRITE_ONLY = 0x51,\n+   D2H_ERROR_CMV_READ_ONLY = 0x61,\n+\n+   H2D_DEBUG_READ_DM = 0x02,\n+   H2D_DEBUG_READ_PM = 0x06,\n+   H2D_DEBUG_WRITE_DM = 0x0a,\n+   H2D_DEBUG_WRITE_PM = 0x0e,\n+\n+   D2H_DEBUG_READ_DM_REPLY = 0x03,\n+   D2H_DEBUG_READ_FM_REPLY = 0x07,\n+   D2H_DEBUG_WRITE_DM_REPLY = 0x0b,\n+   D2H_DEBUG_WRITE_FM_REPLY = 0x0f,\n+   D2H_ERROR_ADDR_UNKNOWN = 0x33,\n+\n+   D2H_AUTONOMOUS_MODEM_READY_MSG = 0xf1\n+} DSL_CmvOpcode_t;\n+\n+/* mutex macros */\n+#define MEI_MUTEX_INIT(id,flag) \\\n+        sema_init(&id,flag)\n+#define MEI_MUTEX_LOCK(id) \\\n+        down_interruptible(&id)\n+#define MEI_MUTEX_UNLOCK(id) \\\n+        up(&id)\n+#define MEI_WAIT(ms) \\\n+        {\\\n+                set_current_state(TASK_INTERRUPTIBLE);\\\n+                schedule_timeout(ms);\\\n+        }\n+#define MEI_INIT_WAKELIST(name,queue) \\\n+        init_waitqueue_head(&queue)\n+\n+/* wait for an event, timeout is measured in ms */\n+#define MEI_WAIT_EVENT_TIMEOUT(ev,timeout)\\\n+        interruptible_sleep_on_timeout(&ev,timeout * HZ / 1000)\n+#define MEI_WAKEUP_EVENT(ev)\\\n+        wake_up_interruptible(&ev)\n+#endif /* IFX_MEI_BSP */\n+\n+/***\tRegister address offsets, relative to MEI_SPACE_ADDRESS ***/\n+#define ME_DX_DATA\t\t\t\t(0x0000)\n+#define\tME_VERSION\t\t\t\t(0x0004)\n+#define\tME_ARC_GP_STAT\t\t\t\t(0x0008)\n+#define ME_DX_STAT\t\t\t\t(0x000C)\n+#define\tME_DX_AD\t\t\t\t(0x0010)\n+#define ME_DX_MWS\t\t\t\t(0x0014)\n+#define\tME_ME2ARC_INT\t\t\t\t(0x0018)\n+#define\tME_ARC2ME_STAT\t\t\t\t(0x001C)\n+#define\tME_ARC2ME_MASK \t\t\t\t(0x0020)\n+#define\tME_DBG_WR_AD\t\t\t\t(0x0024)\n+#define ME_DBG_RD_AD\t\t\t\t(0x0028)\n+#define\tME_DBG_DATA\t\t\t\t(0x002C)\n+#define\tME_DBG_DECODE\t\t\t\t(0x0030)\n+#define ME_CONFIG\t\t\t\t(0x0034)\n+#define\tME_RST_CTRL\t\t\t\t(0x0038)\n+#define\tME_DBG_MASTER\t\t\t\t(0x003C)\n+#define\tME_CLK_CTRL\t\t\t\t(0x0040)\n+#define\tME_BIST_CTRL\t\t\t\t(0x0044)\n+#define\tME_BIST_STAT\t\t\t\t(0x0048)\n+#define ME_XDATA_BASE_SH\t\t\t(0x004c)\n+#define ME_XDATA_BASE\t\t\t\t(0x0050)\n+#define ME_XMEM_BAR_BASE\t\t\t(0x0054)\n+#define ME_XMEM_BAR0\t\t\t\t(0x0054)\n+#define ME_XMEM_BAR1\t\t\t\t(0x0058)\n+#define ME_XMEM_BAR2\t\t\t\t(0x005C)\n+#define ME_XMEM_BAR3\t\t\t\t(0x0060)\n+#define ME_XMEM_BAR4\t\t\t\t(0x0064)\n+#define ME_XMEM_BAR5\t\t\t\t(0x0068)\n+#define ME_XMEM_BAR6\t\t\t\t(0x006C)\n+#define ME_XMEM_BAR7\t\t\t\t(0x0070)\n+#define ME_XMEM_BAR8\t\t\t\t(0x0074)\n+#define ME_XMEM_BAR9\t\t\t\t(0x0078)\n+#define ME_XMEM_BAR10\t\t\t\t(0x007C)\n+#define ME_XMEM_BAR11\t\t\t\t(0x0080)\n+#define ME_XMEM_BAR12\t\t\t\t(0x0084)\n+#define ME_XMEM_BAR13\t\t\t\t(0x0088)\n+#define ME_XMEM_BAR14\t\t\t\t(0x008C)\n+#define ME_XMEM_BAR15\t\t\t\t(0x0090)\n+#define ME_XMEM_BAR16\t\t\t\t(0x0094)\n+\n+#define WHILE_DELAY \t\t20000\n+/*\n+**\tDefine where in ME Processor's memory map the Stratify chip lives\n+*/\n+\n+#define MAXSWAPSIZE      \t(8 * 1024)\t//8k *(32bits)\n+\n+//      Mailboxes\n+#define MSG_LENGTH\t\t16\t// x16 bits\n+#define YES_REPLY      \t \t1\n+#define NO_REPLY         \t0\n+\n+#define CMV_TIMEOUT\t\t1000\t//jiffies\n+\n+//  Block size per BAR\n+#define SDRAM_SEGMENT_SIZE\t(64*1024)\n+// Number of Bar registers\n+#define MAX_BAR_REGISTERS\t(17)\n+\n+#define XDATA_REGISTER\t\t(15)\n+\n+// ARC register addresss\n+#define ARC_STATUS\t\t0x0\n+#define ARC_LP_START\t\t0x2\n+#define ARC_LP_END\t\t0x3\n+#define ARC_DEBUG\t\t0x5\n+#define ARC_INT_MASK\t\t0x10A\n+\n+#define IRAM0_BASE \t\t(0x00000)\n+#define IRAM1_BASE \t\t(0x04000)\n+#if defined(CONFIG_DANUBE)\n+#define BRAM_BASE  \t\t(0x0A000)\n+#elif defined(CONFIG_AMAZON_SE) || defined(CONFIG_AR9) || defined(CONFIG_VR9)\n+#define BRAM_BASE               (0x08000)\n+#endif\n+#define XRAM_BASE\t\t(0x18000)\n+#define YRAM_BASE\t\t(0x1A000)\n+#define EXT_MEM_BASE\t\t(0x80000)\n+#define ARC_GPIO_CTRL\t\t(0xC030)\n+#define ARC_GPIO_DATA\t\t(0xC034)\n+\n+#define IRAM0_SIZE\t\t(16*1024)\n+#define IRAM1_SIZE\t\t(16*1024)\n+#define BRAM_SIZE\t\t(12*1024)\n+#define XRAM_SIZE\t\t(8*1024)\n+#define YRAM_SIZE\t\t(8*1024)\n+#define EXT_MEM_SIZE\t\t(1536*1024)\n+\n+#define ADSL_BASE\t\t(0x20000)\n+#define CRI_BASE\t\t(ADSL_BASE + 0x11F00)\n+#define CRI_CCR0\t\t(CRI_BASE + 0x00)\n+#define CRI_RST\t\t\t(CRI_BASE + 0x04*4)\n+#define ADSL_DILV_BASE \t\t(ADSL_BASE+0x20000)\n+\n+//\n+#define IRAM0_ADDR_BIT_MASK\t0xFFF\n+#define IRAM1_ADDR_BIT_MASK\t0xFFF\n+#define BRAM_ADDR_BIT_MASK\t0xFFF\n+#define RX_DILV_ADDR_BIT_MASK\t0x1FFF\n+\n+/***  Bit definitions ***/\n+#define ARC_AUX_HALT\t\t(1 << 25)\n+#define ARC_DEBUG_HALT\t\t(1 << 1)\n+#define FALSE\t\t\t0\n+#define TRUE\t\t\t1\n+#define BIT0\t\t\t(1<<0)\n+#define BIT1\t\t\t(1<<1)\n+#define BIT2\t\t\t(1<<2)\n+#define BIT3\t\t\t(1<<3)\n+#define BIT4\t\t\t(1<<4)\n+#define BIT5\t\t\t(1<<5)\n+#define BIT6\t\t\t(1<<6)\n+#define BIT7\t\t\t(1<<7)\n+#define BIT8\t\t\t(1<<8)\n+#define BIT9\t\t\t(1<<9)\n+#define BIT10 \t\t\t(1<<10)\n+#define BIT11\t\t\t(1<<11)\n+#define BIT12\t\t\t(1<<12)\n+#define BIT13\t\t\t(1<<13)\n+#define BIT14\t\t\t(1<<14)\n+#define BIT15\t\t\t(1<<15)\n+#define BIT16 \t\t\t(1<<16)\n+#define BIT17\t\t\t(1<<17)\n+#define BIT18\t\t\t(1<<18)\n+#define BIT19\t\t\t(1<<19)\n+#define BIT20\t\t\t(1<<20)\n+#define BIT21\t\t\t(1<<21)\n+#define BIT22\t\t\t(1<<22)\n+#define BIT23\t\t\t(1<<23)\n+#define BIT24\t\t\t(1<<24)\n+#define BIT25\t\t\t(1<<25)\n+#define BIT26\t\t\t(1<<26)\n+#define BIT27\t\t\t(1<<27)\n+#define BIT28\t\t\t(1<<28)\n+#define BIT29\t\t\t(1<<29)\n+#define BIT30\t\t\t(1<<30)\n+#define BIT31\t\t\t(1<<31)\n+\n+// CRI_CCR0 Register definitions\n+#define CLK_2M_MODE_ENABLE\tBIT6\n+#define\tACL_CLK_MODE_ENABLE\tBIT4\n+#define FDF_CLK_MODE_ENABLE\tBIT2\n+#define STM_CLK_MODE_ENABLE\tBIT0\n+\n+// CRI_RST Register definitions\n+#define FDF_SRST\t\tBIT3\n+#define MTE_SRST\t\tBIT2\n+#define FCI_SRST\t\tBIT1\n+#define AAI_SRST\t\tBIT0\n+\n+//      MEI_TO_ARC_INTERRUPT Register definitions\n+#define\tMEI_TO_ARC_INT1\t\tBIT3\n+#define\tMEI_TO_ARC_INT0\t\tBIT2\n+#define MEI_TO_ARC_CS_DONE\tBIT1\t//need to check\n+#define\tMEI_TO_ARC_MSGAV\tBIT0\n+\n+//      ARC_TO_MEI_INTERRUPT Register definitions\n+#define\tARC_TO_MEI_INT1\t\tBIT8\n+#define\tARC_TO_MEI_INT0\t\tBIT7\n+#define\tARC_TO_MEI_CS_REQ\tBIT6\n+#define\tARC_TO_MEI_DBG_DONE\tBIT5\n+#define\tARC_TO_MEI_MSGACK\tBIT4\n+#define\tARC_TO_MEI_NO_ACCESS\tBIT3\n+#define\tARC_TO_MEI_CHECK_AAITX\tBIT2\n+#define\tARC_TO_MEI_CHECK_AAIRX\tBIT1\n+#define\tARC_TO_MEI_MSGAV\tBIT0\n+\n+//      ARC_TO_MEI_INTERRUPT_MASK Register definitions\n+#define\tGP_INT1_EN\t\tBIT8\n+#define\tGP_INT0_EN\t\tBIT7\n+#define\tCS_REQ_EN\t\tBIT6\n+#define\tDBG_DONE_EN\t\tBIT5\n+#define\tMSGACK_EN\t\tBIT4\n+#define\tNO_ACC_EN\t\tBIT3\n+#define\tAAITX_EN\t\tBIT2\n+#define\tAAIRX_EN\t\tBIT1\n+#define\tMSGAV_EN\t\tBIT0\n+\n+#define\tMEI_SOFT_RESET\t\tBIT0\n+\n+#define\tHOST_MSTR\t\tBIT0\n+\n+#define JTAG_MASTER_MODE\t0x0\n+#define MEI_MASTER_MODE\t\tHOST_MSTR\n+\n+//      MEI_DEBUG_DECODE Register definitions\n+#define MEI_DEBUG_DEC_MASK\t(0x3)\n+#define MEI_DEBUG_DEC_AUX_MASK\t(0x0)\n+#define ME_DBG_DECODE_DMP1_MASK\t(0x1)\n+#define MEI_DEBUG_DEC_DMP2_MASK\t(0x2)\n+#define MEI_DEBUG_DEC_CORE_MASK\t(0x3)\n+\n+#define AUX_STATUS\t\t(0x0)\n+#define AUX_ARC_GPIO_CTRL\t(0x10C)\n+#define AUX_ARC_GPIO_DATA\t(0x10D)\n+//      ARC_TO_MEI_MAILBOX[11] is a special location used to indicate\n+//      page swap requests.\n+#if defined(CONFIG_DANUBE)\n+#define OMBOX_BASE      \t0xDF80\n+#define\tARC_TO_MEI_MAILBOX\t0xDFA0\n+#define IMBOX_BASE      \t0xDFC0\n+#define MEI_TO_ARC_MAILBOX\t0xDFD0\n+#elif defined(CONFIG_AMAZON_SE) || defined(CONFIG_AR9) || defined(CONFIG_VR9)\n+#define OMBOX_BASE              0xAF80\n+#define ARC_TO_MEI_MAILBOX      0xAFA0\n+#define IMBOX_BASE              0xAFC0\n+#define MEI_TO_ARC_MAILBOX      0xAFD0\n+#endif\n+\n+#define MEI_TO_ARC_MAILBOXR\t(MEI_TO_ARC_MAILBOX + 0x2C)\n+#define ARC_MEI_MAILBOXR\t(ARC_TO_MEI_MAILBOX + 0x2C)\n+#define OMBOX1  \t\t(OMBOX_BASE+0x4)\n+\n+// Codeswap request messages are indicated by setting BIT31\n+#define OMB_CODESWAP_MESSAGE_MSG_TYPE_MASK\t(0x80000000)\n+\n+// Clear Eoc messages received are indicated by setting BIT17\n+#define OMB_CLEAREOC_INTERRUPT_CODE\t\t(0x00020000)\n+#define OMB_REBOOT_INTERRUPT_CODE               (1 << 18)\n+\n+/*\n+**\tSwap page header\n+*/\n+//      Page must be loaded at boot time if size field has BIT31 set\n+#define BOOT_FLAG\t\t(BIT31)\n+#define BOOT_FLAG_MASK\t\t~BOOT_FLAG\n+\n+#define FREE_RELOAD\t\t1\n+#define FREE_SHOWTIME\t\t2\n+#define FREE_ALL\t\t3\n+\n+// marcos\n+#define\tIFX_MEI_WRITE_REGISTER_L(data,addr)\t*((volatile u32*)(addr)) = (u32)(data)\n+#define IFX_MEI_READ_REGISTER_L(addr) \t(*((volatile u32*)(addr)))\n+#define SET_BIT(reg, mask)\t\t\treg |= (mask)\n+#define CLEAR_BIT(reg, mask)\t\t\treg &= (~mask)\n+#define CLEAR_BITS(reg, mask)\t\t\tCLEAR_BIT(reg, mask)\n+//#define SET_BITS(reg, mask)\t\t\tSET_BIT(reg, mask)\n+#define SET_BITFIELD(reg, mask, off, val)\t{reg &= (~mask); reg |= (val << off);}\n+\n+#define ALIGN_SIZE\t\t\t\t( 1L<<10 )\t//1K size align\n+#define MEM_ALIGN(addr)\t\t\t\t(((addr) + ALIGN_SIZE - 1) & ~ (ALIGN_SIZE -1) )\n+\n+// swap marco\n+#define MEI_HALF_WORD_SWAP(data)\t\t{data = ((data & 0xffff)<<16) + ((data & 0xffff0000)>>16);}\n+#define MEI_BYTE_SWAP(data)\t\t\t{data = ((data & 0xff)<<24) + ((data & 0xff00)<<8)+ ((data & 0xff0000)>>8)+ ((data & 0xff000000)>>24);}\n+\n+\n+#ifdef CONFIG_PROC_FS\n+typedef struct reg_entry\n+{\n+   int *flag;\n+   char name[30];               /* big enough to hold names */\n+   char description[100];       /* big enough to hold description */\n+   unsigned short low_ino;\n+} reg_entry_t;\n+#endif\n+//      Swap page header describes size in 32-bit words, load location, and image offset\n+//      for program and/or data segments\n+typedef struct _arc_swp_page_hdr {\n+\tu32 p_offset;\t\t//Offset bytes of progseg from beginning of image\n+\tu32 p_dest;\t\t//Destination addr of progseg on processor\n+\tu32 p_size;\t\t//Size in 32-bitwords of program segment\n+\tu32 d_offset;\t\t//Offset bytes of dataseg from beginning of image\n+\tu32 d_dest;\t\t//Destination addr of dataseg on processor\n+\tu32 d_size;\t\t//Size in 32-bitwords of data segment\n+} ARC_SWP_PAGE_HDR;\n+\n+/*\n+**\tSwap image header\n+*/\n+#define GET_PROG\t0\t//      Flag used for program mem segment\n+#define GET_DATA\t1\t//      Flag used for data mem segment\n+\n+//      Image header contains size of image, checksum for image, and count of\n+//      page headers. Following that are 'count' page headers followed by\n+//      the code and/or data segments to be loaded\n+typedef struct _arc_img_hdr {\n+\tu32 size;\t\t//      Size of binary image in bytes\n+\tu32 checksum;\t\t//      Checksum for image\n+\tu32 count;\t\t//      Count of swp pages in image\n+\tARC_SWP_PAGE_HDR page[1];\t//      Should be \"count\" pages - '1' to make compiler happy\n+} ARC_IMG_HDR;\n+\n+typedef struct smmu_mem_info {\n+\tint type;\n+\tint boot;\n+\tunsigned long nCopy;\n+\tunsigned long size;\n+\tunsigned char *address;\n+\tunsigned char *org_address;\n+} smmu_mem_info_t;\n+\n+#ifdef __KERNEL__\n+typedef struct ifx_mei_device_private {\n+\tint modem_ready;\n+\tint arcmsgav;\n+\tint cmv_reply;\n+\tint cmv_waiting;\n+\t// Mei to ARC CMV count, reply count, ARC Indicator count\n+\tint modem_ready_cnt;\n+\tint cmv_count;\n+\tint reply_count;\n+\tunsigned long image_size;\n+\tint nBar;\n+\tu16 Recent_indicator[MSG_LENGTH];\n+\n+\tu16 CMV_RxMsg[MSG_LENGTH] __attribute__ ((aligned (4)));\n+\n+\tsmmu_mem_info_t adsl_mem_info[MAX_BAR_REGISTERS];\n+\tARC_IMG_HDR *img_hdr;\n+\t//  to wait for arc cmv reply, sleep on wait_queue_arcmsgav;\n+\twait_queue_head_t wait_queue_arcmsgav;\n+\twait_queue_head_t wait_queue_modemready;\n+\tstruct semaphore mei_cmv_sema;\n+} ifx_mei_device_private_t;\n+#endif\n+typedef struct winhost_message {\n+\tunion {\n+\t\tu16 RxMessage[MSG_LENGTH] __attribute__ ((aligned (4)));\n+\t\tu16 TxMessage[MSG_LENGTH] __attribute__ ((aligned (4)));\n+\t} msg;\n+} DSL_DEV_WinHost_Message_t;\n+/********************************************************************************************************\n+ * DSL CPE API Driver Stack Interface Definitions\n+ * *****************************************************************************************************/\n+/** IOCTL codes for bsp driver */\n+#define DSL_IOC_MEI_BSP_MAGIC\t\t's'\n+\n+#define DSL_FIO_BSP_DSL_START\t\t_IO  (DSL_IOC_MEI_BSP_MAGIC, 0)\n+#define DSL_FIO_BSP_RUN\t\t\t_IO  (DSL_IOC_MEI_BSP_MAGIC, 1)\n+#define DSL_FIO_BSP_FREE_RESOURCE\t_IO  (DSL_IOC_MEI_BSP_MAGIC, 2)\n+#define DSL_FIO_BSP_RESET\t\t_IO  (DSL_IOC_MEI_BSP_MAGIC, 3)\n+#define DSL_FIO_BSP_REBOOT\t\t_IO  (DSL_IOC_MEI_BSP_MAGIC, 4)\n+#define DSL_FIO_BSP_HALT\t\t_IO  (DSL_IOC_MEI_BSP_MAGIC, 5)\n+#define DSL_FIO_BSP_BOOTDOWNLOAD\t_IO  (DSL_IOC_MEI_BSP_MAGIC, 6)\n+#define DSL_FIO_BSP_JTAG_ENABLE\t\t_IO  (DSL_IOC_MEI_BSP_MAGIC, 7)\n+#define DSL_FIO_FREE_RESOURCE\t\t_IO  (DSL_IOC_MEI_BSP_MAGIC, 8)\n+#define DSL_FIO_ARC_MUX_TEST\t\t_IO  (DSL_IOC_MEI_BSP_MAGIC, 9)\n+#define DSL_FIO_BSP_REMOTE\t\t_IOW (DSL_IOC_MEI_BSP_MAGIC, 10, u32)\n+#define DSL_FIO_BSP_GET_BASE_ADDRESS\t_IOR (DSL_IOC_MEI_BSP_MAGIC, 11, u32)\n+#define DSL_FIO_BSP_IS_MODEM_READY\t_IOR (DSL_IOC_MEI_BSP_MAGIC, 12, u32)\n+#define DSL_FIO_BSP_GET_VERSION\t\t_IOR (DSL_IOC_MEI_BSP_MAGIC, 13, DSL_DEV_Version_t)\n+#define DSL_FIO_BSP_CMV_WINHOST\t\t_IOWR(DSL_IOC_MEI_BSP_MAGIC, 14, DSL_DEV_WinHost_Message_t)\n+#define DSL_FIO_BSP_CMV_READ\t\t_IOWR(DSL_IOC_MEI_BSP_MAGIC, 15, DSL_DEV_MeiReg_t)\n+#define DSL_FIO_BSP_CMV_WRITE\t\t_IOW (DSL_IOC_MEI_BSP_MAGIC, 16, DSL_DEV_MeiReg_t)\n+#define DSL_FIO_BSP_DEBUG_READ\t\t_IOWR(DSL_IOC_MEI_BSP_MAGIC, 17, DSL_DEV_MeiDebug_t)\n+#define DSL_FIO_BSP_DEBUG_WRITE\t\t_IOWR(DSL_IOC_MEI_BSP_MAGIC, 18, DSL_DEV_MeiDebug_t)\n+#define DSL_FIO_BSP_GET_CHIP_INFO\t_IOR (DSL_IOC_MEI_BSP_MAGIC, 19, DSL_DEV_HwVersion_t)\n+\n+#define DSL_DEV_MEIDEBUG_BUFFER_SIZES\t512\n+\n+typedef struct DSL_DEV_MeiDebug\n+{\n+\tDSL_uint32_t iAddress;\n+\tDSL_uint32_t iCount;\n+\tDSL_uint32_t buffer[DSL_DEV_MEIDEBUG_BUFFER_SIZES];\n+} DSL_DEV_MeiDebug_t;\t\t\t/* meidebug */\n+\n+/**\n+ *    Structure is used for debug access only.\n+ *       Refer to configure option INCLUDE_ADSL_WINHOST_DEBUG */\n+typedef struct struct_meireg\n+{\n+\t/*\n+\t*       Specifies that address for debug access */\n+\tunsigned long iAddress;\n+\t/*\n+\t*       Specifies the pointer to the data that has to be written or returns a\n+\t*             pointer to the data that has been read out*/\n+\tunsigned long iData;\n+} DSL_DEV_MeiReg_t;\t\t\t\t\t/* meireg */\n+\n+typedef struct DSL_DEV_Device\n+{\n+\tDSL_int_t nInUse;                /* modem state, update by bsp driver, */\n+\tDSL_void_t *pPriv;\n+\tDSL_uint32_t base_address;       /* mei base address */\n+\tDSL_int_t nIrq[2];                  /* irq number */\n+#define IFX_DFEIR\t\t0\n+#define IFX_DYING_GASP\t1\n+\tDSL_DEV_MeiDebug_t lop_debugwr;  /* dying gasp */\n+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0))\n+\tstruct module *owner;\n+#endif\n+} DSL_DEV_Device_t;\t\t\t/* ifx_adsl_device_t */\n+\n+#define DSL_DEV_PRIVATE(dev)  ((ifx_mei_device_private_t*)(dev->pPriv))\n+\n+typedef struct DSL_DEV_Version\t\t/* ifx_adsl_bsp_version */\n+{\n+\tunsigned long major;\n+\tunsigned long minor;\n+\tunsigned long revision;\n+} DSL_DEV_Version_t;\t\t\t/* ifx_adsl_bsp_version_t */\n+\n+typedef struct DSL_DEV_ChipInfo\n+{\n+\tunsigned long major;\n+\tunsigned long minor;\n+} DSL_DEV_HwVersion_t;\n+\n+typedef struct\n+{\n+\tDSL_uint8_t dummy;\n+} DSL_DEV_DeviceConfig_t;\n+\n+/** error code definitions */\n+typedef enum DSL_DEV_MeiError\n+{\n+\tDSL_DEV_MEI_ERR_SUCCESS = 0,\n+\tDSL_DEV_MEI_ERR_FAILURE = -1,\n+\tDSL_DEV_MEI_ERR_MAILBOX_FULL = -2,\n+\tDSL_DEV_MEI_ERR_MAILBOX_EMPTY = -3,\n+\tDSL_DEV_MEI_ERR_MAILBOX_TIMEOUT = -4\n+} DSL_DEV_MeiError_t;\t\t\t/* MEI_ERROR */\n+\n+typedef enum {\n+\tDSL_BSP_MEMORY_READ=0,\n+\tDSL_BSP_MEMORY_WRITE,\n+} DSL_BSP_MemoryAccessType_t;\t\t/* ifx_adsl_memory_access_type_t */\n+\n+typedef enum\n+{\n+\tDSL_LED_LINK_ID=0,\n+\tDSL_LED_DATA_ID\n+} DSL_DEV_LedId_t;\t\t\t/* ifx_adsl_led_id_t */\n+\n+typedef enum\n+{\n+\tDSL_LED_LINK_TYPE=0,\n+\tDSL_LED_DATA_TYPE\n+} DSL_DEV_LedType_t;\t\t\t/* ifx_adsl_led_type_t */\n+\n+typedef enum\n+{\n+\tDSL_LED_HD_CPU=0,\n+\tDSL_LED_HD_FW\n+} DSL_DEV_LedHandler_t;\t\t\t/* ifx_adsl_led_handler_t */\n+\n+typedef enum {\n+\tDSL_LED_ON=0,\n+\tDSL_LED_OFF,\n+\tDSL_LED_FLASH,\n+} DSL_DEV_LedMode_t;\t\t\t/* ifx_adsl_led_mode_t */\n+\n+typedef enum {\n+\tDSL_CPU_HALT=0,\n+\tDSL_CPU_RUN,\n+\tDSL_CPU_RESET,\n+} DSL_DEV_CpuMode_t;\t\t\t/* ifx_adsl_cpu_mode_t */\n+\n+#if 0\n+typedef enum {\n+\tDSL_BSP_EVENT_DYING_GASP = 0,\n+\tDSL_BSP_EVENT_CEOC_IRQ,\n+} DSL_BSP_Event_id_t;\t\t\t/* ifx_adsl_event_id_t */\n+\n+typedef union DSL_BSP_CB_Param\n+{\n+\tDSL_uint32_t nIrqMessage;\n+} DSL_BSP_CB_Param_t;\t\t\t/* ifx_adsl_cbparam_t */\n+\n+typedef struct DSL_BSP_CB_Event\n+{\n+\tDSL_BSP_Event_id_t nID;\n+\tDSL_DEV_Device_t *pDev;\n+\tDSL_BSP_CB_Param_t *pParam;\n+} DSL_BSP_CB_Event_t;\t\t\t/* ifx_adsl_cb_event_t */\n+#endif\n+\n+/* external functions (from the BSP Driver) */\n+extern DSL_DEV_Device_t* DSL_BSP_DriverHandleGet(int, int);\n+extern DSL_int_t DSL_BSP_DriverHandleDelete(DSL_DEV_Device_t *);\n+extern DSL_DEV_MeiError_t DSL_BSP_FWDownload(DSL_DEV_Device_t *, const DSL_char_t *, DSL_uint32_t, DSL_int32_t *, DSL_int32_t *);\n+extern int DSL_BSP_KernelIoctls(DSL_DEV_Device_t *, unsigned int, unsigned long);\n+extern DSL_DEV_MeiError_t DSL_BSP_SendCMV(DSL_DEV_Device_t *, DSL_uint16_t *, DSL_int_t, DSL_uint16_t *);\n+extern DSL_DEV_MeiError_t DSL_BSP_AdslLedInit(DSL_DEV_Device_t *, DSL_DEV_LedId_t, DSL_DEV_LedType_t, DSL_DEV_LedHandler_t);\n+extern DSL_DEV_MeiError_t DSL_BSP_Showtime(DSL_DEV_Device_t *, DSL_uint32_t, DSL_uint32_t);\n+extern int DSL_BSP_ATMLedCBRegister( int (*ifx_adsl_ledcallback)(void));\n+extern DSL_DEV_MeiError_t DSL_BSP_MemoryDebugAccess(DSL_DEV_Device_t *, DSL_BSP_MemoryAccessType_t, DSL_uint32_t, DSL_uint32_t *, DSL_uint32_t);\n+extern volatile DSL_DEV_Device_t *adsl_dev;\n+\n+/**\n+ *    Dummy structure by now to show mechanism of extended data that will be\n+ *       provided within event callback itself.\n+ *       */\n+typedef struct\n+{\n+\t/**\n+\t*    Dummy value */\n+\tDSL_uint32_t nDummy1;\n+} DSL_BSP_CB_Event1DataDummy_t;\n+\n+/**\n+ *    Dummy structure by now to show mechanism of extended data that will be\n+ *       provided within event callback itself.\n+ *       */\n+typedef struct\n+{\n+\t/**\n+\t*    Dummy value */\n+\tDSL_uint32_t nDummy2;\n+} DSL_BSP_CB_Event2DataDummy_t;\n+\n+/**\n+ *    encapsulate all data structures that are necessary for status event\n+ *       callbacks.\n+ *       */\n+typedef union\n+{\n+\tDSL_BSP_CB_Event1DataDummy_t dataEvent1;\n+\tDSL_BSP_CB_Event2DataDummy_t dataEvent2;\n+} DSL_BSP_CB_DATA_Union_t;\n+\n+\n+typedef enum\n+{\n+\t/**\n+\t *    Informs the upper layer driver (DSL CPE API) about a reboot request from the\n+\t *       firmware.\n+\t *          \\note This event does NOT include any additional data.\n+\t *                   More detailed information upon reboot reason has to be requested from\n+\t *                            upper layer software via CMV (INFO 109) if necessary. */\n+\tDSL_BSP_CB_FIRST = 0,\n+        DSL_BSP_CB_DYING_GASP,\n+\tDSL_BSP_CB_CEOC_IRQ,\n+\tDSL_BSP_CB_FIRMWARE_REBOOT,\n+\t/**\n+\t *    Delimiter only */\n+\tDSL_BSP_CB_LAST\n+} DSL_BSP_CB_Type_t;\n+\n+/**\n+ *    Specifies the common event type that has to be used for registering and\n+ *       signalling of interrupts/autonomous status events from MEI BSP Driver.\n+ *\n+ *    \\param pDev\n+ *    Context pointer from MEI BSP Driver.\n+ *\n+ *    \\param IFX_ADSL_BSP_CallbackType_t\n+ *    Specifies the event callback type (reason of callback). Regrading to the\n+ *    setting of this value the data which is included in the following union\n+ *    might have different meanings.\n+ *    Please refer to the description of the union to get information about the\n+ *    meaning of the included data.\n+ *\n+ *    \\param pData\n+ *    Data according to \\ref DSL_BSP_CB_DATA_Union_t.\n+ *    If this pointer is NULL there is no additional data available.\n+ *\n+ *    \\return depending on event\n+ */\n+typedef int (*DSL_BSP_EventCallback_t)\n+(\n+\tDSL_DEV_Device_t *pDev,\n+\tDSL_BSP_CB_Type_t nCallbackType,\n+\tDSL_BSP_CB_DATA_Union_t *pData\n+);\n+\n+typedef struct {\n+        DSL_BSP_EventCallback_t function;\n+        DSL_BSP_CB_Type_t       event;\n+        DSL_BSP_CB_DATA_Union_t *pData;\n+} DSL_BSP_EventCallBack_t;\n+\n+extern int DSL_BSP_EventCBRegister(DSL_BSP_EventCallBack_t *);\n+extern int DSL_BSP_EventCBUnregister(DSL_BSP_EventCallBack_t *);\n+\n+/** Modem states */\n+#define DSL_DEV_STAT_InitState              0x0000\n+#define DSL_DEV_STAT_ReadyState             0x0001\n+#define DSL_DEV_STAT_FailState              0x0002\n+#define DSL_DEV_STAT_IdleState              0x0003\n+#define DSL_DEV_STAT_QuietState             0x0004\n+#define DSL_DEV_STAT_GhsState               0x0005\n+#define DSL_DEV_STAT_FullInitState          0x0006\n+#define DSL_DEV_STAT_ShowTimeState          0x0007\n+#define DSL_DEV_STAT_FastRetrainState       0x0008\n+#define DSL_DEV_STAT_LoopDiagMode           0x0009\n+#define DSL_DEV_STAT_ShortInit              0x000A     /* Bis short initialization */\n+\n+#define DSL_DEV_STAT_CODESWAP_COMPLETE\t    0x0002\n+\n+#endif //IFXMIPS_MEI_H\n--- a/configure.in\n+++ b/configure.in\n@@ -310,7 +310,7 @@ dnl Set kernel build path\n AC_ARG_ENABLE(kernelbuild,\n     AC_HELP_STRING(--enable-kernel-build=x,Set the target kernel build path),\n     [\n-        if test -e $enableval/include/linux/autoconf.h; then\n+        if test -e $enableval/include/linux/autoconf.h -o -e $enableval/include/generated/autoconf.h; then\n             AC_SUBST([KERNEL_BUILD_PATH],[$enableval])\n         else\n             AC_MSG_ERROR([The kernel build directory is not valid or not configured!])\n@@ -333,12 +333,12 @@ AC_ARG_ENABLE(ifxos-include,\n             echo Set the lib_ifxos include path $enableval\n             AC_SUBST([IFXOS_INCLUDE_PATH],[$enableval])\n         else\n-            echo -e Set the default lib_ifxos include path $DEFAULT_IFXOS_INCLUDE_PATH\n+            echo Set the default lib_ifxos include path $DEFAULT_IFXOS_INCLUDE_PATH\n             AC_SUBST([IFXOS_INCLUDE_PATH],[$DEFAULT_IFXOS_INCLUDE_PATH])\n         fi\n     ],\n     [\n-        echo -e Set the default lib_ifxos include path $DEFAULT_IFXOS_INCLUDE_PATH\n+        echo Set the default lib_ifxos include path $DEFAULT_IFXOS_INCLUDE_PATH\n         AC_SUBST([IFXOS_INCLUDE_PATH],[$DEFAULT_IFXOS_INCLUDE_PATH])\n     ]\n )\n@@ -1702,73 +1702,73 @@ dnl Set the configure params for dist ch\n AC_SUBST([DISTCHECK_CONFIGURE_PARAMS],[$CONFIGURE_OPTIONS])\n \n AC_CONFIG_COMMANDS_PRE([\n-echo -e \"------------------------------------------------------------------------\"\n-echo -e \" Configuration for drv_dsl_cpe_api:\"\n-echo -e \"  Configure model type:             $DSL_CONFIG_MODEL_TYPE\"\n-echo -e \"  Source code location:             $srcdir\"\n-echo -e \"  Compiler:                         $CC\"\n-echo -e \"  Compiler c-flags:                 $CFLAGS\"\n-echo -e \"  Extra compiler c-flags:           $EXTRA_DRV_CFLAGS\"\n-echo -e \"  Host System Type:                 $host\"\n-echo -e \"  Install path:                     $prefix\"\n-echo -e \"  Linux kernel include path:        $KERNEL_INCL_PATH\"\n-echo -e \"  Linux kernel build path:          $KERNEL_BUILD_PATH\"\n-echo -e \"  Linux kernel architecture:        $KERNEL_ARCH\"\n-echo -e \"  Include IFXOS:                    $INCLUDE_DSL_CPE_API_IFXOS_SUPPORT\"\n-echo -e \"  IFXOS include path:               $IFXOS_INCLUDE_PATH\"\n-echo -e \"  Driver Include Path               $DSL_DRIVER_INCL_PATH\"\n-echo -e \"  DSL device:                       $DSL_DEVICE_NAME\"\n-echo -e \"  Max device number:                $DSL_DRV_MAX_DEVICE_NUMBER\"\n-echo -e \"  Channels per line:                $DSL_CHANNELS_PER_LINE\"\n-echo -e \"  Build lib (only for kernel 2.6)   $DSL_CPE_API_LIBRARY_BUILD_2_6\"\n-echo -e \"  DSL data led flash frequency:     $DSL_DATA_LED_FLASH_FREQUENCY Hz\"\n-echo -e \"  Disable debug prints:             $DSL_DEBUG_DISABLE\"\n-echo -e \"  Preselection of max. debug level: $DSL_DBG_MAX_LEVEL_SET\"\n-echo -e \"  Preselected max. debug level:     $DSL_DBG_MAX_LEVEL_PRE\"\n-echo -e \"  Include deprecated functions:     $INCLUDE_DEPRECATED\"\n-echo -e \"  Include Device Exception Codes:   $INCLUDE_DEVICE_EXCEPTION_CODES\"\n-echo -e \"  Include FW request support:       $INCLUDE_FW_REQUEST_SUPPORT\"\n-echo -e \"  Include ADSL trace buffer:        $INCLUDE_DSL_CPE_TRACE_BUFFER\"\n-echo -e \"  Include ADSL MIB:                 $INCLUDE_DSL_ADSL_MIB\"\n-echo -e \"  Include ADSL LED:                 $INCLUDE_ADSL_LED\"\n-echo -e \"  Include CEOC:                     $INCLUDE_DSL_CEOC\"\n-echo -e \"  Include config get support:       $INCLUDE_DSL_CONFIG_GET\"\n-echo -e \"  Include System i/f configuration: $INCLUDE_DSL_SYSTEM_INTERFACE\"\n-echo -e \"  Include Resource Statistics:      $INCLUDE_DSL_RESOURCE_STATISTICS\"\n-echo -e \"  Include Framing Parameters:       $INCLUDE_DSL_FRAMING_PARAMETERS\"\n-echo -e \"  Include G997 Line Inventory:      $INCLUDE_DSL_G997_LINE_INVENTORY\"\n-echo -e \"  Include G997 Framing Parameters:  $INCLUDE_DSL_G997_FRAMING_PARAMETERS\"\n-echo -e \"  Include G997 per tone data:       $INCLUDE_DSL_G997_PER_TONE\"\n-echo -e \"  Include G997 status:              $INCLUDE_DSL_G997_STATUS\"\n-echo -e \"  Include G997 alarm:               $INCLUDE_DSL_G997_ALARM\"\n-echo -e \"  Include DSL Bonding:              $INCLUDE_DSL_BONDING\"\n-echo -e \"  Include Misc Line Status          $INCLUDE_DSL_CPE_MISC_LINE_STATUS\"\n-echo -e \"  Include DELT:                     $INCLUDE_DSL_DELT\"\n-echo -e \"  Include DELT data static storage: $DSL_CPE_STATIC_DELT_DATA\"\n-echo -e \"  Include PM:                       $INCLUDE_DSL_PM\"\n-echo -e \"  Include PM config:                $INCLUDE_DSL_CPE_PM_CONFIG\"\n-echo -e \"  Include PM total:                 $INCLUDE_DSL_CPE_PM_TOTAL_COUNTERS\"\n-echo -e \"  Include PM history:               $INCLUDE_DSL_CPE_PM_HISTORY\"\n-echo -e \"  Include PM showtime:              $INCLUDE_DSL_CPE_PM_SHOWTIME_COUNTERS\"\n-echo -e \"  Include PM optional:              $INCLUDE_DSL_CPE_PM_OPTIONAL_PARAMETERS\"\n-echo -e \"  Include PM line:                  $INCLUDE_DSL_CPE_PM_LINE_COUNTERS\"\n-echo -e \"  Include PM line event showtime:   $INCLUDE_DSL_CPE_PM_LINE_EVENT_SHOWTIME_COUNTERS\"\n-echo -e \"  Include PM channel:               $INCLUDE_DSL_CPE_PM_CHANNEL_COUNTERS\"\n-echo -e \"  Include PM channel extended:      $INCLUDE_DSL_CPE_PM_CHANNEL_EXT_COUNTERS\"\n-echo -e \"  Include PM data path:             $INCLUDE_DSL_CPE_PM_DATA_PATH_COUNTERS\"\n-echo -e \"  Include PM data path failure:     $INCLUDE_DSL_CPE_PM_DATA_PATH_FAILURE_COUNTERS\"\n-echo -e \"  Include PM ReTx:                  $INCLUDE_DSL_CPE_PM_RETX_COUNTERS\"\n-echo -e \"  Include PM line threshold:        $INCLUDE_DSL_CPE_PM_LINE_THRESHOLDS\"\n-echo -e \"  Include PM channel threshold:     $INCLUDE_DSL_CPE_PM_CHANNEL_THRESHOLDS\"\n-echo -e \"  Include PM data path threshold:   $INCLUDE_DSL_CPE_PM_DATA_PATH_THRESHOLDS\"\n-echo -e \"  Include PM ReTx threshold:        $INCLUDE_DSL_CPE_PM_RETX_THRESHOLDS\"\n-echo -e \"  Include FW memory free support:   $INCLUDE_DSL_FIRMWARE_MEMORY_FREE\"\n-echo -e \"----------------------- deprectated ! ----------------------------------\"\n-echo -e \"  Include PM line failure:          $INCLUDE_DSL_CPE_PM_LINE_FAILURE_COUNTERS\"\n-echo -e \"\"\n-echo -e \" Settings:\"\n-echo -e \"  Configure options:                $CONFIGURE_OPTIONS\"\n-echo -e \"------------------------------------------------------------------------\"\n+echo \"------------------------------------------------------------------------\"\n+echo \" Configuration for drv_dsl_cpe_api:\"\n+echo \"  Configure model type:             $DSL_CONFIG_MODEL_TYPE\"\n+echo \"  Source code location:             $srcdir\"\n+echo \"  Compiler:                         $CC\"\n+echo \"  Compiler c-flags:                 $CFLAGS\"\n+echo \"  Extra compiler c-flags:           $EXTRA_DRV_CFLAGS\"\n+echo \"  Host System Type:                 $host\"\n+echo \"  Install path:                     $prefix\"\n+echo \"  Linux kernel include path:        $KERNEL_INCL_PATH\"\n+echo \"  Linux kernel build path:          $KERNEL_BUILD_PATH\"\n+echo \"  Linux kernel architecture:        $KERNEL_ARCH\"\n+echo \"  Include IFXOS:                    $INCLUDE_DSL_CPE_API_IFXOS_SUPPORT\"\n+echo \"  IFXOS include path:               $IFXOS_INCLUDE_PATH\"\n+echo \"  Driver Include Path               $DSL_DRIVER_INCL_PATH\"\n+echo \"  DSL device:                       $DSL_DEVICE_NAME\"\n+echo \"  Max device number:                $DSL_DRV_MAX_DEVICE_NUMBER\"\n+echo \"  Channels per line:                $DSL_CHANNELS_PER_LINE\"\n+echo \"  Build lib (only for kernel 2.6)   $DSL_CPE_API_LIBRARY_BUILD_2_6\"\n+echo \"  DSL data led flash frequency:     $DSL_DATA_LED_FLASH_FREQUENCY Hz\"\n+echo \"  Disable debug prints:             $DSL_DEBUG_DISABLE\"\n+echo \"  Preselection of max. debug level: $DSL_DBG_MAX_LEVEL_SET\"\n+echo \"  Preselected max. debug level:     $DSL_DBG_MAX_LEVEL_PRE\"\n+echo \"  Include deprecated functions:     $INCLUDE_DEPRECATED\"\n+echo \"  Include Device Exception Codes:   $INCLUDE_DEVICE_EXCEPTION_CODES\"\n+echo \"  Include FW request support:       $INCLUDE_FW_REQUEST_SUPPORT\"\n+echo \"  Include ADSL trace buffer:        $INCLUDE_DSL_CPE_TRACE_BUFFER\"\n+echo \"  Include ADSL MIB:                 $INCLUDE_DSL_ADSL_MIB\"\n+echo \"  Include ADSL LED:                 $INCLUDE_ADSL_LED\"\n+echo \"  Include CEOC:                     $INCLUDE_DSL_CEOC\"\n+echo \"  Include config get support:       $INCLUDE_DSL_CONFIG_GET\"\n+echo \"  Include System i/f configuration: $INCLUDE_DSL_SYSTEM_INTERFACE\"\n+echo \"  Include Resource Statistics:      $INCLUDE_DSL_RESOURCE_STATISTICS\"\n+echo \"  Include Framing Parameters:       $INCLUDE_DSL_FRAMING_PARAMETERS\"\n+echo \"  Include G997 Line Inventory:      $INCLUDE_DSL_G997_LINE_INVENTORY\"\n+echo \"  Include G997 Framing Parameters:  $INCLUDE_DSL_G997_FRAMING_PARAMETERS\"\n+echo \"  Include G997 per tone data:       $INCLUDE_DSL_G997_PER_TONE\"\n+echo \"  Include G997 status:              $INCLUDE_DSL_G997_STATUS\"\n+echo \"  Include G997 alarm:               $INCLUDE_DSL_G997_ALARM\"\n+echo \"  Include DSL Bonding:              $INCLUDE_DSL_BONDING\"\n+echo \"  Include Misc Line Status          $INCLUDE_DSL_CPE_MISC_LINE_STATUS\"\n+echo \"  Include DELT:                     $INCLUDE_DSL_DELT\"\n+echo \"  Include DELT data static storage: $DSL_CPE_STATIC_DELT_DATA\"\n+echo \"  Include PM:                       $INCLUDE_DSL_PM\"\n+echo \"  Include PM config:                $INCLUDE_DSL_CPE_PM_CONFIG\"\n+echo \"  Include PM total:                 $INCLUDE_DSL_CPE_PM_TOTAL_COUNTERS\"\n+echo \"  Include PM history:               $INCLUDE_DSL_CPE_PM_HISTORY\"\n+echo \"  Include PM showtime:              $INCLUDE_DSL_CPE_PM_SHOWTIME_COUNTERS\"\n+echo \"  Include PM optional:              $INCLUDE_DSL_CPE_PM_OPTIONAL_PARAMETERS\"\n+echo \"  Include PM line:                  $INCLUDE_DSL_CPE_PM_LINE_COUNTERS\"\n+echo \"  Include PM line event showtime:   $INCLUDE_DSL_CPE_PM_LINE_EVENT_SHOWTIME_COUNTERS\"\n+echo \"  Include PM channel:               $INCLUDE_DSL_CPE_PM_CHANNEL_COUNTERS\"\n+echo \"  Include PM channel extended:      $INCLUDE_DSL_CPE_PM_CHANNEL_EXT_COUNTERS\"\n+echo \"  Include PM data path:             $INCLUDE_DSL_CPE_PM_DATA_PATH_COUNTERS\"\n+echo \"  Include PM data path failure:     $INCLUDE_DSL_CPE_PM_DATA_PATH_FAILURE_COUNTERS\"\n+echo \"  Include PM ReTx:                  $INCLUDE_DSL_CPE_PM_RETX_COUNTERS\"\n+echo \"  Include PM line threshold:        $INCLUDE_DSL_CPE_PM_LINE_THRESHOLDS\"\n+echo \"  Include PM channel threshold:     $INCLUDE_DSL_CPE_PM_CHANNEL_THRESHOLDS\"\n+echo \"  Include PM data path threshold:   $INCLUDE_DSL_CPE_PM_DATA_PATH_THRESHOLDS\"\n+echo \"  Include PM ReTx threshold:        $INCLUDE_DSL_CPE_PM_RETX_THRESHOLDS\"\n+echo \"  Include FW memory free support:   $INCLUDE_DSL_FIRMWARE_MEMORY_FREE\"\n+echo \"----------------------- deprectated ! ----------------------------------\"\n+echo \"  Include PM line failure:          $INCLUDE_DSL_CPE_PM_LINE_FAILURE_COUNTERS\"\n+echo \"\"\n+echo \" Settings:\"\n+echo \"  Configure options:                $CONFIGURE_OPTIONS\"\n+echo \"------------------------------------------------------------------------\"\n ])\n \n AC_CONFIG_FILES([Makefile src/Makefile])\n--- a/src/Makefile.am\n+++ b/src/Makefile.am\n@@ -300,7 +300,7 @@ if KERNEL_2_6\n drv_dsl_cpe_api_OBJS = \"$(subst .c,.o,$(filter %.c,$(drv_dsl_cpe_api_SOURCES)))\"\n \n drv_dsl_cpe_api.ko: $(drv_dsl_cpe_api_SOURCES)\n-\t@echo -e \"drv_dsl_cpe_api: Making Linux 2.6.x kernel object\"\n+\t@echo \"drv_dsl_cpe_api: Making Linux 2.6.x kernel object\"\n \tif test ! -e common/drv_dsl_cpe_api.c ; then \\\n \t\techo \"copy source files (as links only!)\"; \\\n \t\tfor f in $(filter %.c,$(drv_dsl_cpe_api_SOURCES)); do \\\n@@ -308,10 +308,10 @@ drv_dsl_cpe_api.ko: $(drv_dsl_cpe_api_SO\n \t\t\tcp -s $(addprefix @abs_srcdir@/,$$f) $(PWD)/`dirname $$f`/ ; \\\n \t\tdone \\\n \tfi\n-\t@echo -e \"# drv_dsl_cpe_api: Generated to build Linux 2.6.x kernel object\" > $(PWD)/Kbuild\n-\t@echo -e \"obj-m := $(subst .ko,.o,$@)\"\t\t\t>> $(PWD)/Kbuild\n-\t@echo -e \"$(subst .ko,,$@)-y := $(drv_dsl_cpe_api_OBJS)\"\t>> $(PWD)/Kbuild\n-\t@echo -e \"EXTRA_CFLAGS := -DHAVE_CONFIG_H $(drv_dsl_cpe_api_CFLAGS) $(DSL_DRIVER_INCL_PATH) $(IFXOS_INCLUDE_PATH) -I@abs_srcdir@/include -I$(PWD)/include\"\t>> $(PWD)/Kbuild\n+\t@echo \"# drv_dsl_cpe_api: Generated to build Linux 2.6.x kernel object\" > $(PWD)/Kbuild\n+\t@echo \"obj-m := $(subst .ko,.o,$@)\"\t\t\t>> $(PWD)/Kbuild\n+\t@echo \"$(subst .ko,,$@)-y := $(drv_dsl_cpe_api_OBJS)\"\t>> $(PWD)/Kbuild\n+\t@echo \"EXTRA_CFLAGS := -DHAVE_CONFIG_H $(drv_dsl_cpe_api_CFLAGS) $(DSL_DRIVER_INCL_PATH) $(IFXOS_INCLUDE_PATH) -I@abs_srcdir@/include -I$(PWD)/include\"\t>> $(PWD)/Kbuild\n \t$(MAKE) ARCH=@KERNEL_ARCH@ -C @KERNEL_BUILD_PATH@ O=@KERNEL_BUILD_PATH@ M=$(PWD) modules\n \n clean-generic:\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-adsl/patches/110-fix_status_polling_loop.patch",
    "content": "--- a/src/device/drv_dsl_cpe_device_danube.c\n+++ b/src/device/drv_dsl_cpe_device_danube.c\n@@ -4069,7 +4069,7 @@ static DSL_Error_t DSL_DRV_DANUBE_XTUSys\n \n    DSL_CTX_WRITE(pContext, nErrCode, xtseCurr, xtseCurr);\n \n-   for (nRetry = 0; nRetry < 20; nRetry++)\n+   for (nRetry = 0; nRetry < 20 && bStatusUpdated == DSL_FALSE; nRetry++)\n    {\n       /* Get STAT1 info*/\n       nErrCode = DSL_DRV_DANUBE_CmvRead(pContext, DSL_CMV_GROUP_STAT,\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-adsl/patches/120-platform.patch",
    "content": "--- a/src/common/drv_dsl_cpe_os_linux.c\n+++ b/src/common/drv_dsl_cpe_os_linux.c\n@@ -11,7 +11,7 @@\n #ifdef __LINUX__\n \n #define DSL_INTERN\n-#include <linux/device.h>\n+#include <linux/of_platform.h>\n \n #include \"drv_dsl_cpe_api.h\"\n #include \"drv_dsl_cpe_api_ioctl.h\"\n@@ -1070,7 +1070,7 @@ static void DSL_DRV_DebugInit(void)\n #endif\n \n /* Entry point of driver */\n-int __init DSL_ModuleInit(void)\n+static int __devinit ltq_adsl_probe(struct platform_device *pdev)\n {\n    struct class *dsl_class;\n    DSL_int_t i;\n@@ -1124,7 +1124,7 @@ int __init DSL_ModuleInit(void)\n    return 0;\n }\n \n-void __exit DSL_ModuleCleanup(void)\n+static int __devexit ltq_adsl_remove(struct platform_device *pdev)\n {\n    printk(\"Module will be unloaded\"DSL_DRV_CRLF);\n \n@@ -1139,7 +1139,7 @@ void __exit DSL_ModuleCleanup(void)\n                (DSL_uint8_t**)&g_BndFpgaBase);\n #endif /* defined(INCLUDE_DSL_CPE_API_VINAX) && defined(INCLUDE_DSL_BONDING)*/\n \n-   return;\n+   return 0;\n }\n \n #ifndef _lint\n@@ -1155,8 +1155,30 @@ module_param(debug_level, byte, 0);\n MODULE_PARM_DESC(debug_level, \"set to get more (1) or fewer (4) debug outputs\");\n #endif /* #ifndef DSL_DEBUG_DISABLE*/\n \n-module_init(DSL_ModuleInit);\n-module_exit(DSL_ModuleCleanup);\n+static const struct of_device_id ltq_adsl_match[] = {\n+#ifdef CONFIG_DANUBE\n+\t{ .compatible = \"lantiq,adsl-danube\"},\n+#elif defined CONFIG_AMAZON_SE\n+\t{ .compatible = \"lantiq,adsl-ase\"},\n+#elif defined CONFIG_AR9\n+\t{ .compatible = \"lantiq,adsl-arx100\"},\n+#endif\n+\t{},\n+};\n+MODULE_DEVICE_TABLE(of, ltq_adsl_match);\n+\n+static struct platform_driver ltq_adsl_driver = {\n+\t.probe = ltq_adsl_probe,\n+\t.remove = __devexit_p(ltq_adsl_remove),\n+\t.driver = {\n+\t\t.name = \"adsl\",\n+\t\t.owner = THIS_MODULE,\n+\t\t.of_match_table = ltq_adsl_match,\n+\t},\n+};\n+\n+module_platform_driver(ltq_adsl_driver);\n+\n #endif /* #ifndef _lint*/\n \n //EXPORT_SYMBOL(DSL_ModuleInit);\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-adsl/patches/130-linux3.8.patch",
    "content": "--- a/src/common/drv_dsl_cpe_os_linux.c\n+++ b/src/common/drv_dsl_cpe_os_linux.c\n@@ -11,6 +11,7 @@\n #ifdef __LINUX__\n \n #define DSL_INTERN\n+#include <linux/kthread.h>\n #include <linux/of_platform.h>\n \n #include \"drv_dsl_cpe_api.h\"\n@@ -39,7 +40,7 @@ static DSL_ssize_t DSL_DRV_Write(DSL_DRV\n static DSL_int_t DSL_DRV_Ioctls(DSL_DRV_inode_t * pINode, DSL_DRV_file_t * pFile,\n                          DSL_uint_t nCommand, unsigned long nArg);\n #else\n-static DSL_int_t DSL_DRV_Ioctls(DSL_DRV_file_t * pFile,\n+static long DSL_DRV_Ioctls(DSL_DRV_file_t * pFile,\n                          DSL_uint_t nCommand, unsigned long nArg);\n #endif\n static int DSL_DRV_Open(DSL_DRV_inode_t * ino, DSL_DRV_file_t * fil);\n@@ -183,7 +184,7 @@ static DSL_int_t DSL_DRV_Ioctls(DSL_DRV_\n    DSL_uint_t nCommand,\n    unsigned long nArg)\n #else\n-static DSL_int_t DSL_DRV_Ioctls(\n+static long DSL_DRV_Ioctls(\n    DSL_DRV_file_t * pFile,\n    DSL_uint_t nCommand,\n    unsigned long nArg)\n@@ -520,9 +521,9 @@ DSL_void_t* DSL_IoctlMemCpyTo(\n    - IFX_SUCCESS on success\n    - IFX_ERROR on error\n */\n-DSL_DRV_STATIC DSL_int32_t DSL_DRV_KernelThreadStartup(\n-                              DSL_DRV_ThreadCtrl_t *pThrCntrl)\n+static int DSL_DRV_KernelThreadStartup(void *data)\n {\n+   DSL_DRV_ThreadCtrl_t *pThrCntrl = (DSL_DRV_ThreadCtrl_t*) data;\n    DSL_int32_t retVal          = -1;\n #ifndef _lint\n \n@@ -545,30 +546,6 @@ DSL_DRV_STATIC DSL_int32_t DSL_DRV_Kerne\n       (DSL_NULL, \"ENTER - Kernel Thread Startup <%s>\" DSL_DRV_CRLF,\n         pThrCntrl->thrParams.pName));\n \n-   /* do LINUX specific setup */\n-#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0))\n-   daemonize();\n-   reparent_to_init();\n-\n-   /* lock the kernel. A new kernel thread starts without\n-      the big kernel lock, regardless of the lock state\n-      of the creator (the lock level is *not* inheritated)\n-   */\n-   lock_kernel();\n-\n-   /* Don't care about any signals. */\n-   siginitsetinv(&current->blocked, 0);\n-\n-   /* set name of this process */\n-   strcpy(kthread->comm, pThrCntrl->thrParams.pName);\n-\n-   /* let others run */\n-   unlock_kernel();\n-#else\n-   daemonize(pThrCntrl->thrParams.pName);\n-\n-#endif\n-\n    /*DSL_DRV_ThreadPriorityModify(pThrCntrl->nPriority);*/\n \n    pThrCntrl->thrParams.bRunning = 1;\n@@ -638,9 +615,7 @@ DSL_int32_t DSL_DRV_ThreadInit(\n          init_completion(&pThrCntrl->thrCompletion);\n \n          /* start kernel thread via the wrapper function */\n-         pThrCntrl->pid = kernel_thread( (DSL_DRV_KERNEL_THREAD_StartRoutine)DSL_DRV_KernelThreadStartup,\n-                        (void *)pThrCntrl,\n-                        DSL_DRV_DRV_THREAD_OPTIONS);\n+         pThrCntrl->pid = kthread_run(DSL_DRV_KernelThreadStartup, (void *)pThrCntrl, pThrCntrl->thrParams.pName);\n \n          pThrCntrl->bValid = DSL_TRUE;\n \n@@ -1070,12 +1045,12 @@ static void DSL_DRV_DebugInit(void)\n #endif\n \n /* Entry point of driver */\n-static int __devinit ltq_adsl_probe(struct platform_device *pdev)\n+static int ltq_adsl_probe(struct platform_device *pdev)\n {\n    struct class *dsl_class;\n    DSL_int_t i;\n \n-   printk(DSL_DRV_CRLF DSL_DRV_CRLF \"Infineon CPE API Driver version: %s\" DSL_DRV_CRLF,\n+   printk(\"Infineon CPE API Driver version: %s\" DSL_DRV_CRLF,\n       &(dsl_cpe_api_version[4]));\n \n    DSL_DRV_MemSet( ifxDevices, 0, sizeof(DSL_devCtx_t) * DSL_DRV_MAX_DEVICE_NUMBER );\n@@ -1124,7 +1099,7 @@ static int __devinit ltq_adsl_probe(stru\n    return 0;\n }\n \n-static int __devexit ltq_adsl_remove(struct platform_device *pdev)\n+static int ltq_adsl_remove(struct platform_device *pdev)\n {\n    printk(\"Module will be unloaded\"DSL_DRV_CRLF);\n \n@@ -1169,7 +1144,7 @@ MODULE_DEVICE_TABLE(of, ltq_adsl_match);\n \n static struct platform_driver ltq_adsl_driver = {\n \t.probe = ltq_adsl_probe,\n-\t.remove = __devexit_p(ltq_adsl_remove),\n+\t.remove = ltq_adsl_remove,\n \t.driver = {\n \t\t.name = \"adsl\",\n \t\t.owner = THIS_MODULE,\n--- a/src/include/drv_dsl_cpe_os_lint_map.h\n+++ b/src/include/drv_dsl_cpe_os_lint_map.h\n@@ -247,7 +247,7 @@ typedef struct\n    DSL_DRV_ThreadFunction_t  pThrFct;\n \n    /** Kernel thread process ID */\n-   DSL_int32_t             pid;\n+   struct task_struct             *pid;\n \n    /** requested kernel thread priority */\n    DSL_int32_t             nPriority;\n--- a/src/include/drv_dsl_cpe_os_linux.h\n+++ b/src/include/drv_dsl_cpe_os_linux.h\n@@ -288,7 +288,7 @@ typedef struct\n    DSL_DRV_ThreadFunction_t  pThrFct;\n \n    /** Kernel thread process ID */\n-   DSL_int32_t             pid;\n+   struct task_struct             *pid;\n \n    /** requested kernel thread priority */\n    DSL_int32_t             nPriority;\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-adsl/patches/140-linux_3.18.patch",
    "content": "--- a/src/include/drv_dsl_cpe_os_linux.h\n+++ b/src/include/drv_dsl_cpe_os_linux.h\n@@ -214,12 +214,25 @@ static inline int dsl_mutex_lock(struct\n #define DSL_DRV_MUTEX_LOCK(id)               down_interruptible(&(id))\n #define DSL_DRV_MUTEX_UNLOCK(id)             up(&(id))\n #endif\n+\n+static inline long\n+ugly_hack_sleep_on_timeout(wait_queue_head_t *q, long timeout)\n+{\n+\tDEFINE_WAIT(wait);\n+\n+\tprepare_to_wait(q, &wait, TASK_INTERRUPTIBLE);\n+\ttimeout = schedule_timeout(timeout);\n+\tfinish_wait(q, &wait);\n+\n+\treturn timeout;\n+}\n+\n #define DSL_DRV_INIT_WAKELIST(name,queue)    init_waitqueue_head(&(queue))\n #define DSL_DRV_WAKEUP_WAKELIST(queue)       wake_up_interruptible(&(queue))\n #define DSL_DRV_INIT_EVENT(name,ev)          init_waitqueue_head(&(ev))\n /* wait for an event, timeout is measured in ms */\n-#define DSL_DRV_WAIT_EVENT_TIMEOUT(ev,t)     interruptible_sleep_on_timeout(&(ev), (t) * HZ / 1000)\n-#define DSL_DRV_WAIT_EVENT(ev)               interruptible_sleep_on(&(ev))\n+#define DSL_DRV_WAIT_EVENT_TIMEOUT(ev,t)     ugly_hack_sleep_on_timeout(&(ev), (t) * HZ / 1000)\n+#define DSL_DRV_WAIT_EVENT(ev)               ugly_hack_sleep_on_timeout(&(ev), MAX_SCHEDULE_TIMEOUT)\n #define DSL_DRV_WAKEUP_EVENT(ev)             wake_up_interruptible(&(ev))\n #define DSL_DRV_TimeMSecGet()                DSL_DRV_ElapsedTimeMSecGet(0)\n #define DSL_WAIT(ms)   msleep(ms)\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-adsl/patches/150-linux_5.9.patch",
    "content": "--- a/src/common/drv_dsl_cpe_os_linux.c\n+++ b/src/common/drv_dsl_cpe_os_linux.c\n@@ -417,7 +417,11 @@ int DSL_DRV_ErrorToOS(DSL_Error_t nError\n DSL_void_t* DSL_DRV_VMalloc(\n    DSL_DRV_size_t    nSize)\n {\n+#if LINUX_VERSION_CODE < KERNEL_VERSION(5,9,0)\n    return __vmalloc((unsigned long)nSize, GFP_KERNEL, PAGE_KERNEL);\n+#else\n+   return __vmalloc((unsigned long)nSize, GFP_KERNEL);\n+#endif\n    /*   return vmalloc(nSize);*/\n }\n \n"
  },
  {
    "path": "package/kernel/lantiq/ltq-adsl/patches/200-fix-elapsed-time.patch",
    "content": "--- a/src/include/drv_dsl_cpe_pm_core.h\n+++ b/src/include/drv_dsl_cpe_pm_core.h\n@@ -1525,9 +1525,9 @@ typedef struct\n    DSL_boolean_t bShowtimeProcessingStart;\n    /** Showtime reached flag*/\n    DSL_boolean_t bShowtimeInvTrigger;\n-   /** Current Showtime synchronization time to be used, (msec) */\n+   /** Current Showtime synchronization time to be used, (sec) */\n    DSL_uint32_t nCurrShowtimeTime;\n-   /** Showtime synchronization time to be used, (msec) */\n+   /** Showtime synchronization time to be used, (sec) */\n    DSL_uint32_t nElapsedShowtimeTime;\n    /** Actual Line state*/\n    DSL_LineStateValue_t nLineState;\n--- a/src/pm/drv_dsl_cpe_api_pm.c\n+++ b/src/pm/drv_dsl_cpe_api_pm.c\n@@ -1445,7 +1445,7 @@ DSL_Error_t DSL_DRV_PM_ChannelCountersTo\n    }\n \n    /* Fill Total Counters elapsed time*/\n-   pCounters->total.nElapsedTime = DSL_DRV_PM_CONTEXT(pContext)->nPmTotalElapsedTime/DSL_PM_MSEC;\n+   pCounters->total.nElapsedTime = DSL_DRV_PM_CONTEXT(pContext)->nPmTotalElapsedTime;\n \n    pChCounters = DSL_DRV_PM_PTR_CHANNEL_COUNTERS_TOTAL(pCounters->nChannel,pCounters->nDirection);\n \n@@ -1501,7 +1501,7 @@ DSL_Error_t DSL_DRV_PM_ChannelCountersEx\n    }\n \n    /* Fill Total Counters elapsed time*/\n-   pCounters->total.nElapsedTime = DSL_DRV_PM_CONTEXT(pContext)->nPmTotalElapsedTime/DSL_PM_MSEC;\n+   pCounters->total.nElapsedTime = DSL_DRV_PM_CONTEXT(pContext)->nPmTotalElapsedTime;\n \n    pChCounters = DSL_DRV_PM_PTR_CHANNEL_COUNTERS_TOTAL_EXT(pCounters->nChannel);\n \n@@ -2418,7 +2418,7 @@ DSL_Error_t DSL_DRV_PM_DataPathCountersT\n    }\n \n    /* Fill Total Counters elapsed time*/\n-   pCounters->total.nElapsedTime = DSL_DRV_PM_CONTEXT(pContext)->nPmTotalElapsedTime/DSL_PM_MSEC;\n+   pCounters->total.nElapsedTime = DSL_DRV_PM_CONTEXT(pContext)->nPmTotalElapsedTime;\n \n    pDpCounters = DSL_DRV_PM_PTR_DATAPATH_COUNTERS_TOTAL(pCounters->nChannel,pCounters->nDirection);\n \n@@ -3190,7 +3190,7 @@ DSL_Error_t DSL_DRV_PM_DataPathFailureCo\n    }\n \n    /* Fill Total Counters elapsed time*/\n-   pCounters->total.nElapsedTime = DSL_DRV_PM_CONTEXT(pContext)->nPmTotalElapsedTime/DSL_PM_MSEC;\n+   pCounters->total.nElapsedTime = DSL_DRV_PM_CONTEXT(pContext)->nPmTotalElapsedTime;\n \n    pDpCounters = DSL_DRV_PM_PTR_DATAPATH_FAILURE_COUNTERS_TOTAL(pCounters->nChannel,pCounters->nDirection);\n \n@@ -3950,7 +3950,7 @@ DSL_Error_t DSL_DRV_PM_LineSecCountersTo\n    }\n \n    /* Fill Total Counters elapsed time*/\n-   pCounters->total.nElapsedTime = DSL_DRV_PM_CONTEXT(pContext)->nPmTotalElapsedTime/DSL_PM_MSEC;\n+   pCounters->total.nElapsedTime = DSL_DRV_PM_CONTEXT(pContext)->nPmTotalElapsedTime;\n \n    pLineCounters = DSL_DRV_PM_PTR_LINE_SEC_COUNTERS_TOTAL(pCounters->nDirection);\n \n@@ -4602,7 +4602,7 @@ DSL_Error_t DSL_DRV_PM_LineInitCountersT\n    }\n \n    /* Fill Total Counters elapsed time*/\n-   pCounters->total.nElapsedTime = DSL_DRV_PM_CONTEXT(pContext)->nPmTotalElapsedTime/DSL_PM_MSEC;\n+   pCounters->total.nElapsedTime = DSL_DRV_PM_CONTEXT(pContext)->nPmTotalElapsedTime;\n \n    pLinitCounters = DSL_DRV_PM_PTR_LINE_INIT_COUNTERS_TOTAL();\n \n@@ -5131,7 +5131,7 @@ DSL_Error_t DSL_DRV_PM_LineEventShowtime\n    }\n \n    /* Fill Total Counters elapsed time*/\n-   pCounters->total.nElapsedTime = DSL_DRV_PM_CONTEXT(pContext)->nPmTotalElapsedTime/DSL_PM_MSEC;\n+   pCounters->total.nElapsedTime = DSL_DRV_PM_CONTEXT(pContext)->nPmTotalElapsedTime;\n \n    pLfCounters = DSL_DRV_PM_PTR_LINE_EVENT_SHOWTIME_COUNTERS_TOTAL(pCounters->nDirection);\n \n@@ -5670,7 +5670,7 @@ DSL_Error_t DSL_DRV_PM_ReTxCountersTotal\n    }\n \n    /* Fill Total Counters elapsed time*/\n-   pCounters->total.nElapsedTime = DSL_DRV_PM_CONTEXT(pContext)->nPmTotalElapsedTime/DSL_PM_MSEC;\n+   pCounters->total.nElapsedTime = DSL_DRV_PM_CONTEXT(pContext)->nPmTotalElapsedTime;\n \n    pReTxCounters = DSL_DRV_PM_PTR_RETX_COUNTERS_TOTAL(pCounters->nDirection);\n \n--- a/src/pm/drv_dsl_cpe_pm_core.c\n+++ b/src/pm/drv_dsl_cpe_pm_core.c\n@@ -61,6 +61,7 @@ static DSL_Error_t DSL_DRV_PM_SyncTimeUp\n {\n    DSL_Error_t nErrCode = DSL_SUCCESS;\n    DSL_uint32_t msecTimeFrame = DSL_PM_COUNTER_POLLING_CYCLE,\n+                secTimeFrame = DSL_PM_COUNTER_POLLING_CYCLE/DSL_PM_MSEC,\n                 nCurrMsTime = 0;\n #ifdef INCLUDE_DSL_CPE_PM_HISTORY\n    DSL_uint32_t nCurrSysTime = 0, nPrevElapsedTime = 0;\n@@ -100,10 +101,13 @@ static DSL_Error_t DSL_DRV_PM_SyncTimeUp\n    {\n       /* Get elapsed time [msec] since the last entry*/\n       msecTimeFrame = nCurrMsTime  - DSL_DRV_PM_CONTEXT(pContext)->nLastMsTimeCheck;\n+\n+      /* Get elapsed time [sec] since the last entry*/\n+      secTimeFrame = (nCurrMsTime/DSL_PM_MSEC) - (DSL_DRV_PM_CONTEXT(pContext)->nLastMsTimeCheck/DSL_PM_MSEC);\n    }\n \n    /* Get Total Elapsed Time Since the PM module startup*/\n-   DSL_DRV_PM_CONTEXT(pContext)->nPmTotalElapsedTime += msecTimeFrame;\n+   DSL_DRV_PM_CONTEXT(pContext)->nPmTotalElapsedTime += secTimeFrame;\n \n    /* Set last time check to the current time*/\n    DSL_DRV_PM_CONTEXT(pContext)->nLastMsTimeCheck = nCurrMsTime;\n@@ -141,7 +145,7 @@ static DSL_Error_t DSL_DRV_PM_SyncTimeUp\n       else\n       {\n          /* Update current showtime elapsed time*/\n-         DSL_DRV_PM_CONTEXT(pContext)->nCurrShowtimeTime   += (msecTimeFrame/DSL_PM_MSEC);\n+         DSL_DRV_PM_CONTEXT(pContext)->nCurrShowtimeTime   += secTimeFrame;\n          DSL_DRV_PM_CONTEXT(pContext)->nElapsedShowtimeTime =\n             DSL_DRV_PM_CONTEXT(pContext)->nCurrShowtimeTime;\n       }\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-adsl-fw/Makefile",
    "content": "#\n# Copyright (C) 2011 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=ltq-adsl-fw\nPKG_VERSION:=0.1\nPKG_RELEASE:=1\n\nPKG_BUILD_DIR:=$(BUILD_DIR)/ltq-dsl-fw-$(PKG_VERSION)\nPKG_SOURCE:=ltq-dsl-fw-$(PKG_VERSION).tar.bz2\nPKG_SOURCE_URL:=https://sources.openwrt.org/\nPKG_HASH:=28676d41c4b76e5bf7a2c5eae106a61fb96b93eabc0cb71120575fff9997269f\nPKG_MAINTAINER:=John Crispin <john@phrozen.org>\n\nPKG_FLAGS:=nonshared\n\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine Package/kmod-ltq-adsl-fw-template\n  TITLE+=Firmware Annex-$(1) $(2)\n  SECTION:=sys\n  CATEGORY:=Kernel modules\n  SUBMENU:=Network Devices\n  VARIANT:= $(2)-fw-$(1)\n  SOC:=$(2)\n  ANNEX:=$(1)\n  URL:=http://www.lantiq.com/\n  DEPENDS:=@$(3) +kmod-ltq-adsl-$(2)\nendef\n\nPackage/kmod-ltq-adsl-danube-fw-a=$(call Package/kmod-ltq-adsl-fw-template,a,danube,(TARGET_lantiq_xway||TARGET_lantiq_xway_legacy))\nPackage/kmod-ltq-adsl-danube-fw-b=$(call Package/kmod-ltq-adsl-fw-template,b,danube,(TARGET_lantiq_xway||TARGET_lantiq_xway_legacy))\nPackage/kmod-ltq-adsl-ar9-fw-a=$(call Package/kmod-ltq-adsl-fw-template,a,ar9,TARGET_lantiq_xway)\nPackage/kmod-ltq-adsl-ar9-fw-b=$(call Package/kmod-ltq-adsl-fw-template,b,ar9,TARGET_lantiq_xway)\nPackage/kmod-ltq-adsl-ase-fw-a=$(call Package/kmod-ltq-adsl-fw-template,a,ase,TARGET_lantiq_ase)\nPackage/kmod-ltq-adsl-ase-fw-b=$(call Package/kmod-ltq-adsl-fw-template,b,ase,TARGET_lantiq_ase)\n\ndefine Build/Compile\nendef\n\ndefine Package/kmod-ltq-adsl-$(BUILD_VARIANT)/install\n\t$(INSTALL_DIR) $(1)/lib/firmware/\n\t$(CP) $(PKG_BUILD_DIR)/ltq-dsl-fw-$(ANNEX)-$(SOC).bin $(1)/lib/firmware/\n\tln -s /lib/firmware/ltq-dsl-fw-$(ANNEX)-$(SOC).bin $(1)/lib/firmware/adsl.bin\nendef\n\n$(eval $(call BuildPackage,kmod-ltq-adsl-danube-fw-a))\n$(eval $(call BuildPackage,kmod-ltq-adsl-danube-fw-b))\n$(eval $(call BuildPackage,kmod-ltq-adsl-ase-fw-a))\n$(eval $(call BuildPackage,kmod-ltq-adsl-ase-fw-b))\n$(eval $(call BuildPackage,kmod-ltq-adsl-ar9-fw-a))\n$(eval $(call BuildPackage,kmod-ltq-adsl-ar9-fw-b))\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-adsl-mei/Makefile",
    "content": "# Copyright (C) 2012 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n\ninclude $(TOPDIR)/rules.mk\ninclude $(INCLUDE_DIR)/kernel.mk\n\nPKG_NAME:=ltq-adsl-mei\nPKG_RELEASE:=1\n\nPKG_MAINTAINER:=John Crispin <john@phrozen.org>\nPKG_CHECK_FORMAT_SECURITY:=0\n\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine KernelPackage/ltq-adsl-mei-template\n  SECTION:=sys\n  CATEGORY:=Kernel modules\n  SUBMENU:=Network Devices\n  TITLE:=mei driver for $(1)\n  URL:=http://www.lantiq.com/\n  VARIANT:=$(1)\n  DEPENDS:=@$(2)\n  FILES:=$(PKG_BUILD_DIR)/drv_mei_cpe.ko\n  AUTOLOAD:=$(call AutoLoad,50,drv_mei_cpe)\nendef\n\nKernelPackage/ltq-adsl-danube-mei=$(call KernelPackage/ltq-adsl-mei-template,danube,(TARGET_lantiq_xway||TARGET_lantiq_xway_legacy))\nKernelPackage/ltq-adsl-ar9-mei=$(call KernelPackage/ltq-adsl-mei-template,ar9,TARGET_lantiq_xway)\nKernelPackage/ltq-adsl-ase-mei=$(call KernelPackage/ltq-adsl-mei-template,ase,TARGET_lantiq_ase)\n\ndefine Build/Configure\nendef\n\ndefine Build/Compile\n\tcd $(LINUX_DIR); \\\n\t\tARCH=mips CROSS_COMPILE=\"$(KERNEL_CROSS)\" \\\n\t\t$(MAKE) BUILD_VARIANT=$(BUILD_VARIANT) M=$(PKG_BUILD_DIR)/ V=1 modules\nendef\n\n$(eval $(call KernelPackage,ltq-adsl-danube-mei))\n$(eval $(call KernelPackage,ltq-adsl-ase-mei))\n$(eval $(call KernelPackage,ltq-adsl-ar9-mei))\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-adsl-mei/src/Makefile",
    "content": "ifeq ($(BUILD_VARIANT),danube)\n  CFLAGS_MODULE = -DCONFIG_DANUBE -DCONFIG_IFXMIPS_DSL_CPE_MEI\nendif\n\nifeq ($(BUILD_VARIANT),ase)\n  CFLAGS_MODULE = -DCONFIG_AMAZON_SE -DCONFIG_IFXMIPS_DSL_CPE_MEI\nendif\n\nifeq ($(BUILD_VARIANT),ar9)\n  CFLAGS_MODULE = -DCONFIG_AR9 -DCONFIG_IFXMIPS_DSL_CPE_MEI\nendif\n\nobj-m = drv_mei_cpe.o\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-adsl-mei/src/drv_mei_cpe.c",
    "content": "/******************************************************************************\n\n                               Copyright (c) 2009\n                            Infineon Technologies AG\n                     Am Campeon 1-12; 81726 Munich, Germany\n\n  For licensing information, see the file 'LICENSE' in the root folder of\n  this software module.\n\n******************************************************************************/\n\n/*!\n  \\defgroup AMAZON_S_MEI Amazon-S MEI Driver Module\n  \\brief Amazon-S MEI driver module\n */\n\n/*!\n  \\defgroup Internal Compile Parametere\n  \\ingroup AMAZON_S_MEI\n  \\brief exported functions for other driver use\n */\n\n/*!\n  \\file amazon_s_mei_bsp.c\n  \\ingroup AMAZON_S_MEI\n  \\brief Amazon-S MEI driver file\n */\n\n#include <linux/kernel.h>\n#include <linux/module.h>\n#include <linux/version.h>\n#include <generated/utsrelease.h>\n#include <linux/types.h>\n#include <linux/fs.h>\n#include <linux/mm.h>\n#include <linux/errno.h>\n#include <linux/interrupt.h>\n#include <linux/netdevice.h>\n#include <linux/etherdevice.h>\n#include <linux/proc_fs.h>\n#include <linux/init.h>\n#include <linux/ioport.h>\n#include <linux/delay.h>\n#include <linux/device.h>\n#include <linux/sched.h>\n#include <linux/platform_device.h>\n#include <asm/uaccess.h>\n#include <asm/hardirq.h>\n\n#include \"lantiq_atm.h\"\n#include <lantiq_soc.h>\n//#include \"ifxmips_atm.h\"\n#define IFX_MEI_BSP\n#include \"ifxmips_mei_interface.h\"\n\n/*#define LTQ_RCU_RST                   IFX_RCU_RST_REQ\n#define LTQ_RCU_RST_REQ_ARC_JTAG      IFX_RCU_RST_REQ_ARC_JTAG\n#define LTQ_RCU_RST_REQ_DFE\t\t  IFX_RCU_RST_REQ_DFE\n#define LTQ_RCU_RST_REQ_AFE\t\t  IFX_RCU_RST_REQ_AFE\n#define IFXMIPS_FUSE_BASE_ADDR            IFX_FUSE_BASE_ADDR\n#define IFXMIPS_ICU_IM0_IER               IFX_ICU_IM0_IER\n#define IFXMIPS_ICU_IM2_IER               IFX_ICU_IM2_IER\n#define LTQ_MEI_INT                   IFX_MEI_INT\n#define LTQ_MEI_DYING_GASP_INT        IFX_MEI_DYING_GASP_INT\n#define LTQ_MEI_BASE_ADDR  \t\t  IFX_MEI_SPACE_ACCESS\n#define IFXMIPS_PMU_PWDCR\t\t  IFX_PMU_PWDCR\n#define IFXMIPS_MPS_CHIPID                IFX_MPS_CHIPID\n\n#define ifxmips_port_reserve_pin \t  ifx_gpio_pin_reserve\n#define ifxmips_port_set_dir_in\t\t  ifx_gpio_dir_in_set\n#define ifxmips_port_clear_altsel0        ifx_gpio_altsel0_set\n#define ifxmips_port_clear_altsel1 \t  ifx_gpio_altsel1_clear\n#define ifxmips_port_set_open_drain       ifx_gpio_open_drain_clear\n#define ifxmips_port_free_pin\t\t  ifx_gpio_pin_free\n#define ifxmips_mask_and_ack_irq\t  bsp_mask_and_ack_irq\n#define IFXMIPS_MPS_CHIPID_VERSION_GET    IFX_MCD_CHIPID_VERSION_GET\n#define ltq_r32(reg)                        __raw_readl(reg)\n#define ltq_w32(val, reg)                   __raw_writel(val, reg)\n#define ltq_w32_mask(clear, set, reg)       ltq_w32((ltq_r32(reg) & ~clear) | set, reg)\n*/\n\n#define LTQ_RCU_BASE_ADDR       0x1F203000\n#define LTQ_ICU_BASE_ADDR       0x1F880200\n#define LTQ_MEI_BASE_ADDR       0x1E116000\n#define LTQ_PMU_BASE_ADDR       0x1F102000\n\n\n#ifdef CONFIG_DANUBE\n# define LTQ_MEI_INT             (INT_NUM_IM1_IRL0 + 23)\n# define LTQ_MEI_DYING_GASP_INT  (INT_NUM_IM1_IRL0 + 21)\n# define LTQ_USB_OC_INT          (INT_NUM_IM4_IRL0 + 23)\n#endif\n\n#ifdef CONFIG_AMAZON_SE\n# define LTQ_MEI_INT             (INT_NUM_IM2_IRL0 + 9)\n# define LTQ_MEI_DYING_GASP_INT  (INT_NUM_IM2_IRL0 + 11)\n# define LTQ_USB_OC_INT          (INT_NUM_IM2_IRL0 + 20)\n#endif\n\n#ifdef CONFIG_AR9\n# define LTQ_MEI_INT             (INT_NUM_IM1_IRL0 + 23)\n# define LTQ_MEI_DYING_GASP_INT  (INT_NUM_IM1_IRL0 + 21)\n# define LTQ_USB_OC_INT          (INT_NUM_IM1_IRL0 + 28)\n#endif\n\n#ifndef LTQ_MEI_INT\n#error \"Unknown Lantiq ARCH!\"\n#endif\n\n#define LTQ_RCU_RST_REQ_DFE\t\t(1 << 7)\n#define LTQ_RCU_RST_REQ_AFE\t\t(1 << 11)\n\n#define LTQ_PMU_BASE\t\t(KSEG1 + LTQ_PMU_BASE_ADDR)\n#define LTQ_RCU_BASE\t\t(KSEG1 + LTQ_RCU_BASE_ADDR)\n#define LTQ_ICU_BASE\t\t(KSEG1 + LTQ_ICU_BASE_ADDR)\n\n#define LTQ_PMU_PWDCR        ((u32 *)(LTQ_PMU_BASE + 0x001C))\n#define LTQ_PMU_PWDSR        ((u32 *)(LTQ_PMU_BASE + 0x0020))\n#define LTQ_RCU_RST          ((u32 *)(LTQ_RCU_BASE + 0x0010))\n#define LTQ_RCU_RST_ALL      0x40000000\n\n#define LTQ_ICU_IM0_ISR      ((u32 *)(LTQ_ICU_BASE + 0x0000))\n#define LTQ_ICU_IM0_IER      ((u32 *)(LTQ_ICU_BASE + 0x0008))\n#define LTQ_ICU_IM0_IOSR     ((u32 *)(LTQ_ICU_BASE + 0x0010))\n#define LTQ_ICU_IM0_IRSR     ((u32 *)(LTQ_ICU_BASE + 0x0018))\n#define LTQ_ICU_IM0_IMR      ((u32 *)(LTQ_ICU_BASE + 0x0020))\n\n\n#define LTQ_ICU_IM1_ISR      ((u32 *)(LTQ_ICU_BASE + 0x0028))\n#define LTQ_ICU_IM2_ISR      ((u32 *)(LTQ_ICU_BASE + 0x0050))\n#define LTQ_ICU_IM3_ISR      ((u32 *)(LTQ_ICU_BASE + 0x0078))\n#define LTQ_ICU_IM4_ISR      ((u32 *)(LTQ_ICU_BASE + 0x00A0))\n\n#define LTQ_ICU_OFFSET       (LTQ_ICU_IM1_ISR - LTQ_ICU_IM0_ISR)\n#define LTQ_ICU_IM2_IER\t\t(LTQ_ICU_IM0_IER + LTQ_ICU_OFFSET)\n\n#define IFX_MEI_EMSG(fmt, args...) pr_err(\"[%s %d]: \" fmt,__FUNCTION__, __LINE__, ## args)\n#define IFX_MEI_DMSG(fmt, args...) pr_debug(\"[%s %d]: \" fmt,__FUNCTION__, __LINE__, ## args)\n\n#define LTQ_FUSE_BASE          (KSEG1 + 0x1F107354)\n\n#ifdef CONFIG_LTQ_MEI_FW_LOOPBACK\n//#define DFE_MEM_TEST\n//#define DFE_PING_TEST\n#define DFE_ATM_LOOPBACK\n\n\n#ifdef DFE_ATM_LOOPBACK\n#include <asm/ifxmips/ifxmips_mei_fw_loopback.h>\n#endif\n\nvoid dfe_loopback_irq_handler (DSL_DEV_Device_t *pDev);\n\n#endif //CONFIG_AMAZON_S_MEI_FW_LOOPBACK\n\nDSL_DEV_Version_t bsp_mei_version = {\n\tmajor:\t5,\n\tminor:\t0,\n\trevision:0\n};\nDSL_DEV_HwVersion_t bsp_chip_info;\n\n#define IFX_MEI_DEVNAME \"ifx_mei\"\n#define BSP_MAX_DEVICES 1\n#define MEI_DIRNAME \"ifxmips_mei\"\n\nDSL_DEV_MeiError_t DSL_BSP_FWDownload (DSL_DEV_Device_t *, const char *, unsigned long, long *, long *);\nDSL_DEV_MeiError_t DSL_BSP_Showtime (DSL_DEV_Device_t *, DSL_uint32_t, DSL_uint32_t);\nDSL_DEV_MeiError_t DSL_BSP_AdslLedInit (DSL_DEV_Device_t *, DSL_DEV_LedId_t, DSL_DEV_LedType_t, DSL_DEV_LedHandler_t);\n//DSL_DEV_MeiError_t DSL_BSP_AdslLedSet (DSL_DEV_Device_t *, DSL_DEV_LedId_t, DSL_DEV_LedMode_t);\nDSL_DEV_MeiError_t DSL_BSP_MemoryDebugAccess (DSL_DEV_Device_t *, DSL_BSP_MemoryAccessType_t, DSL_uint32_t, DSL_uint32_t*, DSL_uint32_t);\nDSL_DEV_MeiError_t DSL_BSP_SendCMV (DSL_DEV_Device_t *, u16 *, int, u16 *);\n\nint DSL_BSP_KernelIoctls (DSL_DEV_Device_t *, unsigned int, unsigned long);\n\nstatic DSL_DEV_MeiError_t IFX_MEI_RunAdslModem (DSL_DEV_Device_t *);\nstatic DSL_DEV_MeiError_t IFX_MEI_CpuModeSet (DSL_DEV_Device_t *, DSL_DEV_CpuMode_t);\nstatic DSL_DEV_MeiError_t IFX_MEI_DownloadBootCode (DSL_DEV_Device_t *);\nstatic DSL_DEV_MeiError_t IFX_MEI_ArcJtagEnable (DSL_DEV_Device_t *, int);\nstatic DSL_DEV_MeiError_t IFX_MEI_AdslMailboxIRQEnable (DSL_DEV_Device_t *, int);\n\nstatic int IFX_MEI_GetPage (DSL_DEV_Device_t *, u32, u32, u32, u32 *, u32 *);\nstatic int IFX_MEI_BarUpdate (DSL_DEV_Device_t *, int);\n\nstatic ssize_t IFX_MEI_Write (DSL_DRV_file_t *, const char *, size_t, loff_t *);\nstatic long IFX_MEI_UserIoctls (DSL_DRV_file_t *, unsigned int, unsigned long);\nstatic int IFX_MEI_Open (DSL_DRV_inode_t *, DSL_DRV_file_t *);\nstatic int IFX_MEI_Release (DSL_DRV_inode_t *, DSL_DRV_file_t *);\n\nvoid AMAZON_SE_MEI_ARC_MUX_Test(void);\n\nvoid IFX_MEI_ARC_MUX_Test(void);\n\nstatic int adsl_dummy_ledcallback(void);\n\nint (*ifx_mei_atm_showtime_enter)(struct port_cell_info *, void *) = NULL;\nEXPORT_SYMBOL(ifx_mei_atm_showtime_enter);\n\nint (*ifx_mei_atm_showtime_exit)(void) = NULL;\nEXPORT_SYMBOL(ifx_mei_atm_showtime_exit);\n\nstatic int (*g_adsl_ledcallback)(void) = adsl_dummy_ledcallback;\n\nstatic unsigned int g_tx_link_rate[2] = {0};\n\nstatic void *g_xdata_addr = NULL;\n\nstatic u32 *mei_arc_swap_buff = NULL;\t//  holding swap pages\n\nextern void ltq_mask_and_ack_irq(struct irq_data *d);\nstatic void inline MEI_MASK_AND_ACK_IRQ(int x)\n{\n\tstruct irq_data d;\n\td.hwirq = x;\n\tltq_mask_and_ack_irq(&d);\n}\n#define MEI_MAJOR\t105\nstatic int dev_major = MEI_MAJOR;\n\nstatic struct file_operations bsp_mei_operations = {\n      owner:THIS_MODULE,\n      open:IFX_MEI_Open,\n      release:IFX_MEI_Release,\n      write:IFX_MEI_Write,\n      unlocked_ioctl:IFX_MEI_UserIoctls,\n};\n\nstatic DSL_DEV_Device_t dsl_devices[BSP_MAX_DEVICES];\n\nstatic ifx_mei_device_private_t\n\tsDanube_Mei_Private[BSP_MAX_DEVICES];\n\nstatic DSL_BSP_EventCallBack_t dsl_bsp_event_callback[DSL_BSP_CB_LAST + 1];\n\n/**\n * Write a value to register\n * This function writes a value to danube register\n *\n * \\param  \tul_address\tThe address to write\n * \\param  \tul_data\t\tThe value to write\n * \\ingroup\tInternal\n */\nstatic void\nIFX_MEI_LongWordWrite (u32 ul_address, u32 ul_data)\n{\n\tIFX_MEI_WRITE_REGISTER_L (ul_data, ul_address);\n\twmb();\n\treturn;\n}\n\n/**\n * Write a value to register\n * This function writes a value to danube register\n *\n * \\param \tpDev\t\tthe device pointer\n * \\param  \tul_address\tThe address to write\n * \\param  \tul_data\t\tThe value to write\n * \\ingroup\tInternal\n */\nstatic void\nIFX_MEI_LongWordWriteOffset (DSL_DEV_Device_t * pDev, u32 ul_address,\n\t\t\t\t   u32 ul_data)\n{\n\tIFX_MEI_WRITE_REGISTER_L (ul_data, pDev->base_address + ul_address);\n\twmb();\n\treturn;\n}\n\n/**\n * Read the danube register\n * This function read the value from danube register\n *\n * \\param  \tul_address\tThe address to write\n * \\param  \tpul_data\tPointer to the data\n * \\ingroup\tInternal\n */\nstatic void\nIFX_MEI_LongWordRead (u32 ul_address, u32 * pul_data)\n{\n\t*pul_data = IFX_MEI_READ_REGISTER_L (ul_address);\n\trmb();\n\treturn;\n}\n\n/**\n * Read the danube register\n * This function read the value from danube register\n *\n * \\param \tpDev\t\tthe device pointer\n * \\param  \tul_address\tThe address to write\n * \\param  \tpul_data\tPointer to the data\n * \\ingroup\tInternal\n */\nstatic void\nIFX_MEI_LongWordReadOffset (DSL_DEV_Device_t * pDev, u32 ul_address,\n\t\t\t\t  u32 * pul_data)\n{\n\t*pul_data = IFX_MEI_READ_REGISTER_L (pDev->base_address + ul_address);\n\trmb();\n\treturn;\n}\n\n/**\n * Write several DWORD datas to ARC memory via ARC DMA interface\n * This function writes several DWORD datas to ARC memory via DMA interface.\n *\n * \\param \tpDev\t\tthe device pointer\n * \\param  \tdestaddr\tThe address to write\n * \\param  \tdatabuff\tPointer to the data buffer\n * \\param  \tdatabuffsize\tNumber of DWORDs to write\n * \\return\tDSL_DEV_MEI_ERR_SUCCESS or DSL_DEV_MEI_ERR_FAILURE\n * \\ingroup\tInternal\n */\nstatic DSL_DEV_MeiError_t\nIFX_MEI_DMAWrite (DSL_DEV_Device_t * pDev, u32 destaddr,\n\t\t\tu32 * databuff, u32 databuffsize)\n{\n\tu32 *p = databuff;\n\tu32 temp;\n\n\tif (destaddr & 3)\n\t\treturn DSL_DEV_MEI_ERR_FAILURE;\n\n\t//      Set the write transfer address\n\tIFX_MEI_LongWordWriteOffset (pDev, ME_DX_AD, destaddr);\n\n\t//      Write the data pushed across DMA\n\twhile (databuffsize--) {\n\t\ttemp = *p;\n\t\tif (destaddr == MEI_TO_ARC_MAILBOX)\n\t\t\tMEI_HALF_WORD_SWAP (temp);\n\t\tIFX_MEI_LongWordWriteOffset (pDev, (u32) ME_DX_DATA, temp);\n\t\tp++;\n\t}\n\n\treturn DSL_DEV_MEI_ERR_SUCCESS;\n\n}\n\n/**\n * Read several DWORD datas from ARC memory via ARC DMA interface\n * This function reads several DWORD datas from ARC memory via DMA interface.\n *\n * \\param \tpDev\t\tthe device pointer\n * \\param  \tsrcaddr\t\tThe address to read\n * \\param  \tdatabuff\tPointer to the data buffer\n * \\param  \tdatabuffsize\tNumber of DWORDs to read\n * \\return\tDSL_DEV_MEI_ERR_SUCCESS or DSL_DEV_MEI_ERR_FAILURE\n * \\ingroup\tInternal\n */\nstatic DSL_DEV_MeiError_t\nIFX_MEI_DMARead (DSL_DEV_Device_t * pDev, u32 srcaddr, u32 * databuff,\n\t\t       u32 databuffsize)\n{\n\tu32 *p = databuff;\n\tu32 temp;\n\n\tif (srcaddr & 3)\n\t\treturn DSL_DEV_MEI_ERR_FAILURE;\n\n\t//      Set the read transfer address\n\tIFX_MEI_LongWordWriteOffset (pDev, (u32) ME_DX_AD, srcaddr);\n\n\t//      Read the data popped across DMA\n\twhile (databuffsize--) {\n\t\tIFX_MEI_LongWordReadOffset (pDev, (u32) ME_DX_DATA, &temp);\n\t\tif (databuff == (u32 *) DSL_DEV_PRIVATE(pDev)->CMV_RxMsg)\t// swap half word\n\t\t\tMEI_HALF_WORD_SWAP (temp);\n\t\t*p = temp;\n\t\tp++;\n\t}\n\n\treturn DSL_DEV_MEI_ERR_SUCCESS;\n\n}\n\n/**\n * Switch the ARC control mode\n * This function switchs the ARC control mode to JTAG mode or MEI mode\n *\n * \\param \tpDev\t\tthe device pointer\n * \\param  \tmode\t\tThe mode want to switch: JTAG_MASTER_MODE or MEI_MASTER_MODE.\n * \\ingroup\tInternal\n */\nstatic void\nIFX_MEI_ControlModeSet (DSL_DEV_Device_t * pDev, int mode)\n{\n\tu32 temp = 0x0;\n\n\tIFX_MEI_LongWordReadOffset (pDev, (u32) ME_DBG_MASTER, &temp);\n\tswitch (mode) {\n\tcase JTAG_MASTER_MODE:\n\t\ttemp &= ~(HOST_MSTR);\n\t\tbreak;\n\tcase MEI_MASTER_MODE:\n\t\ttemp |= (HOST_MSTR);\n\t\tbreak;\n\tdefault:\n\t\tIFX_MEI_EMSG (\"IFX_MEI_ControlModeSet: unkonwn mode [%d]\\n\", mode);\n\t\treturn;\n\t}\n\tIFX_MEI_LongWordWriteOffset (pDev, (u32) ME_DBG_MASTER, temp);\n}\n\n/**\n * Disable ARC to MEI interrupt\n *\n * \\param \tpDev\t\tthe device pointer\n * \\ingroup\tInternal\n */\nstatic void\nIFX_MEI_IRQDisable (DSL_DEV_Device_t * pDev)\n{\n\tIFX_MEI_LongWordWriteOffset (pDev, (u32) ME_ARC2ME_MASK,  0x0);\n}\n\n/**\n * Eable ARC to MEI interrupt\n *\n * \\param \tpDev\t\tthe device pointer\n * \\ingroup\tInternal\n */\nstatic void\nIFX_MEI_IRQEnable (DSL_DEV_Device_t * pDev)\n{\n\tIFX_MEI_LongWordWriteOffset (pDev, (u32) ME_ARC2ME_MASK, MSGAV_EN);\n}\n\n/**\n * Poll for transaction complete signal\n * This function polls and waits for transaction complete signal.\n *\n * \\param \tpDev\t\tthe device pointer\n * \\ingroup\tInternal\n */\nstatic void\nmeiPollForDbgDone (DSL_DEV_Device_t * pDev)\n{\n\tu32 query = 0;\n\tint i = 0;\n\n\twhile (i < WHILE_DELAY) {\n\t\tIFX_MEI_LongWordReadOffset (pDev, (u32) ME_ARC2ME_STAT,  &query);\n\t\tquery &= (ARC_TO_MEI_DBG_DONE);\n\t\tif (query)\n\t\t\tbreak;\n\t\ti++;\n\t\tif (i == WHILE_DELAY) {\n\t\t\tIFX_MEI_EMSG (\"PollforDbg fail!\\n\");\n\t\t}\n\t}\n\tIFX_MEI_LongWordWriteOffset (pDev, (u32) ME_ARC2ME_STAT, ARC_TO_MEI_DBG_DONE);\t// to clear this interrupt\n}\n\n/**\n * ARC Debug Memory Access for a single DWORD reading.\n * This function used for direct, address-based access to ARC memory.\n *\n * \\param \tpDev\t\tthe device pointer\n * \\param  \tDEC_mode\tARC memory space to used\n * \\param  \taddress\t  \tAddress to read\n * \\param  \tdata\t  \tPointer to data\n * \\return\tDSL_DEV_MEI_ERR_SUCCESS or DSL_DEV_MEI_ERR_FAILURE\n * \\ingroup\tInternal\n */\nstatic DSL_DEV_MeiError_t\n_IFX_MEI_DBGLongWordRead (DSL_DEV_Device_t * pDev, u32 DEC_mode,\n\t\t\t\tu32 address, u32 * data)\n{\n\tIFX_MEI_LongWordWriteOffset (pDev, (u32) ME_DBG_DECODE, DEC_mode);\n\tIFX_MEI_LongWordWriteOffset (pDev, (u32) ME_DBG_RD_AD, address);\n\tmeiPollForDbgDone (pDev);\n\tIFX_MEI_LongWordReadOffset (pDev, (u32) ME_DBG_DATA, data);\n\treturn DSL_DEV_MEI_ERR_SUCCESS;\n}\n\n/**\n * ARC Debug Memory Access for a single DWORD writing.\n * This function used for direct, address-based access to ARC memory.\n *\n * \\param \tpDev\t\tthe device pointer\n * \\param  \tDEC_mode\tARC memory space to used\n * \\param  \taddress\t  \tThe address to write\n * \\param  \tdata\t  \tThe data to write\n * \\return\tDSL_DEV_MEI_ERR_SUCCESS or DSL_DEV_MEI_ERR_FAILURE\n * \\ingroup\tInternal\n */\nstatic DSL_DEV_MeiError_t\n_IFX_MEI_DBGLongWordWrite (DSL_DEV_Device_t * pDev, u32 DEC_mode,\n\t\t\t\t u32 address, u32 data)\n{\n\tIFX_MEI_LongWordWriteOffset (pDev, (u32) ME_DBG_DECODE, DEC_mode);\n\tIFX_MEI_LongWordWriteOffset (pDev, (u32) ME_DBG_WR_AD, address);\n\tIFX_MEI_LongWordWriteOffset (pDev, (u32) ME_DBG_DATA, data);\n\tmeiPollForDbgDone (pDev);\n\treturn DSL_DEV_MEI_ERR_SUCCESS;\n}\n\n/**\n * ARC Debug Memory Access for writing.\n * This function used for direct, address-based access to ARC memory.\n *\n * \\param \tpDev\t\tthe device pointer\n * \\param  \tdestaddr\tThe address to read\n * \\param  \tdatabuffer  \tPointer to data\n * \\param\tdatabuffsize\tThe number of DWORDs to read\n * \\return\tDSL_DEV_MEI_ERR_SUCCESS or DSL_DEV_MEI_ERR_FAILURE\n * \\ingroup\tInternal\n */\n\nstatic DSL_DEV_MeiError_t\nIFX_MEI_DebugWrite (DSL_DEV_Device_t * pDev, u32 destaddr,\n\t\t\t  u32 * databuff, u32 databuffsize)\n{\n\tu32 i;\n\tu32 temp = 0x0;\n\tu32 address = 0x0;\n\tu32 *buffer = 0x0;\n\n\t//      Open the debug port before DMP memory write\n\tIFX_MEI_ControlModeSet (pDev, MEI_MASTER_MODE);\n\n\t//      For the requested length, write the address and write the data\n\taddress = destaddr;\n\tbuffer = databuff;\n\tfor (i = 0; i < databuffsize; i++) {\n\t\ttemp = *buffer;\n\t\t_IFX_MEI_DBGLongWordWrite (pDev, ME_DBG_DECODE_DMP1_MASK, address, temp);\n\t\taddress += 4;\n\t\tbuffer++;\n\t}\n\n\t//      Close the debug port after DMP memory write\n\tIFX_MEI_ControlModeSet (pDev, JTAG_MASTER_MODE);\n\n\treturn DSL_DEV_MEI_ERR_SUCCESS;\n}\n\n/**\n * ARC Debug Memory Access for reading.\n * This function used for direct, address-based access to ARC memory.\n *\n * \\param \tpDev\t\tthe device pointer\n * \\param  \tsrcaddr\t  \tThe address to read\n * \\param  \tdatabuffer  \tPointer to data\n * \\param\tdatabuffsize\tThe number of DWORDs to read\n * \\return\tDSL_DEV_MEI_ERR_SUCCESS or DSL_DEV_MEI_ERR_FAILURE\n * \\ingroup\tInternal\n */\nstatic DSL_DEV_MeiError_t\nIFX_MEI_DebugRead (DSL_DEV_Device_t * pDev, u32 srcaddr, u32 * databuff, u32 databuffsize)\n{\n\tu32 i;\n\tu32 temp = 0x0;\n\tu32 address = 0x0;\n\tu32 *buffer = 0x0;\n\n\t//      Open the debug port before DMP memory read\n\tIFX_MEI_ControlModeSet (pDev, MEI_MASTER_MODE);\n\n\t//      For the requested length, write the address and read the data\n\taddress = srcaddr;\n\tbuffer = databuff;\n\tfor (i = 0; i < databuffsize; i++) {\n\t\t_IFX_MEI_DBGLongWordRead (pDev, ME_DBG_DECODE_DMP1_MASK, address, &temp);\n\t\t*buffer = temp;\n\t\taddress += 4;\n\t\tbuffer++;\n\t}\n\n\t//      Close the debug port after DMP memory read\n\tIFX_MEI_ControlModeSet (pDev, JTAG_MASTER_MODE);\n\n\treturn DSL_DEV_MEI_ERR_SUCCESS;\n}\n\n/**\n * Send a message to ARC MailBox.\n * This function sends a message to ARC Mailbox via ARC DMA interface.\n *\n * \\param \tpDev\t\tthe device pointer\n * \\param  \tmsgsrcbuffer  \tPointer to message.\n * \\param\tmsgsize\t\tThe number of words to write.\n * \\return\tDSL_DEV_MEI_ERR_SUCCESS or DSL_DEV_MEI_ERR_FAILURE\n * \\ingroup\tInternal\n */\nstatic DSL_DEV_MeiError_t\nIFX_MEI_MailboxWrite (DSL_DEV_Device_t * pDev, u16 * msgsrcbuffer,\n\t\t\t    u16 msgsize)\n{\n\tint i;\n\tu32 arc_mailbox_status = 0x0;\n\tu32 temp = 0;\n\tDSL_DEV_MeiError_t meiMailboxError = DSL_DEV_MEI_ERR_SUCCESS;\n\n\t//      Write to mailbox\n\tmeiMailboxError =\n\t\tIFX_MEI_DMAWrite (pDev, MEI_TO_ARC_MAILBOX, (u32 *) msgsrcbuffer, msgsize / 2);\n\tmeiMailboxError =\n\t\tIFX_MEI_DMAWrite (pDev, MEI_TO_ARC_MAILBOXR, (u32 *) (&temp), 1);\n\n\t//      Notify arc that mailbox write completed\n\tDSL_DEV_PRIVATE(pDev)->cmv_waiting = 1;\n\tIFX_MEI_LongWordWriteOffset (pDev, (u32) ME_ME2ARC_INT, MEI_TO_ARC_MSGAV);\n\n\ti = 0;\n\twhile (i < WHILE_DELAY) {\t// wait for ARC to clear the bit\n\t\tIFX_MEI_LongWordReadOffset (pDev, (u32) ME_ME2ARC_INT, &arc_mailbox_status);\n\t\tif ((arc_mailbox_status & MEI_TO_ARC_MSGAV) != MEI_TO_ARC_MSGAV)\n\t\t\tbreak;\n\t\ti++;\n\t\tif (i == WHILE_DELAY) {\n\t\t\tIFX_MEI_EMSG (\">>> Timeout waiting for ARC to clear MEI_TO_ARC_MSGAV!!!\"\n\t\t\t      \" MEI_TO_ARC message size = %d DWORDs <<<\\n\", msgsize/2);\n\t\t\tmeiMailboxError = DSL_DEV_MEI_ERR_FAILURE;\n\t\t}\n\t}\n\n\treturn meiMailboxError;\n}\n\n/**\n * Read a message from ARC MailBox.\n * This function reads a message from ARC Mailbox via ARC DMA interface.\n *\n * \\param \tpDev\t\tthe device pointer\n * \\param  \tmsgsrcbuffer  \tPointer to message.\n * \\param\tmsgsize\t\tThe number of words to read\n * \\return\tDSL_DEV_MEI_ERR_SUCCESS or DSL_DEV_MEI_ERR_FAILURE\n * \\ingroup\tInternal\n */\nstatic DSL_DEV_MeiError_t\nIFX_MEI_MailboxRead (DSL_DEV_Device_t * pDev, u16 * msgdestbuffer,\n\t\t\t   u16 msgsize)\n{\n\tDSL_DEV_MeiError_t meiMailboxError = DSL_DEV_MEI_ERR_SUCCESS;\n\t//      Read from mailbox\n\tmeiMailboxError =\n\t\tIFX_MEI_DMARead (pDev, ARC_TO_MEI_MAILBOX, (u32 *) msgdestbuffer, msgsize / 2);\n\n\t//      Notify arc that mailbox read completed\n\tIFX_MEI_LongWordWriteOffset (pDev, (u32) ME_ARC2ME_STAT, ARC_TO_MEI_MSGAV);\n\n\treturn meiMailboxError;\n}\n\n/**\n * Download boot pages to ARC.\n * This function downloads boot pages to ARC.\n *\n * \\param \tpDev\t\tthe device pointer\n * \\return\tDSL_DEV_MEI_ERR_SUCCESS or DSL_DEV_MEI_ERR_FAILURE\n * \\ingroup\tInternal\n */\nstatic DSL_DEV_MeiError_t\nIFX_MEI_DownloadBootPages (DSL_DEV_Device_t * pDev)\n{\n\tint boot_loop;\n\tint page_size;\n\tu32 dest_addr;\n\n\t/*\n\t **     DMA the boot code page(s)\n\t */\n\n\tfor (boot_loop = 1;\n\t     boot_loop <\n\t     (DSL_DEV_PRIVATE(pDev)->img_hdr-> count); boot_loop++) {\n\t\tif ((DSL_DEV_PRIVATE(pDev)-> img_hdr->page[boot_loop].p_size) & BOOT_FLAG) {\n\t\t\tpage_size = IFX_MEI_GetPage (pDev, boot_loop,\n\t\t\t\t\t\t       GET_PROG, MAXSWAPSIZE,\n\t\t\t\t\t\t       mei_arc_swap_buff,\n\t\t\t\t\t\t       &dest_addr);\n\t\t\tif (page_size > 0) {\n\t\t\t\tIFX_MEI_DMAWrite (pDev, dest_addr,\n\t\t\t\t\t\t\tmei_arc_swap_buff,\n\t\t\t\t\t\t\tpage_size);\n\t\t\t}\n\t\t}\n\t\tif ((DSL_DEV_PRIVATE(pDev)-> img_hdr->page[boot_loop].d_size) & BOOT_FLAG) {\n\t\t\tpage_size = IFX_MEI_GetPage (pDev, boot_loop,\n\t\t\t\t\t\t       GET_DATA, MAXSWAPSIZE,\n\t\t\t\t\t\t       mei_arc_swap_buff,\n\t\t\t\t\t\t       &dest_addr);\n\t\t\tif (page_size > 0) {\n\t\t\t\tIFX_MEI_DMAWrite (pDev, dest_addr,\n\t\t\t\t\t\t\tmei_arc_swap_buff,\n\t\t\t\t\t\t\tpage_size);\n\t\t\t}\n\t\t}\n\t}\n\treturn DSL_DEV_MEI_ERR_SUCCESS;\n}\n\n/**\n * Initial efuse rar.\n **/\nstatic void\nIFX_MEI_FuseInit (DSL_DEV_Device_t * pDev)\n{\n\tu32 data = 0;\n\tIFX_MEI_DMAWrite (pDev, IRAM0_BASE, &data, 1);\n\tIFX_MEI_DMAWrite (pDev, IRAM0_BASE + 4, &data, 1);\n\tIFX_MEI_DMAWrite (pDev, IRAM1_BASE, &data, 1);\n\tIFX_MEI_DMAWrite (pDev, IRAM1_BASE + 4, &data, 1);\n\tIFX_MEI_DMAWrite (pDev, BRAM_BASE, &data, 1);\n\tIFX_MEI_DMAWrite (pDev, BRAM_BASE + 4, &data, 1);\n\tIFX_MEI_DMAWrite (pDev, ADSL_DILV_BASE, &data, 1);\n\tIFX_MEI_DMAWrite (pDev, ADSL_DILV_BASE + 4, &data, 1);\n}\n\n/**\n * efuse rar program\n **/\nstatic void\nIFX_MEI_FuseProg (DSL_DEV_Device_t * pDev)\n{\n\tu32 reg_data, fuse_value;\n\tint i = 0;\n\n\tIFX_MEI_LongWordRead ((u32) LTQ_RCU_RST, &reg_data);\n\twhile ((reg_data & 0x10000000) == 0) {\n\t\tIFX_MEI_LongWordRead ((u32) LTQ_RCU_RST,  &reg_data);\n\t\ti++;\n\t\t/* 0x4000 translate to  about 16 ms@111M, so should be enough */\n\t\tif (i == 0x4000)\n\t\t\treturn;\n\t}\n\t// STEP a: Prepare memory for external accesses\n\t// Write fuse_en bit24\n\tIFX_MEI_LongWordRead ((u32) LTQ_RCU_RST, &reg_data);\n\tIFX_MEI_LongWordWrite ((u32) LTQ_RCU_RST, reg_data | (1 << 24));\n\n\tIFX_MEI_FuseInit (pDev);\n\tfor (i = 0; i < 4; i++) {\n\t\tIFX_MEI_LongWordRead ((u32) (LTQ_FUSE_BASE) + i * 4, &fuse_value);\n\t\tswitch (fuse_value & 0xF0000) {\n\t\tcase 0x80000:\n\t\t\treg_data = ((fuse_value & RX_DILV_ADDR_BIT_MASK) |\n\t\t\t\t (RX_DILV_ADDR_BIT_MASK + 0x1));\n\t\t\tIFX_MEI_DMAWrite (pDev, ADSL_DILV_BASE, &reg_data, 1);\n\t\t\tbreak;\n\t\tcase 0x90000:\n\t\t\treg_data = ((fuse_value & RX_DILV_ADDR_BIT_MASK) |\n\t\t\t\t (RX_DILV_ADDR_BIT_MASK + 0x1));\n\t\t\tIFX_MEI_DMAWrite (pDev, ADSL_DILV_BASE + 4, &reg_data, 1);\n\t\t\tbreak;\n\t\tcase 0xA0000:\n\t\t\treg_data = ((fuse_value & IRAM0_ADDR_BIT_MASK) |\n\t\t\t\t (IRAM0_ADDR_BIT_MASK + 0x1));\n\t\t\tIFX_MEI_DMAWrite (pDev, IRAM0_BASE, &reg_data, 1);\n\t\t\tbreak;\n\t\tcase 0xB0000:\n\t\t\treg_data = ((fuse_value & IRAM0_ADDR_BIT_MASK) |\n\t\t\t\t (IRAM0_ADDR_BIT_MASK + 0x1));\n\t\t\tIFX_MEI_DMAWrite (pDev, IRAM0_BASE + 4, &reg_data, 1);\n\t\t\tbreak;\n\t\tcase 0xC0000:\n\t\t\treg_data = ((fuse_value & IRAM1_ADDR_BIT_MASK) |\n\t\t\t\t (IRAM1_ADDR_BIT_MASK + 0x1));\n\t\t\tIFX_MEI_DMAWrite (pDev, IRAM1_BASE, &reg_data, 1);\n\t\t\tbreak;\n\t\tcase 0xD0000:\n\t\t\treg_data = ((fuse_value & IRAM1_ADDR_BIT_MASK) |\n\t\t\t\t (IRAM1_ADDR_BIT_MASK + 0x1));\n\t\t\tIFX_MEI_DMAWrite (pDev, IRAM1_BASE + 4, &reg_data, 1);\n\t\t\tbreak;\n\t\tcase 0xE0000:\n\t\t\treg_data = ((fuse_value & BRAM_ADDR_BIT_MASK) |\n\t\t\t\t (BRAM_ADDR_BIT_MASK + 0x1));\n\t\t\tIFX_MEI_DMAWrite (pDev, BRAM_BASE, &reg_data, 1);\n\t\t\tbreak;\n\t\tcase 0xF0000:\n\t\t\treg_data = ((fuse_value & BRAM_ADDR_BIT_MASK) |\n\t\t\t\t (BRAM_ADDR_BIT_MASK + 0x1));\n\t\t\tIFX_MEI_DMAWrite (pDev, BRAM_BASE + 4, &reg_data, 1);\n\t\t\tbreak;\n\t\tdefault:\t// PPE efuse\n\t\t\tbreak;\n\t\t}\n\t}\n\tIFX_MEI_LongWordRead ((u32) LTQ_RCU_RST, &reg_data);\n\tIFX_MEI_LongWordWrite ((u32) LTQ_RCU_RST, reg_data & ~(1 << 24));\n\tIFX_MEI_LongWordRead ((u32) LTQ_RCU_RST, &reg_data);\n}\n\n/**\n * Enable DFE Clock\n * This function enables DFE Clock\n *\n * \\param \tpDev\t\tthe device pointer\n * \\return\tDSL_DEV_MEI_ERR_SUCCESS or DSL_DEV_MEI_ERR_FAILURE\n * \\ingroup\tInternal\n */\nstatic DSL_DEV_MeiError_t\nIFX_MEI_EnableCLK (DSL_DEV_Device_t * pDev)\n{\n\tu32 arc_debug_data = 0;\n\tIFX_MEI_ControlModeSet (pDev, MEI_MASTER_MODE);\n\t//enable ac_clk signal\n\t_IFX_MEI_DBGLongWordRead (pDev, ME_DBG_DECODE_DMP1_MASK,\n\t\t\t\t\tCRI_CCR0, &arc_debug_data);\n\tarc_debug_data |= ACL_CLK_MODE_ENABLE;\n\t_IFX_MEI_DBGLongWordWrite (pDev, ME_DBG_DECODE_DMP1_MASK,\n\t\t\t\t\t CRI_CCR0, arc_debug_data);\n\tIFX_MEI_ControlModeSet (pDev, JTAG_MASTER_MODE);\n\treturn DSL_DEV_MEI_ERR_SUCCESS;\n}\n\n/**\n * Halt the ARC.\n * This function halts the ARC.\n *\n * \\param \tpDev\t\tthe device pointer\n * \\return\tDSL_DEV_MEI_ERR_SUCCESS or DSL_DEV_MEI_ERR_FAILURE\n * \\ingroup\tInternal\n */\nstatic DSL_DEV_MeiError_t\nIFX_MEI_HaltArc (DSL_DEV_Device_t * pDev)\n{\n\tu32 arc_debug_data = 0x0;\n\n\t//      Switch arc control from JTAG mode to MEI mode\n\tIFX_MEI_ControlModeSet (pDev, MEI_MASTER_MODE);\n\t_IFX_MEI_DBGLongWordRead (pDev, MEI_DEBUG_DEC_AUX_MASK,\n\t\t\t\t\tARC_DEBUG, &arc_debug_data);\n\tarc_debug_data |= ARC_DEBUG_HALT;\n\t_IFX_MEI_DBGLongWordWrite (pDev, MEI_DEBUG_DEC_AUX_MASK,\n\t\t\t\t\t ARC_DEBUG, arc_debug_data);\n\t//      Switch arc control from MEI mode to JTAG mode\n\tIFX_MEI_ControlModeSet (pDev, JTAG_MASTER_MODE);\n\n\tMEI_WAIT (10);\n\n\treturn DSL_DEV_MEI_ERR_SUCCESS;\n}\n\n/**\n * Run the ARC.\n * This function runs the ARC.\n *\n * \\param \tpDev\t\tthe device pointer\n * \\return\tDSL_DEV_MEI_ERR_SUCCESS or DSL_DEV_MEI_ERR_FAILURE\n * \\ingroup\tInternal\n */\nstatic DSL_DEV_MeiError_t\nIFX_MEI_RunArc (DSL_DEV_Device_t * pDev)\n{\n\tu32 arc_debug_data = 0x0;\n\n\t//      Switch arc control from JTAG mode to MEI mode- write '1' to bit0\n\tIFX_MEI_ControlModeSet (pDev, MEI_MASTER_MODE);\n\t_IFX_MEI_DBGLongWordRead (pDev, MEI_DEBUG_DEC_AUX_MASK,\n\t\t\t\t\tAUX_STATUS, &arc_debug_data);\n\n\t//      Write debug data reg with content ANDd with 0xFDFFFFFF (halt bit cleared)\n\tarc_debug_data &= ~ARC_AUX_HALT;\n\t_IFX_MEI_DBGLongWordWrite (pDev, MEI_DEBUG_DEC_AUX_MASK,\n\t\t\t\t\t AUX_STATUS, arc_debug_data);\n\n\t//      Switch arc control from MEI mode to JTAG mode- write '0' to bit0\n\tIFX_MEI_ControlModeSet (pDev, JTAG_MASTER_MODE);\n\t//      Enable mask for arc codeswap interrupts\n\tIFX_MEI_IRQEnable (pDev);\n\n\treturn DSL_DEV_MEI_ERR_SUCCESS;\n\n}\n\n/**\n * Reset the ARC.\n * This function resets the ARC.\n *\n * \\param \tpDev\t\tthe device pointer\n * \\return\tDSL_DEV_MEI_ERR_SUCCESS or DSL_DEV_MEI_ERR_FAILURE\n * \\ingroup\tInternal\n */\nstatic DSL_DEV_MeiError_t\nIFX_MEI_ResetARC (DSL_DEV_Device_t * pDev)\n{\n\tu32 arc_debug_data = 0;\n\n\tIFX_MEI_HaltArc (pDev);\n\n\tIFX_MEI_LongWordRead ((u32) LTQ_RCU_RST, &arc_debug_data);\n\tIFX_MEI_LongWordWrite ((u32) LTQ_RCU_RST,\n\t\tarc_debug_data | LTQ_RCU_RST_REQ_DFE | LTQ_RCU_RST_REQ_AFE);\n\n\t// reset ARC\n\tIFX_MEI_LongWordWriteOffset (pDev, (u32) ME_RST_CTRL, MEI_SOFT_RESET);\n\tIFX_MEI_LongWordWriteOffset (pDev, (u32) ME_RST_CTRL, 0);\n\n\tIFX_MEI_IRQDisable (pDev);\n\n\tIFX_MEI_EnableCLK (pDev);\n\n#if 0\n\t// reset part of PPE\n\t*(unsigned long *) (BSP_PPE32_SRST) = 0xC30;\n\t*(unsigned long *) (BSP_PPE32_SRST) = 0xFFF;\n#endif\n\n\tDSL_DEV_PRIVATE(pDev)->modem_ready = 0;\n\n\treturn DSL_DEV_MEI_ERR_SUCCESS;\n}\n\nDSL_DEV_MeiError_t\nDSL_BSP_Showtime (DSL_DEV_Device_t * dev, DSL_uint32_t rate_fast, DSL_uint32_t rate_intl)\n{\n    struct port_cell_info port_cell = {0};\n\n\tIFX_MEI_EMSG (\"Datarate US intl = %d, fast = %d\\n\", (int)rate_intl,\n\t\t\t    (int)rate_fast);\n\n    if ( rate_fast )\n        g_tx_link_rate[0] = rate_fast / (53 * 8);\n    if ( rate_intl )\n        g_tx_link_rate[1] = rate_intl / (53 * 8);\n\n    if ( g_tx_link_rate[0] == 0 && g_tx_link_rate[1] == 0 ) {\n        IFX_MEI_EMSG (\"Got rate fail.\\n\");\n    }\n\n\tif ( ifx_mei_atm_showtime_enter )\n\t{\n\t    port_cell.port_num = 2;\n\t    port_cell.tx_link_rate[0] = g_tx_link_rate[0];\n\t    port_cell.tx_link_rate[1] = g_tx_link_rate[1];\n        ifx_mei_atm_showtime_enter(&port_cell, g_xdata_addr);\n\t}\n\telse\n\t{\n\t\tIFX_MEI_EMSG(\"no hookup from ATM driver to set cell rate\\n\");\n\t}\n\n\treturn DSL_DEV_MEI_ERR_SUCCESS;\n};\n\n/**\n * Reset/halt/run the DFE.\n * This function provide operations to reset/halt/run the DFE.\n *\n * \\param \tpDev\t\tthe device pointer\n * \\param\tmode\t\twhich operation want to do\n * \\return\tDSL_DEV_MEI_ERR_SUCCESS or DSL_DEV_MEI_ERR_FAILURE\n * \\ingroup\tInternal\n */\nstatic DSL_DEV_MeiError_t\nIFX_MEI_CpuModeSet (DSL_DEV_Device_t *pDev,\n\t\t\t  DSL_DEV_CpuMode_t mode)\n{\n\tDSL_DEV_MeiError_t err_ret = DSL_DEV_MEI_ERR_FAILURE;\n\tswitch (mode) {\n\tcase DSL_CPU_HALT:\n\t\terr_ret = IFX_MEI_HaltArc (pDev);\n\t\tbreak;\n\tcase DSL_CPU_RUN:\n\t\terr_ret = IFX_MEI_RunArc (pDev);\n\t\tbreak;\n\tcase DSL_CPU_RESET:\n\t\terr_ret = IFX_MEI_ResetARC (pDev);\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\treturn err_ret;\n}\n\n/**\n * Accress DFE memory.\n * This function provide a way to access DFE memory;\n *\n * \\param \tpDev\t\tthe device pointer\n * \\param\ttype\t\tread or write\n * \\param\tdestaddr\tdestination address\n * \\param\tdatabuff\tpointer to hold data\n * \\param\tdatabuffsize\tsize want to read/write\n * \\return\tDSL_DEV_MEI_ERR_SUCCESS or DSL_DEV_MEI_ERR_FAILURE\n * \\ingroup\tInternal\n */\nDSL_DEV_MeiError_t\nDSL_BSP_MemoryDebugAccess (DSL_DEV_Device_t * pDev,\n\t\t\t\tDSL_BSP_MemoryAccessType_t type,\n\t\t\t\tDSL_uint32_t destaddr, DSL_uint32_t *databuff,\n\t\t\t\tDSL_uint32_t databuffsize)\n{\n\tDSL_DEV_MeiError_t meierr = DSL_DEV_MEI_ERR_SUCCESS;\n\tswitch (type) {\n\tcase DSL_BSP_MEMORY_READ:\n\t\tmeierr = IFX_MEI_DebugRead (pDev, (u32)destaddr, (u32*)databuff, (u32)databuffsize);\n\t\tbreak;\n\tcase DSL_BSP_MEMORY_WRITE:\n\t\tmeierr = IFX_MEI_DebugWrite (pDev, (u32)destaddr, (u32*)databuff, (u32)databuffsize);\n\t\tbreak;\n\t}\n\treturn DSL_DEV_MEI_ERR_SUCCESS;\n};\n\n/**\n * Download boot code to ARC.\n * This function downloads boot code to ARC.\n *\n * \\param \tpDev\t\tthe device pointer\n * \\return\tDSL_DEV_MEI_ERR_SUCCESS or DSL_DEV_MEI_ERR_FAILURE\n * \\ingroup\tInternal\n */\nstatic DSL_DEV_MeiError_t\nIFX_MEI_DownloadBootCode (DSL_DEV_Device_t *pDev)\n{\n\tIFX_MEI_IRQDisable (pDev);\n\n\tIFX_MEI_EnableCLK (pDev);\n\n\tIFX_MEI_FuseProg (pDev);\t//program fuse rar\n\n\tIFX_MEI_DownloadBootPages (pDev);\n\n\treturn DSL_DEV_MEI_ERR_SUCCESS;\n};\n\n/**\n * Enable Jtag debugger interface\n * This function setups mips gpio to enable jtag debugger\n *\n * \\param \tpDev\t\tthe device pointer\n * \\param \tenable\t\tenable or disable\n * \\return\tDSL_DEV_MEI_ERR_SUCCESS or DSL_DEV_MEI_ERR_FAILURE\n * \\ingroup\tInternal\n */\nstatic DSL_DEV_MeiError_t\nIFX_MEI_ArcJtagEnable (DSL_DEV_Device_t *dev, int enable)\n{\n\t/*\n\tint meierr=0;\n\tu32 reg_data;\n\tswitch (enable) {\n\tcase 1:\n                //reserve gpio 9, 10, 11, 14, 19 for ARC JTAG\n\t\tifxmips_port_reserve_pin (0, 9);\n\t\tifxmips_port_reserve_pin (0, 10);\n\t\tifxmips_port_reserve_pin (0, 11);\n\t\tifxmips_port_reserve_pin (0, 14);\n\t\tifxmips_port_reserve_pin (1, 3);\n\n\t\tifxmips_port_set_dir_in(0, 11);\n\t\tifxmips_port_clear_altsel0(0, 11);\n\t\tifxmips_port_clear_altsel1(0, 11);\n\t\tifxmips_port_set_open_drain(0, 11);\n        //enable ARC JTAG\n        IFX_MEI_LongWordRead ((u32) LTQ_RCU_RST, &reg_data);\n        IFX_MEI_LongWordWrite ((u32) LTQ_RCU_RST, reg_data | LTQ_RCU_RST_REQ_ARC_JTAG);\n\t\tbreak;\n\tcase 0:\n\tdefault:\n\t\tbreak;\n\t}\njtag_end:\n\tif (meierr)\n\t\treturn DSL_DEV_MEI_ERR_FAILURE;\n*/\n\n\treturn DSL_DEV_MEI_ERR_SUCCESS;\n};\n\n/**\n * Enable DFE to MIPS interrupt\n * This function enable DFE to MIPS interrupt\n *\n * \\param \tpDev\t\tthe device pointer\n * \\param \tenable\t\tenable or disable\n * \\return\tDSL_DEV_MEI_ERR_SUCCESS or DSL_DEV_MEI_ERR_FAILURE\n * \\ingroup\tInternal\n */\nstatic DSL_DEV_MeiError_t\nIFX_MEI_AdslMailboxIRQEnable (DSL_DEV_Device_t *pDev, int enable)\n{\n\tDSL_DEV_MeiError_t meierr;\n\tswitch (enable) {\n\tcase 0:\n\t\tmeierr = DSL_DEV_MEI_ERR_SUCCESS;\n\t\tIFX_MEI_IRQDisable (pDev);\n\t\tbreak;\n\tcase 1:\n\t\tIFX_MEI_IRQEnable (pDev);\n\t\tmeierr = DSL_DEV_MEI_ERR_SUCCESS;\n\t\tbreak;\n\tdefault:\n\t\tmeierr = DSL_DEV_MEI_ERR_FAILURE;\n\t\tbreak;\n\n\t}\n\treturn meierr;\n}\n\n/**\n * Get the modem status\n * This function return the modem status\n *\n * \\param \tpDev\t\tthe device pointer\n * \\return\t1: modem ready 0: not ready\n * \\ingroup\tInternal\n */\nstatic int\nIFX_MEI_IsModemReady (DSL_DEV_Device_t * pDev)\n{\n\treturn DSL_DEV_PRIVATE(pDev)->modem_ready;\n}\n\nDSL_DEV_MeiError_t\nDSL_BSP_AdslLedInit (DSL_DEV_Device_t * dev,\n\t\t\t  DSL_DEV_LedId_t led_number,\n\t\t\t  DSL_DEV_LedType_t type,\n\t\t\t  DSL_DEV_LedHandler_t handler)\n{\n#if 0\n        struct led_config_param param;\n        if (led_number == DSL_LED_LINK_ID && type == DSL_LED_LINK_TYPE && handler == /*DSL_LED_HD_CPU*/DSL_LED_HD_FW) {\n                param.operation_mask = CONFIG_OPERATION_UPDATE_SOURCE;\n                param.led = 0x01;\n                param.source = 0x01;\n//                bsp_led_config (&param);\n\n        } else if (led_number == DSL_LED_DATA_ID && type == DSL_LED_DATA_TYPE && (handler == DSL_LED_HD_FW)) {\n                param.operation_mask = CONFIG_OPERATION_UPDATE_SOURCE;\n                param.led = 0x02;\n                param.source = 0x02;\n//                bsp_led_config (&param);\n        }\n#endif\n        return DSL_DEV_MEI_ERR_SUCCESS;\n};\n#if 0\nDSL_DEV_MeiError_t\nDSL_BSP_AdslLedSet (DSL_DEV_Device_t * dev, DSL_DEV_LedId_t led_number, DSL_DEV_LedMode_t mode)\n{\n\tprintk(KERN_INFO \"[%s %d]: mode = %#x, led_number = %d\\n\", __func__, __LINE__, mode, led_number);\n\tswitch (mode) {\n\tcase DSL_LED_OFF:\n\t\tswitch (led_number) {\n\t\tcase DSL_LED_LINK_ID:\n#ifdef CONFIG_BSP_LED\n\t\t\tbsp_led_set_blink (1, 0);\n\t\t\tbsp_led_set_data (1, 0);\n#endif\n\t\t\tbreak;\n\t\tcase DSL_LED_DATA_ID:\n#ifdef CONFIG_BSP_LED\n\t\t\tbsp_led_set_blink (0, 0);\n\t\t\tbsp_led_set_data (0, 0);\n#endif\n\t\t\tbreak;\n\t\t}\n\t\tbreak;\n\tcase DSL_LED_FLASH:\n\t\tswitch (led_number) {\n\t\tcase DSL_LED_LINK_ID:\n#ifdef CONFIG_BSP_LED\n\t\t\tbsp_led_set_blink (1, 1);\t// data\n#endif\n\t\t\tbreak;\n\t\tcase DSL_LED_DATA_ID:\n#ifdef CONFIG_BSP_LED\n\t\t\tbsp_led_set_blink (0, 1);\t// data\n#endif\n\t\t\tbreak;\n\t\t}\n\t\tbreak;\n\tcase DSL_LED_ON:\n\t\tswitch (led_number) {\n\t\tcase DSL_LED_LINK_ID:\n#ifdef CONFIG_BSP_LED\n\t\t\tbsp_led_set_blink (1, 0);\n\t\t\tbsp_led_set_data (1, 1);\n#endif\n\t\t\tbreak;\n\t\tcase DSL_LED_DATA_ID:\n#ifdef CONFIG_BSP_LED\n\t\t\tbsp_led_set_blink (0, 0);\n\t\t\tbsp_led_set_data (0, 1);\n#endif\n\t\t\tbreak;\n\t\t}\n\t\tbreak;\n\t}\n\treturn DSL_DEV_MEI_ERR_SUCCESS;\n};\n\n#endif\n\n/**\n* Compose a message.\n* This function compose a message from opcode, group, address, index, size, and data\n*\n* \\param       opcode          The message opcode\n* \\param       group           The message group number\n* \\param       address         The message address.\n* \\param       index           The message index.\n* \\param       size            The number of words to read/write.\n* \\param       data            The pointer to data.\n* \\param       CMVMSG          The pointer to message buffer.\n* \\ingroup     Internal\n*/\nvoid\nmakeCMV (u8 opcode, u8 group, u16 address, u16 index, int size, u16 * data, u16 *CMVMSG)\n{\n        memset (CMVMSG, 0, MSG_LENGTH * 2);\n        CMVMSG[0] = (opcode << 4) + (size & 0xf);\n        CMVMSG[1] = (((index == 0) ? 0 : 1) << 7) + (group & 0x7f);\n        CMVMSG[2] = address;\n        CMVMSG[3] = index;\n        if (opcode == H2D_CMV_WRITE)\n                memcpy (CMVMSG + 4, data, size * 2);\n        return;\n}\n\n/**\n * Send a message to ARC and read the response\n * This function sends a message to arc, waits the response, and reads the responses.\n *\n * \\param \tpDev\t\tthe device pointer\n * \\param\trequest\t\tPointer to the request\n * \\param\treply\t\tWait reply or not.\n * \\param\tresponse\tPointer to the response\n * \\return\tDSL_DEV_MEI_ERR_SUCCESS or DSL_DEV_MEI_ERR_FAILURE\n * \\ingroup\tInternal\n */\nDSL_DEV_MeiError_t\nDSL_BSP_SendCMV (DSL_DEV_Device_t * pDev, u16 * request, int reply, u16 * response)\t// write cmv to arc, if reply needed, wait for reply\n{\n\tDSL_DEV_MeiError_t meierror;\n#if defined(BSP_PORT_RTEMS)\n\tint delay_counter = 0;\n#endif\n\n\tif (MEI_MUTEX_LOCK (DSL_DEV_PRIVATE(pDev)->mei_cmv_sema))\n\t\treturn -ERESTARTSYS;\n\n\tDSL_DEV_PRIVATE(pDev)->cmv_reply = reply;\n\tmemset (DSL_DEV_PRIVATE(pDev)->CMV_RxMsg, 0,\n\t\tsizeof (DSL_DEV_PRIVATE(pDev)->\n\t\t\tCMV_RxMsg));\n\tDSL_DEV_PRIVATE(pDev)->arcmsgav = 0;\n\n\tmeierror = IFX_MEI_MailboxWrite (pDev, request, MSG_LENGTH);\n\n\tif (meierror != DSL_DEV_MEI_ERR_SUCCESS) {\n\t\tDSL_DEV_PRIVATE(pDev)->cmv_waiting = 0;\n\t\tDSL_DEV_PRIVATE(pDev)->arcmsgav = 0;\n\t\tIFX_MEI_EMSG (\"MailboxWrite Fail!\\n\");\n\t\tIFX_MEI_EMSG (\"Resetting ARC...\\n\");\n\t\tIFX_MEI_ResetARC(pDev);\n\t\tMEI_MUTEX_UNLOCK (DSL_DEV_PRIVATE(pDev)->mei_cmv_sema);\n\t\treturn meierror;\n\t}\n\telse {\n\t\tDSL_DEV_PRIVATE(pDev)->cmv_count++;\n\t}\n\n\tif (DSL_DEV_PRIVATE(pDev)->cmv_reply ==\n\t    NO_REPLY) {\n\t\tMEI_MUTEX_UNLOCK (DSL_DEV_PRIVATE(pDev)->mei_cmv_sema);\n\t\treturn DSL_DEV_MEI_ERR_SUCCESS;\n\t}\n\n#if !defined(BSP_PORT_RTEMS)\n\tif (DSL_DEV_PRIVATE(pDev)->arcmsgav == 0)\n\t\tMEI_WAIT_EVENT_TIMEOUT (DSL_DEV_PRIVATE(pDev)->wait_queue_arcmsgav, CMV_TIMEOUT);\n#else\n\twhile (DSL_DEV_PRIVATE(pDev)->arcmsgav == 0 && delay_counter < CMV_TIMEOUT / 5) {\n\t\tMEI_WAIT (5);\n\t\tdelay_counter++;\n\t}\n#endif\n\n\tDSL_DEV_PRIVATE(pDev)->cmv_waiting = 0;\n\tif (DSL_DEV_PRIVATE(pDev)->arcmsgav == 0) {\t//CMV_timeout\n\t\tDSL_DEV_PRIVATE(pDev)->arcmsgav = 0;\n\t\tIFX_MEI_EMSG (\"\\%s: DSL_DEV_MEI_ERR_MAILBOX_TIMEOUT\\n\",\n\t\t\t\t    __FUNCTION__);\n\t\tMEI_MUTEX_UNLOCK (DSL_DEV_PRIVATE(pDev)->mei_cmv_sema);\n\t\treturn DSL_DEV_MEI_ERR_MAILBOX_TIMEOUT;\n\t}\n\telse {\n\t\tDSL_DEV_PRIVATE(pDev)->arcmsgav = 0;\n\t\tDSL_DEV_PRIVATE(pDev)->\n\t\t\treply_count++;\n\t\tmemcpy (response, DSL_DEV_PRIVATE(pDev)->CMV_RxMsg, MSG_LENGTH * 2);\n\t\tMEI_MUTEX_UNLOCK (DSL_DEV_PRIVATE(pDev)->mei_cmv_sema);\n\t\treturn DSL_DEV_MEI_ERR_SUCCESS;\n\t}\n\tMEI_MUTEX_UNLOCK (DSL_DEV_PRIVATE(pDev)->mei_cmv_sema);\n\treturn DSL_DEV_MEI_ERR_SUCCESS;\n}\n\n/**\n * Reset the ARC, download boot codes, and run the ARC.\n * This function resets the ARC, downloads boot codes to ARC, and runs the ARC.\n *\n * \\param \tpDev\t\tthe device pointer\n * \\return\tDSL_DEV_MEI_ERR_SUCCESS or DSL_DEV_MEI_ERR_FAILURE\n * \\ingroup\tInternal\n */\nstatic DSL_DEV_MeiError_t\nIFX_MEI_RunAdslModem (DSL_DEV_Device_t *pDev)\n{\n\tint nSize = 0, idx = 0;\n\tuint32_t im0_register, im2_register;\n//\tDSL_DEV_WinHost_Message_t m;\n\n\tif (mei_arc_swap_buff == NULL) {\n\t\tmei_arc_swap_buff =\n\t\t\t(u32 *) kmalloc (MAXSWAPSIZE * 4, GFP_KERNEL);\n\t\tif (mei_arc_swap_buff == NULL) {\n\t\t\tIFX_MEI_EMSG (\">>> malloc fail for codeswap buff!!! <<<\\n\");\n\t\t\treturn DSL_DEV_MEI_ERR_FAILURE;\n\t\t}\n                IFX_MEI_DMSG(\"allocate %dKB swap buff memory at: 0x%p\\n\", ksize(mei_arc_swap_buff)/1024, mei_arc_swap_buff);\n\t}\n\n\tDSL_DEV_PRIVATE(pDev)->img_hdr =\n\t\t(ARC_IMG_HDR *) DSL_DEV_PRIVATE(pDev)->adsl_mem_info[0].address;\n\tif ((DSL_DEV_PRIVATE(pDev)->img_hdr->\n\t     count) * sizeof (ARC_SWP_PAGE_HDR) > SDRAM_SEGMENT_SIZE) {\n\t\tIFX_MEI_EMSG (\"firmware header size is bigger than 64K segment size\\n\");\n\t\treturn DSL_DEV_MEI_ERR_FAILURE;\n\t}\n\t// check image size\n\tfor (idx = 0; idx < MAX_BAR_REGISTERS; idx++) {\n\t\tnSize += DSL_DEV_PRIVATE(pDev)->adsl_mem_info[idx].nCopy;\n\t}\n\tif (nSize !=\n\t    DSL_DEV_PRIVATE(pDev)->image_size) {\n\t\tIFX_MEI_EMSG (\"Firmware download is not completed. Please download firmware again!\\n\");\n\t\treturn DSL_DEV_MEI_ERR_FAILURE;\n\t}\n\t// TODO: check crc\n\t///\n\n\tIFX_MEI_ResetARC (pDev);\n\tIFX_MEI_HaltArc (pDev);\n\tIFX_MEI_BarUpdate (pDev, DSL_DEV_PRIVATE(pDev)->nBar);\n\n\t//IFX_MEI_DMSG(\"Starting to meiDownloadBootCode\\n\");\n\n\tIFX_MEI_DownloadBootCode (pDev);\n\n\tim0_register = (*LTQ_ICU_IM0_IER) & (1 << 20);\n\tim2_register = (*LTQ_ICU_IM2_IER) & (1 << 20);\n\n\t/* Turn off irq */\n\tdisable_irq (LTQ_USB_OC_INT);\n\tdisable_irq (pDev->nIrq[IFX_DYING_GASP]);\n\n\tIFX_MEI_RunArc (pDev);\n\n\tMEI_WAIT_EVENT_TIMEOUT (DSL_DEV_PRIVATE(pDev)->wait_queue_modemready, 1000);\n\n\tMEI_MASK_AND_ACK_IRQ (LTQ_USB_OC_INT);\n\tMEI_MASK_AND_ACK_IRQ (pDev->nIrq[IFX_DYING_GASP]);\n\n\t/* Re-enable irq */\n\tenable_irq(pDev->nIrq[IFX_DYING_GASP]);\n\t*LTQ_ICU_IM0_IER |= im0_register;\n\t*LTQ_ICU_IM2_IER |= im2_register;\n\n\tif (DSL_DEV_PRIVATE(pDev)->modem_ready != 1) {\n\t\tIFX_MEI_EMSG (\"Modem failed to be ready!\\n\");\n\t\treturn DSL_DEV_MEI_ERR_FAILURE;\n\t} else {\n\t\tIFX_MEI_DMSG(\"Modem is ready.\\n\");\n\t\treturn DSL_DEV_MEI_ERR_SUCCESS;\n\t}\n}\n\n/**\n * Get the page's data pointer\n * This function caculats the data address from the firmware header.\n *\n * \\param \tpDev\t\tthe device pointer\n * \\param\tPage\t\tThe page number.\n * \\param\tdata\t\tData page or program page.\n * \\param\tMaxSize\t\tThe maximum size to read.\n * \\param\tBuffer\t\tPointer to data.\n * \\param\tDest\t\tPointer to the destination address.\n * \\return\tThe number of bytes to read.\n * \\ingroup\tInternal\n */\nstatic int\nIFX_MEI_GetPage (DSL_DEV_Device_t * pDev, u32 Page, u32 data,\n\t\t       u32 MaxSize, u32 * Buffer, u32 * Dest)\n{\n\tu32 size;\n\tu32 i;\n\tu32 *p;\n\tu32 idx, offset, nBar = 0;\n\n\tif (Page > DSL_DEV_PRIVATE(pDev)->img_hdr->count)\n\t\treturn -2;\n\t/*\n\t **     Get program or data size, depending on \"data\" flag\n\t */\n\tsize = (data == GET_DATA) ? (DSL_DEV_PRIVATE(pDev)->img_hdr->page[Page].d_size) :\n\t\t\t     (DSL_DEV_PRIVATE(pDev)->img_hdr->page[Page].p_size);\n\tsize &= BOOT_FLAG_MASK;\t//      Clear boot bit!\n\tif (size > MaxSize)\n\t\treturn -1;\n\n\tif (size == 0)\n\t\treturn 0;\n\t/*\n\t **     Get program or data offset, depending on \"data\" flag\n\t */\n\ti = data ? (DSL_DEV_PRIVATE(pDev)->img_hdr->page[Page].d_offset) :\n\t\t\t(DSL_DEV_PRIVATE(pDev)->img_hdr->page[Page].p_offset);\n\n\t/*\n\t **     Copy data/program to buffer\n\t */\n\n\tidx = i / SDRAM_SEGMENT_SIZE;\n\toffset = i % SDRAM_SEGMENT_SIZE;\n\tp = (u32 *) ((u8 *) DSL_DEV_PRIVATE(pDev)->adsl_mem_info[idx].address + offset);\n\n\tfor (i = 0; i < size; i++) {\n\t\tif (offset + i * 4 - (nBar * SDRAM_SEGMENT_SIZE) >= SDRAM_SEGMENT_SIZE) {\n\t\t\tidx++;\n\t\t\tnBar++;\n\t\t\tp = (u32 *) ((u8 *) KSEG1ADDR ((u32)DSL_DEV_PRIVATE(pDev)->adsl_mem_info[idx].address));\n\t\t}\n\t\tBuffer[i] = *p++;\n\t}\n\n\t/*\n\t **     Pass back data/program destination address\n\t */\n\t*Dest = data ? (DSL_DEV_PRIVATE(pDev)-> img_hdr->page[Page].d_dest) :\n\t\t\t\t(DSL_DEV_PRIVATE(pDev)->img_hdr->page[Page].p_dest);\n\n\treturn size;\n}\n\n/**\n * Free the memory for ARC firmware\n *\n * \\param \tpDev\t\tthe device pointer\n * \\param\ttype\tFree all memory or free the unused memory after showtime\n * \\ingroup\tInternal\n */\nconst char *free_str[4] = {\"Invalid\", \"Free_Reload\", \"Free_Showtime\", \"Free_All\"};\nstatic int\nIFX_MEI_DFEMemoryFree (DSL_DEV_Device_t * pDev, int type)\n{\n        int idx = 0;\n        smmu_mem_info_t *adsl_mem_info =\n                DSL_DEV_PRIVATE(pDev)->adsl_mem_info;\n\n        for (idx = 0; idx < MAX_BAR_REGISTERS; idx++) {\n                if (type == FREE_ALL ||adsl_mem_info[idx].type == type) {\n                        if (adsl_mem_info[idx].size > 0) {\n                                IFX_MEI_DMSG (\"Freeing memory %p (%s)\\n\", adsl_mem_info[idx].org_address, free_str[adsl_mem_info[idx].type]);\n                                if ( idx == XDATA_REGISTER ) {\n                                    g_xdata_addr = NULL;\n                                    if ( ifx_mei_atm_showtime_exit )\n                                        ifx_mei_atm_showtime_exit();\n                                }\n\t\t\t\tkfree (adsl_mem_info[idx].org_address);\n                                adsl_mem_info[idx].org_address = 0;\n                                adsl_mem_info[idx].address = 0;\n                                adsl_mem_info[idx].size = 0;\n                                adsl_mem_info[idx].type = 0;\n                                adsl_mem_info[idx].nCopy = 0;\n                        }\n                }\n        }\n\n\tif(mei_arc_swap_buff != NULL){\n                IFX_MEI_DMSG(\"free %dKB swap buff memory at: 0x%p\\n\", ksize(mei_arc_swap_buff)/1024, mei_arc_swap_buff);\n\t\tkfree(mei_arc_swap_buff);\n\t\tmei_arc_swap_buff=NULL;\n\t}\n\n        return 0;\n}\nstatic int\nIFX_MEI_DFEMemoryAlloc (DSL_DEV_Device_t * pDev, long size)\n{\n\tunsigned long mem_ptr;\n\tchar *org_mem_ptr = NULL;\n\tint idx = 0;\n\tlong total_size = 0;\n\tint err = 0;\n\tsmmu_mem_info_t *adsl_mem_info =\n\t\t((ifx_mei_device_private_t *) pDev->pPriv)->adsl_mem_info;\n//\t\tDSL_DEV_PRIVATE(pDev)->adsl_mem_info;\n\tint allocate_size = SDRAM_SEGMENT_SIZE;\n\n\tIFX_MEI_DMSG(\"image_size = %ld\\n\", size);\n\t// Alloc Swap Pages\n\tfor (idx = 0; size > 0 && idx < MAX_BAR_REGISTERS; idx++) {\n\t\t// skip bar15 for XDATA usage.\n\t\tif (idx == XDATA_REGISTER)\n\t\t\tcontinue;\n#if 0\n                if (size < SDRAM_SEGMENT_SIZE) {\n                        allocate_size = size;\n                        if (allocate_size < 1024)\n                                allocate_size = 1024;\n                }\n#endif\n                if (idx == (MAX_BAR_REGISTERS - 1))\n                        allocate_size = size;\n                else\n                        allocate_size = SDRAM_SEGMENT_SIZE;\n        \n\t\torg_mem_ptr = kmalloc (allocate_size, GFP_KERNEL);\n\t\tif (org_mem_ptr == NULL) {\n                        IFX_MEI_EMSG (\"%d: kmalloc %d bytes memory fail!\\n\", idx, allocate_size);\n\t\t\terr = -ENOMEM;\n\t\t\tgoto allocate_error;\n\t\t}\n\t\t\n\t\tif (((unsigned long)org_mem_ptr) & (1023)) {\n\t\t\t/* Pointer not 1k aligned, so free it and allocate a larger chunk\n\t\t\t * for further alignment.\n\t\t\t */\n\t\t\tkfree(org_mem_ptr);\n\t\t\torg_mem_ptr = kmalloc (allocate_size + 1024, GFP_KERNEL);\n\t\t\tif (org_mem_ptr == NULL) {\n\t\t\t\tIFX_MEI_EMSG (\"%d: kmalloc %d bytes memory fail!\\n\",\n\t\t\t\t              idx, allocate_size + 1024);\n\t\t\t\terr = -ENOMEM;\n\t\t\t\tgoto allocate_error;\n\t\t\t}\n\t\t\tmem_ptr = (unsigned long) (org_mem_ptr + 1023) & ~(1024 -1);\n\t\t} else {\n\t\t\tmem_ptr = (unsigned long) org_mem_ptr;\n\t\t}\n\n                adsl_mem_info[idx].address = (char *) mem_ptr;\n                adsl_mem_info[idx].org_address = org_mem_ptr;\n                adsl_mem_info[idx].size = allocate_size;\n                size -= allocate_size;\n                total_size += allocate_size;\n\t}\n\tif (size > 0) {\n\t\tIFX_MEI_EMSG (\"Image size is too large!\\n\");\n\t\terr = -EFBIG;\n\t\tgoto allocate_error;\n\t}\n\terr = idx;\n\treturn err;\n\n      allocate_error:\n\tIFX_MEI_DFEMemoryFree (pDev, FREE_ALL);\n\treturn err;\n}\n\n/**\n * Program the BAR registers\n *\n * \\param \tpDev\t\tthe device pointer\n * \\param\tnTotalBar\tThe number of bar to program.\n * \\ingroup\tInternal\n */\nstatic int\nIFX_MEI_BarUpdate (DSL_DEV_Device_t * pDev, int nTotalBar)\n{\n\tint idx = 0;\n\tsmmu_mem_info_t *adsl_mem_info =\n\t\tDSL_DEV_PRIVATE(pDev)->adsl_mem_info;\n\n\tfor (idx = 0; idx < nTotalBar; idx++) {\n\t\t//skip XDATA register\n\t\tif (idx == XDATA_REGISTER)\n\t\t\tcontinue;\n\t\tIFX_MEI_LongWordWriteOffset (pDev, (u32) ME_XMEM_BAR_BASE + idx * 4,\n\t\t\t(((uint32_t) adsl_mem_info[idx].address) & 0x0FFFFFFF));\n\t}\n\tfor (idx = nTotalBar; idx < MAX_BAR_REGISTERS; idx++) {\n\t\tif (idx == XDATA_REGISTER)\n\t\t\tcontinue;\n\t\tIFX_MEI_LongWordWriteOffset (pDev,  (u32) ME_XMEM_BAR_BASE  + idx * 4,\n\t\t\t (((uint32_t)adsl_mem_info[nTotalBar - 1].address) & 0x0FFFFFFF));\n\t\t/* These are for /proc/danube_mei/meminfo purpose */\n\t\tadsl_mem_info[idx].address = adsl_mem_info[nTotalBar - 1].address;\n\t\tadsl_mem_info[idx].org_address = adsl_mem_info[nTotalBar - 1].org_address;\n\t\tadsl_mem_info[idx].size = 0; /* Prevent it from being freed */\n\t}\n\n    g_xdata_addr = adsl_mem_info[XDATA_REGISTER].address;\n\tIFX_MEI_LongWordWriteOffset (pDev,  (u32) ME_XMEM_BAR_BASE  + XDATA_REGISTER * 4,\n\t\t(((uint32_t) adsl_mem_info [XDATA_REGISTER].address) & 0x0FFFFFFF));\n\t// update MEI_XDATA_BASE_SH\n\tIFX_MEI_LongWordWriteOffset (pDev, (u32) ME_XDATA_BASE_SH,\n\t\t ((unsigned long)adsl_mem_info[XDATA_REGISTER].address) & 0x0FFFFFFF);\n\n\treturn DSL_DEV_MEI_ERR_SUCCESS;\n}\n\n/* This copies the firmware from secondary storage to 64k memory segment in SDRAM */\nDSL_DEV_MeiError_t\nDSL_BSP_FWDownload (DSL_DEV_Device_t * pDev, const char *buf,\n\t\t\t unsigned long size, long *loff, long *current_offset)\n{\n\tARC_IMG_HDR img_hdr_tmp;\n\tsmmu_mem_info_t *adsl_mem_info = DSL_DEV_PRIVATE(pDev)->adsl_mem_info;\n\n\tsize_t nRead = 0, nCopy = 0;\n\tchar *mem_ptr;\n\tchar *org_mem_ptr = NULL;\n\tssize_t retval = -ENOMEM;\n\tint idx = 0;\n\n        IFX_MEI_DMSG(\"\\n\");\n\n\tif (*loff == 0) {\n\t\tif (size < sizeof (img_hdr_tmp)) {\n\t\t\tIFX_MEI_EMSG (\"Firmware size is too small!\\n\");\n\t\t\treturn retval;\n\t\t}\n\t\tcopy_from_user ((char *) &img_hdr_tmp, buf, sizeof (img_hdr_tmp));\n\t\t// header of image_size and crc are not included.\n\t\tDSL_DEV_PRIVATE(pDev)->image_size = le32_to_cpu (img_hdr_tmp.size) + 8;\n\n\t\tif (DSL_DEV_PRIVATE(pDev)->image_size > 1024 * 1024) {\n\t\t\tIFX_MEI_EMSG (\"Firmware size is too large!\\n\");\n\t\t\treturn retval;\n\t\t}\n\t\t// check if arc is halt\n\t\tIFX_MEI_ResetARC (pDev);\n\t\tIFX_MEI_HaltArc (pDev);\n\n\t\tIFX_MEI_DFEMemoryFree (pDev, FREE_ALL);\t//free all\n\n\t\tretval = IFX_MEI_DFEMemoryAlloc (pDev,  DSL_DEV_PRIVATE(pDev)->image_size);\n\t\tif (retval < 0) {\n\t\t\tIFX_MEI_EMSG (\"Error: No memory space left.\\n\");\n\t\t\tgoto error;\n\t\t}\n\t\tfor (idx = 0; idx < retval; idx++) {\n\t\t\t//skip XDATA register\n\t\t\tif (idx == XDATA_REGISTER)\n\t\t\t\tcontinue;\n\t\t\tif (idx * SDRAM_SEGMENT_SIZE < le32_to_cpu (img_hdr_tmp.page[0].p_offset))\n\t\t\t\tadsl_mem_info[idx].type = FREE_RELOAD;\n\t\t\telse\n\t\t\t\tadsl_mem_info[idx].type = FREE_SHOWTIME;\n\t\t}\n\t\tDSL_DEV_PRIVATE(pDev)->nBar = retval;\n\n\t\tDSL_DEV_PRIVATE(pDev)->img_hdr =\n\t\t\t(ARC_IMG_HDR *) adsl_mem_info[0].address;\n\n\t\torg_mem_ptr = kmalloc (SDRAM_SEGMENT_SIZE, GFP_KERNEL);\n\t\tif (org_mem_ptr == NULL) {\n\t\t\tIFX_MEI_EMSG (\"kmalloc memory fail!\\n\");\n\t\t\tretval = -ENOMEM;\n\t\t\tgoto error;\n\t\t}\n\t\t\n\t\tif (((unsigned long)org_mem_ptr) & (1023)) {\n\t\t\t/* Pointer not 1k aligned, so free it and allocate a larger chunk\n\t\t\t * for further alignment.\n\t\t\t */\n\t\t\tkfree(org_mem_ptr);\n\t\t\torg_mem_ptr = kmalloc (SDRAM_SEGMENT_SIZE + 1024, GFP_KERNEL);\n\t\t\tif (org_mem_ptr == NULL) {\n\t\t\t\tIFX_MEI_EMSG (\"kmalloc memory fail!\\n\");\n\t\t\t\tretval = -ENOMEM;\n\t\t\t\tgoto error;\n\t\t\t}\n\t\t\tadsl_mem_info[XDATA_REGISTER].address =\n\t\t\t\t(char *) ((unsigned long) (org_mem_ptr + 1023) & ~(1024 -1));\n\t\t} else {\n\t\t\tadsl_mem_info[XDATA_REGISTER].address = org_mem_ptr;\n\t\t}\n\t\t\n\t\tadsl_mem_info[XDATA_REGISTER].org_address = org_mem_ptr;\n\t\tadsl_mem_info[XDATA_REGISTER].size = SDRAM_SEGMENT_SIZE;\n\n\t\tadsl_mem_info[XDATA_REGISTER].type = FREE_RELOAD;\n\t\tIFX_MEI_DMSG(\"-> IFX_MEI_BarUpdate()\\n\");\n\t\tIFX_MEI_BarUpdate (pDev, (DSL_DEV_PRIVATE(pDev)->nBar));\n\t}\n\telse if (DSL_DEV_PRIVATE(pDev)-> image_size == 0) {\n\t\tIFX_MEI_EMSG (\"Error: Firmware size=0! \\n\");\n\t\tgoto error;\n\t}\n\n\tnRead = 0;\n\twhile (nRead < size) {\n\t\tlong offset = ((long) (*loff) + nRead) % SDRAM_SEGMENT_SIZE;\n\t\tidx = (((long) (*loff)) + nRead) / SDRAM_SEGMENT_SIZE;\n\t\tmem_ptr = (char *) KSEG1ADDR ((unsigned long) (adsl_mem_info[idx].address) + offset);\n\t\tif ((size - nRead + offset) > SDRAM_SEGMENT_SIZE)\n\t\t\tnCopy = SDRAM_SEGMENT_SIZE - offset;\n\t\telse\n\t\t\tnCopy = size - nRead;\n\t\tcopy_from_user (mem_ptr, buf + nRead, nCopy);\n\t\tfor (offset = 0; offset < (nCopy / 4); offset++) {\n\t\t\t((unsigned long *) mem_ptr)[offset] = le32_to_cpu (((unsigned long *) mem_ptr)[offset]);\n\t\t}\n\t\tnRead += nCopy;\n\t\tadsl_mem_info[idx].nCopy += nCopy;\n\t}\n\n\t*loff += size;\n\t*current_offset = size;\n\treturn DSL_DEV_MEI_ERR_SUCCESS;\nerror:\n\tIFX_MEI_DFEMemoryFree (pDev, FREE_ALL);\n\treturn DSL_DEV_MEI_ERR_FAILURE;\n}\n/*\n * Register a callback event.\n * Return:\n * -1 if the event already has a callback function registered.\n *  0 success\n */\nint DSL_BSP_EventCBRegister(DSL_BSP_EventCallBack_t *p)\n{\n\tif (!p) {\n                IFX_MEI_EMSG(\"Invalid parameter!\\n\");\n                return -EINVAL;\n\t}\n        if (p->event > DSL_BSP_CB_LAST || p->event < DSL_BSP_CB_FIRST) {\n                IFX_MEI_EMSG(\"Invalid Event %d\\n\", p->event);\n                return -EINVAL;\n        }\n        if (dsl_bsp_event_callback[p->event].function) {\n                IFX_MEI_EMSG(\"Event %d already has a callback function registered!\\n\", p->event);\n                return -1;\n        } else {\n                dsl_bsp_event_callback[p->event].function = p->function;\n                dsl_bsp_event_callback[p->event].event    = p->event;\n                dsl_bsp_event_callback[p->event].pData    = p->pData;\n        }\n        return 0;\n}\nint DSL_BSP_EventCBUnregister(DSL_BSP_EventCallBack_t *p)\n{\n\tif (!p) {\n                IFX_MEI_EMSG(\"Invalid parameter!\\n\");\n                return -EINVAL;\n\t}\n        if (p->event > DSL_BSP_CB_LAST || p->event < DSL_BSP_CB_FIRST) {\n                IFX_MEI_EMSG(\"Invalid Event %d\\n\", p->event);\n                return -EINVAL;\n        }\n        if (dsl_bsp_event_callback[p->event].function) {\n                IFX_MEI_EMSG(\"Unregistering Event %d...\\n\", p->event);\n                dsl_bsp_event_callback[p->event].function = NULL;\n                dsl_bsp_event_callback[p->event].pData    = NULL;\n        } else {\n                IFX_MEI_EMSG(\"Event %d is not registered!\\n\", p->event);\n                return -1;\n        }\n        return 0;\n}\n\n/**\n * MEI Dying Gasp interrupt handler\n *\n * \\param int1\n * \\param void0\n * \\param regs\tPointer to the structure of danube mips registers\n * \\ingroup\tInternal\n */\n/*static irqreturn_t IFX_MEI_Dying_Gasp_IrqHandle (int int1, void *void0)\n{\n\tDSL_DEV_Device_t *pDev = (DSL_DEV_Device_t *) void0;\n        DSL_BSP_CB_Type_t event;\n\n\tif (pDev == NULL)\n\t\tIFX_MEI_EMSG(\"Error: Got Interrupt but pDev is NULL!!!!\\n\");\n\n#ifndef CONFIG_SMP\n\tdisable_irq (pDev->nIrq[IFX_DYING_GASP]);\n#else\n\tdisable_irq_nosync(pDev->nIrq[IFX_DYING_GASP]);\n#endif\n\tevent = DSL_BSP_CB_DYING_GASP;\n\n\tif (dsl_bsp_event_callback[event].function)\n\t\t(*dsl_bsp_event_callback[event].function)(pDev, event, dsl_bsp_event_callback[event].pData);\n\n#ifdef CONFIG_USE_EMULATOR\n    IFX_MEI_EMSG(\"Dying Gasp! Shutting Down... (Work around for Amazon-S Venus emulator)\\n\");\n#else\n\tIFX_MEI_EMSG(\"Dying Gasp! Shutting Down...\\n\");\n//\tkill_proc (1, SIGINT, 1);   \n#endif\n        return IRQ_HANDLED;\n}\n*/\nextern void ifx_usb_enable_afe_oc(void);\n\n/**\n * MEI interrupt handler\n *\n * \\param int1\n * \\param void0\n * \\param regs\tPointer to the structure of danube mips registers\n * \\ingroup\tInternal\n */\nstatic irqreturn_t IFX_MEI_IrqHandle (int int1, void *void0)\n{\n\tu32 scratch;\n\tDSL_DEV_Device_t *pDev = (DSL_DEV_Device_t *) void0;\n#if defined(CONFIG_LTQ_MEI_FW_LOOPBACK) && defined(DFE_PING_TEST)\n\tdfe_loopback_irq_handler (pDev);\n\treturn IRQ_HANDLED;\n#endif //CONFIG_AMAZON_S_MEI_FW_LOOPBACK\n        DSL_BSP_CB_Type_t event;\n\n\tif (pDev == NULL)\n\t\tIFX_MEI_EMSG(\"Error: Got Interrupt but pDev is NULL!!!!\\n\");\n\n\tIFX_MEI_DebugRead (pDev, ARC_MEI_MAILBOXR, &scratch, 1);\n\tif (scratch & OMB_CODESWAP_MESSAGE_MSG_TYPE_MASK) {\n\t\tIFX_MEI_EMSG(\"Receive Code Swap Request interrupt!!!\\n\");\n\t\treturn IRQ_HANDLED;\n\t}\n\telse if (scratch & OMB_CLEAREOC_INTERRUPT_CODE)\t {\n\t\t// clear eoc message interrupt\n\t\tIFX_MEI_DMSG(\"OMB_CLEAREOC_INTERRUPT_CODE\\n\");\n                event = DSL_BSP_CB_CEOC_IRQ;\n\t\tIFX_MEI_LongWordWriteOffset (pDev, (u32) ME_ARC2ME_STAT, ARC_TO_MEI_MSGAV);\n                if (dsl_bsp_event_callback[event].function)\n\t\t\t(*dsl_bsp_event_callback[event].function)(pDev, event, dsl_bsp_event_callback[event].pData);\n        } else if (scratch & OMB_REBOOT_INTERRUPT_CODE) {\n                // Reboot\n                IFX_MEI_DMSG(\"OMB_REBOOT_INTERRUPT_CODE\\n\");\n                event = DSL_BSP_CB_FIRMWARE_REBOOT;\n\n\t\tIFX_MEI_LongWordWriteOffset (pDev, (u32) ME_ARC2ME_STAT, ARC_TO_MEI_MSGAV);\n\n                if (dsl_bsp_event_callback[event].function)\n                        (*dsl_bsp_event_callback[event].function)(pDev, event, dsl_bsp_event_callback[event].pData);\n        } else { // normal message\n                IFX_MEI_MailboxRead (pDev, DSL_DEV_PRIVATE(pDev)->CMV_RxMsg, MSG_LENGTH);\n                if (DSL_DEV_PRIVATE(pDev)-> cmv_waiting == 1) {\n                        DSL_DEV_PRIVATE(pDev)-> arcmsgav = 1;\n                        DSL_DEV_PRIVATE(pDev)-> cmv_waiting = 0;\n#if !defined(BSP_PORT_RTEMS)\n                        MEI_WAKEUP_EVENT (DSL_DEV_PRIVATE(pDev)->wait_queue_arcmsgav);\n#endif\n                }\n\t\telse {\n\t\t\tDSL_DEV_PRIVATE(pDev)-> modem_ready_cnt++;\n\t\t\tmemcpy ((char *) DSL_DEV_PRIVATE(pDev)->Recent_indicator,\n\t\t\t\t(char *) DSL_DEV_PRIVATE(pDev)->CMV_RxMsg, MSG_LENGTH * 2);\n\t\t\tif (((DSL_DEV_PRIVATE(pDev)->CMV_RxMsg[0] & 0xff0) >> 4) == D2H_AUTONOMOUS_MODEM_READY_MSG) {\n\t\t\t\t//check ARC ready message\n\t\t\t\tIFX_MEI_DMSG (\"Got MODEM_READY_MSG\\n\");\n\t\t\t\tDSL_DEV_PRIVATE(pDev)->modem_ready = 1;\n\t\t\t\tMEI_WAKEUP_EVENT (DSL_DEV_PRIVATE(pDev)->wait_queue_modemready);\n\t\t\t}\n\t\t}\n\t}\n\n\treturn IRQ_HANDLED;\n}\n\nint\nDSL_BSP_ATMLedCBRegister (int (*ifx_adsl_ledcallback) (void))\n{\n    g_adsl_ledcallback = ifx_adsl_ledcallback;\n    return 0;\n}\n\nint\nDSL_BSP_ATMLedCBUnregister (int (*ifx_adsl_ledcallback) (void))\n{\n    g_adsl_ledcallback = adsl_dummy_ledcallback;\n    return 0;\n}\n\n#if 0\nint\nDSL_BSP_EventCBRegister (int (*ifx_adsl_callback)\n\t\t\t        (DSL_BSP_CB_Event_t * param))\n{\n\tint error = 0;\n\n\tif (DSL_EventCB == NULL) {\n\t\tDSL_EventCB = ifx_adsl_callback;\n\t}\n\telse {\n\t\terror = -EIO;\n\t}\n\treturn error;\n}\n\nint\nDSL_BSP_EventCBUnregister (int (*ifx_adsl_callback)\n\t\t\t\t  (DSL_BSP_CB_Event_t * param))\n{\n\tint error = 0;\n\n\tif (DSL_EventCB == ifx_adsl_callback) {\n\t\tDSL_EventCB = NULL;\n\t}\n\telse {\n\t\terror = -EIO;\n\t}\n\treturn error;\n}\n\nstatic int\nDSL_BSP_GetEventCB (int (**ifx_adsl_callback)\n\t\t\t   (DSL_BSP_CB_Event_t * param))\n{\n\t*ifx_adsl_callback = DSL_EventCB;\n\treturn 0;\n}\n#endif\n\n#ifdef CONFIG_LTQ_MEI_FW_LOOPBACK\n#define mte_reg_base\t(0x4800*4+0x20000)\n\n/* Iridia Registers Address Constants */\n#define MTE_Reg(r)    \t(int)(mte_reg_base + (r*4))\n\n#define IT_AMODE       \tMTE_Reg(0x0004)\n\n#define TIMER_DELAY   \t(1024)\n#define BC0_BYTES     \t(32)\n#define BC1_BYTES     \t(30)\n#define NUM_MB        \t(12)\n#define TIMEOUT_VALUE \t2000\n\nstatic void\nBFMWait (u32 cycle)\n{\n\tu32 i;\n\tfor (i = 0; i < cycle; i++);\n}\n\nstatic void\nWriteRegLong (u32 addr, u32 data)\n{\n\t//*((volatile u32 *)(addr)) =  data;\n\tIFX_MEI_WRITE_REGISTER_L (data, addr);\n}\n\nstatic u32\nReadRegLong (u32 addr)\n{\n\t// u32  rd_val;\n\t//rd_val = *((volatile u32 *)(addr));\n\t// return rd_val;\n\treturn IFX_MEI_READ_REGISTER_L (addr);\n}\n\n/* This routine writes the mailbox with the data in an input array */\nstatic void\nWriteMbox (u32 * mboxarray, u32 size)\n{\n\tIFX_MEI_DebugWrite (&dsl_devices[0], IMBOX_BASE, mboxarray, size);\n\tIFX_MEI_DMSG(\"write to %X\\n\", IMBOX_BASE);\n\tIFX_MEI_LongWordWriteOffset (&dsl_devices[0], (u32) ME_ME2ARC_INT, MEI_TO_ARC_MSGAV);\n}\n\n/* This routine reads the output mailbox and places the results into an array */\nstatic void\nReadMbox (u32 * mboxarray, u32 size)\n{\n\tIFX_MEI_DebugRead (&dsl_devices[0], OMBOX_BASE, mboxarray, size);\n\tIFX_MEI_DMSG(\"read from %X\\n\", OMBOX_BASE);\n}\n\nstatic void\nMEIWriteARCValue (u32 address, u32 value)\n{\n\tu32 i, check = 0;\n\n\t/* Write address register */\n\tIFX_MEI_WRITE_REGISTER_L (address,  ME_DBG_WR_AD + LTQ_MEI_BASE_ADDR);\n\n\t/* Write data register */\n\tIFX_MEI_WRITE_REGISTER_L (value, ME_DBG_DATA + LTQ_MEI_BASE_ADDR);\n\n\t/* wait until complete - timeout at 40 */\n\tfor (i = 0; i < 40; i++) {\n\t\tcheck = IFX_MEI_READ_REGISTER_L (ME_ARC2ME_STAT + LTQ_MEI_BASE_ADDR);\n\n\t\tif ((check & ARC_TO_MEI_DBG_DONE))\n\t\t\tbreak;\n\t}\n\t/* clear the flag */\n\tIFX_MEI_WRITE_REGISTER_L (ARC_TO_MEI_DBG_DONE, ME_ARC2ME_STAT + LTQ_MEI_BASE_ADDR);\n}\n\nvoid\narc_code_page_download (uint32_t arc_code_length, uint32_t * start_address)\n{\n\tint count;\n\n\tIFX_MEI_DMSG(\"try to download pages,size=%d\\n\", arc_code_length);\n\tIFX_MEI_ControlModeSet (&dsl_devices[0], MEI_MASTER_MODE);\n\tIFX_MEI_HaltArc (&dsl_devices[0]);\n\tIFX_MEI_LongWordWriteOffset (&dsl_devices[0], (u32) ME_DX_AD, 0);\n\tfor (count = 0; count < arc_code_length; count++) {\n\t\tIFX_MEI_LongWordWriteOffset (&dsl_devices[0], (u32) ME_DX_DATA,\n\t\t\t\t\t\t   *(start_address + count));\n\t}\n\tIFX_MEI_ControlModeSet (&dsl_devices[0], JTAG_MASTER_MODE);\n}\nstatic int\nload_jump_table (unsigned long addr)\n{\n\tint i;\n\tuint32_t addr_le, addr_be;\n\tuint32_t jump_table[32];\n\n\tfor (i = 0; i < 16; i++) {\n\t\taddr_le = i * 8 + addr;\n\t\taddr_be = ((addr_le >> 16) & 0xffff);\n\t\taddr_be |= ((addr_le & 0xffff) << 16);\n\t\tjump_table[i * 2 + 0] = 0x0f802020;\n\t\tjump_table[i * 2 + 1] = addr_be;\n\t\t//printk(\"jt %X %08X %08X\\n\",i,jump_table[i*2+0],jump_table[i*2+1]);\n\t}\n\tarc_code_page_download (32, &jump_table[0]);\nreturn 0;\n}\n\nint got_int = 0;\n\nvoid\ndfe_loopback_irq_handler (DSL_DEV_Device_t *pDev)\n{\n\tuint32_t rd_mbox[10];\n\n\tmemset (&rd_mbox[0], 0, 10 * 4);\n\tReadMbox (&rd_mbox[0], 6);\n\tif (rd_mbox[0] == 0x0) {\n\t\tFX_MEI_DMSG(\"Get ARC_ACK\\n\");\n\t\tgot_int = 1;\n\t}\n\telse if (rd_mbox[0] == 0x5) {\n\t\tIFX_MEI_DMSG(\"Get ARC_BUSY\\n\");\n\t\tgot_int = 2;\n\t}\n\telse if (rd_mbox[0] == 0x3) {\n\t\tIFX_MEI_DMSG(\"Get ARC_EDONE\\n\");\n\t\tif (rd_mbox[1] == 0x0) {\n\t\t\tgot_int = 3;\n\t\t\tIFX_MEI_DMSG(\"Get E_MEMTEST\\n\");\n\t\t\tif (rd_mbox[2] != 0x1) {\n\t\t\t\tgot_int = 4;\n\t\t\t\tIFX_MEI_DMSG(\"Get Result %X\\n\", rd_mbox[2]);\n\t\t\t}\n\t\t}\n\t}\n\tIFX_MEI_LongWordWriteOffset (&dsl_devices[0], (u32) ME_ARC2ME_STAT,\n\t\tARC_TO_MEI_DBG_DONE);\n\tMEI_MASK_AND_ACK_IRQ (pDev->nIrq[IFX_DFEIR]);\n\tdisable_irq (pDev->nIrq[IFX_DFEIR]);\n\t//got_int = 1;\n\treturn;\n}\n\nstatic void\nwait_mem_test_result (void)\n{\n\tuint32_t mbox[5];\n\tmbox[0] = 0;\n\n\tIFX_MEI_DMSG(\"Waiting Starting\\n\");\n\twhile (mbox[0] == 0) {\n\t\tReadMbox (&mbox[0], 5);\n\t}\n\tIFX_MEI_DMSG(\"Try to get mem test result.\\n\");\n\tReadMbox (&mbox[0], 5);\n\tif (mbox[0] == 0xA) {\n\t\tIFX_MEI_DMSG(\"Success.\\n\");\n\t}\n\telse if (mbox[0] == 0xA) {\n\t\tIFX_MEI_EMSG(\"Fail,address %X,except data %X,receive data %X\\n\",\n\t\t\tmbox[1], mbox[2], mbox[3]);\n\t}\n\telse {\n\t\tIFX_MEI_EMSG(\"Fail\\n\");\n\t}\n}\n\nstatic int\narc_ping_testing (DSL_DEV_Device_t *pDev)\n{\n#define MEI_PING 0x00000001\n\tuint32_t wr_mbox[10], rd_mbox[10];\n\tint i;\n\n\tfor (i = 0; i < 10; i++) {\n\t\twr_mbox[i] = 0;\n\t\trd_mbox[i] = 0;\n\t}\n\n\tFX_MEI_DMSG(\"send ping msg\\n\");\n\twr_mbox[0] = MEI_PING;\n\tWriteMbox (&wr_mbox[0], 10);\n\n\twhile (got_int == 0) {\n\t\tMEI_WAIT (100);\n\t}\n\n\tIFX_MEI_DMSG(\"send start event\\n\");\n\tgot_int = 0;\n\n\twr_mbox[0] = 0x4;\n\twr_mbox[1] = 0;\n\twr_mbox[2] = 0;\n\twr_mbox[3] = (uint32_t) 0xf5acc307e;\n\twr_mbox[4] = 5;\n\twr_mbox[5] = 2;\n\twr_mbox[6] = 0x1c000;\n\twr_mbox[7] = 64;\n\twr_mbox[8] = 0;\n\twr_mbox[9] = 0;\n\tWriteMbox (&wr_mbox[0], 10);\n\tDSL_ENABLE_IRQ (pDev->nIrq[IFX_DFEIR]);\n\t//printk(\"IFX_MEI_MailboxWrite ret=%d\\n\",i);\n\tIFX_MEI_LongWordWriteOffset (&dsl_devices[0],\n\t\t\t\t\t   (u32) ME_ME2ARC_INT,\n\t\t\t\t\t   MEI_TO_ARC_MSGAV);\n\tIFX_MEI_DMSG(\"sleeping\\n\");\n\twhile (1) {\n\t\tif (got_int > 0) {\n\n\t\t\tif (got_int > 3)\n\t\t\t\tIFX_MEI_DMSG(\"got_int >>>> 3\\n\");\n\t\t\telse\n\t\t\t\tIFX_MEI_DMSG(\"got int = %d\\n\", got_int);\n\t\t\tgot_int = 0;\n\t\t\t//schedule();\n\t\t\tDSL_ENABLE_IRQ (pDev->nIrq[IFX_DFEIR]);\n\t\t}\n\t\t//mbox_read(&rd_mbox[0],6);\n\t\tMEI_WAIT (100);\n\t}\n\treturn 0;\n}\n\nstatic DSL_DEV_MeiError_t\nDFE_Loopback_Test (void)\n{\n\tint i = 0;\n\tu32 arc_debug_data = 0, temp;\n\tDSL_DEV_Device_t *pDev = &dsl_devices[0];\n\tuint32_t wr_mbox[10];\n\n\tIFX_MEI_ResetARC (pDev);\n\t// start the clock\n\tarc_debug_data = ACL_CLK_MODE_ENABLE;\n\tIFX_MEI_DebugWrite (pDev, CRI_CCR0, &arc_debug_data, 1);\n\n#if defined( DFE_PING_TEST )|| defined( DFE_ATM_LOOPBACK)\n\t// WriteARCreg(AUX_XMEM_LTEST,0);\n\tIFX_MEI_ControlModeSet (pDev, MEI_MASTER_MODE);\n#define AUX_XMEM_LTEST 0x128\n\t_IFX_MEI_DBGLongWordWrite (pDev, MEI_DEBUG_DEC_AUX_MASK,  AUX_XMEM_LTEST, 0);\n\tIFX_MEI_ControlModeSet (pDev, JTAG_MASTER_MODE);\n\n\t// WriteARCreg(AUX_XDMA_GAP,0);\n\tIFX_MEI_ControlModeSet (pDev, MEI_MASTER_MODE);\n#define AUX_XDMA_GAP 0x114\n\t_IFX_MEI_DBGLongWordWrite (pDev, MEI_DEBUG_DEC_AUX_MASK, AUX_XDMA_GAP, 0);\n\tIFX_MEI_ControlModeSet (pDev, JTAG_MASTER_MODE);\n\n\tIFX_MEI_ControlModeSet (pDev, MEI_MASTER_MODE);\n\ttemp = 0;\n\t_IFX_MEI_DBGLongWordWrite (pDev, MEI_DEBUG_DEC_AUX_MASK,\n\t\t(u32) ME_XDATA_BASE_SH +  LTQ_MEI_BASE_ADDR, temp);\n\tIFX_MEI_ControlModeSet (pDev, JTAG_MASTER_MODE);\n\n\ti = IFX_MEI_DFEMemoryAlloc (pDev, SDRAM_SEGMENT_SIZE * 16);\n\tif (i >= 0) {\n\t\tint idx;\n\n\t\tfor (idx = 0; idx < i; idx++) {\n\t\t\tDSL_DEV_PRIVATE(pDev)->adsl_mem_info[idx].type = FREE_RELOAD;\n\t\t\tIFX_MEI_WRITE_REGISTER_L ((((uint32_t) DSL_DEV_PRIVATE(pDev)->adsl_mem_info[idx].address) & 0x0fffffff),\n\t\t\t\t\t\t\tLTQ_MEI_BASE_ADDR + ME_XMEM_BAR_BASE  + idx * 4);\n\t\t\tIFX_MEI_DMSG(\"bar%d(%X)=%X\\n\", idx,\n\t\t\t\tLTQ_MEI_BASE_ADDR + ME_XMEM_BAR_BASE  +\n\t\t\t\tidx * 4, (((uint32_t)\n\t\t\t\t\t   ((ifx_mei_device_private_t *)\n\t\t\t\t\t    pDev->pPriv)->adsl_mem_info[idx].\n\t\t\t\t\t   address) & 0x0fffffff));\n\t\t\tmemset ((u8 *) DSL_DEV_PRIVATE(pDev)->adsl_mem_info[idx].address, 0, SDRAM_SEGMENT_SIZE);\n\t\t}\n\n\t\tIFX_MEI_LongWordWriteOffset (pDev, (u32) ME_XDATA_BASE_SH,\n\t\t\t\t\t   ((unsigned long) DSL_DEV_PRIVATE(pDev)->adsl_mem_info[XDATA_REGISTER].address) & 0x0FFFFFFF);\n\t}\n\telse {\n\t\tIFX_MEI_EMSG (\"cannot load image: no memory\\n\");\n\t\treturn DSL_DEV_MEI_ERR_FAILURE;\n\t}\n\t//WriteARCreg(AUX_IC_CTRL,2);\n\tIFX_MEI_DMSG(\"Setting MEI_MASTER_MODE..\\n\");\n\tIFX_MEI_ControlModeSet (pDev, MEI_MASTER_MODE);\n#define AUX_IC_CTRL 0x11\n\t_IFX_MEI_DBGLongWordWrite (pDev, MEI_DEBUG_DEC_AUX_MASK,\n\t\t\t\t\t AUX_IC_CTRL, 2);\n\tIFX_MEI_DMSG(\"Setting JTAG_MASTER_MODE..\\n\");\n\tIFX_MEI_ControlModeSet (pDev, JTAG_MASTER_MODE);\n\n\tIFX_MEI_DMSG(\"Halting ARC...\\n\");\n\tIFX_MEI_HaltArc (&dsl_devices[0]);\n\n#ifdef DFE_PING_TEST\n\n\tIFX_MEI_DMSG(\"ping test image size=%d\\n\", sizeof (arc_ahb_access_code));\n\tmemcpy ((u8 *) (DSL_DEV_PRIVATE(pDev)->\n\t\t\tadsl_mem_info[0].address + 0x1004),\n\t\t&arc_ahb_access_code[0], sizeof (arc_ahb_access_code));\n\tload_jump_table (0x80000 + 0x1004);\n\n#endif //DFE_PING_TEST\n\n\tIFX_MEI_DMSG(\"ARC ping test code download complete\\n\");\n#endif //defined( DFE_PING_TEST )|| defined( DFE_ATM_LOOPBACK)\n#ifdef DFE_MEM_TEST\n\tIFX_MEI_LongWordWriteOffset (&dsl_devices[0], (u32) ME_ARC2ME_MASK, MSGAV_EN);\n\n\tarc_code_page_download (1537, &code_array[0]);\n\tIFX_MEI_DMSG(\"ARC mem test code download complete\\n\");\n#endif //DFE_MEM_TEST\n#ifdef DFE_ATM_LOOPBACK\n\tarc_debug_data = 0xf;\n\tarc_code_page_download (sizeof(code_array) / sizeof(*code_array), &code_array[0]);\n\twr_mbox[0] = 0;\t    //TIMER_DELAY   - org: 1024\n\twr_mbox[1] = 0;\t\t//TXFB_START0\n\twr_mbox[2] = 0x7f;\t//TXFB_END0     - org: 49\n\twr_mbox[3] = 0x80;\t//TXFB_START1   - org: 80\n\twr_mbox[4] = 0xff;\t//TXFB_END1     - org: 109\n\twr_mbox[5] = 0x100;\t//RXFB_START0   - org: 0\n\twr_mbox[6] = 0x17f;\t//RXFB_END0     - org: 49\n\twr_mbox[7] = 0x180;\t//RXFB_START1   - org: 256\n\twr_mbox[8] = 0x1ff;\t//RXFB_END1     - org: 315\n\tWriteMbox (&wr_mbox[0], 9);\n\t// Start Iridia IT_AMODE (in dmp access) why is it required?\n\tIFX_MEI_DebugWrite (&dsl_devices[0], 0x32010, &arc_debug_data, 1);\n#endif //DFE_ATM_LOOPBACK\n\tIFX_MEI_IRQEnable (pDev);\n\tIFX_MEI_DMSG(\"run ARC...\\n\");\n\tIFX_MEI_RunArc (&dsl_devices[0]);\n\n#ifdef DFE_PING_TEST\n\tarc_ping_testing (pDev);\n#endif //DFE_PING_TEST\n#ifdef DFE_MEM_TEST\n\twait_mem_test_result ();\n#endif //DFE_MEM_TEST\n\n\tIFX_MEI_DFEMemoryFree (pDev, FREE_ALL);\n\treturn DSL_DEV_MEI_ERR_SUCCESS;\n}\n\n#endif //CONFIG_AMAZON_S_MEI_FW_LOOPBACK\n\nstatic int\nIFX_MEI_InitDevNode (int num)\n{\n\tif (num == 0) {\n\t\tif ((dev_major = register_chrdev (dev_major, IFX_MEI_DEVNAME, &bsp_mei_operations)) < 0) {\n\t\t\tIFX_MEI_EMSG (\"register_chrdev(%d %s) failed!\\n\", dev_major, IFX_MEI_DEVNAME);\n\t\t\treturn -ENODEV;\n\t\t}\n\t}\n\treturn 0;\n}\n\nstatic int\nIFX_MEI_CleanUpDevNode (int num)\n{\n\tif (num == 0)\n\t\tunregister_chrdev (dev_major, MEI_DIRNAME);\n\treturn 0;\n}\n\nstatic int\nIFX_MEI_InitDevice (int num)\n{\n\tDSL_DEV_Device_t *pDev;\n        u32 temp;\n\tpDev = &dsl_devices[num];\n\tif (pDev == NULL)\n\t\treturn -ENOMEM;\n\tpDev->pPriv = &sDanube_Mei_Private[num];\n\tmemset (pDev->pPriv, 0, sizeof (ifx_mei_device_private_t));\n\n\tmemset (&DSL_DEV_PRIVATE(pDev)->\n\t\tadsl_mem_info[0], 0,\n\t\tsizeof (smmu_mem_info_t) * MAX_BAR_REGISTERS);\n\n\tif (num == 0) {\n\t\tpDev->nIrq[IFX_DFEIR]      = LTQ_MEI_INT;\n\t\tpDev->nIrq[IFX_DYING_GASP] = LTQ_MEI_DYING_GASP_INT;\n\t\tpDev->base_address = KSEG1 + LTQ_MEI_BASE_ADDR;\n\n                /* Power up MEI */\n#ifdef CONFIG_LANTIQ_AMAZON_SE\n\t\t*LTQ_PMU_PWDCR &= ~(1 << 9);  // enable dsl\n\t\t*LTQ_PMU_PWDCR &= ~(1 << 15); // enable AHB base\n#endif\n\t\ttemp = ltq_r32(LTQ_PMU_PWDCR);\n\t\ttemp &= 0xffff7dbe;\n\t\tltq_w32(temp, LTQ_PMU_PWDCR);\n\t}\n\tpDev->nInUse = 0;\n\tDSL_DEV_PRIVATE(pDev)->modem_ready = 0;\n\tDSL_DEV_PRIVATE(pDev)->arcmsgav = 0;\n\n\tMEI_INIT_WAKELIST (\"arcq\", DSL_DEV_PRIVATE(pDev)->wait_queue_arcmsgav);\t// for ARCMSGAV\n\tMEI_INIT_WAKELIST (\"arcr\", DSL_DEV_PRIVATE(pDev)->wait_queue_modemready);\t// for arc modem ready\n\n\tMEI_MUTEX_INIT (DSL_DEV_PRIVATE(pDev)->mei_cmv_sema, 1);\t// semaphore initialization, mutex\n#if 0\n\tMEI_MASK_AND_ACK_IRQ (pDev->nIrq[IFX_DFEIR]);\n\tMEI_MASK_AND_ACK_IRQ (pDev->nIrq[IFX_DYING_GASP]);\n#endif\n\tif (request_irq (pDev->nIrq[IFX_DFEIR], IFX_MEI_IrqHandle, 0, \"DFEIR\", pDev) != 0) {\n\t\tIFX_MEI_EMSG (\"request_irq %d failed!\\n\", pDev->nIrq[IFX_DFEIR]);\n\t\treturn -1;\n\t}\n\t/*if (request_irq (pDev->nIrq[IFX_DYING_GASP], IFX_MEI_Dying_Gasp_IrqHandle, 0, \"DYING_GASP\", pDev) != 0) {\n\t\tIFX_MEI_EMSG (\"request_irq %d failed!\\n\", pDev->nIrq[IFX_DYING_GASP]);\n\t\treturn -1;\n\t}*/\n//\tIFX_MEI_DMSG(\"Device %d initialized. IER %#x\\n\", num, bsp_get_irq_ier(pDev->nIrq[IFX_DYING_GASP]));\n\treturn 0;\n}\n\nstatic int\nIFX_MEI_ExitDevice (int num)\n{\n\tDSL_DEV_Device_t *pDev;\n\tpDev = &dsl_devices[num];\n\n\tif (pDev == NULL)\n\t\treturn -EIO;\n\n\tdisable_irq (pDev->nIrq[IFX_DFEIR]);\n\tdisable_irq (pDev->nIrq[IFX_DYING_GASP]);\n\n\tfree_irq(pDev->nIrq[IFX_DFEIR], pDev);\n\tfree_irq(pDev->nIrq[IFX_DYING_GASP], pDev);\n\n\treturn 0;\n}\n\nstatic DSL_DEV_Device_t *\nIFX_BSP_HandleGet (int maj, int num)\n{\n\tif (num > BSP_MAX_DEVICES)\n\t\treturn NULL;\n\treturn &dsl_devices[num];\n}\n\nDSL_DEV_Device_t *\nDSL_BSP_DriverHandleGet (int maj, int num)\n{\n\tDSL_DEV_Device_t *pDev;\n\n\tif (num > BSP_MAX_DEVICES)\n\t\treturn NULL;\n\n\tpDev = &dsl_devices[num];\n\tif (!try_module_get(pDev->owner))\n\t\treturn NULL;\n\n\tpDev->nInUse++;\n\treturn pDev;\n}\n\nint\nDSL_BSP_DriverHandleDelete (DSL_DEV_Device_t * nHandle)\n{\n\tDSL_DEV_Device_t *pDev = (DSL_DEV_Device_t *) nHandle;\n\tif (pDev->nInUse)\n\t\tpDev->nInUse--;\n        module_put(pDev->owner);\n\treturn 0;\n}\n\nstatic int\nIFX_MEI_Open (DSL_DRV_inode_t * ino, DSL_DRV_file_t * fil)\n{\n\tint maj = MAJOR (ino->i_rdev);\n\tint num = MINOR (ino->i_rdev);\n\n\tDSL_DEV_Device_t *pDev = NULL;\n\tif ((pDev = DSL_BSP_DriverHandleGet (maj, num)) == NULL) {\n\t\tIFX_MEI_EMSG(\"open(%d:%d) fail!\\n\", maj, num);\n\t\treturn -EIO;\n\t}\n\tfil->private_data = pDev;\n\treturn 0;\n}\n\nstatic int\nIFX_MEI_Release (DSL_DRV_inode_t * ino, DSL_DRV_file_t * fil)\n{\n\t//int maj = MAJOR(ino->i_rdev);\n\tint num = MINOR (ino->i_rdev);\n\tDSL_DEV_Device_t *pDev;\n\n\tpDev = &dsl_devices[num];\n\tif (pDev == NULL)\n\t\treturn -EIO;\n\tDSL_BSP_DriverHandleDelete (pDev);\n\treturn 0;\n}\n\n/**\n * Callback function for linux userspace program writing\n */\nstatic ssize_t\nIFX_MEI_Write (DSL_DRV_file_t * filp, const char *buf, size_t size, loff_t * loff)\n{\n\tDSL_DEV_MeiError_t mei_error = DSL_DEV_MEI_ERR_FAILURE;\n\tlong offset = 0;\n\tDSL_DEV_Device_t *pDev = (DSL_DEV_Device_t *) filp->private_data;\n\n\tif (pDev == NULL)\n\t\treturn -EIO;\n\n\tmei_error =\n\t\tDSL_BSP_FWDownload (pDev, buf, size, (long *) loff,  &offset);\n\n\tif (mei_error == DSL_DEV_MEI_ERR_FAILURE)\n\t\treturn -EIO;\n\treturn (ssize_t) offset;\n}\n\n/**\n * Callback function for linux userspace program ioctling\n */\nstatic int\nIFX_MEI_IoctlCopyFrom (int from_kernel, char *dest, char *from, int size)\n{\n\tint ret = 0;\n\n\tif (!from_kernel)\n\t\tret = copy_from_user ((char *) dest, (char *) from, size);\n\telse\n\t\tret = (int)memcpy ((char *) dest, (char *) from, size);\n\treturn ret;\n}\n\nstatic int\nIFX_MEI_IoctlCopyTo (int from_kernel, char *dest, char *from, int size)\n{\n\tint ret = 0;\n\n\tif (!from_kernel)\n\t\tret = copy_to_user ((char *) dest, (char *) from, size);\n\telse\n\t\tret = (int)memcpy ((char *) dest, (char *) from, size);\n\treturn ret;\n}\n\nint\nIFX_MEI_Ioctls (DSL_DEV_Device_t * pDev, int from_kernel, unsigned int command, unsigned long lon)\n{\n\tint i = 0;\n\tint meierr = DSL_DEV_MEI_ERR_SUCCESS;\n\tu32 base_address = LTQ_MEI_BASE_ADDR;\n\tDSL_DEV_WinHost_Message_t winhost_msg, m;\n//\tDSL_DEV_MeiDebug_t debugrdwr;\n\tDSL_DEV_MeiReg_t regrdwr;\n\n\tswitch (command) {\n\n\tcase DSL_FIO_BSP_CMV_WINHOST:\n\t\tIFX_MEI_IoctlCopyFrom (from_kernel, (char *) winhost_msg.msg.TxMessage,\n\t\t\t\t\t     (char *) lon, MSG_LENGTH * 2);\n\n\t\tif ((meierr = DSL_BSP_SendCMV (pDev, winhost_msg.msg.TxMessage, YES_REPLY,\n\t\t\t\t\t   winhost_msg.msg.RxMessage)) != DSL_DEV_MEI_ERR_SUCCESS) {\n\t\t\tIFX_MEI_EMSG (\"WINHOST CMV fail :TxMessage:%X %X %X %X, RxMessage:%X %X %X %X %X\\n\",\n\t\t\t\t winhost_msg.msg.TxMessage[0], winhost_msg.msg.TxMessage[1], winhost_msg.msg.TxMessage[2], winhost_msg.msg.TxMessage[3],\n\t\t\t\t winhost_msg.msg.RxMessage[0], winhost_msg.msg.RxMessage[1], winhost_msg.msg.RxMessage[2], winhost_msg.msg.RxMessage[3],\n\t\t\t\t winhost_msg.msg.RxMessage[4]);\n\t\t\tmeierr = DSL_DEV_MEI_ERR_FAILURE;\n\t\t}\n\t\telse {\n\t\t\tIFX_MEI_IoctlCopyTo (from_kernel, (char *) lon,\n\t\t\t\t\t\t   (char *) winhost_msg.msg.RxMessage,\n\t\t\t\t\t\t   MSG_LENGTH * 2);\n\t\t}\n\t\tbreak;\n\n\tcase DSL_FIO_BSP_CMV_READ:\n\t\tIFX_MEI_IoctlCopyFrom (from_kernel, (char *) (&regrdwr),\n\t\t\t\t\t     (char *) lon, sizeof (DSL_DEV_MeiReg_t));\n\n\t\tIFX_MEI_LongWordRead ((u32) regrdwr.iAddress,\n\t\t\t\t\t    (u32 *) & (regrdwr.iData));\n\n\t\tIFX_MEI_IoctlCopyTo (from_kernel, (char *) lon,\n\t\t\t\t\t   (char *) (&regrdwr),\n\t\t\t\t\t   sizeof (DSL_DEV_MeiReg_t));\n\n\t\tbreak;\n\n\tcase DSL_FIO_BSP_CMV_WRITE:\n\t\tIFX_MEI_IoctlCopyFrom (from_kernel, (char *) (&regrdwr),\n\t\t\t\t\t     (char *) lon, sizeof (DSL_DEV_MeiReg_t));\n\n\t\tIFX_MEI_LongWordWrite ((u32) regrdwr.iAddress,\n\t\t\t\t\t     regrdwr.iData);\n\t\tbreak;\n\n\tcase DSL_FIO_BSP_GET_BASE_ADDRESS:\n\t\tIFX_MEI_IoctlCopyTo (from_kernel, (char *) lon,\n\t\t\t\t\t   (char *) (&base_address),\n\t\t\t\t\t   sizeof (base_address));\n\t\tbreak;\n\n\tcase DSL_FIO_BSP_IS_MODEM_READY:\n\t\ti = IFX_MEI_IsModemReady (pDev);\n\t\tIFX_MEI_IoctlCopyTo (from_kernel, (char *) lon,\n\t\t\t\t\t   (char *) (&i), sizeof (int));\n\t\tmeierr = DSL_DEV_MEI_ERR_SUCCESS;\n\t\tbreak;\n\tcase DSL_FIO_BSP_RESET:\n\tcase DSL_FIO_BSP_REBOOT:\n\t\tmeierr = IFX_MEI_CpuModeSet (pDev, DSL_CPU_RESET);\n\t\tmeierr = IFX_MEI_CpuModeSet (pDev, DSL_CPU_HALT);\n\t\tbreak;\n\n\tcase DSL_FIO_BSP_HALT:\n\t\tmeierr = IFX_MEI_CpuModeSet (pDev, DSL_CPU_HALT);\n\t\tbreak;\n\n\tcase DSL_FIO_BSP_RUN:\n\t\tmeierr = IFX_MEI_CpuModeSet (pDev, DSL_CPU_RUN);\n\t\tbreak;\n\tcase DSL_FIO_BSP_BOOTDOWNLOAD:\n\t\tmeierr = IFX_MEI_DownloadBootCode (pDev);\n\t\tbreak;\n\tcase DSL_FIO_BSP_JTAG_ENABLE:\n\t\tmeierr = IFX_MEI_ArcJtagEnable (pDev, 1);\n\t\tbreak;\n\n\tcase DSL_FIO_BSP_REMOTE:\n\t\tIFX_MEI_IoctlCopyFrom (from_kernel, (char *) (&i),\n\t\t\t\t\t     (char *) lon, sizeof (int));\n\n\t\tmeierr = IFX_MEI_AdslMailboxIRQEnable (pDev, i);\n\t\tbreak;\n\n\tcase DSL_FIO_BSP_DSL_START:\n\t\tIFX_MEI_DMSG(\"DSL_FIO_BSP_DSL_START\\n\");\n\t\tif ((meierr = IFX_MEI_RunAdslModem (pDev)) != DSL_DEV_MEI_ERR_SUCCESS) {\n\t\t\tIFX_MEI_EMSG (\"IFX_MEI_RunAdslModem() error...\");\n\t\t\tmeierr = DSL_DEV_MEI_ERR_FAILURE;\n\t\t}\n\t\tbreak;\n\n/*\tcase DSL_FIO_BSP_DEBUG_READ:\n\tcase DSL_FIO_BSP_DEBUG_WRITE:\n\t\tIFX_MEI_IoctlCopyFrom (from_kernel,\n\t\t\t\t\t     (char *) (&debugrdwr),\n\t\t\t\t\t     (char *) lon,\n\t\t\t\t\t     sizeof (debugrdwr));\n\n\t\tif (command == DSL_FIO_BSP_DEBUG_READ)\n\t\t\tmeierr = DSL_BSP_MemoryDebugAccess (pDev,\n\t\t\t\t\t\t\t\t DSL_BSP_MEMORY_READ,\n\t\t\t\t\t\t\t\t debugrdwr.\n\t\t\t\t\t\t\t\t iAddress,\n\t\t\t\t\t\t\t\t debugrdwr.\n\t\t\t\t\t\t\t\t buffer,\n\t\t\t\t\t\t\t\t debugrdwr.\n\t\t\t\t\t\t\t\t iCount);\n\t\telse\n\t\t\tmeierr = DSL_BSP_MemoryDebugAccess (pDev,\n\t\t\t\t\t\t\t\t DSL_BSP_MEMORY_WRITE,\n\t\t\t\t\t\t\t\t debugrdwr.\n\t\t\t\t\t\t\t\t iAddress,\n\t\t\t\t\t\t\t\t debugrdwr.\n\t\t\t\t\t\t\t\t buffer,\n\t\t\t\t\t\t\t\t debugrdwr.\n\t\t\t\t\t\t\t\t iCount);\n\n\t\tIFX_MEI_IoctlCopyTo (from_kernel, (char *) lon, (char *) (&debugrdwr), sizeof (debugrdwr));\n\t\tbreak;*/\n\tcase DSL_FIO_BSP_GET_VERSION:\n\t\tIFX_MEI_IoctlCopyTo (from_kernel, (char *) lon, (char *) (&bsp_mei_version), sizeof (DSL_DEV_Version_t));\n\t\tbreak;\n\n#define LTQ_MPS_CHIPID_VERSION_GET(value)  (((value) >> 28) & ((1 << 4) - 1))\n\tcase DSL_FIO_BSP_GET_CHIP_INFO:\n                bsp_chip_info.major = 1;\n                bsp_chip_info.minor = LTQ_MPS_CHIPID_VERSION_GET(*LTQ_MPS_CHIPID);\n                IFX_MEI_IoctlCopyTo (from_kernel, (char *) lon, (char *) (&bsp_chip_info), sizeof (DSL_DEV_HwVersion_t));\n                meierr = DSL_DEV_MEI_ERR_SUCCESS;\n\t\tbreak;\n\n        case DSL_FIO_BSP_FREE_RESOURCE:\n                makeCMV (H2D_CMV_READ, DSL_CMV_GROUP_STAT, 4, 0, 1, NULL, m.msg.TxMessage);\n                if (DSL_BSP_SendCMV (pDev, m.msg.TxMessage, YES_REPLY, m.msg.RxMessage) != DSL_DEV_MEI_ERR_SUCCESS) {\n                        meierr = DSL_DEV_MEI_ERR_FAILURE;\n                        return -EIO;\n                }\n                IFX_MEI_DMSG(\"RxMessage[4] = %#x\\n\", m.msg.RxMessage[4]);\n                if (!(m.msg.RxMessage[4] & DSL_DEV_STAT_CODESWAP_COMPLETE)) {\n                        meierr = DSL_DEV_MEI_ERR_FAILURE;\n                        return -EAGAIN;\n                }\n                IFX_MEI_DMSG(\"Freeing all memories marked FREE_SHOWTIME\\n\");\n                IFX_MEI_DFEMemoryFree (pDev, FREE_SHOWTIME);\n                meierr = DSL_DEV_MEI_ERR_SUCCESS;\n\t\tbreak;\n#ifdef CONFIG_IFXMIPS_AMAZON_SE\n\tcase DSL_FIO_ARC_MUX_TEST:\n\t\tAMAZON_SE_MEI_ARC_MUX_Test();\n\t\tbreak;\n#endif\n\tdefault:\n//\t\tIFX_MEI_EMSG(\"Invalid IOCTL command: %d\\n\");\n\t\tbreak;\n\t}\n\treturn meierr;\n}\n\n#ifdef CONFIG_IFXMIPS_AMAZON_SE\nvoid AMAZON_SE_MEI_ARC_MUX_Test(void)\n{\n\tu32 *p, i;\n\t*LTQ_RCU_RST |= LTQ_RCU_RST_REQ_MUX_ARC;\n\n\tp = (u32*)(DFE_LDST_BASE_ADDR + IRAM0_BASE);\n\tIFX_MEI_EMSG(\"Writing to IRAM0(%p)...\\n\", p);\n\tfor (i = 0; i < IRAM0_SIZE/sizeof(u32); i++, p++) {\n\t\t*p = 0xdeadbeef;\n\t\tif (*p != 0xdeadbeef)\n\t\t\tIFX_MEI_EMSG(\"%p: %#x\\n\", p, *p);\n\t}\n\n\tp = (u32*)(DFE_LDST_BASE_ADDR + IRAM1_BASE);\n\tIFX_MEI_EMSG(\"Writing to IRAM1(%p)...\\n\", p);\n\tfor (i = 0; i < IRAM1_SIZE/sizeof(u32); i++, p++) {\n\t\t*p = 0xdeadbeef;\n\t\tif (*p != 0xdeadbeef)\n\t\t\tIFX_MEI_EMSG(\"%p: %#x\\n\", p, *p);\n\t}\n\n\tp = (u32*)(DFE_LDST_BASE_ADDR + BRAM_BASE);\n\tIFX_MEI_EMSG(\"Writing to BRAM(%p)...\\n\", p);\n\tfor (i = 0; i < BRAM_SIZE/sizeof(u32); i++, p++) {\n\t\t*p = 0xdeadbeef;\n\t\tif (*p != 0xdeadbeef)\n\t\t\tIFX_MEI_EMSG(\"%p: %#x\\n\", p, *p);\n\t}\n\n\tp = (u32*)(DFE_LDST_BASE_ADDR + XRAM_BASE);\n\tIFX_MEI_EMSG(\"Writing to XRAM(%p)...\\n\", p);\n\tfor (i = 0; i < XRAM_SIZE/sizeof(u32); i++, p++) {\n\t\t*p = 0xdeadbeef;\n\t\tif (*p != 0xdeadbeef)\n\t\t\tIFX_MEI_EMSG(\"%p: %#x\\n\", p, *p);\n\t}\n\n\tp = (u32*)(DFE_LDST_BASE_ADDR + YRAM_BASE);\n\tIFX_MEI_EMSG(\"Writing to YRAM(%p)...\\n\", p);\n\tfor (i = 0; i < YRAM_SIZE/sizeof(u32); i++, p++) {\n\t\t*p = 0xdeadbeef;\n\t\tif (*p != 0xdeadbeef)\n\t\t\tIFX_MEI_EMSG(\"%p: %#x\\n\", p, *p);\n\t}\n\n\tp = (u32*)(DFE_LDST_BASE_ADDR + EXT_MEM_BASE);\n\tIFX_MEI_EMSG(\"Writing to EXT_MEM(%p)...\\n\", p);\n\tfor (i = 0; i < EXT_MEM_SIZE/sizeof(u32); i++, p++) {\n\t\t*p = 0xdeadbeef;\n\t\tif (*p != 0xdeadbeef)\n\t\t\tIFX_MEI_EMSG(\"%p: %#x\\n\", p, *p);\n\t}\n\t*LTQ_RCU_RST &= ~LTQ_RCU_RST_REQ_MUX_ARC;\n}\n#endif\nint\nDSL_BSP_KernelIoctls (DSL_DEV_Device_t * pDev, unsigned int command,\n\t\t\t   unsigned long lon)\n{\n\tint error = 0;\n\n\terror = IFX_MEI_Ioctls (pDev, 1, command, lon);\n\treturn error;\n}\n\nstatic long\nIFX_MEI_UserIoctls (DSL_DRV_file_t * fil,\n\t\t\t  unsigned int command, unsigned long lon)\n{\n\tint error = 0;\n\tDSL_DEV_Device_t *pDev;\n\n\tpDev = IFX_BSP_HandleGet (0, 0);\n\tif (pDev == NULL)\n\t\treturn -EIO;\n\n\terror = IFX_MEI_Ioctls (pDev, 0, command, lon);\n\treturn error;\n}\n\nstatic int adsl_dummy_ledcallback(void)\n{\n    return 0;\n}\n\nint ifx_mei_atm_led_blink(void)\n{\n    return g_adsl_ledcallback();\n}\nEXPORT_SYMBOL(ifx_mei_atm_led_blink);\n\nint ifx_mei_atm_showtime_check(int *is_showtime, struct port_cell_info *port_cell, void **xdata_addr)\n{\n    int i;\n\n    if ( is_showtime ) {\n        *is_showtime = g_tx_link_rate[0] == 0 && g_tx_link_rate[1] == 0 ? 0 : 1;\n    }\n\n    if ( port_cell ) {\n        for ( i = 0; i < port_cell->port_num && i < 2; i++ )\n            port_cell->tx_link_rate[i] = g_tx_link_rate[i];\n    }\n\n    if ( xdata_addr ) {\n        if ( g_tx_link_rate[0] == 0 && g_tx_link_rate[1] == 0 )\n            *xdata_addr = NULL;\n        else\n            *xdata_addr = g_xdata_addr;\n    }\n\n    return 0;\n}\nEXPORT_SYMBOL(ifx_mei_atm_showtime_check);\n\n/*\n * Writing function for linux proc filesystem\n */\nstatic int ltq_mei_probe(struct platform_device *pdev)\n{\n\tint i = 0;\n\tstatic struct class *dsl_class;\n\n\tpr_info(\"IFX MEI Version %ld.%02ld.%02ld\\n\", bsp_mei_version.major, bsp_mei_version.minor, bsp_mei_version.revision);\n\n\tfor (i = 0; i < BSP_MAX_DEVICES; i++) {\n\t\tif (IFX_MEI_InitDevice (i) != 0) {\n\t\t\tIFX_MEI_EMSG(\"Init device fail!\\n\");\n\t\t\treturn -EIO;\n\t\t}\n\t\tIFX_MEI_InitDevNode (i);\n\t}\n\t\tfor (i = 0; i <= DSL_BSP_CB_LAST ; i++)\n\t\tdsl_bsp_event_callback[i].function = NULL;\n\n#ifdef CONFIG_LTQ_MEI_FW_LOOPBACK\n\tIFX_MEI_DMSG(\"Start loopback test...\\n\");\n\tDFE_Loopback_Test ();\n#endif\n\tdsl_class = class_create(THIS_MODULE, \"ifx_mei\");\n\tdevice_create(dsl_class, NULL, MKDEV(MEI_MAJOR, 0), NULL, \"ifx_mei\");\n\treturn 0;\n}\n\nstatic int ltq_mei_remove(struct platform_device *pdev)\n{\n\tint i = 0;\n\tint num;\n\n\tfor (num = 0; num < BSP_MAX_DEVICES; num++) {\n\t\tIFX_MEI_CleanUpDevNode (num);\n\t}\n\n\tfor (i = 0; i < BSP_MAX_DEVICES; i++) {\n\t\tfor (i = 0; i < BSP_MAX_DEVICES; i++) {\n\t\t\tIFX_MEI_ExitDevice (i);\n\t\t}\n\t}\n\treturn 0;\n}\n\nstatic const struct of_device_id ltq_mei_match[] = {\n\t{ .compatible = \"lantiq,mei-xway\"},\n\t{},\n};\n\nstatic struct platform_driver ltq_mei_driver = {\n\t.probe = ltq_mei_probe,\n\t.remove = ltq_mei_remove,\n\t.driver = {\n\t\t.name = \"lantiq,mei-xway\",\n\t\t.owner = THIS_MODULE,\n\t\t.of_match_table = ltq_mei_match,\n\t},\n};\n\nmodule_platform_driver(ltq_mei_driver);\n\n/* export function for DSL Driver */\n\n/* The functions of MEI_DriverHandleGet and MEI_DriverHandleDelete are\nsomething like open/close in kernel space , where the open could be used\nto register a callback for autonomous messages and returns a mei driver context pointer (comparable to the file descriptor in user space)\n   The context will be required for the multi line chips future! */\n\nEXPORT_SYMBOL (DSL_BSP_DriverHandleGet);\nEXPORT_SYMBOL (DSL_BSP_DriverHandleDelete);\n\nEXPORT_SYMBOL (DSL_BSP_ATMLedCBRegister);\nEXPORT_SYMBOL (DSL_BSP_ATMLedCBUnregister);\nEXPORT_SYMBOL (DSL_BSP_KernelIoctls);\nEXPORT_SYMBOL (DSL_BSP_AdslLedInit);\n//EXPORT_SYMBOL (DSL_BSP_AdslLedSet);\nEXPORT_SYMBOL (DSL_BSP_FWDownload);\nEXPORT_SYMBOL (DSL_BSP_Showtime);\n\nEXPORT_SYMBOL (DSL_BSP_MemoryDebugAccess);\nEXPORT_SYMBOL (DSL_BSP_SendCMV);\n\n// provide a register/unregister function for DSL driver to register a event callback function\nEXPORT_SYMBOL (DSL_BSP_EventCBRegister);\nEXPORT_SYMBOL (DSL_BSP_EventCBUnregister);\n\nMODULE_LICENSE(\"Dual BSD/GPL\");\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-adsl-mei/src/ifxmips_mei_interface.h",
    "content": "/******************************************************************************\n\n                               Copyright (c) 2009\n                            Infineon Technologies AG\n                     Am Campeon 1-12; 81726 Munich, Germany\n\n  For licensing information, see the file 'LICENSE' in the root folder of\n  this software module.\n\n******************************************************************************/\n\n#ifndef IFXMIPS_MEI_H\n#define IFXMIPS_MEI_H\n\n//#define CONFIG_AMAZON_SE 1\n//#define CONFIG_DANUBE 1\n//#define CONFIG_AR9 1\n\n#if !defined(CONFIG_DANUBE) && !defined(CONFIG_AMAZON_SE) && !defined(CONFIG_AR9) && !defined(CONFIG_VR9)\n#error Platform undefined!!!\n#endif\n\n#ifdef IFX_MEI_BSP\n/** This is the character datatype. */\ntypedef char            DSL_char_t;\n/** This is the unsigned 8-bit datatype. */\ntypedef unsigned char   DSL_uint8_t;\n/** This is the signed 8-bit datatype. */\ntypedef signed char     DSL_int8_t;\n/** This is the unsigned 16-bit datatype. */\ntypedef unsigned short  DSL_uint16_t;\n/** This is the signed 16-bit datatype. */\ntypedef signed short    DSL_int16_t;\n/** This is the unsigned 32-bit datatype. */\ntypedef unsigned long   DSL_uint32_t;\n/** This is the signed 32-bit datatype. */\ntypedef signed long     DSL_int32_t;\n/** This is the float datatype. */\ntypedef float           DSL_float_t;\n/** This is the void datatype. */\ntypedef void            DSL_void_t;\n/** integer type, width is depending on processor arch */\ntypedef int             DSL_int_t;\n/** unsigned integer type, width is depending on processor arch */\ntypedef unsigned int    DSL_uint_t;\ntypedef struct file DSL_DRV_file_t;\ntypedef struct inode DSL_DRV_inode_t;\n\n/**\n *    Defines all possible CMV groups\n *    */\ntypedef enum {\n   DSL_CMV_GROUP_CNTL = 1,\n   DSL_CMV_GROUP_STAT = 2,\n   DSL_CMV_GROUP_INFO = 3,\n   DSL_CMV_GROUP_TEST = 4,\n   DSL_CMV_GROUP_OPTN = 5,\n   DSL_CMV_GROUP_RATE = 6,\n   DSL_CMV_GROUP_PLAM = 7,\n   DSL_CMV_GROUP_CNFG = 8\n} DSL_CmvGroup_t;\n/**\n *    Defines all opcode types\n *    */\ntypedef enum {\n   H2D_CMV_READ = 0x00,\n   H2D_CMV_WRITE = 0x04,\n   H2D_CMV_INDICATE_REPLY = 0x10,\n   H2D_ERROR_OPCODE_UNKNOWN =0x20,\n   H2D_ERROR_CMV_UNKNOWN =0x30,\n\n   D2H_CMV_READ_REPLY =0x01,\n   D2H_CMV_WRITE_REPLY = 0x05,\n   D2H_CMV_INDICATE = 0x11,\n   D2H_ERROR_OPCODE_UNKNOWN = 0x21,\n   D2H_ERROR_CMV_UNKNOWN = 0x31,\n   D2H_ERROR_CMV_READ_NOT_AVAILABLE = 0x41,\n   D2H_ERROR_CMV_WRITE_ONLY = 0x51,\n   D2H_ERROR_CMV_READ_ONLY = 0x61,\n\n   H2D_DEBUG_READ_DM = 0x02,\n   H2D_DEBUG_READ_PM = 0x06,\n   H2D_DEBUG_WRITE_DM = 0x0a,\n   H2D_DEBUG_WRITE_PM = 0x0e,\n\n   D2H_DEBUG_READ_DM_REPLY = 0x03,\n   D2H_DEBUG_READ_FM_REPLY = 0x07,\n   D2H_DEBUG_WRITE_DM_REPLY = 0x0b,\n   D2H_DEBUG_WRITE_FM_REPLY = 0x0f,\n   D2H_ERROR_ADDR_UNKNOWN = 0x33,\n\n   D2H_AUTONOMOUS_MODEM_READY_MSG = 0xf1\n} DSL_CmvOpcode_t;\n\n/* mutex macros */\n#define MEI_MUTEX_INIT(id,flag) \\\n        sema_init(&id,flag)\n#define MEI_MUTEX_LOCK(id) \\\n        down_interruptible(&id)\n#define MEI_MUTEX_UNLOCK(id) \\\n        up(&id)\n#define MEI_WAIT(ms) \\\n        {\\\n                set_current_state(TASK_INTERRUPTIBLE);\\\n                schedule_timeout(ms);\\\n        }\n#define MEI_INIT_WAKELIST(name,queue) \\\n        init_waitqueue_head(&queue)\n\nstatic inline long\nugly_hack_sleep_on_timeout(wait_queue_head_t *q, long timeout)\n{\n\tunsigned long flags;\n\twait_queue_entry_t wait;\n\n\tinit_waitqueue_entry(&wait, current);\n\n\t__set_current_state(TASK_INTERRUPTIBLE);\n\tspin_lock_irqsave(&q->lock, flags);\n\t__add_wait_queue(q, &wait);\n\tspin_unlock(&q->lock);\n\n\ttimeout = schedule_timeout(timeout);\n\n\tspin_lock_irq(&q->lock);\n\t__remove_wait_queue(q, &wait);\n\tspin_unlock_irqrestore(&q->lock, flags);\n\n\treturn timeout;\n}\n\n/* wait for an event, timeout is measured in ms */\n#define MEI_WAIT_EVENT_TIMEOUT(ev,timeout)\\\n        ugly_hack_sleep_on_timeout(&ev, timeout * HZ / 1000)\n#define MEI_WAKEUP_EVENT(ev)\\\n        wake_up_interruptible(&ev)\n#endif /* IFX_MEI_BSP */\n\n/***\tRegister address offsets, relative to MEI_SPACE_ADDRESS ***/\n#define ME_DX_DATA\t\t\t\t(0x0000)\n#define\tME_VERSION\t\t\t\t(0x0004)\n#define\tME_ARC_GP_STAT\t\t\t\t(0x0008)\n#define ME_DX_STAT\t\t\t\t(0x000C)\n#define\tME_DX_AD\t\t\t\t(0x0010)\n#define ME_DX_MWS\t\t\t\t(0x0014)\n#define\tME_ME2ARC_INT\t\t\t\t(0x0018)\n#define\tME_ARC2ME_STAT\t\t\t\t(0x001C)\n#define\tME_ARC2ME_MASK \t\t\t\t(0x0020)\n#define\tME_DBG_WR_AD\t\t\t\t(0x0024)\n#define ME_DBG_RD_AD\t\t\t\t(0x0028)\n#define\tME_DBG_DATA\t\t\t\t(0x002C)\n#define\tME_DBG_DECODE\t\t\t\t(0x0030)\n#define ME_CONFIG\t\t\t\t(0x0034)\n#define\tME_RST_CTRL\t\t\t\t(0x0038)\n#define\tME_DBG_MASTER\t\t\t\t(0x003C)\n#define\tME_CLK_CTRL\t\t\t\t(0x0040)\n#define\tME_BIST_CTRL\t\t\t\t(0x0044)\n#define\tME_BIST_STAT\t\t\t\t(0x0048)\n#define ME_XDATA_BASE_SH\t\t\t(0x004c)\n#define ME_XDATA_BASE\t\t\t\t(0x0050)\n#define ME_XMEM_BAR_BASE\t\t\t(0x0054)\n#define ME_XMEM_BAR0\t\t\t\t(0x0054)\n#define ME_XMEM_BAR1\t\t\t\t(0x0058)\n#define ME_XMEM_BAR2\t\t\t\t(0x005C)\n#define ME_XMEM_BAR3\t\t\t\t(0x0060)\n#define ME_XMEM_BAR4\t\t\t\t(0x0064)\n#define ME_XMEM_BAR5\t\t\t\t(0x0068)\n#define ME_XMEM_BAR6\t\t\t\t(0x006C)\n#define ME_XMEM_BAR7\t\t\t\t(0x0070)\n#define ME_XMEM_BAR8\t\t\t\t(0x0074)\n#define ME_XMEM_BAR9\t\t\t\t(0x0078)\n#define ME_XMEM_BAR10\t\t\t\t(0x007C)\n#define ME_XMEM_BAR11\t\t\t\t(0x0080)\n#define ME_XMEM_BAR12\t\t\t\t(0x0084)\n#define ME_XMEM_BAR13\t\t\t\t(0x0088)\n#define ME_XMEM_BAR14\t\t\t\t(0x008C)\n#define ME_XMEM_BAR15\t\t\t\t(0x0090)\n#define ME_XMEM_BAR16\t\t\t\t(0x0094)\n\n#define WHILE_DELAY \t\t20000\n/*\n**\tDefine where in ME Processor's memory map the Stratify chip lives\n*/\n\n#define MAXSWAPSIZE      \t(8 * 1024)\t//8k *(32bits)\n\n//      Mailboxes\n#define MSG_LENGTH\t\t16\t// x16 bits\n#define YES_REPLY      \t \t1\n#define NO_REPLY         \t0\n\n#define CMV_TIMEOUT\t\t1000\t//jiffies\n\n//  Block size per BAR\n#define SDRAM_SEGMENT_SIZE\t(64*1024)\n// Number of Bar registers\n#define MAX_BAR_REGISTERS\t(17)\n\n#define XDATA_REGISTER\t\t(15)\n\n// ARC register addresss\n#define ARC_STATUS\t\t0x0\n#define ARC_LP_START\t\t0x2\n#define ARC_LP_END\t\t0x3\n#define ARC_DEBUG\t\t0x5\n#define ARC_INT_MASK\t\t0x10A\n\n#define IRAM0_BASE \t\t(0x00000)\n#define IRAM1_BASE \t\t(0x04000)\n#if defined(CONFIG_DANUBE)\n#define BRAM_BASE  \t\t(0x0A000)\n#elif defined(CONFIG_AMAZON_SE) || defined(CONFIG_AR9) || defined(CONFIG_VR9)\n#define BRAM_BASE               (0x08000)\n#endif\n#define XRAM_BASE\t\t(0x18000)\n#define YRAM_BASE\t\t(0x1A000)\n#define EXT_MEM_BASE\t\t(0x80000)\n#define ARC_GPIO_CTRL\t\t(0xC030)\n#define ARC_GPIO_DATA\t\t(0xC034)\n\n#define IRAM0_SIZE\t\t(16*1024)\n#define IRAM1_SIZE\t\t(16*1024)\n#define BRAM_SIZE\t\t(12*1024)\n#define XRAM_SIZE\t\t(8*1024)\n#define YRAM_SIZE\t\t(8*1024)\n#define EXT_MEM_SIZE\t\t(1536*1024)\n\n#define ADSL_BASE\t\t(0x20000)\n#define CRI_BASE\t\t(ADSL_BASE + 0x11F00)\n#define CRI_CCR0\t\t(CRI_BASE + 0x00)\n#define CRI_RST\t\t\t(CRI_BASE + 0x04*4)\n#define ADSL_DILV_BASE \t\t(ADSL_BASE+0x20000)\n\n//\n#define IRAM0_ADDR_BIT_MASK\t0xFFF\n#define IRAM1_ADDR_BIT_MASK\t0xFFF\n#define BRAM_ADDR_BIT_MASK\t0xFFF\n#define RX_DILV_ADDR_BIT_MASK\t0x1FFF\n\n/***  Bit definitions ***/\n#define ARC_AUX_HALT\t\t(1 << 25)\n#define ARC_DEBUG_HALT\t\t(1 << 1)\n#define FALSE\t\t\t0\n#define TRUE\t\t\t1\n#define BIT0\t\t\t(1<<0)\n#define BIT1\t\t\t(1<<1)\n#define BIT2\t\t\t(1<<2)\n#define BIT3\t\t\t(1<<3)\n#define BIT4\t\t\t(1<<4)\n#define BIT5\t\t\t(1<<5)\n#define BIT6\t\t\t(1<<6)\n#define BIT7\t\t\t(1<<7)\n#define BIT8\t\t\t(1<<8)\n#define BIT9\t\t\t(1<<9)\n#define BIT10 \t\t\t(1<<10)\n#define BIT11\t\t\t(1<<11)\n#define BIT12\t\t\t(1<<12)\n#define BIT13\t\t\t(1<<13)\n#define BIT14\t\t\t(1<<14)\n#define BIT15\t\t\t(1<<15)\n#define BIT16 \t\t\t(1<<16)\n#define BIT17\t\t\t(1<<17)\n#define BIT18\t\t\t(1<<18)\n#define BIT19\t\t\t(1<<19)\n#define BIT20\t\t\t(1<<20)\n#define BIT21\t\t\t(1<<21)\n#define BIT22\t\t\t(1<<22)\n#define BIT23\t\t\t(1<<23)\n#define BIT24\t\t\t(1<<24)\n#define BIT25\t\t\t(1<<25)\n#define BIT26\t\t\t(1<<26)\n#define BIT27\t\t\t(1<<27)\n#define BIT28\t\t\t(1<<28)\n#define BIT29\t\t\t(1<<29)\n#define BIT30\t\t\t(1<<30)\n#define BIT31\t\t\t(1<<31)\n\n// CRI_CCR0 Register definitions\n#define CLK_2M_MODE_ENABLE\tBIT6\n#define\tACL_CLK_MODE_ENABLE\tBIT4\n#define FDF_CLK_MODE_ENABLE\tBIT2\n#define STM_CLK_MODE_ENABLE\tBIT0\n\n// CRI_RST Register definitions\n#define FDF_SRST\t\tBIT3\n#define MTE_SRST\t\tBIT2\n#define FCI_SRST\t\tBIT1\n#define AAI_SRST\t\tBIT0\n\n//      MEI_TO_ARC_INTERRUPT Register definitions\n#define\tMEI_TO_ARC_INT1\t\tBIT3\n#define\tMEI_TO_ARC_INT0\t\tBIT2\n#define MEI_TO_ARC_CS_DONE\tBIT1\t//need to check\n#define\tMEI_TO_ARC_MSGAV\tBIT0\n\n//      ARC_TO_MEI_INTERRUPT Register definitions\n#define\tARC_TO_MEI_INT1\t\tBIT8\n#define\tARC_TO_MEI_INT0\t\tBIT7\n#define\tARC_TO_MEI_CS_REQ\tBIT6\n#define\tARC_TO_MEI_DBG_DONE\tBIT5\n#define\tARC_TO_MEI_MSGACK\tBIT4\n#define\tARC_TO_MEI_NO_ACCESS\tBIT3\n#define\tARC_TO_MEI_CHECK_AAITX\tBIT2\n#define\tARC_TO_MEI_CHECK_AAIRX\tBIT1\n#define\tARC_TO_MEI_MSGAV\tBIT0\n\n//      ARC_TO_MEI_INTERRUPT_MASK Register definitions\n#define\tGP_INT1_EN\t\tBIT8\n#define\tGP_INT0_EN\t\tBIT7\n#define\tCS_REQ_EN\t\tBIT6\n#define\tDBG_DONE_EN\t\tBIT5\n#define\tMSGACK_EN\t\tBIT4\n#define\tNO_ACC_EN\t\tBIT3\n#define\tAAITX_EN\t\tBIT2\n#define\tAAIRX_EN\t\tBIT1\n#define\tMSGAV_EN\t\tBIT0\n\n#define\tMEI_SOFT_RESET\t\tBIT0\n\n#define\tHOST_MSTR\t\tBIT0\n\n#define JTAG_MASTER_MODE\t0x0\n#define MEI_MASTER_MODE\t\tHOST_MSTR\n\n//      MEI_DEBUG_DECODE Register definitions\n#define MEI_DEBUG_DEC_MASK\t(0x3)\n#define MEI_DEBUG_DEC_AUX_MASK\t(0x0)\n#define ME_DBG_DECODE_DMP1_MASK\t(0x1)\n#define MEI_DEBUG_DEC_DMP2_MASK\t(0x2)\n#define MEI_DEBUG_DEC_CORE_MASK\t(0x3)\n\n#define AUX_STATUS\t\t(0x0)\n#define AUX_ARC_GPIO_CTRL\t(0x10C)\n#define AUX_ARC_GPIO_DATA\t(0x10D)\n//      ARC_TO_MEI_MAILBOX[11] is a special location used to indicate\n//      page swap requests.\n#if defined(CONFIG_DANUBE)\n#define OMBOX_BASE      \t0xDF80\n#define\tARC_TO_MEI_MAILBOX\t0xDFA0\n#define IMBOX_BASE      \t0xDFC0\n#define MEI_TO_ARC_MAILBOX\t0xDFD0\n#elif defined(CONFIG_AMAZON_SE) || defined(CONFIG_AR9) || defined(CONFIG_VR9)\n#define OMBOX_BASE              0xAF80\n#define ARC_TO_MEI_MAILBOX      0xAFA0\n#define IMBOX_BASE              0xAFC0\n#define MEI_TO_ARC_MAILBOX      0xAFD0\n#endif\n\n#define MEI_TO_ARC_MAILBOXR\t(MEI_TO_ARC_MAILBOX + 0x2C)\n#define ARC_MEI_MAILBOXR\t(ARC_TO_MEI_MAILBOX + 0x2C)\n#define OMBOX1  \t\t(OMBOX_BASE+0x4)\n\n// Codeswap request messages are indicated by setting BIT31\n#define OMB_CODESWAP_MESSAGE_MSG_TYPE_MASK\t(0x80000000)\n\n// Clear Eoc messages received are indicated by setting BIT17\n#define OMB_CLEAREOC_INTERRUPT_CODE\t\t(0x00020000)\n#define OMB_REBOOT_INTERRUPT_CODE               (1 << 18)\n\n/*\n**\tSwap page header\n*/\n//      Page must be loaded at boot time if size field has BIT31 set\n#define BOOT_FLAG\t\t(BIT31)\n#define BOOT_FLAG_MASK\t\t~BOOT_FLAG\n\n#define FREE_RELOAD\t\t1\n#define FREE_SHOWTIME\t\t2\n#define FREE_ALL\t\t3\n\n// marcos\n#define\tIFX_MEI_WRITE_REGISTER_L(data,addr)\t*((volatile u32*)(addr)) = (u32)(data)\n#define IFX_MEI_READ_REGISTER_L(addr) \t(*((volatile u32*)(addr)))\n#define SET_BIT(reg, mask)\t\t\treg |= (mask)\n#define CLEAR_BIT(reg, mask)\t\t\treg &= (~mask)\n#define CLEAR_BITS(reg, mask)\t\t\tCLEAR_BIT(reg, mask)\n//#define SET_BITS(reg, mask)\t\t\tSET_BIT(reg, mask)\n#define SET_BITFIELD(reg, mask, off, val)\t{reg &= (~mask); reg |= (val << off);}\n\n#define ALIGN_SIZE\t\t\t\t( 1L<<10 )\t//1K size align\n#define MEM_ALIGN(addr)\t\t\t\t(((addr) + ALIGN_SIZE - 1) & ~ (ALIGN_SIZE -1) )\n\n// swap marco\n#define MEI_HALF_WORD_SWAP(data)\t\t{data = ((data & 0xffff)<<16) + ((data & 0xffff0000)>>16);}\n#define MEI_BYTE_SWAP(data)\t\t\t{data = ((data & 0xff)<<24) + ((data & 0xff00)<<8)+ ((data & 0xff0000)>>8)+ ((data & 0xff000000)>>24);}\n\n\n#ifdef CONFIG_PROC_FS\ntypedef struct reg_entry\n{\n   int *flag;\n   char name[30];               /* big enough to hold names */\n   char description[100];       /* big enough to hold description */\n   unsigned short low_ino;\n} reg_entry_t;\n#endif\n//      Swap page header describes size in 32-bit words, load location, and image offset\n//      for program and/or data segments\ntypedef struct _arc_swp_page_hdr {\n\tu32 p_offset;\t\t//Offset bytes of progseg from beginning of image\n\tu32 p_dest;\t\t//Destination addr of progseg on processor\n\tu32 p_size;\t\t//Size in 32-bitwords of program segment\n\tu32 d_offset;\t\t//Offset bytes of dataseg from beginning of image\n\tu32 d_dest;\t\t//Destination addr of dataseg on processor\n\tu32 d_size;\t\t//Size in 32-bitwords of data segment\n} ARC_SWP_PAGE_HDR;\n\n/*\n**\tSwap image header\n*/\n#define GET_PROG\t0\t//      Flag used for program mem segment\n#define GET_DATA\t1\t//      Flag used for data mem segment\n\n//      Image header contains size of image, checksum for image, and count of\n//      page headers. Following that are 'count' page headers followed by\n//      the code and/or data segments to be loaded\ntypedef struct _arc_img_hdr {\n\tu32 size;\t\t//      Size of binary image in bytes\n\tu32 checksum;\t\t//      Checksum for image\n\tu32 count;\t\t//      Count of swp pages in image\n\tARC_SWP_PAGE_HDR page[1];\t//      Should be \"count\" pages - '1' to make compiler happy\n} ARC_IMG_HDR;\n\ntypedef struct smmu_mem_info {\n\tint type;\n\tint boot;\n\tunsigned long nCopy;\n\tunsigned long size;\n\tunsigned char *address;\n\tunsigned char *org_address;\n} smmu_mem_info_t;\n\n#ifdef __KERNEL__\ntypedef struct ifx_mei_device_private {\n\tint modem_ready;\n\tint arcmsgav;\n\tint cmv_reply;\n\tint cmv_waiting;\n\t// Mei to ARC CMV count, reply count, ARC Indicator count\n\tint modem_ready_cnt;\n\tint cmv_count;\n\tint reply_count;\n\tunsigned long image_size;\n\tint nBar;\n\tu16 Recent_indicator[MSG_LENGTH];\n\n\tu16 CMV_RxMsg[MSG_LENGTH] __attribute__ ((aligned (4)));\n\n\tsmmu_mem_info_t adsl_mem_info[MAX_BAR_REGISTERS];\n\tARC_IMG_HDR *img_hdr;\n\t//  to wait for arc cmv reply, sleep on wait_queue_arcmsgav;\n\twait_queue_head_t wait_queue_arcmsgav;\n\twait_queue_head_t wait_queue_modemready;\n\tstruct semaphore mei_cmv_sema;\n} ifx_mei_device_private_t;\n#endif\ntypedef struct winhost_message {\n\tunion {\n\t\tu16 RxMessage[MSG_LENGTH] __attribute__ ((aligned (4)));\n\t\tu16 TxMessage[MSG_LENGTH] __attribute__ ((aligned (4)));\n\t} msg;\n} DSL_DEV_WinHost_Message_t;\n/********************************************************************************************************\n * DSL CPE API Driver Stack Interface Definitions\n * *****************************************************************************************************/\n/** IOCTL codes for bsp driver */\n#define DSL_IOC_MEI_BSP_MAGIC\t\t's'\n\n#define DSL_FIO_BSP_DSL_START\t\t_IO  (DSL_IOC_MEI_BSP_MAGIC, 0)\n#define DSL_FIO_BSP_RUN\t\t\t_IO  (DSL_IOC_MEI_BSP_MAGIC, 1)\n#define DSL_FIO_BSP_FREE_RESOURCE\t_IO  (DSL_IOC_MEI_BSP_MAGIC, 2)\n#define DSL_FIO_BSP_RESET\t\t_IO  (DSL_IOC_MEI_BSP_MAGIC, 3)\n#define DSL_FIO_BSP_REBOOT\t\t_IO  (DSL_IOC_MEI_BSP_MAGIC, 4)\n#define DSL_FIO_BSP_HALT\t\t_IO  (DSL_IOC_MEI_BSP_MAGIC, 5)\n#define DSL_FIO_BSP_BOOTDOWNLOAD\t_IO  (DSL_IOC_MEI_BSP_MAGIC, 6)\n#define DSL_FIO_BSP_JTAG_ENABLE\t\t_IO  (DSL_IOC_MEI_BSP_MAGIC, 7)\n#define DSL_FIO_FREE_RESOURCE\t\t_IO  (DSL_IOC_MEI_BSP_MAGIC, 8)\n#define DSL_FIO_ARC_MUX_TEST\t\t_IO  (DSL_IOC_MEI_BSP_MAGIC, 9)\n#define DSL_FIO_BSP_REMOTE\t\t_IOW (DSL_IOC_MEI_BSP_MAGIC, 10, u32)\n#define DSL_FIO_BSP_GET_BASE_ADDRESS\t_IOR (DSL_IOC_MEI_BSP_MAGIC, 11, u32)\n#define DSL_FIO_BSP_IS_MODEM_READY\t_IOR (DSL_IOC_MEI_BSP_MAGIC, 12, u32)\n#define DSL_FIO_BSP_GET_VERSION\t\t_IOR (DSL_IOC_MEI_BSP_MAGIC, 13, DSL_DEV_Version_t)\n#define DSL_FIO_BSP_CMV_WINHOST\t\t_IOWR(DSL_IOC_MEI_BSP_MAGIC, 14, DSL_DEV_WinHost_Message_t)\n#define DSL_FIO_BSP_CMV_READ\t\t_IOWR(DSL_IOC_MEI_BSP_MAGIC, 15, DSL_DEV_MeiReg_t)\n#define DSL_FIO_BSP_CMV_WRITE\t\t_IOW (DSL_IOC_MEI_BSP_MAGIC, 16, DSL_DEV_MeiReg_t)\n#define DSL_FIO_BSP_DEBUG_READ\t\t_IOWR(DSL_IOC_MEI_BSP_MAGIC, 17, DSL_DEV_MeiDebug_t)\n#define DSL_FIO_BSP_DEBUG_WRITE\t\t_IOWR(DSL_IOC_MEI_BSP_MAGIC, 18, DSL_DEV_MeiDebug_t)\n#define DSL_FIO_BSP_GET_CHIP_INFO\t_IOR (DSL_IOC_MEI_BSP_MAGIC, 19, DSL_DEV_HwVersion_t)\n\n#define DSL_DEV_MEIDEBUG_BUFFER_SIZES\t512\n\ntypedef struct DSL_DEV_MeiDebug\n{\n\tDSL_uint32_t iAddress;\n\tDSL_uint32_t iCount;\n\tDSL_uint32_t buffer[DSL_DEV_MEIDEBUG_BUFFER_SIZES];\n} DSL_DEV_MeiDebug_t;\t\t\t/* meidebug */\n\n/**\n *    Structure is used for debug access only.\n *       Refer to configure option INCLUDE_ADSL_WINHOST_DEBUG */\ntypedef struct struct_meireg\n{\n\t/*\n\t*       Specifies that address for debug access */\n\tunsigned long iAddress;\n\t/*\n\t*       Specifies the pointer to the data that has to be written or returns a\n\t*             pointer to the data that has been read out*/\n\tunsigned long iData;\n} DSL_DEV_MeiReg_t;\t\t\t\t\t/* meireg */\n\ntypedef struct DSL_DEV_Device\n{\n\tDSL_int_t nInUse;                /* modem state, update by bsp driver, */\n\tDSL_void_t *pPriv;\n\tDSL_uint32_t base_address;       /* mei base address */\n\tDSL_int_t nIrq[2];                  /* irq number */\n#define IFX_DFEIR\t\t0\n#define IFX_DYING_GASP\t1\n\tDSL_DEV_MeiDebug_t lop_debugwr;  /* dying gasp */\n\tstruct module *owner;\n} DSL_DEV_Device_t;\t\t\t/* ifx_adsl_device_t */\n\n#define DSL_DEV_PRIVATE(dev)  ((ifx_mei_device_private_t*)(dev->pPriv))\n\ntypedef struct DSL_DEV_Version\t\t/* ifx_adsl_bsp_version */\n{\n\tunsigned long major;\n\tunsigned long minor;\n\tunsigned long revision;\n} DSL_DEV_Version_t;\t\t\t/* ifx_adsl_bsp_version_t */\n\ntypedef struct DSL_DEV_ChipInfo\n{\n\tunsigned long major;\n\tunsigned long minor;\n} DSL_DEV_HwVersion_t;\n\ntypedef struct\n{\n\tDSL_uint8_t dummy;\n} DSL_DEV_DeviceConfig_t;\n\n/** error code definitions */\ntypedef enum DSL_DEV_MeiError\n{\n\tDSL_DEV_MEI_ERR_SUCCESS = 0,\n\tDSL_DEV_MEI_ERR_FAILURE = -1,\n\tDSL_DEV_MEI_ERR_MAILBOX_FULL = -2,\n\tDSL_DEV_MEI_ERR_MAILBOX_EMPTY = -3,\n\tDSL_DEV_MEI_ERR_MAILBOX_TIMEOUT = -4\n} DSL_DEV_MeiError_t;\t\t\t/* MEI_ERROR */\n\ntypedef enum {\n\tDSL_BSP_MEMORY_READ=0,\n\tDSL_BSP_MEMORY_WRITE,\n} DSL_BSP_MemoryAccessType_t;\t\t/* ifx_adsl_memory_access_type_t */\n\ntypedef enum\n{\n\tDSL_LED_LINK_ID=0,\n\tDSL_LED_DATA_ID\n} DSL_DEV_LedId_t;\t\t\t/* ifx_adsl_led_id_t */\n\ntypedef enum\n{\n\tDSL_LED_LINK_TYPE=0,\n\tDSL_LED_DATA_TYPE\n} DSL_DEV_LedType_t;\t\t\t/* ifx_adsl_led_type_t */\n\ntypedef enum\n{\n\tDSL_LED_HD_CPU=0,\n\tDSL_LED_HD_FW\n} DSL_DEV_LedHandler_t;\t\t\t/* ifx_adsl_led_handler_t */\n\ntypedef enum {\n\tDSL_LED_ON=0,\n\tDSL_LED_OFF,\n\tDSL_LED_FLASH,\n} DSL_DEV_LedMode_t;\t\t\t/* ifx_adsl_led_mode_t */\n\ntypedef enum {\n\tDSL_CPU_HALT=0,\n\tDSL_CPU_RUN,\n\tDSL_CPU_RESET,\n} DSL_DEV_CpuMode_t;\t\t\t/* ifx_adsl_cpu_mode_t */\n\n#if 0\ntypedef enum {\n\tDSL_BSP_EVENT_DYING_GASP = 0,\n\tDSL_BSP_EVENT_CEOC_IRQ,\n} DSL_BSP_Event_id_t;\t\t\t/* ifx_adsl_event_id_t */\n\ntypedef union DSL_BSP_CB_Param\n{\n\tDSL_uint32_t nIrqMessage;\n} DSL_BSP_CB_Param_t;\t\t\t/* ifx_adsl_cbparam_t */\n\ntypedef struct DSL_BSP_CB_Event\n{\n\tDSL_BSP_Event_id_t nID;\n\tDSL_DEV_Device_t *pDev;\n\tDSL_BSP_CB_Param_t *pParam;\n} DSL_BSP_CB_Event_t;\t\t\t/* ifx_adsl_cb_event_t */\n#endif\n\n/* external functions (from the BSP Driver) */\nextern DSL_DEV_Device_t* DSL_BSP_DriverHandleGet(int, int);\nextern DSL_int_t DSL_BSP_DriverHandleDelete(DSL_DEV_Device_t *);\nextern DSL_DEV_MeiError_t DSL_BSP_FWDownload(DSL_DEV_Device_t *, const DSL_char_t *, DSL_uint32_t, DSL_int32_t *, DSL_int32_t *);\nextern int DSL_BSP_KernelIoctls(DSL_DEV_Device_t *, unsigned int, unsigned long);\nextern DSL_DEV_MeiError_t DSL_BSP_SendCMV(DSL_DEV_Device_t *, DSL_uint16_t *, DSL_int_t, DSL_uint16_t *);\nextern DSL_DEV_MeiError_t DSL_BSP_AdslLedInit(DSL_DEV_Device_t *, DSL_DEV_LedId_t, DSL_DEV_LedType_t, DSL_DEV_LedHandler_t);\nextern DSL_DEV_MeiError_t DSL_BSP_Showtime(DSL_DEV_Device_t *, DSL_uint32_t, DSL_uint32_t);\nextern int DSL_BSP_ATMLedCBRegister( int (*ifx_adsl_ledcallback)(void));\nextern DSL_DEV_MeiError_t DSL_BSP_MemoryDebugAccess(DSL_DEV_Device_t *, DSL_BSP_MemoryAccessType_t, DSL_uint32_t, DSL_uint32_t *, DSL_uint32_t);\nextern volatile DSL_DEV_Device_t *adsl_dev;\n\n/**\n *    Dummy structure by now to show mechanism of extended data that will be\n *       provided within event callback itself.\n *       */\ntypedef struct\n{\n\t/**\n\t*    Dummy value */\n\tDSL_uint32_t nDummy1;\n} DSL_BSP_CB_Event1DataDummy_t;\n\n/**\n *    Dummy structure by now to show mechanism of extended data that will be\n *       provided within event callback itself.\n *       */\ntypedef struct\n{\n\t/**\n\t*    Dummy value */\n\tDSL_uint32_t nDummy2;\n} DSL_BSP_CB_Event2DataDummy_t;\n\n/**\n *    encapsulate all data structures that are necessary for status event\n *       callbacks.\n *       */\ntypedef union\n{\n\tDSL_BSP_CB_Event1DataDummy_t dataEvent1;\n\tDSL_BSP_CB_Event2DataDummy_t dataEvent2;\n} DSL_BSP_CB_DATA_Union_t;\n\n\ntypedef enum\n{\n\t/**\n\t *    Informs the upper layer driver (DSL CPE API) about a reboot request from the\n\t *       firmware.\n\t *          \\note This event does NOT include any additional data.\n\t *                   More detailed information upon reboot reason has to be requested from\n\t *                            upper layer software via CMV (INFO 109) if necessary. */\n\tDSL_BSP_CB_FIRST = 0,\n        DSL_BSP_CB_DYING_GASP,\n\tDSL_BSP_CB_CEOC_IRQ,\n\tDSL_BSP_CB_FIRMWARE_REBOOT,\n\t/**\n\t *    Delimiter only */\n\tDSL_BSP_CB_LAST\n} DSL_BSP_CB_Type_t;\n\n/**\n *    Specifies the common event type that has to be used for registering and\n *       signalling of interrupts/autonomous status events from MEI BSP Driver.\n *\n *    \\param pDev\n *    Context pointer from MEI BSP Driver.\n *\n *    \\param IFX_ADSL_BSP_CallbackType_t\n *    Specifies the event callback type (reason of callback). Regrading to the\n *    setting of this value the data which is included in the following union\n *    might have different meanings.\n *    Please refer to the description of the union to get information about the\n *    meaning of the included data.\n *\n *    \\param pData\n *    Data according to \\ref DSL_BSP_CB_DATA_Union_t.\n *    If this pointer is NULL there is no additional data available.\n *\n *    \\return depending on event\n */\ntypedef int (*DSL_BSP_EventCallback_t)\n(\n\tDSL_DEV_Device_t *pDev,\n\tDSL_BSP_CB_Type_t nCallbackType,\n\tDSL_BSP_CB_DATA_Union_t *pData\n);\n\ntypedef struct {\n        DSL_BSP_EventCallback_t function;\n        DSL_BSP_CB_Type_t       event;\n        DSL_BSP_CB_DATA_Union_t *pData;\n} DSL_BSP_EventCallBack_t;\n\nextern int DSL_BSP_EventCBRegister(DSL_BSP_EventCallBack_t *);\nextern int DSL_BSP_EventCBUnregister(DSL_BSP_EventCallBack_t *);\n\n/** Modem states */\n#define DSL_DEV_STAT_InitState              0x0000\n#define DSL_DEV_STAT_ReadyState             0x0001\n#define DSL_DEV_STAT_FailState              0x0002\n#define DSL_DEV_STAT_IdleState              0x0003\n#define DSL_DEV_STAT_QuietState             0x0004\n#define DSL_DEV_STAT_GhsState               0x0005\n#define DSL_DEV_STAT_FullInitState          0x0006\n#define DSL_DEV_STAT_ShowTimeState          0x0007\n#define DSL_DEV_STAT_FastRetrainState       0x0008\n#define DSL_DEV_STAT_LoopDiagMode           0x0009\n#define DSL_DEV_STAT_ShortInit              0x000A     /* Bis short initialization */\n\n#define DSL_DEV_STAT_CODESWAP_COMPLETE\t    0x0002\n\n#endif //IFXMIPS_MEI_H\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-atm/Makefile",
    "content": "# Copyright (C) 2012 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n\ninclude $(TOPDIR)/rules.mk\ninclude $(INCLUDE_DIR)/kernel.mk\n\nPKG_NAME:=ltq-atm\nPKG_RELEASE:=3\n\nPKG_MAINTAINER:=John Crispin <john@phrozen.org>\nPKG_LICENSE:=GPL-2.0+\n\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine KernelPackage/ltq-atm-template\n  SECTION:=sys\n  CATEGORY:=Kernel modules\n  SUBMENU:=Network Devices\n  TITLE:=atm driver for $(1)\n  URL:=http://www.lantiq.com/\n  VARIANT:=$(1)\n  DEPENDS:=@$(2) +kmod-atm +br2684ctl\nifeq ($(1),vr9)\n  DEPENDS+= +PACKAGE_kmod-ltq-atm-$(1):kmod-ltq-vdsl-vr9-mei\nelse\n  DEPENDS+= +PACKAGE_kmod-ltq-atm-$(1):kmod-ltq-adsl-$(1)-mei\nendif\n  FILES:=$(PKG_BUILD_DIR)/ltq_atm_$(1).ko\nendef\n\nKernelPackage/ltq-atm-danube=$(call KernelPackage/ltq-atm-template,danube,(TARGET_lantiq_xway||TARGET_lantiq_xway_legacy))\nKernelPackage/ltq-atm-ar9=$(call KernelPackage/ltq-atm-template,ar9,TARGET_lantiq_xway)\nKernelPackage/ltq-atm-ase=$(call KernelPackage/ltq-atm-template,ase,TARGET_lantiq_ase)\nKernelPackage/ltq-atm-vr9=$(call KernelPackage/ltq-atm-template,vr9,TARGET_lantiq_xrx200)\n\ndefine Build/Configure\nendef\n\ndefine Build/Compile\n\tcd $(LINUX_DIR); \\\n\t\tARCH=mips CROSS_COMPILE=\"$(KERNEL_CROSS)\" \\\n\t\t$(MAKE) $(KERNEL_MAKE_FLAGS) BUILD_VARIANT=$(BUILD_VARIANT) M=$(PKG_BUILD_DIR) V=1 modules\nendef\n\n$(eval $(call KernelPackage,ltq-atm-danube))\n$(eval $(call KernelPackage,ltq-atm-ase))\n$(eval $(call KernelPackage,ltq-atm-ar9))\n$(eval $(call KernelPackage,ltq-atm-vr9))\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-atm/src/Makefile",
    "content": "ifeq ($(BUILD_VARIANT),danube)\n  CFLAGS_MODULE = -DCONFIG_DANUBE\n  obj-m = ltq_atm_danube.o\n  ltq_atm_danube-objs = ltq_atm.o ifxmips_atm_danube.o\nendif\n\nifeq ($(BUILD_VARIANT),ase)\n  CFLAGS_MODULE = -DCONFIG_AMAZON_SE\n  obj-m = ltq_atm_ase.o\n  ltq_atm_ase-objs = ltq_atm.o ifxmips_atm_amazon_se.o\nendif\n\nifeq ($(BUILD_VARIANT),ar9)\n  CFLAGS_MODULE = -DCONFIG_AR9\n  obj-m = ltq_atm_ar9.o\n  ltq_atm_ar9-objs = ltq_atm.o ifxmips_atm_ar9.o\nendif\n\nifeq ($(BUILD_VARIANT),vr9)\n  CFLAGS_MODULE = -DCONFIG_VR9\n  obj-m = ltq_atm_vr9.o\n  ltq_atm_vr9-objs = ltq_atm.o ifxmips_atm_vr9.o\nendif\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-atm/src/ifxmips_atm_amazon_se.c",
    "content": "/******************************************************************************\n**\n** FILE NAME    : ifxmips_atm_amazon_se.c\n** PROJECT      : UEIP\n** MODULES      : ATM\n**\n** DATE         : 7 Jul 2009\n** AUTHOR       : Xu Liang\n** DESCRIPTION  : ATM driver common source file (core functions)\n** COPYRIGHT    :       Copyright (c) 2006\n**                      Infineon Technologies AG\n**                      Am Campeon 1-12, 85579 Neubiberg, Germany\n**\n**    This program is free software; you can redistribute it and/or modify\n**    it under the terms of the GNU General Public License as published by\n**    the Free Software Foundation; either version 2 of the License, or\n**    (at your option) any later version.\n**\n** HISTORY\n** $Date        $Author         $Comment\n** 07 JUL 2009  Xu Liang        Init Version\n*******************************************************************************/\n\n\n\n/*\n * ####################################\n *              Head File\n * ####################################\n */\n\n/*\n *  Common Head File\n */\n#include <linux/kernel.h>\n#include <linux/module.h>\n#include <linux/version.h>\n#include <linux/types.h>\n#include <linux/errno.h>\n#include <linux/proc_fs.h>\n#include <linux/init.h>\n#include <linux/ioctl.h>\n#include <linux/platform_device.h>\n#include <asm/delay.h>\n\n/*\n *  Chip Specific Head File\n */\n#include \"ifxmips_atm_core.h\"\n#include \"ifxmips_atm_fw_amazon_se.h\"\n\n#include <lantiq_soc.h>\n\n\n/*\n * ####################################\n *              Definition\n * ####################################\n */\n\n/*\n *  EMA Settings\n */\n#define EMA_CMD_BUF_LEN      0x0040\n#define EMA_CMD_BASE_ADDR    (0x00001580 << 2)\n#define EMA_DATA_BUF_LEN     0x0100\n#define EMA_DATA_BASE_ADDR   (0x00000B00 << 2)\n#define EMA_WRITE_BURST      0x2\n#define EMA_READ_BURST       0x2\n\n\n\n/*\n * ####################################\n *             Declaration\n * ####################################\n */\n\n/*\n *  Hardware Init/Uninit Functions\n */\nstatic inline void init_pmu(void);\nstatic inline void uninit_pmu(void);\nstatic inline void reset_ppe(struct platform_device *pdev);\nstatic inline void init_ema(void);\nstatic inline void init_mailbox(void);\nstatic inline void init_atm_tc(void);\nstatic inline void clear_share_buffer(void);\n\n\n\n/*\n * ####################################\n *            Local Variable\n * ####################################\n */\n\n\n\n/*\n * ####################################\n *            Local Function\n * ####################################\n */\n#define IFX_PMU_MODULE_PPE_SLL01  BIT(19)\n#define IFX_PMU_MODULE_PPE_TC     BIT(21)\n#define IFX_PMU_MODULE_PPE_EMA    BIT(22)\n#define IFX_PMU_MODULE_PPE_QSB    BIT(18)\n#define IFX_PMU_MODULE_TPE       BIT(13)\n#define IFX_PMU_MODULE_DSL_DFE    BIT(9)\n\nstatic inline void init_pmu(void)\n{\n    //*(unsigned long *)0xBF10201C &= ~((1 << 15) | (1 << 13) | (1 << 9));\n    //PPE_TOP_PMU_SETUP(IFX_PMU_ENABLE);\n/*    PPE_SLL01_PMU_SETUP(IFX_PMU_ENABLE);\n    PPE_TC_PMU_SETUP(IFX_PMU_ENABLE);\n    PPE_EMA_PMU_SETUP(IFX_PMU_ENABLE);\n    //PPE_QSB_PMU_SETUP(IFX_PMU_ENABLE);\n    PPE_TPE_PMU_SETUP(IFX_PMU_ENABLE);\n    DSL_DFE_PMU_SETUP(IFX_PMU_ENABLE);*/\n\tltq_pmu_enable(IFX_PMU_MODULE_PPE_SLL01 |\n\t\tIFX_PMU_MODULE_PPE_TC |\n\t\tIFX_PMU_MODULE_PPE_EMA |\n\t\tIFX_PMU_MODULE_TPE |\n\t\tIFX_PMU_MODULE_DSL_DFE);\n}\n\nstatic inline void uninit_pmu(void)\n{\n    /*PPE_SLL01_PMU_SETUP(IFX_PMU_DISABLE);\n    PPE_TC_PMU_SETUP(IFX_PMU_DISABLE);\n    PPE_EMA_PMU_SETUP(IFX_PMU_DISABLE);\n    //PPE_QSB_PMU_SETUP(IFX_PMU_DISABLE);\n    PPE_TPE_PMU_SETUP(IFX_PMU_DISABLE);\n    DSL_DFE_PMU_SETUP(IFX_PMU_DISABLE);\n    //PPE_TOP_PMU_SETUP(IFX_PMU_DISABLE);*/\n}\n\nstatic inline void reset_ppe(struct platform_device *pdev)\n{\n#if 0 //MODULE\n    unsigned int etop_cfg;\n    unsigned int etop_mdio_cfg;\n    unsigned int etop_ig_plen_ctrl;\n    unsigned int enet_mac_cfg;\n\n    etop_cfg            = *IFX_PP32_ETOP_CFG;\n    etop_mdio_cfg       = *IFX_PP32_ETOP_MDIO_CFG;\n    etop_ig_plen_ctrl   = *IFX_PP32_ETOP_IG_PLEN_CTRL;\n    enet_mac_cfg        = *IFX_PP32_ENET_MAC_CFG;\n\n    *IFX_PP32_ETOP_CFG  = (*IFX_PP32_ETOP_CFG & ~0x03C0) | 0x0001;\n\n    //  reset PPE\n    ifx_rcu_rst(IFX_RCU_DOMAIN_PPE, IFX_RCU_MODULE_ATM);\n\n    *IFX_PP32_ETOP_MDIO_CFG     = etop_mdio_cfg;\n    *IFX_PP32_ETOP_IG_PLEN_CTRL = etop_ig_plen_ctrl;\n    *IFX_PP32_ENET_MAC_CFG      = enet_mac_cfg;\n    *IFX_PP32_ETOP_CFG          = etop_cfg;\n#endif\n}\n\nstatic inline void init_ema(void)\n{\n    IFX_REG_W32((EMA_CMD_BUF_LEN << 16) | (EMA_CMD_BASE_ADDR >> 2), EMA_CMDCFG);\n    IFX_REG_W32((EMA_DATA_BUF_LEN << 16) | (EMA_DATA_BASE_ADDR >> 2), EMA_DATACFG);\n    IFX_REG_W32(0x000000FF, EMA_IER);\n    IFX_REG_W32(EMA_READ_BURST | (EMA_WRITE_BURST << 2), EMA_CFG);\n}\n\nstatic inline void init_mailbox(void)\n{\n    IFX_REG_W32(0xFFFFFFFF, MBOX_IGU1_ISRC);\n    IFX_REG_W32(0x00000000, MBOX_IGU1_IER);\n    IFX_REG_W32(0xFFFFFFFF, MBOX_IGU3_ISRC);\n    IFX_REG_W32(0x00000000, MBOX_IGU3_IER);\n}\n\nstatic inline void init_atm_tc(void)\n{\n    IFX_REG_W32(0x0000,     DREG_AT_CTRL);\n    IFX_REG_W32(0x0000,     DREG_AR_CTRL);\n    IFX_REG_W32(0x0,        DREG_AT_IDLE0);\n    IFX_REG_W32(0x0,        DREG_AT_IDLE1);\n    IFX_REG_W32(0x0,        DREG_AR_IDLE0);\n    IFX_REG_W32(0x0,        DREG_AR_IDLE1);\n    IFX_REG_W32(0x40,       RFBI_CFG);\n    IFX_REG_W32(0x0700,     SFSM_DBA0);\n    IFX_REG_W32(0x0818,     SFSM_DBA1);\n    IFX_REG_W32(0x0930,     SFSM_CBA0);\n    IFX_REG_W32(0x0944,     SFSM_CBA1);\n    IFX_REG_W32(0x14014,    SFSM_CFG0);\n    IFX_REG_W32(0x14014,    SFSM_CFG1);\n    IFX_REG_W32(0x0958,     FFSM_DBA0);\n    IFX_REG_W32(0x09AC,     FFSM_DBA1);\n    IFX_REG_W32(0x10006,    FFSM_CFG0);\n    IFX_REG_W32(0x10006,    FFSM_CFG1);\n    IFX_REG_W32(0x00000001, FFSM_IDLE_HEAD_BC0);\n    IFX_REG_W32(0x00000001, FFSM_IDLE_HEAD_BC1);\n}\n\nstatic inline void clear_share_buffer(void)\n{\n    volatile u32 *p = SB_RAM0_ADDR(0);\n    unsigned int i;\n\n    for ( i = 0; i < SB_RAM0_DWLEN + SB_RAM1_DWLEN; i++ )\n        IFX_REG_W32(0, p++);\n}\n\n/*\n *  Description:\n *    Download PPE firmware binary code.\n *  Input:\n *    src       --- u32 *, binary code buffer\n *    dword_len --- unsigned int, binary code length in DWORD (32-bit)\n *  Output:\n *    int       --- 0:    Success\n *                  else:           Error Code\n */\nstatic inline int pp32_download_code(u32 *code_src, unsigned int code_dword_len, u32 *data_src, unsigned int data_dword_len)\n{\n    volatile u32 *dest;\n\n    if ( code_src == 0 || ((unsigned long)code_src & 0x03) != 0\n        || data_src == 0 || ((unsigned long)data_src & 0x03) != 0 )\n        return -1;\n\n    if ( code_dword_len <= CDM_CODE_MEMORYn_DWLEN(0) )\n        IFX_REG_W32(0x00, CDM_CFG);\n    else\n        IFX_REG_W32(0x04, CDM_CFG);\n\n    /*  copy code   */\n    dest = CDM_CODE_MEMORY(0, 0);\n    while ( code_dword_len-- > 0 )\n        IFX_REG_W32(*code_src++, dest++);\n\n    /*  copy data   */\n    dest = CDM_DATA_MEMORY(0, 0);\n    while ( data_dword_len-- > 0 )\n        IFX_REG_W32(*data_src++, dest++);\n\n    return 0;\n}\n\n\n\n/*\n * ####################################\n *           Global Function\n * ####################################\n */\n\nextern void ase_fw_ver(unsigned int *major, unsigned int *minor)\n{\n    ASSERT(major != NULL, \"pointer is NULL\");\n    ASSERT(minor != NULL, \"pointer is NULL\");\n\n    *major = FW_VER_ID->major;\n    *minor = FW_VER_ID->minor;\n}\n\nvoid ase_init(struct platform_device *pdev)\n{\n    init_pmu();\n\n    reset_ppe(pdev);\n\n    init_ema();\n\n    init_mailbox();\n\n    init_atm_tc();\n\n    clear_share_buffer();\n}\n\nvoid ase_shutdown(void)\n{\n    uninit_pmu();\n}\n\n/*\n *  Description:\n *    Initialize and start up PP32.\n *  Input:\n *    none\n *  Output:\n *    int  --- 0: Success\n *             else:        Error Code\n */\nint ase_start(int pp32)\n{\n    int ret;\n\n    /*  download firmware   */\n    ret = pp32_download_code(firmware_binary_code, sizeof(firmware_binary_code) / sizeof(*firmware_binary_code), firmware_binary_data, sizeof(firmware_binary_data) / sizeof(*firmware_binary_data));\n    if ( ret != 0 )\n        return ret;\n\n    /*  run PP32    */\n    IFX_REG_W32(DBG_CTRL_RESTART, PP32_DBG_CTRL);\n\n    /*  idle for a while to let PP32 init itself    */\n    udelay(10);\n\n    return 0;\n}\n\n/*\n *  Description:\n *    Halt PP32.\n *  Input:\n *    none\n *  Output:\n *    none\n */\nvoid ase_stop(int pp32)\n{\n    /*  halt PP32   */\n    IFX_REG_W32(DBG_CTRL_STOP, PP32_DBG_CTRL);\n}\n\nstruct ltq_atm_ops ase_ops = {\n\t.init = ase_init,\n\t.shutdown = ase_shutdown,\n\t.start = ase_start,\n\t.stop = ase_stop,\n\t.fw_ver = ase_fw_ver,\n};\n\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-atm/src/ifxmips_atm_ar9.c",
    "content": "/******************************************************************************\n**\n** FILE NAME    : ifxmips_atm_ar9.c\n** PROJECT      : UEIP\n** MODULES      : ATM\n**\n** DATE         : 7 Jul 2009\n** AUTHOR       : Xu Liang\n** DESCRIPTION  : ATM driver common source file (core functions)\n** COPYRIGHT    :       Copyright (c) 2006\n**                      Infineon Technologies AG\n**                      Am Campeon 1-12, 85579 Neubiberg, Germany\n**\n**    This program is free software; you can redistribute it and/or modify\n**    it under the terms of the GNU General Public License as published by\n**    the Free Software Foundation; either version 2 of the License, or\n**    (at your option) any later version.\n**\n** HISTORY\n** $Date        $Author         $Comment\n** 07 JUL 2009  Xu Liang        Init Version\n*******************************************************************************/\n\n\n\n/*\n * ####################################\n *              Head File\n * ####################################\n */\n\n/*\n *  Common Head File\n */\n#include <linux/kernel.h>\n#include <linux/module.h>\n#include <linux/version.h>\n#include <linux/types.h>\n#include <linux/errno.h>\n#include <linux/proc_fs.h>\n#include <linux/init.h>\n#include <linux/ioctl.h>\n#include <linux/platform_device.h>\n#include <asm/delay.h>\n\n/*\n *  Chip Specific Head File\n */\n#include \"ifxmips_atm_core.h\"\n\n#include \"ifxmips_atm_fw_ar9.h\"\n#include \"ifxmips_atm_fw_regs_ar9.h\"\n\n#include <lantiq_soc.h>\n\n\n\n/*\n * ####################################\n *              Definition\n * ####################################\n */\n\n/*\n *  EMA Settings\n */\n#define EMA_CMD_BUF_LEN      0x0040\n#define EMA_CMD_BASE_ADDR    (0x00003B80 << 2)\n#define EMA_DATA_BUF_LEN     0x0100\n#define EMA_DATA_BASE_ADDR   (0x00003C00 << 2)\n#define EMA_WRITE_BURST      0x2\n#define EMA_READ_BURST       0x2\n\n\n\n/*\n * ####################################\n *             Declaration\n * ####################################\n */\n\n/*\n *  Hardware Init/Uninit Functions\n */\nstatic inline void init_pmu(void);\nstatic inline void uninit_pmu(void);\nstatic inline void reset_ppe(struct platform_device *pdev);\nstatic inline void init_ema(void);\nstatic inline void init_mailbox(void);\nstatic inline void clear_share_buffer(void);\n\n\n\n/*\n * ####################################\n *            Local Variable\n * ####################################\n */\n\n\n\n/*\n * ####################################\n *            Local Function\n * ####################################\n */\n\n#define IFX_PMU_MODULE_PPE_SLL01  BIT(19)\n#define IFX_PMU_MODULE_PPE_TC     BIT(21)\n#define IFX_PMU_MODULE_PPE_EMA    BIT(22)\n#define IFX_PMU_MODULE_PPE_QSB    BIT(18)\n#define IFX_PMU_MODULE_TPE       BIT(13)\n#define IFX_PMU_MODULE_DSL_DFE    BIT(9)\n\nstatic inline void init_pmu(void)\n{\n\tltq_pmu_enable(IFX_PMU_MODULE_PPE_SLL01 |\n\t\tIFX_PMU_MODULE_PPE_TC |\n\t\tIFX_PMU_MODULE_PPE_EMA |\n\t\tIFX_PMU_MODULE_PPE_QSB |\n\t\tIFX_PMU_MODULE_TPE |\n\t\tIFX_PMU_MODULE_DSL_DFE);\n}\n\nstatic inline void uninit_pmu(void)\n{\n}\n\nstatic inline void reset_ppe(struct platform_device *pdev)\n{\n#ifdef MODULE\n    //  reset PPE\n//    ifx_rcu_rst(IFX_RCU_DOMAIN_PPE, IFX_RCU_MODULE_ATM);\n#endif\n}\n\nstatic inline void init_ema(void)\n{\n    IFX_REG_W32((EMA_CMD_BUF_LEN << 16) | (EMA_CMD_BASE_ADDR >> 2), EMA_CMDCFG);\n    IFX_REG_W32((EMA_DATA_BUF_LEN << 16) | (EMA_DATA_BASE_ADDR >> 2), EMA_DATACFG);\n    IFX_REG_W32(0x000000FF, EMA_IER);\n    IFX_REG_W32(EMA_READ_BURST | (EMA_WRITE_BURST << 2), EMA_CFG);\n}\n\nstatic inline void init_mailbox(void)\n{\n    IFX_REG_W32(0xFFFFFFFF, MBOX_IGU1_ISRC);\n    IFX_REG_W32(0x00000000, MBOX_IGU1_IER);\n    IFX_REG_W32(0xFFFFFFFF, MBOX_IGU3_ISRC);\n    IFX_REG_W32(0x00000000, MBOX_IGU3_IER);\n}\n\nstatic inline void clear_share_buffer(void)\n{\n    volatile u32 *p = SB_RAM0_ADDR(0);\n    unsigned int i;\n\n    for ( i = 0; i < SB_RAM0_DWLEN + SB_RAM1_DWLEN + SB_RAM2_DWLEN + SB_RAM3_DWLEN + SB_RAM4_DWLEN; i++ )\n        IFX_REG_W32(0, p++);\n}\n\nstatic inline int pp32_download_code(u32 *code_src, unsigned int code_dword_len, u32 *data_src, unsigned int data_dword_len)\n{\n    volatile u32 *dest;\n\n    if ( code_src == 0 || ((unsigned long)code_src & 0x03) != 0\n        || data_src == 0 || ((unsigned long)data_src & 0x03) != 0 )\n        return -1;\n\n    if ( code_dword_len <= CDM_CODE_MEMORYn_DWLEN(0) )\n        IFX_REG_W32(0x00, CDM_CFG);\n    else\n        IFX_REG_W32(0x04, CDM_CFG);\n\n    /*  copy code   */\n    dest = CDM_CODE_MEMORY(0, 0);\n    while ( code_dword_len-- > 0 )\n        IFX_REG_W32(*code_src++, dest++);\n\n    /*  copy data   */\n    dest = CDM_DATA_MEMORY(0, 0);\n    while ( data_dword_len-- > 0 )\n        IFX_REG_W32(*data_src++, dest++);\n\n    return 0;\n}\n\nvoid ar9_fw_ver(unsigned int *major, unsigned int *minor)\n{\n    ASSERT(major != NULL, \"pointer is NULL\");\n    ASSERT(minor != NULL, \"pointer is NULL\");\n\n    *major = FW_VER_ID->major;\n    *minor = FW_VER_ID->minor;\n}\n\nvoid ar9_init(struct platform_device *pdev)\n{\n\tinit_pmu();\n\treset_ppe(pdev);\n\tinit_ema();\n\tinit_mailbox();\n\tclear_share_buffer();\n}\n\nvoid ar9_shutdown(void)\n{\n\tltq_pmu_disable(IFX_PMU_MODULE_PPE_SLL01 |\n\t\tIFX_PMU_MODULE_PPE_TC |\n\t\tIFX_PMU_MODULE_PPE_EMA |\n\t\tIFX_PMU_MODULE_PPE_QSB |\n\t\tIFX_PMU_MODULE_TPE |\n\t\tIFX_PMU_MODULE_DSL_DFE);\n}\n\nint ar9_start(int pp32)\n{\n\tint ret;\n\n\tret = pp32_download_code(ar9_fw_bin, sizeof(ar9_fw_bin) / sizeof(*ar9_fw_bin),\n\t\t\tar9_fw_data, sizeof(ar9_fw_data) / sizeof(*ar9_fw_data));\n\tif ( ret != 0 )\n\t\treturn ret;\n\n\tIFX_REG_W32(DBG_CTRL_RESTART, PP32_DBG_CTRL(0));\n\n\tudelay(10);\n\n\treturn 0;\n}\n\nvoid ar9_stop(int pp32)\n{\n\tIFX_REG_W32(DBG_CTRL_STOP, PP32_DBG_CTRL(0));\n}\n\nstruct ltq_atm_ops ar9_ops = {\n\t.init = ar9_init,\n\t.shutdown = ar9_shutdown,\n\t.start = ar9_start,\n\t.stop = ar9_stop,\n\t.fw_ver = ar9_fw_ver,\n};\n\n\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-atm/src/ifxmips_atm_core.h",
    "content": "/******************************************************************************\n**\n** FILE NAME    : ifxmips_atm_core.h\n** PROJECT      : UEIP\n** MODULES      : ATM\n**\n** DATE         : 7 Jul 2009\n** AUTHOR       : Xu Liang\n** DESCRIPTION  : ATM driver header file (core functions)\n** COPYRIGHT    :       Copyright (c) 2006\n**                      Infineon Technologies AG\n**                      Am Campeon 1-12, 85579 Neubiberg, Germany\n**\n**    This program is free software; you can redistribute it and/or modify\n**    it under the terms of the GNU General Public License as published by\n**    the Free Software Foundation; either version 2 of the License, or\n**    (at your option) any later version.\n**\n** HISTORY\n** $Date        $Author         $Comment\n** 17 JUN 2009  Xu Liang        Init Version\n*******************************************************************************/\n\n#ifndef IFXMIPS_ATM_CORE_H\n#define IFXMIPS_ATM_CORE_H\n\n\n#define INT_NUM_IM2_IRL24\t(INT_NUM_IM2_IRL0 + 24)\n#define INT_NUM_IM2_IRL13\t(INT_NUM_IM2_IRL0 + 13)\n#define CONFIG_IFXMIPS_DSL_CPE_MEI\n#define IFX_REG_W32(_v, _r)               __raw_writel((_v), (volatile unsigned int *)(_r))\n#define IFX_REG_R32(_r)                    __raw_readl((volatile unsigned int *)(_r))\n#define IFX_REG_W32_MASK(_clr, _set, _r)   IFX_REG_W32((IFX_REG_R32((_r)) & ~(_clr)) | (_set), (_r))\n#define SET_BITS(x, msb, lsb, value)    (((x) & ~(((1 << ((msb) + 1)) - 1) ^ ((1 << (lsb)) - 1))) | (((value) & ((1 << (1 + (msb) - (lsb))) - 1)) << (lsb)))\n\nstruct ltq_atm_ops {\n\tvoid (*init)(struct platform_device *pdev);\n\tvoid (*shutdown)(void);\n\n\tint (*start)(int pp32);\n\tvoid (*stop)(int pp32);\n\n\tvoid (*fw_ver)(unsigned int *major, unsigned int *minor);\n};\n\n#include <linux/atomic.h>\n#include <lantiq_atm.h>\n\n/*\n * ####################################\n *              Definition\n * ####################################\n */\n\n/*\n *  Compile Options\n */\n\n#define ENABLE_DEBUG                    1\n\n#define ENABLE_ASSERT                   1\n\n#define INLINE\n\n#define DEBUG_DUMP_SKB                  1\n\n#define DEBUG_QOS                       1\n\n#define DISABLE_QOS_WORKAROUND          0\n\n#define ENABLE_DBG_PROC                 1\n\n#define ENABLE_FW_PROC                  1\n\n#ifdef CONFIG_IFX_ATM_TASKLET\n  #define ENABLE_TASKLET                1\n#endif\n\n#ifdef CONFIG_IFX_ATM_RETX\n  #define ENABLE_ATM_RETX               1\n#endif\n\n#if defined(CONFIG_DSL_MEI_CPE_DRV) && !defined(CONFIG_IFXMIPS_DSL_CPE_MEI)\n  #define CONFIG_IFXMIPS_DSL_CPE_MEI    1\n#endif\n\n/*\n *  Debug/Assert/Error Message\n */\n\n#define ifx_atm_dbg_enable 1\n\n#define DBG_ENABLE_MASK_ERR             (1 << 0)\n#define DBG_ENABLE_MASK_DEBUG_PRINT     (1 << 1)\n#define DBG_ENABLE_MASK_ASSERT          (1 << 2)\n#define DBG_ENABLE_MASK_DUMP_SKB_RX     (1 << 8)\n#define DBG_ENABLE_MASK_DUMP_SKB_TX     (1 << 9)\n#define DBG_ENABLE_MASK_DUMP_QOS        (1 << 10)\n#define DBG_ENABLE_MASK_DUMP_INIT       (1 << 11)\n#define DBG_ENABLE_MASK_MAC_SWAP        (1 << 12)\n#define DBG_ENABLE_MASK_ALL             (DBG_ENABLE_MASK_ERR | DBG_ENABLE_MASK_DEBUG_PRINT | DBG_ENABLE_MASK_ASSERT | DBG_ENABLE_MASK_DUMP_SKB_RX | DBG_ENABLE_MASK_DUMP_SKB_TX | DBG_ENABLE_MASK_DUMP_QOS | DBG_ENABLE_MASK_DUMP_INIT | DBG_ENABLE_MASK_MAC_SWAP)\n\n#if defined(ENABLE_ASSERT) && ENABLE_ASSERT\n  #define ASSERT(cond, format, arg...)  do { if ( (ifx_atm_dbg_enable & DBG_ENABLE_MASK_ASSERT) && !(cond) ) printk(KERN_ERR __FILE__ \":%d:%s: \" format \"\\n\", __LINE__, __FUNCTION__, ##arg); } while ( 0 )\n#else\n  #define ASSERT(cond, format, arg...)\n#endif\n\n\n/*\n *  Constants\n */\n#define DEFAULT_TX_LINK_RATE            3200    //  in cells\n\n/*\n *  ATM Port, QSB Queue, DMA RX/TX Channel Parameters\n */\n#define ATM_PORT_NUMBER                 2\n#define MAX_QUEUE_NUMBER                16\n#define OAM_RX_QUEUE                    15\n#define QSB_RESERVE_TX_QUEUE            0\n#define FIRST_QSB_QID                   1\n#define MAX_PVC_NUMBER                  (MAX_QUEUE_NUMBER - FIRST_QSB_QID)\n#define MAX_RX_DMA_CHANNEL_NUMBER       8\n#define MAX_TX_DMA_CHANNEL_NUMBER       16\n#define DATA_BUFFER_ALIGNMENT           EMA_ALIGNMENT\n#define DESC_ALIGNMENT                  8\n#define DEFAULT_RX_HUNT_BITTH           4\n\n/*\n *  RX DMA Channel Allocation\n */\n#define RX_DMA_CH_OAM                   0\n#define RX_DMA_CH_AAL                   1\n#define RX_DMA_CH_TOTAL                 2\n#define RX_DMA_CH_OAM_DESC_LEN          32\n#define RX_DMA_CH_OAM_BUF_SIZE          ((CELL_SIZE + 14) & ~15)\n#define RX_DMA_CH_AAL_BUF_SIZE          (2048 - 48)\n\n/*\n *  OAM Constants\n */\n#define OAM_HTU_ENTRY_NUMBER            3\n#define OAM_F4_SEG_HTU_ENTRY            0\n#define OAM_F4_TOT_HTU_ENTRY            1\n#define OAM_F5_HTU_ENTRY                2\n#define OAM_F4_CELL_ID                  0\n#define OAM_F5_CELL_ID                  15\n#if defined(ENABLE_ATM_RETX) && ENABLE_ATM_RETX\n  #undef  OAM_HTU_ENTRY_NUMBER\n  #define OAM_HTU_ENTRY_NUMBER          4\n  #define OAM_ARQ_HTU_ENTRY             3\n#endif\n\n/*\n *  RX Frame Definitions\n */\n#define MAX_RX_PACKET_ALIGN_BYTES       3\n#define MAX_RX_PACKET_PADDING_BYTES     3\n#define RX_INBAND_TRAILER_LENGTH        8\n#define MAX_RX_FRAME_EXTRA_BYTES        (RX_INBAND_TRAILER_LENGTH + MAX_RX_PACKET_ALIGN_BYTES + MAX_RX_PACKET_PADDING_BYTES)\n\n/*\n *  TX Frame Definitions\n */\n#define MAX_TX_HEADER_ALIGN_BYTES       12\n#define MAX_TX_PACKET_ALIGN_BYTES       3\n#define MAX_TX_PACKET_PADDING_BYTES     3\n#define TX_INBAND_HEADER_LENGTH         8\n#define MAX_TX_FRAME_EXTRA_BYTES        (TX_INBAND_HEADER_LENGTH + MAX_TX_HEADER_ALIGN_BYTES + MAX_TX_PACKET_ALIGN_BYTES + MAX_TX_PACKET_PADDING_BYTES)\n\n#define CELL_SIZE                       ATM_AAL0_SDU\n\n#if defined(ENABLE_ATM_RETX) && ENABLE_ATM_RETX\n  #define RETX_PLAYOUT_BUFFER_ORDER     6\n  #define RETX_PLAYOUT_BUFFER_SIZE      (PAGE_SIZE * (1 << RETX_PLAYOUT_BUFFER_ORDER))\n  #define RETX_PLAYOUT_FW_BUFF_SIZE     (RETX_PLAYOUT_BUFFER_SIZE / (32 * 56 /* cell size */))\n  #define RETX_POLLING_INTERVAL         (HZ / 100 > 0 ? HZ / 100 : 1)\n#endif\n\ntypedef struct {\n\tunsigned int h;\n\tunsigned int l;\n} ppe_u64_t;\n\nstruct port {\n\tunsigned int tx_max_cell_rate;\n\tunsigned int tx_current_cell_rate;\n\n\tstruct atm_dev *dev;\n};\n\nstruct connection {\n\tstruct atm_vcc         *vcc;\n\n\tvolatile struct tx_descriptor *tx_desc;\n\tunsigned int tx_desc_pos;\n\tstruct sk_buff **tx_skb;\n\tspinlock_t lock;\n\n\tunsigned int aal5_vcc_crc_err; /* number of packets with CRC error */\n\tunsigned int aal5_vcc_oversize_sdu; /* number of packets with oversize error */\n\n\tunsigned int port;\n};\n\nstruct atm_priv_data {\n\tunsigned long conn_table;\n\tstruct connection conn[MAX_PVC_NUMBER];\n\n\tvolatile struct rx_descriptor *aal_desc;\n\tunsigned int aal_desc_pos;\n\n\tvolatile struct rx_descriptor *oam_desc;\n\tunsigned char *oam_buf;\n\tunsigned int oam_desc_pos;\n\n\tstruct port port[ATM_PORT_NUMBER];\n\n\tunsigned int wrx_pdu;        /*  successfully received AAL5 packet       */\n\tunsigned int wrx_drop_pdu;   /*  AAL5 packet dropped by driver on RX     */\n\tunsigned int wtx_pdu;        /*  successfully transmitted AAL5 packet    */\n\tunsigned int wtx_err_pdu;    /*  error AAL5 packet                       */\n\tunsigned int wtx_drop_pdu;   /*  AAL5 packet dropped by driver on TX     */\n\n\tunsigned int wrx_oam;        /*  successfully received OAM cell          */\n\tunsigned int wrx_drop_oam;   /*  OAM cell dropped by driver on RX        */\n\tunsigned int wtx_oam;        /*  successfully transmitted OAM cell       */\n\tunsigned int wtx_err_oam;    /*  error during transmiting OAM cell       */\n\tunsigned int wtx_drop_oam;   /*  OAM cell dropped by driver on TX        */\n\n\tppe_u64_t wrx_total_byte;\n\tppe_u64_t wtx_total_byte;\n\tunsigned int prev_wrx_total_byte;\n\tunsigned int prev_wtx_total_byte;\n\n\tvoid *aal_desc_base;\n\tvoid *oam_desc_base;\n\tvoid *oam_buf_base;\n\tvoid *tx_desc_base;\n\tvoid *tx_skb_base;\n};\n\n#include \"ifxmips_atm_ppe_common.h\"\n#include \"ifxmips_atm_fw_regs_common.h\"\n\n#endif\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-atm/src/ifxmips_atm_danube.c",
    "content": "/******************************************************************************\n**\n** FILE NAME    : ifxmips_atm_danube.c\n** PROJECT      : UEIP\n** MODULES      : ATM\n**\n** DATE         : 7 Jul 2009\n** AUTHOR       : Xu Liang\n** DESCRIPTION  : ATM driver common source file (core functions)\n** COPYRIGHT    :       Copyright (c) 2006\n**                      Infineon Technologies AG\n**                      Am Campeon 1-12, 85579 Neubiberg, Germany\n**\n**    This program is free software; you can redistribute it and/or modify\n**    it under the terms of the GNU General Public License as published by\n**    the Free Software Foundation; either version 2 of the License, or\n**    (at your option) any later version.\n**\n** HISTORY\n** $Date        $Author         $Comment\n** 07 JUL 2009  Xu Liang        Init Version\n*******************************************************************************/\n\n\n\n/*\n * ####################################\n *              Head File\n * ####################################\n */\n\n/*\n *  Common Head File\n */\n#include <linux/kernel.h>\n#include <linux/module.h>\n#include <linux/version.h>\n#include <linux/types.h>\n#include <linux/errno.h>\n#include <linux/proc_fs.h>\n#include <linux/init.h>\n#include <linux/ioctl.h>\n#include <linux/platform_device.h>\n#include <linux/delay.h>\n\n/*\n *  Chip Specific Head File\n */\n#include \"ifxmips_atm_core.h\"\n\n#ifdef CONFIG_DANUBE\n\n#include \"ifxmips_atm_fw_danube.h\"\n#include \"ifxmips_atm_fw_regs_danube.h\"\n\n#include <lantiq_soc.h>\n\n#define EMA_CMD_BUF_LEN      0x0040\n#define EMA_CMD_BASE_ADDR    (0x00001580 << 2)\n#define EMA_DATA_BUF_LEN     0x0100\n#define EMA_DATA_BASE_ADDR   (0x00001900 << 2)\n#define EMA_WRITE_BURST      0x2\n#define EMA_READ_BURST       0x2\n\nstatic inline void reset_ppe(struct platform_device *pdev);\n\n#define IFX_PMU_MODULE_PPE_SLL01  BIT(19)\n#define IFX_PMU_MODULE_PPE_TC     BIT(21)\n#define IFX_PMU_MODULE_PPE_EMA    BIT(22)\n#define IFX_PMU_MODULE_PPE_QSB    BIT(18)\n#define IFX_PMU_MODULE_TPE       BIT(13)\n#define IFX_PMU_MODULE_DSL_DFE    BIT(9)\n\nstatic inline void reset_ppe(struct platform_device *pdev)\n{\n/*#ifdef MODULE\n    unsigned int etop_cfg;\n    unsigned int etop_mdio_cfg;\n    unsigned int etop_ig_plen_ctrl;\n    unsigned int enet_mac_cfg;\n\n    etop_cfg            = *IFX_PP32_ETOP_CFG;\n    etop_mdio_cfg       = *IFX_PP32_ETOP_MDIO_CFG;\n    etop_ig_plen_ctrl   = *IFX_PP32_ETOP_IG_PLEN_CTRL;\n    enet_mac_cfg        = *IFX_PP32_ENET_MAC_CFG;\n\n    *IFX_PP32_ETOP_CFG &= ~0x03C0;\n\n    //  reset PPE\n    ifx_rcu_rst(IFX_RCU_DOMAIN_PPE, IFX_RCU_MODULE_ATM);\n\n    *IFX_PP32_ETOP_MDIO_CFG     = etop_mdio_cfg;\n    *IFX_PP32_ETOP_IG_PLEN_CTRL = etop_ig_plen_ctrl;\n    *IFX_PP32_ENET_MAC_CFG      = enet_mac_cfg;\n    *IFX_PP32_ETOP_CFG          = etop_cfg;\n#endif*/\n}\n\n/*\n *  Description:\n *    Download PPE firmware binary code.\n *  Input:\n *    src       --- u32 *, binary code buffer\n *    dword_len --- unsigned int, binary code length in DWORD (32-bit)\n *  Output:\n *    int       --- 0:    Success\n *                  else:           Error Code\n */\nstatic inline int danube_pp32_download_code(u32 *code_src, unsigned int code_dword_len, u32 *data_src, unsigned int data_dword_len)\n{\n\tvolatile u32 *dest;\n\n\tif ( code_src == 0 || ((unsigned long)code_src & 0x03) != 0\n\t\t\t|| data_src == 0 || ((unsigned long)data_src & 0x03) != 0 )\n\t\treturn -1;\n\n\tif ( code_dword_len <= CDM_CODE_MEMORYn_DWLEN(0) )\n\t\tIFX_REG_W32(0x00, CDM_CFG);\n\telse\n\t\tIFX_REG_W32(0x04, CDM_CFG);\n\n\t/*  copy code   */\n\tdest = CDM_CODE_MEMORY(0, 0);\n\twhile ( code_dword_len-- > 0 )\n\t\tIFX_REG_W32(*code_src++, dest++);\n\n\t/*  copy data   */\n\tdest = CDM_DATA_MEMORY(0, 0);\n\twhile ( data_dword_len-- > 0 )\n\t\tIFX_REG_W32(*data_src++, dest++);\n\n\treturn 0;\n}\n\nstatic void danube_fw_ver(unsigned int *major, unsigned int *minor)\n{\n\tASSERT(major != NULL, \"pointer is NULL\");\n\tASSERT(minor != NULL, \"pointer is NULL\");\n\n\t*major = FW_VER_ID->major;\n\t*minor = FW_VER_ID->minor;\n}\n\nstatic void danube_init(struct platform_device *pdev)\n{\n            volatile u32 *p = SB_RAM0_ADDR(0);\n    unsigned int i;\n\n\tltq_pmu_enable(IFX_PMU_MODULE_PPE_SLL01 |\n\t\tIFX_PMU_MODULE_PPE_TC |\n\t\tIFX_PMU_MODULE_PPE_EMA |\n\t\tIFX_PMU_MODULE_PPE_QSB |\n\t\tIFX_PMU_MODULE_TPE |\n\t\tIFX_PMU_MODULE_DSL_DFE);\n\n\treset_ppe(pdev);\n\n    /* init ema */\n        IFX_REG_W32((EMA_CMD_BUF_LEN << 16) | (EMA_CMD_BASE_ADDR >> 2), EMA_CMDCFG);\n    IFX_REG_W32((EMA_DATA_BUF_LEN << 16) | (EMA_DATA_BASE_ADDR >> 2), EMA_DATACFG);\n    IFX_REG_W32(0x000000FF, EMA_IER);\n    IFX_REG_W32(EMA_READ_BURST | (EMA_WRITE_BURST << 2), EMA_CFG);\n\n\t/* init mailbox */\n\tIFX_REG_W32(0xFFFFFFFF, MBOX_IGU1_ISRC);\n\tIFX_REG_W32(0x00000000, MBOX_IGU1_IER);\n\tIFX_REG_W32(0xFFFFFFFF, MBOX_IGU3_ISRC);\n\tIFX_REG_W32(0x00000000, MBOX_IGU3_IER);\n\n    /* init atm tc */\n    IFX_REG_W32(0x0000,     DREG_AT_CTRL);\n    IFX_REG_W32(0x0000,     DREG_AR_CTRL);\n    IFX_REG_W32(0x0,        DREG_AT_IDLE0);\n    IFX_REG_W32(0x0,        DREG_AT_IDLE1);\n    IFX_REG_W32(0x0,        DREG_AR_IDLE0);\n    IFX_REG_W32(0x0,        DREG_AR_IDLE1);\n    IFX_REG_W32(0x40,       RFBI_CFG);\n    IFX_REG_W32(0x1600,     SFSM_DBA0);\n    IFX_REG_W32(0x1718,     SFSM_DBA1);\n    IFX_REG_W32(0x1830,     SFSM_CBA0);\n    IFX_REG_W32(0x1844,     SFSM_CBA1);\n    IFX_REG_W32(0x14014,    SFSM_CFG0);\n    IFX_REG_W32(0x14014,    SFSM_CFG1);\n    IFX_REG_W32(0x1858,     FFSM_DBA0);\n    IFX_REG_W32(0x18AC,     FFSM_DBA1);\n    IFX_REG_W32(0x10006,    FFSM_CFG0);\n    IFX_REG_W32(0x10006,    FFSM_CFG1);\n    IFX_REG_W32(0x00000001, FFSM_IDLE_HEAD_BC0);\n    IFX_REG_W32(0x00000001, FFSM_IDLE_HEAD_BC1);\n\n    for ( i = 0; i < SB_RAM0_DWLEN + SB_RAM1_DWLEN + SB_RAM2_DWLEN + SB_RAM3_DWLEN; i++ )\n        IFX_REG_W32(0, p++);\n}\n\nstatic void danube_shutdown(void)\n{\n}\n\nint danube_start(int pp32)\n{\n\tint ret;\n\n\t/*  download firmware   */\n\tret = danube_pp32_download_code(\n\t\tdanube_fw_bin, sizeof(danube_fw_bin) / sizeof(*danube_fw_bin),\n\t\tdanube_fw_data, sizeof(danube_fw_data) / sizeof(*danube_fw_data));\n\tif ( ret != 0 )\n\t\treturn ret;\n\n\t/*  run PP32    */\n\tIFX_REG_W32(DBG_CTRL_START_SET(1), PP32_DBG_CTRL);\n\n\t/*  idle for a while to let PP32 init itself    */\n\tudelay(10);\n\n\treturn 0;\n}\n\nvoid danube_stop(int pp32)\n{\n\tIFX_REG_W32(DBG_CTRL_STOP_SET(1), PP32_DBG_CTRL);\n}\n\nstruct ltq_atm_ops danube_ops = {\n\t.init = danube_init,\n\t.shutdown = danube_shutdown,\n\t.start = danube_start,\n\t.stop = danube_stop,\n\t.fw_ver = danube_fw_ver,\n};\n\n#endif\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-atm/src/ifxmips_atm_fw_amazon_se.h",
    "content": "#ifndef IFXMIPS_ATM_FW_AMAZON_SE_H\n#define IFXMIPS_ATM_FW_AMAZON_SE_H\n\n\n/******************************************************************************\n**\n** FILE NAME    : ifxmips_atm_fw_amazon_se.h\n** PROJECT      : UEIP\n** MODULES     \t: ATM (ADSL)\n**\n** DATE         : 1 AUG 2005\n** AUTHOR       : Xu Liang\n** DESCRIPTION  : ATM Driver (PP32 Firmware)\n** COPYRIGHT    : \tCopyright (c) 2006\n**\t\t\tInfineon Technologies AG\n**\t\t\tAm Campeon 1-12, 85579 Neubiberg, Germany\n**\n**    This program is free software; you can redistribute it and/or modify\n**    it under the terms of the GNU General Public License as published by\n**    the Free Software Foundation; either version 2 of the License, or\n**    (at your option) any later version.\n**\n** HISTORY\n** $Date        $Author         $Comment\n**  4 AUG 2005  Xu Liang        Initiate Version\n** 23 OCT 2006  Xu Liang        Add GPL header.\n**  9 JAN 2007  Xu Liang        First version got from Anand (IC designer)\n*******************************************************************************/\n\n\n#define VER_IN_FIRMWARE         1\n\n#define ATM_FW_VER_MAJOR        0\n#define ATM_FW_VER_MINOR        16\n\n\nstatic unsigned int firmware_binary_code[] = {\n 0x800004b8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x8000ffe0, 0x00000000, 0x00000000, 0x00000000,\n 0xc1000002, 0xd90c00f8, 0xc2000002, 0xda0800f9, 0x80004cc8, 0xc2000000, 0xda0800f9, 0x80004330,\n 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n 0x800042e8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n 0x800055a8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n 0x800041e8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n 0xc0400000, 0xc0004840, 0xc88400f8, 0x80004988, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n 0xc0400002, 0xc0004840, 0xc88400f8, 0x80004908, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n 0xc3c00004, 0xdbc800f9, 0xc10c0002, 0xd90c00f8, 0x8000fee0, 0x00000000, 0x00000000, 0x00000000,\n 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n 0xc10e0002, 0xd90c00f8, 0xc0004808, 0xc84000f8, 0x80004938, 0x00000000, 0x00000000, 0x00000000,\n 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n 0xc3e1fffe, 0x597dfffe, 0x593dfe14, 0x900004d9, 0x00000000, 0x00000000, 0x00000000, 0x90cc0481,\n 0x00000000, 0x00000000, 0x00000000, 0xc3c00000, 0xdbc800f9, 0xc1400008, 0xc1900000, 0x71588000,\n 0x14100100, 0xc140000a, 0xc1900002, 0x71588000, 0x14100100, 0xc140000c, 0xc1900004, 0x71588000,\n 0x14100100, 0xc1400004, 0xc1900006, 0x71588000, 0x14100100, 0xc1400006, 0xc1900008, 0x71588000,\n 0x14100100, 0xc140000e, 0xc190000a, 0x71588000, 0x14100100, 0xc1400000, 0xc190000c, 0x71588000,\n 0x14100100, 0xc1400002, 0xc190000e, 0x71588000, 0x14100100, 0xc0400000, 0xc11c0000, 0xc000082c,\n 0xcd05ce00, 0xc11c0002, 0xc000082c, 0xcd05ce00, 0xc0400002, 0xc11c0000, 0xc000082c, 0xcd05ce00,\n 0xc11c0002, 0xc000082c, 0xcd05ce00, 0xc0000824, 0x00000000, 0xcbc000f9, 0xcb8000f9, 0xcb4000f9,\n 0xcb0000f8, 0xc0004878, 0x5bfc4000, 0xcfc000f9, 0x5bb84000, 0xcf8000f9, 0x5b744000, 0xcf4000f9,\n 0x5b304000, 0xcf0000f8, 0xc0000a10, 0x00000000, 0xcbc000f9, 0xcb8000f8, 0xc0004874, 0x5bfc4000,\n 0xcfc000f9, 0x5bb84000, 0xcf8000f8, 0xc30001fe, 0xc000140a, 0xcf0000f8, 0xc3000000, 0x7f018000,\n 0xc000042e, 0xcf0000f8, 0xc000040e, 0xcf0000f8, 0xc3c1fffe, 0xc000490e, 0xcfc00078, 0xc000492c,\n 0xcfc00078, 0xc0004924, 0xcfc00038, 0xc0004912, 0xcfc00038, 0xc0004966, 0xcfc00038, 0xc0004968,\n 0xcfc00078, 0xc000496a, 0xcfc00078, 0xc3c1fffe, 0xc00049a0, 0xcfc000f8, 0xc3c00000, 0xc2800020,\n 0xc3000000, 0x7f018000, 0x6ff88000, 0x6fd44000, 0x4395c000, 0x5bb84a00, 0x5838000a, 0xcf0000f8,\n 0x5bfc0002, 0xb7e8ffc8, 0x00000000, 0xc3c00000, 0xc2800010, 0x6ff86000, 0x47bdc000, 0x5bb84c80,\n 0xc3400000, 0x58380004, 0xcb420078, 0x00000000, 0x58380008, 0xcf400078, 0x5bfc0002, 0xb7e8ffb0,\n 0x00000000, 0xc3c00000, 0xc2800020, 0xc348001e, 0xc3000000, 0x7f018000, 0x6ff8a000, 0x6fd44000,\n 0x4795c000, 0x47bdc000, 0x5bb85e00, 0x58380008, 0xcf408418, 0x5838000a, 0xcf0000f8, 0x5bfc0002,\n 0xb7e8ffb0, 0x00000000, 0x00000000, 0xc3e06242, 0x5bfc0020, 0xc0004802, 0xcfc000f8, 0xc161fffe,\n 0x5955fffe, 0x14140000, 0x00000000, 0xc1000000, 0xd91c00f8, 0xc3e01002, 0x5bfd88c0, 0xc3a00f88,\n 0x5bb839a2, 0x99005fa8, 0xdbd800f8, 0xdb9800f9, 0x00000000, 0xc3c00000, 0xdf7f0038, 0xa7ccfff0,\n 0xc3800000, 0xc00048c0, 0xcb818078, 0xc0001408, 0xcfc000f8, 0xc10e0002, 0xd90c00f8, 0x5d3802a6,\n 0xc1000002, 0xd91c1f02, 0x00000000, 0xc121fffe, 0x5911fe14, 0x14100000, 0xa9fe0270, 0xc3c00000,\n 0xddfc00f0, 0x5d3c0000, 0x84000100, 0xc0000c04, 0xcb8000f8, 0xc11c0002, 0x00000000, 0x7391c000,\n 0xcf8000f8, 0xc3800000, 0xc3400080, 0xdf780038, 0xb7b4ffea, 0xc3203002, 0x5b3188c4, 0xc2e00f88,\n 0x5aec100e, 0x99005fa8, 0xdb1800f8, 0xdad800f9, 0x00000000, 0xc3800000, 0xc3400080, 0xdf780038,\n 0xb7b4ffea, 0xc3205002, 0x5b3188c8, 0xc2e00f90, 0x5aec180c, 0x99005fa8, 0xdb1800f8, 0xdad800f9,\n 0x00000000, 0x80000128, 0xc00048cc, 0xca8000f8, 0x00000000, 0xc1000006, 0x76914000, 0x840000fa,\n 0x00000000, 0xa6800070, 0xc3800000, 0xc3400080, 0xdf780038, 0xb7b4ffea, 0xc3202002, 0x5b31c8c6,\n 0xc2e00f88, 0x5aec100e, 0x99005fa8, 0xdb1800f8, 0xdad800f9, 0x00000000, 0xa6820068, 0xc3800000,\n 0xc3400080, 0xdf780038, 0xb7b4ffea, 0xc3204002, 0x5b31c8ca, 0xc2e00f90, 0x5aec180c, 0x99005fa8,\n 0xdb1800f8, 0xdad800f9, 0x00000000, 0xc00048cc, 0xc2800000, 0xce8000f8, 0xc3a00140, 0x5bfc0002,\n 0x47bc8000, 0xc1000000, 0xc53c00fe, 0xdbdc00f0, 0x80000530, 0x00000000, 0x80002130, 0x00000000,\n 0x8000fd70, 0xc0004958, 0xc84000f8, 0x00000000, 0xc3c00002, 0x787c2000, 0xcc4000f8, 0xc0004848,\n 0xcb8400f8, 0xc000495c, 0xcac400f8, 0xc0004844, 0xc88400f8, 0x47ad0000, 0x8400ff82, 0xc000487c,\n 0xc80400f8, 0x00000000, 0x00000000, 0x40080000, 0xca0000f8, 0xc0001624, 0xcb0400f8, 0xa63c007a,\n 0x00000000, 0x00000000, 0xa71eff22, 0x00000000, 0xc0000824, 0xca8400f8, 0x6ca08000, 0x6ca42000,\n 0x46250000, 0x42290000, 0xc35e0002, 0xc6340060, 0xc0001624, 0xcf440078, 0xc2000000, 0xc161fffe,\n 0x5955fffe, 0x14140000, 0x00000000, 0xc0004844, 0xc88400f8, 0xc000082c, 0xca040038, 0x00000000,\n 0x00000000, 0x58880002, 0xb6080018, 0x00000000, 0xc0800000, 0xc0004844, 0xcc840038, 0x5aec0002,\n 0xc000495c, 0xcec400f8, 0x5e6c0006, 0x84000060, 0xc0004848, 0xcb8400f8, 0xc0000838, 0xc2500002,\n 0xce450800, 0x5fb80002, 0xc0004848, 0xcf8400f8, 0x5eec0002, 0xc000495c, 0xcec400f8, 0x00000000,\n 0xc121fffe, 0x5911fe14, 0x14100000, 0x8000fd98, 0xc000495a, 0xc84000f8, 0x00000000, 0xc3c00002,\n 0x787c2000, 0xcc4000f8, 0xc0004960, 0xcac400f8, 0x00000000, 0x00000000, 0x5eec0000, 0x8400010a,\n 0x00000000, 0xb6fc0050, 0xc0001600, 0xca0400f8, 0x00000000, 0x00000000, 0xa61e00d2, 0x6fe90000,\n 0xc0000a28, 0xce850800, 0xc2c00000, 0xc2800004, 0xb6e800a0, 0xc0001604, 0xca8400f8, 0xc0004960,\n 0xcec400f8, 0xa69efcc2, 0x00000000, 0x6fe90000, 0xc0000a28, 0xce850800, 0xc2c00002, 0xc0001600,\n 0xca0400f8, 0x00000000, 0x00000000, 0xa61e002a, 0x6fe90000, 0xc0000a28, 0xce850800, 0xc2c00000,\n 0xc0001604, 0xca8400f8, 0xc0004960, 0xcec400f8, 0xa69efc2a, 0xc2400000, 0xc0000a14, 0xca440028,\n 0x00000000, 0x00000000, 0x466d2000, 0xa4400020, 0xc2800000, 0xdfeb0029, 0x80000010, 0xdfea0029,\n 0xb668f932, 0x00000000, 0xc00048a0, 0xcb0400f8, 0xc0000a10, 0xca8400f8, 0x6f208000, 0x6f242000,\n 0x46250000, 0x42a10000, 0xc2400000, 0xc0000a14, 0xca440028, 0xc35e0002, 0xc6340060, 0xc0001604,\n 0xcf440078, 0x5b300002, 0xb6700018, 0x5aec0002, 0xc3000000, 0xc00048a0, 0xcf0400f8, 0xc0004960,\n 0xcec400f8, 0x8000f868, 0xc0004918, 0xd28000f8, 0xc2000000, 0xdf600038, 0x5e600080, 0x84000272,\n 0x00000000, 0xc161fffe, 0x5955fffe, 0x14140000, 0x00000000, 0xc000480a, 0xca0000f8, 0xc0004912,\n 0xca4000f8, 0xc0004924, 0xca8000f8, 0xc0004966, 0xcac000f8, 0x00000000, 0xc121fffe, 0x5911fe14,\n 0x14100000, 0x76250000, 0x76290000, 0x762d0000, 0x840001ca, 0xc0004918, 0xca4000f8, 0xc28001fe,\n 0x76290000, 0x5a640002, 0x6a254010, 0x5ee80000, 0x8400001a, 0x6aa54000, 0x80000010, 0xc62800f8,\n 0x62818008, 0xc0004918, 0xcf0000f8, 0xc161fffe, 0x5955fffe, 0x14140000, 0x00000000, 0xc0004966,\n 0xca4000f8, 0xc2000002, 0x6a310000, 0x7e010000, 0x76612000, 0xce4000f8, 0x00000000, 0xc121fffe,\n 0x5911fe14, 0x14100000, 0x6f346000, 0x4771a000, 0x5b744c80, 0xc2800000, 0x58340006, 0xca800078,\n 0xc2c00000, 0x58340000, 0xcac000d8, 0xc2400000, 0x5834000a, 0xca420078, 0x6ea82000, 0x42e9e000,\n 0x6f2ca000, 0x42e56000, 0x5aec1400, 0xc3990040, 0xc7381c18, 0xc6f80060, 0x99005fa8, 0xdb9800f8,\n 0xdbd800f9, 0x00000000, 0xdea000f8, 0x46310000, 0x8400fd80, 0xc0004958, 0xc84000f8, 0x00000000,\n 0xc3c00002, 0x787c2000, 0xcc4000f8, 0xc0004848, 0xcb8400f8, 0xc0004844, 0xc88400f8, 0x5fb80000,\n 0x8400f7f2, 0xc0001a1c, 0xca0000f8, 0xc2400002, 0x6a452000, 0x76250000, 0x8400f7c2, 0xc000487c,\n 0xc80400f8, 0x00000000, 0x00000000, 0x40080000, 0xca0000f8, 0xc42400f8, 0x00000000, 0xa63c17da,\n 0x00000000, 0xc0004878, 0xc80400f8, 0x6c908000, 0x45088000, 0x45088000, 0x40100000, 0xca0000f8,\n 0xc42400f8, 0x00000000, 0xc0004934, 0xce0000f8, 0xc2800002, 0xc4681c08, 0xc62821d0, 0xc2600010,\n 0x5a652440, 0xc0004800, 0xcb4000f8, 0xc2200400, 0x5a202400, 0xc7601040, 0xc0001220, 0xce8000f8,\n 0xc0001200, 0xce4000f8, 0xc0001202, 0xce0000f8, 0xc0001240, 0xcb4000f8, 0x00000000, 0x00000000,\n 0xa754ffe0, 0xc2000000, 0xc7600040, 0xa7520042, 0x00000000, 0x00000000, 0x99006720, 0xc0004822,\n 0xc94000f8, 0xc1800002, 0x80001680, 0x58206480, 0xc2000000, 0xca000018, 0xc2400000, 0xca414000,\n 0xc2800000, 0xca812000, 0xc2c00000, 0xcac20018, 0xc0004938, 0xce0000f8, 0xc0004920, 0xce4000f8,\n 0xc0004916, 0xce8000f8, 0xc0004922, 0xcec000f8, 0xa6400540, 0x00000000, 0xc0004938, 0xcbc000f8,\n 0x00000000, 0xc3800000, 0x6ff48000, 0x6fd44000, 0x4355a000, 0x5b744a00, 0x58340000, 0xcb802010,\n 0x00000000, 0xc2000000, 0x6fb46000, 0x4779a000, 0x5b744c80, 0x5834000c, 0xca000020, 0xc000491a,\n 0xcf8000f8, 0x5e200000, 0x8400046a, 0xc2000000, 0xdf610048, 0x5e6001e8, 0x8800ffe8, 0xc2000002,\n 0xc2400466, 0xc2a00000, 0x5aa80000, 0xc0001006, 0xce0000f8, 0xc0001008, 0xce4000f8, 0xc000100a,\n 0xce8000f8, 0x990059e8, 0xc1a0fffe, 0xc0000824, 0xc9840060, 0xc0004934, 0xca4000f8, 0xc2000000,\n 0xc2800002, 0x99005a28, 0xda9800f8, 0xc61400f8, 0xc65800f8, 0xc161fffe, 0x5955fffe, 0x14140000,\n 0x00000000, 0x99005b10, 0xc000491a, 0xc94000f8, 0x00000000, 0x00000000, 0xc121fffe, 0x5911fe14,\n 0x14100000, 0xc0004922, 0xca001118, 0xc3c00000, 0xc3800000, 0xc0004930, 0xce023118, 0xc0004932,\n 0xcbc000d8, 0xc2800000, 0xc000491e, 0xcfc000f8, 0xc0004862, 0xca800060, 0xc3a0001a, 0x5bb94000,\n 0xc6b80060, 0xc000491c, 0xcf8000f8, 0x99005d80, 0xc000491c, 0xc1400000, 0xc9420048, 0x00000000,\n 0x00000000, 0x00000000, 0xa8e2ffe8, 0xc2000000, 0xc1220002, 0xd90c00f8, 0xdf600038, 0x5e600080,\n 0x8400fff2, 0xc000491c, 0xca0000f8, 0xc000491e, 0xca4000f8, 0x00000000, 0x00000000, 0x99005fa8,\n 0xda1800f8, 0xda5800f9, 0x00000000, 0xc2000000, 0xdf610048, 0x5e6001fe, 0x8800ffe8, 0xc0004916,\n 0xca8000f8, 0xc2c00000, 0xdfec0048, 0xc2400000, 0x466d2000, 0x8400004a, 0x5ea80000, 0x8400003a,\n 0xc2600002, 0x99006720, 0xc000482e, 0xc94000f8, 0xc1800002, 0x80000030, 0xc2600000, 0x99006720,\n 0xc000482c, 0xc94000f8, 0xc1800002, 0xc2000068, 0xc6240078, 0xc0004930, 0xce400080, 0xc000491a,\n 0xc98000f8, 0xc0004862, 0xc94000f8, 0x6d9c6000, 0x45d8e000, 0x59dc4c80, 0x99005e08, 0xd95800f8,\n 0xd99800f9, 0xd9d400f8, 0x99005d80, 0xc000491c, 0xc1400000, 0xc9420048, 0xc2000000, 0xdf600038,\n 0x5e600080, 0x8400ffea, 0x00000000, 0xc000491c, 0xca0000f8, 0xc000491e, 0xca4000f8, 0x00000000,\n 0x00000000, 0x99005fa8, 0xda1800f8, 0xda5800f9, 0x00000000, 0x800010e8, 0x00000000, 0x99006720,\n 0xc000482a, 0xc94000f8, 0xc1800002, 0x800010b8, 0xc0004938, 0xcbc000f8, 0x00000000, 0x00000000,\n 0x6ff88000, 0x6fd44000, 0x4395c000, 0x5bb84a00, 0x58380008, 0xca0000f8, 0x00000000, 0x00000000,\n 0xa6000382, 0x00000000, 0xc0004938, 0xcbc000f8, 0xc3000000, 0x00000000, 0x6ff88000, 0x6fd44000,\n 0x4395c000, 0x5bb84a00, 0x58380000, 0xcb002010, 0xc2000000, 0x58380008, 0xca020078, 0x5838000c,\n 0xcac000f8, 0x5838000e, 0xca4000f8, 0xc000491a, 0xcf0000f8, 0xc0004930, 0xcec000f8, 0xc000493c,\n 0xce0000f8, 0xc0004932, 0xce4000f8, 0x5e200000, 0x84000120, 0xc2800000, 0xa6fe00ba, 0x6f206000,\n 0x46310000, 0x5a204c80, 0x5820000c, 0xca800020, 0x00000000, 0x00000000, 0x5ea80000, 0x840001f2,\n 0x00000000, 0xc161fffe, 0x5955fffe, 0x14140000, 0x00000000, 0x99005b10, 0xc000491a, 0xc94000f8,\n 0x00000000, 0x00000000, 0xc121fffe, 0x5911fe14, 0x14100000, 0xc0004930, 0xcac000f8, 0xc0004932,\n 0xca4000f8, 0xc7ec1118, 0xc0004930, 0xcec000f8, 0x5838000c, 0xcec000f8, 0x58000002, 0xce4000f8,\n 0xc0004934, 0xca0000f8, 0xc2400002, 0x6e642000, 0x6e642000, 0x76612000, 0x8400002a, 0xc2400002,\n 0x6e684000, 0x58380008, 0xce804200, 0xa6000020, 0x6e682000, 0x58380008, 0xce802100, 0xc2400002,\n 0x6e642000, 0x76612000, 0x840000ea, 0x58380008, 0xca0000f8, 0xc2800000, 0xc2400000, 0xa60200c0,\n 0xdba800f8, 0x6f386000, 0x47b1c000, 0x5bb84c80, 0x58380004, 0xca400078, 0x58380002, 0xca800078,\n 0x00000000, 0xdeb800f8, 0x46a54000, 0x88000060, 0x00000000, 0xc0004824, 0xca0000f8, 0xc2400002,\n 0x6e640000, 0x5a200002, 0xce0000f8, 0x58380008, 0xce400000, 0x80000018, 0x00000000, 0x80000048,\n 0xc0004934, 0xca0000f8, 0x00000000, 0x00000000, 0xa6020c6a, 0x00000000, 0x00000000, 0x80000c98,\n 0xc2800000, 0xc2000200, 0xc240001a, 0xdf690048, 0x46294000, 0x46a54000, 0x8800ffd2, 0xc2000006,\n 0xc2600982, 0x5a643b6e, 0x5838000a, 0xca8000f8, 0xc0001006, 0xce0000f8, 0xc0001008, 0xce4000f8,\n 0xc000100a, 0xce8000f8, 0x990059e8, 0xc1a0fffe, 0xc0000824, 0xc9840060, 0xc2000000, 0xc0004930,\n 0xca02e008, 0x58380026, 0xca4000f8, 0x00000000, 0xc2800000, 0x99005a28, 0xda9800f8, 0xc61400f8,\n 0xc65800f8, 0xc0004934, 0xca0000f8, 0x00000000, 0x00000000, 0xa6020022, 0x00000000, 0x00000000,\n 0x80000318, 0xc0004938, 0xcbc000f8, 0xc0004878, 0xc80400f8, 0x6c908000, 0x45088000, 0x45088000,\n 0x40100000, 0xca0000f8, 0xc42400f8, 0x00000000, 0x58240018, 0xca0000f8, 0x6ff88000, 0x6fd44000,\n 0x4395c000, 0x5bb84a00, 0xc3000000, 0xc3400002, 0xc2c00000, 0xc62c0078, 0xc6270038, 0xc0004940,\n 0xce400038, 0xc6260038, 0xc0004942, 0xce400038, 0xc000493c, 0xca0000f8, 0x5eec0000, 0x8400018a,\n 0x5a6c0010, 0x46254000, 0x88000190, 0x5a600052, 0x46e54000, 0x88000178, 0x58380006, 0xca8000f8,\n 0xc0004940, 0xca0000f8, 0xc2400000, 0xc6a70038, 0x7e412000, 0x76612000, 0xc2000000, 0xc6a10038,\n 0x46250000, 0x84000138, 0xc0004942, 0xca0000f8, 0xc2400000, 0xc6a60038, 0x7e412000, 0x76612000,\n 0xc2000000, 0xc6a00038, 0x58380002, 0xca8000f8, 0x46250000, 0x840000e8, 0xc2400000, 0xc6a60078,\n 0x466d0000, 0x880000da, 0xc2400000, 0xc6a40078, 0x58380008, 0xca8000f8, 0x46e50000, 0x880000ba,\n 0x00000000, 0xa6820018, 0x00000000, 0xc7700b00, 0xa6840098, 0x00000000, 0xc7700a00, 0x80000080,\n 0xc7700200, 0xc000493c, 0xcac000f8, 0x80000060, 0xc7700300, 0xc000493c, 0xcac000f8, 0x80000040,\n 0xc7700900, 0x80000030, 0xc7700800, 0x80000020, 0xc7700700, 0x80000010, 0xc7700500, 0xc0004944,\n 0xcf0000f8, 0xc000493e, 0xcec000f8, 0xc0004938, 0xca4000f8, 0xc000493c, 0xcb8000f8, 0xc000493e,\n 0xcb4000f8, 0xc3000000, 0x6e608000, 0x6e544000, 0x42150000, 0x5a204a00, 0x5aa00008, 0x58200004,\n 0xcb000078, 0xc0004934, 0xca0000f8, 0xc2400000, 0xc0004930, 0xca42e008, 0xc3c00018, 0xa6020098,\n 0x00000000, 0x43656000, 0x47ad0000, 0x88000050, 0x46f96000, 0x6ee04010, 0x5be00004, 0xc2000000,\n 0xc6e00008, 0x5e200000, 0x84000042, 0x5bfc0002, 0x80000030, 0xc3c00004, 0x5a2c0008, 0x47a10000,\n 0x88000012, 0x5fb80008, 0x6fe04000, 0x42390000, 0x47212000, 0x88000068, 0xc2400000, 0xc0004930,\n 0xca42e008, 0xc2060002, 0xc68000f8, 0xce006300, 0x6fe04000, 0x4721c000, 0x5f700010, 0x4765a000,\n 0xc2000000, 0xc6340008, 0xc25a000a, 0xc000491a, 0xca401c18, 0xc2800000, 0xc0004932, 0xca8000d8,\n 0xc0004862, 0xca400060, 0x6fa04010, 0x42290000, 0xc000491e, 0xce0000f8, 0xc7e41048, 0xc000491c,\n 0xce4000f8, 0x6fe04000, 0x43a1c000, 0xc000493c, 0xcf8000f8, 0xc000493e, 0xcf4000f8, 0xc000493a,\n 0xcfc000f8, 0x80000008, 0x00000000, 0x00000000, 0x00000000, 0xc2000000, 0xdce000f8, 0xa622ffd8,\n 0xc1220002, 0xd90c00f8, 0xc0004938, 0xcbc000f8, 0xc0004944, 0xcb4000f8, 0xc0004862, 0xcb0000f8,\n 0xc0004934, 0xca0000f8, 0x6ff88000, 0x6fd44000, 0x4395c000, 0x5bb84a00, 0xa6020268, 0xc2400000,\n 0x58380008, 0xca406000, 0xdfe800f8, 0xc2218e08, 0x5a21baf6, 0x46a14000, 0x84000022, 0xc2080002,\n 0x7361a000, 0x80000058, 0x5e640000, 0x84000022, 0xc20c0002, 0x7361a000, 0x80000030, 0xc2000000,\n 0xc760e710, 0xc7604218, 0x5e200000, 0x84000272, 0xc2200002, 0xc0004930, 0xce021000, 0x99006720,\n 0xc0004828, 0xc94000f8, 0xc1800002, 0x58380000, 0xca0000f8, 0x00000000, 0x00000000, 0xa6000132,\n 0xc0004940, 0xca8000f8, 0xc0004942, 0xca4000f8, 0xc7600078, 0xc6a01838, 0xc6601038, 0xc000493a,\n 0xca4000f8, 0xc0004934, 0xca8000f8, 0xc0005600, 0x40300000, 0x40240000, 0x5c000004, 0x5ec05800,\n 0x88000012, 0x5c000200, 0xce0000f8, 0x58000002, 0x5ec05800, 0x88000012, 0x5c000200, 0xce8000f8,\n 0xc000493e, 0xca0000f8, 0xc2400000, 0x5838000c, 0xce4000f8, 0x99006720, 0xc0004830, 0xc94000f8,\n 0xc61800f8, 0xc0004930, 0xc6100078, 0xcd000078, 0x800000a8, 0xc2400002, 0x58380008, 0xce400000,\n 0xc0004944, 0xcf4000f8, 0x80000278, 0xc000493c, 0xca4000f8, 0xdfe800f8, 0x5a300018, 0xc0005600,\n 0x40200000, 0xca0000f8, 0x58380008, 0xc6501078, 0xcd021078, 0x5838000a, 0xce8000f8, 0x58380026,\n 0xce0000f8, 0xc0004944, 0xcf4000f8, 0x99005d80, 0xc000491c, 0xc1400000, 0xc9420048, 0x80000038,\n 0x00000000, 0x99006720, 0xc0004826, 0xc94000f8, 0xc1800002, 0x8000fdd8, 0xc2000000, 0xc2400080,\n 0xdf600038, 0xb624ffea, 0xc000491c, 0xca4000f8, 0xc000491e, 0xca8000f8, 0x99005fa8, 0xda5800f8,\n 0xda9800f9, 0x00000000, 0xc0004934, 0xca0000f8, 0x00000000, 0xc2800000, 0xa6020160, 0xc2400004,\n 0xc2000200, 0xdf690048, 0x46294000, 0x46a54000, 0x8800ffda, 0x00000000, 0xc000491a, 0xc98000f8,\n 0xc0004862, 0xc94000f8, 0x6d9c6000, 0x45d8e000, 0x59dc4c80, 0x99005e08, 0xd95800f8, 0xd99800f9,\n 0xd9d400f8, 0x99005d80, 0xc000491c, 0xc1400000, 0xc9420048, 0xc2000000, 0xc2400080, 0xdf600038,\n 0xb624ffea, 0xc000491c, 0xca4000f8, 0xc000491e, 0xca8000f8, 0x99005fa8, 0xda5800f8, 0xda9800f9,\n 0x00000000, 0x58380008, 0xca4000f8, 0xc2000000, 0xce000018, 0xc2a1fffe, 0x5aa9fffe, 0xce021078,\n 0x5838000a, 0xce8000f8, 0xc161fffe, 0x5955fffe, 0x14140000, 0x00000000, 0xc0000838, 0xc2500002,\n 0xce450800, 0xc0004848, 0xcb8400f8, 0xc2000000, 0xc000082c, 0xca040028, 0x5fb80002, 0xc0004848,\n 0xcf8400f8, 0x58880002, 0xb6080018, 0x00000000, 0xc0800000, 0xc0004844, 0xcc8400f8, 0x00000000,\n 0xc121fffe, 0x5911fe14, 0x14100000, 0x8000ded8, 0xc2000000, 0xdf600038, 0x5e200080, 0x8400026a,\n 0x00000000, 0xc161fffe, 0x5955fffe, 0x14140000, 0x00000000, 0xc000480c, 0xca0000f8, 0xc0004910,\n 0xca4000f8, 0xc000492c, 0xca8000f8, 0xc0004968, 0xcac000f8, 0x00000000, 0xc121fffe, 0x5911fe14,\n 0x14100000, 0x76250000, 0x76290000, 0x76e16000, 0x840001c2, 0xc0004926, 0xca4000f8, 0xc201fffe,\n 0x76e16000, 0x5a640002, 0x6ae50010, 0x5f200000, 0x8400001a, 0x6a250000, 0x80000010, 0xc6e000f8,\n 0x62014008, 0xc0004926, 0xce8000f8, 0xc161fffe, 0x5955fffe, 0x14140000, 0x00000000, 0xc0004968,\n 0xca4000f8, 0xc2000002, 0x6a290000, 0x7e010000, 0x76612000, 0xce4000f8, 0x00000000, 0xc121fffe,\n 0x5911fe14, 0x14100000, 0x6eb4a000, 0x6e944000, 0x4755a000, 0x4769a000, 0x5b745e00, 0x58340002,\n 0xc2000000, 0xca0000d8, 0x5834002e, 0xc2400000, 0xca400078, 0x6eb0a000, 0x6ebc4000, 0x473d8000,\n 0x47298000, 0x5b301e2e, 0x5b300004, 0x6e642000, 0x4225e000, 0xc39a8024, 0xc7380060, 0xc6b81c18,\n 0x99005fa8, 0xdb9800f8, 0xdbd800f9, 0x00000000, 0xc2000000, 0xdf600038, 0x5e200080, 0x84000352,\n 0x00000000, 0xc161fffe, 0x5955fffe, 0x14140000, 0x00000000, 0xc000490e, 0xca0000f8, 0xc00049a0,\n 0xca8000f8, 0xc000492a, 0xca4000f8, 0xc000496a, 0xcb0000f8, 0xc0004956, 0xcac000f8, 0x00000000,\n 0xc121fffe, 0x5911fe14, 0x14100000, 0x77218000, 0x77258000, 0x77298000, 0x8400029a, 0xc201fffe,\n 0x77218000, 0x5aec0002, 0x6b2d0010, 0x5ea00000, 0x8400001a, 0x6a2d0000, 0x80000010, 0xc72000f8,\n 0x62016008, 0xc0004956, 0xcec000f8, 0x6ef4a000, 0x6ed44000, 0x4755a000, 0x476da000, 0x5b745e00,\n 0x58340000, 0xc9c000f8, 0xc00049a0, 0xca0000f8, 0xc3000000, 0xc5f04018, 0xc2400000, 0xc5e50038,\n 0x7e412000, 0x76250000, 0xce0000f8, 0xc0004980, 0x40300000, 0xcec000f8, 0xc161fffe, 0x5955fffe,\n 0x14140000, 0x00000000, 0xc000496a, 0xca4000f8, 0xc2000002, 0x6a2d0000, 0x7e010000, 0x76612000,\n 0xce4000f8, 0x00000000, 0xc121fffe, 0x5911fe14, 0x14100000, 0x6ef4a000, 0x6ed44000, 0x4755a000,\n 0x476da000, 0x5b745e00, 0x5834000e, 0xc2000000, 0xca0000d8, 0x58340008, 0xc2400000, 0xca420078,\n 0x5834000c, 0xc2800000, 0xca832010, 0x6e644010, 0x42250000, 0x4229e000, 0xc39a8008, 0x58340008,\n 0xcb809018, 0x58340008, 0xc2800000, 0xca810010, 0x6ee0a000, 0x6ee44000, 0x46250000, 0x462d0000,\n 0x5a200008, 0x5a201e08, 0x42290000, 0xc6380060, 0xc6f81c18, 0x99005fa8, 0xdb9800f8, 0xdbd800f9,\n 0x00000000, 0xc000495a, 0xc84000f8, 0x00000000, 0xc3c00002, 0x787c2000, 0xcc4000f8, 0xc0001a1c,\n 0xca0000f8, 0xc2400008, 0x6a452000, 0x76250000, 0x84000ec2, 0xc0000a28, 0xc3800000, 0xcb840028,\n 0xc0000a14, 0xc3400000, 0xcb440028, 0xc0004880, 0xcb0400f8, 0xb7b40072, 0x58041802, 0xcac000f8,\n 0xa7000078, 0x00000000, 0x00000000, 0xa6c8d598, 0xc1000000, 0xc6d00018, 0xc0004980, 0x40100000,\n 0xca8000f8, 0x80000070, 0x00000000, 0x00000000, 0x00000000, 0x8000d548, 0x00000000, 0xc2800000,\n 0xc7282018, 0xc000490e, 0xca4000f8, 0x6be9e000, 0x00000000, 0x767d2000, 0x8400d500, 0x6ea0a000,\n 0x6e944000, 0x46150000, 0x46290000, 0x5a205e00, 0x5820000c, 0xca0000f8, 0xc0004946, 0xce8000f8,\n 0xa62203a8, 0x00000000, 0xc2200060, 0xc0004948, 0xce000008, 0xce021038, 0xc240000a, 0xc000494a,\n 0xce4000f8, 0xc2b60002, 0xc0004964, 0xce837b00, 0x99006278, 0xc00048a0, 0xc88400f8, 0x00000000,\n 0xc0004946, 0xcbc000f8, 0x00000000, 0x00000000, 0x6ff8a000, 0x6fd44000, 0x4795c000, 0x47bdc000,\n 0x5bb85e00, 0x99006038, 0xdbd800f8, 0xdb9800f9, 0x00000000, 0x99005d80, 0xc000491c, 0xc1400000,\n 0xc9420048, 0xc000491c, 0x99006230, 0xc94000f9, 0xc98000f8, 0x00000000, 0x99005fa8, 0xd95800f8,\n 0xd99800f9, 0x00000000, 0xc161fffe, 0x5955fffe, 0x14140000, 0x00000000, 0x99005c70, 0xdbd800f8,\n 0xdb9800f9, 0xc7d800f8, 0x00000000, 0xc121fffe, 0x5911fe14, 0x14100000, 0x6ff8a000, 0x6fd44000,\n 0x4795c000, 0x47bdc000, 0x5bb85e00, 0x58380010, 0xca0000f8, 0xc0004874, 0xc80400f8, 0x6c908000,\n 0x45088000, 0x45088000, 0x40100000, 0xca4000f8, 0xc43400f8, 0x00000000, 0xc74000f8, 0xce0000f8,\n 0xc161fffe, 0x5955fffe, 0x14140000, 0x00000000, 0xc000490e, 0xca4000f8, 0xc2800002, 0x6abd4000,\n 0x72692000, 0xce4000f8, 0x00000000, 0xc121fffe, 0x5911fe14, 0x14100000, 0x99006720, 0xc0004836,\n 0xc94000f8, 0xc1800002, 0x00000000, 0x00000000, 0x00000000, 0xa8e2ffe8, 0x00000000, 0x58380000,\n 0xc90000f8, 0xc00049a0, 0xca0000f8, 0xc2800000, 0xc5290038, 0x72290000, 0xce0000f8, 0xc1220002,\n 0xd90c00f8, 0xc2000000, 0xc0000a14, 0xca040028, 0xc0000a28, 0xc2500002, 0xce450800, 0x58880002,\n 0xb6080018, 0xc00048a0, 0xc0800000, 0xcc8400f8, 0x8000d110, 0xc0004946, 0xcbc000f8, 0xc161fffe,\n 0x5955fffe, 0x14140000, 0x00000000, 0xc000490e, 0xca4000f8, 0xc2800002, 0x6abd4000, 0x72692000,\n 0xce4000f8, 0x00000000, 0xc121fffe, 0x5911fe14, 0x14100000, 0x6ff8a000, 0x6fd44000, 0x4795c000,\n 0x47bdc000, 0x5bb85e00, 0x58380008, 0xca0000f8, 0x5838000c, 0xca4000f8, 0xc3400000, 0xc6340000,\n 0xc000494e, 0xcf4000f8, 0xc2800000, 0xc62a0078, 0xc3000000, 0xc6308018, 0x6f304000, 0x43298000,\n 0xc000493c, 0xcf0000f8, 0xc2c00000, 0xc66c0078, 0xc0004950, 0xcec000f8, 0xc2800000, 0xc66ae020,\n 0xc0004954, 0xce8000f8, 0x5f740000, 0x840001a0, 0x5e300028, 0x46e12000, 0x8400016a, 0x46e12000,\n 0x88000132, 0x5e300018, 0x46e12000, 0x8800002a, 0x46e12000, 0x84000042, 0x00000000, 0x800000c0,\n 0x00000000, 0x990063b8, 0xdbd800f8, 0xdb9800f9, 0xc78000f8, 0xc3400002, 0xc000494e, 0xcf4000f8,\n 0xc161fffe, 0x5955fffe, 0x14140000, 0x00000000, 0xc000490e, 0xca4000f8, 0xc2800002, 0x6abd4000,\n 0x7e814000, 0x76692000, 0xce4000f8, 0x00000000, 0xc121fffe, 0x5911fe14, 0x14100000, 0xc2200060,\n 0xc0004948, 0xce021038, 0xc2000000, 0xc000494c, 0xce0000f8, 0x80000080, 0x00000000, 0x990063b8,\n 0xdbd800f8, 0xdb9800f9, 0xc78000f8, 0x990065b8, 0xdbd800f8, 0xdb9800f9, 0xc78000f8, 0xc2200058,\n 0xc0004948, 0xce021038, 0xc2000002, 0xc000494c, 0xce0000f8, 0xc2000006, 0xc0001006, 0xce0000f8,\n 0x5838000a, 0xca4000f8, 0xc2200982, 0x5a203b6e, 0xc0001008, 0xce0000f8, 0xc000100a, 0xce4000f8,\n 0xc0004954, 0xca8000f8, 0xc200000c, 0xc000494a, 0xce0000f8, 0xc0004948, 0xce800008, 0xc2b60000,\n 0xc0004964, 0xce8000f8, 0x99006278, 0xc00048a0, 0xc88400f8, 0x00000000, 0xc0004946, 0xcbc000f8,\n 0xc000494c, 0xca0000f8, 0x6ff8a000, 0x6fd44000, 0x4795c000, 0x47bdc000, 0x5bb85e00, 0x5e200000,\n 0x840000fa, 0x00000000, 0x99006038, 0xdbd800f8, 0xdb9800f9, 0x00000000, 0x99005d80, 0xc000491c,\n 0xc1400000, 0xc9420048, 0xc000491c, 0x99006230, 0xc94000f9, 0xc98000f8, 0x00000000, 0x99005fa8,\n 0xd95800f8, 0xd99800f9, 0x00000000, 0xc161fffe, 0x5955fffe, 0x14140000, 0x00000000, 0x99005c70,\n 0xdbd800f8, 0xdb9800f9, 0xc7d800f8, 0x00000000, 0xc121fffe, 0x5911fe14, 0x14100000, 0xc000493c,\n 0xca8000f8, 0xc000494e, 0xcac000f8, 0xc3000018, 0xc3400006, 0x5e200000, 0x8400002a, 0xc2800000,\n 0xc2c00000, 0xc300001e, 0xc3400000, 0xc6ac1078, 0xc72c0418, 0xc76c0810, 0x58380010, 0xca8000f8,\n 0x58380008, 0xcec000f8, 0xc6280100, 0xc0004874, 0xc80400f8, 0x6c908000, 0x45088000, 0x45088000,\n 0x40100000, 0xcb0000f8, 0xc43400f8, 0x00000000, 0xc74000f8, 0xce8000f8, 0xc0004952, 0xce8000f8,\n 0x00000000, 0x00000000, 0x00000000, 0xa8e2ffe8, 0x00000000, 0xc000494c, 0xca0000f8, 0xc0004950,\n 0xcac000f8, 0x5e200000, 0x8400006a, 0xdfe800f8, 0x7e814000, 0x5834001a, 0xce8000f8, 0x99006720,\n 0xc0004834, 0xc94000f8, 0xc1800002, 0x99006720, 0xc0004838, 0xc94000f8, 0xc6d800f8, 0xc1220002,\n 0xd90c00f8, 0x5e200000, 0x84000040, 0x5838002c, 0xcb0000f8, 0xdfe800f8, 0x00000000, 0x58380014,\n 0xcf0000f8, 0x80000058, 0xc2a1fffe, 0x5aa9fffe, 0x58380000, 0xc90000f8, 0xc00049a0, 0xcb0000f8,\n 0xc2c00000, 0xc52d0038, 0x732d8000, 0xcf0000f8, 0x5838000a, 0xce8000f8, 0xc3000000, 0xc0000a14,\n 0xcb040028, 0xc2d00002, 0xc0000a28, 0xcec50800, 0xc000494e, 0xca8000f8, 0x58880002, 0xb4b00018,\n 0xc00048a0, 0xc0800000, 0xcc8400f8, 0x5ea80000, 0x8400017a, 0x5e200000, 0x84000168, 0xc000493c,\n 0xca8000f8, 0x00000000, 0x00000000, 0x5aa80060, 0xce8000f8, 0x990063b8, 0xdbd800f8, 0xdb9800f9,\n 0xc78000f8, 0x990065b8, 0xdbd800f8, 0xdb9800f9, 0xc78000f8, 0x58380000, 0xcac000f8, 0x00000000,\n 0xc2000000, 0xc6e04018, 0xc0004952, 0xcac000f8, 0x58380000, 0xca8000f8, 0xc30c0002, 0xc6300018,\n 0xa6800098, 0x00000000, 0x00000000, 0xc161fffe, 0x5955fffe, 0x14140000, 0x00000000, 0xc0001800,\n 0xca0000f8, 0x00000000, 0x00000000, 0xa60cffea, 0xc6f00500, 0xc6b0c400, 0xcf0000f8, 0x00000000,\n 0xc121fffe, 0x5911fe14, 0x14100000, 0x8000c758, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n 0x8000c6f0, 0xdcbc00f9, 0x5ffc0000, 0x84000052, 0xc3800002, 0xdb8800f9, 0x5ffc0004, 0x8400bf4a,\n 0xc3800000, 0xdb8800f9, 0xc3ce0002, 0xc0000800, 0xcfc0e700, 0xc3e1fffe, 0x597dfffe, 0x593dfe14,\n 0x94000001, 0x00000000, 0x00000000, 0x00000000, 0xc000487c, 0xc80400f8, 0x00000000, 0x00000000,\n 0x40080000, 0xcbc000f8, 0xc43800f8, 0x00000000, 0xc000480e, 0xca0000f8, 0xc0004858, 0xcb4400f8,\n 0x00000000, 0x00000000, 0x47610000, 0x880000b0, 0x00000000, 0xa7c00048, 0xc0004854, 0xc1000002,\n 0xcd0400f8, 0xc11c0000, 0xc000082c, 0xcd05ce00, 0x800000d8, 0x00000000, 0xa7d20138, 0x00000000,\n 0xc7e14040, 0xc2400000, 0xc6246028, 0xc200006a, 0x46250000, 0xc6240030, 0xc0000810, 0xce440030,\n 0x8000ff70, 0xc2000000, 0xc0000808, 0xca040010, 0xc11c0000, 0xc000082c, 0xcd05ce00, 0x5a200002,\n 0x5e600010, 0x84000010, 0xc2000000, 0xc0000808, 0xce040010, 0xc3400000, 0x80000028, 0xc1200002,\n 0xc0000818, 0xcd061000, 0x5b740002, 0xc0004858, 0xcf4400f8, 0x990059c0, 0xc0004848, 0xc94400f8,\n 0xc1800000, 0xc11c0002, 0xc000082c, 0xcd05ce00, 0x80000600, 0x5b740002, 0xc0004858, 0xcf4400f8,\n 0xc78000f8, 0xc13c0002, 0xcd03de00, 0xc0004848, 0xc94400f8, 0xc1800000, 0xc000082c, 0xc9840028,\n 0x59540002, 0xc0004848, 0xcd4400f8, 0x58880002, 0xb4980580, 0x00000000, 0xc0800000, 0x80000568,\n 0xc000487c, 0xc80400f8, 0x00000000, 0x00000000, 0x40080000, 0xcbc000f8, 0xc42800f8, 0x00000000,\n 0xa7c00130, 0xc000484c, 0xca0400f8, 0xc2400000, 0xc0001aec, 0xca440018, 0x5a200002, 0xc000484c,\n 0xce0400f8, 0xb624008a, 0xc68000f8, 0xc13c0002, 0xcd03de00, 0xc0004848, 0xc94400f8, 0xc1800000,\n 0xc000082c, 0xc9840028, 0x59540002, 0xc0004848, 0xcd4400f8, 0x58880002, 0xb4980470, 0x00000000,\n 0xc0800000, 0x80000458, 0xc0004854, 0xc1000004, 0xcd0400f8, 0xc0000820, 0xc2000002, 0xce0400f8,\n 0xc2000000, 0xc000484c, 0xce0400f8, 0xc0004858, 0xce0400f8, 0x8000ff28, 0xc0004854, 0xc1000000,\n 0xcd0400f8, 0xc11c0000, 0xc000082c, 0xcd05ce00, 0x990059c0, 0xc0004848, 0xc94400f8, 0xc1800000,\n 0xc1200000, 0xc0000818, 0xcd061000, 0xc11c0002, 0xc000082c, 0xcd05ce00, 0xc2000000, 0xc000484c,\n 0xce0400f8, 0x80000358, 0xc0001ac0, 0xcb8400f8, 0xc000487c, 0xc80400f8, 0x00000000, 0x00000000,\n 0x40080000, 0xcbc000f8, 0xc42800f8, 0x00000000, 0x00000000, 0xc68000f8, 0xc13c0000, 0xcd03de00,\n 0xa780024a, 0x00000000, 0x00000000, 0xa7c0020a, 0x00000000, 0xc0001b00, 0xc2060006, 0xce046308,\n 0xa7e801c2, 0x00000000, 0xc0004850, 0xca0400f8, 0xc2400000, 0xc0001aec, 0xca448018, 0x5a200002,\n 0xc0004850, 0xce0400f8, 0xb62400aa, 0x00000000, 0xc68000f8, 0xc13c0002, 0xcd03de00, 0xc0001acc,\n 0xc2000002, 0xce040000, 0xc0004848, 0xc94400f8, 0xc1800000, 0xc000082c, 0xc9840028, 0x59540002,\n 0xc0004848, 0xcd4400f8, 0x58880002, 0xb49801c8, 0x00000000, 0xc0800000, 0x800001b0, 0xc0004854,\n 0xc1000000, 0xcd0400f8, 0xc11c0000, 0xc000082c, 0xcd05ce00, 0x990059c0, 0xc0004848, 0xc94400f8,\n 0xc1800000, 0xc2000000, 0xc0000820, 0xce0400f8, 0xc1200000, 0xc0000818, 0xcd061000, 0xc11c0002,\n 0xc000082c, 0xcd05ce00, 0xc0004850, 0xce0400f8, 0xc2000002, 0xc0001acc, 0xce040008, 0x800000e8,\n 0xc2000002, 0xc0004850, 0xce0400f8, 0x8000fe88, 0xc2000000, 0xc0004850, 0xce0400f8, 0xa7e60032,\n 0x00000000, 0xc2000002, 0xc0001b00, 0xce040000, 0x8000fe70, 0x00000000, 0xa7860052, 0x00000000,\n 0xc68000f8, 0xc13c0002, 0xcd03de00, 0xc2020002, 0xc7e2a540, 0xc0001b00, 0xce0400f8, 0x8000fe18,\n 0xc2040002, 0xc0001b00, 0xce044200, 0x8000fdf8, 0xc2c80002, 0x6ac56000, 0xdacc00f8, 0xc0004854,\n 0xcb4400f8, 0xc0004848, 0xcb8400f8, 0xc0000838, 0xc3c00000, 0xcbc40028, 0x5ef40004, 0x84000022,\n 0xc3000000, 0xc0001acc, 0xcf042100, 0x47f98000, 0x8400002a, 0x47f98000, 0x88000030, 0xc1006e8c,\n 0x8000b380, 0xc0004840, 0xcc8400f8, 0x8000f6b0, 0xc0001ac0, 0xcac400f8, 0xc0004854, 0xcb4400f8,\n 0xa6c0fbd2, 0x00000000, 0x5ef40000, 0x8400f70a, 0x5ef40002, 0x8400f99a, 0x5ef40004, 0x8400fb9a,\n 0xc1006ce8, 0x8000b2f8, 0x00000000, 0xc0800000, 0xdf4b0038, 0xc0004900, 0xcb8000f8, 0xc2000000,\n 0xc000490a, 0xa78000d0, 0xcbc000f8, 0xc1000000, 0xd90000f9, 0xc1000002, 0xd90c00f8, 0x6ff46000,\n 0x477da000, 0x5b744c80, 0xc2400000, 0x58340004, 0xca400078, 0xc0004900, 0xce000000, 0x5a640002,\n 0x58340004, 0xc6500078, 0xcd000078, 0xc0004914, 0xca4000f8, 0xc2000002, 0x6a3d0000, 0x72612000,\n 0xce4000f8, 0xc0000408, 0xce0000f8, 0xa78200d8, 0xc0004908, 0xcbc000f8, 0xc1000000, 0xd90000f9,\n 0xc1000002, 0xd90c00f8, 0x6ff4a000, 0x6fd44000, 0x4755a000, 0x477da000, 0x5b745e00, 0xc2800000,\n 0x58340006, 0xca800078, 0xc2000000, 0xc0004900, 0xce002100, 0x5ea80002, 0x58340006, 0xc6900078,\n 0xcd000078, 0x5a7c0020, 0xc2000002, 0x6a250000, 0xc0000408, 0xce0000f8, 0xdca800f9, 0x5ea80000,\n 0x8400b168, 0x00000000, 0xa4800230, 0x00000000, 0xc3c00000, 0xc000140e, 0xcbc00018, 0xc3400000,\n 0xc2400000, 0x6ff86000, 0x47bdc000, 0x5bb84c80, 0x58380008, 0xcb400078, 0x58380006, 0xca400078,\n 0x5f740002, 0x58380008, 0xc7500078, 0xcd000078, 0xc2000000, 0x58380004, 0xca020078, 0xc3000000,\n 0x5838000c, 0xcb000020, 0x5a640002, 0x46610000, 0x84000010, 0xc2400000, 0x58380006, 0xc6500078,\n 0xcd000078, 0xc2000000, 0x5838000a, 0xca020078, 0x5b300002, 0x5838000c, 0xc7100020, 0xcd000020,\n 0xc2420020, 0x5a200004, 0x46252000, 0x84000010, 0xc2000000, 0x5838000a, 0xc6101078, 0xcd021078,\n 0xc0004966, 0xca4000f8, 0xc2000002, 0x6a3d0000, 0x72612000, 0xce4000f8, 0x5f740000, 0x84000040,\n 0xc0004912, 0xca0000f8, 0xc2c00002, 0x6afd6000, 0x7ec16000, 0x762d0000, 0xce0000f8, 0x5f300020,\n 0x84000040, 0xc0004924, 0xca0000f8, 0xc2c00002, 0x6afd6000, 0x7ec16000, 0x762d0000, 0xce0000f8,\n 0xa4820070, 0xc2400000, 0xc000140e, 0xca408018, 0xc2000002, 0xc0004900, 0xce000000, 0xc000490a,\n 0xce4000f8, 0xc1000000, 0xd90000f9, 0xd8400078, 0xc1000004, 0xd90000f9, 0xa4840270, 0x00000000,\n 0xc3c00000, 0xc000140e, 0xcbc10018, 0xc2800000, 0xc2000000, 0x6ff8a000, 0x6fd44000, 0x4795c000,\n 0x47bdc000, 0x5bb85e00, 0x5838002e, 0xca800078, 0x58380006, 0xca020078, 0xc3400000, 0x5838002e,\n 0xcb420078, 0x5aa80002, 0x46a10000, 0x84000010, 0xc2800000, 0x5838002e, 0xc6900078, 0xcd000078,\n 0x5f740002, 0x5838002e, 0xc7501078, 0xcd021078, 0xc0004968, 0xca4000f8, 0xc2000002, 0x6a3d0000,\n 0x72612000, 0xce4000f8, 0xc000492a, 0xca8000f8, 0x5e740000, 0x84000040, 0xc0004910, 0xca0000f8,\n 0xc2c00002, 0x6afd6000, 0x7ec16000, 0x762d0000, 0xce0000f8, 0x6abd4010, 0xa68000ba, 0x00000000,\n 0x58380032, 0xca0000f8, 0x58000002, 0xca4000f8, 0x5838000c, 0x00000000, 0xce0000f9, 0xce4000f8,\n 0xc000492a, 0xca0000f8, 0xc2c00002, 0x6afd6000, 0x722d0000, 0xce0000f8, 0xc000492c, 0xca0000f8,\n 0xc2c00002, 0x6afd6000, 0x722d0000, 0xce0000f8, 0x80000040, 0xc000492c, 0xca0000f8, 0xc2c00002,\n 0x6afd6000, 0x7ec16000, 0x762d0000, 0xce0000f8, 0xa4880148, 0xc2c00000, 0xc000140e, 0xcac20018,\n 0xc000490e, 0xca4000f8, 0xc2000002, 0x6a2d0000, 0x7e010000, 0x76612000, 0xce4000f8, 0xc000496a,\n 0xca4000f8, 0xc2000002, 0x6a2d0000, 0x72612000, 0xce4000f8, 0x6ef0a000, 0x6ed44000, 0x47158000,\n 0x472d8000, 0x5b305e00, 0x58300000, 0xca0000f8, 0x00000000, 0xc2400002, 0x76612000, 0x84000072,\n 0x58300000, 0xca4000f8, 0xc2800000, 0x00000000, 0xc6684018, 0xc24c0002, 0xc6a40018, 0xc624c400,\n 0x58300010, 0xca400500, 0x00000000, 0xc0001800, 0xce4000f8, 0xa4860070, 0xc2400000, 0xc000140e,\n 0xca418018, 0xc2020002, 0xc0004900, 0xce002100, 0xc0004908, 0xce4000f8, 0xc1000000, 0xd90000f9,\n 0xd8400078, 0xc1000004, 0xd90000f9, 0xa48c00e8, 0xc2400000, 0xc000140e, 0xca430018, 0x00000000,\n 0x00000000, 0x5d240002, 0x84000058, 0xc00048c4, 0xca0000f8, 0xc00048c6, 0xc1040002, 0x72110000,\n 0xce0000f8, 0xc1000002, 0xc00048cc, 0xcd000000, 0x80000060, 0x5d240004, 0x84000050, 0xc00048c8,\n 0xca0000f8, 0xc00048ca, 0xc1160002, 0x72110000, 0xce0000f8, 0xc1020002, 0xc00048cc, 0xcd002100,\n 0xc0001408, 0xcc8000f8, 0xc10e0002, 0xd90c00f8, 0x8000ecc8, 0xdfbc00f9, 0xc000496e, 0x990066c8,\n 0xc94000f8, 0xc7d800f8, 0x00000000, 0xc57000f8, 0x5ef00020, 0x88000148, 0x6f346000, 0x4771a000,\n 0x5b744c80, 0x58340008, 0xc2400000, 0xca400078, 0x00000000, 0xc2000000, 0x5a640002, 0xce400078,\n 0x58340004, 0xca000078, 0x00000000, 0x00000000, 0x5e200002, 0xce000078, 0xc0004912, 0xca8000f8,\n 0xc2400002, 0x6a712000, 0x72a54000, 0xce8000f8, 0x5e200000, 0x84000052, 0xc000480a, 0xca0000f8,\n 0xc0000408, 0xca8000f8, 0x76250000, 0x00000000, 0x72a14000, 0xce8000f8, 0x80000038, 0xc0004914,\n 0xca0000f8, 0x7e412000, 0x00000000, 0x76250000, 0xce0000f8, 0x800000d0, 0x6ef4a000, 0x6ed44000,\n 0x4755a000, 0x476da000, 0x5b745e00, 0x5834002e, 0xc2400000, 0xca420078, 0x00000000, 0xc2000000,\n 0x5a640002, 0xc6501078, 0xcd021078, 0x58340006, 0xca000078, 0x00000000, 0x00000000, 0x5a200002,\n 0xce000078, 0xc0004910, 0xca4000f8, 0xc2000002, 0x6a2d0000, 0x72612000, 0xce4000f8, 0xc2000002,\n 0x6a310000, 0xc000042a, 0xce0000f8, 0xc1040002, 0xd90c00f8, 0x00000000, 0x8000ea38, 0x00000000,\n 0xc4980928, 0x9d000000, 0xc5580028, 0xc0000838, 0xcd8400f8, 0xc1440200, 0xc1c01600, 0xc55c1070,\n 0xc000100e, 0x9d000000, 0xcd8000f8, 0xc000100c, 0xcdc000f8, 0xc0004862, 0xc9c000f8, 0x00000000,\n 0x00000000, 0xd9d800f9, 0xc0005600, 0x401c0000, 0x5dc05800, 0x88000012, 0x5c000200, 0xcd8000f8,\n 0xc1f0000a, 0x715ca000, 0xdd9800f8, 0xdd9c00f9, 0x41d8e000, 0xc5d40260, 0xc0001010, 0xcd4000f8,\n 0x6c9c8000, 0x45c8e000, 0x45c8e000, 0x59dc0004, 0xc1601260, 0xc5d40260, 0x9d000000, 0xc0001012,\n 0xcd4000f8, 0x00000000, 0x00000000, 0xd95800f8, 0x6d586000, 0x4594c000, 0x59984c80, 0xd99800f9,\n 0x5818000a, 0xc1800000, 0xc9800078, 0xc0005400, 0x6d5ca000, 0x401c0000, 0x40180000, 0xc94000f8,\n 0x58000002, 0x00000000, 0xc9c000f8, 0xc0004930, 0xcd4000f8, 0xc0004932, 0xcdc000f8, 0x59980004,\n 0xc1c20020, 0xb59c0018, 0x00000000, 0xc1800000, 0xdd9c00f9, 0x581c000a, 0xcd800078, 0x581c000c,\n 0xc1800000, 0xc9800020, 0xc1c00002, 0xdd9400f8, 0x69d4e000, 0x5d980002, 0xcd800020, 0xc0004924,\n 0xc98000f8, 0x00000000, 0x9d000000, 0x00000000, 0x719cc000, 0xcd8000f8, 0xc000492a, 0xc94000f8,\n 0xc1c00002, 0x69d8e000, 0x7dc0c000, 0x7558a000, 0xcd4000f8, 0xc000492c, 0xc94000f8, 0xdd8000f9,\n 0x58000032, 0x755ca000, 0x84000090, 0xc94000f9, 0xc98000f8, 0xdd8000f9, 0x5800000c, 0x00000000,\n 0xcd4000f9, 0xcd8000f8, 0xc000492c, 0xc94000f8, 0xc000492a, 0xc98000f8, 0x715ca000, 0xc000492c,\n 0xcd4000f8, 0x719cc000, 0xc000492a, 0xcd8000f8, 0x9d000000, 0x00000000, 0x00000000, 0x00000000,\n 0xc0004862, 0xc98000f8, 0x00000000, 0xc1c00200, 0x4194c000, 0x459ce000, 0x88000012, 0xc5d800f8,\n 0xc0004862, 0xcd8000f8, 0xc0001406, 0xc98000f8, 0xc1c00002, 0x9d000000, 0xc5d80a00, 0xc5581048,\n 0xcd8000f8, 0xc0004930, 0xc98000f8, 0xc0004932, 0xc9c000f8, 0xc140000e, 0xc5581c18, 0xdd9400f8,\n 0xc0005600, 0x40140000, 0x5d405800, 0x88000012, 0x5c000200, 0xcd8000f8, 0x58000002, 0x5d405800,\n 0x88000012, 0x5c000200, 0xcdc000f8, 0xdd5400f8, 0xc1c00000, 0x58140006, 0xc9c20078, 0xc1800000,\n 0x58140000, 0xc98000d8, 0x6ddc2000, 0xc000491e, 0x41d8e000, 0xcdc000f8, 0xdd9800f8, 0xc1c00022,\n 0xc5d80d70, 0xdd9400f9, 0xc5581c18, 0xc000491c, 0xcd8000f8, 0xdd5400f8, 0xc1c00000, 0x58140006,\n 0xc9c20078, 0xc1800000, 0x58140004, 0xc9820078, 0x00000000, 0x59dc0002, 0x45d8c000, 0x84000010,\n 0xc1c00000, 0x9d000000, 0x58140006, 0xc5d81078, 0xcd821078, 0xc0004860, 0xc94000f8, 0xc1820080,\n 0xc1d00002, 0x58146b00, 0xd58000f8, 0x58000002, 0xd58000f9, 0x59540004, 0xb5580018, 0xc0004860,\n 0xc1400000, 0xcd4000f8, 0xdd9800f9, 0x9d000000, 0xdd9400f8, 0xc0001404, 0xcdc10800, 0xc1c00000,\n 0xc1800200, 0x5d980004, 0xdf5d0048, 0x459ca000, 0x8800fff2, 0xdd8000f9, 0x5800000c, 0x00000000,\n 0xc94000f9, 0xc98000f8, 0xc1c00002, 0xc5d43f00, 0xc5d81e00, 0xc0004862, 0xc9c000f8, 0x00000000,\n 0x00000000, 0x581c5600, 0x5dc05800, 0x88000012, 0x5c000200, 0xcd4000f8, 0x58000002, 0x5dc05800,\n 0x88000012, 0x5c000200, 0xcd8000f8, 0xc0004862, 0xc9c000f8, 0x00000000, 0xc15004c0, 0xc5d40060,\n 0xdd9c00f8, 0xc5d41c18, 0xc1c00000, 0xdd8000f9, 0x58000030, 0xc9c00078, 0xdd8000f9, 0x58000002,\n 0xc98000f8, 0x6ddc2000, 0xc000491c, 0x41d8e000, 0xcd4000f9, 0xcdc000f8, 0xdd9400f9, 0xc1c00000,\n 0x58140030, 0xc9c00078, 0xc1800000, 0x58140006, 0xc9820078, 0x00000000, 0x59dc0002, 0x45d8c000,\n 0x84000010, 0xc1c00000, 0x9d000000, 0x58140030, 0xc5d80078, 0xcd800078, 0xc1c00000, 0xdf5c0038,\n 0x5ddc0080, 0x8400ffea, 0x00000000, 0x9d000000, 0x00000000, 0x00000000, 0x00000000, 0xc160fffe,\n 0xc0000a10, 0xc9440060, 0xc1a0fffe, 0x59981e08, 0xc000100c, 0xcd4000f8, 0xc000100e, 0xcd8000f8,\n 0xc0004964, 0xc98000f8, 0x00000000, 0xc170000a, 0x7158a000, 0x6c988000, 0x4588c000, 0x4588c000,\n 0x59980004, 0xc5940270, 0xc0001010, 0xcd4000f8, 0xc0004946, 0xc94000f8, 0x00000000, 0x00000000,\n 0x6d58a000, 0x6d5c4000, 0x459cc000, 0x4594c000, 0xc000494a, 0xc94000f8, 0xc0004948, 0xc9c000f8,\n 0x4194c000, 0xc1400012, 0xc55c1818, 0x9d000000, 0xc59c0268, 0xc0001012, 0xcdc000f8, 0xc1400000,\n 0x58000012, 0xc9410038, 0xc0004950, 0xc9c000f8, 0xc55800f8, 0xc5940838, 0xc5581078, 0xd99400f8,\n 0xc000493c, 0xc94000f8, 0xc0004954, 0xc98000f8, 0x59dc00a8, 0x45d4e000, 0x41d8e000, 0x5d5c0030,\n 0x88000010, 0xc1c00030, 0xc1800000, 0xc5d84028, 0xc1400000, 0xc5d40008, 0x5dd40002, 0x84000072,\n 0x5dd40004, 0x8400009a, 0x5dd40006, 0x840000c2, 0x5dd80026, 0x840000ea, 0xdd5400f8, 0xdd8000f9,\n 0x58000008, 0x40180000, 0xcd4000f8, 0x59980002, 0x8000ffc0, 0xdd5400f8, 0xdd8000f9, 0x58000008,\n 0x40180000, 0xcd4000b8, 0x59980002, 0x8000ff88, 0xdd5400f8, 0xdd8000f9, 0x58000008, 0x40180000,\n 0xcd400078, 0x59980002, 0x8000ff50, 0xdd5400f8, 0xdd8000f9, 0x58000008, 0x40180000, 0xcd400038,\n 0x59980002, 0x8000ff18, 0x00000000, 0x9d000000, 0x00000000, 0x00000000, 0x00000000, 0x58000012,\n 0xc94000f8, 0xc0004954, 0xc9c000f8, 0xc0004950, 0xc9400078, 0xdd8000f9, 0x58000028, 0x5d9c0000,\n 0x84000052, 0x5d9c0002, 0x84000052, 0x5d9c0004, 0x8400006a, 0xc55b0038, 0xc55c08b8, 0xcd800039,\n 0xcdc108b8, 0x80000060, 0xcd4000f8, 0x80000050, 0xc55900b8, 0xc55c1838, 0xcd8000b9, 0xcdc31838,\n 0x80000028, 0xc55a0078, 0xc55c1078, 0xcd800079, 0xcdc21078, 0x9d000000, 0x00000000, 0x00000000,\n 0x00000000, 0x59540002, 0x6994e018, 0x61c0c008, 0x4194a000, 0x5d940040, 0x88000012, 0xc59400f8,\n 0x9d000000, 0xcd4000f8, 0x00000000, 0x00000000, 0x9d000000, 0x4158a000, 0xcd4000f8, 0x00000000,\n};\n\nstatic unsigned int firmware_binary_data[] = {\n};\n\n\n#endif  //  IFXMIPS_ATM_FW_AMAZON_SE_H\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-atm/src/ifxmips_atm_fw_ar9.h",
    "content": "#ifndef IFXMIPS_ATM_FW_AR9_H\n#define IFXMIPS_ATM_FW_AR9_H\n\n\n/******************************************************************************\n**\n** FILE NAME    : ifxmips_atm_fw_ar9.h\n** PROJECT      : UEIP\n** MODULES     \t: ATM (ADSL)\n**\n** DATE         : 22 OCT 2007\n** AUTHOR       : Xu Liang\n** DESCRIPTION  : ATM Driver (PP32 Firmware)\n** COPYRIGHT    : \tCopyright (c) 2006\n**\t\t\tInfineon Technologies AG\n**\t\t\tAm Campeon 1-12, 85579 Neubiberg, Germany\n**\n**    This program is free software; you can redistribute it and/or modify\n**    it under the terms of the GNU General Public License as published by\n**    the Free Software Foundation; either version 2 of the License, or\n**    (at your option) any later version.\n**\n** HISTORY\n** $Date        $Author         $Comment\n** 22 OCT 2007  Xu Liang        Initiate Version, v00.01\n*******************************************************************************/\n\n\n#define VER_IN_FIRMWARE         1\n\n#define ATM_FW_VER_MAJOR        0\n#define ATM_FW_VER_MINOR        16\n\n\nstatic unsigned int ar9_fw_bin[] = {\n 0x800004b8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x8000ffe0, 0x00000000, 0x00000000, 0x00000000,\n 0xc1000002, 0xd90c00f8, 0xc2000002, 0xda0800f9, 0x80004980, 0xc2000000, 0xda0800f9, 0x80003fe8,\n 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n 0x80003fa0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n 0x80005178, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n 0x80003ea0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n 0xc0400000, 0xc0004840, 0xc88400f8, 0x80004640, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n 0xc0400002, 0xc0004840, 0xc88400f8, 0x800045c0, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n 0xc3c00004, 0xdbc800f9, 0xc10c0002, 0xd90c00f8, 0x8000fee0, 0x00000000, 0x00000000, 0x00000000,\n 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n 0xc10e0002, 0xd90c00f8, 0xc0004808, 0xc84000f8, 0x800045f0, 0x00000000, 0x00000000, 0x00000000,\n 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n 0xc3e1fffe, 0x597dfffe, 0x593dfe14, 0x900004d9, 0x00000000, 0x00000000, 0x00000000, 0x90cc0481,\n 0x00000000, 0x00000000, 0x00000000, 0xc3c00000, 0xdbc800f9, 0xc1400008, 0xc1900000, 0x71588000,\n 0x14100100, 0xc140000a, 0xc1900002, 0x71588000, 0x14100100, 0xc140000c, 0xc1900004, 0x71588000,\n 0x14100100, 0xc1400004, 0xc1900006, 0x71588000, 0x14100100, 0xc1400006, 0xc1900008, 0x71588000,\n 0x14100100, 0xc140000e, 0xc190000a, 0x71588000, 0x14100100, 0xc1400000, 0xc190000c, 0x71588000,\n 0x14100100, 0xc1400002, 0xc190000e, 0x71588000, 0x14100100, 0xc0400000, 0xc11c0000, 0xc000082c,\n 0xcd05ce00, 0xc11c0002, 0xc000082c, 0xcd05ce00, 0xc0400002, 0xc11c0000, 0xc000082c, 0xcd05ce00,\n 0xc11c0002, 0xc000082c, 0xcd05ce00, 0xc0000824, 0x00000000, 0xcbc000f9, 0xcb8000f9, 0xcb4000f9,\n 0xcb0000f8, 0xc0004878, 0x5bfc4000, 0xcfc000f9, 0x5bb84000, 0xcf8000f9, 0x5b744000, 0xcf4000f9,\n 0x5b304000, 0xcf0000f8, 0xc0000a10, 0x00000000, 0xcbc000f9, 0xcb8000f8, 0xc0004874, 0x5bfc4000,\n 0xcfc000f9, 0x5bb84000, 0xcf8000f8, 0xc30001fe, 0xc000140a, 0xcf0000f8, 0xc3000000, 0x7f018000,\n 0xc000042e, 0xcf0000f8, 0xc000040e, 0xcf0000f8, 0xc3c1fffe, 0xc000490e, 0xcfc00078, 0xc000492c,\n 0xcfc00078, 0xc0004924, 0xcfc00038, 0xc0004912, 0xcfc00038, 0xc0004966, 0xcfc00038, 0xc0004968,\n 0xcfc00078, 0xc000496a, 0xcfc00078, 0xc3c1fffe, 0xc00049a0, 0xcfc000f8, 0xc3c00000, 0xc2800020,\n 0xc3000000, 0x7f018000, 0x6ff88000, 0x6fd44000, 0x4395c000, 0x5bb84a00, 0x5838000a, 0xcf0000f8,\n 0x5bfc0002, 0xb7e8ffc8, 0x00000000, 0xc3c00000, 0xc2800010, 0x6ff86000, 0x47bdc000, 0x5bb84c80,\n 0xc3400000, 0x58380004, 0xcb420078, 0x00000000, 0x58380008, 0xcf400078, 0x5bfc0002, 0xb7e8ffb0,\n 0x00000000, 0xc3c00000, 0xc2800020, 0xc348001e, 0xc3000000, 0x7f018000, 0x6ff8a000, 0x6fd44000,\n 0x4795c000, 0x47bdc000, 0x5bb87000, 0x58380008, 0xcf408418, 0x5838000a, 0xcf0000f8, 0x5bfc0002,\n 0xb7e8ffb0, 0x00000000, 0x00000000, 0xc3e0a242, 0x5bfc0020, 0xc0004002, 0xcfc000f8, 0x00000000,\n 0xc121fffe, 0x5911fe14, 0x14100000, 0x80000530, 0x00000000, 0x80002130, 0x00000000, 0x8000ffe0,\n 0xc0004958, 0xc84000f8, 0x00000000, 0xc3c00002, 0x787c2000, 0xcc4000f8, 0xc0004848, 0xcb8400f8,\n 0xc000495c, 0xcac400f8, 0xc0004844, 0xc88400f8, 0x47ad0000, 0x8400ff82, 0xc000487c, 0xc80400f8,\n 0x00000000, 0x00000000, 0x40080000, 0xca0000f8, 0xc0001624, 0xcb0400f8, 0xa63c007a, 0x00000000,\n 0x00000000, 0xa71eff22, 0x00000000, 0xc0000824, 0xca8400f8, 0x6ca08000, 0x6ca42000, 0x46250000,\n 0x42290000, 0xc35e0002, 0xc6340060, 0xc0001624, 0xcf440078, 0xc2000000, 0xc161fffe, 0x5955fffe,\n 0x14140000, 0x00000000, 0xc0004844, 0xc88400f8, 0xc000082c, 0xca040038, 0x00000000, 0x00000000,\n 0x58880002, 0xb6080018, 0x00000000, 0xc0800000, 0xc0004844, 0xcc840038, 0x5aec0002, 0xc000495c,\n 0xcec400f8, 0x5e6c0006, 0x84000060, 0xc0004848, 0xcb8400f8, 0xc0000838, 0xc2500002, 0xce450800,\n 0x5fb80002, 0xc0004848, 0xcf8400f8, 0x5eec0002, 0xc000495c, 0xcec400f8, 0x00000000, 0xc121fffe,\n 0x5911fe14, 0x14100000, 0x8000fd98, 0xc000495a, 0xc84000f8, 0x00000000, 0xc3c00002, 0x787c2000,\n 0xcc4000f8, 0xc0004960, 0xcac400f8, 0x00000000, 0x00000000, 0x5eec0000, 0x8400010a, 0x00000000,\n 0xb6fc0050, 0xc0001600, 0xca0400f8, 0x00000000, 0x00000000, 0xa61e00d2, 0x6fe90000, 0xc0000a28,\n 0xce850800, 0xc2c00000, 0xc2800004, 0xb6e800a0, 0xc0001604, 0xca8400f8, 0xc0004960, 0xcec400f8,\n 0xa69efcc2, 0x00000000, 0x6fe90000, 0xc0000a28, 0xce850800, 0xc2c00002, 0xc0001600, 0xca0400f8,\n 0x00000000, 0x00000000, 0xa61e002a, 0x6fe90000, 0xc0000a28, 0xce850800, 0xc2c00000, 0xc0001604,\n 0xca8400f8, 0xc0004960, 0xcec400f8, 0xa69efc2a, 0xc2400000, 0xc0000a14, 0xca440028, 0x00000000,\n 0x00000000, 0x466d2000, 0xa4400020, 0xc2800000, 0xdfeb0029, 0x80000010, 0xdfea0029, 0xb668fba2,\n 0x00000000, 0xc00048a0, 0xcb0400f8, 0xc0000a10, 0xca8400f8, 0x6f208000, 0x6f242000, 0x46250000,\n 0x42a10000, 0xc2400000, 0xc0000a14, 0xca440028, 0xc35e0002, 0xc6340060, 0xc0001604, 0xcf440078,\n 0x5b300002, 0xb6700018, 0x5aec0002, 0xc3000000, 0xc00048a0, 0xcf0400f8, 0xc0004960, 0xcec400f8,\n 0x8000fad8, 0xc0004918, 0xd28000f8, 0xc2000000, 0xdf600038, 0x5e600080, 0x84000272, 0x00000000,\n 0xc161fffe, 0x5955fffe, 0x14140000, 0x00000000, 0xc000480a, 0xca0000f8, 0xc0004912, 0xca4000f8,\n 0xc0004924, 0xca8000f8, 0xc0004966, 0xcac000f8, 0x00000000, 0xc121fffe, 0x5911fe14, 0x14100000,\n 0x76250000, 0x76290000, 0x762d0000, 0x840001ca, 0xc0004918, 0xca4000f8, 0xc28001fe, 0x76290000,\n 0x5a640002, 0x6a254010, 0x5ee80000, 0x8400001a, 0x6aa54000, 0x80000010, 0xc62800f8, 0x62818008,\n 0xc0004918, 0xcf0000f8, 0xc161fffe, 0x5955fffe, 0x14140000, 0x00000000, 0xc0004966, 0xca4000f8,\n 0xc2000002, 0x6a310000, 0x7e010000, 0x76612000, 0xce4000f8, 0x00000000, 0xc121fffe, 0x5911fe14,\n 0x14100000, 0x6f346000, 0x4771a000, 0x5b744c80, 0xc2800000, 0x58340006, 0xca800078, 0xc2c00000,\n 0x58340000, 0xcac000d8, 0xc2400000, 0x5834000a, 0xca420078, 0x6ea82000, 0x42e9e000, 0x6f2ca000,\n 0x42e56000, 0x5aec2e00, 0xc3990040, 0xc7381c18, 0xc6f80060, 0x99005b78, 0xdb9800f8, 0xdbd800f9,\n 0x00000000, 0xdea000f8, 0x46310000, 0x8400fd80, 0xc0004958, 0xc84000f8, 0x00000000, 0xc3c00002,\n 0x787c2000, 0xcc4000f8, 0xc0004848, 0xcb8400f8, 0xc0004844, 0xc88400f8, 0x5fb80000, 0x8400f7f2,\n 0xc0001a1c, 0xca0000f8, 0xc2400002, 0x6a452000, 0x76250000, 0x8400f7c2, 0xc000487c, 0xc80400f8,\n 0x00000000, 0x00000000, 0x40080000, 0xca0000f8, 0xc42400f8, 0x00000000, 0xa63c17da, 0x00000000,\n 0xc0004878, 0xc80400f8, 0x6c908000, 0x45088000, 0x45088000, 0x40100000, 0xca0000f8, 0xc42400f8,\n 0x00000000, 0xc0004934, 0xce0000f8, 0xc2800002, 0xc4681c08, 0xc62821d0, 0xc2600010, 0x5a650060,\n 0xc0004800, 0xcb4000f8, 0xc2200400, 0x5a200020, 0xc7601040, 0xc0001220, 0xce8000f8, 0xc0001200,\n 0xce4000f8, 0xc0001202, 0xce0000f8, 0xc0001240, 0xcb4000f8, 0x00000000, 0x00000000, 0xa754ffe0,\n 0xc2000000, 0xc7600040, 0xa7520042, 0x00000000, 0x00000000, 0x990062f0, 0xc0004822, 0xc94000f8,\n 0xc1800002, 0x80001680, 0x582040a0, 0xc2000000, 0xca000018, 0xc2400000, 0xca414000, 0xc2800000,\n 0xca812000, 0xc2c00000, 0xcac20018, 0xc0004938, 0xce0000f8, 0xc0004920, 0xce4000f8, 0xc0004916,\n 0xce8000f8, 0xc0004922, 0xcec000f8, 0xa6400540, 0x00000000, 0xc0004938, 0xcbc000f8, 0x00000000,\n 0xc3800000, 0x6ff48000, 0x6fd44000, 0x4355a000, 0x5b744a00, 0x58340000, 0xcb802010, 0x00000000,\n 0xc2000000, 0x6fb46000, 0x4779a000, 0x5b744c80, 0x5834000c, 0xca000020, 0xc000491a, 0xcf8000f8,\n 0x5e200000, 0x8400046a, 0xc2000000, 0xdf610048, 0x5e6001e8, 0x8800ffe8, 0xc2000002, 0xc2400466,\n 0xc2a00000, 0x5aa80000, 0xc0001006, 0xce0000f8, 0xc0001008, 0xce4000f8, 0xc000100a, 0xce8000f8,\n 0x990055b8, 0xc1a0fffe, 0xc0000824, 0xc9840060, 0xc0004934, 0xca4000f8, 0xc2000000, 0xc2800002,\n 0x990055f8, 0xda9800f8, 0xc61400f8, 0xc65800f8, 0xc161fffe, 0x5955fffe, 0x14140000, 0x00000000,\n 0x990056e0, 0xc000491a, 0xc94000f8, 0x00000000, 0x00000000, 0xc121fffe, 0x5911fe14, 0x14100000,\n 0xc0004922, 0xca001118, 0xc3c00000, 0xc3800000, 0xc0004930, 0xce023118, 0xc0004932, 0xcbc000d8,\n 0xc2800000, 0xc000491e, 0xcfc000f8, 0xc0004862, 0xca800060, 0xc3a0001a, 0x5bb94000, 0xc6b80060,\n 0xc000491c, 0xcf8000f8, 0x99005950, 0xc000491c, 0xc1400000, 0xc9420048, 0x00000000, 0x00000000,\n 0x00000000, 0xa8e2ffe8, 0xc2000000, 0xc1220002, 0xd90c00f8, 0xdf600038, 0x5e600080, 0x8400fff2,\n 0xc000491c, 0xca0000f8, 0xc000491e, 0xca4000f8, 0x00000000, 0x00000000, 0x99005b78, 0xda1800f8,\n 0xda5800f9, 0x00000000, 0xc2000000, 0xdf610048, 0x5e6001fe, 0x8800ffe8, 0xc0004916, 0xca8000f8,\n 0xc2c00000, 0xdfec0048, 0xc2400000, 0x466d2000, 0x8400004a, 0x5ea80000, 0x8400003a, 0xc2600002,\n 0x990062f0, 0xc000482e, 0xc94000f8, 0xc1800002, 0x80000030, 0xc2600000, 0x990062f0, 0xc000482c,\n 0xc94000f8, 0xc1800002, 0xc2000068, 0xc6240078, 0xc0004930, 0xce400080, 0xc000491a, 0xc98000f8,\n 0xc0004862, 0xc94000f8, 0x6d9c6000, 0x45d8e000, 0x59dc4c80, 0x990059d8, 0xd95800f8, 0xd99800f9,\n 0xd9d400f8, 0x99005950, 0xc000491c, 0xc1400000, 0xc9420048, 0xc2000000, 0xdf600038, 0x5e600080,\n 0x8400ffea, 0x00000000, 0xc000491c, 0xca0000f8, 0xc000491e, 0xca4000f8, 0x00000000, 0x00000000,\n 0x99005b78, 0xda1800f8, 0xda5800f9, 0x00000000, 0x800010e8, 0x00000000, 0x990062f0, 0xc000482a,\n 0xc94000f8, 0xc1800002, 0x800010b8, 0xc0004938, 0xcbc000f8, 0x00000000, 0x00000000, 0x6ff88000,\n 0x6fd44000, 0x4395c000, 0x5bb84a00, 0x58380008, 0xca0000f8, 0x00000000, 0x00000000, 0xa6000382,\n 0x00000000, 0xc0004938, 0xcbc000f8, 0xc3000000, 0x00000000, 0x6ff88000, 0x6fd44000, 0x4395c000,\n 0x5bb84a00, 0x58380000, 0xcb002010, 0xc2000000, 0x58380008, 0xca020078, 0x5838000c, 0xcac000f8,\n 0x5838000e, 0xca4000f8, 0xc000491a, 0xcf0000f8, 0xc0004930, 0xcec000f8, 0xc000493c, 0xce0000f8,\n 0xc0004932, 0xce4000f8, 0x5e200000, 0x84000120, 0xc2800000, 0xa6fe00ba, 0x6f206000, 0x46310000,\n 0x5a204c80, 0x5820000c, 0xca800020, 0x00000000, 0x00000000, 0x5ea80000, 0x840001f2, 0x00000000,\n 0xc161fffe, 0x5955fffe, 0x14140000, 0x00000000, 0x990056e0, 0xc000491a, 0xc94000f8, 0x00000000,\n 0x00000000, 0xc121fffe, 0x5911fe14, 0x14100000, 0xc0004930, 0xcac000f8, 0xc0004932, 0xca4000f8,\n 0xc7ec1118, 0xc0004930, 0xcec000f8, 0x5838000c, 0xcec000f8, 0x58000002, 0xce4000f8, 0xc0004934,\n 0xca0000f8, 0xc2400002, 0x6e642000, 0x6e642000, 0x76612000, 0x8400002a, 0xc2400002, 0x6e684000,\n 0x58380008, 0xce804200, 0xa6000020, 0x6e682000, 0x58380008, 0xce802100, 0xc2400002, 0x6e642000,\n 0x76612000, 0x840000ea, 0x58380008, 0xca0000f8, 0xc2800000, 0xc2400000, 0xa60200c0, 0xdba800f8,\n 0x6f386000, 0x47b1c000, 0x5bb84c80, 0x58380004, 0xca400078, 0x58380002, 0xca800078, 0x00000000,\n 0xdeb800f8, 0x46a54000, 0x88000060, 0x00000000, 0xc0004824, 0xca0000f8, 0xc2400002, 0x6e640000,\n 0x5a200002, 0xce0000f8, 0x58380008, 0xce400000, 0x80000018, 0x00000000, 0x80000048, 0xc0004934,\n 0xca0000f8, 0x00000000, 0x00000000, 0xa6020c6a, 0x00000000, 0x00000000, 0x80000c98, 0xc2800000,\n 0xc2000200, 0xc240001a, 0xdf690048, 0x46294000, 0x46a54000, 0x8800ffd2, 0xc2000006, 0xc2600982,\n 0x5a643b6e, 0x5838000a, 0xca8000f8, 0xc0001006, 0xce0000f8, 0xc0001008, 0xce4000f8, 0xc000100a,\n 0xce8000f8, 0x990055b8, 0xc1a0fffe, 0xc0000824, 0xc9840060, 0xc2000000, 0xc0004930, 0xca02e008,\n 0x58380026, 0xca4000f8, 0x00000000, 0xc2800000, 0x990055f8, 0xda9800f8, 0xc61400f8, 0xc65800f8,\n 0xc0004934, 0xca0000f8, 0x00000000, 0x00000000, 0xa6020022, 0x00000000, 0x00000000, 0x80000318,\n 0xc0004938, 0xcbc000f8, 0xc0004878, 0xc80400f8, 0x6c908000, 0x45088000, 0x45088000, 0x40100000,\n 0xca0000f8, 0xc42400f8, 0x00000000, 0x58240018, 0xca0000f8, 0x6ff88000, 0x6fd44000, 0x4395c000,\n 0x5bb84a00, 0xc3000000, 0xc3400002, 0xc2c00000, 0xc62c0078, 0xc6270038, 0xc0004940, 0xce400038,\n 0xc6260038, 0xc0004942, 0xce400038, 0xc000493c, 0xca0000f8, 0x5eec0000, 0x8400018a, 0x5a6c0010,\n 0x46254000, 0x88000190, 0x5a600052, 0x46e54000, 0x88000178, 0x58380006, 0xca8000f8, 0xc0004940,\n 0xca0000f8, 0xc2400000, 0xc6a70038, 0x7e412000, 0x76612000, 0xc2000000, 0xc6a10038, 0x46250000,\n 0x84000138, 0xc0004942, 0xca0000f8, 0xc2400000, 0xc6a60038, 0x7e412000, 0x76612000, 0xc2000000,\n 0xc6a00038, 0x58380002, 0xca8000f8, 0x46250000, 0x840000e8, 0xc2400000, 0xc6a60078, 0x466d0000,\n 0x880000da, 0xc2400000, 0xc6a40078, 0x58380008, 0xca8000f8, 0x46e50000, 0x880000ba, 0x00000000,\n 0xa6820018, 0x00000000, 0xc7700b00, 0xa6840098, 0x00000000, 0xc7700a00, 0x80000080, 0xc7700200,\n 0xc000493c, 0xcac000f8, 0x80000060, 0xc7700300, 0xc000493c, 0xcac000f8, 0x80000040, 0xc7700900,\n 0x80000030, 0xc7700800, 0x80000020, 0xc7700700, 0x80000010, 0xc7700500, 0xc0004944, 0xcf0000f8,\n 0xc000493e, 0xcec000f8, 0xc0004938, 0xca4000f8, 0xc000493c, 0xcb8000f8, 0xc000493e, 0xcb4000f8,\n 0xc3000000, 0x6e608000, 0x6e544000, 0x42150000, 0x5a204a00, 0x5aa00008, 0x58200004, 0xcb000078,\n 0xc0004934, 0xca0000f8, 0xc2400000, 0xc0004930, 0xca42e008, 0xc3c00018, 0xa6020098, 0x00000000,\n 0x43656000, 0x47ad0000, 0x88000050, 0x46f96000, 0x6ee04010, 0x5be00004, 0xc2000000, 0xc6e00008,\n 0x5e200000, 0x84000042, 0x5bfc0002, 0x80000030, 0xc3c00004, 0x5a2c0008, 0x47a10000, 0x88000012,\n 0x5fb80008, 0x6fe04000, 0x42390000, 0x47212000, 0x88000068, 0xc2400000, 0xc0004930, 0xca42e008,\n 0xc2060002, 0xc68000f8, 0xce006300, 0x6fe04000, 0x4721c000, 0x5f700010, 0x4765a000, 0xc2000000,\n 0xc6340008, 0xc25a000a, 0xc000491a, 0xca401c18, 0xc2800000, 0xc0004932, 0xca8000d8, 0xc0004862,\n 0xca400060, 0x6fa04010, 0x42290000, 0xc000491e, 0xce0000f8, 0xc7e41048, 0xc000491c, 0xce4000f8,\n 0x6fe04000, 0x43a1c000, 0xc000493c, 0xcf8000f8, 0xc000493e, 0xcf4000f8, 0xc000493a, 0xcfc000f8,\n 0x80000008, 0x00000000, 0x00000000, 0x00000000, 0xc2000000, 0xdce000f8, 0xa622ffd8, 0xc1220002,\n 0xd90c00f8, 0xc0004938, 0xcbc000f8, 0xc0004944, 0xcb4000f8, 0xc0004862, 0xcb0000f8, 0xc0004934,\n 0xca0000f8, 0x6ff88000, 0x6fd44000, 0x4395c000, 0x5bb84a00, 0xa6020268, 0xc2400000, 0x58380008,\n 0xca406000, 0xdfe800f8, 0xc2218e08, 0x5a21baf6, 0x46a14000, 0x84000022, 0xc2080002, 0x7361a000,\n 0x80000058, 0x5e640000, 0x84000022, 0xc20c0002, 0x7361a000, 0x80000030, 0xc2000000, 0xc760e710,\n 0xc7604218, 0x5e200000, 0x84000272, 0xc2200002, 0xc0004930, 0xce021000, 0x990062f0, 0xc0004828,\n 0xc94000f8, 0xc1800002, 0x58380000, 0xca0000f8, 0x00000000, 0x00000000, 0xa6000132, 0xc0004940,\n 0xca8000f8, 0xc0004942, 0xca4000f8, 0xc7600078, 0xc6a01838, 0xc6601038, 0xc000493a, 0xca4000f8,\n 0xc0004934, 0xca8000f8, 0xc0007800, 0x40300000, 0x40240000, 0x5c000004, 0x5ec07a00, 0x88000012,\n 0x5c000200, 0xce0000f8, 0x58000002, 0x5ec07a00, 0x88000012, 0x5c000200, 0xce8000f8, 0xc000493e,\n 0xca0000f8, 0xc2400000, 0x5838000c, 0xce4000f8, 0x990062f0, 0xc0004830, 0xc94000f8, 0xc61800f8,\n 0xc0004930, 0xc6100078, 0xcd000078, 0x800000a8, 0xc2400002, 0x58380008, 0xce400000, 0xc0004944,\n 0xcf4000f8, 0x80000278, 0xc000493c, 0xca4000f8, 0xdfe800f8, 0x5a300018, 0xc0007800, 0x40200000,\n 0xca0000f8, 0x58380008, 0xc6501078, 0xcd021078, 0x5838000a, 0xce8000f8, 0x58380026, 0xce0000f8,\n 0xc0004944, 0xcf4000f8, 0x99005950, 0xc000491c, 0xc1400000, 0xc9420048, 0x80000038, 0x00000000,\n 0x990062f0, 0xc0004826, 0xc94000f8, 0xc1800002, 0x8000fdd8, 0xc2000000, 0xc2400080, 0xdf600038,\n 0xb624ffea, 0xc000491c, 0xca4000f8, 0xc000491e, 0xca8000f8, 0x99005b78, 0xda5800f8, 0xda9800f9,\n 0x00000000, 0xc0004934, 0xca0000f8, 0x00000000, 0xc2800000, 0xa6020160, 0xc2400004, 0xc2000200,\n 0xdf690048, 0x46294000, 0x46a54000, 0x8800ffda, 0x00000000, 0xc000491a, 0xc98000f8, 0xc0004862,\n 0xc94000f8, 0x6d9c6000, 0x45d8e000, 0x59dc4c80, 0x990059d8, 0xd95800f8, 0xd99800f9, 0xd9d400f8,\n 0x99005950, 0xc000491c, 0xc1400000, 0xc9420048, 0xc2000000, 0xc2400080, 0xdf600038, 0xb624ffea,\n 0xc000491c, 0xca4000f8, 0xc000491e, 0xca8000f8, 0x99005b78, 0xda5800f8, 0xda9800f9, 0x00000000,\n 0x58380008, 0xca4000f8, 0xc2000000, 0xce000018, 0xc2a1fffe, 0x5aa9fffe, 0xce021078, 0x5838000a,\n 0xce8000f8, 0xc161fffe, 0x5955fffe, 0x14140000, 0x00000000, 0xc0000838, 0xc2500002, 0xce450800,\n 0xc0004848, 0xcb8400f8, 0xc2000000, 0xc000082c, 0xca040028, 0x5fb80002, 0xc0004848, 0xcf8400f8,\n 0x58880002, 0xb6080018, 0x00000000, 0xc0800000, 0xc0004844, 0xcc8400f8, 0x00000000, 0xc121fffe,\n 0x5911fe14, 0x14100000, 0x8000ded8, 0xc2000000, 0xdf600038, 0x5e200080, 0x8400026a, 0x00000000,\n 0xc161fffe, 0x5955fffe, 0x14140000, 0x00000000, 0xc000480c, 0xca0000f8, 0xc0004910, 0xca4000f8,\n 0xc000492c, 0xca8000f8, 0xc0004968, 0xcac000f8, 0x00000000, 0xc121fffe, 0x5911fe14, 0x14100000,\n 0x76250000, 0x76290000, 0x76e16000, 0x840001c2, 0xc0004926, 0xca4000f8, 0xc201fffe, 0x76e16000,\n 0x5a640002, 0x6ae50010, 0x5f200000, 0x8400001a, 0x6a250000, 0x80000010, 0xc6e000f8, 0x62014008,\n 0xc0004926, 0xce8000f8, 0xc161fffe, 0x5955fffe, 0x14140000, 0x00000000, 0xc0004968, 0xca4000f8,\n 0xc2000002, 0x6a290000, 0x7e010000, 0x76612000, 0xce4000f8, 0x00000000, 0xc121fffe, 0x5911fe14,\n 0x14100000, 0x6eb4a000, 0x6e944000, 0x4755a000, 0x4769a000, 0x5b747000, 0x58340002, 0xc2000000,\n 0xca0000d8, 0x5834002e, 0xc2400000, 0xca400078, 0x6eb0a000, 0x6ebc4000, 0x473d8000, 0x47298000,\n 0x5b30302e, 0x5b300004, 0x6e642000, 0x4225e000, 0xc39a8024, 0xc7380060, 0xc6b81c18, 0x99005b78,\n 0xdb9800f8, 0xdbd800f9, 0x00000000, 0xc2000000, 0xdf600038, 0x5e200080, 0x84000352, 0x00000000,\n 0xc161fffe, 0x5955fffe, 0x14140000, 0x00000000, 0xc000490e, 0xca0000f8, 0xc00049a0, 0xca8000f8,\n 0xc000492a, 0xca4000f8, 0xc000496a, 0xcb0000f8, 0xc0004956, 0xcac000f8, 0x00000000, 0xc121fffe,\n 0x5911fe14, 0x14100000, 0x77218000, 0x77258000, 0x77298000, 0x8400029a, 0xc201fffe, 0x77218000,\n 0x5aec0002, 0x6b2d0010, 0x5ea00000, 0x8400001a, 0x6a2d0000, 0x80000010, 0xc72000f8, 0x62016008,\n 0xc0004956, 0xcec000f8, 0x6ef4a000, 0x6ed44000, 0x4755a000, 0x476da000, 0x5b747000, 0x58340000,\n 0xc9c000f8, 0xc00049a0, 0xca0000f8, 0xc3000000, 0xc5f04018, 0xc2400000, 0xc5e50038, 0x7e412000,\n 0x76250000, 0xce0000f8, 0xc0004980, 0x40300000, 0xcec000f8, 0xc161fffe, 0x5955fffe, 0x14140000,\n 0x00000000, 0xc000496a, 0xca4000f8, 0xc2000002, 0x6a2d0000, 0x7e010000, 0x76612000, 0xce4000f8,\n 0x00000000, 0xc121fffe, 0x5911fe14, 0x14100000, 0x6ef4a000, 0x6ed44000, 0x4755a000, 0x476da000,\n 0x5b747000, 0x5834000e, 0xc2000000, 0xca0000d8, 0x58340008, 0xc2400000, 0xca420078, 0x5834000c,\n 0xc2800000, 0xca832010, 0x6e644010, 0x42250000, 0x4229e000, 0xc39a8008, 0x58340008, 0xcb809018,\n 0x58340008, 0xc2800000, 0xca810010, 0x6ee0a000, 0x6ee44000, 0x46250000, 0x462d0000, 0x5a200008,\n 0x5a203008, 0x42290000, 0xc6380060, 0xc6f81c18, 0x99005b78, 0xdb9800f8, 0xdbd800f9, 0x00000000,\n 0xc000495a, 0xc84000f8, 0x00000000, 0xc3c00002, 0x787c2000, 0xcc4000f8, 0xc0001a1c, 0xca0000f8,\n 0xc2400008, 0x6a452000, 0x76250000, 0x84000ec2, 0xc0000a28, 0xc3800000, 0xcb840028, 0xc0000a14,\n 0xc3400000, 0xcb440028, 0xc0004880, 0xcb0400f8, 0xb7b40072, 0x58041802, 0xcac000f8, 0xa7000078,\n 0x00000000, 0x00000000, 0xa6c8d808, 0xc1000000, 0xc6d00018, 0xc0004980, 0x40100000, 0xca8000f8,\n 0x80000070, 0x00000000, 0x00000000, 0x00000000, 0x8000d7b8, 0x00000000, 0xc2800000, 0xc7282018,\n 0xc000490e, 0xca4000f8, 0x6be9e000, 0x00000000, 0x767d2000, 0x8400d770, 0x6ea0a000, 0x6e944000,\n 0x46150000, 0x46290000, 0x5a207000, 0x5820000c, 0xca0000f8, 0xc0004946, 0xce8000f8, 0xa62203a8,\n 0x00000000, 0xc2200060, 0xc0004948, 0xce000008, 0xce021038, 0xc240000a, 0xc000494a, 0xce4000f8,\n 0xc2b60002, 0xc0004964, 0xce837b00, 0x99005e48, 0xc00048a0, 0xc88400f8, 0x00000000, 0xc0004946,\n 0xcbc000f8, 0x00000000, 0x00000000, 0x6ff8a000, 0x6fd44000, 0x4795c000, 0x47bdc000, 0x5bb87000,\n 0x99005c08, 0xdbd800f8, 0xdb9800f9, 0x00000000, 0x99005950, 0xc000491c, 0xc1400000, 0xc9420048,\n 0xc000491c, 0x99005e00, 0xc94000f9, 0xc98000f8, 0x00000000, 0x99005b78, 0xd95800f8, 0xd99800f9,\n 0x00000000, 0xc161fffe, 0x5955fffe, 0x14140000, 0x00000000, 0x99005840, 0xdbd800f8, 0xdb9800f9,\n 0xc7d800f8, 0x00000000, 0xc121fffe, 0x5911fe14, 0x14100000, 0x6ff8a000, 0x6fd44000, 0x4795c000,\n 0x47bdc000, 0x5bb87000, 0x58380010, 0xca0000f8, 0xc0004874, 0xc80400f8, 0x6c908000, 0x45088000,\n 0x45088000, 0x40100000, 0xca4000f8, 0xc43400f8, 0x00000000, 0xc74000f8, 0xce0000f8, 0xc161fffe,\n 0x5955fffe, 0x14140000, 0x00000000, 0xc000490e, 0xca4000f8, 0xc2800002, 0x6abd4000, 0x72692000,\n 0xce4000f8, 0x00000000, 0xc121fffe, 0x5911fe14, 0x14100000, 0x990062f0, 0xc0004836, 0xc94000f8,\n 0xc1800002, 0x00000000, 0x00000000, 0x00000000, 0xa8e2ffe8, 0x00000000, 0x58380000, 0xc90000f8,\n 0xc00049a0, 0xca0000f8, 0xc2800000, 0xc5290038, 0x72290000, 0xce0000f8, 0xc1220002, 0xd90c00f8,\n 0xc2000000, 0xc0000a14, 0xca040028, 0xc0000a28, 0xc2500002, 0xce450800, 0x58880002, 0xb6080018,\n 0xc00048a0, 0xc0800000, 0xcc8400f8, 0x8000d380, 0xc0004946, 0xcbc000f8, 0xc161fffe, 0x5955fffe,\n 0x14140000, 0x00000000, 0xc000490e, 0xca4000f8, 0xc2800002, 0x6abd4000, 0x72692000, 0xce4000f8,\n 0x00000000, 0xc121fffe, 0x5911fe14, 0x14100000, 0x6ff8a000, 0x6fd44000, 0x4795c000, 0x47bdc000,\n 0x5bb87000, 0x58380008, 0xca0000f8, 0x5838000c, 0xca4000f8, 0xc3400000, 0xc6340000, 0xc000494e,\n 0xcf4000f8, 0xc2800000, 0xc62a0078, 0xc3000000, 0xc6308018, 0x6f304000, 0x43298000, 0xc000493c,\n 0xcf0000f8, 0xc2c00000, 0xc66c0078, 0xc0004950, 0xcec000f8, 0xc2800000, 0xc66ae020, 0xc0004954,\n 0xce8000f8, 0x5f740000, 0x840001a0, 0x5e300028, 0x46e12000, 0x8400016a, 0x46e12000, 0x88000132,\n 0x5e300018, 0x46e12000, 0x8800002a, 0x46e12000, 0x84000042, 0x00000000, 0x800000c0, 0x00000000,\n 0x99005f88, 0xdbd800f8, 0xdb9800f9, 0xc78000f8, 0xc3400002, 0xc000494e, 0xcf4000f8, 0xc161fffe,\n 0x5955fffe, 0x14140000, 0x00000000, 0xc000490e, 0xca4000f8, 0xc2800002, 0x6abd4000, 0x7e814000,\n 0x76692000, 0xce4000f8, 0x00000000, 0xc121fffe, 0x5911fe14, 0x14100000, 0xc2200060, 0xc0004948,\n 0xce021038, 0xc2000000, 0xc000494c, 0xce0000f8, 0x80000080, 0x00000000, 0x99005f88, 0xdbd800f8,\n 0xdb9800f9, 0xc78000f8, 0x99006188, 0xdbd800f8, 0xdb9800f9, 0xc78000f8, 0xc2200058, 0xc0004948,\n 0xce021038, 0xc2000002, 0xc000494c, 0xce0000f8, 0xc2000006, 0xc0001006, 0xce0000f8, 0x5838000a,\n 0xca4000f8, 0xc2200982, 0x5a203b6e, 0xc0001008, 0xce0000f8, 0xc000100a, 0xce4000f8, 0xc0004954,\n 0xca8000f8, 0xc200000c, 0xc000494a, 0xce0000f8, 0xc0004948, 0xce800008, 0xc2b60000, 0xc0004964,\n 0xce8000f8, 0x99005e48, 0xc00048a0, 0xc88400f8, 0x00000000, 0xc0004946, 0xcbc000f8, 0xc000494c,\n 0xca0000f8, 0x6ff8a000, 0x6fd44000, 0x4795c000, 0x47bdc000, 0x5bb87000, 0x5e200000, 0x840000fa,\n 0x00000000, 0x99005c08, 0xdbd800f8, 0xdb9800f9, 0x00000000, 0x99005950, 0xc000491c, 0xc1400000,\n 0xc9420048, 0xc000491c, 0x99005e00, 0xc94000f9, 0xc98000f8, 0x00000000, 0x99005b78, 0xd95800f8,\n 0xd99800f9, 0x00000000, 0xc161fffe, 0x5955fffe, 0x14140000, 0x00000000, 0x99005840, 0xdbd800f8,\n 0xdb9800f9, 0xc7d800f8, 0x00000000, 0xc121fffe, 0x5911fe14, 0x14100000, 0xc000493c, 0xca8000f8,\n 0xc000494e, 0xcac000f8, 0xc3000018, 0xc3400006, 0x5e200000, 0x8400002a, 0xc2800000, 0xc2c00000,\n 0xc300001e, 0xc3400000, 0xc6ac1078, 0xc72c0418, 0xc76c0810, 0x58380010, 0xca8000f8, 0x58380008,\n 0xcec000f8, 0xc6280100, 0xc0004874, 0xc80400f8, 0x6c908000, 0x45088000, 0x45088000, 0x40100000,\n 0xcb0000f8, 0xc43400f8, 0x00000000, 0xc74000f8, 0xce8000f8, 0xc0004952, 0xce8000f8, 0x00000000,\n 0x00000000, 0x00000000, 0xa8e2ffe8, 0x00000000, 0xc000494c, 0xca0000f8, 0xc0004950, 0xcac000f8,\n 0x5e200000, 0x8400006a, 0xdfe800f8, 0x7e814000, 0x5834001a, 0xce8000f8, 0x990062f0, 0xc0004834,\n 0xc94000f8, 0xc1800002, 0x990062f0, 0xc0004838, 0xc94000f8, 0xc6d800f8, 0xc1220002, 0xd90c00f8,\n 0x5e200000, 0x84000040, 0x5838002c, 0xcb0000f8, 0xdfe800f8, 0x00000000, 0x58380014, 0xcf0000f8,\n 0x80000058, 0xc2a1fffe, 0x5aa9fffe, 0x58380000, 0xc90000f8, 0xc00049a0, 0xcb0000f8, 0xc2c00000,\n 0xc52d0038, 0x732d8000, 0xcf0000f8, 0x5838000a, 0xce8000f8, 0xc3000000, 0xc0000a14, 0xcb040028,\n 0xc2d00002, 0xc0000a28, 0xcec50800, 0xc000494e, 0xca8000f8, 0x58880002, 0xb4b00018, 0xc00048a0,\n 0xc0800000, 0xcc8400f8, 0x5ea80000, 0x8400017a, 0x5e200000, 0x84000168, 0xc000493c, 0xca8000f8,\n 0x00000000, 0x00000000, 0x5aa80060, 0xce8000f8, 0x99005f88, 0xdbd800f8, 0xdb9800f9, 0xc78000f8,\n 0x99006188, 0xdbd800f8, 0xdb9800f9, 0xc78000f8, 0x58380000, 0xcac000f8, 0x00000000, 0xc2000000,\n 0xc6e04018, 0xc0004952, 0xcac000f8, 0x58380000, 0xca8000f8, 0xc30c0002, 0xc6300018, 0xa6800098,\n 0x00000000, 0x00000000, 0xc161fffe, 0x5955fffe, 0x14140000, 0x00000000, 0xc0001800, 0xca0000f8,\n 0x00000000, 0x00000000, 0xa60cffea, 0xc6f00500, 0xc6b0c400, 0xcf0000f8, 0x00000000, 0xc121fffe,\n 0x5911fe14, 0x14100000, 0x8000c9c8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x8000c960,\n 0xdcbc00f9, 0x5ffc0000, 0x84000052, 0xc3800002, 0xdb8800f9, 0x5ffc0004, 0x8400c292, 0xc3800000,\n 0xdb8800f9, 0xc3ce0002, 0xc0000800, 0xcfc0e700, 0xc3e1fffe, 0x597dfffe, 0x593dfe14, 0x94000001,\n 0x00000000, 0x00000000, 0x00000000, 0xc000487c, 0xc80400f8, 0x00000000, 0x00000000, 0x40080000,\n 0xcbc000f8, 0xc43800f8, 0x00000000, 0xc000480e, 0xca0000f8, 0xc0004858, 0xcb4400f8, 0x00000000,\n 0x00000000, 0x47610000, 0x880000b0, 0x00000000, 0xa7c00048, 0xc0004854, 0xc1000002, 0xcd0400f8,\n 0xc11c0000, 0xc000082c, 0xcd05ce00, 0x800000d8, 0x00000000, 0xa7d20138, 0x00000000, 0xc7e14040,\n 0xc2400000, 0xc6246028, 0xc200006a, 0x46250000, 0xc6240030, 0xc0000810, 0xce440030, 0x8000ff70,\n 0xc2000000, 0xc0000808, 0xca040010, 0xc11c0000, 0xc000082c, 0xcd05ce00, 0x5a200002, 0x5e600010,\n 0x84000010, 0xc2000000, 0xc0000808, 0xce040010, 0xc3400000, 0x80000028, 0xc1200002, 0xc0000818,\n 0xcd061000, 0x5b740002, 0xc0004858, 0xcf4400f8, 0x99005590, 0xc0004848, 0xc94400f8, 0xc1800000,\n 0xc11c0002, 0xc000082c, 0xcd05ce00, 0x80000600, 0x5b740002, 0xc0004858, 0xcf4400f8, 0xc78000f8,\n 0xc13c0002, 0xcd03de00, 0xc0004848, 0xc94400f8, 0xc1800000, 0xc000082c, 0xc9840028, 0x59540002,\n 0xc0004848, 0xcd4400f8, 0x58880002, 0xb4980580, 0x00000000, 0xc0800000, 0x80000568, 0xc000487c,\n 0xc80400f8, 0x00000000, 0x00000000, 0x40080000, 0xcbc000f8, 0xc42800f8, 0x00000000, 0xa7c00130,\n 0xc000484c, 0xca0400f8, 0xc2400000, 0xc0001aec, 0xca440018, 0x5a200002, 0xc000484c, 0xce0400f8,\n 0xb624008a, 0xc68000f8, 0xc13c0002, 0xcd03de00, 0xc0004848, 0xc94400f8, 0xc1800000, 0xc000082c,\n 0xc9840028, 0x59540002, 0xc0004848, 0xcd4400f8, 0x58880002, 0xb4980470, 0x00000000, 0xc0800000,\n 0x80000458, 0xc0004854, 0xc1000004, 0xcd0400f8, 0xc0000820, 0xc2000002, 0xce0400f8, 0xc2000000,\n 0xc000484c, 0xce0400f8, 0xc0004858, 0xce0400f8, 0x8000ff28, 0xc0004854, 0xc1000000, 0xcd0400f8,\n 0xc11c0000, 0xc000082c, 0xcd05ce00, 0x99005590, 0xc0004848, 0xc94400f8, 0xc1800000, 0xc1200000,\n 0xc0000818, 0xcd061000, 0xc11c0002, 0xc000082c, 0xcd05ce00, 0xc2000000, 0xc000484c, 0xce0400f8,\n 0x80000358, 0xc0001ac0, 0xcb8400f8, 0xc000487c, 0xc80400f8, 0x00000000, 0x00000000, 0x40080000,\n 0xcbc000f8, 0xc42800f8, 0x00000000, 0x00000000, 0xc68000f8, 0xc13c0000, 0xcd03de00, 0xa780024a,\n 0x00000000, 0x00000000, 0xa7c0020a, 0x00000000, 0xc0001b00, 0xc2060006, 0xce046308, 0xa7e801c2,\n 0x00000000, 0xc0004850, 0xca0400f8, 0xc2400000, 0xc0001aec, 0xca448018, 0x5a200002, 0xc0004850,\n 0xce0400f8, 0xb62400aa, 0x00000000, 0xc68000f8, 0xc13c0002, 0xcd03de00, 0xc0001acc, 0xc2000002,\n 0xce040000, 0xc0004848, 0xc94400f8, 0xc1800000, 0xc000082c, 0xc9840028, 0x59540002, 0xc0004848,\n 0xcd4400f8, 0x58880002, 0xb49801c8, 0x00000000, 0xc0800000, 0x800001b0, 0xc0004854, 0xc1000000,\n 0xcd0400f8, 0xc11c0000, 0xc000082c, 0xcd05ce00, 0x99005590, 0xc0004848, 0xc94400f8, 0xc1800000,\n 0xc2000000, 0xc0000820, 0xce0400f8, 0xc1200000, 0xc0000818, 0xcd061000, 0xc11c0002, 0xc000082c,\n 0xcd05ce00, 0xc0004850, 0xce0400f8, 0xc2000002, 0xc0001acc, 0xce040008, 0x800000e8, 0xc2000002,\n 0xc0004850, 0xce0400f8, 0x8000fe88, 0xc2000000, 0xc0004850, 0xce0400f8, 0xa7e60032, 0x00000000,\n 0xc2000002, 0xc0001b00, 0xce040000, 0x8000fe70, 0x00000000, 0xa7860052, 0x00000000, 0xc68000f8,\n 0xc13c0002, 0xcd03de00, 0xc2020002, 0xc7e2a540, 0xc0001b00, 0xce0400f8, 0x8000fe18, 0xc2040002,\n 0xc0001b00, 0xce044200, 0x8000fdf8, 0xc2c80002, 0x6ac56000, 0xdacc00f8, 0xc0004854, 0xcb4400f8,\n 0xc0004848, 0xcb8400f8, 0xc0000838, 0xc3c00000, 0xcbc40028, 0x5ef40004, 0x84000022, 0xc3000000,\n 0xc0001acc, 0xcf042100, 0x47f98000, 0x8400002a, 0x47f98000, 0x88000030, 0xc1006e8c, 0x8000b6c8,\n 0xc0004840, 0xcc8400f8, 0x8000f6b0, 0xc0001ac0, 0xcac400f8, 0xc0004854, 0xcb4400f8, 0xa6c0fbd2,\n 0x00000000, 0x5ef40000, 0x8400f70a, 0x5ef40002, 0x8400f99a, 0x5ef40004, 0x8400fb9a, 0xc1006ce8,\n 0x8000b640, 0x00000000, 0xc0800000, 0xdf4b0038, 0xc0004900, 0xcb8000f8, 0xc2000000, 0xc000490a,\n 0xa78000d0, 0xcbc000f8, 0xc1000000, 0xd90000f9, 0xc1000002, 0xd90c00f8, 0x6ff46000, 0x477da000,\n 0x5b744c80, 0xc2400000, 0x58340004, 0xca400078, 0xc0004900, 0xce000000, 0x5a640002, 0x58340004,\n 0xc6500078, 0xcd000078, 0xc0004914, 0xca4000f8, 0xc2000002, 0x6a3d0000, 0x72612000, 0xce4000f8,\n 0xc0000408, 0xce0000f8, 0xa78200d8, 0xc0004908, 0xcbc000f8, 0xc1000000, 0xd90000f9, 0xc1000002,\n 0xd90c00f8, 0x6ff4a000, 0x6fd44000, 0x4755a000, 0x477da000, 0x5b747000, 0xc2800000, 0x58340006,\n 0xca800078, 0xc2000000, 0xc0004900, 0xce002100, 0x5ea80002, 0x58340006, 0xc6900078, 0xcd000078,\n 0x5a7c0020, 0xc2000002, 0x6a250000, 0xc0000408, 0xce0000f8, 0xdca800f9, 0x5ea80000, 0x8400b4b0,\n 0x00000000, 0xa4800230, 0x00000000, 0xc3c00000, 0xc000140e, 0xcbc00018, 0xc3400000, 0xc2400000,\n 0x6ff86000, 0x47bdc000, 0x5bb84c80, 0x58380008, 0xcb400078, 0x58380006, 0xca400078, 0x5f740002,\n 0x58380008, 0xc7500078, 0xcd000078, 0xc2000000, 0x58380004, 0xca020078, 0xc3000000, 0x5838000c,\n 0xcb000020, 0x5a640002, 0x46610000, 0x84000010, 0xc2400000, 0x58380006, 0xc6500078, 0xcd000078,\n 0xc2000000, 0x5838000a, 0xca020078, 0x5b300002, 0x5838000c, 0xc7100020, 0xcd000020, 0xc2420020,\n 0x5a200004, 0x46252000, 0x84000010, 0xc2000000, 0x5838000a, 0xc6101078, 0xcd021078, 0xc0004966,\n 0xca4000f8, 0xc2000002, 0x6a3d0000, 0x72612000, 0xce4000f8, 0x5f740000, 0x84000040, 0xc0004912,\n 0xca0000f8, 0xc2c00002, 0x6afd6000, 0x7ec16000, 0x762d0000, 0xce0000f8, 0x5f300020, 0x84000040,\n 0xc0004924, 0xca0000f8, 0xc2c00002, 0x6afd6000, 0x7ec16000, 0x762d0000, 0xce0000f8, 0xa4820070,\n 0xc2400000, 0xc000140e, 0xca408018, 0xc2000002, 0xc0004900, 0xce000000, 0xc000490a, 0xce4000f8,\n 0xc1000000, 0xd90000f9, 0xd8400078, 0xc1000004, 0xd90000f9, 0xa4840270, 0x00000000, 0xc3c00000,\n 0xc000140e, 0xcbc10018, 0xc2800000, 0xc2000000, 0x6ff8a000, 0x6fd44000, 0x4795c000, 0x47bdc000,\n 0x5bb87000, 0x5838002e, 0xca800078, 0x58380006, 0xca020078, 0xc3400000, 0x5838002e, 0xcb420078,\n 0x5aa80002, 0x46a10000, 0x84000010, 0xc2800000, 0x5838002e, 0xc6900078, 0xcd000078, 0x5f740002,\n 0x5838002e, 0xc7501078, 0xcd021078, 0xc0004968, 0xca4000f8, 0xc2000002, 0x6a3d0000, 0x72612000,\n 0xce4000f8, 0xc000492a, 0xca8000f8, 0x5e740000, 0x84000040, 0xc0004910, 0xca0000f8, 0xc2c00002,\n 0x6afd6000, 0x7ec16000, 0x762d0000, 0xce0000f8, 0x6abd4010, 0xa68000ba, 0x00000000, 0x58380032,\n 0xca0000f8, 0x58000002, 0xca4000f8, 0x5838000c, 0x00000000, 0xce0000f9, 0xce4000f8, 0xc000492a,\n 0xca0000f8, 0xc2c00002, 0x6afd6000, 0x722d0000, 0xce0000f8, 0xc000492c, 0xca0000f8, 0xc2c00002,\n 0x6afd6000, 0x722d0000, 0xce0000f8, 0x80000040, 0xc000492c, 0xca0000f8, 0xc2c00002, 0x6afd6000,\n 0x7ec16000, 0x762d0000, 0xce0000f8, 0xa4880148, 0xc2c00000, 0xc000140e, 0xcac20018, 0xc000490e,\n 0xca4000f8, 0xc2000002, 0x6a2d0000, 0x7e010000, 0x76612000, 0xce4000f8, 0xc000496a, 0xca4000f8,\n 0xc2000002, 0x6a2d0000, 0x72612000, 0xce4000f8, 0x6ef0a000, 0x6ed44000, 0x47158000, 0x472d8000,\n 0x5b307000, 0x58300000, 0xca0000f8, 0x00000000, 0xc2400002, 0x76612000, 0x84000072, 0x58300000,\n 0xca4000f8, 0xc2800000, 0x00000000, 0xc6684018, 0xc24c0002, 0xc6a40018, 0xc624c400, 0x58300010,\n 0xca400500, 0x00000000, 0xc0001800, 0xce4000f8, 0xa4860070, 0xc2400000, 0xc000140e, 0xca418018,\n 0xc2020002, 0xc0004900, 0xce002100, 0xc0004908, 0xce4000f8, 0xc1000000, 0xd90000f9, 0xd8400078,\n 0xc1000004, 0xd90000f9, 0xc0001408, 0xcc8000f8, 0xc10e0002, 0xd90c00f8, 0x8000edb0, 0xdfbc00f9,\n 0xc000496e, 0x99006298, 0xc94000f8, 0xc7d800f8, 0x00000000, 0xc57000f8, 0x5ef00020, 0x88000148,\n 0x6f346000, 0x4771a000, 0x5b744c80, 0x58340008, 0xc2400000, 0xca400078, 0x00000000, 0xc2000000,\n 0x5a640002, 0xce400078, 0x58340004, 0xca000078, 0x00000000, 0x00000000, 0x5e200002, 0xce000078,\n 0xc0004912, 0xca8000f8, 0xc2400002, 0x6a712000, 0x72a54000, 0xce8000f8, 0x5e200000, 0x84000052,\n 0xc000480a, 0xca0000f8, 0xc0000408, 0xca8000f8, 0x76250000, 0x00000000, 0x72a14000, 0xce8000f8,\n 0x80000038, 0xc0004914, 0xca0000f8, 0x7e412000, 0x00000000, 0x76250000, 0xce0000f8, 0x800000d0,\n 0x6ef4a000, 0x6ed44000, 0x4755a000, 0x476da000, 0x5b747000, 0x5834002e, 0xc2400000, 0xca420078,\n 0x00000000, 0xc2000000, 0x5a640002, 0xc6501078, 0xcd021078, 0x58340006, 0xca000078, 0x00000000,\n 0x00000000, 0x5a200002, 0xce000078, 0xc0004910, 0xca4000f8, 0xc2000002, 0x6a2d0000, 0x72612000,\n 0xce4000f8, 0xc2000002, 0x6a310000, 0xc000042a, 0xce0000f8, 0xc1040002, 0xd90c00f8, 0x00000000,\n 0x8000eb20, 0x00000000, 0xc4980928, 0x9d000000, 0xc5580028, 0xc0000838, 0xcd8400f8, 0xc1440200,\n 0xc1c03800, 0xc55c1070, 0xc000100e, 0x9d000000, 0xcd8000f8, 0xc000100c, 0xcdc000f8, 0xc0004862,\n 0xc9c000f8, 0x00000000, 0x00000000, 0xd9d800f9, 0xc0007800, 0x401c0000, 0x5dc07a00, 0x88000012,\n 0x5c000200, 0xcd8000f8, 0xc1f0000a, 0x715ca000, 0xdd9800f8, 0xdd9c00f9, 0x41d8e000, 0xc5d40260,\n 0xc0001010, 0xcd4000f8, 0x6c9c8000, 0x45c8e000, 0x45c8e000, 0x59dc0004, 0xc1601260, 0xc5d40260,\n 0x9d000000, 0xc0001012, 0xcd4000f8, 0x00000000, 0x00000000, 0xd95800f8, 0x6d586000, 0x4594c000,\n 0x59984c80, 0xd99800f9, 0x5818000a, 0xc1800000, 0xc9800078, 0xc0006e00, 0x6d5ca000, 0x401c0000,\n 0x40180000, 0xc94000f8, 0x58000002, 0x00000000, 0xc9c000f8, 0xc0004930, 0xcd4000f8, 0xc0004932,\n 0xcdc000f8, 0x59980004, 0xc1c20020, 0xb59c0018, 0x00000000, 0xc1800000, 0xdd9c00f9, 0x581c000a,\n 0xcd800078, 0x581c000c, 0xc1800000, 0xc9800020, 0xc1c00002, 0xdd9400f8, 0x69d4e000, 0x5d980002,\n 0xcd800020, 0xc0004924, 0xc98000f8, 0x00000000, 0x9d000000, 0x00000000, 0x719cc000, 0xcd8000f8,\n 0xc000492a, 0xc94000f8, 0xc1c00002, 0x69d8e000, 0x7dc0c000, 0x7558a000, 0xcd4000f8, 0xc000492c,\n 0xc94000f8, 0xdd8000f9, 0x58000032, 0x755ca000, 0x84000090, 0xc94000f9, 0xc98000f8, 0xdd8000f9,\n 0x5800000c, 0x00000000, 0xcd4000f9, 0xcd8000f8, 0xc000492c, 0xc94000f8, 0xc000492a, 0xc98000f8,\n 0x715ca000, 0xc000492c, 0xcd4000f8, 0x719cc000, 0xc000492a, 0xcd8000f8, 0x9d000000, 0x00000000,\n 0x00000000, 0x00000000, 0xc0004862, 0xc98000f8, 0x00000000, 0xc1c00200, 0x4194c000, 0x459ce000,\n 0x88000012, 0xc5d800f8, 0xc0004862, 0xcd8000f8, 0xc0001406, 0xc98000f8, 0xc1c00002, 0x9d000000,\n 0xc5d80a00, 0xc5581048, 0xcd8000f8, 0xc0004930, 0xc98000f8, 0xc0004932, 0xc9c000f8, 0xc140000e,\n 0xc5581c18, 0xdd9400f8, 0xc0007800, 0x40140000, 0x5d407a00, 0x88000012, 0x5c000200, 0xcd8000f8,\n 0x58000002, 0x5d407a00, 0x88000012, 0x5c000200, 0xcdc000f8, 0xdd5400f8, 0xc1c00000, 0x58140006,\n 0xc9c20078, 0xc1800000, 0x58140000, 0xc98000d8, 0x6ddc2000, 0xc000491e, 0x41d8e000, 0xcdc000f8,\n 0xdd9800f8, 0xc1c00022, 0xc5d80d70, 0xdd9400f9, 0xc5581c18, 0xc000491c, 0xcd8000f8, 0xdd5400f8,\n 0xc1c00000, 0x58140006, 0xc9c20078, 0xc1800000, 0x58140004, 0xc9820078, 0x00000000, 0x59dc0002,\n 0x45d8c000, 0x84000010, 0xc1c00000, 0x9d000000, 0x58140006, 0xc5d81078, 0xcd821078, 0xc0004860,\n 0xc94000f8, 0xc1820080, 0xc1d00002, 0x58147700, 0xd58000f8, 0x58000002, 0xd58000f9, 0x59540004,\n 0xb5580018, 0xc0004860, 0xc1400000, 0xcd4000f8, 0xdd9800f9, 0x9d000000, 0xdd9400f8, 0xc0001404,\n 0xcdc10800, 0xc1c00000, 0xc1800200, 0x5d980004, 0xdf5d0048, 0x459ca000, 0x8800fff2, 0xdd8000f9,\n 0x5800000c, 0x00000000, 0xc94000f9, 0xc98000f8, 0xc1c00002, 0xc5d43f00, 0xc5d81e00, 0xc0004862,\n 0xc9c000f8, 0x00000000, 0x00000000, 0x581c7800, 0x5dc07a00, 0x88000012, 0x5c000200, 0xcd4000f8,\n 0x58000002, 0x5dc07a00, 0x88000012, 0x5c000200, 0xcd8000f8, 0xc0004862, 0xc9c000f8, 0x00000000,\n 0xc15004c0, 0xc5d40060, 0xdd9c00f8, 0xc5d41c18, 0xc1c00000, 0xdd8000f9, 0x58000030, 0xc9c00078,\n 0xdd8000f9, 0x58000002, 0xc98000f8, 0x6ddc2000, 0xc000491c, 0x41d8e000, 0xcd4000f9, 0xcdc000f8,\n 0xdd9400f9, 0xc1c00000, 0x58140030, 0xc9c00078, 0xc1800000, 0x58140006, 0xc9820078, 0x00000000,\n 0x59dc0002, 0x45d8c000, 0x84000010, 0xc1c00000, 0x9d000000, 0x58140030, 0xc5d80078, 0xcd800078,\n 0xc1c00000, 0xdf5c0038, 0x5ddc0080, 0x8400ffea, 0x00000000, 0x9d000000, 0x00000000, 0x00000000,\n 0x00000000, 0xc160fffe, 0xc0000a10, 0xc9440060, 0xc1a0fffe, 0x59983008, 0xc000100c, 0xcd4000f8,\n 0xc000100e, 0xcd8000f8, 0xc0004964, 0xc98000f8, 0x00000000, 0xc170000a, 0x7158a000, 0x6c988000,\n 0x4588c000, 0x4588c000, 0x59980004, 0xc5940270, 0xc0001010, 0xcd4000f8, 0xc0004946, 0xc94000f8,\n 0x00000000, 0x00000000, 0x6d58a000, 0x6d5c4000, 0x459cc000, 0x4594c000, 0xc000494a, 0xc94000f8,\n 0xc0004948, 0xc9c000f8, 0x4194c000, 0xc1400012, 0xc55c1818, 0x9d000000, 0xc59c0268, 0xc0001012,\n 0xcdc000f8, 0xc1400000, 0x58000012, 0xc9410038, 0xc0004950, 0xc9c000f8, 0xc55800f8, 0xc5940838,\n 0xc5581078, 0xd99400f8, 0xc000493c, 0xc94000f8, 0xc0004954, 0xc98000f8, 0x59dc00a8, 0x45d4e000,\n 0x41d8e000, 0x5d5c0030, 0x88000010, 0xc1c00030, 0xc1800000, 0xc5d84028, 0xc1400000, 0xc5d40008,\n 0x5dd40002, 0x84000072, 0x5dd40004, 0x8400009a, 0x5dd40006, 0x840000c2, 0x5dd80026, 0x840000ea,\n 0xdd5400f8, 0xdd8000f9, 0x58000008, 0x40180000, 0xcd4000f8, 0x59980002, 0x8000ffc0, 0xdd5400f8,\n 0xdd8000f9, 0x58000008, 0x40180000, 0xcd4000b8, 0x59980002, 0x8000ff88, 0xdd5400f8, 0xdd8000f9,\n 0x58000008, 0x40180000, 0xcd400078, 0x59980002, 0x8000ff50, 0xdd5400f8, 0xdd8000f9, 0x58000008,\n 0x40180000, 0xcd400038, 0x59980002, 0x8000ff18, 0x00000000, 0x9d000000, 0x00000000, 0x00000000,\n 0x00000000, 0x58000012, 0xc94000f8, 0xc0004954, 0xc9c000f8, 0xc0004950, 0xc9400078, 0xdd8000f9,\n 0x58000028, 0x5d9c0000, 0x84000052, 0x5d9c0002, 0x84000052, 0x5d9c0004, 0x8400006a, 0xc55b0038,\n 0xc55c08b8, 0xcd800039, 0xcdc108b8, 0x80000060, 0xcd4000f8, 0x80000050, 0xc55900b8, 0xc55c1838,\n 0xcd8000b9, 0xcdc31838, 0x80000028, 0xc55a0078, 0xc55c1078, 0xcd800079, 0xcdc21078, 0x9d000000,\n 0x00000000, 0x00000000, 0x00000000, 0x59540002, 0x6994e018, 0x61c0c008, 0x4194a000, 0x5d940040,\n 0x88000012, 0xc59400f8, 0x9d000000, 0xcd4000f8, 0x00000000, 0x00000000, 0x9d000000, 0x4158a000,\n 0xcd4000f8, 0x00000000,\n};\n\nstatic unsigned int ar9_fw_data[] = {\n};\n\n\n#endif  //  IFXMIPS_ATM_FW_AR9_H\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-atm/src/ifxmips_atm_fw_ar9_retx.h",
    "content": "#ifndef IFXMIPS_ATM_FW_AR9_H\n#define IFXMIPS_ATM_FW_AR9_H\n\n\n/******************************************************************************\n**\n** FILE NAME    : ifxmips_atm_fw_ar9.h\n** PROJECT      : UEIP\n** MODULES     \t: ATM (ADSL)\n**\n** DATE         : 22 OCT 2007\n** AUTHOR       : Xu Liang\n** DESCRIPTION  : ATM Driver (PP32 Firmware)\n** COPYRIGHT    : \tCopyright (c) 2006\n**\t\t\tInfineon Technologies AG\n**\t\t\tAm Campeon 1-12, 85579 Neubiberg, Germany\n**\n**    This program is free software; you can redistribute it and/or modify\n**    it under the terms of the GNU General Public License as published by\n**    the Free Software Foundation; either version 2 of the License, or\n**    (at your option) any later version.\n**\n** HISTORY\n** $Date        $Author         $Comment\n** 22 OCT 2007  Xu Liang        Initiate Version, v00.01\n*******************************************************************************/\n\n\n#define VER_IN_FIRMWARE         1\n\n#define ATM_FW_VER_MAJOR        0\n#define ATM_FW_VER_MINOR        15\n\n\nstatic unsigned int firmware_binary_code[] = {\n    0x800004B8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x8000FFE0, 0x00000000, 0x00000000, 0x00000000,\n    0xC1000002, 0xD90C00F8, 0xC2000002, 0xDA0800F9, 0xC0001B50, 0x8C100000, 0x00000000, 0x00000000,\n    0x00000000, 0xC2000000, 0xDA0800F9, 0x80006030, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0x80006008, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0xC1001DA6, 0x8D3C0000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0x80005F08, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0xC0400000, 0xC0004840, 0xC88400F8, 0xC2001AEE, 0x8E100000, 0x00000000, 0x00000000, 0x00000000,\n    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0xC0400002, 0xC0004840, 0xC88400F8, 0xC2001AEE, 0x8E100000, 0x00000000, 0x00000000, 0x00000000,\n    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0xC3C00004, 0xDBC800F9, 0xC10C0002, 0xD90C00F8, 0x8000FEE0, 0x00000000, 0x00000000, 0x00000000,\n    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0xC10E0002, 0xD90C00F8, 0xC0004808, 0xC84000F8, 0xC2001B4C, 0x8E100000, 0x00000000, 0x00000000,\n    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0xC3E1FFFE, 0x597DFFFE, 0x593DFE14, 0x900004D9, 0x00000000, 0x00000000, 0x00000000, 0x90CC0481,\n    0x00000000, 0x00000000, 0x00000000, 0xC3E0A252, 0x5BFC001E, 0xC0004002, 0xCFC000F8, 0xC3C00000,\n    0xDBC800F9, 0xC1400008, 0xC1900000, 0x71588000, 0x14100100, 0xC140000A, 0xC1900002, 0x71588000,\n    0x14100100, 0xC140000C, 0xC1900004, 0x71588000, 0x14100100, 0xC1400004, 0xC1900006, 0x71588000,\n    0x14100100, 0xC1400006, 0xC1900008, 0x71588000, 0x14100100, 0xC140000E, 0xC190000A, 0x71588000,\n    0x14100100, 0xC1400000, 0xC190000C, 0x71588000, 0x14100100, 0xC1400002, 0xC190000E, 0x71588000,\n    0x14100100, 0xC0400000, 0xC11C0000, 0xC000082C, 0xCD05CE00, 0xC11C0002, 0xC000082C, 0xCD05CE00,\n    0xC0400002, 0xC11C0000, 0xC000082C, 0xCD05CE00, 0xC0000824, 0x00000000, 0xCBC000F9, 0xCB8000F9,\n    0xCB4000F9, 0xCB0000F8, 0xC0004878, 0x5BFC4000, 0xCFC000F9, 0x5BB84000, 0xCF8000F9, 0x5B744000,\n    0xCF4000F9, 0x5B304000, 0xCF0000F8, 0xC0000A10, 0x00000000, 0xCBC000F9, 0xCB8000F8, 0xC0004874,\n    0x5BFC4000, 0xCFC000F9, 0x5BB84000, 0xCF8000F8, 0xC30001FE, 0xC000140A, 0xCF0000F8, 0xC3000000,\n    0x7F018000, 0xC000042E, 0xCF0000F8, 0xC000040E, 0xCF0000F8, 0xC3C1FFFE, 0xC000490E, 0xCFC00078,\n    0xC000492C, 0xCFC00078, 0xC0004924, 0xCFC00038, 0xC0004912, 0xCFC00038, 0xC0004966, 0xCFC00038,\n    0xC0004968, 0xCFC00078, 0xC000496A, 0xCFC00078, 0xC3C00000, 0xC2800020, 0xC3000000, 0x7F018000,\n    0x6FF88000, 0x6FD44000, 0x4395C000, 0x5BB84A00, 0x5838000A, 0xCF0000F8, 0x5BFC0002, 0xB7E8FFC8,\n    0x00000000, 0xC3C00000, 0xC2800010, 0x6FF86000, 0x47BDC000, 0x5BB84C80, 0xC3400000, 0x58380004,\n    0xCB420078, 0x00000000, 0x58380008, 0xCF400078, 0x5BFC0002, 0xB7E8FFB0, 0x00000000, 0xC3C00000,\n    0xC2800020, 0xC348001E, 0xC3000000, 0x7F018000, 0x6FF8A000, 0x6FD44000, 0x4795C000, 0x47BDC000,\n    0x5BB87000, 0x58380008, 0xCF408418, 0x5838000A, 0xCF0000F8, 0x5BFC0002, 0xB7E8FFB0, 0x00000000,\n    0x00000000, 0xC0004816, 0xC3C00000, 0xCBC00078, 0x00000000, 0x00000000, 0xC1000000, 0xD90400F9,\n    0xDBC40078, 0xC1000006, 0xD90400F9, 0x00000000, 0xC121FFFE, 0x5911FE54, 0x14100000, 0xC3C00000,\n    0xDCFC2000, 0x5FFC0002, 0x00000000, 0x98C08D62, 0xC0004730, 0xC94000F8, 0xC0004732, 0xC0001AF2,\n    0xCBC000F8, 0x00000000, 0x00000000, 0xA7C20470, 0xC000474A, 0xCA8000F8, 0x00000000, 0x00000000,\n    0x5D280000, 0x8400FFE0, 0x00000000, 0xC121FFFE, 0x5911FEF4, 0x14100000, 0x00000000, 0x00000000,\n    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0xC2802000, 0x6EA8E010, 0xC0004200, 0xC2400000, 0x7E410000, 0xC1000000, 0xCE4000F9, 0xCE4000F9,\n    0xCE4000F9, 0xCE4000F9, 0x5EA80002, 0x8400FFD8, 0xC0004300, 0xC2800200, 0x6EA84010, 0xCE4000F9,\n    0xCE0000F9, 0xCE4000F9, 0xCE0000F9, 0xCE4000F9, 0xCE0000F9, 0xCE4000F9, 0xCE0000F9, 0x5EA80002,\n    0x8400FFB8, 0xC0004700, 0xC2800200, 0x6EA8E010, 0xCE4000F9, 0xCE4000F9, 0xCE4000F9, 0xCE4000F9,\n    0x5EA80002, 0x8400FFD8, 0xC0004740, 0xCE4000F8, 0xC0004742, 0xC1000200, 0x5D100002, 0xCD0000F8,\n    0xC0004744, 0xCE4000F8, 0xC0004746, 0xCE4000F8, 0xC0004748, 0xCE4000F8, 0xC000474A, 0xCE4000F8,\n    0xC000474C, 0xC1000002, 0xCD0000F8, 0xC000474E, 0xCE4000F8, 0xC0004750, 0xCE4000F8, 0xC0004752,\n    0xCE4000F8, 0xC0004754, 0xCE4000F8, 0xC0400000, 0xC11C0000, 0xC000082C, 0xCD05CE00, 0xC0000838,\n    0xCE4000F8, 0xC0000818, 0xCE4000F8, 0xC0000820, 0xCE4000F8, 0xC2804840, 0xC240485A, 0x98C086B0,\n    0xC68000F8, 0xC65400F8, 0xC1800000, 0xC11C0002, 0xC000082C, 0xCD05CE00, 0x00000000, 0xC121FFFE,\n    0x5911FE54, 0x14100000, 0xC0000A10, 0xCB8000F8, 0xC0000A12, 0xCB4000F8, 0xC0000A14, 0xCB0000F8,\n    0xC0000A16, 0xCAC000F8, 0xC0000040, 0xC2800000, 0xCE800000, 0x00000000, 0x00000000, 0x00000000,\n    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xC2800002,\n    0xCE800000, 0xC0000A10, 0xCF8000F8, 0xC0000A12, 0xCF4000F8, 0xC0000A14, 0xCF0000F8, 0xC0000A16,\n    0xCEC000F8, 0xC1000000, 0xC00048A0, 0xCD0000F8, 0xC00048A2, 0xCD0000F8, 0xC0001AF2, 0xC1000000,\n    0xCD002100, 0x80001038, 0x00000000, 0xC3C00000, 0xDCFC2000, 0x5FFC0002, 0x00000000, 0x98C08D62,\n    0xC0004730, 0xC94000F8, 0xC0004732, 0x800033D8, 0x00000000, 0xC3C00000, 0xDCFC2000, 0x5FFC0002,\n    0x00000000, 0x98C08D62, 0xC0004730, 0xC94000F8, 0xC0004732, 0xC0004810, 0xC90000F8, 0xC000474A,\n    0xC94000F8, 0xA50007E8, 0x00000000, 0x5D140002, 0x840007D2, 0xC1000000, 0xC000484A, 0xC90000F8,\n    0xC0004740, 0xC84000F8, 0x5D100000, 0x84000798, 0x00000000, 0x00000000, 0xC121FFFE, 0x5911FEF4,\n    0x14100000, 0xC0004744, 0xC88000F8, 0xC0001AF0, 0xC3000000, 0x58000002, 0xCB010038, 0x6C7C2000,\n    0x5BFC4300, 0x98C08A88, 0xC1400000, 0xC4540020, 0x6C40A010, 0x5D240002, 0x8400021A, 0x00000000,\n    0xC0004742, 0xCA8000F8, 0x00000000, 0x00000000, 0x59280002, 0x6D130000, 0x6D130010, 0x45048000,\n    0x84000692, 0x00000000, 0x98C08870, 0xC45400F8, 0xC69800F8, 0xC241FFFE, 0xC67400F8, 0x5D35FFFE,\n    0x84000652, 0x47448000, 0x84000642, 0xC1000000, 0x6F502000, 0xC0004300, 0x40100000, 0xC1400000,\n    0x58000000, 0xC9410038, 0xC1800000, 0xC0004814, 0xC9820038, 0x4714A000, 0xC10001FE, 0x4150A004,\n    0x45588000, 0x880005CA, 0x4744C000, 0xC1000200, 0x4190C004, 0xC000473E, 0xC90000F8, 0x00000000,\n    0x00000000, 0x41188000, 0xCD0000F8, 0xC000471C, 0xC90000F8, 0x00000000, 0x00000000, 0x41188000,\n    0xCD0000F8, 0x98C087E8, 0xC45400F8, 0x6C58A010, 0xC0004700, 0x58440002, 0x6C470000, 0x6C470010,\n    0x44748000, 0x8400FFC0, 0xC74400F8, 0xC0004740, 0xCC4000F8, 0xC0800000, 0xC0004744, 0xCC8000F8,\n    0x800004D0, 0xC1000000, 0x583C0000, 0xC9000038, 0x00000000, 0x00000000, 0x44908000, 0x88000280,\n    0xC1400000, 0x583C0000, 0xC9410038, 0xC1800000, 0xC0004814, 0xC9800038, 0x4714A000, 0xC10001FE,\n    0x4150A004, 0x45588000, 0x88000442, 0xC3800000, 0x583C0002, 0xCB820078, 0xC1000000, 0x583C0002,\n    0xC9000078, 0x00000000, 0x00000000, 0x47908000, 0x8400024A, 0xC0400002, 0xC0800000, 0xC3C00000,\n    0xC000481A, 0xC80000F8, 0x6F908000, 0x45388000, 0x45388000, 0x4011E000, 0xC000491E, 0xCFC000F8,\n    0xC3400000, 0xC0004878, 0xC80400F8, 0x6C908000, 0x45088000, 0x45088000, 0x40100000, 0xCAC000F8,\n    0xC43000F8, 0x00000000, 0xC7340060, 0xC1000002, 0xC5341B00, 0xC100001C, 0xC5341048, 0xC100000C,\n    0xC5340D10, 0xC000491C, 0xCF4000F8, 0xC3000000, 0xDF700038, 0x5D300080, 0x8800FFE8, 0xC000474A,\n    0xC1000002, 0xCD0000F8, 0xC000491C, 0xCB4000F8, 0xC000491E, 0xCBC000F8, 0x99007F18, 0xDB5800F8,\n    0xDBD800F9, 0x00000000, 0xC1400000, 0xC794A030, 0xC1800000, 0xC7980020, 0x58144200, 0xC9C000F8,\n    0xC1210000, 0x69188010, 0x7D008000, 0x75D0E000, 0xCDC000F8, 0x80000228, 0x00000000, 0xC1000000,\n    0x583C0000, 0xC903E000, 0x00000000, 0x00000000, 0x5D100000, 0x84000042, 0xC0004734, 0xC90000F8,\n    0x00000000, 0x00000000, 0x59100002, 0xCD0000F8, 0x800000C0, 0xC1400000, 0x583C0000, 0xC9410038,\n    0xC1800000, 0xC0004814, 0xC9820038, 0x4714A000, 0xC10001FE, 0x4150A004, 0x45588000, 0x8800015A,\n    0xC000473E, 0xC90000F8, 0x00000000, 0x00000000, 0x59100002, 0xCD0000F8, 0xC000471C, 0xC90000F8,\n    0x00000000, 0x00000000, 0x59100002, 0xCD0000F8, 0xC3800000, 0x583C0002, 0xCB820078, 0x00000000,\n    0x00000000, 0x5D39FFFE, 0x84000062, 0xC1400000, 0xC794A030, 0xC1800000, 0xC7980020, 0x58144200,\n    0xC9C000F8, 0xC1210000, 0x69188010, 0x7D008000, 0x75D0E000, 0xCDC000F8, 0x98C087E8, 0xC45400F8,\n    0x6C58A010, 0xC0004700, 0x58440002, 0x6C470000, 0x6C470010, 0xC0004740, 0xCC4000F8, 0xC0800000,\n    0xC0004744, 0xCC8000F8, 0x00000000, 0xC121FFFE, 0x5911FE54, 0x14100000, 0x8000F288, 0x00000000,\n    0x00000000, 0x98C086F0, 0xC0004748, 0xC98000F8, 0xC2000000, 0x00000000, 0x00000000, 0x00000000,\n    0x00000000, 0x00000000, 0x00000000, 0xC1400000, 0xC7D4A030, 0xC1800000, 0xC7D80020, 0x58144200,\n    0xC9C000F8, 0xC1210000, 0x69188010, 0x7D008000, 0x75D0E000, 0xCDC000F8, 0x00000000, 0x00000000,\n    0x00000000, 0x00000000, 0x98C087E8, 0xC7D400F8, 0x6FD8A010, 0xC0004700, 0x00000000, 0x00000000,\n    0x00000000, 0x00000000, 0x98C08870, 0xC7D400F8, 0xC79800F8, 0xC241FFFE, 0x00000000, 0x00000000,\n    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x98C08A88, 0xC1400000, 0xC7D40020, 0x6FC0A010,\n    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x98C08AB8, 0xC1400000, 0xC7D40020, 0x6FC0A010,\n    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x98C08AF0, 0xC7D400F8, 0xC0004740, 0xC9C000F8,\n    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x98C08BE0, 0xC7D400F8, 0xC0004742, 0xC98000F8,\n    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xC0004958, 0xC84000F8, 0x00000000, 0xC3C00002,\n    0x787C2000, 0xCC4000F8, 0xC0004848, 0xCB8400F8, 0xC000495C, 0xCAC400F8, 0xC0004844, 0xC88400F8,\n    0x47AD0000, 0x8400F492, 0xC000487C, 0xC80400F8, 0x00000000, 0x00000000, 0x40080000, 0xCA0000F8,\n    0xC0001624, 0xCB0400F8, 0xA63C007A, 0x00000000, 0x00000000, 0xA71EF432, 0x00000000, 0xC0000824,\n    0xCA8400F8, 0x6CA08000, 0x6CA42000, 0x46250000, 0x42290000, 0xC35E0002, 0xC6340060, 0xC0001624,\n    0xCF440078, 0xC2000000, 0xC161FFFE, 0x5955FFFE, 0x14140000, 0x00000000, 0x00000000, 0x00000000,\n    0x00000000, 0xC0004844, 0xC88400F8, 0xC000082C, 0xCA040038, 0x00000000, 0x00000000, 0x58880002,\n    0xB6080018, 0x00000000, 0xC0800000, 0xC0004844, 0xCC840038, 0x5AEC0002, 0xC000495C, 0xCEC400F8,\n    0x5E6C0006, 0x84000060, 0xC0004848, 0xCB8400F8, 0xC0000838, 0xC2500002, 0xCE450800, 0x5FB80002,\n    0xC0004848, 0xCF8400F8, 0x5EEC0002, 0xC000495C, 0xCEC400F8, 0x00000000, 0xC121FFFE, 0x5911FE54,\n    0x14100000, 0x8000F290, 0xC000495A, 0xC84000F8, 0x00000000, 0xC3C00002, 0x787C2000, 0xCC4000F8,\n    0xC0004960, 0xCAC400F8, 0x00000000, 0x00000000, 0x5EEC0000, 0x8400010A, 0x00000000, 0xB6FC0050,\n    0xC0001600, 0xCA0400F8, 0x00000000, 0x00000000, 0xA61E00D2, 0x6FE90000, 0xC0000A28, 0xCE850800,\n    0xC2C00000, 0xC2800004, 0xB6E800A0, 0xC0001604, 0xCA8400F8, 0xC0004960, 0xCEC400F8, 0xA69EFCAA,\n    0x00000000, 0x6FE90000, 0xC0000A28, 0xCE850800, 0xC2C00002, 0xC0001600, 0xCA0400F8, 0x00000000,\n    0x00000000, 0xA61E002A, 0x6FE90000, 0xC0000A28, 0xCE850800, 0xC2C00000, 0xC0001604, 0xCA8400F8,\n    0xC0004960, 0xCEC400F8, 0xA69EFC12, 0xC2400000, 0xC0000A14, 0xCA440028, 0x00000000, 0x00000000,\n    0x466D2000, 0xA4400020, 0xC2800000, 0xDFEB0029, 0x80000010, 0xDFEA0029, 0xB668EC0A, 0x00000000,\n    0xC00048A0, 0xCB0400F8, 0xC0000A10, 0xCA8400F8, 0x6F208000, 0x6F242000, 0x46250000, 0x42A10000,\n    0xC2400000, 0xC0000A14, 0xCA440028, 0xC35E0002, 0xC6340060, 0xC0001604, 0xCF440078, 0x5B300002,\n    0xB6700018, 0x5AEC0002, 0xC3000000, 0xC00048A0, 0xCF0400F8, 0xC0004960, 0xCEC400F8, 0x8000F030,\n    0xC0004918, 0xD28000F8, 0xC2000000, 0xDF600038, 0x5E600080, 0x840002A2, 0x00000000, 0xC161FFFE,\n    0x5955FFFE, 0x14140000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xC000480A, 0xCA0000F8,\n    0xC0004912, 0xCA4000F8, 0xC0004924, 0xCA8000F8, 0xC0004966, 0xCAC000F8, 0x00000000, 0xC121FFFE,\n    0x5911FE54, 0x14100000, 0x76250000, 0x76290000, 0x762D0000, 0x840001E2, 0xC0004918, 0xCA4000F8,\n    0xC28001FE, 0x76290000, 0x5A640002, 0x6A254010, 0x5EE80000, 0x8400001A, 0x6AA54000, 0x80000010,\n    0xC62800F8, 0x62818008, 0xC0004918, 0xCF0000F8, 0xC161FFFE, 0x5955FFFE, 0x14140000, 0x00000000,\n    0x00000000, 0x00000000, 0x00000000, 0xC0004966, 0xCA4000F8, 0xC2000002, 0x6A310000, 0x7E010000,\n    0x76612000, 0xCE4000F8, 0x00000000, 0xC121FFFE, 0x5911FE54, 0x14100000, 0x6F346000, 0x4771A000,\n    0x5B744C80, 0xC2800000, 0x58340006, 0xCA800078, 0xC2C00000, 0x58340000, 0xCAC000D8, 0xC2400000,\n    0x5834000A, 0xCA420078, 0x6EA82000, 0x42E9E000, 0x6F2CA000, 0x42E56000, 0x5AEC2E00, 0xC3990040,\n    0xC7381C18, 0xC6F80060, 0x99007F18, 0xDB9800F8, 0xDBD800F9, 0x00000000, 0xDEA000F8, 0x46310000,\n    0x8400FD50, 0xC0004958, 0xC84000F8, 0x00000000, 0xC1000002, 0x78502000, 0xCC4000F8, 0xC0004848,\n    0xCBC400F8, 0xC0004844, 0xC88400F8, 0x5FFC0000, 0x8400ECBA, 0xC0004740, 0xCB0000F8, 0xC0004744,\n    0xCAC000F8, 0x6F282000, 0x5AA84300, 0xC000487C, 0xC80400F8, 0x00000000, 0x00000000, 0x40080000,\n    0xCA4000F8, 0xC40000F8, 0x00000000, 0xC0004878, 0xC80400F8, 0x6C908000, 0x45088000, 0x45088000,\n    0x40100000, 0xC90000F8, 0xC43400F8, 0x00000000, 0x5C440000, 0x840000A2, 0x00000000, 0xC00047D2,\n    0xC90000F8, 0x00000000, 0x00000000, 0x59100002, 0xCD0000F8, 0x58340002, 0xC9000078, 0x00000000,\n    0x00000000, 0x58280002, 0x6D120000, 0xCD021078, 0x5AEC0002, 0xC0004744, 0xCEC000F8, 0x80000630,\n    0x00000000, 0xC00047C0, 0xC90000F8, 0x00000000, 0x00000000, 0x59100002, 0xCD0000F8, 0xA67C0048,\n    0xC00047C2, 0xC90000F8, 0x00000000, 0x00000000, 0x59100002, 0xCD0000F8, 0x80001E18, 0x00000000,\n    0xA6600042, 0xC00047C4, 0xC90000F8, 0x00000000, 0x00000000, 0x59100002, 0xCD0000F8, 0x80000570,\n    0xC00047C6, 0xC90000F8, 0x00000000, 0x00000000, 0x59100002, 0xCD0000F8, 0xC3C00000, 0xC67D0038,\n    0xC3800000, 0xC6780038, 0x47F08000, 0x840000A8, 0x47AC8000, 0x84000098, 0xC1000000, 0xC0004814,\n    0xC9000038, 0x00000000, 0x00000000, 0x5D100000, 0x840000F0, 0x5AEC0002, 0xC0004744, 0xCEC000F8,\n    0xC00047CA, 0xC90000F8, 0x00000000, 0x00000000, 0x59100002, 0xCD0000F8, 0x80000478, 0x00000000,\n    0x98C08AF0, 0xC7D400F8, 0xC0004740, 0xC9C000F8, 0x5D240000, 0x8400006A, 0x00000000, 0x98C087E8,\n    0xC7D400F8, 0x6FD8A010, 0xC0004700, 0xC00047C8, 0xC90000F8, 0x00000000, 0x00000000, 0x59100002,\n    0xCD0000F8, 0x80001C40, 0xC00047CC, 0xC90000F8, 0x00000000, 0x00000000, 0x59100002, 0xCD0000F8,\n    0x6FE82000, 0x5AA84300, 0x5D380000, 0x840000A0, 0x00000000, 0x98C086F0, 0xC0004748, 0xC98000F8,\n    0xC2000000, 0x58280002, 0x6E520000, 0xCD021078, 0x58280002, 0xCE400078, 0x5D25FFFE, 0x84000040,\n    0xC00047D0, 0xC90000F8, 0x00000000, 0x00000000, 0x59100002, 0xCD0000F8, 0x800002D0, 0xC3000000,\n    0x58280002, 0xCB000078, 0x00000000, 0x00000000, 0x5D31FFFE, 0x84000048, 0xC00047D0, 0xC90000F8,\n    0x00000000, 0x00000000, 0x59100002, 0xCD0000F8, 0x80000260, 0x00000000, 0x98C086F0, 0xC0004748,\n    0xC98000F8, 0xC2000000, 0x58340002, 0xC6500078, 0xC7D01038, 0xC7901838, 0xCD0000F8, 0x58280002,\n    0xCE400078, 0xC3C00200, 0x5FFC001C, 0xC3800000, 0xDF790048, 0x00000000, 0x00000000, 0x47F88000,\n    0x8800FFDA, 0xC0004862, 0xCBC000F8, 0xC0000000, 0xC76C00F8, 0x5BBC7800, 0xC280001C, 0xCA6C00F9,\n    0x00000000, 0x00000000, 0xCE7800F9, 0xC1007A00, 0x45388000, 0xC1007800, 0xC53800FE, 0x5EA80002,\n    0x8400FFB8, 0xC3800000, 0xC000481A, 0xC80000F8, 0x6F108000, 0x45308000, 0x45308000, 0x4011C000,\n    0xC000491E, 0xCF8000F8, 0xC2C00000, 0xC7EC0060, 0xC100001C, 0xC52C1048, 0xC100000A, 0xC52C0D10,\n    0xC000491C, 0xCEC000F8, 0x99007CF0, 0xC000491C, 0xC1400000, 0xC9420048, 0xC2800000, 0xDF680038,\n    0x5D280080, 0x8800FFE8, 0xC000491C, 0xCAC000F8, 0xC000491E, 0xCB8000F8, 0x99007F18, 0xDAD800F8,\n    0xDB9800F9, 0x00000000, 0xC00047CE, 0xC90000F8, 0x00000000, 0x00000000, 0x59100002, 0xCD0000F8,\n    0x00000000, 0x80001880, 0x00000000, 0x00000000, 0x00000000, 0xC0004878, 0xC80400F8, 0x6C908000,\n    0x45088000, 0x45088000, 0x40100000, 0xCA0000F8, 0xC42400F8, 0x00000000, 0xC0004934, 0xCE0000F8,\n    0xC2800002, 0xC4681C08, 0xC62821D0, 0xC6281E00, 0xC2600010, 0x5A650060, 0xC0004800, 0xCB4000F8,\n    0xC2200400, 0x5A200020, 0xC7601040, 0xC0001220, 0xCE8000F8, 0xC0001200, 0xCE4000F8, 0xC0001202,\n    0xCE0000F8, 0xC0001240, 0xCB4000F8, 0x00000000, 0x00000000, 0xA754FFE0, 0xC2000000, 0xC7600040,\n    0xA7520042, 0x00000000, 0x00000000, 0x99008690, 0xC0004822, 0xC94000F8, 0xC1800002, 0x80001710,\n    0x582040A0, 0xC2000000, 0xCA000018, 0xC2400000, 0xCA414000, 0xC2800000, 0xCA812000, 0xC2C00000,\n    0xCAC20018, 0xC0004938, 0xCE0000F8, 0xC0004920, 0xCE4000F8, 0xC0004916, 0xCE8000F8, 0xC0004922,\n    0xCEC000F8, 0xA6400558, 0x00000000, 0xC0004938, 0xCBC000F8, 0x00000000, 0xC3800000, 0x6FF48000,\n    0x6FD44000, 0x4355A000, 0x5B744A00, 0x58340000, 0xCB802010, 0x00000000, 0xC2000000, 0x6FB46000,\n    0x4779A000, 0x5B744C80, 0x5834000C, 0xCA000020, 0xC000491A, 0xCF8000F8, 0x5E200000, 0x84000482,\n    0xC2000000, 0xDF610048, 0x5E6001E8, 0x8800FFE8, 0xC2000002, 0xC2400466, 0xC2A00000, 0x5AA80000,\n    0xC0001006, 0xCE0000F8, 0xC0001008, 0xCE4000F8, 0xC000100A, 0xCE8000F8, 0x99007958, 0xC1A0FFFE,\n    0xC0000824, 0xC9840060, 0xC0004934, 0xCA4000F8, 0xC2000000, 0xC2800002, 0x99007998, 0xDA9800F8,\n    0xC61400F8, 0xC65800F8, 0xC161FFFE, 0x5955FFFE, 0x14140000, 0x00000000, 0x00000000, 0x00000000,\n    0x00000000, 0x99007A80, 0xC000491A, 0xC94000F8, 0x00000000, 0x00000000, 0xC121FFFE, 0x5911FE54,\n    0x14100000, 0xC0004922, 0xCA001118, 0xC3C00000, 0xC3800000, 0xC0004930, 0xCE023118, 0xC0004932,\n    0xCBC000D8, 0xC2800000, 0xC000491E, 0xCFC000F8, 0xC0004862, 0xCA800060, 0xC3A0001A, 0x5BB94000,\n    0xC6B80060, 0xC000491C, 0xCF8000F8, 0x99007CF0, 0xC000491C, 0xC1400000, 0xC9420048, 0x00000000,\n    0x00000000, 0x00000000, 0xA8E2FFE8, 0xC2000000, 0xC1220002, 0xD90C00F8, 0xDF600038, 0x5E600080,\n    0x8400FFF2, 0xC000491C, 0xCA0000F8, 0xC000491E, 0xCA4000F8, 0x00000000, 0x00000000, 0x99007F18,\n    0xDA1800F8, 0xDA5800F9, 0x00000000, 0xC2000000, 0xDF610048, 0x5E6001FE, 0x8800FFE8, 0xC0004916,\n    0xCA8000F8, 0xC2C00000, 0xDFEC0048, 0xC2400000, 0x466D2000, 0x8400004A, 0x5EA80000, 0x8400003A,\n    0xC2600002, 0x99008690, 0xC000482E, 0xC94000F8, 0xC1800002, 0x80000030, 0xC2600000, 0x99008690,\n    0xC000482C, 0xC94000F8, 0xC1800002, 0xC2000068, 0xC6240078, 0xC0004930, 0xCE400080, 0xC000491A,\n    0xC98000F8, 0xC0004862, 0xC94000F8, 0x6D9C6000, 0x45D8E000, 0x59DC4C80, 0x99007D78, 0xD95800F8,\n    0xD99800F9, 0xD9D400F8, 0x99007CF0, 0xC000491C, 0xC1400000, 0xC9420048, 0xC2000000, 0xDF600038,\n    0x5E600080, 0x8400FFEA, 0x00000000, 0xC000491C, 0xCA0000F8, 0xC000491E, 0xCA4000F8, 0x00000000,\n    0x00000000, 0x99007F18, 0xDA1800F8, 0xDA5800F9, 0x00000000, 0x80001160, 0x00000000, 0x99008690,\n    0xC000482A, 0xC94000F8, 0xC1800002, 0x80001130, 0xC0004938, 0xCBC000F8, 0x00000000, 0x00000000,\n    0x6FF88000, 0x6FD44000, 0x4395C000, 0x5BB84A00, 0x58380008, 0xCA0000F8, 0x00000000, 0x00000000,\n    0xA600039A, 0x00000000, 0xC0004938, 0xCBC000F8, 0xC3000000, 0x00000000, 0x6FF88000, 0x6FD44000,\n    0x4395C000, 0x5BB84A00, 0x58380000, 0xCB002010, 0xC2000000, 0x58380008, 0xCA020078, 0x5838000C,\n    0xCAC000F8, 0x5838000E, 0xCA4000F8, 0xC000491A, 0xCF0000F8, 0xC0004930, 0xCEC000F8, 0xC000493C,\n    0xCE0000F8, 0xC0004932, 0xCE4000F8, 0x5E200000, 0x84000138, 0xC2800000, 0xA6FE00D2, 0x6F206000,\n    0x46310000, 0x5A204C80, 0x5820000C, 0xCA800020, 0x00000000, 0x00000000, 0x5EA80000, 0x8400020A,\n    0x00000000, 0xC161FFFE, 0x5955FFFE, 0x14140000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0x99007A80, 0xC000491A, 0xC94000F8, 0x00000000, 0x00000000, 0xC121FFFE, 0x5911FE54, 0x14100000,\n    0xC0004930, 0xCAC000F8, 0xC0004932, 0xCA4000F8, 0xC7EC1118, 0xC0004930, 0xCEC000F8, 0x5838000C,\n    0xCEC000F8, 0x58000002, 0xCE4000F8, 0xC0004934, 0xCA0000F8, 0xC2400002, 0x6E642000, 0x6E642000,\n    0x76612000, 0x8400002A, 0xC2400002, 0x6E684000, 0x58380008, 0xCE804200, 0xA6000020, 0x6E682000,\n    0x58380008, 0xCE802100, 0xC2400002, 0x6E642000, 0x76612000, 0x840000EA, 0x58380008, 0xCA0000F8,\n    0xC2800000, 0xC2400000, 0xA60200C0, 0xDBA800F8, 0x6F386000, 0x47B1C000, 0x5BB84C80, 0x58380004,\n    0xCA400078, 0x58380002, 0xCA800078, 0x00000000, 0xDEB800F8, 0x46A54000, 0x88000060, 0x00000000,\n    0xC0004824, 0xCA0000F8, 0xC2400002, 0x6E640000, 0x5A200002, 0xCE0000F8, 0x58380008, 0xCE400000,\n    0x80000018, 0x00000000, 0x80000048, 0xC0004934, 0xCA0000F8, 0x00000000, 0x00000000, 0xA6020CCA,\n    0x00000000, 0x00000000, 0x80000CF8, 0xC2800000, 0xC2000200, 0xC240001A, 0xDF690048, 0x46294000,\n    0x46A54000, 0x8800FFD2, 0xC2000006, 0xC2600982, 0x5A643B6E, 0x5838000A, 0xCA8000F8, 0xC0001006,\n    0xCE0000F8, 0xC0001008, 0xCE4000F8, 0xC000100A, 0xCE8000F8, 0x99007958, 0xC1A0FFFE, 0xC0000824,\n    0xC9840060, 0xC2000000, 0xC0004930, 0xCA02E008, 0x58380026, 0xCA4000F8, 0x00000000, 0xC2800000,\n    0x99007998, 0xDA9800F8, 0xC61400F8, 0xC65800F8, 0xC0004934, 0xCA0000F8, 0x00000000, 0x00000000,\n    0xA6020022, 0x00000000, 0x00000000, 0x80000318, 0xC0004938, 0xCBC000F8, 0xC0004878, 0xC80400F8,\n    0x6C908000, 0x45088000, 0x45088000, 0x40100000, 0xCA0000F8, 0xC42400F8, 0x00000000, 0x58240018,\n    0xCA0000F8, 0x6FF88000, 0x6FD44000, 0x4395C000, 0x5BB84A00, 0xC3000000, 0xC3400002, 0xC2C00000,\n    0xC62C0078, 0xC6270038, 0xC0004940, 0xCE400038, 0xC6260038, 0xC0004942, 0xCE400038, 0xC000493C,\n    0xCA0000F8, 0x5EEC0000, 0x8400018A, 0x5A6C0010, 0x46254000, 0x88000190, 0x5A600052, 0x46E54000,\n    0x88000178, 0x58380006, 0xCA8000F8, 0xC0004940, 0xCA0000F8, 0xC2400000, 0xC6A70038, 0x7E412000,\n    0x76612000, 0xC2000000, 0xC6A10038, 0x46250000, 0x84000138, 0xC0004942, 0xCA0000F8, 0xC2400000,\n    0xC6A60038, 0x7E412000, 0x76612000, 0xC2000000, 0xC6A00038, 0x58380002, 0xCA8000F8, 0x46250000,\n    0x840000E8, 0xC2400000, 0xC6A60078, 0x466D0000, 0x880000DA, 0xC2400000, 0xC6A40078, 0x58380008,\n    0xCA8000F8, 0x46E50000, 0x880000BA, 0x00000000, 0xA6820018, 0x00000000, 0xC7700B00, 0xA6840098,\n    0x00000000, 0xC7700A00, 0x80000080, 0xC7700200, 0xC000493C, 0xCAC000F8, 0x80000060, 0xC7700300,\n    0xC000493C, 0xCAC000F8, 0x80000040, 0xC7700900, 0x80000030, 0xC7700800, 0x80000020, 0xC7700700,\n    0x80000010, 0xC7700500, 0xC0004944, 0xCF0000F8, 0xC000493E, 0xCEC000F8, 0xC0004938, 0xCA4000F8,\n    0xC000493C, 0xCB8000F8, 0xC000493E, 0xCB4000F8, 0xC3000000, 0x6E608000, 0x6E544000, 0x42150000,\n    0x5A204A00, 0x5AA00008, 0x58200004, 0xCB000078, 0xC0004934, 0xCA0000F8, 0xC2400000, 0xC0004930,\n    0xCA42E008, 0xC3C00018, 0xA6020098, 0x00000000, 0x43656000, 0x47AD0000, 0x88000050, 0x46F96000,\n    0x6EE04010, 0x5BE00004, 0xC2000000, 0xC6E00008, 0x5E200000, 0x84000042, 0x5BFC0002, 0x80000030,\n    0xC3C00004, 0x5A2C0008, 0x47A10000, 0x88000012, 0x5FB80008, 0x6FE04000, 0x42390000, 0x47212000,\n    0x88000068, 0xC2400000, 0xC0004930, 0xCA42E008, 0xC2060002, 0xC68000F8, 0xCE006300, 0x6FE04000,\n    0x4721C000, 0x5F700010, 0x4765A000, 0xC2000000, 0xC6340008, 0xC25A000A, 0xC000491A, 0xCA401C18,\n    0xC2800000, 0xC0004932, 0xCA8000D8, 0xC0004862, 0xCA400060, 0x6FA04010, 0x42290000, 0xC000491E,\n    0xCE0000F8, 0xC7E41048, 0xC000491C, 0xCE4000F8, 0x6FE04000, 0x43A1C000, 0xC000493C, 0xCF8000F8,\n    0xC000493E, 0xCF4000F8, 0xC000493A, 0xCFC000F8, 0x80000008, 0x00000000, 0x00000000, 0x00000000,\n    0xC2000000, 0xDCE000F8, 0xA622FFD8, 0xC1220002, 0xD90C00F8, 0xC0004938, 0xCBC000F8, 0xC0004944,\n    0xCB4000F8, 0xC0004862, 0xCB0000F8, 0xC0004934, 0xCA0000F8, 0x6FF88000, 0x6FD44000, 0x4395C000,\n    0x5BB84A00, 0xA6020298, 0xC2400000, 0x58380008, 0xCA406000, 0xDFE800F8, 0xC2218E08, 0x5A21BAF6,\n    0x46A14000, 0x84000022, 0xC2080002, 0x7361A000, 0x80000058, 0x5E640000, 0x84000022, 0xC20C0002,\n    0x7361A000, 0x80000030, 0xC2000000, 0xC760E710, 0xC7604218, 0x5E200000, 0x840002A2, 0xC2200002,\n    0xC0004930, 0xCE021000, 0x99008690, 0xC0004828, 0xC94000F8, 0xC1800002, 0xC0004780, 0xC93C00F8,\n    0x00000000, 0x00000000, 0x59100002, 0xCD3C00F8, 0x58380000, 0xCA0000F8, 0x00000000, 0x00000000,\n    0xA6000132, 0xC0004940, 0xCA8000F8, 0xC0004942, 0xCA4000F8, 0xC7600078, 0xC6A01838, 0xC6601038,\n    0xC000493A, 0xCA4000F8, 0xC0004934, 0xCA8000F8, 0xC0007800, 0x40300000, 0x40240000, 0x5C000004,\n    0x5EC07A00, 0x88000012, 0x5C000200, 0xCE0000F8, 0x58000002, 0x5EC07A00, 0x88000012, 0x5C000200,\n    0xCE8000F8, 0xC000493E, 0xCA0000F8, 0xC2400000, 0x5838000C, 0xCE4000F8, 0x99008690, 0xC0004830,\n    0xC94000F8, 0xC61800F8, 0xC0004930, 0xC6100078, 0xCD000078, 0x800000A8, 0xC2400002, 0x58380008,\n    0xCE400000, 0xC0004944, 0xCF4000F8, 0x800002A8, 0xC000493C, 0xCA4000F8, 0xDFE800F8, 0x5A300018,\n    0xC0007800, 0x40200000, 0xCA0000F8, 0x58380008, 0xC6501078, 0xCD021078, 0x5838000A, 0xCE8000F8,\n    0x58380026, 0xCE0000F8, 0xC0004944, 0xCF4000F8, 0x99007CF0, 0xC000491C, 0xC1400000, 0xC9420048,\n    0x80000068, 0x00000000, 0x99008690, 0xC0004826, 0xC94000F8, 0xC1800002, 0xC0004760, 0xC93C00F8,\n    0x00000000, 0x00000000, 0x59100002, 0xCD3C00F8, 0x8000FDA8, 0xC2000000, 0xC2400080, 0xDF600038,\n    0xB624FFEA, 0xC000491C, 0xCA4000F8, 0xC000491E, 0xCA8000F8, 0x99007F18, 0xDA5800F8, 0xDA9800F9,\n    0x00000000, 0xC0004934, 0xCA0000F8, 0x00000000, 0xC2800000, 0xA6020160, 0xC2400004, 0xC2000200,\n    0xDF690048, 0x46294000, 0x46A54000, 0x8800FFDA, 0x00000000, 0xC000491A, 0xC98000F8, 0xC0004862,\n    0xC94000F8, 0x6D9C6000, 0x45D8E000, 0x59DC4C80, 0x99007D78, 0xD95800F8, 0xD99800F9, 0xD9D400F8,\n    0x99007CF0, 0xC000491C, 0xC1400000, 0xC9420048, 0xC2000000, 0xC2400080, 0xDF600038, 0xB624FFEA,\n    0xC000491C, 0xCA4000F8, 0xC000491E, 0xCA8000F8, 0x99007F18, 0xDA5800F8, 0xDA9800F9, 0x00000000,\n    0x58380008, 0xCA4000F8, 0xC2000000, 0xCE000018, 0xC2A1FFFE, 0x5AA9FFFE, 0xCE021078, 0x5838000A,\n    0xCE8000F8, 0xC161FFFE, 0x5955FFFE, 0x14140000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0xC0000838, 0xC2500002, 0xCE450800, 0xC0004848, 0xCBC400F8, 0xC3800000, 0xC000082C, 0xCB840028,\n    0x5FFC0002, 0xC0004848, 0xCFC400F8, 0x58880002, 0x47888000, 0xC1000000, 0xC50800FE, 0xC0004844,\n    0xCC8400F8, 0x00000000, 0xC121FFFE, 0x5911FE54, 0x14100000, 0x8000CBF0, 0xC2000000, 0xDF600038,\n    0x5E200080, 0x8400029A, 0x00000000, 0xC161FFFE, 0x5955FFFE, 0x14140000, 0x00000000, 0x00000000,\n    0x00000000, 0x00000000, 0xC000480C, 0xCA0000F8, 0xC0004910, 0xCA4000F8, 0xC000492C, 0xCA8000F8,\n    0xC0004968, 0xCAC000F8, 0x00000000, 0xC121FFFE, 0x5911FE54, 0x14100000, 0x76250000, 0x76290000,\n    0x76E16000, 0x840001DA, 0xC0004926, 0xCA4000F8, 0xC201FFFE, 0x76E16000, 0x5A640002, 0x6AE50010,\n    0x5F200000, 0x8400001A, 0x6A250000, 0x80000010, 0xC6E000F8, 0x62014008, 0xC0004926, 0xCE8000F8,\n    0xC161FFFE, 0x5955FFFE, 0x14140000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xC0004968,\n    0xCA4000F8, 0xC2000002, 0x6A290000, 0x7E010000, 0x76612000, 0xCE4000F8, 0x00000000, 0xC121FFFE,\n    0x5911FE54, 0x14100000, 0x6EB4A000, 0x6E944000, 0x4755A000, 0x4769A000, 0x5B747000, 0x58340002,\n    0xC2000000, 0xCA0000D8, 0x5834002E, 0xC2400000, 0xCA400078, 0x6EB0A000, 0x6EBC4000, 0x473D8000,\n    0x47298000, 0x5B30302E, 0x5B300004, 0x6E642000, 0x4225E000, 0xC39A8024, 0xC7380060, 0xC6B81C18,\n    0x99007F18, 0xDB9800F8, 0xDBD800F9, 0x00000000, 0xC2000000, 0xDF600038, 0x5E200080, 0x840002D2,\n    0x00000000, 0xC161FFFE, 0x5955FFFE, 0x14140000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0xC000490E, 0xCA0000F8, 0xC000492A, 0xCA4000F8, 0xC000496A, 0xCB0000F8, 0xC0004956, 0xCAC000F8,\n    0x00000000, 0xC121FFFE, 0x5911FE54, 0x14100000, 0x77218000, 0x77258000, 0x8400021A, 0xC201FFFE,\n    0x77218000, 0x5AEC0002, 0x6B2D0010, 0x5EA00000, 0x8400001A, 0x6A2D0000, 0x80000010, 0xC72000F8,\n    0x62016008, 0xC0004956, 0xCEC000F8, 0xC161FFFE, 0x5955FFFE, 0x14140000, 0x00000000, 0x00000000,\n    0x00000000, 0x00000000, 0xC000496A, 0xCA4000F8, 0xC2000002, 0x6A2D0000, 0x7E010000, 0x76612000,\n    0xCE4000F8, 0x00000000, 0xC121FFFE, 0x5911FE54, 0x14100000, 0x6EF4A000, 0x6ED44000, 0x4755A000,\n    0x476DA000, 0x5B747000, 0x5834000E, 0xC2000000, 0xCA0000D8, 0x58340008, 0xC2400000, 0xCA420078,\n    0x5834000C, 0xC2800000, 0xCA832010, 0x6E644010, 0x42250000, 0x4229E000, 0xC39A8008, 0x58340008,\n    0xCB809018, 0x58340008, 0xC2800000, 0xCA810010, 0x6EE0A000, 0x6EE44000, 0x46250000, 0x462D0000,\n    0x5A200008, 0x5A203008, 0x42290000, 0xC6380060, 0xC6F81C18, 0x99007F18, 0xDB9800F8, 0xDBD800F9,\n    0x00000000, 0xC000495A, 0xC84000F8, 0x00000000, 0xC3C00002, 0x787C2000, 0xCC4000F8, 0xC0001A1C,\n    0xCA0000F8, 0xC2400008, 0x6A452000, 0x76250000, 0x84000E9A, 0xC0000A28, 0xC3800000, 0xCB840028,\n    0xC0000A14, 0xC3400000, 0xCB440028, 0xC0004880, 0xCB0400F8, 0x47B48000, 0x88000E48, 0x58041802,\n    0xCAC000F8, 0xA7000060, 0x00000000, 0x00000000, 0xA6C8C5C8, 0xC2800000, 0xC6E80018, 0x80000070,\n    0x00000000, 0x00000000, 0x00000000, 0x8000C590, 0x00000000, 0xC2800000, 0xC7282018, 0xC000490E,\n    0xCA4000F8, 0x6BE9E000, 0x00000000, 0x767D2000, 0x8400C548, 0x6EA0A000, 0x6E944000, 0x46150000,\n    0x46290000, 0x5A207000, 0x5820000C, 0xCA0000F8, 0xC0004946, 0xCE8000F8, 0xA6220398, 0x00000000,\n    0xC2200060, 0xC0004948, 0xCE000008, 0xCE021038, 0xC240000A, 0xC000494A, 0xCE4000F8, 0xC2B60002,\n    0xC0004964, 0xCE837B00, 0x990081E8, 0xC00048A0, 0xC88400F8, 0x00000000, 0xC0004946, 0xCBC000F8,\n    0x00000000, 0x00000000, 0x6FF8A000, 0x6FD44000, 0x4795C000, 0x47BDC000, 0x5BB87000, 0x99007FA8,\n    0xDBD800F8, 0xDB9800F9, 0x00000000, 0x99007CF0, 0xC000491C, 0xC1400000, 0xC9420048, 0xC000491C,\n    0x990081A0, 0xC94000F9, 0xC98000F8, 0x00000000, 0x99007F18, 0xD95800F8, 0xD99800F9, 0x00000000,\n    0xC161FFFE, 0x5955FFFE, 0x14140000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x99007BE0,\n    0xDBD800F8, 0xDB9800F9, 0xC7D800F8, 0x00000000, 0xC121FFFE, 0x5911FE54, 0x14100000, 0x6FF8A000,\n    0x6FD44000, 0x4795C000, 0x47BDC000, 0x5BB87000, 0x58380010, 0xCA0000F8, 0xC0004874, 0xC80400F8,\n    0x6C908000, 0x45088000, 0x45088000, 0x40100000, 0xCA4000F8, 0xC43400F8, 0x00000000, 0xC74000F8,\n    0xCE0000F8, 0xC161FFFE, 0x5955FFFE, 0x14140000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0xC000490E, 0xCA4000F8, 0xC2800002, 0x6ABD4000, 0x72692000, 0xCE4000F8, 0x00000000, 0xC121FFFE,\n    0x5911FE54, 0x14100000, 0x99008690, 0xC0004836, 0xC94000F8, 0xC1800002, 0x00000000, 0x00000000,\n    0x00000000, 0xA8E2FFE8, 0x00000000, 0xC1220002, 0xD90C00F8, 0xC2000000, 0xC0000A14, 0xCA040028,\n    0xC0000A28, 0xC2500002, 0xCE450800, 0x58880002, 0xB6080018, 0xC00048A0, 0xC0800000, 0xCC8400F8,\n    0x8000C168, 0xC0004946, 0xCBC000F8, 0xC161FFFE, 0x5955FFFE, 0x14140000, 0x00000000, 0x00000000,\n    0x00000000, 0x00000000, 0xC000490E, 0xCA4000F8, 0xC2800002, 0x6ABD4000, 0x72692000, 0xCE4000F8,\n    0x00000000, 0xC121FFFE, 0x5911FE54, 0x14100000, 0x6FF8A000, 0x6FD44000, 0x4795C000, 0x47BDC000,\n    0x5BB87000, 0x58380008, 0xCA0000F8, 0x5838000C, 0xCA4000F8, 0xC3400000, 0xC6340000, 0xC000494E,\n    0xCF4000F8, 0xC2800000, 0xC62A0078, 0xC3000000, 0xC6308018, 0x6F304000, 0x43298000, 0xC000493C,\n    0xCF0000F8, 0xC2C00000, 0xC66C0078, 0xC0004950, 0xCEC000F8, 0xC2800000, 0xC66AE020, 0xC0004954,\n    0xCE8000F8, 0x5F740000, 0x840001B8, 0x5E300028, 0x46E12000, 0x84000182, 0x46E12000, 0x8800014A,\n    0x5E300018, 0x46E12000, 0x8800002A, 0x46E12000, 0x84000042, 0x00000000, 0x800000D8, 0x00000000,\n    0x99008328, 0xDBD800F8, 0xDB9800F9, 0xC78000F8, 0xC3400002, 0xC000494E, 0xCF4000F8, 0xC161FFFE,\n    0x5955FFFE, 0x14140000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xC000490E, 0xCA4000F8,\n    0xC2800002, 0x6ABD4000, 0x7E814000, 0x76692000, 0xCE4000F8, 0x00000000, 0xC121FFFE, 0x5911FE54,\n    0x14100000, 0xC2200060, 0xC0004948, 0xCE021038, 0xC2000000, 0xC000494C, 0xCE0000F8, 0x80000080,\n    0x00000000, 0x99008328, 0xDBD800F8, 0xDB9800F9, 0xC78000F8, 0x99008528, 0xDBD800F8, 0xDB9800F9,\n    0xC78000F8, 0xC2200058, 0xC0004948, 0xCE021038, 0xC2000002, 0xC000494C, 0xCE0000F8, 0xC2000006,\n    0xC0001006, 0xCE0000F8, 0x5838000A, 0xCA4000F8, 0xC2200982, 0x5A203B6E, 0xC0001008, 0xCE0000F8,\n    0xC000100A, 0xCE4000F8, 0xC0004954, 0xCA8000F8, 0xC200000C, 0xC000494A, 0xCE0000F8, 0xC0004948,\n    0xCE800008, 0xC2B60000, 0xC0004964, 0xCE8000F8, 0x990081E8, 0xC00048A0, 0xC88400F8, 0x00000000,\n    0xC0004946, 0xCBC000F8, 0xC000494C, 0xCA0000F8, 0x6FF8A000, 0x6FD44000, 0x4795C000, 0x47BDC000,\n    0x5BB87000, 0x5E200000, 0x84000112, 0x00000000, 0x99007FA8, 0xDBD800F8, 0xDB9800F9, 0x00000000,\n    0x99007CF0, 0xC000491C, 0xC1400000, 0xC9420048, 0xC000491C, 0x990081A0, 0xC94000F9, 0xC98000F8,\n    0x00000000, 0x99007F18, 0xD95800F8, 0xD99800F9, 0x00000000, 0xC161FFFE, 0x5955FFFE, 0x14140000,\n    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x99007BE0, 0xDBD800F8, 0xDB9800F9, 0xC7D800F8,\n    0x00000000, 0xC121FFFE, 0x5911FE54, 0x14100000, 0xC000493C, 0xCA8000F8, 0xC000494E, 0xCAC000F8,\n    0xC3000018, 0xC3400006, 0x5E200000, 0x8400002A, 0xC2800000, 0xC2C00000, 0xC300001E, 0xC3400000,\n    0xC6AC1078, 0xC72C0418, 0xC76C0810, 0x58380010, 0xCA8000F8, 0x58380008, 0xCEC000F8, 0xC6280100,\n    0xC0004874, 0xC80400F8, 0x6C908000, 0x45088000, 0x45088000, 0x40100000, 0xCB0000F8, 0xC43400F8,\n    0x00000000, 0xC74000F8, 0xCE8000F8, 0xC0004952, 0xCE8000F8, 0x00000000, 0x00000000, 0x00000000,\n    0xA8E2FFE8, 0x00000000, 0xC000494C, 0xCA0000F8, 0xC0004950, 0xCAC000F8, 0x5E200000, 0x8400006A,\n    0xDFE800F8, 0x7E814000, 0x5834001A, 0xCE8000F8, 0x99008690, 0xC0004834, 0xC94000F8, 0xC1800002,\n    0x99008690, 0xC0004838, 0xC94000F8, 0xC6D800F8, 0xC1220002, 0xD90C00F8, 0x5E200000, 0x84000040,\n    0x5838002C, 0xCB0000F8, 0xDFE800F8, 0x00000000, 0x58380014, 0xCF0000F8, 0x80000018, 0xC2A1FFFE,\n    0x5AA9FFFE, 0x5838000A, 0xCE8000F8, 0xC3000000, 0xC0000A14, 0xCB040028, 0xC2D00002, 0xC0000A28,\n    0xCEC50800, 0xC000494E, 0xCA8000F8, 0x58880002, 0xB4B00018, 0xC00048A0, 0xC0800000, 0xCC8400F8,\n    0x5EA80000, 0x8400016A, 0x5E200000, 0x84000158, 0xC000493C, 0xCA8000F8, 0x00000000, 0x00000000,\n    0x5AA80060, 0xCE8000F8, 0x99008328, 0xDBD800F8, 0xDB9800F9, 0xC78000F8, 0x99008528, 0xDBD800F8,\n    0xDB9800F9, 0xC78000F8, 0xC0004952, 0xCAC000F8, 0x58380000, 0xCA8000F8, 0xC30C0002, 0xC7F00018,\n    0xA68000B0, 0x00000000, 0x00000000, 0xC161FFFE, 0x5955FFFE, 0x14140000, 0x00000000, 0x00000000,\n    0x00000000, 0x00000000, 0xC0001800, 0xCA0000F8, 0x00000000, 0x00000000, 0xA60CFFEA, 0xC6F00500,\n    0xC6B0C400, 0xCF0000F8, 0x00000000, 0xC121FFFE, 0x5911FE54, 0x14100000, 0x8000B7B8, 0x00000000,\n    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0x00000000, 0x00000000, 0x00000000, 0x8000B750, 0xDCBC00F9, 0x5FFC0000, 0x8400095A, 0xC3800002,\n    0xDB8800F9, 0xC3800000, 0xDB8800F9, 0xC0004728, 0xC90000F8, 0x00000000, 0x00000000, 0x59100002,\n    0xCD0000F8, 0xC0004730, 0xC98000F8, 0xC000472E, 0xC94000F8, 0xC00047DC, 0xC90000F8, 0xC00047DE,\n    0xC9C000F8, 0xC000472E, 0xCD8000F8, 0x6D110000, 0xC5D30038, 0xC00047DC, 0xCD0000F8, 0x4594A000,\n    0x6DDD0000, 0xC55C0038, 0xC00047DE, 0xCDC000F8, 0xC0001AC4, 0xC94000F8, 0xC0001AC8, 0xC98000F8,\n    0xC000472C, 0xC9C000F8, 0x45948000, 0xC1000002, 0x41D0E004, 0xCDC000F8, 0xC5501078, 0xC5900078,\n    0xC000472A, 0xCD0000F8, 0xC0001AF0, 0xCBC000F8, 0x58000002, 0xCB8000F8, 0xC3400000, 0xC7F50038,\n    0x6F702000, 0x5B304300, 0xC000474C, 0xCAC000F8, 0xC0004720, 0xC94000F8, 0x00000000, 0x00000000,\n    0x5D940002, 0x6D9B8000, 0x6D9B8010, 0x581847E0, 0xC98000F8, 0x581447E0, 0xC9C000F8, 0x5D2C0000,\n    0x8400007A, 0xC7901078, 0xC7D00078, 0xCD0000F8, 0xC1000000, 0xC5910038, 0x45348000, 0x84000090,\n    0xC0004722, 0xC90000F8, 0x00000000, 0x00000000, 0x59100002, 0xCD0000F8, 0x80000058, 0xC1000000,\n    0xC5D10038, 0x45348000, 0x8400003A, 0xC0004724, 0xC90000F8, 0x00000000, 0x00000000, 0x59100002,\n    0xCD0000F8, 0xA7840080, 0x59540002, 0x6D578000, 0x6D578010, 0xC0004720, 0xCD4000F8, 0xC1000000,\n    0xC5910038, 0x45348000, 0x84000038, 0xC0004726, 0xC90000F8, 0x00000000, 0x00000000, 0x59100002,\n    0xCD0000F8, 0xA78000B8, 0xC2800002, 0xC000474E, 0xCE8000F8, 0xC2C00000, 0xC000474C, 0xCEC000F8,\n    0xC0004758, 0xCFC000F8, 0x58000002, 0xCF8000F8, 0xC000475C, 0xC90000F8, 0x00000000, 0x00000000,\n    0xA53E003A, 0x00000000, 0xC13E0002, 0xCFC000F8, 0xCD03DE08, 0x58000002, 0xCF8000F8, 0x800001A0,\n    0xC000475C, 0xC13C0002, 0xCD03DE08, 0x5D2C0000, 0x8400017A, 0xC2C00000, 0xC000474C, 0xCEC000F8,\n    0x98C08AF0, 0xC75400F8, 0xC0004740, 0xC9C000F8, 0x5D240000, 0x84000042, 0xC1000002, 0xC0004750,\n    0xCD0000F8, 0xC0004752, 0xCD0000F8, 0x80000100, 0x00000000, 0x98C08BE0, 0xC75400F8, 0xC0004742,\n    0xC98000F8, 0x5D240000, 0x8400002A, 0xC1000002, 0xC0004752, 0xCD0000F8, 0x80000060, 0xC0004742,\n    0xC94000F8, 0xC0004754, 0xC1000002, 0xCD0000F8, 0x98C08CF0, 0xC55400F8, 0xC75800F8, 0x00000000,\n    0xC0004742, 0xCF4000F8, 0x98C08AB8, 0xC1400000, 0xC7540020, 0x6F40A010, 0xC1000000, 0xC7D00038,\n    0x58300000, 0x6D110000, 0xCD010838, 0xA7840398, 0xC000474C, 0xCAC000F8, 0xC000474E, 0xCA8000F8,\n    0xC0004750, 0xCBC000F8, 0xC0004752, 0xCB8000F8, 0xC0004710, 0xC90000F8, 0x00000000, 0x00000000,\n    0x59100002, 0xCD0000F8, 0x5D280002, 0x840000B8, 0xC000473C, 0xC90000F8, 0x00000000, 0x00000000,\n    0x59100002, 0xCD0000F8, 0xC0004712, 0xC90000F8, 0x00000000, 0x00000000, 0x59100002, 0xCD0000F8,\n    0xC0004754, 0xC90000F8, 0x00000000, 0x00000000, 0x5D100000, 0x8400021A, 0x58300000, 0xC13C0002,\n    0xCD03DE00, 0x800001F8, 0xC0004714, 0xC90000F8, 0x00000000, 0x00000000, 0x59100002, 0xCD0000F8,\n    0x5D380000, 0x8400003A, 0xC0004736, 0xC90000F8, 0x00000000, 0x00000000, 0x59100002, 0xCD0000F8,\n    0x5D3C0000, 0x84000042, 0xC0004718, 0xC90000F8, 0x00000000, 0x00000000, 0x59100002, 0xCD0000F8,\n    0x80000140, 0xC1000000, 0x58300000, 0xC903E000, 0x00000000, 0x00000000, 0x5D100000, 0x84000042,\n    0xC000471A, 0xC90000F8, 0x00000000, 0x00000000, 0x59100002, 0xCD0000F8, 0x800000D0, 0x58300000,\n    0xC13E0002, 0xCD03FF00, 0xC1000000, 0x58300000, 0xC903C000, 0x00000000, 0x00000000, 0x5D100000,\n    0x84000082, 0xC0004716, 0xC90000F8, 0x00000000, 0x00000000, 0x59100002, 0xCD0000F8, 0xC000473A,\n    0xC90000F8, 0x00000000, 0x00000000, 0x59100002, 0xCD0000F8, 0x58300000, 0xC13C0000, 0xCD03DE00,\n    0xC1000000, 0xC0004746, 0xCD0000F8, 0xC0004750, 0xCD0000F8, 0xC0004752, 0xCD0000F8, 0xC000474E,\n    0xCD0000F8, 0xC2C00002, 0xC000474C, 0xCEC000F8, 0xC0004754, 0xCD0000F8, 0xC3CE0002, 0xC0000800,\n    0xCFC0E700, 0xC3E1FFFE, 0x597DFFFE, 0x593DFE14, 0x94000001, 0x00000000, 0x00000000, 0x00000000,\n    0xC000487C, 0xC80400F8, 0x00000000, 0x00000000, 0x40080000, 0xCBC000F8, 0xC43800F8, 0x00000000,\n    0xC000480E, 0xCA0000F8, 0xC0004858, 0xCB4400F8, 0x00000000, 0x00000000, 0x47610000, 0x880000B0,\n    0x00000000, 0xA7C00048, 0xC0004854, 0xC1000002, 0xCD0400F8, 0xC11C0000, 0xC000082C, 0xCD05CE00,\n    0x800000D8, 0x00000000, 0xA7D20138, 0x00000000, 0xC7E14040, 0xC2400000, 0xC6246028, 0xC200006A,\n    0x46250000, 0xC6240030, 0xC0000810, 0xCE440030, 0x8000FF70, 0xC2000000, 0xC0000808, 0xCA040010,\n    0xC11C0000, 0xC000082C, 0xCD05CE00, 0x5A200002, 0x5E600010, 0x84000010, 0xC2000000, 0xC0000808,\n    0xCE040010, 0xC3400000, 0x80000028, 0xC1200002, 0xC0000818, 0xCD061000, 0x5B740002, 0xC0004858,\n    0xCF4400F8, 0x99007930, 0xC0004848, 0xC94400F8, 0xC1800000, 0xC11C0002, 0xC000082C, 0xCD05CE00,\n    0x80000878, 0x5B740002, 0xC0004858, 0xCF4400F8, 0xC78000F8, 0xC13C0002, 0xCD03DE00, 0xC0004848,\n    0xC94400F8, 0xC1800000, 0xC000082C, 0xC9840028, 0x59540002, 0xC0004848, 0xCD4400F8, 0x58880002,\n    0xB49807F8, 0x00000000, 0xC0800000, 0x800007E0, 0xC000487C, 0xC80400F8, 0x00000000, 0x00000000,\n    0x40080000, 0xCBC000F8, 0xC42800F8, 0x00000000, 0xA7C00130, 0xC000484C, 0xCA0400F8, 0xC2400000,\n    0xC0001AEC, 0xCA440018, 0x5A200002, 0xC000484C, 0xCE0400F8, 0xB624008A, 0xC68000F8, 0xC13C0002,\n    0xCD03DE00, 0xC0004848, 0xC94400F8, 0xC1800000, 0xC000082C, 0xC9840028, 0x59540002, 0xC0004848,\n    0xCD4400F8, 0x58880002, 0xB49806E8, 0x00000000, 0xC0800000, 0x800006D0, 0xC0004854, 0xC1000004,\n    0xCD0400F8, 0xC0000820, 0xC2000002, 0xCE0400F8, 0xC2000000, 0xC000484C, 0xCE0400F8, 0xC0004858,\n    0xCE0400F8, 0x8000FF28, 0xC0004854, 0xC1000000, 0xCD0400F8, 0xC11C0000, 0xC000082C, 0xCD05CE00,\n    0x99007930, 0xC0004848, 0xC94400F8, 0xC1800000, 0xC1200000, 0xC0000818, 0xCD061000, 0xC11C0002,\n    0xC000082C, 0xCD05CE00, 0xC2000000, 0xC000484C, 0xCE0400F8, 0x800005D0, 0xC0001AC0, 0xCB8400F8,\n    0xC000487C, 0xC80400F8, 0x00000000, 0x00000000, 0x40080000, 0xCBC000F8, 0xC42800F8, 0x00000000,\n    0xA78004E2, 0x00000000, 0x00000000, 0xA7C004A2, 0x00000000, 0xC0001B00, 0xC2060006, 0xCE046308,\n    0xA7E8045A, 0x00000000, 0xC0004850, 0xCA0400F8, 0xC2400000, 0xC0004812, 0xCA420078, 0x5A200002,\n    0xC0004850, 0xCE0400F8, 0x5E640000, 0x8400001A, 0x46250000, 0x880002F8, 0xC68000F8, 0xC13C0002,\n    0xCD03DE00, 0xC0001ACC, 0xC2000002, 0xCE040000, 0x5C440000, 0x84000250, 0xC0004810, 0xC94000F8,\n    0xC68000F8, 0xCBC000F8, 0x00000000, 0xC1000000, 0xA5400208, 0xC53C1000, 0x00000000, 0xA7FC01F2,\n    0xC0001AF0, 0xC1000000, 0x58000002, 0xC9000000, 0xC000474E, 0xC98000F8, 0x5D100000, 0x84000022,\n    0xC1000002, 0xC53C1E00, 0x80000198, 0x5D180000, 0x84000022, 0xC1000002, 0xC53C1E00, 0x80000170,\n    0xC0004878, 0xC80400F8, 0x6C908000, 0x45088000, 0x45088000, 0x40100000, 0xC98000F8, 0xC43800F8,\n    0x00000000, 0xC000481E, 0xC9C000F8, 0xC000481C, 0xCA0000F8, 0x00000000, 0x759CC000, 0x45A08000,\n    0x840000E8, 0xC0001AF0, 0xC3400000, 0x58000000, 0xCB410038, 0xC0004746, 0xC94000F8, 0x6F702000,\n    0x5B304300, 0xC2C00000, 0x58300000, 0xCAC00038, 0x00000000, 0x00000000, 0x456C8000, 0x88000020,\n    0xC1000002, 0xC53C1E00, 0x80000040, 0x5AEC0002, 0x58300000, 0xCEC00038, 0xC1000002, 0xC53C1000,\n    0xC77C0838, 0xC57C0038, 0x59540002, 0xC0004746, 0xCD4000F8, 0xC68000F8, 0xCFC000F8, 0xC0004848,\n    0xC94400F8, 0xC1800000, 0xC000082C, 0xC9840028, 0x59540002, 0xC0004848, 0xCD4400F8, 0x58880002,\n    0xB49801F8, 0x00000000, 0xC0800000, 0x800001E0, 0xC000471E, 0xC90000F8, 0x00000000, 0x00000000,\n    0x59100002, 0xCD0000F8, 0xC0004854, 0xC1000000, 0xCD0400F8, 0xC11C0000, 0xC000082C, 0xCD05CE00,\n    0x99007930, 0xC0004848, 0xC94400F8, 0xC1800000, 0xC2000000, 0xC0000820, 0xCE0400F8, 0xC1200000,\n    0xC0000818, 0xCD061000, 0xC11C0002, 0xC000082C, 0xCD05CE00, 0xC0004850, 0xCE0400F8, 0xC2000002,\n    0xC0001ACC, 0xCE040008, 0x800000E8, 0xC2000002, 0xC0004850, 0xCE0400F8, 0x8000FC00, 0xC2000000,\n    0xC0004850, 0xCE0400F8, 0xA7E60032, 0x00000000, 0xC2000002, 0xC0001B00, 0xCE040000, 0x8000FBE8,\n    0x00000000, 0xA7860052, 0x00000000, 0xC68000F8, 0xC13C0002, 0xCD03DE00, 0xC2020002, 0xC7E2A540,\n    0xC0001B00, 0xCE0400F8, 0x8000FB90, 0xC2040002, 0xC0001B00, 0xCE044200, 0x8000FB70, 0xC2C80002,\n    0x6AC56000, 0xDACC00F8, 0xC0004854, 0xCB4400F8, 0xC0004848, 0xCB8400F8, 0xC0000838, 0xC3C00000,\n    0xCBC40028, 0x5EF40004, 0x84000022, 0xC3000000, 0xC0001ACC, 0xCF042100, 0x47F98000, 0x8400004A,\n    0x47F98000, 0x88000050, 0xC1006E8C, 0xC1400010, 0x8D580000, 0x00000000, 0x00000000, 0x00000000,\n    0xC0004840, 0xCC8400F8, 0x8000EB10, 0xC0001AC0, 0xCAC400F8, 0xC0004854, 0xCB4400F8, 0xA6C0F93A,\n    0x00000000, 0x5EF40000, 0x8400F472, 0x5EF40002, 0x8400F702, 0x5EF40004, 0x8400F902, 0xC1006CE8,\n    0xC1400010, 0x8D580000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xC0800000, 0xDF4B0038,\n    0xC0004900, 0xCB8000F8, 0xC2000000, 0xC000490A, 0xA78000D0, 0xCBC000F8, 0xC1000000, 0xD90000F9,\n    0xC1000002, 0xD90C00F8, 0x6FF46000, 0x477DA000, 0x5B744C80, 0xC2400000, 0x58340004, 0xCA400078,\n    0xC0004900, 0xCE000000, 0x5A640002, 0x58340004, 0xC6500078, 0xCD000078, 0xC0004914, 0xCA4000F8,\n    0xC2000002, 0x6A3D0000, 0x72612000, 0xCE4000F8, 0xC0000408, 0xCE0000F8, 0xA78200D8, 0xC0004908,\n    0xCBC000F8, 0xC1000000, 0xD90000F9, 0xC1000002, 0xD90C00F8, 0x6FF4A000, 0x6FD44000, 0x4755A000,\n    0x477DA000, 0x5B747000, 0xC2800000, 0x58340006, 0xCA800078, 0xC2000000, 0xC0004900, 0xCE002100,\n    0x5EA80002, 0x58340006, 0xC6900078, 0xCD000078, 0x5A7C0020, 0xC2000002, 0x6A250000, 0xC0000408,\n    0xCE0000F8, 0xC0000032, 0xDCA800F9, 0xC1000002, 0x45294000, 0x00000000, 0x8C100006, 0x00000000,\n    0x00000000, 0x00000000, 0xA4800230, 0x00000000, 0xC3C00000, 0xC000140E, 0xCBC00018, 0xC3400000,\n    0xC2400000, 0x6FF86000, 0x47BDC000, 0x5BB84C80, 0x58380008, 0xCB400078, 0x58380006, 0xCA400078,\n    0x5F740002, 0x58380008, 0xC7500078, 0xCD000078, 0xC2000000, 0x58380004, 0xCA020078, 0xC3000000,\n    0x5838000C, 0xCB000020, 0x5A640002, 0x46610000, 0x84000010, 0xC2400000, 0x58380006, 0xC6500078,\n    0xCD000078, 0xC2000000, 0x5838000A, 0xCA020078, 0x5B300002, 0x5838000C, 0xC7100020, 0xCD000020,\n    0xC2420020, 0x5A200004, 0x46252000, 0x84000010, 0xC2000000, 0x5838000A, 0xC6101078, 0xCD021078,\n    0xC0004966, 0xCA4000F8, 0xC2000002, 0x6A3D0000, 0x72612000, 0xCE4000F8, 0x5F740000, 0x84000040,\n    0xC0004912, 0xCA0000F8, 0xC2C00002, 0x6AFD6000, 0x7EC16000, 0x762D0000, 0xCE0000F8, 0x5F300020,\n    0x84000040, 0xC0004924, 0xCA0000F8, 0xC2C00002, 0x6AFD6000, 0x7EC16000, 0x762D0000, 0xCE0000F8,\n    0xA4820070, 0xC2400000, 0xC000140E, 0xCA408018, 0xC2000002, 0xC0004900, 0xCE000000, 0xC000490A,\n    0xCE4000F8, 0xC1000000, 0xD90000F9, 0xD8400078, 0xC1000004, 0xD90000F9, 0xA48402A8, 0x00000000,\n    0xC3C00000, 0xC000140E, 0xCBC10018, 0xC2800000, 0xC2000000, 0x6FF8A000, 0x6FD44000, 0x4795C000,\n    0x47BDC000, 0x5BB87000, 0x5838002E, 0xCA800078, 0x58380006, 0xCA020078, 0xC3400000, 0x5838002E,\n    0xCB420078, 0x5AA80002, 0x46A10000, 0x84000010, 0xC2800000, 0x5838002E, 0xC6900078, 0xCD000078,\n    0x5F740002, 0x5838002E, 0xC7501078, 0xCD021078, 0xC0004968, 0xCA4000F8, 0xC2000002, 0x6A3D0000,\n    0x72612000, 0xCE4000F8, 0xC000492A, 0xCA8000F8, 0x5E740000, 0x84000040, 0xC0004910, 0xCA0000F8,\n    0xC2C00002, 0x6AFD6000, 0x7EC16000, 0x762D0000, 0xCE0000F8, 0x6ABD4010, 0xA68000F2, 0x00000000,\n    0xC0004910, 0xCA0000F8, 0xC2C00002, 0x6AFD6000, 0x7EC16000, 0x762D0000, 0xCE0000F8, 0x58380032,\n    0xCA0000F8, 0x58000002, 0xCA4000F8, 0x5838000C, 0x00000000, 0xCE0000F9, 0xCE4000F8, 0xC000492A,\n    0xCA0000F8, 0xC2C00002, 0x6AFD6000, 0x722D0000, 0xCE0000F8, 0xC000492C, 0xCA0000F8, 0xC2C00002,\n    0x6AFD6000, 0x722D0000, 0xCE0000F8, 0x80000040, 0xC000492C, 0xCA0000F8, 0xC2C00002, 0x6AFD6000,\n    0x7EC16000, 0x762D0000, 0xCE0000F8, 0xA4880120, 0xC2C00000, 0xC000140E, 0xCAC20018, 0xC000490E,\n    0xCA4000F8, 0xC2000002, 0x6A2D0000, 0x7E010000, 0x76612000, 0xCE4000F8, 0xC000496A, 0xCA4000F8,\n    0xC2000002, 0x6A2D0000, 0x72612000, 0xCE4000F8, 0x6EF0A000, 0x6ED44000, 0x47158000, 0x472D8000,\n    0x5B307000, 0x58300000, 0xCA0000F8, 0x00000000, 0xC2400002, 0x76612000, 0x8400004A, 0xC24C0002,\n    0xC6E40018, 0xC624C400, 0x58300010, 0xCA400500, 0x00000000, 0xC0001800, 0xCE4000F8, 0xA4860070,\n    0xC2400000, 0xC000140E, 0xCA418018, 0xC2020002, 0xC0004900, 0xCE002100, 0xC0004908, 0xCE4000F8,\n    0xC1000000, 0xD90000F9, 0xD8400078, 0xC1000004, 0xD90000F9, 0xA48C0048, 0xC2800002, 0xC000484A,\n    0xCE8000F8, 0xC2800000, 0xC000474A, 0xCE8000F8, 0xC0004846, 0xCE8000F8, 0xC0001408, 0xCC8000F8,\n    0xC10E0002, 0xD90C00F8, 0x8000EA78, 0xDFBC00F9, 0xC000496E, 0x99008638, 0xC94000F8, 0xC7D800F8,\n    0x00000000, 0xC57000F8, 0x5EF00020, 0x88000148, 0x6F346000, 0x4771A000, 0x5B744C80, 0x58340008,\n    0xC2400000, 0xCA400078, 0x00000000, 0xC2000000, 0x5A640002, 0xCE400078, 0x58340004, 0xCA000078,\n    0x00000000, 0x00000000, 0x5E200002, 0xCE000078, 0xC0004912, 0xCA8000F8, 0xC2400002, 0x6A712000,\n    0x72A54000, 0xCE8000F8, 0x5E200000, 0x84000052, 0xC000480A, 0xCA0000F8, 0xC0000408, 0xCA8000F8,\n    0x76250000, 0x00000000, 0x72A14000, 0xCE8000F8, 0x80000038, 0xC0004914, 0xCA0000F8, 0x7E412000,\n    0x00000000, 0x76250000, 0xCE0000F8, 0x800000D0, 0x6EF4A000, 0x6ED44000, 0x4755A000, 0x476DA000,\n    0x5B747000, 0x5834002E, 0xC2400000, 0xCA420078, 0x00000000, 0xC2000000, 0x5A640002, 0xC6501078,\n    0xCD021078, 0x58340006, 0xCA000078, 0x00000000, 0x00000000, 0x5A200002, 0xCE000078, 0xC0004910,\n    0xCA4000F8, 0xC2000002, 0x6A2D0000, 0x72612000, 0xCE4000F8, 0xC2000002, 0x6A310000, 0xC000042A,\n    0xCE0000F8, 0xC1040002, 0xD90C00F8, 0x00000000, 0x8000E7E8, 0x00000000, 0xC4980928, 0x9D000000,\n    0xC5580028, 0xC0000838, 0xCD8400F8, 0xC1440200, 0xC1C03800, 0xC55C1070, 0xC000100E, 0x9D000000,\n    0xCD8000F8, 0xC000100C, 0xCDC000F8, 0xC0004862, 0xC9C000F8, 0x00000000, 0x00000000, 0xD9D800F9,\n    0xC0007800, 0x401C0000, 0x5DC07A00, 0x88000012, 0x5C000200, 0xCD8000F8, 0xC1F0000A, 0x715CA000,\n    0xDD9800F8, 0xDD9C00F9, 0x41D8E000, 0xC5D40260, 0xC0001010, 0xCD4000F8, 0x6C9C8000, 0x45C8E000,\n    0x45C8E000, 0x59DC0004, 0xC1601260, 0xC5D40260, 0x9D000000, 0xC0001012, 0xCD4000F8, 0x00000000,\n    0x00000000, 0xD95800F8, 0x6D586000, 0x4594C000, 0x59984C80, 0xD99800F9, 0x5818000A, 0xC1800000,\n    0xC9800078, 0xC0006E00, 0x6D5CA000, 0x401C0000, 0x40180000, 0xC94000F8, 0x58000002, 0x00000000,\n    0xC9C000F8, 0xC0004930, 0xCD4000F8, 0xC0004932, 0xCDC000F8, 0x59980004, 0xC1C20020, 0xB59C0018,\n    0x00000000, 0xC1800000, 0xDD9C00F9, 0x581C000A, 0xCD800078, 0x581C000C, 0xC1800000, 0xC9800020,\n    0xC1C00002, 0xDD9400F8, 0x69D4E000, 0x5D980002, 0xCD800020, 0xC0004924, 0xC98000F8, 0x00000000,\n    0x9D000000, 0x00000000, 0x719CC000, 0xCD8000F8, 0xC000492A, 0xC94000F8, 0xC1C00002, 0x69D8E000,\n    0x7DC0C000, 0x7558A000, 0xCD4000F8, 0xC000492C, 0xC94000F8, 0xDD8000F9, 0x58000032, 0x755CA000,\n    0x84000090, 0xC94000F9, 0xC98000F8, 0xDD8000F9, 0x5800000C, 0x00000000, 0xCD4000F9, 0xCD8000F8,\n    0xC000492C, 0xC94000F8, 0xC000492A, 0xC98000F8, 0x715CA000, 0xC000492C, 0xCD4000F8, 0x719CC000,\n    0xC000492A, 0xCD8000F8, 0x9D000000, 0x00000000, 0x00000000, 0x00000000, 0xC0004862, 0xC98000F8,\n    0x00000000, 0xC1C00200, 0x4194C000, 0x459CE000, 0x88000012, 0xC5D800F8, 0xC0004862, 0xCD8000F8,\n    0xC0001406, 0xC98000F8, 0xC1C00002, 0x9D000000, 0xC5D80A00, 0xC5581048, 0xCD8000F8, 0xC0004930,\n    0xC98000F8, 0xC0004932, 0xC9C000F8, 0xC140000E, 0xC5581C18, 0xDD9400F8, 0xC0007800, 0x40140000,\n    0x5D407A00, 0x88000012, 0x5C000200, 0xCD8000F8, 0x58000002, 0x5D407A00, 0x88000012, 0x5C000200,\n    0xCDC000F8, 0xDD5400F8, 0xC1C00000, 0x58140006, 0xC9C20078, 0xC1800000, 0x58140000, 0xC98000D8,\n    0x6DDC2000, 0xC000491E, 0x41D8E000, 0xCDC000F8, 0xDD9800F8, 0xC1C00022, 0xC5D80D70, 0xDD9400F9,\n    0xC5581C18, 0xC000491C, 0xCD8000F8, 0xDD5400F8, 0xC1C00000, 0x58140006, 0xC9C20078, 0xC1800000,\n    0x58140004, 0xC9820078, 0x00000000, 0x59DC0002, 0x45D8C000, 0x84000010, 0xC1C00000, 0x9D000000,\n    0x58140006, 0xC5D81078, 0xCD821078, 0xC0004860, 0xC94000F8, 0xC1820080, 0xC1D00002, 0x58147700,\n    0xD58000F8, 0x58000002, 0xD58000F9, 0x59540004, 0xB5580018, 0xC0004860, 0xC1400000, 0xCD4000F8,\n    0xDD9800F9, 0x9D000000, 0xDD9400F8, 0xC0001404, 0xCDC10800, 0xC1C00000, 0xC1800200, 0x5D980004,\n    0xDF5D0048, 0x459CA000, 0x8800FFF2, 0xDD8000F9, 0x5800000C, 0x00000000, 0xC94000F9, 0xC98000F8,\n    0xC1C00002, 0xC5D43F00, 0xC5D81E00, 0xC0004862, 0xC9C000F8, 0x00000000, 0x00000000, 0x581C7800,\n    0x5DC07A00, 0x88000012, 0x5C000200, 0xCD4000F8, 0x58000002, 0x5DC07A00, 0x88000012, 0x5C000200,\n    0xCD8000F8, 0xC0004862, 0xC9C000F8, 0x00000000, 0xC15004C0, 0xC5D40060, 0xDD9C00F8, 0xC5D41C18,\n    0xC1C00000, 0xDD8000F9, 0x58000030, 0xC9C00078, 0xDD8000F9, 0x58000002, 0xC98000F8, 0x6DDC2000,\n    0xC000491C, 0x41D8E000, 0xCD4000F9, 0xCDC000F8, 0xDD9400F9, 0xC1C00000, 0x58140030, 0xC9C00078,\n    0xC1800000, 0x58140006, 0xC9820078, 0x00000000, 0x59DC0002, 0x45D8C000, 0x84000010, 0xC1C00000,\n    0x9D000000, 0x58140030, 0xC5D80078, 0xCD800078, 0xC1C00000, 0xDF5C0038, 0x5DDC0080, 0x8400FFEA,\n    0x00000000, 0x9D000000, 0x00000000, 0x00000000, 0x00000000, 0xC160FFFE, 0xC0000A10, 0xC9440060,\n    0xC1A0FFFE, 0x59983008, 0xC000100C, 0xCD4000F8, 0xC000100E, 0xCD8000F8, 0xC0004964, 0xC98000F8,\n    0x00000000, 0xC170000A, 0x7158A000, 0x6C988000, 0x4588C000, 0x4588C000, 0x59980004, 0xC5940270,\n    0xC0001010, 0xCD4000F8, 0xC0004946, 0xC94000F8, 0x00000000, 0x00000000, 0x6D58A000, 0x6D5C4000,\n    0x459CC000, 0x4594C000, 0xC000494A, 0xC94000F8, 0xC0004948, 0xC9C000F8, 0x4194C000, 0xC1400012,\n    0xC55C1818, 0x9D000000, 0xC59C0268, 0xC0001012, 0xCDC000F8, 0xC1400000, 0x58000012, 0xC9410038,\n    0xC0004950, 0xC9C000F8, 0xC55800F8, 0xC5940838, 0xC5581078, 0xD99400F8, 0xC000493C, 0xC94000F8,\n    0xC0004954, 0xC98000F8, 0x59DC00A8, 0x45D4E000, 0x41D8E000, 0x5D5C0030, 0x88000010, 0xC1C00030,\n    0xC1800000, 0xC5D84028, 0xC1400000, 0xC5D40008, 0x5DD40002, 0x84000072, 0x5DD40004, 0x8400009A,\n    0x5DD40006, 0x840000C2, 0x5DD80026, 0x840000EA, 0xDD5400F8, 0xDD8000F9, 0x58000008, 0x40180000,\n    0xCD4000F8, 0x59980002, 0x8000FFC0, 0xDD5400F8, 0xDD8000F9, 0x58000008, 0x40180000, 0xCD4000B8,\n    0x59980002, 0x8000FF88, 0xDD5400F8, 0xDD8000F9, 0x58000008, 0x40180000, 0xCD400078, 0x59980002,\n    0x8000FF50, 0xDD5400F8, 0xDD8000F9, 0x58000008, 0x40180000, 0xCD400038, 0x59980002, 0x8000FF18,\n    0x00000000, 0x9D000000, 0x00000000, 0x00000000, 0x00000000, 0x58000012, 0xC94000F8, 0xC0004954,\n    0xC9C000F8, 0xC0004950, 0xC9400078, 0xDD8000F9, 0x58000028, 0x5D9C0000, 0x84000052, 0x5D9C0002,\n    0x84000052, 0x5D9C0004, 0x8400006A, 0xC55B0038, 0xC55C08B8, 0xCD800039, 0xCDC108B8, 0x80000060,\n    0xCD4000F8, 0x80000050, 0xC55900B8, 0xC55C1838, 0xCD8000B9, 0xCDC31838, 0x80000028, 0xC55A0078,\n    0xC55C1078, 0xCD800079, 0xCDC21078, 0x9D000000, 0x00000000, 0x00000000, 0x00000000, 0x59540002,\n    0x6994E018, 0x61C0C008, 0x4194A000, 0x5D940040, 0x88000012, 0xC59400F8, 0x9D000000, 0xCD4000F8,\n    0x00000000, 0x00000000, 0x9D000000, 0x4158A000, 0xCD4000F8, 0x00000000, 0xCD8000F9, 0x45408000,\n    0x8800FFF0, 0x00000000, 0x9CC00000, 0x00000000, 0x00000000, 0x00000000, 0xC0004810, 0xCA010038,\n    0xC241FFFE, 0xC1400000, 0x46148000, 0x00000000, 0x9CC00006, 0xC0004200, 0x40180000, 0xC9C000F8,\n    0x00000000, 0x00000000, 0x61C08010, 0x8400005A, 0xC2400002, 0x6A512000, 0x71E4E000, 0xCDC000F8,\n    0xC0004748, 0xCD8000F8, 0x9CC00000, 0x6D98A000, 0x5998003E, 0x45912000, 0x59540002, 0x59980002,\n    0x46188000, 0xC1000000, 0xC51800FE, 0x8000FF38, 0x00000000, 0x40180000, 0xC9C000F8, 0xC2000000,\n    0xC5600020, 0xC1210000, 0x69208010, 0x7D008000, 0x75D0E000, 0xCDC000F8, 0x6D542000, 0x58144300,\n    0xC1000000, 0xCD0000F9, 0x9CC00000, 0xC121FFFE, 0x5911FFFE, 0xCD0000F9, 0x79588000, 0x6D10A010,\n    0x5D100000, 0x840000C0, 0x45948000, 0x880000B0, 0x6D536000, 0x6D136010, 0x6D54A010, 0xC0004700,\n    0x40140000, 0xCA0000F8, 0x00000000, 0x00000000, 0x6A110000, 0x6A110010, 0x62008018, 0x84000032,\n    0x00000000, 0x9CC00000, 0x6D54A000, 0x5954003E, 0x45512000, 0x59540002, 0x6D57A000, 0x6D57A010,\n    0x6D54A000, 0x6D936000, 0x6D136010, 0xC1E10000, 0x69D0E010, 0x5DDC0002, 0x7DC0E000, 0x6D98A010,\n    0x6D536000, 0x6D136010, 0x6D54A010, 0xC0004700, 0x40140000, 0xCA0000F8, 0x00000000, 0x00000000,\n    0x6A110000, 0x6A110010, 0x45588000, 0x00000000, 0x761D0002, 0x62008018, 0x84000032, 0x00000000,\n    0x9CC00000, 0x6D54A000, 0x5954003E, 0x45512000, 0x45588000, 0x00000000, 0x9CC00002, 0x59540002,\n    0x6D57A000, 0x6D57A010, 0xC0004700, 0x40140000, 0xCA0000F8, 0x8000FF68, 0x00000000, 0x00000000,\n    0x00000000, 0x58004700, 0xC98000F8, 0x9CC00000, 0x00000000, 0x6994C000, 0x6DA7E010, 0x58004700,\n    0xC98000F8, 0xC1210000, 0x9CC00000, 0x69148010, 0x7190C000, 0xCD8000F8, 0xC1000000, 0xC0004810,\n    0xC9020038, 0x00000000, 0x00000000, 0x45D0C000, 0x88000062, 0xC2400002, 0x45588000, 0xC1000000,\n    0xC52400FC, 0x45D48000, 0xC1000000, 0xC52400FE, 0x9CC00000, 0x00000000, 0x00000000, 0x00000000,\n    0x59980200, 0xC2400000, 0x455C8000, 0xC1000002, 0xC52400FC, 0x45948000, 0xC1000002, 0xC52400FE,\n    0x9CC00000, 0x00000000, 0x00000000, 0x00000000, 0xC0004740, 0xC9C000F8, 0x59180002, 0x6D130000,\n    0x6D130010, 0x451C8000, 0xC2400000, 0x9CC00002, 0x00000000, 0x00000000, 0x459C8000, 0x88000062,\n    0xC2400002, 0x455C8000, 0xC1000000, 0xC52400FC, 0x45948000, 0xC1000000, 0xC52400FC, 0x9CC00000,\n    0x00000000, 0x00000000, 0x00000000, 0xC2400000, 0x45588000, 0xC1000002, 0xC52400FE, 0x45D48000,\n    0xC1000002, 0xC52400FE, 0x9CC00000, 0x00000000, 0x00000000, 0x00000000, 0x59540002, 0x6D570000,\n    0x6D570010, 0x45588000, 0x6D402000, 0x9CC00002, 0x58004300, 0x58000000, 0xC13C0002, 0xCD03DE00,\n    0x8000FFB0, 0x00000000, 0x00000000, 0x00000000, 0xC1020002, 0xD90C00F8, 0xC98000F8, 0x59540002,\n    0xC0004730, 0xCD4000F8, 0x5D980002, 0x00000000, 0x80000036, 0x00000000, 0x9CC00000, 0xC0004732,\n    0xCD8000F8, 0x00000000, 0xC0004734, 0xC9C000F8, 0xC1800000, 0xC0004816, 0xC9820078, 0xC0004738,\n    0xCDC000F8, 0xC1C00000, 0xC0004734, 0x9CC00000, 0xCDC000F8, 0xC0004732, 0xCD8000F8,\n};\n\nstatic unsigned int firmware_binary_data[] = {\n};\n\n\n#endif  //  IFXMIPS_ATM_FW_AR9_H\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-atm/src/ifxmips_atm_fw_danube.h",
    "content": "#ifndef IFXMIPS_ATM_FW_DANUBE_H\n#define IFXMIPS_ATM_FW_DANUBE_H\n\n\n/******************************************************************************\n**\n** FILE NAME    : ifxmips_atm_fw_danube.h\n** PROJECT      : Danube\n** MODULES     \t: ATM (ADSL)\n**\n** DATE         : 1 AUG 2005\n** AUTHOR       : Xu Liang\n** DESCRIPTION  : ATM Driver (PP32 Firmware)\n** COPYRIGHT    : \tCopyright (c) 2006\n**\t\t\tInfineon Technologies AG\n**\t\t\tAm Campeon 1-12, 85579 Neubiberg, Germany\n**\n**    This program is free software; you can redistribute it and/or modify\n**    it under the terms of the GNU General Public License as published by\n**    the Free Software Foundation; either version 2 of the License, or\n**    (at your option) any later version.\n**\n** HISTORY\n** $Date        $Author         $Comment\n**  4 AUG 2005  Xu Liang        Initiate Version\n** 23 OCT 2006  Xu Liang        Add GPL header.\n*******************************************************************************/\n\n\n#define VER_IN_FIRMWARE         1\n\n#define ATM_FW_VER_MAJOR        0\n#define ATM_FW_VER_MINOR        17\n//  fix 1 upstream packet stuck in TX queue issue\n//  add multiple queue per PVC feature\n\n\nstatic unsigned int danube_fw_bin[] = {\n    0x800004A0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x8000FFC8, 0x00000000, 0x00000000, 0x00000000,\n    0xC1000002, 0xD90C0000, 0xC2000002, 0xDA080001, 0x80004968, 0xC2000000, 0xDA080001, 0x80003FD0,\n    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0x80003F88, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0x80005160, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0x80003E88, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0xC0400000, 0xC0004840, 0xC8840000, 0x80004628, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0xC0400002, 0xC0004840, 0xC8840000, 0x800045A8, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0xC3C00004, 0xDBC80001, 0xC10C0002, 0xD90C0000, 0x8000FEC8, 0x00000000, 0x00000000, 0x00000000,\n    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0xC10E0002, 0xD90C0000, 0xC0004808, 0xC8400000, 0x800045D8, 0x00000000, 0x00000000, 0x00000000,\n    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0xC3E1FFFE, 0x597DFFFE, 0x593DFE14, 0x900004D9, 0x00000000, 0x00000000, 0x00000000, 0x90CC0481,\n    0x00000000, 0x00000000, 0x00000000, 0xC3C00000, 0xDBC80001, 0xC1400008, 0xC1900000, 0x71948000,\n    0x15000100, 0xC140000A, 0xC1900002, 0x71948000, 0x15000100, 0xC140000C, 0xC1900004, 0x71948000,\n    0x15000100, 0xC1400004, 0xC1900006, 0x71948000, 0x15000100, 0xC1400006, 0xC1900008, 0x71948000,\n    0x15000100, 0xC140000E, 0xC190000A, 0x71948000, 0x15000100, 0xC1400000, 0xC190000C, 0x71948000,\n    0x15000100, 0xC1400002, 0xC190000E, 0x71948000, 0x15000100, 0xC0400000, 0xC11C0000, 0xC000082C,\n    0xCD040E08, 0xC11C0002, 0xC000082C, 0xCD040E08, 0xC0400002, 0xC11C0000, 0xC000082C, 0xCD040E08,\n    0xC11C0002, 0xC000082C, 0xCD040E08, 0xC0000824, 0x00000000, 0xCBC00001, 0xCB800001, 0xCB400001,\n    0xCB000000, 0xC0004878, 0x5BFC4000, 0xCFC00001, 0x5BB84000, 0xCF800001, 0x5B744000, 0xCF400001,\n    0x5B304000, 0xCF000000, 0xC0000A10, 0x00000000, 0xCBC00001, 0xCB800000, 0xC0004874, 0x5BFC4000,\n    0xCFC00001, 0x5BB84000, 0xCF800000, 0xC30001FE, 0xC000140A, 0xCF000000, 0xC3000000, 0x7F018000,\n    0xC000042E, 0xCF000000, 0xC000040E, 0xCF000000, 0xC3C1FFFE, 0xC000490E, 0xCFC00080, 0xC000492C,\n    0xCFC00080, 0xC0004924, 0xCFC00040, 0xC0004912, 0xCFC00040, 0xC0004966, 0xCFC00040, 0xC0004968,\n    0xCFC00080, 0xC000496A, 0xCFC00080, 0xC3C1FFFE, 0xC00049A0, 0xCFC00000, 0xC3C00000, 0xC2800020,\n    0xC3000000, 0x7F018000, 0x6FF88000, 0x6FD44000, 0x4395C000, 0x5BB84A00, 0x5838000A, 0xCF000000,\n    0x5BFC0002, 0xB7E8FFA8, 0x00000000, 0xC3C00000, 0xC2800010, 0x6FF86000, 0x47F9C000, 0x5BB84C80,\n    0xC3400000, 0x58380004, 0xCB420080, 0x00000000, 0x58380008, 0xCF400080, 0x5BFC0002, 0xB7E8FF90,\n    0x00000000, 0xC3C00000, 0xC2800020, 0xC348001E, 0xC3000000, 0x7F018000, 0x6FF8A000, 0x6FD44000,\n    0x4579C000, 0x47F9C000, 0x5BB84E20, 0x58380008, 0xCF400420, 0x5838000A, 0xCF000000, 0x5BFC0002,\n    0xB7E8FF90, 0x00000000, 0x00000000, 0xC3E02242, 0x5BFC0022, 0xC0004002, 0xCFC00000, 0x00000000,\n    0xC121FFFE, 0x5911FE14, 0x15000000, 0x80000518, 0x00000000, 0x80002118, 0x00000000, 0x8000FFC8,\n    0xC0004958, 0xC8400000, 0x00000000, 0xC3C00002, 0x7BC42000, 0xCC400000, 0xC0004848, 0xCB840000,\n    0xC000495C, 0xCAC40000, 0xC0004844, 0xC8840000, 0x46F90000, 0x8400FF6A, 0xC000487C, 0xC8040000,\n    0x00000000, 0x00000000, 0x40080000, 0xCA000000, 0xC0001624, 0xCB040000, 0xA63C005A, 0x00000000,\n    0x00000000, 0xA71EFF02, 0x00000000, 0xC0000824, 0xCA840000, 0x6CA08000, 0x6CA42000, 0x46610000,\n    0x42290000, 0xC35E0002, 0xC6340068, 0xC0001624, 0xCF440080, 0xC2000000, 0xC161FFFE, 0x5955FFFE,\n    0x15400000, 0x00000000, 0xC0004844, 0xC8840000, 0xC000082C, 0xCA040040, 0x00000000, 0x00000000,\n    0x58880002, 0xB608FFF8, 0x00000000, 0xC0800000, 0xC0004844, 0xCC840040, 0x5AEC0002, 0xC000495C,\n    0xCEC40000, 0x5E6C0006, 0x84000048, 0xC0004848, 0xCB840000, 0xC0000838, 0xC2500002, 0xCE440808,\n    0x5FB80002, 0xC0004848, 0xCF840000, 0x5EEC0002, 0xC000495C, 0xCEC40000, 0x00000000, 0xC121FFFE,\n    0x5911FE14, 0x15000000, 0x8000FD80, 0xC000495A, 0xC8400000, 0x00000000, 0xC3C00002, 0x7BC42000,\n    0xCC400000, 0xC0004960, 0xCAC40000, 0x00000000, 0x00000000, 0x5EEC0000, 0x840000F2, 0x00000000,\n    0xB6FC0030, 0xC0001600, 0xCA040000, 0x00000000, 0x00000000, 0xA61E00B2, 0x6FE90000, 0xC0000A28,\n    0xCE840808, 0xC2C00000, 0xC2800004, 0xB6E80080, 0xC0001604, 0xCA840000, 0xC0004960, 0xCEC40000,\n    0xA69EFCA2, 0x00000000, 0x6FE90000, 0xC0000A28, 0xCE840808, 0xC2C00002, 0xC0001600, 0xCA040000,\n    0x00000000, 0x00000000, 0xA61E000A, 0x6FE90000, 0xC0000A28, 0xCE840808, 0xC2C00000, 0xC0001604,\n    0xCA840000, 0xC0004960, 0xCEC40000, 0xA69EFC0A, 0xC2400000, 0xC0000A14, 0xCA440030, 0x00000000,\n    0x00000000, 0x46E52000, 0xA4400000, 0xC2800000, 0xDFEB0031, 0x8000FFF8, 0xDFEA0031, 0xB668FB82,\n    0x00000000, 0xC00048A0, 0xCB040000, 0xC0000A10, 0xCA840000, 0x6F208000, 0x6F242000, 0x46610000,\n    0x42A10000, 0xC2400000, 0xC0000A14, 0xCA440030, 0xC35E0002, 0xC6340068, 0xC0001604, 0xCF440080,\n    0x5B300002, 0xB670FFF8, 0x5AEC0002, 0xC3000000, 0xC00048A0, 0xCF040000, 0xC0004960, 0xCEC40000,\n    0x8000FAC0, 0xC0004918, 0xD2800000, 0xC2000000, 0xDF600040, 0x5E600080, 0x8400025A, 0x00000000,\n    0xC161FFFE, 0x5955FFFE, 0x15400000, 0x00000000, 0xC000480A, 0xCA000000, 0xC0004912, 0xCA400000,\n    0xC0004924, 0xCA800000, 0xC0004966, 0xCAC00000, 0x00000000, 0xC121FFFE, 0x5911FE14, 0x15000000,\n    0x76610000, 0x76A10000, 0x76E10000, 0x840001B2, 0xC0004918, 0xCA400000, 0xC28001FE, 0x76A10000,\n    0x5A640002, 0x6A254010, 0x5EE80000, 0x84000002, 0x6AA54000, 0x8000FFF8, 0xC6280000, 0x62818008,\n    0xC0004918, 0xCF000000, 0xC161FFFE, 0x5955FFFE, 0x15400000, 0x00000000, 0xC0004966, 0xCA400000,\n    0xC2000002, 0x6A310000, 0x7E010000, 0x76252000, 0xCE400000, 0x00000000, 0xC121FFFE, 0x5911FE14,\n    0x15000000, 0x6F346000, 0x4735A000, 0x5B744C80, 0xC2800000, 0x58340006, 0xCA800080, 0xC2C00000,\n    0x58340000, 0xCAC000E0, 0xC2400000, 0x5834000A, 0xCA420080, 0x6EA82000, 0x42E9E000, 0x6F2CA000,\n    0x42E56000, 0x5AEC1400, 0xC3990040, 0xC7381C20, 0xC6F80068, 0x99005B78, 0xDB980000, 0xDBD80001,\n    0x00000000, 0xDEA00000, 0x47210000, 0x8400FD68, 0xC0004958, 0xC8400000, 0x00000000, 0xC3C00002,\n    0x7BC42000, 0xCC400000, 0xC0004848, 0xCB840000, 0xC0004844, 0xC8840000, 0x5FB80000, 0x8400F7DA,\n    0xC0001A1C, 0xCA000000, 0xC2400002, 0x6A452000, 0x76610000, 0x8400F7AA, 0xC000487C, 0xC8040000,\n    0x00000000, 0x00000000, 0x40080000, 0xCA000000, 0xC4240000, 0x00000000, 0xA63C17BA, 0x00000000,\n    0xC0004878, 0xC8040000, 0x6C908000, 0x44908000, 0x44908000, 0x40100000, 0xCA000000, 0xC4240000,\n    0x00000000, 0xC0004934, 0xCE000000, 0xC2800002, 0xC4681C10, 0xC62821D8, 0xC2600010, 0x5A650040,\n    0xC0004800, 0xCB400000, 0xC2200400, 0x5A200000, 0xC7601048, 0xC0001220, 0xCE800000, 0xC0001200,\n    0xCE400000, 0xC0001202, 0xCE000000, 0xC0001240, 0xCB400000, 0x00000000, 0x00000000, 0xA754FFC0,\n    0xC2000000, 0xC7600048, 0xA7520022, 0x00000000, 0x00000000, 0x990062F0, 0xC0004822, 0xC9400000,\n    0xC1800002, 0x80001668, 0x58204080, 0xC2000000, 0xCA000020, 0xC2400000, 0xCA414008, 0xC2800000,\n    0xCA812008, 0xC2C00000, 0xCAC20020, 0xC0004938, 0xCE000000, 0xC0004920, 0xCE400000, 0xC0004916,\n    0xCE800000, 0xC0004922, 0xCEC00000, 0xA6400520, 0x00000000, 0xC0004938, 0xCBC00000, 0x00000000,\n    0xC3800000, 0x6FF48000, 0x6FD44000, 0x4355A000, 0x5B744A00, 0x58340000, 0xCB802018, 0x00000000,\n    0xC2000000, 0x6FB46000, 0x47B5A000, 0x5B744C80, 0x5834000C, 0xCA000028, 0xC000491A, 0xCF800000,\n    0x5E200000, 0x84000452, 0xC2000000, 0xDF610050, 0x5E6001E8, 0x8800FFD0, 0xC2000002, 0xC2400466,\n    0xC2A00000, 0x5AA80000, 0xC0001006, 0xCE000000, 0xC0001008, 0xCE400000, 0xC000100A, 0xCE800000,\n    0x990055B8, 0xC1A0FFFE, 0xC0000824, 0xC9840068, 0xC0004934, 0xCA400000, 0xC2000000, 0xC2800002,\n    0x990055F8, 0xDA980000, 0xC6140000, 0xC6580000, 0xC161FFFE, 0x5955FFFE, 0x15400000, 0x00000000,\n    0x990056E0, 0xC000491A, 0xC9400000, 0x00000000, 0x00000000, 0xC121FFFE, 0x5911FE14, 0x15000000,\n    0xC0004922, 0xCA001120, 0xC3C00000, 0xC3800000, 0xC0004930, 0xCE001120, 0xC0004932, 0xCBC000E0,\n    0xC2800000, 0xC000491E, 0xCFC00000, 0xC0004862, 0xCA800068, 0xC3A0001A, 0x5BB94000, 0xC6B80068,\n    0xC000491C, 0xCF800000, 0x99005950, 0xC000491C, 0xC1400000, 0xC9420050, 0x00000000, 0x00000000,\n    0x00000000, 0xA8E2FFC8, 0xC2000000, 0xC1220002, 0xD90C0000, 0xDF600040, 0x5E600080, 0x8400FFDA,\n    0xC000491C, 0xCA000000, 0xC000491E, 0xCA400000, 0x00000000, 0x00000000, 0x99005B78, 0xDA180000,\n    0xDA580001, 0x00000000, 0xC2000000, 0xDF610050, 0x5E6001FE, 0x8800FFD0, 0xC0004916, 0xCA800000,\n    0xC2C00000, 0xDFEC0050, 0xC2400000, 0x46E52000, 0x84000032, 0x5EA80000, 0x84000022, 0xC2600002,\n    0x990062F0, 0xC000482E, 0xC9400000, 0xC1800002, 0x80000018, 0xC2600000, 0x990062F0, 0xC000482C,\n    0xC9400000, 0xC1800002, 0xC2000068, 0xC6240080, 0xC0004930, 0xCE400088, 0xC000491A, 0xC9800000,\n    0xC0004862, 0xC9400000, 0x6D9C6000, 0x459CE000, 0x59DC4C80, 0x990059D8, 0xD9580000, 0xD9980001,\n    0xD9D40000, 0x99005950, 0xC000491C, 0xC1400000, 0xC9420050, 0xC2000000, 0xDF600040, 0x5E600080,\n    0x8400FFD2, 0x00000000, 0xC000491C, 0xCA000000, 0xC000491E, 0xCA400000, 0x00000000, 0x00000000,\n    0x99005B78, 0xDA180000, 0xDA580001, 0x00000000, 0x800010D0, 0x00000000, 0x990062F0, 0xC000482A,\n    0xC9400000, 0xC1800002, 0x800010A0, 0xC0004938, 0xCBC00000, 0x00000000, 0x00000000, 0x6FF88000,\n    0x6FD44000, 0x4395C000, 0x5BB84A00, 0x58380008, 0xCA000000, 0x00000000, 0x00000000, 0xA6000362,\n    0x00000000, 0xC0004938, 0xCBC00000, 0xC3000000, 0x00000000, 0x6FF88000, 0x6FD44000, 0x4395C000,\n    0x5BB84A00, 0x58380000, 0xCB002018, 0xC2000000, 0x58380008, 0xCA020080, 0x5838000C, 0xCAC00000,\n    0x5838000E, 0xCA400000, 0xC000491A, 0xCF000000, 0xC0004930, 0xCEC00000, 0xC000493C, 0xCE000000,\n    0xC0004932, 0xCE400000, 0x5E200000, 0x84000108, 0xC2800000, 0xA6FE009A, 0x6F206000, 0x47210000,\n    0x5A204C80, 0x5820000C, 0xCA800028, 0x00000000, 0x00000000, 0x5EA80000, 0x840001DA, 0x00000000,\n    0xC161FFFE, 0x5955FFFE, 0x15400000, 0x00000000, 0x990056E0, 0xC000491A, 0xC9400000, 0x00000000,\n    0x00000000, 0xC121FFFE, 0x5911FE14, 0x15000000, 0xC0004930, 0xCAC00000, 0xC0004932, 0xCA400000,\n    0xC7EC1120, 0xC0004930, 0xCEC00000, 0x5838000C, 0xCEC00000, 0x58000002, 0xCE400000, 0xC0004934,\n    0xCA000000, 0xC2400002, 0x6E642000, 0x6E642000, 0x76252000, 0x84000012, 0xC2400002, 0x6E684000,\n    0x58380008, 0xCE800208, 0xA6000000, 0x6E682000, 0x58380008, 0xCE800108, 0xC2400002, 0x6E642000,\n    0x76252000, 0x840000D2, 0x58380008, 0xCA000000, 0xC2800000, 0xC2400000, 0xA60200A0, 0xDBA80000,\n    0x6F386000, 0x4739C000, 0x5BB84C80, 0x58380004, 0xCA400080, 0x58380002, 0xCA800080, 0x00000000,\n    0xDEB80000, 0x46694000, 0x88000048, 0x00000000, 0xC0004824, 0xCA000000, 0xC2400002, 0x6E640000,\n    0x5A200002, 0xCE000000, 0x58380008, 0xCE400008, 0x80000000, 0x00000000, 0x80000030, 0xC0004934,\n    0xCA000000, 0x00000000, 0x00000000, 0xA6020C4A, 0x00000000, 0x00000000, 0x80000C80, 0xC2800000,\n    0xC2000200, 0xC240001A, 0xDF690050, 0x46A14000, 0x46694000, 0x8800FFBA, 0xC2000006, 0xC2600982,\n    0x5A643B6E, 0x5838000A, 0xCA800000, 0xC0001006, 0xCE000000, 0xC0001008, 0xCE400000, 0xC000100A,\n    0xCE800000, 0x990055B8, 0xC1A0FFFE, 0xC0000824, 0xC9840068, 0xC2000000, 0xC0004930, 0xCA02E010,\n    0x58380026, 0xCA400000, 0x00000000, 0xC2800000, 0x990055F8, 0xDA980000, 0xC6140000, 0xC6580000,\n    0xC0004934, 0xCA000000, 0x00000000, 0x00000000, 0xA6020002, 0x00000000, 0x00000000, 0x80000300,\n    0xC0004938, 0xCBC00000, 0xC0004878, 0xC8040000, 0x6C908000, 0x44908000, 0x44908000, 0x40100000,\n    0xCA000000, 0xC4240000, 0x00000000, 0x58240018, 0xCA000000, 0x6FF88000, 0x6FD44000, 0x4395C000,\n    0x5BB84A00, 0xC3000000, 0xC3400002, 0xC2C00000, 0xC62C0080, 0xC6270040, 0xC0004940, 0xCE400040,\n    0xC6260040, 0xC0004942, 0xCE400040, 0xC000493C, 0xCA000000, 0x5EEC0000, 0x84000172, 0x5A6C0010,\n    0x46614000, 0x88000178, 0x5A600052, 0x466D4000, 0x88000160, 0x58380006, 0xCA800000, 0xC0004940,\n    0xCA000000, 0xC2400000, 0xC6A70040, 0x7E412000, 0x76252000, 0xC2000000, 0xC6A10040, 0x46610000,\n    0x84000120, 0xC0004942, 0xCA000000, 0xC2400000, 0xC6A60040, 0x7E412000, 0x76252000, 0xC2000000,\n    0xC6A00040, 0x58380002, 0xCA800000, 0x46610000, 0x840000D0, 0xC2400000, 0xC6A60080, 0x46E50000,\n    0x880000C2, 0xC2400000, 0xC6A40080, 0x58380008, 0xCA800000, 0x466D0000, 0x880000A2, 0x00000000,\n    0xA682FFF8, 0x00000000, 0xC7700B08, 0xA6840078, 0x00000000, 0xC7700A08, 0x80000068, 0xC7700208,\n    0xC000493C, 0xCAC00000, 0x80000048, 0xC7700308, 0xC000493C, 0xCAC00000, 0x80000028, 0xC7700908,\n    0x80000018, 0xC7700808, 0x80000008, 0xC7700708, 0x8000FFF8, 0xC7700508, 0xC0004944, 0xCF000000,\n    0xC000493E, 0xCEC00000, 0xC0004938, 0xCA400000, 0xC000493C, 0xCB800000, 0xC000493E, 0xCB400000,\n    0xC3000000, 0x6E608000, 0x6E544000, 0x42150000, 0x5A204A00, 0x5AA00008, 0x58200004, 0xCB000080,\n    0xC0004934, 0xCA000000, 0xC2400000, 0xC0004930, 0xCA42E010, 0xC3C00018, 0xA6020078, 0x00000000,\n    0x43656000, 0x46F90000, 0x88000038, 0x47AD6000, 0x6EE04010, 0x5BE00004, 0xC2000000, 0xC6E00010,\n    0x5E200000, 0x8400002A, 0x5BFC0002, 0x80000018, 0xC3C00004, 0x5A2C0008, 0x46390000, 0x8800FFFA,\n    0x5FB80008, 0x6FE04000, 0x42390000, 0x46312000, 0x88000050, 0xC2400000, 0xC0004930, 0xCA42E010,\n    0xC2060002, 0xC6800000, 0xCE000308, 0x6FE04000, 0x4631C000, 0x5F700010, 0x4675A000, 0xC2000000,\n    0xC6340010, 0xC25A000A, 0xC000491A, 0xCA401C20, 0xC2800000, 0xC0004932, 0xCA8000E0, 0xC0004862,\n    0xCA400068, 0x6FA04010, 0x42290000, 0xC000491E, 0xCE000000, 0xC7E41050, 0xC000491C, 0xCE400000,\n    0x6FE04000, 0x43A1C000, 0xC000493C, 0xCF800000, 0xC000493E, 0xCF400000, 0xC000493A, 0xCFC00000,\n    0x8000FFF0, 0x00000000, 0x00000000, 0x00000000, 0xC2000000, 0xDCE00000, 0xA622FFB8, 0xC1220002,\n    0xD90C0000, 0xC0004938, 0xCBC00000, 0xC0004944, 0xCB400000, 0xC0004862, 0xCB000000, 0xC0004934,\n    0xCA000000, 0x6FF88000, 0x6FD44000, 0x4395C000, 0x5BB84A00, 0xA6020248, 0xC2400000, 0x58380008,\n    0xCA406008, 0xDFE80000, 0xC2218E08, 0x5A21BAF6, 0x46294000, 0x8400000A, 0xC2080002, 0x7235A000,\n    0x80000040, 0x5E640000, 0x8400000A, 0xC20C0002, 0x7235A000, 0x80000018, 0xC2000000, 0xC760E718,\n    0xC7604220, 0x5E200000, 0x8400025A, 0xC2200002, 0xC0004930, 0xCE001008, 0x990062F0, 0xC0004828,\n    0xC9400000, 0xC1800002, 0x58380000, 0xCA000000, 0x00000000, 0x00000000, 0xA6000112, 0xC0004940,\n    0xCA800000, 0xC0004942, 0xCA400000, 0xC7600080, 0xC6A01840, 0xC6601040, 0xC000493A, 0xCA400000,\n    0xC0004934, 0xCA800000, 0xC0007200, 0x40300000, 0x40240000, 0x5C000004, 0x5EC07400, 0x8800FFFA,\n    0x5C000200, 0xCE000000, 0x58000002, 0x5EC07400, 0x8800FFFA, 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0x840001AA, 0xC0004926, 0xCA400000, 0xC201FFFE, 0x762D6000,\n    0x5A640002, 0x6AE50010, 0x5F200000, 0x84000002, 0x6A250000, 0x8000FFF8, 0xC6E00000, 0x62014008,\n    0xC0004926, 0xCE800000, 0xC161FFFE, 0x5955FFFE, 0x15400000, 0x00000000, 0xC0004968, 0xCA400000,\n    0xC2000002, 0x6A290000, 0x7E010000, 0x76252000, 0xCE400000, 0x00000000, 0xC121FFFE, 0x5911FE14,\n    0x15000000, 0x6EB4A000, 0x6E944000, 0x4575A000, 0x46B5A000, 0x5B744E20, 0x58340002, 0xC2000000,\n    0xCA0000E0, 0x5834002E, 0xC2400000, 0xCA400080, 0x6EB0A000, 0x6EBC4000, 0x47F18000, 0x46B18000,\n    0x5B300E4E, 0x5B300004, 0x6E642000, 0x4225E000, 0xC39A8024, 0xC7380068, 0xC6B81C20, 0x99005B78,\n    0xDB980000, 0xDBD80001, 0x00000000, 0xC2000000, 0xDF600040, 0x5E200080, 0x8400033A, 0x00000000,\n    0xC161FFFE, 0x5955FFFE, 0x15400000, 0x00000000, 0xC000490E, 0xCA000000, 0xC00049A0, 0xCA800000,\n    0xC000492A, 0xCA400000, 0xC000496A, 0xCB000000, 0xC0004956, 0xCAC00000, 0x00000000, 0xC121FFFE,\n    0x5911FE14, 0x15000000, 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0xCBC00000, 0x00000000, 0x00000000, 0x6FF8A000, 0x6FD44000, 0x4579C000, 0x47F9C000, 0x5BB84E20,\n    0x99005C08, 0xDBD80000, 0xDB980001, 0x00000000, 0x99005950, 0xC000491C, 0xC1400000, 0xC9420050,\n    0xC000491C, 0x99005E00, 0xC9400001, 0xC9800000, 0x00000000, 0x99005B78, 0xD9580000, 0xD9980001,\n    0x00000000, 0xC161FFFE, 0x5955FFFE, 0x15400000, 0x00000000, 0x99005840, 0xDBD80000, 0xDB980001,\n    0xC7D80000, 0x00000000, 0xC121FFFE, 0x5911FE14, 0x15000000, 0x6FF8A000, 0x6FD44000, 0x4579C000,\n    0x47F9C000, 0x5BB84E20, 0x58380010, 0xCA000000, 0xC0004874, 0xC8040000, 0x6C908000, 0x44908000,\n    0x44908000, 0x40100000, 0xCA400000, 0xC4340000, 0x00000000, 0xC7400000, 0xCE000000, 0xC161FFFE,\n    0x5955FFFE, 0x15400000, 0x00000000, 0xC000490E, 0xCA400000, 0xC2800002, 0x6ABD4000, 0x72A52000,\n    0xCE400000, 0x00000000, 0xC121FFFE, 0x5911FE14, 0x15000000, 0x990062F0, 0xC0004836, 0xC9400000,\n    0xC1800002, 0x00000000, 0x00000000, 0x00000000, 0xA8E2FFC8, 0x00000000, 0x58380000, 0xC9000000,\n    0xC00049A0, 0xCA000000, 0xC2800000, 0xC5290040, 0x72A10000, 0xCE000000, 0xC1220002, 0xD90C0000,\n    0xC2000000, 0xC0000A14, 0xCA040030, 0xC0000A28, 0xC2500002, 0xCE440808, 0x58880002, 0xB608FFF8,\n    0xC00048A0, 0xC0800000, 0xCC840000, 0x8000D368, 0xC0004946, 0xCBC00000, 0xC161FFFE, 0x5955FFFE,\n    0x15400000, 0x00000000, 0xC000490E, 0xCA400000, 0xC2800002, 0x6ABD4000, 0x72A52000, 0xCE400000,\n    0x00000000, 0xC121FFFE, 0x5911FE14, 0x15000000, 0x6FF8A000, 0x6FD44000, 0x4579C000, 0x47F9C000,\n    0x5BB84E20, 0x58380008, 0xCA000000, 0x5838000C, 0xCA400000, 0xC3400000, 0xC6340008, 0xC000494E,\n    0xCF400000, 0xC2800000, 0xC62A0080, 0xC3000000, 0xC6308020, 0x6F304000, 0x43298000, 0xC000493C,\n    0xCF000000, 0xC2C00000, 0xC66C0080, 0xC0004950, 0xCEC00000, 0xC2800000, 0xC66AE028, 0xC0004954,\n    0xCE800000, 0x5F740000, 0x84000188, 0x5E300028, 0x462D2000, 0x84000152, 0x462D2000, 0x8800011A,\n    0x5E300018, 0x462D2000, 0x88000012, 0x462D2000, 0x8400002A, 0x00000000, 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0x59540002, 0xC0004848, 0xCD440000, 0x58880002, 0xB4980450, 0x00000000, 0xC0800000,\n    0x80000440, 0xC0004854, 0xC1000004, 0xCD040000, 0xC0000820, 0xC2000002, 0xCE040000, 0xC2000000,\n    0xC000484C, 0xCE040000, 0xC0004858, 0xCE040000, 0x8000FF10, 0xC0004854, 0xC1000000, 0xCD040000,\n    0xC11C0000, 0xC000082C, 0xCD040E08, 0x99005590, 0xC0004848, 0xC9440000, 0xC1800000, 0xC1200000,\n    0xC0000818, 0xCD041008, 0xC11C0002, 0xC000082C, 0xCD040E08, 0xC2000000, 0xC000484C, 0xCE040000,\n    0x80000340, 0xC0001AC0, 0xCB840000, 0xC000487C, 0xC8040000, 0x00000000, 0x00000000, 0x40080000,\n    0xCBC00000, 0xC4280000, 0x00000000, 0x00000000, 0xC6800000, 0xC13C0000, 0xCD001E08, 0xA780022A,\n    0x00000000, 0x00000000, 0xA7C001EA, 0x00000000, 0xC0001B00, 0xC2060006, 0xCE040310, 0xA7E801A2,\n    0x00000000, 0xC0004850, 0xCA040000, 0xC2400000, 0xC0001AEC, 0xCA448020, 0x5A200002, 0xC0004850,\n    0xCE040000, 0xB624008A, 0x00000000, 0xC6800000, 0xC13C0002, 0xCD001E08, 0xC0001ACC, 0xC2000002,\n    0xCE040008, 0xC0004848, 0xC9440000, 0xC1800000, 0xC000082C, 0xC9840030, 0x59540002, 0xC0004848,\n    0xCD440000, 0x58880002, 0xB49801A8, 0x00000000, 0xC0800000, 0x80000198, 0xC0004854, 0xC1000000,\n    0xCD040000, 0xC11C0000, 0xC000082C, 0xCD040E08, 0x99005590, 0xC0004848, 0xC9440000, 0xC1800000,\n    0xC2000000, 0xC0000820, 0xCE040000, 0xC1200000, 0xC0000818, 0xCD041008, 0xC11C0002, 0xC000082C,\n    0xCD040E08, 0xC0004850, 0xCE040000, 0xC2000002, 0xC0001ACC, 0xCE040010, 0x800000D0, 0xC2000002,\n    0xC0004850, 0xCE040000, 0x8000FE70, 0xC2000000, 0xC0004850, 0xCE040000, 0xA7E60012, 0x00000000,\n    0xC2000002, 0xC0001B00, 0xCE040008, 0x8000FE58, 0x00000000, 0xA7860032, 0x00000000, 0xC6800000,\n    0xC13C0002, 0xCD001E08, 0xC2020002, 0xC7E2A548, 0xC0001B00, 0xCE040000, 0x8000FE00, 0xC2040002,\n    0xC0001B00, 0xCE040208, 0x8000FDE0, 0xC2C80002, 0x6AC56000, 0xDACC0000, 0xC0004854, 0xCB440000,\n    0xC0004848, 0xCB840000, 0xC0000838, 0xC3C00000, 0xCBC40030, 0x5EF40004, 0x8400000A, 0xC3000000,\n    0xC0001ACC, 0xCF040108, 0x47BD8000, 0x84000012, 0x47BD8000, 0x88000018, 0xC1006E8C, 0x8000B6B0,\n    0xC0004840, 0xCC840000, 0x8000F698, 0xC0001AC0, 0xCAC40000, 0xC0004854, 0xCB440000, 0xA6C0FBB2,\n    0x00000000, 0x5EF40000, 0x8400F6F2, 0x5EF40002, 0x8400F982, 0x5EF40004, 0x8400FB82, 0xC1006CE8,\n    0x8000B628, 0x00000000, 0xC0800000, 0xDF4B0040, 0xC0004900, 0xCB800000, 0xC2000000, 0xC000490A,\n    0xA78000B0, 0xCBC00000, 0xC1000000, 0xD9000001, 0xC1000002, 0xD90C0000, 0x6FF46000, 0x47F5A000,\n    0x5B744C80, 0xC2400000, 0x58340004, 0xCA400080, 0xC0004900, 0xCE000008, 0x5A640002, 0x58340004,\n    0xC6500080, 0xCD000080, 0xC0004914, 0xCA400000, 0xC2000002, 0x6A3D0000, 0x72252000, 0xCE400000,\n    0xC0000408, 0xCE000000, 0xA78200B8, 0xC0004908, 0xCBC00000, 0xC1000000, 0xD9000001, 0xC1000002,\n    0xD90C0000, 0x6FF4A000, 0x6FD44000, 0x4575A000, 0x47F5A000, 0x5B744E20, 0xC2800000, 0x58340006,\n    0xCA800080, 0xC2000000, 0xC0004900, 0xCE000108, 0x5EA80002, 0x58340006, 0xC6900080, 0xCD000080,\n    0x5A7C0020, 0xC2000002, 0x6A250000, 0xC0000408, 0xCE000000, 0xDCA80001, 0x5EA80000, 0x8400B498,\n    0x00000000, 0xA4800210, 0x00000000, 0xC3C00000, 0xC000140E, 0xCBC00020, 0xC3400000, 0xC2400000,\n    0x6FF86000, 0x47F9C000, 0x5BB84C80, 0x58380008, 0xCB400080, 0x58380006, 0xCA400080, 0x5F740002,\n    0x58380008, 0xC7500080, 0xCD000080, 0xC2000000, 0x58380004, 0xCA020080, 0xC3000000, 0x5838000C,\n    0xCB000028, 0x5A640002, 0x46250000, 0x8400FFF8, 0xC2400000, 0x58380006, 0xC6500080, 0xCD000080,\n    0xC2000000, 0x5838000A, 0xCA020080, 0x5B300002, 0x5838000C, 0xC7100028, 0xCD000028, 0xC2420020,\n    0x5A200004, 0x46612000, 0x8400FFF8, 0xC2000000, 0x5838000A, 0xC6101080, 0xCD001080, 0xC0004966,\n    0xCA400000, 0xC2000002, 0x6A3D0000, 0x72252000, 0xCE400000, 0x5F740000, 0x84000028, 0xC0004912,\n    0xCA000000, 0xC2C00002, 0x6AFD6000, 0x7EC16000, 0x76E10000, 0xCE000000, 0x5F300020, 0x84000028,\n    0xC0004924, 0xCA000000, 0xC2C00002, 0x6AFD6000, 0x7EC16000, 0x76E10000, 0xCE000000, 0xA4820050,\n    0xC2400000, 0xC000140E, 0xCA408020, 0xC2000002, 0xC0004900, 0xCE000008, 0xC000490A, 0xCE400000,\n    0xC1000000, 0xD9000001, 0xD8400080, 0xC1000004, 0xD9000001, 0xA4840250, 0x00000000, 0xC3C00000,\n    0xC000140E, 0xCBC10020, 0xC2800000, 0xC2000000, 0x6FF8A000, 0x6FD44000, 0x4579C000, 0x47F9C000,\n    0x5BB84E20, 0x5838002E, 0xCA800080, 0x58380006, 0xCA020080, 0xC3400000, 0x5838002E, 0xCB420080,\n    0x5AA80002, 0x46290000, 0x8400FFF8, 0xC2800000, 0x5838002E, 0xC6900080, 0xCD000080, 0x5F740002,\n    0x5838002E, 0xC7501080, 0xCD001080, 0xC0004968, 0xCA400000, 0xC2000002, 0x6A3D0000, 0x72252000,\n    0xCE400000, 0xC000492A, 0xCA800000, 0x5E740000, 0x84000028, 0xC0004910, 0xCA000000, 0xC2C00002,\n    0x6AFD6000, 0x7EC16000, 0x76E10000, 0xCE000000, 0x6ABD4010, 0xA680009A, 0x00000000, 0x58380032,\n    0xCA000000, 0x58000002, 0xCA400000, 0x5838000C, 0x00000000, 0xCE000001, 0xCE400000, 0xC000492A,\n    0xCA000000, 0xC2C00002, 0x6AFD6000, 0x72E10000, 0xCE000000, 0xC000492C, 0xCA000000, 0xC2C00002,\n    0x6AFD6000, 0x72E10000, 0xCE000000, 0x80000028, 0xC000492C, 0xCA000000, 0xC2C00002, 0x6AFD6000,\n    0x7EC16000, 0x76E10000, 0xCE000000, 0xA4880128, 0xC2C00000, 0xC000140E, 0xCAC20020, 0xC000490E,\n    0xCA400000, 0xC2000002, 0x6A2D0000, 0x7E010000, 0x76252000, 0xCE400000, 0xC000496A, 0xCA400000,\n    0xC2000002, 0x6A2D0000, 0x72252000, 0xCE400000, 0x6EF0A000, 0x6ED44000, 0x45718000, 0x46F18000,\n    0x5B304E20, 0x58300000, 0xCA000000, 0x00000000, 0xC2400002, 0x76252000, 0x8400005A, 0x58300000,\n    0xCA400000, 0xC2800000, 0x00000000, 0xC6684020, 0xC24C0002, 0xC6A40020, 0xC624C408, 0x58300010,\n    0xCA400508, 0x00000000, 0xC0001800, 0xCE400000, 0xA4860050, 0xC2400000, 0xC000140E, 0xCA418020,\n    0xC2020002, 0xC0004900, 0xCE000108, 0xC0004908, 0xCE400000, 0xC1000000, 0xD9000001, 0xD8400080,\n    0xC1000004, 0xD9000001, 0xC0001408, 0xCC800000, 0xC10E0002, 0xD90C0000, 0x8000ED98, 0xDFBC0001,\n    0xC000496E, 0x99006298, 0xC9400000, 0xC7D80000, 0x00000000, 0xC5700000, 0x5EF00020, 0x88000130,\n    0x6F346000, 0x4735A000, 0x5B744C80, 0x58340008, 0xC2400000, 0xCA400080, 0x00000000, 0xC2000000,\n    0x5A640002, 0xCE400080, 0x58340004, 0xCA000080, 0x00000000, 0x00000000, 0x5E200002, 0xCE000080,\n    0xC0004912, 0xCA800000, 0xC2400002, 0x6A712000, 0x72694000, 0xCE800000, 0x5E200000, 0x8400003A,\n    0xC000480A, 0xCA000000, 0xC0000408, 0xCA800000, 0x76610000, 0x00000000, 0x72294000, 0xCE800000,\n    0x80000020, 0xC0004914, 0xCA000000, 0x7E412000, 0x00000000, 0x76610000, 0xCE000000, 0x800000B8,\n    0x6EF4A000, 0x6ED44000, 0x4575A000, 0x46F5A000, 0x5B744E20, 0x5834002E, 0xC2400000, 0xCA420080,\n    0x00000000, 0xC2000000, 0x5A640002, 0xC6501080, 0xCD001080, 0x58340006, 0xCA000080, 0x00000000,\n    0x00000000, 0x5A200002, 0xCE000080, 0xC0004910, 0xCA400000, 0xC2000002, 0x6A2D0000, 0x72252000,\n    0xCE400000, 0xC2000002, 0x6A310000, 0xC000042A, 0xCE000000, 0xC1040002, 0xD90C0000, 0x00000000,\n    0x8000EB08, 0x00000000, 0xC4980930, 0x9D000000, 0xC5580030, 0xC0000838, 0xCD840000, 0xC1440200,\n    0xC1C03200, 0xC55C1078, 0xC000100E, 0x9D000000, 0xCD800000, 0xC000100C, 0xCDC00000, 0xC0004862,\n    0xC9C00000, 0x00000000, 0x00000000, 0xD9D80001, 0xC0007200, 0x401C0000, 0x5DC07400, 0x8800FFFA,\n    0x5C000200, 0xCD800000, 0xC1F0000A, 0x71D4A000, 0xDD980000, 0xDD9C0001, 0x41D8E000, 0xC5D40268,\n    0xC0001010, 0xCD400000, 0x6C9C8000, 0x449CE000, 0x449CE000, 0x59DC0004, 0xC1601260, 0xC5D40268,\n    0x9D000000, 0xC0001012, 0xCD400000, 0x00000000, 0x00000000, 0xD9580000, 0x6D586000, 0x4558C000,\n    0x59984C80, 0xD9980001, 0x5818000A, 0xC1800000, 0xC9800080, 0xC0005400, 0x6D5CA000, 0x401C0000,\n    0x40180000, 0xC9400000, 0x58000002, 0x00000000, 0xC9C00000, 0xC0004930, 0xCD400000, 0xC0004932,\n    0xCDC00000, 0x59980004, 0xC1C20020, 0xB59CFFF8, 0x00000000, 0xC1800000, 0xDD9C0001, 0x581C000A,\n    0xCD800080, 0x581C000C, 0xC1800000, 0xC9800028, 0xC1C00002, 0xDD940000, 0x69D4E000, 0x5D980002,\n    0xCD800028, 0xC0004924, 0xC9800000, 0x00000000, 0x9D000000, 0x00000000, 0x71D8C000, 0xCD800000,\n    0xC000492A, 0xC9400000, 0xC1C00002, 0x69D8E000, 0x7DC0C000, 0x7594A000, 0xCD400000, 0xC000492C,\n    0xC9400000, 0xDD800001, 0x58000032, 0x75D4A000, 0x84000078, 0xC9400001, 0xC9800000, 0xDD800001,\n    0x5800000C, 0x00000000, 0xCD400001, 0xCD800000, 0xC000492C, 0xC9400000, 0xC000492A, 0xC9800000,\n    0x71D4A000, 0xC000492C, 0xCD400000, 0x71D8C000, 0xC000492A, 0xCD800000, 0x9D000000, 0x00000000,\n    0x00000000, 0x00000000, 0xC0004862, 0xC9800000, 0x00000000, 0xC1C00200, 0x4194C000, 0x45D8E000,\n    0x8800FFFA, 0xC5D80000, 0xC0004862, 0xCD800000, 0xC0001406, 0xC9800000, 0xC1C00002, 0x9D000000,\n    0xC5D80A08, 0xC5581050, 0xCD800000, 0xC0004930, 0xC9800000, 0xC0004932, 0xC9C00000, 0xC140000E,\n    0xC5581C20, 0xDD940000, 0xC0007200, 0x40140000, 0x5D407400, 0x8800FFFA, 0x5C000200, 0xCD800000,\n    0x58000002, 0x5D407400, 0x8800FFFA, 0x5C000200, 0xCDC00000, 0xDD540000, 0xC1C00000, 0x58140006,\n    0xC9C20080, 0xC1800000, 0x58140000, 0xC98000E0, 0x6DDC2000, 0xC000491E, 0x41D8E000, 0xCDC00000,\n    0xDD980000, 0xC1C00022, 0xC5D80D78, 0xDD940001, 0xC5581C20, 0xC000491C, 0xCD800000, 0xDD540000,\n    0xC1C00000, 0x58140006, 0xC9C20080, 0xC1800000, 0x58140004, 0xC9820080, 0x00000000, 0x59DC0002,\n    0x459CC000, 0x8400FFF8, 0xC1C00000, 0x9D000000, 0x58140006, 0xC5D81080, 0xCD801080, 0xC0004860,\n    0xC9400000, 0xC1820080, 0xC1D00002, 0x58146B00, 0xD5800000, 0x58000002, 0xD5800001, 0x59540004,\n    0xB558FFF8, 0xC0004860, 0xC1400000, 0xCD400000, 0xDD980001, 0x9D000000, 0xDD940000, 0xC0001404,\n    0xCDC00808, 0xC1C00000, 0xC1800200, 0x5D980004, 0xDF5D0050, 0x45D8A000, 0x8800FFDA, 0xDD800001,\n    0x5800000C, 0x00000000, 0xC9400001, 0xC9800000, 0xC1C00002, 0xC5D43F08, 0xC5D81E08, 0xC0004862,\n    0xC9C00000, 0x00000000, 0x00000000, 0x581C7200, 0x5DC07400, 0x8800FFFA, 0x5C000200, 0xCD400000,\n    0x58000002, 0x5DC07400, 0x8800FFFA, 0x5C000200, 0xCD800000, 0xC0004862, 0xC9C00000, 0x00000000,\n    0xC15004C0, 0xC5D40068, 0xDD9C0000, 0xC5D41C20, 0xC1C00000, 0xDD800001, 0x58000030, 0xC9C00080,\n    0xDD800001, 0x58000002, 0xC9800000, 0x6DDC2000, 0xC000491C, 0x41D8E000, 0xCD400001, 0xCDC00000,\n    0xDD940001, 0xC1C00000, 0x58140030, 0xC9C00080, 0xC1800000, 0x58140006, 0xC9820080, 0x00000000,\n    0x59DC0002, 0x459CC000, 0x8400FFF8, 0xC1C00000, 0x9D000000, 0x58140030, 0xC5D80080, 0xCD800080,\n    0xC1C00000, 0xDF5C0040, 0x5DDC0080, 0x8400FFD2, 0x00000000, 0x9D000000, 0x00000000, 0x00000000,\n    0x00000000, 0xC160FFFE, 0xC0000A10, 0xC9440068, 0xC1A0FFFE, 0x59980E28, 0xC000100C, 0xCD400000,\n    0xC000100E, 0xCD800000, 0xC0004964, 0xC9800000, 0x00000000, 0xC170000A, 0x7194A000, 0x6C988000,\n    0x4498C000, 0x4498C000, 0x59980004, 0xC5940278, 0xC0001010, 0xCD400000, 0xC0004946, 0xC9400000,\n    0x00000000, 0x00000000, 0x6D58A000, 0x6D5C4000, 0x45D8C000, 0x4558C000, 0xC000494A, 0xC9400000,\n    0xC0004948, 0xC9C00000, 0x4194C000, 0xC1400012, 0xC55C1820, 0x9D000000, 0xC59C0270, 0xC0001012,\n    0xCDC00000, 0xC1400000, 0x58000012, 0xC9410040, 0xC0004950, 0xC9C00000, 0xC5580000, 0xC5940840,\n    0xC5581080, 0xD9940000, 0xC000493C, 0xC9400000, 0xC0004954, 0xC9800000, 0x59DC00A8, 0x455CE000,\n    0x41D8E000, 0x5D5C0030, 0x8800FFF8, 0xC1C00030, 0xC1800000, 0xC5D84030, 0xC1400000, 0xC5D40010,\n    0x5DD40002, 0x8400005A, 0x5DD40004, 0x84000082, 0x5DD40006, 0x840000AA, 0x5DD80026, 0x840000D2,\n    0xDD540000, 0xDD800001, 0x58000008, 0x40180000, 0xCD400000, 0x59980002, 0x8000FFA8, 0xDD540000,\n    0xDD800001, 0x58000008, 0x40180000, 0xCD4000C0, 0x59980002, 0x8000FF70, 0xDD540000, 0xDD800001,\n    0x58000008, 0x40180000, 0xCD400080, 0x59980002, 0x8000FF38, 0xDD540000, 0xDD800001, 0x58000008,\n    0x40180000, 0xCD400040, 0x59980002, 0x8000FF00, 0x00000000, 0x9D000000, 0x00000000, 0x00000000,\n    0x00000000, 0x58000012, 0xC9400000, 0xC0004954, 0xC9C00000, 0xC0004950, 0xC9400080, 0xDD800001,\n    0x58000028, 0x5D9C0000, 0x8400003A, 0x5D9C0002, 0x8400003A, 0x5D9C0004, 0x84000052, 0xC55B0040,\n    0xC55C08C0, 0xCD800041, 0xCDC008C0, 0x80000048, 0xCD400000, 0x80000038, 0xC55900C0, 0xC55C1840,\n    0xCD8000C1, 0xCDC01840, 0x80000010, 0xC55A0080, 0xC55C1080, 0xCD800081, 0xCDC01080, 0x9D000000,\n    0x00000000, 0x00000000, 0x00000000, 0x59540002, 0x6994E018, 0x61C0C008, 0x4194A000, 0x5D940040,\n    0x8800FFFA, 0xC5940000, 0x9D000000, 0xCD400000, 0x00000000, 0x00000000, 0x9D000000, 0x4158A000,\n    0xCD400000, 0x00000000,\n};\n\nstatic unsigned int danube_fw_data[] = {\n};\n\n\n#endif  //  IFXMIPS_ATM_FW_DANUBE_H\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-atm/src/ifxmips_atm_fw_danube_retx.h",
    "content": "#ifndef IFXMIPS_ATM_FW_DANUBE_H\n#define IFXMIPS_ATM_FW_DANUBE_H\n\n\n/******************************************************************************\n**\n** FILE NAME    : ifxmips_atm_fw_danube.h\n** PROJECT      : Danube\n** MODULES     \t: ATM (ADSL)\n**\n** DATE         : 1 AUG 2005\n** AUTHOR       : Xu Liang\n** DESCRIPTION  : ATM Driver (PP32 Firmware)\n** COPYRIGHT    : \tCopyright (c) 2006\n**\t\t\tInfineon Technologies AG\n**\t\t\tAm Campeon 1-12, 85579 Neubiberg, Germany\n**\n**    This program is free software; you can redistribute it and/or modify\n**    it under the terms of the GNU General Public License as published by\n**    the Free Software Foundation; either version 2 of the License, or\n**    (at your option) any later version.\n**\n** HISTORY\n** $Date        $Author         $Comment\n**  4 AUG 2005  Xu Liang        Initiate Version\n** 23 OCT 2006  Xu Liang        Add GPL header.\n*******************************************************************************/\n\n\n#define VER_IN_FIRMWARE         1\n\n#define ATM_FW_VER_MAJOR        0\n#define ATM_FW_VER_MINOR        15\n\n\nstatic unsigned int firmware_binary_code[] = {\n    0x800004A0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x8000FFC8, 0x00000000, 0x00000000, 0x00000000,\n    0xC1000002, 0xD90C0000, 0xC2000002, 0xDA080001, 0xC0001B50, 0x8C100000, 0x00000000, 0x00000000,\n    0x00000000, 0xC2000000, 0xDA080001, 0x80006018, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0x80005FF0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0xC1001DA6, 0x8D3C0000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0x80005EF0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0xC0400000, 0xC0004840, 0xC8840000, 0xC2001AEE, 0x8E100000, 0x00000000, 0x00000000, 0x00000000,\n    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0xC0400002, 0xC0004840, 0xC8840000, 0xC2001AEE, 0x8E100000, 0x00000000, 0x00000000, 0x00000000,\n    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0xC3C00004, 0xDBC80001, 0xC10C0002, 0xD90C0000, 0x8000FEC8, 0x00000000, 0x00000000, 0x00000000,\n    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0xC10E0002, 0xD90C0000, 0xC0004808, 0xC8400000, 0xC2001B4C, 0x8E100000, 0x00000000, 0x00000000,\n    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0xC3E1FFFE, 0x597DFFFE, 0x593DFE14, 0x900004D9, 0x00000000, 0x00000000, 0x00000000, 0x90CC0481,\n    0x00000000, 0x00000000, 0x00000000, 0xC3E02252, 0x5BFC001E, 0xC0004002, 0xCFC00000, 0xC3C00000,\n    0xDBC80001, 0xC1400008, 0xC1900000, 0x71948000, 0x15000100, 0xC140000A, 0xC1900002, 0x71948000,\n    0x15000100, 0xC140000C, 0xC1900004, 0x71948000, 0x15000100, 0xC1400004, 0xC1900006, 0x71948000,\n    0x15000100, 0xC1400006, 0xC1900008, 0x71948000, 0x15000100, 0xC140000E, 0xC190000A, 0x71948000,\n    0x15000100, 0xC1400000, 0xC190000C, 0x71948000, 0x15000100, 0xC1400002, 0xC190000E, 0x71948000,\n    0x15000100, 0xC0400000, 0xC11C0000, 0xC000082C, 0xCD040E08, 0xC11C0002, 0xC000082C, 0xCD040E08,\n    0xC0400002, 0xC11C0000, 0xC000082C, 0xCD040E08, 0xC0000824, 0x00000000, 0xCBC00001, 0xCB800001,\n    0xCB400001, 0xCB000000, 0xC0004878, 0x5BFC4000, 0xCFC00001, 0x5BB84000, 0xCF800001, 0x5B744000,\n    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0x6FD44000, 0x4575A000,\n    0x47F5A000, 0x5B744E20, 0xC2800000, 0x58340006, 0xCA800080, 0xC2000000, 0xC0004900, 0xCE000108,\n    0x5EA80002, 0x58340006, 0xC6900080, 0xCD000080, 0x5A7C0020, 0xC2000002, 0x6A250000, 0xC0000408,\n    0xCE000000, 0xC0000032, 0xDCA80001, 0xC1000002, 0x46914000, 0x00000000, 0x8C100006, 0x00000000,\n    0x00000000, 0x00000000, 0xA4800210, 0x00000000, 0xC3C00000, 0xC000140E, 0xCBC00020, 0xC3400000,\n    0xC2400000, 0x6FF86000, 0x47F9C000, 0x5BB84C80, 0x58380008, 0xCB400080, 0x58380006, 0xCA400080,\n    0x5F740002, 0x58380008, 0xC7500080, 0xCD000080, 0xC2000000, 0x58380004, 0xCA020080, 0xC3000000,\n    0x5838000C, 0xCB000028, 0x5A640002, 0x46250000, 0x8400FFF8, 0xC2400000, 0x58380006, 0xC6500080,\n    0xCD000080, 0xC2000000, 0x5838000A, 0xCA020080, 0x5B300002, 0x5838000C, 0xC7100028, 0xCD000028,\n    0xC2420020, 0x5A200004, 0x46612000, 0x8400FFF8, 0xC2000000, 0x5838000A, 0xC6101080, 0xCD001080,\n    0xC0004966, 0xCA400000, 0xC2000002, 0x6A3D0000, 0x72252000, 0xCE400000, 0x5F740000, 0x84000028,\n    0xC0004912, 0xCA000000, 0xC2C00002, 0x6AFD6000, 0x7EC16000, 0x76E10000, 0xCE000000, 0x5F300020,\n    0x84000028, 0xC0004924, 0xCA000000, 0xC2C00002, 0x6AFD6000, 0x7EC16000, 0x76E10000, 0xCE000000,\n    0xA4820050, 0xC2400000, 0xC000140E, 0xCA408020, 0xC2000002, 0xC0004900, 0xCE000008, 0xC000490A,\n    0xCE400000, 0xC1000000, 0xD9000001, 0xD8400080, 0xC1000004, 0xD9000001, 0xA4840288, 0x00000000,\n    0xC3C00000, 0xC000140E, 0xCBC10020, 0xC2800000, 0xC2000000, 0x6FF8A000, 0x6FD44000, 0x4579C000,\n    0x47F9C000, 0x5BB84E20, 0x5838002E, 0xCA800080, 0x58380006, 0xCA020080, 0xC3400000, 0x5838002E,\n    0xCB420080, 0x5AA80002, 0x46290000, 0x8400FFF8, 0xC2800000, 0x5838002E, 0xC6900080, 0xCD000080,\n    0x5F740002, 0x5838002E, 0xC7501080, 0xCD001080, 0xC0004968, 0xCA400000, 0xC2000002, 0x6A3D0000,\n    0x72252000, 0xCE400000, 0xC000492A, 0xCA800000, 0x5E740000, 0x84000028, 0xC0004910, 0xCA000000,\n    0xC2C00002, 0x6AFD6000, 0x7EC16000, 0x76E10000, 0xCE000000, 0x6ABD4010, 0xA68000D2, 0x00000000,\n    0xC0004910, 0xCA000000, 0xC2C00002, 0x6AFD6000, 0x7EC16000, 0x76E10000, 0xCE000000, 0x58380032,\n    0xCA000000, 0x58000002, 0xCA400000, 0x5838000C, 0x00000000, 0xCE000001, 0xCE400000, 0xC000492A,\n    0xCA000000, 0xC2C00002, 0x6AFD6000, 0x72E10000, 0xCE000000, 0xC000492C, 0xCA000000, 0xC2C00002,\n    0x6AFD6000, 0x72E10000, 0xCE000000, 0x80000028, 0xC000492C, 0xCA000000, 0xC2C00002, 0x6AFD6000,\n    0x7EC16000, 0x76E10000, 0xCE000000, 0xA4880100, 0xC2C00000, 0xC000140E, 0xCAC20020, 0xC000490E,\n    0xCA400000, 0xC2000002, 0x6A2D0000, 0x7E010000, 0x76252000, 0xCE400000, 0xC000496A, 0xCA400000,\n    0xC2000002, 0x6A2D0000, 0x72252000, 0xCE400000, 0x6EF0A000, 0x6ED44000, 0x45718000, 0x46F18000,\n    0x5B304E20, 0x58300000, 0xCA000000, 0x00000000, 0xC2400002, 0x76252000, 0x84000032, 0xC24C0002,\n    0xC6E40020, 0xC624C408, 0x58300010, 0xCA400508, 0x00000000, 0xC0001800, 0xCE400000, 0xA4860050,\n    0xC2400000, 0xC000140E, 0xCA418020, 0xC2020002, 0xC0004900, 0xCE000108, 0xC0004908, 0xCE400000,\n    0xC1000000, 0xD9000001, 0xD8400080, 0xC1000004, 0xD9000001, 0xA48C0028, 0xC2800002, 0xC000484A,\n    0xCE800000, 0xC2800000, 0xC000474A, 0xCE800000, 0xC0004846, 0xCE800000, 0xC0001408, 0xCC800000,\n    0xC10E0002, 0xD90C0000, 0x8000EA60, 0xDFBC0001, 0xC000496E, 0x99008638, 0xC9400000, 0xC7D80000,\n    0x00000000, 0xC5700000, 0x5EF00020, 0x88000130, 0x6F346000, 0x4735A000, 0x5B744C80, 0x58340008,\n    0xC2400000, 0xCA400080, 0x00000000, 0xC2000000, 0x5A640002, 0xCE400080, 0x58340004, 0xCA000080,\n    0x00000000, 0x00000000, 0x5E200002, 0xCE000080, 0xC0004912, 0xCA800000, 0xC2400002, 0x6A712000,\n    0x72694000, 0xCE800000, 0x5E200000, 0x8400003A, 0xC000480A, 0xCA000000, 0xC0000408, 0xCA800000,\n    0x76610000, 0x00000000, 0x72294000, 0xCE800000, 0x80000020, 0xC0004914, 0xCA000000, 0x7E412000,\n    0x00000000, 0x76610000, 0xCE000000, 0x800000B8, 0x6EF4A000, 0x6ED44000, 0x4575A000, 0x46F5A000,\n    0x5B744E20, 0x5834002E, 0xC2400000, 0xCA420080, 0x00000000, 0xC2000000, 0x5A640002, 0xC6501080,\n    0xCD001080, 0x58340006, 0xCA000080, 0x00000000, 0x00000000, 0x5A200002, 0xCE000080, 0xC0004910,\n    0xCA400000, 0xC2000002, 0x6A2D0000, 0x72252000, 0xCE400000, 0xC2000002, 0x6A310000, 0xC000042A,\n    0xCE000000, 0xC1040002, 0xD90C0000, 0x00000000, 0x8000E7D0, 0x00000000, 0xC4980930, 0x9D000000,\n    0xC5580030, 0xC0000838, 0xCD840000, 0xC1440200, 0xC1C03200, 0xC55C1078, 0xC000100E, 0x9D000000,\n    0xCD800000, 0xC000100C, 0xCDC00000, 0xC0004862, 0xC9C00000, 0x00000000, 0x00000000, 0xD9D80001,\n    0xC0007200, 0x401C0000, 0x5DC07400, 0x8800FFFA, 0x5C000200, 0xCD800000, 0xC1F0000A, 0x71D4A000,\n    0xDD980000, 0xDD9C0001, 0x41D8E000, 0xC5D40268, 0xC0001010, 0xCD400000, 0x6C9C8000, 0x449CE000,\n    0x449CE000, 0x59DC0004, 0xC1601260, 0xC5D40268, 0x9D000000, 0xC0001012, 0xCD400000, 0x00000000,\n    0x00000000, 0xD9580000, 0x6D586000, 0x4558C000, 0x59984C80, 0xD9980001, 0x5818000A, 0xC1800000,\n    0xC9800080, 0xC0005400, 0x6D5CA000, 0x401C0000, 0x40180000, 0xC9400000, 0x58000002, 0x00000000,\n    0xC9C00000, 0xC0004930, 0xCD400000, 0xC0004932, 0xCDC00000, 0x59980004, 0xC1C20020, 0xB59CFFF8,\n    0x00000000, 0xC1800000, 0xDD9C0001, 0x581C000A, 0xCD800080, 0x581C000C, 0xC1800000, 0xC9800028,\n    0xC1C00002, 0xDD940000, 0x69D4E000, 0x5D980002, 0xCD800028, 0xC0004924, 0xC9800000, 0x00000000,\n    0x9D000000, 0x00000000, 0x71D8C000, 0xCD800000, 0xC000492A, 0xC9400000, 0xC1C00002, 0x69D8E000,\n    0x7DC0C000, 0x7594A000, 0xCD400000, 0xC000492C, 0xC9400000, 0xDD800001, 0x58000032, 0x75D4A000,\n    0x84000078, 0xC9400001, 0xC9800000, 0xDD800001, 0x5800000C, 0x00000000, 0xCD400001, 0xCD800000,\n    0xC000492C, 0xC9400000, 0xC000492A, 0xC9800000, 0x71D4A000, 0xC000492C, 0xCD400000, 0x71D8C000,\n    0xC000492A, 0xCD800000, 0x9D000000, 0x00000000, 0x00000000, 0x00000000, 0xC0004862, 0xC9800000,\n    0x00000000, 0xC1C00200, 0x4194C000, 0x45D8E000, 0x8800FFFA, 0xC5D80000, 0xC0004862, 0xCD800000,\n    0xC0001406, 0xC9800000, 0xC1C00002, 0x9D000000, 0xC5D80A08, 0xC5581050, 0xCD800000, 0xC0004930,\n    0xC9800000, 0xC0004932, 0xC9C00000, 0xC140000E, 0xC5581C20, 0xDD940000, 0xC0007200, 0x40140000,\n    0x5D407400, 0x8800FFFA, 0x5C000200, 0xCD800000, 0x58000002, 0x5D407400, 0x8800FFFA, 0x5C000200,\n    0xCDC00000, 0xDD540000, 0xC1C00000, 0x58140006, 0xC9C20080, 0xC1800000, 0x58140000, 0xC98000E0,\n    0x6DDC2000, 0xC000491E, 0x41D8E000, 0xCDC00000, 0xDD980000, 0xC1C00022, 0xC5D80D78, 0xDD940001,\n    0xC5581C20, 0xC000491C, 0xCD800000, 0xDD540000, 0xC1C00000, 0x58140006, 0xC9C20080, 0xC1800000,\n    0x58140004, 0xC9820080, 0x00000000, 0x59DC0002, 0x459CC000, 0x8400FFF8, 0xC1C00000, 0x9D000000,\n    0x58140006, 0xC5D81080, 0xCD801080, 0xC0004860, 0xC9400000, 0xC1820080, 0xC1D00002, 0x58146B00,\n    0xD5800000, 0x58000002, 0xD5800001, 0x59540004, 0xB558FFF8, 0xC0004860, 0xC1400000, 0xCD400000,\n    0xDD980001, 0x9D000000, 0xDD940000, 0xC0001404, 0xCDC00808, 0xC1C00000, 0xC1800200, 0x5D980004,\n    0xDF5D0050, 0x45D8A000, 0x8800FFDA, 0xDD800001, 0x5800000C, 0x00000000, 0xC9400001, 0xC9800000,\n    0xC1C00002, 0xC5D43F08, 0xC5D81E08, 0xC0004862, 0xC9C00000, 0x00000000, 0x00000000, 0x581C7200,\n    0x5DC07400, 0x8800FFFA, 0x5C000200, 0xCD400000, 0x58000002, 0x5DC07400, 0x8800FFFA, 0x5C000200,\n    0xCD800000, 0xC0004862, 0xC9C00000, 0x00000000, 0xC15004C0, 0xC5D40068, 0xDD9C0000, 0xC5D41C20,\n    0xC1C00000, 0xDD800001, 0x58000030, 0xC9C00080, 0xDD800001, 0x58000002, 0xC9800000, 0x6DDC2000,\n    0xC000491C, 0x41D8E000, 0xCD400001, 0xCDC00000, 0xDD940001, 0xC1C00000, 0x58140030, 0xC9C00080,\n    0xC1800000, 0x58140006, 0xC9820080, 0x00000000, 0x59DC0002, 0x459CC000, 0x8400FFF8, 0xC1C00000,\n    0x9D000000, 0x58140030, 0xC5D80080, 0xCD800080, 0xC1C00000, 0xDF5C0040, 0x5DDC0080, 0x8400FFD2,\n    0x00000000, 0x9D000000, 0x00000000, 0x00000000, 0x00000000, 0xC160FFFE, 0xC0000A10, 0xC9440068,\n    0xC1A0FFFE, 0x59980E28, 0xC000100C, 0xCD400000, 0xC000100E, 0xCD800000, 0xC0004964, 0xC9800000,\n    0x00000000, 0xC170000A, 0x7194A000, 0x6C988000, 0x4498C000, 0x4498C000, 0x59980004, 0xC5940278,\n    0xC0001010, 0xCD400000, 0xC0004946, 0xC9400000, 0x00000000, 0x00000000, 0x6D58A000, 0x6D5C4000,\n    0x45D8C000, 0x4558C000, 0xC000494A, 0xC9400000, 0xC0004948, 0xC9C00000, 0x4194C000, 0xC1400012,\n    0xC55C1820, 0x9D000000, 0xC59C0270, 0xC0001012, 0xCDC00000, 0xC1400000, 0x58000012, 0xC9410040,\n    0xC0004950, 0xC9C00000, 0xC5580000, 0xC5940840, 0xC5581080, 0xD9940000, 0xC000493C, 0xC9400000,\n    0xC0004954, 0xC9800000, 0x59DC00A8, 0x455CE000, 0x41D8E000, 0x5D5C0030, 0x8800FFF8, 0xC1C00030,\n    0xC1800000, 0xC5D84030, 0xC1400000, 0xC5D40010, 0x5DD40002, 0x8400005A, 0x5DD40004, 0x84000082,\n    0x5DD40006, 0x840000AA, 0x5DD80026, 0x840000D2, 0xDD540000, 0xDD800001, 0x58000008, 0x40180000,\n    0xCD400000, 0x59980002, 0x8000FFA8, 0xDD540000, 0xDD800001, 0x58000008, 0x40180000, 0xCD4000C0,\n    0x59980002, 0x8000FF70, 0xDD540000, 0xDD800001, 0x58000008, 0x40180000, 0xCD400080, 0x59980002,\n    0x8000FF38, 0xDD540000, 0xDD800001, 0x58000008, 0x40180000, 0xCD400040, 0x59980002, 0x8000FF00,\n    0x00000000, 0x9D000000, 0x00000000, 0x00000000, 0x00000000, 0x58000012, 0xC9400000, 0xC0004954,\n    0xC9C00000, 0xC0004950, 0xC9400080, 0xDD800001, 0x58000028, 0x5D9C0000, 0x8400003A, 0x5D9C0002,\n    0x8400003A, 0x5D9C0004, 0x84000052, 0xC55B0040, 0xC55C08C0, 0xCD800041, 0xCDC008C0, 0x80000048,\n    0xCD400000, 0x80000038, 0xC55900C0, 0xC55C1840, 0xCD8000C1, 0xCDC01840, 0x80000010, 0xC55A0080,\n    0xC55C1080, 0xCD800081, 0xCDC01080, 0x9D000000, 0x00000000, 0x00000000, 0x00000000, 0x59540002,\n    0x6994E018, 0x61C0C008, 0x4194A000, 0x5D940040, 0x8800FFFA, 0xC5940000, 0x9D000000, 0xCD400000,\n    0x00000000, 0x00000000, 0x9D000000, 0x4158A000, 0xCD400000, 0x00000000, 0xCD800001, 0x44148000,\n    0x8800FFD8, 0x00000000, 0x9CC00000, 0x00000000, 0x00000000, 0x00000000, 0xC0004810, 0xCA010040,\n    0xC241FFFE, 0xC1400000, 0x45608000, 0x00000000, 0x9CC00006, 0xC0004200, 0x40180000, 0xC9C00000,\n    0x00000000, 0x00000000, 0x61C08010, 0x84000042, 0xC2400002, 0x6A512000, 0x725CE000, 0xCDC00000,\n    0xC0004748, 0xCD800000, 0x9CC00000, 0x6D98A000, 0x5998003E, 0x45192000, 0x59540002, 0x59980002,\n    0x45A08000, 0xC1000000, 0xC5180006, 0x8000FF20, 0x00000000, 0x40180000, 0xC9C00000, 0xC2000000,\n    0xC5600028, 0xC1210000, 0x69208010, 0x7D008000, 0x751CE000, 0xCDC00000, 0x6D542000, 0x58144300,\n    0xC1000000, 0xCD000001, 0x9CC00000, 0xC121FFFE, 0x5911FFFE, 0xCD000001, 0x79948000, 0x6D10A010,\n    0x5D100000, 0x840000A8, 0x45588000, 0x88000098, 0x6D536000, 0x6D136010, 0x6D54A010, 0xC0004700,\n    0x40140000, 0xCA000000, 0x00000000, 0x00000000, 0x6A110000, 0x6A110010, 0x62008018, 0x8400001A,\n    0x00000000, 0x9CC00000, 0x6D54A000, 0x5954003E, 0x45152000, 0x59540002, 0x6D57A000, 0x6D57A010,\n    0x6D54A000, 0x6D936000, 0x6D136010, 0xC1E10000, 0x69D0E010, 0x5DDC0002, 0x7DC0E000, 0x6D98A010,\n    0x6D536000, 0x6D136010, 0x6D54A010, 0xC0004700, 0x40140000, 0xCA000000, 0x00000000, 0x00000000,\n    0x6A110000, 0x6A110010, 0x45948000, 0x00000000, 0x75E10002, 0x62008018, 0x8400001A, 0x00000000,\n    0x9CC00000, 0x6D54A000, 0x5954003E, 0x45152000, 0x45948000, 0x00000000, 0x9CC00002, 0x59540002,\n    0x6D57A000, 0x6D57A010, 0xC0004700, 0x40140000, 0xCA000000, 0x8000FF50, 0x00000000, 0x00000000,\n    0x00000000, 0x58004700, 0xC9800000, 0x9CC00000, 0x00000000, 0x6994C000, 0x6DA7E010, 0x58004700,\n    0xC9800000, 0xC1210000, 0x9CC00000, 0x69148010, 0x7118C000, 0xCD800000, 0xC1000000, 0xC0004810,\n    0xC9020040, 0x00000000, 0x00000000, 0x451CC000, 0x8800004A, 0xC2400002, 0x45948000, 0xC1000000,\n    0xC5240004, 0x455C8000, 0xC1000000, 0xC5240006, 0x9CC00000, 0x00000000, 0x00000000, 0x00000000,\n    0x59980200, 0xC2400000, 0x45D48000, 0xC1000002, 0xC5240004, 0x45588000, 0xC1000002, 0xC5240006,\n    0x9CC00000, 0x00000000, 0x00000000, 0x00000000, 0xC0004740, 0xC9C00000, 0x59180002, 0x6D130000,\n    0x6D130010, 0x45D08000, 0xC2400000, 0x9CC00002, 0x00000000, 0x00000000, 0x45D88000, 0x8800004A,\n    0xC2400002, 0x45D48000, 0xC1000000, 0xC5240004, 0x45588000, 0xC1000000, 0xC5240004, 0x9CC00000,\n    0x00000000, 0x00000000, 0x00000000, 0xC2400000, 0x45948000, 0xC1000002, 0xC5240006, 0x455C8000,\n    0xC1000002, 0xC5240006, 0x9CC00000, 0x00000000, 0x00000000, 0x00000000, 0x59540002, 0x6D570000,\n    0x6D570010, 0x45948000, 0x6D402000, 0x9CC00002, 0x58004300, 0x58000000, 0xC13C0002, 0xCD001E08,\n    0x8000FF98, 0x00000000, 0x00000000, 0x00000000, 0xC1020002, 0xD90C0000, 0xC9800000, 0x59540002,\n    0xC0004730, 0xCD400000, 0x5D980002, 0x00000000, 0x8000001E, 0x00000000, 0x9CC00000, 0xC0004732,\n    0xCD800000, 0x00000000, 0xC0004734, 0xC9C00000, 0xC1800000, 0xC0004816, 0xC9820080, 0xC0004738,\n    0xCDC00000, 0xC1C00000, 0xC0004734, 0x9CC00000, 0xCDC00000, 0xC0004732, 0xCD800000,\n};\n\nstatic unsigned int firmware_binary_data[] = {\n};\n\n\n#endif  //  IFXMIPS_ATM_FW_DANUBE_H\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-atm/src/ifxmips_atm_fw_regs_amazon_se.h",
    "content": "/******************************************************************************\n**\n** FILE NAME    : ifxmips_atm_fw_regs_amazon_se.h\n** PROJECT      : UEIP\n** MODULES     \t: ATM (ADSL)\n**\n** DATE         : 1 AUG 2005\n** AUTHOR       : Xu Liang\n** DESCRIPTION  : ATM Driver (Firmware Registers)\n** COPYRIGHT    : \tCopyright (c) 2006\n**\t\t\tInfineon Technologies AG\n**\t\t\tAm Campeon 1-12, 85579 Neubiberg, Germany\n**\n**    This program is free software; you can redistribute it and/or modify\n**    it under the terms of the GNU General Public License as published by\n**    the Free Software Foundation; either version 2 of the License, or\n**    (at your option) any later version.\n**\n** HISTORY\n** $Date        $Author         $Comment\n**  4 AUG 2005  Xu Liang        Initiate Version\n** 23 OCT 2006  Xu Liang        Add GPL header.\n**  9 JAN 2007  Xu Liang        First version got from Anand (IC designer)\n*******************************************************************************/\n\n\n\n#ifndef IFXMIPS_ATM_FW_REGS_AMAZON_SE_H\n#define IFXMIPS_ATM_FW_REGS_AMAZON_SE_H\n\n\n\n/*\n *  Host-PPE Communication Data Address Mapping\n */\n#define FW_VER_ID                       ((volatile struct fw_ver_id *)      SB_BUFFER(0x2401))  /*  Firmware Version ID */\n#define CFG_WRX_HTUTS                   SB_BUFFER(0x2400)   /*  WAN RX HTU Table Size, must be configured before enable PPE firmware.   */\n//#define CFG_WRX_QNUM                    SB_BUFFER(0x2401)   /*  WAN RX Queue Number */\n#define CFG_WRX_DCHNUM                  SB_BUFFER(0x2402)   /*  WAN RX DMA Channel Number, no more than 8, must be configured before enable PPE firmware.   */\n#define CFG_WTX_DCHNUM                  SB_BUFFER(0x2403)   /*  WAN TX DMA Channel Number, no more than 16, must be configured before enable PPE firmware.  */\n#define CFG_WRDES_DELAY                 SB_BUFFER(0x2404)   /*  WAN Descriptor Write Delay, must be configured before enable PPE firmware.  */\n#define WRX_DMACH_ON                    SB_BUFFER(0x2405)   /*  WAN RX DMA Channel Enable, must be configured before enable PPE firmware.   */\n#define WTX_DMACH_ON                    SB_BUFFER(0x2406)   /*  WAN TX DMA Channel Enable, must be configured before enable PPE firmware.   */\n#define WRX_HUNT_BITTH                  SB_BUFFER(0x2407)   /*  WAN RX HUNT Threshold, must be between 2 to 8.  */\n#define WRX_QUEUE_CONFIG(i)             ((struct wrx_queue_config*)         SB_BUFFER(0x2500 + (i) * 20))\n#define WRX_DMA_CHANNEL_CONFIG(i)       ((struct wrx_dma_channel_config*)   SB_BUFFER(0x2640 + (i) * 7))\n#define WTX_PORT_CONFIG(i)              ((struct wtx_port_config*)          SB_BUFFER(0x2440 + (i)))\n#define WTX_QUEUE_CONFIG(i)             ((struct wtx_queue_config*)         SB_BUFFER(0x2F00 + (i) * 27))\n#define WTX_DMA_CHANNEL_CONFIG(i)       ((struct wtx_dma_channel_config*)   SB_BUFFER(0x2F01 + (i) * 27))\n#define WAN_MIB_TABLE                   ((struct wan_mib_table*)            SB_BUFFER(0x2410))\n#define HTU_ENTRY(i)                    ((struct htu_entry*)                SB_BUFFER(0x3200 + (i)))\n#define HTU_MASK(i)                     ((struct htu_mask*)                 SB_BUFFER(0x3220 + (i)))\n#define HTU_RESULT(i)                   ((struct htu_result*)               SB_BUFFER(0x3240 + (i)))\n\n\n\n#endif  //  IFXMIPS_ATM_FW_REGS_AMAZON_SE_H\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-atm/src/ifxmips_atm_fw_regs_ar9.h",
    "content": "/******************************************************************************\n**\n** FILE NAME    : ifxmips_atm_fw_regs_ar9.h\n** PROJECT      : UEIP\n** MODULES     \t: ATM (ADSL)\n**\n** DATE         : 1 AUG 2005\n** AUTHOR       : Xu Liang\n** DESCRIPTION  : ATM Driver (Firmware Registers)\n** COPYRIGHT    : \tCopyright (c) 2006\n**\t\t\tInfineon Technologies AG\n**\t\t\tAm Campeon 1-12, 85579 Neubiberg, Germany\n**\n**    This program is free software; you can redistribute it and/or modify\n**    it under the terms of the GNU General Public License as published by\n**    the Free Software Foundation; either version 2 of the License, or\n**    (at your option) any later version.\n**\n** HISTORY\n** $Date        $Author         $Comment\n**  4 AUG 2005  Xu Liang        Initiate Version\n** 23 OCT 2006  Xu Liang        Add GPL header.\n**  9 JAN 2007  Xu Liang        First version got from Anand (IC designer)\n*******************************************************************************/\n\n\n\n#ifndef IFXMIPS_ATM_FW_REGS_AR9_H\n#define IFXMIPS_ATM_FW_REGS_AR9_H\n\n\n\n/*\n *  Host-PPE Communication Data Address Mapping\n */\n#define FW_VER_ID                       ((volatile struct fw_ver_id *)      SB_BUFFER(0x2001))\n#define CFG_WRX_HTUTS                   SB_BUFFER(0x2400)   /*  WAN RX HTU Table Size, must be configured before enable PPE firmware.   */\n#define CFG_WRX_QNUM                    SB_BUFFER(0x2401)   /*  WAN RX Queue Number */\n#define CFG_WRX_DCHNUM                  SB_BUFFER(0x2402)   /*  WAN RX DMA Channel Number, no more than 8, must be configured before enable PPE firmware.   */\n#define CFG_WTX_DCHNUM                  SB_BUFFER(0x2403)   /*  WAN TX DMA Channel Number, no more than 16, must be configured before enable PPE firmware.  */\n#define CFG_WRDES_DELAY                 SB_BUFFER(0x2404)   /*  WAN Descriptor Write Delay, must be configured before enable PPE firmware.  */\n#define WRX_DMACH_ON                    SB_BUFFER(0x2405)   /*  WAN RX DMA Channel Enable, must be configured before enable PPE firmware.   */\n#define WTX_DMACH_ON                    SB_BUFFER(0x2406)   /*  WAN TX DMA Channel Enable, must be configured before enable PPE firmware.   */\n#define WRX_HUNT_BITTH                  SB_BUFFER(0x2407)   /*  WAN RX HUNT Threshold, must be between 2 to 8.  */\n#define WRX_QUEUE_CONFIG(i)             ((struct wrx_queue_config*)         SB_BUFFER(0x2500 + (i) * 20))\n#define WRX_QUEUE_CONTEXT(i)            ((struct wrx_queue_context*)        SB_BUFFER(0x2504 + (i) * 20))\n#define WRX_DMA_CHANNEL_CONFIG(i)       ((struct wrx_dma_channel_config*)   SB_BUFFER(0x2640 + (i) * 7))\n#define WRX_DESC_CONTEXT(i)             ((struct wrx_desc_context*)         SB_BUFFER(0x2643 + (i) * 7))\n#define WTX_PORT_CONFIG(i)              ((struct wtx_port_config*)          SB_BUFFER(0x2440 + (i)))\n#define WTX_QUEUE_CONFIG(i)             ((struct wtx_queue_config*)         SB_BUFFER(0x3800 + (i) * 27))\n#define WTX_DMA_CHANNEL_CONFIG(i)       ((struct wtx_dma_channel_config*)   SB_BUFFER(0x3801 + (i) * 27))\n#define WAN_MIB_TABLE                   ((struct wan_mib_table*)            SB_BUFFER(0x2410))\n#define HTU_ENTRY(i)                    ((struct htu_entry*)                SB_BUFFER(0x2010 + (i)))\n#define HTU_MASK(i)                     ((struct htu_mask*)                 SB_BUFFER(0x2030 + (i)))\n#define HTU_RESULT(i)                   ((struct htu_result*)               SB_BUFFER(0x2050 + (i)))\n\n#if defined(ENABLE_ATM_RETX) && ENABLE_ATM_RETX\n\n  #define RETX_MODE_CFG                     ((volatile struct Retx_mode_cfg *)      SB_BUFFER(0x2408))\n  #define RETX_TSYNC_CFG                    ((volatile struct Retx_Tsync_cfg *)     SB_BUFFER(0x2409))\n  #define RETX_TD_CFG                       ((volatile struct Retx_Td_cfg *)        SB_BUFFER(0x240A))\n  #define RETX_MIB_TIMER_CFG                ((volatile struct Retx_MIB_Timer_cfg *) SB_BUFFER(0x240B))\n  #define RETX_PLAYOUT_BUFFER_BASE          SB_BUFFER(0x240D)\n  #define RETX_SERVICE_HEADER_CFG           SB_BUFFER(0x240E)\n  #define RETX_MASK_HEADER_CFG              SB_BUFFER(0x240F)\n\n  #define RETX_ADSL_PPE_INTF                ((volatile struct Retx_adsl_ppe_intf *) PPE_REG_ADDR(0x0D78))\n  #define BAD_REC_RETX_ADSL_PPE_INTF        ((volatile struct Retx_adsl_ppe_intf *) SB_BUFFER(0x23AC))\n  #define FIRST_BAD_REC_RETX_ADSL_PPE_INTF  ((volatile struct Retx_adsl_ppe_intf *) SB_BUFFER(0x23AE))\n\n  #define PB_BUFFER_USAGE                   SB_BUFFER(0x2100)\n  #define DTU_STAT_INFO                     ((volatile struct DTU_stat_info *)      SB_BUFFER(0x2180))\n  #define DTU_VLD_STAT                      SB_BUFFER(0x2380)\n\n\n  //=====================================================================\n  // retx firmware mib, for debug purpose\n  //      address : 0x2388 - 0x238F\n  //      size    : 8\n  //=====================================================================\n  #define URETX_RX_TOTAL_DTU                    SB_BUFFER(0x2388)\n  #define URETX_RX_BAD_DTU                      SB_BUFFER(0x2389)\n  #define URETX_RX_GOOD_DTU                     SB_BUFFER(0x238A)\n  #define URETX_RX_CORRECTED_DTU                SB_BUFFER(0x238B)\n  #define URETX_RX_OUTOFDATE_DTU                SB_BUFFER(0x238C)\n  #define URETX_RX_DUPLICATE_DTU                SB_BUFFER(0x238D)\n  #define URETX_RX_TIMEOUT_DTU                  SB_BUFFER(0x238E)\n\n  #define URETX_ALPHA_SWITCH_TO_HUNT_TIMES      SB_BUFFER(0x238F)\n\n  // cell counter for debug purpose\n  #define WRX_BC0_CELL_NUM                      SB_BUFFER(0x23E0)\n  #define WRX_BC0_DROP_CELL_NUM                 SB_BUFFER(0x23E1)\n  #define WRX_BC0_NONRETX_CELL_NUM              SB_BUFFER(0x23E2)\n  #define WRX_BC0_RETX_CELL_NUM                 SB_BUFFER(0x23E3)\n  #define WRX_BC0_OUTOFDATE_CELL_NUM            SB_BUFFER(0x23E4)\n  #define WRX_BC0_DIRECTUP_NUM                  SB_BUFFER(0x23E5)\n  #define WRX_BC0_PBW_TOTAL_NUM                 SB_BUFFER(0x23E6)\n  #define WRX_BC0_PBW_SUCC_NUM                  SB_BUFFER(0x23E7)\n  #define WRX_BC0_PBW_FAIL_NUM                  SB_BUFFER(0x23E8)\n  #define WRX_BC1_CELL_NUM                      SB_BUFFER(0x23E9)\n\n  // debug info (interface)\n\n  #define DBG_DTU_INTF_WRPTR                    SB_BUFFER(0x2390)\n  #define DBG_INTF_FCW_DUP_CNT                  SB_BUFFER(0x2391)\n  #define DBG_INTF_SID_CHANGE_IN_DTU_CNT        SB_BUFFER(0x2392)\n  #define DBG_INTF_LCW_DUP_CNT                  SB_BUFFER(0x2393)\n\n  #define DBG_RFBI_DONE_INT_CNT                 SB_BUFFER(0x2394)\n  #define DBG_DREG_BEG_END                      SB_BUFFER(0x2395)\n  #define DBG_RFBI_BC0_INVALID_CNT              SB_BUFFER(0x2396)\n  #define DBG_RFBI_LAST_T                       SB_BUFFER(0x2397)\n\n  #define DBG_RFBI_INTV0                        SB_BUFFER(0x23EE)\n  #define DBG_RFBI_INTV1                        SB_BUFFER(0x23EF)\n\n  #define DBG_INTF_INFO(i)                      ((volatile struct Retx_adsl_ppe_intf_rec *) SB_BUFFER(0x23F0 + i))\n\n  // Internal status\n  #define URetx_curr_time                       SB_BUFFER(0x2398)\n  #define URetx_sec_counter                     SB_BUFFER(0x2399)\n  #define RxCURR_EFB                            SB_BUFFER(0x239A)\n  #define RxDTURetransmittedCNT                 SB_BUFFER(0x239B)\n\n  //=====================================================================\n  // standardized MIB counter\n  //      address : 0x239C - 0x239F\n  //      size    : 4\n  //=====================================================================\n  #define RxLastEFBCNT                          SB_BUFFER(0x239C)\n  #define RxDTUCorrectedCNT                     SB_BUFFER(0x239D)\n  #define RxDTUCorruptedCNT                     SB_BUFFER(0x239E)\n  #define RxRetxDTUUncorrectedCNT               SB_BUFFER(0x239F)\n\n\n  //=====================================================================\n  // General URetx Context\n  //      address : 0x23A0 - 0x23AF\n  //      size    : 16\n  //=====================================================================\n  #define NEXT_DTU_SID_OUT                      SB_BUFFER(0x23A0)\n  #define LAST_DTU_SID_IN                       SB_BUFFER(0x23A1)\n  #define NEXT_CELL_SID_OUT                     SB_BUFFER(0x23A2)\n  #define ISR_CELL_ID                           SB_BUFFER(0x23A3)\n  #define PB_CELL_SEARCH_IDX                    SB_BUFFER(0x23A4)\n  #define PB_READ_PEND_FLAG                     SB_BUFFER(0x23A5)\n  #define RFBI_FIRST_CW                         SB_BUFFER(0x23A6)\n  #define RFBI_BAD_CW                           SB_BUFFER(0x23A7)\n  #define RFBI_INVALID_CW                       SB_BUFFER(0x23A8)\n  #define RFBI_RETX_CW                          SB_BUFFER(0x23A9)\n  #define RFBI_CHK_DTU_STATUS                   SB_BUFFER(0x23AA)\n\n  //=====================================================================\n  // per PVC counter for RX error_pdu and correct_pdu\n  //      address : 0x23B0 - 0x23CF\n  //      size    : 32\n  //=====================================================================\n  #define WRX_PER_PVC_CORRECT_PDU_BASE          SB_BUFFER(0x23B0)\n  #define WRX_PER_PVC_ERROR_PDU_BASE            SB_BUFFER(0x23C0)\n\n  #define __WRXCTXT_L2_RdPtr(i)                 SB_BUFFER(0x2422 + (i))\n  #define __WRXCTXT_L2Pages(i)                  SB_BUFFER(0x2424 + (i))\n\n  #define __WTXCTXT_TC_WRPTR(i)                 SB_BUFFER(0x2450 + (i))\n  #define __WRXCTXT_PortState(i)                SB_BUFFER(0x242A + (i))\n\n#endif\n\n\n\n#endif  //  IFXMIPS_ATM_FW_REGS_AR9_H\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-atm/src/ifxmips_atm_fw_regs_common.h",
    "content": "/******************************************************************************\n**\n** FILE NAME    : ifxmips_atm_fw_regs_common.h\n** PROJECT      : UEIP\n** MODULES     \t: ATM (ADSL)\n**\n** DATE         : 1 AUG 2005\n** AUTHOR       : Xu Liang\n** DESCRIPTION  : ATM Driver (Firmware Register Structures)\n** COPYRIGHT    : \tCopyright (c) 2006\n**\t\t\tInfineon Technologies AG\n**\t\t\tAm Campeon 1-12, 85579 Neubiberg, Germany\n**\n**    This program is free software; you can redistribute it and/or modify\n**    it under the terms of the GNU General Public License as published by\n**    the Free Software Foundation; either version 2 of the License, or\n**    (at your option) any later version.\n**\n** HISTORY\n** $Date        $Author         $Comment\n**  4 AUG 2005  Xu Liang        Initiate Version\n** 23 OCT 2006  Xu Liang        Add GPL header.\n**  9 JAN 2007  Xu Liang        First version got from Anand (IC designer)\n*******************************************************************************/\n\n\n\n#ifndef IFXMIPS_ATM_FW_REGS_COMMON_H\n#define IFXMIPS_ATM_FW_REGS_COMMON_H\n\n\n#if defined(CONFIG_DANUBE)\n  #include \"ifxmips_atm_fw_regs_danube.h\"\n#elif defined(CONFIG_AMAZON_SE)\n  #include \"ifxmips_atm_fw_regs_amazon_se.h\"\n#elif defined(CONFIG_AR9)\n  #include \"ifxmips_atm_fw_regs_ar9.h\"\n#elif defined(CONFIG_VR9)\n  #include \"ifxmips_atm_fw_regs_vr9.h\"\n#else\n  #error Platform is not specified!\n#endif\n\n\n\n/*\n *  PPE ATM Cell Header\n */\n#if defined(__BIG_ENDIAN)\n    struct uni_cell_header {\n        unsigned int        gfc     :4;\n        unsigned int        vpi     :8;\n        unsigned int        vci     :16;\n        unsigned int        pti     :3;\n        unsigned int        clp     :1;\n    };\n#else\n    struct uni_cell_header {\n        unsigned int        clp     :1;\n        unsigned int        pti     :3;\n        unsigned int        vci     :16;\n        unsigned int        vpi     :8;\n        unsigned int        gfc     :4;\n    };\n#endif  //  defined(__BIG_ENDIAN)\n\n/*\n *  Inband Header and Trailer\n */\n#if defined(__BIG_ENDIAN)\n    struct rx_inband_trailer {\n        /*  0 - 3h  */\n        unsigned int        uu      :8;\n        unsigned int        cpi     :8;\n        unsigned int        stw_res1:4;\n        unsigned int        stw_clp :1;\n        unsigned int        stw_ec  :1;\n        unsigned int        stw_uu  :1;\n        unsigned int        stw_cpi :1;\n        unsigned int        stw_ovz :1;\n        unsigned int        stw_mfl :1;\n        unsigned int        stw_usz :1;\n        unsigned int        stw_crc :1;\n        unsigned int        stw_il  :1;\n        unsigned int        stw_ra  :1;\n        unsigned int        stw_res2:2;\n        /*  4 - 7h  */\n        unsigned int        gfc     :4;\n        unsigned int        vpi     :8;\n        unsigned int        vci     :16;\n        unsigned int        pti     :3;\n        unsigned int        clp     :1;\n    };\n\n    struct tx_inband_header {\n        /*  0 - 3h  */\n        unsigned int        gfc     :4;\n        unsigned int        vpi     :8;\n        unsigned int        vci     :16;\n        unsigned int        pti     :3;\n        unsigned int        clp     :1;\n        /*  4 - 7h  */\n        unsigned int        uu      :8;\n        unsigned int        cpi     :8;\n        unsigned int        pad     :8;\n        unsigned int        res1    :8;\n    };\n#else\n    struct rx_inband_trailer {\n        /*  0 - 3h  */\n        unsigned int        stw_res2:2;\n        unsigned int        stw_ra  :1;\n        unsigned int        stw_il  :1;\n        unsigned int        stw_crc :1;\n        unsigned int        stw_usz :1;\n        unsigned int        stw_mfl :1;\n        unsigned int        stw_ovz :1;\n        unsigned int        stw_cpi :1;\n        unsigned int        stw_uu  :1;\n        unsigned int        stw_ec  :1;\n        unsigned int        stw_clp :1;\n        unsigned int        stw_res1:4;\n        unsigned int        cpi     :8;\n        unsigned int        uu      :8;\n        /*  4 - 7h  */\n        unsigned int        clp     :1;\n        unsigned int        pti     :3;\n        unsigned int        vci     :16;\n        unsigned int        vpi     :8;\n        unsigned int        gfc     :4;\n    };\n\n    struct tx_inband_header {\n        /*  0 - 3h  */\n        unsigned int        clp     :1;\n        unsigned int        pti     :3;\n        unsigned int        vci     :16;\n        unsigned int        vpi     :8;\n        unsigned int        gfc     :4;\n        /*  4 - 7h  */\n        unsigned int        res1    :8;\n        unsigned int        pad     :8;\n        unsigned int        cpi     :8;\n        unsigned int        uu      :8;\n    };\n#endif  //  defined(__BIG_ENDIAN)\n\n/*\n *  MIB Table Maintained by Firmware\n */\nstruct wan_mib_table {\n    u32                     res1;\n    u32                     wrx_drophtu_cell;\n    u32                     wrx_dropdes_pdu;\n    u32                     wrx_correct_pdu;\n    u32                     wrx_err_pdu;\n    u32                     wrx_dropdes_cell;\n    u32                     wrx_correct_cell;\n    u32                     wrx_err_cell;\n    u32                     wrx_total_byte;\n    u32                     res2;\n    u32                     wtx_total_pdu;\n    u32                     wtx_total_cell;\n    u32                     wtx_total_byte;\n};\n\n/*\n *  Host-PPE Communication Data Structure\n */\n\n#if defined(__BIG_ENDIAN)\n    struct fw_ver_id {\n        unsigned int    family      :4;\n        unsigned int    fwtype      :4;\n        unsigned int    interface   :4;\n        unsigned int    fwmode      :4;\n        unsigned int    major       :8;\n        unsigned int    minor       :8;\n    };\n\n    struct wrx_queue_config {\n        /*  0h  */\n        unsigned int    res2        :27;\n        unsigned int    dmach       :4;\n        unsigned int    errdp       :1;\n        /*  1h  */\n        unsigned int    oversize    :16;\n        unsigned int    undersize   :16;\n        /*  2h  */\n        unsigned int    res1        :16;\n        unsigned int    mfs         :16;\n        /*  3h  */\n        unsigned int    uumask      :8;\n        unsigned int    cpimask     :8;\n        unsigned int    uuexp       :8;\n        unsigned int    cpiexp      :8;\n    };\n\n    struct wrx_queue_context {\n        /*  0h  */\n        unsigned int    curr_len    :16;\n        unsigned int    res0        :12;\n        unsigned int    mfs         :1;\n        unsigned int    ec          :1;\n        unsigned int    clp1        :1;\n        unsigned int    aal5dp      :1;\n\n        /*  1h  */\n        unsigned int    intcrc;\n\n        /*  2h, 3h  */\n        unsigned int    curr_des0;\n        unsigned int    curr_des1;\n\n        /*  4h - 0xE    */\n        unsigned int    res1[11];\n\n        unsigned int    last_dword;\n    };\n\n    struct wtx_port_config {\n        unsigned int    res1        :27;\n        unsigned int    qid         :4;\n        unsigned int    qsben       :1;\n    };\n\n    struct wtx_queue_config {\n        unsigned int    res1        :16;\n        unsigned int    same_vc_qmap:8;\n        unsigned int    res2        :1;\n        unsigned int    sbid        :1;\n        unsigned int    qsb_vcid    :4; //  Which QSB queue (VCID) does this TX queue map to.\n        unsigned int    res3        :1;\n        unsigned int    qsben       :1;\n    };\n\n    struct wrx_desc_context {\n        unsigned int dmach_wrptr    : 16;\n        unsigned int dmach_rdptr    : 16;\n\n        unsigned int res0           : 16;\n        unsigned int dmach_fcnt     : 16;\n\n        unsigned int res1           : 11;\n        unsigned int desbuf_wrptr   : 5;\n        unsigned int res2           : 11;\n        unsigned int desbuf_rdptr   : 5;\n\n        unsigned int res3           : 27;\n        unsigned int desbuf_vcnt    : 5;\n    };\n\n    struct wrx_dma_channel_config {\n        /*  0h  */\n        unsigned int    res1        :1;\n        unsigned int    mode        :2;\n        unsigned int    rlcfg       :1;\n        unsigned int    desba       :28;\n        /*  1h  */\n        unsigned int    chrl        :16;\n        unsigned int    clp1th      :16;\n        /*  2h  */\n        unsigned int    deslen      :16;\n        unsigned int    vlddes      :16;\n    };\n\n    struct wtx_dma_channel_config {\n        /*  0h  */\n        unsigned int    res2        :1;\n        unsigned int    mode        :2;\n        unsigned int    res3        :1;\n        unsigned int    desba       :28;\n        /*  1h  */\n        unsigned int    res1        :32;\n        /*  2h  */\n        unsigned int    deslen      :16;\n        unsigned int    vlddes      :16;\n    };\n\n    struct htu_entry {\n        unsigned int    res1        :1;\n        unsigned int    clp         :1;\n        unsigned int    pid         :2;\n        unsigned int    vpi         :8;\n        unsigned int    vci         :16;\n        unsigned int    pti         :3;\n        unsigned int    vld         :1;\n    };\n\n    struct htu_mask {\n        unsigned int    set         :1;\n        unsigned int    clp         :1;\n        unsigned int    pid_mask    :2;\n        unsigned int    vpi_mask    :8;\n        unsigned int    vci_mask    :16;\n        unsigned int    pti_mask    :3;\n        unsigned int    clear       :1;\n    };\n\n   struct htu_result {\n        unsigned int    res1        :12;\n        unsigned int    cellid      :4;\n        unsigned int    res2        :5;\n        unsigned int    type        :1;\n        unsigned int    ven         :1;\n        unsigned int    res3        :5;\n        unsigned int    qid         :4;\n    };\n\n    struct rx_descriptor {\n        /*  0 - 3h  */\n        unsigned int    own         :1;\n        unsigned int    c           :1;\n        unsigned int    sop         :1;\n        unsigned int    eop         :1;\n        unsigned int    res1        :3;\n        unsigned int    byteoff     :2;\n        unsigned int    res2        :2;\n        unsigned int    id          :4;\n        unsigned int    err         :1;\n        unsigned int    datalen     :16;\n        /*  4 - 7h  */\n        unsigned int    res3        :4;\n        unsigned int    dataptr     :28;\n    };\n\n    struct tx_descriptor {\n        /*  0 - 3h  */\n        unsigned int    own         :1;\n        unsigned int    c           :1;\n        unsigned int    sop         :1;\n        unsigned int    eop         :1;\n        unsigned int    byteoff     :5;\n        unsigned int    res1        :5;\n        unsigned int    iscell      :1;\n        unsigned int    clp         :1;\n        unsigned int    datalen     :16;\n        /*  4 - 7h  */\n        unsigned int    res2        :4;\n        unsigned int    dataptr     :28;\n    };\n#else\n    struct wrx_queue_config {\n        /*  0h  */\n        unsigned int    errdp       :1;\n        unsigned int    dmach       :4;\n        unsigned int    res2        :27;\n        /*  1h  */\n        unsigned int    undersize   :16;\n        unsigned int    oversize    :16;\n        /*  2h  */\n        unsigned int    mfs         :16;\n        unsigned int    res1        :16;\n        /*  3h  */\n        unsigned int    cpiexp      :8;\n        unsigned int    uuexp       :8;\n        unsigned int    cpimask     :8;\n        unsigned int    uumask      :8;\n    };\n\n    struct wtx_port_config {\n        unsigned int    qsben       :1;\n        unsigned int    qid         :4;\n        unsigned int    res1        :27;\n    };\n\n    struct wtx_queue_config {\n        unsigned int    qsben       :1;\n        unsigned int    res3        :1;\n        unsigned int    qsb_vcid    :4; //  Which QSB queue (VCID) does this TX queue map to.\n        unsigned int    sbid        :1;\n        unsigned int    res2        :1;\n        unsigned int    same_vc_qmap:8;\n        unsigned int    res1        :16;\n    };\n\n    struct wrx_dma_channel_config\n    {\n        /*  0h  */\n        unsigned int    desba       :28;\n        unsigned int    rlcfg       :1;\n        unsigned int    mode        :2;\n        unsigned int    res1        :1;\n        /*  1h  */\n        unsigned int    clp1th      :16;\n        unsigned int    chrl        :16;\n        /*  2h  */\n        unsigned int    vlddes      :16;\n        unsigned int    deslen      :16;\n    };\n\n    struct wtx_dma_channel_config {\n        /*  0h  */\n        unsigned int    desba       :28;\n        unsigned int    res3        :1;\n        unsigned int    mode        :2;\n        unsigned int    res2        :1;\n        /*  1h  */\n        unsigned int    res1        :32;\n        /*  2h  */\n        unsigned int    vlddes      :16;\n        unsigned int    deslen      :16;\n    };\n\n    struct rx_descriptor {\n        /*  4 - 7h  */\n        unsigned int    dataptr     :28;\n        unsigned int    res3        :4;\n        /*  0 - 3h  */\n        unsigned int    datalen     :16;\n        unsigned int    err         :1;\n        unsigned int    id          :4;\n        unsigned int    res2        :2;\n        unsigned int    byteoff     :2;\n        unsigned int    res1        :3;\n        unsigned int    eop         :1;\n        unsigned int    sop         :1;\n        unsigned int    c           :1;\n        unsigned int    own         :1;\n    };\n\n    struct tx_descriptor {\n        /*  4 - 7h  */\n        unsigned int    dataptr     :28;\n        unsigned int    res2        :4;\n        /*  0 - 3h  */\n        unsigned int    datalen     :16;\n        unsigned int    clp         :1;\n        unsigned int    iscell      :1;\n        unsigned int    res1        :5;\n        unsigned int    byteoff     :5;\n        unsigned int    eop         :1;\n        unsigned int    sop         :1;\n        unsigned int    c           :1;\n        unsigned int    own         :1;\n    };\n#endif  //  defined(__BIG_ENDIAN)\n\n#if defined(ENABLE_ATM_RETX) && ENABLE_ATM_RETX\n  #if defined(__BIG_ENDIAN)\n\n    struct Retx_adsl_ppe_intf {\n        unsigned int res0_0             : 16;\n        unsigned int dtu_sid            : 8;\n        unsigned int dtu_timestamp      : 8;\n\n        unsigned int res1_0             : 16;\n        unsigned int local_time         : 8;\n        unsigned int res1_1             : 5;\n        unsigned int is_last_cw         : 1;\n        unsigned int reinit_flag        : 1;\n        unsigned int is_bad_cw          : 1;\n    };\n\n    struct Retx_adsl_ppe_intf_rec {\n\n        unsigned int local_time         : 8;\n        unsigned int res1_1             : 5;\n        unsigned int is_last_cw         : 1;\n        unsigned int reinit_flag        : 1;\n        unsigned int is_bad_cw          : 1;\n\n        unsigned int dtu_sid            : 8;\n        unsigned int dtu_timestamp      : 8;\n\n    };\n\n    struct Retx_mode_cfg {\n        unsigned int    res0            :8;\n        unsigned int    invld_range     :8;     //  used for rejecting the too late arrival of the retransmitted DTU\n        unsigned int    buff_size       :8;     //  the total number of cells in playout buffer is 32 * buff_size\n        unsigned int    res1            :7;\n        unsigned int    retx_en         :1;\n      };\n\n    struct Retx_Tsync_cfg {\n        unsigned int    fw_alpha        :16;    //  number of consecutive HEC error cell causes that the cell delineation state machine transit from SYNC to HUNT (0 means never)\n        unsigned int    sync_inp        :16;    //  reserved\n    };\n\n    struct Retx_Td_cfg {\n        unsigned int    res0            :8;\n        unsigned int    td_max          :8;    //  maximum delay between the time a DTU is first created at transmitter and the time the DTU is sent out of ReTX layer at receiver\n        unsigned int    res1            :8;\n        unsigned int    td_min          :8;     //  minimum delay between the time a DTU is first created at transmitter and the time the DTU is sent out of ReTX layer at receiver\n    };\n\n    struct Retx_MIB_Timer_cfg {\n        unsigned int    ticks_per_sec   : 16;\n        unsigned int    tick_cycle      : 16;\n    };\n\n    struct DTU_stat_info {\n        unsigned int complete           : 1;\n        unsigned int bad                : 1;\n        unsigned int res0_0             : 14;\n        unsigned int time_stamp         : 8;\n        unsigned int cell_cnt           : 8;\n\n        unsigned int dtu_rd_ptr         : 16;\n        unsigned int dtu_wr_ptr         : 16;\n    };\n\n    struct Retx_ctrl_field {\n        unsigned int res0               : 1;\n\n        unsigned int l2_drop            : 1;\n        unsigned int res1               : 13;\n        unsigned int retx               : 1;\n\n        unsigned int dtu_sid            : 8;\n        unsigned int cell_sid           : 8;\n    };\n\n  #else\n    #error Little Endian is not supported yet.\n  #endif\n\n  struct dsl_param {\n    unsigned int    update_flag;            //  00\n    unsigned int    res0;                   //  04\n    unsigned int    MinDelayrt;             //  08\n    unsigned int    MaxDelayrt;             //  0C\n    unsigned int    res1;                   //  10\n    unsigned int    res2;                   //  14\n    unsigned int    RetxEnable;             //  18\n    unsigned int    ServiceSpecificReTx;    //  1C\n    unsigned int    res3;                   //  20\n    unsigned int    ReTxPVC;                //  24\n    unsigned int    res4;                   //  28\n    unsigned int    res5;                   //  2C\n    unsigned int    res6;                   //  30\n    unsigned int    res7;                   //  34\n    unsigned int    res8;                   //  38\n    unsigned int    res9;                   //  3C\n    unsigned int    res10;                  //  40\n    unsigned int    res11;                  //  44\n    unsigned int    res12;                  //  48\n    unsigned int    res13;                  //  4C\n    unsigned int    RxDtuCorruptedCNT;      //  50\n    unsigned int    RxRetxDtuUnCorrectedCNT;//  54\n    unsigned int    RxLastEFB;              //  58\n    unsigned int    RxDtuCorrectedCNT;      //  5C\n  };\n#endif\n\n\n\n#endif  //  IFXMIPS_ATM_FW_REGS_COMMON_H\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-atm/src/ifxmips_atm_fw_regs_danube.h",
    "content": "/******************************************************************************\n**\n** FILE NAME    : ifxmips_atm_fw_regs_danube.h\n** PROJECT      : UEIP\n** MODULES     \t: ATM (ADSL)\n**\n** DATE         : 1 AUG 2005\n** AUTHOR       : Xu Liang\n** DESCRIPTION  : ATM Driver (Firmware Registers)\n** COPYRIGHT    : \tCopyright (c) 2006\n**\t\t\tInfineon Technologies AG\n**\t\t\tAm Campeon 1-12, 85579 Neubiberg, Germany\n**\n**    This program is free software; you can redistribute it and/or modify\n**    it under the terms of the GNU General Public License as published by\n**    the Free Software Foundation; either version 2 of the License, or\n**    (at your option) any later version.\n**\n** HISTORY\n** $Date        $Author         $Comment\n**  4 AUG 2005  Xu Liang        Initiate Version\n** 23 OCT 2006  Xu Liang        Add GPL header.\n**  9 JAN 2007  Xu Liang        First version got from Anand (IC designer)\n*******************************************************************************/\n\n\n\n#ifndef IFXMIPS_ATM_FW_REGS_DANUBE_H\n#define IFXMIPS_ATM_FW_REGS_DANUBE_H\n\n#define FW_VER_ID                       ((volatile struct fw_ver_id *)      SB_BUFFER(0x2001))\n#define CFG_WRX_HTUTS                   SB_BUFFER(0x2400)   /*  WAN RX HTU Table Size, must be configured before enable PPE firmware.   */\n#define CFG_WRX_QNUM                    SB_BUFFER(0x2401)   /*  WAN RX Queue Number */\n#define CFG_WRX_DCHNUM                  SB_BUFFER(0x2402)   /*  WAN RX DMA Channel Number, no more than 8, must be configured before enable PPE firmware.   */\n#define CFG_WTX_DCHNUM                  SB_BUFFER(0x2403)   /*  WAN TX DMA Channel Number, no more than 16, must be configured before enable PPE firmware.  */\n#define CFG_WRDES_DELAY                 SB_BUFFER(0x2404)   /*  WAN Descriptor Write Delay, must be configured before enable PPE firmware.  */\n#define WRX_DMACH_ON                    SB_BUFFER(0x2405)   /*  WAN RX DMA Channel Enable, must be configured before enable PPE firmware.   */\n#define WTX_DMACH_ON                    SB_BUFFER(0x2406)   /*  WAN TX DMA Channel Enable, must be configured before enable PPE firmware.   */\n#define WRX_HUNT_BITTH                  SB_BUFFER(0x2407)   /*  WAN RX HUNT Threshold, must be between 2 to 8.  */\n\n#define WRX_QUEUE_CONFIG(i)             ((struct wrx_queue_config*)         SB_BUFFER(0x2500 + (i) * 20))\n#define WRX_DMA_CHANNEL_CONFIG(i)       ((struct wrx_dma_channel_config*)   SB_BUFFER(0x2640 + (i) * 7))\n#define WTX_PORT_CONFIG(i)              ((struct wtx_port_config*)          SB_BUFFER(0x2440 + (i)))\n#define WTX_QUEUE_CONFIG(i)             ((struct wtx_queue_config*)         SB_BUFFER(0x2710 + (i) * 27))\n#define WTX_DMA_CHANNEL_CONFIG(i)       ((struct wtx_dma_channel_config*)   SB_BUFFER(0x2711 + (i) * 27))\n#define WAN_MIB_TABLE                   ((struct wan_mib_table*)            SB_BUFFER(0x2410))\n#define HTU_ENTRY(i)                  ((struct htu_entry*)                SB_BUFFER(0x2000 + (i)))\n#define HTU_MASK(i)                   ((struct htu_mask*)                 SB_BUFFER(0x2020 + (i)))\n#define HTU_RESULT(i)                 ((struct htu_result*)               SB_BUFFER(0x2040 + (i)))\n\n#endif\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-atm/src/ifxmips_atm_fw_regs_vr9.h",
    "content": "/******************************************************************************\n**\n** FILE NAME    : ifxmips_atm_fw_regs_vr9.h\n** PROJECT      : UEIP\n** MODULES     \t: ATM (ADSL)\n**\n** DATE         : 1 AUG 2005\n** AUTHOR       : Xu Liang\n** DESCRIPTION  : ATM Driver (Firmware Registers)\n** COPYRIGHT    : \tCopyright (c) 2006\n**\t\t\tInfineon Technologies AG\n**\t\t\tAm Campeon 1-12, 85579 Neubiberg, Germany\n**\n**    This program is free software; you can redistribute it and/or modify\n**    it under the terms of the GNU General Public License as published by\n**    the Free Software Foundation; either version 2 of the License, or\n**    (at your option) any later version.\n**\n** HISTORY\n** $Date        $Author         $Comment\n**  4 AUG 2005  Xu Liang        Initiate Version\n** 23 OCT 2006  Xu Liang        Add GPL header.\n**  9 JAN 2007  Xu Liang        First version got from Anand (IC designer)\n*******************************************************************************/\n\n\n\n#ifndef IFXMIPS_ATM_FW_REGS_VR9_H\n#define IFXMIPS_ATM_FW_REGS_VR9_H\n\n#define FW_VER_ID\t\t((volatile struct fw_ver_id *) SB_BUFFER(0x2001))\n\n/* WAN RX HTU Table Size, must be configured before enable PPE firmware. */\n#define CFG_WRX_HTUTS\t\t\tSB_BUFFER(0x2010)\n/* WAN RX Queue Number */\n#define CFG_WRX_QNUM\t\t\tSB_BUFFER(0x2011)\n/* WAN RX DMA Channel Number, no more than 8, must be configured before enable PPE firmware. */\n#define CFG_WRX_DCHNUM\t\t\tSB_BUFFER(0x2012)\n/* WAN TX DMA Channel Number, no more than 16, must be configured before enable PPE firmware. */\n#define CFG_WTX_DCHNUM\t\t\tSB_BUFFER(0x2013)\n/* WAN Descriptor Write Delay, must be configured before enable PPE firmware. */\n#define CFG_WRDES_DELAY\t\t\tSB_BUFFER(0x2014)\n/* WAN RX DMA Channel Enable, must be configured before enable PPE firmware. */\n#define WRX_DMACH_ON\t\t\tSB_BUFFER(0x2015)\n/* WAN TX DMA Channel Enable, must be configured before enable PPE firmware. */\n#define WTX_DMACH_ON\t\t\tSB_BUFFER(0x2016)\n/* WAN RX HUNT Threshold, must be between 2 to 8. */\n#define WRX_HUNT_BITTH\t\t\tSB_BUFFER(0x2017)\n/*  i < 16  */\n#define WRX_QUEUE_CONFIG(i)\t\t((struct wrx_queue_config *) SB_BUFFER(0x4C00 + (i) * 20))\n/*  i < 8   */\n#define WRX_DMA_CHANNEL_CONFIG(i)\t((struct wrx_dma_channel_config *) SB_BUFFER(0x4F80 + (i) * 7))\n/*  i < 2   */\n#define WTX_PORT_CONFIG(i)\t\t((struct wtx_port_config *) SB_BUFFER(0x4FB8 + (i)))\n/*  i < 16  */\n#define WTX_QUEUE_CONFIG(i)\t\t((struct wtx_queue_config *) SB_BUFFER(0x3A00 + (i) * 27))\n/*  i < 16  */\n#define WTX_DMA_CHANNEL_CONFIG(i)\t((struct wtx_dma_channel_config *) SB_BUFFER(0x3A01 + (i) * 27))\n\n#define WAN_MIB_TABLE\t\t\t((struct wan_mib_table *) SB_BUFFER(0x4EF0))\n/*  i < 32  */\n#define HTU_ENTRY(i)\t\t\t((struct htu_entry *) SB_BUFFER(0x26A0 + (i)))\n/*  i < 32  */\n#define HTU_MASK(i)\t\t\t((struct htu_mask *) SB_BUFFER(0x26C0 + (i)))\n/*  i < 32  */\n#define HTU_RESULT(i)\t\t\t((struct htu_result *) SB_BUFFER(0x26E0 + (i)))\n/* bit 0~3 - 0x0F: in showtime, 0x00: not in showtime */\n#define UTP_CFG\t\t\t\tSB_BUFFER(0x2018)\n\n\n\n#endif  //  IFXMIPS_ATM_FW_REGS_VR9_H\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-atm/src/ifxmips_atm_fw_vr9.h",
    "content": "#ifndef IFXMIPS_ATM_FW_VR9_H\n#define IFXMIPS_ATM_FW_VR9_H\n\n\n/******************************************************************************\n**\n** FILE NAME    : ifxmips_atm_fw_vr9.h\n** PROJECT      : UEIP\n** MODULES     \t: ATM (ADSL)\n**\n** DATE         : 22 OCT 2007\n** AUTHOR       : Xu Liang\n** DESCRIPTION  : ATM Driver (PP32 Firmware)\n** COPYRIGHT    : \tCopyright (c) 2006\n**\t\t\tInfineon Technologies AG\n**\t\t\tAm Campeon 1-12, 85579 Neubiberg, Germany\n**\n**    This program is free software; you can redistribute it and/or modify\n**    it under the terms of the GNU General Public License as published by\n**    the Free Software Foundation; either version 2 of the License, or\n**    (at your option) any later version.\n**\n** HISTORY\n** $Date        $Author         $Comment\n** 22 OCT 2007  Xu Liang        Initial Version, v00.01\n*******************************************************************************/\n\n\n#define VER_IN_FIRMWARE         1\n\n#define ATM_FW_VER_MAJOR        0\n#define ATM_FW_VER_MINOR        24\n\n\nstatic u32 vr9_fw_bin[] = {\n    0x800004B8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x8000FFE0, 0x00000000, 0x00000000, 0x00000000,\n    0xC1000002, 0xD90C00F8, 0xC2000002, 0xDA0800F9, 0x80004390, 0xC2000000, 0xDA0800F9, 0x80003A10,\n    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0x800039C8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0x80004B60, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0x800038C8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0xC0400000, 0xC000ABC0, 0xC88400F8, 0x80004050, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0xC0400002, 0xC000ABC0, 0xC88400F8, 0x80003FD0, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0xC3C00004, 0xDBC800F9, 0xC10C0002, 0xD90C00F8, 0x8000FEE0, 0x00000000, 0x00000000, 0x00000000,\n    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0xC10E0002, 0xD90C00F8, 0xC0004028, 0xC84000F8, 0x80004000, 0x00000000, 0x00000000, 0x00000000,\n    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0xC3E1FFFE, 0x597DFFFE, 0x593DFE14, 0x900004D9, 0x00000000, 0x00000000, 0x00000000, 0x90CC0481,\n    0x00000000, 0x00000000, 0x00000000, 0xC3C00000, 0xDBC800F9, 0xC1400008, 0xC1900000, 0x71588000,\n    0x14100100, 0xC140000A, 0xC1900002, 0x71588000, 0x14100100, 0xC140000C, 0xC1900004, 0x71588000,\n    0x14100100, 0xC1400004, 0xC1900006, 0x71588000, 0x14100100, 0xC1400006, 0xC1900008, 0x71588000,\n    0x14100100, 0xC140000E, 0xC190000A, 0x71588000, 0x14100100, 0xC1400000, 0xC190000C, 0x71588000,\n    0x14100100, 0xC1400002, 0xC190000E, 0x71588000, 0x14100100, 0xC0400000, 0xC11C0000, 0xC000E82C,\n    0xCD05CE00, 0xC11C0002, 0xC000E82C, 0xCD05CE00, 0xC0400002, 0xC11C0000, 0xC000E82C, 0xCD05CE00,\n    0xC11C0002, 0xC000E82C, 0xCD05CE00, 0xC000E824, 0x00000000, 0xCBC000F9, 0xCB8000F9, 0xCB4000F9,\n    0xCB0000F8, 0xC000ABE4, 0x5BFC4000, 0xCFC000F9, 0x5BB84000, 0xCF8000F9, 0x5B744000, 0xCF4000F9,\n    0x5B304000, 0xCF0000F8, 0xC000EA10, 0x00000000, 0xCBC000F9, 0xCB8000F8, 0xC000ABE0, 0x5BFC4000,\n    0xCFC000F9, 0x5BB84000, 0xCF8000F8, 0xC30001FE, 0xC000F416, 0xCF0000F8, 0xC3000000, 0x7F018000,\n    0xC000E42E, 0xCF0000F8, 0xC000E40E, 0xCF0000F8, 0xC3C1FFFE, 0xC000690E, 0xCFC00078, 0xC000692C,\n    0xCFC00078, 0xC0006924, 0xCFC00038, 0xC0006912, 0xCFC00038, 0xC0006966, 0xCFC00038, 0xC0006968,\n    0xCFC00078, 0xC000696A, 0xCFC00078, 0xC3C00000, 0xC2800020, 0xC3000000, 0x7F018000, 0x6FF88000,\n    0x6FD44000, 0x4395C000, 0x5BB89800, 0x5838000A, 0xCF0000F8, 0x5BFC0002, 0xB7E8FFC8, 0x00000000,\n    0xC3C00000, 0xC2800010, 0x6FF86000, 0x47BDC000, 0x5BB89F00, 0xC3400000, 0x58380004, 0xCB420078,\n    0x00000000, 0x58380008, 0xCF400078, 0x5BFC0002, 0xB7E8FFB0, 0x00000000, 0xC3C00000, 0xC2800020,\n    0xC348001E, 0xC3000000, 0x7F018000, 0x6FF8A000, 0x6FD44000, 0x4795C000, 0x47BDC000, 0x5BB87400,\n    0x58380008, 0xCF408418, 0x5838000A, 0xCF0000F8, 0x5BFC0002, 0xB7E8FFB0, 0x00000000, 0x00000000,\n    0xC3E0E282, 0x5BFC0030, 0xC0004002, 0xCFC000F8, 0xC000E82C, 0xC11E0002, 0xCD01EF00, 0xC000E82E,\n    0xCD01EF00, 0x00000000, 0xC121FFFE, 0x5911FE94, 0x14100000, 0x80000028, 0x00000000, 0x80001CB8,\n    0x00000000, 0x8000FFE0, 0xC0006918, 0xD28000F8, 0xC2000000, 0xDF600038, 0x5E600020, 0x84000272,\n    0x00000000, 0xC161FFFE, 0x5955FFFE, 0x14140000, 0x00000000, 0xC000402A, 0xCA0000F8, 0xC0006912,\n    0xCA4000F8, 0xC0006924, 0xCA8000F8, 0xC0006966, 0xCAC000F8, 0x00000000, 0xC121FFFE, 0x5911FE94,\n    0x14100000, 0x76250000, 0x76290000, 0x762D0000, 0x840001CA, 0xC0006918, 0xCA4000F8, 0xC28001FE,\n    0x76290000, 0x5A640002, 0x6A254010, 0x5EE80000, 0x8400001A, 0x6AA54000, 0x80000010, 0xC62800F8,\n    0x62818008, 0xC0006918, 0xCF0000F8, 0xC161FFFE, 0x5955FFFE, 0x14140000, 0x00000000, 0xC0006966,\n    0xCA4000F8, 0xC2000002, 0x6A310000, 0x7E010000, 0x76612000, 0xCE4000F8, 0x00000000, 0xC121FFFE,\n    0x5911FE94, 0x14100000, 0x6F346000, 0x4771A000, 0x5B749F00, 0xC2800000, 0x58340006, 0xCA800078,\n    0xC2C00000, 0x58340000, 0xCAC000D8, 0xC2400000, 0x5834000A, 0xCA420078, 0x6EA82000, 0x42E9E000,\n    0x6F2CA000, 0x42E56000, 0x5AEC3200, 0xC3990040, 0xC7381C18, 0xC6F80060, 0x99005560, 0xDB9800F8,\n    0xDBD800F9, 0x00000000, 0xDEA000F8, 0x46310000, 0x8400FD80, 0xC0006958, 0xC84000F8, 0x00000000,\n    0xC3C00002, 0x787C2000, 0xCC4000F8, 0xC000ABC8, 0xCB8400F8, 0xC000ABC4, 0xC88400F8, 0x5FB80000,\n    0x8400FCFA, 0xC000FAC0, 0xCA0400F8, 0x00000000, 0x00000000, 0xA6040070, 0xC000ABE4, 0xC80400F8,\n    0x6C908000, 0x45088000, 0x45088000, 0x40100000, 0xCA0000F8, 0xC42400F8, 0x00000000, 0x98C05CD8,\n    0xC000697C, 0xCA0000F8, 0x59640004, 0xC0004030, 0xCA0000F8, 0xC2400002, 0x6A452000, 0x76250000,\n    0x8400FC3A, 0xC000ABE8, 0xC80400F8, 0x00000000, 0x00000000, 0x40080000, 0xCA0000F8, 0xC42400F8,\n    0x00000000, 0xA63C17DA, 0x00000000, 0xC000ABE4, 0xC80400F8, 0x6C908000, 0x45088000, 0x45088000,\n    0x40100000, 0xCA0000F8, 0xC42400F8, 0x00000000, 0xC0006934, 0xCE0000F8, 0xC2800002, 0xC4681C08,\n    0xC62821D0, 0xC2600010, 0x5A650D80, 0xC0004020, 0xCB4000F8, 0xC2200400, 0x5A200D40, 0xC7601040,\n    0xC000F220, 0xCE8000F8, 0xC000F200, 0xCE4000F8, 0xC000F202, 0xCE0000F8, 0xC000F240, 0xCB4000F8,\n    0x00000000, 0x00000000, 0xA754FFE0, 0xC2000000, 0xC7600040, 0xA7520042, 0x00000000, 0x00000000,\n    0x99005FD8, 0xC0009DE2, 0xC94000F8, 0xC1800002, 0x80001680, 0x58204DC0, 0xC2000000, 0xCA000018,\n    0xC2400000, 0xCA414000, 0xC2800000, 0xCA812000, 0xC2C00000, 0xCAC20018, 0xC0006938, 0xCE0000F8,\n    0xC0006920, 0xCE4000F8, 0xC0006916, 0xCE8000F8, 0xC0006922, 0xCEC000F8, 0xA6400540, 0x00000000,\n    0xC0006938, 0xCBC000F8, 0x00000000, 0xC3800000, 0x6FF48000, 0x6FD44000, 0x4355A000, 0x5B749800,\n    0x58340000, 0xCB802010, 0x00000000, 0xC2000000, 0x6FB46000, 0x4779A000, 0x5B749F00, 0x5834000C,\n    0xCA000020, 0xC000691A, 0xCF8000F8, 0x5E200000, 0x8400046A, 0xC2000000, 0xDF610048, 0x5E6001E8,\n    0x8800FFE8, 0xC2000002, 0xC2400466, 0xC2A00000, 0x5AA80000, 0xC000F006, 0xCE0000F8, 0xC000F008,\n    0xCE4000F8, 0xC000F00A, 0xCE8000F8, 0x99004FA0, 0xC1A0FFFE, 0xC000E824, 0xC9840070, 0xC0006934,\n    0xCA4000F8, 0xC2000000, 0xC2800002, 0x99004FE0, 0xDA9800F8, 0xC61400F8, 0xC65800F8, 0xC161FFFE,\n    0x5955FFFE, 0x14140000, 0x00000000, 0x990050C8, 0xC000691A, 0xC94000F8, 0x00000000, 0x00000000,\n    0xC121FFFE, 0x5911FE94, 0x14100000, 0xC0006922, 0xCA001118, 0xC3C00000, 0xC3800000, 0xC0006930,\n    0xCE023118, 0xC0006932, 0xCBC000D8, 0xC2800000, 0xC000691E, 0xCFC000F8, 0xC000ABDE, 0xCA800060,\n    0xC3A0001A, 0x5BB94000, 0xC6B80060, 0xC000691C, 0xCF8000F8, 0x99005338, 0xC000691C, 0xC1400000,\n    0xC9420048, 0x00000000, 0x00000000, 0x00000000, 0xA8E2FFE8, 0xC2000000, 0xC1220002, 0xD90C00F8,\n    0xDF600038, 0x5E600020, 0x8400FFF2, 0xC000691C, 0xCA0000F8, 0xC000691E, 0xCA4000F8, 0x00000000,\n    0x00000000, 0x99005560, 0xDA1800F8, 0xDA5800F9, 0x00000000, 0xC2000000, 0xDF610048, 0x5E6001FE,\n    0x8800FFE8, 0xC0006916, 0xCA8000F8, 0xC2C00000, 0xDFEC0048, 0xC2400000, 0x466D2000, 0x8400004A,\n    0x5EA80000, 0x8400003A, 0xC2600002, 0x99005FD8, 0xC0009DEE, 0xC94000F8, 0xC1800002, 0x80000030,\n    0xC2600000, 0x99005FD8, 0xC0009DEC, 0xC94000F8, 0xC1800002, 0xC2000068, 0xC6240078, 0xC0006930,\n    0xCE400080, 0xC000691A, 0xC98000F8, 0xC000ABDE, 0xC94000F8, 0x6D9C6000, 0x45D8E000, 0x59DC9F00,\n    0x990053C0, 0xD95800F8, 0xD99800F9, 0xD9D400F8, 0x99005338, 0xC000691C, 0xC1400000, 0xC9420048,\n    0xC2000000, 0xDF600038, 0x5E600020, 0x8400FFEA, 0x00000000, 0xC000691C, 0xCA0000F8, 0xC000691E,\n    0xCA4000F8, 0x00000000, 0x00000000, 0x99005560, 0xDA1800F8, 0xDA5800F9, 0x00000000, 0x800010E8,\n    0x00000000, 0x99005FD8, 0xC0009DEA, 0xC94000F8, 0xC1800002, 0x800010B8, 0xC0006938, 0xCBC000F8,\n    0x00000000, 0x00000000, 0x6FF88000, 0x6FD44000, 0x4395C000, 0x5BB89800, 0x58380008, 0xCA0000F8,\n    0x00000000, 0x00000000, 0xA6000382, 0x00000000, 0xC0006938, 0xCBC000F8, 0xC3000000, 0x00000000,\n    0x6FF88000, 0x6FD44000, 0x4395C000, 0x5BB89800, 0x58380000, 0xCB002010, 0xC2000000, 0x58380008,\n    0xCA020078, 0x5838000C, 0xCAC000F8, 0x5838000E, 0xCA4000F8, 0xC000691A, 0xCF0000F8, 0xC0006930,\n    0xCEC000F8, 0xC000693C, 0xCE0000F8, 0xC0006932, 0xCE4000F8, 0x5E200000, 0x84000120, 0xC2800000,\n    0xA6FE00BA, 0x6F206000, 0x46310000, 0x5A209F00, 0x5820000C, 0xCA800020, 0x00000000, 0x00000000,\n    0x5EA80000, 0x840001F2, 0x00000000, 0xC161FFFE, 0x5955FFFE, 0x14140000, 0x00000000, 0x990050C8,\n    0xC000691A, 0xC94000F8, 0x00000000, 0x00000000, 0xC121FFFE, 0x5911FE94, 0x14100000, 0xC0006930,\n    0xCAC000F8, 0xC0006932, 0xCA4000F8, 0xC7EC1118, 0xC0006930, 0xCEC000F8, 0x5838000C, 0xCEC000F8,\n    0x58000002, 0xCE4000F8, 0xC0006934, 0xCA0000F8, 0xC2400002, 0x6E642000, 0x6E642000, 0x76612000,\n    0x8400002A, 0xC2400002, 0x6E684000, 0x58380008, 0xCE804200, 0xA6000020, 0x6E682000, 0x58380008,\n    0xCE802100, 0xC2400002, 0x6E642000, 0x76612000, 0x840000EA, 0x58380008, 0xCA0000F8, 0xC2800000,\n    0xC2400000, 0xA60200C0, 0xDBA800F8, 0x6F386000, 0x47B1C000, 0x5BB89F00, 0x58380004, 0xCA400078,\n    0x58380002, 0xCA800078, 0x00000000, 0xDEB800F8, 0x46A54000, 0x88000060, 0x00000000, 0xC0009DE4,\n    0xCA0000F8, 0xC2400002, 0x6E640000, 0x5A200002, 0xCE0000F8, 0x58380008, 0xCE400000, 0x80000018,\n    0x00000000, 0x80000048, 0xC0006934, 0xCA0000F8, 0x00000000, 0x00000000, 0xA6020C6A, 0x00000000,\n    0x00000000, 0x80000C98, 0xC2800000, 0xC2000080, 0xC240001A, 0xDF690048, 0x46294000, 0x46A54000,\n    0x8800FFD2, 0xC2000006, 0xC2600982, 0x5A643B6E, 0x5838000A, 0xCA8000F8, 0xC000F006, 0xCE0000F8,\n    0xC000F008, 0xCE4000F8, 0xC000F00A, 0xCE8000F8, 0x99004FA0, 0xC1A0FFFE, 0xC000E824, 0xC9840070,\n    0xC2000000, 0xC0006930, 0xCA02E008, 0x58380026, 0xCA4000F8, 0x00000000, 0xC2800000, 0x99004FE0,\n    0xDA9800F8, 0xC61400F8, 0xC65800F8, 0xC0006934, 0xCA0000F8, 0x00000000, 0x00000000, 0xA6020022,\n    0x00000000, 0x00000000, 0x80000318, 0xC0006938, 0xCBC000F8, 0xC000ABE4, 0xC80400F8, 0x6C908000,\n    0x45088000, 0x45088000, 0x40100000, 0xCA0000F8, 0xC42400F8, 0x00000000, 0x58240018, 0xCA0000F8,\n    0x6FF88000, 0x6FD44000, 0x4395C000, 0x5BB89800, 0xC3000000, 0xC3400002, 0xC2C00000, 0xC62C0078,\n    0xC6270038, 0xC0006940, 0xCE400038, 0xC6260038, 0xC0006942, 0xCE400038, 0xC000693C, 0xCA0000F8,\n    0x5EEC0000, 0x8400018A, 0x5A6C0010, 0x46254000, 0x88000190, 0x5A600052, 0x46E54000, 0x88000178,\n    0x58380006, 0xCA8000F8, 0xC0006940, 0xCA0000F8, 0xC2400000, 0xC6A70038, 0x7E412000, 0x76612000,\n    0xC2000000, 0xC6A10038, 0x46250000, 0x84000138, 0xC0006942, 0xCA0000F8, 0xC2400000, 0xC6A60038,\n    0x7E412000, 0x76612000, 0xC2000000, 0xC6A00038, 0x58380002, 0xCA8000F8, 0x46250000, 0x840000E8,\n    0xC2400000, 0xC6A60078, 0x466D0000, 0x880000DA, 0xC2400000, 0xC6A40078, 0x58380008, 0xCA8000F8,\n    0x46E50000, 0x880000BA, 0x00000000, 0xA6820018, 0x00000000, 0xC7700B00, 0xA6840098, 0x00000000,\n    0xC7700A00, 0x80000080, 0xC7700200, 0xC000693C, 0xCAC000F8, 0x80000060, 0xC7700300, 0xC000693C,\n    0xCAC000F8, 0x80000040, 0xC7700900, 0x80000030, 0xC7700800, 0x80000020, 0xC7700700, 0x80000010,\n    0xC7700500, 0xC0006944, 0xCF0000F8, 0xC000693E, 0xCEC000F8, 0xC0006938, 0xCA4000F8, 0xC000693C,\n    0xCB8000F8, 0xC000693E, 0xCB4000F8, 0xC3000000, 0x6E608000, 0x6E544000, 0x42150000, 0x5A209800,\n    0x5AA00008, 0x58200004, 0xCB000078, 0xC0006934, 0xCA0000F8, 0xC2400000, 0xC0006930, 0xCA42E008,\n    0xC3C00018, 0xA6020098, 0x00000000, 0x43656000, 0x47AD0000, 0x88000050, 0x46F96000, 0x6EE04010,\n    0x5BE00004, 0xC2000000, 0xC6E00008, 0x5E200000, 0x84000042, 0x5BFC0002, 0x80000030, 0xC3C00004,\n    0x5A2C0008, 0x47A10000, 0x88000012, 0x5FB80008, 0x6FE04000, 0x42390000, 0x47212000, 0x88000068,\n    0xC2400000, 0xC0006930, 0xCA42E008, 0xC2060002, 0xC68000F8, 0xCE006300, 0x6FE04000, 0x4721C000,\n    0x5F700010, 0x4765A000, 0xC2000000, 0xC6340008, 0xC25A000A, 0xC000691A, 0xCA401C18, 0xC2800000,\n    0xC0006932, 0xCA8000D8, 0xC000ABDE, 0xCA400060, 0x6FA04010, 0x42290000, 0xC000691E, 0xCE0000F8,\n    0xC7E41048, 0xC000691C, 0xCE4000F8, 0x6FE04000, 0x43A1C000, 0xC000693C, 0xCF8000F8, 0xC000693E,\n    0xCF4000F8, 0xC000693A, 0xCFC000F8, 0x80000008, 0x00000000, 0x00000000, 0x00000000, 0xC2000000,\n    0xDCE000F8, 0xA622FFD8, 0xC1220002, 0xD90C00F8, 0xC0006938, 0xCBC000F8, 0xC0006944, 0xCB4000F8,\n    0xC000ABDE, 0xCB0000F8, 0xC0006934, 0xCA0000F8, 0x6FF88000, 0x6FD44000, 0x4395C000, 0x5BB89800,\n    0xA6020268, 0xC2400000, 0x58380008, 0xCA406000, 0xDFE800F8, 0xC2218E08, 0x5A21BAF6, 0x46A14000,\n    0x84000022, 0xC2080002, 0x7361A000, 0x80000058, 0x5E640000, 0x84000022, 0xC20C0002, 0x7361A000,\n    0x80000030, 0xC2000000, 0xC760E710, 0xC7604218, 0x5E200000, 0x84000272, 0xC2200002, 0xC0006930,\n    0xCE021000, 0x99005FD8, 0xC0009DE8, 0xC94000F8, 0xC1800002, 0x58380000, 0xCA0000F8, 0x00000000,\n    0x00000000, 0xA6000132, 0xC0006940, 0xCA8000F8, 0xC0006942, 0xCA4000F8, 0xC7600078, 0xC6A01838,\n    0xC6601038, 0xC000693A, 0xCA4000F8, 0xC0006934, 0xCA8000F8, 0xC000AB40, 0x40300000, 0x40240000,\n    0x5C000004, 0x5EC0ABC0, 0x88000012, 0x5C000080, 0xCE0000F8, 0x58000002, 0x5EC0ABC0, 0x88000012,\n    0x5C000080, 0xCE8000F8, 0xC000693E, 0xCA0000F8, 0xC2400000, 0x5838000C, 0xCE4000F8, 0x99005FD8,\n    0xC0009DF0, 0xC94000F8, 0xC61800F8, 0xC0006930, 0xC6100078, 0xCD000078, 0x800000A8, 0xC2400002,\n    0x58380008, 0xCE400000, 0xC0006944, 0xCF4000F8, 0x80000278, 0xC000693C, 0xCA4000F8, 0xDFE800F8,\n    0x5A300018, 0xC000AB40, 0x40200000, 0xCA0000F8, 0x58380008, 0xC6501078, 0xCD021078, 0x5838000A,\n    0xCE8000F8, 0x58380026, 0xCE0000F8, 0xC0006944, 0xCF4000F8, 0x99005338, 0xC000691C, 0xC1400000,\n    0xC9420048, 0x80000038, 0x00000000, 0x99005FD8, 0xC0009DE6, 0xC94000F8, 0xC1800002, 0x8000FDD8,\n    0xC2000000, 0xC2400020, 0xDF600038, 0xB624FFEA, 0xC000691C, 0xCA4000F8, 0xC000691E, 0xCA8000F8,\n    0x99005560, 0xDA5800F8, 0xDA9800F9, 0x00000000, 0xC0006934, 0xCA0000F8, 0x00000000, 0xC2800000,\n    0xA6020160, 0xC2400004, 0xC2000080, 0xDF690048, 0x46294000, 0x46A54000, 0x8800FFDA, 0x00000000,\n    0xC000691A, 0xC98000F8, 0xC000ABDE, 0xC94000F8, 0x6D9C6000, 0x45D8E000, 0x59DC9F00, 0x990053C0,\n    0xD95800F8, 0xD99800F9, 0xD9D400F8, 0x99005338, 0xC000691C, 0xC1400000, 0xC9420048, 0xC2000000,\n    0xC2400020, 0xDF600038, 0xB624FFEA, 0xC000691C, 0xCA4000F8, 0xC000691E, 0xCA8000F8, 0x99005560,\n    0xDA5800F8, 0xDA9800F9, 0x00000000, 0x58380008, 0xCA4000F8, 0xC2000000, 0xCE000018, 0xC2A1FFFE,\n    0x5AA9FFFE, 0xCE021078, 0x5838000A, 0xCE8000F8, 0xC161FFFE, 0x5955FFFE, 0x14140000, 0x00000000,\n    0xC000E838, 0xC2500002, 0xCE450800, 0xC000ABC8, 0xCB8400F8, 0xC2000000, 0xC000E82C, 0xCA040038,\n    0x5FB80002, 0xC000ABC8, 0xCF8400F8, 0x58880002, 0xB6080018, 0x00000000, 0xC0800000, 0xC000ABC4,\n    0xCC8400F8, 0x00000000, 0xC121FFFE, 0x5911FE94, 0x14100000, 0x8000E350, 0xC2000000, 0xDF600038,\n    0x5E200020, 0x8400026A, 0x00000000, 0xC161FFFE, 0x5955FFFE, 0x14140000, 0x00000000, 0xC000402C,\n    0xCA0000F8, 0xC0006910, 0xCA4000F8, 0xC000692C, 0xCA8000F8, 0xC0006968, 0xCAC000F8, 0x00000000,\n    0xC121FFFE, 0x5911FE94, 0x14100000, 0x76250000, 0x76290000, 0x76E16000, 0x840001C2, 0xC0006926,\n    0xCA4000F8, 0xC201FFFE, 0x76E16000, 0x5A640002, 0x6AE50010, 0x5F200000, 0x8400001A, 0x6A250000,\n    0x80000010, 0xC6E000F8, 0x62014008, 0xC0006926, 0xCE8000F8, 0xC161FFFE, 0x5955FFFE, 0x14140000,\n    0x00000000, 0xC0006968, 0xCA4000F8, 0xC2000002, 0x6A290000, 0x7E010000, 0x76612000, 0xCE4000F8,\n    0x00000000, 0xC121FFFE, 0x5911FE94, 0x14100000, 0x6EB4A000, 0x6E944000, 0x4755A000, 0x4769A000,\n    0x5B747400, 0x58340002, 0xC2000000, 0xCA0000D8, 0x5834002E, 0xC2400000, 0xCA400078, 0x6EB0A000,\n    0x6EBC4000, 0x473D8000, 0x47298000, 0x5B30342E, 0x5B300004, 0x6E642000, 0x4225E000, 0xC39A8024,\n    0xC7380060, 0xC6B81C18, 0x99005560, 0xDB9800F8, 0xDBD800F9, 0x00000000, 0xC2000000, 0xDF600038,\n    0x5E200020, 0x840002A2, 0x00000000, 0xC161FFFE, 0x5955FFFE, 0x14140000, 0x00000000, 0xC000690E,\n    0xCA0000F8, 0xC000692A, 0xCA4000F8, 0xC000696A, 0xCB0000F8, 0xC0006956, 0xCAC000F8, 0x00000000,\n    0xC121FFFE, 0x5911FE94, 0x14100000, 0x77218000, 0x77258000, 0x84000202, 0xC201FFFE, 0x77218000,\n    0x5AEC0002, 0x6B2D0010, 0x5EA00000, 0x8400001A, 0x6A2D0000, 0x80000010, 0xC72000F8, 0x62016008,\n    0xC0006956, 0xCEC000F8, 0xC161FFFE, 0x5955FFFE, 0x14140000, 0x00000000, 0xC000696A, 0xCA4000F8,\n    0xC2000002, 0x6A2D0000, 0x7E010000, 0x76612000, 0xCE4000F8, 0x00000000, 0xC121FFFE, 0x5911FE94,\n    0x14100000, 0x6EF4A000, 0x6ED44000, 0x4755A000, 0x476DA000, 0x5B747400, 0x5834000E, 0xC2000000,\n    0xCA0000D8, 0x58340008, 0xC2400000, 0xCA420078, 0x5834000C, 0xC2800000, 0xCA832010, 0x6E644010,\n    0x42250000, 0x4229E000, 0xC39A8008, 0x58340008, 0xCB809018, 0x58340008, 0xC2800000, 0xCA810010,\n    0x6EE0A000, 0x6EE44000, 0x46250000, 0x462D0000, 0x5A200008, 0x5A203408, 0x42290000, 0xC6380060,\n    0xC6F81C18, 0x99005560, 0xDB9800F8, 0xDBD800F9, 0x00000000, 0xC000695A, 0xC84000F8, 0x00000000,\n    0xC3C00002, 0x787C2000, 0xCC4000F8, 0xC0004030, 0xCA0000F8, 0xC2400008, 0x6A452000, 0x76250000,\n    0x84000E02, 0xC000EA28, 0xC3800000, 0xCB840038, 0xC000EA14, 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0x5955FFFE, 0x14140000, 0x00000000, 0x99005228,\n    0xDBD800F8, 0xDB9800F9, 0xC7D800F8, 0x00000000, 0xC121FFFE, 0x5911FE94, 0x14100000, 0x6FF8A000,\n    0x6FD44000, 0x4795C000, 0x47BDC000, 0x5BB87400, 0x58380010, 0xCA0000F8, 0xC000ABE0, 0xC80400F8,\n    0x6C908000, 0x45088000, 0x45088000, 0x40100000, 0xCA4000F8, 0xC43400F8, 0x00000000, 0xC74000F8,\n    0xCE0000F8, 0xC161FFFE, 0x5955FFFE, 0x14140000, 0x00000000, 0xC000690E, 0xCA4000F8, 0xC2800002,\n    0x6ABD4000, 0x72692000, 0xCE4000F8, 0x00000000, 0xC121FFFE, 0x5911FE94, 0x14100000, 0x99005FD8,\n    0xC0009DF6, 0xC94000F8, 0xC1800002, 0x00000000, 0x00000000, 0x00000000, 0xA8E2FFE8, 0x00000000,\n    0xC1220002, 0xD90C00F8, 0xC2000000, 0xC000EA14, 0xCA040038, 0xC000EA28, 0xC2500002, 0xCE450800,\n    0x58880002, 0xB6080018, 0xC0009F74, 0xC0800000, 0xCC8400F8, 0x8000D900, 0xC0006946, 0xCBC000F8,\n    0xC161FFFE, 0x5955FFFE, 0x14140000, 0x00000000, 0xC000690E, 0xCA4000F8, 0xC2800002, 0x6ABD4000,\n    0x72692000, 0xCE4000F8, 0x00000000, 0xC121FFFE, 0x5911FE94, 0x14100000, 0x6FF8A000, 0x6FD44000,\n    0x4795C000, 0x47BDC000, 0x5BB87400, 0x58380008, 0xCA0000F8, 0x5838000C, 0xCA4000F8, 0xC3400000,\n    0xC6340000, 0xC000694E, 0xCF4000F8, 0xC2800000, 0xC62A0078, 0xC3000000, 0xC6308018, 0x6F304000,\n    0x43298000, 0xC000693C, 0xCF0000F8, 0xC2C00000, 0xC66C0078, 0xC0006950, 0xCEC000F8, 0xC2800000,\n    0xC66AE020, 0xC0006954, 0xCE8000F8, 0x5F740000, 0x840001A0, 0x5E300028, 0x46E12000, 0x8400016A,\n    0x46E12000, 0x88000132, 0x5E300018, 0x46E12000, 0x8800002A, 0x46E12000, 0x84000042, 0x00000000,\n    0x800000C0, 0x00000000, 0x99005970, 0xDBD800F8, 0xDB9800F9, 0xC78000F8, 0xC3400002, 0xC000694E,\n    0xCF4000F8, 0xC161FFFE, 0x5955FFFE, 0x14140000, 0x00000000, 0xC000690E, 0xCA4000F8, 0xC2800002,\n    0x6ABD4000, 0x7E814000, 0x76692000, 0xCE4000F8, 0x00000000, 0xC121FFFE, 0x5911FE94, 0x14100000,\n    0xC2200060, 0xC0006948, 0xCE021038, 0xC2000000, 0xC000694C, 0xCE0000F8, 0x80000080, 0x00000000,\n    0x99005970, 0xDBD800F8, 0xDB9800F9, 0xC78000F8, 0x99005B70, 0xDBD800F8, 0xDB9800F9, 0xC78000F8,\n    0xC2200058, 0xC0006948, 0xCE021038, 0xC2000002, 0xC000694C, 0xCE0000F8, 0xC2000006, 0xC000F006,\n    0xCE0000F8, 0x5838000A, 0xCA4000F8, 0xC2200982, 0x5A203B6E, 0xC000F008, 0xCE0000F8, 0xC000F00A,\n    0xCE4000F8, 0xC0006954, 0xCA8000F8, 0xC200000C, 0xC000694A, 0xCE0000F8, 0xC0006948, 0xCE800008,\n    0xC2B60000, 0xC0006964, 0xCE8000F8, 0x99005830, 0xC0009F74, 0xC88400F8, 0x00000000, 0xC0006946,\n    0xCBC000F8, 0xC000694C, 0xCA0000F8, 0x6FF8A000, 0x6FD44000, 0x4795C000, 0x47BDC000, 0x5BB87400,\n    0x5E200000, 0x840000FA, 0x00000000, 0x990055F0, 0xDBD800F8, 0xDB9800F9, 0x00000000, 0x99005338,\n    0xC000691C, 0xC1400000, 0xC9420048, 0xC000691C, 0x990057E8, 0xC94000F9, 0xC98000F8, 0x00000000,\n    0x99005560, 0xD95800F8, 0xD99800F9, 0x00000000, 0xC161FFFE, 0x5955FFFE, 0x14140000, 0x00000000,\n    0x99005228, 0xDBD800F8, 0xDB9800F9, 0xC7D800F8, 0x00000000, 0xC121FFFE, 0x5911FE94, 0x14100000,\n    0xC000693C, 0xCA8000F8, 0xC000694E, 0xCAC000F8, 0xC3000018, 0xC3400006, 0x5E200000, 0x8400002A,\n    0xC2800000, 0xC2C00000, 0xC300001E, 0xC3400000, 0xC6AC1078, 0xC72C0418, 0xC76C0810, 0x58380010,\n    0xCA8000F8, 0x58380008, 0xCEC000F8, 0xC6280100, 0xC000ABE0, 0xC80400F8, 0x6C908000, 0x45088000,\n    0x45088000, 0x40100000, 0xCB0000F8, 0xC43400F8, 0x00000000, 0xC74000F8, 0xCE8000F8, 0xC0006952,\n    0xCE8000F8, 0x00000000, 0x00000000, 0x00000000, 0xA8E2FFE8, 0x00000000, 0xC000694C, 0xCA0000F8,\n    0xC0006950, 0xCAC000F8, 0x5E200000, 0x8400006A, 0xDFE800F8, 0x7E814000, 0x5834001A, 0xCE8000F8,\n    0x99005FD8, 0xC0009DF4, 0xC94000F8, 0xC1800002, 0x99005FD8, 0xC0009DF8, 0xC94000F8, 0xC6D800F8,\n    0xC1220002, 0xD90C00F8, 0x5E200000, 0x84000040, 0x5838002C, 0xCB0000F8, 0xDFE800F8, 0x00000000,\n    0x58380014, 0xCF0000F8, 0x80000018, 0xC2A1FFFE, 0x5AA9FFFE, 0x5838000A, 0xCE8000F8, 0xC3000000,\n    0xC000EA14, 0xCB040038, 0xC2D00002, 0xC000EA28, 0xCEC50800, 0xC000694E, 0xCA8000F8, 0x58880002,\n    0xB4B00018, 0xC0009F74, 0xC0800000, 0xCC8400F8, 0x5EA80000, 0x84000152, 0x5E200000, 0x84000140,\n    0xC000693C, 0xCA8000F8, 0x00000000, 0x00000000, 0x5AA80060, 0xCE8000F8, 0x99005970, 0xDBD800F8,\n    0xDB9800F9, 0xC78000F8, 0x99005B70, 0xDBD800F8, 0xDB9800F9, 0xC78000F8, 0xC0006952, 0xCAC000F8,\n    0x58380000, 0xCA8000F8, 0xC30C0002, 0xC7F00018, 0xA6800098, 0x00000000, 0x00000000, 0xC161FFFE,\n    0x5955FFFE, 0x14140000, 0x00000000, 0xC000F800, 0xCA0000F8, 0x00000000, 0x00000000, 0xA60CFFEA,\n    0xC6F00500, 0xC6B0C400, 0xCF0000F8, 0x00000000, 0xC121FFFE, 0x5911FE94, 0x14100000, 0x8000CFB0,\n    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x8000CF48, 0xDCBC00F9, 0x5FFC0000, 0x84000052,\n    0xC3800002, 0xDB8800F9, 0x5FFC0004, 0x8400C86A, 0xC3800000, 0xDB8800F9, 0xC3CE0002, 0xC000E800,\n    0xCFC0E700, 0xC3E1FFFE, 0x597DFFFE, 0x593DFE14, 0x94000001, 0x00000000, 0x00000000, 0x00000000,\n    0xC000ABE8, 0xC80400F8, 0x00000000, 0x00000000, 0x40080000, 0xCBC000F8, 0xC43800F8, 0x00000000,\n    0xC000402E, 0xCA0000F8, 0xC000ABD8, 0xCB4400F8, 0x00000000, 0x00000000, 0x47610000, 0x880000B0,\n    0x00000000, 0xA7C00048, 0xC000ABD4, 0xC1000002, 0xCD0400F8, 0xC11C0000, 0xC000E82C, 0xCD05CE00,\n    0x800000D8, 0x00000000, 0xA7D20120, 0x00000000, 0xC7E14040, 0xC2400000, 0xC6246028, 0xC200006A,\n    0x46250000, 0xC6240030, 0xC000E810, 0xCE440030, 0x8000FF70, 0xC2000000, 0xC000E808, 0xCA040010,\n    0xC11C0000, 0xC000E82C, 0xCD05CE00, 0x5A200002, 0x5E600010, 0x84000010, 0xC2000000, 0xC000E808,\n    0xCE040010, 0xC3400000, 0x80000010, 0x5B740002, 0xC000ABD8, 0xCF4400F8, 0x99004F78, 0xC000ABC8,\n    0xC94400F8, 0xC1800000, 0xC11C0002, 0xC000E82C, 0xCD05CE00, 0x80000600, 0x5B740002, 0xC000ABD8,\n    0xCF4400F8, 0xC78000F8, 0xC13C0002, 0xCD03DE00, 0xC000ABC8, 0xC94400F8, 0xC1800000, 0xC000E82C,\n    0xC9840038, 0x59540002, 0xC000ABC8, 0xCD4400F8, 0x58880002, 0xB4980580, 0x00000000, 0xC0800000,\n    0x80000568, 0xC000ABE8, 0xC80400F8, 0x00000000, 0x00000000, 0x40080000, 0xCBC000F8, 0xC42800F8,\n    0x00000000, 0xA7C00130, 0xC000ABCC, 0xCA0400F8, 0xC2400000, 0xC000FAEC, 0xCA440018, 0x5A200002,\n    0xC000ABCC, 0xCE0400F8, 0xB624008A, 0xC68000F8, 0xC13C0002, 0xCD03DE00, 0xC000ABC8, 0xC94400F8,\n    0xC1800000, 0xC000E82C, 0xC9840038, 0x59540002, 0xC000ABC8, 0xCD4400F8, 0x58880002, 0xB4980470,\n    0x00000000, 0xC0800000, 0x80000458, 0xC000ABD4, 0xC1000004, 0xCD0400F8, 0xC000E820, 0xC2000002,\n    0xCE0400F8, 0xC2000000, 0xC000ABCC, 0xCE0400F8, 0xC000ABD8, 0xCE0400F8, 0x8000FF28, 0xC000ABD4,\n    0xC1000000, 0xCD0400F8, 0xC11C0000, 0xC000E82C, 0xCD05CE00, 0x99004F78, 0xC000ABC8, 0xC94400F8,\n    0xC1800000, 0xC1200000, 0xC000E818, 0xCD061000, 0xC11C0002, 0xC000E82C, 0xCD05CE00, 0xC2000000,\n    0xC000ABCC, 0xCE0400F8, 0x80000358, 0xC000FAC0, 0xCB8400F8, 0xC000ABE8, 0xC80400F8, 0x00000000,\n    0x00000000, 0x40080000, 0xCBC000F8, 0xC42800F8, 0x00000000, 0x00000000, 0xC68000F8, 0xC13C0000,\n    0xCD03DE00, 0xA780024A, 0x00000000, 0x00000000, 0xA7C0020A, 0x00000000, 0xC000FB60, 0xC2060006,\n    0xCE046308, 0xA7E801C2, 0x00000000, 0xC000ABD0, 0xCA0400F8, 0xC2400000, 0xC000FAEC, 0xCA448018,\n    0x5A200002, 0xC000ABD0, 0xCE0400F8, 0xB62400AA, 0x00000000, 0xC68000F8, 0xC13C0002, 0xCD03DE00,\n    0xC000FACC, 0xC2000002, 0xCE040000, 0xC000ABC8, 0xC94400F8, 0xC1800000, 0xC000E82C, 0xC9840038,\n    0x59540002, 0xC000ABC8, 0xCD4400F8, 0x58880002, 0xB49801C8, 0x00000000, 0xC0800000, 0x800001B0,\n    0xC000ABD4, 0xC1000000, 0xCD0400F8, 0xC11C0000, 0xC000E82C, 0xCD05CE00, 0x99004F78, 0xC000ABC8,\n    0xC94400F8, 0xC1800000, 0xC2000000, 0xC000E820, 0xCE0400F8, 0xC1200000, 0xC000E818, 0xCD061000,\n    0xC11C0002, 0xC000E82C, 0xCD05CE00, 0xC000ABD0, 0xCE0400F8, 0xC2000002, 0xC000FACC, 0xCE040008,\n    0x800000E8, 0xC2000002, 0xC000ABD0, 0xCE0400F8, 0x8000FE88, 0xC2000000, 0xC000ABD0, 0xCE0400F8,\n    0xA7E60032, 0x00000000, 0xC2000002, 0xC000FB60, 0xCE040000, 0x8000FE70, 0x00000000, 0xA7860052,\n    0x00000000, 0xC68000F8, 0xC13C0002, 0xCD03DE00, 0xC2020002, 0xC7E2A540, 0xC000FB60, 0xCE0400F8,\n    0x8000FE18, 0xC2040002, 0xC000FB60, 0xCE044200, 0x8000FDF8, 0xC2C80002, 0x6AC56000, 0xDACC00F8,\n    0xC000ABD4, 0xCB4400F8, 0xC000ABC8, 0xCB8400F8, 0xC000E838, 0xC3C00000, 0xCBC40038, 0x5EF40004,\n    0x84000022, 0xC3000000, 0xC000FACC, 0xCF042100, 0x47F98000, 0x8400002A, 0x47F98000, 0x88000030,\n    0xC1006E8C, 0x8000BCB8, 0xC000ABC0, 0xCC8400F8, 0x8000F6C8, 0xC000FAC0, 0xCAC400F8, 0xC000ABD4,\n    0xCB4400F8, 0xA6C0FBD2, 0x00000000, 0x5EF40000, 0x8400F722, 0x5EF40002, 0x8400F99A, 0x5EF40004,\n    0x8400FB9A, 0xC1006CE8, 0x8000BC30, 0x00000000, 0xC0800000, 0xDF4B0038, 0xC0006900, 0xCB8000F8,\n    0xC2000000, 0xC000690A, 0xA78000D0, 0xCBC000F8, 0xC1000000, 0xD90000F9, 0xC1000002, 0xD90C00F8,\n    0x6FF46000, 0x477DA000, 0x5B749F00, 0xC2400000, 0x58340004, 0xCA400078, 0xC0006900, 0xCE000000,\n    0x5A640002, 0x58340004, 0xC6500078, 0xCD000078, 0xC0006914, 0xCA4000F8, 0xC2000002, 0x6A3D0000,\n    0x72612000, 0xCE4000F8, 0xC000E408, 0xCE0000F8, 0xA78200D8, 0xC0006908, 0xCBC000F8, 0xC1000000,\n    0xD90000F9, 0xC1000002, 0xD90C00F8, 0x6FF4A000, 0x6FD44000, 0x4755A000, 0x477DA000, 0x5B747400,\n    0xC2800000, 0x58340006, 0xCA800078, 0xC2000000, 0xC0006900, 0xCE002100, 0x5EA80002, 0x58340006,\n    0xC6900078, 0xCD000078, 0x5A7C0020, 0xC2000002, 0x6A250000, 0xC000E408, 0xCE0000F8, 0xDCA800F9,\n    0x5EA80000, 0x8400BAA0, 0x00000000, 0xA4800230, 0x00000000, 0xC3C00000, 0xC000F418, 0xCBC00018,\n    0xC3400000, 0xC2400000, 0x6FF86000, 0x47BDC000, 0x5BB89F00, 0x58380008, 0xCB400078, 0x58380006,\n    0xCA400078, 0x5F740002, 0x58380008, 0xC7500078, 0xCD000078, 0xC2000000, 0x58380004, 0xCA020078,\n    0xC3000000, 0x5838000C, 0xCB000020, 0x5A640002, 0x46610000, 0x84000010, 0xC2400000, 0x58380006,\n    0xC6500078, 0xCD000078, 0xC2000000, 0x5838000A, 0xCA020078, 0x5B300002, 0x5838000C, 0xC7100020,\n    0xCD000020, 0xC2420020, 0x5A200004, 0x46252000, 0x84000010, 0xC2000000, 0x5838000A, 0xC6101078,\n    0xCD021078, 0xC0006966, 0xCA4000F8, 0xC2000002, 0x6A3D0000, 0x72612000, 0xCE4000F8, 0x5F740000,\n    0x84000040, 0xC0006912, 0xCA0000F8, 0xC2C00002, 0x6AFD6000, 0x7EC16000, 0x762D0000, 0xCE0000F8,\n    0x5F300020, 0x84000040, 0xC0006924, 0xCA0000F8, 0xC2C00002, 0x6AFD6000, 0x7EC16000, 0x762D0000,\n    0xCE0000F8, 0xA4820070, 0xC2400000, 0xC000F418, 0xCA408018, 0xC2000002, 0xC0006900, 0xCE000000,\n    0xC000690A, 0xCE4000F8, 0xC1000000, 0xD90000F9, 0xD8400078, 0xC1000004, 0xD90000F9, 0xA4840270,\n    0x00000000, 0xC3C00000, 0xC000F418, 0xCBC10018, 0xC2800000, 0xC2000000, 0x6FF8A000, 0x6FD44000,\n    0x4795C000, 0x47BDC000, 0x5BB87400, 0x5838002E, 0xCA800078, 0x58380006, 0xCA020078, 0xC3400000,\n    0x5838002E, 0xCB420078, 0x5AA80002, 0x46A10000, 0x84000010, 0xC2800000, 0x5838002E, 0xC6900078,\n    0xCD000078, 0x5F740002, 0x5838002E, 0xC7501078, 0xCD021078, 0xC0006968, 0xCA4000F8, 0xC2000002,\n    0x6A3D0000, 0x72612000, 0xCE4000F8, 0xC000692A, 0xCA8000F8, 0x5E740000, 0x84000040, 0xC0006910,\n    0xCA0000F8, 0xC2C00002, 0x6AFD6000, 0x7EC16000, 0x762D0000, 0xCE0000F8, 0x6ABD4010, 0xA68000BA,\n    0x00000000, 0x58380032, 0xCA0000F8, 0x58000002, 0xCA4000F8, 0x5838000C, 0x00000000, 0xCE0000F9,\n    0xCE4000F8, 0xC000692A, 0xCA0000F8, 0xC2C00002, 0x6AFD6000, 0x722D0000, 0xCE0000F8, 0xC000692C,\n    0xCA0000F8, 0xC2C00002, 0x6AFD6000, 0x722D0000, 0xCE0000F8, 0x80000040, 0xC000692C, 0xCA0000F8,\n    0xC2C00002, 0x6AFD6000, 0x7EC16000, 0x762D0000, 0xCE0000F8, 0xA4880120, 0xC2C00000, 0xC000F418,\n    0xCAC20018, 0xC000690E, 0xCA4000F8, 0xC2000002, 0x6A2D0000, 0x7E010000, 0x76612000, 0xCE4000F8,\n    0xC000696A, 0xCA4000F8, 0xC2000002, 0x6A2D0000, 0x72612000, 0xCE4000F8, 0x6EF0A000, 0x6ED44000,\n    0x47158000, 0x472D8000, 0x5B307400, 0x58300000, 0xCA0000F8, 0x00000000, 0xC2400002, 0x76612000,\n    0x8400004A, 0xC24C0002, 0xC6E40018, 0xC624C400, 0x58300010, 0xCA400500, 0x00000000, 0xC000F800,\n    0xCE4000F8, 0xA4860070, 0xC2400000, 0xC000F418, 0xCA418018, 0xC2020002, 0xC0006900, 0xCE002100,\n    0xC0006908, 0xCE4000F8, 0xC1000000, 0xD90000F9, 0xD8400078, 0xC1000004, 0xD90000F9, 0xC000F414,\n    0xCC8000F8, 0xC10E0002, 0xD90C00F8, 0x8000EDF0, 0xDFBC00F9, 0xC000696E, 0x99005C80, 0xC94000F8,\n    0xC7D800F8, 0x00000000, 0xC57000F8, 0x5EF00020, 0x88000148, 0x6F346000, 0x4771A000, 0x5B749F00,\n    0x58340008, 0xC2400000, 0xCA400078, 0x00000000, 0xC2000000, 0x5A640002, 0xCE400078, 0x58340004,\n    0xCA000078, 0x00000000, 0x00000000, 0x5E200002, 0xCE000078, 0xC0006912, 0xCA8000F8, 0xC2400002,\n    0x6A712000, 0x72A54000, 0xCE8000F8, 0x5E200000, 0x84000052, 0xC000402A, 0xCA0000F8, 0xC000E408,\n    0xCA8000F8, 0x76250000, 0x00000000, 0x72A14000, 0xCE8000F8, 0x80000038, 0xC0006914, 0xCA0000F8,\n    0x7E412000, 0x00000000, 0x76250000, 0xCE0000F8, 0x800000D0, 0x6EF4A000, 0x6ED44000, 0x4755A000,\n    0x476DA000, 0x5B747400, 0x5834002E, 0xC2400000, 0xCA420078, 0x00000000, 0xC2000000, 0x5A640002,\n    0xC6501078, 0xCD021078, 0x58340006, 0xCA000078, 0x00000000, 0x00000000, 0x5A200002, 0xCE000078,\n    0xC0006910, 0xCA4000F8, 0xC2000002, 0x6A2D0000, 0x72612000, 0xCE4000F8, 0xC2000002, 0x6A310000,\n    0xC000E42A, 0xCE0000F8, 0xC1040002, 0xD90C00F8, 0x00000000, 0x8000EB60, 0x00000000, 0xC4980928,\n    0x9D000000, 0xC5580038, 0xC000E838, 0xCD8400F8, 0xC1440080, 0xC1C06B40, 0xC55C0F80, 0xC000F00E,\n    0x9D000000, 0xCD8000F8, 0xC000F00C, 0xCDC000F8, 0xC000ABDE, 0xC9C000F8, 0x00000000, 0x00000000,\n    0xD9D800F9, 0xC000AB40, 0x401C0000, 0x5DC0ABC0, 0x88000012, 0x5C000080, 0xCD8000F8, 0xC1F0000A,\n    0x715CA000, 0xDD9800F8, 0xDD9C00F9, 0x41D8E000, 0xC5D40260, 0xC000F010, 0xCD4000F8, 0x6C9C8000,\n    0x45C8E000, 0x45C8E000, 0x59DC0004, 0xC1601260, 0xC5D40260, 0x9D000000, 0xC000F012, 0xCD4000F8,\n    0x00000000, 0x00000000, 0xD95800F8, 0x6D586000, 0x4594C000, 0x59989F00, 0xD99800F9, 0x5818000A,\n    0xC1800000, 0xC9800078, 0xC0007200, 0x6D5CA000, 0x401C0000, 0x40180000, 0xC94000F8, 0x58000002,\n    0x00000000, 0xC9C000F8, 0xC0006930, 0xCD4000F8, 0xC0006932, 0xCDC000F8, 0x59980004, 0xC1C20020,\n    0xB59C0018, 0x00000000, 0xC1800000, 0xDD9C00F9, 0x581C000A, 0xCD800078, 0x581C000C, 0xC1800000,\n    0xC9800020, 0xC1C00002, 0xDD9400F8, 0x69D4E000, 0x5D980002, 0xCD800020, 0xC0006924, 0xC98000F8,\n    0x00000000, 0x9D000000, 0x00000000, 0x719CC000, 0xCD8000F8, 0xC000692A, 0xC94000F8, 0xC1C00002,\n    0x69D8E000, 0x7DC0C000, 0x7558A000, 0xCD4000F8, 0xC000692C, 0xC94000F8, 0xDD8000F9, 0x58000032,\n    0x755CA000, 0x84000090, 0xC94000F9, 0xC98000F8, 0xDD8000F9, 0x5800000C, 0x00000000, 0xCD4000F9,\n    0xCD8000F8, 0xC000692C, 0xC94000F8, 0xC000692A, 0xC98000F8, 0x715CA000, 0xC000692C, 0xCD4000F8,\n    0x719CC000, 0xC000692A, 0xCD8000F8, 0x9D000000, 0x00000000, 0x00000000, 0x00000000, 0xC000ABDE,\n    0xC98000F8, 0x00000000, 0xC1C00080, 0x4194C000, 0x459CE000, 0x88000012, 0xC5D800F8, 0xC000ABDE,\n    0xCD8000F8, 0xC000F406, 0xC98000F8, 0xC1C00002, 0x9D000000, 0xC5D80A00, 0xC5581048, 0xCD8000F8,\n    0xC0006930, 0xC98000F8, 0xC0006932, 0xC9C000F8, 0xC140000E, 0xC5581C18, 0xDD9400F8, 0xC000AB40,\n    0x40140000, 0x5D40ABC0, 0x88000012, 0x5C000080, 0xCD8000F8, 0x58000002, 0x5D40ABC0, 0x88000012,\n    0x5C000080, 0xCDC000F8, 0xDD5400F8, 0xC1C00000, 0x58140006, 0xC9C20078, 0xC1800000, 0x58140000,\n    0xC98000D8, 0x6DDC2000, 0xC000691E, 0x41D8E000, 0xCDC000F8, 0xDD9800F8, 0xC1C00022, 0xC5D80D70,\n    0xDD9400F9, 0xC5581C18, 0xC000691C, 0xCD8000F8, 0xDD5400F8, 0xC1C00000, 0x58140006, 0xC9C20078,\n    0xC1800000, 0x58140004, 0xC9820078, 0x00000000, 0x59DC0002, 0x45D8C000, 0x84000010, 0xC1C00000,\n    0x9D000000, 0x58140006, 0xC5D81078, 0xCD821078, 0xC000ABDC, 0xC94000F8, 0xC1820020, 0xC1D00002,\n    0x5814AB00, 0xD58000F8, 0x58000002, 0xD58000F9, 0x59540004, 0xB5580018, 0xC000ABDC, 0xC1400000,\n    0xCD4000F8, 0xDD9800F9, 0x9D000000, 0xDD9400F8, 0xC000F402, 0xCDC10800, 0xC1C00000, 0xC1800080,\n    0x5D980004, 0xDF5D0048, 0x459CA000, 0x8800FFF2, 0xDD8000F9, 0x5800000C, 0x00000000, 0xC94000F9,\n    0xC98000F8, 0xC1C00002, 0xC5D43F00, 0xC5D81E00, 0xC000ABDE, 0xC9C000F8, 0x00000000, 0x00000000,\n    0x581CAB40, 0x5DC0ABC0, 0x88000012, 0x5C000080, 0xCD4000F8, 0x58000002, 0x5DC0ABC0, 0x88000012,\n    0x5C000080, 0xCD8000F8, 0xC000ABDE, 0xC9C000F8, 0x00000000, 0xC15004C0, 0xC5D40060, 0xDD9C00F8,\n    0xC5D41C18, 0xC1C00000, 0xDD8000F9, 0x58000030, 0xC9C00078, 0xDD8000F9, 0x58000002, 0xC98000F8,\n    0x6DDC2000, 0xC000691C, 0x41D8E000, 0xCD4000F9, 0xCDC000F8, 0xDD9400F9, 0xC1C00000, 0x58140030,\n    0xC9C00078, 0xC1800000, 0x58140006, 0xC9820078, 0x00000000, 0x59DC0002, 0x45D8C000, 0x84000010,\n    0xC1C00000, 0x9D000000, 0x58140030, 0xC5D80078, 0xCD800078, 0xC1C00000, 0xDF5C0038, 0x5DDC0020,\n    0x8400FFEA, 0x00000000, 0x9D000000, 0x00000000, 0x00000000, 0x00000000, 0xC160FFFE, 0xC000EA10,\n    0xC9440070, 0xC1A0FFFE, 0x59983408, 0xC000F00C, 0xCD4000F8, 0xC000F00E, 0xCD8000F8, 0xC0006964,\n    0xC98000F8, 0x00000000, 0xC170000A, 0x7158A000, 0x6C988000, 0x4588C000, 0x4588C000, 0x59980004,\n    0xC5940270, 0xC000F010, 0xCD4000F8, 0xC0006946, 0xC94000F8, 0x00000000, 0x00000000, 0x6D58A000,\n    0x6D5C4000, 0x459CC000, 0x4594C000, 0xC000694A, 0xC94000F8, 0xC0006948, 0xC9C000F8, 0x4194C000,\n    0xC1400012, 0xC55C1818, 0x9D000000, 0xC59C0268, 0xC000F012, 0xCDC000F8, 0xC1400000, 0x58000012,\n    0xC9410038, 0xC0006950, 0xC9C000F8, 0xC55800F8, 0xC5940838, 0xC5581078, 0xD99400F8, 0xC000693C,\n    0xC94000F8, 0xC0006954, 0xC98000F8, 0x59DC00A8, 0x45D4E000, 0x41D8E000, 0x5D5C0030, 0x88000010,\n    0xC1C00030, 0xC1800000, 0xC5D84028, 0xC1400000, 0xC5D40008, 0x5DD40002, 0x84000072, 0x5DD40004,\n    0x8400009A, 0x5DD40006, 0x840000C2, 0x5DD80026, 0x840000EA, 0xDD5400F8, 0xDD8000F9, 0x58000008,\n    0x40180000, 0xCD4000F8, 0x59980002, 0x8000FFC0, 0xDD5400F8, 0xDD8000F9, 0x58000008, 0x40180000,\n    0xCD4000B8, 0x59980002, 0x8000FF88, 0xDD5400F8, 0xDD8000F9, 0x58000008, 0x40180000, 0xCD400078,\n    0x59980002, 0x8000FF50, 0xDD5400F8, 0xDD8000F9, 0x58000008, 0x40180000, 0xCD400038, 0x59980002,\n    0x8000FF18, 0x00000000, 0x9D000000, 0x00000000, 0x00000000, 0x00000000, 0x58000012, 0xC94000F8,\n    0xC0006954, 0xC9C000F8, 0xC0006950, 0xC9400078, 0xDD8000F9, 0x58000028, 0x5D9C0000, 0x84000052,\n    0x5D9C0002, 0x84000052, 0x5D9C0004, 0x8400006A, 0xC55B0038, 0xC55C08B8, 0xCD800039, 0xCDC108B8,\n    0x80000060, 0xCD4000F8, 0x80000050, 0xC55900B8, 0xC55C1838, 0xCD8000B9, 0xCDC31838, 0x80000028,\n    0xC55A0078, 0xC55C1078, 0xCD800079, 0xCDC21078, 0x9D000000, 0x00000000, 0x00000000, 0x00000000,\n    0x59540002, 0x6994E018, 0x61C0C008, 0x4194A000, 0x5D940040, 0x88000012, 0xC59400F8, 0x9D000000,\n    0xCD4000F8, 0x00000000, 0x00000000, 0xC000697E, 0xCA4000F8, 0xC0000000, 0xC55800F8, 0xC9D400F9,\n    0x00000000, 0x00000000, 0x79E08000, 0xCD1800F9, 0xC5D000F8, 0xC9D400F9, 0xC66000F8, 0xC52160A0,\n    0xC5241550, 0x79E08000, 0xCD1800F9, 0xC5D000F8, 0xC9D400F9, 0xC66000F8, 0xC52160A0, 0xC5241550,\n    0x79E08000, 0xCD1800F9, 0xC5D000F8, 0xC9D400F9, 0xC66000F8, 0xC52160A0, 0xC5241550, 0x79E08000,\n    0xCD1800F9, 0xC5D000F8, 0xC9D400F9, 0xC66000F8, 0xC52160A0, 0xC5241550, 0x79E08000, 0xCD1800F9,\n    0xC5D000F8, 0xC9D400F9, 0xC66000F8, 0xC52160A0, 0xC5241550, 0x79E08000, 0xCD1800F9, 0xC5D000F8,\n    0xC9D400F9, 0xC66000F8, 0xC52160A0, 0xC5241550, 0x79E08000, 0xCD1800F9, 0xC5D000F8, 0xC9D400F9,\n    0xC66000F8, 0xC52160A0, 0xC5241550, 0x79E08000, 0xCD1800F9, 0xC5D000F8, 0xC9D400F9, 0xC66000F8,\n    0xC52160A0, 0xC5241550, 0x79E08000, 0xCD1800F9, 0xC5D000F8, 0xC9D400F9, 0xC66000F8, 0xC52160A0,\n    0xC5241550, 0x79E08000, 0xCD1800F9, 0xC5D000F8, 0xC9D400F9, 0xC66000F8, 0xC52160A0, 0xC5241550,\n    0x79E08000, 0xCD1800F9, 0xC5D000F8, 0xC9D400F9, 0xC66000F8, 0xC52160A0, 0xC5241550, 0x79E08000,\n    0xCD1800F9, 0xC5D000F8, 0xC9D400F9, 0xC66000F8, 0xC52160A0, 0xC5241550, 0xC000697C, 0x9CC00000,\n    0xCE0000F8, 0xC000697E, 0xCE4000F8, 0x9D000000, 0x4158A000, 0xCD4000F8, 0x00000000,\n};\n\nstatic u32 vr9_fw_data[] = {\n};\n\n\n#endif  //  IFXMIPS_ATM_FW_VR9_H\n\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-atm/src/ifxmips_atm_ppe_amazon_se.h",
    "content": "/******************************************************************************\n**\n** FILE NAME    : ifxmips_atm_ppe_amazon_se.h\n** PROJECT      : UEIP\n** MODULES     \t: ATM (ADSL)\n**\n** DATE         : 1 AUG 2005\n** AUTHOR       : Xu Liang\n** DESCRIPTION  : ATM Driver (PPE Registers)\n** COPYRIGHT    : \tCopyright (c) 2006\n**\t\t\tInfineon Technologies AG\n**\t\t\tAm Campeon 1-12, 85579 Neubiberg, Germany\n**\n**    This program is free software; you can redistribute it and/or modify\n**    it under the terms of the GNU General Public License as published by\n**    the Free Software Foundation; either version 2 of the License, or\n**    (at your option) any later version.\n**\n** HISTORY\n** $Date        $Author         $Comment\n**  4 AUG 2005  Xu Liang        Initiate Version\n** 23 OCT 2006  Xu Liang        Add GPL header.\n**  9 JAN 2007  Xu Liang        First version got from Anand (IC designer)\n*******************************************************************************/\n\n\n\n#ifndef IFXMIPS_ATM_PPE_AMAZON_SE_H\n#define IFXMIPS_ATM_PPE_AMAZON_SE_H\n\n\n\n/*\n *  FPI Configuration Bus Register and Memory Address Mapping\n */\n#define IFX_PPE                         (KSEG1 | 0x1E180000)\n#define PP32_DEBUG_REG_ADDR(i, x)       ((volatile unsigned int*)(IFX_PPE + (((x) + 0x0000) << 2)))\n#define PPM_INT_REG_ADDR(i, x)          ((volatile unsigned int*)(IFX_PPE + (((x) + 0x0030) << 2)))\n#define PP32_INTERNAL_RES_ADDR(i, x)    ((volatile unsigned int*)(IFX_PPE + (((x) + 0x0040) << 2)))\n#define CDM_CODE_MEMORY(i, x)           ((volatile unsigned int*)(IFX_PPE + (((x) + 0x1000) << 2)))\n#define PPE_REG_ADDR(x)                 ((volatile unsigned int*)(IFX_PPE + (((x) + 0x4000) << 2)))\n#define CDM_DATA_MEMORY(i, x)           ((volatile unsigned int*)(IFX_PPE + (((x) + 0x5000) << 2)))\n#define PPM_INT_UNIT_ADDR(x)            ((volatile unsigned int*)(IFX_PPE + (((x) + 0x6000) << 2)))\n#define PPM_TIMER0_ADDR(x)              ((volatile unsigned int*)(IFX_PPE + (((x) + 0x6100) << 2)))\n#define PPM_TASK_IND_REG_ADDR(x)        ((volatile unsigned int*)(IFX_PPE + (((x) + 0x6200) << 2)))\n#define PPS_BRK_ADDR(x)                 ((volatile unsigned int*)(IFX_PPE + (((x) + 0x6300) << 2)))\n#define PPM_TIMER1_ADDR(x)              ((volatile unsigned int*)(IFX_PPE + (((x) + 0x6400) << 2)))\n#define SB_RAM0_ADDR(x)                 ((volatile unsigned int*)(IFX_PPE + (((x) + 0x8200) << 2)))\n#define SB_RAM1_ADDR(x)                 ((volatile unsigned int*)(IFX_PPE + (((x) + 0x8C00) << 2)))\n#define QSB_CONF_REG_ADDR(x)            ((volatile unsigned int*)(IFX_PPE + (((x) + 0xC000) << 2)))\n\n/*\n *  DWORD-Length of Memory Blocks\n */\n#define PP32_DEBUG_REG_DWLEN            0x0030\n#define PPM_INT_REG_DWLEN               0x0010\n#define PP32_INTERNAL_RES_DWLEN         0x00C0\n#define CDM_CODE_MEMORYn_DWLEN(n)       ((n) == 0 ? 0x1000 : 0x0800)\n#define PPE_REG_DWLEN                   0x1000\n#define CDM_DATA_MEMORY_DWLEN           CDM_CODE_MEMORYn_DWLEN(1)\n#define PPM_INT_UNIT_DWLEN              0x0100\n#define PPM_TIMER0_DWLEN                0x0100\n#define PPM_TASK_IND_REG_DWLEN          0x0100\n#define PPS_BRK_DWLEN                   0x0100\n#define PPM_TIMER1_DWLEN                0x0100\n#define SB_RAM0_DWLEN                   0x0A00\n#define SB_RAM1_DWLEN                   0x0A00\n#define QSB_CONF_REG_DWLEN              0x0100\n\n/*\n *  PP32 to FPI Address Mapping\n */\n#define SB_BUFFER(__sb_addr)            ((volatile unsigned int *)((((__sb_addr) >= 0x2200) && ((__sb_addr) <= 0x2BFF)) ? SB_RAM0_ADDR((__sb_addr) - 0x2200) :   \\\n                                                                   (((__sb_addr) >= 0x2C00) && ((__sb_addr) <= 0x35FF)) ? SB_RAM1_ADDR((__sb_addr) - 0x2C00) :   \\\n                                                                0))\n\n/*\n *  PP32 Debug Control Register\n */\n#define PP32_DBG_CTRL                   PP32_DEBUG_REG_ADDR(0, 0x0000)\n\n#define DBG_CTRL_RESTART                0\n#define DBG_CTRL_STOP                   1\n\n#define PP32_HALT_STAT                  PP32_DEBUG_REG_ADDR(0, 0x0D00)\n#define PP32_BREAKPOINT_REASONS         PP32_DEBUG_REG_ADDR(0, 0x0A00)\n\n#define PP32_BRK_SRC                    PP32_DEBUG_REG_ADDR(0, 0x0F00)\n\n#define PP32_DBG_CUR_PC                 PP32_DEBUG_REG_ADDR(0, 0x0F80)\n\n#define PP32_DBG_TASK_NO                PP32_DEBUG_REG_ADDR(0, 0x0F81)\n\n/*\n *  Share Buffer\n */\n#define SB_MST_PRI0                     PPE_REG_ADDR(0x0300)\n#define SB_MST_PRI1                     PPE_REG_ADDR(0x0301)\n\n/*\n *  EMA Registers\n */\n#define EMA_CMDCFG                      PPE_REG_ADDR(0x0A00)\n#define EMA_DATACFG                     PPE_REG_ADDR(0x0A01)\n#define EMA_CMDCNT                      PPE_REG_ADDR(0x0A02)\n#define EMA_DATACNT                     PPE_REG_ADDR(0x0A03)\n#define EMA_ISR                         PPE_REG_ADDR(0x0A04)\n#define EMA_IER                         PPE_REG_ADDR(0x0A05)\n#define EMA_CFG                         PPE_REG_ADDR(0x0A06)\n#define EMA_SUBID                       PPE_REG_ADDR(0x0A07)\n\n#define EMA_ALIGNMENT                   4\n\n/*\n *  Mailbox IGU1 Interrupt\n */\n#define PPE_MAILBOX_IGU1_INT            INT_NUM_IM2_IRL13\n\n\n\n#endif  //  IFXMIPS_ATM_PPE_AMAZON_SE_H\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-atm/src/ifxmips_atm_ppe_ar9.h",
    "content": "/******************************************************************************\n**\n** FILE NAME    : ifxmips_atm_ppe_ar9.h\n** PROJECT      : UEIP\n** MODULES     \t: ATM (ADSL)\n**\n** DATE         : 1 AUG 2005\n** AUTHOR       : Xu Liang\n** DESCRIPTION  : ATM Driver (PPE Registers)\n** COPYRIGHT    : \tCopyright (c) 2006\n**\t\t\tInfineon Technologies AG\n**\t\t\tAm Campeon 1-12, 85579 Neubiberg, Germany\n**\n**    This program is free software; you can redistribute it and/or modify\n**    it under the terms of the GNU General Public License as published by\n**    the Free Software Foundation; either version 2 of the License, or\n**    (at your option) any later version.\n**\n** HISTORY\n** $Date        $Author         $Comment\n**  4 AUG 2005  Xu Liang        Initiate Version\n** 23 OCT 2006  Xu Liang        Add GPL header.\n**  9 JAN 2007  Xu Liang        First version got from Anand (IC designer)\n*******************************************************************************/\n\n\n\n#ifndef IFXMIPS_ATM_PPE_AR9_H\n#define IFXMIPS_ATM_PPE_AR9_H\n\n\n\n/*\n *  FPI Configuration Bus Register and Memory Address Mapping\n */\n#define IFX_PPE                         (KSEG1 | 0x1E180000)\n#define PP32_DEBUG_REG_ADDR(i, x)       ((volatile unsigned int*)(IFX_PPE + (((x) + 0x0000) << 2)))\n#define PPM_INT_REG_ADDR(i, x)          ((volatile unsigned int*)(IFX_PPE + (((x) + 0x0030) << 2)))\n#define PP32_INTERNAL_RES_ADDR(i, x)    ((volatile unsigned int*)(IFX_PPE + (((x) + 0x0040) << 2)))\n#define CDM_CODE_MEMORY(i, x)           ((volatile unsigned int*)(IFX_PPE + (((x) + 0x1000) << 2)))\n#define PPE_REG_ADDR(x)                 ((volatile unsigned int*)(IFX_PPE + (((x) + 0x4000) << 2)))\n#define CDM_DATA_MEMORY(i, x)           ((volatile unsigned int*)(IFX_PPE + (((x) + 0x5000) << 2)))\n#define PPM_INT_UNIT_ADDR(x)            ((volatile unsigned int*)(IFX_PPE + (((x) + 0x6000) << 2)))\n#define PPM_TIMER0_ADDR(x)              ((volatile unsigned int*)(IFX_PPE + (((x) + 0x6100) << 2)))\n#define PPM_TASK_IND_REG_ADDR(x)        ((volatile unsigned int*)(IFX_PPE + (((x) + 0x6200) << 2)))\n#define PPS_BRK_ADDR(x)                 ((volatile unsigned int*)(IFX_PPE + (((x) + 0x6300) << 2)))\n#define PPM_TIMER1_ADDR(x)              ((volatile unsigned int*)(IFX_PPE + (((x) + 0x6400) << 2)))\n#define SB_RAM0_ADDR(x)                 ((volatile unsigned int*)(IFX_PPE + (((x) + 0x8000) << 2)))\n#define SB_RAM1_ADDR(x)                 ((volatile unsigned int*)(IFX_PPE + (((x) + 0x8800) << 2)))\n#define SB_RAM2_ADDR(x)                 ((volatile unsigned int*)(IFX_PPE + (((x) + 0x9000) << 2)))\n#define SB_RAM3_ADDR(x)                 ((volatile unsigned int*)(IFX_PPE + (((x) + 0x9800) << 2)))\n#define SB_RAM4_ADDR(x)                 ((volatile unsigned int*)(IFX_PPE + (((x) + 0xA000) << 2)))\n#define QSB_CONF_REG_ADDR(x)            ((volatile unsigned int*)(IFX_PPE + (((x) + 0xC000) << 2)))\n\n/*\n *  DWORD-Length of Memory Blocks\n */\n#define PP32_DEBUG_REG_DWLEN            0x0030\n#define PPM_INT_REG_DWLEN               0x0010\n#define PP32_INTERNAL_RES_DWLEN         0x00C0\n#define CDM_CODE_MEMORYn_DWLEN(n)       0x1000\n#define PPE_REG_DWLEN                   0x1000\n#define CDM_DATA_MEMORY_DWLEN           CDM_CODE_MEMORYn_DWLEN(1)\n#define PPM_INT_UNIT_DWLEN              0x0100\n#define PPM_TIMER0_DWLEN                0x0100\n#define PPM_TASK_IND_REG_DWLEN          0x0100\n#define PPS_BRK_DWLEN                   0x0100\n#define PPM_TIMER1_DWLEN                0x0100\n#define SB_RAM0_DWLEN                   0x0800\n#define SB_RAM1_DWLEN                   0x0800\n#define SB_RAM2_DWLEN                   0x0800\n#define SB_RAM3_DWLEN                   0x0800\n#define SB_RAM4_DWLEN                   0x0C00\n#define QSB_CONF_REG_DWLEN              0x0100\n\n/*\n *  PP32 to FPI Address Mapping\n */\n#define SB_BUFFER(__sb_addr)            ((volatile unsigned int *)((((__sb_addr) >= 0x0000) && ((__sb_addr) <= 0x0FFF)) ? PPE_REG_ADDR((__sb_addr)):            \\\n                                                                   (((__sb_addr) >= 0x2000) && ((__sb_addr) <= 0x27FF)) ? SB_RAM0_ADDR((__sb_addr) - 0x2000) :  \\\n                                                                   (((__sb_addr) >= 0x2800) && ((__sb_addr) <= 0x2FFF)) ? SB_RAM1_ADDR((__sb_addr) - 0x2800) :  \\\n                                                                   (((__sb_addr) >= 0x3000) && ((__sb_addr) <= 0x37FF)) ? SB_RAM2_ADDR((__sb_addr) - 0x3000) :  \\\n                                                                   (((__sb_addr) >= 0x3800) && ((__sb_addr) <= 0x3FFF)) ? SB_RAM3_ADDR((__sb_addr) - 0x3800) :  \\\n                                                                   (((__sb_addr) >= 0x4000) && ((__sb_addr) <= 0x4BFF)) ? SB_RAM4_ADDR((__sb_addr) - 0x4000) :  \\\n                                                                0))\n\n/*\n *  PP32 Debug Control Register\n */\n#define NUM_OF_PP32                             1\n\n#define PP32_DBG_CTRL(n)                        PP32_DEBUG_REG_ADDR(n, 0x0000)\n\n#define DBG_CTRL_RESTART                        0\n#define DBG_CTRL_STOP                           1\n\n#define PP32_CTRL_CMD(n)                        PP32_DEBUG_REG_ADDR(n, 0x0B00)\n  #define PP32_CTRL_CMD_RESTART                 (1 << 0)\n  #define PP32_CTRL_CMD_STOP                    (1 << 1)\n  #define PP32_CTRL_CMD_STEP                    (1 << 2)\n  #define PP32_CTRL_CMD_BREAKOUT                (1 << 3)\n\n#define PP32_CTRL_OPT(n)                        PP32_DEBUG_REG_ADDR(n, 0x0C00)\n  #define PP32_CTRL_OPT_BREAKOUT_ON_STOP_ON     (3 << 0)\n  #define PP32_CTRL_OPT_BREAKOUT_ON_STOP_OFF    (2 << 0)\n  #define PP32_CTRL_OPT_BREAKOUT_ON_BREAKIN_ON  (3 << 2)\n  #define PP32_CTRL_OPT_BREAKOUT_ON_BREAKIN_OFF (2 << 2)\n  #define PP32_CTRL_OPT_STOP_ON_BREAKIN_ON      (3 << 4)\n  #define PP32_CTRL_OPT_STOP_ON_BREAKIN_OFF     (2 << 4)\n  #define PP32_CTRL_OPT_STOP_ON_BREAKPOINT_ON   (3 << 6)\n  #define PP32_CTRL_OPT_STOP_ON_BREAKPOINT_OFF  (2 << 6)\n  #define PP32_CTRL_OPT_BREAKOUT_ON_STOP(n)     (*PP32_CTRL_OPT(n) & (1 << 0))\n  #define PP32_CTRL_OPT_BREAKOUT_ON_BREAKIN(n)  (*PP32_CTRL_OPT(n) & (1 << 2))\n  #define PP32_CTRL_OPT_STOP_ON_BREAKIN(n)      (*PP32_CTRL_OPT(n) & (1 << 4))\n  #define PP32_CTRL_OPT_STOP_ON_BREAKPOINT(n)   (*PP32_CTRL_OPT(n) & (1 << 6))\n\n#define PP32_BRK_PC(n, i)                       PP32_DEBUG_REG_ADDR(n, 0x0900 + (i) * 2)\n#define PP32_BRK_PC_MASK(n, i)                  PP32_DEBUG_REG_ADDR(n, 0x0901 + (i) * 2)\n#define PP32_BRK_DATA_ADDR(n, i)                PP32_DEBUG_REG_ADDR(n, 0x0904 + (i) * 2)\n#define PP32_BRK_DATA_ADDR_MASK(n, i)           PP32_DEBUG_REG_ADDR(n, 0x0905 + (i) * 2)\n#define PP32_BRK_DATA_VALUE_RD(n, i)            PP32_DEBUG_REG_ADDR(n, 0x0908 + (i) * 2)\n#define PP32_BRK_DATA_VALUE_RD_MASK(n, i)       PP32_DEBUG_REG_ADDR(n, 0x0909 + (i) * 2)\n#define PP32_BRK_DATA_VALUE_WR(n, i)            PP32_DEBUG_REG_ADDR(n, 0x090C + (i) * 2)\n#define PP32_BRK_DATA_VALUE_WR_MASK(n, i)       PP32_DEBUG_REG_ADDR(n, 0x090D + (i) * 2)\n  #define PP32_BRK_CONTEXT_MASK(i)              (1 << (i))\n  #define PP32_BRK_CONTEXT_MASK_EN              (1 << 4)\n  #define PP32_BRK_COMPARE_GREATER_EQUAL        (1 << 5)    //  valid for break data value rd/wr only\n  #define PP32_BRK_COMPARE_LOWER_EQUAL          (1 << 6)\n  #define PP32_BRK_COMPARE_EN                   (1 << 7)\n\n#define PP32_BRK_TRIG(n)                        PP32_DEBUG_REG_ADDR(n, 0x0F00)\n  #define PP32_BRK_GRPi_PCn_ON(i, n)            ((3 << ((n) * 2)) << ((i) * 16))\n  #define PP32_BRK_GRPi_PCn_OFF(i, n)           ((2 << ((n) * 2)) << ((i) * 16))\n  #define PP32_BRK_GRPi_DATA_ADDRn_ON(i, n)     ((3 << ((n) * 2 + 4)) << ((i) * 16))\n  #define PP32_BRK_GRPi_DATA_ADDRn_OFF(i, n)    ((2 << ((n) * 2 + 4)) << ((i) * 16))\n  #define PP32_BRK_GRPi_DATA_VALUE_RDn_ON(i, n) ((3 << ((n) * 2 + 8)) << ((i) * 16))\n  #define PP32_BRK_GRPi_DATA_VALUE_RDn_OFF(i, n)((2 << ((n) * 2 + 8)) << ((i) * 16))\n  #define PP32_BRK_GRPi_DATA_VALUE_WRn_ON(i, n) ((3 << ((n) * 2 + 12)) << ((i) * 16))\n  #define PP32_BRK_GRPi_DATA_VALUE_WRn_OFF(i, n)((2 << ((n) * 2 + 12)) << ((i) * 16))\n  #define PP32_BRK_GRPi_PCn(k, i, n)            (*PP32_BRK_TRIG(k) & ((1 << ((n))) << ((i) * 8)))\n  #define PP32_BRK_GRPi_DATA_ADDRn(k, i, n)     (*PP32_BRK_TRIG(k) & ((1 << ((n) + 2)) << ((i) * 8)))\n  #define PP32_BRK_GRPi_DATA_VALUE_RDn(k, i, n) (*PP32_BRK_TRIG(k) & ((1 << ((n) + 4)) << ((i) * 8)))\n  #define PP32_BRK_GRPi_DATA_VALUE_WRn(k, i, n) (*PP32_BRK_TRIG(k) & ((1 << ((n) + 6)) << ((i) * 8)))\n\n#define PP32_CPU_STATUS(n)                      PP32_DEBUG_REG_ADDR(n, 0x0D00)\n#define PP32_HALT_STAT(n)                       PP32_CPU_STATUS(n)\n#define PP32_DBG_CUR_PC(n)                      PP32_CPU_STATUS(n)\n  #define PP32_CPU_USER_STOPPED(n)              (*PP32_CPU_STATUS(n) & (1 << 0))\n  #define PP32_CPU_USER_BREAKIN_RCV(n)          (*PP32_CPU_STATUS(n) & (1 << 1))\n  #define PP32_CPU_USER_BREAKPOINT_MET(n)       (*PP32_CPU_STATUS(n) & (1 << 2))\n  #define PP32_CPU_CUR_PC(n)                    (*PP32_CPU_STATUS(n) >> 16)\n\n#define PP32_BREAKPOINT_REASONS(n)              PP32_DEBUG_REG_ADDR(n, 0x0A00)\n  #define PP32_BRK_PC_MET(n, i)                 (*PP32_BREAKPOINT_REASONS(n) & (1 << (i)))\n  #define PP32_BRK_DATA_ADDR_MET(n, i)          (*PP32_BREAKPOINT_REASONS(n) & (1 << ((i) + 2)))\n  #define PP32_BRK_DATA_VALUE_RD_MET(n, i)      (*PP32_BREAKPOINT_REASONS(n) & (1 << ((i) + 4)))\n  #define PP32_BRK_DATA_VALUE_WR_MET(n, i)      (*PP32_BREAKPOINT_REASONS(n) & (1 << ((i) + 6)))\n  #define PP32_BRK_DATA_VALUE_RD_LO_EQ(n, i)    (*PP32_BREAKPOINT_REASONS(n) & (1 << ((i) * 2 + 8)))\n  #define PP32_BRK_DATA_VALUE_RD_GT_EQ(n, i)    (*PP32_BREAKPOINT_REASONS(n) & (1 << ((i) * 2 + 9)))\n  #define PP32_BRK_DATA_VALUE_WR_LO_EQ(n, i)    (*PP32_BREAKPOINT_REASONS(n) & (1 << ((i) * 2 + 12)))\n  #define PP32_BRK_DATA_VALUE_WR_GT_EQ(n, i)    (*PP32_BREAKPOINT_REASONS(n) & (1 << ((i) * 2 + 13)))\n  #define PP32_BRK_CUR_CONTEXT(n)               ((*PP32_BREAKPOINT_REASONS(n) >> 16) & 0x03)\n\n#define PP32_GP_REG_BASE(n)                     PP32_DEBUG_REG_ADDR(n, 0x0E00)\n#define PP32_GP_CONTEXTi_REGn(n, i, j)          PP32_DEBUG_REG_ADDR(n, 0x0E00 + (i) * 16 + (j))\n\n/*\n *  EMA Registers\n */\n#define EMA_CMDCFG                      PPE_REG_ADDR(0x0A00)\n#define EMA_DATACFG                     PPE_REG_ADDR(0x0A01)\n#define EMA_CMDCNT                      PPE_REG_ADDR(0x0A02)\n#define EMA_DATACNT                     PPE_REG_ADDR(0x0A03)\n#define EMA_ISR                         PPE_REG_ADDR(0x0A04)\n#define EMA_IER                         PPE_REG_ADDR(0x0A05)\n#define EMA_CFG                         PPE_REG_ADDR(0x0A06)\n#define EMA_SUBID                       PPE_REG_ADDR(0x0A07)\n\n#define EMA_ALIGNMENT                   4\n\n/*\n *  Mailbox IGU1 Interrupt\n */\n#define PPE_MAILBOX_IGU1_INT            INT_NUM_IM2_IRL24\n\n\n\n#endif  //  IFXMIPS_ATM_PPE_AR9_H\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-atm/src/ifxmips_atm_ppe_common.h",
    "content": "/******************************************************************************\n**\n** FILE NAME    : ifxmips_atm_ppe_common.h\n** PROJECT      : UEIP\n** MODULES     \t: ATM (ADSL)\n**\n** DATE         : 1 AUG 2005\n** AUTHOR       : Xu Liang\n** DESCRIPTION  : ATM Driver (PPE Registers)\n** COPYRIGHT    : \tCopyright (c) 2006\n**\t\t\tInfineon Technologies AG\n**\t\t\tAm Campeon 1-12, 85579 Neubiberg, Germany\n**\n**    This program is free software; you can redistribute it and/or modify\n**    it under the terms of the GNU General Public License as published by\n**    the Free Software Foundation; either version 2 of the License, or\n**    (at your option) any later version.\n**\n** HISTORY\n** $Date        $Author         $Comment\n**  4 AUG 2005  Xu Liang        Initiate Version\n** 23 OCT 2006  Xu Liang        Add GPL header.\n**  9 JAN 2007  Xu Liang        First version got from Anand (IC designer)\n*******************************************************************************/\n\n\n\n#ifndef IFXMIPS_ATM_PPE_COMMON_H\n#define IFXMIPS_ATM_PPE_COMMON_H\n\n\n\n#if defined(CONFIG_DANUBE)\n  #include \"ifxmips_atm_ppe_danube.h\"\n#elif defined(CONFIG_AMAZON_SE)\n  #include \"ifxmips_atm_ppe_amazon_se.h\"\n#elif defined(CONFIG_AR9)\n  #include \"ifxmips_atm_ppe_ar9.h\"\n#elif defined(CONFIG_VR9)\n  #include \"ifxmips_atm_ppe_vr9.h\"\n#else\n  #error Platform is not specified!\n#endif\n\n\n\n/*\n *  Code/Data Memory (CDM) Interface Configuration Register\n */\n#define CDM_CFG                         PPE_REG_ADDR(0x0100)\n\n#define CDM_CFG_RAM1                    GET_BITS(*CDM_CFG, 3, 2)\n#define CDM_CFG_RAM0                    (*CDM_CFG & (1 << 1))\n\n#define CDM_CFG_RAM1_SET(value)         SET_BITS(0, 3, 2, value)\n#define CDM_CFG_RAM0_SET(value)         ((value) ? (1 << 1) : 0)\n\n/*\n *  QSB Internal Cell Delay Variation Register\n */\n#define QSB_ICDV                        QSB_CONF_REG_ADDR(0x0007)\n\n#define QSB_ICDV_TAU                    GET_BITS(*QSB_ICDV, 5, 0)\n\n#define QSB_ICDV_TAU_SET(value)         SET_BITS(0, 5, 0, value)\n\n/*\n *  QSB Scheduler Burst Limit Register\n */\n#define QSB_SBL                         QSB_CONF_REG_ADDR(0x0009)\n\n#define QSB_SBL_SBL                     GET_BITS(*QSB_SBL, 3, 0)\n\n#define QSB_SBL_SBL_SET(value)          SET_BITS(0, 3, 0, value)\n\n/*\n *  QSB Configuration Register\n */\n#define QSB_CFG                         QSB_CONF_REG_ADDR(0x000A)\n\n#define QSB_CFG_TSTEPC                  GET_BITS(*QSB_CFG, 1, 0)\n\n#define QSB_CFG_TSTEPC_SET(value)       SET_BITS(0, 1, 0, value)\n\n/*\n *  QSB RAM Transfer Table Register\n */\n#define QSB_RTM                         QSB_CONF_REG_ADDR(0x000B)\n\n#define QSB_RTM_DM                      (*QSB_RTM)\n\n#define QSB_RTM_DM_SET(value)           ((value) & 0xFFFFFFFF)\n\n/*\n *  QSB RAM Transfer Data Register\n */\n#define QSB_RTD                         QSB_CONF_REG_ADDR(0x000C)\n\n#define QSB_RTD_TTV                     (*QSB_RTD)\n\n#define QSB_RTD_TTV_SET(value)          ((value) & 0xFFFFFFFF)\n\n/*\n *  QSB RAM Access Register\n */\n#define QSB_RAMAC                       QSB_CONF_REG_ADDR(0x000D)\n\n#define QSB_RAMAC_RW                    (*QSB_RAMAC & (1 << 31))\n#define QSB_RAMAC_TSEL                  GET_BITS(*QSB_RAMAC, 27, 24)\n#define QSB_RAMAC_LH                    (*QSB_RAMAC & (1 << 16))\n#define QSB_RAMAC_TESEL                 GET_BITS(*QSB_RAMAC, 9, 0)\n\n#define QSB_RAMAC_RW_SET(value)         ((value) ? (1 << 31) : 0)\n#define QSB_RAMAC_TSEL_SET(value)       SET_BITS(0, 27, 24, value)\n#define QSB_RAMAC_LH_SET(value)         ((value) ? (1 << 16) : 0)\n#define QSB_RAMAC_TESEL_SET(value)      SET_BITS(0, 9, 0, value)\n\n/*\n *  QSB Queue Scheduling and Shaping Definitions\n */\n#define QSB_WFQ_NONUBR_MAX              0x3f00\n#define QSB_WFQ_UBR_BYPASS              0x3fff\n#define QSB_TP_TS_MAX                   65472\n#define QSB_TAUS_MAX                    64512\n#define QSB_GCR_MIN                     18\n\n/*\n *  QSB Constant\n */\n#define QSB_RAMAC_RW_READ               0\n#define QSB_RAMAC_RW_WRITE              1\n\n#define QSB_RAMAC_TSEL_QPT              0x01\n#define QSB_RAMAC_TSEL_SCT              0x02\n#define QSB_RAMAC_TSEL_SPT              0x03\n#define QSB_RAMAC_TSEL_VBR              0x08\n\n#define QSB_RAMAC_LH_LOW                0\n#define QSB_RAMAC_LH_HIGH               1\n\n#define QSB_QPT_SET_MASK                0x0\n#define QSB_QVPT_SET_MASK               0x0\n#define QSB_SET_SCT_MASK                0x0\n#define QSB_SET_SPT_MASK                0x0\n#define QSB_SET_SPT_SBVALID_MASK        0x7FFFFFFF\n\n#define QSB_SPT_SBV_VALID               (1 << 31)\n#define QSB_SPT_PN_SET(value)           (((value) & 0x01) ? (1 << 16) : 0)\n#define QSB_SPT_INTRATE_SET(value)      SET_BITS(0, 13, 0, value)\n\n/*\n *  QSB Queue Parameter Table Entry and Queue VBR Parameter Table Entry\n */\n#if defined(__BIG_ENDIAN)\n    union qsb_queue_parameter_table {\n        struct {\n            unsigned int    res1    :1;\n            unsigned int    vbr     :1;\n            unsigned int    wfqf    :14;\n            unsigned int    tp      :16;\n        }               bit;\n        u32             dword;\n    };\n\n    union qsb_queue_vbr_parameter_table {\n        struct {\n            unsigned int    taus    :16;\n            unsigned int    ts      :16;\n        }               bit;\n        u32             dword;\n    };\n#else\n    union qsb_queue_parameter_table {\n        struct {\n            unsigned int    tp      :16;\n            unsigned int    wfqf    :14;\n            unsigned int    vbr     :1;\n            unsigned int    res1    :1;\n        }               bit;\n        u32             dword;\n    };\n\n    union qsb_queue_vbr_parameter_table {\n        struct {\n            unsigned int    ts      :16;\n            unsigned int    taus    :16;\n        }               bit;\n        u32             dword;\n    };\n#endif  //  defined(__BIG_ENDIAN)\n\n/*\n *  Mailbox IGU0 Registers\n */\n#define MBOX_IGU0_ISRS                  PPE_REG_ADDR(0x0200)\n#define MBOX_IGU0_ISRC                  PPE_REG_ADDR(0x0201)\n#define MBOX_IGU0_ISR                   PPE_REG_ADDR(0x0202)\n#define MBOX_IGU0_IER                   PPE_REG_ADDR(0x0203)\n\n#define MBOX_IGU0_ISRS_SET(n)           (1 << (n))\n#define MBOX_IGU0_ISRC_CLEAR(n)         (1 << (n))\n#define MBOX_IGU0_ISR_ISR(n)            (*MBOX_IGU0_ISR & (1 << (n)))\n#define MBOX_IGU0_IER_EN(n)             (*MBOX_IGU0_IER & (1 << (n)))\n#define MBOX_IGU0_IER_EN_SET(n)         (1 << (n))\n\n/*\n *  Mailbox IGU1 Registers\n */\n#define MBOX_IGU1_ISRS                  PPE_REG_ADDR(0x0204)\n#define MBOX_IGU1_ISRC                  PPE_REG_ADDR(0x0205)\n#define MBOX_IGU1_ISR                   PPE_REG_ADDR(0x0206)\n#define MBOX_IGU1_IER                   PPE_REG_ADDR(0x0207)\n\n#define MBOX_IGU1_ISRS_SET(n)           (1 << (n))\n#define MBOX_IGU1_ISRC_CLEAR(n)         (1 << (n))\n#define MBOX_IGU1_ISR_ISR(n)            (*MBOX_IGU1_ISR & (1 << (n)))\n#define MBOX_IGU1_IER_EN(n)             (*MBOX_IGU1_IER & (1 << (n)))\n#define MBOX_IGU1_IER_EN_SET(n)         (1 << (n))\n\n/*\n *  Mailbox IGU3 Registers\n */\n#define MBOX_IGU3_ISRS                  PPE_REG_ADDR(0x0214)\n#define MBOX_IGU3_ISRC                  PPE_REG_ADDR(0x0215)\n#define MBOX_IGU3_ISR                   PPE_REG_ADDR(0x0216)\n#define MBOX_IGU3_IER                   PPE_REG_ADDR(0x0217)\n\n#define MBOX_IGU3_ISRS_SET(n)           (1 << (n))\n#define MBOX_IGU3_ISRC_CLEAR(n)         (1 << (n))\n#define MBOX_IGU3_ISR_ISR(n)            (*MBOX_IGU3_ISR & (1 << (n)))\n#define MBOX_IGU3_IER_EN(n)             (*MBOX_IGU3_IER & (1 << (n)))\n#define MBOX_IGU3_IER_EN_SET(n)         (1 << (n))\n\n/*\n *  RTHA/TTHA Registers\n */\n#define RFBI_CFG                        PPE_REG_ADDR(0x0400)\n#define RBA_CFG0                        PPE_REG_ADDR(0x0404)\n#define RBA_CFG1                        PPE_REG_ADDR(0x0405)\n#define RCA_CFG0                        PPE_REG_ADDR(0x0408)\n#define RCA_CFG1                        PPE_REG_ADDR(0x0409)\n#define RDES_CFG0                       PPE_REG_ADDR(0x040C)\n#define RDES_CFG1                       PPE_REG_ADDR(0x040D)\n#define SFSM_STATE0                     PPE_REG_ADDR(0x0410)\n#define SFSM_STATE1                     PPE_REG_ADDR(0x0411)\n#define SFSM_DBA0                       PPE_REG_ADDR(0x0412)\n#define SFSM_DBA1                       PPE_REG_ADDR(0x0413)\n#define SFSM_CBA0                       PPE_REG_ADDR(0x0414)\n#define SFSM_CBA1                       PPE_REG_ADDR(0x0415)\n#define SFSM_CFG0                       PPE_REG_ADDR(0x0416)\n#define SFSM_CFG1                       PPE_REG_ADDR(0x0417)\n#define SFSM_PGCNT0                     PPE_REG_ADDR(0x041C)\n#define SFSM_PGCNT1                     PPE_REG_ADDR(0x041D)\n#define FFSM_DBA0                       PPE_REG_ADDR(0x0508)\n#define FFSM_DBA1                       PPE_REG_ADDR(0x0509)\n#define FFSM_CFG0                       PPE_REG_ADDR(0x050A)\n#define FFSM_CFG1                       PPE_REG_ADDR(0x050B)\n#define FFSM_IDLE_HEAD_BC0              PPE_REG_ADDR(0x050E)\n#define FFSM_IDLE_HEAD_BC1              PPE_REG_ADDR(0x050F)\n#define FFSM_PGCNT0                     PPE_REG_ADDR(0x0514)\n#define FFSM_PGCNT1                     PPE_REG_ADDR(0x0515)\n\n/*\n *  PPE TC Logic Registers (partial)\n */\n#define DREG_A_VERSION                  PPE_REG_ADDR(0x0D00)\n#define DREG_A_CFG                      PPE_REG_ADDR(0x0D01)\n#define DREG_AT_CTRL                    PPE_REG_ADDR(0x0D02)\n#define DREG_AT_CB_CFG0                 PPE_REG_ADDR(0x0D03)\n#define DREG_AT_CB_CFG1                 PPE_REG_ADDR(0x0D04)\n#define DREG_AR_CTRL                    PPE_REG_ADDR(0x0D08)\n#define DREG_AR_CB_CFG0                 PPE_REG_ADDR(0x0D09)\n#define DREG_AR_CB_CFG1                 PPE_REG_ADDR(0x0D0A)\n#define DREG_A_UTPCFG                   PPE_REG_ADDR(0x0D0E)\n#define DREG_A_STATUS                   PPE_REG_ADDR(0x0D0F)\n#define DREG_AT_CFG0                    PPE_REG_ADDR(0x0D20)\n#define DREG_AT_CFG1                    PPE_REG_ADDR(0x0D21)\n#define DREG_AT_FB_SIZE0                PPE_REG_ADDR(0x0D22)\n#define DREG_AT_FB_SIZE1                PPE_REG_ADDR(0x0D23)\n#define DREG_AT_CELL0                   PPE_REG_ADDR(0x0D24)\n#define DREG_AT_CELL1                   PPE_REG_ADDR(0x0D25)\n#define DREG_AT_IDLE_CNT0               PPE_REG_ADDR(0x0D26)\n#define DREG_AT_IDLE_CNT1               PPE_REG_ADDR(0x0D27)\n#define DREG_AT_IDLE0                   PPE_REG_ADDR(0x0D28)\n#define DREG_AT_IDLE1                   PPE_REG_ADDR(0x0D29)\n#define DREG_AR_CFG0                    PPE_REG_ADDR(0x0D60)\n#define DREG_AR_CFG1                    PPE_REG_ADDR(0x0D61)\n#define DREG_AR_CELL0                   PPE_REG_ADDR(0x0D68)\n#define DREG_AR_CELL1                   PPE_REG_ADDR(0x0D69)\n#define DREG_AR_IDLE_CNT0               PPE_REG_ADDR(0x0D6A)\n#define DREG_AR_IDLE_CNT1               PPE_REG_ADDR(0x0D6B)\n#define DREG_AR_AIIDLE_CNT0             PPE_REG_ADDR(0x0D6C)\n#define DREG_AR_AIIDLE_CNT1             PPE_REG_ADDR(0x0D6D)\n#define DREG_AR_BE_CNT0                 PPE_REG_ADDR(0x0D6E)\n#define DREG_AR_BE_CNT1                 PPE_REG_ADDR(0x0D6F)\n#define DREG_AR_HEC_CNT0                PPE_REG_ADDR(0x0D70)\n#define DREG_AR_HEC_CNT1                PPE_REG_ADDR(0x0D71)\n#define DREG_AR_IDLE0                   PPE_REG_ADDR(0x0D74)\n#define DREG_AR_IDLE1                   PPE_REG_ADDR(0x0D75)\n#define DREG_AR_CVN_CNT0                PPE_REG_ADDR(0x0DA4)\n#define DREG_AR_CVN_CNT1                PPE_REG_ADDR(0x0DA5)\n#define DREG_AR_CVNP_CNT0               PPE_REG_ADDR(0x0DA6)\n#define DREG_AR_CVNP_CNT1               PPE_REG_ADDR(0x0DA7)\n#define DREG_B0_LADR                    PPE_REG_ADDR(0x0DA8)\n#define DREG_B1_LADR                    PPE_REG_ADDR(0x0DA9)\n\n#define SFSM_DBA(i)                     ( (SFSM_dba * )   PPE_REG_ADDR(0x0412 + (i)))\n#define SFSM_CBA(i)                     ( (SFSM_cba * )   PPE_REG_ADDR(0x0414 + (i)))\n#define SFSM_CFG(i)                     ( (SFSM_cfg * )   PPE_REG_ADDR(0x0416 + (i)))\n#define SFSM_PGCNT(i)                   ( (SFSM_pgcnt * ) PPE_REG_ADDR(0x041C + (i)))\n\n#define FFSM_DBA(i)                     ( (FFSM_dba * )   PPE_REG_ADDR(0x0508 + (i)))\n#define FFSM_CFG(i)                     ( (FFSM_cfg * )   PPE_REG_ADDR(0x050A + (i)))\n#define FFSM_PGCNT(i)                   ( (FFSM_pgcnt * ) PPE_REG_ADDR(0x0514 + (i)))\n\ntypedef struct  {\n    unsigned int    res     : 19;\n    unsigned int    dbase   : 13;\n} SFSM_dba;\n\ntypedef struct  {\n    unsigned int    res     : 19;\n    unsigned int    cbase   : 13;\n} SFSM_cba;\n\ntypedef struct  {\n    unsigned int    res     : 15;\n    unsigned int    endian  : 1;\n    unsigned int    idlekeep: 1;\n    unsigned int    sen     : 1;\n    unsigned int    res1    : 8;\n    unsigned int    pnum    : 6;\n} SFSM_cfg;\n\ntypedef struct  {\n    unsigned int    res     : 17;\n    unsigned int    pptr    : 6;\n    unsigned int    dcmd    : 1;\n    unsigned int    res1    : 2;\n    unsigned int    upage   : 6;\n} SFSM_pgcnt;\n\ntypedef struct  {\n    unsigned int    res     : 19;\n    unsigned int    dbase   : 13;\n} FFSM_dba;\n\ntypedef struct  {\n    unsigned int    res     : 12;\n    unsigned int    rstptr  : 1;\n    unsigned int    clvpage : 1;\n    unsigned int    fidle   : 1;\n    unsigned int    endian  : 1;\n    unsigned int    res1    : 10;\n    unsigned int    pnum    : 6;\n} FFSM_cfg;\n\ntypedef struct  {\n    unsigned int    res     : 17;\n    unsigned int    ival    : 6;\n    unsigned int    icmd    : 1;\n    unsigned int    res1    : 2;\n    unsigned int    vpage   : 6;\n} FFSM_pgcnt;\n\n\n\n#endif  //  IFXMIPS_ATM_PPE_COMMON_H\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-atm/src/ifxmips_atm_ppe_danube.h",
    "content": "/******************************************************************************\n**\n** FILE NAME    : ifxmips_atm_ppe_danube.h\n** PROJECT      : UEIP\n** MODULES     \t: ATM (ADSL)\n**\n** DATE         : 1 AUG 2005\n** AUTHOR       : Xu Liang\n** DESCRIPTION  : ATM Driver (PPE Registers)\n** COPYRIGHT    : \tCopyright (c) 2006\n**\t\t\tInfineon Technologies AG\n**\t\t\tAm Campeon 1-12, 85579 Neubiberg, Germany\n**\n**    This program is free software; you can redistribute it and/or modify\n**    it under the terms of the GNU General Public License as published by\n**    the Free Software Foundation; either version 2 of the License, or\n**    (at your option) any later version.\n**\n** HISTORY\n** $Date        $Author         $Comment\n**  4 AUG 2005  Xu Liang        Initiate Version\n** 23 OCT 2006  Xu Liang        Add GPL header.\n**  9 JAN 2007  Xu Liang        First version got from Anand (IC designer)\n*******************************************************************************/\n\n\n\n#ifndef IFXMIPS_ATM_PPE_DANUBE_H\n#define IFXMIPS_ATM_PPE_DANUBE_H\n\n\n\n/*\n *  FPI Configuration Bus Register and Memory Address Mapping\n */\n#define IFX_PPE                      \t(KSEG1 | 0x1E180000)\n#define PP32_DEBUG_REG_ADDR(i, x)       ((volatile unsigned int*)(IFX_PPE + (((x) + 0x0000) << 2)))\n#define PPM_INT_REG_ADDR(i, x)          ((volatile unsigned int*)(IFX_PPE + (((x) + 0x0030) << 2)))\n#define PP32_INTERNAL_RES_ADDR(i, x)    ((volatile unsigned int*)(IFX_PPE + (((x) + 0x0040) << 2)))\n#define CDM_CODE_MEMORY(i, x)           ((volatile unsigned int*)(IFX_PPE + (((x) + 0x1000) << 2)))\n#define PPE_REG_ADDR(x)                 ((volatile unsigned int*)(IFX_PPE + (((x) + 0x4000) << 2)))\n#define CDM_DATA_MEMORY(i, x)           ((volatile unsigned int*)(IFX_PPE + (((x) + 0x5000) << 2)))\n#define PPM_INT_UNIT_ADDR(x)            ((volatile unsigned int*)(IFX_PPE + (((x) + 0x6000) << 2)))\n#define PPM_TIMER0_ADDR(x)              ((volatile unsigned int*)(IFX_PPE + (((x) + 0x6100) << 2)))\n#define PPM_TASK_IND_REG_ADDR(x)        ((volatile unsigned int*)(IFX_PPE + (((x) + 0x6200) << 2)))\n#define PPS_BRK_ADDR(x)                 ((volatile unsigned int*)(IFX_PPE + (((x) + 0x6300) << 2)))\n#define PPM_TIMER1_ADDR(x)              ((volatile unsigned int*)(IFX_PPE + (((x) + 0x6400) << 2)))\n#define SB_RAM0_ADDR(x)                 ((volatile unsigned int*)(IFX_PPE + (((x) + 0x8000) << 2)))\n#define SB_RAM1_ADDR(x)                 ((volatile unsigned int*)(IFX_PPE + (((x) + 0x8400) << 2)))\n#define SB_RAM2_ADDR(x)                 ((volatile unsigned int*)(IFX_PPE + (((x) + 0x8C00) << 2)))\n#define SB_RAM3_ADDR(x)                 ((volatile unsigned int*)(IFX_PPE + (((x) + 0x9600) << 2)))\n#define QSB_CONF_REG_ADDR(x)            ((volatile unsigned int*)(IFX_PPE + (((x) + 0xC000) << 2)))\n\n/*\n *  DWORD-Length of Memory Blocks\n */\n#define PP32_DEBUG_REG_DWLEN            0x0030\n#define PPM_INT_REG_DWLEN               0x0010\n#define PP32_INTERNAL_RES_DWLEN         0x00C0\n#define CDM_CODE_MEMORYn_DWLEN(n)       ((n) == 0 ? 0x1000 : 0x0800)\n#define PPE_REG_DWLEN                   0x1000\n#define CDM_DATA_MEMORY_DWLEN           CDM_CODE_MEMORYn_DWLEN(1)\n#define PPM_INT_UNIT_DWLEN              0x0100\n#define PPM_TIMER0_DWLEN                0x0100\n#define PPM_TASK_IND_REG_DWLEN          0x0100\n#define PPS_BRK_DWLEN                   0x0100\n#define PPM_TIMER1_DWLEN                0x0100\n#define SB_RAM0_DWLEN                   0x0400\n#define SB_RAM1_DWLEN                   0x0800\n#define SB_RAM2_DWLEN                   0x0A00\n#define SB_RAM3_DWLEN                   0x0400\n#define QSB_CONF_REG_DWLEN              0x0100\n\n/*\n *  PP32 to FPI Address Mapping\n */\n#define SB_BUFFER(__sb_addr)            ((volatile unsigned int *)((((__sb_addr) >= 0x2000) && ((__sb_addr) <= 0x23FF)) ? SB_RAM0_ADDR((__sb_addr) - 0x2000) :   \\\n                                                                   (((__sb_addr) >= 0x2400) && ((__sb_addr) <= 0x2BFF)) ? SB_RAM1_ADDR((__sb_addr) - 0x2400) :   \\\n                                                                   (((__sb_addr) >= 0x2C00) && ((__sb_addr) <= 0x35FF)) ? SB_RAM2_ADDR((__sb_addr) - 0x2C00) :   \\\n                                                                   (((__sb_addr) >= 0x3600) && ((__sb_addr) <= 0x39FF)) ? SB_RAM3_ADDR((__sb_addr) - 0x3600) :   \\\n                                                                0))\n\n/*\n *  PP32 Debug Control Register\n */\n#define PP32_DBG_CTRL                   PP32_DEBUG_REG_ADDR(0, 0x0000)\n\n#define DBG_CTRL_START_SET(value)       ((value) ? (1 << 0) : 0)\n#define DBG_CTRL_STOP_SET(value)        ((value) ? (1 << 1) : 0)\n#define DBG_CTRL_STEP_SET(value)        ((value) ? (1 << 2) : 0)\n\n#define PP32_HALT_STAT                  PP32_DEBUG_REG_ADDR(0, 0x0001)\n\n#define PP32_BRK_SRC                    PP32_DEBUG_REG_ADDR(0, 0x0002)\n\n#define PP32_DBG_PC_MIN(i)              PP32_DEBUG_REG_ADDR(0, 0x0010 + (i))\n#define PP32_DBG_PC_MAX(i)              PP32_DEBUG_REG_ADDR(0, 0x0014 + (i))\n#define PP32_DBG_DATA_MIN(i)            PP32_DEBUG_REG_ADDR(0, 0x0018 + (i))\n#define PP32_DBG_DATA_MAX(i)            PP32_DEBUG_REG_ADDR(0, 0x001A + (i))\n#define PP32_DBG_DATA_VAL(i)            PP32_DEBUG_REG_ADDR(0, 0x001C + (i))\n\n#define PP32_DBG_CUR_PC                 PP32_DEBUG_REG_ADDR(0, 0x0080)\n\n#define PP32_DBG_TASK_NO                PP32_DEBUG_REG_ADDR(0, 0x0081)\n\n#define PP32_DBG_REG_BASE(tsk, i)       PP32_DEBUG_REG_ADDR(0, 0x0100 + (tsk) * 16 + (i))\n\n/*\n *  EMA Registers\n */\n#define EMA_CMDCFG                      PPE_REG_ADDR(0x0A00)\n#define EMA_DATACFG                     PPE_REG_ADDR(0x0A01)\n#define EMA_CMDCNT                      PPE_REG_ADDR(0x0A02)\n#define EMA_DATACNT                     PPE_REG_ADDR(0x0A03)\n#define EMA_ISR                         PPE_REG_ADDR(0x0A04)\n#define EMA_IER                         PPE_REG_ADDR(0x0A05)\n#define EMA_CFG                         PPE_REG_ADDR(0x0A06)\n#define EMA_SUBID                       PPE_REG_ADDR(0x0A07)\n\n#define EMA_ALIGNMENT                   4\n\n/*\n *  Mailbox IGU1 Interrupt\n */\n#define PPE_MAILBOX_IGU1_INT            INT_NUM_IM2_IRL24\n\n\n\n#endif  //  IFXMIPS_ATM_PPE_DANUBE_H\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-atm/src/ifxmips_atm_ppe_vr9.h",
    "content": "/******************************************************************************\n**\n** FILE NAME    : ifxmips_atm_ppe_vr9.h\n** PROJECT      : UEIP\n** MODULES     \t: ATM (ADSL)\n**\n** DATE         : 1 AUG 2005\n** AUTHOR       : Xu Liang\n** DESCRIPTION  : ATM Driver (PPE Registers)\n** COPYRIGHT    : \tCopyright (c) 2006\n**\t\t\tInfineon Technologies AG\n**\t\t\tAm Campeon 1-12, 85579 Neubiberg, Germany\n**\n**    This program is free software; you can redistribute it and/or modify\n**    it under the terms of the GNU General Public License as published by\n**    the Free Software Foundation; either version 2 of the License, or\n**    (at your option) any later version.\n**\n** HISTORY\n** $Date        $Author         $Comment\n**  4 AUG 2005  Xu Liang        Initiate Version\n** 23 OCT 2006  Xu Liang        Add GPL header.\n**  9 JAN 2007  Xu Liang        First version got from Anand (IC designer)\n*******************************************************************************/\n\n\n\n#ifndef IFXMIPS_ATM_PPE_VR9_H\n#define IFXMIPS_ATM_PPE_VR9_H\n\n\n\n/*\n *  FPI Configuration Bus Register and Memory Address Mapping\n */\n#define IFX_PPE                         (KSEG1 | 0x1E200000)\n#define PP32_DEBUG_REG_ADDR(i, x)       ((volatile unsigned int*)(IFX_PPE + (((x) + 0x000000 + (i) * 0x00010000) << 2)))\n#define CDM_CODE_MEMORY(i, x)           ((volatile unsigned int*)(IFX_PPE + (((x) + 0x001000 + (i) * 0x00010000) << 2)))\n#define CDM_DATA_MEMORY(i, x)           ((volatile unsigned int*)(IFX_PPE + (((x) + 0x004000 + (i) * 0x00010000) << 2)))\n#define SB_RAM0_ADDR(x)                 ((volatile unsigned int*)(IFX_PPE + (((x) + 0x008000) << 2)))\n#define SB_RAM1_ADDR(x)                 ((volatile unsigned int*)(IFX_PPE + (((x) + 0x009000) << 2)))\n#define SB_RAM2_ADDR(x)                 ((volatile unsigned int*)(IFX_PPE + (((x) + 0x00A000) << 2)))\n#define SB_RAM3_ADDR(x)                 ((volatile unsigned int*)(IFX_PPE + (((x) + 0x00B000) << 2)))\n#define PPE_REG_ADDR(x)                 ((volatile unsigned int*)(IFX_PPE + (((x) + 0x00D000) << 2)))\n#define QSB_CONF_REG_ADDR(x)            ((volatile unsigned int*)(IFX_PPE + (((x) + 0x00E000) << 2)))\n#define SB_RAM6_ADDR(x)                 ((volatile unsigned int*)(IFX_PPE + (((x) + 0x018000) << 2)))\n\n/*\n *  DWORD-Length of Memory Blocks\n */\n#define PP32_DEBUG_REG_DWLEN            0x0030\n#define CDM_CODE_MEMORYn_DWLEN(n)       ((n) == 0 ? 0x1000 : 0x0800)\n#define CDM_DATA_MEMORY_DWLEN           CDM_CODE_MEMORYn_DWLEN(1)\n#define SB_RAM0_DWLEN                   0x1000\n#define SB_RAM1_DWLEN                   0x1000\n#define SB_RAM2_DWLEN                   0x1000\n#define SB_RAM3_DWLEN                   0x1000\n#define SB_RAM6_DWLEN                   0x8000\n#define QSB_CONF_REG_DWLEN              0x0100\n\n/*\n *  PP32 to FPI Address Mapping\n */\n#define SB_BUFFER(__sb_addr)            ((volatile unsigned int *)((((__sb_addr) >= 0x0000) && ((__sb_addr) <= 0x1FFF)) ? PPE_REG_ADDR((__sb_addr)) :           \\\n                                                                   (((__sb_addr) >= 0x2000) && ((__sb_addr) <= 0x2FFF)) ? SB_RAM0_ADDR((__sb_addr) - 0x2000) :  \\\n                                                                   (((__sb_addr) >= 0x3000) && ((__sb_addr) <= 0x3FFF)) ? SB_RAM1_ADDR((__sb_addr) - 0x3000) :  \\\n                                                                   (((__sb_addr) >= 0x4000) && ((__sb_addr) <= 0x4FFF)) ? SB_RAM2_ADDR((__sb_addr) - 0x4000) :  \\\n                                                                   (((__sb_addr) >= 0x5000) && ((__sb_addr) <= 0x5FFF)) ? SB_RAM3_ADDR((__sb_addr) - 0x5000) :  \\\n                                                                   (((__sb_addr) >= 0x7000) && ((__sb_addr) <= 0x7FFF)) ? PPE_REG_ADDR((__sb_addr) - 0x7000) :  \\\n                                                                   (((__sb_addr) >= 0x8000) && ((__sb_addr) <= 0xFFFF)) ? SB_RAM6_ADDR((__sb_addr) - 0x8000) :  \\\n                                                                0))\n\n/*\n *  PP32 Debug Control Register\n */\n#define NUM_OF_PP32                             2\n\n#define PP32_FREEZE                             PPE_REG_ADDR(0x0000)\n#define PP32_SRST                               PPE_REG_ADDR(0x0020)\n\n#define PP32_DBG_CTRL(n)                        PP32_DEBUG_REG_ADDR(n, 0x0000)\n\n#define DBG_CTRL_RESTART                        0\n#define DBG_CTRL_STOP                           1\n\n#define PP32_CTRL_CMD(n)                        PP32_DEBUG_REG_ADDR(n, 0x0B00)\n  #define PP32_CTRL_CMD_RESTART                 (1 << 0)\n  #define PP32_CTRL_CMD_STOP                    (1 << 1)\n  #define PP32_CTRL_CMD_STEP                    (1 << 2)\n  #define PP32_CTRL_CMD_BREAKOUT                (1 << 3)\n\n#define PP32_CTRL_OPT(n)                        PP32_DEBUG_REG_ADDR(n, 0x0C00)\n  #define PP32_CTRL_OPT_BREAKOUT_ON_STOP_ON     (3 << 0)\n  #define PP32_CTRL_OPT_BREAKOUT_ON_STOP_OFF    (2 << 0)\n  #define PP32_CTRL_OPT_BREAKOUT_ON_BREAKIN_ON  (3 << 2)\n  #define PP32_CTRL_OPT_BREAKOUT_ON_BREAKIN_OFF (2 << 2)\n  #define PP32_CTRL_OPT_STOP_ON_BREAKIN_ON      (3 << 4)\n  #define PP32_CTRL_OPT_STOP_ON_BREAKIN_OFF     (2 << 4)\n  #define PP32_CTRL_OPT_STOP_ON_BREAKPOINT_ON   (3 << 6)\n  #define PP32_CTRL_OPT_STOP_ON_BREAKPOINT_OFF  (2 << 6)\n  #define PP32_CTRL_OPT_BREAKOUT_ON_STOP(n)     (*PP32_CTRL_OPT(n) & (1 << 0))\n  #define PP32_CTRL_OPT_BREAKOUT_ON_BREAKIN(n)  (*PP32_CTRL_OPT(n) & (1 << 2))\n  #define PP32_CTRL_OPT_STOP_ON_BREAKIN(n)      (*PP32_CTRL_OPT(n) & (1 << 4))\n  #define PP32_CTRL_OPT_STOP_ON_BREAKPOINT(n)   (*PP32_CTRL_OPT(n) & (1 << 6))\n\n#define PP32_BRK_PC(n, i)                       PP32_DEBUG_REG_ADDR(n, 0x0900 + (i) * 2)\n#define PP32_BRK_PC_MASK(n, i)                  PP32_DEBUG_REG_ADDR(n, 0x0901 + (i) * 2)\n#define PP32_BRK_DATA_ADDR(n, i)                PP32_DEBUG_REG_ADDR(n, 0x0904 + (i) * 2)\n#define PP32_BRK_DATA_ADDR_MASK(n, i)           PP32_DEBUG_REG_ADDR(n, 0x0905 + (i) * 2)\n#define PP32_BRK_DATA_VALUE_RD(n, i)            PP32_DEBUG_REG_ADDR(n, 0x0908 + (i) * 2)\n#define PP32_BRK_DATA_VALUE_RD_MASK(n, i)       PP32_DEBUG_REG_ADDR(n, 0x0909 + (i) * 2)\n#define PP32_BRK_DATA_VALUE_WR(n, i)            PP32_DEBUG_REG_ADDR(n, 0x090C + (i) * 2)\n#define PP32_BRK_DATA_VALUE_WR_MASK(n, i)       PP32_DEBUG_REG_ADDR(n, 0x090D + (i) * 2)\n  #define PP32_BRK_CONTEXT_MASK(i)              (1 << (i))\n  #define PP32_BRK_CONTEXT_MASK_EN              (1 << 4)\n  #define PP32_BRK_COMPARE_GREATER_EQUAL        (1 << 5)    //  valid for break data value rd/wr only\n  #define PP32_BRK_COMPARE_LOWER_EQUAL          (1 << 6)\n  #define PP32_BRK_COMPARE_EN                   (1 << 7)\n\n#define PP32_BRK_TRIG(n)                        PP32_DEBUG_REG_ADDR(n, 0x0F00)\n  #define PP32_BRK_GRPi_PCn_ON(i, n)            ((3 << ((n) * 2)) << ((i) * 16))\n  #define PP32_BRK_GRPi_PCn_OFF(i, n)           ((2 << ((n) * 2)) << ((i) * 16))\n  #define PP32_BRK_GRPi_DATA_ADDRn_ON(i, n)     ((3 << ((n) * 2 + 4)) << ((i) * 16))\n  #define PP32_BRK_GRPi_DATA_ADDRn_OFF(i, n)    ((2 << ((n) * 2 + 4)) << ((i) * 16))\n  #define PP32_BRK_GRPi_DATA_VALUE_RDn_ON(i, n) ((3 << ((n) * 2 + 8)) << ((i) * 16))\n  #define PP32_BRK_GRPi_DATA_VALUE_RDn_OFF(i, n)((2 << ((n) * 2 + 8)) << ((i) * 16))\n  #define PP32_BRK_GRPi_DATA_VALUE_WRn_ON(i, n) ((3 << ((n) * 2 + 12)) << ((i) * 16))\n  #define PP32_BRK_GRPi_DATA_VALUE_WRn_OFF(i, n)((2 << ((n) * 2 + 12)) << ((i) * 16))\n  #define PP32_BRK_GRPi_PCn(k, i, n)            (*PP32_BRK_TRIG(k) & ((1 << ((n))) << ((i) * 8)))\n  #define PP32_BRK_GRPi_DATA_ADDRn(k, i, n)     (*PP32_BRK_TRIG(k) & ((1 << ((n) + 2)) << ((i) * 8)))\n  #define PP32_BRK_GRPi_DATA_VALUE_RDn(k, i, n) (*PP32_BRK_TRIG(k) & ((1 << ((n) + 4)) << ((i) * 8)))\n  #define PP32_BRK_GRPi_DATA_VALUE_WRn(k, i, n) (*PP32_BRK_TRIG(k) & ((1 << ((n) + 6)) << ((i) * 8)))\n\n#define PP32_CPU_STATUS(n)                      PP32_DEBUG_REG_ADDR(n, 0x0D00)\n#define PP32_HALT_STAT(n)                       PP32_CPU_STATUS(n)\n#define PP32_DBG_CUR_PC(n)                      PP32_CPU_STATUS(n)\n  #define PP32_CPU_USER_STOPPED(n)              (*PP32_CPU_STATUS(n) & (1 << 0))\n  #define PP32_CPU_USER_BREAKIN_RCV(n)          (*PP32_CPU_STATUS(n) & (1 << 1))\n  #define PP32_CPU_USER_BREAKPOINT_MET(n)       (*PP32_CPU_STATUS(n) & (1 << 2))\n  #define PP32_CPU_CUR_PC(n)                    (*PP32_CPU_STATUS(n) >> 16)\n\n#define PP32_BREAKPOINT_REASONS(n)              PP32_DEBUG_REG_ADDR(n, 0x0A00)\n  #define PP32_BRK_PC_MET(n, i)                 (*PP32_BREAKPOINT_REASONS(n) & (1 << (i)))\n  #define PP32_BRK_DATA_ADDR_MET(n, i)          (*PP32_BREAKPOINT_REASONS(n) & (1 << ((i) + 2)))\n  #define PP32_BRK_DATA_VALUE_RD_MET(n, i)      (*PP32_BREAKPOINT_REASONS(n) & (1 << ((i) + 4)))\n  #define PP32_BRK_DATA_VALUE_WR_MET(n, i)      (*PP32_BREAKPOINT_REASONS(n) & (1 << ((i) + 6)))\n  #define PP32_BRK_DATA_VALUE_RD_LO_EQ(n, i)    (*PP32_BREAKPOINT_REASONS(n) & (1 << ((i) * 2 + 8)))\n  #define PP32_BRK_DATA_VALUE_RD_GT_EQ(n, i)    (*PP32_BREAKPOINT_REASONS(n) & (1 << ((i) * 2 + 9)))\n  #define PP32_BRK_DATA_VALUE_WR_LO_EQ(n, i)    (*PP32_BREAKPOINT_REASONS(n) & (1 << ((i) * 2 + 12)))\n  #define PP32_BRK_DATA_VALUE_WR_GT_EQ(n, i)    (*PP32_BREAKPOINT_REASONS(n) & (1 << ((i) * 2 + 13)))\n  #define PP32_BRK_CUR_CONTEXT(n)               ((*PP32_BREAKPOINT_REASONS(n) >> 16) & 0x03)\n\n#define PP32_GP_REG_BASE(n)                     PP32_DEBUG_REG_ADDR(n, 0x0E00)\n#define PP32_GP_CONTEXTi_REGn(n, i, j)          PP32_DEBUG_REG_ADDR(n, 0x0E00 + (i) * 16 + (j))\n\n/*\n *  PDMA/EMA Registers\n */\n#define PDMA_CFG                        PPE_REG_ADDR(0x0A00)\n#define PDMA_RX_CMDCNT                  PPE_REG_ADDR(0x0A01)\n#define PDMA_TX_CMDCNT                  PPE_REG_ADDR(0x0A02)\n#define PDMA_RX_FWDATACNT               PPE_REG_ADDR(0x0A03)\n#define PDMA_TX_FWDATACNT               PPE_REG_ADDR(0x0A04)\n#define PDMA_RX_CTX_CFG                 PPE_REG_ADDR(0x0A05)\n#define PDMA_TX_CTX_CFG                 PPE_REG_ADDR(0x0A06)\n#define PDMA_RX_MAX_LEN_REG             PPE_REG_ADDR(0x0A07)\n#define PDMA_RX_DELAY_CFG               PPE_REG_ADDR(0x0A08)\n#define PDMA_INT_FIFO_RD                PPE_REG_ADDR(0x0A09)\n#define PDMA_ISR                        PPE_REG_ADDR(0x0A0A)\n#define PDMA_IER                        PPE_REG_ADDR(0x0A0B)\n#define PDMA_SUBID                      PPE_REG_ADDR(0x0A0C)\n#define PDMA_BAR0                       PPE_REG_ADDR(0x0A0D)\n#define PDMA_BAR1                       PPE_REG_ADDR(0x0A0E)\n\n#define SAR_PDMA_RX_CMDBUF_CFG          PPE_REG_ADDR(0x0F00)\n#define SAR_PDMA_TX_CMDBUF_CFG          PPE_REG_ADDR(0x0F01)\n#define SAR_PDMA_RX_FW_CMDBUF_CFG       PPE_REG_ADDR(0x0F02)\n#define SAR_PDMA_TX_FW_CMDBUF_CFG       PPE_REG_ADDR(0x0F03)\n#define SAR_PDMA_RX_CMDBUF_STATUS       PPE_REG_ADDR(0x0F04)\n#define SAR_PDMA_TX_CMDBUF_STATUS       PPE_REG_ADDR(0x0F05)\n\n#define PDMA_ALIGNMENT                  4\n#define EMA_ALIGNMENT                   PDMA_ALIGNMENT\n\n/*\n *  Mailbox IGU1 Interrupt\n */\n#define PPE_MAILBOX_IGU1_INT            INT_NUM_IM2_IRL24\n\n\n\n#endif  //  IFXMIPS_ATM_PPE_VR9_H\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-atm/src/ifxmips_atm_vr9.c",
    "content": "/******************************************************************************\n**\n** FILE NAME    : ifxmips_atm_vr9.c\n** PROJECT      : UEIP\n** MODULES      : ATM\n**\n** DATE         : 7 Jul 2009\n** AUTHOR       : Xu Liang\n** DESCRIPTION  : ATM driver common source file (core functions)\n** COPYRIGHT    :       Copyright (c) 2006\n**                      Infineon Technologies AG\n**                      Am Campeon 1-12, 85579 Neubiberg, Germany\n**\n**    This program is free software; you can redistribute it and/or modify\n**    it under the terms of the GNU General Public License as published by\n**    the Free Software Foundation; either version 2 of the License, or\n**    (at your option) any later version.\n**\n** HISTORY\n** $Date        $Author         $Comment\n** 07 JUL 2009  Xu Liang        Init Version\n*******************************************************************************/\n\n\n\n/*\n * ####################################\n *              Head File\n * ####################################\n */\n\n/*\n *  Common Head File\n */\n#include <linux/kernel.h>\n#include <linux/module.h>\n#include <linux/version.h>\n#include <linux/types.h>\n#include <linux/errno.h>\n#include <linux/proc_fs.h>\n#include <linux/init.h>\n#include <linux/ioctl.h>\n#include <linux/platform_device.h>\n#include <linux/reset.h>\n#include <asm/delay.h>\n\n#include \"ifxmips_atm_core.h\"\n#include \"ifxmips_atm_fw_vr9.h\"\n\n#ifdef CONFIG_VR9\n\n#include <lantiq_soc.h>\n\n#define IFX_PMU_MODULE_PPE_SLL01  BIT(19)\n#define IFX_PMU_MODULE_PPE_TC     BIT(21)\n#define IFX_PMU_MODULE_PPE_EMA    BIT(22)\n#define IFX_PMU_MODULE_PPE_QSB    BIT(18)\n#define IFX_PMU_MODULE_AHBS       BIT(13)\n#define IFX_PMU_MODULE_DSL_DFE    BIT(9)\n\nstatic inline void vr9_reset_ppe(struct platform_device *pdev)\n{\n\tstruct device *dev = &pdev->dev;\n\tstruct reset_control *dsp;\n\tstruct reset_control *dfe;\n\tstruct reset_control *tc;\n\n\tdsp = devm_reset_control_get(dev, \"dsp\");\n\tif (IS_ERR(dsp)) {\n\t\tif (PTR_ERR(dsp) != -EPROBE_DEFER)\n\t\t\tdev_err(dev, \"Failed to lookup dsp reset\\n\");\n// \t\treturn PTR_ERR(dsp);\n\t}\n\n\tdfe = devm_reset_control_get(dev, \"dfe\");\n\tif (IS_ERR(dfe)) {\n\t\tif (PTR_ERR(dfe) != -EPROBE_DEFER)\n\t\t\tdev_err(dev, \"Failed to lookup dfe reset\\n\");\n// \t\treturn PTR_ERR(dfe);\n\t}\n\n\ttc = devm_reset_control_get(dev, \"tc\");\n\tif (IS_ERR(tc)) {\n\t\tif (PTR_ERR(tc) != -EPROBE_DEFER)\n\t\t\tdev_err(dev, \"Failed to lookup tc reset\\n\");\n// \t\treturn PTR_ERR(tc);\n\t}\n\n\treset_control_assert(dsp);\n\tudelay(1000);\n\treset_control_assert(dfe);\n\tudelay(1000);\n\treset_control_assert(tc);\n\tudelay(1000);\n\t*PP32_SRST &= ~0x000303CF;\n\tudelay(1000);\n\t*PP32_SRST |= 0x000303CF;\n\tudelay(1000);\n}\n\nstatic inline int vr9_pp32_download_code(int pp32, u32 *code_src, unsigned int code_dword_len, u32 *data_src, unsigned int data_dword_len)\n{\n\tunsigned int clr, set;\n\tvolatile u32 *dest;\n\n\tif ( code_src == 0 || ((unsigned long)code_src & 0x03) != 0\n\t\t\t|| data_src == 0 || ((unsigned long)data_src & 0x03) != 0 )\n\t\treturn -1;\n\n\tclr = pp32 ? 0xF0 : 0x0F;\n\tif ( code_dword_len <= CDM_CODE_MEMORYn_DWLEN(0) )\n\t\tset = pp32 ? (3 << 6): (2 << 2);\n\telse\n\t\tset = 0x00;\n\tIFX_REG_W32_MASK(clr, set, CDM_CFG);\n\n\tdest = CDM_CODE_MEMORY(pp32, 0);\n\twhile ( code_dword_len-- > 0 )\n\t\tIFX_REG_W32(*code_src++, dest++);\n\n\tdest = CDM_DATA_MEMORY(pp32, 0);\n\twhile ( data_dword_len-- > 0 )\n\t\tIFX_REG_W32(*data_src++, dest++);\n\n\treturn 0;\n}\n\nstatic void vr9_fw_ver(unsigned int *major, unsigned int *minor)\n{\n\n    *major = FW_VER_ID->major;\n    *minor = FW_VER_ID->minor;\n}\n\nstatic void vr9_init(struct platform_device *pdev)\n{\n\tvolatile u32 *p;\n\tunsigned int i;\n\n\t/* setup pmu */\n\tltq_pmu_enable(IFX_PMU_MODULE_PPE_SLL01 |\n\t\tIFX_PMU_MODULE_PPE_TC |\n\t\tIFX_PMU_MODULE_PPE_EMA |\n\t\tIFX_PMU_MODULE_PPE_QSB |\n\t\tIFX_PMU_MODULE_AHBS |\n\t\tIFX_PMU_MODULE_DSL_DFE);\n\n\tvr9_reset_ppe(pdev);\n\n\t/* pdma init */\n\tIFX_REG_W32(0x08,       PDMA_CFG);\n\tIFX_REG_W32(0x00203580, SAR_PDMA_RX_CMDBUF_CFG);\n\tIFX_REG_W32(0x004035A0, SAR_PDMA_RX_FW_CMDBUF_CFG);\n\n\t/* mailbox init */\n\tIFX_REG_W32(0xFFFFFFFF, MBOX_IGU1_ISRC);\n\tIFX_REG_W32(0x00000000, MBOX_IGU1_IER);\n\tIFX_REG_W32(0xFFFFFFFF, MBOX_IGU3_ISRC);\n\tIFX_REG_W32(0x00000000, MBOX_IGU3_IER);\n\n\t/* tc init - clear sync state */\n\t*SFSM_STATE0 = 0;\n\t*SFSM_STATE1 = 0;\n\n\t/* init shared buffer */\n\tp = SB_RAM0_ADDR(0);\n\tfor ( i = 0; i < SB_RAM0_DWLEN + SB_RAM1_DWLEN + SB_RAM2_DWLEN + SB_RAM3_DWLEN; i++ )\n\t\tIFX_REG_W32(0, p++);\n\n\tp = SB_RAM6_ADDR(0);\n\tfor ( i = 0; i < SB_RAM6_DWLEN; i++ )\n\t\tIFX_REG_W32(0, p++);\n}\n\nstatic void vr9_shutdown(void)\n{\n}\n\nstatic int vr9_start(int pp32)\n{\n\tunsigned int mask = 1 << (pp32 << 4);\n\tint ret;\n\n\t/*  download firmware   */\n\tret = vr9_pp32_download_code(pp32,\n\t\tvr9_fw_bin, sizeof(vr9_fw_bin) / sizeof(*vr9_fw_bin),\n\t\tvr9_fw_data, sizeof(vr9_fw_data) / sizeof(*vr9_fw_data));\n\tif ( ret != 0 )\n\t\treturn ret;\n\n\t/*  run PP32    */\n\tIFX_REG_W32_MASK(mask, 0, PP32_FREEZE);\n\n\t/*  idle for a while to let PP32 init itself    */\n\tudelay(10);\n\n\treturn 0;\n}\n\nstatic void vr9_stop(int pp32)\n{\n\tunsigned int mask = 1 << (pp32 << 4);\n\n\tIFX_REG_W32_MASK(0, mask, PP32_FREEZE);\n}\n\nstruct ltq_atm_ops vr9_ops = {\n\t.init = vr9_init,\n\t.shutdown = vr9_shutdown,\n\t.start = vr9_start,\n\t.stop = vr9_stop,\n\t.fw_ver = vr9_fw_ver,\n};\n\n#endif\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-atm/src/ltq_atm.c",
    "content": "/******************************************************************************\n**\n** FILE NAME    : ifxmips_atm_core.c\n** PROJECT      : UEIP\n** MODULES      : ATM\n**\n** DATE         : 7 Jul 2009\n** AUTHOR       : Xu Liang\n** DESCRIPTION  : ATM driver common source file (core functions)\n** COPYRIGHT    :       Copyright (c) 2006\n**                      Infineon Technologies AG\n**                      Am Campeon 1-12, 85579 Neubiberg, Germany\n**\n**    This program is free software; you can redistribute it and/or modify\n**    it under the terms of the GNU General Public License as published by\n**    the Free Software Foundation; either version 2 of the License, or\n**    (at your option) any later version.\n**\n** HISTORY\n** $Date        $Author         $Comment\n** 07 JUL 2009  Xu Liang        Init Version\n**\n** Copyright 2017 Alexander Couzens <lynxis@fe80.eu>\n*******************************************************************************/\n\n#define IFX_ATM_VER_MAJOR               1\n#define IFX_ATM_VER_MID                 0\n#define IFX_ATM_VER_MINOR               26\n\n#include <linux/kernel.h>\n#include <linux/module.h>\n#include <linux/version.h>\n#include <linux/types.h>\n#include <linux/errno.h>\n#include <linux/proc_fs.h>\n#include <linux/init.h>\n#include <linux/ioctl.h>\n#include <linux/atmdev.h>\n#include <linux/platform_device.h>\n#include <linux/of_device.h>\n#include <linux/atm.h>\n#include <linux/clk.h>\n#include <linux/interrupt.h>\n#include <linux/version.h>\n#ifdef CONFIG_XFRM\n  #include <net/xfrm.h>\n#endif\n\n#include <lantiq_soc.h>\n\n#include \"ifxmips_atm_core.h\"\n\n#define MODULE_PARM_ARRAY(a, b)   module_param_array(a, int, NULL, 0)\n#define MODULE_PARM(a, b)         module_param(a, int, 0)\n\n/*!\n  \\brief QSB cell delay variation due to concurrency\n */\nstatic int qsb_tau   = 1;                       /*  QSB cell delay variation due to concurrency     */\n/*!\n  \\brief QSB scheduler burst length\n */\nstatic int qsb_srvm  = 0x0F;                    /*  QSB scheduler burst length                      */\n/*!\n  \\brief QSB time step, all legal values are 1, 2, 4\n */\nstatic int qsb_tstep = 4 ;                      /*  QSB time step, all legal values are 1, 2, 4     */\n\n/*!\n  \\brief Write descriptor delay\n */\nstatic int write_descriptor_delay  = 0x20;      /*  Write descriptor delay                          */\n\n/*!\n  \\brief AAL5 padding byte ('~')\n */\nstatic int aal5_fill_pattern       = 0x007E;    /*  AAL5 padding byte ('~')                         */\n/*!\n  \\brief Max frame size for RX\n */\nstatic int aal5r_max_packet_size   = 0x0700;    /*  Max frame size for RX                           */\n/*!\n  \\brief Min frame size for RX\n */\nstatic int aal5r_min_packet_size   = 0x0000;    /*  Min frame size for RX                           */\n/*!\n  \\brief Max frame size for TX\n */\nstatic int aal5s_max_packet_size   = 0x0700;    /*  Max frame size for TX                           */\n/*!\n  \\brief Min frame size for TX\n */\nstatic int aal5s_min_packet_size   = 0x0000;    /*  Min frame size for TX                           */\n/*!\n  \\brief Drop error packet in RX path\n */\nstatic int aal5r_drop_error_packet = 1;         /*  Drop error packet in RX path                    */\n\n/*!\n  \\brief Number of descriptors per DMA RX channel\n */\nstatic int dma_rx_descriptor_length = 128;      /*  Number of descriptors per DMA RX channel        */\n/*!\n  \\brief Number of descriptors per DMA TX channel\n */\nstatic int dma_tx_descriptor_length = 64;       /*  Number of descriptors per DMA TX channel        */\n/*!\n  \\brief PPE core clock cycles between descriptor write and effectiveness in external RAM\n */\nstatic int dma_rx_clp1_descriptor_threshold = 38;\n/*@}*/\n\nMODULE_PARM(qsb_tau, \"i\");\nMODULE_PARM_DESC(qsb_tau, \"Cell delay variation. Value must be > 0\");\nMODULE_PARM(qsb_srvm, \"i\");\nMODULE_PARM_DESC(qsb_srvm, \"Maximum burst size\");\nMODULE_PARM(qsb_tstep, \"i\");\nMODULE_PARM_DESC(qsb_tstep, \"n*32 cycles per sbs cycles n=1,2,4\");\n\nMODULE_PARM(write_descriptor_delay, \"i\");\nMODULE_PARM_DESC(write_descriptor_delay, \"PPE core clock cycles between descriptor write and effectiveness in external RAM\");\n\nMODULE_PARM(aal5_fill_pattern, \"i\");\nMODULE_PARM_DESC(aal5_fill_pattern, \"Filling pattern (PAD) for AAL5 frames\");\nMODULE_PARM(aal5r_max_packet_size, \"i\");\nMODULE_PARM_DESC(aal5r_max_packet_size, \"Max packet size in byte for downstream AAL5 frames\");\nMODULE_PARM(aal5r_min_packet_size, \"i\");\nMODULE_PARM_DESC(aal5r_min_packet_size, \"Min packet size in byte for downstream AAL5 frames\");\nMODULE_PARM(aal5s_max_packet_size, \"i\");\nMODULE_PARM_DESC(aal5s_max_packet_size, \"Max packet size in byte for upstream AAL5 frames\");\nMODULE_PARM(aal5s_min_packet_size, \"i\");\nMODULE_PARM_DESC(aal5s_min_packet_size, \"Min packet size in byte for upstream AAL5 frames\");\nMODULE_PARM(aal5r_drop_error_packet, \"i\");\nMODULE_PARM_DESC(aal5r_drop_error_packet, \"Non-zero value to drop error packet for downstream\");\n\nMODULE_PARM(dma_rx_descriptor_length, \"i\");\nMODULE_PARM_DESC(dma_rx_descriptor_length, \"Number of descriptor assigned to DMA RX channel (>16)\");\nMODULE_PARM(dma_tx_descriptor_length, \"i\");\nMODULE_PARM_DESC(dma_tx_descriptor_length, \"Number of descriptor assigned to DMA TX channel (>16)\");\nMODULE_PARM(dma_rx_clp1_descriptor_threshold, \"i\");\nMODULE_PARM_DESC(dma_rx_clp1_descriptor_threshold, \"Descriptor threshold for cells with cell loss priority 1\");\n\n\n\n/*\n * ####################################\n *              Definition\n * ####################################\n */\n\n#ifdef CONFIG_AMAZON_SE\n  #define ENABLE_LESS_CACHE_INV                 1\n  #define LESS_CACHE_INV_LEN                    96\n#endif\n\n#define DUMP_SKB_LEN                            ~0\n\n\n\n/*\n * ####################################\n *             Declaration\n * ####################################\n */\n\n/*\n *  Network Operations\n */\nstatic int ppe_ioctl(struct atm_dev *, unsigned int, void *);\nstatic int ppe_open(struct atm_vcc *);\nstatic void ppe_close(struct atm_vcc *);\nstatic int ppe_send(struct atm_vcc *, struct sk_buff *);\nstatic int ppe_send_oam(struct atm_vcc *, void *, int);\nstatic int ppe_change_qos(struct atm_vcc *, struct atm_qos *, int);\n\n/*\n *  ADSL LED\n */\nstatic inline void adsl_led_flash(void);\n\n/*\n *  64-bit operation used by MIB calculation\n */\nstatic inline void u64_add_u32(ppe_u64_t, unsigned int, ppe_u64_t *);\n\n/*\n *  buffer manage functions\n */\nstatic inline struct sk_buff* alloc_skb_rx(void);\nstatic inline struct sk_buff* alloc_skb_tx(unsigned int);\nstatic inline void atm_free_tx_skb_vcc(struct sk_buff *, struct atm_vcc *);\nstatic inline struct sk_buff *get_skb_rx_pointer(unsigned int);\nstatic inline int get_tx_desc(unsigned int);\n\n/*\n *  mailbox handler and signal function\n */\nstatic inline void mailbox_oam_rx_handler(void);\nstatic inline void mailbox_aal_rx_handler(void);\nstatic irqreturn_t mailbox_irq_handler(int, void *);\nstatic inline void mailbox_signal(unsigned int, int);\nstatic void do_ppe_tasklet(unsigned long);\n#if LINUX_VERSION_CODE < KERNEL_VERSION(5,9,0)\nDECLARE_TASKLET(g_dma_tasklet, do_ppe_tasklet, 0);\n#else\nDECLARE_TASKLET_OLD(g_dma_tasklet, do_ppe_tasklet);\n#endif\n\n/*\n *  QSB & HTU setting functions\n */\nstatic void set_qsb(struct atm_vcc *, struct atm_qos *, unsigned int);\nstatic void qsb_global_set(void);\nstatic inline void set_htu_entry(unsigned int, unsigned int, unsigned int, int, int);\nstatic inline void clear_htu_entry(unsigned int);\nstatic void validate_oam_htu_entry(void);\nstatic void invalidate_oam_htu_entry(void);\n\n/*\n *  look up for connection ID\n */\nstatic inline int find_vpi(unsigned int);\nstatic inline int find_vpivci(unsigned int, unsigned int);\nstatic inline int find_vcc(struct atm_vcc *);\n\nstatic inline int ifx_atm_version(const struct ltq_atm_ops *ops, char *);\n\n/*\n *  Init & clean-up functions\n */\nstatic inline void check_parameters(void);\nstatic inline int init_priv_data(void);\nstatic inline void clear_priv_data(void);\nstatic inline void init_rx_tables(void);\nstatic inline void init_tx_tables(void);\n\n/*\n *  Exteranl Function\n */\n#if defined(CONFIG_IFX_OAM) || defined(CONFIG_IFX_OAM_MODULE)\nextern void ifx_push_oam(unsigned char *);\n#else\nstatic inline void ifx_push_oam(unsigned char *dummy) {}\n#endif\n\n#if defined(CONFIG_IFXMIPS_DSL_CPE_MEI) || defined(CONFIG_IFXMIPS_DSL_CPE_MEI_MODULE)\nextern int ifx_mei_atm_showtime_check(int *is_showtime, struct port_cell_info *port_cell, void **xdata_addr);\nextern int (*ifx_mei_atm_showtime_enter)(struct port_cell_info *, void *);\n\nextern int (*ifx_mei_atm_showtime_exit)(void);\nextern int ifx_mei_atm_led_blink(void);\n#else\nstatic inline int ifx_mei_atm_led_blink(void) { return 0; }\nstatic inline int ifx_mei_atm_showtime_check(int *is_showtime, struct port_cell_info *port_cell, void **xdata_addr)\n{\n\tif ( is_showtime != NULL )\n\t\t*is_showtime = 0;\n\treturn 0;\n}\nint (*ifx_mei_atm_showtime_enter)(struct port_cell_info *, void *) = NULL;\nEXPORT_SYMBOL(ifx_mei_atm_showtime_enter);\n\nint (*ifx_mei_atm_showtime_exit)(void) = NULL;\nEXPORT_SYMBOL(ifx_mei_atm_showtime_exit);\n\n#endif\n\nstatic struct atm_priv_data g_atm_priv_data;\n\nstatic struct atmdev_ops g_ifx_atm_ops = {\n\t.open = ppe_open,\n\t.close = ppe_close,\n\t.ioctl = ppe_ioctl,\n\t.send = ppe_send,\n\t.send_oam = ppe_send_oam,\n\t.change_qos = ppe_change_qos,\n\t.owner = THIS_MODULE,\n};\n\nstatic int g_showtime = 0;\nstatic void *g_xdata_addr = NULL;\n\nstatic int ppe_ioctl(struct atm_dev *dev, unsigned int cmd, void *arg)\n{\n\tint ret = 0;\n\tatm_cell_ifEntry_t mib_cell;\n\tatm_aal5_ifEntry_t mib_aal5;\n\tatm_aal5_vcc_x_t mib_vcc;\n\tunsigned int value;\n\tint conn;\n\n\tif ( _IOC_TYPE(cmd) != PPE_ATM_IOC_MAGIC\n\t\t\t|| _IOC_NR(cmd) >= PPE_ATM_IOC_MAXNR )\n\t\treturn -ENOTTY;\n\n\tif ( _IOC_DIR(cmd) & _IOC_READ )\n\t\tret = !access_ok(arg, _IOC_SIZE(cmd));\n\telse if ( _IOC_DIR(cmd) & _IOC_WRITE )\n\t\tret = !access_ok(arg, _IOC_SIZE(cmd));\n\tif ( ret )\n\t\treturn -EFAULT;\n\n\tswitch (cmd) {\n\tcase PPE_ATM_MIB_CELL:  /*  cell level  MIB */\n\t\t/*  These MIB should be read at ARC side, now put zero only.    */\n\t\tmib_cell.ifHCInOctets_h = 0;\n\t\tmib_cell.ifHCInOctets_l = 0;\n\t\tmib_cell.ifHCOutOctets_h = 0;\n\t\tmib_cell.ifHCOutOctets_l = 0;\n\t\tmib_cell.ifInErrors = 0;\n\t\tmib_cell.ifInUnknownProtos = WAN_MIB_TABLE->wrx_drophtu_cell;\n\t\tmib_cell.ifOutErrors = 0;\n\n\t\tret = sizeof(mib_cell) - copy_to_user(arg, &mib_cell, sizeof(mib_cell));\n\t\tbreak;\n\n\tcase PPE_ATM_MIB_AAL5:  /*  AAL5 MIB    */\n\t\tvalue = WAN_MIB_TABLE->wrx_total_byte;\n\t\tu64_add_u32(g_atm_priv_data.wrx_total_byte, value - g_atm_priv_data.prev_wrx_total_byte, &g_atm_priv_data.wrx_total_byte);\n\t\tg_atm_priv_data.prev_wrx_total_byte = value;\n\t\tmib_aal5.ifHCInOctets_h = g_atm_priv_data.wrx_total_byte.h;\n\t\tmib_aal5.ifHCInOctets_l = g_atm_priv_data.wrx_total_byte.l;\n\n\t\tvalue = WAN_MIB_TABLE->wtx_total_byte;\n\t\tu64_add_u32(g_atm_priv_data.wtx_total_byte, value - g_atm_priv_data.prev_wtx_total_byte, &g_atm_priv_data.wtx_total_byte);\n\t\tg_atm_priv_data.prev_wtx_total_byte = value;\n\t\tmib_aal5.ifHCOutOctets_h = g_atm_priv_data.wtx_total_byte.h;\n\t\tmib_aal5.ifHCOutOctets_l = g_atm_priv_data.wtx_total_byte.l;\n\n\t\tmib_aal5.ifInUcastPkts  = g_atm_priv_data.wrx_pdu;\n\t\tmib_aal5.ifOutUcastPkts = WAN_MIB_TABLE->wtx_total_pdu;\n\t\tmib_aal5.ifInErrors     = WAN_MIB_TABLE->wrx_err_pdu;\n\t\tmib_aal5.ifInDiscards   = WAN_MIB_TABLE->wrx_dropdes_pdu + g_atm_priv_data.wrx_drop_pdu;\n\t\tmib_aal5.ifOutErros     = g_atm_priv_data.wtx_err_pdu;\n\t\tmib_aal5.ifOutDiscards  = g_atm_priv_data.wtx_drop_pdu;\n\n\t\tret = sizeof(mib_aal5) - copy_to_user(arg, &mib_aal5, sizeof(mib_aal5));\n\t\tbreak;\n\n\tcase PPE_ATM_MIB_VCC:   /*  VCC related MIB */\n\t\tcopy_from_user(&mib_vcc, arg, sizeof(mib_vcc));\n\t\tconn = find_vpivci(mib_vcc.vpi, mib_vcc.vci);\n\t\tif (conn >= 0) {\n\t\t\tmib_vcc.mib_vcc.aal5VccCrcErrors     = g_atm_priv_data.conn[conn].aal5_vcc_crc_err;\n\t\t\tmib_vcc.mib_vcc.aal5VccOverSizedSDUs = g_atm_priv_data.conn[conn].aal5_vcc_oversize_sdu;\n\t\t\tmib_vcc.mib_vcc.aal5VccSarTimeOuts   = 0;   /*  no timer support    */\n\t\t\tret = sizeof(mib_vcc) - copy_to_user(arg, &mib_vcc, sizeof(mib_vcc));\n\t\t} else\n\t\t\tret = -EINVAL;\n\t\tbreak;\n\n\tdefault:\n\t\tret = -ENOIOCTLCMD;\n\t}\n\n\treturn ret;\n}\n\nstatic int ppe_open(struct atm_vcc *vcc)\n{\n\tint ret;\n\tshort vpi = vcc->vpi;\n\tint   vci = vcc->vci;\n\tstruct port *port = &g_atm_priv_data.port[(int)vcc->dev->dev_data];\n\tint conn;\n\tint f_enable_irq = 0;\n\n\tif ( vcc->qos.aal != ATM_AAL5 && vcc->qos.aal != ATM_AAL0 )\n\t\treturn -EPROTONOSUPPORT;\n\n#if !defined(DISABLE_QOS_WORKAROUND) || !DISABLE_QOS_WORKAROUND\n\t/*  check bandwidth */\n\tif ( (vcc->qos.txtp.traffic_class == ATM_CBR && vcc->qos.txtp.max_pcr > (port->tx_max_cell_rate - port->tx_current_cell_rate))\n\t\t|| (vcc->qos.txtp.traffic_class == ATM_VBR_RT && vcc->qos.txtp.max_pcr > (port->tx_max_cell_rate - port->tx_current_cell_rate))\n#if 0\n\t\t|| (vcc->qos.txtp.traffic_class == ATM_VBR_NRT && vcc->qos.txtp.scr > (port->tx_max_cell_rate - port->tx_current_cell_rate))\n#endif\n\t\t|| (vcc->qos.txtp.traffic_class == ATM_UBR_PLUS && vcc->qos.txtp.min_pcr > (port->tx_max_cell_rate - port->tx_current_cell_rate)) )\n\t{\n\t\tret = -EINVAL;\n\t\tgoto PPE_OPEN_EXIT;\n\t}\n#endif\n\n\t/*  check existing vpi,vci  */\n\tconn = find_vpivci(vpi, vci);\n\tif ( conn >= 0 ) {\n\t\tret = -EADDRINUSE;\n\t\tgoto PPE_OPEN_EXIT;\n\t}\n\n\t/*  check whether it need to enable irq */\n\tif ( g_atm_priv_data.conn_table == 0 )\n\t\tf_enable_irq = 1;\n\n\t/*  allocate connection */\n\tfor ( conn = 0; conn < MAX_PVC_NUMBER; conn++ ) {\n\t\tif ( test_and_set_bit(conn, &g_atm_priv_data.conn_table) == 0 ) {\n\t\t\tg_atm_priv_data.conn[conn].vcc = vcc;\n\t\t\tbreak;\n\t\t}\n\t}\n\tif ( conn == MAX_PVC_NUMBER ) {\n\t\tret = -EINVAL;\n\t\tgoto PPE_OPEN_EXIT;\n\t}\n\n\t/*  reserve bandwidth   */\n\tswitch ( vcc->qos.txtp.traffic_class ) {\n\tcase ATM_CBR:\n\tcase ATM_VBR_RT:\n\t\tport->tx_current_cell_rate += vcc->qos.txtp.max_pcr;\n\t\tbreak;\n\tcase ATM_VBR_NRT:\n#if 0\n\t\tport->tx_current_cell_rate += vcc->qos.txtp.scr;\n#endif\n\t\tbreak;\n\tcase ATM_UBR_PLUS:\n\t\tport->tx_current_cell_rate += vcc->qos.txtp.min_pcr;\n\t\tbreak;\n\t}\n\n\t/*  set qsb */\n\tset_qsb(vcc, &vcc->qos, conn);\n\n\t/*  update atm_vcc structure    */\n\tvcc->itf = (int)vcc->dev->dev_data;\n\tvcc->vpi = vpi;\n\tvcc->vci = vci;\n\tset_bit(ATM_VF_READY, &vcc->flags);\n\n\t/*  enable irq  */\n\tif ( f_enable_irq ) {\n\t\t*MBOX_IGU1_ISRC = (1 << RX_DMA_CH_AAL) | (1 << RX_DMA_CH_OAM);\n\t\t*MBOX_IGU1_IER  = (1 << RX_DMA_CH_AAL) | (1 << RX_DMA_CH_OAM);\n\n\t\tenable_irq(PPE_MAILBOX_IGU1_INT);\n\t}\n\n\t/*  set port    */\n\tWTX_QUEUE_CONFIG(conn + FIRST_QSB_QID)->sbid = (int)vcc->dev->dev_data;\n\n\t/*  set htu entry   */\n\tset_htu_entry(vpi, vci, conn, vcc->qos.aal == ATM_AAL5 ? 1 : 0, 0);\n\n\t*MBOX_IGU1_ISRC |= (1 << (conn + FIRST_QSB_QID + 16));\n\t*MBOX_IGU1_IER |= (1 << (conn + FIRST_QSB_QID + 16));\n\n\tret = 0;\n\nPPE_OPEN_EXIT:\n\treturn ret;\n}\n\nstatic void ppe_close(struct atm_vcc *vcc)\n{\n\tint conn;\n\tstruct port *port;\n\tstruct connection *connection;\n\tif ( vcc == NULL )\n\t\treturn;\n\n\t/*  get connection id   */\n\tconn = find_vcc(vcc);\n\tif ( conn < 0 ) {\n\t\tpr_err(\"can't find vcc\\n\");\n\t\tgoto PPE_CLOSE_EXIT;\n\t}\n\tconnection = &g_atm_priv_data.conn[conn];\n\tport = &g_atm_priv_data.port[connection->port];\n\n\t/*  clear htu   */\n\tclear_htu_entry(conn);\n\n\t/*  release connection  */\n\tconnection->vcc = NULL;\n\tconnection->aal5_vcc_crc_err = 0;\n\tconnection->aal5_vcc_oversize_sdu = 0;\n\tclear_bit(conn, &g_atm_priv_data.conn_table);\n\n\t/*  disable irq */\n\tif ( g_atm_priv_data.conn_table == 0 )\n\t\tdisable_irq(PPE_MAILBOX_IGU1_INT);\n\n\t/*  release bandwidth   */\n\tswitch ( vcc->qos.txtp.traffic_class )\n\t{\n\tcase ATM_CBR:\n\tcase ATM_VBR_RT:\n\t\tport->tx_current_cell_rate -= vcc->qos.txtp.max_pcr;\n\t\tbreak;\n\tcase ATM_VBR_NRT:\n#if 0\n\t\tport->tx_current_cell_rate -= vcc->qos.txtp.scr;\n#endif\n\t\tbreak;\n\tcase ATM_UBR_PLUS:\n\t\tport->tx_current_cell_rate -= vcc->qos.txtp.min_pcr;\n\t\tbreak;\n\t}\n\n\t/* wait for incoming packets to be processed by upper layers */\n\ttasklet_unlock_wait(&g_dma_tasklet);\n\nPPE_CLOSE_EXIT:\n\treturn;\n}\n\nstatic int ppe_send(struct atm_vcc *vcc, struct sk_buff *skb)\n{\n\tint ret;\n\tint conn;\n\tint desc_base;\n\tint byteoff;\n\tint required;\n\t/* the len of the data without offset and header */\n\tint datalen;\n\tunsigned long flags;\n\tstruct tx_descriptor reg_desc = {0};\n\tstruct tx_inband_header *header;\n\n\tif ( vcc == NULL || skb == NULL )\n\t\treturn -EINVAL;\n\n\n\tconn = find_vcc(vcc);\n\tif ( conn < 0 ) {\n\t\tret = -EINVAL;\n\t\tgoto FIND_VCC_FAIL;\n\t}\n\n\tif ( !g_showtime ) {\n\t\tpr_debug(\"not in showtime\\n\");\n\t\tret = -EIO;\n\t\tgoto PPE_SEND_FAIL;\n\t}\n\n\tbyteoff = (unsigned int)skb->data & (DATA_BUFFER_ALIGNMENT - 1);\n\trequired = sizeof(*header) + byteoff;\n\tif (!skb_clone_writable(skb, required)) {\n\t\tint expand_by = 0;\n\t\tint ret;\n\n\t\tif (skb_headroom(skb) < required)\n\t\t\texpand_by = required - skb_headroom(skb);\n\n\t\tret = pskb_expand_head(skb, expand_by, 0, GFP_ATOMIC);\n\t\tif (ret) {\n\t\t\tprintk(\"pskb_expand_head failed.\\n\");\n\t\t\tatm_free_tx_skb_vcc(skb, vcc);\n\t\t\treturn ret;\n\t\t}\n\t}\n\n\tdatalen = skb->len;\n\theader = (void *)skb_push(skb, byteoff + TX_INBAND_HEADER_LENGTH);\n\n\n\tif ( vcc->qos.aal == ATM_AAL5 ) {\n\t\t/*  setup inband trailer    */\n\t\theader->uu   = 0;\n\t\theader->cpi  = 0;\n\t\theader->pad  = aal5_fill_pattern;\n\t\theader->res1 = 0;\n\n\t\t/*  setup cell header   */\n\t\theader->clp  = (vcc->atm_options & ATM_ATMOPT_CLP) ? 1 : 0;\n\t\theader->pti  = ATM_PTI_US0;\n\t\theader->vci  = vcc->vci;\n\t\theader->vpi  = vcc->vpi;\n\t\theader->gfc  = 0;\n\n\t\t/*  setup descriptor    */\n\t\treg_desc.dataptr = (unsigned int)skb->data >> 2;\n\t\treg_desc.datalen = datalen;\n\t\treg_desc.byteoff = byteoff;\n\t\treg_desc.iscell  = 0;\n\t} else {\n\t\treg_desc.dataptr = (unsigned int)skb->data >> 2;\n\t\treg_desc.datalen = skb->len;\n\t\treg_desc.byteoff = byteoff;\n\t\treg_desc.iscell  = 1;\n\t}\n\n\treg_desc.own = 1;\n\treg_desc.c = 1;\n\treg_desc.sop = reg_desc.eop = 1;\n\n\tspin_lock_irqsave(&g_atm_priv_data.conn[conn].lock, flags);\n\tdesc_base = get_tx_desc(conn);\n\tif ( desc_base < 0 ) {\n\t\tspin_unlock_irqrestore(&g_atm_priv_data.conn[conn].lock, flags);\n\t\tpr_debug(\"ALLOC_TX_CONNECTION_FAIL\\n\");\n\t\tret = -EIO;\n\t\tgoto PPE_SEND_FAIL;\n\t}\n\t/*  update descriptor send pointer  */\n\tif ( g_atm_priv_data.conn[conn].tx_skb[desc_base] != NULL )\n\t\tdev_kfree_skb_any(g_atm_priv_data.conn[conn].tx_skb[desc_base]);\n\tg_atm_priv_data.conn[conn].tx_skb[desc_base] = skb;\n\n\tspin_unlock_irqrestore(&g_atm_priv_data.conn[conn].lock, flags);\n\n\tif ( vcc->stats )\n\t\tatomic_inc(&vcc->stats->tx);\n\tif ( vcc->qos.aal == ATM_AAL5 )\n\t\tg_atm_priv_data.wtx_pdu++;\n\t/*  write discriptor to memory and write back cache */\n\tg_atm_priv_data.conn[conn].tx_desc[desc_base] = reg_desc;\n\tdma_cache_wback((unsigned long)skb->data, skb->len);\n\n\tmailbox_signal(conn, 1);\n\n\tadsl_led_flash();\n\n\treturn 0;\n\nFIND_VCC_FAIL:\n\tpr_err(\"FIND_VCC_FAIL\\n\");\n\tg_atm_priv_data.wtx_err_pdu++;\n\tdev_kfree_skb_any(skb);\n\treturn ret;\n\nPPE_SEND_FAIL:\n\tif ( vcc->qos.aal == ATM_AAL5 )\n\t\tg_atm_priv_data.wtx_drop_pdu++;\n\tif ( vcc->stats )\n\t\tatomic_inc(&vcc->stats->tx_err);\n\tdev_kfree_skb_any(skb);\n\treturn ret;\n}\n\n/* operation and maintainance */\nstatic int ppe_send_oam(struct atm_vcc *vcc, void *cell, int flags)\n{\n\tint conn;\n\tstruct uni_cell_header *uni_cell_header = (struct uni_cell_header *)cell;\n\tint desc_base;\n\tstruct sk_buff *skb;\n\tstruct tx_descriptor reg_desc = {0};\n\n\tif ( ((uni_cell_header->pti == ATM_PTI_SEGF5 || uni_cell_header->pti == ATM_PTI_E2EF5)\n\t\t\t&& find_vpivci(uni_cell_header->vpi, uni_cell_header->vci) < 0)\n\t\t\t|| ((uni_cell_header->vci == 0x03 || uni_cell_header->vci == 0x04)\n\t\t\t&& find_vpi(uni_cell_header->vpi) < 0) )\n\t{\n\t\tg_atm_priv_data.wtx_err_oam++;\n\t\treturn -EINVAL;\n\t}\n\n\tif ( !g_showtime ) {\n\t\tpr_err(\"not in showtime\\n\");\n\t\tg_atm_priv_data.wtx_drop_oam++;\n\t\treturn -EIO;\n\t}\n\n\tconn = find_vcc(vcc);\n\tif ( conn < 0 ) {\n\t\tpr_err(\"FIND_VCC_FAIL\\n\");\n\t\tg_atm_priv_data.wtx_drop_oam++;\n\t\treturn -EINVAL;\n\t}\n\n\tskb = alloc_skb_tx(CELL_SIZE);\n\tif ( skb == NULL ) {\n\t\tpr_err(\"ALLOC_SKB_TX_FAIL\\n\");\n\t\tg_atm_priv_data.wtx_drop_oam++;\n\t\treturn -ENOMEM;\n\t}\n\tskb_put(skb, CELL_SIZE);\n\tmemcpy(skb->data, cell, CELL_SIZE);\n\n\treg_desc.dataptr = (unsigned int)skb->data >> 2;\n\treg_desc.datalen = CELL_SIZE;\n\treg_desc.byteoff = 0;\n\treg_desc.iscell  = 1;\n\n\treg_desc.own = 1;\n\treg_desc.c = 1;\n\treg_desc.sop = reg_desc.eop = 1;\n\n\tdesc_base = get_tx_desc(conn);\n\tif ( desc_base < 0 ) {\n\t\tdev_kfree_skb_any(skb);\n\t\tpr_err(\"ALLOC_TX_CONNECTION_FAIL\\n\");\n\t\tg_atm_priv_data.wtx_drop_oam++;\n\t\treturn -EIO;\n\t}\n\n\tif ( vcc->stats )\n\t\tatomic_inc(&vcc->stats->tx);\n\n\t/*  update descriptor send pointer  */\n\tif ( g_atm_priv_data.conn[conn].tx_skb[desc_base] != NULL )\n\t\tdev_kfree_skb_any(g_atm_priv_data.conn[conn].tx_skb[desc_base]);\n\tg_atm_priv_data.conn[conn].tx_skb[desc_base] = skb;\n\n\t/*  write discriptor to memory and write back cache */\n\tg_atm_priv_data.conn[conn].tx_desc[desc_base] = reg_desc;\n\tdma_cache_wback((unsigned long)skb->data, CELL_SIZE);\n\n\tmailbox_signal(conn, 1);\n\n\tg_atm_priv_data.wtx_oam++;\n\tadsl_led_flash();\n\n\treturn 0;\n}\n\nstatic int ppe_change_qos(struct atm_vcc *vcc, struct atm_qos *qos, int flags)\n{\n\tint conn;\n\n\tif ( vcc == NULL || qos == NULL )\n\t\treturn -EINVAL;\n\n\tconn = find_vcc(vcc);\n\tif ( conn < 0 )\n\t\treturn -EINVAL;\n\n\tset_qsb(vcc, qos, conn);\n\n\treturn 0;\n}\n\nstatic inline void adsl_led_flash(void)\n{\n\tifx_mei_atm_led_blink();\n}\n\n/*\n*  Description:\n*    Add a 32-bit value to 64-bit value, and put result in a 64-bit variable.\n*  Input:\n*    opt1 --- ppe_u64_t, first operand, a 64-bit unsigned integer value\n*    opt2 --- unsigned int, second operand, a 32-bit unsigned integer value\n*    ret  --- ppe_u64_t, pointer to a variable to hold result\n*  Output:\n*    none\n*/\nstatic inline void u64_add_u32(ppe_u64_t opt1, unsigned int opt2, ppe_u64_t *ret)\n{\n\tret->l = opt1.l + opt2;\n\tif ( ret->l < opt1.l || ret->l < opt2 )\n\t\tret->h++;\n}\n\nstatic inline struct sk_buff* alloc_skb_rx(void)\n{\n\tstruct sk_buff *skb;\n\n\tskb = dev_alloc_skb(RX_DMA_CH_AAL_BUF_SIZE + DATA_BUFFER_ALIGNMENT);\n\tif ( skb != NULL ) {\n\t\t/*  must be burst length alignment  */\n\t\tif ( ((unsigned int)skb->data & (DATA_BUFFER_ALIGNMENT - 1)) != 0 )\n\t\t\tskb_reserve(skb, ~((unsigned int)skb->data + (DATA_BUFFER_ALIGNMENT - 1)) & (DATA_BUFFER_ALIGNMENT - 1));\n\t\t/*  pub skb in reserved area \"skb->data - 4\"    */\n\t\t*((struct sk_buff **)skb->data - 1) = skb;\n\t\t/*  write back and invalidate cache */\n\t\tdma_cache_wback_inv((unsigned long)skb->data - sizeof(skb), sizeof(skb));\n\t\t/*  invalidate cache    */\n#if defined(ENABLE_LESS_CACHE_INV) && ENABLE_LESS_CACHE_INV\n\t\tdma_cache_inv((unsigned long)skb->data, LESS_CACHE_INV_LEN);\n#else\n\t\tdma_cache_inv((unsigned long)skb->data, RX_DMA_CH_AAL_BUF_SIZE);\n#endif\n\t}\n\treturn skb;\n}\n\nstatic inline struct sk_buff* alloc_skb_tx(unsigned int size)\n{\n\tstruct sk_buff *skb;\n\n\t/*  allocate memory including header and padding    */\n\tsize += TX_INBAND_HEADER_LENGTH + MAX_TX_PACKET_ALIGN_BYTES + MAX_TX_PACKET_PADDING_BYTES;\n\tsize &= ~(DATA_BUFFER_ALIGNMENT - 1);\n\tskb = dev_alloc_skb(size + DATA_BUFFER_ALIGNMENT);\n\t/*  must be burst length alignment  */\n\tif ( skb != NULL )\n\t\tskb_reserve(skb, (~((unsigned int)skb->data + (DATA_BUFFER_ALIGNMENT - 1)) & (DATA_BUFFER_ALIGNMENT - 1)) + TX_INBAND_HEADER_LENGTH);\n\treturn skb;\n}\n\nstatic inline void atm_free_tx_skb_vcc(struct sk_buff *skb, struct atm_vcc *vcc)\n{\n\tif ( vcc->pop != NULL )\n\t\tvcc->pop(vcc, skb);\n\telse\n\t\tdev_kfree_skb_any(skb);\n}\n\nstatic inline struct sk_buff *get_skb_rx_pointer(unsigned int dataptr)\n{\n\tunsigned int skb_dataptr;\n\tstruct sk_buff *skb;\n\n\tskb_dataptr = ((dataptr - 1) << 2) | KSEG1;\n\tskb = *(struct sk_buff **)skb_dataptr;\n\n\tASSERT((unsigned int)skb >= KSEG0, \"invalid skb - skb = %#08x, dataptr = %#08x\", (unsigned int)skb, dataptr);\n\tASSERT(((unsigned int)skb->data | KSEG1) == ((dataptr << 2) | KSEG1), \"invalid skb - skb = %#08x, skb->data = %#08x, dataptr = %#08x\", (unsigned int)skb, (unsigned int)skb->data, dataptr);\n\n\treturn skb;\n}\n\nstatic inline int get_tx_desc(unsigned int conn)\n{\n\tint desc_base = -1;\n\tstruct connection *p_conn = &g_atm_priv_data.conn[conn];\n\n\tif ( p_conn->tx_desc[p_conn->tx_desc_pos].own == 0 ) {\n\t\tdesc_base = p_conn->tx_desc_pos;\n\t\tif ( ++(p_conn->tx_desc_pos) == dma_tx_descriptor_length )\n\t\t\tp_conn->tx_desc_pos = 0;\n\t}\n\n\treturn desc_base;\n}\n\nstatic void free_tx_ring(unsigned int queue)\n{\n\tunsigned long flags;\n\tint i;\n\tstruct connection *conn = &g_atm_priv_data.conn[queue];\n\tstruct sk_buff *skb;\n\n\tif (!conn)\n\t\treturn;\n\n\tspin_lock_irqsave(&conn->lock, flags);\n\n\tfor (i = 0; i < dma_tx_descriptor_length; i++) {\n\t\tif (conn->tx_desc[i].own == 0 && conn->tx_skb[i] != NULL) {\n\t\t\tskb = conn->tx_skb[i];\n\t\t\tconn->tx_skb[i] = NULL;\n\t\t\tatm_free_tx_skb_vcc(skb, ATM_SKB(skb)->vcc);\n\t\t}\n\t}\n\tspin_unlock_irqrestore(&conn->lock, flags);\n}\n\nstatic void mailbox_tx_handler(unsigned int queue_bitmap)\n{\n\tint i;\n\tint bit;\n\n\t/* only get valid queues */\n\tqueue_bitmap &= g_atm_priv_data.conn_table;\n\n\tfor ( i = 0, bit = 1; i < MAX_PVC_NUMBER; i++, bit <<= 1 ) {\n\t\tif (queue_bitmap & bit)\n\t\t\tfree_tx_ring(i);\n\t}\n}\n\nstatic inline void mailbox_oam_rx_handler(void)\n{\n\tunsigned int vlddes = WRX_DMA_CHANNEL_CONFIG(RX_DMA_CH_OAM)->vlddes;\n\tstruct rx_descriptor reg_desc;\n\tstruct uni_cell_header *header;\n\tint conn;\n\tstruct atm_vcc *vcc;\n\tunsigned int i;\n\n\tfor ( i = 0; i < vlddes; i++ ) {\n\t\tunsigned int loop_count = 0;\n\n\t\tdo {\n\t\t\treg_desc = g_atm_priv_data.oam_desc[g_atm_priv_data.oam_desc_pos];\n\t\t\tif ( ++loop_count == 1000 )\n\t\t\t\tbreak;\n\t\t} while ( reg_desc.own || !reg_desc.c );    //  keep test OWN and C bit until data is ready\n\t\tASSERT(loop_count == 1, \"loop_count = %u, own = %d, c = %d, oam_desc_pos = %u\", loop_count, (int)reg_desc.own, (int)reg_desc.c, g_atm_priv_data.oam_desc_pos);\n\n\t\theader = (struct uni_cell_header *)&g_atm_priv_data.oam_buf[g_atm_priv_data.oam_desc_pos * RX_DMA_CH_OAM_BUF_SIZE];\n\n\t\tif ( header->pti == ATM_PTI_SEGF5 || header->pti == ATM_PTI_E2EF5 )\n\t\t\tconn = find_vpivci(header->vpi, header->vci);\n\t\telse if ( header->vci == 0x03 || header->vci == 0x04 )\n\t\t\tconn = find_vpi(header->vpi);\n\t\telse\n\t\t\tconn = -1;\n\n\t\tif ( conn >= 0 && g_atm_priv_data.conn[conn].vcc != NULL ) {\n\t\t\tvcc = g_atm_priv_data.conn[conn].vcc;\n\n\t\t\tif ( vcc->push_oam != NULL )\n\t\t\t\tvcc->push_oam(vcc, header);\n\t\t\telse\n\t\t\t\tifx_push_oam((unsigned char *)header);\n\n\t\t\tg_atm_priv_data.wrx_oam++;\n\n\t\t\tadsl_led_flash();\n\t\t} else\n\t\t\tg_atm_priv_data.wrx_drop_oam++;\n\n\t\treg_desc.byteoff = 0;\n\t\treg_desc.datalen = RX_DMA_CH_OAM_BUF_SIZE;\n\t\treg_desc.own = 1;\n\t\treg_desc.c   = 0;\n\n\t\tg_atm_priv_data.oam_desc[g_atm_priv_data.oam_desc_pos] = reg_desc;\n\t\tif ( ++g_atm_priv_data.oam_desc_pos == RX_DMA_CH_OAM_DESC_LEN )\n\t\t\tg_atm_priv_data.oam_desc_pos = 0;\n\n\t\tdma_cache_inv((unsigned long)header, CELL_SIZE);\n\t\tmailbox_signal(RX_DMA_CH_OAM, 0);\n\t}\n}\n\nstatic inline void mailbox_aal_rx_handler(void)\n{\n\tunsigned int vlddes = WRX_DMA_CHANNEL_CONFIG(RX_DMA_CH_AAL)->vlddes;\n\tstruct rx_descriptor reg_desc;\n\tint conn;\n\tstruct atm_vcc *vcc;\n\tstruct sk_buff *skb, *new_skb;\n\tstruct rx_inband_trailer *trailer;\n\tunsigned int i;\n\n\tfor ( i = 0; i < vlddes; i++ ) {\n\t\tunsigned int loop_count = 0;\n\n\t\tdo {\n\t\t\treg_desc = g_atm_priv_data.aal_desc[g_atm_priv_data.aal_desc_pos];\n\t\t\tif ( ++loop_count == 1000 )\n\t\t\t\tbreak;\n\t\t} while ( reg_desc.own || !reg_desc.c );    //  keep test OWN and C bit until data is ready\n\t\tASSERT(loop_count == 1, \"loop_count = %u, own = %d, c = %d, aal_desc_pos = %u\", loop_count, (int)reg_desc.own, (int)reg_desc.c, g_atm_priv_data.aal_desc_pos);\n\n\t\tconn = reg_desc.id;\n\n\t\tif ( g_atm_priv_data.conn[conn].vcc != NULL ) {\n\t\t\tvcc = g_atm_priv_data.conn[conn].vcc;\n\n\t\t\tskb = get_skb_rx_pointer(reg_desc.dataptr);\n\n\t\t\tif ( reg_desc.err ) {\n\t\t\t\tif ( vcc->qos.aal == ATM_AAL5 ) {\n\t\t\t\t\ttrailer = (struct rx_inband_trailer *)((unsigned int)skb->data + ((reg_desc.byteoff + reg_desc.datalen + MAX_RX_PACKET_PADDING_BYTES) & ~MAX_RX_PACKET_PADDING_BYTES));\n\t\t\t\t\tif ( trailer->stw_crc )\n\t\t\t\t\t\tg_atm_priv_data.conn[conn].aal5_vcc_crc_err++;\n\t\t\t\t\tif ( trailer->stw_ovz )\n\t\t\t\t\t\tg_atm_priv_data.conn[conn].aal5_vcc_oversize_sdu++;\n\t\t\t\t\tg_atm_priv_data.wrx_drop_pdu++;\n\t\t\t\t}\n\t\t\t\tif ( vcc->stats ) {\n\t\t\t\t\tatomic_inc(&vcc->stats->rx_drop);\n\t\t\t\t\tatomic_inc(&vcc->stats->rx_err);\n\t\t\t\t}\n\t\t\t\treg_desc.err = 0;\n\t\t\t} else if ( atm_charge(vcc, skb->truesize) ) {\n\t\t\t\tnew_skb = alloc_skb_rx();\n\t\t\t\tif ( new_skb != NULL ) {\n#if defined(ENABLE_LESS_CACHE_INV) && ENABLE_LESS_CACHE_INV\n\t\t\t\t\tif ( reg_desc.byteoff + reg_desc.datalen > LESS_CACHE_INV_LEN )\n\t\t\t\t\t\tdma_cache_inv((unsigned long)skb->data + LESS_CACHE_INV_LEN, reg_desc.byteoff + reg_desc.datalen - LESS_CACHE_INV_LEN);\n#endif\n\n\t\t\t\t\tskb_reserve(skb, reg_desc.byteoff);\n\t\t\t\t\tskb_put(skb, reg_desc.datalen);\n\t\t\t\t\tATM_SKB(skb)->vcc = vcc;\n\n\t\t\t\t\tvcc->push(vcc, skb);\n\n\t\t\t\t\tif ( vcc->qos.aal == ATM_AAL5 )\n\t\t\t\t\t\tg_atm_priv_data.wrx_pdu++;\n\t\t\t\t\tif ( vcc->stats )\n\t\t\t\t\t\tatomic_inc(&vcc->stats->rx);\n\t\t\t\t\tadsl_led_flash();\n\n\t\t\t\t\treg_desc.dataptr = (unsigned int)new_skb->data >> 2;\n\t\t\t\t} else {\n\t\t\t\t\tatm_return(vcc, skb->truesize);\n\t\t\t\t\tif ( vcc->qos.aal == ATM_AAL5 )\n\t\t\t\t\t\tg_atm_priv_data.wrx_drop_pdu++;\n\t\t\t\t\tif ( vcc->stats )\n\t\t\t\t\t\tatomic_inc(&vcc->stats->rx_drop);\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\tif ( vcc->qos.aal == ATM_AAL5 )\n\t\t\t\t\tg_atm_priv_data.wrx_drop_pdu++;\n\t\t\t\tif ( vcc->stats )\n\t\t\t\t\tatomic_inc(&vcc->stats->rx_drop);\n\t\t\t}\n\t\t} else {\n\t\t\tg_atm_priv_data.wrx_drop_pdu++;\n\t\t}\n\n\t\treg_desc.byteoff = 0;\n\t\treg_desc.datalen = RX_DMA_CH_AAL_BUF_SIZE;\n\t\treg_desc.own = 1;\n\t\treg_desc.c   = 0;\n\n\t\tg_atm_priv_data.aal_desc[g_atm_priv_data.aal_desc_pos] = reg_desc;\n\t\tif ( ++g_atm_priv_data.aal_desc_pos == dma_rx_descriptor_length )\n\t\t\tg_atm_priv_data.aal_desc_pos = 0;\n\n\t\tmailbox_signal(RX_DMA_CH_AAL, 0);\n\t}\n}\n\nstatic void do_ppe_tasklet(unsigned long data)\n{\n\tunsigned int irqs = *MBOX_IGU1_ISR;\n\t*MBOX_IGU1_ISRC = *MBOX_IGU1_ISR;\n\n\tif (irqs & (1 << RX_DMA_CH_AAL))\n\t\tmailbox_aal_rx_handler();\n\tif (irqs & (1 << RX_DMA_CH_OAM))\n\t\tmailbox_oam_rx_handler();\n\n\t/* any valid tx irqs */\n\tif ((irqs >> (FIRST_QSB_QID + 16)) & g_atm_priv_data.conn_table)\n\t\tmailbox_tx_handler(irqs >> (FIRST_QSB_QID + 16));\n\n\tif ((*MBOX_IGU1_ISR & ((1 << RX_DMA_CH_AAL) | (1 << RX_DMA_CH_OAM))) != 0)\n\t\ttasklet_schedule(&g_dma_tasklet);\n\telse if (*MBOX_IGU1_ISR >> (FIRST_QSB_QID + 16)) /* TX queue */\n\t\ttasklet_schedule(&g_dma_tasklet);\n\telse\n\t\tenable_irq(PPE_MAILBOX_IGU1_INT);\n}\n\nstatic irqreturn_t mailbox_irq_handler(int irq, void *dev_id)\n{\n\tif ( !*MBOX_IGU1_ISR )\n\t\treturn IRQ_HANDLED;\n\n\tdisable_irq_nosync(PPE_MAILBOX_IGU1_INT);\n\ttasklet_schedule(&g_dma_tasklet);\n\n\treturn IRQ_HANDLED;\n}\n\nstatic inline void mailbox_signal(unsigned int queue, int is_tx)\n{\n\tint count = 1000;\n\n\tif ( is_tx ) {\n\t\twhile ( MBOX_IGU3_ISR_ISR(queue + FIRST_QSB_QID + 16) && count > 0 )\n\t\t\tcount--;\n\t\t*MBOX_IGU3_ISRS = MBOX_IGU3_ISRS_SET(queue + FIRST_QSB_QID + 16);\n\t} else {\n\t\twhile ( MBOX_IGU3_ISR_ISR(queue) && count > 0 )\n\t\t\tcount--;\n\t\t*MBOX_IGU3_ISRS = MBOX_IGU3_ISRS_SET(queue);\n\t}\n\n\tASSERT(count > 0, \"queue = %u, is_tx = %d, MBOX_IGU3_ISR = 0x%08x\", queue, is_tx, IFX_REG_R32(MBOX_IGU3_ISR));\n}\n\nstatic void set_qsb(struct atm_vcc *vcc, struct atm_qos *qos, unsigned int queue)\n{\n\tstruct clk *fpi_clk = clk_get_fpi();\n\tunsigned int qsb_clk = clk_get_rate(fpi_clk);\n\tunsigned int qsb_qid = queue + FIRST_QSB_QID;\n\tunion qsb_queue_parameter_table qsb_queue_parameter_table = {{0}};\n\tunion qsb_queue_vbr_parameter_table qsb_queue_vbr_parameter_table = {{0}};\n\tunsigned int tmp;\n\n\n\t/*\n\t *  Peak Cell Rate (PCR) Limiter\n\t */\n\tif ( qos->txtp.max_pcr == 0 )\n\t\tqsb_queue_parameter_table.bit.tp = 0;   /*  disable PCR limiter */\n\telse {\n\t\t/*  peak cell rate would be slightly lower than requested [maximum_rate / pcr = (qsb_clock / 8) * (time_step / 4) / pcr] */\n\t\ttmp = ((qsb_clk * qsb_tstep) >> 5) / qos->txtp.max_pcr + 1;\n\t\t/*  check if overflow takes place   */\n\t\tqsb_queue_parameter_table.bit.tp = tmp > QSB_TP_TS_MAX ? QSB_TP_TS_MAX : tmp;\n\t}\n\n#if !defined(DISABLE_QOS_WORKAROUND) || !DISABLE_QOS_WORKAROUND\n\t//  A funny issue. Create two PVCs, one UBR and one UBR with max_pcr.\n\t//  Send packets to these two PVCs at same time, it trigger strange behavior.\n\t//  In A1, RAM from 0x80000000 to 0x0x8007FFFF was corrupted with fixed pattern 0x00000000 0x40000000.\n\t//  In A4, PPE firmware keep emiting unknown cell and do not respond to driver.\n\t//  To work around, create UBR always with max_pcr.\n\t//  If user want to create UBR without max_pcr, we give a default one larger than line-rate.\n\tif ( qos->txtp.traffic_class == ATM_UBR && qsb_queue_parameter_table.bit.tp == 0 ) {\n\t\tint port = g_atm_priv_data.conn[queue].port;\n\t\tunsigned int max_pcr = g_atm_priv_data.port[port].tx_max_cell_rate + 1000;\n\n\t\ttmp = ((qsb_clk * qsb_tstep) >> 5) / max_pcr + 1;\n\t\tif ( tmp > QSB_TP_TS_MAX )\n\t\t\ttmp = QSB_TP_TS_MAX;\n\t\telse if ( tmp < 1 )\n\t\t\ttmp = 1;\n\t\tqsb_queue_parameter_table.bit.tp = tmp;\n\t}\n#endif\n\n\t/*\n\t *  Weighted Fair Queueing Factor (WFQF)\n\t */\n\tswitch ( qos->txtp.traffic_class ) {\n\tcase ATM_CBR:\n\tcase ATM_VBR_RT:\n\t\t/*  real time queue gets weighted fair queueing bypass  */\n\t\tqsb_queue_parameter_table.bit.wfqf = 0;\n\t\tbreak;\n\tcase ATM_VBR_NRT:\n\tcase ATM_UBR_PLUS:\n\t\t/*  WFQF calculation here is based on virtual cell rates, to reduce granularity for high rates  */\n\t\t/*  WFQF is maximum cell rate / garenteed cell rate                                             */\n\t\t/*  wfqf = qsb_minimum_cell_rate * QSB_WFQ_NONUBR_MAX / requested_minimum_peak_cell_rate        */\n\t\tif ( qos->txtp.min_pcr == 0 )\n\t\t\tqsb_queue_parameter_table.bit.wfqf = QSB_WFQ_NONUBR_MAX;\n\t\telse {\n\t\t\ttmp = QSB_GCR_MIN * QSB_WFQ_NONUBR_MAX / qos->txtp.min_pcr;\n\t\t\tif ( tmp == 0 )\n\t\t\t\tqsb_queue_parameter_table.bit.wfqf = 1;\n\t\t\telse if ( tmp > QSB_WFQ_NONUBR_MAX )\n\t\t\t\tqsb_queue_parameter_table.bit.wfqf = QSB_WFQ_NONUBR_MAX;\n\t\t\telse\n\t\t\t\tqsb_queue_parameter_table.bit.wfqf = tmp;\n\t\t}\n\t\tbreak;\n\tdefault:\n\tcase ATM_UBR:\n\t\tqsb_queue_parameter_table.bit.wfqf = QSB_WFQ_UBR_BYPASS;\n\t}\n\n\t/*\n\t *  Sustained Cell Rate (SCR) Leaky Bucket Shaper VBR.0/VBR.1\n\t */\n\tif ( qos->txtp.traffic_class == ATM_VBR_RT || qos->txtp.traffic_class == ATM_VBR_NRT ) {\n#if 0\n\t\tif ( qos->txtp.scr == 0 ) {\n#endif\n\t\t\t/*  disable shaper  */\n\t\t\tqsb_queue_vbr_parameter_table.bit.taus = 0;\n\t\t\tqsb_queue_vbr_parameter_table.bit.ts = 0;\n#if 0\n\t\t} else {\n\t\t\t/*  Cell Loss Priority  (CLP)   */\n\t\t\tif ( (vcc->atm_options & ATM_ATMOPT_CLP) )\n\t\t\t\t/*  CLP1    */\n\t\t\t\tqsb_queue_parameter_table.bit.vbr = 1;\n\t\t\telse\n\t\t\t\t/*  CLP0    */\n\t\t\t\tqsb_queue_parameter_table.bit.vbr = 0;\n\t\t\t/*  Rate Shaper Parameter (TS) and Burst Tolerance Parameter for SCR (tauS) */\n\t\t\ttmp = ((qsb_clk * qsb_tstep) >> 5) / qos->txtp.scr + 1;\n\t\t\tqsb_queue_vbr_parameter_table.bit.ts = tmp > QSB_TP_TS_MAX ? QSB_TP_TS_MAX : tmp;\n\t\t\ttmp = (qos->txtp.mbs - 1) * (qsb_queue_vbr_parameter_table.bit.ts - qsb_queue_parameter_table.bit.tp) / 64;\n\t\t\tif ( tmp == 0 )\n\t\t\t\tqsb_queue_vbr_parameter_table.bit.taus = 1;\n\t\t\telse if ( tmp > QSB_TAUS_MAX )\n\t\t\t\tqsb_queue_vbr_parameter_table.bit.taus = QSB_TAUS_MAX;\n\t\t\telse\n\t\t\t\tqsb_queue_vbr_parameter_table.bit.taus = tmp;\n\t\t}\n#endif\n\t} else {\n\t\tqsb_queue_vbr_parameter_table.bit.taus = 0;\n\t\tqsb_queue_vbr_parameter_table.bit.ts = 0;\n\t}\n\n\t/*  Queue Parameter Table (QPT) */\n\t*QSB_RTM   = QSB_RTM_DM_SET(QSB_QPT_SET_MASK);\n\t*QSB_RTD   = QSB_RTD_TTV_SET(qsb_queue_parameter_table.dword);\n\t*QSB_RAMAC = QSB_RAMAC_RW_SET(QSB_RAMAC_RW_WRITE) | QSB_RAMAC_TSEL_SET(QSB_RAMAC_TSEL_QPT) | QSB_RAMAC_LH_SET(QSB_RAMAC_LH_LOW) | QSB_RAMAC_TESEL_SET(qsb_qid);\n\t/*  Queue VBR Paramter Table (QVPT) */\n\t*QSB_RTM   = QSB_RTM_DM_SET(QSB_QVPT_SET_MASK);\n\t*QSB_RTD   = QSB_RTD_TTV_SET(qsb_queue_vbr_parameter_table.dword);\n\t*QSB_RAMAC = QSB_RAMAC_RW_SET(QSB_RAMAC_RW_WRITE) | QSB_RAMAC_TSEL_SET(QSB_RAMAC_TSEL_VBR) | QSB_RAMAC_LH_SET(QSB_RAMAC_LH_LOW) | QSB_RAMAC_TESEL_SET(qsb_qid);\n\n}\n\nstatic void qsb_global_set(void)\n{\n\tstruct clk *fpi_clk = clk_get_fpi();\n\tunsigned int qsb_clk = clk_get_rate(fpi_clk);\n\tint i;\n\tunsigned int tmp1, tmp2, tmp3;\n\n\t*QSB_ICDV = QSB_ICDV_TAU_SET(qsb_tau);\n\t*QSB_SBL  = QSB_SBL_SBL_SET(qsb_srvm);\n\t*QSB_CFG  = QSB_CFG_TSTEPC_SET(qsb_tstep >> 1);\n\n\t/*\n\t *  set SCT and SPT per port\n\t */\n\tfor ( i = 0; i < ATM_PORT_NUMBER; i++ ) {\n\t\tif ( g_atm_priv_data.port[i].tx_max_cell_rate != 0 ) {\n\t\t\ttmp1 = ((qsb_clk * qsb_tstep) >> 1) / g_atm_priv_data.port[i].tx_max_cell_rate;\n\t\t\ttmp2 = tmp1 >> 6;                   /*  integer value of Tsb    */\n\t\t\ttmp3 = (tmp1 & ((1 << 6) - 1)) + 1; /*  fractional part of Tsb  */\n\t\t\t/*  carry over to integer part (?)  */\n\t\t\tif ( tmp3 == (1 << 6) ) {\n\t\t\t\ttmp3 = 0;\n\t\t\t\ttmp2++;\n\t\t\t}\n\t\t\tif ( tmp2 == 0 )\n\t\t\t\ttmp2 = tmp3 = 1;\n\t\t\t/*  1. set mask                                 */\n\t\t\t/*  2. write value to data transfer register    */\n\t\t\t/*  3. start the tranfer                        */\n\t\t\t/*  SCT (FracRate)  */\n\t\t\t*QSB_RTM   = QSB_RTM_DM_SET(QSB_SET_SCT_MASK);\n\t\t\t*QSB_RTD   = QSB_RTD_TTV_SET(tmp3);\n\t\t\t*QSB_RAMAC = QSB_RAMAC_RW_SET(QSB_RAMAC_RW_WRITE) |\n\t\t\t\t\tQSB_RAMAC_TSEL_SET(QSB_RAMAC_TSEL_SCT) |\n\t\t\t\t\tQSB_RAMAC_LH_SET(QSB_RAMAC_LH_LOW) |\n\t\t\t\t\tQSB_RAMAC_TESEL_SET(i & 0x01);\n\t\t\t/*  SPT (SBV + PN + IntRage)    */\n\t\t\t*QSB_RTM   = QSB_RTM_DM_SET(QSB_SET_SPT_MASK);\n\t\t\t*QSB_RTD   = QSB_RTD_TTV_SET(QSB_SPT_SBV_VALID | QSB_SPT_PN_SET(i & 0x01) | QSB_SPT_INTRATE_SET(tmp2));\n\t\t\t*QSB_RAMAC = QSB_RAMAC_RW_SET(QSB_RAMAC_RW_WRITE) |\n\t\t\t\tQSB_RAMAC_TSEL_SET(QSB_RAMAC_TSEL_SPT) |\n\t\t\t\tQSB_RAMAC_LH_SET(QSB_RAMAC_LH_LOW) |\n\t\t\t\tQSB_RAMAC_TESEL_SET(i & 0x01);\n\t\t}\n\t}\n}\n\nstatic inline void set_htu_entry(unsigned int vpi, unsigned int vci, unsigned int queue, int aal5, int is_retx)\n{\n\tstruct htu_entry htu_entry = {\n\t\tres1:       0x00,\n\t\tclp:        is_retx ? 0x01 : 0x00,\n\t\tpid:        g_atm_priv_data.conn[queue].port & 0x01,\n\t\tvpi:        vpi,\n\t\tvci:        vci,\n\t\tpti:        0x00,\n\t\tvld:        0x01};\n\n\tstruct htu_mask htu_mask = {\n\t\tset:        0x01,\n\t\tclp:        0x01,\n\t\tpid_mask:   0x02,\n\t\tvpi_mask:   0x00,\n\t\tvci_mask:   0x0000,\n\t\tpti_mask:   0x03,   //  0xx, user data\n\t\tclear:      0x00};\n\n\tstruct htu_result htu_result = {\n\t\tres1:       0x00,\n\t\tcellid:     queue,\n\t\tres2:       0x00,\n\t\ttype:       aal5 ? 0x00 : 0x01,\n\t\tven:        0x01,\n\t\tres3:       0x00,\n\t\tqid:        queue};\n\n\t*HTU_RESULT(queue + OAM_HTU_ENTRY_NUMBER) = htu_result;\n\t*HTU_MASK(queue + OAM_HTU_ENTRY_NUMBER)   = htu_mask;\n\t*HTU_ENTRY(queue + OAM_HTU_ENTRY_NUMBER)  = htu_entry;\n}\n\nstatic inline void clear_htu_entry(unsigned int queue)\n{\n\tHTU_ENTRY(queue + OAM_HTU_ENTRY_NUMBER)->vld = 0;\n}\n\nstatic void validate_oam_htu_entry(void)\n{\n\tHTU_ENTRY(OAM_F4_SEG_HTU_ENTRY)->vld = 1;\n\tHTU_ENTRY(OAM_F4_TOT_HTU_ENTRY)->vld = 1;\n\tHTU_ENTRY(OAM_F5_HTU_ENTRY)->vld = 1;\n}\n\nstatic void invalidate_oam_htu_entry(void)\n{\n\tHTU_ENTRY(OAM_F4_SEG_HTU_ENTRY)->vld = 0;\n\tHTU_ENTRY(OAM_F4_TOT_HTU_ENTRY)->vld = 0;\n\tHTU_ENTRY(OAM_F5_HTU_ENTRY)->vld = 0;\n}\n\nstatic inline int find_vpi(unsigned int vpi)\n{\n\tint i;\n\tunsigned int bit;\n\n\tfor ( i = 0, bit = 1; i < MAX_PVC_NUMBER; i++, bit <<= 1 ) {\n\t\tif ( (g_atm_priv_data.conn_table & bit) != 0\n\t\t\t\t&& g_atm_priv_data.conn[i].vcc != NULL\n\t\t\t\t&& vpi == g_atm_priv_data.conn[i].vcc->vpi )\n\t\t\treturn i;\n\t}\n\n\treturn -1;\n}\n\nstatic inline int find_vpivci(unsigned int vpi, unsigned int vci)\n{\n\tint i;\n\tunsigned int bit;\n\n\tfor ( i = 0, bit = 1; i < MAX_PVC_NUMBER; i++, bit <<= 1 ) {\n\t\tif ( (g_atm_priv_data.conn_table & bit) != 0\n\t\t\t\t&& g_atm_priv_data.conn[i].vcc != NULL\n\t\t\t\t&& vpi == g_atm_priv_data.conn[i].vcc->vpi\n\t\t\t\t&& vci == g_atm_priv_data.conn[i].vcc->vci )\n\t\t\treturn i;\n\t}\n\n\treturn -1;\n}\n\nstatic inline int find_vcc(struct atm_vcc *vcc)\n{\n\tint i;\n\tunsigned int bit;\n\n\tfor ( i = 0, bit = 1; i < MAX_PVC_NUMBER; i++, bit <<= 1 ) {\n\t\tif ( (g_atm_priv_data.conn_table & bit) != 0\n\t\t\t&& g_atm_priv_data.conn[i].vcc == vcc )\n\t\treturn i;\n\t}\n\n\treturn -1;\n}\n\nstatic inline int ifx_atm_version(const struct ltq_atm_ops *ops, char *buf)\n{\n\tint len = 0;\n\tunsigned int major, minor;\n\n\tops->fw_ver(&major, &minor);\n\n\tlen += sprintf(buf + len, \"ATM%d.%d.%d\", IFX_ATM_VER_MAJOR, IFX_ATM_VER_MID, IFX_ATM_VER_MINOR);\n\tlen += sprintf(buf + len, \"    ATM (A1) firmware version %d.%d\\n\", major, minor);\n\n\treturn len;\n}\n\nstatic inline void check_parameters(void)\n{\n\t/*  Please refer to Amazon spec 15.4 for setting these values.  */\n\tif ( qsb_tau < 1 )\n\t\tqsb_tau = 1;\n\tif ( qsb_tstep < 1 )\n\t\tqsb_tstep = 1;\n\telse if ( qsb_tstep > 4 )\n\t\tqsb_tstep = 4;\n\telse if ( qsb_tstep == 3 )\n\t\tqsb_tstep = 2;\n\n\t/*  There is a delay between PPE write descriptor and descriptor is       */\n\t/*  really stored in memory. Host also has this delay when writing        */\n\t/*  descriptor. So PPE will use this value to determine if the write      */\n\t/*  operation makes effect.                                               */\n\tif ( write_descriptor_delay < 0 )\n\t\twrite_descriptor_delay = 0;\n\n\tif ( aal5_fill_pattern < 0 )\n\t\taal5_fill_pattern = 0;\n\telse\n\t\taal5_fill_pattern &= 0xFF;\n\n\t/*  Because of the limitation of length field in descriptors, the packet  */\n\t/*  size could not be larger than 64K minus overhead size.                */\n\tif ( aal5r_max_packet_size < 0 )\n\t\taal5r_max_packet_size = 0;\n\telse if ( aal5r_max_packet_size >= 65535 - MAX_RX_FRAME_EXTRA_BYTES )\n\t\taal5r_max_packet_size = 65535 - MAX_RX_FRAME_EXTRA_BYTES;\n\tif ( aal5r_min_packet_size < 0 )\n\t\taal5r_min_packet_size = 0;\n\telse if ( aal5r_min_packet_size > aal5r_max_packet_size )\n\t\taal5r_min_packet_size = aal5r_max_packet_size;\n\tif ( aal5s_max_packet_size < 0 )\n\t\taal5s_max_packet_size = 0;\n\telse if ( aal5s_max_packet_size >= 65535 - MAX_TX_FRAME_EXTRA_BYTES )\n\t\taal5s_max_packet_size = 65535 - MAX_TX_FRAME_EXTRA_BYTES;\n\tif ( aal5s_min_packet_size < 0 )\n\t\taal5s_min_packet_size = 0;\n\telse if ( aal5s_min_packet_size > aal5s_max_packet_size )\n\t\taal5s_min_packet_size = aal5s_max_packet_size;\n\n\tif ( dma_rx_descriptor_length < 2 )\n\t\tdma_rx_descriptor_length = 2;\n\tif ( dma_tx_descriptor_length < 2 )\n\t\tdma_tx_descriptor_length = 2;\n\tif ( dma_rx_clp1_descriptor_threshold < 0 )\n\t\tdma_rx_clp1_descriptor_threshold = 0;\n\telse if ( dma_rx_clp1_descriptor_threshold > dma_rx_descriptor_length )\n\t\tdma_rx_clp1_descriptor_threshold = dma_rx_descriptor_length;\n\n\tif ( dma_tx_descriptor_length < 2 )\n\t\tdma_tx_descriptor_length = 2;\n}\n\nstatic inline int init_priv_data(void)\n{\n\tvoid *p;\n\tint i;\n\tstruct rx_descriptor rx_desc = {0};\n\tstruct sk_buff *skb;\n\tvolatile struct tx_descriptor *p_tx_desc;\n\tstruct sk_buff **ppskb;\n\n\t//  clear atm private data structure\n\tmemset(&g_atm_priv_data, 0, sizeof(g_atm_priv_data));\n\n\t//  allocate memory for RX (AAL) descriptors\n\tp = kzalloc(dma_rx_descriptor_length * sizeof(struct rx_descriptor) + DESC_ALIGNMENT, GFP_KERNEL);\n\tif ( p == NULL )\n\t\treturn -1;\n\tdma_cache_wback_inv((unsigned long)p, dma_rx_descriptor_length * sizeof(struct rx_descriptor) + DESC_ALIGNMENT);\n\tg_atm_priv_data.aal_desc_base = p;\n\tp = (void *)((((unsigned int)p + DESC_ALIGNMENT - 1) & ~(DESC_ALIGNMENT - 1)) | KSEG1);\n\tg_atm_priv_data.aal_desc = (volatile struct rx_descriptor *)p;\n\n\t//  allocate memory for RX (OAM) descriptors\n\tp = kzalloc(RX_DMA_CH_OAM_DESC_LEN * sizeof(struct rx_descriptor) + DESC_ALIGNMENT, GFP_KERNEL);\n\tif ( p == NULL )\n\t\treturn -1;\n\tdma_cache_wback_inv((unsigned long)p, RX_DMA_CH_OAM_DESC_LEN * sizeof(struct rx_descriptor) + DESC_ALIGNMENT);\n\tg_atm_priv_data.oam_desc_base = p;\n\tp = (void *)((((unsigned int)p + DESC_ALIGNMENT - 1) & ~(DESC_ALIGNMENT - 1)) | KSEG1);\n\tg_atm_priv_data.oam_desc = (volatile struct rx_descriptor *)p;\n\n\t//  allocate memory for RX (OAM) buffer\n\tp = kzalloc(RX_DMA_CH_OAM_DESC_LEN * RX_DMA_CH_OAM_BUF_SIZE + DATA_BUFFER_ALIGNMENT, GFP_KERNEL);\n\tif ( p == NULL )\n\t\treturn -1;\n\tdma_cache_wback_inv((unsigned long)p, RX_DMA_CH_OAM_DESC_LEN * RX_DMA_CH_OAM_BUF_SIZE + DATA_BUFFER_ALIGNMENT);\n\tg_atm_priv_data.oam_buf_base = p;\n\tp = (void *)(((unsigned int)p + DATA_BUFFER_ALIGNMENT - 1) & ~(DATA_BUFFER_ALIGNMENT - 1));\n\tg_atm_priv_data.oam_buf = p;\n\n\t//  allocate memory for TX descriptors\n\tp = kzalloc(MAX_PVC_NUMBER * dma_tx_descriptor_length * sizeof(struct tx_descriptor) + DESC_ALIGNMENT, GFP_KERNEL);\n\tif ( p == NULL )\n\t\treturn -1;\n\tdma_cache_wback_inv((unsigned long)p, MAX_PVC_NUMBER * dma_tx_descriptor_length * sizeof(struct tx_descriptor) + DESC_ALIGNMENT);\n\tg_atm_priv_data.tx_desc_base = p;\n\n\t//  allocate memory for TX skb pointers\n\tp = kzalloc(MAX_PVC_NUMBER * dma_tx_descriptor_length * sizeof(struct sk_buff *) + 4, GFP_KERNEL);\n\tif ( p == NULL )\n\t\treturn -1;\n\tdma_cache_wback_inv((unsigned long)p, MAX_PVC_NUMBER * dma_tx_descriptor_length * sizeof(struct sk_buff *) + 4);\n\tg_atm_priv_data.tx_skb_base = p;\n\n\t//  setup RX (AAL) descriptors\n\trx_desc.own     = 1;\n\trx_desc.c       = 0;\n\trx_desc.sop     = 1;\n\trx_desc.eop     = 1;\n\trx_desc.byteoff = 0;\n\trx_desc.id      = 0;\n\trx_desc.err     = 0;\n\trx_desc.datalen = RX_DMA_CH_AAL_BUF_SIZE;\n\tfor ( i = 0; i < dma_rx_descriptor_length; i++ ) {\n\t\tskb = alloc_skb_rx();\n\t\tif ( skb == NULL )\n\t\t\treturn -1;\n\t\trx_desc.dataptr = ((unsigned int)skb->data >> 2) & 0x0FFFFFFF;\n\t\tg_atm_priv_data.aal_desc[i] = rx_desc;\n\t}\n\n\t//  setup RX (OAM) descriptors\n\tp = (void *)((unsigned int)g_atm_priv_data.oam_buf | KSEG1);\n\trx_desc.own     = 1;\n\trx_desc.c       = 0;\n\trx_desc.sop     = 1;\n\trx_desc.eop     = 1;\n\trx_desc.byteoff = 0;\n\trx_desc.id      = 0;\n\trx_desc.err     = 0;\n\trx_desc.datalen = RX_DMA_CH_OAM_BUF_SIZE;\n\tfor ( i = 0; i < RX_DMA_CH_OAM_DESC_LEN; i++ ) {\n\t\trx_desc.dataptr = ((unsigned int)p >> 2) & 0x0FFFFFFF;\n\t\tg_atm_priv_data.oam_desc[i] = rx_desc;\n\t\tp = (void *)((unsigned int)p + RX_DMA_CH_OAM_BUF_SIZE);\n\t}\n\n\t//  setup TX descriptors and skb pointers\n\tp_tx_desc = (volatile struct tx_descriptor *)((((unsigned int)g_atm_priv_data.tx_desc_base + DESC_ALIGNMENT - 1) & ~(DESC_ALIGNMENT - 1)) | KSEG1);\n\tppskb = (struct sk_buff **)(((unsigned int)g_atm_priv_data.tx_skb_base + 3) & ~3);\n\tfor ( i = 0; i < MAX_PVC_NUMBER; i++ ) {\n\t\tspin_lock_init(&g_atm_priv_data.conn[i].lock);\n\t\tg_atm_priv_data.conn[i].tx_desc = &p_tx_desc[i * dma_tx_descriptor_length];\n\t\tg_atm_priv_data.conn[i].tx_skb  = &ppskb[i * dma_tx_descriptor_length];\n\t}\n\n\tfor ( i = 0; i < ATM_PORT_NUMBER; i++ )\n\t\tg_atm_priv_data.port[i].tx_max_cell_rate = DEFAULT_TX_LINK_RATE;\n\n\treturn 0;\n}\n\nstatic inline void clear_priv_data(void)\n{\n\tint i, j;\n\tstruct sk_buff *skb;\n\n\tfor ( i = 0; i < MAX_PVC_NUMBER; i++ ) {\n\t\tif ( g_atm_priv_data.conn[i].tx_skb != NULL ) {\n\t\t\tfor ( j = 0; j < dma_tx_descriptor_length; j++ )\n\t\t\t\tif ( g_atm_priv_data.conn[i].tx_skb[j] != NULL )\n\t\t\t\t\tdev_kfree_skb_any(g_atm_priv_data.conn[i].tx_skb[j]);\n\t\t}\n\t}\n\n\tif ( g_atm_priv_data.tx_skb_base != NULL )\n\t\tkfree(g_atm_priv_data.tx_skb_base);\n\n\tif ( g_atm_priv_data.tx_desc_base != NULL )\n\t\tkfree(g_atm_priv_data.tx_desc_base);\n\n\tif ( g_atm_priv_data.oam_buf_base != NULL )\n\t\tkfree(g_atm_priv_data.oam_buf_base);\n\n\tif ( g_atm_priv_data.oam_desc_base != NULL )\n\t\tkfree(g_atm_priv_data.oam_desc_base);\n\n\tif ( g_atm_priv_data.aal_desc_base != NULL ) {\n\t\tfor ( i = 0; i < dma_rx_descriptor_length; i++ ) {\n\t\t\tif ( g_atm_priv_data.aal_desc[i].sop || g_atm_priv_data.aal_desc[i].eop ) { //  descriptor initialized\n\t\t\t\tskb = get_skb_rx_pointer(g_atm_priv_data.aal_desc[i].dataptr);\n\t\t\t\tdev_kfree_skb_any(skb);\n\t\t\t}\n\t\t}\n\t\tkfree(g_atm_priv_data.aal_desc_base);\n\t}\n}\n\nstatic inline void init_rx_tables(void)\n{\n\tint i;\n\tstruct wrx_queue_config wrx_queue_config = {0};\n\tstruct wrx_dma_channel_config wrx_dma_channel_config = {0};\n\tstruct htu_entry htu_entry = {0};\n\tstruct htu_result htu_result = {0};\n\tstruct htu_mask htu_mask = {\n\t\tset:        0x01,\n\t\tclp:        0x01,\n\t\tpid_mask:   0x00,\n\t\tvpi_mask:   0x00,\n\t\tvci_mask:   0x00,\n\t\tpti_mask:   0x00,\n\t\tclear:      0x00\n\t};\n\n\t/*\n\t *  General Registers\n\t */\n\t*CFG_WRX_HTUTS  = MAX_PVC_NUMBER + OAM_HTU_ENTRY_NUMBER;\n#ifndef CONFIG_AMAZON_SE\n\t*CFG_WRX_QNUM   = MAX_QUEUE_NUMBER;\n#endif\n\t*CFG_WRX_DCHNUM = RX_DMA_CH_TOTAL;\n\t*WRX_DMACH_ON   = (1 << RX_DMA_CH_TOTAL) - 1;\n\t*WRX_HUNT_BITTH = DEFAULT_RX_HUNT_BITTH;\n\n\t/*\n\t *  WRX Queue Configuration Table\n\t */\n\twrx_queue_config.uumask    = 0xFF;\n\twrx_queue_config.cpimask   = 0xFF;\n\twrx_queue_config.uuexp     = 0;\n\twrx_queue_config.cpiexp    = 0;\n\twrx_queue_config.mfs       = aal5r_max_packet_size;\n\twrx_queue_config.oversize  = aal5r_max_packet_size;\n\twrx_queue_config.undersize = aal5r_min_packet_size;\n\twrx_queue_config.errdp     = aal5r_drop_error_packet;\n\twrx_queue_config.dmach     = RX_DMA_CH_AAL;\n\tfor ( i = 0; i < MAX_QUEUE_NUMBER; i++ )\n\t\t*WRX_QUEUE_CONFIG(i) = wrx_queue_config;\n\tWRX_QUEUE_CONFIG(OAM_RX_QUEUE)->dmach = RX_DMA_CH_OAM;\n\n\t/*\n\t *  WRX DMA Channel Configuration Table\n\t */\n\twrx_dma_channel_config.chrl   = 0;\n\twrx_dma_channel_config.clp1th = dma_rx_clp1_descriptor_threshold;\n\twrx_dma_channel_config.mode   = 0;\n\twrx_dma_channel_config.rlcfg  = 0;\n\n\twrx_dma_channel_config.deslen = RX_DMA_CH_OAM_DESC_LEN;\n\twrx_dma_channel_config.desba  = ((unsigned int)g_atm_priv_data.oam_desc >> 2) & 0x0FFFFFFF;\n\t*WRX_DMA_CHANNEL_CONFIG(RX_DMA_CH_OAM) = wrx_dma_channel_config;\n\n\twrx_dma_channel_config.deslen = dma_rx_descriptor_length;\n\twrx_dma_channel_config.desba  = ((unsigned int)g_atm_priv_data.aal_desc >> 2) & 0x0FFFFFFF;\n\t*WRX_DMA_CHANNEL_CONFIG(RX_DMA_CH_AAL) = wrx_dma_channel_config;\n\n\t/*\n\t *  HTU Tables\n\t */\n\tfor (i = 0; i < MAX_PVC_NUMBER; i++) {\n\t\thtu_result.qid = (unsigned int)i;\n\n\t\t*HTU_ENTRY(i + OAM_HTU_ENTRY_NUMBER)  = htu_entry;\n\t\t*HTU_MASK(i + OAM_HTU_ENTRY_NUMBER)   = htu_mask;\n\t\t*HTU_RESULT(i + OAM_HTU_ENTRY_NUMBER) = htu_result;\n\t}\n\n\t/*  OAM HTU Entry   */\n\thtu_entry.vci = 0x03;\n\thtu_mask.pid_mask = 0x03;\n\thtu_mask.vpi_mask = 0xFF;\n\thtu_mask.vci_mask = 0x0000;\n\thtu_mask.pti_mask = 0x07;\n\thtu_result.cellid = OAM_RX_QUEUE;\n\thtu_result.type   = 1;\n\thtu_result.ven    = 1;\n\thtu_result.qid    = OAM_RX_QUEUE;\n\t*HTU_RESULT(OAM_F4_SEG_HTU_ENTRY) = htu_result;\n\t*HTU_MASK(OAM_F4_SEG_HTU_ENTRY)   = htu_mask;\n\t*HTU_ENTRY(OAM_F4_SEG_HTU_ENTRY)  = htu_entry;\n\thtu_entry.vci     = 0x04;\n\thtu_result.cellid = OAM_RX_QUEUE;\n\thtu_result.type   = 1;\n\thtu_result.ven    = 1;\n\thtu_result.qid    = OAM_RX_QUEUE;\n\t*HTU_RESULT(OAM_F4_TOT_HTU_ENTRY) = htu_result;\n\t*HTU_MASK(OAM_F4_TOT_HTU_ENTRY)   = htu_mask;\n\t*HTU_ENTRY(OAM_F4_TOT_HTU_ENTRY)  = htu_entry;\n\thtu_entry.vci     = 0x00;\n\thtu_entry.pti     = 0x04;\n\thtu_mask.vci_mask = 0xFFFF;\n\thtu_mask.pti_mask = 0x01;\n\thtu_result.cellid = OAM_RX_QUEUE;\n\thtu_result.type   = 1;\n\thtu_result.ven    = 1;\n\thtu_result.qid    = OAM_RX_QUEUE;\n\t*HTU_RESULT(OAM_F5_HTU_ENTRY) = htu_result;\n\t*HTU_MASK(OAM_F5_HTU_ENTRY)   = htu_mask;\n\t*HTU_ENTRY(OAM_F5_HTU_ENTRY)  = htu_entry;\n}\n\nstatic inline void init_tx_tables(void)\n{\n\tint i;\n\tstruct wtx_queue_config wtx_queue_config = {0};\n\tstruct wtx_dma_channel_config wtx_dma_channel_config = {0};\n\tstruct wtx_port_config wtx_port_config = {\n\t\tres1:   0,\n\t\tqid:    0,\n\t\tqsben:  1\n\t};\n\n\t/*\n\t *  General Registers\n\t */\n\t*CFG_WTX_DCHNUM     = MAX_TX_DMA_CHANNEL_NUMBER;\n\t*WTX_DMACH_ON       = ((1 << MAX_TX_DMA_CHANNEL_NUMBER) - 1) ^ ((1 << FIRST_QSB_QID) - 1);\n\t*CFG_WRDES_DELAY    = write_descriptor_delay;\n\n\t/*\n\t *  WTX Port Configuration Table\n\t */\n\tfor ( i = 0; i < ATM_PORT_NUMBER; i++ )\n\t\t*WTX_PORT_CONFIG(i) = wtx_port_config;\n\n\t/*\n\t *  WTX Queue Configuration Table\n\t */\n\twtx_queue_config.qsben = 1;\n\twtx_queue_config.sbid  = 0;\n\tfor ( i = 0; i < MAX_TX_DMA_CHANNEL_NUMBER; i++ ) {\n\t\twtx_queue_config.qsb_vcid = i;\n\t\t*WTX_QUEUE_CONFIG(i) = wtx_queue_config;\n\t}\n\n\t/*\n\t *  WTX DMA Channel Configuration Table\n\t */\n\twtx_dma_channel_config.mode   = 0;\n\twtx_dma_channel_config.deslen = 0;\n\twtx_dma_channel_config.desba  = 0;\n\tfor ( i = 0; i < FIRST_QSB_QID; i++ )\n\t\t*WTX_DMA_CHANNEL_CONFIG(i) = wtx_dma_channel_config;\n\t/*  normal connection   */\n\twtx_dma_channel_config.deslen = dma_tx_descriptor_length;\n\tfor ( ; i < MAX_TX_DMA_CHANNEL_NUMBER ; i++ ) {\n\t\twtx_dma_channel_config.desba = ((unsigned int)g_atm_priv_data.conn[i - FIRST_QSB_QID].tx_desc >> 2) & 0x0FFFFFFF;\n\t\t*WTX_DMA_CHANNEL_CONFIG(i) = wtx_dma_channel_config;\n\t}\n}\n\nstatic int atm_showtime_enter(struct port_cell_info *port_cell, void *xdata_addr)\n{\n\tint i, j, port_num;\n\n\tASSERT(port_cell != NULL, \"port_cell is NULL\");\n\tASSERT(xdata_addr != NULL, \"xdata_addr is NULL\");\n\n\tfor ( j = 0; j < ATM_PORT_NUMBER && j < port_cell->port_num; j++ )\n\t\tif ( port_cell->tx_link_rate[j] > 0 )\n\t\t\tbreak;\n\tfor ( i = 0; i < ATM_PORT_NUMBER && i < port_cell->port_num; i++ )\n\t\tg_atm_priv_data.port[i].tx_max_cell_rate =\n\t\t\tport_cell->tx_link_rate[i] > 0 ? port_cell->tx_link_rate[i] : port_cell->tx_link_rate[j];\n\n\tqsb_global_set();\n\n\tfor ( i = 0; i < MAX_PVC_NUMBER; i++ )\n\t\tif ( g_atm_priv_data.conn[i].vcc != NULL )\n\t\t\tset_qsb(g_atm_priv_data.conn[i].vcc, &g_atm_priv_data.conn[i].vcc->qos, i);\n\n\t//  TODO: ReTX set xdata_addr\n\tg_xdata_addr = xdata_addr;\n\n\tg_showtime = 1;\n\n\tfor ( port_num = 0; port_num < ATM_PORT_NUMBER; port_num++ )\n\t\tatm_dev_signal_change(g_atm_priv_data.port[port_num].dev, ATM_PHY_SIG_FOUND);\n\n#if defined(CONFIG_VR9)\n\tIFX_REG_W32(0x0F, UTP_CFG);\n#endif\n\n\tprintk(\"enter showtime, cell rate: 0 - %d, 1 - %d, xdata addr: 0x%08x\\n\",\n\t\tg_atm_priv_data.port[0].tx_max_cell_rate,\n\t\tg_atm_priv_data.port[1].tx_max_cell_rate,\n\t\t(unsigned int)g_xdata_addr);\n\n\treturn 0;\n}\n\nstatic int atm_showtime_exit(void)\n{\n\tint port_num;\n\n\tif ( !g_showtime )\n\t\treturn -1;\n\n#if defined(CONFIG_VR9)\n\tIFX_REG_W32(0x00, UTP_CFG);\n#endif\n\n\tfor ( port_num = 0; port_num < ATM_PORT_NUMBER; port_num++ )\n\t\tatm_dev_signal_change(g_atm_priv_data.port[port_num].dev, ATM_PHY_SIG_LOST);\n\n\tg_showtime = 0;\n\tg_xdata_addr = NULL;\n\tprintk(\"leave showtime\\n\");\n\treturn 0;\n}\n\nextern struct ltq_atm_ops ar9_ops;\nextern struct ltq_atm_ops vr9_ops;\nextern struct ltq_atm_ops danube_ops;\nextern struct ltq_atm_ops ase_ops;\n\nstatic const struct of_device_id ltq_atm_match[] = {\n#ifdef CONFIG_DANUBE\n\t{ .compatible = \"lantiq,ppe-danube\", .data = &danube_ops },\n#elif defined CONFIG_AMAZON_SE\n\t{ .compatible = \"lantiq,ppe-ase\", .data = &ase_ops },\n#elif defined CONFIG_AR9\n\t{ .compatible = \"lantiq,ppe-arx100\", .data = &ar9_ops },\n#elif defined CONFIG_VR9\n\t{ .compatible = \"lantiq,ppe-xrx200\", .data = &vr9_ops },\n#endif\n\t{},\n};\nMODULE_DEVICE_TABLE(of, ltq_atm_match);\n\nstatic int ltq_atm_probe(struct platform_device *pdev)\n{\n\tconst struct of_device_id *match;\n\tstruct ltq_atm_ops *ops = NULL;\n\tint ret;\n\tint port_num;\n\tstruct port_cell_info port_cell = {0};\n\tchar ver_str[256];\n\n\tmatch = of_match_device(ltq_atm_match, &pdev->dev);\n\tif (!match) {\n\t\tdev_err(&pdev->dev, \"failed to find matching device\\n\");\n\t\treturn -ENOENT;\n\t}\n\tops = (struct ltq_atm_ops *) match->data;\n\n\tcheck_parameters();\n\n\tret = init_priv_data();\n\tif ( ret != 0 ) {\n\t\tpr_err(\"INIT_PRIV_DATA_FAIL\\n\");\n\t\tgoto INIT_PRIV_DATA_FAIL;\n\t}\n\n\tops->init(pdev);\n\tinit_rx_tables();\n\tinit_tx_tables();\n\n\t/*  create devices  */\n\tfor ( port_num = 0; port_num < ATM_PORT_NUMBER; port_num++ ) {\n\t\tg_atm_priv_data.port[port_num].dev = atm_dev_register(\"ifxmips_atm\", NULL, &g_ifx_atm_ops, -1, NULL);\n\t\tif ( !g_atm_priv_data.port[port_num].dev ) {\n\t\t\tpr_err(\"failed to register atm device %d!\\n\", port_num);\n\t\t\tret = -EIO;\n\t\t\tgoto ATM_DEV_REGISTER_FAIL;\n\t\t} else {\n\t\t\tg_atm_priv_data.port[port_num].dev->ci_range.vpi_bits = 8;\n\t\t\tg_atm_priv_data.port[port_num].dev->ci_range.vci_bits = 16;\n\t\t\tg_atm_priv_data.port[port_num].dev->link_rate = g_atm_priv_data.port[port_num].tx_max_cell_rate;\n\t\t\tg_atm_priv_data.port[port_num].dev->dev_data = (void*)port_num;\n\n#if defined(CONFIG_IFXMIPS_DSL_CPE_MEI) || defined(CONFIG_IFXMIPS_DSL_CPE_MEI_MODULE)\n\t\t\tatm_dev_signal_change(g_atm_priv_data.port[port_num].dev, ATM_PHY_SIG_LOST);\n#endif\n\t\t}\n\t}\n\n\t/*  register interrupt handler  */\n\tret = request_irq(PPE_MAILBOX_IGU1_INT, mailbox_irq_handler, 0, \"atm_mailbox_isr\", &g_atm_priv_data);\n\tif ( ret ) {\n\t\tif ( ret == -EBUSY ) {\n\t\t\tpr_err(\"IRQ may be occupied by other driver, please reconfig to disable it.\\n\");\n\t\t} else {\n\t\t\tpr_err(\"request_irq fail irq:%d\\n\", PPE_MAILBOX_IGU1_INT);\n\t\t}\n\t\tgoto REQUEST_IRQ_PPE_MAILBOX_IGU1_INT_FAIL;\n\t}\n\tdisable_irq(PPE_MAILBOX_IGU1_INT);\n\n\n\tret = ops->start(0);\n\tif ( ret ) {\n\t\tpr_err(\"ifx_pp32_start fail!\\n\");\n\t\tgoto PP32_START_FAIL;\n\t}\n\n\tport_cell.port_num = ATM_PORT_NUMBER;\n\tifx_mei_atm_showtime_check(&g_showtime, &port_cell, &g_xdata_addr);\n\tif ( g_showtime ) {\n\t\tatm_showtime_enter(&port_cell, &g_xdata_addr);\n\t} else {\n\t\tqsb_global_set();\n\t}\n\n\tvalidate_oam_htu_entry();\n\n\tifx_mei_atm_showtime_enter = atm_showtime_enter;\n\tifx_mei_atm_showtime_exit  = atm_showtime_exit;\n\n\tifx_atm_version(ops, ver_str);\n\tprintk(KERN_INFO \"%s\", ver_str);\n\tplatform_set_drvdata(pdev, ops);\n\tprintk(\"ifxmips_atm: ATM init succeed\\n\");\n\n\treturn 0;\n\nPP32_START_FAIL:\n\tfree_irq(PPE_MAILBOX_IGU1_INT, &g_atm_priv_data);\nREQUEST_IRQ_PPE_MAILBOX_IGU1_INT_FAIL:\nATM_DEV_REGISTER_FAIL:\n\twhile ( port_num-- > 0 )\n\t\tatm_dev_deregister(g_atm_priv_data.port[port_num].dev);\nINIT_PRIV_DATA_FAIL:\n\tclear_priv_data();\n\tprintk(\"ifxmips_atm: ATM init failed\\n\");\n\treturn ret;\n}\n\nstatic int ltq_atm_remove(struct platform_device *pdev)\n{\n\tint port_num;\n\tstruct ltq_atm_ops *ops = platform_get_drvdata(pdev);\n\n\tifx_mei_atm_showtime_enter = NULL;\n\tifx_mei_atm_showtime_exit  = NULL;\n\n\tinvalidate_oam_htu_entry();\n\n\tops->stop(0);\n\n\tfree_irq(PPE_MAILBOX_IGU1_INT, &g_atm_priv_data);\n\n\tfor ( port_num = 0; port_num < ATM_PORT_NUMBER; port_num++ )\n\t\tatm_dev_deregister(g_atm_priv_data.port[port_num].dev);\n\n\tops->shutdown();\n\n\tclear_priv_data();\n\n\treturn 0;\n}\n\nstatic struct platform_driver ltq_atm_driver = {\n\t.probe = ltq_atm_probe,\n\t.remove = ltq_atm_remove,\n\t.driver = {\n\t\t.name = \"atm\",\n\t\t.owner = THIS_MODULE,\n\t\t.of_match_table = ltq_atm_match,\n\t},\n};\n\nmodule_platform_driver(ltq_atm_driver);\n\nMODULE_LICENSE(\"Dual BSD/GPL\");\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-deu/Makefile",
    "content": "# Copyright (C) 2012 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n\ninclude $(TOPDIR)/rules.mk\ninclude $(INCLUDE_DIR)/kernel.mk\n\nPKG_NAME:=ltq-deu\nPKG_RELEASE:=$(AUTORELEASE)\n\nPKG_MAINTAINER:=John Crispin <john@phrozen.org>\nPKG_LICENSE:=GPL-2.0+\n\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine KernelPackage/ltq-deu-template\n  SECTION:=sys\n  CATEGORY:=Kernel modules\n  SUBMENU:=Cryptographic API modules\n  TITLE:=deu driver for $(1)\n  URL:=http://www.lantiq.com/\n  VARIANT:=$(1)\n  DEPENDS:=@TARGET_lantiq_$(2) +kmod-crypto-manager +kmod-crypto-des\n  FILES:=$(PKG_BUILD_DIR)/ltq_deu_$(1).ko\n  AUTOLOAD:=$(call AutoProbe,ltq_deu_$(1))\nendef\n\nKernelPackage/ltq-deu-danube=$(call KernelPackage/ltq-deu-template,danube,xway)\nKernelPackage/ltq-deu-ar9=$(call KernelPackage/ltq-deu-template,ar9,xway)\nKernelPackage/ltq-deu-vr9=$(call KernelPackage/ltq-deu-template,vr9,xrx200)\n\ndefine Build/Configure\nendef\n\ndefine Build/Compile\n\tcd $(LINUX_DIR); \\\n\t\tARCH=mips CROSS_COMPILE=\"$(KERNEL_CROSS)\" \\\n\t\t$(MAKE) BUILD_VARIANT=$(BUILD_VARIANT) M=$(PKG_BUILD_DIR) V=1 modules\nendef\n\n$(eval $(call KernelPackage,ltq-deu-danube))\n$(eval $(call KernelPackage,ltq-deu-ar9))\n$(eval $(call KernelPackage,ltq-deu-vr9))\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-deu/src/Makefile",
    "content": "ifeq ($(BUILD_VARIANT),danube)\n  CFLAGS_MODULE =-DCONFIG_DANUBE -DCONFIG_CRYPTO_DEV_DEU -DCONFIG_CRYPTO_DEV_SPEED_TEST -DCONFIG_CRYPTO_DEV_DES \\\n  \t\t-DCONFIG_CRYPTO_DEV_AES -DCONFIG_CRYPTO_DEV_SHA1 -DCONFIG_CRYPTO_DEV_MD5\n  obj-m = ltq_deu_danube.o\n  ltq_deu_danube-objs = ifxmips_deu.o ifxmips_deu_danube.o ifxmips_des.o ifxmips_aes.o ifxmips_sha1.o ifxmips_md5.o\nendif\n\nifeq ($(BUILD_VARIANT),ar9)\n  CFLAGS_MODULE = -DCONFIG_AR9 -DCONFIG_CRYPTO_DEV_DEU -DCONFIG_CRYPTO_DEV_SPEED_TEST -DCONFIG_CRYPTO_DEV_DES \\\n  \t\t-DCONFIG_CRYPTO_DEV_AES -DCONFIG_CRYPTO_DEV_SHA1 -DCONFIG_CRYPTO_DEV_MD5 \\\n\t\t-DCONFIG_CRYPTO_DEV_SHA1_HMAC -DCONFIG_CRYPTO_DEV_MD5_HMAC\n  obj-m = ltq_deu_ar9.o\n  ltq_deu_ar9-objs = ifxmips_deu.o ifxmips_deu_ar9.o ifxmips_des.o ifxmips_aes.o \\\n  \t\t\tifxmips_sha1.o ifxmips_md5.o ifxmips_sha1_hmac.o ifxmips_md5_hmac.o\nendif\n\nifeq ($(BUILD_VARIANT),vr9)\n  CFLAGS_MODULE = -DCONFIG_VR9 -DCONFIG_CRYPTO_DEV_DEU -DCONFIG_CRYPTO_DEV_SPEED_TEST -DCONFIG_CRYPTO_DEV_DES \\\n  \t\t-DCONFIG_CRYPTO_DEV_AES -DCONFIG_CRYPTO_DEV_SHA1 -DCONFIG_CRYPTO_DEV_MD5 \\\n\t\t-DCONFIG_CRYPTO_DEV_SHA1_HMAC -DCONFIG_CRYPTO_DEV_MD5_HMAC\n  obj-m = ltq_deu_vr9.o\n  ltq_deu_vr9-objs = ifxmips_deu.o ifxmips_deu_vr9.o ifxmips_des.o ifxmips_aes.o \\\n  \t\t\tifxmips_sha1.o ifxmips_md5.o ifxmips_sha1_hmac.o ifxmips_md5_hmac.o\nendif\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-deu/src/ifxmips_aes.c",
    "content": "/******************************************************************************\n**\n** FILE NAME    : ifxmips_aes.c\n** PROJECT      : IFX UEIP\n** MODULES      : DEU Module\n**\n** DATE         : September 8, 2009\n** AUTHOR       : Mohammad Firdaus\n** DESCRIPTION  : Data Encryption Unit Driver for AES Algorithm\n** COPYRIGHT    :       Copyright (c) 2009\n**                      Infineon Technologies AG\n**                      Am Campeon 1-12, 85579 Neubiberg, Germany\n**\n**    This program is free software; you can redistribute it and/or modify\n**    it under the terms of the GNU General Public License as published by\n**    the Free Software Foundation; either version 2 of the License, or\n**    (at your option) any later version.\n**\n** HISTORY\n** $Date        $Author             $Comment\n** 08,Sept 2009 Mohammad Firdaus    Initial UEIP release\n*******************************************************************************/\n/*!\n \\defgroup IFX_DEU IFX_DEU_DRIVERS\n \\ingroup API\n \\brief ifx DEU driver module\n*/\n\n/*!\n  \\file\tifxmips_aes.c\n  \\ingroup IFX_DEU\n  \\brief AES Encryption Driver main file\n*/\n\n/*!\n \\defgroup IFX_AES_FUNCTIONS IFX_AES_FUNCTIONS\n \\ingroup IFX_DEU\n \\brief IFX AES driver Functions \n*/\n\n\n/* Project Header Files */\n#if defined(CONFIG_MODVERSIONS)\n#define MODVERSIONS\n#include <linux/modeversions>\n#endif\n\n#include <linux/version.h>\n#include <linux/module.h>\n#include <linux/init.h>\n#include <linux/proc_fs.h>\n#include <linux/fs.h>\n#include <linux/types.h>\n#include <linux/errno.h>\n#include <linux/crypto.h>\n#include <linux/interrupt.h>\n#include <linux/delay.h>\n#include <asm/byteorder.h>\n#include <crypto/algapi.h>\n#include <crypto/b128ops.h>\n#include <crypto/gcm.h>\n#include <crypto/gf128mul.h>\n#include <crypto/scatterwalk.h>\n#include <crypto/xts.h>\n#include <crypto/internal/aead.h>\n#include <crypto/internal/hash.h>\n#include <crypto/internal/skcipher.h>\n\n#include \"ifxmips_deu.h\"\n\n#if defined(CONFIG_DANUBE) \n#include \"ifxmips_deu_danube.h\"\nextern int ifx_danube_pre_1_4;\n#elif defined(CONFIG_AR9)\n#include \"ifxmips_deu_ar9.h\"\n#elif defined(CONFIG_VR9) || defined(CONFIG_AR10)\n#include \"ifxmips_deu_vr9.h\"\n#else\n#error \"Unkown platform\"\n#endif\n\n/* DMA related header and variables */\n\nspinlock_t aes_lock;\n#define CRTCL_SECT_INIT        spin_lock_init(&aes_lock)\n#define CRTCL_SECT_START       spin_lock_irqsave(&aes_lock, flag)\n#define CRTCL_SECT_END         spin_unlock_irqrestore(&aes_lock, flag)\n\n/* Definition of constants */\n#define AES_START   IFX_AES_CON\n#define AES_MIN_KEY_SIZE    16\n#define AES_MAX_KEY_SIZE    32\n#define AES_BLOCK_SIZE      16\n#define AES_BLOCK_WORDS     4\n#define CTR_RFC3686_NONCE_SIZE    4\n#define CTR_RFC3686_IV_SIZE       8\n#define CTR_RFC3686_MIN_KEY_SIZE  (AES_MIN_KEY_SIZE + CTR_RFC3686_NONCE_SIZE)\n#define CTR_RFC3686_MAX_KEY_SIZE  (AES_MAX_KEY_SIZE + CTR_RFC3686_NONCE_SIZE)\n#define AES_CBCMAC_DBN_TEMP_SIZE  128\n\n#ifdef CRYPTO_DEBUG\nextern char debug_level;\n#define DPRINTF(level, format, args...) if (level < debug_level) printk(KERN_INFO \"[%s %s %d]: \" format, __FILE__, __func__, __LINE__, ##args);\n#else\n#define DPRINTF(level, format, args...)\n#endif /* CRYPTO_DEBUG */\n\n/* Function decleration */\nint aes_chip_init(void);\nu32 endian_swap(u32 input);\nu32 input_swap(u32 input);\nu32* memory_alignment(const u8 *arg, u32 *buff_alloc, int in_out, int nbytes);\nvoid aes_dma_memory_copy(u32 *outcopy, u32 *out_dma, u8 *out_arg, int nbytes);\nvoid des_dma_memory_copy(u32 *outcopy, u32 *out_dma, u8 *out_arg, int nbytes);\nint aes_memory_allocate(int value);\nint des_memory_allocate(int value);\nvoid memory_release(u32 *addr); \n\n\nextern void ifx_deu_aes (void *ctx_arg, uint8_t *out_arg, const uint8_t *in_arg,\n        uint8_t *iv_arg, size_t nbytes, int encdec, int mode);\n/* End of function decleration */\n\nstruct aes_ctx {\n    int key_length;\n    u8 buf[AES_MAX_KEY_SIZE];\n    u8 tweakkey[AES_MAX_KEY_SIZE];\n    u8 nonce[CTR_RFC3686_NONCE_SIZE];\n    u8 lastbuffer[4 * XTS_BLOCK_SIZE];\n    int use_tweak;\n    u32 byte_count;\n    u32 dbn;\n    int started;\n    u32 (*temp)[AES_BLOCK_WORDS];\n    u8 block[AES_BLOCK_SIZE];\n    u8 hash[AES_BLOCK_SIZE];\n    struct gf128mul_4k *gf128;\n};\n\nextern int disable_deudma;\nextern int disable_multiblock; \n\n/*! \\fn int aes_set_key (struct crypto_tfm *tfm, const uint8_t *in_key, unsigned int key_len)\n *  \\ingroup IFX_AES_FUNCTIONS \n *  \\brief sets the AES keys    \n *  \\param tfm linux crypto algo transform  \n *  \\param in_key input key  \n *  \\param key_len key lengths of 16, 24 and 32 bytes supported  \n *  \\return -EINVAL - bad key length, 0 - SUCCESS\n*/                                 \nint aes_set_key (struct crypto_tfm *tfm, const u8 *in_key, unsigned int key_len)\n{\n    struct aes_ctx *ctx = crypto_tfm_ctx(tfm);\n\n    //printk(\"set_key in %s\\n\", __FILE__);\n\n    //aes_chip_init();\n\n    if (key_len != 16 && key_len != 24 && key_len != 32) {\n        return -EINVAL;\n    }\n\n    ctx->key_length = key_len;\n    ctx->use_tweak = 0;\n    DPRINTF(0, \"ctx @%p, key_len %d, ctx->key_length %d\\n\", ctx, key_len, ctx->key_length);\n    memcpy ((u8 *) (ctx->buf), in_key, key_len);\n\n    return 0;\n}\n\n\n/*! \\fn int aes_set_key_skcipher (struct crypto_skcipher *tfm, const uint8_t *in_key, unsigned int key_len)\n *  \\ingroup IFX_AES_FUNCTIONS\n *  \\brief sets the AES keys for skcipher\n *  \\param tfm linux crypto skcipher\n *  \\param in_key input key\n *  \\param key_len key lengths of 16, 24 and 32 bytes supported\n *  \\return -EINVAL - bad key length, 0 - SUCCESS\n*/\nint aes_set_key_skcipher (struct crypto_skcipher *tfm, const u8 *in_key, unsigned int key_len)\n{\n    return aes_set_key(crypto_skcipher_tfm(tfm), in_key, key_len);\n}\n\n\n/*! \\fn void aes_set_key_skcipher (void *ctx_arg)\n *  \\ingroup IFX_AES_FUNCTIONS\n *  \\brief sets the AES key to the hardware, requires spinlock to be set by caller\n *  \\param ctx_arg crypto algo context  \n *  \\return\n*/\nvoid aes_set_key_hw (void *ctx_arg)\n{\n    /*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */\n    volatile struct aes_t *aes = (volatile struct aes_t *) AES_START;\n    struct aes_ctx *ctx = (struct aes_ctx *)ctx_arg;\n    u8 *in_key = ctx->buf;\n    int key_len = ctx->key_length;\n    /*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */\n\n    if (ctx->use_tweak) in_key = ctx->tweakkey;\n\n    /* 128, 192 or 256 bit key length */\n    aes->controlr.K = key_len / 8 - 2;\n        if (key_len == 128 / 8) {\n        aes->K3R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 0));\n        aes->K2R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 1));\n        aes->K1R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 2));\n        aes->K0R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 3));\n    }\n    else if (key_len == 192 / 8) {\n        aes->K5R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 0));\n        aes->K4R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 1));\n        aes->K3R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 2));\n        aes->K2R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 3));\n        aes->K1R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 4));\n        aes->K0R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 5));\n    }\n    else if (key_len == 256 / 8) {\n        aes->K7R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 0));\n        aes->K6R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 1));\n        aes->K5R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 2));\n        aes->K4R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 3));\n        aes->K3R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 4));\n        aes->K2R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 5));\n        aes->K1R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 6));\n        aes->K0R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 7));\n    }\n    else {\n        printk (KERN_ERR \"[%s %s %d]: Invalid key_len : %d\\n\", __FILE__, __func__, __LINE__, key_len);\n        return; //-EINVAL;\n    }\n\n    /* let HW pre-process DEcryption key in any case (even if\n       ENcryption is used). Key Valid (KV) bit is then only\n       checked in decryption routine! */\n    aes->controlr.PNK = 1;\n\n}\n\n\n/*! \\fn void ifx_deu_aes (void *ctx_arg, u8 *out_arg, const u8 *in_arg, u8 *iv_arg, size_t nbytes, int encdec, int mode)\n *  \\ingroup IFX_AES_FUNCTIONS\n *  \\brief main interface to AES hardware\n *  \\param ctx_arg crypto algo context  \n *  \\param out_arg output bytestream  \n *  \\param in_arg input bytestream   \n *  \\param iv_arg initialization vector  \n *  \\param nbytes length of bytestream  \n *  \\param encdec 1 for encrypt; 0 for decrypt  \n *  \\param mode operation mode such as ebc, cbc, ctr  \n *\n*/                                 \nvoid ifx_deu_aes (void *ctx_arg, u8 *out_arg, const u8 *in_arg,\n        u8 *iv_arg, size_t nbytes, int encdec, int mode)\n\n{\n    /*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */\n    volatile struct aes_t *aes = (volatile struct aes_t *) AES_START;\n    struct aes_ctx *ctx = (struct aes_ctx *)ctx_arg;\n    unsigned long flag;\n    /*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */\n    int i = 0;\n    int byte_cnt = nbytes; \n\n    CRTCL_SECT_START;\n\n    aes_set_key_hw (ctx_arg);\n\n    aes->controlr.E_D = !encdec;    //encryption\n    aes->controlr.O = mode; //0 ECB 1 CBC 2 OFB 3 CFB 4 CTR \n\n    //aes->controlr.F = 128; //default; only for CFB and OFB modes; change only for customer-specific apps\n    if (mode > 0) {\n        aes->IV3R = DEU_ENDIAN_SWAP(*(u32 *) iv_arg);\n        aes->IV2R = DEU_ENDIAN_SWAP(*((u32 *) iv_arg + 1));\n        aes->IV1R = DEU_ENDIAN_SWAP(*((u32 *) iv_arg + 2));\n        aes->IV0R = DEU_ENDIAN_SWAP(*((u32 *) iv_arg + 3));\n    };\n\n\n    i = 0;\n    while (byte_cnt >= 16) {\n\n        aes->ID3R = INPUT_ENDIAN_SWAP(*((u32 *) in_arg + (i * 4) + 0));\n        aes->ID2R = INPUT_ENDIAN_SWAP(*((u32 *) in_arg + (i * 4) + 1));\n        aes->ID1R = INPUT_ENDIAN_SWAP(*((u32 *) in_arg + (i * 4) + 2));\n        aes->ID0R = INPUT_ENDIAN_SWAP(*((u32 *) in_arg + (i * 4) + 3));    /* start crypto */\n        \n        while (aes->controlr.BUS) {\n            // this will not take long\n        }\n\n        *((volatile u32 *) out_arg + (i * 4) + 0) = aes->OD3R;\n        *((volatile u32 *) out_arg + (i * 4) + 1) = aes->OD2R;\n        *((volatile u32 *) out_arg + (i * 4) + 2) = aes->OD1R;\n        *((volatile u32 *) out_arg + (i * 4) + 3) = aes->OD0R;\n\n        i++;\n        byte_cnt -= 16;\n    }\n\n    /* To handle all non-aligned bytes (not aligned to 16B size) */\n    if (byte_cnt) {\n        u8 temparea[16] = {0,};\n\n        memcpy(temparea, ((u32 *) in_arg + (i * 4)), byte_cnt);\n\n        aes->ID3R = INPUT_ENDIAN_SWAP(*((u32 *) temparea + 0));\n        aes->ID2R = INPUT_ENDIAN_SWAP(*((u32 *) temparea + 1));\n        aes->ID1R = INPUT_ENDIAN_SWAP(*((u32 *) temparea + 2));\n        aes->ID0R = INPUT_ENDIAN_SWAP(*((u32 *) temparea + 3));    /* start crypto */\n\n        while (aes->controlr.BUS) {\n        }\n\n        *((volatile u32 *) temparea + 0) = aes->OD3R;\n        *((volatile u32 *) temparea + 1) = aes->OD2R;\n        *((volatile u32 *) temparea + 2) = aes->OD1R;\n        *((volatile u32 *) temparea + 3) = aes->OD0R;\n\n        memcpy(((u32 *) out_arg + (i * 4)), temparea, byte_cnt);\n    }\n\n    //tc.chen : copy iv_arg back\n    if (mode > 0) {\n        *((u32 *) iv_arg) = DEU_ENDIAN_SWAP(aes->IV3R);\n        *((u32 *) iv_arg + 1) = DEU_ENDIAN_SWAP(aes->IV2R);\n        *((u32 *) iv_arg + 2) = DEU_ENDIAN_SWAP(aes->IV1R);\n        *((u32 *) iv_arg + 3) = DEU_ENDIAN_SWAP(aes->IV0R);\n    }\n\n    CRTCL_SECT_END;\n}\n\n/*!\n *  \\fn int ctr_rfc3686_aes_set_key (struct crypto_tfm *tfm, const uint8_t *in_key, unsigned int key_len)\n *  \\ingroup IFX_AES_FUNCTIONS\n *  \\brief sets RFC3686 key   \n *  \\param tfm linux crypto algo transform  \n *  \\param in_key input key  \n *  \\param key_len key lengths of 20, 28 and 36 bytes supported; last 4 bytes is nonce \n *  \\return 0 - SUCCESS\n *          -EINVAL - bad key length\n*/                                 \nint ctr_rfc3686_aes_set_key (struct crypto_tfm *tfm, const uint8_t *in_key, unsigned int key_len)\n{\n    struct aes_ctx *ctx = crypto_tfm_ctx(tfm);\n\n    //printk(\"ctr_rfc3686_aes_set_key in %s\\n\", __FILE__);\n\n    memcpy(ctx->nonce, in_key + (key_len - CTR_RFC3686_NONCE_SIZE),\n           CTR_RFC3686_NONCE_SIZE);\n\n    key_len -= CTR_RFC3686_NONCE_SIZE; // remove 4 bytes of nonce\n\n    if (key_len != 16 && key_len != 24 && key_len != 32) {\n        return -EINVAL;\n    }\n\n    ctx->key_length = key_len;\n    ctx->use_tweak = 0;\n    \n    memcpy ((u8 *) (ctx->buf), in_key, key_len);\n\n    return 0;\n}\n\n/*!\n *  \\fn int ctr_rfc3686_aes_set_key_skcipher (struct crypto_skcipher *tfm, const uint8_t *in_key, unsigned int key_len)\n *  \\ingroup IFX_AES_FUNCTIONS\n *  \\brief sets RFC3686 key for skcipher\n *  \\param tfm linux crypto skcipher\n *  \\param in_key input key\n *  \\param key_len key lengths of 20, 28 and 36 bytes supported; last 4 bytes is nonce\n *  \\return 0 - SUCCESS\n *          -EINVAL - bad key length\n*/\nint ctr_rfc3686_aes_set_key_skcipher (struct crypto_skcipher *tfm, const uint8_t *in_key, unsigned int key_len)\n{\n    return ctr_rfc3686_aes_set_key(crypto_skcipher_tfm(tfm), in_key, key_len);\n}\n\n/*! \\fn void ifx_deu_aes (void *ctx_arg, u8 *out_arg, const u8 *in_arg, u8 *iv_arg, u32 nbytes, int encdec, int mode)\n *  \\ingroup IFX_AES_FUNCTIONS\n *  \\brief main interface with deu hardware in DMA mode\n *  \\param ctx_arg crypto algo context \n *  \\param out_arg output bytestream   \n *  \\param in_arg input bytestream   \n *  \\param iv_arg initialization vector  \n *  \\param nbytes length of bytestream  \n *  \\param encdec 1 for encrypt; 0 for decrypt  \n *  \\param mode operation mode such as ebc, cbc, ctr  \n*/\n\n\n//definitions from linux/include/crypto.h:\n//#define CRYPTO_TFM_MODE_ECB       0x00000001\n//#define CRYPTO_TFM_MODE_CBC       0x00000002\n//#define CRYPTO_TFM_MODE_CFB       0x00000004\n//#define CRYPTO_TFM_MODE_CTR       0x00000008\n//#define CRYPTO_TFM_MODE_OFB       0x00000010 // not even defined\n//but hardware definition: 0 ECB 1 CBC 2 OFB 3 CFB 4 CTR\n\n/*! \\fn void ifx_deu_aes_ecb (void *ctx, uint8_t *dst, const uint8_t *src, uint8_t *iv, size_t nbytes, int encdec, int inplace)\n *  \\ingroup IFX_AES_FUNCTIONS\n *  \\brief sets AES hardware to ECB mode   \n *  \\param ctx crypto algo context  \n *  \\param dst output bytestream  \n *  \\param src input bytestream  \n *  \\param iv initialization vector   \n *  \\param nbytes length of bytestream  \n *  \\param encdec 1 for encrypt; 0 for decrypt  \n *  \\param inplace not used  \n*/                                 \nvoid ifx_deu_aes_ecb (void *ctx, uint8_t *dst, const uint8_t *src,\n        uint8_t *iv, size_t nbytes, int encdec, int inplace)\n{\n     ifx_deu_aes (ctx, dst, src, NULL, nbytes, encdec, 0);\n}\n\n/*! \\fn void ifx_deu_aes_cbc (void *ctx, uint8_t *dst, const uint8_t *src, uint8_t *iv, size_t nbytes, int encdec, int inplace)\n *  \\ingroup IFX_AES_FUNCTIONS\n *  \\brief sets AES hardware to CBC mode   \n *  \\param ctx crypto algo context  \n *  \\param dst output bytestream  \n *  \\param src input bytestream  \n *  \\param iv initialization vector   \n *  \\param nbytes length of bytestream  \n *  \\param encdec 1 for encrypt; 0 for decrypt  \n *  \\param inplace not used  \n*/                                 \nvoid ifx_deu_aes_cbc (void *ctx, uint8_t *dst, const uint8_t *src,\n        uint8_t *iv, size_t nbytes, int encdec, int inplace)\n{\n     ifx_deu_aes (ctx, dst, src, iv, nbytes, encdec, 1);\n}\n\n/*! \\fn void ifx_deu_aes_ofb (void *ctx, uint8_t *dst, const uint8_t *src, uint8_t *iv, size_t nbytes, int encdec, int inplace)\n *  \\ingroup IFX_AES_FUNCTIONS\n *  \\brief sets AES hardware to OFB mode   \n *  \\param ctx crypto algo context  \n *  \\param dst output bytestream  \n *  \\param src input bytestream  \n *  \\param iv initialization vector   \n *  \\param nbytes length of bytestream  \n *  \\param encdec 1 for encrypt; 0 for decrypt  \n *  \\param inplace not used  \n*/                                 \nvoid ifx_deu_aes_ofb (void *ctx, uint8_t *dst, const uint8_t *src,\n        uint8_t *iv, size_t nbytes, int encdec, int inplace)\n{\n     ifx_deu_aes (ctx, dst, src, iv, nbytes, encdec, 2);\n}\n\n/*! \\fn void ifx_deu_aes_cfb (void *ctx, uint8_t *dst, const uint8_t *src, uint8_t *iv, size_t nbytes, int encdec, int inplace)\n *  \\ingroup IFX_AES_FUNCTIONS\n *  \\brief sets AES hardware to CFB mode   \n *  \\param ctx crypto algo context  \n *  \\param dst output bytestream  \n *  \\param src input bytestream  \n *  \\param iv initialization vector   \n *  \\param nbytes length of bytestream  \n *  \\param encdec 1 for encrypt; 0 for decrypt  \n *  \\param inplace not used  \n*/                                 \nvoid ifx_deu_aes_cfb (void *ctx, uint8_t *dst, const uint8_t *src,\n        uint8_t *iv, size_t nbytes, int encdec, int inplace)\n{\n     ifx_deu_aes (ctx, dst, src, iv, nbytes, encdec, 3);\n}\n\n/*! \\fn void ifx_deu_aes_ctr (void *ctx, uint8_t *dst, const uint8_t *src, uint8_t *iv, size_t nbytes, int encdec, int inplace)\n *  \\ingroup IFX_AES_FUNCTIONS\n *  \\brief sets AES hardware to CTR mode   \n *  \\param ctx crypto algo context  \n *  \\param dst output bytestream  \n *  \\param src input bytestream  \n *  \\param iv initialization vector   \n *  \\param nbytes length of bytestream  \n *  \\param encdec 1 for encrypt; 0 for decrypt  \n *  \\param inplace not used  \n*/                                 \nvoid ifx_deu_aes_ctr (void *ctx, uint8_t *dst, const uint8_t *src,\n        uint8_t *iv, size_t nbytes, int encdec, int inplace)\n{\n     ifx_deu_aes (ctx, dst, src, iv, nbytes, encdec, 4);\n}\n\n/*! \\fn void aes_encrypt (struct crypto_tfm *tfm, uint8_t *out, const uint8_t *in)\n *  \\ingroup IFX_AES_FUNCTIONS\n *  \\brief encrypt AES_BLOCK_SIZE of data\n *  \\param tfm linux crypto algo transform\n *  \\param out output bytestream\n *  \\param in input bytestream\n*/\nvoid aes_encrypt (struct crypto_tfm *tfm, uint8_t *out, const uint8_t *in)\n{\n    struct aes_ctx *ctx = crypto_tfm_ctx(tfm);\n    ifx_deu_aes (ctx, out, in, NULL, AES_BLOCK_SIZE,\n            CRYPTO_DIR_ENCRYPT, 0);\n}\n\n/*! \\fn void aes_decrypt (struct crypto_tfm *tfm, uint8_t *out, const uint8_t *in)\n *  \\ingroup IFX_AES_FUNCTIONS\n *  \\brief decrypt AES_BLOCK_SIZE of data\n *  \\param tfm linux crypto algo transform\n *  \\param out output bytestream\n *  \\param in input bytestream\n*/\nvoid aes_decrypt (struct crypto_tfm *tfm, uint8_t *out, const uint8_t *in)\n{\n    struct aes_ctx *ctx = crypto_tfm_ctx(tfm);\n    ifx_deu_aes (ctx, out, in, NULL, AES_BLOCK_SIZE,\n            CRYPTO_DIR_DECRYPT, 0);\n}\n\n/*\n * \\brief AES function mappings\n*/\nstruct crypto_alg ifxdeu_aes_alg = {\n    .cra_name       =   \"aes\",\n    .cra_driver_name    =   \"ifxdeu-aes\",\n    .cra_priority   =   300,\n    .cra_flags      =   CRYPTO_ALG_TYPE_CIPHER | CRYPTO_ALG_KERN_DRIVER_ONLY,\n    .cra_blocksize      =   AES_BLOCK_SIZE,\n    .cra_ctxsize        =   sizeof(struct aes_ctx),\n    .cra_module     =   THIS_MODULE,\n    .cra_list       =   LIST_HEAD_INIT(ifxdeu_aes_alg.cra_list),\n    .cra_u          =   {\n        .cipher = {\n            .cia_min_keysize    =   AES_MIN_KEY_SIZE,\n            .cia_max_keysize    =   AES_MAX_KEY_SIZE,\n            .cia_setkey     =   aes_set_key,\n            .cia_encrypt        =   aes_encrypt,\n            .cia_decrypt        =   aes_decrypt,\n        }\n    }\n};\n\n/*! \\fn int ecb_aes_encrypt(struct skcipher_req *req)\n *  \\ingroup IFX_AES_FUNCTIONS\n *  \\brief ECB AES encrypt using linux crypto skcipher\n *  \\param req skcipher request\n *  \\return err\n*/\nint ecb_aes_encrypt(struct skcipher_request *req)\n{\n    struct aes_ctx *ctx = crypto_tfm_ctx(req->base.tfm);\n    struct skcipher_walk walk;\n    int err;\n    unsigned int enc_bytes, nbytes;\n\n    err = skcipher_walk_virt(&walk, req, false);\n\n    while ((nbytes = enc_bytes = walk.nbytes)) {\n            enc_bytes -= (nbytes % AES_BLOCK_SIZE);\n        ifx_deu_aes_ecb(ctx, walk.dst.virt.addr, walk.src.virt.addr, \n                       NULL, enc_bytes, CRYPTO_DIR_ENCRYPT, 0);\n                nbytes &= AES_BLOCK_SIZE - 1;\n        err = skcipher_walk_done(&walk, nbytes);\n    }\n\n    return err;\n}\n\n/*! \\fn int ecb_aes_decrypt(struct skcipher_req *req)\n *  \\ingroup IFX_AES_FUNCTIONS\n *  \\brief ECB AES decrypt using linux crypto skcipher\n *  \\param req skcipher request\n *  \\return err\n*/\nint ecb_aes_decrypt(struct skcipher_request *req)\n{\n    struct aes_ctx *ctx = crypto_tfm_ctx(req->base.tfm);\n    struct skcipher_walk walk;\n    int err;\n    unsigned int dec_bytes, nbytes;\n\n    err = skcipher_walk_virt(&walk, req, false);\n\n    while ((nbytes = dec_bytes = walk.nbytes)) {\n            dec_bytes -= (nbytes % AES_BLOCK_SIZE);\n        ifx_deu_aes_ecb(ctx, walk.dst.virt.addr, walk.src.virt.addr, \n                       NULL, dec_bytes, CRYPTO_DIR_DECRYPT, 0);\n        nbytes &= AES_BLOCK_SIZE - 1;\n        err = skcipher_walk_done(&walk, nbytes);\n    }\n\n    return err;\n}\n\n/*\n * \\brief AES function mappings\n*/\nstruct skcipher_alg ifxdeu_ecb_aes_alg = {\n    .base.cra_name           =   \"ecb(aes)\",\n    .base.cra_driver_name    =   \"ifxdeu-ecb(aes)\",\n    .base.cra_priority       =   400,\n    .base.cra_flags          =   CRYPTO_ALG_TYPE_SKCIPHER | CRYPTO_ALG_KERN_DRIVER_ONLY,\n    .base.cra_blocksize      =   AES_BLOCK_SIZE,\n    .base.cra_ctxsize        =   sizeof(struct aes_ctx),\n    .base.cra_module         =   THIS_MODULE,\n    .base.cra_list           =   LIST_HEAD_INIT(ifxdeu_ecb_aes_alg.base.cra_list),\n    .min_keysize             =   AES_MIN_KEY_SIZE,\n    .max_keysize             =   AES_MAX_KEY_SIZE,\n    .setkey                  =   aes_set_key_skcipher,\n    .encrypt                 =   ecb_aes_encrypt,\n    .decrypt                 =   ecb_aes_decrypt,\n};\n\n/*! \\fn int ecb_aes_encrypt(struct skcipher_req *req)\n *  \\ingroup IFX_AES_FUNCTIONS\n *  \\brief CBC AES encrypt using linux crypto skcipher\n *  \\param req skcipher request\n *  \\return err\n*/\nint cbc_aes_encrypt(struct skcipher_request *req)\n{\n    struct aes_ctx *ctx = crypto_tfm_ctx(req->base.tfm);\n    struct skcipher_walk walk;\n    int err;\n    unsigned int enc_bytes, nbytes;\n\n    err = skcipher_walk_virt(&walk, req, false);\n\n    while ((nbytes = enc_bytes = walk.nbytes)) {\n            u8 *iv = walk.iv;\n            enc_bytes -= (nbytes % AES_BLOCK_SIZE);\n            ifx_deu_aes_cbc(ctx, walk.dst.virt.addr, walk.src.virt.addr, \n                       iv, enc_bytes, CRYPTO_DIR_ENCRYPT, 0);\n        nbytes &= AES_BLOCK_SIZE - 1;\n        err = skcipher_walk_done(&walk, nbytes);\n    }\n\n    return err;\n}\n\n/*! \\fn int cbc_aes_decrypt(struct skcipher_req *req)\n *  \\ingroup IFX_AES_FUNCTIONS\n *  \\brief CBC AES decrypt using linux crypto skcipher\n *  \\param req skcipher request\n *  \\return err\n*/\nint cbc_aes_decrypt(struct skcipher_request *req)\n{\n    struct aes_ctx *ctx = crypto_tfm_ctx(req->base.tfm);\n    struct skcipher_walk walk;\n    int err;\n    unsigned int dec_bytes, nbytes;\n\n    err = skcipher_walk_virt(&walk, req, false);\n\n    while ((nbytes = dec_bytes = walk.nbytes)) {\n        u8 *iv = walk.iv;\n            dec_bytes -= (nbytes % AES_BLOCK_SIZE);\n            ifx_deu_aes_cbc(ctx, walk.dst.virt.addr, walk.src.virt.addr, \n                       iv, dec_bytes, CRYPTO_DIR_DECRYPT, 0);\n        nbytes &= AES_BLOCK_SIZE - 1;\n        err = skcipher_walk_done(&walk, nbytes);\n    }\n\n    return err;\n}\n\n/*\n * \\brief AES function mappings\n*/\nstruct skcipher_alg ifxdeu_cbc_aes_alg = {\n    .base.cra_name           =   \"cbc(aes)\",\n    .base.cra_driver_name    =   \"ifxdeu-cbc(aes)\",\n    .base.cra_priority       =   400,\n    .base.cra_flags          =   CRYPTO_ALG_TYPE_SKCIPHER | CRYPTO_ALG_KERN_DRIVER_ONLY,\n    .base.cra_blocksize      =   AES_BLOCK_SIZE,\n    .base.cra_ctxsize        =   sizeof(struct aes_ctx),\n    .base.cra_module         =   THIS_MODULE,\n    .base.cra_list           =   LIST_HEAD_INIT(ifxdeu_cbc_aes_alg.base.cra_list),\n    .min_keysize             =   AES_MIN_KEY_SIZE,\n    .max_keysize             =   AES_MAX_KEY_SIZE,\n    .ivsize                  =   AES_BLOCK_SIZE,\n    .setkey                  =   aes_set_key_skcipher,\n    .encrypt                 =   cbc_aes_encrypt,\n    .decrypt                 =   cbc_aes_decrypt,\n};\n\n/*! \\fn void ifx_deu_aes_xts (void *ctx_arg, u8 *out_arg, const u8 *in_arg, u8 *iv_arg, size_t nbytes, int encdec)\n *  \\ingroup IFX_AES_FUNCTIONS\n *  \\brief main interface to AES hardware for XTS impl\n *  \\param ctx_arg crypto algo context\n *  \\param out_arg output bytestream\n *  \\param in_arg input bytestream\n *  \\param iv_arg initialization vector\n *  \\param nbytes length of bytestream\n *  \\param encdec 1 for encrypt; 0 for decrypt\n *\n*/\nvoid ifx_deu_aes_xts (void *ctx_arg, u8 *out_arg, const u8 *in_arg,\n        u8 *iv_arg, size_t nbytes, int encdec)\n{\n    /*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */\n    volatile struct aes_t *aes = (volatile struct aes_t *) AES_START;\n    struct aes_ctx *ctx = (struct aes_ctx *)ctx_arg;\n    unsigned long flag;\n    /*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */\n    u8 oldiv[16];\n    int i = 0;\n    int byte_cnt = nbytes; \n\n    CRTCL_SECT_START;\n\n    aes_set_key_hw (ctx_arg);\n\n    aes->controlr.E_D = !encdec;    //encryption\n    aes->controlr.O = 1; //0 ECB 1 CBC 2 OFB 3 CFB 4 CTR - CBC mode for xts\n\n    i = 0;\n    while (byte_cnt >= 16) {\n\n        if (!encdec) {\n            if (((byte_cnt % 16) > 0) && (byte_cnt < (2*XTS_BLOCK_SIZE))) {\n                 memcpy(oldiv, iv_arg, 16);\n                 gf128mul_x_ble((le128 *)iv_arg, (le128 *)iv_arg);\n            }\n            u128_xor((u128 *)((u32 *) in_arg + (i * 4) + 0), (u128 *)((u32 *) in_arg + (i * 4) + 0), (u128 *)iv_arg);\n        }\n\n        aes->IV3R = DEU_ENDIAN_SWAP(*(u32 *) iv_arg);\n        aes->IV2R = DEU_ENDIAN_SWAP(*((u32 *) iv_arg + 1));\n        aes->IV1R = DEU_ENDIAN_SWAP(*((u32 *) iv_arg + 2));\n        aes->IV0R = DEU_ENDIAN_SWAP(*((u32 *) iv_arg + 3));\n\n        aes->ID3R = INPUT_ENDIAN_SWAP(*((u32 *) in_arg + (i * 4) + 0));\n        aes->ID2R = INPUT_ENDIAN_SWAP(*((u32 *) in_arg + (i * 4) + 1));\n        aes->ID1R = INPUT_ENDIAN_SWAP(*((u32 *) in_arg + (i * 4) + 2));\n        aes->ID0R = INPUT_ENDIAN_SWAP(*((u32 *) in_arg + (i * 4) + 3));    /* start crypto */\n\n        while (aes->controlr.BUS) {\n            // this will not take long\n        }\n\n        *((volatile u32 *) out_arg + (i * 4) + 0) = aes->OD3R;\n        *((volatile u32 *) out_arg + (i * 4) + 1) = aes->OD2R;\n        *((volatile u32 *) out_arg + (i * 4) + 2) = aes->OD1R;\n        *((volatile u32 *) out_arg + (i * 4) + 3) = aes->OD0R;\n\n        if (encdec) {\n            u128_xor((u128 *)((volatile u32 *) out_arg + (i * 4) + 0), (u128 *)((volatile u32 *) out_arg + (i * 4) + 0), (u128 *)iv_arg);\n        }\n        gf128mul_x_ble((le128 *)iv_arg, (le128 *)iv_arg);\n        i++;\n        byte_cnt -= 16;\n    }\n\n    if (byte_cnt) {\n\tu8 state[XTS_BLOCK_SIZE] = {0,};\n\n        if (!encdec) memcpy(iv_arg, oldiv, 16);\n\n        aes->IV3R = DEU_ENDIAN_SWAP(*(u32 *) iv_arg);\n        aes->IV2R = DEU_ENDIAN_SWAP(*((u32 *) iv_arg + 1));\n        aes->IV1R = DEU_ENDIAN_SWAP(*((u32 *) iv_arg + 2));\n        aes->IV0R = DEU_ENDIAN_SWAP(*((u32 *) iv_arg + 3));\n\n        memcpy(state, ((u32 *) in_arg + (i * 4) + 0), byte_cnt);\n        memcpy((state + byte_cnt), (out_arg + ((i - 1) * 16) + byte_cnt), (XTS_BLOCK_SIZE - byte_cnt));\n        if (!encdec) {\n            u128_xor((u128 *)state, (u128 *)state, (u128 *)iv_arg);\n        }\n\n        aes->ID3R = INPUT_ENDIAN_SWAP(*((u32 *) state + 0));\n        aes->ID2R = INPUT_ENDIAN_SWAP(*((u32 *) state + 1));\n        aes->ID1R = INPUT_ENDIAN_SWAP(*((u32 *) state + 2));\n        aes->ID0R = INPUT_ENDIAN_SWAP(*((u32 *) state + 3));    /* start crypto */\n\n        memcpy(((u32 *) out_arg + (i * 4) + 0), ((u32 *) out_arg + ((i - 1) * 4) + 0), byte_cnt);\n\n        while (aes->controlr.BUS) {\n            // this will not take long\n        }\n\n        *((volatile u32 *) out_arg + ((i-1) * 4) + 0) = aes->OD3R;\n        *((volatile u32 *) out_arg + ((i-1) * 4) + 1) = aes->OD2R;\n        *((volatile u32 *) out_arg + ((i-1) * 4) + 2) = aes->OD1R;\n        *((volatile u32 *) out_arg + ((i-1) * 4) + 3) = aes->OD0R;\n\n        if (encdec) {\n            u128_xor((u128 *)((volatile u32 *) out_arg + ((i-1) * 4) + 0), (u128 *)((volatile u32 *) out_arg + ((i-1) * 4) + 0), (u128 *)iv_arg);\n        }\n    }\n\n    CRTCL_SECT_END;\n}\n\n/*! \\fn int xts_aes_encrypt(struct skcipher_req *req)\n *  \\ingroup IFX_AES_FUNCTIONS\n *  \\brief XTS AES encrypt using linux crypto skcipher\n *  \\param req skcipher request\n *  \\return err\n*/\nint xts_aes_encrypt(struct skcipher_request *req)\n{\n    struct aes_ctx *ctx = crypto_tfm_ctx(req->base.tfm);\n    struct skcipher_walk walk;\n    int err;\n    unsigned int enc_bytes, nbytes, processed;\n\n    err = skcipher_walk_virt(&walk, req, false);\n\n    if (req->cryptlen < XTS_BLOCK_SIZE)\n            return -EINVAL;\n\n    ctx->use_tweak = 1;\n    aes_encrypt(req->base.tfm, walk.iv, walk.iv);\n    ctx->use_tweak = 0;\n    processed = 0;\n\n    while ((nbytes = walk.nbytes) && (walk.nbytes >= (XTS_BLOCK_SIZE * 2)) ) {\n        u8 *iv = walk.iv;\n        if (nbytes == walk.total) {\n            enc_bytes = nbytes;\n        } else {\n            enc_bytes = nbytes & ~(XTS_BLOCK_SIZE - 1);\n            if ((req->cryptlen - processed - enc_bytes) < (XTS_BLOCK_SIZE)) {\n                if (enc_bytes > (2 * XTS_BLOCK_SIZE)) {\n                    enc_bytes -= XTS_BLOCK_SIZE;\n                } else {\n                    break;\n                }\n            }\n        }\n        ifx_deu_aes_xts(ctx, walk.dst.virt.addr, walk.src.virt.addr, \n                   iv, enc_bytes, CRYPTO_DIR_ENCRYPT);\n        err = skcipher_walk_done(&walk, nbytes - enc_bytes);\n        processed += enc_bytes;\n    }\n\n    if ((walk.nbytes)) {\n        u8 *iv = walk.iv;\n        nbytes = req->cryptlen - processed;\n        scatterwalk_map_and_copy(ctx->lastbuffer, req->src, (req->cryptlen - nbytes), nbytes, 0);\n        ifx_deu_aes_xts(ctx, ctx->lastbuffer, ctx->lastbuffer, \n                   iv, nbytes, CRYPTO_DIR_ENCRYPT);\n        scatterwalk_map_and_copy(ctx->lastbuffer, req->dst, (req->cryptlen - nbytes), nbytes, 1);\n        skcipher_request_complete(req, 0);\n    }\n\n    return err;\n}\n\n/*! \\fn int xts_aes_decrypt(struct skcipher_req *req)\n *  \\ingroup IFX_AES_FUNCTIONS\n *  \\brief XTS AES decrypt using linux crypto skcipher\n *  \\param req skcipher request\n *  \\return err\n*/\nint xts_aes_decrypt(struct skcipher_request *req)\n{\n    struct aes_ctx *ctx = crypto_tfm_ctx(req->base.tfm);\n    struct skcipher_walk walk;\n    int err;\n    unsigned int dec_bytes, nbytes, processed;\n\n    err = skcipher_walk_virt(&walk, req, false);\n\n    if (req->cryptlen < XTS_BLOCK_SIZE)\n            return -EINVAL;\n\n    ctx->use_tweak = 1;\n    aes_encrypt(req->base.tfm, walk.iv, walk.iv);\n    ctx->use_tweak = 0;\n    processed = 0;\n\n    while ((nbytes = walk.nbytes) && (walk.nbytes >= (XTS_BLOCK_SIZE * 2))) {\n        u8 *iv = walk.iv;\n        if (nbytes == walk.total) {\n            dec_bytes = nbytes;\n        } else {\n            dec_bytes = nbytes & ~(XTS_BLOCK_SIZE - 1);\n            if ((req->cryptlen - processed - dec_bytes) < (XTS_BLOCK_SIZE)) {\n                if (dec_bytes > (2 * XTS_BLOCK_SIZE)) {\n                    dec_bytes -= XTS_BLOCK_SIZE;\n                } else {\n                    break;\n                }\n            }\n        }\n        ifx_deu_aes_xts(ctx, walk.dst.virt.addr, walk.src.virt.addr, \n                   iv, dec_bytes, CRYPTO_DIR_DECRYPT);\n        err = skcipher_walk_done(&walk, nbytes - dec_bytes);\n        processed += dec_bytes;\n    }\n\n    if ((walk.nbytes)) {\n        u8 *iv = walk.iv;\n        nbytes = req->cryptlen - processed;\n        scatterwalk_map_and_copy(ctx->lastbuffer, req->src, (req->cryptlen - nbytes), nbytes, 0);\n        ifx_deu_aes_xts(ctx, ctx->lastbuffer, ctx->lastbuffer, \n                   iv, nbytes, CRYPTO_DIR_DECRYPT);\n        scatterwalk_map_and_copy(ctx->lastbuffer, req->dst, (req->cryptlen - nbytes), nbytes, 1);\n        skcipher_request_complete(req, 0);\n    }\n\n    return err;\n}\n\n/*! \\fn int xts_aes_set_key_skcipher (struct crypto_tfm *tfm, const uint8_t *in_key, unsigned int key_len)\n *  \\ingroup IFX_AES_FUNCTIONS\n *  \\brief sets the AES keys for XTS\n *  \\param tfm linux crypto algo transform\n *  \\param in_key input key\n *  \\param key_len key lengths of 16, 24 and 32 bytes supported\n *  \\return -EINVAL - bad key length, 0 - SUCCESS\n*/\nint xts_aes_set_key_skcipher (struct crypto_skcipher *tfm, const u8 *in_key, unsigned int key_len)\n{\n    struct aes_ctx *ctx = crypto_tfm_ctx(crypto_skcipher_tfm(tfm));\n    unsigned int keylen = (key_len / 2);\n\n    if (key_len % 2) return -EINVAL;\n\n    if (keylen != 16 && keylen != 24 && keylen != 32) {\n        return -EINVAL;\n    }\n\n    ctx->key_length = keylen;\n    ctx->use_tweak = 0;\n    DPRINTF(0, \"ctx @%p, key_len %d, ctx->key_length %d\\n\", ctx, key_len, ctx->key_length);\n    memcpy ((u8 *) (ctx->buf), in_key, keylen);\n    memcpy ((u8 *) (ctx->tweakkey), in_key + keylen, keylen);\n\n    return 0;\n}\n\n/*\n * \\brief AES function mappings\n*/\nstruct skcipher_alg ifxdeu_xts_aes_alg = {\n    .base.cra_name           =   \"xts(aes)\",\n    .base.cra_driver_name    =   \"ifxdeu-xts(aes)\",\n    .base.cra_priority       =   400,\n    .base.cra_flags          =   CRYPTO_ALG_TYPE_SKCIPHER | CRYPTO_ALG_KERN_DRIVER_ONLY,\n    .base.cra_blocksize      =   XTS_BLOCK_SIZE,\n    .base.cra_ctxsize        =   sizeof(struct aes_ctx),\n    .base.cra_module         =   THIS_MODULE,\n    .base.cra_list           =   LIST_HEAD_INIT(ifxdeu_xts_aes_alg.base.cra_list),\n    .min_keysize             =   AES_MIN_KEY_SIZE * 2,\n    .max_keysize             =   AES_MAX_KEY_SIZE * 2,\n    .ivsize                  =   XTS_BLOCK_SIZE,\n    .walksize                =   2 * XTS_BLOCK_SIZE,\n    .setkey                  =   xts_aes_set_key_skcipher,\n    .encrypt                 =   xts_aes_encrypt,\n    .decrypt                 =   xts_aes_decrypt,\n};\n\n/*! \\fn int ofb_aes_encrypt(struct skcipher_req *req)\n *  \\ingroup IFX_AES_FUNCTIONS\n *  \\brief OFB AES encrypt using linux crypto skcipher\n *  \\param req skcipher request\n *  \\return err\n*/\nint ofb_aes_encrypt(struct skcipher_request *req)\n{\n    struct aes_ctx *ctx = crypto_tfm_ctx(req->base.tfm);\n    struct skcipher_walk walk;\n    int err;\n    unsigned int enc_bytes, nbytes;\n\n    err = skcipher_walk_virt(&walk, req, false);\n\n    while ((nbytes = enc_bytes = walk.nbytes) && (walk.nbytes >= AES_BLOCK_SIZE)) {\n            enc_bytes -= (nbytes % AES_BLOCK_SIZE);\n            ifx_deu_aes_ofb(ctx, walk.dst.virt.addr, walk.src.virt.addr, \n                       walk.iv, enc_bytes, CRYPTO_DIR_ENCRYPT, 0);\n        nbytes &= AES_BLOCK_SIZE - 1;\n        err = skcipher_walk_done(&walk, nbytes);\n    }\n\n    /* to handle remaining bytes < AES_BLOCK_SIZE */\n    if (walk.nbytes) {\n\tifx_deu_aes_ofb(ctx, walk.dst.virt.addr, walk.src.virt.addr,\n\t\t\twalk.iv, walk.nbytes, CRYPTO_DIR_ENCRYPT, 0);\n\terr = skcipher_walk_done(&walk, 0);\n    }\n\n    return err;\n}\n\n/*! \\fn int ofb_aes_decrypt(struct skcipher_req *req)\n *  \\ingroup IFX_AES_FUNCTIONS\n *  \\brief OFB AES decrypt using linux crypto skcipher\n *  \\param req skcipher request\n *  \\return err\n*/\nint ofb_aes_decrypt(struct skcipher_request *req)\n{\n    struct aes_ctx *ctx = crypto_tfm_ctx(req->base.tfm);\n    struct skcipher_walk walk;\n    int err;\n    unsigned int dec_bytes, nbytes;\n\n    err = skcipher_walk_virt(&walk, req, false);\n\n    while ((nbytes = dec_bytes = walk.nbytes) && (walk.nbytes >= AES_BLOCK_SIZE)) {\n            dec_bytes -= (nbytes % AES_BLOCK_SIZE);\n            ifx_deu_aes_ofb(ctx, walk.dst.virt.addr, walk.src.virt.addr, \n                       walk.iv, dec_bytes, CRYPTO_DIR_DECRYPT, 0);\n        nbytes &= AES_BLOCK_SIZE - 1;\n        err = skcipher_walk_done(&walk, nbytes);\n    }\n\n    /* to handle remaining bytes < AES_BLOCK_SIZE */\n    if (walk.nbytes) {\n\tifx_deu_aes_ofb(ctx, walk.dst.virt.addr, walk.src.virt.addr,\n\t\t\twalk.iv, walk.nbytes, CRYPTO_DIR_DECRYPT, 0);\n\terr = skcipher_walk_done(&walk, 0);\n    }\n\n    return err;\n}\n\n/*\n * \\brief AES function mappings\n*/\nstruct skcipher_alg ifxdeu_ofb_aes_alg = {\n    .base.cra_name           =   \"ofb(aes)\",\n    .base.cra_driver_name    =   \"ifxdeu-ofb(aes)\",\n    .base.cra_priority       =   400,\n    .base.cra_flags          =   CRYPTO_ALG_TYPE_SKCIPHER | CRYPTO_ALG_KERN_DRIVER_ONLY,\n    .base.cra_blocksize      =   1,\n    .base.cra_ctxsize        =   sizeof(struct aes_ctx),\n    .base.cra_module         =   THIS_MODULE,\n    .base.cra_list           =   LIST_HEAD_INIT(ifxdeu_ofb_aes_alg.base.cra_list),\n    .min_keysize             =   AES_MIN_KEY_SIZE,\n    .max_keysize             =   AES_MAX_KEY_SIZE,\n    .ivsize                  =   AES_BLOCK_SIZE,\n    .chunksize               =   AES_BLOCK_SIZE,\n    .walksize                =   AES_BLOCK_SIZE,\n    .setkey                  =   aes_set_key_skcipher,\n    .encrypt                 =   ofb_aes_encrypt,\n    .decrypt                 =   ofb_aes_decrypt,\n};\n\n/*! \\fn int cfb_aes_encrypt(struct skcipher_req *req)\n *  \\ingroup IFX_AES_FUNCTIONS\n *  \\brief CFB AES encrypt using linux crypto skcipher\n *  \\param req skcipher request\n *  \\return err\n*/\nint cfb_aes_encrypt(struct skcipher_request *req)\n{\n    struct aes_ctx *ctx = crypto_tfm_ctx(req->base.tfm);\n    struct skcipher_walk walk;\n    int err;\n    unsigned int enc_bytes, nbytes;\n\n    err = skcipher_walk_virt(&walk, req, false);\n\n    while ((nbytes = enc_bytes = walk.nbytes) && (walk.nbytes >= AES_BLOCK_SIZE)) {\n            enc_bytes -= (nbytes % AES_BLOCK_SIZE);\n            ifx_deu_aes_cfb(ctx, walk.dst.virt.addr, walk.src.virt.addr, \n                       walk.iv, enc_bytes, CRYPTO_DIR_ENCRYPT, 0);\n        nbytes &= AES_BLOCK_SIZE - 1;\n        err = skcipher_walk_done(&walk, nbytes);\n    }\n\n    /* to handle remaining bytes < AES_BLOCK_SIZE */\n    if (walk.nbytes) {\n\tifx_deu_aes_cfb(ctx, walk.dst.virt.addr, walk.src.virt.addr,\n\t\t\twalk.iv, walk.nbytes, CRYPTO_DIR_ENCRYPT, 0);\n\terr = skcipher_walk_done(&walk, 0);\n    }\n\n    return err;\n}\n\n/*! \\fn int cfb_aes_decrypt(struct skcipher_req *req)\n *  \\ingroup IFX_AES_FUNCTIONS\n *  \\brief CFB AES decrypt using linux crypto skcipher\n *  \\param req skcipher request\n *  \\return err\n*/\nint cfb_aes_decrypt(struct skcipher_request *req)\n{\n    struct aes_ctx *ctx = crypto_tfm_ctx(req->base.tfm);\n    struct skcipher_walk walk;\n    int err;\n    unsigned int dec_bytes, nbytes;\n\n    err = skcipher_walk_virt(&walk, req, false);\n\n    while ((nbytes = dec_bytes = walk.nbytes) && (walk.nbytes >= AES_BLOCK_SIZE)) {\n            dec_bytes -= (nbytes % AES_BLOCK_SIZE);\n            ifx_deu_aes_cfb(ctx, walk.dst.virt.addr, walk.src.virt.addr, \n                       walk.iv, dec_bytes, CRYPTO_DIR_DECRYPT, 0);\n        nbytes &= AES_BLOCK_SIZE - 1;\n        err = skcipher_walk_done(&walk, nbytes);\n    }\n\n    /* to handle remaining bytes < AES_BLOCK_SIZE */\n    if (walk.nbytes) {\n\tifx_deu_aes_cfb(ctx, walk.dst.virt.addr, walk.src.virt.addr,\n\t\t\twalk.iv, walk.nbytes, CRYPTO_DIR_DECRYPT, 0);\n\terr = skcipher_walk_done(&walk, 0);\n    }\n\n    return err;\n}\n\n/*\n * \\brief AES function mappings\n*/\nstruct skcipher_alg ifxdeu_cfb_aes_alg = {\n    .base.cra_name           =   \"cfb(aes)\",\n    .base.cra_driver_name    =   \"ifxdeu-cfb(aes)\",\n    .base.cra_priority       =   400,\n    .base.cra_flags          =   CRYPTO_ALG_TYPE_SKCIPHER | CRYPTO_ALG_KERN_DRIVER_ONLY,\n    .base.cra_blocksize      =   1,\n    .base.cra_ctxsize        =   sizeof(struct aes_ctx),\n    .base.cra_module         =   THIS_MODULE,\n    .base.cra_list           =   LIST_HEAD_INIT(ifxdeu_cfb_aes_alg.base.cra_list),\n    .min_keysize             =   AES_MIN_KEY_SIZE,\n    .max_keysize             =   AES_MAX_KEY_SIZE,\n    .ivsize                  =   AES_BLOCK_SIZE,\n    .chunksize               =   AES_BLOCK_SIZE,\n    .walksize                =   AES_BLOCK_SIZE,\n    .setkey                  =   aes_set_key_skcipher,\n    .encrypt                 =   cfb_aes_encrypt,\n    .decrypt                 =   cfb_aes_decrypt,\n};\n\n/*! \\fn int ctr_basic_aes_encrypt(struct skcipher_req *req)\n *  \\ingroup IFX_AES_FUNCTIONS\n *  \\brief Counter mode AES encrypt using linux crypto skcipher\n *  \\param req skcipher request\n *  \\return err\n*/\nint ctr_basic_aes_encrypt(struct skcipher_request *req)\n{\n    struct aes_ctx *ctx = crypto_tfm_ctx(req->base.tfm);\n    struct skcipher_walk walk;\n    int err;\n    unsigned int enc_bytes, nbytes;\n\n    err = skcipher_walk_virt(&walk, req, false);\n\n    while ((nbytes = enc_bytes = walk.nbytes) && (walk.nbytes >= AES_BLOCK_SIZE)) {\n            enc_bytes -= (nbytes % AES_BLOCK_SIZE);\n            ifx_deu_aes_ctr(ctx, walk.dst.virt.addr, walk.src.virt.addr, \n                       walk.iv, enc_bytes, CRYPTO_DIR_ENCRYPT, 0);\n        nbytes &= AES_BLOCK_SIZE - 1;\n        err = skcipher_walk_done(&walk, nbytes);\n    }\n\n    /* to handle remaining bytes < AES_BLOCK_SIZE */\n    if (walk.nbytes) {\n        ifx_deu_aes_ctr(ctx, walk.dst.virt.addr, walk.src.virt.addr,\n                       walk.iv, walk.nbytes, CRYPTO_DIR_ENCRYPT, 0);\n        err = skcipher_walk_done(&walk, 0);\n    }\n\n    return err;\n}\n\n/*! \\fn int ctr_basic_aes_encrypt(struct skcipher_req *req)\n *  \\ingroup IFX_AES_FUNCTIONS\n *  \\brief Counter mode AES decrypt using linux crypto skcipher\n *  \\param req skcipher request\n *  \\return err\n*/\nint ctr_basic_aes_decrypt(struct skcipher_request *req)\n{\n    struct aes_ctx *ctx = crypto_tfm_ctx(req->base.tfm);\n    struct skcipher_walk walk;\n    int err;\n    unsigned int dec_bytes, nbytes;\n\n    err = skcipher_walk_virt(&walk, req, false);\n\n    while ((nbytes = dec_bytes = walk.nbytes) && (walk.nbytes >= AES_BLOCK_SIZE)) {\n            dec_bytes -= (nbytes % AES_BLOCK_SIZE);\n            ifx_deu_aes_ctr(ctx, walk.dst.virt.addr, walk.src.virt.addr, \n                       walk.iv, dec_bytes, CRYPTO_DIR_DECRYPT, 0);\n        nbytes &= AES_BLOCK_SIZE - 1;\n        err = skcipher_walk_done(&walk, nbytes);\n    }\n\n    /* to handle remaining bytes < AES_BLOCK_SIZE */\n    if (walk.nbytes) {\n        ifx_deu_aes_ctr(ctx, walk.dst.virt.addr, walk.src.virt.addr,\n                       walk.iv, walk.nbytes, CRYPTO_DIR_DECRYPT, 0);\n        err = skcipher_walk_done(&walk, 0);\n    }\n\n    return err;\n}\n\n/*\n * \\brief AES function mappings\n*/\nstruct skcipher_alg ifxdeu_ctr_basic_aes_alg = {\n    .base.cra_name           =   \"ctr(aes)\",\n    .base.cra_driver_name    =   \"ifxdeu-ctr(aes)\",\n    .base.cra_priority       =   400,\n    .base.cra_flags          =   CRYPTO_ALG_TYPE_SKCIPHER | CRYPTO_ALG_KERN_DRIVER_ONLY,\n    .base.cra_blocksize      =   1,\n    .base.cra_ctxsize        =   sizeof(struct aes_ctx),\n    .base.cra_module         =   THIS_MODULE,\n    .base.cra_list           =   LIST_HEAD_INIT(ifxdeu_ctr_basic_aes_alg.base.cra_list),\n    .min_keysize             =   AES_MIN_KEY_SIZE,\n    .max_keysize             =   AES_MAX_KEY_SIZE,\n    .ivsize                  =   AES_BLOCK_SIZE,\n    .walksize                =   AES_BLOCK_SIZE,\n    .setkey                  =   aes_set_key_skcipher,\n    .encrypt                 =   ctr_basic_aes_encrypt,\n    .decrypt                 =   ctr_basic_aes_decrypt,\n};\n\n/*! \\fn int ctr_rfc3686_aes_encrypt(struct skcipher_req *req)\n *  \\ingroup IFX_AES_FUNCTIONS\n *  \\brief Counter mode AES (rfc3686) encrypt using linux crypto skcipher\n *  \\param req skcipher request\n *  \\return err\n*/\nint ctr_rfc3686_aes_encrypt(struct skcipher_request *req)\n{\n    struct aes_ctx *ctx = crypto_tfm_ctx(req->base.tfm);\n    struct skcipher_walk walk;\n    unsigned int nbytes, enc_bytes;\n    int err;\n    u8 rfc3686_iv[16];\n\n    err = skcipher_walk_virt(&walk, req, false);\n    nbytes = walk.nbytes;\n\n    /* set up counter block */\n    memcpy(rfc3686_iv, ctx->nonce, CTR_RFC3686_NONCE_SIZE); \n    memcpy(rfc3686_iv + CTR_RFC3686_NONCE_SIZE, walk.iv, CTR_RFC3686_IV_SIZE);\n\n    /* initialize counter portion of counter block */\n    *(__be32 *)(rfc3686_iv + CTR_RFC3686_NONCE_SIZE + CTR_RFC3686_IV_SIZE) =\n        cpu_to_be32(1);\n\n    while ((nbytes = enc_bytes = walk.nbytes) && (walk.nbytes >= AES_BLOCK_SIZE)) {\n            enc_bytes -= (nbytes % AES_BLOCK_SIZE);\n            ifx_deu_aes_ctr(ctx, walk.dst.virt.addr, walk.src.virt.addr, \n                       rfc3686_iv, enc_bytes, CRYPTO_DIR_ENCRYPT, 0);\n        nbytes &= AES_BLOCK_SIZE - 1;\n        err = skcipher_walk_done(&walk, nbytes);\n    }\n\n    /* to handle remaining bytes < AES_BLOCK_SIZE */\n    if (walk.nbytes) {\n\tifx_deu_aes_ctr(ctx, walk.dst.virt.addr, walk.src.virt.addr,\n\t\t\trfc3686_iv, walk.nbytes, CRYPTO_DIR_ENCRYPT, 0);\n\terr = skcipher_walk_done(&walk, 0);\n    }\n\n    return err;\n}\n\n/*! \\fn int ctr_rfc3686_aes_decrypt(struct skcipher_req *req)\n *  \\ingroup IFX_AES_FUNCTIONS\n *  \\brief Counter mode AES (rfc3686) decrypt using linux crypto skcipher\n *  \\param req skcipher request\n *  \\return err\n*/\nint ctr_rfc3686_aes_decrypt(struct skcipher_request *req)\n{\n    struct aes_ctx *ctx = crypto_tfm_ctx(req->base.tfm);\n    struct skcipher_walk walk;\n    unsigned int nbytes, dec_bytes;\n    int err;\n    u8 rfc3686_iv[16];\n\n    err = skcipher_walk_virt(&walk, req, false);\n    nbytes = walk.nbytes;\n\n    /* set up counter block */\n    memcpy(rfc3686_iv, ctx->nonce, CTR_RFC3686_NONCE_SIZE); \n    memcpy(rfc3686_iv + CTR_RFC3686_NONCE_SIZE, walk.iv, CTR_RFC3686_IV_SIZE);\n\n    /* initialize counter portion of counter block */\n    *(__be32 *)(rfc3686_iv + CTR_RFC3686_NONCE_SIZE + CTR_RFC3686_IV_SIZE) =\n        cpu_to_be32(1);\n\n    while ((nbytes = dec_bytes = walk.nbytes) && (walk.nbytes >= AES_BLOCK_SIZE)) {\n            dec_bytes -= (nbytes % AES_BLOCK_SIZE);\n            ifx_deu_aes_ctr(ctx, walk.dst.virt.addr, walk.src.virt.addr, \n                       rfc3686_iv, dec_bytes, CRYPTO_DIR_DECRYPT, 0);\n        nbytes &= AES_BLOCK_SIZE - 1;\n        err = skcipher_walk_done(&walk, nbytes);\n    }\n\n    /* to handle remaining bytes < AES_BLOCK_SIZE */\n    if (walk.nbytes) {\n\tifx_deu_aes_ctr(ctx, walk.dst.virt.addr, walk.src.virt.addr,\n\t\t\trfc3686_iv, walk.nbytes, CRYPTO_DIR_DECRYPT, 0);\n\terr = skcipher_walk_done(&walk, 0);\n    }\n\n    return err;\n}\n\n/*\n * \\brief AES function mappings\n*/\nstruct skcipher_alg ifxdeu_ctr_rfc3686_aes_alg = {\n    .base.cra_name           =   \"rfc3686(ctr(aes))\",\n    .base.cra_driver_name    =   \"ifxdeu-ctr-rfc3686(aes)\",\n    .base.cra_priority       =   400,\n    .base.cra_flags          =   CRYPTO_ALG_TYPE_SKCIPHER | CRYPTO_ALG_KERN_DRIVER_ONLY,\n    .base.cra_blocksize      =   1,\n    .base.cra_ctxsize        =   sizeof(struct aes_ctx),\n    .base.cra_module         =   THIS_MODULE,\n    .base.cra_list           =   LIST_HEAD_INIT(ifxdeu_ctr_rfc3686_aes_alg.base.cra_list),\n    .min_keysize             =   CTR_RFC3686_MIN_KEY_SIZE,\n    .max_keysize             =   CTR_RFC3686_MAX_KEY_SIZE,\n    .ivsize                  =   CTR_RFC3686_IV_SIZE,\n    .walksize                =   AES_BLOCK_SIZE,\n    .setkey                  =   ctr_rfc3686_aes_set_key_skcipher,\n    .encrypt                 =   ctr_rfc3686_aes_encrypt,\n    .decrypt                 =   ctr_rfc3686_aes_decrypt,\n};\n\nstatic int aes_cbcmac_final_impl(struct shash_desc *desc, u8 *out, bool hash_final);\n\n/*! \\fn static void aes_cbcmac_transform(struct shash_desc *desc, u8 const *in)\n *  \\ingroup IFX_aes_cbcmac_FUNCTIONS\n *  \\brief save input block to context\n *  \\param desc linux crypto shash descriptor\n *  \\param in 16-byte block of input\n*/\nstatic void aes_cbcmac_transform(struct shash_desc *desc, u8 const *in)\n{\n    struct aes_ctx *mctx = crypto_shash_ctx(desc->tfm);\n\n    if ( ((mctx->dbn)+1) > AES_CBCMAC_DBN_TEMP_SIZE )\n    {\n        //printk(\"aes_cbcmac_DBN_TEMP_SIZE exceeded\\n\");\n        aes_cbcmac_final_impl(desc, (u8 *)mctx->hash, false);\n    }\n\n    memcpy(&mctx->temp[mctx->dbn], in, 16); //dbn workaround\n    mctx->dbn += 1;\n}\n\n/*! \\fn int aes_cbcmac_setkey(struct crypto_shash *tfm, const u8 *key, unsigned int keylen)\n *  \\ingroup IFX_aes_cbcmac_FUNCTIONS\n *  \\brief sets cbcmac aes key\n *  \\param tfm linux crypto shash transform\n *  \\param key input key\n *  \\param keylen key\n*/\nstatic int aes_cbcmac_setkey(struct crypto_shash *tfm, const u8 *key, unsigned int keylen)\n{\n    return aes_set_key(crypto_shash_tfm(tfm), key, keylen);\n\n    return 0;\n}\n\n/*! \\fn void aes_cbcmac_init(struct shash_desc *desc)\n *  \\ingroup IFX_aes_cbcmac_FUNCTIONS\n *  \\brief initialize md5 hmac context\n *  \\param desc linux crypto shash descriptor\n*/\nstatic int aes_cbcmac_init(struct shash_desc *desc)\n{\n\n    struct aes_ctx *mctx = crypto_shash_ctx(desc->tfm);\n\n    mctx->dbn = 0; //dbn workaround\n    mctx->started = 0;\n    mctx->byte_count = 0;\n    memset(mctx->hash, 0, AES_BLOCK_SIZE);\n\n    return 0;\n}\n\n/*! \\fn void aes_cbcmac_update(struct shash_desc *desc, const u8 *data, unsigned int len)\n *  \\ingroup IFX_aes_cbcmac_FUNCTIONS\n *  \\brief on-the-fly cbcmac aes computation\n *  \\param desc linux crypto shash descriptor\n *  \\param data input data\n *  \\param len size of input data\n*/\nstatic int aes_cbcmac_update(struct shash_desc *desc, const u8 *data, unsigned int len)\n{\n    struct aes_ctx *mctx = crypto_shash_ctx(desc->tfm);\n    const u32 avail = sizeof(mctx->block) - (mctx->byte_count & 0x0f);\n\n    mctx->byte_count += len;\n\n    if (avail > len) {\n        memcpy((char *)mctx->block + (sizeof(mctx->block) - avail),\n               data, len);\n        return 0;\n    }\n\n    memcpy((char *)mctx->block + (sizeof(mctx->block) - avail),\n           data, avail);\n\n    aes_cbcmac_transform(desc, mctx->block);\n    data += avail;\n    len -= avail;\n\n    while (len >= sizeof(mctx->block)) {\n        memcpy(mctx->block, data, sizeof(mctx->block));\n        aes_cbcmac_transform(desc, mctx->block);\n        data += sizeof(mctx->block);\n        len -= sizeof(mctx->block);\n    }\n\n    memcpy(mctx->block, data, len);\n    return 0;\n}\n\n/*! \\fn static int aes_cbcmac_final_impl(struct shash_desc *desc, u8 *out, bool hash_final)\n *  \\ingroup IFX_aes_cbcmac_FUNCTIONS\n *  \\brief compute final or intermediate md5 hmac value\n *  \\param desc linux crypto shash descriptor\n *  \\param out final cbcmac aes output value\n *  \\param in finalize or intermediate processing\n*/\nstatic int aes_cbcmac_final_impl(struct shash_desc *desc, u8 *out, bool hash_final)\n{\n    struct aes_ctx *mctx = crypto_shash_ctx(desc->tfm);\n    const unsigned int offset = mctx->byte_count & 0x0f;\n    char *p = (char *)mctx->block + offset;\n    volatile struct aes_t *aes = (volatile struct aes_t *) AES_START;\n    unsigned long flag;\n    int i = 0;\n    int dbn;\n    u32 *in = mctx->temp[0];\n\n    CRTCL_SECT_START;\n\n    aes_set_key_hw (mctx);\n\n    aes->controlr.E_D = !CRYPTO_DIR_ENCRYPT;    //encryption\n    aes->controlr.O = 1; //0 ECB 1 CBC 2 OFB 3 CFB 4 CTR \n\n    //aes->controlr.F = 128; //default; only for CFB and OFB modes; change only for customer-specific apps\n\n    //printk(\"\\ndbn = %d\\n\", mctx->dbn);\n\n    if (mctx->started) {\n        aes->IV3R = DEU_ENDIAN_SWAP(*(u32 *) mctx->hash);\n        aes->IV2R = DEU_ENDIAN_SWAP(*((u32 *) mctx->hash + 1));\n        aes->IV1R = DEU_ENDIAN_SWAP(*((u32 *) mctx->hash + 2));\n        aes->IV0R = DEU_ENDIAN_SWAP(*((u32 *) mctx->hash + 3));\n    } else {\n        mctx->started = 1;\n        aes->IV3R = 0;\n        aes->IV2R = 0;\n        aes->IV1R = 0;\n        aes->IV0R = 0;\n    }\n\n    i = 0;\n    for (dbn = 0; dbn < mctx->dbn; dbn++)\n    {\n        aes->ID3R = INPUT_ENDIAN_SWAP(*((u32 *) in + (i * 4) + 0));\n        aes->ID2R = INPUT_ENDIAN_SWAP(*((u32 *) in + (i * 4) + 1));\n        aes->ID1R = INPUT_ENDIAN_SWAP(*((u32 *) in + (i * 4) + 2));\n        aes->ID0R = INPUT_ENDIAN_SWAP(*((u32 *) in + (i * 4) + 3));    /* start crypto */\n\n        while (aes->controlr.BUS) {\n            // this will not take long\n        }\n\n        in += 4;\n    }\n\n    *((u32 *) mctx->hash) = DEU_ENDIAN_SWAP(aes->IV3R);\n    *((u32 *) mctx->hash + 1) = DEU_ENDIAN_SWAP(aes->IV2R);\n    *((u32 *) mctx->hash + 2) = DEU_ENDIAN_SWAP(aes->IV1R);\n    *((u32 *) mctx->hash + 3) = DEU_ENDIAN_SWAP(aes->IV0R);\n\n    if (hash_final && offset) {\n        aes->controlr.O = 0; //0 ECB 1 CBC 2 OFB 3 CFB 4 CTR \n        crypto_xor(mctx->block, mctx->hash, offset);\n\n        memcpy(p, mctx->hash + offset, (AES_BLOCK_SIZE - offset));\n\n        aes->ID3R = INPUT_ENDIAN_SWAP(*((u32 *) mctx->block + 0));\n        aes->ID2R = INPUT_ENDIAN_SWAP(*((u32 *) mctx->block + 1));\n        aes->ID1R = INPUT_ENDIAN_SWAP(*((u32 *) mctx->block + 2));\n        aes->ID0R = INPUT_ENDIAN_SWAP(*((u32 *) mctx->block + 3));    /* start crypto */\n\n        while (aes->controlr.BUS) {\n            // this will not take long\n        }\n\n        *((u32 *) mctx->hash) = DEU_ENDIAN_SWAP(aes->OD3R);\n        *((u32 *) mctx->hash + 1) = DEU_ENDIAN_SWAP(aes->OD2R);\n        *((u32 *) mctx->hash + 2) = DEU_ENDIAN_SWAP(aes->OD1R);\n        *((u32 *) mctx->hash + 3) = DEU_ENDIAN_SWAP(aes->OD0R);\n    }\n\n    CRTCL_SECT_END;\n\n    if (hash_final) {\n        memcpy(out, mctx->hash, AES_BLOCK_SIZE);\n        /* reset the context after we finish with the hash */\n        aes_cbcmac_init(desc);\n    } else {\n        mctx->dbn = 0;\n    }\n    return 0;\n}\n\n/*! \\fn static int aes_cbcmac_final(struct crypto_tfm *tfm, u8 *out)\n *  \\ingroup IFX_aes_cbcmac_FUNCTIONS\n *  \\brief call aes_cbcmac_final_impl with hash_final true\n *  \\param tfm linux crypto algo transform\n *  \\param out final md5 hmac output value\n*/\nstatic int aes_cbcmac_final(struct shash_desc *desc, u8 *out)\n{\n    return aes_cbcmac_final_impl(desc, out, true);\n}\n\n/*! \\fn void aes_cbcmac_init_tfm(struct crypto_tfm *tfm)\n *  \\ingroup IFX_aes_cbcmac_FUNCTIONS\n *  \\brief initialize pointers in aes_ctx\n *  \\param tfm linux crypto shash transform\n*/\nstatic int aes_cbcmac_init_tfm(struct crypto_tfm *tfm)\n{\n    struct aes_ctx *mctx = crypto_tfm_ctx(tfm);\n    mctx->temp = kzalloc(AES_BLOCK_SIZE * AES_CBCMAC_DBN_TEMP_SIZE, GFP_KERNEL);\n    if (IS_ERR(mctx->temp)) return PTR_ERR(mctx->temp);\n\n    return 0;\n}\n\n/*! \\fn void aes_cbcmac_exit_tfm(struct crypto_tfm *tfm)\n *  \\ingroup IFX_aes_cbcmac_FUNCTIONS\n *  \\brief free pointers in aes_ctx\n *  \\param tfm linux crypto shash transform\n*/\nstatic void aes_cbcmac_exit_tfm(struct crypto_tfm *tfm)\n{\n    struct aes_ctx *mctx = crypto_tfm_ctx(tfm);\n    kfree(mctx->temp);\n}\n\n/*\n * \\brief aes_cbcmac function mappings\n*/\nstatic struct shash_alg ifxdeu_cbcmac_aes_alg = {\n    .digestsize         =       AES_BLOCK_SIZE,\n    .init               =       aes_cbcmac_init,\n    .update             =       aes_cbcmac_update,\n    .final              =       aes_cbcmac_final,\n    .setkey             =       aes_cbcmac_setkey,\n    .descsize           =       sizeof(struct aes_ctx),\n    .base               =       {\n        .cra_name       =       \"cbcmac(aes)\",\n        .cra_driver_name=       \"ifxdeu-cbcmac(aes)\",\n        .cra_priority   =       400,\n        .cra_ctxsize    =       sizeof(struct aes_ctx),\n        .cra_flags      =       CRYPTO_ALG_TYPE_HASH | CRYPTO_ALG_KERN_DRIVER_ONLY,\n        .cra_blocksize  =       1,\n        .cra_module     =       THIS_MODULE,\n        .cra_init       =       aes_cbcmac_init_tfm,\n        .cra_exit       =       aes_cbcmac_exit_tfm,\n        }\n};\n\n/*! \\fn int aes_set_key_aead (struct crypto_aead *aead, const uint8_t *in_key, unsigned int key_len)\n *  \\ingroup IFX_AES_FUNCTIONS\n *  \\brief sets the AES keys for aead gcm\n *  \\param aead linux crypto aead\n *  \\param in_key input key\n *  \\param key_len key lengths of 16, 24 and 32 bytes supported\n *  \\return -EINVAL - bad key length, 0 - SUCCESS\n*/\nint aes_set_key_aead (struct crypto_aead *aead, const u8 *in_key, unsigned int key_len)\n{\n    struct aes_ctx *ctx = crypto_aead_ctx(aead);\n    int err;\n\n    err = aes_set_key(&aead->base, in_key, key_len);\n    if (err) return err;\n\n    memset(ctx->block, 0, sizeof(ctx->block));\n    memset(ctx->lastbuffer, 0, AES_BLOCK_SIZE);\n    ifx_deu_aes_ctr(ctx, ctx->block, ctx->block,\n                       ctx->lastbuffer, AES_BLOCK_SIZE, CRYPTO_DIR_ENCRYPT, 0);\n    if (ctx->gf128) gf128mul_free_4k(ctx->gf128);\n    ctx->gf128 = gf128mul_init_4k_lle((be128 *)ctx->block);\n\n    return err;\n}\n\n/*! \\fn int gcm_aes_setauthsize (struct crypto_aead *aead, unsigned int authsize)\n *  \\ingroup IFX_AES_FUNCTIONS\n *  \\brief sets the AES keys for aead gcm\n *  \\param aead linux crypto aead\n *  \\param in_key input authsize\n *  \\return -EINVAL - bad authsize length, 0 - SUCCESS\n*/\nint gcm_aes_setauthsize (struct crypto_aead *aead, unsigned int authsize)\n{\n    return crypto_gcm_check_authsize(authsize);\n}\n\n/*! \\fn int gcm_aes_encrypt(struct aead_request *req)\n *  \\ingroup IFX_AES_FUNCTIONS\n *  \\brief GCM AES encrypt using linux crypto aead\n *  \\param req aead request\n *  \\return err\n*/\nint gcm_aes_encrypt(struct aead_request *req)\n{\n    struct aes_ctx *ctx = crypto_tfm_ctx(req->base.tfm);\n    struct skcipher_walk walk;\n    struct skcipher_request request;\n    int err;\n    unsigned int enc_bytes, nbytes;\n    be128 lengths;\n    u8 iv[AES_BLOCK_SIZE];\n\n    lengths.a = cpu_to_be64(req->assoclen * 8);\n    lengths.b = cpu_to_be64(req->cryptlen * 8);\n\n    memset(ctx->hash, 0, sizeof(ctx->hash));\n    memset(ctx->block, 0, sizeof(ctx->block));\n    memcpy(iv, req->iv, GCM_AES_IV_SIZE);\n    *(__be32 *)((void *)iv + GCM_AES_IV_SIZE) = cpu_to_be32(1);\n    ifx_deu_aes_ctr(ctx, ctx->block, ctx->block,\n                       iv, 16, CRYPTO_DIR_ENCRYPT, 0);\n\n    request.cryptlen = req->cryptlen + req->assoclen;\n    request.src = req->src;\n    request.dst = req->dst;\n    request.base = req->base;\n\n    crypto_skcipher_alg(crypto_skcipher_reqtfm(&request))->walksize = AES_BLOCK_SIZE;\n\n    if (req->assoclen && (req->assoclen < AES_BLOCK_SIZE))\n        crypto_skcipher_alg(crypto_skcipher_reqtfm(&request))->walksize = req->assoclen;\n\n    err = skcipher_walk_virt(&walk, &request, false);\n\n    //process assoc data if available\n    if (req->assoclen > 0) {\n        unsigned int assoc_remain, ghashlen;\n\n        assoc_remain = req->assoclen;\n        ghashlen = min(req->assoclen, walk.nbytes);\n        while ((nbytes = enc_bytes = ghashlen) && (ghashlen >= AES_BLOCK_SIZE)) {\n            u8 *temp;\n            if (nbytes > req->assoclen) nbytes = enc_bytes = req->assoclen;\n            enc_bytes -= (nbytes % AES_BLOCK_SIZE);\n            memcpy(walk.dst.virt.addr, walk.src.virt.addr, enc_bytes);\n            assoc_remain -= enc_bytes;\n            temp = walk.dst.virt.addr;\n            while (enc_bytes > 0) {\n                u128_xor((u128 *)ctx->hash, (u128 *)ctx->hash, (u128 *)temp);\n                gf128mul_4k_lle((be128 *)ctx->hash, ctx->gf128);\n                enc_bytes -= AES_BLOCK_SIZE;\n                temp += 16;\n            }\n            if (assoc_remain < AES_BLOCK_SIZE) walk.stride = assoc_remain;\n            if (assoc_remain == 0) walk.stride = AES_BLOCK_SIZE;\n            enc_bytes = nbytes - (nbytes % AES_BLOCK_SIZE);\n            err = skcipher_walk_done(&walk, (walk.nbytes - enc_bytes));\n            ghashlen = min(assoc_remain, walk.nbytes);\n        }\n\n        if ((enc_bytes = ghashlen)) {\n            memcpy(ctx->lastbuffer, walk.src.virt.addr, enc_bytes);\n            memset(ctx->lastbuffer + enc_bytes, 0, (AES_BLOCK_SIZE - enc_bytes));\n            memcpy(walk.dst.virt.addr, walk.src.virt.addr, ghashlen);\n            u128_xor((u128 *)ctx->hash, (u128 *)ctx->hash, (u128 *)ctx->lastbuffer);\n            gf128mul_4k_lle((be128 *)ctx->hash, ctx->gf128);\n            walk.stride = AES_BLOCK_SIZE;\n            err = skcipher_walk_done(&walk, (walk.nbytes - ghashlen));\n        }\n    }\n\n    //crypt and hash\n    while ((nbytes = enc_bytes = walk.nbytes) && (walk.nbytes >= AES_BLOCK_SIZE)) {\n        u8 *temp;\n        enc_bytes -= (nbytes % AES_BLOCK_SIZE);\n        ifx_deu_aes_ctr(ctx, walk.dst.virt.addr, walk.src.virt.addr,\n                       iv, enc_bytes, CRYPTO_DIR_ENCRYPT, 0);\n        nbytes &= AES_BLOCK_SIZE - 1;\n        temp = walk.dst.virt.addr;\n        while (enc_bytes) {\n            u128_xor((u128 *)ctx->hash, (u128 *)ctx->hash, (u128 *)temp);\n            gf128mul_4k_lle((be128 *)ctx->hash, ctx->gf128);\n            enc_bytes -= AES_BLOCK_SIZE;\n            temp += 16;\n        }\n        err = skcipher_walk_done(&walk, nbytes);\n    }\n\n    /* crypt and hash remaining bytes < AES_BLOCK_SIZE */\n    if ((enc_bytes = walk.nbytes)) {\n        ifx_deu_aes_ctr(ctx, walk.dst.virt.addr, walk.src.virt.addr,\n                       iv, walk.nbytes, CRYPTO_DIR_ENCRYPT, 0);\n        memcpy(ctx->lastbuffer, walk.dst.virt.addr, enc_bytes);\n        memset(ctx->lastbuffer + enc_bytes, 0, (AES_BLOCK_SIZE - enc_bytes));\n        u128_xor((u128 *)ctx->hash, (u128 *)ctx->hash, (u128 *)ctx->lastbuffer);\n        gf128mul_4k_lle((be128 *)ctx->hash, ctx->gf128);\n        err = skcipher_walk_done(&walk, 0);\n    }\n\n    //finalize and copy hash\n    u128_xor((u128 *)ctx->hash, (u128 *)ctx->hash, (u128 *)&lengths);\n    gf128mul_4k_lle((be128 *)ctx->hash, ctx->gf128);\n    u128_xor((u128 *)ctx->hash, (u128 *)ctx->hash, (u128 *)ctx->block);\n    scatterwalk_map_and_copy(ctx->hash, req->dst, req->cryptlen + req->assoclen, crypto_aead_authsize(crypto_aead_reqtfm(req)), 1);\n\n    aead_request_complete(req, 0);\n\n    return err;\n}\n\n/*! \\fn int gcm_aes_decrypt(struct aead_request *req)\n *  \\ingroup IFX_AES_FUNCTIONS\n *  \\brief GCM AES decrypt using linux crypto aead\n *  \\param req aead request\n *  \\return err\n*/\nint gcm_aes_decrypt(struct aead_request *req)\n{\n    struct aes_ctx *ctx = crypto_tfm_ctx(req->base.tfm);\n    struct skcipher_walk walk;\n    struct skcipher_request request;\n    int err;\n    unsigned int dec_bytes, nbytes, authsize;\n    be128 lengths;\n    u8 iv[AES_BLOCK_SIZE];\n\n    authsize = crypto_aead_authsize(crypto_aead_reqtfm(req));\n\n    lengths.a = cpu_to_be64(req->assoclen * 8);\n    lengths.b = cpu_to_be64((req->cryptlen - authsize) * 8);\n\n    memset(ctx->hash, 0, sizeof(ctx->hash));\n    memset(ctx->block, 0, sizeof(ctx->block));\n    memcpy(iv, req->iv, GCM_AES_IV_SIZE);\n    *(__be32 *)((void *)iv + GCM_AES_IV_SIZE) = cpu_to_be32(1);\n    ifx_deu_aes_ctr(ctx, ctx->block, ctx->block,\n                       iv, 16, CRYPTO_DIR_ENCRYPT, 0);\n\n    request.cryptlen = req->cryptlen + req->assoclen - authsize;\n    request.src = req->src;\n    request.dst = req->dst;\n    request.base = req->base;\n    crypto_skcipher_alg(crypto_skcipher_reqtfm(&request))->walksize = AES_BLOCK_SIZE;\n\n    if (req->assoclen && (req->assoclen < AES_BLOCK_SIZE))\n        crypto_skcipher_alg(crypto_skcipher_reqtfm(&request))->walksize = req->assoclen;\n\n    err = skcipher_walk_virt(&walk, &request, false);\n\n    //process assoc data if available\n    if (req->assoclen > 0) {\n        unsigned int assoc_remain, ghashlen;\n\n        assoc_remain = req->assoclen;\n        ghashlen = min(req->assoclen, walk.nbytes);\n        while ((nbytes = dec_bytes = ghashlen) && (ghashlen >= AES_BLOCK_SIZE)) {\n            u8 *temp;\n            if (nbytes > req->assoclen) nbytes = dec_bytes = req->assoclen;\n            dec_bytes -= (nbytes % AES_BLOCK_SIZE);\n            memcpy(walk.dst.virt.addr, walk.src.virt.addr, dec_bytes);\n            assoc_remain -= dec_bytes;\n            temp = walk.dst.virt.addr;\n            while (dec_bytes > 0) {\n                u128_xor((u128 *)ctx->hash, (u128 *)ctx->hash, (u128 *)temp);\n                gf128mul_4k_lle((be128 *)ctx->hash, ctx->gf128);\n                dec_bytes -= AES_BLOCK_SIZE;\n                temp += 16;\n            }\n            if (assoc_remain < AES_BLOCK_SIZE) walk.stride = assoc_remain;\n            if (assoc_remain == 0) walk.stride = AES_BLOCK_SIZE;\n            dec_bytes = nbytes - (nbytes % AES_BLOCK_SIZE);\n            err = skcipher_walk_done(&walk, (walk.nbytes - dec_bytes));\n            ghashlen = min(assoc_remain, walk.nbytes);\n        }\n\n        if ((dec_bytes = ghashlen)) {\n            memcpy(ctx->lastbuffer, walk.src.virt.addr, dec_bytes);\n            memset(ctx->lastbuffer + dec_bytes, 0, (AES_BLOCK_SIZE - dec_bytes));\n            memcpy(walk.dst.virt.addr, walk.src.virt.addr, ghashlen);\n            u128_xor((u128 *)ctx->hash, (u128 *)ctx->hash, (u128 *)ctx->lastbuffer);\n            gf128mul_4k_lle((be128 *)ctx->hash, ctx->gf128);\n            walk.stride = AES_BLOCK_SIZE;\n            err = skcipher_walk_done(&walk, (walk.nbytes - ghashlen));\n        }\n    }\n\n    //crypt and hash\n    while ((nbytes = dec_bytes = walk.nbytes) && (walk.nbytes >= AES_BLOCK_SIZE)) {\n        u8 *temp;\n        dec_bytes -= (nbytes % AES_BLOCK_SIZE);\n        temp = walk.src.virt.addr;\n        while (dec_bytes) {\n            u128_xor((u128 *)ctx->hash, (u128 *)ctx->hash, (u128 *)temp);\n            gf128mul_4k_lle((be128 *)ctx->hash, ctx->gf128);\n            dec_bytes -= AES_BLOCK_SIZE;\n            temp += 16;\n        }\n        dec_bytes = nbytes - (nbytes % AES_BLOCK_SIZE);\n        ifx_deu_aes_ctr(ctx, walk.dst.virt.addr, walk.src.virt.addr,\n                       iv, dec_bytes, CRYPTO_DIR_DECRYPT, 0);\n        nbytes &= AES_BLOCK_SIZE - 1;\n        err = skcipher_walk_done(&walk, nbytes);\n    }\n\n    /* crypt and hash remaining bytes < AES_BLOCK_SIZE */\n    if ((dec_bytes = walk.nbytes)) {\n        memcpy(ctx->lastbuffer, walk.src.virt.addr, dec_bytes);\n        memset(ctx->lastbuffer + dec_bytes, 0, (AES_BLOCK_SIZE - dec_bytes));\n        u128_xor((u128 *)ctx->hash, (u128 *)ctx->hash, (u128 *)ctx->lastbuffer);\n        gf128mul_4k_lle((be128 *)ctx->hash, ctx->gf128);\n        ifx_deu_aes_ctr(ctx, walk.dst.virt.addr, walk.src.virt.addr,\n                       iv, walk.nbytes, CRYPTO_DIR_DECRYPT, 0);\n        err = skcipher_walk_done(&walk, 0);\n    }\n\n    //finalize and copy hash\n    u128_xor((u128 *)ctx->hash, (u128 *)ctx->hash, (u128 *)&lengths);\n    gf128mul_4k_lle((be128 *)ctx->hash, ctx->gf128);\n    u128_xor((u128 *)ctx->hash, (u128 *)ctx->hash, (u128 *)ctx->block);\n\n    scatterwalk_map_and_copy(ctx->lastbuffer, req->src, req->cryptlen + req->assoclen - authsize, authsize, 0);\n    err = crypto_memneq(ctx->lastbuffer, ctx->hash, authsize) ? -EBADMSG : 0;\n\n    aead_request_complete(req, 0);\n\n    return err;\n}\n\n/*! \\fn void aes_gcm_exit_tfm(struct crypto_tfm *tfm)\n *  \\ingroup IFX_aes_cbcmac_FUNCTIONS\n *  \\brief free pointers in aes_ctx\n *  \\param tfm linux crypto shash transform\n*/\nstatic void aes_gcm_exit_tfm(struct crypto_tfm *tfm)\n{\n    struct aes_ctx *ctx = crypto_tfm_ctx(tfm);\n    if (ctx->gf128) gf128mul_free_4k(ctx->gf128);\n}\n\n/*\n * \\brief AES function mappings\n*/\nstruct aead_alg ifxdeu_gcm_aes_alg = {\n    .base.cra_name           =   \"gcm(aes)\",\n    .base.cra_driver_name    =   \"ifxdeu-gcm(aes)\",\n    .base.cra_priority       =   400,\n    .base.cra_flags          =   CRYPTO_ALG_TYPE_SKCIPHER | CRYPTO_ALG_KERN_DRIVER_ONLY,\n    .base.cra_blocksize      =   1,\n    .base.cra_ctxsize        =   sizeof(struct aes_ctx),\n    .base.cra_module         =   THIS_MODULE,\n    .base.cra_list           =   LIST_HEAD_INIT(ifxdeu_gcm_aes_alg.base.cra_list),\n    .base.cra_exit           =   aes_gcm_exit_tfm,\n    .ivsize                  =   GCM_AES_IV_SIZE,\n    .maxauthsize             =   AES_BLOCK_SIZE,\n    .chunksize               =   AES_BLOCK_SIZE,\n    .setkey                  =   aes_set_key_aead,\n    .encrypt                 =   gcm_aes_encrypt,\n    .decrypt                 =   gcm_aes_decrypt,\n    .setauthsize             =   gcm_aes_setauthsize,\n};\n\n/*! \\fn int ifxdeu_init_aes (void)\n *  \\ingroup IFX_AES_FUNCTIONS\n *  \\brief function to initialize AES driver\n *  \\return ret\n*/\nint ifxdeu_init_aes (void)\n{\n    int ret = -ENOSYS;\n\n    aes_chip_init();\n\n    if ((ret = crypto_register_alg(&ifxdeu_aes_alg)))\n        goto aes_err;\n\n    if ((ret = crypto_register_skcipher(&ifxdeu_ecb_aes_alg)))\n        goto ecb_aes_err;\n\n    if ((ret = crypto_register_skcipher(&ifxdeu_cbc_aes_alg)))\n        goto cbc_aes_err;\n\n    if ((ret = crypto_register_skcipher(&ifxdeu_xts_aes_alg)))\n        goto xts_aes_err;\n\n    if ((ret = crypto_register_skcipher(&ifxdeu_ofb_aes_alg)))\n        goto ofb_aes_err;\n\n    if ((ret = crypto_register_skcipher(&ifxdeu_cfb_aes_alg)))\n        goto cfb_aes_err;\n\n    if ((ret = crypto_register_skcipher(&ifxdeu_ctr_basic_aes_alg)))\n        goto ctr_basic_aes_err;\n\n    if ((ret = crypto_register_skcipher(&ifxdeu_ctr_rfc3686_aes_alg)))\n        goto ctr_rfc3686_aes_err;\n\n    if ((ret = crypto_register_shash(&ifxdeu_cbcmac_aes_alg)))\n        goto cbcmac_aes_err;\n\n    if ((ret = crypto_register_aead(&ifxdeu_gcm_aes_alg)))\n        goto gcm_aes_err;\n\n    CRTCL_SECT_INIT;\n\n\n    printk (KERN_NOTICE \"IFX DEU AES initialized%s%s.\\n\", disable_multiblock ? \"\" : \" (multiblock)\", disable_deudma ? \"\" : \" (DMA)\");\n    return ret;\n\ngcm_aes_err:\n    crypto_unregister_aead(&ifxdeu_gcm_aes_alg);\n    printk (KERN_ERR \"IFX gcm_aes initialization failed!\\n\");\n    return ret;\ncbcmac_aes_err:\n    crypto_unregister_shash(&ifxdeu_cbcmac_aes_alg);\n    printk (KERN_ERR \"IFX cbcmac_aes initialization failed!\\n\");\n    return ret;\nctr_rfc3686_aes_err:\n    crypto_unregister_skcipher(&ifxdeu_ctr_rfc3686_aes_alg);\n    printk (KERN_ERR \"IFX ctr_rfc3686_aes initialization failed!\\n\");\n    return ret;\nctr_basic_aes_err:\n    crypto_unregister_skcipher(&ifxdeu_ctr_basic_aes_alg);\n    printk (KERN_ERR \"IFX ctr_basic_aes initialization failed!\\n\");\n    return ret;\ncfb_aes_err:\n    crypto_unregister_skcipher(&ifxdeu_cfb_aes_alg);\n    printk (KERN_ERR \"IFX cfb_aes initialization failed!\\n\");\n    return ret;\nofb_aes_err:\n    crypto_unregister_skcipher(&ifxdeu_ofb_aes_alg);\n    printk (KERN_ERR \"IFX ofb_aes initialization failed!\\n\");\n    return ret;\nxts_aes_err:\n    crypto_unregister_skcipher(&ifxdeu_xts_aes_alg);\n    printk (KERN_ERR \"IFX xts_aes initialization failed!\\n\");\n    return ret;\ncbc_aes_err:\n    crypto_unregister_skcipher(&ifxdeu_cbc_aes_alg);\n    printk (KERN_ERR \"IFX cbc_aes initialization failed!\\n\");\n    return ret;\necb_aes_err:\n    crypto_unregister_skcipher(&ifxdeu_ecb_aes_alg);\n    printk (KERN_ERR \"IFX aes initialization failed!\\n\");\n    return ret;\naes_err:\n    printk(KERN_ERR \"IFX DEU AES initialization failed!\\n\");\n\n    return ret;\n}\n\n/*! \\fn void ifxdeu_fini_aes (void)\n *  \\ingroup IFX_AES_FUNCTIONS\n *  \\brief unregister aes driver\n*/\nvoid ifxdeu_fini_aes (void)\n{\n    crypto_unregister_alg (&ifxdeu_aes_alg);\n    crypto_unregister_skcipher (&ifxdeu_ecb_aes_alg);\n    crypto_unregister_skcipher (&ifxdeu_cbc_aes_alg);\n    crypto_unregister_skcipher (&ifxdeu_xts_aes_alg);\n    crypto_unregister_skcipher (&ifxdeu_ofb_aes_alg);\n    crypto_unregister_skcipher (&ifxdeu_cfb_aes_alg);\n    crypto_unregister_skcipher (&ifxdeu_ctr_basic_aes_alg);\n    crypto_unregister_skcipher (&ifxdeu_ctr_rfc3686_aes_alg);\n    crypto_unregister_shash (&ifxdeu_cbcmac_aes_alg);\n    crypto_unregister_aead (&ifxdeu_gcm_aes_alg);\n}\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-deu/src/ifxmips_arc4.c",
    "content": "/******************************************************************************\n**\n** FILE NAME    : ifxmips_arc4.c\n** PROJECT      : IFX UEIP\n** MODULES      : DEU Module\n**\n** DATE         : September 8, 2009\n** AUTHOR       : Mohammad Firdaus\n** DESCRIPTION  : Data Encryption Unit Driver for ARC4 Algorithm\n** COPYRIGHT    :       Copyright (c) 2009\n**                      Infineon Technologies AG\n**                      Am Campeon 1-12, 85579 Neubiberg, Germany\n**\n**    This program is free software; you can redistribute it and/or modify\n**    it under the terms of the GNU General Public License as published by\n**    the Free Software Foundation; either version 2 of the License, or\n**    (at your option) any later version.\n**\n** HISTORY\n** $Date        $Author             $Comment\n** 08 Sept 2009 Mohammad Firdaus    Initial UEIP release\n*******************************************************************************/\n\n/*!\n  \\defgroup IFX_DEU IFX_DEU_DRIVERS\n  \\ingroup API\n  \\brief ifx deu driver module\n*/\n\n/*!\n  \\file\t\tifxmips_arc4.c\n  \\ingroup \tIFX_DEU\n  \\brief \tARC4 encryption DEU driver file\n*/\n\n/*! \n  \\defgroup IFX_ARC4_FUNCTIONS IFX_ARC4_FUNCTIONS\n  \\ingroup IFX_DEU\n  \\brief IFX deu driver functions\n*/\n\n/* Project header */\n#include <linux/version.h>\n#include <linux/module.h>\n#include <linux/init.h>\n#include <linux/types.h>\n#include <linux/errno.h>\n#include <linux/crypto.h>\n#include <crypto/algapi.h>\n#include <crypto/internal/skcipher.h>\n#include <linux/interrupt.h>\n#include <asm/byteorder.h>\n#include <linux/delay.h>\n\n/* Board specific header files */\n#ifdef CONFIG_AR9\n#include \"ifxmips_deu_ar9.h\"\n#endif\n#ifdef CONFIG_VR9\n#include \"ifxmips_deu_vr9.h\"\n#endif\n \nstatic spinlock_t lock;\n#define CRTCL_SECT_INIT        spin_lock_init(&lock)\n#define CRTCL_SECT_START       spin_lock_irqsave(&lock, flag)\n#define CRTCL_SECT_END         spin_unlock_irqrestore(&lock, flag)\n\n/* Preprocessor declerations */\n#define ARC4_MIN_KEY_SIZE       1\n//#define ARC4_MAX_KEY_SIZE     256\n#define ARC4_MAX_KEY_SIZE       16\n#define ARC4_BLOCK_SIZE         1\n#define ARC4_START   IFX_ARC4_CON\n#ifdef CRYPTO_DEBUG\nextern char debug_level;\n#define DPRINTF(level, format, args...) if (level < debug_level) printk(KERN_INFO \"[%s %s %d]: \" format, __FILE__, __func__, __LINE__, ##args);\n#else\n#define DPRINTF(level, format, args...)\n#endif\n\n/* \n * \\brief arc4 private structure\n*/\nstruct arc4_ctx {\n        int key_length;\n        u8 buf[120];\n};\n\nextern int disable_deudma;\nextern int disable_multiblock;\n\n/*! \\fn static void _deu_arc4 (void *ctx_arg, u8 *out_arg, const u8 *in_arg, u8 *iv_arg, u32 nbytes, int encdec, int mode)\n    \\ingroup IFX_ARC4_FUNCTIONS\n    \\brief main interface to ARC4 hardware   \n    \\param ctx_arg crypto algo context  \n    \\param out_arg output bytestream  \n    \\param in_arg input bytestream   \n    \\param iv_arg initialization vector  \n    \\param nbytes length of bytestream  \n    \\param encdec 1 for encrypt; 0 for decrypt  \n    \\param mode operation mode such as ebc, cbc, ctr  \n*/                                 \nstatic void _deu_arc4 (void *ctx_arg, u8 *out_arg, const u8 *in_arg,\n            u8 *iv_arg, u32 nbytes, int encdec, int mode)\n{\n        volatile struct arc4_t *arc4 = (struct arc4_t *) ARC4_START;\n        \n        int i = 0;\n        unsigned long flag;\n        \n#if 1 // need to handle nbytes not multiple of 16       \n        volatile u32 tmp_array32[4];\n        volatile u8 *tmp_ptr8;\n        int remaining_bytes, j;\n#endif\n\n        CRTCL_SECT_START;\n\n        arc4->IDLEN = nbytes;\n\n#if 1\n        while (i < nbytes) {\n                arc4->ID3R = *((u32 *) in_arg + (i>>2) + 0);\n                arc4->ID2R = *((u32 *) in_arg + (i>>2) + 1);    \n                arc4->ID1R = *((u32 *) in_arg + (i>>2) + 2);\n                arc4->ID0R = *((u32 *) in_arg + (i>>2) + 3);    \n                \n                arc4->controlr.GO = 1; \n                \n                while (arc4->controlr.BUS) {\n                      // this will not take long\n                }\n\n#if 1\n                // need to handle nbytes not multiple of 16 \n                tmp_array32[0] = arc4->OD3R;\n                tmp_array32[1] = arc4->OD2R;\n                tmp_array32[2] = arc4->OD1R;\n                tmp_array32[3] = arc4->OD0R;\n\n                remaining_bytes = nbytes - i;\n                if (remaining_bytes > 16)\n                     remaining_bytes = 16;\n                \n                tmp_ptr8 = (u8 *)&tmp_array32[0];\n                for (j = 0; j < remaining_bytes; j++)\n                     *out_arg++ = *tmp_ptr8++;\n#else                                \n                *((u32 *) out_arg + (i>>2) + 0) = arc4->OD3R;\n                *((u32 *) out_arg + (i>>2) + 1) = arc4->OD2R;\n                *((u32 *) out_arg + (i>>2) + 2) = arc4->OD1R;\n                *((u32 *) out_arg + (i>>2) + 3) = arc4->OD0R;\n#endif\n\n                i += 16;\n        }\n#else // dma\n\n#endif // dma\n\n        CRTCL_SECT_END;\n}\n\n/*! \\fn arc4_chip_init (void)\n    \\ingroup IFX_ARC4_FUNCTIONS\n    \\brief initialize arc4 hardware   \n*/                                 \nstatic void arc4_chip_init (void)\n{\n        //do nothing\n}\n\n/*! \\fn static int arc4_set_key(struct crypto_tfm *tfm, const u8 *in_key, unsigned int key_len)\n    \\ingroup IFX_ARC4_FUNCTIONS\n    \\brief sets ARC4 key    \n    \\param tfm linux crypto algo transform  \n    \\param in_key input key  \n    \\param key_len key lengths less than or equal to 16 bytes supported  \n*/    \nstatic int arc4_set_key(struct crypto_tfm *tfm, const u8 *inkey,\n                       unsigned int key_len)\n{\n        //struct arc4_ctx *ctx = crypto_tfm_ctx(tfm);\n        volatile struct arc4_t *arc4 = (struct arc4_t *) ARC4_START;\n        u32 *in_key = (u32 *)inkey;\n                \n        // must program all bits at one go?!!!\n//#if 1\n        *IFX_ARC4_CON = ( (1<<31) | ((key_len - 1)<<27) | (1<<26) | (3<<16) );\n        //NDC=1,ENDI=1,GO=0,KSAE=1,SM=0\n\n        arc4->K3R = *((u32 *) in_key + 0);\n        arc4->K2R = *((u32 *) in_key + 1);\n        arc4->K1R = *((u32 *) in_key + 2);\n        arc4->K0R = *((u32 *) in_key + 3);\n\n#if 0 // arc4 is a ugly state machine, KSAE can only be set once per session  \n        ctx->key_length = key_len;\n\n        memcpy ((u8 *) (ctx->buf), in_key, key_len);\n#endif\n\n        return 0;\n}\n\n/*! \\fn static int arc4_set_key_skcipher(struct crypto_skcipher *tfm, const u8 *in_key, unsigned int key_len)\n    \\ingroup IFX_ARC4_FUNCTIONS\n    \\brief sets ARC4 key\n    \\param tfm linux crypto skcipher\n    \\param in_key input key\n    \\param key_len key lengths less than or equal to 16 bytes supported\n*/\nstatic int arc4_set_key_skcipher(struct crypto_skcipher *tfm, const u8 *inkey,\n                       unsigned int key_len)\n{\n        return arc4_set_key(crypto_skcipher_ctx(tfm), inkey, key_len);\n}\n\n/*! \\fn static void _deu_arc4_ecb(void *ctx, uint8_t *dst, const uint8_t *src, uint8_t *iv, size_t nbytes, int encdec, int inplace)\n    \\ingroup IFX_ARC4_FUNCTIONS\n    \\brief sets ARC4 hardware to ECB mode   \n    \\param ctx crypto algo context  \n    \\param dst output bytestream  \n    \\param src input bytestream  \n    \\param iv initialization vector   \n    \\param nbytes length of bytestream  \n    \\param encdec 1 for encrypt; 0 for decrypt  \n    \\param inplace not used  \n*/                               \nstatic void _deu_arc4_ecb(void *ctx, uint8_t *dst, const uint8_t *src,\n                uint8_t *iv, size_t nbytes, int encdec, int inplace)\n{\n        _deu_arc4 (ctx, dst, src, NULL, nbytes, encdec, 0);\n}\n\n/*! \\fn static void arc4_crypt(struct crypto_tfm *tfm, u8 *out, const u8 *in)\n    \\ingroup IFX_ARC4_FUNCTIONS\n    \\brief encrypt/decrypt ARC4_BLOCK_SIZE of data   \n    \\param tfm linux crypto algo transform  \n    \\param out output bytestream  \n    \\param in input bytestream  \n*/     \nstatic void arc4_crypt(struct crypto_tfm *tfm, u8 *out, const u8 *in)\n{\n        struct arc4_ctx *ctx = crypto_tfm_ctx(tfm);\n\n        _deu_arc4 (ctx, out, in, NULL, ARC4_BLOCK_SIZE,\n                    CRYPTO_DIR_DECRYPT, 0);\n\n}\n\n/*\n * \\brief ARC4 function mappings\n*/\nstatic struct crypto_alg ifxdeu_arc4_alg = {\n        .cra_name               =       \"arc4\",\n        .cra_driver_name        =       \"ifxdeu-arc4\",\n        .cra_priority           =       300,\n        .cra_flags              =       CRYPTO_ALG_TYPE_CIPHER | CRYPTO_ALG_KERN_DRIVER_ONLY,\n        .cra_blocksize          =       ARC4_BLOCK_SIZE,\n        .cra_ctxsize            =       sizeof(struct arc4_ctx),\n        .cra_module             =       THIS_MODULE,\n        .cra_list               =       LIST_HEAD_INIT(ifxdeu_arc4_alg.cra_list),\n        .cra_u                  =       {\n                .cipher = {\n                        .cia_min_keysize        =       ARC4_MIN_KEY_SIZE,\n                        .cia_max_keysize        =       ARC4_MAX_KEY_SIZE,\n                        .cia_setkey             =       arc4_set_key,\n                        .cia_encrypt            =       arc4_crypt,\n                        .cia_decrypt            =       arc4_crypt,\n                }\n        }\n};\n\n/*! \\fn static int ecb_arc4_encrypt(struct skcipher_request *req)\n    \\ingroup IFX_ARC4_FUNCTIONS\n    \\brief ECB ARC4 encrypt using linux crypto skcipher\n    \\param req skcipher_request\n*/\nstatic int ecb_arc4_encrypt(struct skcipher_request *req)\n{\n        struct arc4_ctx *ctx = crypto_tfm_ctx(req->base.tfm);\n        struct skcipher_walk walk;\n        unsigned int nbytes;\n        int err;\n\n        DPRINTF(1, \"\\n\");\n        err = skcipher_walk_virt(&walk, req, false);\n\n        while ((nbytes = walk.nbytes)) {\n                _deu_arc4_ecb(ctx, walk.dst.virt.addr, walk.src.virt.addr, \n                               NULL, nbytes, CRYPTO_DIR_ENCRYPT, 0);\n                nbytes &= ARC4_BLOCK_SIZE - 1;\n                err = skcipher_walk_done(&walk, nbytes);\n        }\n\n        return err;\n}\n\n/*! \\fn static int ecb_arc4_decrypt(struct skcipher_request *req)\n    \\ingroup IFX_ARC4_FUNCTIONS\n    \\brief ECB ARC4 decrypt using linux crypto skcipher\n    \\param desc skcipher_request\n*/\nstatic int ecb_arc4_decrypt(struct skcipher_request *req)\n{\n        struct arc4_ctx *ctx = crypto_tfm_ctx(req->base.tfm);\n        struct skcipher_walk walk;\n        unsigned int nbytes;\n        int err;\n\n        DPRINTF(1, \"\\n\");\n        err = skcipher_walk_virt(&walk, req, false);\n\n        while ((nbytes = walk.nbytes)) {\n                _deu_arc4_ecb(ctx, walk.dst.virt.addr, walk.src.virt.addr, \n                               NULL, nbytes, CRYPTO_DIR_DECRYPT, 0);\n                nbytes &= ARC4_BLOCK_SIZE - 1;\n                err = skcipher_walk_done(&walk, nbytes);\n        }\n\n        return err;\n}\n\n/*\n * \\brief ARC4 function mappings\n*/\nstatic struct skcipher_alg ifxdeu_ecb_arc4_alg = {\n        .base.cra_name          =       \"ecb(arc4)\",\n        .base.cra_driver_name   =       \"ifxdeu-ecb(arc4)\",\n        .base.cra_priority      =       400,\n        .base.cra_flags         =       CRYPTO_ALG_TYPE_SKCIPHER | CRYPTO_ALG_KERN_DRIVER_ONLY,\n        .base.cra_blocksize     =       ARC4_BLOCK_SIZE,\n        .base.cra_ctxsize       =       sizeof(struct arc4_ctx),\n        .base.cra_module        =       THIS_MODULE,\n        .base.cra_list          =       LIST_HEAD_INIT(ifxdeu_ecb_arc4_alg.base.cra_list),\n        .min_keysize            =       ARC4_MIN_KEY_SIZE,\n        .max_keysize            =       ARC4_MAX_KEY_SIZE,\n        .setkey                 =       arc4_set_key_skcipher,\n        .encrypt                =       ecb_arc4_encrypt,\n        .decrypt                =       ecb_arc4_decrypt,\n};\n\n/*! \\fn int ifxdeu_init_arc4(void)\n    \\ingroup IFX_ARC4_FUNCTIONS\n    \\brief initialize arc4 driver    \n*/                                 \nint ifxdeu_init_arc4(void)\n{\n    int ret = -ENOSYS;\n\n\n        if ((ret = crypto_register_alg(&ifxdeu_arc4_alg)))\n                goto arc4_err;\n\n        if ((ret = crypto_register_skcipher(&ifxdeu_ecb_arc4_alg)))\n                goto ecb_arc4_err;\n\n        arc4_chip_init ();\n\n        CRTCL_SECT_INIT;\n\n        printk (KERN_NOTICE \"IFX DEU ARC4 initialized%s%s.\\n\", disable_multiblock ? \"\" : \" (multiblock)\", disable_deudma ? \"\" : \" (DMA)\");\n        return ret;\n\narc4_err:\n        crypto_unregister_alg(&ifxdeu_arc4_alg);\n        printk(KERN_ERR \"IFX arc4 initialization failed!\\n\");\n        return ret;\necb_arc4_err:\n        crypto_unregister_skcipher(&ifxdeu_ecb_arc4_alg);\n        printk (KERN_ERR \"IFX ecb_arc4 initialization failed!\\n\");\n        return ret;\n\n}\n\n/*! \\fn void ifxdeu_fini_arc4(void)\n    \\ingroup IFX_ARC4_FUNCTIONS\n    \\brief unregister arc4 driver   \n*/                                 \nvoid ifxdeu_fini_arc4(void)\n{\n        crypto_unregister_alg (&ifxdeu_arc4_alg);\n        crypto_unregister_skcipher (&ifxdeu_ecb_arc4_alg);\n\n\n}\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-deu/src/ifxmips_async_aes.c",
    "content": "/******************************************************************************\n**\n** FILE NAME    : ifxmips_async_aes.c\n** PROJECT      : IFX UEIP\n** MODULES      : DEU Module\n**\n** DATE         : October 11, 2010\n** AUTHOR       : Mohammad Firdaus\n** DESCRIPTION  : Data Encryption Unit Driver for AES Algorithm\n** COPYRIGHT    :       Copyright (c) 2010\n**                      Infineon Technologies AG\n**                      Am Campeon 1-12, 85579 Neubiberg, Germany\n**\n**    This program is free software; you can redistribute it and/or modify\n**    it under the terms of the GNU General Public License as published by\n**    the Free Software Foundation; either version 2 of the License, or\n**    (at your option) any later version.\n**\n** HISTORY\n** $Date        $Author             $Comment\n** 08,Sept 2009 Mohammad Firdaus    Initial UEIP release\n** 11, Oct 2010 Mohammad Firdaus    Kernel Port incl. Async. Ablkcipher mode\n** 21,March 2011 Mohammad Firdaus   Changes for Kernel 2.6.32 and IPSec integration\n*******************************************************************************/\n/*!\n \\defgroup IFX_DEU IFX_DEU_DRIVERS\n \\ingroup API\n \\brief ifx DEU driver module\n*/\n\n/*!\n  \\file ifxmips_async_aes.c\n  \\ingroup IFX_DEU\n  \\brief AES Encryption Driver main file\n*/\n\n/*!\n \\defgroup IFX_AES_FUNCTIONS IFX_AES_FUNCTIONS\n \\ingroup IFX_DEU\n \\brief IFX AES driver Functions\n*/\n\n\n\n#include <linux/wait.h>\n#include <linux/crypto.h>\n#include <linux/kernel.h>\n#include <linux/kthread.h>\n#include <linux/interrupt.h>\n#include <linux/spinlock.h>\n#include <linux/list.h>\n#include <crypto/ctr.h>\n#include <crypto/aes.h>\n#include <crypto/algapi.h>\n#include <crypto/scatterwalk.h>\n\n#include <asm/ifx/ifx_regs.h>\n#include <asm/ifx/ifx_types.h>\n#include <asm/ifx/common_routines.h>\n#include <asm/ifx/irq.h>\n#include <asm/ifx/ifx_pmu.h>\n#include <asm/ifx/ifx_gpio.h>\n#include <asm/kmap_types.h>\n\n#include \"ifxmips_deu.h\"\n\n#if defined(CONFIG_DANUBE)\n#include \"ifxmips_deu_danube.h\"\nextern int ifx_danube_pre_1_4;\n#elif defined(CONFIG_AR9)\n#include \"ifxmips_deu_ar9.h\"\n#elif defined(CONFIG_VR9) || defined(CONFIG_AR10)\n#include \"ifxmips_deu_vr9.h\"\n#else\n#error \"Unkown platform\"\n#endif\n\n/* DMA related header and variables */\n\nspinlock_t aes_lock;\n#define CRTCL_SECT_INIT        spin_lock_init(&aes_lock)\n#define CRTCL_SECT_START       spin_lock_irqsave(&aes_lock, flag)\n#define CRTCL_SECT_END         spin_unlock_irqrestore(&aes_lock, flag)\n\n/* Definition of constants */\n//#define AES_START   IFX_AES_CON\n#define AES_MIN_KEY_SIZE    16\n#define AES_MAX_KEY_SIZE    32\n#define AES_BLOCK_SIZE      16\n#define CTR_RFC3686_NONCE_SIZE    4\n#define CTR_RFC3686_IV_SIZE       8\n#define CTR_RFC3686_MAX_KEY_SIZE  (AES_MAX_KEY_SIZE + CTR_RFC3686_NONCE_SIZE)\n\n#ifdef CRYPTO_DEBUG\nextern char debug_level;\n#define DPRINTF(level, format, args...) if (level < debug_level) printk(KERN_INFO \"[%s %s %d]: \" format, __FILE__, __func__, __LINE__, ##args);\n#else\n#define DPRINTF(level, format, args...)\n#endif /* CRYPTO_DEBUG */\n\n\nstatic int disable_multiblock = 0;\nmodule_param(disable_multiblock, int, 0);\n\nstatic int disable_deudma = 1;\n\n/* Function decleration */\nint aes_chip_init(void);\nu32 endian_swap(u32 input);\nu32 input_swap(u32 input);\nu32* memory_alignment(const u8 *arg, u32 *buff_alloc, int in_out, int nbytes);\nvoid aes_dma_memory_copy(u32 *outcopy, u32 *out_dma, u8 *out_arg, int nbytes);\nint aes_memory_allocate(int value);\nint des_memory_allocate(int value);\nvoid memory_release(u32 *addr);\n\n\nstruct aes_ctx {\n    int key_length;\n    u32 buf[AES_MAX_KEY_SIZE];\n    u8 nonce[CTR_RFC3686_NONCE_SIZE];\n\n};\n\nstruct aes_container {\n    u8 *iv;\n    u8 *src_buf;\n    u8 *dst_buf;\n\n    int mode;\n    int encdec;\n    int complete;\n    int flag;\n\n    u32 bytes_processed;\n    u32 nbytes;\n\n    struct ablkcipher_request arequest;\n \n};\n\naes_priv_t *aes_queue;\nextern deu_drv_priv_t deu_dma_priv;\n\nvoid hexdump(unsigned char *buf, unsigned int len)\n{\n        print_hex_dump(KERN_CONT, \"\", DUMP_PREFIX_OFFSET,\n                        16, 1,\n                        buf, len, false);\n}\n\n/*! \\fn void lq_deu_aes_core (void *ctx_arg, u8 *out_arg, const u8 *in_arg, u8 *iv_arg, \n                             size_t nbytes, int encdec, int mode)\n *  \\ingroup IFX_AES_FUNCTIONS\n *  \\brief main interface to AES hardware\n *  \\param ctx_arg crypto algo context\n *  \\param out_arg output bytestream\n *  \\param in_arg input bytestream\n *  \\param iv_arg initialization vector\n *  \\param nbytes length of bytestream\n *  \\param encdec 1 for encrypt; 0 for decrypt\n *  \\param mode operation mode such as ebc, cbc, ctr\n *\n*/\n\nstatic int lq_deu_aes_core (void *ctx_arg, u8 *out_arg, const u8 *in_arg,\n                            u8 *iv_arg, size_t nbytes, int encdec, int mode)\n{\n    /*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */\n    volatile struct aes_t *aes = (volatile struct aes_t *) AES_START;\n    struct aes_ctx *ctx = (struct aes_ctx *)ctx_arg;\n    u32 *in_key = ctx->buf;\n    unsigned long flag;\n    /*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */\n    int key_len = ctx->key_length;\n\n    volatile struct deu_dma_t *dma = (struct deu_dma_t *) IFX_DEU_DMA_CON;\n    struct dma_device_info *dma_device = ifx_deu[0].dma_device;\n    deu_drv_priv_t *deu_priv = (deu_drv_priv_t *)dma_device->priv;\n    int wlen = 0;\n    //u32 *outcopy = NULL;\n    u32 *dword_mem_aligned_in = NULL;\n\n    CRTCL_SECT_START;\n\n    /* 128, 192 or 256 bit key length */\n    aes->controlr.K = key_len / 8 - 2;\n        if (key_len == 128 / 8) {\n        aes->K3R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 0));\n        aes->K2R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 1));\n        aes->K1R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 2));\n        aes->K0R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 3));\n    }\n    else if (key_len == 192 / 8) {\n        aes->K5R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 0));\n        aes->K4R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 1));\n        aes->K3R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 2));\n        aes->K2R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 3));\n        aes->K1R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 4));\n        aes->K0R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 5));\n    }\n    else if (key_len == 256 / 8) {\n        aes->K7R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 0));\n        aes->K6R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 1));\n        aes->K5R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 2));\n        aes->K4R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 3));\n        aes->K3R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 4));\n        aes->K2R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 5));\n        aes->K1R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 6));\n        aes->K0R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 7));\n    }\n    else {\n        printk (KERN_ERR \"[%s %s %d]: Invalid key_len : %d\\n\", __FILE__, __func__, __LINE__, key_len);\n        CRTCL_SECT_END;\n        return -EINVAL;\n    }\n\n    /* let HW pre-process DEcryption key in any case (even if\n       ENcryption is used). Key Valid (KV) bit is then only\n       checked in decryption routine! */\n    aes->controlr.PNK = 1;\n\n    while (aes->controlr.BUS) {\n        // this will not take long\n    }\n    AES_DMA_MISC_CONFIG();\n\n    aes->controlr.E_D = !encdec;    //encryption\n    aes->controlr.O = mode; //0 ECB 1 CBC 2 OFB 3 CFB 4 CTR \n\n    //aes->controlr.F = 128; //default; only for CFB and OFB modes; change only for customer-specific apps\n    if (mode > 0) {\n        aes->IV3R = DEU_ENDIAN_SWAP(*(u32 *) iv_arg);\n        aes->IV2R = DEU_ENDIAN_SWAP(*((u32 *) iv_arg + 1));\n        aes->IV1R = DEU_ENDIAN_SWAP(*((u32 *) iv_arg + 2));\n        aes->IV0R = DEU_ENDIAN_SWAP(*((u32 *) iv_arg + 3));\n    };\n\n\n    /* Prepare Rx buf length used in dma psuedo interrupt */\n    deu_priv->deu_rx_buf = (u32 *)out_arg;\n    deu_priv->deu_rx_len = nbytes;\n   \n    /* memory alignment issue */ \n    dword_mem_aligned_in = (u32 *) DEU_DWORD_REORDERING(in_arg, aes_buff_in, BUFFER_IN, nbytes);\n\n    dma->controlr.ALGO = 1;   //AES\n    dma->controlr.BS = 0;\n    aes->controlr.DAU = 0;\n    dma->controlr.EN = 1;\n\n    while (aes->controlr.BUS) {\n         // wait for AES to be ready\n    };\n\n    deu_priv->outcopy = (u32 *) DEU_DWORD_REORDERING(out_arg, aes_buff_out, BUFFER_OUT, nbytes);\n    deu_priv->event_src = AES_ASYNC_EVENT;\n\n    wlen = dma_device_write (dma_device, (u8 *)dword_mem_aligned_in, nbytes, NULL);\n    if (wlen != nbytes) {\n        dma->controlr.EN = 0;\n        CRTCL_SECT_END;\n        printk (KERN_ERR \"[%s %s %d]: dma_device_write fail!\\n\", __FILE__, __func__, __LINE__);\n        return -EINVAL;\n    }\n\n   // WAIT_AES_DMA_READY();\n\n    CRTCL_SECT_END;\n\n    if (mode > 0) {\n        *((u32 *) iv_arg) = DEU_ENDIAN_SWAP(*((u32 *) iv_arg));\n        *((u32 *) iv_arg + 1) = DEU_ENDIAN_SWAP(*((u32 *) iv_arg + 1));\n        *((u32 *) iv_arg + 2) = DEU_ENDIAN_SWAP(*((u32 *) iv_arg + 2));\n        *((u32 *) iv_arg + 3) = DEU_ENDIAN_SWAP(*((u32 *) iv_arg + 3));\n    }\n   \n    return -EINPROGRESS;\t\n}\n\n/* \\fn static int count_sgs(struct scatterlist *sl, unsigned int total_bytes)\n * \\ingroup IFX_AES_FUNCTIONS\n * \\brief Counts and return the number of scatterlists \n * \\param *sl Function pointer to the scatterlist\n * \\param total_bytes The total number of bytes that needs to be encrypted/decrypted\n * \\return The number of scatterlists \n*/\n\nstatic int count_sgs(struct scatterlist *sl, unsigned int total_bytes)\n{\n        int i = 0;\n\n        do {\n                total_bytes -= sl[i].length;\n                i++;\n\n        } while (total_bytes > 0);\n\n        return i;\n}\n\n/* \\fn void lq_sg_init(struct scatterlist *src,\n *                     struct scatterlist *dst)\n * \\ingroup IFX_AES_FUNCTIONS\n * \\brief Maps the scatterlists into a source/destination page. \n * \\param *src Pointer to the source scatterlist\n * \\param *dst Pointer to the destination scatterlist\n*/\n\nstatic void lq_sg_init(struct aes_container *aes_con,struct scatterlist *src,\n                       struct scatterlist *dst)\n{\n\n    struct page *dst_page, *src_page;\n\n    src_page = sg_virt(src);\n    aes_con->src_buf = (char *) src_page;\n\n    dst_page = sg_virt(dst);\n    aes_con->dst_buf = (char *) dst_page;\n\n}\n\n\n/* \\fn static void lq_sg_complete(struct aes_container *aes_con) \n * \\ingroup IFX_AES_FUNCTIONS\n * \\brief Free the used up memory after encryt/decrypt.\n*/\n\nstatic void lq_sg_complete(struct aes_container *aes_con) \n{\n    unsigned long queue_flag;\n\n    spin_lock_irqsave(&aes_queue->lock, queue_flag);\n    kfree(aes_con);\n    spin_unlock_irqrestore(&aes_queue->lock, queue_flag);\n}\n\n/* \\fn static inline struct aes_container *aes_container_cast (\n *                     struct scatterlist *dst)\n * \\ingroup IFX_AES_FUNCTIONS\n * \\brief Locate the structure aes_container in memory.\n * \\param *areq Pointer to memory location where ablkcipher_request is located\n * \\return *aes_cointainer The function pointer to aes_container\n*/\nstatic inline struct aes_container *aes_container_cast (\n\t\tstruct ablkcipher_request *areq)\n{\n    return container_of(areq, struct aes_container, arequest);\n}\n\n\n/* \\fn static int process_next_packet(struct aes_container *aes_con, struct ablkcipher_request *areq,\n * \\                                  int state)\n * \\ingroup IFX_AES_FUNCTIONS\n * \\brief Process next packet to be encrypt/decrypt\n * \\param *aes_con  AES container structure\n * \\param *areq Pointer to memory location where ablkcipher_request is located \n * \\param state The state of the current packet (part of scatterlist or new packet)\n * \\return -EINVAL: error, -EINPROGRESS: Crypto still running, 1: no more scatterlist \n*/\n\nstatic int process_next_packet(struct aes_container *aes_con, struct ablkcipher_request *areq,\n                               int state)\n{\n    u8 *iv;\n    int mode, dir, err = -EINVAL;\n    unsigned long queue_flag;\n    u32 inc, nbytes, remain, chunk_size;\n    struct scatterlist *src = NULL;\n    struct scatterlist *dst = NULL;\n    struct crypto_ablkcipher *cipher;\n    struct aes_ctx *ctx;\n\n    spin_lock_irqsave(&aes_queue->lock, queue_flag);\n\n    dir = aes_con->encdec;\n    mode = aes_con->mode;\n    iv = aes_con->iv;\n \n    if (state & PROCESS_SCATTER) {\n        src = scatterwalk_sg_next(areq->src);\n        dst = scatterwalk_sg_next(areq->dst);\n \n        if (!src || !dst) {\n            spin_unlock_irqrestore(&aes_queue->lock, queue_flag);\n            return 1;\n        }\n    }\n    else if (state & PROCESS_NEW_PACKET) { \n        src = areq->src;\n        dst = areq->dst;\n    }\n\n    remain = aes_con->bytes_processed;\n    chunk_size = src->length;\n\n    if (remain > DEU_MAX_PACKET_SIZE)\n       inc = DEU_MAX_PACKET_SIZE;\n    else if (remain > chunk_size)\n       inc = chunk_size;\n    else\n       inc = remain;\n\n    remain -= inc;\n    aes_con->nbytes = inc;\n \n    if (state & PROCESS_SCATTER) {\n        aes_con->src_buf += aes_con->nbytes;\n        aes_con->dst_buf += aes_con->nbytes;\n    }\n\n    lq_sg_init(aes_con, src, dst);\n\n    nbytes = aes_con->nbytes;\n\n    //printk(\"debug - Line: %d, func: %s, reqsize: %d, scattersize: %d\\n\",\n    //          __LINE__, __func__, nbytes, chunk_size);\n\n    cipher = crypto_ablkcipher_reqtfm(areq);\n    ctx = crypto_ablkcipher_ctx(cipher);\n\n\n    if (aes_queue->hw_status == AES_IDLE)\n        aes_queue->hw_status = AES_STARTED;\n\n    aes_con->bytes_processed -= aes_con->nbytes;\n    err = ablkcipher_enqueue_request(&aes_queue->list, &aes_con->arequest);\n    if (err == -EBUSY) {\n        spin_unlock_irqrestore(&aes_queue->lock, queue_flag);\n        printk(\"Failed to enqueue request, ln: %d, err: %d\\n\",\n                __LINE__, err);\n        return -EINVAL;\n    }\n\n    spin_unlock_irqrestore(&aes_queue->lock, queue_flag);\n\n    err = lq_deu_aes_core(ctx, aes_con->dst_buf, aes_con->src_buf, iv, nbytes, dir, mode);\n    return err;\n\n}\n\n/* \\fn static void process_queue (unsigned long data)\n * \\ingroup IFX_AES_FUNCTIONS\n * \\brief tasklet to signal the dequeuing of the next packet to be processed\n * \\param unsigned long data Not used\n * \\return void \n*/\n\nstatic void process_queue(unsigned long data)\n{\n\n    DEU_WAKEUP_EVENT(deu_dma_priv.deu_thread_wait, AES_ASYNC_EVENT,\n                deu_dma_priv.aes_event_flags);\n}\n\n\n/* \\fn static int aes_crypto_thread (void *data)\n * \\ingroup IFX_AES_FUNCTIONS\n * \\brief AES thread that handles crypto requests from upper layer & DMA\n * \\param *data Not used\n * \\return -EINVAL: DEU failure, -EBUSY: DEU HW busy, 0: exit thread\n*/\nstatic int aes_crypto_thread (void *data)\n{\n    struct aes_container *aes_con = NULL;\n    struct ablkcipher_request *areq = NULL;\n    int err;\n    unsigned long queue_flag;\n    \n    daemonize(\"lq_aes_thread\");\n    printk(\"AES Queue Manager Starting\\n\");\n\n    while (1)\n    {\n        DEU_WAIT_EVENT(deu_dma_priv.deu_thread_wait, AES_ASYNC_EVENT, \n                       deu_dma_priv.aes_event_flags);\n\n        spin_lock_irqsave(&aes_queue->lock, queue_flag);\n   \n        /* wait to prevent starting a crypto session before\n        * exiting the dma interrupt thread.\n        */\n        if (aes_queue->hw_status == AES_STARTED) {\n            areq = ablkcipher_dequeue_request(&aes_queue->list);\n            aes_con = aes_container_cast(areq);\n            aes_queue->hw_status = AES_BUSY;\n        }\n        else if (aes_queue->hw_status == AES_IDLE) {\n            areq = ablkcipher_dequeue_request(&aes_queue->list);\n            aes_con = aes_container_cast(areq);\n            aes_queue->hw_status = AES_STARTED;\n        }\n        else if (aes_queue->hw_status == AES_BUSY) {\n            areq = ablkcipher_dequeue_request(&aes_queue->list);\n            aes_con = aes_container_cast(areq);\n\t}\n        else if (aes_queue->hw_status == AES_COMPLETED) {\n            lq_sg_complete(aes_con);\n            aes_queue->hw_status = AES_IDLE;\n            areq->base.complete(&areq->base, 0);\n            spin_unlock_irqrestore(&aes_queue->lock, queue_flag);\n\t    return 0;\n\t}\n        //printk(\"debug ln: %d, bytes proc: %d\\n\", __LINE__, aes_con->bytes_processed);\n        spin_unlock_irqrestore(&aes_queue->lock, queue_flag);\n\n        if (!aes_con) {\n           printk(\"AES_CON return null\\n\");\n           goto aes_done;\n\t}\n\n        if (aes_con->bytes_processed == 0) {\n            goto aes_done;\n        }\n       \n        /* Process new packet or the next packet in a scatterlist */\n        if (aes_con->flag & PROCESS_NEW_PACKET) {\n           aes_con->flag = PROCESS_SCATTER;\n           err = process_next_packet(aes_con, areq, PROCESS_NEW_PACKET);\n        }\n        else \n            err = process_next_packet(aes_con, areq, PROCESS_SCATTER);\n \n        if (err == -EINVAL) {\n            areq->base.complete(&areq->base, err);\n            lq_sg_complete(aes_con);\n            printk(\"src/dst returned -EINVAL in func: %s\\n\", __func__);\n        }\n        else if (err > 0) {\n            printk(\"src/dst returned zero in func: %s\\n\", __func__);\n            goto aes_done; \n        }\n        \n\tcontinue;\n\naes_done:\n        //printk(\"debug line - %d, func: %s, qlen: %d\\n\", __LINE__, __func__, aes_queue->list.qlen);\n        areq->base.complete(&areq->base, 0);    \n        lq_sg_complete(aes_con);\n\n        spin_lock_irqsave(&aes_queue->lock, queue_flag);\n        if (aes_queue->list.qlen > 0) {\n            spin_unlock_irqrestore(&aes_queue->lock, queue_flag);\n            tasklet_schedule(&aes_queue->aes_task); \n        }\n        else {\n            aes_queue->hw_status = AES_IDLE;\n            spin_unlock_irqrestore(&aes_queue->lock, queue_flag);\n        }\n    } //while(1)\n    \n    return 0;\n} \n\n/* \\fn static int lq_aes_queue_mgr(struct aes_ctx *ctx, struct ablkcipher_request *areq, \n                            u8 *iv, int dir, int mode)\n * \\ingroup IFX_AES_FUNCTIONS\n * \\brief starts the process of queuing DEU requests\n * \\param *ctx crypto algo contax\n * \\param *areq Pointer to the balkcipher requests\n * \\param *iv Pointer to intput vector location\n * \\param dir Encrypt/Decrypt\n * \\mode The mode AES algo is running\n * \\return 0 if success\n*/\n\nstatic int lq_aes_queue_mgr(struct aes_ctx *ctx, struct ablkcipher_request *areq, \n                            u8 *iv, int dir, int mode)\n{\n    int err = -EINVAL; \n    unsigned long queue_flag;\n    struct scatterlist *src = areq->src;\n    struct scatterlist *dst = areq->dst;\n    struct aes_container *aes_con = NULL;\n    u32 remain, inc, nbytes = areq->nbytes;\n    u32 chunk_bytes = src->length;\n    \n \n    aes_con = (struct aes_container *)kmalloc(sizeof(struct aes_container),\n    \t                                       GFP_KERNEL);\n\n    if (!(aes_con)) {\n        printk(\"Cannot allocate memory for AES container, fn %s, ln %d\\n\",\n\t\t__func__, __LINE__);\n\treturn -ENOMEM;\n    }\n\n    /* AES encrypt/decrypt mode */\n    if (mode == 5) {\n        nbytes = AES_BLOCK_SIZE;\n        chunk_bytes = AES_BLOCK_SIZE;\n        mode = 0;\n    }\n\n    aes_con->bytes_processed = nbytes;\n    aes_con->arequest = *(areq);\n    remain = nbytes;\n\n    //printk(\"debug - Line: %d, func: %s, reqsize: %d, scattersize: %d\\n\",\n    //        __LINE__, __func__, nbytes, chunk_bytes);\n\n    if (remain > DEU_MAX_PACKET_SIZE) \n       inc = DEU_MAX_PACKET_SIZE;\n    else if (remain > chunk_bytes)\n       inc = chunk_bytes; \n    else\n       inc = remain;\n         \n    remain -= inc;\n    lq_sg_init(aes_con, src, dst);  \n\n    if (remain <= 0)\n        aes_con->complete = 1;\n    else\n        aes_con->complete = 0;\n\n    aes_con->nbytes = inc;\n    aes_con->iv = iv;\n    aes_con->mode = mode;\n    aes_con->encdec = dir;\n \n    spin_lock_irqsave(&aes_queue->lock, queue_flag);\n\n    if (aes_queue->hw_status == AES_STARTED || aes_queue->hw_status == AES_BUSY ||\n             aes_queue->list.qlen > 0) {\n\n        aes_con->flag = PROCESS_NEW_PACKET;\n        err = ablkcipher_enqueue_request(&aes_queue->list, &aes_con->arequest);\n\n         /* max queue length reached */\n        if (err == -EBUSY) {\n            spin_unlock_irqrestore(&aes_queue->lock, queue_flag);\n            printk(\"Unable to enqueue request ln: %d, err: %d\\n\", __LINE__, err);\n             return err;\n         }\n\n        spin_unlock_irqrestore(&aes_queue->lock, queue_flag);\n        return -EINPROGRESS;\n    }\n    else if (aes_queue->hw_status == AES_IDLE) \n        aes_queue->hw_status = AES_STARTED;\n\n    aes_con->flag = PROCESS_SCATTER;\n    aes_con->bytes_processed -= aes_con->nbytes;\n    /* or enqueue the whole structure so as to get back the info \n     * at the moment that it's queued. nbytes might be different */\n    err = ablkcipher_enqueue_request(&aes_queue->list, &aes_con->arequest);\n\n    if (err == -EBUSY) {\n        spin_unlock_irqrestore(&aes_queue->lock, queue_flag);\n        printk(\"Unable to enqueue request ln: %d, err: %d\\n\", __LINE__, err);\n        return err;\n    }\n\n    spin_unlock_irqrestore(&aes_queue->lock, queue_flag);\n    return lq_deu_aes_core(ctx, aes_con->dst_buf, aes_con->src_buf, iv, inc, dir, mode);\n\n}\n\n/* \\fn static int aes_setkey(struct crypto_ablkcipher *tfm, const u8 *in_key,\n *                     unsigned int keylen)\n * \\ingroup IFX_AES_FUNCTIONS\n * \\brief Sets AES key\n * \\param *tfm Pointer to the ablkcipher transform\n * \\param *in_key Pointer to input keys\n * \\param key_len Length of the AES keys\n * \\return 0 is success, -EINVAL if bad key length\n*/\n\nstatic int aes_setkey(struct crypto_ablkcipher *tfm, const u8 *in_key,\n                      unsigned int keylen)\n{\n    struct aes_ctx *ctx = crypto_ablkcipher_ctx(tfm); \n    unsigned long *flags = (unsigned long *) &tfm->base.crt_flags;\n\n    DPRINTF(2, \"set_key in %s\\n\", __FILE__);\n\n    if (keylen != 16 && keylen != 24 && keylen != 32) {\n        *flags |= CRYPTO_TFM_RES_BAD_KEY_LEN;\n        return -EINVAL;\n    }\n\n    ctx->key_length = keylen;\n    DPRINTF(0, \"ctx @%p, keylen %d, ctx->key_length %d\\n\", ctx, keylen, ctx->key_length);\n    memcpy ((u8 *) (ctx->buf), in_key, keylen);\n\n    return 0;\n\n}\n\n/* \\fn static int aes_generic_setkey(struct crypto_ablkcipher *tfm, const u8 *in_key,\n *                     unsigned int keylen)\n * \\ingroup IFX_AES_FUNCTIONS\n * \\brief Sets AES key\n * \\param *tfm Pointer to the ablkcipher transform\n * \\param *key Pointer to input keys\n * \\param keylen Length of AES keys\n * \\return 0 is success, -EINVAL if bad key length\n*/\n\nstatic int aes_generic_setkey(struct crypto_ablkcipher *tfm, const u8 *key,\n                              unsigned int keylen)\n{\n   return aes_setkey(tfm, key, keylen);\n}\n\n/* \\fn static int rfc3686_aes_setkey(struct crypto_ablkcipher *tfm, const u8 *in_key,\n *                     unsigned int keylen)\n * \\ingroup IFX_AES_FUNCTIONS\n * \\brief Sets AES key\n * \\param *tfm Pointer to the ablkcipher transform\n * \\param *in_key Pointer to input keys\n * \\param key_len Length of the AES keys\n * \\return 0 is success, -EINVAL if bad key length\n*/\n\nstatic int rfc3686_aes_setkey(struct crypto_ablkcipher *tfm,\n                             const u8 *in_key, unsigned int keylen)\n{\n    struct aes_ctx *ctx = crypto_ablkcipher_ctx(tfm);\n    unsigned long *flags = (unsigned long *)&tfm->base.crt_flags;\n\n    DPRINTF(2, \"ctr_rfc3686_aes_set_key in %s\\n\", __FILE__);\n\n    memcpy(ctx->nonce, in_key + (keylen - CTR_RFC3686_NONCE_SIZE),\n           CTR_RFC3686_NONCE_SIZE);\n\n    keylen -= CTR_RFC3686_NONCE_SIZE; // remove 4 bytes of nonce\n\n    if (keylen != 16 && keylen != 24 && keylen != 32) {\n        *flags |= CRYPTO_TFM_RES_BAD_KEY_LEN;\n        return -EINVAL;\n    }\n\n    ctx->key_length = keylen;\n\n    memcpy ((u8 *) (ctx->buf), in_key, keylen);\n\n    return 0;\n}\n\n/* \\fn static int aes_encrypt(struct ablkcipher_request *areq)\n * \\ingroup IFX_AES_FUNCTIONS\n * \\brief Encrypt function for AES algo\n * \\param *areq Pointer to ablkcipher request in memory\n * \\return 0 is success, -EINPROGRESS if encryting, EINVAL if failure\n*/\n\nstatic int aes_encrypt (struct ablkcipher_request *areq)\n{\n    struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);\n    struct aes_ctx *ctx = crypto_ablkcipher_ctx(cipher);\n\n    return lq_aes_queue_mgr(ctx, areq, NULL, CRYPTO_DIR_ENCRYPT, 5);\n\n}\n\n/* \\fn static int aes_decrypt(struct ablkcipher_request *areq)\n * \\ingroup IFX_AES_FUNCTIONS\n * \\brief Decrypt function for AES algo\n * \\param *areq Pointer to ablkcipher request in memory\n * \\return 0 is success, -EINPROGRESS if encryting, EINVAL if failure\n*/\nstatic int aes_decrypt (struct ablkcipher_request *areq)\n{\n    struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);\n    struct aes_ctx *ctx = crypto_ablkcipher_ctx(cipher);\n\n    return lq_aes_queue_mgr(ctx, areq, NULL, CRYPTO_DIR_DECRYPT, 5);\n}\n\n/* \\fn static int ecb_aes_decrypt(struct ablkcipher_request *areq)\n * \\ingroup IFX_AES_FUNCTIONS\n * \\brief Encrypt function for AES algo\n * \\param *areq Pointer to ablkcipher request in memory\n * \\return 0 is success, -EINPROGRESS if encryting, EINVAL if failure\n*/\n\nstatic int ecb_aes_encrypt (struct ablkcipher_request *areq)\n{\n    struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);\n    struct aes_ctx *ctx = crypto_ablkcipher_ctx(cipher);\n\n    return lq_aes_queue_mgr(ctx, areq, areq->info, CRYPTO_DIR_ENCRYPT, 0);\n\n}\n/* \\fn static int ecb_aes_decrypt(struct ablkcipher_request *areq)\n * \\ingroup IFX_AES_FUNCTIONS\n * \\brief Decrypt function for AES algo\n * \\param *areq Pointer to ablkcipher request in memory\n * \\return 0 is success, -EINPROGRESS if encryting, EINVAL if failure\n*/ \nstatic int ecb_aes_decrypt(struct ablkcipher_request *areq)\n\n{\n    struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);\n    struct aes_ctx *ctx = crypto_ablkcipher_ctx(cipher);\n\n    return lq_aes_queue_mgr(ctx, areq, areq->info, CRYPTO_DIR_DECRYPT, 0);\n}\n\n/* \\fn static int cbc_aes_encrypt(struct ablkcipher_request *areq)\n * \\ingroup IFX_AES_FUNCTIONS\n * \\brief Encrypt function for AES algo\n * \\param *areq Pointer to ablkcipher request in memory\n * \\return 0 is success, -EINPROGRESS if encryting, EINVAL if failure\n*/\n\nstatic int cbc_aes_encrypt (struct ablkcipher_request *areq)\n{\n    struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);\n    struct aes_ctx *ctx = crypto_ablkcipher_ctx(cipher);\n\n    return lq_aes_queue_mgr(ctx, areq, areq->info, CRYPTO_DIR_ENCRYPT, 1);\n\n}\n\n/* \\fn static int cbc_aes_decrypt(struct ablkcipher_request *areq)\n * \\ingroup IFX_AES_FUNCTIONS\n * \\brief Decrypt function for AES algo\n * \\param *areq Pointer to ablkcipher request in memory\n * \\return 0 is success, -EINPROGRESS if encryting, EINVAL if failure\n*/\n\nstatic int cbc_aes_decrypt(struct ablkcipher_request *areq)\n{\n    struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);\n    struct aes_ctx *ctx = crypto_ablkcipher_ctx(cipher);\n\n    return lq_aes_queue_mgr(ctx, areq, areq->info, CRYPTO_DIR_DECRYPT, 1);\n}\n#if 0\nstatic int ofb_aes_encrypt (struct ablkcipher_request *areq)\n{\n    struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);\n    struct aes_ctx *ctx = crypto_ablkcipher_ctx(cipher);\n\n    return lq_aes_queue_mgr(ctx, areq, areq->info, CRYPTO_DIR_ENCRYPT, 2);\n\n}\n\nstatic int ofb_aes_decrypt(struct ablkcipher_request *areq)\n{\n    struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);\n    struct aes_ctx *ctx = crypto_ablkcipher_ctx(cipher);\n\n    return lq_aes_queue_mgr(ctx, areq, areq->info, CRYPTO_DIR_DECRYPT, 2);\n}\n\nstatic int cfb_aes_encrypt (struct ablkcipher_request *areq)\n{\n    struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);\n    struct aes_ctx *ctx = crypto_ablkcipher_ctx(cipher);\n\n    return lq_aes_queue_mgr(ctx, areq, areq->info, CRYPTO_DIR_ENCRYPT, 3);\n\n}\n\nstatic int cfb_aes_decrypt(struct ablkcipher_request *areq)\n{\n    struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);\n    struct aes_ctx *ctx = crypto_ablkcipher_ctx(cipher);\n\n    return lq_aes_queue_mgr(ctx, areq, areq->info, CRYPTO_DIR_DECRYPT, 3);\n}\n#endif\t\n\n/* \\fn static int ctr_aes_encrypt(struct ablkcipher_request *areq)\n * \\ingroup IFX_AES_FUNCTIONS\n * \\brief Encrypt function for AES algo\n * \\param *areq Pointer to ablkcipher request in memory\n * \\return 0 is success, -EINPROGRESS if encryting, EINVAL if failure\n*/\n\nstatic int ctr_aes_encrypt (struct ablkcipher_request *areq)\n{\n    struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);\n    struct aes_ctx *ctx = crypto_ablkcipher_ctx(cipher);\n   \n    return lq_aes_queue_mgr(ctx, areq, areq->info, CRYPTO_DIR_ENCRYPT, 4);\n\n}\n\n/* \\fn static int ctr_aes_decrypt(struct ablkcipher_request *areq)\n * \\ingroup IFX_AES_FUNCTIONS\n * \\brief Decrypt function for AES algo\n * \\param *areq Pointer to ablkcipher request in memory\n * \\return 0 is success, -EINPROGRESS if encryting, EINVAL if failure\n*/\n\nstatic int ctr_aes_decrypt(struct ablkcipher_request *areq)\n{\n    struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);\n    struct aes_ctx *ctx = crypto_ablkcipher_ctx(cipher);\n\n    return lq_aes_queue_mgr(ctx, areq, areq->info, CRYPTO_DIR_DECRYPT, 4);\n}\n\n/* \\fn static int rfc3686_aes_encrypt(struct ablkcipher_request *areq)\n * \\ingroup IFX_AES_FUNCTIONS\n * \\brief Encrypt function for AES algo\n * \\param *areq Pointer to ablkcipher request in memory\n * \\return 0 is success, -EINPROGRESS if encryting, EINVAL if failure\n*/\n\nstatic int rfc3686_aes_encrypt(struct ablkcipher_request *areq)\n{\n    struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);\n    struct aes_ctx *ctx = crypto_ablkcipher_ctx(cipher);\n    int ret;\n    u8 *info = areq->info;\n    u8 rfc3686_iv[16];\n\n    memcpy(rfc3686_iv, ctx->nonce, CTR_RFC3686_NONCE_SIZE);\n    memcpy(rfc3686_iv + CTR_RFC3686_NONCE_SIZE, info, CTR_RFC3686_IV_SIZE);\n\n    /* initialize counter portion of counter block */\n    *(__be32 *)(rfc3686_iv + CTR_RFC3686_NONCE_SIZE + CTR_RFC3686_IV_SIZE) =\n        cpu_to_be32(1);\n\n    areq->info = rfc3686_iv;\n    ret = lq_aes_queue_mgr(ctx, areq, areq->info, CRYPTO_DIR_ENCRYPT, 4);\n    areq->info = info;\n    return ret;\n}\n\n/* \\fn static int rfc3686_aes_decrypt(struct ablkcipher_request *areq)\n * \\ingroup IFX_AES_FUNCTIONS\n * \\brief Decrypt function for AES algo\n * \\param *areq Pointer to ablkcipher request in memory\n * \\return 0 is success, -EINPROGRESS if encryting, EINVAL if failure\n*/\n\nstatic int rfc3686_aes_decrypt(struct ablkcipher_request *areq)\n{\n    struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);\n    struct aes_ctx *ctx = crypto_ablkcipher_ctx(cipher);\n    int ret;\n    u8 *info = areq->info;\n    u8 rfc3686_iv[16];\n\n    /* set up counter block */\n    memcpy(rfc3686_iv, ctx->nonce, CTR_RFC3686_NONCE_SIZE);\n    memcpy(rfc3686_iv + CTR_RFC3686_NONCE_SIZE, info, CTR_RFC3686_IV_SIZE);\n\n    /* initialize counter portion of counter block */\n    *(__be32 *)(rfc3686_iv + CTR_RFC3686_NONCE_SIZE + CTR_RFC3686_IV_SIZE) =\n        cpu_to_be32(1);\n\n    areq->info = rfc3686_iv;\n    ret = lq_aes_queue_mgr(ctx, areq, areq->info, CRYPTO_DIR_DECRYPT, 4);\n    areq->info = info;\n    return ret;\n}\n\nstruct lq_aes_alg {\n    struct crypto_alg alg;\n};\n\n/* AES supported algo array */\nstatic struct lq_aes_alg aes_drivers_alg[] = {\n     {\n         .alg = {\n           .cra_name \t    = \"aes\",\n           .cra_driver_name = \"ifxdeu-aes\",\n           .cra_flags       = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_KERN_DRIVER_ONLY | CRYPTO_ALG_ASYNC,\n           .cra_blocksize   = AES_BLOCK_SIZE,\n           .cra_ctxsize     = sizeof(struct aes_ctx),\n           .cra_type        = &crypto_ablkcipher_type,\n           .cra_priority    = 300,\n           .cra_module      = THIS_MODULE,\n           .cra_ablkcipher = {\n                                .setkey = aes_setkey,\n                                .encrypt = aes_encrypt,\n                                .decrypt = aes_decrypt,\n                                .geniv = \"eseqiv\",\n                                .min_keysize = AES_MIN_KEY_SIZE,\n                                .max_keysize = AES_MAX_KEY_SIZE,\n                                .ivsize = AES_BLOCK_SIZE,\n             }\n          }\n     },{\n     .alg = {\n           .cra_name        = \"ecb(aes)\",\n           .cra_driver_name = \"ifxdeu-ecb(aes)\",\n           .cra_flags       = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_KERN_DRIVER_ONLY | CRYPTO_ALG_ASYNC,\n           .cra_blocksize   = AES_BLOCK_SIZE,\n           .cra_ctxsize     = sizeof(struct aes_ctx),\n           .cra_type        = &crypto_ablkcipher_type,\n           .cra_priority    = 400,\n           .cra_module      = THIS_MODULE,\n           .cra_ablkcipher = {\n                                .setkey = aes_generic_setkey,\n                                .encrypt = ecb_aes_encrypt,\n                                .decrypt = ecb_aes_decrypt,\n                                .geniv = \"eseqiv\",\n                                .min_keysize = AES_MIN_KEY_SIZE,\n                                .max_keysize = AES_MAX_KEY_SIZE,\n                                .ivsize = AES_BLOCK_SIZE,\n             }      \n          }\n     },{\n         .alg = {\n           .cra_name        = \"cbc(aes)\",\n           .cra_driver_name = \"ifxdeu-cbc(aes)\",\n           .cra_flags       = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_KERN_DRIVER_ONLY | CRYPTO_ALG_ASYNC,\n           .cra_blocksize   = AES_BLOCK_SIZE,\n           .cra_ctxsize     = sizeof(struct aes_ctx),\n           .cra_type        = &crypto_ablkcipher_type,\n           .cra_priority    = 400,\n           .cra_module      = THIS_MODULE,\n           .cra_ablkcipher = {\n                                .setkey = aes_generic_setkey,\n                                .encrypt = cbc_aes_encrypt,\n                                .decrypt = cbc_aes_decrypt,\n                                .geniv = \"eseqiv\",\n                                .min_keysize = AES_MIN_KEY_SIZE,\n                                .max_keysize = AES_MAX_KEY_SIZE,\n                                .ivsize = AES_BLOCK_SIZE,\n                }\n          }\n     },{\n         .alg = {\n           .cra_name        = \"ctr(aes)\",\n           .cra_driver_name = \"ifxdeu-ctr(aes)\",\n           .cra_flags       = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_KERN_DRIVER_ONLY | CRYPTO_ALG_ASYNC,\n           .cra_blocksize   = AES_BLOCK_SIZE,\n           .cra_ctxsize     = sizeof(struct aes_ctx),\n           .cra_type        = &crypto_ablkcipher_type,\n           .cra_priority    = 400,\n           .cra_module      = THIS_MODULE,\n           .cra_ablkcipher = {\n                                .setkey = aes_generic_setkey,\n                                .encrypt = ctr_aes_encrypt,\n                                .decrypt = ctr_aes_decrypt,\n                                .geniv = \"eseqiv\",\n                                .min_keysize = AES_MIN_KEY_SIZE,\n                                .max_keysize = AES_MAX_KEY_SIZE,\n                                .ivsize = AES_BLOCK_SIZE,\n                }\n         }\n     },{\n     .alg = {\n           .cra_name        = \"rfc3686(ctr(aes))\",\n           .cra_driver_name = \"ifxdeu-rfc3686(ctr(aes))\",\n           .cra_flags       = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_KERN_DRIVER_ONLY | CRYPTO_ALG_ASYNC,\n           .cra_blocksize   = AES_BLOCK_SIZE,\n           .cra_ctxsize     = sizeof(struct aes_ctx),\n           .cra_type        = &crypto_ablkcipher_type,\n           .cra_priority    = 400,\n           .cra_module      = THIS_MODULE,\n           .cra_ablkcipher = {\n                                .setkey = rfc3686_aes_setkey,\n                                .encrypt = rfc3686_aes_encrypt,\n                                .decrypt = rfc3686_aes_decrypt,\n                                .geniv = \"eseqiv\",\n                                .min_keysize = AES_MIN_KEY_SIZE,\n                                .max_keysize = CTR_RFC3686_MAX_KEY_SIZE,\n\t\t\t\t//.max_keysize = AES_MAX_KEY_SIZE,\n                                //.ivsize = CTR_RFC3686_IV_SIZE,\n\t\t\t\t.ivsize = AES_BLOCK_SIZE,  // else cannot reg\n               }\n         }\n      }\n};\n\n/* \\fn int __init lqdeu_async_aes_init (void)\n * \\ingroup IFX_AES_FUNCTIONS\n * \\brief Initializes the Async. AES driver\n * \\return 0 is success, -EINPROGRESS if encryting, EINVAL if failure\n*/\n\nint __init lqdeu_async_aes_init (void)\n{\n    int i, j, ret = -EINVAL; \n\n#define IFX_DEU_DRV_VERSION  \"2.0.0\"\n    printk(KERN_INFO \"Lantiq Technologies DEU Driver version %s\\n\", IFX_DEU_DRV_VERSION);\n\n    for (i = 0; i < ARRAY_SIZE(aes_drivers_alg); i++) {\n        ret = crypto_register_alg(&aes_drivers_alg[i].alg);\n\tprintk(\"driver: %s\\n\", aes_drivers_alg[i].alg.cra_name);\n        if (ret)\n            goto aes_err;\n    }\n\n    aes_chip_init();\n\n    CRTCL_SECT_INIT;\n\n\n    printk (KERN_NOTICE \"Lantiq DEU AES initialized %s %s.\\n\", \n           disable_multiblock ? \"\" : \" (multiblock)\", disable_deudma ? \"\" : \" (DMA)\");\n    \n    return ret;\n\naes_err:\n    \n    for (j = 0; j < i; j++) \n        crypto_unregister_alg(&aes_drivers_alg[j].alg);\n    \n    printk(KERN_ERR \"Lantiq %s driver initialization failed!\\n\", (char *)&aes_drivers_alg[i].alg.cra_driver_name);\n    return ret;\n\nctr_rfc3686_aes_err:\n    for (i = 0; i < ARRAY_SIZE(aes_drivers_alg); i++) {\n        if (!strcmp((char *)&aes_drivers_alg[i].alg.cra_name, \"rfc3686(ctr(aes))\"))\n            crypto_unregister_alg(&aes_drivers_alg[j].alg);\n    }\n    printk (KERN_ERR \"Lantiq ctr_rfc3686_aes initialization failed!\\n\");\n    return ret;\n}\n\n/*! \\fn void __exit ifxdeu_fini_aes (void)\n *  \\ingroup IFX_AES_FUNCTIONS\n *  \\brief unregister aes driver\n*/\nvoid __exit lqdeu_fini_async_aes (void)\n{\n    int i;\n  \n    for (i = 0; i < ARRAY_SIZE(aes_drivers_alg); i++)\n        crypto_unregister_alg(&aes_drivers_alg[i].alg);\n\n    aes_queue->hw_status = AES_COMPLETED;\n\n    DEU_WAKEUP_EVENT(deu_dma_priv.deu_thread_wait, AES_ASYNC_EVENT,\n                                 deu_dma_priv.aes_event_flags);   \n\n    kfree(aes_queue); \n\n}\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-deu/src/ifxmips_async_des.c",
    "content": "/******************************************************************************\n**\n** FILE NAME    : ifxmips_async_des.c\n** PROJECT      : IFX UEIP\n** MODULES      : DEU Module\n**\n** DATE         : October 11, 2010\n** AUTHOR       : Mohammad Firdaus\n** DESCRIPTION  : Data Encryption Unit Driver for DES Algorithm\n** COPYRIGHT    :       Copyright (c) 2010\n**                      Infineon Technologies AG\n**                      Am Campeon 1-12, 85579 Neubiberg, Germany\n**\n**    This program is free software; you can redistribute it and/or modify\n**    it under the terms of the GNU General Public License as published by\n**    the Free Software Foundation; either version 2 of the License, or\n**    (at your option) any later version.\n**\n** HISTORY\n** $Date        $Author             $Comment\n** 08,Sept 2009 Mohammad Firdaus    Initial UEIP release\n** 11, Oct 2010 Mohammad Firdaus    Kernel Port incl. Async. Ablkcipher mode\n** 21,March 2011 Mohammad Firdaus   Changes for Kernel 2.6.32 and IPSec integration\n*******************************************************************************/\n/*!\n \\defgroup IFX_DEU IFX_DEU_DRIVERS\n \\ingroup API\n \\brief ifx DEU driver module\n*/\n\n/*!\n  \\file ifxmips_async_des.c\n  \\ingroup IFX_DEU\n  \\brief DES Encryption Driver main file\n*/\n\n/*!\n \\defgroup IFX_DES_FUNCTIONS IFX_DES_FUNCTIONS\n \\ingroup IFX_DEU\n \\brief IFX DES driver Functions\n*/\n\n#include <linux/wait.h>\n#include <linux/crypto.h>\n#include <linux/kernel.h>\n#include <linux/interrupt.h>\n#include <linux/spinlock.h>\n#include <linux/list.h>\n#include <crypto/ctr.h>\n#include <crypto/aes.h>\n#include <crypto/algapi.h>\n#include <crypto/scatterwalk.h>\n\n#include <asm/ifx/ifx_regs.h>\n#include <asm/ifx/ifx_types.h>\n#include <asm/ifx/common_routines.h>\n#include <asm/ifx/irq.h>\n#include <asm/ifx/ifx_pmu.h>\n#include <asm/ifx/ifx_gpio.h>\n#include <asm/kmap_types.h>\n\n#include \"ifxmips_deu.h\"\n\n#if defined(CONFIG_DANUBE)\n#include \"ifxmips_deu_danube.h\"\nextern int ifx_danube_pre_1_4;\n#elif defined(CONFIG_AR9)\n#include \"ifxmips_deu_ar9.h\"\n#elif defined(CONFIG_VR9) || defined(CONFIG_AR10)\n#include \"ifxmips_deu_vr9.h\"\n#else\n#error \"Unkown platform\"\n#endif\n\n/* DMA specific header and variables */\n\nspinlock_t des_lock;\n#define CRTCL_SECT_INIT        spin_lock_init(&des_lock)\n#define CRTCL_SECT_START       spin_lock_irqsave(&des_lock, flag)\n#define CRTCL_SECT_END         spin_unlock_irqrestore(&des_lock, flag)\n\n/* Preprocessor declerations */\n#ifdef CRYPTO_DEBUG\nextern char debug_level;\n#define DPRINTF(level, format, args...) if (level < debug_level) printk(KERN_INFO \"[%s %s %d]: \" format, __FILE__, __func__, __LINE__, ##args);\n#else\n#define DPRINTF(level, format, args...)\n#endif\n//#define DES_3DES_START  IFX_DES_CON\n#define DES_KEY_SIZE            8\n#define DES_EXPKEY_WORDS        32\n#define DES_BLOCK_SIZE          8\n#define DES3_EDE_KEY_SIZE       (3 * DES_KEY_SIZE)\n#define DES3_EDE_EXPKEY_WORDS   (3 * DES_EXPKEY_WORDS)\n#define DES3_EDE_BLOCK_SIZE     DES_BLOCK_SIZE\n\n/* Function Declaration to prevent warning messages */\nvoid des_chip_init (void);\nu32 endian_swap(u32 input);\nu32 input_swap(u32 input);\nint aes_memory_allocate(int value);\nint des_memory_allocate(int value);\nvoid memory_release(u32 *buffer);\nu32* memory_alignment(const u8 *arg, u32 *buff_alloc, int in_out, int nbytes);\nvoid aes_dma_memory_copy(u32 *outcopy, u32 *out_dma, u8 *out_arg, int nbytes);\nvoid des_dma_memory_copy(u32 *outcopy, u32 *out_dma, u8 *out_arg, int nbytes);\n\nstatic int lq_deu_des_core (void *ctx_arg, u8 *out_arg, const u8 *in_arg,\n             u8 *iv_arg, u32 nbytes, int encdec, int mode);\n\nstruct des_ctx {\n        int controlr_M;\n        int key_length;\n        u8 iv[DES_BLOCK_SIZE];\n        u32 expkey[DES3_EDE_EXPKEY_WORDS];\n};\n\n\nstatic int disable_multiblock = 0;\nmodule_param(disable_multiblock, int, 0);\n\nstatic int disable_deudma = 1;\n\nstruct des_container {\n    u8 *iv;\n    u8 *dst_buf;\n    u8 *src_buf;\n    int mode;\n    int encdec;\n    int complete;\n    int flag;\n\n    u32 bytes_processed;\n    u32 nbytes;\n\n    struct ablkcipher_request arequest;\n};\n\ndes_priv_t *des_queue;\nextern deu_drv_priv_t deu_dma_priv;\n\nvoid hexdump1(unsigned char *buf, unsigned int len)\n{\n        print_hex_dump(KERN_CONT, \"\", DUMP_PREFIX_OFFSET,\n                        16, 1,\n                        buf, len, false);\n}\n\n\n/*! \\fn int lq_des_setkey(struct crypto_ablkcipher *tfm, const u8 *key, unsigned int keylen)\n *  \\ingroup IFX_DES_FUNCTIONS\n *  \\brief sets DES key\n *  \\param tfm linux crypto algo transform\n *  \\param key input key\n *  \\param keylen key length\n*/\nstatic int lq_des_setkey(struct crypto_ablkcipher *tfm, const u8 *key,\n                         unsigned int keylen)\n{\n        struct des_ctx *dctx = crypto_ablkcipher_ctx(tfm);\n\n        //printk(\"setkey in %s\\n\", __FILE__);\n\n        dctx->controlr_M = 0;   // des\n        dctx->key_length = keylen;\n\n        memcpy ((u8 *) (dctx->expkey), key, keylen);\n\n        return 0;\n}\n\n/*! \\fn int lq_des3_ede_setkey(struct crypto_ablkcipher *tfm, const u8 *key, unsigned int keylen)\n *  \\ingroup IFX_DES_FUNCTIONS\n *  \\brief sets DES key\n *  \\param tfm linux crypto algo transform\n *  \\param key input key\n *  \\param keylen key length\n*/\n\nstatic int lq_des3_ede_setkey(struct crypto_ablkcipher *tfm, const u8 *in_key,\n                      unsigned int keylen)\n{\n    struct des_ctx *dctx = crypto_ablkcipher_ctx(tfm);\n\n    //printk(\"setkey in %s\\n\", __FILE__);\n\n    dctx->controlr_M = keylen/8 + 1;   // des\n    dctx->key_length = keylen;\n\n    memcpy ((u8 *) (dctx->expkey), in_key, keylen);\n\n    return 0;\n}\n\n/*! \\fn void ifx_deu_des_core(void *ctx_arg, u8 *out_arg, const u8 *in_arg, u8 *iv_arg, u32 nbytes, int encdec, int mode)\n *  \\ingroup IFX_DES_FUNCTIONS\n *  \\brief main interface to DES hardware\n *  \\param ctx_arg crypto algo context\n *  \\param out_arg output bytestream\n *  \\param in_arg input bytestream\n *  \\param iv_arg initialization vector\n *  \\param nbytes length of bytestream\n *  \\param encdec 1 for encrypt; 0 for decrypt\n *  \\param mode operation mode such as ebc, cbc\n*/\n\nstatic int lq_deu_des_core (void *ctx_arg, u8 *out_arg, const u8 *in_arg,\n             u8 *iv_arg, u32 nbytes, int encdec, int mode)\n{\n        volatile struct des_t *des = (struct des_t *) DES_3DES_START;\n        struct des_ctx *dctx = ctx_arg;\n        u32 *key = dctx->expkey;\n        unsigned long flag;\n\n        int i = 0;\n        int nblocks = 0;\n\n        CRTCL_SECT_START;\n\n        des->controlr.M = dctx->controlr_M;\n        if (dctx->controlr_M == 0)      // des\n        {\n                des->K1HR = DEU_ENDIAN_SWAP(*((u32 *) key + 0));\n                des->K1LR = DEU_ENDIAN_SWAP(*((u32 *) key + 1));\n\n        }\n        else {\n                /* Hardware Section */\n                switch (dctx->key_length) {\n                case 24:\n                        des->K3HR = DEU_ENDIAN_SWAP(*((u32 *) key + 4));\n                        des->K3LR = DEU_ENDIAN_SWAP(*((u32 *) key + 5));\n                        /* no break; */\n\n                case 16:\n                        des->K2HR = DEU_ENDIAN_SWAP(*((u32 *) key + 2));\n                        des->K2LR = DEU_ENDIAN_SWAP(*((u32 *) key + 3));\n\n                        /* no break; */\n                case 8:\n                        des->K1HR = DEU_ENDIAN_SWAP(*((u32 *) key + 0));\n                        des->K1LR = DEU_ENDIAN_SWAP(*((u32 *) key + 1));\n                        break;\n\n                default:\n                        CRTCL_SECT_END;\n                        return -EINVAL;\n                }\n        }\n\n        des->controlr.E_D = !encdec;    //encryption\n        des->controlr.O = mode; //0 ECB 1 CBC 2 OFB 3 CFB 4 CTR hexdump(prin,sizeof(*des));\n\n        if (mode > 0) {\n                des->IVHR = DEU_ENDIAN_SWAP(*(u32 *) iv_arg);\n                des->IVLR = DEU_ENDIAN_SWAP(*((u32 *) iv_arg + 1));\n        };\n\n    /* memory alignment issue */\n    dword_mem_aligned_in = (u32 *) DEU_DWORD_REORDERING(in_arg, des_buff_in, BUFFER_IN, nbytes);\n    \n    deu_priv->deu_rx_buf = (u32 *) out_arg;\n    deu_priv->deu_rx_len = nbytes;\n\n    dma->controlr.ALGO = 0;       //DES\n    des->controlr.DAU = 0;\n    dma->controlr.BS = 0;\n    dma->controlr.EN = 1;\n\n    while (des->controlr.BUS) {\n    };\n\n    wlen = dma_device_write (dma_device, (u8 *) dword_mem_aligned_in, nbytes, NULL);\n    if (wlen != nbytes) {\n        dma->controlr.EN = 0;\n        CRTCL_SECT_END;\n        printk (KERN_ERR \"[%s %s %d]: dma_device_write fail!\\n\", __FILE__, __func__, __LINE__);\n        return -EINVAL;\n    }\n\n\n    /* Prepare Rx buf length used in dma psuedo interrupt */\n    outcopy = (u32 *) DEU_DWORD_REORDERING(out_arg, des_buff_out, BUFFER_OUT, nbytes);\n    deu_priv->outcopy = outcopy;\n    deu_priv->event_src = DES_ASYNC_EVENT;\n     \n    if (mode > 0) {\n        *(u32 *) iv_arg = DEU_ENDIAN_SWAP(des->IVHR);\n        *((u32 *) iv_arg + 1) = DEU_ENDIAN_SWAP(des->IVLR);\n    };\n\n    CRTCL_SECT_END; \n\n    return -EINPROGRESS;\n\n}\n\nstatic int count_sgs(struct scatterlist *sl, unsigned int total_bytes)\n{\n        int i = 0;\n\n        do {\n                total_bytes -= sl[i].length;\n                i++;\n\n        } while (total_bytes > 0);\n\n        return i;\n}\n\n/* \\fn static inline struct des_container *des_container_cast (\n *                     struct scatterlist *dst)\n * \\ingroup IFX_DES_FUNCTIONS\n * \\brief Locate the structure des_container in memory.\n * \\param *areq Pointer to memory location where ablkcipher_request is located\n * \\return *des_cointainer The function pointer to des_container\n*/\n\nstatic inline struct des_container *des_container_cast(\n                        struct ablkcipher_request *areq)\n{\n    return container_of(areq, struct des_container, arequest);\n}\n\n/* \\fn static void lq_sg_complete(struct des_container *des_con)\n * \\ingroup IFX_DES_FUNCTIONS\n * \\brief Free the used up memory after encryt/decrypt.\n*/\n\nstatic void lq_sg_complete(struct des_container *des_con)\n{\n    unsigned long queue_flag;\n  \n    spin_lock_irqsave(&des_queue->lock, queue_flag);\n    kfree(des_con); \n    spin_unlock_irqrestore(&des_queue->lock, queue_flag);\n}\n\n/* \\fn void lq_sg_init(struct scatterlist *src,\n *                     struct scatterlist *dst)\n * \\ingroup IFX_DES_FUNCTIONS\n * \\brief Maps the scatterlists into a source/destination page.\n * \\param *src Pointer to the source scatterlist\n * \\param *dst Pointer to the destination scatterlist\n*/\n\nstatic void lq_sg_init(struct des_container *des_con, struct scatterlist *src,\n                       struct scatterlist *dst)\n{\n    struct page *dst_page, *src_page;\n\n    src_page = sg_virt(src);\n    des_con->src_buf = (char *) src_page;\n\n    dst_page = sg_virt(dst);\n    des_con->dst_buf = (char *) dst_page;\n}\n\n/* \\fn static int process_next_packet(struct des_container *des_con,  struct ablkcipher_request *areq,\n *                                     int state)\n * \\ingroup IFX_DES_FUNCTIONS\n * \\brief Process the next packet after dequeuing the packet from crypto queue\n * \\param *des_con  Pointer to DES container structure\n * \\param *areq     Pointer to ablkcipher_request container\n * \\param state     State of the packet (scattered packet or new packet to be processed)\n * \\return -EINVAL: DEU failure, -EINPROGRESS: DEU encrypt/decrypt in progress, 1: no scatterlist left\n*/\n\nstatic int process_next_packet(struct des_container *des_con,  struct ablkcipher_request *areq,\n                               int state) \n{\n    u8 *iv;\n    int mode, encdec, err = -EINVAL;\n    u32 remain, inc, chunk_size, nbytes;\n    struct scatterlist *src = NULL;\n    struct scatterlist *dst = NULL;\n    struct crypto_ablkcipher *cipher;\n    struct des_ctx *ctx;\n    unsigned long queue_flag;\n\n    spin_lock_irqsave(&des_queue->lock, queue_flag);\n\n    mode = des_con->mode;\n    encdec = des_con->encdec;\n    iv = des_con->iv;\n\n    if (state & PROCESS_SCATTER) {\n        src = scatterwalk_sg_next(areq->src);\n        dst = scatterwalk_sg_next(areq->dst);\n\n        if (!src || !dst) {\n            spin_unlock_irqrestore(&des_queue->lock, queue_flag);\n      \t    return 1;\n        }\n    }\n    else if (state & PROCESS_NEW_PACKET) {\n        src = areq->src;\n        dst = areq->dst;\n    }\n\n    remain = des_con->bytes_processed;\n    chunk_size = src->length;\n\n    //printk(\"debug ln: %d, func: %s, reqsize: %d, scattersize: %d\\n\", \n//\t\t__LINE__, __func__, areq->nbytes, chunk_size);\n\n    if (remain > DEU_MAX_PACKET_SIZE)\n        inc = DEU_MAX_PACKET_SIZE;\n    else if(remain > chunk_size)\n        inc = chunk_size;\n    else\n        inc = remain;\n \n    remain -= inc;\n    des_con->nbytes = inc;\n    \n    if (state & PROCESS_SCATTER) {\n        des_con->src_buf += des_con->nbytes;\n        des_con->dst_buf += des_con->nbytes;\n    } \n\n    lq_sg_init(des_con, src, dst);\n\n    nbytes = des_con->nbytes;\n\n    cipher = crypto_ablkcipher_reqtfm(areq);\n    ctx = crypto_ablkcipher_ctx(cipher);\n\n    if (des_queue->hw_status == DES_IDLE) {\n        des_queue->hw_status = DES_STARTED;\n    }\n    \n    des_con->bytes_processed -= des_con->nbytes;\n    err = ablkcipher_enqueue_request(&des_queue->list, &des_con->arequest);\n    if (err == -EBUSY) {\n        printk(\"Failed to enqueue request, ln: %d, err: %d\\n\",\n               __LINE__, err);\n        spin_unlock_irqrestore(&des_queue->lock, queue_flag);\n        return -EINVAL;\n    }\n\n    spin_unlock_irqrestore(&des_queue->lock, queue_flag);\n    err = lq_deu_des_core(ctx, des_con->dst_buf, des_con->src_buf, iv, nbytes, encdec, mode);\n \n    return err;\n}\n\n/* \\fn static void process_queue(unsigned long data)\n * \\ingroup IFX_DES_FUNCTIONS\n * \\brief Process next packet in queue\n * \\param data not used\n * \\return \n*/\n\nstatic void process_queue(unsigned long data)\n{\n      DEU_WAKEUP_EVENT(deu_dma_priv.deu_thread_wait, DES_ASYNC_EVENT,\n                deu_dma_priv.des_event_flags);\n\n}\n\n/* \\fn static int des_crypto_thread (void *data)\n * \\ingroup IFX_DES_FUNCTIONS\n * \\brief DES thread that handles crypto requests from upper layer & DMA\n * \\param *data Not used\n * \\return -EINVAL: DEU failure, -EBUSY: DEU HW busy, 0: exit thread\n*/\n\nstatic int des_crypto_thread(void *data)\n{\n    struct des_container *des_con = NULL;\n    struct ablkcipher_request *areq = NULL;\n    int err;\n    unsigned long queue_flag;\n\n    daemonize(\"lq_des_thread\");\n   \n    while (1)\n    {  \n       DEU_WAIT_EVENT(deu_dma_priv.deu_thread_wait, DES_ASYNC_EVENT, \n                       deu_dma_priv.des_event_flags);\n       spin_lock_irqsave(&des_queue->lock, queue_flag);\n\n       /* wait to prevent starting a crypto session before \n        * exiting the dma interrupt thread.\n        */\n       \n       if (des_queue->hw_status == DES_STARTED) {\n            areq = ablkcipher_dequeue_request(&des_queue->list);\n            des_con = des_container_cast(areq);\n            des_queue->hw_status = DES_BUSY;\n       }\n       else if (des_queue->hw_status == DES_IDLE) {\n            areq = ablkcipher_dequeue_request(&des_queue->list);\n            des_con = des_container_cast(areq);\n            des_queue->hw_status = DES_STARTED;\n       }\n       else if (des_queue->hw_status == DES_BUSY) {\n            areq = ablkcipher_dequeue_request(&des_queue->list);\n            des_con = des_container_cast(areq);\n       }\n       else if (des_queue->hw_status == DES_COMPLETED) {\n            areq->base.complete(&areq->base, 0);\n            lq_sg_complete(des_con);\n            des_queue->hw_status = DES_IDLE;\n            spin_unlock_irqrestore(&des_queue->lock, queue_flag);\n            return 0;\n       }\n       spin_unlock_irqrestore(&des_queue->lock, queue_flag);\n            \n       if ((des_con->bytes_processed == 0)) {\n            goto des_done;\n       }\n\n       if (!des_con) {\n           goto des_done;\n       }\n\n       if (des_con->flag & PROCESS_NEW_PACKET) { \n           des_con->flag = PROCESS_SCATTER;\n           err = process_next_packet(des_con, areq, PROCESS_NEW_PACKET);  \n       }\n       else\n           err = process_next_packet(des_con, areq, PROCESS_SCATTER);  \n       \n       if (err == -EINVAL) {\n           areq->base.complete(&areq->base, err);\n           lq_sg_complete(des_con);\n           printk(\"src/dst returned -EINVAL in func: %s\\n\", __func__);\n       }\n       else if (err > 0) { \n           printk(\"src/dst returned zero in func: %s\\n\", __func__);\n           goto des_done;\n       }\n\n       continue;\n   \ndes_done:\n       //printk(\"debug line - %d, func: %s, qlen: %d\\n\", __LINE__, __func__, des_queue->list.qlen);\n       areq->base.complete(&areq->base, 0);\n       lq_sg_complete(des_con);\n\n       spin_lock_irqsave(&des_queue->lock, queue_flag);\n       if (des_queue->list.qlen > 0) {\n           spin_unlock_irqrestore(&des_queue->lock, queue_flag);\n           tasklet_schedule(&des_queue->des_task);\n       } \n       else {\n           des_queue->hw_status = DES_IDLE;\n           spin_unlock_irqrestore(&des_queue->lock, queue_flag);\n       }\n    } // while(1)\n    \n    return 0;\n\n}\n\n/* \\fn static int lq_des_queue_mgr(struct des_ctx *ctx, struct ablkcipher_request *areq,\n                            u8 *iv, int encdec, int mode)\n * \\ingroup IFX_DES_FUNCTIONS\n * \\brief starts the process of queuing DEU requests\n * \\param *ctx crypto algo contax\n * \\param *areq Pointer to the balkcipher requests\n * \\param *iv Pointer to intput vector location\n * \\param dir Encrypt/Decrypt\n * \\mode The mode DES algo is running\n * \\return 0 if success\n*/\n\nstatic int lq_queue_mgr(struct des_ctx *ctx, struct ablkcipher_request *areq, \n                        u8 *iv, int encdec, int mode)\n{\n    int err = -EINVAL;\n    unsigned long queue_flag;\n    struct scatterlist *src = areq->src;\n    struct scatterlist *dst = areq->dst;\n    struct des_container *des_con = NULL;\n    u32 remain, inc, nbytes = areq->nbytes;\n    u32 chunk_bytes = src->length;\n   \n    des_con = (struct des_container *)kmalloc(sizeof(struct des_container), \n                                       GFP_KERNEL);\n\n    if (!(des_con)) {\n        printk(\"Cannot allocate memory for AES container, fn %s, ln %d\\n\",\n                __func__, __LINE__);\n        return -ENOMEM;\n    }\n  \n    /* DES encrypt/decrypt mode  */\n    if (mode == 5) {\n        nbytes = DES_BLOCK_SIZE;\n        chunk_bytes = DES_BLOCK_SIZE;\n        mode = 0;\n    }\n\n    des_con->bytes_processed = nbytes;\n    des_con->arequest = (*areq);\n    remain = nbytes;\n\n    //printk(\"debug - Line: %d, func: %s, reqsize: %d, scattersize: %d\\n\", \n\t//\t__LINE__, __func__, nbytes, chunk_bytes);\n\n    if (remain > DEU_MAX_PACKET_SIZE)  \n        inc = DEU_MAX_PACKET_SIZE;\n    else if(remain > chunk_bytes)\n        inc = chunk_bytes;\n    else \n        inc = remain;\n    \n    remain -= inc;\n    lq_sg_init(des_con, src, dst);\n     \n    if (remain <= 0 ) { \n        des_con->complete = 1;\n    }\n    else \n        des_con->complete = 0;\n        \n    des_con->nbytes = inc; \n    des_con->iv = iv;\n    des_con->mode = mode;\n    des_con->encdec = encdec;\n\n    spin_lock_irqsave(&des_queue->lock, queue_flag);\n\n    if (des_queue->hw_status == DES_STARTED || des_queue->hw_status == DES_BUSY ||\n        des_queue->list.qlen > 0) {\n\n        des_con->flag = PROCESS_NEW_PACKET;\n        err = ablkcipher_enqueue_request(&des_queue->list, &des_con->arequest);\n        if (err == -EBUSY) {\n            spin_unlock_irqrestore(&des_queue->lock, queue_flag); \n            printk(\"Fail to enqueue ablkcipher request ln: %d, err: %d\\n\",\n                   __LINE__, err);\n            return err;\n        }\n\n        spin_unlock_irqrestore(&des_queue->lock, queue_flag); \n        return -EINPROGRESS;\n              \n    }\n    else if (des_queue->hw_status == DES_IDLE) {\n        des_queue->hw_status = DES_STARTED;            \n    }\n   \n    des_con->flag = PROCESS_SCATTER;\n    des_con->bytes_processed -= des_con->nbytes;\n\n    err = ablkcipher_enqueue_request(&des_queue->list, &des_con->arequest);\n    if (err == -EBUSY) {\n        printk(\"Fail to enqueue ablkcipher request ln: %d, err: %d\\n\",\n\t       __LINE__, err);\n\n        spin_unlock_irqrestore(&des_queue->lock, queue_flag);\n        return err;\n     }\n                  \n     spin_unlock_irqrestore(&des_queue->lock, queue_flag); \n     return lq_deu_des_core(ctx, des_con->dst_buf, des_con->src_buf, iv, inc, encdec, mode);\n\n}\n\n/* \\fn static int lq_des_encrypt(struct ablkcipher_request *areq)\n * \\ingroup IFX_DES_FUNCTIONS\n * \\brief Decrypt function for DES algo\n * \\param *areq Pointer to ablkcipher request in memory\n * \\return 0 is success, -EINPROGRESS if encryting, EINVAL if failure\n*/\n\t\nstatic int lq_des_encrypt(struct ablkcipher_request *areq)\n{\n    struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);\n    struct des_ctx *ctx = crypto_ablkcipher_ctx(cipher);\n\n    return lq_queue_mgr(ctx, areq, NULL, CRYPTO_DIR_ENCRYPT, 5);\n\n}\n\n/* \\fn static int lq_des_decrypt(struct ablkcipher_request *areq)\n * \\ingroup IFX_DES_FUNCTIONS\n * \\brief Decrypt function for DES algo\n * \\param *areq Pointer to ablkcipher request in memory\n * \\return 0 is success, -EINPROGRESS if encryting, EINVAL if failure\n*/\n\nstatic int lq_des_decrypt(struct ablkcipher_request *areq)\n{\n    struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);\n    struct des_ctx *ctx = crypto_ablkcipher_ctx(cipher);\n\n    return lq_queue_mgr(ctx, areq, NULL, CRYPTO_DIR_DECRYPT, 5);\n}\n\n/* \\fn static int lq_ecb_des_encrypt(struct ablkcipher_request *areq)\n * \\ingroup IFX_DES_FUNCTIONS\n * \\brief Decrypt function for DES algo\n * \\param *areq Pointer to ablkcipher request in memory\n * \\return 0 is success, -EINPROGRESS if encryting, EINVAL if failure\n*/\n\nstatic int lq_ecb_des_encrypt(struct ablkcipher_request *areq)\n{\n    struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);\n    struct des_ctx *ctx = crypto_ablkcipher_ctx(cipher);\n\n    return lq_queue_mgr(ctx, areq, areq->info, CRYPTO_DIR_ENCRYPT, 0);\n}\n\n/* \\fn static int lq_ecb_des_decrypt(struct ablkcipher_request *areq)\n * \\ingroup IFX_DES_FUNCTIONS\n * \\brief Decrypt function for DES algo\n * \\param *areq Pointer to ablkcipher request in memory\n * \\return 0 is success, -EINPROGRESS if encryting, EINVAL if failure\n*/\nstatic int lq_ecb_des_decrypt(struct ablkcipher_request *areq)\n{\n    struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);\n    struct des_ctx *ctx = crypto_ablkcipher_ctx(cipher);\n\n    return lq_queue_mgr(ctx, areq, areq->info, CRYPTO_DIR_DECRYPT, 0);\n\n}\n\n/* \\fn static int lq_cbc_ecb_des_encrypt(struct ablkcipher_request *areq)\n * \\ingroup IFX_DES_FUNCTIONS\n * \\brief Decrypt function for DES algo\n * \\param *areq Pointer to ablkcipher request in memory\n * \\return 0 is success, -EINPROGRESS if encryting, EINVAL if failure\n*/\n\nstatic int lq_cbc_des_encrypt(struct ablkcipher_request *areq)\n{\n    struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);\n    struct des_ctx *ctx = crypto_ablkcipher_ctx(cipher);\n\n    return lq_queue_mgr(ctx, areq, areq->info, CRYPTO_DIR_ENCRYPT, 1);\n}\n/* \\fn static int lq_cbc_des_decrypt(struct ablkcipher_request *areq)\n * \\ingroup IFX_DES_FUNCTIONS\n * \\brief Decrypt function for DES algo\n * \\param *areq Pointer to ablkcipher request in memory\n * \\return 0 is success, -EINPROGRESS if encryting, EINVAL if failure\n*/\n\nstatic int lq_cbc_des_decrypt(struct ablkcipher_request *areq)\n{\n    struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);\n    struct des_ctx *ctx = crypto_ablkcipher_ctx(cipher);\n\n    return lq_queue_mgr(ctx, areq, areq->info, CRYPTO_DIR_DECRYPT, 1);\n}\n\nstruct lq_des_alg {\n    struct crypto_alg alg;\n};\n\n/* DES Supported algo array */\nstatic struct lq_des_alg des_drivers_alg [] = {\n    {\n        .alg = {\n            .cra_name        = \"des\",\n            .cra_driver_name = \"lqdeu-des\",\n            .cra_flags       = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_KERN_DRIVER_ONLY | CRYPTO_ALG_ASYNC, \n            .cra_blocksize   = DES_BLOCK_SIZE,\n            .cra_ctxsize     = sizeof(struct des_ctx),\n            .cra_type        = &crypto_ablkcipher_type,\n            .cra_priority    = 300,\n            .cra_module      = THIS_MODULE,\n            .cra_ablkcipher  = {\n                                .setkey = lq_des_setkey,\n                                .encrypt = lq_des_encrypt,\n                                .decrypt = lq_des_decrypt,\n                                .geniv = \"eseqiv\",\n                                .min_keysize = DES_KEY_SIZE,\n                                .max_keysize = DES_KEY_SIZE,\n                                .ivsize = DES_BLOCK_SIZE,\n            }\n        }\n\n    },{\n        .alg = {\n            .cra_name        = \"ecb(des)\",\n            .cra_driver_name = \"lqdeu-ecb(des)\",\n            .cra_flags       = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_KERN_DRIVER_ONLY | CRYPTO_ALG_ASYNC, \n            .cra_blocksize   = DES_BLOCK_SIZE,\n            .cra_ctxsize     = sizeof(struct des_ctx),\n            .cra_type        = &crypto_ablkcipher_type,\n            .cra_priority    = 400,\n            .cra_module      = THIS_MODULE,\n            .cra_ablkcipher  = {\n                                .setkey = lq_des_setkey,\n                                .encrypt = lq_ecb_des_encrypt,\n                                .decrypt = lq_ecb_des_decrypt,\n                                .geniv = \"eseqiv\",\n                                .min_keysize = DES_KEY_SIZE,\n                                .max_keysize = DES_KEY_SIZE,\n                                .ivsize = DES_BLOCK_SIZE,\n            }\n         }\n    },{\n        .alg = {\n            .cra_name        = \"cbc(des)\",\n            .cra_driver_name = \"lqdeu-cbc(des)\",\n            .cra_flags       = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_KERN_DRIVER_ONLY | CRYPTO_ALG_ASYNC, \n            .cra_blocksize   = DES_BLOCK_SIZE,\n            .cra_ctxsize     = sizeof(struct des_ctx),\n            .cra_type        = &crypto_ablkcipher_type,\n            .cra_priority    = 400,\n            .cra_module      = THIS_MODULE,\n            .cra_ablkcipher  = {\n                                .setkey = lq_des_setkey,\n                                .encrypt = lq_cbc_des_encrypt,\n                                .decrypt = lq_cbc_des_decrypt,\n                                .geniv = \"eseqiv\",\n                                .min_keysize = DES3_EDE_KEY_SIZE,\n                                .max_keysize = DES3_EDE_KEY_SIZE,\n                                .ivsize = DES3_EDE_BLOCK_SIZE,\n            }\n         }\n    },{\n        .alg = {\n            .cra_name        = \"des3_ede\",\n            .cra_driver_name = \"lqdeu-des3_ede\",\n            .cra_flags       = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_KERN_DRIVER_ONLY | CRYPTO_ALG_ASYNC, \n            .cra_blocksize   = DES_BLOCK_SIZE,\n            .cra_ctxsize     = sizeof(struct des_ctx),\n            .cra_type        = &crypto_ablkcipher_type,\n            .cra_priority    = 300,\n            .cra_module      = THIS_MODULE,\n            .cra_ablkcipher  = {\n                                .setkey = lq_des3_ede_setkey,\n                                .encrypt = lq_des_encrypt,\n                                .decrypt = lq_des_decrypt,\n                                .geniv = \"eseqiv\",\n                                .min_keysize = DES_KEY_SIZE,\n                                .max_keysize = DES_KEY_SIZE,\n                                .ivsize = DES_BLOCK_SIZE,\n            }\n         }\n    },{\n        .alg = {\n            .cra_name        = \"ecb(des3_ede)\",\n            .cra_driver_name = \"lqdeu-ecb(des3_ede)\",\n            .cra_flags       = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_KERN_DRIVER_ONLY | CRYPTO_ALG_ASYNC, \n            .cra_blocksize   = DES_BLOCK_SIZE,\n            .cra_ctxsize     = sizeof(struct des_ctx),\n            .cra_type        = &crypto_ablkcipher_type,\n            .cra_priority    = 400,\n            .cra_module      = THIS_MODULE,\n            .cra_ablkcipher  = {\n                                .setkey = lq_des3_ede_setkey,\n                                .encrypt = lq_ecb_des_encrypt,\n                                .decrypt = lq_ecb_des_decrypt,\n                                .geniv = \"eseqiv\",\n                                .min_keysize = DES3_EDE_KEY_SIZE,\n                                .max_keysize = DES3_EDE_KEY_SIZE,\n                                .ivsize = DES3_EDE_BLOCK_SIZE,\n            }\n         } \n    },{\n        .alg = {\n            .cra_name        = \"cbc(des3_ede)\",\n            .cra_driver_name = \"lqdeu-cbc(des3_ede)\",\n            .cra_flags       = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_KERN_DRIVER_ONLY | CRYPTO_ALG_ASYNC, \n            .cra_blocksize   = DES_BLOCK_SIZE,\n            .cra_ctxsize     = sizeof(struct des_ctx),\n            .cra_type        = &crypto_ablkcipher_type,\n            .cra_priority    = 400,\n            .cra_module      = THIS_MODULE,\n            .cra_ablkcipher  = {\n                                .setkey = lq_des3_ede_setkey,\n                                .encrypt = lq_cbc_des_encrypt,\n                                .decrypt = lq_cbc_des_decrypt,\n                                .geniv = \"eseqiv\",\n                                .min_keysize = DES3_EDE_KEY_SIZE,\n                                .max_keysize = DES3_EDE_KEY_SIZE,\n                                .ivsize = DES3_EDE_BLOCK_SIZE,\n            }\n         }\n    } \n};\n\n/*! \\fn int __init lqdeu_async_des_init (void)\n *  \\ingroup IFX_DES_FUNCTIONS\n *  \\brief initialize des driver\n*/\nint __init lqdeu_async_des_init (void)\n{\n    int i, j, ret = -EINVAL;\n\n     for (i = 0; i < ARRAY_SIZE(des_drivers_alg); i++) {\n         ret = crypto_register_alg(&des_drivers_alg[i].alg);\n\t //printk(\"driver: %s\\n\", des_drivers_alg[i].alg.cra_name);\n         if (ret)\n             goto des_err;\n     }\n            \n     des_chip_init();\n     CRTCL_SECT_INIT;\n\n\n    printk (KERN_NOTICE \"IFX DEU DES initialized%s%s.\\n\", disable_multiblock ? \"\" : \" (multiblock)\", disable_deudma ? \"\" : \" (DMA)\");\n    return ret;\n\ndes_err:\n     for (j = 0; j < i; j++) \n        crypto_unregister_alg(&des_drivers_alg[i].alg);\n\n     printk(KERN_ERR \"Lantiq %s driver initialization failed!\\n\", (char *)&des_drivers_alg[i].alg.cra_driver_name);\n     return ret;\n\ncbc_des3_ede_err:\n     for (i = 0; i < ARRAY_SIZE(des_drivers_alg); i++) {\n         if (!strcmp((char *)&des_drivers_alg[i].alg.cra_name, \"cbc(des3_ede)\"))\n             crypto_unregister_alg(&des_drivers_alg[i].alg);\n     }     \n\n     printk(KERN_ERR \"Lantiq %s driver initialization failed!\\n\", (char *)&des_drivers_alg[i].alg.cra_driver_name);\n     return ret;\n}\n\n/*! \\fn void __exit lqdeu_fini_async_des (void)\n *  \\ingroup IFX_DES_FUNCTIONS\n *  \\brief unregister des driver\n*/\nvoid __exit lqdeu_fini_async_des (void)\n{\n    int i;\n    \n    for (i = 0; i < ARRAY_SIZE(des_drivers_alg); i++)\n        crypto_unregister_alg(&des_drivers_alg[i].alg);\n\n    des_queue->hw_status = DES_COMPLETED;\n    DEU_WAKEUP_EVENT(deu_dma_priv.deu_thread_wait, DES_ASYNC_EVENT,\n                                 deu_dma_priv.des_event_flags); \n   \n    kfree(des_queue);\n}\n\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-deu/src/ifxmips_des.c",
    "content": "/******************************************************************************\n**\n** FILE NAME    : ifxmips_des.c\n** PROJECT      : IFX UEIP\n** MODULES      : DEU Module\n**\n** DATE         : September 8, 2009\n** AUTHOR       : Mohammad Firdaus\n** DESCRIPTION  : Data Encryption Unit Driver for DES Algorithm\n** COPYRIGHT    :       Copyright (c) 2009\n**                      Infineon Technologies AG\n**                      Am Campeon 1-12, 85579 Neubiberg, Germany\n**\n**    This program is free software; you can redistribute it and/or modify\n**    it under the terms of the GNU General Public License as published by\n**    the Free Software Foundation; either version 2 of the License, or\n**    (at your option) any later version.\n**\n** HISTORY\n** $Date        $Author             $Comment\n** 08 Sept 2009 Mohammad Firdaus    Initial UEIP release\n*******************************************************************************/\n\n/*!\n  \\defgroup IFX_DEU IFX_DEU_DRIVERS\n  \\ingroup API\n  \\brief ifx deu driver\n*/\n\n/*!\n  \\file\t\tifxmips_des.c\n  \\ingroup \tIFX_DEU\n  \\brief \tDES encryption DEU driver file\n*/\n\n/*!\n  \\defgroup IFX_DES_FUNCTIONS IFX_DES_FUNCTIONS\n  \\ingroup IFX_DEU\n  \\brief IFX DES Encryption functions\n*/\n\n/* Project Header Files */\n#include <linux/version.h>\n#include <linux/module.h>\n#include <linux/init.h>\n#include <linux/types.h>\n#include <linux/errno.h>\n#include <linux/crypto.h>\n#include <linux/interrupt.h>\n#include <linux/delay.h>\n#include <asm/byteorder.h>\n#include <crypto/algapi.h>\n#include <crypto/des.h>\n#include <crypto/internal/skcipher.h>\n#include \"ifxmips_deu.h\"\n\n#if defined(CONFIG_DANUBE) \n#include \"ifxmips_deu_danube.h\"\nextern int ifx_danube_pre_1_4;\n#elif defined(CONFIG_AR9)\n#include \"ifxmips_deu_ar9.h\"\n#elif defined(CONFIG_VR9) || defined(CONFIG_AR10)\n#include \"ifxmips_deu_vr9.h\"\n#else\n#error \"Unkown platform\"\n#endif\n\n/* DMA specific header and variables */\n\n#if 0\n     #define CRTCL_SECT_INIT        \n     #define CRTCL_SECT_START        \n     #define CRTCL_SECT_END         \n#else\nspinlock_t des_lock;\n#define CRTCL_SECT_INIT        spin_lock_init(&des_lock)\n#define CRTCL_SECT_START       spin_lock_irqsave(&des_lock, flag)\n#define CRTCL_SECT_END         spin_unlock_irqrestore(&des_lock, flag)\n#endif\n\n/* Preprocessor declerations */\n#ifdef CRYPTO_DEBUG\nextern char debug_level;\n#define DPRINTF(level, format, args...) if (level < debug_level) printk(KERN_INFO \"[%s %s %d]: \" format, __FILE__, __func__, __LINE__, ##args);\n#else\n#define DPRINTF(level, format, args...)\n#endif\n#define DES_3DES_START  IFX_DES_CON\n#define DES_KEY_SIZE            8\n#define DES_EXPKEY_WORDS        32\n#define DES_BLOCK_SIZE          8\n#define DES3_EDE_KEY_SIZE       (3 * DES_KEY_SIZE)\n#define DES3_EDE_EXPKEY_WORDS   (3 * DES_EXPKEY_WORDS)\n#define DES3_EDE_BLOCK_SIZE     DES_BLOCK_SIZE\n\n/* Function Declaration to prevent warning messages */\nvoid des_chip_init (void);\nu32 endian_swap(u32 input);\nu32 input_swap(u32 input);\nint aes_memory_allocate(int value);\nint des_memory_allocate(int value);\nvoid memory_release(u32 *buffer);\nu32* memory_alignment(const u8 *arg, u32 *buff_alloc, int in_out, int nbytes);\nvoid aes_dma_memory_copy(u32 *outcopy, u32 *out_dma, u8 *out_arg, int nbytes);\nvoid des_dma_memory_copy(u32 *outcopy, u32 *out_dma, u8 *out_arg, int nbytes);\n\nvoid ifx_deu_des (void *ctx_arg, u8 *out_arg, const u8 *in_arg,\n             u8 *iv_arg, u32 nbytes, int encdec, int mode);\n\nstruct ifx_deu_des_ctx {\n        int controlr_M;\n        int key_length;\n        u8 iv[DES_BLOCK_SIZE];\n        u32 expkey[DES3_EDE_EXPKEY_WORDS];\n        struct des_ctx des_context;\n        struct des3_ede_ctx des3_ede_context;\n};\n\nextern int disable_multiblock;\nextern int disable_deudma;\n\n/*! \\fn\tint des_setkey(struct crypto_tfm *tfm, const u8 *key, unsigned int keylen)\n *  \\ingroup IFX_DES_FUNCTIONS\n *  \\brief sets DES key   \n *  \\param tfm linux crypto algo transform  \n *  \\param key input key  \n *  \\param keylen key length  \n*/                                 \nint des_setkey(struct crypto_tfm *tfm, const u8 *key,\n                      unsigned int keylen)\n{\n        struct ifx_deu_des_ctx *dctx = crypto_tfm_ctx(tfm);\n        int err;\n\n        //printk(\"setkey in %s\\n\", __FILE__);\n\n        err = des_expand_key(&dctx->des_context, key, keylen);\n        if (err == -ENOKEY) {\n                if (crypto_tfm_get_flags(tfm) & CRYPTO_TFM_REQ_FORBID_WEAK_KEYS)\n                        err = -EINVAL;\n                else\n                        err = 0;\n        }\n\n        dctx->controlr_M = 0;   // des\n        dctx->key_length = keylen;\n\n        memcpy ((u8 *) (dctx->expkey), key, keylen);\n\n        if (err)\n                memset(dctx, 0, sizeof(*dctx));\n\n        return err;\n}\n\n/*! \\fn int des_setkey_skcipher (struct crypto_skcipher *tfm, const uint8_t *in_key, unsigned int key_len)\n *  \\ingroup IFX_AES_FUNCTIONS\n *  \\brief sets the AES keys for skcipher\n *  \\param tfm linux crypto skcipher\n *  \\param in_key input key\n *  \\param key_len key lengths of 16, 24 and 32 bytes supported\n *  \\return -EINVAL - bad key length, 0 - SUCCESS\n*/\nint des_setkey_skcipher (struct crypto_skcipher *tfm, const u8 *in_key, unsigned int key_len)\n{\n    return des_setkey(crypto_skcipher_tfm(tfm), in_key, key_len);\n}\n\n/*! \\fn void ifx_deu_des(void *ctx_arg, u8 *out_arg, const u8 *in_arg, u8 *iv_arg, u32 nbytes, int encdec, int mode)\n *  \\ingroup IFX_DES_FUNCTIONS\n *  \\brief main interface to DES hardware   \n *  \\param ctx_arg crypto algo context  \n *  \\param out_arg output bytestream  \n *  \\param in_arg input bytestream   \n *  \\param iv_arg initialization vector  \n *  \\param nbytes length of bytestream  \n *  \\param encdec 1 for encrypt; 0 for decrypt  \n *  \\param mode operation mode such as ebc, cbc \n*/                                 \n\nvoid ifx_deu_des (void *ctx_arg, u8 *out_arg, const u8 *in_arg,\n             u8 *iv_arg, u32 nbytes, int encdec, int mode)\n{\n        volatile struct des_t *des = (struct des_t *) DES_3DES_START;\n        struct ifx_deu_des_ctx *dctx = ctx_arg;\n        u32 *key = dctx->expkey;\n        unsigned long flag;\n\n        int i = 0;\n        int nblocks = 0;\n        \n        CRTCL_SECT_START;\n\n        des->controlr.M = dctx->controlr_M;\n        if (dctx->controlr_M == 0)      // des\n        {\n                des->K1HR = DEU_ENDIAN_SWAP(*((u32 *) key + 0));\n                des->K1LR = DEU_ENDIAN_SWAP(*((u32 *) key + 1));\n\n        }\n        else {\n                /* Hardware Section */\n                switch (dctx->key_length) {\n                case 24:\n                        des->K3HR = DEU_ENDIAN_SWAP(*((u32 *) key + 4));\n                        des->K3LR = DEU_ENDIAN_SWAP(*((u32 *) key + 5));\n                        /* no break; */\n\n                case 16:\n                        des->K2HR = DEU_ENDIAN_SWAP(*((u32 *) key + 2));\n                        des->K2LR = DEU_ENDIAN_SWAP(*((u32 *) key + 3));\n\n                        /* no break; */\n                case 8:\n                        des->K1HR = DEU_ENDIAN_SWAP(*((u32 *) key + 0));\n                        des->K1LR = DEU_ENDIAN_SWAP(*((u32 *) key + 1));\n                        break;\n\n                default:\n                        CRTCL_SECT_END;\n                        return;\n                }\n        }\n\n        des->controlr.E_D = !encdec;    //encryption\n        des->controlr.O = mode; //0 ECB 1 CBC 2 OFB 3 CFB 4 CTR hexdump(prin,sizeof(*des));\n\n        if (mode > 0) {\n                des->IVHR = DEU_ENDIAN_SWAP(*(u32 *) iv_arg);\n                des->IVLR = DEU_ENDIAN_SWAP(*((u32 *) iv_arg + 1));\n        };\n\n        nblocks = nbytes / 4;\n\n        for (i = 0; i < nblocks; i += 2) {\n                /* wait for busy bit to clear */\n\n                /*--- Workaround ----------------------------------------------------\n                do a dummy read to the busy flag because it is not raised early\n                enough in CFB/OFB 3DES modes */\n#ifdef CRYPTO_DEBUG\n                printk (\"ihr: %x\\n\", (*((u32 *) in_arg + i)));\n                printk (\"ilr: %x\\n\", (*((u32 *) in_arg + 1 + i)));\n#endif           \n                des->IHR = INPUT_ENDIAN_SWAP(*((u32 *) in_arg + i));\n                des->ILR = INPUT_ENDIAN_SWAP(*((u32 *) in_arg + 1 + i)); /* start crypto */\n                \n                while (des->controlr.BUS) {\n                        // this will not take long\n                }\n\n                *((u32 *) out_arg + 0 + i) = des->OHR;\n                *((u32 *) out_arg + 1 + i) = des->OLR;\n\n        }\n\n\n    \n    if (mode > 0) {\n        *(u32 *) iv_arg = DEU_ENDIAN_SWAP(des->IVHR);\n        *((u32 *) iv_arg + 1) = DEU_ENDIAN_SWAP(des->IVLR);\n    };\n\n    CRTCL_SECT_END;\n}\n\n//definitions from linux/include/crypto.h:\n//#define CRYPTO_TFM_MODE_ECB           0x00000001\n//#define CRYPTO_TFM_MODE_CBC           0x00000002\n//#define CRYPTO_TFM_MODE_CFB           0x00000004\n//#define CRYPTO_TFM_MODE_CTR           0x00000008\n//#define CRYPTO_TFM_MODE_OFB           0x00000010 // not even defined\n//but hardware definition: 0 ECB 1 CBC 2 OFB 3 CFB 4 CTR\n\n/*! \\fn void ifx_deu_des(void *ctx_arg, u8 *out_arg, const u8 *in_arg, u8 *iv_arg, u32 nbytes, int encdec, int mode)\n *  \\ingroup IFX_DES_FUNCTIONS\n *  \\brief main interface to DES hardware   \n *  \\param ctx_arg crypto algo context  \n *  \\param out_arg output bytestream  \n *  \\param in_arg input bytestream   \n *  \\param iv_arg initialization vector  \n *  \\param nbytes length of bytestream  \n *  \\param encdec 1 for encrypt; 0 for decrypt  \n *  \\param mode operation mode such as ebc, cbc \n*/   \n\n/*! \\fn  void ifx_deu_des_ecb (void *ctx, uint8_t *dst, const uint8_t *src, uint8_t *iv, size_t nbytes, int encdec, int inplace)\n *  \\ingroup IFX_DES_FUNCTIONS\n *  \\brief sets DES hardware to ECB mode   \n *  \\param ctx crypto algo context  \n *  \\param dst output bytestream  \n *  \\param src input bytestream  \n *  \\param iv initialization vector   \n *  \\param nbytes length of bytestream  \n *  \\param encdec 1 for encrypt; 0 for decrypt  \n *  \\param inplace not used  \n*/\nvoid ifx_deu_des_ecb (void *ctx, uint8_t *dst, const uint8_t *src,\n                uint8_t *iv, size_t nbytes, int encdec, int inplace)\n{\n     ifx_deu_des (ctx, dst, src, NULL, nbytes, encdec, 0);\n}\n\n/*! \\fn  void ifx_deu_des_cbc (void *ctx, uint8_t *dst, const uint8_t *src, uint8_t *iv, size_t nbytes, int encdec, int inplace)\n *  \\ingroup IFX_DES_FUNCTIONS\n *  \\brief sets DES hardware to CBC mode   \n *  \\param ctx crypto algo context  \n *  \\param dst output bytestream  \n *  \\param src input bytestream  \n *  \\param iv initialization vector   \n *  \\param nbytes length of bytestream  \n *  \\param encdec 1 for encrypt; 0 for decrypt  \n *  \\param inplace not used  \n*/                                 \nvoid ifx_deu_des_cbc (void *ctx, uint8_t *dst, const uint8_t *src,\n                uint8_t *iv, size_t nbytes, int encdec, int inplace)\n{\n     ifx_deu_des (ctx, dst, src, iv, nbytes, encdec, 1);\n}\n\n/*! \\fn  void ifx_deu_des_ofb (void *ctx, uint8_t *dst, const uint8_t *src, uint8_t *iv, size_t nbytes, int encdec, int inplace)\n *  \\ingroup IFX_DES_FUNCTIONS\n *  \\brief sets DES hardware to OFB mode   \n *  \\param ctx crypto algo context  \n *  \\param dst output bytestream  \n *  \\param src input bytestream  \n *  \\param iv initialization vector   \n *  \\param nbytes length of bytestream  \n *  \\param encdec 1 for encrypt; 0 for decrypt  \n *  \\param inplace not used  \n*/                                 \nvoid ifx_deu_des_ofb (void *ctx, uint8_t *dst, const uint8_t *src,\n                uint8_t *iv, size_t nbytes, int encdec, int inplace)\n{\n     ifx_deu_des (ctx, dst, src, iv, nbytes, encdec, 2);\n}\n\n/*! \\fn void ifx_deu_des_cfb (void *ctx, uint8_t *dst, const uint8_t *src, uint8_t *iv, size_t nbytes, int encdec, int inplace)\n    \\ingroup IFX_DES_FUNCTIONS\n    \\brief sets DES hardware to CFB mode   \n    \\param ctx crypto algo context  \n    \\param dst output bytestream  \n    \\param src input bytestream  \n    \\param iv initialization vector   \n    \\param nbytes length of bytestream  \n    \\param encdec 1 for encrypt; 0 for decrypt  \n    \\param inplace not used  \n*/                                 \nvoid ifx_deu_des_cfb (void *ctx, uint8_t *dst, const uint8_t *src,\n                uint8_t *iv, size_t nbytes, int encdec, int inplace)\n{\n     ifx_deu_des (ctx, dst, src, iv, nbytes, encdec, 3);\n}\n\n/*! \\fn void ifx_deu_des_ctr (void *ctx, uint8_t *dst, const uint8_t *src, uint8_t *iv, size_t nbytes, int encdec, int inplace)\n *  \\ingroup IFX_DES_FUNCTIONS\n *  \\brief sets DES hardware to CTR mode   \n *  \\param ctx crypto algo context  \n *  \\param dst output bytestream  \n *  \\param src input bytestream  \n *  \\param iv initialization vector   \n *  \\param nbytes length of bytestream  \n *  \\param encdec 1 for encrypt; 0 for decrypt  \n *  \\param inplace not used  \n*/                                 \nvoid ifx_deu_des_ctr (void *ctx, uint8_t *dst, const uint8_t *src,\n                uint8_t *iv, size_t nbytes, int encdec, int inplace)\n{\n     ifx_deu_des (ctx, dst, src, iv, nbytes, encdec, 4);\n}\n\n/*! \\fn void ifx_deu_des_encrypt (struct crypto_tfm *tfm, uint8_t *out, const uint8_t *in)\n *  \\ingroup IFX_DES_FUNCTIONS\n *  \\brief encrypt DES_BLOCK_SIZE of data   \n *  \\param tfm linux crypto algo transform  \n *  \\param out output bytestream  \n *  \\param in input bytestream  \n*/                                               \nvoid ifx_deu_des_encrypt (struct crypto_tfm *tfm, uint8_t * out, const uint8_t * in)\n{\n     struct ifx_deu_des_ctx *ctx = crypto_tfm_ctx(tfm);\n     ifx_deu_des (ctx, out, in, NULL, DES_BLOCK_SIZE,\n                    CRYPTO_DIR_ENCRYPT, 0);\n\n}\n\n/*! \\fn void ifx_deu_des_decrypt (struct crypto_tfm *tfm, uint8_t *out, const uint8_t *in)\n *  \\ingroup IFX_DES_FUNCTIONS\n *  \\brief encrypt DES_BLOCK_SIZE of data   \n *  \\param tfm linux crypto algo transform  \n *  \\param out output bytestream  \n *  \\param in input bytestream  \n*/                                               \nvoid ifx_deu_des_decrypt (struct crypto_tfm *tfm, uint8_t * out, const uint8_t * in)\n{\n     struct ifx_deu_des_ctx *ctx = crypto_tfm_ctx(tfm);\n     ifx_deu_des (ctx, out, in, NULL, DES_BLOCK_SIZE,\n                    CRYPTO_DIR_DECRYPT, 0);\n}\n\n/*\n *   \\brief RFC2451:\n *\n *   For DES-EDE3, there is no known need to reject weak or\n *   complementation keys.  Any weakness is obviated by the use of\n *   multiple keys.\n *\n *   However, if the first two or last two independent 64-bit keys are\n *   equal (k1 == k2 or k2 == k3), then the DES3 operation is simply the\n *   same as DES.  Implementers MUST reject keys that exhibit this\n *   property.\n *\n */\n\n/*! \\fn int des3_ede_setkey(struct crypto_tfm *tfm, const u8 *key, unsigned int keylen)\n *  \\ingroup IFX_DES_FUNCTIONS\n *  \\brief sets 3DES key   \n *  \\param tfm linux crypto algo transform  \n *  \\param key input key  \n *  \\param keylen key length  \n*/                                 \nint des3_ede_setkey(struct crypto_tfm *tfm, const u8 *key,\n                    unsigned int keylen)\n{\n        struct ifx_deu_des_ctx *dctx = crypto_tfm_ctx(tfm);\n        int err;\n\n        //printk(\"setkey in %s\\n\", __FILE__);\n\n        err = des3_ede_expand_key(&dctx->des3_ede_context, key, keylen);\n        if (err == -ENOKEY) {\n                if (crypto_tfm_get_flags(tfm) & CRYPTO_TFM_REQ_FORBID_WEAK_KEYS)\n                        err = -EINVAL;\n                else\n                        err = 0;\n        }\n\n        dctx->controlr_M = keylen / 8 + 1;      // 3DES EDE1 / EDE2 / EDE3 Mode\n        dctx->key_length = keylen;\n\n        memcpy ((u8 *) (dctx->expkey), key, keylen);\n\n        if (err)\n                memset(dctx, 0, sizeof(*dctx));\n\n        return err;\n}\n\n/*! \\fn int des3_ede_setkey_skcipher(struct crypto_skcipher *tfm, const u8 *key, unsigned int keylen)\n *  \\ingroup IFX_DES_FUNCTIONS\n *  \\brief sets 3DES key\n *  \\param tfm linux crypto skcipher transform\n *  \\param key input key\n *  \\param keylen key length\n*/\nint des3_ede_setkey_skcipher(struct crypto_skcipher *tfm, const u8 *key,\n                    unsigned int keylen)\n{\n        return des3_ede_setkey(crypto_skcipher_tfm(tfm), key, keylen);\n}\n\n/*\n * \\brief DES function mappings\n*/ \nstruct crypto_alg ifxdeu_des_alg = {\n        .cra_name               =       \"des\",\n        .cra_driver_name        =       \"ifxdeu-des\",\n        .cra_priority           =       300,\n        .cra_flags              =       CRYPTO_ALG_TYPE_CIPHER | CRYPTO_ALG_KERN_DRIVER_ONLY,\n        .cra_blocksize          =       DES_BLOCK_SIZE,\n        .cra_ctxsize            =       sizeof(struct ifx_deu_des_ctx),\n        .cra_module             =       THIS_MODULE,\n        .cra_alignmask          =       3,\n        .cra_list               =       LIST_HEAD_INIT(ifxdeu_des_alg.cra_list),\n        .cra_u                  =       { .cipher = {\n        .cia_min_keysize        =       DES_KEY_SIZE,\n        .cia_max_keysize        =       DES_KEY_SIZE,\n        .cia_setkey             =       des_setkey,\n        .cia_encrypt            =       ifx_deu_des_encrypt,\n        .cia_decrypt            =       ifx_deu_des_decrypt } }\n};\n\n/*\n * \\brief DES function mappings\n*/ \nstruct crypto_alg ifxdeu_des3_ede_alg = {\n        .cra_name               =       \"des3_ede\",\n        .cra_driver_name        =       \"ifxdeu-des3_ede\",\n        .cra_priority           =       300,\n        .cra_flags              =       CRYPTO_ALG_TYPE_CIPHER | CRYPTO_ALG_KERN_DRIVER_ONLY,\n        .cra_blocksize          =       DES3_EDE_BLOCK_SIZE,\n        .cra_ctxsize            =       sizeof(struct ifx_deu_des_ctx),\n        .cra_module             =       THIS_MODULE,\n        .cra_alignmask          =       3,\n        .cra_list               =       LIST_HEAD_INIT(ifxdeu_des3_ede_alg.cra_list),\n        .cra_u                  =       { .cipher = {\n        .cia_min_keysize        =       DES3_EDE_KEY_SIZE,\n        .cia_max_keysize        =       DES3_EDE_KEY_SIZE,\n        .cia_setkey             =       des3_ede_setkey,\n        .cia_encrypt            =       ifx_deu_des_encrypt,\n        .cia_decrypt            =       ifx_deu_des_decrypt } }\n};\n\n/*! \\fn int ecb_des_encrypt(struct skcipher_req *req)\n *  \\ingroup IFX_AES_FUNCTIONS\n *  \\brief ECB DES encrypt using linux crypto skcipher\n *  \\param req skcipher request\n *  \\return err\n*/\nint ecb_des_encrypt(struct skcipher_request *req)\n{\n        struct ifx_deu_des_ctx *ctx = crypto_tfm_ctx(req->base.tfm);\n        struct skcipher_walk walk;\n        int err;\n        unsigned int enc_bytes, nbytes;\n\n        err = skcipher_walk_virt(&walk, req, false);\n\n        while ((nbytes = enc_bytes = walk.nbytes)) {\n                enc_bytes -= (nbytes % DES_BLOCK_SIZE);\n                ifx_deu_des_ecb(ctx, walk.dst.virt.addr, walk.src.virt.addr, \n                               NULL, enc_bytes, CRYPTO_DIR_ENCRYPT, 0);\n                nbytes &= DES_BLOCK_SIZE - 1;\n                err = skcipher_walk_done(&walk, nbytes);\n        }\n\n        return err;\n}\n\n/*! \\fn int ecb_des_decrypt(struct skcipher_req *req)\n *  \\ingroup IFX_AES_FUNCTIONS\n *  \\brief ECB DES decrypt using linux crypto skcipher\n *  \\param req skcipher request\n *  \\return err\n*/\nint ecb_des_decrypt(struct skcipher_request *req)\n{\n        struct ifx_deu_des_ctx *ctx = crypto_tfm_ctx(req->base.tfm);\n        struct skcipher_walk walk;\n        int err;\n        unsigned int dec_bytes, nbytes;\n\n        DPRINTF(1, \"\\n\");\n        err = skcipher_walk_virt(&walk, req, false);\n\n        while ((nbytes = dec_bytes = walk.nbytes)) {\n                dec_bytes -= (nbytes % DES_BLOCK_SIZE);\n                ifx_deu_des_ecb(ctx, walk.dst.virt.addr, walk.src.virt.addr, \n                               NULL, dec_bytes, CRYPTO_DIR_DECRYPT, 0);\n                nbytes &= DES_BLOCK_SIZE - 1;\n                err = skcipher_walk_done(&walk, nbytes);\n        }\n\n        return err;\n}\n\n/*\n * \\brief DES function mappings\n*/\nstruct skcipher_alg ifxdeu_ecb_des_alg = {\n        .base.cra_name          =       \"ecb(des)\",\n        .base.cra_driver_name   =       \"ifxdeu-ecb(des)\",\n        .base.cra_priority      =       400,\n        .base.cra_flags         =       CRYPTO_ALG_TYPE_SKCIPHER | CRYPTO_ALG_KERN_DRIVER_ONLY,\n        .base.cra_blocksize     =       DES_BLOCK_SIZE,\n        .base.cra_ctxsize       =       sizeof(struct ifx_deu_des_ctx),\n        .base.cra_module        =       THIS_MODULE,\n        .base.cra_list          =       LIST_HEAD_INIT(ifxdeu_ecb_des_alg.base.cra_list),\n        .min_keysize            =       DES_KEY_SIZE,\n        .max_keysize            =       DES_KEY_SIZE,\n        .setkey                 =       des_setkey_skcipher,\n        .encrypt                =       ecb_des_encrypt,\n        .decrypt                =       ecb_des_decrypt,\n};\n\n/*\n * \\brief DES function mappings\n*/\nstruct skcipher_alg ifxdeu_ecb_des3_ede_alg = {\n        .base.cra_name          =       \"ecb(des3_ede)\",\n        .base.cra_driver_name   =       \"ifxdeu-ecb(des3_ede)\",\n        .base.cra_priority      =       400,\n        .base.cra_flags         =       CRYPTO_ALG_TYPE_SKCIPHER | CRYPTO_ALG_KERN_DRIVER_ONLY,\n        .base.cra_blocksize     =       DES3_EDE_BLOCK_SIZE,\n        .base.cra_ctxsize       =       sizeof(struct ifx_deu_des_ctx),\n        .base.cra_module        =       THIS_MODULE,\n        .base.cra_list          =       LIST_HEAD_INIT(ifxdeu_ecb_des3_ede_alg.base.cra_list),\n        .min_keysize            =       DES3_EDE_KEY_SIZE,\n        .max_keysize            =       DES3_EDE_KEY_SIZE,\n        .setkey                 =       des3_ede_setkey_skcipher,\n        .encrypt                =       ecb_des_encrypt,\n        .decrypt                =       ecb_des_decrypt,\n};\n\n/*! \\fn int cbc_des_encrypt(struct skcipher_req *req)\n *  \\ingroup IFX_AES_FUNCTIONS\n *  \\brief CBC DES encrypt using linux crypto skcipher\n *  \\param req skcipher request\n *  \\return err\n*/\nint cbc_des_encrypt(struct skcipher_request *req)\n{\n        struct ifx_deu_des_ctx *ctx = crypto_tfm_ctx(req->base.tfm);\n        struct skcipher_walk walk;\n        int err;\n        unsigned int enc_bytes, nbytes;\n\n        DPRINTF(1, \"\\n\");\n        err = skcipher_walk_virt(&walk, req, false);\n\n        while ((nbytes = enc_bytes = walk.nbytes)) {\n                u8 *iv = walk.iv;\n                enc_bytes -= (nbytes % DES_BLOCK_SIZE);\n                ifx_deu_des_cbc(ctx, walk.dst.virt.addr, walk.src.virt.addr, \n                               iv, enc_bytes, CRYPTO_DIR_ENCRYPT, 0);\n                nbytes &= DES_BLOCK_SIZE - 1;\n                err = skcipher_walk_done(&walk, nbytes);\n        }\n\n        return err;\n}\n\n/*! \\fn int cbc_des_encrypt(struct skcipher_req *req)\n *  \\ingroup IFX_AES_FUNCTIONS\n *  \\brief CBC DES decrypt using linux crypto skcipher\n *  \\param req skcipher request\n *  \\return err\n*/\nint cbc_des_decrypt(struct skcipher_request *req)\n{\n        struct ifx_deu_des_ctx *ctx = crypto_tfm_ctx(req->base.tfm);\n        struct skcipher_walk walk;\n        int err;\n        unsigned int dec_bytes, nbytes;\n\n        DPRINTF(1, \"\\n\");\n        err = skcipher_walk_virt(&walk, req, false);\n\n        while ((nbytes = dec_bytes = walk.nbytes)) {\n                u8 *iv = walk.iv;\n                dec_bytes -= (nbytes % DES_BLOCK_SIZE);\n                ifx_deu_des_cbc(ctx, walk.dst.virt.addr, walk.src.virt.addr, \n                               iv, dec_bytes, CRYPTO_DIR_DECRYPT, 0);\n                nbytes &= DES_BLOCK_SIZE - 1;\n                err = skcipher_walk_done(&walk, nbytes);\n        }\n\n        return err;\n}\n\n/*\n * \\brief DES function mappings\n*/\nstruct skcipher_alg ifxdeu_cbc_des_alg = {\n        .base.cra_name          =       \"cbc(des)\",\n        .base.cra_driver_name   =       \"ifxdeu-cbc(des)\",\n        .base.cra_priority      =       400,\n        .base.cra_flags         =       CRYPTO_ALG_TYPE_SKCIPHER | CRYPTO_ALG_KERN_DRIVER_ONLY,\n        .base.cra_blocksize     =       DES_BLOCK_SIZE,\n        .base.cra_ctxsize       =       sizeof(struct ifx_deu_des_ctx),\n        .base.cra_module        =       THIS_MODULE,\n        .base.cra_list          =       LIST_HEAD_INIT(ifxdeu_cbc_des_alg.base.cra_list),\n        .min_keysize            =       DES_KEY_SIZE,\n        .max_keysize            =       DES_KEY_SIZE,\n        .ivsize                 =       DES_BLOCK_SIZE,\n        .setkey                 =       des_setkey_skcipher,\n        .encrypt                =       cbc_des_encrypt,\n        .decrypt                =       cbc_des_decrypt,\n};\n\n/*\n * \\brief DES function mappings\n*/\nstruct skcipher_alg ifxdeu_cbc_des3_ede_alg = {\n        .base.cra_name          =       \"cbc(des3_ede)\",\n        .base.cra_driver_name   =       \"ifxdeu-cbc(des3_ede)\",\n        .base.cra_priority      =       400,\n        .base.cra_flags         =       CRYPTO_ALG_TYPE_SKCIPHER | CRYPTO_ALG_KERN_DRIVER_ONLY,\n        .base.cra_blocksize     =       DES3_EDE_BLOCK_SIZE,\n        .base.cra_ctxsize       =       sizeof(struct ifx_deu_des_ctx),\n        .base.cra_module        =       THIS_MODULE,\n        .base.cra_list          =       LIST_HEAD_INIT(ifxdeu_cbc_des3_ede_alg.base.cra_list),\n        .min_keysize            =       DES3_EDE_KEY_SIZE,\n        .max_keysize            =       DES3_EDE_KEY_SIZE,\n        .ivsize                 =       DES_BLOCK_SIZE,\n        .setkey                 =       des3_ede_setkey_skcipher,\n        .encrypt                =       cbc_des_encrypt,\n        .decrypt                =       cbc_des_decrypt,\n};\n\n/*! \\fn int ifxdeu_init_des (void)\n *  \\ingroup IFX_DES_FUNCTIONS\n *  \\brief initialize des driver      \n*/                                 \nint ifxdeu_init_des (void)\n{\n    int ret = -ENOSYS;\n\n        des_chip_init();\n\n        ret = crypto_register_alg(&ifxdeu_des_alg);\n        if (ret < 0)\n                goto des_err;\n\n        ret = crypto_register_skcipher(&ifxdeu_ecb_des_alg);\n        if (ret < 0)\n                goto ecb_des_err;\n\n        ret = crypto_register_skcipher(&ifxdeu_cbc_des_alg);\n        if (ret < 0)\n                goto cbc_des_err;\n\n        ret = crypto_register_alg(&ifxdeu_des3_ede_alg);\n        if (ret < 0)\n                goto des3_ede_err;\n\n        ret = crypto_register_skcipher(&ifxdeu_ecb_des3_ede_alg);\n        if (ret < 0)\n                goto ecb_des3_ede_err;\n\n        ret = crypto_register_skcipher(&ifxdeu_cbc_des3_ede_alg);\n        if (ret < 0)\n                goto cbc_des3_ede_err;\n\n        CRTCL_SECT_INIT;\n\n\n\n         printk (KERN_NOTICE \"IFX DEU DES initialized%s%s.\\n\", disable_multiblock ? \"\" : \" (multiblock)\", disable_deudma ? \"\" : \" (DMA)\");\n        return ret;\n\ndes_err:\n        crypto_unregister_alg(&ifxdeu_des_alg);\n        printk(KERN_ERR \"IFX des initialization failed!\\n\");\n        return ret;\necb_des_err:\n        crypto_unregister_skcipher(&ifxdeu_ecb_des_alg);\n        printk (KERN_ERR \"IFX ecb_des initialization failed!\\n\");\n        return ret;\ncbc_des_err:\n        crypto_unregister_skcipher(&ifxdeu_cbc_des_alg);\n        printk (KERN_ERR \"IFX cbc_des initialization failed!\\n\");\n        return ret;\ndes3_ede_err:\n        crypto_unregister_alg(&ifxdeu_des3_ede_alg);\n        printk(KERN_ERR \"IFX des3_ede initialization failed!\\n\");\n        return ret;\necb_des3_ede_err:\n        crypto_unregister_skcipher(&ifxdeu_ecb_des3_ede_alg);\n        printk (KERN_ERR \"IFX ecb_des3_ede initialization failed!\\n\");\n        return ret;\ncbc_des3_ede_err:\n        crypto_unregister_skcipher(&ifxdeu_cbc_des3_ede_alg);\n        printk (KERN_ERR \"IFX cbc_des3_ede initialization failed!\\n\");\n        return ret;\n\n}\n\n/*! \\fn void ifxdeu_fini_des (void)\n *  \\ingroup IFX_DES_FUNCTIONS\n *  \\brief unregister des driver    \n*/                                 \nvoid ifxdeu_fini_des (void)\n{\n        crypto_unregister_alg (&ifxdeu_des_alg);\n        crypto_unregister_skcipher (&ifxdeu_ecb_des_alg);\n        crypto_unregister_skcipher (&ifxdeu_cbc_des_alg);\n        crypto_unregister_alg (&ifxdeu_des3_ede_alg);\n        crypto_unregister_skcipher (&ifxdeu_ecb_des3_ede_alg);\n        crypto_unregister_skcipher (&ifxdeu_cbc_des3_ede_alg);\n\n}\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-deu/src/ifxmips_deu.c",
    "content": "/******************************************************************************\n**\n** FILE NAME    : ifxmips_deu.c\n** PROJECT      : IFX UEIP\n** MODULES      : DEU Module for Danube\n**\n** DATE         : September 8, 2009\n** AUTHOR       : Mohammad Firdaus\n** DESCRIPTION  : Data Encryption Unit Driver\n** COPYRIGHT    :       Copyright (c) 2009\n**                      Infineon Technologies AG\n**                      Am Campeon 1-12, 85579 Neubiberg, Germany\n**\n**    This program is free software; you can redistribute it and/or modify\n**    it under the terms of the GNU General Public License as published by\n**    the Free Software Foundation; either version 2 of the License, or\n**    (at your option) any later version.\n**\n** HISTORY\n** $Date        $Author             $Comment\n** 08,Sept 2009 Mohammad Firdaus    Initial UEIP release\n*******************************************************************************/\n\n/*!\n  \\defgroup IFX_DEU IFX_DEU_DRIVERS\n  \\ingroup API\n  \\brief ifx deu driver module\n*/\n\n/*!\n  \\file\tifxmips_deu.c\n  \\ingroup IFX_DEU\n  \\brief main deu driver file\n*/\n\n/*!\n \\defgroup IFX_DEU_FUNCTIONS IFX_DEU_FUNCTIONS\n \\ingroup IFX_DEU\n \\brief IFX DEU functions\n*/\n\n/* Project header */\n#include <linux/version.h>\n#if defined(CONFIG_MODVERSIONS)\n#define MODVERSIONS\n#include <linux/modversions.h>\n#endif\n#include <linux/module.h>\n#include <linux/init.h>\n#include <linux/types.h>\n#include <linux/errno.h>\n#include <linux/crypto.h>\n#include <linux/proc_fs.h>\n#include <linux/platform_device.h>\n#include <linux/fs.h>       /* Stuff about file systems that we need */\n#include <asm/byteorder.h>\n#include \"ifxmips_deu.h\"\n\n#include <lantiq_soc.h>\n\n#if defined(CONFIG_DANUBE)\n#include \"ifxmips_deu_danube.h\"\n#elif defined(CONFIG_AR9)\n#include \"ifxmips_deu_ar9.h\"\n#elif defined(CONFIG_VR9) || defined(CONFIG_AR10)\n#include \"ifxmips_deu_vr9.h\"\n#else \n#error \"Platform unknown!\"\n#endif /* CONFIG_xxxx */\n\nint disable_deudma = 1;\nspinlock_t ltq_deu_hash_lock;\nEXPORT_SYMBOL_GPL(ltq_deu_hash_lock);\n\nvoid chip_version(void);\n\n/*! \\fn static int __init deu_init (void)\n *  \\ingroup IFX_DEU_FUNCTIONS\n *  \\brief link all modules that have been selected in kernel config for ifx hw crypto support   \n *  \\return ret \n*/  \n                               \nstatic int ltq_deu_probe(struct platform_device *pdev)\n{\n    int ret = -ENOSYS;\n\n\n    START_DEU_POWER;\n    CRTCL_SECT_HASH_INIT;\n    \n#define IFX_DEU_DRV_VERSION         \"2.0.0\"\n         printk(KERN_INFO \"Infineon Technologies DEU driver version %s \\n\", IFX_DEU_DRV_VERSION);\n\n    FIND_DEU_CHIP_VERSION;\n\n#if defined(CONFIG_CRYPTO_DEV_DES)\n    if ((ret = ifxdeu_init_des ())) {\n        printk (KERN_ERR \"IFX DES initialization failed!\\n\");\n    }\n#endif\n#if defined(CONFIG_CRYPTO_DEV_AES)\n    if ((ret = ifxdeu_init_aes ())) {\n        printk (KERN_ERR \"IFX AES initialization failed!\\n\");\n    }\n\n#endif\n#if defined(CONFIG_CRYPTO_DEV_ARC4)\n    if ((ret = ifxdeu_init_arc4 ())) {\n        printk (KERN_ERR \"IFX ARC4 initialization failed!\\n\");\n    }\n\n#endif\n#if defined(CONFIG_CRYPTO_DEV_SHA1)\n    if ((ret = ifxdeu_init_sha1 ())) {\n        printk (KERN_ERR \"IFX SHA1 initialization failed!\\n\");\n    }\n#endif\n#if defined(CONFIG_CRYPTO_DEV_MD5)\n    if ((ret = ifxdeu_init_md5 ())) {\n        printk (KERN_ERR \"IFX MD5 initialization failed!\\n\");\n    }\n\n#endif\n#if defined(CONFIG_CRYPTO_DEV_SHA1_HMAC)\n    if ((ret = ifxdeu_init_sha1_hmac ())) {\n        printk (KERN_ERR \"IFX SHA1_HMAC initialization failed!\\n\");\n    }\n#endif\n#if defined(CONFIG_CRYPTO_DEV_MD5_HMAC)\n    if ((ret = ifxdeu_init_md5_hmac ())) {\n        printk (KERN_ERR \"IFX MD5_HMAC initialization failed!\\n\");\n    }\n#endif\n\n\n\n    return ret;\n\n}\n\n/*! \\fn static void __exit deu_fini (void)\n *  \\ingroup IFX_DEU_FUNCTIONS\n *  \\brief remove the loaded crypto algorithms   \n*/                                 \nstatic int ltq_deu_remove(struct platform_device *pdev)\n{\n//#ifdef CONFIG_CRYPTO_DEV_PWR_SAVE_MODE\n    #if defined(CONFIG_CRYPTO_DEV_DES)\n    ifxdeu_fini_des ();\n    #endif\n    #if defined(CONFIG_CRYPTO_DEV_AES)\n    ifxdeu_fini_aes ();\n    #endif\n    #if defined(CONFIG_CRYPTO_DEV_ARC4)\n    ifxdeu_fini_arc4 ();\n    #endif\n    #if defined(CONFIG_CRYPTO_DEV_SHA1)\n    ifxdeu_fini_sha1 ();\n    #endif\n    #if defined(CONFIG_CRYPTO_DEV_MD5)\n    ifxdeu_fini_md5 ();\n    #endif\n    #if defined(CONFIG_CRYPTO_DEV_SHA1_HMAC)\n    ifxdeu_fini_sha1_hmac ();\n    #endif\n    #if defined(CONFIG_CRYPTO_DEV_MD5_HMAC)\n    ifxdeu_fini_md5_hmac ();\n    #endif\n    printk(\"DEU has exited successfully\\n\");\n\n\treturn 0;\n}\n\n\nint disable_multiblock = 0;\n\nmodule_param(disable_multiblock,int,0);\n\n\nstatic const struct of_device_id ltq_deu_match[] = {\n#ifdef CONFIG_DANUBE\n\t{ .compatible = \"lantiq,deu-danube\"},\n#elif defined CONFIG_AR9\n\t{ .compatible = \"lantiq,deu-arx100\"},\n#elif defined CONFIG_VR9\n\t{ .compatible = \"lantiq,deu-xrx200\"},\n#endif\n\t{},\n};\nMODULE_DEVICE_TABLE(of, ltq_deu_match);\n\n\nstatic struct platform_driver ltq_deu_driver = {\n\t.probe = ltq_deu_probe,\n\t.remove = ltq_deu_remove,\n\t.driver = {\n\t\t.name = \"deu\",\n\t\t.owner = THIS_MODULE,\n\t\t.of_match_table = ltq_deu_match,\n\t},\n};\n\nmodule_platform_driver(ltq_deu_driver);\n\nMODULE_DESCRIPTION (\"Infineon DEU crypto engine support.\");\nMODULE_LICENSE (\"GPL\");\nMODULE_AUTHOR (\"Mohammad Firdaus\");\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-deu/src/ifxmips_deu.h",
    "content": "/******************************************************************************\n**\n** FILE NAME    : ifxmips_deu.h\n** DESCRIPTION  : Data Encryption Unit Driver\n** COPYRIGHT    :       Copyright (c) 2009\n**                      Infineon Technologies AG\n**                      Am Campeon 1-12, 85579 Neubiberg, Germany\n**\n**    This program is free software; you can redistribute it and/or modify\n**    it under the terms of the GNU General Public License as published by\n**    the Free Software Foundation; either version 2 of the License, or\n**    (at your option) any later version.\n**\n** HISTORY\n** $Date        $Author             $Comment\n** 08,Sept 2009 Mohammad Firdaus    Initial UEIP release\n*******************************************************************************/\n/*!\n  \\defgroup IFX_DEU IFX_DEU_DRIVERS\n  \\ingroup  API\n  \\brief ifx deu driver module\n*/\n\n/*!\n  \\file\tifxmips_deu.h\n  \\brief main deu driver header file\n*/\n\n/*!\n  \\defgroup IFX_DEU_DEFINITIONS IFX_DEU_DEFINITIONS\n  \\ingroup  IFX_DEU\n  \\brief ifx deu definitions\n*/\n\n\n#ifndef IFXMIPS_DEU_H\n#define IFXMIPS_DEU_H\n\n#include <crypto/algapi.h>\n#include <linux/interrupt.h>\n\n#define IFXDEU_ALIGNMENT 16\n\n#define IFX_DEU_BASE_ADDR                       (KSEG1 | 0x1E103100)\n#define IFX_DEU_CLK                             ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0000))\n#define IFX_DES_CON                             ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0010))\n#define IFX_AES_CON                             ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0050))\n#define IFX_HASH_CON                            ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00B0))\n#define IFX_ARC4_CON                            ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0100))\n\n#define PFX\t\"ifxdeu: \"\n#define CLC_START IFX_DEU_CLK\n#define IFXDEU_CRA_PRIORITY\t300\n#define IFXDEU_COMPOSITE_PRIORITY 400\n//#define KSEG1                         0xA0000000\n#define IFX_PMU_ENABLE 1\n#define IFX_PMU_DISABLE 0\n\n#define CRYPTO_DIR_ENCRYPT 1\n#define CRYPTO_DIR_DECRYPT 0\n\n#define AES_IDLE 0\n#define AES_BUSY 1\n#define AES_STARTED 2\n#define AES_COMPLETED 3\n#define DES_IDLE 0\n#define DES_BUSY 1\n#define DES_STARTED 2\n#define DES_COMPLETED 3\n\n#define PROCESS_SCATTER 1\n#define PROCESS_NEW_PACKET 2\n\n#define PMU_DEU BIT(20)\n#define START_DEU_POWER        \\\n    do {                       \\\n        volatile struct clc_controlr_t *clc = (struct clc_controlr_t *) CLC_START;  \\\n        ltq_pmu_enable(PMU_DEU); \\\n        clc->FSOE = 0;           \\\n        clc->SBWE = 0;           \\\n        clc->SPEN = 0;           \\\n        clc->SBWE = 0;           \\\n        clc->DISS = 0;           \\\n        clc->DISR = 0;           \\\n    } while(0)\n\n#define STOP_DEU_POWER\t\t\\\n    do {\t\t\t\\\n        volatile struct clc_controlr_t *clc = (struct clc_controlr_t *) CLC_START; \\\n\tltq_pmu_disable(PMU_DEU); \\\n        clc->FSOE = 1;\t\t\\\n        clc->SBWE = 1;           \\\n        clc->SPEN = 1;           \\\n        clc->SBWE = 1;           \\\n        clc->DISS = 1;           \\\n        clc->DISR = 1;           \\\n    } while (0)\n\n/* \n * Not used anymore in UEIP (use IFX_DES_CON, IFX_AES_CON, etc instead) \n * #define DEU_BASE   (KSEG1+0x1E103100)\n * #define DES_CON\t\t(DEU_BASE+0x10)\n * #define AES_CON\t\t(DEU_BASE+0x50)\n * #define HASH_CON\t(DEU_BASE+0xB0)\n * #define DMA_CON\t\t(DEU_BASE+0xEC)\n * #define INT_CON\t\t(DEU_BASE+0xF4)\n * #define ARC4_CON\t(DEU_BASE+0x100)\n */\n\n\nint ifxdeu_init_des (void);\nint ifxdeu_init_aes (void);\nint ifxdeu_init_arc4 (void);\nint ifxdeu_init_sha1 (void);\nint ifxdeu_init_md5 (void);\nint ifxdeu_init_sha1_hmac (void);\nint ifxdeu_init_md5_hmac (void);\nint __init lqdeu_async_aes_init(void);\nint __init lqdeu_async_des_init(void);\n\nvoid ifxdeu_fini_des (void);\nvoid ifxdeu_fini_aes (void);\nvoid ifxdeu_fini_arc4 (void);\nvoid ifxdeu_fini_sha1 (void);\nvoid ifxdeu_fini_md5 (void);\nvoid ifxdeu_fini_sha1_hmac (void);\nvoid ifxdeu_fini_md5_hmac (void);\nvoid __exit ifxdeu_fini_dma(void);\nvoid __exit lqdeu_fini_async_aes(void);\nvoid __exit lqdeu_fini_async_des(void);\nvoid __exit deu_fini (void);\nint deu_dma_init (void);\n\nextern spinlock_t ltq_deu_hash_lock;\n#define CRTCL_SECT_HASH_INIT        spin_lock_init(&ltq_deu_hash_lock)\n#define CRTCL_SECT_HASH_START       spin_lock_irqsave(&ltq_deu_hash_lock, flag)\n#define CRTCL_SECT_HASH_END         spin_unlock_irqrestore(&ltq_deu_hash_lock, flag)\n\n\n#define DEU_WAKELIST_INIT(queue) \\\n    init_waitqueue_head(&queue)\n\n#define DEU_WAIT_EVENT_TIMEOUT(queue, event, flags, timeout)     \\\n    do {                                                         \\\n        wait_event_interruptible_timeout((queue),                \\\n            test_bit((event), &(flags)), (timeout));            \\\n        clear_bit((event), &(flags));                            \\\n    }while (0)\n\n\n#define DEU_WAKEUP_EVENT(queue, event, flags)         \\\n    do {                                              \\\n        set_bit((event), &(flags));                   \\\n        wake_up_interruptible(&(queue));              \\\n    }while (0)\n    \n#define DEU_WAIT_EVENT(queue, event, flags)           \\\n    do {                                              \\\n        wait_event_interruptible(queue,               \\\n            test_bit((event), &(flags)));             \\\n        clear_bit((event), &(flags));                 \\\n    }while (0)\n\ntypedef struct deu_drv_priv {\n    wait_queue_head_t  deu_thread_wait;\n#define DEU_EVENT       1\n#define DES_ASYNC_EVENT 2\n#define AES_ASYNC_EVENT 3\n    volatile long      des_event_flags;\n    volatile long      aes_event_flags;\n    volatile long      deu_event_flags;\n    int                event_src;\n    u32                *deu_rx_buf;\n    u32                *outcopy;\n    u32                deu_rx_len;\n\n    struct aes_priv    *aes_dataptr;\n    struct des_priv    *des_dataptr;\n}deu_drv_priv_t;\n\n\n/**\n *\tstruct aes_priv_t - ASYNC AES\n *\t@lock: spinlock lock\n *\t@lock_flag: flag for spinlock activities\n *\t@list: crypto queue API list\n *\t@hw_status: DEU hw status flag \n *\t@aes_wait_flag: flag for sleep queue\n *\t@aes_wait_queue: queue attributes for aes\n *\t@bytes_processed: number of bytes to process by DEU\n *\t@aes_pid: pid number for AES thread\n *\t@aes_sync: atomic wait sync for AES\n *\n*/\n\ntypedef struct {\n    spinlock_t lock;\n    struct crypto_queue list;\n    unsigned int hw_status;\n    volatile long aes_wait_flag;\n    wait_queue_head_t aes_wait_queue;\n\n    pid_t aes_pid;\n\n    struct tasklet_struct aes_task;\n\n} aes_priv_t;\n\n/**\n *      struct des_priv_t - ASYNC DES\n *      @lock: spinlock lock\n *      @list: crypto queue API list\n *      @hw_status: DEU hw status flag\n *      @des_wait_flag: flag for sleep queue\n *      @des_wait_queue: queue attributes for des\n *      @des_pid: pid number for DES thread\n *      @des_sync: atomic wait sync for DES\n *\n*/\n\ntypedef struct {\n    spinlock_t lock;\n    struct crypto_queue list;\n    unsigned int hw_status;\n    volatile long des_wait_flag;\n    wait_queue_head_t des_wait_queue;\n\n    pid_t des_pid;\n\n    struct tasklet_struct des_task;\n\n} des_priv_t;\n    \n#endif\t/* IFXMIPS_DEU_H */\n\n\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-deu/src/ifxmips_deu_ar9.c",
    "content": "/******************************************************************************\n**\n** FILE NAME    : ifxmips_deu_ar9.c\n** PROJECT      : IFX UEIP\n** MODULES      : DEU Module for AR9\n**\n** DATE         : September 8, 2009\n** AUTHOR       : Mohammad Firdaus\n** DESCRIPTION  : Data Encryption Unit Driver\n** COPYRIGHT    :       Copyright (c) 2009\n**                      Infineon Technologies AG\n**                      Am Campeon 1-12, 85579 Neubiberg, Germany\n**\n**    This program is free software; you can redistribute it and/or modify\n**    it under the terms of the GNU General Public License as published by\n**    the Free Software Foundation; either version 2 of the License, or\n**    (at your option) any later version.\n**\n** HISTORY\n** $Date        $Author             $Comment\n** 08,Sept 2009 Mohammad Firdaus    Initial UEIP release\n*******************************************************************************/\n/*!\n  \\defgroup IFX_DEU IFX_DEU_DRIVERS\n  \\ingroup API\n  \\brief ifx deu driver module\n*/\n\n/*!\n  \\file\tifxmips_deu_ar9.c\n  \\brief ifx deu board specific driver file for ar9\n*/\n\n/*! \n \\defgroup BOARD_SPECIFIC_FUNCTIONS IFX_BOARD_SPECIFIC_FUNCTIONS \n \\ingroup IFX_DEU\n \\brief board specific functions\n*/\n\n/* Project header files */\n#include <linux/module.h>\n#include <linux/init.h>\n#include <linux/types.h>\n#include <linux/errno.h>\n#include <asm/io.h> //dma_cache_inv\n\n#include \"ifxmips_deu_dma.h\"\n#include \"ifxmips_deu_ar9.h\"\n\n/* Function decleration */\nvoid aes_chip_init (void);\nvoid des_chip_init (void);\nint deu_dma_init (void);\nu32 endian_swap(u32 input);\nu32* memory_alignment(const u8 *arg, u32 *buff_alloc, int in_out, int nbytes);\nvoid aes_dma_memory_copy(u32 *outcopy, u32 *out_dma, u8 *out_arg, int nbytes);\nvoid des_dma_memory_copy(u32 *outcopy, u32 *out_dma, u8 *out_arg, int nbytes);\nvoid deu_dma_priv_init(void);\nvoid __exit ifxdeu_fini_dma(void);\n\n#define DES_3DES_START  IFX_DES_CON\n#define AES_START       IFX_AES_CON\n#define CLC_START\tIFX_DEU_CLK\n\n/* Variables */\n\nu8 *g_dma_page_ptr = NULL;\nu8 *g_dma_block = NULL;\nu8 *g_dma_block2 = NULL;\n\ndeu_drv_priv_t deu_dma_priv;\n\n\n/*! \\fn u32 endian_swap(u32 input) \n *  \\ingroup BOARD_SPECIFIC_FUNCTIONS\n *  \\brief Swap data given to the function \n *  \\param input   Data input to be swapped\n *  \\return either the swapped data or the input data depending on whether it is in DMA mode or FPI mode\n*/\nu32 endian_swap(u32 input)\n{\n    return input;\n}\n\n/*! \\fn\tu32 input_swap(u32 input)\n *  \\ingroup BOARD_SPECIFIC_FUNCTIONS\n *  \\brief Not used  \n *  \\return input\n*/\n\nu32 input_swap(u32 input)\n{\n    return input;\n}\n\n/*! \\fn void aes_chip_init (void)\n *  \\ingroup BOARD_SPECIFIC_FUNCTIONS\n *  \\brief initialize AES hardware   \n*/\n\nvoid aes_chip_init (void)\n{\n   volatile struct aes_t *aes = (struct aes_t *) AES_START;\n\n   aes->controlr.SM = 1;\n   aes->controlr.ARS = 1;\n\n}\n\n/*! \\fn void des_chip_init (void)\n *  \\ingroup BOARD_SPECIFIC_FUNCTIONS\n *  \\brief initialize DES hardware\n*/         \n                        \nvoid des_chip_init (void)\n{\n    volatile struct des_t *des = (struct des_t *) DES_3DES_START;\n\n    // start crypto engine with write to ILR\n    des->controlr.SM = 1;\n    asm(\"sync\");\n    des->controlr.ARS = 1;\n\n}\n\n/*! \\fn void chip_version(void) \n *  \\ingroup BOARD_SPECIFIC_FUNCTIONS\n *  \\brief not used!\n*/     \n\nvoid chip_version(void) \n{\n    return;\n}\n\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-deu/src/ifxmips_deu_ar9.h",
    "content": "/******************************************************************************\n**\n** FILE NAME    : ifxmips_deu_ar9.h\n** PROJECT      : IFX UEIP\n** MODULES      : DEU Module for AR9\n**\n** DATE         : September 8, 2009\n** AUTHOR       : Mohammad Firdaus\n** DESCRIPTION  : Data Encryption Unit Driver\n** COPYRIGHT    :       Copyright (c) 2009\n**                      Infineon Technologies AG\n**                      Am Campeon 1-12, 85579 Neubiberg, Germany\n**\n**    This program is free software; you can redistribute it and/or modify\n**    it under the terms of the GNU General Public License as published by\n**    the Free Software Foundation; either version 2 of the License, or\n**    (at your option) any later version.\n**\n** HISTORY\n** $Date        $Author             $Comment\n** 08,Sept 2009 Mohammad Firdaus    Initial UEIP release\n*******************************************************************************/\n/*!\n  \\defgroup IFX_DEU IFX_DEU_DRIVERS\n  \\ingroup API\n  \\brief deu driver module\n*/\n\n/*!\n  \\defgroup IFX_DEU_DEFINITIONS IFX_DEU_DEFINITIONS\n  \\ingroup IFX_DEU\n  \\brief ifx deu definitions\n*/\n\n/*!\n  \\file\t\tifxmips_deu_ar9.h\n  \\brief \tdeu driver header file\n*/\n\n\n#ifndef IFXMIPS_DEU_AR9_H\n#define IFXMIPS_DEU_AR9_H\n\n/* Project Header Files */\n#include <linux/version.h>\n#include <linux/module.h>\n#include <linux/init.h>\n#include <linux/types.h>\n#include <linux/errno.h>\n#include <linux/crypto.h>\n#include <linux/interrupt.h>\n#include <linux/delay.h>\n#include <asm/byteorder.h>\n#include <crypto/algapi.h>\n#include <linux/module.h>\n#include <linux/mm.h>\n#include <linux/scatterlist.h>\n#include <linux/skbuff.h>\n#include <linux/netdevice.h>\n#include \"ifxmips_deu.h\"\n\n\n/* SHA CONSTANTS */\n#define HASH_CON_VALUE    0x0700002C\n\n#define INPUT_ENDIAN_SWAP(input)    input_swap(input)\n#define DEU_ENDIAN_SWAP(input)    endian_swap(input)\n#define DELAY_PERIOD    10 \n#define FIND_DEU_CHIP_VERSION    chip_version()\n#define CLC_START IFX_DEU_CLK \n\n#define AES_INIT 0\n#define DES_INIT 1\n#define ARC4_INIT 2\n#define SHA1_INIT 3\n#define MD5_INIT 4\n#define SHA1_HMAC_INIT 5\n#define MD5_HMAC_INIT 6\n\n#define AES_START IFX_AES_CON\n#define DES_3DES_START  IFX_DES_CON\n\t\t\t\t      \n#define WAIT_AES_DMA_READY()          \\\n    do { \t\t\t      \\\n        int i;\t\t\t      \\\n        volatile struct deu_dma_t *dma = (struct deu_dma_t *) IFX_DEU_DMA_CON; \\\n        volatile struct aes_t *aes = (volatile struct aes_t *) AES_START; \\\n        for (i = 0; i < 10; i++)      \\\n\t    udelay(DELAY_PERIOD);     \\\n        while (dma->controlr.BSY) {}; \\\n        while (aes->controlr.BUS) {}; \\\n    } while (0)\n\n#define WAIT_DES_DMA_READY()          \\\n    do { \t\t\t      \\\n        int i;\t\t\t      \\\n        volatile struct deu_dma_t *dma = (struct deu_dma_t *) IFX_DEU_DMA_CON; \\\n        volatile struct des_t *des = (struct des_t *) DES_3DES_START; \\\n        for (i = 0; i < 10; i++)      \\\n            udelay(DELAY_PERIOD);     \\\n        while (dma->controlr.BSY) {}; \\\n        while (des->controlr.BUS) {}; \\\n    } while (0)\n\n#define AES_DMA_MISC_CONFIG()        \\\n    do {                             \\\n        volatile struct aes_t *aes = (volatile struct aes_t *) AES_START; \\\n        aes->controlr.KRE = 1;        \\\n        aes->controlr.GO = 1;         \\\n    } while(0)\n\n#define SHA_HASH_INIT                  \\\n    do {                               \\\n        volatile struct deu_hash_t *hash = (struct deu_hash_t *) HASH_START; \\\n        hash->controlr.SM = 1;    \\\n        hash->controlr.ALGO = 0;  \\\n        hash->controlr.INIT = 1;  \\\n    } while(0)\n\n#define MD5_HASH_INIT                  \\\n    do {                               \\\n        volatile struct deu_hash_t *hash = (struct deu_hash_t *) HASH_START; \\\n        hash->controlr.SM = 1;    \\\n        hash->controlr.ALGO = 1;  \\\n        hash->controlr.INIT = 1;  \\\n    } while(0)\n\n/* DEU Common Structures for AR9*/\n \nstruct clc_controlr_t {\n\tu32 Res:26;\n\tu32 FSOE:1;\n\tu32 SBWE:1;\n\tu32 EDIS:1;\n\tu32 SPEN:1;\n\tu32 DISS:1;\n\tu32 DISR:1;\n\n};\n\nstruct des_t {\n\tstruct des_controlr {\t//10h\n\t\tu32 KRE:1;\n\t\tu32 reserved1:5;\n\t\tu32 GO:1;\n\t\tu32 STP:1;\n\t\tu32 Res2:6;\n                u32 NDC:1;\n                u32 ENDI:1;\n                u32 Res3:2;\n\t\tu32 F:3;\n\t\tu32 O:3;\n\t\tu32 BUS:1;\n\t\tu32 DAU:1;\n\t\tu32 ARS:1;\n\t\tu32 SM:1;\n\t\tu32 E_D:1;\n\t\tu32 M:3;\n\n\t} controlr;\n\tu32 IHR;\t\t//14h\n\tu32 ILR;\t\t//18h\n\tu32 K1HR;\t\t//1c\n\tu32 K1LR;\t\t//\n\tu32 K2HR;\n\tu32 K2LR;\n\tu32 K3HR;\n\tu32 K3LR;\t\t//30h\n\tu32 IVHR;\t\t//34h\n\tu32 IVLR;\t\t//38\n\tu32 OHR;\t\t//3c\n\tu32 OLR;\t\t//40\n};\n\nstruct aes_t {\n\tstruct aes_controlr {\n\n\t\tu32 KRE:1;\n\t\tu32 reserved1:4;\n\t\tu32 PNK:1;\n\t\tu32 GO:1;\n\t\tu32 STP:1;\n\t\tu32 reserved2:6;\n\t\tu32 NDC:1;\n\t\tu32 ENDI:1;\n                u32 reserved3:2;\n\t\tu32 F:3;\t//fbs\n\t\tu32 O:3;\t//om\n\t\tu32 BUS:1;\t//bsy\n\t\tu32 DAU:1;\n\t\tu32 ARS:1;\n\t\tu32 SM:1;\n\t\tu32 E_D:1;\n\t\tu32 KV:1;\n\t\tu32 K:2;\t//KL\n\n\t} controlr;\n\tu32 ID3R;\t\t//80h\n\tu32 ID2R;\t\t//84h\n\tu32 ID1R;\t\t//88h\n\tu32 ID0R;\t\t//8Ch\n\tu32 K7R;\t\t//90h\n\tu32 K6R;\t\t//94h\n\tu32 K5R;\t\t//98h\n\tu32 K4R;\t\t//9Ch\n\tu32 K3R;\t\t//A0h\n\tu32 K2R;\t\t//A4h\n\tu32 K1R;\t\t//A8h\n\tu32 K0R;\t\t//ACh\n\tu32 IV3R;\t\t//B0h\n\tu32 IV2R;\t\t//B4h\n\tu32 IV1R;\t\t//B8h\n\tu32 IV0R;\t\t//BCh\n\tu32 OD3R;\t\t//D4h\n\tu32 OD2R;\t\t//D8h\n\tu32 OD1R;\t\t//DCh\n\tu32 OD0R;\t\t//E0h\n};\n\nstruct arc4_t {\n\tstruct arc4_controlr {\n\n\t\tu32 KRE:1;\n\t\tu32 KLEN:4;\n\t\tu32 KSAE:1;\n\t\tu32 GO:1;\n\t\tu32 STP:1;\n\t\tu32 reserved1:6;\n\t\tu32 NDC:1;\n\t\tu32 ENDI:1;\n\t\tu32 reserved2:8;\n\t\tu32 BUS:1;\t//bsy\n\t\tu32 reserved3:1;\n\t\tu32 ARS:1;\n\t\tu32 SM:1;\n\t\tu32 reserved4:4;\t\t\t\t\t\t\n\n\t} controlr;\n\tu32 K3R;\t\t//104h\n\tu32 K2R;\t\t//108h\n\tu32 K1R;\t\t//10Ch\n\tu32 K0R;\t\t//110h\n\n        u32 IDLEN;\t\t//114h\n\n\tu32 ID3R;\t\t//118h\n\tu32 ID2R;\t\t//11Ch\n\tu32 ID1R;\t\t//120h\n\tu32 ID0R;\t\t//124h\n\t\n\tu32 OD3R;\t\t//128h\n\tu32 OD2R;\t\t//12Ch\n\tu32 OD1R;\t\t//130h\n\tu32 OD0R;\t\t//134h\n};\n\nstruct deu_hash_t {\n\tstruct hash_controlr {\n\t\tu32 reserved1:5;\n\t\tu32 KHS:1;\t\t\n\t\tu32 GO:1;\n\t\tu32 INIT:1;\n\t\tu32 reserved2:6;\n\t\tu32 NDC:1;\n\t\tu32 ENDI:1;\n\t\tu32 reserved3:7;\n\t\tu32 DGRY:1;\t\t\n\t\tu32 BSY:1;\n\t\tu32 reserved4:1;\n\t\tu32 IRCL:1;\n\t\tu32 SM:1;\n\t\tu32 KYUE:1;\n                u32 HMEN:1;\n\t\tu32 SSEN:1;\n\t\tu32 ALGO:1;\n\n\t} controlr;\n\tu32 MR;\t\t\t//B4h\n\tu32 D1R;\t\t//B8h\n\tu32 D2R;\t\t//BCh\n\tu32 D3R;\t\t//C0h\n\tu32 D4R;\t\t//C4h\n\tu32 D5R;\t\t//C8h\n\n\tu32 dummy;\t\t//CCh\n\n\tu32 KIDX;\t\t//D0h\n\tu32 KEY;\t\t//D4h\n\tu32 DBN;\t\t//D8h\n};\n\n\nstruct deu_dma_t {\n\tstruct dma_controlr {\n\t\tu32 reserved1:22;\n\t\tu32 BS:2;\n\t\tu32 BSY:1;\n\t\tu32 reserved2:1;\n\t\tu32 ALGO:2;\n\t\tu32 RXCLS:2;\n\t\tu32 reserved3:1;\n\t\tu32 EN:1;\n\n\t} controlr;\n};\n\n#endif /* IFXMIPS_DEU_AR9_H */\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-deu/src/ifxmips_deu_danube.c",
    "content": "/******************************************************************************\n**\n** FILE NAME    : ifxmips_deu_danube.c\n** PROJECT      : IFX UEIP\n** MODULES      : DEU Module for Danube\n**\n** DATE         : September 8, 2009\n** AUTHOR       : Mohammad Firdaus\n** DESCRIPTION  : Data Encryption Unit Driver\n** COPYRIGHT    :       Copyright (c) 2009\n**                      Infineon Technologies AG\n**                      Am Campeon 1-12, 85579 Neubiberg, Germany\n**\n**    This program is free software; you can redistribute it and/or modify\n**    it under the terms of the GNU General Public License as published by\n**    the Free Software Foundation; either version 2 of the License, or\n**    (at your option) any later version.\n**\n** HISTORY\n** $Date        $Author             $Comment\n** 08,Sept 2009 Mohammad Firdaus    Initial UEIP release\n*******************************************************************************/\n/*!\n  \\defgroup IFX_DEU IFX_DEU_DRIVERS\n  \\ingroup API\n  \\brief deu driver module\n*/\n\n/*!\n  \\file\tifxmips_deu_danube.c\n  \\ingroup IFX_DEU\n  \\brief board specific deu driver file for danube\n*/\n\n/*!\n  \\defgroup BOARD_SPECIFIC_FUNCTIONS IFX_BOARD_SPECIFIC_FUNCTIONS\n  \\ingroup IFX_DEU\n  \\brief board specific deu functions\n*/\n\n/* Project header files */\n#include <linux/module.h>\n#include <linux/init.h>\n#include <linux/types.h>\n#include <linux/errno.h>\n#include <asm/io.h> //dma_cache_inv\n\n#include \"ifxmips_deu_dma.h\"\n#include \"ifxmips_deu_danube.h\"\n\n\n/* Function Declerations */\nint aes_memory_allocate(int value);\nint des_memory_allocate(int value);\nvoid memory_release(u32 *addr); \nint aes_chip_init (void);\nvoid des_chip_init (void);\nint deu_dma_init (void);\nu32 endian_swap(u32 input);\nu32* memory_alignment(const u8 *arg, u32 *buff_alloc, int in_out, int nbytes);\nvoid dma_memory_copy(u32 *outcopy, u32 *out_dma, u8 *out_arg, int nbytes);\nvoid chip_version(void); \nvoid deu_dma_priv_init(void);\nvoid __exit ifxdeu_fini_dma(void);\n\n#define DES_3DES_START  IFX_DES_CON\n#define AES_START       IFX_AES_CON\n#define CLC_START       IFX_DEU_CLK\n\n/* Variables definition */\nint ifx_danube_pre_1_4; \nu8 *g_dma_page_ptr = NULL;\nu8 *g_dma_block = NULL;\nu8 *g_dma_block2 = NULL;\n\ndeu_drv_priv_t deu_dma_priv;\n\n\n/*! \\fn u32 endian_swap(u32 input) \n *  \\ingroup BOARD_SPECIFIC_FUNCTIONS\n *  \\brief function is not used\n *  \\param input Data input to be swapped\n *  \\return input\n*/\n\nu32 endian_swap(u32 input)\n{\n    return input;\n}\n\n/*! \\fn\tu32 input_swap(u32 input)\n *  \\ingroup BOARD_SPECIFIC_FUNCTIONS\n *  \\brief Swap the input data if the current chip is Danube version\n *         1.4 and do nothing to the data if the current chip is \n *         Danube version 1.3 \n *  \\param input data that needs to be swapped\n *  \\return input or swapped input\n*/\n\nu32 input_swap(u32 input)\n{\n    if (!ifx_danube_pre_1_4) {\n        u8 *ptr = (u8 *)&input;\n        return ((ptr[3] << 24) | (ptr[2] << 16) | (ptr[1] << 8) | ptr[0]); \n    }\n    else \n        return input;\n}\n\n\n\n/*! \\fn void aes_chip_init (void)\n *  \\ingroup BOARD_SPECIFIC_FUNCTIONS\n * \\brief initialize AES hardware   \n*/\n\nint aes_chip_init (void)\n{\n    volatile struct aes_t *aes = (struct aes_t *) AES_START;\n\n    //start crypto engine with write to ILR\n    aes->controlr.SM = 1;\n    aes->controlr.ARS = 1;\n    return 0;\n}\n\n/*! \\fn void des_chip_init (void)\n *  \\ingroup BOARD_SPECIFIC_FUNCTIONS\n *  \\brief initialize DES hardware\n*/  \n                        \nvoid des_chip_init (void)\n{\n        volatile struct des_t *des = (struct des_t *) DES_3DES_START;\n\n        // start crypto engine with write to ILR\n        des->controlr.SM = 1;\n        des->controlr.ARS = 1;\n}\n\n/*! \\fn void chip_version (void)\n *  \\ingroup IFX_DES_FUNCTIONS\n *  \\brief To find the version of the chip by looking at the chip ID\n *  \\param ifx_danube_pre_1_4 (sets to 1 if Chip is Danube less than v1.4)\n*/  \n#define IFX_MPS               (KSEG1 | 0x1F107000)\n#define IFX_MPS_CHIPID                          ((volatile u32*)(IFX_MPS + 0x0344))\n\nvoid chip_version(void) \n{\n\n    /* DANUBE PRE 1.4 SOFTWARE FIX */\n    int chip_id = 0;\n    chip_id = *IFX_MPS_CHIPID;\n    chip_id >>= 28;\n\n    if (chip_id >= 4) {\n        ifx_danube_pre_1_4 = 0;\n        printk(\"Danube Chip ver. 1.4 detected. \\n\");\n    }\n    else {\n        ifx_danube_pre_1_4 = 1; \n        printk(\"Danube Chip ver. 1.3 or below detected. \\n\");\n    }\n\n    return;\n}\n\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-deu/src/ifxmips_deu_danube.h",
    "content": "/******************************************************************************\n**\n** FILE NAME    : ifxmips_deu_danube.h\n** PROJECT      : IFX UEIP\n** MODULES      : DEU Module for Danube\n**\n** DATE         : September 8, 2009\n** AUTHOR       : Mohammad Firdaus\n** DESCRIPTION  : Data Encryption Unit Driver\n** COPYRIGHT    :       Copyright (c) 2009\n**                      Infineon Technologies AG\n**                      Am Campeon 1-12, 85579 Neubiberg, Germany\n**\n**    This program is free software; you can redistribute it and/or modify\n**    it under the terms of the GNU General Public License as published by\n**    the Free Software Foundation; either version 2 of the License, or\n**    (at your option) any later version.\n**\n** HISTORY\n** $Date        $Author             $Comment\n** 08,Sept 2009 Mohammad Firdaus    Initial UEIP release\n*******************************************************************************/\n/*!\n  \\defgroup IFX_DEU IFX_DEU_DRIVERS\n  \\ingroup API\n  \\brief deu driver module\n*/\n\n/*!\n  \\file\tifxmips_deu_danube.h\n  \\brief board specific driver header file for danube\n*/\n\n/*!\n  \\defgroup BOARD_SPECIFIC_FUNCTIONS IFX_BOARD_SPECIFIC_FUNCTIONS\n  \\ingroup IFX_DEU\n  \\brief board specific deu header files\n*/\n\n#ifndef IFXMIPS_DEU_DANUBE_H\n#define IFXMIPS_DEU_DANUBE_H\n\n/* Project Header Files */\n#include <linux/version.h>\n#include <linux/module.h>\n#include <linux/init.h>\n#include <linux/types.h>\n#include <linux/errno.h>\n#include <linux/crypto.h>\n#include <linux/interrupt.h>\n#include <linux/delay.h>\n#include <asm/byteorder.h>\n#include <crypto/algapi.h>\n#include <linux/module.h>\n#include <linux/mm.h>\n#include <linux/scatterlist.h>\n#include <linux/skbuff.h>\n#include <linux/netdevice.h>\n#include \"ifxmips_deu.h\"\n\n\n\n#define INPUT_ENDIAN_SWAP(input)\t\t\t      input_swap(input)\n#define DEU_ENDIAN_SWAP(input)                                endian_swap(input)\n#define FIND_DEU_CHIP_VERSION\t\t\t\t      chip_version()\n#define AES_DMA_MISC_CONFIG()\n#define CLC_START IFX_DEU_CLK\n\n#define AES_START IFX_AES_CON\n#define DES_3DES_START  IFX_DES_CON\n\n#define AES_INIT 0\n#define DES_INIT 1\n#define SHA1_INIT 2 \n#define MD5_INIT 3\n\n#define WAIT_AES_DMA_READY()          \\\n    do { \t\t\t      \\\n        int i;\t\t\t      \\\n        volatile struct deu_dma_t *dma = (struct deu_dma_t *) IFX_DEU_DMA_CON; \\\n        volatile struct aes_t *aes = (volatile struct aes_t *) AES_START; \\\n        for (i = 0; i < 10; i++)      \\\n            udelay(DELAY_PERIOD);     \\\n        while (dma->controlr.BSY) {}; \\\n        while (aes->controlr.BUS) {}; \\\n    } while (0)\n\n#define WAIT_DES_DMA_READY()          \\\n    do { \t\t\t      \\\n        int i;\t\t\t      \\\n        volatile struct deu_dma_t *dma = (struct deu_dma_t *) IFX_DEU_DMA_CON; \\\n        volatile struct des_t *des = (struct des_t *) DES_3DES_START; \\\n        for (i = 0; i < 10; i++)      \\\n            udelay(DELAY_PERIOD);     \\\n        while (dma->controlr.BSY) {}; \\\n        while (des->controlr.BUS) {}; \\\n    } while (0)     \n\n#define SHA_HASH_INIT                  \\\n    do {                               \\\n        volatile struct deu_hash_t *hash = (struct deu_hash_t *) HASH_START; \\\n        hash->controlr.SM = 1;    \\\n        hash->controlr.ALGO = 0;  \\\n        hash->controlr.INIT = 1;  \\\n    } while(0)\n\n#define MD5_HASH_INIT                  \\\n    do {                               \\\n        volatile struct deu_hash_t *hash = (struct deu_hash_t *) HASH_START; \\\n        hash->controlr.SM = 1;    \\\n        hash->controlr.ALGO = 1;  \\\n        hash->controlr.INIT = 1;  \\\n    } while(0)\n\n/* DEU STRUCTURES */\n\nstruct clc_controlr_t {\n\tu32 Res:26;\n\tu32 FSOE:1;\n\tu32 SBWE:1;\n\tu32 EDIS:1;\n\tu32 SPEN:1;\n\tu32 DISS:1;\n\tu32 DISR:1;\n\n};\n\nstruct des_t {\n\tstruct des_controlr {\t//10h\n\t\tu32 KRE:1;\n\t\tu32 reserved1:5;\n\t\tu32 GO:1;\n\t\tu32 STP:1;\n\t\tu32 Res2:6;\n\t\tu32 NDC:1;\n\t\tu32 ENDI:1;\n\t\tu32 Res3:2;\n\t\tu32 F:3;\n\t\tu32 O:3;\n\t\tu32 BUS:1;\n\t\tu32 DAU:1;\n\t\tu32 ARS:1;\n\t\tu32 SM:1;\n\t\tu32 E_D:1;\n\t\tu32 M:3;\n\n\t} controlr;\n\tu32 IHR;\t\t//14h\n\tu32 ILR;\t\t//18h\n\tu32 K1HR;\t\t//1c\n\tu32 K1LR;\t\t//\n\tu32 K2HR;\n\tu32 K2LR;\n\tu32 K3HR;\n\tu32 K3LR;\t\t//30h\n\tu32 IVHR;\t\t//34h\n\tu32 IVLR;\t\t//38\n\tu32 OHR;\t\t//3c\n\tu32 OLR;\t\t//40\n};\n\nstruct aes_t {\n\tstruct aes_controlr {\n\n\t\tu32 KRE:1;\n\t\tu32 reserved1:4;\n\t\tu32 PNK:1;\n\t\tu32 GO:1;\n\t\tu32 STP:1;\n\t\t\n\t\tu32 reserved2:6;\n\t\tu32 NDC:1;\n\t\tu32 ENDI:1;\t\t\n\t\tu32 reserved3:2;\n\t\t\n\t\tu32 F:3;\t//fbs\n\t\tu32 O:3;\t//om\n\t\tu32 BUS:1;\t//bsy\n\t\tu32 DAU:1;\n\t\tu32 ARS:1;\n\t\tu32 SM:1;\n\t\tu32 E_D:1;\n\t\tu32 KV:1;\n\t\tu32 K:2;\t//KL\n\n\t} controlr;\n\tu32 ID3R;\t\t//80h\n\tu32 ID2R;\t\t//84h\n\tu32 ID1R;\t\t//88h\n\tu32 ID0R;\t\t//8Ch\n\tu32 K7R;\t\t//90h\n\tu32 K6R;\t\t//94h\n\tu32 K5R;\t\t//98h\n\tu32 K4R;\t\t//9Ch\n\tu32 K3R;\t\t//A0h\n\tu32 K2R;\t\t//A4h\n\tu32 K1R;\t\t//A8h\n\tu32 K0R;\t\t//ACh\n\tu32 IV3R;\t\t//B0h\n\tu32 IV2R;\t\t//B4h\n\tu32 IV1R;\t\t//B8h\n\tu32 IV0R;\t\t//BCh\n\tu32 OD3R;\t\t//D4h\n\tu32 OD2R;\t\t//D8h\n\tu32 OD1R;\t\t//DCh\n\tu32 OD0R;\t\t//E0h\n};\n\nstruct deu_hash_t {\n\tstruct hash_controlr {\n\t\tu32 reserved1:5;\n\t\tu32 KHS:1;\t\t\n\t\tu32 GO:1;\n\t\tu32 INIT:1;\n\t\tu32 reserved2:6;\n\t\tu32 NDC:1;\n\t\tu32 ENDI:1;\n\t\tu32 reserved3:7;\n\t\tu32 DGRY:1;\t\t\n\t\tu32 BSY:1;\n\t\tu32 reserved4:1;\n\t\tu32 IRCL:1;\n\t\tu32 SM:1;\n\t\tu32 KYUE:1;\n                u32 HMEN:1;\n\t\tu32 SSEN:1;\n\t\tu32 ALGO:1;\n\n\t} controlr;\n\tu32 MR;\t\t\t//B4h\n\tu32 D1R;\t\t//B8h\n\tu32 D2R;\t\t//BCh\n\tu32 D3R;\t\t//C0h\n\tu32 D4R;\t\t//C4h\n\tu32 D5R;\t\t//C8h\n\n\tu32 dummy;\t\t//CCh\n\n\tu32 KIDX;\t\t//D0h\n\tu32 KEY;\t\t//D4h\n\tu32 DBN;\t\t//D8h\n};\n\nstruct deu_dma_t {\n\tstruct dma_controlr {\n\t\tu32 reserved1:22;\n\t\tu32 BS:2;\n\t\tu32 BSY:1;\n\t\tu32 reserved2:1;\n\t\tu32 ALGO:2;\n\t\tu32 RXCLS:2;\n\t\tu32 reserved3:1;\n\t\tu32 EN:1;\n\n\t} controlr;\n};\n\n#endif  /* IFXMIPS_DEU_DANUBE_H */\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-deu/src/ifxmips_deu_dma.c",
    "content": "/******************************************************************************\n**\n** FILE NAME    : ifxmips_deu_dma.c\n** PROJECT      : IFX UEIP\n** MODULES      : DEU Module for Danube\n**\n** DATE         : September 8, 2009\n** AUTHOR       : Mohammad Firdaus\n** DESCRIPTION  : Data Encryption Unit Driver\n** COPYRIGHT    :       Copyright (c) 2009\n**                      Infineon Technologies AG\n**                      Am Campeon 1-12, 85579 Neubiberg, Germany\n**\n**    This program is free software; you can redistribute it and/or modify\n**    it under the terms of the GNU General Public License as published by\n**    the Free Software Foundation; either version 2 of the License, or\n**    (at your option) any later version.\n**\n** HISTORY\n** $Date        $Author             $Comment\n** 08 Sept 2009 Mohammad Firdaus    Initial UEIP release\n*******************************************************************************/\n/*!\n  \\defgroup IFX_DEU IFX_DEU_DRIVERS\n  \\ingroup  IFX_API\n  \\brief ifx deu driver module\n*/\n\n/*!\n  \\file\tifxmips_deu_dma.c\n  \\ingroup IFX_DEU\n  \\brief DMA deu driver file \n*/\n\n/*!\n \\defgroup IFX_DMA_FUNCTIONS IFX_DMA_FUNCTIONS\n \\ingroup IFX_DEU\n \\brief deu-dma driver functions\n*/\n\n/* Project header files */ \n\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-deu/src/ifxmips_deu_dma.h",
    "content": "/******************************************************************************\n**\n** FILE NAME    : ifxmips_deu_dma.h\n** DESCRIPTION  : Data Encryption Unit Driver\n** COPYRIGHT    :       Copyright (c) 2009\n**                      Infineon Technologies AG\n**                      Am Campeon 1-12, 85579 Neubiberg, Germany\n**\n**    This program is free software; you can redistribute it and/or modify\n**    it under the terms of the GNU General Public License as published by\n**    the Free Software Foundation; either version 2 of the License, or\n**    (at your option) any later version.\n**\n** HISTORY\n** $Date        $Author             $Comment\n** 08,Sept 2009 Mohammad Firdaus    Initial UEIP release\n*******************************************************************************/\n\n/*!\n  \\addtogroup    IFX_DEU IFX_DEU_DRIVERS\n  \\ingroup\t API\n  \\brief \t ifx deu driver module\n*/\n\n/*!\n  \\file\t\tifxmips_deu_dma.h\n  \\ingroup \tIFX_DEU\n  \\brief \tDMA deu driver header file\n*/\n\n#ifndef IFXMIPS_DEU_DMA_H\n#define IFXMIPS_DEU_DMA_H\n\n#include <linux/init.h>\n#include <linux/module.h>\n#include <linux/mm.h>\n#include <linux/crypto.h>\n#include <linux/scatterlist.h>\n#include <asm/byteorder.h>\n#include <linux/skbuff.h>\n#include <linux/netdevice.h>\n#include <linux/version.h>\n\n// must match the size of memory block allocated for g_dma_block and g_dma_block2\n#define DEU_MAX_PACKET_SIZE    (PAGE_SIZE >> 1)\n\ntypedef struct ifx_deu_device {\n\tstruct dma_device_info *dma_device;\n\tu8 *dst;\n\tu8 *src;\n\tint len;\n\tint dst_count;\n\tint src_count;\n\tint recv_count;\n\tint packet_size;\n\tint packet_num;\n\twait_queue_entry_t wait;\n} _ifx_deu_device;\n\nextern _ifx_deu_device ifx_deu[1];\n\nextern int deu_dma_intr_handler (struct dma_device_info *, int);\nextern u8 *deu_dma_buffer_alloc (int, int *, void **);\nextern int deu_dma_buffer_free (u8 *, void *);\nextern void deu_dma_inactivate_poll(struct dma_device_info* dma_dev);\nextern void deu_dma_activate_poll (struct dma_device_info* dma_dev);\nextern struct dma_device_info* deu_dma_reserve(struct dma_device_info** dma_device);\nextern int deu_dma_release(struct dma_device_info** dma_device);\n\n#endif\t/* IFMIPS_DEU_DMA_H */\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-deu/src/ifxmips_deu_vr9.c",
    "content": "/******************************************************************************\n**\n** FILE NAME    : ifxmips_deu_vr9.c\n** PROJECT      : IFX UEIP\n** MODULES      : DEU Module for VR9\n**\n** DATE         : September 8, 2009\n** AUTHOR       : Mohammad Firdaus\n** DESCRIPTION  : Data Encryption Unit Driver\n** COPYRIGHT    :       Copyright (c) 2009\n**                      Infineon Technologies AG\n**                      Am Campeon 1-12, 85579 Neubiberg, Germany\n**\n**    This program is free software; you can redistribute it and/or modify\n**    it under the terms of the GNU General Public License as published by\n**    the Free Software Foundation; either version 2 of the License, or\n**    (at your option) any later version.\n**\n** HISTORY\n** $Date        $Author             $Comment\n** 08,Sept 2009 Mohammad Firdaus    Initial UEIP release\n*******************************************************************************/\n\n/*!\n  \\defgroup  IFX_DEU IFX_DEU_DRIVERS\n  \\ingroup  API\n  \\brief deu driver module\n*/\n\n/*!\n  \\file\t\tifxmips_deu_vr9.c\n  \\ingroup \tIFX_DEU\n  \\brief \tboard specific deu driver file for vr9\n*/\n\n/*!\n  \\defgroup   BOARD_SPECIFIC_FUNCTIONS IFX_BOARD_SPECIFIC_FUNCTIONS\n  \\ingroup IFX_DEU\n  \\brief board specific deu driver functions\n*/\n\n/* Project header files */\n#include <linux/module.h>\n#include <linux/init.h>\n#include <linux/types.h>\n#include <linux/errno.h>\n#include <asm/io.h> //dma_cache_inv\n\n#include \"ifxmips_deu_dma.h\"\n#include \"ifxmips_deu_vr9.h\"\n\n/* Function decleration */\nvoid aes_chip_init (void);\nvoid des_chip_init (void);\nint deu_dma_init (void);\nvoid deu_dma_priv_init(void);\nu32 endian_swap(u32 input);\nu32* memory_alignment(const u8 *arg, u32 *buff_alloc, int in_out, int nbytes);\nvoid aes_dma_memory_copy(u32 *outcopy, u32 *out_dma, u8 *out_arg, int nbytes);\nvoid des_dma_memory_copy(u32 *outcopy, u32 *out_dma, u8 *out_arg, int nbytes);\nvoid __exit ifxdeu_fini_dma(void);\n\n#define DES_3DES_START  IFX_DES_CON\n#define AES_START       IFX_AES_CON\n\n/* Variables */\n\nu8 *g_dma_page_ptr = NULL;\nu8 *g_dma_block = NULL;\nu8 *g_dma_block2 = NULL;\n\ndeu_drv_priv_t deu_dma_priv;\n\n\n/*! \\fn u32 endian_swap(u32 input) \n *  \\ingroup BOARD_SPECIFIC_FUNCTIONS\n *  \\brief Swap data given to the function \n *  \\param input Data input to be swapped\n *  \\return either the swapped data or the input data depending on whether it is in DMA mode or FPI mode\n*/\n\n\nu32 endian_swap(u32 input)\n{\n    return input;\n}\n\n/*! \\fn u32 input_swap(u32 input)\n *  \\ingroup BOARD_SPECIFIC_FUNCTIONS\n *  \\brief Not used  \n *  \\return input\n*/\n\nu32 input_swap(u32 input)\n{\n    return input;\n}\n\n/*! \\fn void aes_chip_init (void)\n *  \\ingroup BOARD_SPECIFIC_FUNCTIONS\n *  \\brief initialize AES hardware   \n*/\n\nvoid aes_chip_init (void)\n{\n    volatile struct aes_t *aes = (struct aes_t *) AES_START;\n\n    // start crypto engine with write to ILR\n    aes->controlr.SM = 1;\n    aes->controlr.NDC = 1;\n    asm(\"sync\");\n    aes->controlr.ENDI = 1;\n    asm(\"sync\");\n    aes->controlr.ARS = 0;\n\t\n}\n\n/*! \\fn void des_chip_init (void)\n *  \\ingroup IFX_AES_FUNCTIONS\n *  \\brief initialize DES hardware\n*/         \n                        \nvoid des_chip_init (void)\n{\n    volatile struct des_t *des = (struct des_t *) DES_3DES_START;\n\n    // start crypto engine with write to ILR\n    des->controlr.SM = 1;\n    des->controlr.NDC = 1;\n    asm(\"sync\");\n    des->controlr.ENDI = 1;\n    asm(\"sync\");    \n    des->controlr.ARS = 0;\n\n}\n/*! \\fn void chip_version(void)\n *  \\ingroup IFX_DES_FUNCTIONS\n *  \\brief function not used in VR9\n*/\nvoid chip_version(void) \n{\n    return;\n}\n\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-deu/src/ifxmips_deu_vr9.h",
    "content": "/******************************************************************************\n**\n** FILE NAME    : ifxmips_deu_vr9.h\n** PROJECT      : IFX UEIP\n** MODULES      : DEU Module for VR9\n**\n** DATE         : September 8, 2009\n** AUTHOR       : Mohammad Firdaus\n** DESCRIPTION  : Data Encryption Unit Driver\n** COPYRIGHT    :       Copyright (c) 2009\n**                      Infineon Technologies AG\n**                      Am Campeon 1-12, 85579 Neubiberg, Germany\n**\n**    This program is free software; you can redistribute it and/or modify\n**    it under the terms of the GNU General Public License as published by\n**    the Free Software Foundation; either version 2 of the License, or\n**    (at your option) any later version.\n**\n** HISTORY\n** $Date        $Author             $Comment\n** 08,Sept 2009 Mohammad Firdaus    Initial UEIP release\n*******************************************************************************/\n/*!\n  \\defgroup IFX_DEU IFX_DEU_DRIVERS\n  \\ingroup API\n  \\brief deu driver module\n*/\n\n/*!\n  \\file\tifxmips_deu_vr9.h\n  \\ingroup IFX_DEU\n  \\brief board specific deu driver header file for vr9\n*/\n\n/*!\n  \\defgroup IFX_DEU_DEFINITIONS IFX_DEU_DEFINITIONS\n  \\brief deu driver header file\n*/\n\n\n#ifndef IFXMIPS_DEU_VR9_H\n#define IFXMIPS_DEU_VR9_H\n\n/* Project Header Files */\n#include <linux/version.h>\n#include <linux/module.h>\n#include <linux/init.h>\n#include <linux/types.h>\n#include <linux/errno.h>\n#include <linux/crypto.h>\n#include <linux/interrupt.h>\n#include <linux/delay.h>\n#include <asm/byteorder.h>\n#include <crypto/algapi.h>\n#include <linux/module.h>\n#include <linux/mm.h>\n#include <linux/scatterlist.h>\n#include <linux/skbuff.h>\n#include <linux/netdevice.h>\n#include \"ifxmips_deu.h\"\n\n\n#define AES_INIT 1\n#define DES_INIT 2\n#define ARC4_INIT 3\n#define SHA1_INIT 4\n#define MD5_INIT 5\n#define SHA1_HMAC_INIT 6\n#define MD5_HMAC_INIT 7\n\n#define AES_START IFX_AES_CON\n#define DES_3DES_START  IFX_DES_CON\n\n#if 0\n#define AES_IDLE 0\n#define AES_BUSY 1\n#define AES_STARTED 2\n#define AES_COMPLETED 3\n#define DES_IDLE 0\n#define DES_BUSY 1\n#define DES_STARTED 2\n#define DES_COMPLETED 3\n#endif\n\n/* SHA1 CONSTANT */\n#define HASH_CON_VALUE    0x0701002C\n\n#define INPUT_ENDIAN_SWAP(input)    input_swap(input)\n#define DEU_ENDIAN_SWAP(input)    endian_swap(input)\n#define FIND_DEU_CHIP_VERSION    chip_version() \n\n#if defined (CONFIG_AR10)\n#define DELAY_PERIOD    30\n#else\n#define DELAY_PERIOD    10\n#endif\n\t\t\t\t      \n#define WAIT_AES_DMA_READY()          \\\n    do { \t\t\t      \\\n        int i;\t\t\t      \\\n        volatile struct deu_dma_t *dma = (struct deu_dma_t *) IFX_DEU_DMA_CON; \\\n        volatile struct aes_t *aes = (volatile struct aes_t *) AES_START; \\\n        for (i = 0; i < 10; i++)      \\\n            udelay(DELAY_PERIOD);     \\\n        while (dma->controlr.BSY) {}; \\\n        while (aes->controlr.BUS) {}; \\\n    } while (0)\n\n#define WAIT_DES_DMA_READY()          \\\n    do { \t\t\t      \\\n        int i;\t\t\t      \\\n        volatile struct deu_dma_t *dma = (struct deu_dma_t *) IFX_DEU_DMA_CON; \\\n        volatile struct des_t *des = (struct des_t *) DES_3DES_START; \\\n        for (i = 0; i < 10; i++)      \\\n            udelay(DELAY_PERIOD);     \\\n        while (dma->controlr.BSY) {}; \\\n        while (des->controlr.BUS) {}; \\\n    } while (0)\n\n#define AES_DMA_MISC_CONFIG()        \\\n    do { \\\n        volatile struct aes_t *aes = (volatile struct aes_t *) AES_START; \\\n        aes->controlr.KRE = 1;        \\\n        aes->controlr.GO = 1;         \\\n    } while(0)\n\n#define SHA_HASH_INIT                \\\n    do {                               \\\n        volatile struct deu_hash_t *hash = (struct deu_hash_t *) HASH_START; \\\n        hash->controlr.ENDI = 1;  \\\n        hash->controlr.SM = 1;    \\\n        hash->controlr.ALGO = 0;  \\\n        hash->controlr.INIT = 1;  \\\n    } while(0)\n\n#define MD5_HASH_INIT                \\\n    do {                               \\\n        volatile struct deu_hash_t *hash = (struct deu_hash_t *) HASH_START; \\\n        hash->controlr.ENDI = 1;  \\\n        hash->controlr.SM = 1;    \\\n        hash->controlr.ALGO = 1;  \\\n        hash->controlr.INIT = 1;  \\\n    } while(0)\n\n/* DEU Common Structures for AR9*/\n \nstruct clc_controlr_t {\n\tu32 Res:26;\n\tu32 FSOE:1;\n\tu32 SBWE:1;\n\tu32 EDIS:1;\n\tu32 SPEN:1;\n\tu32 DISS:1;\n\tu32 DISR:1;\n\n};\n\nstruct des_t {\n\tstruct des_controlr {\t//10h\n\t\tu32 KRE:1;\n\t\tu32 reserved1:5;\n\t\tu32 GO:1;\n\t\tu32 STP:1;\n\t\tu32 Res2:6;\n                u32 NDC:1;\n                u32 ENDI:1;\n                u32 Res3:2;\n\t\tu32 F:3;\n\t\tu32 O:3;\n\t\tu32 BUS:1;\n\t\tu32 DAU:1;\n\t\tu32 ARS:1;\n\t\tu32 SM:1;\n\t\tu32 E_D:1;\n\t\tu32 M:3;\n\n\t} controlr;\n\tu32 IHR;\t\t//14h\n\tu32 ILR;\t\t//18h\n\tu32 K1HR;\t\t//1c\n\tu32 K1LR;\t\t//\n\tu32 K2HR;\n\tu32 K2LR;\n\tu32 K3HR;\n\tu32 K3LR;\t\t//30h\n\tu32 IVHR;\t\t//34h\n\tu32 IVLR;\t\t//38\n\tu32 OHR;\t\t//3c\n\tu32 OLR;\t\t//40\n};\n\nstruct aes_t {\n\tstruct aes_controlr {\n\n\t\tu32 KRE:1;\n\t\tu32 reserved1:4;\n\t\tu32 PNK:1;\n\t\tu32 GO:1;\n\t\tu32 STP:1;\n\t\tu32 reserved2:6;\n\t\tu32 NDC:1;\n\t\tu32 ENDI:1;\n                u32 reserved3:2;\n\t\tu32 F:3;\t//fbs\n\t\tu32 O:3;\t//om\n\t\tu32 BUS:1;\t//bsy\n\t\tu32 DAU:1;\n\t\tu32 ARS:1;\n\t\tu32 SM:1;\n\t\tu32 E_D:1;\n\t\tu32 KV:1;\n\t\tu32 K:2;\t//KL\n\n\t} controlr;\n\tu32 ID3R;\t\t//80h\n\tu32 ID2R;\t\t//84h\n\tu32 ID1R;\t\t//88h\n\tu32 ID0R;\t\t//8Ch\n\tu32 K7R;\t\t//90h\n\tu32 K6R;\t\t//94h\n\tu32 K5R;\t\t//98h\n\tu32 K4R;\t\t//9Ch\n\tu32 K3R;\t\t//A0h\n\tu32 K2R;\t\t//A4h\n\tu32 K1R;\t\t//A8h\n\tu32 K0R;\t\t//ACh\n\tu32 IV3R;\t\t//B0h\n\tu32 IV2R;\t\t//B4h\n\tu32 IV1R;\t\t//B8h\n\tu32 IV0R;\t\t//BCh\n\tu32 OD3R;\t\t//D4h\n\tu32 OD2R;\t\t//D8h\n\tu32 OD1R;\t\t//DCh\n\tu32 OD0R;\t\t//E0h\n};\n\nstruct arc4_t {\n\tstruct arc4_controlr {\n\n\t\tu32 KRE:1;\n\t\tu32 KLEN:4;\n\t\tu32 KSAE:1;\n\t\tu32 GO:1;\n\t\tu32 STP:1;\n\t\tu32 reserved1:6;\n\t\tu32 NDC:1;\n\t\tu32 ENDI:1;\n\t\tu32 reserved2:8;\n\t\tu32 BUS:1;\t//bsy\n\t\tu32 reserved3:1;\n\t\tu32 ARS:1;\n\t\tu32 SM:1;\n\t\tu32 reserved4:4;\t\t\t\t\t\t\n\n\t} controlr;\n\tu32 K3R;\t\t//104h\n\tu32 K2R;\t\t//108h\n\tu32 K1R;\t\t//10Ch\n\tu32 K0R;\t\t//110h\n\n        u32 IDLEN;\t\t//114h\n\n\tu32 ID3R;\t\t//118h\n\tu32 ID2R;\t\t//11Ch\n\tu32 ID1R;\t\t//120h\n\tu32 ID0R;\t\t//124h\n\t\n\tu32 OD3R;\t\t//128h\n\tu32 OD2R;\t\t//12Ch\n\tu32 OD1R;\t\t//130h\n\tu32 OD0R;\t\t//134h\n};\n\nstruct deu_hash_t {\n\tstruct hash_controlr {\n\t\tu32 reserved1:5;\n\t\tu32 KHS:1;\t\t\n\t\tu32 GO:1;\n\t\tu32 INIT:1;\n\t\tu32 reserved2:6;\n\t\tu32 NDC:1;\n\t\tu32 ENDI:1;\n\t\tu32 reserved3:7;\n\t\tu32 DGRY:1;\t\t\n\t\tu32 BSY:1;\n\t\tu32 reserved4:1;\n\t\tu32 IRCL:1;\n\t\tu32 SM:1;\n\t\tu32 KYUE:1;\n                u32 HMEN:1;\n\t\tu32 SSEN:1;\n\t\tu32 ALGO:1;\n\n\t} controlr;\n\tu32 MR;\t\t\t//B4h\n\tu32 D1R;\t\t//B8h\n\tu32 D2R;\t\t//BCh\n\tu32 D3R;\t\t//C0h\n\tu32 D4R;\t\t//C4h\n\tu32 D5R;\t\t//C8h\n\n\tu32 dummy;\t\t//CCh\n\n\tu32 KIDX;\t\t//D0h\n\tu32 KEY;\t\t//D4h\n\tu32 DBN;\t\t//D8h\n};\n\n\nstruct deu_dma_t {\n\tstruct dma_controlr {\n\t\tu32 reserved1:22;\n\t\tu32 BS:2;\n\t\tu32 BSY:1;\n\t\tu32 reserved2:1;\n\t\tu32 ALGO:2;\n\t\tu32 RXCLS:2;\n\t\tu32 reserved3:1;\n\t\tu32 EN:1;\n\n\t} controlr;\n};\n\n#endif /* IFXMIPS_DEU_VR9_H */\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-deu/src/ifxmips_md5.c",
    "content": "/******************************************************************************\n**\n** FILE NAME    : ifxmips_md5.c\n** PROJECT      : IFX UEIP\n** MODULES      : DEU Module for UEIP\n**\n** DATE         : September 8, 2009\n** AUTHOR       : Mohammad Firdaus\n** DESCRIPTION  : Data Encryption Unit Driver\n** COPYRIGHT    :       Copyright (c) 2009\n**                      Infineon Technologies AG\n**                      Am Campeon 1-12, 85579 Neubiberg, Germany\n**\n**    This program is free software; you can redistribute it and/or modify\n**    it under the terms of the GNU General Public License as published by\n**    the Free Software Foundation; either version 2 of the License, or\n**    (at your option) any later version.\n**\n** HISTORY\n** $Date        $Author             $Comment\n** 08,Sept 2009 Mohammad Firdaus    Initial UEIP release\n*******************************************************************************/\n/*!\n  \\defgroup    IFX_DEU IFX_DEU_DRIVERS\n  \\ingroup API\n  \\brief ifx deu driver module\n*/\n\n/*!\n  \\file\t\tifxmips_md5.c\n  \\ingroup \tIFX_DEU\n  \\brief \tMD5 encryption deu driver file \n*/\n\n/*!\n  \\defgroup IFX_MD5_FUNCTIONS IFX_MD5_FUNCTIONS\n  \\ingroup IFX_DEU\n  \\brief ifx deu MD5 functions\n*/\n\n/*Project header files */\n#include <linux/init.h>\n#include <linux/module.h>\n#include <linux/string.h>\n#include <linux/crypto.h>\n#include <linux/types.h>\n#include <crypto/internal/hash.h>\n#include <asm/byteorder.h>\n\n/* Project header */\n#if defined(CONFIG_DANUBE)\n#include \"ifxmips_deu_danube.h\"\n#elif defined(CONFIG_AR9)\n#include \"ifxmips_deu_ar9.h\"\n#elif defined(CONFIG_VR9) || defined(CONFIG_AR10)\n#include \"ifxmips_deu_vr9.h\"\n#else\n#error \"Plaform Unknwon!\"\n#endif\n\n#define MD5_DIGEST_SIZE     16\n#define MD5_HMAC_BLOCK_SIZE 64\n#define MD5_BLOCK_WORDS     16\n#define MD5_HASH_WORDS      4\n#define HASH_START   IFX_HASH_CON\n\n//#define CRYPTO_DEBUG\n#ifdef CRYPTO_DEBUG\nextern char debug_level;\n#define DPRINTF(level, format, args...) if (level < debug_level) printk(KERN_INFO \"[%s %s %d]: \" format, __FILE__, __func__, __LINE__, ##args);\n#else\n#define DPRINTF(level, format, args...)\n#endif\n\nstruct md5_ctx {\n    int started;\n    u32 hash[MD5_HASH_WORDS];\n    u32 block[MD5_BLOCK_WORDS];\n    u64 byte_count;\n};\n\nextern int disable_deudma;\n\n/*! \\fn static void md5_transform(u32 *hash, u32 const *in)\n *  \\ingroup IFX_MD5_FUNCTIONS\n *  \\brief main interface to md5 hardware   \n *  \\param hash current hash value  \n *  \\param in 64-byte block of input  \n*/                                 \nstatic void md5_transform(struct md5_ctx *mctx, u32 *hash, u32 const *in)\n{\n    int i;\n    volatile struct deu_hash_t *hashs = (struct deu_hash_t *) HASH_START;\n    unsigned long flag;\n\n    CRTCL_SECT_HASH_START;\n\n    MD5_HASH_INIT;\n\n    if (mctx->started) { \n        hashs->D1R = *((u32 *) hash + 0);\n        hashs->D2R = *((u32 *) hash + 1);\n        hashs->D3R = *((u32 *) hash + 2);\n        hashs->D4R = *((u32 *) hash + 3);\n    }\n\n    for (i = 0; i < 16; i++) {\n        hashs->MR = in[i];\n//      printk(\"in[%d]: %08x\\n\", i, in[i]);\n    };\n\n    //wait for processing\n    while (hashs->controlr.BSY) {\n        // this will not take long\n    }\n\n    *((u32 *) hash + 0) = hashs->D1R;\n    *((u32 *) hash + 1) = hashs->D2R;\n    *((u32 *) hash + 2) = hashs->D3R;\n    *((u32 *) hash + 3) = hashs->D4R;\n\n    CRTCL_SECT_HASH_END;\n\n    mctx->started = 1;\n}\n\n/*! \\fn static inline void md5_transform_helper(struct md5_ctx *ctx)\n *  \\ingroup IFX_MD5_FUNCTIONS\n *  \\brief interfacing function for md5_transform()   \n *  \\param ctx crypto context  \n*/                                 \nstatic inline void md5_transform_helper(struct md5_ctx *ctx)\n{\n    //le32_to_cpu_array(ctx->block, sizeof(ctx->block) / sizeof(u32));\n    md5_transform(ctx, ctx->hash, ctx->block);\n}\n\n/*! \\fn static void md5_init(struct crypto_tfm *tfm)\n *  \\ingroup IFX_MD5_FUNCTIONS\n *  \\brief initialize md5 hardware   \n *  \\param tfm linux crypto algo transform  \n*/                                 \nstatic int md5_init(struct shash_desc *desc)\n{\n    struct md5_ctx *mctx = shash_desc_ctx(desc);\n    volatile struct deu_hash_t *hash = (struct deu_hash_t *) HASH_START;\n\n    mctx->byte_count = 0;\n    mctx->started = 0;\n    return 0;\n}\n\n/*! \\fn static void md5_update(struct crypto_tfm *tfm, const u8 *data, unsigned int len)\n *  \\ingroup IFX_MD5_FUNCTIONS\n *  \\brief on-the-fly md5 computation   \n *  \\param tfm linux crypto algo transform  \n *  \\param data input data  \n *  \\param len size of input data  \n*/                                 \nstatic int md5_update(struct shash_desc *desc, const u8 *data, unsigned int len)\n{\n    struct md5_ctx *mctx = shash_desc_ctx(desc);\n    const u32 avail = sizeof(mctx->block) - (mctx->byte_count & 0x3f);\n\n    mctx->byte_count += len;\n\n    if (avail > len) {\n        memcpy((char *)mctx->block + (sizeof(mctx->block) - avail),\n               data, len);\n        return 0;\n    }\n\n    memcpy((char *)mctx->block + (sizeof(mctx->block) - avail),\n           data, avail);\n\n    md5_transform_helper(mctx);\n    data += avail;\n    len -= avail;\n\n    while (len >= sizeof(mctx->block)) {\n        memcpy(mctx->block, data, sizeof(mctx->block));\n        md5_transform_helper(mctx);\n        data += sizeof(mctx->block);\n        len -= sizeof(mctx->block);\n    }\n\n    memcpy(mctx->block, data, len);\n    return 0;\n}\n\n/*! \\fn static void md5_final(struct crypto_tfm *tfm, u8 *out)\n *  \\ingroup IFX_MD5_FUNCTIONS\n *  \\brief compute final md5 value   \n *  \\param tfm linux crypto algo transform  \n *  \\param out final md5 output value  \n*/                                 \nstatic int md5_final(struct shash_desc *desc, u8 *out)\n{\n    struct md5_ctx *mctx = shash_desc_ctx(desc);\n    const unsigned int offset = mctx->byte_count & 0x3f;\n    char *p = (char *)mctx->block + offset;\n    int padding = 56 - (offset + 1);\n    volatile struct deu_hash_t *hashs = (struct deu_hash_t *) HASH_START;\n    unsigned long flag;\n\n    *p++ = 0x80;\n    if (padding < 0) {\n        memset(p, 0x00, padding + sizeof (u64));\n        md5_transform_helper(mctx);\n        p = (char *)mctx->block;\n        padding = 56;\n    }\n\n    memset(p, 0, padding);\n    mctx->block[14] = le32_to_cpu(mctx->byte_count << 3);\n    mctx->block[15] = le32_to_cpu(mctx->byte_count >> 29);\n\n    md5_transform(mctx, mctx->hash, mctx->block);                                                 \n\n    memcpy(out, mctx->hash, MD5_DIGEST_SIZE);\n\n    // Wipe context\n    memset(mctx, 0, sizeof(*mctx));\n\n    return 0;\n}\n\n/*\n * \\brief MD5 function mappings\n*/\nstatic struct shash_alg ifxdeu_md5_alg = {\n    .digestsize         =       MD5_DIGEST_SIZE,\n    .init               =       md5_init,\n    .update             =       md5_update,\n    .final              =       md5_final,\n    .descsize           =       sizeof(struct md5_ctx),\n    .base               =       {\n                .cra_name       =       \"md5\",\n                .cra_driver_name=       \"ifxdeu-md5\",\n                .cra_priority   =       300,\n                .cra_flags      =       CRYPTO_ALG_TYPE_HASH | CRYPTO_ALG_KERN_DRIVER_ONLY,\n                .cra_blocksize  =       MD5_HMAC_BLOCK_SIZE,\n                .cra_module     =       THIS_MODULE,\n    }\n};\n\n/*! \\fn int ifxdeu_init_md5 (void)\n *  \\ingroup IFX_MD5_FUNCTIONS\n *  \\brief initialize md5 driver   \n*/                                 \nint ifxdeu_init_md5 (void)\n{\n    int ret = -ENOSYS;\n\n\n    if ((ret = crypto_register_shash(&ifxdeu_md5_alg)))\n        goto md5_err;\n\n    printk (KERN_NOTICE \"IFX DEU MD5 initialized%s.\\n\", disable_deudma ? \"\" : \" (DMA)\");\n    return ret;\n\nmd5_err:\n    printk(KERN_ERR \"IFX DEU MD5 initialization failed!\\n\");\n    return ret;\n}\n\n/*! \\fn void ifxdeu_fini_md5 (void)\n  * \\ingroup IFX_MD5_FUNCTIONS\n  * \\brief unregister md5 driver   \n*/                  \n               \nvoid ifxdeu_fini_md5 (void)\n{\n    crypto_unregister_shash(&ifxdeu_md5_alg);\n\n}\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-deu/src/ifxmips_md5_hmac.c",
    "content": "/******************************************************************************\n**\n** FILE NAME    : ifxmips_md5_hmac.c\n** PROJECT      : IFX UEIP\n** MODULES      : DEU Module for UEIP\n**\n** DATE         : September 8, 2009\n** AUTHOR       : Mohammad Firdaus\n** DESCRIPTION  : Data Encryption Unit Driver\n** COPYRIGHT    :       Copyright (c) 2009\n**                      Infineon Technologies AG\n**                      Am Campeon 1-12, 85579 Neubiberg, Germany\n**\n**    This program is free software; you can redistribute it and/or modify\n**    it under the terms of the GNU General Public License as published by\n**    the Free Software Foundation; either version 2 of the License, or\n**    (at your option) any later version.\n**\n** HISTORY\n** $Date        $Author             $Comment\n** 08,Sept 2009 Mohammad Firdaus    Initial UEIP release\n** 21,March 2011 Mohammad Firdaus   Changes for Kernel 2.6.32 and IPSec integration\n*******************************************************************************/\n/*!\n  \\defgroup IFX_DEU IFX_DEU_DRIVERS\n  \\ingroup API\n  \\brief  ifx deu driver module\n*/\n\n/*!\n  \\file\tifxmips_md5_hmac.c\n  \\ingroup IFX_DEU\n  \\brief MD5-HMAC encryption deu driver file\n*/\n\n/*!\n \\defgroup IFX_MD5_HMAC_FUNCTIONS IFX_MD5_HMAC_FUNCTIONS\n \\ingroup IFX_DEU\n \\brief ifx md5-hmac driver functions\n*/\n\n/* Project Header files */\n#include <linux/init.h>\n#include <linux/module.h>\n#include <linux/string.h>\n#include <linux/crypto.h>\n#include <linux/types.h>\n#include <crypto/internal/hash.h>\n#include <asm/byteorder.h>\n\n#if defined(CONFIG_AR9)\n#include \"ifxmips_deu_ar9.h\"\n#elif defined(CONFIG_VR9) || defined(CONFIG_AR10)\n#include \"ifxmips_deu_vr9.h\"\n#else\n#error \"Plaform Unknwon!\"\n#endif\n\n#define MD5_DIGEST_SIZE     16\n#define MD5_HMAC_BLOCK_SIZE 64\n#define MD5_BLOCK_WORDS     16\n#define MD5_HASH_WORDS      4\n#define MD5_HMAC_DBN_TEMP_SIZE  1024 // size in dword, needed for dbn workaround \n#define HASH_START   IFX_HASH_CON\n\n//#define CRYPTO_DEBUG\n#ifdef CRYPTO_DEBUG\nextern char debug_level;\n#define DPRINTF(level, format, args...) if (level < debug_level) printk(KERN_INFO \"[%s %s %d]: \" format, __FILE__, __func__, __LINE__, ##args);\n#else\n#define DPRINTF(level, format, args...)\n#endif\n\n#define MAX_HASH_KEYLEN 64\n\nstruct md5_hmac_ctx {\n    u8 key[MAX_HASH_KEYLEN];\n    u32 hash[MD5_HASH_WORDS];\n    u32 block[MD5_BLOCK_WORDS];\n    u64 byte_count;\n    u32 dbn;\n    int started;\n    unsigned int keylen;\n    struct shash_desc *desc;\n    u32 (*temp)[MD5_BLOCK_WORDS];\n};\n\nextern int disable_deudma;\n\nstatic int md5_hmac_final_impl(struct shash_desc *desc, u8 *out, bool hash_final);\n\n/*! \\fn static void md5_hmac_transform(struct crypto_tfm *tfm, u32 const *in)\n *  \\ingroup IFX_MD5_HMAC_FUNCTIONS\n *  \\brief save input block to context   \n *  \\param tfm linux crypto algo transform  \n *  \\param in 64-byte block of input  \n*/                                 \nstatic void md5_hmac_transform(struct shash_desc *desc, u32 const *in)\n{\n    struct md5_hmac_ctx *mctx = crypto_shash_ctx(desc->tfm);\n\n    if ( ((mctx->dbn<<4)+1) > MD5_HMAC_DBN_TEMP_SIZE )\n    {\n        //printk(\"MD5_HMAC_DBN_TEMP_SIZE exceeded\\n\");\n        md5_hmac_final_impl(desc, (u8 *)mctx->hash, false);\n    }\n\n    memcpy(&mctx->temp[mctx->dbn], in, 64); //dbn workaround\n    mctx->dbn += 1;\n}\n\n/*! \\fn int md5_hmac_setkey(struct crypto_tfm *tfm, const u8 *key, unsigned int keylen)\n *  \\ingroup IFX_MD5_HMAC_FUNCTIONS\n *  \\brief sets md5 hmac key   \n *  \\param tfm linux crypto algo transform  \n *  \\param key input key  \n *  \\param keylen key length greater than 64 bytes IS NOT SUPPORTED  \n*/  \nstatic int md5_hmac_setkey(struct crypto_shash *tfm, const u8 *key, unsigned int keylen) \n{\n    struct md5_hmac_ctx *mctx = crypto_shash_ctx(tfm);\n    int err;\n    //printk(\"copying keys to context with length %d\\n\", keylen);\n\n    if (keylen > MAX_HASH_KEYLEN) {\n        char *hash_alg_name = \"md5\";\n\n        mctx->desc->tfm = crypto_alloc_shash(hash_alg_name, 0, 0);\n        if (IS_ERR(mctx->desc->tfm)) return PTR_ERR(mctx->desc->tfm);\n\n        memset(mctx->key, 0, MAX_HASH_KEYLEN);\n        err = crypto_shash_digest(mctx->desc, key, keylen, mctx->key);\n        if (err) return err;\n\n        mctx->keylen = MD5_DIGEST_SIZE;\n\n        crypto_free_shash(mctx->desc->tfm);\n    } else {\n        memcpy(mctx->key, key, keylen);\n        mctx->keylen = keylen;\n    }\n    memset(mctx->key + mctx->keylen, 0, MAX_HASH_KEYLEN - mctx->keylen);\n\n    return 0;\n}\n\n/*! \\fn int md5_hmac_setkey_hw(const u8 *key, unsigned int keylen)\n *  \\ingroup IFX_MD5_HMAC_FUNCTIONS\n *  \\brief sets md5 hmac key into the hardware registers  \n *  \\param key input key  \n *  \\param keylen key length greater than 64 bytes IS NOT SUPPORTED  \n*/  \nstatic int md5_hmac_setkey_hw(const u8 *key, unsigned int keylen)\n{\n    volatile struct deu_hash_t *hash = (struct deu_hash_t *) HASH_START;\n    int i, j;\n    u32 *in_key = (u32 *)key;        \n\n    //printk(\"\\nsetkey keylen: %d\\n key: \", keylen);\n    \n    hash->KIDX |= 0x80000000; // reset all 16 words of the key to '0'\n    j = 0;\n    for (i = 0; i < keylen; i+=4)\n    {\n         hash->KIDX = j;\n         asm(\"sync\");\n         hash->KEY = *((u32 *) in_key + j); \n         asm(\"sync\");\n         j++;\n    }\n\n    return 0;\n}\n\n/*! \\fn void md5_hmac_init(struct crypto_tfm *tfm)\n *  \\ingroup IFX_MD5_HMAC_FUNCTIONS\n *  \\brief initialize md5 hmac context   \n *  \\param tfm linux crypto algo transform  \n*/                                 \nstatic int md5_hmac_init(struct shash_desc *desc)\n{\n\n    struct md5_hmac_ctx *mctx = crypto_shash_ctx(desc->tfm);\n    \n\n    mctx->dbn = 0; //dbn workaround\n    mctx->started = 0;\n    mctx->byte_count = 0;\n\n    return 0;\n}\n    \n/*! \\fn void md5_hmac_update(struct crypto_tfm *tfm, const u8 *data, unsigned int len)\n *  \\ingroup IFX_MD5_HMAC_FUNCTIONS\n *  \\brief on-the-fly md5 hmac computation   \n *  \\param tfm linux crypto algo transform  \n *  \\param data input data  \n *  \\param len size of input data  \n*/                                 \nstatic int md5_hmac_update(struct shash_desc *desc, const u8 *data, unsigned int len)\n{\n    struct md5_hmac_ctx *mctx = crypto_shash_ctx(desc->tfm);\n    const u32 avail = sizeof(mctx->block) - (mctx->byte_count & 0x3f);\n\n    mctx->byte_count += len;\n    \n    if (avail > len) {\n        memcpy((char *)mctx->block + (sizeof(mctx->block) - avail),\n               data, len);\n        return 0;\n    }\n\n    memcpy((char *)mctx->block + (sizeof(mctx->block) - avail),\n           data, avail);\n\n    md5_hmac_transform(desc, mctx->block);\n    data += avail;\n    len -= avail;\n\n    while (len >= sizeof(mctx->block)) {\n        memcpy(mctx->block, data, sizeof(mctx->block));\n        md5_hmac_transform(desc, mctx->block);\n        data += sizeof(mctx->block);\n        len -= sizeof(mctx->block);\n    }\n\n    memcpy(mctx->block, data, len);\n    return 0;    \n}\n\n/*! \\fn static int md5_hmac_final(struct crypto_tfm *tfm, u8 *out)\n *  \\ingroup IFX_MD5_HMAC_FUNCTIONS\n *  \\brief call md5_hmac_final_impl with hash_final true   \n *  \\param tfm linux crypto algo transform  \n *  \\param out final md5 hmac output value  \n*/                                 \nstatic int md5_hmac_final(struct shash_desc *desc, u8 *out)\n{\n    return md5_hmac_final_impl(desc, out, true);\n}\n\n/*! \\fn static int md5_hmac_final_impl(struct crypto_tfm *tfm, u8 *out, bool hash_final)\n *  \\ingroup IFX_MD5_HMAC_FUNCTIONS\n *  \\brief compute final or intermediate md5 hmac value   \n *  \\param tfm linux crypto algo transform  \n *  \\param out final md5 hmac output value  \n *  \\param in finalize or intermediate processing  \n*/                                 \nstatic int md5_hmac_final_impl(struct shash_desc *desc, u8 *out, bool hash_final)\n{\n    struct md5_hmac_ctx *mctx = crypto_shash_ctx(desc->tfm);\n    const unsigned int offset = mctx->byte_count & 0x3f;\n    char *p = (char *)mctx->block + offset;\n    int padding = 56 - (offset + 1);\n    volatile struct deu_hash_t *hashs = (struct deu_hash_t *) HASH_START;\n    unsigned long flag;\n    int i = 0;\n    int dbn;\n    u32 *in = mctx->temp[0];\n\n    if (hash_final) {\n        *p++ = 0x80;\n        if (padding < 0) {\n            memset(p, 0x00, padding + sizeof (u64));\n            md5_hmac_transform(desc, mctx->block);\n            p = (char *)mctx->block;\n            padding = 56;\n        }\n\n        memset(p, 0, padding);\n        mctx->block[14] = le32_to_cpu((mctx->byte_count + 64) << 3); // need to add 512 bit of the IPAD operation \n        mctx->block[15] = 0x00000000;\n\n        md5_hmac_transform(desc, mctx->block);\n    }\n\n    CRTCL_SECT_HASH_START;\n\n    MD5_HASH_INIT;\n\n    md5_hmac_setkey_hw(mctx->key, mctx->keylen);\n\n    //printk(\"\\ndbn = %d\\n\", mctx->dbn); \n    if (hash_final) {\n       hashs->DBN = mctx->dbn;\n    } else {\n       hashs->DBN = mctx->dbn + 5;\n    }\n    asm(\"sync\");\n    \n    *IFX_HASH_CON = 0x0703002D; //khs, go, init, ndc, endi, kyue, hmen, md5 \t\n\n    //wait for processing\n    while (hashs->controlr.BSY) {\n        // this will not take long\n    }\n\n    if (mctx->started) {\n        hashs->D1R = *((u32 *) mctx->hash + 0);\n        hashs->D2R = *((u32 *) mctx->hash + 1);\n        hashs->D3R = *((u32 *) mctx->hash + 2);\n        hashs->D4R = *((u32 *) mctx->hash + 3);\n    } else {\n        mctx->started = 1;\n    }\n\n    for (dbn = 0; dbn < mctx->dbn; dbn++)\n    {\n        for (i = 0; i < 16; i++) {\n            hashs->MR = in[i];\n        };\n\n        hashs->controlr.GO = 1;\n        asm(\"sync\");\n\n        //wait for processing\n        while (hashs->controlr.BSY) {\n           // this will not take long\n        }\n    \n        in += 16;\n}\n\n#if 1\n    if (hash_final) {\n        //wait for digest ready\n        while (! hashs->controlr.DGRY) {\n            // this will not take long\n        }\n    }\n#endif\n\n    *((u32 *) out + 0) = hashs->D1R;\n    *((u32 *) out + 1) = hashs->D2R;\n    *((u32 *) out + 2) = hashs->D3R;\n    *((u32 *) out + 3) = hashs->D4R;\n\n    CRTCL_SECT_HASH_END;\n\n    if (hash_final) {\n        /* reset the context after we finish with the hash */\n        md5_hmac_init(desc);\n    } else {\n        mctx->dbn = 0;\n    }\n    return 0;\n}\n\n/*! \\fn void md5_hmac_init_tfm(struct crypto_tfm *tfm)\n *  \\ingroup IFX_MD5_HMAC_FUNCTIONS\n *  \\brief initialize pointers in md5_hmac_ctx\n *  \\param tfm linux crypto algo transform\n*/\nstatic int md5_hmac_init_tfm(struct crypto_tfm *tfm)\n{\n    struct md5_hmac_ctx *mctx = crypto_tfm_ctx(tfm);\n    mctx->temp = kzalloc(4 * MD5_HMAC_DBN_TEMP_SIZE, GFP_KERNEL);\n    if (IS_ERR(mctx->temp)) return PTR_ERR(mctx->temp);\n    mctx->desc = kzalloc(sizeof(struct shash_desc), GFP_KERNEL);\n    if (IS_ERR(mctx->desc)) return PTR_ERR(mctx->desc);\n\n    return 0;\n}\n\n/*! \\fn void md5_hmac_exit_tfm(struct crypto_tfm *tfm)\n *  \\ingroup IFX_MD5_HMAC_FUNCTIONS\n *  \\brief free pointers in md5_hmac_ctx\n *  \\param tfm linux crypto algo transform\n*/\nstatic void md5_hmac_exit_tfm(struct crypto_tfm *tfm)\n{\n    struct md5_hmac_ctx *mctx = crypto_tfm_ctx(tfm);\n    kfree(mctx->temp);\n    kfree(mctx->desc);\n}\n\n/* \n * \\brief MD5_HMAC function mappings\n*/\nstatic struct shash_alg ifxdeu_md5_hmac_alg = {\n    .digestsize         =       MD5_DIGEST_SIZE,\n    .init               =       md5_hmac_init,\n    .update             =       md5_hmac_update,\n    .final              =       md5_hmac_final,\n    .setkey             =       md5_hmac_setkey,\n    .descsize           =       sizeof(struct md5_hmac_ctx),\n    .base               =       {\n        .cra_name       =       \"hmac(md5)\",\n        .cra_driver_name=       \"ifxdeu-md5_hmac\",\n        .cra_priority   =       400,\n        .cra_ctxsize    =       sizeof(struct md5_hmac_ctx),\n        .cra_flags      =       CRYPTO_ALG_TYPE_HASH | CRYPTO_ALG_KERN_DRIVER_ONLY,\n        .cra_blocksize  =       MD5_HMAC_BLOCK_SIZE,\n        .cra_module     =       THIS_MODULE,\n        .cra_init       =       md5_hmac_init_tfm,\n        .cra_exit       =       md5_hmac_exit_tfm,\n        }\n};\n\n/*! \\fn int ifxdeu_init_md5_hmac (void)\n *  \\ingroup IFX_MD5_HMAC_FUNCTIONS\n *  \\brief initialize md5 hmac driver   \n*/                                 \nint ifxdeu_init_md5_hmac (void)\n{\n\n    int ret = -ENOSYS;\n\n\n    if ((ret = crypto_register_shash(&ifxdeu_md5_hmac_alg)))\n        goto md5_hmac_err;\n\n    printk (KERN_NOTICE \"IFX DEU MD5_HMAC initialized%s.\\n\", disable_deudma ? \"\" : \" (DMA)\");\n    return ret;\n\nmd5_hmac_err:\n    printk(KERN_ERR \"IFX DEU MD5_HMAC initialization failed!\\n\");\n    return ret;\n}\n\n/** \\fn void ifxdeu_fini_md5_hmac (void)\n *  \\ingroup IFX_MD5_HMAC_FUNCTIONS\n *  \\brief unregister md5 hmac driver   \n*/                                 \nvoid ifxdeu_fini_md5_hmac (void)\n{\n    crypto_unregister_shash(&ifxdeu_md5_hmac_alg);\n}\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-deu/src/ifxmips_sha1.c",
    "content": "/******************************************************************************\n**\n** FILE NAME    : ifxmips_sha1.c\n** PROJECT      : IFX UEIP\n** MODULES      : DEU Module for Danube\n**\n** DATE         : September 8, 2009\n** AUTHOR       : Mohammad Firdaus\n** DESCRIPTION  : Data Encryption Unit Driver\n** COPYRIGHT    :       Copyright (c) 2009\n**                      Infineon Technologies AG\n**                      Am Campeon 1-12, 85579 Neubiberg, Germany\n**\n**    This program is free software; you can redistribute it and/or modify\n**    it under the terms of the GNU General Public License as published by\n**    the Free Software Foundation; either version 2 of the License, or\n**    (at your option) any later version.\n**\n** HISTORY\n** $Date        $Author             $Comment\n** 08,Sept 2009 Mohammad Firdaus    Initial UEIP release\n*******************************************************************************/\n/*!\n  \\defgroup IFX_DEU IFX_DEU_DRIVERS\n  \\ingroup API\n  \\brief ifx deu driver module\n*/\n\n/*!\n  \\file\tifxmips_sha1.c\n  \\ingroup IFX_DEU\n  \\brief SHA1 encryption deu driver file\n*/\n\n/*!\n  \\defgroup IFX_SHA1_FUNCTIONS IFX_SHA1_FUNCTIONS\n  \\ingroup IFX_DEU\n  \\brief ifx deu sha1 functions\n*/\n\n/* Project header */\n#include <linux/init.h>\n#include <linux/module.h>\n#include <linux/mm.h>\n#include <linux/crypto.h>\n#include <crypto/sha.h>\n#include <crypto/hash.h>\n#include <crypto/internal/hash.h>\n#include <linux/types.h>\n#include <linux/scatterlist.h>\n#include <asm/byteorder.h>\n\n#if defined(CONFIG_DANUBE)\n#include \"ifxmips_deu_danube.h\"\n#elif defined(CONFIG_AR9)\n#include \"ifxmips_deu_ar9.h\"\n#elif defined(CONFIG_VR9) || defined(CONFIG_AR10)\n#include \"ifxmips_deu_vr9.h\"\n#else\n#error \"Plaform Unknwon!\"\n#endif\n\n#define SHA1_DIGEST_SIZE    20\n#define SHA1_HMAC_BLOCK_SIZE    64\n#define HASH_START   IFX_HASH_CON\n\n//#define CRYPTO_DEBUG\n#ifdef CRYPTO_DEBUG\nextern char debug_level;\n#define DPRINTF(level, format, args...) if (level < debug_level) printk(KERN_INFO \"[%s %s %d]: \" format, __FILE__, __func__, __LINE__, ##args);\n#else\n#define DPRINTF(level, format, args...)\n#endif\n\n/*\n * \\brief SHA1 private structure\n*/\nstruct sha1_ctx {\n\tint started;\n        u64 count;\n\tu32 hash[5];\n        u32 state[5];\n        u8 buffer[64];\n};\n\nextern int disable_deudma;\n\n/*! \\fn static void sha1_transform1 (u32 *state, const u32 *in)\n *  \\ingroup IFX_SHA1_FUNCTIONS\n *  \\brief main interface to sha1 hardware   \n *  \\param state current state \n *  \\param in 64-byte block of input  \n*/                                 \nstatic void sha1_transform1 (struct sha1_ctx *sctx, u32 *state, const u32 *in)\n{\n    int i = 0;\n    volatile struct deu_hash_t *hashs = (struct deu_hash_t *) HASH_START;\n    unsigned long flag;\n\n    CRTCL_SECT_HASH_START;\n\n    SHA_HASH_INIT;\n\n    /* For context switching purposes, the previous hash output\n     * is loaded back into the output register \n    */\n    if (sctx->started) {\n        hashs->D1R = *((u32 *) sctx->hash + 0);\n        hashs->D2R = *((u32 *) sctx->hash + 1);\n        hashs->D3R = *((u32 *) sctx->hash + 2);\n        hashs->D4R = *((u32 *) sctx->hash + 3);\n        hashs->D5R = *((u32 *) sctx->hash + 4);\n    }\n\n    for (i = 0; i < 16; i++) {\n        hashs->MR = in[i];\n    };\n\n    //wait for processing\n    while (hashs->controlr.BSY) {\n        // this will not take long\n    }\n   \n    /* For context switching purposes, the output is saved into a \n     * context struct which can be used later on \n    */\n    *((u32 *) sctx->hash + 0) = hashs->D1R;\n    *((u32 *) sctx->hash + 1) = hashs->D2R;\n    *((u32 *) sctx->hash + 2) = hashs->D3R;\n    *((u32 *) sctx->hash + 3) = hashs->D4R;\n    *((u32 *) sctx->hash + 4) = hashs->D5R;\n\n    sctx->started = 1;\n\n    CRTCL_SECT_HASH_END;\n}\n\n/*! \\fn static void sha1_init1(struct crypto_tfm *tfm)\n *  \\ingroup IFX_SHA1_FUNCTIONS\n *  \\brief initialize sha1 hardware   \n *  \\param tfm linux crypto algo transform  \n*/                                 \nstatic int sha1_init1(struct shash_desc *desc)\n{\n    struct sha1_ctx *sctx = shash_desc_ctx(desc);\n    \n    sctx->started = 0;\n    sctx->count = 0;\n    return 0;\n}\n\n/*! \\fn static void sha1_update(struct crypto_tfm *tfm, const u8 *data, unsigned int len)\n *  \\ingroup IFX_SHA1_FUNCTIONS\n *  \\brief on-the-fly sha1 computation   \n *  \\param tfm linux crypto algo transform  \n *  \\param data input data  \n *  \\param len size of input data  \n*/                                 \nstatic int sha1_update(struct shash_desc * desc, const u8 *data,\n            unsigned int len)\n{\n    struct sha1_ctx *sctx = shash_desc_ctx(desc);\n    unsigned int i, j;\n\n    j = (sctx->count >> 3) & 0x3f;\n    sctx->count += len << 3;\n\n    if ((j + len) > 63) {\n        memcpy (&sctx->buffer[j], data, (i = 64 - j));\n        sha1_transform1 (sctx, sctx->state, (const u32 *)sctx->buffer);\n        for (; i + 63 < len; i += 64) {\n            sha1_transform1 (sctx, sctx->state, (const u32 *)&data[i]);\n        }\n\n        j = 0;\n    }\n    else\n        i = 0;\n\n    memcpy (&sctx->buffer[j], &data[i], len - i);\n    return 0;\n}\n\n/*! \\fn static void sha1_final(struct crypto_tfm *tfm, u8 *out)\n *  \\ingroup IFX_SHA1_FUNCTIONS\n *  \\brief compute final sha1 value   \n *  \\param tfm linux crypto algo transform  \n *  \\param out final md5 output value  \n*/                                 \nstatic int sha1_final(struct shash_desc *desc, u8 *out)\n{\n    struct sha1_ctx *sctx = shash_desc_ctx(desc);\n    u32 index, padlen;\n    u64 t;\n    u8 bits[8] = { 0, };\n    static const u8 padding[64] = { 0x80, };\n    volatile struct deu_hash_t *hashs = (struct deu_hash_t *) HASH_START;\n    unsigned long flag;\n\n    t = sctx->count;\n    bits[7] = 0xff & t;\n    t >>= 8;\n    bits[6] = 0xff & t;\n    t >>= 8;\n    bits[5] = 0xff & t;\n    t >>= 8;\n    bits[4] = 0xff & t;\n    t >>= 8;\n    bits[3] = 0xff & t;\n    t >>= 8;\n    bits[2] = 0xff & t;\n    t >>= 8;\n    bits[1] = 0xff & t;\n    t >>= 8;\n    bits[0] = 0xff & t;\n\n    /* Pad out to 56 mod 64 */\n    index = (sctx->count >> 3) & 0x3f;\n    padlen = (index < 56) ? (56 - index) : ((64 + 56) - index);\n    sha1_update (desc, padding, padlen);\n\n    /* Append length */\n    sha1_update (desc, bits, sizeof bits);\n\n    memcpy(out, sctx->hash, SHA1_DIGEST_SIZE);\n\n    // Wipe context\n    memset (sctx, 0, sizeof *sctx);\n\n    return 0;\n}\n\n/* \n * \\brief SHA1 function mappings\n*/\nstatic struct shash_alg ifxdeu_sha1_alg = {\n        .digestsize     =       SHA1_DIGEST_SIZE,\n        .init           =       sha1_init1,\n        .update         =       sha1_update,\n        .final          =       sha1_final,\n        .descsize       =       sizeof(struct sha1_ctx),\n        .statesize      =       sizeof(struct sha1_state),\n        .base           =       {\n                .cra_name       =       \"sha1\",\n                .cra_driver_name=       \"ifxdeu-sha1\",\n                .cra_priority   =       300,\n                .cra_flags      =       CRYPTO_ALG_TYPE_HASH | CRYPTO_ALG_KERN_DRIVER_ONLY,\n                .cra_blocksize  =       SHA1_HMAC_BLOCK_SIZE,\n                .cra_module     =       THIS_MODULE,\n        }\n};\n\n\n/*! \\fn int ifxdeu_init_sha1 (void)\n *  \\ingroup IFX_SHA1_FUNCTIONS\n *  \\brief initialize sha1 driver    \n*/                                 \nint ifxdeu_init_sha1 (void)\n{\n    int ret = -ENOSYS;\n\n\n    if ((ret = crypto_register_shash(&ifxdeu_sha1_alg)))\n        goto sha1_err;\n\n    printk (KERN_NOTICE \"IFX DEU SHA1 initialized%s.\\n\", disable_deudma ? \"\" : \" (DMA)\");\n    return ret;\n\nsha1_err:\n    printk(KERN_ERR \"IFX DEU SHA1 initialization failed!\\n\");\n    return ret;\n}\n\n/*! \\fn void ifxdeu_fini_sha1 (void)\n *  \\ingroup IFX_SHA1_FUNCTIONS\n *  \\brief unregister sha1 driver   \n*/                                 \nvoid ifxdeu_fini_sha1 (void)\n{\n    crypto_unregister_shash(&ifxdeu_sha1_alg);\n\n\n}\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-deu/src/ifxmips_sha1_hmac.c",
    "content": "/******************************************************************************\n**\n** FILE NAME    : ifxmips_sha1_hmac.c\n** PROJECT      : IFX UEIP\n** MODULES      : DEU Module for UEIP\n** DATE         : September 8, 2009\n** AUTHOR       : Mohammad Firdaus\n** DESCRIPTION  : Data Encryption Unit Driver\n** COPYRIGHT    :       Copyright (c) 2009\n**                      Infineon Technologies AG\n**                      Am Campeon 1-12, 85579 Neubiberg, Germany\n**\n**    This program is free software; you can redistribute it and/or modify\n**    it under the terms of the GNU General Public License as published by\n**    the Free Software Foundation; either version 2 of the License, or\n**    (at your option) any later version.\n**\n** HISTORY\n** $Date        $Author             $Comment\n** 08,Sept 2009 Mohammad Firdaus    Initial UEIP release\n** 21,March 2011 Mohammad Firdaus   Changes for Kernel 2.6.32 and IPSec integration\n*******************************************************************************/\n/*!\n  \\defgroup IFX_DEU IFX_DEU_DRIVERS\n  \\ingroup API\n  \\brief ifx deu driver module\n*/\n\n/*!\n  \\file\tifxmips_sha1_hmac.c\n  \\ingroup IFX_DEU\n  \\brief SHA1-HMAC deu driver file\n*/\n\n/*! \n  \\defgroup IFX_SHA1_HMAC_FUNCTIONS IFX_SHA1_HMAC_FUNCTIONS\n  \\ingroup IFX_DEU\n  \\brief ifx sha1 hmac functions\n*/\n\n/* Project header */\n#include <linux/init.h>\n#include <linux/module.h>\n#include <linux/mm.h>\n#include <linux/crypto.h>\n#include <crypto/internal/hash.h>\n#include <crypto/sha.h>\n#include <linux/types.h>\n#include <linux/scatterlist.h>\n#include <asm/byteorder.h>\n#include <linux/delay.h>\n\n#if defined(CONFIG_AR9)\n#include \"ifxmips_deu_ar9.h\"\n#elif defined(CONFIG_VR9) || defined(CONFIG_AR10)\n#include \"ifxmips_deu_vr9.h\"\n#else\n#error \"Plaform Unknwon!\"\n#endif\n\n#define SHA1_DIGEST_SIZE    20\n#define SHA1_BLOCK_WORDS    16\n#define SHA1_HASH_WORDS     5\n#define SHA1_HMAC_BLOCK_SIZE    64\n#define SHA1_HMAC_DBN_TEMP_SIZE 1024 // size in dword, needed for dbn workaround \n#define HASH_START   IFX_HASH_CON\n\n#define SHA1_HMAC_MAX_KEYLEN 64\n\n#ifdef CRYPTO_DEBUG\nextern char debug_level;\n#define DPRINTF(level, format, args...) if (level < debug_level) printk(KERN_INFO \"[%s %s %d]: \" format, __FILE__, __func__, __LINE__, ##args);\n#else\n#define DPRINTF(level, format, args...)\n#endif\n\nstruct sha1_hmac_ctx {\n    int keylen;\n\n    u8 buffer[SHA1_HMAC_BLOCK_SIZE];\n    u8 key[SHA1_HMAC_MAX_KEYLEN];\n    u32 hash[SHA1_HASH_WORDS];\n    u32 dbn;\n    int started;\n    u64 count;\n\n    struct shash_desc *desc;\n    u32 (*temp)[SHA1_BLOCK_WORDS];\n};\n\nextern int disable_deudma;\n\nstatic int sha1_hmac_final_impl(struct shash_desc *desc, u8 *out, bool hash_final);\n\n/*! \\fn static void sha1_hmac_transform(struct crypto_tfm *tfm, u32 const *in)\n *  \\ingroup IFX_SHA1_HMAC_FUNCTIONS\n *  \\brief save input block to context   \n *  \\param tfm linux crypto algo transform  \n *  \\param in 64-byte block of input  \n*/                                 \nstatic int sha1_hmac_transform(struct shash_desc *desc, u32 const *in)\n{\n    struct sha1_hmac_ctx *sctx =  crypto_shash_ctx(desc->tfm);\n\n    if ( ((sctx->dbn<<4)+1) > SHA1_HMAC_DBN_TEMP_SIZE )\n    {\n        //printk(\"SHA1_HMAC_DBN_TEMP_SIZE exceeded\\n\");\n        sha1_hmac_final_impl(desc, (u8 *)sctx->hash, false);\n    }\n\n    memcpy(&sctx->temp[sctx->dbn], in, 64); //dbn workaround\n    sctx->dbn += 1;\n\n    return 0;\n}\n\n/*! \\fn int sha1_hmac_setkey(struct crypto_tfm *tfm, const u8 *key, unsigned int keylen)\n *  \\ingroup IFX_SHA1_HMAC_FUNCTIONS\n *  \\brief sets sha1 hmac key   \n *  \\param tfm linux crypto algo transform  \n *  \\param key input key  \n *  \\param keylen key length greater than 64 bytes IS NOT SUPPORTED  \n*/                                 \nstatic int sha1_hmac_setkey(struct crypto_shash *tfm, const u8 *key, unsigned int keylen)\n{\n    struct sha1_hmac_ctx *sctx = crypto_shash_ctx(tfm);\n    int err;\n\n    if (keylen > SHA1_HMAC_MAX_KEYLEN) {\n        char *hash_alg_name = \"sha1\";\n\n        sctx->desc->tfm = crypto_alloc_shash(hash_alg_name, 0, 0);\n        if (IS_ERR(sctx->desc->tfm)) return PTR_ERR(sctx->desc->tfm);\n\n        memset(sctx->key, 0, SHA1_HMAC_MAX_KEYLEN);\n        err = crypto_shash_digest(sctx->desc, key, keylen, sctx->key);\n        if (err) return err;\n\n        sctx->keylen = SHA1_DIGEST_SIZE;\n\n        crypto_free_shash(sctx->desc->tfm);\n    } else {\n        memcpy(sctx->key, key, keylen);\n        sctx->keylen = keylen;\n    }\n    memset(sctx->key + sctx->keylen, 0, SHA1_HMAC_MAX_KEYLEN - sctx->keylen);\n\n    //printk(\"Setting keys of len: %d\\n\", keylen);\n\n    return 0;\n}\n\n/*! \\fn int sha1_hmac_setkey_hw(struct crypto_tfm *tfm, const u8 *key, unsigned int keylen)\n *  \\ingroup IFX_SHA1_HMAC_FUNCTIONS\n *  \\brief sets sha1 hmac key  into hw registers \n *  \\param tfm linux crypto algo transform  \n *  \\param key input key  \n *  \\param keylen key length greater than 64 bytes IS NOT SUPPORTED  \n*/                                 \nstatic int sha1_hmac_setkey_hw(const u8 *key, unsigned int keylen)\n{\n    volatile struct deu_hash_t *hash = (struct deu_hash_t *) HASH_START;\n    int i, j;\n    u32 *in_key = (u32 *)key;        \n\n    j = 0;\n\n    hash->KIDX |= 0x80000000; //reset keys back to 0\n    for (i = 0; i < keylen; i+=4)\n    {\n         hash->KIDX = j;\n         asm(\"sync\");\n         hash->KEY = *((u32 *) in_key + j); \n         j++;\n    }\n\n    return 0;\n}\n\n/*! \\fn void sha1_hmac_init(struct crypto_tfm *tfm)\n *  \\ingroup IFX_SHA1_HMAC_FUNCTIONS\n *  \\brief initialize sha1 hmac context   \n *  \\param tfm linux crypto algo transform  \n*/                                 \nstatic int sha1_hmac_init(struct shash_desc *desc)\n{\n    struct sha1_hmac_ctx *sctx =  crypto_shash_ctx(desc->tfm);\n\n    //printk(\"debug ln: %d, fn: %s\\n\", __LINE__, __func__);\n    sctx->dbn = 0; //dbn workaround\n    sctx->started = 0;\n    sctx->count = 0;\n\n    return 0;\n}\n\n/*! \\fn static void sha1_hmac_update(struct crypto_tfm *tfm, const u8 *data, unsigned int len)\n *  \\ingroup IFX_SHA1_HMAC_FUNCTIONS\n *  \\brief on-the-fly sha1 hmac computation   \n *  \\param tfm linux crypto algo transform  \n *  \\param data input data  \n *  \\param len size of input data \n*/                                 \nstatic int sha1_hmac_update(struct shash_desc *desc, const u8 *data,\n            unsigned int len)\n{\n    struct sha1_hmac_ctx *sctx =  crypto_shash_ctx(desc->tfm);\n    unsigned int i, j;\n\n    j = (sctx->count >> 3) & 0x3f;\n    sctx->count += len << 3;\n   // printk(\"sctx->count = %d\\n\", sctx->count);\n\n    if ((j + len) > 63) {\n        memcpy (&sctx->buffer[j], data, (i = 64 - j));\n        sha1_hmac_transform (desc, (const u32 *)sctx->buffer);\n        for (; i + 63 < len; i += 64) {\n            sha1_hmac_transform (desc, (const u32 *)&data[i]);\n        }\n\n        j = 0;\n    }\n    else\n        i = 0;\n\n    memcpy (&sctx->buffer[j], &data[i], len - i);\n    return 0;\n}\n\n/*! \\fn static int sha1_hmac_final(struct crypto_tfm *tfm, u8 *out)\n *  \\ingroup IFX_SHA1_HMAC_FUNCTIONS\n *  \\brief call sha1_hmac_final_impl with hash_final true   \n *  \\param tfm linux crypto algo transform  \n *  \\param out final sha1 hmac output value  \n*/                                 \nstatic int sha1_hmac_final(struct shash_desc *desc, u8 *out)\n{\n    return sha1_hmac_final_impl(desc, out, true);\n}\n\n/*! \\fn static int sha1_hmac_final_impl(struct crypto_tfm *tfm, u8 *out, bool hash_final)\n *  \\ingroup IFX_SHA1_HMAC_FUNCTIONS\n *  \\brief ompute final or intermediate sha1 hmac value   \n *  \\param tfm linux crypto algo transform  \n *  \\param out final sha1 hmac output value  \n *  \\param in finalize or intermediate processing  \n*/                                 \nstatic int sha1_hmac_final_impl(struct shash_desc *desc, u8 *out, bool hash_final)\n{\n    struct sha1_hmac_ctx *sctx =  crypto_shash_ctx(desc->tfm);\n    u32 index, padlen;\n    u64 t;\n    u8 bits[8] = { 0, };\n    static const u8 padding[64] = { 0x80, };\n    volatile struct deu_hash_t *hashs = (struct deu_hash_t *) HASH_START;\n    unsigned long flag;\n    int i = 0;\n    int dbn;\n    u32 *in = sctx->temp[0];\n\n    if (hash_final) {\n        t = sctx->count + 512; // need to add 512 bit of the IPAD operation\n        bits[7] = 0xff & t;\n        t >>= 8;\n        bits[6] = 0xff & t;\n        t >>= 8;\n        bits[5] = 0xff & t;\n        t >>= 8;\n        bits[4] = 0xff & t;\n        t >>= 8;\n        bits[3] = 0xff & t;\n        t >>= 8;\n        bits[2] = 0xff & t;\n        t >>= 8;\n        bits[1] = 0xff & t;\n        t >>= 8;\n        bits[0] = 0xff & t;\n\n        /* Pad out to 56 mod 64 */\n        index = (sctx->count >> 3) & 0x3f;\n        padlen = (index < 56) ? (56 - index) : ((64 + 56) - index);\n        sha1_hmac_update (desc, padding, padlen);\n\n        /* Append length */\n        sha1_hmac_update (desc, bits, sizeof bits);\n    }\n\n    CRTCL_SECT_HASH_START;\n\n    SHA_HASH_INIT;\n\n    sha1_hmac_setkey_hw(sctx->key, sctx->keylen);\n\n    if (hash_final) {\n        hashs->DBN = sctx->dbn;\n    } else {\n        hashs->DBN = sctx->dbn + 5;\n    }\n    asm(\"sync\");\n\n    //for vr9 change, ENDI = 1\n    *IFX_HASH_CON = HASH_CON_VALUE; \n\n    //wait for processing\n    while (hashs->controlr.BSY) {\n        // this will not take long\n    }\n\n    if (sctx->started) {\n        hashs->D1R = *((u32 *) sctx->hash + 0);\n        hashs->D2R = *((u32 *) sctx->hash + 1);\n        hashs->D3R = *((u32 *) sctx->hash + 2);\n        hashs->D4R = *((u32 *) sctx->hash + 3);\n        hashs->D5R = *((u32 *) sctx->hash + 4);\n    } else {\n        sctx->started = 1;\n    }\n\n    for (dbn = 0; dbn < sctx->dbn; dbn++)\n    {\n        for (i = 0; i < 16; i++) {\n            hashs->MR = in[i];\n        };\n\n        hashs->controlr.GO = 1;\n        asm(\"sync\");\n\n        //wait for processing\n        while (hashs->controlr.BSY) {\n            // this will not take long\n        }\n    \n        in += 16;\n    }\n\n\n#if 1\n    if (hash_final) {\n        //wait for digest ready\n        while (! hashs->controlr.DGRY) {\n            // this will not take long\n        }\n    }\n#endif\n\n    *((u32 *) out + 0) = hashs->D1R;\n    *((u32 *) out + 1) = hashs->D2R;\n    *((u32 *) out + 2) = hashs->D3R;\n    *((u32 *) out + 3) = hashs->D4R;\n    *((u32 *) out + 4) = hashs->D5R;\n\n    CRTCL_SECT_HASH_END;\n\n    if (hash_final) {\n        sha1_hmac_init(desc);\n    } else {\n        sctx->dbn = 0;\n    }\n    //printk(\"debug ln: %d, fn: %s\\n\", __LINE__, __func__);\n\n    return 0;\n\n}\n\n/*! \\fn void sha1_hmac_init_tfm(struct crypto_tfm *tfm)\n *  \\ingroup IFX_SHA1_HMAC_FUNCTIONS\n *  \\brief initialize pointers in sha1_hmac_ctx\n *  \\param tfm linux crypto algo transform\n*/\nstatic int sha1_hmac_init_tfm(struct crypto_tfm *tfm)\n{\n    struct sha1_hmac_ctx *sctx = crypto_tfm_ctx(tfm);\n    sctx->temp = kzalloc(4 * SHA1_HMAC_DBN_TEMP_SIZE, GFP_KERNEL);\n    if (IS_ERR(sctx->temp)) return PTR_ERR(sctx->temp);\n    sctx->desc = kzalloc(sizeof(struct shash_desc), GFP_KERNEL);\n    if (IS_ERR(sctx->desc)) return PTR_ERR(sctx->desc);\n\n    return 0;\n}\n\n/*! \\fn void sha1_hmac_exit_tfm(struct crypto_tfm *tfm)\n *  \\ingroup IFX_SHA1_HMAC_FUNCTIONS\n *  \\brief free pointers in sha1_hmac_ctx\n *  \\param tfm linux crypto algo transform\n*/\nstatic void sha1_hmac_exit_tfm(struct crypto_tfm *tfm)\n{\n    struct sha1_hmac_ctx *sctx = crypto_tfm_ctx(tfm);\n    kfree(sctx->temp);\n    kfree(sctx->desc);\n}\n\n/* \n * \\brief SHA1_HMAC function mappings\n*/\n\nstatic struct shash_alg ifxdeu_sha1_hmac_alg = {\n    .digestsize         =       SHA1_DIGEST_SIZE,\n    .init               =       sha1_hmac_init,\n    .update             =       sha1_hmac_update,\n    .final              =       sha1_hmac_final,\n    .setkey             =       sha1_hmac_setkey,\n    .descsize           =       sizeof(struct sha1_hmac_ctx),\n    .base               =       {\n        .cra_name       =       \"hmac(sha1)\",\n        .cra_driver_name=       \"ifxdeu-sha1_hmac\",\n        .cra_priority   =       400,\n        .cra_ctxsize    =       sizeof(struct sha1_hmac_ctx),\n        .cra_flags      =       CRYPTO_ALG_TYPE_HASH | CRYPTO_ALG_KERN_DRIVER_ONLY,\n        .cra_blocksize  =       SHA1_HMAC_BLOCK_SIZE,\n        .cra_module     =       THIS_MODULE,\n        .cra_init       =       sha1_hmac_init_tfm,\n        .cra_exit       =       sha1_hmac_exit_tfm,\n        }\n};\n\n/*! \\fn int ifxdeu_init_sha1_hmac (void)\n *  \\ingroup IFX_SHA1_HMAC_FUNCTIONS\n *  \\brief initialize sha1 hmac driver    \n*/                                 \nint ifxdeu_init_sha1_hmac (void)\n{\n    int ret = -ENOSYS;\n\n\n\n    if ((ret = crypto_register_shash(&ifxdeu_sha1_hmac_alg)))\n        goto sha1_err;\n\n    printk (KERN_NOTICE \"IFX DEU SHA1_HMAC initialized%s.\\n\", disable_deudma ? \"\" : \" (DMA)\");\n    return ret;\n\nsha1_err:\n    printk(KERN_ERR \"IFX DEU SHA1_HMAC initialization failed!\\n\");\n    return ret;\n}\n\n/*! \\fn void ifxdeu_fini_sha1_hmac (void)\n *  \\ingroup IFX_SHA1_HMAC_FUNCTIONS\n *  \\brief unregister sha1 hmac driver    \n*/                                 \nvoid ifxdeu_fini_sha1_hmac (void)\n{\n\n    crypto_unregister_shash(&ifxdeu_sha1_hmac_alg);\n\n\n}\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-deu/src/ifxmips_tcrypt.h",
    "content": "/*\n * Quick & dirty crypto testing module.\n *\n * This will only exist until we have a better testing mechanism\n * (e.g. a char device).\n *\n * Copyright (c) 2002 James Morris <jmorris@intercode.com.au>\n * Copyright (c) 2002 Jean-Francois Dive <jef@linuxbe.org>\n * Copyright (c) 2007 Nokia Siemens Networks\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of the GNU General Public License as published by the Free\n * Software Foundation; either version 2 of the License, or (at your option)\n * any later version.\n *\n */\n#ifndef _IFXMIPS_CRYPTO_TCRYPT_H\n#define _IFXMIPS_CRYPTO_TCRYPT_H\n\nstruct cipher_speed_template {\n\tconst char *key;\n\tunsigned int klen;\n};\n\nstruct hash_speed {\n\tunsigned int blen;\t/* buffer length */\n\tunsigned int plen;\t/* per-update length */\n};\n\n/*\n * DES test vectors.\n */\n#define DES3_SPEED_VECTORS\t1\n#define CRYPTO_ALG_TYPE_SPEED_TEST 0xB\n\nstatic int alg_speed_test(const char *alg, const char *driver,\n\t\t\t  unsigned int sec,\n\t\t\t  struct cipher_speed_template *t,\n\t\t\t  unsigned int tcount, u8 *keysize);\n\nstatic struct cipher_speed_template des3_speed_template[] = {\n\t{\n\t\t.key\t= \"\\x01\\x23\\x45\\x67\\x89\\xab\\xcd\\xef\"\n\t\t\t  \"\\x55\\x55\\x55\\x55\\x55\\x55\\x55\\x55\"\n\t\t\t  \"\\xfe\\xdc\\xba\\x98\\x76\\x54\\x32\\x10\",\n\t\t.klen\t= 24,\n\t}\n};\n\n/*\n * Cipher speed tests\n */\nstatic u8 speed_template_8[] = {8, 0};\nstatic u8 speed_template_24[] = {24, 0};\nstatic u8 speed_template_8_32[] = {8, 32, 0};\nstatic u8 speed_template_16_32[] = {16, 32, 0};\nstatic u8 speed_template_16_24_32[] = {16, 24, 32, 0};\nstatic u8 speed_template_32_40_48[] = {32, 40, 48, 0};\nstatic u8 speed_template_32_48_64[] = {32, 48, 64, 0};\n\n/*\n * Digest speed tests\n */\nstatic struct hash_speed generic_hash_speed_template[] = {\n\t{ .blen = 16,\t.plen = 16, },\n\t{ .blen = 64,\t.plen = 16, },\n\t{ .blen = 64,\t.plen = 64, },\n\t{ .blen = 256,\t.plen = 16, },\n\t{ .blen = 256,\t.plen = 64, },\n\t{ .blen = 256,\t.plen = 256, },\n\t{ .blen = 1024,\t.plen = 16, },\n\t{ .blen = 1024,\t.plen = 256, },\n\t{ .blen = 1024,\t.plen = 1024, },\n\t{ .blen = 2048,\t.plen = 16, },\n\t{ .blen = 2048,\t.plen = 256, },\n\t{ .blen = 2048,\t.plen = 1024, },\n\t{ .blen = 2048,\t.plen = 2048, },\n\t{ .blen = 4096,\t.plen = 16, },\n\t{ .blen = 4096,\t.plen = 256, },\n\t{ .blen = 4096,\t.plen = 1024, },\n\t{ .blen = 4096,\t.plen = 4096, },\n\t{ .blen = 8192,\t.plen = 16, },\n\t{ .blen = 8192,\t.plen = 256, },\n\t{ .blen = 8192,\t.plen = 1024, },\n\t{ .blen = 8192,\t.plen = 4096, },\n\t{ .blen = 8192,\t.plen = 8192, },\n\n\t/* End marker */\n\t{  .blen = 0,\t.plen = 0, }\n};\n\n#endif\t/* _CRYPTO_TCRYPT_H */\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-deu/src/internal.h",
    "content": "/*\n * Cryptographic API.\n *\n * Copyright (c) 2002 James Morris <jmorris@intercode.com.au>\n * Copyright (c) 2005 Herbert Xu <herbert@gondor.apana.org.au>\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of the GNU General Public License as published by the Free\n * Software Foundation; either version 2 of the License, or (at your option) \n * any later version.\n *\n */\n#ifndef _CRYPTO_INTERNAL_H\n#define _CRYPTO_INTERNAL_H\n\n#include <crypto/algapi.h>\n#include <linux/completion.h>\n#include <linux/mm.h>\n#include <linux/highmem.h>\n#include <linux/interrupt.h>\n#include <linux/init.h>\n#include <linux/list.h>\n#include <linux/module.h>\n#include <linux/kernel.h>\n#include <linux/notifier.h>\n#include <linux/rwsem.h>\n#include <linux/slab.h>\n#include <linux/fips.h>\n\n/* Crypto notification events. */\nenum {\n\tCRYPTO_MSG_ALG_REQUEST,\n\tCRYPTO_MSG_ALG_REGISTER,\n\tCRYPTO_MSG_ALG_UNREGISTER,\n\tCRYPTO_MSG_TMPL_REGISTER,\n\tCRYPTO_MSG_TMPL_UNREGISTER,\n};\n\nstruct crypto_instance;\nstruct crypto_template;\n\nstruct crypto_larval {\n\tstruct crypto_alg alg;\n\tstruct crypto_alg *adult;\n\tstruct completion completion;\n\tu32 mask;\n};\n\nextern struct list_head crypto_alg_list;\nextern struct rw_semaphore crypto_alg_sem;\nextern struct blocking_notifier_head crypto_chain;\n\n#ifdef CONFIG_PROC_FS\nvoid __init crypto_init_proc(void);\nvoid __exit crypto_exit_proc(void);\n#else\nstatic inline void crypto_init_proc(void)\n{ }\nstatic inline void crypto_exit_proc(void)\n{ }\n#endif\n\nstatic inline unsigned int crypto_cipher_ctxsize(struct crypto_alg *alg)\n{\n\treturn alg->cra_ctxsize;\n}\n\nstatic inline unsigned int crypto_compress_ctxsize(struct crypto_alg *alg)\n{\n\treturn alg->cra_ctxsize;\n}\n\nstruct crypto_alg *crypto_mod_get(struct crypto_alg *alg);\nstruct crypto_alg *crypto_alg_lookup(const char *name, u32 type, u32 mask);\nstruct crypto_alg *crypto_alg_mod_lookup(const char *name, u32 type, u32 mask);\n\nint crypto_init_cipher_ops(struct crypto_tfm *tfm);\nint crypto_init_compress_ops(struct crypto_tfm *tfm);\n\nvoid crypto_exit_cipher_ops(struct crypto_tfm *tfm);\nvoid crypto_exit_compress_ops(struct crypto_tfm *tfm);\n\nstruct crypto_larval *crypto_larval_alloc(const char *name, u32 type, u32 mask);\nvoid crypto_larval_kill(struct crypto_alg *alg);\nstruct crypto_alg *crypto_larval_lookup(const char *name, u32 type, u32 mask);\nvoid crypto_larval_error(const char *name, u32 type, u32 mask);\nvoid crypto_alg_tested(const char *name, int err);\n\nvoid crypto_shoot_alg(struct crypto_alg *alg);\nstruct crypto_tfm *__crypto_alloc_tfm(struct crypto_alg *alg, u32 type,\n\t\t\t\t      u32 mask);\nvoid *crypto_create_tfm(struct crypto_alg *alg,\n\t\t\tconst struct crypto_type *frontend);\nstruct crypto_alg *crypto_find_alg(const char *alg_name,\n\t\t\t\t   const struct crypto_type *frontend,\n\t\t\t\t   u32 type, u32 mask);\nvoid *crypto_alloc_tfm(const char *alg_name,\n\t\t       const struct crypto_type *frontend, u32 type, u32 mask);\n\nint crypto_register_notifier(struct notifier_block *nb);\nint crypto_unregister_notifier(struct notifier_block *nb);\nint crypto_probing_notify(unsigned long val, void *v);\n\nstatic inline void crypto_alg_put(struct crypto_alg *alg)\n{\n\tif (atomic_dec_and_test(&alg->cra_refcnt) && alg->cra_destroy)\n\t\talg->cra_destroy(alg);\n}\n\nstatic inline int crypto_tmpl_get(struct crypto_template *tmpl)\n{\n\treturn try_module_get(tmpl->module);\n}\n\nstatic inline void crypto_tmpl_put(struct crypto_template *tmpl)\n{\n\tmodule_put(tmpl->module);\n}\n\nstatic inline int crypto_is_larval(struct crypto_alg *alg)\n{\n\treturn alg->cra_flags & CRYPTO_ALG_LARVAL;\n}\n\nstatic inline int crypto_is_dead(struct crypto_alg *alg)\n{\n\treturn alg->cra_flags & CRYPTO_ALG_DEAD;\n}\n\nstatic inline int crypto_is_moribund(struct crypto_alg *alg)\n{\n\treturn alg->cra_flags & (CRYPTO_ALG_DEAD | CRYPTO_ALG_DYING);\n}\n\nstatic inline void crypto_notify(unsigned long val, void *v)\n{\n\tblocking_notifier_call_chain(&crypto_chain, val, v);\n}\n\n#endif\t/* _CRYPTO_INTERNAL_H */\n\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-ifxos/Makefile",
    "content": "# Copyright (C) 2009-2012 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n\ninclude $(TOPDIR)/rules.mk\ninclude $(INCLUDE_DIR)/kernel.mk\n\nPKG_NAME:=ifxos\nPKG_VERSION:=1.7.1\nPKG_RELEASE:=$(AUTORELEASE)\n\nUGW_VERSION=8.5.2.10\nUGW_BASENAME=$(PKG_NAME)-ugw_$(UGW_VERSION)\n\nPKG_SOURCE:=$(UGW_BASENAME).tar.bz2\nPKG_BUILD_DIR:=$(KERNEL_BUILD_DIR)/$(UGW_BASENAME)\nPKG_SOURCE_URL:=https://gitlab.com/prpl-foundation/intel/$(PKG_NAME)/-/archive/ugw_$(UGW_VERSION)/\nPKG_HASH:=055a1f5eab0abfaac34ac7b1613b93ec341fe9ae8462cb11c36c2b0989ce0ca7\nPKG_MAINTAINER:=John Crispin <john@phrozen.org>\nPKG_LICENSE:=GPL-2.0 BSD-2-Clause\nPKG_LICENSE_FILES:=LICENSE\nPKG_EXTMOD_SUBDIRS:=src\n\nPKG_FIXUP:=autoreconf\n\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine KernelPackage/ltq-ifxos\n  SECTION:=sys\n  CATEGORY:=Kernel modules\n  SUBMENU:=Libraries\n  TITLE:=Lantiq OS abstraction library\n  URL:=http://www.lantiq.com/\n  DEPENDS:=@TARGET_lantiq\n  FILES:=$(PKG_BUILD_DIR)/src/drv_ifxos.ko\n  AUTOLOAD:=$(call AutoLoad,10,drv_ifxos)\nendef\n\nCONFIGURE_ARGS += \\\n\tARCH=$(LINUX_KARCH) \\\n\t--enable-linux-26 \\\n\t--enable-kernelbuild=\"$(LINUX_DIR)\" \\\n\t--enable-kernelincl=\"$(LINUX_DIR)/include\" \\\n\t--with-kernel-module\n\nifdef CONFIG_TARGET_lantiq\n  define Build/InstallDev\n\t$(INSTALL_DIR) $(1)/usr/{lib,include/ifxos}\n\t$(CP) $(PKG_BUILD_DIR)/src/include/* $(1)/usr/include/ifxos\n\tmkdir -p $(1)/usr/lib\n\t$(CP) $(PKG_BUILD_DIR)/src/.libs/libifxos.a $(1)/usr/lib/libifxos.a\n  endef\nendif\n\n$(eval $(call KernelPackage,ltq-ifxos))\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-ifxos/patches/001-warnings.patch",
    "content": "--- a/src/include/linux/ifxos_linux_common.h\n+++ b/src/include/linux/ifxos_linux_common.h\n@@ -49,6 +49,7 @@\n    IFX Linux adaptation - Includes (Linux Kernel)\n    ========================================================================= */\n #include <linux/kernel.h>\n+#include <linux/version.h>\n #include <asm/byteorder.h>\n \n /* ============================================================================\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-ifxos/patches/002-fix-compile.patch",
    "content": "--- a/src/linux/ifxos_linux_socket_drv.c\n+++ b/src/linux/ifxos_linux_socket_drv.c\n@@ -28,7 +28,7 @@\n #include <linux/net.h>\n #include <linux/fs.h>\n #include <linux/inet.h>\n-#include <asm/uaccess.h>\n+#include <linux/uaccess.h>\n \n #include \"ifx_types.h\"\n #include \"ifxos_rt_if_check.h\"\n--- a/src/linux/ifxos_linux_socket_ipv6_drv.c\n+++ b/src/linux/ifxos_linux_socket_ipv6_drv.c\n@@ -25,7 +25,7 @@\n #include <linux/version.h>\n #include <linux/in.h>\n #include <linux/net.h>\n-#include <asm/uaccess.h>\n+#include <linux/uaccess.h>\n \n #include \"ifx_types.h\"\n #include \"ifxos_rt_if_check.h\"\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-ifxos/patches/020-no-O3.patch",
    "content": "--- a/src/Makefile.am\n+++ b/src/Makefile.am\n@@ -48,8 +48,6 @@ endif !HAVE_GCC\n \n if ENABLE_DEBUG\n used_gcc_cflags += -O1 -g\n-else\n-used_gcc_cflags += -O3\n endif\n \n AM_CFLAGS = \\\n@@ -92,7 +90,6 @@ endif\n drvifxos_additional_cflags=\\\n \t-DLINUX \\\n \t-D__LINUX__ \\\n-\t-O \\\n \t-D__KERNEL__ \\\n \t-DMODULE \\\n \t-DEXPORT_SYMTAB\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-ifxos/patches/100-compat.patch",
    "content": "--- a/src/linux/ifxos_linux_memory_map_drv.c\n+++ b/src/linux/ifxos_linux_memory_map_drv.c\n@@ -25,6 +25,7 @@\n    IFX Linux adaptation - Global Includes - Kernel\n    ========================================================================= */\n \n+#include <linux/version.h>\n #include <linux/kernel.h>\n #ifdef MODULE\n    #include <linux/module.h>\n@@ -97,8 +98,13 @@ IFX_int32_t IFXOS_Phy2VirtMap(\n    }\n \n    /* remap memory (not cache able): physical --> virtual */\n+#if LINUX_VERSION_CODE < KERNEL_VERSION(5,6,0)\n    pVirtAddr = (IFX_uint8_t *)ioremap_nocache( physicalAddr,\n                                                addrRangeSize_byte );\n+#else\n+   pVirtAddr = (IFX_uint8_t *)ioremap(physicalAddr, addrRangeSize_byte);\n+#endif\n+\n    if (pVirtAddr == IFX_NULL)\n    {\n       IFXOS_PRN_USR_ERR_NL( IFXOS, IFXOS_PRN_LEVEL_ERR,\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-ptm/Makefile",
    "content": "# Copyright (C) 2012 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\ninclude $(INCLUDE_DIR)/kernel.mk\n\nPKG_NAME:=ltq-ptm\nPKG_RELEASE:=3\n\nPKG_MAINTAINER:=John Crispin <john@phrozen.org>\nPKG_LICENSE:=GPL-2.0+\n\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine KernelPackage/ltq-ptm-template\n  SECTION:=sys\n  CATEGORY:=Kernel modules\n  SUBMENU:=Network Devices\n  TITLE:=ptm driver for $(1)\n  URL:=http://www.lantiq.com/\n  VARIANT:=$(1)\n  DEPENDS:=@TARGET_lantiq_$(2)\nifeq ($(1),vr9)\n  DEPENDS+= +PACKAGE_kmod-ltq-ptm-$(1):kmod-ltq-vdsl-vr9-mei\nelse\n  DEPENDS+= +PACKAGE_kmod-ltq-ptm-$(1):kmod-ltq-adsl-$(1)-mei\nendif\nifeq ($(1),ase)\n  DEPENDS+=@BROKEN\nendif\n  FILES:=$(PKG_BUILD_DIR)/ltq_ptm_$(1).ko \nendef\n\nKernelPackage/ltq-ptm-danube=$(call KernelPackage/ltq-ptm-template,danube,xway)\nKernelPackage/ltq-ptm-ar9=$(call KernelPackage/ltq-ptm-template,ar9,xway)\nKernelPackage/ltq-ptm-ase=$(call KernelPackage/ltq-ptm-template,ase,ase)\nKernelPackage/ltq-ptm-vr9=$(call KernelPackage/ltq-ptm-template,vr9,xrx200)\n\ndefine Build/Configure\nendef\n\ndefine Build/Compile\n\tcd $(LINUX_DIR); \\\n\t\tARCH=mips CROSS_COMPILE=\"$(KERNEL_CROSS)\" \\\n\t\t$(MAKE) $(KERNEL_MAKE_FLAGS) BUILD_VARIANT=$(BUILD_VARIANT) M=$(PKG_BUILD_DIR) V=1 modules\nendef\n\n$(eval $(call KernelPackage,ltq-ptm-danube))\n$(eval $(call KernelPackage,ltq-ptm-ase))\n$(eval $(call KernelPackage,ltq-ptm-ar9))\n$(eval $(call KernelPackage,ltq-ptm-vr9))\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-ptm/src/Makefile",
    "content": "ifeq ($(BUILD_VARIANT),danube)\n  CFLAGS_MODULE+=-DCONFIG_DANUBE\n  obj-m = ltq_ptm_danube.o\n  ltq_ptm_danube-objs = ifxmips_ptm_adsl.o ifxmips_ptm_danube.o\nendif\n\nifeq ($(BUILD_VARIANT),ase)\n  CFLAGS_MODULE+=-DCONFIG_AMAZON_SE\n  obj-m = ltq_ptm_ase.o\n  ltq_ptm_ase-objs = ifxmips_ptm_adsl.o ifxmips_ptm_amazon_se.o\nendif\n\nifeq ($(BUILD_VARIANT),ar9)\n  CFLAGS_MODULE+=-DCONFIG_AR9\n  obj-m = ltq_ptm_ar9.o\n  ltq_ptm_ar9-objs = ifxmips_ptm_adsl.o ifxmips_ptm_ar9.o\nendif\n\nifeq ($(BUILD_VARIANT),vr9)\n  CFLAGS_MODULE+=-DCONFIG_VR9\n  obj-m = ltq_ptm_vr9.o\n  ltq_ptm_vr9-objs = ifxmips_ptm_vdsl.o ifxmips_ptm_vr9.o\nendif\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-ptm/src/ifxmips_ptm_adsl.c",
    "content": "/******************************************************************************\n**\n** FILE NAME    : ifxmips_ptm_adsl.c\n** PROJECT      : UEIP\n** MODULES      : PTM\n**\n** DATE         : 7 Jul 2009\n** AUTHOR       : Xu Liang\n** DESCRIPTION  : PTM driver common source file (core functions for Danube/\n**                Amazon-SE/AR9)\n** COPYRIGHT    :       Copyright (c) 2006\n**                      Infineon Technologies AG\n**                      Am Campeon 1-12, 85579 Neubiberg, Germany\n**\n**    This program is free software; you can redistribute it and/or modify\n**    it under the terms of the GNU General Public License as published by\n**    the Free Software Foundation; either version 2 of the License, or\n**    (at your option) any later version.\n**\n** HISTORY\n** $Date        $Author         $Comment\n** 07 JUL 2009  Xu Liang        Init Version\n*******************************************************************************/\n\n\n\n/*\n * ####################################\n *              Head File\n * ####################################\n */\n\n/*\n *  Common Head File\n */\n#include <linux/version.h>\n#include <linux/kernel.h>\n#include <linux/module.h>\n#include <linux/types.h>\n#include <linux/errno.h>\n#include <linux/proc_fs.h>\n#include <linux/init.h>\n#include <linux/ioctl.h>\n#include <linux/etherdevice.h>\n#include <linux/interrupt.h>\n#include <linux/netdevice.h>\n#include <linux/platform_device.h>\n#include <linux/of_device.h>\n#include <asm/io.h>\n\n/*\n *  Chip Specific Head File\n */\n#include \"ifxmips_ptm_adsl.h\"\n\n\n#include <lantiq_soc.h>\n\n/*\n * ####################################\n *        Kernel Version Adaption\n * ####################################\n */\n  #define MODULE_PARM_ARRAY(a, b)   module_param_array(a, int, NULL, 0)\n  #define MODULE_PARM(a, b)         module_param(a, int, 0)\n\n\n\n/*\n * ####################################\n *   Parameters to Configure PPE\n * ####################################\n */\n\nstatic int write_desc_delay     = 0x20;         /*  Write descriptor delay                          */\n\nstatic int rx_max_packet_size   = ETH_MAX_FRAME_LENGTH;\n                                                /*  Max packet size for RX                          */\n\nstatic int dma_rx_descriptor_length = 24;       /*  Number of descriptors per DMA RX channel        */\nstatic int dma_tx_descriptor_length = 24;       /*  Number of descriptors per DMA TX channel        */\n\nstatic int eth_efmtc_crc_cfg = 0x03100710;      /*  default: tx_eth_crc_check: 1, tx_tc_crc_check: 1, tx_tc_crc_len = 16    */\n                                                /*           rx_eth_crc_present: 1, rx_eth_crc_check: 1, rx_tc_crc_check: 1, rx_tc_crc_len = 16 */\n\nMODULE_PARM(write_desc_delay, \"i\");\nMODULE_PARM_DESC(write_desc_delay, \"PPE core clock cycles between descriptor write and effectiveness in external RAM\");\n\nMODULE_PARM(rx_max_packet_size, \"i\");\nMODULE_PARM_DESC(rx_max_packet_size, \"Max packet size in byte for downstream ethernet frames\");\n\nMODULE_PARM(dma_rx_descriptor_length, \"i\");\nMODULE_PARM_DESC(dma_rx_descriptor_length, \"Number of descriptor assigned to DMA RX channel (>16)\");\nMODULE_PARM(dma_tx_descriptor_length, \"i\");\nMODULE_PARM_DESC(dma_tx_descriptor_length, \"Number of descriptor assigned to DMA TX channel (>16)\");\n\nMODULE_PARM(eth_efmtc_crc_cfg, \"i\");\nMODULE_PARM_DESC(eth_efmtc_crc_cfg, \"Configuration for PTM TX/RX ethernet/efm-tc CRC\");\n\n\n\n/*\n * ####################################\n *              Definition\n * ####################################\n */\n\n\n#define DUMP_SKB_LEN                            ~0\n\n\n\n/*\n * ####################################\n *             Declaration\n * ####################################\n */\n\n/*\n *  Network Operations\n */\nstatic void ptm_setup(struct net_device *, int);\nstatic struct net_device_stats *ptm_get_stats(struct net_device *);\nstatic int ptm_open(struct net_device *);\nstatic int ptm_stop(struct net_device *);\n  static unsigned int ptm_poll(int, unsigned int);\n  static int ptm_napi_poll(struct napi_struct *, int);\nstatic int ptm_hard_start_xmit(struct sk_buff *, struct net_device *);\nstatic int ptm_ioctl(struct net_device *, struct ifreq *, int);\n#if LINUX_VERSION_CODE < KERNEL_VERSION(5,6,0)\nstatic void ptm_tx_timeout(struct net_device *);\n#else\nstatic void ptm_tx_timeout(struct net_device *, unsigned int txqueue);\n#endif\n\n/*\n *  DSL Data LED\n */\nstatic INLINE void adsl_led_flash(void);\n\n/*\n *  buffer manage functions\n */\nstatic INLINE struct sk_buff* alloc_skb_rx(void);\n//static INLINE struct sk_buff* alloc_skb_tx(unsigned int);\nstatic INLINE struct sk_buff *get_skb_rx_pointer(unsigned int);\nstatic INLINE int get_tx_desc(unsigned int, unsigned int *);\n\n/*\n *  Mailbox handler and signal function\n */\nstatic INLINE int mailbox_rx_irq_handler(unsigned int);\nstatic irqreturn_t mailbox_irq_handler(int, void *);\nstatic INLINE void mailbox_signal(unsigned int, int);\n#ifdef CONFIG_IFX_PTM_RX_TASKLET\n  static void do_ptm_tasklet(unsigned long);\n#endif\n\n/*\n *  Debug Functions\n */\n#if defined(DEBUG_DUMP_SKB) && DEBUG_DUMP_SKB\n  static void dump_skb(struct sk_buff *, u32, char *, int, int, int);\n#else\n  #define dump_skb(skb, len, title, port, ch, is_tx)    do {} while (0)\n#endif\n#if defined(ENABLE_DBG_PROC) && ENABLE_DBG_PROC\n  static void skb_swap(struct sk_buff *);\n#else\n  #define skb_swap(skb)                                 do {} while (0)\n#endif\n\n/*\n *  Proc File Functions\n */\nstatic INLINE void proc_file_create(void);\nstatic INLINE void proc_file_delete(void);\nstatic int proc_read_version(char *, char **, off_t, int, int *, void *);\nstatic int proc_read_wanmib(char *, char **, off_t, int, int *, void *);\nstatic int proc_write_wanmib(struct file *, const char *, unsigned long, void *);\n#if defined(ENABLE_FW_PROC) && ENABLE_FW_PROC\n  static int proc_read_genconf(char *, char **, off_t, int, int *, void *);\n#endif\n#if defined(ENABLE_DBG_PROC) && ENABLE_DBG_PROC\n  static int proc_read_dbg(char *, char **, off_t, int, int *, void *);\n  static int proc_write_dbg(struct file *, const char *, unsigned long, void *);\n#endif\n\n/*\n *  Proc Help Functions\n */\nstatic INLINE int stricmp(const char *, const char *);\n#if defined(ENABLE_DBG_PROC) && ENABLE_DBG_PROC\n  static INLINE int strincmp(const char *, const char *, int);\n#endif\nstatic INLINE int ifx_ptm_version(char *);\n\n/*\n *  Init & clean-up functions\n */\nstatic INLINE void check_parameters(void);\nstatic INLINE int init_priv_data(void);\nstatic INLINE void clear_priv_data(void);\nstatic INLINE void init_tables(void);\n\n/*\n *  Exteranl Function\n */\n#if defined(CONFIG_IFXMIPS_DSL_CPE_MEI) || defined(CONFIG_IFXMIPS_DSL_CPE_MEI_MODULE)\n  extern int ifx_mei_atm_showtime_check(int *is_showtime, struct port_cell_info *port_cell, void **xdata_addr);\n#else\n  static inline int ifx_mei_atm_showtime_check(int *is_showtime, struct port_cell_info *port_cell, void **xdata_addr)\n  {\n    if ( is_showtime != NULL )\n        *is_showtime = 0;\n    return 0;\n  }\n#endif\n\n/*\n *  External variable\n */\n#if defined(CONFIG_IFXMIPS_DSL_CPE_MEI) || defined(CONFIG_IFXMIPS_DSL_CPE_MEI_MODULE)\n  extern int (*ifx_mei_atm_showtime_enter)(struct port_cell_info *, void *);\n  extern int (*ifx_mei_atm_showtime_exit)(void);\n#else\n  int (*ifx_mei_atm_showtime_enter)(struct port_cell_info *, void *) = NULL;\n  EXPORT_SYMBOL(ifx_mei_atm_showtime_enter);\n  int (*ifx_mei_atm_showtime_exit)(void) = NULL;\n  EXPORT_SYMBOL(ifx_mei_atm_showtime_exit);\n#endif\n\n\n\n/*\n * ####################################\n *            Local Variable\n * ####################################\n */\n\nstatic struct ptm_priv_data g_ptm_priv_data;\n\nstatic struct net_device_ops g_ptm_netdev_ops = {\n    .ndo_get_stats       = ptm_get_stats,\n    .ndo_open            = ptm_open,\n    .ndo_stop            = ptm_stop,\n    .ndo_start_xmit      = ptm_hard_start_xmit,\n    .ndo_validate_addr   = eth_validate_addr,\n    .ndo_set_mac_address = eth_mac_addr,\n    .ndo_do_ioctl        = ptm_ioctl,\n    .ndo_tx_timeout      = ptm_tx_timeout,\n};\n\nstatic struct net_device *g_net_dev[2] = {0};\nstatic char *g_net_dev_name[2] = {\"dsl0\", \"dslfast0\"};\n\n#ifdef CONFIG_IFX_PTM_RX_TASKLET\n  static struct tasklet_struct g_ptm_tasklet[] = {\n    {NULL, 0, ATOMIC_INIT(0), do_ptm_tasklet, 0},\n    {NULL, 0, ATOMIC_INIT(0), do_ptm_tasklet, 1},\n  };\n#endif\n\nunsigned int ifx_ptm_dbg_enable = DBG_ENABLE_MASK_ERR;\n\nstatic struct proc_dir_entry* g_ptm_dir = NULL;\n\nstatic int g_showtime = 0;\n\n\n\n/*\n * ####################################\n *            Local Function\n * ####################################\n */\n\nstatic void ptm_setup(struct net_device *dev, int ndev)\n{\n#if defined(CONFIG_IFXMIPS_DSL_CPE_MEI) || defined(CONFIG_IFXMIPS_DSL_CPE_MEI_MODULE)\n    netif_carrier_off(dev);\n#endif\n\n    /*  hook network operations */\n    dev->netdev_ops      = &g_ptm_netdev_ops;\n    /* Allow up to 1508 bytes, for RFC4638 */\n    dev->max_mtu         = ETH_DATA_LEN + 8;\n    netif_napi_add(dev, &g_ptm_priv_data.itf[ndev].napi, ptm_napi_poll, 25);\n    dev->watchdog_timeo  = ETH_WATCHDOG_TIMEOUT;\n\n    dev->dev_addr[0] = 0x00;\n    dev->dev_addr[1] = 0x20;\n    dev->dev_addr[2] = 0xda;\n    dev->dev_addr[3] = 0x86;\n    dev->dev_addr[4] = 0x23;\n    dev->dev_addr[5] = 0x75 + ndev;\n}\n\nstatic struct net_device_stats *ptm_get_stats(struct net_device *dev)\n{\n    int ndev;\n\n    for ( ndev = 0; ndev < ARRAY_SIZE(g_net_dev) && g_net_dev[ndev] != dev; ndev++ );\n    ASSERT(ndev >= 0 && ndev < ARRAY_SIZE(g_net_dev), \"ndev = %d (wrong value)\", ndev);\n\n    g_ptm_priv_data.itf[ndev].stats.rx_errors   = WAN_MIB_TABLE[ndev].wrx_tccrc_err_pdu + WAN_MIB_TABLE[ndev].wrx_ethcrc_err_pdu;\n    g_ptm_priv_data.itf[ndev].stats.rx_dropped  = WAN_MIB_TABLE[ndev].wrx_nodesc_drop_pdu + WAN_MIB_TABLE[ndev].wrx_len_violation_drop_pdu + (WAN_MIB_TABLE[ndev].wrx_correct_pdu - g_ptm_priv_data.itf[ndev].stats.rx_packets);\n\n    return &g_ptm_priv_data.itf[ndev].stats;\n}\n\nstatic int ptm_open(struct net_device *dev)\n{\n    int ndev;\n\n    for ( ndev = 0; ndev < ARRAY_SIZE(g_net_dev) && g_net_dev[ndev] != dev; ndev++ );\n    ASSERT(ndev >= 0 && ndev < ARRAY_SIZE(g_net_dev), \"ndev = %d (wrong value)\", ndev);\n\n    napi_enable(&g_ptm_priv_data.itf[ndev].napi);\n\n    IFX_REG_W32_MASK(0, 1 << ndev, MBOX_IGU1_IER);\n\n    netif_start_queue(dev);\n\n    return 0;\n}\n\nstatic int ptm_stop(struct net_device *dev)\n{\n    int ndev;\n\n    for ( ndev = 0; ndev < ARRAY_SIZE(g_net_dev) && g_net_dev[ndev] != dev; ndev++ );\n    ASSERT(ndev >= 0 && ndev < ARRAY_SIZE(g_net_dev), \"ndev = %d (wrong value)\", ndev);\n\n    IFX_REG_W32_MASK((1 << ndev) | (1 << (ndev + 16)), 0, MBOX_IGU1_IER);\n\n    napi_disable(&g_ptm_priv_data.itf[ndev].napi);\n\n    netif_stop_queue(dev);\n\n    return 0;\n}\n\nstatic unsigned int ptm_poll(int ndev, unsigned int work_to_do)\n{\n    unsigned int work_done = 0;\n\n    ASSERT(ndev >= 0 && ndev < ARRAY_SIZE(g_net_dev), \"ndev = %d (wrong value)\", ndev);\n\n    while ( work_done < work_to_do && WRX_DMA_CHANNEL_CONFIG(ndev)->vlddes > 0 ) {\n        if ( mailbox_rx_irq_handler(ndev) < 0 )\n            break;\n\n        work_done++;\n    }\n\n    return work_done;\n}\nstatic int ptm_napi_poll(struct napi_struct *napi, int budget)\n{\n    int ndev;\n    unsigned int work_done;\n\n    for ( ndev = 0; ndev < ARRAY_SIZE(g_net_dev) && g_net_dev[ndev] != napi->dev; ndev++ );\n\n    work_done = ptm_poll(ndev, budget);\n\n    //  interface down\n    if ( !netif_running(napi->dev) ) {\n        napi_complete(napi);\n        return work_done;\n    }\n\n    //  no more traffic\n    if ( WRX_DMA_CHANNEL_CONFIG(ndev)->vlddes == 0 ) {\n        //  clear interrupt\n        IFX_REG_W32_MASK(0, 1 << ndev, MBOX_IGU1_ISRC);\n        //  double check\n        if ( WRX_DMA_CHANNEL_CONFIG(ndev)->vlddes == 0 ) {\n            napi_complete(napi);\n            IFX_REG_W32_MASK(0, 1 << ndev, MBOX_IGU1_IER);\n            return work_done;\n        }\n    }\n\n    //  next round\n    return work_done;\n}\n\nstatic int ptm_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)\n{\n    int ndev;\n    unsigned int f_full;\n    int desc_base;\n    register struct tx_descriptor reg_desc = {0};\n\n    for ( ndev = 0; ndev < ARRAY_SIZE(g_net_dev) && g_net_dev[ndev] != dev; ndev++ );\n    ASSERT(ndev >= 0 && ndev < ARRAY_SIZE(g_net_dev), \"ndev = %d (wrong value)\", ndev);\n\n    if ( !g_showtime ) {\n        err(\"not in showtime\");\n        goto PTM_HARD_START_XMIT_FAIL;\n    }\n\n    /*  allocate descriptor */\n    desc_base = get_tx_desc(ndev, &f_full);\n    if ( f_full ) {\n        netif_trans_update(dev);\n        netif_stop_queue(dev);\n\n        IFX_REG_W32_MASK(0, 1 << (ndev + 16), MBOX_IGU1_ISRC);\n        IFX_REG_W32_MASK(0, 1 << (ndev + 16), MBOX_IGU1_IER);\n    }\n    if ( desc_base < 0 )\n        goto PTM_HARD_START_XMIT_FAIL;\n\n    if ( g_ptm_priv_data.itf[ndev].tx_skb[desc_base] != NULL )\n        dev_kfree_skb_any(g_ptm_priv_data.itf[ndev].tx_skb[desc_base]);\n    g_ptm_priv_data.itf[ndev].tx_skb[desc_base] = skb;\n\n    reg_desc.dataptr = (unsigned int)skb->data >> 2;\n    reg_desc.datalen = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len;\n    reg_desc.byteoff = (unsigned int)skb->data & (DATA_BUFFER_ALIGNMENT - 1);\n    reg_desc.own     = 1;\n    reg_desc.c       = 1;\n    reg_desc.sop = reg_desc.eop = 1;\n\n    /*  write discriptor to memory and write back cache */\n    g_ptm_priv_data.itf[ndev].tx_desc[desc_base] = reg_desc;\n    dma_cache_wback((unsigned long)skb->data, skb->len);\n    wmb();\n\n    dump_skb(skb, DUMP_SKB_LEN, (char *)__func__, ndev, ndev, 1);\n\n    if ( (ifx_ptm_dbg_enable & DBG_ENABLE_MASK_MAC_SWAP) ) {\n        skb_swap(skb);\n    }\n\n    g_ptm_priv_data.itf[ndev].stats.tx_packets++;\n    g_ptm_priv_data.itf[ndev].stats.tx_bytes += reg_desc.datalen;\n\n    netif_trans_update(dev);\n    mailbox_signal(ndev, 1);\n\n    adsl_led_flash();\n\n    return NETDEV_TX_OK;\n\nPTM_HARD_START_XMIT_FAIL:\n    dev_kfree_skb_any(skb);\n    g_ptm_priv_data.itf[ndev].stats.tx_dropped++;\n    return NETDEV_TX_OK;\n}\n\nstatic int ptm_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)\n{\n    int ndev;\n\n    for ( ndev = 0; ndev < ARRAY_SIZE(g_net_dev) && g_net_dev[ndev] != dev; ndev++ );\n    ASSERT(ndev >= 0 && ndev < ARRAY_SIZE(g_net_dev), \"ndev = %d (wrong value)\", ndev);\n\n    switch ( cmd )\n    {\n    case IFX_PTM_MIB_CW_GET:\n        ((PTM_CW_IF_ENTRY_T *)ifr->ifr_data)->ifRxNoIdleCodewords   = WAN_MIB_TABLE[ndev].wrx_nonidle_cw;\n        ((PTM_CW_IF_ENTRY_T *)ifr->ifr_data)->ifRxIdleCodewords     = WAN_MIB_TABLE[ndev].wrx_idle_cw;\n        ((PTM_CW_IF_ENTRY_T *)ifr->ifr_data)->ifRxCodingViolation   = WAN_MIB_TABLE[ndev].wrx_err_cw;\n        ((PTM_CW_IF_ENTRY_T *)ifr->ifr_data)->ifTxNoIdleCodewords   = 0;\n        ((PTM_CW_IF_ENTRY_T *)ifr->ifr_data)->ifTxIdleCodewords     = 0;\n        break;\n    case IFX_PTM_MIB_FRAME_GET:\n        ((PTM_FRAME_MIB_T *)ifr->ifr_data)->RxCorrect   = WAN_MIB_TABLE[ndev].wrx_correct_pdu;\n        ((PTM_FRAME_MIB_T *)ifr->ifr_data)->TC_CrcError = WAN_MIB_TABLE[ndev].wrx_tccrc_err_pdu;\n        ((PTM_FRAME_MIB_T *)ifr->ifr_data)->RxDropped   = WAN_MIB_TABLE[ndev].wrx_nodesc_drop_pdu + WAN_MIB_TABLE[ndev].wrx_len_violation_drop_pdu;\n        ((PTM_FRAME_MIB_T *)ifr->ifr_data)->TxSend      = WAN_MIB_TABLE[ndev].wtx_total_pdu;\n        break;\n    case IFX_PTM_CFG_GET:\n        ((IFX_PTM_CFG_T *)ifr->ifr_data)->RxEthCrcPresent = CFG_ETH_EFMTC_CRC->rx_eth_crc_present;\n        ((IFX_PTM_CFG_T *)ifr->ifr_data)->RxEthCrcCheck   = CFG_ETH_EFMTC_CRC->rx_eth_crc_check;\n        ((IFX_PTM_CFG_T *)ifr->ifr_data)->RxTcCrcCheck    = CFG_ETH_EFMTC_CRC->rx_tc_crc_check;\n        ((IFX_PTM_CFG_T *)ifr->ifr_data)->RxTcCrcLen      = CFG_ETH_EFMTC_CRC->rx_tc_crc_len;\n        ((IFX_PTM_CFG_T *)ifr->ifr_data)->TxEthCrcGen     = CFG_ETH_EFMTC_CRC->tx_eth_crc_gen;\n        ((IFX_PTM_CFG_T *)ifr->ifr_data)->TxTcCrcGen      = CFG_ETH_EFMTC_CRC->tx_tc_crc_gen;\n        ((IFX_PTM_CFG_T *)ifr->ifr_data)->TxTcCrcLen      = CFG_ETH_EFMTC_CRC->tx_tc_crc_len;\n        break;\n    case IFX_PTM_CFG_SET:\n        CFG_ETH_EFMTC_CRC->rx_eth_crc_present   = ((IFX_PTM_CFG_T *)ifr->ifr_data)->RxEthCrcPresent ? 1 : 0;\n        CFG_ETH_EFMTC_CRC->rx_eth_crc_check     = ((IFX_PTM_CFG_T *)ifr->ifr_data)->RxEthCrcCheck ? 1 : 0;\n        if ( ((IFX_PTM_CFG_T *)ifr->ifr_data)->RxTcCrcCheck && (((IFX_PTM_CFG_T *)ifr->ifr_data)->RxTcCrcLen == 16 || ((IFX_PTM_CFG_T *)ifr->ifr_data)->RxTcCrcLen == 32) )\n        {\n            CFG_ETH_EFMTC_CRC->rx_tc_crc_check  = 1;\n            CFG_ETH_EFMTC_CRC->rx_tc_crc_len    = ((IFX_PTM_CFG_T *)ifr->ifr_data)->RxTcCrcLen;\n        }\n        else\n        {\n            CFG_ETH_EFMTC_CRC->rx_tc_crc_check  = 0;\n            CFG_ETH_EFMTC_CRC->rx_tc_crc_len    = 0;\n        }\n        CFG_ETH_EFMTC_CRC->tx_eth_crc_gen       = ((IFX_PTM_CFG_T *)ifr->ifr_data)->TxEthCrcGen ? 1 : 0;\n        if ( ((IFX_PTM_CFG_T *)ifr->ifr_data)->TxTcCrcGen && (((IFX_PTM_CFG_T *)ifr->ifr_data)->TxTcCrcLen == 16 || ((IFX_PTM_CFG_T *)ifr->ifr_data)->TxTcCrcLen == 32) )\n        {\n            CFG_ETH_EFMTC_CRC->tx_tc_crc_gen    = 1;\n            CFG_ETH_EFMTC_CRC->tx_tc_crc_len    = ((IFX_PTM_CFG_T *)ifr->ifr_data)->TxTcCrcLen;\n        }\n        else\n        {\n            CFG_ETH_EFMTC_CRC->tx_tc_crc_gen    = 0;\n            CFG_ETH_EFMTC_CRC->tx_tc_crc_len    = 0;\n        }\n        break;\n    default:\n        return -EOPNOTSUPP;\n    }\n\n    return 0;\n}\n\n#if LINUX_VERSION_CODE < KERNEL_VERSION(5,6,0)\nstatic void ptm_tx_timeout(struct net_device *dev)\n#else\nstatic void ptm_tx_timeout(struct net_device *dev, unsigned int txqueue)\n#endif\n{\n    int ndev;\n\n    for ( ndev = 0; ndev < ARRAY_SIZE(g_net_dev) && g_net_dev[ndev] != dev; ndev++ );\n    ASSERT(ndev >= 0 && ndev < ARRAY_SIZE(g_net_dev), \"ndev = %d (wrong value)\", ndev);\n\n    /*  disable TX irq, release skb when sending new packet */\n    IFX_REG_W32_MASK(1 << (ndev + 16), 0, MBOX_IGU1_IER);\n\n    /*  wake up TX queue    */\n    netif_wake_queue(dev);\n\n    return;\n}\n\nstatic INLINE void adsl_led_flash(void)\n{\n}\n\nstatic INLINE struct sk_buff* alloc_skb_rx(void)\n{\n    struct sk_buff *skb;\n\n    /*  allocate memroy including trailer and padding   */\n    skb = dev_alloc_skb(rx_max_packet_size + RX_HEAD_MAC_ADDR_ALIGNMENT + DATA_BUFFER_ALIGNMENT);\n    if ( skb != NULL ) {\n        /*  must be burst length alignment and reserve two more bytes for MAC address alignment  */\n        if ( ((unsigned int)skb->data & (DATA_BUFFER_ALIGNMENT - 1)) != 0 )\n            skb_reserve(skb, ~((unsigned int)skb->data + (DATA_BUFFER_ALIGNMENT - 1)) & (DATA_BUFFER_ALIGNMENT - 1));\n        /*  pub skb in reserved area \"skb->data - 4\"    */\n        *((struct sk_buff **)skb->data - 1) = skb;\n        wmb();\n        /*  write back and invalidate cache    */\n        dma_cache_wback_inv((unsigned long)skb->data - sizeof(skb), sizeof(skb));\n        /*  invalidate cache    */\n        dma_cache_inv((unsigned long)skb->data, (unsigned int)skb->end - (unsigned int)skb->data);\n    }\n\n    return skb;\n}\n\n#if 0\nstatic INLINE struct sk_buff* alloc_skb_tx(unsigned int size)\n{\n    struct sk_buff *skb;\n\n    /*  allocate memory including padding   */\n    size = (size + DATA_BUFFER_ALIGNMENT - 1) & ~(DATA_BUFFER_ALIGNMENT - 1);\n    skb = dev_alloc_skb(size + DATA_BUFFER_ALIGNMENT);\n    /*  must be burst length alignment  */\n    if ( skb != NULL )\n        skb_reserve(skb, ~((unsigned int)skb->data + (DATA_BUFFER_ALIGNMENT - 1)) & (DATA_BUFFER_ALIGNMENT - 1));\n    return skb;\n}\n#endif\n\nstatic INLINE struct sk_buff *get_skb_rx_pointer(unsigned int dataptr)\n{\n    unsigned int skb_dataptr;\n    struct sk_buff *skb;\n\n    skb_dataptr = ((dataptr - 1) << 2) | KSEG1;\n    skb = *(struct sk_buff **)skb_dataptr;\n\n    ASSERT((unsigned int)skb >= KSEG0, \"invalid skb - skb = %#08x, dataptr = %#08x\", (unsigned int)skb, dataptr);\n    ASSERT(((unsigned int)skb->data | KSEG1) == ((dataptr << 2) | KSEG1), \"invalid skb - skb = %#08x, skb->data = %#08x, dataptr = %#08x\", (unsigned int)skb, (unsigned int)skb->data, dataptr);\n\n    return skb;\n}\n\nstatic INLINE int get_tx_desc(unsigned int itf, unsigned int *f_full)\n{\n    int desc_base = -1;\n    struct ptm_itf *p_itf = &g_ptm_priv_data.itf[itf];\n\n    //  assume TX is serial operation\n    //  no protection provided\n\n    *f_full = 1;\n\n    if ( p_itf->tx_desc[p_itf->tx_desc_pos].own == 0 ) {\n        desc_base = p_itf->tx_desc_pos;\n        if ( ++(p_itf->tx_desc_pos) == dma_tx_descriptor_length )\n            p_itf->tx_desc_pos = 0;\n        if ( p_itf->tx_desc[p_itf->tx_desc_pos].own == 0 )\n            *f_full = 0;\n    }\n\n    return desc_base;\n}\n\nstatic INLINE int mailbox_rx_irq_handler(unsigned int ch)   //  return: < 0 - descriptor not available, 0 - received one packet\n{\n    unsigned int ndev = ch;\n    struct sk_buff *skb;\n    struct sk_buff *new_skb;\n    volatile struct rx_descriptor *desc;\n    struct rx_descriptor reg_desc;\n    int netif_rx_ret;\n\n    desc = &g_ptm_priv_data.itf[ndev].rx_desc[g_ptm_priv_data.itf[ndev].rx_desc_pos];\n    if ( desc->own || !desc->c )    //  if PP32 hold descriptor or descriptor not completed\n        return -EAGAIN;\n    if ( ++g_ptm_priv_data.itf[ndev].rx_desc_pos == dma_rx_descriptor_length )\n        g_ptm_priv_data.itf[ndev].rx_desc_pos = 0;\n\n    reg_desc = *desc;\n    skb = get_skb_rx_pointer(reg_desc.dataptr);\n\n    if ( !reg_desc.err ) {\n        new_skb = alloc_skb_rx();\n        if ( new_skb != NULL ) {\n            skb_reserve(skb, reg_desc.byteoff);\n            skb_put(skb, reg_desc.datalen);\n\n            dump_skb(skb, DUMP_SKB_LEN, (char *)__func__, ndev, ndev, 0);\n\n            //  parse protocol header\n            skb->dev = g_net_dev[ndev];\n            skb->protocol = eth_type_trans(skb, skb->dev);\n\n            netif_rx_ret = netif_receive_skb(skb);\n\n            if ( netif_rx_ret != NET_RX_DROP ) {\n                g_ptm_priv_data.itf[ndev].stats.rx_packets++;\n                g_ptm_priv_data.itf[ndev].stats.rx_bytes += reg_desc.datalen;\n            }\n\n            reg_desc.dataptr = ((unsigned int)new_skb->data >> 2) & 0x0FFFFFFF;\n            reg_desc.byteoff = RX_HEAD_MAC_ADDR_ALIGNMENT;\n        }\n    }\n    else\n        reg_desc.err = 0;\n\n    reg_desc.datalen = rx_max_packet_size;\n    reg_desc.own     = 1;\n    reg_desc.c       = 0;\n\n    //  update descriptor\n    *desc = reg_desc;\n    wmb();\n\n    mailbox_signal(ndev, 0);\n\n    adsl_led_flash();\n\n    return 0;\n}\n\nstatic irqreturn_t mailbox_irq_handler(int irq, void *dev_id)\n{\n    unsigned int isr;\n    int i;\n\n    isr = IFX_REG_R32(MBOX_IGU1_ISR);\n    IFX_REG_W32(isr, MBOX_IGU1_ISRC);\n    isr &= IFX_REG_R32(MBOX_IGU1_IER);\n\n    while ( (i = __fls(isr)) >= 0 ) {\n        isr ^= 1 << i;\n\n        if ( i >= 16 ) {\n            //  TX\n            IFX_REG_W32_MASK(1 << i, 0, MBOX_IGU1_IER);\n            i -= 16;\n            if ( i < MAX_ITF_NUMBER )\n                netif_wake_queue(g_net_dev[i]);\n        }\n        else {\n            //  RX\n#ifdef CONFIG_IFX_PTM_RX_INTERRUPT\n            while ( WRX_DMA_CHANNEL_CONFIG(i)->vlddes > 0 )\n                mailbox_rx_irq_handler(i);\n#else\n            IFX_REG_W32_MASK(1 << i, 0, MBOX_IGU1_IER);\n            napi_schedule(&g_ptm_priv_data.itf[i].napi);\n#endif\n        }\n    }\n\n    return IRQ_HANDLED;\n}\n\nstatic INLINE void mailbox_signal(unsigned int itf, int is_tx)\n{\n    int count = 1000;\n\n    if ( is_tx ) {\n        while ( MBOX_IGU3_ISR_ISR(itf + 16) && count > 0 )\n            count--;\n        IFX_REG_W32(MBOX_IGU3_ISRS_SET(itf + 16), MBOX_IGU3_ISRS);\n    }\n    else {\n        while ( MBOX_IGU3_ISR_ISR(itf) && count > 0 )\n            count--;\n        IFX_REG_W32(MBOX_IGU3_ISRS_SET(itf), MBOX_IGU3_ISRS);\n    }\n\n    ASSERT(count != 0, \"MBOX_IGU3_ISR = 0x%08x\", IFX_REG_R32(MBOX_IGU3_ISR));\n}\n\n#ifdef CONFIG_IFX_PTM_RX_TASKLET\nstatic void do_ptm_tasklet(unsigned long arg)\n{\n    unsigned int work_to_do = 25;\n    unsigned int work_done = 0;\n\n    ASSERT(arg >= 0 && arg < ARRAY_SIZE(g_net_dev), \"arg = %lu (wrong value)\", arg);\n\n    while ( work_done < work_to_do && WRX_DMA_CHANNEL_CONFIG(arg)->vlddes > 0 ) {\n        if ( mailbox_rx_irq_handler(arg) < 0 )\n            break;\n\n        work_done++;\n    }\n\n    //  interface down\n    if ( !netif_running(g_net_dev[arg]) )\n        return;\n\n    //  no more traffic\n    if ( WRX_DMA_CHANNEL_CONFIG(arg)->vlddes == 0 ) {\n        //  clear interrupt\n        IFX_REG_W32_MASK(0, 1 << arg, MBOX_IGU1_ISRC);\n        //  double check\n        if ( WRX_DMA_CHANNEL_CONFIG(arg)->vlddes == 0 ) {\n            IFX_REG_W32_MASK(0, 1 << arg, MBOX_IGU1_IER);\n            return;\n        }\n    }\n\n    //  next round\n    tasklet_schedule(&g_ptm_tasklet[arg]);\n}\n#endif\n\n#if defined(DEBUG_DUMP_SKB) && DEBUG_DUMP_SKB\nstatic void dump_skb(struct sk_buff *skb, u32 len, char *title, int port, int ch, int is_tx)\n{\n    int i;\n\n    if ( !(ifx_ptm_dbg_enable & (is_tx ? DBG_ENABLE_MASK_DUMP_SKB_TX : DBG_ENABLE_MASK_DUMP_SKB_RX)) )\n        return;\n\n    if ( skb->len < len )\n        len = skb->len;\n\n    if ( len > rx_max_packet_size ) {\n        printk(\"too big data length: skb = %08x, skb->data = %08x, skb->len = %d\\n\", (u32)skb, (u32)skb->data, skb->len);\n        return;\n    }\n\n    if ( ch >= 0 )\n        printk(\"%s (port %d, ch %d)\\n\", title, port, ch);\n    else\n        printk(\"%s\\n\", title);\n    printk(\"  skb->data = %08X, skb->tail = %08X, skb->len = %d\\n\", (u32)skb->data, (u32)skb->tail, (int)skb->len);\n    for ( i = 1; i <= len; i++ ) {\n        if ( i % 16 == 1 )\n            printk(\"  %4d:\", i - 1);\n        printk(\" %02X\", (int)(*((char*)skb->data + i - 1) & 0xFF));\n        if ( i % 16 == 0 )\n            printk(\"\\n\");\n    }\n    if ( (i - 1) % 16 != 0 )\n        printk(\"\\n\");\n}\n#endif\n\n#if defined(ENABLE_DBG_PROC) && ENABLE_DBG_PROC\nstatic void skb_swap(struct sk_buff *skb)\n{\n    unsigned char tmp[8];\n    unsigned char *p = skb->data;\n\n    if ( !(p[0] & 0x01) ) { //  bypass broadcast/multicast\n        //  swap MAC\n        memcpy(tmp, p, 6);\n        memcpy(p, p + 6, 6);\n        memcpy(p + 6, tmp, 6);\n        p += 12;\n\n        //  bypass VLAN\n        while ( p[0] == 0x81 && p[1] == 0x00 )\n            p += 4;\n\n        //  IP\n        if ( p[0] == 0x08 && p[1] == 0x00 ) {\n            p += 14;\n            memcpy(tmp, p, 4);\n            memcpy(p, p + 4, 4);\n            memcpy(p + 4, tmp, 4);\n            p += 8;\n        }\n\n        dma_cache_wback((unsigned long)skb->data, (unsigned long)p - (unsigned long)skb->data);\n    }\n}\n#endif\n\nstatic INLINE void proc_file_create(void)\n{\n#if defined(ENABLE_DBG_PROC) && ENABLE_DBG_PROC\n    struct proc_dir_entry *res;\n\n    g_ptm_dir = proc_mkdir(\"driver/ifx_ptm\", NULL);\n\n    create_proc_read_entry(\"version\",\n                            0,\n                            g_ptm_dir,\n                            proc_read_version,\n                            NULL);\n\n    res = create_proc_entry(\"wanmib\",\n                            0,\n                            g_ptm_dir);\n    if ( res != NULL ) {\n        res->read_proc  = proc_read_wanmib;\n        res->write_proc = proc_write_wanmib;\n    }\n\n#if defined(ENABLE_FW_PROC) && ENABLE_FW_PROC\n    create_proc_read_entry(\"genconf\",\n                            0,\n                            g_ptm_dir,\n                            proc_read_genconf,\n                            NULL);\n\n  #ifdef CONFIG_AR9\n    create_proc_read_entry(\"regs\",\n                            0,\n                            g_ptm_dir,\n                            ifx_ptm_proc_read_regs,\n                            NULL);\n  #endif\n#endif\n\n    res = create_proc_entry(\"dbg\",\n                            0,\n                            g_ptm_dir);\n    if ( res != NULL ) {\n        res->read_proc  = proc_read_dbg;\n        res->write_proc = proc_write_dbg;\n    }\n#endif\n}\n\nstatic INLINE void proc_file_delete(void)\n{\n#if defined(ENABLE_DBG_PROC) && ENABLE_DBG_PROC\n    remove_proc_entry(\"dbg\", g_ptm_dir);\n#endif\n\n#if defined(ENABLE_FW_PROC) && ENABLE_FW_PROC\n  #ifdef CONFIG_AR9\n    remove_proc_entry(\"regs\", g_ptm_dir);\n  #endif\n\n    remove_proc_entry(\"genconf\", g_ptm_dir);\n#endif\n\n    remove_proc_entry(\"wanmib\", g_ptm_dir);\n\n    remove_proc_entry(\"version\", g_ptm_dir);\n\n    remove_proc_entry(\"driver/ifx_ptm\", NULL);\n}\n\nstatic int proc_read_version(char *buf, char **start, off_t offset, int count, int *eof, void *data)\n{\n    int len = 0;\n\n    len += ifx_ptm_version(buf + len);\n\n    if ( offset >= len ) {\n        *start = buf;\n        *eof = 1;\n        return 0;\n    }\n    *start = buf + offset;\n    if ( (len -= offset) > count )\n        return count;\n    *eof = 1;\n    return len;\n}\n\nstatic int proc_read_wanmib(char *page, char **start, off_t off, int count, int *eof, void *data)\n{\n    int len = 0;\n    int i;\n    char *title[] = {\n        \"dsl0\\n\",\n        \"dslfast0\\n\"\n    };\n\n    for ( i = 0; i < ARRAY_SIZE(title); i++ ) {\n        len += sprintf(page + off + len, title[i]);\n        len += sprintf(page + off + len, \"  wrx_correct_pdu            = %d\\n\", WAN_MIB_TABLE[i].wrx_correct_pdu);\n        len += sprintf(page + off + len, \"  wrx_correct_pdu_bytes      = %d\\n\", WAN_MIB_TABLE[i].wrx_correct_pdu_bytes);\n        len += sprintf(page + off + len, \"  wrx_tccrc_err_pdu          = %d\\n\", WAN_MIB_TABLE[i].wrx_tccrc_err_pdu);\n        len += sprintf(page + off + len, \"  wrx_tccrc_err_pdu_bytes    = %d\\n\", WAN_MIB_TABLE[i].wrx_tccrc_err_pdu_bytes);\n        len += sprintf(page + off + len, \"  wrx_ethcrc_err_pdu         = %d\\n\", WAN_MIB_TABLE[i].wrx_ethcrc_err_pdu);\n        len += sprintf(page + off + len, \"  wrx_ethcrc_err_pdu_bytes   = %d\\n\", WAN_MIB_TABLE[i].wrx_ethcrc_err_pdu_bytes);\n        len += sprintf(page + off + len, \"  wrx_nodesc_drop_pdu        = %d\\n\", WAN_MIB_TABLE[i].wrx_nodesc_drop_pdu);\n        len += sprintf(page + off + len, \"  wrx_len_violation_drop_pdu = %d\\n\", WAN_MIB_TABLE[i].wrx_len_violation_drop_pdu);\n        len += sprintf(page + off + len, \"  wrx_idle_bytes             = %d\\n\", WAN_MIB_TABLE[i].wrx_idle_bytes);\n        len += sprintf(page + off + len, \"  wrx_nonidle_cw             = %d\\n\", WAN_MIB_TABLE[i].wrx_nonidle_cw);\n        len += sprintf(page + off + len, \"  wrx_idle_cw                = %d\\n\", WAN_MIB_TABLE[i].wrx_idle_cw);\n        len += sprintf(page + off + len, \"  wrx_err_cw                 = %d\\n\", WAN_MIB_TABLE[i].wrx_err_cw);\n        len += sprintf(page + off + len, \"  wtx_total_pdu              = %d\\n\", WAN_MIB_TABLE[i].wtx_total_pdu);\n        len += sprintf(page + off + len, \"  wtx_total_bytes            = %d\\n\", WAN_MIB_TABLE[i].wtx_total_bytes);\n    }\n\n    *eof = 1;\n\n    return len;\n}\n\nstatic int proc_write_wanmib(struct file *file, const char *buf, unsigned long count, void *data)\n{\n    char str[2048];\n    char *p;\n    int len, rlen;\n\n    int i;\n\n    len = count < sizeof(str) ? count : sizeof(str) - 1;\n    rlen = len - copy_from_user(str, buf, len);\n    while ( rlen && str[rlen - 1] <= ' ' )\n        rlen--;\n    str[rlen] = 0;\n    for ( p = str; *p && *p <= ' '; p++, rlen-- );\n    if ( !*p )\n        return count;\n\n    if ( stricmp(p, \"clear\") == 0 || stricmp(p, \"clean\") == 0 ) {\n        for ( i = 0; i < 2; i++ )\n            memset((void*)&WAN_MIB_TABLE[i], 0, sizeof(WAN_MIB_TABLE[i]));\n    }\n\n    return count;\n}\n\n#if defined(ENABLE_FW_PROC) && ENABLE_FW_PROC\n\nstatic int proc_read_genconf(char *page, char **start, off_t off, int count, int *eof, void *data)\n{\n    int len = 0;\n    int len_max = off + count;\n    char *pstr;\n    char str[2048];\n    int llen = 0;\n    int i;\n    unsigned long bit;\n\n    pstr = *start = page;\n\n    __sync();\n\n    llen += sprintf(str + llen, \"CFG_WAN_WRDES_DELAY (0x%08X): %d\\n\", (unsigned int)CFG_WAN_WRDES_DELAY, IFX_REG_R32(CFG_WAN_WRDES_DELAY));\n    llen += sprintf(str + llen, \"CFG_WRX_DMACH_ON    (0x%08X):\", (unsigned int)CFG_WRX_DMACH_ON);\n    for ( i = 0, bit = 1; i < MAX_RX_DMA_CHANNEL_NUMBER; i++, bit <<= 1 )\n        llen += sprintf(str + llen, \" %d - %s\", i, (IFX_REG_R32(CFG_WRX_DMACH_ON) & bit) ? \"on \" : \"off\");\n    llen += sprintf(str + llen, \"\\n\");\n    llen += sprintf(str + llen, \"CFG_WTX_DMACH_ON    (0x%08X):\", (unsigned int)CFG_WTX_DMACH_ON);\n    for ( i = 0, bit = 1; i < MAX_TX_DMA_CHANNEL_NUMBER; i++, bit <<= 1 )\n        llen += sprintf(str + llen, \" %d - %s\", i, (IFX_REG_R32(CFG_WTX_DMACH_ON) & bit) ? \"on \" : \"off\");\n    llen += sprintf(str + llen, \"\\n\");\n    llen += sprintf(str + llen, \"CFG_WRX_LOOK_BITTH  (0x%08X): %d\\n\", (unsigned int)CFG_WRX_LOOK_BITTH, IFX_REG_R32(CFG_WRX_LOOK_BITTH));\n    llen += sprintf(str + llen, \"CFG_ETH_EFMTC_CRC   (0x%08X): rx_tc_crc_len    - %2d,  rx_tc_crc_check    - %s\\n\", (unsigned int)CFG_ETH_EFMTC_CRC, CFG_ETH_EFMTC_CRC->rx_tc_crc_len, CFG_ETH_EFMTC_CRC->rx_tc_crc_check ? \" on\" : \"off\");\n    llen += sprintf(str + llen, \"                                  rx_eth_crc_check - %s, rx_eth_crc_present - %s\\n\",   CFG_ETH_EFMTC_CRC->rx_eth_crc_check ? \" on\" : \"off\", CFG_ETH_EFMTC_CRC->rx_eth_crc_present ? \" on\" : \"off\");\n    llen += sprintf(str + llen, \"                                  tx_tc_crc_len    - %2d,  tx_tc_crc_gen      - %s\\n\", CFG_ETH_EFMTC_CRC->tx_tc_crc_len, CFG_ETH_EFMTC_CRC->tx_tc_crc_gen ? \" on\" : \"off\");\n    llen += sprintf(str + llen, \"                                  tx_eth_crc_gen   - %s\\n\", CFG_ETH_EFMTC_CRC->tx_eth_crc_gen ? \" on\" : \"off\");\n\n    llen += sprintf(str + llen, \"RX Port:\\n\");\n    for ( i = 0; i < MAX_RX_DMA_CHANNEL_NUMBER; i++ )\n        llen += sprintf(str + llen, \"  %d (0x%08X). mfs - %5d, dmach - %d, local_state - %d, partner_state - %d\\n\", i, (unsigned int)WRX_PORT_CONFIG(i), WRX_PORT_CONFIG(i)->mfs, WRX_PORT_CONFIG(i)->dmach, WRX_PORT_CONFIG(i)->local_state, WRX_PORT_CONFIG(i)->partner_state);\n    llen += sprintf(str + llen, \"RX DMA Channel:\\n\");\n    for ( i = 0; i < MAX_RX_DMA_CHANNEL_NUMBER; i++ )\n        llen += sprintf(str + llen, \"  %d (0x%08X). desba - 0x%08X (0x%08X), deslen - %d, vlddes - %d\\n\", i, (unsigned int)WRX_DMA_CHANNEL_CONFIG(i), WRX_DMA_CHANNEL_CONFIG(i)->desba, ((unsigned int)WRX_DMA_CHANNEL_CONFIG(i)->desba << 2) | KSEG1, WRX_DMA_CHANNEL_CONFIG(i)->deslen, WRX_DMA_CHANNEL_CONFIG(i)->vlddes);\n\n    llen += sprintf(str + llen, \"TX Port:\\n\");\n    for ( i = 0; i < MAX_TX_DMA_CHANNEL_NUMBER; i++ )\n        llen += sprintf(str + llen, \"  %d (0x%08X). tx_cwth2 - %d, tx_cwth1 - %d\\n\", i, (unsigned int)WTX_PORT_CONFIG(i), WTX_PORT_CONFIG(i)->tx_cwth2, WTX_PORT_CONFIG(i)->tx_cwth1);\n    llen += sprintf(str + llen, \"TX DMA Channel:\\n\");\n    for ( i = 0; i < MAX_TX_DMA_CHANNEL_NUMBER; i++ )\n        llen += sprintf(str + llen, \"  %d (0x%08X). desba - 0x%08X (0x%08X), deslen - %d, vlddes - %d\\n\", i, (unsigned int)WTX_DMA_CHANNEL_CONFIG(i), WTX_DMA_CHANNEL_CONFIG(i)->desba, ((unsigned int)WTX_DMA_CHANNEL_CONFIG(i)->desba << 2) | KSEG1, WTX_DMA_CHANNEL_CONFIG(i)->deslen, WTX_DMA_CHANNEL_CONFIG(i)->vlddes);\n\n    if ( len <= off && len + llen > off )\n    {\n        memcpy(pstr, str + off - len, len + llen - off);\n        pstr += len + llen - off;\n    }\n    else if ( len > off )\n    {\n        memcpy(pstr, str, llen);\n        pstr += llen;\n    }\n    len += llen;\n    if ( len >= len_max )\n        goto PROC_READ_GENCONF_OVERRUN_END;\n\n    *eof = 1;\n\n    return len - off;\n\nPROC_READ_GENCONF_OVERRUN_END:\n    return len - llen - off;\n}\n\n#endif  //  defined(ENABLE_FW_PROC) && ENABLE_FW_PROC\n\n#if defined(ENABLE_DBG_PROC) && ENABLE_DBG_PROC\n\nstatic int proc_read_dbg(char *page, char **start, off_t off, int count, int *eof, void *data)\n{\n    int len = 0;\n\n    len += sprintf(page + off + len, \"error print      - %s\\n\", (ifx_ptm_dbg_enable & DBG_ENABLE_MASK_ERR)              ? \"enabled\" : \"disabled\");\n    len += sprintf(page + off + len, \"debug print      - %s\\n\", (ifx_ptm_dbg_enable & DBG_ENABLE_MASK_DEBUG_PRINT)      ? \"enabled\" : \"disabled\");\n    len += sprintf(page + off + len, \"assert           - %s\\n\", (ifx_ptm_dbg_enable & DBG_ENABLE_MASK_ASSERT)           ? \"enabled\" : \"disabled\");\n    len += sprintf(page + off + len, \"dump rx skb      - %s\\n\", (ifx_ptm_dbg_enable & DBG_ENABLE_MASK_DUMP_SKB_RX)      ? \"enabled\" : \"disabled\");\n    len += sprintf(page + off + len, \"dump tx skb      - %s\\n\", (ifx_ptm_dbg_enable & DBG_ENABLE_MASK_DUMP_SKB_TX)      ? \"enabled\" : \"disabled\");\n    len += sprintf(page + off + len, \"mac swap         - %s\\n\", (ifx_ptm_dbg_enable & DBG_ENABLE_MASK_MAC_SWAP)         ? \"enabled\" : \"disabled\");\n\n    *eof = 1;\n\n    return len;\n}\n\nstatic int proc_write_dbg(struct file *file, const char *buf, unsigned long count, void *data)\n{\n    static const char *dbg_enable_mask_str[] = {\n        \" error print\",\n        \" err\",\n        \" debug print\",\n        \" dbg\",\n        \" assert\",\n        \" assert\",\n        \" dump rx skb\",\n        \" rx\",\n        \" dump tx skb\",\n        \" tx\",\n        \" dump init\",\n        \" init\",\n        \" dump qos\",\n        \" qos\",\n        \" mac swap\",\n        \" swap\",\n        \" all\"\n    };\n    static const int dbg_enable_mask_str_len[] = {\n        12, 4,\n        12, 4,\n        7,  7,\n        12, 3,\n        12, 3,\n        10, 5,\n        9,  4,\n        9,  5,\n        4\n    };\n    unsigned int dbg_enable_mask[] = {\n        DBG_ENABLE_MASK_ERR,\n        DBG_ENABLE_MASK_DEBUG_PRINT,\n        DBG_ENABLE_MASK_ASSERT,\n        DBG_ENABLE_MASK_DUMP_SKB_RX,\n        DBG_ENABLE_MASK_DUMP_SKB_TX,\n        DBG_ENABLE_MASK_DUMP_INIT,\n        DBG_ENABLE_MASK_DUMP_QOS,\n        DBG_ENABLE_MASK_MAC_SWAP,\n        DBG_ENABLE_MASK_ALL\n    };\n\n    char str[2048];\n    char *p;\n\n    int len, rlen;\n\n    int f_enable = 0;\n    int i;\n\n    len = count < sizeof(str) ? count : sizeof(str) - 1;\n    rlen = len - copy_from_user(str, buf, len);\n    while ( rlen && str[rlen - 1] <= ' ' )\n        rlen--;\n    str[rlen] = 0;\n    for ( p = str; *p && *p <= ' '; p++, rlen-- );\n    if ( !*p )\n        return 0;\n\n    //  debugging feature for enter/leave showtime\n    if ( strincmp(p, \"enter\", 5) == 0 && ifx_mei_atm_showtime_enter != NULL )\n        ifx_mei_atm_showtime_enter(NULL, NULL);\n    else if ( strincmp(p, \"leave\", 5) == 0 && ifx_mei_atm_showtime_exit != NULL )\n        ifx_mei_atm_showtime_exit();\n\n    if ( strincmp(p, \"enable\", 6) == 0 ) {\n        p += 6;\n        f_enable = 1;\n    }\n    else if ( strincmp(p, \"disable\", 7) == 0 ) {\n        p += 7;\n        f_enable = -1;\n    }\n    else if ( strincmp(p, \"help\", 4) == 0 || *p == '?' ) {\n        printk(\"echo <enable/disable> [err/dbg/assert/rx/tx/init/qos/swap/all] > /proc/driver/ifx_ptm/dbg\\n\");\n    }\n\n    if ( f_enable ) {\n        if ( *p == 0 ) {\n            if ( f_enable > 0 )\n                ifx_ptm_dbg_enable |= DBG_ENABLE_MASK_ALL & ~DBG_ENABLE_MASK_MAC_SWAP;\n            else\n                ifx_ptm_dbg_enable &= ~DBG_ENABLE_MASK_ALL | DBG_ENABLE_MASK_MAC_SWAP;\n        }\n        else {\n            do {\n                for ( i = 0; i < ARRAY_SIZE(dbg_enable_mask_str); i++ )\n                    if ( strincmp(p, dbg_enable_mask_str[i], dbg_enable_mask_str_len[i]) == 0 ) {\n                        if ( f_enable > 0 )\n                            ifx_ptm_dbg_enable |= dbg_enable_mask[i >> 1];\n                        else\n                            ifx_ptm_dbg_enable &= ~dbg_enable_mask[i >> 1];\n                        p += dbg_enable_mask_str_len[i];\n                        break;\n                    }\n            } while ( i < ARRAY_SIZE(dbg_enable_mask_str) );\n        }\n    }\n\n    return count;\n}\n\n#endif  //  defined(ENABLE_DBG_PROC) && ENABLE_DBG_PROC\n\nstatic INLINE int stricmp(const char *p1, const char *p2)\n{\n    int c1, c2;\n\n    while ( *p1 && *p2 )\n    {\n        c1 = *p1 >= 'A' && *p1 <= 'Z' ? *p1 + 'a' - 'A' : *p1;\n        c2 = *p2 >= 'A' && *p2 <= 'Z' ? *p2 + 'a' - 'A' : *p2;\n        if ( (c1 -= c2) )\n            return c1;\n        p1++;\n        p2++;\n    }\n\n    return *p1 - *p2;\n}\n\n#if defined(ENABLE_DBG_PROC) && ENABLE_DBG_PROC\nstatic INLINE int strincmp(const char *p1, const char *p2, int n)\n{\n    int c1 = 0, c2;\n\n    while ( n && *p1 && *p2 )\n    {\n        c1 = *p1 >= 'A' && *p1 <= 'Z' ? *p1 + 'a' - 'A' : *p1;\n        c2 = *p2 >= 'A' && *p2 <= 'Z' ? *p2 + 'a' - 'A' : *p2;\n        if ( (c1 -= c2) )\n            return c1;\n        p1++;\n        p2++;\n        n--;\n    }\n\n    return n ? *p1 - *p2 : c1;\n}\n#endif\n\nstatic INLINE int ifx_ptm_version(char *buf)\n{\n    int len = 0;\n    unsigned int major, minor;\n\n    ifx_ptm_get_fw_ver(&major, &minor);\n\n    len += sprintf(buf + len, \"PTM %d.%d.%d\", IFX_PTM_VER_MAJOR, IFX_PTM_VER_MID, IFX_PTM_VER_MINOR);\n    len += sprintf(buf + len, \"    PTM (E1) firmware version %d.%d\\n\", major, minor);\n\n    return len;\n}\n\nstatic INLINE void check_parameters(void)\n{\n    /*  There is a delay between PPE write descriptor and descriptor is       */\n    /*  really stored in memory. Host also has this delay when writing        */\n    /*  descriptor. So PPE will use this value to determine if the write      */\n    /*  operation makes effect.                                               */\n    if ( write_desc_delay < 0 )\n        write_desc_delay = 0;\n\n    /*  Because of the limitation of length field in descriptors, the packet  */\n    /*  size could not be larger than 64K minus overhead size.                */\n    if ( rx_max_packet_size < ETH_MIN_FRAME_LENGTH )\n        rx_max_packet_size = ETH_MIN_FRAME_LENGTH;\n    else if ( rx_max_packet_size > 65536 - 1 )\n        rx_max_packet_size = 65536 - 1;\n\n    if ( dma_rx_descriptor_length < 2 )\n        dma_rx_descriptor_length = 2;\n    if ( dma_tx_descriptor_length < 2 )\n        dma_tx_descriptor_length = 2;\n}\n\nstatic INLINE int init_priv_data(void)\n{\n    void *p;\n    int i;\n    struct rx_descriptor rx_desc = {0};\n    struct sk_buff *skb;\n    volatile struct rx_descriptor *p_rx_desc;\n    volatile struct tx_descriptor *p_tx_desc;\n    struct sk_buff **ppskb;\n\n    //  clear ptm private data structure\n    memset(&g_ptm_priv_data, 0, sizeof(g_ptm_priv_data));\n\n    //  allocate memory for RX descriptors\n    p = kzalloc(MAX_ITF_NUMBER * dma_rx_descriptor_length * sizeof(struct rx_descriptor) + DESC_ALIGNMENT, GFP_KERNEL);\n    if ( p == NULL )\n        return -1;\n    dma_cache_inv((unsigned long)p, MAX_ITF_NUMBER * dma_rx_descriptor_length * sizeof(struct rx_descriptor) + DESC_ALIGNMENT);\n    g_ptm_priv_data.rx_desc_base = p;\n    //p = (void *)((((unsigned int)p + DESC_ALIGNMENT - 1) & ~(DESC_ALIGNMENT - 1)) | KSEG1);\n\n    //  allocate memory for TX descriptors\n    p = kzalloc(MAX_ITF_NUMBER * dma_tx_descriptor_length * sizeof(struct tx_descriptor) + DESC_ALIGNMENT, GFP_KERNEL);\n    if ( p == NULL )\n        return -1;\n    dma_cache_inv((unsigned long)p, MAX_ITF_NUMBER * dma_tx_descriptor_length * sizeof(struct tx_descriptor) + DESC_ALIGNMENT);\n    g_ptm_priv_data.tx_desc_base = p;\n\n    //  allocate memroy for TX skb pointers\n    p = kzalloc(MAX_ITF_NUMBER * dma_tx_descriptor_length * sizeof(struct sk_buff *) + 4, GFP_KERNEL);\n    if ( p == NULL )\n        return -1;\n    dma_cache_wback_inv((unsigned long)p, MAX_ITF_NUMBER * dma_tx_descriptor_length * sizeof(struct sk_buff *) + 4);\n    g_ptm_priv_data.tx_skb_base = p;\n\n    p_rx_desc = (volatile struct rx_descriptor *)((((unsigned int)g_ptm_priv_data.rx_desc_base + DESC_ALIGNMENT - 1) & ~(DESC_ALIGNMENT - 1)) | KSEG1);\n    p_tx_desc = (volatile struct tx_descriptor *)((((unsigned int)g_ptm_priv_data.tx_desc_base + DESC_ALIGNMENT - 1) & ~(DESC_ALIGNMENT - 1)) | KSEG1);\n    ppskb = (struct sk_buff **)(((unsigned int)g_ptm_priv_data.tx_skb_base + 3) & ~3);\n    for ( i = 0; i < MAX_ITF_NUMBER; i++ ) {\n        g_ptm_priv_data.itf[i].rx_desc = &p_rx_desc[i * dma_rx_descriptor_length];\n        g_ptm_priv_data.itf[i].tx_desc = &p_tx_desc[i * dma_tx_descriptor_length];\n        g_ptm_priv_data.itf[i].tx_skb = &ppskb[i * dma_tx_descriptor_length];\n    }\n\n    rx_desc.own     = 1;\n    rx_desc.c       = 0;\n    rx_desc.sop     = 1;\n    rx_desc.eop     = 1;\n    rx_desc.byteoff = RX_HEAD_MAC_ADDR_ALIGNMENT;\n    rx_desc.id      = 0;\n    rx_desc.err     = 0;\n    rx_desc.datalen = rx_max_packet_size;\n    for ( i = 0; i < MAX_ITF_NUMBER * dma_rx_descriptor_length; i++ ) {\n        skb = alloc_skb_rx();\n        if ( skb == NULL )\n            return -1;\n        rx_desc.dataptr = ((unsigned int)skb->data >> 2) & 0x0FFFFFFF;\n        p_rx_desc[i] = rx_desc;\n    }\n\n    return 0;\n}\n\nstatic INLINE void clear_priv_data(void)\n{\n    int i, j;\n    struct sk_buff *skb;\n\n    for ( i = 0; i < MAX_ITF_NUMBER; i++ ) {\n        if ( g_ptm_priv_data.itf[i].tx_skb != NULL ) {\n            for ( j = 0; j < dma_tx_descriptor_length; j++ )\n                if ( g_ptm_priv_data.itf[i].tx_skb[j] != NULL )\n                    dev_kfree_skb_any(g_ptm_priv_data.itf[i].tx_skb[j]);\n        }\n        if ( g_ptm_priv_data.itf[i].rx_desc != NULL ) {\n            for ( j = 0; j < dma_rx_descriptor_length; j++ ) {\n                if ( g_ptm_priv_data.itf[i].rx_desc[j].sop || g_ptm_priv_data.itf[i].rx_desc[j].eop ) {    //  descriptor initialized\n                    skb = get_skb_rx_pointer(g_ptm_priv_data.itf[i].rx_desc[j].dataptr);\n                    dev_kfree_skb_any(skb);\n                }\n            }\n        }\n    }\n\n    if ( g_ptm_priv_data.rx_desc_base != NULL )\n        kfree(g_ptm_priv_data.rx_desc_base);\n\n    if ( g_ptm_priv_data.tx_desc_base != NULL )\n        kfree(g_ptm_priv_data.tx_desc_base);\n\n    if ( g_ptm_priv_data.tx_skb_base != NULL )\n        kfree(g_ptm_priv_data.tx_skb_base);\n}\n\nstatic INLINE void init_tables(void)\n{\n    int i;\n    volatile unsigned int *p;\n    struct wrx_dma_channel_config rx_config = {0};\n    struct wtx_dma_channel_config tx_config = {0};\n    struct wrx_port_cfg_status    rx_port_cfg = { 0 };\n    struct wtx_port_cfg           tx_port_cfg = { 0 };\n\n    /*\n     *  CDM Block 1\n     */\n    IFX_REG_W32(CDM_CFG_RAM1_SET(0x00) | CDM_CFG_RAM0_SET(0x00), CDM_CFG);  //  CDM block 1 must be data memory and mapped to 0x5000 (dword addr)\n    p = CDM_DATA_MEMORY(0, 0);                                              //  Clear CDM block 1\n    for ( i = 0; i < CDM_DATA_MEMORY_DWLEN; i++, p++ )\n        IFX_REG_W32(0, p);\n\n    /*\n     *  General Registers\n     */\n    IFX_REG_W32(write_desc_delay, CFG_WAN_WRDES_DELAY);\n    IFX_REG_W32((1 << MAX_RX_DMA_CHANNEL_NUMBER) - 1, CFG_WRX_DMACH_ON);\n    IFX_REG_W32((1 << MAX_TX_DMA_CHANNEL_NUMBER) - 1, CFG_WTX_DMACH_ON);\n\n    IFX_REG_W32(8, CFG_WRX_LOOK_BITTH); // WAN RX EFM-TC Looking Threshold\n\n    IFX_REG_W32(eth_efmtc_crc_cfg, CFG_ETH_EFMTC_CRC);\n\n    /*\n     *  WRX DMA Channel Configuration Table\n     */\n    rx_config.deslen = dma_rx_descriptor_length;\n    rx_port_cfg.mfs = ETH_MAX_FRAME_LENGTH;\n    rx_port_cfg.local_state = 0;     // looking for sync\n    rx_port_cfg.partner_state = 0;   // parter receiver is out of sync\n\n    for ( i = 0; i < MAX_RX_DMA_CHANNEL_NUMBER; i++ ) {\n        rx_config.desba = ((unsigned int)g_ptm_priv_data.itf[i].rx_desc >> 2) & 0x0FFFFFFF;\n        *WRX_DMA_CHANNEL_CONFIG(i) = rx_config;\n\n        rx_port_cfg.dmach = i;\n        *WRX_PORT_CONFIG(i) = rx_port_cfg;\n    }\n\n    /*\n     *  WTX DMA Channel Configuration Table\n     */\n    tx_config.deslen = dma_tx_descriptor_length;\n    tx_port_cfg.tx_cwth1 = 5;\n    tx_port_cfg.tx_cwth2 = 4;\n\n    for ( i = 0; i < MAX_TX_DMA_CHANNEL_NUMBER; i++ ) {\n        tx_config.desba = ((unsigned int)g_ptm_priv_data.itf[i].tx_desc >> 2) & 0x0FFFFFFF;\n        *WTX_DMA_CHANNEL_CONFIG(i) = tx_config;\n\n        *WTX_PORT_CONFIG(i) = tx_port_cfg;\n    }\n}\n\n\n\n/*\n * ####################################\n *           Global Function\n * ####################################\n */\n\nstatic int ptm_showtime_enter(struct port_cell_info *port_cell, void *xdata_addr)\n{\n    int i;\n\n    g_showtime = 1;\n\n    for ( i = 0; i < ARRAY_SIZE(g_net_dev); i++ )\n        netif_carrier_on(g_net_dev[i]);\n\n    printk(\"enter showtime\\n\");\n\n    return 0;\n}\n\nstatic int ptm_showtime_exit(void)\n{\n    int i;\n\n    if ( !g_showtime )\n        return -1;\n\n    for ( i = 0; i < ARRAY_SIZE(g_net_dev); i++ )\n        netif_carrier_off(g_net_dev[i]);\n\n    g_showtime = 0;\n\n    printk(\"leave showtime\\n\");\n\n    return 0;\n}\n\n\nstatic const struct of_device_id ltq_ptm_match[] = {\n#ifdef CONFIG_DANUBE\n       { .compatible = \"lantiq,ppe-danube\", .data = NULL },\n#elif defined CONFIG_AMAZON_SE\n       { .compatible = \"lantiq,ppe-ase\", .data = NULL },\n#elif defined CONFIG_AR9\n       { .compatible = \"lantiq,ppe-arx100\", .data = NULL },\n#elif defined CONFIG_VR9\n       { .compatible = \"lantiq,ppe-xrx200\", .data = NULL },\n#endif\n       {},\n};\nMODULE_DEVICE_TABLE(of, ltq_ptm_match);\n\n/*\n * ####################################\n *           Init/Cleanup API\n * ####################################\n */\n\n/*\n *  Description:\n *    Initialize global variables, PP32, comunication structures, register IRQ\n *    and register device.\n *  Input:\n *    none\n *  Output:\n *    0    --- successful\n *    else --- failure, usually it is negative value of error code\n */\nstatic int ltq_ptm_probe(struct platform_device *pdev)\n{\n    int ret;\n    struct port_cell_info port_cell = {0};\n    void *xdata_addr = NULL;\n    int i;\n    char ver_str[256];\n\n    check_parameters();\n\n    ret = init_priv_data();\n    if ( ret != 0 ) {\n        err(\"INIT_PRIV_DATA_FAIL\");\n        goto INIT_PRIV_DATA_FAIL;\n    }\n\n    ifx_ptm_init_chip(pdev);\n    init_tables();\n\n    for ( i = 0; i < ARRAY_SIZE(g_net_dev); i++ ) {\n        g_net_dev[i] = alloc_netdev(0, g_net_dev_name[i], NET_NAME_UNKNOWN, ether_setup);\n        if ( g_net_dev[i] == NULL )\n            goto ALLOC_NETDEV_FAIL;\n        ptm_setup(g_net_dev[i], i);\n    }\n\n    for ( i = 0; i < ARRAY_SIZE(g_net_dev); i++ ) {\n        ret = register_netdev(g_net_dev[i]);\n        if ( ret != 0 )\n            goto REGISTER_NETDEV_FAIL;\n    }\n\n    /*  register interrupt handler  */\n    ret = request_irq(PPE_MAILBOX_IGU1_INT, mailbox_irq_handler, 0, \"ptm_mailbox_isr\", &g_ptm_priv_data);\n    if ( ret ) {\n        if ( ret == -EBUSY ) {\n            err(\"IRQ may be occupied by other driver, please reconfig to disable it.\");\n        }\n        else {\n            err(\"request_irq fail\");\n        }\n        goto REQUEST_IRQ_PPE_MAILBOX_IGU1_INT_FAIL;\n    }\n    disable_irq(PPE_MAILBOX_IGU1_INT);\n\n    ret = ifx_pp32_start(0);\n    if ( ret ) {\n        err(\"ifx_pp32_start fail!\");\n        goto PP32_START_FAIL;\n    }\n    IFX_REG_W32(0, MBOX_IGU1_IER);\n    IFX_REG_W32(~0, MBOX_IGU1_ISRC);\n\n    enable_irq(PPE_MAILBOX_IGU1_INT);\n\n\n    proc_file_create();\n\n    port_cell.port_num = 1;\n    ifx_mei_atm_showtime_check(&g_showtime, &port_cell, &xdata_addr);\n    if ( g_showtime ) {\n\tptm_showtime_enter(&port_cell, &xdata_addr);\n    }\n\n    ifx_mei_atm_showtime_enter = ptm_showtime_enter;\n    ifx_mei_atm_showtime_exit  = ptm_showtime_exit;\n\n    ifx_ptm_version(ver_str);\n    printk(KERN_INFO \"%s\", ver_str);\n\n    printk(\"ifxmips_ptm: PTM init succeed\\n\");\n\n    return 0;\n\nPP32_START_FAIL:\n    free_irq(PPE_MAILBOX_IGU1_INT, &g_ptm_priv_data);\nREQUEST_IRQ_PPE_MAILBOX_IGU1_INT_FAIL:\n    i = ARRAY_SIZE(g_net_dev);\nREGISTER_NETDEV_FAIL:\n    while ( i-- )\n        unregister_netdev(g_net_dev[i]);\n    i = ARRAY_SIZE(g_net_dev);\nALLOC_NETDEV_FAIL:\n    while ( i-- ) {\n        free_netdev(g_net_dev[i]);\n        g_net_dev[i] = NULL;\n    }\nINIT_PRIV_DATA_FAIL:\n    clear_priv_data();\n    printk(\"ifxmips_ptm: PTM init failed\\n\");\n    return ret;\n}\n\n/*\n *  Description:\n *    Release memory, free IRQ, and deregister device.\n *  Input:\n *    none\n *  Output:\n *   none\n */\nstatic int ltq_ptm_remove(struct platform_device *pdev)\n{\n    int i;\n\n    ifx_mei_atm_showtime_enter = NULL;\n    ifx_mei_atm_showtime_exit  = NULL;\n\n    proc_file_delete();\n\n\n    ifx_pp32_stop(0);\n\n    free_irq(PPE_MAILBOX_IGU1_INT, &g_ptm_priv_data);\n\n    for ( i = 0; i < ARRAY_SIZE(g_net_dev); i++ )\n        unregister_netdev(g_net_dev[i]);\n\n    for ( i = 0; i < ARRAY_SIZE(g_net_dev); i++ ) {\n        free_netdev(g_net_dev[i]);\n        g_net_dev[i] = NULL;\n    }\n\n    ifx_ptm_uninit_chip();\n\n    clear_priv_data();\n\n    return 0;\n}\n\nstatic struct platform_driver ltq_ptm_driver = {\n       .probe = ltq_ptm_probe,\n       .remove = ltq_ptm_remove,\n       .driver = {\n               .name = \"ptm\",\n               .owner = THIS_MODULE,\n               .of_match_table = ltq_ptm_match,\n       },\n};\n\nmodule_platform_driver(ltq_ptm_driver);\n\nMODULE_LICENSE(\"GPL\");\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-ptm/src/ifxmips_ptm_adsl.h",
    "content": "/******************************************************************************\n**\n** FILE NAME    : ifxmips_ptm_adsl.h\n** PROJECT      : UEIP\n** MODULES      : PTM\n**\n** DATE         : 7 Jul 2009\n** AUTHOR       : Xu Liang\n** DESCRIPTION  : PTM driver header file (core functions for Danube/Amazon-SE/\n**                AR9)\n** COPYRIGHT    :       Copyright (c) 2006\n**                      Infineon Technologies AG\n**                      Am Campeon 1-12, 85579 Neubiberg, Germany\n**\n**    This program is free software; you can redistribute it and/or modify\n**    it under the terms of the GNU General Public License as published by\n**    the Free Software Foundation; either version 2 of the License, or\n**    (at your option) any later version.\n**\n** HISTORY\n** $Date        $Author         $Comment\n** 17 JUN 2009  Xu Liang        Init Version\n*******************************************************************************/\n\n#ifndef IFXMIPS_PTM_ADSL_H\n#define IFXMIPS_PTM_ADSL_H\n\n\n\n#include <linux/version.h>\n#include <linux/netdevice.h>\n#include <lantiq_ptm.h>\n#include \"ifxmips_ptm_common.h\"\n#include \"ifxmips_ptm_ppe_common.h\"\n#include \"ifxmips_ptm_fw_regs_adsl.h\"\n\n#define CONFIG_IFXMIPS_DSL_CPE_MEI\n#define INT_NUM_IM2_IRL24\t(INT_NUM_IM2_IRL0 + 24)\n\n#define IFX_REG_W32(_v, _r)               __raw_writel((_v), (volatile unsigned int *)(_r))\n#define IFX_REG_R32(_r)                    __raw_readl((volatile unsigned int *)(_r))\n#define IFX_REG_W32_MASK(_clr, _set, _r)   IFX_REG_W32((IFX_REG_R32((_r)) & ~(_clr)) | (_set), (_r))\n#define SET_BITS(x, msb, lsb, value)    (((x) & ~(((1 << ((msb) + 1)) - 1) ^ ((1 << (lsb)) - 1))) | (((value) & ((1 << (1 + (msb) - (lsb))) - 1)) << (lsb)))\n\n\n\n\n/*\n * ####################################\n *              Definition\n * ####################################\n */\n\n/*\n *  Constant Definition\n */\n#define ETH_WATCHDOG_TIMEOUT            (2 * HZ)\n\n/*\n *  DMA RX/TX Channel Parameters\n */\n#define MAX_ITF_NUMBER                  2\n#define MAX_RX_DMA_CHANNEL_NUMBER       MAX_ITF_NUMBER\n#define MAX_TX_DMA_CHANNEL_NUMBER       MAX_ITF_NUMBER\n#define DATA_BUFFER_ALIGNMENT           EMA_ALIGNMENT\n#define DESC_ALIGNMENT                  8\n\n/*\n *  Ethernet Frame Definitions\n */\n#define ETH_MAC_HEADER_LENGTH           14\n#define ETH_CRC_LENGTH                  4\n#define ETH_MIN_FRAME_LENGTH            64\n#define ETH_MAX_FRAME_LENGTH            (1518 + 4 * 2)\n\n/*\n *  RX Frame Definitions\n */\n#define RX_HEAD_MAC_ADDR_ALIGNMENT      2\n#define RX_TAIL_CRC_LENGTH              0   //  PTM firmware does not have ethernet frame CRC\n                                            //  The len in descriptor doesn't include ETH_CRC\n                                            //  because ETH_CRC may not present in some configuration\n\n\n\n/*\n * ####################################\n *              Data Type\n * ####################################\n */\n\nstruct ptm_itf {\n    volatile struct rx_descriptor  *rx_desc;\n    unsigned int                    rx_desc_pos;\n\n    volatile struct tx_descriptor  *tx_desc;\n    unsigned int                    tx_desc_pos;\n    struct sk_buff                **tx_skb;\n\n    struct net_device_stats         stats;\n\n    struct napi_struct              napi;\n};\n\nstruct ptm_priv_data {\n    struct ptm_itf                  itf[MAX_ITF_NUMBER];\n\n    void                           *rx_desc_base;\n    void                           *tx_desc_base;\n    void                           *tx_skb_base;\n};\n\n\n\n/*\n * ####################################\n *             Declaration\n * ####################################\n */\n\nextern unsigned int ifx_ptm_dbg_enable;\n\nextern void ifx_ptm_get_fw_ver(unsigned int *major, unsigned int *minor);\n\nextern void ifx_ptm_init_chip(struct platform_device *pdev);\nextern void ifx_ptm_uninit_chip(void);\n\nextern int ifx_pp32_start(int pp32);\nextern void ifx_pp32_stop(int pp32);\n\nextern void ifx_reset_ppe(void);\n\nextern int ifx_ptm_proc_read_regs(char *page, char **start, off_t off, int count, int *eof, void *data);\n\n\n\n#endif  //  IFXMIPS_PTM_ADSL_H\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-ptm/src/ifxmips_ptm_amazon_se.c",
    "content": "/******************************************************************************\n**\n** FILE NAME    : ifxmips_ptm_amazon_se.c\n** PROJECT      : UEIP\n** MODULES      : PTM\n**\n** DATE         : 7 Jul 2009\n** AUTHOR       : Xu Liang\n** DESCRIPTION  : PTM driver common source file (core functions)\n** COPYRIGHT    :       Copyright (c) 2006\n**                      Infineon Technologies AG\n**                      Am Campeon 1-12, 85579 Neubiberg, Germany\n**\n**    This program is free software; you can redistribute it and/or modify\n**    it under the terms of the GNU General Public License as published by\n**    the Free Software Foundation; either version 2 of the License, or\n**    (at your option) any later version.\n**\n** HISTORY\n** $Date        $Author         $Comment\n** 07 JUL 2009  Xu Liang        Init Version\n*******************************************************************************/\n\n\n\n/*\n * ####################################\n *              Head File\n * ####################################\n */\n\n/*\n *  Common Head File\n */\n#include <linux/kernel.h>\n#include <linux/module.h>\n#include <linux/version.h>\n#include <linux/types.h>\n#include <linux/errno.h>\n#include <linux/proc_fs.h>\n#include <linux/init.h>\n#include <linux/ioctl.h>\n#include <linux/platform_device.h>\n#include <linux/reset.h>\n#include <asm/delay.h>\n\n/*\n *  Chip Specific Head File\n */\n#include <asm/ifx/ifx_types.h>\n#include <asm/ifx/ifx_regs.h>\n#include <asm/ifx/common_routines.h>\n#include <asm/ifx/ifx_pmu.h>\n#include <asm/ifx/ifx_rcu.h>\n#include \"ifxmips_ptm_adsl.h\"\n#include \"ifxmips_ptm_fw_amazon_se.h\"\n\n\n\n/*\n * ####################################\n *              Definition\n * ####################################\n */\n\n/*\n *  EMA Settings\n */\n#define EMA_CMD_BUF_LEN      0x0040\n#define EMA_CMD_BASE_ADDR    (0x00001580 << 2)\n#define EMA_DATA_BUF_LEN     0x0100\n#define EMA_DATA_BASE_ADDR   (0x00000B00 << 2)\n#define EMA_WRITE_BURST      0x2\n#define EMA_READ_BURST       0x2\n\n\n\n/*\n * ####################################\n *             Declaration\n * ####################################\n */\n\n/*\n *  Hardware Init/Uninit Functions\n */\nstatic inline void init_pmu(void);\nstatic inline void uninit_pmu(void);\nstatic inline void reset_ppe(struct platform_device *pdev);\nstatic inline void init_ema(void);\nstatic inline void init_mailbox(void);\nstatic inline void init_atm_tc(void);\nstatic inline void clear_share_buffer(void);\n\n\n\n/*\n * ####################################\n *            Local Variable\n * ####################################\n */\n\n\n\n/*\n * ####################################\n *            Local Function\n * ####################################\n */\n\nstatic inline void init_pmu(void)\n{\n    //*(unsigned long *)0xBF10201C &= ~((1 << 15) | (1 << 13) | (1 << 9));\n    //PPE_TOP_PMU_SETUP(IFX_PMU_ENABLE);\n    PPE_SLL01_PMU_SETUP(IFX_PMU_ENABLE);\n    PPE_TC_PMU_SETUP(IFX_PMU_ENABLE);\n    PPE_EMA_PMU_SETUP(IFX_PMU_ENABLE);\n    //PPE_QSB_PMU_SETUP(IFX_PMU_ENABLE);\n    PPE_TPE_PMU_SETUP(IFX_PMU_ENABLE);\n    DSL_DFE_PMU_SETUP(IFX_PMU_ENABLE);\n}\n\nstatic inline void uninit_pmu(void)\n{\n    PPE_SLL01_PMU_SETUP(IFX_PMU_DISABLE);\n    PPE_TC_PMU_SETUP(IFX_PMU_DISABLE);\n    PPE_EMA_PMU_SETUP(IFX_PMU_DISABLE);\n    //PPE_QSB_PMU_SETUP(IFX_PMU_DISABLE);\n    PPE_TPE_PMU_SETUP(IFX_PMU_DISABLE);\n    DSL_DFE_PMU_SETUP(IFX_PMU_DISABLE);\n    //PPE_TOP_PMU_SETUP(IFX_PMU_DISABLE);\n}\n\nstatic inline void reset_ppe(struct platform_device *pdev)\n{\n#ifdef MODULE\n    unsigned int etop_cfg;\n    unsigned int etop_mdio_cfg;\n    unsigned int etop_ig_plen_ctrl;\n    unsigned int enet_mac_cfg;\n\n    etop_cfg            = *IFX_PP32_ETOP_CFG;\n    etop_mdio_cfg       = *IFX_PP32_ETOP_MDIO_CFG;\n    etop_ig_plen_ctrl   = *IFX_PP32_ETOP_IG_PLEN_CTRL;\n    enet_mac_cfg        = *IFX_PP32_ENET_MAC_CFG;\n\n    *IFX_PP32_ETOP_CFG  = (*IFX_PP32_ETOP_CFG & ~0x03C0) | 0x0001;\n\n    //  reset PPE\n    ifx_rcu_rst(IFX_RCU_DOMAIN_PPE, IFX_RCU_MODULE_PTM);\n\n    *IFX_PP32_ETOP_MDIO_CFG     = etop_mdio_cfg;\n    *IFX_PP32_ETOP_IG_PLEN_CTRL = etop_ig_plen_ctrl;\n    *IFX_PP32_ENET_MAC_CFG      = enet_mac_cfg;\n    *IFX_PP32_ETOP_CFG          = etop_cfg;\n#endif\n}\n\nstatic inline void init_ema(void)\n{\n    //  Configure share buffer master selection\n    *SB_MST_PRI0 = 1;\n    *SB_MST_PRI1 = 1;\n\n    //  EMA Settings\n    IFX_REG_W32((EMA_CMD_BUF_LEN << 16) | (EMA_CMD_BASE_ADDR >> 2), EMA_CMDCFG);\n    IFX_REG_W32((EMA_DATA_BUF_LEN << 16) | (EMA_DATA_BASE_ADDR >> 2), EMA_DATACFG);\n    IFX_REG_W32(0x000000FF, EMA_IER);\n    IFX_REG_W32(EMA_READ_BURST | (EMA_WRITE_BURST << 2), EMA_CFG);\n}\n\nstatic inline void init_mailbox(void)\n{\n    IFX_REG_W32(0xFFFFFFFF, MBOX_IGU1_ISRC);\n    IFX_REG_W32(0x00000000, MBOX_IGU1_IER);\n    IFX_REG_W32(0xFFFFFFFF, MBOX_IGU3_ISRC);\n    IFX_REG_W32(0x00000000, MBOX_IGU3_IER);\n}\n\nstatic inline void init_atm_tc(void)\n{\n    IFX_REG_W32(0x0F00,     DREG_AT_CTRL);\n    IFX_REG_W32(0x3C00,     DREG_AR_CTRL);\n    IFX_REG_W32(0x0,        DREG_AT_IDLE0);\n    IFX_REG_W32(0x0,        DREG_AT_IDLE1);\n    IFX_REG_W32(0x0,        DREG_AR_IDLE0);\n    IFX_REG_W32(0x0,        DREG_AR_IDLE1);\n    IFX_REG_W32(0x0,        RFBI_CFG);\n    IFX_REG_W32(0x0200,     SFSM_DBA0);\n    IFX_REG_W32(0x0800,     SFSM_DBA1);\n    IFX_REG_W32(0x0321,     SFSM_CBA0);\n    IFX_REG_W32(0x0921,     SFSM_CBA1);\n    IFX_REG_W32(0x14011,    SFSM_CFG0);\n    IFX_REG_W32(0x14011,    SFSM_CFG1);\n    IFX_REG_W32(0x0332,     FFSM_DBA0);\n    IFX_REG_W32(0x0932,     FFSM_DBA1);\n    IFX_REG_W32(0x3000C,    FFSM_CFG0);\n    IFX_REG_W32(0x3000C,    FFSM_CFG1);\n    IFX_REG_W32(0xF0D10000, FFSM_IDLE_HEAD_BC0);\n    IFX_REG_W32(0xF0D10000, FFSM_IDLE_HEAD_BC1);\n}\n\nstatic inline void clear_share_buffer(void)\n{\n    volatile u32 *p = SB_RAM0_ADDR(0);\n    unsigned int i;\n\n    for ( i = 0; i < SB_RAM0_DWLEN + SB_RAM1_DWLEN; i++ )\n        IFX_REG_W32(0, p++);\n}\n\n/*\n *  Description:\n *    Download PPE firmware binary code.\n *  Input:\n *    src       --- u32 *, binary code buffer\n *    dword_len --- unsigned int, binary code length in DWORD (32-bit)\n *  Output:\n *    int       --- 0:    Success\n *                  else:           Error Code\n */\nstatic inline int pp32_download_code(u32 *code_src, unsigned int code_dword_len, u32 *data_src, unsigned int data_dword_len)\n{\n    volatile u32 *dest;\n\n    if ( code_src == 0 || ((unsigned long)code_src & 0x03) != 0\n        || data_src == 0 || ((unsigned long)data_src & 0x03) != 0 )\n        return -1;\n\n    if ( code_dword_len <= CDM_CODE_MEMORYn_DWLEN(0) )\n        IFX_REG_W32(0x00, CDM_CFG);\n    else\n        IFX_REG_W32(0x04, CDM_CFG);\n\n    /*  copy code   */\n    dest = CDM_CODE_MEMORY(0, 0);\n    while ( code_dword_len-- > 0 )\n        IFX_REG_W32(*code_src++, dest++);\n\n    /*  copy data   */\n    dest = CDM_DATA_MEMORY(0, 0);\n    while ( data_dword_len-- > 0 )\n        IFX_REG_W32(*data_src++, dest++);\n\n    return 0;\n}\n\n\n\n/*\n * ####################################\n *           Global Function\n * ####################################\n */\n\nextern void ifx_ptm_get_fw_ver(unsigned int *major, unsigned int *minor)\n{\n    ASSERT(major != NULL, \"pointer is NULL\");\n    ASSERT(minor != NULL, \"pointer is NULL\");\n\n    *major = FW_VER_ID->major;\n    *minor = FW_VER_ID->minor;\n}\n\nvoid ifx_ptm_init_chip(struct platform_device *pdev)\n{\n    init_pmu();\n\n    reset_ppe(pdev);\n\n    init_ema();\n\n    init_mailbox();\n\n    init_atm_tc();\n\n    clear_share_buffer();\n}\n\nvoid ifx_ptm_uninit_chip(void)\n{\n    uninit_pmu();\n}\n\n/*\n *  Description:\n *    Initialize and start up PP32.\n *  Input:\n *    none\n *  Output:\n *    int  --- 0: Success\n *             else:        Error Code\n */\nint ifx_pp32_start(int pp32)\n{\n    int ret;\n\n    /*  download firmware   */\n    ret = pp32_download_code(firmware_binary_code, sizeof(firmware_binary_code) / sizeof(*firmware_binary_code), firmware_binary_data, sizeof(firmware_binary_data) / sizeof(*firmware_binary_data));\n    if ( ret != 0 )\n        return ret;\n\n    /*  run PP32    */\n    IFX_REG_W32(DBG_CTRL_RESTART, PP32_DBG_CTRL(pp32));\n\n    /*  idle for a while to let PP32 init itself    */\n    udelay(10);\n\n    return 0;\n}\n\n/*\n *  Description:\n *    Halt PP32.\n *  Input:\n *    none\n *  Output:\n *    none\n */\nvoid ifx_pp32_stop(int pp32)\n{\n    /*  halt PP32   */\n    IFX_REG_W32(DBG_CTRL_STOP, PP32_DBG_CTRL(pp32));\n}\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-ptm/src/ifxmips_ptm_ar9.c",
    "content": "/******************************************************************************\n**\n** FILE NAME    : ifxmips_ptm_ar9.c\n** PROJECT      : UEIP\n** MODULES      : PTM\n**\n** DATE         : 7 Jul 2009\n** AUTHOR       : Xu Liang\n** DESCRIPTION  : PTM driver common source file (core functions)\n** COPYRIGHT    :       Copyright (c) 2006\n**                      Infineon Technologies AG\n**                      Am Campeon 1-12, 85579 Neubiberg, Germany\n**\n**    This program is free software; you can redistribute it and/or modify\n**    it under the terms of the GNU General Public License as published by\n**    the Free Software Foundation; either version 2 of the License, or\n**    (at your option) any later version.\n**\n** HISTORY\n** $Date        $Author         $Comment\n** 07 JUL 2009  Xu Liang        Init Version\n*******************************************************************************/\n\n\n\n/*\n * ####################################\n *              Head File\n * ####################################\n */\n\n/*\n *  Common Head File\n */\n#include <linux/kernel.h>\n#include <linux/module.h>\n#include <linux/version.h>\n#include <linux/types.h>\n#include <linux/errno.h>\n#include <linux/proc_fs.h>\n#include <linux/init.h>\n#include <linux/ioctl.h>\n#include <linux/platform_device.h>\n#include <linux/reset.h>\n#include <asm/delay.h>\n\n/*\n *  Chip Specific Head File\n */\n#include \"ifxmips_ptm_adsl.h\"\n#include \"ifxmips_ptm_fw_ar9.h\"\n\n#include <lantiq_soc.h>\n\n\n/*\n * ####################################\n *              Definition\n * ####################################\n */\n\n/*\n *  EMA Settings\n */\n#define EMA_CMD_BUF_LEN      0x0040\n#define EMA_CMD_BASE_ADDR    (0x00001B80 << 2)\n#define EMA_DATA_BUF_LEN     0x0100\n#define EMA_DATA_BASE_ADDR   (0x00001C00 << 2)\n#define EMA_WRITE_BURST      0x2\n#define EMA_READ_BURST       0x2\n\n\n\n/*\n * ####################################\n *             Declaration\n * ####################################\n */\n\n/*\n *  Hardware Init/Uninit Functions\n */\nstatic inline void init_pmu(void);\nstatic inline void uninit_pmu(void);\nstatic inline void reset_ppe(struct platform_device *pdev);\nstatic inline void init_ema(void);\nstatic inline void init_mailbox(void);\nstatic inline void init_atm_tc(void);\nstatic inline void clear_share_buffer(void);\n\n\n\n/*\n * ####################################\n *            Local Variable\n * ####################################\n */\n\n\n\n/*\n * ####################################\n *            Local Function\n * ####################################\n */\n\n#define IFX_PMU_MODULE_PPE_SLL01  BIT(19)\n#define IFX_PMU_MODULE_PPE_TC     BIT(21)\n#define IFX_PMU_MODULE_PPE_EMA    BIT(22)\n#define IFX_PMU_MODULE_PPE_QSB    BIT(18)\n#define IFX_PMU_MODULE_TPE       BIT(13)\n#define IFX_PMU_MODULE_DSL_DFE    BIT(9)\n\n\nstatic inline void init_pmu(void)\n{\n\tltq_pmu_enable(IFX_PMU_MODULE_PPE_SLL01 |\n\t\tIFX_PMU_MODULE_PPE_TC |\n\t\tIFX_PMU_MODULE_PPE_EMA |\n\t\tIFX_PMU_MODULE_TPE |\n\t\tIFX_PMU_MODULE_DSL_DFE);\n\n}\n\nstatic inline void uninit_pmu(void)\n{\n\tltq_pmu_disable(IFX_PMU_MODULE_PPE_SLL01 |\n\t\tIFX_PMU_MODULE_PPE_TC |\n\t\tIFX_PMU_MODULE_PPE_EMA |\n\t\tIFX_PMU_MODULE_TPE |\n\t\tIFX_PMU_MODULE_DSL_DFE);\n\n}\n\nstatic inline void reset_ppe(struct platform_device *pdev)\n{\n#ifdef MODULE\n    //  reset PPE\n//    ifx_rcu_rst(IFX_RCU_DOMAIN_PPE, IFX_RCU_MODULE_PTM);\n#endif\n}\n\nstatic inline void init_ema(void)\n{\n    //  Configure share buffer master selection\n    IFX_REG_W32(1, SB_MST_PRI0);\n    IFX_REG_W32(1, SB_MST_PRI1);\n\n    //  EMA Settings\n    IFX_REG_W32((EMA_CMD_BUF_LEN << 16) | (EMA_CMD_BASE_ADDR >> 2), EMA_CMDCFG);\n    IFX_REG_W32((EMA_DATA_BUF_LEN << 16) | (EMA_DATA_BASE_ADDR >> 2), EMA_DATACFG);\n    IFX_REG_W32(0x000000FF, EMA_IER);\n    IFX_REG_W32(EMA_READ_BURST | (EMA_WRITE_BURST << 2), EMA_CFG);\n}\n\nstatic inline void init_mailbox(void)\n{\n    IFX_REG_W32(0xFFFFFFFF, MBOX_IGU1_ISRC);\n    IFX_REG_W32(0x00000000, MBOX_IGU1_IER);\n    IFX_REG_W32(0xFFFFFFFF, MBOX_IGU3_ISRC);\n    IFX_REG_W32(0x00000000, MBOX_IGU3_IER);\n}\n\nstatic inline void init_atm_tc(void)\n{\n    IFX_REG_W32(0x0,        RFBI_CFG);\n    IFX_REG_W32(0x1800,     SFSM_DBA0);\n    IFX_REG_W32(0x1921,     SFSM_DBA1);\n    IFX_REG_W32(0x1A42,     SFSM_CBA0);\n    IFX_REG_W32(0x1A53,     SFSM_CBA1);\n    IFX_REG_W32(0x14011,    SFSM_CFG0);\n    IFX_REG_W32(0x14011,    SFSM_CFG1);\n    IFX_REG_W32(0x1000,     FFSM_DBA0);\n    IFX_REG_W32(0x1700,     FFSM_DBA1);\n    IFX_REG_W32(0x3000C,    FFSM_CFG0);\n    IFX_REG_W32(0x3000C,    FFSM_CFG1);\n    IFX_REG_W32(0xF0D10000, FFSM_IDLE_HEAD_BC0);\n    IFX_REG_W32(0xF0D10000, FFSM_IDLE_HEAD_BC1);\n\n    /*\n     *  0. Backup port2 value to temp\n     *  1. Disable CPU port2 in switch (link and learning)\n     *  2. wait for a while\n     *  3. Configure DM register and counter\n     *  4. restore temp to CPU port2 in switch\n     *  This code will cause network to stop working if there are heavy\n     *  traffic during bootup. This part should be moved to switch and use\n     *  the same code as ATM\n     */\n    {\n        int i;\n        u32 temp;\n\n        temp = IFX_REG_R32(SW_P2_CTL);\n\n        IFX_REG_W32(0x40020000, SW_P2_CTL);\n        for (i = 0; i < 200; i++)\n            udelay(2000);\n\n        IFX_REG_W32(0x00007028, DM_RXCFG);\n        IFX_REG_W32(0x00007028, DS_RXCFG);\n\n        IFX_REG_W32(0x00001100, DM_RXDB);\n        IFX_REG_W32(0x00001100, DS_RXDB);\n\n        IFX_REG_W32(0x00001600, DM_RXCB);\n        IFX_REG_W32(0x00001600, DS_RXCB);\n\n        /*\n         * For dynamic, must reset these counters,\n         * For once initialization, don't need to reset these counters\n         */\n        IFX_REG_W32(0x0, DM_RXPGCNT);\n        IFX_REG_W32(0x0, DS_RXPGCNT);\n        IFX_REG_W32(0x0, DM_RXPKTCNT);\n\n        IFX_REG_W32_MASK(0, 0x80000000, DM_RXCFG);\n        IFX_REG_W32_MASK(0, 0x8000, DS_RXCFG);\n\n        udelay(2000);\n        IFX_REG_W32(temp, SW_P2_CTL);\n        udelay(2000);\n    }\n}\n\nstatic inline void clear_share_buffer(void)\n{\n    volatile u32 *p = SB_RAM0_ADDR(0);\n    unsigned int i;\n\n    for ( i = 0; i < SB_RAM0_DWLEN + SB_RAM1_DWLEN + SB_RAM2_DWLEN + SB_RAM3_DWLEN + SB_RAM4_DWLEN; i++ )\n        IFX_REG_W32(0, p++);\n}\n\n/*\n *  Description:\n *    Download PPE firmware binary code.\n *  Input:\n *    src       --- u32 *, binary code buffer\n *    dword_len --- unsigned int, binary code length in DWORD (32-bit)\n *  Output:\n *    int       --- 0:    Success\n *                  else:           Error Code\n */\nstatic inline int pp32_download_code(u32 *code_src, unsigned int code_dword_len, u32 *data_src, unsigned int data_dword_len)\n{\n    volatile u32 *dest;\n\n    if ( code_src == 0 || ((unsigned long)code_src & 0x03) != 0\n        || data_src == 0 || ((unsigned long)data_src & 0x03) != 0 )\n        return -1;\n\n    if ( code_dword_len <= CDM_CODE_MEMORYn_DWLEN(0) )\n        IFX_REG_W32(0x00, CDM_CFG);\n    else\n        IFX_REG_W32(0x04, CDM_CFG);\n\n    /*  copy code   */\n    dest = CDM_CODE_MEMORY(0, 0);\n    while ( code_dword_len-- > 0 )\n        IFX_REG_W32(*code_src++, dest++);\n\n    /*  copy data   */\n    dest = CDM_DATA_MEMORY(0, 0);\n    while ( data_dword_len-- > 0 )\n        IFX_REG_W32(*data_src++, dest++);\n\n    return 0;\n}\n\n\n\n/*\n * ####################################\n *           Global Function\n * ####################################\n */\n\nvoid ifx_ptm_get_fw_ver(unsigned int *major, unsigned int *minor)\n{\n    ASSERT(major != NULL, \"pointer is NULL\");\n    ASSERT(minor != NULL, \"pointer is NULL\");\n\n    *major = FW_VER_ID->major;\n    *minor = FW_VER_ID->minor;\n}\n\nvoid ifx_ptm_init_chip(struct platform_device *pdev)\n{\n    init_pmu();\n\n    reset_ppe(pdev);\n\n    init_ema();\n\n    init_mailbox();\n\n    init_atm_tc();\n\n    clear_share_buffer();\n}\n\nvoid ifx_ptm_uninit_chip(void)\n{\n    uninit_pmu();\n}\n\n/*\n *  Description:\n *    Initialize and start up PP32.\n *  Input:\n *    none\n *  Output:\n *    int  --- 0: Success\n *             else:        Error Code\n */\nint ifx_pp32_start(int pp32)\n{\n    int ret;\n\n    /*  download firmware   */\n    ret = pp32_download_code(firmware_binary_code, sizeof(firmware_binary_code) / sizeof(*firmware_binary_code), firmware_binary_data, sizeof(firmware_binary_data) / sizeof(*firmware_binary_data));\n    if ( ret != 0 )\n        return ret;\n\n    /*  run PP32    */\n    IFX_REG_W32(DBG_CTRL_RESTART, PP32_DBG_CTRL(0));\n\n    /*  idle for a while to let PP32 init itself    */\n    udelay(10);\n\n    return 0;\n}\n\n/*\n *  Description:\n *    Halt PP32.\n *  Input:\n *    none\n *  Output:\n *    none\n */\nvoid ifx_pp32_stop(int pp32)\n{\n    /*  halt PP32   */\n    IFX_REG_W32(DBG_CTRL_STOP, PP32_DBG_CTRL(0));\n}\n\nint ifx_ptm_proc_read_regs(char *page, char **start, off_t off, int count, int *eof, void *data)\n{\n    int len = 0;\n\n    len += sprintf(page + off + len, \"EMA:\\n\");\n    len += sprintf(page + off + len, \"  SB_MST_PRI0 - 0x%08X, SB_MST_PRI1 - 0x%08X\\n\", IFX_REG_R32(SB_MST_PRI0), IFX_REG_R32(SB_MST_PRI1));\n    len += sprintf(page + off + len, \"  EMA_CMDCFG  - 0x%08X, EMA_DATACFG - 0x%08X\\n\", IFX_REG_R32(EMA_CMDCFG), IFX_REG_R32(EMA_DATACFG));\n    len += sprintf(page + off + len, \"  EMA_IER     - 0x%08X, EMA_CFG     - 0x%08X\\n\", IFX_REG_R32(EMA_IER), IFX_REG_R32(EMA_CFG));\n\n    len += sprintf(page + off + len, \"Mailbox:\\n\");\n    len += sprintf(page + off + len, \"  MBOX_IGU1_IER - 0x%08X, MBOX_IGU1_ISR - 0x%08X\\n\", IFX_REG_R32(MBOX_IGU1_IER), IFX_REG_R32(MBOX_IGU1_ISR));\n    len += sprintf(page + off + len, \"  MBOX_IGU3_IER - 0x%08X, MBOX_IGU3_ISR - 0x%08X\\n\", IFX_REG_R32(MBOX_IGU3_IER), IFX_REG_R32(MBOX_IGU3_ISR));\n\n    len += sprintf(page + off + len, \"TC:\\n\");\n    len += sprintf(page + off + len, \"  RFBI_CFG  - 0x%08X\\n\", IFX_REG_R32(RFBI_CFG));\n    len += sprintf(page + off + len, \"  SFSM_DBA0 - 0x%08X, SFSM_CBA0 - 0x%08X, SFSM_CFG0 - 0x%08X\\n\", IFX_REG_R32(SFSM_DBA0), IFX_REG_R32(SFSM_CBA0), IFX_REG_R32(SFSM_CFG0));\n    len += sprintf(page + off + len, \"  SFSM_DBA1 - 0x%08X, SFSM_CBA1 - 0x%08X, SFSM_CFG1 - 0x%08X\\n\", IFX_REG_R32(SFSM_DBA1), IFX_REG_R32(SFSM_CBA1), IFX_REG_R32(SFSM_CFG1));\n    len += sprintf(page + off + len, \"  FFSM_DBA0 - 0x%08X, FFSM_CFG0 - 0x%08X, IDLE_HEAD - 0x%08X\\n\", IFX_REG_R32(FFSM_DBA0), IFX_REG_R32(FFSM_CFG0), IFX_REG_R32(FFSM_IDLE_HEAD_BC0));\n    len += sprintf(page + off + len, \"  FFSM_DBA1 - 0x%08X, FFSM_CFG1 - 0x%08X, IDLE_HEAD - 0x%08X\\n\", IFX_REG_R32(FFSM_DBA1), IFX_REG_R32(FFSM_CFG1), IFX_REG_R32(FFSM_IDLE_HEAD_BC1));\n\n    len += sprintf(page + off + len, \"DPlus:\\n\");\n    len += sprintf(page + off + len, \"  DM_RXDB    - 0x%08X, DM_RXCB     - 0x%08X, DM_RXCFG - 0x%08X\\n\", IFX_REG_R32(DM_RXDB), IFX_REG_R32(DM_RXCB), IFX_REG_R32(DM_RXCFG));\n    len += sprintf(page + off + len, \"  DM_RXPGCNT - 0x%08X, DM_RXPKTCNT - 0x%08X\\n\", IFX_REG_R32(DM_RXPGCNT), IFX_REG_R32(DM_RXPKTCNT));\n    len += sprintf(page + off + len, \"  DS_RXDB    - 0x%08X, DS_RXCB     - 0x%08X, DS_RXCFG - 0x%08X\\n\", IFX_REG_R32(DS_RXDB), IFX_REG_R32(DS_RXCB), IFX_REG_R32(DS_RXCFG));\n    len += sprintf(page + off + len, \"  DS_RXPGCNT - 0x%08X\\n\", IFX_REG_R32(DS_RXPGCNT));\n\n    *eof = 1;\n\n    return len;\n}\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-ptm/src/ifxmips_ptm_common.h",
    "content": "/******************************************************************************\n**\n** FILE NAME    : ifxmips_ptm_common.h\n** PROJECT      : UEIP\n** MODULES      : PTM\n**\n** DATE         : 7 Jul 2009\n** AUTHOR       : Xu Liang\n** DESCRIPTION  : PTM driver header file (common definitions)\n** COPYRIGHT    :       Copyright (c) 2006\n**                      Infineon Technologies AG\n**                      Am Campeon 1-12, 85579 Neubiberg, Germany\n**\n**    This program is free software; you can redistribute it and/or modify\n**    it under the terms of the GNU General Public License as published by\n**    the Free Software Foundation; either version 2 of the License, or\n**    (at your option) any later version.\n**\n** HISTORY\n** $Date        $Author         $Comment\n** 17 JUN 2009  Xu Liang        Init Version\n*******************************************************************************/\n\n#ifndef IFXMIPS_PTM_COMMON_H\n#define IFXMIPS_PTM_COMMON_H\n\n\n\n/*\n * ####################################\n *              Version No.\n * ####################################\n */\n\n#define IFX_PTM_VER_MAJOR               1\n#define IFX_PTM_VER_MID                 0\n#define IFX_PTM_VER_MINOR               27\n\n\n\n/*\n * ####################################\n *              Definition\n * ####################################\n */\n\n/*\n *  Compile Options\n */\n\n#define ENABLE_DEBUG                    1\n\n#define ENABLE_ASSERT                   1\n\n#define INLINE\n\n#define DEBUG_DUMP_SKB                  1\n\n#define DEBUG_QOS                       1\n\n#define ENABLE_DBG_PROC                 0\n\n#define ENABLE_FW_PROC                  1\n\n#if defined(CONFIG_DSL_MEI_CPE_DRV) && !defined(CONFIG_IFXMIPS_DSL_CPE_MEI)\n  #define CONFIG_IFXMIPS_DSL_CPE_MEI    1\n#endif\n\n/*\n *  Debug/Assert/Error Message\n */\n\n#define DBG_ENABLE_MASK_ERR             (1 << 0)\n#define DBG_ENABLE_MASK_DEBUG_PRINT     (1 << 1)\n#define DBG_ENABLE_MASK_ASSERT          (1 << 2)\n#define DBG_ENABLE_MASK_DUMP_SKB_RX     (1 << 8)\n#define DBG_ENABLE_MASK_DUMP_SKB_TX     (1 << 9)\n#define DBG_ENABLE_MASK_DUMP_QOS        (1 << 10)\n#define DBG_ENABLE_MASK_DUMP_INIT       (1 << 11)\n#define DBG_ENABLE_MASK_MAC_SWAP        (1 << 12)\n#define DBG_ENABLE_MASK_ALL             (DBG_ENABLE_MASK_ERR | DBG_ENABLE_MASK_DEBUG_PRINT | DBG_ENABLE_MASK_ASSERT | DBG_ENABLE_MASK_DUMP_SKB_RX | DBG_ENABLE_MASK_DUMP_SKB_TX | DBG_ENABLE_MASK_DUMP_QOS | DBG_ENABLE_MASK_DUMP_INIT | DBG_ENABLE_MASK_MAC_SWAP)\n\n#define err(format, arg...)             do { if ( (ifx_ptm_dbg_enable & DBG_ENABLE_MASK_ERR) ) printk(KERN_ERR __FILE__ \":%d:%s: \" format \"\\n\", __LINE__, __FUNCTION__, ##arg); } while ( 0 )\n\n#if defined(ENABLE_DEBUG) && ENABLE_DEBUG\n  #undef  dbg\n  #define dbg(format, arg...)           do { if ( (ifx_ptm_dbg_enable & DBG_ENABLE_MASK_DEBUG_PRINT) ) printk(KERN_WARNING __FILE__ \":%d:%s: \" format \"\\n\", __LINE__, __FUNCTION__, ##arg); } while ( 0 )\n#else\n  #if !defined(dbg)\n    #define dbg(format, arg...)\n  #endif\n#endif\n\n#if defined(ENABLE_ASSERT) && ENABLE_ASSERT\n  #define ASSERT(cond, format, arg...)  do { if ( (ifx_ptm_dbg_enable & DBG_ENABLE_MASK_ASSERT) && !(cond) ) printk(KERN_ERR __FILE__ \":%d:%s: \" format \"\\n\", __LINE__, __FUNCTION__, ##arg); } while ( 0 )\n#else\n  #define ASSERT(cond, format, arg...)\n#endif\n\n\n\n#endif  //  IFXMIPS_PTM_COMMON_H\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-ptm/src/ifxmips_ptm_danube.c",
    "content": "/******************************************************************************\n**\n** FILE NAME    : ifxmips_ptm_danube.c\n** PROJECT      : UEIP\n** MODULES      : PTM\n**\n** DATE         : 7 Jul 2009\n** AUTHOR       : Xu Liang\n** DESCRIPTION  : PTM driver common source file (core functions)\n** COPYRIGHT    :       Copyright (c) 2006\n**                      Infineon Technologies AG\n**                      Am Campeon 1-12, 85579 Neubiberg, Germany\n**\n**    This program is free software; you can redistribute it and/or modify\n**    it under the terms of the GNU General Public License as published by\n**    the Free Software Foundation; either version 2 of the License, or\n**    (at your option) any later version.\n**\n** HISTORY\n** $Date        $Author         $Comment\n** 07 JUL 2009  Xu Liang        Init Version\n*******************************************************************************/\n\n\n\n/*\n * ####################################\n *              Head File\n * ####################################\n */\n\n/*\n *  Common Head File\n */\n#include <linux/kernel.h>\n#include <linux/module.h>\n#include <linux/version.h>\n#include <linux/types.h>\n#include <linux/errno.h>\n#include <linux/proc_fs.h>\n#include <linux/init.h>\n#include <linux/ioctl.h>\n#include <linux/platform_device.h>\n#include <linux/reset.h>\n#include <linux/delay.h>\n\n/*\n *  Chip Specific Head File\n */\n#include \"ifxmips_ptm_adsl.h\"\n#include \"ifxmips_ptm_fw_danube.h\"\n\n#include <lantiq_soc.h>\n\n/*\n * ####################################\n *              Definition\n * ####################################\n */\n\n/*\n *  EMA Settings\n */\n#define EMA_CMD_BUF_LEN      0x0040\n#define EMA_CMD_BASE_ADDR    (0x00001580 << 2)\n#define EMA_DATA_BUF_LEN     0x0100\n#define EMA_DATA_BASE_ADDR   (0x00000B00 << 2)\n#define EMA_WRITE_BURST      0x2\n#define EMA_READ_BURST       0x2\n\n\n\n/*\n * ####################################\n *             Declaration\n * ####################################\n */\n\n/*\n *  Hardware Init/Uninit Functions\n */\nstatic inline void init_pmu(void);\nstatic inline void uninit_pmu(void);\nstatic inline void reset_ppe(struct platform_device *pdev);\nstatic inline void init_ema(void);\nstatic inline void init_mailbox(void);\nstatic inline void init_atm_tc(void);\nstatic inline void clear_share_buffer(void);\n\n\n\n/*\n * ####################################\n *            Local Variable\n * ####################################\n */\n\n\n#define IFX_PMU_MODULE_PPE_SLL01  BIT(19)\n#define IFX_PMU_MODULE_PPE_TC     BIT(21)\n#define IFX_PMU_MODULE_PPE_EMA    BIT(22)\n#define IFX_PMU_MODULE_PPE_QSB    BIT(18)\n#define IFX_PMU_MODULE_TPE       BIT(13)\n#define IFX_PMU_MODULE_DSL_DFE    BIT(9)\n\n/*\n * ####################################\n *            Local Function\n * ####################################\n */\n\nstatic inline void init_pmu(void)\n{\n\tltq_pmu_enable(IFX_PMU_MODULE_PPE_SLL01 |\n\t\tIFX_PMU_MODULE_PPE_TC |\n\t\tIFX_PMU_MODULE_PPE_EMA |\n\t\tIFX_PMU_MODULE_TPE |\n\t\tIFX_PMU_MODULE_DSL_DFE);\n}\n\nstatic inline void uninit_pmu(void)\n{\n\tltq_pmu_disable(IFX_PMU_MODULE_PPE_SLL01 |\n\t\tIFX_PMU_MODULE_PPE_TC |\n\t\tIFX_PMU_MODULE_PPE_EMA |\n\t\tIFX_PMU_MODULE_TPE |\n\t\tIFX_PMU_MODULE_DSL_DFE);\n}\n\nstatic inline void reset_ppe(struct platform_device *pdev)\n{\n#ifdef MODULE\n    /*unsigned int etop_cfg;\n    unsigned int etop_mdio_cfg;\n    unsigned int etop_ig_plen_ctrl;\n    unsigned int enet_mac_cfg;\n\n    etop_cfg            = *IFX_PP32_ETOP_CFG;\n    etop_mdio_cfg       = *IFX_PP32_ETOP_MDIO_CFG;\n    etop_ig_plen_ctrl   = *IFX_PP32_ETOP_IG_PLEN_CTRL;\n    enet_mac_cfg        = *IFX_PP32_ENET_MAC_CFG;\n\n    *IFX_PP32_ETOP_CFG &= ~0x03C0;\n\n    //  reset PPE\n    ifx_rcu_rst(IFX_RCU_DOMAIN_PPE, IFX_RCU_MODULE_PTM);\n\n    *IFX_PP32_ETOP_MDIO_CFG     = etop_mdio_cfg;\n    *IFX_PP32_ETOP_IG_PLEN_CTRL = etop_ig_plen_ctrl;\n    *IFX_PP32_ENET_MAC_CFG      = enet_mac_cfg;\n    *IFX_PP32_ETOP_CFG          = etop_cfg;*/\n#endif\n}\n\nstatic inline void init_ema(void)\n{\n    //  Configure share buffer master selection\n\t*SB_MST_SEL |= 0x03;\n\n    //  EMA Settings\n    IFX_REG_W32((EMA_CMD_BUF_LEN << 16) | (EMA_CMD_BASE_ADDR >> 2), EMA_CMDCFG);\n    IFX_REG_W32((EMA_DATA_BUF_LEN << 16) | (EMA_DATA_BASE_ADDR >> 2), EMA_DATACFG);\n    IFX_REG_W32(0x000000FF, EMA_IER);\n    IFX_REG_W32(EMA_READ_BURST | (EMA_WRITE_BURST << 2), EMA_CFG);\n}\n\nstatic inline void init_mailbox(void)\n{\n    IFX_REG_W32(0xFFFFFFFF, MBOX_IGU1_ISRC);\n    IFX_REG_W32(0x00000000, MBOX_IGU1_IER);\n    IFX_REG_W32(0xFFFFFFFF, MBOX_IGU3_ISRC);\n    IFX_REG_W32(0x00000000, MBOX_IGU3_IER);\n}\n\nstatic inline void init_atm_tc(void)\n{\n    IFX_REG_W32(0x0F00,     DREG_AT_CTRL);\n    IFX_REG_W32(0x3C00,     DREG_AR_CTRL);\n    IFX_REG_W32(0x0,        DREG_AT_IDLE0);\n    IFX_REG_W32(0x0,        DREG_AT_IDLE1);\n    IFX_REG_W32(0x0,        DREG_AR_IDLE0);\n    IFX_REG_W32(0x0,        DREG_AR_IDLE1);\n    IFX_REG_W32(0x0,        RFBI_CFG);\n    IFX_REG_W32(0x1600,     SFSM_DBA0);\n    IFX_REG_W32(0x1721,     SFSM_DBA1);\n    IFX_REG_W32(0x1842,     SFSM_CBA0);\n    IFX_REG_W32(0x1853,     SFSM_CBA1);\n    IFX_REG_W32(0x14011,    SFSM_CFG0);\n    IFX_REG_W32(0x14011,    SFSM_CFG1);\n    IFX_REG_W32(0x1864,     FFSM_DBA0);\n    IFX_REG_W32(0x1930,     FFSM_DBA1);\n    IFX_REG_W32(0x3000C,    FFSM_CFG0);\n    IFX_REG_W32(0x3000C,    FFSM_CFG1);\n    IFX_REG_W32(0xF0D10000, FFSM_IDLE_HEAD_BC0);\n    IFX_REG_W32(0xF0D10000, FFSM_IDLE_HEAD_BC1);\n}\n\nstatic inline void clear_share_buffer(void)\n{\n    volatile u32 *p = SB_RAM0_ADDR(0);\n    unsigned int i;\n\n    for ( i = 0; i < SB_RAM0_DWLEN + SB_RAM1_DWLEN + SB_RAM2_DWLEN + SB_RAM3_DWLEN; i++ )\n        IFX_REG_W32(0, p++);\n}\n\n/*\n *  Description:\n *    Download PPE firmware binary code.\n *  Input:\n *    src       --- u32 *, binary code buffer\n *    dword_len --- unsigned int, binary code length in DWORD (32-bit)\n *  Output:\n *    int       --- 0:    Success\n *                  else:           Error Code\n */\nstatic inline int pp32_download_code(u32 *code_src, unsigned int code_dword_len, u32 *data_src, unsigned int data_dword_len)\n{\n    volatile u32 *dest;\n\n    if ( code_src == 0 || ((unsigned long)code_src & 0x03) != 0\n        || data_src == 0 || ((unsigned long)data_src & 0x03) != 0 )\n        return -1;\n\n    if ( code_dword_len <= CDM_CODE_MEMORYn_DWLEN(0) )\n        IFX_REG_W32(0x00, CDM_CFG);\n    else\n        IFX_REG_W32(0x04, CDM_CFG);\n\n    /*  copy code   */\n    dest = CDM_CODE_MEMORY(0, 0);\n    while ( code_dword_len-- > 0 )\n        IFX_REG_W32(*code_src++, dest++);\n\n    /*  copy data   */\n    dest = CDM_DATA_MEMORY(0, 0);\n    while ( data_dword_len-- > 0 )\n        IFX_REG_W32(*data_src++, dest++);\n\n    return 0;\n}\n\n\n\n/*\n * ####################################\n *           Global Function\n * ####################################\n */\n\nextern void ifx_ptm_get_fw_ver(unsigned int *major, unsigned int *minor)\n{\n    ASSERT(major != NULL, \"pointer is NULL\");\n    ASSERT(minor != NULL, \"pointer is NULL\");\n\n    *major = FW_VER_ID->major;\n    *minor = FW_VER_ID->minor;\n}\n\nvoid ifx_ptm_init_chip(struct platform_device *pdev)\n{\n    init_pmu();\n\n    reset_ppe(pdev);\n\n    init_ema();\n\n    init_mailbox();\n\n    init_atm_tc();\n\n    clear_share_buffer();\n}\n\nvoid ifx_ptm_uninit_chip(void)\n{\n    uninit_pmu();\n}\n\n/*\n *  Description:\n *    Initialize and start up PP32.\n *  Input:\n *    none\n *  Output:\n *    int  --- 0: Success\n *             else:        Error Code\n */\nint ifx_pp32_start(int pp32)\n{\n    int ret;\n\n    /*  download firmware   */\n    ret = pp32_download_code(firmware_binary_code, sizeof(firmware_binary_code) / sizeof(*firmware_binary_code), firmware_binary_data, sizeof(firmware_binary_data) / sizeof(*firmware_binary_data));\n    if ( ret != 0 )\n        return ret;\n\n    /*  run PP32    */\n    IFX_REG_W32(DBG_CTRL_START_SET(1), PP32_DBG_CTRL);\n\n    /*  idle for a while to let PP32 init itself    */\n    udelay(10);\n\n    return 0;\n}\n\n/*\n *  Description:\n *    Halt PP32.\n *  Input:\n *    none\n *  Output:\n *    none\n */\nvoid ifx_pp32_stop(int pp32)\n{\n    /*  halt PP32   */\n    IFX_REG_W32(DBG_CTRL_STOP_SET(1), PP32_DBG_CTRL);\n}\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-ptm/src/ifxmips_ptm_fw_amazon_se.h",
    "content": "#ifndef IFXMIPS_PTM_FW_AMAZON_SE_H\n#define IFXMIPS_PTM_FW_AMAZON_SE_H\n\n\n/******************************************************************************\n**\n** FILE NAME    : ifxmips_ptm_fw_amazon_se.h\n** PROJECT      : UEIP\n** MODULES      : PTM (ADSL)\n**\n** DATE         : 1 AUG 2005\n** AUTHOR       : Xu Liang\n** DESCRIPTION  : PTM Driver (PP32 Firmware)\n** COPYRIGHT    :   Copyright (c) 2006\n**          Infineon Technologies AG\n**          Am Campeon 1-12, 85579 Neubiberg, Germany\n**\n**    This program is free software; you can redistribute it and/or modify\n**    it under the terms of the GNU General Public License as published by\n**    the Free Software Foundation; either version 2 of the License, or\n**    (at your option) any later version.\n**\n** HISTORY\n** $Date        $Author         $Comment\n**  4 AUG 2005  Xu Liang        Initiate Version\n** 23 OCT 2006  Xu Liang        Add GPL header.\n**  9 JAN 2007  Xu Liang        First version got from Anand (IC designer)\n*******************************************************************************/\n\n\n#define PTM_FW_VER_MAJOR        0\n#define PTM_FW_VER_MINOR        17\n\n\nstatic unsigned int firmware_binary_code[] = {\n    0x800004b8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x8000ffe0, 0x00000000, 0x00000000, 0x00000000,\n    0xc1000002, 0xd90c00f8, 0xc2000002, 0xda0800f9, 0x800055e0, 0xc2000000, 0xda0800f9, 0x80005580,\n    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0x94000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0x80005e58, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0x94000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0x94000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0x94000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0x94000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0xc10e0002, 0xd90c00f8, 0xc0004808, 0xc84000f8, 0x80005250, 0x00000000, 0x00000000, 0x00000000,\n    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0xc3e1fffe, 0x597dfffe, 0x593dfef4, 0x900004d9, 0x00000000, 0x00000000, 0x00000000, 0x90cc0481,\n    0x00000000, 0x00000000, 0x00000000, 0xc3e06262, 0x5bfc0022, 0xc0004802, 0xcfc000f8, 0xc0004810,\n    0xcbc000f8, 0x00000000, 0xc3800000, 0xc7f80038, 0x5fb80000, 0xc7fa0038, 0xc7bfe802, 0x5fb80000,\n    0x00000000, 0xc7bff802, 0xdbd400f9, 0xc00049a0, 0xc3800002, 0xa7ca006a, 0xc1200000, 0x5911fffe,\n    0xcd0000f9, 0xc1200000, 0x59102042, 0xcd0000f9, 0xc1000004, 0xcd0000f9, 0xc1200000, 0x59103a1e,\n    0xcd0000f9, 0x80000060, 0xc121fffe, 0x5911fffe, 0xcd0000f9, 0xc1203db8, 0x5910de82, 0xcd0000f9,\n    0xc1000006, 0xcd0000f9, 0xc120385a, 0x591033da, 0xcd0000f9, 0x5fb80002, 0x8800001a, 0x6ffe0010,\n    0x8000ff28, 0xdd7c00f9, 0xc3800000, 0xc7f86010, 0x5bb80008, 0xc3540002, 0x777da000, 0xc1000008,\n    0x4791c002, 0xcf8000f9, 0xdb900038, 0xc3800008, 0xc3720002, 0x777da000, 0xa7f00028, 0x47b9c002,\n    0xc1000000, 0xc7d26010, 0x4391c000, 0xcf8000f8, 0xdb900838, 0xc3c00000, 0xdbc800f9, 0xc0400000,\n    0xc11c0000, 0xc000082c, 0xcd05ce00, 0xc11c0002, 0xc000082c, 0xcd05ce00, 0xc0400002, 0xc11c0000,\n    0xc000082c, 0xcd05ce00, 0xc11c0002, 0xc000082c, 0xcd05ce00, 0xc0000824, 0x00000000, 0xcbc000f9,\n    0xcb8000f9, 0xcb4000f9, 0xcb0000f8, 0xc0004878, 0x5bfc4000, 0xcfc000f9, 0x5bb84000, 0xcf8000f9,\n    0x5b744000, 0xcf4000f9, 0x5b304000, 0xcf0000f8, 0xc0000a10, 0x00000000, 0xcbc000f9, 0xcb8000f8,\n    0xc0004874, 0x5bfc4000, 0xcfc000f9, 0x5bb84000, 0xcf8000f8, 0xc30001fe, 0xc000140a, 0xcf0000f8,\n    0xc3000000, 0x7f018000, 0xc000042e, 0xcf0000f8, 0xc000040e, 0xcf0000f8, 0xc3c1fffe, 0xc000490e,\n    0xcfc00078, 0xc000492c, 0xcfc00078, 0xc0004924, 0xcfc00038, 0xc0004912, 0xcfc00038, 0xc000498c,\n    0xcfc00038, 0xc000498e, 0xcfc00078, 0xc0004990, 0xcfc00078, 0xc3c00000, 0xc2800004, 0xc3000000,\n    0x7f018000, 0x6ff88000, 0x6fd44000, 0x4395c000, 0x5bb84a00, 0xc00049a0, 0xcb0000f8, 0x00000000,\n    0x58380006, 0xcf0000f8, 0xc321fffe, 0x5b31fffe, 0x58380024, 0xcf0000f8, 0x5bfc0002, 0xb7e8ff90,\n    0x00000000, 0xc3c00000, 0xc2800010, 0x6ff86000, 0x47bdc000, 0x5bb84c80, 0xc3400000, 0x58380004,\n    0xcb420078, 0x00000000, 0x58380008, 0xcf400078, 0x5bfc0002, 0xb7e8ffb0, 0x00000000, 0xc3c00000,\n    0xc2800004, 0xc3400022, 0xc3000000, 0x7f018000, 0xc2c00016, 0x6ff8a000, 0x47bdc000, 0x5bb84e20,\n    0x58380008, 0xcf400038, 0xc00049a8, 0xcb0000f8, 0x00000000, 0x5838000a, 0xcf0000f8, 0xc321fffe,\n    0x5b31fffe, 0x5838000c, 0xcf0000f8, 0x58380034, 0xcec00038, 0x5bfc0002, 0xb7e8ff78, 0x00000000,\n    0x00000000, 0xc0004840, 0xc3e12624, 0x5bfc2320, 0xcfc000f9, 0xc3e02f2c, 0x5bfd2a28, 0xcfc000f9,\n    0xc3e03734, 0x5bfd3230, 0xcfc000f9, 0xc3e13e3c, 0x5bfc3b38, 0xcfc000f9, 0xc3e14644, 0x5bfc4340,\n    0xcfc000f9, 0xc3e04f4c, 0x5bfd4a48, 0xcfc000f9, 0xc3e05754, 0x5bfd5250, 0xcfc000f9, 0xc3e15e5c,\n    0x5bfc5b58, 0xcfc000f9, 0xc3e06764, 0x5bfd6260, 0xcfc000f9, 0xc3e16e6c, 0x5bfc6b68, 0xcfc000f9,\n    0xc3e17674, 0x5bfc7370, 0xcfc000f9, 0xc3e07f7c, 0x5bfd7a78, 0xcfc000f9, 0xc3e18684, 0x5bfc8380,\n    0xcfc000f9, 0xc3e08f8c, 0x5bfd8a88, 0xcfc000f9, 0xc3e09794, 0x5bfd9290, 0xcfc000f9, 0xc3e19e9c,\n    0x5bfc9b98, 0xcfc000f9, 0xc161fffe, 0x5955fffe, 0x14140000, 0x00000000, 0x00000000, 0x00000000,\n    0x00000000, 0x00000000, 0x00000000, 0xc1000000, 0xd91c00f8, 0xc3e01002, 0x5bfd88c0, 0xc3a00f88,\n    0x5bb839a2, 0x990068d8, 0xdbd800f8, 0xdb9800f9, 0x00000000, 0xc3c00000, 0xdf7f0038, 0xa7ccfff0,\n    0xc3800000, 0xc00048c0, 0xcb818078, 0xc0001408, 0xcfc000f8, 0xc10e0002, 0xd90c00f8, 0x5d3802a6,\n    0xc1000002, 0xd91c1f02, 0xc121fffe, 0x5911fef4, 0x14100000, 0xa9fe0270, 0xc3c00000, 0xddfc00f0,\n    0x5d3c0000, 0x84000100, 0xc0000c04, 0xcb8000f8, 0xc11c0002, 0x00000000, 0x7391c000, 0xcf8000f8,\n    0xc3800000, 0xc3400080, 0xdf780038, 0xb7b4ffea, 0xc3203002, 0x5b3188c4, 0xc2e00f88, 0x5aec100e,\n    0x990068d8, 0xdb1800f8, 0xdad800f9, 0x00000000, 0xc3800000, 0xc3400080, 0xdf780038, 0xb7b4ffea,\n    0xc3205002, 0x5b3188c8, 0xc2e00f90, 0x5aec180c, 0x990068d8, 0xdb1800f8, 0xdad800f9, 0x00000000,\n    0x80000128, 0xc00048cc, 0xca8000f8, 0x00000000, 0xc1000006, 0x76914000, 0x840000fa, 0x00000000,\n    0xa6800070, 0xc3800000, 0xc3400080, 0xdf780038, 0xb7b4ffea, 0xc3202002, 0x5b31c8c6, 0xc2e00f88,\n    0x5aec100e, 0x990068d8, 0xdb1800f8, 0xdad800f9, 0x00000000, 0xa6820068, 0xc3800000, 0xc3400080,\n    0xdf780038, 0xb7b4ffea, 0xc3204002, 0x5b31c8ca, 0xc2e00f90, 0x5aec180c, 0x990068d8, 0xdb1800f8,\n    0xdad800f9, 0x00000000, 0xc00048cc, 0xc2800000, 0xce8000f8, 0xc3a00140, 0x5bfc0002, 0x47bc8000,\n    0xc1000000, 0xc53c00fe, 0xdbdc00f0, 0x80000028, 0x00000000, 0x800004e8, 0x00000000, 0x8000fd70,\n    0xc0004918, 0xd28000f8, 0xc2000000, 0xdf600038, 0x5e600080, 0x840002b2, 0x00000000, 0xc161fffe,\n    0x5955fffe, 0x14140000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0xc000480a, 0xca0000f8, 0xc0004912, 0xca4000f8, 0xc0004924, 0xca8000f8, 0xc000498c, 0xcac000f8,\n    0xc121fffe, 0x5911fef4, 0x14100000, 0x76250000, 0x76290000, 0x762d0000, 0x840001ea, 0xc0004918,\n    0xca4000f8, 0xc28001fe, 0x76290000, 0x5a640002, 0x6a254010, 0x5ee80000, 0x8400001a, 0x6aa54000,\n    0x80000010, 0xc62800f8, 0x62818008, 0xc0004918, 0xcf0000f8, 0xc161fffe, 0x5955fffe, 0x14140000,\n    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xc000498c, 0xca4000f8,\n    0xc2000002, 0x6a310000, 0x7e010000, 0x76612000, 0xce4000f8, 0xc121fffe, 0x5911fef4, 0x14100000,\n    0x6f346000, 0x4771a000, 0x5b744c80, 0xc2800000, 0x58340006, 0xca800078, 0xc2c00000, 0x58340000,\n    0xcac000d8, 0xc2400000, 0x5834000a, 0xca420078, 0x6ea82000, 0x42e9e000, 0x6f2ca000, 0x42e56000,\n    0x5aec1400, 0xc3990040, 0xc7381c18, 0xc6f80060, 0x990068d8, 0xdb9800f8, 0xdbd800f9, 0x00000000,\n    0xdea000f8, 0x46310000, 0x8400fd40, 0xc000495a, 0xc84000f8, 0x00000000, 0xc3c00002, 0x787c2000,\n    0xcc4000f8, 0xc0000838, 0xc3800000, 0xcb840028, 0x6c748000, 0x6c544000, 0x4355a000, 0x5b744a00,\n    0x5ef80000, 0x8400fca2, 0x58340004, 0xcb0000f8, 0x00000000, 0x00000000, 0xa7060020, 0x00000000,\n    0x5ef80002, 0x8400fc62, 0x5834000c, 0xc8800038, 0xc2000000, 0xc000082c, 0xca040028, 0x5a880002,\n    0xc2400000, 0xc0004958, 0xce4000f8, 0xb6280018, 0x00000000, 0xc2800000, 0x58340002, 0xc2000000,\n    0xca020008, 0xc0004956, 0xce8000f8, 0x5e600000, 0x84001ca2, 0x5e600002, 0x84004062, 0x00000000,\n    0x800021d0, 0xc0004958, 0xca0000f8, 0xc0004956, 0xca8000f8, 0x5e200000, 0x84000020, 0xc2500002,\n    0xc0000838, 0xce450800, 0x6c748000, 0x6c544000, 0x4355a000, 0x5b744a00, 0x5834000c, 0xc6900038,\n    0xcd000038, 0x8000fb38, 0xc2000000, 0xdf600038, 0x5e200080, 0x8400028a, 0x00000000, 0xc161fffe,\n    0x5955fffe, 0x14140000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0xc000480c, 0xca0000f8, 0xc0004910, 0xca4000f8, 0xc000492c, 0xca8000f8, 0xc000498e, 0xcac000f8,\n    0xc121fffe, 0x5911fef4, 0x14100000, 0x76250000, 0x76290000, 0x76e16000, 0x840001c2, 0xc0004926,\n    0xca4000f8, 0xc201fffe, 0x76e16000, 0x5a640002, 0x6ae50010, 0x5f200000, 0x8400001a, 0x6a250000,\n    0x80000010, 0xc6e000f8, 0x62014008, 0xc0004926, 0xce8000f8, 0xc161fffe, 0x5955fffe, 0x14140000,\n    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xc000498e, 0xca4000f8,\n    0xc2000002, 0x6a290000, 0x7e010000, 0x76612000, 0xce4000f8, 0xc121fffe, 0x5911fef4, 0x14100000,\n    0x6eb4a000, 0x4769a000, 0x5b744e20, 0x58340002, 0xc2000000, 0xca0000d8, 0x58340036, 0xc2400000,\n    0xca400078, 0x6eb0a000, 0x47298000, 0x5b300e56, 0x5b300004, 0x6e642000, 0x4225e000, 0xc39a8024,\n    0xc7380060, 0xc6b81c18, 0x990068d8, 0xdb9800f8, 0xdbd800f9, 0x00000000, 0xc2000000, 0xdf600038,\n    0x5e200080, 0x840002da, 0x00000000, 0xc161fffe, 0x5955fffe, 0x14140000, 0x00000000, 0x00000000,\n    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xc000490e, 0xca0000f8, 0xc000492a, 0xca4000f8,\n    0xc0004990, 0xcb0000f8, 0xc000498a, 0xcac000f8, 0xc121fffe, 0x5911fef4, 0x14100000, 0x77218000,\n    0x77258000, 0x8400021a, 0xc201fffe, 0x77218000, 0x5aec0002, 0x6b2d0010, 0x5ea00000, 0x8400001a,\n    0x6a2d0000, 0x80000010, 0xc72000f8, 0x62016008, 0xc000498a, 0xcec000f8, 0xc161fffe, 0x5955fffe,\n    0x14140000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xc0004990,\n    0xca4000f8, 0xc2000002, 0x6a2d0000, 0x7e010000, 0x76612000, 0xce4000f8, 0xc121fffe, 0x5911fef4,\n    0x14100000, 0x6ef4a000, 0x476da000, 0x5b744e20, 0x58340010, 0xc2000000, 0xca0000d8, 0x58340008,\n    0xc2400000, 0xca420078, 0x5834000e, 0xc2800000, 0xca832010, 0xc3c00000, 0x47e48000, 0x6e644010,\n    0xc7e800fc, 0x42250000, 0x4229e000, 0xc39a8008, 0x58340008, 0xcb801038, 0x58340008, 0xc2800000,\n    0xca810010, 0x6ee0a000, 0x462d0000, 0x5a20000a, 0x5a200e28, 0x42290000, 0xc6380060, 0xc6f81c18,\n    0x990068d8, 0xdb9800f8, 0xdbd800f9, 0x00000000, 0xc000495c, 0xc84000f8, 0xc3400000, 0xc3c00002,\n    0x787c2000, 0xcc4000f8, 0x6c78a000, 0x4785c000, 0x5bb84e20, 0x58380034, 0xcb410038, 0xc0000a28,\n    0xc3000000, 0xcb040028, 0xc0000a14, 0xc2c00000, 0x43358000, 0xcac40028, 0xc000490e, 0xca8000f8,\n    0x5eec0002, 0x472d8000, 0x8800f258, 0x6bc5e000, 0x76bd4000, 0x8400f240, 0x6c7ca000, 0x47c5e000,\n    0x5bfc4e20, 0x583c0008, 0xc2000000, 0xca020078, 0xc00049aa, 0x00000000, 0xca8000f9, 0xca4000f8,\n    0xc0001008, 0xce8000f8, 0xc0001006, 0xce4000f8, 0x583c000a, 0xca4000f8, 0x00000000, 0xc000100a,\n    0xce4000f8, 0xc2400006, 0xc0001000, 0xce4000f8, 0xc2600982, 0x5a643b6e, 0xc0001002, 0xce4000f8,\n    0x583c000c, 0xca4000f8, 0x00000000, 0xc0001004, 0xce4000f8, 0x583c000e, 0xcb8000f8, 0x00000000,\n    0xc2400000, 0xc7a40078, 0xc2800000, 0xc7aae020, 0xdaa000f9, 0x583c0034, 0xcb8000f8, 0x00000000,\n    0xc2c00000, 0xc7ad0038, 0xc0004978, 0xcec000f8, 0xc0800000, 0xc7880038, 0xc3400000, 0xc7b60038,\n    0xc0004980, 0xcf4000f8, 0x4661c000, 0x43a9c000, 0xc2400000, 0xc000497c, 0xce4000f8, 0xad2c0001,\n    0xc2800000, 0x00000000, 0x80000010, 0xc2800002, 0xc0004976, 0xce8000f8, 0xc2c00000, 0xc34000a0,\n    0xdb5c00f9, 0xc3400002, 0xc000497a, 0xcf4000f8, 0x5f600000, 0x84000180, 0xde2800f9, 0xc6a000f8,\n    0x47a9c000, 0x583c0000, 0xc2800000, 0xca830038, 0xc0000a28, 0xc3000000, 0xcb040028, 0xc3400000,\n    0xc0004976, 0x46b18000, 0x8800006a, 0xcf4000f8, 0x58880002, 0xc3000000, 0xc0000a14, 0xcb040028,\n    0x00000000, 0x00000000, 0xb4b001a8, 0x00000000, 0xc0800000, 0x00000000, 0x80000188, 0xc0004980,\n    0xcb4000f8, 0x00000000, 0x00000000, 0x5af40002, 0xacec0080, 0x00000000, 0xc2c00000, 0xc000497a,\n    0xadec0001, 0x00000000, 0x00000000, 0xad2c007f, 0xc2800000, 0xce8000f8, 0x80000018, 0xc2800002,\n    0xce8000f8, 0x5f6c0000, 0x840000e8, 0x00000000, 0x8000ff00, 0x5f780082, 0x88000258, 0xc3000002,\n    0xc000497c, 0xcf0000f8, 0xc2800080, 0xc1000000, 0xdd110038, 0x46914000, 0x47a94000, 0x880001d8,\n    0x4391a000, 0xc0004980, 0xcf4000f8, 0x6f684010, 0x6f77c000, 0x6f77c010, 0xc0004840, 0x40280000,\n    0xca8000f8, 0xc3000000, 0x6f506000, 0x6a908010, 0xc5300038, 0xdb1c00f9, 0x8000fe30, 0xc3400000,\n    0xc0000a10, 0xcb440060, 0x6cb04000, 0x6f288000, 0x6f744000, 0x42b14000, 0x43694000, 0xc3400000,\n    0xc6b44060, 0xc0004000, 0x40340000, 0xc321e000, 0xcf0000f8, 0x5aa80008, 0x42ad4000, 0xc3400000,\n    0xc6b44060, 0xc0004000, 0x40340000, 0xca4000f8, 0xc3000000, 0xc6f00008, 0xc1400000, 0xddd40039,\n    0x6f306000, 0xc13001fe, 0x69308010, 0x7d008000, 0x76512000, 0x6d570000, 0x6970a010, 0x42552000,\n    0xce4000f8, 0x5aa80002, 0x5aec0002, 0xacec0080, 0x00000000, 0xc2c00000, 0x5f6c0000, 0x84000118,\n    0x00000000, 0x80000040, 0x4391a000, 0x5f740080, 0xc0004980, 0xcf4000f8, 0xc3000004, 0xc000497a,\n    0xcf0000f8, 0x58880002, 0xc3400000, 0xc0000a14, 0xcb440028, 0x00000000, 0x00000000, 0xb4b40018,\n    0x00000000, 0xc0800000, 0xc3400000, 0xc0000a10, 0xcb440060, 0x6cb04000, 0x6f248000, 0x6f744000,\n    0x42712000, 0x43654000, 0xc3400000, 0xc6b44060, 0xc0004000, 0x40340000, 0xc3201e00, 0xcf0000f8,\n    0x5aa80008, 0x42ad4000, 0xc000100c, 0xcb4000f8, 0xc3000000, 0x00000000, 0xc7340060, 0xc300fffe,\n    0xc7341070, 0xcf4000f8, 0xc000100e, 0xcb4000f8, 0xc3000e28, 0x00000000, 0xc7340060, 0xc300fffe,\n    0xc7341070, 0xcf4000f8, 0xc0001010, 0xcb4000f8, 0xc3000002, 0x00000000, 0xc7341a00, 0xc7341800,\n    0xc3000000, 0xc7341900, 0xc6b40070, 0xcf4000f8, 0xc0004982, 0xce8000f8, 0x6c64a000, 0x46452000,\n    0x5a64000a, 0xc0001012, 0xcb4000f8, 0xc2800002, 0x00000000, 0xc6740260, 0xc6340008, 0xc000497c,\n    0xcb0000f8, 0xc6b41800, 0xc6b41b00, 0xc6b41c00, 0xc6b41d00, 0xc7341e00, 0xdd6800f9, 0x7e814000,\n    0x6eab2010, 0x76b14000, 0xc6b41f00, 0xc2800000, 0xc6b41900, 0xc3000080, 0x472d8000, 0xc0004982,\n    0xc90000f8, 0x47394000, 0x88000102, 0x41388000, 0xcd0000f8, 0xc7b41038, 0xc0004994, 0xce8000f8,\n    0xde1000f9, 0x45208000, 0x840000b0, 0xc1000000, 0xdd110038, 0x41388000, 0x412c8000, 0x5d100080,\n    0xc0004980, 0xcd0000f8, 0xc1000002, 0xc000497c, 0xcd0000f8, 0xc5341e00, 0xdd5000f9, 0x7d008000,\n    0xc5373f00, 0xc000497a, 0xc90000f8, 0x42390000, 0x43adc000, 0x59100002, 0xcd0000f8, 0x80000050,\n    0x42390000, 0x80000040, 0xc7341038, 0x41308000, 0xcd0000f8, 0x42310000, 0xc1000000, 0xc0004994,\n    0xcd0000f8, 0xc0001012, 0xcf4000f8, 0xc000493c, 0xce0000f8, 0xc0004984, 0xcf8000f8, 0xc000497a,\n    0xca4000f8, 0xc000497c, 0xca8000f8, 0x6c7ca000, 0x47c5e000, 0x5bfc4e20, 0xc0004976, 0xcac000f8,\n    0xc0004978, 0xca0000f8, 0x5eec0002, 0x8400008a, 0x42250000, 0xc2400000, 0xc000497a, 0xce4000f8,\n    0x583c0000, 0xc2c00000, 0xcac30038, 0x00000000, 0x00000000, 0x46e16000, 0x8800001a, 0x00000000,\n    0xad280002, 0xc000497a, 0xce0000f8, 0xc2000000, 0x5fa80000, 0x840001da, 0x00000000, 0x6c508000,\n    0xc0004880, 0x40100000, 0x58000018, 0xc90000f8, 0x00000000, 0x00000000, 0x59100002, 0xcd0000f8,\n    0x583c000e, 0xc2c00000, 0xcac00078, 0xc1000000, 0xdd532201, 0x42d16000, 0x6c508000, 0xc0004880,\n    0x40100000, 0x5800001a, 0xc90000f8, 0x00000000, 0x00000000, 0x412c8000, 0xcd0000f8, 0x99006968,\n    0xd85800f8, 0xdbd800f9, 0x00000000, 0x990066b0, 0xc000491c, 0xc1400000, 0xc9420048, 0xc000491c,\n    0x99006b68, 0xc94000f9, 0xc98000f8, 0x00000000, 0x990068d8, 0xd95800f8, 0xd99800f9, 0x00000000,\n    0xc161fffe, 0x5955fffe, 0x14140000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0x00000000, 0x98c06528, 0xd85800f8, 0xdbd800f9, 0xc45800f8, 0xc121fffe, 0x5911fef4, 0x14100000,\n    0xade80003, 0xc000493c, 0xcb4000f8, 0x00000000, 0xc3000000, 0xc7701078, 0x80000010, 0xc3000000,\n    0x583c0008, 0xcf021078, 0x6e210000, 0x583c0034, 0xce010838, 0xc0004980, 0xcb8000f8, 0x583c0034,\n    0x00000000, 0x6fba0000, 0xcf821038, 0xc000490e, 0xca0000f8, 0xc2c00002, 0x6ac56000, 0x722d0000,\n    0xce0000f8, 0x00000000, 0x00000000, 0x00000000, 0xa8e2ffe8, 0x00000000, 0xc1220002, 0xd90c00f8,\n    0x5fa80000, 0x84000712, 0xc00049a8, 0xca0000f8, 0x583c000a, 0x00000000, 0xce0000f8, 0xc221fffe,\n    0x5a21fffe, 0x583c000c, 0xce0000f8, 0xc0001004, 0xca0000f8, 0x00000000, 0x583c0012, 0x7e010000,\n    0xce0000f8, 0xa97000e1, 0x00000000, 0x00000000, 0xa97200c9, 0xc0001010, 0xc2740000, 0xce435a00,\n    0x6c64a000, 0x46452000, 0x5a64000a, 0x6e644000, 0xc0001012, 0xce400070, 0xc2600008, 0xce421038,\n    0xc27e0002, 0xce43ff00, 0xc2760002, 0xce437b00, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0x00000000, 0xa8e2ffe8, 0x00000000, 0xc1220002, 0xd90c00f8, 0xc1000000, 0xdd110038, 0x5d100000,\n    0x84000412, 0xc0004982, 0xca0000f8, 0xc0004984, 0xca4000f8, 0xc2800000, 0xc361fffe, 0x5b75fffe,\n    0xa96a001b, 0xdfec00f8, 0xc6ec1078, 0x7af56000, 0x6c40a000, 0x44040000, 0x58004e20, 0x58000014,\n    0xcec000f8, 0xa972001b, 0x5c000002, 0xcec000f8, 0xc0001010, 0xc2f40002, 0xcec35a00, 0x6c6ca000,\n    0x46c56000, 0x5aec000a, 0x6eec4000, 0xc0001012, 0xcec00070, 0xc0004994, 0xc98000f8, 0xc1400000,\n    0xdd150038, 0xc55c00f8, 0x45948000, 0x00000000, 0xc59c00fc, 0x5d1c0000, 0x840000d2, 0xc0001012,\n    0xc5d01038, 0xcd021038, 0xc2f60002, 0xcec37b00, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0x00000000, 0xa8e2ffe8, 0x00000000, 0xc1220002, 0xd90c00f8, 0x45948000, 0x88000052, 0xc0004994,\n    0xcd0000f8, 0xc0004980, 0xcbc000f8, 0x42150000, 0xc0004982, 0xce0000f8, 0x5ffc0000, 0x84000218,\n    0x58880002, 0xc3800000, 0xc0000a14, 0xcb840028, 0xc3c00000, 0xc0000a10, 0xb4b80018, 0x00000000,\n    0xc0800000, 0xcbc40060, 0x6cb84000, 0x6fac8000, 0x6ffc4000, 0x42f96000, 0x43ed0000, 0xc3400000,\n    0xc6344060, 0xc0004000, 0x40340000, 0xc2a1e000, 0xce8000f8, 0x5a200008, 0xc0004980, 0xcbc000f8,\n    0xc3400000, 0xc0004840, 0x6ff84010, 0xc7f40008, 0x40380000, 0xcb8000f8, 0xc2800000, 0x6f506000,\n    0x6b908010, 0xc52c1838, 0xc3400000, 0xc6344060, 0xc0004000, 0x40340000, 0xcec000f8, 0x5a200002,\n    0x5ffc0000, 0x84000092, 0xc0001010, 0xc62c0070, 0xcec00070, 0xc0001012, 0xc7ec1038, 0xcec21038,\n    0xc2f60002, 0xcec37b00, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xa8e2ffe8,\n    0x00000000, 0xc1220002, 0xd90c00f8, 0xc0004994, 0xc100007e, 0x453c8000, 0xcd0000f8, 0x423d0000,\n    0xc0004982, 0xce0000f8, 0xc0004994, 0xca0000f8, 0xc0004980, 0xca4000f8, 0x5e200000, 0x8400015a,\n    0xc2000000, 0xc2800000, 0x5a640002, 0xc6684028, 0xc0004982, 0xcb0000f8, 0xc0004000, 0xc2c00000,\n    0xc72c4060, 0x402c0000, 0x6e67c000, 0x6e67c010, 0x5ee40002, 0x8400003a, 0x5ee40004, 0x8400004a,\n    0x5ee40006, 0x8400005a, 0x00000000, 0x80000060, 0xce0000b8, 0x5aa80002, 0x5b300006, 0x80000040,\n    0xce000078, 0x5aa80002, 0x5b300004, 0x80000020, 0xce000038, 0x5aa80002, 0x5b300002, 0x5ee80020,\n    0x84000052, 0xc0004000, 0xc2c00000, 0xc72c4060, 0x402c0000, 0xce0000f8, 0x5aa80002, 0x5b300008,\n    0x8000ffb8, 0x00000000, 0x80000040, 0x583c000a, 0xd7c000f8, 0xc0001004, 0xca4000f8, 0x00000000,\n    0x583c000c, 0xce4000f8, 0xc000497a, 0xca4000f8, 0xc2800002, 0xc0000a28, 0xc6780928, 0xc6b80800,\n    0xcf850830, 0x6c7ca000, 0x47c5e000, 0x5bfc4e20, 0x583c0034, 0xc4900038, 0xcd000038, 0x8000e418,\n    0x6c6c8000, 0x6c544000, 0x42d56000, 0x5aec4a00, 0xc0000824, 0xca0400f8, 0x6ca48000, 0x42492000,\n    0xc3000000, 0xc3400000, 0x42250000, 0x58204000, 0xca4000f8, 0x5a200002, 0xda2400f9, 0xc2800000,\n    0xc000495e, 0xce8000f8, 0xda6000f8, 0xc2800000, 0xc66b0038, 0xdaa800f8, 0x582c0010, 0x6f206010,\n    0x40200000, 0xd82800f9, 0xca0000f8, 0xc2400000, 0xc7240010, 0x6e644000, 0xda6400f8, 0x6a254010,\n    0xc3c00000, 0xc6bc0018, 0xc3800000, 0xdea000f8, 0x5e60001e, 0x8400002a, 0x5e6001e0, 0x8400001a,\n    0x00000000, 0x80000080, 0xc7f800f8, 0x5e7c0008, 0x8400006a, 0x5bbc0002, 0x5e780008, 0x84000028,\n    0x5b740002, 0xc0004960, 0xcf0000f8, 0x80000030, 0x5e780006, 0x88000022, 0xc2800002, 0xc000495e,\n    0xce8000f8, 0xde8000f9, 0xca8000f8, 0xde6000f8, 0xc240001e, 0x6a612000, 0x7e412000, 0x76a54000,\n    0x6ba12000, 0x72a54000, 0xce8000f8, 0x5e300080, 0x840000ba, 0xc2000000, 0xc7200008, 0x5e600000,\n    0x84000058, 0xde6000f9, 0x58204000, 0xca4000f8, 0x5a200002, 0xda2400f9, 0xc2800000, 0xc66b0038,\n    0xdaa800f8, 0xda6000f8, 0x80000038, 0xc2800000, 0x6e206000, 0xde2400f8, 0x6a610000, 0xc62b0038,\n    0xdaa800f8, 0x5b300002, 0x8000fde0, 0xc2000000, 0x582c0020, 0xca020078, 0x00000000, 0xc2400000,\n    0x5a200002, 0xc6241078, 0xce421078, 0xc000480e, 0xca8000f8, 0x5e740000, 0x84000160, 0x46a12000,\n    0x8800e048, 0xc2400000, 0xc0000808, 0xca440010, 0x582c0010, 0xc1400000, 0xcd4000f9, 0xcd4000f9,\n    0xcd4000f9, 0xcd4000f9, 0xcd4000f9, 0xcd4000f9, 0xcd4000f9, 0xcd4000f9, 0xcd400018, 0x582c0020,\n    0xce021078, 0xc2000010, 0x5a640002, 0xb6240018, 0x00000000, 0xc2400000, 0xc6600010, 0xc0000808,\n    0xce040010, 0xc0004956, 0xca4000f8, 0xc11c0000, 0xc000082c, 0xcd05ce00, 0xc6600928, 0xc2400000,\n    0xc6600028, 0xc0000838, 0xce0400f8, 0xc2400002, 0xc0004958, 0xce4000f8, 0xc11c0002, 0xc000082c,\n    0xcd05ce00, 0x8000df00, 0xc000495e, 0xca0000f8, 0x5e740002, 0x8400dee0, 0x5e200000, 0x8400ded0,\n    0xc0004960, 0xca4000f8, 0xc2200004, 0x582c0002, 0xce021008, 0xc2000082, 0x46250000, 0xc6280030,\n    0xc0000810, 0xce840030, 0x99007000, 0x582c0002, 0xc94000f8, 0xc1a20000, 0x5e640000, 0x8400fed0,\n    0x00000000, 0x8000de40, 0x6c6c8000, 0x6c544000, 0x42d56000, 0x5aec4a00, 0xc000487c, 0xc80400f8,\n    0x00000000, 0x00000000, 0x40080000, 0xcb8000f8, 0xc42400f8, 0x00000000, 0xa78601a0, 0xc3c00000,\n    0xc2000000, 0x582c000c, 0xca010038, 0x6c508000, 0xc0004880, 0x40100000, 0x58000016, 0xc90000f8,\n    0x00000000, 0x00000000, 0x59100002, 0xcd0000f8, 0x5a200002, 0x582c000c, 0xc6100838, 0xcd010838,\n    0x5e600002, 0x84000020, 0xc2200004, 0x582c0002, 0xce021008, 0x5e600008, 0x84000060, 0xc2200002,\n    0x582c0002, 0xce021008, 0x582c000c, 0xcfc10838, 0xc2220002, 0xc0000a14, 0xce063100, 0xc22001a2,\n    0xc0000a1c, 0xce061038, 0x6c6c8000, 0x6c544000, 0x42d56000, 0x5aec4a00, 0x582c0004, 0xcb0000f8,\n    0xc3400000, 0x00000000, 0xa7060028, 0xcf406300, 0xc3100002, 0xc0000838, 0xcf050800, 0x582c000c,\n    0xcf421000, 0x8000dc40, 0x582c000c, 0xcfc10838, 0xc2000000, 0xc7a06010, 0x5e200000, 0x84001c08,\n    0x6c6c8000, 0x6c544000, 0x42d56000, 0x5aec4a00, 0xc000487c, 0xc80400f8, 0x00000000, 0x00000000,\n    0x40080000, 0xcb8000f8, 0xc42400f8, 0x00000000, 0xc2800000, 0xc3400000, 0xc7b5c030, 0xc0004970,\n    0xcf4000f8, 0xc2400000, 0xc7a4e030, 0xc000496c, 0xce4000f8, 0xc3000000, 0xc7b00010, 0xc3c00004,\n    0xc000496e, 0xcfc000f8, 0x582c000c, 0xca0000f8, 0xc2400002, 0xc0004964, 0xce4000f8, 0xa6200372,\n    0x00000000, 0x5e700004, 0x840000ea, 0x5e700006, 0x84000080, 0xc2000002, 0x582c0002, 0xce000000,\n    0xc0000a14, 0xce863100, 0x6c508000, 0xc0004880, 0x40100000, 0x58000014, 0xc90000f8, 0x00000000,\n    0x00000000, 0x59100002, 0xcd0000f8, 0x80001a58, 0x5e70000a, 0x84000040, 0xc2000000, 0x582c0002,\n    0xce000000, 0xc2220002, 0xc0000a14, 0xce063100, 0x8000ff70, 0x5e700008, 0x84000228, 0xc2200002,\n    0x582c000c, 0xce021000, 0x6c508000, 0xc0004880, 0x40100000, 0x58000012, 0xc90000f8, 0x00000000,\n    0x00000000, 0x59100002, 0xcd0000f8, 0x5e340002, 0x6c508000, 0xc0004880, 0x40100000, 0x58000010,\n    0xc90000f8, 0x00000000, 0x00000000, 0x41208000, 0xcd0000f8, 0xc0000a14, 0xce863100, 0xc0004970,\n    0xcb4000f8, 0x6c6c8000, 0x6c544000, 0x42d56000, 0x5aec4a00, 0x582c000e, 0xc4900038, 0xcd000038,\n    0x582c000e, 0xc7500838, 0xcd010838, 0xc2800000, 0x582c0004, 0xce821078, 0x582c0004, 0xce800000,\n    0xc00049a0, 0xca4000f8, 0x00000000, 0x582c0006, 0xce4000f8, 0xc261fffe, 0x5a65fffe, 0x582c0024,\n    0xce4000f8, 0xc2060002, 0x582c0004, 0xce006300, 0xc2400002, 0xc0004958, 0xce4000f8, 0xc0004878,\n    0xc80400f8, 0x6c908000, 0x41088000, 0x40100000, 0x58000020, 0xc90000f8, 0x582c0026, 0x00000000,\n    0xcd0000f8, 0x800017e8, 0x00000000, 0x6c508000, 0xc0004880, 0x40100000, 0x58000016, 0xc90000f8,\n    0x00000000, 0x00000000, 0x59100002, 0xcd0000f8, 0x8000faf0, 0x5e700000, 0x840000c0, 0xc3400082,\n    0xc0004970, 0xcf4000f8, 0xc2400080, 0xc000496c, 0xce4000f8, 0xc3c00002, 0xc000496e, 0xcfc000f8,\n    0xc2400000, 0xc0004964, 0xce4000f8, 0xc0004878, 0xc80400f8, 0x6c908000, 0x41088000, 0x40100000,\n    0x58000020, 0xc90000f8, 0x582c0026, 0x00000000, 0xcd0000f8, 0x80000078, 0x5e700002, 0x84000058,\n    0xc3400082, 0xc0004970, 0xcf4000f8, 0xc3c00004, 0xc000496e, 0xcfc000f8, 0xc2200000, 0x582c000c,\n    0xce021000, 0x80000030, 0x5e700004, 0x8400fe80, 0xc2600002, 0x582c000c, 0xce421000, 0xc0000a14,\n    0xce863100, 0xc000496c, 0xca4000f8, 0x6c508000, 0xc0004880, 0x40100000, 0x58000012, 0xc90000f8,\n    0x00000000, 0x00000000, 0x59100002, 0xcd0000f8, 0xc000496e, 0xcbc000f8, 0x00000000, 0x00000000,\n    0x477d0000, 0x46250000, 0x6c508000, 0xc0004880, 0x40100000, 0x58000010, 0xc90000f8, 0x00000000,\n    0x00000000, 0x41208000, 0xcd0000f8, 0x6c6c8000, 0x6c544000, 0x42d56000, 0x5aec4a00, 0x582c0004,\n    0xca0000f8, 0x00000000, 0x00000000, 0xa60014e2, 0x00000000, 0x6c6c8000, 0x6c544000, 0x42d56000,\n    0x5aec4a00, 0xc3000000, 0x582c0004, 0xcf006300, 0x582c0000, 0xcb002010, 0xc3c00000, 0x582c0004,\n    0xcbc20078, 0xc000491a, 0xcf0000f8, 0xc000493c, 0xcfc000f8, 0x582c0008, 0xcb8000f8, 0x582c000a,\n    0xca4000f8, 0xc0004930, 0xcf8000f8, 0xc0004932, 0xce4000f8, 0x5ffc0000, 0x840001f0, 0x00000000,\n    0xa7be0102, 0xc2800000, 0x6f206000, 0x46310000, 0x5a204c80, 0x5820000c, 0xca800020, 0x00000000,\n    0x00000000, 0x5ea80000, 0x84000112, 0x00000000, 0xc161fffe, 0x5955fffe, 0x14140000, 0x00000000,\n    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x990063c8, 0xc000491a, 0xc94000f8,\n    0x00000000, 0xc121fffe, 0x5911fef4, 0x14100000, 0xc0004930, 0xcb8000f8, 0xc0004932, 0xca4000f8,\n    0xc4781108, 0xc0004930, 0xcf8000f8, 0x582c0008, 0xcf8000f8, 0x582c000a, 0xce4000f8, 0xc7b6e108,\n    0x582c0004, 0xcf402108, 0x80000090, 0x00000000, 0x6c508000, 0xc0004880, 0x40100000, 0x5800000c,\n    0xc90000f8, 0x00000000, 0x00000000, 0x59100002, 0xcd0000f8, 0xc2000002, 0x582c0004, 0xce000000,\n    0xc0000838, 0xc2500002, 0xce450800, 0x80001220, 0x6c7c8000, 0x6c544000, 0x43d5e000, 0x5bfc4a00,\n    0x583c0006, 0xca0000f8, 0xc00049a2, 0x00000000, 0xca8000f9, 0xca4000f8, 0xc0001008, 0xce8000f8,\n    0xc0001006, 0xce4000f8, 0xc000100a, 0xce0000f8, 0xc2400006, 0xc0001000, 0xce4000f8, 0xc2600982,\n    0x5a643b6e, 0xc0001002, 0xce4000f8, 0x583c0024, 0xca4000f8, 0x00000000, 0xc0001004, 0xce4000f8,\n    0xc0004862, 0xc2000000, 0xca000078, 0xc360fffe, 0xc0004862, 0xce0000f8, 0xc0000824, 0xcb440060,\n    0x00000000, 0xc000100e, 0xcf4000f8, 0xc3801600, 0xc2400200, 0x6e644000, 0xc6781070, 0xc000100c,\n    0xcf8000f8, 0xc3200a00, 0xc0001010, 0xcf031810, 0xc2e06200, 0xc0001012, 0xcec31838, 0xc2000000,\n    0x583c0004, 0xca002008, 0xc2800000, 0xc0004966, 0xce0000f8, 0xc62400f8, 0xc3000000, 0xc000496a,\n    0xcf0000f8, 0xc0004974, 0xcf0000f8, 0xc000493c, 0xcb4000f8, 0x583c000e, 0x00000000, 0x5f740000,\n    0x84000180, 0xc3400000, 0xcb410038, 0xc3000002, 0xc000496a, 0x5fb40080, 0x84000152, 0xcf0000f8,\n    0x583c000e, 0xc2c00000, 0xcac00038, 0xc3800080, 0x47b5c000, 0xc0004974, 0xcf8000f8, 0xc0001012,\n    0x6fba0000, 0xcf821038, 0x6fba0010, 0x43a5c000, 0x5b380006, 0x6f284010, 0xc7a40008, 0x6eec4000,\n    0x6ef08000, 0x432d8000, 0x43358000, 0x5b300008, 0xc0001012, 0xc7100070, 0xcd000070, 0xc2000200,\n    0xc2c00000, 0xdf6d0048, 0x462d6000, 0x46e96000, 0x8800ffe2, 0xc2000000, 0xc0004862, 0xca000260,\n    0x00000000, 0x583c0004, 0xca002008, 0xc3360002, 0xc0001010, 0xce000070, 0xc0001012, 0xcf037b00,\n    0xc0004974, 0xcb8000f8, 0x00000000, 0x00000000, 0x5fb80000, 0x84000042, 0x00000000, 0x00000000,\n    0x00000000, 0xa8e2ffe8, 0x00000000, 0xc1220002, 0xd90c00f8, 0xc000496c, 0xcac000f8, 0x00000000,\n    0x00000000, 0x426dc000, 0x5b380006, 0x6f304010, 0xc7a40008, 0xc0004968, 0xce4000f8, 0xc000496e,\n    0xcb4000f8, 0x6ca44000, 0x6e608000, 0x42250000, 0x5a200006, 0x42350000, 0xc0001012, 0xc6100070,\n    0xcd000070, 0x6eee0000, 0xcec21038, 0xc2000200, 0xc2c00000, 0xdf6d0048, 0x462d6000, 0x42b14000,\n    0x46e96000, 0x8800ffda, 0xc000493c, 0xcb4000f8, 0xc0000838, 0xc3100002, 0x5f740000, 0x84000060,\n    0xcf050800, 0xc0004974, 0xcb8000f8, 0x00000000, 0x00000000, 0x5fb80000, 0x8400006a, 0xc0001012,\n    0xc3360002, 0xcf037b00, 0x800000a0, 0x583c0022, 0xcb4000f8, 0xc0004862, 0xca0000f8, 0x00000000,\n    0xc0005600, 0x40200000, 0xcf4000f8, 0xc2000000, 0xc0004862, 0xca000260, 0x00000000, 0x583c0004,\n    0xca002008, 0xc3360002, 0xc0001010, 0xce000070, 0xc0001012, 0xcf037b00, 0xc0004968, 0xcbc000f8,\n    0xc0004964, 0xca4000f8, 0xc7e000f8, 0x00000000, 0x5e640000, 0x84000012, 0xc2000000, 0xc0004974,\n    0xca4000f8, 0xc000496c, 0xca8000f8, 0xc000493c, 0xcb8000f8, 0x42698000, 0x00000000, 0x43b1a000,\n    0x5ef40080, 0x8800019a, 0xc0004966, 0xcac000f8, 0x6c648000, 0x6c544000, 0x42552000, 0x5a644a00,\n    0x58240000, 0x436da000, 0x4761a000, 0xc2400000, 0xca420078, 0x00000000, 0x00000000, 0x46752000,\n    0x88000122, 0x432d8000, 0x47218000, 0x88000010, 0xc3000000, 0x5b300006, 0x6f304010, 0xc000493a,\n    0xcf0000f8, 0xc0004932, 0xc2400000, 0xca4000d8, 0x00000000, 0x6fb84010, 0x42792000, 0xc000491e,\n    0xce4000f8, 0xc0004862, 0xca8000f8, 0x00000000, 0xc2c0000a, 0xc6e80d70, 0xc7281048, 0xc000491c,\n    0xce8000f8, 0x6c708000, 0x6c544000, 0x43158000, 0x5b304a00, 0x6f760000, 0x58300004, 0xcf421078,\n    0x6ffc2000, 0x58300004, 0xcfc02108, 0x800000d0, 0x6c708000, 0x6c544000, 0x43158000, 0x5b304a00,\n    0xc2800002, 0x58300004, 0xce800000, 0x6c508000, 0xc0004880, 0x40100000, 0x5800000e, 0xc90000f8,\n    0x00000000, 0x00000000, 0x59100002, 0xcd0000f8, 0x00000000, 0x00000000, 0x00000000, 0xa8e2ffe8,\n    0x00000000, 0xc1220002, 0xd90c00f8, 0x80000920, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0xa8e2ffe8, 0x00000000, 0xc1220002, 0xd90c00f8, 0xc0004964, 0xca0000f8, 0x6c7c8000, 0x6c544000,\n    0x43d5e000, 0x5bfc4a00, 0xdfe400f8, 0x5e200002, 0x84000608, 0x00000000, 0x583c0004, 0xc2800000,\n    0xca820078, 0xc0004930, 0xcac000f8, 0x00000000, 0x00000000, 0x6eece000, 0x6eefc010, 0x46aca000,\n    0xc1000000, 0xdd500039, 0x6d106010, 0x4550a000, 0xc1000000, 0xdd514201, 0x4550c000, 0xa95000f1,\n    0xc00049a6, 0xca0000f8, 0xa94a0023, 0x00000000, 0x6e660000, 0x6e660010, 0x46612000, 0x840000b2,\n    0x00000000, 0x6c508000, 0xc0004880, 0x40100000, 0x58000004, 0xc90000f8, 0x00000000, 0x00000000,\n    0x59100002, 0xcd0000f8, 0x6c508000, 0xc0004880, 0x40100000, 0x58000006, 0xc90000f8, 0x00000000,\n    0x00000000, 0x41148000, 0xcd0000f8, 0x80000720, 0x00000000, 0xa95203c1, 0xc0001004, 0xcb8000f8,\n    0xc3400000, 0xdd740039, 0x5f740000, 0x840000d0, 0xc1218e08, 0x5911baf6, 0x45388000, 0x84000372,\n    0x00000000, 0x6c508000, 0xc0004880, 0x40100000, 0x58000008, 0xc90000f8, 0x00000000, 0x00000000,\n    0x59100002, 0xcd0000f8, 0x6c508000, 0xc0004880, 0x40100000, 0x5800000a, 0xc90000f8, 0x00000000,\n    0x00000000, 0x41148000, 0xcd0000f8, 0x80000620, 0x00000000, 0xc000496c, 0xcb0000f8, 0x583c0026,\n    0xcac000f8, 0xc0004878, 0xc80400f8, 0x6c908000, 0x41088000, 0x40100000, 0x58000002, 0xca8000f8,\n    0x00000000, 0x00000000, 0x6ea90000, 0x5d300008, 0x8800004a, 0x59300002, 0xc3000000, 0xc5300008,\n    0x6d104010, 0x40100000, 0xca8000f8, 0x5c000002, 0xcac000f8, 0x5d300000, 0x8400003a, 0x6f246000,\n    0x6ae56000, 0xc1000040, 0x45252000, 0x6aa54010, 0x42e96000, 0x583c0026, 0xcec000f8, 0xc1218e08,\n    0x5911baf6, 0xc0001004, 0xcd0000f8, 0x593c0026, 0xc000100e, 0xcd000060, 0xc1340000, 0xc0001010,\n    0xcd035a00, 0xc1200008, 0xa94a0023, 0xc0001012, 0xc1200004, 0x59100004, 0xcd0000b8, 0xc1360002,\n    0xcd037b00, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xa8e2ffe8, 0x00000000,\n    0xc1220002, 0xd90c00f8, 0xc0001004, 0xc90000f8, 0x00000000, 0x00000000, 0x45388000, 0x840000b2,\n    0x00000000, 0x6c508000, 0xc0004880, 0x40100000, 0x58000008, 0xc90000f8, 0x00000000, 0x00000000,\n    0x59100002, 0xcd0000f8, 0x6c508000, 0xc0004880, 0x40100000, 0x5800000a, 0xc90000f8, 0x00000000,\n    0x00000000, 0x41148000, 0xcd0000f8, 0x80000360, 0x00000000, 0x6c508000, 0xc0004880, 0x40100000,\n    0x58000000, 0xc90000f8, 0x00000000, 0x00000000, 0x59100002, 0xcd0000f8, 0x6c508000, 0xc0004880,\n    0x40100000, 0x58000002, 0xc90000f8, 0x00000000, 0x00000000, 0x41148000, 0xcd0000f8, 0xc0004930,\n    0xcd800078, 0xc3000000, 0x583c0008, 0xcf0000f8, 0x80000038, 0xc0001004, 0xca0000f8, 0x583c0006,\n    0xce4000f8, 0x583c0024, 0xce0000f8, 0xc0004862, 0xc2000000, 0xca000078, 0xc000493a, 0xca4000f8,\n    0x00000000, 0x00000000, 0x42254000, 0x5ee80200, 0x88000012, 0xc6e800f8, 0xc0004000, 0x58001600,\n    0x40280000, 0xcb8000f8, 0x00000000, 0x583c0022, 0xcf8000f8, 0xc0004862, 0xce800078, 0xc0001406,\n    0xcac000f8, 0xc2800002, 0x00000000, 0xc66c1048, 0xc6ac0a00, 0xcec000f8, 0xc2000000, 0xdf600038,\n    0x5e600080, 0x8400ffea, 0xc000491c, 0xca4000f8, 0xc000491e, 0xca8000f8, 0x990068d8, 0xda5800f8,\n    0xda9800f9, 0x00000000, 0xc0004964, 0xcbc000f8, 0x00000000, 0x00000000, 0x5ffc0000, 0x84000102,\n    0xc2000000, 0xdf610048, 0x5e6001fe, 0x8800ffe8, 0xc000491a, 0xc98000f8, 0xc0004862, 0xc94000f8,\n    0x6d9c6000, 0x45d8e000, 0x59dc4c80, 0x99006738, 0xd95800f8, 0xd99800f9, 0xd9d400f8, 0x990066b0,\n    0xc000491c, 0xc1400000, 0xc9420048, 0xc2000000, 0xdf600038, 0x5e600080, 0x8400ffea, 0xc000491c,\n    0xca4000f8, 0xc000491e, 0xca8000f8, 0x990068d8, 0xda5800f8, 0xda9800f9, 0x00000000, 0xc0004970,\n    0xcb4000f8, 0x00000000, 0x00000000, 0x5e740082, 0x8400e6d8, 0x00000000, 0x8000c018, 0x00000000,\n    0x6c508000, 0xc0004880, 0x40100000, 0x58000016, 0xc90000f8, 0x00000000, 0x00000000, 0x59100002,\n    0xcd0000f8, 0x8000e308, 0x6c6c8000, 0x6c544000, 0x42d56000, 0x5aec4a00, 0xc000487c, 0xc80400f8,\n    0x00000000, 0x00000000, 0x40080000, 0xca0000f8, 0xc42400f8, 0x00000000, 0xa60600f8, 0xc3c00000,\n    0xc2000000, 0x582c000c, 0xca010038, 0x00000000, 0x00000000, 0x5a200002, 0xc6100838, 0xcd010838,\n    0x5e60000e, 0x8400bf00, 0xc2200000, 0x582c0002, 0xce021008, 0x582c000c, 0xcfc10838, 0x582c0020,\n    0xcfc21078, 0x582c0010, 0xc1400000, 0xcd4000f9, 0xcd4000f9, 0xcd4000f9, 0xcd4000f9, 0xcd4000f9,\n    0xcd4000f9, 0xcd4000f9, 0xcd4000f9, 0xcd400018, 0x8000be68, 0xc2200004, 0x582c0002, 0xce021008,\n    0x582c000c, 0xcfc10838, 0x99007000, 0x582c0002, 0xc94000f8, 0xc1a20000, 0x8000be18, 0xc3e1fffe,\n    0x597dfffe, 0x593dfef4, 0x94000001, 0x00000000, 0x00000000, 0x00000000, 0xc0800000, 0xdf4b0038,\n    0xc0004900, 0xcb8000f8, 0xc2000000, 0xc000490a, 0xa78000d0, 0xcbc000f8, 0xc1000000, 0xd90000f9,\n    0xc1000002, 0xd90c00f8, 0x6ff46000, 0x477da000, 0x5b744c80, 0xc2400000, 0x58340004, 0xca400078,\n    0xc0004900, 0xce000000, 0x5a640002, 0x58340004, 0xc6500078, 0xcd000078, 0xc0004914, 0xca4000f8,\n    0xc2000002, 0x6a3d0000, 0x72612000, 0xce4000f8, 0xc0000408, 0xce0000f8, 0xa78200c8, 0xc0004908,\n    0xcbc000f8, 0xc1000000, 0xd90000f9, 0xc1000002, 0xd90c00f8, 0x6ff4a000, 0x477da000, 0x5b744e20,\n    0xc2800000, 0x58340006, 0xca800078, 0xc2000000, 0xc0004900, 0xce002100, 0x5ea80002, 0x58340006,\n    0xc6900078, 0xcd000078, 0x5a7c0020, 0xc2000002, 0x6a250000, 0xc0000408, 0xce0000f8, 0xdca800f9,\n    0x5ea80000, 0x8400a860, 0x00000000, 0xa4800230, 0x00000000, 0xc3c00000, 0xc000140e, 0xcbc00018,\n    0xc3400000, 0xc2400000, 0x6ff86000, 0x47bdc000, 0x5bb84c80, 0x58380008, 0xcb400078, 0x58380006,\n    0xca400078, 0x5f740002, 0x58380008, 0xc7500078, 0xcd000078, 0xc2000000, 0x58380004, 0xca020078,\n    0xc3000000, 0x5838000c, 0xcb000020, 0x5a640002, 0x46610000, 0x84000010, 0xc2400000, 0x58380006,\n    0xc6500078, 0xcd000078, 0xc2000000, 0x5838000a, 0xca020078, 0x5b300002, 0x5838000c, 0xc7100020,\n    0xcd000020, 0xc2420020, 0x5a200004, 0x46252000, 0x84000010, 0xc2000000, 0x5838000a, 0xc6101078,\n    0xcd021078, 0xc000498c, 0xca4000f8, 0xc2000002, 0x6a3d0000, 0x72612000, 0xce4000f8, 0x5f740000,\n    0x84000040, 0xc0004912, 0xca0000f8, 0xc2c00002, 0x6afd6000, 0x7ec16000, 0x762d0000, 0xce0000f8,\n    0x5f300020, 0x84000040, 0xc0004924, 0xca0000f8, 0xc2c00002, 0x6afd6000, 0x7ec16000, 0x762d0000,\n    0xce0000f8, 0xa4820070, 0xc2400000, 0xc000140e, 0xca408018, 0xc2000002, 0xc0004900, 0xce000000,\n    0xc000490a, 0xce4000f8, 0xc1000000, 0xd90000f9, 0xd8400078, 0xc1000004, 0xd90000f9, 0xa48402d8,\n    0x00000000, 0xc3c00000, 0xc000140e, 0xcbc10018, 0xc2800000, 0xc2000000, 0x6ff8a000, 0x47bdc000,\n    0x5bb84e20, 0x58380036, 0xca800078, 0x58380006, 0xca020078, 0xc3400000, 0x58380036, 0xcb420078,\n    0x5aa80002, 0x46a10000, 0x84000010, 0xc2800000, 0x58380036, 0xc6900078, 0xcd000078, 0x5f740002,\n    0x58380036, 0xc7501078, 0xcd021078, 0xc000498e, 0xca4000f8, 0xc2000002, 0x6a3d0000, 0x72612000,\n    0xce4000f8, 0xc000492a, 0xca8000f8, 0x5e740000, 0x84000040, 0xc0004910, 0xca0000f8, 0xc2c00002,\n    0x6afd6000, 0x7ec16000, 0x762d0000, 0xce0000f8, 0x6abd4010, 0xa6800132, 0x00000000, 0x5838003a,\n    0xca0000f8, 0x58000002, 0xca4000f8, 0x5838000e, 0x00000000, 0xce0000f9, 0xce4000f8, 0xc2400000,\n    0xdd250038, 0xc1000080, 0x45248000, 0xc2400000, 0xc6240078, 0x46510000, 0x00000000, 0xc52400fc,\n    0x5d240078, 0xc1000078, 0xc52400fc, 0xc6600078, 0x5c000002, 0xce000078, 0xc000492a, 0xca0000f8,\n    0xc2c00002, 0x6afd6000, 0x722d0000, 0xce0000f8, 0xc000492c, 0xca0000f8, 0xc2c00002, 0x6afd6000,\n    0x722d0000, 0xce0000f8, 0x80000040, 0xc000492c, 0xca0000f8, 0xc2c00002, 0x6afd6000, 0x7ec16000,\n    0x762d0000, 0xce0000f8, 0xa4880088, 0xc2c00000, 0xc000140e, 0xcac20018, 0xc000490e, 0xca4000f8,\n    0xc2000002, 0x6a2d0000, 0x7e010000, 0x76612000, 0xce4000f8, 0xc0004990, 0xca4000f8, 0xc2000002,\n    0x6a2d0000, 0x72612000, 0xce4000f8, 0xa4860070, 0xc2400000, 0xc000140e, 0xca418018, 0xc2020002,\n    0xc0004900, 0xce002100, 0xc0004908, 0xce4000f8, 0xc1000000, 0xd90000f9, 0xd8400078, 0xc1000004,\n    0xd90000f9, 0xa48c00e8, 0xc2400000, 0xc000140e, 0xca430018, 0x00000000, 0x00000000, 0x5d240002,\n    0x84000058, 0xc00048c4, 0xca0000f8, 0xc00048c6, 0xc1040002, 0x72110000, 0xce0000f8, 0xc1000002,\n    0xc00048cc, 0xcd000000, 0x80000060, 0x5d240004, 0x84000050, 0xc00048c8, 0xca0000f8, 0xc00048ca,\n    0xc1160002, 0x72110000, 0xce0000f8, 0xc1020002, 0xc00048cc, 0xcd002100, 0xc0001408, 0xcc8000f8,\n    0xc10e0002, 0xd90c00f8, 0x8000f668, 0xdfbc00f9, 0xc0004992, 0x99007040, 0xc94000f8, 0xc7d800f8,\n    0x00000000, 0xc57000f8, 0x5ef00020, 0x88000158, 0x6f346000, 0x4771a000, 0x5b744c80, 0x58340008,\n    0xc2400000, 0xca400078, 0x00000000, 0xc2000000, 0x5a640002, 0xc6500078, 0xcd000078, 0x58340004,\n    0xca000078, 0x00000000, 0x00000000, 0x5e200002, 0xc6100078, 0xcd000078, 0xc0004912, 0xca8000f8,\n    0xc2400002, 0x6a712000, 0x72a54000, 0xce8000f8, 0x5e200000, 0x84000052, 0xc000480a, 0xca0000f8,\n    0xc0000408, 0xca8000f8, 0x76250000, 0x00000000, 0x72a14000, 0xce8000f8, 0x80000038, 0xc0004914,\n    0xca0000f8, 0x7e412000, 0x00000000, 0x76250000, 0xce0000f8, 0x800000c8, 0x6ef4a000, 0x476da000,\n    0x5b744e20, 0x58340036, 0xc2400000, 0xca420078, 0x00000000, 0xc2000000, 0x5a640002, 0xc6501078,\n    0xcd021078, 0x58340006, 0xca000078, 0x00000000, 0x00000000, 0x5a200002, 0xc6100078, 0xcd000078,\n    0xc0004910, 0xca4000f8, 0xc2000002, 0x6a2d0000, 0x72612000, 0xce4000f8, 0xc2000002, 0x6a310000,\n    0xc000042a, 0xce0000f8, 0xc1040002, 0xd90c00f8, 0x00000000, 0x8000f3d0, 0x00000000, 0xc4980928,\n    0x9d000000, 0xc5580028, 0xc0000838, 0xcd8400f8, 0xc1440200, 0xc1c01600, 0xc55c1070, 0xc000100e,\n    0x9d000000, 0xcd8000f8, 0xc000100c, 0xcdc000f8, 0xc0004862, 0xc9c000f8, 0x00000000, 0x00000000,\n    0xd9d800f9, 0xc0005600, 0x401c0000, 0x5dc05800, 0x88000012, 0x5c000200, 0xcd8000f8, 0xc1f0000a,\n    0x715ca000, 0xdd9800f8, 0xdd9c00f9, 0x41d8e000, 0xc5d40260, 0xc0001010, 0xcd4000f8, 0x6c9c8000,\n    0x45c8e000, 0x45c8e000, 0x59dc0004, 0xc1601260, 0xc5d40260, 0x9d000000, 0xc0001012, 0xcd4000f8,\n    0x00000000, 0x00000000, 0xd95800f8, 0x6d586000, 0x4594c000, 0x59984c80, 0xd99800f9, 0x5818000a,\n    0xc1800000, 0xc9800078, 0xc0005400, 0x6d5ca000, 0x401c0000, 0x40180000, 0xc94000f8, 0x58000002,\n    0x00000000, 0xc9c000f8, 0xc0004930, 0xcd4000f8, 0xc0004932, 0xcdc000f8, 0x59980004, 0xc1c20020,\n    0xb59c0018, 0x00000000, 0xc1800000, 0xdd9c00f9, 0x581c000a, 0xcd800078, 0x581c000c, 0xc1800000,\n    0xc9800020, 0xc1c00002, 0xdd9400f8, 0x69d4e000, 0x5d980002, 0xcd800020, 0xc0004924, 0xc98000f8,\n    0x00000000, 0x9d000000, 0x00000000, 0x719cc000, 0xcd8000f8, 0xc000492a, 0xc94000f8, 0xc1c00002,\n    0x69d8e000, 0x7dc0c000, 0x7558a000, 0xcd4000f8, 0xc000492c, 0xc94000f8, 0xdd8000f9, 0x5800003a,\n    0x755ca000, 0x84000108, 0xc94000f9, 0xc98000f8, 0xdd8000f9, 0x5800000e, 0x00000000, 0xcd4000f9,\n    0xcd8000f8, 0xc1800000, 0xdd190038, 0xc1000080, 0x45188000, 0xc1800000, 0xc5580078, 0x4590a000,\n    0x00000000, 0xc51800fc, 0x5d180078, 0xc1000078, 0xc51800fc, 0xc5940078, 0x5c000002, 0xcd400078,\n    0xc000492c, 0xc94000f8, 0xc000492a, 0xc98000f8, 0x715ca000, 0xc000492c, 0xcd4000f8, 0x719cc000,\n    0xc000492a, 0xcd8000f8, 0x9cc00000, 0x00000000, 0x00000000, 0x00000000, 0xc0004862, 0xc98000f8,\n    0x00000000, 0xc1c00200, 0x4194c000, 0x459ce000, 0x88000012, 0xc5d800f8, 0xc0004862, 0xcd8000f8,\n    0xc0001406, 0xc98000f8, 0xc1c00002, 0x9d000000, 0xc5d80a00, 0xc5581048, 0xcd8000f8, 0xc0004930,\n    0xc98000f8, 0xc0004932, 0xc9c000f8, 0xc140000e, 0xc5581c18, 0xdd9400f8, 0xc0005600, 0x40140000,\n    0x5d405800, 0x88000012, 0x5c000200, 0xcd8000f8, 0x58000002, 0x5d405800, 0x88000012, 0x5c000200,\n    0xcdc000f8, 0xdd5400f8, 0xc1c00000, 0x58140006, 0xc9c20078, 0xc1800000, 0x58140000, 0xc98000d8,\n    0x6ddc2000, 0xc000491e, 0x41d8e000, 0xcdc000f8, 0xdd9800f8, 0xc1c00022, 0xc5d80d70, 0xdd9400f9,\n    0xc5581c18, 0xc000491c, 0xcd8000f8, 0xdd5400f8, 0xc1c00000, 0x58140006, 0xc9c20078, 0xc1800000,\n    0x58140004, 0xc9820078, 0x00000000, 0x59dc0002, 0x45d8c000, 0x84000010, 0xc1c00000, 0x9d000000,\n    0x58140006, 0xc5d81078, 0xcd821078, 0xc0004860, 0xc94000f8, 0xc1820080, 0xc1d00002, 0x58146b00,\n    0xd58000f8, 0x58000002, 0xd58000f9, 0x59540004, 0xb5580018, 0xc0004860, 0xc1400000, 0xcd4000f8,\n    0xdd9800f9, 0x9d000000, 0xdd9400f8, 0xc0001404, 0xcdc10800, 0xc1c00000, 0xc1800200, 0x5d980004,\n    0xdf5d0048, 0x459ca000, 0x8800fff2, 0xdd8000f9, 0x5800000e, 0x00000000, 0xc94000f9, 0xc98000f8,\n    0xc1c00002, 0xc5d43f00, 0xc5d81e00, 0xc0004862, 0xc9c000f8, 0x00000000, 0x00000000, 0x581c5600,\n    0x5dc05800, 0x88000012, 0x5c000200, 0xcd4000f8, 0x58000002, 0x5dc05800, 0x88000012, 0x5c000200,\n    0xcd8000f8, 0xc0004862, 0xc9c000f8, 0x00000000, 0xc15004c0, 0xc5d40060, 0xdd9c00f8, 0xc5d41c18,\n    0xc1c00000, 0xdd8000f9, 0x58000038, 0xc9c00078, 0xdd8000f9, 0xc1800000, 0x58000002, 0xc98000d8,\n    0x6ddc2000, 0xc000491c, 0x41d8e000, 0xcd4000f9, 0xcdc000f8, 0xdd9400f9, 0xc1c00000, 0x58140038,\n    0xc9c00078, 0xc1800000, 0x58140006, 0xc9820078, 0x00000000, 0x59dc0002, 0x45d8c000, 0x84000010,\n    0xc1c00000, 0x9d000000, 0x58140038, 0xc5d80078, 0xcd800078, 0xc1c00000, 0xdf5c0038, 0x5ddc0080,\n    0x8400ffea, 0x00000000, 0x9d000000, 0x00000000, 0x00000000, 0x00000000, 0xc160fffe, 0xc0000a10,\n    0xc9440060, 0xc1a0fffe, 0x59980e28, 0xc000100c, 0xcd4000f8, 0xc000100e, 0xcd8000f8, 0xc0004962,\n    0xc98000f8, 0x00000000, 0xc170000a, 0x7158a000, 0x6c988000, 0x4588c000, 0x4588c000, 0x59980004,\n    0xc5940270, 0xc0001010, 0xcd4000f8, 0xc0004946, 0xc94000f8, 0x00000000, 0x00000000, 0x6d58a000,\n    0x6d5c4000, 0x459cc000, 0x4594c000, 0xc000494a, 0xc94000f8, 0xc0004948, 0xc9c000f8, 0x4194c000,\n    0xc1400012, 0xc55c1818, 0x9d000000, 0xc59c0268, 0xc0001012, 0xcdc000f8, 0xc1400000, 0x58000014,\n    0xc9410038, 0xc0004950, 0xc9c000f8, 0xc55800f8, 0xc5940838, 0xc5581078, 0xd99400f8, 0xc000493c,\n    0xc94000f8, 0xc0004954, 0xc98000f8, 0x59dc00a8, 0x45d4e000, 0x41d8e000, 0x5d5c0030, 0x88000010,\n    0xc1c00030, 0xc1800000, 0xc5d84028, 0xc1400000, 0xc5d40008, 0x5dd40002, 0x84000072, 0x5dd40004,\n    0x8400009a, 0x5dd40006, 0x840000c2, 0x5dd80026, 0x840000ea, 0xdd5400f8, 0xdd8000f9, 0x58000008,\n    0x40180000, 0xcd4000f8, 0x59980002, 0x8000ffc0, 0xdd5400f8, 0xdd8000f9, 0x58000008, 0x40180000,\n    0xcd4000b8, 0x59980002, 0x8000ff88, 0xdd5400f8, 0xdd8000f9, 0x58000008, 0x40180000, 0xcd400078,\n    0x59980002, 0x8000ff50, 0xdd5400f8, 0xdd8000f9, 0x58000008, 0x40180000, 0xcd400038, 0x59980002,\n    0x8000ff18, 0x00000000, 0x9d000000, 0x00000000, 0x00000000, 0x00000000, 0x58000014, 0xc94000f8,\n    0xc0004954, 0xc9c000f8, 0xc0004950, 0xc9400078, 0xdd8000f9, 0x5800002a, 0x5d9c0000, 0x84000052,\n    0x5d9c0002, 0x84000052, 0x5d9c0004, 0x8400006a, 0xc55b0038, 0xc55c08b8, 0xcd800039, 0xcdc108b8,\n    0x80000060, 0xcd4000f8, 0x80000050, 0xc55900b8, 0xc55c1838, 0xcd8000b9, 0xcdc31838, 0x80000028,\n    0xc55a0078, 0xc55c1078, 0xcd800079, 0xcdc21078, 0x9d000000, 0x00000000, 0x00000000, 0x00000000,\n    0xc1e00000, 0xa540001a, 0xc0000a14, 0xc1a20002, 0x9d000000, 0xcd863100, 0xc0000a1c, 0xcdc61038,\n    0x59540002, 0x6994e018, 0x61c0c008, 0x4194a000, 0x5d940040, 0x88000012, 0xc59400f8, 0x9d000000,\n    0xcd4000f8, 0x00000000, 0x00000000,\n};\n\nstatic unsigned int firmware_binary_data[] = {\n};\n\n\n#endif  //  IFXMIPS_PTM_FW_AMAZON_SE_H\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-ptm/src/ifxmips_ptm_fw_ar9.h",
    "content": "#ifndef IFXMIPS_PTM_FW_AR9_H\n#define IFXMIPS_PTM_FW_AR9_H\n\n\n/******************************************************************************\n**\n** FILE NAME    : ifxmips_ptm_fw_ar9.h\n** PROJECT      : UEIP\n** MODULES     \t: PTM (ADSL)\n**\n** DATE         : 22 OCT 2007\n** AUTHOR       : Xu Liang\n** DESCRIPTION  : PTM Driver (PP32 Firmware)\n** COPYRIGHT    : \tCopyright (c) 2006\n**\t\t\tInfineon Technologies AG\n**\t\t\tAm Campeon 1-12, 85579 Neubiberg, Germany\n**\n**    This program is free software; you can redistribute it and/or modify\n**    it under the terms of the GNU General Public License as published by\n**    the Free Software Foundation; either version 2 of the License, or\n**    (at your option) any later version.\n**\n** HISTORY\n** $Date        $Author         $Comment\n** 22 OCT 2007  Xu Liang        Initiate Version, v00.01\n*******************************************************************************/\n\n\n#define PTM_FW_VER_MAJOR        0\n#define PTM_FW_VER_MINOR        17\n\n\nstatic unsigned int firmware_binary_code[] = {\n    0x800004b8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x8000ffe0, 0x00000000, 0x00000000, 0x00000000,\n    0xc1000002, 0xd90c00f8, 0xc2000002, 0xda0800f9, 0x80005270, 0xc2000000, 0xda0800f9, 0x80005210,\n    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0x94000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0x80005a00, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0x94000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0x94000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0x94000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0x94000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0xc10e0002, 0xd90c00f8, 0xc0004808, 0xc84000f8, 0x80004ee0, 0x00000000, 0x00000000, 0x00000000,\n    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0xc3e1fffe, 0x597dfffe, 0x593dfef4, 0x900004d9, 0x00000000, 0x00000000, 0x00000000, 0x90cc0481,\n    0x00000000, 0x00000000, 0x00000000, 0xc3e0a262, 0x5bfc0022, 0xc0004002, 0xcfc000f8, 0xc0004810,\n    0xcbc000f8, 0x00000000, 0xc3800000, 0xc7f80038, 0x5fb80000, 0xc7fa0038, 0xc7bfe802, 0x5fb80000,\n    0x00000000, 0xc7bff802, 0xdbd400f9, 0xc00049a0, 0xc3800002, 0xa7ca006a, 0xc1200000, 0x5911fffe,\n    0xcd0000f9, 0xc1200000, 0x59102042, 0xcd0000f9, 0xc1000004, 0xcd0000f9, 0xc1200000, 0x59103a1e,\n    0xcd0000f9, 0x80000060, 0xc121fffe, 0x5911fffe, 0xcd0000f9, 0xc1203db8, 0x5910de82, 0xcd0000f9,\n    0xc1000006, 0xcd0000f9, 0xc120385a, 0x591033da, 0xcd0000f9, 0x5fb80002, 0x8800001a, 0x6ffe0010,\n    0x8000ff28, 0xdd7c00f9, 0xc3800000, 0xc7f86010, 0x5bb80008, 0xc3540002, 0x777da000, 0xc1000008,\n    0x4791c002, 0xcf8000f9, 0xdb900038, 0xc3800008, 0xc3720002, 0x777da000, 0xa7f00028, 0x47b9c002,\n    0xc1000000, 0xc7d26010, 0x4391c000, 0xcf8000f8, 0xdb900838, 0xc3c00000, 0xdbc800f9, 0xc0400000,\n    0xc11c0000, 0xc000082c, 0xcd05ce00, 0xc11c0002, 0xc000082c, 0xcd05ce00, 0xc0400002, 0xc11c0000,\n    0xc000082c, 0xcd05ce00, 0xc11c0002, 0xc000082c, 0xcd05ce00, 0xc0000824, 0x00000000, 0xcbc000f9,\n    0xcb8000f9, 0xcb4000f9, 0xcb0000f8, 0xc0004878, 0x5bfc4000, 0xcfc000f9, 0x5bb84000, 0xcf8000f9,\n    0x5b744000, 0xcf4000f9, 0x5b304000, 0xcf0000f8, 0xc0000a10, 0x00000000, 0xcbc000f9, 0xcb8000f8,\n    0xc0004874, 0x5bfc4000, 0xcfc000f9, 0x5bb84000, 0xcf8000f8, 0xc30001fe, 0xc000140a, 0xcf0000f8,\n    0xc3000000, 0x7f018000, 0xc000042e, 0xcf0000f8, 0xc000040e, 0xcf0000f8, 0xc3c1fffe, 0xc000490e,\n    0xcfc00078, 0xc000492c, 0xcfc00078, 0xc0004924, 0xcfc00038, 0xc0004912, 0xcfc00038, 0xc000498c,\n    0xcfc00038, 0xc000498e, 0xcfc00078, 0xc0004990, 0xcfc00078, 0xc3c00000, 0xc2800004, 0xc3000000,\n    0x7f018000, 0x6ff88000, 0x6fd44000, 0x4395c000, 0x5bb87e00, 0xc00049a0, 0xcb0000f8, 0x00000000,\n    0x58380006, 0xcf0000f8, 0xc321fffe, 0x5b31fffe, 0x58380024, 0xcf0000f8, 0x5bfc0002, 0xb7e8ff90,\n    0x00000000, 0xc3c00000, 0xc2800010, 0x6ff86000, 0x47bdc000, 0x5bb84c80, 0xc3400000, 0x58380004,\n    0xcb420078, 0x00000000, 0x58380008, 0xcf400078, 0x5bfc0002, 0xb7e8ffb0, 0x00000000, 0xc3c00000,\n    0xc2800004, 0xc3400022, 0xc3000000, 0x7f018000, 0xc2c00016, 0x6ff8a000, 0x47bdc000, 0x5bb87600,\n    0x58380008, 0xcf400038, 0xc00049a8, 0xcb0000f8, 0x00000000, 0x5838000a, 0xcf0000f8, 0xc321fffe,\n    0x5b31fffe, 0x5838000c, 0xcf0000f8, 0x58380034, 0xcec00038, 0x5bfc0002, 0xb7e8ff78, 0x00000000,\n    0x00000000, 0xc0004840, 0xc3e12624, 0x5bfc2320, 0xcfc000f9, 0xc3e02f2c, 0x5bfd2a28, 0xcfc000f9,\n    0xc3e03734, 0x5bfd3230, 0xcfc000f9, 0xc3e13e3c, 0x5bfc3b38, 0xcfc000f9, 0xc3e14644, 0x5bfc4340,\n    0xcfc000f9, 0xc3e04f4c, 0x5bfd4a48, 0xcfc000f9, 0xc3e05754, 0x5bfd5250, 0xcfc000f9, 0xc3e15e5c,\n    0x5bfc5b58, 0xcfc000f9, 0xc3e06764, 0x5bfd6260, 0xcfc000f9, 0xc3e16e6c, 0x5bfc6b68, 0xcfc000f9,\n    0xc3e17674, 0x5bfc7370, 0xcfc000f9, 0xc3e07f7c, 0x5bfd7a78, 0xcfc000f9, 0xc3e18684, 0x5bfc8380,\n    0xcfc000f9, 0xc3e08f8c, 0x5bfd8a88, 0xcfc000f9, 0xc3e09794, 0x5bfd9290, 0xcfc000f9, 0xc3e19e9c,\n    0x5bfc9b98, 0xcfc000f9, 0xc121fffe, 0x5911fef4, 0x14100000, 0x80000028, 0x00000000, 0x800004e8,\n    0x00000000, 0x8000ffe0, 0xc0004918, 0xd28000f8, 0xc2000000, 0xdf600038, 0x5e600080, 0x840002b2,\n    0x00000000, 0xc161fffe, 0x5955fffe, 0x14140000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0x00000000, 0x00000000, 0xc000480a, 0xca0000f8, 0xc0004912, 0xca4000f8, 0xc0004924, 0xca8000f8,\n    0xc000498c, 0xcac000f8, 0xc121fffe, 0x5911fef4, 0x14100000, 0x76250000, 0x76290000, 0x762d0000,\n    0x840001ea, 0xc0004918, 0xca4000f8, 0xc28001fe, 0x76290000, 0x5a640002, 0x6a254010, 0x5ee80000,\n    0x8400001a, 0x6aa54000, 0x80000010, 0xc62800f8, 0x62818008, 0xc0004918, 0xcf0000f8, 0xc161fffe,\n    0x5955fffe, 0x14140000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0xc000498c, 0xca4000f8, 0xc2000002, 0x6a310000, 0x7e010000, 0x76612000, 0xce4000f8, 0xc121fffe,\n    0x5911fef4, 0x14100000, 0x6f346000, 0x4771a000, 0x5b744c80, 0xc2800000, 0x58340006, 0xca800078,\n    0xc2c00000, 0x58340000, 0xcac000d8, 0xc2400000, 0x5834000a, 0xca420078, 0x6ea82000, 0x42e9e000,\n    0x6f2ca000, 0x42e56000, 0x5aec3680, 0xc3990040, 0xc7381c18, 0xc6f80060, 0x99006480, 0xdb9800f8,\n    0xdbd800f9, 0x00000000, 0xdea000f8, 0x46310000, 0x8400fd40, 0xc000495a, 0xc84000f8, 0x00000000,\n    0xc3c00002, 0x787c2000, 0xcc4000f8, 0xc0000838, 0xc3800000, 0xcb840028, 0x6c748000, 0x6c544000,\n    0x4355a000, 0x5b747e00, 0x5ef80000, 0x8400fca2, 0x58340004, 0xcb0000f8, 0x00000000, 0x00000000,\n    0xa7060020, 0x00000000, 0x5ef80002, 0x8400fc62, 0x5834000c, 0xc8800038, 0xc2000000, 0xc000082c,\n    0xca040028, 0x5a880002, 0xc2400000, 0xc0004958, 0xce4000f8, 0xb6280018, 0x00000000, 0xc2800000,\n    0x58340002, 0xc2000000, 0xca020008, 0xc0004956, 0xce8000f8, 0x5e600000, 0x84001ca2, 0x5e600002,\n    0x84004062, 0x00000000, 0x800021d0, 0xc0004958, 0xca0000f8, 0xc0004956, 0xca8000f8, 0x5e200000,\n    0x84000020, 0xc2500002, 0xc0000838, 0xce450800, 0x6c748000, 0x6c544000, 0x4355a000, 0x5b747e00,\n    0x5834000c, 0xc6900038, 0xcd000038, 0x8000fb38, 0xc2000000, 0xdf600038, 0x5e200080, 0x8400028a,\n    0x00000000, 0xc161fffe, 0x5955fffe, 0x14140000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0x00000000, 0x00000000, 0xc000480c, 0xca0000f8, 0xc0004910, 0xca4000f8, 0xc000492c, 0xca8000f8,\n    0xc000498e, 0xcac000f8, 0xc121fffe, 0x5911fef4, 0x14100000, 0x76250000, 0x76290000, 0x76e16000,\n    0x840001c2, 0xc0004926, 0xca4000f8, 0xc201fffe, 0x76e16000, 0x5a640002, 0x6ae50010, 0x5f200000,\n    0x8400001a, 0x6a250000, 0x80000010, 0xc6e000f8, 0x62014008, 0xc0004926, 0xce8000f8, 0xc161fffe,\n    0x5955fffe, 0x14140000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0xc000498e, 0xca4000f8, 0xc2000002, 0x6a290000, 0x7e010000, 0x76612000, 0xce4000f8, 0xc121fffe,\n    0x5911fef4, 0x14100000, 0x6eb4a000, 0x4769a000, 0x5b747600, 0x58340002, 0xc2000000, 0xca0000d8,\n    0x58340036, 0xc2400000, 0xca400078, 0x6eb0a000, 0x47298000, 0x5b303636, 0x5b300004, 0x6e642000,\n    0x4225e000, 0xc39a8024, 0xc7380060, 0xc6b81c18, 0x99006480, 0xdb9800f8, 0xdbd800f9, 0x00000000,\n    0xc2000000, 0xdf600038, 0x5e200080, 0x840002da, 0x00000000, 0xc161fffe, 0x5955fffe, 0x14140000,\n    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xc000490e, 0xca0000f8,\n    0xc000492a, 0xca4000f8, 0xc0004990, 0xcb0000f8, 0xc000498a, 0xcac000f8, 0xc121fffe, 0x5911fef4,\n    0x14100000, 0x77218000, 0x77258000, 0x8400021a, 0xc201fffe, 0x77218000, 0x5aec0002, 0x6b2d0010,\n    0x5ea00000, 0x8400001a, 0x6a2d0000, 0x80000010, 0xc72000f8, 0x62016008, 0xc000498a, 0xcec000f8,\n    0xc161fffe, 0x5955fffe, 0x14140000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0x00000000, 0xc0004990, 0xca4000f8, 0xc2000002, 0x6a2d0000, 0x7e010000, 0x76612000, 0xce4000f8,\n    0xc121fffe, 0x5911fef4, 0x14100000, 0x6ef4a000, 0x476da000, 0x5b747600, 0x58340010, 0xc2000000,\n    0xca0000d8, 0x58340008, 0xc2400000, 0xca420078, 0x5834000e, 0xc2800000, 0xca832010, 0xc3c00000,\n    0x47e48000, 0x6e644010, 0xc7e800fc, 0x42250000, 0x4229e000, 0xc39a8008, 0x58340008, 0xcb801038,\n    0x58340008, 0xc2800000, 0xca810010, 0x6ee0a000, 0x462d0000, 0x5a20000a, 0x5a203608, 0x42290000,\n    0xc6380060, 0xc6f81c18, 0x99006480, 0xdb9800f8, 0xdbd800f9, 0x00000000, 0xc000495c, 0xc84000f8,\n    0xc3400000, 0xc3c00002, 0x787c2000, 0xcc4000f8, 0x6c78a000, 0x4785c000, 0x5bb87600, 0x58380034,\n    0xcb410038, 0xc0000a28, 0xc3000000, 0xcb040028, 0xc0000a14, 0xc2c00000, 0x43358000, 0xcac40028,\n    0xc000490e, 0xca8000f8, 0x5eec0002, 0x472d8000, 0x8800f4c8, 0x6bc5e000, 0x76bd4000, 0x8400f4b0,\n    0x6c7ca000, 0x47c5e000, 0x5bfc7600, 0x583c0008, 0xc2000000, 0xca020078, 0xc00049aa, 0x00000000,\n    0xca8000f9, 0xca4000f8, 0xc0001008, 0xce8000f8, 0xc0001006, 0xce4000f8, 0x583c000a, 0xca4000f8,\n    0x00000000, 0xc000100a, 0xce4000f8, 0xc2400006, 0xc0001000, 0xce4000f8, 0xc2600982, 0x5a643b6e,\n    0xc0001002, 0xce4000f8, 0x583c000c, 0xca4000f8, 0x00000000, 0xc0001004, 0xce4000f8, 0x583c000e,\n    0xcb8000f8, 0x00000000, 0xc2400000, 0xc7a40078, 0xc2800000, 0xc7aae020, 0xdaa000f9, 0x583c0034,\n    0xcb8000f8, 0x00000000, 0xc2c00000, 0xc7ad0038, 0xc0004978, 0xcec000f8, 0xc0800000, 0xc7880038,\n    0xc3400000, 0xc7b60038, 0xc0004980, 0xcf4000f8, 0x4661c000, 0x43a9c000, 0xc2400000, 0xc000497c,\n    0xce4000f8, 0xad2c0001, 0xc2800000, 0x00000000, 0x80000010, 0xc2800002, 0xc0004976, 0xce8000f8,\n    0xc2c00000, 0xc34000a0, 0xdb5c00f9, 0xc3400002, 0xc000497a, 0xcf4000f8, 0x5f600000, 0x84000180,\n    0xde2800f9, 0xc6a000f8, 0x47a9c000, 0x583c0000, 0xc2800000, 0xca830038, 0xc0000a28, 0xc3000000,\n    0xcb040028, 0xc3400000, 0xc0004976, 0x46b18000, 0x8800006a, 0xcf4000f8, 0x58880002, 0xc3000000,\n    0xc0000a14, 0xcb040028, 0x00000000, 0x00000000, 0xb4b001a8, 0x00000000, 0xc0800000, 0x00000000,\n    0x80000188, 0xc0004980, 0xcb4000f8, 0x00000000, 0x00000000, 0x5af40002, 0xacec0080, 0x00000000,\n    0xc2c00000, 0xc000497a, 0xadec0001, 0x00000000, 0x00000000, 0xad2c007f, 0xc2800000, 0xce8000f8,\n    0x80000018, 0xc2800002, 0xce8000f8, 0x5f6c0000, 0x840000e8, 0x00000000, 0x8000ff00, 0x5f780082,\n    0x88000258, 0xc3000002, 0xc000497c, 0xcf0000f8, 0xc2800080, 0xc1000000, 0xdd110038, 0x46914000,\n    0x47a94000, 0x880001d8, 0x4391a000, 0xc0004980, 0xcf4000f8, 0x6f684010, 0x6f77c000, 0x6f77c010,\n    0xc0004840, 0x40280000, 0xca8000f8, 0xc3000000, 0x6f506000, 0x6a908010, 0xc5300038, 0xdb1c00f9,\n    0x8000fe30, 0xc3400000, 0xc0000a10, 0xcb440060, 0x6cb04000, 0x6f288000, 0x6f744000, 0x42b14000,\n    0x43694000, 0xc3400000, 0xc6b44060, 0xc0004000, 0x40340000, 0xc321e000, 0xcf0000f8, 0x5aa80008,\n    0x42ad4000, 0xc3400000, 0xc6b44060, 0xc0004000, 0x40340000, 0xca4000f8, 0xc3000000, 0xc6f00008,\n    0xc1400000, 0xddd40039, 0x6f306000, 0xc13001fe, 0x69308010, 0x7d008000, 0x76512000, 0x6d570000,\n    0x6970a010, 0x42552000, 0xce4000f8, 0x5aa80002, 0x5aec0002, 0xacec0080, 0x00000000, 0xc2c00000,\n    0x5f6c0000, 0x84000118, 0x00000000, 0x80000040, 0x4391a000, 0x5f740080, 0xc0004980, 0xcf4000f8,\n    0xc3000004, 0xc000497a, 0xcf0000f8, 0x58880002, 0xc3400000, 0xc0000a14, 0xcb440028, 0x00000000,\n    0x00000000, 0xb4b40018, 0x00000000, 0xc0800000, 0xc3400000, 0xc0000a10, 0xcb440060, 0x6cb04000,\n    0x6f248000, 0x6f744000, 0x42712000, 0x43654000, 0xc3400000, 0xc6b44060, 0xc0004000, 0x40340000,\n    0xc3201e00, 0xcf0000f8, 0x5aa80008, 0x42ad4000, 0xc000100c, 0xcb4000f8, 0xc3000000, 0x00000000,\n    0xc7340060, 0xc300fffe, 0xc7341070, 0xcf4000f8, 0xc000100e, 0xcb4000f8, 0xc3003608, 0x00000000,\n    0xc7340060, 0xc300fffe, 0xc7341070, 0xcf4000f8, 0xc0001010, 0xcb4000f8, 0xc3000002, 0x00000000,\n    0xc7341a00, 0xc7341800, 0xc3000000, 0xc7341900, 0xc6b40070, 0xcf4000f8, 0xc0004982, 0xce8000f8,\n    0x6c64a000, 0x46452000, 0x5a64000a, 0xc0001012, 0xcb4000f8, 0xc2800002, 0x00000000, 0xc6740260,\n    0xc6340008, 0xc000497c, 0xcb0000f8, 0xc6b41800, 0xc6b41b00, 0xc6b41c00, 0xc6b41d00, 0xc7341e00,\n    0xdd6800f9, 0x7e814000, 0x6eab2010, 0x76b14000, 0xc6b41f00, 0xc2800000, 0xc6b41900, 0xc3000080,\n    0x472d8000, 0xc0004982, 0xc90000f8, 0x47394000, 0x88000102, 0x41388000, 0xcd0000f8, 0xc7b41038,\n    0xc0004994, 0xce8000f8, 0xde1000f9, 0x45208000, 0x840000b0, 0xc1000000, 0xdd110038, 0x41388000,\n    0x412c8000, 0x5d100080, 0xc0004980, 0xcd0000f8, 0xc1000002, 0xc000497c, 0xcd0000f8, 0xc5341e00,\n    0xdd5000f9, 0x7d008000, 0xc5373f00, 0xc000497a, 0xc90000f8, 0x42390000, 0x43adc000, 0x59100002,\n    0xcd0000f8, 0x80000050, 0x42390000, 0x80000040, 0xc7341038, 0x41308000, 0xcd0000f8, 0x42310000,\n    0xc1000000, 0xc0004994, 0xcd0000f8, 0xc0001012, 0xcf4000f8, 0xc000493c, 0xce0000f8, 0xc0004984,\n    0xcf8000f8, 0xc000497a, 0xca4000f8, 0xc000497c, 0xca8000f8, 0x6c7ca000, 0x47c5e000, 0x5bfc7600,\n    0xc0004976, 0xcac000f8, 0xc0004978, 0xca0000f8, 0x5eec0002, 0x8400008a, 0x42250000, 0xc2400000,\n    0xc000497a, 0xce4000f8, 0x583c0000, 0xc2c00000, 0xcac30038, 0x00000000, 0x00000000, 0x46e16000,\n    0x8800001a, 0x00000000, 0xad280002, 0xc000497a, 0xce0000f8, 0xc2000000, 0x5fa80000, 0x840001da,\n    0x00000000, 0x6c508000, 0xc0004880, 0x40100000, 0x58000018, 0xc90000f8, 0x00000000, 0x00000000,\n    0x59100002, 0xcd0000f8, 0x583c000e, 0xc2c00000, 0xcac00078, 0xc1000000, 0xdd532201, 0x42d16000,\n    0x6c508000, 0xc0004880, 0x40100000, 0x5800001a, 0xc90000f8, 0x00000000, 0x00000000, 0x412c8000,\n    0xcd0000f8, 0x99006510, 0xd85800f8, 0xdbd800f9, 0x00000000, 0x99006258, 0xc000491c, 0xc1400000,\n    0xc9420048, 0xc000491c, 0x99006710, 0xc94000f9, 0xc98000f8, 0x00000000, 0x99006480, 0xd95800f8,\n    0xd99800f9, 0x00000000, 0xc161fffe, 0x5955fffe, 0x14140000, 0x00000000, 0x00000000, 0x00000000,\n    0x00000000, 0x00000000, 0x00000000, 0x98c060d0, 0xd85800f8, 0xdbd800f9, 0xc45800f8, 0xc121fffe,\n    0x5911fef4, 0x14100000, 0xade80003, 0xc000493c, 0xcb4000f8, 0x00000000, 0xc3000000, 0xc7701078,\n    0x80000010, 0xc3000000, 0x583c0008, 0xcf021078, 0x6e210000, 0x583c0034, 0xce010838, 0xc0004980,\n    0xcb8000f8, 0x583c0034, 0x00000000, 0x6fba0000, 0xcf821038, 0xc000490e, 0xca0000f8, 0xc2c00002,\n    0x6ac56000, 0x722d0000, 0xce0000f8, 0x00000000, 0x00000000, 0x00000000, 0xa8e2ffe8, 0x00000000,\n    0xc1220002, 0xd90c00f8, 0x5fa80000, 0x84000712, 0xc00049a8, 0xca0000f8, 0x583c000a, 0x00000000,\n    0xce0000f8, 0xc221fffe, 0x5a21fffe, 0x583c000c, 0xce0000f8, 0xc0001004, 0xca0000f8, 0x00000000,\n    0x583c0012, 0x7e010000, 0xce0000f8, 0xa97000e1, 0x00000000, 0x00000000, 0xa97200c9, 0xc0001010,\n    0xc2740000, 0xce435a00, 0x6c64a000, 0x46452000, 0x5a64000a, 0x6e644000, 0xc0001012, 0xce400070,\n    0xc2600008, 0xce421038, 0xc27e0002, 0xce43ff00, 0xc2760002, 0xce437b00, 0x00000000, 0x00000000,\n    0x00000000, 0x00000000, 0x00000000, 0xa8e2ffe8, 0x00000000, 0xc1220002, 0xd90c00f8, 0xc1000000,\n    0xdd110038, 0x5d100000, 0x84000412, 0xc0004982, 0xca0000f8, 0xc0004984, 0xca4000f8, 0xc2800000,\n    0xc361fffe, 0x5b75fffe, 0xa96a001b, 0xdfec00f8, 0xc6ec1078, 0x7af56000, 0x6c40a000, 0x44040000,\n    0x58007600, 0x58000014, 0xcec000f8, 0xa972001b, 0x5c000002, 0xcec000f8, 0xc0001010, 0xc2f40002,\n    0xcec35a00, 0x6c6ca000, 0x46c56000, 0x5aec000a, 0x6eec4000, 0xc0001012, 0xcec00070, 0xc0004994,\n    0xc98000f8, 0xc1400000, 0xdd150038, 0xc55c00f8, 0x45948000, 0x00000000, 0xc59c00fc, 0x5d1c0000,\n    0x840000d2, 0xc0001012, 0xc5d01038, 0xcd021038, 0xc2f60002, 0xcec37b00, 0x00000000, 0x00000000,\n    0x00000000, 0x00000000, 0x00000000, 0xa8e2ffe8, 0x00000000, 0xc1220002, 0xd90c00f8, 0x45948000,\n    0x88000052, 0xc0004994, 0xcd0000f8, 0xc0004980, 0xcbc000f8, 0x42150000, 0xc0004982, 0xce0000f8,\n    0x5ffc0000, 0x84000218, 0x58880002, 0xc3800000, 0xc0000a14, 0xcb840028, 0xc3c00000, 0xc0000a10,\n    0xb4b80018, 0x00000000, 0xc0800000, 0xcbc40060, 0x6cb84000, 0x6fac8000, 0x6ffc4000, 0x42f96000,\n    0x43ed0000, 0xc3400000, 0xc6344060, 0xc0004000, 0x40340000, 0xc2a1e000, 0xce8000f8, 0x5a200008,\n    0xc0004980, 0xcbc000f8, 0xc3400000, 0xc0004840, 0x6ff84010, 0xc7f40008, 0x40380000, 0xcb8000f8,\n    0xc2800000, 0x6f506000, 0x6b908010, 0xc52c1838, 0xc3400000, 0xc6344060, 0xc0004000, 0x40340000,\n    0xcec000f8, 0x5a200002, 0x5ffc0000, 0x84000092, 0xc0001010, 0xc62c0070, 0xcec00070, 0xc0001012,\n    0xc7ec1038, 0xcec21038, 0xc2f60002, 0xcec37b00, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0x00000000, 0xa8e2ffe8, 0x00000000, 0xc1220002, 0xd90c00f8, 0xc0004994, 0xc100007e, 0x453c8000,\n    0xcd0000f8, 0x423d0000, 0xc0004982, 0xce0000f8, 0xc0004994, 0xca0000f8, 0xc0004980, 0xca4000f8,\n    0x5e200000, 0x8400015a, 0xc2000000, 0xc2800000, 0x5a640002, 0xc6684028, 0xc0004982, 0xcb0000f8,\n    0xc0004000, 0xc2c00000, 0xc72c4060, 0x402c0000, 0x6e67c000, 0x6e67c010, 0x5ee40002, 0x8400003a,\n    0x5ee40004, 0x8400004a, 0x5ee40006, 0x8400005a, 0x00000000, 0x80000060, 0xce0000b8, 0x5aa80002,\n    0x5b300006, 0x80000040, 0xce000078, 0x5aa80002, 0x5b300004, 0x80000020, 0xce000038, 0x5aa80002,\n    0x5b300002, 0x5ee80020, 0x84000052, 0xc0004000, 0xc2c00000, 0xc72c4060, 0x402c0000, 0xce0000f8,\n    0x5aa80002, 0x5b300008, 0x8000ffb8, 0x00000000, 0x80000040, 0x583c000a, 0xd7c000f8, 0xc0001004,\n    0xca4000f8, 0x00000000, 0x583c000c, 0xce4000f8, 0xc000497a, 0xca4000f8, 0xc2800002, 0xc0000a28,\n    0xc6780928, 0xc6b80800, 0xcf850830, 0x6c7ca000, 0x47c5e000, 0x5bfc7600, 0x583c0034, 0xc4900038,\n    0xcd000038, 0x8000e418, 0x6c6c8000, 0x6c544000, 0x42d56000, 0x5aec7e00, 0xc0000824, 0xca0400f8,\n    0x6ca48000, 0x42492000, 0xc3000000, 0xc3400000, 0x42250000, 0x58204000, 0xca4000f8, 0x5a200002,\n    0xda2400f9, 0xc2800000, 0xc000495e, 0xce8000f8, 0xda6000f8, 0xc2800000, 0xc66b0038, 0xdaa800f8,\n    0x582c0010, 0x6f206010, 0x40200000, 0xd82800f9, 0xca0000f8, 0xc2400000, 0xc7240010, 0x6e644000,\n    0xda6400f8, 0x6a254010, 0xc3c00000, 0xc6bc0018, 0xc3800000, 0xdea000f8, 0x5e60001e, 0x8400002a,\n    0x5e6001e0, 0x8400001a, 0x00000000, 0x80000080, 0xc7f800f8, 0x5e7c0008, 0x8400006a, 0x5bbc0002,\n    0x5e780008, 0x84000028, 0x5b740002, 0xc0004960, 0xcf0000f8, 0x80000030, 0x5e780006, 0x88000022,\n    0xc2800002, 0xc000495e, 0xce8000f8, 0xde8000f9, 0xca8000f8, 0xde6000f8, 0xc240001e, 0x6a612000,\n    0x7e412000, 0x76a54000, 0x6ba12000, 0x72a54000, 0xce8000f8, 0x5e300080, 0x840000ba, 0xc2000000,\n    0xc7200008, 0x5e600000, 0x84000058, 0xde6000f9, 0x58204000, 0xca4000f8, 0x5a200002, 0xda2400f9,\n    0xc2800000, 0xc66b0038, 0xdaa800f8, 0xda6000f8, 0x80000038, 0xc2800000, 0x6e206000, 0xde2400f8,\n    0x6a610000, 0xc62b0038, 0xdaa800f8, 0x5b300002, 0x8000fde0, 0xc2000000, 0x582c0020, 0xca020078,\n    0x00000000, 0xc2400000, 0x5a200002, 0xc6241078, 0xce421078, 0xc000480e, 0xca8000f8, 0x5e740000,\n    0x84000160, 0x46a12000, 0x8800e048, 0xc2400000, 0xc0000808, 0xca440010, 0x582c0010, 0xc1400000,\n    0xcd4000f9, 0xcd4000f9, 0xcd4000f9, 0xcd4000f9, 0xcd4000f9, 0xcd4000f9, 0xcd4000f9, 0xcd4000f9,\n    0xcd400018, 0x582c0020, 0xce021078, 0xc2000010, 0x5a640002, 0xb6240018, 0x00000000, 0xc2400000,\n    0xc6600010, 0xc0000808, 0xce040010, 0xc0004956, 0xca4000f8, 0xc11c0000, 0xc000082c, 0xcd05ce00,\n    0xc6600928, 0xc2400000, 0xc6600028, 0xc0000838, 0xce0400f8, 0xc2400002, 0xc0004958, 0xce4000f8,\n    0xc11c0002, 0xc000082c, 0xcd05ce00, 0x8000df00, 0xc000495e, 0xca0000f8, 0x5e740002, 0x8400dee0,\n    0x5e200000, 0x8400ded0, 0xc0004960, 0xca4000f8, 0xc2200004, 0x582c0002, 0xce021008, 0xc2000082,\n    0x46250000, 0xc6280030, 0xc0000810, 0xce840030, 0x99006ba8, 0x582c0002, 0xc94000f8, 0xc1a20000,\n    0x5e640000, 0x8400fed0, 0x00000000, 0x8000de40, 0x6c6c8000, 0x6c544000, 0x42d56000, 0x5aec7e00,\n    0xc000487c, 0xc80400f8, 0x00000000, 0x00000000, 0x40080000, 0xcb8000f8, 0xc42400f8, 0x00000000,\n    0xa78601a0, 0xc3c00000, 0xc2000000, 0x582c000c, 0xca010038, 0x6c508000, 0xc0004880, 0x40100000,\n    0x58000016, 0xc90000f8, 0x00000000, 0x00000000, 0x59100002, 0xcd0000f8, 0x5a200002, 0x582c000c,\n    0xc6100838, 0xcd010838, 0x5e600002, 0x84000020, 0xc2200004, 0x582c0002, 0xce021008, 0x5e600008,\n    0x84000060, 0xc2200002, 0x582c0002, 0xce021008, 0x582c000c, 0xcfc10838, 0xc2220002, 0xc0000a14,\n    0xce063100, 0xc22001a2, 0xc0000a1c, 0xce061038, 0x6c6c8000, 0x6c544000, 0x42d56000, 0x5aec7e00,\n    0x582c0004, 0xcb0000f8, 0xc3400000, 0x00000000, 0xa7060028, 0xcf406300, 0xc3100002, 0xc0000838,\n    0xcf050800, 0x582c000c, 0xcf421000, 0x8000dc40, 0x582c000c, 0xcfc10838, 0xc2000000, 0xc7a06010,\n    0x5e200000, 0x84001c08, 0x6c6c8000, 0x6c544000, 0x42d56000, 0x5aec7e00, 0xc000487c, 0xc80400f8,\n    0x00000000, 0x00000000, 0x40080000, 0xcb8000f8, 0xc42400f8, 0x00000000, 0xc2800000, 0xc3400000,\n    0xc7b5c030, 0xc0004970, 0xcf4000f8, 0xc2400000, 0xc7a4e030, 0xc000496c, 0xce4000f8, 0xc3000000,\n    0xc7b00010, 0xc3c00004, 0xc000496e, 0xcfc000f8, 0x582c000c, 0xca0000f8, 0xc2400002, 0xc0004964,\n    0xce4000f8, 0xa6200372, 0x00000000, 0x5e700004, 0x840000ea, 0x5e700006, 0x84000080, 0xc2000002,\n    0x582c0002, 0xce000000, 0xc0000a14, 0xce863100, 0x6c508000, 0xc0004880, 0x40100000, 0x58000014,\n    0xc90000f8, 0x00000000, 0x00000000, 0x59100002, 0xcd0000f8, 0x80001a58, 0x5e70000a, 0x84000040,\n    0xc2000000, 0x582c0002, 0xce000000, 0xc2220002, 0xc0000a14, 0xce063100, 0x8000ff70, 0x5e700008,\n    0x84000228, 0xc2200002, 0x582c000c, 0xce021000, 0x6c508000, 0xc0004880, 0x40100000, 0x58000012,\n    0xc90000f8, 0x00000000, 0x00000000, 0x59100002, 0xcd0000f8, 0x5e340002, 0x6c508000, 0xc0004880,\n    0x40100000, 0x58000010, 0xc90000f8, 0x00000000, 0x00000000, 0x41208000, 0xcd0000f8, 0xc0000a14,\n    0xce863100, 0xc0004970, 0xcb4000f8, 0x6c6c8000, 0x6c544000, 0x42d56000, 0x5aec7e00, 0x582c000e,\n    0xc4900038, 0xcd000038, 0x582c000e, 0xc7500838, 0xcd010838, 0xc2800000, 0x582c0004, 0xce821078,\n    0x582c0004, 0xce800000, 0xc00049a0, 0xca4000f8, 0x00000000, 0x582c0006, 0xce4000f8, 0xc261fffe,\n    0x5a65fffe, 0x582c0024, 0xce4000f8, 0xc2060002, 0x582c0004, 0xce006300, 0xc2400002, 0xc0004958,\n    0xce4000f8, 0xc0004878, 0xc80400f8, 0x6c908000, 0x41088000, 0x40100000, 0x58000020, 0xc90000f8,\n    0x582c0026, 0x00000000, 0xcd0000f8, 0x800017e8, 0x00000000, 0x6c508000, 0xc0004880, 0x40100000,\n    0x58000016, 0xc90000f8, 0x00000000, 0x00000000, 0x59100002, 0xcd0000f8, 0x8000faf0, 0x5e700000,\n    0x840000c0, 0xc3400082, 0xc0004970, 0xcf4000f8, 0xc2400080, 0xc000496c, 0xce4000f8, 0xc3c00002,\n    0xc000496e, 0xcfc000f8, 0xc2400000, 0xc0004964, 0xce4000f8, 0xc0004878, 0xc80400f8, 0x6c908000,\n    0x41088000, 0x40100000, 0x58000020, 0xc90000f8, 0x582c0026, 0x00000000, 0xcd0000f8, 0x80000078,\n    0x5e700002, 0x84000058, 0xc3400082, 0xc0004970, 0xcf4000f8, 0xc3c00004, 0xc000496e, 0xcfc000f8,\n    0xc2200000, 0x582c000c, 0xce021000, 0x80000030, 0x5e700004, 0x8400fe80, 0xc2600002, 0x582c000c,\n    0xce421000, 0xc0000a14, 0xce863100, 0xc000496c, 0xca4000f8, 0x6c508000, 0xc0004880, 0x40100000,\n    0x58000012, 0xc90000f8, 0x00000000, 0x00000000, 0x59100002, 0xcd0000f8, 0xc000496e, 0xcbc000f8,\n    0x00000000, 0x00000000, 0x477d0000, 0x46250000, 0x6c508000, 0xc0004880, 0x40100000, 0x58000010,\n    0xc90000f8, 0x00000000, 0x00000000, 0x41208000, 0xcd0000f8, 0x6c6c8000, 0x6c544000, 0x42d56000,\n    0x5aec7e00, 0x582c0004, 0xca0000f8, 0x00000000, 0x00000000, 0xa60014e2, 0x00000000, 0x6c6c8000,\n    0x6c544000, 0x42d56000, 0x5aec7e00, 0xc3000000, 0x582c0004, 0xcf006300, 0x582c0000, 0xcb002010,\n    0xc3c00000, 0x582c0004, 0xcbc20078, 0xc000491a, 0xcf0000f8, 0xc000493c, 0xcfc000f8, 0x582c0008,\n    0xcb8000f8, 0x582c000a, 0xca4000f8, 0xc0004930, 0xcf8000f8, 0xc0004932, 0xce4000f8, 0x5ffc0000,\n    0x840001f0, 0x00000000, 0xa7be0102, 0xc2800000, 0x6f206000, 0x46310000, 0x5a204c80, 0x5820000c,\n    0xca800020, 0x00000000, 0x00000000, 0x5ea80000, 0x84000112, 0x00000000, 0xc161fffe, 0x5955fffe,\n    0x14140000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x99005f70,\n    0xc000491a, 0xc94000f8, 0x00000000, 0xc121fffe, 0x5911fef4, 0x14100000, 0xc0004930, 0xcb8000f8,\n    0xc0004932, 0xca4000f8, 0xc4781108, 0xc0004930, 0xcf8000f8, 0x582c0008, 0xcf8000f8, 0x582c000a,\n    0xce4000f8, 0xc7b6e108, 0x582c0004, 0xcf402108, 0x80000090, 0x00000000, 0x6c508000, 0xc0004880,\n    0x40100000, 0x5800000c, 0xc90000f8, 0x00000000, 0x00000000, 0x59100002, 0xcd0000f8, 0xc2000002,\n    0x582c0004, 0xce000000, 0xc0000838, 0xc2500002, 0xce450800, 0x80001220, 0x6c7c8000, 0x6c544000,\n    0x43d5e000, 0x5bfc7e00, 0x583c0006, 0xca0000f8, 0xc00049a2, 0x00000000, 0xca8000f9, 0xca4000f8,\n    0xc0001008, 0xce8000f8, 0xc0001006, 0xce4000f8, 0xc000100a, 0xce0000f8, 0xc2400006, 0xc0001000,\n    0xce4000f8, 0xc2600982, 0x5a643b6e, 0xc0001002, 0xce4000f8, 0x583c0024, 0xca4000f8, 0x00000000,\n    0xc0001004, 0xce4000f8, 0xc0004862, 0xc2000000, 0xca000078, 0xc360fffe, 0xc0004862, 0xce0000f8,\n    0xc0000824, 0xcb440060, 0x00000000, 0xc000100e, 0xcf4000f8, 0xc3803800, 0xc2400200, 0x6e644000,\n    0xc6781070, 0xc000100c, 0xcf8000f8, 0xc3200a00, 0xc0001010, 0xcf031810, 0xc2e06200, 0xc0001012,\n    0xcec31838, 0xc2000000, 0x583c0004, 0xca002008, 0xc2800000, 0xc0004966, 0xce0000f8, 0xc62400f8,\n    0xc3000000, 0xc000496a, 0xcf0000f8, 0xc0004974, 0xcf0000f8, 0xc000493c, 0xcb4000f8, 0x583c000e,\n    0x00000000, 0x5f740000, 0x84000180, 0xc3400000, 0xcb410038, 0xc3000002, 0xc000496a, 0x5fb40080,\n    0x84000152, 0xcf0000f8, 0x583c000e, 0xc2c00000, 0xcac00038, 0xc3800080, 0x47b5c000, 0xc0004974,\n    0xcf8000f8, 0xc0001012, 0x6fba0000, 0xcf821038, 0x6fba0010, 0x43a5c000, 0x5b380006, 0x6f284010,\n    0xc7a40008, 0x6eec4000, 0x6ef08000, 0x432d8000, 0x43358000, 0x5b300008, 0xc0001012, 0xc7100070,\n    0xcd000070, 0xc2000200, 0xc2c00000, 0xdf6d0048, 0x462d6000, 0x46e96000, 0x8800ffe2, 0xc2000000,\n    0xc0004862, 0xca000260, 0x00000000, 0x583c0004, 0xca002008, 0xc3360002, 0xc0001010, 0xce000070,\n    0xc0001012, 0xcf037b00, 0xc0004974, 0xcb8000f8, 0x00000000, 0x00000000, 0x5fb80000, 0x84000042,\n    0x00000000, 0x00000000, 0x00000000, 0xa8e2ffe8, 0x00000000, 0xc1220002, 0xd90c00f8, 0xc000496c,\n    0xcac000f8, 0x00000000, 0x00000000, 0x426dc000, 0x5b380006, 0x6f304010, 0xc7a40008, 0xc0004968,\n    0xce4000f8, 0xc000496e, 0xcb4000f8, 0x6ca44000, 0x6e608000, 0x42250000, 0x5a200006, 0x42350000,\n    0xc0001012, 0xc6100070, 0xcd000070, 0x6eee0000, 0xcec21038, 0xc2000200, 0xc2c00000, 0xdf6d0048,\n    0x462d6000, 0x42b14000, 0x46e96000, 0x8800ffda, 0xc000493c, 0xcb4000f8, 0xc0000838, 0xc3100002,\n    0x5f740000, 0x84000060, 0xcf050800, 0xc0004974, 0xcb8000f8, 0x00000000, 0x00000000, 0x5fb80000,\n    0x8400006a, 0xc0001012, 0xc3360002, 0xcf037b00, 0x800000a0, 0x583c0022, 0xcb4000f8, 0xc0004862,\n    0xca0000f8, 0x00000000, 0xc0007800, 0x40200000, 0xcf4000f8, 0xc2000000, 0xc0004862, 0xca000260,\n    0x00000000, 0x583c0004, 0xca002008, 0xc3360002, 0xc0001010, 0xce000070, 0xc0001012, 0xcf037b00,\n    0xc0004968, 0xcbc000f8, 0xc0004964, 0xca4000f8, 0xc7e000f8, 0x00000000, 0x5e640000, 0x84000012,\n    0xc2000000, 0xc0004974, 0xca4000f8, 0xc000496c, 0xca8000f8, 0xc000493c, 0xcb8000f8, 0x42698000,\n    0x00000000, 0x43b1a000, 0x5ef40080, 0x8800019a, 0xc0004966, 0xcac000f8, 0x6c648000, 0x6c544000,\n    0x42552000, 0x5a647e00, 0x58240000, 0x436da000, 0x4761a000, 0xc2400000, 0xca420078, 0x00000000,\n    0x00000000, 0x46752000, 0x88000122, 0x432d8000, 0x47218000, 0x88000010, 0xc3000000, 0x5b300006,\n    0x6f304010, 0xc000493a, 0xcf0000f8, 0xc0004932, 0xc2400000, 0xca4000d8, 0x00000000, 0x6fb84010,\n    0x42792000, 0xc000491e, 0xce4000f8, 0xc0004862, 0xca8000f8, 0x00000000, 0xc2c0000a, 0xc6e80d70,\n    0xc7281048, 0xc000491c, 0xce8000f8, 0x6c708000, 0x6c544000, 0x43158000, 0x5b307e00, 0x6f760000,\n    0x58300004, 0xcf421078, 0x6ffc2000, 0x58300004, 0xcfc02108, 0x800000d0, 0x6c708000, 0x6c544000,\n    0x43158000, 0x5b307e00, 0xc2800002, 0x58300004, 0xce800000, 0x6c508000, 0xc0004880, 0x40100000,\n    0x5800000e, 0xc90000f8, 0x00000000, 0x00000000, 0x59100002, 0xcd0000f8, 0x00000000, 0x00000000,\n    0x00000000, 0xa8e2ffe8, 0x00000000, 0xc1220002, 0xd90c00f8, 0x80000920, 0x00000000, 0x00000000,\n    0x00000000, 0x00000000, 0xa8e2ffe8, 0x00000000, 0xc1220002, 0xd90c00f8, 0xc0004964, 0xca0000f8,\n    0x6c7c8000, 0x6c544000, 0x43d5e000, 0x5bfc7e00, 0xdfe400f8, 0x5e200002, 0x84000608, 0x00000000,\n    0x583c0004, 0xc2800000, 0xca820078, 0xc0004930, 0xcac000f8, 0x00000000, 0x00000000, 0x6eece000,\n    0x6eefc010, 0x46aca000, 0xc1000000, 0xdd500039, 0x6d106010, 0x4550a000, 0xc1000000, 0xdd514201,\n    0x4550c000, 0xa95000f1, 0xc00049a6, 0xca0000f8, 0xa94a0023, 0x00000000, 0x6e660000, 0x6e660010,\n    0x46612000, 0x840000b2, 0x00000000, 0x6c508000, 0xc0004880, 0x40100000, 0x58000004, 0xc90000f8,\n    0x00000000, 0x00000000, 0x59100002, 0xcd0000f8, 0x6c508000, 0xc0004880, 0x40100000, 0x58000006,\n    0xc90000f8, 0x00000000, 0x00000000, 0x41148000, 0xcd0000f8, 0x80000720, 0x00000000, 0xa95203c1,\n    0xc0001004, 0xcb8000f8, 0xc3400000, 0xdd740039, 0x5f740000, 0x840000d0, 0xc1218e08, 0x5911baf6,\n    0x45388000, 0x84000372, 0x00000000, 0x6c508000, 0xc0004880, 0x40100000, 0x58000008, 0xc90000f8,\n    0x00000000, 0x00000000, 0x59100002, 0xcd0000f8, 0x6c508000, 0xc0004880, 0x40100000, 0x5800000a,\n    0xc90000f8, 0x00000000, 0x00000000, 0x41148000, 0xcd0000f8, 0x80000620, 0x00000000, 0xc000496c,\n    0xcb0000f8, 0x583c0026, 0xcac000f8, 0xc0004878, 0xc80400f8, 0x6c908000, 0x41088000, 0x40100000,\n    0x58000002, 0xca8000f8, 0x00000000, 0x00000000, 0x6ea90000, 0x5d300008, 0x8800004a, 0x59300002,\n    0xc3000000, 0xc5300008, 0x6d104010, 0x40100000, 0xca8000f8, 0x5c000002, 0xcac000f8, 0x5d300000,\n    0x8400003a, 0x6f246000, 0x6ae56000, 0xc1000040, 0x45252000, 0x6aa54010, 0x42e96000, 0x583c0026,\n    0xcec000f8, 0xc1218e08, 0x5911baf6, 0xc0001004, 0xcd0000f8, 0x593c0026, 0xc000100e, 0xcd000060,\n    0xc1340000, 0xc0001010, 0xcd035a00, 0xc1200008, 0xa94a0023, 0xc0001012, 0xc1200004, 0x59100004,\n    0xcd0000b8, 0xc1360002, 0xcd037b00, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0xa8e2ffe8, 0x00000000, 0xc1220002, 0xd90c00f8, 0xc0001004, 0xc90000f8, 0x00000000, 0x00000000,\n    0x45388000, 0x840000b2, 0x00000000, 0x6c508000, 0xc0004880, 0x40100000, 0x58000008, 0xc90000f8,\n    0x00000000, 0x00000000, 0x59100002, 0xcd0000f8, 0x6c508000, 0xc0004880, 0x40100000, 0x5800000a,\n    0xc90000f8, 0x00000000, 0x00000000, 0x41148000, 0xcd0000f8, 0x80000360, 0x00000000, 0x6c508000,\n    0xc0004880, 0x40100000, 0x58000000, 0xc90000f8, 0x00000000, 0x00000000, 0x59100002, 0xcd0000f8,\n    0x6c508000, 0xc0004880, 0x40100000, 0x58000002, 0xc90000f8, 0x00000000, 0x00000000, 0x41148000,\n    0xcd0000f8, 0xc0004930, 0xcd800078, 0xc3000000, 0x583c0008, 0xcf0000f8, 0x80000038, 0xc0001004,\n    0xca0000f8, 0x583c0006, 0xce4000f8, 0x583c0024, 0xce0000f8, 0xc0004862, 0xc2000000, 0xca000078,\n    0xc000493a, 0xca4000f8, 0x00000000, 0x00000000, 0x42254000, 0x5ee80200, 0x88000012, 0xc6e800f8,\n    0xc0004000, 0x58003800, 0x40280000, 0xcb8000f8, 0x00000000, 0x583c0022, 0xcf8000f8, 0xc0004862,\n    0xce800078, 0xc0001406, 0xcac000f8, 0xc2800002, 0x00000000, 0xc66c1048, 0xc6ac0a00, 0xcec000f8,\n    0xc2000000, 0xdf600038, 0x5e600080, 0x8400ffea, 0xc000491c, 0xca4000f8, 0xc000491e, 0xca8000f8,\n    0x99006480, 0xda5800f8, 0xda9800f9, 0x00000000, 0xc0004964, 0xcbc000f8, 0x00000000, 0x00000000,\n    0x5ffc0000, 0x84000102, 0xc2000000, 0xdf610048, 0x5e6001fe, 0x8800ffe8, 0xc000491a, 0xc98000f8,\n    0xc0004862, 0xc94000f8, 0x6d9c6000, 0x45d8e000, 0x59dc4c80, 0x990062e0, 0xd95800f8, 0xd99800f9,\n    0xd9d400f8, 0x99006258, 0xc000491c, 0xc1400000, 0xc9420048, 0xc2000000, 0xdf600038, 0x5e600080,\n    0x8400ffea, 0xc000491c, 0xca4000f8, 0xc000491e, 0xca8000f8, 0x99006480, 0xda5800f8, 0xda9800f9,\n    0x00000000, 0xc0004970, 0xcb4000f8, 0x00000000, 0x00000000, 0x5e740082, 0x8400e6d8, 0x00000000,\n    0x8000c018, 0x00000000, 0x6c508000, 0xc0004880, 0x40100000, 0x58000016, 0xc90000f8, 0x00000000,\n    0x00000000, 0x59100002, 0xcd0000f8, 0x8000e308, 0x6c6c8000, 0x6c544000, 0x42d56000, 0x5aec7e00,\n    0xc000487c, 0xc80400f8, 0x00000000, 0x00000000, 0x40080000, 0xca0000f8, 0xc42400f8, 0x00000000,\n    0xa60600f8, 0xc3c00000, 0xc2000000, 0x582c000c, 0xca010038, 0x00000000, 0x00000000, 0x5a200002,\n    0xc6100838, 0xcd010838, 0x5e60000e, 0x8400bf00, 0xc2200000, 0x582c0002, 0xce021008, 0x582c000c,\n    0xcfc10838, 0x582c0020, 0xcfc21078, 0x582c0010, 0xc1400000, 0xcd4000f9, 0xcd4000f9, 0xcd4000f9,\n    0xcd4000f9, 0xcd4000f9, 0xcd4000f9, 0xcd4000f9, 0xcd4000f9, 0xcd400018, 0x8000be68, 0xc2200004,\n    0x582c0002, 0xce021008, 0x582c000c, 0xcfc10838, 0x99006ba8, 0x582c0002, 0xc94000f8, 0xc1a20000,\n    0x8000be18, 0xc3e1fffe, 0x597dfffe, 0x593dfef4, 0x94000001, 0x00000000, 0x00000000, 0x00000000,\n    0xc0800000, 0xdf4b0038, 0xc0004900, 0xcb8000f8, 0xc2000000, 0xc000490a, 0xa78000d0, 0xcbc000f8,\n    0xc1000000, 0xd90000f9, 0xc1000002, 0xd90c00f8, 0x6ff46000, 0x477da000, 0x5b744c80, 0xc2400000,\n    0x58340004, 0xca400078, 0xc0004900, 0xce000000, 0x5a640002, 0x58340004, 0xc6500078, 0xcd000078,\n    0xc0004914, 0xca4000f8, 0xc2000002, 0x6a3d0000, 0x72612000, 0xce4000f8, 0xc0000408, 0xce0000f8,\n    0xa78200c8, 0xc0004908, 0xcbc000f8, 0xc1000000, 0xd90000f9, 0xc1000002, 0xd90c00f8, 0x6ff4a000,\n    0x477da000, 0x5b747600, 0xc2800000, 0x58340006, 0xca800078, 0xc2000000, 0xc0004900, 0xce002100,\n    0x5ea80002, 0x58340006, 0xc6900078, 0xcd000078, 0x5a7c0020, 0xc2000002, 0x6a250000, 0xc0000408,\n    0xce0000f8, 0xdca800f9, 0x5ea80000, 0x8400abd0, 0x00000000, 0xa4800230, 0x00000000, 0xc3c00000,\n    0xc000140e, 0xcbc00018, 0xc3400000, 0xc2400000, 0x6ff86000, 0x47bdc000, 0x5bb84c80, 0x58380008,\n    0xcb400078, 0x58380006, 0xca400078, 0x5f740002, 0x58380008, 0xc7500078, 0xcd000078, 0xc2000000,\n    0x58380004, 0xca020078, 0xc3000000, 0x5838000c, 0xcb000020, 0x5a640002, 0x46610000, 0x84000010,\n    0xc2400000, 0x58380006, 0xc6500078, 0xcd000078, 0xc2000000, 0x5838000a, 0xca020078, 0x5b300002,\n    0x5838000c, 0xc7100020, 0xcd000020, 0xc2420020, 0x5a200004, 0x46252000, 0x84000010, 0xc2000000,\n    0x5838000a, 0xc6101078, 0xcd021078, 0xc000498c, 0xca4000f8, 0xc2000002, 0x6a3d0000, 0x72612000,\n    0xce4000f8, 0x5f740000, 0x84000040, 0xc0004912, 0xca0000f8, 0xc2c00002, 0x6afd6000, 0x7ec16000,\n    0x762d0000, 0xce0000f8, 0x5f300020, 0x84000040, 0xc0004924, 0xca0000f8, 0xc2c00002, 0x6afd6000,\n    0x7ec16000, 0x762d0000, 0xce0000f8, 0xa4820070, 0xc2400000, 0xc000140e, 0xca408018, 0xc2000002,\n    0xc0004900, 0xce000000, 0xc000490a, 0xce4000f8, 0xc1000000, 0xd90000f9, 0xd8400078, 0xc1000004,\n    0xd90000f9, 0xa48402d8, 0x00000000, 0xc3c00000, 0xc000140e, 0xcbc10018, 0xc2800000, 0xc2000000,\n    0x6ff8a000, 0x47bdc000, 0x5bb87600, 0x58380036, 0xca800078, 0x58380006, 0xca020078, 0xc3400000,\n    0x58380036, 0xcb420078, 0x5aa80002, 0x46a10000, 0x84000010, 0xc2800000, 0x58380036, 0xc6900078,\n    0xcd000078, 0x5f740002, 0x58380036, 0xc7501078, 0xcd021078, 0xc000498e, 0xca4000f8, 0xc2000002,\n    0x6a3d0000, 0x72612000, 0xce4000f8, 0xc000492a, 0xca8000f8, 0x5e740000, 0x84000040, 0xc0004910,\n    0xca0000f8, 0xc2c00002, 0x6afd6000, 0x7ec16000, 0x762d0000, 0xce0000f8, 0x6abd4010, 0xa6800132,\n    0x00000000, 0x5838003a, 0xca0000f8, 0x58000002, 0xca4000f8, 0x5838000e, 0x00000000, 0xce0000f9,\n    0xce4000f8, 0xc2400000, 0xdd250038, 0xc1000080, 0x45248000, 0xc2400000, 0xc6240078, 0x46510000,\n    0x00000000, 0xc52400fc, 0x5d240078, 0xc1000078, 0xc52400fc, 0xc6600078, 0x5c000002, 0xce000078,\n    0xc000492a, 0xca0000f8, 0xc2c00002, 0x6afd6000, 0x722d0000, 0xce0000f8, 0xc000492c, 0xca0000f8,\n    0xc2c00002, 0x6afd6000, 0x722d0000, 0xce0000f8, 0x80000040, 0xc000492c, 0xca0000f8, 0xc2c00002,\n    0x6afd6000, 0x7ec16000, 0x762d0000, 0xce0000f8, 0xa4880088, 0xc2c00000, 0xc000140e, 0xcac20018,\n    0xc000490e, 0xca4000f8, 0xc2000002, 0x6a2d0000, 0x7e010000, 0x76612000, 0xce4000f8, 0xc0004990,\n    0xca4000f8, 0xc2000002, 0x6a2d0000, 0x72612000, 0xce4000f8, 0xa4860070, 0xc2400000, 0xc000140e,\n    0xca418018, 0xc2020002, 0xc0004900, 0xce002100, 0xc0004908, 0xce4000f8, 0xc1000000, 0xd90000f9,\n    0xd8400078, 0xc1000004, 0xd90000f9, 0xc0001408, 0xcc8000f8, 0xc10e0002, 0xd90c00f8, 0x8000f750,\n    0xdfbc00f9, 0xc0004992, 0x99006be8, 0xc94000f8, 0xc7d800f8, 0x00000000, 0xc57000f8, 0x5ef00020,\n    0x88000158, 0x6f346000, 0x4771a000, 0x5b744c80, 0x58340008, 0xc2400000, 0xca400078, 0x00000000,\n    0xc2000000, 0x5a640002, 0xc6500078, 0xcd000078, 0x58340004, 0xca000078, 0x00000000, 0x00000000,\n    0x5e200002, 0xc6100078, 0xcd000078, 0xc0004912, 0xca8000f8, 0xc2400002, 0x6a712000, 0x72a54000,\n    0xce8000f8, 0x5e200000, 0x84000052, 0xc000480a, 0xca0000f8, 0xc0000408, 0xca8000f8, 0x76250000,\n    0x00000000, 0x72a14000, 0xce8000f8, 0x80000038, 0xc0004914, 0xca0000f8, 0x7e412000, 0x00000000,\n    0x76250000, 0xce0000f8, 0x800000c8, 0x6ef4a000, 0x476da000, 0x5b747600, 0x58340036, 0xc2400000,\n    0xca420078, 0x00000000, 0xc2000000, 0x5a640002, 0xc6501078, 0xcd021078, 0x58340006, 0xca000078,\n    0x00000000, 0x00000000, 0x5a200002, 0xc6100078, 0xcd000078, 0xc0004910, 0xca4000f8, 0xc2000002,\n    0x6a2d0000, 0x72612000, 0xce4000f8, 0xc2000002, 0x6a310000, 0xc000042a, 0xce0000f8, 0xc1040002,\n    0xd90c00f8, 0x00000000, 0x8000f4b8, 0x00000000, 0xc4980928, 0x9d000000, 0xc5580028, 0xc0000838,\n    0xcd8400f8, 0xc1440200, 0xc1c03800, 0xc55c1070, 0xc000100e, 0x9d000000, 0xcd8000f8, 0xc000100c,\n    0xcdc000f8, 0xc0004862, 0xc9c000f8, 0x00000000, 0x00000000, 0xd9d800f9, 0xc0007800, 0x401c0000,\n    0x5dc07a00, 0x88000012, 0x5c000200, 0xcd8000f8, 0xc1f0000a, 0x715ca000, 0xdd9800f8, 0xdd9c00f9,\n    0x41d8e000, 0xc5d40260, 0xc0001010, 0xcd4000f8, 0x6c9c8000, 0x45c8e000, 0x45c8e000, 0x59dc0004,\n    0xc1601260, 0xc5d40260, 0x9d000000, 0xc0001012, 0xcd4000f8, 0x00000000, 0x00000000, 0xd95800f8,\n    0x6d586000, 0x4594c000, 0x59984c80, 0xd99800f9, 0x5818000a, 0xc1800000, 0xc9800078, 0xc0007680,\n    0x6d5ca000, 0x401c0000, 0x40180000, 0xc94000f8, 0x58000002, 0x00000000, 0xc9c000f8, 0xc0004930,\n    0xcd4000f8, 0xc0004932, 0xcdc000f8, 0x59980004, 0xc1c20020, 0xb59c0018, 0x00000000, 0xc1800000,\n    0xdd9c00f9, 0x581c000a, 0xcd800078, 0x581c000c, 0xc1800000, 0xc9800020, 0xc1c00002, 0xdd9400f8,\n    0x69d4e000, 0x5d980002, 0xcd800020, 0xc0004924, 0xc98000f8, 0x00000000, 0x9d000000, 0x00000000,\n    0x719cc000, 0xcd8000f8, 0xc000492a, 0xc94000f8, 0xc1c00002, 0x69d8e000, 0x7dc0c000, 0x7558a000,\n    0xcd4000f8, 0xc000492c, 0xc94000f8, 0xdd8000f9, 0x5800003a, 0x755ca000, 0x84000108, 0xc94000f9,\n    0xc98000f8, 0xdd8000f9, 0x5800000e, 0x00000000, 0xcd4000f9, 0xcd8000f8, 0xc1800000, 0xdd190038,\n    0xc1000080, 0x45188000, 0xc1800000, 0xc5580078, 0x4590a000, 0x00000000, 0xc51800fc, 0x5d180078,\n    0xc1000078, 0xc51800fc, 0xc5940078, 0x5c000002, 0xcd400078, 0xc000492c, 0xc94000f8, 0xc000492a,\n    0xc98000f8, 0x715ca000, 0xc000492c, 0xcd4000f8, 0x719cc000, 0xc000492a, 0xcd8000f8, 0x9cc00000,\n    0x00000000, 0x00000000, 0x00000000, 0xc0004862, 0xc98000f8, 0x00000000, 0xc1c00200, 0x4194c000,\n    0x459ce000, 0x88000012, 0xc5d800f8, 0xc0004862, 0xcd8000f8, 0xc0001406, 0xc98000f8, 0xc1c00002,\n    0x9d000000, 0xc5d80a00, 0xc5581048, 0xcd8000f8, 0xc0004930, 0xc98000f8, 0xc0004932, 0xc9c000f8,\n    0xc140000e, 0xc5581c18, 0xdd9400f8, 0xc0007800, 0x40140000, 0x5d407a00, 0x88000012, 0x5c000200,\n    0xcd8000f8, 0x58000002, 0x5d407a00, 0x88000012, 0x5c000200, 0xcdc000f8, 0xdd5400f8, 0xc1c00000,\n    0x58140006, 0xc9c20078, 0xc1800000, 0x58140000, 0xc98000d8, 0x6ddc2000, 0xc000491e, 0x41d8e000,\n    0xcdc000f8, 0xdd9800f8, 0xc1c00022, 0xc5d80d70, 0xdd9400f9, 0xc5581c18, 0xc000491c, 0xcd8000f8,\n    0xdd5400f8, 0xc1c00000, 0x58140006, 0xc9c20078, 0xc1800000, 0x58140004, 0xc9820078, 0x00000000,\n    0x59dc0002, 0x45d8c000, 0x84000010, 0xc1c00000, 0x9d000000, 0x58140006, 0xc5d81078, 0xcd821078,\n    0xc0004860, 0xc94000f8, 0xc1820080, 0xc1d00002, 0x58147700, 0xd58000f8, 0x58000002, 0xd58000f9,\n    0x59540004, 0xb5580018, 0xc0004860, 0xc1400000, 0xcd4000f8, 0xdd9800f9, 0x9d000000, 0xdd9400f8,\n    0xc0001404, 0xcdc10800, 0xc1c00000, 0xc1800200, 0x5d980004, 0xdf5d0048, 0x459ca000, 0x8800fff2,\n    0xdd8000f9, 0x5800000e, 0x00000000, 0xc94000f9, 0xc98000f8, 0xc1c00002, 0xc5d43f00, 0xc5d81e00,\n    0xc0004862, 0xc9c000f8, 0x00000000, 0x00000000, 0x581c7800, 0x5dc07a00, 0x88000012, 0x5c000200,\n    0xcd4000f8, 0x58000002, 0x5dc07a00, 0x88000012, 0x5c000200, 0xcd8000f8, 0xc0004862, 0xc9c000f8,\n    0x00000000, 0xc15004c0, 0xc5d40060, 0xdd9c00f8, 0xc5d41c18, 0xc1c00000, 0xdd8000f9, 0x58000038,\n    0xc9c00078, 0xdd8000f9, 0xc1800000, 0x58000002, 0xc98000d8, 0x6ddc2000, 0xc000491c, 0x41d8e000,\n    0xcd4000f9, 0xcdc000f8, 0xdd9400f9, 0xc1c00000, 0x58140038, 0xc9c00078, 0xc1800000, 0x58140006,\n    0xc9820078, 0x00000000, 0x59dc0002, 0x45d8c000, 0x84000010, 0xc1c00000, 0x9d000000, 0x58140038,\n    0xc5d80078, 0xcd800078, 0xc1c00000, 0xdf5c0038, 0x5ddc0080, 0x8400ffea, 0x00000000, 0x9d000000,\n    0x00000000, 0x00000000, 0x00000000, 0xc160fffe, 0xc0000a10, 0xc9440060, 0xc1a0fffe, 0x59983608,\n    0xc000100c, 0xcd4000f8, 0xc000100e, 0xcd8000f8, 0xc0004962, 0xc98000f8, 0x00000000, 0xc170000a,\n    0x7158a000, 0x6c988000, 0x4588c000, 0x4588c000, 0x59980004, 0xc5940270, 0xc0001010, 0xcd4000f8,\n    0xc0004946, 0xc94000f8, 0x00000000, 0x00000000, 0x6d58a000, 0x6d5c4000, 0x459cc000, 0x4594c000,\n    0xc000494a, 0xc94000f8, 0xc0004948, 0xc9c000f8, 0x4194c000, 0xc1400012, 0xc55c1818, 0x9d000000,\n    0xc59c0268, 0xc0001012, 0xcdc000f8, 0xc1400000, 0x58000014, 0xc9410038, 0xc0004950, 0xc9c000f8,\n    0xc55800f8, 0xc5940838, 0xc5581078, 0xd99400f8, 0xc000493c, 0xc94000f8, 0xc0004954, 0xc98000f8,\n    0x59dc00a8, 0x45d4e000, 0x41d8e000, 0x5d5c0030, 0x88000010, 0xc1c00030, 0xc1800000, 0xc5d84028,\n    0xc1400000, 0xc5d40008, 0x5dd40002, 0x84000072, 0x5dd40004, 0x8400009a, 0x5dd40006, 0x840000c2,\n    0x5dd80026, 0x840000ea, 0xdd5400f8, 0xdd8000f9, 0x58000008, 0x40180000, 0xcd4000f8, 0x59980002,\n    0x8000ffc0, 0xdd5400f8, 0xdd8000f9, 0x58000008, 0x40180000, 0xcd4000b8, 0x59980002, 0x8000ff88,\n    0xdd5400f8, 0xdd8000f9, 0x58000008, 0x40180000, 0xcd400078, 0x59980002, 0x8000ff50, 0xdd5400f8,\n    0xdd8000f9, 0x58000008, 0x40180000, 0xcd400038, 0x59980002, 0x8000ff18, 0x00000000, 0x9d000000,\n    0x00000000, 0x00000000, 0x00000000, 0x58000014, 0xc94000f8, 0xc0004954, 0xc9c000f8, 0xc0004950,\n    0xc9400078, 0xdd8000f9, 0x5800002a, 0x5d9c0000, 0x84000052, 0x5d9c0002, 0x84000052, 0x5d9c0004,\n    0x8400006a, 0xc55b0038, 0xc55c08b8, 0xcd800039, 0xcdc108b8, 0x80000060, 0xcd4000f8, 0x80000050,\n    0xc55900b8, 0xc55c1838, 0xcd8000b9, 0xcdc31838, 0x80000028, 0xc55a0078, 0xc55c1078, 0xcd800079,\n    0xcdc21078, 0x9d000000, 0x00000000, 0x00000000, 0x00000000, 0xc1e00000, 0xa540001a, 0xc0000a14,\n    0xc1a20002, 0x9d000000, 0xcd863100, 0xc0000a1c, 0xcdc61038, 0x59540002, 0x6994e018, 0x61c0c008,\n    0x4194a000, 0x5d940040, 0x88000012, 0xc59400f8, 0x9d000000, 0xcd4000f8, 0x00000000, 0x00000000,\n};\n\nstatic unsigned int firmware_binary_data[] = {\n};\n\n\n#endif  //  IFXMIPS_PTM_FW_AR9_H\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-ptm/src/ifxmips_ptm_fw_danube.h",
    "content": "#ifndef IFXMIPS_PTM_FW_DANUBE_H\n#define IFXMIPS_PTM_FW_DANUBE_H\n\n\n/******************************************************************************\n**\n** FILE NAME    : ifxmips_ptm_fw_danube.h\n** PROJECT      : Danube\n** MODULES     \t: PTM (ADSL)\n**\n** DATE         : 1 AUG 2005\n** AUTHOR       : Xu Liang\n** DESCRIPTION  : PTM Driver (PP32 Firmware)\n** COPYRIGHT    : \tCopyright (c) 2006\n**\t\t\tInfineon Technologies AG\n**\t\t\tAm Campeon 1-12, 85579 Neubiberg, Germany\n**\n**    This program is free software; you can redistribute it and/or modify\n**    it under the terms of the GNU General Public License as published by\n**    the Free Software Foundation; either version 2 of the License, or\n**    (at your option) any later version.\n**\n** HISTORY\n** $Date        $Author         $Comment\n**  4 AUG 2005  Xu Liang        Initiate Version\n** 23 OCT 2006  Xu Liang        Add GPL header.\n*******************************************************************************/\n\n\n#define PTM_FW_VER_MAJOR        0\n#define PTM_FW_VER_MINOR        17\n\n\nstatic unsigned int firmware_binary_code[] = {\n    0x800004a0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x8000ffc8, 0x00000000, 0x00000000, 0x00000000,\n    0xc1000002, 0xd90c0000, 0xc2000002, 0xda080001, 0x80005618, 0xc2000000, 0xda080001, 0x800055b8,\n    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0x94000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0x80005da8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0x94000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0x94000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0x94000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0x94000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0xc10e0002, 0xd90c0000, 0xc0004808, 0xc8400000, 0x80005288, 0x00000000, 0x00000000, 0x00000000,\n    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0xc3e1fffe, 0x597dfffe, 0x593dfef4, 0x900004d9, 0x00000000, 0x00000000, 0x00000000, 0x90cc0481,\n    0x00000000, 0x00000000, 0x00000000, 0xc3e02262, 0x5bfc0022, 0xc0004002, 0xcfc00000, 0xc0004810,\n    0xcbc00000, 0x00000000, 0xc3800000, 0xc7f80040, 0x5fb80000, 0xc7fa0040, 0xc7bfe80a, 0x5fb80000,\n    0x00000000, 0xc7bff80a, 0xdbd40001, 0xc00049a0, 0xc3800002, 0xa7ca004a, 0xc1200000, 0x5911fffe,\n    0xcd000001, 0xc1200000, 0x59102042, 0xcd000001, 0xc1000004, 0xcd000001, 0xc1200000, 0x59103a1e,\n    0xcd000001, 0x80000048, 0xc121fffe, 0x5911fffe, 0xcd000001, 0xc1203db8, 0x5910de82, 0xcd000001,\n    0xc1000006, 0xcd000001, 0xc120385a, 0x591033da, 0xcd000001, 0x5fb80002, 0x88000002, 0x6ffe0010,\n    0x8000ff10, 0xdd7c0001, 0xc3800000, 0xc7f86018, 0x5bb80008, 0xc3540002, 0x77f5a000, 0xc1000008,\n    0x4539c002, 0xcf800001, 0xdb900040, 0xc3800008, 0xc3720002, 0x77f5a000, 0xa7f00008, 0x47b9c002,\n    0xc1000000, 0xc7d26018, 0x4391c000, 0xcf800000, 0xdb900840, 0xc3c00000, 0xdbc80001, 0xc0400000,\n    0xc11c0000, 0xc000082c, 0xcd040e08, 0xc11c0002, 0xc000082c, 0xcd040e08, 0xc0400002, 0xc11c0000,\n    0xc000082c, 0xcd040e08, 0xc11c0002, 0xc000082c, 0xcd040e08, 0xc0000824, 0x00000000, 0xcbc00001,\n    0xcb800001, 0xcb400001, 0xcb000000, 0xc0004878, 0x5bfc4000, 0xcfc00001, 0x5bb84000, 0xcf800001,\n    0x5b744000, 0xcf400001, 0x5b304000, 0xcf000000, 0xc0000a10, 0x00000000, 0xcbc00001, 0xcb800000,\n    0xc0004874, 0x5bfc4000, 0xcfc00001, 0x5bb84000, 0xcf800000, 0xc30001fe, 0xc000140a, 0xcf000000,\n    0xc3000000, 0x7f018000, 0xc000042e, 0xcf000000, 0xc000040e, 0xcf000000, 0xc3c1fffe, 0xc000490e,\n    0xcfc00080, 0xc000492c, 0xcfc00080, 0xc0004924, 0xcfc00040, 0xc0004912, 0xcfc00040, 0xc000498c,\n    0xcfc00040, 0xc000498e, 0xcfc00080, 0xc0004990, 0xcfc00080, 0xc3c00000, 0xc2800004, 0xc3000000,\n    0x7f018000, 0x6ff88000, 0x6fd44000, 0x4395c000, 0x5bb84a00, 0xc00049a0, 0xcb000000, 0x00000000,\n    0x58380006, 0xcf000000, 0xc321fffe, 0x5b31fffe, 0x58380024, 0xcf000000, 0x5bfc0002, 0xb7e8ff70,\n    0x00000000, 0xc3c00000, 0xc2800010, 0x6ff86000, 0x47f9c000, 0x5bb84c80, 0xc3400000, 0x58380004,\n    0xcb420080, 0x00000000, 0x58380008, 0xcf400080, 0x5bfc0002, 0xb7e8ff90, 0x00000000, 0xc3c00000,\n    0xc2800004, 0xc3400022, 0xc3000000, 0x7f018000, 0xc2c00016, 0x6ff8a000, 0x47f9c000, 0x5bb84e20,\n    0x58380008, 0xcf400040, 0xc00049a8, 0xcb000000, 0x00000000, 0x5838000a, 0xcf000000, 0xc321fffe,\n    0x5b31fffe, 0x5838000c, 0xcf000000, 0x58380034, 0xcec00040, 0x5bfc0002, 0xb7e8ff58, 0x00000000,\n    0x00000000, 0xc0004840, 0xc3e12624, 0x5bfc2320, 0xcfc00001, 0xc3e02f2c, 0x5bfd2a28, 0xcfc00001,\n    0xc3e03734, 0x5bfd3230, 0xcfc00001, 0xc3e13e3c, 0x5bfc3b38, 0xcfc00001, 0xc3e14644, 0x5bfc4340,\n    0xcfc00001, 0xc3e04f4c, 0x5bfd4a48, 0xcfc00001, 0xc3e05754, 0x5bfd5250, 0xcfc00001, 0xc3e15e5c,\n    0x5bfc5b58, 0xcfc00001, 0xc3e06764, 0x5bfd6260, 0xcfc00001, 0xc3e16e6c, 0x5bfc6b68, 0xcfc00001,\n    0xc3e17674, 0x5bfc7370, 0xcfc00001, 0xc3e07f7c, 0x5bfd7a78, 0xcfc00001, 0xc3e18684, 0x5bfc8380,\n    0xcfc00001, 0xc3e08f8c, 0x5bfd8a88, 0xcfc00001, 0xc3e09794, 0x5bfd9290, 0xcfc00001, 0xc3e19e9c,\n    0x5bfc9b98, 0xcfc00001, 0xc121fffe, 0x5911fef4, 0x15000000, 0x80000010, 0x00000000, 0x80000638,\n    0x00000000, 0x8000ffc8, 0xc0004918, 0xd2800000, 0xc2000000, 0xdf600040, 0x5e600080, 0x8400029a,\n    0x00000000, 0xc161fffe, 0x5955fffe, 0x15400000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0x00000000, 0x00000000, 0xc000480a, 0xca000000, 0xc0004912, 0xca400000, 0xc0004924, 0xca800000,\n    0xc000498c, 0xcac00000, 0xc121fffe, 0x5911fef4, 0x15000000, 0x76610000, 0x76a10000, 0x76e10000,\n    0x840001d2, 0xc0004918, 0xca400000, 0xc28001fe, 0x76a10000, 0x5a640002, 0x6a254010, 0x5ee80000,\n    0x84000002, 0x6aa54000, 0x8000fff8, 0xc6280000, 0x62818008, 0xc0004918, 0xcf000000, 0xc161fffe,\n    0x5955fffe, 0x15400000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0xc000498c, 0xca400000, 0xc2000002, 0x6a310000, 0x7e010000, 0x76252000, 0xce400000, 0xc121fffe,\n    0x5911fef4, 0x15000000, 0x6f346000, 0x4735a000, 0x5b744c80, 0xc2800000, 0x58340006, 0xca800080,\n    0xc2c00000, 0x58340000, 0xcac000e0, 0xc2400000, 0x5834000a, 0xca420080, 0x6ea82000, 0x42e9e000,\n    0x6f2ca000, 0x42e56000, 0x5aec1400, 0xc3990040, 0xc7381c20, 0xc6f80068, 0x99006840, 0xdb980000,\n    0xdbd80001, 0x00000000, 0xdea00000, 0x47210000, 0x8400fd28, 0xc000495a, 0xc8400000, 0x00000000,\n    0xc3c00002, 0x7bc42000, 0xcc400000, 0xc0000838, 0xc3800000, 0xcb840030, 0x6c748000, 0x6c544000,\n    0x4355a000, 0x5b744a00, 0x5ef80000, 0x8400fc8a, 0x58340004, 0xcb000000, 0x00000000, 0x00000000,\n    0xa7060000, 0x00000000, 0x5ef80002, 0x8400fc4a, 0x5834000c, 0xc8800040, 0xc2000000, 0xc000082c,\n    0xca040030, 0x5a880002, 0xc2400000, 0xc0004958, 0xce400000, 0xb628fff8, 0x00000000, 0xc2800000,\n    0x58340002, 0xc2000000, 0xca020010, 0xc0004956, 0xce800000, 0x5e600000, 0x84001df2, 0x5e600002,\n    0x840043da, 0x00000000, 0x80002320, 0xc0004958, 0xca000000, 0xc0004956, 0xca800000, 0x5e200000,\n    0x84000008, 0xc2500002, 0xc0000838, 0xce440808, 0x6c748000, 0x6c544000, 0x4355a000, 0x5b744a00,\n    0x5834000c, 0xc6900040, 0xcd000040, 0x58340002, 0xc2000000, 0xca020010, 0x00000000, 0x00000000,\n    0x5f600000, 0x84000122, 0xc0004818, 0xc8000000, 0x00000000, 0x00000000, 0x5c000000, 0x840000f2,\n    0xc11c0000, 0xc000082c, 0xcd040e08, 0xc0000838, 0xc3800000, 0xc2400000, 0xcb840030, 0xca452030,\n    0x00000000, 0x42b9a000, 0x5e340022, 0x88000012, 0xc200001e, 0x7635a000, 0x5f740002, 0x8000fff0,\n    0x6e642010, 0x4675a000, 0x84000042, 0xc0004818, 0xc8000000, 0x00000000, 0x00000000, 0x5c000000,\n    0x84000012, 0x00000000, 0x00000000, 0x00000000, 0x8000ffa0, 0xc11c0002, 0xc000082c, 0xcd040e08,\n    0x8000f9b8, 0xc2000000, 0xdf600040, 0x5e200080, 0x84000272, 0x00000000, 0xc161fffe, 0x5955fffe,\n    0x15400000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xc000480c,\n    0xca000000, 0xc0004910, 0xca400000, 0xc000492c, 0xca800000, 0xc000498e, 0xcac00000, 0xc121fffe,\n    0x5911fef4, 0x15000000, 0x76610000, 0x76a10000, 0x762d6000, 0x840001aa, 0xc0004926, 0xca400000,\n    0xc201fffe, 0x762d6000, 0x5a640002, 0x6ae50010, 0x5f200000, 0x84000002, 0x6a250000, 0x8000fff8,\n    0xc6e00000, 0x62014008, 0xc0004926, 0xce800000, 0xc161fffe, 0x5955fffe, 0x15400000, 0x00000000,\n    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xc000498e, 0xca400000, 0xc2000002,\n    0x6a290000, 0x7e010000, 0x76252000, 0xce400000, 0xc121fffe, 0x5911fef4, 0x15000000, 0x6eb4a000,\n    0x46b5a000, 0x5b744e20, 0x58340002, 0xc2000000, 0xca0000e0, 0x58340036, 0xc2400000, 0xca400080,\n    0x6eb0a000, 0x46b18000, 0x5b300e56, 0x5b300004, 0x6e642000, 0x4225e000, 0xc39a8024, 0xc7380068,\n    0xc6b81c20, 0x99006840, 0xdb980000, 0xdbd80001, 0x00000000, 0xc2000000, 0xdf600040, 0x5e200080,\n    0x840002c2, 0x00000000, 0xc161fffe, 0x5955fffe, 0x15400000, 0x00000000, 0x00000000, 0x00000000,\n    0x00000000, 0x00000000, 0x00000000, 0xc000490e, 0xca000000, 0xc000492a, 0xca400000, 0xc0004990,\n    0xcb000000, 0xc000498a, 0xcac00000, 0xc121fffe, 0x5911fef4, 0x15000000, 0x76318000, 0x76718000,\n    0x84000202, 0xc201fffe, 0x76318000, 0x5aec0002, 0x6b2d0010, 0x5ea00000, 0x84000002, 0x6a2d0000,\n    0x8000fff8, 0xc7200000, 0x62016008, 0xc000498a, 0xcec00000, 0xc161fffe, 0x5955fffe, 0x15400000,\n    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xc0004990, 0xca400000,\n    0xc2000002, 0x6a2d0000, 0x7e010000, 0x76252000, 0xce400000, 0xc121fffe, 0x5911fef4, 0x15000000,\n    0x6ef4a000, 0x46f5a000, 0x5b744e20, 0x58340010, 0xc2000000, 0xca0000e0, 0x58340008, 0xc2400000,\n    0xca420080, 0x5834000e, 0xc2800000, 0xca832018, 0xc3c00000, 0x467c8000, 0x6e644010, 0xc7e80004,\n    0x42250000, 0x4229e000, 0xc39a8008, 0x58340008, 0xcb801040, 0x58340008, 0xc2800000, 0xca810018,\n    0x6ee0a000, 0x46e10000, 0x5a20000a, 0x5a200e28, 0x42290000, 0xc6380068, 0xc6f81c20, 0x99006840,\n    0xdb980000, 0xdbd80001, 0x00000000, 0xc000495c, 0xc8400000, 0xc3400000, 0xc3c00002, 0x7bc42000,\n    0xcc400000, 0x6c78a000, 0x4479c000, 0x5bb84e20, 0x58380034, 0xcb410040, 0xc0000a28, 0xc3000000,\n    0xcb040030, 0xc0000a14, 0xc2c00000, 0x43358000, 0xcac40030, 0xc000490e, 0xca800000, 0x5eec0002,\n    0x46f18000, 0x8800f348, 0x6bc5e000, 0x77e94000, 0x8400f330, 0x6c7ca000, 0x447de000, 0x5bfc4e20,\n    0x583c0008, 0xc2000000, 0xca020080, 0xc00049aa, 0x00000000, 0xca800001, 0xca400000, 0xc0001008,\n    0xce800000, 0xc0001006, 0xce400000, 0x583c000a, 0xca400000, 0x00000000, 0xc000100a, 0xce400000,\n    0xc2400006, 0xc0001000, 0xce400000, 0xc2600982, 0x5a643b6e, 0xc0001002, 0xce400000, 0x583c000c,\n    0xca400000, 0x00000000, 0xc0001004, 0xce400000, 0x583c000e, 0xcb800000, 0x00000000, 0xc2400000,\n    0xc7a40080, 0xc2800000, 0xc7aae028, 0xdaa00001, 0x583c0034, 0xcb800000, 0x00000000, 0xc2c00000,\n    0xc7ad0040, 0xc0004978, 0xcec00000, 0xc0800000, 0xc7880040, 0xc3400000, 0xc7b60040, 0xc0004980,\n    0xcf400000, 0x4625c000, 0x43a9c000, 0xc2400000, 0xc000497c, 0xce400000, 0xac2c0001, 0xc2800000,\n    0x00000000, 0x8000fff8, 0xc2800002, 0xc0004976, 0xce800000, 0xc2c00000, 0xc34000a0, 0xdb5c0001,\n    0xc3400002, 0xc000497a, 0xcf400000, 0x5f600000, 0x84000168, 0xde280001, 0xc6a00000, 0x46b9c000,\n    0x583c0000, 0xc2800000, 0xca830040, 0xc0000a28, 0xc3000000, 0xcb040030, 0xc3400000, 0xc0004976,\n    0x47298000, 0x88000052, 0xcf400000, 0x58880002, 0xc3000000, 0xc0000a14, 0xcb040030, 0x00000000,\n    0x00000000, 0xb4b00188, 0x00000000, 0xc0800000, 0x00000000, 0x80000170, 0xc0004980, 0xcb400000,\n    0x00000000, 0x00000000, 0x5af40002, 0xafec0080, 0x00000000, 0xc2c00000, 0xc000497a, 0xacec0001,\n    0x00000000, 0x00000000, 0xac2c007f, 0xc2800000, 0xce800000, 0x80000000, 0xc2800002, 0xce800000,\n    0x5f6c0000, 0x840000d0, 0x00000000, 0x8000fee8, 0x5f780082, 0x88000240, 0xc3000002, 0xc000497c,\n    0xcf000000, 0xc2800080, 0xc1000000, 0xdd110040, 0x45294000, 0x46b94000, 0x880001c0, 0x4391a000,\n    0xc0004980, 0xcf400000, 0x6f684010, 0x6f77c000, 0x6f77c010, 0xc0004840, 0x40280000, 0xca800000,\n    0xc3000000, 0x6f506000, 0x6a908010, 0xc5300040, 0xdb1c0001, 0x8000fe18, 0xc3400000, 0xc0000a10,\n    0xcb440068, 0x6cb04000, 0x6f288000, 0x6f744000, 0x42b14000, 0x43694000, 0xc3400000, 0xc6b44068,\n    0xc0004000, 0x40340000, 0xc321e000, 0xcf000000, 0x5aa80008, 0x42ad4000, 0xc3400000, 0xc6b44068,\n    0xc0004000, 0x40340000, 0xca400000, 0xc3000000, 0xc6f00010, 0xc1400000, 0xddd40041, 0x6f306000,\n    0xc13001fe, 0x69308010, 0x7d008000, 0x75252000, 0x6d570000, 0x6970a010, 0x42552000, 0xce400000,\n    0x5aa80002, 0x5aec0002, 0xafec0080, 0x00000000, 0xc2c00000, 0x5f6c0000, 0x84000100, 0x00000000,\n    0x80000028, 0x4391a000, 0x5f740080, 0xc0004980, 0xcf400000, 0xc3000004, 0xc000497a, 0xcf000000,\n    0x58880002, 0xc3400000, 0xc0000a14, 0xcb440030, 0x00000000, 0x00000000, 0xb4b4fff8, 0x00000000,\n    0xc0800000, 0xc3400000, 0xc0000a10, 0xcb440068, 0x6cb04000, 0x6f248000, 0x6f744000, 0x42712000,\n    0x43654000, 0xc3400000, 0xc6b44068, 0xc0004000, 0x40340000, 0xc3201e00, 0xcf000000, 0x5aa80008,\n    0x42ad4000, 0xc000100c, 0xcb400000, 0xc3000000, 0x00000000, 0xc7340068, 0xc300fffe, 0xc7341078,\n    0xcf400000, 0xc000100e, 0xcb400000, 0xc3000e28, 0x00000000, 0xc7340068, 0xc300fffe, 0xc7341078,\n    0xcf400000, 0xc0001010, 0xcb400000, 0xc3000002, 0x00000000, 0xc7341a08, 0xc7341808, 0xc3000000,\n    0xc7341908, 0xc6b40078, 0xcf400000, 0xc0004982, 0xce800000, 0x6c64a000, 0x44652000, 0x5a64000a,\n    0xc0001012, 0xcb400000, 0xc2800002, 0x00000000, 0xc6740268, 0xc6340010, 0xc000497c, 0xcb000000,\n    0xc6b41808, 0xc6b41b08, 0xc6b41c08, 0xc6b41d08, 0xc7341e08, 0xdd680001, 0x7e814000, 0x6eab2010,\n    0x77294000, 0xc6b41f08, 0xc2800000, 0xc6b41908, 0xc3000080, 0x46f18000, 0xc0004982, 0xc9000000,\n    0x47b14000, 0x880000ea, 0x41388000, 0xcd000000, 0xc7b41040, 0xc0004994, 0xce800000, 0xde100001,\n    0x46108000, 0x84000098, 0xc1000000, 0xdd110040, 0x41388000, 0x412c8000, 0x5d100080, 0xc0004980,\n    0xcd000000, 0xc1000002, 0xc000497c, 0xcd000000, 0xc5341e08, 0xdd500001, 0x7d008000, 0xc5373f08,\n    0xc000497a, 0xc9000000, 0x42390000, 0x43adc000, 0x59100002, 0xcd000000, 0x80000038, 0x42390000,\n    0x80000028, 0xc7341040, 0x41308000, 0xcd000000, 0x42310000, 0xc1000000, 0xc0004994, 0xcd000000,\n    0xc0001012, 0xcf400000, 0xc000493c, 0xce000000, 0xc0004984, 0xcf800000, 0xc000497a, 0xca400000,\n    0xc000497c, 0xca800000, 0x6c7ca000, 0x447de000, 0x5bfc4e20, 0xc0004976, 0xcac00000, 0xc0004978,\n    0xca000000, 0x5eec0002, 0x84000072, 0x42250000, 0xc2400000, 0xc000497a, 0xce400000, 0x583c0000,\n    0xc2c00000, 0xcac30040, 0x00000000, 0x00000000, 0x462d6000, 0x88000002, 0x00000000, 0xac280002,\n    0xc000497a, 0xce000000, 0xc2000000, 0x5fa80000, 0x840001c2, 0x00000000, 0x6c508000, 0xc0004880,\n    0x40100000, 0x58000018, 0xc9000000, 0x00000000, 0x00000000, 0x59100002, 0xcd000000, 0x583c000e,\n    0xc2c00000, 0xcac00080, 0xc1000000, 0xdd532209, 0x42d16000, 0x6c508000, 0xc0004880, 0x40100000,\n    0x5800001a, 0xc9000000, 0x00000000, 0x00000000, 0x412c8000, 0xcd000000, 0x990068d0, 0xd8580000,\n    0xdbd80001, 0x00000000, 0x99006618, 0xc000491c, 0xc1400000, 0xc9420050, 0xc000491c, 0x99006ad0,\n    0xc9400001, 0xc9800000, 0x00000000, 0x99006840, 0xd9580000, 0xd9980001, 0x00000000, 0xc161fffe,\n    0x5955fffe, 0x15400000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0x98c06490, 0xd8580000, 0xdbd80001, 0xc4580000, 0xc121fffe, 0x5911fef4, 0x15000000, 0xace80003,\n    0xc000493c, 0xcb400000, 0x00000000, 0xc3000000, 0xc7701080, 0x8000fff8, 0xc3000000, 0x583c0008,\n    0xcf001080, 0x6e210000, 0x583c0034, 0xce000840, 0xc0004980, 0xcb800000, 0x583c0034, 0x00000000,\n    0x6fba0000, 0xcf801040, 0xc000490e, 0xca000000, 0xc2c00002, 0x6ac56000, 0x72e10000, 0xce000000,\n    0x00000000, 0x00000000, 0x00000000, 0xa8e2ffc8, 0x00000000, 0xc1220002, 0xd90c0000, 0x5fa80000,\n    0x840006fa, 0xc00049a8, 0xca000000, 0x583c000a, 0x00000000, 0xce000000, 0xc221fffe, 0x5a21fffe,\n    0x583c000c, 0xce000000, 0xc0001004, 0xca000000, 0x00000000, 0x583c0012, 0x7e010000, 0xce000000,\n    0xa97000c1, 0x00000000, 0x00000000, 0xa97200a9, 0xc0001010, 0xc2740000, 0xce401a08, 0x6c64a000,\n    0x44652000, 0x5a64000a, 0x6e644000, 0xc0001012, 0xce400078, 0xc2600008, 0xce401040, 0xc27e0002,\n    0xce401f08, 0xc2760002, 0xce401b08, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0xa8e2ffc8, 0x00000000, 0xc1220002, 0xd90c0000, 0xc1000000, 0xdd110040, 0x5d100000, 0x840003fa,\n    0xc0004982, 0xca000000, 0xc0004984, 0xca400000, 0xc2800000, 0xc361fffe, 0x5b75fffe, 0xa96afffb,\n    0xdfec0000, 0xc6ec1080, 0x7b6d6000, 0x6c40a000, 0x44400000, 0x58004e20, 0x58000014, 0xcec00000,\n    0xa972fffb, 0x5c000002, 0xcec00000, 0xc0001010, 0xc2f40002, 0xcec01a08, 0x6c6ca000, 0x446d6000,\n    0x5aec000a, 0x6eec4000, 0xc0001012, 0xcec00078, 0xc0004994, 0xc9800000, 0xc1400000, 0xdd150040,\n    0xc55c0000, 0x45588000, 0x00000000, 0xc59c0004, 0x5d1c0000, 0x840000ba, 0xc0001012, 0xc5d01040,\n    0xcd001040, 0xc2f60002, 0xcec01b08, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0xa8e2ffc8, 0x00000000, 0xc1220002, 0xd90c0000, 0x45588000, 0x8800003a, 0xc0004994, 0xcd000000,\n    0xc0004980, 0xcbc00000, 0x42150000, 0xc0004982, 0xce000000, 0x5ffc0000, 0x84000200, 0x58880002,\n    0xc3800000, 0xc0000a14, 0xcb840030, 0xc3c00000, 0xc0000a10, 0xb4b8fff8, 0x00000000, 0xc0800000,\n    0xcbc40068, 0x6cb84000, 0x6fac8000, 0x6ffc4000, 0x42f96000, 0x43ed0000, 0xc3400000, 0xc6344068,\n    0xc0004000, 0x40340000, 0xc2a1e000, 0xce800000, 0x5a200008, 0xc0004980, 0xcbc00000, 0xc3400000,\n    0xc0004840, 0x6ff84010, 0xc7f40010, 0x40380000, 0xcb800000, 0xc2800000, 0x6f506000, 0x6b908010,\n    0xc52c1840, 0xc3400000, 0xc6344068, 0xc0004000, 0x40340000, 0xcec00000, 0x5a200002, 0x5ffc0000,\n    0x8400007a, 0xc0001010, 0xc62c0078, 0xcec00078, 0xc0001012, 0xc7ec1040, 0xcec01040, 0xc2f60002,\n    0xcec01b08, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xa8e2ffc8, 0x00000000,\n    0xc1220002, 0xd90c0000, 0xc0004994, 0xc100007e, 0x47d08000, 0xcd000000, 0x423d0000, 0xc0004982,\n    0xce000000, 0xc0004994, 0xca000000, 0xc0004980, 0xca400000, 0x5e200000, 0x84000142, 0xc2000000,\n    0xc2800000, 0x5a640002, 0xc6684030, 0xc0004982, 0xcb000000, 0xc0004000, 0xc2c00000, 0xc72c4068,\n    0x402c0000, 0x6e67c000, 0x6e67c010, 0x5ee40002, 0x84000022, 0x5ee40004, 0x84000032, 0x5ee40006,\n    0x84000042, 0x00000000, 0x80000048, 0xce0000c0, 0x5aa80002, 0x5b300006, 0x80000028, 0xce000080,\n    0x5aa80002, 0x5b300004, 0x80000008, 0xce000040, 0x5aa80002, 0x5b300002, 0x5ee80020, 0x8400003a,\n    0xc0004000, 0xc2c00000, 0xc72c4068, 0x402c0000, 0xce000000, 0x5aa80002, 0x5b300008, 0x8000ffa0,\n    0x00000000, 0x80000028, 0x583c000a, 0xd7c00000, 0xc0001004, 0xca400000, 0x00000000, 0x583c000c,\n    0xce400000, 0xc000497a, 0xca400000, 0xc2800002, 0xc0000a28, 0xc6780930, 0xc6b80808, 0xcf840838,\n    0x6c7ca000, 0x447de000, 0x5bfc4e20, 0x583c0034, 0xc4900040, 0xcd000040, 0x8000e400, 0x6c6c8000,\n    0x6c544000, 0x42d56000, 0x5aec4a00, 0xc0000824, 0xca040000, 0x6ca48000, 0x42492000, 0xc3000000,\n    0xc3400000, 0x42250000, 0x58204000, 0xca400000, 0x5a200002, 0xda240001, 0xc2800000, 0xc000495e,\n    0xce800000, 0xda600000, 0xc2800000, 0xc66b0040, 0xdaa80000, 0x582c0010, 0x6f206010, 0x40200000,\n    0xd8280001, 0xca000000, 0xc2400000, 0xc7240018, 0x6e644000, 0xda640000, 0x6a254010, 0xc3c00000,\n    0xc6bc0020, 0xc3800000, 0xdea00000, 0x5e60001e, 0x84000012, 0x5e6001e0, 0x84000002, 0x00000000,\n    0x80000068, 0xc7f80000, 0x5e7c0008, 0x84000052, 0x5bbc0002, 0x5e780008, 0x84000010, 0x5b740002,\n    0xc0004960, 0xcf000000, 0x80000018, 0x5e780006, 0x8800000a, 0xc2800002, 0xc000495e, 0xce800000,\n    0xde800001, 0xca800000, 0xde600000, 0xc240001e, 0x6a612000, 0x7e412000, 0x76694000, 0x6ba12000,\n    0x72694000, 0xce800000, 0x5e300080, 0x840000a2, 0xc2000000, 0xc7200010, 0x5e600000, 0x84000040,\n    0xde600001, 0x58204000, 0xca400000, 0x5a200002, 0xda240001, 0xc2800000, 0xc66b0040, 0xdaa80000,\n    0xda600000, 0x80000020, 0xc2800000, 0x6e206000, 0xde240000, 0x6a610000, 0xc62b0040, 0xdaa80000,\n    0x5b300002, 0x8000fdc8, 0xc2000000, 0x582c0020, 0xca020080, 0x00000000, 0xc2400000, 0x5a200002,\n    0xc6241080, 0xce401080, 0xc000480e, 0xca800000, 0x5e740000, 0x84000148, 0x46292000, 0x8800dec8,\n    0xc2400000, 0xc0000808, 0xca440018, 0x582c0010, 0xc1400000, 0xcd400001, 0xcd400001, 0xcd400001,\n    0xcd400001, 0xcd400001, 0xcd400001, 0xcd400001, 0xcd400001, 0xcd400020, 0x582c0020, 0xce001080,\n    0xc2000010, 0x5a640002, 0xb624fff8, 0x00000000, 0xc2400000, 0xc6600018, 0xc0000808, 0xce040018,\n    0xc0004956, 0xca400000, 0xc11c0000, 0xc000082c, 0xcd040e08, 0xc6600930, 0xc2400000, 0xc6600030,\n    0xc0000838, 0xce040000, 0xc2400002, 0xc0004958, 0xce400000, 0xc11c0002, 0xc000082c, 0xcd040e08,\n    0x8000dd80, 0xc000495e, 0xca000000, 0x5e740002, 0x8400dd60, 0x5e200000, 0x8400dd50, 0xc0004960,\n    0xca400000, 0xc2200004, 0x582c0002, 0xce001010, 0xc2000082, 0x46610000, 0xc6280038, 0xc0000810,\n    0xce840038, 0x99006f68, 0x582c0002, 0xc9400000, 0xc1a20000, 0x5e640000, 0x8400feb8, 0x00000000,\n    0x8000dcc0, 0x6c6c8000, 0x6c544000, 0x42d56000, 0x5aec4a00, 0xc000487c, 0xc8040000, 0x00000000,\n    0x00000000, 0x40080000, 0xcb800000, 0xc4240000, 0x00000000, 0xa7860180, 0xc3c00000, 0xc2000000,\n    0x582c000c, 0xca010040, 0x6c508000, 0xc0004880, 0x40100000, 0x58000016, 0xc9000000, 0x00000000,\n    0x00000000, 0x59100002, 0xcd000000, 0x5a200002, 0x582c000c, 0xc6100840, 0xcd000840, 0x5e600002,\n    0x84000008, 0xc2200004, 0x582c0002, 0xce001010, 0x5e600008, 0x84000048, 0xc2200002, 0x582c0002,\n    0xce001010, 0x582c000c, 0xcfc00840, 0xc2220002, 0xc0000a14, 0xce041108, 0xc22001a2, 0xc0000a1c,\n    0xce041040, 0x6c6c8000, 0x6c544000, 0x42d56000, 0x5aec4a00, 0x582c0004, 0xcb000000, 0xc3400000,\n    0x00000000, 0xa7060008, 0xcf400308, 0xc3100002, 0xc0000838, 0xcf040808, 0x582c000c, 0xcf401008,\n    0x8000dac0, 0x582c000c, 0xcfc00840, 0xc2000000, 0xc7a06018, 0x5e200000, 0x84001e18, 0x6c6c8000,\n    0x6c544000, 0x42d56000, 0x5aec4a00, 0xc000487c, 0xc8040000, 0x00000000, 0x00000000, 0x40080000,\n    0xcb800000, 0xc4240000, 0x00000000, 0xc2800000, 0xc3400000, 0xc7b5c038, 0xc0004970, 0xcf400000,\n    0xc2400000, 0xc7a4e038, 0xc000496c, 0xce400000, 0xc3000000, 0xc7b00018, 0xc3c00004, 0xc000496e,\n    0xcfc00000, 0x582c000c, 0xca000000, 0xc2400002, 0xc0004964, 0xce400000, 0xa6200352, 0x00000000,\n    0x5e700004, 0x840000d2, 0x5e700006, 0x84000068, 0xc2000002, 0x582c0002, 0xce000008, 0xc0000a14,\n    0xce841108, 0x6c508000, 0xc0004880, 0x40100000, 0x58000014, 0xc9000000, 0x00000000, 0x00000000,\n    0x59100002, 0xcd000000, 0x80001c68, 0x5e70000a, 0x84000028, 0xc2000000, 0x582c0002, 0xce000008,\n    0xc2220002, 0xc0000a14, 0xce041108, 0x8000ff58, 0x5e700008, 0x84000210, 0xc2200002, 0x582c000c,\n    0xce001008, 0x6c508000, 0xc0004880, 0x40100000, 0x58000012, 0xc9000000, 0x00000000, 0x00000000,\n    0x59100002, 0xcd000000, 0x5e340002, 0x6c508000, 0xc0004880, 0x40100000, 0x58000010, 0xc9000000,\n    0x00000000, 0x00000000, 0x41208000, 0xcd000000, 0xc0000a14, 0xce841108, 0xc0004970, 0xcb400000,\n    0x6c6c8000, 0x6c544000, 0x42d56000, 0x5aec4a00, 0x582c000e, 0xc4900040, 0xcd000040, 0x582c000e,\n    0xc7500840, 0xcd000840, 0xc2800000, 0x582c0004, 0xce801080, 0x582c0004, 0xce800008, 0xc00049a0,\n    0xca400000, 0x00000000, 0x582c0006, 0xce400000, 0xc261fffe, 0x5a65fffe, 0x582c0024, 0xce400000,\n    0xc2060002, 0x582c0004, 0xce000308, 0xc2400002, 0xc0004958, 0xce400000, 0xc0004878, 0xc8040000,\n    0x6c908000, 0x41088000, 0x40100000, 0x58000020, 0xc9000000, 0x582c0026, 0x00000000, 0xcd000000,\n    0x800019f8, 0x00000000, 0x6c508000, 0xc0004880, 0x40100000, 0x58000016, 0xc9000000, 0x00000000,\n    0x00000000, 0x59100002, 0xcd000000, 0x8000fad8, 0x5e700000, 0x840000a8, 0xc3400082, 0xc0004970,\n    0xcf400000, 0xc2400080, 0xc000496c, 0xce400000, 0xc3c00002, 0xc000496e, 0xcfc00000, 0xc2400000,\n    0xc0004964, 0xce400000, 0xc0004878, 0xc8040000, 0x6c908000, 0x41088000, 0x40100000, 0x58000020,\n    0xc9000000, 0x582c0026, 0x00000000, 0xcd000000, 0x80000060, 0x5e700002, 0x84000040, 0xc3400082,\n    0xc0004970, 0xcf400000, 0xc3c00004, 0xc000496e, 0xcfc00000, 0xc2200000, 0x582c000c, 0xce001008,\n    0x80000018, 0x5e700004, 0x8400fe68, 0xc2600002, 0x582c000c, 0xce401008, 0xc0000a14, 0xce841108,\n    0xc000496c, 0xca400000, 0x6c508000, 0xc0004880, 0x40100000, 0x58000012, 0xc9000000, 0x00000000,\n    0x00000000, 0x59100002, 0xcd000000, 0xc000496e, 0xcbc00000, 0x00000000, 0x00000000, 0x47f50000,\n    0x46610000, 0x6c508000, 0xc0004880, 0x40100000, 0x58000010, 0xc9000000, 0x00000000, 0x00000000,\n    0x41208000, 0xcd000000, 0x6c6c8000, 0x6c544000, 0x42d56000, 0x5aec4a00, 0x582c0004, 0xca000000,\n    0x00000000, 0x00000000, 0xa60016ea, 0x00000000, 0x6c6c8000, 0x6c544000, 0x42d56000, 0x5aec4a00,\n    0xc3000000, 0x582c0004, 0xcf000308, 0x582c0000, 0xcb002018, 0xc3c00000, 0x582c0004, 0xcbc20080,\n    0xc000491a, 0xcf000000, 0xc000493c, 0xcfc00000, 0x582c0008, 0xcb800000, 0x582c000a, 0xca400000,\n    0xc0004930, 0xcf800000, 0xc0004932, 0xce400000, 0x5ffc0000, 0x840001d8, 0x00000000, 0xa7be00e2,\n    0xc2800000, 0x6f206000, 0x47210000, 0x5a204c80, 0x5820000c, 0xca800028, 0x00000000, 0x00000000,\n    0x5ea80000, 0x840000fa, 0x00000000, 0xc161fffe, 0x5955fffe, 0x15400000, 0x00000000, 0x00000000,\n    0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x99006330, 0xc000491a, 0xc9400000, 0x00000000,\n    0xc121fffe, 0x5911fef4, 0x15000000, 0xc0004930, 0xcb800000, 0xc0004932, 0xca400000, 0xc4781110,\n    0xc0004930, 0xcf800000, 0x582c0008, 0xcf800000, 0x582c000a, 0xce400000, 0xc7b6e110, 0x582c0004,\n    0xcf400110, 0x80000078, 0x00000000, 0x6c508000, 0xc0004880, 0x40100000, 0x5800000c, 0xc9000000,\n    0x00000000, 0x00000000, 0x59100002, 0xcd000000, 0xc2000002, 0x582c0004, 0xce000008, 0xc0000838,\n    0xc2500002, 0xce440808, 0x80001430, 0x6c7c8000, 0x6c544000, 0x43d5e000, 0x5bfc4a00, 0x583c0006,\n    0xca000000, 0xc00049a2, 0x00000000, 0xca800001, 0xca400000, 0xc0001008, 0xce800000, 0xc0001006,\n    0xce400000, 0xc000100a, 0xce000000, 0xc2400006, 0xc0001000, 0xce400000, 0xc2600982, 0x5a643b6e,\n    0xc0001002, 0xce400000, 0x583c0024, 0xca400000, 0x00000000, 0xc0001004, 0xce400000, 0xc0004862,\n    0xc2000000, 0xca000080, 0xc360fffe, 0xc0004862, 0xce000000, 0xc0000824, 0xcb440068, 0x00000000,\n    0xc000100e, 0xcf400000, 0xc3801600, 0xc2400200, 0x6e644000, 0xc6781078, 0xc000100c, 0xcf800000,\n    0xc3200a00, 0xc0001010, 0xcf001818, 0xc2e06200, 0xc0001012, 0xcec01840, 0xc2000000, 0x583c0004,\n    0xca002010, 0xc2800000, 0xc0004966, 0xce000000, 0xc6240000, 0xc3000000, 0xc000496a, 0xcf000000,\n    0xc0004974, 0xcf000000, 0xc000493c, 0xcb400000, 0x583c000e, 0x00000000, 0x5f740000, 0x84000168,\n    0xc3400000, 0xcb410040, 0xc3000002, 0xc000496a, 0x5fb40080, 0x8400013a, 0xcf000000, 0x583c000e,\n    0xc2c00000, 0xcac00040, 0xc3800080, 0x4779c000, 0xc0004974, 0xcf800000, 0xc0001012, 0x6fba0000,\n    0xcf801040, 0x6fba0010, 0x43a5c000, 0x5b380006, 0x6f284010, 0xc7a40010, 0x6eec4000, 0x6ef08000,\n    0x432d8000, 0x43358000, 0x5b300008, 0xc0001012, 0xc7100078, 0xcd000078, 0xc2000200, 0xc2c00000,\n    0xdf6d0050, 0x46e16000, 0x46ad6000, 0x8800ffca, 0xc2000000, 0xc0004862, 0xca000268, 0x00000000,\n    0x583c0004, 0xca002010, 0xc3360002, 0xc0001010, 0xce000078, 0xc0001012, 0xcf001b08, 0xc0004974,\n    0xcb800000, 0x00000000, 0x00000000, 0x5fb80000, 0x8400002a, 0x00000000, 0x00000000, 0x00000000,\n    0xa8e2ffc8, 0x00000000, 0xc1220002, 0xd90c0000, 0xc000496c, 0xcac00000, 0x00000000, 0x00000000,\n    0x426dc000, 0x5b380006, 0x6f304010, 0xc7a40010, 0xc0004968, 0xce400000, 0xc000496e, 0xcb400000,\n    0x6ca44000, 0x6e608000, 0x42250000, 0x5a200006, 0x42350000, 0xc0001012, 0xc6100078, 0xcd000078,\n    0x6eee0000, 0xcec01040, 0xc2000200, 0xc2c00000, 0xdf6d0050, 0x46e16000, 0x42b14000, 0x46ad6000,\n    0x8800ffc2, 0xc000493c, 0xcb400000, 0xc0000838, 0xc3100002, 0x5f740000, 0x84000048, 0xcf040808,\n    0xc0004974, 0xcb800000, 0x00000000, 0x00000000, 0x5fb80000, 0x84000052, 0xc0001012, 0xc3360002,\n    0xcf001b08, 0x80000088, 0x583c0022, 0xcb400000, 0xc0004862, 0xca000000, 0x00000000, 0xc0005600,\n    0x40200000, 0xcf400000, 0xc2000000, 0xc0004862, 0xca000268, 0x00000000, 0x583c0004, 0xca002010,\n    0xc3360002, 0xc0001010, 0xce000078, 0xc0001012, 0xcf001b08, 0xc0004968, 0xcbc00000, 0xc0004964,\n    0xca400000, 0xc7e00000, 0x00000000, 0x5e640000, 0x8400fffa, 0xc2000000, 0xc0004974, 0xca400000,\n    0xc000496c, 0xca800000, 0xc000493c, 0xcb800000, 0x42698000, 0x00000000, 0x43b1a000, 0x5ef40080,\n    0x88000182, 0xc0004966, 0xcac00000, 0x6c648000, 0x6c544000, 0x42552000, 0x5a644a00, 0x58240000,\n    0x436da000, 0x4635a000, 0xc2400000, 0xca420080, 0x00000000, 0x00000000, 0x47652000, 0x8800010a,\n    0x432d8000, 0x46318000, 0x8800fff8, 0xc3000000, 0x5b300006, 0x6f304010, 0xc000493a, 0xcf000000,\n    0xc0004932, 0xc2400000, 0xca4000e0, 0x00000000, 0x6fb84010, 0x42792000, 0xc000491e, 0xce400000,\n    0xc0004862, 0xca800000, 0x00000000, 0xc2c0000a, 0xc6e80d78, 0xc7281050, 0xc000491c, 0xce800000,\n    0x6c708000, 0x6c544000, 0x43158000, 0x5b304a00, 0x6f760000, 0x58300004, 0xcf401080, 0x6ffc2000,\n    0x58300004, 0xcfc00110, 0x80000168, 0x6c708000, 0x6c544000, 0x43158000, 0x5b304a00, 0xc2800002,\n    0x58300004, 0xce800008, 0x6c508000, 0xc0004880, 0x40100000, 0x5800000e, 0xc9000000, 0x00000000,\n    0x00000000, 0x59100002, 0xcd000000, 0xc0004816, 0xc8000000, 0x00000000, 0x00000000, 0x5c000000,\n    0x84000072, 0xc11c0000, 0xc000082c, 0xcd040e08, 0xc0004816, 0xc8000000, 0x00000000, 0x00000000,\n    0x5c000000, 0x84000012, 0x00000000, 0x00000000, 0x00000000, 0x8000ffa0, 0xc11c0002, 0xc000082c,\n    0xcd040e08, 0x00000000, 0x00000000, 0x00000000, 0xa8e2ffc8, 0x00000000, 0xc1220002, 0xd90c0000,\n    0x80000a80, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xa8e2ffc8, 0x00000000, 0xc1220002,\n    0xd90c0000, 0xc0004964, 0xca000000, 0x6c7c8000, 0x6c544000, 0x43d5e000, 0x5bfc4a00, 0xdfe40000,\n    0x5e200002, 0x840006a0, 0x00000000, 0x583c0004, 0xc2800000, 0xca820080, 0xc0004930, 0xcac00000,\n    0x00000000, 0x00000000, 0x6eece000, 0x6eefc010, 0x46e8a000, 0xc1000000, 0xdd500041, 0x6d106010,\n    0x4514a000, 0xc1000000, 0xdd514209, 0x4514c000, 0xa9500181, 0xc00049a6, 0xca000000, 0xa94a0003,\n    0x00000000, 0x6e660000, 0x6e660010, 0x46252000, 0x8400014a, 0x00000000, 0xc0004812, 0xc8000000,\n    0x00000000, 0x00000000, 0x5c000000, 0x84000072, 0xc11c0000, 0xc000082c, 0xcd040e08, 0xc0004812,\n    0xc8000000, 0x00000000, 0x00000000, 0x5c000000, 0x84000012, 0x00000000, 0x00000000, 0x00000000,\n    0x8000ffa0, 0xc11c0002, 0xc000082c, 0xcd040e08, 0x6c508000, 0xc0004880, 0x40100000, 0x58000004,\n    0xc9000000, 0x00000000, 0x00000000, 0x59100002, 0xcd000000, 0x6c508000, 0xc0004880, 0x40100000,\n    0x58000006, 0xc9000000, 0x00000000, 0x00000000, 0x41148000, 0xcd000000, 0x800007d0, 0x00000000,\n    0xa95203a1, 0xc0001004, 0xcb800000, 0xc3400000, 0xdd740041, 0x5f740000, 0x840000b8, 0xc1218e08,\n    0x5911baf6, 0x47908000, 0x8400035a, 0x00000000, 0x6c508000, 0xc0004880, 0x40100000, 0x58000008,\n    0xc9000000, 0x00000000, 0x00000000, 0x59100002, 0xcd000000, 0x6c508000, 0xc0004880, 0x40100000,\n    0x5800000a, 0xc9000000, 0x00000000, 0x00000000, 0x41148000, 0xcd000000, 0x800006d0, 0x00000000,\n    0xc000496c, 0xcb000000, 0x583c0026, 0xcac00000, 0xc0004878, 0xc8040000, 0x6c908000, 0x41088000,\n    0x40100000, 0x58000002, 0xca800000, 0x00000000, 0x00000000, 0x6ea90000, 0x5d300008, 0x88000032,\n    0x59300002, 0xc3000000, 0xc5300010, 0x6d104010, 0x40100000, 0xca800000, 0x5c000002, 0xcac00000,\n    0x5d300000, 0x84000022, 0x6f246000, 0x6ae56000, 0xc1000040, 0x46512000, 0x6aa54010, 0x42e96000,\n    0x583c0026, 0xcec00000, 0xc1218e08, 0x5911baf6, 0xc0001004, 0xcd000000, 0x593c0026, 0xc000100e,\n    0xcd000068, 0xc1340000, 0xc0001010, 0xcd001a08, 0xc1200008, 0xa94a0003, 0xc0001012, 0xc1200004,\n    0x59100004, 0xcd0000c0, 0xc1360002, 0xcd001b08, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n    0x00000000, 0xa8e2ffc8, 0x00000000, 0xc1220002, 0xd90c0000, 0xc0001004, 0xc9000000, 0x00000000,\n    0x00000000, 0x47908000, 0x8400009a, 0x00000000, 0x6c508000, 0xc0004880, 0x40100000, 0x58000008,\n    0xc9000000, 0x00000000, 0x00000000, 0x59100002, 0xcd000000, 0x6c508000, 0xc0004880, 0x40100000,\n    0x5800000a, 0xc9000000, 0x00000000, 0x00000000, 0x41148000, 0xcd000000, 0x80000410, 0x00000000,\n    0x6c508000, 0xc0004880, 0x40100000, 0x58000000, 0xc9000000, 0x00000000, 0x00000000, 0x59100002,\n    0xcd000000, 0x6c508000, 0xc0004880, 0x40100000, 0x58000002, 0xc9000000, 0x00000000, 0x00000000,\n    0x41148000, 0xcd000000, 0xc0004930, 0xcd800080, 0xc3000000, 0x583c0008, 0xcf000000, 0x800000e8,\n    0xc0001004, 0xca000000, 0x583c0006, 0xce400000, 0x583c0024, 0xce000000, 0xc0004814, 0xc8000000,\n    0x00000000, 0x00000000, 0x5c000000, 0x8400008a, 0xc001fffe, 0x46400000, 0x84000070, 0xc11c0000,\n    0xc000082c, 0xcd040e08, 0xc0004814, 0xc8000000, 0x00000000, 0x00000000, 0x5c000000, 0x84000012,\n    0x00000000, 0x00000000, 0x00000000, 0x8000ffa0, 0xc11c0002, 0xc000082c, 0xcd040e08, 0xc0004862,\n    0xc2000000, 0xca000080, 0xc000493a, 0xca400000, 0x00000000, 0x00000000, 0x42254000, 0x5ee80200,\n    0x8800fffa, 0xc6e80000, 0xc0004000, 0x58001600, 0x40280000, 0xcb800000, 0x00000000, 0x583c0022,\n    0xcf800000, 0xc0004862, 0xce800080, 0xc0001406, 0xcac00000, 0xc2800002, 0x00000000, 0xc66c1050,\n    0xc6ac0a08, 0xcec00000, 0xc2000000, 0xdf600040, 0x5e600080, 0x8400ffd2, 0xc000491c, 0xca400000,\n    0xc000491e, 0xca800000, 0x99006840, 0xda580000, 0xda980001, 0x00000000, 0xc0004964, 0xcbc00000,\n    0x00000000, 0x00000000, 0x5ffc0000, 0x840000ea, 0xc2000000, 0xdf610050, 0x5e6001fe, 0x8800ffd0,\n    0xc000491a, 0xc9800000, 0xc0004862, 0xc9400000, 0x6d9c6000, 0x459ce000, 0x59dc4c80, 0x990066a0,\n    0xd9580000, 0xd9980001, 0xd9d40000, 0x99006618, 0xc000491c, 0xc1400000, 0xc9420050, 0xc2000000,\n    0xdf600040, 0x5e600080, 0x8400ffd2, 0xc000491c, 0xca400000, 0xc000491e, 0xca800000, 0x99006840,\n    0xda580000, 0xda980001, 0x00000000, 0xc0004970, 0xcb400000, 0x00000000, 0x00000000, 0x5e740082,\n    0x8400e498, 0x00000000, 0x8000bc70, 0x00000000, 0x6c508000, 0xc0004880, 0x40100000, 0x58000016,\n    0xc9000000, 0x00000000, 0x00000000, 0x59100002, 0xcd000000, 0x8000e0c8, 0x6c6c8000, 0x6c544000,\n    0x42d56000, 0x5aec4a00, 0xc000487c, 0xc8040000, 0x00000000, 0x00000000, 0x40080000, 0xca000000,\n    0xc4240000, 0x00000000, 0xa6060108, 0xc3c00000, 0xc2000000, 0x582c000c, 0xca010040, 0x00000000,\n    0x00000000, 0x5a200002, 0xc6100840, 0xcd000840, 0x5e60000e, 0x8400bb58, 0xc2200000, 0x582c0002,\n    0xce001010, 0x582c000c, 0xcfc00840, 0x582c0020, 0xcfc01080, 0x582c0010, 0xc1400000, 0xcd400001,\n    0xcd400001, 0xcd400001, 0xcd400001, 0xcd400001, 0xcd400001, 0xcd400001, 0xcd400001, 0xcd400020,\n    0xc000481a, 0xca000000, 0x00000000, 0x00000000, 0x5a200002, 0xce000000, 0x8000ba90, 0xc2200004,\n    0x582c0002, 0xce001010, 0x582c000c, 0xcfc00840, 0x99006f68, 0x582c0002, 0xc9400000, 0xc1a20000,\n    0x8000ba40, 0xc3e1fffe, 0x597dfffe, 0x593dfef4, 0x94000001, 0x00000000, 0x00000000, 0x00000000,\n    0xc0800000, 0xdf4b0040, 0xc0004900, 0xcb800000, 0xc2000000, 0xc000490a, 0xa78000b0, 0xcbc00000,\n    0xc1000000, 0xd9000001, 0xc1000002, 0xd90c0000, 0x6ff46000, 0x47f5a000, 0x5b744c80, 0xc2400000,\n    0x58340004, 0xca400080, 0xc0004900, 0xce000008, 0x5a640002, 0x58340004, 0xc6500080, 0xcd000080,\n    0xc0004914, 0xca400000, 0xc2000002, 0x6a3d0000, 0x72252000, 0xce400000, 0xc0000408, 0xce000000,\n    0xa78200a8, 0xc0004908, 0xcbc00000, 0xc1000000, 0xd9000001, 0xc1000002, 0xd90c0000, 0x6ff4a000,\n    0x47f5a000, 0x5b744e20, 0xc2800000, 0x58340006, 0xca800080, 0xc2000000, 0xc0004900, 0xce000108,\n    0x5ea80002, 0x58340006, 0xc6900080, 0xcd000080, 0x5a7c0020, 0xc2000002, 0x6a250000, 0xc0000408,\n    0xce000000, 0xdca80001, 0x5ea80000, 0x8400a7f8, 0x00000000, 0xa4800210, 0x00000000, 0xc3c00000,\n    0xc000140e, 0xcbc00020, 0xc3400000, 0xc2400000, 0x6ff86000, 0x47f9c000, 0x5bb84c80, 0x58380008,\n    0xcb400080, 0x58380006, 0xca400080, 0x5f740002, 0x58380008, 0xc7500080, 0xcd000080, 0xc2000000,\n    0x58380004, 0xca020080, 0xc3000000, 0x5838000c, 0xcb000028, 0x5a640002, 0x46250000, 0x8400fff8,\n    0xc2400000, 0x58380006, 0xc6500080, 0xcd000080, 0xc2000000, 0x5838000a, 0xca020080, 0x5b300002,\n    0x5838000c, 0xc7100028, 0xcd000028, 0xc2420020, 0x5a200004, 0x46612000, 0x8400fff8, 0xc2000000,\n    0x5838000a, 0xc6101080, 0xcd001080, 0xc000498c, 0xca400000, 0xc2000002, 0x6a3d0000, 0x72252000,\n    0xce400000, 0x5f740000, 0x84000028, 0xc0004912, 0xca000000, 0xc2c00002, 0x6afd6000, 0x7ec16000,\n    0x76e10000, 0xce000000, 0x5f300020, 0x84000028, 0xc0004924, 0xca000000, 0xc2c00002, 0x6afd6000,\n    0x7ec16000, 0x76e10000, 0xce000000, 0xa4820050, 0xc2400000, 0xc000140e, 0xca408020, 0xc2000002,\n    0xc0004900, 0xce000008, 0xc000490a, 0xce400000, 0xc1000000, 0xd9000001, 0xd8400080, 0xc1000004,\n    0xd9000001, 0xa48402b8, 0x00000000, 0xc3c00000, 0xc000140e, 0xcbc10020, 0xc2800000, 0xc2000000,\n    0x6ff8a000, 0x47f9c000, 0x5bb84e20, 0x58380036, 0xca800080, 0x58380006, 0xca020080, 0xc3400000,\n    0x58380036, 0xcb420080, 0x5aa80002, 0x46290000, 0x8400fff8, 0xc2800000, 0x58380036, 0xc6900080,\n    0xcd000080, 0x5f740002, 0x58380036, 0xc7501080, 0xcd001080, 0xc000498e, 0xca400000, 0xc2000002,\n    0x6a3d0000, 0x72252000, 0xce400000, 0xc000492a, 0xca800000, 0x5e740000, 0x84000028, 0xc0004910,\n    0xca000000, 0xc2c00002, 0x6afd6000, 0x7ec16000, 0x76e10000, 0xce000000, 0x6abd4010, 0xa6800112,\n    0x00000000, 0x5838003a, 0xca000000, 0x58000002, 0xca400000, 0x5838000e, 0x00000000, 0xce000001,\n    0xce400000, 0xc2400000, 0xdd250040, 0xc1000080, 0x46508000, 0xc2400000, 0xc6240080, 0x45250000,\n    0x00000000, 0xc5240004, 0x5d240078, 0xc1000078, 0xc5240004, 0xc6600080, 0x5c000002, 0xce000080,\n    0xc000492a, 0xca000000, 0xc2c00002, 0x6afd6000, 0x72e10000, 0xce000000, 0xc000492c, 0xca000000,\n    0xc2c00002, 0x6afd6000, 0x72e10000, 0xce000000, 0x80000028, 0xc000492c, 0xca000000, 0xc2c00002,\n    0x6afd6000, 0x7ec16000, 0x76e10000, 0xce000000, 0xa4880068, 0xc2c00000, 0xc000140e, 0xcac20020,\n    0xc000490e, 0xca400000, 0xc2000002, 0x6a2d0000, 0x7e010000, 0x76252000, 0xce400000, 0xc0004990,\n    0xca400000, 0xc2000002, 0x6a2d0000, 0x72252000, 0xce400000, 0xa4860050, 0xc2400000, 0xc000140e,\n    0xca418020, 0xc2020002, 0xc0004900, 0xce000108, 0xc0004908, 0xce400000, 0xc1000000, 0xd9000001,\n    0xd8400080, 0xc1000004, 0xd9000001, 0xc0001408, 0xcc800000, 0xc10e0002, 0xd90c0000, 0x8000f738,\n    0xdfbc0001, 0xc0004992, 0x99006fa8, 0xc9400000, 0xc7d80000, 0x00000000, 0xc5700000, 0x5ef00020,\n    0x88000140, 0x6f346000, 0x4735a000, 0x5b744c80, 0x58340008, 0xc2400000, 0xca400080, 0x00000000,\n    0xc2000000, 0x5a640002, 0xc6500080, 0xcd000080, 0x58340004, 0xca000080, 0x00000000, 0x00000000,\n    0x5e200002, 0xc6100080, 0xcd000080, 0xc0004912, 0xca800000, 0xc2400002, 0x6a712000, 0x72694000,\n    0xce800000, 0x5e200000, 0x8400003a, 0xc000480a, 0xca000000, 0xc0000408, 0xca800000, 0x76610000,\n    0x00000000, 0x72294000, 0xce800000, 0x80000020, 0xc0004914, 0xca000000, 0x7e412000, 0x00000000,\n    0x76610000, 0xce000000, 0x800000b0, 0x6ef4a000, 0x46f5a000, 0x5b744e20, 0x58340036, 0xc2400000,\n    0xca420080, 0x00000000, 0xc2000000, 0x5a640002, 0xc6501080, 0xcd001080, 0x58340006, 0xca000080,\n    0x00000000, 0x00000000, 0x5a200002, 0xc6100080, 0xcd000080, 0xc0004910, 0xca400000, 0xc2000002,\n    0x6a2d0000, 0x72252000, 0xce400000, 0xc2000002, 0x6a310000, 0xc000042a, 0xce000000, 0xc1040002,\n    0xd90c0000, 0x00000000, 0x8000f4a0, 0x00000000, 0xc4980930, 0x9d000000, 0xc5580030, 0xc0000838,\n    0xcd840000, 0xc1440200, 0xc1c01600, 0xc55c1078, 0xc000100e, 0x9d000000, 0xcd800000, 0xc000100c,\n    0xcdc00000, 0xc0004862, 0xc9c00000, 0x00000000, 0x00000000, 0xd9d80001, 0xc0005600, 0x401c0000,\n    0x5dc05800, 0x8800fffa, 0x5c000200, 0xcd800000, 0xc1f0000a, 0x71d4a000, 0xdd980000, 0xdd9c0001,\n    0x41d8e000, 0xc5d40268, 0xc0001010, 0xcd400000, 0x6c9c8000, 0x449ce000, 0x449ce000, 0x59dc0004,\n    0xc1601260, 0xc5d40268, 0x9d000000, 0xc0001012, 0xcd400000, 0x00000000, 0x00000000, 0xd9580000,\n    0x6d586000, 0x4558c000, 0x59984c80, 0xd9980001, 0x5818000a, 0xc1800000, 0xc9800080, 0xc0005400,\n    0x6d5ca000, 0x401c0000, 0x40180000, 0xc9400000, 0x58000002, 0x00000000, 0xc9c00000, 0xc0004930,\n    0xcd400000, 0xc0004932, 0xcdc00000, 0x59980004, 0xc1c20020, 0xb59cfff8, 0x00000000, 0xc1800000,\n    0xdd9c0001, 0x581c000a, 0xcd800080, 0x581c000c, 0xc1800000, 0xc9800028, 0xc1c00002, 0xdd940000,\n    0x69d4e000, 0x5d980002, 0xcd800028, 0xc0004924, 0xc9800000, 0x00000000, 0x9d000000, 0x00000000,\n    0x71d8c000, 0xcd800000, 0xc000492a, 0xc9400000, 0xc1c00002, 0x69d8e000, 0x7dc0c000, 0x7594a000,\n    0xcd400000, 0xc000492c, 0xc9400000, 0xdd800001, 0x5800003a, 0x75d4a000, 0x840000f0, 0xc9400001,\n    0xc9800000, 0xdd800001, 0x5800000e, 0x00000000, 0xcd400001, 0xcd800000, 0xc1800000, 0xdd190040,\n    0xc1000080, 0x45908000, 0xc1800000, 0xc5580080, 0x4518a000, 0x00000000, 0xc5180004, 0x5d180078,\n    0xc1000078, 0xc5180004, 0xc5940080, 0x5c000002, 0xcd400080, 0xc000492c, 0xc9400000, 0xc000492a,\n    0xc9800000, 0x71d4a000, 0xc000492c, 0xcd400000, 0x71d8c000, 0xc000492a, 0xcd800000, 0x9cc00000,\n    0x00000000, 0x00000000, 0x00000000, 0xc0004862, 0xc9800000, 0x00000000, 0xc1c00200, 0x4194c000,\n    0x45d8e000, 0x8800fffa, 0xc5d80000, 0xc0004862, 0xcd800000, 0xc0001406, 0xc9800000, 0xc1c00002,\n    0x9d000000, 0xc5d80a08, 0xc5581050, 0xcd800000, 0xc0004930, 0xc9800000, 0xc0004932, 0xc9c00000,\n    0xc140000e, 0xc5581c20, 0xdd940000, 0xc0005600, 0x40140000, 0x5d405800, 0x8800fffa, 0x5c000200,\n    0xcd800000, 0x58000002, 0x5d405800, 0x8800fffa, 0x5c000200, 0xcdc00000, 0xdd540000, 0xc1c00000,\n    0x58140006, 0xc9c20080, 0xc1800000, 0x58140000, 0xc98000e0, 0x6ddc2000, 0xc000491e, 0x41d8e000,\n    0xcdc00000, 0xdd980000, 0xc1c00022, 0xc5d80d78, 0xdd940001, 0xc5581c20, 0xc000491c, 0xcd800000,\n    0xdd540000, 0xc1c00000, 0x58140006, 0xc9c20080, 0xc1800000, 0x58140004, 0xc9820080, 0x00000000,\n    0x59dc0002, 0x459cc000, 0x8400fff8, 0xc1c00000, 0x9d000000, 0x58140006, 0xc5d81080, 0xcd801080,\n    0xc0004860, 0xc9400000, 0xc1820080, 0xc1d00002, 0x58146b00, 0xd5800000, 0x58000002, 0xd5800001,\n    0x59540004, 0xb558fff8, 0xc0004860, 0xc1400000, 0xcd400000, 0xdd980001, 0x9d000000, 0xdd940000,\n    0xc0001404, 0xcdc00808, 0xc1c00000, 0xc1800200, 0x5d980004, 0xdf5d0050, 0x45d8a000, 0x8800ffda,\n    0xdd800001, 0x5800000e, 0x00000000, 0xc9400001, 0xc9800000, 0xc1c00002, 0xc5d43f08, 0xc5d81e08,\n    0xc0004862, 0xc9c00000, 0x00000000, 0x00000000, 0x581c5600, 0x5dc05800, 0x8800fffa, 0x5c000200,\n    0xcd400000, 0x58000002, 0x5dc05800, 0x8800fffa, 0x5c000200, 0xcd800000, 0xc0004862, 0xc9c00000,\n    0x00000000, 0xc15004c0, 0xc5d40068, 0xdd9c0000, 0xc5d41c20, 0xc1c00000, 0xdd800001, 0x58000038,\n    0xc9c00080, 0xdd800001, 0xc1800000, 0x58000002, 0xc98000e0, 0x6ddc2000, 0xc000491c, 0x41d8e000,\n    0xcd400001, 0xcdc00000, 0xdd940001, 0xc1c00000, 0x58140038, 0xc9c00080, 0xc1800000, 0x58140006,\n    0xc9820080, 0x00000000, 0x59dc0002, 0x459cc000, 0x8400fff8, 0xc1c00000, 0x9d000000, 0x58140038,\n    0xc5d80080, 0xcd800080, 0xc1c00000, 0xdf5c0040, 0x5ddc0080, 0x8400ffd2, 0x00000000, 0x9d000000,\n    0x00000000, 0x00000000, 0x00000000, 0xc160fffe, 0xc0000a10, 0xc9440068, 0xc1a0fffe, 0x59980e28,\n    0xc000100c, 0xcd400000, 0xc000100e, 0xcd800000, 0xc0004962, 0xc9800000, 0x00000000, 0xc170000a,\n    0x7194a000, 0x6c988000, 0x4498c000, 0x4498c000, 0x59980004, 0xc5940278, 0xc0001010, 0xcd400000,\n    0xc0004946, 0xc9400000, 0x00000000, 0x00000000, 0x6d58a000, 0x6d5c4000, 0x45d8c000, 0x4558c000,\n    0xc000494a, 0xc9400000, 0xc0004948, 0xc9c00000, 0x4194c000, 0xc1400012, 0xc55c1820, 0x9d000000,\n    0xc59c0270, 0xc0001012, 0xcdc00000, 0xc1400000, 0x58000014, 0xc9410040, 0xc0004950, 0xc9c00000,\n    0xc5580000, 0xc5940840, 0xc5581080, 0xd9940000, 0xc000493c, 0xc9400000, 0xc0004954, 0xc9800000,\n    0x59dc00a8, 0x455ce000, 0x41d8e000, 0x5d5c0030, 0x8800fff8, 0xc1c00030, 0xc1800000, 0xc5d84030,\n    0xc1400000, 0xc5d40010, 0x5dd40002, 0x8400005a, 0x5dd40004, 0x84000082, 0x5dd40006, 0x840000aa,\n    0x5dd80026, 0x840000d2, 0xdd540000, 0xdd800001, 0x58000008, 0x40180000, 0xcd400000, 0x59980002,\n    0x8000ffa8, 0xdd540000, 0xdd800001, 0x58000008, 0x40180000, 0xcd4000c0, 0x59980002, 0x8000ff70,\n    0xdd540000, 0xdd800001, 0x58000008, 0x40180000, 0xcd400080, 0x59980002, 0x8000ff38, 0xdd540000,\n    0xdd800001, 0x58000008, 0x40180000, 0xcd400040, 0x59980002, 0x8000ff00, 0x00000000, 0x9d000000,\n    0x00000000, 0x00000000, 0x00000000, 0x58000014, 0xc9400000, 0xc0004954, 0xc9c00000, 0xc0004950,\n    0xc9400080, 0xdd800001, 0x5800002a, 0x5d9c0000, 0x8400003a, 0x5d9c0002, 0x8400003a, 0x5d9c0004,\n    0x84000052, 0xc55b0040, 0xc55c08c0, 0xcd800041, 0xcdc008c0, 0x80000048, 0xcd400000, 0x80000038,\n    0xc55900c0, 0xc55c1840, 0xcd8000c1, 0xcdc01840, 0x80000010, 0xc55a0080, 0xc55c1080, 0xcd800081,\n    0xcdc01080, 0x9d000000, 0x00000000, 0x00000000, 0x00000000, 0xc1e00000, 0xa540fffa, 0xc0000a14,\n    0xc1a20002, 0x9d000000, 0xcd841108, 0xc0000a1c, 0xcdc41040, 0x59540002, 0x6994e018, 0x61c0c008,\n    0x4194a000, 0x5d940040, 0x8800fffa, 0xc5940000, 0x9d000000, 0xcd400000, 0x00000000, 0x00000000,\n};\n\nstatic unsigned int firmware_binary_data[] = {\n};\n\n\n#endif  //  IFXMIPS_PTM_FW_DANUBE_H\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-ptm/src/ifxmips_ptm_fw_regs_adsl.h",
    "content": "/******************************************************************************\n**\n** FILE NAME    : ifxmips_ptm_fw_regs_adsl.h\n** PROJECT      : UEIP\n** MODULES      : PTM\n**\n** DATE         : 7 Jul 2009\n** AUTHOR       : Xu Liang\n** DESCRIPTION  : PTM driver header file (firmware register for ADSL)\n** COPYRIGHT    :       Copyright (c) 2006\n**                      Infineon Technologies AG\n**                      Am Campeon 1-12, 85579 Neubiberg, Germany\n**\n**    This program is free software; you can redistribute it and/or modify\n**    it under the terms of the GNU General Public License as published by\n**    the Free Software Foundation; either version 2 of the License, or\n**    (at your option) any later version.\n**\n** HISTORY\n** $Date        $Author         $Comment\n** 07 JUL 2009  Xu Liang        Init Version\n*******************************************************************************/\n\n\n\n#ifndef IFXMIPS_PTM_FW_REGS_ADSL_H\n#define IFXMIPS_PTM_FW_REGS_ADSL_H\n\n\n\n#if defined(CONFIG_DANUBE)\n  #include \"ifxmips_ptm_fw_regs_danube.h\"\n#elif defined(CONFIG_AMAZON_SE)\n  #include \"ifxmips_ptm_fw_regs_amazon_se.h\"\n#elif defined(CONFIG_AR9)\n  #include \"ifxmips_ptm_fw_regs_ar9.h\"\n#elif defined(CONFIG_VR9)\n  #error VR9 is not ADSL PTM mode!\n#else\n  #error Platform is not specified!\n#endif\n\n\n\n/*\n *  MIB Table Maintained by Firmware\n */\n\nstruct wan_mib_table {\n    unsigned int            wrx_correct_pdu;            /* 0 */\n    unsigned int            wrx_correct_pdu_bytes;      /* 1 */\n    unsigned int            wrx_tccrc_err_pdu;          /* 2 */\n    unsigned int            wrx_tccrc_err_pdu_bytes;    /* 3 */\n    unsigned int            wrx_ethcrc_err_pdu;         /* 4 */\n    unsigned int            wrx_ethcrc_err_pdu_bytes;   /* 5 */\n    unsigned int            wrx_nodesc_drop_pdu;        /* 6 */\n    unsigned int            wrx_len_violation_drop_pdu; /* 7 */\n    unsigned int            wrx_idle_bytes;             /* 8 */\n    unsigned int            wrx_nonidle_cw;             /* 9 */\n    unsigned int            wrx_idle_cw;                /* A */\n    unsigned int            wrx_err_cw;                 /* B */\n    unsigned int            wtx_total_pdu;              /* C */\n    unsigned int            wtx_total_bytes;            /* D */\n    unsigned int            res0;                       /* E */\n    unsigned int            res1;                       /* F */\n};\n\n\n/*\n *  Host-PPE Communication Data Structure\n */\n\n#if defined(__BIG_ENDIAN)\n\n  struct fw_ver_id {\n    unsigned int family         :4;\n    unsigned int fwtype         :4;\n    unsigned int interface      :4;\n    unsigned int fwmode         :4;\n    unsigned int major          :8;\n    unsigned int minor          :8;\n  };\n\n  struct wrx_port_cfg_status {\n    /* 0h */\n    unsigned int mfs            :16;\n    unsigned int res0           :12;\n    unsigned int dmach          :3;\n    unsigned int res1           :1;\n\n    /* 1h */\n    unsigned int res2           :14;\n    unsigned int local_state    :2;     //  init with 0, written by firmware only\n    unsigned int res3           :15;\n    unsigned int partner_state  :1;     //  init with 0, written by firmware only\n\n  };\n\n  struct wrx_dma_channel_config {\n    /*  0h  */\n    unsigned int res3           :1;\n    unsigned int res4           :2;\n    unsigned int res5           :1;\n    unsigned int desba          :28;\n    /*  1h  */\n    unsigned int res1           :16;\n    unsigned int res2           :16;\n    /*  2h  */\n    unsigned int deslen         :16;\n    unsigned int vlddes         :16;\n  };\n\n  struct wtx_port_cfg {\n    /* 0h */\n    unsigned int tx_cwth2       :8;\n    unsigned int tx_cwth1       :8;\n    unsigned int res0           :16;\n  };\n\n  struct wtx_dma_channel_config {\n    /*  0h  */\n    unsigned int res3           :1;\n    unsigned int res4           :2;\n    unsigned int res5           :1;\n    unsigned int desba          :28;\n\n    /*  1h  */\n    unsigned int res1           :16;\n    unsigned int res2           :16;\n\n    /*  2h  */\n    unsigned int deslen         :16;\n    unsigned int vlddes         :16;\n  };\n\n  struct eth_efmtc_crc_cfg {\n    /*  0h  */\n    unsigned int res0               :6;\n    unsigned int tx_eth_crc_gen     :1;\n    unsigned int tx_tc_crc_gen      :1;\n    unsigned int tx_tc_crc_len      :8;\n    unsigned int res1               :5;\n    unsigned int rx_eth_crc_present :1;\n    unsigned int rx_eth_crc_check   :1;\n    unsigned int rx_tc_crc_check    :1;\n    unsigned int rx_tc_crc_len      :8;\n  };\n\n  /* DMA descriptor */\n  struct rx_descriptor {\n    /*  0 - 3h  */\n    unsigned int own            :1;\n    unsigned int c              :1;\n    unsigned int sop            :1;\n    unsigned int eop            :1;\n    unsigned int res1           :3;\n    unsigned int byteoff        :2;\n    unsigned int res2           :2;\n    unsigned int id             :4;\n    unsigned int err            :1;\n    unsigned int datalen        :16;\n    /*  4 - 7h  */\n    unsigned int res3           :4;\n    unsigned int dataptr        :28;\n  };\n\n  struct tx_descriptor {\n    /*  0 - 3h  */\n    unsigned int own            :1;\n    unsigned int c              :1;\n    unsigned int sop            :1;\n    unsigned int eop            :1;\n    unsigned int byteoff        :5;\n    unsigned int res1           :5;\n    unsigned int iscell         :1;\n    unsigned int clp            :1;\n    unsigned int datalen        :16;\n    /*  4 - 7h  */\n    unsigned int res2           :4;\n    unsigned int dataptr        :28;\n  };\n\n#else /* defined(__BIG_ENDIAN) */\n\n  struct wrx_port_cfg_status {\n    /* 0h */\n    unsigned int res1           :1;\n    unsigned int dmach          :3;\n    unsigned int res0           :12;\n    unsigned int mfs            :16;\n\n    /* 1h */\n    unsigned int partner_state  :1;\n    unsigned int res3           :15;\n    unsigned int local_state    :2;\n    unsigned int res2           :14;\n  };\n\n  struct wrx_dma_channel_config {\n    /*  0h  */\n    unsigned int desba          :28;\n    unsigned int res5           :1;\n    unsigned int res4           :2;\n    unsigned int res3           :1;\n    /*  1h  */\n    unsigned int res2           :16;\n    unsigned int res1           :16;\n    /*  2h  */\n    unsigned int vlddes         :16;\n    unsigned int deslen         :16;\n  };\n\n  struct wtx_port_cfg {\n    /* 0h */\n    unsigned int res0           :16;\n    unsigned int tx_cwth1       :8;\n    unsigned int tx_cwth2       :8;\n  };\n\n  struct wtx_dma_channel_config {\n    /*  0h  */\n    unsigned int desba          :28;\n    unsigned int res5           :1;\n    unsigned int res4           :2;\n    unsigned int res3           :1;\n    /*  1h  */\n    unsigned int res2           :16;\n    unsigned int res1           :16;\n    /*  2h  */\n    unsigned int vlddes         :16;\n    unsigned int deslen         :16;\n  };\n\n  struct eth_efmtc_crc_cfg {\n    /*  0h  */\n    unsigned int rx_tc_crc_len      :8;\n    unsigned int rx_tc_crc_check    :1;\n    unsigned int rx_eth_crc_check   :1;\n    unsigned int rx_eth_crc_present :1;\n    unsigned int res1               :5;\n    unsigned int tx_tc_crc_len      :8;\n    unsigned int tx_tc_crc_gen      :1;\n    unsigned int tx_eth_crc_gen     :1;\n    unsigned int res0               :6;\n  };\n\n  /* DMA descriptor */\n  struct rx_descriptor {\n    /*  4 - 7h  */\n    unsigned int dataptr        :28;\n    unsigned int res3           :4;\n    /*  0 - 3h  */\n    unsigned int datalen        :16;\n    unsigned int err            :1;\n    unsigned int id             :4;\n    unsigned int res2           :2;\n    unsigned int byteoff        :2;\n    unsigned int res1           :3;\n    unsigned int eop            :1;\n    unsigned int sop            :1;\n    unsigned int c              :1;\n    unsigned int own            :1;\n  };\n\n  struct tx_descriptor {\n    /*  4 - 7h  */\n    unsigned int dataptr        :28;\n    unsigned int res2           :4;\n    /*  0 - 3h  */\n    unsigned int datalen        :16;\n    unsigned int clp            :1;\n    unsigned int iscell         :1;\n    unsigned int res1           :5;\n    unsigned int byteoff        :5;\n    unsigned int eop            :1;\n    unsigned int sop            :1;\n    unsigned int c              :1;\n    unsigned int own            :1;\n  };\n#endif  /* defined(__BIG_ENDIAN) */\n\n\n\n#endif  //  IFXMIPS_PTM_FW_REGS_ADSL_H\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-ptm/src/ifxmips_ptm_fw_regs_amazon_se.h",
    "content": "/******************************************************************************\n**\n** FILE NAME    : ifxmips_ptm_fw_regs_amazon_se.h\n** PROJECT      : UEIP\n** MODULES      : PTM\n**\n** DATE         : 7 Jul 2009\n** AUTHOR       : Xu Liang\n** DESCRIPTION  : PTM driver header file (firmware register for Amazon-SE)\n** COPYRIGHT    :       Copyright (c) 2006\n**                      Infineon Technologies AG\n**                      Am Campeon 1-12, 85579 Neubiberg, Germany\n**\n**    This program is free software; you can redistribute it and/or modify\n**    it under the terms of the GNU General Public License as published by\n**    the Free Software Foundation; either version 2 of the License, or\n**    (at your option) any later version.\n**\n** HISTORY\n** $Date        $Author         $Comment\n** 07 JUL 2009  Xu Liang        Init Version\n*******************************************************************************/\n\n\n\n#ifndef IFXMIPS_PTM_FW_REGS_AMAZON_SE_H\n#define IFXMIPS_PTM_FW_REGS_AMAZON_SE_H\n\n\n\n/*\n *  Host-PPE Communication Data Address Mapping\n */\n#define FW_VER_ID                       ((volatile struct fw_ver_id *)              SB_BUFFER(0x2401))\n#define CFG_WAN_WRDES_DELAY             SB_BUFFER(0x2404)\n#define CFG_WRX_DMACH_ON                SB_BUFFER(0x2405)\n#define CFG_WTX_DMACH_ON                SB_BUFFER(0x2406)\n#define CFG_WRX_LOOK_BITTH              SB_BUFFER(0x2407)\n#define CFG_ETH_EFMTC_CRC               ((volatile struct eth_efmtc_crc_cfg *)      SB_BUFFER(0x2408))\n#define WAN_MIB_TABLE                   ((volatile struct wan_mib_table*)           SB_BUFFER(0x2440))\n#define WRX_PORT_CONFIG(i)              ((volatile struct wrx_port_cfg_status*)     SB_BUFFER(0x2500 + (i) * 20))\n#define WRX_DMA_CHANNEL_CONFIG(i)       ((volatile struct wrx_dma_channel_config*)  SB_BUFFER(0x2640 + (i) * 7))\n#define WTX_PORT_CONFIG(i)              ((volatile struct wtx_port_cfg*)            SB_BUFFER(0x2710 + (i) * 31))\n#define WTX_DMA_CHANNEL_CONFIG(i)       ((volatile struct wtx_dma_channel_config*)  SB_BUFFER(0x2711 + (i) * 31))\n\n\n\n#endif  //  IFXMIPS_PTM_FW_REGS_AMAZON_SE_H\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-ptm/src/ifxmips_ptm_fw_regs_ar9.h",
    "content": "/******************************************************************************\n**\n** FILE NAME    : ifxmips_ptm_fw_regs_ar9.h\n** PROJECT      : UEIP\n** MODULES      : PTM\n**\n** DATE         : 7 Jul 2009\n** AUTHOR       : Xu Liang\n** DESCRIPTION  : PTM driver header file (firmware register for AR9)\n** COPYRIGHT    :       Copyright (c) 2006\n**                      Infineon Technologies AG\n**                      Am Campeon 1-12, 85579 Neubiberg, Germany\n**\n**    This program is free software; you can redistribute it and/or modify\n**    it under the terms of the GNU General Public License as published by\n**    the Free Software Foundation; either version 2 of the License, or\n**    (at your option) any later version.\n**\n** HISTORY\n** $Date        $Author         $Comment\n** 07 JUL 2009  Xu Liang        Init Version\n*******************************************************************************/\n\n\n\n#ifndef IFXMIPS_PTM_FW_REGS_AR9_H\n#define IFXMIPS_PTM_FW_REGS_AR9_H\n\n\n\n/*\n *  Host-PPE Communication Data Address Mapping\n */\n#define FW_VER_ID                       ((volatile struct fw_ver_id *)              SB_BUFFER(0x2001))\n#define CFG_WAN_WRDES_DELAY             SB_BUFFER(0x2404)\n#define CFG_WRX_DMACH_ON                SB_BUFFER(0x2405)\n#define CFG_WTX_DMACH_ON                SB_BUFFER(0x2406)\n#define CFG_WRX_LOOK_BITTH              SB_BUFFER(0x2407)\n#define CFG_ETH_EFMTC_CRC               ((volatile struct eth_efmtc_crc_cfg *)      SB_BUFFER(0x2408))\n#define WAN_MIB_TABLE                   ((volatile struct wan_mib_table*)           SB_BUFFER(0x2440))\n#define WRX_PORT_CONFIG(i)              ((volatile struct wrx_port_cfg_status*)     SB_BUFFER(0x3F00 + (i) * 20))\n#define WRX_DMA_CHANNEL_CONFIG(i)       ((volatile struct wrx_dma_channel_config*)  SB_BUFFER(0x2640 + (i) * 7))\n#define WTX_PORT_CONFIG(i)              ((volatile struct wtx_port_cfg*)            SB_BUFFER(0x3B00 + (i) * 31))\n#define WTX_DMA_CHANNEL_CONFIG(i)       ((volatile struct wtx_dma_channel_config*)  SB_BUFFER(0x3B01 + (i) * 31))\n\n\n\n#endif  //  IFXMIPS_PTM_FW_REGS_AR9_H\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-ptm/src/ifxmips_ptm_fw_regs_danube.h",
    "content": "/******************************************************************************\n**\n** FILE NAME    : ifxmips_ptm_fw_regs_danube.h\n** PROJECT      : UEIP\n** MODULES      : PTM\n**\n** DATE         : 7 Jul 2009\n** AUTHOR       : Xu Liang\n** DESCRIPTION  : PTM driver header file (firmware register for Danube)\n** COPYRIGHT    :       Copyright (c) 2006\n**                      Infineon Technologies AG\n**                      Am Campeon 1-12, 85579 Neubiberg, Germany\n**\n**    This program is free software; you can redistribute it and/or modify\n**    it under the terms of the GNU General Public License as published by\n**    the Free Software Foundation; either version 2 of the License, or\n**    (at your option) any later version.\n**\n** HISTORY\n** $Date        $Author         $Comment\n** 07 JUL 2009  Xu Liang        Init Version\n*******************************************************************************/\n\n\n\n#ifndef IFXMIPS_PTM_FW_REGS_DANUBE_H\n#define IFXMIPS_PTM_FW_REGS_DANUBE_H\n\n\n\n/*\n *  Host-PPE Communication Data Address Mapping\n */\n#define FW_VER_ID                       ((volatile struct fw_ver_id *)              SB_BUFFER(0x2001))\n#define CFG_WAN_WRDES_DELAY             SB_BUFFER(0x2404)\n#define CFG_WRX_DMACH_ON                SB_BUFFER(0x2405)\n#define CFG_WTX_DMACH_ON                SB_BUFFER(0x2406)\n#define CFG_WRX_LOOK_BITTH              SB_BUFFER(0x2407)\n#define CFG_ETH_EFMTC_CRC               ((volatile struct eth_efmtc_crc_cfg *)      SB_BUFFER(0x2408))\n#define WAN_MIB_TABLE                   ((volatile struct wan_mib_table*)           SB_BUFFER(0x2440))\n#define WRX_PORT_CONFIG(i)              ((volatile struct wrx_port_cfg_status*)     SB_BUFFER(0x2500 + (i) * 20))\n#define WRX_DMA_CHANNEL_CONFIG(i)       ((volatile struct wrx_dma_channel_config*)  SB_BUFFER(0x2640 + (i) * 7))\n#define WTX_PORT_CONFIG(i)              ((volatile struct wtx_port_cfg*)            SB_BUFFER(0x2710 + (i) * 31))\n#define WTX_DMA_CHANNEL_CONFIG(i)       ((volatile struct wtx_dma_channel_config*)  SB_BUFFER(0x2711 + (i) * 31))\n\n\n\n#endif  //  IFXMIPS_PTM_FW_REGS_DANUBE_H\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-ptm/src/ifxmips_ptm_fw_regs_vdsl.h",
    "content": "/******************************************************************************\n**\n** FILE NAME    : ifxmips_ptm_fw_regs_vdsl.h\n** PROJECT      : UEIP\n** MODULES      : PTM\n**\n** DATE         : 7 Jul 2009\n** AUTHOR       : Xu Liang\n** DESCRIPTION  : PTM driver header file (firmware register for VDSL)\n** COPYRIGHT    :       Copyright (c) 2006\n**                      Infineon Technologies AG\n**                      Am Campeon 1-12, 85579 Neubiberg, Germany\n**\n**    This program is free software; you can redistribute it and/or modify\n**    it under the terms of the GNU General Public License as published by\n**    the Free Software Foundation; either version 2 of the License, or\n**    (at your option) any later version.\n**\n** HISTORY\n** $Date        $Author         $Comment\n** 07 JUL 2009  Xu Liang        Init Version\n*******************************************************************************/\n\n\n\n#ifndef IFXMIPS_PTM_FW_REGS_VDSL_H\n#define IFXMIPS_PTM_FW_REGS_VDSL_H\n\n\n\n#if defined(CONFIG_DANUBE)\n  #error Danube is not VDSL PTM mode!\n#elif defined(CONFIG_AMAZON_SE)\n  #error Amazon-SE is not VDSL PTM mode!\n#elif defined(CONFIG_AR9)\n  #error AR9 is not VDSL PTM mode!\n#elif defined(CONFIG_VR9)\n  #include \"ifxmips_ptm_fw_regs_vr9.h\"\n#else\n  #error Platform is not specified!\n#endif\n\n\n\n/*\n *  MIB Table Maintained by Firmware\n */\n\nstruct wan_rx_mib_table {\n    unsigned int            res1[2];\n    unsigned int            wrx_dropdes_pdu;\n    unsigned int            wrx_total_bytes;\n    unsigned int            res2[4];\n    //  wrx_total_pdu is implemented with hardware counter (not used by PTM TC)\n    //  check register \"TC_RX_MIB_CMD\"\n    //  \"HEC_INC\" used to increase preemption Gamma interface (wrx_total_pdu)\n    //  \"AIIDLE_INC\" used to increase normal Gamma interface (wrx_total_pdu)\n};\n\nstruct wan_tx_mib_table {\n    //unsigned int            wtx_total_pdu;        //  version before 0.26\n    //unsigned int            small_pkt_drop_cnt;\n    //unsigned int            total_pkt_drop_cnt;\n    unsigned int            wrx_total_pdu;          //  version 0.26 and onwards\n    unsigned int            wrx_total_bytes;\n    unsigned int            wtx_total_pdu;\n    unsigned int            wtx_total_bytes;\n\n    unsigned int            wtx_cpu_dropsmall_pdu;\n    unsigned int            wtx_cpu_dropdes_pdu;\n    unsigned int            wtx_fast_dropsmall_pdu;\n    unsigned int            wtx_fast_dropdes_pdu;\n};\n\n\n/*\n *  Host-PPE Communication Data Structure\n */\n\n#if defined(__BIG_ENDIAN)\n\n  struct fw_ver_id_new {    //  @2000\n    /*  0 - 3h  */\n    unsigned int family         :4;\n    unsigned int package        :4;\n    unsigned int major          :8;\n    unsigned int middle         :8;\n    unsigned int minor          :8;\n    /*  4 - 7h  */\n    unsigned int features       :32;\n  };\n\n  struct fw_ver_id {        //  @2001\n    unsigned int family         :4;\n    unsigned int fwtype         :4;\n    unsigned int interface      :4;\n    unsigned int fwmode         :4;\n    unsigned int major          :8;\n    unsigned int minor          :8;\n  };\n\n  struct cfg_std_data_len {\n    unsigned int res1           :14;\n    unsigned int byte_off       :2;     //  byte offset in RX DMA channel\n    unsigned int data_len       :16;    //  data length for standard size packet buffer\n  };\n\n  struct tx_qos_cfg {\n    unsigned int time_tick      :16;    //  number of PP32 cycles per basic time tick\n    unsigned int overhd_bytes   :8;     //  number of overhead bytes per packet in rate shaping\n    unsigned int eth1_eg_qnum   :4;     //  number of egress QoS queues (< 8);\n    unsigned int eth1_burst_chk :1;     //  always 1, more accurate WFQ\n    unsigned int eth1_qss       :1;     //  1: FW QoS, 0: HW QoS\n    unsigned int shape_en       :1;     //  1: enable rate shaping, 0: disable\n    unsigned int wfq_en         :1;     //  1: WFQ enabled, 0: strict priority enabled\n  };\n\n  struct psave_cfg {\n    unsigned int res1           :15;\n    unsigned int start_state    :1;     //  1: start from partial PPE reset, 0: start from full PPE reset\n    unsigned int res2           :15;\n    unsigned int sleep_en       :1;     //  1: enable sleep mode, 0: disable sleep mode\n  };\n\n  struct eg_bwctrl_cfg {\n    unsigned int fdesc_wm       :16;    //  if free descriptors in QoS/Swap channel is less than this watermark, large size packets are discarded\n    unsigned int class_len      :16;    //  if packet length is not less than this value, the packet is recognized as large packet\n  };\n\n  struct test_mode {\n    unsigned int res1           :30;\n    unsigned int mib_clear_mode :1;     //  1: MIB counter is cleared with TPS-TC software reset, 0: MIB counter not cleared\n    unsigned int test_mode      :1;     //  1: test mode, 0: normal mode\n  };\n\n  struct gpio_mode {\n    unsigned int res1           :3;\n    unsigned int gpio_bit_bc1   :5;\n    unsigned int res2           :3;\n    unsigned int gpio_bit_bc0   :5;\n\n    unsigned int res3           :7;\n    unsigned int gpio_bc1_en    :1;\n\n    unsigned int res4           :7;\n    unsigned int gpio_bc0_en    :1;\n  };\n\n  struct gpio_wm_cfg {\n    unsigned int stop_wm_bc1    :8;\n    unsigned int start_wm_bc1   :8;\n    unsigned int stop_wm_bc0    :8;\n    unsigned int start_wm_bc0   :8;\n  };\n\n  struct rx_bc_cfg {\n    unsigned int res1           :14;\n    unsigned int local_state    :2;     //  0: local receiver is \"Looking\", 1: local receiver is \"Freewheel Sync False\", 2: local receiver is \"Synced\", 3: local receiver is \"Freewheel Sync Truee\"\n    unsigned int res2           :15;\n    unsigned int remote_state   :1;     //  0: remote receiver is \"Out-of-Sync\", 1: remote receiver is \"Synced\"\n    unsigned int to_false_th    :16;    //  the number of consecutive \"Miss Sync\" for leaving \"Freewheel Sync False\" to \"Looking\" (default 3)\n    unsigned int to_looking_th  :16;    //  the number of consecutive \"Miss Sync\" for leaving \"Freewheel Sync True\" to \"Freewheel Sync False\" (default 7)\n    unsigned int res_word[30];\n  };\n\n  struct rx_gamma_itf_cfg {\n    unsigned int res1           :31;\n    unsigned int receive_state  :1;     //  0: \"Out-of-Fragment\", 1: \"In-Fragment\"\n    unsigned int res2           :16;\n    unsigned int rx_min_len     :8;     //  min length of packet, padding if packet length is smaller than this value\n    unsigned int rx_pad_en      :1;     //  0:  padding disabled, 1: padding enabled\n    unsigned int res3           :2;\n    unsigned int rx_eth_fcs_ver_dis :1; //  0: ETH FCS verification is enabled, 1: disabled\n    unsigned int rx_rm_eth_fcs      :1; //  0: ETH FCS field is not removed, 1: ETH FCS field is removed\n    unsigned int rx_tc_crc_ver_dis  :1; //  0: TC CRC verification enabled, 1: disabled\n    unsigned int rx_tc_crc_size     :2; //  0: 0-bit, 1: 16-bit, 2: 32-bit\n    unsigned int rx_eth_fcs_result;     //  if the ETH FCS result matches this magic number, then the packet is valid packet\n    unsigned int rx_tc_crc_result;      //  if the TC CRC result matches this magic number, then the packet is valid packet\n    unsigned int rx_crc_cfg     :16;    //  TC CRC config, please check the description of SAR context data structure in the hardware spec\n    unsigned int res4           :16;\n    unsigned int rx_eth_fcs_init_value; //  ETH FCS initialization value\n    unsigned int rx_tc_crc_init_value;  //  TC CRC initialization value\n    unsigned int res_word1;\n    unsigned int rx_max_len_sel :1;     //  0: normal, the max length is given by MAX_LEN_NORMAL, 1: fragment, the max length is given by MAX_LEN_FRAG\n    unsigned int res5           :2;\n    unsigned int rx_edit_num2   :4;     //  number of bytes to be inserted/removed\n    unsigned int rx_edit_pos2   :7;     //  first byte position to be edited\n    unsigned int rx_edit_type2  :1;     //  0: remove, 1: insert\n    unsigned int rx_edit_en2    :1;     //  0: disable insertion or removal of data, 1: enable\n    unsigned int res6           :3;\n    unsigned int rx_edit_num1   :4;     //  number of bytes to be inserted/removed\n    unsigned int rx_edit_pos1   :7;     //  first byte position to be edited\n    unsigned int rx_edit_type1  :1;     //  0: remove, 1: insert\n    unsigned int rx_edit_en1    :1;     //  0: disable insertion or removal of data, 1: enable\n    unsigned int res_word2[2];\n    unsigned int rx_inserted_bytes_1l;\n    unsigned int rx_inserted_bytes_1h;\n    unsigned int rx_inserted_bytes_2l;\n    unsigned int rx_inserted_bytes_2h;\n    int rx_len_adj;                     //  the packet length adjustment, it is sign integer\n    unsigned int res_word3[16];\n  };\n\n  struct tx_bc_cfg {\n    unsigned int fill_wm        :16;    //  default 2\n    unsigned int uflw_wm        :16;    //  default 2\n    unsigned int res_word[31];\n  };\n\n  struct tx_gamma_itf_cfg {\n    unsigned int res_word1;\n    unsigned int res1           :8;\n    unsigned int tx_len_adj     :4;     //  4 * (not TX_ETH_FCS_GEN_DIS) + TX_TC_CRC_SIZE\n    unsigned int tx_crc_off_adj :4;     //  4 + TX_TC_CRC_SIZE\n    unsigned int tx_min_len     :8;     //  min length of packet, if length is less than this value, packet is padded\n    unsigned int res2           :3;\n    unsigned int tx_eth_fcs_gen_dis :1; //  0: ETH FCS generation enabled, 1: disabled\n    unsigned int res3           :2;\n    unsigned int tx_tc_crc_size :2;     //  0: 0-bit, 1: 16-bit, 2: 32-bit\n    unsigned int res4           :24;\n    unsigned int queue_mapping  :8;     //  TX queue attached to this Gamma interface\n    unsigned int res_word2;\n    unsigned int tx_crc_cfg     :16;    //  TC CRC config, please check the description of SAR context data structure in the hardware spec\n    unsigned int res5           :16;\n    unsigned int tx_eth_fcs_init_value; //  ETH FCS initialization value\n    unsigned int tx_tc_crc_init_value;  //  TC CRC initialization value\n    unsigned int res_word3[25];\n  };\n\n  struct wtx_qos_q_desc_cfg {\n    unsigned int threshold      :8;\n    unsigned int length         :8;\n    unsigned int addr           :16;\n    unsigned int rd_ptr         :16;\n    unsigned int wr_ptr         :16;\n  };\n\n  struct wtx_eg_q_shaping_cfg {\n    unsigned int t              :8;\n    unsigned int w              :24;\n    unsigned int s              :16;\n    unsigned int r              :16;\n    unsigned int res1           :8;\n    unsigned int d              :24;    //  ppe internal variable\n    unsigned int res2           :8;\n    unsigned int tick_cnt       :8;     //  ppe internal variable\n    unsigned int b              :16;    //  ppe internal variable\n  };\n\n  /* DMA descriptor */\n  struct rx_descriptor {\n    /*  0 - 3h  */\n    unsigned int own            :1;     //  0: Central DMA TX or MIPS, 1: PPE\n    unsigned int c              :1;     //  PPE tells current descriptor is complete\n    unsigned int sop            :1;\n    unsigned int eop            :1;\n    unsigned int res1           :3;\n    unsigned int byteoff        :2;\n    unsigned int res2           :7;\n    unsigned int datalen        :16;\n    /*  4 - 7h  */\n    unsigned int res3           :4;\n    unsigned int dataptr        :28;    //  byte address\n  };\n\n  struct tx_descriptor {\n    /*  0 - 3h  */\n    unsigned int own            :1;     //  CPU path - 0: MIPS, 1: PPE Dispatcher, Fastpath - 0: PPE Dispatcher, 1: Central DMA, QoS Queue - 0: PPE Dispatcher, 1: PPE DMA, SWAP Channel - 0: MIPS, 1: PPE Dispatcher\n    unsigned int c              :1;     //  MIPS or central DMA tells PPE the current descriptor is complete\n    unsigned int sop            :1;\n    unsigned int eop            :1;\n    unsigned int byteoff        :5;\n    unsigned int qid            :4;     //  TX Queue ID, bit 3 is reserved\n    unsigned int res1           :3;\n    unsigned int datalen        :16;\n    /*  4 - 7h  */\n    unsigned int small          :1;     //  0: standard size, 1: less than standard size\n    unsigned int res2           :3;\n    unsigned int dataptr        :28;    //  byte address\n  };\n\n#else /* defined(__BIG_ENDIAN) */\n  #error structures are defined in big endian\n#endif  /* defined(__BIG_ENDIAN) */\n\n\n\n#endif  //  IFXMIPS_PTM_FW_REGS_VDSL_H\n\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-ptm/src/ifxmips_ptm_fw_regs_vr9.h",
    "content": "/******************************************************************************\n**\n** FILE NAME    : ifxmips_ptm_fw_regs_vr9.h\n** PROJECT      : UEIP\n** MODULES      : PTM\n**\n** DATE         : 7 Jul 2009\n** AUTHOR       : Xu Liang\n** DESCRIPTION  : PTM driver header file (firmware register for VR9)\n** COPYRIGHT    :       Copyright (c) 2006\n**                      Infineon Technologies AG\n**                      Am Campeon 1-12, 85579 Neubiberg, Germany\n**\n**    This program is free software; you can redistribute it and/or modify\n**    it under the terms of the GNU General Public License as published by\n**    the Free Software Foundation; either version 2 of the License, or\n**    (at your option) any later version.\n**\n** HISTORY\n** $Date        $Author         $Comment\n** 07 JUL 2009  Xu Liang        Init Version\n*******************************************************************************/\n\n\n\n#ifndef IFXMIPS_PTM_FW_REGS_VR9_H\n#define IFXMIPS_PTM_FW_REGS_VR9_H\n\n\n\n/*\n *  Host-PPE Communication Data Address Mapping\n */\n#define FW_VER_ID_NEW                           ((volatile struct fw_ver_id_new *)          SB_BUFFER(0x2000))\n#define FW_VER_ID                               ((volatile struct fw_ver_id *)              SB_BUFFER(0x2001))\n#define CFG_STD_DATA_LEN                        ((volatile struct cfg_std_data_len *)       SB_BUFFER(0x2011))\n#define TX_QOS_CFG                              ((volatile struct tx_qos_cfg *)             SB_BUFFER(0x2012))\n#define EG_BWCTRL_CFG                           ((volatile struct eg_bwctrl_cfg *)          SB_BUFFER(0x2013))\n#define PSAVE_CFG                               ((volatile struct psave_cfg *)              SB_BUFFER(0x2014))\n#define GPIO_ADDR                               SB_BUFFER(0x2019)\n#define GPIO_MODE                               ((volatile struct gpio_mode *)              SB_BUFFER(0x201C))\n#define GPIO_WM_CFG                             ((volatile struct gpio_wm_cfg *)            SB_BUFFER(0x201D))\n#define TEST_MODE                               ((volatile struct test_mode *)              SB_BUFFER(0x201F))\n#define WTX_QOS_Q_DESC_CFG(i)                   ((volatile struct wtx_qos_q_desc_cfg *)     SB_BUFFER(0x2FF0 + (i) * 2))    /*  i < 8   */\n#define WTX_EG_Q_PORT_SHAPING_CFG(i)            ((volatile struct wtx_eg_q_shaping_cfg *)   SB_BUFFER(0x2680 + (i) * 4))    /*  i < 1   */\n#define WTX_EG_Q_SHAPING_CFG(i)                 ((volatile struct wtx_eg_q_shaping_cfg *)   SB_BUFFER(0x2684 + (i) * 4))    /*  i < 8   */\n#define TX_QUEUE_CFG(i)                         WTX_EG_Q_PORT_SHAPING_CFG(i)    //  i < 9\n#define RX_BC_CFG(i)                            ((volatile struct rx_bc_cfg *)              SB_BUFFER(0x3E80 + (i) * 0x20)) //  i < 2\n#define TX_BC_CFG(i)                            ((volatile struct tx_bc_cfg *)              SB_BUFFER(0x3EC0 + (i) * 0x20)) //  i < 2\n#define RX_GAMMA_ITF_CFG(i)                     ((volatile struct rx_gamma_itf_cfg *)       SB_BUFFER(0x3D80 + (i) * 0x20)) //  i < 4\n#define TX_GAMMA_ITF_CFG(i)                     ((volatile struct tx_gamma_itf_cfg *)       SB_BUFFER(0x3E00 + (i) * 0x20)) //  i < 4\n#define WAN_RX_MIB_TABLE(i)                     ((volatile struct wan_rx_mib_table *)       SB_BUFFER(0x5B00 + (i) * 8))    //  i < 4\n#define WAN_TX_MIB_TABLE(i)                     ((volatile struct wan_tx_mib_table *)       SB_BUFFER(0x5B20 + (i) * 8))    //  i < 8\n#define TX_CTRL_K_TABLE(i)                      SB_BUFFER(0x47F0 + (i)) //  i < 16\n//  following MIB for debugging purpose\n#define RECEIVE_NON_IDLE_CELL_CNT(i)            SB_BUFFER(5020 + (i))\n#define RECEIVE_IDLE_CELL_CNT(i)                SB_BUFFER(5022 + (i))\n#define TRANSMIT_CELL_CNT(i)                    SB_BUFFER(5024 + (i))\n#define FP_RECEIVE_PKT_CNT                      SB_BUFFER(5026)\n\n#define UTP_CFG                                 SB_BUFFER(0x2018)   //  bit 0~3 - 0x0F: in showtime, 0x00: not in showtime\n\n/*\n *  Descriptor Base Address\n */\n#define CPU_TO_WAN_TX_DESC_BASE                 ((volatile struct tx_descriptor *)SB_BUFFER(0x3D00))\n#define __ETH_WAN_TX_QUEUE_NUM                  g_wanqos_en\n#define __ETH_WAN_TX_QUEUE_LEN                  ((WAN_TX_DESC_NUM_TOTAL / __ETH_WAN_TX_QUEUE_NUM) < 256 ? (WAN_TX_DESC_NUM_TOTAL / __ETH_WAN_TX_QUEUE_NUM) : 255)\n#define __ETH_WAN_TX_DESC_BASE(i)               (0x5C00 + (i) * 2 * __ETH_WAN_TX_QUEUE_LEN)\n#define WAN_TX_DESC_BASE(i)                     ((volatile struct tx_descriptor *)SB_BUFFER(__ETH_WAN_TX_DESC_BASE(i))) //  i < __ETH_WAN_TX_QUEUE_NUM, __ETH_WAN_TX_QUEUE_LEN each queue\n#define WAN_SWAP_DESC_BASE                      ((volatile struct tx_descriptor *)SB_BUFFER(0x2E80))\n#define FASTPATH_TO_WAN_TX_DESC_BASE            ((volatile struct tx_descriptor *)SB_BUFFER(0x2580))\n#define DMA_RX_CH1_DESC_BASE                    FASTPATH_TO_WAN_TX_DESC_BASE\n#define WAN_RX_DESC_BASE                        ((volatile struct rx_descriptor *)SB_BUFFER(0x2600))\n#define DMA_TX_CH1_DESC_BASE                    WAN_RX_DESC_BASE\n\n/*\n *  Descriptor Number\n */\n#define CPU_TO_WAN_TX_DESC_NUM                  64\n#define WAN_TX_DESC_NUM                         __ETH_WAN_TX_QUEUE_LEN\n#define WAN_SWAP_DESC_NUM                       64\n#define WAN_TX_DESC_NUM_TOTAL                   512\n#define FASTPATH_TO_WAN_TX_DESC_NUM             64\n#define DMA_RX_CH1_DESC_NUM                     FASTPATH_TO_WAN_TX_DESC_NUM\n#define WAN_RX_DESC_NUM                         64\n#define DMA_TX_CH1_DESC_NUM                     WAN_RX_DESC_NUM\n\n\n\n#endif  //  IFXMIPS_PTM_FW_REGS_VR9_H\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-ptm/src/ifxmips_ptm_fw_vr9.h",
    "content": "#ifndef IFXMIPS_PTM_FW_VR9_H\n#define IFXMIPS_PTM_FW_VR9_H\n\n\n/******************************************************************************\n** FILE NAME    : ppa_datapath_fw_vr9_e1.h\n** PROJECT      : PPA\n** PLATFORM     : VR9\n** MODULES     \t: E1\n**\n** DATE         : 01/08/2014\n** AUTHOR       : Lantiq PPE FW Team\n** DESCRIPTION  : VR9 E1 PPE Firmware Binary\n** COPYRIGHT    : \t   Copyright (c) 2014\n**\t\t\t        Lantiq Deutschland GmbH\n**\n**    This program is free software; you can redistribute it and/or modify\n**    it under the terms of the GNU General Public License as published by\n**    the Free Software Foundation; either version 2 of the License, or\n**    (at your option) any later version.\n**\n** FW VERSION [31:0] : 0x73021000\n** FW FEATURE [31:0] : 0xB0000000\n** MERCURIAL TAG     : PTM_FW_PPA_2.16_Pre_Rel_04@default@ptm_fw\n**\n** HISTORY\n** $Date         $Author                   $Comment\n** 01/08/2014    Lantiq PPE FW Team        VR9 E1 PPE Firmware Binary\n*******************************************************************************/\n\nstatic unsigned int firmware_binary_code[] = {\n 0x80000980, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x8000ffe0, 0x00000000, 0x00000000, 0x00000000,\n 0x94000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n 0xc1c20002, 0xd9cc00f8, 0xc0006950, 0xcbc000f8, 0xc0004024, 0xc8c000f8, 0xc0006950, 0x5bfc0002,\n 0xa9446c0a, 0xcfc000f8, 0x00000000, 0xa4c26a1a, 0x00000000, 0x00000000, 0x80000790, 0x00000000,\n 0x94000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n 0x94000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n 0x94000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n 0x94000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n 0x94000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n 0x94000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n 0x94000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n 0x94000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n 0x94000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n 0x94000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n 0x94000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n 0x94000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n 0x94000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n 0x94000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n 0x94000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n 0xc0e1fffe, 0x58cdfffe, 0xc1e1fffa, 0x59ddfffe, 0x94000001, 0x00000000, 0x00000000, 0x00000000,\n 0xc0e1fffe, 0x58cdfffe, 0xc1e1fffa, 0x59ddfffe, 0x900009a1, 0x00000000, 0x00000000, 0x00000000,\n 0x90cc0941, 0x00000000, 0x00000000, 0x00000000, 0xc0004010, 0xd14000f8, 0xc000400c, 0xc8c000f8,\n 0xc1c1fffe, 0xd9d7e700, 0x45cce000, 0xc1c00002, 0xd9d40704, 0xc3e0e604, 0x5bfc2000, 0xc0004000,\n 0xcfc000f8, 0xc3e16000, 0x5bfc0000, 0xc0004002, 0xcfc000f8, 0xc0008fde, 0xc1c00000, 0xcdc000f8,\n 0xc0007e22, 0xc9c000f8, 0x00000000, 0x00000000, 0x5ddc0000, 0x84000022, 0xc0008fde, 0xc1c00002,\n 0xcdc000f8, 0xc3c00000, 0xc0004024, 0xcbc20078, 0x00000000, 0x00000000, 0xc1c00000, 0xd9c400f9,\n 0xdbc40078, 0xc1c00006, 0xd9c400f9, 0xc000403c, 0xcfc000f8, 0xc3c0fc10, 0xc0006952, 0xcfc000f8,\n 0xc3c00000, 0xc3400000, 0xc3000040, 0xc2c00080, 0x6ff8a000, 0x5bb87d00, 0x5838001c, 0xcf4000f8,\n 0x5838001e, 0xcec000f8, 0x58380020, 0xcf4000f8, 0x58380022, 0xcf0000f8, 0x5bfc0002, 0x5ebc0004,\n 0x8400ffa0, 0x00000000, 0xc1e1fffe, 0x59ddfffa, 0x141c0000, 0xc0004010, 0xd14000f8, 0xc000400c,\n 0xc8c000f8, 0xc1c1fffe, 0xd9d7e700, 0x45cce000, 0xc1c00002, 0xd9d40704, 0xc1c00000, 0xc000691c,\n 0xcdc000f8, 0xab64002a, 0xc3c00000, 0xab66001a, 0xc3c00002, 0x80001248, 0xc1c00002, 0xc000691c,\n 0xcdc000f8, 0x6ff8a000, 0x5bb87d00, 0x58380004, 0xcb4000f8, 0xc2800000, 0x58380000, 0xca820008,\n 0xc000e824, 0xc3000000, 0xcb3c0070, 0x6f5c8000, 0x41f4e000, 0x431d8000, 0x5b304000, 0xc000e828,\n 0xc1c00000, 0xc9fc0070, 0x00000000, 0xc0004000, 0x41f4e000, 0x401c0000, 0xcac000f8, 0x5de80004,\n 0x84000988, 0xa6c608f2, 0x00000000, 0x6fe42000, 0xc6e4a000, 0x6e60a000, 0x5a207b00, 0xc1800000,\n 0x58200000, 0xc9800000, 0xc2800000, 0xc6e80010, 0x5dd80000, 0x8400003a, 0x5de80008, 0xc6a82012,\n 0xc1c00004, 0x45e8e000, 0x88000030, 0x80000650, 0x5de80004, 0xc6a8010a, 0x5de80008, 0x84000630,\n 0x58380000, 0xc1c00002, 0xcdc00000, 0x58200000, 0xc1c00002, 0xcdc00000, 0x5de80002, 0xcdc00002,\n 0xc000ea14, 0xc1e20000, 0xcdfe3100, 0xc000fb60, 0xc1c00002, 0xcdfc0000, 0xc0006940, 0xc9c000f8,\n 0x403c0000, 0x00000000, 0x59dc0002, 0xcdc000f8, 0xc1c00004, 0x45e8e000, 0x880000fa, 0x58200020,\n 0xc9c000f8, 0xc0c00018, 0xc1000000, 0xa5c0002a, 0xc1400080, 0x5de80000, 0xc6ccf930, 0xc54c1932,\n 0x5de80000, 0xc1c0000a, 0xc5cc1230, 0xc5cc3202, 0x58200022, 0xc9c000f8, 0xc74c0b30, 0xc7cc0008,\n 0xc5cc0528, 0xc1800000, 0xc6982000, 0xc1c00000, 0xc69c0000, 0x71d8e000, 0xc5cc0400, 0x98406308,\n 0xc5d00000, 0x7d80e000, 0xc5d00100, 0x5dd80002, 0x84000480, 0xc1c00000, 0xc6ddc030, 0x59dc0006,\n 0xc5ec0e30, 0xc0c00018, 0xc1000004, 0x59dc0002, 0xc5cc1230, 0xc74c0b30, 0xc7cc0008, 0xc0000088,\n 0x441ce000, 0xc5cc1930, 0xa6cc03a8, 0x583cfac0, 0xc94000f8, 0xc1c80002, 0x70dc6000, 0xa55000c2,\n 0x58380024, 0xc94000f8, 0x00000000, 0x00000000, 0x59540002, 0x58380024, 0xcd4000f8, 0xc0c00010,\n 0x98406308, 0xc74c0b30, 0xc7cc0008, 0xc1000004, 0x58200000, 0xc1c00000, 0xcdc00000, 0x58380026,\n 0xc94000f8, 0x00000000, 0x00000000, 0x59540002, 0x58380026, 0xcd4000f8, 0x800002c0, 0xc1400000,\n 0xc6d5c030, 0x5d540002, 0x6d5c4010, 0x431c0000, 0xc88000f8, 0xc1c00000, 0xc55c0008, 0xc0000006,\n 0x441ce000, 0x6ddc6000, 0x689c4010, 0xc1c001fe, 0x749c4000, 0x59540002, 0xc1c000fe, 0x749c4000,\n 0x5c880020, 0xc48c1930, 0x5dc80002, 0x8800fee2, 0xc1c0007c, 0x45c8e000, 0x8800feca, 0x4148c000,\n 0x59980002, 0x5dd80088, 0x8800002a, 0x58200000, 0xc1c00000, 0xcdc00000, 0x800000c8, 0xc1400000,\n 0x6d9c4010, 0x431c0000, 0xc94000f8, 0xc1c00000, 0xc59c0008, 0xc0000006, 0x441ce000, 0x6ddc6000,\n 0x695ca010, 0xc1c001fe, 0x755ca000, 0x00000000, 0x00000000, 0x5dd40000, 0x84000018, 0x59980002,\n 0x8000ff48, 0x59980002, 0xc0800002, 0x5dd400a0, 0xc4902100, 0xc4ac2602, 0x4588c002, 0xdbc800f9,\n 0xda4800f8, 0xda1000f9, 0x90405849, 0x58200020, 0xc9c000f8, 0x58200022, 0xc94000f8, 0x5ddc0002,\n 0xc1c00000, 0xc5cc1932, 0xc6ddc030, 0x59dc0002, 0x98406308, 0xc5cc1230, 0xc54c0528, 0xc4d08000,\n 0xa5020072, 0xc1c00002, 0xc5d00100, 0xc5ac0e30, 0xa6ccfd9a, 0xc1c00000, 0xc5cc0400, 0xc1c00086,\n 0x45d8e000, 0xc5cc1930, 0x8000ff28, 0x00000000, 0x00000000, 0x00000000, 0x80000070, 0xdbc800f9,\n 0xda4800f8, 0xda1000f9, 0x90405849, 0x58200022, 0xc98000f8, 0x58200020, 0xc9c000f8, 0x00000000,\n 0x98406308, 0x5ddc0002, 0xc58c0528, 0xc5cc1932, 0x80000210, 0xc1400000, 0xc000403e, 0xc9400000,\n 0xc1800000, 0x58200000, 0xc9800000, 0x5dd40002, 0x84000020, 0x5dd80002, 0x84000010, 0x80000120,\n 0x5de80006, 0x84000088, 0x58380000, 0xc1c00002, 0xcdc00000, 0xc000ea14, 0xc1e20000, 0xcdfe3100,\n 0xc000fb60, 0xc1c20002, 0xcdfc2100, 0xc0006944, 0xc9c000f8, 0x403c0000, 0x00000000, 0x59dc0002,\n 0xcdc000f8, 0x80000100, 0x5de8000a, 0x84000080, 0x58380000, 0xc1c00000, 0xcdc00000, 0xc000ea14,\n 0xc1c00000, 0xdd5c5100, 0x7dc0e000, 0xcdfe3100, 0xc000fb60, 0xc1c20002, 0xcdfc2100, 0xc000facc,\n 0xc1c00002, 0xcdfc0000, 0x80000078, 0xa6ca0040, 0xc000facc, 0xc1ca0002, 0xcdfca500, 0xc000fb64,\n 0xc1c60002, 0xcdfc6300, 0x80000038, 0xc000facc, 0xc1c80002, 0xcdfc8400, 0xc000fb64, 0xc1c40002,\n 0xcdfc4200, 0xc0c00010, 0x98406308, 0xc7cc0008, 0xc74c0b30, 0xc1000004, 0x80000818, 0xc1c00002,\n 0x58380008, 0xcdc000f8, 0x58380000, 0xc1e00006, 0xcdc21008, 0xc000facc, 0xc1c80002, 0xcdfc8400,\n 0xc000fb64, 0xc1c40002, 0xcdfc4200, 0xc0c00010, 0x98406308, 0xc7cc0008, 0xc74c0b30, 0xc1000004,\n 0x80000788, 0x5de80006, 0x84000180, 0xa6c60032, 0x00000000, 0x58380000, 0xc1e00004, 0xcdc21008,\n 0x8000f658, 0x58380008, 0xca8000f8, 0xc2400000, 0x58380002, 0xca420078, 0x00000000, 0x5aa80002,\n 0x58380008, 0xce8000f8, 0x46a4e000, 0x8800009a, 0x58380000, 0xc1e00002, 0xcdc21008, 0x58380000,\n 0xc1c00000, 0xcdc00000, 0xc000facc, 0xc1c20002, 0xcdfc2100, 0xc1e1e1a2, 0xc000ea1c, 0xcdfc00f8,\n 0xc000ea14, 0xc1c00000, 0xdd5c5100, 0x7dc0e000, 0xcdfe3100, 0x80000038, 0xc000facc, 0xc1c80002,\n 0xcdfc8400, 0xc000fb64, 0xc1c40002, 0xcdfc4200, 0xc0c00010, 0x98406308, 0xc7cc0008, 0xc74c0b30,\n 0xc1000004, 0x80000600, 0x5de80002, 0x84000150, 0xa6c6004a, 0x00000000, 0x58380000, 0xc1e00004,\n 0xcdc21008, 0xc1f8001e, 0xc000ea1c, 0xcdfc00f8, 0x8000f4b8, 0x58380008, 0xca8000f8, 0xc2400000,\n 0x58380002, 0xca400078, 0xc000facc, 0xc1c20002, 0xcdfc2100, 0x5aa80002, 0x58380008, 0xce8000f8,\n 0x46a4e000, 0x88000072, 0x58380000, 0xc1e00000, 0xcdc21008, 0xc1c00000, 0x58380006, 0xcdc000f8,\n 0xc000e82c, 0xc1c00000, 0xcdfdce00, 0xc000e820, 0xc1c00000, 0xcdfc0000, 0x80000300, 0xc0c00010,\n 0x98406308, 0xc7cc0008, 0xc74c0b30, 0xc1000004, 0x800004a8, 0x5838001c, 0xca8000f8, 0x5838001e,\n 0xca4000f8, 0x5aa80002, 0x5838001c, 0xce8000f8, 0x4668e000, 0x88000098, 0x58380022, 0xca4000f8,\n 0x58380020, 0xca0000f8, 0xc000e82c, 0xc1c00000, 0xcdfdce00, 0xc000e810, 0xce7c0030, 0xc2800000,\n 0x5838001c, 0xce8000f8, 0x5a200002, 0x58380020, 0xce0000f8, 0xc000e82c, 0xc1dc0002, 0xcdfdce00,\n 0x58380006, 0xc8c000f8, 0x5830001c, 0xca8000f9, 0xca4000f9, 0xc2000000, 0xca000001, 0x5dcc0006,\n 0x88000028, 0x58cc0002, 0x58380006, 0xccc000f8, 0x80000250, 0x5838000a, 0xc8c000f9, 0xc90000f9,\n 0xc1400000, 0xc9400001, 0x74e86000, 0x75248000, 0x7560a000, 0x58380010, 0xca8000f9, 0xca4000f9,\n 0xc2000000, 0xca000001, 0x984064d8, 0x74e86000, 0x75248000, 0x7560a000, 0x5dc800a0, 0x840001ba,\n 0x58380016, 0xca8000f9, 0xca4000f9, 0xc2000000, 0xca000001, 0x984064d8, 0x74e86000, 0x75248000,\n 0x7560a000, 0x5dc800a0, 0x84000162, 0x58380000, 0xc1e00004, 0xcdc21008, 0x5838001c, 0xc1c00000,\n 0xcdc000f8, 0xc000e82c, 0xc1c00000, 0xcdfdce00, 0xc1f8001e, 0xc000ea1c, 0xcdfc00f8, 0xc000e820,\n 0xc1c00002, 0xcdfc0000, 0xc1c00082, 0x45c8e000, 0xc000e810, 0xcdfc0030, 0xc2400000, 0xc000e82c,\n 0xca7c0038, 0xc000e83c, 0xc2800000, 0xcabc0038, 0xc0c00010, 0x98406308, 0xc7cc0008, 0xc74c0b30,\n 0xc1000004, 0x5b740002, 0x4674e000, 0xc1c00000, 0xc5f400fe, 0x5ea80002, 0x8400ffb0, 0xc000e83c,\n 0xc1c00000, 0xcdfc0038, 0xc000e82c, 0xc1dc0002, 0xcdfdce00, 0x80000178, 0x58380010, 0xca8000f9,\n 0xca4000f9, 0xc2000000, 0xca000001, 0x58380016, 0xce8000f9, 0xce4000f9, 0xce000001, 0x5838000a,\n 0xca8000f9, 0xca4000f9, 0xc2000000, 0xca000001, 0x58380010, 0xce8000f9, 0xce4000f9, 0xce000001,\n 0x5830001c, 0xca8000f9, 0xca4000f9, 0xc2000000, 0xca000001, 0x5838000a, 0xce8000f9, 0xce4000f9,\n 0xce000001, 0xc000facc, 0xc1c20002, 0xcdfc2100, 0xc0c00010, 0x98406308, 0xc7cc0008, 0xc74c0b30,\n 0xc1000004, 0xc000e83c, 0xc1d00002, 0xcdfd0800, 0xc0c00000, 0xc000e82c, 0xc8fc0038, 0x5b740002,\n 0x00000000, 0x44f4e000, 0xc1c00000, 0xc5f400fe, 0x58380004, 0xcf4000f8, 0x984065b0, 0x00000000,\n 0x00000000, 0x00000000, 0xc000400c, 0xcbc000f8, 0xc000400e, 0xcb8000f8, 0xc0007d00, 0xcac000f8,\n 0x73f8e000, 0x8400034a, 0x58000040, 0xca8000f8, 0xc0006960, 0x4b000058, 0xc1e00002, 0x7dc0e000,\n 0x76dd6000, 0x769d4000, 0xc2620002, 0x5a640002, 0xc3400000, 0xc2000006, 0x46e4e000, 0xc634000a,\n 0x46a4e000, 0xc634020a, 0xc000fb80, 0xcac000f8, 0xc000fba0, 0xca8000f8, 0xc2400000, 0xc2000000,\n 0xc6e40000, 0xc6e40100, 0xc6a40200, 0xc6a40300, 0xc6e02000, 0xc6e02100, 0xc6a02200, 0xc6a02300,\n 0x7765a000, 0x7761a000, 0xc6740818, 0x7b716000, 0x84000232, 0xc0006960, 0xcf4000f8, 0xc0800000,\n 0xc1c1fffe, 0x45fce000, 0x88000022, 0xa9420018, 0x00000000, 0xc0800008, 0x58fc0008, 0x59380008,\n 0xc1c1fffe, 0x45fce000, 0x88000018, 0x58fc0020, 0x59380020, 0x776d4000, 0x840000ca, 0x6e950010,\n 0x5dd40000, 0x84000052, 0xc000f41a, 0xcfc000f8, 0xc1c00000, 0xc7dc4050, 0x581cc000, 0x5dfdfffe,\n 0xc7c000fe, 0x6948a000, 0xcd4000f8, 0xc1c001fe, 0x769d4000, 0x84000052, 0xc000f41a, 0xccc000f8,\n 0xc1c00000, 0xc4dc4050, 0x581cc000, 0x5dcdfffe, 0xc4c000fe, 0x6a894000, 0xce8000f8, 0x7f41a000,\n 0x776d2000, 0x840000ca, 0x6e550010, 0x5dd40000, 0x84000052, 0xc000f41a, 0xcf8000f8, 0xc1c00000,\n 0xc79c4050, 0x581cc000, 0x5df9fffe, 0xc78000fe, 0x6948a000, 0xcd4000f8, 0xc1c001fe, 0x765d2000,\n 0x84000052, 0xc000f41a, 0xcd0000f8, 0xc1c00000, 0xc51c4050, 0x581cc000, 0x5dd1fffe, 0xc50000fe,\n 0x6a492000, 0xce4000f8, 0xa9440180, 0xc000a340, 0xcbc000f8, 0xa9420168, 0xc000a34a, 0xcb8000f8,\n 0xc000f414, 0xcb4000f8, 0x5dfc0002, 0x84000048, 0xc000a346, 0x984063f0, 0xc8c000f9, 0xc90000f8,\n 0xc3c00004, 0xc000a340, 0xcfc000f8, 0x80000058, 0x5dfc0004, 0x84000048, 0xc1c40002, 0x75f4e000,\n 0x84000032, 0xc000f414, 0xcdc000f8, 0xc3c00006, 0xc000a340, 0xcfc000f8, 0x5df80002, 0x84000048,\n 0xc000a350, 0x98406308, 0xc8c000f9, 0xc90000f8, 0xc3800004, 0xc000a34a, 0xcf8000f8, 0x80000058,\n 0x5df80004, 0x84000048, 0xc1c20002, 0x75f4e000, 0x84000032, 0xc000f414, 0xcdc000f8, 0xc3800006,\n 0xc000a34a, 0xcf8000f8, 0xa9440ca2, 0xc0008fde, 0xc9c000f8, 0x00000000, 0xc0007e3e, 0xcdc000f8,\n 0xc0006914, 0xcbc000f8, 0xc2800000, 0xc2400000, 0x5bfc4b00, 0xc7c000f8, 0xcb0000f8, 0x58000002,\n 0xcac000f8, 0xc0004026, 0xca800078, 0xc0004026, 0xca420078, 0xc3400000, 0xc7366018, 0xa73e01da,\n 0x00000000, 0x00000000, 0xc0007e20, 0xc9c000f8, 0x00000000, 0x00000000, 0xa5c20040, 0x00000000,\n 0x00000000, 0x00000000, 0x984027d8, 0x5c3c4b00, 0x6c002010, 0x5800a100, 0xc777e300, 0xc000694c,\n 0xc9c000f8, 0x00000000, 0x00000000, 0x59dc0002, 0xcdc000f8, 0x6f5c6000, 0x58dcb640, 0x580c0000,\n 0xc90000f8, 0x580c0002, 0xc94000f8, 0x59100002, 0x580c0000, 0xcd0000f8, 0xc1c00000, 0xc71c0078,\n 0x415ca000, 0x580c0002, 0xcd4000f8, 0x98402828, 0x5834fc10, 0xc8c000f8, 0xc1000000, 0x5dc80000,\n 0x84000070, 0x6f402000, 0x58005fe0, 0xc3800000, 0x58000000, 0xcb800078, 0xc1c00000, 0x58000002,\n 0xc9c00078, 0x98402b10, 0x00000000, 0x439dc000, 0x00000000, 0x80000028, 0x984028b8, 0xc48c00f8,\n 0x00000000, 0x00000000, 0xc0006916, 0xcbc000f8, 0xc3400000, 0x00000000, 0x5bfc7a00, 0xc7c000f8,\n 0xcb0000f8, 0x58000002, 0xcac000f8, 0xc7366018, 0xa73e0998, 0x00000000, 0xc777e300, 0xc000694e,\n 0xc9c000f8, 0x00000000, 0x00000000, 0x59dc0002, 0xcdc000f8, 0x6f5c6000, 0x58dcb640, 0x580c0000,\n 0xc90000f8, 0x580c0002, 0xc94000f8, 0x59100002, 0x580c0000, 0xcd0000f8, 0xc1c00000, 0xc71c0078,\n 0x415ca000, 0x580c0002, 0xcd4000f8, 0x98402828, 0x5834fc10, 0xc8c000f8, 0xc1000000, 0x5dc80000,\n 0x84000070, 0x6f402000, 0x58005fe0, 0xc3800000, 0x58000000, 0xcb800078, 0xc1c00000, 0x58000002,\n 0xc9c00078, 0x98402e38, 0x00000000, 0x439dc000, 0x00000000, 0x80000850, 0x984029f8, 0xc48c00f8,\n 0x00000000, 0x00000000, 0x80000828, 0xc8c000f8, 0x00000000, 0x00000000, 0xa4feffe8, 0xc1c00000,\n 0xcdc000f8, 0x9c400000, 0xc3400000, 0xc1d00002, 0xc4f40018, 0xc7100078, 0xc0800000, 0x6f402000,\n 0x58005fe0, 0xc1400000, 0x58000000, 0xc9420038, 0x4690e000, 0x88000030, 0x454ca000, 0x9c400000,\n 0x4564e000, 0xc1c00004, 0xc5c800fe, 0x9c400000, 0x454ce000, 0xc1c00002, 0xc5c800fe, 0xc0006914,\n 0xc90000f8, 0xc1400000, 0xc0004022, 0xc9400078, 0x583c0000, 0xc1fc0000, 0xcdc3de00, 0x583c0000,\n 0xcd400078, 0x583c0000, 0xc1fe0002, 0xcdc3ff00, 0x59100004, 0xc1c00100, 0x45d0e000, 0xc1c00000,\n 0xc5d000fe, 0xc0006914, 0xcd0000f8, 0x6f546000, 0x5954b640, 0x5dcc0002, 0x84000038, 0x5814000c,\n 0xc9c000f8, 0x00000000, 0x00000000, 0x59dc0002, 0xcdc000f8, 0xc1c00002, 0xc000691c, 0xcdc000f8,\n 0x5814000e, 0xc9c000f8, 0x00000000, 0x9c400000, 0x59dc0002, 0xcdc000f8, 0x00000000, 0xc0006916,\n 0xc90000f8, 0x583c0000, 0xc1fc0000, 0xcdc3de00, 0x583c0000, 0xc1fe0000, 0xcdc3ff00, 0x59100004,\n 0xc1c00100, 0x45d0e000, 0xc1c00000, 0xc5d000fe, 0xc0006916, 0xcd0000f8, 0x6f546000, 0x5954b640,\n 0x5dcc0002, 0x84000038, 0x58140008, 0xc9c000f8, 0x00000000, 0x00000000, 0x59dc0002, 0xcdc000f8,\n 0xc1c00002, 0xc000691c, 0xcdc000f8, 0x5814000a, 0xc9c000f8, 0x00000000, 0x9c400000, 0x59dc0002,\n 0xcdc000f8, 0x00000000, 0xc78000f8, 0xc8c000f8, 0x58000002, 0xc90000f8, 0xa4e00178, 0xc0006918,\n 0xca0000f8, 0x00000000, 0x00000000, 0x5a205d00, 0xc60000f8, 0xc94000f8, 0x58000002, 0xc98000f8,\n 0xa57e006a, 0xc1c00000, 0xc0c00004, 0xc71c0078, 0xc46000f8, 0x984028b8, 0x45e8e000, 0xc1c00002,\n 0xc5cc00fe, 0x9e000000, 0xc1e00002, 0xc000e408, 0xcdc21000, 0xc55c00f8, 0xc4d400f8, 0xc5cc00f8,\n 0xc59c00f8, 0xc51800f8, 0xc5d000f8, 0xc1c00000, 0xc5d41f00, 0xc5cff000, 0x58200002, 0xcd8000f8,\n 0x5c000002, 0xcd4000f8, 0x5e205d00, 0x5a200004, 0xc1c00080, 0x45e0e000, 0xc1c00000, 0xc5e000fe,\n 0xc0006918, 0xce0000f8, 0xc1e00002, 0xc000e408, 0xcdc21000, 0xc6dc00f8, 0xc52c00f8, 0xc5d000f8,\n 0xc71c00f8, 0xc4f000f8, 0xc5cc00f8, 0xc0004022, 0xcb000078, 0xc1c00002, 0xc5cc1f00, 0xc5f01f00,\n 0xc5f3fe00, 0x58380002, 0xcd0000f8, 0x5c000002, 0xccc000f8, 0x6f402000, 0x58005fe0, 0xc1c00000,\n 0xc9c20138, 0xc2000000, 0x58000002, 0xca000078, 0x00000000, 0x00000000, 0x5a200004, 0x45e0e000,\n 0xc1c00000, 0xc5e000fe, 0xce000078, 0x5e3c4b00, 0x5a200004, 0xc1c00100, 0x45e0e000, 0xc1c00000,\n 0xc5e000fe, 0xc0006914, 0xce0000f8, 0xc1c00002, 0x69f4e000, 0xc5dc0838, 0xd9f000f8, 0x583c0002,\n 0xcec000f8, 0x5c000002, 0xcf0000f8, 0x9c400000, 0xc1c00002, 0xc000691c, 0xcdc000f8, 0x58380002,\n 0xc90000f8, 0x5c000002, 0xc8c000f8, 0xc6dc00f8, 0xc52c00f8, 0xc5d000f8, 0xc71c00f8, 0xc4f000f8,\n 0xc5cc00f8, 0xc1c00002, 0xc5cc1f00, 0xc1c00000, 0xc5f01f00, 0xc5f3fe00, 0x58380002, 0xcd0000f8,\n 0x5c000002, 0xccc000f8, 0x6f402000, 0x58005fe0, 0xc1c00000, 0xc9c20138, 0xc2000000, 0x58000002,\n 0xca000078, 0x00000000, 0x00000000, 0x5a200004, 0x45e0e000, 0xc1c00000, 0xc5e000fe, 0xce000078,\n 0x5e3c7a00, 0x5a200004, 0xc1c00100, 0x45e0e000, 0xc1c00000, 0xc5e000fe, 0xc0006916, 0xce0000f8,\n 0xc1c00002, 0x69f4e000, 0xc5dc0838, 0xd9f000f8, 0x583c0002, 0xcec000f8, 0x5c000002, 0xcf0000f8,\n 0xc1e20002, 0xc000e408, 0xcdc23100, 0x9c400000, 0xc1c00002, 0xc000691c, 0xcdc000f8, 0xc0007e3e,\n 0xc9c000f8, 0x00000000, 0x00000000, 0x5ddc0002, 0xcdc000f8, 0x8800f398, 0xc0004010, 0xc9c000f8,\n 0xc0007e24, 0xc8c000f8, 0xa5c200e2, 0x00000000, 0xc0007e22, 0xc9c000f8, 0x00000000, 0x00000000,\n 0x5ddc0000, 0x840000aa, 0xc000f41a, 0xcdc000f8, 0x580ca100, 0xc90000f8, 0x580cc100, 0x00000000,\n 0xa53e0070, 0x00000000, 0xcd0000f8, 0xc1c00000, 0x580ca100, 0xcdc000f8, 0x58cc0002, 0xc1c00080,\n 0x45cce000, 0xc1c00000, 0xc5cc00fe, 0xc0007e24, 0xccc000f8, 0x8000ff78, 0xc3c00000, 0x6ff8a000,\n 0x5bb87d80, 0xc1c00002, 0xc000691c, 0xcdc000f8, 0x583cfb50, 0xc2800000, 0xca80c030, 0xc2400000,\n 0x58380000, 0xca400078, 0x58380006, 0xca0000f8, 0x583cea28, 0xc9c000f8, 0xc0c00000, 0x00000000,\n 0xc5cc0038, 0x420c8000, 0x4268a000, 0x4514e000, 0x8800012a, 0x58380004, 0xca4000f8, 0x5de00080,\n 0x8800007a, 0xc000ea28, 0xc1d2007e, 0xcdfd2928, 0xc000ea28, 0xc1d00002, 0xcdfd0800, 0x5de0007e,\n 0xc000ea28, 0x6ddd2000, 0xcdfd2928, 0xc000ea28, 0xc1d00002, 0xcdfd0800, 0x80000038, 0xc000ea28,\n 0x6e1d2000, 0xcdfd2928, 0xc000ea28, 0xc1d00002, 0xcdfd0800, 0x583c6948, 0xc9c000f8, 0x00000000,\n 0x00000000, 0x41e0e000, 0xcdc000f8, 0x46612000, 0x58380004, 0xce4000f8, 0x58380006, 0xc1c00000,\n 0xcdc000f8, 0x58380004, 0xca4000f8, 0x583cea28, 0xc9c000f8, 0xc0c00000, 0x00000000, 0xc5cc0038,\n 0xc1400000, 0x58380000, 0xc9420078, 0x424d0000, 0x00000000, 0x42948000, 0x4520e000, 0x880020ba,\n 0xc000fa40, 0xc9bc00f8, 0x6ff42000, 0xc3000000, 0xc5b4e000, 0xc2c07c00, 0x6f5ca000, 0x42dd6000,\n 0x582c0022, 0xc98000f8, 0x00000000, 0x00000000, 0x5dd80000, 0x840003d2, 0x582c0026, 0xca8000f8,\n 0x5838000a, 0xc98000f8, 0xc000ea10, 0xc2400000, 0xca7c0070, 0x6d9c8000, 0x41d8e000, 0x425d2000,\n 0x5a644000, 0x582c0032, 0xc9c000f8, 0x582c002e, 0xc98000f8, 0x582c0030, 0xc94000f8, 0x00000000,\n 0x41d8e000, 0x41d4e000, 0xd9f800f8, 0x5ddc0080, 0x880000a2, 0x00000000, 0xa7400018, 0xc180001e,\n 0xc180015e, 0xc1400000, 0x6d5c4010, 0x425c0000, 0xc1c00006, 0x755c8000, 0x5dd00000, 0xcd80183a,\n 0x5dd00002, 0xcd80103a, 0x5dd00004, 0xcd80083a, 0x5dd00006, 0xcd80003a, 0x5b300008, 0x80000278,\n 0x58240002, 0xc1800000, 0xcd8000f9, 0xcd8000f9, 0xcd8000f9, 0xcd8000f9, 0xcd8000f9, 0xcd8000f9,\n 0xcd8000f9, 0xcd8000f9, 0xcd8000f9, 0xcd8000f9, 0xcd8000f9, 0xcd8000f9, 0xcd8000f9, 0xcd8000f9,\n 0xcd8000f9, 0xcd8000f9, 0xa7400018, 0xc18001e0, 0xc18001ea, 0xc1400000, 0x6d5c4010, 0x425c0000,\n 0xc90000f8, 0xc1c00000, 0xc55c0308, 0x691c8008, 0xc5901838, 0x691c8018, 0xcd0000f8, 0x6d5c4010,\n 0x425c0000, 0xc1c00006, 0x755c8000, 0x5dd00000, 0xcd80183a, 0x5dd00002, 0xcd80103a, 0x5dd00004,\n 0xcd80083a, 0x5dd00006, 0xcd80003a, 0x5b300008, 0xdf9400f8, 0xc1008fe0, 0x6d5c4010, 0x411c0000,\n 0xc98000f8, 0xc1c00000, 0xc55c0308, 0x699cc000, 0x6d9b0010, 0x6f1c4010, 0x425c0000, 0xc94000f8,\n 0xc1c00000, 0xc71c0308, 0x695ca008, 0xc5941838, 0x695ca018, 0xcd4000f8, 0x6f1c4010, 0x425c0000,\n 0xc1c00006, 0x771ca000, 0x5dd40000, 0xcd80183a, 0x5dd40002, 0xcd80103a, 0x5dd40004, 0xcd80083a,\n 0x5dd40006, 0xcd80003a, 0x5b300002, 0x582c0022, 0xc1c00000, 0xcdc000f8, 0x80001610, 0x00000000,\n 0xa9440328, 0xc000e444, 0xc90000f8, 0xc0006956, 0xc8c000f8, 0xc000e442, 0xcd0000f8, 0x70d06000,\n 0xc0006956, 0xccc000f8, 0xc1c00002, 0x69f4e000, 0xc0006960, 0xc88000f8, 0x74dc6000, 0x84001b0a,\n 0x749c4000, 0x80000008, 0xc000401a, 0xc9c000f8, 0x00000000, 0xc000f41a, 0xcdc000f8, 0xc0c00000,\n 0xc0004054, 0xc8c00078, 0xc0006958, 0xc93400f8, 0x6f5ca000, 0x40dc6000, 0x40d06000, 0xc4c000f8,\n 0xc94000f8, 0x00000000, 0x00000000, 0xa57e01a0, 0xc0004054, 0xc9820078, 0x6d1c2010, 0x59100004,\n 0x419cc000, 0x6f5c8000, 0x419cc000, 0xc1c00040, 0x45d0e000, 0xc1c00000, 0xc5d000fe, 0xc0006958,\n 0xcd3400f8, 0x5dc80000, 0x8400016a, 0x580c0002, 0xc90000f8, 0x582c0032, 0xc1c00000, 0xcdc000f8,\n 0x582c002a, 0xccc000f8, 0x582c0034, 0xcd4000f8, 0x582c0036, 0xcd0000f8, 0xa9460042, 0xc58000f8,\n 0xc90000f8, 0x582c0032, 0xc1c00004, 0xcdc000f8, 0x582c0038, 0xcd0000f8, 0xc1c00000, 0xc55e6018,\n 0x582c002c, 0xcdc000f8, 0x582c003a, 0xc8c000f8, 0x582c003c, 0xc9c000f8, 0xc1800000, 0xc5580078,\n 0x58cc0002, 0x41d8e000, 0x582c003a, 0xccc000f8, 0x582c003c, 0xcdc000f8, 0x80000070, 0xc0006956,\n 0xc8c000f8, 0xc1c00002, 0x69f4e000, 0x7dc0e000, 0x74dc6000, 0xccc000f8, 0x80001890, 0xc4c000f8,\n 0xc1c00000, 0xc5d41f00, 0xcd4000f8, 0x80001868, 0x80000b48, 0xdb8800f9, 0xdb4800f8, 0xdb1000f9,\n 0xc2400000, 0xdf240038, 0xc0004024, 0xcb8000f8, 0xdcb400f8, 0x6f404000, 0x58004d48, 0x58000006,\n 0xcb000078, 0xc3400000, 0xc7b50038, 0xc2800000, 0xc7a88018, 0xc000fa40, 0xc8fc00f8, 0xc2800000,\n 0x582c0004, 0xca800038, 0xa4ce0042, 0x58ec0040, 0xc1c00000, 0x580c0004, 0xc9c00038, 0x00000000,\n 0x00000000, 0x729d4000, 0x7e412000, 0x76692000, 0xc0400000, 0xc7840008, 0xc000a0ae, 0x5de40000,\n 0x84000060, 0xc0c00000, 0xc8c000f8, 0x5dc40000, 0xdcb800fb, 0xdcb400fa, 0xdd3000fb, 0x8400170a,\n 0x80000360, 0xc0c00000, 0xccc000f8, 0x80000348, 0xc1c00002, 0xc000691c, 0xcdc000f8, 0xc0c00002,\n 0xccc000f8, 0xc65000f8, 0x61010028, 0x5dc40000, 0x84000018, 0x62410008, 0x800005a0, 0xc0007e26,\n 0xc94000f8, 0xc0400000, 0x00000000, 0x6140c028, 0x00000000, 0x00000000, 0x8400009a, 0xcd4000f8,\n 0x6d804000, 0x5800b7c0, 0x58000000, 0x484000b8, 0x00000000, 0x00000000, 0x58000004, 0xcc4000b8,\n 0x5dc40000, 0x8400ff70, 0xc0007e28, 0xc84000f8, 0xc1c00002, 0x69d8e000, 0x705c2000, 0xcc4000f8,\n 0x8000ff38, 0xc2000000, 0xc0c00000, 0x580c7e2a, 0xc90000f8, 0x00000000, 0x00000000, 0xc50400f8,\n 0x75248000, 0x61010028, 0x58205fb0, 0xc9c000f8, 0x00000000, 0xc1800000, 0x581c0006, 0xc9800078,\n 0xa7820108, 0xc0800000, 0xc1c00000, 0x6e1c2000, 0x59dc5fe0, 0x581c0002, 0xc8820078, 0x581c0000,\n 0xc9c00078, 0x00000000, 0x00000000, 0x409ce000, 0xc0800000, 0x581c0000, 0xc8800078, 0x00000000,\n 0x00000000, 0x40b44000, 0x4588e000, 0x88000070, 0xc0007e3c, 0xc9c000f8, 0x00000000, 0x00000000,\n 0xa5c00028, 0x00000000, 0x7c40e000, 0x765d2000, 0x80000068, 0xc1c00002, 0x69e0e000, 0x7dc0e000,\n 0x765d2000, 0xc0007e3c, 0xc9c000f8, 0x61010028, 0x8400002a, 0x00000000, 0xa5c0fed2, 0x00000000,\n 0x8000fe90, 0x58cc0002, 0x5dcc0012, 0x8800fe42, 0x5de40000, 0xdcb800fb, 0xdcb400fa, 0xdd3000fb,\n 0x840013c2, 0x80000018, 0x5dcc0000, 0x8400018a, 0xa7800180, 0xc2000000, 0xc0400000, 0x58047e2a,\n 0xc88000f8, 0xc0007e28, 0xc9c000f8, 0x00000000, 0x00000000, 0x74a44000, 0x75c8e000, 0x45c8e000,\n 0x84000108, 0x74a84000, 0x60810028, 0x840000f2, 0x6e0c4000, 0x58ccb7c0, 0xc1000000, 0x580c0004,\n 0xc90000b8, 0xc1800000, 0x580c0000, 0xc98000b8, 0x7d00a000, 0xc1f00002, 0x5ddc0002, 0x755ca000,\n 0x59540002, 0xc1ee0002, 0x75d0e000, 0xc5d400fa, 0x45948000, 0x580c0004, 0xcd0000b8, 0x5dd00000,\n 0x8400ff52, 0xc0007e28, 0xc90000f8, 0xc1c00002, 0x69e0e000, 0x7dc0e000, 0x751c8000, 0xcd0000f8,\n 0x8000ff10, 0x58440002, 0x5dc40012, 0x8800fea2, 0x5de40000, 0xdcb800fb, 0xdcb400fa, 0xdd3000fb,\n 0x84001202, 0x62410008, 0xa7800100, 0x00000000, 0xa7820068, 0x00000000, 0xa7860058, 0xc0004022,\n 0xc0c00000, 0xc8c00078, 0x00000000, 0x00000000, 0x470ce000, 0xdcb800fd, 0xdcb400fc, 0xdd3000fd,\n 0x88001182, 0xc0c00000, 0xc65000f8, 0x6100a028, 0x6d584000, 0x5998b7c0, 0xc0400000, 0x58180004,\n 0xc84000b8, 0x00000000, 0x00000000, 0xa46e002a, 0x44c4e000, 0x88000018, 0xc56000f8, 0xc44c00f8,\n 0x6100a028, 0xa54aff98, 0x6e184000, 0x5998b7c0, 0xc0400000, 0xc0800000, 0x6e1c2000, 0x59dc5fe0,\n 0x581c0002, 0xc8420078, 0x581c0000, 0xc8800078, 0x58205fb0, 0xc9c000f8, 0x00000000, 0xc1400000,\n 0x581c0006, 0xc9400078, 0x40484000, 0xc0c00000, 0x58080000, 0xc8c00078, 0x00000000, 0xa78200c0,\n 0x40f42000, 0x4704e000, 0xdcb800fd, 0xdcb400fc, 0xdd3000fd, 0x8800101a, 0x5dd5fffe, 0x84000042,\n 0x4544a000, 0x58205fb0, 0xc9c000f8, 0x00000000, 0x00000000, 0x581c0006, 0xcd400078, 0x5df1fffe,\n 0x8400003a, 0x47058000, 0xdcb400f8, 0x6f404000, 0x58004d48, 0x58000006, 0xcf000078, 0xa78000d0,\n 0xc0400000, 0x58180000, 0xc84000b8, 0xc1000000, 0x58180004, 0xc90000b8, 0x5dc40000, 0x84000092,\n 0xc1ee0002, 0x5ddc0002, 0x445ce000, 0x84000072, 0x450c8000, 0x45348000, 0x58180004, 0xcd0000b8,\n 0x5dd00000, 0x84000012, 0xa52e0038, 0xc0007e28, 0xc84000f8, 0xc1c00002, 0x69e0e000, 0x705c2000,\n 0xcc4000f8, 0x6e106000, 0x5910b640, 0x58100006, 0xc98000f8, 0x58100004, 0xc94000f8, 0x418cc000,\n 0x58100006, 0xcd8000f8, 0x59540002, 0x58100004, 0xcd4000f8, 0x6e242000, 0x5a645fe0, 0xc0c00000,\n 0x58240002, 0xc8c20078, 0xc1000000, 0x58240000, 0xc9020038, 0x582c002a, 0xcc8000f8, 0x582c002c,\n 0xce0000f8, 0xc48000f8, 0xc94000f8, 0x58080002, 0xc98000f8, 0x582c0034, 0xcd4000f8, 0x582c0036,\n 0xcd8000f8, 0x582c0038, 0xc1c00000, 0xcdc000f8, 0x582c0032, 0xc1c00000, 0xcdc000f8, 0x6d102000,\n 0x58cc0004, 0x450ce000, 0xc1c00000, 0xc5cc00fe, 0x58240002, 0x6cde0000, 0xcdc21078, 0xc0e00002,\n 0x68e06000, 0xd8f000f8, 0xdcb800f9, 0xdcb400f8, 0xdd3000f9, 0xc0006910, 0xc8c000f9, 0xc90000f8,\n 0xc1c00000, 0xc1400040, 0x60c04000, 0x7494e000, 0x8400007a, 0xc1400080, 0x61004000, 0x58880040,\n 0x7494e000, 0x84000052, 0x00000000, 0xab6c0002, 0x00000000, 0x00000000, 0x98405d98, 0xc0006902,\n 0xc8c000f8, 0xc3c00000, 0x8000ff58, 0xc0006910, 0xc1c00000, 0xc49ca000, 0x401c0000, 0xc8c000f8,\n 0xc1000002, 0xc1400000, 0xc4940020, 0x6914e000, 0x70dc6000, 0xccc000f8, 0x582c0020, 0xcc8000f8,\n 0xc1c00002, 0x582c0022, 0xcdc000f8, 0xc2409c00, 0x6c9c6000, 0x425d2000, 0xc2807600, 0x6c9c6000,\n 0x429d4000, 0x582c002c, 0xc98000f8, 0x582c0026, 0xce8000f8, 0x582c0028, 0xce4000f8, 0x58240008,\n 0xcd8000f8, 0x5838000a, 0xc98000f8, 0xc000ea10, 0xc2000000, 0xca3c0070, 0x6d9c8000, 0x41d8e000,\n 0x421d0000, 0x5a204000, 0x582c002a, 0xc98000f8, 0xc1400000, 0xc1000000, 0xc58000f8, 0xc9c000f8,\n 0x5824000a, 0xcd8000f8, 0x5824000c, 0xcdc000f8, 0x59ac0034, 0x58180000, 0xc942e020, 0x58180002,\n 0xc90000e0, 0xc000401e, 0xc98000f8, 0x58280002, 0xc1c00000, 0xcdc00078, 0x41148000, 0xc1400000,\n 0xc5941078, 0x7d40a000, 0x75148000, 0xc1400000, 0xc5961078, 0x71148000, 0x58280004, 0xcd0000e0,\n 0x58a40000, 0x586c0008, 0xc44000f8, 0xc8c000f9, 0xc90000f9, 0xc94000f8, 0xc48000f8, 0xccc000f9,\n 0xcd0000f9, 0xcd4000f9, 0x5df00000, 0x84000138, 0x58200000, 0xc1800000, 0xcd8000f9, 0xcd8000f9,\n 0xcd8000f9, 0xcd8000f9, 0xcd8000f9, 0xcd8000f9, 0xcd8000f9, 0xcd8000f9, 0xcd8000f9, 0xcd8000f9,\n 0xcd8000f9, 0xcd8000f9, 0xcd8000f9, 0xcd8000f9, 0xcd8000f9, 0xcd8000f9, 0xcd8000f9, 0xc18001ea,\n 0xc1c00002, 0x75f4e000, 0xc1c001e0, 0xc5d800fa, 0xc1400000, 0x6d5c4010, 0x421c0000, 0xc1c00006,\n 0x755c8000, 0x5dd00000, 0xcd80183a, 0x5dd00002, 0xcd80103a, 0x5dd00004, 0xcd80083a, 0x5dd00006,\n 0xcd80003a, 0x5b300008, 0xc000fa40, 0xc93c00f8, 0xc1400000, 0x582c0002, 0xc9428018, 0xc0400000,\n 0xc0800080, 0x44944000, 0xc45800f8, 0xc1c00200, 0x75d0e000, 0xc49c00f8, 0xc5d800fa, 0x582c0030,\n 0xcd4000f8, 0xd97800f8, 0x59ec0034, 0xc0c00000, 0x582c0002, 0xc8c10038, 0xc1000000, 0x581c0000,\n 0xc9000078, 0x00000000, 0x00000000, 0xc50800f8, 0x4518e000, 0xc59c00f8, 0xc5c800fc, 0xc4d400f8,\n 0x44c8e000, 0xc49c00f8, 0xc5d400fc, 0x582c002e, 0xcd4000f8, 0x582c0032, 0xc88000f8, 0xdf9000f8,\n 0x4150e000, 0x41c8e000, 0xd9f800f8, 0x41f0e000, 0x5ddc0086, 0x88000082, 0xc18000a0, 0x6f1c4010,\n 0x421c0000, 0xc1c00006, 0x771ca000, 0x5dd40000, 0xcd80183a, 0x5dd40002, 0xcd80103a, 0x5dd40004,\n 0xcd80083a, 0x5dd40006, 0xcd80003a, 0x5b300002, 0x80000158, 0x00000000, 0x00000000, 0x00000000,\n 0xdf9400f8, 0xc1008fe0, 0x6d5c4010, 0x411c0000, 0xc98000f8, 0xc1c00000, 0xc55c0308, 0x699cc000,\n 0x6d9b0010, 0x6f1c4010, 0x421c0000, 0xc1c00006, 0x771c6000, 0x5dcc0000, 0xcd80183a, 0x5dcc0002,\n 0xcd80103a, 0x5dcc0004, 0xcd80083a, 0x5dcc0006, 0xcd80003a, 0x5b300002, 0xc18000a0, 0x6f1c4010,\n 0x421c0000, 0xc1c00006, 0x771ca000, 0x5dd40000, 0xcd80183a, 0x5dd40002, 0xcd80103a, 0x5dd40004,\n 0xcd80083a, 0x5dd40006, 0xcd80003a, 0x5b300002, 0x582c0022, 0xc1c00000, 0xcdc000f8, 0x00000000,\n 0x5df00088, 0x88000578, 0x582c0032, 0xca0000f8, 0x582c0038, 0xc8c000f8, 0x5de00000, 0x8400004a,\n 0x582c0020, 0xc98000f8, 0x98405130, 0xc2840002, 0xc5a80528, 0xc2400000, 0x5df00088, 0x88000508,\n 0x582c0020, 0xc98000f8, 0xc2800000, 0xc2400000, 0xc5a80528, 0x582c002e, 0xc98000f8, 0xc1000088,\n 0x45308000, 0xc51400f8, 0x4590e000, 0xc59c00f8, 0xc5d400fc, 0xc5681930, 0x5838000a, 0xc90000f8,\n 0xc7281230, 0xc7e80008, 0xc5280b30, 0xd93800f8, 0xc1c00002, 0xc5e80400, 0x4594e000, 0x8400001a,\n 0xc1c00000, 0xc5e80400, 0x5dd80000, 0x8400002a, 0xc1c00002, 0xc5e80300, 0xc1c00002, 0xc5e80200,\n 0x582c0022, 0xc94000f8, 0xc7640e08, 0x00000000, 0x5d540002, 0x8400001a, 0xc1c00002, 0xc5e40d00,\n 0xc0c00000, 0xc68f2030, 0x430c8000, 0xc5241838, 0xc0800088, 0x44904000, 0xc1c00000, 0xc5c800fc,\n 0x582c0030, 0xc94000f8, 0xc0400000, 0x582c0002, 0xc8420018, 0xc49000f8, 0x4548e000, 0xc55c00f8,\n 0xc5d000fc, 0xc5241418, 0x44546000, 0xc4e41018, 0x4550a000, 0x582c0030, 0xcd4000f8, 0xc0c00000,\n 0xc68f2030, 0x458cc000, 0x582c002e, 0xcd8000f8, 0x43118000, 0x430d8000, 0xdf9800f8, 0xc000ea10,\n 0xc1400000, 0xc97c0070, 0x6d9c8000, 0x41d8e000, 0x415ca000, 0x59544000, 0x00000000, 0xc1000000,\n 0xc0000000, 0xc9140038, 0x00000000, 0x00000000, 0x59100002, 0xcd140038, 0x984063f0, 0xc68c00f8,\n 0xc65000f8, 0x00000000, 0x5df00088, 0x8800e6a2, 0x00000000, 0x80000218, 0xd87800f8, 0xc1000088,\n 0x45308000, 0xc51400f8, 0x4610e000, 0xc61c00f8, 0xc5d400fc, 0xc5681930, 0x46150000, 0x582c0032,\n 0xce0000f8, 0xc56000f8, 0x5838000a, 0xc94000f8, 0xc7281230, 0xc7e80008, 0xc5680b30, 0xc000ea10,\n 0xc1000000, 0xc93c0070, 0x6d5c8000, 0x41d4e000, 0x411c8000, 0x59104000, 0x6f1c4010, 0x411c0000,\n 0xc94000f8, 0xc1c00000, 0xc71c0308, 0x695ca008, 0xc4d71838, 0x695ca018, 0xcd4000f8, 0x5b300002,\n 0x5e200002, 0x84000062, 0x6ccd0000, 0x6f1c4010, 0x411c0000, 0xc94000f8, 0xc1c00000, 0xc71c0308,\n 0x695ca008, 0xc4d71838, 0x695ca018, 0xcd4000f8, 0x5b300002, 0x6ccd0000, 0x582c0038, 0xccc000f8,\n 0xc1400000, 0xc0000000, 0xc9500038, 0x00000000, 0x00000000, 0x59540002, 0xcd500038, 0xdfa000f8,\n 0x984063f0, 0xc68c00f8, 0xc65000f8, 0x00000000, 0x9e000000, 0x00000000, 0x00000000, 0x00000000,\n 0x5df00000, 0x840000ba, 0xc1c00002, 0xc000691c, 0xcdc000f8, 0x5838000a, 0xc94000f8, 0xc1000000,\n 0xc000ea14, 0xc93c0038, 0x59540002, 0x00000000, 0x4514e000, 0xc1c00000, 0xc5d400fe, 0x5838000a,\n 0xcd4000f8, 0x58380004, 0xc94000f8, 0x00000000, 0x00000000, 0x59540002, 0x58380004, 0xcd4000f8,\n 0x5df00000, 0x84000058, 0xa7400020, 0x00000000, 0x6ff42000, 0x8000df80, 0x5bfc0002, 0x5dfc0002,\n 0x8400dcfa, 0x00000000, 0x00000000, 0x00000000, 0xab6c0052, 0x98405d98, 0xc0006902, 0xc8c000f8,\n 0xc3c00000, 0xab6c002a, 0x98405d98, 0xc0006902, 0xc8c000f8, 0xc3c00000, 0xc0004032, 0xcbc000f8,\n 0xc0004038, 0xcb8000f8, 0xc000691a, 0xcb0000f8, 0xc000403a, 0xcb4000f8, 0xc72c00f8, 0xa7800058,\n 0xc2800000, 0x00000000, 0x98405670, 0xc0c07c80, 0xc0007c00, 0x00000000, 0x984056d8, 0xc0006952,\n 0xc80000f8, 0xc1000000, 0xa7900058, 0xc2800002, 0x00000000, 0x98405670, 0xc0c07c80, 0xc0007c00,\n 0x00000000, 0x984056d8, 0xc0006952, 0xc80000f8, 0xc1000000, 0x472ce000, 0x8400023a, 0xc0c00000,\n 0xc78e0020, 0xc1c00002, 0x69cc8000, 0xc78f0020, 0x69cce000, 0x711c8000, 0xc000f41a, 0xcfc000f8,\n 0xc1c00000, 0xc7dc4050, 0x581cc000, 0xcb0000f8, 0x00000000, 0x00000000, 0x76d16000, 0x7d008000,\n 0x77118000, 0x732d8000, 0xcf0000f8, 0xc000691a, 0xcec000f8, 0x80000180, 0x5ea80000, 0xc40c00fa,\n 0xc2400000, 0x580c0004, 0xca400038, 0x58cc0040, 0xc1c00000, 0x580c0004, 0xc9c00038, 0x9c400000,\n 0x00000000, 0x00000000, 0x725d2000, 0x62406028, 0x84000032, 0xc9cc00f8, 0x00000000, 0x00000000,\n 0x411c8000, 0x8000ffd0, 0xc1400000, 0xc7970020, 0x6f4e0010, 0x5de80000, 0xc74c00fa, 0xc7960022,\n 0xc1c00000, 0xc4dd0038, 0x45d0e000, 0x88000048, 0xc1c00000, 0xc4dc0038, 0x451ce000, 0x88000050,\n 0x9c400000, 0x00000000, 0x00000000, 0x00000000, 0xc1c00002, 0x9c400000, 0x69d4e000, 0x7dc0e000,\n 0x76dd6000, 0x9c400000, 0xc1c00002, 0x69d4e000, 0x72dd6000, 0xc0004028, 0xcbc000f8, 0xc000691c,\n 0xcb8000f8, 0xa7c0b3a0, 0x00000000, 0x5df80000, 0x8400b388, 0xc1c00002, 0xc000e070, 0xcdc00000,\n 0x8000b368, 0xdcbc00f9, 0xdcb800f8, 0xdd3400f9, 0xc2400040, 0xc000401e, 0xd08000f8, 0xc000690c,\n 0xc8c000f9, 0xc90000f8, 0xc1c00000, 0x60c18000, 0x7724e000, 0x84000052, 0x61018000, 0x7724e000,\n 0x84000032, 0x984065b0, 0x00000000, 0x00000000, 0x00000000, 0x8000ff90, 0x5b300040, 0xc2c09400,\n 0x6f1c6000, 0x42dd6000, 0xc2809800, 0x429d4000, 0x58340022, 0xcf0000f8, 0x582c0008, 0xcf8000f8,\n 0xc000690c, 0xc1c00000, 0xc71ca000, 0x401c0000, 0xc8c000f8, 0xc2000002, 0x6a30e000, 0x70dc6000,\n 0xccc000f8, 0x58340008, 0xc8c000f9, 0xc90000f9, 0xc94000f9, 0x582c0000, 0xccc000f9, 0xcd0000f9,\n 0xcd4000f9, 0x58340010, 0xc9c000f9, 0xc8c000f9, 0xc90000f9, 0xc94000f9, 0xc98000f9, 0xc84000f9,\n 0xc88000f9, 0x58280000, 0xcdc000f9, 0xccc000f9, 0xcd0000f9, 0xcd4000f9, 0xcd8000f9, 0xcc4000f9,\n 0xcc8000f9, 0xc1c00000, 0x5828000e, 0xc9c3e000, 0x00000000, 0x00000000, 0x5ddc0002, 0x8400026a,\n 0xc000401a, 0xc9c000f8, 0x00000000, 0xc000f41a, 0xcdc000f8, 0xc000691e, 0xc88000f8, 0xc0006908,\n 0xc8c000f8, 0xc1804c00, 0xc1000100, 0xa9440028, 0xc0004056, 0xc9800078, 0x6d102010, 0x00000000,\n 0x6d1c2010, 0x5ddc0004, 0x449ce000, 0x88000150, 0x418c0000, 0x58000000, 0xc943e000, 0x58cc0004,\n 0x450ce000, 0xc1c00000, 0xc5cc00fe, 0xa5400110, 0xc1000000, 0x58000002, 0xc90000e0, 0xc1c00000,\n 0xc0004022, 0xc9c20008, 0x5828000e, 0xcd0000e0, 0x411ce000, 0xc1400000, 0xdc941078, 0x7d40a000,\n 0x75d4e000, 0xc1400000, 0xdc961078, 0x71d4e000, 0x58280004, 0xcdc000e0, 0x5828000e, 0xc1fe0002,\n 0xcdc3ff00, 0x5828000e, 0xc1fc0000, 0xcdc3de00, 0x58340020, 0xc1c00000, 0xcdc000f8, 0xc0006908,\n 0xccc000f8, 0x58880002, 0xc000691e, 0xcc8000f8, 0x80000130, 0xc0c0b600, 0x6f9c6000, 0x40dc6000,\n 0x580c0004, 0xc90000f8, 0x5828000e, 0xc1fc0002, 0xcdc3de00, 0x58340020, 0xc1c00002, 0xcdc000f8,\n 0x59100002, 0x580c0004, 0xcd0000f8, 0x800000b8, 0xc0c00000, 0xc0004022, 0xc8c20008, 0xc1000000,\n 0x5828000e, 0xc90000e0, 0x5828000e, 0xc1fc0000, 0xcdc3de00, 0x58340020, 0xc1c00000, 0xcdc000f8,\n 0x410ce000, 0xc1400000, 0xdc941078, 0x7d40a000, 0x75d4e000, 0xc1400000, 0xdc961078, 0x71d4e000,\n 0x58280004, 0xcdc000e0, 0x94000000, 0xc1c00002, 0xc000691c, 0xcdc000f8, 0xd87800f8, 0xc3800000,\n 0x580c7400, 0xca4000f9, 0xca0000f8, 0xc3400000, 0xc3c00000, 0xc67c0008, 0x5dfc0004, 0x88000480,\n 0xc639c008, 0xc674a028, 0xc0c00000, 0xc64d6030, 0xc000ea10, 0xc3000000, 0xcb3c0070, 0x6cdc8000,\n 0x41cce000, 0x431d8000, 0x5b304000, 0x6faca000, 0x5aec7c00, 0xc0c00000, 0xc0000000, 0xc8f00038,\n 0x6f686000, 0x5aa89c00, 0x5ccc0002, 0xccf00038, 0xc1000000, 0xc6128018, 0x5dd00000, 0x840000f2,\n 0xc1800000, 0xc0800000, 0xc61a0018, 0xc60b0038, 0xc1c40002, 0x419cc000, 0x6d9c4010, 0x429c0000,\n 0xc94000f8, 0xc1c00000, 0xc59c0308, 0x695ca000, 0x6d570010, 0x59980002, 0x6c9c4010, 0x431c0000,\n 0xc1c00006, 0x749c2000, 0x5dc40000, 0xcd40183a, 0x5dc40002, 0xcd40103a, 0x5dc40004, 0xcd40083a,\n 0x5dc40006, 0xcd40003a, 0x58880002, 0x5d100002, 0x8400ff50, 0xa61a00e8, 0xc000401a, 0xc9c000f8,\n 0x00000000, 0xc000f41a, 0xcdc000f8, 0x5828000a, 0xc90000f8, 0x5828000c, 0xc94000f8, 0xc0000000,\n 0xc1c00000, 0xc5d41f00, 0xcd5000f8, 0xc1000002, 0x58280008, 0xc94000f8, 0x5df40040, 0xc0006912,\n 0x44100004, 0xc98000f8, 0x6934e000, 0x7dc0e000, 0x759cc000, 0xcd8000f8, 0xa9440022, 0xc1b00002,\n 0x6994c000, 0xd9b000f8, 0x5ccc0000, 0x840001e0, 0x6fcca000, 0x58cc7d80, 0x580c0006, 0xc90000f8,\n 0xc1400000, 0xc615a000, 0x59100002, 0x580c0006, 0xcd0000f8, 0xc1c00000, 0x7d40a000, 0xc55c0000,\n 0x582c0024, 0xcdc000f8, 0xa61a0168, 0x7f80e000, 0xc5f80000, 0x6faca000, 0x5aec7c00, 0x582c0024,\n 0xc94000f8, 0x580c0004, 0xc98000f8, 0x5dd40002, 0x8400011a, 0x5dd00080, 0x8800007a, 0xc000ea28,\n 0xc1d2007e, 0xcdfd2928, 0xc000ea28, 0xc1d00002, 0xcdfd0800, 0x5dd0007e, 0xc000ea28, 0x6ddd2000,\n 0xcdfd2928, 0xc000ea28, 0xc1d00002, 0xcdfd0800, 0x80000038, 0xc000ea28, 0x6d1d2000, 0xcdfd2928,\n 0xc000ea28, 0xc1d00002, 0xcdfd0800, 0x583c6948, 0xc9c000f8, 0x00000000, 0x00000000, 0x41d0e000,\n 0xcdc000f8, 0x4590c000, 0x580c0004, 0xcd8000f8, 0x580c0006, 0xc1c00000, 0xcdc000f8, 0xc0006902,\n 0xc8c000f8, 0x00000000, 0x00000000, 0x58cc0004, 0xc1c00200, 0x45cce000, 0xc1c00000, 0xc5cc00fe,\n 0xccc000f8, 0xc000f01e, 0xc1d00002, 0xcdc10800, 0xdf8400f8, 0x9c400000, 0x00000000, 0x00000000,\n 0x00000000, 0xc0006904, 0xc94000f8, 0xc000fe08, 0x49c00040, 0x00000000, 0x00000000, 0x5ddc0100,\n 0x8800ffd8, 0xab68008a, 0x00000000, 0x58147200, 0xccc000f9, 0xcd0000f9, 0xc000f016, 0xc1d00002,\n 0xcdc10800, 0x59540004, 0xc1c00200, 0x45d4e000, 0xc1c00000, 0xc5d400fe, 0x9c400000, 0xc0006904,\n 0xcd4000f8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x8000ff30, 0xc0006906, 0xc94000f8,\n 0xc000fe0a, 0x49c00040, 0x00000000, 0x00000000, 0x5ddc0100, 0x8800ffd8, 0xab6a008a, 0x00000000,\n 0x58147400, 0xccc000f9, 0xcd0000f9, 0xc000f404, 0xc1d00002, 0xcdc10800, 0x59540004, 0xc1c00200,\n 0x45d4e000, 0xc1c00000, 0xc5d400fe, 0x9c400000, 0xc0006906, 0xcd4000f8, 0x00000000, 0x00000000,\n 0x00000000, 0x00000000, 0x8000ff30, 0xc08000a0, 0x74d0c000, 0x84000090, 0x78d0c000, 0x8400006a,\n 0x61800018, 0x6180e008, 0x441cc000, 0x84000060, 0x5d940000, 0x84000050, 0x60c04008, 0xa48a0040,\n 0x9c400000, 0x61004008, 0x58880040, 0x00000000, 0xa5400018, 0x00000000, 0xc0800080, 0x9c400000,\n 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xc000f412, 0xc9c000f8,\n 0xc1800000, 0xc0800000, 0xa5c00580, 0xc5d82028, 0xc1c00002, 0xc000691c, 0xcdc000f8, 0x6d886000,\n 0x59089800, 0x5810000e, 0xc9c3c000, 0x59489400, 0xd9b800f8, 0xa5c004ca, 0x58140008, 0xc98000f8,\n 0xc0c07b00, 0xc0800000, 0x6d9ca000, 0x40dc6000, 0xd9b800f8, 0x580c0002, 0xc8808000, 0x00000000,\n 0x00000000, 0xa480004a, 0x580c0004, 0xc98000f8, 0x58140002, 0xc88000f8, 0x00000000, 0x00000000,\n 0x4498e000, 0x84000110, 0xc1c00000, 0x580c0002, 0xc9c04000, 0x00000000, 0x00000000, 0xa5c0004a,\n 0x580c0006, 0xc98000f8, 0x58140004, 0xc88000f8, 0x00000000, 0x00000000, 0x4498e000, 0x840000a0,\n 0xc0800000, 0x58100002, 0xc8800078, 0x580c001e, 0xc94000f8, 0xc1800000, 0x580c0002, 0xc9810038,\n 0x40944000, 0xa4be0052, 0xc1400000, 0x4498e000, 0x88000118, 0x580c0002, 0xc940e000, 0x00000000,\n 0x00000000, 0xa54000ca, 0xc1c00000, 0x00000000, 0x00000000, 0x00000000, 0xdf9400f8, 0x00000000,\n 0x00000000, 0xc1800000, 0xc5582000, 0xa5400042, 0xc000fb64, 0xc1c00002, 0xcdd80000, 0xc000facc,\n 0xc1c40002, 0xcdd84200, 0x800002a0, 0xc000fb64, 0xc1c20002, 0xcdd82100, 0xc000facc, 0xc1c60002,\n 0xcdd86300, 0x80000268, 0x580c0002, 0xc9c10038, 0x00000000, 0x00000000, 0x589c0000, 0xc000401a,\n 0xc9c000f8, 0x00000000, 0xc000f41a, 0xcdc000f8, 0xc000690a, 0xc94000f8, 0xc0c04c00, 0xc1800100,\n 0xa9440028, 0xc0004056, 0xc8c00078, 0x6d982010, 0x00000000, 0x40d46000, 0x59540004, 0x4594e000,\n 0xc1c00000, 0xc5d400fe, 0xc000690a, 0xcd4000f8, 0xc1400000, 0x5810000e, 0xc94000e0, 0xa9440022,\n 0xc1800000, 0xc4c000f8, 0xc98000f8, 0x580c0002, 0xcd4000e0, 0xc4980078, 0xdf9400f8, 0xc1f80006,\n 0xc5db9c18, 0x00000000, 0xc5581508, 0xc4c000f8, 0xcd8000f8, 0xc000e408, 0xc1c00002, 0xcdc000f8,\n 0xc000691e, 0xc98000f8, 0x5810000e, 0xc1fe0000, 0xcdc3ff00, 0x5d980002, 0xc000691e, 0xcd8000f8,\n 0xc1800000, 0x58100002, 0xc9800078, 0x6d486000, 0x5888b600, 0x58080006, 0xc9c000f8, 0x00000000,\n 0x00000000, 0x419cc000, 0x58080006, 0xcd8000f8, 0xc1800000, 0xc5582000, 0xa540002a, 0xc000fb60,\n 0xc1c40002, 0xcdd84200, 0x80000020, 0xc000fb60, 0xc1c60002, 0xcdd86300, 0xdf9400f8, 0xc1800002,\n 0x00000000, 0x00000000, 0x5dd40040, 0xc000690e, 0x44180004, 0xc88000f8, 0x6994e000, 0x7dc0e000,\n 0x749c4000, 0xcc8000f8, 0x9c400000, 0x00000000, 0x00000000, 0x00000000, 0xc000403c, 0xc90000f8,\n 0xc1400000, 0xc4d60078, 0x4550e000, 0x8400003a, 0xcd4000f8, 0xc1c00000, 0xd9c400f9, 0xd9440078,\n 0xc1c00006, 0xd9c400f9, 0xc3c00000, 0xc4fc8018, 0x5bfc0002, 0xc1000000, 0xc140b7b8, 0xc3800000,\n 0x6fb44000, 0x4355a000, 0xc3000000, 0x58340006, 0xcb020038, 0xc2c00000, 0xc2800000, 0x5f300002,\n 0x84000080, 0x58340006, 0xcac00078, 0x58340002, 0xca800078, 0xc2000000, 0x58340002, 0xca020078,\n 0x42e92000, 0x00000000, 0x4624e000, 0xc62400fc, 0x58340000, 0xcb030038, 0x58340006, 0xce400078,\n 0x58340006, 0x6f1e0000, 0xcdc21038, 0x5bb80002, 0x47bce000, 0x8800ff1a, 0xa500003a, 0x00000000,\n 0xc1000002, 0xc3800000, 0xc3c00008, 0xc1404d48, 0x8000fee0, 0x80009bd8, 0x00000000, 0x00000000,\n 0x00000000, 0xa94e9bb8, 0xc0006954, 0xcbc000f8, 0xc3800000, 0xdd790038, 0x5ffc0002, 0xc7bc00fc,\n 0xc0006954, 0xcfc000f8, 0x88009b70, 0xc0004044, 0xcbc000f8, 0xc0004014, 0xcb8000f8, 0x5dfc0000,\n 0x84009b42, 0x6f9d0010, 0x739da000, 0x6f9e0010, 0x735da000, 0x6f9f0010, 0x735da000, 0xc1c0001e,\n 0x775da000, 0xc000e440, 0xcf4000f8, 0x80009ae8, 0x00000000, 0x00000000, 0x00000000,};\n\nstatic unsigned int firmware_binary_data[] = {\n};\n\n\n#endif  //  IFXMIPS_PTM_FW_VR9_H\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-ptm/src/ifxmips_ptm_ppe_amazon_se.h",
    "content": "/******************************************************************************\n**\n** FILE NAME    : ifxmips_ptm_ppe_amazon_se.h\n** PROJECT      : UEIP\n** MODULES      : PTM\n**\n** DATE         : 7 Jul 2009\n** AUTHOR       : Xu Liang\n** DESCRIPTION  : PTM driver header file (PPE register for Amazon-SE)\n** COPYRIGHT    :       Copyright (c) 2006\n**                      Infineon Technologies AG\n**                      Am Campeon 1-12, 85579 Neubiberg, Germany\n**\n**    This program is free software; you can redistribute it and/or modify\n**    it under the terms of the GNU General Public License as published by\n**    the Free Software Foundation; either version 2 of the License, or\n**    (at your option) any later version.\n**\n** HISTORY\n** $Date        $Author         $Comment\n** 07 JUL 2009  Xu Liang        Init Version\n*******************************************************************************/\n\n\n\n#ifndef IFXMIPS_PTM_PPE_AMAZON_SE_H\n#define IFXMIPS_PTM_PPE_AMAZON_SE_H\n\n\n\n/*\n *  FPI Configuration Bus Register and Memory Address Mapping\n */\n#define IFX_PPE                                 (KSEG1 | 0x1E180000)\n#define PP32_DEBUG_REG_ADDR(i, x)               ((volatile unsigned int*)(IFX_PPE + (((x) + 0x0000) << 2)))\n#define PPM_INT_REG_ADDR(i, x)                  ((volatile unsigned int*)(IFX_PPE + (((x) + 0x0030) << 2)))\n#define PP32_INTERNAL_RES_ADDR(i, x)            ((volatile unsigned int*)(IFX_PPE + (((x) + 0x0040) << 2)))\n#define CDM_CODE_MEMORY(i, x)                   ((volatile unsigned int*)(IFX_PPE + (((x) + 0x1000) << 2)))\n#define PPE_REG_ADDR(x)                         ((volatile unsigned int*)(IFX_PPE + (((x) + 0x4000) << 2)))\n#define CDM_DATA_MEMORY(i, x)                   ((volatile unsigned int*)(IFX_PPE + (((x) + 0x5000) << 2)))\n#define PPM_INT_UNIT_ADDR(x)                    ((volatile unsigned int*)(IFX_PPE + (((x) + 0x6000) << 2)))\n#define PPM_TIMER0_ADDR(x)                      ((volatile unsigned int*)(IFX_PPE + (((x) + 0x6100) << 2)))\n#define PPM_TASK_IND_REG_ADDR(x)                ((volatile unsigned int*)(IFX_PPE + (((x) + 0x6200) << 2)))\n#define PPS_BRK_ADDR(x)                         ((volatile unsigned int*)(IFX_PPE + (((x) + 0x6300) << 2)))\n#define PPM_TIMER1_ADDR(x)                      ((volatile unsigned int*)(IFX_PPE + (((x) + 0x6400) << 2)))\n#define SB_RAM0_ADDR(x)                         ((volatile unsigned int*)(IFX_PPE + (((x) + 0x8200) << 2)))\n#define SB_RAM1_ADDR(x)                         ((volatile unsigned int*)(IFX_PPE + (((x) + 0x8C00) << 2)))\n#define QSB_CONF_REG_ADDR(x)                    ((volatile unsigned int*)(IFX_PPE + (((x) + 0xC000) << 2)))\n\n/*\n *  DWORD-Length of Memory Blocks\n */\n#define PP32_DEBUG_REG_DWLEN                    0x0030\n#define PPM_INT_REG_DWLEN                       0x0010\n#define PP32_INTERNAL_RES_DWLEN                 0x00C0\n#define CDM_CODE_MEMORYn_DWLEN(n)               ((n) == 0 ? 0x1000 : 0x0800)\n#define PPE_REG_DWLEN                           0x1000\n#define CDM_DATA_MEMORY_DWLEN                   CDM_CODE_MEMORYn_DWLEN(1)\n#define PPM_INT_UNIT_DWLEN                      0x0100\n#define PPM_TIMER0_DWLEN                        0x0100\n#define PPM_TASK_IND_REG_DWLEN                  0x0100\n#define PPS_BRK_DWLEN                           0x0100\n#define PPM_TIMER1_DWLEN                        0x0100\n#define SB_RAM0_DWLEN                           0x0A00\n#define SB_RAM1_DWLEN                           0x0A00\n#define QSB_CONF_REG_DWLEN                      0x0100\n\n/*\n *  PP32 to FPI Address Mapping\n */\n#define SB_BUFFER(__sb_addr)                    ((volatile unsigned int *)((((__sb_addr) >= 0x0000) && ((__sb_addr) <= 0x0FFF)) ? PPE_REG_ADDR((__sb_addr) - 0x0000) :   \\\n                                                                           (((__sb_addr) >= 0x2200) && ((__sb_addr) <= 0x2BFF)) ? SB_RAM0_ADDR((__sb_addr) - 0x2200) :   \\\n                                                                           (((__sb_addr) >= 0x2C00) && ((__sb_addr) <= 0x35FF)) ? SB_RAM1_ADDR((__sb_addr) - 0x2C00) :   \\\n                                                                        0))\n\n/*\n *  PP32 Debug Control Register\n */\n#define NUM_OF_PP32                             1\n\n#define PP32_DBG_CTRL(n)                        PP32_DEBUG_REG_ADDR(n, 0x0000)\n\n#define DBG_CTRL_RESTART                        0\n#define DBG_CTRL_STOP                           1\n\n#define PP32_CTRL_CMD(n)                        PP32_DEBUG_REG_ADDR(n, 0x0B00)\n  #define PP32_CTRL_CMD_RESTART                 (1 << 0)\n  #define PP32_CTRL_CMD_STOP                    (1 << 1)\n  #define PP32_CTRL_CMD_STEP                    (1 << 2)\n  #define PP32_CTRL_CMD_BREAKOUT                (1 << 3)\n\n#define PP32_CTRL_OPT(n)                        PP32_DEBUG_REG_ADDR(n, 0x0C00)\n  #define PP32_CTRL_OPT_BREAKOUT_ON_STOP_ON     (3 << 0)\n  #define PP32_CTRL_OPT_BREAKOUT_ON_STOP_OFF    (2 << 0)\n  #define PP32_CTRL_OPT_BREAKOUT_ON_BREAKIN_ON  (3 << 2)\n  #define PP32_CTRL_OPT_BREAKOUT_ON_BREAKIN_OFF (2 << 2)\n  #define PP32_CTRL_OPT_STOP_ON_BREAKIN_ON      (3 << 4)\n  #define PP32_CTRL_OPT_STOP_ON_BREAKIN_OFF     (2 << 4)\n  #define PP32_CTRL_OPT_STOP_ON_BREAKPOINT_ON   (3 << 6)\n  #define PP32_CTRL_OPT_STOP_ON_BREAKPOINT_OFF  (2 << 6)\n  #define PP32_CTRL_OPT_BREAKOUT_ON_STOP(n)     (*PP32_CTRL_OPT(n) & (1 << 0))\n  #define PP32_CTRL_OPT_BREAKOUT_ON_BREAKIN(n)  (*PP32_CTRL_OPT(n) & (1 << 2))\n  #define PP32_CTRL_OPT_STOP_ON_BREAKIN(n)      (*PP32_CTRL_OPT(n) & (1 << 4))\n  #define PP32_CTRL_OPT_STOP_ON_BREAKPOINT(n)   (*PP32_CTRL_OPT(n) & (1 << 6))\n\n#define PP32_BRK_PC(n, i)                       PP32_DEBUG_REG_ADDR(n, 0x0900 + (i) * 2)\n#define PP32_BRK_PC_MASK(n, i)                  PP32_DEBUG_REG_ADDR(n, 0x0901 + (i) * 2)\n#define PP32_BRK_DATA_ADDR(n, i)                PP32_DEBUG_REG_ADDR(n, 0x0904 + (i) * 2)\n#define PP32_BRK_DATA_ADDR_MASK(n, i)           PP32_DEBUG_REG_ADDR(n, 0x0905 + (i) * 2)\n#define PP32_BRK_DATA_VALUE_RD(n, i)            PP32_DEBUG_REG_ADDR(n, 0x0908 + (i) * 2)\n#define PP32_BRK_DATA_VALUE_RD_MASK(n, i)       PP32_DEBUG_REG_ADDR(n, 0x0909 + (i) * 2)\n#define PP32_BRK_DATA_VALUE_WR(n, i)            PP32_DEBUG_REG_ADDR(n, 0x090C + (i) * 2)\n#define PP32_BRK_DATA_VALUE_WR_MASK(n, i)       PP32_DEBUG_REG_ADDR(n, 0x090D + (i) * 2)\n  #define PP32_BRK_CONTEXT_MASK(i)              (1 << (i))\n  #define PP32_BRK_CONTEXT_MASK_EN              (1 << 4)\n  #define PP32_BRK_COMPARE_GREATER_EQUAL        (1 << 5)    //  valid for break data value rd/wr only\n  #define PP32_BRK_COMPARE_LOWER_EQUAL          (1 << 6)\n  #define PP32_BRK_COMPARE_EN                   (1 << 7)\n\n#define PP32_BRK_SRC(n)                         PP32_DEBUG_REG_ADDR(n, 0x0F00)\n#define PP32_BRK_TRIG(n)                        PP32_BRK_SRC(n)\n  #define PP32_BRK_GRPi_PCn_ON(i, n)            ((3 << ((n) * 2)) << ((i) * 16))\n  #define PP32_BRK_GRPi_PCn_OFF(i, n)           ((2 << ((n) * 2)) << ((i) * 16))\n  #define PP32_BRK_GRPi_DATA_ADDRn_ON(i, n)     ((3 << ((n) * 2 + 4)) << ((i) * 16))\n  #define PP32_BRK_GRPi_DATA_ADDRn_OFF(i, n)    ((2 << ((n) * 2 + 4)) << ((i) * 16))\n  #define PP32_BRK_GRPi_DATA_VALUE_RDn_ON(i, n) ((3 << ((n) * 2 + 8)) << ((i) * 16))\n  #define PP32_BRK_GRPi_DATA_VALUE_RDn_OFF(i, n)((2 << ((n) * 2 + 8)) << ((i) * 16))\n  #define PP32_BRK_GRPi_DATA_VALUE_WRn_ON(i, n) ((3 << ((n) * 2 + 12)) << ((i) * 16))\n  #define PP32_BRK_GRPi_DATA_VALUE_WRn_OFF(i, n)((2 << ((n) * 2 + 12)) << ((i) * 16))\n  #define PP32_BRK_GRPi_PCn(k, i, n)            (*PP32_BRK_TRIG(k) & ((1 << ((n))) << ((i) * 8)))\n  #define PP32_BRK_GRPi_DATA_ADDRn(k, i, n)     (*PP32_BRK_TRIG(k) & ((1 << ((n) + 2)) << ((i) * 8)))\n  #define PP32_BRK_GRPi_DATA_VALUE_RDn(k, i, n) (*PP32_BRK_TRIG(k) & ((1 << ((n) + 4)) << ((i) * 8)))\n  #define PP32_BRK_GRPi_DATA_VALUE_WRn(k, i, n) (*PP32_BRK_TRIG(k) & ((1 << ((n) + 6)) << ((i) * 8)))\n\n#define PP32_CPU_STATUS(n)                      PP32_DEBUG_REG_ADDR(n, 0x0D00)\n#define PP32_HALT_STAT(n)                       PP32_CPU_STATUS(n)\n#define PP32_DBG_CUR_PC(n)                      PP32_DEBUG_REG_ADDR(n, 0x0F80)\n  #define PP32_CPU_USER_STOPPED(n)              (*PP32_CPU_STATUS(n) & (1 << 0))\n  #define PP32_CPU_USER_BREAKIN_RCV(n)          (*PP32_CPU_STATUS(n) & (1 << 1))\n  #define PP32_CPU_USER_BREAKPOINT_MET(n)       (*PP32_CPU_STATUS(n) & (1 << 2))\n  #define PP32_CPU_CUR_PC(n)                    (*PP32_DBG_CUR_PC(n) & 0xFFFF)\n\n#define PP32_BREAKPOINT_REASONS(n)              PP32_DEBUG_REG_ADDR(n, 0x0A00)\n  #define PP32_BRK_PC_MET(n, i)                 (*PP32_BREAKPOINT_REASONS(n) & (1 << (i)))\n  #define PP32_BRK_DATA_ADDR_MET(n, i)          (*PP32_BREAKPOINT_REASONS(n) & (1 << ((i) + 2)))\n  #define PP32_BRK_DATA_VALUE_RD_MET(n, i)      (*PP32_BREAKPOINT_REASONS(n) & (1 << ((i) + 4)))\n  #define PP32_BRK_DATA_VALUE_WR_MET(n, i)      (*PP32_BREAKPOINT_REASONS(n) & (1 << ((i) + 6)))\n  #define PP32_BRK_DATA_VALUE_RD_LO_EQ(n, i)    (*PP32_BREAKPOINT_REASONS(n) & (1 << ((i) * 2 + 8)))\n  #define PP32_BRK_DATA_VALUE_RD_GT_EQ(n, i)    (*PP32_BREAKPOINT_REASONS(n) & (1 << ((i) * 2 + 9)))\n  #define PP32_BRK_DATA_VALUE_WR_LO_EQ(n, i)    (*PP32_BREAKPOINT_REASONS(n) & (1 << ((i) * 2 + 12)))\n  #define PP32_BRK_DATA_VALUE_WR_GT_EQ(n, i)    (*PP32_BREAKPOINT_REASONS(n) & (1 << ((i) * 2 + 13)))\n//  #define PP32_BRK_CUR_CONTEXT(n)               ((*PP32_BREAKPOINT_REASONS(n) >> 16) & 0x03)\n#define PP32_DBG_TASK_NO(n)                     PP32_DEBUG_REG_ADDR(n, 0x0F81)\n  #define PP32_BRK_CUR_CONTEXT(n)               (*PP32_DBG_TASK_NO(n) & 0x03)\n\n#define PP32_GP_REG_BASE(n)                     PP32_DEBUG_REG_ADDR(n, 0x0E00)\n#define PP32_GP_CONTEXTi_REGn(n, i, j)          PP32_DEBUG_REG_ADDR(n, 0x0E00 + (i) * 16 + (j))\n\n/*\n *  Share Buffer\n */\n#define SB_MST_PRI0                             PPE_REG_ADDR(0x0300)\n#define SB_MST_PRI1                             PPE_REG_ADDR(0x0301)\n\n/*\n *  EMA Registers\n */\n#define EMA_CMDCFG                              PPE_REG_ADDR(0x0A00)\n#define EMA_DATACFG                             PPE_REG_ADDR(0x0A01)\n#define EMA_CMDCNT                              PPE_REG_ADDR(0x0A02)\n#define EMA_DATACNT                             PPE_REG_ADDR(0x0A03)\n#define EMA_ISR                                 PPE_REG_ADDR(0x0A04)\n#define EMA_IER                                 PPE_REG_ADDR(0x0A05)\n#define EMA_CFG                                 PPE_REG_ADDR(0x0A06)\n#define EMA_SUBID                               PPE_REG_ADDR(0x0A07)\n\n#define EMA_ALIGNMENT                           4\n\n/*\n *  Mailbox IGU1 Interrupt\n */\n#define PPE_MAILBOX_IGU1_INT                    INT_NUM_IM2_IRL13\n\n\n\n#endif  //  IFXMIPS_PTM_PPE_AMAZON_SE_H\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-ptm/src/ifxmips_ptm_ppe_ar9.h",
    "content": "/******************************************************************************\n**\n** FILE NAME    : ifxmips_ptm_ppe_ar9.h\n** PROJECT      : UEIP\n** MODULES      : PTM\n**\n** DATE         : 7 Jul 2009\n** AUTHOR       : Xu Liang\n** DESCRIPTION  : PTM driver header file (PPE register for AR9)\n** COPYRIGHT    :       Copyright (c) 2006\n**                      Infineon Technologies AG\n**                      Am Campeon 1-12, 85579 Neubiberg, Germany\n**\n**    This program is free software; you can redistribute it and/or modify\n**    it under the terms of the GNU General Public License as published by\n**    the Free Software Foundation; either version 2 of the License, or\n**    (at your option) any later version.\n**\n** HISTORY\n** $Date        $Author         $Comment\n** 07 JUL 2009  Xu Liang        Init Version\n*******************************************************************************/\n\n\n\n#ifndef IFXMIPS_PTM_PPE_AR9_H\n#define IFXMIPS_PTM_PPE_AR9_H\n\n\n\n/*\n *  FPI Configuration Bus Register and Memory Address Mapping\n */\n#define IFX_PPE                         (KSEG1 | 0x1E180000)\n#define PP32_DEBUG_REG_ADDR(i, x)       ((volatile unsigned int*)(IFX_PPE + (((x) + 0x0000) << 2)))\n#define PPM_INT_REG_ADDR(i, x)          ((volatile unsigned int*)(IFX_PPE + (((x) + 0x0030) << 2)))\n#define PP32_INTERNAL_RES_ADDR(i, x)    ((volatile unsigned int*)(IFX_PPE + (((x) + 0x0040) << 2)))\n#define CDM_CODE_MEMORY(i, x)           ((volatile unsigned int*)(IFX_PPE + (((x) + 0x1000) << 2)))\n#define PPE_REG_ADDR(x)                 ((volatile unsigned int*)(IFX_PPE + (((x) + 0x4000) << 2)))\n#define CDM_DATA_MEMORY(i, x)           ((volatile unsigned int*)(IFX_PPE + (((x) + 0x5000) << 2)))\n#define PPM_INT_UNIT_ADDR(x)            ((volatile unsigned int*)(IFX_PPE + (((x) + 0x6000) << 2)))\n#define PPM_TIMER0_ADDR(x)              ((volatile unsigned int*)(IFX_PPE + (((x) + 0x6100) << 2)))\n#define PPM_TASK_IND_REG_ADDR(x)        ((volatile unsigned int*)(IFX_PPE + (((x) + 0x6200) << 2)))\n#define PPS_BRK_ADDR(x)                 ((volatile unsigned int*)(IFX_PPE + (((x) + 0x6300) << 2)))\n#define PPM_TIMER1_ADDR(x)              ((volatile unsigned int*)(IFX_PPE + (((x) + 0x6400) << 2)))\n#define SB_RAM0_ADDR(x)                 ((volatile unsigned int*)(IFX_PPE + (((x) + 0x8000) << 2)))\n#define SB_RAM1_ADDR(x)                 ((volatile unsigned int*)(IFX_PPE + (((x) + 0x8800) << 2)))\n#define SB_RAM2_ADDR(x)                 ((volatile unsigned int*)(IFX_PPE + (((x) + 0x9000) << 2)))\n#define SB_RAM3_ADDR(x)                 ((volatile unsigned int*)(IFX_PPE + (((x) + 0x9800) << 2)))\n#define SB_RAM4_ADDR(x)                 ((volatile unsigned int*)(IFX_PPE + (((x) + 0xA000) << 2)))\n#define QSB_CONF_REG_ADDR(x)            ((volatile unsigned int*)(IFX_PPE + (((x) + 0xC000) << 2)))\n\n/*\n *  DWORD-Length of Memory Blocks\n */\n#define PP32_DEBUG_REG_DWLEN            0x0030\n#define PPM_INT_REG_DWLEN               0x0010\n#define PP32_INTERNAL_RES_DWLEN         0x00C0\n#define CDM_CODE_MEMORYn_DWLEN(n)       0x1000\n#define PPE_REG_DWLEN                   0x1000\n#define CDM_DATA_MEMORY_DWLEN           CDM_CODE_MEMORYn_DWLEN(1)\n#define PPM_INT_UNIT_DWLEN              0x0100\n#define PPM_TIMER0_DWLEN                0x0100\n#define PPM_TASK_IND_REG_DWLEN          0x0100\n#define PPS_BRK_DWLEN                   0x0100\n#define PPM_TIMER1_DWLEN                0x0100\n#define SB_RAM0_DWLEN                   0x0800\n#define SB_RAM1_DWLEN                   0x0800\n#define SB_RAM2_DWLEN                   0x0800\n#define SB_RAM3_DWLEN                   0x0800\n#define SB_RAM4_DWLEN                   0x0C00\n#define QSB_CONF_REG_DWLEN              0x0100\n\n/*\n *  PP32 to FPI Address Mapping\n */\n#define SB_BUFFER(__sb_addr)            ((volatile unsigned int *)((((__sb_addr) >= 0x0000) && ((__sb_addr) <= 0x0FFF)) ? PP32_DEBUG_REG_ADDR(0, (__sb_addr)):   \\\n                                                                   (((__sb_addr) >= 0x2000) && ((__sb_addr) <= 0x27FF)) ? SB_RAM0_ADDR((__sb_addr) - 0x2000) :   \\\n                                                                   (((__sb_addr) >= 0x2800) && ((__sb_addr) <= 0x2FFF)) ? SB_RAM1_ADDR((__sb_addr) - 0x2800) :   \\\n                                                                   (((__sb_addr) >= 0x3000) && ((__sb_addr) <= 0x37FF)) ? SB_RAM2_ADDR((__sb_addr) - 0x3000) :   \\\n                                                                   (((__sb_addr) >= 0x3800) && ((__sb_addr) <= 0x3FFF)) ? SB_RAM3_ADDR((__sb_addr) - 0x3800) :   \\\n                                                                   (((__sb_addr) >= 0x4000) && ((__sb_addr) <= 0x4BFF)) ? SB_RAM4_ADDR((__sb_addr) - 0x4000) :   \\\n                                                                0))\n\n/*\n *  PP32 Debug Control Register\n */\n#define NUM_OF_PP32                             1\n\n#define PP32_DBG_CTRL(n)                        PP32_DEBUG_REG_ADDR(n, 0x0000)\n\n#define DBG_CTRL_RESTART                        0\n#define DBG_CTRL_STOP                           1\n\n#define PP32_CTRL_CMD(n)                        PP32_DEBUG_REG_ADDR(n, 0x0B00)\n  #define PP32_CTRL_CMD_RESTART                 (1 << 0)\n  #define PP32_CTRL_CMD_STOP                    (1 << 1)\n  #define PP32_CTRL_CMD_STEP                    (1 << 2)\n  #define PP32_CTRL_CMD_BREAKOUT                (1 << 3)\n\n#define PP32_CTRL_OPT(n)                        PP32_DEBUG_REG_ADDR(n, 0x0C00)\n  #define PP32_CTRL_OPT_BREAKOUT_ON_STOP_ON     (3 << 0)\n  #define PP32_CTRL_OPT_BREAKOUT_ON_STOP_OFF    (2 << 0)\n  #define PP32_CTRL_OPT_BREAKOUT_ON_BREAKIN_ON  (3 << 2)\n  #define PP32_CTRL_OPT_BREAKOUT_ON_BREAKIN_OFF (2 << 2)\n  #define PP32_CTRL_OPT_STOP_ON_BREAKIN_ON      (3 << 4)\n  #define PP32_CTRL_OPT_STOP_ON_BREAKIN_OFF     (2 << 4)\n  #define PP32_CTRL_OPT_STOP_ON_BREAKPOINT_ON   (3 << 6)\n  #define PP32_CTRL_OPT_STOP_ON_BREAKPOINT_OFF  (2 << 6)\n  #define PP32_CTRL_OPT_BREAKOUT_ON_STOP(n)     (*PP32_CTRL_OPT(n) & (1 << 0))\n  #define PP32_CTRL_OPT_BREAKOUT_ON_BREAKIN(n)  (*PP32_CTRL_OPT(n) & (1 << 2))\n  #define PP32_CTRL_OPT_STOP_ON_BREAKIN(n)      (*PP32_CTRL_OPT(n) & (1 << 4))\n  #define PP32_CTRL_OPT_STOP_ON_BREAKPOINT(n)   (*PP32_CTRL_OPT(n) & (1 << 6))\n\n#define PP32_BRK_PC(n, i)                       PP32_DEBUG_REG_ADDR(n, 0x0900 + (i) * 2)\n#define PP32_BRK_PC_MASK(n, i)                  PP32_DEBUG_REG_ADDR(n, 0x0901 + (i) * 2)\n#define PP32_BRK_DATA_ADDR(n, i)                PP32_DEBUG_REG_ADDR(n, 0x0904 + (i) * 2)\n#define PP32_BRK_DATA_ADDR_MASK(n, i)           PP32_DEBUG_REG_ADDR(n, 0x0905 + (i) * 2)\n#define PP32_BRK_DATA_VALUE_RD(n, i)            PP32_DEBUG_REG_ADDR(n, 0x0908 + (i) * 2)\n#define PP32_BRK_DATA_VALUE_RD_MASK(n, i)       PP32_DEBUG_REG_ADDR(n, 0x0909 + (i) * 2)\n#define PP32_BRK_DATA_VALUE_WR(n, i)            PP32_DEBUG_REG_ADDR(n, 0x090C + (i) * 2)\n#define PP32_BRK_DATA_VALUE_WR_MASK(n, i)       PP32_DEBUG_REG_ADDR(n, 0x090D + (i) * 2)\n  #define PP32_BRK_CONTEXT_MASK(i)              (1 << (i))\n  #define PP32_BRK_CONTEXT_MASK_EN              (1 << 4)\n  #define PP32_BRK_COMPARE_GREATER_EQUAL        (1 << 5)    //  valid for break data value rd/wr only\n  #define PP32_BRK_COMPARE_LOWER_EQUAL          (1 << 6)\n  #define PP32_BRK_COMPARE_EN                   (1 << 7)\n\n#define PP32_BRK_TRIG(n)                        PP32_DEBUG_REG_ADDR(n, 0x0F00)\n  #define PP32_BRK_GRPi_PCn_ON(i, n)            ((3 << ((n) * 2)) << ((i) * 16))\n  #define PP32_BRK_GRPi_PCn_OFF(i, n)           ((2 << ((n) * 2)) << ((i) * 16))\n  #define PP32_BRK_GRPi_DATA_ADDRn_ON(i, n)     ((3 << ((n) * 2 + 4)) << ((i) * 16))\n  #define PP32_BRK_GRPi_DATA_ADDRn_OFF(i, n)    ((2 << ((n) * 2 + 4)) << ((i) * 16))\n  #define PP32_BRK_GRPi_DATA_VALUE_RDn_ON(i, n) ((3 << ((n) * 2 + 8)) << ((i) * 16))\n  #define PP32_BRK_GRPi_DATA_VALUE_RDn_OFF(i, n)((2 << ((n) * 2 + 8)) << ((i) * 16))\n  #define PP32_BRK_GRPi_DATA_VALUE_WRn_ON(i, n) ((3 << ((n) * 2 + 12)) << ((i) * 16))\n  #define PP32_BRK_GRPi_DATA_VALUE_WRn_OFF(i, n)((2 << ((n) * 2 + 12)) << ((i) * 16))\n  #define PP32_BRK_GRPi_PCn(k, i, n)            (*PP32_BRK_TRIG(k) & ((1 << ((n))) << ((i) * 8)))\n  #define PP32_BRK_GRPi_DATA_ADDRn(k, i, n)     (*PP32_BRK_TRIG(k) & ((1 << ((n) + 2)) << ((i) * 8)))\n  #define PP32_BRK_GRPi_DATA_VALUE_RDn(k, i, n) (*PP32_BRK_TRIG(k) & ((1 << ((n) + 4)) << ((i) * 8)))\n  #define PP32_BRK_GRPi_DATA_VALUE_WRn(k, i, n) (*PP32_BRK_TRIG(k) & ((1 << ((n) + 6)) << ((i) * 8)))\n\n#define PP32_CPU_STATUS(n)                      PP32_DEBUG_REG_ADDR(n, 0x0D00)\n#define PP32_HALT_STAT(n)                       PP32_CPU_STATUS(n)\n#define PP32_DBG_CUR_PC(n)                      PP32_CPU_STATUS(n)\n  #define PP32_CPU_USER_STOPPED(n)              (*PP32_CPU_STATUS(n) & (1 << 0))\n  #define PP32_CPU_USER_BREAKIN_RCV(n)          (*PP32_CPU_STATUS(n) & (1 << 1))\n  #define PP32_CPU_USER_BREAKPOINT_MET(n)       (*PP32_CPU_STATUS(n) & (1 << 2))\n  #define PP32_CPU_CUR_PC(n)                    (*PP32_CPU_STATUS(n) >> 16)\n\n#define PP32_BREAKPOINT_REASONS(n)              PP32_DEBUG_REG_ADDR(n, 0x0A00)\n  #define PP32_BRK_PC_MET(n, i)                 (*PP32_BREAKPOINT_REASONS(n) & (1 << (i)))\n  #define PP32_BRK_DATA_ADDR_MET(n, i)          (*PP32_BREAKPOINT_REASONS(n) & (1 << ((i) + 2)))\n  #define PP32_BRK_DATA_VALUE_RD_MET(n, i)      (*PP32_BREAKPOINT_REASONS(n) & (1 << ((i) + 4)))\n  #define PP32_BRK_DATA_VALUE_WR_MET(n, i)      (*PP32_BREAKPOINT_REASONS(n) & (1 << ((i) + 6)))\n  #define PP32_BRK_DATA_VALUE_RD_LO_EQ(n, i)    (*PP32_BREAKPOINT_REASONS(n) & (1 << ((i) * 2 + 8)))\n  #define PP32_BRK_DATA_VALUE_RD_GT_EQ(n, i)    (*PP32_BREAKPOINT_REASONS(n) & (1 << ((i) * 2 + 9)))\n  #define PP32_BRK_DATA_VALUE_WR_LO_EQ(n, i)    (*PP32_BREAKPOINT_REASONS(n) & (1 << ((i) * 2 + 12)))\n  #define PP32_BRK_DATA_VALUE_WR_GT_EQ(n, i)    (*PP32_BREAKPOINT_REASONS(n) & (1 << ((i) * 2 + 13)))\n  #define PP32_BRK_CUR_CONTEXT(n)               ((*PP32_BREAKPOINT_REASONS(n) >> 16) & 0x03)\n\n#define PP32_GP_REG_BASE(n)                     PP32_DEBUG_REG_ADDR(n, 0x0E00)\n#define PP32_GP_CONTEXTi_REGn(n, i, j)          PP32_DEBUG_REG_ADDR(n, 0x0E00 + (i) * 16 + (j))\n\n/*\n *  Share Buffer Registers\n */\n#define SB_MST_PRI0                     PPE_REG_ADDR(0x0300)\n#define SB_MST_PRI1                     PPE_REG_ADDR(0x0301)\n\n/*\n *  EMA Registers\n */\n#define EMA_CMDCFG                      PPE_REG_ADDR(0x0A00)\n#define EMA_DATACFG                     PPE_REG_ADDR(0x0A01)\n#define EMA_CMDCNT                      PPE_REG_ADDR(0x0A02)\n#define EMA_DATACNT                     PPE_REG_ADDR(0x0A03)\n#define EMA_ISR                         PPE_REG_ADDR(0x0A04)\n#define EMA_IER                         PPE_REG_ADDR(0x0A05)\n#define EMA_CFG                         PPE_REG_ADDR(0x0A06)\n#define EMA_SUBID                       PPE_REG_ADDR(0x0A07)\n\n#define EMA_ALIGNMENT                   4\n\n/*\n *  DPlus Registers\n */\n#define DM_RXDB                         PPE_REG_ADDR(0x0612)\n#define DM_RXCB                         PPE_REG_ADDR(0x0613)\n#define DM_RXCFG                        PPE_REG_ADDR(0x0614)\n#define DM_RXPGCNT                      PPE_REG_ADDR(0x0615)\n#define DM_RXPKTCNT                     PPE_REG_ADDR(0x0616)\n#define DS_RXDB                         PPE_REG_ADDR(0x0710)\n#define DS_RXCB                         PPE_REG_ADDR(0x0711)\n#define DS_RXCFG                        PPE_REG_ADDR(0x0712)\n#define DS_RXPGCNT                      PPE_REG_ADDR(0x0713)\n\n/*\n *  3-Port Switch Registers (partial)\n */\n#define IFX_SW                          (KSEG1 | 0x1E108000)\n#define SW_REG(off)                     ((volatile unsigned int*)(IFX_SW + (off)))\n#define SW_P2_CTL                       SW_REG(0x00C)\n\n\n/*\n *  Mailbox IGU1 Interrupt\n */\n#define PPE_MAILBOX_IGU1_INT            INT_NUM_IM2_IRL24\n\n\n\n#endif  //  IFXMIPS_PTM_PPE_AR9_H\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-ptm/src/ifxmips_ptm_ppe_common.h",
    "content": "/******************************************************************************\n**\n** FILE NAME    : ifxmips_ptm_ppe_common.h\n** PROJECT      : UEIP\n** MODULES      : PTM\n**\n** DATE         : 7 Jul 2009\n** AUTHOR       : Xu Liang\n** DESCRIPTION  : PTM driver header file (PPE register for all platform)\n** COPYRIGHT    :       Copyright (c) 2006\n**                      Infineon Technologies AG\n**                      Am Campeon 1-12, 85579 Neubiberg, Germany\n**\n**    This program is free software; you can redistribute it and/or modify\n**    it under the terms of the GNU General Public License as published by\n**    the Free Software Foundation; either version 2 of the License, or\n**    (at your option) any later version.\n**\n** HISTORY\n** $Date        $Author         $Comment\n** 07 JUL 2009  Xu Liang        Init Version\n*******************************************************************************/\n\n\n\n#ifndef IFXMIPS_PTM_PPE_COMMON_H\n#define IFXMIPS_PTM_PPE_COMMON_H\n\n\n\n#if defined(CONFIG_DANUBE)\n  #include \"ifxmips_ptm_ppe_danube.h\"\n#elif defined(CONFIG_AMAZON_SE)\n  #include \"ifxmips_ptm_ppe_amazon_se.h\"\n#elif defined(CONFIG_AR9)\n  #include \"ifxmips_ptm_ppe_ar9.h\"\n#elif defined(CONFIG_VR9)\n  #include \"ifxmips_ptm_ppe_vr9.h\"\n#else\n  #error Platform is not specified!\n#endif\n\n\n\n/*\n *  Code/Data Memory (CDM) Interface Configuration Register\n */\n#define CDM_CFG                         PPE_REG_ADDR(0x0100)\n\n#define CDM_CFG_RAM1                    GET_BITS(*CDM_CFG, 3, 2)\n#define CDM_CFG_RAM0                    (*CDM_CFG & (1 << 1))\n\n#define CDM_CFG_RAM1_SET(value)         SET_BITS(0, 3, 2, value)\n#define CDM_CFG_RAM0_SET(value)         ((value) ? (1 << 1) : 0)\n\n/*\n *  QSB Internal Cell Delay Variation Register\n */\n#define QSB_ICDV                        QSB_CONF_REG_ADDR(0x0007)\n\n#define QSB_ICDV_TAU                    GET_BITS(*QSB_ICDV, 5, 0)\n\n#define QSB_ICDV_TAU_SET(value)         SET_BITS(0, 5, 0, value)\n\n/*\n *  QSB Scheduler Burst Limit Register\n */\n#define QSB_SBL                         QSB_CONF_REG_ADDR(0x0009)\n\n#define QSB_SBL_SBL                     GET_BITS(*QSB_SBL, 3, 0)\n\n#define QSB_SBL_SBL_SET(value)          SET_BITS(0, 3, 0, value)\n\n/*\n *  QSB Configuration Register\n */\n#define QSB_CFG                         QSB_CONF_REG_ADDR(0x000A)\n\n#define QSB_CFG_TSTEPC                  GET_BITS(*QSB_CFG, 1, 0)\n\n#define QSB_CFG_TSTEPC_SET(value)       SET_BITS(0, 1, 0, value)\n\n/*\n *  QSB RAM Transfer Table Register\n */\n#define QSB_RTM                         QSB_CONF_REG_ADDR(0x000B)\n\n#define QSB_RTM_DM                      (*QSB_RTM)\n\n#define QSB_RTM_DM_SET(value)           ((value) & 0xFFFFFFFF)\n\n/*\n *  QSB RAM Transfer Data Register\n */\n#define QSB_RTD                         QSB_CONF_REG_ADDR(0x000C)\n\n#define QSB_RTD_TTV                     (*QSB_RTD)\n\n#define QSB_RTD_TTV_SET(value)          ((value) & 0xFFFFFFFF)\n\n/*\n *  QSB RAM Access Register\n */\n#define QSB_RAMAC                       QSB_CONF_REG_ADDR(0x000D)\n\n#define QSB_RAMAC_RW                    (*QSB_RAMAC & (1 << 31))\n#define QSB_RAMAC_TSEL                  GET_BITS(*QSB_RAMAC, 27, 24)\n#define QSB_RAMAC_LH                    (*QSB_RAMAC & (1 << 16))\n#define QSB_RAMAC_TESEL                 GET_BITS(*QSB_RAMAC, 9, 0)\n\n#define QSB_RAMAC_RW_SET(value)         ((value) ? (1 << 31) : 0)\n#define QSB_RAMAC_TSEL_SET(value)       SET_BITS(0, 27, 24, value)\n#define QSB_RAMAC_LH_SET(value)         ((value) ? (1 << 16) : 0)\n#define QSB_RAMAC_TESEL_SET(value)      SET_BITS(0, 9, 0, value)\n\n/*\n *  QSB Queue Scheduling and Shaping Definitions\n */\n#define QSB_WFQ_NONUBR_MAX              0x3f00\n#define QSB_WFQ_UBR_BYPASS              0x3fff\n#define QSB_TP_TS_MAX                   65472\n#define QSB_TAUS_MAX                    64512\n#define QSB_GCR_MIN                     18\n\n/*\n *  QSB Constant\n */\n#define QSB_RAMAC_RW_READ               0\n#define QSB_RAMAC_RW_WRITE              1\n\n#define QSB_RAMAC_TSEL_QPT              0x01\n#define QSB_RAMAC_TSEL_SCT              0x02\n#define QSB_RAMAC_TSEL_SPT              0x03\n#define QSB_RAMAC_TSEL_VBR              0x08\n\n#define QSB_RAMAC_LH_LOW                0\n#define QSB_RAMAC_LH_HIGH               1\n\n#define QSB_QPT_SET_MASK                0x0\n#define QSB_QVPT_SET_MASK               0x0\n#define QSB_SET_SCT_MASK                0x0\n#define QSB_SET_SPT_MASK                0x0\n#define QSB_SET_SPT_SBVALID_MASK        0x7FFFFFFF\n\n#define QSB_SPT_SBV_VALID               (1 << 31)\n#define QSB_SPT_PN_SET(value)           (((value) & 0x01) ? (1 << 16) : 0)\n#define QSB_SPT_INTRATE_SET(value)      SET_BITS(0, 13, 0, value)\n\n/*\n *  QSB Queue Parameter Table Entry and Queue VBR Parameter Table Entry\n */\n#if defined(__BIG_ENDIAN)\n    union qsb_queue_parameter_table {\n        struct {\n            unsigned int    res1    :1;\n            unsigned int    vbr     :1;\n            unsigned int    wfqf    :14;\n            unsigned int    tp      :16;\n        }               bit;\n        u32             dword;\n    };\n\n    union qsb_queue_vbr_parameter_table {\n        struct {\n            unsigned int    taus    :16;\n            unsigned int    ts      :16;\n        }               bit;\n        u32             dword;\n    };\n#else\n    union qsb_queue_parameter_table {\n        struct {\n            unsigned int    tp      :16;\n            unsigned int    wfqf    :14;\n            unsigned int    vbr     :1;\n            unsigned int    res1    :1;\n        }               bit;\n        u32             dword;\n    };\n\n    union qsb_queue_vbr_parameter_table {\n        struct {\n            unsigned int    ts      :16;\n            unsigned int    taus    :16;\n        }               bit;\n        u32             dword;\n    };\n#endif  //  defined(__BIG_ENDIAN)\n\n/*\n *  Mailbox IGU0 Registers\n */\n#define MBOX_IGU0_ISRS                  PPE_REG_ADDR(0x0200)\n#define MBOX_IGU0_ISRC                  PPE_REG_ADDR(0x0201)\n#define MBOX_IGU0_ISR                   PPE_REG_ADDR(0x0202)\n#define MBOX_IGU0_IER                   PPE_REG_ADDR(0x0203)\n\n#define MBOX_IGU0_ISRS_SET(n)           (1 << (n))\n#define MBOX_IGU0_ISRC_CLEAR(n)         (1 << (n))\n#define MBOX_IGU0_ISR_ISR(n)            (*MBOX_IGU0_ISR & (1 << (n)))\n#define MBOX_IGU0_IER_EN(n)             (*MBOX_IGU0_IER & (1 << (n)))\n#define MBOX_IGU0_IER_EN_SET(n)         (1 << (n))\n\n/*\n *  Mailbox IGU1 Registers\n */\n#define MBOX_IGU1_ISRS                  PPE_REG_ADDR(0x0204)\n#define MBOX_IGU1_ISRC                  PPE_REG_ADDR(0x0205)\n#define MBOX_IGU1_ISR                   PPE_REG_ADDR(0x0206)\n#define MBOX_IGU1_IER                   PPE_REG_ADDR(0x0207)\n\n#define MBOX_IGU1_ISRS_SET(n)           (1 << (n))\n#define MBOX_IGU1_ISRC_CLEAR(n)         (1 << (n))\n#define MBOX_IGU1_ISR_ISR(n)            (*MBOX_IGU1_ISR & (1 << (n)))\n#define MBOX_IGU1_IER_EN(n)             (*MBOX_IGU1_IER & (1 << (n)))\n#define MBOX_IGU1_IER_EN_SET(n)         (1 << (n))\n\n/*\n *  Mailbox IGU3 Registers\n */\n#define MBOX_IGU3_ISRS                  PPE_REG_ADDR(0x0214)\n#define MBOX_IGU3_ISRC                  PPE_REG_ADDR(0x0215)\n#define MBOX_IGU3_ISR                   PPE_REG_ADDR(0x0216)\n#define MBOX_IGU3_IER                   PPE_REG_ADDR(0x0217)\n\n#define MBOX_IGU3_ISRS_SET(n)           (1 << (n))\n#define MBOX_IGU3_ISRC_CLEAR(n)         (1 << (n))\n#define MBOX_IGU3_ISR_ISR(n)            (*MBOX_IGU3_ISR & (1 << (n)))\n#define MBOX_IGU3_IER_EN(n)             (*MBOX_IGU3_IER & (1 << (n)))\n#define MBOX_IGU3_IER_EN_SET(n)         (1 << (n))\n\n/*\n *  RTHA/TTHA Registers\n */\n#define RFBI_CFG                        PPE_REG_ADDR(0x0400)\n#define RBA_CFG0                        PPE_REG_ADDR(0x0404)\n#define RBA_CFG1                        PPE_REG_ADDR(0x0405)\n#define RCA_CFG0                        PPE_REG_ADDR(0x0408)\n#define RCA_CFG1                        PPE_REG_ADDR(0x0409)\n#define RDES_CFG0                       PPE_REG_ADDR(0x040C)\n#define RDES_CFG1                       PPE_REG_ADDR(0x040D)\n#define SFSM_STATE0                     PPE_REG_ADDR(0x0410)\n#define SFSM_STATE1                     PPE_REG_ADDR(0x0411)\n#define SFSM_DBA0                       PPE_REG_ADDR(0x0412)\n#define SFSM_DBA1                       PPE_REG_ADDR(0x0413)\n#define SFSM_CBA0                       PPE_REG_ADDR(0x0414)\n#define SFSM_CBA1                       PPE_REG_ADDR(0x0415)\n#define SFSM_CFG0                       PPE_REG_ADDR(0x0416)\n#define SFSM_CFG1                       PPE_REG_ADDR(0x0417)\n#define SFSM_PGCNT0                     PPE_REG_ADDR(0x041C)\n#define SFSM_PGCNT1                     PPE_REG_ADDR(0x041D)\n#define FFSM_DBA0                       PPE_REG_ADDR(0x0508)\n#define FFSM_DBA1                       PPE_REG_ADDR(0x0509)\n#define FFSM_CFG0                       PPE_REG_ADDR(0x050A)\n#define FFSM_CFG1                       PPE_REG_ADDR(0x050B)\n#define FFSM_IDLE_HEAD_BC0              PPE_REG_ADDR(0x050E)\n#define FFSM_IDLE_HEAD_BC1              PPE_REG_ADDR(0x050F)\n#define FFSM_PGCNT0                     PPE_REG_ADDR(0x0514)\n#define FFSM_PGCNT1                     PPE_REG_ADDR(0x0515)\n\n/*\n *  PPE TC Logic Registers (partial)\n */\n#define DREG_A_VERSION                  PPE_REG_ADDR(0x0D00)\n#define DREG_A_CFG                      PPE_REG_ADDR(0x0D01)\n#define DREG_AT_CTRL                    PPE_REG_ADDR(0x0D02)\n#define DREG_AT_CB_CFG0                 PPE_REG_ADDR(0x0D03)\n#define DREG_AT_CB_CFG1                 PPE_REG_ADDR(0x0D04)\n#define DREG_AR_CTRL                    PPE_REG_ADDR(0x0D08)\n#define DREG_AR_CB_CFG0                 PPE_REG_ADDR(0x0D09)\n#define DREG_AR_CB_CFG1                 PPE_REG_ADDR(0x0D0A)\n#define DREG_A_UTPCFG                   PPE_REG_ADDR(0x0D0E)\n#define DREG_A_STATUS                   PPE_REG_ADDR(0x0D0F)\n#define DREG_AT_CFG0                    PPE_REG_ADDR(0x0D20)\n#define DREG_AT_CFG1                    PPE_REG_ADDR(0x0D21)\n#define DREG_AT_FB_SIZE0                PPE_REG_ADDR(0x0D22)\n#define DREG_AT_FB_SIZE1                PPE_REG_ADDR(0x0D23)\n#define DREG_AT_CELL0                   PPE_REG_ADDR(0x0D24)\n#define DREG_AT_CELL1                   PPE_REG_ADDR(0x0D25)\n#define DREG_AT_IDLE_CNT0               PPE_REG_ADDR(0x0D26)\n#define DREG_AT_IDLE_CNT1               PPE_REG_ADDR(0x0D27)\n#define DREG_AT_IDLE0                   PPE_REG_ADDR(0x0D28)\n#define DREG_AT_IDLE1                   PPE_REG_ADDR(0x0D29)\n#define DREG_AR_CFG0                    PPE_REG_ADDR(0x0D60)\n#define DREG_AR_CFG1                    PPE_REG_ADDR(0x0D61)\n#define DREG_AR_CELL0                   PPE_REG_ADDR(0x0D68)\n#define DREG_AR_CELL1                   PPE_REG_ADDR(0x0D69)\n#define DREG_AR_IDLE_CNT0               PPE_REG_ADDR(0x0D6A)\n#define DREG_AR_IDLE_CNT1               PPE_REG_ADDR(0x0D6B)\n#define DREG_AR_AIIDLE_CNT0             PPE_REG_ADDR(0x0D6C)\n#define DREG_AR_AIIDLE_CNT1             PPE_REG_ADDR(0x0D6D)\n#define DREG_AR_BE_CNT0                 PPE_REG_ADDR(0x0D6E)\n#define DREG_AR_BE_CNT1                 PPE_REG_ADDR(0x0D6F)\n#define DREG_AR_HEC_CNT0                PPE_REG_ADDR(0x0D70)\n#define DREG_AR_HEC_CNT1                PPE_REG_ADDR(0x0D71)\n#define DREG_AR_IDLE0                   PPE_REG_ADDR(0x0D74)\n#define DREG_AR_IDLE1                   PPE_REG_ADDR(0x0D75)\n#define DREG_AR_CERRN_CNT0              PPE_REG_ADDR(0x0DA0)\n#define DREG_AR_CERRN_CNT1              PPE_REG_ADDR(0x0DA1)\n#define DREG_AR_CERRNP_CNT0             PPE_REG_ADDR(0x0DA2)\n#define DREG_AR_CERRNP_CNT1             PPE_REG_ADDR(0x0DA3)\n#define DREG_AR_CVN_CNT0                PPE_REG_ADDR(0x0DA4)\n#define DREG_AR_CVN_CNT1                PPE_REG_ADDR(0x0DA5)\n#define DREG_AR_CVNP_CNT0               PPE_REG_ADDR(0x0DA6)\n#define DREG_AR_CVNP_CNT1               PPE_REG_ADDR(0x0DA7)\n#define DREG_B0_LADR                    PPE_REG_ADDR(0x0DA8)\n#define DREG_B1_LADR                    PPE_REG_ADDR(0x0DA9)\n\nstatic inline int\nifx_drv_ver(char *buf, char *module, int major, int mid, int minor)\n{\n    return sprintf(buf, \"Lantiq %s driver, version %d.%d.%d, (c) 2001-2013 Lantiq Deutschland GmbH\\n\",\n                    module, major, mid, minor);\n}\n\n\n#endif  //  IFXMIPS_PTM_PPE_COMMON_H\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-ptm/src/ifxmips_ptm_ppe_danube.h",
    "content": "/******************************************************************************\n**\n** FILE NAME    : ifxmips_ptm_ppe_danube.h\n** PROJECT      : UEIP\n** MODULES      : PTM\n**\n** DATE         : 7 Jul 2009\n** AUTHOR       : Xu Liang\n** DESCRIPTION  : PTM driver header file (PPE register for Danube)\n** COPYRIGHT    :       Copyright (c) 2006\n**                      Infineon Technologies AG\n**                      Am Campeon 1-12, 85579 Neubiberg, Germany\n**\n**    This program is free software; you can redistribute it and/or modify\n**    it under the terms of the GNU General Public License as published by\n**    the Free Software Foundation; either version 2 of the License, or\n**    (at your option) any later version.\n**\n** HISTORY\n** $Date        $Author         $Comment\n** 07 JUL 2009  Xu Liang        Init Version\n*******************************************************************************/\n\n\n\n#ifndef IFXMIPS_PTM_PPE_DANUBE_H\n#define IFXMIPS_PTM_PPE_DANUBE_H\n\n\n\n/*\n *  FPI Configuration Bus Register and Memory Address Mapping\n */\n#define IFX_PPE                      \t(KSEG1 | 0x1E180000)\n#define PP32_DEBUG_REG_ADDR(i, x)       ((volatile unsigned int*)(IFX_PPE + (((x) + 0x0000) << 2)))\n#define PPM_INT_REG_ADDR(i, x)          ((volatile unsigned int*)(IFX_PPE + (((x) + 0x0030) << 2)))\n#define PP32_INTERNAL_RES_ADDR(i, x)    ((volatile unsigned int*)(IFX_PPE + (((x) + 0x0040) << 2)))\n#define CDM_CODE_MEMORY(i, x)           ((volatile unsigned int*)(IFX_PPE + (((x) + 0x1000) << 2)))\n#define PPE_REG_ADDR(x)                 ((volatile unsigned int*)(IFX_PPE + (((x) + 0x4000) << 2)))\n#define CDM_DATA_MEMORY(i, x)           ((volatile unsigned int*)(IFX_PPE + (((x) + 0x5000) << 2)))\n#define PPM_INT_UNIT_ADDR(x)            ((volatile unsigned int*)(IFX_PPE + (((x) + 0x6000) << 2)))\n#define PPM_TIMER0_ADDR(x)              ((volatile unsigned int*)(IFX_PPE + (((x) + 0x6100) << 2)))\n#define PPM_TASK_IND_REG_ADDR(x)        ((volatile unsigned int*)(IFX_PPE + (((x) + 0x6200) << 2)))\n#define PPS_BRK_ADDR(x)                 ((volatile unsigned int*)(IFX_PPE + (((x) + 0x6300) << 2)))\n#define PPM_TIMER1_ADDR(x)              ((volatile unsigned int*)(IFX_PPE + (((x) + 0x6400) << 2)))\n#define SB_RAM0_ADDR(x)                 ((volatile unsigned int*)(IFX_PPE + (((x) + 0x8000) << 2)))\n#define SB_RAM1_ADDR(x)                 ((volatile unsigned int*)(IFX_PPE + (((x) + 0x8400) << 2)))\n#define SB_RAM2_ADDR(x)                 ((volatile unsigned int*)(IFX_PPE + (((x) + 0x8C00) << 2)))\n#define SB_RAM3_ADDR(x)                 ((volatile unsigned int*)(IFX_PPE + (((x) + 0x9600) << 2)))\n#define QSB_CONF_REG_ADDR(x)            ((volatile unsigned int*)(IFX_PPE + (((x) + 0xC000) << 2)))\n\n/*\n *  DWORD-Length of Memory Blocks\n */\n#define PP32_DEBUG_REG_DWLEN            0x0030\n#define PPM_INT_REG_DWLEN               0x0010\n#define PP32_INTERNAL_RES_DWLEN         0x00C0\n#define CDM_CODE_MEMORYn_DWLEN(n)       ((n) == 0 ? 0x1000 : 0x0800)\n#define PPE_REG_DWLEN                   0x1000\n#define CDM_DATA_MEMORY_DWLEN           CDM_CODE_MEMORYn_DWLEN(1)\n#define PPM_INT_UNIT_DWLEN              0x0100\n#define PPM_TIMER0_DWLEN                0x0100\n#define PPM_TASK_IND_REG_DWLEN          0x0100\n#define PPS_BRK_DWLEN                   0x0100\n#define PPM_TIMER1_DWLEN                0x0100\n#define SB_RAM0_DWLEN                   0x0400\n#define SB_RAM1_DWLEN                   0x0800\n#define SB_RAM2_DWLEN                   0x0A00\n#define SB_RAM3_DWLEN                   0x0400\n#define QSB_CONF_REG_DWLEN              0x0100\n\n/*\n *  PP32 to FPI Address Mapping\n */\n#define SB_BUFFER(__sb_addr)            ((volatile unsigned int *)((((__sb_addr) >= 0x2000) && ((__sb_addr) <= 0x23FF)) ? SB_RAM0_ADDR((__sb_addr) - 0x2000) :   \\\n                                                                   (((__sb_addr) >= 0x2400) && ((__sb_addr) <= 0x2BFF)) ? SB_RAM1_ADDR((__sb_addr) - 0x2400) :   \\\n                                                                   (((__sb_addr) >= 0x2C00) && ((__sb_addr) <= 0x35FF)) ? SB_RAM2_ADDR((__sb_addr) - 0x2C00) :   \\\n                                                                   (((__sb_addr) >= 0x3600) && ((__sb_addr) <= 0x39FF)) ? SB_RAM3_ADDR((__sb_addr) - 0x3600) :   \\\n                                                                0))\n\n/*\n *  PP32 Debug Control Register\n */\n#define PP32_DBG_CTRL                   PP32_DEBUG_REG_ADDR(0, 0x0000)\n\n#define DBG_CTRL_START_SET(value)       ((value) ? (1 << 0) : 0)\n#define DBG_CTRL_STOP_SET(value)        ((value) ? (1 << 1) : 0)\n#define DBG_CTRL_STEP_SET(value)        ((value) ? (1 << 2) : 0)\n\n#define PP32_HALT_STAT                  PP32_DEBUG_REG_ADDR(0, 0x0001)\n\n#define PP32_BRK_SRC                    PP32_DEBUG_REG_ADDR(0, 0x0002)\n  #define PP32_BRK_SRC_PC(i)            (1 << (i))\n  #define PP32_BRK_SRC_DATA(i, cmd)     ((cmd) << ((i) * 3 + 8))\n\n#define PP32_DBG_PC_MIN(i)              PP32_DEBUG_REG_ADDR(0, 0x0010 + (i))\n#define PP32_DBG_PC_MAX(i)              PP32_DEBUG_REG_ADDR(0, 0x0014 + (i))\n#define PP32_DBG_DATA_MIN(i)            PP32_DEBUG_REG_ADDR(0, 0x0018 + (i))\n#define PP32_DBG_DATA_MAX(i)            PP32_DEBUG_REG_ADDR(0, 0x001A + (i))\n#define PP32_DBG_DATA_VAL(i)            PP32_DEBUG_REG_ADDR(0, 0x001C + (i))\n\n#define PP32_DBG_TASK_GPR(task, i)      PP32_DEBUG_REG_ADDR(0, 0x0040 + (task) * 0x0010 + (i))\n\n#define PP32_DBG_CUR_PC                 PP32_DEBUG_REG_ADDR(0, 0x0080)\n#define PP32_DBG_TASK_NO                PP32_DEBUG_REG_ADDR(0, 0x0081)\n#define PP32_DBG_TASK_PRIO              PP32_DEBUG_REG_ADDR(0, 0x0086)\n#define PP32_DBG_PC_OF_TASK(i)          PP32_DEBUG_REG_ADDR(0, 0x0087 + (i))\n\n/*\n *  Share Buffer Registers\n */\n#define SB_MST_SEL                      PPE_REG_ADDR(0x0304)\n\n/*\n *  EMA Registers\n */\n#define EMA_CMDCFG                      PPE_REG_ADDR(0x0A00)\n#define EMA_DATACFG                     PPE_REG_ADDR(0x0A01)\n#define EMA_CMDCNT                      PPE_REG_ADDR(0x0A02)\n#define EMA_DATACNT                     PPE_REG_ADDR(0x0A03)\n#define EMA_ISR                         PPE_REG_ADDR(0x0A04)\n#define EMA_IER                         PPE_REG_ADDR(0x0A05)\n#define EMA_CFG                         PPE_REG_ADDR(0x0A06)\n#define EMA_SUBID                       PPE_REG_ADDR(0x0A07)\n\n#define EMA_ALIGNMENT                   4\n\n/*\n *  Mailbox IGU1 Interrupt\n */\n#define PPE_MAILBOX_IGU1_INT            INT_NUM_IM2_IRL24\n\n\n\n#endif  //  IFXMIPS_PTM_PPE_DANUBE_H\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-ptm/src/ifxmips_ptm_ppe_vr9.h",
    "content": "/******************************************************************************\n**\n** FILE NAME    : ifxmips_ptm_ppe_vr9.h\n** PROJECT      : UEIP\n** MODULES      : PTM\n**\n** DATE         : 7 Jul 2009\n** AUTHOR       : Xu Liang\n** DESCRIPTION  : PTM driver header file (PPE register for VR9)\n** COPYRIGHT    :       Copyright (c) 2006\n**                      Infineon Technologies AG\n**                      Am Campeon 1-12, 85579 Neubiberg, Germany\n**\n**    This program is free software; you can redistribute it and/or modify\n**    it under the terms of the GNU General Public License as published by\n**    the Free Software Foundation; either version 2 of the License, or\n**    (at your option) any later version.\n**\n** HISTORY\n** $Date        $Author         $Comment\n** 07 JUL 2009  Xu Liang        Init Version\n*******************************************************************************/\n\n\n\n#ifndef IFXMIPS_PTM_PPE_VR9_H\n#define IFXMIPS_PTM_PPE_VR9_H\n\n\n\n/*\n *  FPI Configuration Bus Register and Memory Address Mapping\n */\n#define IFX_PPE                         (KSEG1 | 0x1E200000)\n#define PP32_DEBUG_REG_ADDR(i, x)       ((volatile unsigned int*)(IFX_PPE + (((x) + 0x000000 + (i) * 0x00010000) << 2)))\n#define CDM_CODE_MEMORY(i, x)           ((volatile unsigned int*)(IFX_PPE + (((x) + 0x001000 + (i) * 0x00010000) << 2)))\n#define CDM_DATA_MEMORY(i, x)           ((volatile unsigned int*)(IFX_PPE + (((x) + 0x004000 + (i) * 0x00010000) << 2)))\n#define SB_RAM0_ADDR(x)                 ((volatile unsigned int*)(IFX_PPE + (((x) + 0x008000) << 2)))\n#define SB_RAM1_ADDR(x)                 ((volatile unsigned int*)(IFX_PPE + (((x) + 0x009000) << 2)))\n#define SB_RAM2_ADDR(x)                 ((volatile unsigned int*)(IFX_PPE + (((x) + 0x00A000) << 2)))\n#define SB_RAM3_ADDR(x)                 ((volatile unsigned int*)(IFX_PPE + (((x) + 0x00B000) << 2)))\n#define PPE_REG_ADDR(x)                 ((volatile unsigned int*)(IFX_PPE + (((x) + 0x00D000) << 2)))\n#define QSB_CONF_REG_ADDR(x)            ((volatile unsigned int*)(IFX_PPE + (((x) + 0x00E000) << 2)))\n#define SB_RAM6_ADDR(x)                 ((volatile unsigned int*)(IFX_PPE + (((x) + 0x018000) << 2)))\n\n/*\n *  DWORD-Length of Memory Blocks\n */\n#define PP32_DEBUG_REG_DWLEN            0x0030\n#define CDM_CODE_MEMORYn_DWLEN(n)       ((n) == 0 ? 0x1000 : 0x0800)\n#define CDM_DATA_MEMORY_DWLEN           CDM_CODE_MEMORYn_DWLEN(1)\n#define SB_RAM0_DWLEN                   0x1000\n#define SB_RAM1_DWLEN                   0x1000\n#define SB_RAM2_DWLEN                   0x1000\n#define SB_RAM3_DWLEN                   0x1000\n#define SB_RAM6_DWLEN                   0x8000\n#define QSB_CONF_REG_DWLEN              0x0100\n\n/*\n *  PP32 to FPI Address Mapping\n */\n#define SB_BUFFER(__sb_addr)            ((volatile unsigned int *)((((__sb_addr) >= 0x0000) && ((__sb_addr) <= 0x1FFF)) ? PPE_REG_ADDR((__sb_addr)) :           \\\n                                                                   (((__sb_addr) >= 0x2000) && ((__sb_addr) <= 0x2FFF)) ? SB_RAM0_ADDR((__sb_addr) - 0x2000) :  \\\n                                                                   (((__sb_addr) >= 0x3000) && ((__sb_addr) <= 0x3FFF)) ? SB_RAM1_ADDR((__sb_addr) - 0x3000) :  \\\n                                                                   (((__sb_addr) >= 0x4000) && ((__sb_addr) <= 0x4FFF)) ? SB_RAM2_ADDR((__sb_addr) - 0x4000) :  \\\n                                                                   (((__sb_addr) >= 0x5000) && ((__sb_addr) <= 0x5FFF)) ? SB_RAM3_ADDR((__sb_addr) - 0x5000) :  \\\n                                                                   (((__sb_addr) >= 0x7000) && ((__sb_addr) <= 0x7FFF)) ? PPE_REG_ADDR((__sb_addr) - 0x7000) :  \\\n                                                                   (((__sb_addr) >= 0x8000) && ((__sb_addr) <= 0xFFFF)) ? SB_RAM6_ADDR((__sb_addr) - 0x8000) :  \\\n                                                                0))\n\n/*\n *  PP32 Debug Control Register\n */\n#define NUM_OF_PP32                             2\n\n#define PP32_FREEZE                             PPE_REG_ADDR(0x0000)\n#define PP32_SRST                               PPE_REG_ADDR(0x0020)\n\n#define PP32_DBG_CTRL(n)                        PP32_DEBUG_REG_ADDR(n, 0x0000)\n\n#define DBG_CTRL_RESTART                        0\n#define DBG_CTRL_STOP                           1\n\n#define PP32_CTRL_CMD(n)                        PP32_DEBUG_REG_ADDR(n, 0x0B00)\n  #define PP32_CTRL_CMD_RESTART                 (1 << 0)\n  #define PP32_CTRL_CMD_STOP                    (1 << 1)\n  #define PP32_CTRL_CMD_STEP                    (1 << 2)\n  #define PP32_CTRL_CMD_BREAKOUT                (1 << 3)\n\n#define PP32_CTRL_OPT(n)                        PP32_DEBUG_REG_ADDR(n, 0x0C00)\n  #define PP32_CTRL_OPT_BREAKOUT_ON_STOP_ON     (3 << 0)\n  #define PP32_CTRL_OPT_BREAKOUT_ON_STOP_OFF    (2 << 0)\n  #define PP32_CTRL_OPT_BREAKOUT_ON_BREAKIN_ON  (3 << 2)\n  #define PP32_CTRL_OPT_BREAKOUT_ON_BREAKIN_OFF (2 << 2)\n  #define PP32_CTRL_OPT_STOP_ON_BREAKIN_ON      (3 << 4)\n  #define PP32_CTRL_OPT_STOP_ON_BREAKIN_OFF     (2 << 4)\n  #define PP32_CTRL_OPT_STOP_ON_BREAKPOINT_ON   (3 << 6)\n  #define PP32_CTRL_OPT_STOP_ON_BREAKPOINT_OFF  (2 << 6)\n  #define PP32_CTRL_OPT_BREAKOUT_ON_STOP(n)     (*PP32_CTRL_OPT(n) & (1 << 0))\n  #define PP32_CTRL_OPT_BREAKOUT_ON_BREAKIN(n)  (*PP32_CTRL_OPT(n) & (1 << 2))\n  #define PP32_CTRL_OPT_STOP_ON_BREAKIN(n)      (*PP32_CTRL_OPT(n) & (1 << 4))\n  #define PP32_CTRL_OPT_STOP_ON_BREAKPOINT(n)   (*PP32_CTRL_OPT(n) & (1 << 6))\n\n#define PP32_BRK_PC(n, i)                       PP32_DEBUG_REG_ADDR(n, 0x0900 + (i) * 2)\n#define PP32_BRK_PC_MASK(n, i)                  PP32_DEBUG_REG_ADDR(n, 0x0901 + (i) * 2)\n#define PP32_BRK_DATA_ADDR(n, i)                PP32_DEBUG_REG_ADDR(n, 0x0904 + (i) * 2)\n#define PP32_BRK_DATA_ADDR_MASK(n, i)           PP32_DEBUG_REG_ADDR(n, 0x0905 + (i) * 2)\n#define PP32_BRK_DATA_VALUE_RD(n, i)            PP32_DEBUG_REG_ADDR(n, 0x0908 + (i) * 2)\n#define PP32_BRK_DATA_VALUE_RD_MASK(n, i)       PP32_DEBUG_REG_ADDR(n, 0x0909 + (i) * 2)\n#define PP32_BRK_DATA_VALUE_WR(n, i)            PP32_DEBUG_REG_ADDR(n, 0x090C + (i) * 2)\n#define PP32_BRK_DATA_VALUE_WR_MASK(n, i)       PP32_DEBUG_REG_ADDR(n, 0x090D + (i) * 2)\n  #define PP32_BRK_CONTEXT_MASK(i)              (1 << (i))\n  #define PP32_BRK_CONTEXT_MASK_EN              (1 << 4)\n  #define PP32_BRK_COMPARE_GREATER_EQUAL        (1 << 5)    //  valid for break data value rd/wr only\n  #define PP32_BRK_COMPARE_LOWER_EQUAL          (1 << 6)\n  #define PP32_BRK_COMPARE_EN                   (1 << 7)\n\n#define PP32_BRK_TRIG(n)                        PP32_DEBUG_REG_ADDR(n, 0x0F00)\n  #define PP32_BRK_GRPi_PCn_ON(i, n)            ((3 << ((n) * 2)) << ((i) * 16))\n  #define PP32_BRK_GRPi_PCn_OFF(i, n)           ((2 << ((n) * 2)) << ((i) * 16))\n  #define PP32_BRK_GRPi_DATA_ADDRn_ON(i, n)     ((3 << ((n) * 2 + 4)) << ((i) * 16))\n  #define PP32_BRK_GRPi_DATA_ADDRn_OFF(i, n)    ((2 << ((n) * 2 + 4)) << ((i) * 16))\n  #define PP32_BRK_GRPi_DATA_VALUE_RDn_ON(i, n) ((3 << ((n) * 2 + 8)) << ((i) * 16))\n  #define PP32_BRK_GRPi_DATA_VALUE_RDn_OFF(i, n)((2 << ((n) * 2 + 8)) << ((i) * 16))\n  #define PP32_BRK_GRPi_DATA_VALUE_WRn_ON(i, n) ((3 << ((n) * 2 + 12)) << ((i) * 16))\n  #define PP32_BRK_GRPi_DATA_VALUE_WRn_OFF(i, n)((2 << ((n) * 2 + 12)) << ((i) * 16))\n  #define PP32_BRK_GRPi_PCn(k, i, n)            (*PP32_BRK_TRIG(k) & ((1 << ((n))) << ((i) * 8)))\n  #define PP32_BRK_GRPi_DATA_ADDRn(k, i, n)     (*PP32_BRK_TRIG(k) & ((1 << ((n) + 2)) << ((i) * 8)))\n  #define PP32_BRK_GRPi_DATA_VALUE_RDn(k, i, n) (*PP32_BRK_TRIG(k) & ((1 << ((n) + 4)) << ((i) * 8)))\n  #define PP32_BRK_GRPi_DATA_VALUE_WRn(k, i, n) (*PP32_BRK_TRIG(k) & ((1 << ((n) + 6)) << ((i) * 8)))\n\n#define PP32_CPU_STATUS(n)                      PP32_DEBUG_REG_ADDR(n, 0x0D00)\n#define PP32_HALT_STAT(n)                       PP32_CPU_STATUS(n)\n#define PP32_DBG_CUR_PC(n)                      PP32_CPU_STATUS(n)\n  #define PP32_CPU_USER_STOPPED(n)              (*PP32_CPU_STATUS(n) & (1 << 0))\n  #define PP32_CPU_USER_BREAKIN_RCV(n)          (*PP32_CPU_STATUS(n) & (1 << 1))\n  #define PP32_CPU_USER_BREAKPOINT_MET(n)       (*PP32_CPU_STATUS(n) & (1 << 2))\n  #define PP32_CPU_CUR_PC(n)                    (*PP32_CPU_STATUS(n) >> 16)\n\n#define PP32_BREAKPOINT_REASONS(n)              PP32_DEBUG_REG_ADDR(n, 0x0A00)\n  #define PP32_BRK_PC_MET(n, i)                 (*PP32_BREAKPOINT_REASONS(n) & (1 << (i)))\n  #define PP32_BRK_DATA_ADDR_MET(n, i)          (*PP32_BREAKPOINT_REASONS(n) & (1 << ((i) + 2)))\n  #define PP32_BRK_DATA_VALUE_RD_MET(n, i)      (*PP32_BREAKPOINT_REASONS(n) & (1 << ((i) + 4)))\n  #define PP32_BRK_DATA_VALUE_WR_MET(n, i)      (*PP32_BREAKPOINT_REASONS(n) & (1 << ((i) + 6)))\n  #define PP32_BRK_DATA_VALUE_RD_LO_EQ(n, i)    (*PP32_BREAKPOINT_REASONS(n) & (1 << ((i) * 2 + 8)))\n  #define PP32_BRK_DATA_VALUE_RD_GT_EQ(n, i)    (*PP32_BREAKPOINT_REASONS(n) & (1 << ((i) * 2 + 9)))\n  #define PP32_BRK_DATA_VALUE_WR_LO_EQ(n, i)    (*PP32_BREAKPOINT_REASONS(n) & (1 << ((i) * 2 + 12)))\n  #define PP32_BRK_DATA_VALUE_WR_GT_EQ(n, i)    (*PP32_BREAKPOINT_REASONS(n) & (1 << ((i) * 2 + 13)))\n  #define PP32_BRK_CUR_CONTEXT(n)               ((*PP32_BREAKPOINT_REASONS(n) >> 16) & 0x03)\n\n#define PP32_GP_REG_BASE(n)                     PP32_DEBUG_REG_ADDR(n, 0x0E00)\n#define PP32_GP_CONTEXTi_REGn(n, i, j)          PP32_DEBUG_REG_ADDR(n, 0x0E00 + (i) * 16 + (j))\n\n/*\n *  SAR Registers\n */\n#define SAR_MODE_CFG                    PPE_REG_ADDR(0x080A)\n#define SAR_RX_CMD_CNT                  PPE_REG_ADDR(0x080B)\n#define SAR_TX_CMD_CNT                  PPE_REG_ADDR(0x080C)\n#define SAR_RX_CTX_CFG                  PPE_REG_ADDR(0x080D)\n#define SAR_TX_CTX_CFG                  PPE_REG_ADDR(0x080E)\n#define SAR_TX_CMD_DONE_CNT             PPE_REG_ADDR(0x080F)\n#define SAR_POLY_CFG_SET0               PPE_REG_ADDR(0x0812)\n#define SAR_POLY_CFG_SET1               PPE_REG_ADDR(0x0813)\n#define SAR_POLY_CFG_SET2               PPE_REG_ADDR(0x0814)\n#define SAR_POLY_CFG_SET3               PPE_REG_ADDR(0x0815)\n#define SAR_CRC_SIZE_CFG                PPE_REG_ADDR(0x0816)\n\n/*\n *  PDMA/EMA Registers\n */\n#define PDMA_CFG                        PPE_REG_ADDR(0x0A00)\n#define PDMA_RX_CMDCNT                  PPE_REG_ADDR(0x0A01)\n#define PDMA_TX_CMDCNT                  PPE_REG_ADDR(0x0A02)\n#define PDMA_RX_FWDATACNT               PPE_REG_ADDR(0x0A03)\n#define PDMA_TX_FWDATACNT               PPE_REG_ADDR(0x0A04)\n#define PDMA_RX_CTX_CFG                 PPE_REG_ADDR(0x0A05)\n#define PDMA_TX_CTX_CFG                 PPE_REG_ADDR(0x0A06)\n#define PDMA_RX_MAX_LEN_REG             PPE_REG_ADDR(0x0A07)\n#define PDMA_RX_DELAY_CFG               PPE_REG_ADDR(0x0A08)\n#define PDMA_INT_FIFO_RD                PPE_REG_ADDR(0x0A09)\n#define PDMA_ISR                        PPE_REG_ADDR(0x0A0A)\n#define PDMA_IER                        PPE_REG_ADDR(0x0A0B)\n#define PDMA_SUBID                      PPE_REG_ADDR(0x0A0C)\n#define PDMA_BAR0                       PPE_REG_ADDR(0x0A0D)\n#define PDMA_BAR1                       PPE_REG_ADDR(0x0A0E)\n\n#define SAR_PDMA_RX_CMDBUF_CFG          PPE_REG_ADDR(0x0F00)\n#define SAR_PDMA_TX_CMDBUF_CFG          PPE_REG_ADDR(0x0F01)\n#define SAR_PDMA_RX_FW_CMDBUF_CFG       PPE_REG_ADDR(0x0F02)\n#define SAR_PDMA_TX_FW_CMDBUF_CFG       PPE_REG_ADDR(0x0F03)\n#define SAR_PDMA_RX_CMDBUF_STATUS       PPE_REG_ADDR(0x0F04)\n#define SAR_PDMA_TX_CMDBUF_STATUS       PPE_REG_ADDR(0x0F05)\n\n#define PDMA_ALIGNMENT                  32              //  same as Central DMA because of descriptor swap\n#define EMA_ALIGNMENT                   PDMA_ALIGNMENT\n\n/*\n *  Mailbox IGU1 Interrupt\n */\n#define PPE_MAILBOX_IGU1_INT            INT_NUM_IM2_IRL24\n\n\n\n#endif  //  IFXMIPS_PTM_PPE_VR9_H\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-ptm/src/ifxmips_ptm_test.c",
    "content": "/******************************************************************************\n**\n** FILE NAME    : ifxmips_ptm_vdsl.c\n** PROJECT      : UEIP\n** MODULES      : PTM\n**\n** DATE         : 7 Jul 2009\n** AUTHOR       : Xu Liang\n** DESCRIPTION  : PTM driver common source file (core functions for VR9)\n** COPYRIGHT    :       Copyright (c) 2006\n**                      Infineon Technologies AG\n**                      Am Campeon 1-12, 85579 Neubiberg, Germany\n**\n**    This program is free software; you can redistribute it and/or modify\n**    it under the terms of the GNU General Public License as published by\n**    the Free Software Foundation; either version 2 of the License, or\n**    (at your option) any later version.\n**\n** HISTORY\n** $Date        $Author         $Comment\n** 07 JUL 2009  Xu Liang        Init Version\n*******************************************************************************/\n\n\n\n#ifdef CONFIG_IFX_PTM_TEST_PROC\n\n/*\n * ####################################\n *              Head File\n * ####################################\n */\n\n/*\n *  Common Head File\n */\n#include <linux/kernel.h>\n#include <linux/module.h>\n#include <linux/version.h>\n#include <linux/types.h>\n#include <linux/errno.h>\n#include <linux/proc_fs.h>\n#include <linux/init.h>\n#include <linux/ioctl.h>\n#include <linux/etherdevice.h>\n\n/*\n *  Chip Specific Head File\n */\n#include <asm/ifx/ifx_types.h>\n#include <asm/ifx/ifx_regs.h>\n#include <asm/ifx/common_routines.h>\n#include \"ifxmips_ptm_common.h\"\n#include \"ifxmips_ptm_ppe_common.h\"\n\n\n\n/*\n * ####################################\n *              Definition\n * ####################################\n */\n\n\n\n/*\n * ####################################\n *             Declaration\n * ####################################\n */\n\n/*\n *  Proc File Functions\n */\nstatic inline void proc_file_create(void);\nstatic inline void proc_file_delete(void);\n\n/*\n *  Proc Help Functions\n */\nstatic int proc_write_mem(struct file *, const char *, unsigned long, void *);\nstatic int proc_read_pp32(char *, char **, off_t, int, int *, void *);\nstatic int proc_write_pp32(struct file *, const char *, unsigned long, void *);\nstatic int stricmp(const char *, const char *);\nstatic int strincmp(const char *, const char *, int);\nstatic int get_token(char **, char **, int *, int *);\nstatic int get_number(char **, int *, int);\nstatic inline void ignore_space(char **, int *);\n\n\n\n/*\n * ####################################\n *            Local Variable\n * ####################################\n */\n\n\n\n/*\n * ####################################\n *            Local Function\n * ####################################\n */\n\nstatic inline void proc_file_create(void)\n{\n    struct proc_dir_entry *res;\n\n    res = create_proc_entry(\"driver/ifx_ptm/mem\",\n                            0,\n                            NULL);\n    if ( res != NULL )\n        res->write_proc = proc_write_mem;\n    else\n        printk(\"%s:%s:%d: failed to create proc mem!\", __FILE__, __func__, __LINE__);\n\n    res = create_proc_entry(\"driver/ifx_ptm/pp32\",\n                            0,\n                            NULL);\n    if ( res != NULL ) {\n        res->read_proc = proc_read_pp32;\n        res->write_proc = proc_write_pp32;\n    }\n    else\n        printk(\"%s:%s:%d: failed to create proc pp32!\", __FILE__, __func__, __LINE__);\n}\n\nstatic inline void proc_file_delete(void)\n{\n    remove_proc_entry(\"driver/ifx_ptm/pp32\", NULL);\n\n    remove_proc_entry(\"driver/ifx_ptm/mem\", NULL);\n}\n\nstatic inline unsigned long sb_addr_to_fpi_addr_convert(unsigned long sb_addr)\n{\n#define PP32_SB_ADDR_END        0xFFFF\n\n    if ( sb_addr < PP32_SB_ADDR_END) {\n        return (unsigned long ) SB_BUFFER(sb_addr);\n    }\n    else {\n        return sb_addr;\n    }\n}\n\nstatic int proc_write_mem(struct file *file, const char *buf, unsigned long count, void *data)\n{\n    char *p1, *p2;\n    int len;\n    int colon;\n    unsigned long *p;\n    char local_buf[1024];\n    int i, n, l;\n\n    len = sizeof(local_buf) < count ? sizeof(local_buf) - 1 : count;\n    len = len - copy_from_user(local_buf, buf, len);\n    local_buf[len] = 0;\n\n    p1 = local_buf;\n    colon = 1;\n    while ( get_token(&p1, &p2, &len, &colon) )\n    {\n        if ( stricmp(p1, \"w\") == 0 || stricmp(p1, \"write\") == 0 || stricmp(p1, \"r\") == 0 || stricmp(p1, \"read\") == 0 )\n            break;\n\n        p1 = p2;\n        colon = 1;\n    }\n\n    if ( *p1 == 'w' )\n    {\n        ignore_space(&p2, &len);\n        p = (unsigned long *)get_number(&p2, &len, 1);\n        p = (unsigned long *)sb_addr_to_fpi_addr_convert( (unsigned long) p);\n\n        if ( (u32)p >= KSEG0 )\n            while ( 1 )\n            {\n                ignore_space(&p2, &len);\n                if ( !len || !((*p2 >= '0' && *p2 <= '9') || (*p2 >= 'a' && *p2 <= 'f') || (*p2 >= 'A' && *p2 <= 'F')) )\n                    break;\n\n                *p++ = (u32)get_number(&p2, &len, 1);\n            }\n    }\n    else if ( *p1 == 'r' )\n    {\n        ignore_space(&p2, &len);\n        p = (unsigned long *)get_number(&p2, &len, 1);\n        p = (unsigned long *)sb_addr_to_fpi_addr_convert( (unsigned long) p);\n\n        if ( (u32)p >= KSEG0 )\n        {\n            ignore_space(&p2, &len);\n            n = (int)get_number(&p2, &len, 0);\n            if ( n )\n            {\n                char str[32] = {0};\n                char *pch = str;\n                int k;\n                u32 data;\n                char c;\n\n                n += (l = ((int)p >> 2) & 0x03);\n                p = (unsigned long *)((u32)p & ~0x0F);\n                for ( i = 0; i < n; i++ )\n                {\n                    if ( (i & 0x03) == 0 )\n                    {\n                        printk(\"%08X:\", (u32)p);\n                        pch = str;\n                    }\n                    if ( i < l )\n                    {\n                        printk(\"         \");\n                        sprintf(pch, \"    \");\n                    }\n                    else\n                    {\n                        data = (u32)*p;\n                        printk(\" %08X\", data);\n                        for ( k = 0; k < 4; k++ )\n                        {\n                            c = ((char*)&data)[k];\n                            pch[k] = c < ' ' ? '.' : c;\n                        }\n                    }\n                    p++;\n                    pch += 4;\n                    if ( (i & 0x03) == 0x03 )\n                    {\n                        pch[0] = 0;\n                        printk(\" ; %s\\n\", str);\n                    }\n                }\n                if ( (n & 0x03) != 0x00 )\n                {\n                    for ( k = 4 - (n & 0x03); k > 0; k-- )\n                        printk(\"         \");\n                    pch[0] = 0;\n                    printk(\" ; %s\\n\", str);\n                }\n            }\n        }\n    }\n\n    return count;\n}\n\n#ifdef CONFIG_DANUBE\n\nstatic int proc_read_pp32(char *page, char **start, off_t off, int count, int *eof, void *data)\n{\n    static const char *halt_stat[] = {\n        \"reset\",\n        \"break in line\",\n        \"stop\",\n        \"step\",\n        \"code\",\n        \"data0\",\n        \"data1\"\n    };\n    static const char *brk_src_data[] = {\n        \"off\",\n        \"read\",\n        \"write\",\n        \"read/write\",\n        \"write_equal\",\n        \"N/A\",\n        \"N/A\",\n        \"N/A\"\n    };\n    static const char *brk_src_code[] = {\n        \"off\",\n        \"on\"\n    };\n\n    int len = 0;\n    int cur_task;\n    int i, j;\n    int k;\n    unsigned long bit;\n\n    len += sprintf(page + off + len, \"Task No %d, PC %04x\\n\", *PP32_DBG_TASK_NO & 0x03, *PP32_DBG_CUR_PC & 0xFFFF);\n\n    if ( !(*PP32_HALT_STAT & 0x01) )\n        len += sprintf(page + off + len, \"  Halt State: Running\\n\");\n    else\n    {\n        len += sprintf(page + off + len, \"  Halt State: Stopped\");\n        k = 0;\n        for ( bit = 2, i = 0; bit <= (1 << 7); bit <<= 1, i++ )\n            if ( (*PP32_HALT_STAT & bit) )\n            {\n                if ( !k )\n                {\n                    len += sprintf(page + off + len, \", \");\n                    k++;\n                }\n                else\n                    len += sprintf(page + off + len, \" | \");\n                len += sprintf(page + off + len, halt_stat[i]);\n            }\n\n        len += sprintf(page + off + len, \"\\n\");\n\n        cur_task = *PP32_DBG_TASK_NO & 0x03;\n        len += sprintf(page + off + len, \"General Purpose Register (Task %d):\\n\", cur_task);\n        for ( i = 0; i < 4; i++ )\n        {\n            for ( j = 0; j < 4; j++ )\n                len += sprintf(page + off + len, \"   %2d: %08x\", i + j * 4, *PP32_DBG_TASK_GPR(cur_task, i + j * 4));\n            len += sprintf(page + off + len, \"\\n\");\n        }\n    }\n\n    len += sprintf(page + off + len, \"  Break Src:  data1 - %s, data0 - %s, pc3 - %s, pc2 - %s, pc1 - %s, pc0 - %s\\n\",\n                                                    brk_src_data[(*PP32_BRK_SRC >> 11) & 0x07], brk_src_data[(*PP32_BRK_SRC >> 8) & 0x07], brk_src_code[(*PP32_BRK_SRC >> 3) & 0x01], brk_src_code[(*PP32_BRK_SRC >> 2) & 0x01], brk_src_code[(*PP32_BRK_SRC >> 1) & 0x01], brk_src_code[*PP32_BRK_SRC & 0x01]);\n\n    for ( i = 0; i < 4; i++ )\n        len += sprintf(page + off + len, \"    pc%d:      %04x - %04x\\n\", i, *PP32_DBG_PC_MIN(i), *PP32_DBG_PC_MAX(i));\n\n    for ( i = 0; i < 2; i++ )\n        len += sprintf(page + off + len, \"    data%d:    %04x - %04x (%08x)\\n\", i, *PP32_DBG_DATA_MIN(i), *PP32_DBG_DATA_MAX(i), *PP32_DBG_DATA_VAL(i));\n\n    *eof = 1;\n\n    return len;\n}\n\nstatic int proc_write_pp32(struct file *file, const char *buf, unsigned long count, void *data)\n{\n    char str[2048];\n    char *p;\n    int len, rlen;\n\n    int id;\n    u32 addr;\n    u32 cmd;\n\n    len = count < sizeof(str) ? count : sizeof(str) - 1;\n    rlen = len - copy_from_user(str, buf, len);\n    while ( rlen && str[rlen - 1] <= ' ' )\n        rlen--;\n    str[rlen] = 0;\n    for ( p = str; *p && *p <= ' '; p++, rlen-- );\n    if ( !*p )\n    {\n        return 0;\n    }\n\n    if ( stricmp(str, \"start\") == 0 )\n        *PP32_DBG_CTRL = DBG_CTRL_START_SET(1);\n    else if ( stricmp(str, \"stop\") == 0 )\n        *PP32_DBG_CTRL = DBG_CTRL_STOP_SET(1);\n    else if ( stricmp(str, \"step\") == 0 )\n        *PP32_DBG_CTRL = DBG_CTRL_STEP_SET(1);\n    else if ( strincmp(p, \"pc\", 2) == 0 && p[2] >= '0' && p[2] <= '3' && p[3] == ' ' )\n    {\n        id = (int)(p[2] - '0');\n        p += 4;\n        rlen -= 4;\n        *PP32_BRK_SRC &= ~PP32_BRK_SRC_PC(id);\n        if ( stricmp(p, \"off\") != 0 )\n        {\n            ignore_space(&p, &rlen);\n            *PP32_DBG_PC_MIN(id) = *PP32_DBG_PC_MAX(id) = get_number(&p, &rlen, 1);\n            ignore_space(&p, &rlen);\n            if ( rlen > 0 )\n            {\n                addr = get_number(&p, &rlen, 1);\n                if ( addr >= *PP32_DBG_PC_MIN(id) )\n                    *PP32_DBG_PC_MAX(id) = addr;\n                else\n                    *PP32_DBG_PC_MIN(id) = addr;\n            }\n            *PP32_BRK_SRC |= PP32_BRK_SRC_PC(id);\n        }\n    }\n    else if ( strincmp(p, \"daddr\", 5) == 0 && p[5] >= '0' && p[5] <= '1' && p[6] == ' ' )\n    {\n        id = (int)(p[5] - '0');\n        p += 7;\n        rlen -= 7;\n        *PP32_BRK_SRC &= ~PP32_BRK_SRC_DATA(id, 7);\n        if ( stricmp(p, \"off\") != 0 )\n        {\n            ignore_space(&p, &rlen);\n            *PP32_DBG_DATA_MIN(id) = *PP32_DBG_DATA_MAX(id) = get_number(&p, &rlen, 1);\n            cmd = 1;\n            ignore_space(&p, &rlen);\n            if ( rlen > 0 && ((*p >= '0' && *p <= '9') || (*p >= 'a' && *p <= 'f') || (*p >= 'A' && *p <= 'F')) )\n            {\n                addr = get_number(&p, &rlen, 1);\n                if ( addr >= *PP32_DBG_PC_MIN(id) )\n                    *PP32_DBG_DATA_MAX(id) = addr;\n                else\n                    *PP32_DBG_DATA_MIN(id) = addr;\n                ignore_space(&p, &rlen);\n            }\n            if ( *p == 'w' )\n                cmd = 2;\n            else if ( *p == 'r' && p[1] == 'w' )\n            {\n                cmd = 3;\n                p++;\n                rlen--;\n            }\n            p++;\n            rlen--;\n            if ( rlen > 0 )\n            {\n                ignore_space(&p, &rlen);\n                if ( (*p >= '0' && *p <= '9') || (*p >= 'a' && *p <= 'f') || (*p >= 'A' && *p <= 'F'))\n                {\n                    *PP32_DBG_DATA_VAL(id) = get_number(&p, &rlen, 1);\n                    cmd = 4;\n                }\n            }\n            *PP32_BRK_SRC |= PP32_BRK_SRC_DATA(id, cmd);\n        }\n    }\n    else\n    {\n        printk(\"echo \\\"<command>\\\" > /proc/driver/ifx_ptm/pp32\\n\");\n        printk(\"  command:\\n\");\n        printk(\"    start - run pp32\\n\");\n        printk(\"    stop  - stop pp32\\n\");\n        printk(\"    step  - run pp32 with one step only\\n\");\n        printk(\"    pc0    - pc0 <addr_min [addr_max]>/off, set break point PC0\\n\");\n        printk(\"    pc1    - pc1 <addr_min [addr_max]>/off, set break point PC1\\n\");\n        printk(\"    pc2    - pc2 <addr_min [addr_max]>/off, set break point PC2\\n\");\n        printk(\"    pc3    - pc3 <addr_min [addr_max]>/off, set break point PC3\\n\");\n        printk(\"    daddr0 - daddr0 <addr_min [addr_max] r/w/rw [value]>/off, set break point data address 0\\n\");\n        printk(\"    daddr1 - daddr1 <addr_min [addr_max] r/w/rw [value]>/off, set break point data address 1\\n\");\n        printk(\"    help  - print this screen\\n\");\n    }\n\n    return count;\n}\n\n#else\n\nstatic int proc_read_pp32(char *page, char **start, off_t off, int count, int *eof, void *data)\n{\n    static const char *stron = \" on\";\n    static const char *stroff = \"off\";\n\n    int len = 0;\n    int cur_context;\n    int f_stopped;\n    char str[256];\n    char strlength;\n    int i, j;\n\n    int pp32;\n\n    for ( pp32 = 0; pp32 < NUM_OF_PP32; pp32++ )\n    {\n        f_stopped = 0;\n\n        len += sprintf(page + off + len, \"===== pp32 core %d =====\\n\", pp32);\n\n  #ifdef CONFIG_VR9\n        if ( (*PP32_FREEZE & (1 << (pp32 << 4))) != 0 )\n        {\n            sprintf(str, \"freezed\");\n            f_stopped = 1;\n        }\n  #else\n        if ( 0 )\n        {\n        }\n  #endif\n        else if ( PP32_CPU_USER_STOPPED(pp32) || PP32_CPU_USER_BREAKIN_RCV(pp32) || PP32_CPU_USER_BREAKPOINT_MET(pp32) )\n        {\n            strlength = 0;\n            if ( PP32_CPU_USER_STOPPED(pp32) )\n                strlength += sprintf(str + strlength, \"stopped\");\n            if ( PP32_CPU_USER_BREAKPOINT_MET(pp32) )\n                strlength += sprintf(str + strlength, strlength ? \" | breakpoint\" : \"breakpoint\");\n            if ( PP32_CPU_USER_BREAKIN_RCV(pp32) )\n                strlength += sprintf(str + strlength, strlength ? \" | breakin\" : \"breakin\");\n            f_stopped = 1;\n        }\n        else if ( PP32_CPU_CUR_PC(pp32) == PP32_CPU_CUR_PC(pp32) )\n        {\n            unsigned int pc_value[64] = {0};\n\n            f_stopped = 1;\n            for ( i = 0; f_stopped && i < NUM_ENTITY(pc_value); i++ )\n            {\n                pc_value[i] = PP32_CPU_CUR_PC(pp32);\n                for ( j = 0; j < i; j++ )\n                    if ( pc_value[j] != pc_value[i] )\n                    {\n                        f_stopped = 0;\n                        break;\n                    }\n            }\n            if ( f_stopped )\n                sprintf(str, \"hang\");\n        }\n        if ( !f_stopped )\n            sprintf(str, \"running\");\n        cur_context = PP32_BRK_CUR_CONTEXT(pp32);\n        len += sprintf(page + off + len, \"Context: %d, PC: 0x%04x, %s\\n\", cur_context, PP32_CPU_CUR_PC(pp32), str);\n\n        if ( PP32_CPU_USER_BREAKPOINT_MET(pp32) )\n        {\n            strlength = 0;\n            if ( PP32_BRK_PC_MET(pp32, 0) )\n                strlength += sprintf(str + strlength, \"pc0\");\n            if ( PP32_BRK_PC_MET(pp32, 1) )\n                strlength += sprintf(str + strlength, strlength ? \" | pc1\" : \"pc1\");\n            if ( PP32_BRK_DATA_ADDR_MET(pp32, 0) )\n                strlength += sprintf(str + strlength, strlength ? \" | daddr0\" : \"daddr0\");\n            if ( PP32_BRK_DATA_ADDR_MET(pp32, 1) )\n                strlength += sprintf(str + strlength, strlength ? \" | daddr1\" : \"daddr1\");\n            if ( PP32_BRK_DATA_VALUE_RD_MET(pp32, 0) )\n            {\n                strlength += sprintf(str + strlength, strlength ? \" | rdval0\" : \"rdval0\");\n                if ( PP32_BRK_DATA_VALUE_RD_LO_EQ(pp32, 0) )\n                {\n                    if ( PP32_BRK_DATA_VALUE_RD_GT_EQ(pp32, 0) )\n                        strlength += sprintf(str + strlength, \" ==\");\n                    else\n                        strlength += sprintf(str + strlength, \" <=\");\n                }\n                else if ( PP32_BRK_DATA_VALUE_RD_GT_EQ(pp32, 0) )\n                    strlength += sprintf(str + strlength, \" >=\");\n            }\n            if ( PP32_BRK_DATA_VALUE_RD_MET(pp32, 1) )\n            {\n                strlength += sprintf(str + strlength, strlength ? \" | rdval1\" : \"rdval1\");\n                if ( PP32_BRK_DATA_VALUE_RD_LO_EQ(pp32, 1) )\n                {\n                    if ( PP32_BRK_DATA_VALUE_RD_GT_EQ(pp32, 1) )\n                        strlength += sprintf(str + strlength, \" ==\");\n                    else\n                        strlength += sprintf(str + strlength, \" <=\");\n                }\n                else if ( PP32_BRK_DATA_VALUE_RD_GT_EQ(pp32, 1) )\n                    strlength += sprintf(str + strlength, \" >=\");\n            }\n            if ( PP32_BRK_DATA_VALUE_WR_MET(pp32, 0) )\n            {\n                strlength += sprintf(str + strlength, strlength ? \" | wtval0\" : \"wtval0\");\n                if ( PP32_BRK_DATA_VALUE_WR_LO_EQ(pp32, 0) )\n                {\n                    if ( PP32_BRK_DATA_VALUE_WR_GT_EQ(pp32, 0) )\n                        strlength += sprintf(str + strlength, \" ==\");\n                    else\n                        strlength += sprintf(str + strlength, \" <=\");\n                }\n                else if ( PP32_BRK_DATA_VALUE_WR_GT_EQ(pp32, 0) )\n                    strlength += sprintf(str + strlength, \" >=\");\n            }\n            if ( PP32_BRK_DATA_VALUE_WR_MET(pp32, 1) )\n            {\n                strlength += sprintf(str + strlength, strlength ? \" | wtval1\" : \"wtval1\");\n                if ( PP32_BRK_DATA_VALUE_WR_LO_EQ(pp32, 1) )\n                {\n                    if ( PP32_BRK_DATA_VALUE_WR_GT_EQ(pp32, 1) )\n                        strlength += sprintf(str + strlength, \" ==\");\n                    else\n                        strlength += sprintf(str + strlength, \" <=\");\n                }\n                else if ( PP32_BRK_DATA_VALUE_WR_GT_EQ(pp32, 1) )\n                    strlength += sprintf(str + strlength, \" >=\");\n            }\n            len += sprintf(page + off + len, \"break reason: %s\\n\", str);\n        }\n\n        if ( f_stopped )\n        {\n            len += sprintf(page + off + len, \"General Purpose Register (Context %d):\\n\", cur_context);\n            for ( i = 0; i < 4; i++ )\n            {\n                for ( j = 0; j < 4; j++ )\n                    len += sprintf(page + off + len, \"   %2d: %08x\", i + j * 4, *PP32_GP_CONTEXTi_REGn(pp32, cur_context, i + j * 4));\n                len += sprintf(page + off + len, \"\\n\");\n            }\n        }\n\n        len += sprintf(page + off + len, \"break out on: break in - %s, stop - %s\\n\",\n                                            PP32_CTRL_OPT_BREAKOUT_ON_BREAKIN(pp32) ? stron : stroff,\n                                            PP32_CTRL_OPT_BREAKOUT_ON_STOP(pp32) ? stron : stroff);\n        len += sprintf(page + off + len, \"     stop on: break in - %s, break point - %s\\n\",\n                                            PP32_CTRL_OPT_STOP_ON_BREAKIN(pp32) ? stron : stroff,\n                                            PP32_CTRL_OPT_STOP_ON_BREAKPOINT(pp32) ? stron : stroff);\n        len += sprintf(page + off + len, \"breakpoint:\\n\");\n        len += sprintf(page + off + len, \"     pc0: 0x%08x, %s\\n\", *PP32_BRK_PC(pp32, 0), PP32_BRK_GRPi_PCn(pp32, 0, 0) ? \"group 0\" : \"off\");\n        len += sprintf(page + off + len, \"     pc1: 0x%08x, %s\\n\", *PP32_BRK_PC(pp32, 1), PP32_BRK_GRPi_PCn(pp32, 1, 1) ? \"group 1\" : \"off\");\n        len += sprintf(page + off + len, \"  daddr0: 0x%08x, %s\\n\", *PP32_BRK_DATA_ADDR(pp32, 0), PP32_BRK_GRPi_DATA_ADDRn(pp32, 0, 0) ? \"group 0\" : \"off\");\n        len += sprintf(page + off + len, \"  daddr1: 0x%08x, %s\\n\", *PP32_BRK_DATA_ADDR(pp32, 1), PP32_BRK_GRPi_DATA_ADDRn(pp32, 1, 1) ? \"group 1\" : \"off\");\n        len += sprintf(page + off + len, \"  rdval0: 0x%08x\\n\", *PP32_BRK_DATA_VALUE_RD(pp32, 0));\n        len += sprintf(page + off + len, \"  rdval1: 0x%08x\\n\", *PP32_BRK_DATA_VALUE_RD(pp32, 1));\n        len += sprintf(page + off + len, \"  wrval0: 0x%08x\\n\", *PP32_BRK_DATA_VALUE_WR(pp32, 0));\n        len += sprintf(page + off + len, \"  wrval1: 0x%08x\\n\", *PP32_BRK_DATA_VALUE_WR(pp32, 1));\n    }\n\n    *eof = 1;\n\n    return len;\n}\n\nstatic int proc_write_pp32(struct file *file, const char *buf, unsigned long count, void *data)\n{\n    char str[2048];\n    char *p;\n    int len, rlen;\n\n    int pp32 = 0;\n    u32 addr;\n\n    len = count < sizeof(str) ? count : sizeof(str) - 1;\n    rlen = len - copy_from_user(str, buf, len);\n    while ( rlen && str[rlen - 1] <= ' ' )\n        rlen--;\n    str[rlen] = 0;\n    for ( p = str; *p && *p <= ' '; p++, rlen-- );\n    if ( !*p )\n        return 0;\n\n    if ( strincmp(p, \"pp32 \", 5) == 0 )\n    {\n        p += 5;\n        rlen -= 5;\n\n        while ( rlen > 0 && *p >= '0' && *p <= '9' )\n        {\n            pp32 += *p - '0';\n            p++;\n            rlen--;\n        }\n        while ( rlen > 0 && *p && *p <= ' ' )\n        {\n            p++;\n            rlen--;\n        }\n\n        if ( pp32 >= NUM_OF_PP32 )\n        {\n            printk(KERN_ERR __FILE__ \":%d:%s: incorrect pp32 index - %d\\n\", __LINE__, __FUNCTION__, pp32);\n            return count;\n        }\n    }\n\n    if ( stricmp(p, \"start\") == 0 )\n    {\n  #ifdef CONFIG_AMAZON_SE\n        *PP32_CTRL_CMD(pp32) = 0;\n  #endif\n        *PP32_CTRL_CMD(pp32) = PP32_CTRL_CMD_RESTART;\n    }\n    else if ( stricmp(p, \"stop\") == 0 )\n    {\n  #ifdef CONFIG_AMAZON_SE\n        *PP32_CTRL_CMD(pp32) = 0;\n  #endif\n        *PP32_CTRL_CMD(pp32) = PP32_CTRL_CMD_STOP;\n    }\n    else if ( stricmp(p, \"step\") == 0 )\n    {\n  #ifdef CONFIG_AMAZON_SE\n        *PP32_CTRL_CMD(pp32) = 0;\n  #endif\n        *PP32_CTRL_CMD(pp32) = PP32_CTRL_CMD_STEP;\n    }\n  #ifdef CONFIG_VR9\n    else if ( stricmp(p, \"unfreeze\") == 0 )\n        *PP32_FREEZE &= ~(1 << (pp32 << 4));\n    else if ( stricmp(p, \"freeze\") == 0 )\n        *PP32_FREEZE |= 1 << (pp32 << 4);\n  #else\n    else if ( stricmp(p, \"unfreeze\") == 0 )\n        *PP32_DBG_CTRL(pp32) = DBG_CTRL_RESTART;\n    else if ( stricmp(p, \"freeze\") == 0 )\n        *PP32_DBG_CTRL(pp32) = DBG_CTRL_STOP;\n  #endif\n    else if ( strincmp(p, \"pc0 \", 4) == 0 )\n    {\n        p += 4;\n        rlen -= 4;\n        if ( stricmp(p, \"off\") == 0 )\n        {\n            *PP32_BRK_TRIG(pp32) = PP32_BRK_GRPi_PCn_OFF(0, 0);\n            *PP32_BRK_PC_MASK(pp32, 0) = PP32_BRK_CONTEXT_MASK_EN;\n            *PP32_BRK_PC(pp32, 0) = 0;\n        }\n        else\n        {\n            addr = get_number(&p, &rlen, 1);\n            *PP32_BRK_PC(pp32, 0) = addr;\n            *PP32_BRK_PC_MASK(pp32, 0) = PP32_BRK_CONTEXT_MASK_EN | PP32_BRK_CONTEXT_MASK(0) | PP32_BRK_CONTEXT_MASK(1) | PP32_BRK_CONTEXT_MASK(2) | PP32_BRK_CONTEXT_MASK(3);\n            *PP32_BRK_TRIG(pp32) = PP32_BRK_GRPi_PCn_ON(0, 0);\n        }\n    }\n    else if ( strincmp(p, \"pc1 \", 4) == 0 )\n    {\n        p += 4;\n        rlen -= 4;\n        if ( stricmp(p, \"off\") == 0 )\n        {\n            *PP32_BRK_TRIG(pp32) = PP32_BRK_GRPi_PCn_OFF(1, 1);\n            *PP32_BRK_PC_MASK(pp32, 1) = PP32_BRK_CONTEXT_MASK_EN;\n            *PP32_BRK_PC(pp32, 1) = 0;\n        }\n        else\n        {\n            addr = get_number(&p, &rlen, 1);\n            *PP32_BRK_PC(pp32, 1) = addr;\n            *PP32_BRK_PC_MASK(pp32, 1) = PP32_BRK_CONTEXT_MASK_EN | PP32_BRK_CONTEXT_MASK(0) | PP32_BRK_CONTEXT_MASK(1) | PP32_BRK_CONTEXT_MASK(2) | PP32_BRK_CONTEXT_MASK(3);\n            *PP32_BRK_TRIG(pp32) = PP32_BRK_GRPi_PCn_ON(1, 1);\n        }\n    }\n    else if ( strincmp(p, \"daddr0 \", 7) == 0 )\n    {\n        p += 7;\n        rlen -= 7;\n        if ( stricmp(p, \"off\") == 0 )\n        {\n            *PP32_BRK_TRIG(pp32) = PP32_BRK_GRPi_DATA_ADDRn_OFF(0, 0);\n            *PP32_BRK_DATA_ADDR_MASK(pp32, 0) = PP32_BRK_CONTEXT_MASK_EN;\n            *PP32_BRK_DATA_ADDR(pp32, 0) = 0;\n        }\n        else\n        {\n            addr = get_number(&p, &rlen, 1);\n            *PP32_BRK_DATA_ADDR(pp32, 0) = addr;\n            *PP32_BRK_DATA_ADDR_MASK(pp32, 0) = PP32_BRK_CONTEXT_MASK_EN | PP32_BRK_CONTEXT_MASK(0) | PP32_BRK_CONTEXT_MASK(1) | PP32_BRK_CONTEXT_MASK(2) | PP32_BRK_CONTEXT_MASK(3);\n            *PP32_BRK_TRIG(pp32) = PP32_BRK_GRPi_DATA_ADDRn_ON(0, 0);\n        }\n    }\n    else if ( strincmp(p, \"daddr1 \", 7) == 0 )\n    {\n        p += 7;\n        rlen -= 7;\n        if ( stricmp(p, \"off\") == 0 )\n        {\n            *PP32_BRK_TRIG(pp32) = PP32_BRK_GRPi_DATA_ADDRn_OFF(1, 1);\n            *PP32_BRK_DATA_ADDR_MASK(pp32, 1) = PP32_BRK_CONTEXT_MASK_EN;\n            *PP32_BRK_DATA_ADDR(pp32, 1) = 0;\n        }\n        else\n        {\n            addr = get_number(&p, &rlen, 1);\n            *PP32_BRK_DATA_ADDR(pp32, 1) = addr;\n            *PP32_BRK_DATA_ADDR_MASK(pp32, 1) = PP32_BRK_CONTEXT_MASK_EN | PP32_BRK_CONTEXT_MASK(0) | PP32_BRK_CONTEXT_MASK(1) | PP32_BRK_CONTEXT_MASK(2) | PP32_BRK_CONTEXT_MASK(3);\n            *PP32_BRK_TRIG(pp32) = PP32_BRK_GRPi_DATA_ADDRn_ON(1, 1);\n        }\n    }\n    else\n    {\n\n        printk(\"echo \\\"<command>\\\" > /proc/driver/ifx_ptm/pp32\\n\");\n        printk(\"  command:\\n\");\n        printk(\"    unfreeze - unfreeze pp32\\n\");\n        printk(\"    freeze   - freeze pp32\\n\");\n        printk(\"    start    - run pp32\\n\");\n        printk(\"    stop     - stop pp32\\n\");\n        printk(\"    step     - run pp32 with one step only\\n\");\n        printk(\"    pc0      - pc0 <addr>/off, set break point PC0\\n\");\n        printk(\"    pc1      - pc1 <addr>/off, set break point PC1\\n\");\n        printk(\"    daddr0   - daddr0 <addr>/off, set break point data address 0\\n\");\n        printk(\"    daddr1   - daddr1 <addr>/off, set break point data address 1\\n\");\n        printk(\"    help     - print this screen\\n\");\n    }\n\n    if ( *PP32_BRK_TRIG(pp32) )\n        *PP32_CTRL_OPT(pp32) = PP32_CTRL_OPT_STOP_ON_BREAKPOINT_ON;\n    else\n        *PP32_CTRL_OPT(pp32) = PP32_CTRL_OPT_STOP_ON_BREAKPOINT_OFF;\n\n    return count;\n}\n\n#endif\n\nstatic int stricmp(const char *p1, const char *p2)\n{\n    int c1, c2;\n\n    while ( *p1 && *p2 )\n    {\n        c1 = *p1 >= 'A' && *p1 <= 'Z' ? *p1 + 'a' - 'A' : *p1;\n        c2 = *p2 >= 'A' && *p2 <= 'Z' ? *p2 + 'a' - 'A' : *p2;\n        if ( (c1 -= c2) )\n            return c1;\n        p1++;\n        p2++;\n    }\n\n    return *p1 - *p2;\n}\n\nstatic int strincmp(const char *p1, const char *p2, int n)\n{\n    int c1 = 0, c2;\n\n    while ( n && *p1 && *p2 )\n    {\n        c1 = *p1 >= 'A' && *p1 <= 'Z' ? *p1 + 'a' - 'A' : *p1;\n        c2 = *p2 >= 'A' && *p2 <= 'Z' ? *p2 + 'a' - 'A' : *p2;\n        if ( (c1 -= c2) )\n            return c1;\n        p1++;\n        p2++;\n        n--;\n    }\n\n    return n ? *p1 - *p2 : c1;\n}\n\nstatic int get_token(char **p1, char **p2, int *len, int *colon)\n{\n    int tlen = 0;\n\n    while ( *len && !((**p1 >= 'A' && **p1 <= 'Z') || (**p1 >= 'a' && **p1<= 'z')) )\n    {\n        (*p1)++;\n        (*len)--;\n    }\n    if ( !*len )\n        return 0;\n\n    if ( *colon )\n    {\n        *colon = 0;\n        *p2 = *p1;\n        while ( *len && **p2 > ' ' && **p2 != ',' )\n        {\n            if ( **p2 == ':' )\n            {\n                *colon = 1;\n                break;\n            }\n            (*p2)++;\n            (*len)--;\n            tlen++;\n        }\n        **p2 = 0;\n    }\n    else\n    {\n        *p2 = *p1;\n        while ( *len && **p2 > ' ' && **p2 != ',' )\n        {\n            (*p2)++;\n            (*len)--;\n            tlen++;\n        }\n        **p2 = 0;\n    }\n\n    return tlen;\n}\n\nstatic int get_number(char **p, int *len, int is_hex)\n{\n    int ret = 0;\n    int n = 0;\n\n    if ( (*p)[0] == '0' && (*p)[1] == 'x' )\n    {\n        is_hex = 1;\n        (*p) += 2;\n        (*len) -= 2;\n    }\n\n    if ( is_hex )\n    {\n        while ( *len && ((**p >= '0' && **p <= '9') || (**p >= 'a' && **p <= 'f') || (**p >= 'A' && **p <= 'F')) )\n        {\n            if ( **p >= '0' && **p <= '9' )\n                n = **p - '0';\n            else if ( **p >= 'a' && **p <= 'f' )\n               n = **p - 'a' + 10;\n            else if ( **p >= 'A' && **p <= 'F' )\n                n = **p - 'A' + 10;\n            ret = (ret << 4) | n;\n            (*p)++;\n            (*len)--;\n        }\n    }\n    else\n    {\n        while ( *len && **p >= '0' && **p <= '9' )\n        {\n            n = **p - '0';\n            ret = ret * 10 + n;\n            (*p)++;\n            (*len)--;\n        }\n    }\n\n    return ret;\n}\n\nstatic inline void ignore_space(char **p, int *len)\n{\n    while ( *len && (**p <= ' ' || **p == ':' || **p == '.' || **p == ',') )\n    {\n        (*p)++;\n        (*len)--;\n    }\n}\n\n\n\n/*\n * ####################################\n *           Global Function\n * ####################################\n */\n\n\n\n/*\n * ####################################\n *           Init/Cleanup API\n * ####################################\n */\n\nstatic int __init ifx_ptm_test_init(void)\n{\n    proc_file_create();\n\n    return 0;\n}\n\nstatic void __exit ifx_ptm_test_exit(void)\n{\n    proc_file_delete();\n}\n\nmodule_init(ifx_ptm_test_init);\nmodule_exit(ifx_ptm_test_exit);\n\n#endif\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-ptm/src/ifxmips_ptm_vdsl.c",
    "content": "/******************************************************************************\n**\n** FILE NAME    : ifxmips_ptm_vdsl.c\n** PROJECT      : UEIP\n** MODULES      : PTM\n**\n** DATE         : 7 Jul 2009\n** AUTHOR       : Xu Liang\n** DESCRIPTION  : PTM driver common source file (core functions for VR9)\n** COPYRIGHT    :       Copyright (c) 2006\n**                      Infineon Technologies AG\n**                      Am Campeon 1-12, 85579 Neubiberg, Germany\n**\n**    This program is free software; you can redistribute it and/or modify\n**    it under the terms of the GNU General Public License as published by\n**    the Free Software Foundation; either version 2 of the License, or\n**    (at your option) any later version.\n**\n** HISTORY\n** $Date        $Author         $Comment\n** 07 JUL 2009  Xu Liang        Init Version\n*******************************************************************************/\n\n#include <linux/version.h>\n#include <linux/kernel.h>\n#include <linux/module.h>\n#include <linux/types.h>\n#include <linux/ctype.h>\n#include <linux/errno.h>\n#include <linux/proc_fs.h>\n#include <linux/init.h>\n#include <linux/ioctl.h>\n#include <linux/etherdevice.h>\n#include <linux/interrupt.h>\n#include <linux/netdevice.h>\n#include <linux/platform_device.h>\n#include <linux/of_device.h>\n\n#include \"ifxmips_ptm_vdsl.h\"\n#include <lantiq_soc.h>\n\n#define MODULE_PARM_ARRAY(a, b)   module_param_array(a, int, NULL, 0)\n#define MODULE_PARM(a, b)         module_param(a, int, 0)\n\nstatic int wanqos_en = 0;\nstatic int queue_gamma_map[4] = {0xFE, 0x01, 0x00, 0x00};\n\nMODULE_PARM(wanqos_en, \"i\");\nMODULE_PARM_DESC(wanqos_en, \"WAN QoS support, 1 - enabled, 0 - disabled.\");\n\nMODULE_PARM_ARRAY(queue_gamma_map, \"4-4i\");\nMODULE_PARM_DESC(queue_gamma_map, \"TX QoS queues mapping to 4 TX Gamma interfaces.\");\n\nextern int (*ifx_mei_atm_showtime_enter)(struct port_cell_info *, void *);\nextern int (*ifx_mei_atm_showtime_exit)(void);\nextern int ifx_mei_atm_showtime_check(int *is_showtime, struct port_cell_info *port_cell, void **xdata_addr);\n\nstatic int g_showtime = 0;\nstatic void *g_xdata_addr = NULL;\n\n\n#define ENABLE_TMP_DBG                          0\n\nunsigned long cgu_get_pp32_clock(void)\n{\n\tstruct clk *c = clk_get_ppe();\n\tunsigned long rate = clk_get_rate(c);\n\tclk_put(c);\n\treturn rate;\n}\n\nstatic void ptm_setup(struct net_device *, int);\nstatic struct net_device_stats *ptm_get_stats(struct net_device *);\nstatic int ptm_open(struct net_device *);\nstatic int ptm_stop(struct net_device *);\n  static unsigned int ptm_poll(int, unsigned int);\n  static int ptm_napi_poll(struct napi_struct *, int);\nstatic int ptm_hard_start_xmit(struct sk_buff *, struct net_device *);\nstatic int ptm_ioctl(struct net_device *, struct ifreq *, int);\n#if LINUX_VERSION_CODE < KERNEL_VERSION(5,6,0)\nstatic void ptm_tx_timeout(struct net_device *);\n#else\nstatic void ptm_tx_timeout(struct net_device *, unsigned int txqueue);\n#endif\n\nstatic inline struct sk_buff* alloc_skb_rx(void);\nstatic inline struct sk_buff* alloc_skb_tx(unsigned int);\nstatic inline struct sk_buff *get_skb_pointer(unsigned int);\nstatic inline int get_tx_desc(unsigned int, unsigned int *);\n\n/*\n *  Mailbox handler and signal function\n */\nstatic irqreturn_t mailbox_irq_handler(int, void *);\n\n/*\n *  Tasklet to Handle Swap Descriptors\n */\nstatic void do_swap_desc_tasklet(unsigned long);\n\n\n/*\n *  Init & clean-up functions\n */\nstatic inline int init_priv_data(void);\nstatic inline void clear_priv_data(void);\nstatic inline int init_tables(void);\nstatic inline void clear_tables(void);\n\nstatic int g_wanqos_en = 0;\n\nstatic int g_queue_gamma_map[4];\n\nstatic struct ptm_priv_data g_ptm_priv_data;\n\nstatic struct net_device_ops g_ptm_netdev_ops = {\n    .ndo_get_stats       = ptm_get_stats,\n    .ndo_open            = ptm_open,\n    .ndo_stop            = ptm_stop,\n    .ndo_start_xmit      = ptm_hard_start_xmit,\n    .ndo_validate_addr   = eth_validate_addr,\n    .ndo_set_mac_address = eth_mac_addr,\n    .ndo_do_ioctl        = ptm_ioctl,\n    .ndo_tx_timeout      = ptm_tx_timeout,\n};\n\nstatic struct net_device *g_net_dev[1] = {0};\nstatic char *g_net_dev_name[1] = {\"dsl0\"};\n\nstatic int g_ptm_prio_queue_map[8];\n\n#if LINUX_VERSION_CODE < KERNEL_VERSION(5,9,0)\nstatic DECLARE_TASKLET(g_swap_desc_tasklet, do_swap_desc_tasklet, 0);\n#else\nstatic DECLARE_TASKLET_OLD(g_swap_desc_tasklet, do_swap_desc_tasklet);\n#endif\n\n\nunsigned int ifx_ptm_dbg_enable = DBG_ENABLE_MASK_ERR;\n\n/*\n * ####################################\n *            Local Function\n * ####################################\n */\n\nstatic void ptm_setup(struct net_device *dev, int ndev)\n{\n    netif_carrier_off(dev);\n\n    dev->netdev_ops      = &g_ptm_netdev_ops;\n    /* Allow up to 1508 bytes, for RFC4638 */\n    dev->max_mtu         = ETH_DATA_LEN + 8;\n    netif_napi_add(dev, &g_ptm_priv_data.itf[ndev].napi, ptm_napi_poll, 16);\n    dev->watchdog_timeo  = ETH_WATCHDOG_TIMEOUT;\n\n    dev->dev_addr[0] = 0x00;\n    dev->dev_addr[1] = 0x20;\n\tdev->dev_addr[2] = 0xda;\n\tdev->dev_addr[3] = 0x86;\n\tdev->dev_addr[4] = 0x23;\n\tdev->dev_addr[5] = 0x75 + ndev;\n}\n\nstatic struct net_device_stats *ptm_get_stats(struct net_device *dev)\n{\n   struct net_device_stats *s;\n  \n    if ( dev != g_net_dev[0] )\n        return NULL;\ns = &g_ptm_priv_data.itf[0].stats;\n\n    return s;\n}\n\nstatic int ptm_open(struct net_device *dev)\n{\n    ASSERT(dev == g_net_dev[0], \"incorrect device\");\n\n    napi_enable(&g_ptm_priv_data.itf[0].napi);\n\n    IFX_REG_W32_MASK(0, 1, MBOX_IGU1_IER);\n\n    netif_start_queue(dev);\n\n    return 0;\n}\n\nstatic int ptm_stop(struct net_device *dev)\n{\n    ASSERT(dev == g_net_dev[0], \"incorrect device\");\n\n    IFX_REG_W32_MASK(1 | (1 << 17), 0, MBOX_IGU1_IER);\n\n    napi_disable(&g_ptm_priv_data.itf[0].napi);\n\n    netif_stop_queue(dev);\n\n    return 0;\n}\n\nstatic unsigned int ptm_poll(int ndev, unsigned int work_to_do)\n{\n    unsigned int work_done = 0;\n    volatile struct rx_descriptor *desc;\n    struct rx_descriptor reg_desc;\n    struct sk_buff *skb, *new_skb;\n\n    ASSERT(ndev >= 0 && ndev < ARRAY_SIZE(g_net_dev), \"ndev = %d (wrong value)\", ndev);\n\n    while ( work_done < work_to_do ) {\n\tdesc = &WAN_RX_DESC_BASE[g_ptm_priv_data.itf[0].rx_desc_pos];\n        if ( desc->own /* || !desc->c */ )  //  if PP32 hold descriptor or descriptor not completed\n            break;\n        if ( ++g_ptm_priv_data.itf[0].rx_desc_pos == WAN_RX_DESC_NUM )\n            g_ptm_priv_data.itf[0].rx_desc_pos = 0;\n\n        reg_desc = *desc;\n        skb = get_skb_pointer(reg_desc.dataptr);\n        ASSERT(skb != NULL, \"invalid pointer skb == NULL\");\n\n        new_skb = alloc_skb_rx();\n        if ( new_skb != NULL ) {\n            skb_reserve(skb, reg_desc.byteoff);\n            skb_put(skb, reg_desc.datalen);\n\n            //  parse protocol header\n            skb->dev = g_net_dev[0];\n            skb->protocol = eth_type_trans(skb, skb->dev);\n\n            netif_receive_skb(skb);\n\n            g_ptm_priv_data.itf[0].stats.rx_packets++;\n            g_ptm_priv_data.itf[0].stats.rx_bytes += reg_desc.datalen;\n\n            reg_desc.dataptr = (unsigned int)new_skb->data & 0x0FFFFFFF;\n            reg_desc.byteoff = RX_HEAD_MAC_ADDR_ALIGNMENT;\n        }\n\n        reg_desc.datalen = RX_MAX_BUFFER_SIZE - RX_HEAD_MAC_ADDR_ALIGNMENT;\n        reg_desc.own     = 1;\n        reg_desc.c       = 0;\n\n        /*  write discriptor to memory  */\n        *((volatile unsigned int *)desc + 1) = *((unsigned int *)&reg_desc + 1);\n        wmb();\n        *(volatile unsigned int *)desc = *(unsigned int *)&reg_desc;\n\n        work_done++;\n    }\n\n    return work_done;\n}\n\nstatic int ptm_napi_poll(struct napi_struct *napi, int budget)\n{\n    int ndev = 0;\n    unsigned int work_done;\n\n    work_done = ptm_poll(ndev, budget);\n\n    //  interface down\n    if ( !netif_running(napi->dev) ) {\n        napi_complete(napi);\n        return work_done;\n    }\n\n    //  clear interrupt\n    IFX_REG_W32_MASK(0, 1, MBOX_IGU1_ISRC);\n    //  no more traffic\n    if (work_done < budget) {\n\tnapi_complete(napi);\n        IFX_REG_W32_MASK(0, 1, MBOX_IGU1_IER);\n        return work_done;\n    }\n\n    //  next round\n    return work_done;\n}\n\nstatic int ptm_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)\n{\n    unsigned int f_full;\n    int desc_base;\n    volatile struct tx_descriptor *desc;\n    struct tx_descriptor reg_desc = {0};\n    struct sk_buff *skb_to_free;\n    unsigned int byteoff;\n\n    ASSERT(dev == g_net_dev[0], \"incorrect device\");\n\n    if ( !g_showtime ) {\n        err(\"not in showtime\");\n        goto PTM_HARD_START_XMIT_FAIL;\n    }\n\n    /*  allocate descriptor */\n    desc_base = get_tx_desc(0, &f_full);\n    if ( f_full ) {\n        netif_trans_update(dev);\n        netif_stop_queue(dev);\n\n        IFX_REG_W32_MASK(0, 1 << 17, MBOX_IGU1_ISRC);\n        IFX_REG_W32_MASK(0, 1 << 17, MBOX_IGU1_IER);\n    }\n    if ( desc_base < 0 )\n        goto PTM_HARD_START_XMIT_FAIL;\n    desc = &CPU_TO_WAN_TX_DESC_BASE[desc_base];\n\n    byteoff = (unsigned int)skb->data & (DATA_BUFFER_ALIGNMENT - 1);\n    if ( skb_headroom(skb) < sizeof(struct sk_buff *) + byteoff || skb_cloned(skb) ) {\n        struct sk_buff *new_skb;\n\n        ASSERT(skb_headroom(skb) >= sizeof(struct sk_buff *) + byteoff, \"skb_headroom(skb) < sizeof(struct sk_buff *) + byteoff\");\n        ASSERT(!skb_cloned(skb), \"skb is cloned\");\n\n        new_skb = alloc_skb_tx(skb->len);\n        if ( new_skb == NULL ) {\n            dbg(\"no memory\");\n            goto ALLOC_SKB_TX_FAIL;\n        }\n        skb_put(new_skb, skb->len);\n        memcpy(new_skb->data, skb->data, skb->len);\n        dev_kfree_skb_any(skb);\n        skb = new_skb;\n        byteoff = (unsigned int)skb->data & (DATA_BUFFER_ALIGNMENT - 1);\n        /*  write back to physical memory   */\n        dma_cache_wback((unsigned long)skb->data, skb->len);\n    }\n\n    /* make the skb unowned */\n    skb_orphan(skb);\n\n    *(struct sk_buff **)((unsigned int)skb->data - byteoff - sizeof(struct sk_buff *)) = skb;\n    /*  write back to physical memory   */\n    dma_cache_wback((unsigned long)skb->data - byteoff - sizeof(struct sk_buff *), skb->len + byteoff + sizeof(struct sk_buff *));\n\n    /*  free previous skb   */\n    skb_to_free = get_skb_pointer(desc->dataptr);\n    if ( skb_to_free != NULL )\n        dev_kfree_skb_any(skb_to_free);\n\n    /*  update descriptor   */\n    reg_desc.small   = 0;\n    reg_desc.dataptr = (unsigned int)skb->data & (0x0FFFFFFF ^ (DATA_BUFFER_ALIGNMENT - 1));\n    reg_desc.datalen = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len;\n    reg_desc.qid     = g_ptm_prio_queue_map[skb->priority > 7 ? 7 : skb->priority];\n    reg_desc.byteoff = byteoff;\n    reg_desc.own     = 1;\n    reg_desc.c       = 1;\n    reg_desc.sop = reg_desc.eop = 1;\n\n    /*  update MIB  */\n    g_ptm_priv_data.itf[0].stats.tx_packets++;\n    g_ptm_priv_data.itf[0].stats.tx_bytes += reg_desc.datalen;\n\n    /*  write discriptor to memory  */\n    *((volatile unsigned int *)desc + 1) = *((unsigned int *)&reg_desc + 1);\n    wmb();\n    *(volatile unsigned int *)desc = *(unsigned int *)&reg_desc;\n\n    netif_trans_update(dev);\n\n    return 0;\n\nALLOC_SKB_TX_FAIL:\nPTM_HARD_START_XMIT_FAIL:\n    dev_kfree_skb_any(skb);\n    g_ptm_priv_data.itf[0].stats.tx_dropped++;\n    return 0;\n}\n\nstatic int ptm_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)\n{\n    ASSERT(dev == g_net_dev[0], \"incorrect device\");\n\n    switch ( cmd )\n    {\n    case IFX_PTM_MIB_CW_GET:\n\t((PTM_CW_IF_ENTRY_T *)ifr->ifr_data)->ifRxNoIdleCodewords   = IFX_REG_R32(DREG_AR_CELL0) + IFX_REG_R32(DREG_AR_CELL1);\n        ((PTM_CW_IF_ENTRY_T *)ifr->ifr_data)->ifRxIdleCodewords     = IFX_REG_R32(DREG_AR_IDLE_CNT0) + IFX_REG_R32(DREG_AR_IDLE_CNT1);\n        ((PTM_CW_IF_ENTRY_T *)ifr->ifr_data)->ifRxCodingViolation   = IFX_REG_R32(DREG_AR_CVN_CNT0) + IFX_REG_R32(DREG_AR_CVN_CNT1) + IFX_REG_R32(DREG_AR_CVNP_CNT0) + IFX_REG_R32(DREG_AR_CVNP_CNT1);\n        ((PTM_CW_IF_ENTRY_T *)ifr->ifr_data)->ifTxNoIdleCodewords   = IFX_REG_R32(DREG_AT_CELL0) + IFX_REG_R32(DREG_AT_CELL1);\n        ((PTM_CW_IF_ENTRY_T *)ifr->ifr_data)->ifTxIdleCodewords     = IFX_REG_R32(DREG_AT_IDLE_CNT0) + IFX_REG_R32(DREG_AT_IDLE_CNT1);\n        break;\n    case IFX_PTM_MIB_FRAME_GET:\n\t{\n            PTM_FRAME_MIB_T data = {0};\n            int i;\n\n            data.RxCorrect = IFX_REG_R32(DREG_AR_HEC_CNT0) + IFX_REG_R32(DREG_AR_HEC_CNT1) + IFX_REG_R32(DREG_AR_AIIDLE_CNT0) + IFX_REG_R32(DREG_AR_AIIDLE_CNT1);\n            for ( i = 0; i < 4; i++ )\n                data.RxDropped += WAN_RX_MIB_TABLE(i)->wrx_dropdes_pdu;\n            for ( i = 0; i < 8; i++ )\n                data.TxSend    += WAN_TX_MIB_TABLE(i)->wtx_total_pdu;\n\n            *((PTM_FRAME_MIB_T *)ifr->ifr_data) = data;\n        }\n        break;\n    case IFX_PTM_CFG_GET:\n\t//  use bear channel 0 preemption gamma interface settings\n        ((IFX_PTM_CFG_T *)ifr->ifr_data)->RxEthCrcPresent = 1;\n        ((IFX_PTM_CFG_T *)ifr->ifr_data)->RxEthCrcCheck   = RX_GAMMA_ITF_CFG(0)->rx_eth_fcs_ver_dis == 0 ? 1 : 0;\n        ((IFX_PTM_CFG_T *)ifr->ifr_data)->RxTcCrcCheck    = RX_GAMMA_ITF_CFG(0)->rx_tc_crc_ver_dis == 0 ? 1 : 0;;\n        ((IFX_PTM_CFG_T *)ifr->ifr_data)->RxTcCrcLen      = RX_GAMMA_ITF_CFG(0)->rx_tc_crc_size == 0 ? 0 : (RX_GAMMA_ITF_CFG(0)->rx_tc_crc_size * 16);\n        ((IFX_PTM_CFG_T *)ifr->ifr_data)->TxEthCrcGen     = TX_GAMMA_ITF_CFG(0)->tx_eth_fcs_gen_dis == 0 ? 1 : 0;\n        ((IFX_PTM_CFG_T *)ifr->ifr_data)->TxTcCrcGen      = TX_GAMMA_ITF_CFG(0)->tx_tc_crc_size == 0 ? 0 : 1;\n        ((IFX_PTM_CFG_T *)ifr->ifr_data)->TxTcCrcLen      = TX_GAMMA_ITF_CFG(0)->tx_tc_crc_size == 0 ? 0 : (TX_GAMMA_ITF_CFG(0)->tx_tc_crc_size * 16);\n        break;\n    case IFX_PTM_CFG_SET:\n\t{\n            int i;\n\n            for ( i = 0; i < 4; i++ ) {\n                RX_GAMMA_ITF_CFG(i)->rx_eth_fcs_ver_dis = ((IFX_PTM_CFG_T *)ifr->ifr_data)->RxEthCrcCheck ? 0 : 1;\n\n                RX_GAMMA_ITF_CFG(0)->rx_tc_crc_ver_dis = ((IFX_PTM_CFG_T *)ifr->ifr_data)->RxTcCrcCheck ? 0 : 1;\n\n                switch ( ((IFX_PTM_CFG_T *)ifr->ifr_data)->RxTcCrcLen ) {\n                    case 16: RX_GAMMA_ITF_CFG(0)->rx_tc_crc_size = 1; break;\n                    case 32: RX_GAMMA_ITF_CFG(0)->rx_tc_crc_size = 2; break;\n                    default: RX_GAMMA_ITF_CFG(0)->rx_tc_crc_size = 0;\n                }\n\n                TX_GAMMA_ITF_CFG(0)->tx_eth_fcs_gen_dis = ((IFX_PTM_CFG_T *)ifr->ifr_data)->TxEthCrcGen ? 0 : 1;\n\n                if ( ((IFX_PTM_CFG_T *)ifr->ifr_data)->TxTcCrcGen ) {\n                    switch ( ((IFX_PTM_CFG_T *)ifr->ifr_data)->TxTcCrcLen ) {\n                        case 16: TX_GAMMA_ITF_CFG(0)->tx_tc_crc_size = 1; break;\n                        case 32: TX_GAMMA_ITF_CFG(0)->tx_tc_crc_size = 2; break;\n                        default: TX_GAMMA_ITF_CFG(0)->tx_tc_crc_size = 0;\n                    }\n                }\n                else\n                    TX_GAMMA_ITF_CFG(0)->tx_tc_crc_size = 0;\n            }\n        }\n        break;\n    case IFX_PTM_MAP_PKT_PRIO_TO_Q:\n        {\n            struct ppe_prio_q_map cmd;\n\n            if ( copy_from_user(&cmd, ifr->ifr_data, sizeof(cmd)) )\n                return -EFAULT;\n\n            if ( cmd.pkt_prio < 0 || cmd.pkt_prio >= ARRAY_SIZE(g_ptm_prio_queue_map) )\n                return -EINVAL;\n\n            if ( cmd.qid < 0 || cmd.qid >= g_wanqos_en )\n                return -EINVAL;\n\n            g_ptm_prio_queue_map[cmd.pkt_prio] = cmd.qid;\n        }\n        break;\n    default:\n        return -EOPNOTSUPP;\n    }\n\n    return 0;\n}\n\n#if LINUX_VERSION_CODE < KERNEL_VERSION(5,6,0)\nstatic void ptm_tx_timeout(struct net_device *dev)\n#else\nstatic void ptm_tx_timeout(struct net_device *dev, unsigned int txqueue)\n#endif\n{\n    ASSERT(dev == g_net_dev[0], \"incorrect device\");\n\n    /*  disable TX irq, release skb when sending new packet */\n    IFX_REG_W32_MASK(1 << 17, 0, MBOX_IGU1_IER);\n\n    /*  wake up TX queue    */\n    netif_wake_queue(dev);\n\n    return;\n}\n\nstatic inline struct sk_buff* alloc_skb_rx(void)\n{\n    struct sk_buff *skb;\n\n    /*  allocate memroy including trailer and padding   */\n    skb = dev_alloc_skb(RX_MAX_BUFFER_SIZE + DATA_BUFFER_ALIGNMENT);\n    if ( skb != NULL ) {\n        /*  must be burst length alignment and reserve two more bytes for MAC address alignment  */\n        if ( ((unsigned int)skb->data & (DATA_BUFFER_ALIGNMENT - 1)) != 0 )\n            skb_reserve(skb, ~((unsigned int)skb->data + (DATA_BUFFER_ALIGNMENT - 1)) & (DATA_BUFFER_ALIGNMENT - 1));\n        /*  pub skb in reserved area \"skb->data - 4\"    */\n        *((struct sk_buff **)skb->data - 1) = skb;\n        wmb();\n        /*  write back and invalidate cache    */\n        dma_cache_wback_inv((unsigned long)skb->data - sizeof(skb), sizeof(skb));\n        /*  invalidate cache    */\n        dma_cache_inv((unsigned long)skb->data, (unsigned int)skb->end - (unsigned int)skb->data);\n    }\n\n    return skb;\n}\n\nstatic inline struct sk_buff* alloc_skb_tx(unsigned int size)\n{\n    struct sk_buff *skb;\n\n    /*  allocate memory including padding   */\n    size = RX_MAX_BUFFER_SIZE;\n    size = (size + DATA_BUFFER_ALIGNMENT - 1) & ~(DATA_BUFFER_ALIGNMENT - 1);\n    skb = dev_alloc_skb(size + DATA_BUFFER_ALIGNMENT);\n    /*  must be burst length alignment  */\n    if ( skb != NULL )\n        skb_reserve(skb, ~((unsigned int)skb->data + (DATA_BUFFER_ALIGNMENT - 1)) & (DATA_BUFFER_ALIGNMENT - 1));\n    return skb;\n}\n\nstatic inline struct sk_buff *get_skb_pointer(unsigned int dataptr)\n{\n    unsigned int skb_dataptr;\n    struct sk_buff *skb;\n\n    //  usually, CPE memory is less than 256M bytes\n    //  so NULL means invalid pointer\n    if ( dataptr == 0 ) {\n        dbg(\"dataptr is 0, it's supposed to be invalid pointer\");\n        return NULL;\n    }\n\n    skb_dataptr = (dataptr - 4) | KSEG1;\n    skb = *(struct sk_buff **)skb_dataptr;\n\n    ASSERT((unsigned int)skb >= KSEG0, \"invalid skb - skb = %#08x, dataptr = %#08x\", (unsigned int)skb, dataptr);\n    ASSERT((((unsigned int)skb->data & (0x0FFFFFFF ^ (DATA_BUFFER_ALIGNMENT - 1))) | KSEG1) == (dataptr | KSEG1), \"invalid skb - skb = %#08x, skb->data = %#08x, dataptr = %#08x\", (unsigned int)skb, (unsigned int)skb->data, dataptr);\n\n    return skb;\n}\n\nstatic inline int get_tx_desc(unsigned int itf, unsigned int *f_full)\n{\n    int desc_base = -1;\n    struct ptm_itf *p_itf = &g_ptm_priv_data.itf[0];\n\n    //  assume TX is serial operation\n    //  no protection provided\n\n    *f_full = 1;\n\n    if ( CPU_TO_WAN_TX_DESC_BASE[p_itf->tx_desc_pos].own == 0 ) {\n        desc_base = p_itf->tx_desc_pos;\n        if ( ++(p_itf->tx_desc_pos) == CPU_TO_WAN_TX_DESC_NUM )\n            p_itf->tx_desc_pos = 0;\n        if ( CPU_TO_WAN_TX_DESC_BASE[p_itf->tx_desc_pos].own == 0 )\n            *f_full = 0;\n    }\n\n    return desc_base;\n}\n\nstatic irqreturn_t mailbox_irq_handler(int irq, void *dev_id)\n{\n    unsigned int isr;\n    int i;\n\n    isr = IFX_REG_R32(MBOX_IGU1_ISR);\n    IFX_REG_W32(isr, MBOX_IGU1_ISRC);\n    isr &= IFX_REG_R32(MBOX_IGU1_IER);\n\n            if (isr & BIT(0)) {\n                IFX_REG_W32_MASK(1, 0, MBOX_IGU1_IER);\n                napi_schedule(&g_ptm_priv_data.itf[0].napi);\n#if defined(ENABLE_TMP_DBG) && ENABLE_TMP_DBG\n                {\n                    volatile struct rx_descriptor *desc = &WAN_RX_DESC_BASE[g_ptm_priv_data.itf[0].rx_desc_pos];\n\n                    if ( desc->own ) {  //  PP32 hold\n                        err(\"invalid interrupt\");\n                    }\n                }\n#endif\n            }\n\t   if (isr & BIT(16)) {\n                IFX_REG_W32_MASK(1 << 16, 0, MBOX_IGU1_IER);\n                tasklet_hi_schedule(&g_swap_desc_tasklet);\n            }\n\t    if (isr & BIT(17)) {\n                IFX_REG_W32_MASK(1 << 17, 0, MBOX_IGU1_IER);\n                netif_wake_queue(g_net_dev[0]);\n        \t}\n\n    return IRQ_HANDLED;\n}\n\nstatic void do_swap_desc_tasklet(unsigned long arg)\n{\n    int budget = 32;\n    volatile struct tx_descriptor *desc;\n    struct sk_buff *skb;\n    unsigned int byteoff;\n\n    while ( budget-- > 0 ) {\n\tif ( WAN_SWAP_DESC_BASE[g_ptm_priv_data.itf[0].tx_swap_desc_pos].own )  //  if PP32 hold descriptor\n            break;\n\n        desc = &WAN_SWAP_DESC_BASE[g_ptm_priv_data.itf[0].tx_swap_desc_pos];\n        if ( ++g_ptm_priv_data.itf[0].tx_swap_desc_pos == WAN_SWAP_DESC_NUM )\n            g_ptm_priv_data.itf[0].tx_swap_desc_pos = 0;\n\n        skb = get_skb_pointer(desc->dataptr);\n        if ( skb != NULL )\n            dev_kfree_skb_any(skb);\n\n        skb = alloc_skb_tx(RX_MAX_BUFFER_SIZE);\n        if ( skb == NULL )\n            panic(\"can't allocate swap buffer for PPE firmware use\\n\");\n        byteoff = (unsigned int)skb->data & (DATA_BUFFER_ALIGNMENT - 1);\n        *(struct sk_buff **)((unsigned int)skb->data - byteoff - sizeof(struct sk_buff *)) = skb;\n\n        desc->dataptr = (unsigned int)skb->data & 0x0FFFFFFF;\n        desc->own = 1;\n    }\n\n    //  clear interrupt\n    IFX_REG_W32_MASK(0, 16, MBOX_IGU1_ISRC);\n    //  no more skb to be replaced\n    if ( WAN_SWAP_DESC_BASE[g_ptm_priv_data.itf[0].tx_swap_desc_pos].own ) {    //  if PP32 hold descriptor\n        IFX_REG_W32_MASK(0, 1 << 16, MBOX_IGU1_IER);\n        return;\n    }\n\n    tasklet_hi_schedule(&g_swap_desc_tasklet);\n    return;\n}\n\n\nstatic inline int ifx_ptm_version(char *buf)\n{\n    int len = 0;\n    unsigned int major, mid, minor;\n\n    ifx_ptm_get_fw_ver(&major, &mid, &minor);\n\n    len += ifx_drv_ver(buf + len, \"PTM\", IFX_PTM_VER_MAJOR, IFX_PTM_VER_MID, IFX_PTM_VER_MINOR);\n    if ( mid == ~0 )\n        len += sprintf(buf + len, \"    PTM (E1) firmware version %u.%u\\n\", major, minor);\n    else\n        len += sprintf(buf + len, \"    PTM (E1) firmware version %u.%u.%u\\n\", major, mid, minor);\n\n    return len;\n}\n\nstatic inline int init_priv_data(void)\n{\n    int i, j;\n\n    g_wanqos_en = wanqos_en ? wanqos_en : 8;\n    if ( g_wanqos_en > 8 )\n        g_wanqos_en = 8;\n\n    for ( i = 0; i < ARRAY_SIZE(g_queue_gamma_map); i++ )\n    {\n        g_queue_gamma_map[i] = queue_gamma_map[i] & ((1 << g_wanqos_en) - 1);\n        for ( j = 0; j < i; j++ )\n            g_queue_gamma_map[i] &= ~g_queue_gamma_map[j];\n    }\n\n    memset(&g_ptm_priv_data, 0, sizeof(g_ptm_priv_data));\n\n    {\n        int max_packet_priority = ARRAY_SIZE(g_ptm_prio_queue_map);\n        int tx_num_q;\n        int q_step, q_accum, p_step;\n\n        tx_num_q = __ETH_WAN_TX_QUEUE_NUM;\n        q_step = tx_num_q - 1;\n        p_step = max_packet_priority - 1;\n        for ( j = 0, q_accum = 0; j < max_packet_priority; j++, q_accum += q_step )\n            g_ptm_prio_queue_map[j] = q_step - (q_accum + (p_step >> 1)) / p_step;\n    }\n\n    return 0;\n}\n\nstatic inline void clear_priv_data(void)\n{\n}\n\nstatic inline int init_tables(void)\n{\n    struct sk_buff *skb_pool[WAN_RX_DESC_NUM] = {0};\n    struct cfg_std_data_len cfg_std_data_len = {0};\n    struct tx_qos_cfg tx_qos_cfg = {0};\n    struct psave_cfg psave_cfg = {0};\n    struct eg_bwctrl_cfg eg_bwctrl_cfg = {0};\n    struct test_mode test_mode = {0};\n    struct rx_bc_cfg rx_bc_cfg = {0};\n    struct tx_bc_cfg tx_bc_cfg = {0};\n    struct gpio_mode gpio_mode = {0};\n    struct gpio_wm_cfg gpio_wm_cfg = {0};\n    struct rx_gamma_itf_cfg rx_gamma_itf_cfg = {0};\n    struct tx_gamma_itf_cfg tx_gamma_itf_cfg = {0};\n    struct wtx_qos_q_desc_cfg wtx_qos_q_desc_cfg = {0};\n    struct rx_descriptor rx_desc = {0};\n    struct tx_descriptor tx_desc = {0};\n    int i;\n\n    for ( i = 0; i < WAN_RX_DESC_NUM; i++ ) {\n        skb_pool[i] = alloc_skb_rx();\n        if ( skb_pool[i] == NULL )\n            goto ALLOC_SKB_RX_FAIL;\n    }\n\n    cfg_std_data_len.byte_off = RX_HEAD_MAC_ADDR_ALIGNMENT; //  this field replaces byte_off in rx descriptor of VDSL ingress\n    cfg_std_data_len.data_len = 1600;\n    *CFG_STD_DATA_LEN = cfg_std_data_len;\n\n    tx_qos_cfg.time_tick    = cgu_get_pp32_clock() / 62500; //  16 * (cgu_get_pp32_clock() / 1000000)\n    tx_qos_cfg.overhd_bytes = 0;\n    tx_qos_cfg.eth1_eg_qnum = __ETH_WAN_TX_QUEUE_NUM;\n    tx_qos_cfg.eth1_burst_chk = 1;\n    tx_qos_cfg.eth1_qss     = 0;\n    tx_qos_cfg.shape_en     = 0;    //  disable\n    tx_qos_cfg.wfq_en       = 0;    //  strict priority\n    *TX_QOS_CFG = tx_qos_cfg;\n\n    psave_cfg.start_state   = 0;\n    psave_cfg.sleep_en      = 1;    //  enable sleep mode\n    *PSAVE_CFG = psave_cfg;\n\n    eg_bwctrl_cfg.fdesc_wm  = 16;\n    eg_bwctrl_cfg.class_len = 128;\n    *EG_BWCTRL_CFG = eg_bwctrl_cfg;\n\n    //*GPIO_ADDR = (unsigned int)IFX_GPIO_P0_OUT;\n    *GPIO_ADDR = (unsigned int)0x00000000;  //  disabled by default\n\n    gpio_mode.gpio_bit_bc1 = 2;\n    gpio_mode.gpio_bit_bc0 = 1;\n    gpio_mode.gpio_bc1_en  = 0;\n    gpio_mode.gpio_bc0_en  = 0;\n    *GPIO_MODE = gpio_mode;\n\n    gpio_wm_cfg.stop_wm_bc1  = 2;\n    gpio_wm_cfg.start_wm_bc1 = 4;\n    gpio_wm_cfg.stop_wm_bc0  = 2;\n    gpio_wm_cfg.start_wm_bc0 = 4;\n    *GPIO_WM_CFG = gpio_wm_cfg;\n\n    test_mode.mib_clear_mode    = 0;\n    test_mode.test_mode         = 0;\n    *TEST_MODE = test_mode;\n\n    rx_bc_cfg.local_state   = 0;\n    rx_bc_cfg.remote_state  = 0;\n    rx_bc_cfg.to_false_th   = 7;\n    rx_bc_cfg.to_looking_th = 3;\n    *RX_BC_CFG(0) = rx_bc_cfg;\n    *RX_BC_CFG(1) = rx_bc_cfg;\n\n    tx_bc_cfg.fill_wm   = 2;\n    tx_bc_cfg.uflw_wm   = 2;\n    *TX_BC_CFG(0) = tx_bc_cfg;\n    *TX_BC_CFG(1) = tx_bc_cfg;\n\n    rx_gamma_itf_cfg.receive_state      = 0;\n    rx_gamma_itf_cfg.rx_min_len         = 60;\n    rx_gamma_itf_cfg.rx_pad_en          = 1;\n    rx_gamma_itf_cfg.rx_eth_fcs_ver_dis = 0;\n    rx_gamma_itf_cfg.rx_rm_eth_fcs      = 1;\n    rx_gamma_itf_cfg.rx_tc_crc_ver_dis  = 0;\n    rx_gamma_itf_cfg.rx_tc_crc_size     = 1;\n    rx_gamma_itf_cfg.rx_eth_fcs_result  = 0xC704DD7B;\n    rx_gamma_itf_cfg.rx_tc_crc_result   = 0x1D0F1D0F;\n    rx_gamma_itf_cfg.rx_crc_cfg         = 0x2500;\n    rx_gamma_itf_cfg.rx_eth_fcs_init_value  = 0xFFFFFFFF;\n    rx_gamma_itf_cfg.rx_tc_crc_init_value   = 0x0000FFFF;\n    rx_gamma_itf_cfg.rx_max_len_sel     = 0;\n    rx_gamma_itf_cfg.rx_edit_num2       = 0;\n    rx_gamma_itf_cfg.rx_edit_pos2       = 0;\n    rx_gamma_itf_cfg.rx_edit_type2      = 0;\n    rx_gamma_itf_cfg.rx_edit_en2        = 0;\n    rx_gamma_itf_cfg.rx_edit_num1       = 0;\n    rx_gamma_itf_cfg.rx_edit_pos1       = 0;\n    rx_gamma_itf_cfg.rx_edit_type1      = 0;\n    rx_gamma_itf_cfg.rx_edit_en1        = 0;\n    rx_gamma_itf_cfg.rx_inserted_bytes_1l   = 0;\n    rx_gamma_itf_cfg.rx_inserted_bytes_1h   = 0;\n    rx_gamma_itf_cfg.rx_inserted_bytes_2l   = 0;\n    rx_gamma_itf_cfg.rx_inserted_bytes_2h   = 0;\n    rx_gamma_itf_cfg.rx_len_adj         = -6;\n    for ( i = 0; i < 4; i++ )\n        *RX_GAMMA_ITF_CFG(i) = rx_gamma_itf_cfg;\n\n    tx_gamma_itf_cfg.tx_len_adj         = 6;\n    tx_gamma_itf_cfg.tx_crc_off_adj     = 6;\n    tx_gamma_itf_cfg.tx_min_len         = 0;\n    tx_gamma_itf_cfg.tx_eth_fcs_gen_dis = 0;\n    tx_gamma_itf_cfg.tx_tc_crc_size     = 1;\n    tx_gamma_itf_cfg.tx_crc_cfg         = 0x2F00;\n    tx_gamma_itf_cfg.tx_eth_fcs_init_value  = 0xFFFFFFFF;\n    tx_gamma_itf_cfg.tx_tc_crc_init_value   = 0x0000FFFF;\n    for ( i = 0; i < ARRAY_SIZE(g_queue_gamma_map); i++ ) {\n        tx_gamma_itf_cfg.queue_mapping = g_queue_gamma_map[i];\n        *TX_GAMMA_ITF_CFG(i) = tx_gamma_itf_cfg;\n    }\n\n    for ( i = 0; i < __ETH_WAN_TX_QUEUE_NUM; i++ ) {\n        wtx_qos_q_desc_cfg.length = WAN_TX_DESC_NUM;\n        wtx_qos_q_desc_cfg.addr   = __ETH_WAN_TX_DESC_BASE(i);\n        *WTX_QOS_Q_DESC_CFG(i) = wtx_qos_q_desc_cfg;\n    }\n\n    //  default TX queue QoS config is all ZERO\n\n    //  TX Ctrl K Table\n    IFX_REG_W32(0x90111293, TX_CTRL_K_TABLE(0));\n    IFX_REG_W32(0x14959617, TX_CTRL_K_TABLE(1));\n    IFX_REG_W32(0x18999A1B, TX_CTRL_K_TABLE(2));\n    IFX_REG_W32(0x9C1D1E9F, TX_CTRL_K_TABLE(3));\n    IFX_REG_W32(0xA02122A3, TX_CTRL_K_TABLE(4));\n    IFX_REG_W32(0x24A5A627, TX_CTRL_K_TABLE(5));\n    IFX_REG_W32(0x28A9AA2B, TX_CTRL_K_TABLE(6));\n    IFX_REG_W32(0xAC2D2EAF, TX_CTRL_K_TABLE(7));\n    IFX_REG_W32(0x30B1B233, TX_CTRL_K_TABLE(8));\n    IFX_REG_W32(0xB43536B7, TX_CTRL_K_TABLE(9));\n    IFX_REG_W32(0xB8393ABB, TX_CTRL_K_TABLE(10));\n    IFX_REG_W32(0x3CBDBE3F, TX_CTRL_K_TABLE(11));\n    IFX_REG_W32(0xC04142C3, TX_CTRL_K_TABLE(12));\n    IFX_REG_W32(0x44C5C647, TX_CTRL_K_TABLE(13));\n    IFX_REG_W32(0x48C9CA4B, TX_CTRL_K_TABLE(14));\n    IFX_REG_W32(0xCC4D4ECF, TX_CTRL_K_TABLE(15));\n\n    //  init RX descriptor\n    rx_desc.own     = 1;\n    rx_desc.c       = 0;\n    rx_desc.sop     = 1;\n    rx_desc.eop     = 1;\n    rx_desc.byteoff = RX_HEAD_MAC_ADDR_ALIGNMENT;\n    rx_desc.datalen = RX_MAX_BUFFER_SIZE - RX_HEAD_MAC_ADDR_ALIGNMENT;\n    for ( i = 0; i < WAN_RX_DESC_NUM; i++ ) {\n        rx_desc.dataptr = (unsigned int)skb_pool[i]->data & 0x0FFFFFFF;\n        WAN_RX_DESC_BASE[i] = rx_desc;\n    }\n\n    //  init TX descriptor\n    tx_desc.own     = 0;\n    tx_desc.c       = 0;\n    tx_desc.sop     = 1;\n    tx_desc.eop     = 1;\n    tx_desc.byteoff = 0;\n    tx_desc.qid     = 0;\n    tx_desc.datalen = 0;\n    tx_desc.small   = 0;\n    tx_desc.dataptr = 0;\n    for ( i = 0; i < CPU_TO_WAN_TX_DESC_NUM; i++ )\n        CPU_TO_WAN_TX_DESC_BASE[i] = tx_desc;\n    for ( i = 0; i < WAN_TX_DESC_NUM_TOTAL; i++ )\n        WAN_TX_DESC_BASE(0)[i] = tx_desc;\n\n    //  init Swap descriptor\n    for ( i = 0; i < WAN_SWAP_DESC_NUM; i++ )\n        WAN_SWAP_DESC_BASE[i] = tx_desc;\n\n    //  init fastpath TX descriptor\n    tx_desc.own     = 1;\n    for ( i = 0; i < FASTPATH_TO_WAN_TX_DESC_NUM; i++ )\n        FASTPATH_TO_WAN_TX_DESC_BASE[i] = tx_desc;\n\n    return 0;\n\nALLOC_SKB_RX_FAIL:\n    while ( i-- > 0 )\n        dev_kfree_skb_any(skb_pool[i]);\n    return -1;\n}\n\nstatic inline void clear_tables(void)\n{\n    struct sk_buff *skb;\n    int i, j;\n\n    for ( i = 0; i < WAN_RX_DESC_NUM; i++ ) {\n        skb = get_skb_pointer(WAN_RX_DESC_BASE[i].dataptr);\n        if ( skb != NULL )\n            dev_kfree_skb_any(skb);\n    }\n\n    for ( i = 0; i < CPU_TO_WAN_TX_DESC_NUM; i++ ) {\n        skb = get_skb_pointer(CPU_TO_WAN_TX_DESC_BASE[i].dataptr);\n        if ( skb != NULL )\n            dev_kfree_skb_any(skb);\n    }\n\n    for ( j = 0; j < 8; j++ )\n        for ( i = 0; i < WAN_TX_DESC_NUM; i++ ) {\n            skb = get_skb_pointer(WAN_TX_DESC_BASE(j)[i].dataptr);\n            if ( skb != NULL )\n                dev_kfree_skb_any(skb);\n        }\n\n    for ( i = 0; i < WAN_SWAP_DESC_NUM; i++ ) {\n        skb = get_skb_pointer(WAN_SWAP_DESC_BASE[i].dataptr);\n        if ( skb != NULL )\n            dev_kfree_skb_any(skb);\n    }\n\n    for ( i = 0; i < FASTPATH_TO_WAN_TX_DESC_NUM; i++ ) {\n        skb = get_skb_pointer(FASTPATH_TO_WAN_TX_DESC_BASE[i].dataptr);\n        if ( skb != NULL )\n            dev_kfree_skb_any(skb);\n    }\n}\n\nstatic int ptm_showtime_enter(struct port_cell_info *port_cell, void *xdata_addr)\n{\n\tint i;\n\n\tASSERT(port_cell != NULL, \"port_cell is NULL\");\n\tASSERT(xdata_addr != NULL, \"xdata_addr is NULL\");\n\n\t//  TODO: ReTX set xdata_addr\n\tg_xdata_addr = xdata_addr;\n\n\tg_showtime = 1;\n\n\tfor ( i = 0; i < ARRAY_SIZE(g_net_dev); i++ )\n\t\tnetif_carrier_on(g_net_dev[i]);\n\n\tIFX_REG_W32(0x0F, UTP_CFG);\n\n\t//#ifdef CONFIG_VR9\n\t//    IFX_REG_W32_MASK(1 << 17, 0, FFSM_CFG0);\n\t//#endif\n\n\tprintk(\"enter showtime\\n\");\n\n\treturn 0;\n}\n\nstatic int ptm_showtime_exit(void)\n{\n\tint i;\n\n\tif ( !g_showtime )\n\t\treturn -1;\n\n\t//#ifdef CONFIG_VR9\n\t//    IFX_REG_W32_MASK(0, 1 << 17, FFSM_CFG0);\n\t//#endif\n\n\tIFX_REG_W32(0x00, UTP_CFG);\n\n\tfor ( i = 0; i < ARRAY_SIZE(g_net_dev); i++ )\n\t\tnetif_carrier_off(g_net_dev[i]);\n\n\tg_showtime = 0;\n\n\t//  TODO: ReTX clean state\n\tg_xdata_addr = NULL;\n\n\tprintk(\"leave showtime\\n\");\n\n\treturn 0;\n}\n\nstatic const struct of_device_id ltq_ptm_match[] = {\n#ifdef CONFIG_DANUBE\n\t{ .compatible = \"lantiq,ppe-danube\", .data = NULL },\n#elif defined CONFIG_AMAZON_SE\n\t{ .compatible = \"lantiq,ppe-ase\", .data = NULL },\n#elif defined CONFIG_AR9\n\t{ .compatible = \"lantiq,ppe-arx100\", .data = NULL },\n#elif defined CONFIG_VR9\n\t{ .compatible = \"lantiq,ppe-xrx200\", .data = NULL },\n#endif\n\t{},\n};\nMODULE_DEVICE_TABLE(of, ltq_ptm_match);\n\nstatic int ltq_ptm_probe(struct platform_device *pdev)\n{\n    int ret;\n    int i;\n    char ver_str[256];\n    struct port_cell_info port_cell = {0};\n\n    ret = init_priv_data();\n    if ( ret != 0 ) {\n        err(\"INIT_PRIV_DATA_FAIL\");\n        goto INIT_PRIV_DATA_FAIL;\n    }\n\n    ifx_ptm_init_chip(pdev);\n    ret = init_tables();\n    if ( ret != 0 ) {\n        err(\"INIT_TABLES_FAIL\");\n        goto INIT_TABLES_FAIL;\n    }\n\n    for ( i = 0; i < ARRAY_SIZE(g_net_dev); i++ ) {\n        g_net_dev[i] = alloc_netdev(0, g_net_dev_name[i], NET_NAME_UNKNOWN, ether_setup);\n        if ( g_net_dev[i] == NULL )\n            goto ALLOC_NETDEV_FAIL;\n        ptm_setup(g_net_dev[i], i);\n    }\n\n    for ( i = 0; i < ARRAY_SIZE(g_net_dev); i++ ) {\n        ret = register_netdev(g_net_dev[i]);\n        if ( ret != 0 )\n            goto REGISTER_NETDEV_FAIL;\n    }\n\n    /*  register interrupt handler  */\n    ret = request_irq(PPE_MAILBOX_IGU1_INT, mailbox_irq_handler, 0, \"ptm_mailbox_isr\", &g_ptm_priv_data);\n    if ( ret ) {\n        if ( ret == -EBUSY ) {\n            err(\"IRQ may be occupied by other driver, please reconfig to disable it.\");\n        }\n        else {\n            err(\"request_irq fail\");\n        }\n        goto REQUEST_IRQ_PPE_MAILBOX_IGU1_INT_FAIL;\n    }\n    disable_irq(PPE_MAILBOX_IGU1_INT);\n\n    ret = ifx_pp32_start(0);\n    if ( ret ) {\n        err(\"ifx_pp32_start fail!\");\n        goto PP32_START_FAIL;\n    }\n    IFX_REG_W32(1 << 16, MBOX_IGU1_IER);    //  enable SWAP interrupt\n    IFX_REG_W32(~0, MBOX_IGU1_ISRC);\n\n    enable_irq(PPE_MAILBOX_IGU1_INT);\n\n    ifx_mei_atm_showtime_check(&g_showtime, &port_cell, &g_xdata_addr);\n    if ( g_showtime ) {\n\tptm_showtime_enter(&port_cell, &g_xdata_addr);\n    }\n\n    ifx_mei_atm_showtime_enter = ptm_showtime_enter;\n    ifx_mei_atm_showtime_exit  = ptm_showtime_exit;\n\n    ifx_ptm_version(ver_str);\n    printk(KERN_INFO \"%s\", ver_str);\n\n    printk(\"ifxmips_ptm: PTM init succeed\\n\");\n\n    return 0;\n\nPP32_START_FAIL:\n    free_irq(PPE_MAILBOX_IGU1_INT, &g_ptm_priv_data);\nREQUEST_IRQ_PPE_MAILBOX_IGU1_INT_FAIL:\n    i = ARRAY_SIZE(g_net_dev);\nREGISTER_NETDEV_FAIL:\n    while ( i-- )\n        unregister_netdev(g_net_dev[i]);\n    i = ARRAY_SIZE(g_net_dev);\nALLOC_NETDEV_FAIL:\n    while ( i-- ) {\n        free_netdev(g_net_dev[i]);\n        g_net_dev[i] = NULL;\n    }\nINIT_TABLES_FAIL:\nINIT_PRIV_DATA_FAIL:\n    clear_priv_data();\n    printk(\"ifxmips_ptm: PTM init failed\\n\");\n    return ret;\n}\n\nstatic int ltq_ptm_remove(struct platform_device *pdev)\n{\n    int i;\n\tifx_mei_atm_showtime_enter = NULL;\n\tifx_mei_atm_showtime_exit  = NULL;\n\n\n    ifx_pp32_stop(0);\n\n    free_irq(PPE_MAILBOX_IGU1_INT, &g_ptm_priv_data);\n\n    for ( i = 0; i < ARRAY_SIZE(g_net_dev); i++ )\n        unregister_netdev(g_net_dev[i]);\n\n    for ( i = 0; i < ARRAY_SIZE(g_net_dev); i++ ) {\n        free_netdev(g_net_dev[i]);\n        g_net_dev[i] = NULL;\n    }\n\n    clear_tables();\n\n    ifx_ptm_uninit_chip();\n\n    clear_priv_data();\n\n    return 0;\n}\n\n#ifndef MODULE\nstatic int __init wanqos_en_setup(char *line)\n{\n    wanqos_en = simple_strtoul(line, NULL, 0);\n\n    if ( wanqos_en < 1 || wanqos_en > 8 )\n        wanqos_en = 0;\n\n    return 0;\n}\n\nstatic int __init queue_gamma_map_setup(char *line)\n{\n    char *p;\n    int i;\n\n    for ( i = 0, p = line; i < ARRAY_SIZE(queue_gamma_map) && isxdigit(*p); i++ )\n    {\n        queue_gamma_map[i] = simple_strtoul(p, &p, 0);\n        if ( *p == ',' || *p == ';' || *p == ':' )\n            p++;\n    }\n\n    return 0;\n}\n#endif\nstatic struct platform_driver ltq_ptm_driver = {\n\t.probe = ltq_ptm_probe,\n\t.remove = ltq_ptm_remove,\n\t.driver = {\n\t\t.name = \"ptm\",\n\t\t.owner = THIS_MODULE,\n\t\t.of_match_table = ltq_ptm_match,\n\t},\n};\n\nmodule_platform_driver(ltq_ptm_driver);\n#ifndef MODULE\n  __setup(\"wanqos_en=\", wanqos_en_setup);\n  __setup(\"queue_gamma_map=\", queue_gamma_map_setup);\n#endif\n\nMODULE_LICENSE(\"GPL\");\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-ptm/src/ifxmips_ptm_vdsl.h",
    "content": "/******************************************************************************\n**\n** FILE NAME    : ifxmips_ptm_vdsl.h\n** PROJECT      : UEIP\n** MODULES      : PTM\n**\n** DATE         : 7 Jul 2009\n** AUTHOR       : Xu Liang\n** DESCRIPTION  : PTM driver header file (core functions for VR9)\n** COPYRIGHT    :       Copyright (c) 2006\n**                      Infineon Technologies AG\n**                      Am Campeon 1-12, 85579 Neubiberg, Germany\n**\n**    This program is free software; you can redistribute it and/or modify\n**    it under the terms of the GNU General Public License as published by\n**    the Free Software Foundation; either version 2 of the License, or\n**    (at your option) any later version.\n**\n** HISTORY\n** $Date        $Author         $Comment\n** 07 JUL 2009  Xu Liang        Init Version\n*******************************************************************************/\n\n#ifndef IFXMIPS_PTM_VDSL_H\n#define IFXMIPS_PTM_VDSL_H\n\n#include <linux/version.h>\n#include <linux/netdevice.h>\n#include <lantiq_ptm.h>\n#include \"ifxmips_ptm_common.h\"\n#include \"ifxmips_ptm_ppe_common.h\"\n#include \"ifxmips_ptm_fw_regs_vdsl.h\"\n\n#define INT_NUM_IM2_IRL24\t(INT_NUM_IM2_IRL0 + 24)\n\n#define IFX_REG_W32(_v, _r)               __raw_writel((_v), (volatile unsigned int *)(_r))\n#define IFX_REG_R32(_r)                    __raw_readl((volatile unsigned int *)(_r))\n#define IFX_REG_W32_MASK(_clr, _set, _r)   IFX_REG_W32((IFX_REG_R32((_r)) & ~(_clr)) | (_set), (_r))\n#define SET_BITS(x, msb, lsb, value)    (((x) & ~(((1 << ((msb) + 1)) - 1) ^ ((1 << (lsb)) - 1))) | (((value) & ((1 << (1 + (msb) - (lsb))) - 1)) << (lsb)))\n\n\n\n/*\n * ####################################\n *              Definition\n * ####################################\n */\n\n/*\n *  Constant Definition\n */\n#define ETH_WATCHDOG_TIMEOUT            (10 * HZ)\n\n/*\n *  DMA RX/TX Channel Parameters\n */\n#define MAX_ITF_NUMBER                  1\n#define MAX_RX_DMA_CHANNEL_NUMBER       1\n#define MAX_TX_DMA_CHANNEL_NUMBER       1\n#define DATA_BUFFER_ALIGNMENT           EMA_ALIGNMENT\n#define DESC_ALIGNMENT                  8\n\n/*\n *  Ethernet Frame Definitions\n */\n#define ETH_MAC_HEADER_LENGTH           14\n#define ETH_CRC_LENGTH                  4\n#define ETH_MIN_FRAME_LENGTH            64\n#define ETH_MAX_FRAME_LENGTH            (1518 + 4 * 2)\n\n/*\n *  RX Frame Definitions\n */\n#define RX_MAX_BUFFER_SIZE              (1600 + RX_HEAD_MAC_ADDR_ALIGNMENT)\n#define RX_HEAD_MAC_ADDR_ALIGNMENT      2\n#define RX_TAIL_CRC_LENGTH              0   //  PTM firmware does not have ethernet frame CRC\n                                            //  The len in descriptor doesn't include ETH_CRC\n                                            //  because ETH_CRC may not present in some configuration\n\n\n\n/*\n * ####################################\n *              Data Type\n * ####################################\n */\n\nstruct ptm_itf {\n    unsigned int                    rx_desc_pos;\n\n    unsigned int                    tx_desc_pos;\n\n    unsigned int                    tx_swap_desc_pos;\n\n    struct net_device_stats         stats;\n\n    struct napi_struct              napi;\n};\n\nstruct ptm_priv_data {\n    struct ptm_itf                  itf[MAX_ITF_NUMBER];\n};\n\n\n\n/*\n * ####################################\n *             Declaration\n * ####################################\n */\n\nextern unsigned int ifx_ptm_dbg_enable;\n\nextern void ifx_ptm_get_fw_ver(unsigned int *major, unsigned int *mid, unsigned int *minor);\n\nextern void ifx_ptm_init_chip(struct platform_device *pdev);\nextern void ifx_ptm_uninit_chip(void);\n\nextern int ifx_pp32_start(int pp32);\nextern void ifx_pp32_stop(int pp32);\n\nextern void ifx_reset_ppe(void);\n\n\n\n#endif  //  IFXMIPS_PTM_VDSL_H\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-ptm/src/ifxmips_ptm_vr9.c",
    "content": "/******************************************************************************\n**\n** FILE NAME    : ifxmips_ptm_vr9.c\n** PROJECT      : UEIP\n** MODULES      : PTM\n**\n** DATE         : 7 Jul 2009\n** AUTHOR       : Xu Liang\n** DESCRIPTION  : PTM driver common source file (core functions)\n** COPYRIGHT    :       Copyright (c) 2006\n**                      Infineon Technologies AG\n**                      Am Campeon 1-12, 85579 Neubiberg, Germany\n**\n**    This program is free software; you can redistribute it and/or modify\n**    it under the terms of the GNU General Public License as published by\n**    the Free Software Foundation; either version 2 of the License, or\n**    (at your option) any later version.\n**\n** HISTORY\n** $Date        $Author         $Comment\n** 07 JUL 2009  Xu Liang        Init Version\n*******************************************************************************/\n\n\n\n/*\n * ####################################\n *              Head File\n * ####################################\n */\n\n/*\n *  Common Head File\n */\n#include <linux/kernel.h>\n#include <linux/module.h>\n#include <linux/version.h>\n#include <linux/types.h>\n#include <linux/errno.h>\n#include <linux/proc_fs.h>\n#include <linux/init.h>\n#include <linux/ioctl.h>\n#include <linux/platform_device.h>\n#include <linux/reset.h>\n#include <asm/delay.h>\n\n/*\n *  Chip Specific Head File\n */\n#include \"ifxmips_ptm_vdsl.h\"\n#include \"ifxmips_ptm_fw_vr9.h\"\n\n#include <lantiq_soc.h>\n\nstatic inline void init_pmu(void);\nstatic inline void uninit_pmu(void);\nstatic inline void reset_ppe(struct platform_device *pdev);\nstatic inline void init_pdma(void);\nstatic inline void init_mailbox(void);\nstatic inline void init_atm_tc(void);\nstatic inline void clear_share_buffer(void);\n\n#define IFX_PMU_MODULE_PPE_SLL01  BIT(19)\n#define IFX_PMU_MODULE_PPE_TC     BIT(21)\n#define IFX_PMU_MODULE_PPE_EMA    BIT(22)\n#define IFX_PMU_MODULE_PPE_QSB    BIT(18)\n#define IFX_PMU_MODULE_AHBS       BIT(13)\n#define IFX_PMU_MODULE_DSL_DFE    BIT(9)\n\n\nstatic inline void init_pmu(void)\n{\n\tltq_pmu_enable(IFX_PMU_MODULE_PPE_SLL01 |\n\t\tIFX_PMU_MODULE_PPE_TC |\n\t\tIFX_PMU_MODULE_PPE_EMA |\n\t\tIFX_PMU_MODULE_AHBS |\n\t\tIFX_PMU_MODULE_DSL_DFE);\n\n}\n\nstatic inline void uninit_pmu(void)\n{\n}\n\nstatic inline void reset_ppe(struct platform_device *pdev)\n{\n\tstruct device *dev = &pdev->dev;\n\tstruct reset_control *dsp;\n\tstruct reset_control *dfe;\n\tstruct reset_control *tc;\n\n\tdsp = devm_reset_control_get(dev, \"dsp\");\n\tif (IS_ERR(dsp)) {\n\t\tif (PTR_ERR(dsp) != -EPROBE_DEFER)\n\t\t\tdev_err(dev, \"Failed to lookup dsp reset\\n\");\n// \t\treturn PTR_ERR(dsp);\n\t}\n\n\tdfe = devm_reset_control_get(dev, \"dfe\");\n\tif (IS_ERR(dfe)) {\n\t\tif (PTR_ERR(dfe) != -EPROBE_DEFER)\n\t\t\tdev_err(dev, \"Failed to lookup dfe reset\\n\");\n// \t\treturn PTR_ERR(dfe);\n\t}\n\n\ttc = devm_reset_control_get(dev, \"tc\");\n\tif (IS_ERR(tc)) {\n\t\tif (PTR_ERR(tc) != -EPROBE_DEFER)\n\t\t\tdev_err(dev, \"Failed to lookup tc reset\\n\");\n// \t\treturn PTR_ERR(tc);\n\t}\n\n\treset_control_assert(dsp);\n\tudelay(1000);\n\treset_control_assert(dfe);\n\tudelay(1000);\n\treset_control_assert(tc);\n\tudelay(1000);\n\t*PP32_SRST &= ~0x000303CF;\n\tudelay(1000);\n\t*PP32_SRST |= 0x000303CF;\n\tudelay(1000);\n}\n\nstatic inline void init_pdma(void)\n{\n    IFX_REG_W32(0x00000001, PDMA_CFG);\n    IFX_REG_W32(0x00082C00, PDMA_RX_CTX_CFG);\n    IFX_REG_W32(0x00081B00, PDMA_TX_CTX_CFG);\n    IFX_REG_W32(0x02040604, PDMA_RX_MAX_LEN_REG);\n    IFX_REG_W32(0x000F003F, PDMA_RX_DELAY_CFG);\n\n    IFX_REG_W32(0x00000011, SAR_MODE_CFG);\n    IFX_REG_W32(0x00082A00, SAR_RX_CTX_CFG);\n    IFX_REG_W32(0x00082E00, SAR_TX_CTX_CFG);\n    IFX_REG_W32(0x00001021, SAR_POLY_CFG_SET0);\n    IFX_REG_W32(0x1EDC6F41, SAR_POLY_CFG_SET1);\n    IFX_REG_W32(0x04C11DB7, SAR_POLY_CFG_SET2);\n    IFX_REG_W32(0x00000F3E, SAR_CRC_SIZE_CFG);\n\n    IFX_REG_W32(0x01001900, SAR_PDMA_RX_CMDBUF_CFG);\n    IFX_REG_W32(0x01001A00, SAR_PDMA_TX_CMDBUF_CFG);\n}\n\nstatic inline void init_mailbox(void)\n{\n    IFX_REG_W32(0xFFFFFFFF, MBOX_IGU1_ISRC);\n    IFX_REG_W32(0x00000000, MBOX_IGU1_IER);\n    IFX_REG_W32(0xFFFFFFFF, MBOX_IGU3_ISRC);\n    IFX_REG_W32(0x00000000, MBOX_IGU3_IER);\n}\n\nstatic inline void init_atm_tc(void)\n{\n    IFX_REG_W32(0x00010040, SFSM_CFG0);\n    IFX_REG_W32(0x00010040, SFSM_CFG1);\n    IFX_REG_W32(0x00020000, SFSM_PGCNT0);\n    IFX_REG_W32(0x00020000, SFSM_PGCNT1);\n    IFX_REG_W32(0x00000000, DREG_AT_IDLE0);\n    IFX_REG_W32(0x00000000, DREG_AT_IDLE1);\n    IFX_REG_W32(0x00000000, DREG_AR_IDLE0);\n    IFX_REG_W32(0x00000000, DREG_AR_IDLE1);\n    IFX_REG_W32(0x0000080C, DREG_B0_LADR);\n    IFX_REG_W32(0x0000080C, DREG_B1_LADR);\n\n    IFX_REG_W32(0x000001F0, DREG_AR_CFG0);\n    IFX_REG_W32(0x000001F0, DREG_AR_CFG1);\n    IFX_REG_W32(0x000001E0, DREG_AT_CFG0);\n    IFX_REG_W32(0x000001E0, DREG_AT_CFG1);\n\n    /*  clear sync state    */\n    //IFX_REG_W32(0, SFSM_STATE0);\n    //IFX_REG_W32(0, SFSM_STATE1);\n\n    IFX_REG_W32_MASK(0, 1 << 14, SFSM_CFG0);    //  enable SFSM storing\n    IFX_REG_W32_MASK(0, 1 << 14, SFSM_CFG1);\n\n    IFX_REG_W32_MASK(0, 1 << 15, SFSM_CFG0);    //  HW keep the IDLE cells in RTHA buffer\n    IFX_REG_W32_MASK(0, 1 << 15, SFSM_CFG1);\n\n    IFX_REG_W32(0xF0D10000, FFSM_IDLE_HEAD_BC0);\n    IFX_REG_W32(0xF0D10000, FFSM_IDLE_HEAD_BC1);\n    IFX_REG_W32(0x00030028, FFSM_CFG0);         //  Force_idle\n    IFX_REG_W32(0x00030028, FFSM_CFG1);\n}\n\nstatic inline void clear_share_buffer(void)\n{\n    volatile u32 *p;\n    unsigned int i;\n\n    p = SB_RAM0_ADDR(0);\n    for ( i = 0; i < SB_RAM0_DWLEN + SB_RAM1_DWLEN + SB_RAM2_DWLEN + SB_RAM3_DWLEN; i++ )\n        IFX_REG_W32(0, p++);\n\n    p = SB_RAM6_ADDR(0);\n    for ( i = 0; i < SB_RAM6_DWLEN; i++ )\n        IFX_REG_W32(0, p++);\n}\n\n/*\n *  Description:\n *    Download PPE firmware binary code.\n *  Input:\n *    pp32      --- int, which pp32 core\n *    src       --- u32 *, binary code buffer\n *    dword_len --- unsigned int, binary code length in DWORD (32-bit)\n *  Output:\n *    int       --- 0:    Success\n *                  else:           Error Code\n */\nstatic inline int pp32_download_code(int pp32, u32 *code_src, unsigned int code_dword_len, u32 *data_src, unsigned int data_dword_len)\n{\n    unsigned int clr, set;\n    volatile u32 *dest;\n\n    if ( code_src == 0 || ((unsigned long)code_src & 0x03) != 0\n        || data_src == 0 || ((unsigned long)data_src & 0x03) != 0 )\n        return -1;\n\n    clr = pp32 ? 0xF0 : 0x0F;\n    if ( code_dword_len <= CDM_CODE_MEMORYn_DWLEN(0) )\n        set = pp32 ? (3 << 6): (2 << 2);\n    else\n        set = 0x00;\n    IFX_REG_W32_MASK(clr, set, CDM_CFG);\n\n    /*  copy code   */\n    dest = CDM_CODE_MEMORY(pp32, 0);\n    while ( code_dword_len-- > 0 )\n        IFX_REG_W32(*code_src++, dest++);\n\n    /*  copy data   */\n    dest = CDM_DATA_MEMORY(pp32, 0);\n    while ( data_dword_len-- > 0 )\n        IFX_REG_W32(*data_src++, dest++);\n\n    return 0;\n}\n\n\n\n/*\n * ####################################\n *           Global Function\n * ####################################\n */\n\nvoid ifx_ptm_get_fw_ver(unsigned int *major, unsigned int *mid, unsigned int *minor)\n{\n    ASSERT(major != NULL, \"pointer is NULL\");\n    ASSERT(minor != NULL, \"pointer is NULL\");\n\n    if ( *(volatile unsigned int *)FW_VER_ID_NEW == 0 ) {\n        *major = FW_VER_ID->major;\n        *mid   = ~0;\n        *minor = FW_VER_ID->minor;\n    }\n    else {\n        *major = FW_VER_ID_NEW->major;\n        *mid   = FW_VER_ID_NEW->middle;\n        *minor = FW_VER_ID_NEW->minor;\n    }\n}\n\nvoid ifx_ptm_init_chip(struct platform_device *pdev)\n{\n    init_pmu();\n\n    reset_ppe(pdev);\n\n    init_pdma();\n\n    init_mailbox();\n\n    init_atm_tc();\n\n    clear_share_buffer();\n}\n\nvoid ifx_ptm_uninit_chip(void)\n{\n    uninit_pmu();\n}\n\n/*\n *  Description:\n *    Initialize and start up PP32.\n *  Input:\n *    none\n *  Output:\n *    int  --- 0: Success\n *             else:        Error Code\n */\nint ifx_pp32_start(int pp32)\n{\n    unsigned int mask = 1 << (pp32 << 4);\n    int ret;\n\n    /*  download firmware   */\n    ret = pp32_download_code(pp32, firmware_binary_code, sizeof(firmware_binary_code) / sizeof(*firmware_binary_code), firmware_binary_data, sizeof(firmware_binary_data) / sizeof(*firmware_binary_data));\n    if ( ret != 0 )\n        return ret;\n\n    /*  run PP32    */\n    IFX_REG_W32_MASK(mask, 0, PP32_FREEZE);\n\n    /*  idle for a while to let PP32 init itself    */\n    udelay(10);\n\n    return 0;\n}\n\n/*\n *  Description:\n *    Halt PP32.\n *  Input:\n *    none\n *  Output:\n *    none\n */\nvoid ifx_pp32_stop(int pp32)\n{\n    unsigned int mask = 1 << (pp32 << 4);\n\n    /*  halt PP32   */\n    IFX_REG_W32_MASK(0, mask, PP32_FREEZE);\n}\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-tapi/Config.in",
    "content": "config VOICE_CPE_TAPI_FAX\n\tbool \"fax relay and modem support\"\n\tdepends on PACKAGE_kmod-ltq-tapi\n\tdefault n\n\thelp\n\t\tOption to enable fax/modem support in TAPI.\n\t\tNote: Newer platforms as AR9 and VR9 support a T.38 fax relay stack\n\t\tin FW while older platforms like Danube or VINETIC-CPE require a\n\t\tseparate SW stack executed as an application.\n\nconfig VOICE_CPE_TAPI_CID\n\tbool \"CID support\"\n\tdepends on PACKAGE_kmod-ltq-tapi\n\tdefault y\n\thelp\n\t\tOption to enable Caller ID support.\n\nconfig VOICE_CPE_TAPI_LT_GR909\n\tbool \"Linetesting GR-909 support\"\n\tdepends on PACKAGE_kmod-ltq-tapi\n\tdefault y\n\t\thelp\n\t\t\tOption to enable linetesting GR-909.\n\nconfig VOICE_CPE_TAPI_DECT\n\tbool \"DECT encoding for COSIC modem\"\n\tdepends on PACKAGE_kmod-ltq-tapi\n\tdefault n\n\t\thelp\n\t\t\tOption to enable DECT encoding for COSIC modem.\n\nconfig VOICE_CPE_TAPI_KPI\n\tbool \"KPI (Kernel Packet Interface)\"\n\tdepends on PACKAGE_kmod-ltq-tapi\n\tdefault n\n\thelp\n\t\tOption to enable the generic kernel level packet interface\n\t\twhich allows accelerated packet transfer for various purposes.\n\t\tThe most important example is the QOS option, which allows\n\t\tto redirect RTP packets directly into the IP stack.\n\t\tOther options relying on KPI are DECT and HDLC.\n\nconfig VOICE_CPE_TAPI_QOS\n\tbool \"QOS for accelerated RTP packet handling\"\n\tdepends on PACKAGE_kmod-ltq-tapi\n\tdefault n\n\thelp\n\t\tOption to enable an accelerated RTP packet transfer inside\n\t\tthe LINUX kernel space. This option requires the KPI2UDP\n\t\tpacket, which actually provides the OS specific hooks in\n\t\tthe IP stack.\n\nconfig VOICE_CPE_TAPI_STATISTICS\n\tbool \"TAPI statistics via /proc fs\"\n\tdepends on PACKAGE_kmod-ltq-tapi\n\tdefault y\n\thelp\n\t\tOption to enable /proc fs statistics for packet counts etc.\n\nconfig VOICE_CPE_TAPI_METERING\n\tbool \"Metering (TTX) support\"\n\tdepends on PACKAGE_kmod-ltq-tapi\n\tdefault n\n\thelp\n\t\tOption to enable metering (TTX) support.\n\nconfig VOICE_CPE_TAPI_HDLC\n\tbool \"PCM HDLC support, evaluation\"\n\tdepends on PACKAGE_kmod-ltq-tapi\n\tdefault n\n\thelp\n\t\tOption to enable PCM HDLC framing inside the firmware, e.g. for\n\t\tISDN D-Channel access.\n\nconfig VOICE_CPE_TAPI_TRACES\n\tbool \"enable driver traces\"\n\tdepends on PACKAGE_kmod-ltq-tapi\n\tdefault y\n\thelp\n\t\tenable driver traces with different trace levels to be\n\t\tconfigured dynamically from the application or during insmod\n\nconfig VOICE_CPE_TAPI_LINUX_HOTPLUG\n\tbool \"enable driver Linux hotplug events\"\n\tdepends on PACKAGE_kmod-ltq-tapi\n\tdefault y\n\thelp\n\t\tenable driver Linux hotplug events generation\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-tapi/Makefile",
    "content": "#\n# Copyright (C) 2011 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\ninclude $(INCLUDE_DIR)/kernel.mk\n\nPKG_NAME:=drv_tapi\nPKG_VERSION:=3.13.0\nPKG_RELEASE:=4\n\nPKG_SOURCE:=drv_tapi-$(PKG_VERSION).tar.bz2\nPKG_SOURCE_URL:=@OPENWRT\nPKG_HASH:=109374d52872716570fca3fef3b93c9a93159a804dfd42484b19152b825af5c0\nPKG_MAINTAINER:=John Crispin <john@phrozen.org>\n\nPKG_CHECK_FORMAT_SECURITY:=0\nPKG_FIXUP:=autoreconf\nPKG_EXTMOD_SUBDIRS:=src\n\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine KernelPackage/ltq-tapi\n  SUBMENU:=Voice over IP\n  TITLE:=Lantiq TAPI subsystem\n  URL:=http://www.lantiq.com/\n  DEPENDS:=@(TARGET_lantiq_falcon||TARGET_lantiq_xway||TARGET_lantiq_xrx200) +kmod-ltq-ifxos\n  FILES:=$(PKG_BUILD_DIR)/src/drv_tapi.ko\n  AUTOLOAD:=$(call AutoLoad,20,drv_tapi)\nendef\n\ndefine KernelPackage/ltq-tapi/description\n\tVoice Subsystem Telephony API High Level Driver\nendef\n\ndefine KernelPackage/ltq-tapi/config\n\tsource \"$(SOURCE)/Config.in\"\nendef\n\nMAKE_FLAGS += \\\n\t$(KERNEL_MAKE_FLAGS)\n\nCONFIGURE_ARGS += \\\n\tARCH=$(LINUX_KARCH) \\\n\t--enable-linux-26 \\\n\t--enable-kernelbuild=\"$(LINUX_DIR)\" \\\n\t--enable-kernelincl=\"$(LINUX_DIR)/include\" \\\n\t--with-ifxos-incl=$(STAGING_DIR)/usr/include/ifxos \\\n\t$(call autoconf_bool,CONFIG_IFX_DRV_TAPI_EVENT_LOGGER,el-debug) \\\n\t$(call autoconf_bool,CONFIG_VOICE_CPE_TAPI_FAX,fax t38) \\\n\t$(call autoconf_bool,CONFIG_VOICE_CPE_TAPI_CID,cid) \\\n\t$(call autoconf_bool,CONFIG_VOICE_CPE_TAPI_DECT,dect) \\\n\t$(call autoconf_bool,CONFIG_VOICE_CPE_TAPI_KPI,kpi) \\\n\t$(call autoconf_bool,CONFIG_VOICE_CPE_TAPI_QOS,qos) \\\n\t$(call autoconf_bool,CONFIG_VOICE_CPE_TAPI_LT_GR909,lt) \\\n\t$(call autoconf_bool,CONFIG_VOICE_CPE_TAPI_STATISTICS,statistics) \\\n\t$(call autoconf_bool,CONFIG_VOICE_CPE_TAPI_METERING,metering) \\\n\t$(call autoconf_bool,CONFIG_VOICE_CPE_TAPI_HDLC,hdlc) \\\n\t$(call autoconf_bool,CONFIG_VOICE_CPE_TAPI_TRACES,trace) \\\n\t$(call autoconf_bool,CONFIG_VOICE_CPE_TAPI_LINUX_HOTPLUG,hotplug)\n\ndefine Build/InstallDev\n\t$(INSTALL_DIR) $(1)/usr/include/drv_tapi\n\t$(CP) --dereference $(PKG_BUILD_DIR)/include/* $(1)/usr/include/drv_tapi\n\t(cd $(1)/usr/include/drv_tapi && ln -s . include && ln -s ../ifxos/ifx_types.h .)\nendef\n\n$(eval $(call KernelPackage,ltq-tapi))\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-tapi/patches/000-portability.patch",
    "content": "--- a/src/Makefile.am\n+++ b/src/Makefile.am\n@@ -154,7 +154,7 @@ if KERNEL_2_6\n drv_tapi_OBJS = \"$(subst .c,.o, $(drv_tapi_SOURCES))\"\n \n drv_tapi.ko: $(drv_tapi_SOURCES) $(EXTRA_DIST)\n-\t@echo -e \"Making Linux 2.6.x kernel object\"\n+\t@echo \"Making Linux 2.6.x kernel object\"\n \t@for f in $(drv_tapi_SOURCES) ; do \\\n \t\tif test ! -e $(PWD)/$$f; then \\\n \t\t\techo \"  LN      $$f\" ; \\\n@@ -162,10 +162,10 @@ drv_tapi.ko: $(drv_tapi_SOURCES) $(EXTRA\n \t\t\tln -s @abs_srcdir@/$$f $(PWD)/$$f; \\\n \t\tfi; \\\n \tdone;\n-\t@echo -e \"# drv_tapi: Generated to build Linux 2.6.x kernel object\" > $(PWD)/Kbuild\n-\t@echo -e \"obj-m := $(subst .ko,.o,$@)\"\t\t\t>> $(PWD)/Kbuild\n-\t@echo -e \"$(subst .ko,,$@)-y := $(drv_tapi_OBJS)\"\t>> $(PWD)/Kbuild\n-\t@echo -e \"EXTRA_CFLAGS := -DHAVE_CONFIG_H  $(CFLAGS) $(drv_tapi_CFLAGS) $(INCLUDES)\"\t>> $(PWD)/Kbuild\n+\t@echo \"# drv_tapi: Generated to build Linux 2.6.x kernel object\" > $(PWD)/Kbuild\n+\t@echo \"obj-m := $(subst .ko,.o,$@)\"\t\t\t>> $(PWD)/Kbuild\n+\t@echo \"$(subst .ko,,$@)-y := $(drv_tapi_OBJS)\"\t>> $(PWD)/Kbuild\n+\t@echo \"EXTRA_CFLAGS := -DHAVE_CONFIG_H  $(CFLAGS) $(drv_tapi_CFLAGS) $(INCLUDES)\"\t>> $(PWD)/Kbuild\n \t$(MAKE) ARCH=@KERNEL_ARCH@ -C @KERNEL_BUILD_PATH@ O=@KERNEL_BUILD_PATH@ M=$(PWD) modules\n \n clean-generic:\n--- a/configure.in\n+++ b/configure.in\n@@ -128,7 +128,7 @@ dnl Set kernel build path\n AC_ARG_ENABLE(kernelbuild,\n         AS_HELP_STRING(--enable-kernelbuild=x,Set the target kernel build path),\n         [\n-                if test -r $enableval/include/linux/autoconf.h; then\n+                if test -e $enableval/include/linux/autoconf.h  -o -e $enableval/include/generated/autoconf.h; then\n                         AC_SUBST([KERNEL_BUILD_PATH],[$enableval])\n                 else\n                         AC_MSG_ERROR([The kernel build directory is not valid or not configured!])\n--- a/src/drv_tapi_linux.h\n+++ b/src/drv_tapi_linux.h\n@@ -24,6 +24,7 @@\n #include <linux/version.h>\n #include <linux/interrupt.h>           /* in_interrupt() */\n #include <linux/delay.h>               /* mdelay - udelay */\n+#include <linux/workqueue.h>           /* work_struct */\n #include <asm/poll.h>                  /* POLLIN, POLLOUT */\n \n #include \"ifx_types.h\"                 /* ifx type definitions */\n--- a/src/drv_tapi_linux.c\n+++ b/src/drv_tapi_linux.c\n@@ -47,6 +47,7 @@\n #include <linux/errno.h>\n #include <asm/uaccess.h>               /* copy_from_user(), ... */\n #include <asm/byteorder.h>\n+#include <linux/smp_lock.h>         /* lock_kernel() */\n #include <asm/io.h>\n \n #ifdef LINUX_2_6\n@@ -55,7 +56,11 @@\n    #include <linux/sched.h>\n    #undef   CONFIG_DEVFS_FS\n    #ifndef UTS_RELEASE\n-      #include \"linux/utsrelease.h\"\n+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,33))\n+#   include <linux/utsrelease.h>\n+#else\n+#   include <generated/utsrelease.h>\n+#endif\n    #endif /* UTC_RELEASE */\n #else\n    #include <linux/tqueue.h>\n@@ -3718,7 +3723,11 @@ IFX_void_t TAPI_OS_ThreadKill(IFXOS_Thre\n             flag and released after the down() call. */\n          lock_kernel();\n          mb();\n+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28)\n          kill_proc(pThrCntrl->tid, SIGKILL, 1);\n+#else\n+         kill_pid(find_vpid(pThrCntrl->tid), SIGKILL, 1);\n+#endif\n          /* release the big kernel lock */\n          unlock_kernel();\n          wait_for_completion (&pThrCntrl->thrCompletion);\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-tapi/patches/010-fix-compile.patch",
    "content": "--- a/src/drv_tapi_linux.c\n+++ b/src/drv_tapi_linux.c\n@@ -54,6 +54,10 @@\n    #include <linux/workqueue.h>        /* LINUX 2.6 We need work_struct */\n    #include <linux/device.h>\n    #include <linux/sched.h>\n+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,11,0))\n+   #include <linux/sched/signal.h>\n+   #include <uapi/linux/sched/types.h>\n+#endif\n    #undef   CONFIG_DEVFS_FS\n    #ifndef UTS_RELEASE\n #if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,33))\n@@ -184,7 +188,7 @@ MODULE_PARM_DESC(block_egress_tasklet, \"\n MODULE_PARM_DESC(block_ingress_tasklet, \"block the execution of the ingress tasklet, i.e. force to use the RT kernel thread\");\n \n /** The driver callbacks which will be registered with the kernel*/\n-static struct file_operations tapi_fops = {0};\n+static struct file_operations tapi_fops;\n \n /* ============================= */\n /* Global function definition    */\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-tapi/patches/020-not-leak-cflags.patch",
    "content": "--- a/src/Makefile.am\n+++ b/src/Makefile.am\n@@ -122,13 +122,9 @@ endif\n \n ## flags for the driver\n if USE_MODULE\n-drv_tapi_CFLAGS = -DLINUX -D__KERNEL__ -DMODULE -Wno-format -DEXPORT_SYMTAB $(AM_CFLAGS)\n+drv_tapi_CFLAGS = -DLINUX -D__KERNEL__ -DMODULE -DEXPORT_SYMTAB $(AM_CFLAGS)\n else\n-drv_tapi_CFLAGS = -DLINUX -D__KERNEL__ -Wno-format -DEXPORT_SYMTAB $(AM_CFLAGS)\n-endif\n-\n-if KERNEL_2_6\n-drv_tapi_CFLAGS += -fno-common\n+drv_tapi_CFLAGS = -DLINUX -D__KERNEL__ -DEXPORT_SYMTAB $(AM_CFLAGS)\n endif\n \n \n@@ -165,7 +161,7 @@ drv_tapi.ko: $(drv_tapi_SOURCES) $(EXTRA\n \t@echo \"# drv_tapi: Generated to build Linux 2.6.x kernel object\" > $(PWD)/Kbuild\n \t@echo \"obj-m := $(subst .ko,.o,$@)\"\t\t\t>> $(PWD)/Kbuild\n \t@echo \"$(subst .ko,,$@)-y := $(drv_tapi_OBJS)\"\t>> $(PWD)/Kbuild\n-\t@echo \"EXTRA_CFLAGS := -DHAVE_CONFIG_H  $(CFLAGS) $(drv_tapi_CFLAGS) $(INCLUDES)\"\t>> $(PWD)/Kbuild\n+\t@echo \"EXTRA_CFLAGS := -DHAVE_CONFIG_H  $(drv_tapi_CFLAGS) $(INCLUDES)\"\t>> $(PWD)/Kbuild\n \t$(MAKE) ARCH=@KERNEL_ARCH@ -C @KERNEL_BUILD_PATH@ O=@KERNEL_BUILD_PATH@ M=$(PWD) modules\n \n clean-generic:\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-tapi/patches/100-ifxmips.patch",
    "content": "--- a/src/drv_tapi_linux.c\n+++ b/src/drv_tapi_linux.c\n@@ -556,7 +556,7 @@ static ssize_t ifx_tapi_write (struct fi\n    IFX_uint8_t         *pData;\n    IFX_size_t           buf_size;\n #endif /* TAPI_PACKET */\n-   IFX_ssize_t          size = 0;\n+   ssize_t          size = 0;\n \n #ifdef TAPI_PACKET\n    if (pTapiDev->bInitialized == IFX_FALSE)\n--- a/src/drv_tapi_osmap.h\n+++ b/src/drv_tapi_osmap.h\n@@ -17,39 +17,6 @@\n */\n \n #include \"ifx_types.h\"     /* ifx type definitions */\n-\n-#ifndef HAVE_IFX_ULONG_T\n-   #warning please update your ifx_types.h, using local definition of IFX_ulong_t\n-   /* unsigned long type - valid for 32bit systems only */\n-   typedef unsigned long               IFX_ulong_t;\n-   #define HAVE_IFX_ULONG_T\n-#endif /* HAVE_IFX_ULONG_T */\n-\n-#ifndef HAVE_IFX_LONG_T\n-   #warning please update your ifx_types.h, using local definition of IFX_long_t\n-   /* long type - valid for 32bit systems only */\n-   typedef long                        IFX_long_t;\n-   #define HAVE_IFX_LONG_T\n-#endif /* HAVE_IFX_LONG_T */\n-\n-#ifndef HAVE_IFX_INTPTR_T\n-   #warning please update your ifx_types.h, using local definition of IFX_intptr_t\n-   typedef IFX_long_t                  IFX_intptr_t;\n-   #define HAVE_IFX_INTPTR_T\n-#endif /* HAVE_IFX_INTPTR_T */\n-\n-#ifndef HAVE_IFX_SIZE_T\n-   #warning please update your ifx_types.h, using local definition of IFX_size_t\n-   typedef IFX_ulong_t                 IFX_size_t;\n-   #define HAVE_IFX_SIZE_T\n-#endif /* HAVE_IFX_SIZE_T */\n-\n-#ifndef HAVE_IFX_SSIZE_T\n-   #warning please update your ifx_types.h, using local definition of IFX_ssize_t\n-   typedef IFX_long_t                  IFX_ssize_t;\n-   #define HAVE_IFX_SSIZE_T\n-#endif /* HAVE_IFX_SSIZE_T */\n-\n #include \"ifxos_interrupt.h\"\n #include \"ifxos_memory_alloc.h\"\n #include \"ifxos_copy_user_space.h\"\n--- a/include/drv_tapi_ll_interface.h\n+++ b/include/drv_tapi_ll_interface.h\n@@ -40,13 +40,6 @@\n #include \"ifxos_select.h\"\n #endif /* TAPI_PACKET */\n \n-#ifndef HAVE_IFX_ULONG_T\n-   #warning please update your ifx_types.h, using local definition of IFX_ulong_t\n-   /* unsigned long type - valid for 32bit systems only */\n-   typedef unsigned long               IFX_ulong_t;\n-   #define HAVE_IFX_ULONG_T\n-#endif /* HAVE_IFX_ULONG_T */\n-\n /* ============================= */\n /* Local Macros  Definitions    */\n /* ============================= */\n--- a/src/lib/lib_bufferpool/lib_bufferpool.c\n+++ b/src/lib/lib_bufferpool/lib_bufferpool.c\n@@ -85,24 +85,6 @@\n #include <stdlib.h>\n #endif /*VXWORKS*/\n \n-\n-/* ============================= */\n-/* Extra type definitions        */\n-/* ============================= */\n-#ifndef HAVE_IFX_ULONG_T\n-   #warning please update your ifx_types.h, using local definition of IFX_ulong_t\n-   /* unsigned long type - valid for 32bit systems only */\n-   typedef unsigned long               IFX_ulong_t;\n-   #define HAVE_IFX_ULONG_T\n-#endif /* HAVE_IFX_ULONG_T */\n-\n-#ifndef HAVE_IFX_UINTPTR_T\n-   #warning please update your ifx_types.h, using local definition of IFX_uintptr_t\n-   typedef IFX_ulong_t                 IFX_uintptr_t;\n-   #define HAVE_IFX_UINTPTR_T\n-#endif /* HAVE_IFX_UINTPTR_T */\n-\n-\n /* ============================= */\n /* Local Macros & Definitions    */\n /* ============================= */\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-tapi/patches/200-linux-37.patch",
    "content": "--- a/src/drv_tapi_linux.c\n+++ b/src/drv_tapi_linux.c\n@@ -47,7 +47,9 @@\n #include <linux/errno.h>\n #include <asm/uaccess.h>               /* copy_from_user(), ... */\n #include <asm/byteorder.h>\n+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,33))\n #include <linux/smp_lock.h>         /* lock_kernel() */\n+#endif\n #include <asm/io.h>\n \n #ifdef LINUX_2_6\n@@ -69,7 +71,9 @@\n #else\n    #include <linux/tqueue.h>\n    #include <linux/sched.h>\n+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,33))\n    #include <linux/smp_lock.h>         /* lock_kernel() */\n+#endif\n #endif /* LINUX_2_6 */\n \n #include \"drv_tapi.h\"\n@@ -137,8 +141,13 @@ static ssize_t ifx_tapi_write(struct fil\n                               size_t count, loff_t * ppos);\n static ssize_t ifx_tapi_read(struct file * filp, char *buf,\n                               size_t length, loff_t * ppos);\n+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,36))\n static int ifx_tapi_ioctl(struct inode *inode, struct file *filp,\n                               unsigned int nCmd, unsigned long nArgument);\n+#else\n+static long ifx_tapi_ioctl(struct file *filp,\n+                              unsigned int nCmd, unsigned long nArgument);\n+#endif\n static unsigned int ifx_tapi_poll (struct file *filp, poll_table *table);\n \n #ifdef CONFIG_PROC_FS\n@@ -222,7 +231,11 @@ IFX_return_t TAPI_OS_RegisterLLDrv (IFX_\n    IFX_char_t   *pRegDrvName = IFX_NULL;\n    IFX_int32_t ret = 0;\n \n+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,36))\n    if (tapi_fops.ioctl == IFX_NULL)\n+#else\n+   if (tapi_fops.unlocked_ioctl == IFX_NULL)\n+#endif\n    {\n #ifdef MODULE\n       tapi_fops.owner =    THIS_MODULE;\n@@ -230,7 +243,11 @@ IFX_return_t TAPI_OS_RegisterLLDrv (IFX_\n       tapi_fops.read =     ifx_tapi_read;\n       tapi_fops.write =    ifx_tapi_write;\n       tapi_fops.poll =     ifx_tapi_poll;\n+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,36))\n       tapi_fops.ioctl =    ifx_tapi_ioctl;\n+#else\n+      tapi_fops.unlocked_ioctl =    ifx_tapi_ioctl;\n+#endif\n       tapi_fops.open =     ifx_tapi_open;\n       tapi_fops.release =  ifx_tapi_release;\n    }\n@@ -885,8 +902,13 @@ static IFX_uint32_t ifx_tapi_poll (struc\n    - 0 and positive values - success\n    - negative value - ioctl failed\n */\n+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,36))\n static int ifx_tapi_ioctl(struct inode *inode, struct file *filp,\n                           unsigned int nCmd, unsigned long nArg)\n+#else\n+static long ifx_tapi_ioctl(struct file *filp,\n+                          unsigned int nCmd, unsigned long nArg)\n+#endif\n {\n    TAPI_FD_PRIV_DATA_t *pTapiPriv;\n    IFX_TAPI_ioctlCtx_t  ctx;\n@@ -3725,7 +3747,9 @@ IFX_void_t TAPI_OS_ThreadKill(IFXOS_Thre\n             kernel lock (lock_kernel()). The lock must be\n             grabbed before changing the terminate\n             flag and released after the down() call. */\n-         lock_kernel();\n+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,33)\n+\t lock_kernel();\n+#endif\n          mb();\n #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28)\n          kill_proc(pThrCntrl->tid, SIGKILL, 1);\n@@ -3733,8 +3757,10 @@ IFX_void_t TAPI_OS_ThreadKill(IFXOS_Thre\n          kill_pid(find_vpid(pThrCntrl->tid), SIGKILL, 1);\n #endif\n          /* release the big kernel lock */\n+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,33)\n          unlock_kernel();\n-         wait_for_completion (&pThrCntrl->thrCompletion);\n+#endif\n+\t wait_for_completion (&pThrCntrl->thrCompletion);\n \n #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23)\n          /* Now we are sure the thread is in zombie state.\n--- a/src/lib/lib_fifo/lib_fifo.c\n+++ b/src/lib/lib_fifo/lib_fifo.c\n@@ -41,7 +41,7 @@\n #ifdef LINUX\n /* if linux/slab.h is not available, use the precessor linux/malloc.h */\n #include <linux/slab.h>\n-#elif VXWORKS\n+#elif defined(VXWORKS)\n #include <sys_drv_debug.h>\n #endif /* LINUX */\n \n"
  },
  {
    "path": "package/kernel/lantiq/ltq-tapi/patches/300-linux-310.patch",
    "content": "--- a/src/drv_tapi_linux.c\n+++ b/src/drv_tapi_linux.c\n@@ -97,6 +97,8 @@\n #include \"drv_tapi_announcements.h\"\n #endif /* TAPI_ANNOUNCEMENTS */\n \n+#undef CONFIG_PROC_FS\n+\n #define TAPI_IOCTL_STACKSIZE                 4000 /* allow some overhead 4 k */\n \n /* ================================== */\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-tapi/patches/400-linux-415.patch",
    "content": "--- a/src/drv_tapi_linux.c\n+++ b/src/drv_tapi_linux.c\n@@ -119,7 +119,11 @@ struct _TAPI_FD_PRIV_DATA\n /* ============================= */\n /* Local Functions               */\n /* ============================= */\n+#if LINUX_VERSION_CODE < KERNEL_VERSION(4,15,0)\n static IFX_void_t TAPI_timer_call_back (IFX_ulong_t arg);\n+#else\n+static IFX_void_t TAPI_timer_call_back (struct timer_list *t);\n+#endif\n #if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20))\n static IFX_void_t TAPI_tqueue (IFX_void_t *pWork);\n #else /* for Kernel newer or equal 2.6.20 */\n@@ -3384,11 +3388,15 @@ Timer_ID TAPI_Create_Timer(TIMER_ENTRY p\n    pTimerData->nArgument = nArgument;\n    pTimerData->bStopped = IFX_FALSE;\n \n+#if (LINUX_VERSION_CODE < KERNEL_VERSION(4,15,0))\n    init_timer(&(pTimerData->Timer_List));\n \n    /* set timer call back function */\n    pTimerData->Timer_List.function = TAPI_timer_call_back;\n    pTimerData->Timer_List.data = (IFX_ulong_t) pTimerData;\n+#else\n+   timer_setup(&(pTimerData->Timer_List), TAPI_timer_call_back, 0);\n+#endif\n \n    /* Initialize Timer Task */\n #ifdef LINUX_2_6\n@@ -3529,9 +3537,17 @@ static IFX_void_t TAPI_tqueue (struct wo\n \n    \\param  arg          Pointer to corresponding timer ID.\n */\n+#if LINUX_VERSION_CODE < KERNEL_VERSION(4,15,0)\n static IFX_void_t TAPI_timer_call_back (IFX_ulong_t arg)\n+#else\n+static IFX_void_t TAPI_timer_call_back (struct timer_list *t)\n+#endif\n {\n+#if LINUX_VERSION_CODE < KERNEL_VERSION(4,15,0)\n    Timer_ID Timer = (Timer_ID) arg;\n+#else\n+   Timer_ID Timer = from_timer(Timer, t, Timer_List);\n+#endif\n    /* do the operation in process context,\n       not in interrupt context */\n #ifdef LINUX_2_6\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-tapi/patches/500-linux-509.patch",
    "content": "--- a/src/drv_tapi_linux.c\n+++ b/src/drv_tapi_linux.c\n@@ -3287,10 +3287,13 @@ static IFX_void_t proc_EntriesRemove(IFX\n */\n static IFX_void_t tapi_wq_setscheduler (IFX_int32_t foo)\n {\n+#if LINUX_VERSION_CODE < KERNEL_VERSION(5,9,0)\n    struct sched_param sched_params;\n-\n    sched_params.sched_priority = TAPI_OS_THREAD_PRIO_HIGH;\n    sched_setscheduler(current, SCHED_FIFO, &sched_params);\n+#else\n+   sched_set_fifo_low(current);\n+#endif\n }\n #endif /* LINUX_2_6 */\n \n@@ -3727,6 +3730,7 @@ static IFX_int32_t TAPI_SelectCh (TAPI_F\n */\n IFX_int32_t TAPI_OS_ThreadPriorityModify(IFX_uint32_t newPriority)\n {\n+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5,9,0))\n    struct sched_param sched_params;\n    IFX_int32_t ret;\n \n@@ -3744,6 +3748,10 @@ IFX_int32_t TAPI_OS_ThreadPriorityModify\n    }\n \n    return (ret < 0) ? IFX_ERROR : IFX_SUCCESS;\n+#else\n+   sched_set_fifo_low(current);\n+   return IFX_SUCCESS;\n+#endif\n }\n \n \n--- a/src/drv_tapi_kpi.c\n+++ b/src/drv_tapi_kpi.c\n@@ -134,7 +134,11 @@ extern IFX_int32_t           block_ingre\n /* ========================================================================== */\n static IFX_void_t ifx_tapi_KPI_IngressHandler (IFX_ulong_t foo);\n #ifdef KPI_TASKLET\n+#if LINUX_VERSION_CODE < KERNEL_VERSION(5,9,0)\n DECLARE_TASKLET(tl_kpi_ingress, ifx_tapi_KPI_IngressHandler, 0L);\n+#else\n+DECLARE_TASKLET_OLD(tl_kpi_ingress, ifx_tapi_KPI_IngressHandler);\n+#endif\n #endif /* KPI_TASKLET */\n static IFX_int32_t ifx_tapi_KPI_IngressThread (IFXOS_ThreadParams_t *pThread);\n static IFX_return_t ifx_tapi_KPI_GroupInit(IFX_uint32_t nKpiGroup);\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-vdsl/Makefile",
    "content": "# Copyright (C) 2012 OpenWrt.org\n# Copyright (C) 2015-2016 Lantiq Beteiligungs GmbH & Co KG.\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n\ninclude $(TOPDIR)/rules.mk\ninclude $(INCLUDE_DIR)/kernel.mk\n\nPKG_NAME:=ltq-vdsl-vr9\nPKG_VERSION:=4.17.18.6\nPKG_RELEASE:=7\n\nPKG_BASE_NAME:=drv_dsl_cpe_api\nPKG_SOURCE:=$(PKG_BASE_NAME)_vrx-$(PKG_VERSION).tar.gz\nPKG_BUILD_DIR:=$(KERNEL_BUILD_DIR)/$(PKG_BASE_NAME)-$(PKG_VERSION)\nPKG_SOURCE_URL:=@OPENWRT\nPKG_HASH:=b4966a60653acc49254b168c6cc9c49eb36c54548e763617788aa4f252a29f21\nPKG_LICENSE:=GPL-2.0 BSD-2-Clause\nPKG_LICENSE_FILES:=LICENSE\n\nPKG_FIXUP:=autoreconf\n\nPKG_MAINTAINER:=John Crispin <john@phrozen.org>\n\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine KernelPackage/ltq-vdsl-vr9\n  TITLE:=vdsl driver\n  SECTION:=sys\n  SUBMENU:=Network Devices\n  DEPENDS:=@TARGET_lantiq_xrx200 +kmod-ltq-vdsl-vr9-mei\n  FILES:=$(PKG_BUILD_DIR)/src/drv_dsl_cpe_api.ko\n  AUTOLOAD:=$(call AutoLoad,51,drv_dsl_cpe_api)\nendef\n\ndefine Package/ltq-vdsl-vr9/description\n\tThis package contains the Lantiq DSL CPE API driver.\n\n\tSupported Devices:\n\t\t- VRX200 Family\nendef\n\nMAKE_FLAGS += \\\n\t$(KERNEL_MAKE_FLAGS) \\\n\tSHELL=\"$(BASH)\"\n\nCONFIGURE_ARGS += --enable-kernel-include=\"$(LINUX_DIR)/include\" \\\n\t--with-max-device=\"1\" \\\n\t--with-lines-per-device=\"1\" \\\n\t--with-channels-per-line=\"1\" \\\n\t--enable-vrx \\\n\t--enable-vrx-device=vr9 \\\n\t--enable-ifxos \\\n\t--enable-ifxos-include=\"-I$(STAGING_DIR)/usr/include/ifxos\" \\\n\t--enable-driver-include=\"-I$(STAGING_DIR)/usr/include/vdsl\" \\\n\t--enable-add-drv-cflags=\"-DMODULE -DINCLUDE_DSL_ATM_PTM_INTERFACE_SUPPORT\" \\\n\t--enable-linux-26 \\\n\t--enable-kernelbuild=\"$(LINUX_DIR)\" \\\n\t--enable-debug-prints=no \\\n\tARCH=mips\n\nCONFIGURE_ARGS += \\\n\t--enable-model=full \\\n\t--enable-dsl-ceoc=no\n#CONFIGURE_ARGS += --enable-model=lite\n#CONFIGURE_ARGS += --enable-model=footprint\n#CONFIGURE_ARGS += --enable-model=typical\n#CONFIGURE_ARGS += --enable-model=debug\n\ndefine Build/InstallDev\n\t$(INSTALL_DIR) $(1)/usr/include/drv_vdsl_cpe_api\n\t$(CP) $(PKG_BUILD_DIR)/src/include/drv_dsl_cpe*.h $(1)/usr/include/drv_vdsl_cpe_api/\nendef\n\n$(eval $(call KernelPackage,ltq-vdsl-vr9))\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-vdsl/patches/001-fix-compile.patch",
    "content": "--- a/src/include/drv_dsl_cpe_os_linux.h\n+++ b/src/include/drv_dsl_cpe_os_linux.h\n@@ -33,6 +33,9 @@\n #endif\n \n #include <linux/sched.h>\n+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,11,0))\n+#include <linux/sched/signal.h>\n+#endif\n \n #if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,33))\n    #if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,17))\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-vdsl/patches/020-not-leak-cflags.patch",
    "content": "--- a/src/Makefile.am\n+++ b/src/Makefile.am\n@@ -244,10 +244,7 @@ else\n drv_dsl_cpe_api_common_mod_cflags =\n endif\n \n-drv_dsl_cpe_api_common_cflags = -DLINUX -D__LINUX__ -D__KERNEL__ -DEXPORT_SYMTAB \\\n-    -pipe -Wall -Wformat -Wimplicit -Wunused -Wswitch -Wcomment -Winline \\\n-    -Wuninitialized -Wparentheses -Wsign-compare -Wreturn-type \\\n-    -Wstrict-prototypes -Wno-trigraphs -fno-strict-aliasing -fno-common\n+drv_dsl_cpe_api_common_cflags = -DLINUX -D__LINUX__ -D__KERNEL__ -DEXPORT_SYMTAB\n \n if DSL_DBG_MAX_LEVEL_SET\n drv_dsl_cpe_api_common_cflags += -DDSL_DBG_MAX_LEVEL=$(DSL_DBG_MAX_LEVEL_PRE)\n@@ -257,7 +254,7 @@ endif\n drv_dsl_cpe_api_target_cflags = $(ADD_DRV_CFLAGS)\n \n # compile cflags\n-drv_dsl_cpe_api_compile_cflags = $(EXTRA_DRV_CFLAGS)\n+drv_dsl_cpe_api_compile_cflags =\n \n if !KERNEL_2_6\n # the headerfile of linux kernels 2.6.x contain to much arithmetic\n@@ -311,7 +308,7 @@ drv_dsl_cpe_api.ko: $(drv_dsl_cpe_api_SO\n \t@echo -e \"# drv_dsl_cpe_api: Generated to build Linux 2.6.x kernel object\" > $(PWD)/Kbuild\n \t@echo -e \"obj-m := $(subst .ko,.o,$@)\"\t\t\t>> $(PWD)/Kbuild\n \t@echo -e \"$(subst .ko,,$@)-y := $(drv_dsl_cpe_api_OBJS)\"\t>> $(PWD)/Kbuild\n-\t@echo -e \"EXTRA_CFLAGS := $(CFLAGS) -DHAVE_CONFIG_H $(drv_dsl_cpe_api_CFLAGS) $(DSL_DRIVER_INCL_PATH) $(IFXOS_INCLUDE_PATH) -I@abs_srcdir@/include -I$(PWD)/include\"\t>> $(PWD)/Kbuild\n+\t@echo -e \"EXTRA_CFLAGS := -DHAVE_CONFIG_H $(drv_dsl_cpe_api_CFLAGS) $(DSL_DRIVER_INCL_PATH) $(IFXOS_INCLUDE_PATH) -I@abs_srcdir@/include -I$(PWD)/include\"\t>> $(PWD)/Kbuild\n \t$(MAKE) ARCH=@KERNEL_ARCH@ -C @KERNEL_BUILD_PATH@ O=@KERNEL_BUILD_PATH@ M=$(PWD) modules\n \n clean-generic:\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-vdsl/patches/100-compat.patch",
    "content": "--- a/src/Makefile.in\n+++ b/src/Makefile.in\n@@ -117,7 +117,7 @@ POST_UNINSTALL = :\n \n # the headerfile of linux kernels 2.6.x contain to much arithmetic\n # with void pointers (which is allowed for gcc!)\n-@KERNEL_2_6_FALSE@am__append_6 = -Wpointer-arith\n+@KERNEL_2_6_FALSE@am__append_6 =\n subdir = src\n ACLOCAL_M4 = $(top_srcdir)/aclocal.m4\n am__aclocal_m4_deps = $(top_srcdir)/configure.in\n--- a/src/common/drv_dsl_cpe_os_linux.c\n+++ b/src/common/drv_dsl_cpe_os_linux.c\n@@ -11,6 +11,7 @@\n \n #define DSL_INTERN\n \n+#include <linux/device.h>\n #include \"drv_dsl_cpe_api.h\"\n #include \"drv_dsl_cpe_api_ioctl.h\"\n \n@@ -249,14 +250,7 @@ static DSL_long_t DSL_DRV_Ioctls(DSL_DRV\n    }\n \n #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,36))\n-   if (pFile->f_dentry != DSL_NULL)\n-   {\n-      pINode = pFile->f_dentry->d_inode;\n-   }\n-   else\n-   {\n-      pINode = DSL_NULL;\n-   }\n+   pINode = file_inode(pFile);\n #endif\n \n    if (pINode == DSL_NULL)\n@@ -491,7 +485,11 @@ DSL_void_t* DSL_DRV_VMalloc(\n    DSL_DRV_size_t    nSize)\n {\n    /* VRX500-BU: Better to use vmalloc or vzmalloc here?! */\n+#if LINUX_VERSION_CODE < KERNEL_VERSION(5,9,0)\n    return __vmalloc((unsigned long)nSize, GFP_KERNEL, PAGE_KERNEL);\n+#else\n+   return __vmalloc((unsigned long)nSize, GFP_KERNEL);\n+#endif\n    /*   return vmalloc(nSize);*/\n }\n \n@@ -917,12 +915,19 @@ DSL_int32_t DSL_DRV_ThreadShutdown(\n \n DSL_uint32_t DSL_DRV_SysTimeGet(DSL_uint32_t nOffset)\n {\n-   struct timeval tv;\n    DSL_uint32_t nTime = 0;\n+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 0, 0))\n+   struct timeval tv;\n \n    memset(&tv, 0, sizeof(tv));\n    do_gettimeofday(&tv);\n    nTime = (DSL_uint32_t)tv.tv_sec;\n+#else\n+   struct timespec64 now;\n+\n+   ktime_get_real_ts64(&now);\n+   nTime = (DSL_uint32_t)now.tv_sec;\n+#endif\n \n    if ( (nOffset == 0) || (nOffset > nTime) )\n    {\n@@ -1203,6 +1208,9 @@ static void DSL_DRV_NlSendMsg(DSL_char_t\n }\n #endif\n \n+static struct class *dsl_class;\n+static dev_t dsl_devt;\n+\n /* Entry point of driver */\n int __init DSL_ModuleInit(void)\n {\n@@ -1241,6 +1249,10 @@ int __init DSL_ModuleInit(void)\n \n    DSL_DRV_DevNodeInit();\n \n+   dsl_class = class_create(THIS_MODULE, DRV_DSL_CPE_API_DEV_NAME);\n+   dsl_devt = MKDEV(DRV_DSL_CPE_API_DEV_MAJOR, 0);\n+   device_create(dsl_class, NULL, dsl_devt, NULL, \"dsl_cpe_api/0\");\n+\n    return 0;\n }\n \n@@ -1248,6 +1260,11 @@ void __exit DSL_ModuleCleanup(void)\n {\n    printk(\"Module will be unloaded\"DSL_DRV_CRLF);\n \n+   device_destroy(dsl_class, dsl_devt);\n+   dsl_devt = NULL;\n+   class_destroy(dsl_class);\n+   dsl_class = NULL;\n+\n    unregister_chrdev(nMajorNum, DRV_DSL_CPE_API_DEV_NAME);\n    \n    DSL_DRV_Cleanup();\n--- a/src/device/drv_dsl_cpe_device_vrx.c\n+++ b/src/device/drv_dsl_cpe_device_vrx.c\n@@ -5337,6 +5337,7 @@ DSL_Error_t DSL_DRV_DEV_HybridTypeGet(\n #undef DSL_DBG_BLOCK\n #define DSL_DBG_BLOCK DSL_DBG_NOTIFICATIONS\n \n+#if 0\n DSL_Error_t DSL_DRV_DEV_MeiTcLayerSignaling\n (\n    DSL_Context_t *pContext,\n@@ -5384,6 +5385,15 @@ DSL_Error_t DSL_DRV_DEV_MeiTcLayerSignal\n \n    return nErrCode;\n }\n+#else\n+DSL_Error_t DSL_DRV_DEV_MeiTcLayerSignaling\n+(\n+   DSL_Context_t *pContext,\n+   DSL_TcLayerSelection_t nTcLayer)\n+{\n+   return DSL_SUCCESS;\n+}\n+#endif\n \n DSL_Error_t DSL_DRV_DEV_MeiShowtimeSignaling\n (\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-vdsl/patches/110-semaphore-lock.patch",
    "content": "--- a/src/include/drv_dsl_cpe_pm_core.h\n+++ b/src/include/drv_dsl_cpe_pm_core.h\n@@ -1510,9 +1510,9 @@ typedef struct\n    /** Common PM module mutex*/\n    DSL_DRV_Mutex_t pmMutex;\n    /** PM module direction Near-End mutex*/\n-   DSL_DRV_Mutex_t pmNeMutex;\n+   struct semaphore pmNeMutex;\n    /** PM module direction Far-End mutex*/\n-   DSL_DRV_Mutex_t pmFeMutex;\n+   struct semaphore pmFeMutex;\n    /** PM module Near-End access mutex*/\n    DSL_DRV_Mutex_t pmNeAccessMutex;\n    /** PM module Far-End access mutex*/\n--- a/src/pm/drv_dsl_cpe_api_pm.c\n+++ b/src/pm/drv_dsl_cpe_api_pm.c\n@@ -220,9 +220,9 @@ DSL_Error_t DSL_DRV_PM_Start(\n    /* init PM module common mutex */\n    DSL_DRV_MUTEX_INIT(DSL_DRV_PM_CONTEXT(pContext)->pmMutex);\n    /* init PM module direction Near-End mutex */\n-   DSL_DRV_MUTEX_INIT(DSL_DRV_PM_CONTEXT(pContext)->pmNeMutex);\n+   sema_init(&(DSL_DRV_PM_CONTEXT(pContext)->pmNeMutex),1);\n    /* init PM module direction Far-End mutex */\n-   DSL_DRV_MUTEX_INIT(DSL_DRV_PM_CONTEXT(pContext)->pmFeMutex);\n+   sema_init(&(DSL_DRV_PM_CONTEXT(pContext)->pmFeMutex),1);\n    /* init PM module Near-End access mutex */\n    DSL_DRV_MUTEX_INIT(DSL_DRV_PM_CONTEXT(pContext)->pmNeAccessMutex);\n    /* init PM module Far-End access mutex */\n@@ -592,7 +592,7 @@ DSL_Error_t DSL_DRV_PM_Stop(\n    if( DSL_DRV_PM_CONTEXT(pContext)->pmThreadFe.bRun != DSL_TRUE )\n    {\n       DSL_DEBUG(DSL_DBG_WRN,\n-         (pContext, SYS_DBG_WRN\"DSL[%02d]: PM module Near-End thread already stopped\"\n+         (pContext, SYS_DBG_WRN\"DSL[%02d]: PM module Far-End thread already stopped\"\n          DSL_DRV_CRLF, DSL_DEV_NUM(pContext)));\n    }\n    else\n--- a/src/pm/drv_dsl_cpe_pm_core.c\n+++ b/src/pm/drv_dsl_cpe_pm_core.c\n@@ -1022,7 +1022,7 @@ DSL_Error_t DSL_DRV_PM_DirectionMutexCon\n    {\n       if( bLock )\n       {\n-         if( DSL_DRV_MUTEX_LOCK(DSL_DRV_PM_CONTEXT(pContext)->pmNeMutex) )\n+         if(down_interruptible(&(DSL_DRV_PM_CONTEXT(pContext)->pmNeMutex)))\n          {\n             DSL_DEBUG( DSL_DBG_ERR,\n                (pContext, SYS_DBG_ERR\"DSL[%02d]: ERROR - Couldn't lock PM NE mutex!\"\n@@ -1034,14 +1034,14 @@ DSL_Error_t DSL_DRV_PM_DirectionMutexCon\n       else\n       {\n           /* Unlock PM module NE Mutex*/\n-          DSL_DRV_MUTEX_UNLOCK(DSL_DRV_PM_CONTEXT(pContext)->pmNeMutex);\n+          up(&(DSL_DRV_PM_CONTEXT(pContext)->pmNeMutex));\n       }\n    }\n    else\n    {\n       if( bLock )\n       {\n-         if( DSL_DRV_MUTEX_LOCK(DSL_DRV_PM_CONTEXT(pContext)->pmFeMutex) )\n+         if(down_interruptible(&(DSL_DRV_PM_CONTEXT(pContext)->pmFeMutex)))\n          {\n             DSL_DEBUG( DSL_DBG_ERR,\n                (pContext, SYS_DBG_ERR\"DSL[%02d]: ERROR - Couldn't lock PM FE mutex!\"\n@@ -1053,7 +1053,7 @@ DSL_Error_t DSL_DRV_PM_DirectionMutexCon\n       else\n       {\n          /* Unlock PM module FE Mutex*/\n-         DSL_DRV_MUTEX_UNLOCK(DSL_DRV_PM_CONTEXT(pContext)->pmFeMutex);\n+         up(&(DSL_DRV_PM_CONTEXT(pContext)->pmFeMutex));\n       }\n    }\n \n@@ -1139,7 +1139,7 @@ DSL_Error_t DSL_DRV_PM_Lock(DSL_Context_\n    if( !(DSL_DRV_PM_CONTEXT(pContext)->bPmLock) )\n    {\n       /* Lock PM module Near-End Mutex*/\n-      if( DSL_DRV_MUTEX_LOCK(DSL_DRV_PM_CONTEXT(pContext)->pmNeMutex) )\n+      if(down_interruptible(&(DSL_DRV_PM_CONTEXT(pContext)->pmNeMutex)))\n       {\n          DSL_DEBUG( DSL_DBG_ERR,\n             (pContext, SYS_DBG_ERR\"DSL[%02d]: ERROR - Couldn't lock PM NE mutex!\"\n@@ -1148,8 +1148,8 @@ DSL_Error_t DSL_DRV_PM_Lock(DSL_Context_\n          return DSL_ERR_SEMAPHORE_GET;\n       }\n \n-      /* Lock PM module Near-End Mutex*/\n-      if( DSL_DRV_MUTEX_LOCK(DSL_DRV_PM_CONTEXT(pContext)->pmFeMutex) )\n+      /* Lock PM module Far-End Mutex*/\n+      if( down_interruptible(&(DSL_DRV_PM_CONTEXT(pContext)->pmFeMutex)) )\n       {\n          DSL_DEBUG( DSL_DBG_ERR,\n             (pContext, SYS_DBG_ERR\"DSL[%02d]: ERROR - Couldn't lock PM FE mutex!\"\n@@ -1193,10 +1193,10 @@ DSL_Error_t DSL_DRV_PM_UnLock(DSL_Contex\n    if( DSL_DRV_PM_CONTEXT(pContext)->bPmLock )\n    {\n       /* Unlock PM module NE Mutex*/\n-      DSL_DRV_MUTEX_UNLOCK(DSL_DRV_PM_CONTEXT(pContext)->pmNeMutex);\n+      up(&(DSL_DRV_PM_CONTEXT(pContext)->pmNeMutex));\n \n       /* Unlock PM module FE Mutex*/\n-      DSL_DRV_MUTEX_UNLOCK(DSL_DRV_PM_CONTEXT(pContext)->pmFeMutex);\n+      up(&(DSL_DRV_PM_CONTEXT(pContext)->pmFeMutex));\n \n       /* Clear bPmLock flag*/\n       DSL_DRV_PM_CONTEXT(pContext)->bPmLock = DSL_FALSE;\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-vdsl/patches/200-fix-elapsed-time.patch",
    "content": "--- a/src/include/drv_dsl_cpe_pm_core.h\n+++ b/src/include/drv_dsl_cpe_pm_core.h\n@@ -1552,9 +1552,9 @@ typedef struct\n    DSL_boolean_t bShowtimeProcessingStart;\n    /** Showtime reached flag*/\n    DSL_boolean_t bShowtimeInvTrigger;\n-   /** Current Showtime synchronization time to be used, (msec) */\n+   /** Current Showtime synchronization time to be used, (sec) */\n    DSL_uint32_t nCurrShowtimeTime;\n-   /** Showtime synchronization time to be used, (msec) */\n+   /** Showtime synchronization time to be used, (sec) */\n    DSL_uint32_t nElapsedShowtimeTime;\n    /** Actual Line state*/\n    DSL_LineStateValue_t nLineState;\n--- a/src/pm/drv_dsl_cpe_api_pm.c\n+++ b/src/pm/drv_dsl_cpe_api_pm.c\n@@ -1475,7 +1475,7 @@ DSL_Error_t DSL_DRV_PM_ChannelCountersTo\n    }\n \n    /* Fill Total Counters elapsed time*/\n-   pCounters->total.nElapsedTime = DSL_DRV_PM_CONTEXT(pContext)->nPmTotalElapsedTime/DSL_PM_MSEC;\n+   pCounters->total.nElapsedTime = DSL_DRV_PM_CONTEXT(pContext)->nPmTotalElapsedTime;\n \n    pChCounters = DSL_DRV_PM_PTR_CHANNEL_COUNTERS_TOTAL(pCounters->nChannel,pCounters->nDirection);\n \n@@ -1535,7 +1535,7 @@ DSL_Error_t DSL_DRV_PM_ChannelCountersEx\n    }\n \n    /* Fill Total Counters elapsed time*/\n-   pCounters->total.nElapsedTime = DSL_DRV_PM_CONTEXT(pContext)->nPmTotalElapsedTime/DSL_PM_MSEC;\n+   pCounters->total.nElapsedTime = DSL_DRV_PM_CONTEXT(pContext)->nPmTotalElapsedTime;\n \n    pChCounters = DSL_DRV_PM_PTR_CHANNEL_COUNTERS_TOTAL_EXT(pCounters->nChannel);\n \n@@ -2518,7 +2518,7 @@ DSL_Error_t DSL_DRV_PM_DataPathCountersT\n    }\n \n    /* Fill Total Counters elapsed time*/\n-   pCounters->total.nElapsedTime = DSL_DRV_PM_CONTEXT(pContext)->nPmTotalElapsedTime/DSL_PM_MSEC;\n+   pCounters->total.nElapsedTime = DSL_DRV_PM_CONTEXT(pContext)->nPmTotalElapsedTime;\n \n    pDpCounters = DSL_DRV_PM_PTR_DATAPATH_COUNTERS_TOTAL(pCounters->nChannel,pCounters->nDirection);\n \n@@ -3352,7 +3352,7 @@ DSL_Error_t DSL_DRV_PM_DataPathFailureCo\n    }\n \n    /* Fill Total Counters elapsed time*/\n-   pCounters->total.nElapsedTime = DSL_DRV_PM_CONTEXT(pContext)->nPmTotalElapsedTime/DSL_PM_MSEC;\n+   pCounters->total.nElapsedTime = DSL_DRV_PM_CONTEXT(pContext)->nPmTotalElapsedTime;\n \n    pDpCounters = DSL_DRV_PM_PTR_DATAPATH_FAILURE_COUNTERS_TOTAL(pCounters->nChannel,pCounters->nDirection);\n \n@@ -4130,7 +4130,7 @@ DSL_Error_t DSL_DRV_PM_LineSecCountersTo\n    }\n \n    /* Fill Total Counters elapsed time*/\n-   pCounters->total.nElapsedTime = DSL_DRV_PM_CONTEXT(pContext)->nPmTotalElapsedTime/DSL_PM_MSEC;\n+   pCounters->total.nElapsedTime = DSL_DRV_PM_CONTEXT(pContext)->nPmTotalElapsedTime;\n \n    pLineCounters = DSL_DRV_PM_PTR_LINE_SEC_COUNTERS_TOTAL(pCounters->nDirection);\n \n@@ -4787,7 +4787,7 @@ DSL_Error_t DSL_DRV_PM_LineInitCountersT\n    }\n \n    /* Fill Total Counters elapsed time*/\n-   pCounters->total.nElapsedTime = DSL_DRV_PM_CONTEXT(pContext)->nPmTotalElapsedTime/DSL_PM_MSEC;\n+   pCounters->total.nElapsedTime = DSL_DRV_PM_CONTEXT(pContext)->nPmTotalElapsedTime;\n \n    pLinitCounters = DSL_DRV_PM_PTR_LINE_INIT_COUNTERS_TOTAL();\n \n@@ -5240,7 +5240,7 @@ DSL_Error_t DSL_DRV_PM_LineEventShowtime\n    }\n \n    /* Fill Total Counters elapsed time*/\n-   pCounters->total.nElapsedTime = DSL_DRV_PM_CONTEXT(pContext)->nPmTotalElapsedTime/DSL_PM_MSEC;\n+   pCounters->total.nElapsedTime = DSL_DRV_PM_CONTEXT(pContext)->nPmTotalElapsedTime;\n \n    pLfCounters = DSL_DRV_PM_PTR_LINE_EVENT_SHOWTIME_COUNTERS_TOTAL(pCounters->nDirection);\n \n@@ -5720,7 +5720,7 @@ DSL_Error_t DSL_DRV_PM_ReTxCountersTotal\n    }\n \n    /* Fill Total Counters elapsed time*/\n-   pCounters->total.nElapsedTime = DSL_DRV_PM_CONTEXT(pContext)->nPmTotalElapsedTime/DSL_PM_MSEC;\n+   pCounters->total.nElapsedTime = DSL_DRV_PM_CONTEXT(pContext)->nPmTotalElapsedTime;\n \n    pReTxCounters = DSL_DRV_PM_PTR_RETX_COUNTERS_TOTAL(pCounters->nDirection);\n \n--- a/src/pm/drv_dsl_cpe_pm_core.c\n+++ b/src/pm/drv_dsl_cpe_pm_core.c\n@@ -60,6 +60,7 @@ static DSL_Error_t DSL_DRV_PM_SyncTimeUp\n {\n    DSL_Error_t nErrCode = DSL_SUCCESS;\n    DSL_uint32_t msecTimeFrame = DSL_PM_COUNTER_POLLING_CYCLE,\n+                secTimeFrame = DSL_PM_COUNTER_POLLING_CYCLE/DSL_PM_MSEC,\n                 nCurrMsTime = 0;\n #ifdef INCLUDE_DSL_CPE_PM_HISTORY\n    DSL_uint32_t nCurrSysTime = 0, nPrevElapsedTime = 0;\n@@ -99,10 +100,13 @@ static DSL_Error_t DSL_DRV_PM_SyncTimeUp\n    {\n       /* Get elapsed time [msec] since the last entry*/\n       msecTimeFrame = nCurrMsTime  - DSL_DRV_PM_CONTEXT(pContext)->nLastMsTimeCheck;\n+\n+      /* Get elapsed time [sec] since the last entry*/\n+      secTimeFrame = (nCurrMsTime/DSL_PM_MSEC) - (DSL_DRV_PM_CONTEXT(pContext)->nLastMsTimeCheck/DSL_PM_MSEC);\n    }\n \n    /* Get Total Elapsed Time Since the PM module startup*/\n-   DSL_DRV_PM_CONTEXT(pContext)->nPmTotalElapsedTime += msecTimeFrame;\n+   DSL_DRV_PM_CONTEXT(pContext)->nPmTotalElapsedTime += secTimeFrame;\n \n    /* Set last time check to the current time*/\n    DSL_DRV_PM_CONTEXT(pContext)->nLastMsTimeCheck = nCurrMsTime;\n@@ -140,7 +144,7 @@ static DSL_Error_t DSL_DRV_PM_SyncTimeUp\n       else\n       {\n          /* Update current showtime elapsed time*/\n-         DSL_DRV_PM_CONTEXT(pContext)->nCurrShowtimeTime   += (msecTimeFrame/DSL_PM_MSEC);\n+         DSL_DRV_PM_CONTEXT(pContext)->nCurrShowtimeTime   += secTimeFrame;\n          DSL_DRV_PM_CONTEXT(pContext)->nElapsedShowtimeTime =\n             DSL_DRV_PM_CONTEXT(pContext)->nCurrShowtimeTime;\n       }\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-vdsl-fw/Makefile",
    "content": "# Copyright (C) 2012 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=ltq-vdsl-fw\nPKG_VERSION:=6.8.6\nPKG_RELEASE:=4\n\nPKG_MAINTAINER:=Daniel Golle <daniel@makrotopia.org>\n\nPKG_FLAGS:=nonshared\n\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine Package/ltq-vdsl-vr9-vectoring-fw-installer\n  TITLE:=VDSL2 Vectoring Firmware installer\n  SECTION:=net\n  CATEGORY:=Network\n  DEPENDS:=@TARGET_lantiq_xrx200 +kmod-ltq-vdsl-vr9\nendef\n\ndefine Build/Prepare\n\t$(INSTALL_DIR) $(PKG_BUILD_DIR)\n\t$(CP) ./src/* $(PKG_BUILD_DIR)\nendef\n\ndefine Build/Compile\n\t$(TARGET_CONFIGURE_OPTS) \\\n\t\tCFLAGS=\"$(TARGET_CFLAGS)\" \\\n\t\tLDFLAGS=\"$(TARGET_LDFLAGS)\" \\\n\t\t$(MAKE) -C $(PKG_BUILD_DIR)\nendef\n\ndefine Package/ltq-vdsl-vr9-vectoring-fw-installer/install\n\t$(INSTALL_DIR) $(1)/sbin\n\t$(CP) $(PKG_BUILD_DIR)/w921v_fw_cutter $(PKG_BUILD_DIR)/vdsl_fw_install.sh $(1)/sbin/\nendef\n\n$(eval $(call BuildPackage,ltq-vdsl-vr9-vectoring-fw-installer))\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-vdsl-fw/src/LzmaDecode.c",
    "content": "/*\n  LzmaDecode.c\n  LZMA Decoder (optimized for Speed version)\n  \n  LZMA SDK 4.40 Copyright (c) 1999-2006 Igor Pavlov (2006-05-01)\n  http://www.7-zip.org/\n\n  LZMA SDK is licensed under two licenses:\n  1) GNU Lesser General Public License (GNU LGPL)\n  2) Common Public License (CPL)\n  It means that you can select one of these two licenses and \n  follow rules of that license.\n\n  SPECIAL EXCEPTION:\n  Igor Pavlov, as the author of this Code, expressly permits you to \n  statically or dynamically link your Code (or bind by name) to the \n  interfaces of this file without subjecting your linked Code to the \n  terms of the CPL or GNU LGPL. Any modifications or additions \n  to this file, however, are subject to the LGPL or CPL terms.\n*/\n\n#include \"LzmaDecode.h\"\n\n#define kNumTopBits 24\n#define kTopValue ((UInt32)1 << kNumTopBits)\n\n#define kNumBitModelTotalBits 11\n#define kBitModelTotal (1 << kNumBitModelTotalBits)\n#define kNumMoveBits 5\n\n#define RC_READ_BYTE (*Buffer++)\n\n#define RC_INIT2 Code = 0; Range = 0xFFFFFFFF; \\\n  { int i; for(i = 0; i < 5; i++) { RC_TEST; Code = (Code << 8) | RC_READ_BYTE; }}\n\n#ifdef _LZMA_IN_CB\n\n#define RC_TEST { if (Buffer == BufferLim) \\\n  { SizeT size; int result = InCallback->Read(InCallback, &Buffer, &size); if (result != LZMA_RESULT_OK) return result; \\\n  BufferLim = Buffer + size; if (size == 0) return LZMA_RESULT_DATA_ERROR; }}\n\n#define RC_INIT Buffer = BufferLim = 0; RC_INIT2\n\n#else\n\n#define RC_TEST { if (Buffer == BufferLim) return LZMA_RESULT_DATA_ERROR; }\n\n#define RC_INIT(buffer, bufferSize) Buffer = buffer; BufferLim = buffer + bufferSize; RC_INIT2\n \n#endif\n\n#define RC_NORMALIZE if (Range < kTopValue) { RC_TEST; Range <<= 8; Code = (Code << 8) | RC_READ_BYTE; }\n\n#define IfBit0(p) RC_NORMALIZE; bound = (Range >> kNumBitModelTotalBits) * *(p); if (Code < bound)\n#define UpdateBit0(p) Range = bound; *(p) += (kBitModelTotal - *(p)) >> kNumMoveBits;\n#define UpdateBit1(p) Range -= bound; Code -= bound; *(p) -= (*(p)) >> kNumMoveBits;\n\n#define RC_GET_BIT2(p, mi, A0, A1) IfBit0(p) \\\n  { UpdateBit0(p); mi <<= 1; A0; } else \\\n  { UpdateBit1(p); mi = (mi + mi) + 1; A1; } \n  \n#define RC_GET_BIT(p, mi) RC_GET_BIT2(p, mi, ; , ;)               \n\n#define RangeDecoderBitTreeDecode(probs, numLevels, res) \\\n  { int i = numLevels; res = 1; \\\n  do { CProb *p = probs + res; RC_GET_BIT(p, res) } while(--i != 0); \\\n  res -= (1 << numLevels); }\n\n\n#define kNumPosBitsMax 4\n#define kNumPosStatesMax (1 << kNumPosBitsMax)\n\n#define kLenNumLowBits 3\n#define kLenNumLowSymbols (1 << kLenNumLowBits)\n#define kLenNumMidBits 3\n#define kLenNumMidSymbols (1 << kLenNumMidBits)\n#define kLenNumHighBits 8\n#define kLenNumHighSymbols (1 << kLenNumHighBits)\n\n#define LenChoice 0\n#define LenChoice2 (LenChoice + 1)\n#define LenLow (LenChoice2 + 1)\n#define LenMid (LenLow + (kNumPosStatesMax << kLenNumLowBits))\n#define LenHigh (LenMid + (kNumPosStatesMax << kLenNumMidBits))\n#define kNumLenProbs (LenHigh + kLenNumHighSymbols) \n\n\n#define kNumStates 12\n#define kNumLitStates 7\n\n#define kStartPosModelIndex 4\n#define kEndPosModelIndex 14\n#define kNumFullDistances (1 << (kEndPosModelIndex >> 1))\n\n#define kNumPosSlotBits 6\n#define kNumLenToPosStates 4\n\n#define kNumAlignBits 4\n#define kAlignTableSize (1 << kNumAlignBits)\n\n#define kMatchMinLen 2\n\n#define IsMatch 0\n#define IsRep (IsMatch + (kNumStates << kNumPosBitsMax))\n#define IsRepG0 (IsRep + kNumStates)\n#define IsRepG1 (IsRepG0 + kNumStates)\n#define IsRepG2 (IsRepG1 + kNumStates)\n#define IsRep0Long (IsRepG2 + kNumStates)\n#define PosSlot (IsRep0Long + (kNumStates << kNumPosBitsMax))\n#define SpecPos (PosSlot + (kNumLenToPosStates << kNumPosSlotBits))\n#define Align (SpecPos + kNumFullDistances - kEndPosModelIndex)\n#define LenCoder (Align + kAlignTableSize)\n#define RepLenCoder (LenCoder + kNumLenProbs)\n#define Literal (RepLenCoder + kNumLenProbs)\n\n#if Literal != LZMA_BASE_SIZE\nStopCompilingDueBUG\n#endif\n\nint LzmaDecodeProperties(CLzmaProperties *propsRes, const unsigned char *propsData, int size)\n{\n  unsigned char prop0;\n  if (size < LZMA_PROPERTIES_SIZE)\n    return LZMA_RESULT_DATA_ERROR;\n  prop0 = propsData[0];\n  if (prop0 >= (9 * 5 * 5))\n    return LZMA_RESULT_DATA_ERROR;\n  {\n    for (propsRes->pb = 0; prop0 >= (9 * 5); propsRes->pb++, prop0 -= (9 * 5));\n    for (propsRes->lp = 0; prop0 >= 9; propsRes->lp++, prop0 -= 9);\n    propsRes->lc = prop0;\n    /*\n    unsigned char remainder = (unsigned char)(prop0 / 9);\n    propsRes->lc = prop0 % 9;\n    propsRes->pb = remainder / 5;\n    propsRes->lp = remainder % 5;\n    */\n  }\n\n  #ifdef _LZMA_OUT_READ\n  {\n    int i;\n    propsRes->DictionarySize = 0;\n    for (i = 0; i < 4; i++)\n      propsRes->DictionarySize += (UInt32)(propsData[1 + i]) << (i * 8);\n    if (propsRes->DictionarySize == 0)\n      propsRes->DictionarySize = 1;\n  }\n  #endif\n  return LZMA_RESULT_OK;\n}\n\n#define kLzmaStreamWasFinishedId (-1)\n\nint LzmaDecode(CLzmaDecoderState *vs,\n    #ifdef _LZMA_IN_CB\n    ILzmaInCallback *InCallback,\n    #else\n    const unsigned char *inStream, SizeT inSize, SizeT *inSizeProcessed,\n    #endif\n    unsigned char *outStream, SizeT outSize, SizeT *outSizeProcessed)\n{\n  CProb *p = vs->Probs;\n  SizeT nowPos = 0;\n  Byte previousByte = 0;\n  UInt32 posStateMask = (1 << (vs->Properties.pb)) - 1;\n  UInt32 literalPosMask = (1 << (vs->Properties.lp)) - 1;\n  int lc = vs->Properties.lc;\n\n  #ifdef _LZMA_OUT_READ\n  \n  UInt32 Range = vs->Range;\n  UInt32 Code = vs->Code;\n  #ifdef _LZMA_IN_CB\n  const Byte *Buffer = vs->Buffer;\n  const Byte *BufferLim = vs->BufferLim;\n  #else\n  const Byte *Buffer = inStream;\n  const Byte *BufferLim = inStream + inSize;\n  #endif\n  int state = vs->State;\n  UInt32 rep0 = vs->Reps[0], rep1 = vs->Reps[1], rep2 = vs->Reps[2], rep3 = vs->Reps[3];\n  int len = vs->RemainLen;\n  UInt32 globalPos = vs->GlobalPos;\n  UInt32 distanceLimit = vs->DistanceLimit;\n\n  Byte *dictionary = vs->Dictionary;\n  UInt32 dictionarySize = vs->Properties.DictionarySize;\n  UInt32 dictionaryPos = vs->DictionaryPos;\n\n  Byte tempDictionary[4];\n\n  #ifndef _LZMA_IN_CB\n  *inSizeProcessed = 0;\n  #endif\n  *outSizeProcessed = 0;\n  if (len == kLzmaStreamWasFinishedId)\n    return LZMA_RESULT_OK;\n\n  if (dictionarySize == 0)\n  {\n    dictionary = tempDictionary;\n    dictionarySize = 1;\n    tempDictionary[0] = vs->TempDictionary[0];\n  }\n\n  if (len == kLzmaNeedInitId)\n  {\n    {\n      UInt32 numProbs = Literal + ((UInt32)LZMA_LIT_SIZE << (lc + vs->Properties.lp));\n      UInt32 i;\n      for (i = 0; i < numProbs; i++)\n        p[i] = kBitModelTotal >> 1; \n      rep0 = rep1 = rep2 = rep3 = 1;\n      state = 0;\n      globalPos = 0;\n      distanceLimit = 0;\n      dictionaryPos = 0;\n      dictionary[dictionarySize - 1] = 0;\n      #ifdef _LZMA_IN_CB\n      RC_INIT;\n      #else\n      RC_INIT(inStream, inSize);\n      #endif\n    }\n    len = 0;\n  }\n  while(len != 0 && nowPos < outSize)\n  {\n    UInt32 pos = dictionaryPos - rep0;\n    if (pos >= dictionarySize)\n      pos += dictionarySize;\n    outStream[nowPos++] = dictionary[dictionaryPos] = dictionary[pos];\n    if (++dictionaryPos == dictionarySize)\n      dictionaryPos = 0;\n    len--;\n  }\n  if (dictionaryPos == 0)\n    previousByte = dictionary[dictionarySize - 1];\n  else\n    previousByte = dictionary[dictionaryPos - 1];\n\n  #else /* if !_LZMA_OUT_READ */\n\n  int state = 0;\n  UInt32 rep0 = 1, rep1 = 1, rep2 = 1, rep3 = 1;\n  int len = 0;\n  const Byte *Buffer;\n  const Byte *BufferLim;\n  UInt32 Range;\n  UInt32 Code;\n\n  #ifndef _LZMA_IN_CB\n  *inSizeProcessed = 0;\n  #endif\n  *outSizeProcessed = 0;\n\n  {\n    UInt32 i;\n    UInt32 numProbs = Literal + ((UInt32)LZMA_LIT_SIZE << (lc + vs->Properties.lp));\n    for (i = 0; i < numProbs; i++)\n      p[i] = kBitModelTotal >> 1;\n  }\n  \n  #ifdef _LZMA_IN_CB\n  RC_INIT;\n  #else\n  RC_INIT(inStream, inSize);\n  #endif\n\n  #endif /* _LZMA_OUT_READ */\n\n  while(nowPos < outSize)\n  {\n    CProb *prob;\n    UInt32 bound;\n    int posState = (int)(\n        (nowPos \n        #ifdef _LZMA_OUT_READ\n        + globalPos\n        #endif\n        )\n        & posStateMask);\n\n    prob = p + IsMatch + (state << kNumPosBitsMax) + posState;\n    IfBit0(prob)\n    {\n      int symbol = 1;\n      UpdateBit0(prob)\n      prob = p + Literal + (LZMA_LIT_SIZE * \n        (((\n        (nowPos \n        #ifdef _LZMA_OUT_READ\n        + globalPos\n        #endif\n        )\n        & literalPosMask) << lc) + (previousByte >> (8 - lc))));\n\n      if (state >= kNumLitStates)\n      {\n        int matchByte;\n        #ifdef _LZMA_OUT_READ\n        UInt32 pos = dictionaryPos - rep0;\n        if (pos >= dictionarySize)\n          pos += dictionarySize;\n        matchByte = dictionary[pos];\n        #else\n        matchByte = outStream[nowPos - rep0];\n        #endif\n        do\n        {\n          int bit;\n          CProb *probLit;\n          matchByte <<= 1;\n          bit = (matchByte & 0x100);\n          probLit = prob + 0x100 + bit + symbol;\n          RC_GET_BIT2(probLit, symbol, if (bit != 0) break, if (bit == 0) break)\n        }\n        while (symbol < 0x100);\n      }\n      while (symbol < 0x100)\n      {\n        CProb *probLit = prob + symbol;\n        RC_GET_BIT(probLit, symbol)\n      }\n      previousByte = (Byte)symbol;\n\n      outStream[nowPos++] = previousByte;\n      #ifdef _LZMA_OUT_READ\n      if (distanceLimit < dictionarySize)\n        distanceLimit++;\n\n      dictionary[dictionaryPos] = previousByte;\n      if (++dictionaryPos == dictionarySize)\n        dictionaryPos = 0;\n      #endif\n      if (state < 4) state = 0;\n      else if (state < 10) state -= 3;\n      else state -= 6;\n    }\n    else             \n    {\n      UpdateBit1(prob);\n      prob = p + IsRep + state;\n      IfBit0(prob)\n      {\n        UpdateBit0(prob);\n        rep3 = rep2;\n        rep2 = rep1;\n        rep1 = rep0;\n        state = state < kNumLitStates ? 0 : 3;\n        prob = p + LenCoder;\n      }\n      else\n      {\n        UpdateBit1(prob);\n        prob = p + IsRepG0 + state;\n        IfBit0(prob)\n        {\n          UpdateBit0(prob);\n          prob = p + IsRep0Long + (state << kNumPosBitsMax) + posState;\n          IfBit0(prob)\n          {\n            #ifdef _LZMA_OUT_READ\n            UInt32 pos;\n            #endif\n            UpdateBit0(prob);\n            \n            #ifdef _LZMA_OUT_READ\n            if (distanceLimit == 0)\n            #else\n            if (nowPos == 0)\n            #endif\n              return LZMA_RESULT_DATA_ERROR;\n            \n            state = state < kNumLitStates ? 9 : 11;\n            #ifdef _LZMA_OUT_READ\n            pos = dictionaryPos - rep0;\n            if (pos >= dictionarySize)\n              pos += dictionarySize;\n            previousByte = dictionary[pos];\n            dictionary[dictionaryPos] = previousByte;\n            if (++dictionaryPos == dictionarySize)\n              dictionaryPos = 0;\n            #else\n            previousByte = outStream[nowPos - rep0];\n            #endif\n            outStream[nowPos++] = previousByte;\n            #ifdef _LZMA_OUT_READ\n            if (distanceLimit < dictionarySize)\n              distanceLimit++;\n            #endif\n\n            continue;\n          }\n          else\n          {\n            UpdateBit1(prob);\n          }\n        }\n        else\n        {\n          UInt32 distance;\n          UpdateBit1(prob);\n          prob = p + IsRepG1 + state;\n          IfBit0(prob)\n          {\n            UpdateBit0(prob);\n            distance = rep1;\n          }\n          else \n          {\n            UpdateBit1(prob);\n            prob = p + IsRepG2 + state;\n            IfBit0(prob)\n            {\n              UpdateBit0(prob);\n              distance = rep2;\n            }\n            else\n            {\n              UpdateBit1(prob);\n              distance = rep3;\n              rep3 = rep2;\n            }\n            rep2 = rep1;\n          }\n          rep1 = rep0;\n          rep0 = distance;\n        }\n        state = state < kNumLitStates ? 8 : 11;\n        prob = p + RepLenCoder;\n      }\n      {\n        int numBits, offset;\n        CProb *probLen = prob + LenChoice;\n        IfBit0(probLen)\n        {\n          UpdateBit0(probLen);\n          probLen = prob + LenLow + (posState << kLenNumLowBits);\n          offset = 0;\n          numBits = kLenNumLowBits;\n        }\n        else\n        {\n          UpdateBit1(probLen);\n          probLen = prob + LenChoice2;\n          IfBit0(probLen)\n          {\n            UpdateBit0(probLen);\n            probLen = prob + LenMid + (posState << kLenNumMidBits);\n            offset = kLenNumLowSymbols;\n            numBits = kLenNumMidBits;\n          }\n          else\n          {\n            UpdateBit1(probLen);\n            probLen = prob + LenHigh;\n            offset = kLenNumLowSymbols + kLenNumMidSymbols;\n            numBits = kLenNumHighBits;\n          }\n        }\n        RangeDecoderBitTreeDecode(probLen, numBits, len);\n        len += offset;\n      }\n\n      if (state < 4)\n      {\n        int posSlot;\n        state += kNumLitStates;\n        prob = p + PosSlot +\n            ((len < kNumLenToPosStates ? len : kNumLenToPosStates - 1) << \n            kNumPosSlotBits);\n        RangeDecoderBitTreeDecode(prob, kNumPosSlotBits, posSlot);\n        if (posSlot >= kStartPosModelIndex)\n        {\n          int numDirectBits = ((posSlot >> 1) - 1);\n          rep0 = (2 | ((UInt32)posSlot & 1));\n          if (posSlot < kEndPosModelIndex)\n          {\n            rep0 <<= numDirectBits;\n            prob = p + SpecPos + rep0 - posSlot - 1;\n          }\n          else\n          {\n            numDirectBits -= kNumAlignBits;\n            do\n            {\n              RC_NORMALIZE\n              Range >>= 1;\n              rep0 <<= 1;\n              if (Code >= Range)\n              {\n                Code -= Range;\n                rep0 |= 1;\n              }\n            }\n            while (--numDirectBits != 0);\n            prob = p + Align;\n            rep0 <<= kNumAlignBits;\n            numDirectBits = kNumAlignBits;\n          }\n          {\n            int i = 1;\n            int mi = 1;\n            do\n            {\n              CProb *prob3 = prob + mi;\n              RC_GET_BIT2(prob3, mi, ; , rep0 |= i);\n              i <<= 1;\n            }\n            while(--numDirectBits != 0);\n          }\n        }\n        else\n          rep0 = posSlot;\n        if (++rep0 == (UInt32)(0))\n        {\n          /* it's for stream version */\n          len = kLzmaStreamWasFinishedId;\n          break;\n        }\n      }\n\n      len += kMatchMinLen;\n      #ifdef _LZMA_OUT_READ\n      if (rep0 > distanceLimit) \n      #else\n      if (rep0 > nowPos)\n      #endif\n        return LZMA_RESULT_DATA_ERROR;\n\n      #ifdef _LZMA_OUT_READ\n      if (dictionarySize - distanceLimit > (UInt32)len)\n        distanceLimit += len;\n      else\n        distanceLimit = dictionarySize;\n      #endif\n\n      do\n      {\n        #ifdef _LZMA_OUT_READ\n        UInt32 pos = dictionaryPos - rep0;\n        if (pos >= dictionarySize)\n          pos += dictionarySize;\n        previousByte = dictionary[pos];\n        dictionary[dictionaryPos] = previousByte;\n        if (++dictionaryPos == dictionarySize)\n          dictionaryPos = 0;\n        #else\n        previousByte = outStream[nowPos - rep0];\n        #endif\n        len--;\n        outStream[nowPos++] = previousByte;\n      }\n      while(len != 0 && nowPos < outSize);\n    }\n  }\n  RC_NORMALIZE;\n\n  #ifdef _LZMA_OUT_READ\n  vs->Range = Range;\n  vs->Code = Code;\n  vs->DictionaryPos = dictionaryPos;\n  vs->GlobalPos = globalPos + (UInt32)nowPos;\n  vs->DistanceLimit = distanceLimit;\n  vs->Reps[0] = rep0;\n  vs->Reps[1] = rep1;\n  vs->Reps[2] = rep2;\n  vs->Reps[3] = rep3;\n  vs->State = state;\n  vs->RemainLen = len;\n  vs->TempDictionary[0] = tempDictionary[0];\n  #endif\n\n  #ifdef _LZMA_IN_CB\n  vs->Buffer = Buffer;\n  vs->BufferLim = BufferLim;\n  #else\n  *inSizeProcessed = (SizeT)(Buffer - inStream);\n  #endif\n  *outSizeProcessed = nowPos;\n  return LZMA_RESULT_OK;\n}\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-vdsl-fw/src/LzmaDecode.h",
    "content": "/* \n  LzmaDecode.h\n  LZMA Decoder interface\n\n  LZMA SDK 4.40 Copyright (c) 1999-2006 Igor Pavlov (2006-05-01)\n  http://www.7-zip.org/\n\n  LZMA SDK is licensed under two licenses:\n  1) GNU Lesser General Public License (GNU LGPL)\n  2) Common Public License (CPL)\n  It means that you can select one of these two licenses and \n  follow rules of that license.\n\n  SPECIAL EXCEPTION:\n  Igor Pavlov, as the author of this code, expressly permits you to \n  statically or dynamically link your code (or bind by name) to the \n  interfaces of this file without subjecting your linked code to the \n  terms of the CPL or GNU LGPL. Any modifications or additions \n  to this file, however, are subject to the LGPL or CPL terms.\n*/\n\n#ifndef __LZMADECODE_H\n#define __LZMADECODE_H\n\n#include \"LzmaTypes.h\"\n\n/* #define _LZMA_IN_CB */\n/* Use callback for input data */\n\n/* #define _LZMA_OUT_READ */\n/* Use read function for output data */\n\n/* #define _LZMA_PROB32 */\n/* It can increase speed on some 32-bit CPUs, \n   but memory usage will be doubled in that case */\n\n/* #define _LZMA_LOC_OPT */\n/* Enable local speed optimizations inside code */\n\n#ifdef _LZMA_PROB32\n#define CProb UInt32\n#else\n#define CProb UInt16\n#endif\n\n#define LZMA_RESULT_OK 0\n#define LZMA_RESULT_DATA_ERROR 1\n\n#ifdef _LZMA_IN_CB\ntypedef struct _ILzmaInCallback\n{\n  int (*Read)(void *object, const unsigned char **buffer, SizeT *bufferSize);\n} ILzmaInCallback;\n#endif\n\n#define LZMA_BASE_SIZE 1846\n#define LZMA_LIT_SIZE 768\n\n#define LZMA_PROPERTIES_SIZE 5\n\ntypedef struct _CLzmaProperties\n{\n  int lc;\n  int lp;\n  int pb;\n  #ifdef _LZMA_OUT_READ\n  UInt32 DictionarySize;\n  #endif\n}CLzmaProperties;\n\nint LzmaDecodeProperties(CLzmaProperties *propsRes, const unsigned char *propsData, int size);\n\n#define LzmaGetNumProbs(Properties) (LZMA_BASE_SIZE + (LZMA_LIT_SIZE << ((Properties)->lc + (Properties)->lp)))\n\n#define kLzmaNeedInitId (-2)\n\ntypedef struct _CLzmaDecoderState\n{\n  CLzmaProperties Properties;\n  CProb *Probs;\n\n  #ifdef _LZMA_IN_CB\n  const unsigned char *Buffer;\n  const unsigned char *BufferLim;\n  #endif\n\n  #ifdef _LZMA_OUT_READ\n  unsigned char *Dictionary;\n  UInt32 Range;\n  UInt32 Code;\n  UInt32 DictionaryPos;\n  UInt32 GlobalPos;\n  UInt32 DistanceLimit;\n  UInt32 Reps[4];\n  int State;\n  int RemainLen;\n  unsigned char TempDictionary[4];\n  #endif\n} CLzmaDecoderState;\n\n#ifdef _LZMA_OUT_READ\n#define LzmaDecoderInit(vs) { (vs)->RemainLen = kLzmaNeedInitId; }\n#endif\n\nint LzmaDecode(CLzmaDecoderState *vs,\n    #ifdef _LZMA_IN_CB\n    ILzmaInCallback *inCallback,\n    #else\n    const unsigned char *inStream, SizeT inSize, SizeT *inSizeProcessed,\n    #endif\n    unsigned char *outStream, SizeT outSize, SizeT *outSizeProcessed);\n\n#endif\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-vdsl-fw/src/LzmaTypes.h",
    "content": "/* \nLzmaTypes.h \n\nTypes for LZMA Decoder\n\nThis file written and distributed to public domain by Igor Pavlov.\nThis file is part of LZMA SDK 4.40 (2006-05-01)\n*/\n\n#ifndef __LZMATYPES_H\n#define __LZMATYPES_H\n\n#ifndef _7ZIP_BYTE_DEFINED\n#define _7ZIP_BYTE_DEFINED\ntypedef unsigned char Byte;\n#endif \n\n#ifndef _7ZIP_UINT16_DEFINED\n#define _7ZIP_UINT16_DEFINED\ntypedef unsigned short UInt16;\n#endif \n\n#ifndef _7ZIP_UINT32_DEFINED\n#define _7ZIP_UINT32_DEFINED\n#ifdef _LZMA_UINT32_IS_ULONG\ntypedef unsigned long UInt32;\n#else\ntypedef unsigned int UInt32;\n#endif\n#endif \n\n/* #define _LZMA_NO_SYSTEM_SIZE_T */\n/* You can use it, if you don't want <stddef.h> */\n\n#ifndef _7ZIP_SIZET_DEFINED\n#define _7ZIP_SIZET_DEFINED\n#ifdef _LZMA_NO_SYSTEM_SIZE_T\ntypedef UInt32 SizeT;\n#else\n#include <stddef.h>\ntypedef size_t SizeT;\n#endif\n#endif\n\n#endif\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-vdsl-fw/src/LzmaWrapper.c",
    "content": "/******************************************************************************\n**\n** FILE NAME    : LzmaWrapper.c\n** PROJECT      : bootloader\n** MODULES      : U-boot\n**\n** DATE         : 2 Nov 2006\n** AUTHOR       : Lin Mars\n** DESCRIPTION  : LZMA decoder support for U-boot 1.1.5\n** COPYRIGHT    :       Copyright (c) 2006\n**                      Infineon Technologies AG\n**                      Am Campeon 1-12, 85579 Neubiberg, Germany\n**\n**    This program is free software; you can redistribute it and/or modify\n**    it under the terms of the GNU General Public License as published by\n**    the Free Software Foundation; either version 2 of the License, or\n**    (at your option) any later version.\n**\n** HISTORY\n** $Date        $Author         $Comment\n** 2 Nov 2006   Lin Mars        init version which derived from LzmaTest.c from\n**                              LZMA v4.43 SDK\n** 24 May 2007\tLin Mars\tFix issue for multiple lzma_inflate involved\n*******************************************************************************/\n#include <stdio.h>\n#include <stdlib.h>\n#include <string.h>\n\n#include \"LzmaDecode.h\"\n#include \"LzmaWrapper.h\"\n\n#if defined(DEBUG_ENABLE_BOOTSTRAP_PRINTF) || !defined(CFG_BOOTSTRAP_CODE)\nstatic const char *kCantReadMessage = \"Can not read from source buffer\";\nstatic const char *kCantAllocateMessage = \"Not enough buffer for decompression\";\n#endif\n\nstatic size_t rpos=0, dpos=0;\n\nstatic int MyReadFileAndCheck(unsigned char *src, void *dest, size_t size)\n{\n  if (size == 0)\n    return 0;\n  memcpy(dest, src + rpos, size);\n  rpos += size;\n  return 1;\n}\n\nint lzma_inflate(unsigned char *source, int s_len, unsigned char *dest, int *d_len)\n{\n  /* We use two 32-bit integers to construct 64-bit integer for file size.\n     You can remove outSizeHigh, if you don't need >= 4GB supporting,\n     or you can use UInt64 outSize, if your compiler supports 64-bit integers*/\n  UInt32 outSize = 0;\n  UInt32 outSizeHigh = 0;\n  SizeT outSizeFull;\n  unsigned char *outStream;\n  \n  int waitEOS = 1; \n  /* waitEOS = 1, if there is no uncompressed size in headers, \n   so decoder will wait EOS (End of Stream Marker) in compressed stream */\n\n  SizeT compressedSize;\n  unsigned char *inStream;\n\n  CLzmaDecoderState state;  /* it's about 24-80 bytes structure, if int is 32-bit */\n  unsigned char properties[LZMA_PROPERTIES_SIZE];\n\n  int res;\n\n  rpos=0; dpos=0;\n\n  if (sizeof(UInt32) < 4)\n  {\n#if defined(DEBUG_ENABLE_BOOTSTRAP_PRINTF) || !defined(CFG_BOOTSTRAP_CODE)\n    printf(\"LZMA decoder needs correct UInt32\\n\");\n#endif\n    return LZMA_RESULT_DATA_ERROR;\n  }\n\n  {\n    long length=s_len;\n    if ((long)(SizeT)length != length)\n    {\n#if defined(DEBUG_ENABLE_BOOTSTRAP_PRINTF) || !defined(CFG_BOOTSTRAP_CODE)\n      printf(\"Too big compressed stream\\n\");\n#endif\n      return LZMA_RESULT_DATA_ERROR;\n    }\n    compressedSize = (SizeT)(length - (LZMA_PROPERTIES_SIZE + 8));\n  }\n\n  /* Read LZMA properties for compressed stream */\n\n  if (!MyReadFileAndCheck(source, properties, sizeof(properties)))\n  {\n#if defined(DEBUG_ENABLE_BOOTSTRAP_PRINTF) || !defined(CFG_BOOTSTRAP_CODE)\n    printf(\"%s\\n\", kCantReadMessage);\n#endif\n    return LZMA_RESULT_DATA_ERROR;\n  }\n\n  /* Read uncompressed size */\n  {\n    int i;\n    for (i = 0; i < 8; i++)\n    {\n      unsigned char b;\n      if (!MyReadFileAndCheck(source, &b, 1))\n      {\n#if defined(DEBUG_ENABLE_BOOTSTRAP_PRINTF) || !defined(CFG_BOOTSTRAP_CODE)\n        printf(\"%s\\n\", kCantReadMessage);\n#endif\n        return LZMA_RESULT_DATA_ERROR;\n      }\n      if (b != 0xFF)\n        waitEOS = 0;\n      if (i < 4)\n        outSize += (UInt32)(b) << (i * 8);\n      else\n        outSizeHigh += (UInt32)(b) << ((i - 4) * 8);\n    }\n    \n    if (waitEOS)\n    {\n#if defined(DEBUG_ENABLE_BOOTSTRAP_PRINTF) || !defined(CFG_BOOTSTRAP_CODE)\n      printf(\"Stream with EOS marker is not supported\");\n#endif\n      return LZMA_RESULT_DATA_ERROR;\n    }\n    outSizeFull = (SizeT)outSize;\n    if (sizeof(SizeT) >= 8)\n      outSizeFull |= (((SizeT)outSizeHigh << 16) << 16);\n    else if (outSizeHigh != 0 || (UInt32)(SizeT)outSize != outSize)\n    {\n#if defined(DEBUG_ENABLE_BOOTSTRAP_PRINTF) || !defined(CFG_BOOTSTRAP_CODE)\n      printf(\"Too big uncompressed stream\");\n#endif\n      return LZMA_RESULT_DATA_ERROR;\n    }\n  }\n\n  /* Decode LZMA properties and allocate memory */\n  if (LzmaDecodeProperties(&state.Properties, properties, LZMA_PROPERTIES_SIZE) != LZMA_RESULT_OK)\n  {\n#if defined(DEBUG_ENABLE_BOOTSTRAP_PRINTF) || !defined(CFG_BOOTSTRAP_CODE)\n    printf(\"Incorrect stream properties\");\n#endif\n    return LZMA_RESULT_DATA_ERROR;\n  }\n  state.Probs = (CProb *)malloc(LzmaGetNumProbs(&state.Properties) * sizeof(CProb));\n\n  if (outSizeFull == 0)\n    outStream = 0;\n  else\n  {\n    if (outSizeFull > *d_len)\n      outStream = 0;\n    else\n      outStream = dest;\n  }\n\n  if (compressedSize == 0)\n    inStream = 0;\n  else\n  {\n    if ((compressedSize+rpos) > s_len )\n      inStream = 0;\n    else\n      inStream = source + rpos;\n  }\n\n  if (state.Probs == 0 \n    || (outStream == 0 && outSizeFull != 0)\n    || (inStream == 0 && compressedSize != 0)\n    )\n  {\n    free(state.Probs);\n#if defined(DEBUG_ENABLE_BOOTSTRAP_PRINTF) || !defined(CFG_BOOTSTRAP_CODE)\n    printf(\"%s\\n\", kCantAllocateMessage);\n#endif\n    return LZMA_RESULT_DATA_ERROR;\n  }\n\n  /* Decompress */\n  {\n    SizeT inProcessed;\n    SizeT outProcessed;\n    res = LzmaDecode(&state,\n      inStream, compressedSize, &inProcessed,\n      outStream, outSizeFull, &outProcessed);\n    if (res != 0)\n    {\n#if defined(DEBUG_ENABLE_BOOTSTRAP_PRINTF) || !defined(CFG_BOOTSTRAP_CODE)\n      printf(\"\\nDecoding error = %d\\n\", res);\n#endif\n      res = 1;\n    }\n    else\n    {\n      *d_len = outProcessed;\n    }\n  }\n\n  free(state.Probs);\n  return res;\n}\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-vdsl-fw/src/LzmaWrapper.h",
    "content": "/******************************************************************************\n**\n** FILE NAME    : LzmaWrapper.h\n** PROJECT      : bootloader\n** MODULES      : U-boot\n**\n** DATE         : 2 Nov 2006\n** AUTHOR       : Lin Mars\n** DESCRIPTION  : LZMA decoder support for U-boot 1.1.5\n** COPYRIGHT    :       Copyright (c) 2006\n**                      Infineon Technologies AG\n**                      Am Campeon 1-12, 85579 Neubiberg, Germany\n**\n**    This program is free software; you can redistribute it and/or modify\n**    it under the terms of the GNU General Public License as published by\n**    the Free Software Foundation; either version 2 of the License, or\n**    (at your option) any later version.\n**\n** HISTORY\n** $Date        $Author         $Comment\n** 2 Nov 2006   Lin Mars        init version which derived from LzmaTest.c from\n**                              LZMA v4.43 SDK\n*******************************************************************************/\n#ifndef  __LZMA_WRAPPER_H__\n#define  __LZMA_WRAPPER_H__\n\n#ifndef LZMA_RESULT_OK\n#define LZMA_RESULT_OK 0\n#endif\n#ifndef LZMA_RESULT_DATA_ERROR\n#define LZMA_RESULT_DATA_ERROR 1\n#endif\n\nextern int lzma_inflate(unsigned char *source, int s_len, unsigned char *dest, int *d_len);\n\n#endif /*__LZMA_WRAPPER_H__*/\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-vdsl-fw/src/Makefile",
    "content": "PROG=w921v_fw_cutter\nOBJS=w921v_fw_cutter.c LzmaDecode.c LzmaWrapper.c\n\nall: $(PROG) \n\n$(PROG): $(OBJS)\n\t$(CC) $(CFLAGS) $(LDFLAGS) $^ -o $@\n\nclean:\n\trm *.o $(PROG)\n\n%.o: %.c\n\t$(CC) $(CFLAGS) -c $^ -o $@\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-vdsl-fw/src/vdsl_fw_install.sh",
    "content": "#!/bin/sh\nFW=\"/tmp/firmware-speedport-w921v-1.46.000.bin\"\nURL=\"https://www.telekom.de/hilfe/downloads/firmware-speedport-w-921v-1.48.000.bin\"\nFW_TAPI=\"vr9_tapi_fw.bin\"\nFW_DSL=\"vr9_dsl_fw_annex_b.bin\"\nMD5_FW=\"afa25146119daced87f67c9b66ef94b3\"\nMD5_TAPI=\"57f2d07f59e11250ce1219bad99c1eda\"\nMD5_DSL=\"655442e31deaa42c9c68944869361ec0\"\n\n[ -f /lib/firmware/vdsl.bin ] && exit 0\n\n[ -z \"$1\" ] || URL=$1\n\n[ -f \"${FW}\" ] || {\n\techo \"${FW} does not exist. Try to Download it ? (y/N)\"\n\tread -n 1 R\n\techo \"\"\n\t[ \"$R\" = \"y\" ] || {\n\t\techo \"Please manually download the firmware from ${URL} and copy the file to ${FW}\"\n\t\techo \"See also https://xdarklight.github.io/lantiq-xdsl-firmware-info/ for alternatives\"\n\t\texit 1\n\t}\n\techo \"Download w921v Firmware\"\n\twget \"${URL}\" -O \"${FW}\"\n\t[ $? -eq 0 -a -f \"${FW}\" ] || exit 1\n}\n\nF=$(md5sum -b ${FW} | cut -d\" \" -f1)\n[ \"$F\" = \"${MD5_FW}\" ] || {\n\techo \"Failed to verify Firmware MD5\"\n\texit 1\n}\n\ncd /tmp\necho \"Unpack and decompress w921v Firmware\"\n\nw921v_fw_cutter\n[ $? -eq 0 ] || exit 1\n\nT=$(md5sum -b ${FW_TAPI} | cut -d\" \" -f1)\nD=$(md5sum -b ${FW_DSL} | cut -d\" \" -f1)\n\n[ \"$T\" = \"${MD5_TAPI}\" -a \"$D\" = \"${MD5_DSL}\" ] || {\n\techo \"Failed to verify MD5\"\n\texit 1\n}\n\ncp ${FW_TAPI} ${FW_DSL} /lib/firmware/\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-vdsl-fw/src/w921v_fw_cutter.c",
    "content": "/*\n *   This program is free software; you can redistribute it and/or modify\n *   it under the terms of the GNU General Public License as published by\n *   the Free Software Foundation; version 2 of the License\n *\n *   This program is distributed in the hope that it will be useful,\n *   but WITHOUT ANY WARRANTY; without even the implied warranty of\n *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n *   GNU General Public License for more details.\n *\n *   You should have received a copy of the GNU General Public License\n *   along with this program; if not, write to the Free Software\n *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.\n *\n *   Copyright (C) 2012 John Crispin <blogic@openwrt.org>\n */\n\n#include <sys/types.h>\n#include <sys/stat.h>\n#include <unistd.h>\n#include <stdlib.h>\n#include <stdio.h>\n#include <string.h>\n#include <errno.h>\n#include <fcntl.h>\n\n#include \"LzmaWrapper.h\"\n\n#define FW_NAME\t\t\"/tmp/firmware-speedport-w-921v-1.48.000.bin\"\n\n#define MAGIC\t\t0x50\n#define MAGIC_SZ\t0x3FFC00\n#if __BYTE_ORDER == __LITTLE_ENDIAN\n#define MAGIC_PART\t0x12345678\n#define MAGIC_LZMA\t0x8000005D\n#define MAGIC_ANNEX_B\t0x3C\n#define MAGIC_TAPI\t0x5A\n#else\n#define MAGIC_PART\t0x78563412\n#define MAGIC_LZMA\t0x5D000080\n#define MAGIC_ANNEX_B\t0x3C000000\n#define MAGIC_TAPI\t0x5A000000\n#endif\n\n\nconst char* part_type(unsigned int id)\n{\n\tswitch(id) {\n\tcase MAGIC_ANNEX_B:\n\t\treturn \"/tmp/vr9_dsl_fw_annex_b.bin\";\n\tcase MAGIC_TAPI:\n\t\treturn \"/tmp/vr9_tapi_fw.bin\";\n\t}\n\tprintf(\"\\tUnknown lzma type 0x%02X\\n\", id);\n\treturn \"/tmp/unknown.lzma\";\n}\n\nint main(int argc, char **argv)\n{\n\tstruct stat s;\n\tunsigned char *buf_orig;\n\tunsigned int *buf;\n\tint buflen;\n\tint fd;\n\tint i;\n\tint err;\n\tint start = 0, end = 0;\n\n\tprintf(\"Arcadyan Firmware cutter v0.1\\n\");\n\tprintf(\"-----------------------------\\n\");\n\tprintf(\"This tool extracts the different parts of an arcadyan firmware update file\\n\");\n\tprintf(\"This tool is for private use only. The Firmware that gets extracted has a license that forbids redistribution\\n\");\n\tprintf(\"Please only run this if you understand the risks\\n\\n\");\n\tprintf(\"I understand the risks ? (y/N)\\n\");\n\n\tif (getchar() != 'y')\n\t\treturn -1;\n\n\tif (stat(FW_NAME, &s) != 0) {\n\t\tprintf(\"Failed to find %s\\n\", FW_NAME);\n\t\tprintf(\"Ask Google or try https://www.telekom.de/hilfe/downloads/firmware-speedport-w-921v-1.48.000.bin\\n\");\n\t\treturn -1;\n\t}\n\n\tbuf_orig = malloc(s.st_size);\n\tbuf = malloc(s.st_size);\n\tif (!buf_orig || !buf) {\n\t\tprintf(\"Failed to alloc %d bytes\\n\", s.st_size);\n\t\treturn -1;\n\t}\n\n\tfd = open(FW_NAME, O_RDONLY);\n\tif (fd < 0) {\n\t\tprintf(\"Unable to open %s\\n\", FW_NAME);\n\t\treturn -1;\n\t}\n\n\n\tbuflen = read(fd, buf_orig, s.st_size);\n\tclose(fd);\n\tif (buflen != s.st_size) {\n\t\tprintf(\"Loaded %d instead of %d bytes inside %s\\n\", buflen, s.st_size, FW_NAME);\n\t\treturn -1;\n\t}\n\n\t/* <magic> */\n\tbuf_orig++;\n\tbuflen -= 1;\n\tfor (i = 0; i < MAGIC_SZ; i++) {\n\t\tif ((i % 16) < 3)\n\t\t\tbuf_orig[i] = buf_orig[i + 16] ^ MAGIC;\n\t\telse\n\t\t\tbuf_orig[i] = buf_orig[i] ^ MAGIC;\n\t}\n\tbuflen -= 3;\n\tmemmove(&buf_orig[MAGIC_SZ], &buf_orig[MAGIC_SZ + 3], buflen - MAGIC_SZ);\n\tmemcpy(buf, buf_orig, s.st_size);\n\n\t/* </magic> */\n\tdo {\n\t\tif (buf[end] == MAGIC_PART) {\n\t\t\tend += 2;\n\t\t\tprintf(\"Found partition at 0x%08X with size %d\\n\",\n\t\t\t\tstart * sizeof(unsigned int),\n\t\t\t\t(end - start) * sizeof(unsigned int));\n\t\t\tif (buf[start] == MAGIC_LZMA) {\n\t\t\t\tint dest_len = 1024 * 1024;\n\t\t\t\tint len = buf[end - 3];\n\t\t\t\tunsigned int id = buf[end - 6];\n\t\t\t\tconst char *type = part_type(id);\n\t\t\t\tunsigned char *dest;\n\n\t\t\t\tdest = malloc(dest_len);\n\t\t\t\tif (!dest) {\n\t\t\t\t\tprintf(\"Failed to alloc dest buffer\\n\");\n\t\t\t\t\treturn -1;\n\t\t\t\t}\n\n\t\t\t\tif (lzma_inflate((unsigned char*)&buf[start], len, dest, &dest_len)) {\n\t\t\t\t\tprintf(\"Failed to decompress data\\n\");\n\t\t\t\t\treturn -1;\n\t\t\t\t}\n\n\t\t\t\tfd = creat(type, S_IRUSR | S_IWUSR);\n\t\t\t\tif (fd != -1) {\n\t\t\t\t\tif (write(fd, dest, dest_len) != dest_len)\n\t\t\t\t\t\tprintf(\"\\tFailed to write %d bytes\\n\", dest_len);\n\t\t\t\t\telse\n\t\t\t\t\t\tprintf(\"\\tWrote %d bytes to %s\\n\", dest_len, type);\n\t\t\t\t\tclose(fd);\n\t\t\t\t} else {\n\t\t\t\t\tprintf(\"\\tFailed to open %s\\n\", type);\n\t\t\t\t}\n\t\t\t\tfree(dest);\n\t\t\t} else {\n\t\t\t\tprintf(\"\\tThis is not lzma\\n\");\n\t\t\t}\n\t\t\tstart = end;\n\t\t} else {\n\t\t\tend++;\n\t\t}\n\t} while(end < buflen / sizeof(unsigned int));\n\n\treturn 0;\n}\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-vdsl-mei/Makefile",
    "content": "# Copyright (C) 2012 OpenWrt.org\n# Copyright (C) 2015-2016 Lantiq Beteiligungs GmbH & Co KG.\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n\ninclude $(TOPDIR)/rules.mk\ninclude $(INCLUDE_DIR)/kernel.mk\n\nPKG_NAME:=ltq-vdsl-vr9-mei\nPKG_VERSION:=1.5.17.6\nPKG_RELEASE:=6\n\nPKG_BASE_NAME:=drv_mei_cpe\nPKG_SOURCE:=$(PKG_BASE_NAME)-$(PKG_VERSION).tar.gz\nPKG_BUILD_DIR:=$(KERNEL_BUILD_DIR)/$(PKG_BASE_NAME)-$(PKG_VERSION)\nPKG_SOURCE_URL:=@OPENWRT\nPKG_HASH:=94f6904364348b7f74087e721968abc28b2564fb9bd8899aa930d36490387662\nPKG_FIXUP:=autoreconf\nPKG_FLAGS:=nonshared\nPKG_MAINTAINER:=John Crispin <john@phrozen.org>\nPKG_LICENSE:=GPL-2.0 BSD-2-Clause\nPKG_LICENSE_FILES:=LICENSE\nPKG_EXTMOD_SUBDIRS:=src\n\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine KernelPackage/ltq-vdsl-vr9-mei\n  TITLE:=mei driver for vdsl\n  SECTION:=sys\n  SUBMENU:=Network Devices\n  DEPENDS:=@TARGET_lantiq_xrx200 +kmod-ltq-ifxos +kmod-ltq-vectoring\n  FILES:=$(PKG_BUILD_DIR)/src/drv_mei_cpe.ko\n  AUTOLOAD:=$(call AutoLoad,50,drv_mei_cpe)\nendef\n\ndefine KernelPackage/ltq-vdsl-vr9-mei/description\n\tLantiq MEI CPE Kernel Module Driver\nendef\n\n\ndefine Package/ltq-vdsl-mei-test\n  SECTION:=net\n  CATEGORY:=Network\n  TITLE:=Lantiq mei driver test tool\n  URL:=http://www.lantiq.com/\n  DEPENDS:=@TARGET_lantiq_xrx200\nendef\n\ndefine Package/ltq-vdsl-mei-test/description\n\tUserland tool to directly control the mei driver, this is only needed\n\tfor test and development purposes.\nendef\n\nMAKE_FLAGS += \\\n\t$(KERNEL_MAKE_FLAGS) \\\n\tSHELL=\"$(BASH)\"\n\n# ltq-vdsl-app uses a header provided by the MEI driver which has some\n# conditionals.\n# Define the conditionals here to have the same view on both sides. If you\n# change them, you need to change them for the ltq-vdsl-app as well\nMEI_DRV_CFLAGS = \\\n\t-DMEI_DRV_ATM_PTM_INTERFACE_ENABLE=1 \\\n\t-DMEI_SUPPORT_DEBUG_STREAMS=1 \\\n\t-DMEI_SUPPORT_OPTIMIZED_FW_DL=1\n\nCONFIGURE_ARGS += \\\n\t--enable-kernelincl=\"$(LINUX_DIR)/include\" \\\n\t--enable-device=vr9 \\\n\t--with-max-device=1 \\\n\t--with-lines-per-device=1 \\\n\t--enable-debug \\\n\t--enable-error_print \\\n\t--enable-ifxos-include=\"-I$(STAGING_DIR)/usr/include/ifxos/\" \\\n\t--enable-ifxos-library=\"-L$(STAGING_DIR)/usr/lib\" \\\n\t--enable-add_drv_cflags=\"$(MEI_DRV_CFLAGS)\" \\\n\t--enable-linux-26 \\\n\t--enable-kernelbuild=\"$(LINUX_DIR)\" \\\n\t--enable-drv_test_appl=yes \\\n\tARCH=$(LINUX_KARCH)\n\ndefine Build/InstallDev\n\t$(INSTALL_DIR) $(1)/usr/include/vdsl\n\t$(CP) $(PKG_BUILD_DIR)/src/drv_mei_cpe_api_intern.h $(1)/usr/include/vdsl/\n\t$(CP) $(PKG_BUILD_DIR)/src/drv_mei_cpe_api_atm_ptm_intern.h $(1)/usr/include/vdsl/\n\t$(CP) $(PKG_BUILD_DIR)/src/drv_mei_cpe_interface.h $(1)/usr/include/vdsl\n\t$(CP) $(PKG_BUILD_DIR)/src/drv_mei_cpe_config.h $(1)/usr/include/vdsl/\n\t$(CP) $(PKG_BUILD_DIR)/src/cmv_message_format.h $(1)/usr/include/vdsl/\nendef\n\n$(eval $(call KernelPackage,ltq-vdsl-vr9-mei))\n\ndefine Package/ltq-vdsl-mei-test/install\n\t$(INSTALL_DIR) $(1)/bin\n\t$(INSTALL_BIN) $(PKG_BUILD_DIR)/src/mei_cpe_drv_test $(1)/bin\nendef\n\n$(eval $(call BuildPackage,ltq-vdsl-mei-test))\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-vdsl-mei/patches/001-fix-compile.patch",
    "content": "--- a/src/drv_mei_cpe_linux.h\n+++ b/src/drv_mei_cpe_linux.h\n@@ -31,6 +31,9 @@\n #include <linux/module.h>\n \n #include <linux/sched.h>\n+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,11,0))\n+#include <linux/sched/signal.h>\n+#endif\n #include <linux/interrupt.h>\n #include <linux/version.h>\n #include <linux/crc32.h>\n@@ -121,7 +124,11 @@ typedef int (*MEI_RequestIrq_WrapLinux_t\n /**\n    Function typedef for the Linux free_irq()\n */\n+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,12,0))\n+typedef const void *(*MEI_FreeIrq_WrapLinux_t)( unsigned int usedIrq,\n+#else\n typedef void (*MEI_FreeIrq_WrapLinux_t)( unsigned int usedIrq,\n+#endif\n                                            void *usedDevId );\n \n \n--- a/src/drv_mei_cpe_linux.c\n+++ b/src/drv_mei_cpe_linux.c\n@@ -129,7 +129,7 @@ static int MEI_module_init(void);\n #endif\n \n #if (MEI_DRV_LKM_ENABLE == 1) && (MEI_SUPPORT_DEVICE_VR10_320 != 1)\n-static void __exit MEI_module_exit(void);\n+static void MEI_module_exit(void);\n #else\n static void MEI_module_exit(void);\n #endif\n@@ -2188,7 +2188,7 @@ static int MEI_module_init (void)\n    Called by the kernel.\n */\n #if (MEI_DRV_LKM_ENABLE == 1) && (MEI_SUPPORT_DEVICE_VR10_320 != 1)\n-static void __exit MEI_module_exit (void)\n+static void MEI_module_exit (void)\n #else\n static void MEI_module_exit (void)\n #endif\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-vdsl-mei/patches/010-warnings.patch",
    "content": "--- a/src/drv_mei_cpe_api.h\n+++ b/src/drv_mei_cpe_api.h\n@@ -1000,7 +1000,7 @@ typedef struct MEI_dev_s\n #if ( defined(MEI_DRVOS_HAVE_DRV_SELECT) && (MEI_DRVOS_HAVE_DRV_SELECT == 1) )\n    /** support for select() */\n    IFX_boolean_t         bNfcNeedWakeUp;\n-   MEI_DRVOS_event_t     selNfcWakeupList;\n+   IFXOS_drvSelectQueue_t     selNfcWakeupList;\n #endif\n \n    /** list of all open instances which can receive NFC's, EVT's ALM's */\n--- a/src/drv_mei_cpe_linux.c\n+++ b/src/drv_mei_cpe_linux.c\n@@ -1302,9 +1302,9 @@ static unsigned int MEI_Poll (struct fil\n    }\n \n    MEI_DRVOS_SelectQueueAddTask(\n-               (MEI_DRVOS_select_OSArg_t*) filp,\n-               (MEI_DRVOS_selectQueue_t*)  &(pMeiDev->selNfcWakeupList),\n-               (MEI_DRVOS_selectTable_t*)  wait);\n+               filp,\n+               &(pMeiDev->selNfcWakeupList),\n+               wait);\n \n    if (pDynNfc->pRecvDataCntrl[pDynNfc->rdIdxRd].bufCtrl != MEI_RECV_BUF_CTRL_FREE)      /* buffer in use */\n    {\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-vdsl-mei/patches/020-not-leak-cflags.patch",
    "content": "--- a/src/Makefile.am\n+++ b/src/Makefile.am\n@@ -213,8 +213,7 @@ drv_mei_cpe_common_cflags = $(AM_CFLAGS)\n else\n \n drv_mei_cpe_common_cflags = \\\n-\t$(AM_CFLAGS) -D__KERNEL__ -DLINUX -D__linux__ -DMODULE -DEXPORT_SYMTAB \\\n-\t-pipe -Wimplicit -Wunused -Wuninitialized -Wsign-compare -Wstrict-aliasing\n+\t-D__KERNEL__ -DLINUX -D__linux__ -DMODULE -DEXPORT_SYMTAB\n \n endif\n \n@@ -354,7 +353,7 @@ drv_mei_cpe.ko: $(drv_mei_cpe_SOURCES)\n \t@echo -e \"# drv_mei_cpe: Generated to build Linux 2.6.x kernel object\" > $(PWD)/Kbuild\n \t@echo -e \"obj-m := $(subst .ko,.o,$@)\"\t\t\t>> $(PWD)/Kbuild\n \t@echo -e \"$(subst .ko,,$@)-y := $(drv_mei_cpe_OBJS)\"\t>> $(PWD)/Kbuild\n-\t@echo -e \"EXTRA_CFLAGS := $(CFLAGS) $(drv_mei_cpe_CFLAGS) -I@abs_srcdir@ -I@abs_srcdir@/auto_header $(IFXOS_INCLUDE_PATH)\" >> $(PWD)/Kbuild\n+\t@echo -e \"EXTRA_CFLAGS := $(drv_mei_cpe_CFLAGS) -I@abs_srcdir@ -I@abs_srcdir@/auto_header $(IFXOS_INCLUDE_PATH)\" >> $(PWD)/Kbuild\n \t$(MAKE) ARCH=@KERNEL_ARCH@ -C @KERNEL_BUILD_PATH@ O=@KERNEL_BUILD_PATH@ M=$(PWD) modules\n \n clean-generic:\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-vdsl-mei/patches/030-no-static-linking.patch",
    "content": "This removes -static compile option. The -static option tells GCC to\nlink this statically with the libc, which we do not want in OpenWrt. We\nwant to link everything dynamically to the libc. This fixes a compile\nproblem with glibc.\n\n--- a/src/Makefile.am\n+++ b/src/Makefile.am\n@@ -198,10 +198,10 @@ AM_CFLAGS = -Wall -Wimplicit -Wunused -W\n \n if IFXOS_ENABLE\n AM_LDFLAGS= \\\n-\t-Bstatic -dn -static @IFXOS_LIBRARY_PATH@\n+\t-Bstatic -dn @IFXOS_LIBRARY_PATH@\n else\n AM_LDFLAGS= \\\n-\t-Bstatic -dn -static\n+\t-Bstatic -dn\n endif\n \n #\n@@ -304,7 +304,7 @@ mei_cpe_appl_ldflags= $(ADD_APPL_LDFLAGS\n else\n if TARGET_ADM5120_MIPSEL\n mei_cpe_appl_cflags =  -O1 -g\n-mei_cpe_appl_ldflags = -static\n+mei_cpe_appl_ldflags =\n else\n mei_cpe_appl_cflags =  -DPPC\n endif\n@@ -318,7 +318,7 @@ mei_cpe_drv_test_CPPFLAGS = -I@srcdir@\\\n mei_cpe_drv_test_CFLAGS = $(mei_cpe_app_common_cflags) \\\n \t\t\t\t$(mei_cpe_appl_cflags) $(MEI_DRV_TARGET_OPTIONS)\n \n-mei_cpe_drv_test_LDFLAGS = $(mei_cpe_appl_ldflags) -Bstatic -dn -static @IFXOS_LIBRARY_PATH@\n+mei_cpe_drv_test_LDFLAGS = $(mei_cpe_appl_ldflags) -Bstatic -dn @IFXOS_LIBRARY_PATH@\n \n mei_cpe_drv_test_LDADD = -lifxos\n endif\n@@ -333,7 +333,7 @@ mei_cpe_drv_dbg_strm_dmp_CPPFLAGS = -I@s\n \t\t\t\t-I@KERNEL_INCL_PATH@ $(IFXOS_INCLUDE_PATH)\n mei_cpe_drv_dbg_strm_dmp_CFLAGS = $(mei_cpe_app_common_cflags) \\\n \t\t\t\t$(mei_cpe_appl_cflags) $(MEI_DRV_TARGET_OPTIONS)\n-mei_cpe_drv_dbg_strm_dmp_LDFLAGS = $(mei_cpe_appl_ldflags) -Bstatic -dn -static @IFXOS_LIBRARY_PATH@\n+mei_cpe_drv_dbg_strm_dmp_LDFLAGS = $(mei_cpe_appl_ldflags) -Bstatic -dn @IFXOS_LIBRARY_PATH@\n mei_cpe_drv_dbg_strm_dmp_LDADD = -lifxos\n \n # linux 2.6 kernel object - dummy to force dependencies\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-vdsl-mei/patches/100-compat.patch",
    "content": "--- a/src/drv_mei_cpe_common.c\n+++ b/src/drv_mei_cpe_common.c\n@@ -19,7 +19,6 @@\n /* get at first the driver configuration */\n #include \"drv_mei_cpe_config.h\"\n \n-#include \"ifx_types.h\"\n #include \"drv_mei_cpe_os.h\"\n #include \"drv_mei_cpe_dbg.h\"\n \n--- a/src/drv_mei_cpe_linux.h\n+++ b/src/drv_mei_cpe_linux.h\n@@ -60,12 +60,6 @@\n #include <linux/poll.h>\n #include <linux/types.h>\n \n-#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,10,0))\n-   #include <asm/ifx/ifx_types.h>\n-#else\n-   #include <ifx_types.h>\n-#endif\n-\n #endif /* #if (MEI_DRV_IFXOS_ENABLE == 0)*/\n \n #include <linux/dma-mapping.h>\n--- a/src/drv_mei_cpe_linux.c\n+++ b/src/drv_mei_cpe_linux.c\n@@ -114,6 +114,8 @@\n \n #include \"drv_mei_cpe_api_atm_ptm_intern.h\"\n \n+#include <lantiq_soc.h>\n+\n /* ===================================\n    extern function declarations\n    =================================== */\n@@ -220,6 +222,8 @@ static void MEI_NlSendMsg(IFX_char_t* pM\n /* Local variables (LINUX)             */\n /* =================================== */\n static IFX_uint8_t major_number = 0;\n+static struct class *mei_class;\n+static dev_t mei_devt;\n #ifdef MODULE\n #if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0))\n MODULE_PARM(major_number, \"b\");\n@@ -1479,7 +1483,11 @@ struct proc_entry {\n    char name[32];\n    proc_rd_callback_t rd;\n    proc_wr_callback_t wr;\n+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5,6,0))\n    struct file_operations ops;\n+#else\n+   struct proc_ops ops;\n+#endif\n    int entity;\n };\n \n@@ -1869,6 +1877,7 @@ static int mei_proc_single_open(struct i\n static void mei_proc_entry_create(struct proc_dir_entry *parent_node,\n                                   struct proc_entry *proc_entry)\n {\n+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5,6,0))\n    memset(&proc_entry->ops, 0, sizeof(struct file_operations));\n    proc_entry->ops.owner = THIS_MODULE;\n \n@@ -1879,6 +1888,17 @@ static void mei_proc_entry_create(struct\n    proc_entry->ops.llseek = seq_lseek;\n    if (proc_entry->wr)\n       proc_entry->ops.write = proc_entry->wr;\n+#else\n+   memset(&proc_entry->ops, 0, sizeof(struct proc_ops));\n+\n+   proc_entry->ops.proc_open = mei_proc_single_open;\n+   proc_entry->ops.proc_release = single_release;\n+\n+   proc_entry->ops.proc_read = seq_read;\n+   proc_entry->ops.proc_lseek = seq_lseek;\n+   if (proc_entry->wr)\n+      proc_entry->ops.proc_write = proc_entry->wr;\n+#endif\n \n    proc_create_data(proc_entry->name,\n                      (S_IFREG | S_IRUGO),\n@@ -2174,9 +2194,11 @@ static int MEI_module_init (void)\n       return (result);\n    }\n \n+#if 0\n #if (MEI_DRV_ATM_PTM_INTERFACE_ENABLE == 1)\n    ppa_callback_set(LTQ_MEI_SHOWTIME_CHECK, (void *)ltq_mei_showtime_check);\n #endif /* #if (MEI_DRV_ATM_PTM_INTERFACE_ENABLE == 1) */\n+#endif\n \n    return 0;\n }\n@@ -2304,6 +2326,10 @@ static void MEI_module_exit (void)\n \n #else\n    unregister_chrdev ( major_number , DRV_MEI_NAME );\n+   device_destroy(mei_class, mei_devt);\n+   mei_devt = 0;\n+   class_destroy(mei_class);\n+   mei_class = NULL;\n #endif\n \n #if CONFIG_PROC_FS\n@@ -2388,9 +2414,11 @@ static void MEI_module_exit (void)\n             (\"MEI_DRV: Chipset Basic Exit failed\" MEI_DRV_CRLF));\n    }\n \n+#if 0\n #if (MEI_DRV_ATM_PTM_INTERFACE_ENABLE == 1)\n    ppa_callback_set(LTQ_MEI_SHOWTIME_CHECK, (void *)NULL);\n #endif /* #if (MEI_DRV_ATM_PTM_INTERFACE_ENABLE == 1) */\n+#endif\n \n #if (MEI_SUPPORT_DEBUG_LOGGER == 1)\n    if (nl_debug_sock)\n@@ -2514,6 +2542,10 @@ static int MEI_InitModuleRegCharDev(cons\n             (\"Using major number %d\" MEI_DRV_CRLF, major_number));\n    }\n \n+   mei_class = class_create(THIS_MODULE, devName);\n+   mei_devt = MKDEV(major_number, 0);\n+   device_create(mei_class, NULL, mei_devt, NULL, \"%s/%i\", devName, 0);\n+\n    return 0;\n #endif      /* CONFIG_DEVFS_FS */\n }\n@@ -2563,21 +2595,32 @@ static int MEI_InitModuleBasics(void)\n }\n \n #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0))\n+\n+#define PMU_DFE         BIT(9)\n+\n static int MEI_SysClkEnable(struct clk *clk)\n {\n+#if 0\n    if (IS_ERR(clk))\n       return -1;\n    clk_enable(clk);\n+#else\n+   ltq_pmu_enable(PMU_DFE);\n+#endif\n \n    return 0;\n }\n \n static int MEI_SysClkDisable(struct clk *clk)\n {\n+#if 0\n    if (IS_ERR(clk))\n       return -1;\n    clk_disable(clk);\n    clk_put(clk);\n+#else\n+   ltq_pmu_disable(PMU_DFE);\n+#endif\n \n    return 0;\n }\n@@ -2905,11 +2948,15 @@ IFX_int32_t MEI_IoctlInitDevice(\n             pMeiDev->eModePoll = e_MEI_DEV_ACCESS_MODE_IRQ;\n             pMeiDev->intMask   = ME_ARC2ME_INTERRUPT_UNMASK_ALL;\n \n+#if 1\n+            virq = (IFX_uint32_t)pInitDev->usedIRQ;\n+#else\n #if (LINUX_VERSION_CODE < KERNEL_VERSION(3,8,0))\n             virq = (IFX_uint32_t)pInitDev->usedIRQ;\n #else\n             virq = irq_create_mapping(NULL, (IFX_uint32_t)pInitDev->usedIRQ);\n #endif\n+#endif\n \n             pTmpXCntrl = MEI_VrxXDevToIrqListAdd(\n                                           MEI_DRV_LINENUM_GET(pMeiDev),\n--- a/src/drv_mei_cpe_api_atm_ptm_intern.c\n+++ b/src/drv_mei_cpe_api_atm_ptm_intern.c\n@@ -147,6 +147,7 @@ IFX_int32_t MEI_InternalXtmSwhowtimeExit\n    return retVal;\n }\n \n+#if 0\n IFX_int32_t MEI_InternalTcRequest(\n                               MEI_DYN_CNTRL_T        *pMeiDynCntrl,\n                               MEI_TC_Request_t       *pArgTcRequest)\n@@ -232,6 +233,7 @@ IFX_int32_t MEI_InternalTcReset(\n \n    return retVal;\n }\n+#endif\n \n /**\n    Function that is used by the PP subsystem to get some showtime relevant data\n@@ -311,10 +313,57 @@ int ifx_mei_atm_led_blink(void)\n     return IFX_SUCCESS;\n }\n \n+#if MEI_MAX_DFE_CHAN_DEVICES > 1\n+#error \"Compat functions do not support MEI_MAX_DFE_CHAN_DEVICES > 1 yet\"\n+#else\n+int (*ifx_mei_atm_showtime_enter)(struct port_cell_info *, void *) = NULL;\n+int (*ifx_mei_atm_showtime_exit)(void) = NULL;\n+\n+int ltq_ifx_mei_atm_showtime_enter_compat(IFX_uint8_t dslLineNum,\n+\t\t\t\t      struct port_cell_info *cellInfo,\n+\t\t\t\t      void *xdata) {\n+\tif (ifx_mei_atm_showtime_enter)\n+\t\treturn ifx_mei_atm_showtime_enter(cellInfo, xdata);\n+\n+\treturn -e_MEI_ERR_OP_FAILED;\n+}\n+\n+int ltq_ifx_mei_atm_showtime_exit_compat(IFX_uint8_t dslLineNum) {\n+\tif (ifx_mei_atm_showtime_exit)\n+\t\treturn ifx_mei_atm_showtime_exit();\n+\n+\treturn -e_MEI_ERR_OP_FAILED;\n+}\n+\n+void* ppa_callback_get(e_ltq_mei_cb_type type) {\n+\tswitch (type) {\n+\t\tcase LTQ_MEI_SHOWTIME_ENTER:\n+\t\t\treturn &ltq_ifx_mei_atm_showtime_enter_compat;\n+\t\tcase LTQ_MEI_SHOWTIME_EXIT:\n+\t\t\treturn &ltq_ifx_mei_atm_showtime_exit_compat;\n+\t\t\tbreak;\n+\t}\n+\n+\tBUG();\n+}\n+\n+int ifx_mei_atm_showtime_check(int *is_showtime,\n+                              struct port_cell_info *port_cell,\n+                              void **xdata_addr) {\n+\treturn ltq_mei_showtime_check(0, is_showtime, port_cell, xdata_addr);\n+}\n+\n+EXPORT_SYMBOL(ifx_mei_atm_showtime_enter);\n+EXPORT_SYMBOL(ifx_mei_atm_showtime_exit);\n+EXPORT_SYMBOL(ifx_mei_atm_showtime_check);\n+#endif\n+\n EXPORT_SYMBOL (MEI_InternalXtmSwhowtimeEntrySignal);\n EXPORT_SYMBOL (MEI_InternalXtmSwhowtimeExitSignal);\n+#if 0\n EXPORT_SYMBOL (MEI_InternalTcRequest);\n EXPORT_SYMBOL (MEI_InternalTcReset);\n+#endif\n EXPORT_SYMBOL(ifx_mei_atm_led_blink);\n \n #endif      /* #if (MEI_EXPORT_INTERNAL_API == 1) && (MEI_DRV_ATM_PTM_INTERFACE_ENABLE == 1) */\n--- a/src/drv_mei_cpe_api_atm_ptm_intern.h\n+++ b/src/drv_mei_cpe_api_atm_ptm_intern.h\n@@ -21,7 +21,6 @@\n \n #include \"drv_mei_cpe_config.h\"\n #include \"drv_mei_cpe_interface.h\"\n-#include <net/ppa_stack_al.h>\n \n #if (MEI_EXPORT_INTERNAL_API == 1) && (MEI_DRV_ATM_PTM_INTERFACE_ENABLE == 1)\n \n@@ -59,8 +58,21 @@ extern IFX_int32_t MEI_InternalTcReset(\n                               MEI_DYN_CNTRL_T        *pMeiDynCntrl,\n                               MEI_TC_Reset_t         *pArgTcReset);\n \n+#if 1\n+#include <lantiq_atm.h>\n+typedef enum {\n+\tLTQ_MEI_SHOWTIME_ENTER,\n+\tLTQ_MEI_SHOWTIME_EXIT\n+} e_ltq_mei_cb_type;\n+\n+typedef void (*ltq_mei_atm_showtime_enter_t)(IFX_uint8_t, struct port_cell_info *, void *);\n+typedef void (*ltq_mei_atm_showtime_exit_t)(IFX_uint8_t);\n+\n+void* ppa_callback_get(e_ltq_mei_cb_type type);\n+#else\n extern int ppa_callback_set(e_ltq_mei_cb_type type, void *func);\n extern void* ppa_callback_get(e_ltq_mei_cb_type type);\n+#endif\n \n int ltq_mei_showtime_check(\n                               const unsigned char line_idx,\n--- a/src/drv_mei_cpe_device_vrx.c\n+++ b/src/drv_mei_cpe_device_vrx.c\n@@ -28,17 +28,6 @@\n #include \"drv_mei_cpe_api.h\"\n #include \"drv_mei_cpe_mei_vrx.h\"\n \n-#if defined(LINUX)\n-#  if (LINUX_VERSION_CODE < KERNEL_VERSION(3,10,0))\n-#    if (MEI_SUPPORT_DEVICE_VR10_320 != 1)\n-#       include \"ifx_pcie.h\"\n-#    else\n-#       include \"../drivers/net/ethernet/lantiq/lantiq_pcie.h\"\n-#    endif\n-#  else\n-#    include \"lantiq_pcie.h\"\n-#  endif\n-#endif /* #if defined(LINUX)*/\n \n IFX_int32_t MEI_GPIntProcess(MEI_MeiRegVal_t processInt, MEI_DEV_T *pMeiDev)\n {\n@@ -86,6 +75,7 @@ IFX_int32_t MEI_GetChipInfo(MEI_DEV_T *p\n */\n IFX_int32_t MEI_VR10_PcieEntitiesCheck(IFX_uint8_t nEntityNum)\n {\n+#if 0\n    IFX_uint32_t pcie_entitiesNum;\n \n    /* get information from pcie driver */\n@@ -110,6 +100,9 @@ IFX_int32_t MEI_VR10_PcieEntitiesCheck(I\n    }\n \n    return IFX_SUCCESS;\n+#else\n+   return IFX_ERROR;\n+#endif\n }\n \n /**\n@@ -124,6 +117,7 @@ IFX_int32_t MEI_VR10_PcieEntitiesCheck(I\n */\n IFX_int32_t MEI_VR10_PcieEntityInit(MEI_MEI_DRV_CNTRL_T *pMeiDrvCntrl)\n {\n+#if 0\n    IFX_uint8_t entityNum;\n #if (MEI_SUPPORT_DEVICE_VR10_320 != 1)\n    ifx_pcie_ep_dev_t MEI_pcie_ep_dev;\n@@ -156,6 +150,9 @@ IFX_int32_t MEI_VR10_PcieEntityInit(MEI_\n    pMeiDrvCntrl->MEI_pcie_irq = 99;\n \n    return IFX_SUCCESS;\n+#else\n+   return IFX_ERROR;\n+#endif\n }\n \n /**\n@@ -170,6 +167,7 @@ IFX_int32_t MEI_VR10_PcieEntityInit(MEI_\n */\n IFX_int32_t MEI_VR10_PcieEntityFree(IFX_uint8_t entityNum)\n {\n+#if 0\n #if (MEI_SUPPORT_DEVICE_VR10_320 != 1)\n    if (ifx_pcie_ep_dev_info_release(entityNum))\n #else\n@@ -183,6 +181,9 @@ IFX_int32_t MEI_VR10_PcieEntityFree(IFX_\n    }\n \n    return IFX_SUCCESS;\n+#else\n+   return IFX_ERROR;\n+#endif\n }\n \n /**\n@@ -197,6 +198,7 @@ IFX_int32_t MEI_VR10_PcieEntityFree(IFX_\n */\n IFX_int32_t MEI_VR10_InternalInitDevice(MEI_DYN_CNTRL_T *pMeiDynCntrl)\n {\n+#if 0\n    IFX_int32_t         retVal;\n    IOCTL_MEI_devInit_t InitDev;\n    MEI_DEV_T           *pMeiDev = pMeiDynCntrl->pMeiDev;\n@@ -221,6 +223,9 @@ IFX_int32_t MEI_VR10_InternalInitDevice(\n    *MEI_GPIO_U32REG(GPIO_P0_ALSEL1) &= ~((1 << 0) | (1 << 3) | (1 << 8));\n \n    return IFX_SUCCESS;\n+#else\n+   return IFX_ERROR;\n+#endif\n }\n \n IFX_int32_t MEI_PLL_ConfigInit(MEI_DEV_T *pMeiDev)\n--- a/src/drv_mei_cpe_download_vrx.c\n+++ b/src/drv_mei_cpe_download_vrx.c\n@@ -3281,12 +3281,14 @@ IFX_int32_t MEI_DEV_IoctlFirmwareDownloa\n    /* reset TC layer */\n    if (ret == 0)\n    {\n+#if 0\n       if (MEI_InternalTcReset(pMeiDynCntrl, &tc_reset) != 0)\n       {\n             PRN_ERR_USR_NL( MEI_DRV, MEI_DRV_PRN_LEVEL_WRN,\n                   (\"MEI_DRV[%02d]: Could not perform reset of TC-Layer!\"\n                    MEI_DRV_CRLF, MEI_DRV_LINENUM_GET(pMeiDev)));\n       }\n+#endif\n    }\n #endif\n \n--- a/src/drv_mei_cpe_linux_proc_config.c\n+++ b/src/drv_mei_cpe_linux_proc_config.c\n@@ -1039,6 +1039,7 @@ static int mei_proc_single_open(struct i\n \treturn single_open(file, mei_seq_single_show, PDE_DATA(inode));\n }\n \n+#if (LINUX_VERSION_CODE < KERNEL_VERSION(5,6,0))\n static struct file_operations proc_ops = {\n    .owner = THIS_MODULE,\n    .open = mei_proc_single_open,\n@@ -1047,6 +1048,15 @@ static struct file_operations proc_ops =\n    .llseek = seq_lseek,\n    .write = MEI_ProcWriteConfig\n };\n+#else\n+static struct proc_ops proc_ops = {\n+   .proc_open = mei_proc_single_open,\n+   .proc_release = single_release,\n+   .proc_read = seq_read,\n+   .proc_lseek = seq_lseek,\n+   .proc_write = MEI_ProcWriteConfig\n+};\n+#endif\n \n /**\n    Create an read/write proc entry for configuration.\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-vdsl-mei/patches/101_no-date-time.patch",
    "content": "--- a/src/drv_mei_cpe_linux.c\n+++ b/src/drv_mei_cpe_linux.c\n@@ -1503,8 +1503,8 @@ struct proc_entry {\n static void MEI_GetVersionProc(struct seq_file *s)\n {\n    seq_printf(s, \"%s\" MEI_DRV_CRLF, &MEI_WHATVERSION[4]);\n-   seq_printf(s, \"Compiled on %s, %s for Linux kernel %s (jiffies: %ld)\" MEI_DRV_CRLF,\n-                                    __DATE__, __TIME__, UTS_RELEASE, jiffies);\n+   seq_printf(s, \"Compiled for Linux kernel %s (jiffies: %ld)\" MEI_DRV_CRLF,\n+                                    UTS_RELEASE, jiffies);\n }\n \n /**\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-vdsl-mei/patches/110-reset-g_tx_link_rate-on-showtime-exit.patch",
    "content": "--- a/src/drv_mei_cpe_api_atm_ptm_intern.c\n+++ b/src/drv_mei_cpe_api_atm_ptm_intern.c\n@@ -124,6 +124,9 @@ IFX_int32_t MEI_InternalXtmSwhowtimeExit\n    /* Get line number*/\n    dslLineNum = pMeiDynCntrl->pMeiDev->meiDrvCntrl.dslLineNum;\n \n+   g_tx_link_rate[dslLineNum][0] = 0;\n+   g_tx_link_rate[dslLineNum][1] = 0;\n+\n    /* get NULL or function pointer */\n    mei_showtime_exit =\n         (ltq_mei_atm_showtime_exit_t)ppa_callback_get(LTQ_MEI_SHOWTIME_EXIT);\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-vdsl-mei/patches/200-interrupt-lock.patch",
    "content": "--- a/src/drv_mei_cpe_common.c\n+++ b/src/drv_mei_cpe_common.c\n@@ -104,6 +104,8 @@ IFX_uint32_t MEI_FsmStateSetMsgPreAction\n MEI_DEVCFG_DATA_T MEI_DevCfgData;\n #endif\n \n+static DEFINE_SPINLOCK(MEI_InterruptLock);\n+\n /* ============================================================================\n    Proc-FS and debug variable definitions\n    ========================================================================= */\n@@ -2134,6 +2136,9 @@ IFX_int32_t MEI_ProcessIntPerIrq(MEIX_CN\n #if (MEI_SUPPORT_DEBUG_STREAMS == 1)\n    IFX_int_t   extraDbgStreamLoop = 0;\n #endif\n+   unsigned long flags;\n+\n+   spin_lock_irqsave(&MEI_InterruptLock, flags);\n \n    /* get the actual chip device from the list and step through the VRX devices */\n    while(pNextXCntrl)\n@@ -2167,6 +2172,8 @@ IFX_int32_t MEI_ProcessIntPerIrq(MEIX_CN\n    }\n #endif\n \n+   spin_unlock_irqrestore(&MEI_InterruptLock, flags);\n+\n    return meiIntCnt;\n }\n \n@@ -2639,9 +2646,14 @@ IFX_int32_t MEI_MsgSendPreAction(\n */\n IFX_void_t MEI_DisableDeviceInt(MEI_DEV_T *pMeiDev)\n {\n+   unsigned long flags;\n+   spin_lock_irqsave(&MEI_InterruptLock, flags);\n+\n    MEI_MaskInterrupts( &pMeiDev->meiDrvCntrl,\n                        ME_ARC2ME_INTERRUPT_MASK_ALL);\n \n+   spin_unlock_irqrestore(&MEI_InterruptLock, flags);\n+\n    return;\n }\n \n"
  },
  {
    "path": "package/kernel/lantiq/ltq-vectoring/Makefile",
    "content": "include $(TOPDIR)/rules.mk\n\nPKG_NAME:=ltq-vectoring\nPKG_RELEASE:=$(AUTORELEASE)\nPKG_SOURCE_PROTO:=git\nPKG_SOURCE_URL:=https://gitlab.com/prpl-foundation/intel/ppa_drv.git\nPKG_SOURCE_DATE:=2019-05-20\nPKG_SOURCE_VERSION:=4fa7ac30fcc8ec4eddae9debba5f4230981f469f\nPKG_MIRROR_HASH:=444eb823dd9ddd25453976bf7a3230955e4148b8bf92f35f165ecffee32c4555\nPKG_LICENSE:=GPL-2.0 BSD-2-Clause\n\nMAKE_PATH:=src/vectoring\nPKG_EXTMOD_SUBDIRS:=$(MAKE_PATH)\n\ninclude $(INCLUDE_DIR)/kernel.mk\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine KernelPackage/ltq-vectoring\n  SECTION:=sys\n  CATEGORY:=Kernel modules\n  SUBMENU:=Network Devices\n  TITLE:=driver for sending vectoring error samples\n  DEPENDS:=@TARGET_lantiq_xrx200\n  FILES:=$(PKG_BUILD_DIR)/$(MAKE_PATH)/ltq_vectoring.ko\n  AUTOLOAD:=$(call AutoLoad,49,ltq_vectoring)\nendef\n\ndefine Package/ltq-vectoring/description\n\tThis driver is responsible for sending error reports to the vectoring\n\tcontrol entity, which is required for downstream vectoring to work.\n\n\tThe error reports are generated by the DSL firmware, and passed to this\n\tdriver by the MEI driver.\nendef\n\ndefine KernelPackage/ltq-vectoring-test\n  SECTION:=sys\n  CATEGORY:=Kernel modules\n  SUBMENU:=Network Devices\n  TITLE:=driver for testing the vectoring driver\n  DEPENDS:=@TARGET_lantiq_xrx200 +kmod-ltq-vectoring\n  FILES:=$(PKG_BUILD_DIR)/$(MAKE_PATH)/ltq_vectoring_test.ko\nendef\n\ndefine Package/ltq-vectoring-test/description\n\tThis allows to send dummy data to the vectoring error block callback.\n\tThis is only needed for test and development purposes.\nendef\n\ndefine Build/Configure\nendef\n\ndefine Build/Compile\n\t+$(MAKE) $(PKG_JOBS) -C \"$(LINUX_DIR)\" \\\n\t\t$(KERNEL_MAKE_FLAGS) \\\n\t\tM=\"$(PKG_BUILD_DIR)/$(MAKE_PATH)\" \\\n\t\tmodules\nendef\n\n$(eval $(call KernelPackage,ltq-vectoring))\n$(eval $(call KernelPackage,ltq-vectoring-test))\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-vectoring/patches/001-fix-compile.patch",
    "content": "--- a/src/vectoring/Makefile\n+++ b/src/vectoring/Makefile\n@@ -1,5 +1,5 @@\n-obj-$(CONFIG_PTM_VECTORING)\t+= ifxmips_vectoring.o\n-obj-y += ifxmips_vectoring_stub.o\n-ifeq ($(CONFIG_DSL_MEI_CPE_DRV),)\n-obj-$(CONFIG_PTM_VECTORING)\t+= ifxmips_vectoring_test.o\n-endif\n+obj-m += ltq_vectoring.o\n+ltq_vectoring-objs = ifxmips_vectoring.o ifxmips_vectoring_stub.o\n+\n+obj-m += ltq_vectoring_test.o\n+ltq_vectoring_test-objs = ifxmips_vectoring_test.o\n--- a/src/vectoring/ifxmips_vectoring.c\n+++ b/src/vectoring/ifxmips_vectoring.c\n@@ -30,9 +30,11 @@\n /*\n  *  Common Head File\n  */\n+#include <linux/version.h>\n #include <linux/kernel.h>\n #include <linux/module.h>\n #include <linux/etherdevice.h>\n+#include <linux/proc_fs.h>\n \n /*\n  *  Chip Specific Head File\n@@ -239,7 +241,7 @@ static int netdev_event_handler(struct n\n         && event != NETDEV_UNREGISTER )\n         return NOTIFY_DONE;\n \n-    netif = (struct net_device *)netdev;\n+    netif = netdev_notifier_info_to_dev(netdev);\n     if ( strcmp(netif->name, \"ptm0\") != 0 )\n         return NOTIFY_DONE;\n \n@@ -356,6 +358,7 @@ static int proc_write_dbg(struct file *f\n     return count;\n }\n \n+#if LINUX_VERSION_CODE < KERNEL_VERSION(5,6,0)\n static struct file_operations g_proc_file_vectoring_dbg_seq_fops = {\n     .owner      = THIS_MODULE,\n     .open       = proc_read_dbg_seq_open,\n@@ -364,6 +367,15 @@ static struct file_operations g_proc_fil\n     .llseek     = seq_lseek,\n     .release    = single_release,\n };\n+#else\n+static struct proc_ops g_proc_file_vectoring_dbg_seq_fops = {\n+    .proc_open    = proc_read_dbg_seq_open,\n+    .proc_read    = seq_read,\n+    .proc_write   = proc_write_dbg,\n+    .proc_lseek   = seq_lseek,\n+    .proc_release = single_release,\n+};\n+#endif\n \n static int proc_read_dbg_seq_open(struct inode *inode, struct file *file)\n {\n--- a/src/vectoring/ifxmips_vectoring_test.c\n+++ b/src/vectoring/ifxmips_vectoring_test.c\n@@ -1,6 +1,8 @@\n+#include <linux/version.h>\n #include <linux/kernel.h>\n #include <linux/module.h>\n #include <linux/proc_fs.h>\n+#include <linux/seq_file.h>\n \n #include \"ifxmips_vectoring_stub.h\"\n \n@@ -82,6 +84,7 @@ static int proc_write_vectoring(struct f\n     return count;\n }\n \n+#if LINUX_VERSION_CODE < KERNEL_VERSION(5,6,0)\n static struct file_operations g_proc_file_vectoring_seq_fops = {\n     .owner      = THIS_MODULE,\n     .open       = proc_read_vectoring_seq_open,\n@@ -90,6 +93,15 @@ static struct file_operations g_proc_fil\n     .llseek     = seq_lseek,\n     .release    = single_release,\n };\n+#else\n+static struct proc_ops g_proc_file_vectoring_seq_fops = {\n+    .proc_open    = proc_read_vectoring_seq_open,\n+    .proc_read    = seq_read,\n+    .proc_write   = proc_write_vectoring,\n+    .proc_lseek   = seq_lseek,\n+    .proc_release = single_release,\n+};\n+#endif\n \n static int proc_read_vectoring_seq_open(struct inode *inode, struct file *file)\n {\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-vectoring/patches/100-cleanup.patch",
    "content": "--- a/src/vectoring/ifxmips_vectoring.c\n+++ b/src/vectoring/ifxmips_vectoring.c\n@@ -325,7 +325,7 @@ static int proc_write_dbg(struct file *f\n             else\n                 printk(dbg_enable_mask_str[i] + 1);\n         }\n-        printk(\"] > /proc/vectoring\\n\");\n+        printk(\"] > /proc/driver/vectoring\\n\");\n     }\n \n     if ( f_enable )\n@@ -433,11 +433,10 @@ static int __init vectoring_init(void)\n {\n     struct proc_dir_entry *res;\n \n-    res = proc_create(\"vectoring\",\n+    res = proc_create(\"driver/vectoring\",\n \t\t\t\tS_IRUGO|S_IWUSR,\n \t\t\t\t0,\n \t\t\t\t&g_proc_file_vectoring_dbg_seq_fops);\n-    printk(\"res = %p\\n\", res);\n \n     register_netdev_event_handler();\n     g_ptm_net_dev = dev_get_by_name(&init_net, \"ptm0\");\n@@ -460,7 +459,7 @@ static void __exit vectoring_exit(void)\n \n     unregister_netdev_event_handler();\n \n-    remove_proc_entry(\"vectoring\", NULL);\n+    remove_proc_entry(\"driver/vectoring\", NULL);\n }\n \n module_init(vectoring_init);\n--- a/src/vectoring/ifxmips_vectoring_test.c\n+++ b/src/vectoring/ifxmips_vectoring_test.c\n@@ -79,7 +79,7 @@ static int proc_write_vectoring(struct f\n         }\n     }\n     else\n-        printk(\"echo send <size> > /proc/eth/vectoring\\n\");\n+        printk(\"echo send <size> > /proc/driver/vectoring_test\\n\");\n \n     return count;\n }\n@@ -112,9 +112,7 @@ static __init void proc_file_create(void\n {\n     struct proc_dir_entry *res;\n \n-//    g_proc_dir = proc_mkdir(\"eth\", NULL);\n-\n-    res = proc_create(\"eth/vectoring\",\n+    res = proc_create(\"driver/vectoring_test\",\n                             S_IRUGO|S_IWUSR,\n                             g_proc_dir,\n \t\t\t&g_proc_file_vectoring_seq_fops);\n@@ -122,10 +120,7 @@ static __init void proc_file_create(void\n \n static __exit void proc_file_delete(void)\n {\n-    remove_proc_entry(\"vectoring\",\n-                      g_proc_dir);\n-\n-    remove_proc_entry(\"eth\", NULL);\n+    remove_proc_entry(\"driver/vectoring_test\", NULL);\n }\n \n \n@@ -151,3 +146,5 @@ static void __exit vectoring_test_exit(v\n \n module_init(vectoring_test_init);\n module_exit(vectoring_test_exit);\n+\n+MODULE_LICENSE(\"GPL\");\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-vectoring/patches/200-compat.patch",
    "content": "--- a/src/vectoring/ifxmips_vectoring.c\n+++ b/src/vectoring/ifxmips_vectoring.c\n@@ -35,6 +35,8 @@\n #include <linux/module.h>\n #include <linux/etherdevice.h>\n #include <linux/proc_fs.h>\n+#include <linux/pkt_sched.h>\n+#include <linux/workqueue.h>\n \n /*\n  *  Chip Specific Head File\n@@ -88,6 +90,7 @@ static void dump_skb(struct sk_buff *skb\n \n static void ltq_vectoring_priority(uint32_t priority);\n \n+static void xmit_work_handler(struct work_struct *);\n \n /*\n  * ####################################\n@@ -118,9 +121,11 @@ struct erb_head {\n \n static struct notifier_block g_netdev_event_handler_nb = {0};\n static struct net_device *g_ptm_net_dev = NULL;\n-static uint32_t vector_prio = 0;\n+static uint32_t vector_prio = TC_PRIO_CONTROL;\n static int g_dbg_enable = 0;\n \n+DECLARE_WORK(xmit_work, xmit_work_handler);\n+struct sk_buff_head xmit_queue;\n \n \n /*\n@@ -129,9 +134,16 @@ static int g_dbg_enable = 0;\n  * ####################################\n  */\n \n+static void xmit_work_handler(__attribute__((unused)) struct work_struct *work) {\n+\tstruct sk_buff *skb;\n+\n+\twhile ((skb = skb_dequeue(&xmit_queue)) != NULL) {\n+\t\tdev_queue_xmit(skb);\n+\t}\n+}\n+\n static int mei_dsm_cb_func(unsigned int *p_error_vector)\n {\n-    int rc, ret;\n     struct sk_buff *skb_list = NULL;\n     struct sk_buff *skb;\n     struct erb_head *erb;\n@@ -179,7 +191,6 @@ static int mei_dsm_cb_func(unsigned int\n         }\n     }\n \n-    rc = 0;\n     sent_size = 0;\n     segment_code = 0;\n     while ( (skb = skb_list) != NULL ) {\n@@ -197,24 +208,23 @@ static int mei_dsm_cb_func(unsigned int\n             segment_code |= 0xC0;\n         ((struct erb_head *)skb->data)->segment_code = segment_code;\n \n-        skb->cb[13] = 0x5A; /* magic number indicating forcing QId */\n-        skb->cb[15] = 0x00; /* highest priority queue */\n-\t\tskb->priority = vector_prio;\n+        skb_reset_mac_header(skb);\n+        skb_set_network_header(skb, offsetof(struct erb_head, llc_header));\n+        skb->protocol = htons(ETH_P_802_2);\n+        skb->priority = vector_prio;\n         skb->dev = g_ptm_net_dev;\n \n         dump_skb(skb, ~0, \"vectoring TX\", 0, 0, 1, 0);\n \n-        ret = g_ptm_net_dev->netdev_ops->ndo_start_xmit(skb, g_ptm_net_dev);\n-        if ( rc == 0 )\n-            rc = ret;\n+        skb_queue_tail(&xmit_queue, skb);\n+        schedule_work(&xmit_work);\n \n         segment_code++;\n     }\n \n     *p_error_vector = 0;    /* notify DSL firmware that ERB is sent */\n \n-    ASSERT(rc == 0, \"dev_queue_xmit fail - %d\", rc);\n-    return rc;\n+    return 0;\n }\n static void ltq_vectoring_priority(uint32_t priority)\n {\n@@ -242,7 +252,7 @@ static int netdev_event_handler(struct n\n         return NOTIFY_DONE;\n \n     netif = netdev_notifier_info_to_dev(netdev);\n-    if ( strcmp(netif->name, \"ptm0\") != 0 )\n+    if ( strcmp(netif->name, \"dsl0\") != 0 )\n         return NOTIFY_DONE;\n \n     g_ptm_net_dev = event == NETDEV_REGISTER ? netif : NULL;\n@@ -438,8 +448,10 @@ static int __init vectoring_init(void)\n \t\t\t\t0,\n \t\t\t\t&g_proc_file_vectoring_dbg_seq_fops);\n \n+    skb_queue_head_init(&xmit_queue);\n+\n     register_netdev_event_handler();\n-    g_ptm_net_dev = dev_get_by_name(&init_net, \"ptm0\");\n+    g_ptm_net_dev = dev_get_by_name(&init_net, \"dsl0\");\n     if ( g_ptm_net_dev != NULL )\n         dev_put(g_ptm_net_dev);\n \n@@ -459,6 +471,8 @@ static void __exit vectoring_exit(void)\n \n     unregister_netdev_event_handler();\n \n+    flush_scheduled_work();\n+\n     remove_proc_entry(\"driver/vectoring\", NULL);\n }\n \n"
  },
  {
    "path": "package/kernel/lantiq/ltq-vmmc/Config.in",
    "content": "choice\n\tprompt \"device selection\"\n\tdepends on PACKAGE_kmod-ltq-vmmc\n\tdefault VOICE_CPE_VMMC_WITH_DEVICE_DANUBE\n\thelp\n\t\tSelect the target device.\n\n\tconfig VOICE_CPE_VMMC_WITH_DEVICE_DANUBE\n\t\tbool \"Danube, Twinpass, Vinax\"\n\t\tdepends on TARGET_lantiq_xway\n\n#\tconfig VOICE_CPE_VMMC_WITH_DEVICE_AR9\n#\t\tbool \"AR9 family\"\n#\t\tdepends on TARGET_lantiq_ar9\n\n\tconfig VOICE_CPE_VMMC_WITH_DEVICE_VR9\n\t\tbool \"VR9 family\"\n\t\tdepends on TARGET_lantiq_xrx200\n\t\n\tconfig VOICE_VMMC_WITH_DEVICE_FALCON\n\t\tbool \"FALC-ON\"\n\t\tdepends on (TARGET_lantiq_falcon||TARGET_lantiq_falcon_stable)\n\nendchoice\n\nchoice\n\tdepends on (PACKAGE_kmod-ltq-vmmc && VOICE_VMMC_WITH_DEVICE_FALCON)\n\tprompt \"FXS coefficients\"\n\tdefault LTQ_VOICE_CPE_VMMC_COEF_FALCON_ETSI\n\thelp\n\t\tSelect country specific FXS coefficient file.\n\n\tconfig LTQ_VOICE_CPE_VMMC_COEF_FALCON_ETSI\n\t\tbool \"ETSI_T3R10: Vl:40V, Ic:25mA, Vid:25V, Vri:45Vrms, f:25Hz\"\t\n\t\thelp\n\t\t  These coefficents contains a parameter set with line impedance Zr according to ETSI.\n\n\t\t  T:   gain in transmit direction (attenuation 3dBr) [dBr]\n\t\t  R:   gain in receive direction (attenuation 10dBr) [dBr]\n\t\t  Vl:  on-hook voltage limit [V]\n\t\t  Ic:  off-hook loop current [mA]\n\t\t  Vid: low-power-standby voltage [V]\n\t\t  Vri: ring voltage [v]\n\t\t  f:   ring frequency [V]\n\n\tconfig LTQ_VOICE_CPE_VMMC_COEF_FALCON_US600R\n\t\tbool \"USA_600R_T3R10: Vl:40V, Ic:25mA, Vid:25V, Vri:45V, f:20Hz\"\n\t\thelp\n\t\t  These coefficents contains a parameter set with line impedance e.g. for USA.\n \n\t\t  T:   gain in transmit direction (attenuation 3dBr) [dBr]\n\t\t  R:   gain in receive direction (attenuation 10dBr) [dBr]\n\t\t  Vl:  on-hook voltage limit [V]\n\t\t  Ic:  off-hook loop current [mA]\n\t\t  Vid: low-power-standby voltage [V]\n\t\t  Vri: ring voltage [v]\n\t\t  f:   ring frequency [V]\n\n\tconfig LTQ_VOICE_CPE_VMMC_COEF_FALCON_USE_CUSTOM_FILE\n\t\tbool \"Select own FXS coefficient file\"\nendchoice\n\nconfig VOICE_CPE_VMMC_PMC\n\tdepends on BROKEN\n\tdepends on (VOICE_CPE_VMMC_WITH_DEVICE_AR9 || VOICE_CPE_VMMC_WITH_DEVICE_VR9)\n\tbool \"Power Management Control support\"\n\tdefault n\n\thelp\n\t\tOption to enable Power Management Control on AR9, VR9. Not supported for Danube.\n\nconfig VOICE_CPE_VMMC_DISABLE_DECT_NIBBLE_SWAP\n\tbool \"Disable DECT nibble swap\"\n\tdepends on PACKAGE_kmod-ltq-vmmc\n\tdefault n\n\thelp\n\t\tOption to disable DECT nibble swap for COSIC modem (for backward compatibility only).\n\nconfig VOICE_CPE_VMMC_EVENT_LOGGER\n\tdepends on BROKEN\n\tbool \"Event logger support\"\n\tdepends on PACKAGE_kmod-ltq-vmmc\n\tdefault n\n\thelp\n\t\tOption to enable details traces between drv_vmmc and the voice FW\n\t\t- for debugging only\n\t\t- requires package ifx-evtlog\n\nconfig VOICE_CPE_VMMC_MPS_HISTORY_SIZE\n\tint \"MPS history buffer in words (0<=size<=512)\"\n\tdepends on PACKAGE_kmod-ltq-vmmc\n\tdefault \"128\"\n\thelp\n\t\tMPS history buffer (default=128 words, maximum=512 words, 0=disable)\n\t\tTo opimize the memory footprint in RAM, you might want to set the\n\t\tbuffer size to 0.\n\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-vmmc/Makefile",
    "content": "#\n# Copyright (C) 2011 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\ninclude $(INCLUDE_DIR)/kernel.mk\n\nPKG_NAME:=drv_vmmc\nPKG_VERSION:=1.9.0\nPKG_RELEASE:=4\n\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.bz2\nPKG_HASH:=707f515eb727c032418c4da67d7e86884bb56cdc2a606e8f6ded6057d8767e57\nPKG_SOURCE_URL:=@OPENWRT\nPKG_MAINTAINER:=John Crispin <john@phrozen.org>\n\nPKG_CHECK_FORMAT_SECURITY:=0\nPKG_FIXUP:=autoreconf\n\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine KernelPackage/ltq-vmmc\n  SUBMENU:=Voice over IP\n  TITLE:=TAPI LL driver for Voice Macro\n  URL:=http://www.lantiq.com/\n  DEPENDS:=@(TARGET_lantiq_xway||TARGET_lantiq_xrx200) +kmod-ltq-tapi\n  FILES:=$(PKG_BUILD_DIR)/src/drv_vmmc.ko\n  AUTOLOAD:=$(call AutoProbe,drv_vmmc)\nendef\n\ndefine KernelPackage/ltq-vmmc/description\n\tVoice Subsystem Low Level Driver for Danube, AR9, VR9 device families\nendef\n\ndefine KernelPackage/ltq-vmmc/config\n\tsource \"$(SOURCE)/Config.in\"\nendef\n\nMAKE_FLAGS += \\\n\t$(KERNEL_MAKE_FLAGS)\n\nCONFIGURE_ARGS += \\\n\tARCH=$(LINUX_KARCH) \\\n\t--enable-linux-26 \\\n\t--enable-kernelbuild=\"$(LINUX_DIR)\" \\\n\t--enable-kernelincl=\"$(LINUX_DIR)/include\" \\\n\t--enable-tapiincl=\"$(STAGING_DIR)/usr/include/drv_tapi\" \\\n\t--with-ifxos-incl=$(STAGING_DIR)/usr/include/ifxos \\\n\t$(call autoconf_bool,CONFIG_VOICE_CPE_VMMC_EVENT_LOGGER,el-debug) \\\n\t$(call autoconf_bool,CONFIG_VOICE_CPE_VMMC_PMC,pmc) \\\n\t$(call autoconf_bool,CONFIG_VOICE_CPE_VMMC_DISABLE_DECT_NIBBLE_SWAP,dect-nibble-swap) \\\n\t$(call autoconf_bool,CONFIG_VOICE_CPE_TAPI_FAX,fax t38) \\\n\t$(call autoconf_bool,CONFIG_VOICE_CPE_TAPI_CID,cid) \\\n\t$(call autoconf_bool,CONFIG_VOICE_CPE_TAPI_DECT,dect) \\\n\t$(call autoconf_bool,CONFIG_VOICE_CPE_TAPI_KPI,kpi) \\\n\t$(call autoconf_bool,CONFIG_VOICE_CPE_TAPI_LT_GR909,lt calibration) \\\n\t$(call autoconf_bool,CONFIG_VOICE_CPE_TAPI_HDLC,hdlc) \\\n\t$(call autoconf_bool,CONFIG_VOICE_CPE_TAPI_TRACES,trace)\n\nifneq ($(CONFIG_VOICE_CPE_VMMC_MPS_HISTORY_SIZE),128)\n  CONFIGURE_ARGS += --enable-history-buf=$(CONFIG_VOICE_CPE_VMMC_MPS_HISTORY_SIZE)\nendif\n\n#defaults\nFW_URL:=http://downloads.openwrt.org/sources/\nFW_TARGET:=ifx_firmware.bin\nFW_FILE:=fw_voip_ifx.tar.gz\nCOEF_TARGET:=ifx_bbd_fxs.bin\nCOEF_FILE:=coef_voip_ifx.tar.gz\n\nFW_DIR:=lib/firmware\n\nFW_TARGET_GENERIC:=$(FW_TARGET)\nCOEF_TARGET_GENERIC:=$(COEF_TARGET)\n\nifeq ($(CONFIG_VOICE_CPE_VMMC_WITH_DEVICE_DANUBE)$(CONFIG_LTQ_VOICE_CPE_VMMC_WITH_DEVICE_DANUBE),y)\n  CONFIGURE_ARGS += --with-device=DANUBE\n  FW_SOURCE:=voip_R12.1.0.1.0-enc.bin\n  FW_TARGET:=danube_firmware.bin\n  FW_FILE=fw_voip_danube-12.1.0.1.0.tar.gz\n  FW_HASH:=bb92a6f1b864f217863e435eab6e5bbf8fe9a06b1398fe5aa8542baf53f7d927\n  FW_DOWNLOAD:=1\n  COEF_SRC:=danube_bbd_fxs.bin\n  COEF_TARGET:=danube_bbd_fxs.bin\n  COEF_FILE:=coef_voip_danube-0.9.0.tar.gz\n  COEF_HASH:=6578d6c8f4874b7e4bf10d10c7e5b7e913f6a7cdeba998fb04f28c41f94c82c1\n  COEF_DOWNLOAD:=1\nendif\n\nifeq ($(CONFIG_VOICE_CPE_VMMC_WITH_DEVICE_AR9),y)\n  CONFIGURE_ARGS += --with-device=AR9\n  # TODO: add fw/coef\nendif\n\nCOEF_SRC:=$(COEF_TARGET)\n\nifeq ($(CONFIG_VOICE_VMMC_WITH_DEVICE_FALCON),y)\n  CONFIGURE_ARGS += --with-device=FALCON\n  FW_SOURCE:=voip_R1.1.0.6.0-enc.bin\n  FW_HASH:=5046a9df736ce302bb240f262c2557c4c9d9b214c22ea67910e3a01a3728c84a\n  FW_TARGET:=falcon_voip_fw.bin\n  FW_FILE=fw_voip_falcon-1.1.0.6.0.tar.gz\n  FW_DOWNLOAD:=1\n  COEF_TARGET:=falcon_bbd.bin\n# FXS part\nifeq ($(CONFIG_LTQ_VOICE_CPE_VMMC_COEF_FALCON_ETSI),y)\n\tCOEF_SRC:=ETSI_3_10.BIN\nendif\nifeq ($(CONFIG_LTQ_VOICE_CPE_VMMC_COEF_FALCON_US600R),y)\n\tCOEF_SRC:=R600_3_10.BIN\nendif\nifeq ($(CONFIG_LTQ_VOICE_CPE_VMMC_COEF_FALCON_USE_CUSTOM_FILE),y)\n\tCOEF_SRC:=$(CONFIG_LTQ_VOICE_CPE_VMMC_COEF_FALCON_CUSTOM_FILE)\nendif\n  COEF_FILE:=coef_voip_falcon.tar.gz\n  COEF_HASH:=9b63b2cc7fefdad36d43c307227fc1aade3cf5600ee75fb572da6d908238cf60\n  COEF_DOWNLOAD:=1\nendif\n\nifeq ($(CONFIG_VOICE_CPE_VMMC_WITH_DEVICE_VR9),y)\n  CONFIGURE_ARGS += --with-device=VR9\n  FW_TARGET:=voice_ar9_firmware.bin\n  FW_SOURCE:=voip_R2.3.1.7.0-enc.bin\n  FW_FILE=fw_voip_vr9-2.3.1.7.0.tar.gz\n  FW_HASH:=bc64da5a44a5440d6008f80a5d3f6fdb15c90f9b4023795d1b5b8e35c50bd167\n  FW_DOWNLOAD:=1\n  COEF_SRC:=ETSI_3_10.BIN\n  COEF_TARGET:=vr9_bbd_fxs.bin\n  COEF_FILE:=coef_voip_vr9-0.9.3.tar.gz\n  COEF_HASH:=3264ed2ab0316bdda419b649fd0d6cadf02540c7e5dc0ea501a7fb680fb371e7\n  COEF_DOWNLOAD:=1\n\n  COEF_SRC_FXO:=FXO_ETSI_0_0.BIN\n  COEF_TARGET_FXO:=vr9_bbd.bin\nendif\n\ndefine Download/firmware\n  FILE:=$(FW_FILE)\n  URL:=$(FW_URL)\n  HASH:=$(FW_HASH)\nendef\n$(eval $(if $(FW_DOWNLOAD),$(call Download,firmware)))\n\ndefine Download/coef\n  FILE:=$(COEF_FILE)\n  URL:=$(FW_URL)\n  HASH:=$(COEF_HASH)\nendef\n$(eval $(if $(COEF_DOWNLOAD),$(call Download,coef)))\n\ndefine Build/Configure\n\trm -rf \\\n\t\t$(PKG_BUILD_DIR)/coef \\\n\t\t$(PKG_BUILD_DIR)/firmware\n\tmkdir -p \\\n\t\t$(PKG_BUILD_DIR)/coef \\\n\t\t$(PKG_BUILD_DIR)/firmware\n\t$(TAR) -C $(PKG_BUILD_DIR)/firmware -xvzf $(DL_DIR)/$(FW_FILE)\n\t$(TAR) -C $(PKG_BUILD_DIR)/coef -xvzf $(DL_DIR)/$(COEF_FILE)\n\t$(call Build/Configure/Default)\nendef\n\ndefine Build/InstallDev\n\t$(INSTALL_DIR) $(1)/usr/include\n\tmkdir -p $(1)/usr/include/drv_vmmc\n\t$(CP) -v --dereference $(PKG_BUILD_DIR)/include/* $(1)/usr/include/drv_vmmc\n\t(cd $(1)/usr/include/drv_vmmc && ln -snf . include)\nendef\n\ndefine KernelPackage/ltq-vmmc/install\n\t$(INSTALL_DIR) $(1)/etc/init.d $(1)/$(FW_DIR)\n\t$(INSTALL_BIN) ./files/vmmc.init $(1)/etc/init.d/vmmc\n\t$(INSTALL_DATA) $(PKG_BUILD_DIR)/firmware/$(FW_SOURCE) $(1)/$(FW_DIR)/$(FW_TARGET)\n\tln -s /$(FW_DIR)/$(FW_TARGET) $(1)/$(FW_DIR)/$(FW_TARGET_GENERIC)\n\t$(CP) $(PKG_BUILD_DIR)/coef/$(COEF_SRC) $(1)/$(FW_DIR)/$(COEF_TARGET)\n\t$(CP) $(PKG_BUILD_DIR)/coef/$(COEF_SRC_FXO) $(1)/$(FW_DIR)/$(COEF_TARGET_FXO)\n\tln -s /$(FW_DIR)/$(COEF_TARGET) $(1)/$(FW_DIR)/$(COEF_TARGET_GENERIC)\nendef\n\n$(eval $(call KernelPackage,ltq-vmmc))\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-vmmc/files/vmmc.init",
    "content": "#!/bin/sh /etc/rc.common\n#\n# Activate Voice CPE TAPI subsystem LL driver for VMMC\n\nSTART=31\n\nstart() {\n\tfor i in 10 11 12 13 14 15 16 17 18; do\n\t\tif ! [ -e /dev/vmmc$i ]; then\n\t\t\tmknod -m 664 /dev/vmmc$i c 122 $i\n\t\tfi\n\tdone\n}\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-vmmc/patches/000-portability.patch",
    "content": "--- a/src/Makefile.am\n+++ b/src/Makefile.am\n@@ -228,7 +228,7 @@ drv_vmmc_CFLAGS += -fno-common\n drv_vmmc_OBJS = \"$(subst .c,.o, $(drv_vmmc_SOURCES) $(nodist_drv_vmmc_SOURCES))\"\n \n drv_vmmc.ko: $(drv_vmmc_SOURCES) $(EXTRA_DIST)\n-\t@echo -e \"Making Linux 2.6.x kernel object\"\n+\t@echo \"Making Linux 2.6.x kernel object\"\n \t@for f in $(drv_vmmc_SOURCES) $(nodist_drv_vmmc_SOURCES) ; do \\\n \t\tif test ! -e $(PWD)/$$f; then \\\n \t\t\techo \"  LN      $$f\" ; \\\n@@ -236,10 +236,10 @@ drv_vmmc.ko: $(drv_vmmc_SOURCES) $(EXTRA\n \t\t\tln -s @abs_srcdir@/$$f $(PWD)/$$f; \\\n \t\tfi; \\\n \tdone;\n-\t@echo -e \"# drv_vmmc: Generated to build Linux 2.6.x kernel object\" > $(PWD)/Kbuild\n-\t@echo -e \"obj-m := $(subst .ko,.o,$@)\"\t\t\t>> $(PWD)/Kbuild\n-\t@echo -e \"$(subst .ko,,$@)-y := $(drv_vmmc_OBJS)\"\t>> $(PWD)/Kbuild\n-\t@echo -e \"EXTRA_CFLAGS := -DHAVE_CONFIG_H  $(CFLAGS) $(drv_vmmc_CFLAGS) $(INCLUDES)\"\t>> $(PWD)/Kbuild\n+\t@echo \"# drv_vmmc: Generated to build Linux 2.6.x kernel object\" > $(PWD)/Kbuild\n+\t@echo \"obj-m := $(subst .ko,.o,$@)\"\t\t\t>> $(PWD)/Kbuild\n+\t@echo \"$(subst .ko,,$@)-y := $(drv_vmmc_OBJS)\"\t>> $(PWD)/Kbuild\n+\t@echo \"EXTRA_CFLAGS := -DHAVE_CONFIG_H  $(CFLAGS) $(drv_vmmc_CFLAGS) $(INCLUDES)\"\t>> $(PWD)/Kbuild\n \t$(MAKE) ARCH=@KERNEL_ARCH@ -C @KERNEL_BUILD_PATH@ O=@KERNEL_BUILD_PATH@ M=$(PWD) modules\n \n clean-generic:\n--- a/src/drv_vmmc_linux.c\n+++ b/src/drv_vmmc_linux.c\n@@ -27,11 +27,18 @@\n #include <linux/proc_fs.h>\n #include <linux/wait.h>\n #include <linux/vmalloc.h>\n+#include <linux/sched.h>\n \n #ifdef LINUX_2_6\n #include <linux/version.h>\n #ifndef UTS_RELEASE\n+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,33))\n+#include <linux/autoconf.h>\n #include <linux/utsrelease.h>\n+#else\n+#include <generated/autoconf.h>\n+#include <generated/utsrelease.h>\n+#endif\n #endif /* UTC_RELEASE */\n #undef CONFIG_DEVFS_FS\n #endif /* LINUX_2_6 */\n--- a/src/mps/drv_mps_vmmc_linux.c\n+++ b/src/mps/drv_mps_vmmc_linux.c\n@@ -19,11 +19,22 @@\n #include \"drv_config.h\"\n \n #include \"drv_mps_version.h\"\n+#include <linux/version.h>\n \n #ifdef CONFIG_DEBUG_MINI_BOOT\n #define IKOS_MINI_BOOT\n #endif /* */\n+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,33))\n #include <linux/autoconf.h>\n+#ifndef UTS_RELEASE\n+#include <linux/utsrelease.h>\n+#endif\n+#else\n+#include <generated/autoconf.h>\n+#ifndef UTS_RELEASE\n+#include <generated/utsrelease.h>\n+#endif\n+#endif\n #include <linux/module.h>\n #include <linux/init.h>\n #include <linux/poll.h>\n@@ -34,7 +45,13 @@\n #include <linux/delay.h>\n #include <linux/interrupt.h>\n #ifdef LINUX_2_6\n+#ifndef UTS_RELEASE\n+#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 33)\n #include <linux/utsrelease.h>\n+#else\n+#include <generated/utsrelease.h>\n+#endif\n+#endif /* UTC_RELEASE */\n #else /* */\n #include <linux/uts.h>\n #include <linux/moduleparam.h>\n@@ -94,8 +111,13 @@ IFX_int32_t ifx_mps_get_status_proc (IFX\n #ifndef __KERNEL__\n IFX_int32_t ifx_mps_open (struct inode *inode, struct file *file_p);\n IFX_int32_t ifx_mps_close (struct inode *inode, struct file *file_p);\n+#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 37)\n IFX_int32_t ifx_mps_ioctl (struct inode *inode, struct file *file_p,\n                            IFX_uint32_t nCmd, IFX_ulong_t arg);\n+#else\n+long ifx_mps_ioctl (struct file *file_p,\n+                           IFX_uint32_t nCmd, IFX_ulong_t arg);\n+#endif\n IFX_int32_t ifx_mps_read_mailbox (mps_devices type, mps_message * rw);\n IFX_int32_t ifx_mps_write_mailbox (mps_devices type, mps_message * rw);\n IFX_int32_t ifx_mps_register_data_callback (mps_devices type, IFX_uint32_t dir,\n@@ -155,7 +177,11 @@ IFX_char_t voice_channel_int_name[NUM_VO\n static struct file_operations ifx_mps_fops = {\n  owner:THIS_MODULE,\n  poll:ifx_mps_poll,\n+#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 37)\n  ioctl:ifx_mps_ioctl,\n+#else\n+ unlocked_ioctl:ifx_mps_ioctl,\n+#endif\n  open:ifx_mps_open,\n  release:ifx_mps_close\n };\n@@ -598,8 +624,13 @@ static IFX_uint32_t ifx_mps_poll (struct\n  * \\return  -ENOIOCTLCMD Invalid command\n  * \\ingroup API\n  */\n+#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 37)\n IFX_int32_t ifx_mps_ioctl (struct inode * inode, struct file * file_p,\n                            IFX_uint32_t nCmd, IFX_ulong_t arg)\n+#else\n+long ifx_mps_ioctl (struct file *file_p,\n+                           IFX_uint32_t nCmd, IFX_ulong_t arg)\n+#endif\n {\n    IFX_int32_t retvalue = -EINVAL;\n    mps_message rw_struct;\n@@ -613,17 +644,30 @@ IFX_int32_t ifx_mps_ioctl (struct inode\n       'mps_devices' enum type, which in fact is [0..8]; So, if inode value is\n       [0..NUM_VOICE_CHANNEL+1], then we make sure that we are calling from\n       kernel space. */\n+#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 37)\n    if (((IFX_int32_t) inode >= 0) &&\n        ((IFX_int32_t) inode < NUM_VOICE_CHANNEL + 1))\n+#else\n+   if (((IFX_int32_t) file_p >= 0) &&\n+       ((IFX_int32_t) file_p < NUM_VOICE_CHANNEL + 1))\n+#endif\n    {\n       from_kernel = 1;\n \n       /* Get corresponding mailbox device structure */\n       if ((pMBDev =\n+#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 37)\n            ifx_mps_get_device ((mps_devices) ((IFX_int32_t) inode))) == 0)\n+#else\n+           ifx_mps_get_device ((mps_devices) ((IFX_int32_t) file_p))) == 0)\n+#endif\n       {\n          return (-EINVAL);\n       }\n+#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 37)\n+#else\n+      file_p = NULL;\n+#endif\n    }\n    else\n    {\n--- a/src/mps/drv_mps_vmmc_common.c\n+++ b/src/mps/drv_mps_vmmc_common.c\n@@ -21,7 +21,11 @@\n #undef USE_PLAIN_VOICE_FIRMWARE\n #undef PRINT_ON_ERR_INTERRUPT\n #undef FAIL_ON_ERR_INTERRUPT\n+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,33))\n #include <linux/autoconf.h>\n+#else\n+#include <generated/autoconf.h>\n+#endif\n #include <linux/interrupt.h>\n #include <linux/delay.h>\n \n@@ -92,7 +96,9 @@ extern IFX_uint32_t danube_get_cpu_ver (\n extern mps_mbx_dev *ifx_mps_get_device (mps_devices type);\n \n #ifdef LINUX_2_6\n+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,39))\n extern IFX_void_t bsp_mask_and_ack_irq (IFX_uint32_t irq_nr);\n+#endif\n \n #else /* */\n extern IFX_void_t mask_and_ack_danube_irq (IFX_uint32_t irq_nr);\n--- a/src/mps/drv_mps_vmmc_danube.c\n+++ b/src/mps/drv_mps_vmmc_danube.c\n@@ -20,7 +20,11 @@\n \n #ifdef SYSTEM_DANUBE            /* defined in drv_mps_vmmc_config.h */\n \n+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,33))\n #include <linux/autoconf.h>\n+#else\n+#include <generated/autoconf.h>\n+#endif\n \n /* lib_ifxos headers */\n #include \"ifx_types.h\"\n--- a/configure.in\n+++ b/configure.in\n@@ -112,7 +112,7 @@ dnl Set kernel build path\n AC_ARG_ENABLE(kernelbuild,\n         AS_HELP_STRING(--enable-kernelbuild=x,Set the target kernel build path),\n         [\n-                if test -r $enableval/include/linux/autoconf.h; then\n+                if test -e $enableval/include/linux/autoconf.h -o -e $enableval/include/generated/autoconf.h; then\n                         AC_SUBST([KERNEL_BUILD_PATH],[$enableval])\n                 else\n                         AC_MSG_ERROR([The kernel build directory is not valid or not configured!])\n--- a/src/drv_vmmc_bbd.c\n+++ b/src/drv_vmmc_bbd.c\n@@ -1072,7 +1072,11 @@ static IFX_int32_t vmmc_BBD_DownloadChCr\n    IFX_uint8_t  padBytes = 0;\n #endif\n    IFX_uint16_t cram_offset, cram_crc,\n-                pCmd [MAX_CMD_WORD]  = {0};\n+                pCmd [MAX_CMD_WORD]\n+#if defined (__GNUC__) || defined (__GNUG__)\n+                   __attribute__ ((aligned(4)))\n+#endif\n+                   = {0};\n \n    /* read offset */\n    cpb2w (&cram_offset, &bbd_cram->pData[0], sizeof (IFX_uint16_t));\n--- a/src/drv_vmmc_init.c\n+++ b/src/drv_vmmc_init.c\n@@ -776,8 +776,13 @@ IFX_int32_t VMMC_TAPI_LL_FW_Start(IFX_TA\n       dwld.fwDwld.length = IoInit.pram_size;\n \n      /* download firmware */\n+#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 37)\n       ret = ifx_mps_ioctl((IFX_void_t *) command, IFX_NULL, FIO_MPS_DOWNLOAD,\n                           (IFX_uint32_t) &dwld.fwDwld);\n+#else\n+      ret = ifx_mps_ioctl((IFX_void_t *) command, FIO_MPS_DOWNLOAD,\n+                          (IFX_uint32_t) &dwld.fwDwld);\n+#endif\n    }\n \n    if (VMMC_SUCCESS(ret))\n--- a/src/drv_vmmc_ioctl.c\n+++ b/src/drv_vmmc_ioctl.c\n@@ -426,18 +426,31 @@ IFX_int32_t VMMC_Dev_Spec_Ioctl (IFX_TAP\n          /* MPS driver will do the USR2KERN so just pass on the pointer. */\n          dwnld_struct.data = (IFX_void_t *)IoInit.pPRAMfw;\n \n+#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 37)\n          ret = ifx_mps_ioctl((IFX_void_t *)command, IFX_NULL,\n                              FIO_MPS_DOWNLOAD, (IFX_uint32_t) &dwnld_struct);\n+#else\n+         ret = ifx_mps_ioctl((IFX_void_t *)command,\n+                             FIO_MPS_DOWNLOAD, (IFX_uint32_t) &dwnld_struct);\n+#endif\n          break;\n       }\n       case FIO_DEV_RESET:\n       {\n+#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 37)\n          ret = ifx_mps_ioctl((IFX_void_t *)command, IFX_NULL, FIO_MPS_RESET, 0);\n+#else\n+         ret = ifx_mps_ioctl((IFX_void_t *)command, FIO_MPS_RESET, 0);\n+#endif\n          break;\n       }\n       case FIO_DEV_RESTART:\n       {\n+#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 37)\n          ret = ifx_mps_ioctl((IFX_void_t *)command, IFX_NULL, FIO_MPS_RESTART, 0);\n+#else\n+         ret = ifx_mps_ioctl((IFX_void_t *)command, FIO_MPS_RESTART, 0);\n+#endif\n          break;\n       }\n       case FIO_LASTERR:\n--- a/src/mps/drv_mps_vmmc.h\n+++ b/src/mps/drv_mps_vmmc.h\n@@ -279,8 +279,13 @@ typedef struct\n #include <linux/fs.h>\n IFX_int32_t ifx_mps_open (struct inode *inode, struct file *file_p);\n IFX_int32_t ifx_mps_close (struct inode *inode, struct file *filp);\n+#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 37)\n IFX_int32_t ifx_mps_ioctl (struct inode *inode, struct file *file_p,\n                            IFX_uint32_t nCmd, unsigned long arg);\n+#else\n+long ifx_mps_ioctl (struct file *filp,\n+                           IFX_uint32_t nCmd, unsigned long arg);\n+#endif\n IFX_int32_t ifx_mps_register_data_callback (mps_devices type, IFX_uint32_t dir,\n                                             IFX_void_t (*callback) (mps_devices\n                                                                     type));\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-vmmc/patches/020-not-leak-cflags.patch",
    "content": "--- a/src/Makefile.am\n+++ b/src/Makefile.am\n@@ -224,7 +224,6 @@ install-exec-hook: $(bin_PROGRAMS)\n \n # Extra rule for linux-2.6 kernel object\n if KERNEL_2_6\n-drv_vmmc_CFLAGS += -fno-common\n drv_vmmc_OBJS = \"$(subst .c,.o, $(drv_vmmc_SOURCES) $(nodist_drv_vmmc_SOURCES))\"\n \n drv_vmmc.ko: $(drv_vmmc_SOURCES) $(EXTRA_DIST)\n@@ -239,7 +238,7 @@ drv_vmmc.ko: $(drv_vmmc_SOURCES) $(EXTRA\n \t@echo \"# drv_vmmc: Generated to build Linux 2.6.x kernel object\" > $(PWD)/Kbuild\n \t@echo \"obj-m := $(subst .ko,.o,$@)\"\t\t\t>> $(PWD)/Kbuild\n \t@echo \"$(subst .ko,,$@)-y := $(drv_vmmc_OBJS)\"\t>> $(PWD)/Kbuild\n-\t@echo \"EXTRA_CFLAGS := -DHAVE_CONFIG_H  $(CFLAGS) $(drv_vmmc_CFLAGS) $(INCLUDES)\"\t>> $(PWD)/Kbuild\n+\t@echo \"EXTRA_CFLAGS := -DHAVE_CONFIG_H $(drv_vmmc_CFLAGS) $(INCLUDES)\"\t>> $(PWD)/Kbuild\n \t$(MAKE) ARCH=@KERNEL_ARCH@ -C @KERNEL_BUILD_PATH@ O=@KERNEL_BUILD_PATH@ M=$(PWD) modules\n \n clean-generic:\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-vmmc/patches/100-target.patch",
    "content": "--- a/src/drv_vmmc_access.h\n+++ b/src/drv_vmmc_access.h\n@@ -24,6 +24,10 @@\n #include \"drv_mps_vmmc.h\"\n #endif\n \n+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,28))\n+#  define IFX_MPS IFXMIPS_MPS_BASE_ADDR\n+#endif\n+\n /* ============================= */\n /* Global Defines                */\n /* ============================= */\n--- a/src/drv_vmmc_danube.h\n+++ b/src/drv_vmmc_danube.h\n@@ -15,56 +15,18 @@\n */\n \n #if defined SYSTEM_DANUBE\n-#include <asm/ifx/ifx_gpio.h>\n+#include <lantiq_soc.h>\n+\n #else\n #error no system selected\n #endif\n \n-#define VMMC_TAPI_GPIO_MODULE_ID                        IFX_GPIO_MODULE_TAPI_VMMC\n+#define VMMC_TAPI_GPIO_MODULE_ID             IFX_GPIO_MODULE_TAPI_VMMC\n /**\n \n */\n #define VMMC_PCM_IF_CFG_HOOK(mode, GPIOreserved, ret) \\\n do { \\\n-   ret = VMMC_statusOk; \\\n-   /* Reserve P0.0 as TDM/FSC */ \\\n-   if (!GPIOreserved) \\\n-      ret |= ifx_gpio_pin_reserve(IFX_GPIO_PIN_ID(0, 0), VMMC_TAPI_GPIO_MODULE_ID); \\\n-   ret |= ifx_gpio_altsel0_set(IFX_GPIO_PIN_ID(0, 0), VMMC_TAPI_GPIO_MODULE_ID); \\\n-   ret |= ifx_gpio_altsel1_set(IFX_GPIO_PIN_ID(0, 0), VMMC_TAPI_GPIO_MODULE_ID); \\\n-   ret |= ifx_gpio_open_drain_set(IFX_GPIO_PIN_ID(0, 0), VMMC_TAPI_GPIO_MODULE_ID);\\\n-   \\\n-   /* Reserve P1.9 as TDM/DO */ \\\n-   if (!GPIOreserved) \\\n-      ret |= ifx_gpio_pin_reserve(IFX_GPIO_PIN_ID(1, 9), VMMC_TAPI_GPIO_MODULE_ID); \\\n-   ret |= ifx_gpio_altsel0_set(IFX_GPIO_PIN_ID(1, 9), VMMC_TAPI_GPIO_MODULE_ID); \\\n-   ret |= ifx_gpio_altsel1_clear(IFX_GPIO_PIN_ID(1, 9), VMMC_TAPI_GPIO_MODULE_ID); \\\n-   ret |= ifx_gpio_dir_out_set(IFX_GPIO_PIN_ID(1, 9), VMMC_TAPI_GPIO_MODULE_ID); \\\n-   ret |= ifx_gpio_open_drain_set(IFX_GPIO_PIN_ID(1, 9), VMMC_TAPI_GPIO_MODULE_ID); \\\n-   \\\n-   /* Reserve P1.10 as TDM/DI */ \\\n-   if (!GPIOreserved) \\\n-      ret |= ifx_gpio_pin_reserve(IFX_GPIO_PIN_ID(1,10), VMMC_TAPI_GPIO_MODULE_ID); \\\n-   ret |= ifx_gpio_altsel0_clear(IFX_GPIO_PIN_ID(1,10), VMMC_TAPI_GPIO_MODULE_ID); \\\n-   ret |= ifx_gpio_altsel1_set(IFX_GPIO_PIN_ID(1,10), VMMC_TAPI_GPIO_MODULE_ID);\\\n-   ret |= ifx_gpio_dir_in_set(IFX_GPIO_PIN_ID(1,10), VMMC_TAPI_GPIO_MODULE_ID); \\\n-   \\\n-   /* Reserve P1.11 as TDM/DCL */ \\\n-   if (!GPIOreserved) \\\n-      ret |= ifx_gpio_pin_reserve(IFX_GPIO_PIN_ID(1,11), VMMC_TAPI_GPIO_MODULE_ID); \\\n-   ret |= ifx_gpio_altsel0_set(IFX_GPIO_PIN_ID(1,11), VMMC_TAPI_GPIO_MODULE_ID); \\\n-   ret |= ifx_gpio_altsel1_clear(IFX_GPIO_PIN_ID(1,11), VMMC_TAPI_GPIO_MODULE_ID); \\\n-   ret |= ifx_gpio_open_drain_set(IFX_GPIO_PIN_ID(1,11), VMMC_TAPI_GPIO_MODULE_ID); \\\n-   \\\n-   if (mode == 2) { \\\n-      /* TDM/FSC+DCL Master */ \\\n-      ret |= ifx_gpio_dir_out_set(IFX_GPIO_PIN_ID(0, 0), VMMC_TAPI_GPIO_MODULE_ID); \\\n-      ret |= ifx_gpio_dir_out_set(IFX_GPIO_PIN_ID(1,11), VMMC_TAPI_GPIO_MODULE_ID); \\\n-   } else { \\\n-      /* TDM/FSC+DCL Slave */ \\\n-      ret |= ifx_gpio_dir_in_set(IFX_GPIO_PIN_ID(0, 0), VMMC_TAPI_GPIO_MODULE_ID); \\\n-      ret |= ifx_gpio_dir_in_set(IFX_GPIO_PIN_ID(1,11), VMMC_TAPI_GPIO_MODULE_ID); \\\n-   } \\\n } while(0);\n \n /**\n@@ -72,11 +34,6 @@ do { \\\n */\n #define VMMC_DRIVER_UNLOAD_HOOK(ret) \\\n do { \\\n-   ret = VMMC_statusOk; \\\n-   ret |= ifx_gpio_pin_free(IFX_GPIO_PIN_ID(0, 0), VMMC_TAPI_GPIO_MODULE_ID); \\\n-   ret |= ifx_gpio_pin_free(IFX_GPIO_PIN_ID(1, 9), VMMC_TAPI_GPIO_MODULE_ID); \\\n-   ret |= ifx_gpio_pin_free(IFX_GPIO_PIN_ID(1,10), VMMC_TAPI_GPIO_MODULE_ID); \\\n-   ret |= ifx_gpio_pin_free(IFX_GPIO_PIN_ID(1,11), VMMC_TAPI_GPIO_MODULE_ID); \\\n } while (0)\n \n #endif /* _DRV_VMMC_AMAZON_S_H */\n--- a/src/drv_vmmc_init.c\n+++ b/src/drv_vmmc_init.c\n@@ -52,6 +52,14 @@\n #include \"ifx_pmu.h\"\n #endif /* PMU_SUPPORTED */\n \n+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,28))\n+#  define IFX_MPS_CAD0SR IFXMIPS_MPS_CAD0SR\n+#  define IFX_MPS_CAD1SR IFXMIPS_MPS_CAD1SR\n+#  define IFX_MPS_CVC0SR IFXMIPS_MPS_CVC0SR\n+#  define IFX_MPS_CVC1SR IFXMIPS_MPS_CVC1SR\n+#  define IFX_MPS_CVC2SR IFXMIPS_MPS_CVC2SR\n+#  define IFX_MPS_CVC3SR IFXMIPS_MPS_CVC3SR\n+#endif\n \n /* ============================= */\n /* Local Macros & Definitions    */\n@@ -1591,7 +1599,7 @@ IFX_void_t VMMC_DeviceDriverStop(IFX_voi\n #ifdef VMMC_DRIVER_UNLOAD_HOOK\n    if (VDevices[0].nDevState & DS_GPIO_RESERVED)\n    {\n-      IFX_int32_t ret;\n+      IFX_int32_t ret = 0;\n       VMMC_DRIVER_UNLOAD_HOOK(ret);\n       if (!VMMC_SUCCESS(ret))\n       {\n--- a/src/drv_vmmc_init_cap.c\n+++ b/src/drv_vmmc_init_cap.c\n@@ -22,6 +22,11 @@\n #include \"drv_mps_vmmc.h\"\n #include \"drv_mps_vmmc_device.h\"\n \n+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,28))\n+#  define IFX_MPS_CHIPID_VERSION_GET   IFXMIPS_MPS_CHIPID_VERSION_GET\n+#  define IFX_MPS_CHIPID               IFXMIPS_MPS_CHIPID\n+#endif\n+\n /* ============================= */\n /* Configuration defintions      */\n /* ============================= */\n--- a/src/mps/drv_mps_vmmc_common.c\n+++ b/src/mps/drv_mps_vmmc_common.c\n@@ -17,6 +17,7 @@\n /* Includes                      */\n /* ============================= */\n #include \"drv_config.h\"\n+#include \"drv_vmmc_init.h\"\n \n #undef USE_PLAIN_VOICE_FIRMWARE\n #undef PRINT_ON_ERR_INTERRUPT\n@@ -39,8 +40,32 @@\n #include \"ifxos_interrupt.h\"\n #include \"ifxos_time.h\"\n \n-#include <asm/ifx/ifx_regs.h>\n-#include <asm/ifx/ifx_gptu.h>\n+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,28))\n+#  include <lantiq.h>\n+#  include <linux/irq.h>\n+#  include <lantiq_timer.h>\n+\n+#  define ifx_gptu_timer_request    lq_request_timer\n+#  define ifx_gptu_timer_start      lq_start_timer\n+#  define ifx_gptu_countvalue_get   lq_get_count_value\n+#  define ifx_gptu_timer_free       lq_free_timer\n+\n+\n+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,39))\n+#  define bsp_mask_and_ack_irq      ltq_mask_and_ack_irq\n+#else\n+extern void ltq_mask_and_ack_irq(struct irq_data *d);\n+static void inline bsp_mask_and_ack_irq(int x)\n+{\n+\tstruct irq_data d;\n+\td.hwirq = x;\n+\tltq_mask_and_ack_irq(&d);\n+}\n+#endif\n+#else\n+#  include <asm/ifx/ifx_regs.h>\n+#  include <asm/ifx/ifx_gptu.h>\n+#endif\n \n #include \"drv_mps_vmmc.h\"\n #include \"drv_mps_vmmc_dbg.h\"\n@@ -104,6 +129,9 @@ extern IFX_void_t bsp_mask_and_ack_irq (\n extern IFX_void_t mask_and_ack_danube_irq (IFX_uint32_t irq_nr);\n \n #endif /* */\n+\n+extern void sys_hw_setup (void);\n+\n extern IFXOS_event_t fw_ready_evt;\n /* callback function to free all data buffers currently used by voice FW */\n IFX_void_t (*ifx_mps_bufman_freeall)(IFX_void_t) = IFX_NULL;\n@@ -207,7 +235,8 @@ IFX_boolean_t ifx_mps_ext_bufman ()\n  */\n IFX_void_t *ifx_mps_fastbuf_malloc (IFX_size_t size, IFX_int32_t priority)\n {\n-   IFX_uint32_t ptr, flags;\n+   IFXOS_INTSTAT flags;\n+   IFX_uint32_t ptr;\n    IFX_int32_t index = fastbuf_index;\n \n    if (fastbuf_initialized == 0)\n@@ -261,7 +290,7 @@ IFX_void_t *ifx_mps_fastbuf_malloc (IFX_\n  */\n IFX_void_t ifx_mps_fastbuf_free (const IFX_void_t * ptr)\n {\n-   IFX_uint32_t flags;\n+   IFXOS_INTSTAT flags;\n    IFX_int32_t index = fastbuf_index;\n \n    IFXOS_LOCKINT (flags);\n@@ -457,7 +486,7 @@ static mps_buffer_state_e ifx_mps_bufman\n  */\n static IFX_int32_t ifx_mps_bufman_inc_level (IFX_uint32_t value)\n {\n-   IFX_uint32_t flags;\n+   IFXOS_INTSTAT flags;\n \n    if (mps_buffer.buf_level + value > MPS_BUFFER_MAX_LEVEL)\n    {\n@@ -484,7 +513,7 @@ static IFX_int32_t ifx_mps_bufman_inc_le\n  */\n static IFX_int32_t ifx_mps_bufman_dec_level (IFX_uint32_t value)\n {\n-   IFX_uint32_t flags;\n+   IFXOS_INTSTAT flags;\n \n    if (mps_buffer.buf_level < value)\n    {\n@@ -636,7 +665,7 @@ IFX_int32_t ifx_mps_bufman_buf_provide (\n       mem_seg_ptr[i] =\n          (IFX_uint32_t *) CPHYSADDR ((IFX_uint32_t) mps_buffer.\n                                      malloc (segment_size, FASTBUF_FW_OWNED));\n-      if (mem_seg_ptr[i] == CPHYSADDR (IFX_NULL))\n+      if (mem_seg_ptr[i] == (IFX_uint32_t *)CPHYSADDR (IFX_NULL))\n       {\n          TRACE (MPS, DBG_LEVEL_HIGH,\n                 (\"%s(): cannot allocate buffer\\n\", __FUNCTION__));\n@@ -952,7 +981,7 @@ IFX_int32_t ifx_mps_common_open (mps_com\n                                  mps_mbx_dev * pMBDev, IFX_int32_t bcommand,\n                                  IFX_boolean_t from_kernel)\n {\n-   IFX_uint32_t flags;\n+   IFXOS_INTSTAT flags;\n \n    IFXOS_LOCKINT (flags);\n \n@@ -1068,7 +1097,7 @@ IFX_int32_t ifx_mps_common_close (mps_mb\n IFX_void_t ifx_mps_release_structures (mps_comm_dev * pDev)\n {\n    IFX_int32_t count;\n-   IFX_uint32_t flags;\n+   IFXOS_INTSTAT flags;\n \n    IFXOS_LOCKINT (flags);\n    IFXOS_BlockFree (pFW_img_data);\n@@ -1117,7 +1146,7 @@ IFX_uint32_t ifx_mps_init_structures (mp\n \n    /* Initialize MPS main structure */\n    memset ((IFX_void_t *) pDev, 0, sizeof (mps_comm_dev));\n-   pDev->base_global = (mps_mbx_reg *) IFX_MPS_SRAM;\n+   pDev->base_global = (mps_mbx_reg *) IFXMIPS_MPS_SRAM;\n    pDev->flags = 0x00000000;\n    MBX_Memory = pDev->base_global;\n \n@@ -1125,9 +1154,11 @@ IFX_uint32_t ifx_mps_init_structures (mp\n       for MBX communication. These are: mailbox base address, mailbox size, *\n       mailbox read index and mailbox write index. for command and voice\n       mailbox, * upstream and downstream direction. */\n-   memset ((IFX_void_t *) MBX_Memory,   /* avoid to overwrite CPU boot\n-                                           registers */\n-           0, sizeof (mps_mbx_reg) - 2 * sizeof (mps_boot_cfg_reg));\n+   memset (\n+\t/* avoid to overwrite CPU boot registers */\n+\t   (IFX_void_t *) MBX_Memory,\n+           0,\n+           sizeof (mps_mbx_reg) - 2 * sizeof (mps_boot_cfg_reg));\n    MBX_Memory->MBX_UPSTR_CMD_BASE =\n       (IFX_uint32_t *) CPHYSADDR ((IFX_uint32_t) MBX_UPSTRM_CMD_FIFO_BASE);\n    MBX_Memory->MBX_UPSTR_CMD_SIZE = MBX_CMD_FIFO_SIZE;\n@@ -1564,7 +1595,7 @@ IFX_int32_t ifx_mps_mbx_read_message (mp\n                                       IFX_uint32_t * bytes)\n {\n    IFX_int32_t i, ret;\n-   IFX_uint32_t flags;\n+   IFXOS_INTSTAT flags;\n \n    IFXOS_LOCKINT (flags);\n \n@@ -1774,7 +1805,7 @@ IFX_int32_t ifx_mps_mbx_write_message (m\n {\n    mps_fifo *mbx;\n    IFX_uint32_t i;\n-   IFX_uint32_t flags;\n+   IFXOS_INTSTAT flags;\n    IFX_int32_t retval = -EAGAIN;\n    IFX_int32_t retries = 0;\n    IFX_uint32_t word = 0;\n@@ -2169,6 +2200,7 @@ IFX_int32_t ifx_mps_mbx_write_cmd (mps_m\n       TRACE (MPS, DBG_LEVEL_HIGH,\n              (\"%s(): Invalid device ID %d !\\n\", __FUNCTION__, pMBDev->devID));\n    }\n+\n    return retval;\n }\n \n@@ -2192,7 +2224,7 @@ IFX_void_t ifx_mps_mbx_data_upstream (IF\n    mps_mbx_dev *mbx_dev;\n    MbxMsg_s msg;\n    IFX_uint32_t bytes_read = 0;\n-   IFX_uint32_t flags;\n+   IFXOS_INTSTAT flags;\n    IFX_int32_t ret;\n \n    /* set pointer to data upstream mailbox, no matter if 0,1,2 or 3 because\n@@ -2283,7 +2315,7 @@ IFX_void_t ifx_mps_mbx_data_upstream (IF\n          {\n             ifx_mps_bufman_dec_level (1);\n             if ((ifx_mps_bufman_get_level () <= mps_buffer.buf_threshold) &&\n-                (atomic_read (&pMPSDev->provide_buffer->object.count) == 0))\n+                ((volatile unsigned int)pMPSDev->provide_buffer->object.count == 0))\n             {\n                IFXOS_LockRelease (pMPSDev->provide_buffer);\n             }\n@@ -2326,7 +2358,7 @@ IFX_void_t ifx_mps_mbx_data_upstream (IF\n #endif /* CONFIG_PROC_FS */\n             ifx_mps_bufman_dec_level (1);\n             if ((ifx_mps_bufman_get_level () <= mps_buffer.buf_threshold) &&\n-                (atomic_read (&pMPSDev->provide_buffer->object.count) == 0))\n+                ((volatile unsigned int)pMPSDev->provide_buffer->object.count == 0))\n             {\n                IFXOS_LockRelease (pMPSDev->provide_buffer);\n             }\n@@ -2356,7 +2388,7 @@ IFX_void_t ifx_mps_mbx_data_upstream (IF\n IFX_void_t ifx_mps_mbx_cmd_upstream (IFX_ulong_t dummy)\n {\n    mps_fifo *mbx;\n-   IFX_uint32_t flags;\n+   IFXOS_INTSTAT flags;\n \n    /* set pointer to upstream command mailbox */\n    mbx = &(pMPSDev->cmd_upstrm_fifo);\n@@ -2404,7 +2436,7 @@ IFX_void_t ifx_mps_mbx_event_upstream (I\n    mps_event_msg msg;\n    IFX_int32_t length = 0;\n    IFX_int32_t read_length = 0;\n-   IFX_uint32_t flags;\n+   IFXOS_INTSTAT flags;\n \n    /* set pointer to upstream event mailbox */\n    mbx = &(pMPSDev->event_upstrm_fifo);\n@@ -2619,6 +2651,7 @@ IFX_void_t ifx_mps_enable_mailbox_int ()\n #endif\n \n    *IFX_MPS_AD0ENR = Ad0Reg.val;\n+\n }\n \n /**\n@@ -2647,7 +2680,7 @@ IFX_void_t ifx_mps_disable_mailbox_int (\n */\n IFX_void_t ifx_mps_dd_mbx_int_enable (IFX_void_t)\n {\n-   IFX_uint32_t flags;\n+   IFXOS_INTSTAT flags;\n    MPS_Ad0Reg_u Ad0Reg;\n \n    IFXOS_LOCKINT (flags);\n@@ -2673,7 +2706,7 @@ IFX_void_t ifx_mps_dd_mbx_int_enable (IF\n */\n IFX_void_t ifx_mps_dd_mbx_int_disable (IFX_void_t)\n {\n-   IFX_uint32_t flags;\n+   IFXOS_INTSTAT flags;\n    MPS_Ad0Reg_u Ad0Reg;\n \n    IFXOS_LOCKINT (flags);\n@@ -2738,7 +2771,6 @@ irqreturn_t ifx_mps_ad0_irq (IFX_int32_t\n #else /* */\n    mask_and_ack_danube_irq (irq);\n #endif /* */\n-\n    /* FW is up and ready to process commands */\n    if (MPS_Ad0StatusReg.fld.dl_end)\n    {\n@@ -2800,6 +2832,7 @@ irqreturn_t ifx_mps_ad0_irq (IFX_int32_t\n       }\n    }\n \n+\n    if (MPS_Ad0StatusReg.fld.du_mbx)\n    {\n #ifdef CONFIG_PROC_FS\n@@ -2944,12 +2977,12 @@ irqreturn_t ifx_mps_vc_irq (IFX_int32_t\n    IFX_MPS_CVC0SR[chan] = MPS_VCStatusReg.val;\n    /* handle only enabled interrupts */\n    MPS_VCStatusReg.val &= IFX_MPS_VC0ENR[chan];\n-\n #ifdef LINUX_2_6\n    bsp_mask_and_ack_irq (irq);\n #else /* */\n    mask_and_ack_danube_irq (irq);\n #endif /* */\n+\n    pMPSDev->event.MPS_VCStatReg[chan].val = MPS_VCStatusReg.val;\n #ifdef PRINT_ON_ERR_INTERRUPT\n    if (MPS_VCStatusReg.fld.rcv_ov)\n@@ -3093,7 +3126,8 @@ IFX_int32_t ifx_mps_get_fw_version (IFX_\n  */\n IFX_return_t ifx_mps_init_gpt ()\n {\n-   IFX_uint32_t flags, timer_flags, timer, loops = 0;\n+   unsigned long flags;\n+   IFX_uint32_t timer_flags, timer, loops = 0;\n    IFX_ulong_t count;\n #if defined(SYSTEM_AR9) || defined(SYSTEM_VR9)\n    timer = TIMER1A;\n@@ -3166,6 +3200,7 @@ IFX_void_t ifx_mps_shutdown_gpt (IFX_voi\n #else /* Danube */\n    timer = TIMER1B;\n #endif /* SYSTEM_AR9 || SYSTEM_VR9 */\n+\n    ifx_gptu_timer_free (timer);\n }\n \n--- a/src/mps/drv_mps_vmmc_danube.c\n+++ b/src/mps/drv_mps_vmmc_danube.c\n@@ -16,6 +16,7 @@\n /* ============================= */\n /* Includes                      */\n /* ============================= */\n+#include \"linux/version.h\"\n #include \"drv_config.h\"\n \n #ifdef SYSTEM_DANUBE            /* defined in drv_mps_vmmc_config.h */\n@@ -36,9 +37,22 @@\n #include \"ifxos_select.h\"\n #include \"ifxos_interrupt.h\"\n \n-#include <asm/ifx/ifx_regs.h>\n-#include <asm/ifx/ifx_gpio.h>\n-#include <asm/ifx/common_routines.h>\n+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,28))\n+#  include <lantiq.h>\n+#  include <linux/irq.h>\n+#  include <lantiq_timer.h>\n+#  include <linux/dma-mapping.h>\n+\n+\n+#define LQ_RCU_BASE_ADDR\t(KSEG1 + 0x1F203000)\n+# define LQ_RCU_RST\t\t((u32 *)(LQ_RCU_BASE_ADDR + 0x0010))\n+#define IFX_RCU_RST_REQ_CPU1             (1 << 3)\n+#  define IFX_RCU_RST_REQ        LQ_RCU_RST\n+#else\n+#  include <asm/ifx/ifx_regs.h>\n+#  include <asm/ifx_vpe.h>\n+#  include <asm/ifx/ifx_gpio.h>\n+#endif\n \n #include \"drv_mps_vmmc.h\"\n #include \"drv_mps_vmmc_dbg.h\"\n@@ -75,6 +89,20 @@ IFX_void_t ifx_mps_release (IFX_void_t);\n /* Local function definition     */\n /* ============================= */\n \n+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,28))\n+IFX_uint32_t ifx_get_cp1_size(IFX_void_t)\n+{\n+\treturn 1;\n+}\n+\n+unsigned int *ltq_get_cp1_base(void);\n+\n+IFX_uint32_t *ifx_get_cp1_base(IFX_void_t)\n+{\n+\treturn ltq_get_cp1_base();\n+}\n+#endif\n+\n /******************************************************************************\n  * DANUBE Specific Routines\n  ******************************************************************************/\n@@ -134,6 +162,15 @@ IFX_int32_t ifx_mps_download_firmware (m\n    }\n \n    /* check if FW image fits in available memory space */\n+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,28))\n+   if (mem > ifx_get_cp1_size()<<20)\n+   {\n+      TRACE (MPS, DBG_LEVEL_HIGH,\n+      (\"[%s %s %d]: error, firmware memory exceeds reserved space (%i > %i)!\\n\",\n+                 __FILE__, __func__, __LINE__, mem, ifx_get_cp1_size()<<20));\n+      return IFX_ERROR;\n+   }\n+#else\n    if (mem > ifx_get_cp1_size())\n    {\n       TRACE (MPS, DBG_LEVEL_HIGH,\n@@ -141,6 +178,7 @@ IFX_int32_t ifx_mps_download_firmware (m\n                  __FILE__, __func__, __LINE__, mem, ifx_get_cp1_size()));\n       return IFX_ERROR;\n    }\n+#endif\n \n    /* reset the driver */\n    ifx_mps_reset ();\n@@ -361,7 +399,7 @@ IFX_void_t ifx_mps_release (IFX_void_t)\n  */\n IFX_void_t ifx_mps_wdog_expiry()\n {\n-   IFX_uint32_t flags;\n+   unsigned long flags;\n \n    IFXOS_LOCKINT (flags);\n    /* recalculate and compare the firmware checksum */\n--- a/src/mps/drv_mps_vmmc_device.h\n+++ b/src/mps/drv_mps_vmmc_device.h\n@@ -16,8 +16,58 @@\n                  declarations.\n *******************************************************************************/\n \n-#include <asm/ifx/ifx_regs.h>\n-#include <asm/ifx_vpe.h>\n+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,28))\n+#  include <lantiq.h>\n+#  include <linux/irq.h>\n+#  include <lantiq_soc.h>\n+#  include <linux/gpio.h>\n+#define IFXMIPS_MPS_SRAM\t\t((u32 *)(KSEG1 + 0x1F200000))\n+#define IFXMIPS_MPS_BASE_ADDR\t\t(KSEG1 + 0x1F107000)\n+#define IFXMIPS_MPS_CHIPID\t\t((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0344))\n+#define IFXMIPS_MPS_VC0ENR\t\t((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0000))\n+#define IFXMIPS_MPS_RVC0SR\t\t((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0010))\n+#define IFXMIPS_MPS_CVC0SR\t\t((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0030))\n+#define IFXMIPS_MPS_CVC1SR\t\t((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0034))\n+#define IFXMIPS_MPS_CVC2SR\t\t((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0038))\n+#define IFXMIPS_MPS_CVC3SR\t\t((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x003C))\n+#define IFXMIPS_MPS_RAD0SR\t\t((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0040))\n+#define IFXMIPS_MPS_RAD1SR\t\t((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0044))\n+#define IFXMIPS_MPS_SAD0SR\t\t((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0048))\n+#define IFXMIPS_MPS_SAD1SR\t\t((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x004C))\n+#define IFXMIPS_MPS_CAD0SR\t\t((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0050))\n+#define IFXMIPS_MPS_CAD1SR\t\t((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0054))\n+#define IFXMIPS_MPS_AD0ENR\t\t((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0058))\n+#define IFXMIPS_MPS_AD1ENR\t\t((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x005C))\n+\n+#define IFXMIPS_MPS_CHIPID_VERSION_GET(value)\t(((value) >> 28) & ((1 << 4) - 1))\n+#define IFXMIPS_MPS_CHIPID_VERSION_SET(value)\t((((1 << 4) - 1) & (value)) << 28)\n+#define IFXMIPS_MPS_CHIPID_PARTNUM_GET(value)\t(((value) >> 12) & ((1 << 16) - 1))\n+#define IFXMIPS_MPS_CHIPID_PARTNUM_SET(value)\t((((1 << 16) - 1) & (value)) << 12)\n+#define IFXMIPS_MPS_CHIPID_MANID_GET(value)\t(((value) >> 1) & ((1 << 10) - 1))\n+#define IFXMIPS_MPS_CHIPID_MANID_SET(value)\t((((1 << 10) - 1) & (value)) << 1)\n+#else\n+#  include <asm/ifx/ifx_regs.h>\n+#  include <asm/ifx_vpe.h>\n+#endif\n+/* MPS register */\n+#  define IFX_MPS_AD0ENR      IFXMIPS_MPS_AD0ENR\n+#  define IFX_MPS_AD1ENR      IFXMIPS_MPS_AD1ENR\n+#  define IFX_MPS_RAD0SR      IFXMIPS_MPS_RAD0SR\n+#  define IFX_MPS_RAD1SR      IFXMIPS_MPS_RAD1SR\n+#  define IFX_MPS_VC0ENR      IFXMIPS_MPS_VC0ENR\n+#  define IFX_MPS_RVC0SR      IFXMIPS_MPS_RVC0SR\n+#  define IFX_MPS_CVC0SR      IFXMIPS_MPS_CVC0SR\n+#  define IFX_MPS_CAD0SR      IFXMIPS_MPS_CAD0SR\n+#  define IFX_MPS_CAD1SR      IFXMIPS_MPS_CAD1SR\n+#  define IFX_MPS_CVC1SR      IFXMIPS_MPS_CVC1SR\n+#  define IFX_MPS_CVC2SR      IFXMIPS_MPS_CVC2SR\n+#  define IFX_MPS_CVC3SR      IFXMIPS_MPS_CVC3SR\n+#  define IFX_MPS_SAD0SR      IFXMIPS_MPS_SAD0SR\n+/* interrupt vectors */\n+#  define INT_NUM_IM4_IRL14   (INT_NUM_IM4_IRL0 + 14)\n+#  define INT_NUM_IM4_IRL18   (INT_NUM_IM4_IRL0 + 18)\n+#  define INT_NUM_IM4_IRL19   (INT_NUM_IM4_IRL0 + 19)\n+#  define IFX_ICU_IM4_IER     IFXMIPS_ICU_IM4_IER\n \n /* ============================= */\n /* MPS Common defines            */\n@@ -26,32 +76,28 @@\n #define MPS_BASEADDRESS 0xBF107000\n #define MPS_RAD0SR      MPS_BASEADDRESS + 0x0004\n \n-#define MPS_RAD0SR_DU   (1<<0)\n-#define MPS_RAD0SR_CU   (1<<1)\n-\n #define MBX_BASEADDRESS 0xBF200000\n #define VCPU_BASEADDRESS 0xBF208000     /* 0xBF108000 */\n /*---------------------------------------------------------------------------*/\n+#if !defined(CONFIG_LANTIQ)\n+/* enabling interrupts is done with request_irq by the BSP\n+   The related code should not be needed anymore */\n #if defined(SYSTEM_AR9) || defined(SYSTEM_VR9)\n /* TODO: doublecheck - IM4 or different! */\n #define MPS_INTERRUPTS_ENABLE(X)  *((volatile IFX_uint32_t*) IFX_ICU_IM4_IER) |= X;\n #define MPS_INTERRUPTS_DISABLE(X) *((volatile IFX_uint32_t*) IFX_ICU_IM4_IER) &= ~X;\n-#define MPS_INTERRUPTS_CLEAR(X)   *((volatile IFX_uint32_t*) IFX_ICU_IM4_ISR) = X;\n-#define MPS_INTERRUPTS_SET(X)     *((volatile IFX_uint32_t*) IFX_ICU_IM4_IRSR) = X;/* |= ? */\n #else /* Danube */\n /* TODO: possibly needs to be changed to IM4 !!!!!! */\n #ifdef LINUX_2_6\n #define MPS_INTERRUPTS_ENABLE(X)  *((volatile IFX_uint32_t*) IFX_ICU_IM4_IER) |= X;\n #define MPS_INTERRUPTS_DISABLE(X) *((volatile IFX_uint32_t*) IFX_ICU_IM4_IER) &= ~X;\n-#define MPS_INTERRUPTS_CLEAR(X)   *((volatile IFX_uint32_t*) IFX_ICU_IM4_ISR) = X;\n-#define MPS_INTERRUPTS_SET(X)     *((volatile IFX_uint32_t*) IFX_ICU_IM4_IRSR) = X;/* |= ? */\n #else /* */\n #define MPS_INTERRUPTS_ENABLE(X)  *((volatile IFX_uint32_t*) DANUBE_ICU_IM5_IER) |= X;\n #define MPS_INTERRUPTS_DISABLE(X) *((volatile IFX_uint32_t*) DANUBE_ICU_IM5_IER) &= ~X;\n-#define MPS_INTERRUPTS_CLEAR(X)   *((volatile IFX_uint32_t*) DANUBE_ICU_IM5_ISR) = X;\n-#define MPS_INTERRUPTS_SET(X)     *((volatile IFX_uint32_t*) DANUBE_ICU_IM5_IRSR) = X;/* |= ? */\n #endif /* LINUX_2_6 */\n #endif /* SYSTEM_AR9 || SYSTEM_VR9 */\n+#endif /* !defined(CONFIG_LANTIQ) */\n+\n /*---------------------------------------------------------------------------*/\n \n /*---------------------------------------------------------------------------*/\n@@ -142,53 +188,9 @@\n #if defined(SYSTEM_AR9) || defined(SYSTEM_VR9)\n /* ***** Amazon-S specific defines ***** */\n #define IFX_MPS_Base      AMAZON_S_MPS\n-\n-//#define IFX_MPS_CHIPID              AMAZON_S_MPS_CHIPID\n-//#define IFX_MPS_CHIPID_VERSION_GET  AMAZON_S_MPS_CHIPID_VERSION_GET\n-\n-//#define IFX_MPS_AD0ENR    AMAZON_S_MPS_AD0ENR\n-//#define IFX_MPS_AD1ENR    AMAZON_S_MPS_AD1ENR\n-//#define IFX_MPS_VC0ENR    AMAZON_S_MPS_VC0ENR\n-//#define IFX_MPS_SAD0SR    AMAZON_S_MPS_SAD0SR\n-//#define IFX_MPS_RAD0SR    AMAZON_S_MPS_RAD0SR\n-//#define IFX_MPS_CAD0SR    AMAZON_S_MPS_CAD0SR\n-//#define IFX_MPS_RAD1SR    AMAZON_S_MPS_RAD1SR\n-//#define IFX_MPS_CAD1SR    AMAZON_S_MPS_CAD1SR\n-//#define IFX_MPS_RVC0SR    AMAZON_S_MPS_RVC0SR\n-//#define IFX_MPS_CVC0SR    AMAZON_S_MPS_CVC0SR\n-//#define IFX_MPS_CVC1SR    AMAZON_S_MPS_CVC1SR\n-//#define IFX_MPS_CVC2SR    AMAZON_S_MPS_CVC2SR\n-//#define IFX_MPS_CVC3SR    AMAZON_S_MPS_CVC3SR\n-\n-//#define IFX_MPS_SRAM      AMAZON_S_MPS_SRAM\n #else /* */\n /* ***** DANUBE specific defines ***** */\n #define IFX_MPS_Base      DANUBE_MPS\n-\n-//#define IFX_MPS_CHIPID    DANUBE_MPS_CHIPID\n-//#define IFX_MPS_CHIPID_VERSION_GET  DANUBE_MPS_CHIPID_VERSION_GET\n-//#define IFX_MPS_CHIPID_VERSION_SET  DANUBE_MPS_CHIPID_VERSION_SET\n-//#define IFX_MPS_CHIPID_PARTNUM_GET  DANUBE_MPS_CHIPID_PARTNUM_GET\n-//#define IFX_MPS_CHIPID_PARTNUM_SET  DANUBE_MPS_CHIPID_PARTNUM_SET\n-//#define IFX_MPS_CHIPID_MANID_GET    DANUBE_MPS_CHIPID_MANID_GET\n-//#define IFX_MPS_CHIPID_MANID_SET    DANUBE_MPS_CHIPID_MANID_SET\n-//#define IFX_MPS_SUBVER              DANUBE_MPS_SUBVER\n-\n-//#define IFX_MPS_AD0ENR    DANUBE_MPS_AD0ENR\n-//#define IFX_MPS_AD1ENR    DANUBE_MPS_AD1ENR\n-//#define IFX_MPS_VC0ENR    DANUBE_MPS_VC0ENR\n-//#define IFX_MPS_SAD0SR    DANUBE_MPS_SAD0SR\n-//#define IFX_MPS_RAD0SR    DANUBE_MPS_RAD0SR\n-//#define IFX_MPS_CAD0SR    DANUBE_MPS_CAD0SR\n-//#define IFX_MPS_RAD1SR    DANUBE_MPS_RAD1SR\n-//#define IFX_MPS_CAD1SR    DANUBE_MPS_CAD1SR\n-//#define IFX_MPS_RVC0SR    DANUBE_MPS_RVC0SR\n-//#define IFX_MPS_CVC0SR    DANUBE_MPS_CVC0SR\n-//#define IFX_MPS_CVC1SR    DANUBE_MPS_CVC1SR\n-//#define IFX_MPS_CVC2SR    DANUBE_MPS_CVC2SR\n-//#define IFX_MPS_CVC3SR    DANUBE_MPS_CVC3SR\n-\n-//#define IFX_MPS_SRAM      DANUBE_MPS_SRAM\n #endif /* SYSTEM_AR9 || SYSTEM_VR9 */\n typedef enum\n {\n--- a/src/mps/drv_mps_vmmc_linux.c\n+++ b/src/mps/drv_mps_vmmc_linux.c\n@@ -57,10 +57,11 @@\n #include <linux/moduleparam.h>\n #endif /* */\n \n-\n+#if !defined CONFIG_LANTIQ\n #include <asm/ifx/irq.h>\n #include <asm/ifx/ifx_regs.h>\n #include <asm/ifx_vpe.h>\n+#endif\n \n /* lib_ifxos headers */\n #include \"ifx_types.h\"\n@@ -959,7 +960,7 @@ long ifx_mps_ioctl (struct file *file_p,\n #endif /* MPS_FIFO_BLOCKING_WRITE */\n       case FIO_MPS_GET_STATUS:\n          {\n-            IFX_uint32_t flags;\n+            unsigned long flags;\n \n             /* get the status of the channel */\n             if (!from_kernel)\n@@ -993,7 +994,7 @@ long ifx_mps_ioctl (struct file *file_p,\n #if CONFIG_MPS_HISTORY_SIZE > 0\n       case FIO_MPS_GET_CMD_HISTORY:\n          {\n-            IFX_uint32_t flags;\n+            unsigned long flags;\n \n             if (from_kernel)\n             {\n@@ -1685,6 +1686,7 @@ IFX_int32_t ifx_mps_get_status_proc (IFX\n          sprintf (buf + len, \"   minLv: \\t  %8d\\n\",\n                   ifx_mps_dev.voice_mb[i].upstrm_fifo->min_space);\n    }\n+\n    return len;\n }\n \n@@ -2291,9 +2293,11 @@ IFX_int32_t __init ifx_mps_init_module (\n          return result;\n    }\n \n+#if !defined(CONFIG_LANTIQ)\n+   /** \\todo This is handled already with request_irq, remove */\n    /* Enable all MPS Interrupts at ICU0 */\n    MPS_INTERRUPTS_ENABLE (0x0000FF80);\n-\n+#endif\n    /* enable mailbox interrupts */\n    ifx_mps_enable_mailbox_int ();\n    /* init FW ready event */\n@@ -2421,9 +2425,11 @@ ifx_mps_cleanup_module (IFX_void_t)\n    /* disable mailbox interrupts */\n    ifx_mps_disable_mailbox_int ();\n \n+#if !defined(CONFIG_LANTIQ)\n    /* disable Interrupts at ICU0 */\n-   MPS_INTERRUPTS_DISABLE (DANUBE_MPS_AD0_IR4); /* Disable DFE/AFE 0 Interrupts\n-                                                 */\n+   /* Disable DFE/AFE 0 Interrupts*/\n+   MPS_INTERRUPTS_DISABLE (DANUBE_MPS_AD0_IR4);\n+#endif\n \n    /* disable all MPS interrupts */\n    ifx_mps_disable_all_int ();\n--- a/src/drv_vmmc_ioctl.c\n+++ b/src/drv_vmmc_ioctl.c\n@@ -18,6 +18,7 @@\n /* Includes                      */\n /* ============================= */\n #include \"drv_api.h\"\n+#include \"drv_vmmc_init.h\"\n #include \"drv_vmmc_api.h\"\n #include \"drv_vmmc_bbd.h\"\n \n"
  },
  {
    "path": "package/kernel/lantiq/ltq-vmmc/patches/200-compat.patch",
    "content": "--- a/src/drv_vmmc_linux.c\n+++ b/src/drv_vmmc_linux.c\n@@ -54,6 +54,8 @@\n #include \"drv_vmmc_res.h\"\n #endif /* (VMMC_CFG_FEATURES & VMMC_FEAT_HDLC) */\n \n+#undef VMMC_USE_PROC\n+\n /* ============================= */\n /* Local Macros & Definitions    */\n /* ============================= */\n--- a/src/mps/drv_mps_vmmc_linux.c\n+++ b/src/mps/drv_mps_vmmc_linux.c\n@@ -80,11 +80,15 @@\n /* ============================= */\n #define IFX_MPS_DEV_NAME       \"ifx_mps\"\n \n+#undef CONFIG_MPS_HISTORY_SIZE\n+#define CONFIG_MPS_HISTORY_SIZE 0\n #ifndef CONFIG_MPS_HISTORY_SIZE\n #define CONFIG_MPS_HISTORY_SIZE 128\n #warning CONFIG_MPS_HISTORY_SIZE should have been set via cofigure - setting to default 128\n #endif\n \n+#undef CONFIG_PROC_FS\n+\n /* ============================= */\n /* Global variable definition    */\n /* ============================= */\n@@ -2257,7 +2261,7 @@ IFX_int32_t __init ifx_mps_init_module (\n    ifx_mps_reset ();\n    result = request_irq (INT_NUM_IM4_IRL18,\n #ifdef LINUX_2_6\n-                         ifx_mps_ad0_irq, IRQF_DISABLED\n+                         ifx_mps_ad0_irq, 0x0\n #else /* */\n                          (irqreturn_t (*)(int, IFX_void_t *, struct pt_regs *))\n                          ifx_mps_ad0_irq, SA_INTERRUPT\n@@ -2267,7 +2271,7 @@ IFX_int32_t __init ifx_mps_init_module (\n       return result;\n    result = request_irq (INT_NUM_IM4_IRL19,\n #ifdef LINUX_2_6\n-                         ifx_mps_ad1_irq, IRQF_DISABLED\n+                         ifx_mps_ad1_irq, 0x0\n #else /* */\n                          (irqreturn_t (*)(int, IFX_void_t *, struct pt_regs *))\n                          ifx_mps_ad1_irq, SA_INTERRUPT\n@@ -2282,7 +2286,7 @@ IFX_int32_t __init ifx_mps_init_module (\n       sprintf (&voice_channel_int_name[i][0], \"mps_mbx vc%d\", i);\n       result = request_irq (INT_NUM_IM4_IRL14 + i,\n #ifdef LINUX_2_6\n-                            ifx_mps_vc_irq, IRQF_DISABLED\n+                            ifx_mps_vc_irq, 0x0\n #else /* */\n                             (irqreturn_t (*)\n                              (int, IFX_void_t *,\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-vmmc/patches/400-falcon.patch",
    "content": "--- a/configure.in\n+++ b/configure.in\n@@ -956,14 +956,15 @@ AC_DEFINE([VMMC],[1],[enable VMMC suppor\n AM_CONDITIONAL(DANUBE, false)\n AM_CONDITIONAL(AR9, false)\n AM_CONDITIONAL(VR9, false)\n+AM_CONDITIONAL(FALCON, false)\n AC_ARG_WITH(device,\n    AC_HELP_STRING(\n-      [--with-device=DANUBE|TWINPASS|AR9|VR9],\n+      [--with-device=DANUBE|TWINPASS|AR9|VR9|FALCON],\n       [Set device type, default is DANUBE]\n    ),\n    [\n       if test \"$withval\" = yes; then\n-         AC_MSG_ERROR([Set device type! Valid choices are DANUBE|TWINPASS|AR9|VR9]);\n+         AC_MSG_ERROR([Set device type! Valid choices are DANUBE|TWINPASS|AR9|VR9|FALCON]);\n       else\n          case $withval in\n            DANUBE)\n@@ -986,8 +987,13 @@ AC_ARG_WITH(device,\n                AC_DEFINE([SYSTEM_VR9],[1],[enable VR9 specific code])\n                AM_CONDITIONAL(VR9, true)\n            ;;\n+           FALCON)\n+               AC_MSG_RESULT(FALCON device is used);\n+               AC_DEFINE([SYSTEM_FALCON],[1],[enable FALCON specific code])\n+               AM_CONDITIONAL(FALCON, true)\n+           ;;\n            *)\n-               AC_MSG_ERROR([Set device type! Valid choices are DANUBE|TWINPASS|AR9|VR9]);\n+               AC_MSG_ERROR([Set device type! Valid choices are DANUBE|TWINPASS|AR9|VR9|FALCON]);\n            ;;\n        esac\n       fi\n--- a/src/Makefile.am\n+++ b/src/Makefile.am\n@@ -70,6 +70,11 @@ drv_vmmc_SOURCES +=\\\n    mps/drv_mps_vmmc_ar9.c\n endif\n \n+if FALCON\n+drv_vmmc_SOURCES +=\\\n+   mps/drv_mps_vmmc_falcon.c\n+endif\n+\n endif\n \n if PMC_SUPPORT\n--- a/drv_version.h\n+++ b/drv_version.h\n@@ -36,6 +36,10 @@\n #define MIN_FW_MAJORSTEP   2\n #define MIN_FW_MINORSTEP   1\n #define MIN_FW_HOTFIXSTEP  0\n+#elif  defined(SYSTEM_FALCON)\n+#define MIN_FW_MAJORSTEP   0\n+#define MIN_FW_MINORSTEP   1\n+#define MIN_FW_HOTFIXSTEP  0\n #else\n #error unknown system\n #endif\n--- a/src/drv_vmmc_bbd.c\n+++ b/src/drv_vmmc_bbd.c\n@@ -34,6 +34,7 @@\n #define VMMC_WL_SDD_BASIC_CFG       0x04000400\n #define VMMC_WL_SDD_RING_CFG        0x04000500\n #define VMMC_WL_SDD_DCDC_CFG        0x04000C00\n+#define VMMC_WL_SDD_MWI_CFG         0x04000600\n \n #define IDLE_EXT_TOGGLE_SLEEP_MS    5\n \n@@ -52,6 +53,8 @@\n #define BBD_VMMC_MAGIC                       0x41523921 /* \"AR9\"  */\n #elif defined(SYSTEM_VR9)\n #define BBD_VMMC_MAGIC                       0x56523921 /* \"VR9\"  */\n+#elif defined(SYSTEM_FALCON)\n+#define BBD_VMMC_MAGIC                       0x46414C43 /* \"FALC\"  */\n #else\n #error system undefined\n #endif\n@@ -525,9 +528,6 @@ static IFX_int32_t VMMC_BBD_BlockHandler\n    IFX_uint16_t               slic_val;\n    IFX_int32_t                ret = IFX_SUCCESS;\n \n-   TRACE(VMMC, DBG_LEVEL_LOW,\n-         (\"bbd block with tag 0x%04X passed\\n\", pBBDblock->tag));\n-\n    /* for FXO line allowed blocks are FXO_CRAM and TRANSPARENT */\n    if (pCh->pALM->line_type_fxs != IFX_TRUE)\n    {\n@@ -686,6 +686,7 @@ static IFX_int32_t VMMC_BBD_BlockHandler\n             break;\n       }\n    } /* if */\n+\n    return ret;\n }\n \n@@ -1026,6 +1027,7 @@ static IFX_int32_t vmmc_BBD_WhiteListedC\n          }\n       case VMMC_WL_SDD_RING_CFG:\n       case VMMC_WL_SDD_DCDC_CFG:\n+      case VMMC_WL_SDD_MWI_CFG:\n          ret = CmdWrite (pCh->pParent, Msg.val, Msg.cmd.LENGTH);\n          break;\n \n@@ -1068,7 +1070,7 @@ static IFX_int32_t vmmc_BBD_DownloadChCr\n    IFX_uint32_t countWords;\n    IFX_uint32_t posBytes = 0;\n    IFX_uint8_t  lenBytes, *pByte;\n-#if defined(SYSTEM_AR9) || defined(SYSTEM_VR9)\n+#if defined(SYSTEM_AR9) || defined(SYSTEM_VR9) || defined(SYSTEM_FALCON)\n    IFX_uint8_t  padBytes = 0;\n #endif\n    IFX_uint16_t cram_offset, cram_crc,\n@@ -1088,7 +1090,7 @@ static IFX_int32_t vmmc_BBD_DownloadChCr\n #ifdef SYSTEM_DANUBE\n    /* CMD1 is a COP command  */\n    pCmd[0] = (0x0200) | (pCh->nChannel - 1);\n-#elif  defined(SYSTEM_AR9) || defined(SYSTEM_VR9)\n+#elif  defined(SYSTEM_AR9) || defined(SYSTEM_VR9) || defined(SYSTEM_FALCON)\n    /* SDD_Coef command */\n    pCmd[0] = (0x0400) | (pCh->nChannel - 1);\n    pCmd[1] = (0x0D00);\n@@ -1111,7 +1113,7 @@ static IFX_int32_t vmmc_BBD_DownloadChCr\n       pCmd[1] = ((cram_offset + (posBytes >> 1)) << 8);\n       /* set CRAM data while taking care of endianess  */\n       cpb2w (&pCmd[2], &pByte[posBytes], lenBytes);\n-#elif defined(SYSTEM_AR9) || defined(SYSTEM_VR9)\n+#elif defined(SYSTEM_AR9) || defined(SYSTEM_VR9) || defined(SYSTEM_FALCON)\n       /* calculate length to download (in words = 16bit),\n          maximum allowed length for this message is 56 Bytes = 28 Words */\n       if (countWords > ((MAX_CMD_WORD - CMD_HDR_CNT - 1)))\n@@ -1140,7 +1142,7 @@ static IFX_int32_t vmmc_BBD_DownloadChCr\n       /* write Data */\n #if defined SYSTEM_DANUBE\n       ret = CmdWrite (pCh->pParent, (IFX_uint32_t *) pCmd, lenBytes);\n-#elif defined(SYSTEM_AR9) || defined(SYSTEM_VR9)\n+#elif defined(SYSTEM_AR9) || defined(SYSTEM_VR9) || defined(SYSTEM_FALCON)\n #if 1\n       /* lenBytes + 2 bytes for block offset/length which are not calculated\n          in the download progress */\n--- a/src/mps/drv_mps_version.h\n+++ b/src/mps/drv_mps_version.h\n@@ -17,7 +17,7 @@\n #define VERSIONSTEP  2\n #define VERS_TYPE    5\n \n-#if defined(SYSTEM_AR9) || defined(SYSTEM_VR9)\n+#if defined(SYSTEM_AR9) || defined(SYSTEM_VR9) || defined(SYSTEM_FALCON)\n #define IFX_MPS_PLATFORM_NAME \"MIPS34KEc\"\n #elif  defined(SYSTEM_DANUBE)\n #define IFX_MPS_PLATFORM_NAME \"MIPS24KEc\"\n--- a/src/mps/drv_mps_vmmc_linux.c\n+++ b/src/mps/drv_mps_vmmc_linux.c\n@@ -2229,7 +2229,7 @@ IFX_int32_t __init ifx_mps_init_module (\n #if defined(CONFIG_MIPS) && !defined(CONFIG_MIPS_UNCACHED)\n #if defined(SYSTEM_DANUBE)\n    bDoCacheOps = IFX_TRUE; /* on Danube always perform cache ops */\n-#elif defined(SYSTEM_AR9) || defined(SYSTEM_VR9)\n+#elif defined(SYSTEM_AR9) || defined(SYSTEM_VR9) || defined(SYSTEM_FALCON)\n    /* on AR9/VR9 cache is configured by BSP;\n       here we check whether the D-cache is shared or partitioned;\n       1) in case of shared D-cache all cache operations are omitted;\n@@ -2259,7 +2259,8 @@ IFX_int32_t __init ifx_mps_init_module (\n \n    /* reset the device before initializing the device driver */\n    ifx_mps_reset ();\n-   result = request_irq (INT_NUM_IM4_IRL18,\n+\n+  result = request_irq (INT_NUM_IM4_IRL18,\n #ifdef LINUX_2_6\n                          ifx_mps_ad0_irq, 0x0\n #else /* */\n@@ -2400,7 +2401,7 @@ IFX_int32_t __init ifx_mps_init_module (\n    if (result = ifx_mps_init_gpt_danube ())\n       return result;\n #endif /*DANUBE*/\n-      TRACE (MPS, DBG_LEVEL_HIGH, (\"Downloading Firmware...\\n\"));\n+   TRACE (MPS, DBG_LEVEL_HIGH, (\"Downloading Firmware...\\n\"));\n    ifx_mps_download_firmware (IFX_NULL, (mps_fw *) 0xa0a00000);\n    udelay (500);\n    TRACE (MPS, DBG_LEVEL_HIGH, (\"Providing Buffers...\\n\"));\n--- /dev/null\n+++ b/src/mps/drv_mps_vmmc_falcon.c\n@@ -0,0 +1,396 @@\n+/******************************************************************************\n+\n+                              Copyright (c) 2009\n+                            Lantiq Deutschland GmbH\n+                     Am Campeon 3; 85579 Neubiberg, Germany\n+\n+  For licensing information, see the file 'LICENSE' in the root folder of\n+  this software module.\n+\n+****************************************************************************\n+   Module      : drv_mps_vmmc_falcon.c\n+   Description : This file contains the implementation of the FALC-ON specific\n+                 driver functions.\n+*******************************************************************************/\n+\n+/* ============================= */\n+/* Includes                      */\n+/* ============================= */\n+#include \"drv_config.h\"\n+\n+#if defined(SYSTEM_FALCON) /* defined in drv_config.h */\n+\n+/* lib_ifxos headers */\n+#include \"ifx_types.h\"\n+#include \"ifxos_linux_drv.h\"\n+#include \"ifxos_copy_user_space.h\"\n+#include \"ifxos_event.h\"\n+#include \"ifxos_lock.h\"\n+#include \"ifxos_select.h\"\n+#include \"ifxos_interrupt.h\"\n+#include <linux/gpio.h>\n+#include <sys1_reg.h>\n+#include <falcon.h>\n+#include <falcon_irq.h>\n+#include <vpe.h>\n+#include <sysctrl.h>\n+void (*ifx_bsp_basic_mps_decrypt)(unsigned int addr, int n) = (void (*)(unsigned int, int))0xbf000290;\n+\n+#define IFX_MPS_SRAM IFXMIPS_MPS_SRAM\n+\n+/*#define USE_PLAIN_VOICE_FIRMWARE*/\n+/* board specific headers */\n+\n+/* device specific headers */\n+#include \"drv_mps_vmmc.h\"\n+#include \"drv_mps_vmmc_dbg.h\"\n+#include \"drv_mps_vmmc_device.h\"\n+\n+/* ============================= */\n+/* Local Macros & Definitions    */\n+/* ============================= */\n+/* Firmware watchdog timer counter address */\n+#define VPE1_WDOG_CTR_ADDR ((IFX_uint32_t)((IFX_uint8_t* )IFX_MPS_SRAM + 432))\n+\n+/* Firmware watchdog timeout range, values in ms */\n+#define VPE1_WDOG_TMOUT_MIN 20\n+#define VPE1_WDOG_TMOUT_MAX 5000\n+\n+/* ============================= */\n+/* Global variable definition    */\n+/* ============================= */\n+extern mps_comm_dev *pMPSDev;\n+\n+/* ============================= */\n+/* Global function declaration   */\n+/* ============================= */\n+IFX_void_t ifx_mps_release (IFX_void_t);\n+extern IFX_uint32_t ifx_mps_reset_structures (mps_comm_dev * pMPSDev);\n+extern IFX_int32_t ifx_mps_bufman_close (IFX_void_t);\n+extern IFXOS_event_t fw_ready_evt;\n+\n+/* ============================= */\n+/* Local variable definition     */\n+/* ============================= */\n+static IFX_int32_t vpe1_started = 0;\n+/* VMMC watchdog timer callback */\n+IFX_int32_t (*ifx_wdog_callback) (IFX_uint32_t flags) = IFX_NULL;\n+\n+/* ============================= */\n+/* Local function definition     */\n+/* ============================= */\n+\n+/******************************************************************************\n+ * AR9 Specific Routines\n+ ******************************************************************************/\n+\n+/**\n+ * Firmware download to Voice CPU\n+ * This function performs a firmware download to the coprocessor.\n+ *\n+ * \\param   pMBDev    Pointer to mailbox device structure\n+ * \\param   pFWDwnld  Pointer to firmware structure\n+ * \\return  0         IFX_SUCCESS, firmware ready\n+ * \\return  -1        IFX_ERROR,   firmware not downloaded.\n+ * \\ingroup Internal\n+ */\n+IFX_int32_t ifx_mps_download_firmware (mps_mbx_dev *pMBDev, mps_fw *pFWDwnld)\n+{\n+   IFX_uint32_t mem, cksum;\n+   IFX_uint8_t crc;\n+   IFX_boolean_t bMemReqNotPresent = IFX_FALSE;\n+\n+   /* VCC register */\n+   /* dummy accesss on GTC for GPONC-55, otherwise upper bits are random on read */\n+   ltq_r32 ((u32 *)((KSEG1 | 0x1DC000B0)));\n+   /* NTR Frequency Select 1536 kHz per default or take existing,\n+      NTR Output Enable and NTR8K Output Enable  */\n+   if ((ltq_r32 ((u32 *)(GPON_SYS_BASE + 0xBC)) & 7) == 0)\n+      ltq_w32_mask (0x10187, 0x183, (u32 *)(GPON_SYS_BASE + 0xBC));\n+   else\n+      ltq_w32_mask (0x10180, 0x180, (u32 *)(GPON_SYS_BASE + 0xBC));\n+#if 0\n+   /* BIU-ICU1-IM1_ISR - IM1:FSCT_CMP1=1 and FSC_ROOT=1\n+      (0x1f880328 = 0x00002800) */\n+   ltq_w32 (0x00002800, (u32 *)(GPON_ICU1_BASE + 0x30));\n+#endif\n+   /* copy FW footer from user space */\n+   if (IFX_NULL == IFXOS_CpyFromUser(pFW_img_data,\n+                           pFWDwnld->data+pFWDwnld->length/4-sizeof(*pFW_img_data)/4,\n+                           sizeof(*pFW_img_data)))\n+   {\n+      TRACE (MPS, DBG_LEVEL_HIGH,\n+                  (KERN_ERR \"[%s %s %d]: copy_from_user error\\r\\n\",\n+                   __FILE__, __func__, __LINE__));\n+      return IFX_ERROR;\n+   }\n+\n+   mem = pFW_img_data->mem;\n+\n+   /* memory requirement sanity check */\n+   if ((crc = ~((mem >> 16) + (mem >> 8) + mem)) != (mem >> 24))\n+   {\n+      TRACE (MPS, DBG_LEVEL_HIGH,\n+          (\"[%s %s %d]: warning, image does not contain size - assuming 1MB!\\n\",\n+           __FILE__, __func__, __LINE__));\n+      mem = 1 * 1024 * 1024;\n+      bMemReqNotPresent = IFX_TRUE;\n+   }\n+   else\n+   {\n+      mem &= 0x00FFFFFF;\n+   }\n+\n+   /* check if FW image fits in available memory space */\n+   if (mem > vpe1_get_max_mem(0))\n+   {\n+      TRACE (MPS, DBG_LEVEL_HIGH,\n+      (\"[%s %s %d]: error, firmware memory exceeds reserved space (%i > %i)!\\n\",\n+                 __FILE__, __func__, __LINE__, mem, vpe1_get_max_mem(0)));\n+      return IFX_ERROR;\n+   }\n+\n+   /* reset the driver */\n+   ifx_mps_reset ();\n+\n+   /* call BSP to get cpu1 base address */\n+   cpu1_base_addr = (IFX_uint32_t *)vpe1_get_load_addr(0);\n+\n+   /* check if CPU1 base address is sane\n+      \\todo: check if address is 1MB aligned,\n+      also make it visible in a /proc fs */\n+   if (!cpu1_base_addr)\n+   {\n+      TRACE (MPS, DBG_LEVEL_HIGH,\n+             (KERN_ERR \"IFX_MPS: CPU1 base address is invalid!\\r\\n\"));\n+      return IFX_ERROR;\n+   }\n+   /* further use uncached value */\n+   cpu1_base_addr = (IFX_uint32_t *)KSEG1ADDR(cpu1_base_addr);\n+\n+   /* free all data buffers that might be currently used by FW */\n+   if (IFX_NULL != ifx_mps_bufman_freeall)\n+   {\n+      ifx_mps_bufman_freeall();\n+   }\n+\n+   if(FW_FORMAT_NEW)\n+   {\n+      /* adjust download length */\n+      pFWDwnld->length -= (sizeof(*pFW_img_data)-sizeof(IFX_uint32_t));\n+   }\n+   else\n+   {\n+      pFWDwnld->length -= sizeof(IFX_uint32_t);\n+\n+      /* handle unlikely case if FW image does not contain memory requirement -\n+         assumed for old format only */\n+      if (IFX_TRUE == bMemReqNotPresent)\n+         pFWDwnld->length += sizeof(IFX_uint32_t);\n+\n+      /* in case of old FW format always assume that FW is encrypted;\n+         use compile switch USE_PLAIN_VOICE_FIRMWARE for plain FW */\n+#ifndef USE_PLAIN_VOICE_FIRMWARE\n+      pFW_img_data->enc = 1;\n+#else\n+#warning Using unencrypted firmware!\n+      pFW_img_data->enc = 0;\n+#endif /* USE_PLAIN_VOICE_FIRMWARE */\n+      /* initializations for the old format */\n+      pFW_img_data->st_addr_crc = 2*sizeof(IFX_uint32_t) +\n+                                  FW_AR9_OLD_FMT_XCPT_AREA_SZ;\n+      pFW_img_data->en_addr_crc = pFWDwnld->length;\n+      pFW_img_data->fw_vers = 0;\n+      pFW_img_data->magic = 0;\n+   }\n+\n+   /* copy FW image to base address of CPU1 */\n+   if (IFX_NULL ==\n+       IFXOS_CpyFromUser ((IFX_void_t *)cpu1_base_addr,\n+                          (IFX_void_t *)pFWDwnld->data, pFWDwnld->length))\n+   {\n+      TRACE (MPS, DBG_LEVEL_HIGH,\n+             (KERN_ERR \"[%s %s %d]: copy_from_user error\\r\\n\", __FILE__,\n+              __func__, __LINE__));\n+      return IFX_ERROR;\n+   }\n+\n+   /* process firmware decryption */\n+   if (pFW_img_data->enc == 1)\n+   {\n+      if(FW_FORMAT_NEW)\n+      {\n+         /* adjust decryption length (avoid decrypting CRC32 checksum) */\n+         pFWDwnld->length -= sizeof(IFX_uint32_t);\n+      }\n+      /* BootROM actually decrypts n+4 bytes if n bytes were passed for\n+         decryption. Subtract sizeof(u32) from length to avoid decryption\n+         of data beyond the FW image code */\n+      pFWDwnld->length -= sizeof(IFX_uint32_t);\n+      ifx_bsp_basic_mps_decrypt((unsigned int)cpu1_base_addr, pFWDwnld->length);\n+   }\n+\n+   /* calculate CRC32 checksum over downloaded image */\n+   cksum = ifx_mps_fw_crc32(cpu1_base_addr, pFW_img_data);\n+\n+   /* verify the checksum */\n+   if(FW_FORMAT_NEW)\n+   {\n+      if (cksum != pFW_img_data->crc32)\n+      {\n+         TRACE (MPS, DBG_LEVEL_HIGH,\n+                (\"MPS: FW checksum error: img=0x%08x calc=0x%08x\\r\\n\",\n+                pFW_img_data->crc32, cksum));\n+         return IFX_ERROR;\n+      }\n+   }\n+   else\n+   {\n+      /* just store self-calculated checksum */\n+      pFW_img_data->crc32 = cksum;\n+   }\n+\n+   /* start VPE1 */\n+   ifx_mps_release ();\n+\n+   /* get FW version */\n+   return ifx_mps_get_fw_version (0);\n+}\n+\n+\n+/**\n+ * Restart CPU1\n+ * This function restarts CPU1 by accessing the reset request register and\n+ * reinitializes the mailbox.\n+ *\n+ * \\return  0        IFX_SUCCESS, successful restart\n+ * \\return  -1       IFX_ERROR, if reset failed\n+ * \\ingroup Internal\n+ */\n+IFX_int32_t ifx_mps_restart (IFX_void_t)\n+{\n+   /* raise reset request for CPU1 and reset driver structures */\n+   ifx_mps_reset ();\n+   /* Disable GPTC Interrupt to CPU1 */\n+   ifx_mps_shutdown_gpt ();\n+   /* re-configure GPTC */\n+   ifx_mps_init_gpt ();\n+   /* let CPU1 run */\n+   ifx_mps_release ();\n+   TRACE (MPS, DBG_LEVEL_HIGH, (\"IFX_MPS: Restarting firmware...\"));\n+   return ifx_mps_get_fw_version (0);\n+}\n+\n+/**\n+ * Shutdown MPS - stop VPE1\n+ * This function stops VPE1\n+ *\n+ * \\ingroup Internal\n+ */\n+IFX_void_t ifx_mps_shutdown (IFX_void_t)\n+{\n+   if (vpe1_started)\n+   {\n+      /* stop VPE1 */\n+      vpe1_sw_stop (0);\n+      vpe1_started = 0;\n+   }\n+   /* free GPTC */\n+   ifx_mps_shutdown_gpt ();\n+}\n+\n+/**\n+ * Reset CPU1\n+ * This function causes a reset of CPU1 by clearing the CPU0 boot ready bit\n+ * in the reset request register RCU_RST_REQ.\n+ * It does not change the boot configuration registers for CPU0 or CPU1.\n+ *\n+ * \\return  0        IFX_SUCCESS, cannot fail\n+ * \\ingroup Internal\n+ */\n+IFX_void_t ifx_mps_reset (IFX_void_t)\n+{\n+   /* if VPE1 is already started, stop it */\n+   if (vpe1_started)\n+   {\n+      vpe1_sw_stop (0);\n+      vpe1_started = 0;\n+   }\n+\n+   /* reset driver */\n+   ifx_mps_reset_structures (pMPSDev);\n+   ifx_mps_bufman_close ();\n+   return;\n+}\n+\n+/**\n+ * Let CPU1 run\n+ * This function starts VPE1\n+ *\n+ * \\return  none\n+ * \\ingroup Internal\n+ */\n+IFX_void_t ifx_mps_release (IFX_void_t)\n+{\n+   IFX_int_t ret;\n+   IFX_int32_t RetCode = 0;\n+\n+   /* Start VPE1 */\n+   if (IFX_SUCCESS !=\n+       vpe1_sw_start ((IFX_void_t *)cpu1_base_addr, 0, 0))\n+   {\n+      TRACE (MPS, DBG_LEVEL_HIGH, (KERN_ERR \"Error starting VPE1\\r\\n\"));\n+      return;\n+   }\n+   vpe1_started = 1;\n+\n+   /* sleep 3 seconds until FW is ready */\n+   ret = IFXOS_EventWait (&fw_ready_evt, 3000, &RetCode);\n+   if ((ret == IFX_ERROR) && (RetCode == 1))\n+   {\n+      /* timeout */\n+      TRACE (MPS, DBG_LEVEL_HIGH,\n+             (KERN_ERR \"[%s %s %d]: Timeout waiting for firmware ready.\\r\\n\",\n+              __FILE__, __func__, __LINE__));\n+      /* recalculate and compare the firmware checksum */\n+      ifx_mps_fw_crc_compare(cpu1_base_addr, pFW_img_data);\n+      /* dump exception area on a console */\n+      ifx_mps_dump_fw_xcpt(cpu1_base_addr, pFW_img_data);\n+   }\n+}\n+\n+/**\n+ * Register WDT callback.\n+ * This function is called by VMMC driver to register its callback in\n+ * the MPS driver.\n+ *\n+ * \\return  0        IFX_SUCCESS, cannot fail\n+ * \\ingroup Internal\n+ */\n+IFX_int32_t\n+ifx_mps_register_wdog_callback (IFX_int32_t (*pfn) (IFX_uint32_t flags))\n+{\n+   ifx_wdog_callback = pfn;\n+   return 0;\n+}\n+\n+/**\n+   Hardware setup on FALC ON\n+*/\n+void sys_hw_setup (void)\n+{\n+   /* Set INFRAC register bit 1: clock enable of the GPE primary clock.  */\n+   sys_gpe_hw_activate (0);\n+   /* enable 1.5 V */\n+   ltq_w32_mask (0xf, 0x0b, (u32 *)(GPON_SYS1_BASE | 0xbc));\n+   /* SYS1-CLKEN:GPTC = 1 and MPS, no longer FSCT = 1 */\n+   sys1_hw_activate (ACTS_MPS | ACTS_GPTC);\n+   /* GPTC:CLC:RMC = 1 */\n+   ltq_w32 (0x00000100, (u32 *)(KSEG1 | 0x1E100E00));\n+}\n+\n+#ifndef VMMC_WITH_MPS\n+EXPORT_SYMBOL (ifx_mps_register_wdog_callback);\n+#endif /* !VMMC_WITH_MPS */\n+\n+#endif /* SYSTEM_FALCON */\n--- a/src/mps/drv_mps_vmmc_common.c\n+++ b/src/mps/drv_mps_vmmc_common.c\n@@ -66,6 +66,10 @@ static void inline bsp_mask_and_ack_irq(\n #  include <asm/ifx/ifx_regs.h>\n #  include <asm/ifx/ifx_gptu.h>\n #endif\n+#if defined(SYSTEM_FALCON)\n+#include <sys1_reg.h>\n+#include <sysctrl.h>\n+#endif\n \n #include \"drv_mps_vmmc.h\"\n #include \"drv_mps_vmmc_dbg.h\"\n@@ -1156,7 +1160,12 @@ IFX_uint32_t ifx_mps_init_structures (mp\n       mailbox, * upstream and downstream direction. */\n    memset (\n \t/* avoid to overwrite CPU boot registers */\n+#if defined(SYSTEM_FALCON)\n+\t   (IFX_void_t *) MBX_Memory +\n+           2 * sizeof (mps_boot_cfg_reg),\n+#else\n \t   (IFX_void_t *) MBX_Memory,\n+#endif\n            0,\n            sizeof (mps_mbx_reg) - 2 * sizeof (mps_boot_cfg_reg));\n    MBX_Memory->MBX_UPSTR_CMD_BASE =\n@@ -2651,7 +2660,6 @@ IFX_void_t ifx_mps_enable_mailbox_int ()\n #endif\n \n    *IFX_MPS_AD0ENR = Ad0Reg.val;\n-\n }\n \n /**\n@@ -2669,6 +2677,7 @@ IFX_void_t ifx_mps_disable_mailbox_int (\n    Ad0Reg.fld.cu_mbx = 0;\n    Ad0Reg.fld.du_mbx = 0;\n    *IFX_MPS_AD0ENR = Ad0Reg.val;\n+\n }\n \n /**\n@@ -2766,11 +2775,13 @@ irqreturn_t ifx_mps_ad0_irq (IFX_int32_t\n    /* handle only enabled interrupts */\n    MPS_Ad0StatusReg.val &= *IFX_MPS_AD0ENR;\n \n+#if !defined(SYSTEM_FALCON)\n #ifdef LINUX_2_6\n    bsp_mask_and_ack_irq (irq);\n #else /* */\n    mask_and_ack_danube_irq (irq);\n #endif /* */\n+#endif /* !defined(SYSTEM_FALCON) */\n    /* FW is up and ready to process commands */\n    if (MPS_Ad0StatusReg.fld.dl_end)\n    {\n@@ -2919,11 +2930,13 @@ irqreturn_t ifx_mps_ad1_irq (IFX_int32_t\n    /* handle only enabled interrupts */\n    MPS_Ad1StatusReg.val &= *IFX_MPS_AD1ENR;\n \n+#if !defined(SYSTEM_FALCON)\n #ifdef LINUX_2_6\n    bsp_mask_and_ack_irq (irq);\n #else /* */\n    mask_and_ack_danube_irq (irq);\n #endif /* */\n+#endif /* !defined(SYSTEM_FALCON) */\n    pMPSDev->event.MPS_Ad1Reg.val = MPS_Ad1StatusReg.val;\n \n    /* use callback function or queue wake up to notify about data reception */\n@@ -2977,11 +2990,13 @@ irqreturn_t ifx_mps_vc_irq (IFX_int32_t\n    IFX_MPS_CVC0SR[chan] = MPS_VCStatusReg.val;\n    /* handle only enabled interrupts */\n    MPS_VCStatusReg.val &= IFX_MPS_VC0ENR[chan];\n+#if !defined(SYSTEM_FALCON)\n #ifdef LINUX_2_6\n    bsp_mask_and_ack_irq (irq);\n #else /* */\n    mask_and_ack_danube_irq (irq);\n #endif /* */\n+#endif /* !defined(SYSTEM_FALCON) */\n \n    pMPSDev->event.MPS_VCStatReg[chan].val = MPS_VCStatusReg.val;\n #ifdef PRINT_ON_ERR_INTERRUPT\n@@ -3126,6 +3141,7 @@ IFX_int32_t ifx_mps_get_fw_version (IFX_\n  */\n IFX_return_t ifx_mps_init_gpt ()\n {\n+#if !defined(SYSTEM_FALCON)\n    unsigned long flags;\n    IFX_uint32_t timer_flags, timer, loops = 0;\n    IFX_ulong_t count;\n@@ -3134,7 +3150,11 @@ IFX_return_t ifx_mps_init_gpt ()\n #else /* Danube */\n    timer = TIMER1B;\n #endif /* SYSTEM_AR9 || SYSTEM_VR9 */\n+#endif\n \n+#if defined(SYSTEM_FALCON)\n+   sys_hw_setup ();\n+#else\n    /* calibration loop - required to syncronize GPTC interrupt with falling\n       edge of FSC clock */\n    timer_flags =\n@@ -3179,7 +3199,7 @@ Probably already in use.\\r\\n\", __FILE__,\n #endif /* DEBUG */\n \n    IFXOS_UNLOCKINT (flags);\n-\n+#endif\n    return IFX_SUCCESS;\n }\n \n@@ -3194,6 +3214,9 @@ Probably already in use.\\r\\n\", __FILE__,\n  */\n IFX_void_t ifx_mps_shutdown_gpt (IFX_void_t)\n {\n+#if defined(SYSTEM_FALCON)\n+   sys1_hw_deactivate (ACTS_MPS);\n+#else\n    IFX_uint32_t timer;\n #if defined(SYSTEM_AR9) || defined(SYSTEM_VR9)\n    timer = TIMER1A;\n@@ -3202,6 +3225,7 @@ IFX_void_t ifx_mps_shutdown_gpt (IFX_voi\n #endif /* SYSTEM_AR9 || SYSTEM_VR9 */\n \n    ifx_gptu_timer_free (timer);\n+#endif\n }\n \n /**\n--- a/src/mps/drv_mps_vmmc_device.h\n+++ b/src/mps/drv_mps_vmmc_device.h\n@@ -22,7 +22,12 @@\n #  include <lantiq_soc.h>\n #  include <linux/gpio.h>\n #define IFXMIPS_MPS_SRAM\t\t((u32 *)(KSEG1 + 0x1F200000))\n+#if defined(SYSTEM_FALCON)\n+#define IFXMIPS_MPS_BASE_ADDR\t\t(KSEG1 + 0x1D004000)\n+#else\n #define IFXMIPS_MPS_BASE_ADDR\t\t(KSEG1 + 0x1F107000)\n+#endif\n+\n #define IFXMIPS_MPS_CHIPID\t\t((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0344))\n #define IFXMIPS_MPS_VC0ENR\t\t((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0000))\n #define IFXMIPS_MPS_RVC0SR\t\t((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0010))\n@@ -73,10 +78,11 @@\n /* MPS Common defines            */\n /* ============================= */\n \n-#define MPS_BASEADDRESS 0xBF107000\n-#define MPS_RAD0SR      MPS_BASEADDRESS + 0x0004\n-\n+#if defined(SYSTEM_FALCON)\n+#define MBX_BASEADDRESS 0xBF200040\n+#else\n #define MBX_BASEADDRESS 0xBF200000\n+#endif\n #define VCPU_BASEADDRESS 0xBF208000     /* 0xBF108000 */\n /*---------------------------------------------------------------------------*/\n #if !defined(CONFIG_LANTIQ)\n@@ -118,7 +124,6 @@\n /*---------------------------------------------------------------------------*/\n \n #ifdef CONFIG_MPS_EVENT_MBX\n-\n #define MBX_CMD_FIFO_SIZE  64 /**< Size of command FIFO in bytes */\n #define MBX_DATA_UPSTRM_FIFO_SIZE 64\n #define MBX_DATA_DNSTRM_FIFO_SIZE 128\n@@ -294,6 +299,10 @@ typedef struct\n #ifdef CONFIG_MPS_EVENT_MBX\n typedef struct\n {\n+#if defined(SYSTEM_FALCON)\n+   mps_boot_cfg_reg MBX_CPU0_BOOT_CFG; /**< CPU0 Boot Configuration */\n+   mps_boot_cfg_reg MBX_CPU1_BOOT_CFG; /**< CPU1 Boot Configuration */\n+#endif\n    volatile IFX_uint32_t *MBX_UPSTR_CMD_BASE;  /**< Upstream Command FIFO Base Address */\n    volatile IFX_uint32_t MBX_UPSTR_CMD_SIZE;   /**< Upstream Command FIFO size in byte */\n    volatile IFX_uint32_t *MBX_DNSTR_CMD_BASE;  /**< Downstream Command FIFO Base Address */\n@@ -317,13 +326,19 @@ typedef struct\n    volatile IFX_uint32_t MBX_UPSTR_EVENT_WRITE; /**< Upstream Event FIFO Write Index */\n    volatile IFX_uint32_t MBX_EVENT[MBX_EVENT_DATA_WORDS];\n    volatile IFX_uint32_t reserved[4];\n+#if !defined(SYSTEM_FALCON)\n    mps_boot_cfg_reg MBX_CPU0_BOOT_CFG; /**< CPU0 Boot Configuration */\n    mps_boot_cfg_reg MBX_CPU1_BOOT_CFG; /**< CPU1 Boot Configuration */\n+#endif\n } mps_mbx_reg;\n \n #else /* */\n typedef struct\n {\n+#if defined(SYSTEM_FALCON)\n+   mps_boot_cfg_reg MBX_CPU0_BOOT_CFG; /**< CPU0 Boot Configuration */\n+   mps_boot_cfg_reg MBX_CPU1_BOOT_CFG; /**< CPU1 Boot Configuration */\n+#endif\n    volatile IFX_uint32_t *MBX_UPSTR_CMD_BASE;  /**< Upstream Command FIFO Base Address */\n    volatile IFX_uint32_t MBX_UPSTR_CMD_SIZE;   /**< Upstream Command FIFO size in byte */\n    volatile IFX_uint32_t *MBX_DNSTR_CMD_BASE;  /**< Downstream Command FIFO Base Address */\n@@ -341,8 +356,10 @@ typedef struct\n    volatile IFX_uint32_t MBX_DNSTR_DATA_READ;   /**< Downstream Data FIFO Read Index */\n    volatile IFX_uint32_t MBX_DNSTR_DATA_WRITE;  /**< Downstream Data FIFO Write Index */\n    volatile IFX_uint32_t MBX_DATA[MBX_DATA_WORDS];\n+#if !defined(SYSTEM_FALCON)\n    mps_boot_cfg_reg MBX_CPU0_BOOT_CFG; /**< CPU0 Boot Configuration */\n    mps_boot_cfg_reg MBX_CPU1_BOOT_CFG; /**< CPU1 Boot Configuration */\n+#endif\n } mps_mbx_reg;\n #endif /* CONFIG_MPS_EVENT_MBX */\n \n--- a/src/drv_api.h\n+++ b/src/drv_api.h\n@@ -183,7 +183,7 @@\n #endif\n \n /* TAPI FXS Phone Detection feature is not available for Danube platform */\n-#if defined(TAPI_PHONE_DETECTION) && (defined(SYSTEM_AR9) || defined(SYSTEM_VR9))\n+#if defined(TAPI_PHONE_DETECTION) && (defined(SYSTEM_AR9) || defined(SYSTEM_VR9) || defined(SYSTEM_FALCON))\n #define VMMC_CFG_ADD_FEAT_PHONE_DETECTION VMMC_FEAT_PHONE_DETECTION\n #else\n #define VMMC_CFG_ADD_FEAT_PHONE_DETECTION 0\n--- a/src/drv_vmmc_alm.c\n+++ b/src/drv_vmmc_alm.c\n@@ -800,7 +800,7 @@ IFX_void_t VMMC_ALM_Free_Ch_Structures (\n }\n \n \n-#if defined(SYSTEM_AR9) || defined(SYSTEM_VR9)\n+#if defined(SYSTEM_AR9) || defined(SYSTEM_VR9) || defined(SYSTEM_FALCON)\n /**\n    Check whether SmartSLIC is connected\n \n@@ -836,7 +836,7 @@ IFX_boolean_t VMMC_ALM_SmartSLIC_IsConne\n #endif /*SYSTEM_AR9 || SYSTEM_VR9*/\n \n \n-#if defined(SYSTEM_AR9) || defined(SYSTEM_VR9)\n+#if defined(SYSTEM_AR9) || defined(SYSTEM_VR9) || defined(SYSTEM_FALCON)\n /**\n    Read the number of channels on the SmartSLIC.\n \n@@ -1876,7 +1876,7 @@ IFX_int32_t VMMC_TAPI_LL_ALM_VMMC_Test_L\n       /* write updated message contents */\n       ret = CmdWrite (pDev, (IFX_uint32_t *)((IFX_void_t *)&debugCfg),\n                       DCCTL_CMD_LEN);\n-#elif defined(SYSTEM_AR9) || defined(SYSTEM_VR9)\n+#elif defined(SYSTEM_AR9) || defined(SYSTEM_VR9) || defined(SYSTEM_FALCON)\n       IFX_uint32_t dcctrlLoop[2];\n       IFX_uint32_t ch = (IFX_uint32_t)(pCh->nChannel - 1);\n \n--- a/src/drv_vmmc_alm.h\n+++ b/src/drv_vmmc_alm.h\n@@ -65,7 +65,7 @@ extern IFX_void_t irq_VMMC_ALM_LineDisab\n extern IFX_void_t VMMC_ALM_CorrectLinemodeCache (VMMC_CHANNEL *pCh,\n                                                  IFX_uint16_t lm);\n \n-#if defined(SYSTEM_AR9) || defined(SYSTEM_VR9)\n+#if defined(SYSTEM_AR9) || defined(SYSTEM_VR9) || defined(SYSTEM_FALCON)\n extern IFX_boolean_t VMMC_ALM_SmartSLIC_IsConnected (\n                         VMMC_DEVICE *pDev);\n \n--- a/src/drv_vmmc_init.c\n+++ b/src/drv_vmmc_init.c\n@@ -52,15 +52,6 @@\n #include \"ifx_pmu.h\"\n #endif /* PMU_SUPPORTED */\n \n-#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,28))\n-#  define IFX_MPS_CAD0SR IFXMIPS_MPS_CAD0SR\n-#  define IFX_MPS_CAD1SR IFXMIPS_MPS_CAD1SR\n-#  define IFX_MPS_CVC0SR IFXMIPS_MPS_CVC0SR\n-#  define IFX_MPS_CVC1SR IFXMIPS_MPS_CVC1SR\n-#  define IFX_MPS_CVC2SR IFXMIPS_MPS_CVC2SR\n-#  define IFX_MPS_CVC3SR IFXMIPS_MPS_CVC3SR\n-#endif\n-\n /* ============================= */\n /* Local Macros & Definitions    */\n /* ============================= */\n@@ -820,7 +811,7 @@ static IFX_int32_t VMMC_TAPI_LL_FW_Init(\n                                            MIN_FW_HOTFIXSTEP};\n    IFX_uint8_t          tmp1, tmp2;\n    IFX_TAPI_RESOURCE    nResource;\n-#if defined(SYSTEM_AR9) || defined(SYSTEM_VR9)\n+#if defined(SYSTEM_AR9) || defined(SYSTEM_VR9) || defined(SYSTEM_FALCON)\n    IFX_uint8_t          nChannels, nFXOChannels;\n #endif /*SYSTEM_AR9 || SYSTEM_VR9*/\n    IFX_int32_t          ret = VMMC_statusOk;\n@@ -874,7 +865,7 @@ static IFX_int32_t VMMC_TAPI_LL_FW_Init(\n    pDev->bSmartSlic = IFX_FALSE;\n    pDev->bSlicSupportsIdleMode = IFX_FALSE;\n \n-#if defined(SYSTEM_AR9) || defined(SYSTEM_VR9)\n+#if defined(SYSTEM_AR9) || defined(SYSTEM_VR9) || defined(SYSTEM_FALCON)\n    if (VMMC_SUCCESS(ret))\n    {\n       /* Reduce the number of ALM channels in the capabilities if the SLIC\n--- a/src/drv_vmmc_ioctl.c\n+++ b/src/drv_vmmc_ioctl.c\n@@ -273,7 +273,7 @@ IFX_int32_t VMMC_Dev_Spec_Ioctl (IFX_TAP\n       case FIO_GET_VERS:\n       {\n          VMMC_IO_VERSION *pVers;\n-#if defined(SYSTEM_AR9) || defined(SYSTEM_VR9)\n+#if defined(SYSTEM_AR9) || defined(SYSTEM_VR9) || defined(SYSTEM_FALCON)\n          VMMC_SDD_REVISION_READ_t *pSDDVersCmd = IFX_NULL;\n #endif /*SYSTEM_AR9 || SYSTEM_VR9*/\n          SYS_VER_t *pCmd;\n@@ -322,7 +322,7 @@ IFX_int32_t VMMC_Dev_Spec_Ioctl (IFX_TAP\n             pVers->nTapiVers   = 3;\n             pVers->nDrvVers    = MAJORSTEP << 24 | MINORSTEP << 16 |\n                                  VERSIONSTEP << 8 | VERS_TYPE;\n-#if defined(SYSTEM_AR9) || defined(SYSTEM_VR9)\n+#if defined(SYSTEM_AR9) || defined(SYSTEM_VR9) || defined(SYSTEM_FALCON)\n             /* in case of SmartSLIC based systems, we can give some more\n                versions.*/\n             if (VMMC_ALM_SmartSLIC_IsConnected(pDev))\n"
  },
  {
    "path": "package/kernel/lantiq/ltq-vmmc/patches/500-ar9_vr9.patch",
    "content": "--- a/src/mps/drv_mps_vmmc_ar9.c\n+++ b/src/mps/drv_mps_vmmc_ar9.c\n@@ -30,15 +30,24 @@\n #include \"ifxos_interrupt.h\"\n \n /* board specific headers */\n+#if !defined CONFIG_LANTIQ\n #include <asm/ifx/ifx_regs.h>\n #include <asm/ifx_vpe.h>\n #include <asm/ifx/ifx_gpio.h>\n+#endif\n+\n+#include <lantiq_soc.h>\n+#include <asm/vpe.h>\n \n /* device specific headers */\n #include \"drv_mps_vmmc.h\"\n #include \"drv_mps_vmmc_dbg.h\"\n #include \"drv_mps_vmmc_device.h\"\n \n+const void (*ifx_bsp_basic_mps_decrypt)(unsigned int addr, int n) = NULL;\n+\n+#define IFX_MPS_SRAM IFXMIPS_MPS_SRAM\n+\n /* ============================= */\n /* Local Macros & Definitions    */\n /* ============================= */\n@@ -65,12 +74,7 @@ extern mps_comm_dev *pMPSDev;\n IFX_void_t ifx_mps_release (IFX_void_t);\n extern IFX_uint32_t ifx_mps_reset_structures (mps_comm_dev * pMPSDev);\n extern IFX_int32_t ifx_mps_bufman_close (IFX_void_t);\n-IFX_int32_t ifx_mps_wdog_callback (IFX_uint32_t wdog_cleared_ok_count);\n extern IFXOS_event_t fw_ready_evt;\n-/* ============================= */\n-/* Local function declaration    */\n-/* ============================= */\n-static IFX_int32_t ifx_mps_fw_wdog_start_ar9(IFX_void_t);\n \n /* ============================= */\n /* Local variable definition     */\n@@ -88,61 +92,6 @@ IFX_int32_t (*ifx_wdog_callback) (IFX_ui\n  ******************************************************************************/\n \n /**\n- * Start AR9 EDSP firmware watchdog mechanism.\n- * Called after download and startup of VPE1.\n- *\n- * \\param   none\n- * \\return  0         IFX_SUCCESS\n- * \\return  -1        IFX_ERROR\n- * \\ingroup Internal\n- */\n-IFX_int32_t ifx_mps_fw_wdog_start_ar9()\n-{\n-   /* vpe1_wdog_ctr should be set up in u-boot as\n-      \"vpe1_wdog_ctr_addr=0xBF2001B0\"; protection from incorrect or missing\n-      setting */\n-   if (vpe1_wdog_ctr != VPE1_WDOG_CTR_ADDR)\n-   {\n-      vpe1_wdog_ctr = VPE1_WDOG_CTR_ADDR;\n-   }\n-\n-   /* vpe1_wdog_timeout should be set up in u-boot as \"vpe1_wdog_timeout =\n-      <value in ms>\"; protection from insane setting */\n-   if (vpe1_wdog_timeout < VPE1_WDOG_TMOUT_MIN)\n-   {\n-      vpe1_wdog_timeout = VPE1_WDOG_TMOUT_MIN;\n-   }\n-   if (vpe1_wdog_timeout > VPE1_WDOG_TMOUT_MAX)\n-   {\n-      vpe1_wdog_timeout = VPE1_WDOG_TMOUT_MAX;\n-   }\n-\n-   /* recalculate in jiffies */\n-   vpe1_wdog_timeout = vpe1_wdog_timeout * HZ / 1000;\n-\n-   /* register BSP callback function */\n-   if (IFX_SUCCESS !=\n-       vpe1_sw_wdog_register_reset_handler (ifx_mps_wdog_callback))\n-   {\n-      TRACE (MPS, DBG_LEVEL_HIGH,\n-             (KERN_ERR \"[%s %s %d]: Unable to register WDT callback.\\r\\n\",\n-              __FILE__, __func__, __LINE__));\n-      return IFX_ERROR;;\n-   }\n-\n-   /* start software watchdog timer */\n-   if (IFX_SUCCESS != vpe1_sw_wdog_start (0))\n-   {\n-      TRACE (MPS, DBG_LEVEL_HIGH,\n-             (KERN_ERR\n-              \"[%s %s %d]: Error starting software watchdog timer.\\r\\n\",\n-              __FILE__, __func__, __LINE__));\n-      return IFX_ERROR;\n-   }\n-   return IFX_SUCCESS;\n-}\n-\n-/**\n  * Firmware download to Voice CPU\n  * This function performs a firmware download to the coprocessor.\n  *\n@@ -292,6 +241,18 @@ IFX_int32_t ifx_mps_download_firmware (m\n          decryption. Subtract sizeof(u32) from length to avoid decryption\n          of data beyond the FW image code */\n       pFWDwnld->length -= sizeof(IFX_uint32_t);\n+      switch(ltq_soc_type()) {\n+   \t   case SOC_TYPE_AR9:\n+\t\t   ifx_bsp_basic_mps_decrypt = (const void (*)(unsigned int, int))0xbf0017c4;\n+\t\t   break;\n+\t   case SOC_TYPE_VR9:\n+\t\t   ifx_bsp_basic_mps_decrypt = (const void (*)(unsigned int, int))0xbf001ea4;\n+\t\t   break;\n+\t   case SOC_TYPE_VR9_2:\n+\t\t   ifx_bsp_basic_mps_decrypt = (const void (*)(unsigned int, int))0xbf001f38;\n+\t\t   break;\n+      }\n+      if (ifx_bsp_basic_mps_decrypt)\n       ifx_bsp_basic_mps_decrypt((IFX_uint32_t)cpu1_base_addr, pFWDwnld->length);\n    }\n \n@@ -318,9 +279,6 @@ IFX_int32_t ifx_mps_download_firmware (m\n    /* start VPE1 */\n    ifx_mps_release ();\n \n-   /* start FW watchdog mechanism */\n-   ifx_mps_fw_wdog_start_ar9();\n-\n    /* get FW version */\n    return ifx_mps_get_fw_version (0);\n }\n@@ -345,8 +303,6 @@ IFX_int32_t ifx_mps_restart (IFX_void_t)\n    ifx_mps_init_gpt ();\n    /* let CPU1 run */\n    ifx_mps_release ();\n-   /* start FW watchdog mechanism */\n-   ifx_mps_fw_wdog_start_ar9();\n    TRACE (MPS, DBG_LEVEL_HIGH, (\"IFX_MPS: Restarting firmware...\"));\n    return ifx_mps_get_fw_version (0);\n }\n@@ -361,10 +317,6 @@ IFX_void_t ifx_mps_shutdown (IFX_void_t)\n {\n    if (vpe1_started)\n    {\n-      /* stop software watchdog timer */\n-      vpe1_sw_wdog_stop (0);\n-      /* clean up the BSP callback function */\n-      vpe1_sw_wdog_register_reset_handler (IFX_NULL);\n       /* stop VPE1 */\n       vpe1_sw_stop (0);\n       vpe1_started = 0;\n@@ -387,8 +339,6 @@ IFX_void_t ifx_mps_reset (IFX_void_t)\n    /* if VPE1 is already started, stop it */\n    if (vpe1_started)\n    {\n-      /* stop software watchdog timer first */\n-      vpe1_sw_wdog_stop (0);\n       vpe1_sw_stop (0);\n       vpe1_started = 0;\n    }\n@@ -436,101 +386,6 @@ IFX_void_t ifx_mps_release (IFX_void_t)\n }\n \n /**\n- * WDT callback.\n- * This function is called by BSP (module softdog_vpe) in case if software\n- * watchdog timer expiration is detected by BSP.\n- * This function needs to be registered at BSP as WDT callback using\n- * vpe1_sw_wdog_register_reset_handler() API.\n- *\n- * \\return  0        IFX_SUCCESS, cannot fail\n- * \\ingroup Internal\n- */\n-IFX_int32_t ifx_mps_wdog_callback (IFX_uint32_t wdog_cleared_ok_count)\n-{\n-   IFX_uint32_t flags;\n-#ifdef DEBUG\n-   TRACE (MPS, DBG_LEVEL_HIGH,\n-          (\"MPS: watchdog callback! arg=0x%08x\\r\\n\", wdog_cleared_ok_count));\n-#endif /* DEBUG */\n-\n-   /* reset SmartSLIC */\n-   IFXOS_LOCKINT (flags);\n-   if (ifx_gpio_pin_reserve\n-       (IFX_GPIO_PIN_ID (SSLIC_RST_PORT, SSLIC_RST_PIN), IFX_MPS_MODULE_ID))\n-   {\n-      TRACE (MPS, DBG_LEVEL_HIGH,\n-             (KERN_ERR \"[%s %s %d]: GPIO port/pin reservation error.\\r\\n\",\n-              __FILE__, __func__, __LINE__));\n-   }\n-   /* P1_ALTSEL0.15 = 0 */\n-   if (ifx_gpio_altsel0_clear\n-       (IFX_GPIO_PIN_ID (SSLIC_RST_PORT, SSLIC_RST_PIN), IFX_MPS_MODULE_ID))\n-   {\n-      TRACE (MPS, DBG_LEVEL_HIGH,\n-             (KERN_ERR \"[%s %s %d]: GPIO error clearing ALTSEL0.\\r\\n\", __FILE__,\n-              __func__, __LINE__));\n-   }\n-   /* P1_ALTSEL1.15 = 0 */\n-   if (ifx_gpio_altsel1_clear\n-       (IFX_GPIO_PIN_ID (SSLIC_RST_PORT, SSLIC_RST_PIN), IFX_MPS_MODULE_ID))\n-   {\n-      TRACE (MPS, DBG_LEVEL_HIGH,\n-             (KERN_ERR \"[%s %s %d]: GPIO error clearing ALTSEL1.\\r\\n\", __FILE__,\n-              __func__, __LINE__));\n-   }\n-   /* P1_DIR.15 = 1 */\n-   if (ifx_gpio_dir_out_set\n-       (IFX_GPIO_PIN_ID (SSLIC_RST_PORT, SSLIC_RST_PIN), IFX_MPS_MODULE_ID))\n-   {\n-      TRACE (MPS, DBG_LEVEL_HIGH,\n-             (KERN_ERR \"[%s %s %d]: GPIO error setting DIR.\\r\\n\", __FILE__,\n-              __func__, __LINE__));\n-   }\n-   /* P1_OD.15 = 1 */\n-   if (ifx_gpio_open_drain_set\n-       (IFX_GPIO_PIN_ID (SSLIC_RST_PORT, SSLIC_RST_PIN), IFX_MPS_MODULE_ID))\n-   {\n-      TRACE (MPS, DBG_LEVEL_HIGH,\n-             (KERN_ERR \"[%s %s %d]: GPIO error setting OD.\\r\\n\", __FILE__,\n-              __func__, __LINE__));\n-   }\n-   /* P1_OUT.15 = 0 */\n-   if (ifx_gpio_output_clear\n-       (IFX_GPIO_PIN_ID (SSLIC_RST_PORT, SSLIC_RST_PIN), IFX_MPS_MODULE_ID))\n-   {\n-      TRACE (MPS, DBG_LEVEL_HIGH,\n-             (KERN_ERR \"[%s %s %d]: GPIO error clearing OUT.\\r\\n\", __FILE__,\n-              __func__, __LINE__));\n-   }\n-   if (ifx_gpio_pin_free\n-       (IFX_GPIO_PIN_ID (SSLIC_RST_PORT, SSLIC_RST_PIN), IFX_MPS_MODULE_ID))\n-   {\n-      TRACE (MPS, DBG_LEVEL_HIGH,\n-             (KERN_ERR \"[%s %s %d]: GPIO port/pin freeing error.\\r\\n\", __FILE__,\n-              __func__, __LINE__));\n-   }\n-   IFXOS_UNLOCKINT (flags);\n-\n-   /* recalculate and compare the firmware checksum */\n-   ifx_mps_fw_crc_compare(cpu1_base_addr, pFW_img_data);\n-\n-   /* dump exception area on a console */\n-   ifx_mps_dump_fw_xcpt(cpu1_base_addr, pFW_img_data);\n-\n-   if (IFX_NULL != ifx_wdog_callback)\n-   {\n-      /* call VMMC driver */\n-      ifx_wdog_callback (wdog_cleared_ok_count);\n-   }\n-   else\n-   {\n-      TRACE (MPS, DBG_LEVEL_HIGH,\n-             (KERN_WARNING \"MPS: VMMC watchdog timer callback is NULL.\\r\\n\"));\n-   }\n-   return 0;\n-}\n-\n-/**\n  * Register WDT callback.\n  * This function is called by VMMC driver to register its callback in\n  * the MPS driver.\n--- a/src/drv_vmmc_amazon_s.h\n+++ b/src/drv_vmmc_amazon_s.h\n@@ -15,9 +15,7 @@\n */\n \n \n-#if defined(SYSTEM_AR9) || defined(SYSTEM_VR9)\n-#include <asm/ifx/ifx_gpio.h>\n-#else\n+#if !defined(SYSTEM_AR9) && !defined(SYSTEM_VR9)\n #error no system selected\n #endif\n \n@@ -27,45 +25,6 @@\n */\n #define VMMC_PCM_IF_CFG_HOOK(mode, GPIOreserved, ret) \\\n do { \\\n-   ret = VMMC_statusOk; \\\n-   /* Reserve P0.0 as TDM/FSC */ \\\n-   if (!GPIOreserved) \\\n-      ret |= ifx_gpio_pin_reserve(IFX_GPIO_PIN_ID(0, 0), VMMC_TAPI_GPIO_MODULE_ID); \\\n-   ret |= ifx_gpio_altsel0_set(IFX_GPIO_PIN_ID(0, 0), VMMC_TAPI_GPIO_MODULE_ID); \\\n-   ret |= ifx_gpio_altsel1_set(IFX_GPIO_PIN_ID(0, 0), VMMC_TAPI_GPIO_MODULE_ID); \\\n-   ret |= ifx_gpio_open_drain_set(IFX_GPIO_PIN_ID(0, 0), VMMC_TAPI_GPIO_MODULE_ID);\\\n-   \\\n-   /* Reserve P1.9 as TDM/DO */ \\\n-   if (!GPIOreserved) \\\n-      ret |= ifx_gpio_pin_reserve(IFX_GPIO_PIN_ID(1, 9), VMMC_TAPI_GPIO_MODULE_ID); \\\n-   ret |= ifx_gpio_altsel0_set(IFX_GPIO_PIN_ID(1, 9), VMMC_TAPI_GPIO_MODULE_ID); \\\n-   ret |= ifx_gpio_altsel1_clear(IFX_GPIO_PIN_ID(1, 9), VMMC_TAPI_GPIO_MODULE_ID); \\\n-   ret |= ifx_gpio_dir_out_set(IFX_GPIO_PIN_ID(1, 9), VMMC_TAPI_GPIO_MODULE_ID); \\\n-   ret |= ifx_gpio_open_drain_set(IFX_GPIO_PIN_ID(1, 9), VMMC_TAPI_GPIO_MODULE_ID); \\\n-   \\\n-   /* Reserve P2.9 as TDM/DI */ \\\n-   if (!GPIOreserved) \\\n-      ret |= ifx_gpio_pin_reserve(IFX_GPIO_PIN_ID(2, 9), VMMC_TAPI_GPIO_MODULE_ID); \\\n-   ret |= ifx_gpio_altsel0_clear(IFX_GPIO_PIN_ID(2, 9), VMMC_TAPI_GPIO_MODULE_ID); \\\n-   ret |= ifx_gpio_altsel1_set(IFX_GPIO_PIN_ID(2, 9), VMMC_TAPI_GPIO_MODULE_ID);\\\n-   ret |= ifx_gpio_dir_in_set(IFX_GPIO_PIN_ID(2, 9), VMMC_TAPI_GPIO_MODULE_ID); \\\n-   \\\n-   /* Reserve P2.8 as TDM/DCL */ \\\n-   if (!GPIOreserved) \\\n-      ret |= ifx_gpio_pin_reserve(IFX_GPIO_PIN_ID(2, 8), VMMC_TAPI_GPIO_MODULE_ID); \\\n-   ret |= ifx_gpio_altsel0_clear(IFX_GPIO_PIN_ID(2, 8), VMMC_TAPI_GPIO_MODULE_ID); \\\n-   ret |= ifx_gpio_altsel1_set(IFX_GPIO_PIN_ID(2, 8), VMMC_TAPI_GPIO_MODULE_ID); \\\n-   ret |= ifx_gpio_open_drain_set(IFX_GPIO_PIN_ID(2, 8), VMMC_TAPI_GPIO_MODULE_ID); \\\n-   \\\n-   if (mode == 2) { \\\n-      /* TDM/FSC+DCL Master */ \\\n-      ret |= ifx_gpio_dir_out_set(IFX_GPIO_PIN_ID(0, 0), VMMC_TAPI_GPIO_MODULE_ID); \\\n-      ret |= ifx_gpio_dir_out_set(IFX_GPIO_PIN_ID(2, 8), VMMC_TAPI_GPIO_MODULE_ID); \\\n-   } else { \\\n-      /* TDM/FSC+DCL Slave */ \\\n-      ret |= ifx_gpio_dir_in_set(IFX_GPIO_PIN_ID(0, 0), VMMC_TAPI_GPIO_MODULE_ID); \\\n-      ret |= ifx_gpio_dir_in_set(IFX_GPIO_PIN_ID(2, 8), VMMC_TAPI_GPIO_MODULE_ID); \\\n-   } \\\n } while(0);\n \n /**\n@@ -73,11 +32,6 @@ do { \\\n */\n #define VMMC_DRIVER_UNLOAD_HOOK(ret) \\\n do { \\\n-   ret = VMMC_statusOk; \\\n-   ret |= ifx_gpio_pin_free(IFX_GPIO_PIN_ID(0, 0), VMMC_TAPI_GPIO_MODULE_ID); \\\n-   ret |= ifx_gpio_pin_free(IFX_GPIO_PIN_ID(1, 9), VMMC_TAPI_GPIO_MODULE_ID); \\\n-   ret |= ifx_gpio_pin_free(IFX_GPIO_PIN_ID(2, 9), VMMC_TAPI_GPIO_MODULE_ID); \\\n-   ret |= ifx_gpio_pin_free(IFX_GPIO_PIN_ID(2, 8), VMMC_TAPI_GPIO_MODULE_ID); \\\n } while (0)\n \n #endif /* _DRV_VMMC_AMAZON_S_H */\n"
  },
  {
    "path": "package/kernel/linux/Makefile",
    "content": "#\n# Copyright (C) 2006-2010 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\ninclude $(INCLUDE_DIR)/kernel.mk\n\nPKG_NAME:=kernel\nPKG_FLAGS:=hold\n\nPKG_BUILD_DIR:=$(KERNEL_BUILD_DIR)/packages\nSCAN_DEPS=modules/*.mk $(TOPDIR)/target/linux/*/modules.mk $(TOPDIR)/include/netfilter.mk\n\nPKG_LICENSE:=GPL-2.0\nPKG_LICENSE_FILES:=\n\nexport SHELL:=/bin/sh\n.ONESHELL:\n.SHELLFLAGS = -ec\n\ninclude $(INCLUDE_DIR)/package.mk\n\nifeq ($(DUMP),)\n  STAMP_BUILT:=$(STAMP_BUILT)_$(shell $(SCRIPT_DIR)/kconfig.pl $(LINUX_DIR)/.config | $(MKHASH) md5)\n  -include $(LINUX_DIR)/.config\nendif\n\ndefine Build/Prepare\n\tmkdir -p $(PKG_BUILD_DIR)\nendef\n\ndefine Build/Configure\nendef\n\ndefine Build/Compile\nendef\n\ndefine KernelPackage/depends\nendef\n\nCONFIG_PACKAGE_kernel=y\ndefine Package/kernel\n  SECTION:=sys\n  CATEGORY:=Kernel\n  DEFAULT:=y\n  TITLE:=Virtual kernel package\n  VERSION:=$(LINUX_VERSION)-$(LINUX_RELEASE)-$(LINUX_VERMAGIC)\n  URL:=http://www.kernel.org/\n  PKG_FLAGS:=nonshared\nendef\n\ndefine Package/kernel/install\n  # nothing to do\nendef\n\ndefine Package/kernel/extra_provides\n\tsed -e 's,.*/,,' $(LINUX_DIR)/modules.builtin;\nendef\n\n$(eval $(if $(DUMP),,$(call BuildPackage,kernel)))\n\ninclude $(sort $(wildcard ./modules/*.mk))\n-include $(TOPDIR)/target/linux/*/modules.mk\n"
  },
  {
    "path": "package/kernel/linux/files/hotplug-sched-teql.sh",
    "content": "#!/bin/sh\n\n. /lib/functions.sh\n\nif [ \"$ACTION\" != \"ifup\" ]; then\n\texit\nfi\n\nconfig_load network\n\nconfig_get teql $INTERFACE teql\n\nif [ \"$teql\" != \"\" ]; then\n    logger Adding device $DEVICE to TEQL master $teql\n    insmod sch_teql\n    tc qdisc add dev $DEVICE root $teql\n\n    # The kernel doesn't let us bring it up until it has at least one\n    # slave. So bring it up now, if it isn't already.\n    if ! cat /sys/class/net/$teql/carrier &>/dev/null; then\n        ifup $teql &\n    fi\nfi\n"
  },
  {
    "path": "package/kernel/linux/files/sysctl-br-netfilter.conf",
    "content": "# Do not edit, changes to this file will be lost on upgrades\n# /etc/sysctl.conf can be used to customize sysctl settings\n\n# disable bridge firewalling by default\nnet.bridge.bridge-nf-call-arptables=0\nnet.bridge.bridge-nf-call-ip6tables=0\nnet.bridge.bridge-nf-call-iptables=0\n"
  },
  {
    "path": "package/kernel/linux/files/sysctl-nf-conntrack.conf",
    "content": "# Do not edit, changes to this file will be lost on upgrades\n# /etc/sysctl.conf can be used to customize sysctl settings\n\nnet.netfilter.nf_conntrack_acct=1\nnet.netfilter.nf_conntrack_checksum=0\nnet.netfilter.nf_conntrack_tcp_timeout_established=7440\nnet.netfilter.nf_conntrack_udp_timeout=60\nnet.netfilter.nf_conntrack_udp_timeout_stream=180\n"
  },
  {
    "path": "package/kernel/linux/files/sysctl-tcp-bbr.conf",
    "content": "# Do not edit, changes to this file will be lost on upgrades\n# /etc/sysctl.conf can be used to customize sysctl settings\n\nnet.ipv4.tcp_congestion_control=bbr\n"
  },
  {
    "path": "package/kernel/linux/modules/001-depends.mk",
    "content": "#\n# Copyright (C) 2010-2011 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ndefine AddDepends/nls\n  DEPENDS+= +kmod-nls-base $(foreach cp,$(1),+kmod-nls-$(cp))\nendef\n\ndefine AddDepends/rfkill\n  DEPENDS+= +USE_RFKILL:kmod-rfkill $(1)\nendef\n"
  },
  {
    "path": "package/kernel/linux/modules/block.mk",
    "content": "#\n# Copyright (C) 2006-2012 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\nBLOCK_MENU:=Block Devices\n\ndefine KernelPackage/aoe\n  SUBMENU:=$(BLOCK_MENU)\n  TITLE:=ATA over Ethernet support\n  KCONFIG:=CONFIG_ATA_OVER_ETH\n  FILES:=$(LINUX_DIR)/drivers/block/aoe/aoe.ko\n  AUTOLOAD:=$(call AutoLoad,30,aoe)\nendef\n\ndefine KernelPackage/aoe/description\n Kernel support for ATA over Ethernet\nendef\n\n$(eval $(call KernelPackage,aoe))\n\n\ndefine KernelPackage/ata-core\n  SUBMENU:=$(BLOCK_MENU)\n  TITLE:=Serial and Parallel ATA support\n  DEPENDS:=@PCI_SUPPORT||TARGET_sunxi +kmod-scsi-core\n  KCONFIG:=CONFIG_ATA\n  FILES:=$(LINUX_DIR)/drivers/ata/libata.ko\nifneq ($(wildcard $(LINUX_DIR)/drivers/ata/libahci.ko),)\n  FILES+=$(LINUX_DIR)/drivers/ata/libahci.ko\nendif\nendef\n\n$(eval $(call KernelPackage,ata-core))\n\n\ndefine AddDepends/ata\n  SUBMENU:=$(BLOCK_MENU)\n  DEPENDS+=+kmod-ata-core $(1)\nendef\n\n\ndefine KernelPackage/ata-ahci\n  TITLE:=AHCI Serial ATA support\n  KCONFIG:=CONFIG_SATA_AHCI\n  FILES:= \\\n    $(LINUX_DIR)/drivers/ata/ahci.ko\n  AUTOLOAD:=$(call AutoLoad,41,libahci ahci,1)\n  $(call AddDepends/ata)\nendef\n\ndefine KernelPackage/ata-ahci/description\n Support for AHCI Serial ATA controllers\nendef\n\n$(eval $(call KernelPackage,ata-ahci))\n\n\ndefine KernelPackage/ata-ahci-platform\n  TITLE:=AHCI Serial ATA Platform support\n  KCONFIG:=CONFIG_SATA_AHCI_PLATFORM\n  FILES:= \\\n    $(LINUX_DIR)/drivers/ata/ahci_platform.ko \\\n    $(LINUX_DIR)/drivers/ata/libahci_platform.ko\n  AUTOLOAD:=$(call AutoLoad,40,libahci libahci_platform ahci_platform,1)\n  $(call AddDepends/ata,@TARGET_ipq806x||TARGET_layerscape||TARGET_sunxi)\nendef\n\ndefine KernelPackage/ata-ahci-platform/description\n Platform support for AHCI Serial ATA controllers\nendef\n\n$(eval $(call KernelPackage,ata-ahci-platform))\n\n\ndefine KernelPackage/ata-artop\n  TITLE:=ARTOP 6210/6260 PATA support\n  KCONFIG:=CONFIG_PATA_ARTOP\n  FILES:=$(LINUX_DIR)/drivers/ata/pata_artop.ko\n  AUTOLOAD:=$(call AutoLoad,41,pata_artop,1)\n  $(call AddDepends/ata)\nendef\n\ndefine KernelPackage/ata-artop/description\n PATA support for ARTOP 6210/6260 host controllers\nendef\n\n$(eval $(call KernelPackage,ata-artop))\n\n\ndefine KernelPackage/ata-marvell-sata\n  TITLE:=Marvell Serial ATA support\n  KCONFIG:=CONFIG_SATA_MV\n  FILES:=$(LINUX_DIR)/drivers/ata/sata_mv.ko\n  AUTOLOAD:=$(call AutoLoad,41,sata_mv,1)\n  $(call AddDepends/ata)\nendef\n\ndefine KernelPackage/ata-marvell-sata/description\n SATA support for marvell chipsets\nendef\n\n$(eval $(call KernelPackage,ata-marvell-sata))\n\n\ndefine KernelPackage/ata-nvidia-sata\n  TITLE:=Nvidia Serial ATA support\n  KCONFIG:=CONFIG_SATA_NV\n  FILES:=$(LINUX_DIR)/drivers/ata/sata_nv.ko\n  AUTOLOAD:=$(call AutoLoad,41,sata_nv,1)\n  $(call AddDepends/ata)\nendef\n\n$(eval $(call KernelPackage,ata-nvidia-sata))\n\n\ndefine KernelPackage/ata-pdc202xx-old\n  TITLE:=Older Promise PATA controller support\n  KCONFIG:= \\\n       CONFIG_ATA_SFF=y \\\n       CONFIG_PATA_PDC_OLD\n  FILES:=$(LINUX_DIR)/drivers/ata/pata_pdc202xx_old.ko\n  AUTOLOAD:=$(call AutoLoad,41,pata_pdc202xx_old,1)\n  $(call AddDepends/ata)\nendef\n\ndefine KernelPackage/ata-pdc202xx-old/description\n This option enables support for the Promise 20246, 20262, 20263,\n 20265 and 20267 adapters\nendef\n\n$(eval $(call KernelPackage,ata-pdc202xx-old))\n\n\ndefine KernelPackage/ata-piix\n  TITLE:=Intel PIIX PATA/SATA support\n  KCONFIG:=CONFIG_ATA_PIIX\n  FILES:=$(LINUX_DIR)/drivers/ata/ata_piix.ko\n  AUTOLOAD:=$(call AutoLoad,41,ata_piix,1)\n  $(call AddDepends/ata)\nendef\n\ndefine KernelPackage/ata-piix/description\n SATA support for Intel ICH5/6/7/8 series host controllers and\n PATA support for Intel ESB/ICH/PIIX3/PIIX4 series host controllers\nendef\n\n$(eval $(call KernelPackage,ata-piix))\n\n\ndefine KernelPackage/ata-sil\n  TITLE:=Silicon Image SATA support\n  KCONFIG:=CONFIG_SATA_SIL\n  FILES:=$(LINUX_DIR)/drivers/ata/sata_sil.ko\n  AUTOLOAD:=$(call AutoLoad,41,sata_sil,1)\n  $(call AddDepends/ata)\nendef\n\ndefine KernelPackage/ata-sil/description\n Support for Silicon Image Serial ATA controllers\nendef\n\n$(eval $(call KernelPackage,ata-sil))\n\n\ndefine KernelPackage/ata-sil24\n  TITLE:=Silicon Image 3124/3132 SATA support\n  KCONFIG:=CONFIG_SATA_SIL24\n  FILES:=$(LINUX_DIR)/drivers/ata/sata_sil24.ko\n  AUTOLOAD:=$(call AutoLoad,41,sata_sil24,1)\n  $(call AddDepends/ata)\nendef\n\ndefine KernelPackage/ata-sil24/description\n Support for Silicon Image 3124/3132 Serial ATA controllers\nendef\n\n$(eval $(call KernelPackage,ata-sil24))\n\n\ndefine KernelPackage/ata-via-sata\n  TITLE:=VIA SATA support\n  KCONFIG:=CONFIG_SATA_VIA\n  FILES:=$(LINUX_DIR)/drivers/ata/sata_via.ko\n  AUTOLOAD:=$(call AutoLoad,41,sata_via,1)\n  $(call AddDepends/ata)\nendef\n\ndefine KernelPackage/ata-via-sata/description\n This option enables support for VIA Serial ATA\nendef\n\n$(eval $(call KernelPackage,ata-via-sata))\n\n\ndefine KernelPackage/block2mtd\n  SUBMENU:=$(BLOCK_MENU)\n  TITLE:=Block device MTD emulation\n  KCONFIG:=CONFIG_MTD_BLOCK2MTD\n  FILES:=$(LINUX_DIR)/drivers/mtd/devices/block2mtd.ko\nendef\n\n$(eval $(call KernelPackage,block2mtd))\n\n\ndefine KernelPackage/dax\n  SUBMENU:=$(BLOCK_MENU)\n  TITLE:=DAX: direct access to differentiated memory\n  KCONFIG:=CONFIG_DAX\n  FILES:=$(LINUX_DIR)/drivers/dax/dax.ko\nendef\n\n$(eval $(call KernelPackage,dax))\n\n\ndefine KernelPackage/dm\n  SUBMENU:=$(BLOCK_MENU)\n  TITLE:=Device Mapper\n  DEPENDS:=+kmod-crypto-manager +kmod-dax +KERNEL_KEYS:kmod-keys-encrypted\n  # All the \"=n\" are unnecessary, they're only there\n  # to stop the config from asking the question.\n  # MIRROR is M because I've needed it for pvmove.\n  KCONFIG:= \\\n\tCONFIG_BLK_DEV_MD=n \\\n\tCONFIG_DM_DEBUG=n \\\n\tCONFIG_DM_UEVENT=n \\\n\tCONFIG_DM_DELAY=n \\\n\tCONFIG_DM_LOG_WRITES=n \\\n\tCONFIG_DM_MQ_DEFAULT=n \\\n\tCONFIG_DM_MULTIPATH=n \\\n\tCONFIG_DM_ZERO=n \\\n\tCONFIG_DM_SNAPSHOT=n \\\n\tCONFIG_DM_LOG_USERSPACE=n \\\n\tCONFIG_MD=y \\\n\tCONFIG_BLK_DEV_DM \\\n\tCONFIG_DM_CRYPT \\\n\tCONFIG_DM_MIRROR\n  FILES:= \\\n    $(LINUX_DIR)/drivers/md/dm-mod.ko \\\n    $(LINUX_DIR)/drivers/md/dm-crypt.ko \\\n    $(LINUX_DIR)/drivers/md/dm-log.ko \\\n    $(LINUX_DIR)/drivers/md/dm-mirror.ko \\\n    $(LINUX_DIR)/drivers/md/dm-region-hash.ko\n  AUTOLOAD:=$(call AutoLoad,30,dm-mod dm-log dm-region-hash dm-mirror dm-crypt,1)\nendef\n\ndefine KernelPackage/dm/description\n Kernel module necessary for LVM2 support\nendef\n\n$(eval $(call KernelPackage,dm))\n\ndefine KernelPackage/dm-raid\n  SUBMENU:=$(BLOCK_MENU)\n  TITLE:=LVM2 raid support\n  DEPENDS:=+kmod-dm +kmod-md-mod \\\n           +kmod-md-raid0 +kmod-md-raid1 +kmod-md-raid10 +kmod-md-raid456\n  KCONFIG:= \\\n\tCONFIG_DM_RAID\n  FILES:=$(LINUX_DIR)/drivers/md/dm-raid.ko\n  AUTOLOAD:=$(call AutoLoad,31,dm-raid)\nendef\n\ndefine KernelPackage/dm-raid/description\n Kernel module necessary for LVM2 raid support\nendef\n\n$(eval $(call KernelPackage,dm-raid))\n\n\ndefine KernelPackage/iscsi-initiator\n  SUBMENU:=$(BLOCK_MENU)\n  TITLE:=iSCSI Initiator over TCP/IP\n  DEPENDS:=+kmod-scsi-core +kmod-crypto-hash\n  KCONFIG:= \\\n\tCONFIG_INET \\\n\tCONFIG_SCSI_LOWLEVEL=y \\\n\tCONFIG_ISCSI_TCP \\\n\tCONFIG_SCSI_ISCSI_ATTRS=y\n  FILES:= \\\n\t$(LINUX_DIR)/drivers/scsi/iscsi_tcp.ko \\\n\t$(LINUX_DIR)/drivers/scsi/libiscsi.ko \\\n\t$(LINUX_DIR)/drivers/scsi/libiscsi_tcp.ko \\\n\t$(LINUX_DIR)/drivers/scsi/scsi_transport_iscsi.ko\n  AUTOLOAD:=$(call AutoProbe,libiscsi libiscsi_tcp scsi_transport_iscsi iscsi_tcp)\nendef\n\ndefine KernelPackage/iscsi-initiator/description\nThe iSCSI Driver provides a host with the ability to access storage through an\nIP network. The driver uses the iSCSI protocol to transport SCSI requests and\nresponses over a TCP/IP network between the host (the \"initiator\") and \"targets\".\nendef\n\n$(eval $(call KernelPackage,iscsi-initiator))\n\n\ndefine KernelPackage/md-mod\n  SUBMENU:=$(BLOCK_MENU)\n  TITLE:=MD RAID\n  KCONFIG:= \\\n       CONFIG_MD=y \\\n       CONFIG_BLK_DEV_MD=m \\\n       CONFIG_MD_AUTODETECT=y \\\n       CONFIG_MD_FAULTY=n\n  FILES:=$(LINUX_DIR)/drivers/md/md-mod.ko\n  AUTOLOAD:=$(call AutoLoad,27,md-mod)\nendef\n\ndefine KernelPackage/md-mod/description\n Kernel RAID md module (md-mod.ko).\n You will need to select at least one RAID level module below.\nendef\n\n$(eval $(call KernelPackage,md-mod))\n\n\ndefine KernelPackage/md/Depends\n  SUBMENU:=$(BLOCK_MENU)\n  DEPENDS:=kmod-md-mod $(1)\nendef\n\n\ndefine KernelPackage/md-linear\n$(call KernelPackage/md/Depends,)\n  TITLE:=RAID Linear Module\n  KCONFIG:=CONFIG_MD_LINEAR\n  FILES:=$(LINUX_DIR)/drivers/md/linear.ko\n  AUTOLOAD:=$(call AutoLoad,28,linear)\nendef\n\ndefine KernelPackage/md-linear/description\n RAID \"Linear\" or \"Append\" driver module (linear.ko)\nendef\n\n$(eval $(call KernelPackage,md-linear))\n\n\ndefine KernelPackage/md-raid0\n$(call KernelPackage/md/Depends,)\n  TITLE:=RAID0 Module\n  KCONFIG:=CONFIG_MD_RAID0\n  FILES:=$(LINUX_DIR)/drivers/md/raid0.ko\n  AUTOLOAD:=$(call AutoLoad,28,raid0)\nendef\n\ndefine KernelPackage/md-raid0/description\n RAID Level 0 (Striping) driver module (raid0.ko)\nendef\n\n$(eval $(call KernelPackage,md-raid0))\n\n\ndefine KernelPackage/md-raid1\n$(call KernelPackage/md/Depends,)\n  TITLE:=RAID1 Module\n  KCONFIG:=CONFIG_MD_RAID1\n  FILES:=$(LINUX_DIR)/drivers/md/raid1.ko\n  AUTOLOAD:=$(call AutoLoad,28,raid1)\nendef\n\ndefine KernelPackage/md-raid1/description\n RAID Level 1 (Mirroring) driver (raid1.ko)\nendef\n\n$(eval $(call KernelPackage,md-raid1))\n\n\ndefine KernelPackage/md-raid10\n$(call KernelPackage/md/Depends,)\n  TITLE:=RAID10 Module\n  KCONFIG:=CONFIG_MD_RAID10\n  FILES:=$(LINUX_DIR)/drivers/md/raid10.ko\n  AUTOLOAD:=$(call AutoLoad,28,raid10)\nendef\n\ndefine KernelPackage/md-raid10/description\n RAID Level 10 (Mirroring+Striping) driver module (raid10.ko)\nendef\n\n$(eval $(call KernelPackage,md-raid10))\n\n\ndefine KernelPackage/md-raid456\n$(call KernelPackage/md/Depends,+kmod-lib-raid6 +kmod-lib-xor +kmod-lib-crc32c)\n  TITLE:=RAID Level 456 Driver\n  KCONFIG:= \\\n       CONFIG_ASYNC_CORE \\\n       CONFIG_ASYNC_MEMCPY \\\n       CONFIG_ASYNC_XOR \\\n       CONFIG_ASYNC_PQ \\\n       CONFIG_ASYNC_RAID6_RECOV \\\n       CONFIG_ASYNC_RAID6_TEST=n \\\n       CONFIG_MD_RAID456 \\\n       CONFIG_MULTICORE_RAID456=n\n  FILES:= \\\n\t$(LINUX_DIR)/crypto/async_tx/async_tx.ko \\\n\t$(LINUX_DIR)/crypto/async_tx/async_memcpy.ko \\\n\t$(LINUX_DIR)/crypto/async_tx/async_xor.ko \\\n\t$(LINUX_DIR)/crypto/async_tx/async_pq.ko \\\n\t$(LINUX_DIR)/crypto/async_tx/async_raid6_recov.ko \\\n\t$(LINUX_DIR)/drivers/md/raid456.ko\n  AUTOLOAD:=$(call AutoLoad,28, async_tx async_memcpy async_xor async_pq async_raid6_recov raid456)\nendef\n\ndefine KernelPackage/md-raid456/description\n RAID Level 4,5,6 kernel module (raid456.ko)\n\n Includes the following modules required by\n raid456.ko:\n    xor.ko\n    async_tx.ko\n    async_xor.ko\n    async_memcpy.ko\n    async_pq.ko\n    async_raid5_recov.ko\n    raid6_pq.ko\nendef\n\n$(eval $(call KernelPackage,md-raid456))\n\n\ndefine KernelPackage/md-multipath\n$(call KernelPackage/md/Depends,)\n  TITLE:=MD Multipath Module\n  KCONFIG:=CONFIG_MD_MULTIPATH\n  FILES:=$(LINUX_DIR)/drivers/md/multipath.ko\n  AUTOLOAD:=$(call AutoLoad,29,multipath)\nendef\n\ndefine KernelPackage/md-multipath/description\n Multipath driver module (multipath.ko)\nendef\n\n$(eval $(call KernelPackage,md-multipath))\n\n\ndefine KernelPackage/libsas\n  SUBMENU:=$(BLOCK_MENU)\n  DEPENDS:=@TARGET_x86\n  TITLE:=SAS Domain Transport Attributes\n  KCONFIG:=CONFIG_SCSI_SAS_LIBSAS \\\n\tCONFIG_SCSI_SAS_ATTRS \\\n\tCONFIG_SCSI_SAS_ATA=y \\\n\tCONFIG_SCSI_SAS_HOST_SMP=y \\\n\tCONFIG_SCSI_SAS_LIBSAS_DEBUG=y\n  FILES:= \\\n\t$(LINUX_DIR)/drivers/scsi/scsi_transport_sas.ko \\\n\t$(LINUX_DIR)/drivers/scsi/libsas/libsas.ko\n  AUTOLOAD:=$(call AutoLoad,29,scsi_transport_sas libsas,1)\nendef\n\ndefine KernelPackage/libsas/description\n SAS Domain Transport Attributes support\nendef\n\n$(eval $(call KernelPackage,libsas,1))\n\n\ndefine KernelPackage/loop\n  SUBMENU:=$(BLOCK_MENU)\n  TITLE:=Loopback device support\n  KCONFIG:= \\\n\tCONFIG_BLK_DEV_LOOP \\\n\tCONFIG_BLK_DEV_CRYPTOLOOP=n\n  FILES:=$(LINUX_DIR)/drivers/block/loop.ko\n  AUTOLOAD:=$(call AutoLoad,30,loop)\nendef\n\ndefine KernelPackage/loop/description\n Kernel module for loopback device support\nendef\n\n$(eval $(call KernelPackage,loop))\n\n\ndefine KernelPackage/mvsas\n  SUBMENU:=$(BLOCK_MENU)\n  TITLE:=Marvell 88SE6440 SAS/SATA driver\n  DEPENDS:=@TARGET_x86 +kmod-libsas\n  KCONFIG:= \\\n\tCONFIG_SCSI_MVSAS \\\n\tCONFIG_SCSI_MVSAS_TASKLET=n\n  FILES:=$(LINUX_DIR)/drivers/scsi/mvsas/mvsas.ko\n  AUTOLOAD:=$(call AutoLoad,40,mvsas,1)\nendef\n\ndefine KernelPackage/mvsas/description\n Kernel support for the Marvell SAS SCSI adapters\nendef\n\n$(eval $(call KernelPackage,mvsas))\n\n\ndefine KernelPackage/nbd\n  SUBMENU:=$(BLOCK_MENU)\n  TITLE:=Network block device support\n  KCONFIG:=CONFIG_BLK_DEV_NBD\n  FILES:=$(LINUX_DIR)/drivers/block/nbd.ko\n  AUTOLOAD:=$(call AutoLoad,30,nbd)\nendef\n\ndefine KernelPackage/nbd/description\n Kernel module for network block device support\nendef\n\n$(eval $(call KernelPackage,nbd))\n\n\ndefine KernelPackage/scsi-core\n  SUBMENU:=$(BLOCK_MENU)\n  TITLE:=SCSI device support\n  KCONFIG:= \\\n\tCONFIG_SCSI \\\n\tCONFIG_SCSI_COMMON@ge5.15 \\\n\tCONFIG_BLK_DEV_SD\n  FILES:= \\\n\t$(LINUX_DIR)/drivers/scsi/scsi_mod.ko \\\n\t$(LINUX_DIR)/drivers/scsi/scsi_common.ko@ge5.15 \\\n\t$(LINUX_DIR)/drivers/scsi/sd_mod.ko\n  AUTOLOAD:=$(call AutoLoad,40,scsi_mod scsi_common@ge5.15 sd_mod,1)\nendef\n\n$(eval $(call KernelPackage,scsi-core))\n\n\ndefine KernelPackage/scsi-generic\n  SUBMENU:=$(BLOCK_MENU)\n  TITLE:=Kernel support for SCSI generic\n  DEPENDS:=+kmod-scsi-core\n  KCONFIG:= \\\n\tCONFIG_CHR_DEV_SG\n  FILES:= \\\n\t$(LINUX_DIR)/drivers/scsi/sg.ko\n  AUTOLOAD:=$(call AutoLoad,65,sg)\nendef\n\n$(eval $(call KernelPackage,scsi-generic))\n\n\ndefine KernelPackage/cdrom\n  TITLE:=Kernel library module for CD / DVD drives\n  KCONFIG:=CONFIG_CDROM\n  HIDDEN:=1\n  FILES:=$(LINUX_DIR)/drivers/cdrom/cdrom.ko\nendef\n\n$(eval $(call KernelPackage,cdrom))\n\n\ndefine KernelPackage/scsi-cdrom\n  SUBMENU:=$(BLOCK_MENU)\n  TITLE:=Kernel support for CD / DVD drives\n  DEPENDS:=+kmod-scsi-core +kmod-cdrom\n  KCONFIG:= \\\n    CONFIG_BLK_DEV_SR \\\n    CONFIG_BLK_DEV_SR_VENDOR=n\n  FILES:=$(LINUX_DIR)/drivers/scsi/sr_mod.ko\n  AUTOLOAD:=$(call AutoLoad,45,sr_mod)\nendef\n\n$(eval $(call KernelPackage,scsi-cdrom))\n\n\ndefine KernelPackage/scsi-tape\n  SUBMENU:=$(BLOCK_MENU)\n  TITLE:=Kernel support for scsi tape drives\n  DEPENDS:=+kmod-scsi-core\n  KCONFIG:= \\\n    CONFIG_CHR_DEV_ST\n  FILES:= \\\n    $(LINUX_DIR)/drivers/scsi/st.ko\n  AUTOLOAD:=$(call AutoLoad,45,st)\nendef\n\n$(eval $(call KernelPackage,scsi-tape))\n\ndefine KernelPackage/iosched-bfq\n  SUBMENU:=$(BLOCK_MENU)\n  TITLE:=Kernel support for BFQ I/O scheduler\n  KCONFIG:= \\\n    CONFIG_IOSCHED_BFQ \\\n    CONFIG_BFQ_GROUP_IOSCHED=y \\\n    CONFIG_BFQ_CGROUP_DEBUG=n\n  FILES:= \\\n    $(LINUX_DIR)/block/bfq.ko\n  AUTOLOAD:=$(call AutoLoad,10,bfq)\nendef\n\n$(eval $(call KernelPackage,iosched-bfq))\n"
  },
  {
    "path": "package/kernel/linux/modules/can.mk",
    "content": "#\n# Copyright (C) 2013 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\nCAN_MENU:=CAN Support\n\ndefine KernelPackage/can\n  SUBMENU:=$(CAN_MENU)\n  TITLE:=CAN bus support\n  KCONFIG:=\\\n\tCONFIG_CAN=m \\\n\tCONFIG_CAN_DEV \\\n\tCONFIG_CAN_CALC_BITTIMING=y \\\n\tCONFIG_CAN_LEDS=y \\\n\tCONFIG_CAN_AT91=n \\\n\tCONFIG_CAN_TI_HECC=n \\\n\tCONFIG_CAN_MCP251X=n \\\n\tCONFIG_CAN_BFIN=n \\\n\tCONFIG_CAN_JANZ_ICAN3=n \\\n\tCONFIG_PCH_CAN=n \\\n\tCONFIG_CAN_GRCAN=n \\\n\tCONFIG_CAN_CC770=n \\\n\tCONFIG_CAN_MSCAN=n \\\n\tCONFIG_CAN_SJA1000=n \\\n\tCONFIG_CAN_SOFTING=n \\\n\tCONFIG_NET_EMATCH_CANID=n \\\n\tCONFIG_CAN_DEBUG_DEVICES=n\n  FILES:=$(LINUX_DIR)/drivers/net/can/dev/can-dev.ko \\\n\t $(LINUX_DIR)/net/can/can.ko\n  AUTOLOAD:=$(call AutoProbe,can can-dev)\nendef\n\ndefine KernelPackage/can/description\n Kernel module for CAN bus support.\nendef\n\n$(eval $(call KernelPackage,can))\n\n\ndefine AddDepends/can\n  SUBMENU:=$(CAN_MENU)\n  DEPENDS+=kmod-can $(1)\nendef\n\n\ndefine KernelPackage/can-bcm\n  TITLE:=Broadcast Manager CAN Protcol\n  KCONFIG:=CONFIG_CAN_BCM\n  FILES:=$(LINUX_DIR)/net/can/can-bcm.ko\n  AUTOLOAD:=$(call AutoProbe,can-bcm)\n  $(call AddDepends/can)\nendef\n\ndefine KernelPackage/can-bcm/description\n The Broadcast Manager offers content filtering, timeout monitoring,\n sending of RTR frames, and cyclic CAN messages without permanent user\n interaction.\nendef\n\n$(eval $(call KernelPackage,can-bcm))\n\n\ndefine KernelPackage/can-c-can\n  TITLE:=BOSCH C_CAN/D_CAN drivers\n  KCONFIG:=CONFIG_CAN_C_CAN\n  FILES:=$(LINUX_DIR)/drivers/net/can/c_can/c_can.ko\n  AUTOLOAD:=$(call AutoProbe,c_can)\n  $(call AddDepends/can)\nendef\n\ndefine KernelPackage/can-c-can/description\n This driver adds generic support for the C_CAN/D_CAN chips.\nendef\n\n$(eval $(call KernelPackage,can-c-can))\n\n\ndefine KernelPackage/can-c-can-pci\n  TITLE:=PCI Bus based BOSCH C_CAN/D_CAN driver\n  KCONFIG:=CONFIG_CAN_C_CAN_PCI\n  DEPENDS:=kmod-can-c-can @PCI_SUPPORT\n  FILES:=$(LINUX_DIR)/drivers/net/can/c_can/c_can_pci.ko\n  AUTOLOAD:=$(call AutoProbe,c_can_pci)\n  $(call AddDepends/can)\nendef\n\ndefine KernelPackage/can-c-can-pci/description\n This driver adds support for the C_CAN/D_CAN chips connected\n to the PCI bus.\nendef\n\n$(eval $(call KernelPackage,can-c-can-pci))\n\n\ndefine KernelPackage/can-c-can-platform\n  TITLE:=Platform Bus based BOSCH C_CAN/D_CAN driver\n  KCONFIG:=CONFIG_CAN_C_CAN_PLATFORM\n  DEPENDS:=kmod-can-c-can +kmod-regmap-core\n  FILES:=$(LINUX_DIR)/drivers/net/can/c_can/c_can_platform.ko\n  AUTOLOAD:=$(call AutoProbe,c_can_platform)\n  $(call AddDepends/can)\nendef\n\ndefine KernelPackage/can-c-can-platform/description\n This driver adds support for the C_CAN/D_CAN chips connected\n to the \"platform bus\" (Linux abstraction for directly to the\n processor attached devices) which can be found on various\n boards from ST Microelectronics (http://www.st.com) like the\n SPEAr1310 and SPEAr320 evaluation boards & TI (www.ti.com)\n boards like am335x, dm814x, dm813x and dm811x.\nendef\n\n$(eval $(call KernelPackage,can-c-can-platform))\n\n\ndefine KernelPackage/can-flexcan\n  TITLE:=Support for Freescale FLEXCAN based chips\n  KCONFIG:=CONFIG_CAN_FLEXCAN\n  FILES:=$(LINUX_DIR)/drivers/net/can/flexcan.ko\n  AUTOLOAD:=$(call AutoProbe,flexcan)\n  $(call AddDepends/can,@TARGET_imx)\nendef\n\ndefine KernelPackage/can-flexcan/description\n Freescale FLEXCAN CAN bus controller implementation.\nendef\n\n$(eval $(call KernelPackage,can-flexcan))\n\n\ndefine KernelPackage/can-gw\n  TITLE:=CAN Gateway/Router\n  KCONFIG:=CONFIG_CAN_GW\n  FILES:=$(LINUX_DIR)/net/can/can-gw.ko\n  AUTOLOAD:=$(call AutoProbe,can-gw)\n  $(call AddDepends/can)\nendef\n\ndefine KernelPackage/can-gw/description\n The CAN Gateway/Router is used to route (and modify) CAN frames.\nendef\n\n$(eval $(call KernelPackage,can-gw))\n\n\ndefine KernelPackage/can-mcp251x\n  TITLE:=MCP251x SPI CAN controller\n  KCONFIG:=\\\n\tCONFIG_SPI=y \\\n\tCONFIG_CAN_MCP251X\n  FILES:=$(LINUX_DIR)/drivers/net/can/spi/mcp251x.ko\n  AUTOLOAD:=$(call AutoProbe,can-mcp251x)\n  $(call AddDepends/can)\nendef\n\ndefine KernelPackage/can-mcp251x/description\n Microchip MCP251x SPI CAN controller\nendef\n\n$(eval $(call KernelPackage,can-mcp251x))\n\n\ndefine KernelPackage/can-raw\n  TITLE:=Raw CAN Protcol\n  KCONFIG:=CONFIG_CAN_RAW\n  FILES:=$(LINUX_DIR)/net/can/can-raw.ko\n  AUTOLOAD:=$(call AutoProbe,can-raw)\n  $(call AddDepends/can)\nendef\n\ndefine KernelPackage/can-raw/description\n The raw CAN protocol option offers access to the CAN bus via\n the BSD  socket API.\nendef\n\n$(eval $(call KernelPackage,can-raw))\n\n\ndefine KernelPackage/can-slcan\n  TITLE:=Serial / USB serial CAN Adaptors (slcan)\n  KCONFIG:=CONFIG_CAN_SLCAN\n  FILES:=$(LINUX_DIR)/drivers/net/can/slcan.ko\n  AUTOLOAD:=$(call AutoProbe,slcan)\n  $(call AddDepends/can)\nendef\n\ndefine KernelPackage/can-slcan/description\n CAN driver for several 'low cost' CAN interfaces that are attached\n via serial lines or via USB-to-serial adapters using the LAWICEL\n ASCII protocol.\nendef\n\n$(eval $(call KernelPackage,can-slcan))\n\n\ndefine KernelPackage/can-usb-8dev\n  TITLE:=8 devices USB2CAN interface\n  KCONFIG:=CONFIG_CAN_8DEV_USB\n  FILES:=$(LINUX_DIR)/drivers/net/can/usb/usb_8dev.ko\n  AUTOLOAD:=$(call AutoProbe,usb_8dev)\n  $(call AddDepends/can,+kmod-usb-core)\nendef\n\ndefine KernelPackage/can-usb-8dev/description\n This driver supports the USB2CAN interface\n from 8 devices (http://www.8devices.com).\nendef\n\n$(eval $(call KernelPackage,can-usb-8dev))\n\n\ndefine KernelPackage/can-usb-ems\n  TITLE:=EMS CPC-USB/ARM7 CAN/USB interface\n  KCONFIG:=CONFIG_CAN_EMS_USB\n  FILES:=$(LINUX_DIR)/drivers/net/can/usb/ems_usb.ko\n  AUTOLOAD:=$(call AutoProbe,ems_usb)\n  $(call AddDepends/can,+kmod-usb-core)\nendef\n\ndefine KernelPackage/can-usb-ems/description\n This driver is for the one channel CPC-USB/ARM7 CAN/USB interface\n from EMS Dr. Thomas Wuensche (http://www.ems-wuensche.de).\nendef\n\n$(eval $(call KernelPackage,can-usb-ems))\n\n\ndefine KernelPackage/can-usb-esd\n  TITLE:=ESD USB/2 CAN/USB interface\n  KCONFIG:=CONFIG_CAN_ESD_USB2\n  FILES:=$(LINUX_DIR)/drivers/net/can/usb/esd_usb2.ko\n  AUTOLOAD:=$(call AutoProbe,esd_usb2)\n  $(call AddDepends/can,+kmod-usb-core)\nendef\n\ndefine KernelPackage/can-usb-esd/description\n This driver supports the CAN-USB/2 interface\n from esd electronic system design gmbh (http://www.esd.eu).\nendef\n\n$(eval $(call KernelPackage,can-usb-esd))\n\n\ndefine KernelPackage/can-usb-kvaser\n  TITLE:=Kvaser CAN/USB interface\n  KCONFIG:=CONFIG_CAN_KVASER_USB\n  FILES:= \\\n\t$(LINUX_DIR)/drivers/net/can/usb/kvaser_usb/kvaser_usb.ko\n  AUTOLOAD:=$(call AutoProbe,kvaser_usb)\n  $(call AddDepends/can,+kmod-usb-core)\nendef\n\ndefine KernelPackage/can-usb-kvaser/description\n This driver adds support for Kvaser CAN/USB devices like Kvaser\n Leaf Light.\nendef\n\n$(eval $(call KernelPackage,can-usb-kvaser))\n\n\ndefine KernelPackage/can-usb-peak\n  TITLE:=PEAK PCAN-USB/USB Pro interfaces\n  KCONFIG:=CONFIG_CAN_PEAK_USB\n  FILES:=$(LINUX_DIR)/drivers/net/can/usb/peak_usb/peak_usb.ko\n  AUTOLOAD:=$(call AutoProbe,peak_usb)\n  $(call AddDepends/can,+kmod-usb-core)\nendef\n\ndefine KernelPackage/can-usb-peak/description\n This driver supports the PCAN-USB and PCAN-USB Pro adapters\n from PEAK-System Technik (http://www.peak-system.com).\nendef\n\n$(eval $(call KernelPackage,can-usb-peak))\n\n\ndefine KernelPackage/can-vcan\n  TITLE:=Virtual Local CAN Interface (vcan)\n  KCONFIG:=CONFIG_CAN_VCAN\n  FILES:=$(LINUX_DIR)/drivers/net/can/vcan.ko\n  AUTOLOAD:=$(call AutoProbe,vcan)\n  $(call AddDepends/can)\nendef\n\ndefine KernelPackage/can-vcan/description\n Similar to the network loopback devices, vcan offers a\n virtual local CAN interface.\nendef\n\n$(eval $(call KernelPackage,can-vcan))\n\ndefine KernelPackage/can-xilinx-can\n  TITLE:=Xilinx CAN IP\n  KCONFIG:=CONFIG_CAN_XILINXCAN\n  FILES:=$(LINUX_DIR)/drivers/net/can/xilinx_can.ko\n  AUTOLOAD:=$(call AutoProbe,xilinx_can)\n  $(call AddDepends/can,@TARGET_zynq)\nendef\n\ndefine KernelPackage/can-xilinx-can/description\n Xilinx CAN driver. This driver supports both\n soft AXI CAN IP and Zynq CANPS IP.\nendef\n\n$(eval $(call KernelPackage,can-xilinx-can))\n"
  },
  {
    "path": "package/kernel/linux/modules/crypto.mk",
    "content": "#\n# Copyright (C) 2006-2011 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\nCRYPTO_MENU:=Cryptographic API modules\n\nCRYPTO_MODULES = \\\n\tALGAPI2=crypto_algapi \\\n\tBLKCIPHER2=crypto_blkcipher\n\nCRYPTO_TARGET = $(BOARD)/$(if $(SUBTARGET),$(SUBTARGET),generic)\n\ncrypto_confvar=CONFIG_CRYPTO_$(word 1,$(subst =,$(space),$(1)))\ncrypto_file=$(LINUX_DIR)/crypto/$(word 2,$(subst =,$(space),$(1))).ko\ncrypto_name=$(if $(findstring y,$($(call crypto_confvar,$(1)))),,$(word 2,$(subst =,$(space),$(1))))\n\ndefine AddDepends/crypto\n  SUBMENU:=$(CRYPTO_MENU)\n  DEPENDS+= $(1)\nendef\n\n\ndefine KernelPackage/crypto-acompress\n  TITLE:=Asynchronous Compression operations\n  HIDDEN:=1\n  KCONFIG:=CONFIG_CRYPTO_ACOMP2\n  FILES:=$(LINUX_DIR)/crypto/crypto_acompress.ko\n  AUTOLOAD:=$(call AutoLoad,09,crypto_acompress)\n  $(call AddDepends/crypto)\nendef\n\n$(eval $(call KernelPackage,crypto-acompress))\n\n\ndefine KernelPackage/crypto-aead\n  TITLE:=CryptoAPI AEAD support\n  KCONFIG:= \\\n\tCONFIG_CRYPTO_AEAD \\\n\tCONFIG_CRYPTO_AEAD2\n  FILES:= \\\n\t  $(LINUX_DIR)/crypto/aead.ko \\\n\t  $(LINUX_DIR)/crypto/geniv.ko@ge5.10\n  AUTOLOAD:=$(call AutoLoad,09,aead,1)\n  $(call AddDepends/crypto, +kmod-crypto-null)\nendef\n\n$(eval $(call KernelPackage,crypto-aead))\n\n\ndefine KernelPackage/crypto-arc4\n  TITLE:=ARC4 cipher CryptoAPI module\n  KCONFIG:= \\\n\t  CONFIG_CRYPTO_ARC4 \\\n\t  CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE=y\n  FILES:= \\\n\t  $(LINUX_DIR)/crypto/arc4.ko \\\n\t  $(LINUX_DIR)/lib/crypto/libarc4.ko\n  AUTOLOAD:=$(call AutoLoad,09,arc4)\n  $(call AddDepends/crypto)\nendef\n\n$(eval $(call KernelPackage,crypto-arc4))\n\n\ndefine KernelPackage/crypto-authenc\n  TITLE:=Combined mode wrapper for IPsec\n  DEPENDS:=+kmod-crypto-manager +kmod-crypto-null\n  KCONFIG:=CONFIG_CRYPTO_AUTHENC\n  FILES:=$(LINUX_DIR)/crypto/authenc.ko\n  AUTOLOAD:=$(call AutoLoad,09,authenc)\n  $(call AddDepends/crypto)\nendef\n\n$(eval $(call KernelPackage,crypto-authenc))\n\n\ndefine KernelPackage/crypto-cbc\n  TITLE:=Cipher Block Chaining CryptoAPI module\n  DEPENDS:=+kmod-crypto-manager\n  KCONFIG:=CONFIG_CRYPTO_CBC\n  FILES:=$(LINUX_DIR)/crypto/cbc.ko\n  AUTOLOAD:=$(call AutoLoad,09,cbc)\n  $(call AddDepends/crypto)\nendef\n\n$(eval $(call KernelPackage,crypto-cbc))\n\n\ndefine KernelPackage/crypto-ccm\n TITLE:=Support for Counter with CBC MAC (CCM)\n DEPENDS:=+kmod-crypto-ctr +kmod-crypto-aead\n KCONFIG:=CONFIG_CRYPTO_CCM\n FILES:=$(LINUX_DIR)/crypto/ccm.ko\n AUTOLOAD:=$(call AutoLoad,09,ccm)\n $(call AddDepends/crypto)\nendef\n\n$(eval $(call KernelPackage,crypto-ccm))\n\n\ndefine KernelPackage/crypto-cmac\n  TITLE:=Support for Cipher-based Message Authentication Code (CMAC)\n  DEPENDS:=+kmod-crypto-hash\n  KCONFIG:=CONFIG_CRYPTO_CMAC\n  FILES:=$(LINUX_DIR)/crypto/cmac.ko\n  AUTOLOAD:=$(call AutoLoad,09,cmac)\n  $(call AddDepends/crypto)\nendef\n\n$(eval $(call KernelPackage,crypto-cmac))\n\n\ndefine KernelPackage/crypto-crc32\n  TITLE:=CRC32 CRC module\n  DEPENDS:=+kmod-crypto-hash\n  KCONFIG:=CONFIG_CRYPTO_CRC32\n  HIDDEN:=1\n  FILES:=$(LINUX_DIR)/crypto/crc32_generic.ko\n  AUTOLOAD:=$(call AutoLoad,04,crc32_generic,1)\n  $(call AddDepends/crypto)\nendef\n\n$(eval $(call KernelPackage,crypto-crc32))\n\n\ndefine KernelPackage/crypto-crc32c\n  TITLE:=CRC32c CRC module\n  DEPENDS:=+kmod-crypto-hash\n  KCONFIG:=CONFIG_CRYPTO_CRC32C\n  FILES:=$(LINUX_DIR)/crypto/crc32c_generic.ko\n  AUTOLOAD:=$(call AutoLoad,04,crc32c_generic,1)\n  $(call AddDepends/crypto)\nendef\n\n$(eval $(call KernelPackage,crypto-crc32c))\n\n\ndefine KernelPackage/crypto-ctr\n  TITLE:=Counter Mode CryptoAPI module\n  DEPENDS:=+kmod-crypto-manager +kmod-crypto-seqiv\n  KCONFIG:=CONFIG_CRYPTO_CTR\n  FILES:=$(LINUX_DIR)/crypto/ctr.ko\n  AUTOLOAD:=$(call AutoLoad,09,ctr)\n  $(call AddDepends/crypto)\nendef\n\n$(eval $(call KernelPackage,crypto-ctr))\n\n\ndefine KernelPackage/crypto-cts\n  TITLE:=Cipher Text Stealing CryptoAPI module\n  DEPENDS:=+kmod-crypto-manager\n  KCONFIG:=CONFIG_CRYPTO_CTS\n  FILES:=$(LINUX_DIR)/crypto/cts.ko\n  AUTOLOAD:=$(call AutoLoad,09,cts)\n  $(call AddDepends/crypto)\nendef\n\n$(eval $(call KernelPackage,crypto-cts))\n\n\ndefine KernelPackage/crypto-deflate\n  TITLE:=Deflate compression CryptoAPI module\n  DEPENDS:=+kmod-lib-zlib-inflate +kmod-lib-zlib-deflate +kmod-crypto-acompress\n  KCONFIG:=CONFIG_CRYPTO_DEFLATE\n  FILES:=$(LINUX_DIR)/crypto/deflate.ko\n  AUTOLOAD:=$(call AutoLoad,09,deflate)\n  $(call AddDepends/crypto)\nendef\n\n$(eval $(call KernelPackage,crypto-deflate))\n\n\ndefine KernelPackage/crypto-des\n  TITLE:=DES/3DES cipher CryptoAPI module\n  KCONFIG:=CONFIG_CRYPTO_DES\n  FILES:= \\\n\t$(LINUX_DIR)/crypto/des_generic.ko \\\n\t$(LINUX_DIR)/lib/crypto/libdes.ko\n  AUTOLOAD:=$(call AutoLoad,09,des_generic)\n  $(call AddDepends/crypto)\nendef\n\n$(eval $(call KernelPackage,crypto-des))\n\n\ndefine KernelPackage/crypto-ecb\n  TITLE:=Electronic CodeBook CryptoAPI module\n  DEPENDS:=+kmod-crypto-manager\n  KCONFIG:=CONFIG_CRYPTO_ECB\n  FILES:=$(LINUX_DIR)/crypto/ecb.ko\n  AUTOLOAD:=$(call AutoLoad,09,ecb)\n  $(call AddDepends/crypto)\nendef\n\n$(eval $(call KernelPackage,crypto-ecb))\n\n\ndefine KernelPackage/crypto-ecdh\n  TITLE:=ECDH algorithm\n  DEPENDS:=+kmod-crypto-kpp\n  KCONFIG:= CONFIG_CRYPTO_ECDH\n  FILES:= \\\n\t$(LINUX_DIR)/crypto/ecdh_generic.ko \\\n\t$(LINUX_DIR)/crypto/ecc.ko\n  AUTOLOAD:=$(call AutoLoad,10,ecdh_generic)\n  $(call AddDepends/crypto)\nendef\n\n$(eval $(call KernelPackage,crypto-ecdh))\n\n\ndefine KernelPackage/crypto-echainiv\n  TITLE:=Encrypted Chain IV Generator\n  DEPENDS:=+kmod-crypto-aead\n  KCONFIG:=CONFIG_CRYPTO_ECHAINIV\n  FILES:=$(LINUX_DIR)/crypto/echainiv.ko\n  AUTOLOAD:=$(call AutoLoad,09,echainiv)\n  $(call AddDepends/crypto)\nendef\n\n$(eval $(call KernelPackage,crypto-echainiv))\n\n\ndefine KernelPackage/crypto-fcrypt\n  TITLE:=FCRYPT cipher CryptoAPI module\n  KCONFIG:=CONFIG_CRYPTO_FCRYPT\n  FILES:=$(LINUX_DIR)/crypto/fcrypt.ko\n  AUTOLOAD:=$(call AutoLoad,09,fcrypt)\n  $(call AddDepends/crypto)\nendef\n\n$(eval $(call KernelPackage,crypto-fcrypt))\n\n\ndefine KernelPackage/crypto-gcm\n  TITLE:=GCM/GMAC CryptoAPI module\n  DEPENDS:=+kmod-crypto-ctr +kmod-crypto-ghash +kmod-crypto-null\n  KCONFIG:=CONFIG_CRYPTO_GCM\n  FILES:=$(LINUX_DIR)/crypto/gcm.ko\n  AUTOLOAD:=$(call AutoLoad,09,gcm)\n  $(call AddDepends/crypto)\nendef\n\n$(eval $(call KernelPackage,crypto-gcm))\n\n\ndefine KernelPackage/crypto-xcbc\n  TITLE:=XCBC CryptoAPI module\n  DEPENDS:=+kmod-crypto-hash +kmod-crypto-manager\n  KCONFIG:=CONFIG_CRYPTO_XCBC\n  FILES:=$(LINUX_DIR)/crypto/xcbc.ko\n  AUTOLOAD:=$(call AutoLoad,09,xcbc)\n  $(call AddDepends/crypto)\nendef\n\n$(eval $(call KernelPackage,crypto-xcbc))\n\n\ndefine KernelPackage/crypto-gf128\n  TITLE:=GF(2^128) multiplication functions CryptoAPI module\n  KCONFIG:=CONFIG_CRYPTO_GF128MUL\n  FILES:=$(LINUX_DIR)/crypto/gf128mul.ko\n  AUTOLOAD:=$(call AutoLoad,09,gf128mul)\n  $(call AddDepends/crypto)\nendef\n\n$(eval $(call KernelPackage,crypto-gf128))\n\n\ndefine KernelPackage/crypto-ghash\n  TITLE:=GHASH digest CryptoAPI module\n  DEPENDS:=+kmod-crypto-gf128 +kmod-crypto-hash\n  KCONFIG:= \\\n\tCONFIG_CRYPTO_GHASH \\\n\tCONFIG_CRYPTO_GHASH_ARM_CE\n  FILES:=$(LINUX_DIR)/crypto/ghash-generic.ko\n  AUTOLOAD:=$(call AutoLoad,09,ghash-generic)\n  $(call AddDepends/crypto)\nendef\n\ndefine KernelPackage/crypto-ghash/arm-ce\n  FILES+= $(LINUX_DIR)/arch/arm/crypto/ghash-arm-ce.ko\n  AUTOLOAD+=$(call AutoLoad,09,ghash-arm-ce)\nendef\n\nKernelPackage/crypto-ghash/imx=$(KernelPackage/crypto-ghash/arm-ce)\nKernelPackage/crypto-ghash/ipq40xx=$(KernelPackage/crypto-ghash/arm-ce)\nKernelPackage/crypto-ghash/mvebu/cortexa9=$(KernelPackage/crypto-ghash/arm-ce)\n\n$(eval $(call KernelPackage,crypto-ghash))\n\n\ndefine KernelPackage/crypto-hash\n  TITLE:=CryptoAPI hash support\n  KCONFIG:=CONFIG_CRYPTO_HASH\n  FILES:=$(LINUX_DIR)/crypto/crypto_hash.ko\n  AUTOLOAD:=$(call AutoLoad,02,crypto_hash,1)\n  $(call AddDepends/crypto)\nendef\n\n$(eval $(call KernelPackage,crypto-hash))\n\n\ndefine KernelPackage/crypto-hmac\n  TITLE:=HMAC digest CryptoAPI module\n  DEPENDS:=+kmod-crypto-hash +kmod-crypto-manager\n  KCONFIG:=CONFIG_CRYPTO_HMAC\n  FILES:=$(LINUX_DIR)/crypto/hmac.ko\n  AUTOLOAD:=$(call AutoLoad,09,hmac)\n  $(call AddDepends/crypto)\nendef\n\n$(eval $(call KernelPackage,crypto-hmac))\n\n\ndefine KernelPackage/crypto-hw-ccp\n  TITLE:=AMD Cryptographic Coprocessor\n  DEPENDS:= \\\n\t@TARGET_x86 \\\n\t+kmod-crypto-authenc \\\n\t+kmod-crypto-hash \\\n\t+kmod-crypto-manager \\\n\t+kmod-crypto-rsa \\\n\t+kmod-crypto-sha1 \\\n\t+kmod-crypto-sha256 \\\n\t+kmod-random-core\n  KCONFIG:= \\\n\tCONFIG_CRYPTO_HW=y \\\n\tCONFIG_CRYPTO_DEV_CCP=y \\\n\tCONFIG_CRYPTO_DEV_CCP_CRYPTO \\\n\tCONFIG_CRYPTO_DEV_CCP_DD \\\n\tCONFIG_CRYPTO_DEV_SP_CCP=y\n  FILES:= \\\n\t$(LINUX_DIR)/drivers/crypto/ccp/ccp.ko \\\n\t$(LINUX_DIR)/drivers/crypto/ccp/ccp-crypto.ko\n  AUTOLOAD:=$(call AutoLoad,09,ccp ccp-crypto)\n  $(call AddDepends/crypto)\nendef\n\n$(eval $(call KernelPackage,crypto-hw-ccp))\n\n\ndefine KernelPackage/crypto-hw-geode\n  TITLE:=AMD Geode hardware crypto module\n  DEPENDS:=@TARGET_x86_geode +kmod-crypto-manager\n  KCONFIG:= \\\n\tCONFIG_CRYPTO_HW=y \\\n\tCONFIG_CRYPTO_DEV_GEODE\n  FILES:=$(LINUX_DIR)/drivers/crypto/geode-aes.ko\n  AUTOLOAD:=$(call AutoLoad,09,geode-aes)\n  $(call AddDepends/crypto)\nendef\n\n$(eval $(call KernelPackage,crypto-hw-geode))\n\n\ndefine KernelPackage/crypto-hw-hifn-795x\n  TITLE:=HIFN 795x crypto accelerator\n  DEPENDS:=@PCI_SUPPORT +kmod-random-core +kmod-crypto-manager\n  KCONFIG:= \\\n\tCONFIG_CRYPTO_HW=y \\\n\tCONFIG_CRYPTO_DEV_HIFN_795X \\\n\tCONFIG_CRYPTO_DEV_HIFN_795X_RNG=y\n  FILES:=$(LINUX_DIR)/drivers/crypto/hifn_795x.ko\n  AUTOLOAD:=$(call AutoLoad,09,hifn_795x)\n  $(call AddDepends/crypto,+kmod-crypto-des)\nendef\n\n$(eval $(call KernelPackage,crypto-hw-hifn-795x))\n\n\ndefine KernelPackage/crypto-hw-padlock\n  TITLE:=VIA PadLock ACE with AES/SHA hw crypto module\n  DEPENDS:=+kmod-crypto-manager\n  KCONFIG:= \\\n\tCONFIG_CRYPTO_HW=y \\\n\tCONFIG_CRYPTO_DEV_PADLOCK \\\n\tCONFIG_CRYPTO_DEV_PADLOCK_AES \\\n\tCONFIG_CRYPTO_DEV_PADLOCK_SHA\n  FILES:= \\\n\t$(LINUX_DIR)/drivers/crypto/padlock-aes.ko \\\n\t$(LINUX_DIR)/drivers/crypto/padlock-sha.ko\n  AUTOLOAD:=$(call AutoLoad,09,padlock-aes padlock-sha)\n  $(call AddDepends/crypto)\nendef\n\n$(eval $(call KernelPackage,crypto-hw-padlock))\n\n\ndefine KernelPackage/crypto-hw-safexcel\n  TITLE:= MVEBU SafeXcel Crypto Engine module\n  DEPENDS:=@(TARGET_mvebu_cortexa53||TARGET_mvebu_cortexa72) +eip197-mini-firmware \\\n\t+kmod-crypto-authenc +kmod-crypto-md5 +kmod-crypto-hmac +kmod-crypto-sha256 +kmod-crypto-sha512\n  KCONFIG:= \\\n\tCONFIG_CRYPTO_HW=y \\\n\tCONFIG_CRYPTO_DEV_SAFEXCEL\n  FILES:=$(LINUX_DIR)/drivers/crypto/inside-secure/crypto_safexcel.ko\n  AUTOLOAD:=$(call AutoLoad,90,crypto_safexcel)\n  $(call AddDepends/crypto)\nendef\n\ndefine KernelPackage/crypto-hw-safexcel/description\nMVEBU's EIP97 and EIP197 Cryptographic Engine driver designed by\nInside Secure. This is found on Marvell Armada 37xx/7k/8k SoCs.\n\nParticular version of these IP (EIP197B and EIP197D) require firmware.\nThe mini firmware package provides limited functionality, for most operations\na full-featured firmware is required. Unfortunately the \"full\" firmware is not\nfreely available and needs signed Non-Disclosure Agreement (NDA) with Marvell.\nFor those who have signed NDA the firmware can be obtained at\nhttps://extranet.marvell.com.\nendef\n\n$(eval $(call KernelPackage,crypto-hw-safexcel))\n\n\ndefine KernelPackage/crypto-hw-talitos\n  TITLE:=Freescale integrated security engine (SEC) driver\n  DEPENDS:=@(TARGET_mpc85xx||TARGET_layerscape) +kmod-crypto-manager \\\n\t+kmod-crypto-hash +kmod-random-core +kmod-crypto-authenc +kmod-crypto-des\n  KCONFIG:= \\\n\tCONFIG_CRYPTO_HW=y \\\n\tCONFIG_CRYPTO_DEV_TALITOS \\\n\tCONFIG_CRYPTO_DEV_TALITOS1=y \\\n\tCONFIG_CRYPTO_DEV_TALITOS2=y\n  FILES:= \\\n\t$(LINUX_DIR)/drivers/crypto/talitos.ko\n  AUTOLOAD:=$(call AutoLoad,09,talitos)\n  $(call AddDepends/crypto)\nendef\n\n$(eval $(call KernelPackage,crypto-hw-talitos))\n\n\ndefine KernelPackage/crypto-kpp\n  TITLE:=Key-agreement Protocol Primitives\n  KCONFIG:=CONFIG_CRYPTO_KPP\n  FILES:=$(LINUX_DIR)/crypto/kpp.ko\n  AUTOLOAD:=$(call AutoLoad,09,kpp)\n  $(call AddDepends/crypto)\nendef\n\n$(eval $(call KernelPackage,crypto-kpp))\n\n\ndefine KernelPackage/crypto-lib-blake2s\n  TITLE:=BLAKE2s hash function library\n  KCONFIG:=CONFIG_CRYPTO_LIB_BLAKE2S\n  HIDDEN:=1\n  FILES:=$(LINUX_DIR)/lib/crypto/libblake2s.ko\n  $(call AddDepends/crypto,+PACKAGE_kmod-crypto-hash:kmod-crypto-hash)\nendef\n\ndefine KernelPackage/crypto-lib-blake2s/config\n  imply PACKAGE_kmod-crypto-hash\nendef\n\ndefine KernelPackage/crypto-lib-blake2s/x86/64\n  KCONFIG+=CONFIG_CRYPTO_BLAKE2S_X86\n  FILES+=\\\n\t  $(LINUX_DIR)/lib/crypto/libblake2s-generic.ko \\\n\t  $(LINUX_DIR)/arch/x86/crypto/blake2s-x86_64.ko\nendef\n\ndefine KernelPackage/crypto-lib-blake2s/arm\n  KCONFIG+=CONFIG_CRYPTO_BLAKE2S_ARM\n  FILES+=\\\n\t  $(LINUX_DIR)/lib/crypto/libblake2s-generic.ko@lt5.12 \\\n\t  $(LINUX_DIR)/arch/arm/crypto/blake2s-arm.ko@ge5.12\nendef\n\nifndef KernelPackage/crypto-lib-blake2s/$(CRYPTO_TARGET)\n  define KernelPackage/crypto-lib-blake2s/$(CRYPTO_TARGET)\n    KCONFIG+=CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC\n    FILES+=$(LINUX_DIR)/lib/crypto/libblake2s-generic.ko\n  endef\nendif\n\nifdef KernelPackage/crypto-lib-blake2s/$(ARCH)\n  KernelPackage/crypto-lib-blake2s/$(CRYPTO_TARGET)=\\\n\t  $(KernelPackage/crypto-lib-blake2s/$(ARCH))\nendif\n\n$(eval $(call KernelPackage,crypto-lib-blake2s))\n\n\ndefine KernelPackage/crypto-lib-chacha20\n  TITLE:=ChaCha library interface\n  KCONFIG:=CONFIG_CRYPTO_LIB_CHACHA\n  HIDDEN:=1\n  FILES:=$(LINUX_DIR)/lib/crypto/libchacha.ko\n  $(call AddDepends/crypto)\nendef\n\ndefine KernelPackage/crypto-lib-chacha20/x86_64\n  KCONFIG+=CONFIG_CRYPTO_CHACHA20_X86_64\n  FILES+=$(LINUX_DIR)/arch/x86/crypto/chacha-x86_64.ko\nendef\n\n# Note that a non-neon fallback implementation is available on arm32 when\n# NEON is not supported, hence all arm targets can utilize lib-chacha20/arm\ndefine KernelPackage/crypto-lib-chacha20/arm\n  KCONFIG+=CONFIG_CRYPTO_CHACHA20_NEON\n  FILES:=$(LINUX_DIR)/arch/arm/crypto/chacha-neon.ko\nendef\n\ndefine KernelPackage/crypto-lib-chacha20/aarch64\n  KCONFIG+=CONFIG_CRYPTO_CHACHA20_NEON\n  FILES+=$(LINUX_DIR)/arch/arm64/crypto/chacha-neon.ko\nendef\n\ndefine KernelPackage/crypto-lib-chacha20/mips32r2\n  KCONFIG+=CONFIG_CRYPTO_CHACHA_MIPS\n  FILES:=$(LINUX_DIR)/arch/mips/crypto/chacha-mips.ko\nendef\n\nifeq ($(CONFIG_CPU_MIPS32_R2),y)\n  KernelPackage/crypto-lib-chacha20/$(ARCH)=\\\n\t  $(KernelPackage/crypto-lib-chacha20/mips32r2)\nendif\n\nifdef KernelPackage/crypto-lib-chacha20/$(ARCH)\n  KernelPackage/crypto-lib-chacha20/$(CRYPTO_TARGET)=\\\n\t  $(KernelPackage/crypto-lib-chacha20/$(ARCH))\nendif\n\n$(eval $(call KernelPackage,crypto-lib-chacha20))\n\n\ndefine KernelPackage/crypto-lib-chacha20poly1305\n  TITLE:=ChaCha20-Poly1305 AEAD support (8-byte nonce library version)\n  KCONFIG:=CONFIG_CRYPTO_LIB_CHACHA20POLY1305\n  HIDDEN:=1\n  FILES:=$(LINUX_DIR)/lib/crypto/libchacha20poly1305.ko\n  $(call AddDepends/crypto, +kmod-crypto-lib-chacha20 +kmod-crypto-lib-poly1305)\nendef\n\n$(eval $(call KernelPackage,crypto-lib-chacha20poly1305))\n\n\ndefine KernelPackage/crypto-lib-curve25519\n  TITLE:=Curve25519 scalar multiplication library\n  KCONFIG:=CONFIG_CRYPTO_LIB_CURVE25519\n  HIDDEN:=1\n  FILES:= \\\n\t$(LINUX_DIR)/lib/crypto/libcurve25519.ko \\\n\t$(LINUX_DIR)/lib/crypto/libcurve25519-generic.ko\n  $(call AddDepends/crypto,+PACKAGE_kmod-crypto-kpp:kmod-crypto-kpp)\nendef\n\ndefine KernelPackage/crypto-lib-curve25519/config\n  imply PACKAGE_kmod-crypto-kpp\nendef\n\ndefine KernelPackage/crypto-lib-curve25519/x86/64\n  KCONFIG+=CONFIG_CRYPTO_CURVE25519_X86\n  FILES+=$(LINUX_DIR)/arch/x86/crypto/curve25519-x86_64.ko\nendef\n\ndefine KernelPackage/crypto-lib-curve25519/arm-neon\n  KCONFIG+=CONFIG_CRYPTO_CURVE25519_NEON\n  FILES+=$(LINUX_DIR)/arch/arm/crypto/curve25519-neon.ko\nendef\n\nifeq ($(ARCH)-$(CONFIG_KERNEL_MODE_NEON),arm-y)\n  KernelPackage/crypto-lib-curve25519/$(CRYPTO_TARGET)=\\\n\t  $(KernelPackage/crypto-lib-curve25519/arm-neon)\nendif\n\n$(eval $(call KernelPackage,crypto-lib-curve25519))\n\n\ndefine KernelPackage/crypto-lib-poly1305\n  TITLE:=Poly1305 library interface\n  KCONFIG:=CONFIG_CRYPTO_LIB_POLY1305\n  HIDDEN:=1\n  FILES:=$(LINUX_DIR)/lib/crypto/libpoly1305.ko\n  $(call AddDepends/crypto,+PACKAGE_kmod-crypto-hash:kmod-crypto-hash)\nendef\n\ndefine KernelPackage/crypto-lib-poly1305/config\n  imply PACKAGE_kmod-crypto-hash\nendef\n\ndefine KernelPackage/crypto-lib-poly1305/x86_64\n  KCONFIG+=CONFIG_CRYPTO_POLY1305_X86_64\n  FILES+=$(LINUX_DIR)/arch/x86/crypto/poly1305-x86_64.ko\nendef\n\ndefine KernelPackage/crypto-lib-poly1305/arm\n  KCONFIG+=CONFIG_CRYPTO_POLY1305_ARM\n  FILES:=$(LINUX_DIR)/arch/arm/crypto/poly1305-arm.ko\nendef\n\ndefine KernelPackage/crypto-lib-poly1305/aarch64\n  KCONFIG+=CONFIG_CRYPTO_POLY1305_NEON\n  FILES:=$(LINUX_DIR)/arch/arm64/crypto/poly1305-neon.ko\nendef\n\ndefine KernelPackage/crypto-lib-poly1305/mips\n  KCONFIG+=CONFIG_CRYPTO_POLY1305_MIPS\n  FILES:=$(LINUX_DIR)/arch/mips/crypto/poly1305-mips.ko\nendef\n\nKernelPackage/crypto-lib-poly1305/mipsel=$(KernelPackage/crypto-lib-poly1305/mips)\nKernelPackage/crypto-lib-poly1305/mips64=$(KernelPackage/crypto-lib-poly1305/mips)\nKernelPackage/crypto-lib-poly1305/mips64el=$(KernelPackage/crypto-lib-poly1305/mips)\n\nifdef KernelPackage/crypto-lib-poly1305/$(ARCH)\n  KernelPackage/crypto-lib-poly1305/$(CRYPTO_TARGET)=\\\n\t  $(KernelPackage/crypto-lib-poly1305/$(ARCH))\nendif\n\n$(eval $(call KernelPackage,crypto-lib-poly1305))\n\n\ndefine KernelPackage/crypto-manager\n  TITLE:=CryptoAPI algorithm manager\n  DEPENDS:=+kmod-crypto-aead +kmod-crypto-hash\n  KCONFIG:= \\\n\tCONFIG_CRYPTO_MANAGER \\\n\tCONFIG_CRYPTO_MANAGER2\n  FILES:=$(LINUX_DIR)/crypto/cryptomgr.ko\n  AUTOLOAD:=$(call AutoLoad,09,cryptomgr,1)\n  $(call AddDepends/crypto)\nendef\n\n$(eval $(call KernelPackage,crypto-manager))\n\n\ndefine KernelPackage/crypto-md4\n  TITLE:=MD4 digest CryptoAPI module\n  DEPENDS:=+kmod-crypto-hash\n  KCONFIG:=CONFIG_CRYPTO_MD4\n  FILES:=$(LINUX_DIR)/crypto/md4.ko\n  AUTOLOAD:=$(call AutoLoad,09,md4)\n  $(call AddDepends/crypto)\nendef\n\n$(eval $(call KernelPackage,crypto-md4))\n\n\ndefine KernelPackage/crypto-md5\n  TITLE:=MD5 digest CryptoAPI module\n  DEPENDS:=+kmod-crypto-hash\n  KCONFIG:= \\\n\tCONFIG_CRYPTO_MD5 \\\n\tCONFIG_CRYPTO_MD5_OCTEON\n  FILES:=$(LINUX_DIR)/crypto/md5.ko\n  AUTOLOAD:=$(call AutoLoad,09,md5)\n  $(call AddDepends/crypto)\nendef\n\ndefine KernelPackage/crypto-md5/octeon\n  FILES+=$(LINUX_DIR)/arch/mips/cavium-octeon/crypto/octeon-md5.ko\n  AUTOLOAD+=$(call AutoLoad,09,octeon-md5)\nendef\n\n$(eval $(call KernelPackage,crypto-md5))\n\n\ndefine KernelPackage/crypto-michael-mic\n  TITLE:=Michael MIC keyed digest CryptoAPI module\n  DEPENDS:=+kmod-crypto-hash\n  KCONFIG:=CONFIG_CRYPTO_MICHAEL_MIC\n  FILES:=$(LINUX_DIR)/crypto/michael_mic.ko\n  AUTOLOAD:=$(call AutoLoad,09,michael_mic)\n  $(call AddDepends/crypto)\nendef\n\n$(eval $(call KernelPackage,crypto-michael-mic))\n\n\ndefine KernelPackage/crypto-misc\n  TITLE:=Other CryptoAPI modules\n  DEPENDS:=+kmod-crypto-xts\n  KCONFIG:= \\\n\tCONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE=y \\\n\tCONFIG_CRYPTO_CAMELLIA_X86_64 \\\n\tCONFIG_CRYPTO_BLOWFISH_X86_64 \\\n\tCONFIG_CRYPTO_TWOFISH_X86_64 \\\n\tCONFIG_CRYPTO_TWOFISH_X86_64_3WAY \\\n\tCONFIG_CRYPTO_SERPENT_SSE2_X86_64 \\\n\tCONFIG_CRYPTO_CAMELLIA_AESNI_AVX_X86_64 \\\n\tCONFIG_CRYPTO_CAST5_AVX_X86_64 \\\n\tCONFIG_CRYPTO_CAST6_AVX_X86_64 \\\n\tCONFIG_CRYPTO_TWOFISH_AVX_X86_64 \\\n\tCONFIG_CRYPTO_SERPENT_AVX_X86_64 \\\n\tCONFIG_CRYPTO_CAMELLIA_AESNI_AVX2_X86_64 \\\n\tCONFIG_CRYPTO_SERPENT_AVX2_X86_64 \\\n\tCONFIG_CRYPTO_SERPENT_SSE2_586 \\\n\tCONFIG_CRYPTO_ANUBIS \\\n\tCONFIG_CRYPTO_BLOWFISH \\\n\tCONFIG_CRYPTO_CAMELLIA \\\n\tCONFIG_CRYPTO_CAST5 \\\n\tCONFIG_CRYPTO_CAST6 \\\n\tCONFIG_CRYPTO_FCRYPT \\\n\tCONFIG_CRYPTO_KHAZAD \\\n\tCONFIG_CRYPTO_SERPENT \\\n\tCONFIG_CRYPTO_TEA \\\n\tCONFIG_CRYPTO_TGR192@lt5.12 \\\n\tCONFIG_CRYPTO_TWOFISH \\\n\tCONFIG_CRYPTO_TWOFISH_COMMON \\\n\tCONFIG_CRYPTO_TWOFISH_586 \\\n\tCONFIG_CRYPTO_WP512\n  FILES:= \\\n\t$(LINUX_DIR)/crypto/anubis.ko \\\n\t$(LINUX_DIR)/crypto/camellia_generic.ko \\\n\t$(LINUX_DIR)/crypto/cast_common.ko \\\n\t$(LINUX_DIR)/crypto/cast5_generic.ko \\\n\t$(LINUX_DIR)/crypto/cast6_generic.ko \\\n\t$(LINUX_DIR)/crypto/khazad.ko \\\n\t$(LINUX_DIR)/crypto/tea.ko \\\n\t$(LINUX_DIR)/crypto/tgr192.ko@lt5.12 \\\n\t$(LINUX_DIR)/crypto/twofish_common.ko \\\n\t$(LINUX_DIR)/crypto/wp512.ko \\\n\t$(LINUX_DIR)/crypto/twofish_generic.ko \\\n\t$(LINUX_DIR)/crypto/blowfish_common.ko \\\n\t$(LINUX_DIR)/crypto/blowfish_generic.ko \\\n\t$(LINUX_DIR)/crypto/serpent_generic.ko\n  AUTOLOAD:=$(call AutoLoad,10,anubis camellia_generic cast_common \\\n\tcast5_generic cast6_generic khazad tea tgr192@lt5.12 twofish_common \\\n\twp512 blowfish_common serpent_generic)\n  ifndef CONFIG_TARGET_x86\n\tAUTOLOAD+= $(call AutoLoad,10,twofish_generic blowfish_generic)\n  endif\n  $(call AddDepends/crypto)\nendef\n\nifndef CONFIG_TARGET_x86_64\n  define KernelPackage/crypto-misc/x86\n    FILES+= \\\n\t$(LINUX_DIR)/arch/x86/crypto/twofish-i586.ko \\\n\t$(LINUX_DIR)/arch/x86/crypto/serpent-sse2-i586.ko \\\n\t$(LINUX_DIR)/arch/x86/crypto/glue_helper.ko \\\n\t$(LINUX_DIR)/crypto/cryptd.ko \\\n\t$(LINUX_DIR)/crypto/crypto_simd.ko\n    AUTOLOAD+= $(call AutoLoad,10,cryptd glue_helper \\\n\tserpent-sse2-i586 twofish-i586 blowfish_generic)\n  endef\nendif\n\ndefine KernelPackage/crypto-misc/x86/64\n  FILES+= \\\n\t$(LINUX_DIR)/arch/x86/crypto/camellia-x86_64.ko \\\n\t$(LINUX_DIR)/arch/x86/crypto/blowfish-x86_64.ko \\\n\t$(LINUX_DIR)/arch/x86/crypto/twofish-x86_64.ko \\\n\t$(LINUX_DIR)/arch/x86/crypto/twofish-x86_64-3way.ko \\\n\t$(LINUX_DIR)/arch/x86/crypto/serpent-sse2-x86_64.ko \\\n\t$(LINUX_DIR)/arch/x86/crypto/camellia-aesni-avx-x86_64.ko \\\n\t$(LINUX_DIR)/arch/x86/crypto/cast5-avx-x86_64.ko \\\n\t$(LINUX_DIR)/arch/x86/crypto/cast6-avx-x86_64.ko \\\n\t$(LINUX_DIR)/arch/x86/crypto/twofish-avx-x86_64.ko \\\n\t$(LINUX_DIR)/arch/x86/crypto/serpent-avx-x86_64.ko \\\n\t$(LINUX_DIR)/arch/x86/crypto/camellia-aesni-avx2.ko \\\n\t$(LINUX_DIR)/arch/x86/crypto/serpent-avx2.ko\n  AUTOLOAD+= $(call AutoLoad,10,camellia-x86_64 \\\n\tcamellia-aesni-avx-x86_64 camellia-aesni-avx2 cast5-avx-x86_64 \\\n\tcast6-avx-x86_64 twofish-x86_64 twofish-x86_64-3way \\\n\ttwofish-avx-x86_64 blowfish-x86_64 serpent-avx-x86_64 serpent-avx2)\nendef\n\n$(eval $(call KernelPackage,crypto-misc))\n\n\ndefine KernelPackage/crypto-null\n  TITLE:=Null CryptoAPI module\n  KCONFIG:=CONFIG_CRYPTO_NULL\n  FILES:=$(LINUX_DIR)/crypto/crypto_null.ko\n  AUTOLOAD:=$(call AutoLoad,09,crypto_null)\n  $(call AddDepends/crypto, +kmod-crypto-hash)\nendef\n\n$(eval $(call KernelPackage,crypto-null))\n\n\ndefine KernelPackage/crypto-pcbc\n  TITLE:=Propagating Cipher Block Chaining CryptoAPI module\n  DEPENDS:=+kmod-crypto-manager\n  KCONFIG:=CONFIG_CRYPTO_PCBC\n  FILES:=$(LINUX_DIR)/crypto/pcbc.ko\n  AUTOLOAD:=$(call AutoLoad,09,pcbc)\n  $(call AddDepends/crypto)\nendef\n\n$(eval $(call KernelPackage,crypto-pcbc))\n\n\ndefine KernelPackage/crypto-rsa\n  TITLE:=RSA algorithm\n  DEPENDS:=+kmod-crypto-manager +kmod-asn1-decoder\n  KCONFIG:= CONFIG_CRYPTO_RSA\n  HIDDEN:=1\n  FILES:= \\\n\t$(LINUX_DIR)/lib/mpi/mpi.ko \\\n\t$(LINUX_DIR)/crypto/akcipher.ko \\\n\t$(LINUX_DIR)/crypto/rsa_generic.ko\n  AUTOLOAD:=$(call AutoLoad,10,rsa_generic)\n  $(call AddDepends/crypto)\nendef\n\n$(eval $(call KernelPackage,crypto-rsa))\n\n\ndefine KernelPackage/crypto-rmd160\n  TITLE:=RIPEMD160 digest CryptoAPI module\n  DEPENDS:=+kmod-crypto-hash\n  KCONFIG:=CONFIG_CRYPTO_RMD160\n  FILES:=$(LINUX_DIR)/crypto/rmd160.ko\n  AUTOLOAD:=$(call AutoLoad,09,rmd160)\n  $(call AddDepends/crypto)\nendef\n\n$(eval $(call KernelPackage,crypto-rmd160))\n\n\ndefine KernelPackage/crypto-rng\n  TITLE:=CryptoAPI random number generation\n  DEPENDS:=+kmod-crypto-hash +kmod-crypto-hmac +kmod-crypto-sha256\n  KCONFIG:= \\\n\tCONFIG_CRYPTO_DRBG \\\n\tCONFIG_CRYPTO_DRBG_HMAC=y \\\n\tCONFIG_CRYPTO_DRBG_HASH=n \\\n\tCONFIG_CRYPTO_DRBG_MENU \\\n\tCONFIG_CRYPTO_JITTERENTROPY \\\n\tCONFIG_CRYPTO_RNG2\n  FILES:= \\\n\t$(LINUX_DIR)/crypto/drbg.ko \\\n\t$(LINUX_DIR)/crypto/jitterentropy_rng.ko \\\n\t$(LINUX_DIR)/crypto/rng.ko\n  AUTOLOAD:=$(call AutoLoad,09,drbg jitterentropy_rng rng)\n  $(call AddDepends/crypto)\nendef\n\n$(eval $(call KernelPackage,crypto-rng))\n\n\ndefine KernelPackage/crypto-seqiv\n  TITLE:=CryptoAPI Sequence Number IV Generator\n  DEPENDS:=+kmod-crypto-aead +kmod-crypto-rng\n  KCONFIG:=CONFIG_CRYPTO_SEQIV\n  FILES:=$(LINUX_DIR)/crypto/seqiv.ko\n  AUTOLOAD:=$(call AutoLoad,09,seqiv)\n  $(call AddDepends/crypto)\nendef\n\n$(eval $(call KernelPackage,crypto-seqiv))\n\n\ndefine KernelPackage/crypto-sha1\n  TITLE:=SHA1 digest CryptoAPI module\n  DEPENDS:=+kmod-crypto-hash\n  KCONFIG:= \\\n\tCONFIG_CRYPTO_SHA1 \\\n\tCONFIG_CRYPTO_SHA1_ARM \\\n\tCONFIG_CRYPTO_SHA1_ARM_NEON \\\n\tCONFIG_CRYPTO_SHA1_OCTEON \\\n\tCONFIG_CRYPTO_SHA1_SSSE3\n  FILES:=$(LINUX_DIR)/crypto/sha1_generic.ko\n  AUTOLOAD:=$(call AutoLoad,09,sha1_generic)\n  $(call AddDepends/crypto)\nendef\n\ndefine KernelPackage/crypto-sha1/arm\n  FILES+=$(LINUX_DIR)/arch/arm/crypto/sha1-arm.ko\n  AUTOLOAD+=$(call AutoLoad,09,sha1-arm)\nendef\n\ndefine KernelPackage/crypto-sha1/arm-neon\n  $(call KernelPackage/crypto-sha1/arm)\n  FILES+=$(LINUX_DIR)/arch/arm/crypto/sha1-arm-neon.ko\n  AUTOLOAD+=$(call AutoLoad,09,sha1-arm-neon)\nendef\n\nKernelPackage/crypto-sha1/imx=$(KernelPackage/crypto-sha1/arm-neon)\nKernelPackage/crypto-sha1/ipq40xx=$(KernelPackage/crypto-sha1/arm-neon)\nKernelPackage/crypto-sha1/mvebu/cortexa9=$(KernelPackage/crypto-sha1/arm-neon)\n\ndefine KernelPackage/crypto-sha1/octeon\n  FILES+=$(LINUX_DIR)/arch/mips/cavium-octeon/crypto/octeon-sha1.ko\n  AUTOLOAD+=$(call AutoLoad,09,octeon-sha1)\nendef\n\nKernelPackage/crypto-sha1/tegra=$(KernelPakcage/crypto-sha1/arm)\n\ndefine KernelPackage/crypto-sha1/x86/64\n  FILES+=$(LINUX_DIR)/arch/x86/crypto/sha1-ssse3.ko\n  AUTOLOAD+=$(call AutoLoad,09,sha1-ssse3)\nendef\n\n$(eval $(call KernelPackage,crypto-sha1))\n\n\ndefine KernelPackage/crypto-sha256\n  TITLE:=SHA224 SHA256 digest CryptoAPI module\n  DEPENDS:=+kmod-crypto-hash\n  KCONFIG:= \\\n\tCONFIG_CRYPTO_SHA256 \\\n\tCONFIG_CRYPTO_SHA256_OCTEON \\\n\tCONFIG_CRYPTO_SHA256_SSSE3\n  FILES:= \\\n\t$(LINUX_DIR)/crypto/sha256_generic.ko \\\n\t$(LINUX_DIR)/lib/crypto/libsha256.ko\n  AUTOLOAD:=$(call AutoLoad,09,sha256_generic)\n  $(call AddDepends/crypto)\nendef\n\ndefine KernelPackage/crypto-sha256/octeon\n  FILES+=$(LINUX_DIR)/arch/mips/cavium-octeon/crypto/octeon-sha256.ko\n  AUTOLOAD+=$(call AutoLoad,09,octeon-sha256)\nendef\n\ndefine KernelPackage/crypto-sha256/x86/64\n  FILES+=$(LINUX_DIR)/arch/x86/crypto/sha256-ssse3.ko\n  AUTOLOAD+=$(call AutoLoad,09,sha256-ssse3)\nendef\n\n$(eval $(call KernelPackage,crypto-sha256))\n\n\ndefine KernelPackage/crypto-sha512\n  TITLE:=SHA512 digest CryptoAPI module\n  DEPENDS:=+kmod-crypto-hash\n  KCONFIG:= \\\n\tCONFIG_CRYPTO_SHA512 \\\n\tCONFIG_CRYPTO_SHA512_ARM \\\n\tCONFIG_CRYPTO_SHA512_OCTEON \\\n\tCONFIG_CRYPTO_SHA512_SSSE3\n  FILES:=$(LINUX_DIR)/crypto/sha512_generic.ko\n  AUTOLOAD:=$(call AutoLoad,09,sha512_generic)\n  $(call AddDepends/crypto)\nendef\n\ndefine KernelPackage/crypto-sha512/arm\n  FILES+=$(LINUX_DIR)/arch/arm/crypto/sha512-arm.ko\n  AUTOLOAD+=$(call AutoLoad,09,sha512-arm)\nendef\n\nKernelPackage/crypto-sha512/imx=$(KernelPackage/crypto-sha512/arm)\nKernelPackage/crypto-sha512/ipq40xx=$(KernelPackage/crypto-sha512/arm)\nKernelPackage/crypto-sha512/mvebu/cortexa9=$(KernelPackage/crypto-sha512/arm)\n\ndefine KernelPackage/crypto-sha512/octeon\n  FILES+=$(LINUX_DIR)/arch/mips/cavium-octeon/crypto/octeon-sha512.ko\n  AUTOLOAD+=$(call AutoLoad,09,octeon-sha512)\nendef\n\nKernelPackage/crypto-sha512/tegra=$(KernelPackage/crypto-sha512/arm)\n\ndefine KernelPackage/crypto-sha512/x86/64\n  FILES+=$(LINUX_DIR)/arch/x86/crypto/sha512-ssse3.ko\n  AUTOLOAD+=$(call AutoLoad,09,sha512-ssse3)\nendef\n\n$(eval $(call KernelPackage,crypto-sha512))\n\n\ndefine KernelPackage/crypto-test\n  TITLE:=Test CryptoAPI module\n  KCONFIG:=CONFIG_CRYPTO_TEST\n  FILES:=$(LINUX_DIR)/crypto/tcrypt.ko\n  $(call AddDepends/crypto,+kmod-crypto-manager)\nendef\n\n$(eval $(call KernelPackage,crypto-test))\n\n\ndefine KernelPackage/crypto-user\n  TITLE:=CryptoAPI userspace interface\n  DEPENDS:=+kmod-crypto-hash +kmod-crypto-manager\n  KCONFIG:= \\\n\tCONFIG_CRYPTO_USER \\\n\tCONFIG_CRYPTO_USER_API \\\n\tCONFIG_CRYPTO_USER_API_AEAD \\\n\tCONFIG_CRYPTO_USER_API_HASH \\\n\tCONFIG_CRYPTO_USER_API_RNG \\\n\tCONFIG_CRYPTO_USER_API_SKCIPHER\n  FILES:= \\\n\t$(LINUX_DIR)/crypto/af_alg.ko \\\n\t$(LINUX_DIR)/crypto/algif_aead.ko \\\n\t$(LINUX_DIR)/crypto/algif_hash.ko \\\n\t$(LINUX_DIR)/crypto/algif_rng.ko \\\n\t$(LINUX_DIR)/crypto/algif_skcipher.ko \\\n\t$(LINUX_DIR)/crypto/crypto_user.ko\n  AUTOLOAD:=$(call AutoLoad,09,af_alg algif_aead algif_hash algif_rng algif_skcipher crypto_user)\n  $(call AddDepends/crypto)\nendef\n\n$(eval $(call KernelPackage,crypto-user))\n\n\ndefine KernelPackage/crypto-xts\n  TITLE:=XTS cipher CryptoAPI module\n  DEPENDS:=+kmod-crypto-gf128 +kmod-crypto-manager\n  KCONFIG:=CONFIG_CRYPTO_XTS\n  FILES:=$(LINUX_DIR)/crypto/xts.ko\n  AUTOLOAD:=$(call AutoLoad,09,xts)\n  $(call AddDepends/crypto)\nendef\n\n$(eval $(call KernelPackage,crypto-xts))\n\n"
  },
  {
    "path": "package/kernel/linux/modules/firewire.mk",
    "content": "#\n# Copyright (C) 2008-2011 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\nFIREWIRE_MENU:=FireWire support\n\ndefine KernelPackage/firewire\n  SUBMENU:=$(FIREWIRE_MENU)\n  TITLE:=Support for FireWire (new stack)\n  DEPENDS:=@PCI_SUPPORT +kmod-lib-crc-itu-t\n  KCONFIG:=CONFIG_FIREWIRE\n  FILES:=$(LINUX_DIR)/drivers/firewire/firewire-core.ko\nendef\n\ndefine KernelPackage/firewire/description\n Kernel support for FireWire (new stack)\nendef\n\n$(eval $(call KernelPackage,firewire))\n\n\ndefine KernelPackage/firewire-net\n  SUBMENU:=$(FIREWIRE_MENU)\n  TITLE:=Support for IP networking over FireWire\n  DEPENDS:=kmod-firewire\n  KCONFIG:=CONFIG_FIREWIRE_NET\n  FILES:=$(LINUX_DIR)/drivers/firewire/firewire-net.ko\n  AUTOLOAD:=$(call AutoProbe,firewire-net)\nendef\n\ndefine KernelPackage/firewire-net/description\n Kernel support for IPv4 over FireWire\nendef\n\n$(eval $(call KernelPackage,firewire-net))\n\n\ndefine KernelPackage/firewire-ohci\n  SUBMENU:=$(FIREWIRE_MENU)\n  TITLE:=Support for OHCI-1394 controllers\n  DEPENDS:=kmod-firewire\n  KCONFIG:= \\\n\tCONFIG_FIREWIRE_OHCI \\\n\tCONFIG_FIREWIRE_OHCI_DEBUG=n \\\n\tCONFIG_FIREWIRE_OHCI_REMOTE_DMA=n\n  FILES:=$(LINUX_DIR)/drivers/firewire/firewire-ohci.ko\n  AUTOLOAD:=$(call AutoProbe,firewire-ohci)\nendef\n\n\ndefine KernelPackage/firewire-ohci/description\n Kernel support for FireWire OHCI-1394 controllers\nendef\n\n$(eval $(call KernelPackage,firewire-ohci))\n\n\ndefine KernelPackage/firewire-sbp2\n  SUBMENU:=$(FIREWIRE_MENU)\n  TITLE:=Support for SBP-2 devices over FireWire\n  DEPENDS:=kmod-firewire +kmod-scsi-core\n  KCONFIG:=CONFIG_FIREWIRE_SBP2\n  FILES:=$(LINUX_DIR)/drivers/firewire/firewire-sbp2.ko\n  AUTOLOAD:=$(call AutoProbe,firewire-sbp2)\nendef\n\ndefine KernelPackage/firewire-sbp2/description\n Kernel support for SBP-2 devices over FireWire\nendef\n\n$(eval $(call KernelPackage,firewire-sbp2))\n\n\n"
  },
  {
    "path": "package/kernel/linux/modules/fs.mk",
    "content": "#\n# Copyright (C) 2006-2011 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\nFS_MENU:=Filesystems\n\ndefine KernelPackage/fs-9p\n  SUBMENU:=$(FS_MENU)\n  TITLE:=Plan 9 Resource Sharing Support\n  DEPENDS:=+kmod-9pnet\n  KCONFIG:=\\\n\tCONFIG_9P_FS \\\n\tCONFIG_9P_FS_POSIX_ACL=n \\\n\tCONFIG_9P_FS_SECURITY=n \\\n\tCONFIG_9P_FSCACHE=n\n  FILES:=$(LINUX_DIR)/fs/9p/9p.ko\n  AUTOLOAD:=$(call AutoLoad,30,9p)\nendef\n\ndefine KernelPackage/fs-9p/description\n  Kernel module for Plan 9 Resource Sharing Support support\nendef\n\n$(eval $(call KernelPackage,fs-9p))\n\n\ndefine KernelPackage/fs-afs\n  SUBMENU:=$(FS_MENU)\n  TITLE:=Andrew FileSystem client\n  DEFAULT:=n\n  DEPENDS:=+kmod-rxrpc +kmod-dnsresolver +kmod-fs-fscache\n  KCONFIG:=\\\n\tCONFIG_AFS_FS=m \\\n\tCONFIG_AFS_DEBUG=n \\\n\tCONFIG_AFS_FSCACHE=y\n  FILES:=$(LINUX_DIR)/fs/afs/kafs.ko\n  AUTOLOAD:=$(call AutoLoad,30,kafs)\nendef\n\ndefine KernelPackage/fs-afs/description\n  Kernel module for Andrew FileSystem client support\nendef\n\n$(eval $(call KernelPackage,fs-afs))\n\ndefine KernelPackage/fs-autofs4\n  SUBMENU:=$(FS_MENU)\n  TITLE:=AUTOFS4 filesystem support\n  KCONFIG:= \\\n\tCONFIG_AUTOFS4_FS \\\n\tCONFIG_AUTOFS_FS\n  FILES:= \\\n\t$(LINUX_DIR)/fs/autofs/autofs4.ko\n  AUTOLOAD:=$(call AutoLoad,30,autofs4)\nendef\n\ndefine KernelPackage/fs-autofs4/description\n Kernel module for AutoFS4 support\nendef\n\n$(eval $(call KernelPackage,fs-autofs4))\n\n\ndefine KernelPackage/fs-btrfs\n  SUBMENU:=$(FS_MENU)\n  TITLE:=BTRFS filesystem support\n  DEPENDS:=+kmod-lib-crc32c +kmod-lib-lzo +kmod-lib-zlib-inflate +kmod-lib-zlib-deflate +kmod-lib-raid6 +kmod-lib-xor +kmod-lib-zstd\n  KCONFIG:=\\\n\tCONFIG_BTRFS_FS \\\n\tCONFIG_BTRFS_FS_CHECK_INTEGRITY=n\n  FILES:=\\\n\t$(LINUX_DIR)/fs/btrfs/btrfs.ko\n  AUTOLOAD:=$(call AutoLoad,30,btrfs,1)\nendef\n\ndefine KernelPackage/fs-btrfs/description\n Kernel module for BTRFS support\nendef\n\n$(eval $(call KernelPackage,fs-btrfs))\n\n\ndefine KernelPackage/fs-cifs\n  SUBMENU:=$(FS_MENU)\n  TITLE:=CIFS support\n  KCONFIG:= \\\n\tCONFIG_SMBFS_COMMON@ge5.15 \\\n\tCONFIG_CIFS \\\n\tCONFIG_CIFS_DFS_UPCALL=n \\\n\tCONFIG_CIFS_UPCALL=n\n  FILES:= \\\n\t$(LINUX_DIR)/fs/smbfs_common/cifs_arc4.ko@ge5.15 \\\n\t$(LINUX_DIR)/fs/smbfs_common/cifs_md4.ko@ge5.15 \\\n\t$(LINUX_DIR)/fs/cifs/cifs.ko\n  AUTOLOAD:=$(call AutoLoad,30,cifs)\n  $(call AddDepends/nls)\n  DEPENDS+= \\\n    +(LINUX_5_4||LINUX_5_10):kmod-crypto-md4\\\n    +kmod-crypto-md5 \\\n    +kmod-crypto-sha256 \\\n    +kmod-crypto-sha512 \\\n    +kmod-crypto-cmac \\\n    +kmod-crypto-hmac \\\n    +(LINUX_5_4||LINUX_5_10):kmod-crypto-arc4 \\\n    +kmod-crypto-aead \\\n    +kmod-crypto-ccm \\\n    +kmod-crypto-ecb \\\n    +kmod-crypto-des \\\n    +(LINUX_5_15):kmod-asn1-decoder \\\n    +(LINUX_5_15):kmod-oid-registry \\\n    +(LINUX_5_15):kmod-dnsresolver\nendef\n\ndefine KernelPackage/fs-cifs/description\n Kernel module for CIFS support\nendef\n\n$(eval $(call KernelPackage,fs-cifs))\n\n\ndefine KernelPackage/fs-configfs\n  SUBMENU:=$(FS_MENU)\n  TITLE:=Configuration filesystem support\n  KCONFIG:= \\\n\tCONFIG_CONFIGFS_FS\n  FILES:=$(LINUX_DIR)/fs/configfs/configfs.ko\n  AUTOLOAD:=$(call AutoLoad,30,configfs)\nendef\n\ndefine KernelPackage/fs-configfs/description\n Kernel module for configfs support\nendef\n\n$(eval $(call KernelPackage,fs-configfs))\n\n\ndefine KernelPackage/fs-cramfs\n  SUBMENU:=$(FS_MENU)\n  TITLE:=Compressed RAM/ROM filesystem support\n  DEPENDS:=+kmod-lib-zlib-inflate\n  KCONFIG:= \\\n\tCONFIG_CRAMFS\n  FILES:=$(LINUX_DIR)/fs/cramfs/cramfs.ko\n  AUTOLOAD:=$(call AutoLoad,30,cramfs)\nendef\n\ndefine KernelPackage/fs-cramfs/description\n Kernel module for cramfs support\nendef\n\n$(eval $(call KernelPackage,fs-cramfs))\n\n\ndefine KernelPackage/fs-efivarfs\n  SUBMENU:=$(FS_MENU)\n  TITLE:=efivar filesystem support\n  KCONFIG:=CONFIG_EFIVAR_FS\n  FILES:=$(LINUX_DIR)/fs/efivarfs/efivarfs.ko\n  DEPENDS:=@(x86_64||x86)\n  AUTOLOAD:=$(call Autoload,90,efivarfs)\nendef\n\ndefine KernelPackage/fs-efivarfs/description\n  Kernel module to support efivarfs file system mountpoint.\nendef\n\n$(eval $(call KernelPackage,fs-efivarfs))\n\n\ndefine KernelPackage/fs-exfat\n  SUBMENU:=$(FS_MENU)\n  TITLE:=exFAT filesystem support\n  KCONFIG:= \\\n\tCONFIG_EXFAT_FS \\\n\tCONFIG_EXFAT_DEFAULT_IOCHARSET=\"utf8\"\n  FILES:= \\\n\t$(LINUX_DIR)/drivers/staging/exfat/exfat.ko@lt5.7 \\\n\t$(LINUX_DIR)/fs/exfat/exfat.ko@ge5.7\n  AUTOLOAD:=$(call AutoLoad,30,exfat,1)\n  DEPENDS:=+kmod-nls-base\nendef\n\ndefine KernelPackage/fs-exfat/description\n Kernel module for exFAT filesystem support\nendef\n\n$(eval $(call KernelPackage,fs-exfat))\n\n\ndefine KernelPackage/fs-exportfs\n  SUBMENU:=$(FS_MENU)\n  TITLE:=exportfs kernel server support\n  KCONFIG:=CONFIG_EXPORTFS\n  FILES=$(LINUX_DIR)/fs/exportfs/exportfs.ko\n  AUTOLOAD:=$(call AutoLoad,20,exportfs,1)\nendef\n\ndefine KernelPackage/fs-exportfs/description\n Kernel module for exportfs. Needed for some other modules.\nendef\n\n$(eval $(call KernelPackage,fs-exportfs))\n\n\ndefine KernelPackage/fs-ext4\n  SUBMENU:=$(FS_MENU)\n  TITLE:=EXT4 filesystem support\n  DEPENDS := \\\n    +kmod-lib-crc16 \\\n    +kmod-crypto-hash \\\n    +kmod-crypto-crc32c\n  KCONFIG:= \\\n\tCONFIG_EXT4_FS \\\n\tCONFIG_EXT4_ENCRYPTION=n \\\n\tCONFIG_JBD2\n  FILES:= \\\n\t$(LINUX_DIR)/fs/ext4/ext4.ko \\\n\t$(LINUX_DIR)/fs/jbd2/jbd2.ko \\\n\t$(LINUX_DIR)/fs/mbcache.ko\n  AUTOLOAD:=$(call AutoLoad,30,mbcache jbd2 ext4,1)\nendef\n\ndefine KernelPackage/fs-ext4/description\n Kernel module for EXT4 filesystem support\nendef\n\n$(eval $(call KernelPackage,fs-ext4))\n\n\ndefine KernelPackage/fs-f2fs\n  SUBMENU:=$(FS_MENU)\n  TITLE:=F2FS filesystem support\n  DEPENDS:= +kmod-crypto-hash +kmod-crypto-crc32 +kmod-nls-base\n  KCONFIG:=CONFIG_F2FS_FS\n  FILES:=$(LINUX_DIR)/fs/f2fs/f2fs.ko\n  AUTOLOAD:=$(call AutoLoad,30,f2fs,1)\nendef\n\ndefine KernelPackage/fs-f2fs/description\n Kernel module for F2FS filesystem support\nendef\n\n$(eval $(call KernelPackage,fs-f2fs))\n\n\ndefine KernelPackage/fs-netfs\n  SUBMENU:=$(FS_MENU)\n  TITLE:=Network Filesystems support\n  DEPENDS:=@LINUX_5_15\n  KCONFIG:= CONFIG_NETFS_SUPPORT\n  FILES:=$(LINUX_DIR)/fs/netfs/netfs.ko\n  AUTOLOAD:=$(call AutoLoad,28,netfs)\nendef\n\n$(eval $(call KernelPackage,fs-netfs))\n\ndefine KernelPackage/fs-fscache\n  SUBMENU:=$(FS_MENU)\n  TITLE:=General filesystem local cache manager\n  DEPENDS:=+kmod-fs-netfs\n  KCONFIG:=\\\n\tCONFIG_FSCACHE=m \\\n\tCONFIG_FSCACHE_STATS=y \\\n\tCONFIG_FSCACHE_HISTOGRAM=n \\\n\tCONFIG_FSCACHE_DEBUG=n \\\n\tCONFIG_FSCACHE_OBJECT_LIST=n \\\n\tCONFIG_CACHEFILES=y \\\n\tCONFIG_CACHEFILES_DEBUG=n \\\n\tCONFIG_CACHEFILES_HISTOGRAM=n\n  FILES:=$(LINUX_DIR)/fs/fscache/fscache.ko\n  AUTOLOAD:=$(call AutoLoad,29,fscache)\nendef\n\n$(eval $(call KernelPackage,fs-fscache))\n\n\ndefine KernelPackage/fs-hfs\n  SUBMENU:=$(FS_MENU)\n  TITLE:=HFS filesystem support\n  DEPENDS:=+kmod-cdrom\n  KCONFIG:=CONFIG_HFS_FS\n  FILES:=$(LINUX_DIR)/fs/hfs/hfs.ko\n  AUTOLOAD:=$(call AutoLoad,30,hfs)\n  $(call AddDepends/nls)\nendef\n\ndefine KernelPackage/fs-hfs/description\n Kernel module for HFS filesystem support\nendef\n\n$(eval $(call KernelPackage,fs-hfs))\n\n\ndefine KernelPackage/fs-hfsplus\n  SUBMENU:=$(FS_MENU)\n  TITLE:=HFS+ filesystem support\n  DEPENDS:=+kmod-cdrom\n  KCONFIG:=CONFIG_HFSPLUS_FS\n  FILES:=$(LINUX_DIR)/fs/hfsplus/hfsplus.ko\n  AUTOLOAD:=$(call AutoLoad,30,hfsplus)\n  $(call AddDepends/nls,utf8)\nendef\n\ndefine KernelPackage/fs-hfsplus/description\n Kernel module for HFS+ filesystem support\nendef\n\n$(eval $(call KernelPackage,fs-hfsplus))\n\n\ndefine KernelPackage/fs-isofs\n  SUBMENU:=$(FS_MENU)\n  TITLE:=ISO9660 filesystem support\n  DEPENDS:=+kmod-lib-zlib-inflate +kmod-cdrom\n  KCONFIG:=CONFIG_ISO9660_FS CONFIG_JOLIET=y CONFIG_ZISOFS=n\n  FILES:=$(LINUX_DIR)/fs/isofs/isofs.ko\n  AUTOLOAD:=$(call AutoLoad,30,isofs)\n  $(call AddDepends/nls)\nendef\n\ndefine KernelPackage/fs-isofs/description\n Kernel module for ISO9660 filesystem support\nendef\n\n$(eval $(call KernelPackage,fs-isofs))\n\n\ndefine KernelPackage/fs-jfs\n  SUBMENU:=$(FS_MENU)\n  TITLE:=JFS filesystem support\n  KCONFIG:=CONFIG_JFS_FS\n  FILES:=$(LINUX_DIR)/fs/jfs/jfs.ko\n  AUTOLOAD:=$(call AutoLoad,30,jfs,1)\n  $(call AddDepends/nls)\nendef\n\ndefine KernelPackage/fs-jfs/description\n Kernel module for JFS support\nendef\n\n$(eval $(call KernelPackage,fs-jfs))\n\ndefine KernelPackage/fs-minix\n  SUBMENU:=$(FS_MENU)\n  TITLE:=Minix filesystem support\n  KCONFIG:=CONFIG_MINIX_FS\n  FILES:=$(LINUX_DIR)/fs/minix/minix.ko\n  AUTOLOAD:=$(call AutoLoad,30,minix)\nendef\n\ndefine KernelPackage/fs-minix/description\n Kernel module for Minix filesystem support\nendef\n\n$(eval $(call KernelPackage,fs-minix))\n\n\ndefine KernelPackage/fs-msdos\n  SUBMENU:=$(FS_MENU)\n  TITLE:=MSDOS filesystem support\n  DEPENDS:=+kmod-fs-vfat\n  KCONFIG:=CONFIG_MSDOS_FS\n  FILES:=$(LINUX_DIR)/fs/fat/msdos.ko\n  AUTOLOAD:=$(call AutoLoad,40,msdos)\n  $(call AddDepends/nls)\nendef\n\ndefine KernelPackage/fs-msdos/description\n Kernel module for MSDOS filesystem support\nendef\n\n$(eval $(call KernelPackage,fs-msdos))\n\n\ndefine KernelPackage/fs-nfs\n  SUBMENU:=$(FS_MENU)\n  TITLE:=NFS filesystem client support\n  DEPENDS:=+kmod-fs-nfs-common +kmod-dnsresolver\n  KCONFIG:= \\\n\tCONFIG_NFS_FS \\\n\tCONFIG_NFS_USE_LEGACY_DNS=n \\\n\tCONFIG_NFS_USE_NEW_IDMAPPER=n\n  FILES:= \\\n\t$(LINUX_DIR)/fs/nfs/nfs.ko\n  AUTOLOAD:=$(call AutoLoad,40,nfs)\nendef\n\ndefine KernelPackage/fs-nfs/description\n Kernel module for NFS client support\nendef\n\n$(eval $(call KernelPackage,fs-nfs))\n\n\ndefine KernelPackage/fs-nfs-common\n  SUBMENU:=$(FS_MENU)\n  TITLE:=Common NFS filesystem modules\n  DEPENDS:=+kmod-oid-registry\n  KCONFIG:= \\\n\tCONFIG_LOCKD \\\n\tCONFIG_SUNRPC \\\n\tCONFIG_GRACE_PERIOD \\\n\tCONFIG_NFS_V4=y \\\n\tCONFIG_NFS_V4_1=y \\\n\tCONFIG_NFS_V4_1_IMPLEMENTATION_ID_DOMAIN=\"kernel.org\" \\\n\tCONFIG_NFS_V4_1_MIGRATION=n \\\n\tCONFIG_NFS_V4_2=y \\\n\tCONFIG_NFS_V4_2_READ_PLUS=n\n  FILES:= \\\n\t$(LINUX_DIR)/fs/lockd/lockd.ko \\\n\t$(LINUX_DIR)/net/sunrpc/sunrpc.ko \\\n\t$(LINUX_DIR)/fs/nfs_common/grace.ko \\\n\t$(LINUX_DIR)/fs/nfs_common/nfs_ssc.ko@ge5.10\n  AUTOLOAD:=$(call AutoLoad,30,grace sunrpc lockd)\nendef\n\n$(eval $(call KernelPackage,fs-nfs-common))\n\n\ndefine KernelPackage/fs-nfs-common-rpcsec\n  SUBMENU:=$(FS_MENU)\n  TITLE:=NFS Secure RPC\n  DEPENDS:= \\\n\t+kmod-fs-nfs-common \\\n\t+kmod-crypto-des \\\n\t+kmod-crypto-cbc \\\n\t+kmod-crypto-cts \\\n\t+kmod-crypto-md5 \\\n\t+kmod-crypto-sha1 \\\n\t+kmod-crypto-hmac \\\n\t+kmod-crypto-ecb \\\n\t+kmod-crypto-arc4\n  KCONFIG:= \\\n\tCONFIG_SUNRPC_GSS \\\n\tCONFIG_RPCSEC_GSS_KRB5\n  FILES:= \\\n\t$(LINUX_DIR)/net/sunrpc/auth_gss/auth_rpcgss.ko \\\n\t$(LINUX_DIR)/net/sunrpc/auth_gss/rpcsec_gss_krb5.ko\n  AUTOLOAD:=$(call AutoLoad,31,auth_rpcgss rpcsec_gss_krb5)\nendef\n\ndefine KernelPackage/fs-nfs-common-rpcsec/description\n Kernel modules for NFS Secure RPC\nendef\n\n$(eval $(call KernelPackage,fs-nfs-common-rpcsec))\n\n\ndefine KernelPackage/fs-nfs-v3\n  SUBMENU:=$(FS_MENU)\n  TITLE:=NFS3 filesystem client support\n  DEPENDS:=+kmod-fs-nfs\n  FILES:= \\\n\t$(LINUX_DIR)/fs/nfs/nfsv3.ko\n  AUTOLOAD:=$(call AutoLoad,41,nfsv3)\nendef\n\ndefine KernelPackage/fs-nfs-v3/description\n Kernel module for NFS v3 client support\nendef\n\n$(eval $(call KernelPackage,fs-nfs-v3))\n\n\ndefine KernelPackage/fs-nfs-v4\n  SUBMENU:=$(FS_MENU)\n  TITLE:=NFS4 filesystem client support\n  DEPENDS:=+kmod-fs-nfs\n  KCONFIG:= \\\n\tCONFIG_NFS_V4=y\n  FILES:= \\\n\t$(LINUX_DIR)/fs/nfs/nfsv4.ko\n  AUTOLOAD:=$(call AutoLoad,41,nfsv4)\nendef\n\ndefine KernelPackage/fs-nfs-v4/description\n Kernel module for NFS v4 client support\nendef\n\n$(eval $(call KernelPackage,fs-nfs-v4))\n\n\ndefine KernelPackage/fs-nfsd\n  SUBMENU:=$(FS_MENU)\n  TITLE:=NFS kernel server support\n  DEPENDS:=+kmod-fs-nfs-common +kmod-fs-exportfs +kmod-fs-nfs-common-rpcsec\n  KCONFIG:= \\\n\tCONFIG_NFSD \\\n\tCONFIG_NFSD_V4=y \\\n\tCONFIG_NFSD_V4_SECURITY_LABEL=n \\\n\tCONFIG_NFSD_BLOCKLAYOUT=n \\\n\tCONFIG_NFSD_SCSILAYOUT=n \\\n\tCONFIG_NFSD_FLEXFILELAYOUT=n \\\n\tCONFIG_NFSD_FAULT_INJECTION=n \\\n\tCONFIG_NFSD_V4_2_INTER_SSC=n\n  FILES:=$(LINUX_DIR)/fs/nfsd/nfsd.ko\n  AUTOLOAD:=$(call AutoLoad,40,nfsd)\nendef\n\ndefine KernelPackage/fs-nfsd/description\n Kernel module for NFS kernel server support\nendef\n\n$(eval $(call KernelPackage,fs-nfsd))\n\n\ndefine KernelPackage/fs-ntfs\n  SUBMENU:=$(FS_MENU)\n  TITLE:=NTFS filesystem support\n  KCONFIG:=CONFIG_NTFS_FS\n  FILES:=$(LINUX_DIR)/fs/ntfs/ntfs.ko\n  AUTOLOAD:=$(call AutoLoad,30,ntfs)\n  $(call AddDepends/nls)\nendef\n\ndefine KernelPackage/fs-ntfs/description\n Kernel module for NTFS filesystem support\nendef\n\n$(eval $(call KernelPackage,fs-ntfs))\n\n\ndefine KernelPackage/pstore\n  SUBMENU:=$(FS_MENU)\n  TITLE:=Pstore file system\n  DEFAULT:=m if ALL_KMODS\n  KCONFIG:= \\\n\tCONFIG_PSTORE \\\n\tCONFIG_PSTORE_COMPRESS=y \\\n\tCONFIG_PSTORE_COMPRESS_DEFAULT=\"deflate\" \\\n\tCONFIG_PSTORE_DEFLATE_COMPRESS=y \\\n\tCONFIG_PSTORE_DEFLATE_COMPRESS_DEFAULT=y\n  FILES:= $(LINUX_DIR)/fs/pstore/pstore.ko\n  AUTOLOAD:=$(call AutoLoad,30,pstore,1)\nendef\n\ndefine KernelPackage/pstore/description\n Kernel module for pstore filesystem support\nendef\n\n$(eval $(call KernelPackage,pstore))\n\n\ndefine KernelPackage/fs-reiserfs\n  SUBMENU:=$(FS_MENU)\n  TITLE:=ReiserFS filesystem support\n  KCONFIG:=CONFIG_REISERFS_FS\n  FILES:=$(LINUX_DIR)/fs/reiserfs/reiserfs.ko\n  AUTOLOAD:=$(call AutoLoad,30,reiserfs,1)\nendef\n\ndefine KernelPackage/fs-reiserfs/description\n Kernel module for ReiserFS support\nendef\n\n$(eval $(call KernelPackage,fs-reiserfs))\n\n\ndefine KernelPackage/fs-squashfs\n  SUBMENU:=$(FS_MENU)\n  TITLE:=SquashFS 4.0 filesystem support\n  KCONFIG:=CONFIG_SQUASHFS \\\n\tCONFIG_SQUASHFS_XZ=y\n  FILES:=$(LINUX_DIR)/fs/squashfs/squashfs.ko\n  AUTOLOAD:=$(call AutoLoad,30,squashfs,1)\nendef\n\ndefine KernelPackage/fs-squashfs/description\n Kernel module for SquashFS 4.0 support\nendef\n\n$(eval $(call KernelPackage,fs-squashfs))\n\n\ndefine KernelPackage/fs-udf\n  SUBMENU:=$(FS_MENU)\n  TITLE:=UDF filesystem support\n  KCONFIG:=CONFIG_UDF_FS\n  FILES:=$(LINUX_DIR)/fs/udf/udf.ko\n  AUTOLOAD:=$(call AutoLoad,30,udf)\n  DEPENDS:=+kmod-lib-crc-itu-t +kmod-cdrom\n  $(call AddDepends/nls)\nendef\n\ndefine KernelPackage/fs-udf/description\n Kernel module for UDF filesystem support\nendef\n\n$(eval $(call KernelPackage,fs-udf))\n\n\ndefine KernelPackage/fs-vfat\n  SUBMENU:=$(FS_MENU)\n  TITLE:=VFAT filesystem support\n  KCONFIG:= \\\n\tCONFIG_FAT_FS \\\n\tCONFIG_VFAT_FS\n  FILES:= \\\n\t$(LINUX_DIR)/fs/fat/fat.ko \\\n\t$(LINUX_DIR)/fs/fat/vfat.ko\n  AUTOLOAD:=$(call AutoLoad,30,fat vfat)\n  $(call AddDepends/nls,cp437 iso8859-1 utf8)\nendef\n\ndefine KernelPackage/fs-vfat/description\n Kernel module for VFAT filesystem support\nendef\n\n$(eval $(call KernelPackage,fs-vfat))\n\n\ndefine KernelPackage/fs-xfs\n  SUBMENU:=$(FS_MENU)\n  TITLE:=XFS filesystem support\n  KCONFIG:=CONFIG_XFS_FS\n  DEPENDS:= +kmod-fs-exportfs +kmod-lib-crc32c\n  FILES:=$(LINUX_DIR)/fs/xfs/xfs.ko\n  AUTOLOAD:=$(call AutoLoad,30,xfs,1)\nendef\n\ndefine KernelPackage/fs-xfs/description\n Kernel module for XFS support\nendef\n\n$(eval $(call KernelPackage,fs-xfs))\n\n\ndefine KernelPackage/fuse\n  SUBMENU:=$(FS_MENU)\n  TITLE:=FUSE (Filesystem in Userspace) support\n  KCONFIG:= CONFIG_FUSE_FS\n  FILES:=$(LINUX_DIR)/fs/fuse/fuse.ko\n  AUTOLOAD:=$(call AutoLoad,80,fuse)\nendef\n\ndefine KernelPackage/fuse/description\n Kernel module for userspace filesystem support\nendef\n\n$(eval $(call KernelPackage,fuse))\n\n\ndefine KernelPackage/fs-ntfs3\n  SUBMENU:=$(FS_MENU)\n  TITLE:=Ntfs3 support\n  KCONFIG:= CONFIG_NTFS3_FS CONFIG_NTFS3_FS_POSIX_ACL=y\n  FILES:=$(LINUX_DIR)/fs/ntfs3/ntfs3.ko\n  $(call AddDepends/nls)\n  AUTOLOAD:=$(call AutoLoad,80,ntfs3)\nendef\n\ndefine KernelPackage/fuse/description\n Kernel module for new NTFS3 filesystem support\nendef\n\n$(eval $(call KernelPackage,fs-ntfs3))\n"
  },
  {
    "path": "package/kernel/linux/modules/gpio-cascade.mk",
    "content": "# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\nMENU_TITLE:=GPIO support\n\ndefine KernelPackage/gpio-cascade\n  SUBMENU:=$(MENU_TITLE)\n  TITLE:=Generic GPIO cascade\n  KCONFIG:=CONFIG_GPIO_CASCADE\n  DEPENDS:=@GPIO_SUPPORT +kmod-mux-core\n  FILES:=$(LINUX_DIR)/drivers/gpio/gpio-cascade.ko\n  AUTOLOAD:=$(call AutoLoad,29,gpio-cascade,1)\nendef\n\ndefine KernelPackage/gpio-cascade/description\n  Kernel module for Generic GPIO cascade\nendef\n\n$(eval $(call KernelPackage,gpio-cascade))\n"
  },
  {
    "path": "package/kernel/linux/modules/hwmon.mk",
    "content": "#\n# Copyright (C) 2006-2014 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\nHWMON_MENU:=Hardware Monitoring Support\n\ndefine KernelPackage/hwmon-core\n  SUBMENU:=$(HWMON_MENU)\n  TITLE:=Hardware monitoring support\n  KCONFIG:= \\\n\tCONFIG_HWMON \\\n\tCONFIG_HWMON_DEBUG_CHIP=n\n  FILES:= \\\n\t$(LINUX_DIR)/drivers/hwmon/hwmon.ko\nendef\n\ndefine KernelPackage/hwmon-core/description\n Kernel modules for hardware monitoring\nendef\n\n$(eval $(call KernelPackage,hwmon-core))\n\n\ndefine AddDepends/hwmon\n  SUBMENU:=$(HWMON_MENU)\n  DEPENDS:=+kmod-hwmon-core $(1)\nendef\n\ndefine KernelPackage/hwmon-ad7418\n  TITLE:=AD741x monitoring support\n  KCONFIG:=CONFIG_SENSORS_AD7418\n  FILES:=$(LINUX_DIR)/drivers/hwmon/ad7418.ko\n  AUTOLOAD:=$(call AutoLoad,60,ad7418 ad7418)\n  $(call AddDepends/hwmon,+kmod-i2c-core)\nendef\n\ndefine KernelPackage/hwmon-ad7418/description\n Kernel module for Analog Devices AD7416, AD7417 and AD7418 temperature monitor chip\nendef\n\n$(eval $(call KernelPackage,hwmon-ad7418))\n\ndefine KernelPackage/hwmon-adt7410\n  TITLE:=ADT7410 monitoring support\n  KCONFIG:= \\\n\tCONFIG_SENSORS_ADT7X10 \\\n\tCONFIG_SENSORS_ADT7410\n  FILES:= \\\n\t$(LINUX_DIR)/drivers/hwmon/adt7x10.ko \\\n\t$(LINUX_DIR)/drivers/hwmon/adt7410.ko\n  AUTOLOAD:=$(call AutoLoad,60,adt7x10 adt7410)\n  $(call AddDepends/hwmon,+kmod-i2c-core)\nendef\n\ndefine KernelPackage/hwmon-adt7410/description\n Kernel module for ADT7410/7420 I2C thermal monitor chip\nendef\n\n$(eval $(call KernelPackage,hwmon-adt7410))\n\n\ndefine KernelPackage/hwmon-adt7475\n  TITLE:=ADT7473/7475/7476/7490 monitoring support\n  KCONFIG:=CONFIG_SENSORS_ADT7475\n  FILES:=$(LINUX_DIR)/drivers/hwmon/adt7475.ko\n  AUTOLOAD:=$(call AutoProbe,adt7475)\n  $(call AddDepends/hwmon,+kmod-i2c-core +kmod-hwmon-vid)\nendef\n\ndefine KernelPackage/hwmon-adt7475/description\n Kernel module for ADT7473/7475/7476/7490 thermal monitor chip\nendef\n\n$(eval $(call KernelPackage,hwmon-adt7475))\n\n\ndefine KernelPackage/hwmon-dme1737\n  TITLE:=SMSC DME1737 and compatible monitoring support\n  KCONFIG:=CONFIG_SENSORS_DME1737\n  FILES:= \\\n\t$(LINUX_DIR)/drivers/hwmon/dme1737.ko\n  AUTOLOAD:=$(call AutoProbe,dme1737)\n  $(call AddDepends/hwmon,+kmod-i2c-core +kmod-hwmon-vid)\nendef\n\ndefine KernelPackage/hwmon-dme1737/description\n SMSC DME1737, SCH3112, SCH3114, SCH3116, SCH5027 monitoring support\nendef\n\n$(eval $(call KernelPackage,hwmon-dme1737))\n\n\ndefine KernelPackage/hwmon-drivetemp\n  TITLE:=Hard disk drives with temperature sensor\n  KCONFIG:=CONFIG_SENSORS_DRIVETEMP\n  FILES:=$(LINUX_DIR)/drivers/hwmon/drivetemp.ko\n  AUTOLOAD:=$(call AutoLoad,60,drivetemp)\n  $(call AddDepends/hwmon,+kmod-ata-core +kmod-scsi-core)\nendef\n\ndefine KernelPackage/hwmon-drivetemp/description\n Kernel module for Hard disk drives with temperature sensor\nendef\n\n$(eval $(call KernelPackage,hwmon-drivetemp))\n\n\ndefine KernelPackage/hwmon-gpiofan\n  TITLE:=Generic GPIO FAN support\n  KCONFIG:=CONFIG_SENSORS_GPIO_FAN\n  FILES:=$(LINUX_DIR)/drivers/hwmon/gpio-fan.ko\n  AUTOLOAD:=$(call AutoLoad,60,gpio-fan)\n  $(call AddDepends/hwmon,+kmod-i2c-core +PACKAGE_kmod-thermal:kmod-thermal)\nendef\n\ndefine KernelPackage/hwmon-gpiofan/description\n  Kernel module for GPIO controlled FANs\nendef\n\n$(eval $(call KernelPackage,hwmon-gpiofan))\n\n\ndefine KernelPackage/hwmon-f71882fg\n  TITLE:=F71882FG compatible monitoring support\n  KCONFIG:=CONFIG_SENSORS_F71882FG\n  FILES:=$(LINUX_DIR)/drivers/hwmon/f71882fg.ko\n  AUTOLOAD:=$(call AutoProbe,f71882fg)\n  $(call AddDepends/hwmon,@TARGET_x86)\nendef\n\ndefine KernelPackage/hwmon-f71882fg/description\n Kernel module for hardware monitoring via many Fintek Super-IO chips.\nendef\n\n$(eval $(call KernelPackage,hwmon-f71882fg))\n\n\ndefine KernelPackage/hwmon-g762\n  TITLE:=G762/G763 fan speed PWM controller support\n  KCONFIG:=CONFIG_SENSORS_G762\n  FILES:=$(LINUX_DIR)/drivers/hwmon/g762.ko\n  AUTOLOAD:=$(call AutoProbe,g762)\n  $(call AddDepends/hwmon,+kmod-i2c-core)\nendef\n\ndefine KernelPackage/hwmon-g762/description\n Kernel module for Global Mixed-mode Technology Inc G762 and G763 fan speed PWM controller chips.\nendef\n\n$(eval $(call KernelPackage,hwmon-g762))\n\n\ndefine KernelPackage/hwmon-ina209\n  TITLE:=INA209 monitoring support\n  KCONFIG:=CONFIG_SENSORS_INA209\n  FILES:=$(LINUX_DIR)/drivers/hwmon/ina209.ko\n  AUTOLOAD:=$(call AutoProbe,ina209)\n  $(call AddDepends/hwmon,+kmod-i2c-core)\nendef\n\ndefine KernelPackage/hwmon-ina209/description\n Kernel module for ina209 dc power monitor chips\nendef\n\n$(eval $(call KernelPackage,hwmon-ina209))\n\n\ndefine KernelPackage/hwmon-ina2xx\n  TITLE:=INA2XX monitoring support\n  KCONFIG:=CONFIG_SENSORS_INA2XX\n  FILES:=$(LINUX_DIR)/drivers/hwmon/ina2xx.ko\n  AUTOLOAD:=$(call AutoProbe,ina2xx)\n  $(call AddDepends/hwmon,+kmod-i2c-core +kmod-regmap-i2c)\nendef\n\ndefine KernelPackage/hwmon-ina2xx/description\n Kernel module for ina2xx dc current monitor chips\nendef\n\n$(eval $(call KernelPackage,hwmon-ina2xx))\n\n\ndefine KernelPackage/hwmon-it87\n  TITLE:=IT87 monitoring support\n  KCONFIG:=CONFIG_SENSORS_IT87\n  FILES:=$(LINUX_DIR)/drivers/hwmon/it87.ko\n  AUTOLOAD:=$(call AutoProbe,it87)\n  $(call AddDepends/hwmon,+kmod-i2c-core +kmod-hwmon-vid +PACKAGE_kmod-thermal:kmod-thermal)\nendef\n\ndefine KernelPackage/hwmon-it87/description\n Kernel module for it87 thermal and voltage monitor chip\nendef\n\n$(eval $(call KernelPackage,hwmon-it87))\n\n\ndefine KernelPackage/hwmon-lm63\n  TITLE:=LM63/64 monitoring support\n  KCONFIG:=CONFIG_SENSORS_LM63\n  FILES:=$(LINUX_DIR)/drivers/hwmon/lm63.ko\n  AUTOLOAD:=$(call AutoProbe,lm63)\n  $(call AddDepends/hwmon,+kmod-i2c-core +kmod-regmap-i2c)\nendef\n\ndefine KernelPackage/hwmon-lm63/description\n Kernel module for lm63 and lm64 thermal monitor chip\nendef\n\n$(eval $(call KernelPackage,hwmon-lm63))\n\n\ndefine KernelPackage/hwmon-lm70\n  TITLE:=LM70 monitoring support\n  KCONFIG:=CONFIG_SENSORS_LM70 \\\n        CONFIG_SPI=y \\\n        CONFIG_SPI_MASTER=y\n  FILES:=$(LINUX_DIR)/drivers/hwmon/lm70.ko\n  AUTOLOAD:=$(call AutoProbe,lm70)\n  $(call AddDepends/hwmon)\nendef\n\ndefine KernelPackage/hwmon-lm70/description\n Kernel module for lm70 and compatible thermal monitor chip\nendef\n\n$(eval $(call KernelPackage,hwmon-lm70))\n\n\ndefine KernelPackage/hwmon-lm75\n  TITLE:=LM75 monitoring support\n  KCONFIG:=CONFIG_SENSORS_LM75\n  FILES:=$(LINUX_DIR)/drivers/hwmon/lm75.ko\n  AUTOLOAD:=$(call AutoProbe,lm75)\n  $(call AddDepends/hwmon,+kmod-i2c-core +PACKAGE_kmod-thermal:kmod-thermal +kmod-regmap-i2c)\nendef\n\ndefine KernelPackage/hwmon-lm75/description\n Kernel module for lm75 thermal monitor chip\nendef\n\n$(eval $(call KernelPackage,hwmon-lm75))\n\n\ndefine KernelPackage/hwmon-lm77\n  TITLE:=LM77 monitoring support\n  KCONFIG:=CONFIG_SENSORS_LM77\n  FILES:=$(LINUX_DIR)/drivers/hwmon/lm77.ko\n  AUTOLOAD:=$(call AutoProbe,lm77)\n  $(call AddDepends/hwmon,+kmod-i2c-core)\nendef\n\ndefine KernelPackage/hwmon-lm77/description\n Kernel module for LM77 thermal monitor chip\nendef\n\n$(eval $(call KernelPackage,hwmon-lm77))\n\n\ndefine KernelPackage/hwmon-lm85\n  TITLE:=LM85 monitoring support\n  KCONFIG:=CONFIG_SENSORS_LM85\n  FILES:=$(LINUX_DIR)/drivers/hwmon/lm85.ko\n  AUTOLOAD:=$(call AutoProbe,lm85)\n  $(call AddDepends/hwmon,+kmod-i2c-core +kmod-hwmon-vid)\nendef\n\ndefine KernelPackage/hwmon-lm85/description\n Kernel module for LM85 thermal monitor chip\nendef\n\n$(eval $(call KernelPackage,hwmon-lm85))\n\n\ndefine KernelPackage/hwmon-lm90\n  TITLE:=LM90 monitoring support\n  KCONFIG:=CONFIG_SENSORS_LM90\n  FILES:=$(LINUX_DIR)/drivers/hwmon/lm90.ko\n  AUTOLOAD:=$(call AutoProbe,lm90)\n  $(call AddDepends/hwmon,+kmod-i2c-core)\nendef\n\ndefine KernelPackage/hwmon-lm90/description\n Kernel module for LM90 thermal monitor chip\nendef\n\n$(eval $(call KernelPackage,hwmon-lm90))\n\n\ndefine KernelPackage/hwmon-lm92\n  TITLE:=LM92 monitoring support\n  KCONFIG:=CONFIG_SENSORS_LM92\n  FILES:=$(LINUX_DIR)/drivers/hwmon/lm92.ko\n  AUTOLOAD:=$(call AutoProbe,lm92)\n  $(call AddDepends/hwmon,+kmod-i2c-core)\nendef\n\ndefine KernelPackage/hwmon-lm92/description\n Kernel module for LM92 thermal monitor chip\nendef\n\n$(eval $(call KernelPackage,hwmon-lm92))\n\n\ndefine KernelPackage/hwmon-lm95241\n  TITLE:=LM95241 monitoring support\n  KCONFIG:=CONFIG_SENSORS_LM95241\n  FILES:=$(LINUX_DIR)/drivers/hwmon/lm95241.ko\n  AUTOLOAD:=$(call AutoProbe,lm95241)\n  $(call AddDepends/hwmon,+kmod-i2c-core)\nendef\n\ndefine KernelPackage/hwmon-lm95241/description\n Kernel module for LM95241 thermal monitor chip\nendef\n\n$(eval $(call KernelPackage,hwmon-lm95241))\n\n\ndefine KernelPackage/hwmon-ltc4151\n  TITLE:=LTC4151 monitoring support\n  KCONFIG:=CONFIG_SENSORS_LTC4151\n  FILES:=$(LINUX_DIR)/drivers/hwmon/ltc4151.ko\n  AUTOLOAD:=$(call AutoProbe,ltc4151)\n  $(call AddDepends/hwmon,+kmod-i2c-core)\nendef\n\ndefine KernelPackage/hwmon-ltc4151/description\n Kernel module for Linear Technology LTC4151 current and voltage monitor chip\nendef\n\n$(eval $(call KernelPackage,hwmon-ltc4151))\n\n\ndefine KernelPackage/hwmon-mcp3021\n  TITLE:=MCP3021/3221 monitoring support\n  KCONFIG:=CONFIG_SENSORS_MCP3021\n  FILES:=$(LINUX_DIR)/drivers/hwmon/mcp3021.ko\n  AUTOLOAD:=$(call AutoProbe,mcp3021)\n  $(call AddDepends/hwmon,+kmod-i2c-core)\nendef\n\ndefine KernelPackage/hwmon-mcp3021/description\n Kernel module for Linear Technology MCP3021/3221 current and voltage monitor chip\nendef\n\n$(eval $(call KernelPackage,hwmon-mcp3021))\n\n\ndefine KernelPackage/hwmon-nct6775\n  TITLE:=NCT6106D/6775F/6776F/6779D/6791D/6792D/6793D and compatibles monitoring support\n  KCONFIG:=CONFIG_SENSORS_NCT6775\n  FILES:=$(LINUX_DIR)/drivers/hwmon/nct6775.ko\n  AUTOLOAD:=$(call AutoProbe,nct6775)\n  $(call AddDepends/hwmon,@PCI_SUPPORT @TARGET_x86 +kmod-hwmon-vid)\nendef\n\ndefine KernelPackage/hwmon-nct6775/description\n Kernel module for NCT6106D/6775F/6776F/6779D/6791D/6792D/6793D thermal monitor chip\nendef\n\n$(eval $(call KernelPackage,hwmon-nct6775))\n\n\ndefine KernelPackage/hwmon-nct7802\n  TITLE:=NCT7802Y and compatibles monitoring support\n  KCONFIG:=CONFIG_SENSORS_NCT7802\n  FILES:=$(LINUX_DIR)/drivers/hwmon/nct7802.ko\n  AUTOLOAD:=$(call AutoProbe,nct7802)\n  $(call AddDepends/hwmon,+kmod-regmap-i2c)\nendef\n\ndefine KernelPackage/hwmon-nct7802/description\n Kernel module for NCT7802Y thermal monitor chip\nendef\n\n$(eval $(call KernelPackage,hwmon-nct7802))\n\n\ndefine KernelPackage/hwmon-pc87360\n  TITLE:=PC87360 monitoring support\n  KCONFIG:=CONFIG_SENSORS_PC87360\n  FILES:=$(LINUX_DIR)/drivers/hwmon/pc87360.ko\n  AUTOLOAD:=$(call AutoProbe,pc87360)\n  $(call AddDepends/hwmon,@TARGET_x86 +kmod-hwmon-vid)\nendef\n\ndefine KernelPackage/hwmon-pc87360/description\n Kernel modules for PC87360 chips\nendef\n\n$(eval $(call KernelPackage,hwmon-pc87360))\n\n\ndefine KernelPackage/pmbus-core\n  TITLE:=PMBus support\n  KCONFIG:= CONFIG_PMBUS\n  FILES:=$(LINUX_DIR)/drivers/hwmon/pmbus/pmbus_core.ko\n  $(call AddDepends/hwmon,+kmod-i2c-core)\nendef\n\ndefine KernelPackage/pmbus-core/description\n Kernel modules for Power Management Bus\nendef\n\n$(eval $(call KernelPackage,pmbus-core))\n\n\ndefine KernelPackage/pmbus-zl6100\n  TITLE:=Intersil / Zilker Labs ZL6100 hardware monitoring\n  KCONFIG:=CONFIG_SENSORS_ZL6100\n  FILES:=$(LINUX_DIR)/drivers/hwmon/pmbus/zl6100.ko\n  AUTOLOAD:=$(call AutoProbe,zl6100)\n  $(call AddDepends/hwmon, +kmod-pmbus-core)\nendef\n\ndefine KernelPackage/pmbus-zl6100/description\n Kernel module for Intersil / Zilker Labs ZL6100 and\ncompatible digital DC-DC controllers\nendef\n\n$(eval $(call KernelPackage,pmbus-zl6100))\n\n\ndefine KernelPackage/hwmon-pwmfan\n  TITLE:=Generic PWM FAN support\n  KCONFIG:=CONFIG_SENSORS_PWM_FAN\n  FILES:=$(LINUX_DIR)/drivers/hwmon/pwm-fan.ko\n  AUTOLOAD:=$(call AutoLoad,60,pwm-fan)\n  $(call AddDepends/hwmon, +PACKAGE_kmod-thermal:kmod-thermal)\nendef\n\ndefine KernelPackage/hwmon-pwmfan/description\n  Kernel module for PWM controlled FANs\nendef\n\n$(eval $(call KernelPackage,hwmon-pwmfan))\n\n\ndefine KernelPackage/hwmon-sch5627\n  TITLE:=SMSC SCH5627 monitoring support\n  KCONFIG:= \\\n\tCONFIG_SENSORS_SCH5627 \\\n\tCONFIG_WATCHDOG_CORE=y\n  FILES:= \\\n\t$(LINUX_DIR)/drivers/hwmon/sch5627.ko \\\n\t$(LINUX_DIR)/drivers/hwmon/sch56xx-common.ko\n  AUTOLOAD:=$(call AutoProbe,sch5627)\n  $(call AddDepends/hwmon,+kmod-i2c-core)\nendef\n\ndefine KernelPackage/hwmon-sch5627/description\n SMSC SCH5627 Super I/O chips include complete hardware monitoring\nendef\n\n$(eval $(call KernelPackage,hwmon-sch5627))\n\n\ndefine KernelPackage/hwmon-sht21\n  TITLE:=Sensiron SHT21 and compat. monitoring support\n  KCONFIG:=CONFIG_SENSORS_SHT21\n  FILES:=$(LINUX_DIR)/drivers/hwmon/sht21.ko\n  AUTOLOAD:=$(call AutoProbe,sht21)\n  $(call AddDepends/hwmon,+kmod-i2c-core)\nendef\n\ndefine KernelPackage/hwmon-sht21/description\n Kernel module for Sensirion SHT21 and SHT25 temperature and humidity sensors chip\nendef\n\n$(eval $(call KernelPackage,hwmon-sht21))\n\n\ndefine KernelPackage/hwmon-tmp102\n  TITLE:=Texas Instruments TMP102 monitoring support\n  KCONFIG:=CONFIG_SENSORS_TMP102\n  FILES:=$(LINUX_DIR)/drivers/hwmon/tmp102.ko\n  AUTOLOAD:=$(call AutoProbe,tmp102)\n  $(call AddDepends/hwmon,+kmod-i2c-core +PACKAGE_kmod-thermal:kmod-thermal +kmod-regmap-i2c)\nendef\n\ndefine KernelPackage/hwmon-tmp102/description\n Kernel module for Texas Instruments TMP102 temperature sensors chip\nendef\n\n$(eval $(call KernelPackage,hwmon-tmp102))\n\n\ndefine KernelPackage/hwmon-tmp103\n  TITLE:=Texas Instruments TMP103 monitoring support\n  KCONFIG:=CONFIG_SENSORS_TMP103\n  FILES:=$(LINUX_DIR)/drivers/hwmon/tmp103.ko\n  AUTOLOAD:=$(call AutoProbe,tmp103)\n  $(call AddDepends/hwmon,+kmod-i2c-core +kmod-regmap-i2c)\nendef\n\ndefine KernelPackage/hwmon-tmp103/description\n Kernel module for Texas Instruments TMP103 temperature sensors chip\nendef\n\n$(eval $(call KernelPackage,hwmon-tmp103))\n\n\ndefine KernelPackage/hwmon-tmp421\n  TITLE:=TI TMP421 and compatible monitoring support\n  KCONFIG:=CONFIG_SENSORS_TMP421\n  FILES:=$(LINUX_DIR)/drivers/hwmon/tmp421.ko\n  AUTOLOAD:=$(call AutoLoad,60,tmp421)\n  $(call AddDepends/hwmon,+kmod-i2c-core)\nendef\n\ndefine KernelPackage/hwmon-tmp421/description\n  Kernel module for the Texas Instruments TMP421 and compatible chips.\nendef\n\n$(eval $(call KernelPackage,hwmon-tmp421))\n\n\ndefine KernelPackage/hwmon-vid\n  TITLE:=VID/VRM/VRD voltage conversion module.\n  KCONFIG:=CONFIG_HWMON_VID\n  FILES:=$(LINUX_DIR)/drivers/hwmon/hwmon-vid.ko\n  AUTOLOAD:=$(call AutoLoad,41,hwmon-vid)\n  $(call AddDepends/hwmon,)\nendef\n\ndefine KernelPackage/hwmon-vid/description\n VID/VRM/VRD voltage conversion module for hardware monitoring\nendef\n\n$(eval $(call KernelPackage,hwmon-vid))\n\n\ndefine KernelPackage/hwmon-w83627ehf\n  TITLE:=Winbond W83627EHF/EHG/DHG/UHG, W83667HG monitoring support\n  KCONFIG:=CONFIG_SENSORS_W83627EHF\n  FILES:=$(LINUX_DIR)/drivers/hwmon/w83627ehf.ko\n  AUTOLOAD:=$(call AutoProbe,w83627ehf)\n  $(call AddDepends/hwmon,@TARGET_x86 +kmod-hwmon-vid)\nendef\n\ndefine KernelPackage/hwmon-w83627ehf/description\n Kernel module for Winbond W83627EHF/EHG/DHG/UHG and W83667HG thermal monitor chip\n Support for NCT6775F and NCT6776F has been removed from this driver in favour of\n using the nct6775 driver to handle those chips.\nendef\n\n$(eval $(call KernelPackage,hwmon-w83627ehf))\n\n\ndefine KernelPackage/hwmon-w83627hf\n  TITLE:=Winbond W83627HF monitoring support\n  KCONFIG:=CONFIG_SENSORS_W83627HF\n  FILES:=$(LINUX_DIR)/drivers/hwmon/w83627hf.ko\n  AUTOLOAD:=$(call AutoLoad,50,w83627hf)\n  $(call AddDepends/hwmon,@TARGET_x86 +kmod-hwmon-vid)\nendef\n\ndefine KernelPackage/hwmon-w83627hf/description\n  Kernel module for the Winbond W83627HF chips.\nendef\n\n$(eval $(call KernelPackage,hwmon-w83627hf))\n\n\ndefine KernelPackage/hwmon-w83793\n  TITLE:=Winbond W83793G/R monitoring support\n  KCONFIG:=CONFIG_SENSORS_W83793\n  FILES:=$(LINUX_DIR)/drivers/hwmon/w83793.ko\n  AUTOLOAD:=$(call AutoProbe,w83793)\n  $(call AddDepends/hwmon,+kmod-i2c-core +kmod-hwmon-vid)\nendef\n\ndefine KernelPackage/hwmon-w83793/description\n  Kernel module for the Winbond W83793G and W83793R chips.\nendef\n\n$(eval $(call KernelPackage,hwmon-w83793))\n\n\ndefine KernelPackage/hwmon-adcxx\n  TITLE:=ADCxx monitoring support\n  KCONFIG:=CONFIG_SENSORS_ADCXX\n  FILES:=$(LINUX_DIR)/drivers/hwmon/adcxx.ko\n  AUTOLOAD:=$(call AutoLoad,60,adcxx)\n  $(call AddDepends/hwmon,)\nendef\n\ndefine KernelPackage/hwmon-adcxx/description\n  Kernel module for the National Semiconductor\n  ADC<bb><c>S<sss> chip family, where\n  * bb  is the resolution in number of bits (8, 10, 12)\n  * c   is the number of channels (1, 2, 4, 8)\n  * sss is the maximum conversion speed (021 for 200 kSPS, 051 for 500\n    kSPS and 101 for 1 MSPS)\n\n  Examples : ADC081S101, ADC124S501, ...\nendef\n\n$(eval $(call KernelPackage,hwmon-adcxx))\n\n\n"
  },
  {
    "path": "package/kernel/linux/modules/i2c.mk",
    "content": "#\n# Copyright (C) 2006-2009 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\nI2C_MENU:=I2C support\n\nModuleConfVar=$(word 1,$(subst :,$(space),$(1)))\nModuleFullPath=$(LINUX_DIR)/$(word 2,$(subst :,$(space),$(1))).ko\nModuleKconfig=$(foreach mod,$(1),$(call ModuleConfVar,$(mod)))\nModuleFiles=$(foreach mod,$(1),$(call ModuleFullPath,$(mod)))\nModuleAuto=$(call AutoLoad,$(1),$(foreach mod,$(2),$(basename $(notdir $(call ModuleFullPath,$(mod))))),$(3))\n\ndefine i2c_defaults\n  SUBMENU:=$(I2C_MENU)\n  KCONFIG:=$(call ModuleKconfig,$(1))\n  FILES:=$(call ModuleFiles,$(1))\n  AUTOLOAD:=$(call ModuleAuto,$(2),$(1),$(3))\nendef\n\nI2C_CORE_MODULES:= \\\n  CONFIG_I2C:drivers/i2c/i2c-core \\\n  CONFIG_I2C_CHARDEV:drivers/i2c/i2c-dev\n\ndefine KernelPackage/i2c-core\n  $(call i2c_defaults,$(I2C_CORE_MODULES),51)\n  TITLE:=I2C support\nendef\n\ndefine KernelPackage/i2c-core/description\n Kernel modules for I2C support\nendef\n\n$(eval $(call KernelPackage,i2c-core))\n\n\nI2C_ALGOBIT_MODULES:= \\\n  CONFIG_I2C_ALGOBIT:drivers/i2c/algos/i2c-algo-bit\n\ndefine KernelPackage/i2c-algo-bit\n  $(call i2c_defaults,$(I2C_ALGOBIT_MODULES),55)\n  TITLE:=I2C bit-banging interfaces\n  DEPENDS:=+kmod-i2c-core\nendef\n\ndefine KernelPackage/i2c-algo-bit/description\n Kernel modules for I2C bit-banging interfaces\nendef\n\n$(eval $(call KernelPackage,i2c-algo-bit))\n\n\nI2C_ALGOPCA_MODULES:= \\\n  CONFIG_I2C_ALGOPCA:drivers/i2c/algos/i2c-algo-pca\n\ndefine KernelPackage/i2c-algo-pca\n  $(call i2c_defaults,$(I2C_ALGOPCA_MODULES),55)\n  TITLE:=I2C PCA 9564 interfaces\n  DEPENDS:=+kmod-i2c-core\nendef\n\ndefine KernelPackage/i2c-algo-pca/description\n Kernel modules for I2C PCA 9564 interfaces\nendef\n\n$(eval $(call KernelPackage,i2c-algo-pca))\n\n\nI2C_ALGOPCF_MODULES:= \\\n  CONFIG_I2C_ALGOPCF:drivers/i2c/algos/i2c-algo-pcf\n\ndefine KernelPackage/i2c-algo-pcf\n  $(call i2c_defaults,$(I2C_ALGOPCF_MODULES),55)\n  TITLE:=I2C PCF 8584 interfaces\n  DEPENDS:=+kmod-i2c-core\nendef\n\ndefine KernelPackage/i2c-algo-pcf/description\n Kernel modules for I2C PCF 8584 interfaces\nendef\n\n$(eval $(call KernelPackage,i2c-algo-pcf))\n\n\nI2C_DWCORE_MODULES:= \\\n  CONFIG_I2C_DESIGNWARE_CORE:drivers/i2c/busses/i2c-designware-core\n\ndefine KernelPackage/i2c-designware-core\n  $(call i2c_defaults,$(I2C_DWCORE_MODULES),58)\n  TITLE:=Synopsys DesignWare I2C core\n  DEPENDS:=+kmod-i2c-core +!LINUX_5_4:kmod-regmap-core\n  HIDDEN:=y\nendef\n\n$(eval $(call KernelPackage,i2c-designware-core))\n\n\nI2C_DWPCI_MODULES:= \\\n  CONFIG_I2C_DESIGNWARE_PCI:drivers/i2c/busses/i2c-designware-pci\n\ndefine KernelPackage/i2c-designware-pci\n  $(call i2c_defaults,$(I2C_DWPCI_MODULES),59)\n  TITLE:=Synopsys DesignWare PCI\n  DEPENDS:=+kmod-i2c-designware-core\nendef\n\ndefine KernelPackage/i2c-designware-pci/description\n Support for Synopsys DesignWare I2C controller. Only master mode is supported.\nendef\n\n$(eval $(call KernelPackage,i2c-designware-pci))\n\n\nI2C_GPIO_MODULES:= \\\n  CONFIG_I2C_GPIO:drivers/i2c/busses/i2c-gpio\n\ndefine KernelPackage/i2c-gpio\n  $(call i2c_defaults,$(I2C_GPIO_MODULES),59)\n  TITLE:=GPIO-based bitbanging I2C\n  DEPENDS:=@GPIO_SUPPORT +kmod-i2c-algo-bit\nendef\n\ndefine KernelPackage/i2c-gpio/description\n Kernel modules for a very simple bitbanging I2C driver utilizing the\n arch-neutral GPIO API to control the SCL and SDA lines.\nendef\n\n$(eval $(call KernelPackage,i2c-gpio))\n\n\nI2C_I801_MODULES:= \\\n  CONFIG_I2C_I801:drivers/i2c/busses/i2c-i801\n\ndefine KernelPackage/i2c-i801\n  $(call i2c_defaults,$(I2C_I801_MODULES),59)\n  TITLE:=Intel I801 and compatible I2C interfaces\n  DEPENDS:=@PCI_SUPPORT @TARGET_x86 +kmod-i2c-core +kmod-i2c-smbus\nendef\n\ndefine KernelPackage/i2c-i801/description\n Support for the Intel I801 family of mainboard I2C interfaces,\n specifically 82801AA, 82801AB, 82801BA, 82801CA/CAM, 82801DB,\n 82801EB/ER (ICH5/ICH5R), 6300ESB, ICH6, ICH7, ESB2, ICH8, ICH9,\n EP80579 (Tolapai), ICH10, 5/3400 Series (PCH), 6 Series (PCH),\n Patsburg (PCH), DH89xxCC (PCH), Panther Point (PCH),\n Lynx Point (PCH), Lynx Point-LP (PCH), Avoton (SOC),\n Wellsburg (PCH), Coleto Creek (PCH), Wildcat Point (PCH),\n Wildcat Point-LP (PCH), BayTrail (SOC), Sunrise Point-H (PCH),\n Sunrise Point-LP (PCH), DNV (SOC), Broxton (SOC),\n Lewisburg (PCH).\nendef\n\n$(eval $(call KernelPackage,i2c-i801))\n\n\nI2C_MUX_MODULES:= \\\n  CONFIG_I2C_MUX:drivers/i2c/i2c-mux\n\ndefine KernelPackage/i2c-mux\n  $(call i2c_defaults,$(I2C_MUX_MODULES),51)\n  TITLE:=I2C bus multiplexing support\n  DEPENDS:=+kmod-i2c-core\nendef\n\ndefine KernelPackage/i2c-mux/description\n Kernel modules for I2C bus multiplexing support\nendef\n\n$(eval $(call KernelPackage,i2c-mux))\n\nI2C_MUX_GPIO_MODULES:= \\\n  CONFIG_I2C_MUX_GPIO:drivers/i2c/muxes/i2c-mux-gpio\n\ndefine KernelPackage/i2c-mux-gpio\n  $(call i2c_defaults,$(I2C_MUX_GPIO_MODULES),51)\n  TITLE:=GPIO-based I2C mux/switches\n  DEPENDS:=+kmod-i2c-mux\nendef\n\ndefine KernelPackage/i2c-mux-gpio/description\n Kernel modules for GENERIC_GPIO I2C bus mux/switching devices\nendef\n\n$(eval $(call KernelPackage,i2c-mux-gpio))\n\n\nI2C_MUX_PCA9541_MODULES:= \\\n  CONFIG_I2C_MUX_PCA9541:drivers/i2c/muxes/i2c-mux-pca9541\n\ndefine KernelPackage/i2c-mux-pca9541\n  $(call i2c_defaults,$(I2C_MUX_PCA9541_MODULES),51)\n  TITLE:=Philips PCA9541 I2C mux/switches\n  DEPENDS:=+kmod-i2c-mux\nendef\n\ndefine KernelPackage/i2c-mux-pca9541/description\n Kernel modules for PCA9541 I2C bus mux/switching devices\nendef\n\n$(eval $(call KernelPackage,i2c-mux-pca9541))\n\nI2C_MUX_PCA954x_MODULES:= \\\n  CONFIG_I2C_MUX_PCA954x:drivers/i2c/muxes/i2c-mux-pca954x\n\ndefine KernelPackage/i2c-mux-pca954x\n  $(call i2c_defaults,$(I2C_MUX_PCA954x_MODULES),51)\n  TITLE:=Philips PCA954x I2C mux/switches\n  DEPENDS:=+kmod-i2c-mux\nendef\n\ndefine KernelPackage/i2c-mux-pca954x/description\n Kernel modules for PCA954x I2C bus mux/switching devices\nendef\n\n$(eval $(call KernelPackage,i2c-mux-pca954x))\n\n\nI2C_PIIX4_MODULES:= \\\n  CONFIG_I2C_PIIX4:drivers/i2c/busses/i2c-piix4\n\ndefine KernelPackage/i2c-piix4\n  $(call i2c_defaults,$(I2C_PIIX4_MODULES),59)\n  TITLE:=Intel PIIX4 and compatible I2C interfaces\n  DEPENDS:=@PCI_SUPPORT @TARGET_x86 +kmod-i2c-core\nendef\n\ndefine KernelPackage/i2c-piix4/description\n Support for the Intel PIIX4 family of mainboard I2C interfaces,\n specifically Intel PIIX4, Intel 440MX, ATI IXP200, ATI IXP300,\n ATI IXP400, ATI SB600, ATI SB700/SP5100, ATI SB800, AMD Hudson-2,\n AMD ML, AMD CZ, Serverworks OSB4, Serverworks CSB5,\n Serverworks CSB6, Serverworks HT-1000, Serverworks HT-1100 and\n SMSC Victory66.\nendef\n\n$(eval $(call KernelPackage,i2c-piix4))\n\n\nI2C_PXA_MODULES:= \\\n  CONFIG_I2C_PXA:drivers/i2c/busses/i2c-pxa\n\ndefine KernelPackage/i2c-pxa\n  $(call i2c_defaults,$(I2C_PXA_MODULES),50)\n  TITLE:=Intel PXA I2C bus driver\n  DEPENDS:=+kmod-i2c-core\nendef\n\ndefine KernelPackage/i2c-pxa/description\n  Kernel module for Intel PXA2XX I2C adapter\nendef\n\n$(eval $(call KernelPackage,i2c-pxa))\n\n\nI2C_SMBUS_MODULES:= \\\n  CONFIG_I2C_SMBUS:drivers/i2c/i2c-smbus\n\ndefine KernelPackage/i2c-smbus\n  $(call i2c_defaults,$(I2C_SMBUS_MODULES),58)\n  TITLE:=SMBus-specific protocols helper\n  DEPENDS:=+kmod-i2c-core\nendef\n\ndefine KernelPackage/i2c-smbus/description\n Support for the SMBus extensions to the I2C specification.\nendef\n\n$(eval $(call KernelPackage,i2c-smbus))\n\n\n\nI2C_TINY_USB_MODULES:= \\\n  CONFIG_I2C_TINY_USB:drivers/i2c/busses/i2c-tiny-usb\n\ndefine KernelPackage/i2c-tiny-usb\n  $(call i2c_defaults,$(I2C_TINY_USB_MODULES),59)\n  TITLE:=I2C Tiny USB adaptor\n  DEPENDS:=@USB_SUPPORT +kmod-i2c-core +kmod-usb-core\nendef\n\ndefine KernelPackage/i2c-tiny-usb/description\n Kernel module for the I2C Tiny USB adaptor developed\n by Till Harbaum (http://www.harbaum.org/till/i2c_tiny_usb)\nendef\n\n$(eval $(call KernelPackage,i2c-tiny-usb))\n\n\n"
  },
  {
    "path": "package/kernel/linux/modules/iio.mk",
    "content": "#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\nIIO_MENU:=Industrial I/O Modules\n\n\ndefine KernelPackage/iio-core\n  SUBMENU:=$(IIO_MENU)\n  TITLE:=Industrial IO core\n  KCONFIG:= \\\n\tCONFIG_IIO \\\n\tCONFIG_IIO_BUFFER=y \\\n\tCONFIG_IIO_TRIGGER=y\n  FILES:=$(LINUX_DIR)/drivers/iio/industrialio.ko\n  AUTOLOAD:=$(call AutoLoad,55,industrialio)\nendef\n\ndefine KernelPackage/iio-core/description\n The industrial I/O subsystem provides a unified framework for\n drivers for many different types of embedded sensors using a\n number of different physical interfaces (i2c, spi, etc)\nendef\n\n$(eval $(call KernelPackage,iio-core))\n\n\ndefine KernelPackage/iio-kfifo-buf\n  SUBMENU:=$(IIO_MENU)\n  TITLE:=Industrial I/O buffering based on kfifo\n  DEPENDS:=+kmod-iio-core\n  KCONFIG:=CONFIG_IIO_KFIFO_BUF\n  FILES:=$(LINUX_DIR)/drivers/iio/buffer/kfifo_buf.ko\n  AUTOLOAD:=$(call AutoLoad,55,kfifo_buf)\nendef\n\ndefine KernelPackage/iio-kfifo-buf/description\n A simple fifo based on kfifo.  Note that this currently provides no buffer\n events so it is up to userspace to work out how often to read from the buffer.\nendef\n\n$(eval $(call KernelPackage,iio-kfifo-buf))\n\n\ndefine KernelPackage/industrialio-triggered-buffer\n  SUBMENU:=$(IIO_MENU)\n  TITLE:=Provides helper functions for setting up triggered buffers.\n  DEPENDS:=+kmod-iio-core +kmod-iio-kfifo-buf\n  KCONFIG:=CONFIG_IIO_TRIGGERED_BUFFER\n  FILES:=$(LINUX_DIR)/drivers/iio/buffer/industrialio-triggered-buffer.ko\n  AUTOLOAD:=$(call AutoLoad,55,industrialio-triggered-buffer)\nendef\n\ndefine KernelPackage/industrialio-triggered-buffer/description\n Provides helper functions for setting up triggered buffers.\nendef\n\n$(eval $(call KernelPackage,industrialio-triggered-buffer))\n\n\ndefine KernelPackage/iio-ad799x\n  SUBMENU:=$(IIO_MENU)\n  DEPENDS:=+kmod-i2c-core +kmod-iio-core +kmod-industrialio-triggered-buffer\n  TITLE:=Analog Devices AD799x ADC driver\n  KCONFIG:= \\\n\tCONFIG_AD799X_RING_BUFFER=y \\\n\tCONFIG_AD799X\n  FILES:=$(LINUX_DIR)/drivers/iio/adc/ad799x.ko\n  AUTOLOAD:=$(call AutoLoad,56,ad799x)\nendef\n\ndefine KernelPackage/iio-ad799x/description\n support for Analog Devices:\n ad7991, ad7995, ad7999, ad7992, ad7993, ad7994, ad7997, ad7998\n i2c analog to digital converters (ADC).\nendef\n\n$(eval $(call KernelPackage,iio-ad799x))\n\ndefine KernelPackage/iio-ads1015\n  SUBMENU:=$(IIO_MENU)\n  DEPENDS:=+kmod-i2c-core +kmod-iio-core +kmod-regmap-i2c +kmod-industrialio-triggered-buffer\n  TITLE:=Texas Instruments ADS1015 ADC driver\n  KCONFIG:= CONFIG_TI_ADS1015\n  FILES:=$(LINUX_DIR)/drivers/iio/adc/ti-ads1015.ko\n  AUTOLOAD:=$(call AutoLoad,56,ti-ads1015)\nendef\n\ndefine KernelPackage/iio-ads1015/description\n This driver adds support for Texas Instruments ADS1015 and ADS1115 ADCs.\nendef\n\n$(eval $(call KernelPackage,iio-ads1015))\n\ndefine KernelPackage/iio-hmc5843\n  SUBMENU:=$(IIO_MENU)\n  DEPENDS:=+kmod-i2c-core +kmod-iio-core +kmod-regmap-i2c +kmod-industrialio-triggered-buffer\n  TITLE:=Honeywell HMC58x3 Magnetometer\n  KCONFIG:= CONFIG_SENSORS_HMC5843_I2C\n  FILES:= \\\n      $(LINUX_DIR)/drivers/iio/magnetometer/hmc5843_i2c.ko \\\n      $(LINUX_DIR)/drivers/iio/magnetometer/hmc5843_core.ko\n  AUTOLOAD:=$(call AutoLoad,56,hmc5843)\nendef\n\ndefine KernelPackage/iio-hmc5843/description\n  Honeywell HMC5843/5883/5883L 3-Axis Magnetometer\nendef\n\n$(eval $(call KernelPackage,iio-hmc5843))\n\ndefine KernelPackage/iio-bh1750\n  SUBMENU:=$(IIO_MENU)\n  DEPENDS:=+kmod-i2c-core +kmod-iio-core\n  TITLE:=ROHM BH1750 ambient light sensor\n  KCONFIG:= CONFIG_BH1750\n  FILES:=$(LINUX_DIR)/drivers/iio/light/bh1750.ko\n  AUTOLOAD:=$(call AutoLoad,56,bh1750)\nendef\ndefine KernelPackage/iio-bh1750/description\n  ROHM BH1750 ambient light sensor (i2c bus)\nendef\n$(eval $(call KernelPackage,iio-bh1750))\n\ndefine KernelPackage/iio-am2315\n  SUBMENU:=$(IIO_MENU)\n  DEPENDS:=+kmod-i2c-core +kmod-iio-core +kmod-industrialio-triggered-buffer\n  TITLE:=Asong AM2315 humidity/temperature sensor\n  KCONFIG:= CONFIG_AM2315\n  FILES:=$(LINUX_DIR)/drivers/iio/humidity/am2315.ko\n  AUTOLOAD:=$(call AutoLoad,56,am2315)\nendef\ndefine KernelPackage/iio-am2315/description\n  Aosong AM2315 humidity/temperature sensor (I2C bus)\nendef\n$(eval $(call KernelPackage,iio-am2315))\n\ndefine KernelPackage/iio-mxs-lradc\n  SUBMENU:=$(IIO_MENU)\n  DEPENDS:=@TARGET_mxs +kmod-iio-core +kmod-industrialio-triggered-buffer\n  TITLE:=Freescale i.MX23/i.MX28 LRADC ADC driver\n  KCONFIG:= \\\n\tCONFIG_MXS_LRADC_ADC\n  FILES:=$(LINUX_DIR)/drivers/iio/adc/mxs-lradc-adc.ko\n  AUTOLOAD:=$(call AutoLoad,56,mxs-lradc-adc)\nendef\n\ndefine KernelPackage/iio-mxs-lradc/description\n Support for Freescale's i.MX23/i.MX28 SoC internal Low-Resolution ADC\nendef\n\n$(eval $(call KernelPackage,iio-mxs-lradc))\n\ndefine KernelPackage/iio-dht11\n  SUBMENU:=$(IIO_MENU)\n  DEPENDS:=+kmod-iio-core @GPIO_SUPPORT @USES_DEVICETREE\n  TITLE:=DHT11 (and compatible) humidity and temperature sensors\n  KCONFIG:= \\\n\tCONFIG_DHT11\n  FILES:=$(LINUX_DIR)/drivers/iio/humidity/dht11.ko\n  AUTOLOAD:=$(call AutoLoad,56,dht11)\nendef\n\ndefine KernelPackage/iio-dht11/description\n support for DHT11 and DHT22 digitial humidity and temperature sensors\n attached at GPIO lines. You will need a custom device tree file to\n specify the GPIO line to use.\nendef\n\n$(eval $(call KernelPackage,iio-dht11))\n\n\ndefine KernelPackage/iio-bme680\n  SUBMENU:=$(IIO_MENU)\n  TITLE:=BME680 gas/humidity/pressure/temperature sensor\n  DEPENDS:=+kmod-iio-core +kmod-regmap-core\n  KCONFIG:=CONFIG_BME680\n  FILES:=$(LINUX_DIR)/drivers/iio/chemical/bme680_core.ko\nendef\n\ndefine KernelPackage/iio-bme680/description\n This driver adds support for Bosch Sensortec BME680 sensor with gas,\n humidity, pressure and temperatue sensing capability.\nendef\n\n$(eval $(call KernelPackage,iio-bme680))\n\ndefine KernelPackage/iio-bme680-i2c\n  SUBMENU:=$(IIO_MENU)\n  TITLE:=BME680 gas/humidity/pressure/temperature sensor (I2C)\n  DEPENDS:=+kmod-iio-bme680 +kmod-regmap-i2c\n  KCONFIG:=CONFIG_BME680_I2C\n  FILES:=$(LINUX_DIR)/drivers/iio/chemical/bme680_i2c.ko\n  AUTOLOAD:=$(call AutoProbe,bme680-i2c)\nendef\ndefine KernelPackage/iio-bme680-i2c/description\n This driver adds support for Bosch Sensortec's BME680 connected via I2C.\nendef\n\n$(eval $(call KernelPackage,iio-bme680-i2c))\n\ndefine KernelPackage/iio-bme680-spi\n  SUBMENU:=$(IIO_MENU)\n  TITLE:=BME680 gas/humidity/pressure/temperature sensor (SPI)\n  DEPENDS:=+kmod-iio-bme680 +kmod-regmap-spi\n  KCONFIG:=CONFIG_BME680_SPI\n  FILES:=$(LINUX_DIR)/drivers/iio/chemical/bme680_spi.ko\n  AUTOLOAD:=$(call AutoProbe,bme680-spi)\nendef\ndefine KernelPackage/iio-bme680-spi/description\n This driver adds support for Bosch Sensortec's BME680 connected via SPI.\nendef\n\n$(eval $(call KernelPackage,iio-bme680-spi))\n\n\ndefine KernelPackage/iio-bmp280\n  SUBMENU:=$(IIO_MENU)\n  TITLE:=BMP180/BMP280/BME280 pressure/temperatur sensor\n  DEPENDS:=+kmod-iio-core +kmod-regmap-core\n  KCONFIG:=CONFIG_BMP280\n  FILES:=$(LINUX_DIR)/drivers/iio/pressure/bmp280.ko\nendef\n\ndefine KernelPackage/iio-bmp280/description\n This driver adds support for Bosch Sensortec BMP180 and BMP280 pressure and\n temperature sensors. Also supports the BME280 with an additional humidity\n sensor channel.\nendef\n\n$(eval $(call KernelPackage,iio-bmp280))\n\n\ndefine KernelPackage/iio-bmp280-i2c\n  SUBMENU:=$(IIO_MENU)\n  TITLE:=BMP180/BMP280/BME280 pressure/temperatur sensor (I2C)\n  DEPENDS:=+kmod-iio-bmp280 +kmod-i2c-core +kmod-regmap-i2c\n  KCONFIG:=CONFIG_BMP280_I2C\n  FILES:=$(LINUX_DIR)/drivers/iio/pressure/bmp280-i2c.ko\n  AUTOLOAD:=$(call AutoProbe,bmp280-i2c)\nendef\ndefine KernelPackage/iio-bmp280-i2c/description\n This driver adds support for Bosch Sensortec's digital pressure and\n temperature sensor connected via I2C.\nendef\n\n$(eval $(call KernelPackage,iio-bmp280-i2c))\n\n\ndefine KernelPackage/iio-bmp280-spi\n  SUBMENU:=$(IIO_MENU)\n  TITLE:=BMP180/BMP280/BME280 pressure/temperatur sensor (SPI)\n  DEPENDS:=+kmod-iio-bmp280 +kmod-spi-bitbang\n  KCONFIG:=CONFIG_BMP280_SPI\n  FILES:=$(LINUX_DIR)/drivers/iio/pressure/bmp280-spi.ko\n  AUTOLOAD:=$(call AutoProbe,bmp280-spi)\nendef\ndefine KernelPackage/iio-bmp280-spi/description\n This driver adds support for Bosch Sensortec's digital pressure and\n temperature sensor connected via SPI.\nendef\n\n$(eval $(call KernelPackage,iio-bmp280-spi))\n\ndefine KernelPackage/iio-htu21\n  SUBMENU:=$(IIO_MENU)\n  DEPENDS:=+kmod-i2c-core +kmod-iio-core\n  TITLE:=HTU21 humidity & temperature sensor\n  KCONFIG:= \\\n       CONFIG_HTU21 \\\n       CONFIG_IIO_MS_SENSORS_I2C\n  FILES:= \\\n       $(LINUX_DIR)/drivers/iio/humidity/htu21.ko \\\n       $(LINUX_DIR)/drivers/iio/common/ms_sensors/ms_sensors_i2c.ko\n  AUTOLOAD:=$(call AutoLoad,56,htu21)\nendef\n\ndefine KernelPackage/iio-htu21/description\n support for the Measurement Specialties HTU21 humidity and\n temperature sensor.\n This driver is also used for MS8607 temperature, pressure & humidity\n sensor\nendef\n\n$(eval $(call KernelPackage,iio-htu21))\n\n\ndefine KernelPackage/iio-ccs811\n  SUBMENU:=$(IIO_MENU)\n  DEPENDS:=+kmod-i2c-core +kmod-iio-core +kmod-industrialio-triggered-buffer\n  TITLE:=AMS CCS811 VOC sensor\n  KCONFIG:= \\\n\tCONFIG_CCS811\n  FILES:= $(LINUX_DIR)/drivers/iio/chemical/ccs811.ko\n  AUTOLOAD:=$(call AutoLoad,56,ccs811)\nendef\n\ndefine KernelPackage/iio-ccs811/description\n  Support for the AMS CCS811 VOC (Volatile Organic Compounds) sensor\nendef\n\n$(eval $(call KernelPackage,iio-ccs811))\n\n\ndefine KernelPackage/iio-si7020\n  SUBMENU:=$(IIO_MENU)\n  DEPENDS:=+kmod-i2c-core +kmod-iio-core\n  TITLE:=Silicon Labs Si7020 sensor\n  KCONFIG:= CONFIG_SI7020\n  FILES:=$(LINUX_DIR)/drivers/iio/humidity/si7020.ko\n  AUTOLOAD:=$(call AutoLoad,56,si7020)\nendef\n\ndefine KernelPackage/iio-si7020/description\n Support for Silicon Labs Si7020 family of relative humidity and\n temperature sensors connected via I2C. Following models are usable:\n Si7013, Si7020, Si7021, Hoperf TH06.\nendef\n\n$(eval $(call KernelPackage,iio-si7020))\n\n\ndefine KernelPackage/iio-st_accel\n  SUBMENU:=$(IIO_MENU)\n  TITLE:=STMicroelectronics accelerometer 3-Axis Driver\n  DEPENDS:=+kmod-iio-core +kmod-regmap-core +kmod-industrialio-triggered-buffer\n  KCONFIG:= \\\n\tCONFIG_IIO_ST_ACCEL_3AXIS \\\n\tCONFIG_IIO_ST_SENSORS_CORE\n  FILES:= \\\n\t$(LINUX_DIR)/drivers/iio/accel/st_accel.ko \\\n\t$(LINUX_DIR)/drivers/iio/common/st_sensors/st_sensors.ko\nendef\n\ndefine KernelPackage/iio-st_accel/description\n This package adds support for STMicroelectronics accelerometers:\n  LSM303DLH, LSM303DLHC, LIS3DH, LSM330D, LSM330DL, LSM330DLC,\n  LIS331DLH, LSM303DL, LSM303DLM, LSM330, LIS2DH12, H3LIS331DL,\n  LNG2DM, LIS3DE, LIS2DE12\nendef\n\n$(eval $(call KernelPackage,iio-st_accel))\n\n\ndefine KernelPackage/iio-st_accel-i2c\n  SUBMENU:=$(IIO_MENU)\n  TITLE:=STMicroelectronics accelerometer 3-Axis Driver (I2C)\n  DEPENDS:=+kmod-iio-st_accel +kmod-i2c-core +kmod-regmap-i2c\n  KCONFIG:= CONFIG_IIO_ST_ACCEL_I2C_3AXIS\n  FILES:= \\\n\t$(LINUX_DIR)/drivers/iio/accel/st_accel_i2c.ko \\\n\t$(LINUX_DIR)/drivers/iio/common/st_sensors/st_sensors_i2c.ko\n  AUTOLOAD:=$(call AutoLoad,56,st_accel_i2c)\nendef\n\ndefine KernelPackage/iio-st_accel-i2c/description\n This package adds support for STMicroelectronics I2C based accelerometers\nendef\n\n$(eval $(call KernelPackage,iio-st_accel-i2c))\n\n\ndefine KernelPackage/iio-st_accel-spi\n  SUBMENU:=$(IIO_MENU)\n  TITLE:=STMicroelectronics accelerometer 3-Axis Driver (SPI)\n  DEPENDS:=+kmod-iio-st_accel +kmod-regmap-spi\n  KCONFIG:= CONFIG_IIO_ST_ACCEL_SPI_3AXIS\n  FILES:= \\\n\t$(LINUX_DIR)/drivers/iio/accel/st_accel_spi.ko \\\n\t$(LINUX_DIR)/drivers/iio/common/st_sensors/st_sensors_spi.ko\n  AUTOLOAD:=$(call AutoLoad,56,st_accel_spi)\nendef\n\ndefine KernelPackage/iio-st_accel-spi/description\n This package adds support for STMicroelectronics SPI based accelerometers\nendef\n\n$(eval $(call KernelPackage,iio-st_accel-spi))\n\n\ndefine KernelPackage/iio-lsm6dsx\n  SUBMENU:=$(IIO_MENU)\n  DEPENDS:=+kmod-iio-core +kmod-iio-kfifo-buf +kmod-regmap-core\n  TITLE:=ST LSM6DSx driver for IMU MEMS sensors\n  KCONFIG:=CONFIG_IIO_ST_LSM6DSX\n  FILES:=$(LINUX_DIR)/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx.ko\n  AUTOLOAD:=$(call AutoProbe,st_lsm6dsx)\nendef\n\ndefine KernelPackage/iio-lsm6dsx/description\n Support for the ST LSM6DSx and related IMU MEMS sensors.\nendef\n\n$(eval $(call KernelPackage,iio-lsm6dsx))\n\n\ndefine KernelPackage/iio-lsm6dsx-i2c\n  SUBMENU:=$(IIO_MENU)\n  DEPENDS:=+kmod-iio-lsm6dsx +kmod-i2c-core +kmod-regmap-i2c\n  TITLE:=ST LSM6DSx driver for IMU MEMS sensors (I2C)\n  KCONFIG:=CONFIG_IIO_ST_LSM6DSX\n  FILES:=$(LINUX_DIR)/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_i2c.ko\n  AUTOLOAD:=$(call AutoProbe,st_lsm6dsx-i2c)\nendef\n\ndefine KernelPackage/iio-lsm6dsx-i2c/description\n Support for the ST LSM6DSx and related IMU MEMS I2C sensors.\nendef\n\n$(eval $(call KernelPackage,iio-lsm6dsx-i2c))\n\n\ndefine KernelPackage/iio-lsm6dsx-spi\n  SUBMENU:=$(IIO_MENU)\n  DEPENDS:=+kmod-iio-lsm6dsx +kmod-regmap-spi\n  TITLE:=ST LSM6DSx driver for IMU MEMS sensors (SPI)\n  KCONFIG:=CONFIG_IIO_ST_LSM6DSX\n  FILES:=$(LINUX_DIR)/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_spi.ko\n  AUTOLOAD:=$(call AutoProbe,st_lsm6dsx-spi)\nendef\n\ndefine KernelPackage/iio-lsm6dsx-spi/description\n Support for the ST LSM6DSx and related IMU MEMS SPI sensors.\nendef\n\n$(eval $(call KernelPackage,iio-lsm6dsx-spi))\n\n\ndefine KernelPackage/iio-sps30\n  SUBMENU:=$(IIO_MENU)\n  DEPENDS:=+kmod-i2c-core +kmod-iio-core +kmod-industrialio-triggered-buffer +kmod-lib-crc8\n  TITLE:=Sensirion SPS30 particulate matter sensor\n  KCONFIG:=CONFIG_SPS30\n  FILES:=$(LINUX_DIR)/drivers/iio/chemical/sps30.ko\n  AUTOLOAD:=$(call AutoProbe,sps30)\nendef\n\ndefine KernelPackage/iio-sps30/description\n Support for the Sensirion SPS30 particulate matter sensor.\nendef\n\n$(eval $(call KernelPackage,iio-sps30))\n\n\ndefine KernelPackage/iio-tsl4531\n  SUBMENU:=$(IIO_MENU)\n  DEPENDS:=+kmod-i2c-core +kmod-iio-core\n  TITLE:=TAOS TSL4531 ambient light sensor\n  KCONFIG:= CONFIG_TSL4531\n  FILES:=$(LINUX_DIR)/drivers/iio/light/tsl4531.ko\n  AUTOLOAD:=$(call AutoLoad,56,tsl4531)\nendef\n\ndefine KernelPackage/iio-tsl4531/description\n Support for TAOS TSL4531x family of ambient light sensors\n connected via I2C. Following models are usable:\n TSL45311, TSL45313, TSL45315, TSL45317.\nendef\n\n$(eval $(call KernelPackage,iio-tsl4531))\n\n\ndefine KernelPackage/iio-fxas21002c\n  SUBMENU:=$(IIO_MENU)\n  TITLE:=Freescale FXAS21002C 3-axis gyro driver\n  DEPENDS:=+kmod-iio-core +kmod-regmap-core +kmod-industrialio-triggered-buffer\n  KCONFIG:= CONFIG_FXAS21002C\n  FILES:=$(LINUX_DIR)/drivers/iio/gyro/fxas21002c_core.ko\n  AUTOLOAD:=$(call AutoLoad,56,fxas21002c)\nendef\n\ndefine KernelPackage/iio-fxas21002c/description\n Support for Freescale FXAS21002C 3-axis gyro.\nendef\n\n$(eval $(call KernelPackage,iio-fxas21002c))\n\n\ndefine KernelPackage/iio-fxas21002c-i2c\n  SUBMENU:=$(IIO_MENU)\n  TITLE:=Freescale FXAS21002C 3-axis gyro driver (I2C)\n  DEPENDS:=+kmod-iio-fxas21002c +kmod-i2c-core +kmod-regmap-i2c\n  KCONFIG:= CONFIG_FXAS21002C_I2C\n  FILES:=$(LINUX_DIR)/drivers/iio/gyro/fxas21002c_i2c.ko\n  AUTOLOAD:=$(call AutoLoad,56,fxas21002c_i2c)\nendef\n\ndefine KernelPackage/iio-fxas21002c-i2c/description\n Support for Freescale FXAS21002C 3-axis gyro\n connected via I2C.\nendef\n\n\n$(eval $(call KernelPackage,iio-fxas21002c-i2c))\n\ndefine KernelPackage/iio-fxas21002c-spi\n  SUBMENU:=$(IIO_MENU)\n  DEPENDS:=+kmod-iio-fxas21002c +kmod-regmap-spi\n  TITLE:=Freescale FXAS21002C 3-axis gyro driver (SPI)\n  KCONFIG:= CONFIG_FXAS21002C_SPI\n  FILES:=$(LINUX_DIR)/drivers/iio/gyro/fxas21002c_spi.ko\n  AUTOLOAD:=$(call AutoLoad,56,fxas21002c_spi)\nendef\n\ndefine KernelPackage/iio-fxas21002c-spi/description\n Support for Freescale FXAS21002C 3-axis gyro\n connected via SPI.\nendef\n\n$(eval $(call KernelPackage,iio-fxas21002c-spi))\n\n\ndefine KernelPackage/iio-fxos8700\n  SUBMENU:=$(IIO_MENU)\n  TITLE:=Freescale FXOS8700 3-axis accelerometer driver\n  DEPENDS:=+kmod-iio-core +kmod-regmap-core\n  KCONFIG:= CONFIG_FXOS8700\n  FILES:=$(LINUX_DIR)/drivers/iio/imu/fxos8700_core.ko\n  AUTOLOAD:=$(call AutoLoad,56,fxos8700)\nendef\n\ndefine KernelPackage/iio-fxos8700/description\n Support for Freescale FXOS8700 3-axis accelerometer.\nendef\n\n$(eval $(call KernelPackage,iio-fxos8700))\n\n\ndefine KernelPackage/iio-fxos8700-i2c\n  SUBMENU:=$(IIO_MENU)\n  TITLE:=Freescale FXOS8700 3-axis acceleromter driver (I2C)\n  DEPENDS:=+kmod-iio-fxos8700 +kmod-i2c-core +kmod-regmap-i2c\n  KCONFIG:= CONFIG_FXOS8700_I2C\n  FILES:=$(LINUX_DIR)/drivers/iio/imu/fxos8700_i2c.ko\n  AUTOLOAD:=$(call AutoLoad,56,fxos8700_i2c)\nendef\n\ndefine KernelPackage/iio-fxos8700-i2c/description\n Support for Freescale FXOS8700 3-axis accelerometer\n connected via I2C.\nendef\n\n\n$(eval $(call KernelPackage,iio-fxos8700-i2c))\n\ndefine KernelPackage/iio-fxos8700-spi\n  SUBMENU:=$(IIO_MENU)\n  DEPENDS:=+kmod-iio-fxos8700 +kmod-regmap-spi\n  TITLE:=Freescale FXOS8700 3-axis accelerometer driver (SPI)\n  KCONFIG:= CONFIG_FXOS8700_SPI\n  FILES:=$(LINUX_DIR)/drivers/iio/imu/fxos8700_spi.ko\n  AUTOLOAD:=$(call AutoLoad,56,fxos8700_spi)\nendef\n\ndefine KernelPackage/iio-fxos8700-spi/description\n Support for Freescale FXOS8700 3-axis accelerometer\n connected via SPI.\nendef\n\n$(eval $(call KernelPackage,iio-fxos8700-spi))\n"
  },
  {
    "path": "package/kernel/linux/modules/input.mk",
    "content": "#\n# Copyright (C) 2006-2013 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\nINPUT_MODULES_MENU:=Input modules\n\ndefine KernelPackage/hid\n  SUBMENU:=$(INPUT_MODULES_MENU)\n  TITLE:=HID Devices\n  DEPENDS:=+kmod-input-core +kmod-input-evdev\n  KCONFIG:=CONFIG_HID CONFIG_HIDRAW=y CONFIG_HID_BATTERY_STRENGTH=y\n  FILES:=$(LINUX_DIR)/drivers/hid/hid.ko\n  AUTOLOAD:=$(call AutoLoad,61,hid)\nendef\n\ndefine KernelPackage/hid/description\n Kernel modules for HID devices\nendef\n\n$(eval $(call KernelPackage,hid))\n\ndefine KernelPackage/hid-generic\n  SUBMENU:=$(INPUT_MODULES_MENU)\n  TITLE:=Generic HID device support\n  DEPENDS:=+kmod-hid\n  KCONFIG:=CONFIG_HID_GENERIC\n  FILES:=$(LINUX_DIR)/drivers/hid/hid-generic.ko\n  AUTOLOAD:=$(call AutoProbe,hid-generic)\nendef\n\ndefine KernelPackage/hid/description\n Kernel modules for generic HID device (e.g. keyboards and mice) support\nendef\n\n$(eval $(call KernelPackage,hid-generic))\n\ndefine KernelPackage/input-core\n  SUBMENU:=$(INPUT_MODULES_MENU)\n  TITLE:=Input device core\n  KCONFIG:=CONFIG_INPUT\n  FILES:=$(LINUX_DIR)/drivers/input/input-core.ko\nendef\n\ndefine KernelPackage/input-core/description\n Kernel modules for support of input device\nendef\n\n$(eval $(call KernelPackage,input-core))\n\n\ndefine KernelPackage/input-evdev\n  SUBMENU:=$(INPUT_MODULES_MENU)\n  TITLE:=Input event device\n  DEPENDS:=+kmod-input-core\n  KCONFIG:=CONFIG_INPUT_EVDEV\n  FILES:=$(LINUX_DIR)/drivers/input/evdev.ko\n  AUTOLOAD:=$(call AutoLoad,60,evdev)\nendef\n\ndefine KernelPackage/input-evdev/description\n Kernel modules for support of input device events\nendef\n\n$(eval $(call KernelPackage,input-evdev))\n\n\ndefine KernelPackage/input-gpio-keys\n  SUBMENU:=$(INPUT_MODULES_MENU)\n  TITLE:=GPIO key support\n  DEPENDS:= @GPIO_SUPPORT +kmod-input-core\n  KCONFIG:= \\\n\tCONFIG_KEYBOARD_GPIO \\\n\tCONFIG_INPUT_KEYBOARD=y\n  FILES:=$(LINUX_DIR)/drivers/input/keyboard/gpio_keys.ko\n  AUTOLOAD:=$(call AutoProbe,gpio_keys,1)\nendef\n\ndefine KernelPackage/input-gpio-keys/description\n This driver implements support for buttons connected\n to GPIO pins of various CPUs (and some other chips).\n\n See also gpio-button-hotplug which is an alternative, lower overhead\n implementation that generates uevents instead of kernel input events.\nendef\n\n$(eval $(call KernelPackage,input-gpio-keys))\n\n\ndefine KernelPackage/input-gpio-keys-polled\n  SUBMENU:=$(INPUT_MODULES_MENU)\n  TITLE:=Polled GPIO key support\n  DEPENDS:=@GPIO_SUPPORT +kmod-input-polldev\n  KCONFIG:= \\\n\tCONFIG_KEYBOARD_GPIO_POLLED \\\n\tCONFIG_INPUT_KEYBOARD=y\n  FILES:=$(LINUX_DIR)/drivers/input/keyboard/gpio_keys_polled.ko\n  AUTOLOAD:=$(call AutoProbe,gpio_keys_polled,1)\nendef\n\ndefine KernelPackage/input-gpio-keys-polled/description\n Kernel module for support polled GPIO keys input device\n\n See also gpio-button-hotplug which is an alternative, lower overhead\n implementation that generates uevents instead of kernel input events.\nendef\n\n$(eval $(call KernelPackage,input-gpio-keys-polled))\n\n\ndefine KernelPackage/input-gpio-encoder\n  SUBMENU:=$(INPUT_MODULES_MENU)\n  TITLE:=GPIO rotary encoder\n  DEPENDS:=@GPIO_SUPPORT +kmod-input-core\n  KCONFIG:=CONFIG_INPUT_GPIO_ROTARY_ENCODER\n  FILES:=$(LINUX_DIR)/drivers/input/misc/rotary_encoder.ko\n  AUTOLOAD:=$(call AutoProbe,rotary_encoder)\nendef\n\ndefine KernelPackage/input-gpio-encoder/description\n Kernel module to use rotary encoders connected to GPIO pins\nendef\n\n$(eval $(call KernelPackage,input-gpio-encoder))\n\n\ndefine KernelPackage/input-joydev\n  SUBMENU:=$(INPUT_MODULES_MENU)\n  TITLE:=Joystick device support\n  DEPENDS:=+kmod-input-core\n  KCONFIG:=CONFIG_INPUT_JOYDEV\n  FILES:=$(LINUX_DIR)/drivers/input/joydev.ko\n  AUTOLOAD:=$(call AutoProbe,joydev)\nendef\n\ndefine KernelPackage/input-joydev/description\n Kernel module for joystick support\nendef\n\n$(eval $(call KernelPackage,input-joydev))\n\n\ndefine KernelPackage/input-polldev\n  SUBMENU:=$(INPUT_MODULES_MENU)\n  TITLE:=Polled Input device support\n  DEPENDS:=+kmod-input-core\n  KCONFIG:=CONFIG_INPUT_POLLDEV\n  FILES:=$(LINUX_DIR)/drivers/input/input-polldev.ko\nendef\n\ndefine KernelPackage/input-polldev/description\n Kernel module for support of polled input devices\nendef\n\n$(eval $(call KernelPackage,input-polldev))\n\n\ndefine KernelPackage/input-matrixkmap\n  SUBMENU:=$(INPUT_MODULES_MENU)\n  TITLE:=Input matrix devices support\n  DEPENDS:=+kmod-input-core\n  KCONFIG:=CONFIG_INPUT_MATRIXKMAP\n  FILES:=$(LINUX_DIR)/drivers/input/matrix-keymap.ko\n  AUTOLOAD:=$(call AutoProbe,matrix-keymap)\nendef\n\ndefine KernelPackage/input-matrixkmap/description\n Kernel module support for input matrix devices\nendef\n\n$(eval $(call KernelPackage,input-matrixkmap))\n\n\ndefine KernelPackage/input-touchscreen-ads7846\n  SUBMENU:=$(INPUT_MODULES_MENU)\n  TITLE:=ADS7846/TSC2046/AD7873 and AD(S)7843 based touchscreens\n  DEPENDS:=+kmod-hwmon-core +kmod-input-core +kmod-spi-bitbang\n  KCONFIG:= \\\n\tCONFIG_INPUT_TOUCHSCREEN=y \\\n\tCONFIG_TOUCHSCREEN_PROPERTIES=y@lt5.13 \\\n\tCONFIG_TOUCHSCREEN_ADS7846\n  FILES:=$(LINUX_DIR)/drivers/input/touchscreen/ads7846.ko \\\n\t$(LINUX_DIR)/drivers/input/touchscreen/of_touchscreen.ko@lt5.13\n  AUTOLOAD:=$(call AutoProbe,ads7846)\nendef\n\ndefine KernelPackage/input-touchscreen-ads7846/description\n  Kernel module for ADS7846/TSC2046/AD7873 and AD(S)7843 based touchscreens\nendef\n\n$(eval $(call KernelPackage,input-touchscreen-ads7846))\n\n\ndefine KernelPackage/keyboard-imx\n  SUBMENU:=$(INPUT_MODULES_MENU)\n  TITLE:=IMX keypad support\n  DEPENDS:=@(TARGET_mxs||TARGET_imx) +kmod-input-matrixkmap\n  KCONFIG:= \\\n\tCONFIG_KEYBOARD_IMX \\\n\tCONFIG_INPUT_KEYBOARD=y\n  FILES:=$(LINUX_DIR)/drivers/input/keyboard/imx_keypad.ko\n  AUTOLOAD:=$(call AutoProbe,imx_keypad)\nendef\n\ndefine KernelPackage/keyboard-imx/description\n Enable support for IMX keypad port.\nendef\n\n$(eval $(call KernelPackage,keyboard-imx))\n\n\ndefine KernelPackage/input-uinput\n  SUBMENU:=$(INPUT_MODULES_MENU)\n  TITLE:=user input module\n  DEPENDS:=+kmod-input-core\n  KCONFIG:= \\\n\tCONFIG_INPUT_MISC=y \\\n\tCONFIG_INPUT_UINPUT\n  FILES:=$(LINUX_DIR)/drivers/input/misc/uinput.ko\n  AUTOLOAD:=$(call AutoProbe,uinput)\nendef\n\ndefine KernelPackage/input-uinput/description\n  user input modules needed for bluez\nendef\n\n$(eval $(call KernelPackage,input-uinput))\n"
  },
  {
    "path": "package/kernel/linux/modules/leds.mk",
    "content": "#\n# Copyright (C) 2006-2011 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\nLEDS_MENU:=LED modules\n\ndefine KernelPackage/leds-gpio\n  SUBMENU:=$(LEDS_MENU)\n  TITLE:=GPIO LED support\n  DEPENDS:= @GPIO_SUPPORT\n  KCONFIG:=CONFIG_LEDS_GPIO\n  FILES:=$(LINUX_DIR)/drivers/leds/leds-gpio.ko\n  AUTOLOAD:=$(call AutoLoad,60,leds-gpio,1)\nendef\n\ndefine KernelPackage/leds-gpio/description\n Kernel module for LEDs on GPIO lines\nendef\n\n$(eval $(call KernelPackage,leds-gpio))\n\nLED_TRIGGER_DIR=$(LINUX_DIR)/drivers/leds/trigger\n\ndefine KernelPackage/ledtrig-activity\n  SUBMENU:=$(LEDS_MENU)\n  TITLE:=LED Activity Trigger\n  KCONFIG:=CONFIG_LEDS_TRIGGER_ACTIVITY\n  FILES:=$(LED_TRIGGER_DIR)/ledtrig-activity.ko\n  AUTOLOAD:=$(call AutoLoad,50,ledtrig-activity)\nendef\n\ndefine KernelPackage/ledtrig-activity/description\n Kernel module that allows LEDs to blink based on system load\nendef\n\n$(eval $(call KernelPackage,ledtrig-activity))\n\ndefine KernelPackage/ledtrig-audio\n  SUBMENU:=$(LEDS_MENU)\n  TITLE:=LED Audio Mute Trigger\n  KCONFIG:=CONFIG_LEDS_TRIGGER_AUDIO\n  FILES:=$(LED_TRIGGER_DIR)/ledtrig-audio.ko\n  AUTOLOAD:=$(call AutoLoad,50,ledtrig-audio)\nendef\n\ndefine KernelPackage/ledtrig-audio/description\n Kernel module that allows LEDs to be controlled by audio drivers\n to follow audio mute and mic-mute changes.\nendef\n\n$(eval $(call KernelPackage,ledtrig-audio))\n\ndefine KernelPackage/ledtrig-gpio\n  SUBMENU:=$(LEDS_MENU)\n  TITLE:=LED GPIO Trigger\n  KCONFIG:=CONFIG_LEDS_TRIGGER_GPIO\n  FILES:=$(LED_TRIGGER_DIR)/ledtrig-gpio.ko\n  AUTOLOAD:=$(call AutoLoad,50,ledtrig-gpio)\nendef\n\ndefine KernelPackage/ledtrig-gpio/description\n Kernel module that allows LEDs to be controlled by gpio events\nendef\n\n$(eval $(call KernelPackage,ledtrig-gpio))\n\n\ndefine KernelPackage/ledtrig-transient\n  SUBMENU:=$(LEDS_MENU)\n  TITLE:=LED Transient Trigger\n  KCONFIG:=CONFIG_LEDS_TRIGGER_TRANSIENT\n  FILES:=$(LED_TRIGGER_DIR)/ledtrig-transient.ko\n  AUTOLOAD:=$(call AutoLoad,50,ledtrig-transient,1)\nendef\n\ndefine KernelPackage/ledtrig-transient/description\n Kernel module that allows LEDs one time activation of a transient state.\nendef\n\n$(eval $(call KernelPackage,ledtrig-transient))\n\n\ndefine KernelPackage/ledtrig-oneshot\n  SUBMENU:=$(LEDS_MENU)\n  TITLE:=LED One-Shot Trigger\n  KCONFIG:=CONFIG_LEDS_TRIGGER_ONESHOT\n  FILES:=$(LED_TRIGGER_DIR)/ledtrig-oneshot.ko\n  AUTOLOAD:=$(call AutoLoad,50,ledtrig-oneshot)\nendef\n\ndefine KernelPackage/ledtrig-oneshot/description\n Kernel module that allows LEDs to be triggered by sporadic events in\n one-shot pulses\nendef\n\n$(eval $(call KernelPackage,ledtrig-oneshot))\n\n\ndefine KernelPackage/ledtrig-pattern\n  SUBMENU:=$(LEDS_MENU)\n  TITLE:=LED Pattern Trigger\n  KCONFIG:=CONFIG_LEDS_TRIGGER_PATTERN\n  FILES:=$(LED_TRIGGER_DIR)/ledtrig-pattern.ko\n  AUTOLOAD:=$(call AutoLoad,50,ledtrig-pattern)\nendef\n\ndefine KernelPackage/ledtrig-pattern/description\n This allows LEDs to be controlled by a software or hardware pattern\n which is a series of tuples, of brightness and duration (ms).\nendef\n\n$(eval $(call KernelPackage,ledtrig-pattern))\n\n\ndefine KernelPackage/leds-apu\n  SUBMENU:=$(LEDS_MENU)\n  TITLE:=PC Engines APU1 LED support\n  DEPENDS:= @GPIO_SUPPORT @TARGET_x86\n  KCONFIG:=CONFIG_LEDS_APU\n  FILES:=$(LINUX_DIR)/drivers/leds/leds-apu.ko\n  AUTOLOAD:=$(call AutoLoad,60,leds-apu,1)\nendef\n\ndefine KernelPackage/leds-apu/description\n  Driver for the PC Engines APU1 LEDs.\nendef\n\n$(eval $(call KernelPackage,leds-apu))\n\n\ndefine KernelPackage/leds-pca963x\n  SUBMENU:=$(LEDS_MENU)\n  TITLE:=PCA963x LED support\n  DEPENDS:=+kmod-i2c-core\n  KCONFIG:=CONFIG_LEDS_PCA963X\n  FILES:=$(LINUX_DIR)/drivers/leds/leds-pca963x.ko\n  AUTOLOAD:=$(call AutoLoad,60,leds-pca963x,1)\nendef\n\ndefine KernelPackage/leds-pca963x/description\n Driver for the NXP PCA963x I2C LED controllers.\nendef\n\n$(eval $(call KernelPackage,leds-pca963x))\n\n\ndefine KernelPackage/leds-pwm\n  SUBMENU:=$(LEDS_MENU)\n  TITLE:=PWM driven LED Support\n  KCONFIG:=CONFIG_LEDS_PWM\n  DEPENDS:= @PWM_SUPPORT\n  FILES:=$(LINUX_DIR)/drivers/leds/leds-pwm.ko\n  AUTOLOAD:=$(call AutoLoad,60,leds-pwm,1)\nendef\n\ndefine KernelPackage/leds-pwm/description\n This option enables support for pwm driven LEDs\nendef\n\n$(eval $(call KernelPackage,leds-pwm))\n\n\ndefine KernelPackage/leds-tlc591xx\n  SUBMENU:=$(LEDS_MENU)\n  TITLE:=LED driver for TLC59108 and TLC59116 controllers\n  DEPENDS:=+kmod-i2c-core +kmod-regmap-i2c\n  KCONFIG:=CONFIG_LEDS_TLC591XX\n  FILES:=$(LINUX_DIR)/drivers/leds/leds-tlc591xx.ko\n  AUTOLOAD:=$(call AutoLoad,60,leds-tlc591xx,1)\nendef\n\ndefine KernelPackage/leds-tlc591xx/description\n This option enables support for Texas Instruments TLC59108\n and TLC59116 LED controllers.\nendef\n\n$(eval $(call KernelPackage,leds-tlc591xx))\n\n\ndefine KernelPackage/leds-uleds\n  SUBMENU:=$(LEDS_MENU)\n  TITLE:=Userspace LEDs\n  KCONFIG:=CONFIG_LEDS_USER\n  FILES:=$(LINUX_DIR)/drivers/leds/uleds.ko\n  AUTOLOAD:=$(call AutoLoad,60,uleds,1)\nendef\n\ndefine KernelPackage/leds-uleds/description\n This option enables support for userspace LEDs.\nendef\n\n$(eval $(call KernelPackage,leds-uleds))\n\n\ndefine KernelPackage/input-leds\n  SUBMENU:=$(LEDS_MENU)\n  TITLE:=Input device LED support\n  DEPENDS:=+kmod-input-core\n  KCONFIG:=CONFIG_INPUT_LEDS\n  FILES:=$(LINUX_DIR)/drivers/input/input-leds.ko\n  AUTOLOAD:=$(call AutoLoad,50,input-leds,1)\nendef\n\ndefine KernelPackage/input-leds/description\n Provides support for LEDs on input devices- for example,\n keyboard num/caps/scroll lock.\nendef\n\n$(eval $(call KernelPackage,input-leds))\n"
  },
  {
    "path": "package/kernel/linux/modules/lib.mk",
    "content": "#\n# Copyright (C) 2011 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\nLIB_MENU:=Libraries\n\ndefine KernelPackage/lib-crc-ccitt\n  SUBMENU:=$(LIB_MENU)\n  TITLE:=CRC-CCITT support\n  KCONFIG:=CONFIG_CRC_CCITT\n  FILES:=$(LINUX_DIR)/lib/crc-ccitt.ko\n  AUTOLOAD:=$(call AutoProbe,crc-ccitt)\nendef\n\ndefine KernelPackage/lib-crc-ccitt/description\n Kernel module for CRC-CCITT support\nendef\n\n$(eval $(call KernelPackage,lib-crc-ccitt))\n\n\ndefine KernelPackage/lib-crc-itu-t\n  SUBMENU:=$(LIB_MENU)\n  TITLE:=CRC ITU-T V.41 support\n  KCONFIG:=CONFIG_CRC_ITU_T\n  FILES:=$(LINUX_DIR)/lib/crc-itu-t.ko\n  AUTOLOAD:=$(call AutoProbe,crc-itu-t)\nendef\n\ndefine KernelPackage/lib-crc-itu-t/description\n Kernel module for CRC ITU-T V.41 support\nendef\n\n$(eval $(call KernelPackage,lib-crc-itu-t))\n\n\ndefine KernelPackage/lib-crc7\n  SUBMENU:=$(LIB_MENU)\n  TITLE:=CRC7 support\n  KCONFIG:=CONFIG_CRC7\n  FILES:=$(LINUX_DIR)/lib/crc7.ko\n  AUTOLOAD:=$(call AutoProbe,crc7)\nendef\n\ndefine KernelPackage/lib-crc7/description\n Kernel module for CRC7 support\nendef\n\n$(eval $(call KernelPackage,lib-crc7))\n\n\ndefine KernelPackage/lib-crc8\n  SUBMENU:=$(LIB_MENU)\n  TITLE:=CRC8 support\n  KCONFIG:=CONFIG_CRC8\n  FILES:=$(LINUX_DIR)/lib/crc8.ko\n  AUTOLOAD:=$(call AutoProbe,crc8)\nendef\n\ndefine KernelPackage/lib-crc8/description\n Kernel module for CRC8 support\nendef\n\n$(eval $(call KernelPackage,lib-crc8))\n\n\ndefine KernelPackage/lib-crc16\n  SUBMENU:=$(LIB_MENU)\n  TITLE:=CRC16 support\n  KCONFIG:=CONFIG_CRC16\n  FILES:=$(LINUX_DIR)/lib/crc16.ko\n  AUTOLOAD:=$(call AutoLoad,20,crc16,1)\nendef\n\ndefine KernelPackage/lib-crc16/description\n Kernel module for CRC16 support\nendef\n\n$(eval $(call KernelPackage,lib-crc16))\n\n\ndefine KernelPackage/lib-crc32c\n  SUBMENU:=$(LIB_MENU)\n  TITLE:=CRC32 support\n  KCONFIG:=CONFIG_LIBCRC32C\n  DEPENDS:=+kmod-crypto-crc32c\n  FILES:=$(LINUX_DIR)/lib/libcrc32c.ko\n  AUTOLOAD:=$(call AutoProbe,libcrc32c)\nendef\n\ndefine KernelPackage/lib-crc32c/description\n Kernel module for CRC32 support\nendef\n\n$(eval $(call KernelPackage,lib-crc32c))\n\n\ndefine KernelPackage/lib-lzo\n  SUBMENU:=$(LIB_MENU)\n  TITLE:=LZO support\n  DEPENDS:=+kmod-crypto-acompress\n  KCONFIG:= \\\n\tCONFIG_CRYPTO_LZO \\\n\tCONFIG_LZO_COMPRESS \\\n\tCONFIG_LZO_DECOMPRESS\n  HIDDEN:=1\n  FILES:= \\\n\t$(LINUX_DIR)/crypto/lzo.ko \\\n\t$(LINUX_DIR)/crypto/lzo-rle.ko \\\n\t$(LINUX_DIR)/lib/lzo/lzo_compress.ko \\\n\t$(LINUX_DIR)/lib/lzo/lzo_decompress.ko\n  AUTOLOAD:=$(call AutoProbe,lzo lzo-rle lzo_compress lzo_decompress)\nendef\n\ndefine KernelPackage/lib-lzo/description\n Kernel module for LZO compression/decompression support\nendef\n\n$(eval $(call KernelPackage,lib-lzo))\n\n\ndefine KernelPackage/lib-zstd\n  SUBMENU:=$(LIB_MENU)\n  TITLE:=ZSTD support\n  DEPENDS:=+kmod-crypto-acompress\n  KCONFIG:= \\\n\tCONFIG_CRYPTO_ZSTD \\\n\tCONFIG_ZSTD_COMPRESS \\\n\tCONFIG_ZSTD_DECOMPRESS \\\n\tCONFIG_XXHASH\n  FILES:= \\\n\t$(LINUX_DIR)/crypto/zstd.ko \\\n\t$(LINUX_DIR)/lib/xxhash.ko \\\n\t$(LINUX_DIR)/lib/zstd/zstd_compress.ko \\\n\t$(LINUX_DIR)/lib/zstd/zstd_decompress.ko\n  AUTOLOAD:=$(call AutoProbe,xxhash zstd zstd_compress zstd_decompress)\nendef\n\ndefine KernelPackage/lib-zstd/description\n Kernel module for ZSTD compression/decompression support\nendef\n\n$(eval $(call KernelPackage,lib-zstd))\n\n\ndefine KernelPackage/lib-lz4\n  SUBMENU:=$(LIB_MENU)\n  TITLE:=LZ4 support\n  DEPENDS:=+kmod-crypto-acompress\n  KCONFIG:= \\\n\tCONFIG_CRYPTO_LZ4 \\\n\tCONFIG_LZ4_COMPRESS \\\n\tCONFIG_LZ4_DECOMPRESS\n  FILES:= \\\n\t$(LINUX_DIR)/crypto/lz4.ko \\\n\t$(LINUX_DIR)/lib/lz4/lz4_compress.ko \\\n\t$(LINUX_DIR)/lib/lz4/lz4_decompress.ko\n  AUTOLOAD:=$(call AutoProbe,lz4 lz4_compress lz4_decompress)\nendef\n\ndefine KernelPackage/lib-lz4/description\n Kernel module for LZ4 compression/decompression support\nendef\n\n$(eval $(call KernelPackage,lib-lz4))\n\n\ndefine KernelPackage/lib-raid6\n  SUBMENU:=$(LIB_MENU)\n  TITLE:=RAID6 algorithm support\n  HIDDEN:=1\n  KCONFIG:=CONFIG_RAID6_PQ\n  FILES:=$(LINUX_DIR)/lib/raid6/raid6_pq.ko\n  AUTOLOAD:=$(call AutoProbe,raid6_pq)\nendef\n\ndefine KernelPackage/lib-raid6/description\n Kernel module for RAID6 algorithms\nendef\n\n$(eval $(call KernelPackage,lib-raid6))\n\n\ndefine KernelPackage/lib-xor\n  SUBMENU:=$(LIB_MENU)\n  TITLE:=XOR blocks algorithm support\n  HIDDEN:=1\n  KCONFIG:=CONFIG_XOR_BLOCKS\nifneq ($(wildcard $(LINUX_DIR)/arch/$(LINUX_KARCH)/lib/xor-neon.ko),)\n  FILES:= \\\n    $(LINUX_DIR)/crypto/xor.ko \\\n    $(LINUX_DIR)/arch/$(LINUX_KARCH)/lib/xor-neon.ko\n  AUTOLOAD:=$(call AutoProbe,xor-neon xor)\nelse\n  FILES:=$(LINUX_DIR)/crypto/xor.ko\n  AUTOLOAD:=$(call AutoProbe,xor)\nendif\nendef\n\ndefine KernelPackage/lib-xor/description\n Kernel module for XOR blocks algorithms\nendef\n\n$(eval $(call KernelPackage,lib-xor))\n\n\ndefine KernelPackage/lib-textsearch\nSUBMENU:=$(LIB_MENU)\n  TITLE:=Textsearch support\n  KCONFIG:= \\\n    CONFIG_TEXTSEARCH=y \\\n    CONFIG_TEXTSEARCH_KMP \\\n    CONFIG_TEXTSEARCH_BM \\\n    CONFIG_TEXTSEARCH_FSM\n  FILES:= \\\n    $(LINUX_DIR)/lib/ts_kmp.ko \\\n    $(LINUX_DIR)/lib/ts_bm.ko \\\n    $(LINUX_DIR)/lib/ts_fsm.ko\n  AUTOLOAD:=$(call AutoProbe,ts_kmp ts_bm ts_fsm)\nendef\n\n$(eval $(call KernelPackage,lib-textsearch))\n\n\ndefine KernelPackage/lib-zlib-inflate\n  SUBMENU:=$(LIB_MENU)\n  TITLE:=Zlib support\n  HIDDEN:=1\n  KCONFIG:=CONFIG_ZLIB_INFLATE\n  FILES:=$(LINUX_DIR)/lib/zlib_inflate/zlib_inflate.ko\n  AUTOLOAD:=$(call AutoProbe,zlib_inflate)\nendef\n\n$(eval $(call KernelPackage,lib-zlib-inflate))\n\n\ndefine KernelPackage/lib-zlib-deflate\n  SUBMENU:=$(LIB_MENU)\n  TITLE:=Zlib support\n  HIDDEN:=1\n  KCONFIG:=CONFIG_ZLIB_DEFLATE\n  FILES:=$(LINUX_DIR)/lib/zlib_deflate/zlib_deflate.ko\n  AUTOLOAD:=$(call AutoProbe,zlib_deflate)\nendef\n\n$(eval $(call KernelPackage,lib-zlib-deflate))\n\n\ndefine KernelPackage/lib-cordic\n  SUBMENU:=$(LIB_MENU)\n  TITLE:=Cordic function support\n  KCONFIG:=CONFIG_CORDIC\n  FILES:=$(LINUX_DIR)/lib/math/cordic.ko\n  AUTOLOAD:=$(call AutoProbe,cordic)\nendef\n\ndefine KernelPackage/lib-cordic/description\n Kernel module for Cordic function support\nendef\n\n$(eval $(call KernelPackage,lib-cordic))\n\n\ndefine KernelPackage/asn1-decoder\n  SUBMENU:=$(LIB_MENU)\n  TITLE:=Simple ASN1 decoder\n  KCONFIG:= CONFIG_ASN1\n  HIDDEN:=1\n  FILES:=$(LINUX_DIR)/lib/asn1_decoder.ko\nendef\n\n$(eval $(call KernelPackage,asn1-decoder))\n\ndefine KernelPackage/asn1-encoder\n  SUBMENU:=$(LIB_MENU)\n  TITLE:=Simple ASN1 encoder\n  KCONFIG:= CONFIG_ASN1_ENCODER\n  HIDDEN:=1\n  FILES:=$(LINUX_DIR)/lib/asn1_encoder.ko\nendef\n\n$(eval $(call KernelPackage,asn1-encoder))\n\ndefine KernelPackage/oid-registry\n  SUBMENU:=$(LIB_MENU)\n  TITLE:=Object identifier registry\n  KCONFIG:= CONFIG_OID_REGISTRY\n  FILES:=$(LINUX_DIR)/lib/oid_registry.ko\n  AUTOLOAD:=$(call AutoLoad,31,oid_registry)\nendef\n\n$(eval $(call KernelPackage,oid-registry))\n"
  },
  {
    "path": "package/kernel/linux/modules/multiplexer.mk",
    "content": "# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\nMENU_TITLE:=Multiplexer Support\n\ndefine KernelPackage/mux-core\n  SUBMENU:=$(MENU_TITLE)\n  TITLE:=Multiplexer Support\n  KCONFIG:=CONFIG_MULTIPLEXER\n  FILES:=$(LINUX_DIR)/drivers/mux/mux-core.ko\n  AUTOLOAD:=$(call AutoLoad,25,mux-core,1)\nendef\n\ndefine KernelPackage/mux-core/description\n  Kernel module for multiplexer support\nendef\n\n$(eval $(call KernelPackage,mux-core))\n\ndefine KernelPackage/mux-gpio\n  SUBMENU:=$(MENU_TITLE)\n  TITLE:=GPIO-controlled Multiplexer controller\n  KCONFIG:=CONFIG_MUX_GPIO\n  DEPENDS:=@GPIO_SUPPORT kmod-mux-core\n  FILES:=$(LINUX_DIR)/drivers/mux/mux-gpio.ko\n  AUTOLOAD:=$(call AutoLoad,25,mux-gpio,1)\nendef\n\ndefine KernelPackage/mux-gpio/description\n  Kernel modules for GPIO-controlled Multiplexer controller\nendef\n\n$(eval $(call KernelPackage,mux-gpio))\n"
  },
  {
    "path": "package/kernel/linux/modules/netdevices.mk",
    "content": "#\n# Copyright (C) 2006-2011 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\nNETWORK_DEVICES_MENU:=Network Devices\n\ndefine KernelPackage/sis190\n  SUBMENU:=$(NETWORK_DEVICES_MENU)\n  TITLE:=SiS 190 Fast/Gigabit Ethernet support\n  DEPENDS:=@PCI_SUPPORT +kmod-mii\n  KCONFIG:=CONFIG_SIS190\n  FILES:=$(LINUX_DIR)/drivers/net/ethernet/sis/sis190.ko\n  AUTOLOAD:=$(call AutoProbe,sis190)\nendef\n\n$(eval $(call KernelPackage,sis190))\n\n\ndefine KernelPackage/skge\n  SUBMENU:=$(NETWORK_DEVICES_MENU)\n  TITLE:=SysKonnect Yukon support\n  DEPENDS:=@PCI_SUPPORT\n  KCONFIG:=CONFIG_SKGE \\\n\tCONFIG_SKGE_DEBUG=n \\\n\tCONFIG_SKGE_GENESIS=n\n  FILES:=$(LINUX_DIR)/drivers/net/ethernet/marvell/skge.ko\n  AUTOLOAD:=$(call AutoProbe,skge)\nendef\n\n$(eval $(call KernelPackage,skge))\n\n\ndefine KernelPackage/alx\n  SUBMENU:=$(NETWORK_DEVICES_MENU)\n  TITLE:=Qualcomm Atheros AR816x/AR817x PCI-E Ethernet Network Driver\n  DEPENDS:=@PCI_SUPPORT +kmod-mdio\n  KCONFIG:=CONFIG_ALX\n  FILES:=$(LINUX_DIR)/drivers/net/ethernet/atheros/alx/alx.ko\n  AUTOLOAD:=$(call AutoProbe,alx)\nendef\n\n$(eval $(call KernelPackage,alx))\n\n\ndefine KernelPackage/atl2\n  SUBMENU:=$(NETWORK_DEVICES_MENU)\n  TITLE:=Atheros L2 Fast Ethernet support\n  DEPENDS:=@PCI_SUPPORT\n  KCONFIG:=CONFIG_ATL2\n  FILES:=$(LINUX_DIR)/drivers/net/ethernet/atheros/atlx/atl2.ko\n  AUTOLOAD:=$(call AutoProbe,atl2)\nendef\n\n$(eval $(call KernelPackage,atl2))\n\n\ndefine KernelPackage/atl1\n  SUBMENU:=$(NETWORK_DEVICES_MENU)\n  TITLE:=Atheros L1 Gigabit Ethernet support\n  DEPENDS:=@PCI_SUPPORT +kmod-mii\n  KCONFIG:=CONFIG_ATL1\n  FILES:=$(LINUX_DIR)/drivers/net/ethernet/atheros/atlx/atl1.ko\n  AUTOLOAD:=$(call AutoProbe,atl1)\nendef\n\n$(eval $(call KernelPackage,atl1))\n\n\ndefine KernelPackage/atl1c\n  SUBMENU:=$(NETWORK_DEVICES_MENU)\n  TITLE:=Atheros L1C\n  DEPENDS:=@PCI_SUPPORT\n  KCONFIG:=CONFIG_ATL1C\n  FILES:=$(LINUX_DIR)/drivers/net/ethernet/atheros/atl1c/atl1c.ko\n  AUTOLOAD:=$(call AutoProbe,atl1c)\nendef\n\n$(eval $(call KernelPackage,atl1c))\n\n\ndefine KernelPackage/atl1e\n  SUBMENU:=$(NETWORK_DEVICES_MENU)\n  TITLE:=Atheros L1E\n  DEPENDS:=@PCI_SUPPORT\n  KCONFIG:=CONFIG_ATL1E\n  FILES:=$(LINUX_DIR)/drivers/net/ethernet/atheros/atl1e/atl1e.ko\n  AUTOLOAD:=$(call AutoProbe,atl1e)\nendef\n\n$(eval $(call KernelPackage,atl1e))\n\n\ndefine KernelPackage/libphy\n  SUBMENU:=$(NETWORK_DEVICES_MENU)\n  TITLE:=PHY library\n  KCONFIG:=CONFIG_PHYLIB\n  FILES:=$(LINUX_DIR)/drivers/net/phy/libphy.ko\n  AUTOLOAD:=$(call AutoLoad,15,libphy,1)\nendef\n\ndefine KernelPackage/libphy/description\n PHY library\nendef\n\n$(eval $(call KernelPackage,libphy))\n\n\ndefine KernelPackage/phylink\n  SUBMENU:=$(NETWORK_DEVICES_MENU)\n  TITLE:=Model for MAC to optional PHY connection\n  KCONFIG:=CONFIG_PHYLINK\n  FILES:=$(LINUX_DIR)/drivers/net/phy/phylink.ko\n  AUTOLOAD:=$(call AutoLoad,15,phylink,1)\nendef\n\ndefine KernelPackage/phylink/description\n Model for MAC to optional PHY connection\nendef\n\n$(eval $(call KernelPackage,phylink))\n\n\ndefine KernelPackage/mii\n  SUBMENU:=$(NETWORK_DEVICES_MENU)\n  TITLE:=MII library\n  KCONFIG:=CONFIG_MII\n  FILES:=$(LINUX_DIR)/drivers/net/mii.ko\n  AUTOLOAD:=$(call AutoLoad,15,mii,1)\nendef\n\ndefine KernelPackage/mii/description\n  MII library\nendef\n\n$(eval $(call KernelPackage,mii))\n\n\ndefine KernelPackage/mdio-devres\n  SUBMENU:=$(NETWORK_DEVICES_MENU)\n  TITLE:=Supports MDIO device registration\n  DEPENDS:=@(LINUX_5_10||LINUX_5_15) +kmod-libphy +(TARGET_armvirt||TARGET_bcm27xx_bcm2708||TARGET_tegra):kmod-of-mdio\n  KCONFIG:=CONFIG_MDIO_DEVRES\n  HIDDEN:=1\n  FILES:=$(LINUX_DIR)/drivers/net/phy/mdio_devres.ko\n  AUTOLOAD:=$(call AutoProbe,mdio-devres)\nendef\n\ndefine KernelPackage/mdio-devres/description\n Supports MDIO device registration\nendef\n\n$(eval $(call KernelPackage,mdio-devres))\n\n\ndefine KernelPackage/mdio-gpio\n  SUBMENU:=$(NETWORK_DEVICES_MENU)\n  TITLE:= Supports GPIO lib-based MDIO busses\n  DEPENDS:=+kmod-libphy @GPIO_SUPPORT +(TARGET_armvirt||TARGET_bcm27xx_bcm2708||TARGET_tegra):kmod-of-mdio\n  KCONFIG:= \\\n\tCONFIG_MDIO_BITBANG \\\n\tCONFIG_MDIO_GPIO\n  FILES:= \\\n\t$(LINUX_DIR)/drivers/net/phy/mdio-gpio.ko@lt5.10 \\\n\t$(LINUX_DIR)/drivers/net/phy/mdio-bitbang.ko@lt5.10 \\\n\t$(LINUX_DIR)/drivers/net/mdio/mdio-gpio.ko@ge5.10 \\\n\t$(LINUX_DIR)/drivers/net/mdio/mdio-bitbang.ko@ge5.10\n  AUTOLOAD:=$(call AutoProbe,mdio-gpio)\nendef\n\ndefine KernelPackage/mdio-gpio/description\n Supports GPIO lib-based MDIO busses\nendef\n\n$(eval $(call KernelPackage,mdio-gpio))\n\n\ndefine KernelPackage/et131x\n  SUBMENU:=$(NETWORK_DEVICES_MENU)\n  TITLE:=Agere ET131x Gigabit Ethernet driver\n  URL:=http://sourceforge.net/projects/et131x\n  FILES:= \\\n\t$(LINUX_DIR)/drivers/net/ethernet/agere/et131x.ko\n  KCONFIG:= \\\n\tCONFIG_ET131X \\\n\tCONFIG_ET131X_DEBUG=n\n  DEPENDS:=@PCI_SUPPORT +kmod-libphy\n  AUTOLOAD:=$(call AutoProbe,et131x)\nendef\n\ndefine KernelPackage/et131x/description\n This package contains the et131x kernel module\nendef\n\n$(eval $(call KernelPackage,et131x))\n\ndefine KernelPackage/phy-microchip\n   SUBMENU:=$(NETWORK_DEVICES_MENU)\n   TITLE:=Microchip Ethernet PHY driver\n   KCONFIG:=CONFIG_MICROCHIP_PHY\n   DEPENDS:=+kmod-libphy\n   FILES:=$(LINUX_DIR)/drivers/net/phy/microchip.ko\n   AUTOLOAD:=$(call AutoLoad,18,microchip,1)\nendef\n\ndefine KernelPackage/phy-microchip/description\n   Supports the LAN88XX PHYs.\nendef\n\n$(eval $(call KernelPackage,phy-microchip))\n\n\ndefine KernelPackage/phylib-broadcom\n   SUBMENU:=$(NETWORK_DEVICES_MENU)\n   TITLE:=Broadcom Ethernet PHY library\n   KCONFIG:=CONFIG_BCM_NET_PHYLIB\n   HIDDEN:=1\n   DEPENDS:=+kmod-libphy\n   FILES:=$(LINUX_DIR)/drivers/net/phy/bcm-phy-lib.ko\n   AUTOLOAD:=$(call AutoLoad,17,bcm-phy-lib)\nendef\n\n$(eval $(call KernelPackage,phylib-broadcom))\n\n\ndefine KernelPackage/phy-broadcom\n   SUBMENU:=$(NETWORK_DEVICES_MENU)\n   TITLE:=Broadcom Ethernet PHY driver\n   KCONFIG:=CONFIG_BROADCOM_PHY\n   DEPENDS:=+kmod-libphy +kmod-phylib-broadcom\n   FILES:=$(LINUX_DIR)/drivers/net/phy/broadcom.ko\n   AUTOLOAD:=$(call AutoLoad,18,broadcom,1)\nendef\n\ndefine KernelPackage/phy-broadcom/description\n   Currently supports the BCM5411, BCM5421, BCM5461, BCM5464, BCM5481,\n   BCM5482 and BCM57780 PHYs.\nendef\n\n$(eval $(call KernelPackage,phy-broadcom))\n\n\ndefine KernelPackage/phy-bcm84881\n   SUBMENU:=$(NETWORK_DEVICES_MENU)\n   TITLE:=Broadcom BCM84881 PHY driver\n   KCONFIG:=CONFIG_BCM84881_PHY\n   DEPENDS:=+kmod-libphy\n   FILES:=$(LINUX_DIR)/drivers/net/phy/bcm84881.ko\n   AUTOLOAD:=$(call AutoLoad,18,bcm84881,1)\nendef\n\ndefine KernelPackage/phy-bcm84881/description\n   Supports the Broadcom 84881 PHY.\nendef\n\n$(eval $(call KernelPackage,phy-bcm84881))\n\n\n\ndefine KernelPackage/phy-realtek\n   SUBMENU:=$(NETWORK_DEVICES_MENU)\n   TITLE:=Realtek Ethernet PHY driver\n   KCONFIG:=CONFIG_REALTEK_PHY\n   DEPENDS:=+kmod-libphy\n   FILES:=$(LINUX_DIR)/drivers/net/phy/realtek.ko\n   AUTOLOAD:=$(call AutoLoad,18,realtek,1)\nendef\n\ndefine KernelPackage/phy-realtek/description\n   Supports the Realtek 821x PHY.\nendef\n\n$(eval $(call KernelPackage,phy-realtek))\n\n\ndefine KernelPackage/swconfig\n  SUBMENU:=$(NETWORK_DEVICES_MENU)\n  TITLE:=switch configuration API\n  DEPENDS:=+kmod-libphy\n  KCONFIG:=CONFIG_SWCONFIG\n  FILES:=$(LINUX_DIR)/drivers/net/phy/swconfig.ko\n  AUTOLOAD:=$(call AutoLoad,41,swconfig)\nendef\n\ndefine KernelPackage/swconfig/description\n Switch configuration API module\nendef\n\n$(eval $(call KernelPackage,swconfig))\n\ndefine KernelPackage/switch-bcm53xx\n  SUBMENU:=$(NETWORK_DEVICES_MENU)\n  TITLE:=Broadcom bcm53xx switch support\n  DEPENDS:=+kmod-swconfig\n  KCONFIG:=CONFIG_SWCONFIG_B53\n  FILES:=$(LINUX_DIR)/drivers/net/phy/b53/b53_common.ko\n  AUTOLOAD:=$(call AutoLoad,42,b53_common)\nendef\n\ndefine KernelPackage/switch-bcm53xx/description\n  Broadcom bcm53xx switch support\nendef\n\n$(eval $(call KernelPackage,switch-bcm53xx))\n\ndefine KernelPackage/switch-bcm53xx-mdio\n  SUBMENU:=$(NETWORK_DEVICES_MENU)\n  TITLE:=Broadcom bcm53xx switch MDIO support\n  DEPENDS:=+kmod-switch-bcm53xx\n  KCONFIG:=CONFIG_SWCONFIG_B53_PHY_DRIVER\n  FILES:=$(LINUX_DIR)/drivers/net/phy/b53/b53_mdio.ko\n  AUTOLOAD:=$(call AutoLoad,42,b53_mdio)\nendef\n\ndefine KernelPackage/switch-bcm53xx-mdio/description\n  Broadcom bcm53xx switch MDIO support\nendef\n\n$(eval $(call KernelPackage,switch-bcm53xx-mdio))\n\n\ndefine KernelPackage/switch-ip17xx\n  SUBMENU:=$(NETWORK_DEVICES_MENU)\n  TITLE:=IC+ IP17XX switch support\n  DEPENDS:=+kmod-swconfig\n  KCONFIG:=CONFIG_IP17XX_PHY\n  FILES:=$(LINUX_DIR)/drivers/net/phy/ip17xx.ko\n  AUTOLOAD:=$(call AutoLoad,42,ip17xx)\nendef\n\ndefine KernelPackage/switch-ip17xx/description\n IC+ IP175C/IP178C switch support\nendef\n\n$(eval $(call KernelPackage,switch-ip17xx))\n\n\ndefine KernelPackage/switch-rtl8306\n  SUBMENU:=$(NETWORK_DEVICES_MENU)\n  TITLE:=Realtek RTL8306S switch support\n  DEPENDS:=+kmod-swconfig\n  KCONFIG:=CONFIG_RTL8306_PHY\n  FILES:=$(LINUX_DIR)/drivers/net/phy/rtl8306.ko\n  AUTOLOAD:=$(call AutoLoad,43,rtl8306)\nendef\n\ndefine KernelPackage/switch-rtl8306/description\n Realtek RTL8306S switch support\nendef\n\n$(eval $(call KernelPackage,switch-rtl8306))\n\n\ndefine KernelPackage/switch-rtl8366-smi\n  SUBMENU:=$(NETWORK_DEVICES_MENU)\n  TITLE:=Realtek RTL8366 SMI switch interface support\n  DEPENDS:=@GPIO_SUPPORT +kmod-swconfig +(TARGET_armvirt||TARGET_bcm27xx_bcm2708||TARGET_tegra):kmod-of-mdio\n  KCONFIG:=CONFIG_RTL8366_SMI\n  FILES:=$(LINUX_DIR)/drivers/net/phy/rtl8366_smi.ko\n  AUTOLOAD:=$(call AutoLoad,42,rtl8366_smi,1)\nendef\n\ndefine KernelPackage/switch-rtl8366-smi/description\n  Realtek RTL8366 series SMI switch interface support\nendef\n\n$(eval $(call KernelPackage,switch-rtl8366-smi))\n\n\ndefine KernelPackage/switch-rtl8366rb\n  SUBMENU:=$(NETWORK_DEVICES_MENU)\n  TITLE:=Realtek RTL8366RB switch support\n  DEPENDS:=+kmod-switch-rtl8366-smi\n  KCONFIG:=CONFIG_RTL8366RB_PHY\n  FILES:=$(LINUX_DIR)/drivers/net/phy/rtl8366rb.ko\n  AUTOLOAD:=$(call AutoLoad,43,rtl8366rb)\nendef\n\ndefine KernelPackage/switch-rtl8366rb/description\n Realtek RTL8366RB switch support\nendef\n\n$(eval $(call KernelPackage,switch-rtl8366rb))\n\n\ndefine KernelPackage/switch-rtl8366s\n  SUBMENU:=$(NETWORK_DEVICES_MENU)\n  TITLE:=Realtek RTL8366S switch support\n  DEPENDS:=+kmod-switch-rtl8366-smi\n  KCONFIG:=CONFIG_RTL8366S_PHY\n  FILES:=$(LINUX_DIR)/drivers/net/phy/rtl8366s.ko\n  AUTOLOAD:=$(call AutoLoad,43,rtl8366s)\nendef\n\ndefine KernelPackage/switch-rtl8366s/description\n Realtek RTL8366S switch support\nendef\n\n$(eval $(call KernelPackage,switch-rtl8366s))\n\n\ndefine KernelPackage/switch-rtl8367b\n  SUBMENU:=$(NETWORK_DEVICES_MENU)\n  TITLE:=Realtek RTL8367R/B switch support\n  DEPENDS:=+kmod-switch-rtl8366-smi\n  KCONFIG:=CONFIG_RTL8367B_PHY\n  FILES:=$(LINUX_DIR)/drivers/net/phy/rtl8367b.ko\n  AUTOLOAD:=$(call AutoLoad,43,rtl8367b,1)\nendef\n\ndefine KernelPackage/switch-rtl8367b/description\n Realtek RTL8367R/B switch support\nendef\n\n$(eval $(call KernelPackage,switch-rtl8367b))\n\n\ndefine KernelPackage/natsemi\n  SUBMENU:=$(NETWORK_DEVICES_MENU)\n  TITLE:=National Semiconductor DP8381x series\n  DEPENDS:=@PCI_SUPPORT\n  KCONFIG:=CONFIG_NATSEMI\n  FILES:=$(LINUX_DIR)/drivers/net/ethernet/natsemi/natsemi.ko\n  AUTOLOAD:=$(call AutoLoad,20,natsemi)\nendef\n\ndefine KernelPackage/natsemi/description\n Kernel modules for National Semiconductor DP8381x series PCI Ethernet\n adapters.\nendef\n\n$(eval $(call KernelPackage,natsemi))\n\n\ndefine KernelPackage/r6040\n  SUBMENU:=$(NETWORK_DEVICES_MENU)\n  TITLE:=RDC Fast-Ethernet support\n  DEPENDS:=@PCI_SUPPORT +kmod-libphy\n  KCONFIG:=CONFIG_R6040 \\\n\t\tCONFIG_R6040_NAPI=y\n  FILES:=$(LINUX_DIR)/drivers/net/ethernet/rdc/r6040.ko\n  AUTOLOAD:=$(call AutoProbe,r6040)\nendef\n\ndefine KernelPackage/r6040/description\n Kernel modules for RDC Fast-Ethernet adapters.\nendef\n\n$(eval $(call KernelPackage,r6040))\n\n\ndefine KernelPackage/niu\n  SUBMENU:=$(NETWORK_DEVICES_MENU)\n  TITLE:=Sun Neptune 10Gbit Ethernet support\n  DEPENDS:=@PCI_SUPPORT\n  KCONFIG:=CONFIG_NIU\n  FILES:=$(LINUX_DIR)/drivers/net/ethernet/sun/niu.ko\n  AUTOLOAD:=$(call AutoProbe,niu)\nendef\n\ndefine KernelPackage/niu/description\n This enables support for cards based upon Sun's Neptune chipset.\nendef\n\n$(eval $(call KernelPackage,niu))\n\n\ndefine KernelPackage/sis900\n  SUBMENU:=$(NETWORK_DEVICES_MENU)\n  TITLE:=SiS 900 Ethernet support\n  DEPENDS:=@PCI_SUPPORT +kmod-mii\n  KCONFIG:=CONFIG_SIS900\n  FILES:=$(LINUX_DIR)/drivers/net/ethernet/sis/sis900.ko\n  AUTOLOAD:=$(call AutoProbe,sis900)\nendef\n\ndefine KernelPackage/sis900/description\n Kernel modules for Sis 900 Ethernet adapters.\nendef\n\n$(eval $(call KernelPackage,sis900))\n\n\ndefine KernelPackage/sky2\n  SUBMENU:=$(NETWORK_DEVICES_MENU)\n  TITLE:=SysKonnect Yukon2 support\n  DEPENDS:=@PCI_SUPPORT\n  KCONFIG:=CONFIG_SKY2\n  FILES:=$(LINUX_DIR)/drivers/net/ethernet/marvell/sky2.ko\n  AUTOLOAD:=$(call AutoProbe,sky2)\nendef\n\ndefine KernelPackage/sky2/description\n  This driver supports Gigabit Ethernet adapters based on the\n  Marvell Yukon 2 chipset:\n  Marvell 88E8021/88E8022/88E8035/88E8036/88E8038/88E8050/88E8052/\n  88E8053/88E8055/88E8061/88E8062, SysKonnect SK-9E21D/SK-9S21\n\n  There is companion driver for the older Marvell Yukon and\n  Genesis based adapters: skge.\nendef\n\n$(eval $(call KernelPackage,sky2))\n\n\ndefine KernelPackage/via-rhine\n  SUBMENU:=$(NETWORK_DEVICES_MENU)\n  TITLE:=Via Rhine ethernet support\n  DEPENDS:=@PCI_SUPPORT +kmod-mii\n  KCONFIG:=CONFIG_VIA_RHINE \\\n    CONFIG_VIA_RHINE_MMIO=y\n  FILES:=$(LINUX_DIR)/drivers/net/ethernet/via/via-rhine.ko\n  AUTOLOAD:=$(call AutoProbe,via-rhine)\nendef\n\ndefine KernelPackage/via-rhine/description\n Kernel modules for Via Rhine Ethernet chipsets\nendef\n\n$(eval $(call KernelPackage,via-rhine))\n\n\ndefine KernelPackage/via-velocity\n  SUBMENU:=$(NETWORK_DEVICES_MENU)\n  TITLE:=VIA Velocity Gigabit Ethernet Adapter kernel support\n  DEPENDS:=@PCI_SUPPORT +kmod-lib-crc-ccitt\n  KCONFIG:=CONFIG_VIA_VELOCITY\n  FILES:=$(LINUX_DIR)/drivers/net/ethernet/via/via-velocity.ko\n  AUTOLOAD:=$(call AutoProbe,via-velocity)\nendef\n\ndefine KernelPackage/via-velocity/description\n Kernel modules for VIA Velocity Gigabit Ethernet chipsets\nendef\n\n$(eval $(call KernelPackage,via-velocity))\n\n\ndefine KernelPackage/8139too\n  SUBMENU:=$(NETWORK_DEVICES_MENU)\n  TITLE:=RealTek RTL-8139 PCI Fast Ethernet Adapter kernel support\n  DEPENDS:=@PCI_SUPPORT +kmod-mii\n  KCONFIG:=CONFIG_8139TOO \\\n    CONFIG_8139TOO_PIO=y \\\n    CONFIG_8139TOO_TUNE_TWISTER=n \\\n    CONFIG_8139TOO_8129=n \\\n    CONFIG_8139_OLD_RX_RESET=n\n  FILES:=$(LINUX_DIR)/drivers/net/ethernet/realtek/8139too.ko\n  AUTOLOAD:=$(call AutoProbe,8139too)\nendef\n\ndefine KernelPackage/8139too/description\n Kernel modules for RealTek RTL-8139 PCI Fast Ethernet adapters\nendef\n\n$(eval $(call KernelPackage,8139too))\n\n\ndefine KernelPackage/8139cp\n  SUBMENU:=$(NETWORK_DEVICES_MENU)\n  TITLE:=RealTek RTL-8139C+ PCI Fast Ethernet Adapter kernel support\n  DEPENDS:=@PCI_SUPPORT +kmod-mii\n  KCONFIG:=CONFIG_8139CP\n  FILES:=$(LINUX_DIR)/drivers/net/ethernet/realtek/8139cp.ko\n  AUTOLOAD:=$(call AutoProbe,8139cp)\nendef\n\ndefine KernelPackage/8139cp/description\n Kernel module for RealTek RTL-8139C+ PCI Fast Ethernet adapters\nendef\n\n$(eval $(call KernelPackage,8139cp))\n\n\ndefine KernelPackage/r8169\n  SUBMENU:=$(NETWORK_DEVICES_MENU)\n  TITLE:=RealTek RTL-8169 PCI Gigabit Ethernet Adapter kernel support\n  DEPENDS:=@PCI_SUPPORT +kmod-mii +r8169-firmware +kmod-phy-realtek +(LINUX_5_10||LINUX_5_15):kmod-mdio-devres\n  KCONFIG:= \\\n    CONFIG_R8169 \\\n    CONFIG_R8169_NAPI=y \\\n    CONFIG_R8169_VLAN=n\n  FILES:=$(LINUX_DIR)/drivers/net/ethernet/realtek/r8169.ko\n  AUTOLOAD:=$(call AutoProbe,r8169)\nendef\n\ndefine KernelPackage/r8169/description\n Kernel modules for RealTek RTL-8169 PCI Gigabit Ethernet adapters\nendef\n\n$(eval $(call KernelPackage,r8169))\n\n\ndefine KernelPackage/ne2k-pci\n  SUBMENU:=$(NETWORK_DEVICES_MENU)\n  TITLE:=ne2k-pci Ethernet Adapter kernel support\n  DEPENDS:=@PCI_SUPPORT\n  KCONFIG:=CONFIG_NE2K_PCI\n  FILES:= \\\n\t$(LINUX_DIR)/drivers/net/ethernet/8390/ne2k-pci.ko \\\n\t$(LINUX_DIR)/drivers/net/ethernet/8390/8390.ko\n  AUTOLOAD:=$(call AutoProbe,8390 ne2k-pci)\nendef\n\ndefine KernelPackage/ne2k-pci/description\n Kernel modules for NE2000 PCI Ethernet Adapter kernel\nendef\n\n$(eval $(call KernelPackage,ne2k-pci))\n\n\ndefine KernelPackage/e100\n  SUBMENU:=$(NETWORK_DEVICES_MENU)\n  TITLE:=Intel(R) PRO/100+ cards kernel support\n  DEPENDS:=@PCI_SUPPORT +kmod-mii +e100-firmware\n  KCONFIG:=CONFIG_E100\n  FILES:=$(LINUX_DIR)/drivers/net/ethernet/intel/e100.ko\n  AUTOLOAD:=$(call AutoProbe,e100)\nendef\n\ndefine KernelPackage/e100/description\n Kernel modules for Intel(R) PRO/100+ Ethernet adapters\nendef\n\n$(eval $(call KernelPackage,e100))\n\n\ndefine KernelPackage/e1000\n  SUBMENU:=$(NETWORK_DEVICES_MENU)\n  TITLE:=Intel(R) PRO/1000 PCI cards kernel support\n  DEPENDS:=@PCI_SUPPORT\n  KCONFIG:=CONFIG_E1000 \\\n    CONFIG_E1000_DISABLE_PACKET_SPLIT=n \\\n    CONFIG_E1000_NAPI=y\n  FILES:=$(LINUX_DIR)/drivers/net/ethernet/intel/e1000/e1000.ko\n  AUTOLOAD:=$(call AutoLoad,35,e1000)\nendef\n\ndefine KernelPackage/e1000/description\n Kernel modules for Intel(R) PRO/1000 PCI Ethernet adapters.\nendef\n\n$(eval $(call KernelPackage,e1000))\n\n\ndefine KernelPackage/e1000e\n  SUBMENU:=$(NETWORK_DEVICES_MENU)\n  TITLE:=Intel(R) PRO/1000 PCIe cards kernel support\n  DEPENDS:=@PCIE_SUPPORT +kmod-ptp\n  KCONFIG:=CONFIG_E1000E\n  FILES:=$(LINUX_DIR)/drivers/net/ethernet/intel/e1000e/e1000e.ko\n  AUTOLOAD:=$(call AutoProbe,e1000e)\n  MODPARAMS.e1000e:= \\\n    IntMode=1 \\\n    InterruptThrottleRate=4,4,4,4,4,4,4,4\nendef\n\ndefine KernelPackage/e1000e/description\n Kernel modules for Intel(R) PRO/1000 PCIe Ethernet adapters.\nendef\n\n$(eval $(call KernelPackage,e1000e))\n\n\ndefine KernelPackage/igb\n  SUBMENU:=$(NETWORK_DEVICES_MENU)\n  TITLE:=Intel(R) 82575/82576 PCI-Express Gigabit Ethernet support\n  DEPENDS:=@PCI_SUPPORT +kmod-i2c-core +kmod-i2c-algo-bit +kmod-ptp +kmod-hwmon-core\n  KCONFIG:=CONFIG_IGB \\\n    CONFIG_IGB_HWMON=y \\\n    CONFIG_IGB_DCA=n\n  FILES:=$(LINUX_DIR)/drivers/net/ethernet/intel/igb/igb.ko\n  AUTOLOAD:=$(call AutoLoad,35,igb,1)\nendef\n\ndefine KernelPackage/igb/description\n Kernel modules for Intel(R) 82575/82576 PCI-Express Gigabit Ethernet adapters.\nendef\n\n$(eval $(call KernelPackage,igb))\n\n\ndefine KernelPackage/igbvf\n  SUBMENU:=$(NETWORK_DEVICES_MENU)\n  TITLE:=Intel(R) 82576 Virtual Function Ethernet support\n  DEPENDS:=@PCI_SUPPORT @TARGET_x86 +kmod-i2c-core +kmod-i2c-algo-bit +kmod-ptp\n  KCONFIG:=CONFIG_IGBVF \\\n    CONFIG_IGB_HWMON=y \\\n    CONFIG_IGB_DCA=n\n  FILES:=$(LINUX_DIR)/drivers/net/ethernet/intel/igbvf/igbvf.ko\n  AUTOLOAD:=$(call AutoLoad,35,igbvf)\nendef\n\ndefine KernelPackage/igbvf/description\n Kernel modules for Intel(R) 82576 Virtual Function Ethernet adapters.\nendef\n\n$(eval $(call KernelPackage,igbvf))\n\n\ndefine KernelPackage/ixgbe\n  SUBMENU:=$(NETWORK_DEVICES_MENU)\n  TITLE:=Intel(R) 82598/82599 PCI-Express 10 Gigabit Ethernet support\n  DEPENDS:=@PCI_SUPPORT +kmod-mdio +kmod-ptp +kmod-hwmon-core +kmod-libphy +(LINUX_5_10||LINUX_5_15):kmod-mdio-devres\n  KCONFIG:=CONFIG_IXGBE \\\n    CONFIG_IXGBE_VXLAN=n \\\n    CONFIG_IXGBE_HWMON=y \\\n    CONFIG_IXGBE_DCA=n\n  FILES:=$(LINUX_DIR)/drivers/net/ethernet/intel/ixgbe/ixgbe.ko\n  AUTOLOAD:=$(call AutoLoad,35,ixgbe)\nendef\n\ndefine KernelPackage/ixgbe/description\n Kernel modules for Intel(R) 82598/82599 PCI-Express 10 Gigabit Ethernet adapters.\nendef\n\n$(eval $(call KernelPackage,ixgbe))\n\n\ndefine KernelPackage/ixgbevf\n  SUBMENU:=$(NETWORK_DEVICES_MENU)\n  TITLE:=Intel(R) 82599 Virtual Function Ethernet support\n  DEPENDS:=@PCI_SUPPORT +kmod-ixgbe\n  KCONFIG:=CONFIG_IXGBEVF \\\n    CONFIG_IXGBE_VXLAN=n \\\n    CONFIG_IXGBE_HWMON=y \\\n    CONFIG_IXGBE_DCA=n\n  FILES:=$(LINUX_DIR)/drivers/net/ethernet/intel/ixgbevf/ixgbevf.ko\n  AUTOLOAD:=$(call AutoLoad,35,ixgbevf)\nendef\n\ndefine KernelPackage/ixgbevf/description\n Kernel modules for Intel(R) 82599 Virtual Function Ethernet adapters.\nendef\n\n$(eval $(call KernelPackage,ixgbevf))\n\n\ndefine KernelPackage/i40e\n  SUBMENU:=$(NETWORK_DEVICES_MENU)\n  TITLE:=Intel(R) Ethernet Controller XL710 Family support\n  DEPENDS:=@PCI_SUPPORT +kmod-mdio +kmod-ptp +kmod-hwmon-core +kmod-libphy\n  KCONFIG:=CONFIG_I40E \\\n    CONFIG_I40E_VXLAN=n \\\n    CONFIG_I40E_HWMON=y \\\n    CONFIG_I40E_DCA=n\n  FILES:=$(LINUX_DIR)/drivers/net/ethernet/intel/i40e/i40e.ko\n  AUTOLOAD:=$(call AutoProbe,i40e)\nendef\n\ndefine KernelPackage/i40e/description\n Kernel modules for Intel(R) Ethernet Controller XL710 Family 40 Gigabit Ethernet adapters.\nendef\n\n$(eval $(call KernelPackage,i40e))\n\n\ndefine KernelPackage/iavf\n  SUBMENU:=$(NETWORK_DEVICES_MENU)\n  TITLE:=Intel(R) Ethernet Adaptive Virtual Function support\n  DEPENDS:=@PCI_SUPPORT\n  KCONFIG:= \\\n       CONFIG_I40EVF \\\n       CONFIG_IAVF\n  FILES:= \\\n       $(LINUX_DIR)/drivers/net/ethernet/intel/iavf/iavf.ko\n  AUTOLOAD:=$(call AutoProbe,i40evf iavf)\n  AUTOLOAD:=$(call AutoProbe,iavf)\nendef\n\ndefine KernelPackage/iavf/description\n Kernel modules for Intel XL710,\n\t  X710, X722, XXV710, and all devices advertising support for\n\t  Intel Ethernet Adaptive Virtual Function devices.\nendef\n\n$(eval $(call KernelPackage,iavf))\n\n\ndefine KernelPackage/b44\n  TITLE:=Broadcom 44xx driver\n  KCONFIG:=CONFIG_B44\n  DEPENDS:=@PCI_SUPPORT @!TARGET_bcm47xx_mips74k +!TARGET_bcm47xx:kmod-ssb +kmod-mii +kmod-libphy\n  SUBMENU:=$(NETWORK_DEVICES_MENU)\n  FILES:=$(LINUX_DIR)/drivers/net/ethernet/broadcom/b44.ko\n  AUTOLOAD:=$(call AutoLoad,19,b44,1)\nendef\n\ndefine KernelPackage/b44/description\n Kernel modules for Broadcom 44xx Ethernet adapters.\nendef\n\n$(eval $(call KernelPackage,b44))\n\n\ndefine KernelPackage/3c59x\n  SUBMENU:=$(NETWORK_DEVICES_MENU)\n  TITLE:=3Com 3c590/3c900 series (592/595/597) Vortex/Boomerang\n  DEPENDS:=@PCI_SUPPORT +kmod-mii\n  KCONFIG:=CONFIG_VORTEX\n  FILES:=$(LINUX_DIR)/drivers/net/ethernet/3com/3c59x.ko\n  AUTOLOAD:=$(call AutoProbe,3c59x)\nendef\n\ndefine KernelPackage/3c59x/description\n This option enables driver support for a large number of 10mbps and\n 10/100mbps EISA, PCI and PCMCIA 3Com Ethernet adapters:\n - \"Vortex\"    (Fast EtherLink 3c590/3c592/3c595/3c597) EISA and PCI\n - \"Boomerang\" (EtherLink XL 3c900 or 3c905)            PCI\n - \"Cyclone\"   (3c540/3c900/3c905/3c980/3c575/3c656)    PCI and Cardbus\n - \"Tornado\"   (3c905)                                  PCI\n - \"Hurricane\" (3c555/3cSOHO)                           PCI\nendef\n\n$(eval $(call KernelPackage,3c59x))\n\n\ndefine KernelPackage/pcnet32\n  SUBMENU:=$(NETWORK_DEVICES_MENU)\n  TITLE:=AMD PCnet32 PCI support\n  DEPENDS:=@(PCI_SUPPORT||TARGET_malta) +kmod-mii\n  KCONFIG:=CONFIG_PCNET32\n  FILES:=$(LINUX_DIR)/drivers/net/ethernet/amd/pcnet32.ko\n  AUTOLOAD:=$(call AutoProbe,pcnet32)\nendef\n\ndefine KernelPackage/pcnet32/description\n Kernel modules for AMD PCnet32 Ethernet adapters\nendef\n\n$(eval $(call KernelPackage,pcnet32))\n\n\ndefine KernelPackage/tg3\n  TITLE:=Broadcom Tigon3 Gigabit Ethernet\n  KCONFIG:=CONFIG_TIGON3 \\\n\tCONFIG_TIGON3_HWMON=n\n  DEPENDS:=+!TARGET_bcm47xx:kmod-libphy +kmod-ptp\n  SUBMENU:=$(NETWORK_DEVICES_MENU)\n  FILES:=$(LINUX_DIR)/drivers/net/ethernet/broadcom/tg3.ko\n  AUTOLOAD:=$(call AutoLoad,19,tg3,1)\nendef\n\ndefine KernelPackage/tg3/description\n Kernel modules for Broadcom Tigon3 Gigabit Ethernet adapters\nendef\n\n$(eval $(call KernelPackage,tg3))\n\n\ndefine KernelPackage/hfcpci\n  TITLE:=HFC PCI cards (single port) support for mISDN\n  KCONFIG:=CONFIG_MISDN_HFCPCI\n  DEPENDS:=+kmod-misdn\n  SUBMENU:=$(NETWORK_DEVICES_MENU)\n  FILES:=$(LINUX_DIR)/drivers/isdn/hardware/mISDN/hfcpci.ko\n  AUTOLOAD:=$(call AutoLoad,31,hfcpci)\nendef\n\ndefine KernelPackage/hfcpci/description\n Kernel modules for Cologne AG's HFC pci cards (single port)\n using the mISDN V2 stack\nendef\n\n$(eval $(call KernelPackage,hfcpci))\n\n\ndefine KernelPackage/hfcmulti\n  TITLE:=HFC multiport cards (HFC-4S/8S/E1) support for mISDN\n  KCONFIG:=CONFIG_MISDN_HFCMULTI\n  DEPENDS:=+kmod-misdn\n  SUBMENU:=$(NETWORK_DEVICES_MENU)\n  FILES:=$(LINUX_DIR)/drivers/isdn/hardware/mISDN/hfcmulti.ko\n  AUTOLOAD:=$(call AutoLoad,31,hfcmulti)\nendef\n\ndefine KernelPackage/hfcmulti/description\n Kernel modules for Cologne AG's HFC multiport cards (HFC-4S/8S/E1)\n using the mISDN V2 stack\nendef\n\n$(eval $(call KernelPackage,hfcmulti))\n\n\ndefine KernelPackage/macvlan\n  SUBMENU:=$(NETWORK_DEVICES_MENU)\n  TITLE:=MAC-VLAN support\n  KCONFIG:=CONFIG_MACVLAN\n  FILES:=$(LINUX_DIR)/drivers/net/macvlan.ko\n  AUTOLOAD:=$(call AutoProbe,macvlan)\nendef\n\ndefine KernelPackage/macvlan/description\n A kernel module which allows one to create virtual interfaces that\n map packets to or from specific MAC addresses to a particular interface\nendef\n\n$(eval $(call KernelPackage,macvlan))\n\n\ndefine KernelPackage/ipvlan\n  SUBMENU:=$(NETWORK_DEVICES_MENU)\n  TITLE:=IP-VLAN support\n  KCONFIG:=CONFIG_IPVLAN\n  FILES:=$(LINUX_DIR)/drivers/net/ipvlan/ipvlan.ko\n  AUTOLOAD:=$(call AutoProbe,ipvlan)\nendef\n\ndefine KernelPackage/ipvlan/description\n A kernel module which allows one to create virtual interfaces that\n map packets to or from specific IP addresses to a particular interface\nendef\n\n$(eval $(call KernelPackage,ipvlan))\n\n\ndefine KernelPackage/tulip\n  TITLE:=Tulip family network device support\n  DEPENDS:=@PCI_SUPPORT +kmod-mii\n  SUBMENU:=$(NETWORK_DEVICES_MENU)\n  KCONFIG:= \\\n    CONFIG_NET_TULIP=y \\\n    CONFIG_DE2104X \\\n    CONFIG_DE2104X_DSL=0 \\\n    CONFIG_TULIP \\\n    CONFIG_TULIP_MWI=y \\\n    CONFIG_TULIP_MMIO=y \\\n    CONFIG_TULIP_NAPI=y \\\n    CONFIG_TULIP_NAPI_HW_MITIGATION=y \\\n    CONFIG_DE4X5=n \\\n    CONFIG_WINBOND_840 \\\n    CONFIG_DM9102 \\\n    CONFIG_ULI526X\n  FILES:= \\\n\t$(LINUX_DIR)/drivers/net/ethernet/dec/tulip/tulip.ko \\\n\t$(LINUX_DIR)/drivers/net/ethernet/dec/tulip/de2104x.ko \\\n\t$(LINUX_DIR)/drivers/net/ethernet/dec/tulip/dmfe.ko \\\n\t$(LINUX_DIR)/drivers/net/ethernet/dec/tulip/uli526x.ko \\\n\t$(LINUX_DIR)/drivers/net/ethernet/dec/tulip/winbond-840.ko\n  AUTOLOAD:=$(call AutoProbe,tulip)\nendef\n\ndefine KernelPackage/tulip/description\n Kernel modules for the Tulip family of network cards,\n including DECchip Tulip, DIGITAL EtherWORKS, Winbond W89c840,\n Davicom DM910x/DM980x and ULi M526x controller support.\nendef\n\n$(eval $(call KernelPackage,tulip))\n\n\ndefine KernelPackage/solos-pci\n  SUBMENU:=$(NETWORK_DEVICES_MENU)\n  TITLE:=Solos ADSL2+ multiport modem\n  DEPENDS:=@PCI_SUPPORT +kmod-atm\n  KCONFIG:=CONFIG_ATM_SOLOS\n  FILES:=$(LINUX_DIR)/drivers/atm/solos-pci.ko\n  AUTOLOAD:=$(call AutoProbe,solos-pci)\nendef\n\ndefine KernelPackage/solos-pci/description\n Kernel module for Traverse Technologies' Solos PCI cards\n and Geos ADSL2+ x86 motherboard\nendef\n\n$(eval $(call KernelPackage,solos-pci))\n\n\ndefine KernelPackage/dummy\n  SUBMENU:=$(NETWORK_DEVICES_MENU)\n  TITLE:=Dummy network device\n  KCONFIG:=CONFIG_DUMMY\n  FILES:=$(LINUX_DIR)/drivers/net/dummy.ko\n  AUTOLOAD:=$(call AutoLoad,34,dummy)\nendef\n\ndefine KernelPackage/dummy/description\n The dummy network device\nendef\n\n$(eval $(call KernelPackage,dummy))\n\n\ndefine KernelPackage/ifb\n  SUBMENU:=$(NETWORK_DEVICES_MENU)\n  TITLE:=Intermediate Functional Block support\n  KCONFIG:= \\\n\tCONFIG_IFB \\\n\tCONFIG_NET_CLS=y\n  FILES:=$(LINUX_DIR)/drivers/net/ifb.ko\n  AUTOLOAD:=$(call AutoLoad,34,ifb)\n  MODPARAMS.ifb:=numifbs=0\nendef\n\ndefine KernelPackage/ifb/description\n  The Intermediate Functional Block\nendef\n\n$(eval $(call KernelPackage,ifb))\n\n\ndefine KernelPackage/dm9000\n  SUBMENU:=$(NETWORK_DEVICES_MENU)\n  TITLE:=Davicom 9000 Ethernet support\n  DEPENDS:=+kmod-mii\n  KCONFIG:=CONFIG_DM9000 \\\n    CONFIG_DM9000_DEBUGLEVEL=4 \\\n    CONFIG_DM9000_FORCE_SIMPLE_PHY_POLL=y\n  FILES:=$(LINUX_DIR)/drivers/net/ethernet/davicom/dm9000.ko\n  AUTOLOAD:=$(call AutoLoad,34,dm9000)\nendef\n\ndefine KernelPackage/dm9000/description\n Kernel driver for Davicom 9000 Ethernet adapters.\nendef\n\n$(eval $(call KernelPackage,dm9000))\n\n\ndefine KernelPackage/forcedeth\n  SUBMENU:=$(NETWORK_DEVICES_MENU)\n  TITLE:=nForce Ethernet support\n  DEPENDS:=@PCI_SUPPORT\n  KCONFIG:=CONFIG_FORCEDETH\n  FILES:=$(LINUX_DIR)/drivers/net/ethernet/nvidia/forcedeth.ko\n  AUTOLOAD:=$(call AutoProbe,forcedeth)\nendef\n\ndefine KernelPackage/forcedeth/description\n Kernel driver for Nvidia Ethernet support\nendef\n\n$(eval $(call KernelPackage,forcedeth))\n\ndefine KernelPackage/fixed-phy\n  SUBMENU:=$(NETWORK_DEVICES_MENU)\n  TITLE:=MDIO Bus/PHY emulation with fixed speed/link PHYs\n  DEPENDS:=+kmod-libphy\n  KCONFIG:=CONFIG_FIXED_PHY\n  FILES:=$(LINUX_DIR)/drivers/net/phy/fixed_phy.ko\n  AUTOLOAD:=$(call AutoProbe,fixed_phy)\nendef\n\ndefine KernelPackage/fixed-phy/description\n Kernel driver for \"fixed\" MDIO Bus to cover the boards\n and devices that use PHYs that are not connected to the real MDIO bus.\nendef\n\n$(eval $(call KernelPackage,fixed-phy))\n\ndefine KernelPackage/of-mdio\n  SUBMENU:=$(NETWORK_DEVICES_MENU)\n  TITLE:=OpenFirmware MDIO support\n  DEPENDS:=+kmod-libphy +kmod-fixed-phy @!TARGET_x86\n  KCONFIG:=CONFIG_OF_MDIO\n  FILES:= \\\n\t$(LINUX_DIR)/drivers/of/of_mdio.ko@lt5.10 \\\n\t$(LINUX_DIR)/drivers/net/mdio/of_mdio.ko@ge5.10 \\\n\t$(LINUX_DIR)/drivers/net/mdio/fwnode_mdio.ko@ge5.15\n  AUTOLOAD:=$(call AutoLoad,41,of_mdio)\nendef\n\ndefine KernelPackage/of-mdio/description\n Kernel driver for OpenFirmware MDIO support\nendef\n\n$(eval $(call KernelPackage,of-mdio))\n\n\ndefine KernelPackage/vmxnet3\n  SUBMENU:=$(NETWORK_DEVICES_MENU)\n  TITLE:=VMware VMXNET3 ethernet driver\n  DEPENDS:=@PCI_SUPPORT\n  KCONFIG:=CONFIG_VMXNET3\n  FILES:=$(LINUX_DIR)/drivers/net/vmxnet3/vmxnet3.ko\n  AUTOLOAD:=$(call AutoLoad,35,vmxnet3)\nendef\n\ndefine KernelPackage/vmxnet3/description\n Kernel modules for VMware VMXNET3 ethernet adapters.\nendef\n\n$(eval $(call KernelPackage,vmxnet3))\n\n\ndefine KernelPackage/spi-ks8995\n  SUBMENU:=$(NETWORK_DEVICES_MENU)\n  TITLE:=Micrel/Kendin KS8995 Ethernet switch control\n  FILES:=$(LINUX_DIR)/drivers/net/phy/spi_ks8995.ko\n  KCONFIG:=CONFIG_MICREL_KS8995MA \\\n\tCONFIG_SPI=y \\\n\tCONFIG_SPI_MASTER=y\n  AUTOLOAD:=$(call AutoLoad,50,spi_ks8995)\nendef\n\ndefine KernelPackage/spi-ks8995/description\n  Kernel module for Micrel/Kendin KS8995 ethernet switch\nendef\n\n$(eval $(call KernelPackage,spi-ks8995))\n\n\ndefine KernelPackage/ethoc\n  SUBMENU:=$(NETWORK_DEVICES_MENU)\n  TITLE:=Opencore.org ethoc driver\n  DEPENDS:=+kmod-libphy\n  FILES:=$(LINUX_DIR)/drivers/net/ethernet/ethoc.ko\n  KCONFIG:=CONFIG_ETHOC\n  AUTOLOAD:=$(call AutoProbe,ethoc)\nendef\n\ndefine KernelPackage/ethoc/description\n  Kernel module for the Opencores.org ethernet adapter\nendef\n\n$(eval $(call KernelPackage,ethoc))\n\n\ndefine KernelPackage/bnx2\n  SUBMENU:=$(NETWORK_DEVICES_MENU)\n  TITLE:=BCM5706/5708/5709/5716 ethernet adapter driver\n  DEPENDS:=@PCI_SUPPORT +bnx2-firmware\n  FILES:=$(LINUX_DIR)/drivers/net/ethernet/broadcom/bnx2.ko\n  KCONFIG:=CONFIG_BNX2\n  AUTOLOAD:=$(call AutoProbe,bnx2)\nendef\n\ndefine KernelPackage/bnx2/description\n  Kernel module for the BCM5706/5708/5709/5716 ethernet adapter\nendef\n\n$(eval $(call KernelPackage,bnx2))\n\n\ndefine KernelPackage/bnx2x\n  SUBMENU:=$(NETWORK_DEVICES_MENU)\n  TITLE:=QLogic 5771x/578xx 10/20-Gigabit ethernet adapter driver\n  DEPENDS:=@PCI_SUPPORT +bnx2x-firmware +kmod-lib-crc32c +kmod-mdio +kmod-ptp +kmod-lib-zlib-inflate\n  FILES:=$(LINUX_DIR)/drivers/net/ethernet/broadcom/bnx2x/bnx2x.ko\n  KCONFIG:= \\\n\tCONFIG_BNX2X \\\n\tCONFIG_BNX2X_SRIOV=y\n  AUTOLOAD:=$(call AutoProbe,bnx2x)\nendef\n\ndefine KernelPackage/bnx2x/description\n  QLogic BCM57710/57711/57711E/57712/57712_MF/57800/57800_MF/57810/57810_MF/57840/57840_MF Driver\nendef\n\n$(eval $(call KernelPackage,bnx2x))\n\ndefine KernelPackage/be2net\n  SUBMENU:=$(NETWORK_DEVICES_MENU)\n  TITLE:=Broadcom Emulex OneConnect 10Gbps NIC\n  DEPENDS:=@PCI_SUPPORT +kmod-hwmon-core\n  FILES:=$(LINUX_DIR)/drivers/net/ethernet/emulex/benet/be2net.ko\n  KCONFIG:= \\\n\tCONFIG_BE2NET \\\n\tCONFIG_BE2NET_BE2=y \\\n\tCONFIG_BE2NET_BE3=y \\\n\tCONFIG_BE2NET_LANCER=y \\\n\tCONFIG_BE2NET_SKYHAWK=y \\\n\tCONFIG_BE2NET_HWMON=y\n  AUTOLOAD:=$(call AutoProbe,be2net)\nendef\n\ndefine KernelPackage/be2net/description\n  Broadcom Emulex OneConnect 10Gbit SFP+ support, OneConnect OCe10xxx OCe11xxx OCe14xxx, LightPulse LPe12xxx\nendef\n\n$(eval $(call KernelPackage,be2net))\n\ndefine KernelPackage/mlx4-core\n  SUBMENU:=$(NETWORK_DEVICES_MENU)\n  TITLE:=Mellanox ConnectX(R) mlx4 core Network Driver\n  DEPENDS:=@PCI_SUPPORT +kmod-ptp\n  FILES:= \\\n\t$(LINUX_DIR)/drivers/net/ethernet/mellanox/mlx4/mlx4_core.ko \\\n\t$(LINUX_DIR)/drivers/net/ethernet/mellanox/mlx4/mlx4_en.ko\n  KCONFIG:= CONFIG_MLX4_EN \\\n\tCONFIG_MLX4_EN_DCB=n \\\n\tCONFIG_MLX4_CORE=y \\\n\tCONFIG_MLX4_CORE_GEN2=y \\\n\tCONFIG_MLX4_DEBUG=n\n  AUTOLOAD:=$(call AutoProbe,mlx4_core mlx4_en)\nendef\n\ndefine KernelPackage/mlx4-core/description\n  Supports Mellanox ConnectX-3 series and previous cards\nendef\n\n$(eval $(call KernelPackage,mlx4-core))\n\ndefine KernelPackage/mlx5-core\n  SUBMENU:=$(NETWORK_DEVICES_MENU)\n  TITLE:=Mellanox ConnectX(R) mlx5 core Network Driver\n  DEPENDS:=@PCI_SUPPORT +kmod-ptp\n  FILES:=$(LINUX_DIR)/drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.ko\n  KCONFIG:= CONFIG_MLX5_CORE \\\n\tCONFIG_MLX5_CORE_EN=y \\\n\tCONFIG_MLX5_CORE_EN_DCB=n \\\n\tCONFIG_MLX5_CORE_IPOIB=n \\\n\tCONFIG_MLX5_EN_ARFS=n \\\n\tCONFIG_MLX5_EN_IPSEC=n \\\n\tCONFIG_MLX5_EN_RXNFC=y \\\n\tCONFIG_MLX5_EN_TLS=n \\\n\tCONFIG_MLX5_ESWITCH=n \\\n\tCONFIG_MLX5_FPGA=n \\\n\tCONFIG_MLX5_FPGA_IPSEC=n \\\n\tCONFIG_MLX5_FPGA_TLS=n \\\n\tCONFIG_MLX5_MPFS=y \\\n\tCONFIG_MLX5_SW_STEERING=n \\\n\tCONFIG_MLX5_TC_CT=n \\\n\tCONFIG_MLX5_TLS=n\n  AUTOLOAD:=$(call AutoProbe,mlx5_core)\nendef\n\ndefine KernelPackage/mlx5-core/description\n  Supports Mellanox Connect-IB/ConnectX-4 series and later cards\nendef\n\n$(eval $(call KernelPackage,mlx5-core))\n\n\ndefine KernelPackage/net-selftests\n  SUBMENU:=$(NETWORK_DEVICES_MENU)\n  DEPENDS:=+kmod-libphy\n  TITLE:=Network generic selftest support\n  KCONFIG:=CONFIG_NET_SELFTESTS\n  FILES:=$(LINUX_DIR)/net/core/selftests.ko\n  AUTOLOAD:=$(call AutoLoad,99,selftests)\nendef\n\ndefine KernelPackage/net-selftests/description\n  Kernel modules for the generic selftest support\nendef\n\n$(eval $(call KernelPackage,net-selftests))\n\n\ndefine KernelPackage/qlcnic\n  SUBMENU:=$(NETWORK_DEVICES_MENU)\n  DEPENDS:=@PCI_SUPPORT +kmod-hwmon-core\n  TITLE:=QLogic QLE8240 and QLE8242 device support\n  KCONFIG:= \\\n\tCONFIG_QLCNIC \\\n\tCONFIG_QLCNIC_HWMON=y \\\n\tCONFIG_QLCNIC_SRIOV=y\n  FILES:=$(LINUX_DIR)/drivers/net/ethernet/qlogic/qlcnic/qlcnic.ko\n  AUTOLOAD:=$(call AutoProbe,qlcnic)\nendef\n\ndefine KernelPackage/qlcnic/description\n  This driver supports QLogic QLE8240 and QLE8242 Converged Ethernet\n  devices.\nendef\n\n$(eval $(call KernelPackage,qlcnic))\n\n\ndefine KernelPackage/sfp\n  SUBMENU:=$(NETWORK_DEVICES_MENU)\n  TITLE:=SFP cage support\n  DEPENDS:=+kmod-i2c-core +kmod-hwmon-core +kmod-phylink\n  KCONFIG:= \\\n\tCONFIG_SFP \\\n\tCONFIG_MDIO_I2C\n  FILES:= \\\n\t$(LINUX_DIR)/drivers/net/phy/sfp.ko \\\n\t$(LINUX_DIR)/drivers/net/phy/mdio-i2c.ko@lt5.10 \\\n\t$(LINUX_DIR)/drivers/net/mdio/mdio-i2c.ko@ge5.10\n  AUTOLOAD:=$(call AutoProbe,mdio-i2c sfp)\nendef\n\ndefine KernelPackage/sfp/description\n Kernel module to support SFP cages\nendef\n\n$(eval $(call KernelPackage,sfp))\n\ndefine KernelPackage/igc\n  SUBMENU:=$(NETWORK_DEVICES_MENU)\n  TITLE:=Intel(R) Ethernet Controller I225 Series support\n  DEPENDS:=@PCI_SUPPORT +kmod-ptp\n  KCONFIG:=CONFIG_IGC\n  FILES:=$(LINUX_DIR)/drivers/net/ethernet/intel/igc/igc.ko\n  AUTOLOAD:=$(call AutoProbe,igc)\nendef\n\ndefine KernelPackage/igc/description\n  Kernel modules for Intel(R) Ethernet Controller I225 Series\nendef\n\n$(eval $(call KernelPackage,igc))\n\ndefine KernelPackage/sfc\n  SUBMENU:=$(NETWORK_DEVICES_MENU)\n  TITLE:=Solarflare SFC9000/SFC9100/EF100-family support\n  DEPENDS:=@PCI_SUPPORT +kmod-mdio +kmod-lib-crc32c +kmod-ptp +kmod-hwmon-core\n  KCONFIG:= \\\n\tCONFIG_SFC \\\n\tCONFIG_SFC_MTD=y \\\n\tCONFIG_SFC_MCDI_MON=y \\\n\tCONFIG_SFC_MCDI_LOGGING=y \\\n\tCONFIG_SFC_SRIOV=y\n  FILES:=$(LINUX_DIR)/drivers/net/ethernet/sfc/sfc.ko\n  AUTOLOAD:=$(call AutoProbe,sfc)\nendef\n\ndefine KernelPackage/sfc/description\n  Solarflare SFC9000/SFC9100/EF100-family support\n  Solarflare EF100 support requires at least kernel version 5.9\nendef\n\n$(eval $(call KernelPackage,sfc))\n\ndefine KernelPackage/sfc-falcon\n  SUBMENU:=$(NETWORK_DEVICES_MENU)\n  TITLE:=Solarflare SFC4000 support\n  DEPENDS:=@PCI_SUPPORT +kmod-mdio +kmod-lib-crc32c +kmod-i2c-algo-bit\n  KCONFIG:= \\\n\tCONFIG_SFC_FALCON \\\n\tCONFIG_SFC_FALCON_MTD=y\n  FILES:=$(LINUX_DIR)/drivers/net/ethernet/sfc/falcon/sfc-falcon.ko\n  AUTOLOAD:=$(call AutoProbe,sfc-falcon)\nendef\n\ndefine KernelPackage/sfc-falcon/description\n  Solarflare SFC4000 support\nendef\n\n$(eval $(call KernelPackage,sfc-falcon))\n\ndefine KernelPackage/mhi-net\n  SUBMENU:=$(NETWORK_DEVICES_MENU)\n  TITLE:=MHI Network Device\n  DEPENDS:=@LINUX_5_15 @PCI_SUPPORT +kmod-mhi-bus\n  KCONFIG:=CONFIG_MHI_NET\n  FILES:=$(LINUX_DIR)/drivers/net/mhi_net.ko\n  AUTOLOAD:=$(call AutoProbe,mhi_net)\nendef\n\ndefine KernelPackage/mhi-net/description\n Driver for MHI network interface\nendef\n\n$(eval $(call KernelPackage,mhi-net))\n\ndefine KernelPackage/mhi-wwan-ctrl\n  SUBMENU:=$(NETWORK_DEVICES_MENU)\n  TITLE:=MHI WWAN Control\n  DEPENDS:=@LINUX_5_15 @PCI_SUPPORT +kmod-mhi-bus\n  KCONFIG:=CONFIG_MHI_WWAN_CTRL\n  FILES:=$(LINUX_DIR)/drivers/net/mhi_wwan_ctrl.ko\n  AUTOLOAD:=$(call AutoProbe,mhi_wwan_ctrl)\nendef\n\ndefine KernelPackage/mhi-wwan-ctrl/description\n Driver for MHI WWAN Control\n This exposes all modem control ports like AT, MBIM, QMI, DIAG, ..\nendef\n\n$(eval $(call KernelPackage,mhi-wwan-ctrl))\n\ndefine KernelPackage/mhi-wwan-mbim\n  SUBMENU:=$(NETWORK_DEVICES_MENU)\n  TITLE:=MHI MBIM\n  DEPENDS:=@LINUX_5_15 @PCI_SUPPORT +kmod-mhi-bus\n  KCONFIG:=CONFIG_MHI_WWAN_MBIM\n  FILES:=$(LINUX_DIR)/drivers/net/mhi_wwan_mbim.ko\n  AUTOLOAD:=$(call AutoProbe,mhi_wwan_mbim)\nendef\n\ndefine KernelPackage/mhi-wwan-mbim/description\n Driver for MHI MBIM\n This implements MBIM over MHI\nendef\n\n$(eval $(call KernelPackage,mhi-wwan-mbim))\n"
  },
  {
    "path": "package/kernel/linux/modules/netfilter.mk",
    "content": "\n#\n# Copyright (C) 2006-2010 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\nNF_MENU:=Netfilter Extensions\nNF_KMOD:=1\ninclude $(INCLUDE_DIR)/netfilter.mk\n\n\ndefine KernelPackage/nf-reject\n  SUBMENU:=$(NF_MENU)\n  TITLE:=Netfilter IPv4 reject support\n  KCONFIG:= \\\n\tCONFIG_NETFILTER=y \\\n\tCONFIG_NETFILTER_ADVANCED=y \\\n\t$(KCONFIG_NF_REJECT)\n  FILES:=$(foreach mod,$(NF_REJECT-m),$(LINUX_DIR)/net/$(mod).ko)\n  AUTOLOAD:=$(call AutoProbe,$(notdir $(NF_REJECT-m)))\nendef\n\n$(eval $(call KernelPackage,nf-reject))\n\n\ndefine KernelPackage/nf-reject6\n  SUBMENU:=$(NF_MENU)\n  TITLE:=Netfilter IPv6 reject support\n  KCONFIG:= \\\n\tCONFIG_NETFILTER=y \\\n\tCONFIG_NETFILTER_ADVANCED=y \\\n\t$(KCONFIG_NF_REJECT6)\n  DEPENDS:=@IPV6\n  FILES:=$(foreach mod,$(NF_REJECT6-m),$(LINUX_DIR)/net/$(mod).ko)\n  AUTOLOAD:=$(call AutoProbe,$(notdir $(NF_REJECT6-m)))\nendef\n\n$(eval $(call KernelPackage,nf-reject6))\n\n\ndefine KernelPackage/nf-ipt\n  SUBMENU:=$(NF_MENU)\n  TITLE:=Iptables core\n  KCONFIG:=$(KCONFIG_NF_IPT)\n  FILES:=$(foreach mod,$(NF_IPT-m),$(LINUX_DIR)/net/$(mod).ko)\n  AUTOLOAD:=$(call AutoProbe,$(notdir $(NF_IPT-m)))\nendef\n\n$(eval $(call KernelPackage,nf-ipt))\n\n\ndefine KernelPackage/nf-ipt6\n  SUBMENU:=$(NF_MENU)\n  TITLE:=Ip6tables core\n  KCONFIG:=$(KCONFIG_NF_IPT6)\n  FILES:=$(foreach mod,$(NF_IPT6-m),$(LINUX_DIR)/net/$(mod).ko)\n  AUTOLOAD:=$(call AutoProbe,$(notdir $(NF_IPT6-m)))\n  DEPENDS:=+kmod-nf-ipt +kmod-nf-log6\nendef\n\n$(eval $(call KernelPackage,nf-ipt6))\n\n\n\ndefine KernelPackage/ipt-core\n  SUBMENU:=$(NF_MENU)\n  TITLE:=Iptables core\n  KCONFIG:=$(KCONFIG_IPT_CORE)\n  FILES:=$(foreach mod,$(IPT_CORE-m),$(LINUX_DIR)/net/$(mod).ko)\n  AUTOLOAD:=$(call AutoProbe,$(notdir $(IPT_CORE-m)))\n  DEPENDS:=+kmod-nf-reject +kmod-nf-ipt +kmod-nf-log\nendef\n\ndefine KernelPackage/ipt-core/description\n Netfilter core kernel modules\n Includes:\n - comment\n - limit\n - LOG\n - mac\n - multiport\n - REJECT\n - TCPMSS\nendef\n\n$(eval $(call KernelPackage,ipt-core))\n\n\ndefine KernelPackage/nf-conntrack\n  SUBMENU:=$(NF_MENU)\n  TITLE:=Netfilter connection tracking\n  KCONFIG:= \\\n        CONFIG_NETFILTER=y \\\n        CONFIG_NETFILTER_ADVANCED=y \\\n        CONFIG_NF_CONNTRACK_MARK=y \\\n        CONFIG_NF_CONNTRACK_ZONES=y \\\n\t$(KCONFIG_NF_CONNTRACK)\n  FILES:=$(foreach mod,$(NF_CONNTRACK-m),$(LINUX_DIR)/net/$(mod).ko)\n  AUTOLOAD:=$(call AutoProbe,$(notdir $(NF_CONNTRACK-m)))\nendef\n\ndefine KernelPackage/nf-conntrack/install\n\t$(INSTALL_DIR) $(1)/etc/sysctl.d\n\t$(INSTALL_DATA) ./files/sysctl-nf-conntrack.conf $(1)/etc/sysctl.d/11-nf-conntrack.conf\nendef\n\n$(eval $(call KernelPackage,nf-conntrack))\n\n\ndefine KernelPackage/nf-conntrack6\n  SUBMENU:=$(NF_MENU)\n  TITLE:=Netfilter IPv6 connection tracking\n  KCONFIG:=$(KCONFIG_NF_CONNTRACK6)\n  DEPENDS:=@IPV6 +kmod-nf-conntrack\n  FILES:=$(foreach mod,$(NF_CONNTRACK6-m),$(LINUX_DIR)/net/$(mod).ko)\n  AUTOLOAD:=$(call AutoProbe,$(notdir $(NF_CONNTRACK6-m)))\nendef\n\n$(eval $(call KernelPackage,nf-conntrack6))\n\n\ndefine KernelPackage/nf-log\n  SUBMENU:=$(NF_MENU)\n  TITLE:=Netfilter Logging\n  KCONFIG:=$(KCONFIG_NF_LOG)\n  FILES:=$(foreach mod,$(NF_LOG-m),$(LINUX_DIR)/net/$(mod).ko)\n  AUTOLOAD:=$(call AutoProbe,$(notdir $(NF_LOG-m)))\nendef\n\n$(eval $(call KernelPackage,nf-log))\n\n\ndefine KernelPackage/nf-log6\n  SUBMENU:=$(NF_MENU)\n  TITLE:=Netfilter IPV6 Logging\n  KCONFIG:=$(KCONFIG_NF_LOG6)\n  DEPENDS:=@IPV6 +kmod-nf-log\n  FILES:=$(foreach mod,$(NF_LOG6-m),$(LINUX_DIR)/net/$(mod).ko)\n  AUTOLOAD:=$(call AutoProbe,$(notdir $(NF_LOG6-m)))\nendef\n\n$(eval $(call KernelPackage,nf-log6))\n\n\ndefine KernelPackage/nf-nat\n  SUBMENU:=$(NF_MENU)\n  TITLE:=Netfilter NAT\n  KCONFIG:=$(KCONFIG_NF_NAT)\n  DEPENDS:=+kmod-nf-conntrack\n  FILES:=$(foreach mod,$(NF_NAT-m),$(LINUX_DIR)/net/$(mod).ko)\n  AUTOLOAD:=$(call AutoProbe,$(notdir $(NF_NAT-m)))\nendef\n\n$(eval $(call KernelPackage,nf-nat))\n\n\ndefine KernelPackage/nf-nat6\n  SUBMENU:=$(NF_MENU)\n  TITLE:=Netfilter IPV6-NAT\n  KCONFIG:=$(KCONFIG_NF_NAT6)\n  DEPENDS:=@IPV6 +kmod-nf-conntrack6 +kmod-nf-nat\n  FILES:=$(foreach mod,$(NF_NAT6-m),$(LINUX_DIR)/net/$(mod).ko)\n  AUTOLOAD:=$(call AutoProbe,$(notdir $(NF_NAT6-m)))\nendef\n\n$(eval $(call KernelPackage,nf-nat6))\n\n\ndefine KernelPackage/nf-flow\n  SUBMENU:=$(NF_MENU)\n  TITLE:=Netfilter flowtable support\n  KCONFIG:= \\\n\tCONFIG_NETFILTER_INGRESS=y \\\n\tCONFIG_NF_FLOW_TABLE \\\n\tCONFIG_NF_FLOW_TABLE_HW\n  DEPENDS:=+kmod-nf-conntrack\n  FILES:= \\\n\t$(LINUX_DIR)/net/netfilter/nf_flow_table.ko \\\n\t$(if $(CONFIG_LINUX_5_4),$(LINUX_DIR)/net/netfilter/nf_flow_table_hw.ko)\n  AUTOLOAD:=$(call AutoProbe,nf_flow_table nf_flow_table_hw)\nendef\n\n$(eval $(call KernelPackage,nf-flow))\n\n\ndefine KernelPackage/nf-socket\n  SUBMENU:=$(NF_MENU)\n  TITLE:=Netfilter socket lookup support\n  KCONFIG:= $(KCOFNIG_NF_SOCKET)\n  FILES:=$(foreach mod,$(NF_SOCKET-m),$(LINUX_DIR)/net/$(mod).ko)\n  AUTOLOAD:=$(call AutoProbe,$(notdir $(NF_SOCKET-m)))\nendef\n\n$(eval $(call KernelPackage,nf-socket))\n\n\ndefine KernelPackage/nf-tproxy\n  SUBMENU:=$(NF_MENU)\n  TITLE:=Netfilter tproxy support\n  KCONFIG:= $(KCOFNIG_NF_TPROXY)\n  FILES:=$(foreach mod,$(NF_TPROXY-m),$(LINUX_DIR)/net/$(mod).ko)\n  AUTOLOAD:=$(call AutoProbe,$(notdir $(NF_TPROXY-m)))\nendef\n\n$(eval $(call KernelPackage,nf-tproxy))\n\n\ndefine AddDepends/ipt\n  SUBMENU:=$(NF_MENU)\n  DEPENDS+= +kmod-ipt-core $(1)\nendef\n\n\ndefine KernelPackage/ipt-conntrack\n  TITLE:=Basic connection tracking modules\n  KCONFIG:=$(KCONFIG_IPT_CONNTRACK)\n  FILES:=$(foreach mod,$(IPT_CONNTRACK-m),$(LINUX_DIR)/net/$(mod).ko)\n  AUTOLOAD:=$(call AutoProbe,$(notdir $(IPT_CONNTRACK-m)))\n  $(call AddDepends/ipt,+kmod-nf-conntrack)\nendef\n\ndefine KernelPackage/ipt-conntrack/description\n Netfilter (IPv4) kernel modules for connection tracking\n Includes:\n - conntrack\n - defrag\n - iptables_raw\n - NOTRACK\n - state\nendef\n\n$(eval $(call KernelPackage,ipt-conntrack))\n\n\ndefine KernelPackage/ipt-conntrack-extra\n  TITLE:=Extra connection tracking modules\n  KCONFIG:=$(KCONFIG_IPT_CONNTRACK_EXTRA)\n  FILES:=$(foreach mod,$(IPT_CONNTRACK_EXTRA-m),$(LINUX_DIR)/net/$(mod).ko)\n  AUTOLOAD:=$(call AutoProbe,$(notdir $(IPT_CONNTRACK_EXTRA-m)))\n  $(call AddDepends/ipt,+kmod-ipt-conntrack)\nendef\n\ndefine KernelPackage/ipt-conntrack-extra/description\n Netfilter (IPv4) extra kernel modules for connection tracking\n Includes:\n - connbytes\n - connmark/CONNMARK\n - conntrack\n - helper\n - recent\nendef\n\n$(eval $(call KernelPackage,ipt-conntrack-extra))\n\ndefine KernelPackage/ipt-conntrack-label\n  TITLE:=Module for handling connection tracking labels\n  KCONFIG:=$(KCONFIG_IPT_CONNTRACK_LABEL)\n  FILES:=$(foreach mod,$(IPT_CONNTRACK_LABEL-m),$(LINUX_DIR)/net/$(mod).ko)\n  AUTOLOAD:=$(call AutoProbe,$(notdir $(IPT_CONNTRACK_LABEL-m)))\n  $(call AddDepends/ipt,+kmod-ipt-conntrack)\nendef\n\ndefine KernelPackage/ipt-conntrack-label/description\n Netfilter (IPv4) module for handling connection tracking labels\n Includes:\n - connlabel\nendef\n\n$(eval $(call KernelPackage,ipt-conntrack-label))\n\ndefine KernelPackage/ipt-filter\n  TITLE:=Modules for packet content inspection\n  KCONFIG:=$(KCONFIG_IPT_FILTER)\n  FILES:=$(foreach mod,$(IPT_FILTER-m),$(LINUX_DIR)/net/$(mod).ko)\n  AUTOLOAD:=$(call AutoProbe,$(notdir $(IPT_FILTER-m)))\n  $(call AddDepends/ipt,+kmod-lib-textsearch +kmod-ipt-conntrack)\nendef\n\ndefine KernelPackage/ipt-filter/description\n Netfilter (IPv4) kernel modules for packet content inspection\n Includes:\n - string\n - bpf\nendef\n\n$(eval $(call KernelPackage,ipt-filter))\n\n\ndefine KernelPackage/ipt-offload\n  TITLE:=Netfilter routing/NAT offload support\n  KCONFIG:=$(KCONFIG_IPT_FLOW)\n  FILES:=$(foreach mod,$(IPT_FLOW-m),$(LINUX_DIR)/net/$(mod).ko)\n  AUTOLOAD:=$(call AutoProbe,$(notdir $(IPT_FLOW-m)))\n  $(call AddDepends/ipt,+kmod-nf-flow)\nendef\n\n$(eval $(call KernelPackage,ipt-offload))\n\n\ndefine KernelPackage/ipt-ipopt\n  TITLE:=Modules for matching/changing IP packet options\n  KCONFIG:=$(KCONFIG_IPT_IPOPT)\n  FILES:=$(foreach mod,$(IPT_IPOPT-m),$(LINUX_DIR)/net/$(mod).ko)\n  AUTOLOAD:=$(call AutoProbe,$(notdir $(IPT_IPOPT-m)))\n  $(call AddDepends/ipt)\nendef\n\ndefine KernelPackage/ipt-ipopt/description\n Netfilter (IPv4) modules for matching/changing IP packet options\n Includes:\n - CLASSIFY\n - dscp/DSCP\n - ecn/ECN\n - hl/HL\n - length\n - mark/MARK\n - statistic\n - tcpmss\n - time\n - ttl/TTL\n - unclean\nendef\n\n$(eval $(call KernelPackage,ipt-ipopt))\n\n\ndefine KernelPackage/ipt-ipsec\n  TITLE:=Modules for matching IPSec packets\n  KCONFIG:=$(KCONFIG_IPT_IPSEC)\n  FILES:=$(foreach mod,$(IPT_IPSEC-m),$(LINUX_DIR)/net/$(mod).ko)\n  AUTOLOAD:=$(call AutoProbe,$(notdir $(IPT_IPSEC-m)))\n  $(call AddDepends/ipt)\nendef\n\ndefine KernelPackage/ipt-ipsec/description\n Netfilter (IPv4) modules for matching IPSec packets\n Includes:\n - ah\n - esp\n - policy\nendef\n\n$(eval $(call KernelPackage,ipt-ipsec))\n\nIPSET_MODULES:= \\\n\tipset/ip_set \\\n\tipset/ip_set_bitmap_ip \\\n\tipset/ip_set_bitmap_ipmac \\\n\tipset/ip_set_bitmap_port \\\n\tipset/ip_set_hash_ip \\\n\tipset/ip_set_hash_ipmark \\\n\tipset/ip_set_hash_ipport \\\n\tipset/ip_set_hash_ipportip \\\n\tipset/ip_set_hash_ipportnet \\\n\tipset/ip_set_hash_mac \\\n\tipset/ip_set_hash_netportnet \\\n\tipset/ip_set_hash_net \\\n\tipset/ip_set_hash_netnet \\\n\tipset/ip_set_hash_netport \\\n\tipset/ip_set_hash_netiface \\\n\tipset/ip_set_list_set \\\n\txt_set\n\ndefine KernelPackage/ipt-ipset\n  SUBMENU:=Netfilter Extensions\n  TITLE:=IPset netfilter modules\n  DEPENDS+= +kmod-ipt-core +kmod-nfnetlink\n  KCONFIG:= \\\n\tCONFIG_IP_SET \\\n\tCONFIG_IP_SET_MAX=256 \\\n\tCONFIG_NETFILTER_XT_SET \\\n\tCONFIG_IP_SET_BITMAP_IP \\\n\tCONFIG_IP_SET_BITMAP_IPMAC \\\n\tCONFIG_IP_SET_BITMAP_PORT \\\n\tCONFIG_IP_SET_HASH_IP \\\n\tCONFIG_IP_SET_HASH_IPMAC \\\n\tCONFIG_IP_SET_HASH_IPMARK \\\n\tCONFIG_IP_SET_HASH_IPPORT \\\n\tCONFIG_IP_SET_HASH_IPPORTIP \\\n\tCONFIG_IP_SET_HASH_IPPORTNET \\\n\tCONFIG_IP_SET_HASH_MAC \\\n\tCONFIG_IP_SET_HASH_NET \\\n\tCONFIG_IP_SET_HASH_NETNET \\\n\tCONFIG_IP_SET_HASH_NETIFACE \\\n\tCONFIG_IP_SET_HASH_NETPORT \\\n\tCONFIG_IP_SET_HASH_NETPORTNET \\\n\tCONFIG_IP_SET_LIST_SET \\\n\tCONFIG_NET_EMATCH_IPSET=n\n  FILES:=$(foreach mod,$(IPSET_MODULES),$(LINUX_DIR)/net/netfilter/$(mod).ko)\n  AUTOLOAD:=$(call AutoLoad,49,$(notdir $(IPSET_MODULES)))\nendef\n$(eval $(call KernelPackage,ipt-ipset))\n\n\nIPVS_MODULES:= \\\n\tipvs/ip_vs \\\n\tipvs/ip_vs_lc \\\n\tipvs/ip_vs_wlc \\\n\tipvs/ip_vs_rr \\\n\tipvs/ip_vs_wrr \\\n\tipvs/ip_vs_lblc \\\n\tipvs/ip_vs_lblcr \\\n\tipvs/ip_vs_dh \\\n\tipvs/ip_vs_sh \\\n\tipvs/ip_vs_fo \\\n\tipvs/ip_vs_ovf \\\n\tipvs/ip_vs_nq \\\n\tipvs/ip_vs_sed \\\n\txt_ipvs\n\ndefine KernelPackage/nf-ipvs\n  SUBMENU:=Netfilter Extensions\n  TITLE:=IP Virtual Server modules\n  DEPENDS:=@IPV6 +kmod-lib-crc32c +kmod-ipt-conntrack +kmod-nf-conntrack\n  KCONFIG:= \\\n\tCONFIG_IP_VS \\\n\tCONFIG_IP_VS_IPV6=y \\\n\tCONFIG_IP_VS_DEBUG=n \\\n\tCONFIG_IP_VS_PROTO_TCP=y \\\n\tCONFIG_IP_VS_PROTO_UDP=y \\\n\tCONFIG_IP_VS_PROTO_AH_ESP=y \\\n\tCONFIG_IP_VS_PROTO_ESP=y \\\n\tCONFIG_IP_VS_PROTO_AH=y \\\n\tCONFIG_IP_VS_PROTO_SCTP=y \\\n\tCONFIG_IP_VS_TAB_BITS=12 \\\n\tCONFIG_IP_VS_RR \\\n\tCONFIG_IP_VS_WRR \\\n\tCONFIG_IP_VS_LC \\\n\tCONFIG_IP_VS_WLC \\\n\tCONFIG_IP_VS_FO \\\n\tCONFIG_IP_VS_OVF \\\n\tCONFIG_IP_VS_LBLC \\\n\tCONFIG_IP_VS_LBLCR \\\n\tCONFIG_IP_VS_DH \\\n\tCONFIG_IP_VS_SH \\\n\tCONFIG_IP_VS_SED \\\n\tCONFIG_IP_VS_NQ \\\n\tCONFIG_IP_VS_SH_TAB_BITS=8 \\\n\tCONFIG_IP_VS_NFCT=y \\\n\tCONFIG_NETFILTER_XT_MATCH_IPVS\n  FILES:=$(foreach mod,$(IPVS_MODULES),$(LINUX_DIR)/net/netfilter/$(mod).ko)\n  $(call AddDepends/ipt,+kmod-ipt-conntrack,+kmod-nf-conntrack)\nendef\n\ndefine KernelPackage/nf-ipvs/description\n IPVS (IP Virtual Server) implements transport-layer load balancing inside\n the Linux kernel so called Layer-4 switching.\nendef\n\n$(eval $(call KernelPackage,nf-ipvs))\n\n\ndefine KernelPackage/nf-ipvs-ftp\n  SUBMENU:=$(NF_MENU)\n  TITLE:=Virtual Server FTP protocol support\n  KCONFIG:=CONFIG_IP_VS_FTP\n  DEPENDS:=kmod-nf-ipvs +kmod-nf-nat +kmod-nf-nathelper\n  FILES:=$(LINUX_DIR)/net/netfilter/ipvs/ip_vs_ftp.ko\nendef\n\ndefine KernelPackage/nf-ipvs-ftp/description\n  In the virtual server via Network Address Translation,\n  the IP address and port number of real servers cannot be sent to\n  clients in ftp connections directly, so FTP protocol helper is\n  required for tracking the connection and mangling it back to that of\n  virtual service.\nendef\n\n$(eval $(call KernelPackage,nf-ipvs-ftp))\n\n\ndefine KernelPackage/nf-ipvs-sip\n  SUBMENU:=$(NF_MENU)\n  TITLE:=Virtual Server SIP protocol support\n  KCONFIG:=CONFIG_IP_VS_PE_SIP\n  DEPENDS:=kmod-nf-ipvs +kmod-nf-nathelper-extra\n  FILES:=$(LINUX_DIR)/net/netfilter/ipvs/ip_vs_pe_sip.ko\nendef\n\ndefine KernelPackage/nf-ipvs-sip/description\n  Allow persistence based on the SIP Call-ID\nendef\n\n$(eval $(call KernelPackage,nf-ipvs-sip))\n\n\ndefine KernelPackage/ipt-nat\n  TITLE:=Basic NAT targets\n  KCONFIG:=$(KCONFIG_IPT_NAT)\n  FILES:=$(foreach mod,$(IPT_NAT-m),$(LINUX_DIR)/net/$(mod).ko)\n  AUTOLOAD:=$(call AutoProbe,$(notdir $(IPT_NAT-m)))\n  $(call AddDepends/ipt,+kmod-nf-nat)\nendef\n\ndefine KernelPackage/ipt-nat/description\n Netfilter (IPv4) kernel modules for basic NAT targets\n Includes:\n - MASQUERADE\nendef\n\n$(eval $(call KernelPackage,ipt-nat))\n\n\ndefine KernelPackage/ipt-raw\n  TITLE:=Netfilter IPv4 raw table support\n  KCONFIG:=CONFIG_IP_NF_RAW\n  FILES:=$(LINUX_DIR)/net/ipv4/netfilter/iptable_raw.ko\n  AUTOLOAD:=$(call AutoProbe,iptable_raw)\n  $(call AddDepends/ipt)\nendef\n\n$(eval $(call KernelPackage,ipt-raw))\n\n\ndefine KernelPackage/ipt-raw6\n  TITLE:=Netfilter IPv6 raw table support\n  DEPENDS:=@IPV6\n  KCONFIG:=CONFIG_IP6_NF_RAW\n  FILES:=$(LINUX_DIR)/net/ipv6/netfilter/ip6table_raw.ko\n  AUTOLOAD:=$(call AutoProbe,ip6table_raw)\n  $(call AddDepends/ipt,+kmod-ip6tables)\nendef\n\n$(eval $(call KernelPackage,ipt-raw6))\n\n\ndefine KernelPackage/ipt-nat6\n  TITLE:=IPv6 NAT targets\n  DEPENDS:=@IPV6\n  KCONFIG:=$(KCONFIG_IPT_NAT6)\n  FILES:=$(foreach mod,$(IPT_NAT6-m),$(LINUX_DIR)/net/$(mod).ko)\n  AUTOLOAD:=$(call AutoLoad,43,$(notdir $(IPT_NAT6-m)))\n  $(call AddDepends/ipt,+kmod-nf-nat6)\n  $(call AddDepends/ipt,+kmod-ipt-conntrack)\n  $(call AddDepends/ipt,+kmod-ipt-nat)\n  $(call AddDepends/ipt,+kmod-ip6tables)\nendef\n\ndefine KernelPackage/ipt-nat6/description\n Netfilter (IPv6) kernel modules for NAT targets\nendef\n\n$(eval $(call KernelPackage,ipt-nat6))\n\n\ndefine KernelPackage/ipt-nat-extra\n  TITLE:=Extra NAT targets\n  KCONFIG:=$(KCONFIG_IPT_NAT_EXTRA)\n  FILES:=$(foreach mod,$(IPT_NAT_EXTRA-m),$(LINUX_DIR)/net/$(mod).ko)\n  AUTOLOAD:=$(call AutoProbe,$(notdir $(IPT_NAT_EXTRA-m)))\n  $(call AddDepends/ipt,+kmod-ipt-nat)\nendef\n\ndefine KernelPackage/ipt-nat-extra/description\n Netfilter (IPv4) kernel modules for extra NAT targets\n Includes:\n - NETMAP\n - REDIRECT\nendef\n\n$(eval $(call KernelPackage,ipt-nat-extra))\n\n\ndefine KernelPackage/nf-nathelper\n  SUBMENU:=$(NF_MENU)\n  TITLE:=Basic Conntrack and NAT helpers\n  KCONFIG:=$(KCONFIG_NF_NATHELPER)\n  FILES:=$(foreach mod,$(NF_NATHELPER-m),$(LINUX_DIR)/net/$(mod).ko)\n  AUTOLOAD:=$(call AutoProbe,$(notdir $(NF_NATHELPER-m)))\n  DEPENDS:=+kmod-nf-nat\nendef\n\ndefine KernelPackage/nf-nathelper/description\n Default Netfilter (IPv4) Conntrack and NAT helpers\n Includes:\n - ftp\nendef\n\n$(eval $(call KernelPackage,nf-nathelper))\n\n\ndefine KernelPackage/nf-nathelper-extra\n  SUBMENU:=$(NF_MENU)\n  TITLE:=Extra Conntrack and NAT helpers\n  KCONFIG:=$(KCONFIG_NF_NATHELPER_EXTRA)\n  FILES:=$(foreach mod,$(NF_NATHELPER_EXTRA-m),$(LINUX_DIR)/net/$(mod).ko)\n  AUTOLOAD:=$(call AutoProbe,$(notdir $(NF_NATHELPER_EXTRA-m)))\n  DEPENDS:=+kmod-nf-nat +kmod-lib-textsearch +kmod-asn1-decoder\nendef\n\ndefine KernelPackage/nf-nathelper-extra/description\n Extra Netfilter (IPv4) Conntrack and NAT helpers\n Includes:\n - amanda\n - h323\n - irc\n - mms\n - pptp\n - proto_gre\n - sip\n - snmp_basic\n - tftp\n - broadcast\nendef\n\n$(eval $(call KernelPackage,nf-nathelper-extra))\n\n\ndefine KernelPackage/ipt-ulog\n  TITLE:=Module for user-space packet logging\n  KCONFIG:=$(KCONFIG_IPT_ULOG)\n  FILES:=$(foreach mod,$(IPT_ULOG-m),$(LINUX_DIR)/net/$(mod).ko)\n  AUTOLOAD:=$(call AutoProbe,$(notdir $(IPT_ULOG-m)))\n  $(call AddDepends/ipt)\nendef\n\ndefine KernelPackage/ipt-ulog/description\n Netfilter (IPv4) module for user-space packet logging\n Includes:\n - ULOG\nendef\n\n$(eval $(call KernelPackage,ipt-ulog))\n\n\ndefine KernelPackage/ipt-nflog\n  TITLE:=Module for user-space packet logging\n  KCONFIG:=$(KCONFIG_IPT_NFLOG)\n  FILES:=$(foreach mod,$(IPT_NFLOG-m),$(LINUX_DIR)/net/$(mod).ko)\n  AUTOLOAD:=$(call AutoProbe,$(notdir $(IPT_NFLOG-m)))\n  $(call AddDepends/ipt,+kmod-nfnetlink-log)\nendef\n\ndefine KernelPackage/ipt-nflog/description\n Netfilter module for user-space packet logging\n Includes:\n - NFLOG\nendef\n\n$(eval $(call KernelPackage,ipt-nflog))\n\n\ndefine KernelPackage/ipt-nfqueue\n  TITLE:=Module for user-space packet queuing\n  KCONFIG:=$(KCONFIG_IPT_NFQUEUE)\n  FILES:=$(foreach mod,$(IPT_NFQUEUE-m),$(LINUX_DIR)/net/$(mod).ko)\n  AUTOLOAD:=$(call AutoProbe,$(notdir $(IPT_NFQUEUE-m)))\n  $(call AddDepends/ipt,+kmod-nfnetlink-queue)\nendef\n\ndefine KernelPackage/ipt-nfqueue/description\n Netfilter module for user-space packet queuing\n Includes:\n - NFQUEUE\nendef\n\n$(eval $(call KernelPackage,ipt-nfqueue))\n\n\ndefine KernelPackage/ipt-debug\n  TITLE:=Module for debugging/development\n  KCONFIG:=$(KCONFIG_IPT_DEBUG)\n  FILES:=$(foreach mod,$(IPT_DEBUG-m),$(LINUX_DIR)/net/$(mod).ko)\n  AUTOLOAD:=$(call AutoProbe,$(notdir $(IPT_DEBUG-m)))\n  $(call AddDepends/ipt,+kmod-ipt-raw +IPV6:kmod-ipt-raw6)\nendef\n\ndefine KernelPackage/ipt-debug/description\n Netfilter modules for debugging/development of the firewall\n Includes:\n - TRACE\nendef\n\n$(eval $(call KernelPackage,ipt-debug))\n\n\ndefine KernelPackage/ipt-led\n  TITLE:=Module to trigger a LED with a Netfilter rule\n  KCONFIG:=$(KCONFIG_IPT_LED)\n  FILES:=$(foreach mod,$(IPT_LED-m),$(LINUX_DIR)/net/$(mod).ko)\n  AUTOLOAD:=$(call AutoProbe,$(notdir $(IPT_LED-m)))\n  $(call AddDepends/ipt)\nendef\n\ndefine KernelPackage/ipt-led/description\n Netfilter target to trigger a LED when a network packet is matched.\nendef\n\n$(eval $(call KernelPackage,ipt-led))\n\ndefine KernelPackage/ipt-socket\n  TITLE:=Iptables socket matching support\n  DEPENDS+=+kmod-nf-socket +kmod-nf-conntrack\n  KCONFIG:=$(KCONFIG_IPT_SOCKET)\n  FILES:=$(foreach mod,$(IPT_SOCKET-m),$(LINUX_DIR)/net/$(mod).ko)\n  AUTOLOAD:=$(call AutoProbe,$(notdir $(IPT_SOCKET-m)))\n  $(call AddDepends/ipt)\nendef\n\ndefine KernelPackage/ipt-socket/description\n  Kernel modules for socket matching\nendef\n\n$(eval $(call KernelPackage,ipt-socket))\n\ndefine KernelPackage/ipt-tproxy\n  TITLE:=Transparent proxying support\n  DEPENDS+=+kmod-nf-tproxy +kmod-nf-conntrack\n  KCONFIG:=$(KCONFIG_IPT_TPROXY)\n  FILES:=$(foreach mod,$(IPT_TPROXY-m),$(LINUX_DIR)/net/$(mod).ko)\n  AUTOLOAD:=$(call AutoProbe,$(notdir $(IPT_TPROXY-m)))\n  $(call AddDepends/ipt)\nendef\n\ndefine KernelPackage/ipt-tproxy/description\n  Kernel modules for Transparent Proxying\nendef\n\n$(eval $(call KernelPackage,ipt-tproxy))\n\ndefine KernelPackage/ipt-tee\n  TITLE:=TEE support\n  DEPENDS:=+kmod-ipt-conntrack\n  KCONFIG:=$(KCONFIG_IPT_TEE)\n  FILES:=$(foreach mod,$(IPT_TEE-m),$(LINUX_DIR)/net/$(mod).ko)\n  AUTOLOAD:=$(call AutoProbe,$(notdir nf_tee $(IPT_TEE-m)))\n  $(call AddDepends/ipt)\nendef\n\ndefine KernelPackage/ipt-tee/description\n  Kernel modules for TEE\nendef\n\n$(eval $(call KernelPackage,ipt-tee))\n\n\ndefine KernelPackage/ipt-u32\n  TITLE:=U32 support\n  KCONFIG:=$(KCONFIG_IPT_U32)\n  FILES:=$(foreach mod,$(IPT_U32-m),$(LINUX_DIR)/net/$(mod).ko)\n  AUTOLOAD:=$(call AutoProbe,$(notdir nf_tee $(IPT_U32-m)))\n  $(call AddDepends/ipt)\nendef\n\ndefine KernelPackage/ipt-u32/description\n  Kernel modules for U32\nendef\n\n$(eval $(call KernelPackage,ipt-u32))\n\ndefine KernelPackage/ipt-checksum\n  TITLE:=CHECKSUM support\n  KCONFIG:=$(KCONFIG_IPT_CHECKSUM)\n  FILES:=$(foreach mod,$(IPT_CHECKSUM-m),$(LINUX_DIR)/net/$(mod).ko)\n  AUTOLOAD:=$(call AutoProbe,$(notdir $(IPT_CHECKSUM-m)))\n  $(call AddDepends/ipt)\nendef\n\ndefine KernelPackage/ipt-checksum/description\n  Kernel modules for CHECKSUM fillin target\nendef\n\n$(eval $(call KernelPackage,ipt-checksum))\n\n\ndefine KernelPackage/ipt-iprange\n  TITLE:=Module for matching ip ranges\n  KCONFIG:=$(KCONFIG_IPT_IPRANGE)\n  FILES:=$(foreach mod,$(IPT_IPRANGE-m),$(LINUX_DIR)/net/$(mod).ko)\n  AUTOLOAD:=$(call AutoProbe,$(notdir $(IPT_IPRANGE-m)))\n  $(call AddDepends/ipt)\nendef\n\ndefine KernelPackage/ipt-iprange/description\n Netfilter (IPv4) module for matching ip ranges\n Includes:\n - iprange\nendef\n\n$(eval $(call KernelPackage,ipt-iprange))\n\ndefine KernelPackage/ipt-cluster\n  TITLE:=Module for matching cluster\n  KCONFIG:=$(KCONFIG_IPT_CLUSTER)\n  FILES:=$(foreach mod,$(IPT_CLUSTER-m),$(LINUX_DIR)/net/$(mod).ko)\n  AUTOLOAD:=$(call AutoProbe,$(notdir $(IPT_CLUSTER-m)))\n  $(call AddDepends/ipt,+kmod-nf-conntrack)\nendef\n\ndefine KernelPackage/ipt-cluster/description\n Netfilter (IPv4/IPv6) module for matching cluster\n This option allows you to build work-load-sharing clusters of\n network servers/stateful firewalls without having a dedicated\n load-balancing router/server/switch. Basically, this match returns\n true when the packet must be handled by this cluster node. Thus,\n all nodes see all packets and this match decides which node handles\n what packets. The work-load sharing algorithm is based on source\n address hashing.\n\n This module is usable for ipv4 and ipv6.\n\n To use it also enable iptables-mod-cluster\n\n see `iptables -m cluster --help` for more information.\nendef\n\n$(eval $(call KernelPackage,ipt-cluster))\n\ndefine KernelPackage/ipt-clusterip\n  TITLE:=Module for CLUSTERIP\n  KCONFIG:=$(KCONFIG_IPT_CLUSTERIP)\n  FILES:=$(foreach mod,$(IPT_CLUSTERIP-m),$(LINUX_DIR)/net/$(mod).ko)\n  AUTOLOAD:=$(call AutoProbe,$(notdir $(IPT_CLUSTERIP-m)))\n  $(call AddDepends/ipt,+kmod-nf-conntrack)\nendef\n\ndefine KernelPackage/ipt-clusterip/description\n Netfilter (IPv4-only) module for CLUSTERIP\n The CLUSTERIP target allows you to build load-balancing clusters of\n network servers without having a dedicated load-balancing\n router/server/switch.\n\n To use it also enable iptables-mod-clusterip\n\n see `iptables -j CLUSTERIP --help` for more information.\nendef\n\n$(eval $(call KernelPackage,ipt-clusterip))\n\n\ndefine KernelPackage/ipt-extra\n  TITLE:=Extra modules\n  KCONFIG:=$(KCONFIG_IPT_EXTRA)\n  FILES:=$(foreach mod,$(IPT_EXTRA-m),$(LINUX_DIR)/net/$(mod).ko)\n  AUTOLOAD:=$(call AutoProbe,$(notdir $(IPT_EXTRA-m)))\n  $(call AddDepends/ipt)\nendef\n\ndefine KernelPackage/ipt-extra/description\n Other Netfilter (IPv4) kernel modules\n Includes:\n - addrtype\n - owner\n - pkttype\n - quota\nendef\n\n$(eval $(call KernelPackage,ipt-extra))\n\n\ndefine KernelPackage/ipt-physdev\n  TITLE:=physdev module\n  KCONFIG:=$(KCONFIG_IPT_PHYSDEV)\n  FILES:=$(foreach mod,$(IPT_PHYSDEV-m),$(LINUX_DIR)/net/$(mod).ko)\n  AUTOLOAD:=$(call AutoProbe,$(notdir $(IPT_PHYSDEV-m)))\n  $(call AddDepends/ipt,+kmod-br-netfilter)\nendef\n\ndefine KernelPackage/ipt-physdev/description\n The iptables physdev kernel module\nendef\n\n$(eval $(call KernelPackage,ipt-physdev))\n\n\ndefine KernelPackage/ip6tables\n  SUBMENU:=$(NF_MENU)\n  TITLE:=IPv6 modules\n  DEPENDS:=@IPV6 +kmod-nf-reject6 +kmod-nf-ipt6 +kmod-ipt-core\n  KCONFIG:=$(KCONFIG_IPT_IPV6)\n  FILES:=$(foreach mod,$(IPT_IPV6-m),$(LINUX_DIR)/net/$(mod).ko)\n  AUTOLOAD:=$(call AutoLoad,42,$(notdir $(IPT_IPV6-m)))\nendef\n\ndefine KernelPackage/ip6tables/description\n Netfilter IPv6 firewalling support\nendef\n\n$(eval $(call KernelPackage,ip6tables))\n\ndefine KernelPackage/ip6tables-extra\n  SUBMENU:=$(NF_MENU)\n  TITLE:=Extra IPv6 modules\n  DEPENDS:=@IPV6 +kmod-ip6tables\n  KCONFIG:=$(KCONFIG_IPT_IPV6_EXTRA)\n  FILES:=$(foreach mod,$(IPT_IPV6_EXTRA-m),$(LINUX_DIR)/net/$(mod).ko)\n  AUTOLOAD:=$(call AutoLoad,43,$(notdir $(IPT_IPV6_EXTRA-m)))\nendef\n\ndefine KernelPackage/ip6tables-extra/description\n Netfilter IPv6 extra header matching modules\nendef\n\n$(eval $(call KernelPackage,ip6tables-extra))\n\nARP_MODULES = arp_tables arpt_mangle arptable_filter\ndefine KernelPackage/arptables\n  SUBMENU:=$(NF_MENU)\n  TITLE:=ARP firewalling modules\n  DEPENDS:=+kmod-ipt-core\n  FILES:=$(LINUX_DIR)/net/ipv4/netfilter/arp*.ko\n  KCONFIG:=CONFIG_IP_NF_ARPTABLES \\\n    CONFIG_IP_NF_ARPFILTER \\\n    CONFIG_IP_NF_ARP_MANGLE\n  AUTOLOAD:=$(call AutoProbe,$(ARP_MODULES))\nendef\n\ndefine KernelPackage/arptables/description\n Kernel modules for ARP firewalling\nendef\n\n$(eval $(call KernelPackage,arptables))\n\n\ndefine KernelPackage/br-netfilter\n  SUBMENU:=$(NF_MENU)\n  TITLE:=Bridge netfilter support modules\n  DEPENDS:=+kmod-ipt-core\n  FILES:=$(LINUX_DIR)/net/bridge/br_netfilter.ko\n  KCONFIG:=CONFIG_BRIDGE_NETFILTER\n  AUTOLOAD:=$(call AutoProbe,br_netfilter)\nendef\n\ndefine KernelPackage/br-netfilter/install\n\t$(INSTALL_DIR) $(1)/etc/sysctl.d\n\t$(INSTALL_DATA) ./files/sysctl-br-netfilter.conf $(1)/etc/sysctl.d/11-br-netfilter.conf\nendef\n\n$(eval $(call KernelPackage,br-netfilter))\n\n\ndefine KernelPackage/ebtables\n  SUBMENU:=$(NF_MENU)\n  TITLE:=Bridge firewalling modules\n  DEPENDS:=+kmod-ipt-core\n  FILES:=$(foreach mod,$(EBTABLES-m),$(LINUX_DIR)/net/$(mod).ko)\n  KCONFIG:=$(KCONFIG_EBTABLES)\n  AUTOLOAD:=$(call AutoProbe,$(notdir $(EBTABLES-m)))\nendef\n\ndefine KernelPackage/ebtables/description\n  ebtables is a general, extensible frame/packet identification\n  framework. It provides you to do Ethernet\n  filtering/NAT/brouting on the Ethernet bridge.\nendef\n\n$(eval $(call KernelPackage,ebtables))\n\n\ndefine AddDepends/ebtables\n  SUBMENU:=$(NF_MENU)\n  DEPENDS+= +kmod-ebtables $(1)\nendef\n\n\ndefine KernelPackage/ebtables-ipv4\n  TITLE:=ebtables: IPv4 support\n  FILES:=$(foreach mod,$(EBTABLES_IP4-m),$(LINUX_DIR)/net/$(mod).ko)\n  KCONFIG:=$(KCONFIG_EBTABLES_IP4)\n  AUTOLOAD:=$(call AutoProbe,$(notdir $(EBTABLES_IP4-m)))\n  $(call AddDepends/ebtables)\nendef\n\ndefine KernelPackage/ebtables-ipv4/description\n This option adds the IPv4 support to ebtables, which allows basic\n IPv4 header field filtering, ARP filtering as well as SNAT, DNAT targets.\nendef\n\n$(eval $(call KernelPackage,ebtables-ipv4))\n\n\ndefine KernelPackage/ebtables-ipv6\n  TITLE:=ebtables: IPv6 support\n  DEPENDS:=@IPV6\n  FILES:=$(foreach mod,$(EBTABLES_IP6-m),$(LINUX_DIR)/net/$(mod).ko)\n  KCONFIG:=$(KCONFIG_EBTABLES_IP6)\n  AUTOLOAD:=$(call AutoProbe,$(notdir $(EBTABLES_IP6-m)))\n  $(call AddDepends/ebtables)\nendef\n\ndefine KernelPackage/ebtables-ipv6/description\n This option adds the IPv6 support to ebtables, which allows basic\n IPv6 header field filtering and target support.\nendef\n\n$(eval $(call KernelPackage,ebtables-ipv6))\n\n\ndefine KernelPackage/ebtables-watchers\n  TITLE:=ebtables: watchers support\n  FILES:=$(foreach mod,$(EBTABLES_WATCHERS-m),$(LINUX_DIR)/net/$(mod).ko)\n  KCONFIG:=$(KCONFIG_EBTABLES_WATCHERS)\n  AUTOLOAD:=$(call AutoProbe,$(notdir $(EBTABLES_WATCHERS-m)))\n  $(call AddDepends/ebtables)\nendef\n\ndefine KernelPackage/ebtables-watchers/description\n This option adds the log watchers, that you can use in any rule\n in any ebtables table.\nendef\n\n$(eval $(call KernelPackage,ebtables-watchers))\n\n\ndefine KernelPackage/nfnetlink\n  SUBMENU:=$(NF_MENU)\n  TITLE:=Netlink-based userspace interface\n  FILES:=$(foreach mod,$(NFNETLINK-m),$(LINUX_DIR)/net/$(mod).ko)\n  KCONFIG:=$(KCONFIG_NFNETLINK)\n  AUTOLOAD:=$(call AutoProbe,$(notdir $(NFNETLINK-m)))\nendef\n\ndefine KernelPackage/nfnetlink/description\n Kernel modules support for a netlink-based userspace interface\nendef\n\n$(eval $(call KernelPackage,nfnetlink))\n\n\ndefine AddDepends/nfnetlink\n  SUBMENU:=$(NF_MENU)\n  DEPENDS+=+kmod-nfnetlink $(1)\nendef\n\n\ndefine KernelPackage/nfnetlink-log\n  TITLE:=Netfilter LOG over NFNETLINK interface\n  FILES:=$(foreach mod,$(NFNETLINK_LOG-m),$(LINUX_DIR)/net/$(mod).ko)\n  KCONFIG:=$(KCONFIG_NFNETLINK_LOG)\n  AUTOLOAD:=$(call AutoProbe,$(notdir $(NFNETLINK_LOG-m)))\n  $(call AddDepends/nfnetlink)\nendef\n\ndefine KernelPackage/nfnetlink-log/description\n Kernel modules support for logging packets via NFNETLINK\n Includes:\n - NFLOG\nendef\n\n$(eval $(call KernelPackage,nfnetlink-log))\n\n\ndefine KernelPackage/nfnetlink-queue\n  TITLE:=Netfilter QUEUE over NFNETLINK interface\n  FILES:=$(foreach mod,$(NFNETLINK_QUEUE-m),$(LINUX_DIR)/net/$(mod).ko)\n  KCONFIG:=$(KCONFIG_NFNETLINK_QUEUE)\n  AUTOLOAD:=$(call AutoProbe,$(notdir $(NFNETLINK_QUEUE-m)))\n  $(call AddDepends/nfnetlink)\nendef\n\ndefine KernelPackage/nfnetlink-queue/description\n Kernel modules support for queueing packets via NFNETLINK\n Includes:\n - NFQUEUE\nendef\n\n$(eval $(call KernelPackage,nfnetlink-queue))\n\n\ndefine KernelPackage/nf-conntrack-netlink\n  TITLE:=Connection tracking netlink interface\n  FILES:=$(LINUX_DIR)/net/netfilter/nf_conntrack_netlink.ko\n  KCONFIG:=CONFIG_NF_CT_NETLINK CONFIG_NF_CONNTRACK_EVENTS=y CONFIG_NETFILTER_NETLINK_GLUE_CT=y\n  AUTOLOAD:=$(call AutoProbe,nf_conntrack_netlink)\n  $(call AddDepends/nfnetlink,+kmod-nf-conntrack)\nendef\n\ndefine KernelPackage/nf-conntrack-netlink/description\n Kernel modules support for a netlink-based connection tracking\n userspace interface\nendef\n\n$(eval $(call KernelPackage,nf-conntrack-netlink))\n\ndefine KernelPackage/ipt-hashlimit\n  SUBMENU:=$(NF_MENU)\n  TITLE:=Netfilter hashlimit match\n  DEPENDS:=+kmod-ipt-core\n  KCONFIG:=$(KCONFIG_IPT_HASHLIMIT)\n  FILES:=$(LINUX_DIR)/net/netfilter/xt_hashlimit.ko\n  AUTOLOAD:=$(call AutoProbe,xt_hashlimit)\n  $(call KernelPackage/ipt)\nendef\n\ndefine KernelPackage/ipt-hashlimit/description\n Kernel modules support for the hashlimit bucket match module\nendef\n\n$(eval $(call KernelPackage,ipt-hashlimit))\n\ndefine KernelPackage/ipt-rpfilter\n  SUBMENU:=$(NF_MENU)\n  TITLE:=Netfilter rpfilter match\n  DEPENDS:=+kmod-ipt-core\n  KCONFIG:=$(KCONFIG_IPT_RPFILTER)\n  FILES:=$(realpath \\\n\t$(LINUX_DIR)/net/ipv4/netfilter/ipt_rpfilter.ko \\\n\t$(LINUX_DIR)/net/ipv6/netfilter/ip6t_rpfilter.ko)\n  AUTOLOAD:=$(call AutoProbe,ipt_rpfilter ip6t_rpfilter)\n  $(call KernelPackage/ipt)\nendef\n\ndefine KernelPackage/ipt-rpfilter/description\n Kernel modules support for the Netfilter rpfilter match\nendef\n\n$(eval $(call KernelPackage,ipt-rpfilter))\n\n\ndefine KernelPackage/nft-core\n  SUBMENU:=$(NF_MENU)\n  TITLE:=Netfilter nf_tables support\n  DEPENDS:=+kmod-nfnetlink +kmod-nf-reject +IPV6:kmod-nf-reject6 +IPV6:kmod-nf-conntrack6 +kmod-nf-nat +kmod-nf-log +IPV6:kmod-nf-log6 +kmod-lib-crc32c\n  FILES:=$(foreach mod,$(NFT_CORE-m),$(LINUX_DIR)/net/$(mod).ko)\n  AUTOLOAD:=$(call AutoProbe,$(notdir $(NFT_CORE-m)))\n  KCONFIG:= \\\n\tCONFIG_NFT_COMPAT=n \\\n\tCONFIG_NFT_QUEUE=n \\\n\t$(KCONFIG_NFT_CORE)\nendef\n\ndefine KernelPackage/nft-core/description\n Kernel module support for nftables\nendef\n\n$(eval $(call KernelPackage,nft-core))\n\n\ndefine KernelPackage/nft-arp\n  SUBMENU:=$(NF_MENU)\n  TITLE:=Netfilter nf_tables ARP table support\n  DEPENDS:=+kmod-nft-core\n  FILES:=$(foreach mod,$(NFT_ARP-m),$(LINUX_DIR)/net/$(mod).ko)\n  AUTOLOAD:=$(call AutoProbe,$(notdir $(NFT_ARP-m)))\n  KCONFIG:=$(KCONFIG_NFT_ARP)\nendef\n\n$(eval $(call KernelPackage,nft-arp))\n\n\ndefine KernelPackage/nft-bridge\n  SUBMENU:=$(NF_MENU)\n  TITLE:=Netfilter nf_tables bridge table support\n  DEPENDS:=+kmod-nft-core\n  FILES:=$(foreach mod,$(NFT_BRIDGE-m),$(LINUX_DIR)/net/$(mod).ko)\n  AUTOLOAD:=$(call AutoProbe,$(notdir $(NFT_BRIDGE-m)))\n  KCONFIG:= \\\n\tCONFIG_NF_LOG_BRIDGE=n@lt5.13 \\\n\t$(KCONFIG_NFT_BRIDGE)\nendef\n\n$(eval $(call KernelPackage,nft-bridge))\n\n\ndefine KernelPackage/nft-nat\n  SUBMENU:=$(NF_MENU)\n  TITLE:=Netfilter nf_tables NAT support\n  DEPENDS:=+kmod-nft-core +kmod-nf-nat\n  FILES:=$(foreach mod,$(NFT_NAT-m),$(LINUX_DIR)/net/$(mod).ko)\n  AUTOLOAD:=$(call AutoProbe,$(notdir $(NFT_NAT-m)))\n  KCONFIG:=$(KCONFIG_NFT_NAT)\nendef\n\n$(eval $(call KernelPackage,nft-nat))\n\n\ndefine KernelPackage/nft-offload\n  SUBMENU:=$(NF_MENU)\n  TITLE:=Netfilter nf_tables routing/NAT offload support\n  DEPENDS:=@IPV6 +kmod-nf-flow +kmod-nft-nat\n  KCONFIG:= \\\n\tCONFIG_NF_FLOW_TABLE_INET \\\n\tCONFIG_NF_FLOW_TABLE_IPV4 \\\n\tCONFIG_NF_FLOW_TABLE_IPV6 \\\n\tCONFIG_NFT_FLOW_OFFLOAD\n  FILES:= \\\n\t$(LINUX_DIR)/net/netfilter/nf_flow_table_inet.ko \\\n\t$(LINUX_DIR)/net/ipv4/netfilter/nf_flow_table_ipv4.ko \\\n\t$(LINUX_DIR)/net/ipv6/netfilter/nf_flow_table_ipv6.ko \\\n\t$(LINUX_DIR)/net/netfilter/nft_flow_offload.ko\n  AUTOLOAD:=$(call AutoProbe,nf_flow_table_inet nf_flow_table_ipv4 nf_flow_table_ipv6 nft_flow_offload)\nendef\n\n$(eval $(call KernelPackage,nft-offload))\n\n\ndefine KernelPackage/nft-nat6\n  SUBMENU:=$(NF_MENU)\n  TITLE:=Netfilter nf_tables IPv6-NAT support\n  DEPENDS:=+kmod-nft-nat +kmod-nf-nat6\n  FILES:=$(foreach mod,$(NFT_NAT6-m),$(LINUX_DIR)/net/$(mod).ko)\n  AUTOLOAD:=$(call AutoProbe,$(notdir $(NFT_NAT6-m)))\n  KCONFIG:=$(KCONFIG_NFT_NAT6)\nendef\n\n$(eval $(call KernelPackage,nft-nat6))\n\ndefine KernelPackage/nft-netdev\n  SUBMENU:=$(NF_MENU)\n  TITLE:=Netfilter nf_tables netdev support\n  DEPENDS:=+kmod-nft-core\n  KCONFIG:= \\\n\tCONFIG_NETFILTER_INGRESS=y \\\n\tCONFIG_NF_TABLES_NETDEV \\\n\tCONFIG_NF_DUP_NETDEV \\\n\tCONFIG_NFT_DUP_NETDEV \\\n\tCONFIG_NFT_FWD_NETDEV\n  FILES:= \\\n\t$(LINUX_DIR)/net/netfilter/nf_dup_netdev.ko \\\n\t$(LINUX_DIR)/net/netfilter/nft_dup_netdev.ko \\\n\t$(LINUX_DIR)/net/netfilter/nft_fwd_netdev.ko\n  AUTOLOAD:=$(call AutoProbe,nf_tables_netdev nf_dup_netdev nft_dup_netdev nft_fwd_netdev)\nendef\n\n$(eval $(call KernelPackage,nft-netdev))\n\n\ndefine KernelPackage/nft-fib\n  SUBMENU:=$(NF_MENU)\n  TITLE:=Netfilter nf_tables fib support\n  DEPENDS:=+kmod-nft-core\n  FILES:=$(foreach mod,$(NFT_FIB-m),$(LINUX_DIR)/net/$(mod).ko)\n  AUTOLOAD:=$(call AutoProbe,$(notdir $(NFT_FIB-m)))\n  KCONFIG:=$(KCONFIG_NFT_FIB)\nendef\n\n$(eval $(call KernelPackage,nft-fib))\n\n\ndefine KernelPackage/nft-queue\n  SUBMENU:=$(NF_MENU)\n  TITLE:=Netfilter nf_tables queue support\n  DEPENDS:=+kmod-nft-core +kmod-nfnetlink-queue\n  FILES:=$(foreach mod,$(NFT_QUEUE-m),$(LINUX_DIR)/net/$(mod).ko)\n  AUTOLOAD:=$(call AutoProbe,$(notdir $(NFT_QUEUE-m)))\n  KCONFIG:=$(KCONFIG_NFT_QUEUE)\nendef\n\n$(eval $(call KernelPackage,nft-queue))\n\ndefine KernelPackage/nft-socket\n  SUBMENU:=$(NF_MENU)\n  TITLE:=Netfilter nf_tables socket support\n  DEPENDS:=+kmod-nft-core +kmod-nf-socket\n  FILES:=$(foreach mod,$(NFT_SOCKET-m),$(LINUX_DIR)/net/$(mod).ko)\n  AUTOLOAD:=$(call AutoProbe,$(notdir $(NFT_SOCKET-m)))\n  KCONFIG:=$(KCONFIG_NFT_SOCKET)\nendef\n\n$(eval $(call KernelPackage,nft-socket))\n\ndefine KernelPackage/nft-tproxy\n  SUBMENU:=$(NF_MENU)\n  TITLE:=Netfilter nf_tables tproxy support\n  DEPENDS:=+kmod-nft-core +kmod-nf-tproxy +kmod-nf-conntrack\n  FILES:=$(foreach mod,$(NFT_TPROXY-m),$(LINUX_DIR)/net/$(mod).ko)\n  AUTOLOAD:=$(call AutoProbe,$(notdir $(NFT_TPROXY-m)))\n  KCONFIG:=$(KCONFIG_NFT_TPROXY)\nendef\n\n$(eval $(call KernelPackage,nft-tproxy))\n\ndefine KernelPackage/nft-compat\n  SUBMENU:=$(NF_MENU)\n  TITLE:=Netfilter nf_tables compat support\n  DEPENDS:=+kmod-nft-core +kmod-nf-ipt\n  FILES:=$(foreach mod,$(NFT_COMPAT-m),$(LINUX_DIR)/net/$(mod).ko)\n  AUTOLOAD:=$(call AutoProbe,$(notdir $(NFT_COMPAT-m)))\n  KCONFIG:=$(KCONFIG_NFT_COMPAT)\nendef\n\n$(eval $(call KernelPackage,nft-compat))\n"
  },
  {
    "path": "package/kernel/linux/modules/netsupport.mk",
    "content": "#\n# Copyright (C) 2006-2011 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\nNETWORK_SUPPORT_MENU:=Network Support\n\ndefine KernelPackage/atm\n  SUBMENU:=$(NETWORK_SUPPORT_MENU)\n  TITLE:=ATM support\n  KCONFIG:= \\\n\tCONFIG_ATM \\\n\tCONFIG_ATM_BR2684\n  FILES:= \\\n\t$(LINUX_DIR)/net/atm/atm.ko \\\n\t$(LINUX_DIR)/net/atm/br2684.ko\n  AUTOLOAD:=$(call AutoLoad,30,atm br2684)\nendef\n\ndefine KernelPackage/atm/description\n Kernel modules for ATM support\nendef\n\n$(eval $(call KernelPackage,atm))\n\n\ndefine KernelPackage/atmtcp\n  SUBMENU:=$(NETWORK_SUPPORT_MENU)\n  TITLE:=ATM over TCP\n  DEPENDS:=kmod-atm\n  KCONFIG:=CONFIG_ATM_TCP CONFIG_ATM_DRIVERS=y\n  FILES:=$(LINUX_DIR)/drivers/atm/atmtcp.ko\n  AUTOLOAD:=$(call AutoLoad,40,atmtcp)\nendef\n\ndefine KernelPackage/atmtcp/description\n Kernel module for ATM over TCP support\nendef\n\n$(eval $(call KernelPackage,atmtcp))\n\n\ndefine KernelPackage/bonding\n  SUBMENU:=$(NETWORK_SUPPORT_MENU)\n  TITLE:=Ethernet bonding driver\n  KCONFIG:=CONFIG_BONDING\n  FILES:=$(LINUX_DIR)/drivers/net/bonding/bonding.ko\n  AUTOLOAD:=$(call AutoLoad,40,bonding)\n  MODPARAMS.bonding:=max_bonds=0\nendef\n\ndefine KernelPackage/bonding/description\n Kernel module for NIC bonding.\nendef\n\n$(eval $(call KernelPackage,bonding))\n\n\ndefine KernelPackage/udptunnel4\n  SUBMENU:=$(NETWORK_SUPPORT_MENU)\n  TITLE:=IPv4 UDP tunneling support\n  KCONFIG:=CONFIG_NET_UDP_TUNNEL\n  HIDDEN:=1\n  FILES:=$(LINUX_DIR)/net/ipv4/udp_tunnel.ko\n  AUTOLOAD:=$(call AutoLoad,32,udp_tunnel)\nendef\n\n\n$(eval $(call KernelPackage,udptunnel4))\n\ndefine KernelPackage/udptunnel6\n  SUBMENU:=$(NETWORK_SUPPORT_MENU)\n  TITLE:=IPv6 UDP tunneling support\n  DEPENDS:=@IPV6\n  KCONFIG:=CONFIG_NET_UDP_TUNNEL\n  HIDDEN:=1\n  FILES:=$(LINUX_DIR)/net/ipv6/ip6_udp_tunnel.ko\n  AUTOLOAD:=$(call AutoLoad,32,ip6_udp_tunnel)\nendef\n\n$(eval $(call KernelPackage,udptunnel6))\n\n\ndefine KernelPackage/vxlan\n  SUBMENU:=$(NETWORK_SUPPORT_MENU)\n  TITLE:=Native VXLAN Kernel support\n  DEPENDS:= \\\n\t+kmod-iptunnel \\\n\t+kmod-udptunnel4 \\\n\t+IPV6:kmod-udptunnel6\n  KCONFIG:=CONFIG_VXLAN\n  FILES:=$(LINUX_DIR)/drivers/net/vxlan.ko\n  AUTOLOAD:=$(call AutoLoad,13,vxlan)\nendef\n\ndefine KernelPackage/vxlan/description\n Kernel module for supporting VXLAN in the Kernel.\n Requires Kernel 3.12 or newer.\nendef\n\n$(eval $(call KernelPackage,vxlan))\n\n\ndefine KernelPackage/geneve\n  SUBMENU:=$(NETWORK_SUPPORT_MENU)\n  TITLE:=Generic Network Virtualization Encapsulation (Geneve) support\n  DEPENDS:= \\\n\t+kmod-iptunnel \\\n\t+kmod-udptunnel4 \\\n\t+IPV6:kmod-udptunnel6\n  KCONFIG:=CONFIG_GENEVE\n  FILES:= \\\n\t$(LINUX_DIR)/drivers/net/geneve.ko\n  AUTOLOAD:=$(call AutoLoad,13,geneve)\nendef\n\ndefine KernelPackage/geneve/description\n Kernel module for supporting Geneve in the Kernel.\n Requires Kernel 3.18 or newer.\nendef\n\n$(eval $(call KernelPackage,geneve))\n\n\ndefine KernelPackage/nsh\n  SUBMENU:=$(NETWORK_SUPPORT_MENU)\n  TITLE:=Network Service Header (NSH) protocol\n  DEPENDS:=\n  KCONFIG:=CONFIG_NET_NSH\n  FILES:=$(LINUX_DIR)/net/nsh/nsh.ko\n  AUTOLOAD:=$(call AutoLoad,13,nsh)\nendef\n\ndefine KernelPackage/nsh/description\n  Network Service Header is an implementation of Service Function\n  Chaining (RFC 7665).  Requires kernel 4.14 or newer\nendef\n\n$(eval $(call KernelPackage,nsh))\n\n\ndefine KernelPackage/misdn\n  SUBMENU:=$(NETWORK_SUPPORT_MENU)\n  TITLE:=mISDN (ISDN) Support\n  KCONFIG:= \\\n\tCONFIG_ISDN=y \\\n  \tCONFIG_MISDN \\\n\tCONFIG_MISDN_DSP \\\n\tCONFIG_MISDN_L1OIP\n  FILES:= \\\n  \t$(LINUX_DIR)/drivers/isdn/mISDN/mISDN_core.ko \\\n\t$(LINUX_DIR)/drivers/isdn/mISDN/mISDN_dsp.ko \\\n\t$(LINUX_DIR)/drivers/isdn/mISDN/l1oip.ko\n  AUTOLOAD:=$(call AutoLoad,30,mISDN_core mISDN_dsp l1oip)\nendef\n\ndefine KernelPackage/misdn/description\n  Modular ISDN driver support\nendef\n\n$(eval $(call KernelPackage,misdn))\n\n\ndefine KernelPackage/isdn4linux\n  SUBMENU:=$(NETWORK_SUPPORT_MENU)\n  TITLE:=Old ISDN4Linux (deprecated)\n  DEPENDS:=+kmod-ppp\n  KCONFIG:= \\\n\tCONFIG_ISDN=y \\\n    CONFIG_ISDN_I4L \\\n    CONFIG_ISDN_PPP=y \\\n    CONFIG_ISDN_PPP_VJ=y \\\n    CONFIG_ISDN_MPP=y \\\n    CONFIG_IPPP_FILTER=y \\\n    CONFIG_ISDN_PPP_BSDCOMP \\\n    CONFIG_ISDN_CAPI_MIDDLEWARE=y \\\n    CONFIG_ISDN_CAPI_CAPIFS_BOOL=y \\\n    CONFIG_ISDN_AUDIO=y \\\n    CONFIG_ISDN_TTY_FAX=y \\\n    CONFIG_ISDN_X25=y \\\n    CONFIG_ISDN_DIVERSION\n  FILES:= \\\n    $(LINUX_DIR)/drivers/isdn/divert/dss1_divert.ko \\\n\t$(LINUX_DIR)/drivers/isdn/i4l/isdn.ko \\\n\t$(LINUX_DIR)/drivers/isdn/i4l/isdn_bsdcomp.ko\n  AUTOLOAD:=$(call AutoLoad,40,isdn isdn_bsdcomp dss1_divert)\nendef\n\ndefine KernelPackage/isdn4linux/description\n  This driver allows you to use an ISDN adapter for networking\nendef\n\n$(eval $(call KernelPackage,isdn4linux))\n\n\ndefine KernelPackage/ipip\n  SUBMENU:=$(NETWORK_SUPPORT_MENU)\n  TITLE:=IP-in-IP encapsulation\n  DEPENDS:=+kmod-iptunnel +kmod-iptunnel4\n  KCONFIG:=CONFIG_NET_IPIP\n  FILES:=$(LINUX_DIR)/net/ipv4/ipip.ko\n  AUTOLOAD:=$(call AutoLoad,32,ipip)\nendef\n\ndefine KernelPackage/ipip/description\n Kernel modules for IP-in-IP encapsulation\nendef\n\n$(eval $(call KernelPackage,ipip))\n\n\nIPSEC-m:= \\\n\txfrm/xfrm_algo \\\n\txfrm/xfrm_ipcomp \\\n\txfrm/xfrm_user \\\n\tkey/af_key \\\n\ndefine KernelPackage/ipsec\n  SUBMENU:=$(NETWORK_SUPPORT_MENU)\n  TITLE:=IPsec related modules (IPv4 and IPv6)\n  DEPENDS:= \\\n\t+kmod-crypto-authenc +kmod-crypto-cbc +kmod-crypto-deflate \\\n\t+kmod-crypto-des +kmod-crypto-echainiv +kmod-crypto-hmac \\\n\t+kmod-crypto-md5 +kmod-crypto-sha1\n  KCONFIG:= \\\n\tCONFIG_NET_KEY \\\n\tCONFIG_XFRM_USER \\\n\tCONFIG_INET_IPCOMP \\\n\tCONFIG_XFRM_IPCOMP\n  FILES:=$(foreach mod,$(IPSEC-m),$(LINUX_DIR)/net/$(mod).ko)\n  AUTOLOAD:=$(call AutoLoad,30,$(notdir $(IPSEC-m)))\nendef\n\ndefine KernelPackage/ipsec/description\n Kernel modules for IPsec support in both IPv4 and IPv6.\n Includes:\n - af_key\n - xfrm_algo\n - xfrm_ipcomp\n - xfrm_user\nendef\n\n$(eval $(call KernelPackage,ipsec))\n\nIPSEC4-m = \\\n\tipv4/ah4 \\\n\tipv4/esp4 \\\n\tipv4/xfrm4_tunnel \\\n\tipv4/ipcomp \\\n\nIPSEC4-m += $(ifeq ($$(strip $$(call CompareKernelPatchVer,$$(KERNEL_PATCHVER),le,5.2))),ipv4/xfrm4_mode_beet ipv4/xfrm4_mode_transport ipv4/xfrm4_mode_tunnel)\n\ndefine KernelPackage/ipsec4\n  SUBMENU:=$(NETWORK_SUPPORT_MENU)\n  TITLE:=IPsec related modules (IPv4)\n  DEPENDS:=kmod-ipsec +kmod-iptunnel4\n  KCONFIG:= \\\n\tCONFIG_INET_AH \\\n\tCONFIG_INET_ESP \\\n\tCONFIG_INET_IPCOMP \\\n\tCONFIG_INET_XFRM_MODE_BEET \\\n\tCONFIG_INET_XFRM_MODE_TRANSPORT \\\n\tCONFIG_INET_XFRM_MODE_TUNNEL \\\n\tCONFIG_INET_XFRM_TUNNEL \\\n\tCONFIG_INET_ESP_OFFLOAD=n\n  FILES:=$(foreach mod,$(IPSEC4-m),$(LINUX_DIR)/net/$(mod).ko)\n  AUTOLOAD:=$(call AutoLoad,32,$(notdir $(IPSEC4-m)))\nendef\n\ndefine KernelPackage/ipsec4/description\n Kernel modules for IPsec support in IPv4.\n Includes:\n - ah4\n - esp4\n - ipcomp4\n - xfrm4_mode_beet\n - xfrm4_mode_transport\n - xfrm4_mode_tunnel\n - xfrm4_tunnel\nendef\n\n$(eval $(call KernelPackage,ipsec4))\n\n\nIPSEC6-m = \\\n\tipv6/ah6 \\\n\tipv6/esp6 \\\n\tipv6/xfrm6_tunnel \\\n\tipv6/ipcomp6 \\\n\nIPSEC6-m += $(ifeq ($$(strip $$(call CompareKernelPatchVer,$$(KERNEL_PATCHVER),le,5.2))),ipv6/xfrm6_mode_beet ipv6/xfrm6_mode_transport ipv6/xfrm6_mode_tunnel)\n\ndefine KernelPackage/ipsec6\n  SUBMENU:=$(NETWORK_SUPPORT_MENU)\n  TITLE:=IPsec related modules (IPv6)\n  DEPENDS:=@IPV6 kmod-ipsec +kmod-iptunnel6\n  KCONFIG:= \\\n\tCONFIG_INET6_AH \\\n\tCONFIG_INET6_ESP \\\n\tCONFIG_INET6_IPCOMP \\\n\tCONFIG_INET6_XFRM_MODE_BEET \\\n\tCONFIG_INET6_XFRM_MODE_TRANSPORT \\\n\tCONFIG_INET6_XFRM_MODE_TUNNEL \\\n\tCONFIG_INET6_XFRM_TUNNEL \\\n\tCONFIG_INET6_ESP_OFFLOAD=n\n  FILES:=$(foreach mod,$(IPSEC6-m),$(LINUX_DIR)/net/$(mod).ko)\n  AUTOLOAD:=$(call AutoLoad,32,$(notdir $(IPSEC6-m)))\nendef\n\ndefine KernelPackage/ipsec6/description\n Kernel modules for IPsec support in IPv6.\n Includes:\n - ah6\n - esp6\n - ipcomp6\n - xfrm6_mode_beet\n - xfrm6_mode_transport\n - xfrm6_mode_tunnel\n - xfrm6_tunnel\nendef\n\n$(eval $(call KernelPackage,ipsec6))\n\n\ndefine KernelPackage/iptunnel\n  SUBMENU:=$(NETWORK_SUPPORT_MENU)\n  TITLE:=IP tunnel support\n  HIDDEN:=1\n  KCONFIG:= \\\n\tCONFIG_NET_IP_TUNNEL\n  FILES:=$(LINUX_DIR)/net/ipv4/ip_tunnel.ko\n  AUTOLOAD:=$(call AutoLoad,31,ip_tunnel)\nendef\n\ndefine KernelPackage/iptunnel/description\n Kernel module for generic IP tunnel support\nendef\n\n$(eval $(call KernelPackage,iptunnel))\n\n\ndefine KernelPackage/ip-vti\n  SUBMENU:=$(NETWORK_SUPPORT_MENU)\n  TITLE:=IP VTI (Virtual Tunnel Interface)\n  DEPENDS:=+kmod-iptunnel +kmod-iptunnel4 +kmod-ipsec4\n  KCONFIG:=CONFIG_NET_IPVTI\n  FILES:=$(LINUX_DIR)/net/ipv4/ip_vti.ko\n  AUTOLOAD:=$(call AutoLoad,33,ip_vti)\nendef\n\ndefine KernelPackage/ip-vti/description\n Kernel modules for IP VTI (Virtual Tunnel Interface)\nendef\n\n$(eval $(call KernelPackage,ip-vti))\n\n\ndefine KernelPackage/ip6-vti\n  SUBMENU:=$(NETWORK_SUPPORT_MENU)\n  TITLE:=IPv6 VTI (Virtual Tunnel Interface)\n  DEPENDS:=@IPV6 +kmod-iptunnel +kmod-ip6-tunnel +kmod-ipsec6\n  KCONFIG:=CONFIG_IPV6_VTI\n  FILES:=$(LINUX_DIR)/net/ipv6/ip6_vti.ko\n  AUTOLOAD:=$(call AutoLoad,33,ip6_vti)\nendef\n\ndefine KernelPackage/ip6-vti/description\n Kernel modules for IPv6 VTI (Virtual Tunnel Interface)\nendef\n\n$(eval $(call KernelPackage,ip6-vti))\n\n\ndefine KernelPackage/xfrm-interface\n  SUBMENU:=$(NETWORK_SUPPORT_MENU)\n  TITLE:=IPsec XFRM Interface\n  DEPENDS:=@IPV6 +kmod-ipsec4 +kmod-ipsec6\n  KCONFIG:=CONFIG_XFRM_INTERFACE\n  FILES:=$(LINUX_DIR)/net/xfrm/xfrm_interface.ko\n  AUTOLOAD:=$(call AutoProbe,xfrm_interface)\nendef\n\ndefine KernelPackage/xfrm-interface/description\n Kernel module for XFRM interface support\nendef\n\n$(eval $(call KernelPackage,xfrm-interface))\n\n\ndefine KernelPackage/iptunnel4\n  SUBMENU:=$(NETWORK_SUPPORT_MENU)\n  TITLE:=IPv4 tunneling\n  HIDDEN:=1\n  KCONFIG:= \\\n\tCONFIG_INET_TUNNEL \\\n\tCONFIG_NET_IPIP=m\n  FILES:=$(LINUX_DIR)/net/ipv4/tunnel4.ko\n  AUTOLOAD:=$(call AutoLoad,31,tunnel4)\nendef\n\ndefine KernelPackage/iptunnel4/description\n Kernel modules for IPv4 tunneling\nendef\n\n$(eval $(call KernelPackage,iptunnel4))\n\n\ndefine KernelPackage/iptunnel6\n  SUBMENU:=$(NETWORK_SUPPORT_MENU)\n  TITLE:=IPv6 tunneling\n  DEPENDS:=@IPV6\n  KCONFIG:= \\\n\tCONFIG_INET6_TUNNEL\n  FILES:=$(LINUX_DIR)/net/ipv6/tunnel6.ko\n  AUTOLOAD:=$(call AutoLoad,31,tunnel6)\nendef\n\ndefine KernelPackage/iptunnel6/description\n Kernel modules for IPv6 tunneling\nendef\n\n$(eval $(call KernelPackage,iptunnel6))\n\n\ndefine KernelPackage/sit\n  SUBMENU:=$(NETWORK_SUPPORT_MENU)\n  DEPENDS:=@IPV6 +kmod-iptunnel +kmod-iptunnel4\n  TITLE:=IPv6-in-IPv4 tunnel\n  KCONFIG:=CONFIG_IPV6_SIT \\\n\tCONFIG_IPV6_SIT_6RD=y\n  FILES:=$(LINUX_DIR)/net/ipv6/sit.ko\n  AUTOLOAD:=$(call AutoLoad,32,sit)\nendef\n\ndefine KernelPackage/sit/description\n Kernel modules for IPv6-in-IPv4 tunnelling\nendef\n\n$(eval $(call KernelPackage,sit))\n\n\ndefine KernelPackage/fou\n  SUBMENU:=$(NETWORK_SUPPORT_MENU)\n  TITLE:=FOU and GUE decapsulation\n  DEPENDS:= \\\n\t+kmod-iptunnel \\\n\t+kmod-udptunnel4 \\\n\t+IPV6:kmod-udptunnel6\n  KCONFIG:= \\\n\tCONFIG_NET_FOU \\\n\tCONFIG_NET_FOU_IP_TUNNELS=y\n  FILES:=$(LINUX_DIR)/net/ipv4/fou.ko\n  AUTOLOAD:=$(call AutoProbe,fou)\nendef\n\ndefine KernelPackage/fou/description\n Kernel module for FOU (Foo over UDP) and GUE (Generic UDP Encapsulation) tunnelling.\n Requires Kernel 3.18 or newer.\nendef\n\n$(eval $(call KernelPackage,fou))\n\n\ndefine KernelPackage/fou6\n  SUBMENU:=$(NETWORK_SUPPORT_MENU)\n  TITLE:=FOU and GUE decapsulation over IPv6\n  DEPENDS:= @IPV6 \\\n\t+kmod-fou \\\n\t+kmod-ip6-tunnel\n  KCONFIG:= \\\n\tCONFIG_IPV6_FOU \\\n\tCONFIG_IPV6_FOU_TUNNEL\n  FILES:=$(LINUX_DIR)/net/ipv6/fou6.ko\n  AUTOLOAD:=$(call AutoProbe,fou6)\nendef\n\ndefine KernelPackage/fou6/description\n Kernel module for FOU (Foo over UDP) and GUE (Generic UDP Encapsulation) tunnelling over IPv6.\n Requires Kernel 3.18 or newer.\nendef\n\n$(eval $(call KernelPackage,fou6))\n\n\ndefine KernelPackage/ip6-tunnel\n  SUBMENU:=$(NETWORK_SUPPORT_MENU)\n  TITLE:=IP-in-IPv6 tunnelling\n  DEPENDS:=@IPV6 +kmod-iptunnel6\n  KCONFIG:= CONFIG_IPV6_TUNNEL\n  FILES:=$(LINUX_DIR)/net/ipv6/ip6_tunnel.ko\n  AUTOLOAD:=$(call AutoLoad,32,ip6_tunnel)\nendef\n\ndefine KernelPackage/ip6-tunnel/description\n Kernel modules for IPv6-in-IPv6 and IPv4-in-IPv6 tunnelling\nendef\n\n$(eval $(call KernelPackage,ip6-tunnel))\n\n\ndefine KernelPackage/gre\n  SUBMENU:=$(NETWORK_SUPPORT_MENU)\n  TITLE:=GRE support\n  DEPENDS:=+kmod-iptunnel\n  KCONFIG:=CONFIG_NET_IPGRE CONFIG_NET_IPGRE_DEMUX\n  FILES:=$(LINUX_DIR)/net/ipv4/ip_gre.ko $(LINUX_DIR)/net/ipv4/gre.ko\n  AUTOLOAD:=$(call AutoLoad,39,gre ip_gre)\nendef\n\ndefine KernelPackage/gre/description\n Generic Routing Encapsulation support\nendef\n\n$(eval $(call KernelPackage,gre))\n\n\ndefine KernelPackage/gre6\n  SUBMENU:=$(NETWORK_SUPPORT_MENU)\n  TITLE:=GRE support over IPV6\n  DEPENDS:=@IPV6 +kmod-iptunnel +kmod-ip6-tunnel +kmod-gre\n  KCONFIG:=CONFIG_IPV6_GRE\n  FILES:=$(LINUX_DIR)/net/ipv6/ip6_gre.ko\n  AUTOLOAD:=$(call AutoLoad,39,ip6_gre)\nendef\n\ndefine KernelPackage/gre6/description\n Generic Routing Encapsulation support over IPv6\nendef\n\n$(eval $(call KernelPackage,gre6))\n\n\ndefine KernelPackage/tun\n  SUBMENU:=$(NETWORK_SUPPORT_MENU)\n  TITLE:=Universal TUN/TAP driver\n  KCONFIG:=CONFIG_TUN\n  FILES:=$(LINUX_DIR)/drivers/net/tun.ko\n  AUTOLOAD:=$(call AutoLoad,30,tun)\nendef\n\ndefine KernelPackage/tun/description\n Kernel support for the TUN/TAP tunneling device\nendef\n\n$(eval $(call KernelPackage,tun))\n\n\ndefine KernelPackage/veth\n  SUBMENU:=$(NETWORK_SUPPORT_MENU)\n  TITLE:=Virtual ethernet pair device\n  KCONFIG:=CONFIG_VETH\n  FILES:=$(LINUX_DIR)/drivers/net/veth.ko\n  AUTOLOAD:=$(call AutoLoad,30,veth)\nendef\n\ndefine KernelPackage/veth/description\n This device is a local ethernet tunnel. Devices are created in pairs.\n When one end receives the packet it appears on its pair and vice\n versa.\nendef\n\n$(eval $(call KernelPackage,veth))\n\n\ndefine KernelPackage/vrf\n  SUBMENU:=$(NETWORK_SUPPORT_MENU)\n  TITLE:=Virtual Routing and Forwarding (Lite)\n  DEPENDS:=@KERNEL_NET_L3_MASTER_DEV\n  KCONFIG:=CONFIG_NET_VRF\n  FILES:=$(LINUX_DIR)/drivers/net/vrf.ko\n  AUTOLOAD:=$(call AutoLoad,30,vrf)\nendef\n\ndefine KernelPackage/vrf/description\n This option enables the support for mapping interfaces into VRF's. The\n support enables VRF devices.\nendef\n\n$(eval $(call KernelPackage,vrf))\n\n\ndefine KernelPackage/slhc\n  SUBMENU:=$(NETWORK_SUPPORT_MENU)\n  HIDDEN:=1\n  TITLE:=Serial Line Header Compression\n  DEPENDS:=+kmod-lib-crc-ccitt\n  KCONFIG:=CONFIG_SLHC\n  FILES:=$(LINUX_DIR)/drivers/net/slip/slhc.ko\nendef\n\n$(eval $(call KernelPackage,slhc))\n\n\ndefine KernelPackage/ppp\n  SUBMENU:=$(NETWORK_SUPPORT_MENU)\n  TITLE:=PPP modules\n  DEPENDS:=+kmod-lib-crc-ccitt +kmod-slhc\n  KCONFIG:= \\\n\tCONFIG_PPP \\\n\tCONFIG_PPP_ASYNC\n  FILES:= \\\n\t$(LINUX_DIR)/drivers/net/ppp/ppp_async.ko \\\n\t$(LINUX_DIR)/drivers/net/ppp/ppp_generic.ko\n  AUTOLOAD:=$(call AutoProbe,ppp_async)\nendef\n\ndefine KernelPackage/ppp/description\n Kernel modules for PPP support\nendef\n\n$(eval $(call KernelPackage,ppp))\n\n\ndefine KernelPackage/ppp-synctty\n  SUBMENU:=$(NETWORK_SUPPORT_MENU)\n  TITLE:=PPP sync tty support\n  DEPENDS:=kmod-ppp\n  KCONFIG:=CONFIG_PPP_SYNC_TTY\n  FILES:=$(LINUX_DIR)/drivers/net/ppp/ppp_synctty.ko\n  AUTOLOAD:=$(call AutoProbe,ppp_synctty)\nendef\n\ndefine KernelPackage/ppp-synctty/description\n Kernel modules for PPP sync tty support\nendef\n\n$(eval $(call KernelPackage,ppp-synctty))\n\n\ndefine KernelPackage/pppox\n  SUBMENU:=$(NETWORK_SUPPORT_MENU)\n  TITLE:=PPPoX helper\n  DEPENDS:=kmod-ppp\n  KCONFIG:=CONFIG_PPPOE\n  FILES:=$(LINUX_DIR)/drivers/net/ppp/pppox.ko\nendef\n\ndefine KernelPackage/pppox/description\n Kernel helper module for PPPoE and PPTP support\nendef\n\n$(eval $(call KernelPackage,pppox))\n\n\ndefine KernelPackage/pppoe\n  SUBMENU:=$(NETWORK_SUPPORT_MENU)\n  TITLE:=PPPoE support\n  DEPENDS:=kmod-ppp +kmod-pppox\n  KCONFIG:=CONFIG_PPPOE\n  FILES:=$(LINUX_DIR)/drivers/net/ppp/pppoe.ko\n  AUTOLOAD:=$(call AutoProbe,pppoe)\nendef\n\ndefine KernelPackage/pppoe/description\n Kernel module for PPPoE (PPP over Ethernet) support\nendef\n\n$(eval $(call KernelPackage,pppoe))\n\n\ndefine KernelPackage/pppoa\n  SUBMENU:=$(NETWORK_SUPPORT_MENU)\n  TITLE:=PPPoA support\n  DEPENDS:=kmod-ppp +kmod-atm\n  KCONFIG:=CONFIG_PPPOATM CONFIG_ATM_DRIVERS=y\n  FILES:=$(LINUX_DIR)/net/atm/pppoatm.ko\n  AUTOLOAD:=$(call AutoLoad,40,pppoatm)\nendef\n\ndefine KernelPackage/pppoa/description\n Kernel modules for PPPoA (PPP over ATM) support\nendef\n\n$(eval $(call KernelPackage,pppoa))\n\n\ndefine KernelPackage/pptp\n  SUBMENU:=$(NETWORK_SUPPORT_MENU)\n  TITLE:=PPtP support\n  DEPENDS:=kmod-ppp +kmod-gre +kmod-pppox\n  KCONFIG:=CONFIG_PPTP\n  FILES:=$(LINUX_DIR)/drivers/net/ppp/pptp.ko\n  AUTOLOAD:=$(call AutoProbe,pptp)\nendef\n\n$(eval $(call KernelPackage,pptp))\n\n\ndefine KernelPackage/pppol2tp\n  SUBMENU:=$(NETWORK_SUPPORT_MENU)\n  TITLE:=PPPoL2TP support\n  DEPENDS:=kmod-ppp +kmod-pppox +kmod-l2tp\n  KCONFIG:=CONFIG_PPPOL2TP\n  FILES:=$(LINUX_DIR)/net/l2tp/l2tp_ppp.ko\n  AUTOLOAD:=$(call AutoProbe,l2tp_ppp)\nendef\n\ndefine KernelPackage/pppol2tp/description\n  Kernel modules for PPPoL2TP (PPP over L2TP) support\nendef\n\n$(eval $(call KernelPackage,pppol2tp))\n\n\ndefine KernelPackage/ipoa\n  SUBMENU:=$(NETWORK_SUPPORT_MENU)\n  TITLE:=IPoA support\n  DEPENDS:=kmod-atm\n  KCONFIG:=CONFIG_ATM_CLIP\n  FILES:=$(LINUX_DIR)/net/atm/clip.ko\n  AUTOLOAD:=$(call AutoProbe,clip)\nendef\n\ndefine KernelPackage/ipoa/description\n  Kernel modules for IPoA (IP over ATM) support\nendef\n\n$(eval $(call KernelPackage,ipoa))\n\n\ndefine KernelPackage/mppe\n  SUBMENU:=$(NETWORK_SUPPORT_MENU)\n  TITLE:=Microsoft PPP compression/encryption\n  DEPENDS:=kmod-ppp +kmod-crypto-arc4 +kmod-crypto-sha1 +kmod-crypto-ecb\n  KCONFIG:= \\\n\tCONFIG_PPP_MPPE_MPPC \\\n\tCONFIG_PPP_MPPE\n  FILES:=$(LINUX_DIR)/drivers/net/ppp/ppp_mppe.ko\n  AUTOLOAD:=$(call AutoProbe,ppp_mppe)\nendef\n\ndefine KernelPackage/mppe/description\n Kernel modules for Microsoft PPP compression/encryption\nendef\n\n$(eval $(call KernelPackage,mppe))\n\n\nSCHED_MODULES = $(patsubst $(LINUX_DIR)/net/sched/%.ko,%,$(wildcard $(LINUX_DIR)/net/sched/*.ko))\nSCHED_MODULES_CORE = sch_ingress sch_fq_codel sch_hfsc sch_htb sch_tbf cls_basic cls_fw cls_route cls_flow cls_tcindex cls_u32 em_u32 act_gact act_mirred act_skbedit cls_matchall\nSCHED_MODULES_FILTER = $(SCHED_MODULES_CORE) act_connmark act_ctinfo sch_cake sch_netem sch_mqprio em_ipset cls_bpf cls_flower act_bpf act_vlan\nSCHED_MODULES_EXTRA = $(filter-out $(SCHED_MODULES_FILTER),$(SCHED_MODULES))\nSCHED_FILES = $(patsubst %,$(LINUX_DIR)/net/sched/%.ko,$(filter $(SCHED_MODULES_CORE),$(SCHED_MODULES)))\nSCHED_FILES_EXTRA = $(patsubst %,$(LINUX_DIR)/net/sched/%.ko,$(SCHED_MODULES_EXTRA))\n\ndefine KernelPackage/sched-core\n  SUBMENU:=$(NETWORK_SUPPORT_MENU)\n  TITLE:=Traffic schedulers\n  KCONFIG:= \\\n\tCONFIG_NET_SCHED=y \\\n\tCONFIG_NET_SCH_HFSC \\\n\tCONFIG_NET_SCH_HTB \\\n\tCONFIG_NET_SCH_TBF \\\n\tCONFIG_NET_SCH_INGRESS \\\n\tCONFIG_NET_SCH_FQ_CODEL \\\n\tCONFIG_NET_CLS=y \\\n\tCONFIG_NET_CLS_ACT=y \\\n\tCONFIG_NET_CLS_BASIC \\\n\tCONFIG_NET_CLS_FLOW \\\n\tCONFIG_NET_CLS_FW \\\n\tCONFIG_NET_CLS_ROUTE4 \\\n\tCONFIG_NET_CLS_TCINDEX \\\n\tCONFIG_NET_CLS_U32 \\\n\tCONFIG_NET_ACT_GACT \\\n\tCONFIG_NET_ACT_MIRRED \\\n\tCONFIG_NET_ACT_SKBEDIT \\\n\tCONFIG_NET_CLS_MATCHALL \\\n\tCONFIG_NET_EMATCH=y \\\n\tCONFIG_NET_EMATCH_U32\n  FILES:=$(SCHED_FILES)\n  AUTOLOAD:=$(call AutoLoad,70, $(SCHED_MODULES_CORE))\nendef\n\ndefine KernelPackage/sched-core/description\n Core kernel scheduler support for IP traffic\nendef\n\n$(eval $(call KernelPackage,sched-core))\n\n\ndefine KernelPackage/sched-cake\n  SUBMENU:=$(NETWORK_SUPPORT_MENU)\n  TITLE:=Cake fq_codel/blue derived shaper\n  DEPENDS:=+kmod-sched-core\n  KCONFIG:=CONFIG_NET_SCH_CAKE\n  FILES:=$(LINUX_DIR)/net/sched/sch_cake.ko\n  AUTOLOAD:=$(call AutoProbe,sch_cake)\nendef\n\ndefine KernelPackage/sched-cake/description\n Common Applications Kept Enhanced fq_codel/blue derived shaper\nendef\n\n$(eval $(call KernelPackage,sched-cake))\n\ndefine KernelPackage/sched-flower\n  SUBMENU:=$(NETWORK_SUPPORT_MENU)\n  TITLE:=Flower traffic classifier\n  DEPENDS:=+kmod-sched-core\n  KCONFIG:=CONFIG_NET_CLS_FLOWER\n  FILES:=$(LINUX_DIR)/net/sched/cls_flower.ko\n  AUTOLOAD:=$(call AutoProbe, cls_flower)\nendef\n\ndefine KernelPackage/sched-flower/description\n Allows to classify packets based on a configurable combination of packet keys and masks.\nendef\n\n$(eval $(call KernelPackage,sched-flower))\n\n\ndefine KernelPackage/sched-act-vlan\n  SUBMENU:=$(NETWORK_SUPPORT_MENU)\n  TITLE:=Traffic VLAN manipulation\n  DEPENDS:=+kmod-sched-core\n  KCONFIG:=CONFIG_NET_ACT_VLAN\n  FILES:=$(LINUX_DIR)/net/sched/act_vlan.ko\n  AUTOLOAD:=$(call AutoProbe, act_vlan)\nendef\n\ndefine KernelPackage/sched-act-vlan/description\n Allows to configure rules to push or pop vlan headers.\nendef\n\n$(eval $(call KernelPackage,sched-act-vlan))\n\n\ndefine KernelPackage/sched-mqprio\n  SUBMENU:=$(NETWORK_SUPPORT_MENU)\n  TITLE:=Multi-queue priority scheduler (MQPRIO)\n  DEPENDS:=+kmod-sched-core\n  KCONFIG:=CONFIG_NET_SCH_MQPRIO\n  FILES:=$(LINUX_DIR)/net/sched/sch_mqprio.ko\n  AUTOLOAD:=$(call AutoProbe, sch_mqprio)\nendef\n\ndefine KernelPackage/sched-mqprio/description\n  This scheduler allows QOS to be offloaded on NICs that have support for offloading QOS schedulers.\nendef\n\n$(eval $(call KernelPackage,sched-mqprio))\n\ndefine KernelPackage/sched-connmark\n  SUBMENU:=$(NETWORK_SUPPORT_MENU)\n  TITLE:=Traffic shaper conntrack mark support\n  DEPENDS:=+kmod-sched-core +kmod-ipt-core +kmod-ipt-conntrack-extra\n  KCONFIG:=CONFIG_NET_ACT_CONNMARK\n  FILES:=$(LINUX_DIR)/net/sched/act_connmark.ko\n  AUTOLOAD:=$(call AutoLoad,71, act_connmark)\nendef\n$(eval $(call KernelPackage,sched-connmark))\n\ndefine KernelPackage/sched-ctinfo\n  SUBMENU:=$(NETWORK_SUPPORT_MENU)\n  TITLE:=Traffic shaper ctinfo support\n  DEPENDS:=+kmod-sched-core +kmod-ipt-core +kmod-ipt-conntrack-extra\n  KCONFIG:=CONFIG_NET_ACT_CTINFO\n  FILES:=$(LINUX_DIR)/net/sched/act_ctinfo.ko\n  AUTOLOAD:=$(call AutoLoad,71, act_ctinfo)\nendef\n$(eval $(call KernelPackage,sched-ctinfo))\n\ndefine KernelPackage/sched-ipset\n  SUBMENU:=$(NETWORK_SUPPORT_MENU)\n  TITLE:=Traffic shaper ipset support\n  DEPENDS:=+kmod-sched-core +kmod-ipt-ipset\n  KCONFIG:= \\\n\tCONFIG_NET_EMATCH_IPSET\n  FILES:= \\\n\t$(LINUX_DIR)/net/sched/em_ipset.ko\n  AUTOLOAD:=$(call AutoLoad,72,em_ipset)\nendef\n\n$(eval $(call KernelPackage,sched-ipset))\n\n\ndefine KernelPackage/sched-bpf\n  SUBMENU:=$(NETWORK_SUPPORT_MENU)\n  TITLE:=Traffic shaper support for Berkeley Packet Filter\n  KCONFIG:= \\\n\tCONFIG_NET_CLS_BPF \\\n\tCONFIG_NET_ACT_BPF\n  FILES:= \\\n\t$(LINUX_DIR)/net/sched/cls_bpf.ko \\\n\t$(LINUX_DIR)/net/sched/act_bpf.ko\n  AUTOLOAD:=$(call AutoLoad,72,cls_bpf act_bpf)\nendef\n\n$(eval $(call KernelPackage,sched-bpf))\n\n\ndefine KernelPackage/bpf-test\n  SUBMENU:=$(NETWORK_SUPPORT_MENU)\n  TITLE:=Test Berkeley Packet Filter functionality\n  KCONFIG:=CONFIG_TEST_BPF\n  FILES:=$(LINUX_DIR)/lib/test_bpf.ko\nendef\n\n$(eval $(call KernelPackage,bpf-test))\n\n\ndefine KernelPackage/sched\n  SUBMENU:=$(NETWORK_SUPPORT_MENU)\n  TITLE:=Extra traffic schedulers\n  DEPENDS:=+kmod-sched-core +kmod-ipt-core +kmod-lib-crc32c\n  KCONFIG:= \\\n\tCONFIG_NET_SCH_CODEL \\\n\tCONFIG_NET_SCH_DSMARK \\\n\tCONFIG_NET_SCH_FIFO \\\n\tCONFIG_NET_SCH_GRED \\\n\tCONFIG_NET_SCH_MULTIQ \\\n\tCONFIG_NET_SCH_PRIO \\\n\tCONFIG_NET_SCH_RED \\\n\tCONFIG_NET_SCH_SFQ \\\n\tCONFIG_NET_SCH_TEQL \\\n\tCONFIG_NET_SCH_FQ \\\n\tCONFIG_NET_SCH_PIE \\\n\tCONFIG_NET_ACT_POLICE \\\n\tCONFIG_NET_ACT_IPT \\\n\tCONFIG_NET_ACT_PEDIT \\\n\tCONFIG_NET_ACT_SIMP \\\n\tCONFIG_NET_ACT_CSUM \\\n\tCONFIG_NET_EMATCH_CMP \\\n\tCONFIG_NET_EMATCH_NBYTE \\\n\tCONFIG_NET_EMATCH_META \\\n\tCONFIG_NET_EMATCH_TEXT\n  FILES:=$(SCHED_FILES_EXTRA)\n  AUTOLOAD:=$(call AutoLoad,73, $(SCHED_MODULES_EXTRA))\nendef\n\ndefine KernelPackage/sched/description\n Extra kernel schedulers modules for IP traffic\nendef\n\nSCHED_TEQL_HOTPLUG:=hotplug-sched-teql.sh\n\ndefine KernelPackage/sched/install\n\t$(INSTALL_DIR) $(1)/etc/hotplug.d/iface\n\t$(INSTALL_DATA) ./files/$(SCHED_TEQL_HOTPLUG) $(1)/etc/hotplug.d/iface/15-teql\nendef\n\n$(eval $(call KernelPackage,sched))\n\n\ndefine KernelPackage/tcp-bbr\n  SUBMENU:=$(NETWORK_SUPPORT_MENU)\n  TITLE:=BBR TCP congestion control\n  KCONFIG:=CONFIG_TCP_CONG_BBR\n  FILES:=$(LINUX_DIR)/net/ipv4/tcp_bbr.ko\n  AUTOLOAD:=$(call AutoProbe,tcp_bbr)\nendef\n\ndefine KernelPackage/tcp-bbr/description\n Kernel module for BBR (Bottleneck Bandwidth and RTT) TCP congestion\n control. It requires the fq (\"Fair Queue\") pacing packet scheduler.\n For kernel 4.13+, TCP internal pacing is implemented as fallback.\nendef\n\nTCP_BBR_SYSCTL_CONF:=sysctl-tcp-bbr.conf\n\ndefine KernelPackage/tcp-bbr/install\n\t$(INSTALL_DIR) $(1)/etc/sysctl.d\n\t$(INSTALL_DATA) ./files/$(TCP_BBR_SYSCTL_CONF) $(1)/etc/sysctl.d/12-tcp-bbr.conf\nendef\n\n$(eval $(call KernelPackage,tcp-bbr))\n\n\ndefine KernelPackage/tcp-hybla\n  SUBMENU:=$(NETWORK_SUPPORT_MENU)\n  TITLE:=TCP-Hybla congestion control algorithm\n  KCONFIG:=CONFIG_TCP_CONG_HYBLA\n  FILES:=$(LINUX_DIR)/net/ipv4/tcp_hybla.ko\n  AUTOLOAD:=$(call AutoProbe,tcp_hybla)\nendef\n\ndefine KernelPackage/tcp-hybla/description\n  TCP-Hybla is a sender-side only change that eliminates penalization of\n  long-RTT, large-bandwidth connections, like when satellite legs are\n  involved, especially when sharing a common bottleneck with normal\n  terrestrial connections.\nendef\n\n$(eval $(call KernelPackage,tcp-hybla))\n\n\ndefine KernelPackage/tcp-scalable\n  SUBMENU:=$(NETWORK_SUPPORT_MENU)\n  TITLE:=TCP-Scalable congestion control algorithm\n  KCONFIG:=CONFIG_TCP_CONG_SCALABLE\n  FILES:=$(LINUX_DIR)/net/ipv4/tcp_scalable.ko\n  AUTOLOAD:=$(call AutoProbe,tcp-scalable)\nendef\n\ndefine KernelPackage/tcp-scalable/description\n  Scalable TCP is a sender-side only change to TCP which uses a\n\tMIMD congestion control algorithm which has some nice scaling\n\tproperties, though is known to have fairness issues.\n\tSee http://www.deneholme.net/tom/scalable/\nendef\n\n$(eval $(call KernelPackage,tcp-scalable))\n\n\ndefine KernelPackage/ax25\n  SUBMENU:=$(NETWORK_SUPPORT_MENU)\n  TITLE:=AX25 support\n  DEPENDS:=+kmod-lib-crc16\n  KCONFIG:= \\\n\tCONFIG_HAMRADIO=y \\\n\tCONFIG_AX25 \\\n\tCONFIG_MKISS\n  FILES:= \\\n\t$(LINUX_DIR)/net/ax25/ax25.ko \\\n\t$(LINUX_DIR)/drivers/net/hamradio/mkiss.ko\n  AUTOLOAD:=$(call AutoLoad,80,ax25 mkiss)\nendef\n\ndefine KernelPackage/ax25/description\n Kernel modules for AX25 support\nendef\n\n$(eval $(call KernelPackage,ax25))\n\n\ndefine KernelPackage/pktgen\n  SUBMENU:=$(NETWORK_SUPPORT_MENU)\n  DEPENDS:=@!TARGET_uml\n  TITLE:=Network packet generator\n  KCONFIG:=CONFIG_NET_PKTGEN\n  FILES:=$(LINUX_DIR)/net/core/pktgen.ko\n  AUTOLOAD:=$(call AutoLoad,99,pktgen)\nendef\n\ndefine KernelPackage/pktgen/description\n  Kernel modules for the Network Packet Generator\nendef\n\n$(eval $(call KernelPackage,pktgen))\n\ndefine KernelPackage/l2tp\n  SUBMENU:=$(NETWORK_SUPPORT_MENU)\n  TITLE:=Layer Two Tunneling Protocol (L2TP)\n  DEPENDS:= \\\n\t+kmod-udptunnel4 \\\n\t+IPV6:kmod-udptunnel6\n  KCONFIG:=CONFIG_L2TP \\\n\tCONFIG_L2TP_V3=y \\\n\tCONFIG_L2TP_DEBUGFS=n\n  FILES:=$(LINUX_DIR)/net/l2tp/l2tp_core.ko \\\n\t$(LINUX_DIR)/net/l2tp/l2tp_netlink.ko\n  AUTOLOAD:=$(call AutoLoad,32,l2tp_core l2tp_netlink)\nendef\n\ndefine KernelPackage/l2tp/description\n Kernel modules for L2TP V3 Support\nendef\n\n$(eval $(call KernelPackage,l2tp))\n\n\ndefine KernelPackage/l2tp-eth\n  SUBMENU:=$(NETWORK_SUPPORT_MENU)\n  TITLE:=L2TP ethernet pseudowire support for L2TPv3\n  DEPENDS:=+kmod-l2tp\n  KCONFIG:=CONFIG_L2TP_ETH\n  FILES:=$(LINUX_DIR)/net/l2tp/l2tp_eth.ko\n  AUTOLOAD:=$(call AutoLoad,33,l2tp_eth)\nendef\n\ndefine KernelPackage/l2tp-eth/description\n Kernel modules for L2TP ethernet pseudowire support for L2TPv3\nendef\n\n$(eval $(call KernelPackage,l2tp-eth))\n\ndefine KernelPackage/l2tp-ip\n  SUBMENU:=$(NETWORK_SUPPORT_MENU)\n  TITLE:=L2TP IP encapsulation for L2TPv3\n  DEPENDS:=+kmod-l2tp\n  KCONFIG:=CONFIG_L2TP_IP\n  FILES:= \\\n\t$(LINUX_DIR)/net/l2tp/l2tp_ip.ko \\\n\t$(if $(CONFIG_IPV6),$(LINUX_DIR)/net/l2tp/l2tp_ip6.ko)\n  AUTOLOAD:=$(call AutoLoad,33,l2tp_ip $(if $(CONFIG_IPV6),l2tp_ip6))\nendef\n\ndefine KernelPackage/l2tp-ip/description\n Kernel modules for L2TP IP encapsulation for L2TPv3\nendef\n\n$(eval $(call KernelPackage,l2tp-ip))\n\n\ndefine KernelPackage/sctp\n  SUBMENU:=$(NETWORK_SUPPORT_MENU)\n  TITLE:=SCTP protocol kernel support\n  KCONFIG:=\\\n     CONFIG_IP_SCTP \\\n     CONFIG_SCTP_DBG_MSG=n \\\n     CONFIG_SCTP_DBG_OBJCNT=n \\\n     CONFIG_SCTP_HMAC_NONE=n \\\n     CONFIG_SCTP_HMAC_SHA1=n \\\n     CONFIG_SCTP_HMAC_MD5=y \\\n     CONFIG_SCTP_COOKIE_HMAC_SHA1=n \\\n     CONFIG_SCTP_COOKIE_HMAC_MD5=y \\\n     CONFIG_SCTP_DEFAULT_COOKIE_HMAC_NONE=n \\\n     CONFIG_SCTP_DEFAULT_COOKIE_HMAC_SHA1=n \\\n     CONFIG_SCTP_DEFAULT_COOKIE_HMAC_MD5=y\n  FILES:= $(LINUX_DIR)/net/sctp/sctp.ko\n  AUTOLOAD:= $(call AutoLoad,32,sctp)\n  DEPENDS:=+kmod-lib-crc32c +kmod-crypto-md5 +kmod-crypto-hmac \\\n    +LINUX_5_15:kmod-udptunnel4 +LINUX_5_15:kmod-udptunnel6\nendef\n\ndefine KernelPackage/sctp/description\n Kernel modules for SCTP protocol support\nendef\n\n$(eval $(call KernelPackage,sctp))\n\n\ndefine KernelPackage/netem\n  SUBMENU:=$(NETWORK_SUPPORT_MENU)\n  TITLE:=Network emulation functionality\n  DEPENDS:=+kmod-sched\n  KCONFIG:=CONFIG_NET_SCH_NETEM\n  FILES:=$(LINUX_DIR)/net/sched/sch_netem.ko\n  AUTOLOAD:=$(call AutoLoad,99,netem)\nendef\n\ndefine KernelPackage/netem/description\n  Kernel modules for emulating the properties of wide area networks\nendef\n\n$(eval $(call KernelPackage,netem))\n\ndefine KernelPackage/slip\n  SUBMENU:=$(NETWORK_SUPPORT_MENU)\n  DEPENDS:=+kmod-slhc\n  TITLE:=SLIP modules\n  KCONFIG:= \\\n       CONFIG_SLIP \\\n       CONFIG_SLIP_COMPRESSED=y \\\n       CONFIG_SLIP_SMART=y \\\n       CONFIG_SLIP_MODE_SLIP6=y\n\n  FILES:= \\\n       $(LINUX_DIR)/drivers/net/slip/slip.ko\n  AUTOLOAD:=$(call AutoLoad,30,slip)\nendef\n\ndefine KernelPackage/slip/description\n Kernel modules for SLIP support\nendef\n\n$(eval $(call KernelPackage,slip))\n\ndefine KernelPackage/dnsresolver\n  SUBMENU:=$(NETWORK_SUPPORT_MENU)\n  TITLE:=In-kernel DNS Resolver\n  KCONFIG:= CONFIG_DNS_RESOLVER\n  FILES:=$(LINUX_DIR)/net/dns_resolver/dns_resolver.ko\n  AUTOLOAD:=$(call AutoLoad,30,dns_resolver)\nendef\n\n$(eval $(call KernelPackage,dnsresolver))\n\ndefine KernelPackage/rxrpc\n  SUBMENU:=$(NETWORK_SUPPORT_MENU)\n  TITLE:=AF_RXRPC support\n  HIDDEN:=1\n  KCONFIG:= \\\n\tCONFIG_AF_RXRPC \\\n\tCONFIG_RXKAD=m \\\n\tCONFIG_AF_RXRPC_DEBUG=n\n  FILES:= \\\n\t$(LINUX_DIR)/net/rxrpc/rxrpc.ko\n  AUTOLOAD:=$(call AutoLoad,30,rxrpc.ko)\n  DEPENDS:= +kmod-crypto-manager +kmod-crypto-pcbc +kmod-crypto-fcrypt\nendef\n\ndefine KernelPackage/rxrpc/description\n  Kernel support for AF_RXRPC; required for AFS client\nendef\n\n$(eval $(call KernelPackage,rxrpc))\n\ndefine KernelPackage/mpls\n  SUBMENU:=$(NETWORK_SUPPORT_MENU)\n  TITLE:=MPLS support\n  DEPENDS:=+kmod-iptunnel\n  KCONFIG:= \\\n\tCONFIG_MPLS=y \\\n\tCONFIG_LWTUNNEL=y \\\n\tCONFIG_LWTUNNEL_BPF=n \\\n\tCONFIG_NET_MPLS_GSO=m \\\n\tCONFIG_MPLS_ROUTING=m \\\n\tCONFIG_MPLS_IPTUNNEL=m\n  FILES:= \\\n\t$(LINUX_DIR)/net/mpls/mpls_gso.ko \\\n\t$(LINUX_DIR)/net/mpls/mpls_iptunnel.ko \\\n\t$(LINUX_DIR)/net/mpls/mpls_router.ko\n  AUTOLOAD:=$(call AutoLoad,30,mpls_router mpls_iptunnel mpls_gso)\nendef\n\ndefine KernelPackage/mpls/description\n  Kernel support for MPLS\nendef\n\n$(eval $(call KernelPackage,mpls))\n\ndefine KernelPackage/9pnet\n  SUBMENU:=$(NETWORK_SUPPORT_MENU)\n  TITLE:=Plan 9 Resource Sharing Support (9P2000)\n  DEPENDS:=@VIRTIO_SUPPORT\n  KCONFIG:= \\\n\tCONFIG_NET_9P \\\n\tCONFIG_NET_9P_DEBUG=n \\\n\tCONFIG_NET_9P_XEN=n \\\n\tCONFIG_NET_9P_VIRTIO\n  FILES:= \\\n\t$(LINUX_DIR)/net/9p/9pnet.ko \\\n\t$(LINUX_DIR)/net/9p/9pnet_virtio.ko\n  AUTOLOAD:=$(call AutoLoad,29,9pnet 9pnet_virtio)\nendef\n\ndefine KernelPackage/9pnet/description\n  Kernel support support for\n  Plan 9 resource sharing via the 9P2000 protocol.\nendef\n\n$(eval $(call KernelPackage,9pnet))\n\n\ndefine KernelPackage/nlmon\n  SUBMENU:=$(NETWORK_SUPPORT_MENU)\n  TITLE:=Virtual netlink monitoring device\n  KCONFIG:=CONFIG_NLMON\n  FILES:=$(LINUX_DIR)/drivers/net/nlmon.ko\n  AUTOLOAD:=$(call AutoProbe,nlmon)\nendef\n\ndefine KernelPackage/nlmon/description\n  Kernel module which adds a monitoring device for netlink.\nendef\n\n$(eval $(call KernelPackage,nlmon))\n\n\ndefine KernelPackage/mdio\n  SUBMENU:=$(NETWORK_SUPPORT_MENU)\n  TITLE:=MDIO (clause 45) PHY support\n  KCONFIG:=CONFIG_MDIO\n  HIDDEN:=1\n  FILES:=$(LINUX_DIR)/drivers/net/mdio.ko\n  AUTOLOAD:=$(call AutoLoad,32,mdio)\nendef\n\ndefine KernelPackage/mdio/description\n Kernel modules for MDIO (clause 45) PHY support\nendef\n\n$(eval $(call KernelPackage,mdio))\n\ndefine KernelPackage/macsec\n  SUBMENU:=$(NETWORK_SUPPORT_MENU)\n  TITLE:=IEEE 802.1AE MAC-level encryption (MAC)\n  DEPENDS:=+kmod-crypto-gcm\n  KCONFIG:=CONFIG_MACSEC\n  FILES:=$(LINUX_DIR)/drivers/net/macsec.ko\n  AUTOLOAD:=$(call AutoLoad,13,macsec)\nendef\n\ndefine KernelPackage/macsec/description\n MACsec is an encryption standard for Ethernet.\nendef\n\n$(eval $(call KernelPackage,macsec))\n\n\ndefine KernelPackage/netlink-diag\n  SUBMENU:=$(NETWORK_SUPPORT_MENU)\n  TITLE:=Netlink diag support for ss utility\n  KCONFIG:=CONFIG_NETLINK_DIAG\n  FILES:=$(LINUX_DIR)/net/netlink/netlink_diag.ko\n  AUTOLOAD:=$(call AutoLoad,31,netlink-diag)\nendef\n\ndefine KernelPackage/netlink-diag/description\n Netlink diag is a module made for use with iproute2's ss utility\nendef\n\n$(eval $(call KernelPackage,netlink-diag))\n\n\ndefine KernelPackage/inet-diag\n  SUBMENU:=$(NETWORK_SUPPORT_MENU)\n  TITLE:=INET diag support for ss utility\n  KCONFIG:= \\\n\tCONFIG_INET_DIAG \\\n\tCONFIG_INET_TCP_DIAG \\\n\tCONFIG_INET_UDP_DIAG \\\n\tCONFIG_INET_RAW_DIAG \\\n\tCONFIG_INET_DIAG_DESTROY=n\n  FILES:= \\\n\t$(LINUX_DIR)/net/ipv4/inet_diag.ko \\\n\t$(LINUX_DIR)/net/ipv4/tcp_diag.ko \\\n\t$(LINUX_DIR)/net/ipv4/udp_diag.ko \\\n\t$(LINUX_DIR)/net/ipv4/raw_diag.ko\n  AUTOLOAD:=$(call AutoLoad,31,inet_diag tcp_diag udp_diag raw_diag)\nendef\n\ndefine KernelPackage/inet-diag/description\nSupport for INET (TCP, DCCP, etc) socket monitoring interface used by\nnative Linux tools such as ss.\nendef\n\n$(eval $(call KernelPackage,inet-diag))\n\n\ndefine KernelPackage/wireguard\n  SUBMENU:=$(NETWORK_SUPPORT_MENU)\n  TITLE:=WireGuard secure network tunnel\n  DEPENDS:= \\\n\t  +kmod-crypto-lib-blake2s \\\n\t  +kmod-crypto-lib-chacha20poly1305 \\\n\t  +kmod-crypto-lib-curve25519 \\\n\t  +kmod-udptunnel4 \\\n\t  +IPV6:kmod-udptunnel6\n  KCONFIG:= \\\n\t  CONFIG_WIREGUARD \\\n\t  CONFIG_WIREGUARD_DEBUG=n\n  FILES:=$(LINUX_DIR)/drivers/net/wireguard/wireguard.ko\n  AUTOLOAD:=$(call AutoProbe,wireguard)\nendef\n\ndefine KernelPackage/wireguard/description\n  WireGuard is a novel VPN that runs inside the Linux Kernel and utilizes\n  state-of-the-art cryptography. It aims to be faster, simpler, leaner, and\n  more useful than IPSec, while avoiding the massive headache. It intends to\n  be considerably more performant than OpenVPN.  WireGuard is designed as a\n  general purpose VPN for running on embedded interfaces and super computers\n  alike, fit for many different circumstances. It uses UDP.\nendef\n\n$(eval $(call KernelPackage,wireguard))\n"
  },
  {
    "path": "package/kernel/linux/modules/nls.mk",
    "content": "#\n# Copyright (C) 2006-2011 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ndefine KernelPackage/nls-base\n  SUBMENU:=Native Language Support\n  TITLE:=Native Language Support\n  KCONFIG:=CONFIG_NLS\n  FILES:=$(LINUX_DIR)/fs/nls/nls_base.ko\nendef\n\ndefine KernelPackage/nls-base/description\n Kernel module for NLS (Native Language Support)\nendef\n\n$(eval $(call KernelPackage,nls-base))\n\n\ndefine KernelPackage/nls-cp437\n  SUBMENU:=Native Language Support\n  TITLE:=Codepage 437 (United States, Canada)\n  KCONFIG:=CONFIG_NLS_CODEPAGE_437\n  FILES:=$(LINUX_DIR)/fs/nls/nls_cp437.ko\n  AUTOLOAD:=$(call AutoLoad,25,nls_cp437)\n  $(call AddDepends/nls)\nendef\n\ndefine KernelPackage/nls-cp437/description\n Kernel module for NLS Codepage 437 (United States, Canada)\nendef\n\n$(eval $(call KernelPackage,nls-cp437))\n\n\ndefine KernelPackage/nls-cp775\n  SUBMENU:=Native Language Support\n  TITLE:=Codepage 775 (Baltic Rim)\n  KCONFIG:=CONFIG_NLS_CODEPAGE_775\n  FILES:=$(LINUX_DIR)/fs/nls/nls_cp775.ko\n  AUTOLOAD:=$(call AutoLoad,25,nls_cp775)\n  $(call AddDepends/nls)\nendef\n\ndefine KernelPackage/nls-cp775/description\n Kernel module for NLS Codepage 775 (Baltic Rim)\nendef\n\n$(eval $(call KernelPackage,nls-cp775))\n\n\ndefine KernelPackage/nls-cp850\n  SUBMENU:=Native Language Support\n  TITLE:=Codepage 850 (Europe)\n  KCONFIG:=CONFIG_NLS_CODEPAGE_850\n  FILES:=$(LINUX_DIR)/fs/nls/nls_cp850.ko\n  AUTOLOAD:=$(call AutoLoad,25,nls_cp850)\n  $(call AddDepends/nls)\nendef\n\ndefine KernelPackage/nls-cp850/description\n Kernel module for NLS Codepage 850 (Europe)\nendef\n\n$(eval $(call KernelPackage,nls-cp850))\n\n\ndefine KernelPackage/nls-cp852\n  SUBMENU:=Native Language Support\n  TITLE:=Codepage 852 (Europe)\n  KCONFIG:=CONFIG_NLS_CODEPAGE_852\n  FILES:=$(LINUX_DIR)/fs/nls/nls_cp852.ko\n  AUTOLOAD:=$(call AutoLoad,25,nls_cp852)\n  $(call AddDepends/nls)\nendef\n\ndefine KernelPackage/nls-cp852/description\n Kernel module for NLS Codepage 852 (Europe)\nendef\n\n$(eval $(call KernelPackage,nls-cp852))\n\n\ndefine KernelPackage/nls-cp862\n  SUBMENU:=Native Language Support\n  TITLE:=Codepage 862 (Hebrew)\n  KCONFIG:=CONFIG_NLS_CODEPAGE_862\n  FILES:=$(LINUX_DIR)/fs/nls/nls_cp862.ko\n  AUTOLOAD:=$(call AutoLoad,25,nls_cp862)\n  $(call AddDepends/nls)\nendef\n\ndefine KernelPackage/nls-cp862/description\n  Kernel module for NLS Codepage 862 (Hebrew)\nendef\n\n$(eval $(call KernelPackage,nls-cp862))\n\n\ndefine KernelPackage/nls-cp864\n  SUBMENU:=Native Language Support\n  TITLE:=Codepage 864 (Arabic)\n  KCONFIG:=CONFIG_NLS_CODEPAGE_864\n  FILES:=$(LINUX_DIR)/fs/nls/nls_cp864.ko\n  AUTOLOAD:=$(call AutoLoad,25,nls_cp864)\n  $(call AddDepends/nls)\nendef\n\ndefine KernelPackage/nls-cp864/description\n  Kernel module for NLS Codepage 864 (Arabic)\nendef\n\n$(eval $(call KernelPackage,nls-cp864))\n\n\ndefine KernelPackage/nls-cp866\n  SUBMENU:=Native Language Support\n  TITLE:=Codepage 866 (Cyrillic)\n  KCONFIG:=CONFIG_NLS_CODEPAGE_866\n  FILES:=$(LINUX_DIR)/fs/nls/nls_cp866.ko\n  AUTOLOAD:=$(call AutoLoad,25,nls_cp866)\n  $(call AddDepends/nls)\nendef\n\ndefine KernelPackage/nls-cp866/description\n  Kernel module for NLS Codepage 866 (Cyrillic)\nendef\n\n$(eval $(call KernelPackage,nls-cp866))\n\n\ndefine KernelPackage/nls-cp932\n  SUBMENU:=Native Language Support\n  TITLE:=Codepage 932 (Japanese)\n  KCONFIG:=CONFIG_NLS_CODEPAGE_932\n  FILES:=$(LINUX_DIR)/fs/nls/nls_cp932.ko\n  AUTOLOAD:=$(call AutoLoad,25,nls_cp932)\n  $(call AddDepends/nls)\nendef\n\ndefine KernelPackage/nls-cp932/description\n  Kernel module for NLS Codepage 932 (Japanese)\nendef\n\n$(eval $(call KernelPackage,nls-cp932))\n\n\ndefine KernelPackage/nls-cp936\n  SUBMENU:=Native Language Support\n  TITLE:=Codepage 936 (Simplified Chinese)\n  KCONFIG:=CONFIG_NLS_CODEPAGE_936\n  FILES:=$(LINUX_DIR)/fs/nls/nls_cp936.ko\n  AUTOLOAD:=$(call AutoLoad,25,nls_cp936)\n  $(call AddDepends/nls)\nendef\n\ndefine KernelPackage/nls-cp936/description\n  Kernel module for NLS Codepage 936 (Simplified Chinese)\nendef\n\n$(eval $(call KernelPackage,nls-cp936))\n\n\ndefine KernelPackage/nls-cp950\n  SUBMENU:=Native Language Support\n  TITLE:=Codepage 950 (Traditional Chinese)\n  KCONFIG:=CONFIG_NLS_CODEPAGE_950\n  FILES:=$(LINUX_DIR)/fs/nls/nls_cp950.ko\n  AUTOLOAD:=$(call AutoLoad,25,nls_cp950)\n  $(call AddDepends/nls)\nendef\n\ndefine KernelPackage/nls-cp950/description\n  Kernel module for NLS Codepage 950 (Traditional Chinese)\nendef\n\n$(eval $(call KernelPackage,nls-cp950))\n\n\ndefine KernelPackage/nls-cp1250\n  SUBMENU:=Native Language Support\n  TITLE:=Codepage 1250 (Eastern Europe)\n  KCONFIG:=CONFIG_NLS_CODEPAGE_1250\n  FILES:=$(LINUX_DIR)/fs/nls/nls_cp1250.ko\n  AUTOLOAD:=$(call AutoLoad,25,nls_cp1250)\n  $(call AddDepends/nls)\nendef\n\ndefine KernelPackage/nls-cp1250/description\n Kernel module for NLS Codepage 1250 (Eastern Europe)\nendef\n\n$(eval $(call KernelPackage,nls-cp1250))\n\n\ndefine KernelPackage/nls-cp1251\n  SUBMENU:=Native Language Support\n  TITLE:=Codepage 1251 (Russian)\n  KCONFIG:=CONFIG_NLS_CODEPAGE_1251\n  FILES:=$(LINUX_DIR)/fs/nls/nls_cp1251.ko\n  AUTOLOAD:=$(call AutoLoad,25,nls_cp1251)\n  $(call AddDepends/nls)\nendef\n\ndefine KernelPackage/nls-cp1251/description\n Kernel module for NLS Codepage 1251 (Russian)\nendef\n\n$(eval $(call KernelPackage,nls-cp1251))\n\n\ndefine KernelPackage/nls-iso8859-1\n  SUBMENU:=Native Language Support\n  TITLE:=ISO 8859-1 (Latin 1; Western European Languages)\n  KCONFIG:=CONFIG_NLS_ISO8859_1\n  FILES:=$(LINUX_DIR)/fs/nls/nls_iso8859-1.ko\n  AUTOLOAD:=$(call AutoLoad,25,nls_iso8859-1)\n  $(call AddDepends/nls)\nendef\n\ndefine KernelPackage/nls-iso8859-1/description\n Kernel module for NLS ISO 8859-1 (Latin 1)\nendef\n\n$(eval $(call KernelPackage,nls-iso8859-1))\n\n\ndefine KernelPackage/nls-iso8859-2\n  SUBMENU:=Native Language Support\n  TITLE:=ISO 8859-2 (Latin 2; Central European Languages)\n  KCONFIG:=CONFIG_NLS_ISO8859_2\n  FILES:=$(LINUX_DIR)/fs/nls/nls_iso8859-2.ko\n  AUTOLOAD:=$(call AutoLoad,25,nls_iso8859-2)\n  $(call AddDepends/nls)\nendef\n\ndefine KernelPackage/nls-iso8859-2/description\n Kernel module for NLS ISO 8859-2 (Latin 2)\nendef\n\n$(eval $(call KernelPackage,nls-iso8859-2))\n\n\ndefine KernelPackage/nls-iso8859-6\n  SUBMENU:=Native Language Support\n  TITLE:=ISO 8859-6 (Arabic)\n  KCONFIG:=CONFIG_NLS_ISO8859_6\n  FILES:=$(LINUX_DIR)/fs/nls/nls_iso8859-6.ko\n  AUTOLOAD:=$(call AutoLoad,25,nls_iso8859-6)\n  $(call AddDepends/nls)\nendef\n\ndefine KernelPackage/nls-iso8859-6/description\n Kernel module for NLS ISO 8859-6 (Arabic)\nendef\n\n$(eval $(call KernelPackage,nls-iso8859-6))\n\n\ndefine KernelPackage/nls-iso8859-8\n  SUBMENU:=Native Language Support\n  TITLE:=ISO 8859-8, CP1255 (Hebrew)\n  KCONFIG:=CONFIG_NLS_ISO8859_8\n  FILES:=$(LINUX_DIR)/fs/nls/nls_cp1255.ko\n  AUTOLOAD:=$(call AutoLoad,25,nls_cp1255)\n  $(call AddDepends/nls)\nendef\n\ndefine KernelPackage/nls-iso8859-8/description\n Kernel module for Hebrew charsets (ISO-8859-8, CP1255)\nendef\n\n$(eval $(call KernelPackage,nls-iso8859-8))\n\n\ndefine KernelPackage/nls-iso8859-13\n  SUBMENU:=Native Language Support\n  TITLE:=ISO 8859-13 (Latin 7; Baltic)\n  KCONFIG:=CONFIG_NLS_ISO8859_13\n  FILES:=$(LINUX_DIR)/fs/nls/nls_iso8859-13.ko\n  AUTOLOAD:=$(call AutoLoad,25,nls_iso8859-13)\n  $(call AddDepends/nls)\nendef\n\ndefine KernelPackage/nls-iso8859-13/description\n Kernel module for NLS ISO 8859-13 (Latin 7; Baltic)\nendef\n\n$(eval $(call KernelPackage,nls-iso8859-13))\n\n\ndefine KernelPackage/nls-iso8859-15\n  SUBMENU:=Native Language Support\n  TITLE:=ISO 8859-15 (Latin 9; Western, with Euro symbol)\n  KCONFIG:=CONFIG_NLS_ISO8859_15\n  FILES:=$(LINUX_DIR)/fs/nls/nls_iso8859-15.ko\n  AUTOLOAD:=$(call AutoLoad,25,nls_iso8859-15)\n  $(call AddDepends/nls)\nendef\n\ndefine KernelPackage/nls-iso8859-15/description\n Kernel module for NLS ISO 8859-15 (Latin 9)\nendef\n\n$(eval $(call KernelPackage,nls-iso8859-15))\n\n\ndefine KernelPackage/nls-koi8r\n  SUBMENU:=Native Language Support\n  TITLE:=KOI8-R (Russian)\n  KCONFIG:=CONFIG_NLS_KOI8_R\n  FILES:=$(LINUX_DIR)/fs/nls/nls_koi8-r.ko\n  AUTOLOAD:=$(call AutoLoad,25,nls_koi8-r)\n  $(call AddDepends/nls)\nendef\n\ndefine KernelPackage/nls-koi8r/description\n Kernel module for NLS KOI8-R (Russian)\nendef\n\n$(eval $(call KernelPackage,nls-koi8r))\n\n\ndefine KernelPackage/nls-utf8\n  SUBMENU:=Native Language Support\n  TITLE:=UTF-8\n  KCONFIG:=CONFIG_NLS_UTF8\n  FILES:=$(LINUX_DIR)/fs/nls/nls_utf8.ko\n  AUTOLOAD:=$(call AutoLoad,25,nls_utf8)\n  $(call AddDepends/nls)\nendef\n\ndefine KernelPackage/nls-utf8/description\n Kernel module for NLS UTF-8\nendef\n\n$(eval $(call KernelPackage,nls-utf8))\n"
  },
  {
    "path": "package/kernel/linux/modules/other.mk",
    "content": "#\n# Copyright (C) 2006-2015 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\nOTHER_MENU:=Other modules\n\nWATCHDOG_DIR:=watchdog\n\n\ndefine KernelPackage/6lowpan\n  SUBMENU:=$(OTHER_MENU)\n  TITLE:=6LoWPAN shared code\n  KCONFIG:= \\\n\tCONFIG_6LOWPAN \\\n\tCONFIG_6LOWPAN_NHC=n\n  FILES:=$(LINUX_DIR)/net/6lowpan/6lowpan.ko\n  AUTOLOAD:=$(call AutoProbe,6lowpan)\nendef\n\ndefine KernelPackage/6lowpan/description\n  Shared 6lowpan code for IEEE 802.15.4 and Bluetooth.\nendef\n\n$(eval $(call KernelPackage,6lowpan))\n\n\ndefine KernelPackage/bluetooth\n  SUBMENU:=$(OTHER_MENU)\n  TITLE:=Bluetooth support\n  DEPENDS:=@USB_SUPPORT +kmod-usb-core +kmod-crypto-hash +kmod-crypto-ecb +kmod-lib-crc16 +kmod-hid +kmod-crypto-cmac +kmod-regmap-core +kmod-crypto-ecdh\n  KCONFIG:= \\\n\tCONFIG_BT \\\n\tCONFIG_BT_BREDR=y \\\n\tCONFIG_BT_DEBUGFS=n \\\n\tCONFIG_BT_LE=y \\\n\tCONFIG_BT_RFCOMM \\\n\tCONFIG_BT_BNEP \\\n\tCONFIG_BT_HCIBTUSB \\\n\tCONFIG_BT_HCIBTUSB_BCM=n \\\n\tCONFIG_BT_HCIUART \\\n\tCONFIG_BT_HCIUART_BCM=n \\\n\tCONFIG_BT_HCIUART_INTEL=n \\\n\tCONFIG_BT_HCIUART_H4 \\\n\tCONFIG_BT_HCIUART_NOKIA=n \\\n\tCONFIG_BT_HIDP\n  $(call AddDepends/rfkill)\n  FILES:= \\\n\t$(LINUX_DIR)/net/bluetooth/bluetooth.ko \\\n\t$(LINUX_DIR)/net/bluetooth/rfcomm/rfcomm.ko \\\n\t$(LINUX_DIR)/net/bluetooth/bnep/bnep.ko \\\n\t$(LINUX_DIR)/net/bluetooth/hidp/hidp.ko \\\n\t$(LINUX_DIR)/drivers/bluetooth/hci_uart.ko \\\n\t$(LINUX_DIR)/drivers/bluetooth/btusb.ko \\\n\t$(LINUX_DIR)/drivers/bluetooth/btintel.ko\n  AUTOLOAD:=$(call AutoProbe,bluetooth rfcomm bnep hidp hci_uart btusb)\nendef\n\ndefine KernelPackage/bluetooth/description\n Kernel support for Bluetooth devices\nendef\n\n$(eval $(call KernelPackage,bluetooth))\n\ndefine KernelPackage/ath3k\n  SUBMENU:=$(OTHER_MENU)\n  TITLE:=ATH3K Kernel Module support\n  DEPENDS:=+kmod-bluetooth +ar3k-firmware\n  KCONFIG:= \\\n\tCONFIG_BT_ATH3K \\\n\tCONFIG_BT_HCIUART_ATH3K=y\n  FILES:= \\\n\t$(LINUX_DIR)/drivers/bluetooth/ath3k.ko\n  AUTOLOAD:=$(call AutoProbe,ath3k)\nendef\n\ndefine KernelPackage/ath3k/description\n Kernel support for ATH3K Module\nendef\n\n$(eval $(call KernelPackage,ath3k))\n\n\ndefine KernelPackage/bluetooth-6lowpan\n  SUBMENU:=$(OTHER_MENU)\n  TITLE:=Bluetooth 6LoWPAN support\n  DEPENDS:=+kmod-6lowpan +kmod-bluetooth\n  KCONFIG:=CONFIG_BT_6LOWPAN\n  FILES:=$(LINUX_DIR)/net/bluetooth/bluetooth_6lowpan.ko\n  AUTOLOAD:=$(call AutoProbe,bluetooth_6lowpan)\nendef\n\ndefine KernelPackage/bluetooth-6lowpan/description\n Kernel support for 6LoWPAN over Bluetooth Low Energy devices\nendef\n\n$(eval $(call KernelPackage,bluetooth-6lowpan))\n\n\ndefine KernelPackage/btmrvl\n  SUBMENU:=$(OTHER_MENU)\n  TITLE:=Marvell Bluetooth Kernel Module support\n  DEPENDS:=+kmod-mmc +kmod-bluetooth +mwifiex-sdio-firmware\n  KCONFIG:= \\\n\tCONFIG_BT_MRVL \\\n\tCONFIG_BT_MRVL_SDIO\n  FILES:= \\\n\t$(LINUX_DIR)/drivers/bluetooth/btmrvl.ko \\\n\t$(LINUX_DIR)/drivers/bluetooth/btmrvl_sdio.ko\n  AUTOLOAD:=$(call AutoProbe,btmrvl btmrvl_sdio)\nendef\n\ndefine KernelPackage/btmrvl/description\n Kernel support for Marvell SDIO Bluetooth Module\nendef\n\n$(eval $(call KernelPackage,btmrvl))\n\n\ndefine KernelPackage/dma-buf\n  SUBMENU:=$(OTHER_MENU)\n  TITLE:=DMA shared buffer support\n  HIDDEN:=1\n  KCONFIG:=CONFIG_DMA_SHARED_BUFFER\n  ifeq ($(strip $(CONFIG_EXTERNAL_KERNEL_TREE)),\"\")\n    ifeq ($(strip $(CONFIG_KERNEL_GIT_CLONE_URI)),\"\")\n      FILES:=$(LINUX_DIR)/drivers/dma-buf/dma-shared-buffer.ko\n    endif\n  endif\n  AUTOLOAD:=$(call AutoLoad,20,dma-shared-buffer)\nendef\n$(eval $(call KernelPackage,dma-buf))\n\n\ndefine KernelPackage/eeprom-93cx6\n  SUBMENU:=$(OTHER_MENU)\n  TITLE:=EEPROM 93CX6 support\n  KCONFIG:=CONFIG_EEPROM_93CX6\n  FILES:=$(LINUX_DIR)/drivers/misc/eeprom/eeprom_93cx6.ko\n  AUTOLOAD:=$(call AutoLoad,20,eeprom_93cx6)\nendef\n\ndefine KernelPackage/eeprom-93cx6/description\n Kernel module for EEPROM 93CX6 support\nendef\n\n$(eval $(call KernelPackage,eeprom-93cx6))\n\n\ndefine KernelPackage/eeprom-at24\n  SUBMENU:=$(OTHER_MENU)\n  TITLE:=EEPROM AT24 support\n  KCONFIG:=CONFIG_EEPROM_AT24\n  DEPENDS:=+kmod-i2c-core +kmod-regmap-i2c\n  FILES:=$(LINUX_DIR)/drivers/misc/eeprom/at24.ko\n  AUTOLOAD:=$(call AutoProbe,at24)\nendef\n\ndefine KernelPackage/eeprom-at24/description\n Kernel module for most I2C EEPROMs\nendef\n\n$(eval $(call KernelPackage,eeprom-at24))\n\n\ndefine KernelPackage/eeprom-at25\n  SUBMENU:=$(OTHER_MENU)\n  TITLE:=EEPROM AT25 support\n  KCONFIG:=CONFIG_EEPROM_AT25\n  FILES:=$(LINUX_DIR)/drivers/misc/eeprom/at25.ko\n  AUTOLOAD:=$(call AutoProbe,at25)\nendef\n\ndefine KernelPackage/eeprom-at25/description\n Kernel module for most SPI EEPROMs\nendef\n\n$(eval $(call KernelPackage,eeprom-at25))\n\n\ndefine KernelPackage/google-firmware\n  SUBMENU:=$(OTHER_MENU)\n  TITLE:=Google firmware drivers (Coreboot, VPD, Memconsole)\n  KCONFIG:= \\\n\tCONFIG_GOOGLE_FIRMWARE=y \\\n\tCONFIG_GOOGLE_COREBOOT_TABLE \\\n\tCONFIG_GOOGLE_MEMCONSOLE \\\n\tCONFIG_GOOGLE_MEMCONSOLE_COREBOOT \\\n\tCONFIG_GOOGLE_VPD\n  FILES:= \\\n\t  $(LINUX_DIR)/drivers/firmware/google/coreboot_table.ko \\\n\t  $(LINUX_DIR)/drivers/firmware/google/memconsole.ko \\\n\t  $(LINUX_DIR)/drivers/firmware/google/memconsole-coreboot.ko \\\n\t  $(LINUX_DIR)/drivers/firmware/google/vpd-sysfs.ko\n  AUTOLOAD:=$(call AutoProbe,coreboot_table memconsole-coreboot vpd-sysfs)\nendef\n\ndefine KernelPackage/google-firmware/description\n  Kernel modules for Google firmware drivers. Useful for examining firmware and\n  boot details on devices using a Google bootloader based on Coreboot. Provides\n  files like /sys/firmware/log and /sys/firmware/vpd.\nendef\n\n$(eval $(call KernelPackage,google-firmware))\n\n\ndefine KernelPackage/gpio-f7188x\n  SUBMENU:=$(OTHER_MENU)\n  TITLE:=Fintek F718xx/F818xx GPIO Support\n  DEPENDS:=@GPIO_SUPPORT @TARGET_x86\n  KCONFIG:=CONFIG_GPIO_F7188X\n  FILES:=$(LINUX_DIR)/drivers/gpio/gpio-f7188x.ko\n  AUTOLOAD:=$(call AutoProbe,gpio-f7188x)\nendef\n\ndefine KernelPackage/gpio-f7188x/description\n  Kernel module for the GPIOs found on many Fintek Super-IO chips.\nendef\n\n$(eval $(call KernelPackage,gpio-f7188x))\n\n\ndefine KernelPackage/gpio-mcp23s08\n  SUBMENU:=$(OTHER_MENU)\n  TITLE:=Microchip MCP23xxx I/O expander\n  DEPENDS:=@GPIO_SUPPORT +kmod-i2c-core +kmod-regmap-i2c\n  KCONFIG:= \\\n\tCONFIG_GPIO_MCP23S08 \\\n\tCONFIG_PINCTRL_MCP23S08\n  FILES:= \\\n\t$(LINUX_DIR)/drivers/pinctrl/pinctrl-mcp23s08.ko\n  AUTOLOAD:=$(call AutoLoad,40,pinctrl-mcp23s08)\nendef\n\ndefine KernelPackage/gpio-mcp23s08/description\n Kernel module for Microchip MCP23xxx SPI/I2C I/O expander\nendef\n\n$(eval $(call KernelPackage,gpio-mcp23s08))\n\n\ndefine KernelPackage/gpio-nxp-74hc164\n  SUBMENU:=$(OTHER_MENU)\n  TITLE:=NXP 74HC164 GPIO expander support\n  KCONFIG:=CONFIG_GPIO_74X164\n  FILES:=$(LINUX_DIR)/drivers/gpio/gpio-74x164.ko\n  AUTOLOAD:=$(call AutoProbe,gpio-74x164)\nendef\n\ndefine KernelPackage/gpio-nxp-74hc164/description\n Kernel module for NXP 74HC164 GPIO expander\nendef\n\n$(eval $(call KernelPackage,gpio-nxp-74hc164))\n\ndefine KernelPackage/gpio-pca953x\n  SUBMENU:=$(OTHER_MENU)\n  DEPENDS:=@GPIO_SUPPORT +kmod-i2c-core +kmod-regmap-i2c\n  TITLE:=PCA95xx, TCA64xx, and MAX7310 I/O ports\n  KCONFIG:=CONFIG_GPIO_PCA953X\n  FILES:=$(LINUX_DIR)/drivers/gpio/gpio-pca953x.ko\n  AUTOLOAD:=$(call AutoLoad,55,gpio-pca953x)\nendef\n\ndefine KernelPackage/gpio-pca953x/description\n Kernel module for MAX731{0,2,3,5}, PCA6107, PCA953{4-9}, PCA955{4-7},\n PCA957{4,5} and TCA64{08,16} I2C GPIO expanders\nendef\n\n$(eval $(call KernelPackage,gpio-pca953x))\n\ndefine KernelPackage/gpio-pcf857x\n  SUBMENU:=$(OTHER_MENU)\n  DEPENDS:=@GPIO_SUPPORT +kmod-i2c-core\n  TITLE:=PCX857x, PCA967x and MAX732X I2C GPIO expanders\n  KCONFIG:=CONFIG_GPIO_PCF857X\n  FILES:=$(LINUX_DIR)/drivers/gpio/gpio-pcf857x.ko\n  AUTOLOAD:=$(call AutoLoad,55,gpio-pcf857x)\nendef\n\ndefine KernelPackage/gpio-pcf857x/description\n Kernel module for PCF857x, PCA{85,96}7x, and MAX732[89] I2C GPIO expanders\nendef\n\n$(eval $(call KernelPackage,gpio-pcf857x))\n\n\ndefine KernelPackage/gpio-it87\n  SUBMENU:=$(OTHER_MENU)\n  DEPENDS:=@GPIO_SUPPORT @TARGET_x86\n  TITLE:=GPIO support for IT87xx Super I/O chips\n  KCONFIG:=CONFIG_GPIO_IT87\n  FILES:=$(LINUX_DIR)/drivers/gpio/gpio-it87.ko\n  AUTOLOAD:=$(call AutoLoad,25,gpio-it87,1)\nendef\n\ndefine KernelPackage/gpio-it87/description\n  This driver is tested with ITE IT8728 and IT8732 Super I/O chips, and\n  supports the IT8761E, IT8613, IT8620E, and IT8628E Super I/O chips as\n  well.\nendef\n\n$(eval $(call KernelPackage,gpio-it87))\n\n\ndefine KernelPackage/gpio-amd-fch\n  SUBMENU:=$(OTHER_MENU)\n  DEPENDS:=@GPIO_SUPPORT @TARGET_x86\n  TITLE:=GPIO support for AMD Fusion Controller Hub (G-series SOCs)\n  KCONFIG:=CONFIG_GPIO_AMD_FCH\n  FILES:=$(LINUX_DIR)/drivers/gpio/gpio-amd-fch.ko\n  AUTOLOAD:=$(call AutoLoad,25,gpio-amd-fch,1)\nendef\n\ndefine KernelPackage/gpio-amd-fch/description\n  This option enables driver for GPIO on AMDs Fusion Controller Hub,\n  as found on G-series SOCs (eg. GX-412TC)\nendef\n\n$(eval $(call KernelPackage,gpio-amd-fch))\n\n\ndefine KernelPackage/ppdev\n  SUBMENU:=$(OTHER_MENU)\n  TITLE:=Parallel port support\n  KCONFIG:= \\\n\tCONFIG_PARPORT \\\n\tCONFIG_PPDEV\n  FILES:= \\\n\t$(LINUX_DIR)/drivers/parport/parport.ko \\\n\t$(LINUX_DIR)/drivers/char/ppdev.ko\n  AUTOLOAD:=$(call AutoLoad,50,parport ppdev)\nendef\n\n$(eval $(call KernelPackage,ppdev))\n\n\ndefine KernelPackage/parport-pc\n  SUBMENU:=$(OTHER_MENU)\n  TITLE:=Parallel port interface (PC-style) support\n  DEPENDS:=+kmod-ppdev\n  KCONFIG:= \\\n\tCONFIG_KS0108=n \\\n\tCONFIG_PARPORT_PC \\\n\tCONFIG_PARPORT_1284=y \\\n\tCONFIG_PARPORT_PC_FIFO=y \\\n\tCONFIG_PARPORT_PC_PCMCIA=n \\\n\tCONFIG_PARPORT_PC_SUPERIO=y \\\n\tCONFIG_PARPORT_SERIAL=n \\\n\tCONFIG_PARIDE=n \\\n\tCONFIG_SCSI_IMM=n \\\n\tCONFIG_SCSI_PPA=n\n  FILES:= \\\n\t$(LINUX_DIR)/drivers/parport/parport_pc.ko\n  AUTOLOAD:=$(call AutoLoad,51,parport_pc)\nendef\n\n$(eval $(call KernelPackage,parport-pc))\n\n\ndefine KernelPackage/lp\n  SUBMENU:=$(OTHER_MENU)\n  TITLE:=Parallel port line printer device support\n  DEPENDS:=+kmod-ppdev\n  KCONFIG:= \\\n\tCONFIG_PRINTER\n  FILES:= \\\n\t$(LINUX_DIR)/drivers/char/lp.ko\n  AUTOLOAD:=$(call AutoLoad,52,lp)\nendef\n\n$(eval $(call KernelPackage,lp))\n\n\ndefine KernelPackage/mmc\n  SUBMENU:=$(OTHER_MENU)\n  TITLE:=MMC/SD Card Support\n  DEPENDS:=@!TARGET_uml\n  KCONFIG:= \\\n\tCONFIG_MMC \\\n\tCONFIG_MMC_BLOCK \\\n\tCONFIG_MMC_DEBUG=n \\\n\tCONFIG_MMC_UNSAFE_RESUME=n \\\n\tCONFIG_MMC_BLOCK_BOUNCE=y \\\n\tCONFIG_MMC_TIFM_SD=n \\\n\tCONFIG_MMC_WBSD=n \\\n\tCONFIG_SDIO_UART=n\n  FILES:= \\\n\t$(LINUX_DIR)/drivers/mmc/core/mmc_core.ko \\\n\t$(LINUX_DIR)/drivers/mmc/core/mmc_block.ko\n  AUTOLOAD:=$(call AutoProbe,mmc_core mmc_block,1)\nendef\n\ndefine KernelPackage/mmc/description\n Kernel support for MMC/SD cards\nendef\n\n$(eval $(call KernelPackage,mmc))\n\n\ndefine KernelPackage/mvsdio\n  SUBMENU:=$(OTHER_MENU)\n  TITLE:=Marvell MMC/SD/SDIO host driver\n  DEPENDS:=+kmod-mmc @TARGET_kirkwood\n  KCONFIG:= CONFIG_MMC_MVSDIO\n  FILES:= \\\n\t$(LINUX_DIR)/drivers/mmc/host/mvsdio.ko\n  AUTOLOAD:=$(call AutoProbe,mvsdio,1)\nendef\n\ndefine KernelPackage/mvsdio/description\n Kernel support for the Marvell SDIO host driver.\nendef\n\n$(eval $(call KernelPackage,mvsdio))\n\n\ndefine KernelPackage/sdhci\n  SUBMENU:=$(OTHER_MENU)\n  TITLE:=Secure Digital Host Controller Interface support\n  DEPENDS:=+kmod-mmc\n  KCONFIG:= \\\n\tCONFIG_MMC_SDHCI \\\n\tCONFIG_MMC_SDHCI_PLTFM \\\n\tCONFIG_MMC_SDHCI_PCI=n\n  FILES:= \\\n\t$(LINUX_DIR)/drivers/mmc/host/sdhci.ko \\\n\t$(LINUX_DIR)/drivers/mmc/host/sdhci-pltfm.ko\n\n  AUTOLOAD:=$(call AutoProbe,sdhci-pltfm,1)\nendef\n\ndefine KernelPackage/sdhci/description\n Kernel support for SDHCI Hosts\nendef\n\n$(eval $(call KernelPackage,sdhci))\n\n\ndefine KernelPackage/rfkill\n  SUBMENU:=$(OTHER_MENU)\n  TITLE:=RF switch subsystem support\n  DEPENDS:=@USE_RFKILL +kmod-input-core\n  KCONFIG:= \\\n    CONFIG_RFKILL_FULL \\\n    CONFIG_RFKILL_INPUT=y \\\n    CONFIG_RFKILL_LEDS=y\n  FILES:= \\\n    $(LINUX_DIR)/net/rfkill/rfkill.ko\n  AUTOLOAD:=$(call AutoLoad,20,rfkill)\nendef\n\ndefine KernelPackage/rfkill/description\n Say Y here if you want to have control over RF switches\n found on many WiFi and Bluetooth cards\nendef\n\n$(eval $(call KernelPackage,rfkill))\n\n\ndefine KernelPackage/softdog\n  SUBMENU:=$(OTHER_MENU)\n  TITLE:=Software watchdog driver\n  KCONFIG:=CONFIG_SOFT_WATCHDOG \\\n  \tCONFIG_SOFT_WATCHDOG_PRETIMEOUT=n\n  FILES:=$(LINUX_DIR)/drivers/$(WATCHDOG_DIR)/softdog.ko\n  AUTOLOAD:=$(call AutoLoad,50,softdog,1)\nendef\n\ndefine KernelPackage/softdog/description\n Software watchdog driver\nendef\n\n$(eval $(call KernelPackage,softdog))\n\n\ndefine KernelPackage/ssb\n  SUBMENU:=$(OTHER_MENU)\n  TITLE:=Silicon Sonics Backplane glue code\n  DEPENDS:=@PCI_SUPPORT @!TARGET_bcm47xx @!TARGET_bcm63xx\n  KCONFIG:=\\\n\tCONFIG_SSB \\\n\tCONFIG_SSB_B43_PCI_BRIDGE=y \\\n\tCONFIG_SSB_DRIVER_MIPS=n \\\n\tCONFIG_SSB_DRIVER_PCICORE=y \\\n\tCONFIG_SSB_DRIVER_PCICORE_POSSIBLE=y \\\n\tCONFIG_SSB_PCIHOST=y \\\n\tCONFIG_SSB_PCIHOST_POSSIBLE=y \\\n\tCONFIG_SSB_POSSIBLE=y \\\n\tCONFIG_SSB_SPROM=y \\\n\tCONFIG_SSB_SILENT=y\n  FILES:=$(LINUX_DIR)/drivers/ssb/ssb.ko\n  AUTOLOAD:=$(call AutoLoad,18,ssb,1)\nendef\n\ndefine KernelPackage/ssb/description\n Silicon Sonics Backplane glue code.\nendef\n\n$(eval $(call KernelPackage,ssb))\n\n\ndefine KernelPackage/bcma\n  SUBMENU:=$(OTHER_MENU)\n  TITLE:=BCMA support\n  DEPENDS:=@PCI_SUPPORT @!TARGET_bcm47xx @!TARGET_bcm53xx\n  KCONFIG:=\\\n\tCONFIG_BCMA \\\n\tCONFIG_BCMA_POSSIBLE=y \\\n\tCONFIG_BCMA_BLOCKIO=y \\\n\tCONFIG_BCMA_HOST_PCI_POSSIBLE=y \\\n\tCONFIG_BCMA_HOST_PCI=y \\\n\tCONFIG_BCMA_HOST_SOC=n \\\n\tCONFIG_BCMA_DRIVER_MIPS=n \\\n\tCONFIG_BCMA_DRIVER_PCI_HOSTMODE=n \\\n\tCONFIG_BCMA_DRIVER_GMAC_CMN=n \\\n\tCONFIG_BCMA_DEBUG=n\n  FILES:=$(LINUX_DIR)/drivers/bcma/bcma.ko\n  AUTOLOAD:=$(call AutoLoad,29,bcma)\nendef\n\ndefine KernelPackage/bcma/description\n Bus driver for Broadcom specific Advanced Microcontroller Bus Architecture\nendef\n\n$(eval $(call KernelPackage,bcma))\n\n\ndefine KernelPackage/rtc-ds1307\n  SUBMENU:=$(OTHER_MENU)\n  TITLE:=Dallas/Maxim DS1307 (and compatible) RTC support\n  DEFAULT:=m if ALL_KMODS && RTC_SUPPORT\n  DEPENDS:=+kmod-i2c-core +kmod-regmap-i2c +kmod-hwmon-core\n  KCONFIG:=CONFIG_RTC_DRV_DS1307 \\\n\tCONFIG_RTC_CLASS=y\n  FILES:=$(LINUX_DIR)/drivers/rtc/rtc-ds1307.ko\n  AUTOLOAD:=$(call AutoProbe,rtc-ds1307)\nendef\n\ndefine KernelPackage/rtc-ds1307/description\n Kernel module for Dallas/Maxim DS1307/DS1337/DS1338/DS1340/DS1388/DS3231,\n Epson RX-8025 and various other compatible RTC chips connected via I2C.\nendef\n\n$(eval $(call KernelPackage,rtc-ds1307))\n\n\ndefine KernelPackage/rtc-ds1374\n  SUBMENU:=$(OTHER_MENU)\n  TITLE:=Dallas/Maxim DS1374 RTC support\n  DEFAULT:=m if ALL_KMODS && RTC_SUPPORT\n  DEPENDS:=+kmod-i2c-core\n  KCONFIG:=CONFIG_RTC_DRV_DS1374 \\\n\tCONFIG_RTC_DRV_DS1374_WDT=n \\\n\tCONFIG_RTC_CLASS=y\n  FILES:=$(LINUX_DIR)/drivers/rtc/rtc-ds1374.ko\n  AUTOLOAD:=$(call AutoProbe,rtc-ds1374)\nendef\n\ndefine KernelPackage/rtc-ds1374/description\n Kernel module for Dallas/Maxim DS1374.\nendef\n\n$(eval $(call KernelPackage,rtc-ds1374))\n\n\ndefine KernelPackage/rtc-ds1672\n  SUBMENU:=$(OTHER_MENU)\n  TITLE:=Dallas/Maxim DS1672 RTC support\n  DEFAULT:=m if ALL_KMODS && RTC_SUPPORT\n  DEPENDS:=+kmod-i2c-core\n  KCONFIG:=CONFIG_RTC_DRV_DS1672 \\\n\tCONFIG_RTC_CLASS=y\n  FILES:=$(LINUX_DIR)/drivers/rtc/rtc-ds1672.ko\n  AUTOLOAD:=$(call AutoProbe,rtc-ds1672)\nendef\n\ndefine KernelPackage/rtc-ds1672/description\n Kernel module for Dallas/Maxim DS1672 RTC.\nendef\n\n$(eval $(call KernelPackage,rtc-ds1672))\n\n\ndefine KernelPackage/rtc-em3027\n  SUBMENU:=$(OTHER_MENU)\n  TITLE:=Microelectronic EM3027 RTC support\n  DEFAULT:=m if ALL_KMODS && RTC_SUPPORT\n  DEPENDS:=+kmod-i2c-core\n  KCONFIG:=CONFIG_RTC_DRV_EM3027 \\\n\tCONFIG_RTC_CLASS=y\n  FILES:=$(LINUX_DIR)/drivers/rtc/rtc-em3027.ko\n  AUTOLOAD:=$(call AutoProbe,rtc-em3027)\nendef\n\ndefine KernelPackage/rtc-em3027/description\n Kernel module for Microelectronic EM3027 RTC.\nendef\n\n$(eval $(call KernelPackage,rtc-em3027))\n\n\ndefine KernelPackage/rtc-isl1208\n  SUBMENU:=$(OTHER_MENU)\n  TITLE:=Intersil ISL1208 RTC support\n  DEFAULT:=m if ALL_KMODS && RTC_SUPPORT\n  DEPENDS:=+kmod-i2c-core\n  KCONFIG:=CONFIG_RTC_DRV_ISL1208 \\\n\tCONFIG_RTC_CLASS=y\n  FILES:=$(LINUX_DIR)/drivers/rtc/rtc-isl1208.ko\n  AUTOLOAD:=$(call AutoProbe,rtc-isl1208)\nendef\n\ndefine KernelPackage/rtc-isl1208/description\n Kernel module for Intersil ISL1208 RTC.\nendef\n\n$(eval $(call KernelPackage,rtc-isl1208))\n\n\ndefine KernelPackage/rtc-pcf8563\n  SUBMENU:=$(OTHER_MENU)\n  TITLE:=Philips PCF8563/Epson RTC8564 RTC support\n  DEFAULT:=m if ALL_KMODS && RTC_SUPPORT\n  DEPENDS:=+kmod-i2c-core\n  KCONFIG:=CONFIG_RTC_DRV_PCF8563 \\\n\tCONFIG_RTC_CLASS=y\n  FILES:=$(LINUX_DIR)/drivers/rtc/rtc-pcf8563.ko\n  AUTOLOAD:=$(call AutoProbe,rtc-pcf8563)\nendef\n\ndefine KernelPackage/rtc-pcf8563/description\n Kernel module for Philips PCF8563 RTC chip.\n The Epson RTC8564 should work as well.\nendef\n\n$(eval $(call KernelPackage,rtc-pcf8563))\n\n\ndefine KernelPackage/rtc-pcf2123\n  SUBMENU:=$(OTHER_MENU)\n  TITLE:=Philips PCF2123 RTC support\n  DEFAULT:=m if ALL_KMODS && RTC_SUPPORT\n  DEPENDS:=+kmod-regmap-spi\n  KCONFIG:=CONFIG_RTC_DRV_PCF2123 \\\n\tCONFIG_RTC_CLASS=y\n  FILES:=$(LINUX_DIR)/drivers/rtc/rtc-pcf2123.ko\n  AUTOLOAD:=$(call AutoProbe,rtc-pcf2123)\nendef\n\ndefine KernelPackage/rtc-pcf2123/description\n Kernel module for Philips PCF2123 RTC chip\nendef\n\n$(eval $(call KernelPackage,rtc-pcf2123))\n\ndefine KernelPackage/rtc-pcf2127\n  SUBMENU:=$(OTHER_MENU)\n  TITLE:=NXP PCF2127 and PCF2129 RTC support\n  DEFAULT:=m if ALL_KMODS && RTC_SUPPORT\n  DEPENDS:=+kmod-i2c-core +kmod-regmap-spi\n  KCONFIG:=CONFIG_RTC_DRV_PCF2127 \\\n\tCONFIG_RTC_CLASS=y\n  FILES:=$(LINUX_DIR)/drivers/rtc/rtc-pcf2127.ko\n  AUTOLOAD:=$(call AutoProbe,rtc-pcf2127)\nendef\n\ndefine KernelPackage/rtc-pcf2127/description\n Kernel module for NXP PCF2127 and PCF2129 RTC chip\nendef\n\n$(eval $(call KernelPackage,rtc-pcf2127))\n\ndefine KernelPackage/rtc-pt7c4338\n  SUBMENU:=$(OTHER_MENU)\n  TITLE:=Pericom PT7C4338 RTC support\n  DEFAULT:=m if ALL_KMODS && RTC_SUPPORT\n  DEPENDS:=+kmod-i2c-core\n  KCONFIG:=CONFIG_RTC_DRV_PT7C4338 \\\n\tCONFIG_RTC_CLASS=y\n  FILES:=$(LINUX_DIR)/drivers/rtc/rtc-pt7c4338.ko\n  AUTOLOAD:=$(call AutoProbe,rtc-pt7c4338)\nendef\n\ndefine KernelPackage/rtc-pt7c4338/description\n Kernel module for Pericom PT7C4338 i2c RTC chip\nendef\n\n$(eval $(call KernelPackage,rtc-pt7c4338))\n\ndefine KernelPackage/rtc-rs5c372a\n  SUBMENU:=$(OTHER_MENU)\n  TITLE:=Ricoh R2025S/D, RS5C372A/B, RV5C386, RV5C387A\n  DEFAULT:=m if ALL_KMODS && RTC_SUPPORT\n  DEPENDS:=+kmod-i2c-core\n  KCONFIG:=CONFIG_RTC_DRV_RS5C372 \\\n\tCONFIG_RTC_CLASS=y\n  FILES:=$(LINUX_DIR)/drivers/rtc/rtc-rs5c372.ko\n  AUTOLOAD:=$(call AutoLoad,50,rtc-rs5c372,1)\nendef\n\ndefine KernelPackage/rtc-rs5c372a/description\n Kernel module for Ricoh R2025S/D, RS5C372A/B, RV5C386, RV5C387A RTC on chip module\nendef\n\n$(eval $(call KernelPackage,rtc-rs5c372a))\n\ndefine KernelPackage/rtc-rx8025\n  SUBMENU:=$(OTHER_MENU)\n  TITLE:=Epson RX-8025 / RX-8035\n  DEFAULT:=m if ALL_KMODS && RTC_SUPPORT\n  DEPENDS:=+kmod-i2c-core\n  KCONFIG:=CONFIG_RTC_DRV_RX8025 \\\n\tCONFIG_RTC_CLASS=y\n  FILES:=$(LINUX_DIR)/drivers/rtc/rtc-rx8025.ko\n  AUTOLOAD:=$(call AutoLoad,50,rtc-rx8025,1)\nendef\n\ndefine KernelPackage/rtc-rx8025/description\n Kernel module for Epson RX-8025 and RX-8035 I2C RTC chip\nendef\n\n$(eval $(call KernelPackage,rtc-rx8025))\n\ndefine KernelPackage/rtc-s35390a\n  SUBMENU:=$(OTHER_MENU)\n  TITLE:=Seico S-35390A\n  DEFAULT:=m if ALL_KMODS && RTC_SUPPORT\n  DEPENDS:=+kmod-i2c-core\n  KCONFIG:=CONFIG_RTC_DRV_S35390A \\\n\tCONFIG_RTC_CLASS=y\n  FILES:=$(LINUX_DIR)/drivers/rtc/rtc-s35390a.ko\n  AUTOLOAD:=$(call AutoLoad,50,rtc-s35390a,1)\nendef\n\ndefine KernelPackage/rtc-s35390a/description\n Kernel module for Seiko Instruments S-35390A I2C RTC chip\nendef\n\n$(eval $(call KernelPackage,rtc-s35390a))\n\n\ndefine KernelPackage/mtdtests\n  SUBMENU:=$(OTHER_MENU)\n  TITLE:=MTD subsystem tests\n  KCONFIG:=CONFIG_MTD_TESTS\n  FILES:=\\\n\t$(LINUX_DIR)/drivers/mtd/tests/mtd_nandecctest.ko \\\n\t$(LINUX_DIR)/drivers/mtd/tests/mtd_oobtest.ko \\\n\t$(LINUX_DIR)/drivers/mtd/tests/mtd_pagetest.ko \\\n\t$(LINUX_DIR)/drivers/mtd/tests/mtd_readtest.ko \\\n\t$(LINUX_DIR)/drivers/mtd/tests/mtd_speedtest.ko \\\n\t$(LINUX_DIR)/drivers/mtd/tests/mtd_stresstest.ko \\\n\t$(LINUX_DIR)/drivers/mtd/tests/mtd_subpagetest.ko \\\n\t$(LINUX_DIR)/drivers/mtd/tests/mtd_torturetest.ko\nendef\n\ndefine KernelPackage/mtdtests/description\n Kernel modules for MTD subsystem/driver testing\nendef\n\n$(eval $(call KernelPackage,mtdtests))\n\n\ndefine KernelPackage/mtdoops\n  SUBMENU:=$(OTHER_MENU)\n  TITLE:=Log panic/oops to an MTD buffer\n  KCONFIG:=CONFIG_MTD_OOPS\n  FILES:=$(LINUX_DIR)/drivers/mtd/mtdoops.ko\nendef\n\ndefine KernelPackage/mtdoops/description\n Kernel modules for Log panic/oops to an MTD buffer\nendef\n\n$(eval $(call KernelPackage,mtdoops))\n\n\ndefine KernelPackage/mtdram\n  SUBMENU:=$(OTHER_MENU)\n  TITLE:=Test MTD driver using RAM\n  KCONFIG:=CONFIG_MTD_MTDRAM \\\n    CONFIG_MTDRAM_TOTAL_SIZE=4096 \\\n    CONFIG_MTDRAM_ERASE_SIZE=128\n  FILES:=$(LINUX_DIR)/drivers/mtd/devices/mtdram.ko\nendef\n\ndefine KernelPackage/mtdram/description\n  Test MTD driver using RAM\nendef\n\n$(eval $(call KernelPackage,mtdram))\n\n\ndefine KernelPackage/ramoops\n  SUBMENU:=$(OTHER_MENU)\n  TITLE:=Ramoops (pstore-ram)\n  DEFAULT:=m if ALL_KMODS\n  KCONFIG:=CONFIG_PSTORE_RAM\n  DEPENDS:=+kmod-pstore +kmod-reed-solomon\n  FILES:= $(LINUX_DIR)/fs/pstore/ramoops.ko\n  AUTOLOAD:=$(call AutoLoad,30,ramoops,1)\nendef\n\ndefine KernelPackage/ramoops/description\n Kernel module for pstore-ram (ramoops) crash log storage\nendef\n\n$(eval $(call KernelPackage,ramoops))\n\n\ndefine KernelPackage/reed-solomon\n  SUBMENU:=$(OTHER_MENU)\n  TITLE:=Reed-Solomon error correction\n  DEFAULT:=m if ALL_KMODS\n  KCONFIG:=CONFIG_REED_SOLOMON \\\n\tCONFIG_REED_SOLOMON_DEC8=y \\\n\tCONFIG_REED_SOLOMON_ENC8=y\n  FILES:= $(LINUX_DIR)/lib/reed_solomon/reed_solomon.ko\n  AUTOLOAD:=$(call AutoLoad,30,reed_solomon,1)\nendef\n\ndefine KernelPackage/reed-solomon/description\n Kernel module for Reed-Solomon error correction\nendef\n\n$(eval $(call KernelPackage,reed-solomon))\n\n\ndefine KernelPackage/serial-8250\n  SUBMENU:=$(OTHER_MENU)\n  TITLE:=8250 UARTs\n  KCONFIG:= CONFIG_SERIAL_8250 \\\n\tCONFIG_SERIAL_8250_PCI \\\n\tCONFIG_SERIAL_8250_NR_UARTS=16 \\\n\tCONFIG_SERIAL_8250_RUNTIME_UARTS=16 \\\n\tCONFIG_SERIAL_8250_EXTENDED=y \\\n\tCONFIG_SERIAL_8250_MANY_PORTS=y \\\n\tCONFIG_SERIAL_8250_SHARE_IRQ=y \\\n\tCONFIG_SERIAL_8250_DETECT_IRQ=n \\\n\tCONFIG_SERIAL_8250_RSA=n\n  FILES:= \\\n\t$(LINUX_DIR)/drivers/tty/serial/8250/8250.ko \\\n\t$(LINUX_DIR)/drivers/tty/serial/8250/8250_base.ko \\\n\t$(if $(CONFIG_PCI),$(LINUX_DIR)/drivers/tty/serial/8250/8250_pci.ko) \\\n\t$(if $(CONFIG_GPIOLIB),$(LINUX_DIR)/drivers/tty/serial/serial_mctrl_gpio.ko)\n  AUTOLOAD:=$(call AutoProbe,8250 8250_base 8250_pci)\nendef\n\ndefine KernelPackage/serial-8250/description\n Kernel module for 8250 UART based serial ports\nendef\n\n$(eval $(call KernelPackage,serial-8250))\n\n\ndefine KernelPackage/serial-8250-exar\n  SUBMENU:=$(OTHER_MENU)\n  TITLE:=Exar 8250 UARTs\n  KCONFIG:= CONFIG_SERIAL_8250_EXAR\n  FILES:=$(LINUX_DIR)/drivers/tty/serial/8250/8250_exar.ko\n  AUTOLOAD:=$(call AutoProbe,8250 8250_base 8250_exar)\n  DEPENDS:=+kmod-serial-8250\nendef\n\ndefine KernelPackage/serial-8250-exar/description\n Kernel module for Exar serial ports\nendef\n\n$(eval $(call KernelPackage,serial-8250-exar))\n\n\ndefine KernelPackage/regmap-core\n  SUBMENU:=$(OTHER_MENU)\n  TITLE:=Generic register map support\n  HIDDEN:=1\n  KCONFIG:=CONFIG_REGMAP\nifneq ($(wildcard $(LINUX_DIR)/drivers/base/regmap/regmap-core.ko),)\n  FILES:=$(LINUX_DIR)/drivers/base/regmap/regmap-core.ko\nendif\nendef\n\ndefine KernelPackage/regmap-core/description\n Generic register map support\nendef\n\n$(eval $(call KernelPackage,regmap-core))\n\n\ndefine KernelPackage/regmap-spi\n  SUBMENU:=$(OTHER_MENU)\n  TITLE:=SPI register map support\n  DEPENDS:=+kmod-regmap-core\n  HIDDEN:=1\n  KCONFIG:=CONFIG_REGMAP_SPI \\\n\t   CONFIG_SPI=y\n  FILES:=$(LINUX_DIR)/drivers/base/regmap/regmap-spi.ko\nendef\n\ndefine KernelPackage/regmap-spi/description\n SPI register map support\nendef\n\n$(eval $(call KernelPackage,regmap-spi))\n\n\ndefine KernelPackage/regmap-i2c\n  SUBMENU:=$(OTHER_MENU)\n  TITLE:=I2C register map support\n  DEPENDS:=+kmod-regmap-core +kmod-i2c-core\n  HIDDEN:=1\n  KCONFIG:=CONFIG_REGMAP_I2C\n  FILES:=$(LINUX_DIR)/drivers/base/regmap/regmap-i2c.ko\nendef\n\ndefine KernelPackage/regmap-i2c/description\n I2C register map support\nendef\n\n$(eval $(call KernelPackage,regmap-i2c))\n\n\ndefine KernelPackage/regmap-mmio\n  SUBMENU:=$(OTHER_MENU)\n  TITLE:=MMIO register map support\n  DEPENDS:=+kmod-regmap-core\n  HIDDEN:=1\n  KCONFIG:=CONFIG_REGMAP_MMIO\n  FILES:=$(LINUX_DIR)/drivers/base/regmap/regmap-mmio.ko\nendef\n\ndefine KernelPackage/regmap-mmio/description\n MMIO register map support\nendef\n\n$(eval $(call KernelPackage,regmap-mmio))\n\n\ndefine KernelPackage/ikconfig\n  SUBMENU:=$(OTHER_MENU)\n  TITLE:=Kernel configuration via /proc/config.gz\n  KCONFIG:=CONFIG_IKCONFIG \\\n\t   CONFIG_IKCONFIG_PROC=y\n  FILES:=$(LINUX_DIR)/kernel/configs.ko\n  AUTOLOAD:=$(call AutoLoad,70,configs)\nendef\n\ndefine KernelPackage/ikconfig/description\n Kernel configuration via /proc/config.gz\nendef\n\n$(eval $(call KernelPackage,ikconfig))\n\n\ndefine KernelPackage/zram\n  SUBMENU:=$(OTHER_MENU)\n  TITLE:=ZRAM\n  KCONFIG:= \\\n\tCONFIG_ZSMALLOC \\\n\tCONFIG_ZRAM \\\n\tCONFIG_ZRAM_DEBUG=n \\\n\tCONFIG_ZRAM_WRITEBACK=n \\\n\tCONFIG_ZSMALLOC_STAT=n\n  FILES:= \\\n\t$(LINUX_DIR)/mm/zsmalloc.ko \\\n\t$(LINUX_DIR)/drivers/block/zram/zram.ko\n  AUTOLOAD:=$(call AutoLoad,20,zsmalloc zram)\nendef\n\ndefine KernelPackage/zram/description\n Compressed RAM block device support\nendef\n\ndefine KernelPackage/zram/config\n  choice\n    prompt \"ZRAM Default compressor\"\n    default ZRAM_DEF_COMP_LZORLE\n\n  config ZRAM_DEF_COMP_LZORLE\n            bool \"lzo-rle\"\n            select PACKAGE_kmod-lib-lzo\n\n  config ZRAM_DEF_COMP_LZO\n            bool \"lzo\"\n            select PACKAGE_kmod-lib-lzo\n\n  config ZRAM_DEF_COMP_LZ4\n            bool \"lz4\"\n            select PACKAGE_kmod-lib-lz4\n\n  config ZRAM_DEF_COMP_ZSTD\n            bool \"zstd\"\n            select PACKAGE_kmod-lib-zstd\n\n  endchoice\nendef\n\n$(eval $(call KernelPackage,zram))\n\ndefine KernelPackage/pps\n  SUBMENU:=$(OTHER_MENU)\n  TITLE:=PPS support\n  KCONFIG:=CONFIG_PPS\n  FILES:=$(LINUX_DIR)/drivers/pps/pps_core.ko\n  AUTOLOAD:=$(call AutoLoad,17,pps_core,1)\nendef\n\ndefine KernelPackage/pps/description\n PPS (Pulse Per Second) is a special pulse provided by some GPS\n antennae. Userland can use it to get a high-precision time\n reference.\nendef\n\n$(eval $(call KernelPackage,pps))\n\n\ndefine KernelPackage/pps-gpio\n  SUBMENU:=$(OTHER_MENU)\n  TITLE:=PPS client using GPIO\n  DEPENDS:=+kmod-pps\n  KCONFIG:=CONFIG_PPS_CLIENT_GPIO\n  FILES:=$(LINUX_DIR)/drivers/pps/clients/pps-gpio.ko\n  AUTOLOAD:=$(call AutoLoad,18,pps-gpio,1)\nendef\n\ndefine KernelPackage/pps-gpio/description\n Support for a PPS source using GPIO. To be useful you must\n also register a platform device specifying the GPIO pin and\n other options, usually in your board setup.\nendef\n\n$(eval $(call KernelPackage,pps-gpio))\n\n\ndefine KernelPackage/pps-ldisc\n  SUBMENU:=$(OTHER_MENU)\n  TITLE:=PPS line discipline\n  DEPENDS:=+kmod-pps\n  KCONFIG:=CONFIG_PPS_CLIENT_LDISC\n  FILES:=$(LINUX_DIR)/drivers/pps/clients/pps-ldisc.ko\n  AUTOLOAD:=$(call AutoLoad,18,pps-ldisc,1)\nendef\n\ndefine KernelPackage/pps-ldisc/description\n Support for a PPS source connected with the CD (Carrier\n Detect) pin of your serial port.\nendef\n\n$(eval $(call KernelPackage,pps-ldisc))\n\n\ndefine KernelPackage/ptp\n  SUBMENU:=$(OTHER_MENU)\n  TITLE:=PTP clock support\n  DEPENDS:=+kmod-pps\n  KCONFIG:= \\\n\tCONFIG_PTP_1588_CLOCK \\\n\tCONFIG_NET_PTP_CLASSIFY=y\n  FILES:=$(LINUX_DIR)/drivers/ptp/ptp.ko\n  AUTOLOAD:=$(call AutoLoad,18,ptp,1)\nendef\n\ndefine KernelPackage/ptp/description\n The IEEE 1588 standard defines a method to precisely\n synchronize distributed clocks over Ethernet networks.\nendef\n\n$(eval $(call KernelPackage,ptp))\n\n\ndefine KernelPackage/ptp-qoriq\n  SUBMENU:=$(OTHER_MENU)\n  TITLE:=Freescale QorIQ PTP support\n  DEPENDS:=@(TARGET_mpc85xx||TARGET_qoriq) +kmod-ptp\n  KCONFIG:=CONFIG_PTP_1588_CLOCK_QORIQ\n  FILES:=$(LINUX_DIR)/drivers/ptp/ptp-qoriq.ko\n  AUTOLOAD:=$(call AutoProbe,ptp-qoriq)\nendef\n\n\ndefine KernelPackage/ptp-qoriq/description\n Kernel module for IEEE 1588 support for Freescale\n QorIQ Ethernet drivers\nendef\n\n$(eval $(call KernelPackage,ptp-qoriq))\n\ndefine KernelPackage/random-core\n  SUBMENU:=$(OTHER_MENU)\n  TITLE:=Hardware Random Number Generator Core support\n  KCONFIG:=CONFIG_HW_RANDOM\n  FILES:=$(LINUX_DIR)/drivers/char/hw_random/rng-core.ko\nendef\n\ndefine KernelPackage/random-core/description\n Kernel module for the HW random number generator core infrastructure\nendef\n\n$(eval $(call KernelPackage,random-core))\n\n\ndefine KernelPackage/thermal\n  SUBMENU:=$(OTHER_MENU)\n  TITLE:=Thermal driver\n  DEPENDS:=+kmod-hwmon-core\n  HIDDEN:=1\n  KCONFIG:= \\\n\tCONFIG_THERMAL=y \\\n\tCONFIG_THERMAL_OF=y \\\n\tCONFIG_CPU_THERMAL=y \\\n\tCONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y \\\n\tCONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE=n \\\n\tCONFIG_THERMAL_DEFAULT_GOV_USER_SPACE=n \\\n\tCONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 \\\n\tCONFIG_THERMAL_GOV_FAIR_SHARE=n \\\n\tCONFIG_THERMAL_GOV_STEP_WISE=y \\\n\tCONFIG_THERMAL_GOV_USER_SPACE=n \\\n\tCONFIG_THERMAL_HWMON=y \\\n\tCONFIG_THERMAL_EMULATION=n\nendef\n\ndefine KernelPackage/thermal/description\n Thermal driver offers a generic mechanism for thermal management.\n Usually it's made up of one or more thermal zone and cooling device.\nendef\n\n$(eval $(call KernelPackage,thermal))\n\n\ndefine KernelPackage/gpio-beeper\n  SUBMENU:=$(OTHER_MENU)\n  TITLE:=GPIO beeper support\n  DEPENDS:=+kmod-input-core\n  KCONFIG:= \\\n\tCONFIG_INPUT_MISC=y \\\n\tCONFIG_INPUT_GPIO_BEEPER\n  FILES:= \\\n\t$(LINUX_DIR)/drivers/input/misc/gpio-beeper.ko\n  AUTOLOAD:=$(call AutoLoad,50,gpio-beeper)\nendef\n\ndefine KernelPackage/gpio-beeper/description\n This enables playing beeps through an GPIO-connected buzzer\nendef\n\n$(eval $(call KernelPackage,gpio-beeper))\n\n\ndefine KernelPackage/echo\n  SUBMENU:=$(OTHER_MENU)\n  TITLE:=Line Echo Canceller\n  KCONFIG:=CONFIG_ECHO\n  FILES:=$(LINUX_DIR)/drivers/misc/echo/echo.ko\n  AUTOLOAD:=$(call AutoLoad,50,echo)\nendef\n\ndefine KernelPackage/echo/description\n This driver provides line echo cancelling support for mISDN and\n DAHDI drivers\nendef\n\n$(eval $(call KernelPackage,echo))\n\n\ndefine KernelPackage/keys-encrypted\n  SUBMENU:=$(OTHER_MENU)\n  TITLE:=encrypted keys on kernel keyring\n  DEPENDS:=@KERNEL_KEYS +kmod-crypto-cbc +kmod-crypto-hmac +kmod-crypto-rng \\\n           +kmod-crypto-sha256 +kmod-keys-trusted\n  KCONFIG:=CONFIG_ENCRYPTED_KEYS\n  FILES:=$(LINUX_DIR)/security/keys/encrypted-keys/encrypted-keys.ko\n  AUTOLOAD:=$(call AutoLoad,01,encrypted-keys,1)\nendef\n\ndefine KernelPackage/keys-encrypted/description\n\tThis module provides support for create/encrypting/decrypting keys\n\tin the kernel.  Encrypted keys are kernel generated random numbers,\n\twhich are encrypted/decrypted with a 'master' symmetric key. The\n\t'master' key can be either a trusted-key or user-key type.\n\tUserspace only ever sees/stores encrypted blobs.\nendef\n\n$(eval $(call KernelPackage,keys-encrypted))\n\n\ndefine KernelPackage/keys-trusted\n  SUBMENU:=$(OTHER_MENU)\n  TITLE:=TPM trusted keys on kernel keyring\n  DEPENDS:=@KERNEL_KEYS +kmod-crypto-hash +kmod-crypto-hmac +kmod-crypto-sha1 +kmod-tpm\n  KCONFIG:=CONFIG_TRUSTED_KEYS\n  FILES:= \\\n\t  $(LINUX_DIR)/security/keys/trusted.ko@lt5.10 \\\n\t  $(LINUX_DIR)/security/keys/trusted-keys/trusted.ko@ge5.10\n  AUTOLOAD:=$(call AutoLoad,01,trusted-keys,1)\nendef\n\ndefine KernelPackage/keys-trusted/description\n\tThis module provides support for creating, sealing, and unsealing\n\tkeys in the kernel. Trusted keys are random number symmetric keys,\n\tgenerated and RSA-sealed by the TPM. The TPM only unseals the keys,\n\tif the boot PCRs and other criteria match.  Userspace will only ever\n\tsee encrypted blobs.\nendef\n\n$(eval $(call KernelPackage,keys-trusted))\n\n\ndefine KernelPackage/tpm\n  SUBMENU:=$(OTHER_MENU)\n  TITLE:=TPM Hardware Support\n  DEPENDS:= +kmod-random-core +(LINUX_5_15):kmod-asn1-decoder \\\n\t  +(LINUX_5_15):kmod-asn1-encoder +(LINUX_5_15):kmod-oid-registry\n  KCONFIG:= CONFIG_TCG_TPM\n  FILES:= $(LINUX_DIR)/drivers/char/tpm/tpm.ko\n  AUTOLOAD:=$(call AutoLoad,10,tpm,1)\nendef\n\ndefine KernelPackage/tpm/description\n\tThis enables TPM Hardware Support.\nendef\n\n$(eval $(call KernelPackage,tpm))\n\ndefine KernelPackage/tpm-tis\n  SUBMENU:=$(OTHER_MENU)\n  TITLE:=TPM TIS 1.2 Interface / TPM 2.0 FIFO Interface\n\tDEPENDS:= @TARGET_x86 +kmod-tpm\n  KCONFIG:= CONFIG_TCG_TIS\n  FILES:= \\\n\t$(LINUX_DIR)/drivers/char/tpm/tpm_tis.ko \\\n\t$(LINUX_DIR)/drivers/char/tpm/tpm_tis_core.ko\n  AUTOLOAD:=$(call AutoLoad,20,tpm_tis,1)\nendef\n\ndefine KernelPackage/tpm-tis/description\n\tIf you have a TPM security chip that is compliant with the\n\tTCG TIS 1.2 TPM specification (TPM1.2) or the TCG PTP FIFO\n\tspecification (TPM2.0) say Yes and it will be accessible from\n\twithin Linux.\nendef\n\n$(eval $(call KernelPackage,tpm-tis))\n\ndefine KernelPackage/tpm-i2c-atmel\n  SUBMENU:=$(OTHER_MENU)\n  TITLE:=TPM I2C Atmel Support\n  DEPENDS:= +kmod-tpm +kmod-i2c-core\n  KCONFIG:= CONFIG_TCG_TIS_I2C_ATMEL\n  FILES:= $(LINUX_DIR)/drivers/char/tpm/tpm_i2c_atmel.ko\n  AUTOLOAD:=$(call AutoLoad,40,tpm_i2c_atmel,1)\nendef\n\ndefine KernelPackage/tpm-i2c-atmel/description\n\tThis enables the TPM Interface Specification 1.2 Interface (I2C - Atmel)\nendef\n\n$(eval $(call KernelPackage,tpm-i2c-atmel))\n\ndefine KernelPackage/tpm-i2c-infineon\n  SUBMENU:=$(OTHER_MENU)\n  TITLE:= TPM I2C Infineon driver\n  DEPENDS:= +kmod-tpm +kmod-i2c-core\n  KCONFIG:= CONFIG_TCG_TIS_I2C_INFINEON\n  FILES:= $(LINUX_DIR)/drivers/char/tpm/tpm_i2c_infineon.ko\n  AUTOLOAD:= $(call AutoLoad,40,tpm_i2c_infineon,1)\nendef\n\ndefine KernelPackage/tpm-i2c-infineon/description\n\tThis enables the TPM Interface Specification 1.2 Interface (I2C - Infineon)\nendef\n\n$(eval $(call KernelPackage,tpm-i2c-infineon))\n\n\ndefine KernelPackage/i6300esb-wdt\n  SUBMENU:=$(OTHER_MENU)\n  TITLE:=Intel 6300ESB Timer/Watchdog\n  DEPENDS:=@PCI_SUPPORT @!SMALL_FLASH\n  KCONFIG:=CONFIG_I6300ESB_WDT \\\n\t   CONFIG_WATCHDOG_CORE=y\n  FILES:=$(LINUX_DIR)/drivers/$(WATCHDOG_DIR)/i6300esb.ko\n  AUTOLOAD:=$(call AutoLoad,50,i6300esb,1)\nendef\n\ndefine KernelPackage/i6300esb-wdt/description\n  Kernel module for the watchdog timer built into the Intel\n  6300ESB controller hub. Also used by QEMU/libvirt.\nendef\n\n$(eval $(call KernelPackage,i6300esb-wdt))\n\n\ndefine KernelPackage/mhi-bus\n  SUBMENU:=$(OTHER_MENU)\n  TITLE:=MHI bus\n  DEPENDS:=@LINUX_5_15\n  KCONFIG:=CONFIG_MHI_BUS \\\n           CONFIG_MHI_BUS_DEBUG=y\n  FILES:=$(LINUX_DIR)/drivers/bus/mhi/core/mhi.ko\n  AUTOLOAD:=$(call AutoProbe,mhi)\nendef\n\ndefine KernelPackage/mhi-bus/description\n  Kernel module for the Qualcomm MHI bus.\nendef\n\n$(eval $(call KernelPackage,mhi-bus))\n\ndefine KernelPackage/mhi-pci-generic\n  SUBMENU:=$(OTHER_MENU)\n  TITLE:=MHI PCI controller driver\n  DEPENDS:=@LINUX_5_15 +kmod-mhi-bus\n  KCONFIG:=CONFIG_MHI_BUS_PCI_GENERIC\n  FILES:=$(LINUX_DIR)/drivers/bus/mhi/mhi_pci_generic.ko\n  AUTOLOAD:=$(call AutoProbe,mhi_pci_generic)\nendef\n\ndefine KernelPackage/mhi-pci-generic/description\n  Kernel module for the MHI PCI controller driver.\nendef\n\n$(eval $(call KernelPackage,mhi-pci-generic))\n"
  },
  {
    "path": "package/kernel/linux/modules/pcmcia.mk",
    "content": "#\n# Copyright (C) 2006-2010 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\nPCMCIA_MENU:=PCMCIA support\n\ndefine KernelPackage/pcmcia-core\n  SUBMENU:=$(PCMCIA_MENU)\n  TITLE:=PCMCIA/CardBus support\n  DEPENDS:=@PCMCIA_SUPPORT\n  KCONFIG:= \\\n\tCONFIG_PCMCIA \\\n\tCONFIG_PCMCIA_LOAD_CIS=y \\\n\tCONFIG_CARDBUS \\\n\tCONFIG_PCCARD \\\n\tPCMCIA_DEBUG=n\n  FILES:= \\\n\t$(LINUX_DIR)/drivers/pcmcia/pcmcia_core.ko \\\n\t$(LINUX_DIR)/drivers/pcmcia/pcmcia.ko\n  AUTOLOAD:=$(call AutoLoad,25,pcmcia_core pcmcia)\nendef\n\ndefine KernelPackage/pcmcia-core/description\n Kernel support for PCMCIA/CardBus controllers\nendef\n\n$(eval $(call KernelPackage,pcmcia-core))\n\n\ndefine AddDepends/pcmcia\n  SUBMENU:=$(PCMCIA_MENU)\n  DEPENDS+=kmod-pcmcia-core $(1)\nendef\n\n\ndefine KernelPackage/pcmcia-rsrc\n  TITLE:=PCMCIA resource support\n  KCONFIG:=CONFIG_PCCARD_NONSTATIC=y\n  FILES:=$(LINUX_DIR)/drivers/pcmcia/pcmcia_rsrc.ko\n  AUTOLOAD:=$(call AutoLoad,26,pcmcia_rsrc)\n  $(call AddDepends/pcmcia)\nendef\n\ndefine KernelPackage/pcmcia-rsrc/description\n Kernel support for PCMCIA resource allocation\nendef\n\n$(eval $(call KernelPackage,pcmcia-rsrc))\n\n\ndefine KernelPackage/pcmcia-yenta\n  TITLE:=yenta socket driver\n  KCONFIG:=CONFIG_YENTA\n  FILES:=$(LINUX_DIR)/drivers/pcmcia/yenta_socket.ko\n  AUTOLOAD:=$(call AutoLoad,41,yenta_socket)\n  DEPENDS:=+kmod-pcmcia-rsrc\n  $(call AddDepends/pcmcia)\nendef\n\n$(eval $(call KernelPackage,pcmcia-yenta))\n\n\ndefine KernelPackage/pcmcia-serial\n  TITLE:=Serial devices support\n  KCONFIG:= \\\n\tCONFIG_PCMCIA_SERIAL_CS \\\n\tCONFIG_SERIAL_8250_CS\n  FILES:=$(LINUX_DIR)/drivers/tty/serial/8250/serial_cs.ko\n  AUTOLOAD:=$(call AutoLoad,45,serial_cs)\n  DEPENDS:=+kmod-serial-8250\n  $(call AddDepends/pcmcia)\nendef\n\ndefine KernelPackage/pcmcia-serial/description\n Kernel support for PCMCIA/CardBus serial devices\nendef\n\n$(eval $(call KernelPackage,pcmcia-serial))\n\n\ndefine KernelPackage/pcmcia-pd6729\n  TITLE:=Cirrus PD6729 compatible bridge support\n  KCONFIG:=CONFIG_PD6729\n  FILES:=$(LINUX_DIR)/drivers/pcmcia/pd6729.ko\n  AUTOLOAD:=$(call AutoLoad,41,pd6729)\n  DEPENDS:=+kmod-pcmcia-rsrc\n  $(call AddDepends/pcmcia)\nendef\n\ndefine KernelPackage/pcmcia-pd6729/description\n Kernel support for the Cirrus PD6729 PCI-to-PCMCIA bridge\nendef\n\n$(eval $(call KernelPackage,pcmcia-pd6729))\n\n\ndefine KernelPackage/pcmcia-nozomi\n  TITLE:=Option Fusion+ card\n  KCONFIG:=CONFIG_NOZOMI\n  FILES:=$(LINUX_DIR)/drivers/tty/nozomi.ko\n  AUTOLOAD:=$(call AutoLoad,60,nozomi)\n  DEPENDS:=+kmod-pcmcia-rsrc\n  $(call AddDepends/pcmcia)\nendef\n\ndefine KernelPackage/pcmcia-nozomi/description\n Kernel support for Option Fusion+ card\nendef\n\n$(eval $(call KernelPackage,pcmcia-nozomi))\n"
  },
  {
    "path": "package/kernel/linux/modules/sound.mk",
    "content": "#\n# Copyright (C) 2006-2013 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\nSOUND_MENU:=Sound Support\n\n# allow targets to override the soundcore stuff\nSOUNDCORE_LOAD ?= \\\n\tsoundcore \\\n\tsnd \\\n\tsnd-hwdep \\\n\tsnd-seq-device \\\n\tsnd-rawmidi \\\n\tsnd-timer \\\n\tsnd-pcm \\\n\tsnd-mixer-oss \\\n\tsnd-pcm-oss \\\n\tsnd-compress\n\nSOUNDCORE_FILES ?= \\\n\t$(LINUX_DIR)/sound/soundcore.ko \\\n\t$(LINUX_DIR)/sound/core/snd.ko \\\n\t$(LINUX_DIR)/sound/core/snd-hwdep.ko \\\n\t$(LINUX_DIR)/sound/core/snd-seq-device.ko \\\n\t$(LINUX_DIR)/sound/core/snd-rawmidi.ko \\\n\t$(LINUX_DIR)/sound/core/snd-timer.ko \\\n\t$(LINUX_DIR)/sound/core/snd-pcm.ko \\\n\t$(LINUX_DIR)/sound/core/oss/snd-mixer-oss.ko \\\n\t$(LINUX_DIR)/sound/core/oss/snd-pcm-oss.ko \\\n\t$(LINUX_DIR)/sound/core/snd-compress.ko\n\nSOUNDCORE_LOAD += \\\n\t$(if $(CONFIG_SND_DMAENGINE_PCM),snd-pcm-dmaengine)\n\nSOUNDCORE_FILES += \\\n\t$(if $(CONFIG_SND_DMAENGINE_PCM),$(LINUX_DIR)/sound/core/snd-pcm-dmaengine.ko)\n\ndefine KernelPackage/sound-core\n  SUBMENU:=$(SOUND_MENU)\n  TITLE:=Sound support\n  DEPENDS:=@AUDIO_SUPPORT +kmod-input-core\n  KCONFIG:= \\\n\tCONFIG_SOUND \\\n\tCONFIG_SND \\\n\tCONFIG_SND_HWDEP \\\n\tCONFIG_SND_RAWMIDI \\\n\tCONFIG_SND_TIMER \\\n\tCONFIG_SND_PCM \\\n\tCONFIG_SND_PCM_TIMER=y \\\n\tCONFIG_SND_SEQUENCER \\\n\tCONFIG_SND_VIRMIDI \\\n\tCONFIG_SND_SEQ_DUMMY \\\n\tCONFIG_SND_SEQUENCER_OSS=y \\\n\tCONFIG_HOSTAUDIO \\\n\tCONFIG_SND_PCM_OSS \\\n\tCONFIG_SND_MIXER_OSS \\\n\tCONFIG_SOUND_OSS_CORE_PRECLAIM=y \\\n\tCONFIG_SND_COMPRESS_OFFLOAD\n  FILES:=$(SOUNDCORE_FILES)\n  AUTOLOAD:=$(call AutoLoad,30,$(SOUNDCORE_LOAD))\nendef\n\ndefine KernelPackage/sound-core/uml\n  FILES:= \\\n\t$(LINUX_DIR)/sound/soundcore.ko \\\n\t$(LINUX_DIR)/arch/um/drivers/hostaudio.ko\n  AUTOLOAD+=$(call AutoLoad,30,soundcore hostaudio)\nendef\n\ndefine KernelPackage/sound-core/description\n Kernel modules for sound support\nendef\n\n$(eval $(call KernelPackage,sound-core))\n\n\ndefine AddDepends/sound\n  SUBMENU:=$(SOUND_MENU)\n  DEPENDS+=kmod-sound-core $(1) @!TARGET_uml\nendef\n\n\ndefine KernelPackage/ac97\n  TITLE:=ac97 controller\n  KCONFIG:=CONFIG_SND_AC97_CODEC\n  FILES:= \\\n\t$(LINUX_DIR)/sound/ac97_bus.ko \\\n\t$(LINUX_DIR)/sound/pci/ac97/snd-ac97-codec.ko\n  AUTOLOAD:=$(call AutoLoad,35,ac97_bus snd-ac97-codec)\n  $(call AddDepends/sound)\nendef\n\ndefine KernelPackage/ac97/description\n The ac97 controller\nendef\n\n$(eval $(call KernelPackage,ac97))\n\n\ndefine KernelPackage/sound-mpu401\n  TITLE:=MPU-401 uart driver\n  KCONFIG:=CONFIG_SND_MPU401_UART\n  FILES:= \\\n\t$(LINUX_DIR)/sound/drivers/mpu401/snd-mpu401-uart.ko\n  AUTOLOAD:=$(call AutoLoad,35,snd-mpu401-uart)\n  $(call AddDepends/sound)\nendef\n\ndefine KernelPackage/sound-mpu401/description\n support for MIDI ports compatible with the Roland MPU-401\n interface in UART mode.\nendef\n\n$(eval $(call KernelPackage,sound-mpu401))\n\n\ndefine KernelPackage/sound-seq\n  TITLE:=Sequencer support\n  FILES:= \\\n\t$(LINUX_DIR)/sound/core/seq/snd-seq.ko \\\n\t$(LINUX_DIR)/sound/core/seq/snd-seq-midi-event.ko \\\n\t$(LINUX_DIR)/sound/core/seq/snd-seq-midi.ko\n  AUTOLOAD:=$(call AutoLoad,35,snd-seq snd-seq-midi-event snd-seq-midi)\n  $(call AddDepends/sound)\nendef\n\ndefine KernelPackage/sound-seq/description\n Kernel modules for sequencer support\nendef\n\n$(eval $(call KernelPackage,sound-seq))\n\n\ndefine KernelPackage/sound-ens1371\n  TITLE:=(Creative) Ensoniq AudioPCI 1371\n  KCONFIG:=CONFIG_SND_ENS1371\n  DEPENDS:=@PCI_SUPPORT +kmod-ac97\n  FILES:=$(LINUX_DIR)/sound/pci/snd-ens1371.ko\n  AUTOLOAD:=$(call AutoLoad,36,snd-ens1371)\n  $(call AddDepends/sound)\nendef\n\ndefine KernelPackage/sound-ens1371/description\n support for (Creative) Ensoniq AudioPCI 1371 chips\nendef\n\n$(eval $(call KernelPackage,sound-ens1371))\n\n\ndefine KernelPackage/sound-i8x0\n  TITLE:=Intel/SiS/nVidia/AMD/ALi AC97 Controller\n  DEPENDS:=+kmod-ac97\n  KCONFIG:=CONFIG_SND_INTEL8X0\n  FILES:=$(LINUX_DIR)/sound/pci/snd-intel8x0.ko\n  AUTOLOAD:=$(call AutoLoad,36,snd-intel8x0)\n  $(call AddDepends/sound)\nendef\n\ndefine KernelPackage/sound-i8x0/description\n support for the integrated AC97 sound device on motherboards\n with Intel/SiS/nVidia/AMD chipsets, or ALi chipsets using\n the M5455 Audio Controller.\nendef\n\n$(eval $(call KernelPackage,sound-i8x0))\n\n\ndefine KernelPackage/sound-via82xx\n  TITLE:=VIA 82xx AC97 Controller\n  DEPENDS:=+kmod-ac97 +kmod-sound-mpu401\n  KCONFIG:=CONFIG_SND_VIA82XX\n  FILES:=$(LINUX_DIR)/sound/pci/snd-via82xx.ko\n  AUTOLOAD:=$(call AutoLoad,36,snd-via82xx)\n  $(call AddDepends/sound)\nendef\n\ndefine KernelPackage/sound-via82xx/description\n support for the integrated AC97 sound device on motherboards\n with VIA chipsets.\nendef\n\n$(eval $(call KernelPackage,sound-via82xx))\n\n\ndefine KernelPackage/sound-soc-core\n  TITLE:=SoC sound support\n  DEPENDS:=+kmod-regmap-core +kmod-ac97\n  KCONFIG:= \\\n\tCONFIG_SND_SOC \\\n\tCONFIG_SND_SOC_ADI=n \\\n\tCONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y \\\n\tCONFIG_SND_SOC_ALL_CODECS=n\n  FILES:=$(LINUX_DIR)/sound/soc/snd-soc-core.ko\n  AUTOLOAD:=$(call AutoLoad,55,snd-soc-core)\n  $(call AddDepends/sound)\nendef\n\n$(eval $(call KernelPackage,sound-soc-core))\n\n\ndefine KernelPackage/sound-soc-ac97\n  TITLE:=AC97 Codec support\n  KCONFIG:=CONFIG_SND_SOC_AC97_CODEC\n  FILES:=$(LINUX_DIR)/sound/soc/codecs/snd-soc-ac97.ko\n  AUTOLOAD:=$(call AutoLoad,57,snd-soc-ac97)\n  DEPENDS:=+kmod-ac97 +kmod-sound-soc-core\n  $(call AddDepends/sound)\nendef\n\n$(eval $(call KernelPackage,sound-soc-ac97))\n\n\ndefine KernelPackage/sound-soc-imx\n  TITLE:=IMX SoC support\n  KCONFIG:=\\\n\tCONFIG_SND_IMX_SOC \\\n\tCONFIG_SND_SOC_IMX_AUDMUX \\\n\tCONFIG_SND_SOC_FSL_SSI \\\n\tCONFIG_SND_SOC_IMX_PCM_DMA\n  FILES:= \\\n\t$(LINUX_DIR)/sound/soc/fsl/snd-soc-imx-audmux.ko \\\n\t$(LINUX_DIR)/sound/soc/fsl/snd-soc-fsl-ssi.ko \\\n\t$(LINUX_DIR)/sound/soc/fsl/imx-pcm-dma.ko\n  AUTOLOAD:=$(call AutoLoad,56,snd-soc-imx-audmux snd-soc-fsl-ssi snd-soc-imx-pcm)\n  DEPENDS:=@TARGET_imx +kmod-sound-soc-core\n  $(call AddDepends/sound)\nendef\n\ndefine KernelPackage/sound-soc-imx/description\n Support for i.MX Platform sound (ssi/audmux/pcm)\nendef\n\n$(eval $(call KernelPackage,sound-soc-imx))\n\n\ndefine KernelPackage/sound-soc-imx-sgtl5000\n  TITLE:=IMX SoC support for SGTL5000\n  KCONFIG:=CONFIG_SND_SOC_IMX_SGTL5000\n  FILES:=\\\n\t$(LINUX_DIR)/sound/soc/codecs/snd-soc-sgtl5000.ko \\\n\t$(LINUX_DIR)/sound/soc/fsl/snd-soc-imx-sgtl5000.ko\n  AUTOLOAD:=$(call AutoLoad,57,snd-soc-sgtl5000 snd-soc-imx-sgtl5000)\n  DEPENDS:=@TARGET_imx +kmod-sound-soc-imx +kmod-regmap-i2c\n  $(call AddDepends/sound)\nendef\n\ndefine KernelPackage/sound-soc-imx-sgtl5000/description\n Support for i.MX Platform sound SGTL5000 codec\nendef\n\n$(eval $(call KernelPackage,sound-soc-imx-sgtl5000))\n\n\ndefine KernelPackage/sound-soc-spdif\n  TITLE:=SoC S/PDIF codec support\n  KCONFIG:=CONFIG_SND_SOC_SPDIF\n  FILES:= \\\n\t$(LINUX_DIR)/sound/soc/codecs/snd-soc-spdif-tx.ko \\\n\t$(LINUX_DIR)/sound/soc/codecs/snd-soc-spdif-rx.ko\n  DEPENDS:=+kmod-sound-soc-core\n  AUTOLOAD:=$(call AutoProbe,snd-soc-spdif-tx snd-soc-spdif-rx)\n  $(call AddDepends/sound)\nendef\n\n$(eval $(call KernelPackage,sound-soc-spdif))\n\n\ndefine KernelPackage/pcspkr\n  DEPENDS:=@TARGET_x86 +kmod-input-core\n  TITLE:=PC speaker support\n  KCONFIG:= \\\n\tCONFIG_SND_PCSP\n  FILES:= \\\n\t$(LINUX_DIR)/sound/drivers/pcsp/snd-pcsp.ko\n  AUTOLOAD:=$(call AutoLoad,50,snd-pcsp)\n  $(call AddDepends/sound)\nendef\n\ndefine KernelPackage/pcspkr/description\n This enables sounds (tones) through the pc speaker\nendef\n\n$(eval $(call KernelPackage,pcspkr))\n\ndefine KernelPackage/sound-dummy\n  $(call AddDepends/sound)\n  TITLE:=Null sound output driver (sink)\n  KCONFIG:= \\\n\tCONFIG_SND_DUMMY\n  FILES:= \\\n\t$(LINUX_DIR)/sound/drivers/snd-dummy.ko\n  AUTOLOAD:=$(call AutoLoad,32,snd-dummy)\nendef\n\ndefine KernelPackage/sound-dummy/description\n Dummy sound device for Alsa when no hardware present\nendef\n\n$(eval $(call KernelPackage,sound-dummy))\n\ndefine KernelPackage/sound-hda-core\n  SUBMENU:=$(SOUND_MENU)\n  TITLE:=HD Audio Sound Core Support\n  DEPENDS:=+kmod-ledtrig-audio\n  KCONFIG:= \\\n\tCONFIG_SND_HDA_CORE \\\n\tCONFIG_SND_HDA_HWDEP=y \\\n\tCONFIG_SND_HDA_RECONFIG=n \\\n\tCONFIG_SND_HDA_INPUT_BEEP=n \\\n\tCONFIG_SND_HDA_PATCH_LOADER=n \\\n\tCONFIG_SND_HDA_GENERIC\n  FILES:= \\\n\t$(LINUX_DIR)/sound/hda/snd-hda-core.ko \\\n\t$(LINUX_DIR)/sound/pci/hda/snd-hda-codec.ko \\\n\t$(LINUX_DIR)/sound/pci/hda/snd-hda-codec-generic.ko\n  AUTOLOAD:=$(call AutoProbe,snd-hda-core snd-hda-codec snd-hda-codec-generic)\n  $(call AddDepends/sound,+kmod-regmap-core)\nendef\n\ndefine KernelPackage/sound-hda-core/description\n Kernel modules for HD Audio sound support\nendef\n\n$(eval $(call KernelPackage,sound-hda-core))\n\ndefine KernelPackage/sound-hda-codec-realtek\n  SUBMENU:=$(SOUND_MENU)\n  TITLE:= HD Audio Realtek Codec\n  KCONFIG:= \\\n\tCONFIG_SND_HDA_CODEC_REALTEK\n  FILES:= \\\n\t$(LINUX_DIR)/sound/pci/hda/snd-hda-codec-realtek.ko\n  AUTOLOAD:=$(call AutoProbe,snd-hda-codec-realtek)\n  $(call AddDepends/sound,kmod-sound-hda-core)\nendef\n\ndefine KernelPackage/sound-hda-codec-realtek/description\n Kernel modules for Intel HDA Realtek codec support\nendef\n\n$(eval $(call KernelPackage,sound-hda-codec-realtek))\n\ndefine KernelPackage/sound-hda-codec-cmedia\n  SUBMENU:=$(SOUND_MENU)\n  TITLE:=HD Audio C-Media Codec\n  KCONFIG:= \\\n\tCONFIG_SND_HDA_CODEC_CMEDIA\n  FILES:= \\\n\t$(LINUX_DIR)/sound/pci/hda/snd-hda-codec-cmedia.ko\n  AUTOLOAD:=$(call AutoProbe,snd-hda-codec-cmedia)\n  $(call AddDepends/sound,kmod-sound-hda-core)\nendef\n\ndefine KernelPackage/sound-hda-codec-cmedia/description\n Kernel modules for HD Audio C-Media codec support\nendef\n\n$(eval $(call KernelPackage,sound-hda-codec-cmedia))\n\ndefine KernelPackage/sound-hda-codec-analog\n  SUBMENU:=$(SOUND_MENU)\n  TITLE:=HD Audio Analog Devices Codec\n  KCONFIG:= \\\n\tCONFIG_SND_HDA_CODEC_ANALOG\n  FILES:= \\\n\t$(LINUX_DIR)/sound/pci/hda/snd-hda-codec-analog.ko\n  AUTOLOAD:=$(call AutoProbe,snd-hda-codec-analog)\n  $(call AddDepends/sound,kmod-sound-hda-core)\nendef\n\ndefine KernelPackage/sound-hda-codec-analog/description\n Kernel modules for HD Audio Analog Devices codec support\nendef\n\n$(eval $(call KernelPackage,sound-hda-codec-analog))\n\ndefine KernelPackage/sound-hda-codec-idt\n  SUBMENU:=$(SOUND_MENU)\n  TITLE:=HD Audio Sigmatel IDT Codec\n  KCONFIG:= \\\n\tCONFIG_SND_HDA_CODEC_SIGMATEL\n  FILES:= \\\n\t$(LINUX_DIR)/sound/pci/hda/snd-hda-codec-idt.ko\n  AUTOLOAD:=$(call AutoProbe,snd-hda-codec-idt)\n  $(call AddDepends/sound,kmod-sound-hda-core)\nendef\n\ndefine KernelPackage/sound-hda-codec-idt/description\n Kernel modules for HD Audio Sigmatel IDT codec support\nendef\n\n$(eval $(call KernelPackage,sound-hda-codec-idt))\n\ndefine KernelPackage/sound-hda-codec-si3054\n  SUBMENU:=$(SOUND_MENU)\n  TITLE:=HD Audio Silicon Labs 3054 Codec\n  KCONFIG:= \\\n\tCONFIG_SND_HDA_CODEC_SI3054\n  FILES:= \\\n\t$(LINUX_DIR)/sound/pci/hda/snd-hda-codec-si3054.ko\n  AUTOLOAD:=$(call AutoProbe,snd-hda-codec-si3054)\n  $(call AddDepends/sound,kmod-sound-hda-core)\nendef\n\ndefine KernelPackage/sound-hda-codec-si3054/description\n Kernel modules for HD Audio Silicon Labs 3054 codec support\nendef\n\n$(eval $(call KernelPackage,sound-hda-codec-si3054))\n\ndefine KernelPackage/sound-hda-codec-cirrus\n  SUBMENU:=$(SOUND_MENU)\n  TITLE:=HD Audio Cirrus Logic Codec\n  KCONFIG:= \\\n\tCONFIG_SND_HDA_CODEC_CIRRUS\n  FILES:= \\\n\t$(LINUX_DIR)/sound/pci/hda/snd-hda-codec-cirrus.ko\n  AUTOLOAD:=$(call AutoProbe,snd-hda-codec-cirrus)\n  $(call AddDepends/sound,kmod-sound-hda-core)\nendef\n\ndefine KernelPackage/sound-hda-codec-cirrus/description\n Kernel modules for HD Audio Cirrus Logic codec support\nendef\n\n$(eval $(call KernelPackage,sound-hda-codec-cirrus))\n\ndefine KernelPackage/sound-hda-codec-ca0110\n  SUBMENU:=$(SOUND_MENU)\n  TITLE:=HD Audio Creative CA0110 Codec\n  KCONFIG:= \\\n\tCONFIG_SND_HDA_CODEC_CA0110\n  FILES:= \\\n\t$(LINUX_DIR)/sound/pci/hda/snd-hda-codec-ca0110.ko\n  AUTOLOAD:=$(call AutoProbe,snd-hda-codec-ca0110)\n  $(call AddDepends/sound,kmod-sound-hda-core)\nendef\n\ndefine KernelPackage/sound-hda-codec-ca0110/description\n Kernel modules for HD Audio Creative CA0110 codec support\nendef\n\n$(eval $(call KernelPackage,sound-hda-codec-ca0110))\n\ndefine KernelPackage/sound-hda-codec-ca0132\n  SUBMENU:=$(SOUND_MENU)\n  TITLE:=HD Audio Creative CA0132 Codec\n  KCONFIG:= \\\n\tCONFIG_SND_HDA_CODEC_CA0132 \\\n\tCONFIG_SND_HDA_CODEC_CA0132_DSP=n\n  FILES:= \\\n\t$(LINUX_DIR)/sound/pci/hda/snd-hda-codec-ca0132.ko\n  AUTOLOAD:=$(call AutoProbe,snd-hda-codec-ca0132)\n  $(call AddDepends/sound,kmod-sound-hda-core)\nendef\n\ndefine KernelPackage/sound-hda-codec-ca0132/description\n Kernel modules for HD Audio Creative CA0132 codec support\nendef\n\n$(eval $(call KernelPackage,sound-hda-codec-ca0132))\n\ndefine KernelPackage/sound-hda-codec-conexant\n  SUBMENU:=$(SOUND_MENU)\n  TITLE:=HD Audio Conexant Codec\n  KCONFIG:= \\\n\tCONFIG_SND_HDA_CODEC_CONEXANT\n  FILES:= \\\n\t$(LINUX_DIR)/sound/pci/hda/snd-hda-codec-conexant.ko\n  AUTOLOAD:=$(call AutoProbe,snd-hda-codec-conexant)\n  $(call AddDepends/sound,kmod-sound-hda-core)\nendef\n\ndefine KernelPackage/sound-hda-codec-conexant/description\n Kernel modules for HD Audio Conexant codec support\nendef\n\n$(eval $(call KernelPackage,sound-hda-codec-conexant))\n\ndefine KernelPackage/sound-hda-codec-via\n  SUBMENU:=$(SOUND_MENU)\n  TITLE:=HD Audio Via Codec\n  KCONFIG:= \\\n\tCONFIG_SND_HDA_CODEC_VIA\n  FILES:= \\\n\t$(LINUX_DIR)/sound/pci/hda/snd-hda-codec-via.ko\n  AUTOLOAD:=$(call AutoProbe,snd-hda-codec-via)\n  $(call AddDepends/sound,kmod-sound-hda-core)\nendef\n\ndefine KernelPackage/sound-hda-codec-via/description\n Kernel modules for HD Audio VIA codec support\nendef\n\n$(eval $(call KernelPackage,sound-hda-codec-via))\n\ndefine KernelPackage/sound-hda-codec-hdmi\n  SUBMENU:=$(SOUND_MENU)\n  TITLE:=HD Audio HDMI/DisplayPort Codec\n  KCONFIG:= \\\n\tCONFIG_SND_HDA_CODEC_HDMI\n  FILES:= \\\n\t$(LINUX_DIR)/sound/pci/hda/snd-hda-codec-hdmi.ko\n  AUTOLOAD:=$(call AutoProbe,snd-hda-codec-hdmi)\n  $(call AddDepends/sound,kmod-sound-hda-core)\nendef\n\ndefine KernelPackage/sound-hda-codec-hdmi/description\n Kernel modules for HD Audio HDMI codec support\nendef\n\n$(eval $(call KernelPackage,sound-hda-codec-hdmi))\n\ndefine KernelPackage/sound-hda-intel\n  SUBMENU:=$(SOUND_MENU)\n  TITLE:=HD Audio Intel Driver\n  DEPENDS:=@TARGET_x86\n  KCONFIG:= \\\n\tCONFIG_SOUND_PCI \\\n\tCONFIG_SND_HDA_INTEL\n  FILES:= \\\n\t$(LINUX_DIR)/sound/pci/hda/snd-hda-intel.ko \\\n\t$(LINUX_DIR)/sound/hda/snd-intel-nhlt.ko@lt5.5 \\\n\t$(LINUX_DIR)/sound/hda/snd-intel-dspcfg.ko@ge5.5\n  AUTOLOAD:=$(call AutoProbe,snd-hda-intel)\n  $(call AddDepends/sound,kmod-sound-hda-core)\nendef\n\ndefine KernelPackage/sound-hda-intel/description\n Kernel modules for HD Audio Intel driver support\nendef\n\n$(eval $(call KernelPackage,sound-hda-intel))\n"
  },
  {
    "path": "package/kernel/linux/modules/spi.mk",
    "content": "#\n# Copyright (C) 2006-2011 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\nSPI_MENU:=SPI Support\n\ndefine KernelPackage/mmc-spi\n  SUBMENU:=$(SPI_MENU)\n  TITLE:=MMC/SD over SPI Support\n  DEPENDS:=+kmod-mmc +kmod-lib-crc-itu-t +kmod-lib-crc7\n  KCONFIG:=CONFIG_MMC_SPI \\\n          CONFIG_SPI=y \\\n          CONFIG_SPI_MASTER=y\n  FILES:=\\\n\t$(if $(CONFIG_OF),$(LINUX_DIR)/drivers/mmc/host/of_mmc_spi.ko) \\\n\t$(LINUX_DIR)/drivers/mmc/host/mmc_spi.ko\n  AUTOLOAD:=$(call AutoProbe,$(if $(CONFIG_OF),of_mmc_spi) mmc_spi)\nendef\n\ndefine KernelPackage/mmc-spi/description\n Kernel support for MMC/SD over SPI\nendef\n\n$(eval $(call KernelPackage,mmc-spi))\n\n\ndefine KernelPackage/spi-bitbang\n  SUBMENU:=$(SPI_MENU)\n  TITLE:=Serial Peripheral Interface bitbanging library\n  KCONFIG:=CONFIG_SPI_BITBANG \\\n          CONFIG_SPI=y \\\n          CONFIG_SPI_MASTER=y\n  FILES:=$(LINUX_DIR)/drivers/spi/spi-bitbang.ko\nendef\n\ndefine KernelPackage/spi-bitbang/description\n This package contains the SPI bitbanging library\nendef\n\n$(eval $(call KernelPackage,spi-bitbang))\n\n\ndefine KernelPackage/spi-gpio\n  SUBMENU:=$(SPI_MENU)\n  TITLE:=GPIO-based bitbanging SPI Master\n  DEPENDS:=@GPIO_SUPPORT +kmod-spi-bitbang\n  KCONFIG:=CONFIG_SPI_GPIO\n  FILES:=$(LINUX_DIR)/drivers/spi/spi-gpio.ko\n  AUTOLOAD:=$(call AutoProbe,spi-gpio)\nendef\n\ndefine KernelPackage/spi-gpio/description\n This package contains the GPIO-based bitbanging SPI Master\nendef\n\n$(eval $(call KernelPackage,spi-gpio))\n\ndefine KernelPackage/spi-dev\n  SUBMENU:=$(SPI_MENU)\n  TITLE:=User mode SPI device driver\n  KCONFIG:=CONFIG_SPI_SPIDEV \\\n          CONFIG_SPI=y \\\n          CONFIG_SPI_MASTER=y\n  FILES:=$(LINUX_DIR)/drivers/spi/spidev.ko\n  AUTOLOAD:=$(call AutoProbe,spidev)\nendef\n\ndefine KernelPackage/spi-dev/description\n This package contains the user mode SPI device driver\nendef\n\n$(eval $(call KernelPackage,spi-dev))\n"
  },
  {
    "path": "package/kernel/linux/modules/usb.mk",
    "content": "#\n# Copyright (C) 2006-2014 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\nUSB_MENU:=USB Support\n\nUSBNET_DIR:=net/usb\nUSBHID_DIR?=hid/usbhid\nUSBINPUT_DIR?=input/misc\n\ndefine KernelPackage/usb-core\n  SUBMENU:=$(USB_MENU)\n  TITLE:=Support for USB\n  DEPENDS:=@USB_SUPPORT\n  KCONFIG:=CONFIG_USB CONFIG_XPS_USB_HCD_XILINX=n CONFIG_USB_FHCI_HCD=n\n  FILES:= \\\n\t$(LINUX_DIR)/drivers/usb/core/usbcore.ko \\\n\t$(LINUX_DIR)/drivers/usb/common/usb-common.ko\n  AUTOLOAD:=$(call AutoLoad,20,usb-common usbcore,1)\n  $(call AddDepends/nls)\nendef\n\ndefine KernelPackage/usb-core/description\n Kernel support for USB\nendef\n\n$(eval $(call KernelPackage,usb-core))\n\n\ndefine AddDepends/usb\n  SUBMENU:=$(USB_MENU)\n  DEPENDS+=+kmod-usb-core $(1)\nendef\n\n\ndefine KernelPackage/usb-ledtrig-usbport\n  TITLE:=LED trigger for USB ports\n  KCONFIG:=CONFIG_USB_LEDS_TRIGGER_USBPORT\n  FILES:=$(LINUX_DIR)/drivers/usb/core/ledtrig-usbport.ko\n  AUTOLOAD:=$(call AutoLoad,50,ledtrig-usbport)\n  $(call AddDepends/usb)\nendef\n\ndefine KernelPackage/usb-ledtrig-usbport/description\n  This driver allows LEDs to be controlled by USB events. Enabling this\n  trigger allows specifying list of USB ports that should turn on LED\n  when some USB device gets connected.\n  If possible it should be prefered over similar ledtrig-usbdev.\nendef\n\n$(eval $(call KernelPackage,usb-ledtrig-usbport))\n\n\ndefine KernelPackage/usb-phy-nop\n  TITLE:=Support for USB NOP transceiver\n  KCONFIG:=CONFIG_NOP_USB_XCEIV\n  HIDDEN:=1\n  FILES:=$(LINUX_DIR)/drivers/usb/phy/phy-generic.ko\n  AUTOLOAD:=$(call AutoLoad,21,phy-generic,1)\n  $(call AddDepends/usb)\nendef\n\ndefine KernelPackage/usb-phy-nop/description\n  Support for USB NOP transceiver\nendef\n\n$(eval $(call KernelPackage,usb-phy-nop))\n\n\ndefine KernelPackage/phy-ath79-usb\n  TITLE:=Support for ATH79 USB PHY\n  KCONFIG:=CONFIG_PHY_AR7100_USB \\\n\tCONFIG_PHY_AR7200_USB\n  DEPENDS:=@TARGET_ath79\n  HIDDEN:=1\n  FILES:=$(LINUX_DIR)/drivers/phy/phy-ar7100-usb.ko \\\n\t$(LINUX_DIR)/drivers/phy/phy-ar7200-usb.ko\n  AUTOLOAD:=$(call AutoLoad,21,phy-ar7100-usb phy-ar7200-usb,1)\n  $(call AddDepends/usb)\nendef\n\ndefine KernelPackage/phy-ath79-usb/description\n  Support for ATH79 USB transceiver\nendef\n\n$(eval $(call KernelPackage,phy-ath79-usb))\n\n\ndefine KernelPackage/usb-gadget\n  TITLE:=USB Gadget support\n  KCONFIG:=CONFIG_USB_GADGET\n  HIDDEN:=1\n  FILES:=\\\n\t$(LINUX_DIR)/drivers/usb/gadget/udc/udc-core.ko\n  AUTOLOAD:=$(call AutoLoad,21,udc-core,1)\n  DEPENDS:=@USB_GADGET_SUPPORT\n  $(call AddDepends/usb)\nendef\n\ndefine KernelPackage/usb-gadget/description\n Kernel support for USB Gadget mode\nendef\n\n$(eval $(call KernelPackage,usb-gadget))\n\ndefine KernelPackage/usb-lib-composite\n  TITLE:=USB lib composite\n  KCONFIG:=CONFIG_USB_LIBCOMPOSITE\n  DEPENDS:=+kmod-usb-gadget +kmod-fs-configfs\n  HIDDEN:=1\n  FILES:=$(LINUX_DIR)/drivers/usb/gadget/libcomposite.ko\n  AUTOLOAD:=$(call AutoLoad,50,libcomposite)\n  $(call AddDepends/usb)\nendef\n\ndefine KernelPackage/usb-lib-composite/description\n Lib Composite\nendef\n\n$(eval $(call KernelPackage,usb-lib-composite))\n\ndefine KernelPackage/usb-gadget-hid\n  TITLE:=USB HID Gadget Support\n  KCONFIG:=CONFIG_USB_G_HID\n  DEPENDS:=+kmod-usb-gadget +kmod-usb-lib-composite\n  FILES:= \\\n\t  $(LINUX_DIR)/drivers/usb/gadget/legacy/g_hid.ko \\\n\t  $(LINUX_DIR)/drivers/usb/gadget/function/usb_f_hid.ko\n  AUTOLOAD:=$(call AutoLoad,52,usb_f_hid)\n  $(call AddDepends/usb)\nendef\n\ndefine KernelPackage/usb-gadget-hid/description\n  Kernel support for USB HID Gadget.\nendef\n\n$(eval $(call KernelPackage,usb-gadget-hid))\n\ndefine KernelPackage/usb-gadget-ehci-debug\n  TITLE:=USB EHCI debug port Gadget support\n  KCONFIG:=\\\n\tCONFIG_USB_G_DBGP \\\n\tCONFIG_USB_G_DBGP_SERIAL=y \\\n\tCONFIG_USB_G_DBGP_PRINTK=n\n  DEPENDS:=+kmod-usb-gadget +kmod-usb-lib-composite +kmod-usb-gadget-serial\n  FILES:=$(LINUX_DIR)/drivers/usb/gadget/legacy/g_dbgp.ko\n  $(call AddDepends/usb)\nendef\n\ndefine KernelPackage/usb-gadget-ehci-debug/description\n  Kernel support for USB EHCI debug port Gadget.\nendef\n\n$(eval $(call KernelPackage,usb-gadget-ehci-debug))\n\ndefine KernelPackage/usb-gadget-eth\n  TITLE:=USB Ethernet Gadget support\n  KCONFIG:= \\\n\tCONFIG_USB_ETH \\\n\tCONFIG_USB_ETH_RNDIS=y \\\n\tCONFIG_USB_ETH_EEM=n\n  DEPENDS:=+kmod-usb-gadget +kmod-usb-lib-composite\n  FILES:= \\\n\t$(LINUX_DIR)/drivers/usb/gadget/function/u_ether.ko \\\n\t$(LINUX_DIR)/drivers/usb/gadget/function/usb_f_ecm.ko \\\n\t$(LINUX_DIR)/drivers/usb/gadget/function/usb_f_ecm_subset.ko \\\n\t$(LINUX_DIR)/drivers/usb/gadget/function/usb_f_rndis.ko \\\n\t$(LINUX_DIR)/drivers/usb/gadget/legacy/g_ether.ko\n  AUTOLOAD:=$(call AutoLoad,52,usb_f_ecm)\n  $(call AddDepends/usb)\nendef\n\ndefine KernelPackage/usb-gadget-eth/description\n Kernel support for USB Ethernet Gadget\nendef\n\n$(eval $(call KernelPackage,usb-gadget-eth))\n\ndefine KernelPackage/usb-gadget-ncm\n  TITLE:=USB Network Control Model (NCM) Gadget support\n  KCONFIG:=CONFIG_USB_G_NCM\n  DEPENDS:=+kmod-usb-gadget +kmod-usb-lib-composite \\\n\t+kmod-usb-gadget-eth\n  FILES:= \\\n\t$(LINUX_DIR)/drivers/usb/gadget/function/usb_f_ncm.ko \\\n\t$(LINUX_DIR)/drivers/usb/gadget/legacy/g_ncm.ko\n  AUTOLOAD:=$(call AutoLoad,52,usb_f_ncm)\n  $(call AddDepends/usb)\nendef\n\ndefine KernelPackage/usb-gadget-ncm/description\n  Kernel support for USB Network Control Model (NCM) Gadget\nendef\n\n$(eval $(call KernelPackage,usb-gadget-ncm))\n\ndefine KernelPackage/usb-gadget-serial\n  TITLE:=USB Serial Gadget support\n  KCONFIG:=CONFIG_USB_G_SERIAL\n  DEPENDS:=+kmod-usb-gadget +kmod-usb-lib-composite\n  FILES:= \\\n\t$(LINUX_DIR)/drivers/usb/gadget/function/u_serial.ko \\\n\t$(LINUX_DIR)/drivers/usb/gadget/function/usb_f_acm.ko \\\n\t$(LINUX_DIR)/drivers/usb/gadget/function/usb_f_obex.ko \\\n\t$(LINUX_DIR)/drivers/usb/gadget/function/usb_f_serial.ko \\\n\t$(LINUX_DIR)/drivers/usb/gadget/legacy/g_serial.ko\n  AUTOLOAD:=$(call AutoLoad,52,usb_f_acm)\n  $(call AddDepends/usb)\nendef\n\ndefine KernelPackage/usb-gadget-serial/description\n  Kernel support for USB Serial Gadget.\nendef\n\n$(eval $(call KernelPackage,usb-gadget-serial))\n\ndefine KernelPackage/usb-gadget-mass-storage\n  TITLE:=USB Mass Storage support\n  KCONFIG:=CONFIG_USB_MASS_STORAGE\n  DEPENDS:=+kmod-usb-gadget +kmod-usb-lib-composite\n  FILES:= \\\n\t$(LINUX_DIR)/drivers/usb/gadget/function/usb_f_mass_storage.ko \\\n\t$(LINUX_DIR)/drivers/usb/gadget/legacy/g_mass_storage.ko\n  AUTOLOAD:=$(call AutoLoad,52,usb_f_mass_storage)\n  $(call AddDepends/usb)\nendef\n\ndefine KernelPackage/usb-gadget-mass-storage/description\n  Kernel support for USB Gadget Mass Storage\nendef\n\n$(eval $(call KernelPackage,usb-gadget-mass-storage))\n\ndefine KernelPackage/usb-gadget-cdc-composite\n  TITLE:= USB CDC Composite (Ethernet + ACM)\n  KCONFIG:=CONFIG_USB_CDC_COMPOSITE\n  DEPENDS:=+kmod-usb-gadget +kmod-usb-lib-composite \\\n\t+kmod-usb-gadget-eth +kmod-usb-gadget-serial\n  FILES:= $(LINUX_DIR)/drivers/usb/gadget/legacy/g_cdc.ko\n  $(call AddDepends/usb)\nendef\n\ndefine KernelPackage/usb-gadget-cdc-composite/description\n  Kernel support for the USB CDC Composite gadget.\n  This appears as an ethernet + ACM serial gadget.\nendef\n\n$(eval $(call KernelPackage,usb-gadget-cdc-composite))\n\n\ndefine KernelPackage/usb-uhci\n  TITLE:=Support for UHCI controllers\n  KCONFIG:= \\\n\tCONFIG_USB_PCI=y \\\n\tCONFIG_USB_UHCI_ALT \\\n\tCONFIG_USB_UHCI_HCD\n  FILES:=$(LINUX_DIR)/drivers/usb/host/uhci-hcd.ko\n  AUTOLOAD:=$(call AutoLoad,50,uhci-hcd,1)\n  $(call AddDepends/usb)\nendef\n\ndefine KernelPackage/usb-uhci/description\n Kernel support for USB UHCI controllers\nendef\n\n$(eval $(call KernelPackage,usb-uhci,1))\n\n\ndefine KernelPackage/usb-ohci\n  TITLE:=Support for OHCI controllers\n  DEPENDS:= \\\n\t+TARGET_bcm53xx:kmod-usb-bcma \\\n\t+TARGET_bcm47xx:kmod-usb-bcma \\\n\t+TARGET_bcm47xx:kmod-usb-ssb\n  KCONFIG:= \\\n\tCONFIG_USB_OHCI \\\n\tCONFIG_USB_OHCI_HCD \\\n\tCONFIG_USB_OHCI_ATH79=y \\\n\tCONFIG_USB_OHCI_HCD_AT91=y \\\n\tCONFIG_USB_OHCI_BCM63XX=y \\\n\tCONFIG_USB_OCTEON_OHCI=y \\\n\tCONFIG_USB_OHCI_HCD_OMAP3=y \\\n\tCONFIG_USB_OHCI_HCD_PLATFORM=y\n  FILES:= \\\n\t$(LINUX_DIR)/drivers/usb/host/ohci-hcd.ko \\\n\t$(LINUX_DIR)/drivers/usb/host/ohci-platform.ko\n  ifneq ($(wildcard $(LINUX_DIR)/drivers/usb/host/ohci-at91.ko),)\n    FILES+=$(LINUX_DIR)/drivers/usb/host/ohci-at91.ko\n  endif\n  AUTOLOAD:=$(call AutoLoad,50,ohci-hcd ohci-platform ohci-at91,1)\n  $(call AddDepends/usb)\nendef\n\ndefine KernelPackage/usb-ohci/description\n Kernel support for USB OHCI controllers\nendef\n\n$(eval $(call KernelPackage,usb-ohci,1))\n\n\ndefine KernelPackage/usb-ohci-pci\n  TITLE:=Support for PCI OHCI controllers\n  DEPENDS:=@PCI_SUPPORT +kmod-usb-ohci\n  KCONFIG:= \\\n\tCONFIG_USB_PCI=y \\\n\tCONFIG_USB_OHCI_HCD_PCI\n  FILES:=$(LINUX_DIR)/drivers/usb/host/ohci-pci.ko\n  AUTOLOAD:=$(call AutoLoad,51,ohci-pci,1)\n  $(call AddDepends/usb)\nendef\n\ndefine KernelPackage/usb-ohci-pci/description\n Kernel support for PCI OHCI controllers\nendef\n\n$(eval $(call KernelPackage,usb-ohci-pci))\n\n\ndefine KernelPackage/usb-bcma\n  TITLE:=Support for BCMA USB controllers\n  DEPENDS:=@USB_SUPPORT @TARGET_bcm47xx||TARGET_bcm53xx\n  HIDDEN:=1\n  KCONFIG:=CONFIG_USB_HCD_BCMA\n  FILES:= \\\n\t$(if $(CONFIG_USB_HCD_BCMA),$(LINUX_DIR)/drivers/usb/host/bcma-hcd.ko)\n  AUTOLOAD:=$(call AutoLoad,19,$(if $(CONFIG_USB_HCD_BCMA),bcma-hcd),1)\n  $(call AddDepends/usb)\nendef\n$(eval $(call KernelPackage,usb-bcma))\n\ndefine KernelPackage/usb-fotg210\n  TITLE:=Support for FOTG210 USB host controllers\n  DEPENDS:=@USB_SUPPORT @TARGET_gemini\n  KCONFIG:=CONFIG_USB_FOTG210_HCD\n  FILES:= \\\n\t$(if $(CONFIG_USB_FOTG210_HCD),$(LINUX_DIR)/drivers/usb/host/fotg210-hcd.ko)\n  AUTOLOAD:=$(call AutoLoad,50,fotg210-hcd,1)\n  $(call AddDepends/usb)\nendef\n$(eval $(call KernelPackage,usb-fotg210))\n\ndefine KernelPackage/usb-ssb\n  TITLE:=Support for SSB USB controllers\n  DEPENDS:=@USB_SUPPORT @TARGET_bcm47xx\n  HIDDEN:=1\n  KCONFIG:=CONFIG_USB_HCD_SSB\n  FILES:= \\\n\t$(if $(CONFIG_USB_HCD_SSB),$(LINUX_DIR)/drivers/usb/host/ssb-hcd.ko)\n  AUTOLOAD:=$(call AutoLoad,19,$(if $(CONFIG_USB_HCD_SSB),ssb-hcd),1)\n  $(call AddDepends/usb)\nendef\n$(eval $(call KernelPackage,usb-ssb))\n\ndefine KernelPackage/usb-ehci\n  TITLE:=EHCI controller support\n  HIDDEN:=1\n  KCONFIG:= \\\n\tCONFIG_USB_EHCI_HCD\n  FILES:= \\\n\t$(LINUX_DIR)/drivers/usb/host/ehci-hcd.ko\n  AUTOLOAD:=$(call AutoLoad,35,ehci-hcd,1)\n  $(call AddDepends/usb)\nendef\n$(eval $(call KernelPackage,usb-ehci))\n\ndefine KernelPackage/usb2\n  TITLE:=Support for USB2 controllers\n  DEPENDS:=\\\n\t+TARGET_bcm47xx:kmod-usb-bcma \\\n\t+TARGET_bcm47xx:kmod-usb-ssb \\\n\t+TARGET_bcm53xx:kmod-usb-bcma \\\n\t+TARGET_bcm53xx:kmod-phy-bcm-ns-usb2 \\\n\t+TARGET_ath79:kmod-phy-ath79-usb \\\n\t+kmod-usb-ehci\n  KCONFIG:=\\\n\tCONFIG_USB_EHCI_HCD_PLATFORM \\\n\tCONFIG_USB_EHCI_BCM63XX=y \\\n\tCONFIG_USB_IMX21_HCD=y \\\n\tCONFIG_USB_EHCI_MXC=y \\\n\tCONFIG_USB_OCTEON_EHCI=y \\\n\tCONFIG_USB_EHCI_HCD_ORION=y \\\n\tCONFIG_USB_EHCI_HCD_AT91=y \\\n\tCONFIG_USB_EHCI_FSL\n  FILES:= \\\n\t$(LINUX_DIR)/drivers/usb/host/ehci-platform.ko\n  ifneq ($(wildcard $(LINUX_DIR)/drivers/usb/host/ehci-orion.ko),)\n    FILES+=$(LINUX_DIR)/drivers/usb/host/ehci-orion.ko\n  endif\n  ifneq ($(wildcard $(LINUX_DIR)/drivers/usb/host/ehci-atmel.ko),)\n    FILES+=$(LINUX_DIR)/drivers/usb/host/ehci-atmel.ko\n  endif\n  ifneq ($(wildcard $(LINUX_DIR)/drivers/usb/host/ehci-fsl.ko),)\n    FILES+=$(LINUX_DIR)/drivers/usb/host/ehci-fsl.ko\n  endif\n  ifneq ($(wildcard $(LINUX_DIR)/drivers/usb/host/fsl-mph-dr-of.ko),)\n    FILES+=$(LINUX_DIR)/drivers/usb/host/fsl-mph-dr-of.ko\n  endif\n  AUTOLOAD:=$(call AutoLoad,40,ehci-hcd ehci-platform ehci-orion ehci-atmel ehci-fsl fsl-mph-dr-of,1)\n  $(call AddDepends/usb)\nendef\n\ndefine KernelPackage/usb2/description\n Kernel support for USB2 (EHCI) controllers\nendef\n\n$(eval $(call KernelPackage,usb2))\n\n\ndefine KernelPackage/usb2-pci\n  TITLE:=Support for PCI USB2 controllers\n  DEPENDS:=@PCI_SUPPORT +kmod-usb2\n  KCONFIG:= \\\n\tCONFIG_USB_PCI=y \\\n\tCONFIG_USB_EHCI_PCI\n  FILES:=$(LINUX_DIR)/drivers/usb/host/ehci-pci.ko\n  AUTOLOAD:=$(call AutoLoad,42,ehci-pci,1)\n  $(call AddDepends/usb)\nendef\n\ndefine KernelPackage/usb2-pci/description\n Kernel support for PCI USB2 (EHCI) controllers\nendef\n\n$(eval $(call KernelPackage,usb2-pci))\n\n\ndefine KernelPackage/usb-dwc2\n  TITLE:=DWC2 USB controller driver\n  DEPENDS:=+USB_GADGET_SUPPORT:kmod-usb-gadget +kmod-usb-roles\n  KCONFIG:= \\\n\tCONFIG_USB_PCI=y \\\n\tCONFIG_USB_DWC2 \\\n\tCONFIG_USB_DWC2_PCI \\\n\tCONFIG_USB_DWC2_PLATFORM \\\n\tCONFIG_USB_DWC2_DEBUG=n \\\n\tCONFIG_USB_DWC2_VERBOSE=n \\\n\tCONFIG_USB_DWC2_TRACK_MISSED_SOFS=n \\\n\tCONFIG_USB_DWC2_DEBUG_PERIODIC=n\n  FILES:= \\\n\t$(LINUX_DIR)/drivers/usb/dwc2/dwc2.ko\n  AUTOLOAD:=$(call AutoLoad,54,dwc2,1)\n  $(call AddDepends/usb)\nendef\n\ndefine KernelPackage/usb-dwc2/description\n This driver provides USB Device Controller support for the\n Synopsys DesignWare USB OTG Core\nendef\n\n$(eval $(call KernelPackage,usb-dwc2))\n\n\ndefine KernelPackage/usb-dwc3\n  TITLE:=DWC3 USB controller driver\n  KCONFIG:= \\\n\tCONFIG_USB_DWC3 \\\n\tCONFIG_USB_DWC3_HOST=y \\\n\tCONFIG_USB_DWC3_GADGET=n \\\n\tCONFIG_USB_DWC3_DUAL_ROLE=n \\\n\tCONFIG_USB_DWC3_DEBUG=n \\\n\tCONFIG_USB_DWC3_VERBOSE=n\n  FILES:= $(LINUX_DIR)/drivers/usb/dwc3/dwc3.ko\n  AUTOLOAD:=$(call AutoLoad,54,dwc3,1)\n  $(call AddDepends/usb)\nendef\n\ndefine KernelPackage/usb-dwc3/description\n This driver provides support for the Dual Role SuperSpeed\n USB Controller based on the Synopsys DesignWare USB3 IP Core\nendef\n\n$(eval $(call KernelPackage,usb-dwc3))\n\n\ndefine KernelPackage/usb-dwc3-qcom\n  TITLE:=DWC3 Qualcomm USB driver\n  DEPENDS:=@(TARGET_ipq40xx||TARGET_ipq806x) +kmod-usb-dwc3\n  KCONFIG:= CONFIG_USB_DWC3_QCOM\n  FILES:= $(LINUX_DIR)/drivers/usb/dwc3/dwc3-qcom.ko\n  AUTOLOAD:=$(call AutoLoad,53,dwc3-qcom,1)\n  $(call AddDepends/usb)\nendef\n\ndefine KernelPackage/usb-dwc3-qcom/description\n Some Qualcomm SoCs use DesignWare Core IP for USB2/3 functionality.\n This driver also handles Qscratch wrapper which is needed for\n peripheral mode support.\nendef\n\n\n$(eval $(call KernelPackage,usb-dwc3-qcom))\n\n\ndefine KernelPackage/usb-acm\n  TITLE:=Support for modems/isdn controllers\n  KCONFIG:=CONFIG_USB_ACM\n  FILES:=$(LINUX_DIR)/drivers/usb/class/cdc-acm.ko\n  AUTOLOAD:=$(call AutoProbe,cdc-acm)\n$(call AddDepends/usb)\nendef\n\ndefine KernelPackage/usb-acm/description\n Kernel support for USB ACM devices (modems/isdn controllers)\nendef\n\n$(eval $(call KernelPackage,usb-acm))\n\n\ndefine KernelPackage/usb-wdm\n  TITLE:=USB Wireless Device Management\n  KCONFIG:=CONFIG_USB_WDM\n  FILES:=$(LINUX_DIR)/drivers/usb/class/cdc-wdm.ko\n  AUTOLOAD:=$(call AutoProbe,cdc-wdm)\n$(call AddDepends/usb)\n$(call AddDepends/usb-net)\nendef\n\ndefine KernelPackage/usb-wdm/description\n USB Wireless Device Management support\nendef\n\n$(eval $(call KernelPackage,usb-wdm))\n\n\ndefine KernelPackage/usb-audio\n  TITLE:=Support for USB audio devices\n  KCONFIG:= \\\n\tCONFIG_USB_AUDIO \\\n\tCONFIG_SND_USB=y \\\n\tCONFIG_SND_USB_AUDIO\n  $(call AddDepends/usb)\n  $(call AddDepends/sound)\n  FILES:= \\\n\t$(LINUX_DIR)/sound/usb/snd-usbmidi-lib.ko \\\n\t$(LINUX_DIR)/sound/usb/snd-usb-audio.ko\n  AUTOLOAD:=$(call AutoProbe,snd-usbmidi-lib snd-usb-audio)\nendef\n\ndefine KernelPackage/usb-audio/description\n Kernel support for USB audio devices\nendef\n\n$(eval $(call KernelPackage,usb-audio))\n\n\ndefine KernelPackage/usb-printer\n  TITLE:=Support for printers\n  KCONFIG:=CONFIG_USB_PRINTER\n  FILES:=$(LINUX_DIR)/drivers/usb/class/usblp.ko\n  AUTOLOAD:=$(call AutoProbe,usblp)\n  $(call AddDepends/usb)\nendef\n\ndefine KernelPackage/usb-printer/description\n Kernel support for USB printers\nendef\n\n$(eval $(call KernelPackage,usb-printer))\n\n\ndefine KernelPackage/usb-serial\n  TITLE:=Support for USB-to-Serial converters\n  KCONFIG:=CONFIG_USB_SERIAL\n  FILES:=$(LINUX_DIR)/drivers/usb/serial/usbserial.ko\n  AUTOLOAD:=$(call AutoProbe,usbserial)\n  $(call AddDepends/usb)\nendef\n\ndefine KernelPackage/usb-serial/description\n Kernel support for USB-to-Serial converters\nendef\n\n$(eval $(call KernelPackage,usb-serial))\n\n\ndefine AddDepends/usb-serial\n  SUBMENU:=$(USB_MENU)\n  DEPENDS+=+kmod-usb-serial $(1)\nendef\n\n\ndefine KernelPackage/usb-serial-belkin\n  TITLE:=Support for Belkin devices\n  KCONFIG:=CONFIG_USB_SERIAL_BELKIN\n  FILES:=$(LINUX_DIR)/drivers/usb/serial/belkin_sa.ko\n  AUTOLOAD:=$(call AutoProbe,belkin_sa)\n  $(call AddDepends/usb-serial)\nendef\n\ndefine KernelPackage/usb-serial-belkin/description\n Kernel support for Belkin USB-to-Serial converters\nendef\n\n$(eval $(call KernelPackage,usb-serial-belkin))\n\n\ndefine KernelPackage/usb-serial-ch341\n  TITLE:=Support for CH341 devices\n  KCONFIG:=CONFIG_USB_SERIAL_CH341\n  FILES:=$(LINUX_DIR)/drivers/usb/serial/ch341.ko\n  AUTOLOAD:=$(call AutoProbe,ch341)\n  $(call AddDepends/usb-serial)\nendef\n\ndefine KernelPackage/usb-serial-ch341/description\n Kernel support for Winchiphead CH341 USB-to-Serial converters\nendef\n\n$(eval $(call KernelPackage,usb-serial-ch341))\n\n\ndefine KernelPackage/usb-serial-edgeport\n  TITLE:=Support for Digi Edgeport devices\n  KCONFIG:=CONFIG_USB_SERIAL_EDGEPORT\n  FILES:=$(LINUX_DIR)/drivers/usb/serial/io_edgeport.ko\n  AUTOLOAD:=$(call AutoProbe,io_edgeport)\n  $(call AddDepends/usb-serial)\n  DEPENDS+=+edgeport-firmware\nendef\n\ndefine KernelPackage/usb-serial-edgeport/description\n Kernel support for Inside Out Networks (Digi)\n\tEdgeport/4\n\tRapidport/4\n\tEdgeport/4t\n\tEdgeport/2\n\tEdgeport/4i\n\tEdgeport/2i\n\tEdgeport/421\n\tEdgeport/21\n\tEdgeport/8\n\tEdgeport/8 Dual\n\tEdgeport/2D8\n\tEdgeport/4D8\n\tEdgeport/8i\n\tEdgeport/2 DIN\n\tEdgeport/4 DIN\n\tEdgeport/16 Dual\nendef\n\n$(eval $(call KernelPackage,usb-serial-edgeport))\n\n\ndefine KernelPackage/usb-serial-ftdi\n  TITLE:=Support for FTDI devices\n  KCONFIG:=CONFIG_USB_SERIAL_FTDI_SIO\n  FILES:=$(LINUX_DIR)/drivers/usb/serial/ftdi_sio.ko\n  AUTOLOAD:=$(call AutoProbe,ftdi_sio)\n  $(call AddDepends/usb-serial)\nendef\n\ndefine KernelPackage/usb-serial-ftdi/description\n Kernel support for FTDI USB-to-Serial converters\nendef\n\n$(eval $(call KernelPackage,usb-serial-ftdi))\n\n\ndefine KernelPackage/usb-serial-garmin\n  TITLE:=Support for Garmin GPS devices\n  KCONFIG:=CONFIG_USB_SERIAL_GARMIN\n  FILES:=$(LINUX_DIR)/drivers/usb/serial/garmin_gps.ko\n  AUTOLOAD:=$(call AutoProbe,garmin_gps)\n  $(call AddDepends/usb-serial)\nendef\n\ndefine KernelPackage/usb-serial-garmin/description\n Should work with most Garmin GPS devices which have a native USB port.\nendef\n\n$(eval $(call KernelPackage,usb-serial-garmin))\n\n\ndefine KernelPackage/usb-serial-simple\n  TITLE:=USB Serial Simple (Motorola phone)\n  KCONFIG:=CONFIG_USB_SERIAL_SIMPLE\n  FILES:=$(LINUX_DIR)/drivers/usb/serial/usb-serial-simple.ko\n  AUTOLOAD:=$(call AutoProbe,usb-serial-simple)\n  $(call AddDepends/usb-serial)\nendef\n\ndefine KernelPackage/usb-serial-simple/description\n  Kernel support for \"very simple devices\".\n\nSpecifically, it supports:\n\t- Suunto ANT+ USB device.\n\t- Medtronic CareLink USB device (3.18)\n\t- Fundamental Software dongle.\n\t- Google USB serial devices (3.19)\n\t- HP4x calculators\n\t- a number of Motorola phones\n\t- Novatel Wireless GPS receivers (3.18)\n\t- Siemens USB/MPI adapter.\n\t- ViVOtech ViVOpay USB device.\n\t- Infineon Modem Flashloader USB interface\n\t- ZIO Motherboard USB serial interface\nendef\n\n$(eval $(call KernelPackage,usb-serial-simple))\n\n\ndefine KernelPackage/usb-serial-ti-usb\n  TITLE:=Support for TI USB 3410/5052\n  KCONFIG:=CONFIG_USB_SERIAL_TI\n  FILES:=$(LINUX_DIR)/drivers/usb/serial/ti_usb_3410_5052.ko\n  AUTOLOAD:=$(call AutoProbe,ti_usb_3410_5052)\n  $(call AddDepends/usb-serial)\nendef\n\ndefine KernelPackage/usb-serial-ti-usb/description\n Kernel support for TI USB 3410/5052 devices\nendef\n\n$(eval $(call KernelPackage,usb-serial-ti-usb))\n\n\ndefine KernelPackage/usb-serial-ipw\n  TITLE:=Support for IPWireless 3G devices\n  KCONFIG:=CONFIG_USB_SERIAL_IPW\n  FILES:=$(LINUX_DIR)/drivers/usb/serial/ipw.ko\n  AUTOLOAD:=$(call AutoProbe,ipw)\n  $(call AddDepends/usb-serial,+kmod-usb-serial-wwan)\nendef\n\n$(eval $(call KernelPackage,usb-serial-ipw))\n\n\ndefine KernelPackage/usb-serial-mct\n  TITLE:=Support for Magic Control Tech. devices\n  KCONFIG:=CONFIG_USB_SERIAL_MCT_U232\n  FILES:=$(LINUX_DIR)/drivers/usb/serial/mct_u232.ko\n  AUTOLOAD:=$(call AutoProbe,mct_u232)\n  $(call AddDepends/usb-serial)\nendef\n\ndefine KernelPackage/usb-serial-mct/description\n Kernel support for Magic Control Technology USB-to-Serial converters\nendef\n\n$(eval $(call KernelPackage,usb-serial-mct))\n\n\ndefine KernelPackage/usb-serial-mos7720\n  TITLE:=Support for Moschip MOS7720 devices\n  KCONFIG:=CONFIG_USB_SERIAL_MOS7720\n  FILES:=$(LINUX_DIR)/drivers/usb/serial/mos7720.ko\n  AUTOLOAD:=$(call AutoProbe,mos7720)\n  $(call AddDepends/usb-serial)\nendef\n\ndefine KernelPackage/usb-serial-mos7720/description\n Kernel support for Moschip MOS7720 USB-to-Serial converters\nendef\n\n$(eval $(call KernelPackage,usb-serial-mos7720))\n\n\ndefine KernelPackage/usb-serial-mos7840\n  TITLE:=Support for Moschip MOS7840 devices\n  KCONFIG:=CONFIG_USB_SERIAL_MOS7840\n  FILES:=$(LINUX_DIR)/drivers/usb/serial/mos7840.ko\n  AUTOLOAD:=$(call AutoProbe,mos7840)\n  $(call AddDepends/usb-serial)\nendef\n\ndefine KernelPackage/usb-serial-mos7840/description\n Kernel support for Moschip MOS7840 USB-to-Serial converters\nendef\n\n$(eval $(call KernelPackage,usb-serial-mos7840))\n\n\ndefine KernelPackage/usb-serial-pl2303\n  TITLE:=Support for Prolific PL2303 devices\n  KCONFIG:=CONFIG_USB_SERIAL_PL2303\n  FILES:=$(LINUX_DIR)/drivers/usb/serial/pl2303.ko\n  AUTOLOAD:=$(call AutoProbe,pl2303)\n  $(call AddDepends/usb-serial)\nendef\n\ndefine KernelPackage/usb-serial-pl2303/description\n Kernel support for Prolific PL2303 USB-to-Serial converters\nendef\n\n$(eval $(call KernelPackage,usb-serial-pl2303))\n\n\ndefine KernelPackage/usb-serial-cp210x\n  TITLE:=Support for Silicon Labs cp210x devices\n  KCONFIG:=CONFIG_USB_SERIAL_CP210X\n  FILES:=$(LINUX_DIR)/drivers/usb/serial/cp210x.ko\n  AUTOLOAD:=$(call AutoProbe,cp210x)\n  $(call AddDepends/usb-serial)\nendef\n\ndefine KernelPackage/usb-serial-cp210x/description\n Kernel support for Silicon Labs cp210x USB-to-Serial converters\nendef\n\n$(eval $(call KernelPackage,usb-serial-cp210x))\n\n\ndefine KernelPackage/usb-serial-ark3116\n  TITLE:=Support for ArkMicroChips ARK3116 devices\n  KCONFIG:=CONFIG_USB_SERIAL_ARK3116\n  FILES:=$(LINUX_DIR)/drivers/usb/serial/ark3116.ko\n  AUTOLOAD:=$(call AutoProbe,ark3116)\n  $(call AddDepends/usb-serial)\nendef\n\ndefine KernelPackage/usb-serial-ark3116/description\n Kernel support for ArkMicroChips ARK3116 USB-to-Serial converters\nendef\n\n$(eval $(call KernelPackage,usb-serial-ark3116))\n\n\ndefine KernelPackage/usb-serial-oti6858\n  TITLE:=Support for Ours Technology OTI6858 devices\n  KCONFIG:=CONFIG_USB_SERIAL_OTI6858\n  FILES:=$(LINUX_DIR)/drivers/usb/serial/oti6858.ko\n  AUTOLOAD:=$(call AutoProbe,oti6858)\n  $(call AddDepends/usb-serial)\nendef\n\ndefine KernelPackage/usb-serial-oti6858/description\n Kernel support for Ours Technology OTI6858 USB-to-Serial converters\nendef\n\n$(eval $(call KernelPackage,usb-serial-oti6858))\n\n\ndefine KernelPackage/usb-serial-sierrawireless\n  TITLE:=Support for Sierra Wireless devices\n  KCONFIG:=CONFIG_USB_SERIAL_SIERRAWIRELESS\n  FILES:=$(LINUX_DIR)/drivers/usb/serial/sierra.ko\n  AUTOLOAD:=$(call AutoProbe,sierra)\n  $(call AddDepends/usb-serial)\nendef\n\ndefine KernelPackage/usb-serial-sierrawireless/description\n Kernel support for Sierra Wireless devices\nendef\n\n$(eval $(call KernelPackage,usb-serial-sierrawireless))\n\n\ndefine KernelPackage/usb-serial-visor\n  TITLE:=Support for Handspring Visor devices\n  KCONFIG:=CONFIG_USB_SERIAL_VISOR\n  FILES:=$(LINUX_DIR)/drivers/usb/serial/visor.ko\n  AUTOLOAD:=$(call AutoProbe,visor)\n  $(call AddDepends/usb-serial)\nendef\n\ndefine KernelPackage/usb-serial-visor/description\n Kernel support for Handspring Visor PDAs\nendef\n\n$(eval $(call KernelPackage,usb-serial-visor))\n\n\ndefine KernelPackage/usb-serial-cypress-m8\n  TITLE:=Support for CypressM8 USB-Serial\n  KCONFIG:=CONFIG_USB_SERIAL_CYPRESS_M8\n  FILES:=$(LINUX_DIR)/drivers/usb/serial/cypress_m8.ko\n  AUTOLOAD:=$(call AutoProbe,cypress_m8)\n  $(call AddDepends/usb-serial)\nendef\n\ndefine KernelPackage/usb-serial-cypress-m8/description\n Kernel support for devices with Cypress M8 USB to Serial chip\n (for example, the Delorme Earthmate LT-20 GPS)\n Supported microcontrollers in the CY4601 family are:\n CY7C63741 CY7C63742 CY7C63743 CY7C64013\nendef\n\n$(eval $(call KernelPackage,usb-serial-cypress-m8))\n\n\ndefine KernelPackage/usb-serial-keyspan\n  TITLE:=Support for Keyspan USB-to-Serial devices\n  KCONFIG:= \\\n\tCONFIG_USB_SERIAL_KEYSPAN \\\n\tCONFIG_USB_SERIAL_KEYSPAN_USA28 \\\n\tCONFIG_USB_SERIAL_KEYSPAN_USA28X \\\n\tCONFIG_USB_SERIAL_KEYSPAN_USA28XA \\\n\tCONFIG_USB_SERIAL_KEYSPAN_USA28XB \\\n\tCONFIG_USB_SERIAL_KEYSPAN_USA19 \\\n\tCONFIG_USB_SERIAL_KEYSPAN_USA18X \\\n\tCONFIG_USB_SERIAL_KEYSPAN_USA19W \\\n\tCONFIG_USB_SERIAL_KEYSPAN_USA19QW \\\n\tCONFIG_USB_SERIAL_KEYSPAN_USA19QI \\\n\tCONFIG_USB_SERIAL_KEYSPAN_MPR \\\n\tCONFIG_USB_SERIAL_KEYSPAN_USA49W \\\n\tCONFIG_USB_SERIAL_KEYSPAN_USA49WLC\n  FILES:= \\\n\t$(LINUX_DIR)/drivers/usb/serial/keyspan.ko \\\n\t$(wildcard $(LINUX_DIR)/drivers/usb/misc/ezusb.ko)\n  AUTOLOAD:=$(call AutoProbe,ezusb keyspan)\n  $(call AddDepends/usb-serial)\nendef\n\ndefine KernelPackage/usb-serial-keyspan/description\n Kernel support for Keyspan USB-to-Serial devices\nendef\n\n$(eval $(call KernelPackage,usb-serial-keyspan))\n\n\ndefine KernelPackage/usb-serial-wwan\n  TITLE:=Support for GSM and CDMA modems\n  KCONFIG:=CONFIG_USB_SERIAL_WWAN\n  FILES:=$(LINUX_DIR)/drivers/usb/serial/usb_wwan.ko\n  HIDDEN:=1\n  AUTOLOAD:=$(call AutoProbe,usb_wwan)\n  $(call AddDepends/usb-serial)\nendef\n\ndefine KernelPackage/usb-serial-wwan/description\n Kernel support for USB GSM and CDMA modems\nendef\n\n$(eval $(call KernelPackage,usb-serial-wwan))\n\n\ndefine KernelPackage/usb-serial-option\n  TITLE:=Support for Option HSDPA modems\n  KCONFIG:=CONFIG_USB_SERIAL_OPTION\n  FILES:=$(LINUX_DIR)/drivers/usb/serial/option.ko\n  AUTOLOAD:=$(call AutoProbe,option)\n  $(call AddDepends/usb-serial,+kmod-usb-serial-wwan)\nendef\n\ndefine KernelPackage/usb-serial-option/description\n Kernel support for Option HSDPA modems\nendef\n\n$(eval $(call KernelPackage,usb-serial-option))\n\n\ndefine KernelPackage/usb-serial-qualcomm\n  TITLE:=Support for Qualcomm USB serial\n  KCONFIG:=CONFIG_USB_SERIAL_QUALCOMM\n  FILES:=$(LINUX_DIR)/drivers/usb/serial/qcserial.ko\n  AUTOLOAD:=$(call AutoProbe,qcserial)\n  $(call AddDepends/usb-serial,+kmod-usb-serial-wwan)\nendef\n\ndefine KernelPackage/usb-serial-qualcomm/description\n Kernel support for Qualcomm USB Serial devices (Gobi)\nendef\n\n$(eval $(call KernelPackage,usb-serial-qualcomm))\n\n\ndefine KernelPackage/usb-storage\n  TITLE:=USB Storage support\n  DEPENDS:= +kmod-scsi-core\n  KCONFIG:=CONFIG_USB_STORAGE\n  FILES:=$(LINUX_DIR)/drivers/usb/storage/usb-storage.ko\n  AUTOLOAD:=$(call AutoProbe,usb-storage,1)\n  $(call AddDepends/usb)\nendef\n\ndefine KernelPackage/usb-storage/description\n Kernel support for USB Mass Storage devices\nendef\n\n$(eval $(call KernelPackage,usb-storage))\n\n\ndefine KernelPackage/usb-storage-extras\n  SUBMENU:=$(USB_MENU)\n  TITLE:=Extra drivers for usb-storage\n  DEPENDS:=+kmod-usb-storage\n  KCONFIG:= \\\n\tCONFIG_USB_STORAGE_ALAUDA \\\n\tCONFIG_USB_STORAGE_CYPRESS_ATACB \\\n\tCONFIG_USB_STORAGE_DATAFAB \\\n\tCONFIG_USB_STORAGE_FREECOM \\\n\tCONFIG_USB_STORAGE_ISD200 \\\n\tCONFIG_USB_STORAGE_JUMPSHOT \\\n\tCONFIG_USB_STORAGE_KARMA \\\n\tCONFIG_USB_STORAGE_SDDR09 \\\n\tCONFIG_USB_STORAGE_SDDR55 \\\n\tCONFIG_USB_STORAGE_USBAT\n  FILES:= \\\n\t$(LINUX_DIR)/drivers/usb/storage/ums-alauda.ko \\\n\t$(LINUX_DIR)/drivers/usb/storage/ums-cypress.ko \\\n\t$(LINUX_DIR)/drivers/usb/storage/ums-datafab.ko \\\n\t$(LINUX_DIR)/drivers/usb/storage/ums-freecom.ko \\\n\t$(LINUX_DIR)/drivers/usb/storage/ums-isd200.ko \\\n\t$(LINUX_DIR)/drivers/usb/storage/ums-jumpshot.ko \\\n\t$(LINUX_DIR)/drivers/usb/storage/ums-karma.ko \\\n\t$(LINUX_DIR)/drivers/usb/storage/ums-sddr09.ko \\\n\t$(LINUX_DIR)/drivers/usb/storage/ums-sddr55.ko \\\n\t$(LINUX_DIR)/drivers/usb/storage/ums-usbat.ko\n  AUTOLOAD:=$(call AutoProbe,ums-alauda ums-cypress ums-datafab \\\n\t\t\t\tums-freecom ums-isd200 ums-jumpshot \\\n\t\t\t\tums-karma ums-sddr09 ums-sddr55 ums-usbat)\nendef\n\ndefine KernelPackage/usb-storage-extras/description\n Say Y here if you want to have some more drivers,\n such as for SmartMedia card readers\nendef\n\n$(eval $(call KernelPackage,usb-storage-extras))\n\n\ndefine KernelPackage/usb-storage-uas\n  SUBMENU:=$(USB_MENU)\n  TITLE:=USB Attached SCSI (UASP) support\n  DEPENDS:=+kmod-usb-storage\n  KCONFIG:=CONFIG_USB_UAS\n  FILES:=$(LINUX_DIR)/drivers/usb/storage/uas.ko\n  AUTOLOAD:=$(call AutoProbe,uas,1)\nendef\n\ndefine KernelPackage/usb-storage-uas/description\n Say Y here if you want to include support for\n USB Attached SCSI (UAS/UASP), a higher\n performance protocol available on many\n newer USB 3.0 storage devices\nendef\n\n$(eval $(call KernelPackage,usb-storage-uas))\n\n\ndefine KernelPackage/usb-atm\n  TITLE:=Support for ATM on USB bus\n  DEPENDS:=+kmod-atm\n  KCONFIG:=CONFIG_USB_ATM\n  FILES:=$(LINUX_DIR)/drivers/usb/atm/usbatm.ko\n  AUTOLOAD:=$(call AutoProbe,usbatm)\n  $(call AddDepends/usb)\nendef\n\ndefine KernelPackage/usb-atm/description\n Kernel support for USB DSL modems\nendef\n\n$(eval $(call KernelPackage,usb-atm))\n\n\ndefine AddDepends/usb-atm\n  SUBMENU:=$(USB_MENU)\n  DEPENDS+=kmod-usb-atm $(1)\nendef\n\n\ndefine KernelPackage/usb-atm-speedtouch\n  TITLE:=SpeedTouch USB ADSL modems support\n  KCONFIG:=CONFIG_USB_SPEEDTOUCH\n  FILES:=$(LINUX_DIR)/drivers/usb/atm/speedtch.ko\n  AUTOLOAD:=$(call AutoProbe,speedtch)\n  $(call AddDepends/usb-atm)\nendef\n\ndefine KernelPackage/usb-atm-speedtouch/description\n Kernel support for SpeedTouch USB ADSL modems\nendef\n\n$(eval $(call KernelPackage,usb-atm-speedtouch))\n\n\ndefine KernelPackage/usb-atm-ueagle\n  TITLE:=Eagle 8051 based USB ADSL modems support\n  FILES:=$(LINUX_DIR)/drivers/usb/atm/ueagle-atm.ko\n  KCONFIG:=CONFIG_USB_UEAGLEATM\n  AUTOLOAD:=$(call AutoProbe,ueagle-atm)\n  $(call AddDepends/usb-atm)\nendef\n\ndefine KernelPackage/usb-atm-ueagle/description\n Kernel support for Eagle 8051 based USB ADSL modems\nendef\n\n$(eval $(call KernelPackage,usb-atm-ueagle))\n\n\ndefine KernelPackage/usb-atm-cxacru\n  TITLE:=cxacru\n  FILES:=$(LINUX_DIR)/drivers/usb/atm/cxacru.ko\n  KCONFIG:=CONFIG_USB_CXACRU\n  AUTOLOAD:=$(call AutoProbe,cxacru)\n  $(call AddDepends/usb-atm)\nendef\n\ndefine KernelPackage/usb-atm-cxacru/description\n Kernel support for cxacru based USB ADSL modems\nendef\n\n$(eval $(call KernelPackage,usb-atm-cxacru))\n\n\ndefine KernelPackage/usb-net\n  TITLE:=Kernel modules for USB-to-Ethernet convertors\n  DEPENDS:=+kmod-mii\n  KCONFIG:=CONFIG_USB_USBNET \\\n\tCONFIG_USB_NET_DRIVERS\n  AUTOLOAD:=$(call AutoProbe,usbnet)\n  FILES:=$(LINUX_DIR)/drivers/$(USBNET_DIR)/usbnet.ko\n  $(call AddDepends/usb)\nendef\n\ndefine KernelPackage/usb-net/description\n Kernel modules for USB-to-Ethernet convertors\nendef\n\n$(eval $(call KernelPackage,usb-net))\n\n\ndefine AddDepends/usb-net\n  SUBMENU:=$(USB_MENU)\n  DEPENDS+=+kmod-usb-net $(1)\nendef\n\n\ndefine KernelPackage/usb-net-aqc111\n  TITLE:=Support for USB-to-Ethernet Aquantia AQtion 5/2.5GbE\n  KCONFIG:=CONFIG_USB_NET_AQC111\n  FILES:=$(LINUX_DIR)/drivers/$(USBNET_DIR)/aqc111.ko\n  AUTOLOAD:=$(call AutoProbe,aqc111)\n  $(call AddDepends/usb-net)\nendef\n\ndefine KernelPackage/usb-net-aqc111/description\n Support for USB-to-Ethernet Aquantia AQtion 5/2.5GbE\nendef\n\n$(eval $(call KernelPackage,usb-net-aqc111))\n\n\ndefine KernelPackage/usb-net-asix\n  TITLE:=Kernel module for USB-to-Ethernet Asix convertors\n  DEPENDS:=+kmod-libphy +LINUX_5_15:kmod-net-selftests +LINUX_5_15:kmod-mdio-devres\n  KCONFIG:=CONFIG_USB_NET_AX8817X\n  FILES:=$(LINUX_DIR)/drivers/$(USBNET_DIR)/asix.ko\n  AUTOLOAD:=$(call AutoProbe,asix)\n  $(call AddDepends/usb-net)\nendef\n\ndefine KernelPackage/usb-net-asix/description\n Kernel module for USB-to-Ethernet Asix convertors\nendef\n\n$(eval $(call KernelPackage,usb-net-asix))\n\n\ndefine KernelPackage/usb-net-asix-ax88179\n  TITLE:=Kernel module for USB-to-Gigabit-Ethernet Asix convertors\n  DEPENDS:=+kmod-libphy\n  KCONFIG:=CONFIG_USB_NET_AX88179_178A\n  FILES:=$(LINUX_DIR)/drivers/$(USBNET_DIR)/ax88179_178a.ko\n  AUTOLOAD:=$(call AutoProbe,ax88179_178a)\n  $(call AddDepends/usb-net)\nendef\n\ndefine KernelPackage/usb-net-asix-ax88179/description\n Kernel module for USB-to-Ethernet ASIX AX88179 based USB 3.0/2.0\n to Gigabit Ethernet adapters.\nendef\n\n$(eval $(call KernelPackage,usb-net-asix-ax88179))\n\n\ndefine KernelPackage/usb-net-hso\n  TITLE:=Kernel module for Option USB High Speed Mobile Devices\n  KCONFIG:=CONFIG_USB_HSO\n  FILES:= \\\n\t$(LINUX_DIR)/drivers/$(USBNET_DIR)/hso.ko\n  AUTOLOAD:=$(call AutoProbe,hso)\n  $(call AddDepends/usb-net)\n  $(call AddDepends/rfkill)\nendef\n\ndefine KernelPackage/usb-net-hso/description\n Kernel module for Option USB High Speed Mobile Devices\nendef\n\n$(eval $(call KernelPackage,usb-net-hso))\n\n\ndefine KernelPackage/usb-net-kaweth\n  TITLE:=Kernel module for USB-to-Ethernet Kaweth convertors\n  KCONFIG:=CONFIG_USB_KAWETH\n  FILES:=$(LINUX_DIR)/drivers/$(USBNET_DIR)/kaweth.ko\n  AUTOLOAD:=$(call AutoProbe,kaweth)\n  $(call AddDepends/usb-net)\nendef\n\ndefine KernelPackage/usb-net-kaweth/description\n Kernel module for USB-to-Ethernet Kaweth convertors\nendef\n\n$(eval $(call KernelPackage,usb-net-kaweth))\n\n\ndefine KernelPackage/usb-net-lan78xx\n  TITLE:=USB-To-Ethernet Microchip LAN78XX convertors\n  DEPENDS:=+kmod-fixed-phy +kmod-phy-microchip +PACKAGE_kmod-of-mdio:kmod-of-mdio\n  KCONFIG:=CONFIG_USB_LAN78XX\n  FILES:=$(LINUX_DIR)/drivers/$(USBNET_DIR)/lan78xx.ko\n  AUTOLOAD:=$(call AutoProbe,lan78xx)\n  $(call AddDepends/usb-net)\nendef\n\ndefine KernelPackage/usb-net-lan78xx/description\n Kernel module for Microchip LAN78XX based USB 2 & USB 3\n 10/100/1000 Ethernet adapters.\nendef\n\n$(eval $(call KernelPackage,usb-net-lan78xx))\n\n\ndefine KernelPackage/usb-net-pegasus\n  TITLE:=Kernel module for USB-to-Ethernet Pegasus convertors\n  KCONFIG:=CONFIG_USB_PEGASUS\n  FILES:=$(LINUX_DIR)/drivers/$(USBNET_DIR)/pegasus.ko\n  AUTOLOAD:=$(call AutoProbe,pegasus)\n  $(call AddDepends/usb-net)\nendef\n\ndefine KernelPackage/usb-net-pegasus/description\n Kernel module for USB-to-Ethernet Pegasus convertors\nendef\n\n$(eval $(call KernelPackage,usb-net-pegasus))\n\n\ndefine KernelPackage/usb-net-mcs7830\n  TITLE:=Kernel module for USB-to-Ethernet MCS7830 convertors\n  KCONFIG:=CONFIG_USB_NET_MCS7830\n  FILES:=$(LINUX_DIR)/drivers/$(USBNET_DIR)/mcs7830.ko\n  AUTOLOAD:=$(call AutoProbe,mcs7830)\n  $(call AddDepends/usb-net)\nendef\n\ndefine KernelPackage/usb-net-mcs7830/description\n Kernel module for USB-to-Ethernet MCS7830 convertors\nendef\n\n$(eval $(call KernelPackage,usb-net-mcs7830))\n\n\ndefine KernelPackage/usb-net-smsc75xx\n  TITLE:=SMSC LAN75XX based USB 2.0 Gigabit ethernet devices\n  DEPENDS:=+!LINUX_5_4:kmod-libphy\n  KCONFIG:=CONFIG_USB_NET_SMSC75XX\n  FILES:=$(LINUX_DIR)/drivers/$(USBNET_DIR)/smsc75xx.ko\n  AUTOLOAD:=$(call AutoProbe,smsc75xx)\n  $(call AddDepends/usb-net, +kmod-lib-crc16)\nendef\n\ndefine KernelPackage/usb-net-smsc75xx/description\n Kernel module for SMSC LAN75XX based devices\nendef\n\n$(eval $(call KernelPackage,usb-net-smsc75xx))\n\n\ndefine KernelPackage/usb-net-smsc95xx\n  TITLE:=SMSC LAN95XX based USB 2.0 10/100 ethernet devices\n  DEPENDS:=+(LINUX_5_10||LINUX_5_15):kmod-libphy\n  KCONFIG:=CONFIG_USB_NET_SMSC95XX\n  FILES:=$(LINUX_DIR)/drivers/$(USBNET_DIR)/smsc95xx.ko\n  AUTOLOAD:=$(call AutoProbe,smsc95xx)\n  $(call AddDepends/usb-net, +kmod-lib-crc16)\nendef\n\ndefine KernelPackage/usb-net-smsc95xx/description\n Kernel module for SMSC LAN95XX based devices\nendef\n\n$(eval $(call KernelPackage,usb-net-smsc95xx))\n\n\ndefine KernelPackage/usb-net-dm9601-ether\n  TITLE:=Support for DM9601 ethernet connections\n  KCONFIG:=CONFIG_USB_NET_DM9601\n  FILES:=$(LINUX_DIR)/drivers/$(USBNET_DIR)/dm9601.ko\n  AUTOLOAD:=$(call AutoProbe,dm9601)\n  $(call AddDepends/usb-net)\nendef\n\ndefine KernelPackage/usb-net-dm9601-ether/description\n Kernel support for USB DM9601 devices\nendef\n\n$(eval $(call KernelPackage,usb-net-dm9601-ether))\n\ndefine KernelPackage/usb-net-cdc-ether\n  TITLE:=Support for cdc ethernet connections\n  KCONFIG:=CONFIG_USB_NET_CDCETHER\n  FILES:=$(LINUX_DIR)/drivers/$(USBNET_DIR)/cdc_ether.ko\n  AUTOLOAD:=$(call AutoProbe,cdc_ether)\n  $(call AddDepends/usb-net)\nendef\n\ndefine KernelPackage/usb-net-cdc-ether/description\n Kernel support for USB CDC Ethernet devices\nendef\n\n$(eval $(call KernelPackage,usb-net-cdc-ether))\n\n\ndefine KernelPackage/usb-net-cdc-eem\n  TITLE:=Support for CDC EEM connections\n  KCONFIG:=CONFIG_USB_NET_CDC_EEM\n  FILES:=$(LINUX_DIR)/drivers/$(USBNET_DIR)/cdc_eem.ko\n  AUTOLOAD:=$(call AutoProbe,cdc_eem)\n  $(call AddDepends/usb-net)\nendef\n\ndefine KernelPackage/usb-net-cdc-eem/description\n Kernel support for USB CDC EEM\nendef\n\n$(eval $(call KernelPackage,usb-net-cdc-eem))\n\n\ndefine KernelPackage/usb-net-cdc-subset\n  TITLE:=Support for CDC Ethernet subset connections\n  KCONFIG:= \\\n\tCONFIG_USB_NET_CDC_SUBSET \\\n\tCONFIG_USB_ARMLINUX\n  FILES:=$(LINUX_DIR)/drivers/$(USBNET_DIR)/cdc_subset.ko\n  AUTOLOAD:=$(call AutoProbe,cdc_subset)\n  $(call AddDepends/usb-net)\nendef\n\ndefine KernelPackage/usb-net-cdc-subset/description\n Kernel support for Simple USB Network Links (CDC Ethernet subset)\nendef\n\n$(eval $(call KernelPackage,usb-net-cdc-subset))\n\n\ndefine KernelPackage/usb-net-qmi-wwan\n  TITLE:=QMI WWAN driver\n  KCONFIG:=CONFIG_USB_NET_QMI_WWAN\n  FILES:= $(LINUX_DIR)/drivers/$(USBNET_DIR)/qmi_wwan.ko\n  AUTOLOAD:=$(call AutoProbe,qmi_wwan)\n  $(call AddDepends/usb-net,+kmod-usb-wdm)\nendef\n\ndefine KernelPackage/usb-net-qmi-wwan/description\n QMI WWAN driver for Qualcomm MSM based 3G and LTE modems\nendef\n\n$(eval $(call KernelPackage,usb-net-qmi-wwan))\n\n\ndefine KernelPackage/usb-net-rtl8150\n  TITLE:=Kernel module for USB-to-Ethernet Realtek convertors\n  KCONFIG:=CONFIG_USB_RTL8150\n  FILES:=$(LINUX_DIR)/drivers/$(USBNET_DIR)/rtl8150.ko\n  AUTOLOAD:=$(call AutoProbe,rtl8150)\n  $(call AddDepends/usb-net)\nendef\n\ndefine KernelPackage/usb-net-rtl8150/description\n Kernel module for USB-to-Ethernet Realtek 8150 convertors\nendef\n\n$(eval $(call KernelPackage,usb-net-rtl8150))\n\n\ndefine KernelPackage/usb-net-rtl8152\n  TITLE:=Kernel module for USB-to-Ethernet Realtek convertors\n  DEPENDS:=+r8152-firmware +kmod-crypto-sha256 +kmod-usb-net-cdc-ncm\n  KCONFIG:=CONFIG_USB_RTL8152\n  FILES:=$(LINUX_DIR)/drivers/$(USBNET_DIR)/r8152.ko\n  AUTOLOAD:=$(call AutoProbe,r8152)\n  $(call AddDepends/usb-net, +LINUX_5_10:kmod-crypto-hash)\nendef\n\ndefine KernelPackage/usb-net-rtl8152/description\n Kernel module for USB-to-Ethernet Realtek 8152 USB2.0/3.0 convertors\nendef\n\n$(eval $(call KernelPackage,usb-net-rtl8152))\n\n\ndefine KernelPackage/usb-net-sr9700\n  TITLE:=Support for CoreChip SR9700 ethernet devices\n  KCONFIG:=CONFIG_USB_NET_SR9700\n  FILES:=$(LINUX_DIR)/drivers/$(USBNET_DIR)/sr9700.ko\n  AUTOLOAD:=$(call AutoProbe,sr9700)\n  $(call AddDepends/usb-net)\nendef\n\ndefine KernelPackage/usb-net-sr9700/description\n Kernel module for CoreChip-sz SR9700 based USB 1.1 10/100 ethernet devices\nendef\n\n$(eval $(call KernelPackage,usb-net-sr9700))\n\n\ndefine KernelPackage/usb-net-rndis\n  TITLE:=Support for RNDIS connections\n  KCONFIG:=CONFIG_USB_NET_RNDIS_HOST\n  FILES:= $(LINUX_DIR)/drivers/$(USBNET_DIR)/rndis_host.ko\n  AUTOLOAD:=$(call AutoProbe,rndis_host)\n  $(call AddDepends/usb-net,+kmod-usb-net-cdc-ether)\nendef\n\ndefine KernelPackage/usb-net-rndis/description\n Kernel support for RNDIS connections\nendef\n\n$(eval $(call KernelPackage,usb-net-rndis))\n\n\ndefine KernelPackage/usb-net-cdc-mbim\n  SUBMENU:=$(USB_MENU)\n  TITLE:=Kernel module for MBIM Devices\n  KCONFIG:=CONFIG_USB_NET_CDC_MBIM\n  FILES:= \\\n   $(LINUX_DIR)/drivers/$(USBNET_DIR)/cdc_mbim.ko\n  AUTOLOAD:=$(call AutoProbe,cdc_mbim)\n  $(call AddDepends/usb-net,+kmod-usb-wdm +kmod-usb-net-cdc-ncm)\nendef\n\ndefine KernelPackage/usb-net-cdc-mbim/description\n Kernel module for CDC MBIM (Mobile Broadband Interface Model) devices\nendef\n\n$(eval $(call KernelPackage,usb-net-cdc-mbim))\n\n\ndefine KernelPackage/usb-net-cdc-ncm\n  TITLE:=Support for CDC NCM connections\n  KCONFIG:=CONFIG_USB_NET_CDC_NCM\n  FILES:= $(LINUX_DIR)/drivers/$(USBNET_DIR)/cdc_ncm.ko\n  AUTOLOAD:=$(call AutoProbe,cdc_ncm)\n  $(call AddDepends/usb-net,+!LINUX_5_4:kmod-usb-net-cdc-ether)\nendef\n\ndefine KernelPackage/usb-net-cdc-ncm/description\n Kernel support for CDC NCM connections\nendef\n\n$(eval $(call KernelPackage,usb-net-cdc-ncm))\n\n\ndefine KernelPackage/usb-net-huawei-cdc-ncm\n  TITLE:=Support for Huawei CDC NCM connections\n  KCONFIG:=CONFIG_USB_NET_HUAWEI_CDC_NCM\n  FILES:= $(LINUX_DIR)/drivers/$(USBNET_DIR)/huawei_cdc_ncm.ko\n  AUTOLOAD:=$(call AutoProbe,huawei_cdc_ncm)\n  $(call AddDepends/usb-net,+kmod-usb-net-cdc-ncm +kmod-usb-wdm)\nendef\n\ndefine KernelPackage/usb-net-huawei-cdc-ncm/description\n Kernel support for Huawei CDC NCM connections\nendef\n\n$(eval $(call KernelPackage,usb-net-huawei-cdc-ncm))\n\n\ndefine KernelPackage/usb-net-sierrawireless\n  TITLE:=Support for Sierra Wireless devices\n  KCONFIG:=CONFIG_USB_SIERRA_NET\n  FILES:=$(LINUX_DIR)/drivers/net/usb/sierra_net.ko\n  AUTOLOAD:=$(call AutoProbe,sierra_net)\n  $(call AddDepends/usb-net)\nendef\n\ndefine KernelPackage/usb-net-sierrawireless/description\n Kernel support for Sierra Wireless devices\nendef\n\n$(eval $(call KernelPackage,usb-net-sierrawireless))\n\n\ndefine KernelPackage/usb-net-ipheth\n  TITLE:=Apple iPhone USB Ethernet driver\n  KCONFIG:=CONFIG_USB_IPHETH\n  FILES:=$(LINUX_DIR)/drivers/net/usb/ipheth.ko\n  AUTOLOAD:=$(call AutoProbe,ipheth)\n  $(call AddDepends/usb-net)\nendef\n\ndefine KernelPackage/usb-net-ipheth/description\n Kernel support for Apple iPhone USB Ethernet driver\nendef\n\n$(eval $(call KernelPackage,usb-net-ipheth))\n\n\ndefine KernelPackage/usb-net-kalmia\n  TITLE:=Samsung Kalmia based LTE USB modem\n  KCONFIG:=CONFIG_USB_NET_KALMIA\n  FILES:=$(LINUX_DIR)/drivers/net/usb/kalmia.ko\n  AUTOLOAD:=$(call AutoProbe,kalmia)\n  $(call AddDepends/usb-net)\nendef\n\ndefine KernelPackage/usb-net-kalmia/description\n Kernel support for Samsung Kalmia based LTE USB modem\nendef\n\n$(eval $(call KernelPackage,usb-net-kalmia))\n\ndefine KernelPackage/usb-net-pl\n  TITLE:=Prolific PL-2301/2302/25A1 based cables\n  KCONFIG:=CONFIG_USB_NET_PLUSB\n  FILES:=$(LINUX_DIR)/drivers/net/usb/plusb.ko\n  AUTOLOAD:=$(call AutoProbe,plusb)\n  $(call AddDepends/usb-net)\nendef\n\ndefine KernelPackage/usb-net-pl/description\n Kernel support for Prolific PL-2301/2302/25A1 based cables\nendef\n\n$(eval $(call KernelPackage,usb-net-pl))\n\ndefine KernelPackage/usb-hid\n  TITLE:=Support for USB Human Input Devices\n  KCONFIG:=CONFIG_HID_SUPPORT=y CONFIG_USB_HID CONFIG_USB_HIDDEV=y\n  DEPENDS:=+kmod-hid +kmod-hid-generic +kmod-input-evdev\n  FILES:=$(LINUX_DIR)/drivers/$(USBHID_DIR)/usbhid.ko\n  AUTOLOAD:=$(call AutoProbe,usbhid)\n  $(call AddDepends/usb)\nendef\n\ndefine KernelPackage/usb-hid/description\n Kernel support for USB HID devices such as keyboards and mice\nendef\n\n$(eval $(call KernelPackage,usb-hid))\n\n\ndefine KernelPackage/usb-hid-cp2112\n  SUBMENU:=$(USB_MENU)\n  TITLE:=Silicon Labs CP2112 HID USB to SMBus Master Bridge\n  KCONFIG:=CONFIG_GPIOLIB=y CONFIG_HID_CP2112\n  DEPENDS:=+kmod-usb-hid +kmod-i2c-core\n  FILES:=$(LINUX_DIR)/drivers/hid/hid-cp2112.ko\n  AUTOLOAD:=$(call AutoProbe,hid-cp2112)\nendef\n\ndefine KernelPackage/usb-hid-cp2112/description\n HID device driver which registers as an i2c adapter and gpiochip to expose\n these functions of the CP2112.\nendef\n\n$(eval $(call KernelPackage,usb-hid-cp2112))\n\n\ndefine KernelPackage/usb-yealink\n  TITLE:=USB Yealink VOIP phone\n  DEPENDS:=+kmod-input-evdev\n  KCONFIG:=CONFIG_USB_YEALINK CONFIG_INPUT_YEALINK CONFIG_INPUT=m CONFIG_INPUT_MISC=y\n  FILES:=$(LINUX_DIR)/drivers/$(USBINPUT_DIR)/yealink.ko\n  AUTOLOAD:=$(call AutoProbe,yealink)\n  $(call AddDepends/usb)\nendef\n\ndefine KernelPackage/usb-yealink/description\n Kernel support for Yealink VOIP phone\nendef\n\n$(eval $(call KernelPackage,usb-yealink))\n\n\ndefine KernelPackage/usb-cm109\n  TITLE:=Support for CM109 device\n  DEPENDS:=+kmod-input-evdev\n  KCONFIG:=CONFIG_USB_CM109 CONFIG_INPUT_CM109 CONFIG_INPUT=m CONFIG_INPUT_MISC=y\n  FILES:=$(LINUX_DIR)/drivers/$(USBINPUT_DIR)/cm109.ko\n  AUTOLOAD:=$(call AutoProbe,cm109)\n  $(call AddDepends/usb)\nendef\n\ndefine KernelPackage/usb-cm109/description\n Kernel support for CM109 VOIP phone\nendef\n\n$(eval $(call KernelPackage,usb-cm109))\n\n\ndefine KernelPackage/usb-test\n  TITLE:=USB Testing Driver\n  DEPENDS:=@DEVEL\n  KCONFIG:=CONFIG_USB_TEST\n  FILES:=$(LINUX_DIR)/drivers/usb/misc/usbtest.ko\n  $(call AddDepends/usb)\nendef\n\ndefine KernelPackage/usb-test/description\n Kernel support for testing USB Host Controller software\nendef\n\n$(eval $(call KernelPackage,usb-test))\n\n\ndefine KernelPackage/usbip\n  TITLE := USB-over-IP kernel support\n  KCONFIG:= \\\n\tCONFIG_USBIP_CORE \\\n\tCONFIG_USBIP_DEBUG=n\n  FILES:=$(LINUX_DIR)/drivers/usb/usbip/usbip-core.ko\n  AUTOLOAD:=$(call AutoProbe,usbip-core)\n  $(call AddDepends/usb)\nendef\n\n$(eval $(call KernelPackage,usbip))\n\n\ndefine KernelPackage/usbip-client\n  TITLE := USB-over-IP client driver\n  DEPENDS := +kmod-usbip\n  KCONFIG := CONFIG_USBIP_VHCI_HCD\n  FILES :=$(LINUX_DIR)/drivers/usb/usbip/vhci-hcd.ko\n  AUTOLOAD := $(call AutoProbe,vhci-hcd)\n  $(call AddDepends/usb)\nendef\n\n$(eval $(call KernelPackage,usbip-client))\n\n\ndefine KernelPackage/usbip-server\n$(call KernelPackage/usbip/Default)\n  TITLE := USB-over-IP host driver\n  DEPENDS := +kmod-usbip\n  KCONFIG := CONFIG_USBIP_HOST\n  FILES :=$(LINUX_DIR)/drivers/usb/usbip/usbip-host.ko\n  AUTOLOAD := $(call AutoProbe,usbip-host)\n  $(call AddDepends/usb)\nendef\n\n$(eval $(call KernelPackage,usbip-server))\n\ndefine KernelPackage/usb-chipidea\n  TITLE:=Host and device support for Chipidea controllers\n  DEPENDS:=+USB_GADGET_SUPPORT:kmod-usb-gadget @TARGET_ath79 +kmod-usb-ehci +kmod-usb-phy-nop +kmod-usb-roles\n  KCONFIG:= \\\n\tCONFIG_EXTCON \\\n\tCONFIG_USB_CHIPIDEA \\\n\tCONFIG_USB_CHIPIDEA_GENERIC \\\n\tCONFIG_USB_CHIPIDEA_HOST=y \\\n\tCONFIG_USB_CHIPIDEA_UDC=y \\\n\tCONFIG_USB_CHIPIDEA_DEBUG=y\n  FILES:= \\\n\t$(LINUX_DIR)/drivers/extcon/extcon-core.ko \\\n\t$(LINUX_DIR)/drivers/usb/chipidea/ci_hdrc.ko \\\n\t$(LINUX_DIR)/drivers/usb/common/ulpi.ko\n  AUTOLOAD:=$(call AutoLoad,39,ci_hdrc,1)\n  $(call AddDepends/usb)\nendef\n\ndefine KernelPackage/usb-chipidea/description\n Kernel support for USB Chipidea controllers\nendef\n\n$(eval $(call KernelPackage,usb-chipidea))\n\n\ndefine KernelPackage/usb-chipidea2\n  TITLE:=Host and device support for Chipidea2 controllers\n  DEPENDS:=+kmod-usb-chipidea\n  KCONFIG:= \\\n\tCONFIG_EXTCON \\\n\tCONFIG_USB_CHIPIDEA \\\n\tCONFIG_USB_CHIPIDEA_HOST=y \\\n\tCONFIG_USB_CHIPIDEA_UDC=y \\\n\tCONFIG_USB_CHIPIDEA_DEBUG=y\n  FILES:= \\\n\t$(LINUX_DIR)/drivers/extcon/extcon-core.ko \\\n\t$(LINUX_DIR)/drivers/usb/chipidea/ci_hdrc_usb2.ko\n  AUTOLOAD:=$(call AutoLoad,39,ci_hdrc_usb2,1)\n  $(call AddDepends/usb)\nendef\n\ndefine KernelPackage/usb-chipidea2/description\n Kernel support for USB Chipidea controllers\nendef\n\n$(eval $(call KernelPackage,usb-chipidea2))\n\n\ndefine KernelPackage/usbmon\n  TITLE:=USB traffic monitor\n  KCONFIG:=CONFIG_USB_MON\n  $(call AddDepends/usb)\n  FILES:=$(LINUX_DIR)/drivers/usb/mon/usbmon.ko\n  AUTOLOAD:=$(call AutoProbe,usbmon)\nendef\n\ndefine KernelPackage/usbmon/description\n Kernel support for USB traffic monitoring\nendef\n\n$(eval $(call KernelPackage,usbmon))\n\nXHCI_MODULES := xhci-pci xhci-plat-hcd\nXHCI_FILES := $(wildcard $(patsubst %,$(LINUX_DIR)/drivers/usb/host/%.ko,$(XHCI_MODULES)))\nXHCI_AUTOLOAD := $(patsubst $(LINUX_DIR)/drivers/usb/host/%.ko,%,$(XHCI_FILES))\n\ndefine KernelPackage/usb3\n  TITLE:=Support for USB3 controllers\n  DEPENDS:= \\\n\t+kmod-usb-xhci-hcd \\\n\t+TARGET_bcm53xx:kmod-usb-bcma \\\n\t+TARGET_bcm53xx:kmod-phy-bcm-ns-usb3 \\\n\t+TARGET_ramips_mt7621:kmod-usb-xhci-mtk \\\n\t+TARGET_apm821xx_nand:kmod-usb-xhci-pci-renesas \\\n\t+TARGET_mvebu_cortexa9:kmod-usb-xhci-pci-renesas\n  KCONFIG:= \\\n\tCONFIG_USB_PCI=y \\\n\tCONFIG_USB_XHCI_PCI \\\n\tCONFIG_USB_XHCI_PLATFORM\n  FILES:= \\\n\t$(XHCI_FILES)\n  AUTOLOAD:=$(call AutoLoad,54,$(XHCI_AUTOLOAD),1)\n  $(call AddDepends/usb)\nendef\n\ndefine KernelPackage/usb3/description\n Kernel support for USB3 (XHCI) controllers\nendef\n\n$(eval $(call KernelPackage,usb3))\n\n\ndefine KernelPackage/usb-net2280\n  TITLE:=Support for NetChip 228x PCI USB peripheral controller\n  KCONFIG:= \\\n\tCONFIG_USB_PCI=y \\\n\tCONFIG_USB_NET2280\n  DEPENDS:=@PCI_SUPPORT +kmod-usb-gadget\n  FILES:=$(LINUX_DIR)/drivers/usb/gadget/udc/net2280.ko\n  AUTOLOAD:=$(call AutoLoad,46,net2280)\n  $(call AddDepends/usb)\nendef\n\ndefine KernelPackage/usb-net2280/description\n  Kernel support for NetChip 228x / PLX USB338x PCI USB peripheral controller.\nendef\n\n$(eval $(call KernelPackage,usb-net2280))\n\ndefine KernelPackage/usb-roles\n  TITLE:=USB Role Switch Library Module\n  KCONFIG:=CONFIG_USB_ROLE_SWITCH\n  HIDDEN:=1\n  FILES:=$(LINUX_DIR)/drivers/usb/roles/roles.ko\n  $(call AddDepends/usb)\nendef\n\ndefine KernelPackage/usb-roles/description\n  Support for USB Role Switch\nendef\n\n$(eval $(call KernelPackage,usb-roles))\n\n\ndefine KernelPackage/usb-xhci-hcd\n  TITLE:=xHCI HCD (USB 3.0) support\n  KCONFIG:= \\\n\t  CONFIG_USB_XHCI_HCD \\\n\t  CONFIG_USB_XHCI_HCD_DEBUGGING=n\n  HIDDEN:=1\n  FILES:=$(LINUX_DIR)/drivers/usb/host/xhci-hcd.ko\n  AUTOLOAD:=$(call AutoLoad,54,xhci-hcd,1)\n  $(call AddDepends/usb)\nendef\n\ndefine KernelPackage/usb-xhci-hcd/description\n  The eXtensible Host Controller Interface (xHCI) is standard for USB 3.0\n  \"SuperSpeed\" host controller hardware.\nendef\n\n$(eval $(call KernelPackage,usb-xhci-hcd))\n\n\ndefine KernelPackage/usb-xhci-mtk\n  TITLE:=xHCI support for MediaTek SoCs\n  DEPENDS:=+kmod-usb-xhci-hcd\n  KCONFIG:=CONFIG_USB_XHCI_MTK\n  HIDDEN:=1\n  FILES:= \\\n\t $(LINUX_DIR)/drivers/usb/host/xhci-mtk.ko@lt5.13 \\\n\t $(LINUX_DIR)/drivers/usb/host/xhci-mtk-hcd.ko@ge5.13\n  AUTOLOAD:=$(call AutoLoad,54,xhci-mtk@lt5.13 xhci-mtk-hcd@gt5.13,1)\n  $(call AddDepends/usb)\nendef\n\ndefine KernelPackage/usb-xhci-mtk/description\n  Kernel support for the xHCI host controller found in MediaTek SoCs.\nendef\n\n$(eval $(call KernelPackage,usb-xhci-mtk))\n\n\ndefine KernelPackage/usb-xhci-pci-renesas\n  TITLE:=Support for additional Renesas xHCI controller with firmware\n  KCONFIG:=CONFIG_USB_XHCI_PCI_RENESAS\n  HIDDEN:=1\n  FILES:=$(LINUX_DIR)/drivers/usb/host/xhci-pci-renesas.ko\n  AUTOLOAD:=$(call AutoLoad,54,xhci-pci-renesas,1)\n  $(call AddDepends/usb)\nendef\n\ndefine KernelPackage/usb-xhci-pci-renesas/description\n  Kernel support for the Renesas xHCI controller with firmware. Make sure you have\n  the firwmare for the device and installed on your system for this device to work.\nendef\n\n$(eval $(call KernelPackage,usb-xhci-pci-renesas))\n\n\ndefine KernelPackage/chaoskey\n  SUBMENU:=$(USB_MENU)\n  TITLE:=Chaoskey hardware RNG support\n  DEPENDS:=+kmod-random-core\n  KCONFIG:=CONFIG_USB_CHAOSKEY\n  FILES:=$(LINUX_DIR)/drivers/usb/misc/chaoskey.ko\n  AUTOLOAD:=$(call AutoProbe,chaoskey)\n  $(call AddDepends/usb)\nendef\n\ndefine KernelPackage/chaoskey/description\n  Kernel module for chaoskey, USB attached true random number generator\nendef\n\n$(eval $(call KernelPackage,chaoskey))\n\n"
  },
  {
    "path": "package/kernel/linux/modules/video.mk",
    "content": "#\n# Copyright (C) 2009 David Cooper <dave@kupesoft.com>\n# Copyright (C) 2006-2010 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\nVIDEO_MENU:=Video Support\n\nV4L2_DIR=v4l2-core\nV4L2_USB_DIR=usb\n\n#\n# Video Display\n#\n\ndefine KernelPackage/backlight\n\tSUBMENU:=$(VIDEO_MENU)\n\tTITLE:=Backlight support\n\tDEPENDS:=@DISPLAY_SUPPORT\n\tHIDDEN:=1\n\tKCONFIG:=CONFIG_BACKLIGHT_CLASS_DEVICE \\\n\t\tCONFIG_BACKLIGHT_LCD_SUPPORT=y \\\n\t\tCONFIG_LCD_CLASS_DEVICE=n \\\n\t\tCONFIG_BACKLIGHT_GENERIC=n \\\n\t\tCONFIG_BACKLIGHT_ADP8860=n \\\n\t\tCONFIG_BACKLIGHT_ADP8870=n \\\n\t\tCONFIG_BACKLIGHT_OT200=n \\\n\t\tCONFIG_BACKLIGHT_PM8941_WLED=n\n\tFILES:=$(LINUX_DIR)/drivers/video/backlight/backlight.ko\n\tAUTOLOAD:=$(call AutoProbe,video backlight)\nendef\n\ndefine KernelPackage/backlight/description\n\tKernel module for Backlight support.\nendef\n\n$(eval $(call KernelPackage,backlight))\n\ndefine KernelPackage/backlight-pwm\n\tSUBMENU:=$(VIDEO_MENU)\n\tTITLE:=PWM Backlight support\n\tDEPENDS:=+kmod-backlight\n\tKCONFIG:=CONFIG_BACKLIGHT_PWM\n\tFILES:=$(LINUX_DIR)/drivers/video/backlight/pwm_bl.ko\n\tAUTOLOAD:=$(call AutoProbe,video pwm_bl)\nendef\n\ndefine KernelPackage/backlight-pwm/description\n\tKernel module for PWM based Backlight support.\nendef\n\n$(eval $(call KernelPackage,backlight-pwm))\n\n\ndefine KernelPackage/fb\n  SUBMENU:=$(VIDEO_MENU)\n  TITLE:=Framebuffer and framebuffer console support\n  DEPENDS:=@DISPLAY_SUPPORT\n  KCONFIG:= \\\n\tCONFIG_FB \\\n\tCONFIG_FB_MXS=n \\\n\tCONFIG_FB_SM750=n \\\n\tCONFIG_FRAMEBUFFER_CONSOLE=y \\\n\tCONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y \\\n\tCONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y \\\n\tCONFIG_FONTS=y \\\n\tCONFIG_FONT_8x8=y \\\n\tCONFIG_FONT_8x16=y \\\n\tCONFIG_FONT_6x11=n \\\n\tCONFIG_FONT_7x14=n \\\n\tCONFIG_FONT_PEARL_8x8=n \\\n\tCONFIG_FONT_ACORN_8x8=n \\\n\tCONFIG_FONT_MINI_4x6=n \\\n\tCONFIG_FONT_6x10=n \\\n\tCONFIG_FONT_SUN8x16=n \\\n\tCONFIG_FONT_SUN12x22=n \\\n\tCONFIG_FONT_10x18=n \\\n\tCONFIG_VT=y \\\n\tCONFIG_CONSOLE_TRANSLATIONS=y \\\n\tCONFIG_VT_CONSOLE=y \\\n\tCONFIG_VT_HW_CONSOLE_BINDING=y\n  FILES:=$(LINUX_DIR)/drivers/video/fbdev/core/fb.ko \\\n\t$(LINUX_DIR)/lib/fonts/font.ko\n  AUTOLOAD:=$(call AutoLoad,06,fb font)\nendef\n\ndefine KernelPackage/fb/description\n Kernel support for framebuffers and framebuffer console.\nendef\n\ndefine KernelPackage/fb/x86\n  FILES+=$(LINUX_DIR)/arch/x86/video/fbdev.ko\n  AUTOLOAD:=$(call AutoLoad,06,fbdev fb font)\nendef\n\n$(eval $(call KernelPackage,fb))\n\n\ndefine KernelPackage/fb-cfb-fillrect\n  SUBMENU:=$(VIDEO_MENU)\n  TITLE:=Framebuffer software rectangle filling support\n  DEPENDS:=+kmod-fb\n  KCONFIG:=CONFIG_FB_CFB_FILLRECT\n  FILES:=$(LINUX_DIR)/drivers/video/fbdev/core/cfbfillrect.ko\n  AUTOLOAD:=$(call AutoLoad,07,cfbfillrect)\nendef\n\ndefine KernelPackage/fb-cfb-fillrect/description\n Kernel support for software rectangle filling\nendef\n\n$(eval $(call KernelPackage,fb-cfb-fillrect))\n\n\ndefine KernelPackage/fb-cfb-copyarea\n  SUBMENU:=$(VIDEO_MENU)\n  TITLE:=Framebuffer software copy area support\n  DEPENDS:=+kmod-fb\n  KCONFIG:=CONFIG_FB_CFB_COPYAREA\n  FILES:=$(LINUX_DIR)/drivers/video/fbdev/core/cfbcopyarea.ko\n  AUTOLOAD:=$(call AutoLoad,07,cfbcopyarea)\nendef\n\ndefine KernelPackage/fb-cfb-copyarea/description\n Kernel support for software copy area\nendef\n\n$(eval $(call KernelPackage,fb-cfb-copyarea))\n\ndefine KernelPackage/fb-cfb-imgblt\n  SUBMENU:=$(VIDEO_MENU)\n  TITLE:=Framebuffer software image blit support\n  DEPENDS:=+kmod-fb\n  KCONFIG:=CONFIG_FB_CFB_IMAGEBLIT\n  FILES:=$(LINUX_DIR)/drivers/video/fbdev/core/cfbimgblt.ko\n  AUTOLOAD:=$(call AutoLoad,07,cfbimgblt)\nendef\n\ndefine KernelPackage/fb-cfb-imgblt/description\n Kernel support for software image blitting\nendef\n\n$(eval $(call KernelPackage,fb-cfb-imgblt))\n\n\ndefine KernelPackage/fb-sys-fops\n  SUBMENU:=$(VIDEO_MENU)\n  TITLE:=Framebuffer software sys ops support\n  DEPENDS:=+kmod-fb\n  KCONFIG:=CONFIG_FB_SYS_FOPS\n  FILES:=$(LINUX_DIR)/drivers/video/fbdev/core/fb_sys_fops.ko\n  AUTOLOAD:=$(call AutoLoad,07,fb_sys_fops)\nendef\n\ndefine KernelPackage/fb-sys-fops/description\n Kernel support for framebuffer sys ops\nendef\n\n$(eval $(call KernelPackage,fb-sys-fops))\n\n\ndefine KernelPackage/fb-sys-ram\n  SUBMENU:=$(VIDEO_MENU)\n  TITLE:=Framebuffer in system RAM support\n  DEPENDS:=+kmod-fb\n  KCONFIG:= \\\n\tCONFIG_FB_SYS_COPYAREA \\\n\tCONFIG_FB_SYS_FILLRECT \\\n\tCONFIG_FB_SYS_IMAGEBLIT\n  FILES:= \\\n\t$(LINUX_DIR)/drivers/video/fbdev/core/syscopyarea.ko \\\n\t$(LINUX_DIR)/drivers/video/fbdev/core/sysfillrect.ko \\\n\t$(LINUX_DIR)/drivers/video/fbdev/core/sysimgblt.ko\n  AUTOLOAD:=$(call AutoLoad,07,syscopyarea sysfillrect sysimgblt)\nendef\n\ndefine KernelPackage/fb-sys-ram/description\n Kernel support for framebuffers in system RAM\nendef\n\n$(eval $(call KernelPackage,fb-sys-ram))\n\n\ndefine KernelPackage/fb-tft\n  SUBMENU:=$(VIDEO_MENU)\n  TITLE:=Support for small TFT LCD display modules\n  DEPENDS:= \\\n\t  @GPIO_SUPPORT +kmod-backlight \\\n\t  +kmod-fb +kmod-fb-sys-fops +kmod-fb-sys-ram +kmod-spi-bitbang\n  KCONFIG:= \\\n       CONFIG_FB_BACKLIGHT=y \\\n       CONFIG_FB_DEFERRED_IO=y \\\n       CONFIG_FB_TFT\n  FILES:= \\\n       $(LINUX_DIR)/drivers/staging/fbtft/fbtft.ko\n  AUTOLOAD:=$(call AutoLoad,08,fbtft)\nendef\n\ndefine KernelPackage/fb-tft/description\n  Support for small TFT LCD display modules\nendef\n\n$(eval $(call KernelPackage,fb-tft))\n\n\ndefine KernelPackage/fb-tft-ili9486\n  SUBMENU:=$(VIDEO_MENU)\n  TITLE:=FB driver for the ILI9486 LCD Controller\n  DEPENDS:=+kmod-fb-tft\n  KCONFIG:=CONFIG_FB_TFT_ILI9486\n  FILES:=$(LINUX_DIR)/drivers/staging/fbtft/fb_ili9486.ko\n  AUTOLOAD:=$(call AutoLoad,09,fb_ili9486)\nendef\n\ndefine KernelPackage/fb-tft-ili9486/description\n  FB driver for the ILI9486 LCD Controller\nendef\n\n$(eval $(call KernelPackage,fb-tft-ili9486))\n\n\ndefine KernelPackage/drm\n  SUBMENU:=$(VIDEO_MENU)\n  TITLE:=Direct Rendering Manager (DRM) support\n  HIDDEN:=1\n  DEPENDS:=+kmod-dma-buf +kmod-i2c-core +PACKAGE_kmod-backlight:kmod-backlight \\\n\t+(LINUX_5_15):kmod-fb\n  KCONFIG:=CONFIG_DRM\n  FILES:= \\\n\t$(LINUX_DIR)/drivers/gpu/drm/drm.ko \\\n\t$(LINUX_DIR)/drivers/gpu/drm/drm_panel_orientation_quirks.ko\n  AUTOLOAD:=$(call AutoLoad,05,drm)\nendef\n\ndefine KernelPackage/drm/description\n  Direct Rendering Manager (DRM) core support\nendef\n\n$(eval $(call KernelPackage,drm))\n\ndefine KernelPackage/drm-ttm\n  SUBMENU:=$(VIDEO_MENU)\n  TITLE:=GPU memory management subsystem\n  DEPENDS:=@DISPLAY_SUPPORT +kmod-drm\n  KCONFIG:=CONFIG_DRM_TTM\n  FILES:=$(LINUX_DIR)/drivers/gpu/drm/ttm/ttm.ko\n  AUTOLOAD:=$(call AutoProbe,ttm)\nendef\n\ndefine KernelPackage/drm-ttm/description\n  GPU memory management subsystem for devices with multiple GPU memory types.\n  Will be enabled automatically if a device driver uses it.\nendef\n\n$(eval $(call KernelPackage,drm-ttm))\n\ndefine KernelPackage/drm-kms-helper\n  SUBMENU:=$(VIDEO_MENU)\n  TITLE:=CRTC helpers for KMS drivers\n  DEPENDS:=@DISPLAY_SUPPORT +kmod-drm +kmod-fb +kmod-fb-sys-fops +kmod-fb-cfb-copyarea \\\n\t+kmod-fb-cfb-fillrect +kmod-fb-cfb-imgblt +kmod-fb-sys-ram\n  KCONFIG:= \\\n    CONFIG_DRM_KMS_HELPER \\\n    CONFIG_DRM_KMS_FB_HELPER=y\n  FILES:=$(LINUX_DIR)/drivers/gpu/drm/drm_kms_helper.ko\n  AUTOLOAD:=$(call AutoProbe,drm_kms_helper)\nendef\n\ndefine KernelPackage/drm-kms-helper/description\n  CRTC helpers for KMS drivers.\nendef\n\n$(eval $(call KernelPackage,drm-kms-helper))\n\ndefine KernelPackage/drm-amdgpu\n  SUBMENU:=$(VIDEO_MENU)\n  TITLE:=AMDGPU DRM support\n  DEPENDS:=@TARGET_x86 @DISPLAY_SUPPORT +kmod-backlight +kmod-drm-ttm \\\n\t+kmod-drm-kms-helper +kmod-i2c-algo-bit +amdgpu-firmware\n  KCONFIG:=CONFIG_DRM_AMDGPU \\\n\tCONFIG_DRM_AMDGPU_SI=y \\\n\tCONFIG_DRM_AMDGPU_CIK=y \\\n\tCONFIG_DRM_AMD_DC=y \\\n\tCONFIG_DEBUG_KERNEL_DC=n\n  FILES:=$(LINUX_DIR)/drivers/gpu/drm/amd/amdgpu/amdgpu.ko \\\n\t$(LINUX_DIR)/drivers/gpu/drm/scheduler/gpu-sched.ko\n  AUTOLOAD:=$(call AutoProbe,amdgpu)\nendef\n\ndefine KernelPackage/drm-amdgpu/description\n  Direct Rendering Manager (DRM) support for AMDGPU Cards\nendef\n\n$(eval $(call KernelPackage,drm-amdgpu))\n\n\ndefine KernelPackage/drm-imx\n  SUBMENU:=$(VIDEO_MENU)\n  TITLE:=Freescale i.MX DRM support\n  DEPENDS:=@TARGET_imx +kmod-drm-kms-helper\n  KCONFIG:=CONFIG_DRM_IMX \\\n\tCONFIG_DRM_FBDEV_EMULATION=y \\\n\tCONFIG_DRM_FBDEV_OVERALLOC=100 \\\n\tCONFIG_IMX_IPUV3_CORE \\\n\tCONFIG_RESET_CONTROLLER=y \\\n\tCONFIG_DRM_IMX_IPUV3 \\\n\tCONFIG_IMX_IPUV3 \\\n\tCONFIG_DRM_GEM_CMA_HELPER=y \\\n\tCONFIG_DRM_KMS_CMA_HELPER=y \\\n\tCONFIG_DRM_IMX_FB_HELPER \\\n\tCONFIG_DRM_IMX_PARALLEL_DISPLAY=n \\\n\tCONFIG_DRM_IMX_TVE=n \\\n\tCONFIG_DRM_IMX_LDB=n \\\n\tCONFIG_DRM_IMX_HDMI=n\n  FILES:= \\\n\t$(LINUX_DIR)/drivers/gpu/drm/imx/imxdrm.ko \\\n\t$(LINUX_DIR)/drivers/gpu/ipu-v3/imx-ipu-v3.ko\n  AUTOLOAD:=$(call AutoLoad,08,imxdrm imx-ipu-v3 imx-ipuv3-crtc)\nendef\n\ndefine KernelPackage/drm-imx/description\n  Direct Rendering Manager (DRM) support for Freescale i.MX\nendef\n\n$(eval $(call KernelPackage,drm-imx))\n\ndefine KernelPackage/drm-imx-hdmi\n  SUBMENU:=$(VIDEO_MENU)\n  TITLE:=Freescale i.MX HDMI DRM support\n  DEPENDS:=+kmod-sound-core kmod-drm-imx\n  KCONFIG:=CONFIG_DRM_IMX_HDMI \\\n\tCONFIG_DRM_DW_HDMI_AHB_AUDIO \\\n\tCONFIG_DRM_DW_HDMI_I2S_AUDIO\n  FILES:= \\\n\t$(LINUX_DIR)/drivers/gpu/drm/bridge/synopsys/dw-hdmi.ko \\\n\t$(LINUX_DIR)/drivers/gpu/drm/bridge/synopsys/dw-hdmi-ahb-audio.ko \\\n\t$(LINUX_DIR)/drivers/gpu/drm/imx/dw_hdmi-imx.ko\n  AUTOLOAD:=$(call AutoLoad,08,dw-hdmi dw-hdmi-ahb-audio.ko dw_hdmi-imx)\nendef\n\ndefine KernelPackage/drm-imx-hdmi/description\n  Direct Rendering Manager (DRM) support for Freescale i.MX HDMI\nendef\n\n$(eval $(call KernelPackage,drm-imx-hdmi))\n\ndefine KernelPackage/drm-imx-ldb\n  SUBMENU:=$(VIDEO_MENU)\n  TITLE:=Freescale i.MX LVDS DRM support\n  DEPENDS:=+kmod-backlight kmod-drm-imx\n  KCONFIG:=CONFIG_DRM_IMX_LDB \\\n\tCONFIG_DRM_PANEL_SIMPLE \\\n\tCONFIG_DRM_PANEL=y \\\n\tCONFIG_DRM_PANEL_SAMSUNG_LD9040=n \\\n\tCONFIG_DRM_PANEL_SAMSUNG_S6E8AA0=n \\\n\tCONFIG_DRM_PANEL_LG_LG4573=n \\\n\tCONFIG_DRM_PANEL_LD9040=n \\\n\tCONFIG_DRM_PANEL_LVDS=n \\\n\tCONFIG_DRM_PANEL_S6E8AA0=n \\\n\tCONFIG_DRM_PANEL_SITRONIX_ST7789V=n\n  FILES:=$(LINUX_DIR)/drivers/gpu/drm/imx/imx-ldb.ko \\\n\t$(LINUX_DIR)/drivers/gpu/drm/panel/panel-simple.ko \\\n\t$(LINUX_DIR)/drivers/gpu/drm/drm_dp_aux_bus.ko@gt5.10\n  AUTOLOAD:=$(call AutoLoad,08,imx-ldb)\nendef\n\ndefine KernelPackage/drm-imx-ldb/description\n  Direct Rendering Manager (DRM) support for Freescale i.MX LVDS\nendef\n\n$(eval $(call KernelPackage,drm-imx-ldb))\n\ndefine KernelPackage/drm-radeon\n  SUBMENU:=$(VIDEO_MENU)\n  TITLE:=Radeon DRM support\n  DEPENDS:=@TARGET_x86 @DISPLAY_SUPPORT +kmod-backlight +kmod-drm-kms-helper \\\n\t+kmod-drm-ttm +kmod-i2c-algo-bit +radeon-firmware\n  KCONFIG:=CONFIG_DRM_RADEON\n  FILES:=$(LINUX_DIR)/drivers/gpu/drm/radeon/radeon.ko\n  AUTOLOAD:=$(call AutoProbe,radeon)\nendef\n\ndefine KernelPackage/drm-radeon/description\n  Direct Rendering Manager (DRM) support for Radeon Cards\nendef\n\n$(eval $(call KernelPackage,drm-radeon))\n\n#\n# Video Capture\n#\n\ndefine KernelPackage/video-core\n  SUBMENU:=$(VIDEO_MENU)\n  TITLE=Video4Linux support\n  DEPENDS:=+PACKAGE_kmod-i2c-core:kmod-i2c-core\n  KCONFIG:= \\\n\tCONFIG_MEDIA_SUPPORT \\\n\tCONFIG_MEDIA_CAMERA_SUPPORT=y \\\n\tCONFIG_VIDEO_DEV \\\n\tCONFIG_V4L_PLATFORM_DRIVERS=y\n  FILES:= \\\n\t$(LINUX_DIR)/drivers/media/$(V4L2_DIR)/videodev.ko\n  AUTOLOAD:=$(call AutoLoad,60, videodev v4l2-common)\nendef\n\ndefine KernelPackage/video-core/description\n Kernel modules for Video4Linux support\nendef\n\n$(eval $(call KernelPackage,video-core))\n\n\ndefine AddDepends/video\n  SUBMENU:=$(VIDEO_MENU)\n  DEPENDS+=kmod-video-core $(1)\nendef\n\ndefine AddDepends/camera\n$(AddDepends/video)\n  KCONFIG+=CONFIG_MEDIA_USB_SUPPORT=y \\\n\t CONFIG_MEDIA_CAMERA_SUPPORT=y\nendef\n\n\ndefine KernelPackage/video-videobuf2\n  TITLE:=videobuf2 lib\n  DEPENDS:=+kmod-dma-buf\n  KCONFIG:= \\\n\tCONFIG_VIDEOBUF2_CORE \\\n\tCONFIG_VIDEOBUF2_MEMOPS \\\n\tCONFIG_VIDEOBUF2_VMALLOC\n  FILES:= \\\n\t$(LINUX_DIR)/drivers/media/common/videobuf2/videobuf2-common.ko \\\n\t$(LINUX_DIR)/drivers/media/common/videobuf2/videobuf2-v4l2.ko \\\n\t$(LINUX_DIR)/drivers/media/common/videobuf2/videobuf2-memops.ko \\\n\t$(LINUX_DIR)/drivers/media/common/videobuf2/videobuf2-vmalloc.ko\n  AUTOLOAD:=$(call AutoLoad,65,videobuf2-core videobuf-v4l2 videobuf2-memops videobuf2-vmalloc)\n  $(call AddDepends/video)\nendef\n\ndefine KernelPackage/video-videobuf2/description\n Kernel modules that implements three basic types of media buffers.\nendef\n\n$(eval $(call KernelPackage,video-videobuf2))\n\n\ndefine KernelPackage/video-cpia2\n  TITLE:=CPIA2 video driver\n  DEPENDS:=@USB_SUPPORT +kmod-usb-core\n  KCONFIG:=CONFIG_VIDEO_CPIA2\n  FILES:=$(LINUX_DIR)/drivers/media/$(V4L2_USB_DIR)/cpia2/cpia2.ko\n  AUTOLOAD:=$(call AutoProbe,cpia2)\n  $(call AddDepends/camera)\nendef\n\ndefine KernelPackage/video-cpia2/description\n Kernel modules for supporting CPIA2 USB based cameras\nendef\n\n$(eval $(call KernelPackage,video-cpia2))\n\n\ndefine KernelPackage/video-pwc\n  TITLE:=Philips USB webcam support\n  DEPENDS:=@USB_SUPPORT +kmod-usb-core +kmod-video-videobuf2\n  KCONFIG:= \\\n\tCONFIG_USB_PWC \\\n\tCONFIG_USB_PWC_DEBUG=n\n  FILES:=$(LINUX_DIR)/drivers/media/$(V4L2_USB_DIR)/pwc/pwc.ko\n  AUTOLOAD:=$(call AutoProbe,pwc)\n  $(call AddDepends/camera)\nendef\n\ndefine KernelPackage/video-pwc/description\n Kernel modules for supporting Philips USB based cameras\nendef\n\n$(eval $(call KernelPackage,video-pwc))\n\n\ndefine KernelPackage/video-uvc\n  TITLE:=USB Video Class (UVC) support\n  DEPENDS:=@USB_SUPPORT +kmod-usb-core +kmod-video-videobuf2 +kmod-input-core\n  KCONFIG:= CONFIG_USB_VIDEO_CLASS\n  FILES:=$(LINUX_DIR)/drivers/media/$(V4L2_USB_DIR)/uvc/uvcvideo.ko\n  AUTOLOAD:=$(call AutoProbe,uvcvideo)\n  $(call AddDepends/camera)\nendef\n\ndefine KernelPackage/video-uvc/description\n Kernel modules for supporting USB Video Class (UVC) devices\nendef\n\n$(eval $(call KernelPackage,video-uvc))\n\n\ndefine KernelPackage/video-gspca-core\n  MENU:=1\n  TITLE:=GSPCA webcam core support framework\n  DEPENDS:=@USB_SUPPORT +kmod-usb-core +kmod-input-core +kmod-video-videobuf2\n  KCONFIG:=CONFIG_USB_GSPCA\n  FILES:=$(LINUX_DIR)/drivers/media/$(V4L2_USB_DIR)/gspca/gspca_main.ko\n  AUTOLOAD:=$(call AutoProbe,gspca_main)\n  $(call AddDepends/camera)\nendef\n\ndefine KernelPackage/video-gspca-core/description\n Kernel modules for supporting GSPCA based webcam devices. Note this is just\n the core of the driver, please select a submodule that supports your webcam.\nendef\n\n$(eval $(call KernelPackage,video-gspca-core))\n\n\ndefine AddDepends/camera-gspca\n  SUBMENU:=$(VIDEO_MENU)\n  DEPENDS+=kmod-video-gspca-core $(1)\nendef\n\n\ndefine KernelPackage/video-gspca-conex\n  TITLE:=conex webcam support\n  KCONFIG:=CONFIG_USB_GSPCA_CONEX\n  FILES:=$(LINUX_DIR)/drivers/media/$(V4L2_USB_DIR)/gspca/gspca_conex.ko\n  AUTOLOAD:=$(call AutoProbe,gspca_conex)\n  $(call AddDepends/camera-gspca)\nendef\n\ndefine KernelPackage/video-gspca-conex/description\n The Conexant Camera Driver (conex) kernel module\nendef\n\n$(eval $(call KernelPackage,video-gspca-conex))\n\n\ndefine KernelPackage/video-gspca-etoms\n  TITLE:=etoms webcam support\n  KCONFIG:=CONFIG_USB_GSPCA_ETOMS\n  FILES:=$(LINUX_DIR)/drivers/media/$(V4L2_USB_DIR)/gspca/gspca_etoms.ko\n  AUTOLOAD:=$(call AutoProbe,gspca_etoms)\n  $(call AddDepends/camera-gspca)\nendef\n\ndefine KernelPackage/video-gspca-etoms/description\n The Etoms USB Camera Driver (etoms) kernel module\nendef\n\n$(eval $(call KernelPackage,video-gspca-etoms))\n\n\ndefine KernelPackage/video-gspca-finepix\n  TITLE:=finepix webcam support\n  KCONFIG:=CONFIG_USB_GSPCA_FINEPIX\n  FILES:=$(LINUX_DIR)/drivers/media/$(V4L2_USB_DIR)/gspca/gspca_finepix.ko\n  AUTOLOAD:=$(call AutoProbe,gspca_finepix)\n  $(call AddDepends/camera-gspca)\nendef\n\ndefine KernelPackage/video-gspca-finepix/description\n The Fujifilm FinePix USB V4L2 driver (finepix) kernel module\nendef\n\n$(eval $(call KernelPackage,video-gspca-finepix))\n\n\ndefine KernelPackage/video-gspca-mars\n  TITLE:=mars webcam support\n  KCONFIG:=CONFIG_USB_GSPCA_MARS\n  FILES:=$(LINUX_DIR)/drivers/media/$(V4L2_USB_DIR)/gspca/gspca_mars.ko\n  AUTOLOAD:=$(call AutoProbe,gspca_mars)\n  $(call AddDepends/camera-gspca)\nendef\n\ndefine KernelPackage/video-gspca-mars/description\n The Mars USB Camera Driver (mars) kernel module\nendef\n\n$(eval $(call KernelPackage,video-gspca-mars))\n\n\ndefine KernelPackage/video-gspca-mr97310a\n  TITLE:=mr97310a webcam support\n  KCONFIG:=CONFIG_USB_GSPCA_MR97310A\n  FILES:=$(LINUX_DIR)/drivers/media/$(V4L2_USB_DIR)/gspca/gspca_mr97310a.ko\n  AUTOLOAD:=$(call AutoProbe,gspca_mr97310a)\n  $(call AddDepends/camera-gspca)\nendef\n\ndefine KernelPackage/video-gspca-mr97310a/description\n The Mars-Semi MR97310A USB Camera Driver (mr97310a) kernel module\nendef\n\n$(eval $(call KernelPackage,video-gspca-mr97310a))\n\n\ndefine KernelPackage/video-gspca-ov519\n  TITLE:=ov519 webcam support\n  KCONFIG:=CONFIG_USB_GSPCA_OV519\n  FILES:=$(LINUX_DIR)/drivers/media/$(V4L2_USB_DIR)/gspca/gspca_ov519.ko\n  AUTOLOAD:=$(call AutoProbe,gspca_ov519)\n  $(call AddDepends/camera-gspca)\nendef\n\ndefine KernelPackage/video-gspca-ov519/description\n The OV519 USB Camera Driver (ov519) kernel module\nendef\n\n$(eval $(call KernelPackage,video-gspca-ov519))\n\n\ndefine KernelPackage/video-gspca-ov534\n  TITLE:=ov534 webcam support\n  KCONFIG:=CONFIG_USB_GSPCA_OV534\n  FILES:=$(LINUX_DIR)/drivers/media/$(V4L2_USB_DIR)/gspca/gspca_ov534.ko\n  AUTOLOAD:=$(call AutoProbe,gspca_ov534)\n  $(call AddDepends/camera-gspca)\nendef\n\ndefine KernelPackage/video-gspca-ov534/description\n The OV534 USB Camera Driver (ov534) kernel module\nendef\n\n$(eval $(call KernelPackage,video-gspca-ov534))\n\n\ndefine KernelPackage/video-gspca-ov534-9\n  TITLE:=ov534-9 webcam support\n  KCONFIG:=CONFIG_USB_GSPCA_OV534_9\n  FILES:=$(LINUX_DIR)/drivers/media/$(V4L2_USB_DIR)/gspca/gspca_ov534_9.ko\n  AUTOLOAD:=$(call AutoProbe,gspca_ov534_9)\n  $(call AddDepends/camera-gspca)\nendef\n\ndefine KernelPackage/video-gspca-ov534-9/description\n The OV534-9 USB Camera Driver (ov534_9) kernel module\nendef\n\n$(eval $(call KernelPackage,video-gspca-ov534-9))\n\n\ndefine KernelPackage/video-gspca-pac207\n  TITLE:=pac207 webcam support\n  KCONFIG:=CONFIG_USB_GSPCA_PAC207\n  FILES:=$(LINUX_DIR)/drivers/media/$(V4L2_USB_DIR)/gspca/gspca_pac207.ko\n  AUTOLOAD:=$(call AutoProbe,gspca_pac207)\n  $(call AddDepends/camera-gspca)\nendef\n\ndefine KernelPackage/video-gspca-pac207/description\n The Pixart PAC207 USB Camera Driver (pac207) kernel module\nendef\n\n$(eval $(call KernelPackage,video-gspca-pac207))\n\n\ndefine KernelPackage/video-gspca-pac7311\n  TITLE:=pac7311 webcam support\n  KCONFIG:=CONFIG_USB_GSPCA_PAC7311\n  FILES:=$(LINUX_DIR)/drivers/media/$(V4L2_USB_DIR)/gspca/gspca_pac7311.ko\n  AUTOLOAD:=$(call AutoProbe,gspca_pac7311)\n  $(call AddDepends/camera-gspca)\nendef\n\ndefine KernelPackage/video-gspca-pac7311/description\n The Pixart PAC7311 USB Camera Driver (pac7311) kernel module\nendef\n\n$(eval $(call KernelPackage,video-gspca-pac7311))\n\n\ndefine KernelPackage/video-gspca-se401\n  TITLE:=se401 webcam support\n  KCONFIG:=CONFIG_USB_GSPCA_SE401\n  FILES:=$(LINUX_DIR)/drivers/media/$(V4L2_USB_DIR)/gspca/gspca_se401.ko\n  AUTOLOAD:=$(call AutoProbe,gspca_se401)\n  $(call AddDepends/camera-gspca)\nendef\n\ndefine KernelPackage/video-gspca-se401/description\n The SE401 USB Camera Driver kernel module\nendef\n\n$(eval $(call KernelPackage,video-gspca-se401))\n\n\ndefine KernelPackage/video-gspca-sn9c20x\n  TITLE:=sn9c20x webcam support\n  KCONFIG:=CONFIG_USB_GSPCA_SN9C20X\n  FILES:=$(LINUX_DIR)/drivers/media/$(V4L2_USB_DIR)/gspca/gspca_sn9c20x.ko\n  AUTOLOAD:=$(call AutoProbe,gspca_sn9c20x)\n  $(call AddDepends/camera-gspca)\nendef\n\ndefine KernelPackage/video-gspca-sn9c20x/description\n The SN9C20X USB Camera Driver (sn9c20x) kernel module\nendef\n\n$(eval $(call KernelPackage,video-gspca-sn9c20x))\n\n\ndefine KernelPackage/video-gspca-sonixb\n  TITLE:=sonixb webcam support\n  KCONFIG:=CONFIG_USB_GSPCA_SONIXB\n  FILES:=$(LINUX_DIR)/drivers/media/$(V4L2_USB_DIR)/gspca/gspca_sonixb.ko\n  AUTOLOAD:=$(call AutoProbe,gspca_sonixb)\n  $(call AddDepends/camera-gspca)\nendef\n\ndefine KernelPackage/video-gspca-sonixb/description\n The SONIX Bayer USB Camera Driver (sonixb) kernel module\nendef\n\n$(eval $(call KernelPackage,video-gspca-sonixb))\n\n\ndefine KernelPackage/video-gspca-sonixj\n  TITLE:=sonixj webcam support\n  KCONFIG:=CONFIG_USB_GSPCA_SONIXJ\n  FILES:=$(LINUX_DIR)/drivers/media/$(V4L2_USB_DIR)/gspca/gspca_sonixj.ko\n  AUTOLOAD:=$(call AutoProbe,gspca_sonixj)\n  $(call AddDepends/camera-gspca)\nendef\n\ndefine KernelPackage/video-gspca-sonixj/description\n The SONIX JPEG USB Camera Driver (sonixj) kernel module\nendef\n\n$(eval $(call KernelPackage,video-gspca-sonixj))\n\n\ndefine KernelPackage/video-gspca-spca500\n  TITLE:=spca500 webcam support\n  KCONFIG:=CONFIG_USB_GSPCA_SPCA500\n  FILES:=$(LINUX_DIR)/drivers/media/$(V4L2_USB_DIR)/gspca/gspca_spca500.ko\n  AUTOLOAD:=$(call AutoProbe,gspca_spca500)\n  $(call AddDepends/camera-gspca)\nendef\n\ndefine KernelPackage/video-gspca-spca500/description\n The SPCA500 USB Camera Driver (spca500) kernel module\nendef\n\n$(eval $(call KernelPackage,video-gspca-spca500))\n\n\ndefine KernelPackage/video-gspca-spca501\n  TITLE:=spca501 webcam support\n  KCONFIG:=CONFIG_USB_GSPCA_SPCA501\n  FILES:=$(LINUX_DIR)/drivers/media/$(V4L2_USB_DIR)/gspca/gspca_spca501.ko\n  AUTOLOAD:=$(call AutoProbe,gspca_spca501)\n  $(call AddDepends/camera-gspca)\nendef\n\ndefine KernelPackage/video-gspca-spca501/description\n The SPCA501 USB Camera Driver (spca501) kernel module\nendef\n\n$(eval $(call KernelPackage,video-gspca-spca501))\n\n\ndefine KernelPackage/video-gspca-spca505\n  TITLE:=spca505 webcam support\n  KCONFIG:=CONFIG_USB_GSPCA_SPCA505\n  FILES:=$(LINUX_DIR)/drivers/media/$(V4L2_USB_DIR)/gspca/gspca_spca505.ko\n  AUTOLOAD:=$(call AutoProbe,gspca_spca505)\n  $(call AddDepends/camera-gspca)\nendef\n\ndefine KernelPackage/video-gspca-spca505/description\n The SPCA505 USB Camera Driver (spca505) kernel module\nendef\n\n$(eval $(call KernelPackage,video-gspca-spca505))\n\n\ndefine KernelPackage/video-gspca-spca506\n  TITLE:=spca506 webcam support\n  KCONFIG:=CONFIG_USB_GSPCA_SPCA506\n  FILES:=$(LINUX_DIR)/drivers/media/$(V4L2_USB_DIR)/gspca/gspca_spca506.ko\n  AUTOLOAD:=$(call AutoProbe,gspca_spca506)\n  $(call AddDepends/camera-gspca)\nendef\n\ndefine KernelPackage/video-gspca-spca506/description\n The SPCA506 USB Camera Driver (spca506) kernel module\nendef\n\n$(eval $(call KernelPackage,video-gspca-spca506))\n\n\ndefine KernelPackage/video-gspca-spca508\n  TITLE:=spca508 webcam support\n  KCONFIG:=CONFIG_USB_GSPCA_SPCA508\n  FILES:=$(LINUX_DIR)/drivers/media/$(V4L2_USB_DIR)/gspca/gspca_spca508.ko\n  AUTOLOAD:=$(call AutoProbe,gspca_spca508)\n  $(call AddDepends/camera-gspca)\nendef\n\ndefine KernelPackage/video-gspca-spca508/description\n The SPCA508 USB Camera Driver (spca508) kernel module\nendef\n\n$(eval $(call KernelPackage,video-gspca-spca508))\n\n\ndefine KernelPackage/video-gspca-spca561\n  TITLE:=spca561 webcam support\n  KCONFIG:=CONFIG_USB_GSPCA_SPCA561\n  FILES:=$(LINUX_DIR)/drivers/media/$(V4L2_USB_DIR)/gspca/gspca_spca561.ko\n  AUTOLOAD:=$(call AutoProbe,gspca_spca561)\n  $(call AddDepends/camera-gspca)\nendef\n\ndefine KernelPackage/video-gspca-spca561/description\n The SPCA561 USB Camera Driver (spca561) kernel module\nendef\n\n$(eval $(call KernelPackage,video-gspca-spca561))\n\n\ndefine KernelPackage/video-gspca-sq905\n  TITLE:=sq905 webcam support\n  KCONFIG:=CONFIG_USB_GSPCA_SQ905\n  FILES:=$(LINUX_DIR)/drivers/media/$(V4L2_USB_DIR)/gspca/gspca_sq905.ko\n  AUTOLOAD:=$(call AutoProbe,gspca_sq905)\n  $(call AddDepends/camera-gspca)\nendef\n\ndefine KernelPackage/video-gspca-sq905/description\n The SQ Technologies SQ905 based USB Camera Driver (sq905) kernel module\nendef\n\n$(eval $(call KernelPackage,video-gspca-sq905))\n\n\ndefine KernelPackage/video-gspca-sq905c\n  TITLE:=sq905c webcam support\n  KCONFIG:=CONFIG_USB_GSPCA_SQ905C\n  FILES:=$(LINUX_DIR)/drivers/media/$(V4L2_USB_DIR)/gspca/gspca_sq905c.ko\n  AUTOLOAD:=$(call AutoProbe,gspca_sq905c)\n  $(call AddDepends/camera-gspca)\nendef\n\ndefine KernelPackage/video-gspca-sq905c/description\n The SQ Technologies SQ905C based USB Camera Driver (sq905c) kernel module\nendef\n\n$(eval $(call KernelPackage,video-gspca-sq905c))\n\n\ndefine KernelPackage/video-gspca-sq930x\n  TITLE:=sq930x webcam support\n  KCONFIG:=CONFIG_USB_GSPCA_SQ930X\n  FILES:=$(LINUX_DIR)/drivers/media/$(V4L2_USB_DIR)/gspca/gspca_sq930x.ko\n  AUTOLOAD:=$(call AutoProbe,gspca_sq930x)\n  $(call AddDepends/camera-gspca)\nendef\n\ndefine KernelPackage/video-gspca-sq930x/description\n The SQ Technologies SQ930X based USB Camera Driver (sq930x) kernel module\nendef\n\n$(eval $(call KernelPackage,video-gspca-sq930x))\n\n\ndefine KernelPackage/video-gspca-stk014\n  TITLE:=stk014 webcam support\n  KCONFIG:=CONFIG_USB_GSPCA_STK014\n  FILES:=$(LINUX_DIR)/drivers/media/$(V4L2_USB_DIR)/gspca/gspca_stk014.ko\n  AUTOLOAD:=$(call AutoProbe,gspca_stk014)\n  $(call AddDepends/camera-gspca)\nendef\n\ndefine KernelPackage/video-gspca-stk014/description\n The Syntek DV4000 (STK014) USB Camera Driver (stk014) kernel module\nendef\n\n$(eval $(call KernelPackage,video-gspca-stk014))\n\n\ndefine KernelPackage/video-gspca-sunplus\n  TITLE:=sunplus webcam support\n  KCONFIG:=CONFIG_USB_GSPCA_SUNPLUS\n  FILES:=$(LINUX_DIR)/drivers/media/$(V4L2_USB_DIR)/gspca/gspca_sunplus.ko\n  AUTOLOAD:=$(call AutoProbe,gspca_sunplus)\n  $(call AddDepends/camera-gspca)\nendef\n\ndefine KernelPackage/video-gspca-sunplus/description\n The SUNPLUS USB Camera Driver (sunplus) kernel module\nendef\n\n$(eval $(call KernelPackage,video-gspca-sunplus))\n\n\ndefine KernelPackage/video-gspca-t613\n  TITLE:=t613 webcam support\n  KCONFIG:=CONFIG_USB_GSPCA_T613\n  FILES:=$(LINUX_DIR)/drivers/media/$(V4L2_USB_DIR)/gspca/gspca_t613.ko\n  AUTOLOAD:=$(call AutoProbe,gspca_t613)\n  $(call AddDepends/camera-gspca)\nendef\n\ndefine KernelPackage/video-gspca-t613/description\n The T613 (JPEG Compliance) USB Camera Driver (t613) kernel module\nendef\n\n$(eval $(call KernelPackage,video-gspca-t613))\n\n\ndefine KernelPackage/video-gspca-tv8532\n  TITLE:=tv8532 webcam support\n  KCONFIG:=CONFIG_USB_GSPCA_TV8532\n  FILES:=$(LINUX_DIR)/drivers/media/$(V4L2_USB_DIR)/gspca/gspca_tv8532.ko\n  AUTOLOAD:=$(call AutoProbe,gspca_tv8532)\n  $(call AddDepends/camera-gspca)\nendef\n\ndefine KernelPackage/video-gspca-tv8532/description\n The TV8532 USB Camera Driver (tv8532) kernel module\nendef\n\n$(eval $(call KernelPackage,video-gspca-tv8532))\n\n\ndefine KernelPackage/video-gspca-vc032x\n  TITLE:=vc032x webcam support\n  KCONFIG:=CONFIG_USB_GSPCA_VC032X\n  FILES:=$(LINUX_DIR)/drivers/media/$(V4L2_USB_DIR)/gspca/gspca_vc032x.ko\n  AUTOLOAD:=$(call AutoProbe,gspca_vc032x)\n  $(call AddDepends/camera-gspca)\nendef\n\ndefine KernelPackage/video-gspca-vc032x/description\n The VC032X USB Camera Driver (vc032x) kernel module\nendef\n\n$(eval $(call KernelPackage,video-gspca-vc032x))\n\n\ndefine KernelPackage/video-gspca-zc3xx\n  TITLE:=zc3xx webcam support\n  KCONFIG:=CONFIG_USB_GSPCA_ZC3XX\n  FILES:=$(LINUX_DIR)/drivers/media/$(V4L2_USB_DIR)/gspca/gspca_zc3xx.ko\n  AUTOLOAD:=$(call AutoProbe,gspca_zc3xx)\n  $(call AddDepends/camera-gspca)\nendef\n\ndefine KernelPackage/video-gspca-zc3xx/description\n The ZC3XX USB Camera Driver (zc3xx) kernel module\nendef\n\n$(eval $(call KernelPackage,video-gspca-zc3xx))\n\n\ndefine KernelPackage/video-gspca-m5602\n  TITLE:=m5602 webcam support\n  KCONFIG:=CONFIG_USB_M5602\n  FILES:=$(LINUX_DIR)/drivers/media/$(V4L2_USB_DIR)/gspca/m5602/gspca_m5602.ko\n  AUTOLOAD:=$(call AutoProbe,gspca_m5602)\n  $(call AddDepends/camera-gspca)\nendef\n\ndefine KernelPackage/video-gspca-m5602/description\n The ALi USB m5602 Camera Driver (m5602) kernel module\nendef\n\n$(eval $(call KernelPackage,video-gspca-m5602))\n\n\ndefine KernelPackage/video-gspca-stv06xx\n  TITLE:=stv06xx webcam support\n  KCONFIG:=CONFIG_USB_STV06XX\n  FILES:=$(LINUX_DIR)/drivers/media/$(V4L2_USB_DIR)/gspca/stv06xx/gspca_stv06xx.ko\n  AUTOLOAD:=$(call AutoProbe,gspca_stv06xx)\n  $(call AddDepends/camera-gspca)\nendef\n\ndefine KernelPackage/video-gspca-stv06xx/description\n The STV06XX USB Camera Driver (stv06xx) kernel module\nendef\n\n$(eval $(call KernelPackage,video-gspca-stv06xx))\n\n\ndefine KernelPackage/video-gspca-gl860\n  TITLE:=gl860 webcam support\n  KCONFIG:=CONFIG_USB_GL860\n  FILES:=$(LINUX_DIR)/drivers/media/$(V4L2_USB_DIR)/gspca/gl860/gspca_gl860.ko\n  AUTOLOAD:=$(call AutoProbe,gspca_gl860)\n  $(call AddDepends/camera-gspca)\nendef\n\ndefine KernelPackage/video-gspca-gl860/description\n The GL860 USB Camera Driver (gl860) kernel module\nendef\n\n$(eval $(call KernelPackage,video-gspca-gl860))\n\n\ndefine KernelPackage/video-gspca-jeilinj\n  TITLE:=jeilinj webcam support\n  KCONFIG:=CONFIG_USB_GSPCA_JEILINJ\n  FILES:=$(LINUX_DIR)/drivers/media/$(V4L2_USB_DIR)/gspca/gspca_jeilinj.ko\n  AUTOLOAD:=$(call AutoProbe,gspca_jeilinj)\n  $(call AddDepends/camera-gspca)\nendef\n\ndefine KernelPackage/video-gspca-jeilinj/description\n The JEILINJ USB Camera Driver (jeilinj) kernel module\nendef\n\n$(eval $(call KernelPackage,video-gspca-jeilinj))\n\n\ndefine KernelPackage/video-gspca-konica\n  TITLE:=konica webcam support\n  KCONFIG:=CONFIG_USB_GSPCA_KONICA\n  FILES:=$(LINUX_DIR)/drivers/media/$(V4L2_USB_DIR)/gspca/gspca_konica.ko\n  AUTOLOAD:=$(call AutoProbe,gspca_konica)\n  $(call AddDepends/camera-gspca)\nendef\n\ndefine KernelPackage/video-gspca-konica/description\n The Konica USB Camera Driver (konica) kernel module\nendef\n\n$(eval $(call KernelPackage,video-gspca-konica))\n"
  },
  {
    "path": "package/kernel/linux/modules/virt.mk",
    "content": "#\n# Copyright (C) 2016 Yousong Zhou <yszhou4tech@gmail.com>\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\ndefine KernelPackage/irqbypass\n  SUBMENU:=Virtualization\n  TITLE:=IRQ offload/bypass manager\n  KCONFIG:=CONFIG_IRQ_BYPASS_MANAGER\n  HIDDEN:=1\n  FILES:= $(LINUX_DIR)/virt/lib/irqbypass.ko\n  AUTOLOAD:=$(call AutoProbe,irqbypass.ko)\nendef\n$(eval $(call KernelPackage,irqbypass))\n\n\ndefine KernelPackage/kvm-x86\n  SUBMENU:=Virtualization\n  TITLE:=Kernel-based Virtual Machine (KVM) support\n  DEPENDS:=@TARGET_x86_generic||TARGET_x86_64 +kmod-irqbypass\n  KCONFIG:=\\\n\t  CONFIG_KVM \\\n\t  CONFIG_KVM_MMU_AUDIT=n \\\n\t  CONFIG_VIRTUALIZATION=y\n  FILES:= $(LINUX_DIR)/arch/$(LINUX_KARCH)/kvm/kvm.ko\n  AUTOLOAD:=$(call AutoProbe,kvm.ko)\nendef\n\ndefine KernelPackage/kvm-x86/description\n  Support hosting fully virtualized guest machines using hardware\n  virtualization extensions.  You will need a fairly recent\n  processor equipped with virtualization extensions. You will also\n  need to select one or more of the processor modules.\n\n  This module provides access to the hardware capabilities through\n  a character device node named /dev/kvm.\nendef\n\n$(eval $(call KernelPackage,kvm-x86))\n\n\ndefine KernelPackage/kvm-intel\n  SUBMENU:=Virtualization\n  TITLE:=KVM for Intel processors support\n  DEPENDS:=+kmod-kvm-x86\n  KCONFIG:=CONFIG_KVM_INTEL\n  FILES:= $(LINUX_DIR)/arch/$(LINUX_KARCH)/kvm/kvm-intel.ko\n  AUTOLOAD:=$(call AutoProbe,kvm-intel.ko)\nendef\n\ndefine KernelPackage/kvm-intel/description\n  Provides support for KVM on Intel processors equipped with the VT\n  extensions.\nendef\n\n$(eval $(call KernelPackage,kvm-intel))\n\n\ndefine KernelPackage/kvm-amd\n  SUBMENU:=Virtualization\n  TITLE:=KVM for AMD processors support\n  DEPENDS:=+kmod-kvm-x86\n  KCONFIG:=CONFIG_KVM_AMD\n  FILES:= $(LINUX_DIR)/arch/$(LINUX_KARCH)/kvm/kvm-amd.ko\n  AUTOLOAD:=$(call AutoProbe,kvm-amd.ko)\nendef\n\ndefine KernelPackage/kvm-amd/description\n  Provides support for KVM on AMD processors equipped with the AMD-V\n  (SVM) extensions.\nendef\n\n$(eval $(call KernelPackage,kvm-amd))\n"
  },
  {
    "path": "package/kernel/linux/modules/w1.mk",
    "content": "#\n# Copyright (C) 2008-2010 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\nW1_MENU:=W1 support\nW1_MASTERS_DIR:=$(LINUX_DIR)/drivers/w1/masters\nW1_SLAVES_DIR:=$(LINUX_DIR)/drivers/w1/slaves\n\ndefine KernelPackage/w1\n  SUBMENU:=$(W1_MENU)\n  TITLE:=Dallas's 1-wire support\n  KCONFIG:=CONFIG_W1\n  FILES:=$(LINUX_DIR)/drivers/w1/wire.ko\n  DEPENDS:=+kmod-hwmon-core\nendef\n\ndefine KernelPackage/w1/description\n Kernel module for Dallas's 1-wire support\nendef\n\n$(eval $(call KernelPackage,w1))\n\n\ndefine AddDepends/w1\n  SUBMENU:=$(W1_MENU)\n  DEPENDS+=kmod-w1 $(1)\nendef\n\n\n#\n# 1-wire masters\n#\ndefine KernelPackage/w1-master-gpio\n  TITLE:=GPIO 1-wire bus master driver\n  DEPENDS:=@GPIO_SUPPORT\n  KCONFIG:=CONFIG_W1_MASTER_GPIO\n  FILES:=$(W1_MASTERS_DIR)/w1-gpio.ko\n  AUTOLOAD:=$(call AutoProbe,w1-gpio)\n  $(call AddDepends/w1)\nendef\n\ndefine KernelPackage/w1-master-gpio/description\n Kernel module for the GPIO 1-wire bus master driver\nendef\n\n$(eval $(call KernelPackage,w1-master-gpio))\n\ndefine KernelPackage/w1-master-ds2482\n  TITLE:=DS2482 1-wire i2c bus master driver\n  KCONFIG:=CONFIG_W1_MASTER_DS2482\n  FILES:=$(W1_MASTERS_DIR)/ds2482.ko\n  AUTOLOAD:=$(call AutoProbe,ds2482)\n  $(call AddDepends/w1,+kmod-i2c-core)\nendef\n\ndefine KernelPackage/w1-master-ds2482/description\n Kernel module for the DS2482 i2c 1-wire bus master driver\n NOTE: Init with: echo ds2482 0x18 > /sys/bus/i2c/devices/i2c-0/new_device\n or use owfs\nendef\n\n$(eval $(call KernelPackage,w1-master-ds2482))\n\n\ndefine KernelPackage/w1-master-ds2490\n  TITLE:=DS2490 1-wire usb bus master driver\n  DEPENDS:=@USB_SUPPORT +kmod-usb-core\n  KCONFIG:=CONFIG_W1_MASTER_DS2490\n  FILES:=$(W1_MASTERS_DIR)/ds2490.ko\n  AUTOLOAD:=$(call AutoProbe,ds2490)\n  $(call AddDepends/w1)\nendef\n\ndefine KernelPackage/w1-master-ds2490/description\n Kernel module for the DS2490 usb 1-wire bus master driver\nendef\n\n$(eval $(call KernelPackage,w1-master-ds2490))\n\n\ndefine KernelPackage/w1-master-mxc\n  TITLE:=Freescale MXC 1-wire busmaster\n  DEPENDS:=@TARGET_imx\n  KCONFIG:=CONFIG_W1_MASTER_MXC\n  FILES:=$(W1_MASTERS_DIR)/mxc_w1.ko\n  AUTOLOAD:=$(call AutoProbe,mxc_w1)\n  $(call AddDepends/w1)\nendef\n\ndefine KernelPackage/w1-master-mxc/description\n Kernel module for 1-wire Freescale MXC 1-wire busmaster\nendef\n\n$(eval $(call KernelPackage,w1-master-mxc))\n\n\n#\n# 1-wire slaves\n#\ndefine KernelPackage/w1-slave-therm\n  TITLE:=Thermal family implementation\n  KCONFIG:=CONFIG_W1_SLAVE_THERM\n  FILES:=$(W1_SLAVES_DIR)/w1_therm.ko\n  AUTOLOAD:=$(call AutoProbe,w1_therm)\n  $(call AddDepends/w1)\nendef\n\ndefine KernelPackage/w1-slave-therm/description\n Kernel module for 1-wire thermal sensors\nendef\n\n$(eval $(call KernelPackage,w1-slave-therm))\n\n\ndefine KernelPackage/w1-slave-smem\n  TITLE:=Simple 64bit memory family implementation\n  KCONFIG:=CONFIG_W1_SLAVE_SMEM\n  FILES:=$(W1_SLAVES_DIR)/w1_smem.ko\n  AUTOLOAD:=$(call AutoProbe,w1_smem)\n  $(call AddDepends/w1)\nendef\n\ndefine KernelPackage/w1-slave-smem/description\n Kernel module for 1-wire simple 64bit memory rom(ds2401/ds2411/ds1990*)\nendef\n\n$(eval $(call KernelPackage,w1-slave-smem))\n\ndefine KernelPackage/w1-slave-ds2431\n  TITLE:=DS2431 1kb EEPROM driver\n  KCONFIG:= CONFIG_W1_SLAVE_DS2431\n  FILES:=$(W1_SLAVES_DIR)/w1_ds2431.ko\n  AUTOLOAD:=$(call AutoProbe,w1_ds2431)\n  $(call AddDepends/w1)\nendef\n\ndefine KernelPackage/w1-slave-ds2431/description\n Kernel module for 1-wire 1kb EEPROM (DS2431)\nendef\n\n$(eval $(call KernelPackage,w1-slave-ds2431))\n\ndefine KernelPackage/w1-slave-ds2433\n  TITLE:=DS2433 4kb EEPROM driver\n  KCONFIG:= \\\n\tCONFIG_W1_SLAVE_DS2433 \\\n\tCONFIG_W1_SLAVE_DS2433_CRC=n\n  FILES:=$(W1_SLAVES_DIR)/w1_ds2433.ko\n  AUTOLOAD:=$(call AutoProbe,w1_ds2433)\n  $(call AddDepends/w1)\nendef\n\ndefine KernelPackage/w1-slave-ds2433/description\n Kernel module for 1-wire 4kb EEPROM (DS2433)\nendef\n\n$(eval $(call KernelPackage,w1-slave-ds2433))\n\n\ndefine KernelPackage/w1-slave-ds2760\n  TITLE:=Dallas 2760 battery monitor chip (HP iPAQ & others)\n  KCONFIG:= \\\n\tCONFIG_W1_SLAVE_DS2760 \\\n\tCONFIG_W1_SLAVE_DS2433_CRC=n\n  FILES:=$(W1_SLAVES_DIR)/w1_ds2760.ko\n  AUTOLOAD:=$(call AutoProbe,w1_ds2760)\n  $(call AddDepends/w1)\nendef\n\ndefine KernelPackage/w1-slave-ds2760/description\n Kernel module for 1-wire DS2760 battery monitor chip support\nendef\n\n$(eval $(call KernelPackage,w1-slave-ds2760))\n\n\ndefine KernelPackage/w1-slave-ds2413\n  TITLE:=DS2413 2 Ch. Addressable Switch\n  KCONFIG:= \\\n\tCONFIG_W1_SLAVE_DS2413\n  FILES:=$(W1_SLAVES_DIR)/w1_ds2413.ko\n  AUTOLOAD:=$(call AutoProbe,w1_ds2413)\n  $(call AddDepends/w1)\nendef\n\ndefine KernelPackage/w1-slave-ds2413/description\n Kernel module for 1-wire DS2413 Dual Channel Addressable Switch support\nendef\n\n$(eval $(call KernelPackage,w1-slave-ds2413))\n"
  },
  {
    "path": "package/kernel/linux/modules/wireless.mk",
    "content": "#\n# Copyright (C) 2006-2008 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\nWIRELESS_MENU:=Wireless Drivers\n\ndefine KernelPackage/net-prism54\n  SUBMENU:=$(WIRELESS_MENU)\n  TITLE:=Intersil Prism54 support\n  DEPENDS:=@PCI_SUPPORT +@DRIVER_WEXT_SUPPORT +prism54-firmware\n  KCONFIG:=CONFIG_PRISM54\n  FILES:= \\\n\t$(LINUX_DIR)/drivers/net/wireless/intersil/prism54/prism54.ko\n  AUTOLOAD:=$(call AutoProbe,prism54)\nendef\n\ndefine KernelPackage/net-prism54/description\n Kernel modules for Intersil Prism54 support\nendef\n\n$(eval $(call KernelPackage,net-prism54))\n\n\ndefine KernelPackage/net-rtl8192su\n  SUBMENU:=$(WIRELESS_MENU)\n  TITLE:=RTL8192SU support (staging)\n  DEPENDS:=@USB_SUPPORT +@DRIVER_WEXT_SUPPORT +kmod-usb-core +rtl8192su-firmware\n  KCONFIG:=\\\n\tCONFIG_STAGING=y \\\n\tCONFIG_R8712U\n  FILES:=$(LINUX_DIR)/drivers/staging/rtl8712/r8712u.ko\n  AUTOLOAD:=$(call AutoProbe,r8712u)\nendef\n\ndefine KernelPackage/net-rtl8192su/description\n Kernel modules for RealTek RTL8712 and RTL81XXSU fullmac support.\nendef\n\n$(eval $(call KernelPackage,net-rtl8192su))\n"
  },
  {
    "path": "package/kernel/linux/modules/wpan.mk",
    "content": "#\n# Copyright (C) 2015 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n\nWPAN_MENU:=WPAN 802.15.4 Support\n\ndefine KernelPackage/ieee802154\n  SUBMENU:=$(WPAN_MENU)\n  TITLE:=IEEE-802.15.4 support\n  KCONFIG:= \\\n\tCONFIG_IEEE802154 \\\n\tCONFIG_IEEE802154_SOCKET=y \\\n\tCONFIG_IEEE802154_NL802154_EXPERIMENTAL=n\n  FILES:= \\\n\t$(LINUX_DIR)/net/ieee802154/ieee802154.ko \\\n\t$(LINUX_DIR)/net/ieee802154/ieee802154_socket.ko\n  AUTOLOAD:=$(call AutoLoad,90,ieee802154 ieee802154_socket)\nendef\n\ndefine KernelPackage/ieee802154/description\n  IEEE Std 802.15.4 defines a low data rate, low power and low\n  complexity short range wireless personal area networks. It was\n  designed to organise networks of sensors, switches, etc automation\n  devices. Maximum allowed data rate is 250 kb/s and typical personal\n  operating space around 10m.\nendef\n\n$(eval $(call KernelPackage,ieee802154))\n\ndefine KernelPackage/mac802154\n  SUBMENU:=$(WPAN_MENU)\n  TITLE:=MAC-802.15.4 support\n  DEPENDS:=+kmod-ieee802154 +kmod-crypto-aead +kmod-lib-crc-ccitt\n  KCONFIG:= \\\n\tCONFIG_MAC802154 \\\n\tCONFIG_IEEE802154_DRIVERS=y\n  FILES:=$(LINUX_DIR)/net/mac802154/mac802154.ko\n  AUTOLOAD:=$(call AutoLoad,91,mac802154)\nendef\n\ndefine KernelPackage/mac802154/description\n  This option enables the hardware independent IEEE 802.15.4\n  networking stack for SoftMAC devices (the ones implementing\n  only PHY level of IEEE 802.15.4 standard).\n\n  Note: this implementation is neither certified, nor feature\n  complete! Compatibility with other implementations hasn't\n  been tested yet!\nendef\n\n$(eval $(call KernelPackage,mac802154))\n\ndefine KernelPackage/fakelb\n  SUBMENU:=$(WPAN_MENU)\n  TITLE:=Fake LR-WPAN driver\n  DEPENDS:=+kmod-mac802154\n  KCONFIG:=CONFIG_IEEE802154_FAKELB\n  FILES:=$(LINUX_DIR)/drivers/net/ieee802154/fakelb.ko\n  AUTOLOAD:=$(call AutoLoad,92,fakelb)\nendef\n\ndefine KernelPackage/fakelb/description\n  Say Y here to enable the fake driver that can emulate a net\n  of several interconnected radio devices.\nendef\n\n$(eval $(call KernelPackage,fakelb))\n\ndefine KernelPackage/atusb\n  SUBMENU:=$(WPAN_MENU)\n  TITLE:=ATUSB transceiver driver\n  DEPENDS:=@USB_SUPPORT +kmod-usb-core +kmod-mac802154\n  KCONFIG:=CONFIG_IEEE802154_ATUSB\n  FILES:=$(LINUX_DIR)/drivers/net/ieee802154/atusb.ko\n  AUTOLOAD:=$(call AutoProbe,atusb)\nendef\n\n$(eval $(call KernelPackage,atusb))\n\ndefine KernelPackage/at86rf230\n  SUBMENU:=$(WPAN_MENU)\n  TITLE:=AT86RF230 transceiver driver\n  DEPENDS:=+kmod-mac802154 +kmod-regmap-spi\n  KCONFIG:=CONFIG_IEEE802154_AT86RF230 \\\n\tCONFIG_IEEE802154_AT86RF230_DEBUGFS=n \\\n\tCONFIG_SPI=y \\\n\tCONFIG_SPI_MASTER=y\n  FILES:=$(LINUX_DIR)/drivers/net/ieee802154/at86rf230.ko\n  AUTOLOAD:=$(call AutoProbe,at86rf230)\nendef\n\n$(eval $(call KernelPackage,at86rf230))\n\ndefine KernelPackage/mrf24j40\n  SUBMENU:=$(WPAN_MENU)\n  TITLE:=MRF24J40 transceiver driver\n  DEPENDS:=+kmod-mac802154 +kmod-regmap-spi\n  KCONFIG:=CONFIG_IEEE802154_MRF24J40 \\\n\tCONFIG_SPI=y \\\n\tCONFIG_SPI_MASTER=y\n  FILES:=$(LINUX_DIR)/drivers/net/ieee802154/mrf24j40.ko\n  AUTOLOAD:=$(call AutoProbe,mrf24j40)\nendef\n\n$(eval $(call KernelPackage,mrf24j40))\n\ndefine KernelPackage/cc2520\n  SUBMENU:=$(WPAN_MENU)\n  TITLE:=CC2520 transceiver driver\n  DEPENDS:=+kmod-mac802154\n  KCONFIG:=CONFIG_IEEE802154_CC2520 \\\n\tCONFIG_SPI=y \\\n\tCONFIG_SPI_MASTER=y\n  FILES:=$(LINUX_DIR)/drivers/net/ieee802154/cc2520.ko\n  AUTOLOAD:=$(call AutoProbe,cc2520)\nendef\n\n$(eval $(call KernelPackage,cc2520))\n\n\ndefine KernelPackage/ca8210\n  SUBMENU:=$(WPAN_MENU)\n  TITLE:=CA8210 transceiver driver\n  DEPENDS:=+kmod-mac802154\n  KCONFIG:=CONFIG_IEEE802154_CA8210 \\\n\tCONFIG_SPI=y \\\n\tCONFIG_SPI_MASTER=y \\\n\tCONFIG_IEEE802154_CA8210_DEBUGFS=n\n  FILES:=$(LINUX_DIR)/drivers/net/ieee802154/ca8210.ko\n  AUTOLOAD:=$(call AutoProbe,ca8210)\nendef\n\n$(eval $(call KernelPackage,ca8210))\n\n\ndefine KernelPackage/ieee802154-6lowpan\n  SUBMENU:=$(WPAN_MENU)\n  TITLE:= 6LoWPAN support over IEEE-802.15.4\n  DEPENDS:=+kmod-6lowpan +kmod-ieee802154\n  KCONFIG:=CONFIG_IEEE802154_6LOWPAN\n  FILES:= \\\n\t$(LINUX_DIR)/net/ieee802154/6lowpan/ieee802154_6lowpan.ko\n  AUTOLOAD:=$(call AutoLoad,91,ieee802154_6lowpan)\nendef\n\ndefine KernelPackage/ieee802154-6lowpan/description\n IPv6 compression over IEEE 802.15.4\nendef\n\n$(eval $(call KernelPackage,ieee802154-6lowpan))\n"
  },
  {
    "path": "package/kernel/mac80211/Makefile",
    "content": "#\n# Copyright (C) 2007-2015 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\ninclude $(INCLUDE_DIR)/kernel.mk\n\nPKG_NAME:=mac80211\n\nPKG_VERSION:=5.15.33-1\nPKG_RELEASE:=1\nPKG_SOURCE_URL:=@KERNEL/linux/kernel/projects/backports/stable/v5.15.33/\nPKG_HASH:=1b6b3bded4c81814ebebe2d194c2f8966d2399005b85ebb0557285b6e73f5422\n\nPKG_SOURCE:=backports-$(PKG_VERSION).tar.xz\nPKG_BUILD_DIR:=$(KERNEL_BUILD_DIR)/backports-$(PKG_VERSION)\nPKG_BUILD_PARALLEL:=1\n\nPKG_MAINTAINER:=Felix Fietkau <nbd@nbd.name>\n\nPKG_DRIVERS = \\\n\tadm8211 \\\n\thermes hermes-pci hermes-pcmcia hermes-plx\\\n\tlib80211 \\\n\tmac80211-hwsim \\\n\tmt7601u \\\n\tp54-common p54-pci p54-usb \\\n\trsi91x rsi91x-usb rsi91x-sdio\\\n\twlcore wl12xx wl18xx \\\n\tzd1211rw\n\nPKG_CONFIG_DEPENDS:= \\\n\tCONFIG_PACKAGE_kmod-mac80211 \\\n\tCONFIG_PACKAGE_CFG80211_TESTMODE \\\n\tCONFIG_PACKAGE_MAC80211_DEBUGFS \\\n\tCONFIG_PACKAGE_MAC80211_MESH \\\n\tCONFIG_PACKAGE_MAC80211_TRACING \\\n\tCONFIG_PACKAGE_IWLWIFI_DEBUG \\\n\tCONFIG_PACKAGE_IWLWIFI_DEBUGFS \\\n\tCONFIG_PACKAGE_RTLWIFI_DEBUG \\\n\ninclude $(INCLUDE_DIR)/package.mk\n\nWMENU:=Wireless Drivers\n\ndefine KernelPackage/mac80211/Default\n  SUBMENU:=$(WMENU)\n  URL:=https://wireless.wiki.kernel.org/\n  MAINTAINER:=Felix Fietkau <nbd@nbd.name>\nendef\n\nconfig_package=$(if $(CONFIG_PACKAGE_kmod-$(1)),m)\n\nconfig-y:= \\\n\tWLAN \\\n\tCFG80211_WEXT \\\n\tCFG80211_CERTIFICATION_ONUS \\\n\tMAC80211_RC_MINSTREL \\\n\tMAC80211_RC_MINSTREL_HT \\\n\tMAC80211_RC_MINSTREL_VHT \\\n\tMAC80211_RC_DEFAULT_MINSTREL \\\n\tWLAN_VENDOR_ADMTEK \\\n\tWLAN_VENDOR_ATH \\\n\tWLAN_VENDOR_ATMEL \\\n\tWLAN_VENDOR_BROADCOM \\\n\tWLAN_VENDOR_CISCO \\\n\tWLAN_VENDOR_INTEL \\\n\tWLAN_VENDOR_INTERSIL \\\n\tWLAN_VENDOR_MARVELL \\\n\tWLAN_VENDOR_MEDIATEK \\\n\tWLAN_VENDOR_RALINK \\\n\tWLAN_VENDOR_REALTEK \\\n\tWLAN_VENDOR_RSI \\\n\tWLAN_VENDOR_ST \\\n\tWLAN_VENDOR_TI \\\n\tWLAN_VENDOR_ZYDAS \\\n\nconfig-$(call config_package,cfg80211) += CFG80211\nconfig-$(CONFIG_PACKAGE_CFG80211_TESTMODE) += NL80211_TESTMODE\n\nconfig-$(call config_package,mac80211) += MAC80211\nconfig-$(CONFIG_PACKAGE_MAC80211_MESH) += MAC80211_MESH\n\ninclude ath.mk\ninclude broadcom.mk\ninclude intel.mk\ninclude marvell.mk\ninclude ralink.mk\ninclude realtek.mk\n\nPKG_CONFIG_DEPENDS += \\\n\t$(patsubst %,CONFIG_PACKAGE_kmod-%,$(PKG_DRIVERS))\n\ndefine KernelPackage/cfg80211\n  $(call KernelPackage/mac80211/Default)\n  TITLE:=cfg80211 - wireless configuration API\n  DEPENDS+= +iw +iwinfo +wireless-regdb +USE_RFKILL:kmod-rfkill\n  ABI_VERSION:=$(PKG_VERSION)-$(PKG_RELEASE)\n  FILES:= \\\n\t$(PKG_BUILD_DIR)/compat/compat.ko \\\n\t$(PKG_BUILD_DIR)/net/wireless/cfg80211.ko\nendef\n\ndefine KernelPackage/cfg80211/description\ncfg80211 is the Linux wireless LAN (802.11) configuration API.\nendef\n\ndefine KernelPackage/cfg80211/config\n  if PACKAGE_kmod-cfg80211\n\n\tconfig PACKAGE_CFG80211_TESTMODE\n\t\tbool \"Enable testmode command support\"\n\t\tdefault n\n\t\thelp\n\t\t  This is typically used for tests and calibration during\n\t\t  manufacturing, or vendor specific debugging features\n\n  endif\nendef\n\n\ndefine KernelPackage/mac80211\n  $(call KernelPackage/mac80211/Default)\n  TITLE:=Linux 802.11 Wireless Networking Stack\n  # +kmod-crypto-cmac is a runtime only dependency of net/mac80211/aes_cmac.c\n  DEPENDS+= +kmod-cfg80211 +kmod-crypto-cmac +kmod-crypto-ccm +kmod-crypto-gcm +hostapd-common\n  KCONFIG:=\\\n\tCONFIG_AVERAGE=y\n  FILES:= $(PKG_BUILD_DIR)/net/mac80211/mac80211.ko\n  ABI_VERSION:=$(PKG_VERSION)-$(PKG_RELEASE)\n  MENU:=1\nendef\n\ndefine KernelPackage/mac80211/config\n  if PACKAGE_kmod-mac80211\n\n\tconfig PACKAGE_MAC80211_DEBUGFS\n\t\tbool \"Export mac80211 internals in DebugFS\"\n\t\tselect KERNEL_DEBUG_FS\n\t\tdefault y\n\t\thelp\n\t\t  Select this to see extensive information about\n\t\t  the internal state of mac80211 in debugfs.\n\n\tconfig PACKAGE_MAC80211_TRACING\n\t\tbool \"Enable tracing (mac80211 and supported drivers)\"\n\t\tselect KERNEL_FTRACE\n\t\tselect KERNEL_ENABLE_DEFAULT_TRACERS\n\t\tdefault n\n\t\thelp\n\t\t  Select this to enable tracing of mac80211 and\n\t\t  related wifi drivers (using trace-cmd).\n\n\tconfig PACKAGE_MAC80211_MESH\n\t\tbool \"Enable 802.11s mesh support\"\n\t\tdefault y\n\n  endif\nendef\n\ndefine KernelPackage/mac80211/description\nGeneric IEEE 802.11 Networking Stack (mac80211)\nendef\n\ndefine KernelPackage/adm8211\n  $(call KernelPackage/mac80211/Default)\n  TITLE:=ADMTek 8211 support\n  DEPENDS+=@PCI_SUPPORT +kmod-mac80211 +kmod-eeprom-93cx6\n  FILES:=$(PKG_BUILD_DIR)/drivers/net/wireless/admtek/adm8211.ko\n  AUTOLOAD:=$(call AutoProbe,adm8211)\nendef\n\ndefine KernelPackage/hermes\n  $(call KernelPackage/mac80211/Default)\n  TITLE:=Hermes 802.11b chipset support\n  DEPENDS:=@PCI_SUPPORT||PCMCIA_SUPPORT +kmod-cfg80211 +@DRIVER_WEXT_SUPPORT +kmod-crypto-michael-mic\n  FILES:=$(PKG_BUILD_DIR)/drivers/net/wireless/intersil/orinoco/orinoco.ko\n  AUTOLOAD:=$(call AutoProbe,orinoco)\nendef\n\ndefine KernelPackage/hermes/description\n Kernel support for Hermes 802.11b chipsets\nendef\n\ndefine KernelPackage/hermes-pci\n  $(call KernelPackage/mac80211/Default)\n  TITLE:=Intersil Prism 2.5 PCI support\n  DEPENDS:=@PCI_SUPPORT +kmod-hermes\n  FILES:=$(PKG_BUILD_DIR)/drivers/net/wireless/intersil/orinoco/orinoco_pci.ko\n  AUTOLOAD:=$(call AutoProbe,orinoco_pci)\nendef\n\ndefine KernelPackage/hermes-pci/description\n Kernel modules for Intersil Prism 2.5 PCI support\nendef\n\ndefine KernelPackage/hermes-plx\n  $(call KernelPackage/mac80211/Default)\n  TITLE:=PLX9052 based PCI adaptor\n  DEPENDS:=@PCI_SUPPORT +kmod-hermes\n  FILES:=$(PKG_BUILD_DIR)/drivers/net/wireless/intersil/orinoco/orinoco_plx.ko\n  AUTOLOAD:=$(call AutoProbe,orinoco_plx)\nendef\n\ndefine KernelPackage/hermes-plx/description\n Kernel modules for Hermes in PLX9052 based PCI adaptors\nendef\n\ndefine KernelPackage/hermes-pcmcia\n  $(call KernelPackage/mac80211/Default)\n  TITLE:=Hermes based PCMCIA adaptors\n  DEPENDS:=@PCMCIA_SUPPORT +kmod-hermes +kmod-pcmcia-core\n  FILES:=$(PKG_BUILD_DIR)/drivers/net/wireless/intersil/orinoco/orinoco_cs.ko\n  AUTOLOAD:=$(call AutoProbe,orinoco_cs)\nendef\n\ndefine KernelPackage/hermes-pcmcia/description\n Kernel modules for Hermes based PCMCIA adaptors\nendef\n\n\ndefine KernelPackage/lib80211\n  $(call KernelPackage/mac80211/Default)\n  TITLE:=802.11 Networking stack\n  DEPENDS:=+kmod-cfg80211 +kmod-crypto-hash +kmod-crypto-ccm\n  FILES:= \\\n\t$(PKG_BUILD_DIR)/net/wireless/lib80211.ko \\\n\t$(PKG_BUILD_DIR)/net/wireless/lib80211_crypt_wep.ko \\\n\t$(PKG_BUILD_DIR)/net/wireless/lib80211_crypt_ccmp.ko \\\n\t$(PKG_BUILD_DIR)/net/wireless/lib80211_crypt_tkip.ko\n  AUTOLOAD:=$(call AutoProbe, \\\n\tlib80211 \\\n\tlib80211_crypt_wep \\\n\tlib80211_crypt_ccmp \\\n\tlib80211_crypt_tkip \\\n  )\nendef\n\ndefine KernelPackage/lib80211/description\n Kernel modules for 802.11 Networking stack\n Includes:\n - lib80211\n - lib80211_crypt_wep\n - lib80211_crypt_tkip\n - lib80211_crytp_ccmp\nendef\n\n\ndefine KernelPackage/mac80211-hwsim\n  $(call KernelPackage/mac80211/Default)\n  TITLE:=mac80211 HW simulation device\n  DEPENDS+= +kmod-mac80211 +@DRIVER_11AC_SUPPORT +@DRIVER_11N_SUPPORT\n  FILES:=$(PKG_BUILD_DIR)/drivers/net/wireless/mac80211_hwsim.ko\n  AUTOLOAD:=$(call AutoProbe,mac80211_hwsim)\nendef\n\n\ndefine KernelPackage/mt7601u\n  $(call KernelPackage/mac80211/Default)\n  TITLE:=MT7601U-based USB dongles Wireless Driver\n  DEPENDS+= +kmod-mac80211 +@DRIVER_11N_SUPPORT @USB_SUPPORT +kmod-usb-core +mt7601u-firmware\n  FILES:=$(PKG_BUILD_DIR)/drivers/net/wireless/mediatek/mt7601u/mt7601u.ko\n  AUTOLOAD:=$(call AutoProbe,mt7601u)\nendef\n\ndefine KernelPackage/p54/Default\n  $(call KernelPackage/mac80211/Default)\n  TITLE:=Prism54 Drivers\nendef\n\ndefine KernelPackage/p54/description\n  Kernel module for Prism54 chipsets (mac80211)\nendef\n\ndefine KernelPackage/p54-common\n  $(call KernelPackage/p54/Default)\n  DEPENDS+= @(PCI_SUPPORT||USB_SUPPORT) +kmod-mac80211 +kmod-lib-crc-ccitt\n  TITLE+= (COMMON)\n  FILES:=$(PKG_BUILD_DIR)/drivers/net/wireless/intersil/p54/p54common.ko\nendef\n\ndefine KernelPackage/p54-pci\n  $(call KernelPackage/p54/Default)\n  TITLE+= (PCI)\n  DEPENDS+= @PCI_SUPPORT +kmod-p54-common +p54-pci-firmware\n  FILES:=$(PKG_BUILD_DIR)/drivers/net/wireless/intersil/p54/p54pci.ko\n  AUTOLOAD:=$(call AutoProbe,p54pci)\nendef\n\ndefine KernelPackage/p54-usb\n  $(call KernelPackage/p54/Default)\n  TITLE+= (USB)\n  DEPENDS+= @USB_SUPPORT +kmod-usb-core +kmod-p54-common +p54-usb-firmware\n  FILES:=$(PKG_BUILD_DIR)/drivers/net/wireless/intersil/p54/p54usb.ko\n  AUTOLOAD:=$(call AutoProbe,p54usb)\nendef\n\ndefine KernelPackage/rsi91x\n  $(call KernelPackage/mac80211/Default)\n  TITLE:=Redpine Signals Inc 91x WLAN driver support\n  DEPENDS+= +kmod-mac80211 +rs9113-firmware +@DRIVER_11N_SUPPORT\n  FILES:=$(PKG_BUILD_DIR)/drivers/net/wireless/rsi/rsi_91x.ko\nendef\n\ndefine KernelPackage/rsi91x-usb\n  $(call KernelPackage/mac80211/Default)\n  TITLE:=Redpine Signals USB bus support\n  DEPENDS+=@USB_SUPPORT +kmod-usb-core +kmod-mac80211 +kmod-rsi91x +rs9113-firmware\n  FILES:=$(PKG_BUILD_DIR)/drivers/net/wireless/rsi/rsi_usb.ko\n  AUTOLOAD:=$(call AutoProbe,rsi_usb)\nendef\n\ndefine KernelPackage/rsi91x-sdio\n  $(call KernelPackage/mac80211/Default)\n  TITLE:=Redpine Signals SDIO bus support\n  DEPENDS+= +kmod-mac80211 +kmod-mmc +kmod-rsi91x +rs9113-firmware\n  FILES:=$(PKG_BUILD_DIR)/drivers/net/wireless/rsi/rsi_sdio.ko\n  AUTOLOAD:=$(call AutoProbe,rsi_sdio)\nendef\n\n\ndefine KernelPackage/wlcore\n  $(call KernelPackage/mac80211/Default)\n  TITLE:=TI common driver part\n  DEPENDS+= +kmod-mmc +kmod-mac80211 +@DRIVER_11N_SUPPORT\n  FILES:= \\\n\t$(PKG_BUILD_DIR)/drivers/net/wireless/ti/wlcore/wlcore.ko \\\n\t$(PKG_BUILD_DIR)/drivers/net/wireless/ti/wlcore/wlcore_sdio.ko\n  AUTOLOAD:=$(call AutoProbe,wlcore wlcore_sdio)\nendef\n\ndefine KernelPackage/wlcore/description\n This module contains some common parts needed by TI Wireless drivers.\nendef\n\ndefine KernelPackage/wl12xx\n  $(call KernelPackage/mac80211/Default)\n  TITLE:=Driver for TI WL12xx\n  URL:=https://wireless.wiki.kernel.org/en/users/drivers/wl12xx\n  DEPENDS+= +kmod-wlcore +wl12xx-firmware\n  FILES:=$(PKG_BUILD_DIR)/drivers/net/wireless/ti/wl12xx/wl12xx.ko\n  AUTOLOAD:=$(call AutoProbe,wl12xx)\nendef\n\ndefine KernelPackage/wl12xx/description\n Kernel modules for TI WL12xx\nendef\n\ndefine KernelPackage/wl18xx\n  $(call KernelPackage/mac80211/Default)\n  TITLE:=Driver for TI WL18xx\n  URL:=https://wireless.wiki.kernel.org/en/users/drivers/wl18xx\n  DEPENDS+= +kmod-wlcore +wl18xx-firmware\n  FILES:=$(PKG_BUILD_DIR)/drivers/net/wireless/ti/wl18xx/wl18xx.ko\n  AUTOLOAD:=$(call AutoProbe,wl18xx)\nendef\n\ndefine KernelPackage/wl18xx/description\n Kernel modules for TI WL18xx\nendef\n\n\nZD1211FW_NAME:=zd1211-firmware\nZD1211FW_VERSION:=1.4\ndefine Download/zd1211rw\n  FILE:=$(ZD1211FW_NAME)-$(ZD1211FW_VERSION).tar.bz2\n  URL:=@SF/zd1211/\n  HASH:=866308f6f59f7075f075d4959dff2ede47735c751251fecd1496df1ba4d338e1\nendef\n$(eval $(call Download,zd1211rw))\n\ndefine KernelPackage/zd1211rw\n  $(call KernelPackage/mac80211/Default)\n  TITLE:=Zydas ZD1211 support\n  DEPENDS+= @USB_SUPPORT +kmod-usb-core +kmod-mac80211\n  FILES:=$(PKG_BUILD_DIR)/drivers/net/wireless/zydas/zd1211rw/zd1211rw.ko\n  AUTOLOAD:=$(call AutoProbe,zd1211rw)\nendef\n\nifdef CONFIG_PACKAGE_MAC80211_DEBUGFS\n  config-y += \\\n\tCFG80211_DEBUGFS \\\n\tMAC80211_DEBUGFS\nendif\n\nifdef CONFIG_PACKAGE_MAC80211_TRACING\n  config-y += \\\n\tIWLWIFI_DEVICE_TRACING\nendif\n\nconfig-$(call config_package,lib80211) += LIB80211 LIB80211_CRYPT_WEP LIB80211_CRYPT_CCMP LIB80211_CRYPT_TKIP\n\nconfig-$(call config_package,mac80211-hwsim) += MAC80211_HWSIM\nconfig-$(call config_package,mt7601u) += MT7601U\nconfig-y += WL_MEDIATEK\n\nconfig-$(call config_package,p54-common) += P54_COMMON\nconfig-$(call config_package,p54-pci) += P54_PCI\nconfig-$(call config_package,p54-usb) += P54_USB\n\nconfig-$(call config_package,hermes) += HERMES\nconfig-$(call config_package,hermes-pci) += PCI_HERMES\nconfig-$(call config_package,hermes-plx) += PLX_HERMES\nconfig-$(call config_package,hermes-pcmcia) += PCMCIA_HERMES\nconfig-y += HERMES_PRISM\n\nconfig-$(call config_package,adm8211) += ADM8211\nconfig-$(call config_package,wlcore) += WLCORE WLCORE_SDIO\nconfig-$(call config_package,wl12xx) += WL12XX\nconfig-$(call config_package,wl18xx) += WL18XX\nconfig-y += WL_TI WILINK_PLATFORM_DATA\nconfig-$(call config_package,zd1211rw) += ZD1211RW\nconfig-$(call config_package,rsi91x) += RSI_91X\nconfig-$(call config_package,rsi91x-usb) += RSI_USB\nconfig-$(call config_package,rsi91x-sdio) += RSI_SDIO\n\nconfig-$(CONFIG_LEDS_TRIGGERS) += MAC80211_LEDS\n\nC_DEFINES=\n\nifeq ($(BUILD_VARIANT),smallbuffers)\n\tC_DEFINES+= -DCONFIG_ATH10K_SMALLBUFFERS\nendif\n\nMAKE_OPTS:= -C \"$(PKG_BUILD_DIR)\" \\\n\t$(KERNEL_MAKE_FLAGS) \\\n\tEXTRA_CFLAGS=\"-I$(PKG_BUILD_DIR)/include $(IREMAP_CFLAGS) $(C_DEFINES)\" \\\n\tKLIB_BUILD=\"$(LINUX_DIR)\" \\\n\tMODPROBE=true \\\n\tKLIB=$(TARGET_MODULES_DIR) \\\n\tKERNEL_SUBLEVEL=$(lastword $(subst ., ,$(KERNEL_PATCHVER))) \\\n\tKBUILD_LDFLAGS_MODULE_PREREQ=\n\ndefine ConfigVars\n$(subst $(space),,$(foreach opt,$(config-$(1)),CPTCFG_$(opt)=$(1)\n))\nendef\n\ndefine mac80211_config\n$(call ConfigVars,m)$(call ConfigVars,y)\nendef\n$(eval $(call shexport,mac80211_config))\n\ndefine Build/Prepare\n\trm -rf $(PKG_BUILD_DIR)\n\tmkdir -p $(PKG_BUILD_DIR)\n\t$(PKG_UNPACK)\n\t$(Build/Patch)\n\t$(TAR) -C $(PKG_BUILD_DIR) -xzf $(DL_DIR)/$(IPW2100_NAME)-$(IPW2100_VERSION).tgz\n\t$(TAR) -C $(PKG_BUILD_DIR) -xzf $(DL_DIR)/$(IPW2200_NAME)-$(IPW2200_VERSION).tgz\n\t$(TAR) -C $(PKG_BUILD_DIR) -xjf $(DL_DIR)/$(ZD1211FW_NAME)-$(ZD1211FW_VERSION).tar.bz2\n\trm -rf \\\n\t\t$(PKG_BUILD_DIR)/include/linux/ssb \\\n\t\t$(PKG_BUILD_DIR)/include/linux/bcma \\\n\t\t$(PKG_BUILD_DIR)/include/net/bluetooth\n\n\trm -f \\\n\t\t$(PKG_BUILD_DIR)/include/linux/cordic.h \\\n\t\t$(PKG_BUILD_DIR)/include/linux/crc8.h \\\n\t\t$(PKG_BUILD_DIR)/include/linux/eeprom_93cx6.h \\\n\t\t$(PKG_BUILD_DIR)/include/linux/wl12xx.h \\\n\t\t$(PKG_BUILD_DIR)/include/linux/spi/libertas_spi.h \\\n\t\t$(PKG_BUILD_DIR)/include/net/ieee80211.h \\\n\t\t$(PKG_BUILD_DIR)/backport-include/linux/bcm47xx_nvram.h\n\n\techo 'compat-wireless-$(PKG_VERSION)-$(PKG_RELEASE)-$(REVISION)' > $(PKG_BUILD_DIR)/compat_version\nendef\n\nifneq ($(CONFIG_PACKAGE_kmod-cfg80211)$(CONFIG_PACKAGE_kmod-lib80211),)\n define Build/Compile/kmod\n\trm -rf $(PKG_BUILD_DIR)/modules\n\t+$(MAKE) $(PKG_JOBS) $(MAKE_OPTS) modules\n endef\nendif\n\n#do not Build/Configure for EXTERNAL KERNEL\nifeq ($(strip $(CONFIG_EXTERNAL_KERNEL_TREE)),\"\")\n  ifeq ($(strip $(CONFIG_KERNEL_GIT_CLONE_URI)),\"\")\n    define Build/Configure\n\t  cmp $(PKG_BUILD_DIR)/include/linux/ath9k_platform.h $(LINUX_DIR)/include/linux/ath9k_platform.h\n\t  cmp $(PKG_BUILD_DIR)/include/linux/ath5k_platform.h $(LINUX_DIR)/include/linux/ath5k_platform.h\n\t  cmp $(PKG_BUILD_DIR)/include/linux/rt2x00_platform.h $(LINUX_DIR)/include/linux/rt2x00_platform.h\n    endef\n  endif\nendif\n\ndefine Build/Patch\n\t$(if $(QUILT),rm -rf $(PKG_BUILD_DIR)/patches; mkdir -p $(PKG_BUILD_DIR)/patches)\n\t$(call PatchDir,$(PKG_BUILD_DIR),$(PATCH_DIR)/build,build/)\n\t$(call PatchDir,$(PKG_BUILD_DIR),$(PATCH_DIR)/subsys,subsys/)\n\t$(call PatchDir,$(PKG_BUILD_DIR),$(PATCH_DIR)/ath,ath/)\n\t$(call PatchDir,$(PKG_BUILD_DIR),$(PATCH_DIR)/ath5k,ath5k/)\n\t$(call PatchDir,$(PKG_BUILD_DIR),$(PATCH_DIR)/ath9k,ath9k/)\n\t$(call PatchDir,$(PKG_BUILD_DIR),$(PATCH_DIR)/ath10k,ath10k/)\n\t$(call PatchDir,$(PKG_BUILD_DIR),$(PATCH_DIR)/ath11k,ath11k/)\n\t$(call PatchDir,$(PKG_BUILD_DIR),$(PATCH_DIR)/rt2x00,rt2x00/)\n\t$(call PatchDir,$(PKG_BUILD_DIR),$(PATCH_DIR)/mwl,mwl/)\n\t$(call PatchDir,$(PKG_BUILD_DIR),$(PATCH_DIR)/brcm,brcm/)\n\t$(call PatchDir,$(PKG_BUILD_DIR),$(PATCH_DIR)/rtl,rtl/)\n\t$(if $(QUILT),touch $(PKG_BUILD_DIR)/.quilt_used)\nendef\n\ndefine Quilt/Refresh/Package\n\t$(call Quilt/RefreshDir,$(PKG_BUILD_DIR),$(PATCH_DIR)/build,build/)\n\t$(call Quilt/RefreshDir,$(PKG_BUILD_DIR),$(PATCH_DIR)/subsys,subsys/)\n\t$(call Quilt/RefreshDir,$(PKG_BUILD_DIR),$(PATCH_DIR)/ath,ath/)\n\t$(call Quilt/RefreshDir,$(PKG_BUILD_DIR),$(PATCH_DIR)/ath5k,ath5k/)\n\t$(call Quilt/RefreshDir,$(PKG_BUILD_DIR),$(PATCH_DIR)/ath9k,ath9k/)\n\t$(call Quilt/RefreshDir,$(PKG_BUILD_DIR),$(PATCH_DIR)/ath10k,ath10k/)\n\t$(call Quilt/RefreshDir,$(PKG_BUILD_DIR),$(PATCH_DIR)/ath11k,ath11k/)\n\t$(call Quilt/RefreshDir,$(PKG_BUILD_DIR),$(PATCH_DIR)/rt2x00,rt2x00/)\n\t$(call Quilt/RefreshDir,$(PKG_BUILD_DIR),$(PATCH_DIR)/mwl,mwl/)\n\t$(call Quilt/RefreshDir,$(PKG_BUILD_DIR),$(PATCH_DIR)/brcm,brcm/)\n\t$(call Quilt/RefreshDir,$(PKG_BUILD_DIR),$(PATCH_DIR)/rtl,rtl/)\nendef\n\ndefine Build/Compile\n\t$(SH_FUNC) var2file \"$(call shvar,mac80211_config)\" $(PKG_BUILD_DIR)/.config\n\t$(MAKE) $(MAKE_OPTS) allnoconfig\n\t$(call Build/Compile/kmod)\nendef\n\ndefine Build/InstallDev\n\tmkdir -p \\\n\t\t$(1)/usr/include/mac80211 \\\n\t\t$(1)/usr/include/mac80211-backport \\\n\t\t$(1)/usr/include/mac80211/ath \\\n\t\t$(1)/usr/include/net/mac80211\n\t$(CP) $(PKG_BUILD_DIR)/net/mac80211/*.h $(PKG_BUILD_DIR)/include/* $(1)/usr/include/mac80211/\n\t$(CP) $(PKG_BUILD_DIR)/backport-include/* $(1)/usr/include/mac80211-backport/\n\t$(CP) $(PKG_BUILD_DIR)/net/mac80211/rate.h $(1)/usr/include/net/mac80211/\n\t$(CP) $(PKG_BUILD_DIR)/drivers/net/wireless/ath/*.h $(1)/usr/include/mac80211/ath/\n\trm -f $(1)/usr/include/mac80211-backport/linux/module.h\nendef\n\n\ndefine KernelPackage/cfg80211/install\n\t$(INSTALL_DIR) $(1)/lib/wifi $(1)/lib/netifd/wireless\n\t$(INSTALL_DATA) ./files/lib/wifi/mac80211.sh $(1)/lib/wifi\n\t$(INSTALL_BIN) ./files/lib/netifd/wireless/mac80211.sh $(1)/lib/netifd/wireless\n\t$(INSTALL_DIR) $(1)/etc/hotplug.d/ieee80211\n\t$(INSTALL_DATA) ./files/mac80211.hotplug $(1)/etc/hotplug.d/ieee80211/10-wifi-detect\nendef\n\ndefine KernelPackage/zd1211rw/install\n\t$(INSTALL_DIR) $(1)/lib/firmware/zd1211\n\t$(INSTALL_DATA) $(PKG_BUILD_DIR)/$(ZD1211FW_NAME)/zd1211* $(1)/lib/firmware/zd1211\nendef\n\n$(eval $(foreach drv,$(PKG_DRIVERS),$(call KernelPackage,$(drv))))\n$(eval $(call KernelPackage,cfg80211))\n$(eval $(call KernelPackage,mac80211))\n"
  },
  {
    "path": "package/kernel/mac80211/ath.mk",
    "content": "PKG_DRIVERS += \\\n\tath ath5k ath6kl ath6kl-sdio ath6kl-usb ath9k ath9k-common ath9k-htc ath10k ath10k-smallbuffers \\\n\tcarl9170 owl-loader ar5523 wil6210\n\nPKG_CONFIG_DEPENDS += \\\n\tCONFIG_PACKAGE_ATH_DEBUG \\\n\tCONFIG_PACKAGE_ATH_DFS \\\n\tCONFIG_PACKAGE_ATH_SPECTRAL \\\n\tCONFIG_PACKAGE_ATH_DYNACK \\\n\tCONFIG_ATH9K_HWRNG \\\n\tCONFIG_ATH9K_SUPPORT_PCOEM \\\n\tCONFIG_ATH9K_TX99 \\\n\tCONFIG_ATH10K_LEDS \\\n\tCONFIG_ATH10K_THERMAL \\\n\tCONFIG_ATH_USER_REGD\n\nifdef CONFIG_PACKAGE_MAC80211_DEBUGFS\n  config-y += \\\n\tATH9K_DEBUGFS \\\n\tATH9K_HTC_DEBUGFS \\\n\tATH10K_DEBUGFS \\\n\tCARL9170_DEBUGFS \\\n\tATH5K_DEBUG \\\n\tATH6KL_DEBUG \\\n\tWIL6210_DEBUGFS\nendif\n\nifdef CONFIG_PACKAGE_MAC80211_TRACING\n  config-y += \\\n\tATH10K_TRACING \\\n\tATH6KL_TRACING \\\n\tATH_TRACEPOINTS \\\n\tATH5K_TRACER \\\n\tWIL6210_TRACING\nendif\n\nconfig-$(call config_package,ath) += ATH_CARDS ATH_COMMON\nconfig-$(CONFIG_PACKAGE_ATH_DEBUG) += ATH_DEBUG ATH10K_DEBUG ATH9K_STATION_STATISTICS\nconfig-$(CONFIG_PACKAGE_ATH_DFS) += ATH9K_DFS_CERTIFIED ATH10K_DFS_CERTIFIED\nconfig-$(CONFIG_PACKAGE_ATH_SPECTRAL) += ATH9K_COMMON_SPECTRAL ATH10K_SPECTRAL\nconfig-$(CONFIG_PACKAGE_ATH_DYNACK) += ATH9K_DYNACK\nconfig-$(call config_package,ath9k) += ATH9K\nconfig-$(call config_package,ath9k-common) += ATH9K_COMMON\nconfig-$(call config_package,owl-loader) += ATH9K_PCI_NO_EEPROM\nconfig-$(CONFIG_TARGET_ath79) += ATH9K_AHB\nconfig-$(CONFIG_TARGET_ipq40xx) += ATH10K_AHB\nconfig-$(CONFIG_PCI) += ATH9K_PCI\nconfig-$(CONFIG_ATH_USER_REGD) += ATH_USER_REGD ATH_REG_DYNAMIC_USER_REG_HINTS\nconfig-$(CONFIG_ATH9K_HWRNG) += ATH9K_HWRNG\nconfig-$(CONFIG_ATH9K_SUPPORT_PCOEM) += ATH9K_PCOEM\nconfig-$(CONFIG_ATH9K_TX99) += ATH9K_TX99\nconfig-$(CONFIG_ATH9K_UBNTHSR) += ATH9K_UBNTHSR\nconfig-$(CONFIG_ATH10K_LEDS) += ATH10K_LEDS\nconfig-$(CONFIG_ATH10K_THERMAL) += ATH10K_THERMAL\n\nconfig-$(call config_package,ath9k-htc) += ATH9K_HTC\nconfig-$(call config_package,ath10k) += ATH10K ATH10K_PCI\nconfig-$(call config_package,ath10k-smallbuffers) += ATH10K ATH10K_PCI ATH10K_SMALLBUFFERS\n\nconfig-$(call config_package,ath5k) += ATH5K\nifdef CONFIG_TARGET_ath25\n  config-y += ATH5K_AHB\nelse\n  config-y += ATH5K_PCI\nendif\n\nconfig-$(call config_package,ath6kl) += ATH6KL\nconfig-$(call config_package,ath6kl-sdio) += ATH6KL_SDIO\nconfig-$(call config_package,ath6kl-usb) += ATH6KL_USB\n\nconfig-$(call config_package,carl9170) += CARL9170\nconfig-$(call config_package,ar5523) += AR5523\n\nconfig-$(call config_package,wil6210) += WIL6210\n\ndefine KernelPackage/ath/config\n  if PACKAGE_kmod-ath\n\tconfig ATH_USER_REGD\n\t\tbool \"Force Atheros drivers to respect the user's regdomain settings\"\n\t\tdefault y\n\t\thelp\n\t\t  Atheros' idea of regulatory handling is that the EEPROM of the card defines\n\t\t  the regulatory limits and the user is only allowed to restrict the settings\n\t\t  even further, even if the country allows frequencies or power levels that\n\t\t  are forbidden by the EEPROM settings.\n\n\t\t  Select this option if you want the driver to respect the user's decision about\n\t\t  regulatory settings.\n\n\tconfig PACKAGE_ATH_DEBUG\n\t\tbool \"Atheros wireless debugging\"\n\t\thelp\n\t\t  Say Y, if you want to debug atheros wireless drivers.\n\t\t  Only ath9k & ath10k make use of this.\n\n\tconfig PACKAGE_ATH_DFS\n\t\tbool \"Enable DFS support\"\n\t\tdefault y\n\t\thelp\n\t\t  Dynamic frequency selection (DFS) is required for most of the 5 GHz band\n\t\t  channels in Europe, US, and Japan.\n\n\t\t  Select this option if you want to use such channels.\n\n\tconfig PACKAGE_ATH_SPECTRAL\n\t\tbool \"Atheros spectral scan support\"\n\t\tdepends on PACKAGE_ATH_DEBUG\n\t\tselect KERNEL_RELAY\n\t\thelp\n\t\t  Say Y to enable access to the FFT/spectral data via debugfs.\n\n\tconfig PACKAGE_ATH_DYNACK\n\t\tbool \"Enable Dynack support\"\n\t\tdepends on PACKAGE_kmod-ath9k-common\n\t\thelp\n\t\t  Enables support for Dynamic ACK estimation, which allows the fastest possible speed\n\t\t  at any distance automatically by increasing/decreasing the max frame ACK time for\n\t\t  the most remote station detected.  It can be enabled by using iw (iw phy0 set distance auto),\n\t\t  or by sending the NL80211_ATTR_WIPHY_DYN_ACK flag to mac80211 driver using netlink.\n\n\t\t  Select this option if you want to enable this feature\n\n  endif\nendef\n\ndefine KernelPackage/ath\n  $(call KernelPackage/mac80211/Default)\n  TITLE:=Atheros common driver part\n  DEPENDS+= @PCI_SUPPORT||USB_SUPPORT||TARGET_ath79||TARGET_ath25 +kmod-mac80211\n  FILES:=$(PKG_BUILD_DIR)/drivers/net/wireless/ath/ath.ko\n  MENU:=1\nendef\n\ndefine KernelPackage/ath/description\n This module contains some common parts needed by Atheros Wireless drivers.\nendef\n\ndefine KernelPackage/ath5k\n  $(call KernelPackage/mac80211/Default)\n  TITLE:=Atheros 5xxx wireless cards support\n  URL:=https://wireless.wiki.kernel.org/en/users/drivers/ath5k\n  DEPENDS+= @(PCI_SUPPORT||TARGET_ath25) +kmod-ath\n  FILES:=$(PKG_BUILD_DIR)/drivers/net/wireless/ath/ath5k/ath5k.ko\n  AUTOLOAD:=$(call AutoProbe,ath5k)\nendef\n\ndefine KernelPackage/ath5k/description\n This module adds support for wireless adapters based on\n Atheros 5xxx chipset.\nendef\n\ndefine KernelPackage/ath6kl\n  $(call KernelPackage/mac80211/Default)\n  TITLE:=Atheros FullMAC wireless devices (common code for ath6kl_sdio and ath6kl_usb)\n  URL:=https://wireless.wiki.kernel.org/en/users/drivers/ath6kl\n  HIDDEN:=1\n  DEPENDS+= +kmod-ath +@DRIVER_11N_SUPPORT\n  FILES:= $(PKG_BUILD_DIR)/drivers/net/wireless/ath/ath6kl/ath6kl_core.ko\nendef\n\ndefine KernelPackage/ath6kl-sdio\n  $(call KernelPackage/mac80211/Default)\n  TITLE:=Atheros 802.11n SDIO wireless cards support\n  URL:=https://wireless.wiki.kernel.org/en/users/drivers/ath6kl\n  DEPENDS+= +kmod-mmc +kmod-ath6kl\n  FILES:= $(PKG_BUILD_DIR)/drivers/net/wireless/ath/ath6kl/ath6kl_sdio.ko\n  AUTOLOAD:=$(call AutoProbe,ath6kl_sdio)\nendef\n\ndefine KernelPackage/ath6kl-sdio/description\nThis module adds support for wireless adapters based on\nAtheros IEEE 802.11n AR6003 and AR6004 family of chipsets.\nendef\n\ndefine KernelPackage/ath6kl-usb\n  $(call KernelPackage/mac80211/Default)\n  TITLE:=Atheros 802.11n USB wireless cards support\n  URL:=https://wireless.wiki.kernel.org/en/users/drivers/ath6kl\n  DEPENDS+= @USB_SUPPORT +kmod-usb-core +kmod-ath6kl\n  FILES:= $(PKG_BUILD_DIR)/drivers/net/wireless/ath/ath6kl/ath6kl_usb.ko\n  AUTOLOAD:=$(call AutoProbe,ath6kl_usb)\nendef\n\ndefine KernelPackage/ath6kl-usb/description\nThis module adds support for wireless adapters based on the\nAtheros IEEE 802.11n AR6004 chipset.\nendef\n\ndefine KernelPackage/ath9k-common\n  $(call KernelPackage/mac80211/Default)\n  TITLE:=Atheros 802.11n wireless devices (common code for ath9k and ath9k_htc)\n  URL:=https://wireless.wiki.kernel.org/en/users/drivers/ath9k\n  HIDDEN:=1\n  DEPENDS+= @PCI_SUPPORT||USB_SUPPORT||TARGET_ath79 +kmod-ath +@DRIVER_11N_SUPPORT\n  FILES:= \\\n\t$(PKG_BUILD_DIR)/drivers/net/wireless/ath/ath9k/ath9k_common.ko \\\n\t$(PKG_BUILD_DIR)/drivers/net/wireless/ath/ath9k/ath9k_hw.ko\nendef\n\ndefine KernelPackage/ath9k\n  $(call KernelPackage/mac80211/Default)\n  TITLE:=Atheros 802.11n PCI wireless cards support\n  URL:=https://wireless.wiki.kernel.org/en/users/drivers/ath9k\n  DEPENDS+= @PCI_SUPPORT||TARGET_ath79 +kmod-ath9k-common\n  FILES:= \\\n\t$(PKG_BUILD_DIR)/drivers/net/wireless/ath/ath9k/ath9k.ko\n  AUTOLOAD:=$(call AutoProbe,ath9k)\nendef\n\ndefine KernelPackage/ath9k/description\nThis module adds support for wireless adapters based on\nAtheros IEEE 802.11n AR5008 and AR9001 family of chipsets.\nendef\n\ndefine KernelPackage/ath9k/config\n\n\tconfig ATH9K_HWRNG\n\t\tbool \"Add wireless noise as source of randomness to kernel entropy pool\"\n\t\tdepends on PACKAGE_kmod-ath9k\n\t\tselect PACKAGE_kmod-random-core\n\t\tdefault n\n\n\tconfig ATH9K_SUPPORT_PCOEM\n\t\tbool \"Support chips used in PC OEM cards\"\n\t\tdepends on PACKAGE_kmod-ath9k\n\t\tdefault y if (x86_64 || i386)\n\n       config ATH9K_TX99\n               bool \"Enable TX99 support (WARNING: testing only, breaks normal operation!)\"\n               depends on PACKAGE_kmod-ath9k\n\n\tconfig ATH9K_UBNTHSR\n\t\tbool \"Support for Ubiquiti UniFi Outdoor+ access point\"\n\t\tdepends on PACKAGE_kmod-ath9k && TARGET_ath79\n\t\tdefault y\n\nendef\n\ndefine KernelPackage/ath9k-htc\n  $(call KernelPackage/mac80211/Default)\n  TITLE:=Atheros 802.11n USB device support\n  URL:=https://wireless.wiki.kernel.org/en/users/drivers/ath9k\n  DEPENDS+= @USB_SUPPORT +kmod-ath9k-common +kmod-usb-core +ath9k-htc-firmware\n  FILES:= \\\n\t$(PKG_BUILD_DIR)/drivers/net/wireless/ath/ath9k/ath9k_htc.ko\n  AUTOLOAD:=$(call AutoProbe,ath9k_htc)\nendef\n\ndefine KernelPackage/ath9k-htc/description\nThis module adds support for wireless adapters based on\nAtheros USB AR9271 and AR7010 family of chipsets.\nendef\n\ndefine KernelPackage/ath10k\n  $(call KernelPackage/mac80211/Default)\n  TITLE:=Atheros 802.11ac wireless cards support\n  URL:=https://wireless.wiki.kernel.org/en/users/drivers/ath10k\n  DEPENDS+= @PCI_SUPPORT +kmod-ath +@DRIVER_11N_SUPPORT +@DRIVER_11AC_SUPPORT \\\n\t+ATH10K_THERMAL:kmod-hwmon-core +ATH10K_THERMAL:kmod-thermal\n  FILES:= \\\n\t$(PKG_BUILD_DIR)/drivers/net/wireless/ath/ath10k/ath10k_core.ko \\\n\t$(PKG_BUILD_DIR)/drivers/net/wireless/ath/ath10k/ath10k_pci.ko\n  AUTOLOAD:=$(call AutoProbe,ath10k_pci)\n  VARIANT:=regular\nendef\n\ndefine KernelPackage/ath10k/description\nThis module adds support for wireless adapters based on\nAtheros IEEE 802.11ac family of chipsets. For now only\nPCI is supported.\nendef\n\ndefine KernelPackage/ath10k/config\n\n       config ATH10K_LEDS\n               bool \"Enable LED support\"\n               default y\n               depends on PACKAGE_kmod-ath10k || PACKAGE_kmod-ath10k-smallbuffers\n\n       config ATH10K_THERMAL\n               bool \"Enable thermal sensors and throttling support\"\n               depends on PACKAGE_kmod-ath10k || PACKAGE_kmod-ath10k-smallbuffers\n\nendef\n\ndefine KernelPackage/ath10k-smallbuffers\n  $(call KernelPackage/ath10k)\n  TITLE+= (small buffers for low-RAM devices)\n  VARIANT:=smallbuffers\nendef\n\ndefine KernelPackage/carl9170\n  $(call KernelPackage/mac80211/Default)\n  TITLE:=Driver for Atheros AR9170 USB sticks\n  DEPENDS:=@USB_SUPPORT +kmod-mac80211 +kmod-ath +kmod-usb-core +kmod-input-core +@DRIVER_11N_SUPPORT +carl9170-firmware\n  FILES:=$(PKG_BUILD_DIR)/drivers/net/wireless/ath/carl9170/carl9170.ko\n  AUTOLOAD:=$(call AutoProbe,carl9170)\nendef\n\ndefine KernelPackage/owl-loader\n  $(call KernelPackage/mac80211/Default)\n  TITLE:=Owl loader for initializing Atheros PCI(e) Wifi chips\n  DEPENDS:=@PCI_SUPPORT +kmod-ath9k\n  FILES:=$(PKG_BUILD_DIR)/drivers/net/wireless/ath/ath9k/ath9k_pci_owl_loader.ko\n  AUTOLOAD:=$(call AutoProbe,ath9k_pci_owl_loader)\nendef\n\ndefine KernelPackage/owl-loader/description\n  Kernel module that helps to initialize certain Qualcomm\n  Atheros' PCI(e) Wifi chips, which have the init data\n  (which contains the PCI device ID for example) stored\n  together with the calibration data in the file system.\n\n  This is necessary for devices like the Cisco Meraki Z1.\nendef\n\ndefine KernelPackage/ar5523\n  $(call KernelPackage/mac80211/Default)\n  TITLE:=Driver for Atheros AR5523 USB sticks\n  DEPENDS:=@USB_SUPPORT +kmod-mac80211 +kmod-ath +kmod-usb-core +kmod-input-core \n  FILES:=$(PKG_BUILD_DIR)/drivers/net/wireless/ath/ar5523/ar5523.ko\n  AUTOLOAD:=$(call AutoProbe,ar5523)\nendef\n\ndefine KernelPackage/wil6210\n  $(call KernelPackage/mac80211/Default)\n  TITLE:=QCA/Wilocity 60g WiFi card wil6210 support\n  DEPENDS+= @PCI_SUPPORT +kmod-mac80211 +wil6210-firmware\n  FILES:=$(PKG_BUILD_DIR)/drivers/net/wireless/ath/wil6210/wil6210.ko\n  AUTOLOAD:=$(call AutoProbe,wil6210)\nendef\n"
  },
  {
    "path": "package/kernel/mac80211/broadcom.mk",
    "content": "PKG_DRIVERS += \\\n\tb43 b43legacy brcmsmac brcmfmac brcmutil\n\nPKG_CONFIG_DEPENDS += \\\n\tCONFIG_PACKAGE_B43_DEBUG \\\n\tCONFIG_PACKAGE_B43_PIO \\\n\tCONFIG_PACKAGE_B43_PHY_G \\\n\tCONFIG_PACKAGE_B43_PHY_N \\\n\tCONFIG_PACKAGE_B43_PHY_LP \\\n\tCONFIG_PACKAGE_B43_PHY_HT \\\n\tCONFIG_PACKAGE_B43_BUSES_BCMA_AND_SSB \\\n\tCONFIG_PACKAGE_B43_BUSES_BCMA \\\n\tCONFIG_PACKAGE_B43_BUSES_SSB \\\n\tCONFIG_PACKAGE_BRCM80211_DEBUG\n\nconfig-$(call config_package,b43) += B43\nconfig-$(CONFIG_PACKAGE_B43_BUSES_BCMA_AND_SSB) += B43_BUSES_BCMA_AND_SSB\nconfig-$(CONFIG_PACKAGE_B43_BUSES_BCMA) += B43_BUSES_BCMA\nconfig-$(CONFIG_PACKAGE_B43_BUSES_SSB) += B43_BUSES_SSB\nconfig-$(CONFIG_PACKAGE_B43_PHY_G) += B43_PHY_G\nconfig-$(CONFIG_PACKAGE_B43_PHY_N) += B43_PHY_N\nconfig-$(CONFIG_PACKAGE_B43_PHY_LP) += B43_PHY_LP\nconfig-$(CONFIG_PACKAGE_B43_PHY_HT) += B43_PHY_HT\nconfig-$(CONFIG_PACKAGE_B43_PIO) += B43_PIO\nconfig-$(CONFIG_PACKAGE_B43_DEBUG) += B43_DEBUG\n\nconfig-$(call config_package,b43legacy) += B43LEGACY\nconfig-y += B43LEGACY_DMA_MODE\n\nconfig-$(call config_package,brcmutil) += BRCMUTIL\nconfig-$(call config_package,brcmsmac) += BRCMSMAC\nconfig-$(call config_package,brcmfmac) += BRCMFMAC\nconfig-$(CONFIG_BRCMFMAC_SDIO) += BRCMFMAC_SDIO\nconfig-$(CONFIG_BRCMFMAC_USB) += BRCMFMAC_USB\nconfig-$(CONFIG_BRCMFMAC_PCIE) += BRCMFMAC_PCIE\nconfig-$(CONFIG_PACKAGE_BRCM80211_DEBUG) += BRCMDBG\n\nconfig-$(CONFIG_LEDS_TRIGGERS) += B43_LEDS B43LEGACY_LEDS\n\n#Broadcom firmware\nifneq ($(CONFIG_B43_FW_6_30),)\n  PKG_B43_FWV4_NAME:=broadcom-wl\n  PKG_B43_FWV4_VERSION:=6.30.163.46\n  PKG_B43_FWV4_OBJECT:=$(PKG_B43_FWV4_NAME)-$(PKG_B43_FWV4_VERSION).wl_apsta.o\n  PKG_B43_FWV4_SOURCE:=$(PKG_B43_FWV4_NAME)-$(PKG_B43_FWV4_VERSION).tar.bz2\n  PKG_B43_FWV4_SOURCE_URL:=http://www.lwfinger.com/b43-firmware/\n  PKG_B43_FWV4_HASH:=a07c3b6b277833c7dbe61daa511f908cd66c5e2763eb7a0859abc36cd9335c2d\nelse\nifneq ($(CONFIG_B43_FW_5_10),)\n  PKG_B43_FWV4_NAME:=broadcom-wl\n  PKG_B43_FWV4_VERSION:=5.10.56.27.3\n  PKG_B43_FWV4_OBJECT:=$(PKG_B43_FWV4_NAME)-$(PKG_B43_FWV4_VERSION)/driver/wl_apsta/wl_prebuilt.o\n  PKG_B43_FWV4_SOURCE:=$(PKG_B43_FWV4_NAME)-$(PKG_B43_FWV4_VERSION)_mipsel.tar.bz2\n  PKG_B43_FWV4_SOURCE_URL:=@OPENWRT\n  PKG_B43_FWV4_HASH:=26a8c370f48fc129d0731cfd751c36cae1419b0bc8ca35781126744e60eae009\nelse\nifneq ($(CONFIG_B43_FW_4_178),)\n  PKG_B43_FWV4_NAME:=broadcom-wl\n  PKG_B43_FWV4_VERSION:=4.178.10.4\n  PKG_B43_FWV4_OBJECT:=$(PKG_B43_FWV4_NAME)-$(PKG_B43_FWV4_VERSION)/linux/wl_apsta.o\n  PKG_B43_FWV4_SOURCE:=$(PKG_B43_FWV4_NAME)-$(PKG_B43_FWV4_VERSION).tar.bz2\n  PKG_B43_FWV4_SOURCE_URL:=@OPENWRT\n  PKG_B43_FWV4_HASH:=32f6ad98facbb9045646fdc8b54bb03086d204153253f9c65d0234a5d90ae53f\nelse\nifneq ($(CONFIG_B43_FW_5_100_138),)\n  PKG_B43_FWV4_NAME:=broadcom-wl\n  PKG_B43_FWV4_VERSION:=5.100.138\n  PKG_B43_FWV4_OBJECT:=$(PKG_B43_FWV4_NAME)-$(PKG_B43_FWV4_VERSION)/linux/wl_apsta.o\n  PKG_B43_FWV4_SOURCE:=$(PKG_B43_FWV4_NAME)-$(PKG_B43_FWV4_VERSION).tar.bz2\n  PKG_B43_FWV4_SOURCE_URL:=http://www.lwfinger.com/b43-firmware/\n  PKG_B43_FWV4_HASH:=f1e7067aac5b62b67b8b6e4c517990277804339ac16065eb13c731ff909ae46f\nelse\n  PKG_B43_FWV4_NAME:=broadcom-wl\n  PKG_B43_FWV4_VERSION:=4.150.10.5\n  PKG_B43_FWV4_OBJECT:=$(PKG_B43_FWV4_NAME)-$(PKG_B43_FWV4_VERSION)/driver/wl_apsta_mimo.o\n  PKG_B43_FWV4_SOURCE:=$(PKG_B43_FWV4_NAME)-$(PKG_B43_FWV4_VERSION).tar.bz2\n  PKG_B43_FWV4_SOURCE_URL:=@OPENWRT\n  PKG_B43_FWV4_HASH:=a9f4e276a4d8d3a1cd0f2eb87080ae89b77f0a7140f06d4e9e2135fc44fdd533\nendif\nendif\nendif\nendif\nifneq ($(CONFIG_B43_OPENFIRMWARE),)\n  PKG_B43_FWV4_NAME:=broadcom-wl\n  PKG_B43_FWV4_VERSION:=5.2\n  PKG_B43_FWV4_OBJECT:=openfwwf-$(PKG_B43_FWV4_VERSION)\n  PKG_B43_FWV4_SOURCE:=openfwwf-$(PKG_B43_FWV4_VERSION).tar.gz\n  PKG_B43_FWV4_SOURCE_URL:=http://netweb.ing.unibs.it/~openfwwf/firmware\n  PKG_B43_FWV4_HASH:=9de03320083201080b2e94b81637ac07a159cf4e6f3481383e1a217e627bc0dc\nendif\n\n\ndefine Download/b43\n  FILE:=$(PKG_B43_FWV4_SOURCE)\n  URL:=$(PKG_B43_FWV4_SOURCE_URL)\n  HASH:=$(PKG_B43_FWV4_HASH)\nendef\n$(eval $(call Download,b43))\n\ndefine KernelPackage/b43\n  $(call KernelPackage/mac80211/Default)\n  TITLE:=Broadcom 43xx wireless support\n  URL:=https://wireless.wiki.kernel.org/en/users/drivers/b43\n  KCONFIG:= \\\n  \tCONFIG_HW_RANDOM=y\n  # Depend on PCI_SUPPORT to make sure we can select kmod-bcma or kmod-ssb\n  DEPENDS += \\\n\t@PCI_SUPPORT +kmod-mac80211 +kmod-lib-cordic \\\n\t$(if $(CONFIG_PACKAGE_B43_USE_SSB),+kmod-ssb) \\\n\t$(if $(CONFIG_PACKAGE_B43_USE_BCMA),+kmod-bcma)\n  FILES:=$(PKG_BUILD_DIR)/drivers/net/wireless/broadcom/b43/b43.ko\n  AUTOLOAD:=$(call AutoProbe,b43)\n  MENU:=1\nendef\n\ndefine KernelPackage/b43/config\n\nconfig PACKAGE_B43_USE_SSB\n\tselect PACKAGE_kmod-ssb\n\ttristate\n\tdepends on !TARGET_bcm47xx && !TARGET_bcm63xx\n\tdefault PACKAGE_kmod-b43 if PACKAGE_B43_BUSES_BCMA_AND_SSB\n\tdefault PACKAGE_kmod-b43 if PACKAGE_B43_BUSES_SSB\n\nconfig PACKAGE_B43_USE_BCMA\n\tselect PACKAGE_kmod-bcma\n\ttristate\n\tdepends on !TARGET_bcm47xx && !TARGET_bcm53xx\n\tdefault PACKAGE_kmod-b43 if PACKAGE_B43_BUSES_BCMA_AND_SSB\n\tdefault PACKAGE_kmod-b43 if PACKAGE_B43_BUSES_BCMA\n\n  if PACKAGE_kmod-b43\n\n\tchoice\n\t\tprompt \"b43 firmware version\"\n\t\tdefault B43_FW_5_100_138\n\t\thelp\n\t\t  This option allows you to select the version of the b43 firmware.\n\n\tconfig B43_FW_4_150\n\t\tbool \"Firmware 410.2160 from driver 4.150.10.5 (old stable)\"\n\t\thelp\n\t\t  Old stable firmware for BCM43xx devices.\n\n\t\t  If unsure, select this.\n\n\tconfig B43_FW_4_178\n\t\tbool \"Firmware 478.104 from driver 4.178.10.4\"\n\t\thelp\n\t\t  Older firmware for BCM43xx devices.\n\n\t\t  If unsure, select the \"stable\" firmware.\n\n\tconfig B43_FW_5_10\n\t\tbool \"Firmware 508.1084 from driver 5.10.56.27\"\n\t\thelp\n\t\t  Older firmware for BCM43xx devices.\n\n\t\t  If unsure, select the \"stable\" firmware.\n\n\tconfig B43_FW_5_100_138\n\t\tbool \"Firmware 666.2 from driver 5.100.138 (stable)\"\n\t\thelp\n\t\t  The currently default firmware for BCM43xx devices.\n\n\t\t  This firmware currently gets most of the testing and is needed for some N-PHY devices.\n\n\t\t  If unsure, select the this firmware.\n\n\tconfig B43_FW_6_30\n\t\tbool \"Firmware 784.2 from driver 6.30.163.46 (experimental)\"\n\t\thelp\n\t\t  Newer experimental firmware for BCM43xx devices.\n\n\t\t  This firmware is mostly untested.\n\n\t\t  If unsure, select the \"stable\" firmware.\n\n\tconfig B43_OPENFIRMWARE\n\t\tbool \"Open FirmWare for WiFi networks\"\n\t\thelp\n\t\t  Opensource firmware for BCM43xx devices.\n\n\t\t  Do _not_ select this, unless you know what you are doing.\n\t\t  The Opensource firmware is not suitable for embedded devices, yet.\n\t\t  It does not support QoS, which is bad for AccessPoints.\n\t\t  It does not support hardware crypto acceleration, which is a showstopper\n\t\t  for embedded devices with low CPU resources.\n\n\t\t  If unsure, select the \"stable\" firmware.\n\n\tendchoice\n\n\tconfig B43_FW_SQUASH\n\t\tbool \"Remove unnecessary firmware files\"\n\t\tdepends on !B43_OPENFIRMWARE\n\t\tdefault y\n\t\thelp\n\t\t  This options allows you to remove unnecessary b43 firmware files\n\t\t  from the final rootfs image. This can reduce the rootfs size by\n\t\t  up to 200k.\n\n\t\t  If unsure, say Y.\n\n\tconfig B43_FW_SQUASH_COREREVS\n\t\tstring \"Core revisions to include\"\n\t\tdepends on B43_FW_SQUASH\n\t\tdefault \"5,6,7,8,9,10,11,13,15\" if TARGET_bcm47xx_legacy\n\t\tdefault \"16,28,29,30\" if TARGET_bcm47xx_mips74k\n\t\tdefault \"5,6,7,8,9,10,11,13,15,16,28,29,30\"\n\t\thelp\n\t\t  This is a comma separated list of core revision numbers.\n\n\t\t  Example (keep files for rev5 only):\n\t\t    5\n\n\t\t  Example (keep files for rev5 and rev11):\n\t\t    5,11\n\n\tconfig B43_FW_SQUASH_PHYTYPES\n\t\tstring \"PHY types to include\"\n\t\tdepends on B43_FW_SQUASH\n\t\tdefault \"G,N,LP\" if TARGET_bcm47xx_legacy\n\t\tdefault \"N,HT\" if TARGET_bcm47xx_mips74k\n\t\tdefault \"G,N,LP,HT\"\n\t\thelp\n\t\t  This is a comma separated list of PHY types:\n\t\t    A  => A-PHY\n\t\t    AG => Dual A-PHY G-PHY\n\t\t    G  => G-PHY\n\t\t    LP => LP-PHY\n\t\t    N  => N-PHY\n\t\t    HT  => HT-PHY\n\t\t    LCN  => LCN-PHY\n\t\t    LCN40  => LCN40-PHY\n\t\t    AC  => AC-PHY\n\n\t\t  Example (keep files for G-PHY only):\n\t\t    G\n\n\t\t  Example (keep files for G-PHY and N-PHY):\n\t\t    G,N\n\n\tchoice\n\t\tprompt \"Supported buses\"\n\t\tdefault PACKAGE_B43_BUSES_BCMA_AND_SSB\n\t\thelp\n\t\t  This allows choosing buses that b43 should support.\n\n\tconfig PACKAGE_B43_BUSES_BCMA_AND_SSB\n\t\tdepends on !TARGET_bcm47xx_legacy && !TARGET_bcm47xx_mips74k && !TARGET_bcm53xx\n\t\tbool \"BCMA and SSB\"\n\n\tconfig PACKAGE_B43_BUSES_BCMA\n\t\tdepends on !TARGET_bcm47xx_legacy\n\t\tbool \"BCMA only\"\n\n\tconfig PACKAGE_B43_BUSES_SSB\n\t\tdepends on !TARGET_bcm47xx_mips74k && !TARGET_bcm53xx\n\t\tbool \"SSB only\"\n\n\tendchoice\n\n\tconfig PACKAGE_B43_DEBUG\n\t\tbool \"Enable debug output and debugfs for b43\"\n\t\tdefault n\n\t\thelp\n\t\t  Enable additional debug output and runtime sanity checks for b43\n\t\t  and enables the debugfs interface.\n\n\t\t  If unsure, say N.\n\n\tconfig PACKAGE_B43_PIO\n\t\tbool \"Enable support for PIO transfer mode\"\n\t\tdefault n\n\t\thelp\n\t\t  Enable support for using PIO instead of DMA. Unless you have DMA\n\t\t  transfer problems you don't need this.\n\n\t\t  If unsure, say N.\n\n\tconfig PACKAGE_B43_PHY_G\n\t\tbool \"Enable support for G-PHYs\"\n\t\tdefault n if TARGET_bcm47xx_mips74k\n\t\tdefault y\n\t\thelp\n\t\t  Enable support for G-PHY. This includes support for the following devices:\n\t\t  PCI: BCM4306, BCM4311, BCM4318\n\t\t  SoC: BCM5352E, BCM4712\n\n\t\t  If unsure, say Y.\n\n\tconfig PACKAGE_B43_PHY_N\n\t\tbool \"Enable support for N-PHYs\"\n\t\tdefault y\n\t\thelp\n\t\t  Enable support for N-PHY. This includes support for the following devices:\n\t\t  PCI: BCM4321, BCM4322, BCM43222, BCM43224, BCM43225\n\t\t  SoC: BCM4716, BCM4717, BCM4718\n\n\t\t  Currently only 11g speed is available.\n\n\t\t  If unsure, say Y.\n\n\tconfig PACKAGE_B43_PHY_LP\n\t\tbool \"Enable support for LP-PHYs\"\n\t\tdefault n if TARGET_bcm47xx_mips74k\n\t\tdefault y\n\t\thelp\n\t\t  Enable support for LP-PHY. This includes support for the following devices:\n\t\t  PCI: BCM4312\n\t\t  SoC: BCM5354\n\n\t\t  If unsure, say Y.\n\n\tconfig PACKAGE_B43_PHY_HT\n\t\tbool \"Enable support for HT-PHYs\"\n\t\tdefault n if TARGET_bcm47xx_legacy\n\t\tdefault y\n\t\thelp\n\t\t  Enable support for HT-PHY. This includes support for the following devices:\n\t\t  PCI: BCM4331\n\n\t\t  Currently only 11g speed is available.\n\n\t\t  If unsure, say Y.\n\n\tconfig PACKAGE_B43_PHY_LCN\n\t\tbool \"Enable support for LCN-PHYs\"\n\t\tdepends on BROKEN\n\t\tdefault n\n\t\thelp\n\t\t  Currently broken.\n\n\t\t  If unsure, say N.\n\n  endif\nendef\n\ndefine KernelPackage/b43/description\nKernel module for Broadcom 43xx wireless support (mac80211 stack) new\nendef\n\ndefine KernelPackage/b43legacy\n  $(call KernelPackage/mac80211/Default)\n  TITLE:=Broadcom 43xx-legacy wireless support\n  URL:=https://wireless.wiki.kernel.org/en/users/drivers/b43\n  KCONFIG:= \\\n  \tCONFIG_HW_RANDOM=y\n  DEPENDS+= +kmod-mac80211 +!(TARGET_bcm47xx||TARGET_bcm63xx):kmod-ssb @!TARGET_bcm47xx_mips74k +b43legacy-firmware\n  FILES:=$(PKG_BUILD_DIR)/drivers/net/wireless/broadcom/b43legacy/b43legacy.ko\n  AUTOLOAD:=$(call AutoProbe,b43legacy)\n  MENU:=1\nendef\n\ndefine KernelPackage/b43legacy/description\nKernel module for Broadcom 43xx-legacy wireless support (mac80211 stack) new\nendef\n\n\ndefine KernelPackage/brcmutil\n  $(call KernelPackage/mac80211/Default)\n  TITLE:=Broadcom IEEE802.11n common driver parts\n  URL:=https://wireless.wiki.kernel.org/en/users/drivers/brcm80211\n  DEPENDS+=@PCI_SUPPORT||USB_SUPPORT\n  FILES:=$(PKG_BUILD_DIR)/drivers/net/wireless/broadcom/brcm80211/brcmutil/brcmutil.ko\n  AUTOLOAD:=$(call AutoProbe,brcmutil)\n  MENU:=1\nendef\n\ndefine KernelPackage/brcmutil/description\n This module contains some common parts needed by Broadcom Wireless drivers brcmsmac and brcmfmac.\nendef\n\ndefine KernelPackage/brcmutil/config\n  if PACKAGE_kmod-brcmutil\n\n\tconfig PACKAGE_BRCM80211_DEBUG\n\t\tbool \"Broadcom wireless driver debugging\"\n\t\thelp\n\t\t  Say Y, if you want to debug brcmsmac and brcmfmac wireless driver.\n\n  endif\nendef\n\nPKG_BRCMSMAC_FW_NAME:=broadcom-wl\nPKG_BRCMSMAC_FW_VERSION:=5.100.138\nPKG_BRCMSMAC_FW_OBJECT:=$(PKG_BRCMSMAC_FW_NAME)-$(PKG_BRCMSMAC_FW_VERSION)/linux/wl_apsta.o\nPKG_BRCMSMAC_FW_SOURCE:=$(PKG_BRCMSMAC_FW_NAME)-$(PKG_BRCMSMAC_FW_VERSION).tar.bz2\nPKG_BRCMSMAC_FW_SOURCE_URL:=http://www.lwfinger.com/b43-firmware/\nPKG_BRCMSMAC_FW_HASH:=f1e7067aac5b62b67b8b6e4c517990277804339ac16065eb13c731ff909ae46f\n\ndefine Download/brcmsmac\n  FILE:=$(PKG_BRCMSMAC_FW_SOURCE)\n  URL:=$(PKG_BRCMSMAC_FW_SOURCE_URL)\n  HASH:=$(PKG_BRCMSMAC_FW_HASH)\nendef\n$(eval $(call Download,brcmsmac))\n\ndefine KernelPackage/brcmsmac\n  $(call KernelPackage/mac80211/Default)\n  TITLE:=Broadcom IEEE802.11n PCIe SoftMAC WLAN driver\n  URL:=https://wireless.wiki.kernel.org/en/users/drivers/brcm80211\n  DEPENDS+= +kmod-mac80211 +@DRIVER_11N_SUPPORT +!TARGET_bcm47xx:kmod-bcma +kmod-lib-cordic +kmod-lib-crc8 +kmod-brcmutil +!BRCMSMAC_USE_FW_FROM_WL:brcmsmac-firmware\n  FILES:=$(PKG_BUILD_DIR)/drivers/net/wireless/broadcom/brcm80211/brcmsmac/brcmsmac.ko\n  AUTOLOAD:=$(call AutoProbe,brcmsmac)\n  MENU:=1\nendef\n\ndefine KernelPackage/brcmsmac/description\n Kernel module for Broadcom IEEE802.11n PCIe Wireless cards\nendef\n\ndefine KernelPackage/brcmsmac/config\n  if PACKAGE_kmod-brcmsmac\n\n\tconfig BRCMSMAC_USE_FW_FROM_WL\n\t\tbool \"Use firmware extracted from broadcom proprietary driver\"\n\t\tdefault y\n\t\thelp\n\t\t  Instead of using the official brcmsmac firmware a firmware\n\t\t  version 666.2 extracted from the proprietary Broadcom driver\n\t\t  is used. This is needed to get core rev 17 used in bcm4716\n\t\t  to work.\n\n\t\t  If unsure, say Y.\n\n  endif\nendef\n\n\ndefine KernelPackage/brcmfmac\n  $(call KernelPackage/mac80211/Default)\n  TITLE:=Broadcom IEEE802.11n USB FullMAC WLAN driver\n  URL:=https://wireless.wiki.kernel.org/en/users/drivers/brcm80211\n  DEPENDS+= @USB_SUPPORT +kmod-cfg80211 +@DRIVER_11N_SUPPORT +@DRIVER_11AC_SUPPORT \\\n  \t+kmod-brcmutil +BRCMFMAC_SDIO:kmod-mmc @!TARGET_uml \\\n\t+BRCMFMAC_USB:kmod-usb-core +BRCMFMAC_USB:brcmfmac-firmware-usb\n  FILES:=$(PKG_BUILD_DIR)/drivers/net/wireless/broadcom/brcm80211/brcmfmac/brcmfmac.ko\n  AUTOLOAD:=$(call AutoProbe,brcmfmac)\nendef\n\ndefine KernelPackage/brcmfmac/description\n Kernel module for Broadcom IEEE802.11n USB Wireless cards\nendef\n\ndefine KernelPackage/brcmfmac/config\n  if PACKAGE_kmod-brcmfmac\n\n\tconfig BRCMFMAC_SDIO\n\t\tbool \"Enable SDIO bus interface support\"\n\t\tdefault y if TARGET_bcm27xx\n\t\tdefault y if TARGET_sunxi\n\t\tdefault n\n\t\thelp\n\t\t  Enable support for cards attached to an SDIO bus.\n\t\t  Select this option only if you are sure that your\n\t\t  board has a Broadcom wireless chip atacched to\n\t\t  that bus.\n\n\tconfig BRCMFMAC_USB\n\t\tbool \"Enable USB bus interface support\"\n\t\tdepends on USB_SUPPORT\n\t\tdefault y\n\t\thelp\n\t\t  Supported USB connected chipsets:\n\t\t  BCM43235, BCM43236, BCM43238 (all in revision 3 only)\n\t\t  BCM43143, BCM43242, BCM43566, BCM43569\n\n\tconfig BRCMFMAC_PCIE\n\t\tbool \"Enable PCIE bus interface support\"\n\t\tdepends on PCI_SUPPORT\n\t\tdefault y\n\t\thelp\n\t\t  Supported PCIe connected chipsets:\n\t\t  BCM4354, BCM4356, BCM43567, BCM43570, BCM43602\n\n  endif\nendef\n\n\ndefine KernelPackage/b43/install\n\trm -rf $(1)/lib/firmware/\nifeq ($(CONFIG_B43_OPENFIRMWARE),y)\n\ttar xzf \"$(DL_DIR)/$(PKG_B43_FWV4_SOURCE)\" -C \"$(PKG_BUILD_DIR)\"\nelse\n\ttar xjf \"$(DL_DIR)/$(PKG_B43_FWV4_SOURCE)\" -C \"$(PKG_BUILD_DIR)\"\nendif\n\t$(INSTALL_DIR) $(1)/lib/firmware/\nifeq ($(CONFIG_B43_OPENFIRMWARE),y)\n\t$(MAKE) -C \"$(PKG_BUILD_DIR)/$(PKG_B43_FWV4_OBJECT)/\"\n\t$(INSTALL_DIR) $(1)/lib/firmware/b43-open/\n\t$(INSTALL_DATA) $(PKG_BUILD_DIR)/$(PKG_B43_FWV4_OBJECT)/ucode5.fw $(1)/lib/firmware/b43-open/ucode5.fw\n\t$(INSTALL_DATA) $(PKG_BUILD_DIR)/$(PKG_B43_FWV4_OBJECT)/b0g0bsinitvals5.fw $(1)/lib/firmware/b43-open/b0g0bsinitvals5.fw\n\t$(INSTALL_DATA) $(PKG_BUILD_DIR)/$(PKG_B43_FWV4_OBJECT)/b0g0initvals5.fw $(1)/lib/firmware/b43-open/b0g0initvals5.fw\nelse\n\tb43-fwcutter -w $(1)/lib/firmware/ $(PKG_BUILD_DIR)/$(PKG_B43_FWV4_OBJECT)\nendif\nifneq ($(CONFIG_B43_FW_SQUASH),)\n\tb43-fwsquash.py \"$(CONFIG_B43_FW_SQUASH_PHYTYPES)\" \"$(CONFIG_B43_FW_SQUASH_COREREVS)\" \"$(1)/lib/firmware/b43\"\nendif\nendef\n\ndefine KernelPackage/brcmsmac/install\n\t$(INSTALL_DIR) $(1)/lib/firmware/brcm\nifeq ($(CONFIG_BRCMSMAC_USE_FW_FROM_WL),y)\n\ttar xjf \"$(DL_DIR)/$(PKG_BRCMSMAC_FW_SOURCE)\" -C \"$(PKG_BUILD_DIR)\"\n\tb43-fwcutter --brcmsmac -w $(1)/lib/firmware/ $(PKG_BUILD_DIR)/$(PKG_BRCMSMAC_FW_OBJECT)\nendif\nendef\n"
  },
  {
    "path": "package/kernel/mac80211/files/lib/netifd/wireless/mac80211.sh",
    "content": "#!/bin/sh\n. /lib/netifd/netifd-wireless.sh\n. /lib/netifd/hostapd.sh\n\ninit_wireless_driver \"$@\"\n\nMP_CONFIG_INT=\"mesh_retry_timeout mesh_confirm_timeout mesh_holding_timeout mesh_max_peer_links\n\t       mesh_max_retries mesh_ttl mesh_element_ttl mesh_hwmp_max_preq_retries\n\t       mesh_path_refresh_time mesh_min_discovery_timeout mesh_hwmp_active_path_timeout\n\t       mesh_hwmp_preq_min_interval mesh_hwmp_net_diameter_traversal_time mesh_hwmp_rootmode\n\t       mesh_hwmp_rann_interval mesh_gate_announcements mesh_sync_offset_max_neighor\n\t       mesh_rssi_threshold mesh_hwmp_active_path_to_root_timeout mesh_hwmp_root_interval\n\t       mesh_hwmp_confirmation_interval mesh_awake_window mesh_plink_timeout\"\nMP_CONFIG_BOOL=\"mesh_auto_open_plinks mesh_fwding\"\nMP_CONFIG_STRING=\"mesh_power_mode\"\n\nNEWAPLIST=\nOLDAPLIST=\nNEWSPLIST=\nOLDSPLIST=\nNEWUMLIST=\nOLDUMLIST=\n\ndrv_mac80211_init_device_config() {\n\thostapd_common_add_device_config\n\n\tconfig_add_string path phy 'macaddr:macaddr'\n\tconfig_add_string tx_burst\n\tconfig_add_string distance\n\tconfig_add_int beacon_int chanbw frag rts\n\tconfig_add_int rxantenna txantenna antenna_gain txpower\n\tconfig_add_boolean noscan ht_coex acs_exclude_dfs\n\tconfig_add_array ht_capab\n\tconfig_add_array channels\n\tconfig_add_array scan_list\n\tconfig_add_boolean \\\n\t\trxldpc \\\n\t\tshort_gi_80 \\\n\t\tshort_gi_160 \\\n\t\ttx_stbc_2by1 \\\n\t\tsu_beamformer \\\n\t\tsu_beamformee \\\n\t\tmu_beamformer \\\n\t\tmu_beamformee \\\n\t\the_su_beamformer \\\n\t\the_su_beamformee \\\n\t\the_mu_beamformer \\\n\t\tvht_txop_ps \\\n\t\thtc_vht \\\n\t\trx_antenna_pattern \\\n\t\ttx_antenna_pattern \\\n\t\the_spr_sr_control \\\n\t\the_twt_required\n\tconfig_add_int \\\n\t\tbeamformer_antennas \\\n\t\tbeamformee_antennas \\\n\t\tvht_max_a_mpdu_len_exp \\\n\t\tvht_max_mpdu \\\n\t\tvht_link_adapt \\\n\t\tvht160 \\\n\t\trx_stbc \\\n\t\ttx_stbc \\\n\t\the_bss_color \\\n\t\the_spr_non_srg_obss_pd_max_offset\n\tconfig_add_boolean \\\n\t\tldpc \\\n\t\tgreenfield \\\n\t\tshort_gi_20 \\\n\t\tshort_gi_40 \\\n\t\tmax_amsdu \\\n\t\tdsss_cck_40\n}\n\ndrv_mac80211_init_iface_config() {\n\thostapd_common_add_bss_config\n\n\tconfig_add_string 'macaddr:macaddr' ifname\n\n\tconfig_add_boolean wds powersave enable\n\tconfig_add_string wds_bridge\n\tconfig_add_int maxassoc\n\tconfig_add_int max_listen_int\n\tconfig_add_int dtim_period\n\tconfig_add_int start_disabled\n\n\t# mesh\n\tconfig_add_string mesh_id\n\tconfig_add_int $MP_CONFIG_INT\n\tconfig_add_boolean $MP_CONFIG_BOOL\n\tconfig_add_string $MP_CONFIG_STRING\n}\n\nmac80211_add_capabilities() {\n\tlocal __var=\"$1\"; shift\n\tlocal __mask=\"$1\"; shift\n\tlocal __out= oifs\n\n\toifs=\"$IFS\"\n\tIFS=:\n\tfor capab in \"$@\"; do\n\t\tset -- $capab\n\n\t\t[ \"$(($4))\" -gt 0 ] || continue\n\t\t[ \"$(($__mask & $2))\" -eq \"$((${3:-$2}))\" ] || continue\n\t\t__out=\"$__out[$1]\"\n\tdone\n\tIFS=\"$oifs\"\n\n\texport -n -- \"$__var=$__out\"\n}\n\nmac80211_add_he_capabilities() {\n\tlocal __out= oifs\n\n\toifs=\"$IFS\"\n\tIFS=:\n\tfor capab in \"$@\"; do\n\t\tset -- $capab\n\t\t[ \"$(($4))\" -gt 0 ] || continue\n\t\t[ \"$(((0x$2) & $3))\" -gt 0 ] || {\n\t\t\teval \"$1=0\"\n\t\t\tcontinue\n\t\t}\n\t\tappend base_cfg \"$1=1\" \"$N\"\n\tdone\n\tIFS=\"$oifs\"\n}\n\nmac80211_hostapd_setup_base() {\n\tlocal phy=\"$1\"\n\n\tjson_select config\n\n\t[ \"$auto_channel\" -gt 0 ] && channel=acs_survey\n\n\t[ \"$auto_channel\" -gt 0 ] && json_get_vars acs_exclude_dfs\n\t[ -n \"$acs_exclude_dfs\" ] && [ \"$acs_exclude_dfs\" -gt 0 ] &&\n\t\tappend base_cfg \"acs_exclude_dfs=1\" \"$N\"\n\n\tjson_get_vars noscan ht_coex\n\tjson_get_values ht_capab_list ht_capab tx_burst\n\tjson_get_values channel_list channels\n\n\t[ \"$auto_channel\" = 0 ] && [ -z \"$channel_list\" ] && \\\n\t\tchannel_list=\"$channel\"\n\n\tset_default noscan 0\n\n\t[ \"$noscan\" -gt 0 ] && hostapd_noscan=1\n\t[ \"$tx_burst\" = 0 ] && tx_burst=\n\n\tchan_ofs=0\n\t[ \"$band\" = \"6g\" ] && chan_ofs=1\n\n\tieee80211n=1\n\tht_capab=\n\tcase \"$htmode\" in\n\t\tVHT20|HT20|HE20) ;;\n\t\tHT40*|VHT40|VHT80|VHT160|HE40|HE80|HE160)\n\t\t\tcase \"$hwmode\" in\n\t\t\t\ta)\n\t\t\t\t\tcase \"$(( (($channel / 4) + $chan_ofs) % 2 ))\" in\n\t\t\t\t\t\t1) ht_capab=\"[HT40+]\";;\n\t\t\t\t\t\t0) ht_capab=\"[HT40-]\";;\n\t\t\t\t\tesac\n\t\t\t\t;;\n\t\t\t\t*)\n\t\t\t\t\tcase \"$htmode\" in\n\t\t\t\t\t\tHT40+) ht_capab=\"[HT40+]\";;\n\t\t\t\t\t\tHT40-) ht_capab=\"[HT40-]\";;\n\t\t\t\t\t\t*)\n\t\t\t\t\t\t\tif [ \"$channel\" -lt 7 ]; then\n\t\t\t\t\t\t\t\tht_capab=\"[HT40+]\"\n\t\t\t\t\t\t\telse\n\t\t\t\t\t\t\t\tht_capab=\"[HT40-]\"\n\t\t\t\t\t\t\tfi\n\t\t\t\t\t\t;;\n\t\t\t\t\tesac\n\t\t\t\t;;\n\t\t\tesac\n\t\t\t[ \"$auto_channel\" -gt 0 ] && ht_capab=\"[HT40+]\"\n\t\t;;\n\t\t*) ieee80211n= ;;\n\tesac\n\n\t[ -n \"$ieee80211n\" ] && {\n\t\tappend base_cfg \"ieee80211n=1\" \"$N\"\n\n\t\tset_default ht_coex 0\n\t\tappend base_cfg \"ht_coex=$ht_coex\" \"$N\"\n\n\t\tjson_get_vars \\\n\t\t\tldpc:1 \\\n\t\t\tgreenfield:0 \\\n\t\t\tshort_gi_20:1 \\\n\t\t\tshort_gi_40:1 \\\n\t\t\ttx_stbc:1 \\\n\t\t\trx_stbc:3 \\\n\t\t\tmax_amsdu:1 \\\n\t\t\tdsss_cck_40:1\n\n\t\tht_cap_mask=0\n\t\tfor cap in $(iw phy \"$phy\" info | grep 'Capabilities:' | cut -d: -f2); do\n\t\t\tht_cap_mask=\"$(($ht_cap_mask | $cap))\"\n\t\tdone\n\n\t\tcap_rx_stbc=$((($ht_cap_mask >> 8) & 3))\n\t\t[ \"$rx_stbc\" -lt \"$cap_rx_stbc\" ] && cap_rx_stbc=\"$rx_stbc\"\n\t\tht_cap_mask=\"$(( ($ht_cap_mask & ~(0x300)) | ($cap_rx_stbc << 8) ))\"\n\n\t\tmac80211_add_capabilities ht_capab_flags $ht_cap_mask \\\n\t\t\tLDPC:0x1::$ldpc \\\n\t\t\tGF:0x10::$greenfield \\\n\t\t\tSHORT-GI-20:0x20::$short_gi_20 \\\n\t\t\tSHORT-GI-40:0x40::$short_gi_40 \\\n\t\t\tTX-STBC:0x80::$tx_stbc \\\n\t\t\tRX-STBC1:0x300:0x100:1 \\\n\t\t\tRX-STBC12:0x300:0x200:1 \\\n\t\t\tRX-STBC123:0x300:0x300:1 \\\n\t\t\tMAX-AMSDU-7935:0x800::$max_amsdu \\\n\t\t\tDSSS_CCK-40:0x1000::$dsss_cck_40\n\n\t\tht_capab=\"$ht_capab$ht_capab_flags\"\n\t\t[ -n \"$ht_capab\" ] && append base_cfg \"ht_capab=$ht_capab\" \"$N\"\n\t}\n\n\t# 802.11ac\n\tenable_ac=0\n\tvht_oper_chwidth=0\n\tvht_center_seg0=\n\n\tidx=\"$channel\"\n\tcase \"$htmode\" in\n\t\tVHT20|HE20) enable_ac=1;;\n\t\tVHT40|HE40)\n\t\t\tcase \"$(( (($channel / 4) + $chan_ofs) % 2 ))\" in\n\t\t\t\t1) idx=$(($channel + 2));;\n\t\t\t\t0) idx=$(($channel - 2));;\n\t\t\tesac\n\t\t\tenable_ac=1\n\t\t\tvht_center_seg0=$idx\n\t\t;;\n\t\tVHT80|HE80)\n\t\t\tcase \"$(( (($channel / 4) + $chan_ofs) % 4 ))\" in\n\t\t\t\t1) idx=$(($channel + 6));;\n\t\t\t\t2) idx=$(($channel + 2));;\n\t\t\t\t3) idx=$(($channel - 2));;\n\t\t\t\t0) idx=$(($channel - 6));;\n\t\t\tesac\n\t\t\tenable_ac=1\n\t\t\tvht_oper_chwidth=1\n\t\t\tvht_center_seg0=$idx\n\t\t;;\n\t\tVHT160|HE160)\n\t\t\tif [ \"$band\" = \"6g\" ]; then\n\t\t\t\tcase \"$channel\" in\n\t\t\t\t\t1|5|9|13|17|21|25|29) idx=15;;\n\t\t\t\t\t33|37|41|45|49|53|57|61) idx=47;;\n\t\t\t\t\t65|69|73|77|81|85|89|93) idx=79;;\n\t\t\t\t\t97|101|105|109|113|117|121|125) idx=111;;\n\t\t\t\t\t129|133|137|141|145|149|153|157) idx=143;;\n\t\t\t\t\t161|165|169|173|177|181|185|189) idx=175;;\n\t\t\t\t\t193|197|201|205|209|213|217|221) idx=207;;\n\t\t\t\tesac\n\t\t\telse\n\t\t\t\tcase \"$channel\" in\n\t\t\t\t\t36|40|44|48|52|56|60|64) idx=50;;\n\t\t\t\t\t100|104|108|112|116|120|124|128) idx=114;;\n\t\t\t\tesac\n\t\t\tfi\n\t\t\tenable_ac=1\n\t\t\tvht_oper_chwidth=2\n\t\t\tvht_center_seg0=$idx\n\t\t;;\n\tesac\n\t[ \"$band\" = \"6g\" ] && {\n\t\top_class=\n\t\tcase \"$htmode\" in\n\t\t\tHE20) op_class=131;;\n\t\t\tHE*) op_class=$((132 + $vht_oper_chwidth))\n\t\tesac\n\t\t[ -n \"$op_class\" ] && append base_cfg \"op_class=$op_class\" \"$N\"\n\t}\n\t[ \"$hwmode\" = \"a\" ] || enable_ac=0\n\n\tif [ \"$enable_ac\" != \"0\" ]; then\n\t\tjson_get_vars \\\n\t\t\trxldpc:1 \\\n\t\t\tshort_gi_80:1 \\\n\t\t\tshort_gi_160:1 \\\n\t\t\ttx_stbc_2by1:1 \\\n\t\t\tsu_beamformer:1 \\\n\t\t\tsu_beamformee:1 \\\n\t\t\tmu_beamformer:1 \\\n\t\t\tmu_beamformee:1 \\\n\t\t\tvht_txop_ps:1 \\\n\t\t\thtc_vht:1 \\\n\t\t\tbeamformee_antennas:4 \\\n\t\t\tbeamformer_antennas:4 \\\n\t\t\trx_antenna_pattern:1 \\\n\t\t\ttx_antenna_pattern:1 \\\n\t\t\tvht_max_a_mpdu_len_exp:7 \\\n\t\t\tvht_max_mpdu:11454 \\\n\t\t\trx_stbc:4 \\\n\t\t\tvht_link_adapt:3 \\\n\t\t\tvht160:2\n\n\t\tset_default tx_burst 2.0\n\t\tappend base_cfg \"ieee80211ac=1\" \"$N\"\n\t\tvht_cap=0\n\t\tfor cap in $(iw phy \"$phy\" info | awk -F \"[()]\" '/VHT Capabilities/ { print $2 }'); do\n\t\t\tvht_cap=\"$(($vht_cap | $cap))\"\n\t\tdone\n\n\t\tappend base_cfg \"vht_oper_chwidth=$vht_oper_chwidth\" \"$N\"\n\t\tappend base_cfg \"vht_oper_centr_freq_seg0_idx=$vht_center_seg0\" \"$N\"\n\n\t\tcap_rx_stbc=$((($vht_cap >> 8) & 7))\n\t\t[ \"$rx_stbc\" -lt \"$cap_rx_stbc\" ] && cap_rx_stbc=\"$rx_stbc\"\n\t\tvht_cap=\"$(( ($vht_cap & ~(0x700)) | ($cap_rx_stbc << 8) ))\"\n\n\t\tmac80211_add_capabilities vht_capab $vht_cap \\\n\t\t\tRXLDPC:0x10::$rxldpc \\\n\t\t\tSHORT-GI-80:0x20::$short_gi_80 \\\n\t\t\tSHORT-GI-160:0x40::$short_gi_160 \\\n\t\t\tTX-STBC-2BY1:0x80::$tx_stbc_2by1 \\\n\t\t\tSU-BEAMFORMER:0x800::$su_beamformer \\\n\t\t\tSU-BEAMFORMEE:0x1000::$su_beamformee \\\n\t\t\tMU-BEAMFORMER:0x80000::$mu_beamformer \\\n\t\t\tMU-BEAMFORMEE:0x100000::$mu_beamformee \\\n\t\t\tVHT-TXOP-PS:0x200000::$vht_txop_ps \\\n\t\t\tHTC-VHT:0x400000::$htc_vht \\\n\t\t\tRX-ANTENNA-PATTERN:0x10000000::$rx_antenna_pattern \\\n\t\t\tTX-ANTENNA-PATTERN:0x20000000::$tx_antenna_pattern \\\n\t\t\tRX-STBC-1:0x700:0x100:1 \\\n\t\t\tRX-STBC-12:0x700:0x200:1 \\\n\t\t\tRX-STBC-123:0x700:0x300:1 \\\n\t\t\tRX-STBC-1234:0x700:0x400:1 \\\n\n\t\t[ \"$(($vht_cap & 0x800))\" -gt 0 -a \"$su_beamformer\" -gt 0 ] && {\n\t\t\tcap_ant=\"$(( ( ($vht_cap >> 16) & 3 ) + 1 ))\"\n\t\t\t[ \"$cap_ant\" -gt \"$beamformer_antennas\" ] && cap_ant=\"$beamformer_antennas\"\n\t\t\t[ \"$cap_ant\" -gt 1 ] && vht_capab=\"$vht_capab[SOUNDING-DIMENSION-$cap_ant]\"\n\t\t}\n\n\t\t[ \"$(($vht_cap & 0x1000))\" -gt 0 -a \"$su_beamformee\" -gt 0 ] && {\n\t\t\tcap_ant=\"$(( ( ($vht_cap >> 13) & 3 ) + 1 ))\"\n\t\t\t[ \"$cap_ant\" -gt \"$beamformee_antennas\" ] && cap_ant=\"$beamformee_antennas\"\n\t\t\t[ \"$cap_ant\" -gt 1 ] && vht_capab=\"$vht_capab[BF-ANTENNA-$cap_ant]\"\n\t\t}\n\n\t\t# supported Channel widths\n\t\tvht160_hw=0\n\t\t[ \"$(($vht_cap & 12))\" -eq 4 -a 1 -le \"$vht160\" ] && \\\n\t\t\tvht160_hw=1\n\t\t[ \"$(($vht_cap & 12))\" -eq 8 -a 2 -le \"$vht160\" ] && \\\n\t\t\tvht160_hw=2\n\t\t[ \"$vht160_hw\" = 1 ] && vht_capab=\"$vht_capab[VHT160]\"\n\t\t[ \"$vht160_hw\" = 2 ] && vht_capab=\"$vht_capab[VHT160-80PLUS80]\"\n\n\t\t# maximum MPDU length\n\t\tvht_max_mpdu_hw=3895\n\t\t[ \"$(($vht_cap & 3))\" -ge 1 -a 7991 -le \"$vht_max_mpdu\" ] && \\\n\t\t\tvht_max_mpdu_hw=7991\n\t\t[ \"$(($vht_cap & 3))\" -ge 2 -a 11454 -le \"$vht_max_mpdu\" ] && \\\n\t\t\tvht_max_mpdu_hw=11454\n\t\t[ \"$vht_max_mpdu_hw\" != 3895 ] && \\\n\t\t\tvht_capab=\"$vht_capab[MAX-MPDU-$vht_max_mpdu_hw]\"\n\n\t\t# maximum A-MPDU length exponent\n\t\tvht_max_a_mpdu_len_exp_hw=0\n\t\t[ \"$(($vht_cap & 58720256))\" -ge 8388608 -a 1 -le \"$vht_max_a_mpdu_len_exp\" ] && \\\n\t\t\tvht_max_a_mpdu_len_exp_hw=1\n\t\t[ \"$(($vht_cap & 58720256))\" -ge 16777216 -a 2 -le \"$vht_max_a_mpdu_len_exp\" ] && \\\n\t\t\tvht_max_a_mpdu_len_exp_hw=2\n\t\t[ \"$(($vht_cap & 58720256))\" -ge 25165824 -a 3 -le \"$vht_max_a_mpdu_len_exp\" ] && \\\n\t\t\tvht_max_a_mpdu_len_exp_hw=3\n\t\t[ \"$(($vht_cap & 58720256))\" -ge 33554432 -a 4 -le \"$vht_max_a_mpdu_len_exp\" ] && \\\n\t\t\tvht_max_a_mpdu_len_exp_hw=4\n\t\t[ \"$(($vht_cap & 58720256))\" -ge 41943040 -a 5 -le \"$vht_max_a_mpdu_len_exp\" ] && \\\n\t\t\tvht_max_a_mpdu_len_exp_hw=5\n\t\t[ \"$(($vht_cap & 58720256))\" -ge 50331648 -a 6 -le \"$vht_max_a_mpdu_len_exp\" ] && \\\n\t\t\tvht_max_a_mpdu_len_exp_hw=6\n\t\t[ \"$(($vht_cap & 58720256))\" -ge 58720256 -a 7 -le \"$vht_max_a_mpdu_len_exp\" ] && \\\n\t\t\tvht_max_a_mpdu_len_exp_hw=7\n\t\tvht_capab=\"$vht_capab[MAX-A-MPDU-LEN-EXP$vht_max_a_mpdu_len_exp_hw]\"\n\n\t\t# whether or not the STA supports link adaptation using VHT variant\n\t\tvht_link_adapt_hw=0\n\t\t[ \"$(($vht_cap & 201326592))\" -ge 134217728 -a 2 -le \"$vht_link_adapt\" ] && \\\n\t\t\tvht_link_adapt_hw=2\n\t\t[ \"$(($vht_cap & 201326592))\" -ge 201326592 -a 3 -le \"$vht_link_adapt\" ] && \\\n\t\t\tvht_link_adapt_hw=3\n\t\t[ \"$vht_link_adapt_hw\" != 0 ] && \\\n\t\t\tvht_capab=\"$vht_capab[VHT-LINK-ADAPT-$vht_link_adapt_hw]\"\n\n\t\t[ -n \"$vht_capab\" ] && append base_cfg \"vht_capab=$vht_capab\" \"$N\"\n\tfi\n\n\t# 802.11ax\n\tenable_ax=0\n\tcase \"$htmode\" in\n\t\tHE*) enable_ax=1 ;;\n\tesac\n\n\tif [ \"$enable_ax\" != \"0\" ]; then\n\t\tjson_get_vars \\\n\t\t\the_su_beamformer:1 \\\n\t\t\the_su_beamformee:0 \\\n\t\t\the_mu_beamformer:1 \\\n\t\t\the_twt_required:0 \\\n\t\t\the_spr_sr_control:0 \\\n\t\t\the_spr_non_srg_obss_pd_max_offset:1 \\\n\t\t\the_bss_color\n\n\t\the_phy_cap=$(iw phy \"$phy\" info | awk -F \"[()]\" '/HE PHY Capabilities/ { print $2 }' | head -1)\n\t\the_phy_cap=${he_phy_cap:2}\n\t\the_mac_cap=$(iw phy \"$phy\" info | awk -F \"[()]\" '/HE MAC Capabilities/ { print $2 }' | head -1)\n\t\the_mac_cap=${he_mac_cap:2}\n\n\t\tappend base_cfg \"ieee80211ax=1\" \"$N\"\n\t\t[ -n \"$he_bss_color\" ] && append base_cfg \"he_bss_color=$he_bss_color\" \"$N\"\n\t\t[ \"$hwmode\" = \"a\" ] && {\n\t\t\tappend base_cfg \"he_oper_chwidth=$vht_oper_chwidth\" \"$N\"\n\t\t\tappend base_cfg \"he_oper_centr_freq_seg0_idx=$vht_center_seg0\" \"$N\"\n\t\t}\n\n\t\tmac80211_add_he_capabilities \\\n\t\t\the_su_beamformer:${he_phy_cap:6:2}:0x80:$he_su_beamformer \\\n\t\t\the_su_beamformee:${he_phy_cap:8:2}:0x1:$he_su_beamformee \\\n\t\t\the_mu_beamformer:${he_phy_cap:8:2}:0x2:$he_mu_beamformer \\\n\t\t\the_spr_sr_control:${he_phy_cap:14:2}:0x1:$he_spr_sr_control \\\n\t\t\the_twt_required:${he_mac_cap:0:2}:0x6:$he_twt_required\n\n\t\t[ \"$he_spr_sr_control\" -gt 0 ] && append base_cfg \"he_spr_non_srg_obss_pd_max_offset=$he_spr_non_srg_obss_pd_max_offset\" \"$N\"\n\n\t\tappend base_cfg \"he_default_pe_duration=4\" \"$N\"\n\t\tappend base_cfg \"he_rts_threshold=1023\" \"$N\"\n\t\tappend base_cfg \"he_mu_edca_qos_info_param_count=0\" \"$N\"\n\t\tappend base_cfg \"he_mu_edca_qos_info_q_ack=0\" \"$N\"\n\t\tappend base_cfg \"he_mu_edca_qos_info_queue_request=0\" \"$N\"\n\t\tappend base_cfg \"he_mu_edca_qos_info_txop_request=0\" \"$N\"\n\t\tappend base_cfg \"he_mu_edca_ac_be_aifsn=8\" \"$N\"\n\t\tappend base_cfg \"he_mu_edca_ac_be_aci=0\" \"$N\"\n\t\tappend base_cfg \"he_mu_edca_ac_be_ecwmin=9\" \"$N\"\n\t\tappend base_cfg \"he_mu_edca_ac_be_ecwmax=10\" \"$N\"\n\t\tappend base_cfg \"he_mu_edca_ac_be_timer=255\" \"$N\"\n\t\tappend base_cfg \"he_mu_edca_ac_bk_aifsn=15\" \"$N\"\n\t\tappend base_cfg \"he_mu_edca_ac_bk_aci=1\" \"$N\"\n\t\tappend base_cfg \"he_mu_edca_ac_bk_ecwmin=9\" \"$N\"\n\t\tappend base_cfg \"he_mu_edca_ac_bk_ecwmax=10\" \"$N\"\n\t\tappend base_cfg \"he_mu_edca_ac_bk_timer=255\" \"$N\"\n\t\tappend base_cfg \"he_mu_edca_ac_vi_ecwmin=5\" \"$N\"\n\t\tappend base_cfg \"he_mu_edca_ac_vi_ecwmax=7\" \"$N\"\n\t\tappend base_cfg \"he_mu_edca_ac_vi_aifsn=5\" \"$N\"\n\t\tappend base_cfg \"he_mu_edca_ac_vi_aci=2\" \"$N\"\n\t\tappend base_cfg \"he_mu_edca_ac_vi_timer=255\" \"$N\"\n\t\tappend base_cfg \"he_mu_edca_ac_vo_aifsn=5\" \"$N\"\n\t\tappend base_cfg \"he_mu_edca_ac_vo_aci=3\" \"$N\"\n\t\tappend base_cfg \"he_mu_edca_ac_vo_ecwmin=5\" \"$N\"\n\t\tappend base_cfg \"he_mu_edca_ac_vo_ecwmax=7\" \"$N\"\n\t\tappend base_cfg \"he_mu_edca_ac_vo_timer=255\" \"$N\"\n\tfi\n\n\thostapd_prepare_device_config \"$hostapd_conf_file\" nl80211\n\tcat >> \"$hostapd_conf_file\" <<EOF\n${channel:+channel=$channel}\n${channel_list:+chanlist=$channel_list}\n${hostapd_noscan:+noscan=1}\n${tx_burst:+tx_queue_data2_burst=$tx_burst}\n$base_cfg\n\nEOF\n\tjson_select ..\n\tradio_md5sum=$(md5sum $hostapd_conf_file | cut -d\" \" -f1)\n\techo \"radio_config_id=${radio_md5sum}\" >> $hostapd_conf_file\n}\n\nmac80211_hostapd_setup_bss() {\n\tlocal phy=\"$1\"\n\tlocal ifname=\"$2\"\n\tlocal macaddr=\"$3\"\n\tlocal type=\"$4\"\n\n\thostapd_cfg=\n\tappend hostapd_cfg \"$type=$ifname\" \"$N\"\n\n\thostapd_set_bss_options hostapd_cfg \"$phy\" \"$vif\" || return 1\n\tjson_get_vars wds wds_bridge dtim_period max_listen_int start_disabled\n\n\tset_default wds 0\n\tset_default start_disabled 0\n\n\t[ \"$wds\" -gt 0 ] && {\n\t\tappend hostapd_cfg \"wds_sta=1\" \"$N\"\n\t\t[ -n \"$wds_bridge\" ] && append hostapd_cfg \"wds_bridge=$wds_bridge\" \"$N\"\n\t}\n\t[ \"$staidx\" -gt 0 -o \"$start_disabled\" -eq 1 ] && append hostapd_cfg \"start_disabled=1\" \"$N\"\n\n\tcat >> /var/run/hostapd-$phy.conf <<EOF\n$hostapd_cfg\nbssid=$macaddr\n${dtim_period:+dtim_period=$dtim_period}\n${max_listen_int:+max_listen_interval=$max_listen_int}\nEOF\n}\n\nmac80211_get_addr() {\n\tlocal phy=\"$1\"\n\tlocal idx=\"$(($2 + 1))\"\n\n\thead -n $idx /sys/class/ieee80211/${phy}/addresses | tail -n1\n}\n\nmac80211_generate_mac() {\n\tlocal phy=\"$1\"\n\tlocal id=\"${macidx:-0}\"\n\n\tlocal ref=\"$(cat /sys/class/ieee80211/${phy}/macaddress)\"\n\tlocal mask=\"$(cat /sys/class/ieee80211/${phy}/address_mask)\"\n\n\t[ \"$mask\" = \"00:00:00:00:00:00\" ] && {\n\t\tmask=\"ff:ff:ff:ff:ff:ff\";\n\n\t\t[ \"$(wc -l < /sys/class/ieee80211/${phy}/addresses)\" -gt $id ] && {\n\t\t\taddr=\"$(mac80211_get_addr \"$phy\" \"$id\")\"\n\t\t\t[ -n \"$addr\" ] && {\n\t\t\t\techo \"$addr\"\n\t\t\t\treturn\n\t\t\t}\n\t\t}\n\t}\n\n\tlocal oIFS=\"$IFS\"; IFS=\":\"; set -- $mask; IFS=\"$oIFS\"\n\n\tlocal mask1=$1\n\tlocal mask6=$6\n\n\tlocal oIFS=\"$IFS\"; IFS=\":\"; set -- $ref; IFS=\"$oIFS\"\n\n\tmacidx=$(($id + 1))\n\t[ \"$((0x$mask1))\" -gt 0 ] && {\n\t\tb1=\"0x$1\"\n\t\t[ \"$id\" -gt 0 ] && \\\n\t\t\tb1=$(($b1 ^ ((($id - !($b1 & 2)) << 2)) | 0x2))\n\t\tprintf \"%02x:%s:%s:%s:%s:%s\" $b1 $2 $3 $4 $5 $6\n\t\treturn\n\t}\n\n\t[ \"$((0x$mask6))\" -lt 255 ] && {\n\t\tprintf \"%s:%s:%s:%s:%s:%02x\" $1 $2 $3 $4 $5 $(( 0x$6 ^ $id ))\n\t\treturn\n\t}\n\n\toff2=$(( (0x$6 + $id) / 0x100 ))\n\tprintf \"%s:%s:%s:%s:%02x:%02x\" \\\n\t\t$1 $2 $3 $4 \\\n\t\t$(( (0x$5 + $off2) % 0x100 )) \\\n\t\t$(( (0x$6 + $id) % 0x100 ))\n}\n\nfind_phy() {\n\t[ -n \"$phy\" -a -d /sys/class/ieee80211/$phy ] && return 0\n\t[ -n \"$path\" ] && {\n\t\tphy=\"$(iwinfo nl80211 phyname \"path=$path\")\"\n\t\t[ -n \"$phy\" ] && return 0\n\t}\n\t[ -n \"$macaddr\" ] && {\n\t\tfor phy in $(ls /sys/class/ieee80211 2>/dev/null); do\n\t\t\tgrep -i -q \"$macaddr\" \"/sys/class/ieee80211/${phy}/macaddress\" && return 0\n\t\tdone\n\t}\n\treturn 1\n}\n\nmac80211_check_ap() {\n\thas_ap=1\n}\n\nmac80211_iw_interface_add() {\n\tlocal phy=\"$1\"\n\tlocal ifname=\"$2\"\n\tlocal type=\"$3\"\n\tlocal wdsflag=\"$4\"\n\tlocal rc\n\tlocal oldifname\n\n\tiw phy \"$phy\" interface add \"$ifname\" type \"$type\" $wdsflag >/dev/null 2>&1\n\trc=\"$?\"\n\n\t[ \"$rc\" = 233 ] && {\n\t\t# Device might have just been deleted, give the kernel some time to finish cleaning it up\n\t\tsleep 1\n\n\t\tiw phy \"$phy\" interface add \"$ifname\" type \"$type\" $wdsflag >/dev/null 2>&1\n\t\trc=\"$?\"\n\t}\n\n\t[ \"$rc\" = 233 ] && {\n\t\t# Keep matching pre-existing interface\n\t\t[ -d \"/sys/class/ieee80211/${phy}/device/net/${ifname}\" ] && \\\n\t\tcase \"$(iw dev $ifname info | grep \"^\\ttype\" | cut -d' ' -f2- 2>/dev/null)\" in\n\t\t\t\"AP\")\n\t\t\t\t[ \"$type\" = \"__ap\" ] && rc=0\n\t\t\t\t;;\n\t\t\t\"IBSS\")\n\t\t\t\t[ \"$type\" = \"adhoc\" ] && rc=0\n\t\t\t\t;;\n\t\t\t\"managed\")\n\t\t\t\t[ \"$type\" = \"managed\" ] && rc=0\n\t\t\t\t;;\n\t\t\t\"mesh point\")\n\t\t\t\t[ \"$type\" = \"mp\" ] && rc=0\n\t\t\t\t;;\n\t\t\t\"monitor\")\n\t\t\t\t[ \"$type\" = \"monitor\" ] && rc=0\n\t\t\t\t;;\n\t\tesac\n\t}\n\n\t[ \"$rc\" = 233 ] && {\n\t\tiw dev \"$ifname\" del >/dev/null 2>&1\n\t\t[ \"$?\" = 0 ] && {\n\t\t\tsleep 1\n\n\t\t\tiw phy \"$phy\" interface add \"$ifname\" type \"$type\" $wdsflag >/dev/null 2>&1\n\t\t\trc=\"$?\"\n\t\t}\n\t}\n\n\t[ \"$rc\" != 0 ] && {\n\t\t# Device might not support virtual interfaces, so the interface never got deleted in the first place.\n\t\t# Check if the interface already exists, and avoid failing in this case.\n\t\t[ -d \"/sys/class/ieee80211/${phy}/device/net/${ifname}\" ] && rc=0\n\t}\n\n\t[ \"$rc\" != 0 ] && {\n\t\t# Device doesn't support virtual interfaces and may have existing interface other than ifname.\n\t\toldifname=\"$(basename \"/sys/class/ieee80211/${phy}/device/net\"/* 2>/dev/null)\"\n\t\t[ \"$oldifname\" ] && ip link set \"$oldifname\" name \"$ifname\" 1>/dev/null 2>&1\n\t\trc=\"$?\"\n\t}\n\n\t[ \"$rc\" != 0 ] && echo \"Failed to create interface $ifname\"\n\treturn $rc\n}\n\nmac80211_prepare_vif() {\n\tjson_select config\n\n\tjson_get_vars ifname mode ssid wds powersave macaddr enable wpa_psk_file vlan_file\n\n\t[ -n \"$ifname\" ] || ifname=\"wlan${phy#phy}${if_idx:+-$if_idx}\"\n\tif_idx=$((${if_idx:-0} + 1))\n\n\tset_default wds 0\n\tset_default powersave 0\n\n\tjson_select ..\n\n\t[ -n \"$macaddr\" ] || {\n\t\tmacaddr=\"$(mac80211_generate_mac $phy)\"\n\t\tmacidx=\"$(($macidx + 1))\"\n\t}\n\n\tjson_add_object data\n\tjson_add_string ifname \"$ifname\"\n\tjson_close_object\n\n\t[ \"$mode\" == \"ap\" ] && {\n\t\t[ -z \"$wpa_psk_file\" ] && hostapd_set_psk \"$ifname\"\n\t\t[ -z \"$vlan_file\" ] && hostapd_set_vlan \"$ifname\"\n\t}\n\n\tjson_select config\n\n\t# It is far easier to delete and create the desired interface\n\tcase \"$mode\" in\n\t\tadhoc)\n\t\t\tmac80211_iw_interface_add \"$phy\" \"$ifname\" adhoc || return\n\t\t;;\n\t\tap)\n\t\t\t# Hostapd will handle recreating the interface and\n\t\t\t# subsequent virtual APs belonging to the same PHY\n\t\t\tif [ -n \"$hostapd_ctrl\" ]; then\n\t\t\t\ttype=bss\n\t\t\telse\n\t\t\t\ttype=interface\n\t\t\tfi\n\n\t\t\tmac80211_hostapd_setup_bss \"$phy\" \"$ifname\" \"$macaddr\" \"$type\" || return\n\n\t\t\tNEWAPLIST=\"${NEWAPLIST}$ifname \"\n\t\t\t[ -n \"$hostapd_ctrl\" ] || {\n\t\t\t\tap_ifname=\"${ifname}\"\n\t\t\t\thostapd_ctrl=\"${hostapd_ctrl:-/var/run/hostapd/$ifname}\"\n\t\t\t}\n\t\t;;\n\t\tmesh)\n\t\t\tmac80211_iw_interface_add \"$phy\" \"$ifname\" mp || return\n\t\t;;\n\t\tmonitor)\n\t\t\tmac80211_iw_interface_add \"$phy\" \"$ifname\" monitor || return\n\t\t;;\n\t\tsta)\n\t\t\tlocal wdsflag=\n\t\t\t[ \"$enable\" = 0 ] || staidx=\"$(($staidx + 1))\"\n\t\t\t[ \"$wds\" -gt 0 ] && wdsflag=\"4addr on\"\n\t\t\tmac80211_iw_interface_add \"$phy\" \"$ifname\" managed \"$wdsflag\" || return\n\t\t\tif [ \"$wds\" -gt 0 ]; then\n\t\t\t\tiw \"$ifname\" set 4addr on\n\t\t\telse\n\t\t\t\tiw \"$ifname\" set 4addr off\n\t\t\tfi\n\t\t\t[ \"$powersave\" -gt 0 ] && powersave=\"on\" || powersave=\"off\"\n\t\t\tiw \"$ifname\" set power_save \"$powersave\"\n\t\t;;\n\tesac\n\n\tcase \"$mode\" in\n\t\tmonitor|mesh)\n\t\t\t[ \"$auto_channel\" -gt 0 ] || iw dev \"$ifname\" set channel \"$channel\" $iw_htmode\n\t\t;;\n\tesac\n\n\tif [ \"$mode\" != \"ap\" ]; then\n\t\t# ALL ap functionality will be passed to hostapd\n\t\t# All interfaces must have unique mac addresses\n\t\t# which can either be explicitly set in the device\n\t\t# section, or automatically generated\n\t\tip link set dev \"$ifname\" address \"$macaddr\"\n\tfi\n\n\tjson_select ..\n}\n\nmac80211_setup_supplicant() {\n\tlocal enable=$1\n\tlocal add_sp=0\n\tlocal spobj=\"$(ubus -S list | grep wpa_supplicant.${ifname})\"\n\n\t[ \"$enable\" = 0 ] && {\n\t\tubus call wpa_supplicant.${phy} config_remove \"{\\\"iface\\\":\\\"$ifname\\\"}\"\n\t\tip link set dev \"$ifname\" down\n\t\tiw dev \"$ifname\" del\n\t\treturn 0\n\t}\n\n\twpa_supplicant_prepare_interface \"$ifname\" nl80211 || {\n\t\tiw dev \"$ifname\" del\n\t\treturn 1\n\t}\n\tif [ \"$mode\" = \"sta\" ]; then\n\t\twpa_supplicant_add_network \"$ifname\"\n\telse\n\t\twpa_supplicant_add_network \"$ifname\" \"$freq\" \"$htmode\" \"$noscan\"\n\tfi\n\n\tNEWSPLIST=\"${NEWSPLIST}$ifname \"\n\n\tif [ \"${NEWAPLIST%% *}\" != \"${OLDAPLIST%% *}\" ]; then\n\t\t[ \"$spobj\" ] && ubus call wpa_supplicant config_remove \"{\\\"iface\\\":\\\"$ifname\\\"}\"\n\t\tadd_sp=1\n\tfi\n\t[ -z \"$spobj\" ] && add_sp=1\n\n\tNEW_MD5_SP=$(test -e \"${_config}\" && md5sum ${_config})\n\tOLD_MD5_SP=$(uci -q -P /var/state get wireless._${phy}.md5_${ifname})\n\tif [ \"$add_sp\" = \"1\" ]; then\n\t\twpa_supplicant_run \"$ifname\" \"$hostapd_ctrl\"\n\telse\n\t\t[ \"${NEW_MD5_SP}\" == \"${OLD_MD5_SP}\" ] || ubus call $spobj reload\n\tfi\n\tuci -q -P /var/state set wireless._${phy}.md5_${ifname}=\"${NEW_MD5_SP}\"\n\treturn 0\n}\n\nmac80211_setup_supplicant_noctl() {\n\tlocal enable=$1\n\tlocal spobj=\"$(ubus -S list | grep wpa_supplicant.${ifname})\"\n\twpa_supplicant_prepare_interface \"$ifname\" nl80211 || {\n\t\tiw dev \"$ifname\" del\n\t\treturn 1\n\t}\n\n\twpa_supplicant_add_network \"$ifname\" \"$freq\" \"$htmode\" \"$noscan\"\n\n\tNEWSPLIST=\"${NEWSPLIST}$ifname \"\n\t[ \"$enable\" = 0 ] && {\n\t\tubus call wpa_supplicant config_remove \"{\\\"iface\\\":\\\"$ifname\\\"}\"\n\t\tip link set dev \"$ifname\" down\n\t\treturn 0\n\t}\n\tif [ -z \"$spobj\" ]; then\n\t\twpa_supplicant_run \"$ifname\"\n\telse\n\t\tubus call $spobj reload\n\tfi\n}\n\nmac80211_prepare_iw_htmode() {\n\tcase \"$htmode\" in\n\t\tVHT20|HT20) iw_htmode=HT20;;\n\t\tHT40*|VHT40|VHT160)\n\t\t\tcase \"$band\" in\n\t\t\t\t2g)\n\t\t\t\t\tcase \"$htmode\" in\n\t\t\t\t\t\tHT40+) iw_htmode=\"HT40+\";;\n\t\t\t\t\t\tHT40-) iw_htmode=\"HT40-\";;\n\t\t\t\t\t\t*)\n\t\t\t\t\t\t\tif [ \"$channel\" -lt 7 ]; then\n\t\t\t\t\t\t\t\tiw_htmode=\"HT40+\"\n\t\t\t\t\t\t\telse\n\t\t\t\t\t\t\t\tiw_htmode=\"HT40-\"\n\t\t\t\t\t\t\tfi\n\t\t\t\t\t\t;;\n\t\t\t\t\tesac\n\t\t\t\t;;\n\t\t\t\t*)\n\t\t\t\t\tcase \"$(( ($channel / 4) % 2 ))\" in\n\t\t\t\t\t\t1) iw_htmode=\"HT40+\" ;;\n\t\t\t\t\t\t0) iw_htmode=\"HT40-\";;\n\t\t\t\t\tesac\n\t\t\t\t;;\n\t\t\tesac\n\t\t\t[ \"$auto_channel\" -gt 0 ] && iw_htmode=\"HT40+\"\n\t\t;;\n\t\tVHT80)\n\t\t\tiw_htmode=\"80MHZ\"\n\t\t;;\n\t\tNONE|NOHT)\n\t\t\tiw_htmode=\"NOHT\"\n\t\t;;\n\t\t*) iw_htmode=\"\" ;;\n\tesac\n}\n\nmac80211_setup_adhoc() {\n\tlocal enable=$1\n\tjson_get_vars bssid ssid key mcast_rate\n\n\tNEWUMLIST=\"${NEWUMLIST}$ifname \"\n\n\t[ \"$enable\" = 0 ] && {\n\t\tip link set dev \"$ifname\" down\n\t\treturn 0\n\t}\n\n\tkeyspec=\n\t[ \"$auth_type\" = \"wep\" ] && {\n\t\tset_default key 1\n\t\tcase \"$key\" in\n\t\t\t[1234])\n\t\t\t\tlocal idx\n\t\t\t\tfor idx in 1 2 3 4; do\n\t\t\t\t\tjson_get_var ikey \"key$idx\"\n\n\t\t\t\t\t[ -n \"$ikey\" ] && {\n\t\t\t\t\t\tikey=\"$(($idx - 1)):$(prepare_key_wep \"$ikey\")\"\n\t\t\t\t\t\t[ $idx -eq $key ] && ikey=\"d:$ikey\"\n\t\t\t\t\t\tappend keyspec \"$ikey\"\n\t\t\t\t\t}\n\t\t\t\tdone\n\t\t\t;;\n\t\t\t*)\n\t\t\t\tappend keyspec \"d:0:$(prepare_key_wep \"$key\")\"\n\t\t\t;;\n\t\tesac\n\t}\n\n\tbrstr=\n\tfor br in $basic_rate_list; do\n\t\twpa_supplicant_add_rate brstr \"$br\"\n\tdone\n\n\tmcval=\n\t[ -n \"$mcast_rate\" ] && wpa_supplicant_add_rate mcval \"$mcast_rate\"\n\n\tiw dev \"$ifname\" set type ibss\n\tiw dev \"$ifname\" ibss join \"$ssid\" $freq $iw_htmode fixed-freq $bssid \\\n\t\tbeacon-interval $beacon_int \\\n\t\t${brstr:+basic-rates $brstr} \\\n\t\t${mcval:+mcast-rate $mcval} \\\n\t\t${keyspec:+keys $keyspec}\n}\n\nmac80211_setup_mesh() {\n\tlocal enable=$1\n\tjson_get_vars ssid mesh_id mcast_rate\n\n\tNEWUMLIST=\"${NEWUMLIST}$ifname \"\n\n\t[ \"$enable\" = 0 ] && {\n\t\tip link set dev \"$ifname\" down\n\t\treturn 0\n\t}\n\n\tmcval=\n\t[ -n \"$mcast_rate\" ] && wpa_supplicant_add_rate mcval \"$mcast_rate\"\n\t[ -n \"$mesh_id\" ] && ssid=\"$mesh_id\"\n\n\tiw dev \"$ifname\" mesh join \"$ssid\" freq $freq $iw_htmode \\\n\t\t${mcval:+mcast-rate $mcval} \\\n\t\tbeacon-interval $beacon_int\n}\n\nmac80211_setup_vif() {\n\tlocal name=\"$1\"\n\tlocal failed\n\tlocal action=up\n\n\tjson_select data\n\tjson_get_vars ifname\n\tjson_select ..\n\n\tjson_select config\n\tjson_get_vars mode\n\tjson_get_var vif_txpower\n\tjson_get_var vif_enable enable 1\n\n\t[ \"$vif_enable\" = 1 ] || action=down\n\tif [ \"$mode\" != \"ap\" ] || [ \"$ifname\" = \"$ap_ifname\" ]; then\n\t\tip link set dev \"$ifname\" \"$action\" || {\n\t\t\twireless_setup_vif_failed IFUP_ERROR\n\t\t\tjson_select ..\n\t\t\treturn\n\t\t}\n\t\t[ -z \"$vif_txpower\" ] || iw dev \"$ifname\" set txpower fixed \"${vif_txpower%%.*}00\"\n\tfi\n\n\tcase \"$mode\" in\n\t\tmesh)\n\t\t\twireless_vif_parse_encryption\n\t\t\t[ -z \"$htmode\" ] && htmode=\"NOHT\";\n\t\t\tif [ \"$wpa\" -gt 0 -o \"$auto_channel\" -gt 0 ] || chan_is_dfs \"$phy\" \"$channel\"; then\n\t\t\t\tmac80211_setup_supplicant $vif_enable || failed=1\n\t\t\telse\n\t\t\t\tmac80211_setup_mesh $vif_enable\n\t\t\tfi\n\t\t\tfor var in $MP_CONFIG_INT $MP_CONFIG_BOOL $MP_CONFIG_STRING; do\n\t\t\t\tjson_get_var mp_val \"$var\"\n\t\t\t\t[ -n \"$mp_val\" ] && iw dev \"$ifname\" set mesh_param \"$var\" \"$mp_val\"\n\t\t\tdone\n\t\t;;\n\t\tadhoc)\n\t\t\twireless_vif_parse_encryption\n\t\t\tif [ \"$wpa\" -gt 0 -o \"$auto_channel\" -gt 0 ]; then\n\t\t\t\tmac80211_setup_supplicant_noctl $vif_enable || failed=1\n\t\t\telse\n\t\t\t\tmac80211_setup_adhoc $vif_enable\n\t\t\tfi\n\t\t;;\n\t\tsta)\n\t\t\tmac80211_setup_supplicant $vif_enable || failed=1\n\t\t;;\n\tesac\n\n\tjson_select ..\n\t[ -n \"$failed\" ] || wireless_add_vif \"$name\" \"$ifname\"\n}\n\nget_freq() {\n\tlocal phy=\"$1\"\n\tlocal channel=\"$2\"\n\tlocal band=\"$3\"\n\n\tcase \"$band\" in\n\t\t2g) band=\"1:\";;\n\t\t5g) band=\"2:\";;\n\t\t60g) band=\"3:\";;\n\t\t6g) band=\"4:\";;\n\tesac\n\n\tiw \"$phy\" info | awk -v band=\"$band\" -v channel=\"[$channel]\" '\n\n$1 ~ /Band/ {\n\tband_match = band == $2\n}\n\nband_match && $3 == \"MHz\" && $4 == channel {\n\tprint $2\n\texit\n}\n'\n}\n\n\nchan_is_dfs() {\n\tlocal phy=\"$1\"\n\tlocal chan=\"$2\"\n\tiw \"$phy\" info | grep -E -m1 \"(\\* ${chan:-....} MHz${chan:+|\\\\[$chan\\\\]})\" | grep -q \"MHz.*radar detection\"\n\treturn $!\n}\n\nmac80211_vap_cleanup() {\n\tlocal service=\"$1\"\n\tlocal vaps=\"$2\"\n\n\tfor wdev in $vaps; do\n\t\t[ \"$service\" != \"none\" ] && ubus call ${service} config_remove \"{\\\"iface\\\":\\\"$wdev\\\"}\"\n\t\tip link set dev \"$wdev\" down 2>/dev/null\n\t\tiw dev \"$wdev\" del\n\tdone\n}\n\nmac80211_interface_cleanup() {\n\tlocal phy=\"$1\"\n\tlocal primary_ap=$(uci -q -P /var/state get wireless._${phy}.aplist)\n\tprimary_ap=${primary_ap%% *}\n\n\tmac80211_vap_cleanup hostapd \"${primary_ap}\"\n\tmac80211_vap_cleanup wpa_supplicant \"$(uci -q -P /var/state get wireless._${phy}.splist)\"\n\tmac80211_vap_cleanup none \"$(uci -q -P /var/state get wireless._${phy}.umlist)\"\n}\n\nmac80211_set_noscan() {\n\thostapd_noscan=1\n}\n\ndrv_mac80211_cleanup() {\n\thostapd_common_cleanup\n}\n\ndrv_mac80211_setup() {\n\tjson_select config\n\tjson_get_vars \\\n\t\tphy macaddr path \\\n\t\tcountry chanbw distance \\\n\t\ttxpower antenna_gain \\\n\t\trxantenna txantenna \\\n\t\tfrag rts beacon_int:100 htmode\n\tjson_get_values basic_rate_list basic_rate\n\tjson_get_values scan_list scan_list\n\tjson_select ..\n\n\tfind_phy || {\n\t\techo \"Could not find PHY for device '$1'\"\n\t\twireless_set_retry 0\n\t\treturn 1\n\t}\n\n\twireless_set_data phy=\"$phy\"\n\t[ -z \"$(uci -q -P /var/state show wireless._${phy})\" ] && uci -q -P /var/state set wireless._${phy}=phy\n\n\tOLDAPLIST=$(uci -q -P /var/state get wireless._${phy}.aplist)\n\tOLDSPLIST=$(uci -q -P /var/state get wireless._${phy}.splist)\n\tOLDUMLIST=$(uci -q -P /var/state get wireless._${phy}.umlist)\n\n\tlocal wdev\n\tlocal cwdev\n\tlocal found\n\n\tfor wdev in $(list_phy_interfaces \"$phy\"); do\n\t\tfound=0\n\t\tfor cwdev in $OLDAPLIST $OLDSPLIST $OLDUMLIST; do\n\t\t\tif [ \"$wdev\" = \"$cwdev\" ]; then\n\t\t\t\tfound=1\n\t\t\t\tbreak\n\t\t\tfi\n\t\tdone\n\t\tif [ \"$found\" = \"0\" ]; then\n\t\t\tip link set dev \"$wdev\" down\n\t\t\tiw dev \"$wdev\" del\n\t\tfi\n\tdone\n\n\t# convert channel to frequency\n\t[ \"$auto_channel\" -gt 0 ] || freq=\"$(get_freq \"$phy\" \"$channel\" \"$band\")\"\n\n\t[ -n \"$country\" ] && {\n\t\tiw reg get | grep -q \"^country $country:\" || {\n\t\t\tiw reg set \"$country\"\n\t\t\tsleep 1\n\t\t}\n\t}\n\n\thostapd_conf_file=\"/var/run/hostapd-$phy.conf\"\n\n\tno_ap=1\n\tmacidx=0\n\tstaidx=0\n\n\t[ -n \"$chanbw\" ] && {\n\t\tfor file in /sys/kernel/debug/ieee80211/$phy/ath9k*/chanbw /sys/kernel/debug/ieee80211/$phy/ath5k/bwmode; do\n\t\t\t[ -f \"$file\" ] && echo \"$chanbw\" > \"$file\"\n\t\tdone\n\t}\n\n\tset_default rxantenna 0xffffffff\n\tset_default txantenna 0xffffffff\n\tset_default distance 0\n\tset_default antenna_gain 0\n\n\t[ \"$txantenna\" = \"all\" ] && txantenna=0xffffffff\n\t[ \"$rxantenna\" = \"all\" ] && rxantenna=0xffffffff\n\n\tiw phy \"$phy\" set antenna $txantenna $rxantenna >/dev/null 2>&1\n\tiw phy \"$phy\" set antenna_gain $antenna_gain >/dev/null 2>&1\n\tiw phy \"$phy\" set distance \"$distance\" >/dev/null 2>&1\n\n\tif [ -n \"$txpower\" ]; then\n\t\tiw phy \"$phy\" set txpower fixed \"${txpower%%.*}00\"\n\telse\n\t\tiw phy \"$phy\" set txpower auto\n\tfi\n\n\t[ -n \"$frag\" ] && iw phy \"$phy\" set frag \"${frag%%.*}\"\n\t[ -n \"$rts\" ] && iw phy \"$phy\" set rts \"${rts%%.*}\"\n\n\thas_ap=\n\thostapd_ctrl=\n\tap_ifname=\n\thostapd_noscan=\n\tfor_each_interface \"ap\" mac80211_check_ap\n\n\trm -f \"$hostapd_conf_file\"\n\n\tfor_each_interface \"sta adhoc mesh\" mac80211_set_noscan\n\t[ -n \"$has_ap\" ] && mac80211_hostapd_setup_base \"$phy\"\n\n\tmac80211_prepare_iw_htmode\n\tfor_each_interface \"sta adhoc mesh monitor\" mac80211_prepare_vif\n\tNEWAPLIST=\n\tfor_each_interface \"ap\" mac80211_prepare_vif\n\tNEW_MD5=$(test -e \"${hostapd_conf_file}\" && md5sum ${hostapd_conf_file})\n\tOLD_MD5=$(uci -q -P /var/state get wireless._${phy}.md5)\n\tif [ \"${NEWAPLIST}\" != \"${OLDAPLIST}\" ]; then\n\t\tmac80211_vap_cleanup hostapd \"${OLDAPLIST}\"\n\tfi\n\t[ -n \"${NEWAPLIST}\" ] && mac80211_iw_interface_add \"$phy\" \"${NEWAPLIST%% *}\" __ap\n\tlocal add_ap=0\n\tlocal primary_ap=${NEWAPLIST%% *}\n\t[ -n \"$hostapd_ctrl\" ] && {\n\t\tlocal no_reload=1\n\t\tif [ -n \"$(ubus list | grep hostapd.$primary_ap)\" ]; then\n\t\t\tno_reload=0\n\t\t\t[ \"${NEW_MD5}\" = \"${OLD_MD5}\" ] || {\n\t\t\t\tubus call hostapd.$primary_ap reload\n\t\t\t\tno_reload=$?\n\t\t\t\tif [ \"$no_reload\" != \"0\" ]; then\n\t\t\t\t\tmac80211_vap_cleanup hostapd \"${OLDAPLIST}\"\n\t\t\t\t\tmac80211_vap_cleanup wpa_supplicant \"$(uci -q -P /var/state get wireless._${phy}.splist)\"\n\t\t\t\t\tmac80211_vap_cleanup none \"$(uci -q -P /var/state get wireless._${phy}.umlist)\"\n\t\t\t\t\tsleep 2\n\t\t\t\t\tmac80211_iw_interface_add \"$phy\" \"${NEWAPLIST%% *}\" __ap\n\t\t\t\t\tfor_each_interface \"sta adhoc mesh monitor\" mac80211_prepare_vif\n\t\t\t\tfi\n\t\t\t}\n\t\tfi\n\t\tif [ \"$no_reload\" != \"0\" ]; then\n\t\t\tadd_ap=1\n\t\t\tubus wait_for hostapd\n\t\t\tlocal hostapd_res=\"$(ubus call hostapd config_add \"{\\\"iface\\\":\\\"$primary_ap\\\", \\\"config\\\":\\\"${hostapd_conf_file}\\\"}\")\"\n\t\t\tret=\"$?\"\n\t\t\t[ \"$ret\" != 0 -o -z \"$hostapd_res\" ] && {\n\t\t\t\twireless_setup_failed HOSTAPD_START_FAILED\n\t\t\t\treturn\n\t\t\t}\n\t\t\twireless_add_process \"$(jsonfilter -s \"$hostapd_res\" -l 1 -e @.pid)\" \"/usr/sbin/hostapd\" 1 1\n\t\tfi\n\t}\n\tuci -q -P /var/state set wireless._${phy}.aplist=\"${NEWAPLIST}\"\n\tuci -q -P /var/state set wireless._${phy}.md5=\"${NEW_MD5}\"\n\n\t[ \"${add_ap}\" = 1 ] && sleep 1\n\tfor_each_interface \"ap\" mac80211_setup_vif\n\n\tNEWSPLIST=\n\tNEWUMLIST=\n\n\tfor_each_interface \"sta adhoc mesh monitor\" mac80211_setup_vif\n\n\tuci -q -P /var/state set wireless._${phy}.splist=\"${NEWSPLIST}\"\n\tuci -q -P /var/state set wireless._${phy}.umlist=\"${NEWUMLIST}\"\n\n\tlocal foundvap\n\tlocal dropvap=\"\"\n\tfor oldvap in $OLDSPLIST; do\n\t\tfoundvap=0\n\t\tfor newvap in $NEWSPLIST; do\n\t\t\t[ \"$oldvap\" = \"$newvap\" ] && foundvap=1\n\t\tdone\n\t\t[ \"$foundvap\" = \"0\" ] && dropvap=\"$dropvap $oldvap\"\n\tdone\n\t[ -n \"$dropvap\" ] && mac80211_vap_cleanup wpa_supplicant \"$dropvap\"\n\twireless_set_up\n}\n\n_list_phy_interfaces() {\n\tlocal phy=\"$1\"\n\tif [ -d \"/sys/class/ieee80211/${phy}/device/net\" ]; then\n\t\tls \"/sys/class/ieee80211/${phy}/device/net\" 2>/dev/null;\n\telse\n\t\tls \"/sys/class/ieee80211/${phy}/device\" 2>/dev/null | grep net: | sed -e 's,net:,,g'\n\tfi\n}\n\nlist_phy_interfaces() {\n\tlocal phy=\"$1\"\n\n\tfor dev in $(_list_phy_interfaces \"$phy\"); do\n\t\treadlink \"/sys/class/net/${dev}/phy80211\" | grep -q \"/${phy}\\$\" || continue\n\t\techo \"$dev\"\n\tdone\n}\n\ndrv_mac80211_teardown() {\n\tjson_select data\n\tjson_get_vars phy\n\tjson_select ..\n\t[ -n \"$phy\" ] || {\n\t\techo \"Bug: PHY is undefined for device '$1'\"\n\t\treturn 1\n\t}\n\n\tmac80211_interface_cleanup \"$phy\"\n\tuci -q -P /var/state revert wireless._${phy}\n}\n\nadd_driver mac80211\n"
  },
  {
    "path": "package/kernel/mac80211/files/lib/wifi/mac80211.sh",
    "content": "#!/bin/sh\n\nappend DRIVERS \"mac80211\"\n\nlookup_phy() {\n\t[ -n \"$phy\" ] && {\n\t\t[ -d /sys/class/ieee80211/$phy ] && return\n\t}\n\n\tlocal devpath\n\tconfig_get devpath \"$device\" path\n\t[ -n \"$devpath\" ] && {\n\t\tphy=\"$(iwinfo nl80211 phyname \"path=$devpath\")\"\n\t\t[ -n \"$phy\" ] && return\n\t}\n\n\tlocal macaddr=\"$(config_get \"$device\" macaddr | tr 'A-Z' 'a-z')\"\n\t[ -n \"$macaddr\" ] && {\n\t\tfor _phy in /sys/class/ieee80211/*; do\n\t\t\t[ -e \"$_phy\" ] || continue\n\n\t\t\t[ \"$macaddr\" = \"$(cat ${_phy}/macaddress)\" ] || continue\n\t\t\tphy=\"${_phy##*/}\"\n\t\t\treturn\n\t\tdone\n\t}\n\tphy=\n\treturn\n}\n\nfind_mac80211_phy() {\n\tlocal device=\"$1\"\n\n\tconfig_get phy \"$device\" phy\n\tlookup_phy\n\t[ -n \"$phy\" -a -d \"/sys/class/ieee80211/$phy\" ] || {\n\t\techo \"PHY for wifi device $1 not found\"\n\t\treturn 1\n\t}\n\tconfig_set \"$device\" phy \"$phy\"\n\n\tconfig_get macaddr \"$device\" macaddr\n\t[ -z \"$macaddr\" ] && {\n\t\tconfig_set \"$device\" macaddr \"$(cat /sys/class/ieee80211/${phy}/macaddress)\"\n\t}\n\n\treturn 0\n}\n\ncheck_mac80211_device() {\n\tconfig_get phy \"$1\" phy\n\t[ -z \"$phy\" ] && {\n\t\tfind_mac80211_phy \"$1\" >/dev/null || return 0\n\t\tconfig_get phy \"$1\" phy\n\t}\n\t[ \"$phy\" = \"$dev\" ] && found=1\n}\n\n\n__get_band_defaults() {\n\tlocal phy=\"$1\"\n\n\t( iw phy \"$phy\" info; echo ) | awk '\nBEGIN {\n        bands = \"\"\n}\n\n($1 == \"Band\" || $1 == \"\") && band {\n        if (channel) {\n\t\tmode=\"NOHT\"\n\t\tif (ht) mode=\"HT20\"\n\t\tif (vht && band != \"1:\") mode=\"VHT80\"\n\t\tif (he) mode=\"HE80\"\n\t\tif (he && band == \"1:\") mode=\"HE20\"\n                sub(\"\\\\[\", \"\", channel)\n                sub(\"\\\\]\", \"\", channel)\n                bands = bands band channel \":\" mode \" \"\n        }\n        band=\"\"\n}\n\n$1 == \"Band\" {\n        band = $2\n        channel = \"\"\n\tvht = \"\"\n\tht = \"\"\n\the = \"\"\n}\n\n$0 ~ \"Capabilities:\" {\n\tht=1\n}\n\n$0 ~ \"VHT Capabilities\" {\n\tvht=1\n}\n\n$0 ~ \"HE Iftypes\" {\n\the=1\n}\n\n$1 == \"*\" && $3 == \"MHz\" && $0 !~ /disabled/ && band && !channel {\n        channel = $4\n}\n\nEND {\n        print bands\n}'\n}\n\nget_band_defaults() {\n\tlocal phy=\"$1\"\n\n\tfor c in $(__get_band_defaults \"$phy\"); do\n\t\tlocal band=\"${c%%:*}\"\n\t\tc=\"${c#*:}\"\n\t\tlocal chan=\"${c%%:*}\"\n\t\tc=\"${c#*:}\"\n\t\tlocal mode=\"${c%%:*}\"\n\n\t\tcase \"$band\" in\n\t\t\t1) band=2g;;\n\t\t\t2) band=5g;;\n\t\t\t3) band=60g;;\n\t\t\t4) band=6g;;\n\t\t\t*) band=\"\";;\n\t\tesac\n\n\t\t[ -n \"$band\" ] || continue\n\t\t[ -n \"$mode_band\" -a \"$band\" = \"6g\" ] && return\n\n\t\tmode_band=\"$band\"\n\t\tchannel=\"$chan\"\n\t\thtmode=\"$mode\"\n\tdone\n}\n\ndetect_mac80211() {\n\tdevidx=0\n\tconfig_load wireless\n\twhile :; do\n\t\tconfig_get type \"radio$devidx\" type\n\t\t[ -n \"$type\" ] || break\n\t\tdevidx=$(($devidx + 1))\n\tdone\n\n\tfor _dev in /sys/class/ieee80211/*; do\n\t\t[ -e \"$_dev\" ] || continue\n\n\t\tdev=\"${_dev##*/}\"\n\n\t\tfound=0\n\t\tconfig_foreach check_mac80211_device wifi-device\n\t\t[ \"$found\" -gt 0 ] && continue\n\n\t\tmode_band=\"\"\n\t\tchannel=\"\"\n\t\thtmode=\"\"\n\t\tht_capab=\"\"\n\n\t\tget_band_defaults \"$dev\"\n\n\t\tpath=\"$(iwinfo nl80211 path \"$dev\")\"\n\t\tif [ -n \"$path\" ]; then\n\t\t\tdev_id=\"set wireless.radio${devidx}.path='$path'\"\n\t\telse\n\t\t\tdev_id=\"set wireless.radio${devidx}.macaddr=$(cat /sys/class/ieee80211/${dev}/macaddress)\"\n\t\tfi\n\n\t\tuci -q batch <<-EOF\n\t\t\tset wireless.radio${devidx}=wifi-device\n\t\t\tset wireless.radio${devidx}.type=mac80211\n\t\t\t${dev_id}\n\t\t\tset wireless.radio${devidx}.channel=${channel}\n\t\t\tset wireless.radio${devidx}.band=${mode_band}\n\t\t\tset wireless.radio${devidx}.htmode=$htmode\n\t\t\tset wireless.radio${devidx}.disabled=1\n\n\t\t\tset wireless.default_radio${devidx}=wifi-iface\n\t\t\tset wireless.default_radio${devidx}.device=radio${devidx}\n\t\t\tset wireless.default_radio${devidx}.network=lan\n\t\t\tset wireless.default_radio${devidx}.mode=ap\n\t\t\tset wireless.default_radio${devidx}.ssid=OpenWrt\n\t\t\tset wireless.default_radio${devidx}.encryption=none\nEOF\n\t\tuci -q commit wireless\n\n\t\tdevidx=$(($devidx + 1))\n\tdone\n}\n"
  },
  {
    "path": "package/kernel/mac80211/files/mac80211.hotplug",
    "content": "#!/bin/sh\n\n[ \"${ACTION}\" = \"add\" ] && {\n\t/sbin/wifi config\n}\n"
  },
  {
    "path": "package/kernel/mac80211/intel.mk",
    "content": "PKG_DRIVERS += \\\n\tiwl-legacy iwl3945 iwl4965 iwlwifi \\\n\tlibipw ipw2100 ipw2200 \\\n\nconfig-$(call config_package,iwl-legacy) += IWLEGACY\nconfig-$(call config_package,iwl3945) += IWL3945\nconfig-$(call config_package,iwl4965) += IWL4965\nconfig-$(call config_package,iwlwifi) += IWLWIFI IWLDVM IWLMVM\nconfig-$(CONFIG_PACKAGE_IWLWIFI_DEBUG)+= IWLWIFI_DEBUG\nconfig-$(CONFIG_PACKAGE_IWLWIFI_DEBUGFS)+= IWLWIFI_DEBUGFS\n\nconfig-$(call config_package,libipw) += LIBIPW\nconfig-$(call config_package,ipw2100) += IPW2100\nconfig-$(call config_package,ipw2200) += IPW2200\n\ndefine KernelPackage/iwlwifi\n  $(call KernelPackage/mac80211/Default)\n  DEPENDS:= +kmod-mac80211 @PCI_SUPPORT +@DRIVER_11N_SUPPORT +@DRIVER_11AC_SUPPORT\n  TITLE:=Intel AGN Wireless support\n  FILES:= \\\n\t$(PKG_BUILD_DIR)/drivers/net/wireless/intel/iwlwifi/iwlwifi.ko \\\n\t$(PKG_BUILD_DIR)/drivers/net/wireless/intel/iwlwifi/dvm/iwldvm.ko \\\n\t$(PKG_BUILD_DIR)/drivers/net/wireless/intel/iwlwifi/mvm/iwlmvm.ko\n  AUTOLOAD:=$(call AutoProbe,iwlwifi iwldvm iwlmvm)\n  MENU:=1\nendef\n\ndefine KernelPackage/iwlwifi/description\n iwlwifi kernel module for\n Intel Wireless WiFi Link 6250AGN Adapter\n Intel 6000 Series Wi-Fi Adapters (6200AGN and 6300AGN)\n Intel WiFi Link 1000BGN\n Intel Wireless WiFi 5150AGN\n Intel Wireless WiFi 5100AGN, 5300AGN, and 5350AGN\n Intel 6005 Series Wi-Fi Adapters\n Intel 6030 Series Wi-Fi Adapters\n Intel Wireless WiFi Link 6150BGN 2 Adapter\n Intel 100 Series Wi-Fi Adapters (100BGN and 130BGN)\n Intel 2000 Series Wi-Fi Adapters\n Intel 7260 Wi-Fi Adapter\n Intel 3160 Wi-Fi Adapter\n Intel 7265 Wi-Fi Adapter\n Intel 8260 Wi-Fi Adapter\n Intel 3165 Wi-Fi Adapter\nendef\n\ndefine KernelPackage/iwlwifi/config\n  if PACKAGE_kmod-iwlwifi\n\n\tconfig PACKAGE_IWLWIFI_DEBUG\n\t\tbool \"Enable full debugging output in the iwlwifi driver\"\n\t\tdefault n\n\t\thelp\n\t\t  This option will enable debug tracing output for the iwlwifi drivers\n\n\t\t  This will result in the kernel module being ~100k larger.  You can\n\t\t  control which debug output is sent to the kernel log by setting the\n\t\t  value in\n\n\t\t\t/sys/module/iwlwifi/parameters/debug\n\n\t\t  This entry will only exist if this option is enabled.\n\n\t\t  To set a value, simply echo an 8-byte hex value to the same file:\n\n\t\t\t  % echo 0x43fff > /sys/module/iwlwifi/parameters/debug\n\n\t\t  You can find the list of debug mask values in:\n\t\t\t  drivers/net/wireless/intel/iwlwifi/iwl-debug.h\n\n\t\t  If this is your first time using this driver, you should say Y here\n\t\t  as the debug information can assist others in helping you resolve\n\t\t  any problems you may encounter.\n\n\tconfig PACKAGE_IWLWIFI_DEBUGFS\n\t        bool \"iwlwifi debugfs support\"\n\t\tdepends on PACKAGE_MAC80211_DEBUGFS\n\t\tdefault n\n\t\thelp\n\t\t  Enable creation of debugfs files for the iwlwifi drivers. This\n\t\t  is a low-impact option that allows getting insight into the\n\t\t  driver's state at runtime.\n\n  endif\nendef\n\ndefine KernelPackage/iwl-legacy\n  $(call KernelPackage/mac80211/Default)\n  DEPENDS:= +kmod-mac80211 @PCI_SUPPORT\n  TITLE:=Intel legacy Wireless support\n  FILES:=$(PKG_BUILD_DIR)/drivers/net/wireless/intel/iwlegacy/iwlegacy.ko\n  AUTOLOAD:=$(call AutoProbe,iwlegacy)\nendef\n\ndefine KernelPackage/iwl-legacy/description\n iwl-legacy kernel module for legacy Intel wireless support\nendef\n\ndefine KernelPackage/iwl3945\n  $(call KernelPackage/mac80211/Default)\n  DEPENDS:= +kmod-mac80211 +kmod-iwl-legacy +iwl3945-firmware\n  TITLE:=Intel iwl3945 Wireless support\n  FILES:=$(PKG_BUILD_DIR)/drivers/net/wireless/intel/iwlegacy/iwl3945.ko\n  AUTOLOAD:=$(call AutoProbe,iwl3945)\nendef\n\ndefine KernelPackage/iwl3945/description\n iwl3945 kernel module for Intel 3945 support\nendef\n\ndefine KernelPackage/iwl4965\n  $(call KernelPackage/mac80211/Default)\n  DEPENDS:= +kmod-mac80211 +kmod-iwl-legacy +@DRIVER_11N_SUPPORT +iwl4965-firmware\n  TITLE:=Intel iwl4965 Wireless support\n  FILES:=$(PKG_BUILD_DIR)/drivers/net/wireless/intel/iwlegacy/iwl4965.ko\n  AUTOLOAD:=$(call AutoProbe,iwl4965)\nendef\n\ndefine KernelPackage/iwl4965/description\n iwl4965 kernel module for Intel 4965 support\nendef\n\n\ndefine KernelPackage/libipw\n  $(call KernelPackage/mac80211/Default)\n  TITLE:=libipw for ipw2100 and ipw2200\n  DEPENDS:=@PCI_SUPPORT +kmod-crypto-michael-mic +kmod-crypto-ecb +kmod-lib80211 +kmod-cfg80211 +@DRIVER_WEXT_SUPPORT @!BIG_ENDIAN\n  FILES:=$(PKG_BUILD_DIR)/drivers/net/wireless/intel/ipw2x00/libipw.ko\n  AUTOLOAD:=$(call AutoProbe,libipw)\nendef\n\ndefine KernelPackage/libipw/description\n Hardware independent IEEE 802.11 networking stack for ipw2100 and ipw2200.\nendef\n\nIPW2100_NAME:=ipw2100-fw\nIPW2100_VERSION:=1.3\n\ndefine Download/ipw2100\n  URL:= \\\n\thttps://src.fedoraproject.org/repo/pkgs/ipw2100-firmware/ipw2100-fw-1.3.tgz/46aa75bcda1a00efa841f9707bbbd113/ \\\n\thttps://archlinux.mirror.pkern.at/other/packages/ipw2100-fw/ \\\n\thttp://mirror.ox.ac.uk/sites/ftp.openbsd.org/pub/OpenBSD/distfiles/firmware/ \\\n\thttp://firmware.openbsd.org/firmware-dist/\n  FILE:=$(IPW2100_NAME)-$(IPW2100_VERSION).tgz\n  HASH:=e1107c455e48d324a616b47a622593bc8413dcce72026f72731c0b03dae3a7a2\nendef\n$(eval $(call Download,ipw2100))\n\ndefine KernelPackage/ipw2100\n  $(call KernelPackage/mac80211/Default)\n  TITLE:=Intel IPW2100 driver\n  DEPENDS:=@PCI_SUPPORT +kmod-libipw\n  FILES:=$(PKG_BUILD_DIR)/drivers/net/wireless/intel/ipw2x00/ipw2100.ko\n  AUTOLOAD:=$(call AutoProbe,ipw2100)\nendef\n\ndefine KernelPackage/ipw2100/description\n Kernel support for Intel IPW2100\n Includes:\n - ipw2100\nendef\n\nIPW2200_NAME:=ipw2200-fw\nIPW2200_VERSION:=3.1\n\ndefine Download/ipw2200\n  URL:= \\\n\thttps://src.fedoraproject.org/repo/pkgs/ipw2200-firmware/ipw2200-fw-3.1.tgz/eaba788643c7cc7483dd67ace70f6e99/ \\\n\thttps://archlinux.mirror.pkern.at/other/packages/ipw2200-fw/ \\\n\thttp://mirror.ox.ac.uk/sites/ftp.openbsd.org/pub/OpenBSD/distfiles/firmware/ \\\n\thttp://firmware.openbsd.org/firmware-dist/\n  FILE:=$(IPW2200_NAME)-$(IPW2200_VERSION).tgz\n  HASH:=c6818c11c18cc030d55ff83f64b2bad8feef485e7742f84f94a61d811a6258bd\nendef\n$(eval $(call Download,ipw2200))\n\ndefine KernelPackage/ipw2200\n  $(call KernelPackage/mac80211/Default)\n  TITLE:=Intel IPW2200 driver\n  DEPENDS:=@PCI_SUPPORT +kmod-libipw\n  FILES:=$(PKG_BUILD_DIR)/drivers/net/wireless/intel/ipw2x00/ipw2200.ko\n  AUTOLOAD:=$(call AutoProbe,ipw2200)\nendef\n\ndefine KernelPackage/ipw2200/description\n Kernel support for Intel IPW2200\n Includes:\n - ipw2200\nendef\n\ndefine KernelPackage/ipw2100/install\n\t$(INSTALL_DIR) $(1)/lib/firmware\n\t$(INSTALL_DATA) $(PKG_BUILD_DIR)/ipw2100-$(IPW2100_VERSION)*.fw $(1)/lib/firmware\nendef\n\ndefine KernelPackage/ipw2200/install\n\t$(INSTALL_DIR) $(1)/lib/firmware\n\t$(INSTALL_DATA) $(PKG_BUILD_DIR)/$(IPW2200_NAME)-$(IPW2200_VERSION)/ipw2200*.fw $(1)/lib/firmware\nendef\n"
  },
  {
    "path": "package/kernel/mac80211/marvell.mk",
    "content": "PKG_DRIVERS += \\\n\tlibertas-sdio libertas-usb libertas-spi \\\n\tmwl8k mwifiex-pcie mwifiex-sdio\n\nconfig-$(call config_package,libertas-sdio) += LIBERTAS LIBERTAS_SDIO\nconfig-$(call config_package,libertas-usb) += LIBERTAS LIBERTAS_USB\nconfig-$(call config_package,libertas-spi) += LIBERTAS LIBERTAS_SPI\nconfig-$(call config_package,mwl8k) += MWL8K\nconfig-$(call config_package,mwifiex-pcie) += MWIFIEX MWIFIEX_PCIE\nconfig-$(call config_package,mwifiex-sdio) += MWIFIEX MWIFIEX_SDIO\n\ndefine KernelPackage/libertas-usb\n  $(call KernelPackage/mac80211/Default)\n  DEPENDS+= @USB_SUPPORT +kmod-cfg80211 +kmod-usb-core +kmod-lib80211 +@DRIVER_WEXT_SUPPORT +libertas-usb-firmware\n  TITLE:=Marvell 88W8015 Wireless Driver\n  FILES:= \\\n\t$(PKG_BUILD_DIR)/drivers/net/wireless/marvell/libertas/libertas.ko \\\n\t$(PKG_BUILD_DIR)/drivers/net/wireless/marvell/libertas/usb8xxx.ko\n  AUTOLOAD:=$(call AutoProbe,libertas usb8xxx)\nendef\n\ndefine KernelPackage/libertas-sdio\n  $(call KernelPackage/mac80211/Default)\n  DEPENDS+= +kmod-cfg80211 +kmod-lib80211 +kmod-mmc +@DRIVER_WEXT_SUPPORT @!TARGET_uml +libertas-sdio-firmware\n  TITLE:=Marvell 88W8686 Wireless Driver\n  FILES:= \\\n\t$(PKG_BUILD_DIR)/drivers/net/wireless/marvell/libertas/libertas.ko \\\n\t$(PKG_BUILD_DIR)/drivers/net/wireless/marvell/libertas/libertas_sdio.ko\n  AUTOLOAD:=$(call AutoProbe,libertas libertas_sdio)\nendef\n\ndefine KernelPackage/libertas-spi\n  $(call KernelPackage/mac80211/Default)\n  SUBMENU:=Wireless Drivers\n  DEPENDS+= +kmod-cfg80211 +kmod-lib80211 +@DRIVER_WEXT_SUPPORT @!TARGET_uml +libertas-spi-firmware\n  KCONFIG := \\\n\tCONFIG_SPI=y \\\n\tCONFIG_SPI_MASTER=y\n  TITLE:=Marvell 88W8686 SPI Wireless Driver\n  FILES:= \\\n\t$(PKG_BUILD_DIR)/drivers/net/wireless/marvell/libertas/libertas.ko \\\n\t$(PKG_BUILD_DIR)/drivers/net/wireless/marvell/libertas/libertas_spi.ko\n  AUTOLOAD:=$(call AutoProbe,libertas libertas_spi)\nendef\n\n\ndefine KernelPackage/mwl8k\n  $(call KernelPackage/mac80211/Default)\n  TITLE:=Driver for Marvell TOPDOG 802.11 Wireless cards\n  URL:=https://wireless.wiki.kernel.org/en/users/drivers/mwl8k\n  DEPENDS+= @PCI_SUPPORT +kmod-mac80211 +@DRIVER_11N_SUPPORT +mwl8k-firmware\n  FILES:=$(PKG_BUILD_DIR)/drivers/net/wireless/marvell/mwl8k.ko\n  AUTOLOAD:=$(call AutoProbe,mwl8k)\nendef\n\ndefine KernelPackage/mwl8k/description\n Kernel modules for Marvell TOPDOG 802.11 Wireless cards\nendef\n\n\ndefine KernelPackage/mwifiex-pcie\n  $(call KernelPackage/mac80211/Default)\n  TITLE:=Driver for Marvell 802.11n/802.11ac PCIe Wireless cards\n  URL:=https://wireless.wiki.kernel.org/en/users/drivers/mwifiex\n  DEPENDS+= @PCI_SUPPORT +kmod-mac80211 +@DRIVER_11N_SUPPORT +@DRIVER_11AC_SUPPORT +mwifiex-pcie-firmware\n  FILES:= \\\n\t$(PKG_BUILD_DIR)/drivers/net/wireless/marvell/mwifiex/mwifiex.ko \\\n\t$(PKG_BUILD_DIR)/drivers/net/wireless/marvell/mwifiex/mwifiex_pcie.ko\n  AUTOLOAD:=$(call AutoProbe,mwifiex_pcie)\nendef\n\ndefine KernelPackage/mwifiex-pcie/description\n Kernel modules for Marvell 802.11n/802.11ac PCIe Wireless cards\nendef\n\ndefine KernelPackage/mwifiex-sdio\n  $(call KernelPackage/mac80211/Default)\n  TITLE:=Driver for Marvell 802.11n/802.11ac SDIO Wireless cards\n  URL:=https://wireless.wiki.kernel.org/en/users/drivers/mwifiex\n  DEPENDS+= +kmod-mmc +kmod-mac80211 +@DRIVER_11N_SUPPORT +@DRIVER_11AC_SUPPORT +mwifiex-sdio-firmware\n  FILES:= \\\n\t$(PKG_BUILD_DIR)/drivers/net/wireless/marvell/mwifiex/mwifiex.ko \\\n\t$(PKG_BUILD_DIR)/drivers/net/wireless/marvell/mwifiex/mwifiex_sdio.ko\n  AUTOLOAD:=$(call AutoProbe,mwifiex_sdio)\nendef\n\ndefine KernelPackage/mwifiex-sdio/description\n Kernel modules for Marvell 802.11n/802.11ac SDIO Wireless cards\nendef\n\n"
  },
  {
    "path": "package/kernel/mac80211/patches/ath/070-ath_common_config.patch",
    "content": "--- a/drivers/net/wireless/ath/Kconfig\n+++ b/drivers/net/wireless/ath/Kconfig\n@@ -1,6 +1,6 @@\n # SPDX-License-Identifier: ISC\n config ATH_COMMON\n-\ttristate\n+\ttristate \"ath.ko\"\n \tdepends on m\n \n config WLAN_VENDOR_ATH\n"
  },
  {
    "path": "package/kernel/mac80211/patches/ath/400-ath_move_debug_code.patch",
    "content": "--- a/drivers/net/wireless/ath/Makefile\n+++ b/drivers/net/wireless/ath/Makefile\n@@ -15,10 +15,10 @@ ath-objs :=\tmain.o \\\n \t\tregd.o \\\n \t\thw.o \\\n \t\tkey.o \\\n+\t\tdebug.o \\\n \t\tdfs_pattern_detector.o \\\n \t\tdfs_pri_detector.o\n \n-ath-$(CPTCFG_ATH_DEBUG) += debug.o\n ath-$(CPTCFG_ATH_TRACEPOINTS) += trace.o\n \n CFLAGS_trace.o := -I$(src)\n--- a/drivers/net/wireless/ath/ath.h\n+++ b/drivers/net/wireless/ath/ath.h\n@@ -317,14 +317,7 @@ void _ath_dbg(struct ath_common *common,\n #endif /* CPTCFG_ATH_DEBUG */\n \n /** Returns string describing opmode, or NULL if unknown mode. */\n-#ifdef CPTCFG_ATH_DEBUG\n const char *ath_opmode_to_string(enum nl80211_iftype opmode);\n-#else\n-static inline const char *ath_opmode_to_string(enum nl80211_iftype opmode)\n-{\n-\treturn \"UNKNOWN\";\n-}\n-#endif\n \n extern const char *ath_bus_type_strings[];\n static inline const char *ath_bus_type_to_string(enum ath_bus_type bustype)\n"
  },
  {
    "path": "package/kernel/mac80211/patches/ath/402-ath_regd_optional.patch",
    "content": "--- a/drivers/net/wireless/ath/regd.c\n+++ b/drivers/net/wireless/ath/regd.c\n@@ -24,6 +24,7 @@\n #include \"regd_common.h\"\n \n static int __ath_regd_init(struct ath_regulatory *reg);\n+static struct reg_dmn_pair_mapping *ath_get_regpair(int regdmn);\n \n /*\n  * This is a set of common rules used by our world regulatory domains.\n@@ -116,6 +117,9 @@ static const struct ieee80211_regdomain\n \n static bool dynamic_country_user_possible(struct ath_regulatory *reg)\n {\n+\tif (IS_ENABLED(CPTCFG_ATH_USER_REGD))\n+\t\treturn true;\n+\n \tif (IS_ENABLED(CPTCFG_ATH_REG_DYNAMIC_USER_CERT_TESTING))\n \t\treturn true;\n \n@@ -188,6 +192,8 @@ static bool dynamic_country_user_possibl\n \n static bool ath_reg_dyn_country_user_allow(struct ath_regulatory *reg)\n {\n+\tif (IS_ENABLED(CPTCFG_ATH_USER_REGD))\n+\t\treturn true;\n \tif (!IS_ENABLED(CPTCFG_ATH_REG_DYNAMIC_USER_REG_HINTS))\n \t\treturn false;\n \tif (!dynamic_country_user_possible(reg))\n@@ -345,6 +351,9 @@ ath_reg_apply_beaconing_flags(struct wip\n \tstruct ieee80211_channel *ch;\n \tunsigned int i;\n \n+\tif (IS_ENABLED(CPTCFG_ATH_USER_REGD))\n+\t\treturn;\n+\n \tfor (band = 0; band < NUM_NL80211_BANDS; band++) {\n \t\tif (!wiphy->bands[band])\n \t\t\tcontinue;\n@@ -379,6 +388,9 @@ ath_reg_apply_ir_flags(struct wiphy *wip\n {\n \tstruct ieee80211_supported_band *sband;\n \n+\tif (IS_ENABLED(CPTCFG_ATH_USER_REGD))\n+\t\treturn;\n+\n \tsband = wiphy->bands[NL80211_BAND_2GHZ];\n \tif (!sband)\n \t\treturn;\n@@ -408,6 +420,9 @@ static void ath_reg_apply_radar_flags(st\n \tstruct ieee80211_channel *ch;\n \tunsigned int i;\n \n+\tif (IS_ENABLED(CPTCFG_ATH_USER_REGD))\n+\t\treturn;\n+\n \tif (!wiphy->bands[NL80211_BAND_5GHZ])\n \t\treturn;\n \n@@ -640,6 +655,10 @@ ath_regd_init_wiphy(struct ath_regulator\n \tconst struct ieee80211_regdomain *regd;\n \n \twiphy->reg_notifier = reg_notifier;\n+\n+\tif (IS_ENABLED(CPTCFG_ATH_USER_REGD))\n+\t\treturn 0;\n+\n \twiphy->regulatory_flags |= REGULATORY_STRICT_REG |\n \t\t\t\t   REGULATORY_CUSTOM_REG;\n \n--- a/drivers/net/wireless/ath/Kconfig\n+++ b/drivers/net/wireless/ath/Kconfig\n@@ -24,6 +24,9 @@ config WLAN_VENDOR_ATH\n \n if WLAN_VENDOR_ATH\n \n+config ATH_USER_REGD\n+\tbool \"Do not enforce EEPROM regulatory restrictions\"\n+\n config ATH_DEBUG\n \tbool \"Atheros wireless debugging\"\n \thelp\n--- a/local-symbols\n+++ b/local-symbols\n@@ -83,6 +83,7 @@ ADM8211=\n ATH_COMMON=\n WLAN_VENDOR_ATH=\n ATH_DEBUG=\n+ATH_USER_REGD=\n ATH_TRACEPOINTS=\n ATH_REG_DYNAMIC_USER_REG_HINTS=\n ATH_REG_DYNAMIC_USER_CERT_TESTING=\n"
  },
  {
    "path": "package/kernel/mac80211/patches/ath/403-world_regd_fixup.patch",
    "content": "--- a/drivers/net/wireless/ath/regd.c\n+++ b/drivers/net/wireless/ath/regd.c\n@@ -44,7 +44,8 @@ static struct reg_dmn_pair_mapping *ath_\n \t\t\t\t\t NL80211_RRF_NO_OFDM)\n \n /* We allow IBSS on these on a case by case basis by regulatory domain */\n-#define ATH_5GHZ_5150_5350\tREG_RULE(5150-10, 5350+10, 80, 0, 30,\\\n+#define ATH_5GHZ_5150_5350\tREG_RULE(5150-10, 5240+10, 80, 0, 30, 0),\\\n+\t\t\t\tREG_RULE(5260-10, 5350+10, 80, 0, 30,\\\n \t\t\t\t\t NL80211_RRF_NO_IR)\n #define ATH_5GHZ_5470_5850\tREG_RULE(5470-10, 5850+10, 80, 0, 30,\\\n \t\t\t\t\t NL80211_RRF_NO_IR)\n@@ -62,57 +63,56 @@ static struct reg_dmn_pair_mapping *ath_\n #define ATH_5GHZ_NO_MIDBAND\tATH_5GHZ_5150_5350, \\\n \t\t\t\tATH_5GHZ_5725_5850\n \n+#define REGD_RULES(...) \\\n+\t.reg_rules = { __VA_ARGS__ }, \\\n+\t.n_reg_rules = ARRAY_SIZE(((struct ieee80211_reg_rule[]) { __VA_ARGS__ }))\n+\n /* Can be used for:\n  * 0x60, 0x61, 0x62 */\n static const struct ieee80211_regdomain ath_world_regdom_60_61_62 = {\n-\t.n_reg_rules = 5,\n \t.alpha2 =  \"99\",\n-\t.reg_rules = {\n+\tREGD_RULES(\n \t\tATH_2GHZ_ALL,\n \t\tATH_5GHZ_ALL,\n-\t}\n+\t)\n };\n \n /* Can be used by 0x63 and 0x65 */\n static const struct ieee80211_regdomain ath_world_regdom_63_65 = {\n-\t.n_reg_rules = 4,\n \t.alpha2 =  \"99\",\n-\t.reg_rules = {\n+\tREGD_RULES(\n \t\tATH_2GHZ_CH01_11,\n \t\tATH_2GHZ_CH12_13,\n \t\tATH_5GHZ_NO_MIDBAND,\n-\t}\n+\t)\n };\n \n /* Can be used by 0x64 only */\n static const struct ieee80211_regdomain ath_world_regdom_64 = {\n-\t.n_reg_rules = 3,\n \t.alpha2 =  \"99\",\n-\t.reg_rules = {\n+\tREGD_RULES(\n \t\tATH_2GHZ_CH01_11,\n \t\tATH_5GHZ_NO_MIDBAND,\n-\t}\n+\t)\n };\n \n /* Can be used by 0x66 and 0x69 */\n static const struct ieee80211_regdomain ath_world_regdom_66_69 = {\n-\t.n_reg_rules = 3,\n \t.alpha2 =  \"99\",\n-\t.reg_rules = {\n+\tREGD_RULES(\n \t\tATH_2GHZ_CH01_11,\n \t\tATH_5GHZ_ALL,\n-\t}\n+\t)\n };\n \n /* Can be used by 0x67, 0x68, 0x6A and 0x6C */\n static const struct ieee80211_regdomain ath_world_regdom_67_68_6A_6C = {\n-\t.n_reg_rules = 4,\n \t.alpha2 =  \"99\",\n-\t.reg_rules = {\n+\tREGD_RULES(\n \t\tATH_2GHZ_CH01_11,\n \t\tATH_2GHZ_CH12_13,\n \t\tATH_5GHZ_ALL,\n-\t}\n+\t)\n };\n \n static bool dynamic_country_user_possible(struct ath_regulatory *reg)\n"
  },
  {
    "path": "package/kernel/mac80211/patches/ath/404-regd_no_assoc_hints.patch",
    "content": "--- a/net/wireless/reg.c\n+++ b/net/wireless/reg.c\n@@ -3304,6 +3304,8 @@ void regulatory_hint_country_ie(struct w\n \tenum environment_cap env = ENVIRON_ANY;\n \tstruct regulatory_request *request = NULL, *lr;\n \n+\treturn;\n+\n \t/* IE len must be evenly divisible by 2 */\n \tif (country_ie_len & 0x01)\n \t\treturn;\n@@ -3555,6 +3557,7 @@ static bool is_wiphy_all_set_reg_flag(en\n \n void regulatory_hint_disconnect(void)\n {\n+\treturn;\n \t/* Restore of regulatory settings is not required when wiphy(s)\n \t * ignore IE from connected access point but clearance of beacon hints\n \t * is required when wiphy(s) supports beacon hints.\n"
  },
  {
    "path": "package/kernel/mac80211/patches/ath/405-ath_regd_us.patch",
    "content": "--- a/drivers/net/wireless/ath/regd_common.h\n+++ b/drivers/net/wireless/ath/regd_common.h\n@@ -32,6 +32,7 @@ enum EnumRd {\n \tFCC2_WORLD = 0x21,\n \tFCC2_ETSIC = 0x22,\n \tFCC6_WORLD = 0x23,\n+\tFCC3_FCCA_2 = 0x2A,\n \tFRANCE_RES = 0x31,\n \tFCC3_FCCA = 0x3A,\n \tFCC3_WORLD = 0x3B,\n@@ -172,6 +173,7 @@ static struct reg_dmn_pair_mapping regDo\n \t{FCC2_WORLD, CTL_FCC, CTL_ETSI},\n \t{FCC2_ETSIC, CTL_FCC, CTL_ETSI},\n \t{FCC3_FCCA, CTL_FCC, CTL_FCC},\n+\t{FCC3_FCCA_2, CTL_FCC, CTL_FCC},\n \t{FCC3_WORLD, CTL_FCC, CTL_ETSI},\n \t{FCC3_ETSIC, CTL_FCC, CTL_ETSI},\n \t{FCC4_FCCA, CTL_FCC, CTL_FCC},\n@@ -483,6 +485,7 @@ static struct country_code_to_enum_rd al\n \t{CTRY_UAE, NULL1_WORLD, \"AE\"},\n \t{CTRY_UNITED_KINGDOM, ETSI1_WORLD, \"GB\"},\n \t{CTRY_UNITED_STATES, FCC3_FCCA, \"US\"},\n+\t{CTRY_UNITED_STATES, FCC3_FCCA_2, \"US\"},\n \t{CTRY_UNITED_STATES2, FCC3_FCCA, \"US\"},\n \t{CTRY_UNITED_STATES3, FCC3_FCCA, \"US\"},\n \t/* This \"PS\" is for US public safety actually... to support this we\n"
  },
  {
    "path": "package/kernel/mac80211/patches/ath/406-ath_relax_default_regd.patch",
    "content": "--- a/drivers/net/wireless/ath/regd.c\n+++ b/drivers/net/wireless/ath/regd.c\n@@ -115,6 +115,16 @@ static const struct ieee80211_regdomain\n \t)\n };\n \n+static u16 ath_regd_get_eepromRD(struct ath_regulatory *reg)\n+{\n+\treturn reg->current_rd & ~WORLDWIDE_ROAMING_FLAG;\n+}\n+\n+static bool is_default_regd(struct ath_regulatory *reg)\n+{\n+\treturn ath_regd_get_eepromRD(reg) == CTRY_DEFAULT;\n+}\n+\n static bool dynamic_country_user_possible(struct ath_regulatory *reg)\n {\n \tif (IS_ENABLED(CPTCFG_ATH_USER_REGD))\n@@ -123,6 +133,9 @@ static bool dynamic_country_user_possibl\n \tif (IS_ENABLED(CPTCFG_ATH_REG_DYNAMIC_USER_CERT_TESTING))\n \t\treturn true;\n \n+\tif (is_default_regd(reg))\n+\t\treturn true;\n+\n \tswitch (reg->country_code) {\n \tcase CTRY_UNITED_STATES:\n \tcase CTRY_JAPAN1:\n@@ -208,11 +221,6 @@ static inline bool is_wwr_sku(u16 regd)\n \t\t(regd == WORLD));\n }\n \n-static u16 ath_regd_get_eepromRD(struct ath_regulatory *reg)\n-{\n-\treturn reg->current_rd & ~WORLDWIDE_ROAMING_FLAG;\n-}\n-\n bool ath_is_world_regd(struct ath_regulatory *reg)\n {\n \treturn is_wwr_sku(ath_regd_get_eepromRD(reg));\n@@ -659,6 +667,9 @@ ath_regd_init_wiphy(struct ath_regulator\n \tif (IS_ENABLED(CPTCFG_ATH_USER_REGD))\n \t\treturn 0;\n \n+\tif (is_default_regd(reg))\n+\t\treturn 0;\n+\n \twiphy->regulatory_flags |= REGULATORY_STRICT_REG |\n \t\t\t\t   REGULATORY_CUSTOM_REG;\n \n"
  },
  {
    "path": "package/kernel/mac80211/patches/ath/431-add_platform_eeprom_support_to_ath5k.patch",
    "content": "--- a/drivers/net/wireless/ath/ath5k/pci.c\n+++ b/drivers/net/wireless/ath/ath5k/pci.c\n@@ -20,6 +20,7 @@\n #include <linux/pci.h>\n #include <linux/etherdevice.h>\n #include <linux/module.h>\n+#include <linux/ath5k_platform.h>\n #include \"../ath.h\"\n #include \"ath5k.h\"\n #include \"debug.h\"\n@@ -71,7 +72,7 @@ static void ath5k_pci_read_cachesize(str\n }\n \n /*\n- * Read from eeprom\n+ * Read from eeprom or platform_data\n  */\n static bool\n ath5k_pci_eeprom_read(struct ath_common *common, u32 offset, u16 *data)\n@@ -79,6 +80,19 @@ ath5k_pci_eeprom_read(struct ath_common\n \tstruct ath5k_hw *ah = (struct ath5k_hw *) common->ah;\n \tu32 status, timeout;\n \n+\tstruct ath5k_platform_data *pdata = NULL;\n+\n+\tif (ah->pdev)\n+\t\tpdata = ah->pdev->dev.platform_data;\n+\n+\tif (pdata && pdata->eeprom_data && pdata->eeprom_data[61] == AR5K_EEPROM_MAGIC_VALUE) {\n+\t\tif (offset >= ATH5K_PLAT_EEP_MAX_WORDS)\n+\t\t\treturn false;\n+\n+\t\t*data = pdata->eeprom_data[offset];\n+\t\treturn true;\n+\t}\n+\n \t/*\n \t * Initialize EEPROM access\n \t */\n@@ -122,6 +136,16 @@ static int ath5k_pci_eeprom_read_mac(str\n \tu16 data;\n \tint octet;\n \n+\tstruct ath5k_platform_data *pdata = NULL;\n+\n+\tif (ah->pdev)\n+\t\tpdata = ah->pdev->dev.platform_data;\n+\n+\tif (pdata && pdata->macaddr) {\n+\t\tmemcpy(mac, pdata->macaddr, ETH_ALEN);\n+\t\treturn 0;\n+\t}\n+\n \tAR5K_EEPROM_READ(0x20, data);\n \n \tfor (offset = 0x1f, octet = 0, total = 0; offset >= 0x1d; offset--) {\n"
  },
  {
    "path": "package/kernel/mac80211/patches/ath10k/080-ath10k_thermal_config.patch",
    "content": "--- a/drivers/net/wireless/ath/ath10k/Kconfig\n+++ b/drivers/net/wireless/ath/ath10k/Kconfig\n@@ -86,6 +86,12 @@ config ATH10K_TRACING\n \thelp\n \t  Select this to ath10k use tracing infrastructure.\n \n+config ATH10K_THERMAL\n+\tbool \"Atheros ath10k thermal monitoring support\"\n+\tdepends on THERMAL\n+\t---help---\n+\t  Select this to ath10k use hwmon for thermal measurement.\n+\n config ATH10K_DFS_CERTIFIED\n \tbool \"Atheros DFS support for certified platforms\"\n \tdepends on ATH10K && CFG80211_CERTIFICATION_ONUS\n--- a/drivers/net/wireless/ath/ath10k/Makefile\n+++ b/drivers/net/wireless/ath/ath10k/Makefile\n@@ -18,7 +18,7 @@ ath10k_core-y += mac.o \\\n ath10k_core-$(CPTCFG_ATH10K_SPECTRAL) += spectral.o\n ath10k_core-$(CPTCFG_NL80211_TESTMODE) += testmode.o\n ath10k_core-$(CPTCFG_ATH10K_TRACING) += trace.o\n-ath10k_core-$(CONFIG_THERMAL) += thermal.o\n+ath10k_core-$(CPTCFG_ATH10K_THERMAL) += thermal.o\n ath10k_core-$(CPTCFG_MAC80211_DEBUGFS) += debugfs_sta.o\n ath10k_core-$(CONFIG_PM) += wow.o\n ath10k_core-$(CONFIG_DEV_COREDUMP) += coredump.o\n--- a/drivers/net/wireless/ath/ath10k/thermal.h\n+++ b/drivers/net/wireless/ath/ath10k/thermal.h\n@@ -25,7 +25,7 @@ struct ath10k_thermal {\n \tint temperature;\n };\n \n-#if IS_REACHABLE(CONFIG_THERMAL)\n+#if IS_REACHABLE(CPTCFG_ATH10K_THERMAL)\n int ath10k_thermal_register(struct ath10k *ar);\n void ath10k_thermal_unregister(struct ath10k *ar);\n void ath10k_thermal_event_temperature(struct ath10k *ar, int temperature);\n--- a/local-symbols\n+++ b/local-symbols\n@@ -142,6 +142,7 @@ ATH10K_SNOC=\n ATH10K_DEBUG=\n ATH10K_DEBUGFS=\n ATH10K_SPECTRAL=\n+ATH10K_THERMAL=\n ATH10K_TRACING=\n ATH10K_DFS_CERTIFIED=\n WCN36XX=\n"
  },
  {
    "path": "package/kernel/mac80211/patches/ath10k/120-ath10k-fetch-calibration-data-via-nvmem-subsystem.patch",
    "content": "From e2333703373e8b81294da5d1c73c30154f75b082 Mon Sep 17 00:00:00 2001\nFrom: Christian Lamparter <chunkeey@gmail.com>\nDate: Fri, 15 Oct 2021 18:56:33 +0200\nSubject: [PATCH] ath10k: fetch (pre-)calibration data via nvmem subsystem\n\nOn most embedded ath10k devices (like range extenders,\nrouters, accesspoints, ...) the calibration data is\nstored in a easily accessible MTD partitions named\n\"ART\", \"caldata\", \"calibration\", etc...\n\nSince commit 4b361cfa8624 (\"mtd: core: add OTP nvmem provider support\"):\nMTD partitions and portions of them can be specified\nas potential nvmem-cells which are accessible through\nthe nvmem subsystem.\n\nThis feature - together with an nvmem cell definition either\nin the platform data or via device-tree allows drivers to get\nthe (pre-)calibration data which is required for initializing\nthe WIFI.\n\nTested with Netgear EX6150v2 (IPQ4018)\n\nCc: Robert Marko <robimarko@gmail.com>\nCc: Thibaut Varene <hacks@slashdirt.org>\nSigned-off-by: Christian Lamparter <chunkeey@gmail.com>\n---\n--- a/drivers/net/wireless/ath/ath10k/core.c\n+++ b/drivers/net/wireless/ath/ath10k/core.c\n@@ -12,6 +12,7 @@\n #include <linux/dmi.h>\n #include <linux/ctype.h>\n #include <linux/pm_qos.h>\n+#include <linux/nvmem-consumer.h>\n #include <asm/byteorder.h>\n \n #include \"core.h\"\n@@ -952,7 +953,8 @@ static int ath10k_core_get_board_id_from\n \t}\n \n \tif (ar->cal_mode == ATH10K_PRE_CAL_MODE_DT ||\n-\t    ar->cal_mode == ATH10K_PRE_CAL_MODE_FILE)\n+\t    ar->cal_mode == ATH10K_PRE_CAL_MODE_FILE ||\n+\t    ar->cal_mode == ATH10K_PRE_CAL_MODE_NVMEM)\n \t\tbmi_board_id_param = BMI_PARAM_GET_FLASH_BOARD_ID;\n \telse\n \t\tbmi_board_id_param = BMI_PARAM_GET_EEPROM_BOARD_ID;\n@@ -1743,7 +1745,8 @@ static int ath10k_download_and_run_otp(s\n \n \t/* As of now pre-cal is valid for 10_4 variants */\n \tif (ar->cal_mode == ATH10K_PRE_CAL_MODE_DT ||\n-\t    ar->cal_mode == ATH10K_PRE_CAL_MODE_FILE)\n+\t    ar->cal_mode == ATH10K_PRE_CAL_MODE_FILE ||\n+\t    ar->cal_mode == ATH10K_PRE_CAL_MODE_NVMEM)\n \t\tbmi_otp_exe_param = BMI_PARAM_FLASH_SECTION_ALL;\n \n \tret = ath10k_bmi_execute(ar, address, bmi_otp_exe_param, &result);\n@@ -1870,6 +1873,39 @@ out_free:\n \treturn ret;\n }\n \n+static int ath10k_download_cal_nvmem(struct ath10k *ar, const char *cell_name)\n+{\n+\tstruct nvmem_cell *cell;\n+\tvoid *buf;\n+\tsize_t len;\n+\tint ret;\n+\n+\tcell = devm_nvmem_cell_get(ar->dev, cell_name);\n+\tif (IS_ERR(cell)) {\n+\t\tret = PTR_ERR(cell);\n+\t\treturn ret;\n+\t}\n+\n+\tbuf = nvmem_cell_read(cell, &len);\n+\tif (IS_ERR(buf))\n+\t\treturn PTR_ERR(buf);\n+\n+\tif (ar->hw_params.cal_data_len != len) {\n+\t\tkfree(buf);\n+\t\tath10k_warn(ar, \"invalid calibration data length in nvmem-cell '%s': %zu != %u\\n\",\n+\t\t\t    cell_name, len, ar->hw_params.cal_data_len);\n+\t\treturn -EMSGSIZE;\n+\t}\n+\n+\tret = ath10k_download_board_data(ar, buf, len);\n+\tkfree(buf);\n+\tif (ret)\n+\t\tath10k_warn(ar, \"failed to download calibration data from nvmem-cell '%s': %d\\n\",\n+\t\t\t    cell_name, ret);\n+\n+\treturn ret;\n+}\n+\n int ath10k_core_fetch_firmware_api_n(struct ath10k *ar, const char *name,\n \t\t\t\t     struct ath10k_fw_file *fw_file)\n {\n@@ -2104,6 +2140,18 @@ static int ath10k_core_pre_cal_download(\n {\n \tint ret;\n \n+\tret = ath10k_download_cal_nvmem(ar, \"pre-calibration\");\n+\tif (ret == 0) {\n+\t\tar->cal_mode = ATH10K_PRE_CAL_MODE_NVMEM;\n+\t\tgoto success;\n+\t} else if (ret == -EPROBE_DEFER) {\n+\t\treturn ret;\n+\t}\n+\n+\tath10k_dbg(ar, ATH10K_DBG_BOOT,\n+\t\t   \"boot did not find a pre-calibration nvmem-cell, try file next: %d\\n\",\n+\t\t   ret);\n+\n \tret = ath10k_download_cal_file(ar, ar->pre_cal_file);\n \tif (ret == 0) {\n \t\tar->cal_mode = ATH10K_PRE_CAL_MODE_FILE;\n@@ -2170,6 +2218,18 @@ static int ath10k_download_cal_data(stru\n \t\t   \"pre cal download procedure failed, try cal file: %d\\n\",\n \t\t   ret);\n \n+\tret = ath10k_download_cal_nvmem(ar, \"calibration\");\n+\tif (ret == 0) {\n+\t\tar->cal_mode = ATH10K_CAL_MODE_NVMEM;\n+\t\tgoto done;\n+\t} else if (ret == -EPROBE_DEFER) {\n+\t\treturn ret;\n+\t}\n+\n+\tath10k_dbg(ar, ATH10K_DBG_BOOT,\n+\t\t   \"boot did not find a calibration nvmem-cell, try file next: %d\\n\",\n+\t\t   ret);\n+\n \tret = ath10k_download_cal_file(ar, ar->cal_file);\n \tif (ret == 0) {\n \t\tar->cal_mode = ATH10K_CAL_MODE_FILE;\n--- a/drivers/net/wireless/ath/ath10k/core.h\n+++ b/drivers/net/wireless/ath/ath10k/core.h\n@@ -877,8 +877,10 @@ enum ath10k_cal_mode {\n \tATH10K_CAL_MODE_FILE,\n \tATH10K_CAL_MODE_OTP,\n \tATH10K_CAL_MODE_DT,\n+\tATH10K_CAL_MODE_NVMEM,\n \tATH10K_PRE_CAL_MODE_FILE,\n \tATH10K_PRE_CAL_MODE_DT,\n+\tATH10K_PRE_CAL_MODE_NVMEM,\n \tATH10K_CAL_MODE_EEPROM,\n };\n \n@@ -898,10 +900,14 @@ static inline const char *ath10k_cal_mod\n \t\treturn \"otp\";\n \tcase ATH10K_CAL_MODE_DT:\n \t\treturn \"dt\";\n+\tcase ATH10K_CAL_MODE_NVMEM:\n+\t\treturn \"nvmem\";\n \tcase ATH10K_PRE_CAL_MODE_FILE:\n \t\treturn \"pre-cal-file\";\n \tcase ATH10K_PRE_CAL_MODE_DT:\n \t\treturn \"pre-cal-dt\";\n+\tcase ATH10K_PRE_CAL_MODE_NVMEM:\n+\t\treturn \"pre-cal-nvmem\";\n \tcase ATH10K_CAL_MODE_EEPROM:\n \t\treturn \"eeprom\";\n \t}\n"
  },
  {
    "path": "package/kernel/mac80211/patches/ath10k/921-ath10k_init_devices_synchronously.patch",
    "content": "From: Sven Eckelmann <sven@open-mesh.com>\nDate: Tue, 18 Nov 2014 12:29:28 +0100\nSubject: [PATCH] ath10k: Don't initialize devices asynchronously\n\nOpenWrt requires all PHYs to be initialized to create the configuration files\nduring bootup. ath10k violates this because it delays the creation of the PHY\nto a not well defined point in the future.\n\nForcing the work to be done immediately works around this problem but may also\ndelay the boot when firmware images cannot be found.\n\nSigned-off-by: Sven Eckelmann <sven@open-mesh.com>\n---\n\n--- a/drivers/net/wireless/ath/ath10k/core.c\n+++ b/drivers/net/wireless/ath/ath10k/core.c\n@@ -3429,6 +3429,16 @@ int ath10k_core_register(struct ath10k *\n \n \tqueue_work(ar->workqueue, &ar->register_work);\n \n+\t/* OpenWrt requires all PHYs to be initialized to create the\n+\t * configuration files during bootup. ath10k violates this\n+\t * because it delays the creation of the PHY to a not well defined\n+\t * point in the future.\n+\t *\n+\t * Forcing the work to be done immediately works around this problem\n+\t * but may also delay the boot when firmware images cannot be found.\n+\t */\n+\tflush_workqueue(ar->workqueue);\n+\n \treturn 0;\n }\n EXPORT_SYMBOL(ath10k_core_register);\n"
  },
  {
    "path": "package/kernel/mac80211/patches/ath10k/930-ath10k_add_tpt_led_trigger.patch",
    "content": "--- a/drivers/net/wireless/ath/ath10k/mac.c\n+++ b/drivers/net/wireless/ath/ath10k/mac.c\n@@ -9843,6 +9843,21 @@ static int ath10k_mac_init_rd(struct ath\n \treturn 0;\n }\n \n+#ifdef CPTCFG_MAC80211_LEDS\n+static const struct ieee80211_tpt_blink ath10k_tpt_blink[] = {\n+\t{ .throughput = 0 * 1024, .blink_time = 334 },\n+\t{ .throughput = 1 * 1024, .blink_time = 260 },\n+\t{ .throughput = 2 * 1024, .blink_time = 220 },\n+\t{ .throughput = 5 * 1024, .blink_time = 190 },\n+\t{ .throughput = 10 * 1024, .blink_time = 170 },\n+\t{ .throughput = 25 * 1024, .blink_time = 150 },\n+\t{ .throughput = 54 * 1024, .blink_time = 130 },\n+\t{ .throughput = 120 * 1024, .blink_time = 110 },\n+\t{ .throughput = 265 * 1024, .blink_time = 80 },\n+\t{ .throughput = 586 * 1024, .blink_time = 50 },\n+};\n+#endif\n+\n int ath10k_mac_register(struct ath10k *ar)\n {\n \tstatic const u32 cipher_suites[] = {\n@@ -10195,6 +10210,12 @@ int ath10k_mac_register(struct ath10k *a\n \n \tar->hw->weight_multiplier = ATH10K_AIRTIME_WEIGHT_MULTIPLIER;\n \n+#ifdef CPTCFG_MAC80211_LEDS\n+\tieee80211_create_tpt_led_trigger(ar->hw,\n+\t\tIEEE80211_TPT_LEDTRIG_FL_RADIO, ath10k_tpt_blink,\n+\t\tARRAY_SIZE(ath10k_tpt_blink));\n+#endif\n+\n \tret = ieee80211_register_hw(ar->hw);\n \tif (ret) {\n \t\tath10k_err(ar, \"failed to register ieee80211: %d\\n\", ret);\n"
  },
  {
    "path": "package/kernel/mac80211/patches/ath10k/974-ath10k_add-LED-and-GPIO-controlling-support-for-various-chipsets.patch",
    "content": "From: Sebastian Gottschall <s.gottschall@newmedia-net.de>\n\nAdds LED and GPIO Control support for 988x, 9887, 9888, 99x0, 9984 based\nchipsets with on chipset connected led's using WMI Firmware API.  The LED\ndevice will get available named as \"ath10k-phyX\" at sysfs and can be controlled\nwith various triggers.  adds also debugfs interface for gpio control.\n\nThis patch is specific for OpenWRt base, as is use old backported package\nwith old wireless source. Support for QCA9984 is removed and a simbol\nis added to local-simbol file to export the actually compile the code \nwith the ATH10K_LEDS simbol.\n\n\nSigned-off-by: Sebastian Gottschall <s.gottschall@dd-wrt.com>\nReviewed-by: Steve deRosier <derosier@cal-sierra.com>\n[kvalo: major reorg and cleanup]\nSigned-off-by: Kalle Valo <kvalo@codeaurora.org>\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\n---\n\nv13:\n\n* only compile tested!\n\n* fix all checkpatch warnings\n\n* fix commit log\n\n* sizeof(struct ath10k_gpiocontrol) -> sizeof(*gpio)\n\n* unsigned -> unsigned int\n\n* remove GPIOLIB code, that should be added in a separate patch\n\n* rename gpio.c to leds.c\n\n* add leds.h\n\n* rename some functions:\n\n  ath10k_attach_led() -> ath10k_leds_register()\n  ath10k_unregister_led() -> ath10k_leds_unregister()\n  ath10k_reset_led_pin() -> ath10k_leds_start()\n\n* call ath10k_leds_unregister() before ath10k_thermal_unregister() to preserve ordering\n\n* call ath10k_leds_start() only from ath10k_core_start() and not from mac.c\n\n* rename struct ath10k_gpiocontrol as anonymous function under struct\n  ath10k::leds, no need for memory allocation\n\n* merge ath10k_add_led() to ath10k_attach_led(), which is it's only caller\n\n* remove #if IS_ENABLED() checks from most of places, memory savings from those were not worth it\n\n* Kconfig help text improvement and move it lower in the menu, also don't enable it by default\n\n* switch to set_brightness_blocking() so that the callback can sleep,\n  then no need to use ath10k_wmi_cmd_send_nowait() and can take mutex\n  to access ar->state\n\n* don't touch ath10k_wmi_pdev_get_temperature()\n\n* as QCA6174/QCA9377 are not (yet) supported don't add the command to WMI-TLV interface\n\n* remove debugfs interface, that should be added in another patch\n\n* cleanup includes\n\n\n drivers/net/wireless/ath/ath10k/Kconfig   |  10 +++\n drivers/net/wireless/ath/ath10k/Makefile  |   1 +\n drivers/net/wireless/ath/ath10k/core.c    |  22 +++++++\n drivers/net/wireless/ath/ath10k/core.h    |   9 ++-\n drivers/net/wireless/ath/ath10k/hw.h      |   1 +\n drivers/net/wireless/ath/ath10k/leds.c    | 103 ++++++++++++++++++++++++++++++\n drivers/net/wireless/ath/ath10k/leds.h    |  45 +++++++++++++\n drivers/net/wireless/ath/ath10k/mac.c     |   1 +\n drivers/net/wireless/ath/ath10k/wmi-ops.h |  32 ++++++++++\n drivers/net/wireless/ath/ath10k/wmi-tlv.c |   2 +\n drivers/net/wireless/ath/ath10k/wmi.c     |  54 ++++++++++++++++\n drivers/net/wireless/ath/ath10k/wmi.h     |  35 ++++++++++\n 12 files changed, 314 insertions(+), 1 deletion(-)\n create mode 100644 drivers/net/wireless/ath/ath10k/leds.c\n create mode 100644 drivers/net/wireless/ath/ath10k/leds.h\n--- a/drivers/net/wireless/ath/ath10k/Kconfig\n+++ b/drivers/net/wireless/ath/ath10k/Kconfig\n@@ -71,6 +71,16 @@ config ATH10K_DEBUGFS\n \n \t  If unsure, say Y to make it easier to debug problems.\n \n+config ATH10K_LEDS\n+\tbool \"Atheros ath10k LED support\"\n+\tdepends on ATH10K\n+\tselect MAC80211_LEDS\n+\tselect LEDS_CLASS\n+\tselect NEW_LEDS\n+\tdefault y\n+\t---help---\n+\t  This option is necessary, if you want LED support for chipset connected led pins. If unsure, say N.\n+\n config ATH10K_SPECTRAL\n \tbool \"Atheros ath10k spectral scan support\"\n \tdepends on ATH10K_DEBUGFS\n--- a/drivers/net/wireless/ath/ath10k/Makefile\n+++ b/drivers/net/wireless/ath/ath10k/Makefile\n@@ -19,6 +19,7 @@ ath10k_core-$(CPTCFG_ATH10K_SPECTRAL) +=\n ath10k_core-$(CPTCFG_NL80211_TESTMODE) += testmode.o\n ath10k_core-$(CPTCFG_ATH10K_TRACING) += trace.o\n ath10k_core-$(CPTCFG_ATH10K_THERMAL) += thermal.o\n+ath10k_core-$(CPTCFG_ATH10K_LEDS) += leds.o\n ath10k_core-$(CPTCFG_MAC80211_DEBUGFS) += debugfs_sta.o\n ath10k_core-$(CONFIG_PM) += wow.o\n ath10k_core-$(CONFIG_DEV_COREDUMP) += coredump.o\n--- a/local-symbols\n+++ b/local-symbols\n@@ -143,6 +143,7 @@ ATH10K_DEBUG=\n ATH10K_DEBUGFS=\n ATH10K_SPECTRAL=\n ATH10K_THERMAL=\n+ATH10K_LEDS=\n ATH10K_TRACING=\n ATH10K_DFS_CERTIFIED=\n WCN36XX=\n--- a/drivers/net/wireless/ath/ath10k/core.c\n+++ b/drivers/net/wireless/ath/ath10k/core.c\n@@ -26,6 +26,7 @@\n #include \"testmode.h\"\n #include \"wmi-ops.h\"\n #include \"coredump.h\"\n+#include \"leds.h\"\n \n unsigned int ath10k_debug_mask;\n EXPORT_SYMBOL(ath10k_debug_mask);\n@@ -62,6 +63,7 @@ static const struct ath10k_hw_params ath\n \t\t.dev_id = QCA988X_2_0_DEVICE_ID,\n \t\t.bus = ATH10K_BUS_PCI,\n \t\t.name = \"qca988x hw2.0\",\n+\t\t.led_pin = 1,\n \t\t.patch_load_addr = QCA988X_HW_2_0_PATCH_LOAD_ADDR,\n \t\t.uart_pin = 7,\n \t\t.cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_ALL,\n@@ -135,6 +137,7 @@ static const struct ath10k_hw_params ath\n \t\t.dev_id = QCA9887_1_0_DEVICE_ID,\n \t\t.bus = ATH10K_BUS_PCI,\n \t\t.name = \"qca9887 hw1.0\",\n+\t\t.led_pin = 1,\n \t\t.patch_load_addr = QCA9887_HW_1_0_PATCH_LOAD_ADDR,\n \t\t.uart_pin = 7,\n \t\t.cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_ALL,\n@@ -352,6 +355,7 @@ static const struct ath10k_hw_params ath\n \t\t.dev_id = QCA99X0_2_0_DEVICE_ID,\n \t\t.bus = ATH10K_BUS_PCI,\n \t\t.name = \"qca99x0 hw2.0\",\n+\t\t.led_pin = 17,\n \t\t.patch_load_addr = QCA99X0_HW_2_0_PATCH_LOAD_ADDR,\n \t\t.uart_pin = 7,\n \t\t.otp_exe_param = 0x00000700,\n@@ -394,6 +398,7 @@ static const struct ath10k_hw_params ath\n \t\t.dev_id = QCA9984_1_0_DEVICE_ID,\n \t\t.bus = ATH10K_BUS_PCI,\n \t\t.name = \"qca9984/qca9994 hw1.0\",\n+\t\t.led_pin = 17,\n \t\t.patch_load_addr = QCA9984_HW_1_0_PATCH_LOAD_ADDR,\n \t\t.uart_pin = 7,\n \t\t.cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_EACH,\n@@ -443,6 +448,7 @@ static const struct ath10k_hw_params ath\n \t\t.dev_id = QCA9888_2_0_DEVICE_ID,\n \t\t.bus = ATH10K_BUS_PCI,\n \t\t.name = \"qca9888 hw2.0\",\n+\t\t.led_pin = 17,\n \t\t.patch_load_addr = QCA9888_HW_2_0_PATCH_LOAD_ADDR,\n \t\t.uart_pin = 7,\n \t\t.cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_EACH,\n@@ -3144,6 +3150,10 @@ int ath10k_core_start(struct ath10k *ar,\n \t\tgoto err_hif_stop;\n \t}\n \n+\tstatus = ath10k_leds_start(ar);\n+\tif (status)\n+\t\tgoto err_hif_stop;\n+\n \treturn 0;\n \n err_hif_stop:\n@@ -3402,9 +3412,18 @@ static void ath10k_core_register_work(st\n \t\tgoto err_spectral_destroy;\n \t}\n \n+\tstatus = ath10k_leds_register(ar);\n+\tif (status) {\n+\t\tath10k_err(ar, \"could not register leds: %d\\n\",\n+\t\t\t   status);\n+\t\tgoto err_thermal_unregister;\n+\t}\n+\n \tset_bit(ATH10K_FLAG_CORE_REGISTERED, &ar->dev_flags);\n \treturn;\n \n+err_thermal_unregister:\n+\tath10k_thermal_unregister(ar);\n err_spectral_destroy:\n \tath10k_spectral_destroy(ar);\n err_debug_destroy:\n@@ -3450,6 +3469,8 @@ void ath10k_core_unregister(struct ath10\n \tif (!test_bit(ATH10K_FLAG_CORE_REGISTERED, &ar->dev_flags))\n \t\treturn;\n \n+\tath10k_leds_unregister(ar);\n+\n \tath10k_thermal_unregister(ar);\n \t/* Stop spectral before unregistering from mac80211 to remove the\n \t * relayfs debugfs file cleanly. Otherwise the parent debugfs tree\n--- a/drivers/net/wireless/ath/ath10k/core.h\n+++ b/drivers/net/wireless/ath/ath10k/core.h\n@@ -14,6 +14,7 @@\n #include <linux/pci.h>\n #include <linux/uuid.h>\n #include <linux/time.h>\n+#include <linux/leds.h>\n \n #include \"htt.h\"\n #include \"htc.h\"\n@@ -1256,6 +1257,13 @@ struct ath10k {\n \t} testmode;\n \n \tstruct {\n+\t\tstruct gpio_led wifi_led;\n+\t\tstruct led_classdev cdev;\n+\t\tchar label[48];\n+\t\tu32 gpio_state_pin;\n+\t} leds;\n+\n+\tstruct {\n \t\t/* protected by data_lock */\n \t\tu32 rx_crc_err_drop;\n \t\tu32 fw_crash_counter;\n--- a/drivers/net/wireless/ath/ath10k/hw.h\n+++ b/drivers/net/wireless/ath/ath10k/hw.h\n@@ -517,6 +517,7 @@ struct ath10k_hw_params {\n \tconst char *name;\n \tu32 patch_load_addr;\n \tint uart_pin;\n+\tint led_pin;\n \tu32 otp_exe_param;\n \n \t/* Type of hw cycle counter wraparound logic, for more info\n--- /dev/null\n+++ b/drivers/net/wireless/ath/ath10k/leds.c\n@@ -0,0 +1,103 @@\n+/*\n+ * Copyright (c) 2005-2011 Atheros Communications Inc.\n+ * Copyright (c) 2011-2017 Qualcomm Atheros, Inc.\n+ * Copyright (c) 2018 Sebastian Gottschall <s.gottschall@dd-wrt.com>\n+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.\n+ *\n+ * Permission to use, copy, modify, and/or distribute this software for any\n+ * purpose with or without fee is hereby granted, provided that the above\n+ * copyright notice and this permission notice appear in all copies.\n+ *\n+ * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n+ */\n+\n+#include <linux/leds.h>\n+\n+#include \"core.h\"\n+#include \"wmi.h\"\n+#include \"wmi-ops.h\"\n+\n+#include \"leds.h\"\n+\n+static int ath10k_leds_set_brightness_blocking(struct led_classdev *led_cdev,\n+\t\t\t\t\t       enum led_brightness brightness)\n+{\n+\tstruct ath10k *ar = container_of(led_cdev, struct ath10k,\n+\t\t\t\t\t leds.cdev);\n+\tstruct gpio_led *led = &ar->leds.wifi_led;\n+\n+\tmutex_lock(&ar->conf_mutex);\n+\n+\tif (ar->state != ATH10K_STATE_ON)\n+\t\tgoto out;\n+\n+\tar->leds.gpio_state_pin = (brightness != LED_OFF) ^ led->active_low;\n+\tath10k_wmi_gpio_output(ar, led->gpio, ar->leds.gpio_state_pin);\n+\n+out:\n+\tmutex_unlock(&ar->conf_mutex);\n+\n+\treturn 0;\n+}\n+\n+int ath10k_leds_start(struct ath10k *ar)\n+{\n+\tif (ar->hw_params.led_pin == 0)\n+\t\t/* leds not supported */\n+\t\treturn 0;\n+\n+\t/* under some circumstances, the gpio pin gets reconfigured\n+\t * to default state by the firmware, so we need to\n+\t * reconfigure it this behaviour has only ben seen on\n+\t * QCA9984 and QCA99XX devices so far\n+\t */\n+\tath10k_wmi_gpio_config(ar, ar->hw_params.led_pin, 0,\n+\t\t\t       WMI_GPIO_PULL_NONE, WMI_GPIO_INTTYPE_DISABLE);\n+\tath10k_wmi_gpio_output(ar, ar->hw_params.led_pin, 1);\n+\n+\treturn 0;\n+}\n+\n+int ath10k_leds_register(struct ath10k *ar)\n+{\n+\tint ret;\n+\n+\tif (ar->hw_params.led_pin == 0)\n+\t\t/* leds not supported */\n+\t\treturn 0;\n+\n+\tsnprintf(ar->leds.label, sizeof(ar->leds.label), \"ath10k-%s\",\n+\t\t wiphy_name(ar->hw->wiphy));\n+\tar->leds.wifi_led.active_low = 1;\n+\tar->leds.wifi_led.gpio = ar->hw_params.led_pin;\n+\tar->leds.wifi_led.name = ar->leds.label;\n+\tar->leds.wifi_led.default_state = LEDS_GPIO_DEFSTATE_KEEP;\n+\n+\tar->leds.cdev.name = ar->leds.label;\n+\tar->leds.cdev.brightness_set_blocking = ath10k_leds_set_brightness_blocking;\n+\n+\t/* FIXME: this assignment doesn't make sense as it's NULL, remove it? */\n+\tar->leds.cdev.default_trigger = ar->leds.wifi_led.default_trigger;\n+\n+\tret = led_classdev_register(wiphy_dev(ar->hw->wiphy), &ar->leds.cdev);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\treturn 0;\n+}\n+\n+void ath10k_leds_unregister(struct ath10k *ar)\n+{\n+\tif (ar->hw_params.led_pin == 0)\n+\t\t/* leds not supported */\n+\t\treturn;\n+\n+\tled_classdev_unregister(&ar->leds.cdev);\n+}\n+\n--- /dev/null\n+++ b/drivers/net/wireless/ath/ath10k/leds.h\n@@ -0,0 +1,41 @@\n+/*\n+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.\n+ *\n+ * Permission to use, copy, modify, and/or distribute this software for any\n+ * purpose with or without fee is hereby granted, provided that the above\n+ * copyright notice and this permission notice appear in all copies.\n+ *\n+ * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n+ */\n+#ifndef _LEDS_H_\n+#define _LEDS_H_\n+\n+#include \"core.h\"\n+\n+#ifdef CPTCFG_ATH10K_LEDS\n+void ath10k_leds_unregister(struct ath10k *ar);\n+int ath10k_leds_start(struct ath10k *ar);\n+int ath10k_leds_register(struct ath10k *ar);\n+#else\n+static inline void ath10k_leds_unregister(struct ath10k *ar)\n+{\n+}\n+\n+static inline int ath10k_leds_start(struct ath10k *ar)\n+{\n+\treturn 0;\n+}\n+\n+static inline int ath10k_leds_register(struct ath10k *ar)\n+{\n+\treturn 0;\n+}\n+\n+#endif\n+#endif /* _LEDS_H_ */\n--- a/drivers/net/wireless/ath/ath10k/mac.c\n+++ b/drivers/net/wireless/ath/ath10k/mac.c\n@@ -24,6 +24,7 @@\n #include \"wmi-tlv.h\"\n #include \"wmi-ops.h\"\n #include \"wow.h\"\n+#include \"leds.h\"\n \n /*********/\n /* Rates */\n--- a/drivers/net/wireless/ath/ath10k/wmi-ops.h\n+++ b/drivers/net/wireless/ath/ath10k/wmi-ops.h\n@@ -226,7 +226,10 @@ struct wmi_ops {\n \t\t\t const struct wmi_bb_timing_cfg_arg *arg);\n \tstruct sk_buff *(*gen_per_peer_per_tid_cfg)(struct ath10k *ar,\n \t\t\t\t\t\t    const struct wmi_per_peer_per_tid_cfg_arg *arg);\n+\tstruct sk_buff *(*gen_gpio_config)(struct ath10k *ar, u32 gpio_num,\n+\t\t\t\t\t   u32 input, u32 pull_type, u32 intr_mode);\n \n+\tstruct sk_buff *(*gen_gpio_output)(struct ath10k *ar, u32 gpio_num, u32 set);\n };\n \n int ath10k_wmi_cmd_send(struct ath10k *ar, struct sk_buff *skb, u32 cmd_id);\n@@ -1122,6 +1125,35 @@ ath10k_wmi_force_fw_hang(struct ath10k *\n \treturn ath10k_wmi_cmd_send(ar, skb, ar->wmi.cmd->force_fw_hang_cmdid);\n }\n \n+static inline int ath10k_wmi_gpio_config(struct ath10k *ar, u32 gpio_num,\n+\t\t\t\t\t u32 input, u32 pull_type, u32 intr_mode)\n+{\n+\tstruct sk_buff *skb;\n+\n+\tif (!ar->wmi.ops->gen_gpio_config)\n+\t\treturn -EOPNOTSUPP;\n+\n+\tskb = ar->wmi.ops->gen_gpio_config(ar, gpio_num, input, pull_type, intr_mode);\n+\tif (IS_ERR(skb))\n+\t\treturn PTR_ERR(skb);\n+\n+\treturn ath10k_wmi_cmd_send(ar, skb, ar->wmi.cmd->gpio_config_cmdid);\n+}\n+\n+static inline int ath10k_wmi_gpio_output(struct ath10k *ar, u32 gpio_num, u32 set)\n+{\n+\tstruct sk_buff *skb;\n+\n+\tif (!ar->wmi.ops->gen_gpio_config)\n+\t\treturn -EOPNOTSUPP;\n+\n+\tskb = ar->wmi.ops->gen_gpio_output(ar, gpio_num, set);\n+\tif (IS_ERR(skb))\n+\t\treturn PTR_ERR(skb);\n+\n+\treturn ath10k_wmi_cmd_send(ar, skb, ar->wmi.cmd->gpio_output_cmdid);\n+}\n+\n static inline int\n ath10k_wmi_dbglog_cfg(struct ath10k *ar, u64 module_enable, u32 log_level)\n {\n--- a/drivers/net/wireless/ath/ath10k/wmi-tlv.c\n+++ b/drivers/net/wireless/ath/ath10k/wmi-tlv.c\n@@ -4594,6 +4594,8 @@ static const struct wmi_ops wmi_tlv_ops\n \t.gen_echo = ath10k_wmi_tlv_op_gen_echo,\n \t.gen_vdev_spectral_conf = ath10k_wmi_tlv_op_gen_vdev_spectral_conf,\n \t.gen_vdev_spectral_enable = ath10k_wmi_tlv_op_gen_vdev_spectral_enable,\n+\t/* .gen_gpio_config not implemented */\n+\t/* .gen_gpio_output not implemented */\n };\n \n static const struct wmi_peer_flags_map wmi_tlv_peer_flags_map = {\n--- a/drivers/net/wireless/ath/ath10k/wmi.c\n+++ b/drivers/net/wireless/ath/ath10k/wmi.c\n@@ -7472,6 +7472,49 @@ ath10k_wmi_op_gen_peer_set_param(struct\n \treturn skb;\n }\n \n+static struct sk_buff *ath10k_wmi_op_gen_gpio_config(struct ath10k *ar,\n+\t\t\t\t\t\t     u32 gpio_num, u32 input,\n+\t\t\t\t\t\t     u32 pull_type, u32 intr_mode)\n+{\n+\tstruct wmi_gpio_config_cmd *cmd;\n+\tstruct sk_buff *skb;\n+\n+\tskb = ath10k_wmi_alloc_skb(ar, sizeof(*cmd));\n+\tif (!skb)\n+\t\treturn ERR_PTR(-ENOMEM);\n+\n+\tcmd = (struct wmi_gpio_config_cmd *)skb->data;\n+\tcmd->pull_type = __cpu_to_le32(pull_type);\n+\tcmd->gpio_num = __cpu_to_le32(gpio_num);\n+\tcmd->input = __cpu_to_le32(input);\n+\tcmd->intr_mode = __cpu_to_le32(intr_mode);\n+\n+\tath10k_dbg(ar, ATH10K_DBG_WMI, \"wmi gpio_config gpio_num 0x%08x input 0x%08x pull_type 0x%08x intr_mode 0x%08x\\n\",\n+\t\t   gpio_num, input, pull_type, intr_mode);\n+\n+\treturn skb;\n+}\n+\n+static struct sk_buff *ath10k_wmi_op_gen_gpio_output(struct ath10k *ar,\n+\t\t\t\t\t\t     u32 gpio_num, u32 set)\n+{\n+\tstruct wmi_gpio_output_cmd *cmd;\n+\tstruct sk_buff *skb;\n+\n+\tskb = ath10k_wmi_alloc_skb(ar, sizeof(*cmd));\n+\tif (!skb)\n+\t\treturn ERR_PTR(-ENOMEM);\n+\n+\tcmd = (struct wmi_gpio_output_cmd *)skb->data;\n+\tcmd->gpio_num = __cpu_to_le32(gpio_num);\n+\tcmd->set = __cpu_to_le32(set);\n+\n+\tath10k_dbg(ar, ATH10K_DBG_WMI, \"wmi gpio_output gpio_num 0x%08x set 0x%08x\\n\",\n+\t\t   gpio_num, set);\n+\n+\treturn skb;\n+}\n+\n static struct sk_buff *\n ath10k_wmi_op_gen_set_psmode(struct ath10k *ar, u32 vdev_id,\n \t\t\t     enum wmi_sta_ps_mode psmode)\n@@ -9160,6 +9203,9 @@ static const struct wmi_ops wmi_ops = {\n \t.fw_stats_fill = ath10k_wmi_main_op_fw_stats_fill,\n \t.get_vdev_subtype = ath10k_wmi_op_get_vdev_subtype,\n \t.gen_echo = ath10k_wmi_op_gen_echo,\n+\t.gen_gpio_config = ath10k_wmi_op_gen_gpio_config,\n+\t.gen_gpio_output = ath10k_wmi_op_gen_gpio_output,\n+\n \t/* .gen_bcn_tmpl not implemented */\n \t/* .gen_prb_tmpl not implemented */\n \t/* .gen_p2p_go_bcn_ie not implemented */\n@@ -9230,6 +9276,8 @@ static const struct wmi_ops wmi_10_1_ops\n \t.fw_stats_fill = ath10k_wmi_10x_op_fw_stats_fill,\n \t.get_vdev_subtype = ath10k_wmi_op_get_vdev_subtype,\n \t.gen_echo = ath10k_wmi_op_gen_echo,\n+\t.gen_gpio_config = ath10k_wmi_op_gen_gpio_config,\n+\t.gen_gpio_output = ath10k_wmi_op_gen_gpio_output,\n \t/* .gen_bcn_tmpl not implemented */\n \t/* .gen_prb_tmpl not implemented */\n \t/* .gen_p2p_go_bcn_ie not implemented */\n@@ -9302,6 +9350,8 @@ static const struct wmi_ops wmi_10_2_ops\n \t.gen_delba_send = ath10k_wmi_op_gen_delba_send,\n \t.fw_stats_fill = ath10k_wmi_10x_op_fw_stats_fill,\n \t.get_vdev_subtype = ath10k_wmi_op_get_vdev_subtype,\n+\t.gen_gpio_config = ath10k_wmi_op_gen_gpio_config,\n+\t.gen_gpio_output = ath10k_wmi_op_gen_gpio_output,\n \t/* .gen_pdev_enable_adaptive_cca not implemented */\n };\n \n@@ -9373,6 +9423,8 @@ static const struct wmi_ops wmi_10_2_4_o\n \t\tath10k_wmi_op_gen_pdev_enable_adaptive_cca,\n \t.get_vdev_subtype = ath10k_wmi_10_2_4_op_get_vdev_subtype,\n \t.gen_bb_timing = ath10k_wmi_10_2_4_op_gen_bb_timing,\n+\t.gen_gpio_config = ath10k_wmi_op_gen_gpio_config,\n+\t.gen_gpio_output = ath10k_wmi_op_gen_gpio_output,\n \t/* .gen_bcn_tmpl not implemented */\n \t/* .gen_prb_tmpl not implemented */\n \t/* .gen_p2p_go_bcn_ie not implemented */\n@@ -9454,6 +9506,8 @@ static const struct wmi_ops wmi_10_4_ops\n \t.gen_pdev_bss_chan_info_req = ath10k_wmi_10_2_op_gen_pdev_bss_chan_info,\n \t.gen_echo = ath10k_wmi_op_gen_echo,\n \t.gen_pdev_get_tpc_config = ath10k_wmi_10_2_4_op_gen_pdev_get_tpc_config,\n+\t.gen_gpio_config = ath10k_wmi_op_gen_gpio_config,\n+\t.gen_gpio_output = ath10k_wmi_op_gen_gpio_output,\n };\n \n int ath10k_wmi_attach(struct ath10k *ar)\n--- a/drivers/net/wireless/ath/ath10k/wmi.h\n+++ b/drivers/net/wireless/ath/ath10k/wmi.h\n@@ -3030,6 +3030,41 @@ enum wmi_10_4_feature_mask {\n \n };\n \n+/* WMI_GPIO_CONFIG_CMDID */\n+enum {\n+\tWMI_GPIO_PULL_NONE,\n+\tWMI_GPIO_PULL_UP,\n+\tWMI_GPIO_PULL_DOWN,\n+};\n+\n+enum {\n+\tWMI_GPIO_INTTYPE_DISABLE,\n+\tWMI_GPIO_INTTYPE_RISING_EDGE,\n+\tWMI_GPIO_INTTYPE_FALLING_EDGE,\n+\tWMI_GPIO_INTTYPE_BOTH_EDGE,\n+\tWMI_GPIO_INTTYPE_LEVEL_LOW,\n+\tWMI_GPIO_INTTYPE_LEVEL_HIGH\n+};\n+\n+/* WMI_GPIO_CONFIG_CMDID */\n+struct wmi_gpio_config_cmd {\n+\t__le32 gpio_num;             /* GPIO number to be setup */\n+\t__le32 input;                /* 0 - Output/ 1 - Input */\n+\t__le32 pull_type;            /* Pull type defined above */\n+\t__le32 intr_mode;            /* Interrupt mode defined above (Input) */\n+} __packed;\n+\n+/* WMI_GPIO_OUTPUT_CMDID */\n+struct wmi_gpio_output_cmd {\n+\t__le32 gpio_num;    /* GPIO number to be setup */\n+\t__le32 set;         /* Set the GPIO pin*/\n+} __packed;\n+\n+/* WMI_GPIO_INPUT_EVENTID */\n+struct wmi_gpio_input_event {\n+\t__le32 gpio_num;    /* GPIO number which changed state */\n+} __packed;\n+\n struct wmi_ext_resource_config_10_4_cmd {\n \t/* contains enum wmi_host_platform_type */\n \t__le32 host_platform_config;\n"
  },
  {
    "path": "package/kernel/mac80211/patches/ath10k/975-ath10k-use-tpt-trigger-by-default.patch",
    "content": "From 79c9d7aabae1d1da9eea97d83b61e1517a8a2221 Mon Sep 17 00:00:00 2001\nFrom: Mathias Kresin <dev@kresin.me>\nDate: Fri, 22 Jun 2018 18:59:44 +0200\nSubject: [PATCH] ath10k: use tpt LED trigger by default\n\nUse the tpt LED trigger for each created phy led. Ths way LEDs attached\nto the ath10k GPIO pins are indicating the phy status and blink on\ntraffic.\n\nSigned-off-by: Mathias Kresin <dev@kresin.me>\n---\n drivers/net/wireless/ath/ath10k/core.h | 4 ++++\n drivers/net/wireless/ath/ath10k/leds.c | 4 +---\n drivers/net/wireless/ath/ath10k/mac.c  | 2 +-\n 3 files changed, 6 insertions(+), 4 deletions(-)\n\n--- a/drivers/net/wireless/ath/ath10k/core.h\n+++ b/drivers/net/wireless/ath/ath10k/core.h\n@@ -1312,6 +1312,10 @@ struct ath10k {\n \ts32 tx_power_2g_limit;\n \ts32 tx_power_5g_limit;\n \n+#ifdef CPTCFG_MAC80211_LEDS\n+\tconst char *led_default_trigger;\n+#endif\n+\n \t/* must be last */\n \tu8 drv_priv[] __aligned(sizeof(void *));\n };\n--- a/drivers/net/wireless/ath/ath10k/leds.c\n+++ b/drivers/net/wireless/ath/ath10k/leds.c\n@@ -81,9 +81,7 @@ int ath10k_leds_register(struct ath10k *\n \n \tar->leds.cdev.name = ar->leds.label;\n \tar->leds.cdev.brightness_set_blocking = ath10k_leds_set_brightness_blocking;\n-\n-\t/* FIXME: this assignment doesn't make sense as it's NULL, remove it? */\n-\tar->leds.cdev.default_trigger = ar->leds.wifi_led.default_trigger;\n+\tar->leds.cdev.default_trigger = ar->led_default_trigger;\n \n \tret = led_classdev_register(wiphy_dev(ar->hw->wiphy), &ar->leds.cdev);\n \tif (ret)\n--- a/drivers/net/wireless/ath/ath10k/mac.c\n+++ b/drivers/net/wireless/ath/ath10k/mac.c\n@@ -10212,7 +10212,7 @@ int ath10k_mac_register(struct ath10k *a\n \tar->hw->weight_multiplier = ATH10K_AIRTIME_WEIGHT_MULTIPLIER;\n \n #ifdef CPTCFG_MAC80211_LEDS\n-\tieee80211_create_tpt_led_trigger(ar->hw,\n+\tar->led_default_trigger = ieee80211_create_tpt_led_trigger(ar->hw,\n \t\tIEEE80211_TPT_LEDTRIG_FL_RADIO, ath10k_tpt_blink,\n \t\tARRAY_SIZE(ath10k_tpt_blink));\n #endif\n"
  },
  {
    "path": "package/kernel/mac80211/patches/ath10k/981-ath10k-adjust-tx-power-reduction-for-US-regulatory-d.patch",
    "content": "From: Sven Eckelmann <seckelmann@datto.com>\nDate: Wed, 28 Nov 2018 16:16:27 +0100\nSubject: ath10k: adjust tx power reduction for US regulatory domain\n\nFCC allows maximum antenna gain of 6 dBi. 15.247(b)(4):\n\n> (4) The conducted output power limit\n> specified in paragraph (b) of this section\n> is based on the use of antennas\n> with directional gains that do not exceed\n> 6 dBi. Except as shown in paragraph\n> (c) of this section, if transmitting\n> antennas of directional gain greater\n> than 6 dBi are used, the conducted\n> output power from the intentional radiator\n> shall be reduced below the stated\n> values in paragraphs (b)(1), (b)(2),\n> and (b)(3) of this section, as appropriate,\n> by the amount in dB that the\n> directional gain of the antenna exceeds\n> 6 dBi.\n\nhttps://www.gpo.gov/fdsys/pkg/CFR-2013-title47-vol1/pdf/CFR-2013-title47-vol1-sec15-247.pdf\n\nSigned-off-by: Sven Eckelmann <seckelmann@datto.com>\n\nForwarded: no\n\n--- a/drivers/net/wireless/ath/ath10k/mac.c\n+++ b/drivers/net/wireless/ath/ath10k/mac.c\n@@ -1021,6 +1021,40 @@ static inline int ath10k_vdev_setup_sync\n \treturn ar->last_wmi_vdev_start_status;\n }\n \n+static u32 ath10k_get_max_antenna_gain(struct ath10k *ar,\n+\t\t\t\t       u32 ch_max_antenna_gain)\n+{\n+\tu32 max_antenna_gain;\n+\n+\tif (ar->dfs_detector && ar->dfs_detector->region == NL80211_DFS_FCC) {\n+\t\t/* FCC allows maximum antenna gain of 6 dBi. 15.247(b)(4):\n+\t\t *\n+\t\t * > (4) The conducted output power limit\n+\t\t * > specified in paragraph (b) of this section\n+\t\t * > is based on the use of antennas\n+\t\t * > with directional gains that do not exceed\n+\t\t * > 6 dBi. Except as shown in paragraph\n+\t\t * > (c) of this section, if transmitting\n+\t\t * > antennas of directional gain greater\n+\t\t * > than 6 dBi are used, the conducted\n+\t\t * > output power from the intentional radiator\n+\t\t * > shall be reduced below the stated\n+\t\t * > values in paragraphs (b)(1), (b)(2),\n+\t\t * > and (b)(3) of this section, as appropriate,\n+\t\t * > by the amount in dB that the\n+\t\t * > directional gain of the antenna exceeds\n+\t\t * > 6 dBi.\n+\t\t *\n+\t\t * https://www.gpo.gov/fdsys/pkg/CFR-2013-title47-vol1/pdf/CFR-2013-title47-vol1-sec15-247.pdf\n+\t\t */\n+\t\tmax_antenna_gain = 6;\n+\t} else {\n+\t\tmax_antenna_gain = 0;\n+\t}\n+\n+\treturn max(ch_max_antenna_gain, max_antenna_gain);\n+}\n+\n static int ath10k_monitor_vdev_start(struct ath10k *ar, int vdev_id)\n {\n \tstruct cfg80211_chan_def *chandef = NULL;\n@@ -1053,7 +1087,8 @@ static int ath10k_monitor_vdev_start(str\n \targ.channel.min_power = 0;\n \targ.channel.max_power = channel->max_power * 2;\n \targ.channel.max_reg_power = channel->max_reg_power * 2;\n-\targ.channel.max_antenna_gain = channel->max_antenna_gain;\n+\targ.channel.max_antenna_gain = ath10k_get_max_antenna_gain(ar,\n+\t\t\t\t\t\tchannel->max_antenna_gain);\n \n \treinit_completion(&ar->vdev_setup_done);\n \treinit_completion(&ar->vdev_delete_done);\n@@ -1499,7 +1534,8 @@ static int ath10k_vdev_start_restart(str\n \targ.channel.min_power = 0;\n \targ.channel.max_power = chandef->chan->max_power * 2;\n \targ.channel.max_reg_power = chandef->chan->max_reg_power * 2;\n-\targ.channel.max_antenna_gain = chandef->chan->max_antenna_gain;\n+\targ.channel.max_antenna_gain = ath10k_get_max_antenna_gain(ar,\n+\t\t\t\t\tchandef->chan->max_antenna_gain);\n \n \tif (arvif->vdev_type == WMI_VDEV_TYPE_AP) {\n \t\targ.ssid = arvif->u.ap.ssid;\n@@ -3427,7 +3463,8 @@ static int ath10k_update_channel_list(st\n \t\t\tch->min_power = 0;\n \t\t\tch->max_power = channel->max_power * 2;\n \t\t\tch->max_reg_power = channel->max_reg_power * 2;\n-\t\t\tch->max_antenna_gain = channel->max_antenna_gain;\n+\t\t\tch->max_antenna_gain = ath10k_get_max_antenna_gain(ar,\n+\t\t\t\t\t\tchannel->max_antenna_gain);\n \t\t\tch->reg_class_id = 0; /* FIXME */\n \n \t\t\t/* FIXME: why use only legacy modes, why not any\n"
  },
  {
    "path": "package/kernel/mac80211/patches/ath10k/984-ath10k-Try-to-get-mac-address-from-dts.patch",
    "content": "From 22fb5991a44c78ff18ec0082dc90c809356eb893 Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Sun, 27 Sep 2020 19:23:35 +0200\nSubject: [PATCH 1/2] ath10k: Try to get mac-address from dts\n\nMost of embedded device that have the ath10k wifi integrated store the\nmac-address in nvmem partitions. Try to fetch the mac-address using the\nstandard 'of_get_mac_address' than in all the check also try to fetch the\naddress using the nvmem api searching for a defined 'mac-address' cell.\nMac-address defined in the dts have priority than any other address found.\n\nTested-on: QCA9984 hw1.0 PCI 10.4\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\n---\n drivers/net/wireless/ath/ath10k/core.c | 10 ++++++++++\n 1 file changed, 10 insertions(+)\n\n--- a/drivers/net/wireless/ath/ath10k/core.c\n+++ b/drivers/net/wireless/ath/ath10k/core.c\n@@ -8,6 +8,7 @@\n #include <linux/module.h>\n #include <linux/firmware.h>\n #include <linux/of.h>\n+#include <linux/of_net.h>\n #include <linux/property.h>\n #include <linux/dmi.h>\n #include <linux/ctype.h>\n@@ -3320,6 +3321,8 @@ static int ath10k_core_probe_fw(struct a\n \n \tdevice_get_mac_address(ar->dev, ar->mac_addr, sizeof(ar->mac_addr));\n \n+\tof_get_mac_address(ar->dev->of_node, ar->mac_addr);\n+\n \tret = ath10k_core_init_firmware_features(ar);\n \tif (ret) {\n \t\tath10k_err(ar, \"fatal problem with firmware features: %d\\n\",\n"
  },
  {
    "path": "package/kernel/mac80211/patches/ath10k/990-ath10k-small-buffers.patch",
    "content": "--- a/drivers/net/wireless/ath/ath10k/htt.h\n+++ b/drivers/net/wireless/ath/ath10k/htt.h\n@@ -235,7 +235,11 @@ enum htt_rx_ring_flags {\n };\n \n #define HTT_RX_RING_SIZE_MIN 128\n+#ifndef CONFIG_ATH10K_SMALLBUFFERS\n #define HTT_RX_RING_SIZE_MAX 2048\n+#else\n+#define HTT_RX_RING_SIZE_MAX 512\n+#endif\n #define HTT_RX_RING_SIZE HTT_RX_RING_SIZE_MAX\n #define HTT_RX_RING_FILL_LEVEL (((HTT_RX_RING_SIZE) / 2) - 1)\n #define HTT_RX_RING_FILL_LEVEL_DUAL_MAC (HTT_RX_RING_SIZE - 1)\n--- a/drivers/net/wireless/ath/ath10k/pci.c\n+++ b/drivers/net/wireless/ath/ath10k/pci.c\n@@ -131,7 +131,11 @@ static const struct ce_attr pci_host_ce_\n \t\t.flags = CE_ATTR_FLAGS,\n \t\t.src_nentries = 0,\n \t\t.src_sz_max = 2048,\n+#ifndef CONFIG_ATH10K_SMALLBUFFERS\n \t\t.dest_nentries = 512,\n+#else\n+\t\t.dest_nentries = 128,\n+#endif\n \t\t.recv_cb = ath10k_pci_htt_htc_rx_cb,\n \t},\n \n@@ -140,7 +144,11 @@ static const struct ce_attr pci_host_ce_\n \t\t.flags = CE_ATTR_FLAGS,\n \t\t.src_nentries = 0,\n \t\t.src_sz_max = 2048,\n+#ifndef CONFIG_ATH10K_SMALLBUFFERS\n \t\t.dest_nentries = 128,\n+#else\n+\t\t.dest_nentries = 64,\n+#endif\n \t\t.recv_cb = ath10k_pci_htc_rx_cb,\n \t},\n \n@@ -167,7 +175,11 @@ static const struct ce_attr pci_host_ce_\n \t\t.flags = CE_ATTR_FLAGS,\n \t\t.src_nentries = 0,\n \t\t.src_sz_max = 512,\n+#ifndef CONFIG_ATH10K_SMALLBUFFERS\n \t\t.dest_nentries = 512,\n+#else\n+\t\t.dest_nentries = 128,\n+#endif\n \t\t.recv_cb = ath10k_pci_htt_rx_cb,\n \t},\n \n@@ -192,7 +204,11 @@ static const struct ce_attr pci_host_ce_\n \t\t.flags = CE_ATTR_FLAGS,\n \t\t.src_nentries = 0,\n \t\t.src_sz_max = 2048,\n+#ifndef CONFIG_ATH10K_SMALLBUFFERS\n \t\t.dest_nentries = 128,\n+#else\n+\t\t.dest_nentries = 96,\n+#endif\n \t\t.recv_cb = ath10k_pci_pktlog_rx_cb,\n \t},\n \n"
  },
  {
    "path": "package/kernel/mac80211/patches/ath5k/201-ath5k-WAR-for-AR71xx-PCI-bug.patch",
    "content": "--- a/drivers/net/wireless/ath/ath5k/initvals.c\n+++ b/drivers/net/wireless/ath/ath5k/initvals.c\n@@ -62,8 +62,14 @@ static const struct ath5k_ini ar5210_ini\n \t{ AR5K_IMR,\t\t0 },\n \t{ AR5K_IER,\t\tAR5K_IER_DISABLE },\n \t{ AR5K_BSR,\t\t0, AR5K_INI_READ },\n+#if !defined(CONFIG_ATHEROS_AR71XX) && !defined(CONFIG_ATH79)\n \t{ AR5K_TXCFG,\t\tAR5K_DMASIZE_128B },\n \t{ AR5K_RXCFG,\t\tAR5K_DMASIZE_128B },\n+#else\n+\t/* WAR for AR71xx PCI bug */\n+\t{ AR5K_TXCFG,\t\tAR5K_DMASIZE_128B },\n+\t{ AR5K_RXCFG,\t\tAR5K_DMASIZE_4B },\n+#endif\n \t{ AR5K_CFG,\t\tAR5K_INIT_CFG },\n \t{ AR5K_TOPS,\t\t8 },\n \t{ AR5K_RXNOFRM,\t\t8 },\n--- a/drivers/net/wireless/ath/ath5k/dma.c\n+++ b/drivers/net/wireless/ath/ath5k/dma.c\n@@ -869,10 +869,18 @@ ath5k_hw_dma_init(struct ath5k_hw *ah)\n \t * guess we can tweak it and see how it goes ;-)\n \t */\n \tif (ah->ah_version != AR5K_AR5210) {\n+#if !defined(CONFIG_ATHEROS_AR71XX) && !defined(CONFIG_ATH79)\n \t\tAR5K_REG_WRITE_BITS(ah, AR5K_TXCFG,\n \t\t\tAR5K_TXCFG_SDMAMR, AR5K_DMASIZE_128B);\n \t\tAR5K_REG_WRITE_BITS(ah, AR5K_RXCFG,\n \t\t\tAR5K_RXCFG_SDMAMW, AR5K_DMASIZE_128B);\n+#else\n+\t\t/* WAR for AR71xx PCI bug */\n+\t\tAR5K_REG_WRITE_BITS(ah, AR5K_TXCFG,\n+\t\t\tAR5K_TXCFG_SDMAMR, AR5K_DMASIZE_128B);\n+\t\tAR5K_REG_WRITE_BITS(ah, AR5K_RXCFG,\n+\t\t\tAR5K_RXCFG_SDMAMW, AR5K_DMASIZE_4B);\n+#endif\n \t}\n \n \t/* Pre-enable interrupts on 5211/5212*/\n"
  },
  {
    "path": "package/kernel/mac80211/patches/ath5k/411-ath5k_allow_adhoc_and_ap.patch",
    "content": "--- a/drivers/net/wireless/ath/ath5k/mac80211-ops.c\n+++ b/drivers/net/wireless/ath/ath5k/mac80211-ops.c\n@@ -86,13 +86,8 @@ ath5k_add_interface(struct ieee80211_hw\n \t\tgoto end;\n \t}\n \n-\t/* Don't allow other interfaces if one ad-hoc is configured.\n-\t * TODO: Fix the problems with ad-hoc and multiple other interfaces.\n-\t * We would need to operate the HW in ad-hoc mode to allow TSF updates\n-\t * for the IBSS, but this breaks with additional AP or STA interfaces\n-\t * at the moment. */\n-\tif (ah->num_adhoc_vifs ||\n-\t    (ah->nvifs && vif->type == NL80211_IFTYPE_ADHOC)) {\n+\t/* Don't allow more than one ad-hoc interface */\n+\tif (ah->num_adhoc_vifs && vif->type == NL80211_IFTYPE_ADHOC) {\n \t\tATH5K_ERR(ah, \"Only one single ad-hoc interface is allowed.\\n\");\n \t\tret = -ELNRNG;\n \t\tgoto end;\n--- a/drivers/net/wireless/ath/ath5k/base.c\n+++ b/drivers/net/wireless/ath/ath5k/base.c\n@@ -1963,7 +1963,7 @@ ath5k_beacon_send(struct ath5k_hw *ah)\n \t}\n \n \tif ((ah->opmode == NL80211_IFTYPE_AP && ah->num_ap_vifs +\n-\t\t\tah->num_mesh_vifs > 1) ||\n+\t\t\tah->num_adhoc_vifs + ah->num_mesh_vifs > 1) ||\n \t\t\tah->opmode == NL80211_IFTYPE_MESH_POINT) {\n \t\tu64 tsf = ath5k_hw_get_tsf64(ah);\n \t\tu32 tsftu = TSF_TO_TU(tsf);\n@@ -2049,7 +2049,7 @@ ath5k_beacon_update_timers(struct ath5k_\n \n \tintval = ah->bintval & AR5K_BEACON_PERIOD;\n \tif (ah->opmode == NL80211_IFTYPE_AP && ah->num_ap_vifs\n-\t\t+ ah->num_mesh_vifs > 1) {\n+\t\t+ ah->num_adhoc_vifs + ah->num_mesh_vifs > 1) {\n \t\tintval /= ATH_BCBUF;\t/* staggered multi-bss beacons */\n \t\tif (intval < 15)\n \t\t\tATH5K_WARN(ah, \"intval %u is too low, min 15\\n\",\n@@ -2515,6 +2515,7 @@ static const struct ieee80211_iface_limi\n \t\t\t\t BIT(NL80211_IFTYPE_MESH_POINT) |\n #endif\n \t\t\t\t BIT(NL80211_IFTYPE_AP) },\n+\t{ .max = 1,\t.types = BIT(NL80211_IFTYPE_ADHOC) },\n };\n \n static const struct ieee80211_iface_combination if_comb = {\n"
  },
  {
    "path": "package/kernel/mac80211/patches/ath5k/420-ath5k_disable_fast_cc.patch",
    "content": "--- a/drivers/net/wireless/ath/ath5k/reset.c\n+++ b/drivers/net/wireless/ath/ath5k/reset.c\n@@ -1154,6 +1154,7 @@ ath5k_hw_reset(struct ath5k_hw *ah, enum\n \ttsf_lo = 0;\n \tmode = 0;\n \n+#if 0\n \t/*\n \t * Sanity check for fast flag\n \t * Fast channel change only available\n@@ -1161,6 +1162,7 @@ ath5k_hw_reset(struct ath5k_hw *ah, enum\n \t */\n \tif (fast && (ah->ah_radio != AR5K_RF2413) &&\n \t(ah->ah_radio != AR5K_RF5413))\n+#endif\n \t\tfast = false;\n \n \t/* Disable sleep clock operation\n"
  },
  {
    "path": "package/kernel/mac80211/patches/ath5k/430-add_ath5k_platform.patch",
    "content": "--- /dev/null\n+++ b/include/linux/ath5k_platform.h\n@@ -0,0 +1,30 @@\n+/*\n+ * Copyright (c) 2008 Atheros Communications Inc.\n+ * Copyright (c) 2009 Gabor Juhos <juhosg@openwrt.org>\n+ * Copyright (c) 2009 Imre Kaloz <kaloz@openwrt.org>\n+ * Copyright (c) 2010 Daniel Golle <daniel.golle@gmail.com>\n+ *\n+ * Permission to use, copy, modify, and/or distribute this software for any\n+ * purpose with or without fee is hereby granted, provided that the above\n+ * copyright notice and this permission notice appear in all copies.\n+ *\n+ * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n+ */\n+\n+#ifndef _LINUX_ATH5K_PLATFORM_H\n+#define _LINUX_ATH5K_PLATFORM_H\n+\n+#define ATH5K_PLAT_EEP_MAX_WORDS\t2048\n+\n+struct ath5k_platform_data {\n+\tu16 *eeprom_data;\n+\tu8 *macaddr;\n+};\n+\n+#endif /* _LINUX_ATH5K_PLATFORM_H */\n"
  },
  {
    "path": "package/kernel/mac80211/patches/ath5k/432-ath5k_add_pciids.patch",
    "content": "--- a/drivers/net/wireless/ath/ath5k/pci.c\n+++ b/drivers/net/wireless/ath/ath5k/pci.c\n@@ -47,6 +47,8 @@ static const struct pci_device_id ath5k_\n \t{ PCI_VDEVICE(ATHEROS, 0x001b) }, /* 5413 Eagle */\n \t{ PCI_VDEVICE(ATHEROS, 0x001c) }, /* PCI-E cards */\n \t{ PCI_VDEVICE(ATHEROS, 0x001d) }, /* 2417 Nala */\n+\t{ PCI_VDEVICE(ATHEROS, 0xff16) }, /* 2413,2414 sx76x on lantiq_danube */\n+\t{ PCI_VDEVICE(ATHEROS, 0xff1a) }, /* 2417 arv45xx on lantiq_danube */\n \t{ PCI_VDEVICE(ATHEROS, 0xff1b) }, /* AR5BXB63 */\n \t{ 0 }\n };\n"
  },
  {
    "path": "package/kernel/mac80211/patches/ath5k/440-ath5k_channel_bw_debugfs.patch",
    "content": "This adds a bwmode debugfs file which can be used to set alternate\nchannel operating bandwidths.  Only tested with AR5413 and only at\n5 and 20 mhz channels.\n\nSigned-off-by: Pat Erley <pat-lkml at erley.org>\n---\nOther devices will need to be added to the switch in  write_file_bwmode\n\ndrivers/net/wireless/ath/ath5k/debug.c |   86 ++++++++++++++++++++++++++++++++\n 1 files changed, 86 insertions(+), 0 deletions(-)\n\n--- a/drivers/net/wireless/ath/ath5k/debug.c\n+++ b/drivers/net/wireless/ath/ath5k/debug.c\n@@ -803,6 +803,97 @@ static const struct file_operations fops\n \t.llseek = default_llseek,\n };\n \n+/* debugfs: bwmode */\n+\n+static ssize_t read_file_bwmode(struct file *file, char __user *user_buf,\n+\t\t\t\t   size_t count, loff_t *ppos)\n+{\n+\tstruct ath5k_hw *ah = file->private_data;\n+\tchar buf[15];\n+\tunsigned int len = 0;\n+\n+\tint cur_ah_bwmode = ah->ah_bwmode_debug;\n+\n+#define print_selected(MODE, LABEL) \\\n+\tif (cur_ah_bwmode == MODE) \\\n+\t\tlen += snprintf(buf+len, sizeof(buf)-len, \"[%s]\", LABEL); \\\n+\telse \\\n+\t\tlen += snprintf(buf+len, sizeof(buf)-len, \"%s\", LABEL); \\\n+\tlen += snprintf(buf+len, sizeof(buf)-len, \" \");\n+\n+\tprint_selected(AR5K_BWMODE_5MHZ, \"5\");\n+\tprint_selected(AR5K_BWMODE_10MHZ, \"10\");\n+\tprint_selected(AR5K_BWMODE_DEFAULT, \"20\");\n+\tprint_selected(AR5K_BWMODE_40MHZ, \"40\");\n+#undef print_selected\n+\n+\tlen += snprintf(buf+len, sizeof(buf)-len, \"\\n\");\n+\n+\treturn simple_read_from_buffer(user_buf, count, ppos, buf, len);\n+}\n+\n+static ssize_t write_file_bwmode(struct file *file,\n+\t\t\t\t const char __user *userbuf,\n+\t\t\t\t size_t count, loff_t *ppos)\n+{\n+\tstruct ath5k_hw *ah = file->private_data;\n+\tchar buf[3];\n+\tint bw = 20;\n+\tint tobwmode = AR5K_BWMODE_DEFAULT;\n+\n+\tif (copy_from_user(buf, userbuf, min(count, sizeof(buf))))\n+\t\treturn -EFAULT;\n+\n+\t/* TODO: Add check for active interface */\n+\n+\tif(strncmp(buf, \"5\", 1) == 0 ) {\n+\t\ttobwmode = AR5K_BWMODE_5MHZ;\n+\t\tbw = 5;\n+\t} else if ( strncmp(buf, \"10\", 2) == 0 ) {\n+\t\ttobwmode = AR5K_BWMODE_10MHZ;\n+\t\tbw = 10;\n+\t} else if ( strncmp(buf, \"20\", 2) == 0 ) {\n+\t\ttobwmode = AR5K_BWMODE_DEFAULT;\n+\t\tbw = 20;\n+\t} else if ( strncmp(buf, \"40\", 2) == 0 ) {\n+\t\ttobwmode = AR5K_BWMODE_40MHZ;\n+\t\tbw = 40;\n+\t} else\n+\t\treturn -EINVAL;\n+\n+\tATH5K_INFO(ah, \"Changing to %imhz channel width[%i]\\n\",\n+\t\tbw, tobwmode);\n+\n+\tswitch (ah->ah_radio) {\n+\t/* TODO: only define radios that actually support 5/10mhz channels */\n+\tcase AR5K_RF5413:\n+\tcase AR5K_RF5110:\n+\tcase AR5K_RF5111:\n+\tcase AR5K_RF5112:\n+\tcase AR5K_RF2413:\n+\tcase AR5K_RF2316:\n+\tcase AR5K_RF2317:\n+\tcase AR5K_RF2425:\n+\t\tif(ah->ah_bwmode_debug != tobwmode) {\n+\t\t\tmutex_lock(&ah->lock);\n+\t\t\tah->ah_bwmode = tobwmode;\n+\t\t\tah->ah_bwmode_debug = tobwmode;\n+\t\t\tmutex_unlock(&ah->lock);\n+\t\t}\n+\t\tbreak;\n+\tdefault:\n+\t\treturn -EOPNOTSUPP;\n+\t}\n+\treturn count;\n+}\n+\n+static const struct file_operations fops_bwmode = {\n+\t.read = read_file_bwmode,\n+\t.write = write_file_bwmode,\n+\t.open = simple_open,\n+\t.owner = THIS_MODULE,\n+\t.llseek = default_llseek,\n+};\n \n /* debugfs: queues etc */\n \n@@ -997,6 +1088,8 @@ ath5k_debug_init_device(struct ath5k_hw\n \tdebugfs_create_file(\"queue\", 0600, phydir, ah, &fops_queue);\n \tdebugfs_create_bool(\"32khz_clock\", 0600, phydir,\n \t\t\t    &ah->ah_use_32khz_clock);\n+\tdebugfs_create_file(\"bwmode\", S_IWUSR | S_IRUSR, phydir, ah,\n+\t\t\t    &fops_bwmode);\n }\n \n /* functions used in other places */\n--- a/drivers/net/wireless/ath/ath5k/ath5k.h\n+++ b/drivers/net/wireless/ath/ath5k/ath5k.h\n@@ -1372,6 +1372,7 @@ struct ath5k_hw {\n \tu8\t\t\tah_coverage_class;\n \tbool\t\t\tah_ack_bitrate_high;\n \tu8\t\t\tah_bwmode;\n+\tu8\t\t\tah_bwmode_debug;\n \tbool\t\t\tah_short_slot;\n \n \t/* Antenna Control */\n--- a/drivers/net/wireless/ath/ath5k/base.c\n+++ b/drivers/net/wireless/ath/ath5k/base.c\n@@ -465,6 +465,9 @@ ath5k_chan_set(struct ath5k_hw *ah, stru\n \t\treturn -EINVAL;\n \t}\n \n+\tif (ah->ah_bwmode_debug != AR5K_BWMODE_DEFAULT)\n+\t\tah->ah_bwmode = ah->ah_bwmode_debug;\n+\n \t/*\n \t * To switch channels clear any pending DMA operations;\n \t * wait long enough for the RX fifo to drain, reset the\n"
  },
  {
    "path": "package/kernel/mac80211/patches/ath9k/040-ath9k-support-DT-ieee80211-freq-limit-property-to-li.patch",
    "content": "From 03469e79fee9e8e908dae3bd1a80bcd9a66f2a88 Mon Sep 17 00:00:00 2001\nFrom: Christian Lamparter <chunkeey@gmail.com>\nDate: Mon, 11 Oct 2021 18:18:00 +0300\nSubject: ath9k: support DT ieee80211-freq-limit property to limit channels\n\nThe common DT property can be used to limit the available channels\nbut ath9k has to manually call wiphy_read_of_freq_limits().\n\nI would have put this into ath9k_of_init(). But it didn't work there.\nThe reason is that in ath9k_of_init() the channels and bands are not yet\nregistered in the wiphy struct. So there isn't any channel to flag as\ndisabled.\n\nSigned-off-by: Christian Lamparter <chunkeey@gmail.com>\nSigned-off-by: Kalle Valo <kvalo@codeaurora.org>\nLink: https://lore.kernel.org/r/20211009212847.1781986-1-chunkeey@gmail.com\n---\n--- a/drivers/net/wireless/ath/ath9k/init.c\n+++ b/drivers/net/wireless/ath/ath9k/init.c\n@@ -1038,6 +1038,8 @@ int ath9k_init_device(u16 devid, struct\n \t\tARRAY_SIZE(ath9k_tpt_blink));\n #endif\n \n+\twiphy_read_of_freq_limits(hw->wiphy);\n+\n \t/* Register with mac80211 */\n \terror = ieee80211_register_hw(hw);\n \tif (error)\n"
  },
  {
    "path": "package/kernel/mac80211/patches/ath9k/350-ath9k_hw-reset-AHB-WMAC-interface-on-AR91xx.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nDate: Sat, 9 Jul 2016 15:25:24 +0200\nSubject: [PATCH] ath9k_hw: reset AHB-WMAC interface on AR91xx\n\nShould fix a few stability issues\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n\n--- a/drivers/net/wireless/ath/ath9k/hw.c\n+++ b/drivers/net/wireless/ath/ath9k/hw.c\n@@ -1434,8 +1434,12 @@ static bool ath9k_hw_set_reset(struct at\n \tif (!AR_SREV_9100(ah))\n \t\tREG_WRITE(ah, AR_RC, 0);\n \n-\tif (AR_SREV_9100(ah))\n+\tif (AR_SREV_9100(ah)) {\n+\t\t/* Reset the AHB-WMAC interface */\n+\t\tif (ah->external_reset)\n+\t\t\tah->external_reset();\n \t\tudelay(50);\n+\t}\n \n \treturn true;\n }\n"
  },
  {
    "path": "package/kernel/mac80211/patches/ath9k/351-ath9k_hw-issue-external-reset-for-QCA955x.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nDate: Sat, 9 Jul 2016 15:26:44 +0200\nSubject: [PATCH] ath9k_hw: issue external reset for QCA955x\n\nThe RTC interface on the SoC needs to be reset along with the rest of\nthe WMAC.\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n\n--- a/drivers/net/wireless/ath/ath9k/hw.c\n+++ b/drivers/net/wireless/ath/ath9k/hw.c\n@@ -1311,39 +1311,56 @@ void ath9k_hw_get_delta_slope_vals(struc\n \t*coef_exponent = coef_exp - 16;\n }\n \n-/* AR9330 WAR:\n- * call external reset function to reset WMAC if:\n- * - doing a cold reset\n- * - we have pending frames in the TX queues.\n- */\n-static bool ath9k_hw_ar9330_reset_war(struct ath_hw *ah, int type)\n+static bool ath9k_hw_need_external_reset(struct ath_hw *ah, int type)\n {\n-\tint i, npend = 0;\n+\tint i;\n \n-\tfor (i = 0; i < AR_NUM_QCU; i++) {\n-\t\tnpend = ath9k_hw_numtxpending(ah, i);\n-\t\tif (npend)\n-\t\t\tbreak;\n-\t}\n-\n-\tif (ah->external_reset &&\n-\t    (npend || type == ATH9K_RESET_COLD)) {\n-\t\tint reset_err = 0;\n-\n-\t\tath_dbg(ath9k_hw_common(ah), RESET,\n-\t\t\t\"reset MAC via external reset\\n\");\n-\n-\t\treset_err = ah->external_reset();\n-\t\tif (reset_err) {\n-\t\t\tath_err(ath9k_hw_common(ah),\n-\t\t\t\t\"External reset failed, err=%d\\n\",\n-\t\t\t\treset_err);\n-\t\t\treturn false;\n+\tif (type == ATH9K_RESET_COLD)\n+\t\treturn true;\n+\n+\tif (AR_SREV_9550(ah))\n+\t\treturn true;\n+\n+\t/* AR9330 WAR:\n+\t * call external reset function to reset WMAC if:\n+\t * - doing a cold reset\n+\t * - we have pending frames in the TX queues.\n+\t */\n+\tif (AR_SREV_9330(ah)) {\n+\t\tfor (i = 0; i < AR_NUM_QCU; i++) {\n+\t\t\tif (ath9k_hw_numtxpending(ah, i))\n+\t\t\t\treturn true;\n \t\t}\n+\t}\n+\n+\treturn false;\n+}\n+\n+static bool ath9k_hw_external_reset(struct ath_hw *ah, int type)\n+{\n+\tint err;\n+\n+\tif (!ah->external_reset || !ath9k_hw_need_external_reset(ah, type))\n+\t\treturn true;\n+\n+\tath_dbg(ath9k_hw_common(ah), RESET,\n+\t\t\"reset MAC via external reset\\n\");\n \n-\t\tREG_WRITE(ah, AR_RTC_RESET, 1);\n+\terr = ah->external_reset();\n+\tif (err) {\n+\t\tath_err(ath9k_hw_common(ah),\n+\t\t\t\"External reset failed, err=%d\\n\", err);\n+\t\treturn false;\n \t}\n \n+\tif (AR_SREV_9550(ah)) {\n+\t\tREG_WRITE(ah, AR_RTC_RESET, 0);\n+\t\tudelay(10);\n+\t}\n+\n+\tREG_WRITE(ah, AR_RTC_RESET, 1);\n+\tudelay(10);\n+\n \treturn true;\n }\n \n@@ -1396,24 +1413,24 @@ static bool ath9k_hw_set_reset(struct at\n \t\t\trst_flags |= AR_RTC_RC_MAC_COLD;\n \t}\n \n-\tif (AR_SREV_9330(ah)) {\n-\t\tif (!ath9k_hw_ar9330_reset_war(ah, type))\n-\t\t\treturn false;\n-\t}\n-\n \tif (ath9k_hw_mci_is_enabled(ah))\n \t\tar9003_mci_check_gpm_offset(ah);\n \n \t/* DMA HALT added to resolve ar9300 and ar9580 bus error during\n-\t * RTC_RC reg read\n+\t * RTC_RC reg read. Also needed for AR9550 external reset\n \t */\n-\tif (AR_SREV_9300(ah) || AR_SREV_9580(ah)) {\n+\tif (AR_SREV_9300(ah) || AR_SREV_9580(ah) || AR_SREV_9550(ah)) {\n \t\tREG_SET_BIT(ah, AR_CFG, AR_CFG_HALT_REQ);\n \t\tath9k_hw_wait(ah, AR_CFG, AR_CFG_HALT_ACK, AR_CFG_HALT_ACK,\n \t\t\t      20 * AH_WAIT_TIMEOUT);\n-\t\tREG_CLR_BIT(ah, AR_CFG, AR_CFG_HALT_REQ);\n \t}\n \n+\tif (!AR_SREV_9100(ah))\n+\t\tath9k_hw_external_reset(ah, type);\n+\n+\tif (AR_SREV_9300(ah) || AR_SREV_9580(ah))\n+\t\tREG_CLR_BIT(ah, AR_CFG, AR_CFG_HALT_REQ);\n+\n \tREG_WRITE(ah, AR_RTC_RC, rst_flags);\n \n \tREGWRITE_BUFFER_FLUSH(ah);\n"
  },
  {
    "path": "package/kernel/mac80211/patches/ath9k/354-ath9k-force-rx_clear-when-disabling-rx.patch",
    "content": "From: Felix Fietkau <nbd@openwrt.org>\nDate: Sun, 7 Jun 2015 13:53:35 +0200\nSubject: [PATCH] ath9k: force rx_clear when disabling rx\n\nThis makes stopping Rx more reliable and should reduce the frequency of\nRx related DMA stop warnings. Don't use rx_clear in TX99 mode.\n\nCc: stable@vger.kernel.org\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\nSigned-off-by: Helmut Schaa <helmut.schaa@googlemail.com>\n---\n\n--- a/drivers/net/wireless/ath/ath9k/mac.c\n+++ b/drivers/net/wireless/ath/ath9k/mac.c\n@@ -678,13 +678,18 @@ void ath9k_hw_startpcureceive(struct ath\n \n \tath9k_ani_reset(ah, is_scanning);\n \n-\tREG_CLR_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));\n+\tREG_CLR_BIT(ah, AR_DIAG_SW,\n+\t\t    AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT | AR_DIAG_FORCE_RX_CLEAR);\n }\n EXPORT_SYMBOL(ath9k_hw_startpcureceive);\n \n void ath9k_hw_abortpcurecv(struct ath_hw *ah)\n {\n-\tREG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_ABORT | AR_DIAG_RX_DIS);\n+\tu32 reg = AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT;\n+\n+\tif (!IS_ENABLED(CPTCFG_ATH9K_TX99))\n+\t\treg |= AR_DIAG_FORCE_RX_CLEAR;\n+\tREG_SET_BIT(ah, AR_DIAG_SW, reg);\n \n \tath9k_hw_disable_mib_counters(ah);\n }\n"
  },
  {
    "path": "package/kernel/mac80211/patches/ath9k/356-Revert-ath9k-interpret-requested-txpower-in-EIRP-dom.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nDate: Sat, 14 May 2016 14:51:02 +0200\nSubject: [PATCH] Revert \"ath9k: interpret requested txpower in EIRP\n domain\"\n\nThis reverts commit 71f5137bf010c6faffab50c0ec15374c59c4a411.\n---\n\n--- a/drivers/net/wireless/ath/ath9k/hw.c\n+++ b/drivers/net/wireless/ath/ath9k/hw.c\n@@ -2977,7 +2977,8 @@ void ath9k_hw_apply_txpower(struct ath_h\n {\n \tstruct ath_regulatory *reg = ath9k_hw_regulatory(ah);\n \tstruct ieee80211_channel *channel;\n-\tint chan_pwr, new_pwr;\n+\tint chan_pwr, new_pwr, max_gain;\n+\tint ant_gain, ant_reduction = 0;\n \tu16 ctl = NO_CTL;\n \n \tif (!chan)\n@@ -2989,9 +2990,14 @@ void ath9k_hw_apply_txpower(struct ath_h\n \tchannel = chan->chan;\n \tchan_pwr = min_t(int, channel->max_power * 2, MAX_COMBINED_POWER);\n \tnew_pwr = min_t(int, chan_pwr, reg->power_limit);\n+\tmax_gain = chan_pwr - new_pwr + channel->max_antenna_gain * 2;\n+\n+\tant_gain = get_antenna_gain(ah, chan);\n+\tif (ant_gain > max_gain)\n+\t\tant_reduction = ant_gain - max_gain;\n \n \tah->eep_ops->set_txpower(ah, chan, ctl,\n-\t\t\t\t get_antenna_gain(ah, chan), new_pwr, test);\n+\t\t\t\t ant_reduction, new_pwr, test);\n }\n \n void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test)\n"
  },
  {
    "path": "package/kernel/mac80211/patches/ath9k/365-ath9k-adjust-tx-power-reduction-for-US-regulatory-do.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nDate: Wed, 19 Jul 2017 08:49:31 +0200\nSubject: [PATCH] ath9k: adjust tx power reduction for US regulatory\n domain\n\nFCC regulatory rules allow for up to 6 dBi antenna gain. Account for\nthis in the EEPROM based tx power reduction code.\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n\n--- a/drivers/net/wireless/ath/ath9k/hw.c\n+++ b/drivers/net/wireless/ath/ath9k/hw.c\n@@ -2996,6 +2996,10 @@ void ath9k_hw_apply_txpower(struct ath_h\n \tif (ant_gain > max_gain)\n \t\tant_reduction = ant_gain - max_gain;\n \n+\t/* FCC allows maximum antenna gain of 6 dBi */\n+\tif (reg->region == NL80211_DFS_FCC)\n+\t\tant_reduction = max_t(int, ant_reduction - 12, 0);\n+\n \tah->eep_ops->set_txpower(ah, chan, ctl,\n \t\t\t\t ant_reduction, new_pwr, test);\n }\n"
  },
  {
    "path": "package/kernel/mac80211/patches/ath9k/401-ath9k_blink_default.patch",
    "content": "--- a/drivers/net/wireless/ath/ath9k/init.c\n+++ b/drivers/net/wireless/ath/ath9k/init.c\n@@ -47,7 +47,7 @@ int ath9k_modparam_nohwcrypt;\n module_param_named(nohwcrypt, ath9k_modparam_nohwcrypt, int, 0444);\n MODULE_PARM_DESC(nohwcrypt, \"Disable hardware encryption\");\n \n-int ath9k_led_blink;\n+int ath9k_led_blink = 1;\n module_param_named(blink, ath9k_led_blink, int, 0444);\n MODULE_PARM_DESC(blink, \"Enable LED blink on activity\");\n \n"
  },
  {
    "path": "package/kernel/mac80211/patches/ath9k/410-ath9k_allow_adhoc_and_ap.patch",
    "content": "--- a/drivers/net/wireless/ath/ath9k/init.c\n+++ b/drivers/net/wireless/ath/ath9k/init.c\n@@ -826,6 +826,7 @@ static const struct ieee80211_iface_limi\n \t\t\t\t BIT(NL80211_IFTYPE_AP) },\n \t{ .max = 1,\t.types = BIT(NL80211_IFTYPE_P2P_CLIENT) |\n \t\t\t\t BIT(NL80211_IFTYPE_P2P_GO) },\n+\t{ .max = 1,\t.types = BIT(NL80211_IFTYPE_ADHOC) },\n };\n \n #ifdef CPTCFG_ATH9K_CHANNEL_CONTEXT\n"
  },
  {
    "path": "package/kernel/mac80211/patches/ath9k/450-ath9k-enabled-MFP-capability-unconditionally.patch",
    "content": "From d946085ff5a331de64e91a2e3c96b9ca79d740f5 Mon Sep 17 00:00:00 2001\nFrom: David Bauer <mail@david-bauer.net>\nDate: Mon, 15 Jun 2020 00:10:34 +0200\nSubject: [PATCH] ath9k: enabled MFP capability unconditionally\n\nath9k will already fallback on software-crypto for chipsets not\nsupporting IEEE802.11w (MFP). So advertising MFP is not dependent\non disabling HW crypto for all traffic entirely.\n\nSigned-off-by: David Bauer <mail@david-bauer.net>\n---\n drivers/net/wireless/ath/ath9k/init.c | 4 +---\n 1 file changed, 1 insertion(+), 3 deletions(-)\n\n--- a/drivers/net/wireless/ath/ath9k/init.c\n+++ b/drivers/net/wireless/ath/ath9k/init.c\n@@ -907,6 +907,7 @@ static void ath9k_set_hw_capab(struct at\n \tieee80211_hw_set(hw, HOST_BROADCAST_PS_BUFFERING);\n \tieee80211_hw_set(hw, SUPPORT_FAST_XMIT);\n \tieee80211_hw_set(hw, SUPPORTS_CLONED_SKBS);\n+\tieee80211_hw_set(hw, MFP_CAPABLE);\n \n \tif (ath9k_ps_enable)\n \t\tieee80211_hw_set(hw, SUPPORTS_PS);\n@@ -919,9 +920,6 @@ static void ath9k_set_hw_capab(struct at\n \t\t\t\tIEEE80211_RADIOTAP_MCS_HAVE_STBC;\n \t}\n \n-\tif (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || ath9k_modparam_nohwcrypt)\n-\t\tieee80211_hw_set(hw, MFP_CAPABLE);\n-\n \thw->wiphy->features |= NL80211_FEATURE_ACTIVE_MONITOR |\n \t\t\t       NL80211_FEATURE_AP_MODE_CHAN_WIDTH_CHANGE |\n \t\t\t       NL80211_FEATURE_P2P_GO_CTWIN;\n"
  },
  {
    "path": "package/kernel/mac80211/patches/ath9k/500-ath9k_eeprom_debugfs.patch",
    "content": "--- a/drivers/net/wireless/ath/ath9k/debug.c\n+++ b/drivers/net/wireless/ath/ath9k/debug.c\n@@ -1364,6 +1364,53 @@ void ath9k_deinit_debug(struct ath_softc\n \tath9k_cmn_spectral_deinit_debug(&sc->spec_priv);\n }\n \n+static ssize_t read_file_eeprom(struct file *file, char __user *user_buf,\n+\t\t\t     size_t count, loff_t *ppos)\n+{\n+\tstruct ath_softc *sc = file->private_data;\n+\tstruct ath_hw *ah = sc->sc_ah;\n+\tstruct ath_common *common = ath9k_hw_common(ah);\n+\tint bytes = 0;\n+\tint pos = *ppos;\n+\tint size = 4096;\n+\tu16 val;\n+\tint i;\n+\n+\tif (AR_SREV_9300_20_OR_LATER(ah))\n+\t\tsize = 16384;\n+\n+\tif (*ppos < 0)\n+\t\treturn -EINVAL;\n+\n+\tif (count > size - *ppos)\n+\t\tcount = size - *ppos;\n+\n+\tfor (i = *ppos / 2; count > 0; count -= bytes, *ppos += bytes, i++) {\n+\t\tvoid *from = &val;\n+\n+\t\tif (!common->bus_ops->eeprom_read(common, i, &val))\n+\t\t\tval = 0xffff;\n+\n+\t\tif (*ppos % 2) {\n+\t\t\tfrom++;\n+\t\t\tbytes = 1;\n+\t\t} else if (count == 1) {\n+\t\t\tbytes = 1;\n+\t\t} else {\n+\t\t\tbytes = 2;\n+\t\t}\n+\t\tcopy_to_user(user_buf, from, bytes);\n+\t\tuser_buf += bytes;\n+\t}\n+\treturn *ppos - pos;\n+}\n+\n+static const struct file_operations fops_eeprom = {\n+\t.read = read_file_eeprom,\n+\t.open = simple_open,\n+\t.owner = THIS_MODULE\n+};\n+\n int ath9k_init_debug(struct ath_hw *ah)\n {\n \tstruct ath_common *common = ath9k_hw_common(ah);\n@@ -1383,6 +1430,8 @@ int ath9k_init_debug(struct ath_hw *ah)\n \tath9k_tx99_init_debug(sc);\n \tath9k_cmn_spectral_init_debug(&sc->spec_priv, sc->debug.debugfs_phy);\n \n+\tdebugfs_create_file(\"eeprom\", S_IRUSR, sc->debug.debugfs_phy, sc,\n+\t\t\t    &fops_eeprom);\n \tdebugfs_create_devm_seqfile(sc->dev, \"dma\", sc->debug.debugfs_phy,\n \t\t\t\t    read_file_dma);\n \tdebugfs_create_devm_seqfile(sc->dev, \"interrupt\", sc->debug.debugfs_phy,\n"
  },
  {
    "path": "package/kernel/mac80211/patches/ath9k/501-ath9k_ahb_init.patch",
    "content": "--- a/drivers/net/wireless/ath/ath9k/init.c\n+++ b/drivers/net/wireless/ath/ath9k/init.c\n@@ -1122,25 +1122,25 @@ static int __init ath9k_init(void)\n {\n \tint error;\n \n-\terror = ath_pci_init();\n+\terror = ath_ahb_init();\n \tif (error < 0) {\n-\t\tpr_err(\"No PCI devices found, driver not installed\\n\");\n \t\terror = -ENODEV;\n \t\tgoto err_out;\n \t}\n \n-\terror = ath_ahb_init();\n+\terror = ath_pci_init();\n \tif (error < 0) {\n+\t\tpr_err(\"No PCI devices found, driver not installed\\n\");\n \t\terror = -ENODEV;\n-\t\tgoto err_pci_exit;\n+\t\tgoto err_ahb_exit;\n \t}\n \n \tdmi_check_system(ath9k_quirks);\n \n \treturn 0;\n \n- err_pci_exit:\n-\tath_pci_exit();\n+ err_ahb_exit:\n+\tath_ahb_exit();\n  err_out:\n \treturn error;\n }\n"
  },
  {
    "path": "package/kernel/mac80211/patches/ath9k/510-ath9k_intr_mitigation_tweak.patch",
    "content": "--- a/drivers/net/wireless/ath/ath9k/hw.c\n+++ b/drivers/net/wireless/ath/ath9k/hw.c\n@@ -402,13 +402,8 @@ static void ath9k_hw_init_config(struct\n \n \tah->config.rx_intr_mitigation = true;\n \n-\tif (AR_SREV_9300_20_OR_LATER(ah)) {\n-\t\tah->config.rimt_last = 500;\n-\t\tah->config.rimt_first = 2000;\n-\t} else {\n-\t\tah->config.rimt_last = 250;\n-\t\tah->config.rimt_first = 700;\n-\t}\n+\tah->config.rimt_last = 250;\n+\tah->config.rimt_first = 500;\n \n \tif (AR_SREV_9462(ah) || AR_SREV_9565(ah))\n \t\tah->config.pll_pwrsave = 7;\n"
  },
  {
    "path": "package/kernel/mac80211/patches/ath9k/511-ath9k_reduce_rxbuf.patch",
    "content": "--- a/drivers/net/wireless/ath/ath9k/ath9k.h\n+++ b/drivers/net/wireless/ath/ath9k/ath9k.h\n@@ -88,7 +88,7 @@ int ath_descdma_setup(struct ath_softc *\n \t\t(_l) &= ((_sz) - 1);\t\t\\\n \t} while (0)\n \n-#define ATH_RXBUF               512\n+#define ATH_RXBUF               256\n #define ATH_TXBUF               512\n #define ATH_TXBUF_RESERVE       5\n #define ATH_TXMAXTRY            13\n"
  },
  {
    "path": "package/kernel/mac80211/patches/ath9k/512-ath9k_channelbw_debugfs.patch",
    "content": "--- a/drivers/net/wireless/ath/ath9k/debug.c\n+++ b/drivers/net/wireless/ath/ath9k/debug.c\n@@ -1411,6 +1411,52 @@ static const struct file_operations fops\n \t.owner = THIS_MODULE\n };\n \n+\n+static ssize_t read_file_chan_bw(struct file *file, char __user *user_buf,\n+\t\t\t     size_t count, loff_t *ppos)\n+{\n+\tstruct ath_softc *sc = file->private_data;\n+\tstruct ath_common *common = ath9k_hw_common(sc->sc_ah);\n+\tchar buf[32];\n+\tunsigned int len;\n+\n+\tlen = sprintf(buf, \"0x%08x\\n\", common->chan_bw);\n+\treturn simple_read_from_buffer(user_buf, count, ppos, buf, len);\n+}\n+\n+static ssize_t write_file_chan_bw(struct file *file, const char __user *user_buf,\n+\t\t\t     size_t count, loff_t *ppos)\n+{\n+\tstruct ath_softc *sc = file->private_data;\n+\tstruct ath_common *common = ath9k_hw_common(sc->sc_ah);\n+\tunsigned long chan_bw;\n+\tchar buf[32];\n+\tssize_t len;\n+\n+\tlen = min(count, sizeof(buf) - 1);\n+\tif (copy_from_user(buf, user_buf, len))\n+\t\treturn -EFAULT;\n+\n+\tbuf[len] = '\\0';\n+\tif (kstrtoul(buf, 0, &chan_bw))\n+\t\treturn -EINVAL;\n+\n+\tcommon->chan_bw = chan_bw;\n+\tif (!test_bit(ATH_OP_INVALID, &common->op_flags))\n+\t\tath9k_ops.config(sc->hw, IEEE80211_CONF_CHANGE_CHANNEL);\n+\n+\treturn count;\n+}\n+\n+static const struct file_operations fops_chanbw = {\n+\t.read = read_file_chan_bw,\n+\t.write = write_file_chan_bw,\n+\t.open = simple_open,\n+\t.owner = THIS_MODULE,\n+\t.llseek = default_llseek,\n+};\n+\n+\n int ath9k_init_debug(struct ath_hw *ah)\n {\n \tstruct ath_common *common = ath9k_hw_common(ah);\n@@ -1432,6 +1478,8 @@ int ath9k_init_debug(struct ath_hw *ah)\n \n \tdebugfs_create_file(\"eeprom\", S_IRUSR, sc->debug.debugfs_phy, sc,\n \t\t\t    &fops_eeprom);\n+\tdebugfs_create_file(\"chanbw\", S_IRUSR | S_IWUSR, sc->debug.debugfs_phy,\n+\t\t\t    sc, &fops_chanbw);\n \tdebugfs_create_devm_seqfile(sc->dev, \"dma\", sc->debug.debugfs_phy,\n \t\t\t\t    read_file_dma);\n \tdebugfs_create_devm_seqfile(sc->dev, \"interrupt\", sc->debug.debugfs_phy,\n--- a/drivers/net/wireless/ath/ath.h\n+++ b/drivers/net/wireless/ath/ath.h\n@@ -149,6 +149,7 @@ struct ath_common {\n \tint debug_mask;\n \tenum ath_device_state state;\n \tunsigned long op_flags;\n+\tu32 chan_bw;\n \n \tstruct ath_ani ani;\n \n--- a/drivers/net/wireless/ath/ath9k/common.c\n+++ b/drivers/net/wireless/ath/ath9k/common.c\n@@ -297,11 +297,13 @@ EXPORT_SYMBOL(ath9k_cmn_get_hw_crypto_ke\n /*\n  * Update internal channel flags.\n  */\n-static void ath9k_cmn_update_ichannel(struct ath9k_channel *ichan,\n+static void ath9k_cmn_update_ichannel(struct ath_common *common,\n+\t\t\t\t      struct ath9k_channel *ichan,\n \t\t\t\t      struct cfg80211_chan_def *chandef)\n {\n \tstruct ieee80211_channel *chan = chandef->chan;\n \tu16 flags = 0;\n+\tint width;\n \n \tichan->channel = chan->center_freq;\n \tichan->chan = chan;\n@@ -309,7 +311,19 @@ static void ath9k_cmn_update_ichannel(st\n \tif (chan->band == NL80211_BAND_5GHZ)\n \t\tflags |= CHANNEL_5GHZ;\n \n-\tswitch (chandef->width) {\n+\tswitch (common->chan_bw) {\n+\tcase 5:\n+\t\twidth = NL80211_CHAN_WIDTH_5;\n+\t\tbreak;\n+\tcase 10:\n+\t\twidth = NL80211_CHAN_WIDTH_10;\n+\t\tbreak;\n+\tdefault:\n+\t\twidth = chandef->width;\n+\t\tbreak;\n+\t}\n+\n+\tswitch (width) {\n \tcase NL80211_CHAN_WIDTH_5:\n \t\tflags |= CHANNEL_QUARTER;\n \t\tbreak;\n@@ -342,10 +356,11 @@ struct ath9k_channel *ath9k_cmn_get_chan\n \t\t\t\t\t    struct cfg80211_chan_def *chandef)\n {\n \tstruct ieee80211_channel *curchan = chandef->chan;\n+\tstruct ath_common *common = ath9k_hw_common(ah);\n \tstruct ath9k_channel *channel;\n \n \tchannel = &ah->channels[curchan->hw_value];\n-\tath9k_cmn_update_ichannel(channel, chandef);\n+\tath9k_cmn_update_ichannel(common, channel, chandef);\n \n \treturn channel;\n }\n"
  },
  {
    "path": "package/kernel/mac80211/patches/ath9k/513-ath9k_add_pci_ids.patch",
    "content": "--- a/drivers/net/wireless/ath/ath9k/hw.c\n+++ b/drivers/net/wireless/ath/ath9k/hw.c\n@@ -662,6 +662,7 @@ int ath9k_hw_init(struct ath_hw *ah)\n \n \t/* These are all the AR5008/AR9001/AR9002/AR9003 hardware family of chipsets */\n \tswitch (ah->hw_version.devid) {\n+\tcase AR9300_DEVID_INVALID:\n \tcase AR5416_DEVID_PCI:\n \tcase AR5416_DEVID_PCIE:\n \tcase AR5416_AR9100_DEVID:\n--- a/drivers/net/wireless/ath/ath9k/hw.h\n+++ b/drivers/net/wireless/ath/ath9k/hw.h\n@@ -36,6 +36,7 @@\n \n #define ATHEROS_VENDOR_ID\t0x168c\n \n+#define AR9300_DEVID_INVALID\t0xabcd\n #define AR5416_DEVID_PCI\t0x0023\n #define AR5416_DEVID_PCIE\t0x0024\n #define AR9160_DEVID_PCI\t0x0027\n--- a/drivers/net/wireless/ath/ath9k/pci.c\n+++ b/drivers/net/wireless/ath/ath9k/pci.c\n@@ -774,6 +774,7 @@ static const struct pci_device_id ath_pc\n \t  .driver_data = ATH9K_PCI_BT_ANT_DIV },\n #endif\n \n+\t{ PCI_VDEVICE(ATHEROS, 0xabcd) }, /* PCI-E  internal chip default ID */\n \t{ 0 }\n };\n \n"
  },
  {
    "path": "package/kernel/mac80211/patches/ath9k/530-ath9k_extra_leds.patch",
    "content": "--- a/drivers/net/wireless/ath/ath9k/ath9k.h\n+++ b/drivers/net/wireless/ath/ath9k/ath9k.h\n@@ -843,6 +843,9 @@ static inline int ath9k_dump_btcoex(stru\n #ifdef CPTCFG_MAC80211_LEDS\n void ath_init_leds(struct ath_softc *sc);\n void ath_deinit_leds(struct ath_softc *sc);\n+int ath_create_gpio_led(struct ath_softc *sc, int gpio, const char *name,\n+\t\t\tconst char *trigger, bool active_low);\n+\n #else\n static inline void ath_init_leds(struct ath_softc *sc)\n {\n@@ -979,6 +982,13 @@ void ath_ant_comb_scan(struct ath_softc\n \n #define ATH9K_NUM_CHANCTX  2 /* supports 2 operating channels */\n \n+struct ath_led {\n+\tstruct list_head list;\n+\tstruct ath_softc *sc;\n+\tconst struct gpio_led *gpio;\n+\tstruct led_classdev cdev;\n+};\n+\n struct ath_softc {\n \tstruct ieee80211_hw *hw;\n \tstruct device *dev;\n@@ -1032,9 +1042,8 @@ struct ath_softc {\n \tspinlock_t chan_lock;\n \n #ifdef CPTCFG_MAC80211_LEDS\n-\tbool led_registered;\n-\tchar led_name[32];\n-\tstruct led_classdev led_cdev;\n+\tconst char *led_default_trigger;\n+\tstruct list_head leds;\n #endif\n \n #ifdef CPTCFG_ATH9K_DEBUGFS\n--- a/drivers/net/wireless/ath/ath9k/gpio.c\n+++ b/drivers/net/wireless/ath/ath9k/gpio.c\n@@ -39,61 +39,111 @@ static void ath_fill_led_pin(struct ath_\n \t\telse\n \t\t\tah->led_pin = ATH_LED_PIN_DEF;\n \t}\n+}\n+\n+static void ath_led_brightness(struct led_classdev *led_cdev,\n+\t\t\t       enum led_brightness brightness)\n+{\n+\tstruct ath_led *led = container_of(led_cdev, struct ath_led, cdev);\n+\tstruct ath_softc *sc = led->sc;\n+\n+\tath9k_ps_wakeup(sc);\n+\tath9k_hw_set_gpio(sc->sc_ah, led->gpio->gpio,\n+\t\t\t  (brightness != LED_OFF) ^ led->gpio->active_low);\n+\tath9k_ps_restore(sc);\n+}\n+\n+static int ath_add_led(struct ath_softc *sc, struct ath_led *led)\n+{\n+\tconst struct gpio_led *gpio = led->gpio;\n+\tint ret;\n+\n+\tled->cdev.name = gpio->name;\n+\tled->cdev.default_trigger = gpio->default_trigger;\n+\tled->cdev.brightness_set = ath_led_brightness;\n+\n+\tret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->cdev);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\tled->sc = sc;\n+\tlist_add(&led->list, &sc->leds);\n \n \t/* Configure gpio for output */\n-\tath9k_hw_gpio_request_out(ah, ah->led_pin, \"ath9k-led\",\n+\tath9k_hw_gpio_request_out(sc->sc_ah, gpio->gpio, gpio->name,\n \t\t\t\t  AR_GPIO_OUTPUT_MUX_AS_OUTPUT);\n \n-\t/* LED off, active low */\n-\tath9k_hw_set_gpio(ah, ah->led_pin, ah->config.led_active_high ? 0 : 1);\n+\t/* LED off */\n+\tath9k_hw_set_gpio(sc->sc_ah, gpio->gpio, gpio->active_low);\n+\n+\treturn 0;\n }\n \n-static void ath_led_brightness(struct led_classdev *led_cdev,\n-\t\t\t       enum led_brightness brightness)\n+int ath_create_gpio_led(struct ath_softc *sc, int gpio_num, const char *name,\n+\t\t\tconst char *trigger, bool active_low)\n {\n-\tstruct ath_softc *sc = container_of(led_cdev, struct ath_softc, led_cdev);\n-\tu32 val = (brightness == LED_OFF);\n+\tstruct ath_led *led;\n+\tstruct gpio_led *gpio;\n+\tchar *_name;\n+\tint ret;\n \n-\tif (sc->sc_ah->config.led_active_high)\n-\t\tval = !val;\n+\tled = kzalloc(sizeof(*led) + sizeof(*gpio) + strlen(name) + 1,\n+\t\t      GFP_KERNEL);\n+\tif (!led)\n+\t\treturn -ENOMEM;\n+\n+\tled->gpio = gpio = (struct gpio_led *) (led + 1);\n+\t_name = (char *) (led->gpio + 1);\n+\n+\tstrcpy(_name, name);\n+\tgpio->name = _name;\n+\tgpio->gpio = gpio_num;\n+\tgpio->active_low = active_low;\n+\tgpio->default_trigger = trigger;\n+\n+\tret = ath_add_led(sc, led);\n+\tif (unlikely(ret < 0))\n+\t\tkfree(led);\n \n-\tath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, val);\n+\treturn ret;\n }\n \n void ath_deinit_leds(struct ath_softc *sc)\n {\n-\tif (!sc->led_registered)\n-\t\treturn;\n+\tstruct ath_led *led;\n \n-\tath_led_brightness(&sc->led_cdev, LED_OFF);\n-\tled_classdev_unregister(&sc->led_cdev);\n-\n-\tath9k_hw_gpio_free(sc->sc_ah, sc->sc_ah->led_pin);\n+\twhile (!list_empty(&sc->leds)) {\n+\t\tled = list_first_entry(&sc->leds, struct ath_led, list);\n+\t\tlist_del(&led->list);\n+\t\tath_led_brightness(&led->cdev, LED_OFF);\n+\t\tled_classdev_unregister(&led->cdev);\n+\t\tath9k_hw_gpio_free(sc->sc_ah, led->gpio->gpio);\n+\t\tkfree(led);\n+\t}\n }\n \n void ath_init_leds(struct ath_softc *sc)\n {\n-\tint ret;\n+\tchar led_name[32];\n+\tconst char *trigger;\n+\n+\tINIT_LIST_HEAD(&sc->leds);\n \n \tif (AR_SREV_9100(sc->sc_ah))\n \t\treturn;\n \n \tath_fill_led_pin(sc);\n \n-\tif (!ath9k_led_blink)\n-\t\tsc->led_cdev.default_trigger =\n-\t\t\tieee80211_get_radio_led_name(sc->hw);\n-\n-\tsnprintf(sc->led_name, sizeof(sc->led_name),\n-\t\t\"ath9k-%s\", wiphy_name(sc->hw->wiphy));\n-\tsc->led_cdev.name = sc->led_name;\n-\tsc->led_cdev.brightness_set = ath_led_brightness;\n+\tsnprintf(led_name, sizeof(led_name), \"ath9k-%s\",\n+\t\t wiphy_name(sc->hw->wiphy));\n \n-\tret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &sc->led_cdev);\n-\tif (ret < 0)\n-\t\treturn;\n+\tif (ath9k_led_blink)\n+\t\ttrigger = sc->led_default_trigger;\n+\telse\n+\t\ttrigger = ieee80211_get_radio_led_name(sc->hw);\n \n-\tsc->led_registered = true;\n+\tath_create_gpio_led(sc, sc->sc_ah->led_pin, led_name, trigger,\n+\t\t\t   !sc->sc_ah->config.led_active_high);\n }\n #endif\n \n--- a/drivers/net/wireless/ath/ath9k/init.c\n+++ b/drivers/net/wireless/ath/ath9k/init.c\n@@ -1032,7 +1032,7 @@ int ath9k_init_device(u16 devid, struct\n \n #ifdef CPTCFG_MAC80211_LEDS\n \t/* must be initialized before ieee80211_register_hw */\n-\tsc->led_cdev.default_trigger = ieee80211_create_tpt_led_trigger(sc->hw,\n+\tsc->led_default_trigger = ieee80211_create_tpt_led_trigger(sc->hw,\n \t\tIEEE80211_TPT_LEDTRIG_FL_RADIO, ath9k_tpt_blink,\n \t\tARRAY_SIZE(ath9k_tpt_blink));\n #endif\n--- a/drivers/net/wireless/ath/ath9k/debug.c\n+++ b/drivers/net/wireless/ath/ath9k/debug.c\n@@ -1456,6 +1456,61 @@ static const struct file_operations fops\n \t.llseek = default_llseek,\n };\n \n+#ifdef CONFIG_MAC80211_LEDS\n+\n+static ssize_t write_file_gpio_led(struct file *file, const char __user *ubuf,\n+\t\t\t\t   size_t count, loff_t *ppos)\n+{\n+\tstruct ath_softc *sc = file->private_data;\n+\tchar buf[32], *str, *name, *c;\n+\tssize_t len;\n+\tunsigned int gpio;\n+\tbool active_low = false;\n+\n+\tlen = min(count, sizeof(buf) - 1);\n+\tif (copy_from_user(buf, ubuf, len))\n+\t\treturn -EFAULT;\n+\n+\tbuf[len] = '\\0';\n+\tname = strchr(buf, ',');\n+\tif (!name)\n+\t\treturn -EINVAL;\n+\n+\t*(name++) = 0;\n+\tif (!*name)\n+\t\treturn -EINVAL;\n+\n+\tc = strchr(name, '\\n');\n+\tif (c)\n+\t\t*c = 0;\n+\n+\tstr = buf;\n+\tif (*str == '!') {\n+\t\tstr++;\n+\t\tactive_low = true;\n+\t}\n+\n+\tif (kstrtouint(str, 0, &gpio) < 0)\n+\t\treturn -EINVAL;\n+\n+\tif (gpio >= sc->sc_ah->caps.num_gpio_pins)\n+\t\treturn -EINVAL;\n+\n+\tif (ath_create_gpio_led(sc, gpio, name, NULL, active_low) < 0)\n+\t\treturn -EINVAL;\n+\n+\treturn count;\n+}\n+\n+static const struct file_operations fops_gpio_led = {\n+\t.write = write_file_gpio_led,\n+\t.open = simple_open,\n+\t.owner = THIS_MODULE,\n+\t.llseek = default_llseek,\n+};\n+\n+#endif\n+\n \n int ath9k_init_debug(struct ath_hw *ah)\n {\n@@ -1480,6 +1535,10 @@ int ath9k_init_debug(struct ath_hw *ah)\n \t\t\t    &fops_eeprom);\n \tdebugfs_create_file(\"chanbw\", S_IRUSR | S_IWUSR, sc->debug.debugfs_phy,\n \t\t\t    sc, &fops_chanbw);\n+#ifdef CONFIG_MAC80211_LEDS\n+\tdebugfs_create_file(\"gpio_led\", S_IWUSR,\n+\t\t\t   sc->debug.debugfs_phy, sc, &fops_gpio_led);\n+#endif\n \tdebugfs_create_devm_seqfile(sc->dev, \"dma\", sc->debug.debugfs_phy,\n \t\t\t\t    read_file_dma);\n \tdebugfs_create_devm_seqfile(sc->dev, \"interrupt\", sc->debug.debugfs_phy,\n"
  },
  {
    "path": "package/kernel/mac80211/patches/ath9k/531-ath9k_extra_platform_leds.patch",
    "content": "--- a/include/linux/ath9k_platform.h\n+++ b/include/linux/ath9k_platform.h\n@@ -46,6 +46,9 @@ struct ath9k_platform_data {\n \tint (*external_reset)(void);\n \n \tbool use_eeprom;\n+\n+\tint num_leds;\n+\tconst struct gpio_led *leds;\n };\n \n #endif /* _LINUX_ATH9K_PLATFORM_H */\n--- a/drivers/net/wireless/ath/ath9k/gpio.c\n+++ b/drivers/net/wireless/ath/ath9k/gpio.c\n@@ -15,6 +15,7 @@\n  */\n \n #include \"ath9k.h\"\n+#include <linux/ath9k_platform.h>\n \n /********************************/\n /*\t LED functions\t\t*/\n@@ -108,6 +109,24 @@ int ath_create_gpio_led(struct ath_softc\n \treturn ret;\n }\n \n+static int ath_create_platform_led(struct ath_softc *sc,\n+\t\t\t\t   const struct gpio_led *gpio)\n+{\n+\tstruct ath_led *led;\n+\tint ret;\n+\n+\tled = kzalloc(sizeof(*led), GFP_KERNEL);\n+\tif (!led)\n+\t\treturn -ENOMEM;\n+\n+\tled->gpio = gpio;\n+\tret = ath_add_led(sc, led);\n+\tif (ret < 0)\n+\t\tkfree(led);\n+\n+\treturn ret;\n+}\n+\n void ath_deinit_leds(struct ath_softc *sc)\n {\n \tstruct ath_led *led;\n@@ -124,8 +143,10 @@ void ath_deinit_leds(struct ath_softc *s\n \n void ath_init_leds(struct ath_softc *sc)\n {\n+\tstruct ath9k_platform_data *pdata = sc->dev->platform_data;\n \tchar led_name[32];\n \tconst char *trigger;\n+\tint i;\n \n \tINIT_LIST_HEAD(&sc->leds);\n \n@@ -134,6 +155,17 @@ void ath_init_leds(struct ath_softc *sc)\n \n \tath_fill_led_pin(sc);\n \n+\tif (pdata && pdata->leds && pdata->num_leds)\n+\t\tfor (i = 0; i < pdata->num_leds; i++) {\n+\t\t\tif (pdata->leds[i].gpio == sc->sc_ah->led_pin)\n+\t\t\t\tsc->sc_ah->led_pin = -1;\n+\n+\t\t\tath_create_platform_led(sc, &pdata->leds[i]);\n+\t\t}\n+\n+\tif (sc->sc_ah->led_pin < 0)\n+\t\treturn;\n+\n \tsnprintf(led_name, sizeof(led_name), \"ath9k-%s\",\n \t\t wiphy_name(sc->hw->wiphy));\n \n"
  },
  {
    "path": "package/kernel/mac80211/patches/ath9k/540-ath9k_reduce_ani_interval.patch",
    "content": "--- a/drivers/net/wireless/ath/ath9k/ani.h\n+++ b/drivers/net/wireless/ath/ath9k/ani.h\n@@ -42,7 +42,7 @@\n #define ATH9K_ANI_PERIOD                  300\n \n /* in ms */\n-#define ATH9K_ANI_POLLINTERVAL            1000\n+#define ATH9K_ANI_POLLINTERVAL            300\n \n #define ATH9K_SIG_FIRSTEP_SETTING_MIN     0\n #define ATH9K_SIG_FIRSTEP_SETTING_MAX     20\n"
  },
  {
    "path": "package/kernel/mac80211/patches/ath9k/542-ath9k_debugfs_diag.patch",
    "content": "--- a/drivers/net/wireless/ath/ath9k/debug.c\n+++ b/drivers/net/wireless/ath/ath9k/debug.c\n@@ -1512,6 +1512,50 @@ static const struct file_operations fops\n #endif\n \n \n+static ssize_t read_file_diag(struct file *file, char __user *user_buf,\n+\t\t\t     size_t count, loff_t *ppos)\n+{\n+\tstruct ath_softc *sc = file->private_data;\n+\tstruct ath_hw *ah = sc->sc_ah;\n+\tchar buf[32];\n+\tunsigned int len;\n+\n+\tlen = sprintf(buf, \"0x%08lx\\n\", ah->diag);\n+\treturn simple_read_from_buffer(user_buf, count, ppos, buf, len);\n+}\n+\n+static ssize_t write_file_diag(struct file *file, const char __user *user_buf,\n+\t\t\t     size_t count, loff_t *ppos)\n+{\n+\tstruct ath_softc *sc = file->private_data;\n+\tstruct ath_hw *ah = sc->sc_ah;\n+\tunsigned long diag;\n+\tchar buf[32];\n+\tssize_t len;\n+\n+\tlen = min(count, sizeof(buf) - 1);\n+\tif (copy_from_user(buf, user_buf, len))\n+\t\treturn -EFAULT;\n+\n+\tbuf[len] = '\\0';\n+\tif (kstrtoul(buf, 0, &diag))\n+\t\treturn -EINVAL;\n+\n+\tah->diag = diag;\n+\tath9k_hw_update_diag(ah);\n+\n+\treturn count;\n+}\n+\n+static const struct file_operations fops_diag = {\n+\t.read = read_file_diag,\n+\t.write = write_file_diag,\n+\t.open = simple_open,\n+\t.owner = THIS_MODULE,\n+\t.llseek = default_llseek,\n+};\n+\n+\n int ath9k_init_debug(struct ath_hw *ah)\n {\n \tstruct ath_common *common = ath9k_hw_common(ah);\n@@ -1539,6 +1583,8 @@ int ath9k_init_debug(struct ath_hw *ah)\n \tdebugfs_create_file(\"gpio_led\", S_IWUSR,\n \t\t\t   sc->debug.debugfs_phy, sc, &fops_gpio_led);\n #endif\n+\tdebugfs_create_file(\"diag\", S_IRUSR | S_IWUSR, sc->debug.debugfs_phy,\n+\t\t\t    sc, &fops_diag);\n \tdebugfs_create_devm_seqfile(sc->dev, \"dma\", sc->debug.debugfs_phy,\n \t\t\t\t    read_file_dma);\n \tdebugfs_create_devm_seqfile(sc->dev, \"interrupt\", sc->debug.debugfs_phy,\n--- a/drivers/net/wireless/ath/ath9k/hw.h\n+++ b/drivers/net/wireless/ath/ath9k/hw.h\n@@ -522,6 +522,12 @@ enum {\n \tATH9K_RESET_COLD,\n };\n \n+enum {\n+\tATH_DIAG_DISABLE_RX,\n+\tATH_DIAG_DISABLE_TX,\n+\tATH_DIAG_TRIGGER_ERROR,\n+};\n+\n struct ath9k_hw_version {\n \tu32 magic;\n \tu16 devid;\n@@ -810,6 +816,8 @@ struct ath_hw {\n \tu32 ah_flags;\n \ts16 nf_override;\n \n+\tunsigned long diag;\n+\n \tbool reset_power_on;\n \tbool htc_reset_init;\n \n@@ -1077,6 +1085,7 @@ void ath9k_hw_check_nav(struct ath_hw *a\n bool ath9k_hw_check_alive(struct ath_hw *ah);\n \n bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode);\n+void ath9k_hw_update_diag(struct ath_hw *ah);\n \n /* Generic hw timer primitives */\n struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,\n--- a/drivers/net/wireless/ath/ath9k/hw.c\n+++ b/drivers/net/wireless/ath/ath9k/hw.c\n@@ -1881,6 +1881,20 @@ u32 ath9k_hw_get_tsf_offset(struct times\n }\n EXPORT_SYMBOL(ath9k_hw_get_tsf_offset);\n \n+void ath9k_hw_update_diag(struct ath_hw *ah)\n+{\n+\tif (test_bit(ATH_DIAG_DISABLE_RX, &ah->diag))\n+\t\tREG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS);\n+\telse\n+\t\tREG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS);\n+\n+\tif (test_bit(ATH_DIAG_DISABLE_TX, &ah->diag))\n+\t\tREG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_LOOP_BACK);\n+\telse\n+\t\tREG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_LOOP_BACK);\n+}\n+EXPORT_SYMBOL(ath9k_hw_update_diag);\n+\n int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,\n \t\t   struct ath9k_hw_cal_data *caldata, bool fastcc)\n {\n@@ -2089,6 +2103,7 @@ int ath9k_hw_reset(struct ath_hw *ah, st\n \t\tar9003_hw_disable_phy_restart(ah);\n \n \tath9k_hw_apply_gpio_override(ah);\n+\tath9k_hw_update_diag(ah);\n \n \tif (AR_SREV_9565(ah) && common->bt_ant_diversity)\n \t\tREG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV, AR_BTCOEX_WL_LNADIV_FORCE_ON);\n--- a/drivers/net/wireless/ath/ath9k/main.c\n+++ b/drivers/net/wireless/ath/ath9k/main.c\n@@ -538,6 +538,11 @@ irqreturn_t ath_isr(int irq, void *dev)\n \t\treturn IRQ_HANDLED;\n \t}\n \n+\tif (test_bit(ATH_DIAG_TRIGGER_ERROR, &ah->diag)) {\n+\t\tstatus |= ATH9K_INT_FATAL;\n+\t\tclear_bit(ATH_DIAG_TRIGGER_ERROR, &ah->diag);\n+\t}\n+\n \t/*\n \t * If there are no status bits set, then this interrupt was not\n \t * for me (should have been caught above).\n"
  },
  {
    "path": "package/kernel/mac80211/patches/ath9k/543-ath9k_entropy_from_adc.patch",
    "content": "--- a/drivers/net/wireless/ath/ath9k/hw.h\n+++ b/drivers/net/wireless/ath/ath9k/hw.h\n@@ -723,6 +723,7 @@ struct ath_spec_scan {\n  * @config_pci_powersave:\n  * @calibrate: periodic calibration for NF, ANI, IQ, ADC gain, ADC-DC\n  *\n+ * @get_adc_entropy: get entropy from the raw ADC I/Q output\n  * @spectral_scan_config: set parameters for spectral scan and enable/disable it\n  * @spectral_scan_trigger: trigger a spectral scan run\n  * @spectral_scan_wait: wait for a spectral scan run to finish\n@@ -745,6 +746,7 @@ struct ath_hw_ops {\n \t\t\tstruct ath_hw_antcomb_conf *antconf);\n \tvoid (*antdiv_comb_conf_set)(struct ath_hw *ah,\n \t\t\tstruct ath_hw_antcomb_conf *antconf);\n+\tvoid (*get_adc_entropy)(struct ath_hw *ah, u8 *buf, size_t len);\n \tvoid (*spectral_scan_config)(struct ath_hw *ah,\n \t\t\t\t     struct ath_spec_scan *param);\n \tvoid (*spectral_scan_trigger)(struct ath_hw *ah);\n--- a/drivers/net/wireless/ath/ath9k/ar9003_phy.c\n+++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.c\n@@ -1927,6 +1927,26 @@ void ar9003_hw_init_rate_txpower(struct\n \t}\n }\n \n+static void ar9003_hw_get_adc_entropy(struct ath_hw *ah, u8 *buf, size_t len)\n+{\n+\tint i, j;\n+\n+\tREG_RMW_FIELD(ah, AR_PHY_TEST, AR_PHY_TEST_BBB_OBS_SEL, 1);\n+\tREG_CLR_BIT(ah, AR_PHY_TEST, AR_PHY_TEST_RX_OBS_SEL_BIT5);\n+\tREG_RMW_FIELD(ah, AR_PHY_TEST_CTL_STATUS, AR_PHY_TEST_CTL_RX_OBS_SEL, 0);\n+\n+\tmemset(buf, 0, len);\n+\tfor (i = 0; i < len; i++) {\n+\t\tfor (j = 0; j < 4; j++) {\n+\t\t\tu32 regval = REG_READ(ah, AR_PHY_TST_ADC);\n+\n+\t\t\tbuf[i] <<= 2;\n+\t\t\tbuf[i] |= (regval & 1) | ((regval & BIT(10)) >> 9);\n+\t\t\tudelay(1);\n+\t\t}\n+\t}\n+}\n+\n void ar9003_hw_attach_phy_ops(struct ath_hw *ah)\n {\n \tstruct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);\n@@ -1963,6 +1983,7 @@ void ar9003_hw_attach_phy_ops(struct ath\n \tpriv_ops->set_radar_params = ar9003_hw_set_radar_params;\n \tpriv_ops->fast_chan_change = ar9003_hw_fast_chan_change;\n \n+\tops->get_adc_entropy = ar9003_hw_get_adc_entropy;\n \tops->antdiv_comb_conf_get = ar9003_hw_antdiv_comb_conf_get;\n \tops->antdiv_comb_conf_set = ar9003_hw_antdiv_comb_conf_set;\n \tops->spectral_scan_config = ar9003_hw_spectral_scan_config;\n--- a/drivers/net/wireless/ath/ath9k/init.c\n+++ b/drivers/net/wireless/ath/ath9k/init.c\n@@ -814,7 +814,8 @@ static void ath9k_init_txpower_limits(st\n \tif (ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ)\n \t\tath9k_init_band_txpower(sc, NL80211_BAND_5GHZ);\n \n-\tah->curchan = curchan;\n+\tif (curchan)\n+\t\tah->curchan = curchan;\n }\n \n static const struct ieee80211_iface_limit if_limits[] = {\n@@ -992,6 +993,18 @@ static void ath9k_set_hw_capab(struct at\n \twiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CAN_REPLACE_PTK0);\n }\n \n+static void ath_get_initial_entropy(struct ath_softc *sc)\n+{\n+\tstruct ath_hw *ah = sc->sc_ah;\n+\tchar buf[256];\n+\n+\t/* reuse last channel initialized by the tx power test */\n+\tath9k_hw_reset(ah, ah->curchan, NULL, false);\n+\n+\tath9k_hw_get_adc_entropy(ah, buf, sizeof(buf));\n+\tadd_device_randomness(buf, sizeof(buf));\n+}\n+\n int ath9k_init_device(u16 devid, struct ath_softc *sc,\n \t\t    const struct ath_bus_ops *bus_ops)\n {\n@@ -1039,6 +1052,8 @@ int ath9k_init_device(u16 devid, struct\n \n \twiphy_read_of_freq_limits(hw->wiphy);\n \n+\tath_get_initial_entropy(sc);\n+\n \t/* Register with mac80211 */\n \terror = ieee80211_register_hw(hw);\n \tif (error)\n--- a/drivers/net/wireless/ath/ath9k/hw-ops.h\n+++ b/drivers/net/wireless/ath/ath9k/hw-ops.h\n@@ -100,6 +100,12 @@ static inline void ath9k_hw_tx99_set_txp\n \t\tath9k_hw_ops(ah)->tx99_set_txpower(ah, power);\n }\n \n+static inline void ath9k_hw_get_adc_entropy(struct ath_hw *ah,\n+\t\tu8 *buf, size_t len)\n+{\n+\tath9k_hw_ops(ah)->get_adc_entropy(ah, buf, len);\n+}\n+\n #ifdef CPTCFG_ATH9K_BTCOEX_SUPPORT\n \n static inline void ath9k_hw_set_bt_ant_diversity(struct ath_hw *ah, bool enable)\n--- a/drivers/net/wireless/ath/ath9k/ar5008_phy.c\n+++ b/drivers/net/wireless/ath/ath9k/ar5008_phy.c\n@@ -1340,9 +1340,30 @@ void ar5008_hw_init_rate_txpower(struct\n \t}\n }\n \n+static void ar5008_hw_get_adc_entropy(struct ath_hw *ah, u8 *buf, size_t len)\n+{\n+\tint i, j;\n+\n+\tREG_RMW_FIELD(ah, AR_PHY_TEST, AR_PHY_TEST_BBB_OBS_SEL, 1);\n+\tREG_CLR_BIT(ah, AR_PHY_TEST, AR_PHY_TEST_RX_OBS_SEL_BIT5);\n+\tREG_RMW_FIELD(ah, AR_PHY_TEST2, AR_PHY_TEST2_RX_OBS_SEL, 0);\n+\n+\tmemset(buf, 0, len);\n+\tfor (i = 0; i < len; i++) {\n+\t\tfor (j = 0; j < 4; j++) {\n+\t\t\tu32 regval = REG_READ(ah, AR_PHY_TST_ADC);\n+\n+\t\t\tbuf[i] <<= 2;\n+\t\t\tbuf[i] |= (regval & 1) | ((regval & BIT(9)) >> 8);\n+\t\t\tudelay(1);\n+\t\t}\n+\t}\n+}\n+\n int ar5008_hw_attach_phy_ops(struct ath_hw *ah)\n {\n \tstruct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);\n+\tstruct ath_hw_ops *ops = ath9k_hw_ops(ah);\n \tstatic const u32 ar5416_cca_regs[6] = {\n \t\tAR_PHY_CCA,\n \t\tAR_PHY_CH1_CCA,\n@@ -1357,6 +1378,8 @@ int ar5008_hw_attach_phy_ops(struct ath_\n \tif (ret)\n \t    return ret;\n \n+\tops->get_adc_entropy = ar5008_hw_get_adc_entropy;\n+\n \tpriv_ops->rf_set_freq = ar5008_hw_set_channel;\n \tpriv_ops->spur_mitigate_freq = ar5008_hw_spur_mitigate;\n \n--- a/drivers/net/wireless/ath/ath9k/ar9002_phy.h\n+++ b/drivers/net/wireless/ath/ath9k/ar9002_phy.h\n@@ -20,6 +20,12 @@\n #define PHY_AGC_CLR             0x10000000\n #define RFSILENT_BB             0x00002000\n \n+#define AR_PHY_TEST_BBB_OBS_SEL       0x780000\n+#define AR_PHY_TEST_BBB_OBS_SEL_S     19\n+\n+#define AR_PHY_TEST_RX_OBS_SEL_BIT5_S 23\n+#define AR_PHY_TEST_RX_OBS_SEL_BIT5   (1 << AR_PHY_TEST_RX_OBS_SEL_BIT5_S)\n+\n #define AR_PHY_TURBO                0x9804\n #define AR_PHY_FC_TURBO_MODE        0x00000001\n #define AR_PHY_FC_TURBO_SHORT       0x00000002\n@@ -36,6 +42,9 @@\n \n #define AR_PHY_TEST2\t\t\t0x9808\n \n+#define AR_PHY_TEST2_RX_OBS_SEL        0x3C00\n+#define AR_PHY_TEST2_RX_OBS_SEL_S      10\n+\n #define AR_PHY_TIMING2           0x9810\n #define AR_PHY_TIMING3           0x9814\n #define AR_PHY_TIMING3_DSC_MAN   0xFFFE0000\n@@ -393,6 +402,8 @@\n #define AR_PHY_RFBUS_GRANT       0x9C20\n #define AR_PHY_RFBUS_GRANT_EN    0x00000001\n \n+#define AR_PHY_TST_ADC      0x9C24\n+\n #define AR_PHY_CHAN_INFO_GAIN_DIFF             0x9CF4\n #define AR_PHY_CHAN_INFO_GAIN_DIFF_UPPER_LIMIT 320\n \n"
  },
  {
    "path": "package/kernel/mac80211/patches/ath9k/544-ath9k-ar933x-usb-hang-workaround.patch",
    "content": "--- a/drivers/net/wireless/ath/ath9k/hw.c\n+++ b/drivers/net/wireless/ath/ath9k/hw.c\n@@ -247,6 +247,19 @@ void ath9k_hw_get_channel_centers(struct\n \t\tcenters->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);\n }\n \n+static inline void ath9k_hw_disable_pll_lock_detect(struct ath_hw *ah)\n+{\n+\t/* On AR9330 and AR9340 devices, some PHY registers must be\n+\t * tuned to gain better stability/performance. These registers\n+\t * might be changed while doing wlan reset so the registers must\n+\t * be reprogrammed after each reset.\n+\t */\n+\tREG_CLR_BIT(ah, AR_PHY_USB_CTRL1, BIT(20));\n+\tREG_RMW(ah, AR_PHY_USB_CTRL2,\n+\t\t(1 << 21) | (0xf << 22),\n+\t\t(1 << 21) | (0x3 << 22));\n+}\n+\n /******************/\n /* Chip Revisions */\n /******************/\n@@ -1454,6 +1467,9 @@ static bool ath9k_hw_set_reset(struct at\n \t\tudelay(50);\n \t}\n \n+\tif (AR_SREV_9330(ah) || AR_SREV_9340(ah))\n+\t\tath9k_hw_disable_pll_lock_detect(ah);\n+\n \treturn true;\n }\n \n@@ -1553,6 +1569,9 @@ static bool ath9k_hw_chip_reset(struct a\n \t\tar9003_hw_internal_regulator_apply(ah);\n \tath9k_hw_init_pll(ah, chan);\n \n+\tif (AR_SREV_9330(ah) || AR_SREV_9340(ah))\n+\t\tath9k_hw_disable_pll_lock_detect(ah);\n+\n \treturn true;\n }\n \n@@ -1859,8 +1878,14 @@ static int ath9k_hw_do_fastcc(struct ath\n \tif (AR_SREV_9271(ah))\n \t\tar9002_hw_load_ani_reg(ah, chan);\n \n+\tif (AR_SREV_9330(ah) || AR_SREV_9340(ah))\n+\t\tath9k_hw_disable_pll_lock_detect(ah);\n+\n \treturn 0;\n fail:\n+\tif (AR_SREV_9330(ah) || AR_SREV_9340(ah))\n+\t\tath9k_hw_disable_pll_lock_detect(ah);\n+\n \treturn -EINVAL;\n }\n \n@@ -2114,6 +2139,9 @@ int ath9k_hw_reset(struct ath_hw *ah, st\n \t\tath9k_hw_set_radar_params(ah);\n \t}\n \n+\tif (AR_SREV_9330(ah) || AR_SREV_9340(ah))\n+\t\tath9k_hw_disable_pll_lock_detect(ah);\n+\n \treturn 0;\n }\n EXPORT_SYMBOL(ath9k_hw_reset);\n--- a/drivers/net/wireless/ath/ath9k/phy.h\n+++ b/drivers/net/wireless/ath/ath9k/phy.h\n@@ -48,6 +48,9 @@\n #define AR_PHY_PLL_CONTROL 0x16180\n #define AR_PHY_PLL_MODE 0x16184\n \n+#define AR_PHY_USB_CTRL1\t0x16c84\n+#define AR_PHY_USB_CTRL2\t0x16c88\n+\n enum ath9k_ant_div_comb_lna_conf {\n \tATH_ANT_DIV_COMB_LNA1_MINUS_LNA2,\n \tATH_ANT_DIV_COMB_LNA2,\n"
  },
  {
    "path": "package/kernel/mac80211/patches/ath9k/545-ath9k_ani_ws_detect.patch",
    "content": "--- a/drivers/net/wireless/ath/ath9k/ar5008_phy.c\n+++ b/drivers/net/wireless/ath/ath9k/ar5008_phy.c\n@@ -969,55 +969,6 @@ static bool ar5008_hw_ani_control_new(st\n \t\t * on == 0 means more noise imm\n \t\t */\n \t\tu32 on = param ? 1 : 0;\n-\t\t/*\n-\t\t * make register setting for default\n-\t\t * (weak sig detect ON) come from INI file\n-\t\t */\n-\t\tint m1ThreshLow = on ?\n-\t\t\taniState->iniDef.m1ThreshLow : m1ThreshLow_off;\n-\t\tint m2ThreshLow = on ?\n-\t\t\taniState->iniDef.m2ThreshLow : m2ThreshLow_off;\n-\t\tint m1Thresh = on ?\n-\t\t\taniState->iniDef.m1Thresh : m1Thresh_off;\n-\t\tint m2Thresh = on ?\n-\t\t\taniState->iniDef.m2Thresh : m2Thresh_off;\n-\t\tint m2CountThr = on ?\n-\t\t\taniState->iniDef.m2CountThr : m2CountThr_off;\n-\t\tint m2CountThrLow = on ?\n-\t\t\taniState->iniDef.m2CountThrLow : m2CountThrLow_off;\n-\t\tint m1ThreshLowExt = on ?\n-\t\t\taniState->iniDef.m1ThreshLowExt : m1ThreshLowExt_off;\n-\t\tint m2ThreshLowExt = on ?\n-\t\t\taniState->iniDef.m2ThreshLowExt : m2ThreshLowExt_off;\n-\t\tint m1ThreshExt = on ?\n-\t\t\taniState->iniDef.m1ThreshExt : m1ThreshExt_off;\n-\t\tint m2ThreshExt = on ?\n-\t\t\taniState->iniDef.m2ThreshExt : m2ThreshExt_off;\n-\n-\t\tREG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,\n-\t\t\t      AR_PHY_SFCORR_LOW_M1_THRESH_LOW,\n-\t\t\t      m1ThreshLow);\n-\t\tREG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,\n-\t\t\t      AR_PHY_SFCORR_LOW_M2_THRESH_LOW,\n-\t\t\t      m2ThreshLow);\n-\t\tREG_RMW_FIELD(ah, AR_PHY_SFCORR,\n-\t\t\t      AR_PHY_SFCORR_M1_THRESH, m1Thresh);\n-\t\tREG_RMW_FIELD(ah, AR_PHY_SFCORR,\n-\t\t\t      AR_PHY_SFCORR_M2_THRESH, m2Thresh);\n-\t\tREG_RMW_FIELD(ah, AR_PHY_SFCORR,\n-\t\t\t      AR_PHY_SFCORR_M2COUNT_THR, m2CountThr);\n-\t\tREG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,\n-\t\t\t      AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW,\n-\t\t\t      m2CountThrLow);\n-\n-\t\tREG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,\n-\t\t\t      AR_PHY_SFCORR_EXT_M1_THRESH_LOW, m1ThreshLowExt);\n-\t\tREG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,\n-\t\t\t      AR_PHY_SFCORR_EXT_M2_THRESH_LOW, m2ThreshLowExt);\n-\t\tREG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,\n-\t\t\t      AR_PHY_SFCORR_EXT_M1_THRESH, m1ThreshExt);\n-\t\tREG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,\n-\t\t\t      AR_PHY_SFCORR_EXT_M2_THRESH, m2ThreshExt);\n \n \t\tif (on)\n \t\t\tREG_SET_BIT(ah, AR_PHY_SFCORR_LOW,\n--- a/drivers/net/wireless/ath/ath9k/ar9003_phy.c\n+++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.c\n@@ -42,20 +42,6 @@ static const int cycpwrThr1_table[] =\n /* level:  0   1   2   3   4   5   6   7   8  */\n \t{ -6, -4, -2,  0,  2,  4,  6,  8 };     /* lvl 0-7, default 3 */\n \n-/*\n- * register values to turn OFDM weak signal detection OFF\n- */\n-static const int m1ThreshLow_off = 127;\n-static const int m2ThreshLow_off = 127;\n-static const int m1Thresh_off = 127;\n-static const int m2Thresh_off = 127;\n-static const int m2CountThr_off =  31;\n-static const int m2CountThrLow_off =  63;\n-static const int m1ThreshLowExt_off = 127;\n-static const int m2ThreshLowExt_off = 127;\n-static const int m1ThreshExt_off = 127;\n-static const int m2ThreshExt_off = 127;\n-\n static const u8 ofdm2pwr[] = {\n \tALL_TARGET_LEGACY_6_24,\n \tALL_TARGET_LEGACY_6_24,\n@@ -1077,11 +1063,6 @@ static bool ar9003_hw_ani_control(struct\n \tstruct ath_common *common = ath9k_hw_common(ah);\n \tstruct ath9k_channel *chan = ah->curchan;\n \tstruct ar5416AniState *aniState = &ah->ani;\n-\tint m1ThreshLow, m2ThreshLow;\n-\tint m1Thresh, m2Thresh;\n-\tint m2CountThr, m2CountThrLow;\n-\tint m1ThreshLowExt, m2ThreshLowExt;\n-\tint m1ThreshExt, m2ThreshExt;\n \ts32 value, value2;\n \n \tswitch (cmd & ah->ani_function) {\n@@ -1095,61 +1076,6 @@ static bool ar9003_hw_ani_control(struct\n \t\t */\n \t\tu32 on = param ? 1 : 0;\n \n-\t\tif (AR_SREV_9462(ah) || AR_SREV_9565(ah))\n-\t\t\tgoto skip_ws_det;\n-\n-\t\tm1ThreshLow = on ?\n-\t\t\taniState->iniDef.m1ThreshLow : m1ThreshLow_off;\n-\t\tm2ThreshLow = on ?\n-\t\t\taniState->iniDef.m2ThreshLow : m2ThreshLow_off;\n-\t\tm1Thresh = on ?\n-\t\t\taniState->iniDef.m1Thresh : m1Thresh_off;\n-\t\tm2Thresh = on ?\n-\t\t\taniState->iniDef.m2Thresh : m2Thresh_off;\n-\t\tm2CountThr = on ?\n-\t\t\taniState->iniDef.m2CountThr : m2CountThr_off;\n-\t\tm2CountThrLow = on ?\n-\t\t\taniState->iniDef.m2CountThrLow : m2CountThrLow_off;\n-\t\tm1ThreshLowExt = on ?\n-\t\t\taniState->iniDef.m1ThreshLowExt : m1ThreshLowExt_off;\n-\t\tm2ThreshLowExt = on ?\n-\t\t\taniState->iniDef.m2ThreshLowExt : m2ThreshLowExt_off;\n-\t\tm1ThreshExt = on ?\n-\t\t\taniState->iniDef.m1ThreshExt : m1ThreshExt_off;\n-\t\tm2ThreshExt = on ?\n-\t\t\taniState->iniDef.m2ThreshExt : m2ThreshExt_off;\n-\n-\t\tREG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,\n-\t\t\t      AR_PHY_SFCORR_LOW_M1_THRESH_LOW,\n-\t\t\t      m1ThreshLow);\n-\t\tREG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,\n-\t\t\t      AR_PHY_SFCORR_LOW_M2_THRESH_LOW,\n-\t\t\t      m2ThreshLow);\n-\t\tREG_RMW_FIELD(ah, AR_PHY_SFCORR,\n-\t\t\t      AR_PHY_SFCORR_M1_THRESH,\n-\t\t\t      m1Thresh);\n-\t\tREG_RMW_FIELD(ah, AR_PHY_SFCORR,\n-\t\t\t      AR_PHY_SFCORR_M2_THRESH,\n-\t\t\t      m2Thresh);\n-\t\tREG_RMW_FIELD(ah, AR_PHY_SFCORR,\n-\t\t\t      AR_PHY_SFCORR_M2COUNT_THR,\n-\t\t\t      m2CountThr);\n-\t\tREG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,\n-\t\t\t      AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW,\n-\t\t\t      m2CountThrLow);\n-\t\tREG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,\n-\t\t\t      AR_PHY_SFCORR_EXT_M1_THRESH_LOW,\n-\t\t\t      m1ThreshLowExt);\n-\t\tREG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,\n-\t\t\t      AR_PHY_SFCORR_EXT_M2_THRESH_LOW,\n-\t\t\t      m2ThreshLowExt);\n-\t\tREG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,\n-\t\t\t      AR_PHY_SFCORR_EXT_M1_THRESH,\n-\t\t\t      m1ThreshExt);\n-\t\tREG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,\n-\t\t\t      AR_PHY_SFCORR_EXT_M2_THRESH,\n-\t\t\t      m2ThreshExt);\n-skip_ws_det:\n \t\tif (on)\n \t\t\tREG_SET_BIT(ah, AR_PHY_SFCORR_LOW,\n \t\t\t\t    AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);\n"
  },
  {
    "path": "package/kernel/mac80211/patches/ath9k/547-ath9k_led_defstate_fix.patch",
    "content": "From: Michal Cieslakiewicz <michal.cieslakiewicz@wp.pl>\nDate: Sun, 31 Jan 2016 20:48:49 +0100\nSubject: [PATCH v4 2/8] mac80211: ath9k: set default state for platform LEDs\n\nSupport default state for platform LEDs connected to ath9k device.\nNow LEDs are correctly set on or off at ath9k module initialization.\nVery useful if power LED is connected to wireless chip.\n\nSigned-off-by: Michal Cieslakiewicz <michal.cieslakiewicz@wp.pl>\n---\n gpio.c |    7 +++++--\n 1 file changed, 5 insertions(+), 2 deletions(-)\n\n--- a/drivers/net/wireless/ath/ath9k/gpio.c\n+++ b/drivers/net/wireless/ath/ath9k/gpio.c\n@@ -74,8 +74,11 @@ static int ath_add_led(struct ath_softc\n \tath9k_hw_gpio_request_out(sc->sc_ah, gpio->gpio, gpio->name,\n \t\t\t\t  AR_GPIO_OUTPUT_MUX_AS_OUTPUT);\n \n-\t/* LED off */\n-\tath9k_hw_set_gpio(sc->sc_ah, gpio->gpio, gpio->active_low);\n+\t/* Set default LED state */\n+\tif (gpio->default_state == LEDS_GPIO_DEFSTATE_ON)\n+\t\tath9k_hw_set_gpio(sc->sc_ah, gpio->gpio, !gpio->active_low);\n+\telse\n+\t\tath9k_hw_set_gpio(sc->sc_ah, gpio->gpio, gpio->active_low);\n \n \treturn 0;\n }\n"
  },
  {
    "path": "package/kernel/mac80211/patches/ath9k/548-ath9k_enable_gpio_chip.patch",
    "content": "From: Michal Cieslakiewicz <michal.cieslakiewicz@wp.pl>\nDate: Sun, 31 Jan 2016 21:01:31 +0100\nSubject: [PATCH v4 4/8] mac80211: ath9k: enable access to GPIO\n\nEnable access to GPIO chip and its pins for Atheros AR92xx\nwireless devices. For now AR9285 and AR9287 are supported.\n\nSigned-off-by: Michal Cieslakiewicz <michal.cieslakiewicz@wp.pl>\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n--- a/drivers/net/wireless/ath/ath9k/ath9k.h\n+++ b/drivers/net/wireless/ath/ath9k/ath9k.h\n@@ -24,6 +24,7 @@\n #include <linux/completion.h>\n #include <linux/time.h>\n #include <linux/hw_random.h>\n+#include <linux/gpio/driver.h>\n \n #include \"common.h\"\n #include \"debug.h\"\n@@ -989,6 +990,14 @@ struct ath_led {\n \tstruct led_classdev cdev;\n };\n \n+#ifdef CONFIG_GPIOLIB\n+struct ath9k_gpio_chip {\n+\tstruct ath_softc *sc;\n+\tchar label[32];\n+\tstruct gpio_chip gchip;\n+};\n+#endif\n+\n struct ath_softc {\n \tstruct ieee80211_hw *hw;\n \tstruct device *dev;\n@@ -1044,6 +1053,9 @@ struct ath_softc {\n #ifdef CPTCFG_MAC80211_LEDS\n \tconst char *led_default_trigger;\n \tstruct list_head leds;\n+#ifdef CONFIG_GPIOLIB\n+\tstruct ath9k_gpio_chip *gpiochip;\n+#endif\n #endif\n \n #ifdef CPTCFG_ATH9K_DEBUGFS\n--- a/drivers/net/wireless/ath/ath9k/gpio.c\n+++ b/drivers/net/wireless/ath/ath9k/gpio.c\n@@ -16,13 +16,139 @@\n \n #include \"ath9k.h\"\n #include <linux/ath9k_platform.h>\n+#include <linux/gpio.h>\n+\n+#ifdef CPTCFG_MAC80211_LEDS\n+\n+#ifdef CONFIG_GPIOLIB\n+\n+/***************/\n+/*  GPIO Chip  */\n+/***************/\n+\n+/* gpio_chip handler : set GPIO to input */\n+static int ath9k_gpio_pin_cfg_input(struct gpio_chip *chip, unsigned offset)\n+{\n+\tstruct ath9k_gpio_chip *gc = container_of(chip, struct ath9k_gpio_chip,\n+\t\t\t\t\t\t  gchip);\n+\n+\tath9k_hw_gpio_request_in(gc->sc->sc_ah, offset, \"ath9k-gpio\");\n+\n+\treturn 0;\n+}\n+\n+/* gpio_chip handler : set GPIO to output */\n+static int ath9k_gpio_pin_cfg_output(struct gpio_chip *chip, unsigned offset,\n+\t\t\t\t     int value)\n+{\n+\tstruct ath9k_gpio_chip *gc = container_of(chip, struct ath9k_gpio_chip,\n+\t\t\t\t\t\t  gchip);\n+\n+\tath9k_hw_gpio_request_out(gc->sc->sc_ah, offset, \"ath9k-gpio\",\n+\t\t\t\t  AR_GPIO_OUTPUT_MUX_AS_OUTPUT);\n+\tath9k_hw_set_gpio(gc->sc->sc_ah, offset, value);\n+\n+\treturn 0;\n+}\n+\n+/* gpio_chip handler : query GPIO direction (0=out, 1=in) */\n+static int ath9k_gpio_pin_get_dir(struct gpio_chip *chip, unsigned offset)\n+{\n+\tstruct ath9k_gpio_chip *gc = container_of(chip, struct ath9k_gpio_chip,\n+\t\t\t\t\t\t  gchip);\n+\tstruct ath_hw *ah = gc->sc->sc_ah;\n+\n+\treturn !((REG_READ(ah, AR_GPIO_OE_OUT) >> (offset * 2)) & 3);\n+}\n+\n+/* gpio_chip handler : get GPIO pin value */\n+static int ath9k_gpio_pin_get(struct gpio_chip *chip, unsigned offset)\n+{\n+\tstruct ath9k_gpio_chip *gc = container_of(chip, struct ath9k_gpio_chip,\n+\t\t\t\t\t\t  gchip);\n+\n+\treturn ath9k_hw_gpio_get(gc->sc->sc_ah, offset);\n+}\n+\n+/* gpio_chip handler : set GPIO pin to value */\n+static void ath9k_gpio_pin_set(struct gpio_chip *chip, unsigned offset,\n+\t\t\t       int value)\n+{\n+\tstruct ath9k_gpio_chip *gc = container_of(chip, struct ath9k_gpio_chip,\n+\t\t\t\t\t\t  gchip);\n+\n+\tath9k_hw_set_gpio(gc->sc->sc_ah, offset, value);\n+}\n+\n+/* register GPIO chip */\n+static void ath9k_register_gpio_chip(struct ath_softc *sc)\n+{\n+\tstruct ath9k_gpio_chip *gc;\n+\tstruct ath_hw *ah = sc->sc_ah;\n+\n+\tgc = kzalloc(sizeof(struct ath9k_gpio_chip), GFP_KERNEL);\n+\tif (!gc)\n+\t\treturn;\n+\n+\tgc->sc = sc;\n+\tsnprintf(gc->label, sizeof(gc->label), \"ath9k-%s\",\n+\t\t wiphy_name(sc->hw->wiphy));\n+#ifdef CONFIG_OF\n+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4,5,0)\n+\tgc->gchip.parent = sc->dev;\n+#else\n+\tgc->gchip.dev = sc->dev;\n+#endif\n+#endif\n+\tgc->gchip.label = gc->label;\n+\tgc->gchip.base = -1;\t/* determine base automatically */\n+\tgc->gchip.ngpio = ah->caps.num_gpio_pins;\n+\tgc->gchip.direction_input = ath9k_gpio_pin_cfg_input;\n+\tgc->gchip.direction_output = ath9k_gpio_pin_cfg_output;\n+\tgc->gchip.get_direction = ath9k_gpio_pin_get_dir;\n+\tgc->gchip.get = ath9k_gpio_pin_get;\n+\tgc->gchip.set = ath9k_gpio_pin_set;\n+\n+\tif (gpiochip_add(&gc->gchip)) {\n+\t\tkfree(gc);\n+\t\treturn;\n+\t}\n+\n+#ifdef CONFIG_OF\n+\tgc->gchip.owner = NULL;\n+#endif\n+\tsc->gpiochip = gc;\n+}\n+\n+/* remove GPIO chip */\n+static void ath9k_unregister_gpio_chip(struct ath_softc *sc)\n+{\n+\tstruct ath9k_gpio_chip *gc = sc->gpiochip;\n+\n+\tif (!gc)\n+\t\treturn;\n+\n+\tgpiochip_remove(&gc->gchip);\n+\tkfree(gc);\n+\tsc->gpiochip = NULL;\n+}\n+\n+#else /* CONFIG_GPIOLIB */\n+\n+static inline void ath9k_register_gpio_chip(struct ath_softc *sc)\n+{\n+}\n+\n+static inline void ath9k_unregister_gpio_chip(struct ath_softc *sc)\n+{\n+}\n+\n+#endif /* CONFIG_GPIOLIB */\n \n /********************************/\n /*\t LED functions\t\t*/\n /********************************/\n \n-#ifdef CPTCFG_MAC80211_LEDS\n-\n static void ath_fill_led_pin(struct ath_softc *sc)\n {\n \tstruct ath_hw *ah = sc->sc_ah;\n@@ -80,6 +206,12 @@ static int ath_add_led(struct ath_softc\n \telse\n \t\tath9k_hw_set_gpio(sc->sc_ah, gpio->gpio, gpio->active_low);\n \n+#ifdef CONFIG_GPIOLIB\n+\t/* If there is GPIO chip configured, reserve LED pin */\n+\tif (sc->gpiochip)\n+\t\tgpio_request(sc->gpiochip->gchip.base + gpio->gpio, gpio->name);\n+#endif\n+\n \treturn 0;\n }\n \n@@ -136,17 +268,24 @@ void ath_deinit_leds(struct ath_softc *s\n \n \twhile (!list_empty(&sc->leds)) {\n \t\tled = list_first_entry(&sc->leds, struct ath_led, list);\n+#ifdef CONFIG_GPIOLIB\n+\t\t/* If there is GPIO chip configured, free LED pin */\n+\t\tif (sc->gpiochip)\n+\t\t\tgpio_free(sc->gpiochip->gchip.base + led->gpio->gpio);\n+#endif\n \t\tlist_del(&led->list);\n \t\tath_led_brightness(&led->cdev, LED_OFF);\n \t\tled_classdev_unregister(&led->cdev);\n \t\tath9k_hw_gpio_free(sc->sc_ah, led->gpio->gpio);\n \t\tkfree(led);\n \t}\n+\tath9k_unregister_gpio_chip(sc);\n }\n \n void ath_init_leds(struct ath_softc *sc)\n {\n \tstruct ath9k_platform_data *pdata = sc->dev->platform_data;\n+\tstruct device_node *np = sc->dev->of_node;\n \tchar led_name[32];\n \tconst char *trigger;\n \tint i;\n@@ -156,6 +295,15 @@ void ath_init_leds(struct ath_softc *sc)\n \tif (AR_SREV_9100(sc->sc_ah))\n \t\treturn;\n \n+\tif (!np)\n+\t\tath9k_register_gpio_chip(sc);\n+\n+\t/* setup gpio controller only if requested and skip the led_pin setup */\n+\tif (of_property_read_bool(np, \"gpio-controller\")) {\n+\t\tath9k_register_gpio_chip(sc);\n+\t\treturn;\n+\t}\n+\n \tath_fill_led_pin(sc);\n \n \tif (pdata && pdata->leds && pdata->num_leds)\n@@ -180,6 +328,7 @@ void ath_init_leds(struct ath_softc *sc)\n \tath_create_gpio_led(sc, sc->sc_ah->led_pin, led_name, trigger,\n \t\t\t   !sc->sc_ah->config.led_active_high);\n }\n+\n #endif\n \n /*******************/\n"
  },
  {
    "path": "package/kernel/mac80211/patches/ath9k/549-ath9k_enable_gpio_buttons.patch",
    "content": "From: Michal Cieslakiewicz <michal.cieslakiewicz@wp.pl>\nSubject: [PATCH v5 5/8] mac80211: ath9k: enable GPIO buttons\n\nEnable platform-defined GPIO button support for ath9k device.\nKey poller is activated for attached platform buttons.\nRequires ath9k GPIO chip access.\n\nSigned-off-by: Michal Cieslakiewicz <michal.cieslakiewicz@wp.pl>\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n--- a/drivers/net/wireless/ath/ath9k/ath9k.h\n+++ b/drivers/net/wireless/ath/ath9k/ath9k.h\n@@ -1055,6 +1055,7 @@ struct ath_softc {\n \tstruct list_head leds;\n #ifdef CONFIG_GPIOLIB\n \tstruct ath9k_gpio_chip *gpiochip;\n+\tstruct platform_device *btnpdev;\t/* gpio-keys-polled */\n #endif\n #endif\n \n--- a/drivers/net/wireless/ath/ath9k/gpio.c\n+++ b/drivers/net/wireless/ath/ath9k/gpio.c\n@@ -17,6 +17,8 @@\n #include \"ath9k.h\"\n #include <linux/ath9k_platform.h>\n #include <linux/gpio.h>\n+#include <linux/platform_device.h>\n+#include <linux/gpio_keys.h>\n \n #ifdef CPTCFG_MAC80211_LEDS\n \n@@ -133,6 +135,67 @@ static void ath9k_unregister_gpio_chip(s\n \tsc->gpiochip = NULL;\n }\n \n+/******************/\n+/*  GPIO Buttons  */\n+/******************/\n+\n+/* add GPIO buttons */\n+static void ath9k_init_buttons(struct ath_softc *sc)\n+{\n+\tstruct ath9k_platform_data *pdata = sc->dev->platform_data;\n+\tstruct platform_device *pdev;\n+\tstruct gpio_keys_platform_data gkpdata;\n+\tstruct gpio_keys_button *bt;\n+\tint i;\n+\n+\tif (!sc->gpiochip)\n+\t\treturn;\n+\n+\tif (!pdata || !pdata->btns || !pdata->num_btns)\n+\t\treturn;\n+\n+\tbt = devm_kmemdup(sc->dev, pdata->btns,\n+\t\t\t  pdata->num_btns * sizeof(struct gpio_keys_button),\n+\t\t\t  GFP_KERNEL);\n+\tif (!bt)\n+\t\treturn;\n+\n+\tfor (i = 0; i < pdata->num_btns; i++) {\n+\t\tif (pdata->btns[i].gpio == sc->sc_ah->led_pin)\n+\t\t\t\tsc->sc_ah->led_pin = -1;\n+\n+\t\tath9k_hw_gpio_request_in(sc->sc_ah, pdata->btns[i].gpio,\n+\t\t\t\t\t \"ath9k-gpio\");\n+\t\tbt[i].gpio = sc->gpiochip->gchip.base + pdata->btns[i].gpio;\n+\t}\n+\n+\tmemset(&gkpdata, 0, sizeof(struct gpio_keys_platform_data));\n+\tgkpdata.buttons = bt;\n+\tgkpdata.nbuttons = pdata->num_btns;\n+\tgkpdata.poll_interval = pdata->btn_poll_interval;\n+\n+\tpdev = platform_device_register_data(sc->dev, \"gpio-keys-polled\",\n+\t\t\t\t\t     PLATFORM_DEVID_AUTO, &gkpdata,\n+\t\t\t\t\t     sizeof(gkpdata));\n+\tif (!IS_ERR_OR_NULL(pdev))\n+\t\tsc->btnpdev = pdev;\n+\telse {\n+\t\tsc->btnpdev = NULL;\n+\t\tdevm_kfree(sc->dev, bt);\n+\t}\n+}\n+\n+/* remove GPIO buttons */\n+static void ath9k_deinit_buttons(struct ath_softc *sc)\n+{\n+\tif (!sc->gpiochip || !sc->btnpdev)\n+\t\treturn;\n+\n+\tplatform_device_unregister(sc->btnpdev);\n+\n+\tsc->btnpdev = NULL;\n+}\n+\n #else /* CONFIG_GPIOLIB */\n \n static inline void ath9k_register_gpio_chip(struct ath_softc *sc)\n@@ -143,6 +206,14 @@ static inline void ath9k_unregister_gpio\n {\n }\n \n+static inline void ath9k_init_buttons(struct ath_softc *sc)\n+{\n+}\n+\n+static inline void ath9k_deinit_buttons(struct ath_softc *sc)\n+{\n+}\n+\n #endif /* CONFIG_GPIOLIB */\n \n /********************************/\n@@ -266,6 +337,7 @@ void ath_deinit_leds(struct ath_softc *s\n {\n \tstruct ath_led *led;\n \n+\tath9k_deinit_buttons(sc);\n \twhile (!list_empty(&sc->leds)) {\n \t\tled = list_first_entry(&sc->leds, struct ath_led, list);\n #ifdef CONFIG_GPIOLIB\n@@ -305,6 +377,7 @@ void ath_init_leds(struct ath_softc *sc)\n \t}\n \n \tath_fill_led_pin(sc);\n+\tath9k_init_buttons(sc);\n \n \tif (pdata && pdata->leds && pdata->num_leds)\n \t\tfor (i = 0; i < pdata->num_leds; i++) {\n--- a/include/linux/ath9k_platform.h\n+++ b/include/linux/ath9k_platform.h\n@@ -49,6 +49,10 @@ struct ath9k_platform_data {\n \n \tint num_leds;\n \tconst struct gpio_led *leds;\n+\n+\tunsigned num_btns;\n+\tconst struct gpio_keys_button *btns;\n+\tunsigned btn_poll_interval;\n };\n \n #endif /* _LINUX_ATH9K_PLATFORM_H */\n"
  },
  {
    "path": "package/kernel/mac80211/patches/ath9k/551-ath9k_ubnt_uap_plus_hsr.patch",
    "content": "--- a/drivers/net/wireless/ath/ath9k/channel.c\n+++ b/drivers/net/wireless/ath/ath9k/channel.c\n@@ -15,6 +15,7 @@\n  */\n \n #include \"ath9k.h\"\n+#include \"hsr.h\"\n \n /* Set/change channels.  If the channel is really being changed, it's done\n  * by reseting the chip.  To accomplish this we must first cleanup any pending\n@@ -22,6 +23,7 @@\n  */\n static int ath_set_channel(struct ath_softc *sc)\n {\n+\tstruct device_node *np = sc->dev->of_node;\n \tstruct ath_hw *ah = sc->sc_ah;\n \tstruct ath_common *common = ath9k_hw_common(ah);\n \tstruct ieee80211_hw *hw = sc->hw;\n@@ -42,6 +44,11 @@ static int ath_set_channel(struct ath_so\n \tath_dbg(common, CONFIG, \"Set channel: %d MHz width: %d\\n\",\n \t\tchan->center_freq, chandef->width);\n \n+\tif (of_property_read_bool(np, \"ubnt,hsr\")) {\n+\t\tath9k_hsr_enable(ah, chandef->width, chan->center_freq);\n+\t\tath9k_hsr_status(ah);\n+\t}\n+\n \t/* update survey stats for the old channel before switching */\n \tspin_lock_irqsave(&common->cc_lock, flags);\n \tath_update_survey_stats(sc);\n--- /dev/null\n+++ b/drivers/net/wireless/ath/ath9k/hsr.c\n@@ -0,0 +1,247 @@\n+/*\n+ *\n+ * The MIT License (MIT)\n+ *\n+ * Copyright (c) 2015 Kirill Berezin\n+ *\n+ * Permission is hereby granted, free of charge, to any person obtaining a copy\n+ * of this software and associated documentation files (the \"Software\"), to deal\n+ * in the Software without restriction, including without limitation the rights\n+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\n+ * copies of the Software, and to permit persons to whom the Software is\n+ * furnished to do so, subject to the following conditions:\n+ *\n+ * The above copyright notice and this permission notice shall be included in\n+ * all copies or substantial portions of the Software.\n+ *\n+ * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\n+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n+ * SOFTWARE.\n+ *\n+ */\n+\n+#include <linux/io.h>\n+#include <linux/slab.h>\n+#include <linux/module.h>\n+#include <linux/time.h>\n+#include <linux/bitops.h>\n+#include <linux/etherdevice.h>\n+#include <linux/rtnetlink.h>\n+#include <asm/unaligned.h>\n+\n+#include \"hw.h\"\n+#include \"ath9k.h\"\n+\n+#define HSR_GPIO_CSN 8\n+#define HSR_GPIO_CLK 6\n+#define HSR_GPIO_DOUT 7\n+#define HSR_GPIO_DIN 5\n+\n+/* delays are in useconds */\n+#define HSR_DELAY_HALF_TICK 100\n+#define HSR_DELAY_PRE_WRITE 75\n+#define HSR_DELAY_FINAL 20000\n+#define HSR_DELAY_TRAILING 200\n+\n+void ath9k_hsr_init(struct ath_hw *ah)\n+{\n+\tath9k_hw_gpio_request_in(ah, HSR_GPIO_DIN, NULL);\n+\tath9k_hw_gpio_request_out(ah, HSR_GPIO_CSN, NULL,\n+\t\t\t\t  AR_GPIO_OUTPUT_MUX_AS_OUTPUT);\n+\tath9k_hw_gpio_request_out(ah, HSR_GPIO_CLK, NULL,\n+\t\t\t\t  AR_GPIO_OUTPUT_MUX_AS_OUTPUT);\n+\tath9k_hw_gpio_request_out(ah, HSR_GPIO_DOUT, NULL,\n+\t\t\t\t  AR_GPIO_OUTPUT_MUX_AS_OUTPUT);\n+\n+\tath9k_hw_set_gpio(ah, HSR_GPIO_CSN, 1);\n+\tath9k_hw_set_gpio(ah, HSR_GPIO_CLK, 0);\n+\tath9k_hw_set_gpio(ah, HSR_GPIO_DOUT, 0);\n+\n+\tudelay(HSR_DELAY_TRAILING);\n+}\n+\n+static u32 ath9k_hsr_write_byte(struct ath_hw *ah, int delay, u32 value)\n+{\n+\tstruct ath_common *common = ath9k_hw_common(ah);\n+\tint i;\n+\tu32 rval = 0;\n+\n+\tudelay(delay);\n+\n+\tath9k_hw_set_gpio(ah, HSR_GPIO_CLK, 0);\n+\tudelay(HSR_DELAY_HALF_TICK);\n+\n+\tath9k_hw_set_gpio(ah, HSR_GPIO_CSN, 0);\n+\tudelay(HSR_DELAY_HALF_TICK);\n+\n+\tfor (i = 0; i < 8; ++i) {\n+\t\trval = rval << 1;\n+\n+\t\t/* pattern is left to right, that is 7-th bit runs first */\n+\t\tath9k_hw_set_gpio(ah, HSR_GPIO_DOUT, (value >> (7 - i)) & 0x1);\n+\t\tudelay(HSR_DELAY_HALF_TICK);\n+\n+\t\tath9k_hw_set_gpio(ah, HSR_GPIO_CLK, 1);\n+\t\tudelay(HSR_DELAY_HALF_TICK);\n+\n+\t\trval |= ath9k_hw_gpio_get(ah, HSR_GPIO_DIN);\n+\n+\t\tath9k_hw_set_gpio(ah, HSR_GPIO_CLK, 0);\n+\t\tudelay(HSR_DELAY_HALF_TICK);\n+\t}\n+\n+\tath9k_hw_set_gpio(ah, HSR_GPIO_CSN, 1);\n+\tudelay(HSR_DELAY_HALF_TICK);\n+\n+\tath_dbg(common, CONFIG, \"ath9k_hsr_write_byte: write byte %d return value is %d %c\\n\",\n+\t\tvalue, rval, rval > 32 ? rval : '-');\n+\n+\treturn rval & 0xff;\n+}\n+\n+static int ath9k_hsr_write_a_chain(struct ath_hw *ah, char *chain, int items)\n+{\n+\tint status = 0;\n+\tint i = 0;\n+\tint err;\n+\n+\t/* a preamble */\n+\tath9k_hsr_write_byte(ah, HSR_DELAY_PRE_WRITE, 0);\n+\tstatus = ath9k_hsr_write_byte(ah, HSR_DELAY_PRE_WRITE, 0);\n+\n+\t/* clear HSR's reply buffer */\n+\tif (status) {\n+\t\tint loop = 0;\n+\n+\t\tfor (loop = 0; (loop < 42) && status; ++loop)\n+\t\t\tstatus = ath9k_hsr_write_byte(ah, HSR_DELAY_PRE_WRITE,\n+\t\t\t\t\t\t      0);\n+\n+\t\tif (loop >= 42) {\n+\t\t\tATH_DBG_WARN(1,\n+\t\t\t\t     \"ath9k_hsr_write_a_chain: can't clear an output buffer after a 42 cycles.\\n\");\n+\t\t\treturn -1;\n+\t\t}\n+\t}\n+\n+\tfor (i = 0; (i < items) && (chain[i] != 0); ++i)\n+\t\tath9k_hsr_write_byte(ah, HSR_DELAY_PRE_WRITE, (u32)chain[i]);\n+\n+\tath9k_hsr_write_byte(ah, HSR_DELAY_PRE_WRITE, 0);\n+\tmdelay(HSR_DELAY_FINAL / 1000);\n+\n+\t/* reply */\n+\tmemset(chain, 0, items);\n+\n+\tath9k_hsr_write_byte(ah, HSR_DELAY_PRE_WRITE, 0);\n+\tudelay(HSR_DELAY_TRAILING);\n+\n+\tfor (i = 0; i < (items - 1); ++i) {\n+\t\tu32 ret;\n+\n+\t\tret = ath9k_hsr_write_byte(ah, HSR_DELAY_PRE_WRITE, 0);\n+\t\tif (ret != 0)\n+\t\t\tchain[i] = (char)ret;\n+\t\telse\n+\t\t\tbreak;\n+\n+\t\tudelay(HSR_DELAY_TRAILING);\n+\t}\n+\n+\tif (i <= 1)\n+\t\treturn 0;\n+\n+\terr = kstrtoint(chain + 1, 10, &i);\n+\tif (err)\n+\t\treturn err;\n+\n+\treturn i;\n+}\n+\n+int ath9k_hsr_disable(struct ath_hw *ah)\n+{\n+\tchar cmd[10] = {'b', '4', '0', 0, 0, 0, 0, 0, 0, 0};\n+\tint ret;\n+\n+\tret = ath9k_hsr_write_a_chain(ah, cmd, sizeof(cmd));\n+\tif ((ret > 0) && (*cmd == 'B'))\n+\t\treturn 0;\n+\n+\treturn -1;\n+}\n+\n+int ath9k_hsr_enable(struct ath_hw *ah, int bw, int fq)\n+{\n+\tchar cmd[10];\n+\tint ret;\n+\n+\t/* Bandwidth argument is 0 sometimes. Assume default 802.11bgn\n+\t * 20MHz on invalid values\n+\t */\n+\tif ((bw != 5) && (bw != 10) && (bw != 20) && (bw != 40))\n+\t\tbw = 20;\n+\n+\tmemset(cmd, 0, sizeof(cmd));\n+\t*cmd = 'b';\n+\tsnprintf(cmd + 1, 3, \"%02d\", bw);\n+\n+\tret = ath9k_hsr_write_a_chain(ah, cmd, sizeof(cmd));\n+\tif ((*cmd != 'B') || (ret != bw)) {\n+\t\tATH_DBG_WARN(1,\n+\t\t\t     \"ath9k_hsr_enable: failed changing bandwidth -> set (%d,%d) reply (%d, %d)\\n\",\n+\t\t\t     'b', bw, *cmd, ret);\n+\t\treturn -1;\n+\t}\n+\n+\tmemset(cmd, 0, sizeof(cmd));\n+\t*cmd = 'x';\n+\tret = ath9k_hsr_write_a_chain(ah, cmd, sizeof(cmd));\n+\tif (*cmd != 'X') {\n+\t\tATH_DBG_WARN(1,\n+\t\t\t     \"ath9k_hsr_enable: failed 'x' command -> reply (%d, %d)\\n\",\n+\t\t\t     *cmd, ret);\n+\t\treturn -1;\n+\t}\n+\n+\tmemset(cmd, 0, sizeof(cmd));\n+\t*cmd = 'm';\n+\tret = ath9k_hsr_write_a_chain(ah, cmd, sizeof(cmd));\n+\tif (*cmd != 'M') {\n+\t\tATH_DBG_WARN(1,\n+\t\t\t     \"ath9k_hsr_enable: failed 'm' command -> reply (%d, %d)\\n\",\n+\t\t\t     *cmd, ret);\n+\t\treturn  -1;\n+\t}\n+\n+\tmemset(cmd, 0, sizeof(cmd));\n+\t*cmd = 'f';\n+\tsnprintf(cmd + 1, 6, \"%05d\", fq);\n+\tret = ath9k_hsr_write_a_chain(ah, cmd, sizeof(cmd));\n+\tif ((*cmd != 'F') && (ret != fq)) {\n+\t\tATH_DBG_WARN(1,\n+\t\t\t     \"ath9k_hsr_enable: failed set frequency -> reply (%d, %d)\\n\",\n+\t\t\t     *cmd, ret);\n+\t\treturn -1;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+int ath9k_hsr_status(struct ath_hw *ah)\n+{\n+\tchar cmd[10] = {'s', 0, 0, 0, 0, 0, 0, 0, 0, 0};\n+\tint ret;\n+\n+\tret = ath9k_hsr_write_a_chain(ah, cmd, sizeof(cmd));\n+\tif (*cmd != 'S') {\n+\t\tATH_DBG_WARN(1, \"ath9k_hsr_status: returned %d,%d\\n\", *cmd,\n+\t\t\t     ret);\n+\t\treturn -1;\n+\t}\n+\n+\treturn 0;\n+}\n--- /dev/null\n+++ b/drivers/net/wireless/ath/ath9k/hsr.h\n@@ -0,0 +1,48 @@\n+/*\n+ * The MIT License (MIT)\n+ *\n+ * Copyright (c) 2015 Kirill Berezin\n+ *\n+ * Permission is hereby granted, free of charge, to any person obtaining a copy\n+ * of this software and associated documentation files (the \"Software\"), to deal\n+ * in the Software without restriction, including without limitation the rights\n+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\n+ * copies of the Software, and to permit persons to whom the Software is\n+ * furnished to do so, subject to the following conditions:\n+ *\n+ * The above copyright notice and this permission notice shall be included in\n+ * all copies or substantial portions of the Software.\n+ *\n+ * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\n+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\n+ * SOFTWARE.\n+ */\n+\n+#ifndef HSR_H\n+#define HSR_H\n+\n+#ifdef CPTCFG_ATH9K_UBNTHSR\n+\n+void ath9k_hsr_init(struct ath_hw *ah);\n+int ath9k_hsr_disable(struct ath_hw *ah);\n+int ath9k_hsr_enable(struct ath_hw *ah, int bw, int fq);\n+int ath9k_hsr_status(struct ath_hw *ah);\n+\n+#else\n+static inline void ath9k_hsr_init(struct ath_hw *ah) {}\n+\n+static inline int ath9k_hsr_enable(struct ath_hw *ah, int bw, int fq)\n+{\n+\treturn 0;\n+}\n+\n+static inline int ath9k_hsr_disable(struct ath_hw *ah) { return 0; }\n+static inline int ath9k_hsr_status(struct ath_hw *ah) { return 0; }\n+\n+#endif\n+\n+#endif /* HSR_H */\n--- a/drivers/net/wireless/ath/ath9k/main.c\n+++ b/drivers/net/wireless/ath/ath9k/main.c\n@@ -18,6 +18,7 @@\n #include <linux/delay.h>\n #include \"ath9k.h\"\n #include \"btcoex.h\"\n+#include \"hsr.h\"\n \n static void ath9k_flush(struct ieee80211_hw *hw, struct ieee80211_vif *vif,\n \t\t\tu32 queues, bool drop);\n@@ -659,6 +660,7 @@ void ath_reset_work(struct work_struct *\n static int ath9k_start(struct ieee80211_hw *hw)\n {\n \tstruct ath_softc *sc = hw->priv;\n+\tstruct device_node *np = sc->dev->of_node;\n \tstruct ath_hw *ah = sc->sc_ah;\n \tstruct ath_common *common = ath9k_hw_common(ah);\n \tstruct ieee80211_channel *curchan = sc->cur_chan->chandef.chan;\n@@ -737,6 +739,11 @@ static int ath9k_start(struct ieee80211_\n \t\t\t\t\t  AR_GPIO_OUTPUT_MUX_AS_OUTPUT);\n \t}\n \n+\tif (of_property_read_bool(np, \"ubnt,hsr\")) {\n+\t\tath9k_hsr_init(ah);\n+\t\tath9k_hsr_disable(ah);\n+\t}\n+\n \t/*\n \t * Reset key cache to sane defaults (all entries cleared) instead of\n \t * semi-random values after suspend/resume.\n--- a/drivers/net/wireless/ath/ath9k/Makefile\n+++ b/drivers/net/wireless/ath/ath9k/Makefile\n@@ -17,6 +17,7 @@ ath9k-$(CPTCFG_ATH9K_DFS_CERTIFIED) += d\n ath9k-$(CPTCFG_ATH9K_TX99) += tx99.o\n ath9k-$(CPTCFG_ATH9K_WOW) += wow.o\n ath9k-$(CPTCFG_ATH9K_HWRNG) += rng.o\n+ath9k-$(CPTCFG_ATH9K_UBNTHSR) += hsr.o\n \n ath9k-$(CPTCFG_ATH9K_DEBUGFS) += debug.o\n \n--- a/local-symbols\n+++ b/local-symbols\n@@ -110,6 +110,7 @@ ATH9K_WOW=\n ATH9K_RFKILL=\n ATH9K_CHANNEL_CONTEXT=\n ATH9K_PCOEM=\n+ATH9K_UBNTHSR=\n ATH9K_PCI_NO_EEPROM=\n ATH9K_HTC=\n ATH9K_HTC_DEBUGFS=\n--- a/drivers/net/wireless/ath/ath9k/Kconfig\n+++ b/drivers/net/wireless/ath/ath9k/Kconfig\n@@ -58,6 +58,19 @@ config ATH9K_AHB\n \t  Say Y, if you have a SoC with a compatible built-in\n \t  wireless MAC. Say N if unsure.\n \n+config ATH9K_UBNTHSR\n+\tbool \"Ubiquiti UniFi Outdoor Plus HSR support\"\n+\tdepends on ATH9K\n+\t---help---\n+\t  This options enables code to control the HSR RF\n+\t  filter in the receive path of the Ubiquiti UniFi\n+\t  Outdoor Plus access point.\n+\n+\t  Say Y if you want to use the access point. The\n+\t  code will only be used if the device is detected,\n+\t  so it does not harm other setup other than occupying\n+\t  a bit of memory.\n+\n config ATH9K_DEBUGFS\n \tbool \"Atheros ath9k debugging\"\n \tdepends on ATH9K && DEBUG_FS\n"
  },
  {
    "path": "package/kernel/mac80211/patches/ath9k/552-ath9k-ahb_of.patch",
    "content": "--- a/drivers/net/wireless/ath/ath9k/ahb.c\n+++ b/drivers/net/wireless/ath/ath9k/ahb.c\n@@ -20,7 +20,15 @@\n #include <linux/platform_device.h>\n #include <linux/module.h>\n #include <linux/mod_devicetable.h>\n+#include <linux/of_device.h>\n #include \"ath9k.h\"\n+#include <linux/ath9k_platform.h>\n+\n+#ifdef CONFIG_OF\n+#include <asm/mach-ath79/ath79.h>\n+#include <asm/mach-ath79/ar71xx_regs.h>\n+#include <linux/mtd/mtd.h>\n+#endif\n \n static const struct platform_device_id ath9k_platform_id_table[] = {\n \t{\n@@ -69,6 +77,236 @@ static const struct ath_bus_ops ath_ahb_\n \t.eeprom_read = ath_ahb_eeprom_read,\n };\n \n+#ifdef CONFIG_OF\n+\n+#define QCA955X_DDR_CTL_CONFIG          0x108\n+#define QCA955X_DDR_CTL_CONFIG_ACT_WMAC BIT(23)\n+\n+static int of_get_wifi_cal(struct device_node *np, struct ath9k_platform_data *pdata)\n+{\n+#ifdef CONFIG_MTD\n+\tstruct device_node *mtd_np = NULL;\n+\tsize_t retlen;\n+\tint size, ret;\n+\tstruct mtd_info *mtd;\n+\tconst char *part;\n+\tconst __be32 *list;\n+\tphandle phandle;\n+\n+\tlist = of_get_property(np, \"mtd-cal-data\", &size);\n+\tif (!list)\n+\t\treturn 0;\n+\n+\tif (size != (2 * sizeof(*list)))\n+\t\treturn 1;\n+\n+\tphandle = be32_to_cpup(list++);\n+\tif (phandle)\n+\t\tmtd_np = of_find_node_by_phandle(phandle);\n+\n+\tif (!mtd_np)\n+\t\treturn 1;\n+\n+\tpart = of_get_property(mtd_np, \"label\", NULL);\n+\tif (!part)\n+\t\tpart = mtd_np->name;\n+\n+\tmtd = get_mtd_device_nm(part);\n+\tif (IS_ERR(mtd))\n+\t\treturn 1;\n+\n+\tret = mtd_read(mtd, be32_to_cpup(list), sizeof(pdata->eeprom_data),\n+\t\t\t&retlen, (u8*)pdata->eeprom_data);\n+\tput_mtd_device(mtd);\n+\n+#endif\n+\treturn 0;\n+}\n+\n+static int ar913x_wmac_reset(void)\n+{\n+\tath79_device_reset_set(AR913X_RESET_AMBA2WMAC);\n+\tmdelay(10);\n+\n+\tath79_device_reset_clear(AR913X_RESET_AMBA2WMAC);\n+\tmdelay(10);\n+\n+\treturn 0;\n+}\n+\n+static int ar933x_wmac_reset(void)\n+{\n+\tint retries = 20;\n+\n+\tath79_device_reset_set(AR933X_RESET_WMAC);\n+\tath79_device_reset_clear(AR933X_RESET_WMAC);\n+\n+\twhile (1) {\n+\t\tu32 bootstrap;\n+\n+\t\tbootstrap = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);\n+\t\tif ((bootstrap & AR933X_BOOTSTRAP_EEPBUSY) == 0)\n+\t\t\treturn 0;\n+\n+\t\tif (retries-- == 0)\n+\t\t\tbreak;\n+\n+\t\tudelay(10000);\n+\t}\n+\n+\tpr_err(\"ar933x: WMAC reset timed out\");\n+\treturn -ETIMEDOUT;\n+}\n+\n+static int qca955x_wmac_reset(void)\n+{\n+\tint i;\n+\n+\t/* Try to wait for WMAC DDR activity to stop */\n+\tfor (i = 0; i < 10; i++) {\n+\t\tif (!(__raw_readl(ath79_ddr_base + QCA955X_DDR_CTL_CONFIG) &\n+\t\t    QCA955X_DDR_CTL_CONFIG_ACT_WMAC))\n+\t\t\tbreak;\n+\n+\t\tudelay(10);\n+\t}\n+\n+\tath79_device_reset_set(QCA955X_RESET_RTC);\n+\tudelay(10);\n+\tath79_device_reset_clear(QCA955X_RESET_RTC);\n+\tudelay(10);\n+\n+\treturn 0;\n+}\n+\n+enum {\n+\tAR913X_WMAC = 0,\n+\tAR933X_WMAC,\n+\tAR934X_WMAC,\n+\tQCA953X_WMAC,\n+\tQCA955X_WMAC,\n+\tQCA956X_WMAC,\n+};\n+\n+static int ar9330_get_soc_revision(void)\n+{\n+\tif (ath79_soc_rev == 1)\n+\t\treturn ath79_soc_rev;\n+\n+\treturn 0;\n+}\n+\n+static int ath79_get_soc_revision(void)\n+{\n+\treturn ath79_soc_rev;\n+}\n+\n+static const struct of_ath_ahb_data {\n+\tu16 dev_id;\n+\tu32 bootstrap_reg;\n+\tu32 bootstrap_ref;\n+\n+\tint (*soc_revision)(void);\n+\tint (*wmac_reset)(void);\n+} of_ath_ahb_data[] = {\n+\t[AR913X_WMAC] = {\n+\t\t.dev_id = AR5416_AR9100_DEVID,\n+\t\t.wmac_reset = ar913x_wmac_reset,\n+\n+\t},\n+\t[AR933X_WMAC] = {\n+\t\t.dev_id = AR9300_DEVID_AR9330,\n+\t\t.bootstrap_reg = AR933X_RESET_REG_BOOTSTRAP,\n+\t\t.bootstrap_ref = AR933X_BOOTSTRAP_REF_CLK_40,\n+\t\t.soc_revision = ar9330_get_soc_revision,\n+\t\t.wmac_reset = ar933x_wmac_reset,\n+\t},\n+\t[AR934X_WMAC] = {\n+\t\t.dev_id = AR9300_DEVID_AR9340,\n+\t\t.bootstrap_reg = AR934X_RESET_REG_BOOTSTRAP,\n+\t\t.bootstrap_ref = AR934X_BOOTSTRAP_REF_CLK_40,\n+\t\t.soc_revision = ath79_get_soc_revision,\n+\t},\n+\t[QCA953X_WMAC] = {\n+\t\t.dev_id = AR9300_DEVID_AR953X,\n+\t\t.bootstrap_reg = QCA953X_RESET_REG_BOOTSTRAP,\n+\t\t.bootstrap_ref = QCA953X_BOOTSTRAP_REF_CLK_40,\n+\t\t.soc_revision = ath79_get_soc_revision,\n+\t},\n+\t[QCA955X_WMAC] = {\n+\t\t.dev_id = AR9300_DEVID_QCA955X,\n+\t\t.bootstrap_reg = QCA955X_RESET_REG_BOOTSTRAP,\n+\t\t.bootstrap_ref = QCA955X_BOOTSTRAP_REF_CLK_40,\n+\t\t.wmac_reset = qca955x_wmac_reset,\n+\t},\n+\t[QCA956X_WMAC] = {\n+\t\t.dev_id = AR9300_DEVID_QCA956X,\n+\t\t.bootstrap_reg = QCA956X_RESET_REG_BOOTSTRAP,\n+\t\t.bootstrap_ref = QCA956X_BOOTSTRAP_REF_CLK_40,\n+\t\t.soc_revision = ath79_get_soc_revision,\n+\t},\n+};\n+\n+const struct of_device_id of_ath_ahb_match[] = {\n+\t{ .compatible = \"qca,ar9130-wmac\", .data = &of_ath_ahb_data[AR913X_WMAC] },\n+\t{ .compatible = \"qca,ar9330-wmac\", .data = &of_ath_ahb_data[AR933X_WMAC] },\n+\t{ .compatible = \"qca,ar9340-wmac\", .data = &of_ath_ahb_data[AR934X_WMAC] },\n+\t{ .compatible = \"qca,qca9530-wmac\", .data = &of_ath_ahb_data[QCA953X_WMAC] },\n+\t{ .compatible = \"qca,qca9550-wmac\", .data = &of_ath_ahb_data[QCA955X_WMAC] },\n+\t{ .compatible = \"qca,qca9560-wmac\", .data = &of_ath_ahb_data[QCA956X_WMAC] },\n+\t{},\n+};\n+MODULE_DEVICE_TABLE(of, of_ath_ahb_match);\n+\n+static int of_ath_ahb_probe(struct platform_device *pdev)\n+{\n+\tstruct ath9k_platform_data *pdata;\n+\tconst struct of_device_id *match;\n+\tconst struct of_ath_ahb_data *data;\n+\tu8 led_pin;\n+\n+\tmatch = of_match_device(of_ath_ahb_match, &pdev->dev);\n+\tdata = (const struct of_ath_ahb_data *)match->data;\n+\n+\tpdata = dev_get_platdata(&pdev->dev);\n+\n+\tif (!of_property_read_u8(pdev->dev.of_node, \"qca,led-pin\", &led_pin))\n+\t\tpdata->led_pin = led_pin;\n+\telse\n+\t\tpdata->led_pin = -1;\n+\n+\tif (of_property_read_bool(pdev->dev.of_node, \"qca,tx-gain-buffalo\"))\n+\t\tpdata->tx_gain_buffalo = true;\n+\n+\tif (data->wmac_reset) {\n+\t\tdata->wmac_reset();\n+\t\tpdata->external_reset = data->wmac_reset;\n+\t}\n+\n+\tif (data->dev_id == AR9300_DEVID_AR953X) {\n+\t\t/*\n+\t\t * QCA953x only supports 25MHz refclk.\n+\t\t * Some vendors have an invalid bootstrap option\n+\t\t * set, which would break the WMAC here.\n+\t\t */\n+\t\tpdata->is_clk_25mhz = true;\n+\t} else if (data->bootstrap_reg && data->bootstrap_ref) {\n+\t\tu32 t = ath79_reset_rr(data->bootstrap_reg);\n+\t\tif (t & data->bootstrap_ref)\n+\t\t\tpdata->is_clk_25mhz = false;\n+\t\telse\n+\t\t\tpdata->is_clk_25mhz = true;\n+\t}\n+\n+\tpdata->get_mac_revision = data->soc_revision;\n+\n+\tif (of_get_wifi_cal(pdev->dev.of_node, pdata))\n+\t\tdev_err(&pdev->dev, \"failed to load calibration data from mtd device\\n\");\n+\n+\treturn data->dev_id;\n+}\n+#endif\n+\n static int ath_ahb_probe(struct platform_device *pdev)\n {\n \tvoid __iomem *mem;\n@@ -80,6 +318,17 @@ static int ath_ahb_probe(struct platform\n \tint ret = 0;\n \tstruct ath_hw *ah;\n \tchar hw_name[64];\n+\tu16 dev_id;\n+\n+\tif (id)\n+\t\tdev_id = id->driver_data;\n+\n+#ifdef CONFIG_OF\n+\tif (pdev->dev.of_node)\n+\t\tpdev->dev.platform_data = devm_kzalloc(&pdev->dev,\n+\t\t\t\t\tsizeof(struct ath9k_platform_data),\n+\t\t\t\t\tGFP_KERNEL);\n+#endif\n \n \tif (!dev_get_platdata(&pdev->dev)) {\n \t\tdev_err(&pdev->dev, \"no platform data specified\\n\");\n@@ -122,13 +371,16 @@ static int ath_ahb_probe(struct platform\n \tsc->mem = mem;\n \tsc->irq = irq;\n \n+#ifdef CONFIG_OF\n+\tdev_id = of_ath_ahb_probe(pdev);\n+#endif\n \tret = request_irq(irq, ath_isr, IRQF_SHARED, \"ath9k\", sc);\n \tif (ret) {\n \t\tdev_err(&pdev->dev, \"request_irq failed\\n\");\n \t\tgoto err_free_hw;\n \t}\n \n-\tret = ath9k_init_device(id->driver_data, sc, &ath_ahb_bus_ops);\n+\tret = ath9k_init_device(dev_id, sc, &ath_ahb_bus_ops);\n \tif (ret) {\n \t\tdev_err(&pdev->dev, \"failed to initialize device\\n\");\n \t\tgoto err_irq;\n@@ -159,6 +411,9 @@ static int ath_ahb_remove(struct platfor\n \t\tfree_irq(sc->irq, sc);\n \t\tieee80211_free_hw(sc->hw);\n \t}\n+#ifdef CONFIG_OF\n+\tpdev->dev.platform_data = NULL;\n+#endif\n \n \treturn 0;\n }\n@@ -168,6 +423,9 @@ static struct platform_driver ath_ahb_dr\n \t.remove     = ath_ahb_remove,\n \t.driver\t\t= {\n \t\t.name\t= \"ath9k\",\n+#ifdef CONFIG_OF\n+\t\t.of_match_table = of_ath_ahb_match,\n+#endif\n \t},\n \t.id_table    = ath9k_platform_id_table,\n };\n--- a/drivers/net/wireless/ath/ath9k/ath9k.h\n+++ b/drivers/net/wireless/ath/ath9k/ath9k.h\n@@ -25,6 +25,7 @@\n #include <linux/time.h>\n #include <linux/hw_random.h>\n #include <linux/gpio/driver.h>\n+#include <linux/reset.h>\n \n #include \"common.h\"\n #include \"debug.h\"\n@@ -1011,6 +1012,9 @@ struct ath_softc {\n \tstruct ath_hw *sc_ah;\n \tvoid __iomem *mem;\n \tint irq;\n+#ifdef CONFIG_OF\n+\tstruct reset_control *reset;\n+#endif\n \tspinlock_t sc_serial_rw;\n \tspinlock_t sc_pm_lock;\n \tspinlock_t sc_pcu_lock;\n"
  },
  {
    "path": "package/kernel/mac80211/patches/ath9k/553-ath9k_of_gpio_mask.patch",
    "content": "--- a/drivers/net/wireless/ath/ath9k/init.c\n+++ b/drivers/net/wireless/ath/ath9k/init.c\n@@ -644,6 +644,12 @@ static int ath9k_of_init(struct ath_soft\n \treturn 0;\n }\n \n+static void ath9k_of_gpio_mask(struct ath_softc *sc)\n+{\n+\tof_property_read_u32(sc->dev->of_node, \"qca,gpio-mask\",\n+\t\t\t     &sc->sc_ah->caps.gpio_mask);\n+}\n+\n static int ath9k_init_softc(u16 devid, struct ath_softc *sc,\n \t\t\t    const struct ath_bus_ops *bus_ops)\n {\n@@ -747,6 +753,9 @@ static int ath9k_init_softc(u16 devid, s\n \tif (ret)\n \t\tgoto err_hw;\n \n+\t/* GPIO mask quirk */\n+\tath9k_of_gpio_mask(sc);\n+\n \tret = ath9k_init_queues(sc);\n \tif (ret)\n \t\tgoto err_queues;\n"
  },
  {
    "path": "package/kernel/mac80211/patches/ath9k/580-ath9k_ar9561_fix_bias_level.patch",
    "content": "From 4509e523dba46f789377cfec6f20579adf743416 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Thibaut=20VAR=C3=88NE?= <hacks+kernel@slashdirt.org>\nDate: Sun, 17 Apr 2022 11:31:35 +0200\nSubject: [PATCH v2] ath9k: fix QCA9561 PA bias level\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nThis patch fixes an invalid TX PA DC bias level on QCA9561, which\nresults in a very low output power and very low throughput as devices\nare further away from the AP (compared to other 2.4GHz APs).\n\nThis patch was suggested by Felix Fietkau, who noted[1]:\n\"The value written to that register is wrong, because while the mask\ndefinition AR_CH0_TOP2_XPABIASLVL uses a different value for 9561, the\nshift definition AR_CH0_TOP2_XPABIASLVL_S is hardcoded to 12, which is\nwrong for 9561.\"\n\nIn real life testing, without this patch the 2.4GHz throughput on\nYuncore XD3200 is around 10Mbps sitting next to the AP, and closer to\npractical maximum with the patch applied.\n\n[1] https://lore.kernel.org/all/91c58969-c60e-2f41-00ac-737786d435ae@nbd.name\n\nSigned-off-by: Thibaut VARÈNE <hacks+kernel@slashdirt.org>\n---\nv2: Adjust #define per Felix's suggestion\n---\n drivers/net/wireless/ath/ath9k/ar9003_phy.h | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\ndiff --git a/drivers/net/wireless/ath/ath9k/ar9003_phy.h b/drivers/net/wireless/ath/ath9k/ar9003_phy.h\nindex a171dbb29..ad949eb02 100644\n--- a/drivers/net/wireless/ath/ath9k/ar9003_phy.h\n+++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.h\n@@ -720,7 +720,7 @@\n #define AR_CH0_TOP2\t\t(AR_SREV_9300(ah) ? 0x1628c : \\\n \t\t\t\t\t(AR_SREV_9462(ah) ? 0x16290 : 0x16284))\n #define AR_CH0_TOP2_XPABIASLVL\t\t(AR_SREV_9561(ah) ? 0x1e00 : 0xf000)\n-#define AR_CH0_TOP2_XPABIASLVL_S\t12\n+#define AR_CH0_TOP2_XPABIASLVL_S\t(AR_SREV_9561(ah) ? 9 : 12)\n \n #define AR_CH0_XTAL\t\t(AR_SREV_9300(ah) ? 0x16294 : \\\n \t\t\t\t ((AR_SREV_9462(ah) || AR_SREV_9565(ah)) ? 0x16298 : \\\n-- \n2.30.2\n\n"
  },
  {
    "path": "package/kernel/mac80211/patches/ath9k/600-v5.16-ath9k-fetch-calibration-data-via-nvmem-subsystem.patch",
    "content": "From dab16ef495dbb3cabb355b6c80f0771a4a25e35d Mon Sep 17 00:00:00 2001\nFrom: Christian Lamparter <chunkeey@gmail.com>\nDate: Fri, 20 Aug 2021 22:44:52 +0200\nSubject: [PATCH] ath9k: fetch calibration data via nvmem subsystem\n\nOn most embedded ath9k devices (like range extenders,\nrouters, accesspoints, ...) the calibration data is\nstored in a MTD partitions named \"ART\", or \"caldata\"/\n\"calibration\".\n\nEver since commit\n4b361cfa8624 (\"mtd: core: add OTP nvmem provider support\")\nall MTD partitions are all automatically available through\nthe nvmem subsystem. This allows drivers like ath9k to read\nthe necessary data without needing any userspace helpers\nthat would do this extraction.\n\nSigned-off-by: Christian Lamparter <chunkeey@gmail.com>\n---\n\nincludes:\n\nFrom 57671351379b2051cfb07fc14e0bead9916a0880 Mon Sep 17 00:00:00 2001\nFrom: Dan Carpenter <dan.carpenter@oracle.com>\nDate: Mon, 11 Oct 2021 18:18:01 +0300\nSubject: ath9k: fix an IS_ERR() vs NULL check\n\nThe devm_kmemdup() function doesn't return error pointers, it returns\nNULL on error.\n\nFixes: eb3a97a69be8 (\"ath9k: fetch calibration data via nvmem subsystem\")\nSigned-off-by: Dan Carpenter <dan.carpenter@oracle.com>\nSigned-off-by: Kalle Valo <kvalo@codeaurora.org>\nLink: https://lore.kernel.org/r/20211011123533.GA15188@kili\n\n---\n\n--- a/drivers/net/wireless/ath/ath9k/eeprom.c\n+++ b/drivers/net/wireless/ath/ath9k/eeprom.c\n@@ -135,13 +135,23 @@ static bool ath9k_hw_nvram_read_firmware\n \t\t\t\t\t offset, data);\n }\n \n+static bool ath9k_hw_nvram_read_nvmem(struct ath_hw *ah, off_t offset,\n+\t\t\t\t      u16 *data)\n+{\n+\treturn ath9k_hw_nvram_read_array(ah->nvmem_blob,\n+\t\t\t\t\t ah->nvmem_blob_len / sizeof(u16),\n+\t\t\t\t\t offset, data);\n+}\n+\n bool ath9k_hw_nvram_read(struct ath_hw *ah, u32 off, u16 *data)\n {\n \tstruct ath_common *common = ath9k_hw_common(ah);\n \tstruct ath9k_platform_data *pdata = ah->dev->platform_data;\n \tbool ret;\n \n-\tif (ah->eeprom_blob)\n+\tif (ah->nvmem_blob)\n+\t\tret = ath9k_hw_nvram_read_nvmem(ah, off, data);\n+\telse if (ah->eeprom_blob)\n \t\tret = ath9k_hw_nvram_read_firmware(ah->eeprom_blob, off, data);\n \telse if (pdata && !pdata->use_eeprom)\n \t\tret = ath9k_hw_nvram_read_pdata(pdata, off, data);\n--- a/drivers/net/wireless/ath/ath9k/hw.h\n+++ b/drivers/net/wireless/ath/ath9k/hw.h\n@@ -988,6 +988,8 @@ struct ath_hw {\n \tbool disable_5ghz;\n \n \tconst struct firmware *eeprom_blob;\n+\tu16 *nvmem_blob;\t/* devres managed */\n+\tsize_t nvmem_blob_len;\n \n \tstruct ath_dynack dynack;\n \n--- a/drivers/net/wireless/ath/ath9k/init.c\n+++ b/drivers/net/wireless/ath/ath9k/init.c\n@@ -22,6 +22,7 @@\n #include <linux/module.h>\n #include <linux/of.h>\n #include <linux/of_net.h>\n+#include <linux/nvmem-consumer.h>\n #include <linux/relay.h>\n #include <linux/dmi.h>\n #include <net/ieee80211_radiotap.h>\n@@ -568,6 +569,57 @@ static void ath9k_eeprom_release(struct\n \trelease_firmware(sc->sc_ah->eeprom_blob);\n }\n \n+static int ath9k_nvmem_request_eeprom(struct ath_softc *sc)\n+{\n+\tstruct ath_hw *ah = sc->sc_ah;\n+\tstruct nvmem_cell *cell;\n+\tvoid *buf;\n+\tsize_t len;\n+\tint err;\n+\n+\tcell = devm_nvmem_cell_get(sc->dev, \"calibration\");\n+\tif (IS_ERR(cell)) {\n+\t\terr = PTR_ERR(cell);\n+\n+\t\t/* nvmem cell might not be defined, or the nvmem\n+\t\t * subsystem isn't included. In this case, follow\n+\t\t * the established \"just return 0;\" convention of\n+\t\t * ath9k_init_platform to say:\n+\t\t * \"All good. Nothing to see here. Please go on.\"\n+\t\t */\n+\t\tif (err == -ENOENT || err == -EOPNOTSUPP)\n+\t\t\treturn 0;\n+\n+\t\treturn err;\n+\t}\n+\n+\tbuf = nvmem_cell_read(cell, &len);\n+\tif (IS_ERR(buf))\n+\t\treturn PTR_ERR(buf);\n+\n+\t/* run basic sanity checks on the returned nvram cell length.\n+\t * That length has to be a multiple of a \"u16\" (i.e.: & 1).\n+\t * Furthermore, it has to be more than \"let's say\" 512 bytes\n+\t * but less than the maximum of AR9300_EEPROM_SIZE (16kb).\n+\t */\n+\tif (((len & 1) == 1) || (len < 512) || (len >= AR9300_EEPROM_SIZE)) {\n+\t\tkfree(buf);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\t/* devres manages the calibration values release on shutdown */\n+\tah->nvmem_blob = (u16 *)devm_kmemdup(sc->dev, buf, len, GFP_KERNEL);\n+\tkfree(buf);\n+\tif (!ah->nvmem_blob)\n+\t\treturn -ENOMEM;\n+\n+\tah->nvmem_blob_len = len;\n+\tah->ah_flags &= ~AH_USE_EEPROM;\n+\tah->ah_flags |= AH_NO_EEP_SWAP;\n+\n+\treturn 0;\n+}\n+\n static int ath9k_init_platform(struct ath_softc *sc)\n {\n \tstruct ath9k_platform_data *pdata = sc->dev->platform_data;\n@@ -710,6 +762,10 @@ static int ath9k_init_softc(u16 devid, s\n \tif (ret)\n \t\treturn ret;\n \n+\tret = ath9k_nvmem_request_eeprom(sc);\n+\tif (ret)\n+\t\treturn ret;\n+\n \tif (ath9k_led_active_high != -1)\n \t\tah->config.led_active_high = ath9k_led_active_high == 1;\n \n"
  },
  {
    "path": "package/kernel/mac80211/patches/ath9k/601-v5.16-ath9k-owl-loader-fetch-pci-init-values-through-nvmem.patch",
    "content": "From 9bf31835f11aa3c4fe5a9c1f7462c199c5d8e7ca Mon Sep 17 00:00:00 2001\nFrom: Christian Lamparter <chunkeey@gmail.com>\nDate: Sat, 21 Aug 2021 00:22:39 +0200\nSubject: [PATCH] ath9k: owl-loader: fetch pci init values through nvmem\n\nextends the owl loader to fetch important pci initialization\nvalues - which are stored together with the calibration data -\nthrough the nvmem subsystem.\n\nThis allows for much faster WIFI/ath9k initializations on devices\nthat do not require to perform any post-processing (like XOR'ing/\nreversal or unpacking) since no userspace helper is required.\n\nSigned-off-by: Christian Lamparter <chunkeey@gmail.com>\n---\n .../wireless/ath/ath9k/ath9k_pci_owl_loader.c | 105 +++++++++++++-----\n 1 file changed, 76 insertions(+), 29 deletions(-)\n\n--- a/drivers/net/wireless/ath/ath9k/ath9k_pci_owl_loader.c\n+++ b/drivers/net/wireless/ath/ath9k/ath9k_pci_owl_loader.c\n@@ -19,9 +19,14 @@\n #include <linux/delay.h>\n #include <linux/platform_device.h>\n #include <linux/ath9k_platform.h>\n+#include <linux/nvmem-consumer.h>\n+#include <linux/workqueue.h>\n \n struct owl_ctx {\n+\tstruct pci_dev *pdev;\n \tstruct completion eeprom_load;\n+\tstruct work_struct work;\n+\tstruct nvmem_cell *cell;\n };\n \n #define EEPROM_FILENAME_LEN 100\n@@ -42,6 +47,12 @@ static int ath9k_pci_fixup(struct pci_de\n \tu32 bar0;\n \tbool swap_needed = false;\n \n+\t/* also note that we are doing *u16 operations on the file */\n+\tif (cal_len > 4096 || cal_len < 0x200 || (cal_len & 1) == 1) {\n+\t\tdev_err(&pdev->dev, \"eeprom has an invalid size.\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n \tif (*cal_data != AR5416_EEPROM_MAGIC) {\n \t\tif (*cal_data != swab16(AR5416_EEPROM_MAGIC)) {\n \t\t\tdev_err(&pdev->dev, \"invalid calibration data\\n\");\n@@ -99,38 +110,31 @@ static int ath9k_pci_fixup(struct pci_de\n \treturn 0;\n }\n \n-static void owl_fw_cb(const struct firmware *fw, void *context)\n+static void owl_rescan(struct pci_dev *pdev)\n {\n-\tstruct pci_dev *pdev = (struct pci_dev *)context;\n-\tstruct owl_ctx *ctx = (struct owl_ctx *)pci_get_drvdata(pdev);\n-\tstruct pci_bus *bus;\n-\n-\tcomplete(&ctx->eeprom_load);\n-\n-\tif (!fw) {\n-\t\tdev_err(&pdev->dev, \"no eeprom data received.\\n\");\n-\t\tgoto release;\n-\t}\n-\n-\t/* also note that we are doing *u16 operations on the file */\n-\tif (fw->size > 4096 || fw->size < 0x200 || (fw->size & 1) == 1) {\n-\t\tdev_err(&pdev->dev, \"eeprom file has an invalid size.\\n\");\n-\t\tgoto release;\n-\t}\n-\n-\tif (ath9k_pci_fixup(pdev, (const u16 *)fw->data, fw->size))\n-\t\tgoto release;\n+\tstruct pci_bus *bus = pdev->bus;\n \n \tpci_lock_rescan_remove();\n-\tbus = pdev->bus;\n \tpci_stop_and_remove_bus_device(pdev);\n \t/* the device should come back with the proper\n \t * ProductId. But we have to initiate a rescan.\n \t */\n \tpci_rescan_bus(bus);\n \tpci_unlock_rescan_remove();\n+}\n+\n+static void owl_fw_cb(const struct firmware *fw, void *context)\n+{\n+\tstruct owl_ctx *ctx = (struct owl_ctx *)context;\n+\n+\tcomplete(&ctx->eeprom_load);\n \n-release:\n+\tif (fw) {\n+\t\tath9k_pci_fixup(ctx->pdev, (const u16 *)fw->data, fw->size);\n+\t\towl_rescan(ctx->pdev);\n+\t} else {\n+\t\tdev_err(&ctx->pdev->dev, \"no eeprom data received.\\n\");\n+\t}\n \trelease_firmware(fw);\n }\n \n@@ -152,6 +156,43 @@ static const char *owl_get_eeprom_name(s\n \treturn eeprom_name;\n }\n \n+static void owl_nvmem_work(struct work_struct *work)\n+{\n+\tstruct owl_ctx *ctx = container_of(work, struct owl_ctx, work);\n+\tvoid *buf;\n+\tsize_t len;\n+\n+\tcomplete(&ctx->eeprom_load);\n+\n+\tbuf = nvmem_cell_read(ctx->cell, &len);\n+\tif (!IS_ERR(buf)) {\n+\t\tath9k_pci_fixup(ctx->pdev, buf, len);\n+\t\tkfree(buf);\n+\t\towl_rescan(ctx->pdev);\n+\t} else {\n+\t\tdev_err(&ctx->pdev->dev, \"no nvmem data received.\\n\");\n+\t}\n+}\n+\n+static int owl_nvmem_probe(struct owl_ctx *ctx)\n+{\n+\tint err;\n+\n+\tctx->cell = devm_nvmem_cell_get(&ctx->pdev->dev, \"calibration\");\n+\tif (IS_ERR(ctx->cell)) {\n+\t\terr = PTR_ERR(ctx->cell);\n+\t\tif (err == -ENOENT || err == -EOPNOTSUPP)\n+\t\t\treturn 1; /* not present, try firmware_request */\n+\n+\t\treturn err;\n+\t}\n+\n+\tINIT_WORK(&ctx->work, owl_nvmem_work);\n+\tschedule_work(&ctx->work);\n+\n+\treturn 0;\n+}\n+\n static int owl_probe(struct pci_dev *pdev,\n \t\t     const struct pci_device_id *id)\n {\n@@ -164,21 +205,27 @@ static int owl_probe(struct pci_dev *pde\n \n \tpcim_pin_device(pdev);\n \n-\teeprom_name = owl_get_eeprom_name(pdev);\n-\tif (!eeprom_name) {\n-\t\tdev_err(&pdev->dev, \"no eeprom filename found.\\n\");\n-\t\treturn -ENODEV;\n-\t}\n-\n \tctx = devm_kzalloc(&pdev->dev, sizeof(*ctx), GFP_KERNEL);\n \tif (!ctx)\n \t\treturn -ENOMEM;\n \n \tinit_completion(&ctx->eeprom_load);\n+\tctx->pdev = pdev;\n \n \tpci_set_drvdata(pdev, ctx);\n+\n+\terr = owl_nvmem_probe(ctx);\n+\tif (err <= 0)\n+\t\treturn err;\n+\n+\teeprom_name = owl_get_eeprom_name(pdev);\n+\tif (!eeprom_name) {\n+\t\tdev_err(&pdev->dev, \"no eeprom filename found.\\n\");\n+\t\treturn -ENODEV;\n+\t}\n+\n \terr = request_firmware_nowait(THIS_MODULE, true, eeprom_name,\n-\t\t\t\t      &pdev->dev, GFP_KERNEL, pdev, owl_fw_cb);\n+\t\t\t\t      &pdev->dev, GFP_KERNEL, ctx, owl_fw_cb);\n \tif (err)\n \t\tdev_err(&pdev->dev, \"failed to request caldata (%d).\\n\", err);\n \n"
  },
  {
    "path": "package/kernel/mac80211/patches/brcm/040-brcmutil_option.patch",
    "content": "--- a/drivers/net/wireless/broadcom/brcm80211/Kconfig\n+++ b/drivers/net/wireless/broadcom/brcm80211/Kconfig\n@@ -1,6 +1,6 @@\n # SPDX-License-Identifier: GPL-2.0-only\n config BRCMUTIL\n-\ttristate\n+\ttristate \"Broadcom 802.11 driver utility functions\"\n \tdepends on m\n \n config BRCMSMAC\n"
  },
  {
    "path": "package/kernel/mac80211/patches/brcm/810-b43-gpio-mask-module-option.patch",
    "content": "--- a/drivers/net/wireless/broadcom/b43/b43.h\n+++ b/drivers/net/wireless/broadcom/b43/b43.h\n@@ -840,6 +840,7 @@ struct b43_wldev {\n \tbool qos_enabled;\t\t/* TRUE, if QoS is used. */\n \tbool hwcrypto_enabled;\t\t/* TRUE, if HW crypto acceleration is enabled. */\n \tbool use_pio;\t\t\t/* TRUE if next init should use PIO */\n+\tint gpiomask;\t\t\t/* GPIO LED mask as a module parameter */\n \n \t/* PHY/Radio device. */\n \tstruct b43_phy phy;\n--- a/drivers/net/wireless/broadcom/b43/main.c\n+++ b/drivers/net/wireless/broadcom/b43/main.c\n@@ -72,6 +72,11 @@ MODULE_FIRMWARE(\"b43/ucode40.fw\");\n MODULE_FIRMWARE(\"b43/ucode42.fw\");\n MODULE_FIRMWARE(\"b43/ucode9.fw\");\n \n+static int modparam_gpiomask = 0x000F;\n+module_param_named(gpiomask, modparam_gpiomask, int, 0444);\n+MODULE_PARM_DESC(gpiomask,\n+         \"GPIO mask for LED control (default 0x000F)\");\n+\n static int modparam_bad_frames_preempt;\n module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);\n MODULE_PARM_DESC(bad_frames_preempt,\n@@ -2869,10 +2874,10 @@ static int b43_gpio_init(struct b43_wlde\n \tu32 mask, set;\n \n \tb43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_GPOUTSMSK, 0);\n-\tb43_maskset16(dev, B43_MMIO_GPIO_MASK, ~0, 0xF);\n+\tb43_maskset16(dev, B43_MMIO_GPIO_MASK, ~0, modparam_gpiomask);\n \n \tmask = 0x0000001F;\n-\tset = 0x0000000F;\n+\tset = modparam_gpiomask;\n \tif (dev->dev->chip_id == 0x4301) {\n \t\tmask |= 0x0060;\n \t\tset |= 0x0060;\n"
  },
  {
    "path": "package/kernel/mac80211/patches/brcm/811-b43_no_pio.patch",
    "content": "--- a/drivers/net/wireless/broadcom/b43/Makefile\n+++ b/drivers/net/wireless/broadcom/b43/Makefile\n@@ -18,7 +18,7 @@ b43-$(CPTCFG_B43_PHY_AC)\t+= phy_ac.o\n b43-y\t\t\t\t+= sysfs.o\n b43-y\t\t\t\t+= xmit.o\n b43-y\t\t\t\t+= dma.o\n-b43-y\t\t\t\t+= pio.o\n+b43-$(CPTCFG_B43_PIO)\t\t+= pio.o\n b43-y\t\t\t\t+= rfkill.o\n b43-y\t\t\t\t+= ppr.o\n b43-$(CPTCFG_B43_LEDS)\t\t+= leds.o\n--- a/drivers/net/wireless/broadcom/b43/main.c\n+++ b/drivers/net/wireless/broadcom/b43/main.c\n@@ -2001,10 +2001,12 @@ static void b43_do_interrupt_thread(stru\n \t\t\tdma_reason[0], dma_reason[1],\n \t\t\tdma_reason[2], dma_reason[3],\n \t\t\tdma_reason[4], dma_reason[5]);\n+#ifdef CPTCFG_B43_PIO\n \t\tb43err(dev->wl, \"This device does not support DMA \"\n \t\t\t       \"on your system. It will now be switched to PIO.\\n\");\n \t\t/* Fall back to PIO transfers if we get fatal DMA errors! */\n \t\tdev->use_pio = true;\n+#endif\n \t\tb43_controller_restart(dev, \"DMA error\");\n \t\treturn;\n \t}\n--- a/drivers/net/wireless/broadcom/b43/pio.h\n+++ b/drivers/net/wireless/broadcom/b43/pio.h\n@@ -151,7 +151,7 @@ static inline void b43_piorx_write32(str\n \tb43_write32(q->dev, q->mmio_base + offset, value);\n }\n \n-\n+#ifdef CPTCFG_B43_PIO\n int b43_pio_init(struct b43_wldev *dev);\n void b43_pio_free(struct b43_wldev *dev);\n \n@@ -162,5 +162,37 @@ void b43_pio_rx(struct b43_pio_rxqueue *\n \n void b43_pio_tx_suspend(struct b43_wldev *dev);\n void b43_pio_tx_resume(struct b43_wldev *dev);\n+#else\n+static inline int b43_pio_init(struct b43_wldev *dev)\n+{\n+\treturn 0;\n+}\n+\n+static inline void b43_pio_free(struct b43_wldev *dev)\n+{\n+}\n+\n+static inline int b43_pio_tx(struct b43_wldev *dev, struct sk_buff *skb)\n+{\n+\treturn 0;\n+}\n+\n+static inline void b43_pio_handle_txstatus(struct b43_wldev *dev,\n+\t\t\t\t\t   const struct b43_txstatus *status)\n+{\n+}\n+\n+static inline void b43_pio_rx(struct b43_pio_rxqueue *q)\n+{\n+}\n+\n+static inline void b43_pio_tx_suspend(struct b43_wldev *dev)\n+{\n+}\n+\n+static inline void b43_pio_tx_resume(struct b43_wldev *dev)\n+{\n+}\n+#endif /* CPTCFG_B43_PIO */\n \n #endif /* B43_PIO_H_ */\n--- a/drivers/net/wireless/broadcom/b43/Kconfig\n+++ b/drivers/net/wireless/broadcom/b43/Kconfig\n@@ -100,7 +100,7 @@ config B43_BCMA_PIO\n \tdefault y\n \n config B43_PIO\n-\tbool\n+\tbool \"Broadcom 43xx PIO support\"\n \tdepends on B43 && B43_SSB\n \tdepends on SSB_BLOCKIO\n \tdefault y\n"
  },
  {
    "path": "package/kernel/mac80211/patches/brcm/812-b43-add-antenna-control.patch",
    "content": "--- a/drivers/net/wireless/broadcom/b43/main.c\n+++ b/drivers/net/wireless/broadcom/b43/main.c\n@@ -1643,7 +1643,7 @@ static void b43_write_beacon_template(st\n \t\t\t\t  len, ram_offset, shm_size_offset, rate);\n \n \t/* Write the PHY TX control parameters. */\n-\tantenna = B43_ANTENNA_DEFAULT;\n+\tantenna = dev->tx_antenna;\n \tantenna = b43_antenna_to_phyctl(antenna);\n \tctl = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL);\n \t/* We can't send beacons with short preamble. Would get PHY errors. */\n@@ -3284,8 +3284,8 @@ static int b43_chip_init(struct b43_wlde\n \n \t/* Select the antennae */\n \tif (phy->ops->set_rx_antenna)\n-\t\tphy->ops->set_rx_antenna(dev, B43_ANTENNA_DEFAULT);\n-\tb43_mgmtframe_txantenna(dev, B43_ANTENNA_DEFAULT);\n+\t\tphy->ops->set_rx_antenna(dev, dev->rx_antenna);\n+\tb43_mgmtframe_txantenna(dev, dev->tx_antenna);\n \n \tif (phy->type == B43_PHYTYPE_B) {\n \t\tvalue16 = b43_read16(dev, 0x005E);\n@@ -3985,7 +3985,6 @@ static int b43_op_config(struct ieee8021\n \tstruct b43_wldev *dev = wl->current_dev;\n \tstruct b43_phy *phy = &dev->phy;\n \tstruct ieee80211_conf *conf = &hw->conf;\n-\tint antenna;\n \tint err = 0;\n \n \tmutex_lock(&wl->mutex);\n@@ -4028,11 +4027,9 @@ static int b43_op_config(struct ieee8021\n \t}\n \n \t/* Antennas for RX and management frame TX. */\n-\tantenna = B43_ANTENNA_DEFAULT;\n-\tb43_mgmtframe_txantenna(dev, antenna);\n-\tantenna = B43_ANTENNA_DEFAULT;\n+\tb43_mgmtframe_txantenna(dev, dev->tx_antenna);\n \tif (phy->ops->set_rx_antenna)\n-\t\tphy->ops->set_rx_antenna(dev, antenna);\n+\t\tphy->ops->set_rx_antenna(dev, dev->rx_antenna);\n \n \tif (wl->radio_enabled != phy->radio_on) {\n \t\tif (wl->radio_enabled) {\n@@ -5175,6 +5172,47 @@ static int b43_op_get_survey(struct ieee\n \treturn 0;\n }\n \n+static int b43_op_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant)\n+{\n+\tstruct b43_wl *wl = hw_to_b43_wl(hw);\n+\tstruct b43_wldev *dev = wl->current_dev;\n+\n+\tif (tx_ant == 1 && rx_ant == 1) {\n+\t\tdev->tx_antenna = B43_ANTENNA0;\n+\t\tdev->rx_antenna = B43_ANTENNA0;\n+\t}\n+\telse if (tx_ant == 2 && rx_ant == 2) {\n+\t\tdev->tx_antenna = B43_ANTENNA1;\n+\t\tdev->rx_antenna = B43_ANTENNA1;\n+\t}\n+\telse if ((tx_ant & 3) == 3 && (rx_ant & 3) == 3) {\n+\t\tdev->tx_antenna = B43_ANTENNA_DEFAULT;\n+\t\tdev->rx_antenna = B43_ANTENNA_DEFAULT;\n+\t}\n+\telse {\n+\t\treturn -EINVAL;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+\n+static int b43_op_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant)\n+{\n+\tstruct b43_wl *wl = hw_to_b43_wl(hw);\n+\tstruct b43_wldev *dev = wl->current_dev;\n+\n+\tswitch (dev->tx_antenna) {\n+\tcase B43_ANTENNA0:\n+\t\t*tx_ant = 1; *rx_ant = 1; break;\n+\tcase B43_ANTENNA1:\n+\t\t*tx_ant = 2; *rx_ant = 2; break;\n+\tcase B43_ANTENNA_DEFAULT:\n+\t\t*tx_ant = 3; *rx_ant = 3; break;\n+\t}\n+\treturn 0;\n+}\n+\n static const struct ieee80211_ops b43_hw_ops = {\n \t.tx\t\t\t= b43_op_tx,\n \t.conf_tx\t\t= b43_op_conf_tx,\n@@ -5196,6 +5234,8 @@ static const struct ieee80211_ops b43_hw\n \t.sw_scan_complete\t= b43_op_sw_scan_complete_notifier,\n \t.get_survey\t\t= b43_op_get_survey,\n \t.rfkill_poll\t\t= b43_rfkill_poll,\n+\t.set_antenna\t\t= b43_op_set_antenna,\n+\t.get_antenna\t\t= b43_op_get_antenna,\n };\n \n /* Hard-reset the chip. Do not call this directly.\n@@ -5497,6 +5537,8 @@ static int b43_one_core_attach(struct b4\n \tif (!wldev)\n \t\tgoto out;\n \n+\twldev->rx_antenna = B43_ANTENNA_DEFAULT;\n+\twldev->tx_antenna = B43_ANTENNA_DEFAULT;\n \twldev->use_pio = b43_modparam_pio;\n \twldev->dev = dev;\n \twldev->wl = wl;\n@@ -5588,6 +5630,9 @@ static struct b43_wl *b43_wireless_init(\n \n \twiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CQM_RSSI_LIST);\n \n+\thw->wiphy->available_antennas_rx = 0x3;\n+\thw->wiphy->available_antennas_tx = 0x3;\n+\n \twl->hw_registered = false;\n \thw->max_rates = 2;\n \tSET_IEEE80211_DEV(hw, dev->dev);\n--- a/drivers/net/wireless/broadcom/b43/b43.h\n+++ b/drivers/net/wireless/broadcom/b43/b43.h\n@@ -841,6 +841,8 @@ struct b43_wldev {\n \tbool hwcrypto_enabled;\t\t/* TRUE, if HW crypto acceleration is enabled. */\n \tbool use_pio;\t\t\t/* TRUE if next init should use PIO */\n \tint gpiomask;\t\t\t/* GPIO LED mask as a module parameter */\n+\tint rx_antenna;\t\t\t/* Used RX antenna (B43_ANTENNAxxx) */\n+\tint tx_antenna;\t\t\t/* Used TX antenna (B43_ANTENNAxxx) */\n \n \t/* PHY/Radio device. */\n \tstruct b43_phy phy;\n"
  },
  {
    "path": "package/kernel/mac80211/patches/brcm/813-b43-reduce-number-of-RX-slots.patch",
    "content": "--- a/drivers/net/wireless/broadcom/b43/dma.h\n+++ b/drivers/net/wireless/broadcom/b43/dma.h\n@@ -170,7 +170,7 @@ struct b43_dmadesc_generic {\n \n /* DMA engine tuning knobs */\n #define B43_TXRING_SLOTS\t\t256\n-#define B43_RXRING_SLOTS\t\t256\n+#define B43_RXRING_SLOTS\t\t32\n #define B43_DMA0_RX_FW598_BUFSIZE\t(B43_DMA0_RX_FW598_FO + IEEE80211_MAX_FRAME_LEN)\n #define B43_DMA0_RX_FW351_BUFSIZE\t(B43_DMA0_RX_FW351_FO + IEEE80211_MAX_FRAME_LEN)\n \n"
  },
  {
    "path": "package/kernel/mac80211/patches/brcm/814-b43-only-use-gpio-0-1-for-led.patch",
    "content": "--- a/drivers/net/wireless/broadcom/b43/main.c\n+++ b/drivers/net/wireless/broadcom/b43/main.c\n@@ -2886,6 +2886,14 @@ static int b43_gpio_init(struct b43_wlde\n \t} else if (dev->dev->chip_id == 0x5354) {\n \t\t/* Don't allow overtaking buttons GPIOs */\n \t\tset &= 0x2; /* 0x2 is LED GPIO on BCM5354 */\n+\t} else if (dev->dev->chip_id == BCMA_CHIP_ID_BCM4716 || \n+\t\t   dev->dev->chip_id == BCMA_CHIP_ID_BCM47162 ||\n+\t\t   dev->dev->chip_id == BCMA_CHIP_ID_BCM5356 ||\n+\t\t   dev->dev->chip_id == BCMA_CHIP_ID_BCM5357 ||\n+\t\t   dev->dev->chip_id == BCMA_CHIP_ID_BCM53572) {\n+\t\t/* just use gpio 0 and 1 for 2.4 GHz wifi led */\n+\t\tset &= 0x3;\n+\t\tmask &= 0x3;\n \t}\n \n \tif (0 /* FIXME: conditional unknown */ ) {\n"
  },
  {
    "path": "package/kernel/mac80211/patches/brcm/815-b43-always-take-overlapping-devs.patch",
    "content": "--- a/drivers/net/wireless/broadcom/b43/main.c\n+++ b/drivers/net/wireless/broadcom/b43/main.c\n@@ -114,7 +114,7 @@ static int b43_modparam_pio = 0;\n module_param_named(pio, b43_modparam_pio, int, 0644);\n MODULE_PARM_DESC(pio, \"Use PIO accesses by default: 0=DMA, 1=PIO\");\n \n-static int modparam_allhwsupport = !IS_ENABLED(CPTCFG_BRCMSMAC);\n+static int modparam_allhwsupport = 1;\n module_param_named(allhwsupport, modparam_allhwsupport, int, 0444);\n MODULE_PARM_DESC(allhwsupport, \"Enable support for all hardware (even it if overlaps with the brcmsmac driver)\");\n \n"
  },
  {
    "path": "package/kernel/mac80211/patches/brcm/850-brcmsmac-remove-extra-regulation-restriction.patch",
    "content": "--- a/drivers/net/wireless/broadcom/brcm80211/brcmsmac/channel.c\n+++ b/drivers/net/wireless/broadcom/brcm80211/brcmsmac/channel.c\n@@ -58,19 +58,12 @@\n \t\t\t\t (((c) < 149) ? 3 : 4))))\n \n #define BRCM_2GHZ_2412_2462\tREG_RULE(2412-10, 2462+10, 40, 0, 19, 0)\n-#define BRCM_2GHZ_2467_2472\tREG_RULE(2467-10, 2472+10, 20, 0, 19, \\\n-\t\t\t\t\t NL80211_RRF_NO_IR)\n+#define BRCM_2GHZ_2467_2472\tREG_RULE(2467-10, 2472+10, 20, 0, 19, 0)\n \n-#define BRCM_5GHZ_5180_5240\tREG_RULE(5180-10, 5240+10, 40, 0, 21, \\\n-\t\t\t\t\t NL80211_RRF_NO_IR)\n-#define BRCM_5GHZ_5260_5320\tREG_RULE(5260-10, 5320+10, 40, 0, 21, \\\n-\t\t\t\t\t NL80211_RRF_DFS | \\\n-\t\t\t\t\t NL80211_RRF_NO_IR)\n-#define BRCM_5GHZ_5500_5700\tREG_RULE(5500-10, 5700+10, 40, 0, 21, \\\n-\t\t\t\t\t NL80211_RRF_DFS | \\\n-\t\t\t\t\t NL80211_RRF_NO_IR)\n-#define BRCM_5GHZ_5745_5825\tREG_RULE(5745-10, 5825+10, 40, 0, 21, \\\n-\t\t\t\t\t NL80211_RRF_NO_IR)\n+#define BRCM_5GHZ_5180_5240\tREG_RULE(5180-10, 5240+10, 40, 0, 21, 0)\n+#define BRCM_5GHZ_5260_5320\tREG_RULE(5260-10, 5320+10, 40, 0, 21, 0)\n+#define BRCM_5GHZ_5500_5700\tREG_RULE(5500-10, 5700+10, 40, 0, 21, 0)\n+#define BRCM_5GHZ_5745_5825\tREG_RULE(5745-10, 5825+10, 40, 0, 21, 0)\n \n static const struct ieee80211_regdomain brcms_regdom_x2 = {\n \t.n_reg_rules = 6,\n"
  },
  {
    "path": "package/kernel/mac80211/patches/brcm/860-brcmfmac-register-wiphy-s-during-module_init.patch",
    "content": "From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <zajec5@gmail.com>\nDate: Mon, 8 Jun 2015 16:11:40 +0200\nSubject: [PATCH] brcmfmac: register wiphy(s) during module_init\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nThis is needed by OpenWrt which expects all PHYs to be created after\nmodule loads successfully.\n\nSigned-off-by: Rafał Miłecki <zajec5@gmail.com>\n---\n\n--- a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/firmware.c\n+++ b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/firmware.c\n@@ -431,6 +431,7 @@ struct brcmf_fw {\n \tstruct brcmf_fw_request *req;\n \tu32 curpos;\n \tvoid (*done)(struct device *dev, int err, struct brcmf_fw_request *req);\n+\tstruct completion *completion;\n };\n \n #ifdef CONFIG_EFI\n@@ -655,6 +656,8 @@ static void brcmf_fw_request_done(const\n \t\tfwctx->req = NULL;\n \t}\n \tfwctx->done(fwctx->dev, ret, fwctx->req);\n+\tif (fwctx->completion)\n+\t\tcomplete(fwctx->completion);\n \tkfree(fwctx);\n }\n \n@@ -695,6 +698,8 @@ int brcmf_fw_get_firmwares(struct device\n {\n \tstruct brcmf_fw_item *first = &req->items[0];\n \tstruct brcmf_fw *fwctx;\n+\tstruct completion completion;\n+\tunsigned long time_left;\n \tchar *alt_path = NULL;\n \tint ret;\n \n@@ -712,6 +717,9 @@ int brcmf_fw_get_firmwares(struct device\n \tfwctx->dev = dev;\n \tfwctx->req = req;\n \tfwctx->done = fw_cb;\n+ \n+\tinit_completion(&completion);\n+\tfwctx->completion = &completion;\n \n \t/* First try alternative board-specific path if any */\n \tif (fwctx->req->board_type)\n@@ -730,6 +738,12 @@ int brcmf_fw_get_firmwares(struct device\n \tif (ret < 0)\n \t\tbrcmf_fw_request_done(NULL, fwctx);\n \n+\n+\ttime_left = wait_for_completion_timeout(&completion,\n+\t\t\t\t\t\tmsecs_to_jiffies(5000));\n+\tif (!time_left && fwctx)\n+\t\tfwctx->completion = NULL;\n+\n \treturn 0;\n }\n \n"
  },
  {
    "path": "package/kernel/mac80211/patches/brcm/861-brcmfmac-workaround-bug-with-some-inconsistent-BSSes.patch",
    "content": "From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <zajec5@gmail.com>\nDate: Thu, 9 Jul 2015 00:07:59 +0200\nSubject: [PATCH] brcmfmac: workaround bug with some inconsistent BSSes state\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nSigned-off-by: Rafał Miłecki <zajec5@gmail.com>\n---\n\n--- a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c\n+++ b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c\n@@ -715,8 +715,36 @@ static struct wireless_dev *brcmf_cfg802\n \tstruct brcmf_cfg80211_info *cfg = wiphy_to_cfg(wiphy);\n \tstruct brcmf_pub *drvr = cfg->pub;\n \tstruct wireless_dev *wdev;\n+\tstruct net_device *dev;\n \tint err;\n \n+\t/*\n+\t * There is a bug with in-firmware BSS management. When adding virtual\n+\t * interface brcmfmac first tells firmware to create new BSS and then\n+\t * it creates new struct net_device.\n+\t *\n+\t * If creating/registering netdev(ice) fails, BSS remains in some bugged\n+\t * state. It conflicts with existing BSSes by overtaking their auth\n+\t * requests.\n+\t *\n+\t * It results in one BSS (addresss X) sending beacons and another BSS\n+\t * (address Y) replying to authentication requests. This makes interface\n+\t * unusable as AP.\n+\t *\n+\t * To workaround this bug we may try to guess if register_netdev(ice)\n+\t * will fail. The most obvious case is using interface name that already\n+\t * exists. This is actually quite likely with brcmfmac & some user space\n+\t * scripts as brcmfmac doesn't allow deleting virtual interfaces.\n+\t * So this bug can be triggered even by something trivial like:\n+\t * iw dev wlan0 delete\n+\t * iw phy phy0 interface add wlan0 type __ap\n+\t */\n+\tdev = dev_get_by_name(&init_net, name);\n+\tif (dev) {\n+\t\tdev_put(dev);\n+\t\treturn ERR_PTR(-ENFILE);\n+\t}\n+\n \tbrcmf_dbg(TRACE, \"enter: %s type %d\\n\", name, type);\n \terr = brcmf_vif_add_validate(wiphy_to_cfg(wiphy), type);\n \tif (err) {\n"
  },
  {
    "path": "package/kernel/mac80211/patches/brcm/862-brcmfmac-Disable-power-management.patch",
    "content": "From 66ae1b1750720a33e29792a177b1e696f4f005fb Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.org>\nDate: Wed, 9 Mar 2016 17:25:59 +0000\nSubject: [PATCH] brcmfmac: Disable power management\n\nDisable wireless power saving in the brcmfmac WLAN driver. This is a\ntemporary measure until the connectivity loss resulting from power\nsaving is resolved.\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.org>\n---\n drivers/net/wireless/brcm80211/brcmfmac/cfg80211.c | 2 ++\n 1 file changed, 2 insertions(+)\n\n--- a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c\n+++ b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c\n@@ -2974,6 +2974,10 @@ brcmf_cfg80211_set_power_mgmt(struct wip\n \t * preference in cfg struct to apply this to\n \t * FW later while initializing the dongle\n \t */\n+#if defined(CONFIG_ARCH_BCM2835)\n+\tbrcmf_dbg(INFO, \"power management disabled\\n\");\n+\tenabled = false;\n+#endif\n \tcfg->pwr_save = enabled;\n \tif (!check_vif_up(ifp->vif)) {\n \n"
  },
  {
    "path": "package/kernel/mac80211/patches/brcm/863-brcmfmac-add-in-driver-tables-with-country-codes.patch",
    "content": "From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nSubject: [PATCH] brcmfmac: add in-driver tables with country codes\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nThis adds early support for changing region. Ideally this data should\nbe stored in DT as all these mappings are devices specific.\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\n---\n\n--- a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/of.c\n+++ b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/of.c\n@@ -58,6 +58,36 @@ static int brcmf_of_get_country_codes(st\n \treturn 0;\n }\n \n+/* TODO: FIXME: Use DT */\n+static void brcmf_of_probe_cc(struct device *dev,\n+\t\t\t      struct brcmf_mp_device *settings)\n+{\n+\tstatic struct brcmfmac_pd_cc_entry netgear_r8000_cc_ent[] = {\n+\t\t{ \"JP\", \"JP\", 78 },\n+\t\t{ \"US\", \"Q2\", 86 },\n+\t};\n+\tstruct brcmfmac_pd_cc_entry *cc_ent = NULL;\n+\tint table_size = 0;\n+\n+\tif (of_machine_is_compatible(\"netgear,r8000\")) {\n+\t\tcc_ent = netgear_r8000_cc_ent;\n+\t\ttable_size = ARRAY_SIZE(netgear_r8000_cc_ent);\n+\t}\n+\n+\tif (cc_ent && table_size) {\n+\t\tstruct brcmfmac_pd_cc *cc;\n+\t\tsize_t memsize;\n+\n+\t\tmemsize = table_size * sizeof(struct brcmfmac_pd_cc_entry);\n+\t\tcc = devm_kzalloc(dev, sizeof(*cc) + memsize, GFP_KERNEL);\n+\t\tif (!cc)\n+\t\t\treturn;\n+\t\tcc->table_size = table_size;\n+\t\tmemcpy(cc->table, cc_ent, memsize);\n+\t\tsettings->country_codes = cc;\n+\t}\n+}\n+\n void brcmf_of_probe(struct device *dev, enum brcmf_bus_type bus_type,\n \t\t    struct brcmf_mp_device *settings)\n {\n@@ -90,6 +120,8 @@ void brcmf_of_probe(struct device *dev,\n \t\tof_node_put(root);\n \t}\n \n+\tbrcmf_of_probe_cc(dev, settings);\n+\n \tif (!np || !of_device_is_compatible(np, \"brcm,bcm4329-fmac\"))\n \t\treturn;\n \n"
  },
  {
    "path": "package/kernel/mac80211/patches/brcm/864-brcmfmac-do-not-use-internal-roaming-engine-by-default.patch",
    "content": "brcmfmac: do not use internal roaming engine by default\n\nSome evidence of curing disconnects with this disabled, so make it a default.\nCan be overridden with module parameter roamoff=0\nSee: http://projectable.me/optimize-my-pi-wi-fi/\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.org>\n---\n\n--- a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/common.c\n+++ b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/common.c\n@@ -59,7 +59,11 @@ static int brcmf_fcmode;\n module_param_named(fcmode, brcmf_fcmode, int, 0);\n MODULE_PARM_DESC(fcmode, \"Mode of firmware signalled flow control\");\n \n+#if defined(CONFIG_ARCH_BCM2835)\n+static int brcmf_roamoff = 1;\n+#else\n static int brcmf_roamoff;\n+#endif\n module_param_named(roamoff, brcmf_roamoff, int, 0400);\n MODULE_PARM_DESC(roamoff, \"Do not use internal roaming engine\");\n \n"
  },
  {
    "path": "package/kernel/mac80211/patches/brcm/998-survey.patch",
    "content": "--- a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c\n+++ b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c\n@@ -2921,6 +2921,63 @@ done:\n }\n \n static int\n+brcmf_cfg80211_dump_survey(struct wiphy *wiphy, struct net_device *ndev,\n+\t\t\t   int idx, struct survey_info *survey)\n+{\n+\tstruct brcmf_cfg80211_info *cfg = wiphy_to_cfg(wiphy);\n+\tstruct brcmf_if *ifp = netdev_priv(ndev);\n+\tstruct brcmu_chan ch;\n+\tenum nl80211_band band = 0;\n+\ts32 err = 0;\n+\tint noise;\n+\tu32 freq;\n+\tu32 chanspec;\n+\n+\tmemset(survey, 0, sizeof(struct survey_info));\n+\tif (idx != 0) {\n+\t\tif (idx >= cfg->pub->num_chan_stats || cfg->pub->chan_stats == NULL)\n+\t\t\treturn -ENOENT;\n+\t\tif (cfg->pub->chan_stats[idx].freq == 0)\n+\t\t\treturn -ENOENT;\n+\t\tsurvey->filled = SURVEY_INFO_NOISE_DBM;\n+\t\tsurvey->channel = ieee80211_get_channel(wiphy, cfg->pub->chan_stats[idx].freq);\n+\t\tsurvey->noise = cfg->pub->chan_stats[idx].noise;\n+\t\treturn 0;\n+\t}\n+\n+\terr = brcmf_fil_iovar_int_get(ifp, \"chanspec\", &chanspec);\n+\tif (err) {\n+\t\tbrcmf_err(\"chanspec failed (%d)\\n\", err);\n+\t\treturn err;\n+\t}\n+\n+\tch.chspec = chanspec;\n+\tcfg->d11inf.decchspec(&ch);\n+\n+\tswitch (ch.band) {\n+\tcase BRCMU_CHAN_BAND_2G:\n+\t\tband = NL80211_BAND_2GHZ;\n+\t\tbreak;\n+\tcase BRCMU_CHAN_BAND_5G:\n+\t\tband = NL80211_BAND_5GHZ;\n+\t\tbreak;\n+\t}\n+\n+\tfreq = ieee80211_channel_to_frequency(ch.control_ch_num, band);\n+\tsurvey->channel = ieee80211_get_channel(wiphy, freq);\n+\n+\terr = brcmf_fil_cmd_int_get(ifp, BRCMF_C_GET_PHY_NOISE, &noise);\n+\tif (err) {\n+\t\tbrcmf_err(\"Could not get noise (%d)\\n\", err);\n+\t\treturn err;\n+\t}\n+\n+\tsurvey->filled = SURVEY_INFO_NOISE_DBM | SURVEY_INFO_IN_USE;\n+\tsurvey->noise = le32_to_cpu(noise);\n+\treturn 0;\n+}\n+\n+static int\n brcmf_cfg80211_dump_station(struct wiphy *wiphy, struct net_device *ndev,\n \t\t\t    int idx, u8 *mac, struct station_info *sinfo)\n {\n@@ -3021,6 +3078,7 @@ static s32 brcmf_inform_single_bss(struc\n \tstruct brcmu_chan ch;\n \tu16 channel;\n \tu32 freq;\n+\tint i;\n \tu16 notify_capability;\n \tu16 notify_interval;\n \tu8 *notify_ie;\n@@ -3045,6 +3103,17 @@ static s32 brcmf_inform_single_bss(struc\n \t\tband = NL80211_BAND_5GHZ;\n \n \tfreq = ieee80211_channel_to_frequency(channel, band);\n+\tfor (i = 0;i < cfg->pub->num_chan_stats;i++) {\n+\t\tif (freq == cfg->pub->chan_stats[i].freq)\n+\t\t\tbreak;\n+\t\tif (cfg->pub->chan_stats[i].freq == 0)\n+\t\t\tbreak;\n+\t}\n+\tif (i < cfg->pub->num_chan_stats) {\n+\t\tcfg->pub->chan_stats[i].freq = freq;\n+\t\tcfg->pub->chan_stats[i].noise = bi->phy_noise;\n+\t}\n+\n \tbss_data.chan = ieee80211_get_channel(wiphy, freq);\n \tbss_data.scan_width = NL80211_BSS_CHAN_WIDTH_20;\n \tbss_data.boottime_ns = ktime_to_ns(ktime_get_boottime());\n@@ -5573,6 +5642,7 @@ static struct cfg80211_ops brcmf_cfg8021\n \t.leave_ibss = brcmf_cfg80211_leave_ibss,\n \t.get_station = brcmf_cfg80211_get_station,\n \t.dump_station = brcmf_cfg80211_dump_station,\n+\t.dump_survey = brcmf_cfg80211_dump_survey,\n \t.set_tx_power = brcmf_cfg80211_set_tx_power,\n \t.get_tx_power = brcmf_cfg80211_get_tx_power,\n \t.add_key = brcmf_cfg80211_add_key,\n--- a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/core.c\n+++ b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/core.c\n@@ -1361,6 +1361,8 @@ int brcmf_attach(struct device *dev)\n \n \t/* Link to bus module */\n \tdrvr->hdrlen = 0;\n+\tdrvr->chan_stats = vzalloc(256 * sizeof(struct brcmf_chan_stats));\n+\tdrvr->num_chan_stats = 256;\n \n \t/* Attach and link in the protocol */\n \tret = brcmf_proto_attach(drvr);\n@@ -1443,6 +1445,12 @@ void brcmf_detach(struct device *dev)\n \tif (drvr == NULL)\n \t\treturn;\n \n+\tdrvr->num_chan_stats = 0;\n+\tif (drvr->chan_stats) {\n+\t\tvfree(drvr->chan_stats);\n+\t\tdrvr->chan_stats = NULL;\n+\t}\n+\n #ifdef CONFIG_INET\n \tunregister_inetaddr_notifier(&drvr->inetaddr_notifier);\n #endif\n--- a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/core.h\n+++ b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/core.h\n@@ -91,6 +91,11 @@ struct brcmf_rev_info {\n \tu32 nvramrev;\n };\n \n+struct brcmf_chan_stats {\n+\tu32 freq;\n+\tint noise;\n+};\n+\n /* Common structure for module and instance linkage */\n struct brcmf_pub {\n \t/* Linkage ponters */\n@@ -100,6 +105,9 @@ struct brcmf_pub {\n \tstruct cfg80211_ops *ops;\n \tstruct brcmf_cfg80211_info *config;\n \n+\tint num_chan_stats;\n+\tstruct brcmf_chan_stats *chan_stats;\n+\n \t/* Internal brcmf items */\n \tuint hdrlen;\t\t/* Total BRCMF header length (proto + bus) */\n \n"
  },
  {
    "path": "package/kernel/mac80211/patches/build/000-fix_kconfig.patch",
    "content": "--- a/kconf/Makefile\n+++ b/kconf/Makefile\n@@ -1,9 +1,9 @@\n-CFLAGS=-Wall -Wmissing-prototypes -Wstrict-prototypes -O2 -fomit-frame-pointer\n+CFLAGS=-Wall -Wmissing-prototypes -Wstrict-prototypes -O2 -fomit-frame-pointer -DKBUILD_NO_NLS\n \n LXDIALOG := lxdialog/checklist.o lxdialog/inputbox.o lxdialog/menubox.o lxdialog/textbox.o lxdialog/util.o lxdialog/yesno.o\n \n conf: conf.o zconf.tab.o\n-mconf_CFLAGS := $(shell ./lxdialog/check-lxdialog.sh -ccflags) -DLOCALE\n+mconf_CFLAGS := $(shell ./lxdialog/check-lxdialog.sh -ccflags)\n mconf_LDFLAGS := $(shell ./lxdialog/check-lxdialog.sh -ldflags $(CC))\n mconf: CFLAGS += $(mconf_CFLAGS)\n \n"
  },
  {
    "path": "package/kernel/mac80211/patches/build/001-fix_build.patch",
    "content": "--- a/Makefile\n+++ b/Makefile\n@@ -5,7 +5,7 @@\n ifeq ($(KERNELRELEASE),)\n \n MAKEFLAGS += --no-print-directory\n-SHELL := /bin/bash\n+SHELL := /usr/bin/env bash\n BACKPORT_DIR := $(shell pwd)\n \n KMODDIR ?= updates\n@@ -19,6 +19,7 @@ KLIB_BUILD ?= $(KLIB)/build/\n KERNEL_CONFIG := $(KLIB_BUILD)/.config\n KERNEL_MAKEFILE := $(KLIB_BUILD)/Makefile\n CONFIG_MD5 := $(shell md5sum $(KERNEL_CONFIG) 2>/dev/null | sed 's/\\s.*//')\n+STAMP_KERNEL_CONFIG := .kernel_config_md5_$(CONFIG_MD5)\n \n export KLIB KLIB_BUILD BACKPORT_DIR KMODDIR KMODPATH_ARG\n \n@@ -36,7 +37,8 @@ mrproper:\n \t@rm -f .kernel_config_md5 Kconfig.versions Kconfig.kernel\n \t@rm -f backport-include/backport/autoconf.h\n \n-.DEFAULT:\n+.SILENT: $(STAMP_KERNEL_CONFIG)\n+$(STAMP_KERNEL_CONFIG):\n \t@set -e ; test -f local-symbols || (\t\t\t\t\t\t\\\n \techo \"/--------------\"\t\t\t\t\t\t\t\t;\\\n \techo \"| You shouldn't run make in the backports tree, but only in\"\t\t;\\\n@@ -60,58 +62,62 @@ mrproper:\n \techo \"| (that isn't currently running.)\"\t\t\t\t\t;\\\n \techo \"\\\\--\"\t\t\t\t\t\t\t\t\t;\\\n \tfalse)\n-\t@set -e ; if [ \"$$(cat .kernel_config_md5 2>/dev/null)\" != \"$(CONFIG_MD5)\" ]\t;\\\n-\tthen \t\t\t\t\t\t\t\t\t\t\\\n-\t\techo -n \"Generating local configuration database from kernel ...\"\t;\\\n-\t\tgrep -v -f local-symbols $(KERNEL_CONFIG) | grep = | (\t\t\t\\\n-\t\t\twhile read l ; do\t\t\t\t\t\t\\\n-\t\t\t\tif [ \"$${l:0:7}\" != \"CONFIG_\" ] ; then\t\t\t\\\n-\t\t\t\t\tcontinue\t\t\t\t\t;\\\n-\t\t\t\tfi\t\t\t\t\t\t\t;\\\n-\t\t\t\tl=$${l:7}\t\t\t\t\t\t;\\\n-\t\t\t\tn=$${l%%=*}\t\t\t\t\t\t;\\\n-\t\t\t\tv=$${l#*=}\t\t\t\t\t\t;\\\n-\t\t\t\tif [ \"$$v\" = \"m\" ] ; then\t\t\t\t\\\n-\t\t\t\t\techo config $$n\t\t\t\t\t;\\\n-\t\t\t\t\techo '    tristate' \t\t\t\t;\\\n-\t\t\t\telif [ \"$$v\" = \"y\" ] ; then\t\t\t\t\\\n-\t\t\t\t\techo config $$n\t\t\t\t\t;\\\n-\t\t\t\t\techo '    bool'\t\t\t\t\t;\\\n-\t\t\t\telse\t\t\t\t\t\t\t\\\n-\t\t\t\t\tcontinue\t\t\t\t\t;\\\n-\t\t\t\tfi\t\t\t\t\t\t\t;\\\n-\t\t\t\techo \"    default $$v\"\t\t\t\t\t;\\\n-\t\t\t\techo \"\"\t\t\t\t\t\t\t;\\\n-\t\t\tdone\t\t\t\t\t\t\t\t\\\n-\t\t) > Kconfig.kernel\t\t\t\t\t\t\t;\\\n-\t\tkver=$$($(MAKE) --no-print-directory -C $(KLIB_BUILD) M=$(BACKPORT_DIR)\t\\\n-\t\t\tkernelversion |\tsed 's/^\\(\\([3-5]\\|2\\.6\\)\\.[0-9]\\+\\).*/\\1/;t;d');\\\n-\t\ttest \"$$kver\" != \"\" || echo \"Kernel version parse failed!\"\t\t;\\\n-\t\ttest \"$$kver\" != \"\"\t\t\t\t\t\t\t;\\\n-\t\tkvers=\"$$(seq 14 39 | sed 's/^/2.6./')\"\t\t\t\t\t;\\\n-\t\tkvers=\"$$kvers $$(seq 0 19 | sed 's/^/3./')\"\t\t\t\t;\\\n-\t\tkvers=\"$$kvers $$(seq 0 20 | sed 's/^/4./')\"\t\t\t\t;\\\n-\t\tkvers=\"$$kvers $$(seq 0 99 | sed 's/^/5./')\"\t\t\t\t;\\\n-\t\tprint=0\t\t\t\t\t\t\t\t\t;\\\n-\t\tfor v in $$kvers ; do\t\t\t\t\t\t\t\\\n-\t\t\tif [ \"$$print\" = \"1\" ] ; then\t\t\t\t\t\\\n-\t\t\t\techo config KERNEL_$$(echo $$v | tr . _)\t;\\\n-\t\t\t\techo \"    def_bool y\"\t\t\t\t\t;\\\n-\t\t\tfi\t\t\t\t\t\t\t\t;\\\n-\t\t\tif [ \"$$v\" = \"$$kver\" ] ; then print=1 ; fi\t\t\t;\\\n-\t\tdone > Kconfig.versions\t\t\t\t\t\t\t;\\\n-\t\t# RHEL as well, sadly we need to grep for it\t\t\t\t;\\\n-\t\tRHEL_MAJOR=$$(grep '^RHEL_MAJOR' $(KERNEL_MAKEFILE) | \t\t\t\\\n-\t\t\t\t\tsed 's/.*=\\s*\\([0-9]*\\)/\\1/;t;d')\t\t;\\\n-\t\tRHEL_MINOR=$$(grep '^RHEL_MINOR' $(KERNEL_MAKEFILE) | \t\t\t\\\n-\t\t\t\t\tsed 's/.*=\\s*\\([0-9]*\\)/\\1/;t;d')\t\t;\\\n-\t\tfor v in $$(seq 0 $$RHEL_MINOR) ; do \t\t\t\t\t\\\n-\t\t\techo config BACKPORT_RHEL_KERNEL_$${RHEL_MAJOR}_$$v\t\t;\\\n-\t\t\techo \"    def_bool y\"\t\t\t\t\t\t;\\\n-\t\tdone >> Kconfig.versions\t\t\t\t\t\t;\\\n-\t\techo \" done.\"\t\t\t\t\t\t\t\t;\\\n-\tfi\t\t\t\t\t\t\t\t\t\t;\\\n-\techo \"$(CONFIG_MD5)\" > .kernel_config_md5\n+\t@rm -f .kernel_config_md5_*\n+\t@touch $@\n+\n+Kconfig.kernel: $(STAMP_KERNEL_CONFIG) local-symbols\n+\t@printf \"Generating local configuration database from kernel ...\"\n+\t@grep -v -f local-symbols $(KERNEL_CONFIG) | grep = | (\t\t\t\\\n+\t\twhile read l ; do\t\t\t\t\t\t\\\n+\t\t\tif [ \"$${l:0:7}\" != \"CONFIG_\" ] ; then\t\t\t\\\n+\t\t\t\tcontinue\t\t\t\t\t;\\\n+\t\t\tfi\t\t\t\t\t\t\t;\\\n+\t\t\tl=$${l:7}\t\t\t\t\t\t;\\\n+\t\t\tn=$${l%%=*}\t\t\t\t\t\t;\\\n+\t\t\tv=$${l#*=}\t\t\t\t\t\t;\\\n+\t\t\tif [ \"$$v\" = \"m\" ] ; then\t\t\t\t\\\n+\t\t\t\techo config $$n\t\t\t\t\t;\\\n+\t\t\t\techo '    tristate' \t\t\t\t;\\\n+\t\t\telif [ \"$$v\" = \"y\" ] ; then\t\t\t\t\\\n+\t\t\t\techo config $$n\t\t\t\t\t;\\\n+\t\t\t\techo '    bool'\t\t\t\t\t;\\\n+\t\t\telse\t\t\t\t\t\t\t\\\n+\t\t\t\tcontinue\t\t\t\t\t;\\\n+\t\t\tfi\t\t\t\t\t\t\t;\\\n+\t\t\techo \"    default $$v\"\t\t\t\t\t;\\\n+\t\t\techo \"\"\t\t\t\t\t\t\t;\\\n+\t\tdone\t\t\t\t\t\t\t\t\\\n+\t) > $@\n+\t@echo \" done.\"\n+\n+Kconfig.versions: Kconfig.kernel\n+\t@kver=$$($(MAKE) --no-print-directory -C $(KLIB_BUILD) M=$(BACKPORT_DIR) \\\n+\t\tkernelversion |\tsed 's/^\\(\\([3-5]\\|2\\.6\\)\\.[0-9]\\+\\).*/\\1/;t;d');\\\n+\ttest \"$$kver\" != \"\" || echo \"Kernel version parse failed!\"\t\t;\\\n+\ttest \"$$kver\" != \"\"\t\t\t\t\t\t\t;\\\n+\tkvers=\"$$(seq 14 39 | sed 's/^/2.6./')\"\t\t\t\t\t;\\\n+\tkvers=\"$$kvers $$(seq 0 19 | sed 's/^/3./')\"\t\t\t\t;\\\n+\tkvers=\"$$kvers $$(seq 0 20 | sed 's/^/4./')\"\t\t\t\t;\\\n+\tkvers=\"$$kvers $$(seq 0 99 | sed 's/^/5./')\"\t\t\t\t;\\\n+\tprint=0\t\t\t\t\t\t\t\t\t;\\\n+\tfor v in $$kvers ; do\t\t\t\t\t\t\t\\\n+\t\tif [ \"$$print\" = \"1\" ] ; then\t\t\t\t\t\\\n+\t\t\techo config KERNEL_$$(echo $$v | tr . _)\t;\\\n+\t\t\techo \"    def_bool y\"\t\t\t\t\t;\\\n+\t\tfi\t\t\t\t\t\t\t\t;\\\n+\t\tif [ \"$$v\" = \"$$kver\" ] ; then print=1 ; fi\t\t\t;\\\n+\tdone > $@\n+\t@RHEL_MAJOR=$$(grep '^RHEL_MAJOR' $(KERNEL_MAKEFILE) | \t\t\t\\\n+\t\t\t\tsed 's/.*=\\s*\\([0-9]*\\)/\\1/;t;d')\t\t;\\\n+\tRHEL_MINOR=$$(grep '^RHEL_MINOR' $(KERNEL_MAKEFILE) | \t\t\t\\\n+\t\t\t\tsed 's/.*=\\s*\\([0-9]*\\)/\\1/;t;d')\t\t;\\\n+\tfor v in $$(seq 0 $$RHEL_MINOR) ; do \t\t\t\t\t\\\n+\t\techo config BACKPORT_RHEL_KERNEL_$${RHEL_MAJOR}_$$v\t\t;\\\n+\t\techo \"    def_bool y\"\t\t\t\t\t\t;\\\n+\tdone >> $@\n+\n+.DEFAULT:\n+\t@$(MAKE) Kconfig.versions\n \t@$(MAKE) -f Makefile.real \"$@\"\n \n .PHONY: defconfig-help\n--- a/Makefile.real\n+++ b/Makefile.real\n@@ -59,7 +59,7 @@ defconfig-%::\n \n backport-include/backport/autoconf.h: .config Kconfig.versions Kconfig.kernel\n \t@$(MAKE) oldconfig\n-\t@echo -n \"Building backport-include/backport/autoconf.h ...\"\n+\t@printf \"Building backport-include/backport/autoconf.h ...\"\n \t@grep -f local-symbols .config | (\t\t\t\t\\\n \t\techo \"#ifndef COMPAT_AUTOCONF_INCLUDED\"\t\t\t;\\\n \t\techo \"#define COMPAT_AUTOCONF_INCLUDED\"\t\t\t;\\\n@@ -80,7 +80,12 @@ backport-include/backport/autoconf.h: .c\n \t\t\tesac\t\t\t\t\t\t;\\\n \t\tdone\t\t\t\t\t\t\t;\\\n \t\techo \"#endif /* COMPAT_AUTOCONF_INCLUDED */\"\t\t;\\\n-\t) > backport-include/backport/autoconf.h\n+\t) > $@.new\n+\t@if cmp -s $@ $@.new; then \\\n+\t\trm -f $@.new; \\\n+\telse \\\n+\t\tmv $@.new $@; \\\n+\tfi\n \t@echo \" done.\"\n \n .PHONY: modules\n"
  },
  {
    "path": "package/kernel/mac80211/patches/build/002-change_allconfig.patch",
    "content": "--- a/kconf/conf.c\n+++ b/kconf/conf.c\n@@ -598,40 +598,12 @@ int main(int ac, char **av)\n \tcase oldconfig:\n \tcase listnewconfig:\n \tcase olddefconfig:\n-\t\tconf_read(NULL);\n-\t\tbreak;\n \tcase allnoconfig:\n \tcase allyesconfig:\n \tcase allmodconfig:\n \tcase alldefconfig:\n \tcase randconfig:\n-\t\tname = getenv(\"KCONFIG_ALLCONFIG\");\n-\t\tif (!name)\n-\t\t\tbreak;\n-\t\tif ((strcmp(name, \"\") != 0) && (strcmp(name, \"1\") != 0)) {\n-\t\t\tif (conf_read_simple(name, S_DEF_USER)) {\n-\t\t\t\tfprintf(stderr,\n-\t\t\t\t\t_(\"*** Can't read seed configuration \\\"%s\\\"!\\n\"),\n-\t\t\t\t\tname);\n-\t\t\t\texit(1);\n-\t\t\t}\n-\t\t\tbreak;\n-\t\t}\n-\t\tswitch (input_mode) {\n-\t\tcase allnoconfig:\tname = \"allno.config\"; break;\n-\t\tcase allyesconfig:\tname = \"allyes.config\"; break;\n-\t\tcase allmodconfig:\tname = \"allmod.config\"; break;\n-\t\tcase alldefconfig:\tname = \"alldef.config\"; break;\n-\t\tcase randconfig:\tname = \"allrandom.config\"; break;\n-\t\tdefault: break;\n-\t\t}\n-\t\tif (conf_read_simple(name, S_DEF_USER) &&\n-\t\t    conf_read_simple(\"all.config\", S_DEF_USER)) {\n-\t\t\tfprintf(stderr,\n-\t\t\t\t_(\"*** KCONFIG_ALLCONFIG set, but no \\\"%s\\\" or \\\"all.config\\\" file found\\n\"),\n-\t\t\t\tname);\n-\t\t\texit(1);\n-\t\t}\n+\t\tconf_read(NULL);\n \t\tbreak;\n \tdefault:\n \t\tbreak;\n--- a/kconf/confdata.c\n+++ b/kconf/confdata.c\n@@ -1170,6 +1170,8 @@ bool conf_set_all_new_symbols(enum conf_\n \t}\n \tbool has_changed = false;\n \n+\tsym_clear_all_valid();\n+\n \tfor_all_symbols(i, sym) {\n \t\tif (sym_has_value(sym) || (sym->flags & SYMBOL_VALID))\n \t\t\tcontinue;\n@@ -1213,8 +1215,6 @@ bool conf_set_all_new_symbols(enum conf_\n \n \t}\n \n-\tsym_clear_all_valid();\n-\n \t/*\n \t * We have different type of choice blocks.\n \t * If curr.tri equals to mod then we can select several\n"
  },
  {
    "path": "package/kernel/mac80211/patches/build/003-remove_bogus_modparams.patch",
    "content": "--- a/compat/main.c\n+++ b/compat/main.c\n@@ -19,31 +19,6 @@ MODULE_LICENSE(\"GPL\");\n #error \"You need a CPTCFG_VERSION\"\n #endif\n \n-static char *backported_kernel_name = CPTCFG_KERNEL_NAME;\n-\n-module_param(backported_kernel_name, charp, 0400);\n-MODULE_PARM_DESC(backported_kernel_name,\n-\t\t \"The kernel tree name that was used for this backport (\" CPTCFG_KERNEL_NAME \")\");\n-\n-#ifdef BACKPORTS_GIT_TRACKED\n-static char *backports_tracker_id = BACKPORTS_GIT_TRACKED;\n-module_param(backports_tracker_id, charp, 0400);\n-MODULE_PARM_DESC(backports_tracker_id,\n-\t\t \"The version of the tree containing this backport (\" BACKPORTS_GIT_TRACKED \")\");\n-#else\n-static char *backported_kernel_version = CPTCFG_KERNEL_VERSION;\n-static char *backports_version = CPTCFG_VERSION;\n-\n-module_param(backported_kernel_version, charp, 0400);\n-MODULE_PARM_DESC(backported_kernel_version,\n-\t\t \"The kernel version that was used for this backport (\" CPTCFG_KERNEL_VERSION \")\");\n-\n-module_param(backports_version, charp, 0400);\n-MODULE_PARM_DESC(backports_version,\n-\t\t \"The git version of the backports tree used to generate this backport (\" CPTCFG_VERSION \")\");\n-\n-#endif\n-\n void backport_dependency_symbol(void)\n {\n }\n"
  },
  {
    "path": "package/kernel/mac80211/patches/build/012-kernel_build_check.patch",
    "content": "--- a/Makefile\n+++ b/Makefile\n@@ -2,7 +2,7 @@\n # Makefile for the output source package\n #\n \n-ifeq ($(KERNELRELEASE),)\n+ifeq ($(KERNELVERSION),)\n \n MAKEFLAGS += --no-print-directory\n SHELL := /usr/bin/env bash\n"
  },
  {
    "path": "package/kernel/mac80211/patches/build/015-ipw200-mtu.patch",
    "content": "--- a/drivers/net/wireless/intel/ipw2x00/ipw2200.c\n+++ b/drivers/net/wireless/intel/ipw2x00/ipw2200.c\n@@ -11470,6 +11470,15 @@ static const struct attribute_group ipw_\n \t.attrs = ipw_sysfs_entries,\n };\n \n+#if LINUX_VERSION_IS_LESS(4,10,0)\n+static int __change_mtu(struct net_device *ndev, int new_mtu){\n+\tif (new_mtu < 68 || new_mtu > LIBIPW_DATA_LEN)\n+\t\treturn -EINVAL;\n+\tndev->mtu = new_mtu;\n+\treturn 0;\n+}\n+#endif\n+\n #ifdef CPTCFG_IPW2200_PROMISCUOUS\n static int ipw_prom_open(struct net_device *dev)\n {\n@@ -11518,15 +11527,6 @@ static netdev_tx_t ipw_prom_hard_start_x\n \treturn NETDEV_TX_OK;\n }\n \n-#if LINUX_VERSION_IS_LESS(4,10,0)\n-static int __change_mtu(struct net_device *ndev, int new_mtu){\n-\tif (new_mtu < 68 || new_mtu > LIBIPW_DATA_LEN)\n-\t\treturn -EINVAL;\n-\tndev->mtu = new_mtu;\n-\treturn 0;\n-}\n-#endif\n-\n static const struct net_device_ops ipw_prom_netdev_ops = {\n #if LINUX_VERSION_IS_LESS(4,10,0)\n \t.ndo_change_mtu = __change_mtu,\n"
  },
  {
    "path": "package/kernel/mac80211/patches/build/050-lib80211_option.patch",
    "content": "--- a/net/wireless/Kconfig\n+++ b/net/wireless/Kconfig\n@@ -188,7 +188,7 @@ config CFG80211_WEXT_EXPORT\n endif # CFG80211\n \n config LIB80211\n-\ttristate\n+\ttristate \"lib80211\"\n \tdepends on m\n \tdefault n\n \thelp\n@@ -198,19 +198,19 @@ config LIB80211\n \t  Drivers should select this themselves if needed.\n \n config LIB80211_CRYPT_WEP\n-\ttristate\n+\ttristate \"lib80211 WEP support\"\n \tdepends on m\n \tselect BPAUTO_CRYPTO_LIB_ARC4\n \n config LIB80211_CRYPT_CCMP\n-\ttristate\n+\ttristate \"lib80211 CCMP support\"\n \tdepends on m\n \tdepends on CRYPTO\n \tdepends on CRYPTO_AES\n \tdepends on CRYPTO_CCM\n \n config LIB80211_CRYPT_TKIP\n-\ttristate\n+\ttristate \"lib80211 TKIP support\"\n \tdepends on m\n \tselect BPAUTO_CRYPTO_LIB_ARC4\n \n"
  },
  {
    "path": "package/kernel/mac80211/patches/build/060-no_local_ssb_bcma.patch",
    "content": "--- a/local-symbols\n+++ b/local-symbols\n@@ -428,43 +428,6 @@ USB_VL600=\n USB_NET_CH9200=\n USB_NET_AQC111=\n USB_RTL8153_ECM=\n-SSB_POSSIBLE=\n-SSB=\n-SSB_SPROM=\n-SSB_BLOCKIO=\n-SSB_PCIHOST_POSSIBLE=\n-SSB_PCIHOST=\n-SSB_B43_PCI_BRIDGE=\n-SSB_PCMCIAHOST_POSSIBLE=\n-SSB_PCMCIAHOST=\n-SSB_SDIOHOST_POSSIBLE=\n-SSB_SDIOHOST=\n-SSB_HOST_SOC=\n-SSB_SERIAL=\n-SSB_DRIVER_PCICORE_POSSIBLE=\n-SSB_DRIVER_PCICORE=\n-SSB_PCICORE_HOSTMODE=\n-SSB_DRIVER_MIPS=\n-SSB_SFLASH=\n-SSB_EMBEDDED=\n-SSB_DRIVER_EXTIF=\n-SSB_DRIVER_GIGE=\n-SSB_DRIVER_GPIO=\n-BCMA_POSSIBLE=\n-BCMA=\n-BCMA_BLOCKIO=\n-BCMA_HOST_PCI_POSSIBLE=\n-BCMA_HOST_PCI=\n-BCMA_HOST_SOC=\n-BCMA_DRIVER_PCI=\n-BCMA_DRIVER_PCI_HOSTMODE=\n-BCMA_DRIVER_MIPS=\n-BCMA_PFLASH=\n-BCMA_SFLASH=\n-BCMA_NFLASH=\n-BCMA_DRIVER_GMAC_CMN=\n-BCMA_DRIVER_GPIO=\n-BCMA_DEBUG=\n USB_ACM=\n USB_PRINTER=\n USB_WDM=\n--- a/drivers/net/wireless/broadcom/b43/Kconfig\n+++ b/drivers/net/wireless/broadcom/b43/Kconfig\n@@ -63,21 +63,21 @@ endchoice\n config B43_PCI_AUTOSELECT\n \tbool\n \tdepends on B43 && SSB_PCIHOST_POSSIBLE\n-\tselect SSB_PCIHOST\n-\tselect SSB_B43_PCI_BRIDGE\n+\tdepends on SSB_PCIHOST\n+\tdepends on SSB_B43_PCI_BRIDGE\n \tdefault y\n \n # Auto-select SSB PCICORE driver, if possible\n config B43_PCICORE_AUTOSELECT\n \tbool\n \tdepends on B43 && SSB_DRIVER_PCICORE_POSSIBLE\n-\tselect SSB_DRIVER_PCICORE\n+\tdepends on SSB_DRIVER_PCICORE\n \tdefault y\n \n config B43_SDIO\n \tbool \"Broadcom 43xx SDIO device support\"\n \tdepends on B43 && B43_SSB && SSB_SDIOHOST_POSSIBLE\n-\tselect SSB_SDIOHOST\n+\tdepends on SSB_SDIOHOST\n \thelp\n \t  Broadcom 43xx device support for Soft-MAC SDIO devices.\n \n@@ -96,13 +96,13 @@ config B43_SDIO\n config B43_BCMA_PIO\n \tbool\n \tdepends on B43 && B43_BCMA\n-\tselect BCMA_BLOCKIO\n+\tdepends on BCMA_BLOCKIO\n \tdefault y\n \n config B43_PIO\n \tbool\n \tdepends on B43 && B43_SSB\n-\tselect SSB_BLOCKIO\n+\tdepends on SSB_BLOCKIO\n \tdefault y\n \n config B43_PHY_G\n--- a/drivers/net/wireless/broadcom/b43/main.c\n+++ b/drivers/net/wireless/broadcom/b43/main.c\n@@ -2853,7 +2853,7 @@ static struct ssb_device *b43_ssb_gpio_d\n {\n \tstruct ssb_bus *bus = dev->dev->sdev->bus;\n \n-#ifdef CPTCFG_SSB_DRIVER_PCICORE\n+#ifdef CONFIG_SSB_DRIVER_PCICORE\n \treturn (bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev);\n #else\n \treturn bus->chipco.dev;\n@@ -4870,7 +4870,7 @@ static int b43_wireless_core_init(struct\n \t}\n \tif (sprom->boardflags_lo & B43_BFL_XTAL_NOSLOW)\n \t\thf |= B43_HF_DSCRQ; /* Disable slowclock requests from ucode. */\n-#if defined(CPTCFG_B43_SSB) && defined(CPTCFG_SSB_DRIVER_PCICORE)\n+#if defined(CPTCFG_B43_SSB) && defined(CONFIG_SSB_DRIVER_PCICORE)\n \tif (dev->dev->bus_type == B43_BUS_SSB &&\n \t    dev->dev->sdev->bus->bustype == SSB_BUSTYPE_PCI &&\n \t    dev->dev->sdev->bus->pcicore.dev->id.revision <= 10)\n--- a/drivers/net/wireless/broadcom/b43legacy/Kconfig\n+++ b/drivers/net/wireless/broadcom/b43legacy/Kconfig\n@@ -3,7 +3,7 @@ config B43LEGACY\n \ttristate \"Broadcom 43xx-legacy wireless support (mac80211 stack)\"\n \tdepends on m\n \tdepends on SSB_POSSIBLE && MAC80211 && HAS_DMA\n-\tselect SSB\n+\tdepends on SSB\n \tdepends on FW_LOADER\n \thelp\n \t  b43legacy is a driver for 802.11b devices from Broadcom (BCM4301 and\n@@ -25,15 +25,15 @@ config B43LEGACY\n config B43LEGACY_PCI_AUTOSELECT\n \tbool\n \tdepends on B43LEGACY && SSB_PCIHOST_POSSIBLE\n-\tselect SSB_PCIHOST\n-\tselect SSB_B43_PCI_BRIDGE\n+\tdepends on SSB_PCIHOST\n+\tdepends on SSB_B43_PCI_BRIDGE\n \tdefault y\n \n # Auto-select SSB PCICORE driver, if possible\n config B43LEGACY_PCICORE_AUTOSELECT\n \tbool\n \tdepends on B43LEGACY && SSB_DRIVER_PCICORE_POSSIBLE\n-\tselect SSB_DRIVER_PCICORE\n+\tdepends on SSB_DRIVER_PCICORE\n \tdefault y\n \n # LED support\n--- a/drivers/net/wireless/broadcom/b43legacy/main.c\n+++ b/drivers/net/wireless/broadcom/b43legacy/main.c\n@@ -1907,7 +1907,7 @@ static int b43legacy_gpio_init(struct b4\n \tif (dev->dev->id.revision >= 2)\n \t\tmask  |= 0x0010; /* FIXME: This is redundant. */\n \n-#ifdef CPTCFG_SSB_DRIVER_PCICORE\n+#ifdef CONFIG_SSB_DRIVER_PCICORE\n \tpcidev = bus->pcicore.dev;\n #endif\n \tgpiodev = bus->chipco.dev ? : pcidev;\n@@ -1926,7 +1926,7 @@ static void b43legacy_gpio_cleanup(struc\n \tstruct ssb_bus *bus = dev->dev->bus;\n \tstruct ssb_device *gpiodev, *pcidev = NULL;\n \n-#ifdef CPTCFG_SSB_DRIVER_PCICORE\n+#ifdef CONFIG_SSB_DRIVER_PCICORE\n \tpcidev = bus->pcicore.dev;\n #endif\n \tgpiodev = bus->chipco.dev ? : pcidev;\n--- a/drivers/net/wireless/broadcom/brcm80211/brcmsmac/led.h\n+++ b/drivers/net/wireless/broadcom/brcm80211/brcmsmac/led.h\n@@ -24,7 +24,7 @@ struct brcms_led {\n \tstruct gpio_desc *gpiod;\n };\n \n-#ifdef CPTCFG_BCMA_DRIVER_GPIO\n+#ifdef CONFIG_BCMA_DRIVER_GPIO\n void brcms_led_unregister(struct brcms_info *wl);\n int brcms_led_register(struct brcms_info *wl);\n #else\n--- a/drivers/net/wireless/broadcom/brcm80211/brcmsmac/Makefile\n+++ b/drivers/net/wireless/broadcom/brcm80211/brcmsmac/Makefile\n@@ -42,6 +42,6 @@ brcmsmac-y := \\\n \tbrcms_trace_events.o \\\n \tdebug.o\n \n-brcmsmac-$(CPTCFG_BCMA_DRIVER_GPIO) += led.o\n+brcmsmac-$(CONFIG_BCMA_DRIVER_GPIO) += led.o\n \n obj-$(CPTCFG_BRCMSMAC)\t+= brcmsmac.o\n--- a/drivers/net/wireless/broadcom/brcm80211/Kconfig\n+++ b/drivers/net/wireless/broadcom/brcm80211/Kconfig\n@@ -8,7 +8,7 @@ config BRCMSMAC\n \tdepends on m\n \tdepends on MAC80211\n \tdepends on BCMA_POSSIBLE\n-\tselect BCMA\n+\tdepends on BCMA\n \tselect NEW_LEDS if BCMA_DRIVER_GPIO\n \tselect LEDS_CLASS if BCMA_DRIVER_GPIO\n \tselect BRCMUTIL\n--- a/Kconfig.local\n+++ b/Kconfig.local\n@@ -1288,117 +1288,6 @@ config BACKPORTED_USB_NET_AQC111\n config BACKPORTED_USB_RTL8153_ECM\n \ttristate\n \tdefault USB_RTL8153_ECM\n-config BACKPORTED_SSB_POSSIBLE\n-\ttristate\n-\tdefault SSB_POSSIBLE\n-config BACKPORTED_SSB\n-\ttristate\n-\tdefault SSB\n-config BACKPORTED_SSB_SPROM\n-\ttristate\n-\tdefault SSB_SPROM\n-config BACKPORTED_SSB_BLOCKIO\n-\ttristate\n-\tdefault SSB_BLOCKIO\n-config BACKPORTED_SSB_PCIHOST_POSSIBLE\n-\ttristate\n-\tdefault SSB_PCIHOST_POSSIBLE\n-config BACKPORTED_SSB_PCIHOST\n-\ttristate\n-\tdefault SSB_PCIHOST\n-config BACKPORTED_SSB_B43_PCI_BRIDGE\n-\ttristate\n-\tdefault SSB_B43_PCI_BRIDGE\n-config BACKPORTED_SSB_PCMCIAHOST_POSSIBLE\n-\ttristate\n-\tdefault SSB_PCMCIAHOST_POSSIBLE\n-config BACKPORTED_SSB_PCMCIAHOST\n-\ttristate\n-\tdefault SSB_PCMCIAHOST\n-config BACKPORTED_SSB_SDIOHOST_POSSIBLE\n-\ttristate\n-\tdefault SSB_SDIOHOST_POSSIBLE\n-config BACKPORTED_SSB_SDIOHOST\n-\ttristate\n-\tdefault SSB_SDIOHOST\n-config BACKPORTED_SSB_HOST_SOC\n-\ttristate\n-\tdefault SSB_HOST_SOC\n-config BACKPORTED_SSB_SERIAL\n-\ttristate\n-\tdefault SSB_SERIAL\n-config BACKPORTED_SSB_DRIVER_PCICORE_POSSIBLE\n-\ttristate\n-\tdefault SSB_DRIVER_PCICORE_POSSIBLE\n-config BACKPORTED_SSB_DRIVER_PCICORE\n-\ttristate\n-\tdefault SSB_DRIVER_PCICORE\n-config BACKPORTED_SSB_PCICORE_HOSTMODE\n-\ttristate\n-\tdefault SSB_PCICORE_HOSTMODE\n-config BACKPORTED_SSB_DRIVER_MIPS\n-\ttristate\n-\tdefault SSB_DRIVER_MIPS\n-config BACKPORTED_SSB_SFLASH\n-\ttristate\n-\tdefault SSB_SFLASH\n-config BACKPORTED_SSB_EMBEDDED\n-\ttristate\n-\tdefault SSB_EMBEDDED\n-config BACKPORTED_SSB_DRIVER_EXTIF\n-\ttristate\n-\tdefault SSB_DRIVER_EXTIF\n-config BACKPORTED_SSB_DRIVER_GIGE\n-\ttristate\n-\tdefault SSB_DRIVER_GIGE\n-config BACKPORTED_SSB_DRIVER_GPIO\n-\ttristate\n-\tdefault SSB_DRIVER_GPIO\n-config BACKPORTED_BCMA_POSSIBLE\n-\ttristate\n-\tdefault BCMA_POSSIBLE\n-config BACKPORTED_BCMA\n-\ttristate\n-\tdefault BCMA\n-config BACKPORTED_BCMA_BLOCKIO\n-\ttristate\n-\tdefault BCMA_BLOCKIO\n-config BACKPORTED_BCMA_HOST_PCI_POSSIBLE\n-\ttristate\n-\tdefault BCMA_HOST_PCI_POSSIBLE\n-config BACKPORTED_BCMA_HOST_PCI\n-\ttristate\n-\tdefault BCMA_HOST_PCI\n-config BACKPORTED_BCMA_HOST_SOC\n-\ttristate\n-\tdefault BCMA_HOST_SOC\n-config BACKPORTED_BCMA_DRIVER_PCI\n-\ttristate\n-\tdefault BCMA_DRIVER_PCI\n-config BACKPORTED_BCMA_DRIVER_PCI_HOSTMODE\n-\ttristate\n-\tdefault BCMA_DRIVER_PCI_HOSTMODE\n-config BACKPORTED_BCMA_DRIVER_MIPS\n-\ttristate\n-\tdefault BCMA_DRIVER_MIPS\n-config BACKPORTED_BCMA_PFLASH\n-\ttristate\n-\tdefault BCMA_PFLASH\n-config BACKPORTED_BCMA_SFLASH\n-\ttristate\n-\tdefault BCMA_SFLASH\n-config BACKPORTED_BCMA_NFLASH\n-\ttristate\n-\tdefault BCMA_NFLASH\n-config BACKPORTED_BCMA_DRIVER_GMAC_CMN\n-\ttristate\n-\tdefault BCMA_DRIVER_GMAC_CMN\n-config BACKPORTED_BCMA_DRIVER_GPIO\n-\ttristate\n-\tdefault BCMA_DRIVER_GPIO\n-config BACKPORTED_BCMA_DEBUG\n-\ttristate\n-\tdefault BCMA_DEBUG\n config BACKPORTED_USB_ACM\n \ttristate\n \tdefault USB_ACM\n--- a/Kconfig.sources\n+++ b/Kconfig.sources\n@@ -9,9 +9,6 @@ source \"$BACKPORT_DIR/drivers/bus/mhi/Kc\n source \"$BACKPORT_DIR/drivers/net/wireless/Kconfig\"\n source \"$BACKPORT_DIR/drivers/net/usb/Kconfig\"\n \n-source \"$BACKPORT_DIR/drivers/ssb/Kconfig\"\n-source \"$BACKPORT_DIR/drivers/bcma/Kconfig\"\n-\n source \"$BACKPORT_DIR/drivers/usb/class/Kconfig\"\n \n source \"$BACKPORT_DIR/drivers/staging/Kconfig\"\n--- a/Makefile.kernel\n+++ b/Makefile.kernel\n@@ -42,8 +42,6 @@ obj-$(CPTCFG_MAC80211) += net/mac80211/\n obj-$(CPTCFG_QRTR) += net/qrtr/\n obj-$(CPTCFG_MHI_BUS) += drivers/bus/mhi/\n obj-$(CPTCFG_WLAN) += drivers/net/wireless/\n-obj-$(CPTCFG_SSB) += drivers/ssb/\n-obj-$(CPTCFG_BCMA) += drivers/bcma/\n obj-$(CPTCFG_USB_NET_RNDIS_WLAN) += drivers/net/usb/\n \n obj-$(CPTCFG_USB_WDM) += drivers/usb/class/\n"
  },
  {
    "path": "package/kernel/mac80211/patches/mwl/700-mwl8k-missing-pci-id-for-WNR854T.patch",
    "content": "--- a/drivers/net/wireless/marvell/mwl8k.c\n+++ b/drivers/net/wireless/marvell/mwl8k.c\n@@ -5699,6 +5699,7 @@ MODULE_FIRMWARE(\"mwl8k/fmimage_8366.fw\")\n MODULE_FIRMWARE(MWL8K_8366_AP_FW(MWL8K_8366_AP_FW_API));\n \n static const struct pci_device_id mwl8k_pci_id_table[] = {\n+\t{ PCI_VDEVICE(MARVELL, 0x2a02), .driver_data = MWL8363, },\n \t{ PCI_VDEVICE(MARVELL, 0x2a0a), .driver_data = MWL8363, },\n \t{ PCI_VDEVICE(MARVELL, 0x2a0c), .driver_data = MWL8363, },\n \t{ PCI_VDEVICE(MARVELL, 0x2a24), .driver_data = MWL8363, },\n"
  },
  {
    "path": "package/kernel/mac80211/patches/mwl/801-libertas-configure-sysfs-links.patch",
    "content": "--- a/drivers/net/wireless/marvell/libertas/cfg.c\n+++ b/drivers/net/wireless/marvell/libertas/cfg.c\n@@ -2053,6 +2053,8 @@ struct wireless_dev *lbs_cfg_alloc(struc\n \t\tgoto err_wiphy_new;\n \t}\n \n+\tset_wiphy_dev(wdev->wiphy, dev);\n+\n \treturn wdev;\n \n  err_wiphy_new:\n--- a/drivers/net/wireless/marvell/libertas/main.c\n+++ b/drivers/net/wireless/marvell/libertas/main.c\n@@ -935,6 +935,7 @@ struct lbs_private *lbs_add_card(void *c\n \t\tgoto err_adapter;\n \t}\n \n+\tdev_net_set(dev, wiphy_net(wdev->wiphy));\n \tdev->ieee80211_ptr = wdev;\n \tdev->ml_priv = priv;\n \tSET_NETDEV_DEV(dev, dmdev);\n"
  },
  {
    "path": "package/kernel/mac80211/patches/mwl/802-libertas-set-wireless-macaddr.patch",
    "content": "--- a/drivers/net/wireless/marvell/libertas/cfg.c\n+++ b/drivers/net/wireless/marvell/libertas/cfg.c\n@@ -2129,6 +2129,8 @@ int lbs_cfg_register(struct lbs_private\n \twdev->wiphy->n_cipher_suites = ARRAY_SIZE(cipher_suites);\n \twdev->wiphy->reg_notifier = lbs_reg_notifier;\n \n+\tmemcpy(wdev->wiphy->perm_addr, priv->current_addr, ETH_ALEN);\n+\n \tret = wiphy_register(wdev->wiphy);\n \tif (ret < 0)\n \t\tpr_err(\"cannot register wiphy device\\n\");\n"
  },
  {
    "path": "package/kernel/mac80211/patches/mwl/940-mwl8k_init_devices_synchronously.patch",
    "content": "--- a/drivers/net/wireless/marvell/mwl8k.c\n+++ b/drivers/net/wireless/marvell/mwl8k.c\n@@ -6285,6 +6285,8 @@ static int mwl8k_probe(struct pci_dev *p\n \n \tpriv->running_bsses = 0;\n \n+\twait_for_completion(&priv->firmware_loading_complete);\n+\n \treturn rc;\n \n err_stop_firmware:\n@@ -6318,8 +6320,6 @@ static void mwl8k_remove(struct pci_dev\n \t\treturn;\n \tpriv = hw->priv;\n \n-\twait_for_completion(&priv->firmware_loading_complete);\n-\n \tif (priv->fw_state == FW_STATE_ERROR) {\n \t\tmwl8k_hw_reset(priv);\n \t\tgoto unmap;\n"
  },
  {
    "path": "package/kernel/mac80211/patches/rt2x00/002-rt2x00-define-RF5592-in-init_eeprom-routine.patch",
    "content": "From patchwork Thu Dec 27 14:05:26 2018\nContent-Type: text/plain; charset=\"utf-8\"\nMIME-Version: 1.0\nContent-Transfer-Encoding: 8bit\nX-Patchwork-Submitter: Tom Psyborg <pozega.tomislav@gmail.com>\nX-Patchwork-Id: 10743707\nX-Patchwork-Delegate: kvalo@adurom.com\nFrom: =?utf-8?q?Tomislav_Po=C5=BEega?= <pozega.tomislav@gmail.com>\nTo: linux-wireless@vger.kernel.org\nCc: kvalo@codeaurora.org, hauke@hauke-m.de, nbd@nbd.name,\n        john@phrozen.org, sgruszka@redhat.com, daniel@makrotopia.org\nSubject: [PATCH 2/2] rt2x00: define RF5592 in init_eeprom routine\nDate: Thu, 27 Dec 2018 15:05:26 +0100\nMessage-Id: <1545919526-4074-2-git-send-email-pozega.tomislav@gmail.com>\nX-Mailer: git-send-email 1.7.0.4\nIn-Reply-To: <1545919526-4074-1-git-send-email-pozega.tomislav@gmail.com>\nReferences: <1545919526-4074-1-git-send-email-pozega.tomislav@gmail.com>\nMIME-Version: 1.0\nSender: linux-wireless-owner@vger.kernel.org\nPrecedence: bulk\nList-ID: <linux-wireless.vger.kernel.org>\nX-Mailing-List: linux-wireless@vger.kernel.org\nX-Virus-Scanned: ClamAV using ClamSMTP\n\nThis patch fixes following crash on Linksys EA2750 during 5GHz wifi\ninit:\n\n[    7.955153] rt2800pci 0000:01:00.0: card - bus=0x1, slot = 0x0 irq=4\n[    7.962259] rt2800pci 0000:01:00.0: loaded eeprom from mtd device \"Factory\"\n[    7.969435] ieee80211 phy0: rt2x00_set_rt: Info - RT chipset 5592, rev 0222 detected\n[    7.977348] ieee80211 phy0: rt2800_init_eeprom: Error - Invalid RF chipset 0x0000 detected\n[    7.985793] ieee80211 phy0: rt2x00lib_probe_dev: Error - Failed to allocate device\n[    7.993569] CPU 0 Unable to handle kernel paging request at virtual address 00000024, epc == 800c8f54, ra == 80249ff8\n[    8.004408] Oops[#1]:\n\nSigned-off-by: Tomislav Požega <pozega.tomislav@gmail.com>\n---\n drivers/net/wireless/ralink/rt2x00/rt2800lib.c |    2 ++\n 1 files changed, 2 insertions(+), 0 deletions(-)\n\n--- a/drivers/net/wireless/ralink/rt2x00/rt2800lib.c\n+++ b/drivers/net/wireless/ralink/rt2x00/rt2800lib.c\n@@ -9435,6 +9435,8 @@ static int rt2800_init_eeprom(struct rt2\n \t\trf = RF3853;\n \telse if (rt2x00_rt(rt2x00dev, RT5350))\n \t\trf = RF5350;\n+\telse if (rt2x00_rt(rt2x00dev, RT5592))\n+\t\trf = RF5592;\n \telse\n \t\trf = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE);\n \n"
  },
  {
    "path": "package/kernel/mac80211/patches/rt2x00/100-rt2x00_options.patch",
    "content": "--- a/drivers/net/wireless/ralink/rt2x00/Kconfig\n+++ b/drivers/net/wireless/ralink/rt2x00/Kconfig\n@@ -226,36 +226,37 @@ config RT2800SOC\n \n \n config RT2800_LIB\n-\ttristate\n+\ttristate \"RT2800 USB/PCI support\"\n \tdepends on m\n \n config RT2800_LIB_MMIO\n-\ttristate\n+\ttristate \"RT2800 MMIO support\"\n \tdepends on m\n \tselect RT2X00_LIB_MMIO\n \tselect RT2800_LIB\n \n config RT2X00_LIB_MMIO\n-\ttristate\n+\ttristate \"RT2x00 MMIO support\"\n \tdepends on m\n \n config RT2X00_LIB_PCI\n-\ttristate\n+\ttristate \"RT2x00 PCI support\"\n \tdepends on m\n \tselect RT2X00_LIB\n \n config RT2X00_LIB_SOC\n-\ttristate\n+\ttristate \"RT2x00 SoC support\"\n+\tdepends on SOC_RT288X || SOC_RT305X || SOC_MT7620\n \tdepends on m\n \tselect RT2X00_LIB\n \n config RT2X00_LIB_USB\n-\ttristate\n+\ttristate \"RT2x00 USB support\"\n \tdepends on m\n \tselect RT2X00_LIB\n \n config RT2X00_LIB\n-\ttristate\n+\ttristate \"RT2x00 support\"\n \tdepends on m\n \n config RT2X00_LIB_FIRMWARE\n"
  },
  {
    "path": "package/kernel/mac80211/patches/rt2x00/501-rt2x00-allow-to-build-rt2800soc-module-for-RT3883.patch",
    "content": "From 91094ed065f7794886b4a5490fd6de942f036bb4 Mon Sep 17 00:00:00 2001\nFrom: Gabor Juhos <juhosg@openwrt.org>\nDate: Sun, 24 Mar 2013 19:26:26 +0100\nSubject: [PATCH] rt2x00: allow to build rt2800soc module for RT3883\n\nSigned-off-by: Gabor Juhos <juhosg@openwrt.org>\n---\n drivers/net/wireless/ralink/rt2x00/Kconfig |    2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/drivers/net/wireless/ralink/rt2x00/Kconfig\n+++ b/drivers/net/wireless/ralink/rt2x00/Kconfig\n@@ -211,7 +211,7 @@ endif\n config RT2800SOC\n \ttristate \"Ralink WiSoC support\"\n \tdepends on m\n-\tdepends on SOC_RT288X || SOC_RT305X || SOC_MT7620\n+\tdepends on SOC_RT288X || SOC_RT305X || SOC_RT3883 || SOC_MT7620\n \tselect RT2X00_LIB_SOC\n \tselect RT2X00_LIB_MMIO\n \tselect RT2X00_LIB_CRYPTO\n@@ -246,7 +246,7 @@ config RT2X00_LIB_PCI\n \n config RT2X00_LIB_SOC\n \ttristate \"RT2x00 SoC support\"\n-\tdepends on SOC_RT288X || SOC_RT305X || SOC_MT7620\n+\tdepends on SOC_RT288X || SOC_RT305X || SOC_RT3883 || SOC_MT7620\n \tdepends on m\n \tselect RT2X00_LIB\n \n"
  },
  {
    "path": "package/kernel/mac80211/patches/rt2x00/601-rt2x00-introduce-rt2x00_platform_h.patch",
    "content": "--- /dev/null\n+++ b/include/linux/rt2x00_platform.h\n@@ -0,0 +1,19 @@\n+/*\n+ * Platform data definition for the rt2x00 driver\n+ *\n+ * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>\n+ *\n+ * This program is free software; you can redistribute it and/or modify it\n+ * under the terms of the GNU General Public License version 2 as published\n+ * by the Free Software Foundation.\n+ *\n+ */\n+\n+#ifndef _RT2X00_PLATFORM_H\n+#define _RT2X00_PLATFORM_H\n+\n+struct rt2x00_platform_data {\n+\tchar *eeprom_file_name;\n+};\n+\n+#endif /* _RT2X00_PLATFORM_H */\n--- a/drivers/net/wireless/ralink/rt2x00/rt2x00.h\n+++ b/drivers/net/wireless/ralink/rt2x00/rt2x00.h\n@@ -28,6 +28,7 @@\n #include <linux/average.h>\n #include <linux/usb.h>\n #include <linux/clk.h>\n+#include <linux/rt2x00_platform.h>\n \n #include <net/mac80211.h>\n \n"
  },
  {
    "path": "package/kernel/mac80211/patches/rt2x00/602-rt2x00-introduce-rt2x00eeprom.patch",
    "content": "--- a/local-symbols\n+++ b/local-symbols\n@@ -322,6 +322,7 @@ RT2X00_LIB_FIRMWARE=\n RT2X00_LIB_CRYPTO=\n RT2X00_LIB_LEDS=\n RT2X00_LIB_DEBUGFS=\n+RT2X00_LIB_EEPROM=\n RT2X00_DEBUG=\n WLAN_VENDOR_REALTEK=\n RTL8180=\n--- a/drivers/net/wireless/ralink/rt2x00/Kconfig\n+++ b/drivers/net/wireless/ralink/rt2x00/Kconfig\n@@ -70,6 +70,7 @@ config RT2800PCI\n \tselect RT2X00_LIB_MMIO\n \tselect RT2X00_LIB_PCI\n \tselect RT2X00_LIB_FIRMWARE\n+\tselect RT2X00_LIB_EEPROM\n \tselect RT2X00_LIB_CRYPTO\n \tdepends on CRC_CCITT\n \tdepends on EEPROM_93CX6\n@@ -216,6 +217,7 @@ config RT2800SOC\n \tselect RT2X00_LIB_MMIO\n \tselect RT2X00_LIB_CRYPTO\n \tselect RT2X00_LIB_FIRMWARE\n+\tselect RT2X00_LIB_EEPROM\n \tselect RT2800_LIB\n \tselect RT2800_LIB_MMIO\n \thelp\n@@ -266,6 +268,9 @@ config RT2X00_LIB_FIRMWARE\n config RT2X00_LIB_CRYPTO\n \tbool\n \n+config RT2X00_LIB_EEPROM\n+\tbool\n+\n config RT2X00_LIB_LEDS\n \tbool\n \tdefault y if (RT2X00_LIB=y && LEDS_CLASS=y) || (RT2X00_LIB=m && LEDS_CLASS!=n)\n--- a/drivers/net/wireless/ralink/rt2x00/Makefile\n+++ b/drivers/net/wireless/ralink/rt2x00/Makefile\n@@ -8,6 +8,7 @@ rt2x00lib-$(CPTCFG_RT2X00_LIB_DEBUGFS)\t+\n rt2x00lib-$(CPTCFG_RT2X00_LIB_CRYPTO)\t+= rt2x00crypto.o\n rt2x00lib-$(CPTCFG_RT2X00_LIB_FIRMWARE)\t+= rt2x00firmware.o\n rt2x00lib-$(CPTCFG_RT2X00_LIB_LEDS)\t+= rt2x00leds.o\n+rt2x00lib-$(CPTCFG_RT2X00_LIB_EEPROM)\t+= rt2x00eeprom.o\n \n obj-$(CPTCFG_RT2X00_LIB)\t\t+= rt2x00lib.o\n obj-$(CPTCFG_RT2X00_LIB_MMIO)\t\t+= rt2x00mmio.o\n--- a/drivers/net/wireless/ralink/rt2x00/rt2800lib.h\n+++ b/drivers/net/wireless/ralink/rt2x00/rt2800lib.h\n@@ -37,6 +37,8 @@ struct rt2800_drv_data {\n \tstruct ieee80211_sta *wcid_to_sta[STA_IDS_SIZE];\n };\n \n+#include \"rt2800.h\"\n+\n struct rt2800_ops {\n \tu32 (*register_read)(struct rt2x00_dev *rt2x00dev,\n \t\t\t      const unsigned int offset);\n@@ -135,6 +137,15 @@ static inline int rt2800_read_eeprom(str\n {\n \tconst struct rt2800_ops *rt2800ops = rt2x00dev->ops->drv;\n \n+\tif (rt2x00dev->eeprom_file) {\n+\t\tmemcpy(rt2x00dev->eeprom, rt2x00dev->eeprom_file->data,\n+\t\t       EEPROM_SIZE);\n+\t\treturn 0;\n+\t}\n+\n+\tif (!rt2800ops->read_eeprom)\n+\t\treturn -EINVAL;\n+\n \treturn rt2800ops->read_eeprom(rt2x00dev);\n }\n \n--- a/drivers/net/wireless/ralink/rt2x00/rt2800soc.c\n+++ b/drivers/net/wireless/ralink/rt2x00/rt2800soc.c\n@@ -90,19 +90,6 @@ static int rt2800soc_set_device_state(st\n \treturn retval;\n }\n \n-static int rt2800soc_read_eeprom(struct rt2x00_dev *rt2x00dev)\n-{\n-\tvoid __iomem *base_addr = ioremap(0x1F040000, EEPROM_SIZE);\n-\n-\tif (!base_addr)\n-\t\treturn -ENOMEM;\n-\n-\tmemcpy_fromio(rt2x00dev->eeprom, base_addr, EEPROM_SIZE);\n-\n-\tiounmap(base_addr);\n-\treturn 0;\n-}\n-\n /* Firmware functions */\n static char *rt2800soc_get_firmware_name(struct rt2x00_dev *rt2x00dev)\n {\n@@ -167,7 +154,6 @@ static const struct rt2800_ops rt2800soc\n \t.register_multiread\t= rt2x00mmio_register_multiread,\n \t.register_multiwrite\t= rt2x00mmio_register_multiwrite,\n \t.regbusy_read\t\t= rt2x00mmio_regbusy_read,\n-\t.read_eeprom\t\t= rt2800soc_read_eeprom,\n \t.hwcrypt_disabled\t= rt2800soc_hwcrypt_disabled,\n \t.drv_write_firmware\t= rt2800soc_write_firmware,\n \t.drv_init_registers\t= rt2800mmio_init_registers,\n--- a/drivers/net/wireless/ralink/rt2x00/rt2x00.h\n+++ b/drivers/net/wireless/ralink/rt2x00/rt2x00.h\n@@ -703,6 +703,7 @@ enum rt2x00_capability_flags {\n \tREQUIRE_HT_TX_DESC,\n \tREQUIRE_PS_AUTOWAKE,\n \tREQUIRE_DELAYED_RFKILL,\n+\tREQUIRE_EEPROM_FILE,\n \n \t/*\n \t * Capabilities\n@@ -980,6 +981,11 @@ struct rt2x00_dev {\n \tconst struct firmware *fw;\n \n \t/*\n+\t * EEPROM image.\n+\t */\n+\tconst struct firmware *eeprom_file;\n+\n+\t/*\n \t * FIFO for storing tx status reports between isr and tasklet.\n \t */\n \tDECLARE_KFIFO_PTR(txstatus_fifo, u32);\n--- a/drivers/net/wireless/ralink/rt2x00/rt2x00dev.c\n+++ b/drivers/net/wireless/ralink/rt2x00/rt2x00dev.c\n@@ -1401,6 +1401,10 @@ int rt2x00lib_probe_dev(struct rt2x00_de\n \tINIT_DELAYED_WORK(&rt2x00dev->autowakeup_work, rt2x00lib_autowakeup);\n \tINIT_WORK(&rt2x00dev->sleep_work, rt2x00lib_sleep);\n \n+\tretval = rt2x00lib_load_eeprom_file(rt2x00dev);\n+\tif (retval)\n+\t\tgoto exit;\n+\n \t/*\n \t * Let the driver probe the device to detect the capabilities.\n \t */\n@@ -1541,6 +1545,11 @@ void rt2x00lib_remove_dev(struct rt2x00_\n \t * Free the driver data.\n \t */\n \tkfree(rt2x00dev->drv_data);\n+\n+\t/*\n+\t * Free EEPROM image.\n+\t */\n+\trt2x00lib_free_eeprom_file(rt2x00dev);\n }\n EXPORT_SYMBOL_GPL(rt2x00lib_remove_dev);\n \n--- /dev/null\n+++ b/drivers/net/wireless/ralink/rt2x00/rt2x00eeprom.c\n@@ -0,0 +1,106 @@\n+/*\n+\tCopyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>\n+\tCopyright (C) 2004 - 2009 Gertjan van Wingerde <gwingerde@gmail.com>\n+\t<http://rt2x00.serialmonkey.com>\n+\n+\tThis program is free software; you can redistribute it and/or modify\n+\tit under the terms of the GNU General Public License as published by\n+\tthe Free Software Foundation; either version 2 of the License, or\n+\t(at your option) any later version.\n+\n+\tThis program is distributed in the hope that it will be useful,\n+\tbut WITHOUT ANY WARRANTY; without even the implied warranty of\n+\tMERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n+\tGNU General Public License for more details.\n+\n+\tYou should have received a copy of the GNU General Public License\n+\talong with this program; if not, write to the\n+\tFree Software Foundation, Inc.,\n+\t59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.\n+ */\n+\n+/*\n+\tModule: rt2x00lib\n+\tAbstract: rt2x00 eeprom file loading routines.\n+ */\n+\n+#include <linux/kernel.h>\n+#include <linux/module.h>\n+\n+#include \"rt2x00.h\"\n+#include \"rt2x00lib.h\"\n+\n+static const char *\n+rt2x00lib_get_eeprom_file_name(struct rt2x00_dev *rt2x00dev)\n+{\n+\tstruct rt2x00_platform_data *pdata = rt2x00dev->dev->platform_data;\n+\n+\tif (pdata && pdata->eeprom_file_name)\n+\t\treturn pdata->eeprom_file_name;\n+\n+\treturn NULL\n+}\n+\n+static int rt2x00lib_request_eeprom_file(struct rt2x00_dev *rt2x00dev)\n+{\n+\tconst struct firmware *ee;\n+\tconst char *ee_name;\n+\tint retval;\n+\n+\tee_name = rt2x00lib_get_eeprom_file_name(rt2x00dev);\n+\tif (!ee_name && test_bit(REQUIRE_EEPROM_FILE, &rt2x00dev->cap_flags)) {\n+\t\trt2x00_err(rt2x00dev, \"Required EEPROM name is missing.\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (!ee_name)\n+\t\treturn 0;\n+\n+\trt2x00_info(rt2x00dev, \"Loading EEPROM data from '%s'.\\n\", ee_name);\n+\n+\tretval = request_firmware(&ee, ee_name, rt2x00dev->dev);\n+\tif (retval) {\n+\t\trt2x00_err(rt2x00dev, \"Failed to request EEPROM.\\n\");\n+\t\treturn retval;\n+\t}\n+\n+\tif (!ee || !ee->size || !ee->data) {\n+\t\trt2x00_err(rt2x00dev, \"Failed to read EEPROM file.\\n\");\n+\t\tretval = -ENOENT;\n+\t\tgoto err_exit;\n+\t}\n+\n+\tif (ee->size != rt2x00dev->ops->eeprom_size) {\n+\t\trt2x00_err(rt2x00dev,\n+\t\t\t   \"EEPROM file size is invalid, it should be %d bytes\\n\",\n+\t\t\t   rt2x00dev->ops->eeprom_size);\n+\t\tretval = -EINVAL;\n+\t\tgoto err_release_ee;\n+\t}\n+\n+\trt2x00dev->eeprom_file = ee;\n+\treturn 0;\n+\n+err_release_ee:\n+\trelease_firmware(ee);\n+err_exit:\n+\treturn retval;\n+}\n+\n+int rt2x00lib_load_eeprom_file(struct rt2x00_dev *rt2x00dev)\n+{\n+\tint retval;\n+\n+\tretval = rt2x00lib_request_eeprom_file(rt2x00dev);\n+\tif (retval)\n+\t\treturn retval;\n+\n+\treturn 0;\n+}\n+\n+void rt2x00lib_free_eeprom_file(struct rt2x00_dev *rt2x00dev)\n+{\n+\tif (rt2x00dev->eeprom_file && rt2x00dev->eeprom_file->size)\n+\t\trelease_firmware(rt2x00dev->eeprom_file);\n+\trt2x00dev->eeprom_file = NULL;\n+}\n--- a/drivers/net/wireless/ralink/rt2x00/rt2x00lib.h\n+++ b/drivers/net/wireless/ralink/rt2x00/rt2x00lib.h\n@@ -286,6 +286,22 @@ static inline void rt2x00lib_free_firmwa\n #endif /* CPTCFG_RT2X00_LIB_FIRMWARE */\n \n /*\n+ * EEPROM file handlers.\n+ */\n+#ifdef CPTCFG_RT2X00_LIB_EEPROM\n+int rt2x00lib_load_eeprom_file(struct rt2x00_dev *rt2x00dev);\n+void rt2x00lib_free_eeprom_file(struct rt2x00_dev *rt2x00dev);\n+#else\n+static inline int rt2x00lib_load_eeprom_file(struct rt2x00_dev *rt2x00dev)\n+{\n+\treturn 0;\n+}\n+static inline void rt2x00lib_free_eeprom_file(struct rt2x00_dev *rt2x00dev)\n+{\n+}\n+#endif /* CPTCFG_RT2X00_LIB_EEPROM */\n+\n+/*\n  * Debugfs handlers.\n  */\n #ifdef CPTCFG_RT2X00_LIB_DEBUGFS\n--- a/drivers/net/wireless/ralink/rt2x00/rt2x00soc.c\n+++ b/drivers/net/wireless/ralink/rt2x00/rt2x00soc.c\n@@ -86,6 +86,7 @@ int rt2x00soc_probe(struct platform_devi\n \tif (IS_ERR(rt2x00dev->clk))\n \t\trt2x00dev->clk = NULL;\n \n+\tset_bit(REQUIRE_EEPROM_FILE, &rt2x00dev->cap_flags);\n \trt2x00_set_chip_intf(rt2x00dev, RT2X00_CHIP_INTF_SOC);\n \n \tretval = rt2x00soc_alloc_reg(rt2x00dev);\n"
  },
  {
    "path": "package/kernel/mac80211/patches/rt2x00/603-rt2x00-of_load_eeprom_filename.patch",
    "content": "--- a/drivers/net/wireless/ralink/rt2x00/rt2x00eeprom.c\n+++ b/drivers/net/wireless/ralink/rt2x00/rt2x00eeprom.c\n@@ -26,6 +26,7 @@\n \n #include <linux/kernel.h>\n #include <linux/module.h>\n+#include <linux/of.h>\n \n #include \"rt2x00.h\"\n #include \"rt2x00lib.h\"\n@@ -34,11 +35,21 @@ static const char *\n rt2x00lib_get_eeprom_file_name(struct rt2x00_dev *rt2x00dev)\n {\n \tstruct rt2x00_platform_data *pdata = rt2x00dev->dev->platform_data;\n+#ifdef CONFIG_OF\n+\tstruct device_node *np;\n+\tconst char *eep;\n+#endif\n \n \tif (pdata && pdata->eeprom_file_name)\n \t\treturn pdata->eeprom_file_name;\n \n-\treturn NULL\n+#ifdef CONFIG_OF\n+\tnp = rt2x00dev->dev->of_node;\n+\tif (np && of_property_read_string(np, \"ralink,eeprom\", &eep) == 0)\n+\t    return eep;\n+#endif\n+\n+\treturn NULL;\n }\n \n static int rt2x00lib_request_eeprom_file(struct rt2x00_dev *rt2x00dev)\n"
  },
  {
    "path": "package/kernel/mac80211/patches/rt2x00/604-rt2x00-load-eeprom-on-SoC-from-a-mtd-device-defines-.patch",
    "content": "From 339fe73f340161a624cc08e738d2244814852c3e Mon Sep 17 00:00:00 2001\nFrom: John Crispin <blogic@openwrt.org>\nDate: Sun, 17 Mar 2013 00:55:04 +0100\nSubject: [PATCH] rt2x00: load eeprom on SoC from a mtd device defines inside\n OF\n\nSigned-off-by: John Crispin <blogic@openwrt.org>\n---\n drivers/net/wireless/ralink/rt2x00/Kconfig        |  1 +\n drivers/net/wireless/ralink/rt2x00/rt2x00eeprom.c | 65 +++++++++++++++++++++++\n 2 files changed, 66 insertions(+)\n\n--- a/drivers/net/wireless/ralink/rt2x00/Kconfig\n+++ b/drivers/net/wireless/ralink/rt2x00/Kconfig\n@@ -220,6 +220,7 @@ config RT2800SOC\n \tselect RT2X00_LIB_EEPROM\n \tselect RT2800_LIB\n \tselect RT2800_LIB_MMIO\n+\tselect MTD if SOC_RT288X || SOC_RT305X\n \thelp\n \t  This adds support for Ralink WiSoC devices.\n \t  Supported chips: RT2880, RT3050, RT3052, RT3350, RT3352.\n--- a/drivers/net/wireless/ralink/rt2x00/rt2x00eeprom.c\n+++ b/drivers/net/wireless/ralink/rt2x00/rt2x00eeprom.c\n@@ -26,11 +26,76 @@\n \n #include <linux/kernel.h>\n #include <linux/module.h>\n+#if IS_ENABLED(CONFIG_MTD)\n+#include <linux/mtd/mtd.h>\n+#include <linux/mtd/partitions.h>\n+#endif\n #include <linux/of.h>\n \n #include \"rt2x00.h\"\n #include \"rt2x00lib.h\"\n \n+#if IS_ENABLED(CONFIG_MTD)\n+static int rt2800lib_read_eeprom_mtd(struct rt2x00_dev *rt2x00dev)\n+{\n+\tint ret = -EINVAL;\n+#ifdef CONFIG_OF\n+\tstatic struct firmware mtd_fw;\n+\tstruct device_node *np = rt2x00dev->dev->of_node, *mtd_np = NULL;\n+\tsize_t retlen, len = rt2x00dev->ops->eeprom_size;\n+\tint i, size, offset = 0;\n+\tstruct mtd_info *mtd;\n+\tconst char *part;\n+\tconst __be32 *list;\n+\tphandle phandle;\n+\n+\tlist = of_get_property(np, \"ralink,mtd-eeprom\", &size);\n+\tif (!list)\n+\t\treturn -ENOENT;\n+\n+\tphandle = be32_to_cpup(list++);\n+\tif (phandle)\n+\t\tmtd_np = of_find_node_by_phandle(phandle);\n+\tif (!mtd_np) {\n+\t\tdev_err(rt2x00dev->dev, \"failed to load mtd phandle\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tpart = of_get_property(mtd_np, \"label\", NULL);\n+\tif (!part)\n+\t\tpart = mtd_np->name;\n+\n+\tmtd = get_mtd_device_nm(part);\n+\tif (IS_ERR(mtd)) {\n+\t\tdev_err(rt2x00dev->dev, \"failed to get mtd device \\\"%s\\\"\\n\", part);\n+\t\treturn PTR_ERR(mtd);\n+\t}\n+\n+\tif (size > sizeof(*list))\n+\t\toffset = be32_to_cpup(list);\n+\n+\tret = mtd_read(mtd, offset, len, &retlen, (u_char *) rt2x00dev->eeprom);\n+\tput_mtd_device(mtd);\n+\n+\tif ((retlen != rt2x00dev->ops->eeprom_size) || ret) {\n+\t\tdev_err(rt2x00dev->dev, \"failed to load eeprom from device \\\"%s\\\"\\n\", part);\n+\t\treturn ret;\n+\t}\n+\n+\tif (of_find_property(np, \"ralink,mtd-eeprom-swap\", NULL))\n+\t\tfor (i = 0; i < len/sizeof(u16); i++)\n+\t\t\trt2x00dev->eeprom[i] = swab16(rt2x00dev->eeprom[i]);\n+\n+\trt2x00dev->eeprom_file = &mtd_fw;\n+\tmtd_fw.data = (const u8 *) rt2x00dev->eeprom;\n+\n+\tdev_info(rt2x00dev->dev, \"loaded eeprom from mtd device \\\"%s\\\"\\n\", part);\n+#endif\n+\n+\treturn ret;\n+}\n+#endif\n+\n static const char *\n rt2x00lib_get_eeprom_file_name(struct rt2x00_dev *rt2x00dev)\n {\n@@ -58,6 +123,11 @@ static int rt2x00lib_request_eeprom_file\n \tconst char *ee_name;\n \tint retval;\n \n+#if IS_ENABLED(CONFIG_MTD)\n+\tif (!rt2800lib_read_eeprom_mtd(rt2x00dev))\n+\t\treturn 0;\n+#endif\n+\n \tee_name = rt2x00lib_get_eeprom_file_name(rt2x00dev);\n \tif (!ee_name && test_bit(REQUIRE_EEPROM_FILE, &rt2x00dev->cap_flags)) {\n \t\trt2x00_err(rt2x00dev, \"Required EEPROM name is missing.\");\n"
  },
  {
    "path": "package/kernel/mac80211/patches/rt2x00/606-rt2x00-allow_disabling_bands_through_platform_data.patch",
    "content": "--- a/include/linux/rt2x00_platform.h\n+++ b/include/linux/rt2x00_platform.h\n@@ -14,6 +14,9 @@\n \n struct rt2x00_platform_data {\n \tchar *eeprom_file_name;\n+\n+\tint disable_2ghz;\n+\tint disable_5ghz;\n };\n \n #endif /* _RT2X00_PLATFORM_H */\n--- a/drivers/net/wireless/ralink/rt2x00/rt2x00dev.c\n+++ b/drivers/net/wireless/ralink/rt2x00/rt2x00dev.c\n@@ -1007,6 +1007,22 @@ static int rt2x00lib_probe_hw_modes(stru\n \tunsigned int num_rates;\n \tunsigned int i;\n \n+\tif (rt2x00dev->dev->platform_data) {\n+\t\tstruct rt2x00_platform_data *pdata;\n+\n+\t\tpdata = rt2x00dev->dev->platform_data;\n+\t\tif (pdata->disable_2ghz)\n+\t\t\tspec->supported_bands &= ~SUPPORT_BAND_2GHZ;\n+\t\tif (pdata->disable_5ghz)\n+\t\t\tspec->supported_bands &= ~SUPPORT_BAND_5GHZ;\n+\t}\n+\n+\tif ((spec->supported_bands & SUPPORT_BAND_BOTH) == 0) {\n+\t\trt2x00_err(rt2x00dev, \"No supported bands\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\n \tnum_rates = 0;\n \tif (spec->supported_rates & SUPPORT_RATE_CCK)\n \t\tnum_rates += 4;\n--- a/drivers/net/wireless/ralink/rt2x00/rt2x00.h\n+++ b/drivers/net/wireless/ralink/rt2x00/rt2x00.h\n@@ -408,6 +408,7 @@ struct hw_mode_spec {\n \tunsigned int supported_bands;\n #define SUPPORT_BAND_2GHZ\t0x00000001\n #define SUPPORT_BAND_5GHZ\t0x00000002\n+#define SUPPORT_BAND_BOTH\t(SUPPORT_BAND_2GHZ | SUPPORT_BAND_5GHZ)\n \n \tunsigned int supported_rates;\n #define SUPPORT_RATE_CCK\t0x00000001\n"
  },
  {
    "path": "package/kernel/mac80211/patches/rt2x00/607-rt2x00-add_platform_data_mac_addr.patch",
    "content": "--- a/drivers/net/wireless/ralink/rt2x00/rt2x00dev.c\n+++ b/drivers/net/wireless/ralink/rt2x00/rt2x00dev.c\n@@ -989,6 +989,12 @@ static void rt2x00lib_rate(struct ieee80\n \n void rt2x00lib_set_mac_address(struct rt2x00_dev *rt2x00dev, u8 *eeprom_mac_addr)\n {\n+\tstruct rt2x00_platform_data *pdata;\n+\n+\tpdata = rt2x00dev->dev->platform_data;\n+\tif (pdata && pdata->mac_address)\n+\t\tether_addr_copy(eeprom_mac_addr, pdata->mac_address);\n+\n \tof_get_mac_address(rt2x00dev->dev->of_node, eeprom_mac_addr);\n \n \tif (!is_valid_ether_addr(eeprom_mac_addr)) {\n--- a/include/linux/rt2x00_platform.h\n+++ b/include/linux/rt2x00_platform.h\n@@ -14,6 +14,7 @@\n \n struct rt2x00_platform_data {\n \tchar *eeprom_file_name;\n+\tconst u8 *mac_address;\n \n \tint disable_2ghz;\n \tint disable_5ghz;\n"
  },
  {
    "path": "package/kernel/mac80211/patches/rt2x00/608-rt2x00-allow_disabling_bands_through_dts.patch",
    "content": "--- a/drivers/net/wireless/ralink/rt2x00/rt2x00dev.c\n+++ b/drivers/net/wireless/ralink/rt2x00/rt2x00dev.c\n@@ -1012,6 +1012,16 @@ static int rt2x00lib_probe_hw_modes(stru\n \tstruct ieee80211_rate *rates;\n \tunsigned int num_rates;\n \tunsigned int i;\n+#ifdef CONFIG_OF\n+\tstruct device_node *np = rt2x00dev->dev->of_node;\n+\tunsigned int enabled;\n+\tif (!of_property_read_u32(np, \"ralink,2ghz\",\n+                                          &enabled) && !enabled)\n+\t\tspec->supported_bands &= ~SUPPORT_BAND_2GHZ;\n+\tif (!of_property_read_u32(np, \"ralink,5ghz\",\n+                                          &enabled) && !enabled)\n+\t\tspec->supported_bands &= ~SUPPORT_BAND_5GHZ;\n+#endif /* CONFIG_OF */\n \n \tif (rt2x00dev->dev->platform_data) {\n \t\tstruct rt2x00_platform_data *pdata;\n"
  },
  {
    "path": "package/kernel/mac80211/patches/rt2x00/609-rt2x00-make-wmac-loadable-via-OF-on-rt288x-305x-SoC.patch",
    "content": "From 04dbd87265f6ba4a373b211ba324b437d224fb2d Mon Sep 17 00:00:00 2001\nFrom: John Crispin <blogic@openwrt.org>\nDate: Sun, 17 Mar 2013 00:03:31 +0100\nSubject: [PATCH 21/38] rt2x00: make wmac loadable via OF on rt288x/305x SoC\n\nThis patch ads the match table to allow loading the wmac support from a\ndevicetree.\n\nSigned-off-by: John Crispin <blogic@openwrt.org>\n---\n drivers/net/wireless/ralink/rt2x00/rt2800pci.c |    7 +++++++\n 1 file changed, 7 insertions(+)\n\n--- a/drivers/net/wireless/ralink/rt2x00/rt2800soc.c\n+++ b/drivers/net/wireless/ralink/rt2x00/rt2800soc.c\n@@ -224,10 +224,17 @@ static int rt2800soc_probe(struct platfo\n \treturn rt2x00soc_probe(pdev, &rt2800soc_ops);\n }\n \n+static const struct of_device_id rt2880_wmac_match[] = {\n+\t{ .compatible = \"ralink,rt2880-wmac\" },\n+\t{},\n+};\n+MODULE_DEVICE_TABLE(of, rt2880_wmac_match);\n+\n static struct platform_driver rt2800soc_driver = {\n \t.driver\t\t= {\n \t\t.name\t\t= \"rt2800_wmac\",\n \t\t.mod_name\t= KBUILD_MODNAME,\n+\t\t.of_match_table\t= rt2880_wmac_match,\n \t},\n \t.probe\t\t= rt2800soc_probe,\n \t.remove\t\t= rt2x00soc_remove,\n"
  },
  {
    "path": "package/kernel/mac80211/patches/rt2x00/610-rt2x00-change-led-polarity-from-OF.patch",
    "content": "--- a/drivers/net/wireless/ralink/rt2x00/rt2800lib.c\n+++ b/drivers/net/wireless/ralink/rt2x00/rt2800lib.c\n@@ -25,6 +25,7 @@\n #include <linux/kernel.h>\n #include <linux/module.h>\n #include <linux/slab.h>\n+#include <linux/of.h>\n \n #include \"rt2x00.h\"\n #include \"rt2800lib.h\"\n@@ -9549,6 +9550,17 @@ static int rt2800_init_eeprom(struct rt2\n \trt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);\n \trt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);\n \n+\t{\n+\t\tstruct device_node *np = rt2x00dev->dev->of_node;\n+\t\tunsigned int led_polarity;\n+\n+\t\t/* Allow overriding polarity from OF */\n+\t\tif (!of_property_read_u32(np, \"ralink,led-polarity\",\n+\t\t\t\t\t  &led_polarity))\n+\t\t\trt2x00_set_field16(&eeprom, EEPROM_FREQ_LED_POLARITY,\n+\t\t\t\t\t   led_polarity);\n+\t}\n+\n \trt2x00dev->led_mcu_reg = eeprom;\n #endif /* CPTCFG_RT2X00_LIB_LEDS */\n \n--- a/drivers/net/wireless/ralink/rt2x00/rt2x00leds.c\n+++ b/drivers/net/wireless/ralink/rt2x00/rt2x00leds.c\n@@ -98,6 +98,9 @@ static int rt2x00leds_register_led(struc\n \tled->led_dev.name = name;\n \tled->led_dev.brightness = LED_OFF;\n \n+\tif (rt2x00_is_soc(rt2x00dev))\n+\t\tled->led_dev.brightness_set(&led->led_dev, LED_OFF);\n+\n \tretval = led_classdev_register(device, &led->led_dev);\n \tif (retval) {\n \t\trt2x00_err(rt2x00dev, \"Failed to register led handler\\n\");\n"
  },
  {
    "path": "package/kernel/mac80211/patches/rt2x00/611-rt2x00-add-AP+STA-support.patch",
    "content": "--- a/drivers/net/wireless/ralink/rt2x00/rt2x00dev.c\n+++ b/drivers/net/wireless/ralink/rt2x00/rt2x00dev.c\n@@ -1340,7 +1340,7 @@ static inline void rt2x00lib_set_if_comb\n \t */\n \tif_limit = &rt2x00dev->if_limits_ap;\n \tif_limit->max = rt2x00dev->ops->max_ap_intf;\n-\tif_limit->types = BIT(NL80211_IFTYPE_AP);\n+\tif_limit->types = BIT(NL80211_IFTYPE_AP) | BIT(NL80211_IFTYPE_STATION);\n #ifdef CPTCFG_MAC80211_MESH\n \tif_limit->types |= BIT(NL80211_IFTYPE_MESH_POINT);\n #endif\n"
  },
  {
    "path": "package/kernel/mac80211/patches/rt2x00/612-rt2x00-led-tpt-trigger-support.patch",
    "content": "From: David Bauer <mail@david-bauer.net>\nDate: Mon, 16 Dec 2019 20:47:06 +0100\nSubject: [PATCH] rt2x00: add throughput LED trigger\n\nThis adds a (currently missing) throughput LED trigger for the rt2x00\ndriver. Previously, LED triggers had to be assigned to the netdev, which\nwas limited to a single VAP.\n\nSigned-off-by: David Bauer <mail@david-bauer.net>\nTested-by: Christoph Krapp <achterin@googlemail.com>\n\n--- a/drivers/net/wireless/ralink/rt2x00/rt2x00dev.c\n+++ b/drivers/net/wireless/ralink/rt2x00/rt2x00dev.c\n@@ -1125,6 +1125,19 @@ static void rt2x00lib_remove_hw(struct r\n \tkfree(rt2x00dev->spec.channels_info);\n }\n \n+static const struct ieee80211_tpt_blink rt2x00_tpt_blink[] = {\n+\t{ .throughput = 0 * 1024, .blink_time = 334 },\n+\t{ .throughput = 1 * 1024, .blink_time = 260 },\n+\t{ .throughput = 2 * 1024, .blink_time = 220 },\n+\t{ .throughput = 5 * 1024, .blink_time = 190 },\n+\t{ .throughput = 10 * 1024, .blink_time = 170 },\n+\t{ .throughput = 25 * 1024, .blink_time = 150 },\n+\t{ .throughput = 54 * 1024, .blink_time = 130 },\n+\t{ .throughput = 120 * 1024, .blink_time = 110 },\n+\t{ .throughput = 265 * 1024, .blink_time = 80 },\n+\t{ .throughput = 586 * 1024, .blink_time = 50 },\n+};\n+\n static int rt2x00lib_probe_hw(struct rt2x00_dev *rt2x00dev)\n {\n \tstruct hw_mode_spec *spec = &rt2x00dev->spec;\n@@ -1206,6 +1219,10 @@ static int rt2x00lib_probe_hw(struct rt2\n \n #undef RT2X00_TASKLET_INIT\n \n+\tieee80211_create_tpt_led_trigger(rt2x00dev->hw,\n+\t\tIEEE80211_TPT_LEDTRIG_FL_RADIO, rt2x00_tpt_blink,\n+\t\tARRAY_SIZE(rt2x00_tpt_blink));\n+\n \t/*\n \t * Register HW.\n \t */\n"
  },
  {
    "path": "package/kernel/mac80211/patches/rt2x00/650-rt2x00-add-support-for-external-PA-on-MT7620.patch",
    "content": "From 9782a7f7488443568fa4d6088b73c9aff7eb8510 Mon Sep 17 00:00:00 2001\nFrom: Daniel Golle <daniel@makrotopia.org>\nDate: Wed, 19 Apr 2017 16:14:53 +0200\nSubject: [PATCH] rt2x00: add support for external PA on MT7620\nTo: Stanislaw Gruszka <sgruszka@redhat.com>\nCc: Helmut Schaa <helmut.schaa@googlemail.com>,\n    linux-wireless@vger.kernel.org,\n    Kalle Valo <kvalo@codeaurora.org>\nContent-Type: text/plain; charset=\"UTF-8\"\nContent-Transfer-Encoding: quoted-printable\n\nSigned-off-by: Daniel Golle <daniel@makrotopia.org>\nSigned-off-by: Tomislav Po=C5=BEega <pozega.tomislav@gmail.com>\n[pozega.tomislav@gmail.com: use chanreg and dccal helpers.]\n\n---\n drivers/net/wireless/ralink/rt2x00/rt2800.h    |  1 +\n drivers/net/wireless/ralink/rt2x00/rt2800lib.c | 70 +++++++++++++++++++++++++-\n 2 files changed, 70 insertions(+), 1 deletion(-)\n\n--- a/drivers/net/wireless/ralink/rt2x00/rt2800.h\n+++ b/drivers/net/wireless/ralink/rt2x00/rt2800.h\n@@ -2739,6 +2739,7 @@ enum rt2800_eeprom_word {\n #define EEPROM_NIC_CONF2_RX_STREAM\tFIELD16(0x000f)\n #define EEPROM_NIC_CONF2_TX_STREAM\tFIELD16(0x00f0)\n #define EEPROM_NIC_CONF2_CRYSTAL\tFIELD16(0x0600)\n+#define EEPROM_NIC_CONF2_EXTERNAL_PA\tFIELD16(0xc000)\n \n /*\n  * EEPROM LNA\n--- a/drivers/net/wireless/ralink/rt2x00/rt2800lib.c\n+++ b/drivers/net/wireless/ralink/rt2x00/rt2800lib.c\n@@ -4369,6 +4369,45 @@ static void rt2800_config_channel(struct\n \t\trt2800_iq_calibrate(rt2x00dev, rf->channel);\n \t}\n \n+\tif (rt2x00_rt(rt2x00dev, RT6352)) {\n+\t\tif (test_bit(CAPABILITY_EXTERNAL_PA_TX0,\n+\t\t\t     &rt2x00dev->cap_flags)) {\n+\t\t\trt2x00_warn(rt2x00dev, \"Using incomplete support for \" \\\n+\t\t\t\t\t       \"external PA\\n\");\n+\t\t\treg = rt2800_register_read(rt2x00dev, RF_CONTROL3);\n+\t\t\treg |= 0x00000101;\n+\t\t\trt2800_register_write(rt2x00dev, RF_CONTROL3, reg);\n+\n+\t\t\treg = rt2800_register_read(rt2x00dev, RF_BYPASS3);\n+\t\t\treg |= 0x00000101;\n+\t\t\trt2800_register_write(rt2x00dev, RF_BYPASS3, reg);\n+\n+\t\t\trt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0x73);\n+\t\t\trt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0x73);\n+\t\t\trt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0x73);\n+\t\t\trt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x27);\n+\t\t\trt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0xC8);\n+\t\t\trt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xA4);\n+\t\t\trt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x05);\n+\t\t\trt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x27);\n+\t\t\trt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0xC8);\n+\t\t\trt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xA4);\n+\t\t\trt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x05);\n+\t\t\trt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x27);\n+\t\t\trt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0xC8);\n+\t\t\trt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xA4);\n+\t\t\trt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x05);\n+\t\t\trt2800_rfcsr_write_dccal(rt2x00dev, 05, 0x00);\n+\n+\t\t\trt2800_register_write(rt2x00dev, TX0_RF_GAIN_CORRECT,\n+\t\t\t\t\t      0x36303636);\n+\t\t\trt2800_register_write(rt2x00dev, TX0_RF_GAIN_ATTEN,\n+\t\t\t\t\t      0x6C6C6B6C);\n+\t\t\trt2800_register_write(rt2x00dev, TX1_RF_GAIN_ATTEN,\n+\t\t\t\t\t      0x6C6C6B6C);\n+\t\t}\n+\t}\n+\n \tbbp = rt2800_bbp_read(rt2x00dev, 4);\n \trt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));\n \trt2800_bbp_write(rt2x00dev, 4, bbp);\n@@ -9578,7 +9617,8 @@ static int rt2800_init_eeprom(struct rt2\n \t */\n \teeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);\n \n-\tif (rt2x00_rt(rt2x00dev, RT3352)) {\n+\tif (rt2x00_rt(rt2x00dev, RT3352) ||\n+\t    rt2x00_rt(rt2x00dev, RT6352)) {\n \t\tif (rt2x00_get_field16(eeprom,\n \t\t    EEPROM_NIC_CONF1_EXTERNAL_TX0_PA_3352))\n \t\t    __set_bit(CAPABILITY_EXTERNAL_PA_TX0,\n@@ -9589,6 +9629,18 @@ static int rt2800_init_eeprom(struct rt2\n \t\t\t      &rt2x00dev->cap_flags);\n \t}\n \n+\teeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF2);\n+\n+\tif (rt2x00_rt(rt2x00dev, RT6352) && eeprom != 0 && eeprom != 0xffff) {\n+\t\tif (rt2x00_get_field16(eeprom,\n+\t\t    EEPROM_NIC_CONF2_EXTERNAL_PA)) {\n+\t\t    __set_bit(CAPABILITY_EXTERNAL_PA_TX0,\n+\t\t\t      &rt2x00dev->cap_flags);\n+\t\t    __set_bit(CAPABILITY_EXTERNAL_PA_TX1,\n+\t\t\t      &rt2x00dev->cap_flags);\n+\t\t}\n+\t}\n+\n \treturn 0;\n }\n \n"
  },
  {
    "path": "package/kernel/mac80211/patches/rt2x00/982-rt2x00-add-rf-self-txdc-calibration.patch",
    "content": "--- a/drivers/net/wireless/ralink/rt2x00/rt2800lib.c\n+++ b/drivers/net/wireless/ralink/rt2x00/rt2800lib.c\n@@ -8438,6 +8438,56 @@ static void rt2800_init_rfcsr_5592(struc\n \trt2800_led_open_drain_enable(rt2x00dev);\n }\n \n+static void rt2800_rf_self_txdc_cal(struct rt2x00_dev *rt2x00dev)\n+{\n+\tu8 rfb5r1_org, rfb7r1_org, rfvalue;\n+\tu32 mac0518, mac051c, mac0528, mac052c;\n+\tu8 i;\n+\n+\trt2x00_info(rt2x00dev, \"RF Tx self calibration start\\n\");\n+\tmac0518 = rt2800_register_read(rt2x00dev, RF_CONTROL0);\n+\tmac051c = rt2800_register_read(rt2x00dev, RF_BYPASS0);\n+\tmac0528 = rt2800_register_read(rt2x00dev, RF_CONTROL2);\n+\tmac052c = rt2800_register_read(rt2x00dev, RF_BYPASS2);\n+\n+\trt2800_register_write(rt2x00dev, RF_BYPASS0, 0x0);\n+\trt2800_register_write(rt2x00dev, RF_BYPASS2, 0x0);\n+\n+\trt2800_register_write(rt2x00dev, RF_CONTROL0, 0xC);\n+\trt2800_register_write(rt2x00dev, RF_BYPASS0, 0x3306);\n+\trt2800_register_write(rt2x00dev, RF_CONTROL2, 0x3330);\n+\trt2800_register_write(rt2x00dev, RF_BYPASS2, 0xfffff);\n+\trfb5r1_org = rt2800_rfcsr_read_bank(rt2x00dev, 5, 1);\n+\trfb7r1_org = rt2800_rfcsr_read_bank(rt2x00dev, 7, 1);\n+\n+\trt2800_rfcsr_write_bank(rt2x00dev, 5, 1, 0x4);\n+\tfor (i = 0; i < 100; i = i + 1) {\n+\t\tudelay(50);\n+\t\trfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 5, 1);\n+\t\tif((rfvalue & 0x04) != 0x4)\n+\t\t\tbreak;\n+\t}\n+\trt2800_rfcsr_write_bank(rt2x00dev, 5, 1, rfb5r1_org);\n+\n+\trt2800_rfcsr_write_bank(rt2x00dev, 7, 1, 0x4);\n+\tfor (i = 0; i < 100; i = i + 1) {\n+\t\tudelay(50);\n+\t\trfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 7, 1);\n+\t\tif((rfvalue & 0x04) != 0x4)\n+\t\t\tbreak;\n+\t}\n+\trt2800_rfcsr_write_bank(rt2x00dev, 7, 1, rfb7r1_org);\n+\n+\trt2800_register_write(rt2x00dev, RF_BYPASS0, 0x0);\n+\trt2800_register_write(rt2x00dev, RF_BYPASS2, 0x0);\n+\trt2800_register_write(rt2x00dev, RF_CONTROL0, mac0518);\n+\trt2800_register_write(rt2x00dev, RF_BYPASS0, mac051c);\n+\trt2800_register_write(rt2x00dev, RF_CONTROL2, mac0528);\n+\trt2800_register_write(rt2x00dev, RF_BYPASS2, mac052c);\n+\n+\trt2x00_info(rt2x00dev, \"RF Tx self calibration end\\n\");\n+}\n+\n static void rt2800_bbp_core_soft_reset(struct rt2x00_dev *rt2x00dev,\n \t\t\t\t       bool set_bw, bool is_ht40)\n {\n@@ -9045,6 +9095,7 @@ static void rt2800_init_rfcsr_6352(struc\n \trt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x00);\n \trt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x7C);\n \n+\trt2800_rf_self_txdc_cal(rt2x00dev);\n \trt2800_bw_filter_calibration(rt2x00dev, true);\n \trt2800_bw_filter_calibration(rt2x00dev, false);\n }\n"
  },
  {
    "path": "package/kernel/mac80211/patches/rt2x00/983-rt2x00-add-r-calibration.patch",
    "content": "--- a/drivers/net/wireless/ralink/rt2x00/rt2800lib.c\n+++ b/drivers/net/wireless/ralink/rt2x00/rt2800lib.c\n@@ -8488,6 +8488,155 @@ static void rt2800_rf_self_txdc_cal(stru\n \trt2x00_info(rt2x00dev, \"RF Tx self calibration end\\n\");\n }\n \n+static int rt2800_calcrcalibrationcode(struct rt2x00_dev *rt2x00dev, int d1, int d2)\n+{\n+\tint calcode;\n+\tcalcode = ((d2 - d1) * 1000) / 43;\n+\tif ((calcode%10) >= 5)\n+\t\tcalcode += 10;\n+\tcalcode = (calcode / 10);\n+\n+\treturn calcode;\n+}\n+\n+static void rt2800_r_calibration(struct rt2x00_dev *rt2x00dev)\n+{\n+\tu32 savemacsysctrl;\n+\tu8 saverfb0r1, saverfb0r34, saverfb0r35;\n+\tu8 saverfb5r4, saverfb5r17, saverfb5r18;\n+\tu8 saverfb5r19, saverfb5r20;\n+\tu8 savebbpr22, savebbpr47, savebbpr49;\n+\tu8 bytevalue = 0;\n+\tint rcalcode;\n+\tu8 r_cal_code = 0;\n+\tchar d1 = 0, d2 = 0;\n+\tu8 rfvalue;\n+\tu32 MAC_RF_BYPASS0, MAC_RF_CONTROL0, MAC_PWR_PIN_CFG;\n+\tu32 maccfg, macstatus;\n+\tint i;\n+\n+\tsaverfb0r1 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 1);\n+\tsaverfb0r34 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 34);\n+\tsaverfb0r35 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 35);\n+\tsaverfb5r4 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4);\n+\tsaverfb5r17 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 17);\n+\tsaverfb5r18 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 18);\n+\tsaverfb5r19 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 19);\n+\tsaverfb5r20 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 20);\n+\n+\tsavebbpr22 = rt2800_bbp_read(rt2x00dev, 22);\n+\tsavebbpr47 = rt2800_bbp_read(rt2x00dev, 47);\n+\tsavebbpr49 = rt2800_bbp_read(rt2x00dev, 49);\n+\n+\tsavemacsysctrl = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);\n+\tMAC_RF_BYPASS0 = rt2800_register_read(rt2x00dev, RF_BYPASS0);\n+\tMAC_RF_CONTROL0 = rt2800_register_read(rt2x00dev, RF_CONTROL0);\n+\tMAC_PWR_PIN_CFG = rt2800_register_read(rt2x00dev, PWR_PIN_CFG);\n+\n+\tmaccfg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);\n+\tmaccfg &= (~0x04);\n+\trt2800_register_write(rt2x00dev, MAC_SYS_CTRL, maccfg);\n+\n+\tfor (i = 0; i < 10000; i++) {\n+\t\tmacstatus = rt2800_register_read(rt2x00dev, MAC_STATUS_CFG);\n+\t\tif (macstatus & 0x1)\n+\t\t\tudelay(50);\n+\t\telse\n+\t\t\tbreak;\n+\t}\n+\n+\tif (i == 10000)\n+\t\trt2x00_warn(rt2x00dev, \"Wait MAC Tx Status to MAX !!!\\n\");\n+\n+\tmaccfg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);\n+\tmaccfg &= (~0x04);\n+\trt2800_register_write(rt2x00dev, MAC_SYS_CTRL, maccfg);\n+\n+\tfor (i = 0; i < 10000; i++) {\n+\t\tmacstatus = rt2800_register_read(rt2x00dev, MAC_STATUS_CFG);\n+\t\tif (macstatus & 0x2)\n+\t\t\tudelay(50);\n+\t\telse\n+\t\t\tbreak;\n+\t\t}\n+\n+\tif (i == 10000)\n+\t\trt2x00_warn(rt2x00dev, \"Wait MAC Rx Status to MAX !!!\\n\");\n+\n+\trfvalue = (MAC_RF_BYPASS0 | 0x3004);\n+\trt2800_register_write(rt2x00dev, RF_BYPASS0, rfvalue);\n+\trfvalue = (MAC_RF_CONTROL0 | (~0x3002));\n+\trt2800_register_write(rt2x00dev, RF_CONTROL0, rfvalue);\n+\n+\trt2800_rfcsr_write_bank(rt2x00dev, 5, 4, 0x27);\n+\trt2800_rfcsr_write_bank(rt2x00dev, 5, 17, 0x80);\n+\trt2800_rfcsr_write_bank(rt2x00dev, 5, 18, 0x83);\n+\trt2800_rfcsr_write_bank(rt2x00dev, 5, 19, 0x00);\n+\trt2800_rfcsr_write_bank(rt2x00dev, 5, 20, 0x20);\n+\n+\trt2800_rfcsr_write_bank(rt2x00dev, 0, 1, 0x00);\n+\trt2800_rfcsr_write_bank(rt2x00dev, 0, 34, 0x13);\n+\trt2800_rfcsr_write_bank(rt2x00dev, 0, 35, 0x00);\n+\n+\trt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x1);\n+\n+\trt2800_bbp_write(rt2x00dev, 47, 0x04);\n+\trt2800_bbp_write(rt2x00dev, 22, 0x80);\n+\tudelay(100);\n+\tbytevalue = rt2800_bbp_read(rt2x00dev, 49);\n+\tif (bytevalue > 128)\n+\t\td1 = bytevalue - 256;\n+\telse\n+\t\td1 = (char)bytevalue;\n+\trt2800_bbp_write(rt2x00dev, 22, 0x0);\n+\trt2800_rfcsr_write_bank(rt2x00dev, 0, 35, 0x01);\n+\n+\trt2800_bbp_write(rt2x00dev, 22, 0x80);\n+\tudelay(100);\n+\tbytevalue = rt2800_bbp_read(rt2x00dev, 49);\n+\tif (bytevalue > 128)\n+\t\td2 = bytevalue - 256;\n+\telse\n+\t\td2 = (char)bytevalue;\n+\trt2800_bbp_write(rt2x00dev, 22, 0x0);\n+\n+\trcalcode = rt2800_calcrcalibrationcode(rt2x00dev, d1, d2);\n+\tif (rcalcode < 0)\n+\t\tr_cal_code = 256 + rcalcode;\n+\telse\n+\t\tr_cal_code = (u8)rcalcode;\n+\n+\trt2800_rfcsr_write_bank(rt2x00dev, 0, 7, r_cal_code);\n+\n+\trt2800_bbp_write(rt2x00dev, 22, 0x0);\n+\n+\tbytevalue = rt2800_bbp_read(rt2x00dev, 21);\n+\tbytevalue |= 0x1;\n+\trt2800_bbp_write(rt2x00dev, 21, bytevalue);\n+\tbytevalue = rt2800_bbp_read(rt2x00dev, 21);\n+\tbytevalue &= (~0x1);\n+\trt2800_bbp_write(rt2x00dev, 21, bytevalue);\n+\n+\trt2800_rfcsr_write_bank(rt2x00dev, 0, 1, saverfb0r1);\n+\trt2800_rfcsr_write_bank(rt2x00dev, 0, 34, saverfb0r34);\n+\trt2800_rfcsr_write_bank(rt2x00dev, 0, 35, saverfb0r35);\n+\trt2800_rfcsr_write_bank(rt2x00dev, 5, 4, saverfb5r4);\n+\trt2800_rfcsr_write_bank(rt2x00dev, 5, 17, saverfb5r17);\n+\trt2800_rfcsr_write_bank(rt2x00dev, 5, 18, saverfb5r18);\n+\trt2800_rfcsr_write_bank(rt2x00dev, 5, 19, saverfb5r19);\n+\trt2800_rfcsr_write_bank(rt2x00dev, 5, 20, saverfb5r20);\n+\n+\trt2800_bbp_write(rt2x00dev, 22, savebbpr22);\n+\trt2800_bbp_write(rt2x00dev, 47, savebbpr47);\n+\trt2800_bbp_write(rt2x00dev, 49, savebbpr49);\n+\n+\trt2800_register_write(rt2x00dev, RF_BYPASS0, MAC_RF_BYPASS0);\n+\trt2800_register_write(rt2x00dev, RF_CONTROL0, MAC_RF_CONTROL0);\n+\n+\trt2800_register_write(rt2x00dev, MAC_SYS_CTRL, savemacsysctrl);\n+\trt2800_register_write(rt2x00dev, PWR_PIN_CFG, MAC_PWR_PIN_CFG);\n+}\n+\n static void rt2800_bbp_core_soft_reset(struct rt2x00_dev *rt2x00dev,\n \t\t\t\t       bool set_bw, bool is_ht40)\n {\n@@ -9095,6 +9244,7 @@ static void rt2800_init_rfcsr_6352(struc\n \trt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x00);\n \trt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x7C);\n \n+\trt2800_r_calibration(rt2x00dev);\n \trt2800_rf_self_txdc_cal(rt2x00dev);\n \trt2800_bw_filter_calibration(rt2x00dev, true);\n \trt2800_bw_filter_calibration(rt2x00dev, false);\n"
  },
  {
    "path": "package/kernel/mac80211/patches/rt2x00/984-rt2x00-add-rxdcoc-calibration.patch",
    "content": "--- a/drivers/net/wireless/ralink/rt2x00/rt2800lib.c\n+++ b/drivers/net/wireless/ralink/rt2x00/rt2800lib.c\n@@ -8637,6 +8637,70 @@ static void rt2800_r_calibration(struct\n \trt2800_register_write(rt2x00dev, PWR_PIN_CFG, MAC_PWR_PIN_CFG);\n }\n \n+static void rt2800_rxdcoc_calibration(struct rt2x00_dev *rt2x00dev)\n+{\n+\tu8 bbpreg = 0;\n+\tu32 macvalue = 0, macvalue1 = 0;\n+\tu8 saverfb0r2, saverfb5r4, saverfb7r4, rfvalue;\n+\tint i;\n+\n+\tsaverfb0r2 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 2);\n+\trfvalue = saverfb0r2;\n+\trfvalue |= 0x03;\n+\trt2800_rfcsr_write_bank(rt2x00dev, 0, 2, rfvalue);\n+\n+\trt2800_bbp_write(rt2x00dev, 158, 141);\n+\tbbpreg = rt2800_bbp_read(rt2x00dev, 159);\n+\tbbpreg |= 0x10;\n+\trt2800_bbp_write(rt2x00dev, 159, bbpreg);\n+\n+\tmacvalue = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);\n+\trt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x8);\n+\n+\tfor (i = 0; i < 10000; i++) {\n+\t\tmacvalue1 = rt2800_register_read(rt2x00dev, MAC_STATUS_CFG);\n+\t\tif (macvalue1 & 0x1)\n+\t\t\tudelay(50);\n+\t\telse\n+\t\t\tbreak;\n+\t}\n+\n+\tsaverfb5r4 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 0);\n+\tsaverfb7r4 = rt2800_rfcsr_read_bank(rt2x00dev, 7, 4);\n+\tsaverfb5r4 = saverfb5r4 & (~0x40);\n+\tsaverfb7r4 = saverfb7r4 & (~0x40);\n+\trt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x64);\n+\trt2800_rfcsr_write_bank(rt2x00dev, 5, 4, saverfb5r4);\n+\trt2800_rfcsr_write_bank(rt2x00dev, 7, 4, saverfb7r4);\n+\n+\trt2800_bbp_write(rt2x00dev, 158, 141);\n+\tbbpreg = rt2800_bbp_read(rt2x00dev, 159);\n+\tbbpreg = bbpreg & (~0x40);\n+\trt2800_bbp_write(rt2x00dev, 159, bbpreg);\n+\tbbpreg |= 0x48;\n+\trt2800_bbp_write(rt2x00dev, 159, bbpreg);\n+\n+\tfor (i = 0; i < 10000; i++) {\n+\t\tbbpreg = rt2800_bbp_read(rt2x00dev, 159);\n+\t\tif ((bbpreg & 0x40)==0)\n+\t\t\tbreak;\n+\t\tudelay(50);\n+\t}\n+\n+\tbbpreg = rt2800_bbp_read(rt2x00dev, 159);\n+\tbbpreg = bbpreg & (~0x40);\n+\trt2800_bbp_write(rt2x00dev, 159, bbpreg);\n+\n+\trt2800_register_write(rt2x00dev, MAC_SYS_CTRL, macvalue);\n+\n+\trt2800_bbp_write(rt2x00dev, 158, 141);\n+\tbbpreg = rt2800_bbp_read(rt2x00dev, 159);\n+\tbbpreg &= (~0x10);\n+\trt2800_bbp_write(rt2x00dev, 159, bbpreg);\n+\n+\trt2800_rfcsr_write_bank(rt2x00dev, 0, 2, saverfb0r2);\n+}\n+\n static void rt2800_bbp_core_soft_reset(struct rt2x00_dev *rt2x00dev,\n \t\t\t\t       bool set_bw, bool is_ht40)\n {\n@@ -9246,6 +9310,7 @@ static void rt2800_init_rfcsr_6352(struc\n \n \trt2800_r_calibration(rt2x00dev);\n \trt2800_rf_self_txdc_cal(rt2x00dev);\n+\trt2800_rxdcoc_calibration(rt2x00dev);\n \trt2800_bw_filter_calibration(rt2x00dev, true);\n \trt2800_bw_filter_calibration(rt2x00dev, false);\n }\n"
  },
  {
    "path": "package/kernel/mac80211/patches/rt2x00/985-rt2x00-add-rxiq-calibration.patch",
    "content": "--- a/drivers/net/wireless/ralink/rt2x00/rt2800lib.c\n+++ b/drivers/net/wireless/ralink/rt2x00/rt2800lib.c\n@@ -8701,6 +8701,384 @@ static void rt2800_rxdcoc_calibration(st\n \trt2800_rfcsr_write_bank(rt2x00dev, 0, 2, saverfb0r2);\n }\n \n+static u32 rt2800_do_sqrt_accumulation(u32 si) {\n+\tu32 root, root_pre, bit;\n+\tchar i;\n+\tbit = 1 << 15;\n+\troot = 0;\n+\tfor (i = 15; i >= 0; i = i - 1) {\n+\t\troot_pre = root + bit;\n+\t\tif ((root_pre*root_pre) <= si)\n+\t\t\troot = root_pre;\n+\t\tbit = bit >> 1;\n+\t}\n+\n+\treturn root;\n+}\n+\n+static void rt2800_rxiq_calibration(struct rt2x00_dev *rt2x00dev) {\n+\tu8 rfb0r1, rfb0r2, rfb0r42;\n+\tu8 rfb4r0, rfb4r19;\n+\tu8 rfb5r3, rfb5r4, rfb5r17, rfb5r18, rfb5r19, rfb5r20;\n+\tu8 rfb6r0, rfb6r19;\n+\tu8 rfb7r3, rfb7r4, rfb7r17, rfb7r18, rfb7r19, rfb7r20;\n+\n+\tu8 bbp1, bbp4;\n+\tu8 bbpr241, bbpr242;\n+\tu32 i;\n+\tu8 ch_idx;\n+\tu8 bbpval;\n+\tu8 rfval, vga_idx = 0;\n+\tint mi = 0, mq = 0, si = 0, sq = 0, riq = 0;\n+\tint sigma_i, sigma_q, r_iq, g_rx;\n+\tint g_imb;\n+\tint ph_rx;\n+\tu32 savemacsysctrl = 0;\n+\tu32 orig_RF_CONTROL0 = 0;\n+\tu32 orig_RF_BYPASS0 = 0;\n+\tu32 orig_RF_CONTROL1 = 0;\n+\tu32 orig_RF_BYPASS1 = 0;\n+\tu32 orig_RF_CONTROL3 = 0;\n+\tu32 orig_RF_BYPASS3 = 0;\n+\tu32 macstatus, bbpval1 = 0;\n+\tu8 rf_vga_table[] = {0x20, 0x21, 0x22, 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f};\n+\n+\tsavemacsysctrl = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);\n+\torig_RF_CONTROL0 = rt2800_register_read(rt2x00dev, RF_CONTROL0);\n+\torig_RF_BYPASS0 = rt2800_register_read(rt2x00dev, RF_BYPASS0);\n+\torig_RF_CONTROL1 = rt2800_register_read(rt2x00dev, RF_CONTROL1);\n+\torig_RF_BYPASS1 = rt2800_register_read(rt2x00dev, RF_BYPASS1);\n+\torig_RF_CONTROL3 = rt2800_register_read(rt2x00dev, RF_CONTROL3);\n+\torig_RF_BYPASS3 = rt2800_register_read(rt2x00dev, RF_BYPASS3);\n+\n+\tbbp1 = rt2800_bbp_read(rt2x00dev, 1);\n+\tbbp4 = rt2800_bbp_read(rt2x00dev, 4);\n+\n+\trt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x0);\n+\n+\tfor (i = 0; i < 10000; i++) {\n+\t\tmacstatus = rt2800_register_read(rt2x00dev, MAC_STATUS_CFG);\n+\t\tif (macstatus & 0x3)\n+\t\t\tudelay(50);\n+\t\telse\n+\t\t\tbreak;\n+\t}\n+\n+\tif (i == 10000)\n+\t\trt2x00_warn(rt2x00dev, \"Wait MAC Status to MAX !!!\\n\");\n+\n+\tbbpval = bbp4 & (~0x18);\n+\tbbpval = bbp4 | 0x00;\n+\trt2800_bbp_write(rt2x00dev, 4, bbpval);\n+\n+\tbbpval = rt2800_bbp_read(rt2x00dev, 21);\n+\tbbpval = bbpval | 1;\n+\trt2800_bbp_write(rt2x00dev, 21, bbpval);\n+\tbbpval = bbpval & 0xfe;\n+\trt2800_bbp_write(rt2x00dev, 21, bbpval);\n+\n+\trt2800_register_write(rt2x00dev, RF_CONTROL1, 0x00000202);\n+\trt2800_register_write(rt2x00dev, RF_BYPASS1, 0x00000303);\n+\tif (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags))\n+\t\trt2800_register_write(rt2x00dev, RF_CONTROL3, 0x0101);\n+\telse\n+\t\trt2800_register_write(rt2x00dev, RF_CONTROL3, 0x0000);\n+\n+\trt2800_register_write(rt2x00dev, RF_BYPASS3, 0xf1f1);\n+\n+\trfb0r1 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 1);\n+\trfb0r2 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 2);\n+\trfb0r42 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 42);\n+\trfb4r0 = rt2800_rfcsr_read_bank(rt2x00dev, 4, 0);\n+\trfb4r19 = rt2800_rfcsr_read_bank(rt2x00dev, 4, 19);\n+\trfb5r3 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 3);\n+\trfb5r4 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4);\n+\trfb5r17 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 17);\n+\trfb5r18 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 18);\n+\trfb5r19 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 19);\n+\trfb5r20 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 20);\n+\n+\trfb6r0 = rt2800_rfcsr_read_bank(rt2x00dev, 6, 0);\n+\trfb6r19 = rt2800_rfcsr_read_bank(rt2x00dev, 6, 19);\n+\trfb7r3 = rt2800_rfcsr_read_bank(rt2x00dev, 7, 3);\n+\trfb7r4 = rt2800_rfcsr_read_bank(rt2x00dev, 7, 4);\n+\trfb7r17 = rt2800_rfcsr_read_bank(rt2x00dev, 7, 17);\n+\trfb7r18 = rt2800_rfcsr_read_bank(rt2x00dev, 7, 18);\n+\trfb7r19 = rt2800_rfcsr_read_bank(rt2x00dev, 7, 19);\n+\trfb7r20 = rt2800_rfcsr_read_bank(rt2x00dev, 7, 20);\n+\n+\trt2800_rfcsr_write_chanreg(rt2x00dev, 0, 0x87);\n+\trt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0x27);\n+\trt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x38);\n+\trt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x38);\n+\trt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x80);\n+\trt2800_rfcsr_write_dccal(rt2x00dev, 18, 0xC1);\n+\trt2800_rfcsr_write_dccal(rt2x00dev, 19, 0x60);\n+\trt2800_rfcsr_write_dccal(rt2x00dev, 20, 0x00);\n+\n+\trt2800_bbp_write(rt2x00dev, 23, 0x0);\n+\trt2800_bbp_write(rt2x00dev, 24, 0x0);\n+\n+\trt2800_bbp_dcoc_write(rt2x00dev, 5, 0x0);\n+\n+\tbbpr241 = rt2800_bbp_read(rt2x00dev, 241);\n+\tbbpr242 = rt2800_bbp_read(rt2x00dev, 242);\n+\n+\trt2800_bbp_write(rt2x00dev, 241, 0x10);\n+\trt2800_bbp_write(rt2x00dev, 242, 0x84);\n+\trt2800_bbp_write(rt2x00dev, 244, 0x31);\n+\n+\tbbpval = rt2800_bbp_dcoc_read(rt2x00dev, 3);\n+\tbbpval = bbpval & (~0x7);\n+\trt2800_bbp_dcoc_write(rt2x00dev, 3, bbpval);\n+\n+\trt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00000004);\n+\tudelay(1);\n+\trt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00000006);\n+\tusleep_range(1, 200);\n+\trt2800_register_write(rt2x00dev, RF_BYPASS0, 0x00003376);\n+\trt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00001006);\n+\tudelay(1);\n+\tif (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {\n+\t\trt2800_bbp_write(rt2x00dev, 23, 0x06);\n+\t\trt2800_bbp_write(rt2x00dev, 24, 0x06);\n+\t} else {\n+\t\trt2800_bbp_write(rt2x00dev, 23, 0x02);\n+\t\trt2800_bbp_write(rt2x00dev, 24, 0x02);\n+\t}\n+\n+\tfor (ch_idx = 0; ch_idx < 2; ch_idx = ch_idx + 1) {\n+\t\tif (ch_idx == 0) {\n+\t\t\trfval = rfb0r1 & (~0x3);\n+\t\t\trfval = rfb0r1 | 0x1;\n+\t\t\trt2800_rfcsr_write_bank(rt2x00dev, 0, 1, rfval);\n+\t\t\trfval = rfb0r2 & (~0x33);\n+\t\t\trfval = rfb0r2 | 0x11;\n+\t\t\trt2800_rfcsr_write_bank(rt2x00dev, 0, 2, rfval);\n+\t\t\trfval = rfb0r42 & (~0x50);\n+\t\t\trfval = rfb0r42 | 0x10;\n+\t\t\trt2800_rfcsr_write_bank(rt2x00dev, 0, 42, rfval);\n+\n+\t\t\trt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00001006);\n+\t\t\tudelay(1);\n+\n+\t\t\tbbpval = bbp1 & (~ 0x18);\n+\t\t\tbbpval = bbpval | 0x00;\n+\t\t\trt2800_bbp_write(rt2x00dev, 1, bbpval);\n+\n+\t\t\trt2800_bbp_dcoc_write(rt2x00dev, 1, 0x00);\n+\t\t} else {\n+\t\t\trfval = rfb0r1 & (~0x3);\n+\t\t\trfval = rfb0r1 | 0x2;\n+\t\t\trt2800_rfcsr_write_bank(rt2x00dev, 0, 1, rfval);\n+\t\t\trfval = rfb0r2 & (~0x33);\n+\t\t\trfval = rfb0r2 | 0x22;\n+\t\t\trt2800_rfcsr_write_bank(rt2x00dev, 0, 2, rfval);\n+\t\t\trfval = rfb0r42 & (~0x50);\n+\t\t\trfval = rfb0r42 | 0x40;\n+\t\t\trt2800_rfcsr_write_bank(rt2x00dev, 0, 42, rfval);\n+\n+\t\t\trt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00002006);\n+\t\t\tudelay(1);\n+\n+\t\t\tbbpval = bbp1 & (~ 0x18);\n+\t\t\tbbpval = bbpval | 0x08;\n+\t\t\trt2800_bbp_write(rt2x00dev, 1, bbpval);\n+\n+\t\t\trt2800_bbp_dcoc_write(rt2x00dev, 1, 0x01);\n+\t\t}\n+\t\tudelay(500);\n+\n+\t\tvga_idx = 0;\n+\t\t\twhile (vga_idx < 11) {\n+\t\t\t\trt2800_rfcsr_write_dccal(rt2x00dev, 3, rf_vga_table[vga_idx]);\n+\t\t\t\trt2800_rfcsr_write_dccal(rt2x00dev, 4, rf_vga_table[vga_idx]);\n+\n+\t\t\t\trt2800_bbp_dcoc_write(rt2x00dev, 0, 0x93);\n+\n+\t\t\t\tfor (i = 0; i < 10000; i++) {\n+\t\t\t\t\tbbpval = rt2800_bbp_read(rt2x00dev, 159);\n+\t\t\t\t\tif ((bbpval & 0xff) == 0x93)\n+\t\t\t\t\t\tudelay(50);\n+\t\t\t\t\telse\n+\t\t\t\t\t\tbreak;\n+\t\t\t\t\t}\n+\n+\t\t\t\tif ((bbpval & 0xff) == 0x93) {\n+\t\t\t\t\trt2x00_warn(rt2x00dev, \"Fatal Error: Calibration doesn't finish\");\n+\t\t\t\t\tgoto restore_value;\n+\t\t\t\t}\n+\n+\t\t\t\tfor (i = 0; i < 5; i++) {\n+\t\t\t\t\tu32 bbptemp = 0;\n+\t\t\t\t\tu8 value = 0;\n+\t\t\t\t\tint result = 0;\n+\n+\t\t\t\t\trt2800_bbp_write(rt2x00dev, 158, 0x1e);\n+\t\t\t\t\trt2800_bbp_write(rt2x00dev, 159, i);\n+\t\t\t\t\trt2800_bbp_write(rt2x00dev, 158, 0x22);\n+\t\t\t\t\tvalue = rt2800_bbp_read(rt2x00dev, 159);\n+\t\t\t\t\tbbptemp = bbptemp + (value << 24);\n+\t\t\t\t\trt2800_bbp_write(rt2x00dev, 158, 0x21);\n+\t\t\t\t\tvalue = rt2800_bbp_read(rt2x00dev, 159);\n+\t\t\t\t\tbbptemp = bbptemp + (value << 16);\n+\t\t\t\t\trt2800_bbp_write(rt2x00dev, 158, 0x20);\n+\t\t\t\t\tvalue = rt2800_bbp_read(rt2x00dev, 159);\n+\t\t\t\t\tbbptemp = bbptemp + (value << 8);\n+\t\t\t\t\trt2800_bbp_write(rt2x00dev, 158, 0x1f);\n+\t\t\t\t\tvalue = rt2800_bbp_read(rt2x00dev, 159);\n+\t\t\t\t\tbbptemp = bbptemp + value;\n+\n+\t\t\t\t\tif ((i < 2) && (bbptemp & 0x800000))\n+\t\t\t\t\t\tresult = (bbptemp & 0xffffff) - 0x1000000;\n+\t\t\t\t\telse if (i == 4)\n+\t\t\t\t\t\tresult = bbptemp;\n+\t\t\t\t\telse\n+\t\t\t\t\t\tresult = bbptemp;\n+\n+\t\t\t\t\tif (i == 0)\n+\t\t\t\t\t\tmi = result/4096;\n+\t\t\t\t\telse if (i == 1)\n+\t\t\t\t\t\tmq = result/4096;\n+\t\t\t\t\telse if (i == 2)\n+\t\t\t\t\t\tsi = bbptemp/4096;\n+\t\t\t\t\telse if (i == 3)\n+\t\t\t\t\t\tsq = bbptemp/4096;\n+\t\t\t\t\telse\n+\t\t\t\t\t\triq = result/4096;\n+\t\t\t\t}\n+\n+\t\t\t\tbbpval1 = si - mi*mi;\n+\t\t\t\trt2x00_dbg(rt2x00dev, \"RXIQ si=%d, sq=%d, riq=%d, bbpval %d, vga_idx %d\", si, sq, riq, bbpval1, vga_idx);\n+\n+\t\t\t\tif (bbpval1 >= (100*100))\n+\t\t\t\t\tbreak;\n+\n+\t\t\t\tif (bbpval1 <= 100)\n+\t\t\t\t\tvga_idx = vga_idx + 9;\n+\t\t\t\telse if (bbpval1 <= 158)\n+\t\t\t\t\tvga_idx = vga_idx + 8;\n+\t\t\t\telse if (bbpval1 <= 251)\n+\t\t\t\t\tvga_idx = vga_idx + 7;\n+\t\t\t\telse if (bbpval1 <= 398)\n+\t\t\t\t\tvga_idx = vga_idx + 6;\n+\t\t\t\telse if (bbpval1 <= 630)\n+\t\t\t\t\tvga_idx = vga_idx + 5;\n+\t\t\t\telse if (bbpval1 <= 1000)\n+\t\t\t\t\tvga_idx = vga_idx + 4;\n+\t\t\t\telse if (bbpval1 <= 1584)\n+\t\t\t\t\tvga_idx = vga_idx + 3;\n+\t\t\t\telse if (bbpval1 <= 2511)\n+\t\t\t\t\tvga_idx = vga_idx + 2;\n+\t\t\t\telse\n+\t\t\t\t\tvga_idx = vga_idx + 1;\n+\t\t\t}\n+\n+\t\tsigma_i = rt2800_do_sqrt_accumulation(100*(si - mi*mi));\n+\t\tsigma_q = rt2800_do_sqrt_accumulation(100*(sq - mq*mq));\n+\t\tr_iq = 10*(riq-(mi*mq));\n+\n+\t\trt2x00_dbg(rt2x00dev, \"Sigma_i=%d, Sigma_q=%d, R_iq=%d\", sigma_i, sigma_q, r_iq);\n+\n+\t\tif (((sigma_i <= 1400 ) && (sigma_i >= 1000))\n+\t\t\t&& ((sigma_i - sigma_q) <= 112)\n+\t\t\t&& ((sigma_i - sigma_q) >= -112)\n+\t\t\t&& ((mi <= 32) && (mi >= -32))\n+\t\t\t&& ((mq <= 32) && (mq >= -32))) {\n+\t\t\t\tr_iq = 10*(riq-(mi*mq));\n+\t\t\t\trt2x00_dbg(rt2x00dev, \"RXIQ Sigma_i=%d, Sigma_q=%d, R_iq=%d\\n\", sigma_i, sigma_q, r_iq);\n+\n+\t\t\t\tg_rx = (1000 * sigma_q) / sigma_i;\n+\t\t\t\tg_imb = ((-2) * 128 * (1000 - g_rx)) / (1000 + g_rx);\n+\t\t\t\tph_rx = (r_iq * 2292) / (sigma_i * sigma_q);\n+\t\t\t\trt2x00_info(rt2x00dev, \"RXIQ G_imb=%d, Ph_rx=%d\\n\", g_imb, ph_rx);\n+\n+\t\t\t\tif ((ph_rx > 20) || (ph_rx < -20)) {\n+\t\t\t\t\tph_rx = 0;\n+\t\t\t\t\trt2x00_warn(rt2x00dev, \"RXIQ calibration FAIL\");\n+\t\t\t\t}\n+\n+\t\t\t\tif ((g_imb > 12) || (g_imb < -12)) {\n+\t\t\t\t\tg_imb = 0;\n+\t\t\t\t\trt2x00_warn(rt2x00dev, \"RXIQ calibration FAIL\");\n+\t\t\t\t}\n+\t\t\t}\n+\t\telse {\n+\t\t\tg_imb = 0;\n+\t\t\tph_rx = 0;\n+\t\t\trt2x00_dbg(rt2x00dev, \"RXIQ Sigma_i=%d, Sigma_q=%d, R_iq=%d\\n\", sigma_i, sigma_q, r_iq);\n+\t\t\trt2x00_warn(rt2x00dev, \"RXIQ calibration FAIL\");\n+\t\t}\n+\n+\t\tif (ch_idx == 0) {\n+\t\t\trt2800_bbp_write(rt2x00dev, 158, 0x37);\n+\t\t\trt2800_bbp_write(rt2x00dev, 159, g_imb & 0x3f);\n+\t\t\trt2800_bbp_write(rt2x00dev, 158, 0x35);\n+\t\t\trt2800_bbp_write(rt2x00dev, 159, ph_rx & 0x3f);\n+\t\t} else {\n+\t\t\trt2800_bbp_write(rt2x00dev, 158, 0x55);\n+\t\t\trt2800_bbp_write(rt2x00dev, 159, g_imb & 0x3f);\n+\t\t\trt2800_bbp_write(rt2x00dev, 158, 0x53);\n+\t\t\trt2800_bbp_write(rt2x00dev, 159, ph_rx & 0x3f);\n+\t\t}\n+\t}\n+\n+restore_value:\n+\trt2800_bbp_write(rt2x00dev, 158, 0x3);\n+\tbbpval = rt2800_bbp_read(rt2x00dev, 159);\n+\trt2800_bbp_write(rt2x00dev, 159, (bbpval | 0x07));\n+\n+\trt2800_bbp_write(rt2x00dev, 158, 0x00);\n+\trt2800_bbp_write(rt2x00dev, 159, 0x00);\n+\trt2800_bbp_write(rt2x00dev, 1, bbp1);\n+\trt2800_bbp_write(rt2x00dev, 4, bbp4);\n+\trt2800_bbp_write(rt2x00dev, 241, bbpr241);\n+\trt2800_bbp_write(rt2x00dev, 242, bbpr242);\n+\n+\trt2800_bbp_write(rt2x00dev, 244, 0x00);\n+\tbbpval = rt2800_bbp_read(rt2x00dev, 21);\n+\tbbpval |= 0x1;\n+\trt2800_bbp_write(rt2x00dev, 21, bbpval);\n+\tusleep_range(10, 200);\n+\tbbpval &= 0xfe;\n+\trt2800_bbp_write(rt2x00dev, 21, bbpval);\n+\n+\trt2800_rfcsr_write_bank(rt2x00dev, 0, 1, rfb0r1);\n+\trt2800_rfcsr_write_bank(rt2x00dev, 0, 2, rfb0r2);\n+\trt2800_rfcsr_write_bank(rt2x00dev, 0, 42, rfb0r42);\n+\n+\trt2800_rfcsr_write_bank(rt2x00dev, 4, 0, rfb4r0);\n+\trt2800_rfcsr_write_bank(rt2x00dev, 4, 19, rfb4r19);\n+\trt2800_rfcsr_write_bank(rt2x00dev, 5, 3, rfb5r3);\n+\trt2800_rfcsr_write_bank(rt2x00dev, 5, 4, rfb5r4);\n+\trt2800_rfcsr_write_bank(rt2x00dev, 5, 17, rfb5r17);\n+\trt2800_rfcsr_write_bank(rt2x00dev, 5, 18, rfb5r18);\n+\trt2800_rfcsr_write_bank(rt2x00dev, 5, 19, rfb5r19);\n+\trt2800_rfcsr_write_bank(rt2x00dev, 5, 20, rfb5r20);\n+\n+\trt2800_rfcsr_write_bank(rt2x00dev, 6, 0, rfb6r0);\n+\trt2800_rfcsr_write_bank(rt2x00dev, 6, 19, rfb6r19);\n+\trt2800_rfcsr_write_bank(rt2x00dev, 7, 3, rfb7r3);\n+\trt2800_rfcsr_write_bank(rt2x00dev, 7, 4, rfb7r4);\n+\trt2800_rfcsr_write_bank(rt2x00dev, 7, 17, rfb7r17);\n+\trt2800_rfcsr_write_bank(rt2x00dev, 7, 18, rfb7r18);\n+\trt2800_rfcsr_write_bank(rt2x00dev, 7, 19, rfb7r19);\n+\trt2800_rfcsr_write_bank(rt2x00dev, 7, 20, rfb7r20);\n+\n+\trt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00000006);\n+\tudelay(1);\n+\trt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00000004);\n+\tudelay(1);\n+\trt2800_register_write(rt2x00dev, RF_CONTROL0, orig_RF_CONTROL0);\n+\tudelay(1);\n+\trt2800_register_write(rt2x00dev, RF_BYPASS0, orig_RF_BYPASS0);\n+\trt2800_register_write(rt2x00dev, RF_CONTROL1, orig_RF_CONTROL1);\n+\trt2800_register_write(rt2x00dev, RF_BYPASS1, orig_RF_BYPASS1);\n+\trt2800_register_write(rt2x00dev, RF_CONTROL3, orig_RF_CONTROL3);\n+\trt2800_register_write(rt2x00dev, RF_BYPASS3, orig_RF_BYPASS3);\n+\trt2800_register_write(rt2x00dev, MAC_SYS_CTRL, savemacsysctrl);\n+}\n+\n static void rt2800_bbp_core_soft_reset(struct rt2x00_dev *rt2x00dev,\n \t\t\t\t       bool set_bw, bool is_ht40)\n {\n@@ -9313,6 +9691,7 @@ static void rt2800_init_rfcsr_6352(struc\n \trt2800_rxdcoc_calibration(rt2x00dev);\n \trt2800_bw_filter_calibration(rt2x00dev, true);\n \trt2800_bw_filter_calibration(rt2x00dev, false);\n+\trt2800_rxiq_calibration(rt2x00dev);\n }\n \n static void rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)\n"
  },
  {
    "path": "package/kernel/mac80211/patches/rt2x00/986-rt2x00-add-TX-LOFT-calibration.patch",
    "content": "--- a/drivers/net/wireless/ralink/rt2x00/rt2800lib.c\n+++ b/drivers/net/wireless/ralink/rt2x00/rt2800lib.c\n@@ -9079,6 +9079,943 @@ restore_value:\n \trt2800_register_write(rt2x00dev, MAC_SYS_CTRL, savemacsysctrl);\n }\n \n+static void rt2800_rf_configstore(struct rt2x00_dev *rt2x00dev, rf_reg_pair rf_reg_record[][13], u8 chain)\n+{\n+\tu8 rfvalue = 0;\n+\n+\tif (chain == CHAIN_0) {\n+\t\trfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 1);\n+\t\trf_reg_record[CHAIN_0][0].bank = 0;\n+\t\trf_reg_record[CHAIN_0][0].reg = 1;\n+\t\trf_reg_record[CHAIN_0][0].value = rfvalue;\n+\t\trfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 2);\n+\t\trf_reg_record[CHAIN_0][1].bank = 0;\n+\t\trf_reg_record[CHAIN_0][1].reg = 2;\n+\t\trf_reg_record[CHAIN_0][1].value = rfvalue;\n+\t\trfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 35);\n+\t\trf_reg_record[CHAIN_0][2].bank = 0;\n+\t\trf_reg_record[CHAIN_0][2].reg = 35;\n+\t\trf_reg_record[CHAIN_0][2].value = rfvalue;\n+\t\trfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 42);\n+\t\trf_reg_record[CHAIN_0][3].bank = 0;\n+\t\trf_reg_record[CHAIN_0][3].reg = 42;\n+\t\trf_reg_record[CHAIN_0][3].value = rfvalue;\n+\t\trfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 4, 0);\n+\t\trf_reg_record[CHAIN_0][4].bank = 4;\n+\t\trf_reg_record[CHAIN_0][4].reg = 0;\n+\t\trf_reg_record[CHAIN_0][4].value = rfvalue;\n+\t\trfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 4, 2);\n+\t\trf_reg_record[CHAIN_0][5].bank = 4;\n+\t\trf_reg_record[CHAIN_0][5].reg = 2;\n+\t\trf_reg_record[CHAIN_0][5].value = rfvalue;\n+\t\trfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 4, 34);\n+\t\trf_reg_record[CHAIN_0][6].bank = 4;\n+\t\trf_reg_record[CHAIN_0][6].reg = 34;\n+\t\trf_reg_record[CHAIN_0][6].value = rfvalue;\n+\t\trfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 5, 3);\n+\t\trf_reg_record[CHAIN_0][7].bank = 5;\n+\t\trf_reg_record[CHAIN_0][7].reg = 3;\n+\t\trf_reg_record[CHAIN_0][7].value = rfvalue;\n+\t\trfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4);\n+\t\trf_reg_record[CHAIN_0][8].bank = 5;\n+\t\trf_reg_record[CHAIN_0][8].reg = 4;\n+\t\trf_reg_record[CHAIN_0][8].value = rfvalue;\n+\t\trfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 5, 17);\n+\t\trf_reg_record[CHAIN_0][9].bank = 5;\n+\t\trf_reg_record[CHAIN_0][9].reg = 17;\n+\t\trf_reg_record[CHAIN_0][9].value = rfvalue;\n+\t\trfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 5, 18);\n+\t\trf_reg_record[CHAIN_0][10].bank = 5;\n+\t\trf_reg_record[CHAIN_0][10].reg = 18;\n+\t\trf_reg_record[CHAIN_0][10].value = rfvalue;\n+\t\trfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 5, 19);\n+\t\trf_reg_record[CHAIN_0][11].bank = 5;\n+\t\trf_reg_record[CHAIN_0][11].reg = 19;\n+\t\trf_reg_record[CHAIN_0][11].value = rfvalue;\n+\t\trfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 5, 20);\n+\t\trf_reg_record[CHAIN_0][12].bank = 5;\n+\t\trf_reg_record[CHAIN_0][12].reg = 20;\n+\t\trf_reg_record[CHAIN_0][12].value = rfvalue;\n+\t} else if (chain == CHAIN_1) {\n+\t\trfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 1);\n+\t\trf_reg_record[CHAIN_1][0].bank = 0;\n+\t\trf_reg_record[CHAIN_1][0].reg = 1;\n+\t\trf_reg_record[CHAIN_1][0].value = rfvalue;\n+\t\trfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 2);\n+\t\trf_reg_record[CHAIN_1][1].bank = 0;\n+\t\trf_reg_record[CHAIN_1][1].reg = 2;\n+\t\trf_reg_record[CHAIN_1][1].value = rfvalue;\n+\t\trfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 35);\n+\t\trf_reg_record[CHAIN_1][2].bank = 0;\n+\t\trf_reg_record[CHAIN_1][2].reg = 35;\n+\t\trf_reg_record[CHAIN_1][2].value = rfvalue;\n+\t\trfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 42);\n+\t\trf_reg_record[CHAIN_1][3].bank = 0;\n+\t\trf_reg_record[CHAIN_1][3].reg = 42;\n+\t\trf_reg_record[CHAIN_1][3].value = rfvalue;\n+\t\trfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 6, 0);\n+\t\trf_reg_record[CHAIN_1][4].bank = 6;\n+\t\trf_reg_record[CHAIN_1][4].reg = 0;\n+\t\trf_reg_record[CHAIN_1][4].value = rfvalue;\n+\t\trfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 6, 2);\n+\t\trf_reg_record[CHAIN_1][5].bank = 6;\n+\t\trf_reg_record[CHAIN_1][5].reg = 2;\n+\t\trf_reg_record[CHAIN_1][5].value = rfvalue;\n+\t\trfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 6, 34);\n+\t\trf_reg_record[CHAIN_1][6].bank = 6;\n+\t\trf_reg_record[CHAIN_1][6].reg = 34;\n+\t\trf_reg_record[CHAIN_1][6].value = rfvalue;\n+\t\trfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 7, 3);\n+\t\trf_reg_record[CHAIN_1][7].bank = 7;\n+\t\trf_reg_record[CHAIN_1][7].reg = 3;\n+\t\trf_reg_record[CHAIN_1][7].value = rfvalue;\n+\t\trfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 7, 4);\n+\t\trf_reg_record[CHAIN_1][8].bank = 7;\n+\t\trf_reg_record[CHAIN_1][8].reg = 4;\n+\t\trf_reg_record[CHAIN_1][8].value = rfvalue;\n+\t\trfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 7, 17);\n+\t\trf_reg_record[CHAIN_1][9].bank = 7;\n+\t\trf_reg_record[CHAIN_1][9].reg = 17;\n+\t\trf_reg_record[CHAIN_1][9].value = rfvalue;\n+\t\trfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 7, 18);\n+\t\trf_reg_record[CHAIN_1][10].bank = 7;\n+\t\trf_reg_record[CHAIN_1][10].reg = 18;\n+\t\trf_reg_record[CHAIN_1][10].value = rfvalue;\n+\t\trfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 7, 19);\n+\t\trf_reg_record[CHAIN_1][11].bank = 7;\n+\t\trf_reg_record[CHAIN_1][11].reg = 19;\n+\t\trf_reg_record[CHAIN_1][11].value = rfvalue;\n+\t\trfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 7, 20);\n+\t\trf_reg_record[CHAIN_1][12].bank = 7;\n+\t\trf_reg_record[CHAIN_1][12].reg = 20;\n+\t\trf_reg_record[CHAIN_1][12].value = rfvalue;\n+\t} else {\n+\t\trt2x00_warn(rt2x00dev, \"Unknown chain = %u\\n\", chain);\n+\t\treturn;\n+\t}\n+\n+\treturn;\n+}\n+\n+static void rt2800_rf_configrecover(struct rt2x00_dev *rt2x00dev, rf_reg_pair rf_record[][13])\n+{\n+\tu8 chain_index = 0, record_index = 0;\n+\tu8 bank = 0, rf_register = 0, value = 0;\n+\n+\tfor (chain_index = 0; chain_index < 2; chain_index++) {\n+\t\tfor (record_index = 0; record_index < 13; record_index++) {\n+\t\t\tbank = rf_record[chain_index][record_index].bank;\n+\t\t\trf_register = rf_record[chain_index][record_index].reg;\n+\t\t\tvalue = rf_record[chain_index][record_index].value;\n+\t\t\trt2800_rfcsr_write_bank(rt2x00dev, bank, rf_register, value);\n+\t\t\trt2x00_dbg(rt2x00dev, \"bank: %d, rf_register: %d, value: %x\\n\", bank, rf_register, value);\n+\t\t}\n+\t}\n+\n+\treturn;\n+}\n+\n+static void rt2800_setbbptonegenerator(struct rt2x00_dev *rt2x00dev)\n+{\n+\trt2800_bbp_write(rt2x00dev, 158, 0xAA);\n+\trt2800_bbp_write(rt2x00dev, 159, 0x00);\n+\n+\trt2800_bbp_write(rt2x00dev, 158, 0xAB);\n+\trt2800_bbp_write(rt2x00dev, 159, 0x0A);\n+\n+\trt2800_bbp_write(rt2x00dev, 158, 0xAC);\n+\trt2800_bbp_write(rt2x00dev, 159, 0x3F);\n+\n+\trt2800_bbp_write(rt2x00dev, 158, 0xAD);\n+\trt2800_bbp_write(rt2x00dev, 159, 0x3F);\n+\n+\trt2800_bbp_write(rt2x00dev, 244, 0x40);\n+\n+\treturn;\n+}\n+\n+static u32 rt2800_do_fft_accumulation(struct rt2x00_dev *rt2x00dev, u8 tidx, u8 read_neg)\n+{\n+\tu32 macvalue = 0;\n+\tint fftout_i = 0, fftout_q = 0;\n+\tu32 ptmp=0, pint = 0;\n+\tu8 bbp = 0;\n+\tu8 tidxi;\n+\n+\trt2800_bbp_write(rt2x00dev, 158, 0x00);\n+\trt2800_bbp_write(rt2x00dev, 159, 0x9b);\n+\n+\tbbp = 0x9b;\n+\n+\twhile (bbp == 0x9b) {\n+\t\tudelay(10);\n+\t\tbbp = rt2800_bbp_read(rt2x00dev, 159);\n+\t\tbbp = bbp & 0xff;\n+\t}\n+\n+\trt2800_bbp_write(rt2x00dev, 158, 0xba);\n+\trt2800_bbp_write(rt2x00dev, 159, tidx);\n+\trt2800_bbp_write(rt2x00dev, 159, tidx);\n+\trt2800_bbp_write(rt2x00dev, 159, tidx);\n+\n+\tmacvalue = rt2800_register_read(rt2x00dev, 0x057C);\n+\n+\tfftout_i = (macvalue >> 16);\n+\tfftout_i = (fftout_i & 0x8000) ? (fftout_i - 0x10000) : fftout_i;\n+\tfftout_q = (macvalue & 0xffff);\n+\tfftout_q = (fftout_q & 0x8000) ? (fftout_q - 0x10000) : fftout_q;\n+\tptmp = (fftout_i * fftout_i);\n+\tptmp = ptmp + (fftout_q * fftout_q);\n+\tpint = ptmp;\n+\trt2x00_dbg(rt2x00dev, \"I = %d,  Q = %d, power = %x\\n\", fftout_i, fftout_q, pint);\n+\tif (read_neg) {\n+\t\tpint = pint >> 1;\n+\t\ttidxi = 0x40 - tidx;\n+\t\ttidxi = tidxi & 0x3f;\n+\n+\t\trt2800_bbp_write(rt2x00dev, 158, 0xba);\n+\t\trt2800_bbp_write(rt2x00dev, 159, tidxi);\n+\t\trt2800_bbp_write(rt2x00dev, 159, tidxi);\n+\t\trt2800_bbp_write(rt2x00dev, 159, tidxi);\n+\n+\t\tmacvalue = rt2800_register_read(rt2x00dev, 0x057C);\n+\n+\t\tfftout_i = (macvalue >> 16);\n+\t\tfftout_i = (fftout_i & 0x8000) ? (fftout_i - 0x10000) : fftout_i;\n+\t\tfftout_q = (macvalue & 0xffff);\n+\t\tfftout_q = (fftout_q & 0x8000) ? (fftout_q - 0x10000) : fftout_q;\n+\t\tptmp = (fftout_i * fftout_i);\n+\t\tptmp = ptmp + (fftout_q * fftout_q);\n+\t\tptmp = ptmp >> 1;\n+\t\tpint = pint + ptmp;\n+\t}\n+\n+\treturn pint;\n+}\n+\n+static u32 rt2800_read_fft_accumulation(struct rt2x00_dev *rt2x00dev, u8 tidx) {\n+\tu32 macvalue = 0;\n+\tint fftout_i = 0, fftout_q = 0;\n+\tu32 ptmp=0, pint = 0;\n+\n+\trt2800_bbp_write(rt2x00dev, 158, 0xBA);\n+\trt2800_bbp_write(rt2x00dev, 159, tidx);\n+\trt2800_bbp_write(rt2x00dev, 159, tidx);\n+\trt2800_bbp_write(rt2x00dev, 159, tidx);\n+\n+\tmacvalue = rt2800_register_read(rt2x00dev, 0x057C);\n+\n+\tfftout_i = (macvalue >> 16);\n+\tfftout_i = (fftout_i & 0x8000) ? (fftout_i - 0x10000) : fftout_i;\n+\tfftout_q = (macvalue & 0xffff);\n+\tfftout_q = (fftout_q & 0x8000) ? (fftout_q - 0x10000) : fftout_q;\n+\tptmp = (fftout_i * fftout_i);\n+\tptmp = ptmp + (fftout_q * fftout_q);\n+\tpint = ptmp;\n+\trt2x00_info(rt2x00dev, \"I = %d,  Q = %d, power = %x\\n\", fftout_i, fftout_q, pint);\n+\n+\treturn pint;\n+}\n+\n+static void rt2800_write_dc(struct rt2x00_dev *rt2x00dev, u8 ch_idx, u8 alc, u8 iorq, u8 dc)\n+{\n+\tu8 bbp = 0;\n+\n+\trt2800_bbp_write(rt2x00dev, 158, 0xb0);\n+\tbbp = alc | 0x80;\n+\trt2800_bbp_write(rt2x00dev, 159, bbp);\n+\n+\tif (ch_idx == 0)\n+\t\tbbp = (iorq == 0) ? 0xb1: 0xb2;\n+\telse\n+\t\tbbp = (iorq == 0) ? 0xb8: 0xb9;\n+\n+\trt2800_bbp_write(rt2x00dev, 158, bbp);\n+\tbbp = dc;\n+\trt2800_bbp_write(rt2x00dev, 159, bbp);\n+\n+\treturn;\n+}\n+\n+static void rt2800_loft_search(struct rt2x00_dev *rt2x00dev, u8 ch_idx, u8 alc_idx, u8 dc_result[][RF_ALC_NUM][2])\n+{\n+\tu32 p0 = 0, p1 = 0, pf = 0;\n+\tchar idx0 = 0, idx1 = 0;\n+\tu8 idxf[] = {0x00, 0x00};\n+\tu8 ibit = 0x20;\n+\tu8 iorq;\n+\tchar bidx;\n+\n+\trt2800_bbp_write(rt2x00dev, 158, 0xb0);\n+\trt2800_bbp_write(rt2x00dev, 159, 0x80);\n+\n+\tfor (bidx = 5; bidx >= 0; bidx--) {\n+\t\tfor (iorq = 0; iorq <= 1; iorq++) {\n+\t\t\trt2x00_dbg(rt2x00dev, \"\\n========================================================\\n\");\n+\n+\t\t\tif (idxf[iorq] == 0x20) {\n+\t\t\t\tidx0 = 0x20;\n+\t\t\t\tp0 = pf;\n+\t\t\t} else {\n+\t\t\t\tidx0 = idxf[iorq] - ibit;\n+\t\t\t\tidx0 = idx0 & 0x3F;\n+\t\t\t\trt2800_write_dc(rt2x00dev, ch_idx, 0, iorq, idx0);\n+\t\t\t\tp0 = rt2800_do_fft_accumulation(rt2x00dev, 0x0A, 0);\n+\t\t\t}\n+\n+\t\t\tidx1 = idxf[iorq] + ((bidx == 5) ? 0 : ibit);\n+\t\t\tidx1 = idx1 & 0x3F;\n+\t\t\trt2800_write_dc(rt2x00dev, ch_idx, 0, iorq, idx1);\n+\t\t\tp1 = rt2800_do_fft_accumulation(rt2x00dev, 0x0A, 0);\n+\n+\t\t\trt2x00_dbg(rt2x00dev, \"alc=%u, IorQ=%u, idx_final=%2x\\n\", alc_idx, iorq, idxf[iorq]);\n+\t\t\trt2x00_dbg(rt2x00dev, \"p0=%x, p1=%x, pf=%x, idx_0=%x, idx_1=%x, ibit=%x !\\n\", p0, p1, pf, idx0, idx1, ibit);\n+\n+\t\t\tif ((bidx != 5) && (pf <= p0) && (pf < p1)) {\n+\t\t\t\tpf = pf;\n+\t\t\t\tidxf[iorq] = idxf[iorq];\n+\t\t\t} else if (p0 < p1) {\n+\t\t\t\tpf = p0;\n+\t\t\t\tidxf[iorq] = idx0 & 0x3F;\n+\t\t\t} else {\n+\t\t\t\tpf = p1;\n+\t\t\t\tidxf[iorq] = idx1 & 0x3F;\n+\t\t\t}\n+\t\t\trt2x00_dbg(rt2x00dev, \"IorQ=%u, idx_final[%u]:%x, pf:%8x\\n\", iorq, iorq, idxf[iorq], pf);\n+\n+\t\t\trt2800_write_dc(rt2x00dev, ch_idx, 0, iorq, idxf[iorq]);\n+\n+\t\t}\n+\t\tibit = ibit >> 1;\n+\t}\n+\tdc_result[ch_idx][alc_idx][0] = idxf[0];\n+\tdc_result[ch_idx][alc_idx][1] = idxf[1];\n+\n+\treturn;\n+}\n+\n+static void rt2800_iq_search(struct rt2x00_dev *rt2x00dev, u8 ch_idx, u8 *ges, u8 *pes)\n+{\n+\tu32 p0 = 0, p1 = 0, pf = 0;\n+\tchar perr = 0, gerr = 0, iq_err = 0;\n+\tchar pef = 0, gef = 0;\n+\tchar psta, pend;\n+\tchar gsta, gend;\n+\n+\tu8 ibit = 0x20;\n+\tu8 first_search = 0x00, touch_neg_max = 0x00;\n+\tchar idx0 = 0, idx1 = 0;\n+\tu8 gop;\n+\tu8 bbp = 0;\n+\tchar bidx;\n+\n+\trt2x00_info(rt2x00dev, \"IQCalibration Start!\\n\");\n+\tfor (bidx = 5; bidx >= 1; bidx--) {\n+\t\tfor (gop = 0; gop < 2; gop++) {\n+\t\t\trt2x00_dbg(rt2x00dev, \"\\n========================================================\\n\");\n+\n+\t\t\tif ((gop == 1) || (bidx < 4)) {\n+\t\t\t\tif (gop == 0)\n+\t\t\t\t\tiq_err = gerr;\n+\t\t\t\telse\n+\t\t\t\t\tiq_err = perr;\n+\n+\t\t\t\tfirst_search = (gop == 0) ? (bidx == 3) : (bidx == 5);\n+\t\t\t\ttouch_neg_max = (gop) ? ((iq_err & 0x0F) == 0x08) : ((iq_err & 0x3F) == 0x20);\n+\n+\t\t\t\tif (touch_neg_max) {\n+\t\t\t\t\tp0 = pf;\n+\t\t\t\t\tidx0 = iq_err;\n+\t\t\t\t} else {\n+\t\t\t\t\tidx0 = iq_err - ibit;\n+\t\t\t\t\tbbp = (ch_idx == 0) ? ((gop == 0) ? 0x28 : 0x29): ((gop == 0) ? 0x46 : 0x47);\n+\n+\t\t\t\t\trt2800_bbp_write(rt2x00dev, 158, bbp);\n+\t\t\t\t\trt2800_bbp_write(rt2x00dev, 159, idx0);\n+\n+\t\t\t\t\tp0 = rt2800_do_fft_accumulation(rt2x00dev, 0x14, 1);\n+\t\t\t\t}\n+\n+\t\t\t\tidx1 = iq_err + (first_search ? 0 : ibit);\n+\t\t\t\tidx1 = (gop == 0) ? (idx1 & 0x0F) : (idx1 & 0x3F);\n+\n+\t\t\t\tbbp = (ch_idx == 0) ? (gop == 0) ? 0x28 : 0x29 : (gop == 0) ? 0x46 : 0x47;\n+\n+\t\t\t\trt2800_bbp_write(rt2x00dev, 158, bbp);\n+\t\t\t\trt2800_bbp_write(rt2x00dev, 159, idx1);\n+\n+\t\t\t\tp1 = rt2800_do_fft_accumulation(rt2x00dev, 0x14, 1);\n+\n+\t\t\t\trt2x00_dbg(rt2x00dev, \"p0=%x, p1=%x, pwer_final=%x, idx0=%x, idx1=%x, iq_err=%x, gop=%d, ibit=%x !\\n\", p0, p1, pf, idx0, idx1, iq_err, gop, ibit);\n+\n+\t\t\t\tif ((!first_search) && (pf <= p0) && (pf < p1)) {\n+\t\t\t\t\tpf = pf;\n+\t\t\t\t} else if (p0 < p1) {\n+\t\t\t\t\tpf = p0;\n+\t\t\t\t\tiq_err = idx0;\n+\t\t\t\t} else {\n+\t\t\t\t\tpf = p1;\n+\t\t\t\t\tiq_err = idx1;\n+\t\t\t\t}\n+\n+\t\t\t\tbbp = (ch_idx == 0) ? (gop == 0) ? 0x28 : 0x29 : (gop == 0) ? 0x46 : 0x47;\n+\n+\t\t\t\trt2800_bbp_write(rt2x00dev, 158, bbp);\n+\t\t\t\trt2800_bbp_write(rt2x00dev, 159, iq_err);\n+\n+\t\t\t\tif (gop == 0)\n+\t\t\t\t\tgerr = iq_err;\n+\t\t\t\telse\n+\t\t\t\t\tperr = iq_err;\n+\n+\t\t\t\trt2x00_dbg(rt2x00dev, \"IQCalibration pf=%8x (%2x, %2x) !\\n\", pf, gerr & 0x0F, perr & 0x3F);\n+\n+\t\t\t}\n+\t\t}\n+\n+\t\tif (bidx > 0)\n+\t\t\tibit = (ibit >> 1);\n+\t}\n+\tgerr = (gerr & 0x08) ? (gerr & 0x0F) - 0x10 : (gerr & 0x0F);\n+\tperr = (perr & 0x20) ? (perr & 0x3F) - 0x40 : (perr & 0x3F);\n+\n+\tgerr = (gerr < -0x07) ? -0x07 : (gerr > 0x05) ? 0x05 : gerr;\n+\tgsta = gerr - 1;\n+\tgend = gerr + 2;\n+\n+\tperr = (perr < -0x1f) ? -0x1f : (perr > 0x1d) ? 0x1d : perr;\n+\tpsta = perr - 1;\n+\tpend = perr + 2;\n+\n+\tfor (gef = gsta; gef <= gend; gef = gef + 1)\n+\t\tfor (pef = psta; pef <= pend; pef = pef + 1) {\n+\t\t\tbbp = (ch_idx == 0) ? 0x28 : 0x46;\n+\t\t\trt2800_bbp_write(rt2x00dev, 158, bbp);\n+\t\t\trt2800_bbp_write(rt2x00dev, 159, gef & 0x0F);\n+\n+\t\t\tbbp = (ch_idx == 0) ? 0x29 : 0x47;\n+\t\t\trt2800_bbp_write(rt2x00dev, 158, bbp);\n+\t\t\trt2800_bbp_write(rt2x00dev, 159, pef & 0x3F);\n+\n+\t\t\tp1 = rt2800_do_fft_accumulation(rt2x00dev, 0x14, 1);\n+\t\t\tif ((gef == gsta) && (pef == psta)) {\n+\t\t\t\tpf = p1;\n+\t\t\t\tgerr = gef;\n+\t\t\t\tperr = pef;\n+\t\t\t}\n+\t\t\telse if (pf > p1){\n+\t\t\t\tpf = p1;\n+\t\t\t\tgerr = gef;\n+\t\t\t\tperr = pef;\n+\t\t\t}\n+\t\t\trt2x00_dbg(rt2x00dev, \"Fine IQCalibration p1=%8x pf=%8x (%2x, %2x) !\\n\", p1, pf, gef & 0x0F, pef & 0x3F);\n+\t\t}\n+\n+\tges[ch_idx] = gerr & 0x0F;\n+\tpes[ch_idx] = perr & 0x3F;\n+\n+\trt2x00_info(rt2x00dev, \"IQCalibration Done! CH = %u, (gain=%2x, phase=%2x)\\n\", ch_idx, gerr & 0x0F, perr & 0x3F);\n+\n+\treturn;\n+}\n+\n+static void rt2800_rf_aux_tx0_loopback(struct rt2x00_dev *rt2x00dev)\n+{\n+\trt2800_rfcsr_write_bank(rt2x00dev, 0, 1, 0x21);\n+\trt2800_rfcsr_write_bank(rt2x00dev, 0, 2, 0x10);\n+\trt2800_rfcsr_write_bank(rt2x00dev, 0, 35, 0x00);\n+\trt2800_rfcsr_write_bank(rt2x00dev, 0, 42, 0x1b);\n+\trt2800_rfcsr_write_bank(rt2x00dev, 4, 0, 0x81);\n+\trt2800_rfcsr_write_bank(rt2x00dev, 4, 2, 0x81);\n+\trt2800_rfcsr_write_bank(rt2x00dev, 4, 34, 0xee);\n+\trt2800_rfcsr_write_bank(rt2x00dev, 5, 3, 0x2d);\n+\trt2800_rfcsr_write_bank(rt2x00dev, 5, 4, 0x2d);\n+\trt2800_rfcsr_write_bank(rt2x00dev, 5, 17, 0x80);\n+\trt2800_rfcsr_write_bank(rt2x00dev, 5, 18, 0xd7);\n+\trt2800_rfcsr_write_bank(rt2x00dev, 5, 19, 0xa2);\n+\trt2800_rfcsr_write_bank(rt2x00dev, 5, 20, 0x20);\n+}\n+\n+static void rt2800_rf_aux_tx1_loopback(struct rt2x00_dev *rt2x00dev)\n+{\n+\trt2800_rfcsr_write_bank(rt2x00dev, 0, 1, 0x22);\n+\trt2800_rfcsr_write_bank(rt2x00dev, 0, 2, 0x20);\n+\trt2800_rfcsr_write_bank(rt2x00dev, 0, 35, 0x00);\n+\trt2800_rfcsr_write_bank(rt2x00dev, 0, 42, 0x4b);\n+\trt2800_rfcsr_write_bank(rt2x00dev, 6, 0, 0x81);\n+\trt2800_rfcsr_write_bank(rt2x00dev, 6, 2, 0x81);\n+\trt2800_rfcsr_write_bank(rt2x00dev, 6, 34, 0xee);\n+\trt2800_rfcsr_write_bank(rt2x00dev, 7, 3, 0x2d);\n+\trt2800_rfcsr_write_bank(rt2x00dev, 7, 4, 0x2d);\n+\trt2800_rfcsr_write_bank(rt2x00dev, 7, 17, 0x80);\n+\trt2800_rfcsr_write_bank(rt2x00dev, 7, 18, 0xd7);\n+\trt2800_rfcsr_write_bank(rt2x00dev, 7, 19, 0xa2);\n+\trt2800_rfcsr_write_bank(rt2x00dev, 7, 20, 0x20);\n+}\n+\n+void rt2800_loft_iq_calibration(struct rt2x00_dev *rt2x00dev)\n+{\n+\trf_reg_pair rf_store[CHAIN_NUM][13];\n+\tu32 macorg1 = 0;\n+\tu32 macorg2 = 0;\n+\tu32 macorg3 = 0;\n+\tu32 macorg4 = 0;\n+\tu32 macorg5 = 0;\n+\tu32 orig528 = 0;\n+\tu32 orig52c = 0;\n+\n+\tu32 savemacsysctrl = 0, mtxcycle = 0;\n+\tu32 macvalue = 0;\n+\tu32 mac13b8 = 0;\n+\tu32 p0 = 0, p1 = 0;\n+\tu32 p0_idx10 = 0, p1_idx10 = 0;\n+\n+\tu8 rfvalue;\n+\tu8 loft_dc_search_result[CHAIN_NUM][RF_ALC_NUM][2];\n+\tu8 ger[CHAIN_NUM], per[CHAIN_NUM];\n+\tu8 rf_gain[] = {0x00, 0x01, 0x02, 0x04, 0x08, 0x0c};\n+\tu8 rfvga_gain_table[] = {0x24, 0x25, 0x26, 0x27, 0x28, 0x2c, 0x2d, 0x2e, 0x2f, 0x30, 0x31, 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3F};\n+\n+\tu8 vga_gain[] = {14, 14};\n+\tu8 bbp_2324gain[] = {0x16, 0x14, 0x12, 0x10, 0x0c, 0x08};\n+\tu8 bbp = 0, ch_idx = 0, rf_alc_idx = 0, idx = 0;\n+\tu8 bbpr30, rfb0r39, rfb0r42;\n+\tu8 bbpr1;\n+\tu8 bbpr4;\n+\tu8 bbpr241, bbpr242;\n+\tu8 count_step;\n+\n+\tsavemacsysctrl = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);\n+\tmacorg1 = rt2800_register_read(rt2x00dev, TX_PIN_CFG);\n+\tmacorg2 = rt2800_register_read(rt2x00dev, RF_CONTROL0);\n+\tmacorg3 = rt2800_register_read(rt2x00dev, RF_BYPASS0);\n+\tmacorg4 = rt2800_register_read(rt2x00dev, RF_CONTROL3);\n+\tmacorg5 = rt2800_register_read(rt2x00dev, RF_BYPASS3);\n+\tmac13b8 = rt2800_register_read(rt2x00dev, 0x13b8);\n+\torig528 = rt2800_register_read(rt2x00dev, RF_CONTROL2);\n+\torig52c = rt2800_register_read(rt2x00dev, RF_BYPASS2);\n+\n+\tmacvalue = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);\n+\tmacvalue &= (~0x04);\n+\trt2800_register_write(rt2x00dev, MAC_SYS_CTRL, macvalue);\n+\n+\tfor (mtxcycle = 0; mtxcycle < 10000; mtxcycle++) {\n+\t\tmacvalue = rt2800_register_read(rt2x00dev, MAC_STATUS_CFG);\n+\t\tif (macvalue & 0x01)\n+\t\t\tudelay(50);\n+\t\telse\n+\t\t\tbreak;\n+\t}\n+\n+\tmacvalue = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);\n+\tmacvalue &= (~0x08);\n+\trt2800_register_write(rt2x00dev, MAC_SYS_CTRL, macvalue);\n+\n+\tfor (mtxcycle = 0; mtxcycle < 10000; mtxcycle++) {\n+\t\tmacvalue = rt2800_register_read(rt2x00dev, MAC_STATUS_CFG);\n+\t\tif (macvalue & 0x02)\n+\t\t\tudelay(50);\n+\t\telse\n+\t\t\tbreak;\n+\t}\n+\n+\tfor (ch_idx = 0; ch_idx < 2; ch_idx++) {\n+\t\trt2800_rf_configstore(rt2x00dev, rf_store, ch_idx);\n+\t}\n+\n+\tbbpr30 = rt2800_bbp_read(rt2x00dev, 30);\n+\trfb0r39 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 39);\n+\trfb0r42 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 42);\n+\n+\trt2800_bbp_write(rt2x00dev, 30, 0x1F);\n+\trt2800_rfcsr_write_bank(rt2x00dev, 0, 39, 0x80);\n+\trt2800_rfcsr_write_bank(rt2x00dev, 0, 42, 0x5B);\n+\n+\trt2800_bbp_write(rt2x00dev, 23, 0x00);\n+\trt2800_bbp_write(rt2x00dev, 24, 0x00);\n+\n+\trt2800_setbbptonegenerator(rt2x00dev);\n+\n+\tfor (ch_idx = 0; ch_idx < 2; ch_idx ++) {\n+\t\trt2800_bbp_write(rt2x00dev, 23, 0x00);\n+\t\trt2800_bbp_write(rt2x00dev, 24, 0x00);\n+\t\trt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00);\n+\t\trt2800_register_write(rt2x00dev, TX_PIN_CFG, 0x0000000F);\n+\t\trt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00000004);\n+\t\trt2800_register_write(rt2x00dev, RF_BYPASS0, 0x00003306);\n+\t\trt2800_register_write(rt2x00dev, 0x13b8, 0x10);\n+\t\tudelay(1);\n+\n+\t\tif (ch_idx == 0) {\n+\t\t\trt2800_rf_aux_tx0_loopback(rt2x00dev);\n+\t\t} else {\n+\t\t\trt2800_rf_aux_tx1_loopback(rt2x00dev);\n+\t\t}\n+\t\tudelay(1);\n+\n+\t\tif (ch_idx == 0) {\n+\t\t\trt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00001004);\n+\t\t} else {\n+\t\t\trt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00002004);\n+\t\t}\n+\n+\t\trt2800_bbp_write(rt2x00dev, 158, 0x05);\n+\t\trt2800_bbp_write(rt2x00dev, 159, 0x00);\n+\n+\t\trt2800_bbp_write(rt2x00dev, 158, 0x01);\n+\t\tif (ch_idx == 0)\n+\t\t\trt2800_bbp_write(rt2x00dev, 159, 0x00);\n+\t\telse\n+\t\t\trt2800_bbp_write(rt2x00dev, 159, 0x01);\n+\n+\t\tvga_gain[ch_idx] = 18;\n+\t\tfor (rf_alc_idx = 0; rf_alc_idx < 3; rf_alc_idx++) {\n+\t\t\trt2800_bbp_write(rt2x00dev, 23, bbp_2324gain[rf_alc_idx]);\n+\t\t\trt2800_bbp_write(rt2x00dev, 24, bbp_2324gain[rf_alc_idx]);\n+\n+\t\t\tmacvalue = rt2800_register_read(rt2x00dev, RF_CONTROL3);\n+\t\t\tmacvalue &= (~0x0000F1F1);\n+\t\t\tmacvalue |= (rf_gain[rf_alc_idx] << 4);\n+\t\t\tmacvalue |= (rf_gain[rf_alc_idx] << 12);\n+\t\t\trt2800_register_write(rt2x00dev, RF_CONTROL3, macvalue);\n+\t\t\tmacvalue = (0x0000F1F1);\n+\t\t\trt2800_register_write(rt2x00dev, RF_BYPASS3, macvalue);\n+\n+\t\t\tif (rf_alc_idx == 0) {\n+\t\t\t\trt2800_write_dc(rt2x00dev, ch_idx, 0, 1, 0x21);\n+\t\t\t\tfor (;vga_gain[ch_idx] > 0;vga_gain[ch_idx] = vga_gain[ch_idx] - 2) {\n+\t\t\t\t\trfvalue = rfvga_gain_table[vga_gain[ch_idx]];\n+\t\t\t\t\trt2800_rfcsr_write_dccal(rt2x00dev, 3, rfvalue);\n+\t\t\t\t\trt2800_rfcsr_write_dccal(rt2x00dev, 4, rfvalue);\n+\t\t\t\t\trt2800_write_dc(rt2x00dev, ch_idx, 0, 1, 0x00);\n+\t\t\t\t\trt2800_write_dc(rt2x00dev, ch_idx, 0, 0, 0x00);\n+\t\t\t\t\tp0 = rt2800_do_fft_accumulation(rt2x00dev, 0x0A, 0);\n+\t\t\t\t\trt2800_write_dc(rt2x00dev, ch_idx, 0, 0, 0x21);\n+\t\t\t\t\tp1 = rt2800_do_fft_accumulation(rt2x00dev, 0x0A, 0);\n+\t\t\t\t\trt2x00_dbg(rt2x00dev, \"LOFT AGC %d %d\\n\", p0, p1);\n+\t\t\t\t\tif ((p0 < 7000*7000) && (p1 < (7000*7000))) {\n+\t\t\t\t\t\tbreak;\n+\t\t\t\t\t}\n+\t\t\t\t}\n+\n+\t\t\t\trt2800_write_dc(rt2x00dev, ch_idx, 0, 0, 0x00);\n+\t\t\t\trt2800_write_dc(rt2x00dev, ch_idx, 0, 1, 0x00);\n+\n+\t\t\t\trt2x00_dbg(rt2x00dev, \"Used VGA %d %x\\n\",vga_gain[ch_idx], rfvga_gain_table[vga_gain[ch_idx]]);\n+\n+\t\t\t\tif (vga_gain[ch_idx] < 0)\n+\t\t\t\t\tvga_gain[ch_idx] = 0;\n+\t\t \t}\n+\n+\t\t\trfvalue = rfvga_gain_table[vga_gain[ch_idx]];\n+\n+\t\t\trt2800_rfcsr_write_dccal(rt2x00dev, 3, rfvalue);\n+\t\t\trt2800_rfcsr_write_dccal(rt2x00dev, 4, rfvalue);\n+\n+\t\t\trt2800_loft_search(rt2x00dev, ch_idx, rf_alc_idx, loft_dc_search_result);\n+\t\t}\n+\t}\n+\n+\tfor (rf_alc_idx = 0; rf_alc_idx < 3; rf_alc_idx++) {\n+\t\tfor (idx = 0; idx < 4; idx++) {\n+\t\t\trt2800_bbp_write(rt2x00dev, 158, 0xB0);\n+\t\t\tbbp = (idx<<2) + rf_alc_idx;\n+\t\t\trt2800_bbp_write(rt2x00dev, 159, bbp);\n+\t\t\trt2x00_dbg(rt2x00dev, \" ALC %2x,\", bbp);\n+\n+\t\t\trt2800_bbp_write(rt2x00dev, 158, 0xb1);\n+\t\t\tbbp = loft_dc_search_result[CHAIN_0][rf_alc_idx][0x00];\n+\t\t\tbbp = bbp & 0x3F;\n+\t\t\trt2800_bbp_write(rt2x00dev, 159, bbp);\n+\t\t\trt2x00_dbg(rt2x00dev, \" I0 %2x,\", bbp);\n+\n+\t\t\trt2800_bbp_write(rt2x00dev, 158, 0xb2);\n+\t\t\tbbp = loft_dc_search_result[CHAIN_0][rf_alc_idx][0x01];\n+\t\t\tbbp = bbp & 0x3F;\n+\t\t\trt2800_bbp_write(rt2x00dev, 159, bbp);\n+\t\t\trt2x00_dbg(rt2x00dev, \" Q0 %2x,\", bbp);\n+\n+\t\t\trt2800_bbp_write(rt2x00dev, 158, 0xb8);\n+\t\t\tbbp = loft_dc_search_result[CHAIN_1][rf_alc_idx][0x00];\n+\t\t\tbbp = bbp & 0x3F;\n+\t\t\trt2800_bbp_write(rt2x00dev, 159, bbp);\n+\t\t\trt2x00_dbg(rt2x00dev, \" I1 %2x,\", bbp);\n+\n+\t\t\trt2800_bbp_write(rt2x00dev, 158, 0xb9);\n+\t\t\tbbp = loft_dc_search_result[CHAIN_1][rf_alc_idx][0x01];\n+\t\t\tbbp = bbp & 0x3F;\n+\t\t\trt2800_bbp_write(rt2x00dev, 159, bbp);\n+\t\t\trt2x00_dbg(rt2x00dev, \" Q1 %2x\\n\", bbp);\n+\t\t}\n+\t}\n+\n+\trt2800_bbp_write(rt2x00dev, 23, 0x00);\n+\trt2800_bbp_write(rt2x00dev, 24, 0x00);\n+\n+\trt2800_register_write(rt2x00dev, RF_CONTROL0, 0x04);\n+\n+\trt2800_bbp_write(rt2x00dev, 158, 0x00);\n+\trt2800_bbp_write(rt2x00dev, 159, 0x00);\n+\n+\tbbp = 0x00;\n+\trt2800_bbp_write(rt2x00dev, 244, 0x00);\n+\n+\trt2800_bbp_write(rt2x00dev, 21, 0x01);\n+\tudelay(1);\n+\trt2800_bbp_write(rt2x00dev, 21, 0x00);\n+\n+\trt2800_rf_configrecover(rt2x00dev, rf_store);\n+\n+\trt2800_register_write(rt2x00dev, TX_PIN_CFG, macorg1);\n+\trt2800_register_write(rt2x00dev, RF_CONTROL0, 0x04);\n+\trt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00);\n+\trt2800_register_write(rt2x00dev, RF_BYPASS0, 0x00);\n+\trt2800_register_write(rt2x00dev, RF_CONTROL0, macorg2);\n+\tudelay(1);\n+\trt2800_register_write(rt2x00dev, RF_BYPASS0, macorg3);\n+\trt2800_register_write(rt2x00dev, RF_CONTROL3, macorg4);\n+\trt2800_register_write(rt2x00dev, RF_BYPASS3, macorg5);\n+\trt2800_register_write(rt2x00dev, MAC_SYS_CTRL, savemacsysctrl);\n+\trt2800_register_write(rt2x00dev, RF_CONTROL2, orig528);\n+\trt2800_register_write(rt2x00dev, RF_BYPASS2, orig52c);\n+\trt2800_register_write(rt2x00dev, 0x13b8, mac13b8);\n+\n+\trt2x00_info(rt2x00dev, \"LOFT Calibration Done!\\n\");\n+\n+\tsavemacsysctrl = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);\n+\tmacorg1 = rt2800_register_read(rt2x00dev, TX_PIN_CFG);\n+\tmacorg2 = rt2800_register_read(rt2x00dev, RF_CONTROL0);\n+\tmacorg3 = rt2800_register_read(rt2x00dev, RF_BYPASS0);\n+\tmacorg4 = rt2800_register_read(rt2x00dev, RF_CONTROL3);\n+\tmacorg5 = rt2800_register_read(rt2x00dev, RF_BYPASS3);\n+\n+\tbbpr1 = rt2800_bbp_read(rt2x00dev, 1);\n+\tbbpr4 = rt2800_bbp_read(rt2x00dev, 4);\n+\tbbpr241 = rt2800_bbp_read(rt2x00dev, 241);\n+\tbbpr242 = rt2800_bbp_read(rt2x00dev, 242);\n+\tmac13b8 = rt2800_register_read(rt2x00dev, 0x13b8);\n+\n+\tmacvalue = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);\n+\tmacvalue &= (~0x04);\n+\trt2800_register_write(rt2x00dev, MAC_SYS_CTRL, macvalue);\n+\tfor (mtxcycle = 0; mtxcycle < 10000; mtxcycle++) {\n+\t\tmacvalue = rt2800_register_read(rt2x00dev, MAC_STATUS_CFG);\n+\t\tif (macvalue & 0x01)\n+\t\t\tudelay(50);\n+\t\telse\n+\t\t\tbreak;\n+\t}\n+\n+\tmacvalue = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);\n+\tmacvalue &= (~0x08);\n+\trt2800_register_write(rt2x00dev, MAC_SYS_CTRL, macvalue);\n+\tfor (mtxcycle = 0; mtxcycle < 10000; mtxcycle++) {\n+\t\tmacvalue = rt2800_register_read(rt2x00dev, MAC_STATUS_CFG);\n+\t\tif (macvalue & 0x02)\n+\t\t\tudelay(50);\n+\t\telse\n+\t\t\tbreak;\n+\t}\n+\n+\tif (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {\n+\t\trt2800_register_write(rt2x00dev, RF_CONTROL3, 0x00000101);\n+\t\trt2800_register_write(rt2x00dev, RF_BYPASS3, 0x0000F1F1);\n+\t}\n+\n+\trt2800_bbp_write(rt2x00dev, 23, 0x00);\n+\trt2800_bbp_write(rt2x00dev, 24, 0x00);\n+\n+\tif (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {\n+\t\trt2800_bbp_write(rt2x00dev, 4, bbpr4 & (~0x18));\n+\t\trt2800_bbp_write(rt2x00dev, 21, 0x01);\n+\t\tudelay(1);\n+\t\trt2800_bbp_write(rt2x00dev, 21, 0x00);\n+\n+\t\trt2800_bbp_write(rt2x00dev, 241, 0x14);\n+\t\trt2800_bbp_write(rt2x00dev, 242, 0x80);\n+\t\trt2800_bbp_write(rt2x00dev, 244, 0x31);\n+\t} else {\n+\t\trt2800_setbbptonegenerator(rt2x00dev);\n+\t}\n+\n+\trt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00000004);\n+\trt2800_register_write(rt2x00dev, RF_BYPASS0, 0x00003306);\n+\tudelay(1);\n+\n+\trt2800_register_write(rt2x00dev, TX_PIN_CFG, 0x0000000F);\n+\n+\tif (!test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {\n+\t\trt2800_register_write(rt2x00dev, RF_CONTROL3, 0x00000000);\n+\t\trt2800_register_write(rt2x00dev, RF_BYPASS3, 0x0000F1F1);\n+\t}\n+\n+\trt2800_register_write(rt2x00dev, 0x13b8, 0x00000010);\n+\n+\tfor (ch_idx = 0; ch_idx < 2; ch_idx++) {\n+\t\trt2800_rf_configstore(rt2x00dev, rf_store, ch_idx);\n+\t}\n+\n+\trt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x3B);\n+\trt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x3B);\n+\n+\trt2800_bbp_write(rt2x00dev, 158, 0x03);\n+\trt2800_bbp_write(rt2x00dev, 159, 0x60);\n+\trt2800_bbp_write(rt2x00dev, 158, 0xB0);\n+\trt2800_bbp_write(rt2x00dev, 159, 0x80);\n+\n+\tfor (ch_idx = 0; ch_idx < 2; ch_idx ++) {\n+\t\trt2800_bbp_write(rt2x00dev, 23, 0x00);\n+\t\trt2800_bbp_write(rt2x00dev, 24, 0x00);\n+\n+\t\tif (ch_idx == 0) {\n+\t\t\trt2800_bbp_write(rt2x00dev, 158, 0x01);\n+\t\t\trt2800_bbp_write(rt2x00dev, 159, 0x00);\n+\t\t\tif (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {\n+\t\t\t\tbbp = bbpr1 & (~0x18);\n+\t\t\t\tbbp = bbp | 0x00;\n+\t\t\t\trt2800_bbp_write(rt2x00dev, 1, bbp);\n+\t\t\t}\n+\t\t\trt2800_rf_aux_tx0_loopback(rt2x00dev);\n+\t\t\trt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00001004);\n+\t\t} else {\n+\t\t\trt2800_bbp_write(rt2x00dev, 158, 0x01);\n+\t\t\trt2800_bbp_write(rt2x00dev, 159, 0x01);\n+\t\t\tif (test_bit(CAPABILITY_EXTERNAL_PA_TX1, &rt2x00dev->cap_flags)) {\n+\t\t\t\tbbp = bbpr1 & (~0x18);\n+\t\t\t\tbbp = bbp | 0x08;\n+\t\t\t\trt2800_bbp_write(rt2x00dev, 1, bbp);\n+\t\t\t}\n+\t\t\trt2800_rf_aux_tx1_loopback(rt2x00dev);\n+\t\t\trt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00002004);\n+\t\t}\n+\n+\t\trt2800_bbp_write(rt2x00dev, 158, 0x05);\n+\t\trt2800_bbp_write(rt2x00dev, 159, 0x04);\n+\n+\t\tbbp = (ch_idx == 0) ? 0x28 : 0x46;\n+\t\trt2800_bbp_write(rt2x00dev, 158, bbp);\n+\t\trt2800_bbp_write(rt2x00dev, 159, 0x00);\n+\n+\t\tif (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {\n+\t\t\trt2800_bbp_write(rt2x00dev, 23, 0x06);\n+\t\t\trt2800_bbp_write(rt2x00dev, 24, 0x06);\n+\t\t\tcount_step = 1;\n+\t\t} else {\n+\t\t\trt2800_bbp_write(rt2x00dev, 23, 0x1F);\n+\t\t\trt2800_bbp_write(rt2x00dev, 24, 0x1F);\n+\t\t\tcount_step = 2;\n+\t\t}\n+\n+\t\tfor (;vga_gain[ch_idx] < 19; vga_gain[ch_idx]=(vga_gain[ch_idx] + count_step)) {\n+\t\t\trfvalue = rfvga_gain_table[vga_gain[ch_idx]];\n+\t\t\trt2800_rfcsr_write_dccal(rt2x00dev, 3, rfvalue);\n+\t\t\trt2800_rfcsr_write_dccal(rt2x00dev, 4, rfvalue);\n+\n+\t\t\tbbp = (ch_idx == 0) ? 0x29 : 0x47;\n+\t\t\trt2800_bbp_write(rt2x00dev, 158, bbp);\n+\t\t\trt2800_bbp_write(rt2x00dev, 159, 0x00);\n+\t\t\tp0 = rt2800_do_fft_accumulation(rt2x00dev, 0x14, 0);\n+\t\t\tif (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {\n+\t\t\t\tp0_idx10 = rt2800_read_fft_accumulation(rt2x00dev, 0x0A);\n+\t\t\t}\n+\n+\t\t\tbbp = (ch_idx == 0) ? 0x29 : 0x47;\n+\t\t\trt2800_bbp_write(rt2x00dev, 158, bbp);\n+\t\t\trt2800_bbp_write(rt2x00dev, 159, 0x21);\n+\t\t\tp1 = rt2800_do_fft_accumulation(rt2x00dev, 0x14, 0);\n+\t\t\tif (test_bit(CAPABILITY_EXTERNAL_PA_TX1, &rt2x00dev->cap_flags)) {\n+\t\t\t\tp1_idx10 = rt2800_read_fft_accumulation(rt2x00dev, 0x0A);\n+\t\t\t}\n+\n+\t\t\trt2x00_dbg(rt2x00dev, \"IQ AGC %d %d\\n\", p0, p1);\n+\n+\t\t\tif (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {\n+\t\t\t\trt2x00_dbg(rt2x00dev, \"IQ AGC IDX 10 %d %d\\n\", p0_idx10, p1_idx10);\n+\t\t\t\tif ((p0_idx10 > 7000*7000) || (p1_idx10 > 7000*7000)) {\n+\t\t\t\t\tif (vga_gain[ch_idx]!=0)\n+\t\t\t\t\t\tvga_gain[ch_idx] = vga_gain[ch_idx]-1;\n+\t\t\t\t\tbreak;\n+\t\t\t\t}\n+\t\t\t}\n+\n+\t\t\tif ((p0 > 2500*2500) || (p1 > 2500*2500)) {\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t}\n+\n+\t\tif (vga_gain[ch_idx] > 18)\n+\t\t\tvga_gain[ch_idx] = 18;\n+\t\trt2x00_dbg(rt2x00dev, \"Used VGA %d %x\\n\",vga_gain[ch_idx], rfvga_gain_table[vga_gain[ch_idx]]);\n+\n+\t\tbbp = (ch_idx == 0) ? 0x29 : 0x47;\n+\t\trt2800_bbp_write(rt2x00dev, 158, bbp);\n+\t\trt2800_bbp_write(rt2x00dev, 159, 0x00);\n+\n+\t\trt2800_iq_search(rt2x00dev, ch_idx, ger, per);\n+\t}\n+\n+\trt2800_bbp_write(rt2x00dev, 23, 0x00);\n+\trt2800_bbp_write(rt2x00dev, 24, 0x00);\n+\trt2800_register_write(rt2x00dev, RF_CONTROL0, 0x04);\n+\n+\trt2800_bbp_write(rt2x00dev, 158, 0x28);\n+\tbbp = ger[CHAIN_0] & 0x0F;\n+\trt2800_bbp_write(rt2x00dev, 159, bbp);\n+\n+\trt2800_bbp_write(rt2x00dev, 158, 0x29);\n+\tbbp = per[CHAIN_0] & 0x3F;\n+\trt2800_bbp_write(rt2x00dev, 159, bbp);\n+\n+\trt2800_bbp_write(rt2x00dev, 158, 0x46);\n+\tbbp = ger[CHAIN_1] & 0x0F;\n+\trt2800_bbp_write(rt2x00dev, 159, bbp);\n+\n+\trt2800_bbp_write(rt2x00dev, 158, 0x47);\n+\tbbp = per[CHAIN_1] & 0x3F;\n+\trt2800_bbp_write(rt2x00dev, 159, bbp);\n+\n+\tif (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {\n+\t\trt2800_bbp_write(rt2x00dev, 1, bbpr1);\n+\t\trt2800_bbp_write(rt2x00dev, 241, bbpr241);\n+\t\trt2800_bbp_write(rt2x00dev, 242, bbpr242);\n+\t}\n+\trt2800_bbp_write(rt2x00dev, 244, 0x00);\n+\n+\trt2800_bbp_write(rt2x00dev, 158, 0x00);\n+\trt2800_bbp_write(rt2x00dev, 159, 0x00);\n+\trt2800_bbp_write(rt2x00dev, 158, 0xB0);\n+\trt2800_bbp_write(rt2x00dev, 159, 0x00);\n+\n+\trt2800_bbp_write(rt2x00dev, 30, bbpr30);\n+\trt2800_rfcsr_write_bank(rt2x00dev, 0, 39, rfb0r39);\n+\trt2800_rfcsr_write_bank(rt2x00dev, 0, 42, rfb0r42);\n+\n+\tif (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {\n+\t\trt2800_bbp_write(rt2x00dev, 4, bbpr4);\n+\t}\n+\n+\trt2800_bbp_write(rt2x00dev, 21, 0x01);\n+\tudelay(1);\n+\trt2800_bbp_write(rt2x00dev, 21, 0x00);\n+\n+\trt2800_rf_configrecover(rt2x00dev, rf_store);\n+\n+\trt2800_register_write(rt2x00dev, TX_PIN_CFG, macorg1);\n+\trt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00);\n+\trt2800_register_write(rt2x00dev, RF_BYPASS0, 0x00);\n+\trt2800_register_write(rt2x00dev, RF_CONTROL0, macorg2);\n+\tudelay(1);\n+\trt2800_register_write(rt2x00dev, RF_BYPASS0, macorg3);\n+\trt2800_register_write(rt2x00dev, RF_CONTROL3, macorg4);\n+\trt2800_register_write(rt2x00dev, RF_BYPASS3, macorg5);\n+\trt2800_register_write(rt2x00dev, MAC_SYS_CTRL, savemacsysctrl);\n+\trt2800_register_write(rt2x00dev, 0x13b8, mac13b8);\n+\n+\trt2x00_info(rt2x00dev, \"TX IQ Calibration Done!\\n\");\n+\n+\treturn;\n+}\n+\n static void rt2800_bbp_core_soft_reset(struct rt2x00_dev *rt2x00dev,\n \t\t\t\t       bool set_bw, bool is_ht40)\n {\n@@ -9691,6 +10628,7 @@ static void rt2800_init_rfcsr_6352(struc\n \trt2800_rxdcoc_calibration(rt2x00dev);\n \trt2800_bw_filter_calibration(rt2x00dev, true);\n \trt2800_bw_filter_calibration(rt2x00dev, false);\n+\trt2800_loft_iq_calibration(rt2x00dev);\n \trt2800_rxiq_calibration(rt2x00dev);\n }\n \n--- a/drivers/net/wireless/ralink/rt2x00/rt2800lib.h\n+++ b/drivers/net/wireless/ralink/rt2x00/rt2800lib.h\n@@ -17,6 +17,16 @@\n #define WCID_START\t33\n #define WCID_END\t222\n #define STA_IDS_SIZE\t(WCID_END - WCID_START + 2)\n+#define CHAIN_0\t\t0x0\n+#define CHAIN_1\t\t0x1\n+#define RF_ALC_NUM\t6\n+#define CHAIN_NUM\t2\n+\n+typedef struct rf_reg_pair {\n+\tu8 bank;\n+\tu8 reg;\n+\tu8 value;\n+} rf_reg_pair;\n \n /* RT2800 driver data structure */\n struct rt2800_drv_data {\n"
  },
  {
    "path": "package/kernel/mac80211/patches/rt2x00/990-rt2x00-mt7620-introduce-accessors-for-CHIP_VER-register.patch",
    "content": "--- a/drivers/net/wireless/ralink/rt2x00/rt2800lib.h\n+++ b/drivers/net/wireless/ralink/rt2x00/rt2800lib.h\n@@ -78,6 +78,9 @@ struct rt2800_ops {\n \tint (*drv_init_registers)(struct rt2x00_dev *rt2x00dev);\n \t__le32 *(*drv_get_txwi)(struct queue_entry *entry);\n \tunsigned int (*drv_get_dma_done)(struct data_queue *queue);\n+\tint (*hw_get_chippkg)(void);\n+\tint (*hw_get_chipver)(void);\n+\tint (*hw_get_chipeco)(void);\n };\n \n static inline u32 rt2800_register_read(struct rt2x00_dev *rt2x00dev,\n@@ -195,6 +198,27 @@ static inline unsigned int rt2800_drv_ge\n \treturn rt2800ops->drv_get_dma_done(queue);\n }\n \n+static inline int rt2800_hw_get_chippkg(struct rt2x00_dev *rt2x00dev)\n+{\n+\tconst struct rt2800_ops *rt2800ops = rt2x00dev->ops->drv;\n+\n+\treturn rt2800ops->hw_get_chippkg();\n+}\n+\n+static inline int rt2800_hw_get_chipver(struct rt2x00_dev *rt2x00dev)\n+{\n+\tconst struct rt2800_ops *rt2800ops = rt2x00dev->ops->drv;\n+\n+\treturn rt2800ops->hw_get_chipver();\n+}\n+\n+static inline int rt2800_hw_get_chipeco(struct rt2x00_dev *rt2x00dev)\n+{\n+\tconst struct rt2800_ops *rt2800ops = rt2x00dev->ops->drv;\n+\n+\treturn rt2800ops->hw_get_chipeco();\n+}\n+\n void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,\n \t\t\tconst u8 command, const u8 token,\n \t\t\tconst u8 arg0, const u8 arg1);\n--- a/drivers/net/wireless/ralink/rt2x00/rt2800pci.c\n+++ b/drivers/net/wireless/ralink/rt2x00/rt2800pci.c\n@@ -286,6 +286,10 @@ static int rt2800pci_read_eeprom(struct\n \treturn retval;\n }\n \n+static int rt2800pci_get_chippkg(void) { return 0; }\n+static int rt2800pci_get_chipver(void) { return 0; }\n+static int rt2800pci_get_chipeco(void) { return 0; }\n+\n static const struct ieee80211_ops rt2800pci_mac80211_ops = {\n \t.tx\t\t\t= rt2x00mac_tx,\n \t.start\t\t\t= rt2x00mac_start,\n@@ -328,6 +332,9 @@ static const struct rt2800_ops rt2800pci\n \t.drv_init_registers\t= rt2800mmio_init_registers,\n \t.drv_get_txwi\t\t= rt2800mmio_get_txwi,\n \t.drv_get_dma_done\t= rt2800mmio_get_dma_done,\n+\t.hw_get_chippkg\t\t= rt2800pci_get_chippkg,\n+\t.hw_get_chipver\t\t= rt2800pci_get_chipver,\n+\t.hw_get_chipeco\t\t= rt2800pci_get_chipeco,\n };\n \n static const struct rt2x00lib_ops rt2800pci_rt2x00_ops = {\n--- a/drivers/net/wireless/ralink/rt2x00/rt2800soc.c\n+++ b/drivers/net/wireless/ralink/rt2x00/rt2800soc.c\n@@ -27,6 +27,12 @@\n #include \"rt2800lib.h\"\n #include \"rt2800mmio.h\"\n \n+/* Needed to probe CHIP_VER register on MT7620 */\n+#ifdef CONFIG_SOC_MT7620\n+#include <asm/mach-ralink/ralink_regs.h>\n+#include <asm/mach-ralink/mt7620.h>\n+#endif\n+\n /* Allow hardware encryption to be disabled. */\n static bool modparam_nohwcrypt;\n module_param_named(nohwcrypt, modparam_nohwcrypt, bool, 0444);\n@@ -118,6 +124,27 @@ static int rt2800soc_write_firmware(stru\n \treturn 0;\n }\n \n+#ifdef CONFIG_SOC_MT7620\n+static int rt2800soc_get_chippkg(void)\n+{\n+\treturn mt7620_get_pkg();\n+}\n+\n+static int rt2800soc_get_chipver(void)\n+{\n+\treturn mt7620_get_chipver();\n+}\n+\n+static int rt2800soc_get_chipeco(void)\n+{\n+\treturn mt7620_get_eco();\n+}\n+#else\n+static int rt2800soc_get_chippkg(void) { return 0; }\n+static int rt2800soc_get_chipver(void) { return 0; }\n+static int rt2800soc_get_chipeco(void) { return 0; }\n+#endif\n+\n static const struct ieee80211_ops rt2800soc_mac80211_ops = {\n \t.tx\t\t\t= rt2x00mac_tx,\n \t.start\t\t\t= rt2x00mac_start,\n@@ -159,6 +186,9 @@ static const struct rt2800_ops rt2800soc\n \t.drv_init_registers\t= rt2800mmio_init_registers,\n \t.drv_get_txwi\t\t= rt2800mmio_get_txwi,\n \t.drv_get_dma_done\t= rt2800mmio_get_dma_done,\n+\t.hw_get_chippkg\t\t= rt2800soc_get_chippkg,\n+\t.hw_get_chipver\t\t= rt2800soc_get_chipver,\n+\t.hw_get_chipeco\t\t= rt2800soc_get_chipeco,\n };\n \n static const struct rt2x00lib_ops rt2800soc_rt2x00_ops = {\n--- a/drivers/net/wireless/ralink/rt2x00/rt2800usb.c\n+++ b/drivers/net/wireless/ralink/rt2x00/rt2800usb.c\n@@ -628,6 +628,10 @@ static int rt2800usb_probe_hw(struct rt2\n \treturn 0;\n }\n \n+static int rt2800usb_get_chippkg(void) { return 0; }\n+static int rt2800usb_get_chipver(void) { return 0; }\n+static int rt2800usb_get_chipeco(void) { return 0; }\n+\n static const struct ieee80211_ops rt2800usb_mac80211_ops = {\n \t.tx\t\t\t= rt2x00mac_tx,\n \t.start\t\t\t= rt2x00mac_start,\n@@ -671,6 +675,9 @@ static const struct rt2800_ops rt2800usb\n \t.drv_init_registers\t= rt2800usb_init_registers,\n \t.drv_get_txwi\t\t= rt2800usb_get_txwi,\n \t.drv_get_dma_done\t= rt2800usb_get_dma_done,\n+\t.hw_get_chippkg\t\t= rt2800usb_get_chippkg,\n+\t.hw_get_chipver\t\t= rt2800usb_get_chipver,\n+\t.hw_get_chipeco\t\t= rt2800usb_get_chipeco,\n };\n \n static const struct rt2x00lib_ops rt2800usb_rt2x00_ops = {\n"
  },
  {
    "path": "package/kernel/mac80211/patches/rt2x00/991-rt2x00-mt7620-differentiate-based-on-SoC-CHIP_VER.patch",
    "content": "--- a/drivers/net/wireless/ralink/rt2x00/rt2800.h\n+++ b/drivers/net/wireless/ralink/rt2x00/rt2800.h\n@@ -1042,6 +1042,11 @@\n #define MIMO_PS_CFG_RX_STBY_POL\t\tFIELD32(0x00000010)\n #define MIMO_PS_CFG_RX_RX_STBY0\t\tFIELD32(0x00000020)\n \n+#define BB_PA_MODE_CFG0\t\t\t0x1214\n+#define BB_PA_MODE_CFG1\t\t\t0x1218\n+#define RF_PA_MODE_CFG0\t\t\t0x121C\n+#define RF_PA_MODE_CFG1\t\t\t0x1220\n+\n /*\n  * EDCA_AC0_CFG:\n  */\n--- a/drivers/net/wireless/ralink/rt2x00/rt2800lib.c\n+++ b/drivers/net/wireless/ralink/rt2x00/rt2800lib.c\n@@ -3698,14 +3698,16 @@ static void rt2800_config_channel_rf7620\n \trt2x00_set_field8(&rfcsr, RFCSR19_K, rf->rf4);\n \trt2800_rfcsr_write(rt2x00dev, 19, rfcsr);\n \n-\t/* Default: XO=20MHz , SDM mode */\n-\trfcsr = rt2800_rfcsr_read(rt2x00dev, 16);\n-\trt2x00_set_field8(&rfcsr, RFCSR16_SDM_MODE_MT7620, 0x80);\n-\trt2800_rfcsr_write(rt2x00dev, 16, rfcsr);\n-\n-\trfcsr = rt2800_rfcsr_read(rt2x00dev, 21);\n-\trt2x00_set_field8(&rfcsr, RFCSR21_BIT8, 1);\n-\trt2800_rfcsr_write(rt2x00dev, 21, rfcsr);\n+\tif (rt2800_hw_get_chipver(rt2x00dev) > 1) {\n+\t\t/* Default: XO=20MHz , SDM mode */\n+\t\trfcsr = rt2800_rfcsr_read(rt2x00dev, 16);\n+\t\trt2x00_set_field8(&rfcsr, RFCSR16_SDM_MODE_MT7620, 0x80);\n+\t\trt2800_rfcsr_write(rt2x00dev, 16, rfcsr);\n+\n+\t\trfcsr = rt2800_rfcsr_read(rt2x00dev, 21);\n+\t\trt2x00_set_field8(&rfcsr, RFCSR21_BIT8, 1);\n+\t\trt2800_rfcsr_write(rt2x00dev, 21, rfcsr);\n+\t}\n \n \trfcsr = rt2800_rfcsr_read(rt2x00dev, 1);\n \trt2x00_set_field8(&rfcsr, RFCSR1_TX2_EN_MT7620,\n@@ -3739,18 +3741,23 @@ static void rt2800_config_channel_rf7620\n \t\trt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x20);\n \t}\n \n-\tif (conf_is_ht40(conf)) {\n-\t\trt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x08);\n-\t\trt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x08);\n-\t} else {\n-\t\trt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x28);\n-\t\trt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x28);\n+\tif (rt2800_hw_get_chipver(rt2x00dev) > 1) {\n+\t\tif (conf_is_ht40(conf)) {\n+\t\t\trt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x08);\n+\t\t\trt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x08);\n+\t\t} else {\n+\t\t\trt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x28);\n+\t\t\trt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x28);\n+\t\t}\n \t}\n \n-\trfcsr = rt2800_rfcsr_read(rt2x00dev, 28);\n-\trt2x00_set_field8(&rfcsr, RFCSR28_CH11_HT40,\n-\t\t\t  conf_is_ht40(conf) && (rf->channel == 11));\n-\trt2800_rfcsr_write(rt2x00dev, 28, rfcsr);\n+\tif (rt2800_hw_get_chipver(rt2x00dev) > 1 &&\n+\t    rt2800_hw_get_chipeco(rt2x00dev) == 2) {\n+\t\trfcsr = rt2800_rfcsr_read(rt2x00dev, 28);\n+\t\trt2x00_set_field8(&rfcsr, RFCSR28_CH11_HT40,\n+\t\t\t\t  conf_is_ht40(conf) && (rf->channel == 11));\n+\t\trt2800_rfcsr_write(rt2x00dev, 28, rfcsr);\n+\t}\n \n \tif (!test_bit(DEVICE_STATE_SCANNING, &rt2x00dev->flags)) {\n \t\tif (conf_is_ht40(conf)) {\n@@ -3850,25 +3857,29 @@ static void rt2800_config_alc(struct rt2\n \tif (i == 10000)\n \t\trt2x00_warn(rt2x00dev, \"Wait MAC Status to MAX !!!\\n\");\n \n-\tif (chan->center_freq > 2457) {\n-\t\tbbp = rt2800_bbp_read(rt2x00dev, 30);\n-\t\tbbp = 0x40;\n-\t\trt2800_bbp_write(rt2x00dev, 30, bbp);\n-\t\trt2800_rfcsr_write(rt2x00dev, 39, 0);\n-\t\tif (rt2x00_has_cap_external_lna_bg(rt2x00dev))\n-\t\t\trt2800_rfcsr_write(rt2x00dev, 42, 0xfb);\n-\t\telse\n-\t\t\trt2800_rfcsr_write(rt2x00dev, 42, 0x7b);\n-\t} else {\n-\t\tbbp = rt2800_bbp_read(rt2x00dev, 30);\n-\t\tbbp = 0x1f;\n-\t\trt2800_bbp_write(rt2x00dev, 30, bbp);\n-\t\trt2800_rfcsr_write(rt2x00dev, 39, 0x80);\n-\t\tif (rt2x00_has_cap_external_lna_bg(rt2x00dev))\n-\t\t\trt2800_rfcsr_write(rt2x00dev, 42, 0xdb);\n-\t\telse\n-\t\t\trt2800_rfcsr_write(rt2x00dev, 42, 0x5b);\n+\tif (rt2800_hw_get_chipver(rt2x00dev) > 1 &&\n+\t    rt2800_hw_get_chipeco(rt2x00dev) >= 2) {\n+\t\tif (chan->center_freq > 2457) {\n+\t\t\tbbp = rt2800_bbp_read(rt2x00dev, 30);\n+\t\t\tbbp = 0x40;\n+\t\t\trt2800_bbp_write(rt2x00dev, 30, bbp);\n+\t\t\trt2800_rfcsr_write(rt2x00dev, 39, 0);\n+\t\t\tif (rt2x00_has_cap_external_lna_bg(rt2x00dev))\n+\t\t\t\trt2800_rfcsr_write(rt2x00dev, 42, 0xfb);\n+\t\t\telse\n+\t\t\t\trt2800_rfcsr_write(rt2x00dev, 42, 0x7b);\n+\t\t} else {\n+\t\t\tbbp = rt2800_bbp_read(rt2x00dev, 30);\n+\t\t\tbbp = 0x1f;\n+\t\t\trt2800_bbp_write(rt2x00dev, 30, bbp);\n+\t\t\trt2800_rfcsr_write(rt2x00dev, 39, 0x80);\n+\t\t\tif (rt2x00_has_cap_external_lna_bg(rt2x00dev))\n+\t\t\t\trt2800_rfcsr_write(rt2x00dev, 42, 0xdb);\n+\t\t\telse\n+\t\t\t\trt2800_rfcsr_write(rt2x00dev, 42, 0x5b);\n+\t\t}\n \t}\n+\n \trt2800_register_write(rt2x00dev, MAC_SYS_CTRL, mac_sys_ctrl);\n \n \trt2800_vco_calibration(rt2x00dev);\n@@ -5906,18 +5917,33 @@ static int rt2800_init_registers(struct\n \t} else if (rt2x00_rt(rt2x00dev, RT5350)) {\n \t\trt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);\n \t} else if (rt2x00_rt(rt2x00dev, RT6352)) {\n-\t\trt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000401);\n-\t\trt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x000C0000);\n-\t\trt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);\n-\t\trt2800_register_write(rt2x00dev, TX_ALC_VGA3, 0x00000000);\n-\t\trt2800_register_write(rt2x00dev, TX0_BB_GAIN_ATTEN, 0x0);\n-\t\trt2800_register_write(rt2x00dev, TX1_BB_GAIN_ATTEN, 0x0);\n-\t\trt2800_register_write(rt2x00dev, TX0_RF_GAIN_ATTEN, 0x6C6C666C);\n-\t\trt2800_register_write(rt2x00dev, TX1_RF_GAIN_ATTEN, 0x6C6C666C);\n-\t\trt2800_register_write(rt2x00dev, TX0_RF_GAIN_CORRECT,\n-\t\t\t\t      0x3630363A);\n-\t\trt2800_register_write(rt2x00dev, TX1_RF_GAIN_CORRECT,\n-\t\t\t\t      0x3630363A);\n+\t\tif (rt2800_hw_get_chipver(rt2x00dev) <= 1) {\n+\t\t\trt2800_register_write(rt2x00dev, TX_ALC_VGA3,\n+\t\t\t\t\t      0x00000000);\n+\t\t\trt2800_register_write(rt2x00dev, BB_PA_MODE_CFG0,\n+\t\t\t\t\t      0x000055FF);\n+\t\t\trt2800_register_write(rt2x00dev, BB_PA_MODE_CFG1,\n+\t\t\t\t\t      0x00550055);\n+\t\t\trt2800_register_write(rt2x00dev, RF_PA_MODE_CFG0,\n+\t\t\t\t\t      0x000055FF);\n+\t\t\trt2800_register_write(rt2x00dev, RF_PA_MODE_CFG1,\n+\t\t\t\t\t      0x00550055);\n+\t\t} else {\n+\t\t\trt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000401);\n+\t\t\trt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x000C0000);\n+\t\t\trt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);\n+\t\t\trt2800_register_write(rt2x00dev, TX_ALC_VGA3, 0x00000000);\n+\t\t\trt2800_register_write(rt2x00dev, TX0_BB_GAIN_ATTEN, 0x0);\n+\t\t\trt2800_register_write(rt2x00dev, TX1_BB_GAIN_ATTEN, 0x0);\n+\t\t\trt2800_register_write(rt2x00dev, TX0_RF_GAIN_ATTEN,\n+\t\t\t\t\t      0x6C6C666C);\n+\t\t\trt2800_register_write(rt2x00dev, TX1_RF_GAIN_ATTEN,\n+\t\t\t\t\t      0x6C6C666C);\n+\t\t\trt2800_register_write(rt2x00dev, TX0_RF_GAIN_CORRECT,\n+\t\t\t\t\t      0x3630363A);\n+\t\t\trt2800_register_write(rt2x00dev, TX1_RF_GAIN_CORRECT,\n+\t\t\t\t\t      0x3630363A);\n+\t\t}\n \t\treg = rt2800_register_read(rt2x00dev, TX_ALC_CFG_1);\n \t\trt2x00_set_field32(&reg, TX_ALC_CFG_1_ROS_BUSY_EN, 0);\n \t\trt2800_register_write(rt2x00dev, TX_ALC_CFG_1, reg);\n@@ -7061,14 +7087,16 @@ static void rt2800_init_bbp_6352(struct\n \trt2800_bbp_write(rt2x00dev, 188, 0x00);\n \trt2800_bbp_write(rt2x00dev, 189, 0x00);\n \n-\trt2800_bbp_write(rt2x00dev, 91, 0x06);\n-\trt2800_bbp_write(rt2x00dev, 92, 0x04);\n-\trt2800_bbp_write(rt2x00dev, 93, 0x54);\n-\trt2800_bbp_write(rt2x00dev, 99, 0x50);\n-\trt2800_bbp_write(rt2x00dev, 148, 0x84);\n-\trt2800_bbp_write(rt2x00dev, 167, 0x80);\n-\trt2800_bbp_write(rt2x00dev, 178, 0xFF);\n-\trt2800_bbp_write(rt2x00dev, 106, 0x13);\n+\tif (rt2800_hw_get_chipver(rt2x00dev) > 1) {\n+\t\trt2800_bbp_write(rt2x00dev, 91, 0x06);\n+\t\trt2800_bbp_write(rt2x00dev, 92, 0x04);\n+\t\trt2800_bbp_write(rt2x00dev, 93, 0x54);\n+\t\trt2800_bbp_write(rt2x00dev, 99, 0x50);\n+\t\trt2800_bbp_write(rt2x00dev, 148, 0x84);\n+\t\trt2800_bbp_write(rt2x00dev, 167, 0x80);\n+\t\trt2800_bbp_write(rt2x00dev, 178, 0xFF);\n+\t\trt2800_bbp_write(rt2x00dev, 106, 0x13);\n+\t}\n \n \t/* BBP for G band GLRT function (BBP_128 ~ BBP_221) */\n \trt2800_bbp_glrt_write(rt2x00dev, 0, 0x00);\n@@ -10407,31 +10435,36 @@ static void rt2800_init_rfcsr_6352(struc\n \trt2800_rfcsr_write(rt2x00dev, 42, 0x5B);\n \trt2800_rfcsr_write(rt2x00dev, 43, 0x00);\n \n-\trt2800_rfcsr_write(rt2x00dev, 11, 0x21);\n-\tif (rt2800_clk_is_20mhz(rt2x00dev))\n-\t\trt2800_rfcsr_write(rt2x00dev, 13, 0x03);\n-\telse\n-\t\trt2800_rfcsr_write(rt2x00dev, 13, 0x00);\n-\trt2800_rfcsr_write(rt2x00dev, 14, 0x7C);\n-\trt2800_rfcsr_write(rt2x00dev, 16, 0x80);\n-\trt2800_rfcsr_write(rt2x00dev, 17, 0x99);\n-\trt2800_rfcsr_write(rt2x00dev, 18, 0x99);\n-\trt2800_rfcsr_write(rt2x00dev, 19, 0x09);\n-\trt2800_rfcsr_write(rt2x00dev, 20, 0x50);\n-\trt2800_rfcsr_write(rt2x00dev, 21, 0xB0);\n-\trt2800_rfcsr_write(rt2x00dev, 22, 0x00);\n-\trt2800_rfcsr_write(rt2x00dev, 23, 0x06);\n-\trt2800_rfcsr_write(rt2x00dev, 24, 0x00);\n-\trt2800_rfcsr_write(rt2x00dev, 25, 0x00);\n-\trt2800_rfcsr_write(rt2x00dev, 26, 0x5D);\n-\trt2800_rfcsr_write(rt2x00dev, 27, 0x00);\n-\trt2800_rfcsr_write(rt2x00dev, 28, 0x61);\n-\trt2800_rfcsr_write(rt2x00dev, 29, 0xB5);\n-\trt2800_rfcsr_write(rt2x00dev, 43, 0x02);\n-\n-\trt2800_rfcsr_write(rt2x00dev, 28, 0x62);\n-\trt2800_rfcsr_write(rt2x00dev, 29, 0xAD);\n-\trt2800_rfcsr_write(rt2x00dev, 39, 0x80);\n+\tif (rt2800_hw_get_chipver(rt2x00dev) > 1) {\n+\t\trt2800_rfcsr_write(rt2x00dev, 11, 0x21);\n+\t\tif (rt2800_clk_is_20mhz(rt2x00dev))\n+\t\t\trt2800_rfcsr_write(rt2x00dev, 13, 0x03);\n+\t\telse\n+\t\t\trt2800_rfcsr_write(rt2x00dev, 13, 0x00);\n+\t\trt2800_rfcsr_write(rt2x00dev, 14, 0x7C);\n+\t\trt2800_rfcsr_write(rt2x00dev, 16, 0x80);\n+\t\trt2800_rfcsr_write(rt2x00dev, 17, 0x99);\n+\t\trt2800_rfcsr_write(rt2x00dev, 18, 0x99);\n+\t\trt2800_rfcsr_write(rt2x00dev, 19, 0x09);\n+\t\trt2800_rfcsr_write(rt2x00dev, 20, 0x50);\n+\t\trt2800_rfcsr_write(rt2x00dev, 21, 0xB0);\n+\t\trt2800_rfcsr_write(rt2x00dev, 22, 0x00);\n+\t\trt2800_rfcsr_write(rt2x00dev, 23, 0x06);\n+\t\trt2800_rfcsr_write(rt2x00dev, 24, 0x00);\n+\t\trt2800_rfcsr_write(rt2x00dev, 25, 0x00);\n+\t\trt2800_rfcsr_write(rt2x00dev, 26, 0x5D);\n+\t\trt2800_rfcsr_write(rt2x00dev, 27, 0x00);\n+\t\trt2800_rfcsr_write(rt2x00dev, 28, 0x61);\n+\t\trt2800_rfcsr_write(rt2x00dev, 29, 0xB5);\n+\t\trt2800_rfcsr_write(rt2x00dev, 43, 0x02);\n+\t}\n+\n+\tif (rt2800_hw_get_chipver(rt2x00dev) > 1 &&\n+\t    rt2800_hw_get_chipeco(rt2x00dev) >= 2) {\n+\t\trt2800_rfcsr_write(rt2x00dev, 28, 0x62);\n+\t\trt2800_rfcsr_write(rt2x00dev, 29, 0xAD);\n+\t\trt2800_rfcsr_write(rt2x00dev, 39, 0x80);\n+\t}\n \n \t/* Initialize RF channel register to default value */\n \trt2800_rfcsr_write_chanreg(rt2x00dev, 0, 0x03);\n@@ -10497,63 +10530,71 @@ static void rt2800_init_rfcsr_6352(struc\n \n \trt2800_rfcsr_write_bank(rt2x00dev, 6, 45, 0xC5);\n \n-\trt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x47);\n-\trt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x71);\n-\trt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x33);\n-\trt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x0E);\n-\trt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x23);\n-\trt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA4);\n-\trt2800_rfcsr_write_chanreg(rt2x00dev, 20, 0x02);\n-\trt2800_rfcsr_write_chanreg(rt2x00dev, 21, 0x12);\n-\trt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x1C);\n-\trt2800_rfcsr_write_chanreg(rt2x00dev, 29, 0xEB);\n-\trt2800_rfcsr_write_chanreg(rt2x00dev, 32, 0x7D);\n-\trt2800_rfcsr_write_chanreg(rt2x00dev, 34, 0xD6);\n-\trt2800_rfcsr_write_chanreg(rt2x00dev, 36, 0x08);\n-\trt2800_rfcsr_write_chanreg(rt2x00dev, 38, 0xB4);\n-\trt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xD3);\n-\trt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xB3);\n-\trt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xD5);\n-\trt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x27);\n-\trt2800_rfcsr_write_bank(rt2x00dev, 4, 47, 0x67);\n-\trt2800_rfcsr_write_bank(rt2x00dev, 6, 47, 0x69);\n-\trt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xFF);\n-\trt2800_rfcsr_write_bank(rt2x00dev, 4, 54, 0x27);\n-\trt2800_rfcsr_write_bank(rt2x00dev, 6, 54, 0x20);\n-\trt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66);\n-\trt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xFF);\n-\trt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x1C);\n-\trt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x20);\n-\trt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B);\n-\trt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xF7);\n-\trt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x09);\n-\n-\trt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x51);\n-\trt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x06);\n-\trt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA7);\n-\trt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x2C);\n-\trt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x64);\n-\trt2800_rfcsr_write_chanreg(rt2x00dev, 8, 0x51);\n-\trt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x36);\n-\trt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x53);\n-\trt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x16);\n-\n-\trt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x6C);\n-\trt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xFC);\n-\trt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x1F);\n-\trt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x27);\n-\trt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66);\n-\trt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B);\n-\n-\t/* Initialize RF channel register for DRQFN */\n-\trt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xD3);\n-\trt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xE3);\n-\trt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xE5);\n-\trt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x28);\n-\trt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x68);\n-\trt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xF7);\n-\trt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x02);\n-\trt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xC7);\n+\tif (rt2800_hw_get_chipver(rt2x00dev) > 1) {\n+\t\trt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x47);\n+\t\trt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x71);\n+\t\trt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x33);\n+\t\trt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x0E);\n+\t\trt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x23);\n+\t\trt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA4);\n+\t\trt2800_rfcsr_write_chanreg(rt2x00dev, 20, 0x02);\n+\t\trt2800_rfcsr_write_chanreg(rt2x00dev, 21, 0x12);\n+\t\trt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x1C);\n+\t\trt2800_rfcsr_write_chanreg(rt2x00dev, 29, 0xEB);\n+\t\trt2800_rfcsr_write_chanreg(rt2x00dev, 32, 0x7D);\n+\t\trt2800_rfcsr_write_chanreg(rt2x00dev, 34, 0xD6);\n+\t\trt2800_rfcsr_write_chanreg(rt2x00dev, 36, 0x08);\n+\t\trt2800_rfcsr_write_chanreg(rt2x00dev, 38, 0xB4);\n+\t\trt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xD3);\n+\t\trt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xB3);\n+\t\trt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xD5);\n+\t\trt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x27);\n+\t\trt2800_rfcsr_write_bank(rt2x00dev, 4, 47, 0x67);\n+\t\trt2800_rfcsr_write_bank(rt2x00dev, 6, 47, 0x69);\n+\t\trt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xFF);\n+\t\trt2800_rfcsr_write_bank(rt2x00dev, 4, 54, 0x27);\n+\t\trt2800_rfcsr_write_bank(rt2x00dev, 6, 54, 0x20);\n+\t\trt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66);\n+\t\trt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xFF);\n+\t\trt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x1C);\n+\t\trt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x20);\n+\t\trt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B);\n+\t\trt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xF7);\n+\t\trt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x09);\n+\t}\n+\n+\tif (rt2800_hw_get_chipver(rt2x00dev) > 1 &&\n+\t    rt2800_hw_get_chipeco(rt2x00dev) >= 2) {\n+\t\trt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x51);\n+\t\trt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x06);\n+\t\trt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA7);\n+\t\trt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x2C);\n+\t\trt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x64);\n+\t\trt2800_rfcsr_write_chanreg(rt2x00dev, 8, 0x51);\n+\t\trt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x36);\n+\t\trt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x53);\n+\t\trt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x16);\n+\n+\t\trt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x6C);\n+\t\trt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xFC);\n+\t\trt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x1F);\n+\t\trt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x27);\n+\t\trt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66);\n+\t\trt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B);\n+\t}\n+\n+\tif (rt2800_hw_get_chippkg(rt2x00dev) == 0 &&\n+\t    rt2800_hw_get_chipver(rt2x00dev) == 1) {\n+\t\t/* Initialize RF channel register for DRQFN */\n+\t\trt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xD3);\n+\t\trt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xE3);\n+\t\trt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xE5);\n+\t\trt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x28);\n+\t\trt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x68);\n+\t\trt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xF7);\n+\t\trt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x02);\n+\t\trt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xC7);\n+\t}\n \n \t/* Initialize RF DC calibration register to default value */\n \trt2800_rfcsr_write_dccal(rt2x00dev, 0, 0x47);\n@@ -10616,12 +10657,17 @@ static void rt2800_init_rfcsr_6352(struc\n \trt2800_rfcsr_write_dccal(rt2x00dev, 62, 0x00);\n \trt2800_rfcsr_write_dccal(rt2x00dev, 63, 0x00);\n \n-\trt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x08);\n-\trt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x04);\n-\trt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x20);\n+\tif (rt2800_hw_get_chipver(rt2x00dev) > 1) {\n+\t\trt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x08);\n+\t\trt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x04);\n+\t\trt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x20);\n+\t}\n \n-\trt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x00);\n-\trt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x7C);\n+\tif (rt2800_hw_get_chipver(rt2x00dev) > 1 &&\n+\t    rt2800_hw_get_chipeco(rt2x00dev) >= 2) {\n+\t\trt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x00);\n+\t\trt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x7C);\n+\t}\n \n \trt2800_r_calibration(rt2x00dev);\n \trt2800_rf_self_txdc_cal(rt2x00dev);\n"
  },
  {
    "path": "package/kernel/mac80211/patches/subsys/110-mac80211_keep_keys_on_stop_ap.patch",
    "content": "Used for AP+STA support in OpenWrt - preserve AP mode keys across STA reconnects\n\n--- a/net/mac80211/cfg.c\n+++ b/net/mac80211/cfg.c\n@@ -1319,7 +1319,6 @@ static int ieee80211_stop_ap(struct wiph\n \tsdata->vif.bss_conf.ftmr_params = NULL;\n \n \t__sta_info_flush(sdata, true);\n-\tieee80211_free_keys(sdata, true);\n \n \tsdata->vif.bss_conf.enable_beacon = false;\n \tsdata->beacon_rate_set = false;\n"
  },
  {
    "path": "package/kernel/mac80211/patches/subsys/120-cfg80211_allow_perm_addr_change.patch",
    "content": "--- a/net/wireless/sysfs.c\n+++ b/net/wireless/sysfs.c\n@@ -24,18 +24,35 @@ static inline struct cfg80211_registered\n \treturn container_of(dev, struct cfg80211_registered_device, wiphy.dev);\n }\n \n-#define SHOW_FMT(name, fmt, member)\t\t\t\t\t\\\n+#define SHOW_FMT(name, fmt, member, mode)\t\t\t\t\\\n static ssize_t name ## _show(struct device *dev,\t\t\t\\\n \t\t\t      struct device_attribute *attr,\t\t\\\n \t\t\t      char *buf)\t\t\t\t\\\n {\t\t\t\t\t\t\t\t\t\\\n \treturn sprintf(buf, fmt \"\\n\", dev_to_rdev(dev)->member);\t\\\n }\t\t\t\t\t\t\t\t\t\\\n-static DEVICE_ATTR_RO(name)\n+static DEVICE_ATTR_##mode(name)\n \n-SHOW_FMT(index, \"%d\", wiphy_idx);\n-SHOW_FMT(macaddress, \"%pM\", wiphy.perm_addr);\n-SHOW_FMT(address_mask, \"%pM\", wiphy.addr_mask);\n+static ssize_t macaddress_store(struct device *dev,\n+\t\t\t\tstruct device_attribute *attr,\n+\t\t\t\tconst char *buf, size_t len)\n+{\n+\tu8 mac[ETH_ALEN];\n+\n+\tif (!mac_pton(buf, mac))\n+\t\treturn -EINVAL;\n+\n+\tif (buf[3 * ETH_ALEN - 1] && buf[3 * ETH_ALEN - 1] != '\\n')\n+\t\treturn -EINVAL;\n+\n+\tmemcpy(dev_to_rdev(dev)->wiphy.perm_addr, mac, ETH_ALEN);\n+\n+\treturn strnlen(buf, len);\n+}\n+\n+SHOW_FMT(index, \"%d\", wiphy_idx, RO);\n+SHOW_FMT(macaddress, \"%pM\", wiphy.perm_addr, RW);\n+SHOW_FMT(address_mask, \"%pM\", wiphy.addr_mask, RO);\n \n static ssize_t name_show(struct device *dev,\n \t\t\t struct device_attribute *attr,\n"
  },
  {
    "path": "package/kernel/mac80211/patches/subsys/150-disable_addr_notifier.patch",
    "content": "--- a/net/mac80211/main.c\n+++ b/net/mac80211/main.c\n@@ -337,7 +337,7 @@ void ieee80211_restart_hw(struct ieee802\n }\n EXPORT_SYMBOL(ieee80211_restart_hw);\n \n-#ifdef CONFIG_INET\n+#ifdef __disabled__CONFIG_INET\n static int ieee80211_ifa_changed(struct notifier_block *nb,\n \t\t\t\t unsigned long data, void *arg)\n {\n@@ -396,7 +396,7 @@ static int ieee80211_ifa_changed(struct\n }\n #endif\n \n-#if IS_ENABLED(CONFIG_IPV6)\n+#if IS_ENABLED(__disabled__CONFIG_IPV6)\n static int ieee80211_ifa6_changed(struct notifier_block *nb,\n \t\t\t\t  unsigned long data, void *arg)\n {\n@@ -1321,14 +1321,14 @@ int ieee80211_register_hw(struct ieee802\n \twiphy_unlock(hw->wiphy);\n \trtnl_unlock();\n \n-#ifdef CONFIG_INET\n+#ifdef __disabled__CONFIG_INET\n \tlocal->ifa_notifier.notifier_call = ieee80211_ifa_changed;\n \tresult = register_inetaddr_notifier(&local->ifa_notifier);\n \tif (result)\n \t\tgoto fail_ifa;\n #endif\n \n-#if IS_ENABLED(CONFIG_IPV6)\n+#if IS_ENABLED(__disabled__CONFIG_IPV6)\n \tlocal->ifa6_notifier.notifier_call = ieee80211_ifa6_changed;\n \tresult = register_inet6addr_notifier(&local->ifa6_notifier);\n \tif (result)\n@@ -1337,13 +1337,13 @@ int ieee80211_register_hw(struct ieee802\n \n \treturn 0;\n \n-#if IS_ENABLED(CONFIG_IPV6)\n+#if IS_ENABLED(__disabled__CONFIG_IPV6)\n  fail_ifa6:\n-#ifdef CONFIG_INET\n+#ifdef __disabled__CONFIG_INET\n \tunregister_inetaddr_notifier(&local->ifa_notifier);\n #endif\n #endif\n-#if defined(CONFIG_INET) || defined(CONFIG_IPV6)\n+#if defined(__disabled__CONFIG_INET) || defined(__disabled__CONFIG_IPV6)\n  fail_ifa:\n #endif\n \twiphy_unregister(local->hw.wiphy);\n@@ -1371,10 +1371,10 @@ void ieee80211_unregister_hw(struct ieee\n \ttasklet_kill(&local->tx_pending_tasklet);\n \ttasklet_kill(&local->tasklet);\n \n-#ifdef CONFIG_INET\n+#ifdef __disabled__CONFIG_INET\n \tunregister_inetaddr_notifier(&local->ifa_notifier);\n #endif\n-#if IS_ENABLED(CONFIG_IPV6)\n+#if IS_ENABLED(__disabled__CONFIG_IPV6)\n \tunregister_inet6addr_notifier(&local->ifa6_notifier);\n #endif\n \n"
  },
  {
    "path": "package/kernel/mac80211/patches/subsys/210-ap_scan.patch",
    "content": "--- a/net/mac80211/cfg.c\n+++ b/net/mac80211/cfg.c\n@@ -2497,7 +2497,7 @@ static int ieee80211_scan(struct wiphy *\n \t\t * the  frames sent while scanning on other channel will be\n \t\t * lost)\n \t\t */\n-\t\tif (sdata->u.ap.beacon &&\n+\t\tif (0 && sdata->u.ap.beacon &&\n \t\t    (!(wiphy->features & NL80211_FEATURE_AP_SCAN) ||\n \t\t     !(req->flags & NL80211_SCAN_FLAG_AP)))\n \t\t\treturn -EOPNOTSUPP;\n"
  },
  {
    "path": "package/kernel/mac80211/patches/subsys/301-mac80211-sta-randomize-BA-session-dialog-token-alloc.patch",
    "content": "From b478e06a16a8baa00c5ecc87c1d636981f2206d5 Mon Sep 17 00:00:00 2001\nFrom: Johannes Berg <johannes.berg@intel.com>\nDate: Tue, 29 Oct 2019 10:25:25 +0100\nSubject: [PATCH] mac80211: sta: randomize BA session dialog token allocator\n\nWe currently always start the dialog token generator at zero,\nso the first dialog token we use is always 1. This would be\nOK if we had a perfect guarantee that we always do a proper\ndeauth/re-auth handshake, but in IBSS mode this doesn't always\nhappen properly.\n\nTo make problems with block ack (aggregation) sessions getting\nstuck less likely, randomize the dialog token so if we start a\nnew session but the peer still has old state for us, it can\nbetter detect this.\n\nThis is really just a workaround to make things a bit more\nrobust than they are now - a better fix would be to do a full\nauthentication handshake in IBSS mode upon having discovered a\nnew station, and on the receiver resetting the state (removing\nand re-adding the station) on receiving the authentication\npacket.\n\nSigned-off-by: Johannes Berg <johannes.berg@intel.com>\n---\n net/mac80211/sta_info.c | 1 +\n 1 file changed, 1 insertion(+)\n\n--- a/net/mac80211/sta_info.c\n+++ b/net/mac80211/sta_info.c\n@@ -357,6 +357,7 @@ struct sta_info *sta_info_alloc(struct i\n \tINIT_WORK(&sta->drv_deliver_wk, sta_deliver_ps_frames);\n \tINIT_WORK(&sta->ampdu_mlme.work, ieee80211_ba_session_work);\n \tmutex_init(&sta->ampdu_mlme.mtx);\n+\tsta->ampdu_mlme.dialog_token_allocator = prandom_u32_max(U8_MAX);\n #ifdef CPTCFG_MAC80211_MESH\n \tif (ieee80211_vif_is_mesh(&sdata->vif)) {\n \t\tsta->mesh = kzalloc(sizeof(*sta->mesh), gfp);\n"
  },
  {
    "path": "package/kernel/mac80211/patches/subsys/303-mac80211-set-up-the-fwd_skb-dev-for-mesh-forwarding.patch",
    "content": "From: Xing Song <xing.song@mediatek.com>\nDate: Tue, 23 Nov 2021 11:31:23 +0800\nSubject: [PATCH] mac80211: set up the fwd_skb->dev for mesh forwarding\n\nMesh forwarding requires that the fwd_skb->dev is set up for TX handling,\notherwise the following warning will be generated, so set it up for the\npending frames.\n\n[   72.835674 ] WARNING: CPU: 0 PID: 1193 at __skb_flow_dissect+0x284/0x1298\n[   72.842379 ] Modules linked in: ksmbd pppoe ppp_async l2tp_ppp ...\n[   72.962020 ] CPU: 0 PID: 1193 Comm: kworker/u5:1 Tainted: P S 5.4.137 #0\n[   72.969938 ] Hardware name: MT7622_MT7531 RFB (DT)\n[   72.974659 ] Workqueue: napi_workq napi_workfn\n[   72.979025 ] pstate: 60000005 (nZCv daif -PAN -UAO)\n[   72.983822 ] pc : __skb_flow_dissect+0x284/0x1298\n[   72.988444 ] lr : __skb_flow_dissect+0x54/0x1298\n[   72.992977 ] sp : ffffffc010c738c0\n[   72.996293 ] x29: ffffffc010c738c0 x28: 0000000000000000\n[   73.001615 ] x27: 000000000000ffc2 x26: ffffff800c2eb818\n[   73.006937 ] x25: ffffffc010a987c8 x24: 00000000000000ce\n[   73.012259 ] x23: ffffffc010c73a28 x22: ffffffc010a99c60\n[   73.017581 ] x21: 000000000000ffc2 x20: ffffff80094da800\n[   73.022903 ] x19: 0000000000000000 x18: 0000000000000014\n[   73.028226 ] x17: 00000000084d16af x16: 00000000d1fc0bab\n[   73.033548 ] x15: 00000000715f6034 x14: 000000009dbdd301\n[   73.038870 ] x13: 00000000ea4dcbc3 x12: 0000000000000040\n[   73.044192 ] x11: 000000000eb00ff0 x10: 0000000000000000\n[   73.049513 ] x9 : 000000000eb00073 x8 : 0000000000000088\n[   73.054834 ] x7 : 0000000000000000 x6 : 0000000000000001\n[   73.060155 ] x5 : 0000000000000000 x4 : 0000000000000000\n[   73.065476 ] x3 : ffffffc010a98000 x2 : 0000000000000000\n[   73.070797 ] x1 : 0000000000000000 x0 : 0000000000000000\n[   73.076120 ] Call trace:\n[   73.078572 ]  __skb_flow_dissect+0x284/0x1298\n[   73.082846 ]  __skb_get_hash+0x7c/0x228\n[   73.086629 ]  ieee80211_txq_may_transmit+0x7fc/0x17b8 [mac80211]\n[   73.092564 ]  ieee80211_tx_prepare_skb+0x20c/0x268 [mac80211]\n[   73.098238 ]  ieee80211_tx_pending+0x144/0x330 [mac80211]\n[   73.103560 ]  tasklet_action_common.isra.16+0xb4/0x158\n[   73.108618 ]  tasklet_action+0x2c/0x38\n[   73.112286 ]  __do_softirq+0x168/0x3b0\n[   73.115954 ]  do_softirq.part.15+0x88/0x98\n[   73.119969 ]  __local_bh_enable_ip+0xb0/0xb8\n[   73.124156 ]  napi_workfn+0x58/0x90\n[   73.127565 ]  process_one_work+0x20c/0x478\n[   73.131579 ]  worker_thread+0x50/0x4f0\n[   73.135249 ]  kthread+0x124/0x128\n[   73.138484 ]  ret_from_fork+0x10/0x1c\n\nSigned-off-by: Xing Song <xing.song@mediatek.com>\n---\n\n--- a/net/mac80211/rx.c\n+++ b/net/mac80211/rx.c\n@@ -2949,6 +2949,7 @@ ieee80211_rx_h_mesh_fwding(struct ieee80\n \tif (!fwd_skb)\n \t\tgoto out;\n \n+\tfwd_skb->dev = sdata->dev;\n \tfwd_hdr =  (struct ieee80211_hdr *) fwd_skb->data;\n \tfwd_hdr->frame_control &= ~cpu_to_le16(IEEE80211_FCTL_RETRY);\n \tinfo = IEEE80211_SKB_CB(fwd_skb);\n"
  },
  {
    "path": "package/kernel/mac80211/patches/subsys/306-mac80211-use-coarse-boottime-for-airtime-fairness-co.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nDate: Tue, 14 Dec 2021 17:53:12 +0100\nSubject: [PATCH] mac80211: use coarse boottime for airtime fairness code\n\nThe time values used by the airtime fairness code only need to be accurate\nenough to cover station activity detection.\nUsing ktime_get_coarse_boottime_ns instead of ktime_get_boottime_ns will\ndrop the accuracy down to jiffies intervals, but at the same time saves\na lot of CPU cycles in a hot path\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n\n--- a/net/mac80211/tx.c\n+++ b/net/mac80211/tx.c\n@@ -3820,7 +3820,7 @@ struct ieee80211_txq *ieee80211_next_txq\n {\n \tstruct ieee80211_local *local = hw_to_local(hw);\n \tstruct airtime_sched_info *air_sched;\n-\tu64 now = ktime_get_boottime_ns();\n+\tu64 now = ktime_get_coarse_boottime_ns();\n \tstruct ieee80211_txq *ret = NULL;\n \tstruct airtime_info *air_info;\n \tstruct txq_info *txqi = NULL;\n@@ -3947,7 +3947,7 @@ void ieee80211_update_airtime_weight(str\n \tu64 weight_sum = 0;\n \n \tif (unlikely(!now))\n-\t\tnow = ktime_get_boottime_ns();\n+\t\tnow = ktime_get_coarse_boottime_ns();\n \n \tlockdep_assert_held(&air_sched->lock);\n \n@@ -3973,7 +3973,7 @@ void ieee80211_schedule_txq(struct ieee8\n \tstruct ieee80211_local *local = hw_to_local(hw);\n \tstruct txq_info *txqi = to_txq_info(txq);\n \tstruct airtime_sched_info *air_sched;\n-\tu64 now = ktime_get_boottime_ns();\n+\tu64 now = ktime_get_coarse_boottime_ns();\n \tstruct airtime_info *air_info;\n \tu8 ac = txq->ac;\n \tbool was_active;\n@@ -4031,7 +4031,7 @@ static void __ieee80211_unschedule_txq(s\n \n \tif (!purge)\n \t\tairtime_set_active(air_sched, air_info,\n-\t\t\t\t   ktime_get_boottime_ns());\n+\t\t\t\t   ktime_get_coarse_boottime_ns());\n \n \trb_erase_cached(&txqi->schedule_order,\n \t\t\t&air_sched->active_txqs);\n@@ -4119,7 +4119,7 @@ bool ieee80211_txq_may_transmit(struct i\n \tif (RB_EMPTY_NODE(&txqi->schedule_order))\n \t\tgoto out;\n \n-\tnow = ktime_get_boottime_ns();\n+\tnow = ktime_get_coarse_boottime_ns();\n \n \t/* Like in ieee80211_next_txq(), make sure the first station in the\n \t * scheduling order is eligible for transmission to avoid starvation.\n"
  },
  {
    "path": "package/kernel/mac80211/patches/subsys/307-mac80211_hwsim-make-6-GHz-channels-usable.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nDate: Mon, 24 May 2021 11:46:09 +0200\nSubject: [PATCH] mac80211_hwsim: make 6 GHz channels usable\n\nThe previous commit that claimed to add 6 GHz channels didn't actually make\nthem usable, since the 6 GHz band was not registered with mac80211.\n\nFixes: 28881922abd7 (\"mac80211_hwsim: add 6GHz channels\")\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n\n--- a/drivers/net/wireless/mac80211_hwsim.c\n+++ b/drivers/net/wireless/mac80211_hwsim.c\n@@ -3001,15 +3001,19 @@ static void mac80211_hwsim_he_capab(stru\n {\n \tu16 n_iftype_data;\n \n-\tif (sband->band == NL80211_BAND_2GHZ) {\n+\tswitch (sband->band) {\n+\tcase NL80211_BAND_2GHZ:\n \t\tn_iftype_data = ARRAY_SIZE(he_capa_2ghz);\n \t\tsband->iftype_data =\n \t\t\t(struct ieee80211_sband_iftype_data *)he_capa_2ghz;\n-\t} else if (sband->band == NL80211_BAND_5GHZ) {\n+\t\tbreak;\n+\tcase NL80211_BAND_5GHZ:\n+\tcase NL80211_BAND_6GHZ:\n \t\tn_iftype_data = ARRAY_SIZE(he_capa_5ghz);\n \t\tsband->iftype_data =\n \t\t\t(struct ieee80211_sband_iftype_data *)he_capa_5ghz;\n-\t} else {\n+\t\tbreak;\n+\tdefault:\n \t\treturn;\n \t}\n \n@@ -3299,6 +3303,12 @@ static int mac80211_hwsim_new_radio(stru\n \t\t\tsband->vht_cap.vht_mcs.tx_mcs_map =\n \t\t\t\tsband->vht_cap.vht_mcs.rx_mcs_map;\n \t\t\tbreak;\n+\t\tcase NL80211_BAND_6GHZ:\n+\t\t\tsband->channels = data->channels_6ghz;\n+\t\t\tsband->n_channels = ARRAY_SIZE(hwsim_channels_6ghz);\n+\t\t\tsband->bitrates = data->rates + 4;\n+\t\t\tsband->n_bitrates = ARRAY_SIZE(hwsim_rates) - 4;\n+\t\t\tbreak;\n \t\tcase NL80211_BAND_S1GHZ:\n \t\t\tmemcpy(&sband->s1g_cap, &hwsim_s1g_cap,\n \t\t\t       sizeof(sband->s1g_cap));\n@@ -3309,6 +3319,13 @@ static int mac80211_hwsim_new_radio(stru\n \t\t\tcontinue;\n \t\t}\n \n+\t\tmac80211_hwsim_he_capab(sband);\n+\n+\t\thw->wiphy->bands[band] = sband;\n+\n+\t\tif (band == NL80211_BAND_6GHZ)\n+\t\t\tcontinue;\n+\n \t\tsband->ht_cap.ht_supported = true;\n \t\tsband->ht_cap.cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |\n \t\t\t\t    IEEE80211_HT_CAP_GRN_FLD |\n@@ -3322,10 +3339,6 @@ static int mac80211_hwsim_new_radio(stru\n \t\tsband->ht_cap.mcs.rx_mask[0] = 0xff;\n \t\tsband->ht_cap.mcs.rx_mask[1] = 0xff;\n \t\tsband->ht_cap.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;\n-\n-\t\tmac80211_hwsim_he_capab(sband);\n-\n-\t\thw->wiphy->bands[band] = sband;\n \t}\n \n \t/* By default all radios belong to the first group */\n"
  },
  {
    "path": "package/kernel/mac80211/patches/subsys/308-mac80211-add-support-for-.ndo_fill_forward_path.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nDate: Fri, 12 Nov 2021 12:22:23 +0100\nSubject: [PATCH] mac80211: add support for .ndo_fill_forward_path\n\nThis allows drivers to provide a destination device + info for flow offload\nOnly supported in combination with 802.3 encap offload\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\nTested-by: Lorenzo Bianconi <lorenzo@kernel.org>\nLink: https://lore.kernel.org/r/20211112112223.1209-1-nbd@nbd.name\nSigned-off-by: Johannes Berg <johannes.berg@intel.com>\n---\n\n--- a/include/net/mac80211.h\n+++ b/include/net/mac80211.h\n@@ -3937,6 +3937,8 @@ struct ieee80211_prep_tx_info {\n  *\ttwt structure.\n  * @twt_teardown_request: Update the hw with TWT teardown request received\n  *\tfrom the peer.\n+ * @net_fill_forward_path: Called from .ndo_fill_forward_path in order to\n+ *\tresolve a path for hardware flow offloading\n  */\n struct ieee80211_ops {\n \tvoid (*tx)(struct ieee80211_hw *hw,\n@@ -4265,6 +4267,13 @@ struct ieee80211_ops {\n \t\t\t      struct ieee80211_twt_setup *twt);\n \tvoid (*twt_teardown_request)(struct ieee80211_hw *hw,\n \t\t\t\t     struct ieee80211_sta *sta, u8 flowid);\n+#if LINUX_VERSION_IS_GEQ(5,10,0)\n+\tint (*net_fill_forward_path)(struct ieee80211_hw *hw,\n+\t\t\t\t     struct ieee80211_vif *vif,\n+\t\t\t\t     struct ieee80211_sta *sta,\n+\t\t\t\t     struct net_device_path_ctx *ctx,\n+\t\t\t\t     struct net_device_path *path);\n+#endif\n };\n \n /**\n--- a/net/mac80211/driver-ops.h\n+++ b/net/mac80211/driver-ops.h\n@@ -1486,4 +1486,28 @@ static inline void drv_twt_teardown_requ\n \ttrace_drv_return_void(local);\n }\n \n+#if LINUX_VERSION_IS_GEQ(5,10,0)\n+static inline int drv_net_fill_forward_path(struct ieee80211_local *local,\n+\t\t\t\t\t    struct ieee80211_sub_if_data *sdata,\n+\t\t\t\t\t    struct ieee80211_sta *sta,\n+\t\t\t\t\t    struct net_device_path_ctx *ctx,\n+\t\t\t\t\t    struct net_device_path *path)\n+{\n+\tint ret = -EOPNOTSUPP;\n+\n+\tsdata = get_bss_sdata(sdata);\n+\tif (!check_sdata_in_driver(sdata))\n+\t\treturn -EIO;\n+\n+\ttrace_drv_net_fill_forward_path(local, sdata, sta);\n+\tif (local->ops->net_fill_forward_path)\n+\t\tret = local->ops->net_fill_forward_path(&local->hw,\n+\t\t\t\t\t\t\t&sdata->vif, sta,\n+\t\t\t\t\t\t\tctx, path);\n+\ttrace_drv_return_int(local, ret);\n+\n+\treturn ret;\n+}\n+#endif\n+\n #endif /* __MAC80211_DRIVER_OPS */\n--- a/net/mac80211/ieee80211_i.h\n+++ b/net/mac80211/ieee80211_i.h\n@@ -1485,7 +1485,7 @@ struct ieee80211_local {\n };\n \n static inline struct ieee80211_sub_if_data *\n-IEEE80211_DEV_TO_SUB_IF(struct net_device *dev)\n+IEEE80211_DEV_TO_SUB_IF(const struct net_device *dev)\n {\n \treturn netdev_priv(dev);\n }\n--- a/net/mac80211/iface.c\n+++ b/net/mac80211/iface.c\n@@ -822,6 +822,66 @@ static const struct net_device_ops ieee8\n \n };\n \n+#if LINUX_VERSION_IS_GEQ(5,10,0)\n+static int ieee80211_netdev_fill_forward_path(struct net_device_path_ctx *ctx,\n+\t\t\t\t\t      struct net_device_path *path)\n+{\n+\tstruct ieee80211_sub_if_data *sdata;\n+\tstruct ieee80211_local *local;\n+\tstruct sta_info *sta;\n+\tint ret = -ENOENT;\n+\n+\tsdata = IEEE80211_DEV_TO_SUB_IF(ctx->dev);\n+\tlocal = sdata->local;\n+\n+\tif (!local->ops->net_fill_forward_path)\n+\t\treturn -EOPNOTSUPP;\n+\n+\trcu_read_lock();\n+\tswitch (sdata->vif.type) {\n+\tcase NL80211_IFTYPE_AP_VLAN:\n+\t\tsta = rcu_dereference(sdata->u.vlan.sta);\n+\t\tif (sta)\n+\t\t\tbreak;\n+\t\tif (sdata->wdev.use_4addr)\n+\t\t\tgoto out;\n+\t\tif (is_multicast_ether_addr(ctx->daddr))\n+\t\t\tgoto out;\n+\t\tsta = sta_info_get_bss(sdata, ctx->daddr);\n+\t\tbreak;\n+\tcase NL80211_IFTYPE_AP:\n+\t\tif (is_multicast_ether_addr(ctx->daddr))\n+\t\t\tgoto out;\n+\t\tsta = sta_info_get(sdata, ctx->daddr);\n+\t\tbreak;\n+\tcase NL80211_IFTYPE_STATION:\n+\t\tif (sdata->wdev.wiphy->flags & WIPHY_FLAG_SUPPORTS_TDLS) {\n+\t\t\tsta = sta_info_get(sdata, ctx->daddr);\n+\t\t\tif (sta && test_sta_flag(sta, WLAN_STA_TDLS_PEER)) {\n+\t\t\t\tif (!test_sta_flag(sta, WLAN_STA_TDLS_PEER_AUTH))\n+\t\t\t\t\tgoto out;\n+\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t}\n+\n+\t\tsta = sta_info_get(sdata, sdata->u.mgd.bssid);\n+\t\tbreak;\n+\tdefault:\n+\t\tgoto out;\n+\t}\n+\n+\tif (!sta)\n+\t\tgoto out;\n+\n+\tret = drv_net_fill_forward_path(local, sdata, &sta->sta, ctx, path);\n+out:\n+\trcu_read_unlock();\n+\n+\treturn ret;\n+}\n+#endif\n+\n static const struct net_device_ops ieee80211_dataif_8023_ops = {\n #if LINUX_VERSION_IS_LESS(4,10,0)\n \t.ndo_change_mtu = __change_mtu,\n@@ -839,7 +899,9 @@ static const struct net_device_ops ieee8\n #else\n \t.ndo_get_stats64 = bp_ieee80211_get_stats64,\n #endif\n-\n+#if LINUX_VERSION_IS_GEQ(5,10,0)\n+\t.ndo_fill_forward_path = ieee80211_netdev_fill_forward_path,\n+#endif\n };\n \n static bool ieee80211_iftype_supports_hdr_offload(enum nl80211_iftype iftype)\n--- a/net/mac80211/trace.h\n+++ b/net/mac80211/trace.h\n@@ -2892,6 +2892,15 @@ TRACE_EVENT(drv_twt_teardown_request,\n \t)\n );\n \n+#if LINUX_VERSION_IS_GEQ(5,10,0)\n+DEFINE_EVENT(sta_event, drv_net_fill_forward_path,\n+\tTP_PROTO(struct ieee80211_local *local,\n+\t\t struct ieee80211_sub_if_data *sdata,\n+\t\t struct ieee80211_sta *sta),\n+\tTP_ARGS(local, sdata, sta)\n+);\n+#endif\n+\n #endif /* !__MAC80211_DRIVER_TRACE || TRACE_HEADER_MULTI_READ */\n \n #undef TRACE_INCLUDE_PATH\n"
  },
  {
    "path": "package/kernel/mac80211/patches/subsys/309-mac80211-minstrel_ht-fix-MINSTREL_FRAC-macro.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nDate: Wed, 28 Apr 2021 21:03:13 +0200\nSubject: [PATCH] mac80211: minstrel_ht: fix MINSTREL_FRAC macro\n\nAdd missing braces to avoid issues with e.g. using additions in the\ndiv expression\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n\n--- a/net/mac80211/rc80211_minstrel_ht.h\n+++ b/net/mac80211/rc80211_minstrel_ht.h\n@@ -14,7 +14,7 @@\n \n /* scaled fraction values */\n #define MINSTREL_SCALE  12\n-#define MINSTREL_FRAC(val, div) (((val) << MINSTREL_SCALE) / div)\n+#define MINSTREL_FRAC(val, div) (((val) << MINSTREL_SCALE) / (div))\n #define MINSTREL_TRUNC(val) ((val) >> MINSTREL_SCALE)\n \n #define EWMA_LEVEL\t96\t/* ewma weighting factor [/EWMA_DIV] */\n"
  },
  {
    "path": "package/kernel/mac80211/patches/subsys/310-mac80211-minstrel_ht-reduce-fluctuations-in-rate-pro.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nDate: Sat, 6 Feb 2021 16:08:01 +0100\nSubject: [PATCH] mac80211: minstrel_ht: reduce fluctuations in rate\n probability stats\n\nIn some scenarios when there is a lot of fluctuation in packet error rates,\nrate switching can be amplified when the statistics get skewed by time slots\nwith very few tries.\nMake the input data to the moving average more smooth by adding the\nsuccess/attempts count from the last stats window as well. This has the\nadvantage of smoothing the data without introducing any extra lag to sampling\nrates.\nThis significantly improves rate stability on a strong test link subjected to\nperiodic noise bursts generated with a SDR\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n\n--- a/net/mac80211/rc80211_minstrel_ht.c\n+++ b/net/mac80211/rc80211_minstrel_ht.c\n@@ -700,7 +700,8 @@ minstrel_ht_calc_rate_stats(struct minst\n \tunsigned int cur_prob;\n \n \tif (unlikely(mrs->attempts > 0)) {\n-\t\tcur_prob = MINSTREL_FRAC(mrs->success, mrs->attempts);\n+\t\tcur_prob = MINSTREL_FRAC(mrs->success + mrs->last_success,\n+\t\t\t\t\t mrs->attempts + mrs->last_attempts);\n \t\tminstrel_filter_avg_add(&mrs->prob_avg,\n \t\t\t\t\t&mrs->prob_avg_1, cur_prob);\n \t\tmrs->att_hist += mrs->attempts;\n"
  },
  {
    "path": "package/kernel/mac80211/patches/subsys/311-mac80211-minstrel_ht-rework-rate-downgrade-code-and-.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nDate: Sat, 6 Feb 2021 16:33:14 +0100\nSubject: [PATCH] mac80211: minstrel_ht: rework rate downgrade code and\n max_prob rate selection\n\nThe current fallback code for fast rate switching on potentially failing rates\nis triggering too often if there is some strong noise on the channel. This can\nlead to wild fluctuations in the rate selection.\nAdditionally, switching down to max_prob_rate can create a significant gap down\nin throughput, especially when using only 2 spatial streams, because max_prob_rate\nis limited to using fewer streams than the max_tp rates.\nIn order to improve throughput without reducing reliability too much, use the\nrate downgrade code for the max_prob_rate only, and allow the non-downgraded\nmax_prob_rate to use as many spatial streams as the max_tp rates\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n\n--- a/net/mac80211/rc80211_minstrel_ht.c\n+++ b/net/mac80211/rc80211_minstrel_ht.c\n@@ -511,6 +511,14 @@ minstrel_ht_set_best_prob_rate(struct mi\n \tint cur_tp_avg, cur_group, cur_idx;\n \tint max_gpr_group, max_gpr_idx;\n \tint max_gpr_tp_avg, max_gpr_prob;\n+\tint min_dur;\n+\n+\tmin_dur = max(minstrel_get_duration(mi->max_tp_rate[0]),\n+\t\t      minstrel_get_duration(mi->max_tp_rate[1]));\n+\n+\t/* make the rate at least 18% slower than max tp rates */\n+\tif (minstrel_get_duration(index) <= min_dur * 19 / 16)\n+\t\treturn;\n \n \tcur_group = MI_RATE_GROUP(index);\n \tcur_idx = MI_RATE_IDX(index);\n@@ -532,11 +540,6 @@ minstrel_ht_set_best_prob_rate(struct mi\n \t    !minstrel_ht_is_legacy_group(max_tp_group))\n \t\treturn;\n \n-\t/* skip rates faster than max tp rate with lower prob */\n-\tif (minstrel_get_duration(mi->max_tp_rate[0]) > minstrel_get_duration(index) &&\n-\t    mrs->prob_avg < max_tp_prob)\n-\t\treturn;\n-\n \tmax_gpr_group = MI_RATE_GROUP(mg->max_group_prob_rate);\n \tmax_gpr_idx = MI_RATE_IDX(mg->max_group_prob_rate);\n \tmax_gpr_prob = mi->groups[max_gpr_group].rates[max_gpr_idx].prob_avg;\n@@ -594,40 +597,6 @@ minstrel_ht_assign_best_tp_rates(struct\n \n }\n \n-/*\n- * Try to increase robustness of max_prob rate by decrease number of\n- * streams if possible.\n- */\n-static inline void\n-minstrel_ht_prob_rate_reduce_streams(struct minstrel_ht_sta *mi)\n-{\n-\tstruct minstrel_mcs_group_data *mg;\n-\tint tmp_max_streams, group, tmp_idx, tmp_prob;\n-\tint tmp_tp = 0;\n-\n-\tif (!mi->sta->ht_cap.ht_supported)\n-\t\treturn;\n-\n-\tgroup = MI_RATE_GROUP(mi->max_tp_rate[0]);\n-\ttmp_max_streams = minstrel_mcs_groups[group].streams;\n-\tfor (group = 0; group < ARRAY_SIZE(minstrel_mcs_groups); group++) {\n-\t\tmg = &mi->groups[group];\n-\t\tif (!mi->supported[group] || group == MINSTREL_CCK_GROUP)\n-\t\t\tcontinue;\n-\n-\t\ttmp_idx = MI_RATE_IDX(mg->max_group_prob_rate);\n-\t\ttmp_prob = mi->groups[group].rates[tmp_idx].prob_avg;\n-\n-\t\tif (tmp_tp < minstrel_ht_get_tp_avg(mi, group, tmp_idx, tmp_prob) &&\n-\t\t   (minstrel_mcs_groups[group].streams < tmp_max_streams)) {\n-\t\t\t\tmi->max_prob_rate = mg->max_group_prob_rate;\n-\t\t\t\ttmp_tp = minstrel_ht_get_tp_avg(mi, group,\n-\t\t\t\t\t\t\t\ttmp_idx,\n-\t\t\t\t\t\t\t\ttmp_prob);\n-\t\t}\n-\t}\n-}\n-\n static u16\n __minstrel_ht_get_sample_rate(struct minstrel_ht_sta *mi,\n \t\t\t      enum minstrel_sample_type type)\n@@ -1107,8 +1076,6 @@ minstrel_ht_update_stats(struct minstrel\n \n \tmi->max_prob_rate = tmp_max_prob_rate;\n \n-\t/* Try to increase robustness of max_prob_rate*/\n-\tminstrel_ht_prob_rate_reduce_streams(mi);\n \tminstrel_ht_refill_sample_rates(mi);\n \n #ifdef CPTCFG_MAC80211_DEBUGFS\n@@ -1153,7 +1120,7 @@ minstrel_ht_txstat_valid(struct minstrel\n }\n \n static void\n-minstrel_downgrade_rate(struct minstrel_ht_sta *mi, u16 *idx, bool primary)\n+minstrel_downgrade_prob_rate(struct minstrel_ht_sta *mi, u16 *idx)\n {\n \tint group, orig_group;\n \n@@ -1168,11 +1135,7 @@ minstrel_downgrade_rate(struct minstrel_\n \t\t    minstrel_mcs_groups[orig_group].streams)\n \t\t\tcontinue;\n \n-\t\tif (primary)\n-\t\t\t*idx = mi->groups[group].max_group_tp_rate[0];\n-\t\telse\n-\t\t\t*idx = mi->groups[group].max_group_tp_rate[1];\n-\t\tbreak;\n+\t\t*idx = mi->groups[group].max_group_prob_rate;\n \t}\n }\n \n@@ -1183,7 +1146,7 @@ minstrel_ht_tx_status(void *priv, struct\n \tstruct ieee80211_tx_info *info = st->info;\n \tstruct minstrel_ht_sta *mi = priv_sta;\n \tstruct ieee80211_tx_rate *ar = info->status.rates;\n-\tstruct minstrel_rate_stats *rate, *rate2;\n+\tstruct minstrel_rate_stats *rate;\n \tstruct minstrel_priv *mp = priv;\n \tu32 update_interval = mp->update_interval;\n \tbool last, update = false;\n@@ -1233,18 +1196,13 @@ minstrel_ht_tx_status(void *priv, struct\n \t\t/*\n \t\t * check for sudden death of spatial multiplexing,\n \t\t * downgrade to a lower number of streams if necessary.\n+\t\t * only do this for the max_prob_rate to prevent spurious\n+\t\t * rate fluctuations when the link changes suddenly\n \t\t */\n-\t\trate = minstrel_get_ratestats(mi, mi->max_tp_rate[0]);\n+\t\trate = minstrel_get_ratestats(mi, mi->max_prob_rate);\n \t\tif (rate->attempts > 30 &&\n \t\t    rate->success < rate->attempts / 4) {\n-\t\t\tminstrel_downgrade_rate(mi, &mi->max_tp_rate[0], true);\n-\t\t\tupdate = true;\n-\t\t}\n-\n-\t\trate2 = minstrel_get_ratestats(mi, mi->max_tp_rate[1]);\n-\t\tif (rate2->attempts > 30 &&\n-\t\t    rate2->success < rate2->attempts / 4) {\n-\t\t\tminstrel_downgrade_rate(mi, &mi->max_tp_rate[1], false);\n+\t\t\tminstrel_downgrade_prob_rate(mi, &mi->max_prob_rate);\n \t\t\tupdate = true;\n \t\t}\n \t}\n"
  },
  {
    "path": "package/kernel/mac80211/patches/subsys/312-mac80211-split-beacon-retrieval-functions.patch",
    "content": "From: Aloka Dixit <alokad@codeaurora.org>\nDate: Tue, 5 Oct 2021 21:09:36 -0700\nSubject: [PATCH] mac80211: split beacon retrieval functions\n\nSplit __ieee80211_beacon_get() into a separate function for AP mode\nieee80211_beacon_get_ap().\nAlso, move the code common to all modes (AP, adhoc and mesh) to\na separate function ieee80211_beacon_get_finish().\n\nSigned-off-by: Aloka Dixit <alokad@codeaurora.org>\nLink: https://lore.kernel.org/r/20211006040938.9531-2-alokad@codeaurora.org\nSigned-off-by: Johannes Berg <johannes.berg@intel.com>\n---\n\n--- a/net/mac80211/tx.c\n+++ b/net/mac80211/tx.c\n@@ -4987,6 +4987,115 @@ static int ieee80211_beacon_protect(stru\n \treturn 0;\n }\n \n+static void\n+ieee80211_beacon_get_finish(struct ieee80211_hw *hw,\n+\t\t\t    struct ieee80211_vif *vif,\n+\t\t\t    struct ieee80211_mutable_offsets *offs,\n+\t\t\t    struct beacon_data *beacon,\n+\t\t\t    struct sk_buff *skb,\n+\t\t\t    struct ieee80211_chanctx_conf *chanctx_conf,\n+\t\t\t    u16 csa_off_base)\n+{\n+\tstruct ieee80211_local *local = hw_to_local(hw);\n+\tstruct ieee80211_sub_if_data *sdata = vif_to_sdata(vif);\n+\tstruct ieee80211_tx_info *info;\n+\tenum nl80211_band band;\n+\tstruct ieee80211_tx_rate_control txrc;\n+\n+\t/* CSA offsets */\n+\tif (offs && beacon) {\n+\t\tu16 i;\n+\n+\t\tfor (i = 0; i < IEEE80211_MAX_CNTDWN_COUNTERS_NUM; i++) {\n+\t\t\tu16 csa_off = beacon->cntdwn_counter_offsets[i];\n+\n+\t\t\tif (!csa_off)\n+\t\t\t\tcontinue;\n+\n+\t\t\toffs->cntdwn_counter_offs[i] = csa_off_base + csa_off;\n+\t\t}\n+\t}\n+\n+\tband = chanctx_conf->def.chan->band;\n+\tinfo = IEEE80211_SKB_CB(skb);\n+\tinfo->flags |= IEEE80211_TX_INTFL_DONT_ENCRYPT;\n+\tinfo->flags |= IEEE80211_TX_CTL_NO_ACK;\n+\tinfo->band = band;\n+\n+\tmemset(&txrc, 0, sizeof(txrc));\n+\ttxrc.hw = hw;\n+\ttxrc.sband = local->hw.wiphy->bands[band];\n+\ttxrc.bss_conf = &sdata->vif.bss_conf;\n+\ttxrc.skb = skb;\n+\ttxrc.reported_rate.idx = -1;\n+\tif (sdata->beacon_rate_set && sdata->beacon_rateidx_mask[band])\n+\t\ttxrc.rate_idx_mask = sdata->beacon_rateidx_mask[band];\n+\telse\n+\t\ttxrc.rate_idx_mask = sdata->rc_rateidx_mask[band];\n+\ttxrc.bss = true;\n+\trate_control_get_rate(sdata, NULL, &txrc);\n+\n+\tinfo->control.vif = vif;\n+\tinfo->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT |\n+\t\t       IEEE80211_TX_CTL_ASSIGN_SEQ |\n+\t\t       IEEE80211_TX_CTL_FIRST_FRAGMENT;\n+}\n+\n+static struct sk_buff *\n+ieee80211_beacon_get_ap(struct ieee80211_hw *hw,\n+\t\t\tstruct ieee80211_vif *vif,\n+\t\t\tstruct ieee80211_mutable_offsets *offs,\n+\t\t\tbool is_template,\n+\t\t\tstruct beacon_data *beacon,\n+\t\t\tstruct ieee80211_chanctx_conf *chanctx_conf)\n+{\n+\tstruct ieee80211_local *local = hw_to_local(hw);\n+\tstruct ieee80211_sub_if_data *sdata = vif_to_sdata(vif);\n+\tstruct ieee80211_if_ap *ap = &sdata->u.ap;\n+\tstruct sk_buff *skb = NULL;\n+\tu16 csa_off_base = 0;\n+\n+\tif (beacon->cntdwn_counter_offsets[0]) {\n+\t\tif (!is_template)\n+\t\t\tieee80211_beacon_update_cntdwn(vif);\n+\n+\t\tieee80211_set_beacon_cntdwn(sdata, beacon);\n+\t}\n+\n+\t/* headroom, head length,\n+\t * tail length and maximum TIM length\n+\t */\n+\tskb = dev_alloc_skb(local->tx_headroom + beacon->head_len +\n+\t\t\t    beacon->tail_len + 256 +\n+\t\t\t    local->hw.extra_beacon_tailroom);\n+\tif (!skb)\n+\t\treturn NULL;\n+\n+\tskb_reserve(skb, local->tx_headroom);\n+\tskb_put_data(skb, beacon->head, beacon->head_len);\n+\n+\tieee80211_beacon_add_tim(sdata, &ap->ps, skb, is_template);\n+\n+\tif (offs) {\n+\t\toffs->tim_offset = beacon->head_len;\n+\t\toffs->tim_length = skb->len - beacon->head_len;\n+\t\toffs->cntdwn_counter_offs[0] = beacon->cntdwn_counter_offsets[0];\n+\n+\t\t/* for AP the csa offsets are from tail */\n+\t\tcsa_off_base = skb->len;\n+\t}\n+\n+\tif (beacon->tail)\n+\t\tskb_put_data(skb, beacon->tail, beacon->tail_len);\n+\n+\tif (ieee80211_beacon_protect(skb, local, sdata) < 0)\n+\t\treturn NULL;\n+\n+\tieee80211_beacon_get_finish(hw, vif, offs, beacon, skb, chanctx_conf,\n+\t\t\t\t    csa_off_base);\n+\treturn skb;\n+}\n+\n static struct sk_buff *\n __ieee80211_beacon_get(struct ieee80211_hw *hw,\n \t\t       struct ieee80211_vif *vif,\n@@ -4996,12 +5105,8 @@ __ieee80211_beacon_get(struct ieee80211_\n \tstruct ieee80211_local *local = hw_to_local(hw);\n \tstruct beacon_data *beacon = NULL;\n \tstruct sk_buff *skb = NULL;\n-\tstruct ieee80211_tx_info *info;\n \tstruct ieee80211_sub_if_data *sdata = NULL;\n-\tenum nl80211_band band;\n-\tstruct ieee80211_tx_rate_control txrc;\n \tstruct ieee80211_chanctx_conf *chanctx_conf;\n-\tint csa_off_base = 0;\n \n \trcu_read_lock();\n \n@@ -5018,48 +5123,11 @@ __ieee80211_beacon_get(struct ieee80211_\n \t\tstruct ieee80211_if_ap *ap = &sdata->u.ap;\n \n \t\tbeacon = rcu_dereference(ap->beacon);\n-\t\tif (beacon) {\n-\t\t\tif (beacon->cntdwn_counter_offsets[0]) {\n-\t\t\t\tif (!is_template)\n-\t\t\t\t\tieee80211_beacon_update_cntdwn(vif);\n-\n-\t\t\t\tieee80211_set_beacon_cntdwn(sdata, beacon);\n-\t\t\t}\n-\n-\t\t\t/*\n-\t\t\t * headroom, head length,\n-\t\t\t * tail length and maximum TIM length\n-\t\t\t */\n-\t\t\tskb = dev_alloc_skb(local->tx_headroom +\n-\t\t\t\t\t    beacon->head_len +\n-\t\t\t\t\t    beacon->tail_len + 256 +\n-\t\t\t\t\t    local->hw.extra_beacon_tailroom);\n-\t\t\tif (!skb)\n-\t\t\t\tgoto out;\n-\n-\t\t\tskb_reserve(skb, local->tx_headroom);\n-\t\t\tskb_put_data(skb, beacon->head, beacon->head_len);\n-\n-\t\t\tieee80211_beacon_add_tim(sdata, &ap->ps, skb,\n-\t\t\t\t\t\t is_template);\n-\n-\t\t\tif (offs) {\n-\t\t\t\toffs->tim_offset = beacon->head_len;\n-\t\t\t\toffs->tim_length = skb->len - beacon->head_len;\n-\t\t\t\toffs->cntdwn_counter_offs[0] = beacon->cntdwn_counter_offsets[0];\n-\n-\t\t\t\t/* for AP the csa offsets are from tail */\n-\t\t\t\tcsa_off_base = skb->len;\n-\t\t\t}\n-\n-\t\t\tif (beacon->tail)\n-\t\t\t\tskb_put_data(skb, beacon->tail,\n-\t\t\t\t\t     beacon->tail_len);\n-\n-\t\t\tif (ieee80211_beacon_protect(skb, local, sdata) < 0)\n-\t\t\t\tgoto out;\n-\t\t} else\n+\t\tif (!beacon)\n \t\t\tgoto out;\n+\n+\t\tskb = ieee80211_beacon_get_ap(hw, vif, offs, is_template,\n+\t\t\t\t\t      beacon, chanctx_conf);\n \t} else if (sdata->vif.type == NL80211_IFTYPE_ADHOC) {\n \t\tstruct ieee80211_if_ibss *ifibss = &sdata->u.ibss;\n \t\tstruct ieee80211_hdr *hdr;\n@@ -5085,6 +5153,9 @@ __ieee80211_beacon_get(struct ieee80211_\n \t\thdr = (struct ieee80211_hdr *) skb->data;\n \t\thdr->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT |\n \t\t\t\t\t\t IEEE80211_STYPE_BEACON);\n+\n+\t\tieee80211_beacon_get_finish(hw, vif, offs, beacon, skb,\n+\t\t\t\t\t    chanctx_conf, 0);\n \t} else if (ieee80211_vif_is_mesh(&sdata->vif)) {\n \t\tstruct ieee80211_if_mesh *ifmsh = &sdata->u.mesh;\n \n@@ -5124,51 +5195,13 @@ __ieee80211_beacon_get(struct ieee80211_\n \t\t}\n \n \t\tskb_put_data(skb, beacon->tail, beacon->tail_len);\n+\t\tieee80211_beacon_get_finish(hw, vif, offs, beacon, skb,\n+\t\t\t\t\t    chanctx_conf, 0);\n \t} else {\n \t\tWARN_ON(1);\n \t\tgoto out;\n \t}\n \n-\t/* CSA offsets */\n-\tif (offs && beacon) {\n-\t\tint i;\n-\n-\t\tfor (i = 0; i < IEEE80211_MAX_CNTDWN_COUNTERS_NUM; i++) {\n-\t\t\tu16 csa_off = beacon->cntdwn_counter_offsets[i];\n-\n-\t\t\tif (!csa_off)\n-\t\t\t\tcontinue;\n-\n-\t\t\toffs->cntdwn_counter_offs[i] = csa_off_base + csa_off;\n-\t\t}\n-\t}\n-\n-\tband = chanctx_conf->def.chan->band;\n-\n-\tinfo = IEEE80211_SKB_CB(skb);\n-\n-\tinfo->flags |= IEEE80211_TX_INTFL_DONT_ENCRYPT;\n-\tinfo->flags |= IEEE80211_TX_CTL_NO_ACK;\n-\tinfo->band = band;\n-\n-\tmemset(&txrc, 0, sizeof(txrc));\n-\ttxrc.hw = hw;\n-\ttxrc.sband = local->hw.wiphy->bands[band];\n-\ttxrc.bss_conf = &sdata->vif.bss_conf;\n-\ttxrc.skb = skb;\n-\ttxrc.reported_rate.idx = -1;\n-\tif (sdata->beacon_rate_set && sdata->beacon_rateidx_mask[band])\n-\t\ttxrc.rate_idx_mask = sdata->beacon_rateidx_mask[band];\n-\telse\n-\t\ttxrc.rate_idx_mask = sdata->rc_rateidx_mask[band];\n-\ttxrc.bss = true;\n-\trate_control_get_rate(sdata, NULL, &txrc);\n-\n-\tinfo->control.vif = vif;\n-\n-\tinfo->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT |\n-\t\t\tIEEE80211_TX_CTL_ASSIGN_SEQ |\n-\t\t\tIEEE80211_TX_CTL_FIRST_FRAGMENT;\n  out:\n \trcu_read_unlock();\n \treturn skb;\n"
  },
  {
    "path": "package/kernel/mac80211/patches/subsys/313-nl80211-MBSSID-and-EMA-support-in-AP-mode.patch",
    "content": "From: John Crispin <john@phrozen.org>\nDate: Wed, 15 Sep 2021 19:54:34 -0700\nSubject: [PATCH] nl80211: MBSSID and EMA support in AP mode\n\nAdd new attributes to configure support for multiple BSSID\nand advanced multi-BSSID advertisements (EMA) in AP mode.\n\n- NL80211_ATTR_MBSSID_CONFIG used for per interface configuration.\n- NL80211_ATTR_MBSSID_ELEMS used to MBSSID elements for beacons.\n\nMemory for the elements is allocated dynamically. This change frees\nthe memory in existing functions which call nl80211_parse_beacon(),\na comment is added to indicate the new references to do the same.\n\nSigned-off-by: John Crispin <john@phrozen.org>\nCo-developed-by: Aloka Dixit <alokad@codeaurora.org>\nSigned-off-by: Aloka Dixit <alokad@codeaurora.org>\nLink: https://lore.kernel.org/r/20210916025437.29138-2-alokad@codeaurora.org\n[don't leave ERR_PTR hanging around]\nSigned-off-by: Johannes Berg <johannes.berg@intel.com>\n---\n\n--- a/include/net/cfg80211.h\n+++ b/include/net/cfg80211.h\n@@ -1046,6 +1046,36 @@ struct cfg80211_crypto_settings {\n };\n \n /**\n+ * struct cfg80211_mbssid_config - AP settings for multi bssid\n+ *\n+ * @tx_wdev: pointer to the transmitted interface in the MBSSID set\n+ * @index: index of this AP in the multi bssid group.\n+ * @ema: set to true if the beacons should be sent out in EMA mode.\n+ */\n+struct cfg80211_mbssid_config {\n+\tstruct wireless_dev *tx_wdev;\n+\tu8 index;\n+\tbool ema;\n+};\n+\n+/**\n+ * struct cfg80211_mbssid_elems - Multiple BSSID elements\n+ *\n+ * @cnt: Number of elements in array %elems.\n+ *\n+ * @elem: Array of multiple BSSID element(s) to be added into Beacon frames.\n+ * @elem.data: Data for multiple BSSID elements.\n+ * @elem.len: Length of data.\n+ */\n+struct cfg80211_mbssid_elems {\n+\tu8 cnt;\n+\tstruct {\n+\t\tconst u8 *data;\n+\t\tsize_t len;\n+\t} elem[];\n+};\n+\n+/**\n  * struct cfg80211_beacon_data - beacon data\n  * @head: head portion of beacon (before TIM IE)\n  *\tor %NULL if not changed\n@@ -1063,6 +1093,7 @@ struct cfg80211_crypto_settings {\n  * @assocresp_ies_len: length of assocresp_ies in octets\n  * @probe_resp_len: length of probe response template (@probe_resp)\n  * @probe_resp: probe response template (AP mode only)\n+ * @mbssid_ies: multiple BSSID elements\n  * @ftm_responder: enable FTM responder functionality; -1 for no change\n  *\t(which also implies no change in LCI/civic location data)\n  * @lci: Measurement Report element content, starting with Measurement Token\n@@ -1080,6 +1111,7 @@ struct cfg80211_beacon_data {\n \tconst u8 *probe_resp;\n \tconst u8 *lci;\n \tconst u8 *civicloc;\n+\tstruct cfg80211_mbssid_elems *mbssid_ies;\n \ts8 ftm_responder;\n \n \tsize_t head_len, tail_len;\n@@ -1194,6 +1226,7 @@ enum cfg80211_ap_settings_flags {\n  * @he_oper: HE operation IE (or %NULL if HE isn't enabled)\n  * @fils_discovery: FILS discovery transmission parameters\n  * @unsol_bcast_probe_resp: Unsolicited broadcast probe response parameters\n+ * @mbssid_config: AP settings for multiple bssid\n  */\n struct cfg80211_ap_settings {\n \tstruct cfg80211_chan_def chandef;\n@@ -1226,6 +1259,7 @@ struct cfg80211_ap_settings {\n \tstruct cfg80211_he_bss_color he_bss_color;\n \tstruct cfg80211_fils_discovery fils_discovery;\n \tstruct cfg80211_unsol_bcast_probe_resp unsol_bcast_probe_resp;\n+\tstruct cfg80211_mbssid_config mbssid_config;\n };\n \n /**\n@@ -4986,6 +5020,13 @@ struct wiphy_iftype_akm_suites {\n  *\t%NL80211_TID_CONFIG_ATTR_RETRY_LONG attributes\n  * @sar_capa: SAR control capabilities\n  * @rfkill: a pointer to the rfkill structure\n+ *\n+ * @mbssid_max_interfaces: maximum number of interfaces supported by the driver\n+ *\tin a multiple BSSID set. This field must be set to a non-zero value\n+ *\tby the driver to advertise MBSSID support.\n+ * @mbssid_max_ema_profile_periodicity: maximum profile periodicity supported by\n+ *\tthe driver. Setting this field to a non-zero value indicates that the\n+ *\tdriver supports enhanced multi-BSSID advertisements (EMA AP).\n  */\n struct wiphy {\n \tstruct mutex mtx;\n@@ -5133,6 +5174,9 @@ struct wiphy {\n \n \tstruct rfkill *rfkill;\n \n+\tu8 mbssid_max_interfaces;\n+\tu8 ema_max_profile_periodicity;\n+\n \tchar priv[] __aligned(NETDEV_ALIGN);\n };\n \n--- a/include/uapi/linux/nl80211.h\n+++ b/include/uapi/linux/nl80211.h\n@@ -337,7 +337,10 @@\n  * @NL80211_CMD_DEL_INTERFACE: Virtual interface was deleted, has attributes\n  *\t%NL80211_ATTR_IFINDEX and %NL80211_ATTR_WIPHY. Can also be sent from\n  *\tuserspace to request deletion of a virtual interface, then requires\n- *\tattribute %NL80211_ATTR_IFINDEX.\n+ *\tattribute %NL80211_ATTR_IFINDEX. If multiple BSSID advertisements are\n+ *\tenabled using %NL80211_ATTR_MBSSID_CONFIG, %NL80211_ATTR_MBSSID_ELEMS,\n+ *\tand if this command is used for the transmitting interface, then all\n+ *\tthe non-transmitting interfaces are deleted as well.\n  *\n  * @NL80211_CMD_GET_KEY: Get sequence counter information for a key specified\n  *\tby %NL80211_ATTR_KEY_IDX and/or %NL80211_ATTR_MAC.\n@@ -2593,6 +2596,18 @@ enum nl80211_commands {\n  * @NL80211_ATTR_COLOR_CHANGE_ELEMS: Nested set of attributes containing the IE\n  *\tinformation for the time while performing a color switch.\n  *\n+ * @NL80211_ATTR_MBSSID_CONFIG: Nested attribute for multiple BSSID\n+ *\tadvertisements (MBSSID) parameters in AP mode.\n+ *\tKernel uses this attribute to indicate the driver's support for MBSSID\n+ *\tand enhanced multi-BSSID advertisements (EMA AP) to the userspace.\n+ *\tUserspace should use this attribute to configure per interface MBSSID\n+ *\tparameters.\n+ *\tSee &enum nl80211_mbssid_config_attributes for details.\n+ *\n+ * @NL80211_ATTR_MBSSID_ELEMS: Nested parameter to pass multiple BSSID elements.\n+ *\tMandatory parameter for the transmitting interface to enable MBSSID.\n+ *\tOptional for the non-transmitting interfaces.\n+ *\n  * @NUM_NL80211_ATTR: total number of nl80211_attrs available\n  * @NL80211_ATTR_MAX: highest attribute number currently defined\n  * @__NL80211_ATTR_AFTER_LAST: internal use\n@@ -3096,6 +3111,9 @@ enum nl80211_attrs {\n \tNL80211_ATTR_COLOR_CHANGE_COLOR,\n \tNL80211_ATTR_COLOR_CHANGE_ELEMS,\n \n+\tNL80211_ATTR_MBSSID_CONFIG,\n+\tNL80211_ATTR_MBSSID_ELEMS,\n+\n \t/* add attributes here, update the policy in nl80211.c */\n \n \t__NL80211_ATTR_AFTER_LAST,\n@@ -7349,4 +7367,60 @@ enum nl80211_sar_specs_attrs {\n \tNL80211_SAR_ATTR_SPECS_MAX = __NL80211_SAR_ATTR_SPECS_LAST - 1,\n };\n \n+/**\n+ * enum nl80211_mbssid_config_attributes - multiple BSSID (MBSSID) and enhanced\n+ * multi-BSSID advertisements (EMA) in AP mode.\n+ * Kernel uses some of these attributes to advertise driver's support for\n+ * MBSSID and EMA.\n+ * Remaining attributes should be used by the userspace to configure the\n+ * features.\n+ *\n+ * @__NL80211_MBSSID_CONFIG_ATTR_INVALID: Invalid\n+ *\n+ * @NL80211_MBSSID_CONFIG_ATTR_MAX_INTERFACES: Used by the kernel to advertise\n+ *\tthe maximum number of MBSSID interfaces supported by the driver.\n+ *\tDriver should indicate MBSSID support by setting\n+ *\twiphy->mbssid_max_interfaces to a value more than or equal to 2.\n+ *\n+ * @NL80211_MBSSID_CONFIG_ATTR_MAX_EMA_PROFILE_PERIODICITY: Used by the kernel\n+ *\tto advertise the maximum profile periodicity supported by the driver\n+ *\tif EMA is enabled. Driver should indicate EMA support to the userspace\n+ *\tby setting wiphy->mbssid_max_ema_profile_periodicity to\n+ *\ta non-zero value.\n+ *\n+ * @NL80211_MBSSID_CONFIG_ATTR_INDEX: Mandatory parameter to pass the index of\n+ *\tthis BSS (u8) in the multiple BSSID set.\n+ *\tValue must be set to 0 for the transmitting interface and non-zero for\n+ *\tall non-transmitting interfaces. The userspace will be responsible\n+ *\tfor using unique indices for the interfaces.\n+ *\tRange: 0 to wiphy->mbssid_max_interfaces-1.\n+ *\n+ * @NL80211_MBSSID_CONFIG_ATTR_TX_IFINDEX: Mandatory parameter for\n+ *\ta non-transmitted profile which provides the interface index (u32) of\n+ *\tthe transmitted profile. The value must match one of the interface\n+ *\tindices advertised by the kernel. Optional if the interface being set up\n+ *\tis the transmitting one, however, if provided then the value must match\n+ *\tthe interface index of the same.\n+ *\n+ * @NL80211_MBSSID_CONFIG_ATTR_EMA: Flag used to enable EMA AP feature.\n+ *\tSetting this flag is permitted only if the driver advertises EMA support\n+ *\tby setting wiphy->mbssid_max_ema_profile_periodicity to non-zero.\n+ *\n+ * @__NL80211_MBSSID_CONFIG_ATTR_LAST: Internal\n+ * @NL80211_MBSSID_CONFIG_ATTR_MAX: highest attribute\n+ */\n+enum nl80211_mbssid_config_attributes {\n+\t__NL80211_MBSSID_CONFIG_ATTR_INVALID,\n+\n+\tNL80211_MBSSID_CONFIG_ATTR_MAX_INTERFACES,\n+\tNL80211_MBSSID_CONFIG_ATTR_MAX_EMA_PROFILE_PERIODICITY,\n+\tNL80211_MBSSID_CONFIG_ATTR_INDEX,\n+\tNL80211_MBSSID_CONFIG_ATTR_TX_IFINDEX,\n+\tNL80211_MBSSID_CONFIG_ATTR_EMA,\n+\n+\t/* keep last */\n+\t__NL80211_MBSSID_CONFIG_ATTR_LAST,\n+\tNL80211_MBSSID_CONFIG_ATTR_MAX = __NL80211_MBSSID_CONFIG_ATTR_LAST - 1,\n+};\n+\n #endif /* __LINUX_NL80211_H */\n--- a/net/wireless/nl80211.c\n+++ b/net/wireless/nl80211.c\n@@ -442,6 +442,16 @@ sar_policy[NL80211_SAR_ATTR_MAX + 1] = {\n \t[NL80211_SAR_ATTR_SPECS] = NLA_POLICY_NESTED_ARRAY(sar_specs_policy),\n };\n \n+static const struct nla_policy\n+nl80211_mbssid_config_policy[NL80211_MBSSID_CONFIG_ATTR_MAX + 1] = {\n+\t[NL80211_MBSSID_CONFIG_ATTR_MAX_INTERFACES] = NLA_POLICY_MIN(NLA_U8, 2),\n+\t[NL80211_MBSSID_CONFIG_ATTR_MAX_EMA_PROFILE_PERIODICITY] =\n+\t\t\t\t\t\tNLA_POLICY_MIN(NLA_U8, 1),\n+\t[NL80211_MBSSID_CONFIG_ATTR_INDEX] = { .type = NLA_U8 },\n+\t[NL80211_MBSSID_CONFIG_ATTR_TX_IFINDEX] = { .type = NLA_U32 },\n+\t[NL80211_MBSSID_CONFIG_ATTR_EMA] = { .type = NLA_FLAG },\n+};\n+\n static const struct nla_policy nl80211_policy[NUM_NL80211_ATTR] = {\n \t[0] = { .strict_start_type = NL80211_ATTR_HE_OBSS_PD },\n \t[NL80211_ATTR_WIPHY] = { .type = NLA_U32 },\n@@ -783,6 +793,9 @@ static const struct nla_policy nl80211_p\n \t[NL80211_ATTR_COLOR_CHANGE_COUNT] = { .type = NLA_U8 },\n \t[NL80211_ATTR_COLOR_CHANGE_COLOR] = { .type = NLA_U8 },\n \t[NL80211_ATTR_COLOR_CHANGE_ELEMS] = NLA_POLICY_NESTED(nl80211_policy),\n+\t[NL80211_ATTR_MBSSID_CONFIG] =\n+\t\t\tNLA_POLICY_NESTED(nl80211_mbssid_config_policy),\n+\t[NL80211_ATTR_MBSSID_ELEMS] = { .type = NLA_NESTED },\n };\n \n /* policy for the key attributes */\n@@ -2231,6 +2244,35 @@ fail:\n \treturn -ENOBUFS;\n }\n \n+static int nl80211_put_mbssid_support(struct wiphy *wiphy, struct sk_buff *msg)\n+{\n+\tstruct nlattr *config;\n+\n+\tif (!wiphy->mbssid_max_interfaces)\n+\t\treturn 0;\n+\n+\tconfig = nla_nest_start(msg, NL80211_ATTR_MBSSID_CONFIG);\n+\tif (!config)\n+\t\treturn -ENOBUFS;\n+\n+\tif (nla_put_u8(msg, NL80211_MBSSID_CONFIG_ATTR_MAX_INTERFACES,\n+\t\t       wiphy->mbssid_max_interfaces))\n+\t\tgoto fail;\n+\n+\tif (wiphy->ema_max_profile_periodicity &&\n+\t    nla_put_u8(msg,\n+\t\t       NL80211_MBSSID_CONFIG_ATTR_MAX_EMA_PROFILE_PERIODICITY,\n+\t\t       wiphy->ema_max_profile_periodicity))\n+\t\tgoto fail;\n+\n+\tnla_nest_end(msg, config);\n+\treturn 0;\n+\n+fail:\n+\tnla_nest_cancel(msg, config);\n+\treturn -ENOBUFS;\n+}\n+\n struct nl80211_dump_wiphy_state {\n \ts64 filter_wiphy;\n \tlong start;\n@@ -2816,6 +2858,9 @@ static int nl80211_send_wiphy(struct cfg\n \t\tif (nl80211_put_sar_specs(rdev, msg))\n \t\t\tgoto nla_put_failure;\n \n+\t\tif (nl80211_put_mbssid_support(&rdev->wiphy, msg))\n+\t\t\tgoto nla_put_failure;\n+\n \t\t/* done */\n \t\tstate->split_start = 0;\n \t\tbreak;\n@@ -5005,6 +5050,96 @@ static int validate_beacon_tx_rate(struc\n \treturn 0;\n }\n \n+static int nl80211_parse_mbssid_config(struct wiphy *wiphy,\n+\t\t\t\t       struct net_device *dev,\n+\t\t\t\t       struct nlattr *attrs,\n+\t\t\t\t       struct cfg80211_mbssid_config *config,\n+\t\t\t\t       u8 num_elems)\n+{\n+\tstruct nlattr *tb[NL80211_MBSSID_CONFIG_ATTR_MAX + 1];\n+\n+\tif (!wiphy->mbssid_max_interfaces)\n+\t\treturn -EOPNOTSUPP;\n+\n+\tif (nla_parse_nested(tb, NL80211_MBSSID_CONFIG_ATTR_MAX, attrs, NULL,\n+\t\t\t     NULL) ||\n+\t    !tb[NL80211_MBSSID_CONFIG_ATTR_INDEX])\n+\t\treturn -EINVAL;\n+\n+\tconfig->ema = nla_get_flag(tb[NL80211_MBSSID_CONFIG_ATTR_EMA]);\n+\tif (config->ema) {\n+\t\tif (!wiphy->ema_max_profile_periodicity)\n+\t\t\treturn -EOPNOTSUPP;\n+\n+\t\tif (num_elems > wiphy->ema_max_profile_periodicity)\n+\t\t\treturn -EINVAL;\n+\t}\n+\n+\tconfig->index = nla_get_u8(tb[NL80211_MBSSID_CONFIG_ATTR_INDEX]);\n+\tif (config->index >= wiphy->mbssid_max_interfaces ||\n+\t    (!config->index && !num_elems))\n+\t\treturn -EINVAL;\n+\n+\tif (tb[NL80211_MBSSID_CONFIG_ATTR_TX_IFINDEX]) {\n+\t\tu32 tx_ifindex =\n+\t\t\tnla_get_u32(tb[NL80211_MBSSID_CONFIG_ATTR_TX_IFINDEX]);\n+\n+\t\tif ((!config->index && tx_ifindex != dev->ifindex) ||\n+\t\t    (config->index && tx_ifindex == dev->ifindex))\n+\t\t\treturn -EINVAL;\n+\n+\t\tif (tx_ifindex != dev->ifindex) {\n+\t\t\tstruct net_device *tx_netdev =\n+\t\t\t\tdev_get_by_index(wiphy_net(wiphy), tx_ifindex);\n+\n+\t\t\tif (!tx_netdev || !tx_netdev->ieee80211_ptr ||\n+\t\t\t    tx_netdev->ieee80211_ptr->wiphy != wiphy ||\n+\t\t\t    tx_netdev->ieee80211_ptr->iftype !=\n+\t\t\t\t\t\t\tNL80211_IFTYPE_AP) {\n+\t\t\t\tdev_put(tx_netdev);\n+\t\t\t\treturn -EINVAL;\n+\t\t\t}\n+\n+\t\t\tconfig->tx_wdev = tx_netdev->ieee80211_ptr;\n+\t\t} else {\n+\t\t\tconfig->tx_wdev = dev->ieee80211_ptr;\n+\t\t}\n+\t} else if (!config->index) {\n+\t\tconfig->tx_wdev = dev->ieee80211_ptr;\n+\t} else {\n+\t\treturn -EINVAL;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static struct cfg80211_mbssid_elems *\n+nl80211_parse_mbssid_elems(struct wiphy *wiphy, struct nlattr *attrs)\n+{\n+\tstruct nlattr *nl_elems;\n+\tstruct cfg80211_mbssid_elems *elems;\n+\tint rem_elems;\n+\tu8 i = 0, num_elems = 0;\n+\n+\tif (!wiphy->mbssid_max_interfaces)\n+\t\treturn ERR_PTR(-EINVAL);\n+\n+\tnla_for_each_nested(nl_elems, attrs, rem_elems)\n+\t\tnum_elems++;\n+\n+\telems = kzalloc(struct_size(elems, elem, num_elems), GFP_KERNEL);\n+\tif (!elems)\n+\t\treturn ERR_PTR(-ENOMEM);\n+\n+\tnla_for_each_nested(nl_elems, attrs, rem_elems) {\n+\t\telems->elem[i].data = nla_data(nl_elems);\n+\t\telems->elem[i].len = nla_len(nl_elems);\n+\t\ti++;\n+\t}\n+\telems->cnt = num_elems;\n+\treturn elems;\n+}\n+\n static int nl80211_parse_beacon(struct cfg80211_registered_device *rdev,\n \t\t\t\tstruct nlattr *attrs[],\n \t\t\t\tstruct cfg80211_beacon_data *bcn)\n@@ -5085,6 +5220,17 @@ static int nl80211_parse_beacon(struct c\n \t\tbcn->ftm_responder = -1;\n \t}\n \n+\tif (attrs[NL80211_ATTR_MBSSID_ELEMS]) {\n+\t\tstruct cfg80211_mbssid_elems *mbssid =\n+\t\t\tnl80211_parse_mbssid_elems(&rdev->wiphy,\n+\t\t\t\t\t\t   attrs[NL80211_ATTR_MBSSID_ELEMS]);\n+\n+\t\tif (IS_ERR(mbssid))\n+\t\t\treturn PTR_ERR(mbssid);\n+\n+\t\tbcn->mbssid_ies = mbssid;\n+\t}\n+\n \treturn 0;\n }\n \n@@ -5541,6 +5687,17 @@ static int nl80211_start_ap(struct sk_bu\n \t\t\tgoto out;\n \t}\n \n+\tif (info->attrs[NL80211_ATTR_MBSSID_CONFIG]) {\n+\t\terr = nl80211_parse_mbssid_config(&rdev->wiphy, dev,\n+\t\t\t\t\t\t  info->attrs[NL80211_ATTR_MBSSID_CONFIG],\n+\t\t\t\t\t\t  &params.mbssid_config,\n+\t\t\t\t\t\t  params.beacon.mbssid_ies ?\n+\t\t\t\t\t\t\tparams.beacon.mbssid_ies->cnt :\n+\t\t\t\t\t\t\t0);\n+\t\tif (err)\n+\t\t\tgoto out;\n+\t}\n+\n \tnl80211_calculate_ap_params(&params);\n \n \tif (info->attrs[NL80211_ATTR_EXTERNAL_AUTH_SUPPORT])\n@@ -5562,6 +5719,11 @@ static int nl80211_start_ap(struct sk_bu\n \n out:\n \tkfree(params.acl);\n+\tkfree(params.beacon.mbssid_ies);\n+\tif (params.mbssid_config.tx_wdev &&\n+\t    params.mbssid_config.tx_wdev->netdev &&\n+\t    params.mbssid_config.tx_wdev->netdev != dev)\n+\t\tdev_put(params.mbssid_config.tx_wdev->netdev);\n \n \treturn err;\n }\n@@ -5586,12 +5748,14 @@ static int nl80211_set_beacon(struct sk_\n \n \terr = nl80211_parse_beacon(rdev, info->attrs, &params);\n \tif (err)\n-\t\treturn err;\n+\t\tgoto out;\n \n \twdev_lock(wdev);\n \terr = rdev_change_beacon(rdev, dev, &params);\n \twdev_unlock(wdev);\n \n+out:\n+\tkfree(params.mbssid_ies);\n \treturn err;\n }\n \n@@ -9268,12 +9432,14 @@ static int nl80211_channel_switch(struct\n \n \terr = nl80211_parse_beacon(rdev, info->attrs, &params.beacon_after);\n \tif (err)\n-\t\treturn err;\n+\t\tgoto free;\n \n \tcsa_attrs = kcalloc(NL80211_ATTR_MAX + 1, sizeof(*csa_attrs),\n \t\t\t    GFP_KERNEL);\n-\tif (!csa_attrs)\n-\t\treturn -ENOMEM;\n+\tif (!csa_attrs) {\n+\t\terr = -ENOMEM;\n+\t\tgoto free;\n+\t}\n \n \terr = nla_parse_nested_deprecated(csa_attrs, NL80211_ATTR_MAX,\n \t\t\t\t\t  info->attrs[NL80211_ATTR_CSA_IES],\n@@ -9392,6 +9558,8 @@ skip_beacons:\n \twdev_unlock(wdev);\n \n free:\n+\tkfree(params.beacon_after.mbssid_ies);\n+\tkfree(params.beacon_csa.mbssid_ies);\n \tkfree(csa_attrs);\n \treturn err;\n }\n@@ -14939,6 +15107,8 @@ static int nl80211_color_change(struct s\n \twdev_unlock(wdev);\n \n out:\n+\tkfree(params.beacon_next.mbssid_ies);\n+\tkfree(params.beacon_color_change.mbssid_ies);\n \tkfree(tb);\n \treturn err;\n }\n"
  },
  {
    "path": "package/kernel/mac80211/patches/subsys/314-cfg80211-implement-APIs-for-dedicated-radar-detectio.patch",
    "content": "From: Lorenzo Bianconi <lorenzo@kernel.org>\nDate: Sat, 23 Oct 2021 11:10:50 +0200\nSubject: [PATCH] cfg80211: implement APIs for dedicated radar detection HW\n\nIf a dedicated (off-channel) radar detection hardware (chain)\nis available in the hardware/driver, allow this to be used by\ncalling the NL80211_CMD_RADAR_DETECT command with a new flag\nattribute requesting off-channel radar detection is used.\n\nOffchannel CAC (channel availability check) avoids the CAC\ndowntime when switching to a radar channel or when turning on\nthe AP.\n\nDrivers advertise support for this using the new feature flag\nNL80211_EXT_FEATURE_RADAR_OFFCHAN.\n\nTested-by: Evelyn Tsai <evelyn.tsai@mediatek.com>\nSigned-off-by: Lorenzo Bianconi <lorenzo@kernel.org>\nLink: https://lore.kernel.org/r/7468e291ef5d05d692c1738d25b8f778d8ea5c3f.1634979655.git.lorenzo@kernel.org\nLink: https://lore.kernel.org/r/1e60e60fef00e14401adae81c3d49f3e5f307537.1634979655.git.lorenzo@kernel.org\nLink: https://lore.kernel.org/r/85fa50f57fc3adb2934c8d9ca0be30394de6b7e8.1634979655.git.lorenzo@kernel.org\nLink: https://lore.kernel.org/r/4b6c08671ad59aae0ac46fc94c02f31b1610eb72.1634979655.git.lorenzo@kernel.org\nLink: https://lore.kernel.org/r/241849ccaf2c228873c6f8495bf87b19159ba458.1634979655.git.lorenzo@kernel.org\n[remove offchan_mutex, fix cfg80211_stop_offchan_radar_detection(),\n remove gfp_t argument, fix documentation, fix tracing]\nSigned-off-by: Johannes Berg <johannes.berg@intel.com>\n---\n\n--- a/include/net/cfg80211.h\n+++ b/include/net/cfg80211.h\n@@ -4057,6 +4057,15 @@ struct mgmt_frame_regs {\n  * @set_sar_specs: Update the SAR (TX power) settings.\n  *\n  * @color_change: Initiate a color change.\n+ *\n+ * @set_radar_offchan: Configure dedicated offchannel chain available for\n+ *\tradar/CAC detection on some hw. This chain can't be used to transmit\n+ *\tor receive frames and it is bounded to a running wdev.\n+ *\tOffchannel radar/CAC detection allows to avoid the CAC downtime\n+ *\tswitching to a different channel during CAC detection on the selected\n+ *\tradar channel.\n+ *\tThe caller is expected to set chandef pointer to NULL in order to\n+ *\tdisable offchannel CAC/radar detection.\n  */\n struct cfg80211_ops {\n \tint\t(*suspend)(struct wiphy *wiphy, struct cfg80211_wowlan *wow);\n@@ -4387,6 +4396,8 @@ struct cfg80211_ops {\n \tint\t(*color_change)(struct wiphy *wiphy,\n \t\t\t\tstruct net_device *dev,\n \t\t\t\tstruct cfg80211_color_change_settings *params);\n+\tint\t(*set_radar_offchan)(struct wiphy *wiphy,\n+\t\t\t\t     struct cfg80211_chan_def *chandef);\n };\n \n /*\n@@ -7608,6 +7619,20 @@ void cfg80211_cac_event(struct net_devic\n \t\t\tconst struct cfg80211_chan_def *chandef,\n \t\t\tenum nl80211_radar_event event, gfp_t gfp);\n \n+/**\n+ * cfg80211_offchan_cac_event - Channel Availability Check (CAC) offchan event\n+ * @wiphy: the wiphy\n+ * @chandef: chandef for the current channel\n+ * @event: type of event\n+ *\n+ * This function is called when a Channel Availability Check (CAC) is finished,\n+ * started or aborted by a offchannel dedicated chain.\n+ *\n+ * Note that this acquires the wiphy lock.\n+ */\n+void cfg80211_offchan_cac_event(struct wiphy *wiphy,\n+\t\t\t\tconst struct cfg80211_chan_def *chandef,\n+\t\t\t\tenum nl80211_radar_event event);\n \n /**\n  * cfg80211_gtk_rekey_notify - notify userspace about driver rekeying\n--- a/include/uapi/linux/nl80211.h\n+++ b/include/uapi/linux/nl80211.h\n@@ -2608,6 +2608,13 @@ enum nl80211_commands {\n  *\tMandatory parameter for the transmitting interface to enable MBSSID.\n  *\tOptional for the non-transmitting interfaces.\n  *\n+ * @NL80211_ATTR_RADAR_OFFCHAN: Configure dedicated offchannel chain available for\n+ *\tradar/CAC detection on some hw. This chain can't be used to transmit\n+ *\tor receive frames and it is bounded to a running wdev.\n+ *\tOffchannel radar/CAC detection allows to avoid the CAC downtime\n+ *\tswitching on a different channel during CAC detection on the selected\n+ *\tradar channel.\n+ *\n  * @NUM_NL80211_ATTR: total number of nl80211_attrs available\n  * @NL80211_ATTR_MAX: highest attribute number currently defined\n  * @__NL80211_ATTR_AFTER_LAST: internal use\n@@ -3114,6 +3121,8 @@ enum nl80211_attrs {\n \tNL80211_ATTR_MBSSID_CONFIG,\n \tNL80211_ATTR_MBSSID_ELEMS,\n \n+\tNL80211_ATTR_RADAR_OFFCHAN,\n+\n \t/* add attributes here, update the policy in nl80211.c */\n \n \t__NL80211_ATTR_AFTER_LAST,\n@@ -6013,6 +6022,9 @@ enum nl80211_feature_flags {\n  * @NL80211_EXT_FEATURE_BSS_COLOR: The driver supports BSS color collision\n  *\tdetection and change announcemnts.\n  *\n+ * @NL80211_EXT_FEATURE_RADAR_OFFCHAN: Device supports offchannel radar/CAC\n+ *\tdetection.\n+ *\n  * @NUM_NL80211_EXT_FEATURES: number of extended features.\n  * @MAX_NL80211_EXT_FEATURES: highest extended feature index.\n  */\n@@ -6078,6 +6090,7 @@ enum nl80211_ext_feature_index {\n \tNL80211_EXT_FEATURE_SECURE_RTT,\n \tNL80211_EXT_FEATURE_PROT_RANGE_NEGO_AND_MEASURE,\n \tNL80211_EXT_FEATURE_BSS_COLOR,\n+\tNL80211_EXT_FEATURE_RADAR_OFFCHAN,\n \n \t/* add new features before the definition below */\n \tNUM_NL80211_EXT_FEATURES,\n--- a/net/wireless/core.c\n+++ b/net/wireless/core.c\n@@ -543,6 +543,7 @@ use_default_name:\n \tINIT_WORK(&rdev->rfkill_block, cfg80211_rfkill_block_work);\n \tINIT_WORK(&rdev->conn_work, cfg80211_conn_work);\n \tINIT_WORK(&rdev->event_work, cfg80211_event_work);\n+\tINIT_DELAYED_WORK(&rdev->offchan_cac_work, cfg80211_offchan_cac_work);\n \n \tinit_waitqueue_head(&rdev->dev_wait);\n \n@@ -1205,6 +1206,8 @@ void __cfg80211_leave(struct cfg80211_re\n \n \tcfg80211_pmsr_wdev_down(wdev);\n \n+\tcfg80211_stop_offchan_radar_detection(wdev);\n+\n \tswitch (wdev->iftype) {\n \tcase NL80211_IFTYPE_ADHOC:\n \t\t__cfg80211_leave_ibss(rdev, dev, true);\n--- a/net/wireless/core.h\n+++ b/net/wireless/core.h\n@@ -84,6 +84,10 @@ struct cfg80211_registered_device {\n \n \tstruct delayed_work dfs_update_channels_wk;\n \n+\tstruct wireless_dev *offchan_radar_wdev;\n+\tstruct cfg80211_chan_def offchan_radar_chandef;\n+\tstruct delayed_work offchan_cac_work;\n+\n \t/* netlink port which started critical protocol (0 means not started) */\n \tu32 crit_proto_nlportid;\n \n@@ -491,6 +495,15 @@ cfg80211_chandef_dfs_cac_time(struct wip\n \n void cfg80211_sched_dfs_chan_update(struct cfg80211_registered_device *rdev);\n \n+int\n+cfg80211_start_offchan_radar_detection(struct cfg80211_registered_device *rdev,\n+\t\t\t\t       struct wireless_dev *wdev,\n+\t\t\t\t       struct cfg80211_chan_def *chandef);\n+\n+void cfg80211_stop_offchan_radar_detection(struct wireless_dev *wdev);\n+\n+void cfg80211_offchan_cac_work(struct work_struct *work);\n+\n bool cfg80211_any_wiphy_oper_chan(struct wiphy *wiphy,\n \t\t\t\t  struct ieee80211_channel *chan);\n \n--- a/net/wireless/mlme.c\n+++ b/net/wireless/mlme.c\n@@ -970,3 +970,116 @@ void cfg80211_cac_event(struct net_devic\n \tnl80211_radar_notify(rdev, chandef, event, netdev, gfp);\n }\n EXPORT_SYMBOL(cfg80211_cac_event);\n+\n+void cfg80211_offchan_cac_work(struct work_struct *work)\n+{\n+\tstruct delayed_work *delayed_work = to_delayed_work(work);\n+\tstruct cfg80211_registered_device *rdev;\n+\n+\trdev = container_of(delayed_work, struct cfg80211_registered_device,\n+\t\t\t    offchan_cac_work);\n+\tcfg80211_offchan_cac_event(&rdev->wiphy, &rdev->offchan_radar_chandef,\n+\t\t\t\t   NL80211_RADAR_CAC_FINISHED);\n+}\n+\n+static void\n+__cfg80211_offchan_cac_event(struct cfg80211_registered_device *rdev,\n+\t\t\t     struct wireless_dev *wdev,\n+\t\t\t     const struct cfg80211_chan_def *chandef,\n+\t\t\t     enum nl80211_radar_event event)\n+{\n+\tstruct wiphy *wiphy = &rdev->wiphy;\n+\tstruct net_device *netdev;\n+\n+\tlockdep_assert_wiphy(&rdev->wiphy);\n+\n+\tif (event != NL80211_RADAR_CAC_STARTED && !rdev->offchan_radar_wdev)\n+\t\treturn;\n+\n+\tswitch (event) {\n+\tcase NL80211_RADAR_CAC_FINISHED:\n+\t\tcfg80211_set_dfs_state(wiphy, chandef, NL80211_DFS_AVAILABLE);\n+\t\tmemcpy(&rdev->cac_done_chandef, chandef, sizeof(*chandef));\n+\t\tqueue_work(cfg80211_wq, &rdev->propagate_cac_done_wk);\n+\t\tcfg80211_sched_dfs_chan_update(rdev);\n+\t\twdev = rdev->offchan_radar_wdev;\n+\t\trdev->offchan_radar_wdev = NULL;\n+\t\tbreak;\n+\tcase NL80211_RADAR_CAC_ABORTED:\n+\t\tcancel_delayed_work(&rdev->offchan_cac_work);\n+\t\twdev = rdev->offchan_radar_wdev;\n+\t\trdev->offchan_radar_wdev = NULL;\n+\t\tbreak;\n+\tcase NL80211_RADAR_CAC_STARTED:\n+\t\tWARN_ON(!wdev);\n+\t\trdev->offchan_radar_wdev = wdev;\n+\t\tbreak;\n+\tdefault:\n+\t\treturn;\n+\t}\n+\n+\tnetdev = wdev ? wdev->netdev : NULL;\n+\tnl80211_radar_notify(rdev, chandef, event, netdev, GFP_KERNEL);\n+}\n+\n+void cfg80211_offchan_cac_event(struct wiphy *wiphy,\n+\t\t\t\tconst struct cfg80211_chan_def *chandef,\n+\t\t\t\tenum nl80211_radar_event event)\n+{\n+\tstruct cfg80211_registered_device *rdev = wiphy_to_rdev(wiphy);\n+\n+\twiphy_lock(wiphy);\n+\t__cfg80211_offchan_cac_event(rdev, NULL, chandef, event);\n+\twiphy_unlock(wiphy);\n+}\n+EXPORT_SYMBOL(cfg80211_offchan_cac_event);\n+\n+int\n+cfg80211_start_offchan_radar_detection(struct cfg80211_registered_device *rdev,\n+\t\t\t\t       struct wireless_dev *wdev,\n+\t\t\t\t       struct cfg80211_chan_def *chandef)\n+{\n+\tunsigned int cac_time_ms;\n+\tint err;\n+\n+\tlockdep_assert_wiphy(&rdev->wiphy);\n+\n+\tif (!wiphy_ext_feature_isset(&rdev->wiphy,\n+\t\t\t\t     NL80211_EXT_FEATURE_RADAR_OFFCHAN))\n+\t\treturn -EOPNOTSUPP;\n+\n+\tif (rdev->offchan_radar_wdev)\n+\t\treturn -EBUSY;\n+\n+\terr = rdev_set_radar_offchan(rdev, chandef);\n+\tif (err)\n+\t\treturn err;\n+\n+\tcac_time_ms = cfg80211_chandef_dfs_cac_time(&rdev->wiphy, chandef);\n+\tif (!cac_time_ms)\n+\t\tcac_time_ms = IEEE80211_DFS_MIN_CAC_TIME_MS;\n+\n+\trdev->offchan_radar_chandef = *chandef;\n+\t__cfg80211_offchan_cac_event(rdev, wdev, chandef,\n+\t\t\t\t     NL80211_RADAR_CAC_STARTED);\n+\tqueue_delayed_work(cfg80211_wq, &rdev->offchan_cac_work,\n+\t\t\t   msecs_to_jiffies(cac_time_ms));\n+\n+\treturn 0;\n+}\n+\n+void cfg80211_stop_offchan_radar_detection(struct wireless_dev *wdev)\n+{\n+\tstruct wiphy *wiphy = wdev->wiphy;\n+\tstruct cfg80211_registered_device *rdev = wiphy_to_rdev(wiphy);\n+\n+\tlockdep_assert_wiphy(wiphy);\n+\n+\tif (wdev != rdev->offchan_radar_wdev)\n+\t\treturn;\n+\n+\trdev_set_radar_offchan(rdev, NULL);\n+\n+\t__cfg80211_offchan_cac_event(rdev, NULL, NULL,\n+\t\t\t\t     NL80211_RADAR_CAC_ABORTED);\n+}\n--- a/net/wireless/nl80211.c\n+++ b/net/wireless/nl80211.c\n@@ -796,6 +796,7 @@ static const struct nla_policy nl80211_p\n \t[NL80211_ATTR_MBSSID_CONFIG] =\n \t\t\tNLA_POLICY_NESTED(nl80211_mbssid_config_policy),\n \t[NL80211_ATTR_MBSSID_ELEMS] = { .type = NLA_NESTED },\n+\t[NL80211_ATTR_RADAR_OFFCHAN] = { .type = NLA_FLAG },\n };\n \n /* policy for the key attributes */\n@@ -9272,12 +9273,6 @@ static int nl80211_start_radar_detection\n \tif (err)\n \t\treturn err;\n \n-\tif (netif_carrier_ok(dev))\n-\t\treturn -EBUSY;\n-\n-\tif (wdev->cac_started)\n-\t\treturn -EBUSY;\n-\n \terr = cfg80211_chandef_dfs_required(wiphy, &chandef, wdev->iftype);\n \tif (err < 0)\n \t\treturn err;\n@@ -9288,6 +9283,16 @@ static int nl80211_start_radar_detection\n \tif (!cfg80211_chandef_dfs_usable(wiphy, &chandef))\n \t\treturn -EINVAL;\n \n+\tif (nla_get_flag(info->attrs[NL80211_ATTR_RADAR_OFFCHAN]))\n+\t\treturn cfg80211_start_offchan_radar_detection(rdev, wdev,\n+\t\t\t\t\t\t\t      &chandef);\n+\n+\tif (netif_carrier_ok(dev))\n+\t\treturn -EBUSY;\n+\n+\tif (wdev->cac_started)\n+\t\treturn -EBUSY;\n+\n \t/* CAC start is offloaded to HW and can't be started manually */\n \tif (wiphy_ext_feature_isset(wiphy, NL80211_EXT_FEATURE_DFS_OFFLOAD))\n \t\treturn -EOPNOTSUPP;\n--- a/net/wireless/rdev-ops.h\n+++ b/net/wireless/rdev-ops.h\n@@ -1381,4 +1381,21 @@ static inline int rdev_color_change(stru\n \treturn ret;\n }\n \n+static inline int\n+rdev_set_radar_offchan(struct cfg80211_registered_device *rdev,\n+\t\t       struct cfg80211_chan_def *chandef)\n+{\n+\tstruct wiphy *wiphy = &rdev->wiphy;\n+\tint ret;\n+\n+\tif (!rdev->ops->set_radar_offchan)\n+\t\treturn -EOPNOTSUPP;\n+\n+\ttrace_rdev_set_radar_offchan(wiphy, chandef);\n+\tret = rdev->ops->set_radar_offchan(wiphy, chandef);\n+\ttrace_rdev_return_int(wiphy, ret);\n+\n+\treturn ret;\n+}\n+\n #endif /* __CFG80211_RDEV_OPS */\n--- a/net/wireless/trace.h\n+++ b/net/wireless/trace.h\n@@ -3643,6 +3643,25 @@ TRACE_EVENT(cfg80211_bss_color_notify,\n \t\t  __entry->color_bitmap)\n );\n \n+TRACE_EVENT(rdev_set_radar_offchan,\n+\tTP_PROTO(struct wiphy *wiphy, struct cfg80211_chan_def *chandef),\n+\n+\tTP_ARGS(wiphy, chandef),\n+\n+\tTP_STRUCT__entry(\n+\t\tWIPHY_ENTRY\n+\t\tCHAN_DEF_ENTRY\n+\t),\n+\n+\tTP_fast_assign(\n+\t\tWIPHY_ASSIGN;\n+\t\tCHAN_DEF_ASSIGN(chandef)\n+\t),\n+\n+\tTP_printk(WIPHY_PR_FMT \", \" CHAN_DEF_PR_FMT,\n+\t\t  WIPHY_PR_ARG, CHAN_DEF_PR_ARG)\n+);\n+\n #endif /* !__RDEV_OPS_TRACE || TRACE_HEADER_MULTI_READ */\n \n #undef TRACE_INCLUDE_PATH\n"
  },
  {
    "path": "package/kernel/mac80211/patches/subsys/315-cfg80211-move-offchan_cac_event-to-a-dedicated-work.patch",
    "content": "From: Lorenzo Bianconi <lorenzo@kernel.org>\nDate: Wed, 27 Oct 2021 11:03:42 +0200\nSubject: [PATCH] cfg80211: move offchan_cac_event to a dedicated work\n\nIn order to make cfg80211_offchan_cac_abort() (renamed from\ncfg80211_offchan_cac_event) callable in other contexts and\nwithout so much locking restrictions, make it trigger a new\nwork instead of operating directly.\n\nDo some other renames while at it to clarify.\n\nSigned-off-by: Lorenzo Bianconi <lorenzo@kernel.org>\nLink: https://lore.kernel.org/r/6145c3d0f30400a568023f67981981d24c7c6133.1635325205.git.lorenzo@kernel.org\n[rewrite commit log]\nSigned-off-by: Johannes Berg <johannes.berg@intel.com>\n---\n\n--- a/include/net/cfg80211.h\n+++ b/include/net/cfg80211.h\n@@ -7620,19 +7620,13 @@ void cfg80211_cac_event(struct net_devic\n \t\t\tenum nl80211_radar_event event, gfp_t gfp);\n \n /**\n- * cfg80211_offchan_cac_event - Channel Availability Check (CAC) offchan event\n+ * cfg80211_offchan_cac_abort - Channel Availability Check offchan abort event\n  * @wiphy: the wiphy\n- * @chandef: chandef for the current channel\n- * @event: type of event\n  *\n- * This function is called when a Channel Availability Check (CAC) is finished,\n- * started or aborted by a offchannel dedicated chain.\n- *\n- * Note that this acquires the wiphy lock.\n+ * This function is called by the driver when a Channel Availability Check\n+ * (CAC) is aborted by a offchannel dedicated chain.\n  */\n-void cfg80211_offchan_cac_event(struct wiphy *wiphy,\n-\t\t\t\tconst struct cfg80211_chan_def *chandef,\n-\t\t\t\tenum nl80211_radar_event event);\n+void cfg80211_offchan_cac_abort(struct wiphy *wiphy);\n \n /**\n  * cfg80211_gtk_rekey_notify - notify userspace about driver rekeying\n--- a/net/wireless/core.c\n+++ b/net/wireless/core.c\n@@ -543,7 +543,9 @@ use_default_name:\n \tINIT_WORK(&rdev->rfkill_block, cfg80211_rfkill_block_work);\n \tINIT_WORK(&rdev->conn_work, cfg80211_conn_work);\n \tINIT_WORK(&rdev->event_work, cfg80211_event_work);\n-\tINIT_DELAYED_WORK(&rdev->offchan_cac_work, cfg80211_offchan_cac_work);\n+\tINIT_WORK(&rdev->offchan_cac_abort_wk, cfg80211_offchan_cac_abort_wk);\n+\tINIT_DELAYED_WORK(&rdev->offchan_cac_done_wk,\n+\t\t\t  cfg80211_offchan_cac_done_wk);\n \n \tinit_waitqueue_head(&rdev->dev_wait);\n \n@@ -1053,11 +1055,13 @@ void wiphy_unregister(struct wiphy *wiph\n \tcancel_work_sync(&rdev->conn_work);\n \tflush_work(&rdev->event_work);\n \tcancel_delayed_work_sync(&rdev->dfs_update_channels_wk);\n+\tcancel_delayed_work_sync(&rdev->offchan_cac_done_wk);\n \tflush_work(&rdev->destroy_work);\n \tflush_work(&rdev->sched_scan_stop_wk);\n \tflush_work(&rdev->propagate_radar_detect_wk);\n \tflush_work(&rdev->propagate_cac_done_wk);\n \tflush_work(&rdev->mgmt_registrations_update_wk);\n+\tflush_work(&rdev->offchan_cac_abort_wk);\n \n #ifdef CONFIG_PM\n \tif (rdev->wiphy.wowlan_config && rdev->ops->set_wakeup)\n--- a/net/wireless/core.h\n+++ b/net/wireless/core.h\n@@ -86,7 +86,8 @@ struct cfg80211_registered_device {\n \n \tstruct wireless_dev *offchan_radar_wdev;\n \tstruct cfg80211_chan_def offchan_radar_chandef;\n-\tstruct delayed_work offchan_cac_work;\n+\tstruct delayed_work offchan_cac_done_wk;\n+\tstruct work_struct offchan_cac_abort_wk;\n \n \t/* netlink port which started critical protocol (0 means not started) */\n \tu32 crit_proto_nlportid;\n@@ -502,7 +503,9 @@ cfg80211_start_offchan_radar_detection(s\n \n void cfg80211_stop_offchan_radar_detection(struct wireless_dev *wdev);\n \n-void cfg80211_offchan_cac_work(struct work_struct *work);\n+void cfg80211_offchan_cac_done_wk(struct work_struct *work);\n+\n+void cfg80211_offchan_cac_abort_wk(struct work_struct *work);\n \n bool cfg80211_any_wiphy_oper_chan(struct wiphy *wiphy,\n \t\t\t\t  struct ieee80211_channel *chan);\n--- a/net/wireless/mlme.c\n+++ b/net/wireless/mlme.c\n@@ -971,17 +971,6 @@ void cfg80211_cac_event(struct net_devic\n }\n EXPORT_SYMBOL(cfg80211_cac_event);\n \n-void cfg80211_offchan_cac_work(struct work_struct *work)\n-{\n-\tstruct delayed_work *delayed_work = to_delayed_work(work);\n-\tstruct cfg80211_registered_device *rdev;\n-\n-\trdev = container_of(delayed_work, struct cfg80211_registered_device,\n-\t\t\t    offchan_cac_work);\n-\tcfg80211_offchan_cac_event(&rdev->wiphy, &rdev->offchan_radar_chandef,\n-\t\t\t\t   NL80211_RADAR_CAC_FINISHED);\n-}\n-\n static void\n __cfg80211_offchan_cac_event(struct cfg80211_registered_device *rdev,\n \t\t\t     struct wireless_dev *wdev,\n@@ -1006,7 +995,7 @@ __cfg80211_offchan_cac_event(struct cfg8\n \t\trdev->offchan_radar_wdev = NULL;\n \t\tbreak;\n \tcase NL80211_RADAR_CAC_ABORTED:\n-\t\tcancel_delayed_work(&rdev->offchan_cac_work);\n+\t\tcancel_delayed_work(&rdev->offchan_cac_done_wk);\n \t\twdev = rdev->offchan_radar_wdev;\n \t\trdev->offchan_radar_wdev = NULL;\n \t\tbreak;\n@@ -1022,17 +1011,44 @@ __cfg80211_offchan_cac_event(struct cfg8\n \tnl80211_radar_notify(rdev, chandef, event, netdev, GFP_KERNEL);\n }\n \n-void cfg80211_offchan_cac_event(struct wiphy *wiphy,\n-\t\t\t\tconst struct cfg80211_chan_def *chandef,\n-\t\t\t\tenum nl80211_radar_event event)\n+static void\n+cfg80211_offchan_cac_event(struct cfg80211_registered_device *rdev,\n+\t\t\t   const struct cfg80211_chan_def *chandef,\n+\t\t\t   enum nl80211_radar_event event)\n+{\n+\twiphy_lock(&rdev->wiphy);\n+\t__cfg80211_offchan_cac_event(rdev, NULL, chandef, event);\n+\twiphy_unlock(&rdev->wiphy);\n+}\n+\n+void cfg80211_offchan_cac_done_wk(struct work_struct *work)\n+{\n+\tstruct delayed_work *delayed_work = to_delayed_work(work);\n+\tstruct cfg80211_registered_device *rdev;\n+\n+\trdev = container_of(delayed_work, struct cfg80211_registered_device,\n+\t\t\t    offchan_cac_done_wk);\n+\tcfg80211_offchan_cac_event(rdev, &rdev->offchan_radar_chandef,\n+\t\t\t\t   NL80211_RADAR_CAC_FINISHED);\n+}\n+\n+void cfg80211_offchan_cac_abort_wk(struct work_struct *work)\n+{\n+\tstruct cfg80211_registered_device *rdev;\n+\n+\trdev = container_of(work, struct cfg80211_registered_device,\n+\t\t\t    offchan_cac_abort_wk);\n+\tcfg80211_offchan_cac_event(rdev, &rdev->offchan_radar_chandef,\n+\t\t\t\t   NL80211_RADAR_CAC_ABORTED);\n+}\n+\n+void cfg80211_offchan_cac_abort(struct wiphy *wiphy)\n {\n \tstruct cfg80211_registered_device *rdev = wiphy_to_rdev(wiphy);\n \n-\twiphy_lock(wiphy);\n-\t__cfg80211_offchan_cac_event(rdev, NULL, chandef, event);\n-\twiphy_unlock(wiphy);\n+\tqueue_work(cfg80211_wq, &rdev->offchan_cac_abort_wk);\n }\n-EXPORT_SYMBOL(cfg80211_offchan_cac_event);\n+EXPORT_SYMBOL(cfg80211_offchan_cac_abort);\n \n int\n cfg80211_start_offchan_radar_detection(struct cfg80211_registered_device *rdev,\n@@ -1062,7 +1078,7 @@ cfg80211_start_offchan_radar_detection(s\n \trdev->offchan_radar_chandef = *chandef;\n \t__cfg80211_offchan_cac_event(rdev, wdev, chandef,\n \t\t\t\t     NL80211_RADAR_CAC_STARTED);\n-\tqueue_delayed_work(cfg80211_wq, &rdev->offchan_cac_work,\n+\tqueue_delayed_work(cfg80211_wq, &rdev->offchan_cac_done_wk,\n \t\t\t   msecs_to_jiffies(cac_time_ms));\n \n \treturn 0;\n"
  },
  {
    "path": "package/kernel/mac80211/patches/subsys/316-cfg80211-fix-possible-NULL-pointer-dereference-in-cf.patch",
    "content": "From: Lorenzo Bianconi <lorenzo@kernel.org>\nDate: Wed, 3 Nov 2021 18:02:35 +0100\nSubject: [PATCH] cfg80211: fix possible NULL pointer dereference in\n cfg80211_stop_offchan_radar_detection\n\nFix the following NULL pointer dereference in\ncfg80211_stop_offchan_radar_detection routine that occurs when hostapd\nis stopped during the CAC on offchannel chain:\n\nSat Jan  1 0[  779.567851]   ESR = 0x96000005\n0:12:50 2000 dae[  779.572346]   EC = 0x25: DABT (current EL), IL = 32 bits\nmon.debug hostap[  779.578984]   SET = 0, FnV = 0\nd: hostapd_inter[  779.583445]   EA = 0, S1PTW = 0\nface_deinit_free[  779.587936] Data abort info:\n: num_bss=1 conf[  779.592224]   ISV = 0, ISS = 0x00000005\n->num_bss=1\nSat[  779.597403]   CM = 0, WnR = 0\n Jan  1 00:12:50[  779.601749] user pgtable: 4k pages, 39-bit VAs, pgdp=00000000418b2000\n 2000 daemon.deb[  779.609601] [0000000000000000] pgd=0000000000000000, p4d=0000000000000000, pud=0000000000000000\nug hostapd: host[  779.619657] Internal error: Oops: 96000005 [#1] SMP\n[  779.770810] CPU: 0 PID: 2202 Comm: hostapd Not tainted 5.10.75 #0\n[  779.776892] Hardware name: MediaTek MT7622 RFB1 board (DT)\n[  779.782370] pstate: 80000005 (Nzcv daif -PAN -UAO -TCO BTYPE=--)\n[  779.788384] pc : cfg80211_chandef_valid+0x10/0x490 [cfg80211]\n[  779.794128] lr : cfg80211_check_station_change+0x3190/0x3950 [cfg80211]\n[  779.800731] sp : ffffffc01204b7e0\n[  779.804036] x29: ffffffc01204b7e0 x28: ffffff80039bdc00\n[  779.809340] x27: 0000000000000000 x26: ffffffc008cb3050\n[  779.814644] x25: 0000000000000000 x24: 0000000000000002\n[  779.819948] x23: ffffff8002630000 x22: ffffff8003e748d0\n[  779.825252] x21: 0000000000000cc0 x20: ffffff8003da4a00\n[  779.830556] x19: 0000000000000000 x18: ffffff8001bf7ce0\n[  779.835860] x17: 00000000ffffffff x16: 0000000000000000\n[  779.841164] x15: 0000000040d59200 x14: 00000000000019c0\n[  779.846467] x13: 00000000000001c8 x12: 000636b9e9dab1c6\n[  779.851771] x11: 0000000000000141 x10: 0000000000000820\n[  779.857076] x9 : 0000000000000000 x8 : ffffff8003d7d038\n[  779.862380] x7 : 0000000000000000 x6 : ffffff8003d7d038\n[  779.867683] x5 : 0000000000000e90 x4 : 0000000000000038\n[  779.872987] x3 : 0000000000000002 x2 : 0000000000000004\n[  779.878291] x1 : 0000000000000000 x0 : 0000000000000000\n[  779.883594] Call trace:\n[  779.886039]  cfg80211_chandef_valid+0x10/0x490 [cfg80211]\n[  779.891434]  cfg80211_check_station_change+0x3190/0x3950 [cfg80211]\n[  779.897697]  nl80211_radar_notify+0x138/0x19c [cfg80211]\n[  779.903005]  cfg80211_stop_offchan_radar_detection+0x7c/0x8c [cfg80211]\n[  779.909616]  __cfg80211_leave+0x2c/0x190 [cfg80211]\n[  779.914490]  cfg80211_register_netdevice+0x1c0/0x6d0 [cfg80211]\n[  779.920404]  raw_notifier_call_chain+0x50/0x70\n[  779.924841]  call_netdevice_notifiers_info+0x54/0xa0\n[  779.929796]  __dev_close_many+0x40/0x100\n[  779.933712]  __dev_change_flags+0x98/0x190\n[  779.937800]  dev_change_flags+0x20/0x60\n[  779.941628]  devinet_ioctl+0x534/0x6d0\n[  779.945370]  inet_ioctl+0x1bc/0x230\n[  779.948849]  sock_do_ioctl+0x44/0x200\n[  779.952502]  sock_ioctl+0x268/0x4c0\n[  779.955985]  __arm64_sys_ioctl+0xac/0xd0\n[  779.959900]  el0_svc_common.constprop.0+0x60/0x110\n[  779.964682]  do_el0_svc+0x1c/0x24\n[  779.967990]  el0_svc+0x10/0x1c\n[  779.971036]  el0_sync_handler+0x9c/0x120\n[  779.974950]  el0_sync+0x148/0x180\n[  779.978259] Code: a9bc7bfd 910003fd a90153f3 aa0003f3 (f9400000)\n[  779.984344] ---[ end trace 0e67b4f5d6cdeec7 ]---\n[  779.996400] Kernel panic - not syncing: Oops: Fatal exception\n[  780.002139] SMP: stopping secondary CPUs\n[  780.006057] Kernel Offset: disabled\n[  780.009537] CPU features: 0x0000002,04002004\n[  780.013796] Memory Limit: none\n\nFixes: b8f5facf286b (\"cfg80211: implement APIs for dedicated radar detection HW\")\nReported-by: Evelyn Tsai <evelyn.tsai@mediatek.com>\nTested-by: Evelyn Tsai <evelyn.tsai@mediatek.com>\nSigned-off-by: Lorenzo Bianconi <lorenzo@kernel.org>\nLink: https://lore.kernel.org/r/c2e34c065bf8839c5ffa45498ae154021a72a520.1635958796.git.lorenzo@kernel.org\nSigned-off-by: Johannes Berg <johannes.berg@intel.com>\n---\n\n--- a/net/wireless/mlme.c\n+++ b/net/wireless/mlme.c\n@@ -982,6 +982,9 @@ __cfg80211_offchan_cac_event(struct cfg8\n \n \tlockdep_assert_wiphy(&rdev->wiphy);\n \n+\tif (!cfg80211_chandef_valid(chandef))\n+\t\treturn;\n+\n \tif (event != NL80211_RADAR_CAC_STARTED && !rdev->offchan_radar_wdev)\n \t\treturn;\n \n@@ -1096,6 +1099,6 @@ void cfg80211_stop_offchan_radar_detecti\n \n \trdev_set_radar_offchan(rdev, NULL);\n \n-\t__cfg80211_offchan_cac_event(rdev, NULL, NULL,\n+\t__cfg80211_offchan_cac_event(rdev, wdev, &rdev->offchan_radar_chandef,\n \t\t\t\t     NL80211_RADAR_CAC_ABORTED);\n }\n"
  },
  {
    "path": "package/kernel/mac80211/patches/subsys/317-cfg80211-schedule-offchan_cac_abort_wk-in-cfg80211_r.patch",
    "content": "From: Lorenzo Bianconi <lorenzo@kernel.org>\nDate: Tue, 16 Nov 2021 12:41:52 +0100\nSubject: [PATCH] cfg80211: schedule offchan_cac_abort_wk in\n cfg80211_radar_event\n\nIf necessary schedule offchan_cac_abort_wk work in cfg80211_radar_event\nroutine adding offchan parameter to cfg80211_radar_event signature.\nRename cfg80211_radar_event in __cfg80211_radar_event and introduce\nthe two following inline helpers:\n- cfg80211_radar_event\n- cfg80211_offchan_radar_event\nDoing so the drv will not need to run cfg80211_offchan_cac_abort() after\nradar detection on the offchannel chain.\n\nTested-by: Owen Peng <owen.peng@mediatek.com>\nSigned-off-by: Lorenzo Bianconi <lorenzo@kernel.org>\nLink: https://lore.kernel.org/r/3ff583e021e3343a3ced54a7b09b5e184d1880dc.1637062727.git.lorenzo@kernel.org\nSigned-off-by: Johannes Berg <johannes.berg@intel.com>\n---\n\n--- a/include/net/cfg80211.h\n+++ b/include/net/cfg80211.h\n@@ -7580,15 +7580,33 @@ void cfg80211_cqm_txe_notify(struct net_\n void cfg80211_cqm_beacon_loss_notify(struct net_device *dev, gfp_t gfp);\n \n /**\n- * cfg80211_radar_event - radar detection event\n+ * __cfg80211_radar_event - radar detection event\n  * @wiphy: the wiphy\n  * @chandef: chandef for the current channel\n+ * @offchan: the radar has been detected on the offchannel chain\n  * @gfp: context flags\n  *\n  * This function is called when a radar is detected on the current chanenl.\n  */\n-void cfg80211_radar_event(struct wiphy *wiphy,\n-\t\t\t  struct cfg80211_chan_def *chandef, gfp_t gfp);\n+void __cfg80211_radar_event(struct wiphy *wiphy,\n+\t\t\t    struct cfg80211_chan_def *chandef,\n+\t\t\t    bool offchan, gfp_t gfp);\n+\n+static inline void\n+cfg80211_radar_event(struct wiphy *wiphy,\n+\t\t     struct cfg80211_chan_def *chandef,\n+\t\t     gfp_t gfp)\n+{\n+\t__cfg80211_radar_event(wiphy, chandef, false, gfp);\n+}\n+\n+static inline void\n+cfg80211_offchan_radar_event(struct wiphy *wiphy,\n+\t\t\t     struct cfg80211_chan_def *chandef,\n+\t\t\t     gfp_t gfp)\n+{\n+\t__cfg80211_radar_event(wiphy, chandef, true, gfp);\n+}\n \n /**\n  * cfg80211_sta_opmode_change_notify - STA's ht/vht operation mode change event\n--- a/net/wireless/mlme.c\n+++ b/net/wireless/mlme.c\n@@ -905,13 +905,13 @@ void cfg80211_dfs_channels_update_work(s\n }\n \n \n-void cfg80211_radar_event(struct wiphy *wiphy,\n-\t\t\t  struct cfg80211_chan_def *chandef,\n-\t\t\t  gfp_t gfp)\n+void __cfg80211_radar_event(struct wiphy *wiphy,\n+\t\t\t    struct cfg80211_chan_def *chandef,\n+\t\t\t    bool offchan, gfp_t gfp)\n {\n \tstruct cfg80211_registered_device *rdev = wiphy_to_rdev(wiphy);\n \n-\ttrace_cfg80211_radar_event(wiphy, chandef);\n+\ttrace_cfg80211_radar_event(wiphy, chandef, offchan);\n \n \t/* only set the chandef supplied channel to unavailable, in\n \t * case the radar is detected on only one of multiple channels\n@@ -919,6 +919,9 @@ void cfg80211_radar_event(struct wiphy *\n \t */\n \tcfg80211_set_dfs_state(wiphy, chandef, NL80211_DFS_UNAVAILABLE);\n \n+\tif (offchan)\n+\t\tqueue_work(cfg80211_wq, &rdev->offchan_cac_abort_wk);\n+\n \tcfg80211_sched_dfs_chan_update(rdev);\n \n \tnl80211_radar_notify(rdev, chandef, NL80211_RADAR_DETECTED, NULL, gfp);\n@@ -926,7 +929,7 @@ void cfg80211_radar_event(struct wiphy *\n \tmemcpy(&rdev->radar_chandef, chandef, sizeof(struct cfg80211_chan_def));\n \tqueue_work(cfg80211_wq, &rdev->propagate_radar_detect_wk);\n }\n-EXPORT_SYMBOL(cfg80211_radar_event);\n+EXPORT_SYMBOL(__cfg80211_radar_event);\n \n void cfg80211_cac_event(struct net_device *netdev,\n \t\t\tconst struct cfg80211_chan_def *chandef,\n@@ -998,7 +1001,8 @@ __cfg80211_offchan_cac_event(struct cfg8\n \t\trdev->offchan_radar_wdev = NULL;\n \t\tbreak;\n \tcase NL80211_RADAR_CAC_ABORTED:\n-\t\tcancel_delayed_work(&rdev->offchan_cac_done_wk);\n+\t\tif (!cancel_delayed_work(&rdev->offchan_cac_done_wk))\n+\t\t\treturn;\n \t\twdev = rdev->offchan_radar_wdev;\n \t\trdev->offchan_radar_wdev = NULL;\n \t\tbreak;\n--- a/net/wireless/trace.h\n+++ b/net/wireless/trace.h\n@@ -3022,18 +3022,21 @@ TRACE_EVENT(cfg80211_ch_switch_started_n\n );\n \n TRACE_EVENT(cfg80211_radar_event,\n-\tTP_PROTO(struct wiphy *wiphy, struct cfg80211_chan_def *chandef),\n-\tTP_ARGS(wiphy, chandef),\n+\tTP_PROTO(struct wiphy *wiphy, struct cfg80211_chan_def *chandef,\n+\t\t bool offchan),\n+\tTP_ARGS(wiphy, chandef, offchan),\n \tTP_STRUCT__entry(\n \t\tWIPHY_ENTRY\n \t\tCHAN_DEF_ENTRY\n+\t\t__field(bool, offchan)\n \t),\n \tTP_fast_assign(\n \t\tWIPHY_ASSIGN;\n \t\tCHAN_DEF_ASSIGN(chandef);\n+\t\t__entry->offchan = offchan;\n \t),\n-\tTP_printk(WIPHY_PR_FMT \", \" CHAN_DEF_PR_FMT,\n-\t\t  WIPHY_PR_ARG, CHAN_DEF_PR_ARG)\n+\tTP_printk(WIPHY_PR_FMT \", \" CHAN_DEF_PR_FMT \", offchan %d\",\n+\t\t  WIPHY_PR_ARG, CHAN_DEF_PR_ARG, __entry->offchan)\n );\n \n TRACE_EVENT(cfg80211_cac_event,\n"
  },
  {
    "path": "package/kernel/mac80211/patches/subsys/318-cfg80211-allow-continuous-radar-monitoring-on-offcha.patch",
    "content": "From: Lorenzo Bianconi <lorenzo@kernel.org>\nDate: Tue, 16 Nov 2021 15:03:36 +0100\nSubject: [PATCH] cfg80211: allow continuous radar monitoring on offchannel\n chain\n\nAllow continuous radar detection on the offchannel chain in order\nto switch to the monitored channel whenever the underlying driver\nreports a radar pattern on the main channel.\n\nTested-by: Owen Peng <owen.peng@mediatek.com>\nSigned-off-by: Lorenzo Bianconi <lorenzo@kernel.org>\nLink: https://lore.kernel.org/r/d46217310a49b14ff0e9c002f0a6e0547d70fd2c.1637071350.git.lorenzo@kernel.org\nSigned-off-by: Johannes Berg <johannes.berg@intel.com>\n---\n\n--- a/net/wireless/chan.c\n+++ b/net/wireless/chan.c\n@@ -712,6 +712,19 @@ static bool cfg80211_is_wiphy_oper_chan(\n \treturn false;\n }\n \n+static bool\n+cfg80211_offchan_chain_is_active(struct cfg80211_registered_device *rdev,\n+\t\t\t\t struct ieee80211_channel *channel)\n+{\n+\tif (!rdev->offchan_radar_wdev)\n+\t\treturn false;\n+\n+\tif (!cfg80211_chandef_valid(&rdev->offchan_radar_chandef))\n+\t\treturn false;\n+\n+\treturn cfg80211_is_sub_chan(&rdev->offchan_radar_chandef, channel);\n+}\n+\n bool cfg80211_any_wiphy_oper_chan(struct wiphy *wiphy,\n \t\t\t\t  struct ieee80211_channel *chan)\n {\n@@ -728,6 +741,9 @@ bool cfg80211_any_wiphy_oper_chan(struct\n \n \t\tif (cfg80211_is_wiphy_oper_chan(&rdev->wiphy, chan))\n \t\t\treturn true;\n+\n+\t\tif (cfg80211_offchan_chain_is_active(rdev, chan))\n+\t\t\treturn true;\n \t}\n \n \treturn false;\n--- a/net/wireless/mlme.c\n+++ b/net/wireless/mlme.c\n@@ -988,7 +988,7 @@ __cfg80211_offchan_cac_event(struct cfg8\n \tif (!cfg80211_chandef_valid(chandef))\n \t\treturn;\n \n-\tif (event != NL80211_RADAR_CAC_STARTED && !rdev->offchan_radar_wdev)\n+\tif (!rdev->offchan_radar_wdev)\n \t\treturn;\n \n \tswitch (event) {\n@@ -998,17 +998,13 @@ __cfg80211_offchan_cac_event(struct cfg8\n \t\tqueue_work(cfg80211_wq, &rdev->propagate_cac_done_wk);\n \t\tcfg80211_sched_dfs_chan_update(rdev);\n \t\twdev = rdev->offchan_radar_wdev;\n-\t\trdev->offchan_radar_wdev = NULL;\n \t\tbreak;\n \tcase NL80211_RADAR_CAC_ABORTED:\n \t\tif (!cancel_delayed_work(&rdev->offchan_cac_done_wk))\n \t\t\treturn;\n \t\twdev = rdev->offchan_radar_wdev;\n-\t\trdev->offchan_radar_wdev = NULL;\n \t\tbreak;\n \tcase NL80211_RADAR_CAC_STARTED:\n-\t\tWARN_ON(!wdev);\n-\t\trdev->offchan_radar_wdev = wdev;\n \t\tbreak;\n \tdefault:\n \t\treturn;\n@@ -1024,7 +1020,8 @@ cfg80211_offchan_cac_event(struct cfg802\n \t\t\t   enum nl80211_radar_event event)\n {\n \twiphy_lock(&rdev->wiphy);\n-\t__cfg80211_offchan_cac_event(rdev, NULL, chandef, event);\n+\t__cfg80211_offchan_cac_event(rdev, rdev->offchan_radar_wdev,\n+\t\t\t\t     chandef, event);\n \twiphy_unlock(&rdev->wiphy);\n }\n \n@@ -1071,7 +1068,13 @@ cfg80211_start_offchan_radar_detection(s\n \t\t\t\t     NL80211_EXT_FEATURE_RADAR_OFFCHAN))\n \t\treturn -EOPNOTSUPP;\n \n-\tif (rdev->offchan_radar_wdev)\n+\t/* Offchannel chain already locked by another wdev */\n+\tif (rdev->offchan_radar_wdev && rdev->offchan_radar_wdev != wdev)\n+\t\treturn -EBUSY;\n+\n+\t/* CAC already in progress on the offchannel chain */\n+\tif (rdev->offchan_radar_wdev == wdev &&\n+\t    delayed_work_pending(&rdev->offchan_cac_done_wk))\n \t\treturn -EBUSY;\n \n \terr = rdev_set_radar_offchan(rdev, chandef);\n@@ -1083,6 +1086,8 @@ cfg80211_start_offchan_radar_detection(s\n \t\tcac_time_ms = IEEE80211_DFS_MIN_CAC_TIME_MS;\n \n \trdev->offchan_radar_chandef = *chandef;\n+\trdev->offchan_radar_wdev = wdev; /* Get offchain ownership */\n+\n \t__cfg80211_offchan_cac_event(rdev, wdev, chandef,\n \t\t\t\t     NL80211_RADAR_CAC_STARTED);\n \tqueue_delayed_work(cfg80211_wq, &rdev->offchan_cac_done_wk,\n@@ -1102,6 +1107,7 @@ void cfg80211_stop_offchan_radar_detecti\n \t\treturn;\n \n \trdev_set_radar_offchan(rdev, NULL);\n+\trdev->offchan_radar_wdev = NULL; /* Release offchain ownership */\n \n \t__cfg80211_offchan_cac_event(rdev, wdev, &rdev->offchan_radar_chandef,\n \t\t\t\t     NL80211_RADAR_CAC_ABORTED);\n--- a/net/wireless/nl80211.c\n+++ b/net/wireless/nl80211.c\n@@ -9263,42 +9263,60 @@ static int nl80211_start_radar_detection\n \tstruct cfg80211_chan_def chandef;\n \tenum nl80211_dfs_regions dfs_region;\n \tunsigned int cac_time_ms;\n-\tint err;\n+\tint err = -EINVAL;\n+\n+\tflush_delayed_work(&rdev->dfs_update_channels_wk);\n+\n+\twiphy_lock(wiphy);\n \n \tdfs_region = reg_get_dfs_region(wiphy);\n \tif (dfs_region == NL80211_DFS_UNSET)\n-\t\treturn -EINVAL;\n+\t\tgoto unlock;\n \n \terr = nl80211_parse_chandef(rdev, info, &chandef);\n \tif (err)\n-\t\treturn err;\n+\t\tgoto unlock;\n \n \terr = cfg80211_chandef_dfs_required(wiphy, &chandef, wdev->iftype);\n \tif (err < 0)\n-\t\treturn err;\n+\t\tgoto unlock;\n \n-\tif (err == 0)\n-\t\treturn -EINVAL;\n+\tif (err == 0) {\n+\t\terr = -EINVAL;\n+\t\tgoto unlock;\n+\t}\n \n-\tif (!cfg80211_chandef_dfs_usable(wiphy, &chandef))\n-\t\treturn -EINVAL;\n+\tif (!cfg80211_chandef_dfs_usable(wiphy, &chandef)) {\n+\t\terr = -EINVAL;\n+\t\tgoto unlock;\n+\t}\n \n-\tif (nla_get_flag(info->attrs[NL80211_ATTR_RADAR_OFFCHAN]))\n-\t\treturn cfg80211_start_offchan_radar_detection(rdev, wdev,\n-\t\t\t\t\t\t\t      &chandef);\n+\tif (nla_get_flag(info->attrs[NL80211_ATTR_RADAR_OFFCHAN])) {\n+\t\terr = cfg80211_start_offchan_radar_detection(rdev, wdev,\n+\t\t\t\t\t\t\t     &chandef);\n+\t\tgoto unlock;\n+\t}\n \n-\tif (netif_carrier_ok(dev))\n-\t\treturn -EBUSY;\n+\tif (netif_carrier_ok(dev)) {\n+\t\terr = -EBUSY;\n+\t\tgoto unlock;\n+\t}\n \n-\tif (wdev->cac_started)\n-\t\treturn -EBUSY;\n+\tif (wdev->cac_started) {\n+\t\terr = -EBUSY;\n+\t\tgoto unlock;\n+\t}\n \n \t/* CAC start is offloaded to HW and can't be started manually */\n-\tif (wiphy_ext_feature_isset(wiphy, NL80211_EXT_FEATURE_DFS_OFFLOAD))\n-\t\treturn -EOPNOTSUPP;\n+\tif (wiphy_ext_feature_isset(wiphy, NL80211_EXT_FEATURE_DFS_OFFLOAD)) {\n+\t\terr = -EOPNOTSUPP;\n+\t\tgoto unlock;\n+\t}\n \n-\tif (!rdev->ops->start_radar_detection)\n-\t\treturn -EOPNOTSUPP;\n+\tif (!rdev->ops->start_radar_detection) {\n+\t\terr = -EOPNOTSUPP;\n+\t\tgoto unlock;\n+\t}\n \n \tcac_time_ms = cfg80211_chandef_dfs_cac_time(&rdev->wiphy, &chandef);\n \tif (WARN_ON(!cac_time_ms))\n@@ -9311,6 +9329,9 @@ static int nl80211_start_radar_detection\n \t\twdev->cac_start_time = jiffies;\n \t\twdev->cac_time_ms = cac_time_ms;\n \t}\n+unlock:\n+\twiphy_unlock(wiphy);\n+\n \treturn err;\n }\n \n@@ -15941,7 +15962,8 @@ static const struct genl_small_ops nl802\n \t\t.validate = GENL_DONT_VALIDATE_STRICT | GENL_DONT_VALIDATE_DUMP,\n \t\t.doit = nl80211_start_radar_detection,\n \t\t.flags = GENL_UNS_ADMIN_PERM,\n-\t\t.internal_flags = NL80211_FLAG_NEED_NETDEV_UP,\n+\t\t.internal_flags = NL80211_FLAG_NEED_NETDEV_UP |\n+\t\t\t\t  NL80211_FLAG_NO_WIPHY_MTX,\n \t},\n \t{\n \t\t.cmd = NL80211_CMD_GET_PROTOCOL_FEATURES,\n"
  },
  {
    "path": "package/kernel/mac80211/patches/subsys/319-mac80211-introduce-set_radar_offchan-callback.patch",
    "content": "From: Lorenzo Bianconi <lorenzo@kernel.org>\nDate: Sat, 23 Oct 2021 11:10:51 +0200\nSubject: [PATCH] mac80211: introduce set_radar_offchan callback\n\nSimilar to cfg80211, introduce set_radar_offchan callback in mac80211_ops\nin order to configure a dedicated offchannel chain available on some hw\n(e.g. mt7915) to perform offchannel CAC detection and avoid tx/rx downtime.\n\nTested-by: Evelyn Tsai <evelyn.tsai@mediatek.com>\nSigned-off-by: Lorenzo Bianconi <lorenzo@kernel.org>\nLink: https://lore.kernel.org/r/201110606d4f3a7dfdf31440e351f2e2c375d4f0.1634979655.git.lorenzo@kernel.org\nSigned-off-by: Johannes Berg <johannes.berg@intel.com>\n---\n\n--- a/include/net/mac80211.h\n+++ b/include/net/mac80211.h\n@@ -3937,6 +3937,14 @@ struct ieee80211_prep_tx_info {\n  *\ttwt structure.\n  * @twt_teardown_request: Update the hw with TWT teardown request received\n  *\tfrom the peer.\n+ * @set_radar_offchan: Configure dedicated offchannel chain available for\n+ *\tradar/CAC detection on some hw. This chain can't be used to transmit\n+ *\tor receive frames and it is bounded to a running wdev.\n+ *\tOffchannel radar/CAC detection allows to avoid the CAC downtime\n+ *\tswitching to a different channel during CAC detection on the selected\n+ *\tradar channel.\n+ *\tThe caller is expected to set chandef pointer to NULL in order to\n+ *\tdisable offchannel CAC/radar detection.\n  * @net_fill_forward_path: Called from .ndo_fill_forward_path in order to\n  *\tresolve a path for hardware flow offloading\n  */\n@@ -4267,6 +4275,8 @@ struct ieee80211_ops {\n \t\t\t      struct ieee80211_twt_setup *twt);\n \tvoid (*twt_teardown_request)(struct ieee80211_hw *hw,\n \t\t\t\t     struct ieee80211_sta *sta, u8 flowid);\n+\tint (*set_radar_offchan)(struct ieee80211_hw *hw,\n+\t\t\t\t struct cfg80211_chan_def *chandef);\n #if LINUX_VERSION_IS_GEQ(5,10,0)\n \tint (*net_fill_forward_path)(struct ieee80211_hw *hw,\n \t\t\t\t     struct ieee80211_vif *vif,\n--- a/net/mac80211/cfg.c\n+++ b/net/mac80211/cfg.c\n@@ -4344,6 +4344,18 @@ out:\n \treturn err;\n }\n \n+static int\n+ieee80211_set_radar_offchan(struct wiphy *wiphy,\n+\t\t\t    struct cfg80211_chan_def *chandef)\n+{\n+\tstruct ieee80211_local *local = wiphy_priv(wiphy);\n+\n+\tif (!local->ops->set_radar_offchan)\n+\t\treturn -EOPNOTSUPP;\n+\n+\treturn local->ops->set_radar_offchan(&local->hw, chandef);\n+}\n+\n const struct cfg80211_ops mac80211_config_ops = {\n \t.add_virtual_intf = ieee80211_add_iface,\n \t.del_virtual_intf = ieee80211_del_iface,\n@@ -4448,4 +4460,5 @@ const struct cfg80211_ops mac80211_confi\n \t.reset_tid_config = ieee80211_reset_tid_config,\n \t.set_sar_specs = ieee80211_set_sar_specs,\n \t.color_change = ieee80211_color_change,\n+\t.set_radar_offchan = ieee80211_set_radar_offchan,\n };\n"
  },
  {
    "path": "package/kernel/mac80211/patches/subsys/320-cfg80211-rename-offchannel_chain-structs-to-backgrou.patch",
    "content": "From: Lorenzo Bianconi <lorenzo@kernel.org>\nDate: Mon, 29 Nov 2021 14:11:24 +0100\nSubject: [PATCH] cfg80211: rename offchannel_chain structs to background_chain\n to avoid confusion with ETSI standard\n\nETSI standard defines \"Offchannel CAC\" as:\n\"Off-Channel CAC is performed by a number of non-continuous checks\nspread over a period in time. This period, which is required to\ndetermine the presence of radar signals, is defined as the Off-Channel\nCAC Time..\nMinimum Off-Channel CAC Time 6 minutes and Maximum Off-Channel CAC Time\n4 hours..\".\nmac80211 implementation refers to a dedicated hw chain used for continuous\nradar monitoring. Rename offchannel_* references to background_* in\norder to avoid confusion with ETSI standard.\n\nSigned-off-by: Lorenzo Bianconi <lorenzo@kernel.org>\nLink: https://lore.kernel.org/r/4204cc1d648d76b44557981713231e030a3bd991.1638190762.git.lorenzo@kernel.org\nSigned-off-by: Johannes Berg <johannes.berg@intel.com>\n---\n\n--- a/include/net/cfg80211.h\n+++ b/include/net/cfg80211.h\n@@ -4058,14 +4058,14 @@ struct mgmt_frame_regs {\n  *\n  * @color_change: Initiate a color change.\n  *\n- * @set_radar_offchan: Configure dedicated offchannel chain available for\n+ * @set_radar_background: Configure dedicated offchannel chain available for\n  *\tradar/CAC detection on some hw. This chain can't be used to transmit\n  *\tor receive frames and it is bounded to a running wdev.\n- *\tOffchannel radar/CAC detection allows to avoid the CAC downtime\n+ *\tBackground radar/CAC detection allows to avoid the CAC downtime\n  *\tswitching to a different channel during CAC detection on the selected\n  *\tradar channel.\n  *\tThe caller is expected to set chandef pointer to NULL in order to\n- *\tdisable offchannel CAC/radar detection.\n+ *\tdisable background CAC/radar detection.\n  */\n struct cfg80211_ops {\n \tint\t(*suspend)(struct wiphy *wiphy, struct cfg80211_wowlan *wow);\n@@ -4396,8 +4396,8 @@ struct cfg80211_ops {\n \tint\t(*color_change)(struct wiphy *wiphy,\n \t\t\t\tstruct net_device *dev,\n \t\t\t\tstruct cfg80211_color_change_settings *params);\n-\tint\t(*set_radar_offchan)(struct wiphy *wiphy,\n-\t\t\t\t     struct cfg80211_chan_def *chandef);\n+\tint\t(*set_radar_background)(struct wiphy *wiphy,\n+\t\t\t\t\tstruct cfg80211_chan_def *chandef);\n };\n \n /*\n@@ -7601,9 +7601,9 @@ cfg80211_radar_event(struct wiphy *wiphy\n }\n \n static inline void\n-cfg80211_offchan_radar_event(struct wiphy *wiphy,\n-\t\t\t     struct cfg80211_chan_def *chandef,\n-\t\t\t     gfp_t gfp)\n+cfg80211_background_radar_event(struct wiphy *wiphy,\n+\t\t\t\tstruct cfg80211_chan_def *chandef,\n+\t\t\t\tgfp_t gfp)\n {\n \t__cfg80211_radar_event(wiphy, chandef, true, gfp);\n }\n@@ -7638,13 +7638,13 @@ void cfg80211_cac_event(struct net_devic\n \t\t\tenum nl80211_radar_event event, gfp_t gfp);\n \n /**\n- * cfg80211_offchan_cac_abort - Channel Availability Check offchan abort event\n+ * cfg80211_background_cac_abort - Channel Availability Check offchan abort event\n  * @wiphy: the wiphy\n  *\n  * This function is called by the driver when a Channel Availability Check\n  * (CAC) is aborted by a offchannel dedicated chain.\n  */\n-void cfg80211_offchan_cac_abort(struct wiphy *wiphy);\n+void cfg80211_background_cac_abort(struct wiphy *wiphy);\n \n /**\n  * cfg80211_gtk_rekey_notify - notify userspace about driver rekeying\n--- a/include/net/mac80211.h\n+++ b/include/net/mac80211.h\n@@ -3937,14 +3937,14 @@ struct ieee80211_prep_tx_info {\n  *\ttwt structure.\n  * @twt_teardown_request: Update the hw with TWT teardown request received\n  *\tfrom the peer.\n- * @set_radar_offchan: Configure dedicated offchannel chain available for\n+ * @set_radar_background: Configure dedicated offchannel chain available for\n  *\tradar/CAC detection on some hw. This chain can't be used to transmit\n  *\tor receive frames and it is bounded to a running wdev.\n- *\tOffchannel radar/CAC detection allows to avoid the CAC downtime\n+ *\tBackground radar/CAC detection allows to avoid the CAC downtime\n  *\tswitching to a different channel during CAC detection on the selected\n  *\tradar channel.\n  *\tThe caller is expected to set chandef pointer to NULL in order to\n- *\tdisable offchannel CAC/radar detection.\n+ *\tdisable background CAC/radar detection.\n  * @net_fill_forward_path: Called from .ndo_fill_forward_path in order to\n  *\tresolve a path for hardware flow offloading\n  */\n@@ -4275,8 +4275,8 @@ struct ieee80211_ops {\n \t\t\t      struct ieee80211_twt_setup *twt);\n \tvoid (*twt_teardown_request)(struct ieee80211_hw *hw,\n \t\t\t\t     struct ieee80211_sta *sta, u8 flowid);\n-\tint (*set_radar_offchan)(struct ieee80211_hw *hw,\n-\t\t\t\t struct cfg80211_chan_def *chandef);\n+\tint (*set_radar_background)(struct ieee80211_hw *hw,\n+\t\t\t\t    struct cfg80211_chan_def *chandef);\n #if LINUX_VERSION_IS_GEQ(5,10,0)\n \tint (*net_fill_forward_path)(struct ieee80211_hw *hw,\n \t\t\t\t     struct ieee80211_vif *vif,\n--- a/include/uapi/linux/nl80211.h\n+++ b/include/uapi/linux/nl80211.h\n@@ -2608,10 +2608,10 @@ enum nl80211_commands {\n  *\tMandatory parameter for the transmitting interface to enable MBSSID.\n  *\tOptional for the non-transmitting interfaces.\n  *\n- * @NL80211_ATTR_RADAR_OFFCHAN: Configure dedicated offchannel chain available for\n- *\tradar/CAC detection on some hw. This chain can't be used to transmit\n- *\tor receive frames and it is bounded to a running wdev.\n- *\tOffchannel radar/CAC detection allows to avoid the CAC downtime\n+ * @NL80211_ATTR_RADAR_BACKGROUND: Configure dedicated offchannel chain\n+ *\tavailable for radar/CAC detection on some hw. This chain can't be used\n+ *\tto transmit or receive frames and it is bounded to a running wdev.\n+ *\tBackground radar/CAC detection allows to avoid the CAC downtime\n  *\tswitching on a different channel during CAC detection on the selected\n  *\tradar channel.\n  *\n@@ -3121,7 +3121,7 @@ enum nl80211_attrs {\n \tNL80211_ATTR_MBSSID_CONFIG,\n \tNL80211_ATTR_MBSSID_ELEMS,\n \n-\tNL80211_ATTR_RADAR_OFFCHAN,\n+\tNL80211_ATTR_RADAR_BACKGROUND,\n \n \t/* add attributes here, update the policy in nl80211.c */\n \n@@ -6022,7 +6022,7 @@ enum nl80211_feature_flags {\n  * @NL80211_EXT_FEATURE_BSS_COLOR: The driver supports BSS color collision\n  *\tdetection and change announcemnts.\n  *\n- * @NL80211_EXT_FEATURE_RADAR_OFFCHAN: Device supports offchannel radar/CAC\n+ * @NL80211_EXT_FEATURE_RADAR_BACKGROUND: Device supports background radar/CAC\n  *\tdetection.\n  *\n  * @NUM_NL80211_EXT_FEATURES: number of extended features.\n@@ -6090,7 +6090,7 @@ enum nl80211_ext_feature_index {\n \tNL80211_EXT_FEATURE_SECURE_RTT,\n \tNL80211_EXT_FEATURE_PROT_RANGE_NEGO_AND_MEASURE,\n \tNL80211_EXT_FEATURE_BSS_COLOR,\n-\tNL80211_EXT_FEATURE_RADAR_OFFCHAN,\n+\tNL80211_EXT_FEATURE_RADAR_BACKGROUND,\n \n \t/* add new features before the definition below */\n \tNUM_NL80211_EXT_FEATURES,\n--- a/net/mac80211/cfg.c\n+++ b/net/mac80211/cfg.c\n@@ -4345,15 +4345,15 @@ out:\n }\n \n static int\n-ieee80211_set_radar_offchan(struct wiphy *wiphy,\n-\t\t\t    struct cfg80211_chan_def *chandef)\n+ieee80211_set_radar_background(struct wiphy *wiphy,\n+\t\t\t       struct cfg80211_chan_def *chandef)\n {\n \tstruct ieee80211_local *local = wiphy_priv(wiphy);\n \n-\tif (!local->ops->set_radar_offchan)\n+\tif (!local->ops->set_radar_background)\n \t\treturn -EOPNOTSUPP;\n \n-\treturn local->ops->set_radar_offchan(&local->hw, chandef);\n+\treturn local->ops->set_radar_background(&local->hw, chandef);\n }\n \n const struct cfg80211_ops mac80211_config_ops = {\n@@ -4460,5 +4460,5 @@ const struct cfg80211_ops mac80211_confi\n \t.reset_tid_config = ieee80211_reset_tid_config,\n \t.set_sar_specs = ieee80211_set_sar_specs,\n \t.color_change = ieee80211_color_change,\n-\t.set_radar_offchan = ieee80211_set_radar_offchan,\n+\t.set_radar_background = ieee80211_set_radar_background,\n };\n--- a/net/wireless/chan.c\n+++ b/net/wireless/chan.c\n@@ -716,13 +716,13 @@ static bool\n cfg80211_offchan_chain_is_active(struct cfg80211_registered_device *rdev,\n \t\t\t\t struct ieee80211_channel *channel)\n {\n-\tif (!rdev->offchan_radar_wdev)\n+\tif (!rdev->background_radar_wdev)\n \t\treturn false;\n \n-\tif (!cfg80211_chandef_valid(&rdev->offchan_radar_chandef))\n+\tif (!cfg80211_chandef_valid(&rdev->background_radar_chandef))\n \t\treturn false;\n \n-\treturn cfg80211_is_sub_chan(&rdev->offchan_radar_chandef, channel);\n+\treturn cfg80211_is_sub_chan(&rdev->background_radar_chandef, channel);\n }\n \n bool cfg80211_any_wiphy_oper_chan(struct wiphy *wiphy,\n--- a/net/wireless/core.c\n+++ b/net/wireless/core.c\n@@ -543,9 +543,10 @@ use_default_name:\n \tINIT_WORK(&rdev->rfkill_block, cfg80211_rfkill_block_work);\n \tINIT_WORK(&rdev->conn_work, cfg80211_conn_work);\n \tINIT_WORK(&rdev->event_work, cfg80211_event_work);\n-\tINIT_WORK(&rdev->offchan_cac_abort_wk, cfg80211_offchan_cac_abort_wk);\n-\tINIT_DELAYED_WORK(&rdev->offchan_cac_done_wk,\n-\t\t\t  cfg80211_offchan_cac_done_wk);\n+\tINIT_WORK(&rdev->background_cac_abort_wk,\n+\t\t  cfg80211_background_cac_abort_wk);\n+\tINIT_DELAYED_WORK(&rdev->background_cac_done_wk,\n+\t\t\t  cfg80211_background_cac_done_wk);\n \n \tinit_waitqueue_head(&rdev->dev_wait);\n \n@@ -1055,13 +1056,13 @@ void wiphy_unregister(struct wiphy *wiph\n \tcancel_work_sync(&rdev->conn_work);\n \tflush_work(&rdev->event_work);\n \tcancel_delayed_work_sync(&rdev->dfs_update_channels_wk);\n-\tcancel_delayed_work_sync(&rdev->offchan_cac_done_wk);\n+\tcancel_delayed_work_sync(&rdev->background_cac_done_wk);\n \tflush_work(&rdev->destroy_work);\n \tflush_work(&rdev->sched_scan_stop_wk);\n \tflush_work(&rdev->propagate_radar_detect_wk);\n \tflush_work(&rdev->propagate_cac_done_wk);\n \tflush_work(&rdev->mgmt_registrations_update_wk);\n-\tflush_work(&rdev->offchan_cac_abort_wk);\n+\tflush_work(&rdev->background_cac_abort_wk);\n \n #ifdef CONFIG_PM\n \tif (rdev->wiphy.wowlan_config && rdev->ops->set_wakeup)\n@@ -1210,7 +1211,7 @@ void __cfg80211_leave(struct cfg80211_re\n \n \tcfg80211_pmsr_wdev_down(wdev);\n \n-\tcfg80211_stop_offchan_radar_detection(wdev);\n+\tcfg80211_stop_background_radar_detection(wdev);\n \n \tswitch (wdev->iftype) {\n \tcase NL80211_IFTYPE_ADHOC:\n--- a/net/wireless/core.h\n+++ b/net/wireless/core.h\n@@ -84,10 +84,10 @@ struct cfg80211_registered_device {\n \n \tstruct delayed_work dfs_update_channels_wk;\n \n-\tstruct wireless_dev *offchan_radar_wdev;\n-\tstruct cfg80211_chan_def offchan_radar_chandef;\n-\tstruct delayed_work offchan_cac_done_wk;\n-\tstruct work_struct offchan_cac_abort_wk;\n+\tstruct wireless_dev *background_radar_wdev;\n+\tstruct cfg80211_chan_def background_radar_chandef;\n+\tstruct delayed_work background_cac_done_wk;\n+\tstruct work_struct background_cac_abort_wk;\n \n \t/* netlink port which started critical protocol (0 means not started) */\n \tu32 crit_proto_nlportid;\n@@ -497,15 +497,15 @@ cfg80211_chandef_dfs_cac_time(struct wip\n void cfg80211_sched_dfs_chan_update(struct cfg80211_registered_device *rdev);\n \n int\n-cfg80211_start_offchan_radar_detection(struct cfg80211_registered_device *rdev,\n-\t\t\t\t       struct wireless_dev *wdev,\n-\t\t\t\t       struct cfg80211_chan_def *chandef);\n+cfg80211_start_background_radar_detection(struct cfg80211_registered_device *rdev,\n+\t\t\t\t\t  struct wireless_dev *wdev,\n+\t\t\t\t\t  struct cfg80211_chan_def *chandef);\n \n-void cfg80211_stop_offchan_radar_detection(struct wireless_dev *wdev);\n+void cfg80211_stop_background_radar_detection(struct wireless_dev *wdev);\n \n-void cfg80211_offchan_cac_done_wk(struct work_struct *work);\n+void cfg80211_background_cac_done_wk(struct work_struct *work);\n \n-void cfg80211_offchan_cac_abort_wk(struct work_struct *work);\n+void cfg80211_background_cac_abort_wk(struct work_struct *work);\n \n bool cfg80211_any_wiphy_oper_chan(struct wiphy *wiphy,\n \t\t\t\t  struct ieee80211_channel *chan);\n--- a/net/wireless/mlme.c\n+++ b/net/wireless/mlme.c\n@@ -920,7 +920,7 @@ void __cfg80211_radar_event(struct wiphy\n \tcfg80211_set_dfs_state(wiphy, chandef, NL80211_DFS_UNAVAILABLE);\n \n \tif (offchan)\n-\t\tqueue_work(cfg80211_wq, &rdev->offchan_cac_abort_wk);\n+\t\tqueue_work(cfg80211_wq, &rdev->background_cac_abort_wk);\n \n \tcfg80211_sched_dfs_chan_update(rdev);\n \n@@ -975,10 +975,10 @@ void cfg80211_cac_event(struct net_devic\n EXPORT_SYMBOL(cfg80211_cac_event);\n \n static void\n-__cfg80211_offchan_cac_event(struct cfg80211_registered_device *rdev,\n-\t\t\t     struct wireless_dev *wdev,\n-\t\t\t     const struct cfg80211_chan_def *chandef,\n-\t\t\t     enum nl80211_radar_event event)\n+__cfg80211_background_cac_event(struct cfg80211_registered_device *rdev,\n+\t\t\t\tstruct wireless_dev *wdev,\n+\t\t\t\tconst struct cfg80211_chan_def *chandef,\n+\t\t\t\tenum nl80211_radar_event event)\n {\n \tstruct wiphy *wiphy = &rdev->wiphy;\n \tstruct net_device *netdev;\n@@ -988,7 +988,7 @@ __cfg80211_offchan_cac_event(struct cfg8\n \tif (!cfg80211_chandef_valid(chandef))\n \t\treturn;\n \n-\tif (!rdev->offchan_radar_wdev)\n+\tif (!rdev->background_radar_wdev)\n \t\treturn;\n \n \tswitch (event) {\n@@ -997,12 +997,12 @@ __cfg80211_offchan_cac_event(struct cfg8\n \t\tmemcpy(&rdev->cac_done_chandef, chandef, sizeof(*chandef));\n \t\tqueue_work(cfg80211_wq, &rdev->propagate_cac_done_wk);\n \t\tcfg80211_sched_dfs_chan_update(rdev);\n-\t\twdev = rdev->offchan_radar_wdev;\n+\t\twdev = rdev->background_radar_wdev;\n \t\tbreak;\n \tcase NL80211_RADAR_CAC_ABORTED:\n-\t\tif (!cancel_delayed_work(&rdev->offchan_cac_done_wk))\n+\t\tif (!cancel_delayed_work(&rdev->background_cac_done_wk))\n \t\t\treturn;\n-\t\twdev = rdev->offchan_radar_wdev;\n+\t\twdev = rdev->background_radar_wdev;\n \t\tbreak;\n \tcase NL80211_RADAR_CAC_STARTED:\n \t\tbreak;\n@@ -1015,49 +1015,49 @@ __cfg80211_offchan_cac_event(struct cfg8\n }\n \n static void\n-cfg80211_offchan_cac_event(struct cfg80211_registered_device *rdev,\n-\t\t\t   const struct cfg80211_chan_def *chandef,\n-\t\t\t   enum nl80211_radar_event event)\n+cfg80211_background_cac_event(struct cfg80211_registered_device *rdev,\n+\t\t\t      const struct cfg80211_chan_def *chandef,\n+\t\t\t      enum nl80211_radar_event event)\n {\n \twiphy_lock(&rdev->wiphy);\n-\t__cfg80211_offchan_cac_event(rdev, rdev->offchan_radar_wdev,\n-\t\t\t\t     chandef, event);\n+\t__cfg80211_background_cac_event(rdev, rdev->background_radar_wdev,\n+\t\t\t\t\tchandef, event);\n \twiphy_unlock(&rdev->wiphy);\n }\n \n-void cfg80211_offchan_cac_done_wk(struct work_struct *work)\n+void cfg80211_background_cac_done_wk(struct work_struct *work)\n {\n \tstruct delayed_work *delayed_work = to_delayed_work(work);\n \tstruct cfg80211_registered_device *rdev;\n \n \trdev = container_of(delayed_work, struct cfg80211_registered_device,\n-\t\t\t    offchan_cac_done_wk);\n-\tcfg80211_offchan_cac_event(rdev, &rdev->offchan_radar_chandef,\n-\t\t\t\t   NL80211_RADAR_CAC_FINISHED);\n+\t\t\t    background_cac_done_wk);\n+\tcfg80211_background_cac_event(rdev, &rdev->background_radar_chandef,\n+\t\t\t\t      NL80211_RADAR_CAC_FINISHED);\n }\n \n-void cfg80211_offchan_cac_abort_wk(struct work_struct *work)\n+void cfg80211_background_cac_abort_wk(struct work_struct *work)\n {\n \tstruct cfg80211_registered_device *rdev;\n \n \trdev = container_of(work, struct cfg80211_registered_device,\n-\t\t\t    offchan_cac_abort_wk);\n-\tcfg80211_offchan_cac_event(rdev, &rdev->offchan_radar_chandef,\n-\t\t\t\t   NL80211_RADAR_CAC_ABORTED);\n+\t\t\t    background_cac_abort_wk);\n+\tcfg80211_background_cac_event(rdev, &rdev->background_radar_chandef,\n+\t\t\t\t      NL80211_RADAR_CAC_ABORTED);\n }\n \n-void cfg80211_offchan_cac_abort(struct wiphy *wiphy)\n+void cfg80211_background_cac_abort(struct wiphy *wiphy)\n {\n \tstruct cfg80211_registered_device *rdev = wiphy_to_rdev(wiphy);\n \n-\tqueue_work(cfg80211_wq, &rdev->offchan_cac_abort_wk);\n+\tqueue_work(cfg80211_wq, &rdev->background_cac_abort_wk);\n }\n-EXPORT_SYMBOL(cfg80211_offchan_cac_abort);\n+EXPORT_SYMBOL(cfg80211_background_cac_abort);\n \n int\n-cfg80211_start_offchan_radar_detection(struct cfg80211_registered_device *rdev,\n-\t\t\t\t       struct wireless_dev *wdev,\n-\t\t\t\t       struct cfg80211_chan_def *chandef)\n+cfg80211_start_background_radar_detection(struct cfg80211_registered_device *rdev,\n+\t\t\t\t\t  struct wireless_dev *wdev,\n+\t\t\t\t\t  struct cfg80211_chan_def *chandef)\n {\n \tunsigned int cac_time_ms;\n \tint err;\n@@ -1065,19 +1065,19 @@ cfg80211_start_offchan_radar_detection(s\n \tlockdep_assert_wiphy(&rdev->wiphy);\n \n \tif (!wiphy_ext_feature_isset(&rdev->wiphy,\n-\t\t\t\t     NL80211_EXT_FEATURE_RADAR_OFFCHAN))\n+\t\t\t\t     NL80211_EXT_FEATURE_RADAR_BACKGROUND))\n \t\treturn -EOPNOTSUPP;\n \n \t/* Offchannel chain already locked by another wdev */\n-\tif (rdev->offchan_radar_wdev && rdev->offchan_radar_wdev != wdev)\n+\tif (rdev->background_radar_wdev && rdev->background_radar_wdev != wdev)\n \t\treturn -EBUSY;\n \n \t/* CAC already in progress on the offchannel chain */\n-\tif (rdev->offchan_radar_wdev == wdev &&\n-\t    delayed_work_pending(&rdev->offchan_cac_done_wk))\n+\tif (rdev->background_radar_wdev == wdev &&\n+\t    delayed_work_pending(&rdev->background_cac_done_wk))\n \t\treturn -EBUSY;\n \n-\terr = rdev_set_radar_offchan(rdev, chandef);\n+\terr = rdev_set_radar_background(rdev, chandef);\n \tif (err)\n \t\treturn err;\n \n@@ -1085,30 +1085,31 @@ cfg80211_start_offchan_radar_detection(s\n \tif (!cac_time_ms)\n \t\tcac_time_ms = IEEE80211_DFS_MIN_CAC_TIME_MS;\n \n-\trdev->offchan_radar_chandef = *chandef;\n-\trdev->offchan_radar_wdev = wdev; /* Get offchain ownership */\n+\trdev->background_radar_chandef = *chandef;\n+\trdev->background_radar_wdev = wdev; /* Get offchain ownership */\n \n-\t__cfg80211_offchan_cac_event(rdev, wdev, chandef,\n-\t\t\t\t     NL80211_RADAR_CAC_STARTED);\n-\tqueue_delayed_work(cfg80211_wq, &rdev->offchan_cac_done_wk,\n+\t__cfg80211_background_cac_event(rdev, wdev, chandef,\n+\t\t\t\t\tNL80211_RADAR_CAC_STARTED);\n+\tqueue_delayed_work(cfg80211_wq, &rdev->background_cac_done_wk,\n \t\t\t   msecs_to_jiffies(cac_time_ms));\n \n \treturn 0;\n }\n \n-void cfg80211_stop_offchan_radar_detection(struct wireless_dev *wdev)\n+void cfg80211_stop_background_radar_detection(struct wireless_dev *wdev)\n {\n \tstruct wiphy *wiphy = wdev->wiphy;\n \tstruct cfg80211_registered_device *rdev = wiphy_to_rdev(wiphy);\n \n \tlockdep_assert_wiphy(wiphy);\n \n-\tif (wdev != rdev->offchan_radar_wdev)\n+\tif (wdev != rdev->background_radar_wdev)\n \t\treturn;\n \n-\trdev_set_radar_offchan(rdev, NULL);\n-\trdev->offchan_radar_wdev = NULL; /* Release offchain ownership */\n+\trdev_set_radar_background(rdev, NULL);\n+\trdev->background_radar_wdev = NULL; /* Release offchain ownership */\n \n-\t__cfg80211_offchan_cac_event(rdev, wdev, &rdev->offchan_radar_chandef,\n-\t\t\t\t     NL80211_RADAR_CAC_ABORTED);\n+\t__cfg80211_background_cac_event(rdev, wdev,\n+\t\t\t\t\t&rdev->background_radar_chandef,\n+\t\t\t\t\tNL80211_RADAR_CAC_ABORTED);\n }\n--- a/net/wireless/nl80211.c\n+++ b/net/wireless/nl80211.c\n@@ -796,7 +796,7 @@ static const struct nla_policy nl80211_p\n \t[NL80211_ATTR_MBSSID_CONFIG] =\n \t\t\tNLA_POLICY_NESTED(nl80211_mbssid_config_policy),\n \t[NL80211_ATTR_MBSSID_ELEMS] = { .type = NLA_NESTED },\n-\t[NL80211_ATTR_RADAR_OFFCHAN] = { .type = NLA_FLAG },\n+\t[NL80211_ATTR_RADAR_BACKGROUND] = { .type = NLA_FLAG },\n };\n \n /* policy for the key attributes */\n@@ -9291,9 +9291,9 @@ static int nl80211_start_radar_detection\n \t\tgoto unlock;\n \t}\n \n-\tif (nla_get_flag(info->attrs[NL80211_ATTR_RADAR_OFFCHAN])) {\n-\t\terr = cfg80211_start_offchan_radar_detection(rdev, wdev,\n-\t\t\t\t\t\t\t     &chandef);\n+\tif (nla_get_flag(info->attrs[NL80211_ATTR_RADAR_BACKGROUND])) {\n+\t\terr = cfg80211_start_background_radar_detection(rdev, wdev,\n+\t\t\t\t\t\t\t\t&chandef);\n \t\tgoto unlock;\n \t}\n \n--- a/net/wireless/rdev-ops.h\n+++ b/net/wireless/rdev-ops.h\n@@ -1382,17 +1382,17 @@ static inline int rdev_color_change(stru\n }\n \n static inline int\n-rdev_set_radar_offchan(struct cfg80211_registered_device *rdev,\n-\t\t       struct cfg80211_chan_def *chandef)\n+rdev_set_radar_background(struct cfg80211_registered_device *rdev,\n+\t\t\t  struct cfg80211_chan_def *chandef)\n {\n \tstruct wiphy *wiphy = &rdev->wiphy;\n \tint ret;\n \n-\tif (!rdev->ops->set_radar_offchan)\n+\tif (!rdev->ops->set_radar_background)\n \t\treturn -EOPNOTSUPP;\n \n-\ttrace_rdev_set_radar_offchan(wiphy, chandef);\n-\tret = rdev->ops->set_radar_offchan(wiphy, chandef);\n+\ttrace_rdev_set_radar_background(wiphy, chandef);\n+\tret = rdev->ops->set_radar_background(wiphy, chandef);\n \ttrace_rdev_return_int(wiphy, ret);\n \n \treturn ret;\n--- a/net/wireless/trace.h\n+++ b/net/wireless/trace.h\n@@ -3646,7 +3646,7 @@ TRACE_EVENT(cfg80211_bss_color_notify,\n \t\t  __entry->color_bitmap)\n );\n \n-TRACE_EVENT(rdev_set_radar_offchan,\n+TRACE_EVENT(rdev_set_radar_background,\n \tTP_PROTO(struct wiphy *wiphy, struct cfg80211_chan_def *chandef),\n \n \tTP_ARGS(wiphy, chandef),\n"
  },
  {
    "path": "package/kernel/mac80211/patches/subsys/323-mac80211-MBSSID-support-in-interface-handling.patch",
    "content": "From: John Crispin <john@phrozen.org>\nDate: Wed, 15 Sep 2021 19:54:35 -0700\nSubject: [PATCH] mac80211: MBSSID support in interface handling\n\nConfigure multiple BSSID and enhanced multi-BSSID advertisement (EMA)\nparameters in mac80211 for AP mode.\n\nFor each interface, 'mbssid_tx_vif' points to the transmitting interface of\nthe MBSSID set. The pointer is set to NULL if MBSSID is disabled.\n\nFunction ieee80211_stop() is modified to always bring down all the\nnon-transmitting interfaces first and the transmitting interface last.\n\nSigned-off-by: John Crispin <john@phrozen.org>\nCo-developed-by: Aloka Dixit <alokad@codeaurora.org>\nSigned-off-by: Aloka Dixit <alokad@codeaurora.org>\nLink: https://lore.kernel.org/r/20210916025437.29138-3-alokad@codeaurora.org\n[slightly change logic to be more obvious]\nSigned-off-by: Johannes Berg <johannes.berg@intel.com>\n---\n\n--- a/include/net/mac80211.h\n+++ b/include/net/mac80211.h\n@@ -1719,6 +1719,7 @@ enum ieee80211_offload_flags {\n  *\twrite-protected by sdata_lock and local->mtx so holding either is fine\n  *\tfor read access.\n  * @color_change_color: the bss color that will be used after the change.\n+ * @mbssid_tx_vif: Pointer to the transmitting interface if MBSSID is enabled.\n  */\n struct ieee80211_vif {\n \tenum nl80211_iftype type;\n@@ -1750,6 +1751,8 @@ struct ieee80211_vif {\n \tbool color_change_active;\n \tu8 color_change_color;\n \n+\tstruct ieee80211_vif *mbssid_tx_vif;\n+\n \t/* must be last */\n \tu8 drv_priv[] __aligned(sizeof(void *));\n };\n--- a/net/mac80211/cfg.c\n+++ b/net/mac80211/cfg.c\n@@ -112,6 +112,36 @@ static int ieee80211_set_mon_options(str\n \treturn 0;\n }\n \n+static int ieee80211_set_ap_mbssid_options(struct ieee80211_sub_if_data *sdata,\n+\t\t\t\t\t   struct cfg80211_mbssid_config params)\n+{\n+\tstruct ieee80211_sub_if_data *tx_sdata;\n+\n+\tsdata->vif.mbssid_tx_vif = NULL;\n+\tsdata->vif.bss_conf.bssid_index = 0;\n+\tsdata->vif.bss_conf.nontransmitted = false;\n+\tsdata->vif.bss_conf.ema_ap = false;\n+\n+\tif (sdata->vif.type != NL80211_IFTYPE_AP || !params.tx_wdev)\n+\t\treturn -EINVAL;\n+\n+\ttx_sdata = IEEE80211_WDEV_TO_SUB_IF(params.tx_wdev);\n+\tif (!tx_sdata)\n+\t\treturn -EINVAL;\n+\n+\tif (tx_sdata == sdata) {\n+\t\tsdata->vif.mbssid_tx_vif = &sdata->vif;\n+\t} else {\n+\t\tsdata->vif.mbssid_tx_vif = &tx_sdata->vif;\n+\t\tsdata->vif.bss_conf.nontransmitted = true;\n+\t\tsdata->vif.bss_conf.bssid_index = params.index;\n+\t}\n+\tif (params.ema)\n+\t\tsdata->vif.bss_conf.ema_ap = true;\n+\n+\treturn 0;\n+}\n+\n static struct wireless_dev *ieee80211_add_iface(struct wiphy *wiphy,\n \t\t\t\t\t\tconst char *name,\n \t\t\t\t\t\tunsigned char name_assign_type,\n@@ -1107,6 +1137,14 @@ static int ieee80211_start_ap(struct wip\n \t\t\tchanged |= BSS_CHANGED_HE_BSS_COLOR;\n \t}\n \n+\tif (sdata->vif.type == NL80211_IFTYPE_AP &&\n+\t    params->mbssid_config.tx_wdev) {\n+\t\terr = ieee80211_set_ap_mbssid_options(sdata,\n+\t\t\t\t\t\t      params->mbssid_config);\n+\t\tif (err)\n+\t\t\treturn err;\n+\t}\n+\n \tmutex_lock(&local->mtx);\n \terr = ieee80211_vif_use_channel(sdata, &params->chandef,\n \t\t\t\t\tIEEE80211_CHANCTX_SHARED);\n--- a/net/mac80211/iface.c\n+++ b/net/mac80211/iface.c\n@@ -632,17 +632,46 @@ static void ieee80211_do_stop(struct iee\n \t\tieee80211_add_virtual_monitor(local);\n }\n \n+static void ieee80211_stop_mbssid(struct ieee80211_sub_if_data *sdata)\n+{\n+\tstruct ieee80211_sub_if_data *tx_sdata, *non_tx_sdata, *tmp_sdata;\n+\tstruct ieee80211_vif *tx_vif = sdata->vif.mbssid_tx_vif;\n+\n+\tif (!tx_vif)\n+\t\treturn;\n+\n+\ttx_sdata = vif_to_sdata(tx_vif);\n+\tsdata->vif.mbssid_tx_vif = NULL;\n+\n+\tlist_for_each_entry_safe(non_tx_sdata, tmp_sdata,\n+\t\t\t\t &tx_sdata->local->interfaces, list) {\n+\t\tif (non_tx_sdata != sdata && non_tx_sdata != tx_sdata &&\n+\t\t    non_tx_sdata->vif.mbssid_tx_vif == tx_vif &&\n+\t\t    ieee80211_sdata_running(non_tx_sdata)) {\n+\t\t\tnon_tx_sdata->vif.mbssid_tx_vif = NULL;\n+\t\t\tdev_close(non_tx_sdata->wdev.netdev);\n+\t\t}\n+\t}\n+\n+\tif (sdata != tx_sdata && ieee80211_sdata_running(tx_sdata)) {\n+\t\ttx_sdata->vif.mbssid_tx_vif = NULL;\n+\t\tdev_close(tx_sdata->wdev.netdev);\n+\t}\n+}\n+\n static int ieee80211_stop(struct net_device *dev)\n {\n \tstruct ieee80211_sub_if_data *sdata = IEEE80211_DEV_TO_SUB_IF(dev);\n \n-\t/* close all dependent VLAN interfaces before locking wiphy */\n+\t/* close dependent VLAN and MBSSID interfaces before locking wiphy */\n \tif (sdata->vif.type == NL80211_IFTYPE_AP) {\n \t\tstruct ieee80211_sub_if_data *vlan, *tmpsdata;\n \n \t\tlist_for_each_entry_safe(vlan, tmpsdata, &sdata->u.ap.vlans,\n \t\t\t\t\t u.vlan.list)\n \t\t\tdev_close(vlan->dev);\n+\n+\t\tieee80211_stop_mbssid(sdata);\n \t}\n \n \twiphy_lock(sdata->local->hw.wiphy);\n"
  },
  {
    "path": "package/kernel/mac80211/patches/subsys/324-mac80211-MBSSID-beacon-handling-in-AP-mode.patch",
    "content": "From: Lorenzo Bianconi <lorenzo@kernel.org>\nDate: Thu, 24 Feb 2022 12:54:58 +0100\nSubject: [PATCH] mac80211: MBSSID beacon handling in AP mode\n\nAdd new fields in struct beacon_data to store all MBSSID elements.\nGenerate a beacon template which includes all MBSSID elements.\nMove CSA offset to reflect the MBSSID element length.\n\nCo-developed-by: Aloka Dixit <alokad@codeaurora.org>\nSigned-off-by: Aloka Dixit <alokad@codeaurora.org>\nCo-developed-by: John Crispin <john@phrozen.org>\nSigned-off-by: John Crispin <john@phrozen.org>\nSigned-off-by: Lorenzo Bianconi <lorenzo@kernel.org>\nTested-by: Money Wang <money.wang@mediatek.com>\nLink: https://lore.kernel.org/r/5322db3c303f431adaf191ab31c45e151dde5465.1645702516.git.lorenzo@kernel.org\n[small cleanups]\nSigned-off-by: Johannes Berg <johannes.berg@intel.com>\n---\n\n--- a/include/net/mac80211.h\n+++ b/include/net/mac80211.h\n@@ -4938,12 +4938,14 @@ void ieee80211_report_low_ack(struct iee\n  * @cntdwn_counter_offs: array of IEEE80211_MAX_CNTDWN_COUNTERS_NUM offsets\n  *\tto countdown counters.  This array can contain zero values which\n  *\tshould be ignored.\n+ * @mbssid_off: position of the multiple bssid element\n  */\n struct ieee80211_mutable_offsets {\n \tu16 tim_offset;\n \tu16 tim_length;\n \n \tu16 cntdwn_counter_offs[IEEE80211_MAX_CNTDWN_COUNTERS_NUM];\n+\tu16 mbssid_off;\n };\n \n /**\n--- a/net/mac80211/cfg.c\n+++ b/net/mac80211/cfg.c\n@@ -989,11 +989,29 @@ static int ieee80211_set_ftm_responder_p\n \treturn 0;\n }\n \n+static int\n+ieee80211_copy_mbssid_beacon(u8 *pos, struct cfg80211_mbssid_elems *dst,\n+\t\t\t     struct cfg80211_mbssid_elems *src)\n+{\n+\tint i, offset = 0;\n+\n+\tfor (i = 0; i < src->cnt; i++) {\n+\t\tmemcpy(pos + offset, src->elem[i].data, src->elem[i].len);\n+\t\tdst->elem[i].len = src->elem[i].len;\n+\t\tdst->elem[i].data = pos + offset;\n+\t\toffset += dst->elem[i].len;\n+\t}\n+\tdst->cnt = src->cnt;\n+\n+\treturn offset;\n+}\n+\n static int ieee80211_assign_beacon(struct ieee80211_sub_if_data *sdata,\n \t\t\t\t   struct cfg80211_beacon_data *params,\n \t\t\t\t   const struct ieee80211_csa_settings *csa,\n \t\t\t\t   const struct ieee80211_color_change_settings *cca)\n {\n+\tstruct cfg80211_mbssid_elems *mbssid = NULL;\n \tstruct beacon_data *new, *old;\n \tint new_head_len, new_tail_len;\n \tint size, err;\n@@ -1021,6 +1039,17 @@ static int ieee80211_assign_beacon(struc\n \n \tsize = sizeof(*new) + new_head_len + new_tail_len;\n \n+\t/* new or old multiple BSSID elements? */\n+\tif (params->mbssid_ies) {\n+\t\tmbssid = params->mbssid_ies;\n+\t\tsize += struct_size(new->mbssid_ies, elem, mbssid->cnt);\n+\t\tsize += ieee80211_get_mbssid_beacon_len(mbssid);\n+\t} else if (old && old->mbssid_ies) {\n+\t\tmbssid = old->mbssid_ies;\n+\t\tsize += struct_size(new->mbssid_ies, elem, mbssid->cnt);\n+\t\tsize += ieee80211_get_mbssid_beacon_len(mbssid);\n+\t}\n+\n \tnew = kzalloc(size, GFP_KERNEL);\n \tif (!new)\n \t\treturn -ENOMEM;\n@@ -1029,12 +1058,20 @@ static int ieee80211_assign_beacon(struc\n \n \t/*\n \t * pointers go into the block we allocated,\n-\t * memory is | beacon_data | head | tail |\n+\t * memory is | beacon_data | head | tail | mbssid_ies\n \t */\n \tnew->head = ((u8 *) new) + sizeof(*new);\n \tnew->tail = new->head + new_head_len;\n \tnew->head_len = new_head_len;\n \tnew->tail_len = new_tail_len;\n+\t/* copy in optional mbssid_ies */\n+\tif (mbssid) {\n+\t\tu8 *pos = new->tail + new->tail_len;\n+\n+\t\tnew->mbssid_ies = (void *)pos;\n+\t\tpos += struct_size(new->mbssid_ies, elem, mbssid->cnt);\n+\t\tieee80211_copy_mbssid_beacon(pos, new->mbssid_ies, mbssid);\n+\t}\n \n \tif (csa) {\n \t\tnew->cntdwn_current_counter = csa->count;\n@@ -1332,8 +1369,11 @@ static int ieee80211_stop_ap(struct wiph\n \n \tmutex_unlock(&local->mtx);\n \n-\tkfree(sdata->u.ap.next_beacon);\n-\tsdata->u.ap.next_beacon = NULL;\n+\tif (sdata->u.ap.next_beacon) {\n+\t\tkfree(sdata->u.ap.next_beacon->mbssid_ies);\n+\t\tkfree(sdata->u.ap.next_beacon);\n+\t\tsdata->u.ap.next_beacon = NULL;\n+\t}\n \n \t/* turn off carrier for this interface and dependent VLANs */\n \tlist_for_each_entry(vlan, &sdata->u.ap.vlans, u.vlan.list)\n@@ -3126,12 +3166,24 @@ cfg80211_beacon_dup(struct cfg80211_beac\n \n \tlen = beacon->head_len + beacon->tail_len + beacon->beacon_ies_len +\n \t      beacon->proberesp_ies_len + beacon->assocresp_ies_len +\n-\t      beacon->probe_resp_len + beacon->lci_len + beacon->civicloc_len;\n+\t      beacon->probe_resp_len + beacon->lci_len + beacon->civicloc_len +\n+\t      ieee80211_get_mbssid_beacon_len(beacon->mbssid_ies);\n \n \tnew_beacon = kzalloc(sizeof(*new_beacon) + len, GFP_KERNEL);\n \tif (!new_beacon)\n \t\treturn NULL;\n \n+\tif (beacon->mbssid_ies && beacon->mbssid_ies->cnt) {\n+\t\tnew_beacon->mbssid_ies =\n+\t\t\tkzalloc(struct_size(new_beacon->mbssid_ies,\n+\t\t\t\t\t    elem, beacon->mbssid_ies->cnt),\n+\t\t\t\tGFP_KERNEL);\n+\t\tif (!new_beacon->mbssid_ies) {\n+\t\t\tkfree(new_beacon);\n+\t\t\treturn NULL;\n+\t\t}\n+\t}\n+\n \tpos = (u8 *)(new_beacon + 1);\n \tif (beacon->head_len) {\n \t\tnew_beacon->head_len = beacon->head_len;\n@@ -3169,6 +3221,10 @@ cfg80211_beacon_dup(struct cfg80211_beac\n \t\tmemcpy(pos, beacon->probe_resp, beacon->probe_resp_len);\n \t\tpos += beacon->probe_resp_len;\n \t}\n+\tif (beacon->mbssid_ies && beacon->mbssid_ies->cnt)\n+\t\tpos += ieee80211_copy_mbssid_beacon(pos,\n+\t\t\t\t\t\t    new_beacon->mbssid_ies,\n+\t\t\t\t\t\t    beacon->mbssid_ies);\n \n \t/* might copy -1, meaning no changes requested */\n \tnew_beacon->ftm_responder = beacon->ftm_responder;\n@@ -3206,8 +3262,11 @@ static int ieee80211_set_after_csa_beaco\n \tcase NL80211_IFTYPE_AP:\n \t\terr = ieee80211_assign_beacon(sdata, sdata->u.ap.next_beacon,\n \t\t\t\t\t      NULL, NULL);\n-\t\tkfree(sdata->u.ap.next_beacon);\n-\t\tsdata->u.ap.next_beacon = NULL;\n+\t\tif (sdata->u.ap.next_beacon) {\n+\t\t\tkfree(sdata->u.ap.next_beacon->mbssid_ies);\n+\t\t\tkfree(sdata->u.ap.next_beacon);\n+\t\t\tsdata->u.ap.next_beacon = NULL;\n+\t\t}\n \n \t\tif (err < 0)\n \t\t\treturn err;\n@@ -3362,8 +3421,12 @@ static int ieee80211_set_csa_beacon(stru\n \t\tif ((params->n_counter_offsets_beacon >\n \t\t     IEEE80211_MAX_CNTDWN_COUNTERS_NUM) ||\n \t\t    (params->n_counter_offsets_presp >\n-\t\t     IEEE80211_MAX_CNTDWN_COUNTERS_NUM))\n+\t\t     IEEE80211_MAX_CNTDWN_COUNTERS_NUM)) {\n+\t\t\tkfree(sdata->u.ap.next_beacon->mbssid_ies);\n+\t\t\tkfree(sdata->u.ap.next_beacon);\n+\t\t\tsdata->u.ap.next_beacon = NULL;\n \t\t\treturn -EINVAL;\n+\t\t}\n \n \t\tcsa.counter_offsets_beacon = params->counter_offsets_beacon;\n \t\tcsa.counter_offsets_presp = params->counter_offsets_presp;\n@@ -3373,7 +3436,9 @@ static int ieee80211_set_csa_beacon(stru\n \n \t\terr = ieee80211_assign_beacon(sdata, &params->beacon_csa, &csa, NULL);\n \t\tif (err < 0) {\n+\t\t\tkfree(sdata->u.ap.next_beacon->mbssid_ies);\n \t\t\tkfree(sdata->u.ap.next_beacon);\n+\t\t\tsdata->u.ap.next_beacon = NULL;\n \t\t\treturn err;\n \t\t}\n \t\t*changed |= err;\n@@ -3463,8 +3528,11 @@ static int ieee80211_set_csa_beacon(stru\n static void ieee80211_color_change_abort(struct ieee80211_sub_if_data  *sdata)\n {\n \tsdata->vif.color_change_active = false;\n-\tkfree(sdata->u.ap.next_beacon);\n-\tsdata->u.ap.next_beacon = NULL;\n+\tif (sdata->u.ap.next_beacon) {\n+\t\tkfree(sdata->u.ap.next_beacon->mbssid_ies);\n+\t\tkfree(sdata->u.ap.next_beacon);\n+\t\tsdata->u.ap.next_beacon = NULL;\n+\t}\n \n \tcfg80211_color_change_aborted_notify(sdata->dev);\n }\n@@ -4202,8 +4270,11 @@ ieee80211_set_after_color_change_beacon(\n \n \t\tret = ieee80211_assign_beacon(sdata, sdata->u.ap.next_beacon,\n \t\t\t\t\t      NULL, NULL);\n-\t\tkfree(sdata->u.ap.next_beacon);\n-\t\tsdata->u.ap.next_beacon = NULL;\n+\t\tif (sdata->u.ap.next_beacon) {\n+\t\t\tkfree(sdata->u.ap.next_beacon->mbssid_ies);\n+\t\t\tkfree(sdata->u.ap.next_beacon);\n+\t\t\tsdata->u.ap.next_beacon = NULL;\n+\t\t}\n \n \t\tif (ret < 0)\n \t\t\treturn ret;\n@@ -4246,7 +4317,11 @@ ieee80211_set_color_change_beacon(struct\n \t\terr = ieee80211_assign_beacon(sdata, &params->beacon_color_change,\n \t\t\t\t\t      NULL, &color_change);\n \t\tif (err < 0) {\n-\t\t\tkfree(sdata->u.ap.next_beacon);\n+\t\t\tif (sdata->u.ap.next_beacon) {\n+\t\t\t\tkfree(sdata->u.ap.next_beacon->mbssid_ies);\n+\t\t\t\tkfree(sdata->u.ap.next_beacon);\n+\t\t\t\tsdata->u.ap.next_beacon = NULL;\n+\t\t\t}\n \t\t\treturn err;\n \t\t}\n \t\t*changed |= err;\n--- a/net/mac80211/ieee80211_i.h\n+++ b/net/mac80211/ieee80211_i.h\n@@ -261,6 +261,7 @@ struct beacon_data {\n \tstruct ieee80211_meshconf_ie *meshconf;\n \tu16 cntdwn_counter_offsets[IEEE80211_MAX_CNTDWN_COUNTERS_NUM];\n \tu8 cntdwn_current_counter;\n+\tstruct cfg80211_mbssid_elems *mbssid_ies;\n \tstruct rcu_head rcu_head;\n };\n \n@@ -1083,6 +1084,20 @@ ieee80211_vif_get_shift(struct ieee80211\n \treturn shift;\n }\n \n+static inline int\n+ieee80211_get_mbssid_beacon_len(struct cfg80211_mbssid_elems *elems)\n+{\n+\tint i, len = 0;\n+\n+\tif (!elems)\n+\t\treturn 0;\n+\n+\tfor (i = 0; i < elems->cnt; i++)\n+\t\tlen += elems->elem[i].len;\n+\n+\treturn len;\n+}\n+\n enum {\n \tIEEE80211_RX_MSG\t= 1,\n \tIEEE80211_TX_STATUS_MSG\t= 2,\n--- a/net/mac80211/tx.c\n+++ b/net/mac80211/tx.c\n@@ -5041,6 +5041,19 @@ ieee80211_beacon_get_finish(struct ieee8\n \t\t       IEEE80211_TX_CTL_FIRST_FRAGMENT;\n }\n \n+static void\n+ieee80211_beacon_add_mbssid(struct sk_buff *skb, struct beacon_data *beacon)\n+{\n+\tint i;\n+\n+\tif (!beacon->mbssid_ies)\n+\t\treturn;\n+\n+\tfor (i = 0; i < beacon->mbssid_ies->cnt; i++)\n+\t\tskb_put_data(skb, beacon->mbssid_ies->elem[i].data,\n+\t\t\t     beacon->mbssid_ies->elem[i].len);\n+}\n+\n static struct sk_buff *\n ieee80211_beacon_get_ap(struct ieee80211_hw *hw,\n \t\t\tstruct ieee80211_vif *vif,\n@@ -5054,6 +5067,7 @@ ieee80211_beacon_get_ap(struct ieee80211\n \tstruct ieee80211_if_ap *ap = &sdata->u.ap;\n \tstruct sk_buff *skb = NULL;\n \tu16 csa_off_base = 0;\n+\tint mbssid_len;\n \n \tif (beacon->cntdwn_counter_offsets[0]) {\n \t\tif (!is_template)\n@@ -5063,11 +5077,12 @@ ieee80211_beacon_get_ap(struct ieee80211\n \t}\n \n \t/* headroom, head length,\n-\t * tail length and maximum TIM length\n+\t * tail length, maximum TIM length and multiple BSSID length\n \t */\n+\tmbssid_len = ieee80211_get_mbssid_beacon_len(beacon->mbssid_ies);\n \tskb = dev_alloc_skb(local->tx_headroom + beacon->head_len +\n \t\t\t    beacon->tail_len + 256 +\n-\t\t\t    local->hw.extra_beacon_tailroom);\n+\t\t\t    local->hw.extra_beacon_tailroom + mbssid_len);\n \tif (!skb)\n \t\treturn NULL;\n \n@@ -5081,6 +5096,11 @@ ieee80211_beacon_get_ap(struct ieee80211\n \t\toffs->tim_length = skb->len - beacon->head_len;\n \t\toffs->cntdwn_counter_offs[0] = beacon->cntdwn_counter_offsets[0];\n \n+\t\tif (mbssid_len) {\n+\t\t\tieee80211_beacon_add_mbssid(skb, beacon);\n+\t\t\toffs->mbssid_off = skb->len - mbssid_len;\n+\t\t}\n+\n \t\t/* for AP the csa offsets are from tail */\n \t\tcsa_off_base = skb->len;\n \t}\n"
  },
  {
    "path": "package/kernel/mac80211/patches/subsys/325-mac80211-MBSSID-channel-switch.patch",
    "content": "From: John Crispin <john@phrozen.org>\nDate: Thu, 24 Feb 2022 12:54:59 +0100\nSubject: [PATCH] mac80211: MBSSID channel switch\n\nTrigger ieee80211_csa_finish() on the non-transmitting interfaces\nwhen channel switch concludes on the transmitting interface.\n\nCo-developed-by: Lorenzo Bianconi <lorenzo@kernel.org>\nSigned-off-by: Lorenzo Bianconi <lorenzo@kernel.org>\nCo-developed-by: Aloka Dixit <alokad@codeaurora.org>\nSigned-off-by: Aloka Dixit <alokad@codeaurora.org>\nSigned-off-by: John Crispin <john@phrozen.org>\nLink: https://lore.kernel.org/r/6fde4d7f9fa387494f46a7aa4a584478dcda06f1.1645702516.git.lorenzo@kernel.org\nSigned-off-by: Johannes Berg <johannes.berg@intel.com>\n---\n\n--- a/net/mac80211/cfg.c\n+++ b/net/mac80211/cfg.c\n@@ -3247,9 +3247,31 @@ cfg80211_beacon_dup(struct cfg80211_beac\n void ieee80211_csa_finish(struct ieee80211_vif *vif)\n {\n \tstruct ieee80211_sub_if_data *sdata = vif_to_sdata(vif);\n+\tstruct ieee80211_local *local = sdata->local;\n \n-\tieee80211_queue_work(&sdata->local->hw,\n-\t\t\t     &sdata->csa_finalize_work);\n+\trcu_read_lock();\n+\n+\tif (vif->mbssid_tx_vif == vif) {\n+\t\t/* Trigger ieee80211_csa_finish() on the non-transmitting\n+\t\t * interfaces when channel switch is received on\n+\t\t * transmitting interface\n+\t\t */\n+\t\tstruct ieee80211_sub_if_data *iter;\n+\n+\t\tlist_for_each_entry_rcu(iter, &local->interfaces, list) {\n+\t\t\tif (!ieee80211_sdata_running(iter))\n+\t\t\t\tcontinue;\n+\n+\t\t\tif (iter == sdata || iter->vif.mbssid_tx_vif != vif)\n+\t\t\t\tcontinue;\n+\n+\t\t\tieee80211_queue_work(&iter->local->hw,\n+\t\t\t\t\t     &iter->csa_finalize_work);\n+\t\t}\n+\t}\n+\tieee80211_queue_work(&local->hw, &sdata->csa_finalize_work);\n+\n+\trcu_read_unlock();\n }\n EXPORT_SYMBOL(ieee80211_csa_finish);\n \n"
  },
  {
    "path": "package/kernel/mac80211/patches/subsys/326-mac80211-update-bssid_indicator-in-ieee80211_assign_.patch",
    "content": "From: Lorenzo Bianconi <lorenzo@kernel.org>\nDate: Thu, 24 Feb 2022 12:55:00 +0100\nSubject: [PATCH] mac80211: update bssid_indicator in\n ieee80211_assign_beacon\n\nUpdate bssid_indicator in ieee80211_bss_conf according to the\nnumber of bssid in the set.\n\nSigned-off-by: Lorenzo Bianconi <lorenzo@kernel.org>\nLink: https://lore.kernel.org/r/f92317e002fca9933f05a445fcefb4f53291d601.1645702516.git.lorenzo@kernel.org\nSigned-off-by: Johannes Berg <johannes.berg@intel.com>\n---\n\n--- a/net/mac80211/cfg.c\n+++ b/net/mac80211/cfg.c\n@@ -1071,6 +1071,9 @@ static int ieee80211_assign_beacon(struc\n \t\tnew->mbssid_ies = (void *)pos;\n \t\tpos += struct_size(new->mbssid_ies, elem, mbssid->cnt);\n \t\tieee80211_copy_mbssid_beacon(pos, new->mbssid_ies, mbssid);\n+\t\t/* update bssid_indicator */\n+\t\tsdata->vif.bss_conf.bssid_indicator =\n+\t\t\tilog2(__roundup_pow_of_two(mbssid->cnt + 1));\n \t}\n \n \tif (csa) {\n"
  },
  {
    "path": "package/kernel/mac80211/patches/subsys/329-mac80211-minstrel_ht-fix-where-rate-stats-are-stored.patch",
    "content": "From: Peter Seiderer <ps.report@gmx.net>\nDate: Mon, 4 Apr 2022 18:54:14 +0200\nSubject: [PATCH] mac80211: minstrel_ht: fix where rate stats are stored (fixes\n debugfs output)\n\nUsing an ath9k card the debugfs output of minstrel_ht looks like the following\n(note the zero values for the first four rates sum-of success/attempts):\n\n             best    ____________rate__________    ____statistics___    _____last____    ______sum-of________\nmode guard #  rate   [name   idx airtime  max_tp]  [avg(tp) avg(prob)]  [retry|suc|att]  [#success | #attempts]\nOFDM       1    DP     6.0M  272    1640     5.2       3.1      53.8       3     0 0             0   0\nOFDM       1   C       9.0M  273    1104     7.7       4.6      53.8       4     0 0             0   0\nOFDM       1  B       12.0M  274     836    10.0       6.0      53.8       4     0 0             0   0\nOFDM       1 A    S   18.0M  275     568    14.3       8.5      53.8       5     0 0             0   0\nOFDM       1      S   24.0M  276     436    18.1       0.0       0.0       5     0 1            80   1778\nOFDM       1          36.0M  277     300    24.9       0.0       0.0       0     0 1             0   107\nOFDM       1      S   48.0M  278     236    30.4       0.0       0.0       0     0 0             0   75\nOFDM       1          54.0M  279     212    33.0       0.0       0.0       0     0 0             0   72\n\nTotal packet count::    ideal 16582      lookaround 885\nAverage # of aggregated frames per A-MPDU: 1.0\n\nDebugging showed that the rate statistics for the first four rates where\nstored in the MINSTREL_CCK_GROUP instead of the MINSTREL_OFDM_GROUP because\nin minstrel_ht_get_stats() the supported check was not honoured as done in\nvarious other places, e.g net/mac80211/rc80211_minstrel_ht_debugfs.c:\n\n 74                 if (!(mi->supported[i] & BIT(j)))\n 75                         continue;\n\nWith the patch applied the output looks good:\n\n              best    ____________rate__________    ____statistics___    _____last____    ______sum-of________\nmode guard #  rate   [name   idx airtime  max_tp]  [avg(tp) avg(prob)]  [retry|suc|att]  [#success | #attempts]\nOFDM       1    D      6.0M  272    1640     5.2       5.2     100.0       3     0 0             1   1\nOFDM       1   C       9.0M  273    1104     7.7       7.7     100.0       4     0 0            38   38\nOFDM       1  B       12.0M  274     836    10.0       9.9      89.5       4     2 2           372   395\nOFDM       1 A   P    18.0M  275     568    14.3      14.3      97.2       5    52 53         6956   7181\nOFDM       1      S   24.0M  276     436    18.1       0.0       0.0       0     0 1             6   163\nOFDM       1          36.0M  277     300    24.9       0.0       0.0       0     0 1             0   35\nOFDM       1      S   48.0M  278     236    30.4       0.0       0.0       0     0 0             0   38\nOFDM       1      S   54.0M  279     212    33.0       0.0       0.0       0     0 0             0   38\n\nTotal packet count::    ideal 7097      lookaround 287\nAverage # of aggregated frames per A-MPDU: 1.0\n\nSigned-off-by: Peter Seiderer <ps.report@gmx.net>\n---\n\n--- a/net/mac80211/rc80211_minstrel_ht.c\n+++ b/net/mac80211/rc80211_minstrel_ht.c\n@@ -364,6 +364,9 @@ minstrel_ht_get_stats(struct minstrel_pr\n \n \tgroup = MINSTREL_CCK_GROUP;\n \tfor (idx = 0; idx < ARRAY_SIZE(mp->cck_rates); idx++) {\n+\t\tif (!(mi->supported[group] & BIT(idx)))\n+\t\t\tcontinue;\n+\n \t\tif (rate->idx != mp->cck_rates[idx])\n \t\t\tcontinue;\n \n"
  },
  {
    "path": "package/kernel/mac80211/patches/subsys/400-allow-ibss-mixed.patch",
    "content": "ath10k-ct starting with version 5.2 allows the combination of \nNL80211_IFTYPE_ADHOC and beacon_int_min_gcd in ath10k_10x_ct_if_comb \nwhich triggers this warning. Ben told me that this is not a big problem \nand we should ignore this.\n\n--- a/net/wireless/core.c\n+++ b/net/wireless/core.c\n@@ -625,21 +625,6 @@ static int wiphy_verify_combinations(str\n \t\t\t\t    c->limits[j].max > 1))\n \t\t\t\treturn -EINVAL;\n \n-\t\t\t/*\n-\t\t\t * This isn't well-defined right now. If you have an\n-\t\t\t * IBSS interface, then its beacon interval may change\n-\t\t\t * by joining other networks, and nothing prevents it\n-\t\t\t * from doing that.\n-\t\t\t * So technically we probably shouldn't even allow AP\n-\t\t\t * and IBSS in the same interface, but it seems that\n-\t\t\t * some drivers support that, possibly only with fixed\n-\t\t\t * beacon intervals for IBSS.\n-\t\t\t */\n-\t\t\tif (WARN_ON(types & BIT(NL80211_IFTYPE_ADHOC) &&\n-\t\t\t\t    c->beacon_int_min_gcd)) {\n-\t\t\t\treturn -EINVAL;\n-\t\t\t}\n-\n \t\t\tcnt += c->limits[j].max;\n \t\t\t/*\n \t\t\t * Don't advertise an unsupported type\n"
  },
  {
    "path": "package/kernel/mac80211/patches/subsys/500-mac80211_configure_antenna_gain.patch",
    "content": "--- a/include/net/cfg80211.h\n+++ b/include/net/cfg80211.h\n@@ -3869,6 +3869,7 @@ struct mgmt_frame_regs {\n  *\t(as advertised by the nl80211 feature flag.)\n  * @get_tx_power: store the current TX power into the dbm variable;\n  *\treturn 0 if successful\n+ * @set_antenna_gain: set antenna gain to reduce maximum tx power if necessary\n  *\n  * @rfkill_poll: polls the hw rfkill line, use cfg80211 reporting\n  *\tfunctions to adjust rfkill hw state\n@@ -4202,6 +4203,7 @@ struct cfg80211_ops {\n \t\t\t\tenum nl80211_tx_power_setting type, int mbm);\n \tint\t(*get_tx_power)(struct wiphy *wiphy, struct wireless_dev *wdev,\n \t\t\t\tint *dbm);\n+\tint\t(*set_antenna_gain)(struct wiphy *wiphy, int dbi);\n \n \tvoid\t(*rfkill_poll)(struct wiphy *wiphy);\n \n--- a/include/net/mac80211.h\n+++ b/include/net/mac80211.h\n@@ -1566,6 +1566,7 @@ enum ieee80211_smps_mode {\n  *\n  * @power_level: requested transmit power (in dBm), backward compatibility\n  *\tvalue only that is set to the minimum of all interfaces\n+ * @max_antenna_gain: maximum antenna gain adjusted by user config (in dBi)\n  *\n  * @chandef: the channel definition to tune to\n  * @radar_enabled: whether radar detection is enabled\n@@ -1586,6 +1587,7 @@ enum ieee80211_smps_mode {\n struct ieee80211_conf {\n \tu32 flags;\n \tint power_level, dynamic_ps_timeout;\n+\tint max_antenna_gain;\n \n \tu16 listen_interval;\n \tu8 ps_dtim_period;\n--- a/include/uapi/linux/nl80211.h\n+++ b/include/uapi/linux/nl80211.h\n@@ -2615,6 +2615,9 @@ enum nl80211_commands {\n  *\tswitching on a different channel during CAC detection on the selected\n  *\tradar channel.\n  *\n+ * @NL80211_ATTR_WIPHY_ANTENNA_GAIN: Configured antenna gain. Used to reduce\n+ *\ttransmit power to stay within regulatory limits. u32, dBi.\n+ *\n  * @NUM_NL80211_ATTR: total number of nl80211_attrs available\n  * @NL80211_ATTR_MAX: highest attribute number currently defined\n  * @__NL80211_ATTR_AFTER_LAST: internal use\n@@ -3123,6 +3126,8 @@ enum nl80211_attrs {\n \n \tNL80211_ATTR_RADAR_BACKGROUND,\n \n+\tNL80211_ATTR_WIPHY_ANTENNA_GAIN,\n+\n \t/* add attributes here, update the policy in nl80211.c */\n \n \t__NL80211_ATTR_AFTER_LAST,\n--- a/net/mac80211/cfg.c\n+++ b/net/mac80211/cfg.c\n@@ -2845,6 +2845,19 @@ static int ieee80211_get_tx_power(struct\n \treturn 0;\n }\n \n+static int ieee80211_set_antenna_gain(struct wiphy *wiphy, int dbi)\n+{\n+\tstruct ieee80211_local *local = wiphy_priv(wiphy);\n+\n+\tif (dbi < 0)\n+\t\treturn -EINVAL;\n+\n+\tlocal->user_antenna_gain = dbi;\n+\tieee80211_hw_config(local, 0);\n+\n+\treturn 0;\n+}\n+\n static void ieee80211_rfkill_poll(struct wiphy *wiphy)\n {\n \tstruct ieee80211_local *local = wiphy_priv(wiphy);\n@@ -4549,6 +4562,7 @@ const struct cfg80211_ops mac80211_confi\n \t.set_wiphy_params = ieee80211_set_wiphy_params,\n \t.set_tx_power = ieee80211_set_tx_power,\n \t.get_tx_power = ieee80211_get_tx_power,\n+\t.set_antenna_gain = ieee80211_set_antenna_gain,\n \t.rfkill_poll = ieee80211_rfkill_poll,\n \tCFG80211_TESTMODE_CMD(ieee80211_testmode_cmd)\n \tCFG80211_TESTMODE_DUMP(ieee80211_testmode_dump)\n--- a/net/mac80211/ieee80211_i.h\n+++ b/net/mac80211/ieee80211_i.h\n@@ -1464,6 +1464,7 @@ struct ieee80211_local {\n \tint dynamic_ps_forced_timeout;\n \n \tint user_power_level; /* in dBm, for all interfaces */\n+\tint user_antenna_gain; /* in dBi */\n \n \tenum ieee80211_smps_mode smps_mode;\n \n--- a/net/mac80211/main.c\n+++ b/net/mac80211/main.c\n@@ -96,7 +96,7 @@ static u32 ieee80211_hw_conf_chan(struct\n \tstruct ieee80211_sub_if_data *sdata;\n \tstruct cfg80211_chan_def chandef = {};\n \tu32 changed = 0;\n-\tint power;\n+\tint power, max_power;\n \tu32 offchannel_flag;\n \n \toffchannel_flag = local->hw.conf.flags & IEEE80211_CONF_OFFCHANNEL;\n@@ -157,6 +157,12 @@ static u32 ieee80211_hw_conf_chan(struct\n \t}\n \trcu_read_unlock();\n \n+\tmax_power = chandef.chan->max_reg_power;\n+\tif (local->user_antenna_gain > 0) {\n+\t\tmax_power -= local->user_antenna_gain;\n+\t\tpower = min(power, max_power);\n+\t}\n+\n \tif (local->hw.conf.power_level != power) {\n \t\tchanged |= IEEE80211_CONF_CHANGE_POWER;\n \t\tlocal->hw.conf.power_level = power;\n@@ -679,6 +685,7 @@ struct ieee80211_hw *ieee80211_alloc_hw_\n \t\t\t\t\t IEEE80211_RADIOTAP_MCS_HAVE_BW;\n \tlocal->hw.radiotap_vht_details = IEEE80211_RADIOTAP_VHT_KNOWN_GI |\n \t\t\t\t\t IEEE80211_RADIOTAP_VHT_KNOWN_BANDWIDTH;\n+\tlocal->user_antenna_gain = 0;\n \tlocal->hw.uapsd_queues = IEEE80211_DEFAULT_UAPSD_QUEUES;\n \tlocal->hw.uapsd_max_sp_len = IEEE80211_DEFAULT_MAX_SP_LEN;\n \tlocal->hw.max_mtu = IEEE80211_MAX_DATA_LEN;\n--- a/net/wireless/nl80211.c\n+++ b/net/wireless/nl80211.c\n@@ -797,6 +797,7 @@ static const struct nla_policy nl80211_p\n \t\t\tNLA_POLICY_NESTED(nl80211_mbssid_config_policy),\n \t[NL80211_ATTR_MBSSID_ELEMS] = { .type = NLA_NESTED },\n \t[NL80211_ATTR_RADAR_BACKGROUND] = { .type = NLA_FLAG },\n+\t[NL80211_ATTR_WIPHY_ANTENNA_GAIN] = { .type = NLA_U32 },\n };\n \n /* policy for the key attributes */\n@@ -3377,6 +3378,22 @@ static int nl80211_set_wiphy(struct sk_b\n \t\tif (result)\n \t\t\tgoto out;\n \t}\n+\n+\tif (info->attrs[NL80211_ATTR_WIPHY_ANTENNA_GAIN]) {\n+\t\tint idx, dbi = 0;\n+\n+\t\tif (!rdev->ops->set_antenna_gain) {\n+\t\t\tresult = -EOPNOTSUPP;\n+\t\t\tgoto out;\n+\t\t}\n+\n+\t\tidx = NL80211_ATTR_WIPHY_ANTENNA_GAIN;\n+\t\tdbi = nla_get_u32(info->attrs[idx]);\n+\n+\t\tresult = rdev->ops->set_antenna_gain(&rdev->wiphy, dbi);\n+\t\tif (result)\n+\t\t\tgoto out;\n+\t}\n \n \tif (info->attrs[NL80211_ATTR_WIPHY_TX_POWER_SETTING]) {\n \t\tstruct wireless_dev *txp_wdev = wdev;\n"
  },
  {
    "path": "package/kernel/mac80211/patches/subsys/782-net-next-1-of-net-pass-the-dst-buffer-to-of_get_mac_address.patch",
    "content": "--- a/backport-include/linux/of_net.h\n+++ /dev/null\n@@ -1,26 +0,0 @@\n-#ifndef _BP_OF_NET_H\n-#define _BP_OF_NET_H\n-#include_next <linux/of_net.h>\n-#include <linux/version.h>\n-#include <linux/etherdevice.h>\n-\n-/* The behavior of of_get_mac_address() changed in kernel 5.2, it now\n- * returns an error code and not NULL in case of an error.\n- */\n-#if LINUX_VERSION_IS_LESS(5,13,0)\n-static inline int backport_of_get_mac_address(struct device_node *np, u8 *mac_out)\n-{\n-\tconst void *mac = of_get_mac_address(np);\n-\n-\tif (!mac)\n-\t\treturn -ENODEV;\n-\tif (IS_ERR(mac))\n-\t\treturn PTR_ERR(mac);\n-\tether_addr_copy(mac_out, mac);\n-\t\n-\treturn 0;\n-}\n-#define of_get_mac_address LINUX_BACKPORT(of_get_mac_address)\n-#endif /* < 5.2 */\n-\n-#endif /* _BP_OF_NET_H */\n"
  },
  {
    "path": "package/kernel/mac80211/ralink.mk",
    "content": "PKG_DRIVERS += \\\n\trt2x00-lib rt2x00-pci rt2x00-usb rt2x00-mmio \\\n\trt2400-pci rt2500-pci rt2500-usb \\\n\trt2800-lib rt2800-mmio rt2800-pci rt2800-soc rt2800-usb \\\n\trt61-pci rt73-usb\n\nPKG_CONFIG_DEPENDS += \\\n\tCONFIG_PACKAGE_RT2X00_LIB_DEBUGFS \\\n\tCONFIG_PACKAGE_RT2X00_DEBUG\n\nconfig-$(call config_package,rt2x00-lib) += RT2X00 RT2X00_LIB\nconfig-$(call config_package,rt2x00-pci) += RT2X00_LIB_PCI\nconfig-$(call config_package,rt2x00-mmio) += RT2X00_LIB_MMIO\nconfig-$(call config_package,rt2x00-usb) += RT2X00_LIB_USB\nconfig-$(CONFIG_PACKAGE_RT2X00_LIB_DEBUGFS) += RT2X00_LIB_DEBUGFS\nconfig-$(CONFIG_PACKAGE_RT2X00_DEBUG) += RT2X00_DEBUG\n\nconfig-$(call config_package,rt2400-pci) += RT2400PCI\nconfig-$(call config_package,rt2500-pci) += RT2500PCI\nconfig-$(call config_package,rt2500-usb) += RT2500USB\nconfig-$(call config_package,rt61-pci) += RT61PCI\nconfig-$(call config_package,rt73-usb) += RT73USB\n\nconfig-$(call config_package,rt2800-lib) += RT2800_LIB\n\nconfig-$(call config_package,rt2800-soc) += RT2800SOC\nconfig-$(call config_package,rt2800-pci) += RT2800PCI\nconfig-y += RT2800PCI_RT33XX RT2800PCI_RT35XX RT2800PCI_RT53XX RT2800PCI_RT3290\n\nconfig-$(call config_package,rt2800-usb) += RT2800USB\nconfig-y += RT2800USB_RT33XX RT2800USB_RT35XX RT2800USB_RT3573 RT2800USB_RT53XX RT2800USB_RT55XX RT2800USB_UNKNOWN\n\ndefine KernelPackage/rt2x00/Default\n  $(call KernelPackage/mac80211/Default)\n  TITLE:=Ralink Drivers for RT2x00 cards\nendef\n\ndefine KernelPackage/rt2x00-lib\n$(call KernelPackage/rt2x00/Default)\n  DEPENDS+= @(PCI_SUPPORT||USB_SUPPORT||TARGET_ramips) +kmod-mac80211\n  TITLE+= (LIB)\n  FILES:=$(PKG_BUILD_DIR)/drivers/net/wireless/ralink/rt2x00/rt2x00lib.ko\n  MENU:=1\nendef\n\ndefine KernelPackage/rt2x00-lib/config\n  if PACKAGE_kmod-rt2x00-lib\n\n\tconfig PACKAGE_RT2X00_LIB_DEBUGFS\n\t\tbool \"Enable rt2x00 debugfs support\"\n\t\tdepends on PACKAGE_MAC80211_DEBUGFS\n\t\thelp\n\t\t  Enable creation of debugfs files for the rt2x00 drivers.\n\t\t  These debugfs files support both reading and writing of the\n\t\t  most important register types of the rt2x00 hardware.\n\n\tconfig PACKAGE_RT2X00_DEBUG\n\t\tbool \"Enable rt2x00 debug output\"\n\t\thelp\n\t\t  Enable debugging output for all rt2x00 modules\n\n  endif\nendef\n\ndefine KernelPackage/rt2x00-mmio\n$(call KernelPackage/rt2x00/Default)\n  DEPENDS+= @(PCI_SUPPORT||TARGET_ramips) +kmod-rt2x00-lib\n  HIDDEN:=1\n  TITLE+= (MMIO)\n  FILES:= $(PKG_BUILD_DIR)/drivers/net/wireless/ralink/rt2x00/rt2x00mmio.ko\nendef\n\ndefine KernelPackage/rt2x00-pci\n$(call KernelPackage/rt2x00/Default)\n  DEPENDS+= @PCI_SUPPORT +kmod-rt2x00-mmio +kmod-rt2x00-lib\n  HIDDEN:=1\n  TITLE+= (PCI)\n  FILES:= $(PKG_BUILD_DIR)/drivers/net/wireless/ralink/rt2x00/rt2x00pci.ko\n  AUTOLOAD:=$(call AutoProbe,rt2x00pci)\nendef\n\ndefine KernelPackage/rt2x00-usb\n$(call KernelPackage/rt2x00/Default)\n  DEPENDS+= @USB_SUPPORT +kmod-rt2x00-lib +kmod-usb-core\n  HIDDEN:=1\n  TITLE+= (USB)\n  FILES:=$(PKG_BUILD_DIR)/drivers/net/wireless/ralink/rt2x00/rt2x00usb.ko\n  AUTOLOAD:=$(call AutoProbe,rt2x00usb)\nendef\n\ndefine KernelPackage/rt2800-lib\n$(call KernelPackage/rt2x00/Default)\n  DEPENDS+= @(PCI_SUPPORT||USB_SUPPORT||TARGET_ramips) +kmod-rt2x00-lib +kmod-lib-crc-ccitt +@DRIVER_11N_SUPPORT\n  HIDDEN:=1\n  TITLE+= (rt2800 LIB)\n  FILES:=$(PKG_BUILD_DIR)/drivers/net/wireless/ralink/rt2x00/rt2800lib.ko\nendef\n\ndefine KernelPackage/rt2400-pci\n$(call KernelPackage/rt2x00/Default)\n  DEPENDS+= @PCI_SUPPORT +kmod-rt2x00-pci +kmod-eeprom-93cx6\n  TITLE+= (RT2400 PCI)\n  FILES:=$(PKG_BUILD_DIR)/drivers/net/wireless/ralink/rt2x00/rt2400pci.ko\n  AUTOLOAD:=$(call AutoProbe,rt2400pci)\nendef\n\ndefine KernelPackage/rt2500-pci\n$(call KernelPackage/rt2x00/Default)\n  DEPENDS+= @PCI_SUPPORT +kmod-rt2x00-pci +kmod-eeprom-93cx6\n  TITLE+= (RT2500 PCI)\n  FILES:=$(PKG_BUILD_DIR)/drivers/net/wireless/ralink/rt2x00/rt2500pci.ko\n  AUTOLOAD:=$(call AutoProbe,rt2500pci)\nendef\n\ndefine KernelPackage/rt2500-usb\n$(call KernelPackage/rt2x00/Default)\n  DEPENDS+= @USB_SUPPORT +kmod-rt2x00-usb\n  TITLE+= (RT2500 USB)\n  FILES:=$(PKG_BUILD_DIR)/drivers/net/wireless/ralink/rt2x00/rt2500usb.ko\n  AUTOLOAD:=$(call AutoProbe,rt2500usb)\nendef\n\ndefine KernelPackage/rt2800-mmio\n$(call KernelPackage/rt2x00/Default)\n  TITLE += (RT28xx/RT3xxx MMIO)\n  DEPENDS += +kmod-rt2800-lib +kmod-rt2x00-mmio\n  HIDDEN:=1\n  FILES:=$(PKG_BUILD_DIR)/drivers/net/wireless/ralink/rt2x00/rt2800mmio.ko\nendef\n\ndefine KernelPackage/rt2800-soc\n$(call KernelPackage/rt2x00/Default)\n  DEPENDS += @(TARGET_ramips_rt288x||TARGET_ramips_rt305x||TARGET_ramips_rt3883||TARGET_ramips_mt7620) +kmod-rt2800-mmio +kmod-rt2800-lib\n  TITLE += (RT28xx/RT3xxx SoC)\n  FILES := \\\n\t$(PKG_BUILD_DIR)/drivers/net/wireless/ralink/rt2x00/rt2x00soc.ko \\\n\t$(PKG_BUILD_DIR)/drivers/net/wireless/ralink/rt2x00/rt2800soc.ko\n  AUTOLOAD:=$(call AutoProbe,rt2800soc)\nendef\n\ndefine KernelPackage/rt2800-pci\n$(call KernelPackage/rt2x00/Default)\n  DEPENDS+= @PCI_SUPPORT +kmod-rt2x00-pci +kmod-rt2800-lib +kmod-rt2800-mmio +kmod-eeprom-93cx6 +rt2800-pci-firmware\n  TITLE+= (RT2860 PCI)\n  FILES:=$(PKG_BUILD_DIR)/drivers/net/wireless/ralink/rt2x00/rt2800pci.ko\n  AUTOLOAD:=$(call AutoProbe,rt2800pci)\nendef\n\ndefine KernelPackage/rt2800-usb\n$(call KernelPackage/rt2x00/Default)\n  DEPENDS+= @USB_SUPPORT +kmod-rt2x00-usb +kmod-rt2800-lib +kmod-lib-crc-ccitt +rt2800-usb-firmware\n  TITLE+= (RT2870 USB)\n  FILES:=$(PKG_BUILD_DIR)/drivers/net/wireless/ralink/rt2x00/rt2800usb.ko\n  AUTOLOAD:=$(call AutoProbe,rt2800usb)\nendef\n\n\ndefine KernelPackage/rt61-pci\n$(call KernelPackage/rt2x00/Default)\n  DEPENDS+= @PCI_SUPPORT +kmod-rt2x00-pci +kmod-eeprom-93cx6 +kmod-lib-crc-itu-t +rt61-pci-firmware\n  TITLE+= (RT2x61 PCI)\n  FILES:=$(PKG_BUILD_DIR)/drivers/net/wireless/ralink/rt2x00/rt61pci.ko\n  AUTOLOAD:=$(call AutoProbe,rt61pci)\nendef\n\ndefine KernelPackage/rt73-usb\n  $(call KernelPackage/rt2x00/Default)\n  DEPENDS+= @USB_SUPPORT +kmod-rt2x00-usb +kmod-lib-crc-itu-t +rt73-usb-firmware\n  TITLE+= (RT73 USB)\n  FILES:=$(PKG_BUILD_DIR)/drivers/net/wireless/ralink/rt2x00/rt73usb.ko\n  AUTOLOAD:=$(call AutoProbe,rt73usb)\nendef\n"
  },
  {
    "path": "package/kernel/mac80211/realtek.mk",
    "content": "PKG_DRIVERS += \\\n\trtl8180 rtl8187 \\\n\trtlwifi rtlwifi-pci rtlwifi-btcoexist rtlwifi-usb rtl8192c-common \\\n\trtl8192ce rtl8192se rtl8192de rtl8192cu rtl8723bs rtl8821ae \\\n\trtl8xxxu rtw88\n\nconfig-$(call config_package,rtl8180) += RTL8180\nconfig-$(call config_package,rtl8187) += RTL8187\n\nconfig-$(call config_package,rtlwifi) += RTL_CARDS RTLWIFI\nconfig-$(call config_package,rtlwifi-pci) += RTLWIFI_PCI\nconfig-$(call config_package,rtlwifi-btcoexist) += RTLBTCOEXIST\nconfig-$(call config_package,rtlwifi-usb) += RTLWIFI_USB\nconfig-$(call config_package,rtl8192c-common) += RTL8192C_COMMON\nconfig-$(call config_package,rtl8192ce) += RTL8192CE\nconfig-$(call config_package,rtl8192se) += RTL8192SE\nconfig-$(call config_package,rtl8192de) += RTL8192DE\nconfig-$(call config_package,rtl8192cu) += RTL8192CU\nconfig-$(call config_package,rtl8821ae) += RTL8821AE\nconfig-$(CONFIG_PACKAGE_RTLWIFI_DEBUG) += RTLWIFI_DEBUG\n\nconfig-$(call config_package,rtl8xxxu) += RTL8XXXU\nconfig-y += RTL8XXXU_UNTESTED\n\nconfig-$(call config_package,rtl8723bs) += RTL8723BS\nconfig-y += STAGING\n\nconfig-$(call config_package,rtw88) += RTW88 RTW88_CORE RTW88_PCI\nconfig-y += RTW88_8822BE RTW88_8822CE RTW88_8723DE\nconfig-$(CONFIG_PACKAGE_RTW88_DEBUG) += RTW88_DEBUG\nconfig-$(CONFIG_PACKAGE_RTW88_DEBUGFS) += RTW88_DEBUGFS\n\ndefine KernelPackage/rtl818x/Default\n  $(call KernelPackage/mac80211/Default)\n  TITLE:=Realtek Drivers for RTL818x devices\n  URL:=https://wireless.wiki.kernel.org/en/users/drivers/rtl8187\n  DEPENDS+= +kmod-eeprom-93cx6 +kmod-mac80211\nendef\n\ndefine KernelPackage/rtl8180\n  $(call KernelPackage/rtl818x/Default)\n  DEPENDS+= @PCI_SUPPORT\n  TITLE+= (RTL8180 PCI)\n  FILES:=$(PKG_BUILD_DIR)/drivers/net/wireless/realtek/rtl818x/rtl8180/rtl818x_pci.ko\n  AUTOLOAD:=$(call AutoProbe,rtl818x_pci)\nendef\n\ndefine KernelPackage/rtl8187\n$(call KernelPackage/rtl818x/Default)\n  DEPENDS+= @USB_SUPPORT +kmod-usb-core\n  TITLE+= (RTL8187 USB)\n  FILES:=$(PKG_BUILD_DIR)/drivers/net/wireless/realtek/rtl818x/rtl8187/rtl8187.ko\n  AUTOLOAD:=$(call AutoProbe,rtl8187)\nendef\n\ndefine KernelPackage/rtlwifi/config\n\tconfig PACKAGE_RTLWIFI_DEBUG\n\t\tbool \"Realtek wireless debugging\"\n\t\tdepends on PACKAGE_kmod-rtlwifi\n\t\thelp\n\t\t  Say Y, if you want to debug realtek wireless drivers.\n\nendef\n\ndefine KernelPackage/rtlwifi\n  $(call KernelPackage/mac80211/Default)\n  TITLE:=Realtek common driver part\n  DEPENDS+= @(PCI_SUPPORT||USB_SUPPORT) +kmod-mac80211 +@DRIVER_11N_SUPPORT\n  FILES:=$(PKG_BUILD_DIR)/drivers/net/wireless/realtek/rtlwifi/rtlwifi.ko\n  HIDDEN:=1\nendef\n\ndefine KernelPackage/rtlwifi-pci\n  $(call KernelPackage/mac80211/Default)\n  TITLE:=Realtek common driver part (PCI support)\n  DEPENDS+= @PCI_SUPPORT +kmod-rtlwifi\n  FILES:=$(PKG_BUILD_DIR)/drivers/net/wireless/realtek/rtlwifi/rtl_pci.ko\n  AUTOLOAD:=$(call AutoProbe,rtl_pci)\n  HIDDEN:=1\nendef\n\ndefine KernelPackage/rtlwifi-btcoexist\n  $(call KernelPackage/mac80211/Default)\n  TITLE:=Realtek BT coexist support\n  DEPENDS+= +kmod-rtlwifi\n  FILES:=$(PKG_BUILD_DIR)/drivers/net/wireless/realtek/rtlwifi/btcoexist/btcoexist.ko\n  AUTOLOAD:=$(call AutoProbe,btcoexist)\n  HIDDEN:=1\nendef\n\ndefine KernelPackage/rtlwifi-usb\n  $(call KernelPackage/mac80211/Default)\n  TITLE:=Realtek common driver part (USB support)\n  DEPENDS+= @USB_SUPPORT +kmod-usb-core +kmod-rtlwifi\n  FILES:=$(PKG_BUILD_DIR)/drivers/net/wireless/realtek/rtlwifi/rtl_usb.ko\n  AUTOLOAD:=$(call AutoProbe,rtl_usb)\n  HIDDEN:=1\nendef\n\ndefine KernelPackage/rtl8192c-common\n  $(call KernelPackage/mac80211/Default)\n  TITLE:=Realtek RTL8192CE/RTL8192CU common support module\n  DEPENDS+= +kmod-rtlwifi\n  FILES:= $(PKG_BUILD_DIR)/drivers/net/wireless/realtek/rtlwifi/rtl8192c/rtl8192c-common.ko\n  HIDDEN:=1\nendef\n\ndefine KernelPackage/rtl8192ce\n  $(call KernelPackage/mac80211/Default)\n  TITLE:=Realtek RTL8192CE/RTL8188CE support\n  DEPENDS+= +kmod-rtlwifi-pci +kmod-rtl8192c-common +rtl8192ce-firmware\n  FILES:= $(PKG_BUILD_DIR)/drivers/net/wireless/realtek/rtlwifi/rtl8192ce/rtl8192ce.ko\n  AUTOLOAD:=$(call AutoProbe,rtl8192ce)\nendef\n\ndefine KernelPackage/rtl8192se\n  $(call KernelPackage/mac80211/Default)\n  TITLE:=Realtek RTL8192SE/RTL8191SE support\n  DEPENDS+= +kmod-rtlwifi-pci +rtl8192se-firmware\n  FILES:=$(PKG_BUILD_DIR)/drivers/net/wireless/realtek/rtlwifi/rtl8192se/rtl8192se.ko\n  AUTOLOAD:=$(call AutoProbe,rtl8192se)\nendef\n\ndefine KernelPackage/rtl8192de\n  $(call KernelPackage/mac80211/Default)\n  TITLE:=Realtek RTL8192DE/RTL8188DE support\n  DEPENDS+= +kmod-rtlwifi-pci +rtl8192de-firmware\n  FILES:= $(PKG_BUILD_DIR)/drivers/net/wireless/realtek/rtlwifi/rtl8192de/rtl8192de.ko\n  AUTOLOAD:=$(call AutoProbe,rtl8192de)\nendef\n\ndefine KernelPackage/rtl8192cu\n  $(call KernelPackage/mac80211/Default)\n  TITLE:=Realtek RTL8192CU/RTL8188CU support\n  DEPENDS+= +kmod-rtlwifi-usb +kmod-rtl8192c-common +rtl8192cu-firmware\n  FILES:= $(PKG_BUILD_DIR)/drivers/net/wireless/realtek/rtlwifi/rtl8192cu/rtl8192cu.ko\n  AUTOLOAD:=$(call AutoProbe,rtl8192cu)\nendef\n\ndefine KernelPackage/rtl8821ae\n  $(call KernelPackage/mac80211/Default)\n  TITLE:=Realtek RTL8821AE support\n  DEPENDS+= +kmod-rtlwifi-btcoexist +kmod-rtlwifi-pci +rtl8821ae-firmware\n  FILES:= $(PKG_BUILD_DIR)/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/rtl8821ae.ko\n  AUTOLOAD:=$(call AutoProbe,rtl8821ae)\nendef\n\ndefine KernelPackage/rtl8xxxu\n  $(call KernelPackage/mac80211/Default)\n  TITLE:=alternative Realtek RTL8XXXU support\n  DEPENDS+= @USB_SUPPORT +kmod-usb-core +kmod-mac80211\n  FILES:= $(PKG_BUILD_DIR)/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.ko\n  AUTOLOAD:=$(call AutoProbe,rtl8xxxu)\nendef\n\ndefine KernelPackage/rtl8xxxu/description\n  This is an alternative driver for various Realtek RTL8XXX\n  parts written to utilize the Linux mac80211 stack.\n  The driver is known to work with a number of RTL8723AU,\n  RL8188CU, RTL8188RU, RTL8191CU, and RTL8192CU devices\n\n  This driver is under development and has a limited feature\n  set. In particular it does not yet support 40MHz channels\n  and power management. However it should have a smaller\n  memory footprint than the vendor drivers and benetifs\n  from the in kernel mac80211 stack.\n\n  It can coexist with drivers from drivers/staging/rtl8723au,\n  drivers/staging/rtl8192u, and drivers/net/wireless/rtlwifi,\n  but you will need to control which module you wish to load.\n\n  RTL8XXXU_UNTESTED is enabled\n  This option enables detection of Realtek 8723/8188/8191/8192 WiFi\n  USB devices which have not been tested directly by the driver\n  author or reported to be working by third parties.\n\n  Please report your results!\nendef\n\ndefine KernelPackage/rtw88/config\n\tconfig PACKAGE_RTW88_DEBUG\n\t\tbool \"Realtek wireless debugging (rtw88)\"\n\t\tdepends on PACKAGE_kmod-rtw88\n\t\thelp\n\t\t  Enable debugging output for rtw88 devices\n\n\tconfig PACKAGE_RTW88_DEBUGFS\n\t\tbool \"Enable rtw88 debugfS support\"\n\t\tselect KERNEL_DEBUG_FS\n\t\tdepends on PACKAGE_kmod-rtw88\n\t\thelp\n\t\t  Select this to see extensive information about\n\t\t  the internal state of rtw88 in debugfs.\nendef\n\ndefine KernelPackage/rtw88\n  $(call KernelPackage/mac80211/Default)\n  TITLE:=Realtek RTL8822BE/RTL8822CE/RTL8723DE\n  DEPENDS+= @(PCI_SUPPORT) +kmod-mac80211 +@DRIVER_11AC_SUPPORT +@DRIVER_11N_SUPPORT\n  FILES:=\\\n\t$(PKG_BUILD_DIR)/drivers/net/wireless/realtek/rtw88/rtw88_8822be.ko \\\n\t$(PKG_BUILD_DIR)/drivers/net/wireless/realtek/rtw88/rtw88_8822b.ko \\\n\t$(PKG_BUILD_DIR)/drivers/net/wireless/realtek/rtw88/rtw88_8822ce.ko \\\n\t$(PKG_BUILD_DIR)/drivers/net/wireless/realtek/rtw88/rtw88_8822c.ko \\\n\t$(PKG_BUILD_DIR)/drivers/net/wireless/realtek/rtw88/rtw88_8723de.ko \\\n\t$(PKG_BUILD_DIR)/drivers/net/wireless/realtek/rtw88/rtw88_8723d.ko \\\n\t$(PKG_BUILD_DIR)/drivers/net/wireless/realtek/rtw88/rtw88_core.ko \\\n\t$(PKG_BUILD_DIR)/drivers/net/wireless/realtek/rtw88/rtw88_pci.ko\n  AUTOLOAD:=$(call AutoProbe,rtw88_8822be rtw88_8822ce rtw88_8723de)\nendef\n\ndefine KernelPackage/rtl8723bs\n  $(call KernelPackage/mac80211/Default)\n  TITLE:=Realtek RTL8723BS SDIO Wireless LAN NIC driver (staging)\n  DEPENDS+=+kmod-mmc +kmod-mac80211\n  FILES:=$(PKG_BUILD_DIR)/drivers/staging/rtl8723bs/r8723bs.ko\n  AUTOLOAD:=$(call AutoProbe,r8723bs)\nendef\n\ndefine KernelPackage/rtl8723bs/description\n This option enables support for RTL8723BS SDIO drivers, such as the wifi found\n on the 1st gen Intel Compute Stick, the CHIP and many other Intel Atom and ARM\n based devices.\nendef\n"
  },
  {
    "path": "package/kernel/mac80211/scripts/import-backports.sh",
    "content": "#!/usr/bin/env bash\nBASE=$1; shift\n\nusage() {\n\techo \"Usage: $0 NNN <file>...\"\n\texit 1\n}\n\ncheck_number() {\n\tcase \"$1\" in\n\t\t[0-9][0-9][0-9]) return 0;;\n\tesac\n\treturn 1;\n}\n\npatch_header()\n{\n\tawk '\n\t/^(---|\\*\\*\\*|Index:)[ \\t][^ \\t]|^diff -/ \\\n\t\t{ exit }\n\t\t{ print }\n\t'\n}\n\nstrip_diffstat()\n{\n\tawk '\n\t/#? .* \\| / \\\n\t\t{ eat = eat $0 \"\\n\"\n\t\t  next }\n\t/^#? .* files? changed(, .* insertions?\\(\\+\\))?(, .* deletions?\\(-\\))?/ \\\n\t\t{ eat = \"\"\n\t\t  next }\n\t\t{ print eat $0\n\t\t  eat = \"\" }\n\t'\n}\n\nstrip_trailing_whitespace() {\n\tsed -e 's:[ '$'\\t'']*$::'\n}\n\nfixup_header() {\n\tawk '\n\t\t/^From / { next }\n\t\t/^Subject: / {\n\t\t\tsub(\"Subject: \\\\[[^\\]]*\\\\]\", \"Subject: [PATCH]\")\n\t\t}\n\t\t{ print }\n\t'\n}\n\ncheck_number \"$BASE\" || usage\n\nquilt series > /dev/null || {\n\techo \"Not in quilt directory\"\n\texit 2\n}\n\nget_next() {\n\tNEW=$BASE\n\tquilt series | while read CUR; do\n\t\t[ -n \"$CUR\" ] || break\n\t\tCUR=${CUR%%-*}\n\t\tcheck_number \"$CUR\" || continue\n\t\t[ \"$CUR\" -lt \"$NEW\" ] && continue\n\t\t[ \"$CUR\" -ge \"$(($BASE + 100))\" ] && continue\n\t\tNEW=\"$(($CUR + 1))\"\n\t\techo $NEW\n\tdone | tail -n1\n}\n\nCUR=$(get_next)\nCUR=\"${CUR:-$BASE}\"\n\nwhile [ -n \"$1\" ]; do\n\tFILE=\"$1\"; shift\n\tNAME=\"$(basename $FILE)\"\n\tNAME=\"${NAME#[0-9]*-}\"\n\techo -n \"Processing patch $NAME: \"\n\n\t[ -e \"$FILE\" ] || {\n\t\techo \"file $FILE not found\"\n\t\texit 1\n\t}\n\n\tgrep -qE \"$NAME$\" patches/series && {\n\t\techo \"already applied\"\n\t\tcontinue\n\t}\n\n\tquilt new \"$CUR-$NAME\" || exit 1\n\tpatch_header < \"$FILE\" |\n\t\tstrip_diffstat |\n\t\tstrip_trailing_whitespace |\n\t\tfixup_header > \"patches/$CUR-$NAME\"\n\n\tquilt fold < \"$FILE\" || {\n\t\tcp \"$FILE\" ./cur_patch\n\t\techo \"patch $FILE failed to apply, copied to ./cur_patch\"\n\t\texit 1\n\t}\n\n\tquilt refresh -p ab --no-index --no-timestamps\n\n\tCUR=\"$(($CUR + 1))\"\ndone\n\nexit 0\n"
  },
  {
    "path": "package/kernel/mt76/Makefile",
    "content": "include $(TOPDIR)/rules.mk\n\nPKG_NAME:=mt76\nPKG_RELEASE=4\n\nPKG_LICENSE:=GPLv2\nPKG_LICENSE_FILES:=\n\nPKG_SOURCE_URL:=https://github.com/openwrt/mt76\nPKG_SOURCE_PROTO:=git\nPKG_SOURCE_DATE:=2022-04-23\nPKG_SOURCE_VERSION:=a666d5637bc3afd3e310be09fac048906560097b\nPKG_MIRROR_HASH:=1a7f7a36e5e376d1b18da98c7939f980855f1981be0c3ad7024360dee702c9f8\n\nPKG_MAINTAINER:=Felix Fietkau <nbd@nbd.name>\nPKG_USE_NINJA:=0\nPKG_BUILD_PARALLEL:=1\n\nPKG_CONFIG_DEPENDS += \\\n\tCONFIG_PACKAGE_kmod-mt76-usb \\\n\tCONFIG_PACKAGE_kmod-mt76x02-common \\\n\tCONFIG_PACKAGE_kmod-mt76x0-common \\\n\tCONFIG_PACKAGE_kmod-mt76x0u \\\n\tCONFIG_PACKAGE_kmod-mt76x2-common \\\n\tCONFIG_PACKAGE_kmod-mt76x2 \\\n\tCONFIG_PACKAGE_kmod-mt76x2u \\\n\tCONFIG_PACKAGE_kmod-mt7603 \\\n\tCONFIG_PACKAGE_CFG80211_TESTMODE\n\nSTAMP_CONFIGURED_DEPENDS := $(STAGING_DIR)/usr/include/mac80211-backport/backport/autoconf.h\n\ninclude $(INCLUDE_DIR)/kernel.mk\ninclude $(INCLUDE_DIR)/package.mk\ninclude $(INCLUDE_DIR)/cmake.mk\n\nCMAKE_SOURCE_DIR:=$(PKG_BUILD_DIR)/tools\nCMAKE_BINARY_DIR:=$(PKG_BUILD_DIR)/tools\n\ndefine KernelPackage/mt76-default\n  SUBMENU:=Wireless Drivers\n  DEPENDS:= \\\n\t+kmod-mac80211 \\\n\t+@DRIVER_11AC_SUPPORT +@DRIVER_11N_SUPPORT\nendef\n\ndefine KernelPackage/mt76\n  SUBMENU:=Wireless Drivers\n  TITLE:=MediaTek MT76x2/MT7603 wireless driver (metapackage)\n  DEPENDS:= \\\n\t+kmod-mt76-core +kmod-mt76x2 +kmod-mt7603\nendef\n\ndefine KernelPackage/mt76-core\n  $(KernelPackage/mt76-default)\n  TITLE:=MediaTek MT76xx wireless driver\n  HIDDEN:=1\n  FILES:=\\\n\t$(PKG_BUILD_DIR)/mt76.ko\nendef\n\ndefine KernelPackage/mt76-usb\n  $(KernelPackage/mt76-default)\n  TITLE:=MediaTek MT76xx wireless driver USB support\n  DEPENDS += +kmod-usb-core +kmod-mt76-core\n  HIDDEN:=1\n  FILES:=\\\n\t$(PKG_BUILD_DIR)/mt76-usb.ko\nendef\n\ndefine KernelPackage/mt76x02-usb\n  $(KernelPackage/mt76-default)\n  TITLE:=MediaTek MT76x0/MT76x2 USB wireless driver common code\n  DEPENDS+=+kmod-mt76-usb +kmod-mt76x02-common\n  HIDDEN:=1\n  FILES:=$(PKG_BUILD_DIR)/mt76x02-usb.ko\nendef\n\ndefine KernelPackage/mt76x02-common\n  $(KernelPackage/mt76-default)\n  TITLE:=MediaTek MT76x0/MT76x2 wireless driver common code\n  DEPENDS+=+kmod-mt76-core\n  HIDDEN:=1\n  FILES:=$(PKG_BUILD_DIR)/mt76x02-lib.ko\nendef\n\ndefine KernelPackage/mt76x0-common\n  $(KernelPackage/mt76-default)\n  TITLE:=MediaTek MT76x0 wireless driver common code\n  DEPENDS+=+kmod-mt76x02-common\n  HIDDEN:=1\n  FILES:=$(PKG_BUILD_DIR)/mt76x0/mt76x0-common.ko\nendef\n\ndefine KernelPackage/mt76x0e\n  $(KernelPackage/mt76-default)\n  TITLE:=MediaTek MT76x0E wireless driver\n  DEPENDS+=@PCI_SUPPORT +kmod-mt76x0-common\n  FILES:=\\\n\t$(PKG_BUILD_DIR)/mt76x0/mt76x0e.ko\n  AUTOLOAD:=$(call AutoProbe,mt76x0e)\nendef\n\ndefine KernelPackage/mt76x0u\n  $(KernelPackage/mt76-default)\n  TITLE:=MediaTek MT76x0U wireless driver\n  DEPENDS+=+kmod-mt76x0-common +kmod-mt76x02-usb\n  FILES:=\\\n\t$(PKG_BUILD_DIR)/mt76x0/mt76x0u.ko\n  AUTOLOAD:=$(call AutoProbe,mt76x0u)\nendef\n\ndefine KernelPackage/mt76x2-common\n  $(KernelPackage/mt76-default)\n  TITLE:=MediaTek MT76x2 wireless driver common code\n  DEPENDS+=+kmod-mt76-core +kmod-mt76x02-common\n  HIDDEN:=1\n  FILES:=$(PKG_BUILD_DIR)/mt76x2/mt76x2-common.ko\nendef\n\ndefine KernelPackage/mt76x2u\n  $(KernelPackage/mt76-default)\n  TITLE:=MediaTek MT76x2U wireless driver\n  DEPENDS+=+kmod-mt76x2-common +kmod-mt76x02-usb\n  FILES:=\\\n\t$(PKG_BUILD_DIR)/mt76x2/mt76x2u.ko\n  AUTOLOAD:=$(call AutoProbe,mt76x2u)\nendef\n\ndefine KernelPackage/mt76x2\n  $(KernelPackage/mt76-default)\n  TITLE:=MediaTek MT76x2 wireless driver\n  DEPENDS+=@PCI_SUPPORT +kmod-mt76x2-common\n  FILES:=\\\n\t$(PKG_BUILD_DIR)/mt76x2/mt76x2e.ko\n  AUTOLOAD:=$(call AutoProbe,mt76x2e)\nendef\n\ndefine KernelPackage/mt7603\n  $(KernelPackage/mt76-default)\n  TITLE:=MediaTek MT7603 wireless driver\n  DEPENDS+=@PCI_SUPPORT +kmod-mt76-core\n  FILES:=\\\n\t$(PKG_BUILD_DIR)/mt7603/mt7603e.ko\n  AUTOLOAD:=$(call AutoProbe,mt7603e)\nendef\n\ndefine KernelPackage/mt76-connac\n  $(KernelPackage/mt76-default)\n  TITLE:=MediaTek MT7615/MT79xx wireless driver common code\n  HIDDEN:=1\n  DEPENDS+=+kmod-mt76-core\n  FILES:= $(PKG_BUILD_DIR)/mt76-connac-lib.ko\nendef\n\ndefine KernelPackage/mt76-sdio\n  $(KernelPackage/mt76-default)\n  TITLE:=MediaTek MT7615/MT79xx SDIO driver common code\n  HIDDEN:=1\n  DEPENDS+=+kmod-mt76-core +kmod-mmc\n  FILES:= $(PKG_BUILD_DIR)/mt76-sdio.ko\nendef\n\ndefine KernelPackage/mt7615-common\n  $(KernelPackage/mt76-default)\n  TITLE:=MediaTek MT7615 wireless driver common code\n  HIDDEN:=1\n  DEPENDS+=@PCI_SUPPORT +kmod-mt76-core +kmod-mt76-connac +kmod-hwmon-core\n  FILES:= $(PKG_BUILD_DIR)/mt7615/mt7615-common.ko\nendef\n\ndefine KernelPackage/mt7615-firmware\n  $(KernelPackage/mt76-default)\n  TITLE:=MediaTek MT7615e firmware\n  DEFAULT:=PACKAGE_kmod-mt7615e\nendef\n\ndefine KernelPackage/mt7615e\n  $(KernelPackage/mt76-default)\n  TITLE:=MediaTek MT7615e wireless driver\n  DEPENDS+=@PCI_SUPPORT +kmod-mt7615-common\n  FILES:= $(PKG_BUILD_DIR)/mt7615/mt7615e.ko\n  AUTOLOAD:=$(call AutoProbe,mt7615e)\nendef\n\ndefine KernelPackage/mt7663-firmware-ap\n  $(KernelPackage/mt76-default)\n  TITLE:=MediaTek MT7663e firmware (optimized for AP)\nendef\n\ndefine KernelPackage/mt7663-firmware-sta\n  $(KernelPackage/mt76-default)\n  TITLE:=MediaTek MT7663e firmware (client mode offload)\nendef\n\ndefine KernelPackage/mt7663-usb-sdio\n  $(KernelPackage/mt76-default)\n  TITLE:=MediaTek MT7663 USB/SDIO shared code\n  DEPENDS+=+kmod-mt7615-common\n  HIDDEN:=1\n  FILES:= \\\n\t$(PKG_BUILD_DIR)/mt7615/mt7663-usb-sdio-common.ko\nendef\n\ndefine KernelPackage/mt7663s\n  $(KernelPackage/mt76-default)\n  TITLE:=MediaTek MT7663s wireless driver\n  DEPENDS+=+kmod-mt76-sdio +kmod-mt7615-common +kmod-mt7663-usb-sdio\n  FILES:= \\\n\t$(PKG_BUILD_DIR)/mt7615/mt7663s.ko\n  AUTOLOAD:=$(call AutoProbe,mt7663s)\nendef\n\ndefine KernelPackage/mt7663u\n  $(KernelPackage/mt76-default)\n  TITLE:=MediaTek MT7663u wireless driver\n  DEPENDS+=+kmod-mt76-usb +kmod-mt7615-common +kmod-mt7663-usb-sdio\n  FILES:= $(PKG_BUILD_DIR)/mt7615/mt7663u.ko\n  AUTOLOAD:=$(call AutoProbe,mt7663u)\nendef\n\ndefine KernelPackage/mt7915e\n  $(KernelPackage/mt76-default)\n  TITLE:=MediaTek MT7915e wireless driver\n  DEPENDS+=@PCI_SUPPORT +kmod-mt7615-common +kmod-hwmon-core +kmod-thermal +@DRIVER_11AX_SUPPORT +@KERNEL_RELAY\n  FILES:= $(PKG_BUILD_DIR)/mt7915/mt7915e.ko\n  AUTOLOAD:=$(call AutoProbe,mt7915e)\nendef\n\ndefine KernelPackage/mt7921-common\n  $(KernelPackage/mt76-default)\n  TITLE:=MediaTek MT7615 wireless driver common code\n  HIDDEN:=1\n  DEPENDS+=+kmod-mt76-connac +@DRIVER_11AX_SUPPORT\n  FILES:= $(PKG_BUILD_DIR)/mt7921/mt7921-common.ko\nendef\n\ndefine KernelPackage/mt7921u\n  $(KernelPackage/mt76-default)\n  TITLE:=MediaTek MT7921U wireless driver\n  DEPENDS+=+kmod-mt76-usb +kmod-mt7921-common\n  FILES:= $(PKG_BUILD_DIR)/mt7921/mt7921u.ko\n  AUTOLOAD:=$(call AutoProbe,mt7921u)\nendef\n\ndefine KernelPackage/mt7921s\n  $(KernelPackage/mt76-default)\n  TITLE:=MediaTek MT7921S wireless driver\n  DEPENDS+=+kmod-mt76-sdio +kmod-mt7921-common\n  FILES:= $(PKG_BUILD_DIR)/mt7921/mt7921s.ko\n  AUTOLOAD:=$(call AutoProbe,mt7921s)\nendef\n\ndefine KernelPackage/mt7921e\n  $(KernelPackage/mt76-default)\n  TITLE:=MediaTek MT7921e wireless driver\n  DEPENDS+=@PCI_SUPPORT +kmod-mt7921-common\n  FILES:= $(PKG_BUILD_DIR)/mt7921/mt7921e.ko\n  AUTOLOAD:=$(call AutoProbe,mt7921e)\nendef\n\ndefine Package/mt76-test\n  SECTION:=devel\n  CATEGORY:=Development\n  TITLE:=mt76 testmode CLI\n  DEPENDS:=kmod-mt76-core +libnl-tiny\nendef\n\nTARGET_CFLAGS += -I$(STAGING_DIR)/usr/include/libnl-tiny\n\nNOSTDINC_FLAGS := \\\n\t$(KERNEL_NOSTDINC_FLAGS) \\\n\t-I$(PKG_BUILD_DIR) \\\n\t-I$(STAGING_DIR)/usr/include/mac80211-backport/uapi \\\n\t-I$(STAGING_DIR)/usr/include/mac80211-backport \\\n\t-I$(STAGING_DIR)/usr/include/mac80211/uapi \\\n\t-I$(STAGING_DIR)/usr/include/mac80211 \\\n\t-include backport/autoconf.h \\\n\t-include backport/backport.h\n\nifdef CONFIG_PACKAGE_MAC80211_MESH\n  NOSTDINC_FLAGS += -DCONFIG_MAC80211_MESH\nendif\n\nifdef CONFIG_PACKAGE_CFG80211_TESTMODE\n  NOSTDINC_FLAGS += -DCONFIG_NL80211_TESTMODE\n  PKG_MAKE_FLAGS += CONFIG_NL80211_TESTMODE=y\nendif\n\nifdef CONFIG_PACKAGE_kmod-mt76-usb\n  PKG_MAKE_FLAGS += CONFIG_MT76_USB=m\nendif\nifdef CONFIG_PACKAGE_kmod-mt76x02-common\n  PKG_MAKE_FLAGS += CONFIG_MT76x02_LIB=m\nendif\nifdef CONFIG_PACKAGE_kmod-mt76x02-usb\n  PKG_MAKE_FLAGS += CONFIG_MT76x02_USB=m\nendif\nifdef CONFIG_PACKAGE_kmod-mt76x0-common\n  PKG_MAKE_FLAGS += CONFIG_MT76x0_COMMON=m\nendif\nifdef CONFIG_PACKAGE_kmod-mt76x0e\n  PKG_MAKE_FLAGS += CONFIG_MT76x0E=m\nendif\nifdef CONFIG_PACKAGE_kmod-mt76x0u\n  PKG_MAKE_FLAGS += CONFIG_MT76x0U=m\nendif\nifdef CONFIG_PACKAGE_kmod-mt76x2-common\n  PKG_MAKE_FLAGS += CONFIG_MT76x2_COMMON=m\nendif\nifdef CONFIG_PACKAGE_kmod-mt76x2\n  PKG_MAKE_FLAGS += CONFIG_MT76x2E=m\nendif\nifdef CONFIG_PACKAGE_kmod-mt76x2u\n  PKG_MAKE_FLAGS += CONFIG_MT76x2U=m\nendif\nifdef CONFIG_PACKAGE_kmod-mt7603\n  PKG_MAKE_FLAGS += CONFIG_MT7603E=m\nendif\nifdef CONFIG_PACKAGE_kmod-mt76-connac\n  PKG_MAKE_FLAGS += CONFIG_MT76_CONNAC_LIB=m\nendif\nifdef CONFIG_PACKAGE_kmod-mt76-sdio\n  PKG_MAKE_FLAGS += CONFIG_MT76_SDIO=m\nendif\nifdef CONFIG_PACKAGE_kmod-mt7615-common\n  PKG_MAKE_FLAGS += CONFIG_MT7615_COMMON=m\nendif\nifdef CONFIG_PACKAGE_kmod-mt7615e\n  PKG_MAKE_FLAGS += CONFIG_MT7615E=m\n  ifdef CONFIG_TARGET_mediatek_mt7622\n    PKG_MAKE_FLAGS += CONFIG_MT7622_WMAC=y\n    NOSTDINC_FLAGS += -DCONFIG_MT7622_WMAC\n  endif\nendif\nifdef CONFIG_PACKAGE_kmod-mt7663-usb-sdio\n  PKG_MAKE_FLAGS += CONFIG_MT7663_USB_SDIO_COMMON=m\nendif\nifdef CONFIG_PACKAGE_kmod-mt7663s\n  PKG_MAKE_FLAGS += CONFIG_MT7663S=m\nendif\nifdef CONFIG_PACKAGE_kmod-mt7663u\n  PKG_MAKE_FLAGS += CONFIG_MT7663U=m\nendif\nifdef CONFIG_PACKAGE_kmod-mt7915e\n  PKG_MAKE_FLAGS += CONFIG_MT7915E=m\nendif\nifdef CONFIG_PACKAGE_kmod-mt7921-common\n  PKG_MAKE_FLAGS += CONFIG_MT7921_COMMON=m\nendif\nifdef CONFIG_PACKAGE_kmod-mt7921u\n  PKG_MAKE_FLAGS += CONFIG_MT7921U=m\nendif\nifdef CONFIG_PACKAGE_kmod-mt7921s\n  PKG_MAKE_FLAGS += CONFIG_MT7921S=m\nendif\nifdef CONFIG_PACKAGE_kmod-mt7921e\n  PKG_MAKE_FLAGS += CONFIG_MT7921E=m\nendif\n\ndefine Build/Compile\n\t+$(MAKE) $(PKG_JOBS) -C \"$(LINUX_DIR)\" \\\n\t\t$(KERNEL_MAKE_FLAGS) \\\n\t\t$(PKG_MAKE_FLAGS) \\\n\t\tM=\"$(PKG_BUILD_DIR)\" \\\n\t\tNOSTDINC_FLAGS=\"$(NOSTDINC_FLAGS)\" \\\n\t\tmodules\n\t$(MAKE) -C $(PKG_BUILD_DIR)/tools\nendef\n\ndefine Build/Install\n\t:\nendef\n\ndefine Package/kmod-mt76/install\n\ttrue\nendef\n\ndefine KernelPackage/mt76x0-common/install\n\t$(INSTALL_DIR) $(1)/lib/firmware/mediatek\n\tcp \\\n\t\t$(PKG_BUILD_DIR)/firmware/mt7610e.bin \\\n\t\t$(1)/lib/firmware/mediatek\nendef\n\ndefine KernelPackage/mt76x2-common/install\n\t$(INSTALL_DIR) $(1)/lib/firmware\n\tcp \\\n\t\t$(PKG_BUILD_DIR)/firmware/mt7662_rom_patch.bin \\\n\t\t$(PKG_BUILD_DIR)/firmware/mt7662.bin \\\n\t\t$(1)/lib/firmware\nendef\n\ndefine KernelPackage/mt76x0u/install\n\t$(INSTALL_DIR) $(1)/lib/firmware/mediatek\n\tln -sf mt7610e.bin $(1)/lib/firmware/mediatek/mt7610u.bin\nendef\n\ndefine KernelPackage/mt76x2u/install\n\t$(INSTALL_DIR) $(1)/lib/firmware/mediatek\n\tln -sf ../mt7662.bin $(1)/lib/firmware/mediatek/mt7662u.bin\n\tln -sf ../mt7662_rom_patch.bin $(1)/lib/firmware/mediatek/mt7662u_rom_patch.bin\nendef\n\ndefine KernelPackage/mt7603/install\n\t$(INSTALL_DIR) $(1)/lib/firmware\n\tcp $(if $(CONFIG_TARGET_ramips_mt76x8), \\\n\t\t$(PKG_BUILD_DIR)/firmware/mt7628_e1.bin \\\n\t\t$(PKG_BUILD_DIR)/firmware/mt7628_e2.bin \\\n\t\t,\\\n\t\t$(PKG_BUILD_DIR)/firmware/mt7603_e1.bin \\\n\t\t$(PKG_BUILD_DIR)/firmware/mt7603_e2.bin \\\n\t\t) \\\n\t\t$(1)/lib/firmware\nendef\n\ndefine KernelPackage/mt7615-firmware/install\n\t$(INSTALL_DIR) $(1)/lib/firmware/mediatek\n\tcp \\\n\t\t$(PKG_BUILD_DIR)/firmware/mt7615_cr4.bin \\\n\t\t$(PKG_BUILD_DIR)/firmware/mt7615_n9.bin \\\n\t\t$(PKG_BUILD_DIR)/firmware/mt7615_rom_patch.bin \\\n\t\t$(if $(CONFIG_TARGET_mediatek_mt7622), \\\n\t\t\t$(PKG_BUILD_DIR)/firmware/mt7622_n9.bin \\\n\t\t\t$(PKG_BUILD_DIR)/firmware/mt7622_rom_patch.bin) \\\n\t\t$(1)/lib/firmware/mediatek\nendef\n\ndefine KernelPackage/mt7663-firmware-ap/install\n\t$(INSTALL_DIR) $(1)/lib/firmware/mediatek\n\tcp \\\n\t\t$(PKG_BUILD_DIR)/firmware/mt7663_n9_rebb.bin \\\n\t\t$(PKG_BUILD_DIR)/firmware/mt7663pr2h_rebb.bin \\\n\t\t$(1)/lib/firmware/mediatek\nendef\n\ndefine KernelPackage/mt7663-firmware-sta/install\n\t$(INSTALL_DIR) $(1)/lib/firmware/mediatek\n\tcp \\\n\t\t$(PKG_BUILD_DIR)/firmware/mt7663_n9_v3.bin \\\n\t\t$(PKG_BUILD_DIR)/firmware/mt7663pr2h.bin \\\n\t\t$(1)/lib/firmware/mediatek\nendef\n\ndefine KernelPackage/mt7915e/install\n\t$(INSTALL_DIR) $(1)/lib/firmware/mediatek\n\tcp \\\n\t\t$(PKG_BUILD_DIR)/firmware/mt7915_wa.bin \\\n\t\t$(PKG_BUILD_DIR)/firmware/mt7915_wm.bin \\\n\t\t$(PKG_BUILD_DIR)/firmware/mt7915_rom_patch.bin \\\n\t\t$(1)/lib/firmware/mediatek\nendef\n\ndefine KernelPackage/mt7921e/install\n\t$(INSTALL_DIR) $(1)/lib/firmware/mediatek\n\tcp \\\n\t\t$(PKG_BUILD_DIR)/firmware/WIFI_MT7961_patch_mcu_1_2_hdr.bin \\\n\t\t$(PKG_BUILD_DIR)/firmware/WIFI_RAM_CODE_MT7961_1.bin \\\n\t\t$(1)/lib/firmware/mediatek\nendef\n\ndefine Package/mt76-test/install\n\tmkdir -p $(1)/usr/sbin\n\t$(INSTALL_BIN) $(PKG_BUILD_DIR)/tools/mt76-test $(1)/usr/sbin\nendef\n\n$(eval $(call KernelPackage,mt76-core))\n$(eval $(call KernelPackage,mt76-usb))\n$(eval $(call KernelPackage,mt76x02-usb))\n$(eval $(call KernelPackage,mt76x02-common))\n$(eval $(call KernelPackage,mt76x0-common))\n$(eval $(call KernelPackage,mt76x0e))\n$(eval $(call KernelPackage,mt76x0u))\n$(eval $(call KernelPackage,mt76x2-common))\n$(eval $(call KernelPackage,mt76x2u))\n$(eval $(call KernelPackage,mt76x2))\n$(eval $(call KernelPackage,mt7603))\n$(eval $(call KernelPackage,mt76-connac))\n$(eval $(call KernelPackage,mt76-sdio))\n$(eval $(call KernelPackage,mt7615-common))\n$(eval $(call KernelPackage,mt7615-firmware))\n$(eval $(call KernelPackage,mt7615e))\n$(eval $(call KernelPackage,mt7663-firmware-ap))\n$(eval $(call KernelPackage,mt7663-firmware-sta))\n$(eval $(call KernelPackage,mt7663-usb-sdio))\n$(eval $(call KernelPackage,mt7663u))\n$(eval $(call KernelPackage,mt7663s))\n$(eval $(call KernelPackage,mt7915e))\n$(eval $(call KernelPackage,mt7921-common))\n$(eval $(call KernelPackage,mt7921u))\n$(eval $(call KernelPackage,mt7921s))\n$(eval $(call KernelPackage,mt7921e))\n$(eval $(call KernelPackage,mt76))\n$(eval $(call BuildPackage,mt76-test))\n"
  },
  {
    "path": "package/kernel/mt7621-qtn-rgmii/Makefile",
    "content": "#\n# Copyright (C) 2020 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\ninclude $(INCLUDE_DIR)/kernel.mk\n\nPKG_NAME:=mt7621-qtn-rgmii\nPKG_RELEASE:=1\nPKG_LICENSE:=GPL-2.0\n\nPKG_MAINTAINER:=Bjørn Mork <bjorn@mork.no>\n\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine KernelPackage/mt7621-qtn-rgmii\n  SECTION:=kernel\n  SUBMENU:=Other modules\n  TITLE:=Enable RGMII connected Quantenna module on MT7621\n  DEPENDS:=@TARGET_ramips_mt7621\n  HIDDEN:=1\n  FILES:=$(PKG_BUILD_DIR)/mt7621-qtn-rgmii.ko\n  AUTOLOAD:=$(call AutoLoad,30,mt7621-qtn-rgmii,1)\nendef\n\ndefine KernelPackage/mt7621-qtn-rgmii/description\n  Enable RGMII connected Quantenna module on MT7621.\n\n  The Mitrastar designed ZyXEL WAP6805 has a Quantenna QV840\n  module connected to the RGMII pins of the MT7621 SoC. For\n  unknown reasons, it is necessary to change the value of\n  the register at 0x1e110008 from default (usually 0xc000c)\n  to 0x9000c for this connection wo work.\n\n  This driver simply does that without much fuzz.\nendef\n\ndefine Build/Compile\n        $(KERNEL_MAKE) M=$(PKG_BUILD_DIR) modules\nendef\n\n$(eval $(call KernelPackage,mt7621-qtn-rgmii))\n"
  },
  {
    "path": "package/kernel/mt7621-qtn-rgmii/src/Makefile",
    "content": "obj-m += mt7621-qtn-rgmii.o\n"
  },
  {
    "path": "package/kernel/mt7621-qtn-rgmii/src/mt7621-qtn-rgmii.c",
    "content": "// SPDX-License-Identifier: GPL-2.0-only\n/*\n * Copyright (c) 2020  Bjørn Mork <bjorn@mork.no>\n */\n#include <linux/io.h>\n#include <linux/module.h>\n\n#define MODULE_NAME \"mt7621-qtn-rgmii\"\n#define RGMII_REG_BASE\t0x1e110008\n#define RGMII_REG_SIZE\t4\n#define RGMII_REG_VALUE\t0x9000c\n\nstatic u32 oldval;\n\nstatic int __init mt7621_qtn_rgmii_init(void)\n{\n\tvoid __iomem *base = ioremap(RGMII_REG_BASE, RGMII_REG_SIZE);\n\n\tif (!base)\n\t\treturn -ENOMEM;\n\toldval = ioread32(base);\n\tif (oldval != RGMII_REG_VALUE) {\n\t\tiowrite32(RGMII_REG_VALUE, base);\n\t\tpr_info(MODULE_NAME \": changed register 0x%08x value from 0x%08x to 0x%08x\\n\", RGMII_REG_BASE, oldval,  RGMII_REG_VALUE);\n\t}\n\tiounmap(base);\n\treturn 0;\n}\n\nstatic void __exit mt7621_qtn_rgmii_exit(void)\n{\n\tvoid __iomem *base = ioremap(RGMII_REG_BASE, RGMII_REG_SIZE);\n\n\tif (!base)\n\t\treturn;\n\tif (oldval != RGMII_REG_VALUE) {\n\t\tiowrite32(oldval, base);\n\t\tpr_info(MODULE_NAME \": reset register 0x%08x back to 0x%08x\\n\", RGMII_REG_BASE, oldval);\n\t}\n\tiounmap(base);\n}\n\nmodule_init(mt7621_qtn_rgmii_init);\nmodule_exit(mt7621_qtn_rgmii_exit);\n\nMODULE_LICENSE(\"GPL\");\nMODULE_AUTHOR(\"Bjørn Mork <bjorn@mork.no>\");\nMODULE_DESCRIPTION(\"Enable RGMII connected Quantenna module on MT7621\");\n"
  },
  {
    "path": "package/kernel/mwlwifi/Makefile",
    "content": "#\n# Copyright (C) 2014-2016 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=mwlwifi\nPKG_RELEASE=3\n\nPKG_LICENSE:=ISC\nPKG_LICENSE_FILES:=\n\nPKG_SOURCE_URL:=https://github.com/kaloz/mwlwifi\nPKG_SOURCE_PROTO:=git\nPKG_SOURCE_DATE:=2020-02-06\nPKG_SOURCE_VERSION:=a2fd00bb74c35820dfe233d762690c0433a87ef5\nPKG_MIRROR_HASH:=0eda0e774a87e58e611d6436350e1cf2be3de50fddde334909a07a15b0c9862b\n\nPKG_MAINTAINER:=Imre Kaloz <kaloz@openwrt.org>\nPKG_BUILD_PARALLEL:=1\nPKG_FLAGS:=nonshared\n\ninclude $(INCLUDE_DIR)/kernel.mk\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine KernelPackage/mwlwifi\n  SUBMENU:=Wireless Drivers\n  TITLE:=Marvell 88W8864/88W8897/88W8964/88W8997 wireless driver\n  DEPENDS:=+kmod-mac80211 +@DRIVER_11N_SUPPORT +@DRIVER_11AC_SUPPORT @PCI_SUPPORT @TARGET_mvebu\n  FILES:=$(PKG_BUILD_DIR)/mwlwifi.ko\n  AUTOLOAD:=$(call AutoLoad,50,mwlwifi)\nendef\n\nNOSTDINC_FLAGS := \\\n\t$(KERNEL_NOSTDINC_FLAGS) \\\n\t-I$(PKG_BUILD_DIR) \\\n\t-I$(STAGING_DIR)/usr/include/mac80211-backport/uapi \\\n\t-I$(STAGING_DIR)/usr/include/mac80211-backport \\\n\t-I$(STAGING_DIR)/usr/include/mac80211/uapi \\\n\t-I$(STAGING_DIR)/usr/include/mac80211 \\\n\t-include backport/backport.h\n\ndefine Build/Compile\n\t+$(MAKE) $(PKG_JOBS) -C \"$(LINUX_DIR)\" \\\n\t\t$(KERNEL_MAKE_FLAGS) \\\n\t\tM=\"$(PKG_BUILD_DIR)\" \\\n\t\tNOSTDINC_FLAGS=\"$(NOSTDINC_FLAGS)\" \\\n\t\tmodules\nendef\n\ndefine Package/mwlwifi-firmware-default\n  SECTION:=firmware\n  CATEGORY:=Firmware\n  TITLE:=Marvell $(1) firmware\n  DEPENDS:=+kmod-mwlwifi @TARGET_mvebu\nendef\n\ndefine Package/mwlwifi-firmware/install\n\t$(INSTALL_DIR) $(1)/lib/firmware\n\t$(INSTALL_DIR) $(1)/lib/firmware/mwlwifi\n\t$(CP) $(PKG_BUILD_DIR)/bin/firmware/$(2) $(1)/lib/firmware/mwlwifi/\n\t$(CP) $(PKG_BUILD_DIR)/bin/firmware/Marvell_license.txt $(1)/lib/firmware/mwlwifi/$(2).Marvell_license.txt\nendef\n\ndefine Package/mwlwifi-firmware-88w8864\n$(call Package/mwlwifi-firmware-default,88W8864)\nendef\n\ndefine Package/mwlwifi-firmware-88w8864/install\n\t$(call Package/mwlwifi-firmware/install,$(1),88W8864.bin)\nendef\n\ndefine Package/mwlwifi-firmware-88w8897\n$(call Package/mwlwifi-firmware-default,88W8897)\nendef\n\ndefine Package/mwlwifi-firmware-88w8897/install\n\t$(call Package/mwlwifi-firmware/install,$(1),88W8897.bin)\nendef\n\ndefine Package/mwlwifi-firmware-88w8964\n$(call Package/mwlwifi-firmware-default,88W8964)\nendef\n\ndefine Package/mwlwifi-firmware-88w8964/install\n\t$(call Package/mwlwifi-firmware/install,$(1),88W8964.bin)\nendef\n\ndefine Package/mwlwifi-firmware-88w8997\n$(call Package/mwlwifi-firmware-default,88W8997)\nendef\n\ndefine Package/mwlwifi-firmware-88w8997/install\n\t$(call Package/mwlwifi-firmware/install,$(1),88W8997.bin)\nendef\n\n$(eval $(call KernelPackage,mwlwifi))\n$(eval $(call BuildPackage,mwlwifi-firmware-88w8864))\n$(eval $(call BuildPackage,mwlwifi-firmware-88w8897))\n$(eval $(call BuildPackage,mwlwifi-firmware-88w8964))\n$(eval $(call BuildPackage,mwlwifi-firmware-88w8997))\n"
  },
  {
    "path": "package/kernel/mwlwifi/patches/001-Fix-compile-with-mac80211-backports-5_3+.patch",
    "content": "From 182391a3c96ff6ad79bbba0758338a16a66abbd8 Mon Sep 17 00:00:00 2001\nFrom: DENG Qingfang <dengqf6@mail2.sysu.edu.cn>\nDate: Wed, 12 Feb 2020 14:18:58 +0800\nSubject: [PATCH] Fix driver loading with backports 5.3+\n\nCommit 747796b2f126 did not solve the issue that it crashes when an older kernel\nwith a newer backport tries loading it, because it only detects kernel version.\n\nAs net/cfg80211.h in 5.3+ defines VENDOR_CMD_RAW_DATA, use it as a condition.\n\nSigned-off-by: DENG Qingfang <dqfext@gmail.com>\n---\n vendor_cmd.c | 4 ++--\n 1 file changed, 2 insertions(+), 2 deletions(-)\n\n--- a/vendor_cmd.c\n+++ b/vendor_cmd.c\n@@ -92,7 +92,7 @@ static const struct wiphy_vendor_command\n \t\t\t  .subcmd = MWL_VENDOR_CMD_SET_BF_TYPE},\n \t\t.flags = WIPHY_VENDOR_CMD_NEED_NETDEV,\n \t\t.doit = mwl_vendor_cmd_set_bf_type,\n-#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5,3,0))\n+#ifdef VENDOR_CMD_RAW_DATA\n \t\t.policy = mwl_vendor_attr_policy,\n #endif\n \t},\n@@ -101,7 +101,7 @@ static const struct wiphy_vendor_command\n \t\t\t  .subcmd = MWL_VENDOR_CMD_GET_BF_TYPE},\n \t\t.flags = WIPHY_VENDOR_CMD_NEED_NETDEV,\n \t\t.doit = mwl_vendor_cmd_get_bf_type,\n-#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5,3,0))\n+#ifdef VENDOR_CMD_RAW_DATA\n \t\t.policy = mwl_vendor_attr_policy,\n #endif\n \t}\n"
  },
  {
    "path": "package/kernel/mwlwifi/patches/002-mwlwifi-remove-MODULE_SUPPORTED_DEVICE.patch",
    "content": "From 392f8e9d798acff3079e753dd881e272f6150d74 Mon Sep 17 00:00:00 2001\nFrom: Robert Marko <robert.marko@sartura.hr>\nDate: Wed, 30 Mar 2022 19:32:38 +0200\nSubject: [PATCH] mwlwifi: remove MODULE_SUPPORTED_DEVICE\n\nKernel 5.12 finally removed all MODULE_SUPPORTED_DEVICE references and\nsupport for it as it was never actually implemented and was safe to\ndrop it completely.\n\nSo, do the same in order to compile in 5.12 and newer.\n\nSigned-off-by: Robert Marko <robert.marko@sartura.hr>\n---\n hif/pcie/pcie.c | 2 --\n 1 file changed, 2 deletions(-)\n\n--- a/hif/pcie/pcie.c\n+++ b/hif/pcie/pcie.c\n@@ -31,7 +31,6 @@\n #include \"hif/pcie/rx_ndp.h\"\n \n #define PCIE_DRV_DESC \"Marvell Mac80211 Wireless PCIE Network Driver\"\n-#define PCIE_DEV_NAME \"Marvell 802.11ac PCIE Adapter\"\n \n #define MAX_WAIT_FW_COMPLETE_ITERATIONS 10000\n #define CHECK_BA_TRAFFIC_TIME           300 /* msec */\n@@ -1641,5 +1640,4 @@ MODULE_DESCRIPTION(PCIE_DRV_DESC);\n MODULE_VERSION(PCIE_DRV_VERSION);\n MODULE_AUTHOR(\"Marvell Semiconductor, Inc.\");\n MODULE_LICENSE(\"GPL v2\");\n-MODULE_SUPPORTED_DEVICE(PCIE_DEV_NAME);\n MODULE_DEVICE_TABLE(pci, pcie_id_tbl);\n"
  },
  {
    "path": "package/kernel/mwlwifi/patches/003-mwlwifi-replace-get-set_fs-calls.patch",
    "content": "From 16e51cb83f9fa1717383c9d67f5531df7348347c Mon Sep 17 00:00:00 2001\nFrom: Robert Marko <robert.marko@sartura.hr>\nDate: Wed, 30 Mar 2022 19:51:56 +0200\nSubject: [PATCH] mwlwifi: replace get/set_fs() calls\n\nSince kernel 5.9 the get/set_fs() call implementation have started to get\ndropped from individual architectures, ARM64 one got dropped in 5.11.\n\nReplace the get/set_fs() calls with force_uaccess_begin/end() to allow\ncompiling on newer kernels.\nThere is no need to add kernel version checks as the replacement functions\nare available since kernel 5.9.\n\nSigned-off-by: Robert Marko <robert.marko@sartura.hr>\n---\n hif/pcie/pcie.c | 5 ++---\n 1 file changed, 2 insertions(+), 3 deletions(-)\n\n--- a/hif/pcie/pcie.c\n+++ b/hif/pcie/pcie.c\n@@ -1293,8 +1293,7 @@ static void pcie_bf_mimo_ctrl_decode(str\n \tchar *buf = &str_buf[0];\n \tmm_segment_t oldfs;\n \n-\toldfs = get_fs();\n-\tset_fs(KERNEL_DS);\n+\toldfs = force_uaccess_begin();\n \n \tbuf += sprintf(buf, \"\\nMAC: %pM\\n\", bf_mimo_ctrl->rec_mac);\n \tbuf += sprintf(buf, \"SU_0_MU_1: %d\\n\", bf_mimo_ctrl->type);\n@@ -1314,7 +1313,7 @@ static void pcie_bf_mimo_ctrl_decode(str\n \t\t\t  filename, (unsigned int)fp_data);\n \t}\n \n-\tset_fs(oldfs);\n+\tforce_uaccess_end(oldfs);\n }\n \n static void pcie_process_account(struct ieee80211_hw *hw)\n"
  },
  {
    "path": "package/kernel/mwlwifi/patches/004-mwlwifi-fix-PCIe-DT-node-null-pointer-dereference.patch",
    "content": "From 8e809b241695252e397bf0d7fc5f36e115c38831 Mon Sep 17 00:00:00 2001\nFrom: Robert Marko <robert.marko@sartura.hr>\nDate: Fri, 5 Mar 2021 11:47:59 +0100\nSubject: [PATCH] mwlwifi: fix PCIe DT node null pointer dereference\n\npci_bus_to_OF_node() used to get the PCI bus DT node\nreturns node if found or NULL if none is found.\n\nSince the return of pci_bus_to_OF_node() is not checked in\nthe DT node name print it will cause a null pointer\ndereference and crash the kernel.\n\nSo first check whether the node is not NULL and then print.\n\nSigned-off-by: Robert Marko <robert.marko@sartura.hr>\n---\n hif/pcie/pcie.c | 3 ++-\n 1 file changed, 2 insertions(+), 1 deletion(-)\n\n--- a/hif/pcie/pcie.c\n+++ b/hif/pcie/pcie.c\n@@ -570,7 +570,8 @@ static struct device_node *pcie_get_devi\n \tstruct device_node *dev_node;\n \n \tdev_node = pci_bus_to_OF_node(pcie_priv->pdev->bus);\n-\twiphy_info(priv->hw->wiphy, \"device node: %s\\n\", dev_node->full_name);\n+\tif (dev_node)\n+\t\twiphy_info(priv->hw->wiphy, \"device node: %s\\n\", dev_node->full_name);\n \n \treturn dev_node;\n }\n"
  },
  {
    "path": "package/kernel/nat46/Makefile",
    "content": "include $(TOPDIR)/rules.mk\ninclude $(INCLUDE_DIR)/kernel.mk\n\nPKG_NAME:=nat46\n\nPKG_MIRROR_HASH:=c26b8c60aa991a087011b8b6492e43a6749f0a5d9dc79ffcfd352da5fa20b78d\nPKG_SOURCE_URL:=https://github.com/ayourtch/nat46.git\nPKG_SOURCE_DATE:=2022-03-30\nPKG_SOURCE_PROTO:=git\nPKG_SOURCE_VERSION:=95ca1c3b99376da2d0306919f2df4a8d3c9bb78b\n\nPKG_MAINTAINER:=Hans Dedecker <dedeckeh@gmail.com>\nPKG_LICENSE:=GPL-2.0\n\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine KernelPackage/nat46\n  DEPENDS:=@IPV6\n  TITLE:=Stateless NAT46 translation kernel module\n  SECTION:=kernel\n  SUBMENU:=Network Support\n  FILES:=$(PKG_BUILD_DIR)/nat46/modules/nat46.ko\n  AUTOLOAD:=$(call AutoLoad,33,nat46)\nendef\n\ninclude $(INCLUDE_DIR)/kernel-defaults.mk\n\ndefine Build/Compile\n\t$(KERNEL_MAKE) M=\"$(PKG_BUILD_DIR)/nat46/modules\" \\\n\t\tMODFLAGS=\"-DMODULE -mlong-calls\" \\\n\t\tEXTRA_CFLAGS=\"-DNAT46_VERSION=\\\\\\\"$(PKG_SOURCE_VERSION)\\\\\\\"\" \\\n\t\tmodules\nendef\n\n$(eval $(call KernelPackage,nat46))\n"
  },
  {
    "path": "package/kernel/rtc-rv5c386a/Makefile",
    "content": "#\n# Copyright (C) 2006-2009 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\ninclude $(INCLUDE_DIR)/kernel.mk\n\nPKG_NAME:=rtc-rv5c386a\nPKG_RELEASE:=1\n\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine KernelPackage/rtc-rv5c386a\n  SUBMENU:=Other modules\n  DEPENDS:=@TARGET_bcm47xx @!IN_SDK\n  TITLE:=Driver for RTC RV5C386A (used in WL-700gE and WL-HDD)\n  AUTOLOAD:=$(call AutoLoad,70,rtc)\n  FILES:=$(PKG_BUILD_DIR)/rtc.ko\nendef\n\ndefine Build/Compile\n\t$(MAKE) -C \"$(LINUX_DIR)\" \\\n\t\t$(KERNEL_MAKE_FLAGS) \\\n\t\tM=\"$(PKG_BUILD_DIR)\" \\\n\t\tEXTRA_CFLAGS=\"$(BUILDFLAGS)\" \\\n\t\tmodules\nendef\n\n$(eval $(call KernelPackage,rtc-rv5c386a))\n"
  },
  {
    "path": "package/kernel/rtc-rv5c386a/src/Makefile",
    "content": "# $Id$\n#\n# Makefile for Real Time Clock driver for WL-HDD\n#\n# Copyright (C) 2007 Andreas Engel\n#\n# This program is free software; you can redistribute it and/or\n# modify it under the terms of the GNU General Public License\n# as published by the Free Software Foundation; either version\n# 2 of the License, or (at your option) any later version.\n#\n\nobj-m := rtc.o\n\nifeq ($(MAKING_MODULES),1)\n\n-include $(TOPDIR)/Rules.make\nendif\n"
  },
  {
    "path": "package/kernel/rtc-rv5c386a/src/rtc.c",
    "content": "/*\n * Real Time Clock driver for WL-HDD\n *\n * Copyright (C) 2007 Andreas Engel\n *\n * Hacked together mostly by copying the relevant code parts from:\n *   drivers/i2c/i2c-bcm5365.c\n *   drivers/i2c/i2c-algo-bit.c\n *   drivers/char/rtc.c\n *\n * Note 1:\n * This module uses the standard char device (10,135), while the Asus module\n * rtcdrv.o uses (12,0). So, both can coexist which might be handy during\n * development (but see the comment in rtc_open()).\n *\n * Note 2:\n * You might need to set the clock once after loading the driver the first\n * time because the driver switches the chip into 24h mode if it is running\n * in 12h mode.\n *\n * Usage:\n * For compatibility reasons with the original asus driver, the time can be\n * read and set via the /dev/rtc device entry. The only accepted data format\n * is \"YYYY:MM:DD:W:HH:MM:SS\\n\". See OpenWrt wiki for a script which handles\n * this format.\n *\n * In addition, this driver supports the standard ioctl() calls for setting\n * and reading the hardware clock, so the ordinary hwclock utility can also\n * be used.\n *\n * This program is free software; you can redistribute it and/or\n * modify it under the terms of the GNU General Public License\n * as published by the Free Software Foundation; either version\n * 2 of the License, or (at your option) any later version.\n *\n * TODO:\n * - add a /proc/driver/rtc interface?\n * - make the battery failure bit available through the /proc interface?\n *\n * $Id: rtc.c 7 2007-05-25 19:37:01Z ae $\n */\n\n#include <linux/module.h>\n#include <linux/kmod.h>\n#include <linux/kernel.h>\n#include <linux/types.h>\n#include <linux/miscdevice.h>\n#include <linux/ioport.h>\n#include <linux/fcntl.h>\n#include <linux/mc146818rtc.h>\n#include <linux/init.h>\n#include <linux/spinlock.h>\n#include <linux/rtc.h>\n#include <linux/delay.h>\n#include <linux/version.h>\n#include <linux/gpio.h>\n#include <linux/uaccess.h>\n\n#include <asm/current.h>\n\n#include <bcm47xx.h>\n#include <linux/bcm47xx_nvram.h>\n\n#define RTC_IS_OPEN\t\t0x01\t/* Means /dev/rtc is in use.  */\n\n/* Can be changed via a module parameter.  */\nstatic int rtc_debug = 0;\n\nstatic unsigned long rtc_status = 0;\t/* Bitmapped status byte.\t*/\n\n/* These settings are platform dependents.  */\nunsigned int sda_index = 0;\nunsigned int scl_index = 0;\n\n#define I2C_READ_MASK  1\n#define I2C_WRITE_MASK 0\n\n#define I2C_ACK 1\n#define I2C_NAK 0\n\n#define RTC_EPOCH\t\t1900\n#define RTC_I2C_ADDRESS\t\t(0x32 << 1)\n#define RTC_24HOUR_MODE_MASK\t0x20\n#define RTC_PM_MASK\t\t0x20\n#define RTC_VDET_MASK\t\t0x40\n#define RTC_Y2K_MASK\t\t0x80\n\n/*\n * Delay in microseconds for generating the pulses on the I2C bus. We use\n * a rather conservative setting here.  See datasheet of the RTC chip.\n */\n#define ADAP_DELAY 50\n\n/* Avoid spurious compiler warnings.  */\n#define UNUSED __attribute__((unused))\n\nMODULE_AUTHOR(\"Andreas Engel\");\nMODULE_LICENSE(\"GPL\");\n\n/* Test stolen from switch-adm.c.  */\nmodule_param(rtc_debug, int, 0);\n\nstatic inline void sdalo(void)\n{\n\tgpio_direction_output(sda_index, 1);\n\tudelay(ADAP_DELAY);\n}\n\nstatic inline void sdahi(void)\n{\n\tgpio_direction_input(sda_index);\n\tudelay(ADAP_DELAY);\n}\n\nstatic inline void scllo(void)\n{\n   gpio_direction_output(scl_index, 1);\n\tudelay(ADAP_DELAY);\n}\n\nstatic inline int getscl(void)\n{\n\treturn (gpio_get_value(scl_index));\n}\n\nstatic inline int getsda(void)\n{\n\treturn (gpio_get_value(sda_index));\n}\n\n/*\n * We shouldn't simply set the SCL pin to high. Like SDA, the SCL line is\n * bidirectional too. According to the I2C spec, the slave is allowed to\n * pull down the SCL line to slow down the clock, so we need to check this.\n * Generally, we'd need a timeout here, but in our case, we just check the\n * line, assuming the RTC chip behaves well.\n */\nstatic int sclhi(void)\n{\n\tgpio_direction_input(scl_index);\n\tudelay(ADAP_DELAY);\n\tif (!getscl()) {\n\t\tprintk(KERN_ERR \"SCL pin should be low\\n\");\n\t\treturn -ETIMEDOUT;\n\t}\n\treturn 0;\n}\n\nstatic void i2c_start(void)\n{\n\tsdalo();\n\tscllo();\n}\n\nstatic void i2c_stop(void)\n{\n\tsdalo();\n\tsclhi();\n\tsdahi();\n}\n\nstatic int i2c_outb(int c)\n{\n\tint i;\n\tint ack;\n\n\t/* assert: scl is low */\n\tfor (i = 7; i >= 0; i--) {\n\t\tif (c & ( 1 << i )) {\n\t\t\tsdahi();\n\t\t} else {\n\t\t\tsdalo();\n\t\t}\n\t\tif (sclhi() < 0) { /* timed out */\n\t\t\tsdahi(); /* we don't want to block the net */\n\t\t\treturn -ETIMEDOUT;\n\t\t};\n\t\tscllo();\n\t}\n\tsdahi();\n\tif (sclhi() < 0) {\n\t\treturn -ETIMEDOUT;\n\t};\n\t/* read ack: SDA should be pulled down by slave */\n\tack = getsda() == 0;\t/* ack: sda is pulled low ->success.\t */\n\tscllo();\n\n\tif (rtc_debug)\n\t\tprintk(KERN_DEBUG \"i2c_outb(0x%02x) -> %s\\n\",\n\t\t       c, ack ? \"ACK\": \"NAK\");\n\n\treturn ack;\t\t/* return 1 if device acked\t */\n\t/* assert: scl is low (sda undef) */\n}\n\nstatic int i2c_inb(int ack)\n{\n\tint i;\n\tunsigned int indata = 0;\n\n\t/* assert: scl is low */\n\n\tsdahi();\n\tfor (i = 0; i < 8; i++) {\n\t\tif (sclhi() < 0) {\n\t\t\treturn -ETIMEDOUT;\n\t\t};\n\t\tindata *= 2;\n\t\tif (getsda())\n\t\t\tindata |= 0x01;\n\t\tscllo();\n\t}\n\tif (ack) {\n\t\tsdalo();\n\t} else {\n\t\tsdahi();\n\t}\n\n\tif (sclhi() < 0) {\n\t\tsdahi();\n\t\treturn -ETIMEDOUT;\n\t}\n\tscllo();\n\tsdahi();\n\n\tif (rtc_debug)\n\t\tprintk(KERN_DEBUG \"i2c_inb() -> 0x%02x\\n\", indata);\n\n\t/* assert: scl is low */\n\treturn indata & 0xff;\n}\n\nstatic void i2c_init(void)\n{\n    /* no gpio_control for EXTIF */\n\t// ssb_gpio_control(&ssb, sda_mask | scl_mask, 0);\n\n   gpio_set_value(sda_index, 0);\n   gpio_set_value(scl_index, 0);\n\tsdahi();\n\tsclhi();\n}\n\nstatic int rtc_open(UNUSED struct inode *inode, UNUSED struct file *filp)\n{\n\tspin_lock_irq(&rtc_lock);\n\n\tif (rtc_status & RTC_IS_OPEN) {\n\t\tspin_unlock_irq(&rtc_lock);\n\t\treturn -EBUSY;\n\t}\n\n\trtc_status |= RTC_IS_OPEN;\n\n\t/*\n\t * The following call is only necessary if we use both this driver and\n\t * the proprietary one from asus at the same time (which, b.t.w. only\n\t * makes sense during development). Otherwise, each access via the asus\n\t * driver will make access via this driver impossible.\n\t */\n\ti2c_init();\n\n\tspin_unlock_irq(&rtc_lock);\n\n\treturn 0;\n}\n\nstatic int rtc_release(UNUSED struct inode *inode, UNUSED struct file *filp)\n{\n\t/* No need for locking here. */\n\trtc_status &= ~RTC_IS_OPEN;\n\treturn 0;\n}\n\nstatic int from_bcd(int bcdnum)\n{\n\tint fac, num = 0;\n\n\tfor (fac = 1; bcdnum; fac *= 10) {\n\t\tnum += (bcdnum % 16) * fac;\n\t\tbcdnum /= 16;\n\t}\n\n\treturn num;\n}\n\nstatic int to_bcd(int decnum)\n{\n\tint fac, num = 0;\n\n\tfor (fac = 1; decnum; fac *= 16) {\n\t\tnum += (decnum % 10) * fac;\n\t\tdecnum /= 10;\n\t}\n\n\treturn num;\n}\n\nstatic void get_rtc_time(struct rtc_time *rtc_tm)\n{\n\tint cr2;\n\n\t/*\n\t * Read date and time from the RTC. We use read method (3).\n\t */\n\n\tspin_lock_irq(&rtc_lock);\n\ti2c_start();\n\ti2c_outb(RTC_I2C_ADDRESS | I2C_READ_MASK);\n\tcr2             = i2c_inb(I2C_ACK);\n\trtc_tm->tm_sec  = i2c_inb(I2C_ACK);\n\trtc_tm->tm_min  = i2c_inb(I2C_ACK);\n\trtc_tm->tm_hour = i2c_inb(I2C_ACK);\n\trtc_tm->tm_wday = i2c_inb(I2C_ACK);\n\trtc_tm->tm_mday = i2c_inb(I2C_ACK);\n\trtc_tm->tm_mon  = i2c_inb(I2C_ACK);\n\trtc_tm->tm_year = i2c_inb(I2C_NAK);\n\ti2c_stop();\n\tspin_unlock_irq(&rtc_lock);\n\n\tif (cr2 & RTC_VDET_MASK) {\n\t\tprintk(KERN_WARNING \"***RTC BATTERY FAILURE***\\n\");\n\t}\n\n\t/* Handle century bit */\n\tif (rtc_tm->tm_mon & RTC_Y2K_MASK) {\n\t\trtc_tm->tm_mon &= ~RTC_Y2K_MASK;\n\t\trtc_tm->tm_year += 0x100;\n\t}\n\n\trtc_tm->tm_sec  = from_bcd(rtc_tm->tm_sec);\n\trtc_tm->tm_min  = from_bcd(rtc_tm->tm_min);\n\trtc_tm->tm_hour = from_bcd(rtc_tm->tm_hour);\n\trtc_tm->tm_mday = from_bcd(rtc_tm->tm_mday);\n\trtc_tm->tm_mon  = from_bcd(rtc_tm->tm_mon) - 1;\n\trtc_tm->tm_year = from_bcd(rtc_tm->tm_year);\n\n\trtc_tm->tm_isdst = -1; /* DST not known */\n}\n\nstatic void set_rtc_time(struct rtc_time *rtc_tm)\n{\n\trtc_tm->tm_sec  = to_bcd(rtc_tm->tm_sec);\n\trtc_tm->tm_min  = to_bcd(rtc_tm->tm_min);\n\trtc_tm->tm_hour = to_bcd(rtc_tm->tm_hour);\n\trtc_tm->tm_mday = to_bcd(rtc_tm->tm_mday);\n\trtc_tm->tm_mon  = to_bcd(rtc_tm->tm_mon + 1);\n\trtc_tm->tm_year = to_bcd(rtc_tm->tm_year);\n\n\tif (rtc_tm->tm_year >= 0x100) {\n\t\trtc_tm->tm_year -= 0x100;\n\t\trtc_tm->tm_mon |= RTC_Y2K_MASK;\n\t}\n\n\tspin_lock_irq(&rtc_lock);\n\ti2c_start();\n\ti2c_outb(RTC_I2C_ADDRESS | I2C_WRITE_MASK);\n\ti2c_outb(0x00);\t/* set starting register to 0 (=seconds) */\n\ti2c_outb(rtc_tm->tm_sec);\n\ti2c_outb(rtc_tm->tm_min);\n\ti2c_outb(rtc_tm->tm_hour);\n\ti2c_outb(rtc_tm->tm_wday);\n\ti2c_outb(rtc_tm->tm_mday);\n\ti2c_outb(rtc_tm->tm_mon);\n\ti2c_outb(rtc_tm->tm_year);\n\ti2c_stop();\n\tspin_unlock_irq(&rtc_lock);\n}\n\nstatic ssize_t rtc_write(UNUSED struct file *filp, const char *buf,\n                         size_t count, loff_t *ppos)\n{\n\tstruct rtc_time rtc_tm;\n\tchar buffer[23];\n\tchar *p;\n\n\tif (!capable(CAP_SYS_TIME))\n\t\treturn -EACCES;\n\n\tif (ppos != &filp->f_pos)\n\t\treturn -ESPIPE;\n\n\t/*\n\t * For simplicity, the only acceptable format is:\n\t * YYYY:MM:DD:W:HH:MM:SS\\n\n\t */\n\n\tif (count != 22)\n\t\tgoto err_out;\n\n\tif (copy_from_user(buffer, buf, count))\n\t\treturn -EFAULT;\n\n\tbuffer[sizeof(buffer)-1] = '\\0';\n\n\tp = &buffer[0];\n\n\trtc_tm.tm_year  = simple_strtoul(p, &p, 10);\n\tif (*p++ != ':') goto err_out;\n\n\trtc_tm.tm_mon = simple_strtoul(p, &p, 10) - 1;\n\tif (*p++ != ':') goto err_out;\n\n\trtc_tm.tm_mday = simple_strtoul(p, &p, 10);\n\tif (*p++ != ':') goto err_out;\n\n\trtc_tm.tm_wday = simple_strtoul(p, &p, 10);\n\tif (*p++ != ':') goto err_out;\n\n\trtc_tm.tm_hour = simple_strtoul(p, &p, 10);\n\tif (*p++ != ':') goto err_out;\n\n\trtc_tm.tm_min = simple_strtoul(p, &p, 10);\n\tif (*p++ != ':') goto err_out;\n\n\trtc_tm.tm_sec = simple_strtoul(p, &p, 10);\n\tif (*p != '\\n') goto err_out;\n\n\trtc_tm.tm_year -= RTC_EPOCH;\n\n\tset_rtc_time(&rtc_tm);\n\n\t*ppos += count;\n\n\treturn count;\n\n err_out:\n\tprintk(KERN_ERR \"invalid format: use YYYY:MM:DD:W:HH:MM:SS\\\\n\\n\");\n\treturn -EINVAL;\n}\n\n\nstatic ssize_t rtc_read(UNUSED struct file *filp, char *buf, size_t count,\n                        loff_t *ppos)\n{\n\tchar wbuf[23];\n\tstruct rtc_time tm;\n\tssize_t len;\n\n\tif (count == 0 || *ppos != 0)\n\t\treturn 0;\n\n\tget_rtc_time(&tm);\n\n\tlen = sprintf(wbuf, \"%04d:%02d:%02d:%d:%02d:%02d:%02d\\n\",\n\t\t      tm.tm_year + RTC_EPOCH,\n\t\t      tm.tm_mon + 1,\n\t\t      tm.tm_mday,\n\t\t      tm.tm_wday,\n\t\t      tm.tm_hour,\n\t\t      tm.tm_min,\n\t\t      tm.tm_sec);\n\n\tif (len > (ssize_t)count)\n\t\tlen = count;\n\n\tif (copy_to_user(buf, wbuf, len))\n\t\treturn -EFAULT;\n\n\t*ppos += len;\n\n\treturn len;\n}\n\nstatic int rtc_do_ioctl(unsigned int cmd, unsigned long arg)\n{\n\tstruct rtc_time rtc_tm;\n\n\tswitch (cmd) {\n\t\tcase RTC_RD_TIME:\n\t\t\tmemset(&rtc_tm, 0, sizeof(struct rtc_time));\n\t\t\tget_rtc_time(&rtc_tm);\n\t\t\tif (copy_to_user((void *)arg, &rtc_tm, sizeof(rtc_tm)))\n\t\t\t\treturn -EFAULT;\n\t\t\tbreak;\n\n\t\tcase RTC_SET_TIME:\n\t\t\tif (!capable(CAP_SYS_TIME))\n\t\t\t\treturn -EACCES;\n\n\t\t\tif (copy_from_user(&rtc_tm, (struct rtc_time *)arg,\n\t\t\t\t\t   sizeof(struct rtc_time)))\n\t\t\t\treturn -EFAULT;\n\n\t\t\tset_rtc_time(&rtc_tm);\n\t\t\tbreak;\n\n\t\tdefault:\n\t\t\treturn -ENOTTY;\n\t}\n\n\treturn 0;\n}\n\nstatic long rtc_ioctl(struct file *file, unsigned int cmd, unsigned long arg)\n{\n\tlong ret;\n\tret = rtc_do_ioctl(cmd, arg);\n\treturn ret;\n}\n\nstatic const struct file_operations rtc_fops = {\n\t.owner\t\t= THIS_MODULE,\n\t.llseek\t\t= no_llseek,\n\t.read\t\t= rtc_read,\n\t.write\t\t= rtc_write,\n\t.unlocked_ioctl\t= rtc_ioctl,\n\t.open\t\t= rtc_open,\n\t.release\t= rtc_release,\n};\n\nstatic struct miscdevice rtc_dev = {\n\t.minor = RTC_MINOR,\n\t.name  = \"rtc\",\n\t.fops  = &rtc_fops,\n};\n\n/* Savagely ripped from diag.c.  */\nstatic inline int startswith (char *source, char *cmp)\n{\n\treturn !strncmp(source, cmp, strlen(cmp));\n}\n\nstatic void platform_detect(void)\n{\n\tchar buf[20];\n\tint et0phyaddr, et1phyaddr;\n\n\t/* Based on \"model_no\".  */\n\tif (bcm47xx_nvram_getenv(\"model_no\", buf, sizeof(buf)) >= 0) {\n\t\tif (startswith(buf, \"WL700\")) { /* WL700* */\n\t\t\tsda_index = 2;\n\t\t\tscl_index = 5;\n\t\t\treturn;\n\t\t}\n\t}\n\n\tif (bcm47xx_nvram_getenv(\"et0phyaddr\", buf, sizeof(buf)) >= 0 )\n\t\tet0phyaddr = simple_strtoul(buf, NULL, 0);\n\tif (bcm47xx_nvram_getenv(\"et1phyaddr\", buf, sizeof(buf)) >= 0 )\n\t\tet1phyaddr = simple_strtoul(buf, NULL, 0);\n\n\tif (bcm47xx_nvram_getenv(\"hardware_version\", buf, sizeof(buf)) >= 0) {\n\t\t/* Either WL-300g or WL-HDD, do more extensive checks */\n\t\tif (startswith(buf, \"WL300-\") && et0phyaddr == 0 && et1phyaddr == 1) {\n\t\t\tsda_index = 4;\n\t\t\tscl_index = 5;\n\t\t\treturn;\n\t\t}\n\t}\n\t/* not found */\n}\n\nstatic int __init rtc_init(void)\n{\n\tint cr1;\n\n\tplatform_detect();\n\n\tif (sda_index == scl_index) {\n\t\tprintk(KERN_ERR \"RTC-RV5C386A: unrecognized platform!\\n\");\n\t\treturn -ENODEV;\n\t}\n\n\ti2c_init();\n\n\t/*\n\t * Switch RTC to 24h mode\n\t */\n\tspin_lock_irq(&rtc_lock);\n\ti2c_start();\n\ti2c_outb(RTC_I2C_ADDRESS | I2C_WRITE_MASK);\n\ti2c_outb(0xE4); /* start at address 0xE, transmission mode 4 */\n\tcr1 = i2c_inb(I2C_NAK);\n\ti2c_stop();\n\tspin_unlock_irq(&rtc_lock);\n\tif ((cr1 & RTC_24HOUR_MODE_MASK) == 0) {\n\t\t/* RTC is running in 12h mode */\n\t\tprintk(KERN_INFO \"rtc.o: switching to 24h mode\\n\");\n\t\tspin_lock_irq(&rtc_lock);\n\t\ti2c_start();\n\t\ti2c_outb(RTC_I2C_ADDRESS | I2C_WRITE_MASK);\n\t\ti2c_outb(0xE0);\n\t\ti2c_outb(cr1 | RTC_24HOUR_MODE_MASK);\n\t\ti2c_stop();\n\t\tspin_unlock_irq(&rtc_lock);\n\t}\n\n\tmisc_register(&rtc_dev);\n\n\tprintk(KERN_INFO \"RV5C386A Real Time Clock Driver loaded\\n\");\n\n\treturn 0;\n}\n\nstatic void __exit rtc_exit (void)\n{\n\tmisc_deregister(&rtc_dev);\n\tprintk(KERN_INFO \"Successfully removed RTC RV5C386A driver\\n\");\n}\n\nmodule_init(rtc_init);\nmodule_exit(rtc_exit);\n\n/*\n * Local Variables:\n * indent-tabs-mode:t\n * c-basic-offset:8\n * End:\n */\n"
  },
  {
    "path": "package/kernel/rtl8812au-ct/Makefile",
    "content": "include $(TOPDIR)/rules.mk\n\nPKG_NAME:=rtl8812au-ct\nPKG_RELEASE=1\n\nPKG_LICENSE:=GPLv2\nPKG_LICENSE_FILES:=\n\nPKG_SOURCE_URL:=https://github.com/greearb/rtl8812AU_8821AU_linux.git\nPKG_MIRROR_HASH:=31e658df3e4d4c18c396259c2e0bef2bfc44a4aa870931f031a31e948be98af4\nPKG_SOURCE_PROTO:=git\nPKG_SOURCE_DATE:=2021-11-07\nPKG_SOURCE_VERSION:=39df55967b7de9f6c9600017b724303f95a8b9e2\n\nPKG_MAINTAINER:=Ben Greear <greearb@candelatech.com>\nPKG_BUILD_PARALLEL:=1\n#PKG_EXTMOD_SUBDIRS:=rtl8812au-ct\n\nSTAMP_CONFIGURED_DEPENDS := $(STAGING_DIR)/usr/include/mac80211-backport/backport/autoconf.h\n\ninclude $(INCLUDE_DIR)/kernel.mk\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine KernelPackage/rtl8812au-ct\n  SUBMENU:=Wireless Drivers\n  TITLE:=Driver for Realtek 8812 AU devices comfast 912-ac, etc\n  DEPENDS:=+kmod-cfg80211 +kmod-usb-core +@DRIVER_11N_SUPPORT +@DRIVER_11AC_SUPPORT\n  FILES:=\\\n\t$(PKG_BUILD_DIR)/rtl8812au.ko\n  AUTOLOAD:=$(call AutoProbe,rtl8812au)\n  PROVIDES:=kmod-rtl8812au\nendef\n\nNOSTDINC_FLAGS := \\\n\t$(KERNEL_NOSTDINC_FLAGS) \\\n\t-I$(PKG_BUILD_DIR) \\\n\t-I$(PKG_BUILD_DIR)/include \\\n\t-I$(STAGING_DIR)/usr/include/mac80211-backport \\\n\t-I$(STAGING_DIR)/usr/include/mac80211-backport/uapi \\\n\t-I$(STAGING_DIR)/usr/include/mac80211 \\\n\t-I$(STAGING_DIR)/usr/include/mac80211/uapi \\\n\t-include backport/backport.h\n\nNOSTDINC_FLAGS+=-DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT -DBUILD_OPENWRT\n\ndefine Build/Compile\n\t+$(MAKE) $(PKG_JOBS) -C \"$(LINUX_DIR)\" \\\n\t\t$(KERNEL_MAKE_FLAGS) \\\n\t\tM=\"$(PKG_BUILD_DIR)\" \\\n\t\tNOSTDINC_FLAGS=\"$(NOSTDINC_FLAGS)\" \\\n\t\tmodules\nendef\n\n$(eval $(call KernelPackage,rtl8812au-ct))\n"
  },
  {
    "path": "package/kernel/rtl8812au-ct/patches/001-use-kernel-byteorder.patch",
    "content": "Fix compile problem when rtw_byteorder.h and asm/byteorder.h gets \nincluded in addition for example indirectly, do not use realtek own copy \nof the byteorder headers.\n\n--- a/include/drv_types.h\n+++ b/include/drv_types.h\n@@ -30,7 +30,7 @@\n #include <drv_conf.h>\n #include <basic_types.h>\n #include <osdep_service.h>\n-#include <rtw_byteorder.h>\n+#include <asm/byteorder.h>\n #include <wlan_bssdef.h>\n #include <wifi.h>\n #include <ieee80211.h>\n"
  },
  {
    "path": "package/kernel/rtl8812au-ct/patches/002-vendor_command_policy.patch",
    "content": "mac80211 from kernel 5.3 and later checks the new policy attribute.\nAs this driver does not define any policies and does strange things, \njust tell mac80211 to ignore the policies.\n\n--- a/os_dep/linux/rtw_cfgvendor.c\n+++ b/os_dep/linux/rtw_cfgvendor.c\n@@ -1173,7 +1173,8 @@ static const struct wiphy_vendor_command\n \t\t\t.subcmd = BRCM_VENDOR_SCMD_PRIV_STR\n \t\t},\n \t\t.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,\n-\t\t.doit = wl_cfgvendor_priv_string_handler\n+\t\t.doit = wl_cfgvendor_priv_string_handler,\n+\t\t.policy = VENDOR_CMD_RAW_DATA,\n \t},\n #if defined(GSCAN_SUPPORT) && 0\n \t{\n@@ -1182,7 +1183,8 @@ static const struct wiphy_vendor_command\n \t\t\t.subcmd = GSCAN_SUBCMD_GET_CAPABILITIES\n \t\t},\n \t\t.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,\n-\t\t.doit = wl_cfgvendor_gscan_get_capabilities\n+\t\t.doit = wl_cfgvendor_gscan_get_capabilities,\n+\t\t.policy = VENDOR_CMD_RAW_DATA,\n \t},\n \t{\n \t\t{\n@@ -1190,7 +1192,8 @@ static const struct wiphy_vendor_command\n \t\t\t.subcmd = GSCAN_SUBCMD_SET_CONFIG\n \t\t},\n \t\t.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,\n-\t\t.doit = wl_cfgvendor_set_scan_cfg\n+\t\t.doit = wl_cfgvendor_set_scan_cfg,\n+\t\t.policy = VENDOR_CMD_RAW_DATA,\n \t},\n \t{\n \t\t{\n@@ -1198,7 +1201,8 @@ static const struct wiphy_vendor_command\n \t\t\t.subcmd = GSCAN_SUBCMD_SET_SCAN_CONFIG\n \t\t},\n \t\t.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,\n-\t\t.doit = wl_cfgvendor_set_batch_scan_cfg\n+\t\t.doit = wl_cfgvendor_set_batch_scan_cfg,\n+\t\t.policy = VENDOR_CMD_RAW_DATA,\n \t},\n \t{\n \t\t{\n@@ -1206,7 +1210,8 @@ static const struct wiphy_vendor_command\n \t\t\t.subcmd = GSCAN_SUBCMD_ENABLE_GSCAN\n \t\t},\n \t\t.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,\n-\t\t.doit = wl_cfgvendor_initiate_gscan\n+\t\t.doit = wl_cfgvendor_initiate_gscan,\n+\t\t.policy = VENDOR_CMD_RAW_DATA,\n \t},\n \t{\n \t\t{\n@@ -1214,7 +1219,8 @@ static const struct wiphy_vendor_command\n \t\t\t.subcmd = GSCAN_SUBCMD_ENABLE_FULL_SCAN_RESULTS\n \t\t},\n \t\t.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,\n-\t\t.doit = wl_cfgvendor_enable_full_scan_result\n+\t\t.doit = wl_cfgvendor_enable_full_scan_result,\n+\t\t.policy = VENDOR_CMD_RAW_DATA,\n \t},\n \t{\n \t\t{\n@@ -1222,7 +1228,8 @@ static const struct wiphy_vendor_command\n \t\t\t.subcmd = GSCAN_SUBCMD_SET_HOTLIST\n \t\t},\n \t\t.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,\n-\t\t.doit = wl_cfgvendor_hotlist_cfg\n+\t\t.doit = wl_cfgvendor_hotlist_cfg,\n+\t\t.policy = VENDOR_CMD_RAW_DATA,\n \t},\n \t{\n \t\t{\n@@ -1230,7 +1237,8 @@ static const struct wiphy_vendor_command\n \t\t\t.subcmd = GSCAN_SUBCMD_SET_SIGNIFICANT_CHANGE_CONFIG\n \t\t},\n \t\t.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,\n-\t\t.doit = wl_cfgvendor_significant_change_cfg\n+\t\t.doit = wl_cfgvendor_significant_change_cfg,\n+\t\t.policy = VENDOR_CMD_RAW_DATA,\n \t},\n \t{\n \t\t{\n@@ -1238,7 +1246,8 @@ static const struct wiphy_vendor_command\n \t\t\t.subcmd = GSCAN_SUBCMD_GET_SCAN_RESULTS\n \t\t},\n \t\t.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,\n-\t\t.doit = wl_cfgvendor_gscan_get_batch_results\n+\t\t.doit = wl_cfgvendor_gscan_get_batch_results,\n+\t\t.policy = VENDOR_CMD_RAW_DATA,\n \t},\n \t{\n \t\t{\n@@ -1246,7 +1255,8 @@ static const struct wiphy_vendor_command\n \t\t\t.subcmd = GSCAN_SUBCMD_GET_CHANNEL_LIST\n \t\t},\n \t\t.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,\n-\t\t.doit = wl_cfgvendor_gscan_get_channel_list\n+\t\t.doit = wl_cfgvendor_gscan_get_channel_list,\n+\t\t.policy = VENDOR_CMD_RAW_DATA,\n \t},\n #endif /* GSCAN_SUPPORT */\n #if defined(RTT_SUPPORT) && 0\n@@ -1256,7 +1266,8 @@ static const struct wiphy_vendor_command\n \t\t\t.subcmd = RTT_SUBCMD_SET_CONFIG\n \t\t},\n \t\t.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,\n-\t\t.doit = wl_cfgvendor_rtt_set_config\n+\t\t.doit = wl_cfgvendor_rtt_set_config,\n+\t\t.policy = VENDOR_CMD_RAW_DATA,\n \t},\n \t{\n \t\t{\n@@ -1264,7 +1275,8 @@ static const struct wiphy_vendor_command\n \t\t\t.subcmd = RTT_SUBCMD_CANCEL_CONFIG\n \t\t},\n \t\t.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,\n-\t\t.doit = wl_cfgvendor_rtt_cancel_config\n+\t\t.doit = wl_cfgvendor_rtt_cancel_config,\n+\t\t.policy = VENDOR_CMD_RAW_DATA,\n \t},\n \t{\n \t\t{\n@@ -1272,7 +1284,8 @@ static const struct wiphy_vendor_command\n \t\t\t.subcmd = RTT_SUBCMD_GETCAPABILITY\n \t\t},\n \t\t.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,\n-\t\t.doit = wl_cfgvendor_rtt_get_capability\n+\t\t.doit = wl_cfgvendor_rtt_get_capability,\n+\t\t.policy = VENDOR_CMD_RAW_DATA,\n \t},\n #endif /* RTT_SUPPORT */\n \t{\n@@ -1281,7 +1294,8 @@ static const struct wiphy_vendor_command\n \t\t\t.subcmd = ANDR_WIFI_SUBCMD_GET_FEATURE_SET\n \t\t},\n \t\t.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,\n-\t\t.doit = rtw_cfgvendor_get_feature_set\n+\t\t.doit = rtw_cfgvendor_get_feature_set,\n+\t\t.policy = VENDOR_CMD_RAW_DATA,\n \t},\n \t{\n \t\t{\n@@ -1289,7 +1303,8 @@ static const struct wiphy_vendor_command\n \t\t\t.subcmd = ANDR_WIFI_SUBCMD_GET_FEATURE_SET_MATRIX\n \t\t},\n \t\t.flags = WIPHY_VENDOR_CMD_NEED_WDEV | WIPHY_VENDOR_CMD_NEED_NETDEV,\n-\t\t.doit = rtw_cfgvendor_get_feature_set_matrix\n+\t\t.doit = rtw_cfgvendor_get_feature_set_matrix,\n+\t\t.policy = VENDOR_CMD_RAW_DATA,\n \t}\n };\n \n"
  },
  {
    "path": "package/kernel/rtl8812au-ct/patches/003-wireless-5.8.patch",
    "content": "--- a/os_dep/linux/ioctl_cfg80211.c\n+++ b/os_dep/linux/ioctl_cfg80211.c\n@@ -5177,6 +5177,15 @@ exit:\n \treturn ret;\n }\n \n+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 8, 0)) || defined(BUILD_OPENWRT)\n+static void cfg80211_rtw_update_mgmt_frame_registrations(struct wiphy *wiphy,\n+\t\t\t\t\t\t   struct wireless_dev *wdev,\n+\t\t\t\t\t\t   struct mgmt_frame_regs *upd)\n+{\n+\n+}\n+#endif\n+ \n #if defined(CONFIG_TDLS) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3,2,0))\n static int cfg80211_rtw_tdls_mgmt(struct wiphy *wiphy,\n \t\tstruct net_device *ndev,\n@@ -5990,7 +5999,10 @@ static struct cfg80211_ops rtw_cfg80211_\n \t.cancel_remain_on_channel = cfg80211_rtw_cancel_remain_on_channel,\n #endif\n \n-#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) || defined(COMPAT_KERNEL_RELEASE)\n+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5,8,0)) || defined(BUILD_OPENWRT)\n+\t.mgmt_tx = cfg80211_rtw_mgmt_tx,\n+\t.update_mgmt_frame_registrations = cfg80211_rtw_update_mgmt_frame_registrations,\n+#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) || defined(COMPAT_KERNEL_RELEASE)\n \t.mgmt_tx = cfg80211_rtw_mgmt_tx,\n #elif  (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,34) && LINUX_VERSION_CODE<=KERNEL_VERSION(2,6,35))\n \t.action = cfg80211_rtw_mgmt_tx,\n"
  },
  {
    "path": "package/kernel/trelay/Makefile",
    "content": "#\n# Copyright (C) 2012 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\ninclude $(INCLUDE_DIR)/kernel.mk\n\nPKG_NAME:=trelay\nPKG_RELEASE:=2\n\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine KernelPackage/trelay\n  SUBMENU:=Network Support\n  TITLE:=Trivial Ethernet Relay\n  FILES:=$(PKG_BUILD_DIR)/trelay.ko\n  AUTOLOAD:=$(call AutoLoad,50,trelay)\nendef\n\ndefine KernelPackage/trelay/description\ntrelay relays ethernet packets between two devices (similar to a bridge), but\nwithout any MAC address checks. This makes it possible to bridge client mode\nor ad-hoc mode wifi devices to ethernet VLANs, assuming the remote end uses\nthe same source MAC address as the device that packets are supposed to exit\nfrom.\nendef\n\ninclude $(INCLUDE_DIR)/kernel-defaults.mk\n\ndefine Build/Compile\n\t$(KERNEL_MAKE) M=\"$(PKG_BUILD_DIR)\" modules\nendef\n\ndefine KernelPackage/trelay/conffiles\n/etc/config/trelay\nendef\n\ndefine KernelPackage/trelay/install\n\t$(INSTALL_DIR) $(1)/etc/hotplug.d/net $(1)/etc/init.d $(1)/etc/config\n\t$(INSTALL_CONF) ./files/trelay.hotplug $(1)/etc/hotplug.d/net/50-trelay\n\t$(INSTALL_BIN) ./files/trelay.init $(1)/etc/init.d/trelay\n\t$(INSTALL_CONF) ./files/trelay.config $(1)/etc/config/trelay\nendef\n\n$(eval $(call KernelPackage,trelay))\n"
  },
  {
    "path": "package/kernel/trelay/files/trelay.config",
    "content": "config trelay\n\toption enabled\t0\n\toption dev1\teth0\n\toption dev2\twlan0\n"
  },
  {
    "path": "package/kernel/trelay/files/trelay.hotplug",
    "content": "case \"$ACTION\" in\n\tadd|register)\n\t\t[ -f /var/run/trelay.active ] && /etc/init.d/trelay start\n\t;;\nesac\n"
  },
  {
    "path": "package/kernel/trelay/files/trelay.init",
    "content": "#!/bin/sh /etc/rc.common\nSTART=80\n\ncheck_relay() {\n\tlocal cfg=\"$1\"\n\n\tconfig_get_bool enabled \"$cfg\" enabled 1\n\t[ \"$enabled\" -gt 0 ] || return\n\n\tconfig_get dev1 \"$cfg\" dev1\n\tconfig_get dev2 \"$cfg\" dev2\n\n\t[ -d \"/sys/kernel/debug/trelay/${dev1}-${dev2}\" ] && return\n\t[ -d \"/sys/class/net/${dev1}\" -a -d \"/sys/class/net/${dev2}\" ] || return\n\n\tip link set dev \"$dev1\" up\n\tip link set dev \"$dev2\" up\n\techo \"${dev1}-${dev2},${dev1},${dev2}\" > /sys/kernel/debug/trelay/add\n}\n\nstart() {\n\tconfig_load trelay\n\tconfig_foreach check_relay trelay\n\ttouch /var/run/trelay.active\n}\n\nstop() {\n\trm -f /var/run/trelay.active\n\tfor relay in /sys/kernel/debug/trelay/*; do\n\t\t[ -d \"$relay\" ] && echo > \"$relay/remove\"\n\tdone\n}\n"
  },
  {
    "path": "package/kernel/trelay/src/Makefile",
    "content": "obj-m   := trelay.o\n"
  },
  {
    "path": "package/kernel/trelay/src/trelay.c",
    "content": "/*\n * trelay.c: Trivial Ethernet Relay\n *\n * Copyright (C) 2012 Felix Fietkau <nbd@nbd.name>\n *\n * This program is free software; you can redistribute it and/or\n * modify it under the terms of the GNU General Public License\n * as published by the Free Software Foundation; either version 2\n * of the License, or (at your option) any later version.\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n * GNU General Public License for more details.\n */\n#include <linux/module.h>\n#include <linux/list.h>\n#include <linux/mutex.h>\n#include <linux/netdevice.h>\n#include <linux/rtnetlink.h>\n#include <linux/debugfs.h>\n\n#define trelay_log(loglevel, tr, fmt, ...) \\\n\tprintk(loglevel \"trelay: %s <-> %s: \" fmt \"\\n\", \\\n\t\ttr->dev1->name, tr->dev2->name, ##__VA_ARGS__);\n\nstatic LIST_HEAD(trelay_devs);\nstatic struct dentry *debugfs_dir;\n\nstruct trelay {\n\tstruct list_head list;\n\tstruct net_device *dev1, *dev2;\n\tstruct dentry *debugfs;\n\tint to_remove;\n\tchar name[];\n};\n\nrx_handler_result_t trelay_handle_frame(struct sk_buff **pskb)\n{\n\tstruct net_device *dev;\n\tstruct sk_buff *skb = *pskb;\n\n\tdev = rcu_dereference(skb->dev->rx_handler_data);\n\tif (!dev)\n\t\treturn RX_HANDLER_PASS;\n\n\tif (skb->protocol == htons(ETH_P_PAE))\n\t\treturn RX_HANDLER_PASS;\n\n\tskb_push(skb, ETH_HLEN);\n\tskb->dev = dev;\n\tskb_forward_csum(skb);\n\tdev_queue_xmit(skb);\n\n\treturn RX_HANDLER_CONSUMED;\n}\n\nstatic int trelay_open(struct inode *inode, struct file *file)\n{\n\tfile->private_data = inode->i_private;\n\treturn 0;\n}\n\nstatic int trelay_do_remove(struct trelay *tr)\n{\n\tlist_del(&tr->list);\n\n\t/* First and before all, ensure that the debugfs file is removed\n\t * to prevent dangling pointer in file->private_data */\n\tdebugfs_remove_recursive(tr->debugfs);\n\n\tdev_put(tr->dev1);\n\tdev_put(tr->dev2);\n\n\tnetdev_rx_handler_unregister(tr->dev1);\n\tnetdev_rx_handler_unregister(tr->dev2);\n\n\ttrelay_log(KERN_INFO, tr, \"stopped\");\n\n\tkfree(tr);\n\n\treturn 0;\n}\n\nstatic struct trelay *trelay_find(struct net_device *dev)\n{\n\tstruct trelay *tr;\n\n\tlist_for_each_entry(tr, &trelay_devs, list) {\n\t\tif (tr->dev1 == dev || tr->dev2 == dev)\n\t\t\treturn tr;\n\t}\n\treturn NULL;\n}\n\nstatic int tr_device_event(struct notifier_block *unused, unsigned long event,\n\t\t\t   void *ptr)\n{\n\tstruct net_device *dev = netdev_notifier_info_to_dev(ptr);\n\tstruct trelay *tr;\n\n\tif (event != NETDEV_UNREGISTER)\n\t\tgoto out;\n\n\ttr = trelay_find(dev);\n\tif (!tr)\n\t\tgoto out;\n\n\ttrelay_do_remove(tr);\n\nout:\n\treturn NOTIFY_DONE;\n}\n\nstatic ssize_t trelay_remove_write(struct file *file, const char __user *ubuf,\n\t\t\t\t   size_t count, loff_t *ppos)\n{\n\tstruct trelay *tr = file->private_data;\n\ttr->to_remove = 1;\n\n\treturn count;\n}\n\nstatic int trelay_remove_release(struct inode *inode, struct file *file)\n{\n\tstruct trelay *tr, *tmp;\n\n\t/* This is the only file op that is called outside debugfs_use_file_*()\n\t * context which means that: (1) this file can be removed and\n\t * (2) file->private_data may no longer be valid */\n\trtnl_lock();\n\tlist_for_each_entry_safe(tr, tmp, &trelay_devs, list)\n\t\tif (tr->to_remove)\n\t\t\ttrelay_do_remove(tr);\n\trtnl_unlock();\n\n\treturn 0;\n}\n\nstatic const struct file_operations fops_remove = {\n\t.owner = THIS_MODULE,\n\t.open = trelay_open,\n\t.write = trelay_remove_write,\n\t.llseek = default_llseek,\n\t.release = trelay_remove_release,\n};\n\n\nstatic int trelay_do_add(char *name, char *devn1, char *devn2)\n{\n\tstruct net_device *dev1, *dev2;\n\tstruct trelay *tr, *tr1;\n\tint ret;\n\n\ttr = kzalloc(sizeof(*tr) + strlen(name) + 1, GFP_KERNEL);\n\tif (!tr)\n\t\treturn -ENOMEM;\n\n\trtnl_lock();\n\trcu_read_lock();\n\n\tret = -EEXIST;\n\tlist_for_each_entry(tr1, &trelay_devs, list) {\n\t\tif (!strcmp(tr1->name, name))\n\t\t\tgoto out;\n\t}\n\n\tret = -ENOENT;\n\tdev1 = dev_get_by_name_rcu(&init_net, devn1);\n\tdev2 = dev_get_by_name_rcu(&init_net, devn2);\n\tif (!dev1 || !dev2)\n\t\tgoto out;\n\n\tret = netdev_rx_handler_register(dev1, trelay_handle_frame, dev2);\n\tif (ret < 0)\n\t\tgoto out;\n\n\tret = netdev_rx_handler_register(dev2, trelay_handle_frame, dev1);\n\tif (ret < 0) {\n\t\tnetdev_rx_handler_unregister(dev1);\n\t\tgoto out;\n\t}\n\n\tdev_hold(dev1);\n\tdev_hold(dev2);\n\n\tstrcpy(tr->name, name);\n\ttr->dev1 = dev1;\n\ttr->dev2 = dev2;\n\tlist_add_tail(&tr->list, &trelay_devs);\n\n\ttrelay_log(KERN_INFO, tr, \"started\");\n\n\ttr->debugfs = debugfs_create_dir(name, debugfs_dir);\n\tdebugfs_create_file(\"remove\", S_IWUSR, tr->debugfs, tr, &fops_remove);\n\tret = 0;\n\nout:\n\trcu_read_unlock();\n\trtnl_unlock();\n\tif (ret < 0)\n\t\tkfree(tr);\n\n\treturn ret;\n}\n\nstatic ssize_t trelay_add_write(struct file *file, const char __user *ubuf,\n\t\t\t\tsize_t count, loff_t *ppos)\n{\n\tchar buf[256];\n\tchar *dev1, *dev2, *tmp;\n\tssize_t len, ret;\n\n\tlen = min(count, sizeof(buf) - 1);\n\tif (copy_from_user(buf, ubuf, len))\n\t\treturn -EFAULT;\n\n\tbuf[len] = 0;\n\n\tif ((tmp = strchr(buf, '\\n')))\n\t\t*tmp = 0;\n\n\tdev1 = strchr(buf, ',');\n\tif (!dev1)\n\t\treturn -EINVAL;\n\n\t*(dev1++) = 0;\n\n\tdev2 = strchr(dev1, ',');\n\tif (!dev2)\n\t\treturn -EINVAL;\n\n\t*(dev2++) = 0;\n\tif (strchr(dev2, ','))\n\t\treturn -EINVAL;\n\n\tif (!strlen(buf) || !strlen(dev1) || !strlen(dev2))\n\t\treturn -EINVAL;\n\n\tret = trelay_do_add(buf, dev1, dev2);\n\tif (ret < 0)\n\t\treturn ret;\n\n\treturn count;\n}\n\nstatic const struct file_operations fops_add = {\n\t.owner = THIS_MODULE,\n\t.write = trelay_add_write,\n\t.llseek = default_llseek,\n};\n\nstatic struct notifier_block tr_dev_notifier = {\n\t.notifier_call = tr_device_event\n};\n\nstatic int __init trelay_init(void)\n{\n\tint ret;\n\n\tdebugfs_dir = debugfs_create_dir(\"trelay\", NULL);\n\tif (!debugfs_dir)\n\t\treturn -ENOMEM;\n\n\tdebugfs_create_file(\"add\", S_IWUSR, debugfs_dir, NULL, &fops_add);\n\n\tret = register_netdevice_notifier(&tr_dev_notifier);\n\tif (ret < 0)\n\t\tgoto error;\n\n\treturn 0;\n\nerror:\n\tdebugfs_remove_recursive(debugfs_dir);\n\treturn ret;\n}\n\nstatic void __exit trelay_exit(void)\n{\n\tstruct trelay *tr, *tmp;\n\n\tunregister_netdevice_notifier(&tr_dev_notifier);\n\n\trtnl_lock();\n\tlist_for_each_entry_safe(tr, tmp, &trelay_devs, list)\n\t\ttrelay_do_remove(tr);\n\trtnl_unlock();\n\n\tdebugfs_remove_recursive(debugfs_dir);\n}\n\nmodule_init(trelay_init);\nmodule_exit(trelay_exit);\nMODULE_LICENSE(\"GPL\");\n"
  },
  {
    "path": "package/libs/argp-standalone/Makefile",
    "content": "#\n# Copyright (C) 2007-2014 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=argp-standalone\nPKG_VERSION:=1.3\nPKG_RELEASE:=2\n\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz\nPKG_SOURCE_URL:=http://www.lysator.liu.se/~nisse/misc/\nPKG_HASH:=dec79694da1319acd2238ce95df57f3680fea2482096e483323fddf3d818d8be\nPKG_MAINTAINER:=Ted Hess <thess@kitschensync.net>\n\nPKG_LICENSE:=LGPL-2.1\nPKG_LICENSE:=Makefile.am\n\ninclude $(INCLUDE_DIR)/package.mk\ninclude $(INCLUDE_DIR)/host-build.mk\n\ndefine Package/argp-standalone\n  SECTION:=libs\n  CATEGORY:=Libraries\n  TITLE:=Hierarchial argument parsing broken out from glibc\n  URL:=http://www.lysator.liu.se/~nisse/misc/\nendef\n\ndefine Package/argp-standalone/description\n  GNU libc hierarchial argument parsing library broken out from glibc.\nendef\n\nMAKE_FLAGS += \\\n\tCFLAGS=\"$(TARGET_CFLAGS) $(FPIC) -std=gnu89\"\n\nHOST_MAKE_FLAGS += \\\n\tCFLAGS=\"$(HOST_CFLAGS) $(FPIC) -std=gnu89\"\n\ndefine Build/InstallDev\n\t$(INSTALL_DIR) $(1)/usr/include\n\t$(CP)   $(PKG_BUILD_DIR)/argp.h \\\n\t\t$(1)/usr/include/\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(CP)   $(PKG_BUILD_DIR)/libargp.a \\\n\t\t$(1)/usr/lib/\nendef\n\ndefine Host/Install\n\t$(INSTALL_DIR) $(1)/include\n\t$(CP)   $(HOST_BUILD_DIR)/argp.h \\\n\t\t$(1)/include/\n\t$(INSTALL_DIR) $(1)/lib\n\t$(CP)   $(HOST_BUILD_DIR)/libargp.a \\\n\t\t$(1)/lib/\nendef\n\n$(eval $(call BuildPackage,argp-standalone))\n$(eval $(call HostBuild))\n"
  },
  {
    "path": "package/libs/argp-standalone/patches/001-throw-in-funcdef.patch",
    "content": "# --- T2-COPYRIGHT-NOTE-BEGIN ---\n# This copyright note is auto-generated by ./scripts/Create-CopyPatch.\n# \n# T2 SDE: package/.../rng-tools/throw-in-funcdef.patch.argp-standalone\n# Copyright (C) 2006 The T2 SDE Project\n# \n# More information can be found in the files COPYING and README.\n# \n# This patch file is dual-licensed. It is available under the license the\n# patched project is licensed under, as long as it is an OpenSource license\n# as defined at http://www.opensource.org/ (e.g. BSD, X11) or under the terms\n# of the GNU General Public License as published by the Free Software\n# Foundation; either version 2 of the License, or (at your option) any later\n# version.\n# --- T2-COPYRIGHT-NOTE-END ---\n\n\nNo __THROW in function implementation.\n\t--jsaw\n\n--- a/argp.h\n+++ b/argp.h\n@@ -560,17 +560,17 @@ __argp_short_program_name(const struct a\n # endif\n \n # ifndef ARGP_EI\n-#  define ARGP_EI extern __inline__\n+#  define ARGP_EI extern inline\n # endif\n \n ARGP_EI void\n-__argp_usage (__const struct argp_state *__state) __THROW\n+__argp_usage (__const struct argp_state *__state)\n {\n   __argp_state_help (__state, stderr, ARGP_HELP_STD_USAGE);\n }\n \n ARGP_EI int\n-__option_is_short (__const struct argp_option *__opt) __THROW\n+__option_is_short (__const struct argp_option *__opt)\n {\n   if (__opt->flags & OPTION_DOC)\n     return 0;\n@@ -582,7 +582,7 @@ __option_is_short (__const struct argp_o\n }\n \n ARGP_EI int\n-__option_is_end (__const struct argp_option *__opt) __THROW\n+__option_is_end (__const struct argp_option *__opt)\n {\n   return !__opt->key && !__opt->name && !__opt->doc && !__opt->group;\n }\n--- a/argp-parse.c\n+++ b/argp-parse.c\n@@ -1277,13 +1277,13 @@ weak_alias (__argp_input, _argp_input)\n /* Defined here, in case a user is not inlining the definitions in\n  * argp.h */\n void\n-__argp_usage (__const struct argp_state *__state) __THROW\n+__argp_usage (__const struct argp_state *__state)\n {\n   __argp_state_help (__state, stderr, ARGP_HELP_STD_USAGE);\n }\n \n int\n-__option_is_short (__const struct argp_option *__opt) __THROW\n+__option_is_short (__const struct argp_option *__opt) \n {\n   if (__opt->flags & OPTION_DOC)\n     return 0;\n@@ -1297,7 +1297,7 @@ __option_is_short (__const struct argp_o\n }\n \n int\n-__option_is_end (__const struct argp_option *__opt) __THROW\n+__option_is_end (__const struct argp_option *__opt) \n {\n   return !__opt->key && !__opt->name && !__opt->doc && !__opt->group;\n }\n"
  },
  {
    "path": "package/libs/argp-standalone/patches/002-no_optimize.patch",
    "content": "--- a/argp-fmtstream.h\n+++ b/argp-fmtstream.h\n@@ -192,7 +192,7 @@ extern void __argp_fmtstream_update (arg\n extern int _argp_fmtstream_ensure (argp_fmtstream_t __fs, size_t __amount);\n extern int __argp_fmtstream_ensure (argp_fmtstream_t __fs, size_t __amount);\n \f\n-#ifdef __OPTIMIZE__\n+#if 0\n /* Inline versions of above routines.  */\n \n #if !_LIBC\n"
  },
  {
    "path": "package/libs/argp-standalone/patches/900-fix-segfault-in_canon_doc_option.patch",
    "content": "--- a/argp-help.c\n+++ b/argp-help.c\n@@ -777,9 +777,9 @@ hol_entry_cmp (const struct hol_entry *e\n       const char *long2 = hol_entry_first_long (entry2);\n \n       if (doc1)\n-\tdoc1 = canon_doc_option (&long1);\n+        doc1 = long1 != NULL && canon_doc_option (&long1);\n       if (doc2)\n-\tdoc2 = canon_doc_option (&long2);\n+\tdoc2 = long2 != NULL && canon_doc_option (&long2);\n \n       if (doc1 != doc2)\n \t/* `documentation' options always follow normal options (or\n"
  },
  {
    "path": "package/libs/elfutils/Makefile",
    "content": "#\n# Copyright (C) 2010-2019 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=elfutils\nPKG_VERSION:=0.186\nPKG_RELEASE:=1\n\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.bz2\nPKG_SOURCE_URL:=https://sourceware.org/$(PKG_NAME)/ftp/$(PKG_VERSION)\nPKG_HASH:=7f6fb9149b1673d38d9178a0d3e0fb8a1ec4f53a9f4c2ff89469609879641177\n\nPKG_MAINTAINER:=Luiz Angelo Daros de Luca <luizluca@gmail.com>\nPKG_LICENSE:=GPL-3.0-or-later\nPKG_LICENSE_FILES:=COPYING COPYING-GPLV2 COPYING-LGPLV3\nPKG_CPE_ID:=cpe:/a:elfutils_project:elfutils\n\nPKG_FIXUP:=autoreconf\nPKG_INSTALL:=1\nPKG_USE_MIPS16:=1\nPKG_BUILD_DEPENDS:=!USE_GLIBC:argp-standalone\n\nHOST_BUILD_DEPENDS:=argp-standalone/host musl-fts/host\n\ninclude $(INCLUDE_DIR)/package.mk\ninclude $(INCLUDE_DIR)/nls.mk\ninclude $(INCLUDE_DIR)/host-build.mk\n\ndefine Package/elfutils/Default\n  SECTION:=libs\n  CATEGORY:=Libraries\n  TITLE:=ELF manipulation libraries\n  URL:=https://fedorahosted.org/elfutils/\n  ABI_VERSION:=1\nendef\n\ndefine Package/libasm\n  $(call Package/elfutils/Default)\n  TITLE+= (libasm)\n  DEPENDS:=+libelf +libdw\nendef\n\ndefine Package/libdw\n  $(call Package/elfutils/Default)\n  DEPENDS:=+libelf +libbz2 +USE_MUSL:musl-fts\n  TITLE+= (libdw)\nendef\n\ndefine Package/libelf\n  $(call Package/elfutils/Default)\n  DEPENDS:=$(INTL_DEPENDS) +zlib\n  TITLE+= (libelf)\n  PROVIDES:=libelf1\nendef\n\nifeq ($(CONFIG_BUILD_NLS),y)\nTARGET_LDFLAGS += -lintl\nelse\nCONFIGURE_ARGS += --disable-nls\nendif\n\nHOST_CONFIGURE_ARGS += \\\n\t--disable-shared \\\n\t--disable-nls \\\n\t--disable-debuginfod \\\n\t--disable-libdebuginfod \\\n\t--without-lzma \\\n\t--without-zstd\n\nCONFIGURE_ARGS += \\\n\t--program-prefix=eu- \\\n\t--disable-debuginfod \\\n\t--disable-libdebuginfod \\\n\t--without-lzma \\\n\t--without-zstd\n\nHOST_CONFIGURE_VARS += \\\n\tac_cv_search__obstack_free=yes\n\nCONFIGURE_VARS += \\\n\tac_cv_search__obstack_free=yes\n\nTARGET_CFLAGS += -D_GNU_SOURCE -Wno-unused-result -Wno-format-nonliteral\n\ndefine Build/InstallDev\n\t$(INSTALL_DIR) $(1)/usr/include\n\t$(CP) $(PKG_INSTALL_DIR)/usr/include/* $(1)/usr/include/\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/libasm*.{a,so*} $(1)/usr/lib/\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/libdw*.{a,so*} $(1)/usr/lib/\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/libelf*.{a,so*} $(1)/usr/lib/\n\t$(INSTALL_DIR) $(1)/usr/lib/pkgconfig\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/pkgconfig/libelf.pc $(1)/usr/lib/pkgconfig/\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/pkgconfig/libdw.pc $(1)/usr/lib/pkgconfig/\nendef\n\ndefine Package/libasm/install\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/libasm{-*.so,*.so.*} $(1)/usr/lib/\nendef\n\ndefine Package/libdw/install\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/libdw{-*.so,*.so.*} $(1)/usr/lib/\nendef\n\ndefine Package/libelf/install\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/libelf{-*.so,*.so.*} $(1)/usr/lib/\nendef\n\n# these lines need to be ordered by dependency because of ABI versioning\n$(eval $(call HostBuild))\n$(eval $(call BuildPackage,libelf))\n$(eval $(call BuildPackage,libdw))\n$(eval $(call BuildPackage,libasm))\n"
  },
  {
    "path": "package/libs/elfutils/patches/003-libintl-compatibility.patch",
    "content": "--- a/config/libelf.pc.in\n+++ b/config/libelf.pc.in\n@@ -8,7 +8,7 @@ Description: elfutils libelf library to\n Version: @VERSION@\n URL: http://elfutils.org/\n \n-Libs: -L${libdir} -lelf\n+Libs: -L${libdir} -lelf @intl_LDFLAGS@\n Cflags: -I${includedir}\n \n Requires.private: zlib\n--- a/configure.ac\n+++ b/configure.ac\n@@ -610,6 +610,9 @@ dnl AM_GNU_GETTEXT_REQUIRE_VERSION suppo\n AM_GNU_GETTEXT_VERSION([0.19.6])\n AM_GNU_GETTEXT_REQUIRE_VERSION([0.19.6])\n \n+case \"$USE_NLS\" in yes) intl_LDFLAGS=\"-lintl\" ;; esac\n+AC_SUBST([intl_LDFLAGS])\n+\n dnl Appended to the config.h file.\n dnl We hide all kinds of configuration magic in lib/eu-config.h.\n AH_BOTTOM([#include <eu-config.h>])\n"
  },
  {
    "path": "package/libs/elfutils/patches/005-build_only_libs.patch",
    "content": "--- a/Makefile.am\n+++ b/Makefile.am\n@@ -27,7 +27,7 @@ AM_MAKEFLAGS = --no-print-directory\n pkginclude_HEADERS = version.h\n \n SUBDIRS = config lib libelf libcpu backends libebl libdwelf libdwfl libdw \\\n-\t  libasm debuginfod src po doc tests\n+\t  libasm\n \n EXTRA_DIST = elfutils.spec GPG-KEY NOTES CONTRIBUTING \\\n \t     COPYING COPYING-GPLV2 COPYING-LGPLV3\n"
  },
  {
    "path": "package/libs/elfutils/patches/006-Fix-build-on-aarch64-musl.patch",
    "content": "From 578f370c7e7a9f056aefa062b34590b0aa13bce5 Mon Sep 17 00:00:00 2001\nFrom: Hongxu Jia <hongxu.jia@windriver.com>\nDate: Tue, 15 Aug 2017 17:27:30 +0800\nSubject: [PATCH] Fix build on aarch64/musl\n\nErrors\n\ninvalid operands to binary & (have 'long double' and 'unsigned int')\n\nerror: redefinition\n of 'struct iovec'\n struct iovec { void *iov_base; size_t iov_len; };\n        ^\nUpstream-Status: Pending\nSigned-off-by: Khem Raj <raj.khem@gmail.com>\n\nRebase to 0.170\nSigned-off-by: Hongxu Jia <hongxu.jia@windriver.com>\n\n---\n backends/aarch64_initreg.c | 4 ++--\n backends/arm_initreg.c     | 2 +-\n 2 files changed, 3 insertions(+), 3 deletions(-)\n\n--- a/backends/aarch64_initreg.c\n+++ b/backends/aarch64_initreg.c\n@@ -33,7 +33,7 @@\n #include \"system.h\"\n #include <assert.h>\n #if defined(__aarch64__) && defined(__linux__)\n-# include <linux/uio.h>\n+# include <sys/uio.h>\n # include <sys/user.h>\n # include <sys/ptrace.h>\n /* Deal with old glibc defining user_pt_regs instead of user_regs_struct.  */\n@@ -82,7 +82,7 @@ aarch64_set_initial_registers_tid (pid_t\n \n   Dwarf_Word dwarf_fregs[32];\n   for (int r = 0; r < 32; r++)\n-    dwarf_fregs[r] = fregs.vregs[r] & 0xFFFFFFFF;\n+    dwarf_fregs[r] = (unsigned int)fregs.vregs[r] & 0xFFFFFFFF;\n \n   if (! setfunc (64, 32, dwarf_fregs, arg))\n     return false;\n--- a/backends/arm_initreg.c\n+++ b/backends/arm_initreg.c\n@@ -38,7 +38,7 @@\n #endif\n \n #ifdef __aarch64__\n-# include <linux/uio.h>\n+# include <sys/uio.h>\n # include <sys/user.h>\n # include <sys/ptrace.h>\n /* Deal with old glibc defining user_pt_regs instead of user_regs_struct.  */\n"
  },
  {
    "path": "package/libs/elfutils/patches/100-musl-compat.patch",
    "content": "--- a/libdw/libdw_alloc.c\n+++ b/libdw/libdw_alloc.c\n@@ -152,5 +152,5 @@ __attribute ((noreturn)) attribute_hidde\n __libdw_oom (void)\n {\n   while (1)\n-    error (EXIT_FAILURE, ENOMEM, \"libdw\");\n+    error (EXIT_FAILURE, errno, gettext (\"cannot allocate memory\"));\n }\n--- a/libdwfl/dwfl_error.c\n+++ b/libdwfl/dwfl_error.c\n@@ -140,6 +140,7 @@ __libdwfl_seterrno (Dwfl_Error error)\n static const char *\n errnomsg(int error)\n {\n+#if defined(__GLIBC__) && !defined(__UCLIBC__)\n   /* Won't be changed by strerror_r, but not const so compiler doesn't throw warning */\n   static char unknown[] = \"unknown error\";\n \n@@ -150,6 +151,9 @@ errnomsg(int error)\n   static __thread char msg[128];\n   return strerror_r (error, msg, sizeof (msg)) ? unknown : msg;\n #endif\n+#else\n+  return strerror (error & 0xffff);\n+#endif\n }\n \n const char *\n"
  },
  {
    "path": "package/libs/elfutils/patches/101-no-fts.patch",
    "content": "--- a/libdwfl/argp-std.c\n+++ b/libdwfl/argp-std.c\n@@ -53,9 +53,6 @@ static const struct argp_option options[\n   { \"linux-process-map\", 'M', \"FILE\", 0,\n     N_(\"Find addresses in files mapped as read from FILE\"\n        \" in Linux /proc/PID/maps format\"), 0 },\n-  { \"kernel\", 'k', NULL, 0, N_(\"Find addresses in the running kernel\"), 0 },\n-  { \"offline-kernel\", 'K', \"RELEASE\", OPTION_ARG_OPTIONAL,\n-    N_(\"Kernel with all modules\"), 0 },\n   { \"debuginfo-path\", OPT_DEBUGINFO, \"PATH\", 0,\n     N_(\"Search path for separate debuginfo files\"), 0 },\n   { NULL, 0, NULL, 0, NULL, 0 }\n@@ -82,15 +79,6 @@ static const Dwfl_Callbacks proc_callbac\n     .find_elf = INTUSE(dwfl_linux_proc_find_elf),\n   };\n \n-static const Dwfl_Callbacks kernel_callbacks =\n-  {\n-    .find_debuginfo = INTUSE(dwfl_standard_find_debuginfo),\n-    .debuginfo_path = &debuginfo_path,\n-\n-    .find_elf = INTUSE(dwfl_linux_kernel_find_elf),\n-    .section_address = INTUSE(dwfl_linux_kernel_module_section_address),\n-  };\n-\n /* Structure held at state->HOOK.  */\n struct parse_opt\n {\n@@ -223,43 +211,6 @@ parse_opt (int key, char *arg, struct ar\n       }\n       break;\n \n-    case 'k':\n-      {\n-\tstruct parse_opt *opt = state->hook;\n-\tif (opt->dwfl == NULL)\n-\t  {\n-\t    Dwfl *dwfl = INTUSE(dwfl_begin) (&kernel_callbacks);\n-\t    int result = INTUSE(dwfl_linux_kernel_report_kernel) (dwfl);\n-\t    if (result != 0)\n-\t      return fail (dwfl, result, _(\"cannot load kernel symbols\"), state);\n-\t    result = INTUSE(dwfl_linux_kernel_report_modules) (dwfl);\n-\t    if (result != 0)\n-\t      /* Non-fatal to have no modules since we do have the kernel.  */\n-\t      argp_failure (state, 0, result, _(\"cannot find kernel modules\"));\n-\t    opt->dwfl = dwfl;\n-\t  }\n-\telse\n-\t  goto toomany;\n-      }\n-      break;\n-\n-    case 'K':\n-      {\n-\tstruct parse_opt *opt = state->hook;\n-\tif (opt->dwfl == NULL)\n-\t  {\n-\t    Dwfl *dwfl = INTUSE(dwfl_begin) (&offline_callbacks);\n-\t    int result = INTUSE(dwfl_linux_kernel_report_offline) (dwfl, arg,\n-\t\t\t\t\t\t\t\t   NULL);\n-\t    if (result != 0)\n-\t      return fail (dwfl, result, _(\"cannot find kernel or modules\"), state);\n-\t    opt->dwfl = dwfl;\n-\t  }\n-\telse\n-\t  goto toomany;\n-      }\n-      break;\n-\n     case ARGP_KEY_SUCCESS:\n       {\n \tstruct parse_opt *opt = state->hook;\n--- a/libdwfl/Makefile.am\n+++ b/libdwfl/Makefile.am\n@@ -50,7 +50,7 @@ libdwfl_a_SOURCES = dwfl_begin.c dwfl_en\n \t\t    argp-std.c find-debuginfo.c \\\n \t\t    dwfl_build_id_find_elf.c \\\n \t\t    dwfl_build_id_find_debuginfo.c \\\n-\t\t    linux-kernel-modules.c linux-proc-maps.c \\\n+\t\t    linux-proc-maps.c \\\n \t\t    dwfl_addrmodule.c dwfl_addrdwarf.c \\\n \t\t    cu.c dwfl_module_nextcu.c dwfl_nextcu.c dwfl_cumodule.c \\\n \t\t    dwfl_module_addrdie.c dwfl_addrdie.c \\\n"
  },
  {
    "path": "package/libs/gettext-full/Makefile",
    "content": "#\n# Copyright (C) 2006-2015 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=gettext-full\nPKG_VERSION:=0.21\nPKG_RELEASE:=2\n\nPKG_SOURCE:=gettext-$(PKG_VERSION).tar.xz\nPKG_SOURCE_URL:=@GNU/gettext\nPKG_HASH:=d20fcbb537e02dcf1383197ba05bd0734ef7bf5db06bdb241eb69b7d16b73192\nPKG_BUILD_DIR:=$(BUILD_DIR)/gettext-$(PKG_VERSION)\nHOST_BUILD_DIR:=$(BUILD_DIR_HOST)/gettext-$(PKG_VERSION)\n\nPKG_MAINTAINER:=Jo-Philipp Wich <jo@mein.io>\nPKG_LICENSE:=GPL-3.0-or-later\nPKG_CPE_ID:=cpe:/a:gnu:gettext\n\nPKG_FIXUP:=autoreconf\nPKG_INSTALL:=1\nPKG_BUILD_DEPENDS:=gettext-full/host\nPKG_BUILD_PARALLEL:=0\nHOST_BUILD_PARALLEL:=0\n\ninclude $(INCLUDE_DIR)/package.mk\ninclude $(INCLUDE_DIR)/host-build.mk\n\ndefine Package/libintl-full\n  SECTION:=libs\n  CATEGORY:=Libraries\n  TITLE:=GNU Internationalization library\n  URL:=http://www.gnu.org/software/gettext/\n  ABI_VERSION:=8\nendef\n\nTARGET_CFLAGS += $(FPIC)\nifneq ($(HOST_OS),Linux)\n  TARGET_CFLAGS += -I$(STAGING_DIR_HOSTPKG)/include\nendif\n\nCONFIGURE_ARGS += \\\n\t--enable-shared \\\n\t--enable-static \\\n\t--disable-libasprintf \\\n\t--disable-rpath \\\n\t--enable-nls \\\n\t--disable-java \\\n\t--disable-openmp \\\n\t--disable-curses \\\n\t--with-included-gettext \\\n\t--without-libintl-prefix \\\n\t--without-libexpat-prefix \\\n\t--without-emacs\n\nHOST_CONFIGURE_ARGS += \\\n\t--disable-shared \\\n\t--enable-static \\\n\t--disable-libasprintf \\\n\t--disable-rpath \\\n\t--disable-java \\\n\t--disable-openmp \\\n\t--without-emacs \\\n\t--without-libxml2-prefix\n\nHOST_CONFIGURE_VARS += \\\n\tEMACS=\"no\" \\\n\tam_cv_lib_iconv=no \\\n\tam_cv_func_iconv=no \\\n\tac_cv_header_iconv_h=no \\\n\nHOST_CFLAGS += $(HOST_FPIC)\n\ndefine Build/InstallDev\n\t$(INSTALL_DIR) $(1)/usr/lib/libintl-full/include\n\t$(CP) $(PKG_INSTALL_DIR)/usr/include/libintl.h $(1)/usr/lib/libintl-full/include/\n\n\t$(INSTALL_DIR) $(1)/usr/lib/libintl-full/lib\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/libintl.{a,so*} $(1)/usr/lib/libintl-full/lib/\n\n\t$(INSTALL_DIR) $(1)/usr/share/aclocal\n\t$(INSTALL_DATA) $(PKG_INSTALL_DIR)/usr/share/aclocal/* $(1)/usr/share/aclocal/\n\n\t$(SED) '/read dummy/d' $(STAGING_DIR_HOSTPKG)/bin/gettextize\nendef\n\ndefine Host/Install\n\t$(call Host/Install/Default)\n\t$(LN) msgfmt $(STAGING_DIR_HOSTPKG)/bin/gmsgfmt\nendef\n\ndefine Package/libintl-full/install\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/libintl.so.* $(1)/usr/lib/\nendef\n\n$(eval $(call HostBuild))\n$(eval $(call BuildPackage,libintl-full))\n"
  },
  {
    "path": "package/libs/gettext-full/patches/000-relocatable.patch",
    "content": "--- a/gettext-tools/misc/autopoint.in\n+++ b/gettext-tools/misc/autopoint.in\n@@ -27,7 +27,11 @@ archive_version=@ARCHIVE_VERSION@\n \n # Set variables\n # - gettext_datadir     directory where the data files are stored.\n-prefix=\"@prefix@\"\n+if [ -n \"$STAGING_DIR_HOSTPKG\" ]; then\n+\tprefix=\"$STAGING_DIR_HOSTPKG\"\n+else\n+\tprefix=\"@prefix@\"\n+fi\n datarootdir=\"@datarootdir@\"\n : ${gettext_datadir=\"@datadir@/gettext\"}\n : ${AUTOM4TE=autom4te}\n--- a/gettext-tools/misc/gettextize.in\n+++ b/gettext-tools/misc/gettextize.in\n@@ -27,7 +27,11 @@ archive_version=@ARCHIVE_VERSION@\n \n # Set variables\n # - gettext_datadir     directory where the data files are stored.\n-prefix=\"@prefix@\"\n+if [ -n \"$STAGING_DIR_HOSTPKG\" ]; then\n+\tprefix=\"$STAGING_DIR_HOSTPKG\"\n+else\n+\tprefix=\"@prefix@\"\n+fi\n datarootdir=\"@datarootdir@\"\n : ${gettext_datadir=\"@datadir@/gettext\"}\n : ${AUTOM4TE=autom4te}\n"
  },
  {
    "path": "package/libs/gettext-full/patches/001-autotools.patch",
    "content": "--- a/gettext-runtime/man/Makefile.am\n+++ b/gettext-runtime/man/Makefile.am\n@@ -176,8 +176,7 @@ textdomain.3.html: textdomain.3.in\n bindtextdomain.3.html: bindtextdomain.3.in\n bind_textdomain_codeset.3.html: bind_textdomain_codeset.3.in\n \n-install-html-local:\n-\t$(MKDIR_P) $(DESTDIR)$(htmldir)\n+install-html: installdirs-html\n \tfor file in $(man_HTML); do \\\n \t  if test -f $$file; then dir=.; else dir=$(srcdir); fi; \\\n \t  $(INSTALL_DATA) $$dir/$$file $(DESTDIR)$(htmldir)/$$file; \\\n--- a/gettext-tools/man/Makefile.am\n+++ b/gettext-tools/man/Makefile.am\n@@ -157,8 +157,7 @@ recode-sr-latin.1.html: recode-sr-latin.\n gettextize.1.html: gettextize.1\n autopoint.1.html: autopoint.1\n \n-install-html-local:\n-\t$(MKDIR_P) $(DESTDIR)$(htmldir)\n+install-html: installdirs-html\n \tfor file in $(man_HTML); do \\\n \t  if test -f $$file; then dir=.; else dir=$(srcdir); fi; \\\n \t  $(INSTALL_DATA) $$dir/$$file $(DESTDIR)$(htmldir)/$$file; \\\n"
  },
  {
    "path": "package/libs/gettext-full/patches/001-no_examples_and_tests.patch",
    "content": "--- a/gettext-runtime/Makefile.am\n+++ b/gettext-runtime/Makefile.am\n@@ -27,7 +27,7 @@ SUBDIR_libasprintf = libasprintf\n else\n SUBDIR_libasprintf =\n endif\n-SUBDIRS = doc intl intl-java intl-csharp gnulib-lib $(SUBDIR_libasprintf) src po man m4 tests\n+SUBDIRS = intl intl-java intl-csharp gnulib-lib $(SUBDIR_libasprintf) src po m4\n \n EXTRA_DIST = BUGS\n \n--- a/gettext-tools/Makefile.am\n+++ b/gettext-tools/Makefile.am\n@@ -19,7 +19,7 @@\n AUTOMAKE_OPTIONS = 1.5 gnu no-dependencies\n ACLOCAL_AMFLAGS = -I m4 -I ../gettext-runtime/m4 -I ../m4 -I gnulib-m4 -I libgrep/gnulib-m4 -I libgettextpo/gnulib-m4\n \n-SUBDIRS = intl gnulib-lib libgrep src libgettextpo po its projects styles emacs misc man m4 tests system-tests gnulib-tests examples doc\n+SUBDIRS = intl gnulib-lib libgrep src libgettextpo po its projects styles misc m4\n \n EXTRA_DIST = misc/DISCLAIM\n MOSTLYCLEANFILES = core *.stackdump\n"
  },
  {
    "path": "package/libs/gettext-full/patches/010-m4.patch",
    "content": "--- a/gettext-runtime/gnulib-m4/stddef_h.m4\n+++ b/gettext-runtime/gnulib-m4/stddef_h.m4\n@@ -8,7 +8,7 @@ dnl with or without modifications, as lo\n AC_DEFUN([gl_STDDEF_H],\n [\n   AC_REQUIRE([gl_STDDEF_H_DEFAULTS])\n-  AC_REQUIRE([gt_TYPE_WCHAR_T])\n+  AC_REQUIRE([gt_TYPE_WCHAR_T_GT])\n   STDDEF_H=\n \n   dnl Test whether the type max_align_t exists and whether its alignment\n--- a/gettext-runtime/gnulib-m4/stdint.m4\n+++ b/gettext-runtime/gnulib-m4/stdint.m4\n@@ -15,7 +15,7 @@ AC_DEFUN_ONCE([gl_STDINT_H],\n   AC_REQUIRE([AC_CANONICAL_HOST]) dnl for cross-compiles\n \n   AC_REQUIRE([gl_LIMITS_H])\n-  AC_REQUIRE([gt_TYPE_WINT_T])\n+  AC_REQUIRE([gt_TYPE_WINT_T_GT])\n \n   dnl For backward compatibility. Some packages may still be testing these\n   dnl macros.\n--- a/gettext-runtime/gnulib-m4/wchar_h.m4\n+++ b/gettext-runtime/gnulib-m4/wchar_h.m4\n@@ -27,7 +27,7 @@ AC_DEFUN([gl_WCHAR_H],\n \n   AC_REQUIRE([gl_FEATURES_H])\n \n-  AC_REQUIRE([gt_TYPE_WINT_T])\n+  AC_REQUIRE([gt_TYPE_WINT_T_GT])\n   if test $gt_cv_c_wint_t = yes; then\n     HAVE_WINT_T=1\n   else\n--- a/gettext-runtime/gnulib-m4/wchar_t.m4\n+++ b/gettext-runtime/gnulib-m4/wchar_t.m4\n@@ -8,7 +8,7 @@ dnl From Bruno Haible.\n dnl Test whether <stddef.h> has the 'wchar_t' type.\n dnl Prerequisite: AC_PROG_CC\n \n-AC_DEFUN([gt_TYPE_WCHAR_T],\n+AC_DEFUN([gt_TYPE_WCHAR_T_GT],\n [\n   AC_CACHE_CHECK([for wchar_t], [gt_cv_c_wchar_t],\n     [AC_COMPILE_IFELSE(\n--- a/gettext-runtime/gnulib-m4/wctype_h.m4\n+++ b/gettext-runtime/gnulib-m4/wctype_h.m4\n@@ -22,7 +22,7 @@ AC_DEFUN([gl_WCTYPE_H],\n   fi\n   AC_SUBST([HAVE_ISWCNTRL])\n \n-  AC_REQUIRE([gt_TYPE_WINT_T])\n+  AC_REQUIRE([gt_TYPE_WINT_T_GT])\n   if test $gt_cv_c_wint_t = yes; then\n     HAVE_WINT_T=1\n   else\n--- a/gettext-runtime/gnulib-m4/wcwidth.m4\n+++ b/gettext-runtime/gnulib-m4/wcwidth.m4\n@@ -12,8 +12,8 @@ AC_DEFUN([gl_FUNC_WCWIDTH],\n   dnl Persuade glibc <wchar.h> to declare wcwidth().\n   AC_REQUIRE([AC_USE_SYSTEM_EXTENSIONS])\n \n-  AC_REQUIRE([gt_TYPE_WCHAR_T])\n-  AC_REQUIRE([gt_TYPE_WINT_T])\n+  AC_REQUIRE([gt_TYPE_WCHAR_T_GT])\n+  AC_REQUIRE([gt_TYPE_WINT_T_GT])\n \n   AC_CHECK_HEADERS_ONCE([wchar.h])\n   AC_CHECK_FUNCS_ONCE([wcwidth])\n--- a/gettext-runtime/gnulib-m4/wint_t.m4\n+++ b/gettext-runtime/gnulib-m4/wint_t.m4\n@@ -9,7 +9,7 @@ dnl Test whether <wchar.h> has the 'wint\n dnl <wchar.h> or <wctype.h> would, if present, override 'wint_t'.\n dnl Prerequisite: AC_PROG_CC\n \n-AC_DEFUN([gt_TYPE_WINT_T],\n+AC_DEFUN([gt_TYPE_WINT_T_GT],\n [\n   AC_CACHE_CHECK([for wint_t], [gt_cv_c_wint_t],\n     [AC_COMPILE_IFELSE(\n--- a/gettext-runtime/intl/Makefile.am\n+++ b/gettext-runtime/intl/Makefile.am\n@@ -274,7 +274,7 @@ libgnuintl.h: $(srcdir)/libgnuintl.in.h\n \t    -e 's,@''HAVE_ASPRINTF''@,@HAVE_ASPRINTF@,g' \\\n \t    -e 's,@''HAVE_SNPRINTF''@,@HAVE_SNPRINTF@,g' \\\n \t    -e 's,@''HAVE_WPRINTF''@,@HAVE_WPRINTF@,g' \\\n-\t    -e 's,@''HAVE_NAMELESS_LOCALES''@,@HAVE_NAMELESS_LOCALES@,g' \\\n+\t    -e 's,@''HAVE_NAMELESS_LOCALES''@,0,g' \\\n \t    -e 's,@''HAVE_NEWLOCALE''@,@HAVE_NEWLOCALE@,g' \\\n \t  < $(srcdir)/libgnuintl.in.h \\\n \t| if test '@WOE32DLL@' = yes; then \\\n@@ -294,7 +294,7 @@ libintl.h: $(srcdir)/libgnuintl.in.h\n \t    -e 's,@''HAVE_ASPRINTF''@,@HAVE_ASPRINTF@,g' \\\n \t    -e 's,@''HAVE_SNPRINTF''@,@HAVE_SNPRINTF@,g' \\\n \t    -e 's,@''HAVE_WPRINTF''@,@HAVE_WPRINTF@,g' \\\n-\t    -e 's,@''HAVE_NAMELESS_LOCALES''@,@HAVE_NAMELESS_LOCALES@,g' \\\n+\t    -e 's,@''HAVE_NAMELESS_LOCALES''@,0,g' \\\n \t    -e 's,@''HAVE_NEWLOCALE''@,@HAVE_NEWLOCALE@,g' \\\n \t  < $(srcdir)/libgnuintl.in.h > libintl.h\n MOSTLYCLEANFILES += libintl.h\n--- a/gettext-runtime/libasprintf/configure.ac\n+++ b/gettext-runtime/libasprintf/configure.ac\n@@ -76,8 +76,8 @@ dnl Checks for typedefs, structures, and\n AC_C_INLINE\n AC_TYPE_SIZE_T\n AC_TYPE_LONG_LONG_INT\n-gt_TYPE_WCHAR_T\n-gt_TYPE_WINT_T\n+gt_TYPE_WCHAR_T_GT\n+gt_TYPE_WINT_T_GT\n AC_TYPE_MBSTATE_T\n AC_CHECK_TYPE([ptrdiff_t], ,\n   [AC_DEFINE([ptrdiff_t], [long],\n--- a/gettext-runtime/libasprintf/gnulib-m4/wchar_t.m4\n+++ b/gettext-runtime/libasprintf/gnulib-m4/wchar_t.m4\n@@ -8,7 +8,7 @@ dnl From Bruno Haible.\n dnl Test whether <stddef.h> has the 'wchar_t' type.\n dnl Prerequisite: AC_PROG_CC\n \n-AC_DEFUN([gt_TYPE_WCHAR_T],\n+AC_DEFUN([gt_TYPE_WCHAR_T_GT],\n [\n   AC_CACHE_CHECK([for wchar_t], [gt_cv_c_wchar_t],\n     [AC_COMPILE_IFELSE(\n--- a/gettext-runtime/libasprintf/gnulib-m4/wint_t.m4\n+++ b/gettext-runtime/libasprintf/gnulib-m4/wint_t.m4\n@@ -9,7 +9,7 @@ dnl Test whether <wchar.h> has the 'wint\n dnl <wchar.h> or <wctype.h> would, if present, override 'wint_t'.\n dnl Prerequisite: AC_PROG_CC\n \n-AC_DEFUN([gt_TYPE_WINT_T],\n+AC_DEFUN([gt_TYPE_WINT_T_GT],\n [\n   AC_CACHE_CHECK([for wint_t], [gt_cv_c_wint_t],\n     [AC_COMPILE_IFELSE(\n--- a/gettext-runtime/m4/intl.m4\n+++ b/gettext-runtime/m4/intl.m4\n@@ -31,8 +31,8 @@ AC_DEFUN([AM_INTL_SUBDIR],\n   AC_REQUIRE([gl_VISIBILITY])dnl\n   AC_REQUIRE([gt_INTL_SUBDIR_CORE])dnl\n   AC_REQUIRE([AC_TYPE_LONG_LONG_INT])dnl\n-  AC_REQUIRE([gt_TYPE_WCHAR_T])dnl\n-  AC_REQUIRE([gt_TYPE_WINT_T])dnl\n+  AC_REQUIRE([gt_TYPE_WCHAR_T_GT])dnl\n+  AC_REQUIRE([gt_TYPE_WINT_T_GT])dnl\n   AC_REQUIRE([gl_AC_HEADER_INTTYPES_H])\n   AC_REQUIRE([gt_TYPE_INTMAX_T])\n   AC_REQUIRE([gt_PRINTF_POSIX])\n--- a/gettext-tools/gnulib-m4/gnulib-comp.m4\n+++ b/gettext-tools/gnulib-m4/gnulib-comp.m4\n@@ -1843,8 +1843,8 @@ changequote([, ])dnl\n   AC_REQUIRE([gl_SOCKETS])\n   gl_TYPE_SOCKLEN_T\n   gl_STDALIGN_H\n-  AC_REQUIRE([gt_TYPE_WCHAR_T])\n-  AC_REQUIRE([gt_TYPE_WINT_T])\n+  AC_REQUIRE([gt_TYPE_WCHAR_T_GT])\n+  AC_REQUIRE([gt_TYPE_WINT_T_GT])\n   gl_FUNC_STRERROR_R\n   if test $HAVE_DECL_STRERROR_R = 0 || test $REPLACE_STRERROR_R = 1; then\n     AC_LIBOBJ([strerror_r])\n--- a/gettext-tools/gnulib-m4/stddef_h.m4\n+++ b/gettext-tools/gnulib-m4/stddef_h.m4\n@@ -8,7 +8,7 @@ dnl with or without modifications, as lo\n AC_DEFUN([gl_STDDEF_H],\n [\n   AC_REQUIRE([gl_STDDEF_H_DEFAULTS])\n-  AC_REQUIRE([gt_TYPE_WCHAR_T])\n+  AC_REQUIRE([gt_TYPE_WCHAR_T_GT])\n   STDDEF_H=\n \n   dnl Test whether the type max_align_t exists and whether its alignment\n--- a/gettext-tools/gnulib-m4/stdint.m4\n+++ b/gettext-tools/gnulib-m4/stdint.m4\n@@ -15,7 +15,7 @@ AC_DEFUN_ONCE([gl_STDINT_H],\n   AC_REQUIRE([AC_CANONICAL_HOST]) dnl for cross-compiles\n \n   AC_REQUIRE([gl_LIMITS_H])\n-  AC_REQUIRE([gt_TYPE_WINT_T])\n+  AC_REQUIRE([gt_TYPE_WINT_T_GT])\n \n   dnl For backward compatibility. Some packages may still be testing these\n   dnl macros.\n--- a/gettext-tools/gnulib-m4/vasnprintf.m4\n+++ b/gettext-tools/gnulib-m4/vasnprintf.m4\n@@ -32,16 +32,16 @@ AC_DEFUN([gl_REPLACE_VASNPRINTF],\n # Prerequisites of lib/printf-args.h, lib/printf-args.c.\n AC_DEFUN([gl_PREREQ_PRINTF_ARGS],\n [\n-  AC_REQUIRE([gt_TYPE_WCHAR_T])\n-  AC_REQUIRE([gt_TYPE_WINT_T])\n+  AC_REQUIRE([gt_TYPE_WCHAR_T_GT])\n+  AC_REQUIRE([gt_TYPE_WINT_T_GT])\n ])\n \n # Prerequisites of lib/printf-parse.h, lib/printf-parse.c.\n AC_DEFUN([gl_PREREQ_PRINTF_PARSE],\n [\n   AC_REQUIRE([gl_FEATURES_H])\n-  AC_REQUIRE([gt_TYPE_WCHAR_T])\n-  AC_REQUIRE([gt_TYPE_WINT_T])\n+  AC_REQUIRE([gt_TYPE_WCHAR_T_GT])\n+  AC_REQUIRE([gt_TYPE_WINT_T_GT])\n   AC_REQUIRE([AC_TYPE_SIZE_T])\n   AC_CHECK_TYPE([ptrdiff_t], ,\n     [AC_DEFINE([ptrdiff_t], [long],\n@@ -54,8 +54,8 @@ AC_DEFUN([gl_PREREQ_PRINTF_PARSE],\n AC_DEFUN_ONCE([gl_PREREQ_VASNPRINTF],\n [\n   AC_REQUIRE([AC_FUNC_ALLOCA])\n-  AC_REQUIRE([gt_TYPE_WCHAR_T])\n-  AC_REQUIRE([gt_TYPE_WINT_T])\n+  AC_REQUIRE([gt_TYPE_WCHAR_T_GT])\n+  AC_REQUIRE([gt_TYPE_WINT_T_GT])\n   AC_CHECK_FUNCS([snprintf strnlen wcslen wcsnlen mbrtowc wcrtomb])\n   dnl Use the _snprintf function only if it is declared (because on NetBSD it\n   dnl is defined as a weak alias of snprintf; we prefer to use the latter).\n--- a/gettext-tools/gnulib-m4/wchar_h.m4\n+++ b/gettext-tools/gnulib-m4/wchar_h.m4\n@@ -27,7 +27,7 @@ AC_DEFUN([gl_WCHAR_H],\n \n   AC_REQUIRE([gl_FEATURES_H])\n \n-  AC_REQUIRE([gt_TYPE_WINT_T])\n+  AC_REQUIRE([gt_TYPE_WINT_T_GT])\n   if test $gt_cv_c_wint_t = yes; then\n     HAVE_WINT_T=1\n   else\n--- a/gettext-tools/gnulib-m4/wchar_t.m4\n+++ b/gettext-tools/gnulib-m4/wchar_t.m4\n@@ -8,7 +8,7 @@ dnl From Bruno Haible.\n dnl Test whether <stddef.h> has the 'wchar_t' type.\n dnl Prerequisite: AC_PROG_CC\n \n-AC_DEFUN([gt_TYPE_WCHAR_T],\n+AC_DEFUN([gt_TYPE_WCHAR_T_GT],\n [\n   AC_CACHE_CHECK([for wchar_t], [gt_cv_c_wchar_t],\n     [AC_COMPILE_IFELSE(\n--- a/gettext-tools/gnulib-m4/wctype_h.m4\n+++ b/gettext-tools/gnulib-m4/wctype_h.m4\n@@ -22,7 +22,7 @@ AC_DEFUN([gl_WCTYPE_H],\n   fi\n   AC_SUBST([HAVE_ISWCNTRL])\n \n-  AC_REQUIRE([gt_TYPE_WINT_T])\n+  AC_REQUIRE([gt_TYPE_WINT_T_GT])\n   if test $gt_cv_c_wint_t = yes; then\n     HAVE_WINT_T=1\n   else\n--- a/gettext-tools/gnulib-m4/wcwidth.m4\n+++ b/gettext-tools/gnulib-m4/wcwidth.m4\n@@ -12,8 +12,8 @@ AC_DEFUN([gl_FUNC_WCWIDTH],\n   dnl Persuade glibc <wchar.h> to declare wcwidth().\n   AC_REQUIRE([AC_USE_SYSTEM_EXTENSIONS])\n \n-  AC_REQUIRE([gt_TYPE_WCHAR_T])\n-  AC_REQUIRE([gt_TYPE_WINT_T])\n+  AC_REQUIRE([gt_TYPE_WCHAR_T_GT])\n+  AC_REQUIRE([gt_TYPE_WINT_T_GT])\n \n   AC_CHECK_HEADERS_ONCE([wchar.h])\n   AC_CHECK_FUNCS_ONCE([wcwidth])\n--- a/gettext-tools/gnulib-m4/wint_t.m4\n+++ b/gettext-tools/gnulib-m4/wint_t.m4\n@@ -9,7 +9,7 @@ dnl Test whether <wchar.h> has the 'wint\n dnl <wchar.h> or <wctype.h> would, if present, override 'wint_t'.\n dnl Prerequisite: AC_PROG_CC\n \n-AC_DEFUN([gt_TYPE_WINT_T],\n+AC_DEFUN([gt_TYPE_WINT_T_GT],\n [\n   AC_CACHE_CHECK([for wint_t], [gt_cv_c_wint_t],\n     [AC_COMPILE_IFELSE(\n--- a/gettext-tools/intl/Makefile.am\n+++ b/gettext-tools/intl/Makefile.am\n@@ -274,7 +274,7 @@ libgnuintl.h: $(srcdir)/libgnuintl.in.h\n \t    -e 's,@''HAVE_ASPRINTF''@,@HAVE_ASPRINTF@,g' \\\n \t    -e 's,@''HAVE_SNPRINTF''@,@HAVE_SNPRINTF@,g' \\\n \t    -e 's,@''HAVE_WPRINTF''@,@HAVE_WPRINTF@,g' \\\n-\t    -e 's,@''HAVE_NAMELESS_LOCALES''@,@HAVE_NAMELESS_LOCALES@,g' \\\n+\t    -e 's,@''HAVE_NAMELESS_LOCALES''@,0,g' \\\n \t    -e 's,@''HAVE_NEWLOCALE''@,@HAVE_NEWLOCALE@,g' \\\n \t  < $(srcdir)/libgnuintl.in.h \\\n \t| if test '@WOE32DLL@' = yes; then \\\n@@ -294,7 +294,7 @@ libintl.h: $(srcdir)/libgnuintl.in.h\n \t    -e 's,@''HAVE_ASPRINTF''@,@HAVE_ASPRINTF@,g' \\\n \t    -e 's,@''HAVE_SNPRINTF''@,@HAVE_SNPRINTF@,g' \\\n \t    -e 's,@''HAVE_WPRINTF''@,@HAVE_WPRINTF@,g' \\\n-\t    -e 's,@''HAVE_NAMELESS_LOCALES''@,@HAVE_NAMELESS_LOCALES@,g' \\\n+\t    -e 's,@''HAVE_NAMELESS_LOCALES''@,0,g' \\\n \t    -e 's,@''HAVE_NEWLOCALE''@,@HAVE_NEWLOCALE@,g' \\\n \t  < $(srcdir)/libgnuintl.in.h > libintl.h\n MOSTLYCLEANFILES += libintl.h\n--- a/libtextstyle/gnulib-m4/stddef_h.m4\n+++ b/libtextstyle/gnulib-m4/stddef_h.m4\n@@ -8,7 +8,7 @@ dnl with or without modifications, as lo\n AC_DEFUN([gl_STDDEF_H],\n [\n   AC_REQUIRE([gl_STDDEF_H_DEFAULTS])\n-  AC_REQUIRE([gt_TYPE_WCHAR_T])\n+  AC_REQUIRE([gt_TYPE_WCHAR_T_GT])\n   STDDEF_H=\n \n   dnl Test whether the type max_align_t exists and whether its alignment\n--- a/libtextstyle/gnulib-m4/stdint.m4\n+++ b/libtextstyle/gnulib-m4/stdint.m4\n@@ -15,7 +15,7 @@ AC_DEFUN_ONCE([gl_STDINT_H],\n   AC_REQUIRE([AC_CANONICAL_HOST]) dnl for cross-compiles\n \n   AC_REQUIRE([gl_LIMITS_H])\n-  AC_REQUIRE([gt_TYPE_WINT_T])\n+  AC_REQUIRE([gt_TYPE_WINT_T_GT])\n \n   dnl For backward compatibility. Some packages may still be testing these\n   dnl macros.\n--- a/libtextstyle/gnulib-m4/vasnprintf.m4\n+++ b/libtextstyle/gnulib-m4/vasnprintf.m4\n@@ -32,16 +32,16 @@ AC_DEFUN([gl_REPLACE_VASNPRINTF],\n # Prerequisites of lib/printf-args.h, lib/printf-args.c.\n AC_DEFUN([gl_PREREQ_PRINTF_ARGS],\n [\n-  AC_REQUIRE([gt_TYPE_WCHAR_T])\n-  AC_REQUIRE([gt_TYPE_WINT_T])\n+  AC_REQUIRE([gt_TYPE_WCHAR_T_GT])\n+  AC_REQUIRE([gt_TYPE_WINT_T_GT])\n ])\n \n # Prerequisites of lib/printf-parse.h, lib/printf-parse.c.\n AC_DEFUN([gl_PREREQ_PRINTF_PARSE],\n [\n   AC_REQUIRE([gl_FEATURES_H])\n-  AC_REQUIRE([gt_TYPE_WCHAR_T])\n-  AC_REQUIRE([gt_TYPE_WINT_T])\n+  AC_REQUIRE([gt_TYPE_WCHAR_T_GT])\n+  AC_REQUIRE([gt_TYPE_WINT_T_GT])\n   AC_REQUIRE([AC_TYPE_SIZE_T])\n   AC_CHECK_TYPE([ptrdiff_t], ,\n     [AC_DEFINE([ptrdiff_t], [long],\n@@ -54,8 +54,8 @@ AC_DEFUN([gl_PREREQ_PRINTF_PARSE],\n AC_DEFUN_ONCE([gl_PREREQ_VASNPRINTF],\n [\n   AC_REQUIRE([AC_FUNC_ALLOCA])\n-  AC_REQUIRE([gt_TYPE_WCHAR_T])\n-  AC_REQUIRE([gt_TYPE_WINT_T])\n+  AC_REQUIRE([gt_TYPE_WCHAR_T_GT])\n+  AC_REQUIRE([gt_TYPE_WINT_T_GT])\n   AC_CHECK_FUNCS([snprintf strnlen wcslen wcsnlen mbrtowc wcrtomb])\n   dnl Use the _snprintf function only if it is declared (because on NetBSD it\n   dnl is defined as a weak alias of snprintf; we prefer to use the latter).\n--- a/libtextstyle/gnulib-m4/wchar_h.m4\n+++ b/libtextstyle/gnulib-m4/wchar_h.m4\n@@ -27,7 +27,7 @@ AC_DEFUN([gl_WCHAR_H],\n \n   AC_REQUIRE([gl_FEATURES_H])\n \n-  AC_REQUIRE([gt_TYPE_WINT_T])\n+  AC_REQUIRE([gt_TYPE_WINT_T_GT])\n   if test $gt_cv_c_wint_t = yes; then\n     HAVE_WINT_T=1\n   else\n--- a/libtextstyle/gnulib-m4/wchar_t.m4\n+++ b/libtextstyle/gnulib-m4/wchar_t.m4\n@@ -8,7 +8,7 @@ dnl From Bruno Haible.\n dnl Test whether <stddef.h> has the 'wchar_t' type.\n dnl Prerequisite: AC_PROG_CC\n \n-AC_DEFUN([gt_TYPE_WCHAR_T],\n+AC_DEFUN([gt_TYPE_WCHAR_T_GT],\n [\n   AC_CACHE_CHECK([for wchar_t], [gt_cv_c_wchar_t],\n     [AC_COMPILE_IFELSE(\n--- a/libtextstyle/gnulib-m4/wint_t.m4\n+++ b/libtextstyle/gnulib-m4/wint_t.m4\n@@ -9,7 +9,7 @@ dnl Test whether <wchar.h> has the 'wint\n dnl <wchar.h> or <wctype.h> would, if present, override 'wint_t'.\n dnl Prerequisite: AC_PROG_CC\n \n-AC_DEFUN([gt_TYPE_WINT_T],\n+AC_DEFUN([gt_TYPE_WINT_T_GT],\n [\n   AC_CACHE_CHECK([for wint_t], [gt_cv_c_wint_t],\n     [AC_COMPILE_IFELSE(\n"
  },
  {
    "path": "package/libs/gettext-full/patches/150-disable_libxml_iconv.patch",
    "content": "--- a/gettext-tools/gnulib-lib/libxml/xmlversion.in.h\n+++ b/gettext-tools/gnulib-lib/libxml/xmlversion.in.h\n@@ -302,7 +302,7 @@ XMLPUBFUN void XMLCALL xmlCheckVersion(i\n  *\n  * Whether iconv support is available\n  */\n-#if 1\n+#if 0\n #define LIBXML_ICONV_ENABLED\n #endif\n \n--- a/gnulib-local/lib/libxml/xmlversion.in.h\n+++ b/gnulib-local/lib/libxml/xmlversion.in.h\n@@ -302,7 +302,7 @@ XMLPUBFUN void XMLCALL xmlCheckVersion(i\n  *\n  * Whether iconv support is available\n  */\n-#if 1\n+#if 0\n #define LIBXML_ICONV_ENABLED\n #endif\n \n"
  },
  {
    "path": "package/libs/gmp/Makefile",
    "content": "#\n# Copyright (C) 2006-2016 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=gmp\nPKG_VERSION:=6.2.1\nPKG_RELEASE:=1\n\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION)$(PKG_REVISION).tar.xz\nPKG_SOURCE_URL:=@GNU/gmp/\nPKG_HASH:=fd4829912cddd12f84181c3451cc752be224643e87fac497b69edddadc49b4f2\n\nPKG_BUILD_PARALLEL:=1\nPKG_INSTALL:=1\nPKG_FIXUP:=autoreconf\nPKG_LICENSE:=GPL-2.0-or-later\n\nPKG_USE_MIPS16:=0\n\ninclude $(INCLUDE_DIR)/host-build.mk\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine Package/libgmp\n  SECTION:=libs\n  CATEGORY:=Libraries\n  TITLE:=GNU multiprecision arithmetic library\n  URL:=http://gmplib.org/\n  ABI_VERSION:=10\nendef\n\ndefine Package/libgmp/description\n\tGMP is a free library for arbitrary precision arithmetic, operating on\n\tsigned integers, rational numbers, and floating point numbers.\nendef\n\nTARGET_CFLAGS += $(FPIC)\nCONFIGURE_VARS += CC=\"$(TARGET_CROSS)gcc\"\nCONFIGURE_ARGS += \\\n\t--enable-shared \\\n\t--enable-static \\\n\t--without-readline \\\n\t--disable-fft \\\n\ndefine Build/Compile\n\t$(call Build/Compile/Default, \\\n\t\tDESTDIR=\"$(PKG_INSTALL_DIR)\" \\\n\t\tCC=\"$(TARGET_CC)\" \\\n\t\tall \\\n\t)\nendef\n\ndefine Build/InstallDev\n\t$(INSTALL_DIR) $(1)/usr/include\n\t$(CP) $(PKG_INSTALL_DIR)/usr/include/gmp* $(1)/usr/include/\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/libgmp.{a,so*} $(1)/usr/lib/\nendef\n\ndefine Package/libgmp/install\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/libgmp.so.* $(1)/usr/lib/\nendef\n\n$(eval $(call BuildPackage,libgmp))\n$(eval $(call HostBuild))\n"
  },
  {
    "path": "package/libs/jansson/Makefile",
    "content": "#\n# Copyright (C) 2011-2017 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=jansson\nPKG_VERSION:=2.13.1\nPKG_RELEASE:=2\nPKG_LICENSE:=MIT\nPKG_LICENSE_FILES:=LICENSE\n\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.bz2\nPKG_SOURCE_URL:=http://www.digip.org/jansson/releases/\nPKG_HASH:=ee90a0f879d2b7b7159124ff22b937a2a9a8c36d3bb65d1da7dd3f04370a10bd\n\ninclude $(INCLUDE_DIR)/package.mk\ninclude $(INCLUDE_DIR)/cmake.mk\n\nCMAKE_INSTALL:=1\nCMAKE_OPTIONS += \\\n\t-DJANSSON_BUILD_DOCS:BOOL=OFF \\\n\t-DJANSSON_BUILD_SHARED_LIBS:BOOL=ON \\\n\t-DJANSSON_EXAMPLES:BOOL=OFF \\\n\t-DJANSSON_WITHOUT_TESTS:BOOL=ON\n\ndefine Package/jansson\n  SECTION:=libs\n  CATEGORY:=Libraries\n  TITLE:=Jansson library\n  URL:=http://www.digip.org/jansson/\n  ABI_VERSION:=4\nendef\n\ndefine Package/jansson/description\n  Jansson is a C library for encoding, decoding and manipulating JSON data\nendef\n\nTARGET_CFLAGS += -flto\nTARGET_LDFLAGS += -flto\n\ndefine Package/jansson/install\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/libjansson*so* $(1)/usr/lib/\nendef\n\n$(eval $(call BuildPackage,jansson))\n"
  },
  {
    "path": "package/libs/libaudit/Makefile",
    "content": "#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=libaudit\nPKG_VERSION:=2.8.5\nPKG_RELEASE:=1\n\nPKG_SOURCE_NAME:=audit\nPKG_SOURCE:=$(PKG_SOURCE_NAME)-$(PKG_VERSION).tar.gz\nPKG_SOURCE_URL:=http://people.redhat.com/sgrubb/audit\nPKG_HASH:=0e5d4103646e00f8d1981e1cd2faea7a2ae28e854c31a803e907a383c5e2ecb7\nPKG_BUILD_DIR:=$(BUILD_DIR)/$(PKG_SOURCE_NAME)-$(PKG_VERSION)\nHOST_BUILD_DIR:=$(BUILD_DIR_HOST)/$(PKG_SOURCE_NAME)-$(PKG_VERSION)\nPKG_MAINTAINER:=Thomas Petazzoni <thomas.petazzoni@bootlin.com>\nPKG_LICENSE:=GPL-2.0\nPKG_LICENSE_FILES:=COPYING\nPKG_CPE_ID:=cpe:/a:linux_audit_project:linux_audit\n\nPKG_FIXUP:=autoreconf\n\nPKG_USE_MIPS16:=0\nPKG_INSTALL:=1\n\ninclude $(INCLUDE_DIR)/package.mk\ninclude $(INCLUDE_DIR)/host-build.mk\n\ndefine Package/libaudit\n  CATEGORY:=Libraries\n  TITLE:=Linux Auditing Framework (shared library)\n  URL:=http://people.redhat.com/sgrubb/audit/\nendef\n\ndefine Package/libaudit/description\n\tThis package contains the audit shared library.\nendef\n\nCONFIGURE_VARS += \\\n\tLDFLAGS_FOR_BUILD=\"$(HOST_LDFLAGS)\" \\\n\tCPPFLAGS_FOR_BUILD=\"$(HOST_CPPFLAGS)\" \\\n\tCFLAGS_FOR_BUILD=\"$(HOST_CFLAGS)\" \\\n\tCC_FOR_BUILD=\"$(HOSTCC)\"\n\nCONFIGURE_ARGS += \\\n\t--without-libcap-ng \\\n\t--disable-systemd \\\n\t--without-python \\\n\t--without-python3 \\\n\t--disable-zos-remote\n\nifeq ($(ARCH),aarch64)\nCONFIGURE_ARGS += --with-aarch64\nelse ifeq ($(ARCH),arm)\nCONFIGURE_ARGS += --with-arm\nendif\n\nHOST_CONFIGURE_ARGS += \\\n\t--without-libcap-ng \\\n\t--disable-systemd \\\n\t--without-python \\\n\t--without-python3 \\\n\t--disable-zos-remote\n\nMAKE_PATH:=lib\n\n# Host/Compile/default doesn't include $(MAKE_PATH), override to use,\n# so we avoid building and installing unnecessary parts on the host.\ndefine Host/Compile\n\t+$(HOST_MAKE_VARS) $(MAKE) $(HOST_JOBS) -C $(HOST_BUILD_DIR)/$(MAKE_PATH) $(HOST_MAKE_FLAGS) all\nendef\n\ndefine Host/Install\n\t+$(HOST_MAKE_VARS) $(MAKE) $(HOST_JOBS) -C $(HOST_BUILD_DIR)/lib $(HOST_MAKE_FLAGS) install\n\t+$(HOST_MAKE_VARS) $(MAKE) $(HOST_JOBS) -C $(HOST_BUILD_DIR)/init.d $(HOST_MAKE_FLAGS) install\nendef\n\n# We can't use the default, as the default passes $(MAKE_ARGS), which\n# overrides CC, CFLAGS, etc. and defeats the *_FOR_BUILD definitions\n# passed in CONFIGURE_VARS\ndefine Build/Compile\n\t$(MAKE) $(PKG_JOBS) -C $(PKG_BUILD_DIR)/$(MAKE_PATH)\nendef\n\ndefine Build/Install\n\t$(MAKE) $(PKG_JOBS) -C $(PKG_BUILD_DIR)/lib $(MAKE_INSTALL_FLAGS) install\n\t$(MAKE) $(PKG_JOBS) -C $(PKG_BUILD_DIR)/init.d $(MAKE_INSTALL_FLAGS) install\nendef\n\ndefine Build/InstallDev\n\t$(INSTALL_DIR) $(1)/usr/include\n\t$(CP) $(PKG_INSTALL_DIR)/usr/include/* $(1)/usr/include/\n\t$(INSTALL_DIR) $(1)/usr/lib/pkgconfig\n\t$(INSTALL_DATA) $(PKG_INSTALL_DIR)/usr/lib/pkgconfig/*.pc $(1)/usr/lib/pkgconfig/\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/* $(1)/usr/lib/\nendef\n\ndefine Package/libaudit/install\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/*.so.* $(1)/usr/lib/\n\t$(INSTALL_DIR) $(1)/etc\n\t$(CP) $(PKG_INSTALL_DIR)/etc/libaudit.conf $(1)/etc/\nendef\n\n$(eval $(call HostBuild))\n$(eval $(call BuildPackage,libaudit))\n"
  },
  {
    "path": "package/libs/libaudit/patches/0001-Add-substitue-functions-for-strndupa-rawmemchr.patch",
    "content": "From c39a071e7c021f6ff3554aca2758e97b47a9777c Mon Sep 17 00:00:00 2001\nFrom: Steve Grubb <sgrubb@redhat.com>\nDate: Tue, 26 Feb 2019 18:33:33 -0500\nSubject: [PATCH] Add substitue functions for strndupa & rawmemchr\n\n(cherry picked from commit d579a08bb1cde71f939c13ac6b2261052ae9f77e)\nSigned-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>\n---\n auparse/auparse.c   | 12 +++++++++++-\n auparse/interpret.c |  9 ++++++++-\n configure.ac        | 14 +++++++++++++-\n src/ausearch-lol.c  | 12 +++++++++++-\n 4 files changed, 43 insertions(+), 4 deletions(-)\n\ndiff --git a/auparse/auparse.c b/auparse/auparse.c\nindex 650db02..2e1c737 100644\n--- a/auparse/auparse.c\n+++ b/auparse/auparse.c\n@@ -1,5 +1,5 @@\n /* auparse.c --\n- * Copyright 2006-08,2012-17 Red Hat Inc., Durham, North Carolina.\n+ * Copyright 2006-08,2012-19 Red Hat Inc., Durham, North Carolina.\n  * All Rights Reserved.\n  *\n  * This library is free software; you can redistribute it and/or\n@@ -1118,6 +1118,16 @@ static int str2event(char *s, au_event_t *e)\n \treturn 0;\n }\n \n+#ifndef HAVE_STRNDUPA\n+static inline char *strndupa(const char *old, size_t n)\n+{\n+\tsize_t len = strnlen(old, n);\n+\tchar *tmp = alloca(len + 1);\n+\ttmp[len] = 0;\n+\treturn memcpy(tmp, old, len);\n+}\n+#endif\n+\n /* Returns 0 on success and 1 on error */\n static int extract_timestamp(const char *b, au_event_t *e)\n {\ndiff --git a/auparse/interpret.c b/auparse/interpret.c\nindex 51c4a5e..67b7b77 100644\n--- a/auparse/interpret.c\n+++ b/auparse/interpret.c\n@@ -853,6 +853,13 @@ err_out:\n \t\treturn print_escaped(id->val);\n }\n \n+// rawmemchr is faster. Let's use it if we have it.\n+#ifdef HAVE_RAWMEMCHR\n+#define STRCHR rawmemchr\n+#else\n+#define STRCHR strchr\n+#endif\n+\n static const char *print_proctitle(const char *val)\n {\n \tchar *out = (char *)print_escaped(val);\n@@ -863,7 +870,7 @@ static const char *print_proctitle(const char *val)\n \t\t// Proctitle has arguments separated by NUL bytes\n \t\t// We need to write over the NUL bytes with a space\n \t\t// so that we can see the arguments\n-\t\twhile ((ptr  = rawmemchr(ptr, '\\0'))) {\n+\t\twhile ((ptr  = STRCHR(ptr, '\\0'))) {\n \t\t\tif (ptr >= end)\n \t\t\t\tbreak;\n \t\t\t*ptr = ' ';\ndiff --git a/configure.ac b/configure.ac\nindex 6e345f1..6f3007e 100644\n--- a/configure.ac\n+++ b/configure.ac\n@@ -1,7 +1,7 @@\n dnl\n define([AC_INIT_NOTICE],\n [### Generated automatically using autoconf version] AC_ACVERSION [\n-### Copyright 2005-18 Steve Grubb <sgrubb@redhat.com>\n+### Copyright 2005-19 Steve Grubb <sgrubb@redhat.com>\n ###\n ### Permission is hereby granted, free of charge, to any person obtaining a\n ### copy of this software and associated documentation files (the \"Software\"),\n@@ -72,6 +72,18 @@ dnl; posix_fallocate is used in audisp-remote\n AC_CHECK_FUNCS([posix_fallocate])\n dnl; signalfd is needed for libev\n AC_CHECK_FUNC([signalfd], [], [ AC_MSG_ERROR([The signalfd system call is necessary for auditd]) ])\n+dnl; check if rawmemchr is available\n+AC_CHECK_FUNCS([rawmemchr])\n+dnl; check if strndupa is available\n+AC_LINK_IFELSE(\n+  [AC_LANG_SOURCE(\n+    [[\n+      #define _GNU_SOURCE\n+      #include <string.h>\n+      int main() { (void) strndupa(\"test\", 10); return 0; }]])],\n+ [AC_DEFINE(HAVE_STRNDUPA, 1, [Let us know if we have it or not])],\n+ []\n+)\n \n ALLWARNS=\"\"\n ALLDEBUG=\"-g\"\ndiff --git a/src/ausearch-lol.c b/src/ausearch-lol.c\nindex 5d17a72..758c33e 100644\n--- a/src/ausearch-lol.c\n+++ b/src/ausearch-lol.c\n@@ -1,6 +1,6 @@\n /*\n * ausearch-lol.c - linked list of linked lists library\n-* Copyright (c) 2008,2010,2014,2016 Red Hat Inc., Durham, North Carolina.\n+* Copyright (c) 2008,2010,2014,2016,2019 Red Hat Inc., Durham, North Carolina.\n * All Rights Reserved. \n *\n * This software may be freely redistributed and/or modified under the\n@@ -152,6 +152,16 @@ static int compare_event_time(event *e1, event *e2)\n \treturn 0;\n }\n \n+#ifndef HAVE_STRNDUPA\n+static inline char *strndupa(const char *old, size_t n)\n+{\n+\tsize_t len = strnlen(old, n);\n+\tchar *tmp = alloca(len + 1);\n+\ttmp[len] = 0;\n+\treturn memcpy(tmp, old, len);\n+}\n+#endif\n+\n /*\n  * This function will look at the line and pick out pieces of it.\n  */\n-- \n2.21.0\n\n"
  },
  {
    "path": "package/libs/libaudit/patches/0002-fix-gcc-10.patch",
    "content": "From 017e6c6ab95df55f34e339d2139def83e5dada1f Mon Sep 17 00:00:00 2001\nFrom: Steve Grubb <sgrubb@redhat.com>\nDate: Fri, 10 Jan 2020 21:13:50 -0500\nSubject: [PATCH 01/30] Header definitions need to be external when building\n with -fno-common (which is default in GCC 10) - Tony Jones\n\n---\n src/ausearch-common.h | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\ndiff --git a/src/ausearch-common.h b/src/ausearch-common.h\nindex 6669203..3040547 100644\n--- a/src/ausearch-common.h\n+++ b/src/ausearch-common.h\n@@ -50,7 +50,7 @@ extern pid_t event_pid;\n extern int event_exact_match;\n extern uid_t event_uid, event_euid, event_loginuid;\n extern const char *event_tuid, *event_teuid, *event_tauid;\n-slist *event_node_list;\n+extern slist *event_node_list;\n extern const char *event_comm;\n extern const char *event_filename;\n extern const char *event_hostname;\n-- \n2.26.2\n\n"
  },
  {
    "path": "package/libs/libbsd/Makefile",
    "content": "include $(TOPDIR)/rules.mk\n\nPKG_NAME:=libbsd\nPKG_VERSION:=0.10.0\nPKG_RELEASE:=1\n\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz\nPKG_SOURCE_URL:=https://libbsd.freedesktop.org/releases\nPKG_HASH:=34b8adc726883d0e85b3118fa13605e179a62b31ba51f676136ecb2d0bc1a887\n\nPKG_LICENSE:=BSD-4-Clause\nPKG_LICENSE_FILES:=COPYING\n\nPKG_INSTALL:=1\nPKG_BUILD_PARALLEL:=1\n\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine Package/libbsd\n  SECTION:=libs\n  CATEGORY:=Libraries\n  TITLE:=common BSD library\n  ABI_VERSION:=0\nendef\n\ndefine Package/libbsd/description\n This library provides useful functions commonly found on BSD systems, and lacking on others like GNU systems, thus making it easier to port projects with strong BSD origins, without needing to embed the same code over and over again on each project.\nendef\n\ndefine Build/InstallDev\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(INSTALL_DIR) $(1)/usr/lib/pkgconfig\n\t$(INSTALL_DIR) $(1)/usr/include\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/libbsd.{la,so*} $(1)/usr/lib/\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/pkgconfig/libbsd*.pc $(1)/usr/lib/pkgconfig/\n\t$(CP) $(PKG_INSTALL_DIR)/usr/include/* $(1)/usr/include/\nendef\n\ndefine Package/libbsd/install\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/libbsd.so.* $(1)/usr/lib/\nendef\n\n$(eval $(call BuildPackage,libbsd))\n\n"
  },
  {
    "path": "package/libs/libcap/Makefile",
    "content": "#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=libcap\nPKG_VERSION:=2.63\nPKG_RELEASE:=$(AUTORELEASE)\n\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz\nPKG_SOURCE_URL:=@KERNEL/linux/libs/security/linux-privs/libcap2\nPKG_HASH:=0c637b8f44fc7d8627787e9cf57f15ac06c1ddccb53e41feec5496be3466f77f\n\nPKG_MAINTAINER:=Paul Wassi <p.wassi@gmx.at>\nPKG_LICENSE:=GPL-2.0-only\nPKG_LICENSE_FILES:=License\n\nPKG_INSTALL:=1\nPKG_BUILD_PARALLEL:=1\n\ninclude $(INCLUDE_DIR)/package.mk\ninclude $(INCLUDE_DIR)/kernel.mk\n\ndefine Package/libcap/Default\n  TITLE:=Linux capabilities library\n  SECTION:=libs\n  CATEGORY:=Libraries\n  URL:=https://www.kernel.org/pub/linux/libs/security/linux-privs/libcap2/\nendef\n\ndefine Package/libcap/description/Default\n  Linux capabilities\nendef\n\ndefine Package/libcap\n  $(call Package/libcap/Default)\n  TITLE += library\nendef\n\ndefine Package/libcap-bin\n  $(call Package/libcap/Default)\n  TITLE += binaries\n  DEPENDS += libcap\nendef\n\ndefine Package/libcap-bin/description\n  $(call Package/libcap/description/Default)\n  .\n  This package contains the libcap utilities.\nendef\n\ndefine Package/libcap-bin/config\n  if PACKAGE_libcap-bin\n  config PACKAGE_libcap-bin-capsh-shell\n    string \"capsh shell\"\n    help\n      Set the capsh shell.\n    default \"/bin/sh\"\n  endif\nendef\n\nMAKE_FLAGS += \\\n    BUILD_CC=\"$(CC)\" \\\n    BUILD_CFLAGS=\"$(FPIC) -I$(PKG_BUILD_DIR)/libcap/include\" \\\n    CFLAGS=\"$(TARGET_CFLAGS)\" \\\n    LD=\"$(TARGET_CC) -Wl,-x -shared\" \\\n    LDFLAGS=\"$(TARGET_LDFLAGS)\" \\\n    INDENT=\"| true\" \\\n    GOLANG=\"no\" \\\n    PAM_CAP=\"no\" \\\n    RAISE_SETFCAP=\"no\" \\\n    DYNAMIC=\"yes\" \\\n    lib=\"lib\"\n\nTARGET_CFLAGS += $(FPIC)\n\nifneq ($(CONFIG_PACKAGE_libcap-bin-capsh-shell),)\nTARGET_CFLAGS += -DSHELL='\\\"$(CONFIG_PACKAGE_libcap-bin-capsh-shell)\\\"'\nendif\n\nTARGET_CFLAGS += $(if $(CONFIG_USE_MUSL),-Dpthread_yield=sched_yield)\n\ndefine Build/InstallDev\n\t$(INSTALL_DIR) $(1)/usr/include/sys\n\t$(CP) $(PKG_INSTALL_DIR)/usr/include/sys/*.h $(1)/usr/include/sys/\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(CP) $(PKG_INSTALL_DIR)/lib/libcap.{so*,a} $(1)/usr/lib/\n\t$(INSTALL_DATA) $(PKG_INSTALL_DIR)/lib/libpsx.a $(1)/usr/lib/\n\t$(INSTALL_DIR) $(1)/usr/lib/pkgconfig\n\t$(INSTALL_DATA) $(PKG_INSTALL_DIR)/lib/pkgconfig/libcap.pc $(1)/usr/lib/pkgconfig/\n\t$(SED) 's,exec_prefix=,exec_prefix=/usr,g' $(1)/usr/lib/pkgconfig/libcap.pc\n\t$(SED) 's,/lib,$$$${exec_prefix}/lib,g' $(1)/usr/lib/pkgconfig/libcap.pc\n\t$(SED) 's,/usr/include,$$$${prefix}/include,g' $(1)/usr/lib/pkgconfig/libcap.pc\n\t$(INSTALL_DATA) $(PKG_INSTALL_DIR)/lib/pkgconfig/libpsx.pc $(1)/usr/lib/pkgconfig/\n\t$(SED) 's,exec_prefix=,exec_prefix=/usr,g' $(1)/usr/lib/pkgconfig/libpsx.pc\n\t$(SED) 's,/lib,$$$${exec_prefix}/lib,g' $(1)/usr/lib/pkgconfig/libpsx.pc\n\t$(SED) 's,/usr/include,$$$${prefix}/include,g' $(1)/usr/lib/pkgconfig/libpsx.pc\nendef\n\ndefine Package/libcap/install\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(CP) $(PKG_INSTALL_DIR)/lib/libcap.so* $(1)/usr/lib/\nendef\n\ndefine Package/libcap-bin/install\n\t$(INSTALL_DIR) $(1)/usr/sbin\n\t$(CP) $(PKG_INSTALL_DIR)/sbin/capsh     $(1)/usr/sbin/\n\t$(CP) $(PKG_INSTALL_DIR)/sbin/getcap    $(1)/usr/sbin/\n\t$(CP) $(PKG_INSTALL_DIR)/sbin/getpcaps  $(1)/usr/sbin/\n\t$(CP) $(PKG_INSTALL_DIR)/sbin/setcap    $(1)/usr/sbin/\nendef\n\n$(eval $(call BuildPackage,libcap))\n$(eval $(call BuildPackage,libcap-bin))\n"
  },
  {
    "path": "package/libs/libcap/patches/300-disable-tests.patch",
    "content": "--- a/Makefile\n+++ b/Makefile\n@@ -17,7 +17,6 @@ ifeq ($(GOLANG),yes)\n \t$(MAKE) -C go $@\n \trm -f cap/go.sum\n endif\n-\t$(MAKE) -C tests $@\n \t$(MAKE) -C progs $@\n \t$(MAKE) -C doc $@\n \n"
  },
  {
    "path": "package/libs/libevent2/Makefile",
    "content": "#\n# Copyright (C) 2011-2015 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=libevent2\nPKG_VERSION:=2.1.12\nPKG_RELEASE:=1\n\nPKG_SOURCE:=libevent-$(PKG_VERSION)-stable.tar.gz\nPKG_SOURCE_URL:=https://github.com/libevent/libevent/releases/download/release-$(PKG_VERSION)-stable\nPKG_HASH:=92e6de1be9ec176428fd2367677e61ceffc2ee1cb119035037a27d346b0403bb\nPKG_BUILD_DIR:=$(BUILD_DIR)/libevent-$(PKG_VERSION)-stable\n\nPKG_MAINTAINER:=Jo-Philipp Wich <jo@mein.io>\nPKG_LICENSE:=BSD-3-Clause\nPKG_LICENSE_FILES:=LICENSE\nPKG_CPE_ID:=cpe:/a:libevent_project:libevent\n\nPKG_CONFIG_DEPENDS:= \\\n\tCONFIG_PACKAGE_libevent2-openssl \\\n\tCONFIG_PACKAGE_libevent2-pthreads \\\n\tCONFIG_PACKAGE_libevent2-mbedtls\n\ninclude $(INCLUDE_DIR)/package.mk\ninclude $(INCLUDE_DIR)/cmake.mk\n\ndefine Package/libevent2/Default\n  SECTION:=libs\n  CATEGORY:=Libraries\n  TITLE:=Event notification\n  URL:=http://libevent.org\n  ABI_VERSION:=7\nendef\n\ndefine Package/libevent2/Default/description\n\tThe libevent API provides a mechanism to execute a callback function\n\twhen a specific event occurs on a file descriptor or after a timeout\n\thas been reached. Furthermore, libevent also support callbacks due\n\tto signals or regular timeouts.\n\n\tlibevent is meant to replace the event loop found in event driven\n\tnetwork servers. An application just needs to call event_dispatch()\n\tand then add or remove events dynamically without having to change\n\tthe event loop.\nendef\n\ndefine Package/libevent2\n  $(call Package/libevent2/Default)\n  TITLE+= library (version 2.1)\nendef\n\ndefine Package/libevent2/description\n\t$(call Package/libevent2/Default/description)\n\n\tThis package contains the libevent shared library historically\n\tcontaining both the core & extra libraries.\nendef\n\ndefine Package/libevent2-core\n  $(call Package/libevent2/Default)\n  TITLE+= core library (version 2.1)\nendef\n\ndefine Package/libevent2-core/description\n\t$(call Package/libevent2/Default/description)\n\n\tThis package contains the libevent core shared library for the event,\n\tbuffer & utility functions.\nendef\n\ndefine Package/libevent2-extra\n  $(call Package/libevent2/Default)\n  TITLE+= extra library (version 2.1)\n  DEPENDS+=+libevent2-core\nendef\n\ndefine Package/libevent2-extra/description\n\t$(call Package/libevent2/Default/description)\n\n\tThis package contains the libevent extra shared library for specific\n\tprotocols including HTTP, DNS & RPC.\nendef\n\ndefine Package/libevent2-openssl\n  $(call Package/libevent2/Default)\n  TITLE+= OpenSSL library (version 2.1)\n  DEPENDS+=+libopenssl +libevent2-core\nendef\n\ndefine Package/libevent2-openssl/description\n\t$(call Package/libevent2/Default/description)\n\n\tThis package contains the libevent OpenSSL shared library for encrypted\n\tbufferevents.\nendef\n\ndefine Package/libevent2-pthreads\n  $(call Package/libevent2/Default)\n  TITLE+= Pthreads library (version 2.1)\n  DEPENDS+=+libpthread +libevent2-core\nendef\n\ndefine Package/libevent2-pthreads/description\n\t$(call Package/libevent2/Default/description)\n\n\tThis package contains the libevent Pthreads shared library for\n\tthreading & locking.\nendef\n\nTARGET_CFLAGS += $(FPIC) -ffunction-sections -fdata-sections -flto\nTARGET_LDFLAGS += -Wl,--gc-sections,--as-needed -flto\n\nCMAKE_OPTIONS += \\\n\t-DEVENT__DISABLE_BENCHMARK:BOOL=ON \\\n\t-DEVENT__DISABLE_DEBUG_MODE:BOOL=ON \\\n\t-DEVENT__DISABLE_REGRESS:BOOL=ON \\\n\t-DEVENT__DISABLE_SAMPLES:BOOL=ON \\\n\t$(if $(CONFIG_PACKAGE_libevent2-openssl),-DEVENT__DISABLE_OPENSSL:BOOL=OFF,-DEVENT__DISABLE_OPENSSL:BOOL=ON) \\\n\t$(if $(CONFIG_PACKAGE_libevent2-pthreads),-DEVENT__DISABLE_THREAD_SUPPORT:BOOL=OFF,-DEVENT__DISABLE_THREAD_SUPPORT:BOOL=ON) \\\n\t-DEVENT__DISABLE_TESTS:BOOL=ON \\\n\t-DBUILD_TESTING:BOOL=OFF\n\ndefine Build/InstallDev\n\t$(call Build/InstallDev/cmake,$(1))\n\t$(SED) 's,/usr/include,$$$${prefix}/include,g' $(1)/usr/lib/pkgconfig/libevent*.pc\n\t$(SED) 's,/usr/lib,$$$${exec_prefix}/lib,g' $(1)/usr/lib/pkgconfig/libevent*.pc\nendef\n\ndefine Package/libevent2/install\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/libevent-2.1.so.* $(1)/usr/lib/\nendef\n\ndefine Package/libevent2-core/install\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/libevent_core-2.1.so.* $(1)/usr/lib/\nendef\n\ndefine Package/libevent2-extra/install\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/libevent_extra-2.1.so.* $(1)/usr/lib/\nendef\n\ndefine Package/libevent2-openssl/install\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/libevent_openssl-2.1.so.* $(1)/usr/lib/\nendef\n\ndefine Package/libevent2-pthreads/install\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/libevent_pthreads-2.1.so.* $(1)/usr/lib/\nendef\n\n$(eval $(call BuildPackage,libevent2))\n$(eval $(call BuildPackage,libevent2-core))\n$(eval $(call BuildPackage,libevent2-extra))\n$(eval $(call BuildPackage,libevent2-openssl))\n$(eval $(call BuildPackage,libevent2-pthreads))\n"
  },
  {
    "path": "package/libs/libiconv/COPYING",
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You can do so by permitting\nredistribution under these terms (or, alternatively, under the terms of the\nordinary General Public License).\n\n  To apply these terms, attach the following notices to the library.  It is\nsafest to attach them to the start of each source file to most effectively\nconvey the exclusion of warranty; and each file should have at least the\n\"copyright\" line and a pointer to where the full notice is found.\n\n    <one line to give the library's name and a brief idea of what it does.>\n    Copyright (C) <year>  <name of author>\n\n    This library is free software; you can redistribute it and/or\n    modify it under the terms of the GNU Lesser General Public\n    License as published by the Free Software Foundation; either\n    version 2 of the License, or (at your option) any later version.\n\n    This library is distributed in the hope that it will be useful,\n    but WITHOUT ANY WARRANTY; without even the implied warranty of\n    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\n    Lesser General Public License for more details.\n\n    You should have received a copy of the GNU Lesser General Public\n    License along with this library; if not, write to the Free Software\n    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA\n\nAlso add information on how to contact you by electronic and paper mail.\n\nYou should also get your employer (if you work as a programmer) or your\nschool, if any, to sign a \"copyright disclaimer\" for the library, if\nnecessary.  Here is a sample; alter the names:\n\n  Yoyodyne, Inc., hereby disclaims all copyright interest in the\n  library `Frob' (a library for tweaking knobs) written by James Random Hacker.\n\n  <signature of Ty Coon>, 1 April 1990\n  Ty Coon, President of Vice\n\nThat's all there is to it!\n\n\n"
  },
  {
    "path": "package/libs/libiconv/COPYRIGHT",
    "content": "Copyright status on all included code:\n\nAll files which have no copyright comments are original works\nCopyright (C) 2005-2006 Rich Felker. The decision to exclude such\ncomments is intentional, as it should be possible to carry around the\ncomplete source code on tiny storage media. All public header files\n(include/*) should be treated as Public Domain as they intentionally\ncontain no content which can be covered by copyright. Some source\nmodules may fall in this category as well. If you believe that a file\nis so trivial that it should be in the Public Domain, please contact\nme and, if I agree, I will explicitly release it from copyright.\n\nSome code has been modified by the OpenWrt project, this includes\nthe conversion from char map files to C arrays and the iconv.h header\nfile in particular.\n\nThe library as a whole is licensed under the GNU LGPL version 2.1.\nSee the file COPYING for the text of this license.\n\nThe original source can be accessed at svn://svn.mplayerhq.hu/libc/trunk\n"
  },
  {
    "path": "package/libs/libiconv/Makefile",
    "content": "#\n# Copyright (C) 2010-2012 OpenWrt.org\n#\n# This Makefile and the code shipped in src/ is free software, licensed\n# under the GNU Lesser General Public License, version 2.1 and later.\n# See src/COPYING for more information.\n#\n# Refer to src/COPYRIGHT for copyright statements on the source files.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=libiconv\nPKG_RELEASE:=8\n\nPKG_LICENSE:=LGPL-2.1\nPKG_LICENSE_FILES:=LICENSE\n\nPKG_MAINTAINER:=Jo-Philipp Wich <jo@mein.io>\n\ninclude $(INCLUDE_DIR)/package.mk\ninclude $(INCLUDE_DIR)/host-build.mk\n\ndefine Package/libiconv\n  SECTION:=libs\n  CATEGORY:=Libraries\n  TITLE:=Tiny drop-in replacement for the GNU Character set conversion library\nendef\n\ndefine Build/Configure\nendef\n\ndefine Build/Compile\n\t$(TARGET_CC) $(TARGET_CFLAGS) -c $(PKG_BUILD_DIR)/iconv.c -o $(PKG_BUILD_DIR)/iconv.o -I$(PKG_BUILD_DIR)/include $(FPIC)\n\t$(TARGET_CROSS)ar rcs $(PKG_BUILD_DIR)/libiconv.a $(PKG_BUILD_DIR)/iconv.o\nendef\n\ndefine Build/InstallDev\n\t$(INSTALL_DIR) $(1)/usr/lib/libiconv-stub/lib\n\t$(INSTALL_DATA) $(PKG_BUILD_DIR)/libiconv.a $(1)/usr/lib/libiconv-stub/lib/\n\n\t$(INSTALL_DIR) $(1)/usr/lib/libiconv-stub/include\n\t$(INSTALL_DATA) $(PKG_BUILD_DIR)/include/iconv.h $(1)/usr/lib/libiconv-stub/include/\n\n\t$(INSTALL_DIR) $(1)/usr/share/aclocal\n\t$(INSTALL_DATA) $(PKG_BUILD_DIR)/m4/* $(1)/usr/share/aclocal/\nendef\n\ndefine Package/libiconv/install\n\t$(INSTALL_DIR) $(1)/tmp\n\ttouch $(1)/tmp/.libiconv-placeholder\nendef\n\ndefine Host/Prepare\n\tmkdir -p $(HOST_BUILD_DIR)\nendef\n\ndefine Host/Configure\n\nendef\n\ndefine Host/Compile\n\t$(HOSTCC) -c src/iconv.c -o $(HOST_BUILD_DIR)/iconv.o -Isrc/include -fPIC\n\tar rcs $(HOST_BUILD_DIR)/libiconv.a $(HOST_BUILD_DIR)/iconv.o\nendef\n\ndefine Host/Install\n\t$(INSTALL_DIR) $(STAGING_DIR_HOSTPKG)/lib\n\t$(INSTALL_DATA) $(HOST_BUILD_DIR)/libiconv.a $(STAGING_DIR_HOSTPKG)/lib/\n\n\t$(INSTALL_DIR) $(STAGING_DIR_HOSTPKG)/include\n\t$(INSTALL_DATA) ./src/include/iconv.h $(STAGING_DIR_HOSTPKG)/include/\n\n\t$(INSTALL_DIR) $(STAGING_DIR_HOSTPKG)/share/aclocal\n\t$(INSTALL_DATA) ./src/m4/* $(STAGING_DIR_HOSTPKG)/share/aclocal/\nendef\n\n$(eval $(call HostBuild))\n$(eval $(call BuildPackage,libiconv))\n"
  },
  {
    "path": "package/libs/libiconv/src/LICENSE",
    "content": "The source file iconv.m4 contains the following message\n\nCopyright (C) 2000-2002, 2007-2010 Free Software Foundation, Inc.\nThis file is free software; the Free Software Foundation\ngives unlimited permission to copy and/or distribute it,\nwith or without modifications, as long as this notice is preserved.\n"
  },
  {
    "path": "package/libs/libiconv/src/iconv.c",
    "content": "#include <iconv.h>\n#include <errno.h>\n#include <wchar.h>\n#include <string.h>\n#include <strings.h>\n#include <stdlib.h>\n#include <limits.h>\n\n#include <dirent.h>\n#include <fcntl.h>\n#include <sys/mman.h>\n#include <sys/stat.h>\n#include <unistd.h>\n#include <stdint.h>\n\n/* builtin charmaps */\n#include \"charmaps.h\"\n\n/* only 0-7 are valid as dest charset */\n#define UTF_16BE    000\n#define UTF_16LE    001\n#define UTF_32BE    002\n#define UTF_32LE    003\n#define WCHAR_T     004\n#define UTF_8       005\n#define US_ASCII    006\n#define LATIN_1     007\n\n/* additional charsets with algorithmic conversion */\n#define LATIN_9     010\n#define TIS_620     011\n#define JIS_0201    012\n\n/* some programs like php need this */\nint _libiconv_version = _LIBICONV_VERSION;\n\n/* these must match the constants above */\nstatic const unsigned char charsets[] =\n\t\"\\005\" \"UTF-8\"      \"\\0\"\n\t\"\\004\" \"WCHAR_T\"    \"\\0\"\n\t\"\\000\" \"UTF-16BE\"   \"\\0\"\n\t\"\\001\" \"UTF-16LE\"   \"\\0\"\n\t\"\\002\" \"UTF-32BE\"   \"\\0\"\n\t\"\\003\" \"UTF-32LE\"   \"\\0\"\n\t\"\\006\" \"ASCII\"      \"\\0\"\n\t\"\\006\" \"US-ASCII\"   \"\\0\"\n\t\"\\006\" \"ISO646-US\"  \"\\0\"\n\t\"\\006\" \"ISO_646.IRV:1991\"  \"\\0\"\n\t\"\\006\" \"ISO-IR-6\"   \"\\0\"\n\t\"\\006\" \"ANSI_X3.4-1968\"    \"\\0\"\n\t\"\\006\" \"ANSI_X3.4-1986\"    \"\\0\"\n\t\"\\006\" \"CP367\"      \"\\0\"\n\t\"\\006\" \"IBM367\"     \"\\0\"\n\t\"\\006\" \"US\"         \"\\0\"\n\t\"\\006\" \"CSASCII\"    \"\\0\"\n\t\"\\007\" \"ISO-8859-1\" \"\\0\"\n\t\"\\007\" \"LATIN1\"     \"\\0\"\n\t\"\\010\" \"ISO-8859-15\"\"\\0\"\n\t\"\\010\" \"LATIN9\"     \"\\0\"\n\t\"\\011\" \"ISO-8859-11\"\"\\0\"\n\t\"\\011\" \"TIS-620\"    \"\\0\"\n\t\"\\012\" \"JIS-0201\"   \"\\0\"\n\t\"\\377\";\n\n/* separate identifiers for sbcs/dbcs/etc map type */\n#define UCS2_8BIT   000\n#define UCS3_8BIT   001\n#define EUC         002\n#define EUC_TW      003\n#define SHIFT_JIS   004\n#define BIG5        005\n#define GBK         006\n\n/* FIXME: these are not implemented yet\n// EUC:   A1-FE A1-FE\n// GBK:   81-FE 40-7E,80-FE\n// Big5:  A1-FE 40-7E,A1-FE\n*/\n\nstatic const unsigned short maplen[] = {\n\t[UCS2_8BIT] = 4+ 2* 128,\n\t[UCS3_8BIT] = 4+ 3* 128,\n\t[EUC]       = 4+ 2* 94*94,\n\t[SHIFT_JIS] = 4+ 2* 94*94,\n\t[BIG5]      = 4+ 2* 94*157,\n\t[GBK]       = 4+ 2* 126*190,\n\t[EUC_TW]    = 4+ 2* 2*94*94,\n};\n\nstatic int find_charmap(const char *name)\n{\n\tint i;\n\tfor (i = 0; i < (sizeof(charmaps) / sizeof(charmaps[0])); i++)\n\t\tif (!strcasecmp(charmaps[i].name, name))\n\t\t\treturn i;\n\treturn -1;\n}\n\nstatic int find_charset(const char *name)\n{\n\tconst unsigned char *s;\n\tfor (s=charsets; *s<0xff && strcasecmp(s+1, name); s+=strlen(s)+1);\n\treturn *s;\n}\n\niconv_t iconv_open(const char *to, const char *from)\n{\n\tunsigned f, t;\n\tint m;\n\n\tif ((t = find_charset(to)) > 8)\n\t\treturn -1;\n\n\tif ((f = find_charset(from)) < 255)\n\t\treturn 0 | (t<<1) | (f<<8);\n\n\tif ((m = find_charmap(from)) > -1)\n\t\treturn 1 | (t<<1) | (m<<8);\n\n\treturn -1;\n}\n\nint iconv_close(iconv_t cd)\n{\n\treturn 0;\n}\n\nstatic inline wchar_t get_16(const unsigned char *s, int endian)\n{\n\tendian &= 1;\n\treturn s[endian]<<8 | s[endian^1];\n}\n\nstatic inline void put_16(unsigned char *s, wchar_t c, int endian)\n{\n\tendian &= 1;\n\ts[endian] = c>>8;\n\ts[endian^1] = c;\n}\n\nstatic inline int utf8enc_wchar(char *outb, wchar_t c)\n{\n\tif (c <= 0x7F) {\n\t\t*outb = c;\n\t\treturn 1;\n\t}\n\telse if (c <= 0x7FF) {\n\t\t*outb++ = ((c >>  6) & 0x1F) | 0xC0;\n\t\t*outb++ = ( c        & 0x3F) | 0x80;\n\t\treturn 2;\n\t}\n\telse if (c <= 0xFFFF) {\n\t\t*outb++ = ((c >> 12) & 0x0F) | 0xE0;\n\t\t*outb++ = ((c >>  6) & 0x3F) | 0x80;\n\t\t*outb++ = ( c        & 0x3F) | 0x80;\n\t\treturn 3;\n\t}\n\telse if (c <= 0x10FFFF) {\n\t\t*outb++ = ((c >> 18) & 0x07) | 0xF0;\n\t\t*outb++ = ((c >> 12) & 0x3F) | 0x80;\n\t\t*outb++ = ((c >>  6) & 0x3F) | 0x80;\n\t\t*outb++ = ( c        & 0x3F) | 0x80;\n\t\treturn 4;\n\t}\n\telse {\n\t\t*outb++ = '?';\n\t\treturn 1;\n\t}\n}\n\nstatic inline int utf8seq_is_overlong(char *s, int n)\n{\n\tswitch (n)\n\t{\n\tcase 2:\n\t\t/* 1100000x (10xxxxxx) */\n\t\treturn (((*s >> 1) == 0x60) &&\n\t\t\t\t((*(s+1) >> 6) == 0x02));\n\n\tcase 3:\n\t\t/* 11100000 100xxxxx (10xxxxxx) */\n\t\treturn ((*s == 0xE0) &&\n\t\t\t\t((*(s+1) >> 5) == 0x04) &&\n\t\t\t\t((*(s+2) >> 6) == 0x02));\n\n\tcase 4:\n\t\t/* 11110000 1000xxxx (10xxxxxx 10xxxxxx) */\n\t\treturn ((*s == 0xF0) &&\n\t\t\t\t((*(s+1) >> 4) == 0x08) &&\n\t\t\t\t((*(s+2) >> 6) == 0x02) &&\n\t\t\t\t((*(s+3) >> 6) == 0x02));\n\t}\n\n\treturn 0;\n}\n\nstatic inline int utf8seq_is_surrogate(char *s, int n)\n{\n\treturn ((n == 3) && (*s == 0xED) && (*(s+1) >= 0xA0) && (*(s+1) <= 0xBF));\n}\n\nstatic inline int utf8seq_is_illegal(char *s, int n)\n{\n\treturn ((n == 3) && (*s == 0xEF) && (*(s+1) == 0xBF) &&\n\t        (*(s+2) >= 0xBE) && (*(s+2) <= 0xBF));\n}\n\nstatic inline int utf8dec_wchar(wchar_t *c, unsigned char *in, size_t inb)\n{\n\tint i;\n\tint n = -1;\n\n\t/* trivial char */\n\tif (*in <= 0x7F) {\n\t\t*c = *in;\n\t\treturn 1;\n\t}\n\n\t/* find utf8 sequence length */\n\tif      ((*in & 0xE0) == 0xC0) n = 2;\n\telse if ((*in & 0xF0) == 0xE0) n = 3;\n\telse if ((*in & 0xF8) == 0xF0) n = 4;\n\telse if ((*in & 0xFC) == 0xF8) n = 5;\n\telse if ((*in & 0xFE) == 0xFC) n = 6;\n\n\t/* starved? */\n\tif (n > inb)\n\t\treturn -2;\n\n\t/* decode ... */\n\tif (n > 1 && n < 5) {\n\t\t/* reject invalid sequences */\n\t\tif (utf8seq_is_overlong(in, n) ||\n\t\t\tutf8seq_is_surrogate(in, n) ||\n\t\t\tutf8seq_is_illegal(in, n))\n\t\t\treturn -1;\n\n\t\t/* decode ... */\n\t\t*c = (char)(*in++ & (0x7F >> n));\n\n\t\tfor (i = 1; i < n; i++) {\n\t\t\t/* illegal continuation byte */\n\t\t\tif (*in < 0x80 || *in > 0xBF)\n\t\t\t\treturn -1;\n\n\t\t\t*c = (*c << 6) | (*in++ & 0x3F);\n\t\t}\n\n\t\treturn n;\n\t}\n\n\t/* unmapped sequence (> 4) */\n\treturn -1;\n}\n\nstatic inline wchar_t latin9_translit(wchar_t c)\n{\n\t/* a number of trivial iso-8859-15 <> utf-8 transliterations */\n\tswitch (c) {\n\tcase 0x20AC: return 0xA4; /* Euro */\n\tcase 0x0160: return 0xA6; /* S caron */\n\tcase 0x0161: return 0xA8; /* s caron */\n\tcase 0x017D: return 0xB4; /* Z caron */\n\tcase 0x017E: return 0xB8; /* z caron */\n\tcase 0x0152: return 0xBC; /* OE */\n\tcase 0x0153: return 0xBD; /* oe */\n\tcase 0x0178: return 0xBE; /* Y diaeresis */\n\tdefault:     return 0xFFFD; /* cannot translate */\n\t}\n}\n\nsize_t iconv(iconv_t cd, char **in, size_t *inb, char **out, size_t *outb)\n{\n\tsize_t x=0;\n\tunsigned char to = (cd>>1)&127;\n\tunsigned char from = 255;\n\tconst unsigned char *map = 0;\n\tchar tmp[MB_LEN_MAX];\n\twchar_t c, d;\n\tsize_t k, l;\n\tint err;\n\n\tif (!in || !*in || !*inb) return 0;\n\n\tif (cd & 1)\n\t\tmap = charmaps[cd>>8].map;\n\telse\n\t\tfrom = cd>>8;\n\n\tfor (; *inb; *in+=l, *inb-=l) {\n\t\tc = *(unsigned char *)*in;\n\t\tl = 1;\n\t\tif (from >= UTF_8 && c < 0x80) goto charok;\n\t\tswitch (from) {\n\t\tcase WCHAR_T:\n\t\t\tl = sizeof(wchar_t);\n\t\t\tif (*inb < l) goto starved;\n\t\t\tc = *(wchar_t *)*in;\n\t\t\tbreak;\n\t\tcase UTF_8:\n\t\t\tl = utf8dec_wchar(&c, *in, *inb);\n\t\t\tif (!l) l++;\n\t\t\telse if (l == (size_t)-1) goto ilseq;\n\t\t\telse if (l == (size_t)-2) goto starved;\n\t\t\tbreak;\n\t\tcase US_ASCII:\n\t\t\tgoto ilseq;\n\t\tcase LATIN_9:\n\t\t\tif ((unsigned)c - 0xa4 <= 0xbe - 0xa4) {\n\t\t\t\tstatic const unsigned char map[] = {\n\t\t\t\t\t0, 0x60, 0, 0x61, 0, 0, 0, 0, 0, 0, 0,\n\t\t\t\t\t0, 0, 0, 0, 0x7d, 0, 0, 0, 0x7e, 0, 0, 0,\n\t\t\t\t\t0x52, 0x53, 0x78\n\t\t\t\t};\n\t\t\t\tif (c == 0xa4) c = 0x20ac;\n\t\t\t\telse if (map[c-0xa5]) c = 0x100 | map[c-0xa5];\n\t\t\t}\n\t\tcase LATIN_1:\n\t\t\tgoto charok;\n\t\tcase TIS_620:\n\t\t\tif (c >= 0xa1) c += 0x0e01-0xa1;\n\t\t\tgoto charok;\n\t\tcase JIS_0201:\n\t\t\tif (c >= 0xa1) {\n\t\t\t\tif (c <= 0xdf) c += 0xff61-0xa1;\n\t\t\t\telse goto ilseq;\n\t\t\t}\n\t\t\tgoto charok;\n\t\tcase UTF_16BE:\n\t\tcase UTF_16LE:\n\t\t\tl = 2;\n\t\t\tif (*inb < 2) goto starved;\n\t\t\tc = get_16(*in, from);\n\t\t\tif ((unsigned)(c-0xdc00) < 0x400) goto ilseq;\n\t\t\tif ((unsigned)(c-0xd800) < 0x400) {\n\t\t\t\tl = 4;\n\t\t\t\tif (*inb < 4) goto starved;\n\t\t\t\td = get_16(*in + 2, from);\n\t\t\t\tif ((unsigned)(c-0xdc00) >= 0x400) goto ilseq;\n\t\t\t\tc = ((c-0xd800)<<10) | (d-0xdc00);\n\t\t\t}\n\t\t\tbreak;\n\t\tcase UTF_32BE:\n\t\tcase UTF_32LE:\n\t\t\tl = 4;\n\t\t\tif (*inb < 4) goto starved;\n\t\t\t// FIXME\n\t\t\t// c = get_32(*in, from);\n\t\t\tbreak;\n\t\tdefault:\n\t\t\t/* only support ascii supersets */\n\t\t\tif (c < 0x80) break;\n\t\t\tswitch (map[0]) {\n\t\t\tcase UCS2_8BIT:\n\t\t\t\tc -= 0x80;\n\t\t\t\tbreak;\n\t\t\tcase EUC:\n\t\t\t\tif ((unsigned)c - 0xa1 >= 94) goto ilseq;\n\t\t\t\tif ((unsigned)in[0][1] - 0xa1 >= 94) goto ilseq;\n\t\t\t\tc = (c-0xa1)*94 + (in[0][1]-0xa1);\n\t\t\t\tl = 2;\n\t\t\t\tbreak;\n\t\t\tcase SHIFT_JIS:\n\t\t\t\tif ((unsigned)c - 0xa1 <= 0xdf-0xa1) {\n\t\t\t\t\tc += 0xff61-0xa1;\n\t\t\t\t\tgoto charok;\n\t\t\t\t}\n\t\t\t\t// FIXME...\n\t\t\t\tl = 2;\n\t\t\t\tbreak;\n\t\t\tdefault:\n\t\t\t\tgoto badf;\n\t\t\t}\n\t\t\tc = get_16(map + 4 + 2*c, 0);\n\t\t\tif (c == 0xffff) goto ilseq;\n\t\t\tgoto charok;\n\t\t}\n\n\t\tif ((unsigned)c - 0xd800 < 0x800 || (unsigned)c >= 0x110000)\n\t\t\tgoto ilseq;\ncharok:\n\t\tswitch (to) {\n\t\tcase WCHAR_T:\n\t\t\tif (*outb < sizeof(wchar_t)) goto toobig;\n\t\t\t*(wchar_t *)*out = c;\n\t\t\t*out += sizeof(wchar_t);\n\t\t\t*outb -= sizeof(wchar_t);\n\t\t\tbreak;\n\t\tcase UTF_8:\n\t\t\tif (*outb < 4) {\n\t\t\t\tk = utf8enc_wchar(tmp, c);\n\t\t\t\tif (*outb < k) goto toobig;\n\t\t\t\tmemcpy(*out, tmp, k);\n\t\t\t} else k = utf8enc_wchar(*out, c);\n\t\t\t*out += k;\n\t\t\t*outb -= k;\n\t\t\tbreak;\n\t\tcase US_ASCII:\n\t\t\tif (c > 0x7f) c = 0xfffd;\n\t\t\t/* fall thru and count replacement in latin1 case */\n\t\tcase LATIN_9:\n\t\t\tif (c >= 0x100 && c != 0xfffd)\n\t\t\t\tc = latin9_translit(c);\n\t\t\t/* fall through */\n\t\tcase LATIN_1:\n\t\t\tif (c > 0xff) goto ilseq;\n\t\t\tif (!*outb) goto toobig;\n\t\t\t**out = c;\n\t\t\t++*out;\n\t\t\t--*outb;\n\t\t\tbreak;\n\t\tcase UTF_16BE:\n\t\tcase UTF_16LE:\n\t\t\tif (c < 0x10000) {\n\t\t\t\tif (*outb < 2) goto toobig;\n\t\t\t\tput_16(*out, c, to);\n\t\t\t\t*out += 2;\n\t\t\t\t*outb -= 2;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\tif (*outb < 4) goto toobig;\n\t\t\tput_16(*out, (c>>10)|0xd800, to);\n\t\t\tput_16(*out + 2, (c&0x3ff)|0xdc00, to);\n\t\t\t*out += 4;\n\t\t\t*outb -= 4;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tgoto badf;\n\t\t}\n\t}\n\treturn x;\nilseq:\n\terr = EILSEQ;\n\tx = -1;\n\tgoto end;\nbadf:\n\terr = EBADF;\n\tx = -1;\n\tgoto end;\ntoobig:\n\terr = E2BIG;\n\tx = -1;\n\tgoto end;\nstarved:\n\terr = EINVAL;\nend:\n\terrno = err;\n\treturn x;\n}\n"
  },
  {
    "path": "package/libs/libiconv/src/include/charmaps/iso-8859-10.h",
    "content": "static const unsigned char map_iso_8859_10[] = {\n\t0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x81, 0x00, 0x82, 0x00, 0x83,\n\t0x00, 0x84, 0x00, 0x85, 0x00, 0x86, 0x00, 0x87, 0x00, 0x88, 0x00, 0x89,\n\t0x00, 0x8a, 0x00, 0x8b, 0x00, 0x8c, 0x00, 0x8d, 0x00, 0x8e, 0x00, 0x8f,\n\t0x00, 0x90, 0x00, 0x91, 0x00, 0x92, 0x00, 0x93, 0x00, 0x94, 0x00, 0x95,\n\t0x00, 0x96, 0x00, 0x97, 0x00, 0x98, 0x00, 0x99, 0x00, 0x9a, 0x00, 0x9b,\n\t0x00, 0x9c, 0x00, 0x9d, 0x00, 0x9e, 0x00, 0x9f, 0x00, 0xa0, 0x01, 0x04,\n\t0x01, 0x12, 0x01, 0x22, 0x01, 0x2a, 0x01, 0x28, 0x01, 0x36, 0x00, 0xa7,\n\t0x01, 0x3b, 0x01, 0x10, 0x01, 0x60, 0x01, 0x66, 0x01, 0x7d, 0x00, 0xad,\n\t0x01, 0x6a, 0x01, 0x4a, 0x00, 0xb0, 0x01, 0x05, 0x01, 0x13, 0x01, 0x23,\n\t0x01, 0x2b, 0x01, 0x29, 0x01, 0x37, 0x00, 0xb7, 0x01, 0x3c, 0x01, 0x11,\n\t0x01, 0x61, 0x01, 0x67, 0x01, 0x7e, 0x20, 0x15, 0x01, 0x6b, 0x01, 0x4b,\n\t0x01, 0x00, 0x00, 0xc1, 0x00, 0xc2, 0x00, 0xc3, 0x00, 0xc4, 0x00, 0xc5,\n\t0x00, 0xc6, 0x01, 0x2e, 0x01, 0x0c, 0x00, 0xc9, 0x01, 0x18, 0x00, 0xcb,\n\t0x01, 0x16, 0x00, 0xcd, 0x00, 0xce, 0x00, 0xcf, 0x00, 0xd0, 0x01, 0x45,\n\t0x01, 0x4c, 0x00, 0xd3, 0x00, 0xd4, 0x00, 0xd5, 0x00, 0xd6, 0x01, 0x68,\n\t0x00, 0xd8, 0x01, 0x72, 0x00, 0xda, 0x00, 0xdb, 0x00, 0xdc, 0x00, 0xdd,\n\t0x00, 0xde, 0x00, 0xdf, 0x01, 0x01, 0x00, 0xe1, 0x00, 0xe2, 0x00, 0xe3,\n\t0x00, 0xe4, 0x00, 0xe5, 0x00, 0xe6, 0x01, 0x2f, 0x01, 0x0d, 0x00, 0xe9,\n\t0x01, 0x19, 0x00, 0xeb, 0x01, 0x17, 0x00, 0xed, 0x00, 0xee, 0x00, 0xef,\n\t0x00, 0xf0, 0x01, 0x46, 0x01, 0x4d, 0x00, 0xf3, 0x00, 0xf4, 0x00, 0xf5,\n\t0x00, 0xf6, 0x01, 0x69, 0x00, 0xf8, 0x01, 0x73, 0x00, 0xfa, 0x00, 0xfb,\n\t0x00, 0xfc, 0x00, 0xfd, 0x00, 0xfe, 0x01, 0x38\n};\n"
  },
  {
    "path": "package/libs/libiconv/src/include/charmaps/iso-8859-13.h",
    "content": "static const unsigned char map_iso_8859_13[] = {\n\t0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x81, 0x00, 0x82, 0x00, 0x83,\n\t0x00, 0x84, 0x00, 0x85, 0x00, 0x86, 0x00, 0x87, 0x00, 0x88, 0x00, 0x89,\n\t0x00, 0x8a, 0x00, 0x8b, 0x00, 0x8c, 0x00, 0x8d, 0x00, 0x8e, 0x00, 0x8f,\n\t0x00, 0x90, 0x00, 0x91, 0x00, 0x92, 0x00, 0x93, 0x00, 0x94, 0x00, 0x95,\n\t0x00, 0x96, 0x00, 0x97, 0x00, 0x98, 0x00, 0x99, 0x00, 0x9a, 0x00, 0x9b,\n\t0x00, 0x9c, 0x00, 0x9d, 0x00, 0x9e, 0x00, 0x9f, 0x00, 0xa0, 0x20, 0x1d,\n\t0x00, 0xa2, 0x00, 0xa3, 0x00, 0xa4, 0x20, 0x1e, 0x00, 0xa6, 0x00, 0xa7,\n\t0x00, 0xd8, 0x00, 0xa9, 0x01, 0x56, 0x00, 0xab, 0x00, 0xac, 0x00, 0xad,\n\t0x00, 0xae, 0x00, 0xc6, 0x00, 0xb0, 0x00, 0xb1, 0x00, 0xb2, 0x00, 0xb3,\n\t0x20, 0x1c, 0x00, 0xb5, 0x00, 0xb6, 0x00, 0xb7, 0x00, 0xf8, 0x00, 0xb9,\n\t0x01, 0x57, 0x00, 0xbb, 0x00, 0xbc, 0x00, 0xbd, 0x00, 0xbe, 0x00, 0xe6,\n\t0x01, 0x04, 0x01, 0x2e, 0x01, 0x00, 0x01, 0x06, 0x00, 0xc4, 0x00, 0xc5,\n\t0x01, 0x18, 0x01, 0x12, 0x01, 0x0c, 0x00, 0xc9, 0x01, 0x79, 0x01, 0x16,\n\t0x01, 0x22, 0x01, 0x36, 0x01, 0x2a, 0x01, 0x3b, 0x01, 0x60, 0x01, 0x43,\n\t0x01, 0x45, 0x00, 0xd3, 0x01, 0x4c, 0x00, 0xd5, 0x00, 0xd6, 0x00, 0xd7,\n\t0x01, 0x72, 0x01, 0x41, 0x01, 0x5a, 0x01, 0x6a, 0x00, 0xdc, 0x01, 0x7b,\n\t0x01, 0x7d, 0x00, 0xdf, 0x01, 0x05, 0x01, 0x2f, 0x01, 0x01, 0x01, 0x07,\n\t0x00, 0xe4, 0x00, 0xe5, 0x01, 0x19, 0x01, 0x13, 0x01, 0x0d, 0x00, 0xe9,\n\t0x01, 0x7a, 0x01, 0x17, 0x01, 0x23, 0x01, 0x37, 0x01, 0x2b, 0x01, 0x3c,\n\t0x01, 0x61, 0x01, 0x44, 0x01, 0x46, 0x00, 0xf3, 0x01, 0x4d, 0x00, 0xf5,\n\t0x00, 0xf6, 0x00, 0xf7, 0x01, 0x73, 0x01, 0x42, 0x01, 0x5b, 0x01, 0x6b,\n\t0x00, 0xfc, 0x01, 0x7c, 0x01, 0x7e, 0x20, 0x19\n};\n"
  },
  {
    "path": "package/libs/libiconv/src/include/charmaps/iso-8859-14.h",
    "content": "static const unsigned char map_iso_8859_14[] = {\n\t0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x81, 0x00, 0x82, 0x00, 0x83,\n\t0x00, 0x84, 0x00, 0x85, 0x00, 0x86, 0x00, 0x87, 0x00, 0x88, 0x00, 0x89,\n\t0x00, 0x8a, 0x00, 0x8b, 0x00, 0x8c, 0x00, 0x8d, 0x00, 0x8e, 0x00, 0x8f,\n\t0x00, 0x90, 0x00, 0x91, 0x00, 0x92, 0x00, 0x93, 0x00, 0x94, 0x00, 0x95,\n\t0x00, 0x96, 0x00, 0x97, 0x00, 0x98, 0x00, 0x99, 0x00, 0x9a, 0x00, 0x9b,\n\t0x00, 0x9c, 0x00, 0x9d, 0x00, 0x9e, 0x00, 0x9f, 0x00, 0xa0, 0x1e, 0x02,\n\t0x1e, 0x03, 0x00, 0xa3, 0x01, 0x0a, 0x01, 0x0b, 0x1e, 0x0a, 0x00, 0xa7,\n\t0x1e, 0x80, 0x00, 0xa9, 0x1e, 0x82, 0x1e, 0x0b, 0x1e, 0xf2, 0x00, 0xad,\n\t0x00, 0xae, 0x01, 0x78, 0x1e, 0x1e, 0x1e, 0x1f, 0x01, 0x20, 0x01, 0x21,\n\t0x1e, 0x40, 0x1e, 0x41, 0x00, 0xb6, 0x1e, 0x56, 0x1e, 0x81, 0x1e, 0x57,\n\t0x1e, 0x83, 0x1e, 0x60, 0x1e, 0xf3, 0x1e, 0x84, 0x1e, 0x85, 0x1e, 0x61,\n\t0x00, 0xc0, 0x00, 0xc1, 0x00, 0xc2, 0x00, 0xc3, 0x00, 0xc4, 0x00, 0xc5,\n\t0x00, 0xc6, 0x00, 0xc7, 0x00, 0xc8, 0x00, 0xc9, 0x00, 0xca, 0x00, 0xcb,\n\t0x00, 0xcc, 0x00, 0xcd, 0x00, 0xce, 0x00, 0xcf, 0x01, 0x74, 0x00, 0xd1,\n\t0x00, 0xd2, 0x00, 0xd3, 0x00, 0xd4, 0x00, 0xd5, 0x00, 0xd6, 0x1e, 0x6a,\n\t0x00, 0xd8, 0x00, 0xd9, 0x00, 0xda, 0x00, 0xdb, 0x00, 0xdc, 0x00, 0xdd,\n\t0x01, 0x76, 0x00, 0xdf, 0x00, 0xe0, 0x00, 0xe1, 0x00, 0xe2, 0x00, 0xe3,\n\t0x00, 0xe4, 0x00, 0xe5, 0x00, 0xe6, 0x00, 0xe7, 0x00, 0xe8, 0x00, 0xe9,\n\t0x00, 0xea, 0x00, 0xeb, 0x00, 0xec, 0x00, 0xed, 0x00, 0xee, 0x00, 0xef,\n\t0x01, 0x75, 0x00, 0xf1, 0x00, 0xf2, 0x00, 0xf3, 0x00, 0xf4, 0x00, 0xf5,\n\t0x00, 0xf6, 0x1e, 0x6b, 0x00, 0xf8, 0x00, 0xf9, 0x00, 0xfa, 0x00, 0xfb,\n\t0x00, 0xfc, 0x00, 0xfd, 0x01, 0x77, 0x00, 0xff\n};\n\n"
  },
  {
    "path": "package/libs/libiconv/src/include/charmaps/iso-8859-16.h",
    "content": "static const unsigned char map_iso_8859_16[] = {\n\t0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x81, 0x00, 0x82, 0x00, 0x83,\n\t0x00, 0x84, 0x00, 0x85, 0x00, 0x86, 0x00, 0x87, 0x00, 0x88, 0x00, 0x89,\n\t0x00, 0x8a, 0x00, 0x8b, 0x00, 0x8c, 0x00, 0x8d, 0x00, 0x8e, 0x00, 0x8f,\n\t0x00, 0x90, 0x00, 0x91, 0x00, 0x92, 0x00, 0x93, 0x00, 0x94, 0x00, 0x95,\n\t0x00, 0x96, 0x00, 0x97, 0x00, 0x98, 0x00, 0x99, 0x00, 0x9a, 0x00, 0x9b,\n\t0x00, 0x9c, 0x00, 0x9d, 0x00, 0x9e, 0x00, 0x9f, 0x00, 0xa0, 0x01, 0x04,\n\t0x01, 0x05, 0x01, 0x41, 0x20, 0xac, 0x20, 0x1e, 0x01, 0x60, 0x00, 0xa7,\n\t0x01, 0x61, 0x00, 0xa9, 0x02, 0x18, 0x00, 0xab, 0x01, 0x79, 0x00, 0xad,\n\t0x01, 0x7a, 0x01, 0x7b, 0x00, 0xb0, 0x00, 0xb1, 0x01, 0x0c, 0x01, 0x42,\n\t0x01, 0x7d, 0x20, 0x1d, 0x00, 0xb6, 0x00, 0xb7, 0x01, 0x7e, 0x01, 0x0d,\n\t0x02, 0x19, 0x00, 0xbb, 0x01, 0x52, 0x01, 0x53, 0x01, 0x78, 0x01, 0x7c,\n\t0x00, 0xc0, 0x00, 0xc1, 0x00, 0xc2, 0x01, 0x02, 0x00, 0xc4, 0x01, 0x06,\n\t0x00, 0xc6, 0x00, 0xc7, 0x00, 0xc8, 0x00, 0xc9, 0x00, 0xca, 0x00, 0xcb,\n\t0x00, 0xcc, 0x00, 0xcd, 0x00, 0xce, 0x00, 0xcf, 0x01, 0x10, 0x01, 0x43,\n\t0x00, 0xd2, 0x00, 0xd3, 0x00, 0xd4, 0x01, 0x50, 0x00, 0xd6, 0x01, 0x5a,\n\t0x01, 0x70, 0x00, 0xd9, 0x00, 0xda, 0x00, 0xdb, 0x00, 0xdc, 0x01, 0x18,\n\t0x02, 0x1a, 0x00, 0xdf, 0x00, 0xe0, 0x00, 0xe1, 0x00, 0xe2, 0x01, 0x03,\n\t0x00, 0xe4, 0x01, 0x07, 0x00, 0xe6, 0x00, 0xe7, 0x00, 0xe8, 0x00, 0xe9,\n\t0x00, 0xea, 0x00, 0xeb, 0x00, 0xec, 0x00, 0xed, 0x00, 0xee, 0x00, 0xef,\n\t0x01, 0x11, 0x01, 0x44, 0x00, 0xf2, 0x00, 0xf3, 0x00, 0xf4, 0x01, 0x51,\n\t0x00, 0xf6, 0x01, 0x5b, 0x01, 0x71, 0x00, 0xf9, 0x00, 0xfa, 0x00, 0xfb,\n\t0x00, 0xfc, 0x01, 0x19, 0x02, 0x1b, 0x00, 0xff\n};\n"
  },
  {
    "path": "package/libs/libiconv/src/include/charmaps/iso-8859-2.h",
    "content": "static const unsigned char map_iso_8859_2[] = {\n\t0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x81, 0x00, 0x82, 0x00, 0x83,\n\t0x00, 0x84, 0x00, 0x85, 0x00, 0x86, 0x00, 0x87, 0x00, 0x88, 0x00, 0x89,\n\t0x00, 0x8a, 0x00, 0x8b, 0x00, 0x8c, 0x00, 0x8d, 0x00, 0x8e, 0x00, 0x8f,\n\t0x00, 0x90, 0x00, 0x91, 0x00, 0x92, 0x00, 0x93, 0x00, 0x94, 0x00, 0x95,\n\t0x00, 0x96, 0x00, 0x97, 0x00, 0x98, 0x00, 0x99, 0x00, 0x9a, 0x00, 0x9b,\n\t0x00, 0x9c, 0x00, 0x9d, 0x00, 0x9e, 0x00, 0x9f, 0x00, 0xa0, 0x01, 0x04,\n\t0x02, 0xd8, 0x01, 0x41, 0x00, 0xa4, 0x01, 0x3d, 0x01, 0x5a, 0x00, 0xa7,\n\t0x00, 0xa8, 0x01, 0x60, 0x01, 0x5e, 0x01, 0x64, 0x01, 0x79, 0x00, 0xad,\n\t0x01, 0x7d, 0x01, 0x7b, 0x00, 0xb0, 0x01, 0x05, 0x02, 0xdb, 0x01, 0x42,\n\t0x00, 0xb4, 0x01, 0x3e, 0x01, 0x5b, 0x02, 0xc7, 0x00, 0xb8, 0x01, 0x61,\n\t0x01, 0x5f, 0x01, 0x65, 0x01, 0x7a, 0x02, 0xdd, 0x01, 0x7e, 0x01, 0x7c,\n\t0x01, 0x54, 0x00, 0xc1, 0x00, 0xc2, 0x01, 0x02, 0x00, 0xc4, 0x01, 0x39,\n\t0x01, 0x06, 0x00, 0xc7, 0x01, 0x0c, 0x00, 0xc9, 0x01, 0x18, 0x00, 0xcb,\n\t0x01, 0x1a, 0x00, 0xcd, 0x00, 0xce, 0x01, 0x0e, 0x01, 0x10, 0x01, 0x43,\n\t0x01, 0x47, 0x00, 0xd3, 0x00, 0xd4, 0x01, 0x50, 0x00, 0xd6, 0x00, 0xd7,\n\t0x01, 0x58, 0x01, 0x6e, 0x00, 0xda, 0x01, 0x70, 0x00, 0xdc, 0x00, 0xdd,\n\t0x01, 0x62, 0x00, 0xdf, 0x01, 0x55, 0x00, 0xe1, 0x00, 0xe2, 0x01, 0x03,\n\t0x00, 0xe4, 0x01, 0x3a, 0x01, 0x07, 0x00, 0xe7, 0x01, 0x0d, 0x00, 0xe9,\n\t0x01, 0x19, 0x00, 0xeb, 0x01, 0x1b, 0x00, 0xed, 0x00, 0xee, 0x01, 0x0f,\n\t0x01, 0x11, 0x01, 0x44, 0x01, 0x48, 0x00, 0xf3, 0x00, 0xf4, 0x01, 0x51,\n\t0x00, 0xf6, 0x00, 0xf7, 0x01, 0x59, 0x01, 0x6f, 0x00, 0xfa, 0x01, 0x71,\n\t0x00, 0xfc, 0x00, 0xfd, 0x01, 0x63, 0x02, 0xd9\n};\n"
  },
  {
    "path": "package/libs/libiconv/src/include/charmaps/iso-8859-3.h",
    "content": "static const unsigned char map_iso_8859_3[] = {\n\t0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x81, 0x00, 0x82, 0x00, 0x83,\n\t0x00, 0x84, 0x00, 0x85, 0x00, 0x86, 0x00, 0x87, 0x00, 0x88, 0x00, 0x89,\n\t0x00, 0x8a, 0x00, 0x8b, 0x00, 0x8c, 0x00, 0x8d, 0x00, 0x8e, 0x00, 0x8f,\n\t0x00, 0x90, 0x00, 0x91, 0x00, 0x92, 0x00, 0x93, 0x00, 0x94, 0x00, 0x95,\n\t0x00, 0x96, 0x00, 0x97, 0x00, 0x98, 0x00, 0x99, 0x00, 0x9a, 0x00, 0x9b,\n\t0x00, 0x9c, 0x00, 0x9d, 0x00, 0x9e, 0x00, 0x9f, 0x00, 0xa0, 0x01, 0x26,\n\t0x02, 0xd8, 0x00, 0xa3, 0x00, 0xa4, 0xff, 0xff, 0x01, 0x24, 0x00, 0xa7,\n\t0x00, 0xa8, 0x01, 0x30, 0x01, 0x5e, 0x01, 0x1e, 0x01, 0x34, 0x00, 0xad,\n\t0xff, 0xff, 0x01, 0x7b, 0x00, 0xb0, 0x01, 0x27, 0x00, 0xb2, 0x00, 0xb3,\n\t0x00, 0xb4, 0x00, 0xb5, 0x01, 0x25, 0x00, 0xb7, 0x00, 0xb8, 0x01, 0x31,\n\t0x01, 0x5f, 0x01, 0x1f, 0x01, 0x35, 0x00, 0xbd, 0xff, 0xff, 0x01, 0x7c,\n\t0x00, 0xc0, 0x00, 0xc1, 0x00, 0xc2, 0xff, 0xff, 0x00, 0xc4, 0x01, 0x0a,\n\t0x01, 0x08, 0x00, 0xc7, 0x00, 0xc8, 0x00, 0xc9, 0x00, 0xca, 0x00, 0xcb,\n\t0x00, 0xcc, 0x00, 0xcd, 0x00, 0xce, 0x00, 0xcf, 0xff, 0xff, 0x00, 0xd1,\n\t0x00, 0xd2, 0x00, 0xd3, 0x00, 0xd4, 0x01, 0x20, 0x00, 0xd6, 0x00, 0xd7,\n\t0x01, 0x1c, 0x00, 0xd9, 0x00, 0xda, 0x00, 0xdb, 0x00, 0xdc, 0x01, 0x6c,\n\t0x01, 0x5c, 0x00, 0xdf, 0x00, 0xe0, 0x00, 0xe1, 0x00, 0xe2, 0xff, 0xff,\n\t0x00, 0xe4, 0x01, 0x0b, 0x01, 0x09, 0x00, 0xe7, 0x00, 0xe8, 0x00, 0xe9,\n\t0x00, 0xea, 0x00, 0xeb, 0x00, 0xec, 0x00, 0xed, 0x00, 0xee, 0x00, 0xef,\n\t0xff, 0xff, 0x00, 0xf1, 0x00, 0xf2, 0x00, 0xf3, 0x00, 0xf4, 0x01, 0x21,\n\t0x00, 0xf6, 0x00, 0xf7, 0x01, 0x1d, 0x00, 0xf9, 0x00, 0xfa, 0x00, 0xfb,\n\t0x00, 0xfc, 0x01, 0x6d, 0x01, 0x5d, 0x02, 0xd9\n};\n"
  },
  {
    "path": "package/libs/libiconv/src/include/charmaps/iso-8859-4.h",
    "content": "static const unsigned char map_iso_8859_4[] = {\n\t0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x81, 0x00, 0x82, 0x00, 0x83,\n\t0x00, 0x84, 0x00, 0x85, 0x00, 0x86, 0x00, 0x87, 0x00, 0x88, 0x00, 0x89,\n\t0x00, 0x8a, 0x00, 0x8b, 0x00, 0x8c, 0x00, 0x8d, 0x00, 0x8e, 0x00, 0x8f,\n\t0x00, 0x90, 0x00, 0x91, 0x00, 0x92, 0x00, 0x93, 0x00, 0x94, 0x00, 0x95,\n\t0x00, 0x96, 0x00, 0x97, 0x00, 0x98, 0x00, 0x99, 0x00, 0x9a, 0x00, 0x9b,\n\t0x00, 0x9c, 0x00, 0x9d, 0x00, 0x9e, 0x00, 0x9f, 0x00, 0xa0, 0x01, 0x04,\n\t0x01, 0x38, 0x01, 0x56, 0x00, 0xa4, 0x01, 0x28, 0x01, 0x3b, 0x00, 0xa7,\n\t0x00, 0xa8, 0x01, 0x60, 0x01, 0x12, 0x01, 0x22, 0x01, 0x66, 0x00, 0xad,\n\t0x01, 0x7d, 0x00, 0xaf, 0x00, 0xb0, 0x01, 0x05, 0x02, 0xdb, 0x01, 0x57,\n\t0x00, 0xb4, 0x01, 0x29, 0x01, 0x3c, 0x02, 0xc7, 0x00, 0xb8, 0x01, 0x61,\n\t0x01, 0x13, 0x01, 0x23, 0x01, 0x67, 0x01, 0x4a, 0x01, 0x7e, 0x01, 0x4b,\n\t0x01, 0x00, 0x00, 0xc1, 0x00, 0xc2, 0x00, 0xc3, 0x00, 0xc4, 0x00, 0xc5,\n\t0x00, 0xc6, 0x01, 0x2e, 0x01, 0x0c, 0x00, 0xc9, 0x01, 0x18, 0x00, 0xcb,\n\t0x01, 0x16, 0x00, 0xcd, 0x00, 0xce, 0x01, 0x2a, 0x01, 0x10, 0x01, 0x45,\n\t0x01, 0x4c, 0x01, 0x36, 0x00, 0xd4, 0x00, 0xd5, 0x00, 0xd6, 0x00, 0xd7,\n\t0x00, 0xd8, 0x01, 0x72, 0x00, 0xda, 0x00, 0xdb, 0x00, 0xdc, 0x01, 0x68,\n\t0x01, 0x6a, 0x00, 0xdf, 0x01, 0x01, 0x00, 0xe1, 0x00, 0xe2, 0x00, 0xe3,\n\t0x00, 0xe4, 0x00, 0xe5, 0x00, 0xe6, 0x01, 0x2f, 0x01, 0x0d, 0x00, 0xe9,\n\t0x01, 0x19, 0x00, 0xeb, 0x01, 0x17, 0x00, 0xed, 0x00, 0xee, 0x01, 0x2b,\n\t0x01, 0x11, 0x01, 0x46, 0x01, 0x4d, 0x01, 0x37, 0x00, 0xf4, 0x00, 0xf5,\n\t0x00, 0xf6, 0x00, 0xf7, 0x00, 0xf8, 0x01, 0x73, 0x00, 0xfa, 0x00, 0xfb,\n\t0x00, 0xfc, 0x01, 0x69, 0x01, 0x6b, 0x02, 0xd9\n};\n"
  },
  {
    "path": "package/libs/libiconv/src/include/charmaps/iso-8859-5.h",
    "content": "static const unsigned char map_iso_8859_5[] = {\n\t0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x81, 0x00, 0x82, 0x00, 0x83,\n\t0x00, 0x84, 0x00, 0x85, 0x00, 0x86, 0x00, 0x87, 0x00, 0x88, 0x00, 0x89,\n\t0x00, 0x8a, 0x00, 0x8b, 0x00, 0x8c, 0x00, 0x8d, 0x00, 0x8e, 0x00, 0x8f,\n\t0x00, 0x90, 0x00, 0x91, 0x00, 0x92, 0x00, 0x93, 0x00, 0x94, 0x00, 0x95,\n\t0x00, 0x96, 0x00, 0x97, 0x00, 0x98, 0x00, 0x99, 0x00, 0x9a, 0x00, 0x9b,\n\t0x00, 0x9c, 0x00, 0x9d, 0x00, 0x9e, 0x00, 0x9f, 0x00, 0xa0, 0x04, 0x01,\n\t0x04, 0x02, 0x04, 0x03, 0x04, 0x04, 0x04, 0x05, 0x04, 0x06, 0x04, 0x07,\n\t0x04, 0x08, 0x04, 0x09, 0x04, 0x0a, 0x04, 0x0b, 0x04, 0x0c, 0x00, 0xad,\n\t0x04, 0x0e, 0x04, 0x0f, 0x04, 0x10, 0x04, 0x11, 0x04, 0x12, 0x04, 0x13,\n\t0x04, 0x14, 0x04, 0x15, 0x04, 0x16, 0x04, 0x17, 0x04, 0x18, 0x04, 0x19,\n\t0x04, 0x1a, 0x04, 0x1b, 0x04, 0x1c, 0x04, 0x1d, 0x04, 0x1e, 0x04, 0x1f,\n\t0x04, 0x20, 0x04, 0x21, 0x04, 0x22, 0x04, 0x23, 0x04, 0x24, 0x04, 0x25,\n\t0x04, 0x26, 0x04, 0x27, 0x04, 0x28, 0x04, 0x29, 0x04, 0x2a, 0x04, 0x2b,\n\t0x04, 0x2c, 0x04, 0x2d, 0x04, 0x2e, 0x04, 0x2f, 0x04, 0x30, 0x04, 0x31,\n\t0x04, 0x32, 0x04, 0x33, 0x04, 0x34, 0x04, 0x35, 0x04, 0x36, 0x04, 0x37,\n\t0x04, 0x38, 0x04, 0x39, 0x04, 0x3a, 0x04, 0x3b, 0x04, 0x3c, 0x04, 0x3d,\n\t0x04, 0x3e, 0x04, 0x3f, 0x04, 0x40, 0x04, 0x41, 0x04, 0x42, 0x04, 0x43,\n\t0x04, 0x44, 0x04, 0x45, 0x04, 0x46, 0x04, 0x47, 0x04, 0x48, 0x04, 0x49,\n\t0x04, 0x4a, 0x04, 0x4b, 0x04, 0x4c, 0x04, 0x4d, 0x04, 0x4e, 0x04, 0x4f,\n\t0x21, 0x16, 0x04, 0x51, 0x04, 0x52, 0x04, 0x53, 0x04, 0x54, 0x04, 0x55,\n\t0x04, 0x56, 0x04, 0x57, 0x04, 0x58, 0x04, 0x59, 0x04, 0x5a, 0x04, 0x5b,\n\t0x04, 0x5c, 0x00, 0xa7, 0x04, 0x5e, 0x04, 0x5f\n};\n"
  },
  {
    "path": "package/libs/libiconv/src/include/charmaps/iso-8859-6.h",
    "content": "static const unsigned char map_iso_8859_6[] = {\n\t0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x81, 0x00, 0x82, 0x00, 0x83,\n\t0x00, 0x84, 0x00, 0x85, 0x00, 0x86, 0x00, 0x87, 0x00, 0x88, 0x00, 0x89,\n\t0x00, 0x8a, 0x00, 0x8b, 0x00, 0x8c, 0x00, 0x8d, 0x00, 0x8e, 0x00, 0x8f,\n\t0x00, 0x90, 0x00, 0x91, 0x00, 0x92, 0x00, 0x93, 0x00, 0x94, 0x00, 0x95,\n\t0x00, 0x96, 0x00, 0x97, 0x00, 0x98, 0x00, 0x99, 0x00, 0x9a, 0x00, 0x9b,\n\t0x00, 0x9c, 0x00, 0x9d, 0x00, 0x9e, 0x00, 0x9f, 0x00, 0xa0, 0xff, 0xff,\n\t0xff, 0xff, 0xff, 0xff, 0x00, 0xa4, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x06, 0x0c, 0x00, 0xad,\n\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n\t0xff, 0xff, 0x06, 0x1b, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x06, 0x1f,\n\t0xff, 0xff, 0x06, 0x21, 0x06, 0x22, 0x06, 0x23, 0x06, 0x24, 0x06, 0x25,\n\t0x06, 0x26, 0x06, 0x27, 0x06, 0x28, 0x06, 0x29, 0x06, 0x2a, 0x06, 0x2b,\n\t0x06, 0x2c, 0x06, 0x2d, 0x06, 0x2e, 0x06, 0x2f, 0x06, 0x30, 0x06, 0x31,\n\t0x06, 0x32, 0x06, 0x33, 0x06, 0x34, 0x06, 0x35, 0x06, 0x36, 0x06, 0x37,\n\t0x06, 0x38, 0x06, 0x39, 0x06, 0x3a, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n\t0xff, 0xff, 0xff, 0xff, 0x06, 0x40, 0x06, 0x41, 0x06, 0x42, 0x06, 0x43,\n\t0x06, 0x44, 0x06, 0x45, 0x06, 0x46, 0x06, 0x47, 0x06, 0x48, 0x06, 0x49,\n\t0x06, 0x4a, 0x06, 0x4b, 0x06, 0x4c, 0x06, 0x4d, 0x06, 0x4e, 0x06, 0x4f,\n\t0x06, 0x50, 0x06, 0x51, 0x06, 0x52, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff\n};\n"
  },
  {
    "path": "package/libs/libiconv/src/include/charmaps/iso-8859-7.h",
    "content": "static const unsigned char map_iso_8859_7[] = {\n\t0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x81, 0x00, 0x82, 0x00, 0x83,\n\t0x00, 0x84, 0x00, 0x85, 0x00, 0x86, 0x00, 0x87, 0x00, 0x88, 0x00, 0x89,\n\t0x00, 0x8a, 0x00, 0x8b, 0x00, 0x8c, 0x00, 0x8d, 0x00, 0x8e, 0x00, 0x8f,\n\t0x00, 0x90, 0x00, 0x91, 0x00, 0x92, 0x00, 0x93, 0x00, 0x94, 0x00, 0x95,\n\t0x00, 0x96, 0x00, 0x97, 0x00, 0x98, 0x00, 0x99, 0x00, 0x9a, 0x00, 0x9b,\n\t0x00, 0x9c, 0x00, 0x9d, 0x00, 0x9e, 0x00, 0x9f, 0x00, 0xa0, 0x20, 0x18,\n\t0x20, 0x19, 0x00, 0xa3, 0x20, 0xac, 0x20, 0xaf, 0x00, 0xa6, 0x00, 0xa7,\n\t0x00, 0xa8, 0x00, 0xa9, 0x03, 0x7a, 0x00, 0xab, 0x00, 0xac, 0x00, 0xad,\n\t0xff, 0xff, 0x20, 0x15, 0x00, 0xb0, 0x00, 0xb1, 0x00, 0xb2, 0x00, 0xb3,\n\t0x03, 0x84, 0x03, 0x85, 0x03, 0x86, 0x00, 0xb7, 0x03, 0x88, 0x03, 0x89,\n\t0x03, 0x8a, 0x00, 0xbb, 0x03, 0x8c, 0x00, 0xbd, 0x03, 0x8e, 0x03, 0x8f,\n\t0x03, 0x90, 0x03, 0x91, 0x03, 0x92, 0x03, 0x93, 0x03, 0x94, 0x03, 0x95,\n\t0x03, 0x96, 0x03, 0x97, 0x03, 0x98, 0x03, 0x99, 0x03, 0x9a, 0x03, 0x9b,\n\t0x03, 0x9c, 0x03, 0x9d, 0x03, 0x9e, 0x03, 0x9f, 0x03, 0xa0, 0x03, 0xa1,\n\t0xff, 0xff, 0x03, 0xa3, 0x03, 0xa4, 0x03, 0xa5, 0x03, 0xa6, 0x03, 0xa7,\n\t0x03, 0xa8, 0x03, 0xa9, 0x03, 0xaa, 0x03, 0xab, 0x03, 0xac, 0x03, 0xad,\n\t0x03, 0xae, 0x03, 0xaf, 0x03, 0xb0, 0x03, 0xb1, 0x03, 0xb2, 0x03, 0xb3,\n\t0x03, 0xb4, 0x03, 0xb5, 0x03, 0xb6, 0x03, 0xb7, 0x03, 0xb8, 0x03, 0xb9,\n\t0x03, 0xba, 0x03, 0xbb, 0x03, 0xbc, 0x03, 0xbd, 0x03, 0xbe, 0x03, 0xbf,\n\t0x03, 0xc0, 0x03, 0xc1, 0x03, 0xc2, 0x03, 0xc3, 0x03, 0xc4, 0x03, 0xc5,\n\t0x03, 0xc6, 0x03, 0xc7, 0x03, 0xc8, 0x03, 0xc9, 0x03, 0xca, 0x03, 0xcb,\n\t0x03, 0xcc, 0x03, 0xcd, 0x03, 0xce, 0xff, 0xff\n};\n"
  },
  {
    "path": "package/libs/libiconv/src/include/charmaps/iso-8859-8.h",
    "content": "static const unsigned char map_iso_8859_8[] = {\n\t0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x81, 0x00, 0x82, 0x00, 0x83,\n\t0x00, 0x84, 0x00, 0x85, 0x00, 0x86, 0x00, 0x87, 0x00, 0x88, 0x00, 0x89,\n\t0x00, 0x8a, 0x00, 0x8b, 0x00, 0x8c, 0x00, 0x8d, 0x00, 0x8e, 0x00, 0x8f,\n\t0x00, 0x90, 0x00, 0x91, 0x00, 0x92, 0x00, 0x93, 0x00, 0x94, 0x00, 0x95,\n\t0x00, 0x96, 0x00, 0x97, 0x00, 0x98, 0x00, 0x99, 0x00, 0x9a, 0x00, 0x9b,\n\t0x00, 0x9c, 0x00, 0x9d, 0x00, 0x9e, 0x00, 0x9f, 0x00, 0xa0, 0xff, 0xff,\n\t0x00, 0xa2, 0x00, 0xa3, 0x00, 0xa4, 0x00, 0xa5, 0x00, 0xa6, 0x00, 0xa7,\n\t0x00, 0xa8, 0x00, 0xa9, 0x00, 0xd7, 0x00, 0xab, 0x00, 0xac, 0x00, 0xad,\n\t0x00, 0xae, 0x00, 0xaf, 0x00, 0xb0, 0x00, 0xb1, 0x00, 0xb2, 0x00, 0xb3,\n\t0x00, 0xb4, 0x00, 0xb5, 0x00, 0xb6, 0x00, 0xb7, 0x00, 0xb8, 0x00, 0xb9,\n\t0x00, 0xf7, 0x00, 0xbb, 0x00, 0xbc, 0x00, 0xbd, 0x00, 0xbe, 0xff, 0xff,\n\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n\t0xff, 0xff, 0x20, 0x17, 0x05, 0xd0, 0x05, 0xd1, 0x05, 0xd2, 0x05, 0xd3,\n\t0x05, 0xd4, 0x05, 0xd5, 0x05, 0xd6, 0x05, 0xd7, 0x05, 0xd8, 0x05, 0xd9,\n\t0x05, 0xda, 0x05, 0xdb, 0x05, 0xdc, 0x05, 0xdd, 0x05, 0xde, 0x05, 0xdf,\n\t0x05, 0xe0, 0x05, 0xe1, 0x05, 0xe2, 0x05, 0xe3, 0x05, 0xe4, 0x05, 0xe5,\n\t0x05, 0xe6, 0x05, 0xe7, 0x05, 0xe8, 0x05, 0xe9, 0x05, 0xea, 0xff, 0xff,\n\t0xff, 0xff, 0x20, 0x0e, 0x20, 0x0f, 0xff, 0xff\n};\n"
  },
  {
    "path": "package/libs/libiconv/src/include/charmaps/iso-8859-9.h",
    "content": "static const unsigned char map_iso_8859_9[] = {\n\t0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x81, 0x00, 0x82, 0x00, 0x83,\n\t0x00, 0x84, 0x00, 0x85, 0x00, 0x86, 0x00, 0x87, 0x00, 0x88, 0x00, 0x89,\n\t0x00, 0x8a, 0x00, 0x8b, 0x00, 0x8c, 0x00, 0x8d, 0x00, 0x8e, 0x00, 0x8f,\n\t0x00, 0x90, 0x00, 0x91, 0x00, 0x92, 0x00, 0x93, 0x00, 0x94, 0x00, 0x95,\n\t0x00, 0x96, 0x00, 0x97, 0x00, 0x98, 0x00, 0x99, 0x00, 0x9a, 0x00, 0x9b,\n\t0x00, 0x9c, 0x00, 0x9d, 0x00, 0x9e, 0x00, 0x9f, 0x00, 0xa0, 0x00, 0xa1,\n\t0x00, 0xa2, 0x00, 0xa3, 0x00, 0xa4, 0x00, 0xa5, 0x00, 0xa6, 0x00, 0xa7,\n\t0x00, 0xa8, 0x00, 0xa9, 0x00, 0xaa, 0x00, 0xab, 0x00, 0xac, 0x00, 0xad,\n\t0x00, 0xae, 0x00, 0xaf, 0x00, 0xb0, 0x00, 0xb1, 0x00, 0xb2, 0x00, 0xb3,\n\t0x00, 0xb4, 0x00, 0xb5, 0x00, 0xb6, 0x00, 0xb7, 0x00, 0xb8, 0x00, 0xb9,\n\t0x00, 0xba, 0x00, 0xbb, 0x00, 0xbc, 0x00, 0xbd, 0x00, 0xbe, 0x00, 0xbf,\n\t0x00, 0xc0, 0x00, 0xc1, 0x00, 0xc2, 0x00, 0xc3, 0x00, 0xc4, 0x00, 0xc5,\n\t0x00, 0xc6, 0x00, 0xc7, 0x00, 0xc8, 0x00, 0xc9, 0x00, 0xca, 0x00, 0xcb,\n\t0x00, 0xcc, 0x00, 0xcd, 0x00, 0xce, 0x00, 0xcf, 0x01, 0x1e, 0x00, 0xd1,\n\t0x00, 0xd2, 0x00, 0xd3, 0x00, 0xd4, 0x00, 0xd5, 0x00, 0xd6, 0x00, 0xd7,\n\t0x00, 0xd8, 0x00, 0xd9, 0x00, 0xda, 0x00, 0xdb, 0x00, 0xdc, 0x01, 0x30,\n\t0x01, 0x5e, 0x00, 0xdf, 0x00, 0xe0, 0x00, 0xe1, 0x00, 0xe2, 0x00, 0xe3,\n\t0x00, 0xe4, 0x00, 0xe5, 0x00, 0xe6, 0x00, 0xe7, 0x00, 0xe8, 0x00, 0xe9,\n\t0x00, 0xea, 0x00, 0xeb, 0x00, 0xec, 0x00, 0xed, 0x00, 0xee, 0x00, 0xef,\n\t0x01, 0x1f, 0x00, 0xf1, 0x00, 0xf2, 0x00, 0xf3, 0x00, 0xf4, 0x00, 0xf5,\n\t0x00, 0xf6, 0x00, 0xf7, 0x00, 0xf8, 0x00, 0xf9, 0x00, 0xfa, 0x00, 0xfb,\n\t0x00, 0xfc, 0x01, 0x31, 0x01, 0x5f, 0x00, 0xff\n};\n"
  },
  {
    "path": "package/libs/libiconv/src/include/charmaps/koi8-r.h",
    "content": "static const unsigned char map_koi8_r[] = {\n\t0x00, 0x00, 0x00, 0x00, 0x25, 0x00, 0x25, 0x02, 0x25, 0x0c, 0x25, 0x10,\n\t0x25, 0x14, 0x25, 0x18, 0x25, 0x1c, 0x25, 0x24, 0x25, 0x2c, 0x25, 0x34,\n\t0x25, 0x3c, 0x25, 0x80, 0x25, 0x84, 0x25, 0x88, 0x25, 0x8c, 0x25, 0x90,\n\t0x25, 0x91, 0x25, 0x92, 0x25, 0x93, 0x23, 0x20, 0x25, 0xa0, 0x22, 0x19,\n\t0x22, 0x1a, 0x22, 0x48, 0x22, 0x64, 0x22, 0x65, 0x00, 0xa0, 0x23, 0x21,\n\t0x00, 0xb0, 0x00, 0xb2, 0x00, 0xb7, 0x00, 0xf7, 0x25, 0x50, 0x25, 0x51,\n\t0x25, 0x52, 0x04, 0x51, 0x25, 0x53, 0x25, 0x54, 0x25, 0x55, 0x25, 0x56,\n\t0x25, 0x57, 0x25, 0x58, 0x25, 0x59, 0x25, 0x5a, 0x25, 0x5b, 0x25, 0x5c,\n\t0x25, 0x5d, 0x25, 0x5e, 0x25, 0x5f, 0x25, 0x60, 0x25, 0x61, 0x04, 0x01,\n\t0x25, 0x62, 0x25, 0x63, 0x25, 0x64, 0x25, 0x65, 0x25, 0x66, 0x25, 0x67,\n\t0x25, 0x68, 0x25, 0x69, 0x25, 0x6a, 0x25, 0x6b, 0x25, 0x6c, 0x00, 0xa9,\n\t0x04, 0x4e, 0x04, 0x30, 0x04, 0x31, 0x04, 0x46, 0x04, 0x34, 0x04, 0x35,\n\t0x04, 0x44, 0x04, 0x33, 0x04, 0x45, 0x04, 0x38, 0x04, 0x39, 0x04, 0x3a,\n\t0x04, 0x3b, 0x04, 0x3c, 0x04, 0x3d, 0x04, 0x3e, 0x04, 0x3f, 0x04, 0x4f,\n\t0x04, 0x40, 0x04, 0x41, 0x04, 0x42, 0x04, 0x43, 0x04, 0x36, 0x04, 0x32,\n\t0x04, 0x4c, 0x04, 0x4b, 0x04, 0x37, 0x04, 0x48, 0x04, 0x4d, 0x04, 0x49,\n\t0x04, 0x47, 0x04, 0x4a, 0x04, 0x2e, 0x04, 0x10, 0x04, 0x11, 0x04, 0x26,\n\t0x04, 0x14, 0x04, 0x15, 0x04, 0x24, 0x04, 0x13, 0x04, 0x25, 0x04, 0x18,\n\t0x04, 0x19, 0x04, 0x1a, 0x04, 0x1b, 0x04, 0x1c, 0x04, 0x1d, 0x04, 0x1e,\n\t0x04, 0x1f, 0x04, 0x2f, 0x04, 0x20, 0x04, 0x21, 0x04, 0x22, 0x04, 0x23,\n\t0x04, 0x16, 0x04, 0x12, 0x04, 0x2c, 0x04, 0x2b, 0x04, 0x17, 0x04, 0x28,\n\t0x04, 0x2d, 0x04, 0x29, 0x04, 0x27, 0x04, 0x2a\n};\n"
  },
  {
    "path": "package/libs/libiconv/src/include/charmaps/windows-1250.h",
    "content": "static const unsigned char map_windows_1250[] = {\n\t0x00, 0x00, 0x00, 0x00, 0x20, 0xac, 0xff, 0xff, 0x20, 0x1a, 0xff, 0xff,\n\t0x20, 0x1e, 0x20, 0x26, 0x20, 0x20, 0x20, 0x21, 0xff, 0xff, 0x20, 0x30,\n\t0x01, 0x60, 0x20, 0x39, 0x01, 0x5a, 0x01, 0x64, 0x01, 0x7d, 0x01, 0x79,\n\t0xff, 0xff, 0x20, 0x18, 0x20, 0x19, 0x20, 0x1c, 0x20, 0x1d, 0x20, 0x22,\n\t0x20, 0x13, 0x20, 0x14, 0xff, 0xff, 0x21, 0x22, 0x01, 0x61, 0x20, 0x3a,\n\t0x01, 0x5b, 0x01, 0x65, 0x01, 0x7e, 0x01, 0x7a, 0x00, 0xa0, 0x02, 0xc7,\n\t0x02, 0xd8, 0x01, 0x41, 0x00, 0xa4, 0x01, 0x04, 0x00, 0xa6, 0x00, 0xa7,\n\t0x00, 0xa8, 0x00, 0xa9, 0x01, 0x5e, 0x00, 0xab, 0x00, 0xac, 0x00, 0xad,\n\t0x00, 0xae, 0x01, 0x7b, 0x00, 0xb0, 0x00, 0xb1, 0x02, 0xdb, 0x01, 0x42,\n\t0x00, 0xb4, 0x00, 0xb5, 0x00, 0xb6, 0x00, 0xb7, 0x00, 0xb8, 0x01, 0x05,\n\t0x01, 0x5f, 0x00, 0xbb, 0x01, 0x3d, 0x02, 0xdd, 0x01, 0x3e, 0x01, 0x7c,\n\t0x01, 0x54, 0x00, 0xc1, 0x00, 0xc2, 0x01, 0x02, 0x00, 0xc4, 0x01, 0x39,\n\t0x01, 0x06, 0x00, 0xc7, 0x01, 0x0c, 0x00, 0xc9, 0x01, 0x18, 0x00, 0xcb,\n\t0x01, 0x1a, 0x00, 0xcd, 0x00, 0xce, 0x01, 0x0e, 0x01, 0x10, 0x01, 0x43,\n\t0x01, 0x47, 0x00, 0xd3, 0x00, 0xd4, 0x01, 0x50, 0x00, 0xd6, 0x00, 0xd7,\n\t0x01, 0x58, 0x01, 0x6e, 0x00, 0xda, 0x01, 0x70, 0x00, 0xdc, 0x00, 0xdd,\n\t0x01, 0x62, 0x00, 0xdf, 0x01, 0x55, 0x00, 0xe1, 0x00, 0xe2, 0x01, 0x03,\n\t0x00, 0xe4, 0x01, 0x3a, 0x01, 0x07, 0x00, 0xe7, 0x01, 0x0d, 0x00, 0xe9,\n\t0x01, 0x19, 0x00, 0xeb, 0x01, 0x1b, 0x00, 0xed, 0x00, 0xee, 0x01, 0x0f,\n\t0x01, 0x11, 0x01, 0x44, 0x01, 0x48, 0x00, 0xf3, 0x00, 0xf4, 0x01, 0x51,\n\t0x00, 0xf6, 0x00, 0xf7, 0x01, 0x59, 0x01, 0x6f, 0x00, 0xfa, 0x01, 0x71,\n\t0x00, 0xfc, 0x00, 0xfd, 0x01, 0x63, 0x02, 0xd9\n};\n"
  },
  {
    "path": "package/libs/libiconv/src/include/charmaps/windows-1251.h",
    "content": "static const unsigned char map_windows_1251[] = {\n\t0x00, 0x00, 0x00, 0x00, 0x04, 0x02, 0x04, 0x03, 0x20, 0x1a, 0x04, 0x53,\n\t0x20, 0x1e, 0x20, 0x26, 0x20, 0x20, 0x20, 0x21, 0x20, 0xac, 0x20, 0x30,\n\t0x04, 0x09, 0x20, 0x39, 0x04, 0x0a, 0x04, 0x0c, 0x04, 0x0b, 0x04, 0x0f,\n\t0x04, 0x52, 0x20, 0x18, 0x20, 0x19, 0x20, 0x1c, 0x20, 0x1d, 0x20, 0x22,\n\t0x20, 0x13, 0x20, 0x14, 0xff, 0xff, 0x21, 0x22, 0x04, 0x59, 0x20, 0x3a,\n\t0x04, 0x5a, 0x04, 0x5c, 0x04, 0x5b, 0x04, 0x5f, 0x00, 0xa0, 0x04, 0x0e,\n\t0x04, 0x5e, 0x04, 0x08, 0x00, 0xa4, 0x04, 0x90, 0x00, 0xa6, 0x00, 0xa7,\n\t0x04, 0x01, 0x00, 0xa9, 0x04, 0x04, 0x00, 0xab, 0x00, 0xac, 0x00, 0xad,\n\t0x00, 0xae, 0x04, 0x07, 0x00, 0xb0, 0x00, 0xb1, 0x04, 0x06, 0x04, 0x56,\n\t0x04, 0x91, 0x00, 0xb5, 0x00, 0xb6, 0x00, 0xb7, 0x04, 0x51, 0x21, 0x16,\n\t0x04, 0x54, 0x00, 0xbb, 0x04, 0x58, 0x04, 0x05, 0x04, 0x55, 0x04, 0x57,\n\t0x04, 0x10, 0x04, 0x11, 0x04, 0x12, 0x04, 0x13, 0x04, 0x14, 0x04, 0x15,\n\t0x04, 0x16, 0x04, 0x17, 0x04, 0x18, 0x04, 0x19, 0x04, 0x1a, 0x04, 0x1b,\n\t0x04, 0x1c, 0x04, 0x1d, 0x04, 0x1e, 0x04, 0x1f, 0x04, 0x20, 0x04, 0x21,\n\t0x04, 0x22, 0x04, 0x23, 0x04, 0x24, 0x04, 0x25, 0x04, 0x26, 0x04, 0x27,\n\t0x04, 0x28, 0x04, 0x29, 0x04, 0x2a, 0x04, 0x2b, 0x04, 0x2c, 0x04, 0x2d,\n\t0x04, 0x2e, 0x04, 0x2f, 0x04, 0x30, 0x04, 0x31, 0x04, 0x32, 0x04, 0x33,\n\t0x04, 0x34, 0x04, 0x35, 0x04, 0x36, 0x04, 0x37, 0x04, 0x38, 0x04, 0x39,\n\t0x04, 0x3a, 0x04, 0x3b, 0x04, 0x3c, 0x04, 0x3d, 0x04, 0x3e, 0x04, 0x3f,\n\t0x04, 0x40, 0x04, 0x41, 0x04, 0x42, 0x04, 0x43, 0x04, 0x44, 0x04, 0x45,\n\t0x04, 0x46, 0x04, 0x47, 0x04, 0x48, 0x04, 0x49, 0x04, 0x4a, 0x04, 0x4b,\n\t0x04, 0x4c, 0x04, 0x4d, 0x04, 0x4e, 0x04, 0x4f\n};\n"
  },
  {
    "path": "package/libs/libiconv/src/include/charmaps/windows-1252.h",
    "content": "static const unsigned char map_windows_1252[] = {\n\t0x00, 0x00, 0x00, 0x00, 0x20, 0xac, 0xff, 0xff, 0x20, 0x1a, 0x01, 0x92,\n\t0x20, 0x1e, 0x20, 0x26, 0x20, 0x20, 0x20, 0x21, 0x02, 0xc6, 0x20, 0x30,\n\t0x01, 0x60, 0x20, 0x39, 0x01, 0x52, 0xff, 0xff, 0x01, 0x7d, 0xff, 0xff,\n\t0xff, 0xff, 0x20, 0x18, 0x20, 0x19, 0x20, 0x1c, 0x20, 0x1d, 0x20, 0x22,\n\t0x20, 0x13, 0x20, 0x14, 0x02, 0xdc, 0x21, 0x22, 0x01, 0x61, 0x20, 0x3a,\n\t0x01, 0x53, 0xff, 0xff, 0x01, 0x7e, 0x01, 0x78, 0x00, 0xa0, 0x00, 0xa1,\n\t0x00, 0xa2, 0x00, 0xa3, 0x00, 0xa4, 0x00, 0xa5, 0x00, 0xa6, 0x00, 0xa7,\n\t0x00, 0xa8, 0x00, 0xa9, 0x00, 0xaa, 0x00, 0xab, 0x00, 0xac, 0x00, 0xad,\n\t0x00, 0xae, 0x00, 0xaf, 0x00, 0xb0, 0x00, 0xb1, 0x00, 0xb2, 0x00, 0xb3,\n\t0x00, 0xb4, 0x00, 0xb5, 0x00, 0xb6, 0x00, 0xb7, 0x00, 0xb8, 0x00, 0xb9,\n\t0x00, 0xba, 0x00, 0xbb, 0x00, 0xbc, 0x00, 0xbd, 0x00, 0xbe, 0x00, 0xbf,\n\t0x00, 0xc0, 0x00, 0xc1, 0x00, 0xc2, 0x00, 0xc3, 0x00, 0xc4, 0x00, 0xc5,\n\t0x00, 0xc6, 0x00, 0xc7, 0x00, 0xc8, 0x00, 0xc9, 0x00, 0xca, 0x00, 0xcb,\n\t0x00, 0xcc, 0x00, 0xcd, 0x00, 0xce, 0x00, 0xcf, 0x00, 0xd0, 0x00, 0xd1,\n\t0x00, 0xd2, 0x00, 0xd3, 0x00, 0xd4, 0x00, 0xd5, 0x00, 0xd6, 0x00, 0xd7,\n\t0x00, 0xd8, 0x00, 0xd9, 0x00, 0xda, 0x00, 0xdb, 0x00, 0xdc, 0x00, 0xdd,\n\t0x00, 0xde, 0x00, 0xdf, 0x00, 0xe0, 0x00, 0xe1, 0x00, 0xe2, 0x00, 0xe3,\n\t0x00, 0xe4, 0x00, 0xe5, 0x00, 0xe6, 0x00, 0xe7, 0x00, 0xe8, 0x00, 0xe9,\n\t0x00, 0xea, 0x00, 0xeb, 0x00, 0xec, 0x00, 0xed, 0x00, 0xee, 0x00, 0xef,\n\t0x00, 0xf0, 0x00, 0xf1, 0x00, 0xf2, 0x00, 0xf3, 0x00, 0xf4, 0x00, 0xf5,\n\t0x00, 0xf6, 0x00, 0xf7, 0x00, 0xf8, 0x00, 0xf9, 0x00, 0xfa, 0x00, 0xfb,\n\t0x00, 0xfc, 0x00, 0xfd, 0x00, 0xfe, 0x00, 0xff\n};\n\n"
  },
  {
    "path": "package/libs/libiconv/src/include/charmaps/windows-1253.h",
    "content": "static const unsigned char map_windows_1253[] = {\n\t0x00, 0x00, 0x00, 0x00, 0x20, 0xac, 0xff, 0xff, 0x20, 0x1a, 0x01, 0x92,\n\t0x20, 0x1e, 0x20, 0x26, 0x20, 0x20, 0x20, 0x21, 0xff, 0xff, 0x20, 0x30,\n\t0xff, 0xff, 0x20, 0x39, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n\t0xff, 0xff, 0x20, 0x18, 0x20, 0x19, 0x20, 0x1c, 0x20, 0x1d, 0x20, 0x22,\n\t0x20, 0x13, 0x20, 0x14, 0xff, 0xff, 0x21, 0x22, 0xff, 0xff, 0x20, 0x3a,\n\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0xa0, 0x03, 0x85,\n\t0x03, 0x86, 0x00, 0xa3, 0x00, 0xa4, 0x00, 0xa5, 0x00, 0xa6, 0x00, 0xa7,\n\t0x00, 0xa8, 0x00, 0xa9, 0xff, 0xff, 0x00, 0xab, 0x00, 0xac, 0x00, 0xad,\n\t0x00, 0xae, 0x20, 0x15, 0x00, 0xb0, 0x00, 0xb1, 0x00, 0xb2, 0x00, 0xb3,\n\t0x03, 0x84, 0x00, 0xb5, 0x00, 0xb6, 0x00, 0xb7, 0x03, 0x88, 0x03, 0x89,\n\t0x03, 0x8a, 0x00, 0xbb, 0x03, 0x8c, 0x00, 0xbd, 0x03, 0x8e, 0x03, 0x8f,\n\t0x03, 0x90, 0x03, 0x91, 0x03, 0x92, 0x03, 0x93, 0x03, 0x94, 0x03, 0x95,\n\t0x03, 0x96, 0x03, 0x97, 0x03, 0x98, 0x03, 0x99, 0x03, 0x9a, 0x03, 0x9b,\n\t0x03, 0x9c, 0x03, 0x9d, 0x03, 0x9e, 0x03, 0x9f, 0x03, 0xa0, 0x03, 0xa1,\n\t0xff, 0xff, 0x03, 0xa3, 0x03, 0xa4, 0x03, 0xa5, 0x03, 0xa6, 0x03, 0xa7,\n\t0x03, 0xa8, 0x03, 0xa9, 0x03, 0xaa, 0x03, 0xab, 0x03, 0xac, 0x03, 0xad,\n\t0x03, 0xae, 0x03, 0xaf, 0x03, 0xb0, 0x03, 0xb1, 0x03, 0xb2, 0x03, 0xb3,\n\t0x03, 0xb4, 0x03, 0xb5, 0x03, 0xb6, 0x03, 0xb7, 0x03, 0xb8, 0x03, 0xb9,\n\t0x03, 0xba, 0x03, 0xbb, 0x03, 0xbc, 0x03, 0xbd, 0x03, 0xbe, 0x03, 0xbf,\n\t0x03, 0xc0, 0x03, 0xc1, 0x03, 0xc2, 0x03, 0xc3, 0x03, 0xc4, 0x03, 0xc5,\n\t0x03, 0xc6, 0x03, 0xc7, 0x03, 0xc8, 0x03, 0xc9, 0x03, 0xca, 0x03, 0xcb,\n\t0x03, 0xcc, 0x03, 0xcd, 0x03, 0xce, 0xff, 0xff\n};\n"
  },
  {
    "path": "package/libs/libiconv/src/include/charmaps/windows-1254.h",
    "content": "static const unsigned char map_windows_1254[] = {\n\t0x00, 0x00, 0x00, 0x00, 0x20, 0xac, 0xff, 0xff, 0x20, 0x1a, 0x01, 0x92,\n\t0x20, 0x1e, 0x20, 0x26, 0x20, 0x20, 0x20, 0x21, 0x02, 0xc6, 0x20, 0x30,\n\t0x01, 0x60, 0x20, 0x39, 0x01, 0x52, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n\t0xff, 0xff, 0x20, 0x18, 0x20, 0x19, 0x20, 0x1c, 0x20, 0x1d, 0x20, 0x22,\n\t0x20, 0x13, 0x20, 0x14, 0x02, 0xdc, 0x21, 0x22, 0x01, 0x61, 0x20, 0x3a,\n\t0x01, 0x53, 0xff, 0xff, 0xff, 0xff, 0x01, 0x78, 0x00, 0xa0, 0x00, 0xa1,\n\t0x00, 0xa2, 0x00, 0xa3, 0x00, 0xa4, 0x00, 0xa5, 0x00, 0xa6, 0x00, 0xa7,\n\t0x00, 0xa8, 0x00, 0xa9, 0x00, 0xaa, 0x00, 0xab, 0x00, 0xac, 0x00, 0xad,\n\t0x00, 0xae, 0x00, 0xaf, 0x00, 0xb0, 0x00, 0xb1, 0x00, 0xb2, 0x00, 0xb3,\n\t0x00, 0xb4, 0x00, 0xb5, 0x00, 0xb6, 0x00, 0xb7, 0x00, 0xb8, 0x00, 0xb9,\n\t0x00, 0xba, 0x00, 0xbb, 0x00, 0xbc, 0x00, 0xbd, 0x00, 0xbe, 0x00, 0xbf,\n\t0x00, 0xc0, 0x00, 0xc1, 0x00, 0xc2, 0x00, 0xc3, 0x00, 0xc4, 0x00, 0xc5,\n\t0x00, 0xc6, 0x00, 0xc7, 0x00, 0xc8, 0x00, 0xc9, 0x00, 0xca, 0x00, 0xcb,\n\t0x00, 0xcc, 0x00, 0xcd, 0x00, 0xce, 0x00, 0xcf, 0x01, 0x1e, 0x00, 0xd1,\n\t0x00, 0xd2, 0x00, 0xd3, 0x00, 0xd4, 0x00, 0xd5, 0x00, 0xd6, 0x00, 0xd7,\n\t0x00, 0xd8, 0x00, 0xd9, 0x00, 0xda, 0x00, 0xdb, 0x00, 0xdc, 0x01, 0x30,\n\t0x01, 0x5e, 0x00, 0xdf, 0x00, 0xe0, 0x00, 0xe1, 0x00, 0xe2, 0x00, 0xe3,\n\t0x00, 0xe4, 0x00, 0xe5, 0x00, 0xe6, 0x00, 0xe7, 0x00, 0xe8, 0x00, 0xe9,\n\t0x00, 0xea, 0x00, 0xeb, 0x00, 0xec, 0x00, 0xed, 0x00, 0xee, 0x00, 0xef,\n\t0x01, 0x1f, 0x00, 0xf1, 0x00, 0xf2, 0x00, 0xf3, 0x00, 0xf4, 0x00, 0xf5,\n\t0x00, 0xf6, 0x00, 0xf7, 0x00, 0xf8, 0x00, 0xf9, 0x00, 0xfa, 0x00, 0xfb,\n\t0x00, 0xfc, 0x01, 0x31, 0x01, 0x5f, 0x00, 0xff\n};\n"
  },
  {
    "path": "package/libs/libiconv/src/include/charmaps/windows-1255.h",
    "content": "static const unsigned char map_windows_1255[] = {\n\t0x00, 0x00, 0x00, 0x00, 0x20, 0xac, 0xff, 0xff, 0x20, 0x1a, 0x01, 0x92,\n\t0x20, 0x1e, 0x20, 0x26, 0x20, 0x20, 0x20, 0x21, 0x02, 0xc6, 0x20, 0x30,\n\t0xff, 0xff, 0x20, 0x39, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n\t0xff, 0xff, 0x20, 0x18, 0x20, 0x19, 0x20, 0x1c, 0x20, 0x1d, 0x20, 0x22,\n\t0x20, 0x13, 0x20, 0x14, 0x02, 0xdc, 0x21, 0x22, 0xff, 0xff, 0x20, 0x3a,\n\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0xa0, 0x00, 0xa1,\n\t0x00, 0xa2, 0x00, 0xa3, 0x20, 0xaa, 0x00, 0xa5, 0x00, 0xa6, 0x00, 0xa7,\n\t0x00, 0xa8, 0x00, 0xa9, 0x00, 0xd7, 0x00, 0xab, 0x00, 0xac, 0x00, 0xad,\n\t0x00, 0xae, 0x00, 0xaf, 0x00, 0xb0, 0x00, 0xb1, 0x00, 0xb2, 0x00, 0xb3,\n\t0x00, 0xb4, 0x00, 0xb5, 0x00, 0xb6, 0x00, 0xb7, 0x00, 0xb8, 0x00, 0xb9,\n\t0x00, 0xf7, 0x00, 0xbb, 0x00, 0xbc, 0x00, 0xbd, 0x00, 0xbe, 0x00, 0xbf,\n\t0x05, 0xb0, 0x05, 0xb1, 0x05, 0xb2, 0x05, 0xb3, 0x05, 0xb4, 0x05, 0xb5,\n\t0x05, 0xb6, 0x05, 0xb7, 0x05, 0xb8, 0x05, 0xb9, 0xff, 0xff, 0x05, 0xbb,\n\t0x05, 0xbc, 0x05, 0xbd, 0x05, 0xbe, 0x05, 0xbf, 0x05, 0xc0, 0x05, 0xc1,\n\t0x05, 0xc2, 0x05, 0xc3, 0x05, 0xf0, 0x05, 0xf1, 0x05, 0xf2, 0x05, 0xf3,\n\t0x05, 0xf4, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n\t0xff, 0xff, 0xff, 0xff, 0x05, 0xd0, 0x05, 0xd1, 0x05, 0xd2, 0x05, 0xd3,\n\t0x05, 0xd4, 0x05, 0xd5, 0x05, 0xd6, 0x05, 0xd7, 0x05, 0xd8, 0x05, 0xd9,\n\t0x05, 0xda, 0x05, 0xdb, 0x05, 0xdc, 0x05, 0xdd, 0x05, 0xde, 0x05, 0xdf,\n\t0x05, 0xe0, 0x05, 0xe1, 0x05, 0xe2, 0x05, 0xe3, 0x05, 0xe4, 0x05, 0xe5,\n\t0x05, 0xe6, 0x05, 0xe7, 0x05, 0xe8, 0x05, 0xe9, 0x05, 0xea, 0xff, 0xff,\n\t0xff, 0xff, 0x20, 0x0e, 0x20, 0x0f, 0xff, 0xff\n};\n"
  },
  {
    "path": "package/libs/libiconv/src/include/charmaps/windows-1256.h",
    "content": "static const unsigned char map_windows_1256[] = {\n\t0x00, 0x00, 0x00, 0x00, 0x20, 0xac, 0x06, 0x7e, 0x20, 0x1a, 0x01, 0x92,\n\t0x20, 0x1e, 0x20, 0x26, 0x20, 0x20, 0x20, 0x21, 0x02, 0xc6, 0x20, 0x30,\n\t0x06, 0x79, 0x20, 0x39, 0x01, 0x52, 0x06, 0x86, 0x06, 0x98, 0x06, 0x88,\n\t0x06, 0xaf, 0x20, 0x18, 0x20, 0x19, 0x20, 0x1c, 0x20, 0x1d, 0x20, 0x22,\n\t0x20, 0x13, 0x20, 0x14, 0x06, 0xa9, 0x21, 0x22, 0x06, 0x91, 0x20, 0x3a,\n\t0x01, 0x53, 0x20, 0x0c, 0x20, 0x0d, 0x06, 0xba, 0x00, 0xa0, 0x06, 0x0c,\n\t0x00, 0xa2, 0x00, 0xa3, 0x00, 0xa4, 0x00, 0xa5, 0x00, 0xa6, 0x00, 0xa7,\n\t0x00, 0xa8, 0x00, 0xa9, 0x06, 0xbe, 0x00, 0xab, 0x00, 0xac, 0x00, 0xad,\n\t0x00, 0xae, 0x00, 0xaf, 0x00, 0xb0, 0x00, 0xb1, 0x00, 0xb2, 0x00, 0xb3,\n\t0x00, 0xb4, 0x00, 0xb5, 0x00, 0xb6, 0x00, 0xb7, 0x00, 0xb8, 0x00, 0xb9,\n\t0x06, 0x1b, 0x00, 0xbb, 0x00, 0xbc, 0x00, 0xbd, 0x00, 0xbe, 0x06, 0x1f,\n\t0x06, 0xc1, 0x06, 0x21, 0x06, 0x22, 0x06, 0x23, 0x06, 0x24, 0x06, 0x25,\n\t0x06, 0x26, 0x06, 0x27, 0x06, 0x28, 0x06, 0x29, 0x06, 0x2a, 0x06, 0x2b,\n\t0x06, 0x2c, 0x06, 0x2d, 0x06, 0x2e, 0x06, 0x2f, 0x06, 0x30, 0x06, 0x31,\n\t0x06, 0x32, 0x06, 0x33, 0x06, 0x34, 0x06, 0x35, 0x06, 0x36, 0x00, 0xd7,\n\t0x06, 0x37, 0x06, 0x38, 0x06, 0x39, 0x06, 0x3a, 0x06, 0x40, 0x06, 0x41,\n\t0x06, 0x42, 0x06, 0x43, 0x00, 0xe0, 0x06, 0x44, 0x00, 0xe2, 0x06, 0x45,\n\t0x06, 0x46, 0x06, 0x47, 0x06, 0x48, 0x00, 0xe7, 0x00, 0xe8, 0x00, 0xe9,\n\t0x00, 0xea, 0x00, 0xeb, 0x06, 0x49, 0x06, 0x4a, 0x00, 0xee, 0x00, 0xef,\n\t0x06, 0x4b, 0x06, 0x4c, 0x06, 0x4d, 0x06, 0x4e, 0x00, 0xf4, 0x06, 0x4f,\n\t0x06, 0x50, 0x00, 0xf7, 0x06, 0x51, 0x00, 0xf9, 0x06, 0x52, 0x00, 0xfb,\n\t0x00, 0xfc, 0x20, 0x0e, 0x20, 0x0f, 0x06, 0xd2\n};\n"
  },
  {
    "path": "package/libs/libiconv/src/include/charmaps/windows-1257.h",
    "content": "static const unsigned char map_windows_1257[] = {\n\t0x00, 0x00, 0x00, 0x00, 0x20, 0xac, 0xff, 0xff, 0x20, 0x1a, 0xff, 0xff,\n\t0x20, 0x1e, 0x20, 0x26, 0x20, 0x20, 0x20, 0x21, 0xff, 0xff, 0x20, 0x30,\n\t0xff, 0xff, 0x20, 0x39, 0xff, 0xff, 0x00, 0xa8, 0x02, 0xc7, 0x00, 0xb8,\n\t0xff, 0xff, 0x20, 0x18, 0x20, 0x19, 0x20, 0x1c, 0x20, 0x1d, 0x20, 0x22,\n\t0x20, 0x13, 0x20, 0x14, 0xff, 0xff, 0x21, 0x22, 0xff, 0xff, 0x20, 0x3a,\n\t0xff, 0xff, 0x00, 0xaf, 0x02, 0xdb, 0xff, 0xff, 0x00, 0xa0, 0xff, 0xff,\n\t0x00, 0xa2, 0x00, 0xa3, 0x00, 0xa4, 0xff, 0xff, 0x00, 0xa6, 0x00, 0xa7,\n\t0x00, 0xd8, 0x00, 0xa9, 0x01, 0x56, 0x00, 0xab, 0x00, 0xac, 0x00, 0xad,\n\t0x00, 0xae, 0x00, 0xc6, 0x00, 0xb0, 0x00, 0xb1, 0x00, 0xb2, 0x00, 0xb3,\n\t0x00, 0xb4, 0x00, 0xb5, 0x00, 0xb6, 0x00, 0xb7, 0x00, 0xf8, 0x00, 0xb9,\n\t0x01, 0x57, 0x00, 0xbb, 0x00, 0xbc, 0x00, 0xbd, 0x00, 0xbe, 0x00, 0xe6,\n\t0x01, 0x04, 0x01, 0x2e, 0x01, 0x00, 0x01, 0x06, 0x00, 0xc4, 0x00, 0xc5,\n\t0x01, 0x18, 0x01, 0x12, 0x01, 0x0c, 0x00, 0xc9, 0x01, 0x79, 0x01, 0x16,\n\t0x01, 0x22, 0x01, 0x36, 0x01, 0x2a, 0x01, 0x3b, 0x01, 0x60, 0x01, 0x43,\n\t0x01, 0x45, 0x00, 0xd3, 0x01, 0x4c, 0x00, 0xd5, 0x00, 0xd6, 0x00, 0xd7,\n\t0x01, 0x72, 0x01, 0x41, 0x01, 0x5a, 0x01, 0x6a, 0x00, 0xdc, 0x01, 0x7b,\n\t0x01, 0x7d, 0x00, 0xdf, 0x01, 0x05, 0x01, 0x2f, 0x01, 0x01, 0x01, 0x07,\n\t0x00, 0xe4, 0x00, 0xe5, 0x01, 0x19, 0x01, 0x13, 0x01, 0x0d, 0x00, 0xe9,\n\t0x01, 0x7a, 0x01, 0x17, 0x01, 0x23, 0x01, 0x37, 0x01, 0x2b, 0x01, 0x3c,\n\t0x01, 0x61, 0x01, 0x44, 0x01, 0x46, 0x00, 0xf3, 0x01, 0x4d, 0x00, 0xf5,\n\t0x00, 0xf6, 0x00, 0xf7, 0x01, 0x73, 0x01, 0x42, 0x01, 0x5b, 0x01, 0x6b,\n\t0x00, 0xfc, 0x01, 0x7c, 0x01, 0x7e, 0x02, 0xd9\n};\n"
  },
  {
    "path": "package/libs/libiconv/src/include/charmaps/windows-1258.h",
    "content": "static const unsigned char map_windows_1258[] = {\n\t0x00, 0x00, 0x00, 0x00, 0x20, 0xac, 0xff, 0xff, 0x20, 0x1a, 0x01, 0x92,\n\t0x20, 0x1e, 0x20, 0x26, 0x20, 0x20, 0x20, 0x21, 0x02, 0xc6, 0x20, 0x30,\n\t0xff, 0xff, 0x20, 0x39, 0x01, 0x52, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n\t0xff, 0xff, 0x20, 0x18, 0x20, 0x19, 0x20, 0x1c, 0x20, 0x1d, 0x20, 0x22,\n\t0x20, 0x13, 0x20, 0x14, 0x02, 0xdc, 0x21, 0x22, 0xff, 0xff, 0x20, 0x3a,\n\t0x01, 0x53, 0xff, 0xff, 0xff, 0xff, 0x01, 0x78, 0x00, 0xa0, 0x00, 0xa1,\n\t0x00, 0xa2, 0x00, 0xa3, 0x00, 0xa4, 0x00, 0xa5, 0x00, 0xa6, 0x00, 0xa7,\n\t0x00, 0xa8, 0x00, 0xa9, 0x00, 0xaa, 0x00, 0xab, 0x00, 0xac, 0x00, 0xad,\n\t0x00, 0xae, 0x00, 0xaf, 0x00, 0xb0, 0x00, 0xb1, 0x00, 0xb2, 0x00, 0xb3,\n\t0x00, 0xb4, 0x00, 0xb5, 0x00, 0xb6, 0x00, 0xb7, 0x00, 0xb8, 0x00, 0xb9,\n\t0x00, 0xba, 0x00, 0xbb, 0x00, 0xbc, 0x00, 0xbd, 0x00, 0xbe, 0x00, 0xbf,\n\t0x00, 0xc0, 0x00, 0xc1, 0x00, 0xc2, 0x01, 0x02, 0x00, 0xc4, 0x00, 0xc5,\n\t0x00, 0xc6, 0x00, 0xc7, 0x00, 0xc8, 0x00, 0xc9, 0x00, 0xca, 0x00, 0xcb,\n\t0x03, 0x00, 0x00, 0xcd, 0x00, 0xce, 0x00, 0xcf, 0x01, 0x10, 0x00, 0xd1,\n\t0x03, 0x09, 0x00, 0xd3, 0x00, 0xd4, 0x01, 0xa0, 0x00, 0xd6, 0x00, 0xd7,\n\t0x00, 0xd8, 0x00, 0xd9, 0x00, 0xda, 0x00, 0xdb, 0x00, 0xdc, 0x01, 0xaf,\n\t0x03, 0x03, 0x00, 0xdf, 0x00, 0xe0, 0x00, 0xe1, 0x00, 0xe2, 0x01, 0x03,\n\t0x00, 0xe4, 0x00, 0xe5, 0x00, 0xe6, 0x00, 0xe7, 0x00, 0xe8, 0x00, 0xe9,\n\t0x00, 0xea, 0x00, 0xeb, 0x03, 0x01, 0x00, 0xed, 0x00, 0xee, 0x00, 0xef,\n\t0x01, 0x11, 0x00, 0xf1, 0x03, 0x23, 0x00, 0xf3, 0x00, 0xf4, 0x01, 0xa1,\n\t0x00, 0xf6, 0x00, 0xf7, 0x00, 0xf8, 0x00, 0xf9, 0x00, 0xfa, 0x00, 0xfb,\n\t0x00, 0xfc, 0x01, 0xb0, 0x20, 0xab, 0x00, 0xff\n};\n"
  },
  {
    "path": "package/libs/libiconv/src/include/charmaps/windows-874.h",
    "content": "static const unsigned char map_windows_874[] = {\n\t0x00, 0x00, 0x00, 0x00, 0x20, 0xac, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n\t0xff, 0xff, 0x20, 0x26, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n\t0xff, 0xff, 0x20, 0x18, 0x20, 0x19, 0x20, 0x1c, 0x20, 0x1d, 0x20, 0x22,\n\t0x20, 0x13, 0x20, 0x14, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0xa0, 0x0e, 0x01,\n\t0x0e, 0x02, 0x0e, 0x03, 0x0e, 0x04, 0x0e, 0x05, 0x0e, 0x06, 0x0e, 0x07,\n\t0x0e, 0x08, 0x0e, 0x09, 0x0e, 0x0a, 0x0e, 0x0b, 0x0e, 0x0c, 0x0e, 0x0d,\n\t0x0e, 0x0e, 0x0e, 0x0f, 0x0e, 0x10, 0x0e, 0x11, 0x0e, 0x12, 0x0e, 0x13,\n\t0x0e, 0x14, 0x0e, 0x15, 0x0e, 0x16, 0x0e, 0x17, 0x0e, 0x18, 0x0e, 0x19,\n\t0x0e, 0x1a, 0x0e, 0x1b, 0x0e, 0x1c, 0x0e, 0x1d, 0x0e, 0x1e, 0x0e, 0x1f,\n\t0x0e, 0x20, 0x0e, 0x21, 0x0e, 0x22, 0x0e, 0x23, 0x0e, 0x24, 0x0e, 0x25,\n\t0x0e, 0x26, 0x0e, 0x27, 0x0e, 0x28, 0x0e, 0x29, 0x0e, 0x2a, 0x0e, 0x2b,\n\t0x0e, 0x2c, 0x0e, 0x2d, 0x0e, 0x2e, 0x0e, 0x2f, 0x0e, 0x30, 0x0e, 0x31,\n\t0x0e, 0x32, 0x0e, 0x33, 0x0e, 0x34, 0x0e, 0x35, 0x0e, 0x36, 0x0e, 0x37,\n\t0x0e, 0x38, 0x0e, 0x39, 0x0e, 0x3a, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\n\t0xff, 0xff, 0x0e, 0x3f, 0x0e, 0x40, 0x0e, 0x41, 0x0e, 0x42, 0x0e, 0x43,\n\t0x0e, 0x44, 0x0e, 0x45, 0x0e, 0x46, 0x0e, 0x47, 0x0e, 0x48, 0x0e, 0x49,\n\t0x0e, 0x4a, 0x0e, 0x4b, 0x0e, 0x4c, 0x0e, 0x4d, 0x0e, 0x4e, 0x0e, 0x4f,\n\t0x0e, 0x50, 0x0e, 0x51, 0x0e, 0x52, 0x0e, 0x53, 0x0e, 0x54, 0x0e, 0x55,\n\t0x0e, 0x56, 0x0e, 0x57, 0x0e, 0x58, 0x0e, 0x59, 0x0e, 0x5a, 0x0e, 0x5b,\n\t0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff\n};\n"
  },
  {
    "path": "package/libs/libiconv/src/include/charmaps.h",
    "content": "#include \"charmaps/iso-8859-2.h\"\n#include \"charmaps/iso-8859-10.h\"\n#include \"charmaps/windows-874.h\"\n#include \"charmaps/windows-1250.h\"\n#include \"charmaps/koi8-r.h\"\n\n#ifdef ALL_CHARSETS\n#include \"charmaps/iso-8859-3.h\"\n#include \"charmaps/iso-8859-4.h\"\n#include \"charmaps/iso-8859-5.h\"\n#include \"charmaps/iso-8859-6.h\"\n#include \"charmaps/iso-8859-7.h\"\n#include \"charmaps/iso-8859-8.h\"\n#include \"charmaps/iso-8859-9.h\"\n#include \"charmaps/iso-8859-13.h\"\n#include \"charmaps/iso-8859-14.h\"\n#include \"charmaps/iso-8859-16.h\"\n#include \"charmaps/windows-1251.h\"\n#include \"charmaps/windows-1252.h\"\n#include \"charmaps/windows-1253.h\"\n#include \"charmaps/windows-1254.h\"\n#include \"charmaps/windows-1255.h\"\n#include \"charmaps/windows-1256.h\"\n#include \"charmaps/windows-1257.h\"\n#include \"charmaps/windows-1258.h\"\n#endif\n\n\nstruct charmap {\n\tconst char name[13];\n\tconst unsigned char *map;\n};\n\nstatic struct charmap charmaps[] = {\n\t{ \"ISO-8859-2\",   map_iso_8859_2   },\n\t{ \"ISO-8859-10\",  map_iso_8859_10  },\n\n#ifdef ALL_CHARSETS\n\t{ \"ISO-8859-3\",   map_iso_8859_3   },\n\t{ \"ISO-8859-4\",   map_iso_8859_4   },\n\t{ \"ISO-8859-5\",   map_iso_8859_5   },\n\t{ \"ISO-8859-6\",   map_iso_8859_6   },\n\t{ \"ISO-8859-7\",   map_iso_8859_7   },\n\t{ \"ISO-8859-8\",   map_iso_8859_8   },\n\t{ \"ISO-8859-9\",   map_iso_8859_9   },\n\t{ \"ISO-8859-13\",  map_iso_8859_13  },\n\t{ \"ISO-8859-14\",  map_iso_8859_14  },\n\t{ \"ISO-8859-16\",  map_iso_8859_16  },\n#endif\n\n\t{ \"WINDOWS-874\",  map_windows_874  },\n\t{ \"WINDOWS-1250\", map_windows_1250 },\n\n#ifdef ALL_CHARSETS\n\t{ \"WINDOWS-1251\", map_windows_1251 },\n\t{ \"WINDOWS-1252\", map_windows_1252 },\n\t{ \"WINDOWS-1253\", map_windows_1253 },\n\t{ \"WINDOWS-1254\", map_windows_1254 },\n\t{ \"WINDOWS-1255\", map_windows_1255 },\n\t{ \"WINDOWS-1256\", map_windows_1256 },\n\t{ \"WINDOWS-1257\", map_windows_1257 },\n\t{ \"WINDOWS-1258\", map_windows_1258 },\n#endif\n\n\t{ \"KOI8-R\",       map_koi8_r       },\n\n\t/* Aliases */\n\t{ \"LATIN2\",       map_iso_8859_2   },\n\t{ \"LATIN6\",       map_iso_8859_10  },\n\n#ifdef ALL_CHARSETS\n\t{ \"ARABIC\",       map_iso_8859_6   },\n\t{ \"CYRILLIC\",     map_iso_8859_5   },\n\t{ \"GREEK\",        map_iso_8859_7   },\n\t{ \"HEBREW\",       map_iso_8859_8   },\n\t{ \"LATIN3\",       map_iso_8859_3   },\n\t{ \"LATIN4\",       map_iso_8859_4   },\n\t{ \"LATIN5\",       map_iso_8859_9   },\n#endif\n};\n"
  },
  {
    "path": "package/libs/libiconv/src/include/iconv.h",
    "content": "#ifndef _LIBICONV_H\n#define _LIBICONV_H 1\n\n#define _LIBICONV_VERSION 0x010B    /* version number: (major<<8) + minor */\n\n#include <stddef.h>\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\nextern int _libiconv_version; /* Likewise */\n\ntypedef long iconv_t;\n\n#define iconv_open libiconv_open\n#define iconv libiconv\n#define iconv_close libiconv_close\n\nextern iconv_t\niconv_open(const char *tocode, const char *fromcode);\n\nextern size_t\niconv(iconv_t cd, char **inbuf, size_t *inbytesleft,\n                  char **outbuf, size_t *outbytesleft);\n\nextern int\niconv_close(iconv_t cd);\n\n#define libiconv_set_relocation_prefix(...) do {} while(0)\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* _LIBICONV_H */\n"
  },
  {
    "path": "package/libs/libiconv/src/m4/iconv.m4",
    "content": "# iconv.m4 serial 11 (gettext-0.18.1)\ndnl Copyright (C) 2000-2002, 2007-2010 Free Software Foundation, Inc.\ndnl This file is free software; the Free Software Foundation\ndnl gives unlimited permission to copy and/or distribute it,\ndnl with or without modifications, as long as this notice is preserved.\n\ndnl From Bruno Haible.\n\nAC_DEFUN([AM_ICONV_LINKFLAGS_BODY],\n[\n  dnl Prerequisites of AC_LIB_LINKFLAGS_BODY.\n  AC_REQUIRE([AC_LIB_PREPARE_PREFIX])\n  AC_REQUIRE([AC_LIB_RPATH])\n\n  dnl Search for libiconv and define LIBICONV, LTLIBICONV and INCICONV\n  dnl accordingly.\n  AC_LIB_LINKFLAGS_BODY([iconv])\n])\n\nAC_DEFUN([AM_ICONV_LINK],\n[\n  dnl Some systems have iconv in libc, some have it in libiconv (OSF/1 and\n  dnl those with the standalone portable GNU libiconv installed).\n  AC_REQUIRE([AC_CANONICAL_HOST]) dnl for cross-compiles\n\n  dnl Search for libiconv and define LIBICONV, LTLIBICONV and INCICONV\n  dnl accordingly.\n  AC_REQUIRE([AM_ICONV_LINKFLAGS_BODY])\n\n  dnl Add $INCICONV to CPPFLAGS before performing the following checks,\n  dnl because if the user has installed libiconv and not disabled its use\n  dnl via --without-libiconv-prefix, he wants to use it. The first\n  dnl AC_TRY_LINK will then fail, the second AC_TRY_LINK will succeed.\n  am_save_CPPFLAGS=\"$CPPFLAGS\"\n  AC_LIB_APPENDTOVAR([CPPFLAGS], [$INCICONV])\n\n  AC_CACHE_CHECK([for iconv], [am_cv_func_iconv], [\n    am_cv_func_iconv=\"no, consider installing GNU libiconv\"\n    am_cv_lib_iconv=no\n    AC_TRY_LINK([#include <stdlib.h>\n#include <iconv.h>],\n      [iconv_t cd = iconv_open(\"\",\"\");\n       iconv(cd,NULL,NULL,NULL,NULL);\n       iconv_close(cd);],\n      [am_cv_func_iconv=yes])\n    if test \"$am_cv_func_iconv\" != yes; then\n      am_save_LIBS=\"$LIBS\"\n      LIBS=\"$LIBS $LIBICONV\"\n      AC_TRY_LINK([#include <stdlib.h>\n#include <iconv.h>],\n        [iconv_t cd = iconv_open(\"\",\"\");\n         iconv(cd,NULL,NULL,NULL,NULL);\n         iconv_close(cd);],\n        [am_cv_lib_iconv=yes]\n        [am_cv_func_iconv=yes])\n      LIBS=\"$am_save_LIBS\"\n    fi\n  ])\n  if test \"$am_cv_func_iconv\" = yes; then\n    AC_CACHE_CHECK([for working iconv], [am_cv_func_iconv_works], [\n      dnl This tests against bugs in AIX 5.1, HP-UX 11.11, Solaris 10.\n      am_save_LIBS=\"$LIBS\"\n      if test $am_cv_lib_iconv = yes; then\n        LIBS=\"$LIBS $LIBICONV\"\n      fi\n      AC_TRY_RUN([\n#include <iconv.h>\n#include <string.h>\nint main ()\n{\n  /* Test against AIX 5.1 bug: Failures are not distinguishable from successful\n     returns.  */\n  {\n    iconv_t cd_utf8_to_88591 = iconv_open (\"ISO8859-1\", \"UTF-8\");\n    if (cd_utf8_to_88591 != (iconv_t)(-1))\n      {\n        static const char input[] = \"\\342\\202\\254\"; /* EURO SIGN */\n        char buf[10];\n        const char *inptr = input;\n        size_t inbytesleft = strlen (input);\n        char *outptr = buf;\n        size_t outbytesleft = sizeof (buf);\n        size_t res = iconv (cd_utf8_to_88591,\n                            (char **) &inptr, &inbytesleft,\n                            &outptr, &outbytesleft);\n        if (res == 0)\n          return 1;\n      }\n  }\n  /* Test against Solaris 10 bug: Failures are not distinguishable from\n     successful returns.  */\n  {\n    iconv_t cd_ascii_to_88591 = iconv_open (\"ISO8859-1\", \"646\");\n    if (cd_ascii_to_88591 != (iconv_t)(-1))\n      {\n        static const char input[] = \"\\263\";\n        char buf[10];\n        const char *inptr = input;\n        size_t inbytesleft = strlen (input);\n        char *outptr = buf;\n        size_t outbytesleft = sizeof (buf);\n        size_t res = iconv (cd_ascii_to_88591,\n                            (char **) &inptr, &inbytesleft,\n                            &outptr, &outbytesleft);\n        if (res == 0)\n          return 1;\n      }\n  }\n#if 0 /* This bug could be worked around by the caller.  */\n  /* Test against HP-UX 11.11 bug: Positive return value instead of 0.  */\n  {\n    iconv_t cd_88591_to_utf8 = iconv_open (\"utf8\", \"iso88591\");\n    if (cd_88591_to_utf8 != (iconv_t)(-1))\n      {\n        static const char input[] = \"\\304rger mit b\\366sen B\\374bchen ohne Augenma\\337\";\n        char buf[50];\n        const char *inptr = input;\n        size_t inbytesleft = strlen (input);\n        char *outptr = buf;\n        size_t outbytesleft = sizeof (buf);\n        size_t res = iconv (cd_88591_to_utf8,\n                            (char **) &inptr, &inbytesleft,\n                            &outptr, &outbytesleft);\n        if ((int)res > 0)\n          return 1;\n      }\n  }\n#endif\n  /* Test against HP-UX 11.11 bug: No converter from EUC-JP to UTF-8 is\n     provided.  */\n  if (/* Try standardized names.  */\n      iconv_open (\"UTF-8\", \"EUC-JP\") == (iconv_t)(-1)\n      /* Try IRIX, OSF/1 names.  */\n      && iconv_open (\"UTF-8\", \"eucJP\") == (iconv_t)(-1)\n      /* Try AIX names.  */\n      && iconv_open (\"UTF-8\", \"IBM-eucJP\") == (iconv_t)(-1)\n      /* Try HP-UX names.  */\n      && iconv_open (\"utf8\", \"eucJP\") == (iconv_t)(-1))\n    return 1;\n  return 0;\n}], [am_cv_func_iconv_works=yes], [am_cv_func_iconv_works=no],\n        [case \"$host_os\" in\n           aix* | hpux*) am_cv_func_iconv_works=\"guessing no\" ;;\n           *)            am_cv_func_iconv_works=\"guessing yes\" ;;\n         esac])\n      LIBS=\"$am_save_LIBS\"\n    ])\n    case \"$am_cv_func_iconv_works\" in\n      *no) am_func_iconv=no am_cv_lib_iconv=no ;;\n      *)   am_func_iconv=yes ;;\n    esac\n  else\n    am_func_iconv=no am_cv_lib_iconv=no\n  fi\n  if test \"$am_func_iconv\" = yes; then\n    AC_DEFINE([HAVE_ICONV], [1],\n      [Define if you have the iconv() function and it works.])\n  fi\n  if test \"$am_cv_lib_iconv\" = yes; then\n    AC_MSG_CHECKING([how to link with libiconv])\n    AC_MSG_RESULT([$LIBICONV])\n  else\n    dnl If $LIBICONV didn't lead to a usable library, we don't need $INCICONV\n    dnl either.\n    CPPFLAGS=\"$am_save_CPPFLAGS\"\n    LIBICONV=\n    LTLIBICONV=\n  fi\n  AC_SUBST([LIBICONV])\n  AC_SUBST([LTLIBICONV])\n])\n\ndnl Define AM_ICONV using AC_DEFUN_ONCE for Autoconf >= 2.64, in order to\ndnl avoid warnings like\ndnl \"warning: AC_REQUIRE: `AM_ICONV' was expanded before it was required\".\ndnl This is tricky because of the way 'aclocal' is implemented:\ndnl - It requires defining an auxiliary macro whose name ends in AC_DEFUN.\ndnl   Otherwise aclocal's initial scan pass would miss the macro definition.\ndnl - It requires a line break inside the AC_DEFUN_ONCE and AC_DEFUN expansions.\ndnl   Otherwise aclocal would emit many \"Use of uninitialized value $1\"\ndnl   warnings.\nm4_define([gl_iconv_AC_DEFUN],\n  m4_version_prereq([2.64],\n    [[AC_DEFUN_ONCE(\n        [$1], [$2])]],\n    [[AC_DEFUN(\n        [$1], [$2])]]))\ngl_iconv_AC_DEFUN([AM_ICONV],\n[\n  AM_ICONV_LINK\n  if test \"$am_cv_func_iconv\" = yes; then\n    AC_MSG_CHECKING([for iconv declaration])\n    AC_CACHE_VAL([am_cv_proto_iconv], [\n      AC_TRY_COMPILE([\n#include <stdlib.h>\n#include <iconv.h>\nextern\n#ifdef __cplusplus\n\"C\"\n#endif\n#if defined(__STDC__) || defined(__cplusplus)\nsize_t iconv (iconv_t cd, char * *inbuf, size_t *inbytesleft, char * *outbuf, size_t *outbytesleft);\n#else\nsize_t iconv();\n#endif\n], [], [am_cv_proto_iconv_arg1=\"\"], [am_cv_proto_iconv_arg1=\"const\"])\n      am_cv_proto_iconv=\"extern size_t iconv (iconv_t cd, $am_cv_proto_iconv_arg1 char * *inbuf, size_t *inbytesleft, char * *outbuf, size_t *outbytesleft);\"])\n    am_cv_proto_iconv=`echo \"[$]am_cv_proto_iconv\" | tr -s ' ' | sed -e 's/( /(/'`\n    AC_MSG_RESULT([\n         $am_cv_proto_iconv])\n    AC_DEFINE_UNQUOTED([ICONV_CONST], [$am_cv_proto_iconv_arg1],\n      [Define as const if the declaration of iconv() needs const.])\n  fi\n])\n"
  },
  {
    "path": "package/libs/libiconv-full/Makefile",
    "content": "#\n# Copyright (C) 2006-2015 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=libiconv-full\nPKG_VERSION:=1.16\nPKG_RELEASE:=1\n\nPKG_SOURCE:=libiconv-$(PKG_VERSION).tar.gz\nPKG_SOURCE_URL:=@GNU/libiconv\nPKG_HASH:=e6a1b1b589654277ee790cce3734f07876ac4ccfaecbee8afa0b649cf529cc04\nPKG_BUILD_DIR:=$(BUILD_DIR)/libiconv-$(PKG_VERSION)\n\nPKG_MAINTAINER:=Jo-Philipp Wich <jo@mein.io>\nPKG_LICENSE:=LGPL-2.1-or-later\nPKG_LICENSE_FILES:=COPYING.LIB\n\nPKG_FIXUP:=patch-libtool\nPKG_INSTALL:=1\nPKG_BUILD_PARALLEL:=1\n\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine Package/libiconv-full/Default\n  URL:=https://www.gnu.org/software/libiconv/\n  TITLE:=Character set conversion\nendef\n\ndefine Package/libiconv-full\n  $(call Package/libiconv-full/Default)\n  SECTION:=libs\n  CATEGORY:=Libraries\n  TITLE+= library\n  ABI_VERSION:=2\nendef\n\ndefine Package/libcharset\n  $(call Package/libiconv-full/Default)\n  SECTION:=libs\n  CATEGORY:=Libraries\n  TITLE+= library\n  ABI_VERSION:=1\nendef\n\ndefine Package/iconv\n  $(call Package/libiconv-full/Default)\n  DEPENDS:=+libiconv-full +libcharset\n  SECTION:=utils\n  CATEGORY:=Utilities\n  TITLE+= utility\nendef\n\nCONFIGURE_ARGS += \\\n\t--enable-shared \\\n\t--enable-static \\\n\t--disable-rpath \\\n\t--enable-relocatable\n\ndefine Build/InstallDev\n\t$(INSTALL_DIR) $(1)/usr/lib/libiconv-full/include\n\t$(CP) $(PKG_INSTALL_DIR)/usr/include/iconv.h $(1)/usr/lib/libiconv-full/include/\n\n\t$(INSTALL_DIR) $(1)/usr/lib/libiconv-full/lib\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/libcharset.{a,so*} $(1)/usr/lib/libiconv-full/lib/\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/libiconv.{a,so*} $(1)/usr/lib/libiconv-full/lib/\nendef\n\ndefine Package/libcharset/install\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/libcharset.so.* $(1)/usr/lib/\nendef\n\ndefine Package/libiconv-full/install\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/libiconv.so.* $(1)/usr/lib/\nendef\n\ndefine Package/iconv/install\n\t$(INSTALL_DIR) $(1)/usr/bin\n\t$(CP) $(PKG_INSTALL_DIR)/usr/bin/iconv $(1)/usr/bin/\nendef\n\n$(eval $(call BuildPackage,libcharset))\n$(eval $(call BuildPackage,libiconv-full))\n$(eval $(call BuildPackage,iconv))\n"
  },
  {
    "path": "package/libs/libjson-c/Makefile",
    "content": "#\n# Copyright (C) 2006-2014 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=json-c\nPKG_VERSION:=0.15\nPKG_RELEASE:=2\n\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION)-nodoc.tar.gz\nPKG_SOURCE_URL:=https://s3.amazonaws.com/json-c_releases/releases/\nPKG_HASH:=99bca4f944b8ced8ae0bbc6310d6a3528ca715e69541793a1ef51f8c5b4b0878\n\nPKG_MAINTAINER:=Felix Fietkau <nbd@nbd.name>\nPKG_LICENSE:=MIT\nPKG_LICENSE_FILES:=COPYING\nPKG_CPE_ID:=cpe:/a:json-c_project:json-c\n\nHOST_BUILD_PREFIX:=$(STAGING_DIR_HOST)\n\ninclude $(INCLUDE_DIR)/package.mk\ninclude $(INCLUDE_DIR)/host-build.mk\ninclude $(INCLUDE_DIR)/cmake.mk\n\nCMAKE_HOST_OPTIONS += \\\n\t-DBUILD_SHARED_LIBS=FALSE\n\ndefine Package/libjson-c\n  SECTION:=libs\n  CATEGORY:=Libraries\n  TITLE:=javascript object notation\n  URL:=https://json-c.github.io/json-c/\n  ABI_VERSION:=5\nendef\n\ndefine Package/libjson-c/description\n This package contains a library for javascript object notation backends.\nendef\n\ndefine Build/InstallDev\n\t$(call Build/InstallDev/cmake,$(1))\n\t$(SED) 's,/usr/include,$$$${prefix}/include,g' $(1)/usr/lib/pkgconfig/json-c.pc\n\t$(SED) 's,/usr/lib,$$$${exec_prefix}/lib,g' $(1)/usr/lib/pkgconfig/json-c.pc\nendef\n\ndefine Package/libjson-c/install\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/libjson-c.so.* $(1)/usr/lib/\nendef\n\n$(eval $(call BuildPackage,libjson-c))\n$(eval $(call HostBuild))\n"
  },
  {
    "path": "package/libs/libjson-c/patches/001-dont-build-docs.patch",
    "content": "--- a/CMakeLists.txt\n+++ b/CMakeLists.txt\n@@ -401,8 +401,6 @@ set(JSON_C_SOURCES\n include_directories(${PROJECT_SOURCE_DIR})\n include_directories(${PROJECT_BINARY_DIR})\n \n-add_subdirectory(doc)\n-\n # uninstall\n add_custom_target(uninstall\n   COMMAND cat ${PROJECT_BINARY_DIR}/install_manifest.txt | xargs rm\n"
  },
  {
    "path": "package/libs/libjson-c/patches/010-clang.patch",
    "content": "--- a/CMakeLists.txt\n+++ b/CMakeLists.txt\n@@ -265,7 +265,7 @@ message(STATUS \"Wrote ${PROJECT_BINARY_D\n configure_file(${PROJECT_SOURCE_DIR}/cmake/json_config.h.in   ${PROJECT_BINARY_DIR}/json_config.h)\n message(STATUS \"Wrote ${PROJECT_BINARY_DIR}/json_config.h\")\n \n-if (\"${CMAKE_C_COMPILER_ID}\" STREQUAL \"GNU\")\n+if (\"${CMAKE_C_COMPILER_ID}\" STREQUAL \"GNU\" OR \"${CMAKE_C_COMPILER_ID}\" STREQUAL \"Clang\")\n     set(CMAKE_C_FLAGS           \"${CMAKE_C_FLAGS} -ffunction-sections -fdata-sections\")\n \tif (\"${DISABLE_WERROR}\" STREQUAL \"OFF\")\n \t    set(CMAKE_C_FLAGS           \"${CMAKE_C_FLAGS} -Werror\")\n"
  },
  {
    "path": "package/libs/libmnl/Makefile",
    "content": "#\n# Copyright (C) 2011-2012 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=libmnl\nPKG_VERSION:=1.0.5\nPKG_RELEASE:=1\n\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.bz2\nPKG_SOURCE_URL:= \\\n\thttp://www.netfilter.org/projects/libmnl/files \\\n\tftp://ftp.netfilter.org/pub/libmnl\nPKG_HASH:=274b9b919ef3152bfb3da3a13c950dd60d6e2bcd54230ffeca298d03b40d0525\n\nPKG_MAINTAINER:=Jo-Philipp Wich <jo@mein.io>\n\nPKG_FIXUP:=autoreconf\nPKG_INSTALL:=1\nPKG_LICENSE:=LGPL-2.1+\n\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine Package/libmnl\n  SECTION:=libs\n  CATEGORY:=Libraries\n  TITLE:=Minimalistic user-space library for Netlink\n  URL:=http://www.netfilter.org/projects/libmnl/\n  ABI_VERSION:=0\nendef\n\ndefine Package/libmnl/description\n libmnl is a minimalistic user-space library oriented to Netlink developers.\n There are a lot of common tasks in parsing, validating, constructing of\n both the Netlink header and TLVs that are repetitive and easy to get wrong.\n This library aims to provide simple helpers that allows you to re-use code\n and to avoid re-inventing the wheel. The main features of this library are:\n .\n * Small: the shared library requires around 30KB for an x86-based computer.\n .\n * Simple: this library avoids complexity and elaborated abstractions that\n   tend to hide Netlink details.\n .\n * Easy to use: the library simplifies the work for Netlink-wise developers.\n   It provides functions to make socket handling, message building, validating,\n   parsing and sequence tracking, easier.\n .\n * Easy to re-use: you can use the library to build your own abstraction layer\n   on top of this library.\n .\n * Decoupling: the interdependency of the main bricks that compose the library\n   is reduced, i.e. the library provides many helpers, but the programmer is not\n   forced to use them.\nendef\n\nCONFIGURE_ARGS+= \\\n\t--enable-shared \\\n\t--enable-static \\\n\ndefine Build/InstallDev\n\t$(INSTALL_DIR) $(1)/usr/include\n\t$(CP) $(PKG_INSTALL_DIR)/usr/include/libmnl $(1)/usr/include/\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/libmnl.{a,so*} $(1)/usr/lib/\n\t$(INSTALL_DIR) $(1)/usr/lib/pkgconfig\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/pkgconfig/libmnl.pc $(1)/usr/lib/pkgconfig/\nendef\n\ndefine Package/libmnl/install\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/libmnl.so.* $(1)/usr/lib/\nendef\n\n$(eval $(call BuildPackage,libmnl))\n"
  },
  {
    "path": "package/libs/libnetfilter-conntrack/Makefile",
    "content": "#\n# Copyright (C) 2009-2013 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=libnetfilter_conntrack\nPKG_VERSION:=1.0.9\nPKG_RELEASE:=2\n\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.bz2\nPKG_SOURCE_URL:=https://www.netfilter.org/projects/libnetfilter_conntrack/files\nPKG_HASH:=67bd9df49fe34e8b82144f6dfb93b320f384a8ea59727e92ff8d18b5f4b579a8\n\nPKG_MAINTAINER:=Jo-Philipp Wich <jo@mein.io>\nPKG_LICENSE:=GPL-2.0-or-later\nPKG_LICENSE_FILES:=COPYING\n\nPKG_INSTALL:=1\nPKG_BUILD_PARALLEL:=1\n\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine Package/libnetfilter-conntrack\n  SECTION:=libs\n  CATEGORY:=Libraries\n  DEPENDS:=+libnfnetlink +kmod-nf-conntrack-netlink +libmnl\n  TITLE:=API to the in-kernel connection tracking state table\n  URL:=http://www.netfilter.org/projects/libnetfilter_conntrack/\n  ABI_VERSION:=3\nendef\n\ndefine Package/libnetfilter-conntrack/description\n libnetfilter_conntrack is a userspace library providing a programming\n interface (API) to the in-kernel connection tracking state table. The\n library libnetfilter_conntrack has been previously known as\n libnfnetlink_conntrack and libctnetlink. This library is currently\n used by conntrack-tools among many other applications.\nendef\n\nTARGET_CFLAGS += $(FPIC)\n\nCONFIGURE_ARGS += \\\n\t--enable-static \\\n\t--enable-shared \\\n\ndefine Build/InstallDev\n\t$(INSTALL_DIR) $(1)/usr/include/libnetfilter_conntrack\n\t$(CP) \\\n\t\t$(PKG_INSTALL_DIR)/usr/include/libnetfilter_conntrack/*.h \\\n\t\t$(1)/usr/include/libnetfilter_conntrack/\n\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(CP) \\\n\t\t$(PKG_INSTALL_DIR)/usr/lib/libnetfilter_conntrack.{so*,a,la} \\\n\t\t$(1)/usr/lib/\n\n\t$(INSTALL_DIR) $(1)/usr/lib/pkgconfig\n\t$(CP) \\\n\t\t$(PKG_INSTALL_DIR)/usr/lib/pkgconfig/libnetfilter_conntrack.pc \\\n\t\t$(1)/usr/lib/pkgconfig/\nendef\n\ndefine Package/libnetfilter-conntrack/install\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(CP) \\\n\t\t$(PKG_INSTALL_DIR)/usr/lib/libnetfilter_conntrack.so.* \\\n\t\t$(1)/usr/lib/\nendef\n\n$(eval $(call BuildPackage,libnetfilter-conntrack))\n"
  },
  {
    "path": "package/libs/libnetfilter-conntrack/patches/0001-conntrack-fix-build-with-kernel-5_15-and-musl.patch",
    "content": "From 21ee35dde73aec5eba35290587d479218c6dd824 Mon Sep 17 00:00:00 2001\nFrom: Robert Marko <robimarko@gmail.com>\nDate: Thu, 24 Feb 2022 15:01:11 +0100\nSubject: conntrack: fix build with kernel 5.15 and musl\n\nCurrently, with kernel 5.15 headers and musl building is failing with\nredefinition errors due to a conflict between the kernel and musl headers.\n\nMusl is able to suppres the conflicting kernel header definitions if they\nare included after the standard libc ones, however since ICMP definitions\nwere moved into a separate internal header to avoid duplication this has\nstopped working and is breaking the builds.\n\nIt seems that the issue is that <netinet/in.h> which contains the UAPI\nsuppression defines is included in the internal.h header and not in the\nproto.h which actually includes the kernel ICMP headers and thus UAPI\nsupression defines are not present.\n\nSolve this by moving the <netinet/in.h> include before the ICMP kernel\nincludes in the proto.h\n\nFixes: bc1cb4b11403 (\"conntrack: Move icmp request>reply type mapping to common file\")\nSigned-off-by: Robert Marko <robimarko@gmail.com>\nSigned-off-by: Florian Westphal <fw@strlen.de>\n---\n include/internal/internal.h | 1 -\n include/internal/proto.h    | 1 +\n 2 files changed, 1 insertion(+), 1 deletion(-)\n\n--- a/include/internal/internal.h\n+++ b/include/internal/internal.h\n@@ -14,7 +14,6 @@\n #include <arpa/inet.h>\n #include <time.h>\n #include <errno.h>\n-#include <netinet/in.h>\n \n #include <libnfnetlink/libnfnetlink.h>\n #include <libnetfilter_conntrack/libnetfilter_conntrack.h>\n--- a/include/internal/proto.h\n+++ b/include/internal/proto.h\n@@ -2,6 +2,7 @@\n #define _NFCT_PROTO_H_\n \n #include <stdint.h>\n+#include <netinet/in.h>\n #include <linux/icmp.h>\n #include <linux/icmpv6.h>\n \n"
  },
  {
    "path": "package/libs/libnfnetlink/Makefile",
    "content": "#\n# Copyright (C) 2007-2013 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=libnfnetlink\nPKG_VERSION:=1.0.2\nPKG_RELEASE:=1\n\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.bz2\nPKG_SOURCE_URL:= \\\n\thttp://www.netfilter.org/projects/libnfnetlink/files/ \\\n\tftp://ftp.netfilter.org/pub/libnfnetlink/\nPKG_HASH:=b064c7c3d426efb4786e60a8e6859b82ee2f2c5e49ffeea640cfe4fe33cbc376\nPKG_MAINTAINER:=Jo-Philipp Wich <jo@mein.io>\nPKG_LICENSE:=GPL-2.0+\n\nPKG_FIXUP:=autoreconf\n\nPKG_INSTALL:=1\n\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine Package/libnfnetlink\n  SECTION:=libs\n  CATEGORY:=Libraries\n  TITLE:=A low-level library for netfilter related kernel/userspace communication\n  URL:=http://netfilter.org/projects/libnfnetlink/\n  ABI_VERSION:=0\nendef\n\ndefine Package/libnfnetlink/description\n libnfnetlink is is the low-level library for netfilter related kernel/userspace communication.\n It provides a generic messaging infrastructure for in-kernel netfilter subsystems\n (such as nfnetlink_log, nfnetlink_queue, nfnetlink_conntrack) and their respective users\n and/or management tools in userspace.\nendef\n\nCONFIGURE_ARGS += \\\n\t--enable-static \\\n\t--enable-shared\n\nCONFIGURE_VARS += \\\n\tlt_prog_compiler_pic=\"$(FPIC)\"\n\ndefine Build/InstallDev\n\t$(INSTALL_DIR) $(1)/usr/include/libnfnetlink\n\t$(CP) \\\n\t\t$(PKG_INSTALL_DIR)/usr/include/libnfnetlink/{libnfnetlink,linux_nfnetlink,linux_nfnetlink_compat}.h \\\n\t\t$(1)/usr/include/libnfnetlink/\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(CP) \\\n\t\t$(PKG_INSTALL_DIR)/usr/lib/libnfnetlink.{a,so*} \\\n\t\t$(1)/usr/lib/\n\t$(INSTALL_DIR) $(1)/usr/lib/pkgconfig\n\t$(CP) \\\n\t\t$(PKG_INSTALL_DIR)/usr/lib/pkgconfig/libnfnetlink.pc \\\n\t\t$(1)/usr/lib/pkgconfig/\nendef\n\ndefine Package/libnfnetlink/install\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(CP) \\\n\t\t$(PKG_INSTALL_DIR)/usr/lib/libnfnetlink.so.* \\\n\t\t$(1)/usr/lib/\nendef\n\n$(eval $(call BuildPackage,libnfnetlink))\n"
  },
  {
    "path": "package/libs/libnftnl/Makefile",
    "content": "#\n# Copyright (C) 2014 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=libnftnl\nPKG_VERSION:=1.2.1\nPKG_RELEASE:=$(AUTORELEASE)\n\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.bz2\nPKG_SOURCE_URL:=https://netfilter.org/projects/$(PKG_NAME)/files\nPKG_HASH:=7508a5c414fab13e3cb3ce8262d0ce4f02c1590a8e4f8628ab497b5b4585937c\n\nPKG_MAINTAINER:=Steven Barth <steven@midlink.org>\nPKG_LICENSE:=GPL-2.0-or-later\nPKG_LICENSE_FILES:=COPYING\n\nPKG_INSTALL:=1\nPKG_BUILD_PARALLEL:=1\n\ninclude $(INCLUDE_DIR)/package.mk\n\nDISABLE_NLS:=\n\ndefine Package/libnftnl\n  SECTION:=libs\n  CATEGORY:=Libraries\n  DEPENDS:=+libmnl\n  TITLE:=Low-level netlink library for the nf_tables subsystem\n  URL:=http://www.netfilter.org/projects/libnftnl\n  ABI_VERSION:=11\nendef\n\ndefine Package/libnftnl/description\n libnftnl is a userspace library providing a low-level netlink\n programming interface (API) to the in-kernel nf_tables subsystem.\nendef\n\nTARGET_CFLAGS += $(FPIC) -flto\nTARGET_LDFLAGS += -flto\n\nCONFIGURE_ARGS += \\\n\t--enable-static \\\n\t--enable-shared\n\ndefine Build/InstallDev\n\t$(INSTALL_DIR) $(1)/usr/include/libnftnl\n\t$(CP) \\\n\t\t$(PKG_INSTALL_DIR)/usr/include/libnftnl/*.h \\\n\t\t$(1)/usr/include/libnftnl/\n\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(CP) \\\n\t\t$(PKG_INSTALL_DIR)/usr/lib/libnftnl.{so*,a,la} \\\n\t\t$(1)/usr/lib/\n\n\t$(INSTALL_DIR) $(1)/usr/lib/pkgconfig\n\t$(CP) \\\n\t\t$(PKG_INSTALL_DIR)/usr/lib/pkgconfig/libnftnl.pc \\\n\t\t$(1)/usr/lib/pkgconfig/\nendef\n\ndefine Package/libnftnl/install\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(CP) \\\n\t\t$(PKG_INSTALL_DIR)/usr/lib/libnftnl.so.* \\\n\t\t$(1)/usr/lib/\nendef\n\n$(eval $(call BuildPackage,libnftnl))\n"
  },
  {
    "path": "package/libs/libnl/Makefile",
    "content": "#\n# Copyright (C) 2006-2013 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=libnl\nPKG_VERSION:=3.5.0\nPKG_RELEASE:=1\n\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz\nPKG_SOURCE_URL:=https://github.com/thom311/libnl/releases/download/libnl$(subst .,_,$(PKG_VERSION))\nPKG_HASH:=352133ec9545da76f77e70ccb48c9d7e5324d67f6474744647a7ed382b5e05fa\nPKG_LICENSE:=LGPL-2.1\n\nPKG_INSTALL:=1\nPKG_FIXUP:=autoreconf\n\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine Package/libnl/default\n  SECTION:=libs\n  CATEGORY:=Libraries\n  URL:=http://www.infradead.org/~tgr/libnl/\n  ABI_VERSION:=200\nendef\n\ndefine Package/libnl-core\n$(call Package/libnl/default)\n  TITLE:=Core Netlink Library\n  DEPENDS:=+libpthread\nendef\n\ndefine Package/libnl-genl\n$(call Package/libnl/default)\n  TITLE:=Generic Netlink Library\n  DEPENDS:=+libnl-core\nendef\n\ndefine Package/libnl-route\n$(call Package/libnl/default)\n  TITLE:=Routing Netlink Library\n  DEPENDS:=+libnl-core\nendef\n\ndefine Package/libnl-nf\n$(call Package/libnl/default)\n  TITLE:=Netfilter Netlink Library\n  DEPENDS:=+libnl-route\nendef\n\ndefine Package/libnl\n$(call Package/libnl/default)\n  TITLE:=Full Netlink Library\n  DEPENDS:=+libnl-genl +libnl-route +libnl-nf\nendef\n\ndefine Package/libnl-core/description\n Common code for all netlink libraries\nendef\n\ndefine Package/libnl-genl/description\n Generic Netlink Library Functions\nendef\n\ndefine Package/libnl-route/description\n Routing Netlink Library Functions\nendef\n\ndefine Package/libnl-nf/description\n Netfilter Netlink Library Functions\nendef\n\ndefine Package/libnl/description\n Socket handling, connection management, sending and receiving of data,\n message construction and parsing, object caching system, etc.\nendef\n\nTARGET_CFLAGS += -ffunction-sections -fdata-sections $(FPIC)\n\nCONFIGURE_ARGS += \\\n\t--disable-debug\n\ndefine Build/InstallDev\n\t$(INSTALL_DIR) $(1)/usr/include/libnl3 $(1)/usr/lib/pkgconfig\n\t$(CP) $(PKG_INSTALL_DIR)/usr/include/libnl3/* $(1)/usr/include/libnl3/\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/* $(1)/usr/lib\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/pkgconfig/*.pc $(1)/usr/lib/pkgconfig\n\n\t# Copy symlinks\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/libnl-3.so $(1)/usr/lib/libnl.so\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/libnl-genl-3.so $(1)/usr/lib/libnl-genl.so\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/libnl-nf-3.so $(1)/usr/lib/libnl-nf.so\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/libnl-route-3.so $(1)/usr/lib/libnl-route.so\nendef\n\ndefine Package/libnl-core/install\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/libnl-3.so.* $(1)/usr/lib/\nendef\n\ndefine Package/libnl-genl/install\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/libnl-genl-3.so.* $(1)/usr/lib/\nendef\n\ndefine Package/libnl-route/install\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/libnl-route-3.so.* $(1)/usr/lib/\nendef\n\ndefine Package/libnl-nf/install\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/libnl-nf-3.so.* $(1)/usr/lib/\nendef\n\ndefine Package/libnl/install\n\t:\nendef\n\n$(eval $(call BuildPackage,libnl-core))\n$(eval $(call BuildPackage,libnl-genl))\n$(eval $(call BuildPackage,libnl-route))\n$(eval $(call BuildPackage,libnl-nf))\n$(eval $(call BuildPackage,libnl))\n"
  },
  {
    "path": "package/libs/libnl/patches/100-build-add-Libs.private-field-in-libnl-pkg-config-file.patch",
    "content": "From db0d59cd06f3ffd350379847c0885e1bfb85af0f Mon Sep 17 00:00:00 2001\nFrom: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>\nDate: Sat, 7 Mar 2015 11:34:42 +0100\nSubject: [PATCH 2/2] build: add Libs.private field in libnl pkg-config file\n\nIn order to support static linking, the libnl pkg-config file should\nindicate in its Libs.private field the libraries that libnl-3.0.a\nrequires. The LIBS variable contains the appropriate list of\nlibraries: -lm in all cases, and -lpthread when pthread support is\nenabled. This allows to statically link applications against libnl\nproperly.\n\nSigned-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>\n---\n libnl-3.0.pc.in | 1 +\n 1 file changed, 1 insertion(+)\n\n--- a/libnl-3.0.pc.in\n+++ b/libnl-3.0.pc.in\n@@ -7,4 +7,5 @@ Name: libnl\n Description: Convenience library for netlink sockets\n Version: @PACKAGE_VERSION@\n Libs: -L${libdir} -lnl-@MAJ_VERSION@\n+Libs.private: @LIBS@\n Cflags: -I${includedir}/libnl@MAJ_VERSION@\n"
  },
  {
    "path": "package/libs/libnl-tiny/Makefile",
    "content": "#\n# Copyright (C) 2006-2012 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=libnl-tiny\nPKG_RELEASE:=1\n\nPKG_SOURCE_PROTO:=git\nPKG_SOURCE_URL=$(PROJECT_GIT)/project/libnl-tiny.git\nPKG_SOURCE_DATE:=2021-11-21\nPKG_SOURCE_VERSION:=8e0555fb39f51a5d6436b4f1370850caa03611ea\nPKG_MIRROR_HASH:=2cfbcc62384535674a2c0157cb24a0736520fcb66ed50be23bf9141c8488885f\nCMAKE_INSTALL:=1\n\nPKG_LICENSE:=LGPL-2.1\nPKG_MAINTAINER:=Felix Fietkau <nbd@nbd.name>\n\ninclude $(INCLUDE_DIR)/package.mk\ninclude $(INCLUDE_DIR)/cmake.mk\n\ndefine Package/libnl-tiny\n  SECTION:=libs\n  CATEGORY:=Libraries\n  TITLE:=netlink socket library\n  ABI_VERSION:=1\nendef\n\ndefine Package/libnl-tiny/description\n This package contains a stripped down version of libnl\nendef\n\ndefine Build/InstallDev\n\t$(INSTALL_DIR) $(1)/usr/lib/pkgconfig $(1)/usr/include/libnl-tiny\n\t$(CP) $(PKG_INSTALL_DIR)/usr/include/libnl-tiny/* $(1)/usr/include/libnl-tiny\n\t$(INSTALL_DATA) $(PKG_INSTALL_DIR)/usr/lib/libnl-tiny.so $(1)/usr/lib/\n\t$(INSTALL_DATA) $(PKG_BUILD_DIR)/libnl-tiny.pc $(1)/usr/lib/pkgconfig\nendef\n\ndefine Package/libnl-tiny/install\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(INSTALL_DATA) $(PKG_INSTALL_DIR)/usr/lib/libnl-tiny.so $(1)/usr/lib/\nendef\n\n$(eval $(call BuildPackage,libnl-tiny))\n"
  },
  {
    "path": "package/libs/libpcap/Config.in",
    "content": "menu \"Configuration\"\n\tdepends on PACKAGE_libpcap\n\nconfig PCAP_HAS_USB\n\tbool \"Include USB support\"\n\tdefault n\n\nconfig PCAP_HAS_BT\n\tbool \"Include bluetooth support\"\n\tdepends on BROKEN\n\tdefault n\n\nconfig PCAP_HAS_NETFILTER\n\tbool \"Include netfilter support\"\n\tdefault n\n\nendmenu\n"
  },
  {
    "path": "package/libs/libpcap/Makefile",
    "content": "#\n# Copyright (C) 2006-2013 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=libpcap\nPKG_VERSION:=1.10.1\nPKG_RELEASE:=$(AUTORELEASE)\n\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz\nPKG_SOURCE_URL:=http://www.tcpdump.org/release/\nPKG_HASH:=ed285f4accaf05344f90975757b3dbfe772ba41d1c401c2648b7fa45b711bdd4\n\nPKG_MAINTAINER:=Felix Fietkau <nbd@nbd.name>\nPKG_LICENSE:=BSD-3-Clause\nPKG_LICENSE_FILES:=LICENSE\n\nPKG_ASLR_PIE_REGULAR:=1\n\ninclude $(INCLUDE_DIR)/package.mk\ninclude $(INCLUDE_DIR)/cmake.mk\n\ndefine Package/libpcap\n  SECTION:=libs\n  CATEGORY:=Libraries\n  TITLE:=Low-level packet capture library\n  URL:=http://www.tcpdump.org/\n  MENU:=1\n  ABI_VERSION:=1\nendef\n\ndefine Package/libpcap/description\nThis package contains a system-independent library for user-level network packet\ncapture.\nendef\n\ndefine Package/libpcap/config\n\tsource \"$(SOURCE)/Config.in\"\nendef\n\ndefine Package/rpcapd\n  SECTION:=net\n  CATEGORY:=Network\n  TITLE:=Capture daemon to be controlled by a remote libpcap application\n  URL:=http://www.tcpdump.org/\n  DEPENDS+= +libpcap\nendef\n\nifdef CONFIG_PACKAGE_rpcapd\n\tCMAKE_OPTIONS += \\\n\t\t-DENABLE_REMOTE=ON\nendif\n\nCMAKE_OPTIONS += \\\n\t-DBUILD_SHARED_LIBS=ON \\\n\t-DBUILD_WITH_LIBNL=OFF \\\n\t-DINET6=O$(if $(CONFIG_IPV6),N,FF) \\\n\t-DPCAP_SUPPORT_NETFILTER=O$(if $(CONFIG_PCAP_HAS_NETFILTER),N,FF)\n\n# grep 'option(DISABLE_' CMakeLists.txt | cut -f2 -d'(' | cut -f1 -d' ' | sort --unique\nCMAKE_OPTIONS += \\\n\t-DDISABLE_BLUETOOTH=O$(if $(CONFIG_PCAP_HAS_BT),FF,N) \\\n\t-DDISABLE_DAG=ON \\\n\t-DDISABLE_DBUS=ON \\\n\t-DDISABLE_DPDK=ON \\\n\t-DDISABLE_LINUX_USBMON=O$(if $(CONFIG_PCAP_HAS_USB),FF,N) \\\n\t-DDISABLE_NETMAP=ON \\\n\t-DDISABLE_RDMA=ON \\\n\t-DDISABLE_SEPTEL=ON \\\n\t-DDISABLE_SNF=ON \\\n\t-DDISABLE_TC=ON \\\n\n# Debugging options\nCMAKE_OPTIONS += \\\n\t-DBDEBUG=OFF \\\n\t-DYYDEBUG=OFF \\\n\ndefine Build/InstallDev\n\t$(call Build/InstallDev/cmake,$(1))\n\t$(SED) \\\n\t\t's,^\\(prefix\\|exec_prefix\\)=.*,\\1=$(STAGING_DIR)/usr,g' \\\n\t\t$(1)/usr/bin/pcap-config\n\t$(INSTALL_DIR) $(2)/bin\n\t$(LN) ../../usr/bin/pcap-config $(2)/bin/pcap-config\nendef\n\ndefine Package/libpcap/install\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/libpcap.so.* $(1)/usr/lib/\nendef\n\ndefine Package/rpcapd/install\n\t$(INSTALL_DIR) $(1)/usr/sbin\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/sbin/rpcapd $(1)/usr/sbin/\nendef\n\n$(eval $(call BuildPackage,libpcap))\n$(eval $(call BuildPackage,rpcapd))\n"
  },
  {
    "path": "package/libs/libpcap/patches/100-no-openssl.patch",
    "content": "--- a/CMakeLists.txt\n+++ b/CMakeLists.txt\n@@ -1042,7 +1042,6 @@ endif()\n #\n # OpenSSL/libressl.\n #\n-find_package(OpenSSL)\n if(OPENSSL_FOUND)\n   #\n   # We have OpenSSL.\n"
  },
  {
    "path": "package/libs/libpcap/patches/102-skip-manpages.patch",
    "content": "From f172e36e436d714f4def1439b13efd147a6a8411 Mon Sep 17 00:00:00 2001\nFrom: Yousong Zhou <yszhou4tech@gmail.com>\nDate: Fri, 18 Oct 2019 12:43:22 +0000\nSubject: [PATCH] skip manpages\n\n---\n CMakeLists.txt | 55 --------------------------------------------------\n 1 file changed, 55 deletions(-)\n\n--- a/CMakeLists.txt\n+++ b/CMakeLists.txt\n@@ -2732,57 +2732,6 @@ if(NOT MSVC)\n     if(MINGW)\n         find_program(LINK_EXECUTABLE ln)\n     endif(MINGW)\n-    if(UNIX OR (MINGW AND LINK_EXECUTABLE))\n-        set(MAN1 \"\")\n-        foreach(MANPAGE ${MAN1_NOEXPAND})\n-            set(MAN1 ${MAN1} ${CMAKE_CURRENT_SOURCE_DIR}/${MANPAGE})\n-        endforeach(MANPAGE)\n-        install(FILES ${MAN1} DESTINATION ${CMAKE_INSTALL_MANDIR}/man1)\n-\n-        set(MAN3PCAP \"\")\n-        foreach(MANPAGE ${MAN3PCAP_NOEXPAND})\n-            set(MAN3PCAP ${MAN3PCAP} ${CMAKE_CURRENT_SOURCE_DIR}/${MANPAGE})\n-        endforeach(MANPAGE)\n-        foreach(TEMPLATE_MANPAGE ${MAN3PCAP_EXPAND})\n-            string(REPLACE \".in\" \"\" MANPAGE ${TEMPLATE_MANPAGE})\n-            configure_file(${CMAKE_CURRENT_SOURCE_DIR}/${TEMPLATE_MANPAGE} ${CMAKE_CURRENT_BINARY_DIR}/${MANPAGE} @ONLY)\n-            set(MAN3PCAP ${MAN3PCAP} ${CMAKE_CURRENT_BINARY_DIR}/${MANPAGE})\n-        endforeach(TEMPLATE_MANPAGE)\n-        install(FILES ${MAN3PCAP} DESTINATION ${CMAKE_INSTALL_MANDIR}/man3)\n-        install_manpage_symlink(pcap_datalink_val_to_name.3pcap pcap_datalink_val_to_description.3pcap ${CMAKE_INSTALL_MANDIR}/man3)\n-        install_manpage_symlink(pcap_datalink_val_to_name.3pcap pcap_datalink_val_to_description_or_dlt.3pcap ${CMAKE_INSTALL_MANDIR}/man3)\n-        install_manpage_symlink(pcap_dump_open.3pcap pcap_dump_fopen.3pcap ${CMAKE_INSTALL_MANDIR}/man3)\n-        install_manpage_symlink(pcap_findalldevs.3pcap pcap_freealldevs.3pcap ${CMAKE_INSTALL_MANDIR}/man3)\n-        install_manpage_symlink(pcap_geterr.3pcap pcap_perror.3pcap ${CMAKE_INSTALL_MANDIR}/man3)\n-        install_manpage_symlink(pcap_inject.3pcap pcap_sendpacket.3pcap ${CMAKE_INSTALL_MANDIR}/man3)\n-        install_manpage_symlink(pcap_list_datalinks.3pcap pcap_free_datalinks.3pcap ${CMAKE_INSTALL_MANDIR}/man3)\n-        install_manpage_symlink(pcap_list_tstamp_types.3pcap pcap_free_tstamp_types.3pcap ${CMAKE_INSTALL_MANDIR}/man3)\n-        install_manpage_symlink(pcap_loop.3pcap pcap_dispatch.3pcap ${CMAKE_INSTALL_MANDIR}/man3)\n-        install_manpage_symlink(pcap_major_version.3pcap pcap_minor_version.3pcap ${CMAKE_INSTALL_MANDIR}/man3)\n-        install_manpage_symlink(pcap_next_ex.3pcap pcap_next.3pcap ${CMAKE_INSTALL_MANDIR}/man3)\n-        install_manpage_symlink(pcap_open_dead.3pcap pcap_open_dead_with_tstamp_precision.3pcap ${CMAKE_INSTALL_MANDIR}/man3)\n-        install_manpage_symlink(pcap_open_offline.3pcap pcap_open_offline_with_tstamp_precision.3pcap ${CMAKE_INSTALL_MANDIR}/man3)\n-        install_manpage_symlink(pcap_open_offline.3pcap pcap_fopen_offline.3pcap ${CMAKE_INSTALL_MANDIR}/man3)\n-        install_manpage_symlink(pcap_open_offline.3pcap pcap_fopen_offline_with_tstamp_precision.3pcap ${CMAKE_INSTALL_MANDIR}/man3)\n-        install_manpage_symlink(pcap_tstamp_type_val_to_name.3pcap pcap_tstamp_type_val_to_description.3pcap ${CMAKE_INSTALL_MANDIR}/man3)\n-        install_manpage_symlink(pcap_setnonblock.3pcap pcap_getnonblock.3pcap ${CMAKE_INSTALL_MANDIR}/man3)\n-\n-        set(MANFILE \"\")\n-        foreach(TEMPLATE_MANPAGE ${MANFILE_EXPAND})\n-            string(REPLACE \".manfile.in\" \".${MAN_FILE_FORMATS}\" MANPAGE ${TEMPLATE_MANPAGE})\n-            configure_file(${CMAKE_CURRENT_SOURCE_DIR}/${TEMPLATE_MANPAGE} ${CMAKE_CURRENT_BINARY_DIR}/${MANPAGE} @ONLY)\n-            set(MANFILE ${MANFILE} ${CMAKE_CURRENT_BINARY_DIR}/${MANPAGE})\n-        endforeach(TEMPLATE_MANPAGE)\n-        install(FILES ${MANFILE} DESTINATION ${CMAKE_INSTALL_MANDIR}/man${MAN_FILE_FORMATS})\n-\n-        set(MANMISC \"\")\n-        foreach(TEMPLATE_MANPAGE ${MANMISC_EXPAND})\n-            string(REPLACE \".manmisc.in\" \".${MAN_MISC_INFO}\" MANPAGE ${TEMPLATE_MANPAGE})\n-            configure_file(${CMAKE_CURRENT_SOURCE_DIR}/${TEMPLATE_MANPAGE} ${CMAKE_CURRENT_BINARY_DIR}/${MANPAGE} @ONLY)\n-            set(MANMISC ${MANMISC} ${CMAKE_CURRENT_BINARY_DIR}/${MANPAGE})\n-        endforeach(TEMPLATE_MANPAGE)\n-        install(FILES ${MANMISC} DESTINATION ${CMAKE_INSTALL_MANDIR}/man${MAN_MISC_INFO})\n-    endif(UNIX OR (MINGW AND LINK_EXECUTABLE))\n endif(NOT MSVC)\n \n # uninstall target\n"
  },
  {
    "path": "package/libs/libpcap/patches/201-space_optimization.patch",
    "content": "--- a/pcap-common.c\n+++ b/pcap-common.c\n@@ -1662,14 +1662,23 @@ swap_pseudo_headers(int linktype, struct\n \t\tbreak;\n \n \tcase DLT_USB_LINUX:\n+#ifndef PCAP_SUPPORT_USB\n+\t\treturn;\n+#endif\n \t\tswap_linux_usb_header(hdr, data, 0);\n \t\tbreak;\n \n \tcase DLT_USB_LINUX_MMAPPED:\n+#ifndef PCAP_SUPPORT_USB\n+\t\treturn;\n+#endif\n \t\tswap_linux_usb_header(hdr, data, 1);\n \t\tbreak;\n \n \tcase DLT_NFLOG:\n+#ifndef PCAP_SUPPORT_NETFILTER\n+\t\treturn;\n+#endif\n \t\tswap_nflog_header(hdr, data);\n \t\tbreak;\n \t}\n"
  },
  {
    "path": "package/libs/libselinux/Makefile",
    "content": "#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=libselinux\nPKG_VERSION:=3.3\nPKG_RELEASE:=2\n\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz\nPKG_SOURCE_URL:=https://github.com/SELinuxProject/selinux/releases/download/$(PKG_VERSION)\nPKG_HASH:=acfdee27633d2496508c28727c3d41d3748076f66d42fccde2e6b9f3463a7057\nHOST_BUILD_DEPENDS:=libsepol/host pcre/host\n\nPKG_LICENSE:=libselinux-1.0\nPKG_LICENSE_FILES:=LICENSE\nPKG_MAINTAINER:=Thomas Petazzoni <thomas.petazzoni@bootlin.com>\n\nHOST_BUILD_DEPENDS:=libsepol/host musl-fts/host pcre/host\n\ninclude $(INCLUDE_DIR)/package.mk\ninclude $(INCLUDE_DIR)/host-build.mk\n\nLIBSELINUX_UTILS := \\\n\tavcstat \\\n\tcompute_av \\\n\tcompute_create \\\n\tcompute_member \\\n\tcompute_relabel \\\n\tgetconlist \\\n\tgetdefaultcon \\\n\tgetenforce \\\n\tgetfilecon \\\n\tgetpidcon \\\n\tgetsebool \\\n\tgetseuser \\\n\tmatchpathcon \\\n\tpolicyvers \\\n\tsefcontext_compile \\\n\tselabel_digest \\\n\tselabel_get_digests_all_partial_matches \\\n\tselabel_lookup \\\n\tselabel_lookup_best_match \\\n\tselabel_partial_match \\\n\tselinux_check_access \\\n\tselinux_check_securetty_context \\\n\tselinuxenabled \\\n\tselinuxexeccon \\\n\tsetenforce \\\n\tsetfilecon \\\n\ttogglesebool \\\n\tvalidatetrans\n\nLIBSELINUX_ALTS := \\\n\tgetenforce \\\n\tgetsebool \\\n\tmatchpathcon \\\n\tselinuxenabled \\\n\tsetenforce\n\n$(eval $(foreach a,$(LIBSELINUX_ALTS),ALTS_$(a):=300:/usr/sbin/$(a):/usr/sbin/libselinux-$(a)$(newline)))\n\ndefine Package/libselinux/Default\n  TITLE:=Runtime SELinux library\n  URL:=http://selinuxproject.org/page/Main_Page\nendef\n\ndefine Package/libselinux\n  $(call Package/libselinux/Default)\n  SECTION:=libs\n  CATEGORY:=Libraries\n  DEPENDS:=+libsepol +libpcre +USE_MUSL:musl-fts\nendef\n\ndefine Package/libselinux/description\n\tlibselinux is the runtime SELinux library that provides\n\tinterfaces (e.g. library functions for the SELinux kernel\n\tAPIs like getcon(), other support functions like\n\tgetseuserbyname()) to SELinux-aware applications. libselinux\n\tmay use the shared libsepol to manipulate the binary policy\n\tif necessary (e.g. to downgrade the policy format to an\n\tolder version supported by the kernel) when loading policy.\nendef\n\ndefine GenUtilPkg\n define Package/$(1)\n   $(call Package/libselinux/Default)\n   TITLE+= $(2) utility\n   SECTION:=utils\n   DEPENDS:=+libselinux\n   CATEGORY:=Utilities\n   SUBMENU:=libselinux tools\n   ALTERNATIVES:=$(ALTS_$(2))\n endef\n\n define Package/$(1)/description\n  libselinux version of the $(2) utility.\n endef\nendef\n\n$(foreach a,$(LIBSELINUX_UTILS),$(eval $(call GenUtilPkg,libselinux-$(a),$(a))))\n\n# Needed to link libselinux utilities, which link against\n# libselinux.so, which indirectly depends on libpcre.so, installed in\n# $(STAGING_DIR_HOSTPKG).\nHOST_LDFLAGS += -Wl,-rpath=\"$(STAGING_DIR_HOSTPKG)/lib\"\n\nHOST_MAKE_FLAGS += \\\n\tPREFIX=$(STAGING_DIR_HOSTPKG) \\\n\tSHLIBDIR=$(STAGING_DIR_HOSTPKG)/lib \\\n\tFTS_LDLIBS=-lfts\n\nifeq ($(CONFIG_USE_MUSL),y)\nMAKE_FLAGS += FTS_LDLIBS=-lfts\nendif\n\nMAKE_FLAGS += \\\n\tSHLIBDIR=/usr/lib \\\n\tOS=Linux\n\ndefine Build/Compile\n\t$(call Build/Compile/Default,all)\nendef\n\ndefine Build/Install\n\t$(call Build/Install/Default,install)\nendef\n\ndefine Build/InstallDev\n\t$(INSTALL_DIR) $(1)/usr/include\n\t$(CP) $(PKG_INSTALL_DIR)/usr/include/* $(1)/usr/include/\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/* $(1)/usr/lib/\n\t$(INSTALL_DIR) $(1)/usr/lib/pkgconfig\n\t$(INSTALL_DATA) $(PKG_INSTALL_DIR)/usr/lib/pkgconfig/libselinux.pc $(1)/usr/lib/pkgconfig/\n\t$(SED) 's,/usr/include,$$$${prefix}/include,g' $(1)/usr/lib/pkgconfig/libselinux.pc\n\t$(SED) 's,/usr/lib,$$$${exec_prefix}/lib,g' $(1)/usr/lib/pkgconfig/libselinux.pc\nendef\n\ndefine Package/libselinux/install\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/libselinux.so.* $(1)/usr/lib/\nendef\n\ndefine BuildUtil\n  define Package/$(1)/install\n\t$(INSTALL_DIR) $$(1)/usr/sbin\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/sbin/$(2) $$(1)/usr/sbin/$(if $(ALTS_$(2)),libselinux-$(2),$(2))\n  endef\n\n  $$(eval $$(call BuildPackage,$(1)))\nendef\n\n$(eval $(call HostBuild))\n$(eval $(call BuildPackage,libselinux))\n$(foreach a,$(LIBSELINUX_UTILS),$(eval $(call BuildUtil,libselinux-$(a),$(a))))\n"
  },
  {
    "path": "package/libs/libsemanage/Makefile",
    "content": "#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=libsemanage\nPKG_VERSION:=3.3\nPKG_RELEASE:=1\n\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz\nPKG_SOURCE_URL:=https://github.com/SELinuxProject/selinux/releases/download/$(PKG_VERSION)\nPKG_HASH:=84d0ec5afa34bbbb471f602d8c1bf317d12443d07852a34b60741d428d597ce8\nPKG_MAINTAINER:=Thomas Petazzoni <thomas.petazzoni@bootlin.com>\nPKG_LICENSE:=LGPL-2.1\nPKG_LICENSE_FILES:=COPYING\nPKG_CPE_ID:=cpe:/a:selinuxproject:libsemanage\n\n\nHOST_BUILD_DEPENDS:=libaudit/host libselinux/host bzip2/host\n\n\ninclude $(INCLUDE_DIR)/package.mk\ninclude $(INCLUDE_DIR)/host-build.mk\n\nPKG_INSTALL:=1\n\ndefine Package/libsemanage\n  SECTION:=libs\n  DEPENDS:=+libaudit +libselinux +libbz2\n  CATEGORY:=Libraries\n  TITLE:=SELinux policy management library\n  URL:=http://selinuxproject.org/page/Main_Page\nendef\n\ndefine Package/libsemanage/description\n\tlibsemanage is the policy management library. It uses\n\tlibsepol for binary policy manipulation and libselinux for\n\tinteracting with the SELinux system. It also exec's helper\n\tprograms for loading policy and for checking whether the\n\tfile_contexts configuration is valid (load_policy and\n\tsetfiles from policycoreutils) presently, although this may\n\tchange at least for the bootstrapping case (for rpm).\nendef #'\n\n\nHOST_MAKE_FLAGS += \\\n\tDESTDIR=$(STAGING_DIR_HOSTPKG) \\\n\tPREFIX=\"\"\n\n\ndefine Build/Configure\nendef\n\ndefine Build/InstallDev\n\t$(INSTALL_DIR) $(1)/usr/include\n\t$(CP) $(PKG_INSTALL_DIR)/usr/include/* $(1)/usr/include/\n\t$(INSTALL_DIR) $(1)/usr/lib/pkgconfig\n\t$(INSTALL_DATA) $(PKG_INSTALL_DIR)/usr/lib/pkgconfig/libsemanage.pc $(1)/usr/lib/pkgconfig/\n\t$(SED) 's,/usr/include,$$$${prefix}/include,g' $(1)/usr/lib/pkgconfig/libsemanage.pc\n\t$(SED) 's,/usr/lib,$$$${exec_prefix}/lib,g' $(1)/usr/lib/pkgconfig/libsemanage.pc\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/* $(1)/usr/lib/\nendef\n\ndefine Package/libsemanage/install\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/libsemanage.so.* $(1)/usr/lib/\nendef\n\n$(eval $(call HostBuild))\n$(eval $(call BuildPackage,libsemanage))\n"
  },
  {
    "path": "package/libs/libsepol/Makefile",
    "content": "#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=libsepol\nPKG_VERSION:=3.3\nPKG_RELEASE:=1\n\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz\nPKG_SOURCE_URL:=https://github.com/SELinuxProject/selinux/releases/download/$(PKG_VERSION)\nPKG_HASH:=2d97df3eb8466169b389c3660acbb90c54200ac96e452eca9f41a9639f4f238b\n\nPKG_MAINTAINER:=Thomas Petazzoni <thomas.petazzoni@bootlin.com>\n\ninclude $(INCLUDE_DIR)/package.mk\ninclude $(INCLUDE_DIR)/host-build.mk\n\ndefine Package/libsepol\n  SECTION:=libs\n  CATEGORY:=Libraries\n  TITLE:=SELinux binary policy manipulation library\n  URL:=http://selinuxproject.org/page/Main_Page\nendef\n\ndefine Package/libsepol/description\n\tLibsepol is the binary policy manipulation library. It doesn't\n\tdepend upon or use any of the other SELinux components.\nendef\n\ndefine Package/chkcon\n  SECTION:=utils\n  CATEGORY:=Utilities\n  DEPENDS:=+libsepol\n  TITLE:=libsepol chkcon security context validation tool\n  URL:=http://selinuxproject.org/page/Main_Page\nendef\n\ndefine Package/chkcon/description\n\tchkcon - determine if a security context is valid for a given binary policy\nendef\n\nHOST_MAKE_FLAGS += \\\n\tPREFIX=$(STAGING_DIR_HOSTPKG) \\\n\tSHLIBDIR=$(STAGING_DIR_HOSTPKG)/lib\n\nMAKE_FLAGS += \\\n\tSHLIBDIR=/usr/lib \\\n\tOS=Linux\n\ndefine Build/Compile\n\t$(call Build/Compile/Default,all)\nendef\n\ndefine Build/Install\n\t$(call Build/Install/Default,install)\nendef\n\ndefine Build/InstallDev\n\t$(INSTALL_DIR) $(1)/usr/include\n\t$(CP) $(PKG_INSTALL_DIR)/usr/include/* $(1)/usr/include/\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/* $(1)/usr/lib/\n\t$(INSTALL_DIR) $(1)/usr/lib/pkgconfig\n\t$(INSTALL_DATA) $(PKG_INSTALL_DIR)/usr/lib/pkgconfig/libsepol.pc $(1)/usr/lib/pkgconfig/\n\t$(SED) 's,/usr/include,$$$${prefix}/include,g' $(1)/usr/lib/pkgconfig/libsepol.pc\n\t$(SED) 's,/usr/lib,$$$${exec_prefix}/lib,g' $(1)/usr/lib/pkgconfig/libsepol.pc\nendef\n\ndefine Package/libsepol/install\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/libsepol.so.* $(1)/usr/lib/\nendef\n\ndefine Package/chkcon/install\n\t$(INSTALL_DIR) $(1)/usr/bin\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/bin/chkcon $(1)/usr/bin/\nendef\n\n$(eval $(call HostBuild))\n$(eval $(call BuildPackage,libsepol))\n$(eval $(call BuildPackage,chkcon))\n"
  },
  {
    "path": "package/libs/libtool/Makefile",
    "content": "#\n# Copyright (C) 2006 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=libtool\nPKG_VERSION:=2.4.6\nPKG_RELEASE:=2\n\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz\nPKG_SOURCE_URL:=@GNU/libtool\nPKG_HASH:=7c87a8c2c8c0fc9cd5019e402bed4292462d00a718a7cd5f11218153bf28b26f\n\nPKG_LICENSE:=GPL-2.0+\nPKG_LICENSE_FILES:=COPYING\nPKG_CPE_ID:=cpe:/a:gnu:libtool\n\nPKG_BUILD_PARALLEL:=0\n\ninclude $(INCLUDE_DIR)/package.mk\n\nCONFIGURE_PREFIX=$(STAGING_DIR_HOSTPKG)\nexport GLOBAL_LIBDIR=$(STAGING_DIR)/usr/lib\n\ndefine Package/libltdl\n  SECTION:=libs\n  CATEGORY:=Libraries\n  TITLE:=A generic dynamic object loading library\n  URL:=http://www.gnu.org/software/libtool/\n  ABI_VERSION:=7\nendef\n\ndefine Build/InstallDev\n\t$(MAKE) -C $(PKG_BUILD_DIR) \\\n\t\tbindir=\"$(2)/libltdl/bin\" \\\n\t\tdatadir=\"$(2)/libltdl/share\" \\\n\t\tprefix=\"$(2)/libltdl\" \\\n\t\texec_prefix=\"$(2)/libltdl\" \\\n\t\tinstall\n\t$(INSTALL_DIR) $(1)/usr/lib $(1)/usr/include\n\tmv $(2)/libltdl/lib/* $(1)/usr/lib/\n\tmv $(2)/libltdl/include/* $(1)/usr/include/\nendef\n\ndefine Package/libltdl/install\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(CP) $(PKG_BUILD_DIR)/libltdl/.libs/libltdl.so.* $(1)/usr/lib/\nendef\n\n$(eval $(call BuildPackage,libltdl))\n"
  },
  {
    "path": "package/libs/libubox/Makefile",
    "content": "include $(TOPDIR)/rules.mk\n\nPKG_NAME:=libubox\nPKG_RELEASE=1\n\nPKG_SOURCE_PROTO:=git\nPKG_SOURCE_URL=$(PROJECT_GIT)/project/libubox.git\nPKG_MIRROR_HASH:=cf48d00ed0ea74d53f2043eb9f9dc52834c0b214f258201cf22dfff7dd6c6e40\nPKG_SOURCE_DATE:=2022-05-15\nPKG_SOURCE_VERSION:=d2223ef9da7172a84d1508733dc58840e1381e3c\nPKG_ABI_VERSION:=$(call abi_version_str,$(PKG_SOURCE_DATE))\nCMAKE_INSTALL:=1\n\nPKG_LICENSE:=ISC\nPKG_LICENSE_FILES:=\n\nPKG_MAINTAINER:=Felix Fietkau <nbd@nbd.name>\n\nPKG_BUILD_DEPENDS:=lua\nHOST_BUILD_DEPENDS:=libjson-c/host\nHOST_BUILD_PREFIX:=$(STAGING_DIR_HOST)\n\ninclude $(INCLUDE_DIR)/package.mk\ninclude $(INCLUDE_DIR)/host-build.mk\ninclude $(INCLUDE_DIR)/cmake.mk\n\ndefine Package/libubox\n  SECTION:=libs\n  CATEGORY:=Libraries\n  TITLE:=Basic utility library\n  ABI_VERSION:=$(PKG_ABI_VERSION)\n  DEPENDS:=\nendef\n\ndefine Package/libblobmsg-json\n  SECTION:=libs\n  CATEGORY:=Libraries\n  TITLE:=blobmsg <-> json conversion library\n  ABI_VERSION:=$(PKG_ABI_VERSION)\n  DEPENDS:=+libjson-c +libubox\nendef\n\ndefine Package/jshn\n  SECTION:=utils\n  CATEGORY:=Utilities\n  DEPENDS:=+libjson-c +libubox +libblobmsg-json\n  TITLE:=JSON SHell Notation\nendef\n\ndefine Package/jshn/description\n  Library for parsing and generating JSON from shell scripts\nendef\n\ndefine Package/libjson-script\n  SECTION:=utils\n  CATEGORY:=Utilities\n  DEPENDS:=+libubox\n  ABI_VERSION:=$(PKG_ABI_VERSION)\n  TITLE:=Minimalistic JSON based scripting engine\nendef\n\ndefine Package/libubox-lua\n  SECTION:=libs\n  CATEGORY:=Libraries\n  DEPENDS:=+libubox +liblua\n  TITLE:=Lua binding for the OpenWrt Basic utility library\nendef\n\nTARGET_CFLAGS += -I$(STAGING_DIR)/usr/include\nCMAKE_OPTIONS += \\\n\t-DLUAPATH=/usr/lib/lua \\\n\t-DABIVERSION=\"$(PKG_ABI_VERSION)\"\n\ndefine Package/libubox/install\n\t$(INSTALL_DIR) $(1)/lib/\n\t$(INSTALL_DATA) $(PKG_INSTALL_DIR)/usr/lib/libubox.so.* $(1)/lib/\nendef\n\ndefine Package/libblobmsg-json/install\n\t$(INSTALL_DIR) $(1)/lib/\n\t$(INSTALL_DATA) $(PKG_INSTALL_DIR)/usr/lib/libblobmsg_json.so.* $(1)/lib/\nendef\n\ndefine Package/jshn/install\n\t$(INSTALL_DIR) $(1)/usr/bin $(1)/usr/share/libubox\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/bin/jshn $(1)/usr/bin\n\t$(INSTALL_DATA) $(PKG_INSTALL_DIR)/usr/share/libubox/jshn.sh $(1)/usr/share/libubox\nendef\n\ndefine Package/libjson-script/install\n\t$(INSTALL_DIR) $(1)/lib/\n\t$(INSTALL_DATA) $(PKG_INSTALL_DIR)/usr/lib/libjson_script.so.* $(1)/lib/\nendef\n\ndefine Package/libubox-lua/install\n\t$(INSTALL_DIR) $(1)/usr/lib/lua\n\t$(CP) $(PKG_BUILD_DIR)/lua/uloop.so $(1)/usr/lib/lua/\nendef\n\n\nCMAKE_HOST_OPTIONS += \\\n\t-DBUILD_LUA=OFF \\\n\t-DBUILD_EXAMPLES=OFF \\\n\t-DCMAKE_SKIP_RPATH=FALSE \\\n\t-DCMAKE_MACOSX_RPATH=1 \\\n\t-DCMAKE_INSTALL_RPATH=\"${STAGING_DIR_HOST}/lib\" \\\n\n$(eval $(call BuildPackage,libubox))\n$(eval $(call BuildPackage,libblobmsg-json))\n$(eval $(call BuildPackage,jshn))\n$(eval $(call BuildPackage,libjson-script))\n$(eval $(call BuildPackage,libubox-lua))\n$(eval $(call HostBuild))\n"
  },
  {
    "path": "package/libs/libunwind/Makefile",
    "content": "#\n# Copyright (C) 2008-2013 OpenWrt.org\n# Copyright (C) 2017-2019 Yousong Zhou <yszhou4tech@gmail.com>\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=libunwind\nPKG_VERSION:=1.5.0\nPKG_RELEASE:=2\n\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz\nPKG_SOURCE_URL:=@SAVANNAH/$(PKG_NAME)\nPKG_HASH:=90337653d92d4a13de590781371c604f9031cdb50520366aa1e3a91e1efb1017\n\nPKG_MAINTAINER:=Yousong Zhou <yszhou4tech@gmail.com>\nPKG_LICENSE:=X11\nPKG_LICENSE_FILES:=LICENSE\nPKG_CPE_ID:=cpe:/a:libunwind_project:libunwind\n\nPKG_FIXUP:=autoreconf\nPKG_INSTALL:=1\nPKG_BUILD_PARALLEL:=1\n\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine Package/libunwind\n  SECTION:=libs\n  CATEGORY:=Libraries\n  TITLE:=The libunwind project\n  URL:=http://www.nongnu.org/libunwind/\n  DEPENDS:=@((mips||mipsel||mips64||powerpc64||x86_64||arm||aarch64)||(USE_GLIBC&&(powerpc||i386))) +zlib\n  ABI_VERSION:=8\nendef\n\ndefine Package/libunwind/description\n  Libunwind defines a portable and efficient C programming interface (API) to determine the call-chain of a program.\nendef\n\nCONFIGURE_ARGS += \\\n\t--disable-documentation \\\n\t--disable-tests \\\n\t--disable-minidebuginfo\n\nTARGET_LDFLAGS += $(if $(CONFIG_USE_MUSL),-lssp_nonshared)\n\ndefine Package/libunwind/install\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/libunwin*.so.* $(1)/usr/lib/\nendef\n\ndefine Build/InstallDev\n\t$(INSTALL_DIR) $(1)/usr/include $(1)/usr/lib/pkgconfig\n\t$(CP) $(PKG_INSTALL_DIR)/usr/include/*.h $(1)/usr/include\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/libunwin*.so* $(1)/usr/lib\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/pkgconfig/* $(1)/usr/lib/pkgconfig/\nendef\n\n$(eval $(call BuildPackage,libunwind))\n"
  },
  {
    "path": "package/libs/libunwind/patches/001-Don-t-force-exec_prefix-lib64-libdir-on-ppc64.patch",
    "content": "From 0af7e7a53480ce8e1cf6cfb4e9fe071c1185ef31 Mon Sep 17 00:00:00 2001\nFrom: Matthias Diener <matthias.diener@gmail.com>\nDate: Fri, 2 Jul 2021 12:36:10 -0500\nSubject: [PATCH] Don't force {exec_prefix}/lib64 libdir on ppc64\n\n---\n configure.ac | 6 ------\n 1 file changed, 6 deletions(-)\n\ndiff --git a/configure.ac b/configure.ac\nindex 9fadc163..0dec4ca6 100644\n--- a/configure.ac\n+++ b/configure.ac\n@@ -215,12 +215,6 @@ fi\n AM_CONDITIONAL(USE_DWARF, [test x$use_dwarf = xyes])\n AC_MSG_RESULT([$use_dwarf])\n \n-if test x$target_arch = xppc64; then\n-        libdir='${exec_prefix}/lib64'\n-        AC_MSG_NOTICE([PowerPC64 detected, lib will be installed ${libdir}]);\n-        AC_SUBST([libdir])\n-fi\n-\n AC_MSG_CHECKING([whether to restrict build to remote support])\n if test x$target_arch != x$host_arch; then\n   CPPFLAGS=\"${CPPFLAGS} -DUNW_REMOTE_ONLY\"\n-- \n2.32.0\n\n"
  },
  {
    "path": "package/libs/libunwind/patches/002-fix-building-getcontext_S.patch",
    "content": "--- a/src/mips/getcontext.S\n+++ b/src/mips/getcontext.S\n@@ -24,12 +24,12 @@ OF CONTRACT, TORT OR OTHERWISE, ARISING\n WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */\n \n #include \"offsets.h\"\n-#include <endian.h>\n \n \t.text\n+\t.set nomips16\n \n #if _MIPS_SIM == _ABIO32\n-# if __BYTE_ORDER == __BIG_ENDIAN\n+# if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__\n #  define OFFSET 4\n # else\n #  define OFFSET 0\n"
  },
  {
    "path": "package/libs/libunwind/patches/003-fix-missing-ef_reg-defs-with-musl.patch",
    "content": "--- a/include/libunwind-mips.h\n+++ b/include/libunwind-mips.h\n@@ -114,6 +114,42 @@ typedef enum\n   }\n mips_regnum_t;\n \n+#ifndef __GLIBC__\n+#include <sys/reg.h>\n+\n+/* musl as of 1.1.14 does not export these */\n+#define EF_REG0\t\t\t6\n+#define EF_REG1\t\t\t7\n+#define EF_REG2\t\t\t8\n+#define EF_REG3\t\t\t9\n+#define EF_REG4\t\t\t10\n+#define EF_REG5\t\t\t11\n+#define EF_REG6\t\t\t12\n+#define EF_REG7\t\t\t13\n+#define EF_REG8\t\t\t14\n+#define EF_REG9\t\t\t15\n+#define EF_REG10\t\t16\n+#define EF_REG11\t\t17\n+#define EF_REG12\t\t18\n+#define EF_REG13\t\t19\n+#define EF_REG14\t\t20\n+#define EF_REG15\t\t21\n+#define EF_REG16\t\t22\n+#define EF_REG17\t\t23\n+#define EF_REG18\t\t24\n+#define EF_REG19\t\t25\n+#define EF_REG20\t\t26\n+#define EF_REG21\t\t27\n+#define EF_REG22\t\t28\n+#define EF_REG23\t\t29\n+#define EF_REG24\t\t30\n+#define EF_REG25\t\t31\n+#define EF_REG28\t\t34\n+#define EF_REG29\t\t35\n+#define EF_REG30\t\t36\n+#define EF_REG31\t\t37\n+#endif\n+\n typedef enum\n   {\n     UNW_MIPS_ABI_O32,\n"
  },
  {
    "path": "package/libs/libunwind/patches/004-ppc-musl.patch",
    "content": "--- a/include/libunwind-ppc32.h\n+++ b/include/libunwind-ppc32.h\n@@ -74,6 +74,88 @@ typedef int64_t unw_sword_t;\n \n typedef long double unw_tdep_fpreg_t;\n \n+#ifndef __GLIBC__\n+\n+/* We can't include asm/ptrace.h here, as it conflicts with musl's definitions */\n+\n+#define PT_R0\t0\n+#define PT_R1\t1\n+#define PT_R2\t2\n+#define PT_R3\t3\n+#define PT_R4\t4\n+#define PT_R5\t5\n+#define PT_R6\t6\n+#define PT_R7\t7\n+#define PT_R8\t8\n+#define PT_R9\t9\n+#define PT_R10\t10\n+#define PT_R11\t11\n+#define PT_R12\t12\n+#define PT_R13\t13\n+#define PT_R14\t14\n+#define PT_R15\t15\n+#define PT_R16\t16\n+#define PT_R17\t17\n+#define PT_R18\t18\n+#define PT_R19\t19\n+#define PT_R20\t20\n+#define PT_R21\t21\n+#define PT_R22\t22\n+#define PT_R23\t23\n+#define PT_R24\t24\n+#define PT_R25\t25\n+#define PT_R26\t26\n+#define PT_R27\t27\n+#define PT_R28\t28\n+#define PT_R29\t29\n+#define PT_R30\t30\n+#define PT_R31\t31\n+\n+#define PT_NIP\t32\n+#define PT_MSR\t33\n+#define PT_ORIG_R3 34\n+#define PT_CTR\t35\n+#define PT_LNK\t36\n+#define PT_XER\t37\n+#define PT_CCR\t38\n+#ifndef __powerpc64__\n+#define PT_MQ\t39\n+#else\n+#define PT_SOFTE 39\n+#endif\n+#define PT_TRAP\t40\n+#define PT_DAR\t41\n+#define PT_DSISR 42\n+#define PT_RESULT 43\n+#define PT_DSCR 44\n+#define PT_REGS_COUNT 44\n+\n+#define PT_FPR0\t48\t/* each FP reg occupies 2 slots in this space */\n+\n+#ifndef __powerpc64__\n+\n+#define PT_FPR31 (PT_FPR0 + 2*31)\n+#define PT_FPSCR (PT_FPR0 + 2*32 + 1)\n+\n+#else /* __powerpc64__ */\n+\n+#define PT_FPSCR (PT_FPR0 + 32)\t/* each FP reg occupies 1 slot in 64-bit space */\n+\n+\n+#define PT_VR0 82\t/* each Vector reg occupies 2 slots in 64-bit */\n+#define PT_VSCR (PT_VR0 + 32*2 + 1)\n+#define PT_VRSAVE (PT_VR0 + 33*2)\n+\n+\n+/*\n+ * Only store first 32 VSRs here. The second 32 VSRs in VR0-31\n+ */\n+#define PT_VSR0 150\t/* each VSR reg occupies 2 slots in 64-bit */\n+#define PT_VSR31 (PT_VSR0 + 2*31)\n+#endif /* __powerpc64__ */\n+\n+#endif /* !__GLIBC__ */\n+\n typedef enum\n   {\n     UNW_PPC32_R0,\n--- a/include/libunwind-ppc64.h\n+++ b/include/libunwind-ppc64.h\n@@ -81,6 +81,88 @@ typedef struct {\n     uint64_t halves[2];\n } unw_tdep_vreg_t;\n \n+#ifndef __GLIBC__\n+\n+/* We can't include asm/ptrace.h here, as it conflicts with musl's definitions */\n+\n+#define PT_R0\t0\n+#define PT_R1\t1\n+#define PT_R2\t2\n+#define PT_R3\t3\n+#define PT_R4\t4\n+#define PT_R5\t5\n+#define PT_R6\t6\n+#define PT_R7\t7\n+#define PT_R8\t8\n+#define PT_R9\t9\n+#define PT_R10\t10\n+#define PT_R11\t11\n+#define PT_R12\t12\n+#define PT_R13\t13\n+#define PT_R14\t14\n+#define PT_R15\t15\n+#define PT_R16\t16\n+#define PT_R17\t17\n+#define PT_R18\t18\n+#define PT_R19\t19\n+#define PT_R20\t20\n+#define PT_R21\t21\n+#define PT_R22\t22\n+#define PT_R23\t23\n+#define PT_R24\t24\n+#define PT_R25\t25\n+#define PT_R26\t26\n+#define PT_R27\t27\n+#define PT_R28\t28\n+#define PT_R29\t29\n+#define PT_R30\t30\n+#define PT_R31\t31\n+\n+#define PT_NIP\t32\n+#define PT_MSR\t33\n+#define PT_ORIG_R3 34\n+#define PT_CTR\t35\n+#define PT_LNK\t36\n+#define PT_XER\t37\n+#define PT_CCR\t38\n+#ifndef __powerpc64__\n+#define PT_MQ\t39\n+#else\n+#define PT_SOFTE 39\n+#endif\n+#define PT_TRAP\t40\n+#define PT_DAR\t41\n+#define PT_DSISR 42\n+#define PT_RESULT 43\n+#define PT_DSCR 44\n+#define PT_REGS_COUNT 44\n+\n+#define PT_FPR0\t48\t/* each FP reg occupies 2 slots in this space */\n+\n+#ifndef __powerpc64__\n+\n+#define PT_FPR31 (PT_FPR0 + 2*31)\n+#define PT_FPSCR (PT_FPR0 + 2*32 + 1)\n+\n+#else /* __powerpc64__ */\n+\n+#define PT_FPSCR (PT_FPR0 + 32)\t/* each FP reg occupies 1 slot in 64-bit space */\n+\n+\n+#define PT_VR0 82\t/* each Vector reg occupies 2 slots in 64-bit */\n+#define PT_VSCR (PT_VR0 + 32*2 + 1)\n+#define PT_VRSAVE (PT_VR0 + 33*2)\n+\n+\n+/*\n+ * Only store first 32 VSRs here. The second 32 VSRs in VR0-31\n+ */\n+#define PT_VSR0 150\t/* each VSR reg occupies 2 slots in 64-bit */\n+#define PT_VSR31 (PT_VSR0 + 2*31)\n+#endif /* __powerpc64__ */\n+\n+#endif /* !__GLIBC__ */\n+\n typedef enum\n   {\n     UNW_PPC64_R0,\n--- a/src/ppc32/Ginit.c\n+++ b/src/ppc32/Ginit.c\n@@ -46,14 +46,19 @@ static void *\n uc_addr (ucontext_t *uc, int reg)\n {\n   void *addr;\n+#ifdef __GLIBC__\n+  mcontext_t *mc = uc->uc_mcontext.uc_regs;\n+#else\n+  mcontext_t *mc = &uc->uc_mcontext;\n+#endif\n \n   if ((unsigned) (reg - UNW_PPC32_R0) < 32)\n-    addr = &uc->uc_mcontext.uc_regs->gregs[reg - UNW_PPC32_R0];\n+    addr = &mc->gregs[reg - UNW_PPC32_R0];\n \n   else\n   if ( ((unsigned) (reg - UNW_PPC32_F0) < 32) &&\n        ((unsigned) (reg - UNW_PPC32_F0) >= 0) )\n-    addr = &uc->uc_mcontext.uc_regs->fpregs.fpregs[reg - UNW_PPC32_F0];\n+    addr = &mc->fpregs.fpregs[reg - UNW_PPC32_F0];\n \n   else\n     {\n@@ -76,7 +81,7 @@ uc_addr (ucontext_t *uc, int reg)\n         default:\n           return NULL;\n         }\n-      addr = &uc->uc_mcontext.uc_regs->gregs[gregs_idx];\n+      addr = &mc->gregs[gregs_idx];\n     }\n   return addr;\n }\n--- a/src/ppc32/ucontext_i.h\n+++ b/src/ppc32/ucontext_i.h\n@@ -46,83 +46,89 @@ WITH THE SOFTWARE OR THE USE OR OTHER DE\n    various structure members. */\n static ucontext_t dmy_ctxt UNUSED;\n \n-#define UC_MCONTEXT_GREGS_R0 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[0] - (void *)&dmy_ctxt)\n-#define UC_MCONTEXT_GREGS_R1 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[1] - (void *)&dmy_ctxt)\n-#define UC_MCONTEXT_GREGS_R2 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[2] - (void *)&dmy_ctxt)\n-#define UC_MCONTEXT_GREGS_R3 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[3] - (void *)&dmy_ctxt)\n-#define UC_MCONTEXT_GREGS_R4 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[4] - (void *)&dmy_ctxt)\n-#define UC_MCONTEXT_GREGS_R5 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[5] - (void *)&dmy_ctxt)\n-#define UC_MCONTEXT_GREGS_R6 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[6] - (void *)&dmy_ctxt)\n-#define UC_MCONTEXT_GREGS_R7 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[7] - (void *)&dmy_ctxt)\n-#define UC_MCONTEXT_GREGS_R8 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[8] - (void *)&dmy_ctxt)\n-#define UC_MCONTEXT_GREGS_R9 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[9] - (void *)&dmy_ctxt)\n-#define UC_MCONTEXT_GREGS_R10 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[10] - (void *)&dmy_ctxt)\n-#define UC_MCONTEXT_GREGS_R11 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[11] - (void *)&dmy_ctxt)\n-#define UC_MCONTEXT_GREGS_R12 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[12] - (void *)&dmy_ctxt)\n-#define UC_MCONTEXT_GREGS_R13 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[13] - (void *)&dmy_ctxt)\n-#define UC_MCONTEXT_GREGS_R14 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[14] - (void *)&dmy_ctxt)\n-#define UC_MCONTEXT_GREGS_R15 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[15] - (void *)&dmy_ctxt)\n-#define UC_MCONTEXT_GREGS_R16 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[16] - (void *)&dmy_ctxt)\n-#define UC_MCONTEXT_GREGS_R17 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[17] - (void *)&dmy_ctxt)\n-#define UC_MCONTEXT_GREGS_R18 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[18] - (void *)&dmy_ctxt)\n-#define UC_MCONTEXT_GREGS_R19 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[19] - (void *)&dmy_ctxt)\n-#define UC_MCONTEXT_GREGS_R20 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[20] - (void *)&dmy_ctxt)\n-#define UC_MCONTEXT_GREGS_R21 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[21] - (void *)&dmy_ctxt)\n-#define UC_MCONTEXT_GREGS_R22 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[22] - (void *)&dmy_ctxt)\n-#define UC_MCONTEXT_GREGS_R23 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[23] - (void *)&dmy_ctxt)\n-#define UC_MCONTEXT_GREGS_R24 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[24] - (void *)&dmy_ctxt)\n-#define UC_MCONTEXT_GREGS_R25 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[25] - (void *)&dmy_ctxt)\n-#define UC_MCONTEXT_GREGS_R26 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[26] - (void *)&dmy_ctxt)\n-#define UC_MCONTEXT_GREGS_R27 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[27] - (void *)&dmy_ctxt)\n-#define UC_MCONTEXT_GREGS_R28 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[28] - (void *)&dmy_ctxt)\n-#define UC_MCONTEXT_GREGS_R29 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[29] - (void *)&dmy_ctxt)\n-#define UC_MCONTEXT_GREGS_R30 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[30] - (void *)&dmy_ctxt)\n-#define UC_MCONTEXT_GREGS_R31 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[31] - (void *)&dmy_ctxt)\n+#ifdef __GLIBC__\n+#define UC_MCONTEXT_OFFSET(field) ((void *)&dmy_ctxt.uc_mcontext.uc_regs->field - (void *)&dmy_ctxt)\n+#else\n+#define UC_MCONTEXT_OFFSET(field) ((void *)&dmy_ctxt.uc_mcontext.field - (void *)&dmy_ctxt)\n+#endif\n+\n+#define UC_MCONTEXT_GREGS_R0 UC_MCONTEXT_OFFSET(gregs[0])\n+#define UC_MCONTEXT_GREGS_R1 UC_MCONTEXT_OFFSET(gregs[1])\n+#define UC_MCONTEXT_GREGS_R2 UC_MCONTEXT_OFFSET(gregs[2])\n+#define UC_MCONTEXT_GREGS_R3 UC_MCONTEXT_OFFSET(gregs[3])\n+#define UC_MCONTEXT_GREGS_R4 UC_MCONTEXT_OFFSET(gregs[4])\n+#define UC_MCONTEXT_GREGS_R5 UC_MCONTEXT_OFFSET(gregs[5])\n+#define UC_MCONTEXT_GREGS_R6 UC_MCONTEXT_OFFSET(gregs[6])\n+#define UC_MCONTEXT_GREGS_R7 UC_MCONTEXT_OFFSET(gregs[7])\n+#define UC_MCONTEXT_GREGS_R8 UC_MCONTEXT_OFFSET(gregs[8])\n+#define UC_MCONTEXT_GREGS_R9 UC_MCONTEXT_OFFSET(gregs[9])\n+#define UC_MCONTEXT_GREGS_R10 UC_MCONTEXT_OFFSET(gregs[10])\n+#define UC_MCONTEXT_GREGS_R11 UC_MCONTEXT_OFFSET(gregs[11])\n+#define UC_MCONTEXT_GREGS_R12 UC_MCONTEXT_OFFSET(gregs[12])\n+#define UC_MCONTEXT_GREGS_R13 UC_MCONTEXT_OFFSET(gregs[13])\n+#define UC_MCONTEXT_GREGS_R14 UC_MCONTEXT_OFFSET(gregs[14])\n+#define UC_MCONTEXT_GREGS_R15 UC_MCONTEXT_OFFSET(gregs[15])\n+#define UC_MCONTEXT_GREGS_R16 UC_MCONTEXT_OFFSET(gregs[16])\n+#define UC_MCONTEXT_GREGS_R17 UC_MCONTEXT_OFFSET(gregs[17])\n+#define UC_MCONTEXT_GREGS_R18 UC_MCONTEXT_OFFSET(gregs[18])\n+#define UC_MCONTEXT_GREGS_R19 UC_MCONTEXT_OFFSET(gregs[19])\n+#define UC_MCONTEXT_GREGS_R20 UC_MCONTEXT_OFFSET(gregs[20])\n+#define UC_MCONTEXT_GREGS_R21 UC_MCONTEXT_OFFSET(gregs[21])\n+#define UC_MCONTEXT_GREGS_R22 UC_MCONTEXT_OFFSET(gregs[22])\n+#define UC_MCONTEXT_GREGS_R23 UC_MCONTEXT_OFFSET(gregs[23])\n+#define UC_MCONTEXT_GREGS_R24 UC_MCONTEXT_OFFSET(gregs[24])\n+#define UC_MCONTEXT_GREGS_R25 UC_MCONTEXT_OFFSET(gregs[25])\n+#define UC_MCONTEXT_GREGS_R26 UC_MCONTEXT_OFFSET(gregs[26])\n+#define UC_MCONTEXT_GREGS_R27 UC_MCONTEXT_OFFSET(gregs[27])\n+#define UC_MCONTEXT_GREGS_R28 UC_MCONTEXT_OFFSET(gregs[28])\n+#define UC_MCONTEXT_GREGS_R29 UC_MCONTEXT_OFFSET(gregs[29])\n+#define UC_MCONTEXT_GREGS_R30 UC_MCONTEXT_OFFSET(gregs[30])\n+#define UC_MCONTEXT_GREGS_R31 UC_MCONTEXT_OFFSET(gregs[31])\n \n-#define UC_MCONTEXT_GREGS_MSR ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[MSR_IDX] - (void *)&dmy_ctxt)\n-#define UC_MCONTEXT_GREGS_ORIG_GPR3 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[ORIG_GPR3_IDX] - (void *)&dmy_ctxt)\n-#define UC_MCONTEXT_GREGS_CTR ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[CTR_IDX] - (void *)&dmy_ctxt)\n-#define UC_MCONTEXT_GREGS_LINK ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[LINK_IDX] - (void *)&dmy_ctxt)\n-#define UC_MCONTEXT_GREGS_XER ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[XER_IDX] - (void *)&dmy_ctxt)\n-#define UC_MCONTEXT_GREGS_CCR ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[CCR_IDX] - (void *)&dmy_ctxt)\n-#define UC_MCONTEXT_GREGS_SOFTE ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[SOFTE_IDX] - (void *)&dmy_ctxt)\n-#define UC_MCONTEXT_GREGS_TRAP ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[TRAP_IDX] - (void *)&dmy_ctxt)\n-#define UC_MCONTEXT_GREGS_DAR ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[DAR_IDX] - (void *)&dmy_ctxt)\n-#define UC_MCONTEXT_GREGS_DSISR ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[DSISR_IDX] - (void *)&dmy_ctxt)\n-#define UC_MCONTEXT_GREGS_RESULT ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[RESULT_IDX] - (void *)&dmy_ctxt)\n+#define UC_MCONTEXT_GREGS_MSR UC_MCONTEXT_OFFSET(gregs[MSR_IDX])\n+#define UC_MCONTEXT_GREGS_ORIG_GPR3 UC_MCONTEXT_OFFSET(gregs[ORIG_GPR3_IDX])\n+#define UC_MCONTEXT_GREGS_CTR UC_MCONTEXT_OFFSET(gregs[CTR_IDX])\n+#define UC_MCONTEXT_GREGS_LINK UC_MCONTEXT_OFFSET(gregs[LINK_IDX])\n+#define UC_MCONTEXT_GREGS_XER UC_MCONTEXT_OFFSET(gregs[XER_IDX])\n+#define UC_MCONTEXT_GREGS_CCR UC_MCONTEXT_OFFSET(gregs[CCR_IDX])\n+#define UC_MCONTEXT_GREGS_SOFTE UC_MCONTEXT_OFFSET(gregs[SOFTE_IDX])\n+#define UC_MCONTEXT_GREGS_TRAP UC_MCONTEXT_OFFSET(gregs[TRAP_IDX])\n+#define UC_MCONTEXT_GREGS_DAR UC_MCONTEXT_OFFSET(gregs[DAR_IDX])\n+#define UC_MCONTEXT_GREGS_DSISR UC_MCONTEXT_OFFSET(gregs[DSISR_IDX])\n+#define UC_MCONTEXT_GREGS_RESULT UC_MCONTEXT_OFFSET(gregs[RESULT_IDX])\n \n-#define UC_MCONTEXT_FREGS_R0 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->fpregs.fpregs[0] - (void *)&dmy_ctxt)\n-#define UC_MCONTEXT_FREGS_R1 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->fpregs.fpregs[1] - (void *)&dmy_ctxt)\n-#define UC_MCONTEXT_FREGS_R2 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->fpregs.fpregs[2] - (void *)&dmy_ctxt)\n-#define UC_MCONTEXT_FREGS_R3 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->fpregs.fpregs[3] - (void *)&dmy_ctxt)\n-#define UC_MCONTEXT_FREGS_R4 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->fpregs.fpregs[4] - (void *)&dmy_ctxt)\n-#define UC_MCONTEXT_FREGS_R5 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->fpregs.fpregs[5] - (void *)&dmy_ctxt)\n-#define UC_MCONTEXT_FREGS_R6 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->fpregs.fpregs[6] - (void *)&dmy_ctxt)\n-#define UC_MCONTEXT_FREGS_R7 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->fpregs.fpregs[7] - (void *)&dmy_ctxt)\n-#define UC_MCONTEXT_FREGS_R8 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->fpregs.fpregs[8] - (void *)&dmy_ctxt)\n-#define UC_MCONTEXT_FREGS_R9 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->fpregs.fpregs[9] - (void *)&dmy_ctxt)\n-#define UC_MCONTEXT_FREGS_R10 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->fpregs.fpregs[10] - (void *)&dmy_ctxt)\n-#define UC_MCONTEXT_FREGS_R11 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->fpregs.fpregs[11] - (void *)&dmy_ctxt)\n-#define UC_MCONTEXT_FREGS_R12 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->fpregs.fpregs[12] - (void *)&dmy_ctxt)\n-#define UC_MCONTEXT_FREGS_R13 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->fpregs.fpregs[13] - (void *)&dmy_ctxt)\n-#define UC_MCONTEXT_FREGS_R14 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->fpregs.fpregs[14] - (void *)&dmy_ctxt)\n-#define UC_MCONTEXT_FREGS_R15 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->fpregs.fpregs[15] - (void *)&dmy_ctxt)\n-#define UC_MCONTEXT_FREGS_R16 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->fpregs.fpregs[16] - (void *)&dmy_ctxt)\n-#define UC_MCONTEXT_FREGS_R17 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->fpregs.fpregs[17] - (void *)&dmy_ctxt)\n-#define UC_MCONTEXT_FREGS_R18 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->fpregs.fpregs[18] - (void *)&dmy_ctxt)\n-#define UC_MCONTEXT_FREGS_R19 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->fpregs.fpregs[19] - (void *)&dmy_ctxt)\n-#define UC_MCONTEXT_FREGS_R20 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->fpregs.fpregs[20] - (void *)&dmy_ctxt)\n-#define UC_MCONTEXT_FREGS_R21 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->fpregs.fpregs[21] - (void *)&dmy_ctxt)\n-#define UC_MCONTEXT_FREGS_R22 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->fpregs.fpregs[22] - (void *)&dmy_ctxt)\n-#define UC_MCONTEXT_FREGS_R23 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->fpregs.fpregs[23] - (void *)&dmy_ctxt)\n-#define UC_MCONTEXT_FREGS_R24 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->fpregs.fpregs[24] - (void *)&dmy_ctxt)\n-#define UC_MCONTEXT_FREGS_R25 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->fpregs.fpregs[25] - (void *)&dmy_ctxt)\n-#define UC_MCONTEXT_FREGS_R26 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->fpregs.fpregs[26] - (void *)&dmy_ctxt)\n-#define UC_MCONTEXT_FREGS_R27 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->fpregs.fpregs[27] - (void *)&dmy_ctxt)\n-#define UC_MCONTEXT_FREGS_R28 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->fpregs.fpregs[28] - (void *)&dmy_ctxt)\n-#define UC_MCONTEXT_FREGS_R29 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->fpregs.fpregs[29] - (void *)&dmy_ctxt)\n-#define UC_MCONTEXT_FREGS_R30 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->fpregs.fpregs[30] - (void *)&dmy_ctxt)\n-#define UC_MCONTEXT_FREGS_R31 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->fpregs.fpregs[31] - (void *)&dmy_ctxt)\n-#define UC_MCONTEXT_FREGS_FPSCR ((void *)&dmy_ctxt.uc_mcontext.uc_regs->fpregs.fpregs[32] - (void *)&dmy_ctxt)\n+#define UC_MCONTEXT_FREGS_R0 UC_MCONTEXT_OFFSET(fpregs.fpregs[0])\n+#define UC_MCONTEXT_FREGS_R1 UC_MCONTEXT_OFFSET(fpregs.fpregs[1])\n+#define UC_MCONTEXT_FREGS_R2 UC_MCONTEXT_OFFSET(fpregs.fpregs[2])\n+#define UC_MCONTEXT_FREGS_R3 UC_MCONTEXT_OFFSET(fpregs.fpregs[3])\n+#define UC_MCONTEXT_FREGS_R4 UC_MCONTEXT_OFFSET(fpregs.fpregs[4])\n+#define UC_MCONTEXT_FREGS_R5 UC_MCONTEXT_OFFSET(fpregs.fpregs[5])\n+#define UC_MCONTEXT_FREGS_R6 UC_MCONTEXT_OFFSET(fpregs.fpregs[6])\n+#define UC_MCONTEXT_FREGS_R7 UC_MCONTEXT_OFFSET(fpregs.fpregs[7])\n+#define UC_MCONTEXT_FREGS_R8 UC_MCONTEXT_OFFSET(fpregs.fpregs[8])\n+#define UC_MCONTEXT_FREGS_R9 UC_MCONTEXT_OFFSET(fpregs.fpregs[9])\n+#define UC_MCONTEXT_FREGS_R10 UC_MCONTEXT_OFFSET(fpregs.fpregs[10])\n+#define UC_MCONTEXT_FREGS_R11 UC_MCONTEXT_OFFSET(fpregs.fpregs[11])\n+#define UC_MCONTEXT_FREGS_R12 UC_MCONTEXT_OFFSET(fpregs.fpregs[12])\n+#define UC_MCONTEXT_FREGS_R13 UC_MCONTEXT_OFFSET(fpregs.fpregs[13])\n+#define UC_MCONTEXT_FREGS_R14 UC_MCONTEXT_OFFSET(fpregs.fpregs[14])\n+#define UC_MCONTEXT_FREGS_R15 UC_MCONTEXT_OFFSET(fpregs.fpregs[15])\n+#define UC_MCONTEXT_FREGS_R16 UC_MCONTEXT_OFFSET(fpregs.fpregs[16])\n+#define UC_MCONTEXT_FREGS_R17 UC_MCONTEXT_OFFSET(fpregs.fpregs[17])\n+#define UC_MCONTEXT_FREGS_R18 UC_MCONTEXT_OFFSET(fpregs.fpregs[18])\n+#define UC_MCONTEXT_FREGS_R19 UC_MCONTEXT_OFFSET(fpregs.fpregs[19])\n+#define UC_MCONTEXT_FREGS_R20 UC_MCONTEXT_OFFSET(fpregs.fpregs[20])\n+#define UC_MCONTEXT_FREGS_R21 UC_MCONTEXT_OFFSET(fpregs.fpregs[21])\n+#define UC_MCONTEXT_FREGS_R22 UC_MCONTEXT_OFFSET(fpregs.fpregs[22])\n+#define UC_MCONTEXT_FREGS_R23 UC_MCONTEXT_OFFSET(fpregs.fpregs[23])\n+#define UC_MCONTEXT_FREGS_R24 UC_MCONTEXT_OFFSET(fpregs.fpregs[24])\n+#define UC_MCONTEXT_FREGS_R25 UC_MCONTEXT_OFFSET(fpregs.fpregs[25])\n+#define UC_MCONTEXT_FREGS_R26 UC_MCONTEXT_OFFSET(fpregs.fpregs[26])\n+#define UC_MCONTEXT_FREGS_R27 UC_MCONTEXT_OFFSET(fpregs.fpregs[27])\n+#define UC_MCONTEXT_FREGS_R28 UC_MCONTEXT_OFFSET(fpregs.fpregs[28])\n+#define UC_MCONTEXT_FREGS_R29 UC_MCONTEXT_OFFSET(fpregs.fpregs[29])\n+#define UC_MCONTEXT_FREGS_R30 UC_MCONTEXT_OFFSET(fpregs.fpregs[30])\n+#define UC_MCONTEXT_FREGS_R31 UC_MCONTEXT_OFFSET(fpregs.fpregs[31])\n+#define UC_MCONTEXT_FREGS_FPSCR UC_MCONTEXT_OFFSET(fpregs.fpregs[32])\n \n #endif\n"
  },
  {
    "path": "package/libs/libusb/Makefile",
    "content": "#\n# Copyright (C) 2010-2016 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=libusb\nPKG_VERSION:=1.0.24\nPKG_RELEASE:=$(AUTORELEASE)\n\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.bz2\nPKG_SOURCE_URL:=\\\n  https://github.com/libusb/libusb/releases/download/v$(PKG_VERSION) \\\n  @SF/$(PKG_NAME)\nPKG_HASH:=7efd2685f7b327326dcfb85cee426d9b871fd70e22caa15bb68d595ce2a2b12a\n\nPKG_MAINTAINER:= Felix Fietkau <nbd@nbd.name>\nPKG_LICENSE:=LGPL-2.1-or-later\nPKG_LICENSE_FILES:=COPYING\n\nPKG_INSTALL:=1\nPKG_BUILD_PARALLEL:=1\n\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine Package/libusb-1.0\n  SECTION:=libs\n  CATEGORY:=Libraries\n  TITLE:=A library for accessing Linux USB devices\n  DEPENDS:=+libpthread +librt\n  URL:=http://libusb.info/\n  ABI_VERSION:=0\nendef\n\ndefine Package/libusb-1.0/description\n  libusb is a C library that gives applications easy access to USB devices on\n  many different operating systems.\nendef\n\nTARGET_CFLAGS += $(FPIC)\nCONFIGURE_ARGS += \\\n\t--disable-udev \\\n\t--disable-log\n\ndefine Build/InstallDev\n\t$(INSTALL_DIR) $(1)/usr/include/libusb-1.0\n\t$(CP) $(PKG_INSTALL_DIR)/usr/include/libusb-1.0/libusb.h $(1)/usr/include/libusb-1.0/\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/libusb-1.0.* $(1)/usr/lib/\n\t$(INSTALL_DIR) $(1)/usr/lib/pkgconfig\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/pkgconfig/libusb-1.0.pc $(1)/usr/lib/pkgconfig/\nendef\n\ndefine Package/libusb-1.0/install\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/libusb-1.0.so.* $(1)/usr/lib/\nendef\n\n$(eval $(call BuildPackage,libusb-1.0))\n"
  },
  {
    "path": "package/libs/libusb/patches/001-Correct-a-typo-in-the-Changelog-and-clean-up-a-stray.patch",
    "content": "From 369af149e3ad92514a2d24f112cedfeb7acaf558 Mon Sep 17 00:00:00 2001\nFrom: Chris Dickens <christopher.a.dickens@gmail.com>\nDate: Sun, 13 Dec 2020 15:46:27 -0800\nSubject: [PATCH] Correct a typo in the Changelog and clean up a stray file\n\nSigned-off-by: Chris Dickens <christopher.a.dickens@gmail.com>\n---\n ChangeLog             | 2 +-\n libusb/version_nano.h | 2 +-\n test                  | 0\n 3 files changed, 2 insertions(+), 2 deletions(-)\n delete mode 100644 test\n\n--- a/ChangeLog\n+++ b/ChangeLog\n@@ -12,7 +12,7 @@ visit: http://log.libusb.info\n * Darwin (macOS): use IOUSBDevice as darwin_device_class explicitly (#693)\n * Linux: Drop support for kernel older than 2.6.32\n * Linux: Provide an event thread name (#689)\n-* Linux: Wait until all USBs have been reaped before freeing them (#607)\n+* Linux: Wait until all URBs have been reaped before freeing them (#607)\n * NetBSD: Recognize device timeouts (#710)\n * OpenBSD: Allow opening ugen devices multiple times (#763)\n * OpenBSD: Support libusb_get_port_number() (#764)\n--- a/libusb/version_nano.h\n+++ b/libusb/version_nano.h\n@@ -1 +1 @@\n-#define LIBUSB_NANO 11584\n+#define LIBUSB_NANO 11585\n"
  },
  {
    "path": "package/libs/libusb/patches/002-linux_usbfs-Fix-parsing-of-descriptors-for-multi-con.patch",
    "content": "From f6d2cb561402c3b6d3627c0eb89e009b503d9067 Mon Sep 17 00:00:00 2001\nFrom: Chris Dickens <christopher.a.dickens@gmail.com>\nDate: Sun, 13 Dec 2020 15:49:19 -0800\nSubject: [PATCH] linux_usbfs: Fix parsing of descriptors for\n multi-configuration devices\n\nCommit e2be556bd2 (\"linux_usbfs: Parse config descriptors during device\ninitialization\") introduced a regression for devices with multiple\nconfigurations. The logic that verifies the reported length of the\nconfiguration descriptors failed to count the length of the\nconfiguration descriptor itself and would truncate the actual length by\n9 bytes, leading to a parsing error for subsequent descriptors.\n\nCloses #825\n\nSigned-off-by: Chris Dickens <christopher.a.dickens@gmail.com>\n---\n libusb/os/linux_usbfs.c | 12 ++++++++----\n libusb/version_nano.h   |  2 +-\n 2 files changed, 9 insertions(+), 5 deletions(-)\n\n--- a/libusb/os/linux_usbfs.c\n+++ b/libusb/os/linux_usbfs.c\n@@ -641,7 +641,12 @@ static int seek_to_next_config(struct li\n \tuint8_t *buffer, size_t len)\n {\n \tstruct usbi_descriptor_header *header;\n-\tint offset = 0;\n+\tint offset;\n+\n+\t/* Start seeking past the config descriptor */\n+\toffset = LIBUSB_DT_CONFIG_SIZE;\n+\tbuffer += LIBUSB_DT_CONFIG_SIZE;\n+\tlen -= LIBUSB_DT_CONFIG_SIZE;\n \n \twhile (len > 0) {\n \t\tif (len < 2) {\n@@ -718,7 +723,7 @@ static int parse_config_descriptors(stru\n \t\t}\n \n \t\tif (priv->sysfs_dir) {\n-\t\t\t /*\n+\t\t\t/*\n \t\t\t * In sysfs wTotalLength is ignored, instead the kernel returns a\n \t\t\t * config descriptor with verified bLength fields, with descriptors\n \t\t\t * with an invalid bLength removed.\n@@ -727,8 +732,7 @@ static int parse_config_descriptors(stru\n \t\t\tint offset;\n \n \t\t\tif (num_configs > 1 && idx < num_configs - 1) {\n-\t\t\t\toffset = seek_to_next_config(ctx, buffer + LIBUSB_DT_CONFIG_SIZE,\n-\t\t\t\t\t\t\t     remaining - LIBUSB_DT_CONFIG_SIZE);\n+\t\t\t\toffset = seek_to_next_config(ctx, buffer, remaining);\n \t\t\t\tif (offset < 0)\n \t\t\t\t\treturn offset;\n \t\t\t\tsysfs_config_len = (uint16_t)offset;\n--- a/libusb/version_nano.h\n+++ b/libusb/version_nano.h\n@@ -1 +1 @@\n-#define LIBUSB_NANO 11585\n+#define LIBUSB_NANO 11586\n"
  },
  {
    "path": "package/libs/mbedtls/Makefile",
    "content": "#\n# Copyright (C) 2011-2015 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=mbedtls\nPKG_VERSION:=2.28.0\nPKG_RELEASE:=$(AUTORELEASE)\nPKG_USE_MIPS16:=0\n\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz\nPKG_SOURCE_URL:=https://codeload.github.com/ARMmbed/mbedtls/tar.gz/v$(PKG_VERSION)?\nPKG_HASH:=6519579b836ed78cc549375c7c18b111df5717e86ca0eeff4cb64b2674f424cc\n\nPKG_LICENSE:=GPL-2.0-or-later\nPKG_LICENSE_FILES:=gpl-2.0.txt\nPKG_CPE_ID:=cpe:/a:arm:mbed_tls\n\nPKG_CONFIG_DEPENDS := \\\n\tCONFIG_LIBMBEDTLS_DEBUG_C \\\n\tCONFIG_LIBMBEDTLS_HKDF_C\n\ninclude $(INCLUDE_DIR)/package.mk\ninclude $(INCLUDE_DIR)/cmake.mk\n\ndefine Package/mbedtls/Default\n  TITLE:=Embedded SSL\n  URL:=https://tls.mbed.org\nendef\n\ndefine Package/mbedtls/Default/description\nThe aim of the mbedtls project is to provide a quality, open-source\ncryptographic library written in C and targeted at embedded systems.\nendef\n\ndefine Package/libmbedtls\n$(call Package/mbedtls/Default)\n  SECTION:=libs\n  CATEGORY:=Libraries\n  SUBMENU:=SSL\n  TITLE+= (library)\n  ABI_VERSION:=12\nendef\n\ndefine Package/libmbedtls/config\nconfig LIBMBEDTLS_DEBUG_C\n\tdepends on PACKAGE_libmbedtls\n\tbool \"Enable debug functions\"\n\tdefault n\n\thelp\n\t This option enables mbedtls library's debug functions.\n\n\t It increases the uncompressed libmbedtls binary size\n\t by around 60 KiB (for an ARMv5 platform).\n\n\t Usually, you don't need this, so don't select this if you're unsure.\n\nconfig LIBMBEDTLS_HKDF_C\n\tdepends on PACKAGE_libmbedtls\n\tbool \"Enable the HKDF algorithm (RFC 5869)\"\n\tdefault n\n\thelp\n\t This option adds support for the Hashed Message Authentication Code\n\t (HMAC)-based key derivation function (HKDF).\nendef\n\ndefine Package/mbedtls-util\n$(call Package/mbedtls/Default)\n  SECTION:=utils\n  CATEGORY:=Utilities\n  TITLE+= (utilities)\n  DEPENDS:=+libmbedtls\nendef\n\ndefine Package/libmbedtls/description\n$(call Package/mbedtls/Default/description)\nThis package contains the mbedtls library.\nendef\n\ndefine Package/mbedtls-util/description\n$(call Package/mbedtls/Default/description)\nThis package contains mbedtls helper programs for private key and\nCSR generation (gen_key, cert_req)\nendef\n\nTARGET_CFLAGS += -ffunction-sections -fdata-sections\nTARGET_CFLAGS := $(filter-out -O%,$(TARGET_CFLAGS))\n\nCMAKE_OPTIONS += \\\n\t-DUSE_SHARED_MBEDTLS_LIBRARY:Bool=ON \\\n\t-DENABLE_TESTING:Bool=OFF \\\n\t-DENABLE_PROGRAMS:Bool=ON\n\ndefine Build/Configure\n\t$(Build/Configure/Default)\n\n\tawk 'BEGIN { rc = 1 } \\\n\t     /#define MBEDTLS_DEBUG_C/ { $$$$0 = \"$(if $(CONFIG_LIBMBEDTLS_DEBUG_C),,// )#define MBEDTLS_DEBUG_C\"; rc = 0 } \\\n\t     { print } \\\n\t     END { exit(rc) }' $(PKG_BUILD_DIR)/include/mbedtls/config.h \\\n\t     >$(PKG_BUILD_DIR)/include/mbedtls/config.h.new && \\\n\tmv $(PKG_BUILD_DIR)/include/mbedtls/config.h.new $(PKG_BUILD_DIR)/include/mbedtls/config.h\n\n\tawk 'BEGIN { rc = 1 } \\\n\t     /#define MBEDTLS_HKDF_C/ { $$$$0 = \"$(if $(CONFIG_LIBMBEDTLS_HKDF_C),,// )#define MBEDTLS_HKDF_C\"; rc = 0 } \\\n\t     { print } \\\n\t     END { exit(rc) }' $(PKG_BUILD_DIR)/include/mbedtls/config.h \\\n\t     >$(PKG_BUILD_DIR)/include/mbedtls/config.h.new && \\\n\tmv $(PKG_BUILD_DIR)/include/mbedtls/config.h.new $(PKG_BUILD_DIR)/include/mbedtls/config.h\n\n\tsed -i '/fuzz/d' $(PKG_BUILD_DIR)/programs/CMakeLists.txt\n\tsed -i '/test/d' $(PKG_BUILD_DIR)/programs/CMakeLists.txt\nendef\n\ndefine Build/InstallDev\n\t$(INSTALL_DIR) $(1)/usr/include\n\t$(CP) $(PKG_INSTALL_DIR)/usr/include/mbedtls $(1)/usr/include/\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/lib*.so* $(1)/usr/lib/\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/lib*.a $(1)/usr/lib/\nendef\n\ndefine Package/libmbedtls/install\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/lib*.so.* $(1)/usr/lib/\nendef\n\ndefine Package/mbedtls-util/install\n\t$(INSTALL_DIR) $(1)/usr/bin\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/bin/gen_key $(1)/usr/bin/\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/bin/cert_req $(1)/usr/bin/\nendef\n\n$(eval $(call BuildPackage,libmbedtls))\n$(eval $(call BuildPackage,mbedtls-util))\n"
  },
  {
    "path": "package/libs/mbedtls/patches/200-config.patch",
    "content": "--- a/include/mbedtls/config.h\n+++ b/include/mbedtls/config.h\n@@ -665,14 +665,14 @@\n  *\n  * Enable Output Feedback mode (OFB) for symmetric ciphers.\n  */\n-#define MBEDTLS_CIPHER_MODE_OFB\n+//#define MBEDTLS_CIPHER_MODE_OFB\n \n /**\n  * \\def MBEDTLS_CIPHER_MODE_XTS\n  *\n  * Enable Xor-encrypt-xor with ciphertext stealing mode (XTS) for AES.\n  */\n-#define MBEDTLS_CIPHER_MODE_XTS\n+//#define MBEDTLS_CIPHER_MODE_XTS\n \n /**\n  * \\def MBEDTLS_CIPHER_NULL_CIPHER\n@@ -790,20 +790,20 @@\n  * Comment macros to disable the curve and functions for it\n  */\n /* Short Weierstrass curves (supporting ECP, ECDH, ECDSA) */\n-#define MBEDTLS_ECP_DP_SECP192R1_ENABLED\n-#define MBEDTLS_ECP_DP_SECP224R1_ENABLED\n+//#define MBEDTLS_ECP_DP_SECP192R1_ENABLED\n+//#define MBEDTLS_ECP_DP_SECP224R1_ENABLED\n #define MBEDTLS_ECP_DP_SECP256R1_ENABLED\n #define MBEDTLS_ECP_DP_SECP384R1_ENABLED\n-#define MBEDTLS_ECP_DP_SECP521R1_ENABLED\n-#define MBEDTLS_ECP_DP_SECP192K1_ENABLED\n-#define MBEDTLS_ECP_DP_SECP224K1_ENABLED\n+//#define MBEDTLS_ECP_DP_SECP521R1_ENABLED\n+//#define MBEDTLS_ECP_DP_SECP192K1_ENABLED\n+//#define MBEDTLS_ECP_DP_SECP224K1_ENABLED\n #define MBEDTLS_ECP_DP_SECP256K1_ENABLED\n-#define MBEDTLS_ECP_DP_BP256R1_ENABLED\n-#define MBEDTLS_ECP_DP_BP384R1_ENABLED\n-#define MBEDTLS_ECP_DP_BP512R1_ENABLED\n+//#define MBEDTLS_ECP_DP_BP256R1_ENABLED\n+//#define MBEDTLS_ECP_DP_BP384R1_ENABLED\n+//#define MBEDTLS_ECP_DP_BP512R1_ENABLED\n /* Montgomery curves (supporting ECP) */\n #define MBEDTLS_ECP_DP_CURVE25519_ENABLED\n-#define MBEDTLS_ECP_DP_CURVE448_ENABLED\n+//#define MBEDTLS_ECP_DP_CURVE448_ENABLED\n \n /**\n  * \\def MBEDTLS_ECP_NIST_OPTIM\n@@ -956,7 +956,7 @@\n  *             See dhm.h for more details.\n  *\n  */\n-#define MBEDTLS_KEY_EXCHANGE_DHE_PSK_ENABLED\n+//#define MBEDTLS_KEY_EXCHANGE_DHE_PSK_ENABLED\n \n /**\n  * \\def MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED\n@@ -976,7 +976,7 @@\n  *      MBEDTLS_TLS_ECDHE_PSK_WITH_3DES_EDE_CBC_SHA\n  *      MBEDTLS_TLS_ECDHE_PSK_WITH_RC4_128_SHA\n  */\n-#define MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED\n+//#define MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED\n \n /**\n  * \\def MBEDTLS_KEY_EXCHANGE_RSA_PSK_ENABLED\n@@ -1001,7 +1001,7 @@\n  *      MBEDTLS_TLS_RSA_PSK_WITH_3DES_EDE_CBC_SHA\n  *      MBEDTLS_TLS_RSA_PSK_WITH_RC4_128_SHA\n  */\n-#define MBEDTLS_KEY_EXCHANGE_RSA_PSK_ENABLED\n+//#define MBEDTLS_KEY_EXCHANGE_RSA_PSK_ENABLED\n \n /**\n  * \\def MBEDTLS_KEY_EXCHANGE_RSA_ENABLED\n@@ -1135,7 +1135,7 @@\n  *      MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_128_GCM_SHA256\n  *      MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_256_GCM_SHA384\n  */\n-#define MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA_ENABLED\n+//#define MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA_ENABLED\n \n /**\n  * \\def MBEDTLS_KEY_EXCHANGE_ECDH_RSA_ENABLED\n@@ -1159,7 +1159,7 @@\n  *      MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_128_GCM_SHA256\n  *      MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_256_GCM_SHA384\n  */\n-#define MBEDTLS_KEY_EXCHANGE_ECDH_RSA_ENABLED\n+//#define MBEDTLS_KEY_EXCHANGE_ECDH_RSA_ENABLED\n \n /**\n  * \\def MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED\n@@ -1263,7 +1263,7 @@\n  * This option is only useful if both MBEDTLS_SHA256_C and\n  * MBEDTLS_SHA512_C are defined. Otherwise the available hash module is used.\n  */\n-//#define MBEDTLS_ENTROPY_FORCE_SHA256\n+#define MBEDTLS_ENTROPY_FORCE_SHA256\n \n /**\n  * \\def MBEDTLS_ENTROPY_NV_SEED\n@@ -1478,14 +1478,14 @@\n  * Uncomment this macro to disable the use of CRT in RSA.\n  *\n  */\n-//#define MBEDTLS_RSA_NO_CRT\n+#define MBEDTLS_RSA_NO_CRT\n \n /**\n  * \\def MBEDTLS_SELF_TEST\n  *\n  * Enable the checkup functions (*_self_test).\n  */\n-#define MBEDTLS_SELF_TEST\n+//#define MBEDTLS_SELF_TEST\n \n /**\n  * \\def MBEDTLS_SHA256_SMALLER\n@@ -1756,7 +1756,7 @@\n  *          configuration of this extension).\n  *\n  */\n-#define MBEDTLS_SSL_RENEGOTIATION\n+//#define MBEDTLS_SSL_RENEGOTIATION\n \n /**\n  * \\def MBEDTLS_SSL_SRV_SUPPORT_SSLV2_CLIENT_HELLO\n@@ -2017,7 +2017,7 @@\n  *\n  * Comment this macro to disable support for truncated HMAC in SSL\n  */\n-#define MBEDTLS_SSL_TRUNCATED_HMAC\n+//#define MBEDTLS_SSL_TRUNCATED_HMAC\n \n /**\n  * \\def MBEDTLS_SSL_TRUNCATED_HMAC_COMPAT\n@@ -2185,7 +2185,7 @@\n  *\n  * Comment this to disable run-time checking and save ROM space\n  */\n-#define MBEDTLS_VERSION_FEATURES\n+//#define MBEDTLS_VERSION_FEATURES\n \n /**\n  * \\def MBEDTLS_X509_ALLOW_EXTENSIONS_NON_V3\n@@ -2534,7 +2534,7 @@\n  *      MBEDTLS_TLS_PSK_WITH_CAMELLIA_128_GCM_SHA256\n  *      MBEDTLS_TLS_PSK_WITH_CAMELLIA_128_CBC_SHA256\n  */\n-#define MBEDTLS_CAMELLIA_C\n+//#define MBEDTLS_CAMELLIA_C\n \n /**\n  * \\def MBEDTLS_ARIA_C\n@@ -2600,7 +2600,7 @@\n  * This module enables the AES-CCM ciphersuites, if other requisites are\n  * enabled as well.\n  */\n-#define MBEDTLS_CCM_C\n+//#define MBEDTLS_CCM_C\n \n /**\n  * \\def MBEDTLS_CERTS_C\n@@ -2612,7 +2612,7 @@\n  *\n  * This module is used for testing (ssl_client/server).\n  */\n-#define MBEDTLS_CERTS_C\n+//#define MBEDTLS_CERTS_C\n \n /**\n  * \\def MBEDTLS_CHACHA20_C\n@@ -2725,7 +2725,7 @@\n  * \\warning   DES is considered a weak cipher and its use constitutes a\n  *            security risk. We recommend considering stronger ciphers instead.\n  */\n-#define MBEDTLS_DES_C\n+//#define MBEDTLS_DES_C\n \n /**\n  * \\def MBEDTLS_DHM_C\n@@ -2890,7 +2890,7 @@\n  * This module adds support for the Hashed Message Authentication Code\n  * (HMAC)-based key derivation function (HKDF).\n  */\n-#define MBEDTLS_HKDF_C\n+//#define MBEDTLS_HKDF_C\n \n /**\n  * \\def MBEDTLS_HMAC_DRBG_C\n@@ -3203,7 +3203,7 @@\n  *\n  * This module enables abstraction of common (libc) functions.\n  */\n-#define MBEDTLS_PLATFORM_C\n+//#define MBEDTLS_PLATFORM_C\n \n /**\n  * \\def MBEDTLS_POLY1305_C\n@@ -3279,7 +3279,7 @@\n  * Caller:  library/md.c\n  *\n  */\n-#define MBEDTLS_RIPEMD160_C\n+//#define MBEDTLS_RIPEMD160_C\n \n /**\n  * \\def MBEDTLS_RSA_C\n@@ -3486,7 +3486,7 @@\n  *\n  * This module provides run-time version information.\n  */\n-#define MBEDTLS_VERSION_C\n+//#define MBEDTLS_VERSION_C\n \n /**\n  * \\def MBEDTLS_X509_USE_C\n@@ -3596,7 +3596,7 @@\n  * Module:  library/xtea.c\n  * Caller:\n  */\n-#define MBEDTLS_XTEA_C\n+//#define MBEDTLS_XTEA_C\n \n /* \\} name SECTION: mbed TLS modules */\n \n"
  },
  {
    "path": "package/libs/musl-fts/Makefile",
    "content": "#\n# Copyright (C) 2017 Lucian Cristian <lucian.cristian@gmail.com>\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n# updated to work with latest source from abrasive\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=musl-fts\nPKG_VERSION:=1.2.7\nPKG_RELEASE:=1\n\nPKG_SOURCE_PROTO:=git\nPKG_SOURCE_URL:=https://github.com/pullmoll/musl-fts.git\nPKG_SOURCE_VERSION:=0bde52df588e8969879a2cae51c3a4774ec62472\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz\nPKG_MIRROR_HASH:=29c62a600128e9189b1b2e1aea568546178eedf739527f657873b3b773072ecb\n\nPKG_MAINTAINER:=Lucian Cristian <lucian.cristian@gmail.com>\n\nPKG_LICENSE:=LGPL-2.1\nPKG_LICENSE_FILES:=COPYING AUTHORS\n\nPKG_FIXUP:=autoreconf\nPKG_REMOVE_FILES:=autogen.sh\n\nPKG_BUILD_PARALLEL:=1\nPKG_INSTALL:=1\n\ninclude $(INCLUDE_DIR)/package.mk\ninclude $(INCLUDE_DIR)/host-build.mk\n\ndefine Package/musl-fts\n  SECTION:=libs\n  CATEGORY:=Libraries\n  TITLE:=fts implementation for musl libc\n  URL:=https://github.com/pullmoll/musl-fts\n  DEPENDS:= +libpthread\nendef\n\ndefine Package/musl-fts/description\n  The musl-fts package implements the fts(3) functions fts_open, fts_read, fts_children, fts_set and fts_close, which are missing in musl libc.\nendef\n\nHOST_CONFIGURE_ARGS += --disable-shared --with-pic\n\ndefine Build/InstallDev\n\t$(INSTALL_DIR) $(1)/usr/include\n\t$(CP) $(PKG_INSTALL_DIR)/usr/include/fts.h $(1)/usr/include/\n\t$(INSTALL_DIR) $(1)/usr/lib/pkgconfig\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/libfts.so* $(1)/usr/lib/\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/pkgconfig/musl-fts.pc $(1)/usr/lib/pkgconfig/\nendef\n\ndefine Package/musl-fts/install\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/libfts.so* $(1)/usr/lib/\nendef\n\n$(eval $(call BuildPackage,musl-fts))\n$(eval $(call HostBuild))\n"
  },
  {
    "path": "package/libs/ncurses/Makefile",
    "content": "#\n# Copyright (C) 2006-2015 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=ncurses\nPKG_VERSION:=6.3\nPKG_RELEASE:=$(AUTORELEASE)\n\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz\nPKG_SOURCE_URL:=@GNU/$(PKG_NAME)\nPKG_HASH:=97fc51ac2b085d4cde31ef4d2c3122c21abc217e9090a43a30fc5ec21684e059\n\nPKG_LICENSE:=MIT\nPKG_LICENSE_FILES:=README\n\nPKG_INSTALL:=1\nPKG_BUILD_PARALLEL:=1\n\nPKG_BUILD_DEPENDS:=ncurses/host\n\ninclude $(INCLUDE_DIR)/package.mk\ninclude $(INCLUDE_DIR)/host-build.mk\n\ndefine Package/terminfo\n  SECTION:=libs\n  CATEGORY:=Libraries\n  TITLE:=Terminal Info Database (ncurses)\n  URL:=http://www.gnu.org/software/ncurses/\nendef\n\ndefine Package/libncurses\n  SECTION:=libs\n  CATEGORY:=Libraries\n  TITLE:=Terminal handling library (Unicode)\n  URL:=http://www.gnu.org/software/ncurses/\n  PROVIDES:=libncursesw\n  DEPENDS:= +terminfo\n  ABI_VERSION:=6\nendef\n\ndefine Package/libncurses-dev\n  SECTION:=devel\n  CATEGORY:=Development\n  SUBMENU:=Libraries\n  DEPENDS:=zlib\n  TITLE:=Development files for the ncurses library\nendef\n\nTARGET_CFLAGS += $(FPIC)\n\nCONFIGURE_ARGS += \\\n\t--enable-echo \\\n\t--enable-const \\\n\t--enable-overwrite \\\n\t--enable-pc-files \\\n\t--disable-rpath \\\n\t--without-ada \\\n\t--without-debug \\\n\t--without-manpages \\\n\t--without-profile \\\n\t--without-progs \\\n\t--without-tests \\\n\t--disable-big-core \\\n\t--disable-home-terminfo \\\n\t--with-normal \\\n\t--with-shared \\\n\t--with-terminfo-dirs=/usr/share/terminfo \\\n\t--with-default-terminfo-dir=/usr/share/terminfo \\\n\t--with-pkg-config-libdir=/usr/lib/pkgconfig \\\n\t--enable-widec \\\n\t--with-build-cppflags=-D_GNU_SOURCE\n\nCONFIGURE_VARS += \\\n\tcf_try_fPIC=no\n\nHOST_CFLAGS += $(HOST_FPIC)\n\nHOST_CONFIGURE_ARGS += \\\n\t--without-cxx \\\n\t--without-cxx-binding \\\n\t--without-ada \\\n\t--without-debug \\\n\t--without-manpages \\\n\t--without-profile \\\n\t--without-tests \\\n\t--without-curses-h\n\n\nifeq ($(HOST_OS),FreeBSD)\n\tCONFIGURE_ARGS +=\n\t\t--with-terminfo=/usr/share/terminfo.db \nendif\n\nMAKE_FLAGS += \\\n\tBUILD_CC=\"$(HOSTCC)\" \\\n\tHOSTCC=\"$(HOSTCC)\" \\\n\tHOSTCCFLAGS=\"\" \\\n\tPKG_CONFIG_LIBDIR=/usr/lib/pkgconfig \\\n\tlibs\n\ndefine Build/Install/Default\n\t$(MAKE_VARS) \\\n\t$(MAKE) -C $(PKG_BUILD_DIR)/$(MAKE_PATH) \\\n\t\t$(MAKE_INSTALL_FLAGS) \\\n\t\t$(1) install.libs install.data;\nendef\n\ndefine Package/terminfo/install\n\techo \"\"\nifneq ($(HOST_OS),FreeBSD)\n\t$(INSTALL_DIR) $(1)/usr/share/terminfo\n\t(cd $(PKG_INSTALL_DIR)/usr/share/terminfo; \\\n\t\tfor dir in ??; do \\\n\t\t\t[ -d \"$$$$dir\" ] || continue; \\\n\t\t\tmv $$$$dir $$$$(echo -ne \"\\x$$$$dir\"); \\\n\t\tdone \\\n\t)\n\tfor file in \\\n\t\ta/ansi \\\n\t\td/dumb \\\n\t\tl/linux \\\n\t\tr/rxvt \\\n\t\tr/rxvt-unicode \\\n\t\ts/screen \\\n\t\ts/screen-256color \\\n\t\tt/tmux \\\n\t\tt/tmux-256color \\\n\t\tv/vt100 \\\n\t\tv/vt102 \\\n\t\tx/xterm \\\n\t\tx/xterm-color \\\n\t\tx/xterm-256color; do \\\n\t\t$(INSTALL_DIR) $(1)/usr/share/terminfo/`dirname $$$$file`; \\\n\t\t$(CP) $(PKG_INSTALL_DIR)/usr/share/terminfo/$$$$file \\\n\t\t\t$(1)/usr/share/terminfo/$$$$file; \\\n\tdone\nendif\nendef\n\ndefine Package/libncurses/install\n\t$(INSTALL_DIR) $(1)/usr/lib\n\tfor lib in ncurses panel menu form; do \\\n\t\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/lib$$$${lib}w.so.* $(1)/usr/lib/; \\\n\t\tfor so in $(1)/usr/lib/lib$$$${lib}w.so.*; do \\\n\t\t\tln -s $$$${so##*/} $$$${so%w.so*}.so$$$${so##*w.so}; \\\n\t\tdone; \\\n\tdone\nendef\n\ndefine Package/libncurses-dev/install\n\t$(INSTALL_DIR) $(1)/usr/bin\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/bin/* $(1)/usr/bin/\n\t$(INSTALL_DIR) $(1)/usr/include\n\t$(CP) $(PKG_INSTALL_DIR)/usr/include/*.h $(1)/usr/include/\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/*.a $(1)/usr/lib/\n\t$(INSTALL_DIR) $(1)/usr/lib/pkgconfig\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/pkgconfig/*.pc $(1)/usr/lib/pkgconfig/\nendef\n\ndefine Build/InstallDev\n\t$(CP) $(PKG_INSTALL_DIR)/* $(1)\n\tfor lib in ncurses panel menu form; do \\\n\t\tfor so in $(1)/usr/lib/lib$$$${lib}w.so*; do \\\n\t\t\tln -s $$$${so##*/} $$$${so%w.so*}.so$$$${so##*w.so}; \\\n\t\tdone; \\\n\tdone\n\tln -s . $(1)/usr/include/ncursesw\n\t$(TARGET_CROSS)ar rc $(1)/usr/lib/libtinfo.a\n\t$(INSTALL_DIR) $(2)/bin\n\t$(CP) $(PKG_INSTALL_DIR)/usr/bin/ncursesw6-config $(2)/bin/\n\t$(SED) 's,^\\(prefix\\|exec_prefix\\)=.*,\\1=$(STAGING_DIR)/usr,g' -e 's/$$$$INCS //g' \\\n\t\t$(2)/bin/ncursesw6-config\n\tln -sf $(STAGING_DIR)/host/bin/ncursesw6-config $(1)/usr/bin/ncursesw6-config\nendef\n\ndefine Host/Compile\n\t$(MAKE) -C $(HOST_BUILD_DIR) libs\n\t$(MAKE) -C $(HOST_BUILD_DIR)/progs tic\nendef\n\n$(eval $(call HostBuild))\n$(eval $(call BuildPackage,terminfo))\n$(eval $(call BuildPackage,libncurses))\n$(eval $(call BuildPackage,libncurses-dev))\n"
  },
  {
    "path": "package/libs/ncurses/patches/100-ncurses-5.6-20080112-urxvt.patch",
    "content": "--- a/misc/terminfo.src\n+++ b/misc/terminfo.src\n@@ -6616,6 +6616,172 @@ rxvt-cygwin-native|rxvt terminal emulato\n rxvt-16color|rxvt with 16 colors like aixterm,\n \tncv#32, use=ibm+16color, use=rxvt,\n \n+# rxvt-unicode\n+# http://cvs.schmorp.de/rxvt-unicode/doc/etc/rxvt-unicode.terminfo?revision=1.20\n+# From: Thomas Dickey <dickey@clark.net> 04 Oct 1997\n+# Updated: Özgür Kesim <kesim@math.fu-berlin.de> 02 Nov 1997\n+# Updated: Marc Lehmann <pcg@goof.com>, 17 Feb 2005\n+rxvt-unicode|rxvt-unicode terminal (X Window System),\n+\tam,\n+\tbce,\n+\teo,\n+\tkm,\n+\tmsgr,\n+\txenl,\n+\ths,\n+\tcols#80,\n+\tit#8,\n+\tlines#24,\n+\tacsc=``aaffggjjkkllmmnnooppqqrrssttuuvvwwxxyyzz{{||}}~~-A.B+C\\,D0EhFiG,\n+\tbel=^G,\n+\tblink=\\E[5m,\n+\tbold=\\E[1m,\n+\tcivis=\\E[?25l,\n+\tclear=\\E[H\\E[2J,\n+\tcnorm=\\E[?25h,\n+\tcr=^M,\n+\tcsr=\\E[%i%p1%d;%p2%dr,\n+\tcub=\\E[%p1%dD,\n+\tcub1=^H,\n+\tcud=\\E[%p1%dB,\n+\tcud1=^J,\n+\tcuf=\\E[%p1%dC,\n+\tcuf1=\\E[C,\n+\tcup=\\E[%i%p1%d;%p2%dH,\n+\tcuu=\\E[%p1%dA,\n+\tcuu1=\\E[A,\n+\tcvvis=\\E[?25h,\n+\tdch=\\E[%p1%dP,\n+\tdch1=\\E[P,\n+\tdl=\\E[%p1%dM,\n+\tdl1=\\E[M,\n+\ted=\\E[J,\n+\tel=\\E[K,\n+\tel1=\\E[1K,\n+\tflash=\\E[?5h$<20/>\\E[?5l,\n+\thome=\\E[H,\n+\thpa=\\E[%i%p1%dG,\n+\tht=^I,\n+\thts=\\EH,\n+\tich=\\E[%p1%d@,\n+\tich1=\\E[@,\n+\til=\\E[%p1%dL,\n+\til1=\\E[L,\n+\tind=^J,\n+\tis1=\\E[?47l\\E=\\E[?1l,\n+\tis2=\\E[r\\E[m\\E[2J\\E[H\\E[?7h\\E[?1;3;4;6l\\E[4l,\n+\tkDC=\\E[3$,\n+\tkIC=\\E2$,\n+\tkEND=\\E[8$,\n+\tkHOM=\\E[7$,\n+\tkLFT=\\E[d,\n+\tkNXT=\\E[6$,\n+\tkPRV=\\E[5$,\n+\tkRIT=\\E[c,\n+\tkbs=\\177,\n+\tka1=\\EOw,\n+\tka3=\\EOy,\n+\tkb2=\\EOu,\n+\tkc1=\\EOq,\n+\tkc3=\\EOs,\n+\tkcbt=\\E[Z,\n+\tkcub1=\\E[D,\n+\tkcud1=\\E[B,\n+\tkcuf1=\\E[C,\n+\tkcuu1=\\E[A,\n+\tkdch1=\\E[3~,\n+\tkel=\\E[8\\^,\n+\tkend=\\E[8~,\n+\tkent=\\EOM,\n+\tkf1=\\E[11~,\n+\tkf10=\\E[21~,\n+\tkf11=\\E[23~,\n+\tkf12=\\E[24~,\n+\tkf13=\\E[25~,\n+\tkf14=\\E[26~,\n+\tkf15=\\E[28~,\n+\tkf16=\\E[29~,\n+\tkf17=\\E[31~,\n+\tkf18=\\E[32~,\n+\tkf19=\\E[33~,\n+\tkf2=\\E[12~,\n+\tkf20=\\E[34~,\n+\tkf3=\\E[13~,\n+\tkf4=\\E[14~,\n+\tkf5=\\E[15~,\n+\tkf6=\\E[17~,\n+\tkf7=\\E[18~,\n+\tkf8=\\E[19~,\n+\tkf9=\\E[20~,\n+\tkfnd=\\E[1~,\n+\tkhome=\\E[7~,\n+\tkich1=\\E[2~,\n+\tkmous=\\E[M,\n+\tknp=\\E[6~,\n+\tkpp=\\E[5~,\n+\tkslt=\\E[4~,\n+\trc=\\E8,\n+\trev=\\E[7m,\n+\tri=\\EM,\n+\trmso=\\E[27m,\n+\trmul=\\E[24m,\n+\trs1=\\Ec,\n+\trs2=\\E[r\\E[m\\E[2J\\E[H\\E[?7h\\E[?1;3;4;6l\\E[4l\\E>,\n+\tsgr0=\\E[m\\017,\n+\tenacs=,\n+\tsmacs=\\E(0,\n+\trmacs=\\E(B,\n+\tsmso=\\E[7m,\n+\tsmul=\\E[4m,\n+\ttbc=\\E[3g,\n+\tvpa=\\E[%i%p1%dd,\n+\tcolors#88,\n+\tpairs#256,\n+\tbtns#5,\n+\tlm#0,\n+\tccc,\n+\tnpc,\n+\tmc5i,\n+\tncv#0,\n+\tmir,\n+\txon,\n+\tbw,\n+\tech=\\E[%p1%dX,\n+\tmc0=\\E[i,\n+\tmc4=\\E[4i,\n+\tmc5=\\E[5i,\n+\tsitm=\\E[3m,\n+\tritm=\\E[23m,\n+\tsmam=\\E[?7h,\n+\trmam=\\E[?7l,\n+\tsmir=\\E[4h,\n+\trmir=\\E[4l,\n+\tsmcup=\\E[?1049h,\n+\trmcup=\\E[r\\E[?1049l,\n+\tsmkx=\\E=,\n+\trmkx=\\E>,\n+\tindn=\\E[%p1%dS,\n+\trin=\\E[%p1%dT,\n+\tsgr=\\E[0%?%p6%t;1%;%?%p2%t;4%;%?%p1%p3%|%t;7%;%?%p4%t;5%;%?%p7%t;8%;m%?%p9%t\\E(0%e\\E(B%;,\n+\top=\\E[39;49m,\n+\tsetaf=\\E[38;5;%p1%dm,\n+\tsetab=\\E[48;5;%p1%dm,\n+\tsetf=%?%p1%{7}%>%t\\E[38;5;%p1%dm%e\\E[3%?%p1%{1}%=%t4%e%p1%{3}%=%t6%e%p1%{4}%=%t1%e%p1%{6}%=%t3%e%p1%d%;m%;,\n+\tsetb=%?%p1%{7}%>%t\\E[48;5;%p1%dm%e\\E[4%?%p1%{1}%=%t4%e%p1%{3}%=%t6%e%p1%{4}%=%t1%e%p1%{6}%=%t3%e%p1%d%;m%;,\n+\tinitc=\\E]4;%p1%d;rgb\\:%p2%{65535}%*%{1000}%/%4.4X/%p3%{65535}%*%{1000}%/%4.4X/%p4%{65535}%*%{1000}%/%4.4X\\E\\\\,\n+\tsc=\\E7,\n+\ts0ds=\\E(B,\n+\ts1ds=\\E(0,\n+\ts2ds=\\E*B,\n+\ts3ds=\\E+B,\n+\tu6=\\E[%i%d;%dR,\n+\tu7=\\E[6n,\n+\tu8=\\E[?1;2c,\n+\tu9=\\E[c,\n+\ttsl=\\E]2;,\n+\tfsl=\\007,\n+\tdsl=\\E]2;\\007,\n+\n #### MRXVT\n # mrxvt 0.5.4\n #\n"
  },
  {
    "path": "package/libs/ncurses/patches/101-ncurses-5.6-20080628-kbs.patch",
    "content": "--- a/misc/terminfo.src\n+++ b/misc/terminfo.src\n@@ -4815,6 +4815,7 @@ xterm+nofkeys|building block for xterm f\n # This version reflects the current xterm features.\n xterm-new|modern xterm terminal emulator,\n \tnpc,\n+\tkbs=\\177,\n \tkcbt=\\E[Z, kent=\\EOM, nel=\\EE, use=ecma+index,\n \tuse=ansi+rep, use=ecma+strikeout, use=xterm+pcfkeys,\n \tuse=xterm+nofkeys,\n@@ -6416,6 +6417,7 @@ mlterm-256color|mlterm 3.0 with xterm 25\n rxvt-basic|rxvt terminal base (X Window System),\n \tOTbs, am, bce, eo, mir, msgr, xenl, xon, XT,\n \tcols#80, it#8, lines#24,\n+\tkbs=\\177,\n \tacsc=``aaffggjjkkllmmnnooppqqrrssttuuvvwwxxyyzz{{||}}~~,\n \tbel=^G, blink=\\E[5m, bold=\\E[1m, clear=\\E[H\\E[2J, cr=\\r,\n \tcsr=\\E[%i%p1%d;%p2%dr, cub=\\E[%p1%dD, cub1=^H,\n@@ -6425,7 +6427,7 @@ rxvt-basic|rxvt terminal base (X Window\n \tenacs=\\E(B\\E)0, flash=\\E[?5h$<100/>\\E[?5l, home=\\E[H,\n \tht=^I, hts=\\EH, ich=\\E[%p1%d@, il=\\E[%p1%dL, il1=\\E[L,\n \tind=\\n, is1=\\E[?47l\\E=\\E[?1l,\n-\tis2=\\E[r\\E[m\\E[2J\\E[H\\E[?7h\\E[?1;3;4;6l\\E[4l, kbs=^H,\n+\tis2=\\E[r\\E[m\\E[2J\\E[H\\E[?7h\\E[?1;3;4;6l\\E[4l,\n \tkcbt=\\E[Z, kmous=\\E[M, rc=\\E8, rev=\\E[7m, ri=\\EM, rmacs=^O,\n \trmcup=\\E[2J\\E[?47l\\E8, rmir=\\E[4l, rmkx=\\E>, rmso=\\E[27m,\n \trmul=\\E[24m,\n@@ -8060,6 +8062,7 @@ dumb-emacs-ansi|Emacs dumb terminal with\n screen|VT 100/ANSI X3.64 virtual terminal,\n \tOTbs, OTpt, am, km, mir, msgr, xenl, G0,\n \tcolors#8, cols#80, it#8, lines#24, ncv@, pairs#64, U8#1,\n+\tkbs=\\177,\n \tacsc=++\\,\\,--..00``aaffgghhiijjkkllmmnnooppqqrrssttuuvvwwxxy\n \t     yzz{{||}}~~,\n \tbel=^G, blink=\\E[5m, bold=\\E[1m, cbt=\\E[Z, civis=\\E[?25l,\n@@ -8071,7 +8074,7 @@ screen|VT 100/ANSI X3.64 virtual termina\n \tdl=\\E[%p1%dM, dl1=\\E[M, ed=\\E[J, el=\\E[K, el1=\\E[1K,\n \tenacs=\\E(B\\E)0, flash=\\Eg, home=\\E[H, hpa=\\E[%i%p1%dG,\n \tht=^I, hts=\\EH, ich=\\E[%p1%d@, il=\\E[%p1%dL, il1=\\E[L,\n-\tind=\\n, indn=\\E[%p1%dS, is2=\\E)0, kbs=^H, kcbt=\\E[Z,\n+\tind=\\n, indn=\\E[%p1%dS, is2=\\E)0, kcbt=\\E[Z,\n \tkcub1=\\EOD, kcud1=\\EOB, kcuf1=\\EOC, kcuu1=\\EOA, kf1=\\EOP,\n \tkf10=\\E[21~, kf11=\\E[23~, kf12=\\E[24~, kf2=\\EOQ, kf3=\\EOR,\n \tkf4=\\EOS, kf5=\\E[15~, kf6=\\E[17~, kf7=\\E[18~, kf8=\\E[19~,\n@@ -8199,6 +8202,7 @@ screen.xterm-r6|screen customized for X1\n # on Solaris because Sun's curses implementation gets confused.\n screen.teraterm|disable ncv in teraterm,\n \tncv#127,\n+\tkbs=^H,\n \tacsc=+\\020\\,\\021-\\030.^Y0\\333`\\004a\\261f\\370g\\361h\\260i\n \t     \\316j\\331k\\277l\\332m\\300n\\305o~p\\304q\\304r\\304s_t\\303u\n \t     \\264v\\301w\\302x\\263y\\363z\\362{\\343|\\330}\\234~\\376,\n"
  },
  {
    "path": "package/libs/ncurses/patches/102-ncurses-5.9-gcc-5.patch",
    "content": "https://bugs.gentoo.org/545114\n\nextracted from the upstream change (which had many unrelated commits in one)\n\nFrom 97bb4678dc03e753290b39bbff30ba2825df9517 Mon Sep 17 00:00:00 2001\nFrom: \"Thomas E. Dickey\" <dickey@invisible-island.net>\nDate: Sun, 7 Dec 2014 03:10:09 +0000\nSubject: [PATCH] ncurses 5.9 - patch 20141206\n\n+ modify MKlib_gen.sh to work around change in development version of\n  gcc introduced here:\n\t  https://gcc.gnu.org/ml/gcc-patches/2014-06/msg02185.html\n\t  https://gcc.gnu.org/ml/gcc-patches/2014-07/msg00236.html\n  (reports by Marcus Shawcroft, Maohui Lei).\n\n--- a/ncurses/base/MKlib_gen.sh\n+++ b/ncurses/base/MKlib_gen.sh\n@@ -511,11 +511,22 @@ sed -n -f $ED1 \\\n \t-e 's/gen_$//' \\\n \t-e 's/  / /g' >>$TMP\n \n+cat >$ED1 <<EOF\n+s/  / /g\n+s/^ //\n+s/ $//\n+s/P_NCURSES_BOOL/NCURSES_BOOL/g\n+EOF\n+\n+# A patch discussed here:\n+#\thttps://gcc.gnu.org/ml/gcc-patches/2014-06/msg02185.html\n+# introduces spurious #line markers.  Work around that by ignoring the system's\n+# attempt to define \"bool\" and using our own symbol here.\n+sed -e 's/bool/P_NCURSES_BOOL/g' $TMP > $ED2\n+cat $ED2 >$TMP\n+\n $preprocessor $TMP 2>/dev/null \\\n-| sed \\\n-\t-e 's/  / /g' \\\n-\t-e 's/^ //' \\\n-\t-e 's/_Bool/NCURSES_BOOL/g' \\\n+| sed -f $ED1 \\\n | \"$AWK\" -f $AW2 \\\n | sed -f $ED3 \\\n | sed \\\n"
  },
  {
    "path": "package/libs/ncurses/patches/103-ncurses-ar-determinism.patch",
    "content": "--- a/aclocal.m4\n+++ b/aclocal.m4\n@@ -505,7 +505,7 @@ AC_CACHE_CHECK(for options to update arc\n \t\t;;\n \t(*)\n \t\tcf_cv_ar_flags=unknown\n-\t\tfor cf_ar_flags in -curvU -curv curv -crv crv -cqv cqv -rv rv\n+\t\tfor cf_ar_flags in -curvD -curv curv -crv crv -cqv cqv -rv rv\n \t\tdo\n \n \t\t\t# check if $ARFLAGS already contains this choice\n--- a/configure\n+++ b/configure\n@@ -5072,7 +5072,7 @@ else\n \t\t;;\n \t(*)\n \t\tcf_cv_ar_flags=unknown\n-\t\tfor cf_ar_flags in -curvU -curv curv -crv crv -cqv cqv -rv rv\n+\t\tfor cf_ar_flags in -curvD -curv curv -crv crv -cqv cqv -rv rv\n \t\tdo\n \n \t\t\t# check if $ARFLAGS already contains this choice\n"
  },
  {
    "path": "package/libs/ncurses/patches/200-fix_missing_include.patch",
    "content": "--- a/ncurses/curses.priv.h\n+++ b/ncurses/curses.priv.h\n@@ -56,6 +56,11 @@ extern \"C\" {\n \n #include <ncurses_cfg.h>\n \n+#if NEED_WCHAR_H\n+#include <stdarg.h>\n+#include <wchar.h>\n+#endif\n+\n #if USE_RCS_IDS\n #define MODULE_ID(id) static const char Ident[] = id;\n #else\n"
  },
  {
    "path": "package/libs/ncurses/patches/900-terminfo.patch",
    "content": "--- a/misc/terminfo.src\n+++ b/misc/terminfo.src\n@@ -6240,12 +6240,11 @@ konsole-xf3x|KDE console window with key\n # The value for kbs (see konsole-vt100) reflects local customization rather\n # than the settings used for XFree86 xterm.\n konsole-xf4x|KDE console window with keyboard for XFree86 4.x xterm,\n-\tkend=\\EOF, khome=\\EOH, use=konsole+pcfkeys,\n-\tuse=konsole-vt100,\n-\n-konsole+pcfkeys|konsole subset of xterm+pcfkeys,\n-\tkcbt=\\E[Z, use=xterm+pcc2, use=xterm+pcf0,\n-\tuse=xterm+pce2,\n+\tkend=\\EOF, kf1=\\EOP, kf13=\\EO2P, kf14=\\EO2Q, kf15=\\EO2R,\n+\tkf16=\\EO2S, kf17=\\E[15;2~, kf18=\\E[17;2~, kf19=\\E[18;2~,\n+\tkf2=\\EOQ, kf20=\\E[19;2~, kf21=\\E[20;2~, kf22=\\E[21;2~,\n+\tkf23=\\E[23;2~, kf24=\\E[24;2~, kf3=\\EOR, kf4=\\EOS,\n+\tkhome=\\EOH, use=konsole-vt100,\n \n # Obsolete: vt100.keymap\n # KDE's \"vt100\" keyboard has no relationship to any terminal that DEC made, but\n"
  },
  {
    "path": "package/libs/nettle/Config.in",
    "content": "# nettle avanced configuration\n\nmenu \"Configuration\"\n\tdepends on PACKAGE_libnettle\n\nconfig LIBNETTLE_MINI\n\tbool \"use mini-gmp instead of gmp; the library will be much smaller at a 10x performance penalty. Note that this option may have side effects to programs that link to both nettle and gmp.\"\n\nendmenu\n"
  },
  {
    "path": "package/libs/nettle/Makefile",
    "content": "#\n# Copyright (C) 2014 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=nettle\nPKG_VERSION:=3.7.3\nPKG_RELEASE:=$(AUTORELEASE)\nPKG_USE_MIPS16:=0\n\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz\nPKG_SOURCE_URL:=@GNU/nettle\nPKG_HASH:=661f5eb03f048a3b924c3a8ad2515d4068e40f67e774e8a26827658007e3bcf0\n\nPKG_LICENSE:=GPL-2.0-or-later\nPKG_LICENSE_FILES:=COPYING\nPKG_BUILD_PARALLEL:=1\n\nPKG_CONFIG_DEPENDS := CONFIG_LIBNETTLE_MINI\n\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine Package/libnettle\n  SECTION:=libs\n  CATEGORY:=Libraries\n  TITLE:=GNU crypto library\n  URL:=http://www.lysator.liu.se/~nisse/nettle/\n  DEPENDS+= +!LIBNETTLE_MINI:libgmp\n  ABI_VERSION:=8\nendef\n\ndefine Package/libnettle/config\n\tsource \"$(SOURCE)/Config.in\"\nendef\n\nTARGET_CFLAGS += $(FPIC)\n\nCONFIGURE_ARGS += \\\n\t--enable-shared \\\n\t--enable-fat \\\n\t--disable-openssl \\\n\t--disable-documentation \\\n\t--enable-static \\\n\t$(if $(CONFIG_powerpc64), $(if $(CONFIG_USE_MUSL),--disable-assembler))\n\nifeq ($(CONFIG_LIBNETTLE_MINI),y)\nCONFIGURE_ARGS += --enable-mini-gmp\nendif\n\nifeq ($(CONFIG_CPU_SUBTYPE),neon)\nCONFIGURE_ARGS += \\\n\t--enable-arm-neon\nendif\n\nifeq ($(ARCH),armeb)\nCONFIGURE_ARGS += \\\n\t--disable-assembler\nendif\n\ndefine Build/Compile\n\t$(call Build/Compile/Default, \\\n\t\tDESTDIR=\"$(PKG_INSTALL_DIR)\" \\\n\t\tCC=\"$(TARGET_CC)\" \\\n\t\tlibnettle.so libhogweed.so\n\t+$(MAKE) -i $(PKG_JOBS) -C $(PKG_BUILD_DIR) \\\n\t\tDESTDIR=\"$(PKG_INSTALL_DIR)\" \\\n\t\tinstall)\nendef\n\ndefine Build/InstallDev\n\t$(INSTALL_DIR) $(1)/usr/include/nettle\n\t$(CP) $(PKG_INSTALL_DIR)/usr/include/nettle/*.h $(1)/usr/include/nettle/\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/libnettle.{a,so*} $(1)/usr/lib/\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/libhogweed.{a,so*} $(1)/usr/lib/\n\t$(INSTALL_DIR) $(1)/usr/lib/pkgconfig\n\t$(CP) \\\n\t\t$(PKG_INSTALL_DIR)/usr/lib/pkgconfig/nettle.pc \\\n\t\t$(PKG_INSTALL_DIR)/usr/lib/pkgconfig/hogweed.pc \\\n\t\t$(1)/usr/lib/pkgconfig/\nendef\n\ndefine Package/libnettle/install\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/libnettle.so.* $(1)/usr/lib/\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/libhogweed.so.* $(1)/usr/lib/\nendef\n\n$(eval $(call BuildPackage,libnettle))\n"
  },
  {
    "path": "package/libs/nettle/patches/100-portability.patch",
    "content": "--- a/configure\n+++ b/configure\n@@ -4661,6 +4661,7 @@ $as_echo_n \"checking build system compil\n # remove anything that might look like compiler output to our \"||\" expression\n rm -f conftest* a.out b.out a.exe a_out.exe\n cat >conftest.c <<EOF\n+#include <stdlib.h>\n int\n main ()\n {\n@@ -4693,6 +4694,7 @@ $as_echo_n \"checking build system compil\n # remove anything that might look like compiler output to our \"||\" expression\n rm -f conftest* a.out b.out a.exe a_out.exe\n cat >conftest.c <<EOF\n+#include <stdlib.h>\n int\n main ()\n {\n@@ -4729,6 +4731,7 @@ $as_echo_n \"checking build system compil\n # remove anything that might look like compiler output to our \"||\" expression\n rm -f conftest* a.out b.out a.exe a_out.exe\n cat >conftest.c <<EOF\n+#include <stdlib.h>\n int\n main ()\n {\n@@ -4779,6 +4782,7 @@ else\n   gmp_cv_prog_exeext_for_build=\"$EXEEXT\"\n else\n   cat >conftest.c <<EOF\n+#include <stdlib.h>\n int\n main ()\n {\n"
  },
  {
    "path": "package/libs/openssl/Config.in",
    "content": "if PACKAGE_libopenssl\n\ncomment \"Build Options\"\n\nconfig OPENSSL_OPTIMIZE_SPEED\n\tbool\n\tdefault y if x86_64 || i386\n\tprompt \"Enable optimization for speed instead of size\"\n\tselect OPENSSL_WITH_ASM\n\thelp\n\t\tEnabling this option increases code size (around 20%) and\n\t\tperformance.  The increase in performance and size depends on the\n\t\ttarget CPU. EC and AES seem to benefit the most, with EC speed\n\t\tincreased by 20%-50% (mipsel & x86).\n\t\tAES-GCM is supposed to be 3x faster on x86. YMMV.\n\nconfig OPENSSL_WITH_ASM\n\tbool\n\tdefault y if !SMALL_FLASH || !arm\n\tprompt \"Compile with optimized assembly code\"\n\tdepends on !arc\n\thelp\n\t\tDisabling this option will reduce code size and performance.\n\t\tThe increase in performance and size depends on the target\n\t\tCPU and on the algorithms being optimized.  As of 1.1.0i*:\n\n\t\tPlatform  Pkg Inc. Algorithms where assembly is used - ~% Speed Increase\n\t\taarch64   174K     BN, aes, sha1, sha256, sha512, nist256, poly1305\n\t\tarm       152K     BN, aes, sha1, sha256, sha512, nist256, poly1305\n\t\ti386      183K     BN+147%, aes+300%, rc4+55%, sha1+160%, sha256+114%, sha512+270%, nist256+282%, poly1305+292%\n\t\tmipsel      1.5K   BN+97%, aes+4%, sha1+94%, sha256+60%\n\t\tmips64\t    3.7K   BN, aes, sha1, sha256, sha512, poly1305\n\t\tpowerpc    20K     BN, aes, sha1, sha256, sha512, poly1305\n\t\tx86_64    228K     BN+220%, aes+173%, rc4+38%, sha1+40%, sha256+64%, sha512+31%, nist256+354%, poly1305+228%\n\n\t\t* Only most common algorithms shown. Your mileage may vary.\n\t\t  BN (bignum) performance was measured using RSA sign/verify.\n\nconfig OPENSSL_WITH_SSE2\n\tbool\n\tdefault y if !TARGET_x86_legacy && !TARGET_x86_geode\n\tprompt \"Enable use of x86 SSE2 instructions\"\n\tdepends on OPENSSL_WITH_ASM && i386\n\thelp\n\t\tUse of SSE2 instructions greatly increase performance (up to\n\t\t3x faster) with a minimum (~0.2%, or 23KB) increase in package\n\t\tsize, but it will bring no benefit if your hardware does not\n\t\tsupport them, such as Geode GX and LX.  In this case you may\n\t\tsave 23KB by saying yes here.  AMD Geode NX, and Intel\n\t\tPentium 4 and above support SSE2.\n\nconfig OPENSSL_WITH_DEPRECATED\n\tbool\n\tdefault y\n\tprompt \"Include deprecated APIs (See help for a list of packages that need this)\"\n\thelp\n\t\tSince openssl 1.1.x is still new to openwrt, some packages\n\t\trequiring this option do not list it as a requirement yet:\n\t\t * freeswitch-stable, freeswitch, python, python3, squid.\n\nconfig OPENSSL_NO_DEPRECATED\n\tbool\n\tdefault !OPENSSL_WITH_DEPRECATED\n\nconfig OPENSSL_WITH_ERROR_MESSAGES\n\tbool\n\tdefault y if !SMALL_FLASH && !LOW_MEMORY_FOOTPRINT\n\tprompt \"Include error messages\"\n\thelp\n\t\tThis option aids debugging, but increases package size and\n\t\tmemory usage.\n\ncomment \"Protocol Support\"\n\nconfig OPENSSL_WITH_TLS13\n\tbool\n\tdefault y\n\tprompt \"Enable support for TLS 1.3\"\n\thelp\n\t\tTLS 1.3 is the newest version of the TLS specification.\n\t\tIt aims:\n\t\t * to increase the overall security of the protocol,\n\t\t   removing outdated algorithms, and encrypting more of the\n\t\t   protocol;\n\t\t * to increase performance by reducing the number of round-trips\n\t\t   when performing a full handshake.\n\t\tIt increases package size by ~4KB.\n\nconfig OPENSSL_WITH_DTLS\n\tbool\n\tprompt \"Enable DTLS support\"\n\thelp\n\t\tDatagram Transport Layer Security (DTLS) provides TLS-like security\n\t\tfor datagram-based (UDP, DCCP, CAPWAP, SCTP & SRTP) applications.\n\nconfig OPENSSL_WITH_NPN\n\tbool\n\tprompt \"Enable NPN support\"\n\thelp\n\t\tNPN is a TLS extension, obsoleted and replaced with ALPN,\n\t\tused to negotiate SPDY, and HTTP/2.\n\nconfig OPENSSL_WITH_SRP\n\tbool\n\tdefault y\n\tprompt \"Enable SRP support\"\n\thelp\n\t\tThe Secure Remote Password protocol (SRP) is an augmented\n\t\tpassword-authenticated key agreement (PAKE) protocol, specifically\n\t\tdesigned to work around existing patents.\n\nconfig OPENSSL_WITH_CMS\n\tbool\n\tdefault y\n\tprompt \"Enable CMS (RFC 5652) support\"\n\thelp\n\t\tCryptographic Message Syntax (CMS) is used to digitally sign,\n\t\tdigest, authenticate, or encrypt arbitrary message content.\n\ncomment \"Algorithm Selection\"\n\nconfig OPENSSL_WITH_EC2M\n\tbool\n\tprompt \"Enable ec2m support\"\n\thelp\n\t\tThis option enables the more efficient, yet less common, binary\n\t\tfield elliptic curves.\n\nconfig OPENSSL_WITH_CHACHA_POLY1305\n\tbool\n\tdefault y\n\tprompt \"Enable ChaCha20-Poly1305 ciphersuite support\"\n\thelp\n\t\tChaCha20-Poly1305 is an AEAD ciphersuite with 256-bit keys,\n\t\tcombining ChaCha stream cipher with Poly1305 MAC.\n\t\tIt is 3x faster than AES, when not using a CPU with AES-specific\n\t\tinstructions, as is the case of most embedded devices.\n\nconfig OPENSSL_PREFER_CHACHA_OVER_GCM\n\tbool\n\tdefault y if !x86_64 && !aarch64\n\tprompt \"Prefer ChaCha20-Poly1305 over AES-GCM by default\"\n\tdepends on OPENSSL_WITH_CHACHA_POLY1305\n\thelp\n\t\tThe default openssl preference is for AES-GCM before ChaCha, but\n\t\tthat takes into account AES-NI capable chips.  It is not the\n\t\tcase with most embedded chips, so it may be better to invert\n\t\tthat preference.  This is just for the default case. The\n\t\tapplication can always override this.\n\nconfig OPENSSL_WITH_PSK\n\tbool\n\tdefault y\n\tprompt \"Enable PSK support\"\n\thelp\n\t\tBuild support for Pre-Shared Key based cipher suites.\n\ncomment \"Less commonly used build options\"\n\nconfig OPENSSL_WITH_ARIA\n\tbool\n\tprompt \"Enable ARIA support\"\n\thelp\n\t\tARIA is a block cipher developed in South Korea, based on AES.\n\nconfig OPENSSL_WITH_CAMELLIA\n\tbool\n\tprompt \"Enable Camellia cipher support\"\n\thelp\n\t\tCamellia is a bock cipher with security levels and processing\n\t\tabilities comparable to AES.\n\nconfig OPENSSL_WITH_IDEA\n\tbool\n\tprompt \"Enable IDEA cipher support\"\n\thelp\n\t\tIDEA is a block cipher with 128-bit keys.\n\nconfig OPENSSL_WITH_SEED\n\tbool\n\tprompt \"Enable SEED cipher support\"\n\thelp\n\t\tSEED is a block cipher with 128-bit keys broadly used in\n\t\tSouth Korea, but seldom found elsewhere.\n\nconfig OPENSSL_WITH_SM234\n\tbool\n\tprompt \"Enable SM2/3/4 algorithms support\"\n\thelp\n\t\tThese algorithms are a set of \"Commercial Cryptography\"\n\t\talgorithms approved for use in China.\n\t\t  * SM2 is an EC algorithm equivalent to ECDSA P-256\n\t\t  * SM3 is a hash function equivalent to SHA-256\n\t\t  * SM4 is a 128-block cipher equivalent to AES-128\n\nconfig OPENSSL_WITH_BLAKE2\n\tbool\n\tprompt \"Enable BLAKE2 digest support\"\n\thelp\n\t\tBLAKE2 is a cryptographic hash function based on the ChaCha\n\t\tstream cipher.\n\nconfig OPENSSL_WITH_MDC2\n\tbool\n\tprompt \"Enable MDC2 digest support\"\n\nconfig OPENSSL_WITH_WHIRLPOOL\n\tbool\n\tprompt \"Enable Whirlpool digest support\"\n\nconfig OPENSSL_WITH_COMPRESSION\n\tbool\n\tprompt \"Enable compression support\"\n\thelp\n\t\tTLS compression is not recommended, as it is deemed insecure.\n\t\tThe CRIME attack exploits this weakness.\n\t\tEven with this option turned on, it is disabled by default, and the\n\t\tapplication must explicitly turn it on.\n\nconfig OPENSSL_WITH_RFC3779\n\tbool\n\tprompt \"Enable RFC3779 support (BGP)\"\n\thelp\n\t\tRFC 3779 defines two X.509 v3 certificate extensions.  The first\n\t\tbinds a list of IP address blocks, or prefixes, to the subject of a\n\t\tcertificate.  The second binds a list of autonomous system\n\t\tidentifiers to the subject of a certificate.  These extensions may be\n\t\tused to convey the authorization of the subject to use the IP\n\t\taddresses and autonomous system identifiers contained in the\n\t\textensions.\n\ncomment \"Engine/Hardware Support\"\n\nconfig OPENSSL_ENGINE\n\tbool \"Enable engine support\"\n\tdefault y\n\thelp\n\t\tThis enables alternative cryptography implementations,\n\t\tmost commonly for interfacing with external crypto devices,\n\t\tor supporting new/alternative ciphers and digests.\n\t\tIf you compile the library with this option disabled, packages built\n\t\tusing an engine-enabled library (i.e. from the official repo) may\n\t\tfail to run.  Compile and install the packages with engine support\n\t\tdisabled, and you should be fine.\n\t\tNote that you need to enable KERNEL_AIO to be able to build the\n\t\tafalg engine package.\n\nconfig OPENSSL_ENGINE_BUILTIN\n\tbool \"Build chosen engines into libcrypto\"\n\tdepends on OPENSSL_ENGINE\n\thelp\n\t\tThis builds all chosen engines into libcrypto.so, instead of building\n\t\tthem as dynamic engines in separate packages.\n\t\tThe benefit of building the engines into libcrypto is that they won't\n\t\trequire any configuration to be used by default.\n\nconfig OPENSSL_ENGINE_BUILTIN_AFALG\n\tbool\n\tprompt \"Acceleration support through AF_ALG sockets engine\"\n\tdepends on OPENSSL_ENGINE_BUILTIN && KERNEL_AIO\n\tselect PACKAGE_libopenssl-conf\n\thelp\n\t\tThis enables use of hardware acceleration through the\n\t\tAF_ALG kernel interface.\n\nconfig OPENSSL_ENGINE_BUILTIN_DEVCRYPTO\n\tbool\n\tprompt \"Acceleration support through /dev/crypto\"\n\tdepends on OPENSSL_ENGINE_BUILTIN\n\tselect PACKAGE_libopenssl-conf\n\thelp\n\t\tThis enables use of hardware acceleration through OpenBSD\n\t\tCryptodev API (/dev/crypto) interface.\n\t\tEven though configuration is not strictly needed, it is worth seeing\n\t\thttps://openwrt.org/docs/techref/hardware/cryptographic.hardware.accelerators\n\t\tfor information on how to configure the engine.\n\nconfig OPENSSL_ENGINE_BUILTIN_PADLOCK\n\tbool\n\tprompt \"VIA Padlock Acceleration support engine\"\n\tdepends on OPENSSL_ENGINE_BUILTIN && TARGET_x86\n\tselect PACKAGE_libopenssl-conf\n\thelp\n\t\tThis enables use of hardware acceleration through the\n\t\tVIA Padlock module.\n\nconfig OPENSSL_WITH_ASYNC\n\tbool\n\tprompt \"Enable asynchronous jobs support\"\n\tdepends on OPENSSL_ENGINE && USE_GLIBC\n\thelp\n\t\tEnables async-aware applications to be able to use OpenSSL to\n\t\tinitiate crypto operations asynchronously. In order to work\n\t\tthis will require the presence of an async capable engine.\n\nendif\n"
  },
  {
    "path": "package/libs/openssl/Makefile",
    "content": "#\n# Copyright (C) 2006-2016 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=openssl\nPKG_BASE:=1.1.1\nPKG_BUGFIX:=o\nPKG_VERSION:=$(PKG_BASE)$(PKG_BUGFIX)\nPKG_RELEASE:=$(AUTORELEASE)\nPKG_USE_MIPS16:=0\n\nPKG_BUILD_PARALLEL:=1\n\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz\nPKG_SOURCE_URL:= \\\n\thttp://www.openssl.org/source/ \\\n\thttp://www.openssl.org/source/old/$(PKG_BASE)/ \\\n\thttp://ftp.fi.muni.cz/pub/openssl/source/ \\\n\thttp://ftp.fi.muni.cz/pub/openssl/source/old/$(PKG_BASE)/ \\\n\tftp://ftp.pca.dfn.de/pub/tools/net/openssl/source/ \\\n\tftp://ftp.pca.dfn.de/pub/tools/net/openssl/source/old/$(PKG_BASE)/\n\nPKG_HASH:=9384a2b0570dd80358841464677115df785edb941c71211f75076d72fe6b438f\n\nPKG_LICENSE:=OpenSSL\nPKG_LICENSE_FILES:=LICENSE\nPKG_MAINTAINER:=Eneas U de Queiroz <cotequeiroz@gmail.com>\nPKG_CPE_ID:=cpe:/a:openssl:openssl\nPKG_CONFIG_DEPENDS:= \\\n\tCONFIG_OPENSSL_ENGINE \\\n\tCONFIG_OPENSSL_ENGINE_BUILTIN \\\n\tCONFIG_OPENSSL_ENGINE_BUILTIN_AFALG \\\n\tCONFIG_OPENSSL_ENGINE_BUILTIN_DEVCRYPTO \\\n\tCONFIG_OPENSSL_ENGINE_BUILTIN_PADLOCK \\\n\tCONFIG_OPENSSL_NO_DEPRECATED \\\n\tCONFIG_OPENSSL_OPTIMIZE_SPEED \\\n\tCONFIG_OPENSSL_PREFER_CHACHA_OVER_GCM \\\n\tCONFIG_OPENSSL_WITH_ARIA \\\n\tCONFIG_OPENSSL_WITH_ASM \\\n\tCONFIG_OPENSSL_WITH_ASYNC \\\n\tCONFIG_OPENSSL_WITH_BLAKE2 \\\n\tCONFIG_OPENSSL_WITH_CAMELLIA \\\n\tCONFIG_OPENSSL_WITH_CHACHA_POLY1305 \\\n\tCONFIG_OPENSSL_WITH_CMS \\\n\tCONFIG_OPENSSL_WITH_COMPRESSION \\\n\tCONFIG_OPENSSL_WITH_DTLS \\\n\tCONFIG_OPENSSL_WITH_EC2M \\\n\tCONFIG_OPENSSL_WITH_ERROR_MESSAGES \\\n\tCONFIG_OPENSSL_WITH_IDEA \\\n\tCONFIG_OPENSSL_WITH_MDC2 \\\n\tCONFIG_OPENSSL_WITH_NPN \\\n\tCONFIG_OPENSSL_WITH_PSK \\\n\tCONFIG_OPENSSL_WITH_RFC3779 \\\n\tCONFIG_OPENSSL_WITH_SEED \\\n\tCONFIG_OPENSSL_WITH_SM234 \\\n\tCONFIG_OPENSSL_WITH_SRP \\\n\tCONFIG_OPENSSL_WITH_SSE2 \\\n\tCONFIG_OPENSSL_WITH_TLS13 \\\n\tCONFIG_OPENSSL_WITH_WHIRLPOOL\n\ninclude $(INCLUDE_DIR)/package.mk\ninclude $(INCLUDE_DIR)/openssl-engine.mk\n\nifneq ($(CONFIG_CCACHE),)\nHOSTCC=$(HOSTCC_NOCACHE)\nHOSTCXX=$(HOSTCXX_NOCACHE)\nendif\n\ndefine Package/openssl/Default\n  TITLE:=Open source SSL toolkit\n  URL:=http://www.openssl.org/\n  SECTION:=libs\n  CATEGORY:=Libraries\nendef\n\ndefine Package/libopenssl/config\nsource \"$(SOURCE)/Config.in\"\nendef\n\ndefine Package/openssl/Default/description\nThe OpenSSL Project is a collaborative effort to develop a robust,\ncommercial-grade, full-featured, and Open Source toolkit implementing the\nTransport Layer Security (TLS) protocol as well as a full-strength\ngeneral-purpose cryptography library.\nendef\n\ndefine Package/libopenssl\n$(call Package/openssl/Default)\n  SUBMENU:=SSL\n  DEPENDS:=+OPENSSL_WITH_COMPRESSION:zlib \\\n\t   +OPENSSL_ENGINE_BUILTIN_AFALG:kmod-crypto-user \\\n\t   +OPENSSL_ENGINE_BUILTIN_DEVCRYPTO:kmod-cryptodev \\\n\t   +OPENSSL_ENGINE_BUILTIN_PADLOCK:kmod-crypto-hw-padlock\n  TITLE+= (libraries)\n  ABI_VERSION:=1.1\n  MENU:=1\nendef\n\ndefine Package/libopenssl/description\n$(call Package/openssl/Default/description)\nThis package contains the OpenSSL shared libraries, needed by other programs.\nendef\n\ndefine Package/openssl-util\n  $(call Package/openssl/Default)\n  SECTION:=utils\n  CATEGORY:=Utilities\n  DEPENDS:=+libopenssl +libopenssl-conf\n  TITLE+= (utility)\nendef\n\ndefine Package/openssl-util/description\n$(call Package/openssl/Default/description)\nThis package contains the OpenSSL command-line utility.\nendef\n\ndefine Package/libopenssl-conf\n  $(call Package/openssl/Default)\n  SUBMENU:=SSL\n  TITLE:=/etc/ssl/openssl.cnf config file\n  DEPENDS:=libopenssl\nendef\n\ndefine Package/libopenssl-conf/conffiles\n/etc/ssl/openssl.cnf\n$(if CONFIG_OPENSSL_ENGINE_BUILTIN_DEVCRYPTO,/etc/ssl/engines.cnf.d/devcrypto.cnf)\n$(if CONFIG_OPENSSL_ENGINE_BUILTIN_PADLOCK,/etc/ssl/engines.cnf.d/padlock.cnf)\nendef\n\ndefine Package/libopenssl-conf/description\n$(call Package/openssl/Default/description)\nThis package installs the OpenSSL configuration file /etc/ssl/openssl.cnf.\nendef\n\n$(eval $(call Package/openssl/add-engine,afalg))\ndefine Package/libopenssl-afalg\n  $(call Package/openssl/Default)\n  $(call Package/openssl/engine/Default)\n  TITLE:=AFALG hardware acceleration engine\n  DEPENDS += @KERNEL_AIO +PACKAGE_libopenssl-afalg:kmod-crypto-user \\\n\t     @!OPENSSL_ENGINE_BUILTIN\nendef\n\ndefine Package/libopenssl-afalg/description\nThis package adds an engine that enables hardware acceleration\nthrough the AF_ALG kernel interface.\nSee https://www.openssl.org/docs/man1.1.1/man5/config.html#Engine-Configuration-Module\nand https://openwrt.org/docs/techref/hardware/cryptographic.hardware.accelerators\nThe engine_id is \"afalg\"\nendef\n\n$(eval $(call Package/openssl/add-engine,devcrypto))\ndefine Package/libopenssl-devcrypto\n  $(call Package/openssl/Default)\n  $(call Package/openssl/engine/Default)\n  TITLE:=/dev/crypto hardware acceleration engine\n  DEPENDS += +PACKAGE_libopenssl-devcrypto:kmod-cryptodev @!OPENSSL_ENGINE_BUILTIN\nendef\n\ndefine Package/libopenssl-devcrypto/description\nThis package adds an engine that enables hardware acceleration\nthrough the /dev/crypto kernel interface.\nSee https://www.openssl.org/docs/man1.1.1/man5/config.html#Engine-Configuration-Module\nand https://openwrt.org/docs/techref/hardware/cryptographic.hardware.accelerators\nThe engine_id is \"devcrypto\"\nendef\n\n$(eval $(call Package/openssl/add-engine,padlock))\ndefine Package/libopenssl-padlock\n  $(call Package/openssl/Default)\n  $(call Package/openssl/engine/Default)\n  TITLE:=VIA Padlock hardware acceleration engine\n  DEPENDS += @TARGET_x86 +PACKAGE_libopenssl-padlock:kmod-crypto-hw-padlock \\\n\t     @!OPENSSL_ENGINE_BUILTIN\nendef\n\ndefine Package/libopenssl-padlock/description\nThis package adds an engine that enables VIA Padlock hardware acceleration.\nSee https://www.openssl.org/docs/man1.1.1/man5/config.html#Engine-Configuration-Module\nand https://openwrt.org/docs/techref/hardware/cryptographic.hardware.accelerators\nThe engine_id is \"padlock\"\nendef\n\nOPENSSL_OPTIONS:= shared\n\nifndef CONFIG_OPENSSL_WITH_BLAKE2\n  OPENSSL_OPTIONS += no-blake2\nendif\n\nifndef CONFIG_OPENSSL_WITH_CHACHA_POLY1305\n  OPENSSL_OPTIONS += no-chacha no-poly1305\nelse\n  ifdef CONFIG_OPENSSL_PREFER_CHACHA_OVER_GCM\n    OPENSSL_OPTIONS += -DOPENSSL_PREFER_CHACHA_OVER_GCM\n  endif\nendif\n\nifndef CONFIG_OPENSSL_WITH_ASYNC\n  OPENSSL_OPTIONS += no-async\nendif\n\nifndef CONFIG_OPENSSL_WITH_EC2M\n  OPENSSL_OPTIONS += no-ec2m\nendif\n\nifndef CONFIG_OPENSSL_WITH_ERROR_MESSAGES\n  OPENSSL_OPTIONS += no-err\nendif\n\nifndef CONFIG_OPENSSL_WITH_TLS13\n  OPENSSL_OPTIONS += no-tls1_3\nendif\n\nifndef CONFIG_OPENSSL_WITH_ARIA\n  OPENSSL_OPTIONS += no-aria\nendif\n\nifndef CONFIG_OPENSSL_WITH_SM234\n  OPENSSL_OPTIONS += no-sm2 no-sm3 no-sm4\nendif\n\nifndef CONFIG_OPENSSL_WITH_CAMELLIA\n  OPENSSL_OPTIONS += no-camellia\nendif\n\nifndef CONFIG_OPENSSL_WITH_IDEA\n  OPENSSL_OPTIONS += no-idea\nendif\n\nifndef CONFIG_OPENSSL_WITH_SEED\n  OPENSSL_OPTIONS += no-seed\nendif\n\nifndef CONFIG_OPENSSL_WITH_MDC2\n  OPENSSL_OPTIONS += no-mdc2\nendif\n\nifndef CONFIG_OPENSSL_WITH_WHIRLPOOL\n  OPENSSL_OPTIONS += no-whirlpool\nendif\n\nifndef CONFIG_OPENSSL_WITH_CMS\n  OPENSSL_OPTIONS += no-cms\nendif\n\nifndef CONFIG_OPENSSL_WITH_RFC3779\n  OPENSSL_OPTIONS += no-rfc3779\nendif\n\nifdef CONFIG_OPENSSL_NO_DEPRECATED\n  OPENSSL_OPTIONS += no-deprecated\nendif\n\nifeq ($(CONFIG_OPENSSL_OPTIMIZE_SPEED),y)\n  TARGET_CFLAGS := $(filter-out -O%,$(TARGET_CFLAGS)) -O3\nelse\n  OPENSSL_OPTIONS += -DOPENSSL_SMALL_FOOTPRINT\nendif\n\nifdef CONFIG_OPENSSL_ENGINE\n  ifdef CONFIG_OPENSSL_ENGINE_BUILTIN\n    OPENSSL_OPTIONS += disable-dynamic-engine\n    ifndef CONFIG_OPENSSL_ENGINE_BUILTIN_AFALG\n      OPENSSL_OPTIONS += no-afalgeng\n    endif\n    ifdef CONFIG_OPENSSL_ENGINE_BUILTIN_DEVCRYPTO\n      OPENSSL_OPTIONS += enable-devcryptoeng\n    endif\n    ifndef CONFIG_OPENSSL_ENGINE_BUILTIN_PADLOCK\n      OPENSSL_OPTIONS += no-hw-padlock\n    endif\n  else\n    ifdef CONFIG_PACKAGE_libopenssl-devcrypto\n      OPENSSL_OPTIONS += enable-devcryptoeng\n    endif\n    ifndef CONFIG_PACKAGE_libopenssl-afalg\n      OPENSSL_OPTIONS += no-afalgeng\n    endif\n    ifndef CONFIG_PACKAGE_libopenssl-padlock\n      OPENSSL_OPTIONS += no-hw-padlock\n    endif\n  endif\nelse\n  OPENSSL_OPTIONS += no-engine\nendif\n\nifndef CONFIG_OPENSSL_WITH_DTLS\n  OPENSSL_OPTIONS += no-dtls\nendif\n\nifdef CONFIG_OPENSSL_WITH_COMPRESSION\n  OPENSSL_OPTIONS += zlib-dynamic\nelse\n  OPENSSL_OPTIONS += no-comp\nendif\n\nifndef CONFIG_OPENSSL_WITH_NPN\n  OPENSSL_OPTIONS += no-nextprotoneg\nendif\n\nifndef CONFIG_OPENSSL_WITH_PSK\n  OPENSSL_OPTIONS += no-psk\nendif\n\nifndef CONFIG_OPENSSL_WITH_SRP\n  OPENSSL_OPTIONS += no-srp\nendif\n\nifndef CONFIG_OPENSSL_WITH_ASM\n  OPENSSL_OPTIONS += no-asm\nendif\n\nifdef CONFIG_i386\n  ifndef CONFIG_OPENSSL_WITH_SSE2\n    OPENSSL_OPTIONS += no-sse2\n  endif\nendif\n\nOPENSSL_TARGET:=linux-$(call qstrip,$(CONFIG_ARCH))-openwrt\n\nSTAMP_CONFIGURED := $(STAMP_CONFIGURED)_$(shell echo $(OPENSSL_OPTIONS) | $(MKHASH) md5)\n\ndefine Build/Configure\n\t(cd $(PKG_BUILD_DIR); \\\n\t\t./Configure $(OPENSSL_TARGET) \\\n\t\t\t--prefix=/usr \\\n\t\t\t--libdir=lib \\\n\t\t\t--openssldir=/etc/ssl \\\n\t\t\t--cross-compile-prefix=\"$(TARGET_CROSS)\" \\\n\t\t\t$(TARGET_CPPFLAGS) \\\n\t\t\t$(TARGET_LDFLAGS) \\\n\t\t\t$(OPENSSL_OPTIONS) && \\\n\t\t{ [ -f $(STAMP_CONFIGURED) ] || make clean; } \\\n\t)\nendef\n\nTARGET_CFLAGS += $(FPIC) -ffunction-sections -fdata-sections\nTARGET_LDFLAGS += -Wl,--gc-sections\n\ndefine Build/Compile\n\t+$(MAKE) $(PKG_JOBS) -C $(PKG_BUILD_DIR) \\\n\t\tCC=\"$(TARGET_CC)\" \\\n\t\tSOURCE_DATE_EPOCH=$(SOURCE_DATE_EPOCH) \\\n\t\tOPENWRT_OPTIMIZATION_FLAGS=\"$(TARGET_CFLAGS)\" \\\n\t\t$(OPENSSL_MAKEFLAGS) \\\n\t\tall\n\t$(MAKE) -C $(PKG_BUILD_DIR) \\\n\t\tCC=\"$(TARGET_CC)\" \\\n\t\tDESTDIR=\"$(PKG_INSTALL_DIR)\" \\\n\t\t$(OPENSSL_MAKEFLAGS) \\\n\t\tinstall_sw install_ssldirs\nendef\n\ndefine Build/InstallDev\n\t$(INSTALL_DIR) $(1)/usr/include\n\t$(CP) $(PKG_INSTALL_DIR)/usr/include/openssl $(1)/usr/include/\n\t$(INSTALL_DIR) $(1)/usr/lib/\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/lib{crypto,ssl}.{a,so*} $(1)/usr/lib/\n\t$(INSTALL_DIR) $(1)/usr/lib/pkgconfig\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/pkgconfig/{openssl,libcrypto,libssl}.pc $(1)/usr/lib/pkgconfig/\n\t[ -n \"$(TARGET_LDFLAGS)\" ] && $(SED) 's#$(TARGET_LDFLAGS)##g' $(1)/usr/lib/pkgconfig/{openssl,libcrypto,libssl}.pc || true\nendef\n\ndefine Package/libopenssl/install\n\t$(INSTALL_DIR) $(1)/etc/ssl/certs\n\t$(INSTALL_DIR) $(1)/etc/ssl/private\n\tchmod 0700 $(1)/etc/ssl/private\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(INSTALL_DATA) $(PKG_INSTALL_DIR)/usr/lib/libcrypto.so.* $(1)/usr/lib/\n\t$(INSTALL_DATA) $(PKG_INSTALL_DIR)/usr/lib/libssl.so.* $(1)/usr/lib/\n\t$(if $(CONFIG_OPENSSL_ENGINE),$(INSTALL_DIR) $(1)/usr/lib/$(ENGINES_DIR))\nendef\n\ndefine Package/libopenssl-conf/install\n\t$(INSTALL_DIR) $(1)/etc/ssl/engines.cnf.d $(1)/etc/config $(1)/etc/init.d\n\t$(CP) $(PKG_INSTALL_DIR)/etc/ssl/openssl.cnf $(1)/etc/ssl/\n\t$(INSTALL_BIN) ./files/openssl.init $(1)/etc/init.d/openssl\n\t$(SED) 's!%ENGINES_DIR%!/usr/lib/$(ENGINES_DIR)!' $(1)/etc/init.d/openssl\n\ttouch $(1)/etc/config/openssl\n\t$(if $(CONFIG_OPENSSL_ENGINE_BUILTIN_DEVCRYPTO),\n\t\t$(CP) ./files/devcrypto.cnf $(1)/etc/ssl/engines.cnf.d/\n\t\techo -e \"config engine 'devcrypto'\\n\\toption enabled '1'\" >> $(1)/etc/config/openssl)\n\t$(if $(CONFIG_OPENSSL_ENGINE_BUILTIN_PADLOCK),\n\t\t$(CP) ./files/padlock.cnf $(1)/etc/ssl/engines.cnf.d/\n\t\techo -e \"\\nconfig engine 'padlock'\\n\\toption enabled '1'\" >> $(1)/etc/config/openssl)\nendef\n\ndefine Package/openssl-util/install\n\t$(INSTALL_DIR) $(1)/usr/bin\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/bin/openssl $(1)/usr/bin/\nendef\n\n$(eval $(call BuildPackage,libopenssl))\n$(eval $(call BuildPackage,libopenssl-conf))\n$(eval $(call BuildPackage,libopenssl-afalg))\n$(eval $(call BuildPackage,libopenssl-devcrypto))\n$(eval $(call BuildPackage,libopenssl-padlock))\n$(eval $(call BuildPackage,openssl-util))\n"
  },
  {
    "path": "package/libs/openssl/files/afalg.cnf",
    "content": "[afalg]\ndefault_algorithms = ALL\n\n"
  },
  {
    "path": "package/libs/openssl/files/devcrypto.cnf",
    "content": "[devcrypto]\n# Leave this alone and configure algorithms with CIPERS/DIGESTS below\ndefault_algorithms = ALL\n\n# Configuration commands:\n# Run 'openssl engine -t -c -vv -pre DUMP_INFO devcrypto' to see a\n# list of supported algorithms, along with their driver, whether they\n# are hw accelerated or not, and the engine's configuration commands.\n\n# USE_SOFTDRIVERS: specifies whether to use software (not accelerated)\n# drivers (0=use only accelerated drivers, 1=allow all drivers, 2=use\n# if acceleration can't be determined) [default=2]\n#USE_SOFTDRIVERS = 2\n\n# CIPHERS: either ALL, NONE, or a comma-separated list of ciphers to\n# enable [default=ALL]\n# It is recommended to disable the ECB ciphers; in most cases, it will\n# only be used for PRNG, in small blocks, where performance is poor,\n# and there may be problems with apps forking with open crypto\n# contexts, leading to failures.  The CBC ciphers work well:\n#CIPHERS=DES-CBC, DES-EDE3-CBC, AES-128-CBC, AES-192-CBC, AES-256-CBC\n\n# DIGESTS: either ALL, NONE, or a comma-separated list of digests to\n# enable [default=NONE]\n# It is strongly recommended not to enable digests; their performance\n# is poor, and there are many cases in which they will not work,\n# especially when calling fork with open crypto contexts.  Openssh,\n# for example, does this, and you may not be able to login.\n#DIGESTS = NONE\n\n\n"
  },
  {
    "path": "package/libs/openssl/files/openssl.init",
    "content": "#!/bin/sh /etc/rc.common\n\nSTART=13\nENGINES_CNF_D=\"/etc/ssl/engines.cnf.d\"\nENGINES_CNF=\"/var/etc/ssl/engines.cnf\"\nENGINES_DIR=\"%ENGINES_DIR%\"\n\nconfig_engine() {\n\tlocal enabled force\n\tconfig_get_bool enabled \"$1\" enabled 1\n\tconfig_get_bool force \"$1\" force 0\n\t[ \"$enabled\" = 0 ] && return\n\tif [ \"$force\" = 0 ] && \\\n\t   [ ! -f \"${ENGINES_CNF_D}/$1.cnf\" ] && \\\n\t   [ ! -f \"${ENGINES_DIR}/$1.so\" ]; then\n\t    echo Skipping engine \"$1\": not installed\n\t    return\n\tfi\n\techo Enabling engine \"$1\"\n\techo \"$1=$1\" >> \"${ENGINES_CNF}\"\n}\n\nstart() {\n\tmkdir -p \"$(dirname \"${ENGINES_CNF}\")\" || exit 1\n\techo Generating engines.cnf\n\techo \"# This file is automatically generated from /etc/config/openssl.\" \\\n\t      > \"${ENGINES_CNF}\" || \\\n\t      { echo Error writing ${ENGINES_CNF} >&2; exit 1; }\n        config_load openssl\n\tconfig_foreach config_engine engine\n}\n"
  },
  {
    "path": "package/libs/openssl/files/padlock.cnf",
    "content": "[padlock]\ndefault_algorithms = ALL\n\n"
  },
  {
    "path": "package/libs/openssl/patches/001-crypto-perlasm-ppc-xlate.pl-add-linux64v2-flavour.patch",
    "content": "From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001\nFrom: Andy Polyakov <appro@openssl.org>\nDate: Sun, 5 May 2019 18:25:50 +0200\nSubject: crypto/perlasm/ppc-xlate.pl: add linux64v2 flavour\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nThis is a big endian ELFv2 configuration. ELFv2 was already being\nused for little endian, and big endian was traditionally ELFv1\nbut there are practical configurations that use ELFv2 with big\nendian nowadays (Adélie Linux, Void Linux, possibly Gentoo, etc.)\n\nReviewed-by: Paul Dale <paul.dale@oracle.com>\nReviewed-by: Richard Levitte <levitte@openssl.org>\n(Merged from https://github.com/openssl/openssl/pull/8883)\n\ndiff --git a/crypto/perlasm/ppc-xlate.pl b/crypto/perlasm/ppc-xlate.pl\n--- a/crypto/perlasm/ppc-xlate.pl\n+++ b/crypto/perlasm/ppc-xlate.pl\n@@ -49,7 +49,7 @@ my $globl = sub {\n \t/osx/\t\t&& do { $name = \"_$name\";\n \t\t\t\tlast;\n \t\t\t      };\n-\t/linux.*(32|64le)/\n+\t/linux.*(32|64(le|v2))/\n \t\t\t&& do {\t$ret .= \".globl\t$name\";\n \t\t\t\tif (!$$type) {\n \t\t\t\t    $ret .= \"\\n.type\t$name,\\@function\";\n@@ -80,7 +80,7 @@ my $globl = sub {\n };\n my $text = sub {\n     my $ret = ($flavour =~ /aix/) ? \".csect\\t.text[PR],7\" : \".text\";\n-    $ret = \".abiversion\t2\\n\".$ret\tif ($flavour =~ /linux.*64le/);\n+    $ret = \".abiversion\t2\\n\".$ret\tif ($flavour =~ /linux.*64(le|v2)/);\n     $ret;\n };\n my $machine = sub {\n@@ -186,7 +186,7 @@ my $vmr = sub {\n \n # Some ABIs specify vrsave, special-purpose register #256, as reserved\n # for system use.\n-my $no_vrsave = ($flavour =~ /aix|linux64le/);\n+my $no_vrsave = ($flavour =~ /aix|linux64(le|v2)/);\n my $mtspr = sub {\n     my ($f,$idx,$ra) = @_;\n     if ($idx == 256 && $no_vrsave) {\n@@ -318,7 +318,7 @@ while($line=<>) {\n \tif ($label) {\n \t    my $xlated = ($GLOBALS{$label} or $label);\n \t    print \"$xlated:\";\n-\t    if ($flavour =~ /linux.*64le/) {\n+\t    if ($flavour =~ /linux.*64(le|v2)/) {\n \t\tif ($TYPES{$label} =~ /function/) {\n \t\t    printf \"\\n.localentry\t%s,0\\n\",$xlated;\n \t\t}\n"
  },
  {
    "path": "package/libs/openssl/patches/100-Configure-afalg-support.patch",
    "content": "From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001\nFrom: Eneas U de Queiroz <cote2004-github@yahoo.com>\nDate: Thu, 27 Sep 2018 08:29:21 -0300\nSubject: Do not use host kernel version to disable AFALG\n\nThis patch prevents the Configure script from using the host kernel\nversion to disable building the AFALG engine on openwrt targets.\n\nSigned-off-by: Eneas U de Queiroz <cote2004-github@yahoo.com>\n\ndiff --git a/Configure b/Configure\n--- a/Configure\n+++ b/Configure\n@@ -1548,7 +1548,9 @@ unless ($disabled{\"crypto-mdebug-backtrace\"})\n \n unless ($disabled{afalgeng}) {\n     $config{afalgeng}=\"\";\n-    if (grep { $_ eq 'afalgeng' } @{$target{enable}}) {\n+    if ($target =~ m/openwrt$/) {\n+        push @{$config{engdirs}}, \"afalg\";\n+    } elsif (grep { $_ eq 'afalgeng' } @{$target{enable}}) {\n         my $minver = 4*10000 + 1*100 + 0;\n         if ($config{CROSS_COMPILE} eq \"\") {\n             my $verstr = `uname -r`;\n"
  },
  {
    "path": "package/libs/openssl/patches/110-openwrt_targets.patch",
    "content": "From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001\nFrom: Eneas U de Queiroz <cote2004-github@yahoo.com>\nDate: Thu, 27 Sep 2018 08:30:24 -0300\nSubject: Add openwrt targets\n\nTargets are named: linux-$(CONFIG_ARCH)-openwrt\n\nSigned-off-by: Eneas U de Queiroz <cote2004-github@yahoo.com>\n\ndiff --git a/Configurations/25-openwrt.conf b/Configurations/25-openwrt.conf\nnew file mode 100644\n--- /dev/null\n+++ b/Configurations/25-openwrt.conf\n@@ -0,0 +1,52 @@\n+## Openwrt \"CONFIG_ARCH\" matching targets.\n+\n+# The targets need to end in '-openwrt' for the AFALG patch to work\n+\n+my %targets = (\n+    \"openwrt\" => {\n+\ttemplate\t=> 1,\n+\tCFLAGS\t\t=> add(\"\\$(OPENWRT_OPTIMIZATION_FLAGS)\"),\n+    },\n+    \"linux-aarch64-openwrt\" => {\n+        inherit_from    => [ \"linux-aarch64\", \"openwrt\" ],\n+    },\n+    \"linux-arc-openwrt\" => {\n+        inherit_from    => [ \"linux-generic32\", \"openwrt\" ],\n+    },\n+    \"linux-arm-openwrt\" => {\n+        inherit_from    => [ \"linux-armv4\", \"openwrt\" ],\n+    },\n+    \"linux-armeb-openwrt\" => {\n+        inherit_from    => [ \"linux-armv4\", \"openwrt\" ],\n+    },\n+    \"linux-i386-openwrt\" => {\n+        inherit_from    => [ \"linux-x86\", \"openwrt\" ],\n+    },\n+    \"linux-mips-openwrt\" => {\n+        inherit_from    => [ \"linux-mips32\", \"openwrt\" ],\n+    },\n+    \"linux-mips64-openwrt\" => {\n+        inherit_from    => [ \"linux64-mips64\", \"openwrt\" ],\n+    },\n+    \"linux-mips64el-openwrt\" => {\n+        inherit_from    => [ \"linux64-mips64\", \"openwrt\" ],\n+    },\n+    \"linux-mipsel-openwrt\" => {\n+        inherit_from    => [ \"linux-mips32\", \"openwrt\" ],\n+    },\n+    \"linux-powerpc-openwrt\" => {\n+        inherit_from    => [ \"linux-ppc\", \"openwrt\" ],\n+    },\n+    \"linux-powerpc64-openwrt\" => {\n+        inherit_from    => [ \"linux-ppc64\", \"openwrt\" ],\n+        perlasm_scheme  => \"linux64v2\",\n+    },\n+    \"linux-x86_64-openwrt\" => {\n+        inherit_from    => [ \"linux-x86_64\", \"openwrt\" ],\n+    },\n+\n+### Basic default option\n+    \"linux-generic32-openwrt\" => {\n+        inherit_from    => [ \"linux-generic32\", \"openwrt\" ],\n+    },\n+);\n"
  },
  {
    "path": "package/libs/openssl/patches/120-strip-cflags-from-binary.patch",
    "content": "From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001\nFrom: Eneas U de Queiroz <cote2004-github@yahoo.com>\nDate: Thu, 27 Sep 2018 08:31:38 -0300\nSubject: Avoid exposing build directories\n\nThe CFLAGS contain the build directories, and are shown by calling\nOpenSSL_version(OPENSSL_CFLAGS), or running openssl version -a\n\nSigned-off-by: Eneas U de Queiroz <cote2004-github@yahoo.com>\n\ndiff --git a/crypto/build.info b/crypto/build.info\n--- a/crypto/build.info\n+++ b/crypto/build.info\n@@ -10,7 +10,7 @@ EXTRA=  ../ms/uplink-x86.pl ../ms/uplink.c ../ms/applink.c \\\n         ppccpuid.pl pariscid.pl alphacpuid.pl arm64cpuid.pl armv4cpuid.pl\n \n DEPEND[cversion.o]=buildinf.h\n-GENERATE[buildinf.h]=../util/mkbuildinf.pl \"$(CC) $(LIB_CFLAGS) $(CPPFLAGS_Q)\" \"$(PLATFORM)\"\n+GENERATE[buildinf.h]=../util/mkbuildinf.pl \"$(filter-out -I% -iremap% -fmacro-prefix-map% -ffile-prefix-map%,$(CC) $(LIB_CFLAGS) $(CPPFLAGS_Q))\" \"$(PLATFORM)\"\n DEPEND[buildinf.h]=../configdata.pm\n \n GENERATE[uplink-x86.s]=../ms/uplink-x86.pl $(PERLASM_SCHEME)\n"
  },
  {
    "path": "package/libs/openssl/patches/130-dont-build-tests-fuzz.patch",
    "content": "From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001\nFrom: Eneas U de Queiroz <cote2004-github@yahoo.com>\nDate: Thu, 27 Sep 2018 08:34:38 -0300\nSubject: Do not build tests and fuzz directories\n\nThis shortens build time.\n\nSigned-off-by: Eneas U de Queiroz <cote2004-github@yahoo.com>\n\ndiff --git a/Configure b/Configure\n--- a/Configure\n+++ b/Configure\n@@ -318,7 +318,7 @@ my $auto_threads=1;    # enable threads automatically? true by default\n my $default_ranlib;\n \n # Top level directories to build\n-$config{dirs} = [ \"crypto\", \"ssl\", \"engines\", \"apps\", \"test\", \"util\", \"tools\", \"fuzz\" ];\n+$config{dirs} = [ \"crypto\", \"ssl\", \"engines\", \"apps\", \"util\", \"tools\" ];\n # crypto/ subdirectories to build\n $config{sdirs} = [\n     \"objects\",\n@@ -330,7 +330,7 @@ $config{sdirs} = [\n     \"cms\", \"ts\", \"srp\", \"cmac\", \"ct\", \"async\", \"kdf\", \"store\"\n     ];\n # test/ subdirectories to build\n-$config{tdirs} = [ \"ossl_shim\" ];\n+$config{tdirs} = [];\n \n # Known TLS and DTLS protocols\n my @tls = qw(ssl3 tls1 tls1_1 tls1_2 tls1_3);\n"
  },
  {
    "path": "package/libs/openssl/patches/140-allow-prefer-chacha20.patch",
    "content": "From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001\nFrom: Eneas U de Queiroz <cote2004-github@yahoo.com>\nDate: Thu, 27 Sep 2018 08:44:39 -0300\nSubject: Add OPENSSL_PREFER_CHACHA_OVER_GCM option\n\nThis enables a compile-time option to prefer ChaCha20-Poly1305 over\nAES-GCM in the openssl default ciphersuite, which is useful in systems\nwithout AES specific CPU instructions.\nOPENSSL_PREFER_CHACHA_OVER_GCM must be defined to enable it.\n\nNote that this does not have the same effect as the\nSL_OP_PRIORITIZE_CHACHA option, which prioritizes ChaCha20-Poly1305 only\nwhen the client has it on top of its ciphersuite preference.\n\nSigned-off-by: Eneas U de Queiroz <cote2004-github@yahoo.com>\n\ndiff --git a/include/openssl/ssl.h b/include/openssl/ssl.h\n--- a/include/openssl/ssl.h\n+++ b/include/openssl/ssl.h\n@@ -173,9 +173,15 @@ extern \"C\" {\n # define SSL_DEFAULT_CIPHER_LIST \"ALL:!COMPLEMENTOFDEFAULT:!eNULL\"\n /* This is the default set of TLSv1.3 ciphersuites */\n # if !defined(OPENSSL_NO_CHACHA) && !defined(OPENSSL_NO_POLY1305)\n-#  define TLS_DEFAULT_CIPHERSUITES \"TLS_AES_256_GCM_SHA384:\" \\\n-                                   \"TLS_CHACHA20_POLY1305_SHA256:\" \\\n-                                   \"TLS_AES_128_GCM_SHA256\"\n+#  ifdef OPENSSL_PREFER_CHACHA_OVER_GCM\n+#   define TLS_DEFAULT_CIPHERSUITES \"TLS_CHACHA20_POLY1305_SHA256:\" \\\n+                                    \"TLS_AES_256_GCM_SHA384:\" \\\n+                                    \"TLS_AES_128_GCM_SHA256\"\n+#  else\n+#   define TLS_DEFAULT_CIPHERSUITES \"TLS_AES_256_GCM_SHA384:\" \\\n+                                    \"TLS_CHACHA20_POLY1305_SHA256:\" \\\n+                                    \"TLS_AES_128_GCM_SHA256\"\n+#  endif\n # else\n #  define TLS_DEFAULT_CIPHERSUITES \"TLS_AES_256_GCM_SHA384:\" \\\n                                    \"TLS_AES_128_GCM_SHA256\"\ndiff --git a/ssl/ssl_ciph.c b/ssl/ssl_ciph.c\n--- a/ssl/ssl_ciph.c\n+++ b/ssl/ssl_ciph.c\n@@ -1467,11 +1467,29 @@ STACK_OF(SSL_CIPHER) *ssl_create_cipher_list(const SSL_METHOD *ssl_method,\n     ssl_cipher_apply_rule(0, SSL_kECDHE, 0, 0, 0, 0, 0, CIPHER_DEL, -1, &head,\n                           &tail);\n \n+    /*\n+     * If OPENSSL_PREFER_CHACHA_OVER_GCM is defined, ChaCha20_Poly1305\n+     * will be placed before AES-256.  Otherwise, the default behavior of\n+     * preferring GCM over CHACHA is used.\n+     * This is useful for systems that do not have AES-specific CPU\n+     * instructions, where ChaCha20-Poly1305 is 3 times faster than AES.\n+     * Note that this does not have the same effect as the SSL_OP_PRIORITIZE_CHACHA\n+     * option, which prioritizes ChaCha20-Poly1305 only when the client has it on top\n+     * of its ciphersuite preference.\n+     */\n+\n+#ifdef OPENSSL_PREFER_CHACHA_OVER_GCM\n+    ssl_cipher_apply_rule(0, 0, 0, SSL_CHACHA20, 0, 0, 0, CIPHER_ADD, -1,\n+                          &head, &tail);\n+    ssl_cipher_apply_rule(0, 0, 0, SSL_AESGCM, 0, 0, 0, CIPHER_ADD, -1,\n+                          &head, &tail);\n+#else\n     /* Within each strength group, we prefer GCM over CHACHA... */\n     ssl_cipher_apply_rule(0, 0, 0, SSL_AESGCM, 0, 0, 0, CIPHER_ADD, -1,\n                           &head, &tail);\n     ssl_cipher_apply_rule(0, 0, 0, SSL_CHACHA20, 0, 0, 0, CIPHER_ADD, -1,\n                           &head, &tail);\n+#endif\n \n     /*\n      * ...and generally, our preferred cipher is AES.\n@@ -1527,7 +1545,7 @@ STACK_OF(SSL_CIPHER) *ssl_create_cipher_list(const SSL_METHOD *ssl_method,\n      * Within each group, ciphers remain sorted by strength and previous\n      * preference, i.e.,\n      * 1) ECDHE > DHE\n-     * 2) GCM > CHACHA\n+     * 2) GCM > CHACHA, reversed if OPENSSL_PREFER_CHACHA_OVER_GCM is defined\n      * 3) AES > rest\n      * 4) TLS 1.2 > legacy\n      *\n"
  },
  {
    "path": "package/libs/openssl/patches/150-openssl.cnf-add-engines-conf.patch",
    "content": "From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001\nFrom: Eneas U de Queiroz <cotequeiroz@gmail.com>\nDate: Sat, 27 Mar 2021 17:43:25 -0300\nSubject: openssl.cnf: add engine configuration\n\nThis adds configuration options for engines, loading all cnf files under\n/etc/ssl/engines.cnf.d/.\n\nSigned-off-by: Eneas U de Queiroz <cotequeiroz@gmail.com>\n\ndiff --git a/apps/openssl.cnf b/apps/openssl.cnf\n--- a/apps/openssl.cnf\n+++ b/apps/openssl.cnf\n@@ -22,6 +22,16 @@ oid_section\t\t= new_oids\n # (Alternatively, use a configuration file that has only\n # X.509v3 extensions in its main [= default] section.)\n \n+openssl_conf=openssl_conf\n+\n+[openssl_conf]\n+engines=engines\n+\n+[engines]\n+.include /var/etc/ssl/engines.cnf\n+\n+.include /etc/ssl/engines.cnf.d\n+\n [ new_oids ]\n \n # We can add new OIDs in here for use by 'ca', 'req' and 'ts'.\n"
  },
  {
    "path": "package/libs/openssl/patches/400-eng_devcrypto-save-ioctl-if-EVP_MD_.FLAG_ONESHOT.patch",
    "content": "From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001\nFrom: Eneas U de Queiroz <cote2004-github@yahoo.com>\nDate: Mon, 5 Nov 2018 15:54:17 -0200\nSubject: eng_devcrypto: save ioctl if EVP_MD_..FLAG_ONESHOT\n\nSince each ioctl causes a context switch, slowing things down, if\nEVP_MD_CTX_FLAG_ONESHOT is set, then:\n - call the ioctl in digest_update, saving the result; and\n - just copy the result in digest_final, instead of using another ioctl.\n\nSigned-off-by: Eneas U de Queiroz <cote2004-github@yahoo.com>\n\nReviewed-by: Matthias St. Pierre <Matthias.St.Pierre@ncp-e.com>\nReviewed-by: Richard Levitte <levitte@openssl.org>\n(Merged from https://github.com/openssl/openssl/pull/7585)\n\ndiff --git a/crypto/engine/eng_devcrypto.c b/crypto/engine/eng_devcrypto.c\n--- a/crypto/engine/eng_devcrypto.c\n+++ b/crypto/engine/eng_devcrypto.c\n@@ -461,6 +461,7 @@ struct digest_ctx {\n     struct session_op sess;\n     /* This signals that the init function was called, not that it succeeded. */\n     int init_called;\n+    unsigned char digest_res[HASH_MAX_LEN];\n };\n \n static const struct digest_data_st {\n@@ -564,12 +565,15 @@ static int digest_update(EVP_MD_CTX *ctx, const void *data, size_t count)\n     if (digest_ctx == NULL)\n         return 0;\n \n-    if (digest_op(digest_ctx, data, count, NULL, COP_FLAG_UPDATE) < 0) {\n-        SYSerr(SYS_F_IOCTL, errno);\n-        return 0;\n+    if (EVP_MD_CTX_test_flags(ctx, EVP_MD_CTX_FLAG_ONESHOT)) {\n+        if (digest_op(digest_ctx, data, count, digest_ctx->digest_res, 0) >= 0)\n+            return 1;\n+    } else if (digest_op(digest_ctx, data, count, NULL, COP_FLAG_UPDATE) >= 0) {\n+        return 1;\n     }\n \n-    return 1;\n+    SYSerr(SYS_F_IOCTL, errno);\n+    return 0;\n }\n \n static int digest_final(EVP_MD_CTX *ctx, unsigned char *md)\n@@ -579,7 +583,10 @@ static int digest_final(EVP_MD_CTX *ctx, unsigned char *md)\n \n     if (md == NULL || digest_ctx == NULL)\n         return 0;\n-    if (digest_op(digest_ctx, NULL, 0, md, COP_FLAG_FINAL) < 0) {\n+\n+    if (EVP_MD_CTX_test_flags(ctx, EVP_MD_CTX_FLAG_ONESHOT)) {\n+        memcpy(md, digest_ctx->digest_res, EVP_MD_CTX_size(ctx));\n+    } else if (digest_op(digest_ctx, NULL, 0, md, COP_FLAG_FINAL) < 0) {\n         SYSerr(SYS_F_IOCTL, errno);\n         return 0;\n     }\n"
  },
  {
    "path": "package/libs/openssl/patches/410-eng_devcrypto-add-configuration-options.patch",
    "content": "From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001\nFrom: Eneas U de Queiroz <cote2004-github@yahoo.com>\nDate: Sat, 3 Nov 2018 15:41:10 -0300\nSubject: eng_devcrypto: add configuration options\n\nUSE_SOFTDRIVERS: whether to use software (not accelerated) drivers\nCIPHERS: list of ciphers to enable\nDIGESTS: list of digests to enable\n\nSigned-off-by: Eneas U de Queiroz <cote2004-github@yahoo.com>\n\nReviewed-by: Matthias St. Pierre <Matthias.St.Pierre@ncp-e.com>\nReviewed-by: Richard Levitte <levitte@openssl.org>\n(Merged from https://github.com/openssl/openssl/pull/7585)\n\ndiff --git a/crypto/engine/eng_devcrypto.c b/crypto/engine/eng_devcrypto.c\n--- a/crypto/engine/eng_devcrypto.c\n+++ b/crypto/engine/eng_devcrypto.c\n@@ -16,6 +16,7 @@\n #include <unistd.h>\n #include <assert.h>\n \n+#include <openssl/conf.h>\n #include <openssl/evp.h>\n #include <openssl/err.h>\n #include <openssl/engine.h>\n@@ -36,6 +37,30 @@\n  * saner...  why re-open /dev/crypto for every session?\n  */\n static int cfd;\n+#define DEVCRYPTO_REQUIRE_ACCELERATED 0 /* require confirmation of acceleration */\n+#define DEVCRYPTO_USE_SOFTWARE        1 /* allow software drivers */\n+#define DEVCRYPTO_REJECT_SOFTWARE     2 /* only disallow confirmed software drivers */\n+\n+#define DEVCRYPTO_DEFAULT_USE_SOFDTRIVERS DEVCRYPTO_REJECT_SOFTWARE\n+static int use_softdrivers = DEVCRYPTO_DEFAULT_USE_SOFDTRIVERS;\n+\n+/*\n+ * cipher/digest status & acceleration definitions\n+ * Make sure the defaults are set to 0\n+ */\n+struct driver_info_st {\n+    enum devcrypto_status_t {\n+        DEVCRYPTO_STATUS_UNUSABLE       = -1, /* session open failed */\n+        DEVCRYPTO_STATUS_UNKNOWN        =  0, /* not tested yet */\n+        DEVCRYPTO_STATUS_USABLE         =  1  /* algo can be used */\n+    } status;\n+\n+    enum devcrypto_accelerated_t {\n+        DEVCRYPTO_NOT_ACCELERATED       = -1, /* software implemented */\n+        DEVCRYPTO_ACCELERATION_UNKNOWN  =  0, /* acceleration support unkown */\n+        DEVCRYPTO_ACCELERATED           =  1  /* hardware accelerated */\n+    } accelerated;\n+};\n \n static int clean_devcrypto_session(struct session_op *sess) {\n     if (ioctl(cfd, CIOCFSESSION, &sess->ses) < 0) {\n@@ -119,13 +144,22 @@ static const struct cipher_data_st {\n #endif\n };\n \n-static size_t get_cipher_data_index(int nid)\n+static size_t find_cipher_data_index(int nid)\n {\n     size_t i;\n \n     for (i = 0; i < OSSL_NELEM(cipher_data); i++)\n         if (nid == cipher_data[i].nid)\n             return i;\n+    return (size_t)-1;\n+}\n+\n+static size_t get_cipher_data_index(int nid)\n+{\n+    size_t i = find_cipher_data_index(nid);\n+\n+    if (i != (size_t)-1)\n+        return i;\n \n     /*\n      * Code further down must make sure that only NIDs in the table above\n@@ -333,19 +367,40 @@ static int cipher_cleanup(EVP_CIPHER_CTX *ctx)\n }\n \n /*\n- * Keep a table of known nids and associated methods.\n+ * Keep tables of known nids, associated methods, selected ciphers, and driver\n+ * info.\n  * Note that known_cipher_nids[] isn't necessarily indexed the same way as\n- * cipher_data[] above, which known_cipher_methods[] is.\n+ * cipher_data[] above, which the other tables are.\n  */\n static int known_cipher_nids[OSSL_NELEM(cipher_data)];\n static int known_cipher_nids_amount = -1; /* -1 indicates not yet initialised */\n static EVP_CIPHER *known_cipher_methods[OSSL_NELEM(cipher_data)] = { NULL, };\n+static int selected_ciphers[OSSL_NELEM(cipher_data)];\n+static struct driver_info_st cipher_driver_info[OSSL_NELEM(cipher_data)];\n+\n+\n+static int devcrypto_test_cipher(size_t cipher_data_index)\n+{\n+    return (cipher_driver_info[cipher_data_index].status == DEVCRYPTO_STATUS_USABLE\n+            && selected_ciphers[cipher_data_index] == 1\n+            && (cipher_driver_info[cipher_data_index].accelerated\n+                    == DEVCRYPTO_ACCELERATED\n+                || use_softdrivers == DEVCRYPTO_USE_SOFTWARE\n+                || (cipher_driver_info[cipher_data_index].accelerated\n+                        != DEVCRYPTO_NOT_ACCELERATED\n+                    && use_softdrivers == DEVCRYPTO_REJECT_SOFTWARE)));\n+}\n \n static void prepare_cipher_methods(void)\n {\n     size_t i;\n     struct session_op sess;\n     unsigned long cipher_mode;\n+#ifdef CIOCGSESSINFO\n+    struct session_info_op siop;\n+#endif\n+\n+    memset(&cipher_driver_info, 0, sizeof(cipher_driver_info));\n \n     memset(&sess, 0, sizeof(sess));\n     sess.key = (void *)\"01234567890123456789012345678901234567890123456789\";\n@@ -353,15 +408,16 @@ static void prepare_cipher_methods(void)\n     for (i = 0, known_cipher_nids_amount = 0;\n          i < OSSL_NELEM(cipher_data); i++) {\n \n+        selected_ciphers[i] = 1;\n         /*\n-         * Check that the algo is really availably by trying to open and close\n-         * a session.\n+         * Check that the cipher is usable\n          */\n         sess.cipher = cipher_data[i].devcryptoid;\n         sess.keylen = cipher_data[i].keylen;\n-        if (ioctl(cfd, CIOCGSESSION, &sess) < 0\n-            || ioctl(cfd, CIOCFSESSION, &sess.ses) < 0)\n+        if (ioctl(cfd, CIOCGSESSION, &sess) < 0) {\n+            cipher_driver_info[i].status = DEVCRYPTO_STATUS_UNUSABLE;\n             continue;\n+        }\n \n         cipher_mode = cipher_data[i].flags & EVP_CIPH_MODE;\n \n@@ -387,15 +443,41 @@ static void prepare_cipher_methods(void)\n                                             cipher_cleanup)\n             || !EVP_CIPHER_meth_set_impl_ctx_size(known_cipher_methods[i],\n                                                   sizeof(struct cipher_ctx))) {\n+            cipher_driver_info[i].status = DEVCRYPTO_STATUS_UNUSABLE;\n             EVP_CIPHER_meth_free(known_cipher_methods[i]);\n             known_cipher_methods[i] = NULL;\n         } else {\n+            cipher_driver_info[i].status = DEVCRYPTO_STATUS_USABLE;\n+#ifdef CIOCGSESSINFO\n+            siop.ses = sess.ses;\n+            if (ioctl(cfd, CIOCGSESSINFO, &siop) < 0)\n+                cipher_driver_info[i].accelerated = DEVCRYPTO_ACCELERATION_UNKNOWN;\n+            else if (!(siop.flags & SIOP_FLAG_KERNEL_DRIVER_ONLY))\n+                cipher_driver_info[i].accelerated = DEVCRYPTO_NOT_ACCELERATED;\n+            else\n+                cipher_driver_info[i].accelerated = DEVCRYPTO_ACCELERATED;\n+#endif /* CIOCGSESSINFO */\n+        }\n+        ioctl(cfd, CIOCFSESSION, &sess.ses);\n+        if (devcrypto_test_cipher(i)) {\n             known_cipher_nids[known_cipher_nids_amount++] =\n                 cipher_data[i].nid;\n         }\n     }\n }\n \n+static void rebuild_known_cipher_nids(ENGINE *e)\n+{\n+    size_t i;\n+\n+    for (i = 0, known_cipher_nids_amount = 0; i < OSSL_NELEM(cipher_data); i++) {\n+        if (devcrypto_test_cipher(i))\n+            known_cipher_nids[known_cipher_nids_amount++] = cipher_data[i].nid;\n+    }\n+    ENGINE_unregister_ciphers(e);\n+    ENGINE_register_ciphers(e);\n+}\n+\n static const EVP_CIPHER *get_cipher_method(int nid)\n {\n     size_t i = get_cipher_data_index(nid);\n@@ -438,6 +520,36 @@ static int devcrypto_ciphers(ENGINE *e, const EVP_CIPHER **cipher,\n     return *cipher != NULL;\n }\n \n+static void devcrypto_select_all_ciphers(int *cipher_list)\n+{\n+    size_t i;\n+\n+    for (i = 0; i < OSSL_NELEM(cipher_data); i++)\n+        cipher_list[i] = 1;\n+}\n+\n+static int cryptodev_select_cipher_cb(const char *str, int len, void *usr)\n+{\n+    int *cipher_list = (int *)usr;\n+    char *name;\n+    const EVP_CIPHER *EVP;\n+    size_t i;\n+\n+    if (len == 0)\n+        return 1;\n+    if (usr == NULL || (name = OPENSSL_strndup(str, len)) == NULL)\n+        return 0;\n+    EVP = EVP_get_cipherbyname(name);\n+    if (EVP == NULL)\n+        fprintf(stderr, \"devcrypto: unknown cipher %s\\n\", name);\n+    else if ((i = find_cipher_data_index(EVP_CIPHER_nid(EVP))) != (size_t)-1)\n+        cipher_list[i] = 1;\n+    else\n+        fprintf(stderr, \"devcrypto: cipher %s not available\\n\", name);\n+    OPENSSL_free(name);\n+    return 1;\n+}\n+\n /*\n  * We only support digests if the cryptodev implementation supports multiple\n  * data updates and session copying.  Otherwise, we would be forced to maintain\n@@ -493,13 +605,22 @@ static const struct digest_data_st {\n #endif\n };\n \n-static size_t get_digest_data_index(int nid)\n+static size_t find_digest_data_index(int nid)\n {\n     size_t i;\n \n     for (i = 0; i < OSSL_NELEM(digest_data); i++)\n         if (nid == digest_data[i].nid)\n             return i;\n+    return (size_t)-1;\n+}\n+\n+static size_t get_digest_data_index(int nid)\n+{\n+    size_t i = find_digest_data_index(nid);\n+\n+    if (i != (size_t)-1)\n+        return i;\n \n     /*\n      * Code further down must make sure that only NIDs in the table above\n@@ -516,8 +637,8 @@ static const struct digest_data_st *get_digest_data(int nid)\n }\n \n /*\n- * Following are the four necessary functions to map OpenSSL functionality\n- * with cryptodev.\n+ * Following are the five necessary functions to map OpenSSL functionality\n+ * with cryptodev: init, update, final, cleanup, and copy.\n  */\n \n static int digest_init(EVP_MD_CTX *ctx)\n@@ -630,52 +751,94 @@ static int digest_cleanup(EVP_MD_CTX *ctx)\n     return clean_devcrypto_session(&digest_ctx->sess);\n }\n \n-static int devcrypto_test_digest(size_t digest_data_index)\n-{\n-    struct session_op sess1, sess2;\n-    struct cphash_op cphash;\n-    int ret=0;\n-\n-    memset(&sess1, 0, sizeof(sess1));\n-    memset(&sess2, 0, sizeof(sess2));\n-    sess1.mac = digest_data[digest_data_index].devcryptoid;\n-    if (ioctl(cfd, CIOCGSESSION, &sess1) < 0)\n-        return 0;\n-    /* Make sure the driver is capable of hash state copy */\n-    sess2.mac = sess1.mac;\n-    if (ioctl(cfd, CIOCGSESSION, &sess2) >= 0) {\n-        cphash.src_ses = sess1.ses;\n-        cphash.dst_ses = sess2.ses;\n-        if (ioctl(cfd, CIOCCPHASH, &cphash) >= 0)\n-            ret = 1;\n-        ioctl(cfd, CIOCFSESSION, &sess2.ses);\n-    }\n-    ioctl(cfd, CIOCFSESSION, &sess1.ses);\n-    return ret;\n-}\n-\n /*\n- * Keep a table of known nids and associated methods.\n+ * Keep tables of known nids, associated methods, selected digests, and\n+ * driver info.\n  * Note that known_digest_nids[] isn't necessarily indexed the same way as\n- * digest_data[] above, which known_digest_methods[] is.\n+ * digest_data[] above, which the other tables are.\n  */\n static int known_digest_nids[OSSL_NELEM(digest_data)];\n static int known_digest_nids_amount = -1; /* -1 indicates not yet initialised */\n static EVP_MD *known_digest_methods[OSSL_NELEM(digest_data)] = { NULL, };\n+static int selected_digests[OSSL_NELEM(digest_data)];\n+static struct driver_info_st digest_driver_info[OSSL_NELEM(digest_data)];\n+\n+static int devcrypto_test_digest(size_t digest_data_index)\n+{\n+    return (digest_driver_info[digest_data_index].status == DEVCRYPTO_STATUS_USABLE\n+            && selected_digests[digest_data_index] == 1\n+            && (digest_driver_info[digest_data_index].accelerated\n+                    == DEVCRYPTO_ACCELERATED\n+                || use_softdrivers == DEVCRYPTO_USE_SOFTWARE\n+                || (digest_driver_info[digest_data_index].accelerated\n+                        != DEVCRYPTO_NOT_ACCELERATED\n+                    && use_softdrivers == DEVCRYPTO_REJECT_SOFTWARE)));\n+}\n+\n+static void rebuild_known_digest_nids(ENGINE *e)\n+{\n+    size_t i;\n+\n+    for (i = 0, known_digest_nids_amount = 0; i < OSSL_NELEM(digest_data); i++) {\n+        if (devcrypto_test_digest(i))\n+            known_digest_nids[known_digest_nids_amount++] = digest_data[i].nid;\n+    }\n+    ENGINE_unregister_digests(e);\n+    ENGINE_register_digests(e);\n+}\n \n static void prepare_digest_methods(void)\n {\n     size_t i;\n+    struct session_op sess1, sess2;\n+#ifdef CIOCGSESSINFO\n+    struct session_info_op siop;\n+#endif\n+    struct cphash_op cphash;\n+\n+    memset(&digest_driver_info, 0, sizeof(digest_driver_info));\n+\n+    memset(&sess1, 0, sizeof(sess1));\n+    memset(&sess2, 0, sizeof(sess2));\n \n     for (i = 0, known_digest_nids_amount = 0; i < OSSL_NELEM(digest_data);\n          i++) {\n \n+        selected_digests[i] = 1;\n+\n         /*\n-         * Check that the algo is usable\n+         * Check that the digest is usable\n          */\n-        if (!devcrypto_test_digest(i))\n-            continue;\n+        sess1.mac = digest_data[i].devcryptoid;\n+        sess2.ses = 0;\n+        if (ioctl(cfd, CIOCGSESSION, &sess1) < 0) {\n+            digest_driver_info[i].status = DEVCRYPTO_STATUS_UNUSABLE;\n+            goto finish;\n+        }\n \n+#ifdef CIOCGSESSINFO\n+        /* gather hardware acceleration info from the driver */\n+        siop.ses = sess1.ses;\n+        if (ioctl(cfd, CIOCGSESSINFO, &siop) < 0)\n+            digest_driver_info[i].accelerated = DEVCRYPTO_ACCELERATION_UNKNOWN;\n+        else if (siop.flags & SIOP_FLAG_KERNEL_DRIVER_ONLY)\n+            digest_driver_info[i].accelerated = DEVCRYPTO_ACCELERATED;\n+        else\n+            digest_driver_info[i].accelerated = DEVCRYPTO_NOT_ACCELERATED;\n+#endif\n+\n+        /* digest must be capable of hash state copy */\n+        sess2.mac = sess1.mac;\n+        if (ioctl(cfd, CIOCGSESSION, &sess2) < 0) {\n+            digest_driver_info[i].status = DEVCRYPTO_STATUS_UNUSABLE;\n+            goto finish;\n+        }\n+        cphash.src_ses = sess1.ses;\n+        cphash.dst_ses = sess2.ses;\n+        if (ioctl(cfd, CIOCCPHASH, &cphash) < 0) {\n+            digest_driver_info[i].status = DEVCRYPTO_STATUS_UNUSABLE;\n+            goto finish;\n+        }\n         if ((known_digest_methods[i] = EVP_MD_meth_new(digest_data[i].nid,\n                                                        NID_undef)) == NULL\n             || !EVP_MD_meth_set_input_blocksize(known_digest_methods[i],\n@@ -689,11 +852,18 @@ static void prepare_digest_methods(void)\n             || !EVP_MD_meth_set_cleanup(known_digest_methods[i], digest_cleanup)\n             || !EVP_MD_meth_set_app_datasize(known_digest_methods[i],\n                                              sizeof(struct digest_ctx))) {\n+            digest_driver_info[i].status = DEVCRYPTO_STATUS_UNUSABLE;\n             EVP_MD_meth_free(known_digest_methods[i]);\n             known_digest_methods[i] = NULL;\n-        } else {\n-            known_digest_nids[known_digest_nids_amount++] = digest_data[i].nid;\n+            goto finish;\n         }\n+        digest_driver_info[i].status = DEVCRYPTO_STATUS_USABLE;\n+finish:\n+        ioctl(cfd, CIOCFSESSION, &sess1.ses);\n+        if (sess2.ses != 0)\n+            ioctl(cfd, CIOCFSESSION, &sess2.ses);\n+        if (devcrypto_test_digest(i))\n+            known_digest_nids[known_digest_nids_amount++] = digest_data[i].nid;\n     }\n }\n \n@@ -739,8 +909,154 @@ static int devcrypto_digests(ENGINE *e, const EVP_MD **digest,\n     return *digest != NULL;\n }\n \n+static void devcrypto_select_all_digests(int *digest_list)\n+{\n+    size_t i;\n+\n+    for (i = 0; i < OSSL_NELEM(digest_data); i++)\n+        digest_list[i] = 1;\n+}\n+\n+static int cryptodev_select_digest_cb(const char *str, int len, void *usr)\n+{\n+    int *digest_list = (int *)usr;\n+    char *name;\n+    const EVP_MD *EVP;\n+    size_t i;\n+\n+    if (len == 0)\n+        return 1;\n+    if (usr == NULL || (name = OPENSSL_strndup(str, len)) == NULL)\n+        return 0;\n+    EVP = EVP_get_digestbyname(name);\n+    if (EVP == NULL)\n+        fprintf(stderr, \"devcrypto: unknown digest %s\\n\", name);\n+    else if ((i = find_digest_data_index(EVP_MD_type(EVP))) != (size_t)-1)\n+        digest_list[i] = 1;\n+    else\n+        fprintf(stderr, \"devcrypto: digest %s not available\\n\", name);\n+    OPENSSL_free(name);\n+    return 1;\n+}\n+\n+#endif\n+\n+/******************************************************************************\n+ *\n+ * CONTROL COMMANDS\n+ *\n+ *****/\n+\n+#define DEVCRYPTO_CMD_USE_SOFTDRIVERS ENGINE_CMD_BASE\n+#define DEVCRYPTO_CMD_CIPHERS (ENGINE_CMD_BASE + 1)\n+#define DEVCRYPTO_CMD_DIGESTS (ENGINE_CMD_BASE + 2)\n+#define DEVCRYPTO_CMD_DUMP_INFO (ENGINE_CMD_BASE + 3)\n+\n+/* Helper macros for CPP string composition */\n+#ifndef OPENSSL_MSTR\n+# define OPENSSL_MSTR_HELPER(x) #x\n+# define OPENSSL_MSTR(x) OPENSSL_MSTR_HELPER(x)\n+#endif\n+\n+static const ENGINE_CMD_DEFN devcrypto_cmds[] = {\n+#ifdef CIOCGSESSINFO\n+   {DEVCRYPTO_CMD_USE_SOFTDRIVERS,\n+    \"USE_SOFTDRIVERS\",\n+    \"specifies whether to use software (not accelerated) drivers (\"\n+        OPENSSL_MSTR(DEVCRYPTO_REQUIRE_ACCELERATED) \"=use only accelerated drivers, \"\n+        OPENSSL_MSTR(DEVCRYPTO_USE_SOFTWARE) \"=allow all drivers, \"\n+        OPENSSL_MSTR(DEVCRYPTO_REJECT_SOFTWARE)\n+        \"=use if acceleration can't be determined) [default=\"\n+        OPENSSL_MSTR(DEVCRYPTO_DEFAULT_USE_SOFDTRIVERS) \"]\",\n+    ENGINE_CMD_FLAG_NUMERIC},\n+#endif\n+\n+   {DEVCRYPTO_CMD_CIPHERS,\n+    \"CIPHERS\",\n+    \"either ALL, NONE, or a comma-separated list of ciphers to enable [default=ALL]\",\n+    ENGINE_CMD_FLAG_STRING},\n+\n+#ifdef IMPLEMENT_DIGEST\n+   {DEVCRYPTO_CMD_DIGESTS,\n+    \"DIGESTS\",\n+    \"either ALL, NONE, or a comma-separated list of digests to enable [default=ALL]\",\n+    ENGINE_CMD_FLAG_STRING},\n #endif\n \n+   {0, NULL, NULL, 0}\n+};\n+\n+static int devcrypto_ctrl(ENGINE *e, int cmd, long i, void *p, void (*f) (void))\n+{\n+    int *new_list;\n+    switch (cmd) {\n+#ifdef CIOCGSESSINFO\n+    case DEVCRYPTO_CMD_USE_SOFTDRIVERS:\n+        switch (i) {\n+        case DEVCRYPTO_REQUIRE_ACCELERATED:\n+        case DEVCRYPTO_USE_SOFTWARE:\n+        case DEVCRYPTO_REJECT_SOFTWARE:\n+            break;\n+        default:\n+            fprintf(stderr, \"devcrypto: invalid value (%ld) for USE_SOFTDRIVERS\\n\", i);\n+            return 0;\n+        }\n+        if (use_softdrivers == i)\n+            return 1;\n+        use_softdrivers = i;\n+#ifdef IMPLEMENT_DIGEST\n+        rebuild_known_digest_nids(e);\n+#endif\n+        rebuild_known_cipher_nids(e);\n+        return 1;\n+#endif /* CIOCGSESSINFO */\n+\n+    case DEVCRYPTO_CMD_CIPHERS:\n+        if (p == NULL)\n+            return 1;\n+        if (strcasecmp((const char *)p, \"ALL\") == 0) {\n+            devcrypto_select_all_ciphers(selected_ciphers);\n+        } else if (strcasecmp((const char*)p, \"NONE\") == 0) {\n+            memset(selected_ciphers, 0, sizeof(selected_ciphers));\n+        } else {\n+            new_list=OPENSSL_zalloc(sizeof(selected_ciphers));\n+            if (!CONF_parse_list(p, ',', 1, cryptodev_select_cipher_cb, new_list)) {\n+                OPENSSL_free(new_list);\n+                return 0;\n+            }\n+            memcpy(selected_ciphers, new_list, sizeof(selected_ciphers));\n+            OPENSSL_free(new_list);\n+        }\n+        rebuild_known_cipher_nids(e);\n+        return 1;\n+\n+#ifdef IMPLEMENT_DIGEST\n+    case DEVCRYPTO_CMD_DIGESTS:\n+        if (p == NULL)\n+            return 1;\n+        if (strcasecmp((const char *)p, \"ALL\") == 0) {\n+            devcrypto_select_all_digests(selected_digests);\n+        } else if (strcasecmp((const char*)p, \"NONE\") == 0) {\n+            memset(selected_digests, 0, sizeof(selected_digests));\n+        } else {\n+            new_list=OPENSSL_zalloc(sizeof(selected_digests));\n+            if (!CONF_parse_list(p, ',', 1, cryptodev_select_digest_cb, new_list)) {\n+                OPENSSL_free(new_list);\n+                return 0;\n+            }\n+            memcpy(selected_digests, new_list, sizeof(selected_digests));\n+            OPENSSL_free(new_list);\n+        }\n+        rebuild_known_digest_nids(e);\n+        return 1;\n+#endif /* IMPLEMENT_DIGEST */\n+\n+    default:\n+        break;\n+    }\n+    return 0;\n+}\n+\n /******************************************************************************\n  *\n  * LOAD / UNLOAD\n@@ -806,6 +1122,8 @@ void engine_load_devcrypto_int()\n \n     if (!ENGINE_set_id(e, \"devcrypto\")\n         || !ENGINE_set_name(e, \"/dev/crypto engine\")\n+        || !ENGINE_set_cmd_defns(e, devcrypto_cmds)\n+        || !ENGINE_set_ctrl_function(e, devcrypto_ctrl)\n \n /*\n  * Asymmetric ciphers aren't well supported with /dev/crypto.  Among the BSD\n"
  },
  {
    "path": "package/libs/openssl/patches/420-eng_devcrypto-add-command-to-dump-driver-info.patch",
    "content": "From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001\nFrom: Eneas U de Queiroz <cote2004-github@yahoo.com>\nDate: Tue, 6 Nov 2018 22:54:07 -0200\nSubject: eng_devcrypto: add command to dump driver info\n\nThis is useful to determine the kernel driver running each algorithm.\n\nSigned-off-by: Eneas U de Queiroz <cote2004-github@yahoo.com>\n\nReviewed-by: Matthias St. Pierre <Matthias.St.Pierre@ncp-e.com>\nReviewed-by: Richard Levitte <levitte@openssl.org>\n(Merged from https://github.com/openssl/openssl/pull/7585)\n\ndiff --git a/crypto/engine/eng_devcrypto.c b/crypto/engine/eng_devcrypto.c\n--- a/crypto/engine/eng_devcrypto.c\n+++ b/crypto/engine/eng_devcrypto.c\n@@ -50,16 +50,20 @@ static int use_softdrivers = DEVCRYPTO_DEFAULT_USE_SOFDTRIVERS;\n  */\n struct driver_info_st {\n     enum devcrypto_status_t {\n-        DEVCRYPTO_STATUS_UNUSABLE       = -1, /* session open failed */\n-        DEVCRYPTO_STATUS_UNKNOWN        =  0, /* not tested yet */\n-        DEVCRYPTO_STATUS_USABLE         =  1  /* algo can be used */\n+        DEVCRYPTO_STATUS_FAILURE         = -3, /* unusable for other reason */\n+        DEVCRYPTO_STATUS_NO_CIOCCPHASH   = -2, /* hash state copy not supported */\n+        DEVCRYPTO_STATUS_NO_CIOCGSESSION = -1, /* session open failed */\n+        DEVCRYPTO_STATUS_UNKNOWN         =  0, /* not tested yet */\n+        DEVCRYPTO_STATUS_USABLE          =  1  /* algo can be used */\n     } status;\n \n     enum devcrypto_accelerated_t {\n-        DEVCRYPTO_NOT_ACCELERATED       = -1, /* software implemented */\n-        DEVCRYPTO_ACCELERATION_UNKNOWN  =  0, /* acceleration support unkown */\n-        DEVCRYPTO_ACCELERATED           =  1  /* hardware accelerated */\n+        DEVCRYPTO_NOT_ACCELERATED        = -1, /* software implemented */\n+        DEVCRYPTO_ACCELERATION_UNKNOWN   =  0, /* acceleration support unkown */\n+        DEVCRYPTO_ACCELERATED            =  1  /* hardware accelerated */\n     } accelerated;\n+\n+    char *driver_name;\n };\n \n static int clean_devcrypto_session(struct session_op *sess) {\n@@ -415,7 +419,7 @@ static void prepare_cipher_methods(void)\n         sess.cipher = cipher_data[i].devcryptoid;\n         sess.keylen = cipher_data[i].keylen;\n         if (ioctl(cfd, CIOCGSESSION, &sess) < 0) {\n-            cipher_driver_info[i].status = DEVCRYPTO_STATUS_UNUSABLE;\n+            cipher_driver_info[i].status = DEVCRYPTO_STATUS_NO_CIOCGSESSION;\n             continue;\n         }\n \n@@ -443,19 +447,24 @@ static void prepare_cipher_methods(void)\n                                             cipher_cleanup)\n             || !EVP_CIPHER_meth_set_impl_ctx_size(known_cipher_methods[i],\n                                                   sizeof(struct cipher_ctx))) {\n-            cipher_driver_info[i].status = DEVCRYPTO_STATUS_UNUSABLE;\n+            cipher_driver_info[i].status = DEVCRYPTO_STATUS_FAILURE;\n             EVP_CIPHER_meth_free(known_cipher_methods[i]);\n             known_cipher_methods[i] = NULL;\n         } else {\n             cipher_driver_info[i].status = DEVCRYPTO_STATUS_USABLE;\n #ifdef CIOCGSESSINFO\n             siop.ses = sess.ses;\n-            if (ioctl(cfd, CIOCGSESSINFO, &siop) < 0)\n+            if (ioctl(cfd, CIOCGSESSINFO, &siop) < 0) {\n                 cipher_driver_info[i].accelerated = DEVCRYPTO_ACCELERATION_UNKNOWN;\n-            else if (!(siop.flags & SIOP_FLAG_KERNEL_DRIVER_ONLY))\n-                cipher_driver_info[i].accelerated = DEVCRYPTO_NOT_ACCELERATED;\n-            else\n-                cipher_driver_info[i].accelerated = DEVCRYPTO_ACCELERATED;\n+            } else {\n+                cipher_driver_info[i].driver_name =\n+                    OPENSSL_strndup(siop.cipher_info.cra_driver_name,\n+                                    CRYPTODEV_MAX_ALG_NAME);\n+                if (!(siop.flags & SIOP_FLAG_KERNEL_DRIVER_ONLY))\n+                    cipher_driver_info[i].accelerated = DEVCRYPTO_NOT_ACCELERATED;\n+                else\n+                    cipher_driver_info[i].accelerated = DEVCRYPTO_ACCELERATED;\n+            }\n #endif /* CIOCGSESSINFO */\n         }\n         ioctl(cfd, CIOCFSESSION, &sess.ses);\n@@ -505,8 +514,11 @@ static void destroy_all_cipher_methods(void)\n {\n     size_t i;\n \n-    for (i = 0; i < OSSL_NELEM(cipher_data); i++)\n+    for (i = 0; i < OSSL_NELEM(cipher_data); i++) {\n         destroy_cipher_method(cipher_data[i].nid);\n+        OPENSSL_free(cipher_driver_info[i].driver_name);\n+        cipher_driver_info[i].driver_name = NULL;\n+    }\n }\n \n static int devcrypto_ciphers(ENGINE *e, const EVP_CIPHER **cipher,\n@@ -550,6 +562,40 @@ static int cryptodev_select_cipher_cb(const char *str, int len, void *usr)\n     return 1;\n }\n \n+static void dump_cipher_info(void)\n+{\n+    size_t i;\n+    const char *name;\n+\n+    fprintf (stderr, \"Information about ciphers supported by the /dev/crypto\"\n+             \" engine:\\n\");\n+#ifndef CIOCGSESSINFO\n+    fprintf(stderr, \"CIOCGSESSINFO (session info call) unavailable\\n\");\n+#endif\n+    for (i = 0; i < OSSL_NELEM(cipher_data); i++) {\n+        name = OBJ_nid2sn(cipher_data[i].nid);\n+        fprintf (stderr, \"Cipher %s, NID=%d, /dev/crypto info: id=%d, \",\n+                 name ? name : \"unknown\", cipher_data[i].nid,\n+                 cipher_data[i].devcryptoid);\n+        if (cipher_driver_info[i].status == DEVCRYPTO_STATUS_NO_CIOCGSESSION ) {\n+            fprintf (stderr, \"CIOCGSESSION (session open call) failed\\n\");\n+            continue;\n+        }\n+        fprintf (stderr, \"driver=%s \", cipher_driver_info[i].driver_name ?\n+                 cipher_driver_info[i].driver_name : \"unknown\");\n+        if (cipher_driver_info[i].accelerated == DEVCRYPTO_ACCELERATED)\n+            fprintf(stderr, \"(hw accelerated)\");\n+        else if (cipher_driver_info[i].accelerated == DEVCRYPTO_NOT_ACCELERATED)\n+            fprintf(stderr, \"(software)\");\n+        else\n+            fprintf(stderr, \"(acceleration status unknown)\");\n+        if (cipher_driver_info[i].status == DEVCRYPTO_STATUS_FAILURE)\n+            fprintf (stderr, \". Cipher setup failed\");\n+        fprintf(stderr, \"\\n\");\n+    }\n+    fprintf(stderr, \"\\n\");\n+}\n+\n /*\n  * We only support digests if the cryptodev implementation supports multiple\n  * data updates and session copying.  Otherwise, we would be forced to maintain\n@@ -812,31 +858,36 @@ static void prepare_digest_methods(void)\n         sess1.mac = digest_data[i].devcryptoid;\n         sess2.ses = 0;\n         if (ioctl(cfd, CIOCGSESSION, &sess1) < 0) {\n-            digest_driver_info[i].status = DEVCRYPTO_STATUS_UNUSABLE;\n+            digest_driver_info[i].status = DEVCRYPTO_STATUS_NO_CIOCGSESSION;\n             goto finish;\n         }\n \n #ifdef CIOCGSESSINFO\n         /* gather hardware acceleration info from the driver */\n         siop.ses = sess1.ses;\n-        if (ioctl(cfd, CIOCGSESSINFO, &siop) < 0)\n+        if (ioctl(cfd, CIOCGSESSINFO, &siop) < 0) {\n             digest_driver_info[i].accelerated = DEVCRYPTO_ACCELERATION_UNKNOWN;\n-        else if (siop.flags & SIOP_FLAG_KERNEL_DRIVER_ONLY)\n-            digest_driver_info[i].accelerated = DEVCRYPTO_ACCELERATED;\n-        else\n-            digest_driver_info[i].accelerated = DEVCRYPTO_NOT_ACCELERATED;\n+        } else {\n+            digest_driver_info[i].driver_name =\n+                OPENSSL_strndup(siop.hash_info.cra_driver_name,\n+                                CRYPTODEV_MAX_ALG_NAME);\n+            if (siop.flags & SIOP_FLAG_KERNEL_DRIVER_ONLY)\n+                digest_driver_info[i].accelerated = DEVCRYPTO_ACCELERATED;\n+            else\n+                digest_driver_info[i].accelerated = DEVCRYPTO_NOT_ACCELERATED;\n+        }\n #endif\n \n         /* digest must be capable of hash state copy */\n         sess2.mac = sess1.mac;\n         if (ioctl(cfd, CIOCGSESSION, &sess2) < 0) {\n-            digest_driver_info[i].status = DEVCRYPTO_STATUS_UNUSABLE;\n+            digest_driver_info[i].status = DEVCRYPTO_STATUS_FAILURE;\n             goto finish;\n         }\n         cphash.src_ses = sess1.ses;\n         cphash.dst_ses = sess2.ses;\n         if (ioctl(cfd, CIOCCPHASH, &cphash) < 0) {\n-            digest_driver_info[i].status = DEVCRYPTO_STATUS_UNUSABLE;\n+            digest_driver_info[i].status = DEVCRYPTO_STATUS_NO_CIOCCPHASH;\n             goto finish;\n         }\n         if ((known_digest_methods[i] = EVP_MD_meth_new(digest_data[i].nid,\n@@ -852,7 +903,7 @@ static void prepare_digest_methods(void)\n             || !EVP_MD_meth_set_cleanup(known_digest_methods[i], digest_cleanup)\n             || !EVP_MD_meth_set_app_datasize(known_digest_methods[i],\n                                              sizeof(struct digest_ctx))) {\n-            digest_driver_info[i].status = DEVCRYPTO_STATUS_UNUSABLE;\n+            digest_driver_info[i].status = DEVCRYPTO_STATUS_FAILURE;\n             EVP_MD_meth_free(known_digest_methods[i]);\n             known_digest_methods[i] = NULL;\n             goto finish;\n@@ -894,8 +945,11 @@ static void destroy_all_digest_methods(void)\n {\n     size_t i;\n \n-    for (i = 0; i < OSSL_NELEM(digest_data); i++)\n+    for (i = 0; i < OSSL_NELEM(digest_data); i++) {\n         destroy_digest_method(digest_data[i].nid);\n+        OPENSSL_free(digest_driver_info[i].driver_name);\n+        digest_driver_info[i].driver_name = NULL;\n+    }\n }\n \n static int devcrypto_digests(ENGINE *e, const EVP_MD **digest,\n@@ -939,6 +993,43 @@ static int cryptodev_select_digest_cb(const char *str, int len, void *usr)\n     return 1;\n }\n \n+static void dump_digest_info(void)\n+{\n+    size_t i;\n+    const char *name;\n+\n+    fprintf (stderr, \"Information about digests supported by the /dev/crypto\"\n+             \" engine:\\n\");\n+#ifndef CIOCGSESSINFO\n+    fprintf(stderr, \"CIOCGSESSINFO (session info call) unavailable\\n\");\n+#endif\n+\n+    for (i = 0; i < OSSL_NELEM(digest_data); i++) {\n+        name = OBJ_nid2sn(digest_data[i].nid);\n+        fprintf (stderr, \"Digest %s, NID=%d, /dev/crypto info: id=%d, driver=%s\",\n+                 name ? name : \"unknown\", digest_data[i].nid,\n+                 digest_data[i].devcryptoid,\n+                 digest_driver_info[i].driver_name ? digest_driver_info[i].driver_name : \"unknown\");\n+        if (digest_driver_info[i].status == DEVCRYPTO_STATUS_NO_CIOCGSESSION) {\n+            fprintf (stderr, \". CIOCGSESSION (session open) failed\\n\");\n+            continue;\n+        }\n+        if (digest_driver_info[i].accelerated == DEVCRYPTO_ACCELERATED)\n+            fprintf(stderr, \" (hw accelerated)\");\n+        else if (digest_driver_info[i].accelerated == DEVCRYPTO_NOT_ACCELERATED)\n+            fprintf(stderr, \" (software)\");\n+        else\n+            fprintf(stderr, \" (acceleration status unknown)\");\n+        if (cipher_driver_info[i].status == DEVCRYPTO_STATUS_FAILURE)\n+            fprintf (stderr, \". Cipher setup failed\\n\");\n+        else if (digest_driver_info[i].status == DEVCRYPTO_STATUS_NO_CIOCCPHASH)\n+            fprintf(stderr, \", CIOCCPHASH failed\\n\");\n+        else\n+            fprintf(stderr, \", CIOCCPHASH capable\\n\");\n+    }\n+    fprintf(stderr, \"\\n\");\n+}\n+\n #endif\n \n /******************************************************************************\n@@ -983,6 +1074,11 @@ static const ENGINE_CMD_DEFN devcrypto_cmds[] = {\n     ENGINE_CMD_FLAG_STRING},\n #endif\n \n+   {DEVCRYPTO_CMD_DUMP_INFO,\n+    \"DUMP_INFO\",\n+    \"dump info about each algorithm to stderr; use 'openssl engine -pre DUMP_INFO devcrypto'\",\n+    ENGINE_CMD_FLAG_NO_INPUT},\n+\n    {0, NULL, NULL, 0}\n };\n \n@@ -1051,6 +1147,13 @@ static int devcrypto_ctrl(ENGINE *e, int cmd, long i, void *p, void (*f) (void))\n         return 1;\n #endif /* IMPLEMENT_DIGEST */\n \n+    case DEVCRYPTO_CMD_DUMP_INFO:\n+        dump_cipher_info();\n+#ifdef IMPLEMENT_DIGEST\n+        dump_digest_info();\n+#endif\n+        return 1;\n+\n     default:\n         break;\n     }\n"
  },
  {
    "path": "package/libs/openssl/patches/430-e_devcrypto-make-the-dev-crypto-engine-dynamic.patch",
    "content": "From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001\nFrom: Eneas U de Queiroz <cote2004-github@yahoo.com>\nDate: Tue, 6 Nov 2018 10:57:03 -0200\nSubject: e_devcrypto: make the /dev/crypto engine dynamic\n\nEngine has been moved from crypto/engine/eng_devcrypto.c to\nengines/e_devcrypto.c.\n\nSigned-off-by: Eneas U de Queiroz <cote2004-github@yahoo.com>\n\ndiff --git a/crypto/engine/build.info b/crypto/engine/build.info\n--- a/crypto/engine/build.info\n+++ b/crypto/engine/build.info\n@@ -6,6 +6,3 @@ SOURCE[../../libcrypto]=\\\n         tb_cipher.c tb_digest.c tb_pkmeth.c tb_asnmth.c tb_eckey.c \\\n         eng_openssl.c eng_cnf.c eng_dyn.c \\\n         eng_rdrand.c\n-IF[{- !$disabled{devcryptoeng} -}]\n-  SOURCE[../../libcrypto]=eng_devcrypto.c\n-ENDIF\ndiff --git a/crypto/init.c b/crypto/init.c\n--- a/crypto/init.c\n+++ b/crypto/init.c\n@@ -328,18 +328,6 @@ DEFINE_RUN_ONCE_STATIC(ossl_init_engine_openssl)\n     engine_load_openssl_int();\n     return 1;\n }\n-# ifndef OPENSSL_NO_DEVCRYPTOENG\n-static CRYPTO_ONCE engine_devcrypto = CRYPTO_ONCE_STATIC_INIT;\n-DEFINE_RUN_ONCE_STATIC(ossl_init_engine_devcrypto)\n-{\n-#  ifdef OPENSSL_INIT_DEBUG\n-    fprintf(stderr, \"OPENSSL_INIT: ossl_init_engine_devcrypto: \"\n-                    \"engine_load_devcrypto_int()\\n\");\n-#  endif\n-    engine_load_devcrypto_int();\n-    return 1;\n-}\n-# endif\n \n # ifndef OPENSSL_NO_RDRAND\n static CRYPTO_ONCE engine_rdrand = CRYPTO_ONCE_STATIC_INIT;\n@@ -364,6 +352,18 @@ DEFINE_RUN_ONCE_STATIC(ossl_init_engine_dynamic)\n     return 1;\n }\n # ifndef OPENSSL_NO_STATIC_ENGINE\n+#  ifndef OPENSSL_NO_DEVCRYPTOENG\n+static CRYPTO_ONCE engine_devcrypto = CRYPTO_ONCE_STATIC_INIT;\n+DEFINE_RUN_ONCE_STATIC(ossl_init_engine_devcrypto)\n+{\n+#   ifdef OPENSSL_INIT_DEBUG\n+    fprintf(stderr, \"OPENSSL_INIT: ossl_init_engine_devcrypto: \"\n+                    \"engine_load_devcrypto_int()\\n\");\n+#   endif\n+    engine_load_devcrypto_int();\n+    return 1;\n+}\n+#  endif\n #  if !defined(OPENSSL_NO_HW) && !defined(OPENSSL_NO_HW_PADLOCK)\n static CRYPTO_ONCE engine_padlock = CRYPTO_ONCE_STATIC_INIT;\n DEFINE_RUN_ONCE_STATIC(ossl_init_engine_padlock)\n@@ -704,11 +704,6 @@ int OPENSSL_init_crypto(uint64_t opts, const OPENSSL_INIT_SETTINGS *settings)\n     if ((opts & OPENSSL_INIT_ENGINE_OPENSSL)\n             && !RUN_ONCE(&engine_openssl, ossl_init_engine_openssl))\n         return 0;\n-# if !defined(OPENSSL_NO_HW) && !defined(OPENSSL_NO_DEVCRYPTOENG)\n-    if ((opts & OPENSSL_INIT_ENGINE_CRYPTODEV)\n-            && !RUN_ONCE(&engine_devcrypto, ossl_init_engine_devcrypto))\n-        return 0;\n-# endif\n # ifndef OPENSSL_NO_RDRAND\n     if ((opts & OPENSSL_INIT_ENGINE_RDRAND)\n             && !RUN_ONCE(&engine_rdrand, ossl_init_engine_rdrand))\n@@ -718,6 +713,11 @@ int OPENSSL_init_crypto(uint64_t opts, const OPENSSL_INIT_SETTINGS *settings)\n             && !RUN_ONCE(&engine_dynamic, ossl_init_engine_dynamic))\n         return 0;\n # ifndef OPENSSL_NO_STATIC_ENGINE\n+#  ifndef OPENSSL_NO_DEVCRYPTOENG\n+    if ((opts & OPENSSL_INIT_ENGINE_CRYPTODEV)\n+            && !RUN_ONCE(&engine_devcrypto, ossl_init_engine_devcrypto))\n+        return 0;\n+#  endif\n #  if !defined(OPENSSL_NO_HW) && !defined(OPENSSL_NO_HW_PADLOCK)\n     if ((opts & OPENSSL_INIT_ENGINE_PADLOCK)\n             && !RUN_ONCE(&engine_padlock, ossl_init_engine_padlock))\ndiff --git a/engines/build.info b/engines/build.info\n--- a/engines/build.info\n+++ b/engines/build.info\n@@ -11,6 +11,9 @@ IF[{- !$disabled{\"engine\"} -}]\n     IF[{- !$disabled{afalgeng} -}]\n       SOURCE[../libcrypto]=e_afalg.c\n     ENDIF\n+    IF[{- !$disabled{\"devcryptoeng\"} -}]\n+      SOURCE[../libcrypto]=e_devcrypto.c\n+    ENDIF\n   ELSE\n     IF[{- !$disabled{hw} && !$disabled{'hw-padlock'} -}]\n       ENGINES=padlock\n@@ -30,6 +33,12 @@ IF[{- !$disabled{\"engine\"} -}]\n       DEPEND[afalg]=../libcrypto\n       INCLUDE[afalg]= ../include\n     ENDIF\n+    IF[{- !$disabled{\"devcryptoeng\"} -}]\n+      ENGINES=devcrypto\n+      SOURCE[devcrypto]=e_devcrypto.c\n+      DEPEND[devcrypto]=../libcrypto\n+      INCLUDE[devcrypto]=../include\n+    ENDIF\n \n     ENGINES_NO_INST=ossltest dasync\n     SOURCE[dasync]=e_dasync.c\ndiff --git a/crypto/engine/eng_devcrypto.c b/engines/e_devcrypto.c\nsimilarity index 95%\nrename from crypto/engine/eng_devcrypto.c\nrename to engines/e_devcrypto.c\n--- a/crypto/engine/eng_devcrypto.c\n+++ b/engines/e_devcrypto.c\n@@ -7,7 +7,7 @@\n  * https://www.openssl.org/source/license.html\n  */\n \n-#include \"e_os.h\"\n+#include \"../e_os.h\"\n #include <string.h>\n #include <sys/types.h>\n #include <sys/stat.h>\n@@ -31,18 +31,20 @@\n # define CHECK_BSD_STYLE_MACROS\n #endif\n \n+#define engine_devcrypto_id \"devcrypto\"\n+\n /*\n  * ONE global file descriptor for all sessions.  This allows operations\n  * such as digest session data copying (see digest_copy()), but is also\n  * saner...  why re-open /dev/crypto for every session?\n  */\n-static int cfd;\n+static int cfd = -1;\n #define DEVCRYPTO_REQUIRE_ACCELERATED 0 /* require confirmation of acceleration */\n #define DEVCRYPTO_USE_SOFTWARE        1 /* allow software drivers */\n #define DEVCRYPTO_REJECT_SOFTWARE     2 /* only disallow confirmed software drivers */\n \n-#define DEVCRYPTO_DEFAULT_USE_SOFDTRIVERS DEVCRYPTO_REJECT_SOFTWARE\n-static int use_softdrivers = DEVCRYPTO_DEFAULT_USE_SOFDTRIVERS;\n+#define DEVCRYPTO_DEFAULT_USE_SOFTDRIVERS DEVCRYPTO_REJECT_SOFTWARE\n+static int use_softdrivers = DEVCRYPTO_DEFAULT_USE_SOFTDRIVERS;\n \n /*\n  * cipher/digest status & acceleration definitions\n@@ -1058,7 +1060,7 @@ static const ENGINE_CMD_DEFN devcrypto_cmds[] = {\n         OPENSSL_MSTR(DEVCRYPTO_USE_SOFTWARE) \"=allow all drivers, \"\n         OPENSSL_MSTR(DEVCRYPTO_REJECT_SOFTWARE)\n         \"=use if acceleration can't be determined) [default=\"\n-        OPENSSL_MSTR(DEVCRYPTO_DEFAULT_USE_SOFDTRIVERS) \"]\",\n+        OPENSSL_MSTR(DEVCRYPTO_DEFAULT_USE_SOFTDRIVERS) \"]\",\n     ENGINE_CMD_FLAG_NUMERIC},\n #endif\n \n@@ -1166,32 +1168,22 @@ static int devcrypto_ctrl(ENGINE *e, int cmd, long i, void *p, void (*f) (void))\n  *\n  *****/\n \n-static int devcrypto_unload(ENGINE *e)\n-{\n-    destroy_all_cipher_methods();\n-#ifdef IMPLEMENT_DIGEST\n-    destroy_all_digest_methods();\n-#endif\n-\n-    close(cfd);\n-\n-    return 1;\n-}\n /*\n- * This engine is always built into libcrypto, so it doesn't offer any\n- * ability to be dynamically loadable.\n+ * Opens /dev/crypto\n  */\n-void engine_load_devcrypto_int()\n+static int open_devcrypto(void)\n {\n-    ENGINE *e = NULL;\n     int fd;\n \n+    if (cfd >= 0)\n+        return 1;\n+\n     if ((fd = open(\"/dev/crypto\", O_RDWR, 0)) < 0) {\n #ifndef ENGINE_DEVCRYPTO_DEBUG\n         if (errno != ENOENT)\n #endif\n             fprintf(stderr, \"Could not open /dev/crypto: %s\\n\", strerror(errno));\n-        return;\n+        return 0;\n     }\n \n #ifdef CRIOGET\n@@ -1199,35 +1191,61 @@ void engine_load_devcrypto_int()\n         fprintf(stderr, \"Could not create crypto fd: %s\\n\", strerror(errno));\n         close(fd);\n         cfd = -1;\n-        return;\n+        return 0;\n     }\n     close(fd);\n #else\n     cfd = fd;\n #endif\n \n-    if ((e = ENGINE_new()) == NULL\n-        || !ENGINE_set_destroy_function(e, devcrypto_unload)) {\n-        ENGINE_free(e);\n-        /*\n-         * We know that devcrypto_unload() won't be called when one of the\n-         * above two calls have failed, so we close cfd explicitly here to\n-         * avoid leaking resources.\n-         */\n-        close(cfd);\n-        return;\n+    return 1;\n+}\n+\n+static int close_devcrypto(void)\n+{\n+    int ret;\n+\n+    if (cfd < 0)\n+        return 1;\n+    ret = close(cfd);\n+    cfd = -1;\n+    if (ret != 0) {\n+        fprintf(stderr, \"Error closing /dev/crypto: %s\\n\", strerror(errno));\n+        return 0;\n     }\n+    return 1;\n+}\n \n-    prepare_cipher_methods();\n+static int devcrypto_unload(ENGINE *e)\n+{\n+    destroy_all_cipher_methods();\n #ifdef IMPLEMENT_DIGEST\n-    prepare_digest_methods();\n+    destroy_all_digest_methods();\n #endif\n \n-    if (!ENGINE_set_id(e, \"devcrypto\")\n+    close_devcrypto();\n+\n+    return 1;\n+}\n+\n+static int bind_devcrypto(ENGINE *e) {\n+\n+    if (!ENGINE_set_id(e, engine_devcrypto_id)\n         || !ENGINE_set_name(e, \"/dev/crypto engine\")\n+        || !ENGINE_set_destroy_function(e, devcrypto_unload)\n         || !ENGINE_set_cmd_defns(e, devcrypto_cmds)\n-        || !ENGINE_set_ctrl_function(e, devcrypto_ctrl)\n+        || !ENGINE_set_ctrl_function(e, devcrypto_ctrl))\n+        return 0;\n \n+    prepare_cipher_methods();\n+#ifdef IMPLEMENT_DIGEST\n+    prepare_digest_methods();\n+#endif\n+\n+    return (ENGINE_set_ciphers(e, devcrypto_ciphers)\n+#ifdef IMPLEMENT_DIGEST\n+        && ENGINE_set_digests(e, devcrypto_digests)\n+#endif\n /*\n  * Asymmetric ciphers aren't well supported with /dev/crypto.  Among the BSD\n  * implementations, it seems to only exist in FreeBSD, and regarding the\n@@ -1250,23 +1268,36 @@ void engine_load_devcrypto_int()\n  */\n #if 0\n # ifndef OPENSSL_NO_RSA\n-        || !ENGINE_set_RSA(e, devcrypto_rsa)\n+        && ENGINE_set_RSA(e, devcrypto_rsa)\n # endif\n # ifndef OPENSSL_NO_DSA\n-        || !ENGINE_set_DSA(e, devcrypto_dsa)\n+        && ENGINE_set_DSA(e, devcrypto_dsa)\n # endif\n # ifndef OPENSSL_NO_DH\n-        || !ENGINE_set_DH(e, devcrypto_dh)\n+        && ENGINE_set_DH(e, devcrypto_dh)\n # endif\n # ifndef OPENSSL_NO_EC\n-        || !ENGINE_set_EC(e, devcrypto_ec)\n+        && ENGINE_set_EC(e, devcrypto_ec)\n # endif\n #endif\n-        || !ENGINE_set_ciphers(e, devcrypto_ciphers)\n-#ifdef IMPLEMENT_DIGEST\n-        || !ENGINE_set_digests(e, devcrypto_digests)\n-#endif\n-        ) {\n+        );\n+}\n+\n+#ifdef OPENSSL_NO_DYNAMIC_ENGINE\n+/*\n+ * In case this engine is built into libcrypto, then it doesn't offer any\n+ * ability to be dynamically loadable.\n+ */\n+void engine_load_devcrypto_int(void)\n+{\n+    ENGINE *e = NULL;\n+\n+    if (!open_devcrypto())\n+        return;\n+\n+    if ((e = ENGINE_new()) == NULL\n+        || !bind_devcrypto(e)) {\n+        close_devcrypto();\n         ENGINE_free(e);\n         return;\n     }\n@@ -1275,3 +1306,22 @@ void engine_load_devcrypto_int()\n     ENGINE_free(e);          /* Loose our local reference */\n     ERR_clear_error();\n }\n+\n+#else\n+\n+static int bind_helper(ENGINE *e, const char *id)\n+{\n+    if ((id && (strcmp(id, engine_devcrypto_id) != 0))\n+        || !open_devcrypto())\n+        return 0;\n+    if (!bind_devcrypto(e)) {\n+        close_devcrypto();\n+        return 0;\n+    }\n+    return 1;\n+}\n+\n+IMPLEMENT_DYNAMIC_CHECK_FN()\n+IMPLEMENT_DYNAMIC_BIND_FN(bind_helper)\n+\n+#endif\n"
  },
  {
    "path": "package/libs/openssl/patches/500-e_devcrypto-default-to-not-use-digests-in-engine.patch",
    "content": "From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001\nFrom: Eneas U de Queiroz <cote2004-github@yahoo.com>\nDate: Mon, 11 Mar 2019 09:29:13 -0300\nSubject: e_devcrypto: default to not use digests in engine\n\nDigests are almost always slower when using /dev/crypto because of the\ncost of the context switches.  Only for large blocks it is worth it.\n\nAlso, when forking, the open context structures are duplicated, but the\ninternal kernel sessions are still shared between forks, which means an\nupdate/close operation in one fork affects all processes using that\nsession.\n\nThis affects digests, especially for HMAC, where the session with the\nkey hash is used as a source for subsequent operations.  At least one\npopular application does this across a fork.  Disabling digests by\ndefault will mitigate the problem, while still allowing the user to\nturn them on if it is safe and fast enough.\n\nSigned-off-by: Eneas U de Queiroz <cote2004-github@yahoo.com>\n\ndiff --git a/engines/e_devcrypto.c b/engines/e_devcrypto.c\n--- a/engines/e_devcrypto.c\n+++ b/engines/e_devcrypto.c\n@@ -852,7 +852,7 @@ static void prepare_digest_methods(void)\n     for (i = 0, known_digest_nids_amount = 0; i < OSSL_NELEM(digest_data);\n          i++) {\n \n-        selected_digests[i] = 1;\n+        selected_digests[i] = 0;\n \n         /*\n          * Check that the digest is usable\n@@ -1072,7 +1072,7 @@ static const ENGINE_CMD_DEFN devcrypto_cmds[] = {\n #ifdef IMPLEMENT_DIGEST\n    {DEVCRYPTO_CMD_DIGESTS,\n     \"DIGESTS\",\n-    \"either ALL, NONE, or a comma-separated list of digests to enable [default=ALL]\",\n+    \"either ALL, NONE, or a comma-separated list of digests to enable [default=NONE]\",\n     ENGINE_CMD_FLAG_STRING},\n #endif\n \n"
  },
  {
    "path": "package/libs/openssl/patches/510-e_devcrypto-ignore-error-when-closing-session.patch",
    "content": "From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001\nFrom: Eneas U de Queiroz <cote2004-github@yahoo.com>\nDate: Mon, 11 Mar 2019 10:15:14 -0300\nSubject: e_devcrypto: ignore error when closing session\n\nIn cipher_init, ignore an eventual error when closing the previous\nsession.  It may have been closed by another process after a fork.\n\nSigned-off-by: Eneas U de Queiroz <cote2004-github@yahoo.com>\n\ndiff --git a/engines/e_devcrypto.c b/engines/e_devcrypto.c\n--- a/engines/e_devcrypto.c\n+++ b/engines/e_devcrypto.c\n@@ -195,9 +195,8 @@ static int cipher_init(EVP_CIPHER_CTX *ctx, const unsigned char *key,\n         get_cipher_data(EVP_CIPHER_CTX_nid(ctx));\n \n     /* cleanup a previous session */\n-    if (cipher_ctx->sess.ses != 0 &&\n-        clean_devcrypto_session(&cipher_ctx->sess) == 0)\n-        return 0;\n+    if (cipher_ctx->sess.ses != 0)\n+        clean_devcrypto_session(&cipher_ctx->sess);\n \n     cipher_ctx->sess.cipher = cipher_d->devcryptoid;\n     cipher_ctx->sess.keylen = cipher_d->keylen;\n"
  },
  {
    "path": "package/libs/pcre/Config.in",
    "content": "config PCRE_JIT_ENABLED\n\tbool\n\tdepends on PACKAGE_libpcre && (arm || i386 || i686 || x86_64 || mips || mipsel || powerpc || sparc)\n\tdefault y if (arm || i686 || x86_64)\n\tprompt \"Enable JIT compiler support\"\n\thelp\n\t\tEnable JIT (Just-In-Time) compiler support.\n\n\t\tEnabling this option can give an about 10x performance increase on JIT operations. It can be desireable for e.g. high performance Apache mod_rewrite or HA-Proxy reqrep operations.\n\n\t\tHowever, JIT should _only_ be enabled on architectures that are supported. Enabling JIT on unsupported platforms will result in a compilation failure. A list of supported architectures can be found here: https://pcre.org/original/doc/html/pcrejit.html#SEC3 .\n"
  },
  {
    "path": "package/libs/pcre/Makefile",
    "content": "#\n# Copyright (C) 2006-2015 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=pcre\nPKG_VERSION:=8.45\nPKG_RELEASE:=$(AUTORELEASE)\n\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.bz2\nPKG_SOURCE_URL:=@SF/$(PKG_NAME)\nPKG_HASH:=4dae6fdcd2bb0bb6c37b5f97c33c2be954da743985369cddac3546e3218bffb8\n\nPKG_MAINTAINER:=Thomas Heil <heil@terminal-consulting.de>\nPKG_LICENSE:=BSD-3-Clause\nPKG_LICENSE_FILES:=LICENCE\nPKG_CPE_ID:=cpe:/a:pcre:pcre\n\nPKG_INSTALL:=1\nPKG_BUILD_PARALLEL:=1\n\nPKG_CONFIG_DEPENDS:=\\\n\tCONFIG_PACKAGE_libpcrecpp \\\n\tCONFIG_PCRE_JIT_ENABLED\n\ninclude $(INCLUDE_DIR)/package.mk\ninclude $(INCLUDE_DIR)/host-build.mk\n\ndefine Package/libpcre/default\n  SECTION:=libs\n  CATEGORY:=Libraries\n  URL:=https://www.pcre.org/\nendef\n\ndefine Package/libpcre/config\n  source \"$(SOURCE)/Config.in\"\nendef\n\ndefine Package/libpcre\n  $(call Package/libpcre/default)\n  TITLE:=A Perl Compatible Regular Expression library\nendef\n\ndefine Package/libpcre16\n  $(call Package/libpcre/default)\n  TITLE:=A Perl Compatible Regular Expression library (16bit support)\nendef\n\ndefine Package/libpcre32\n  $(call Package/libpcre/default)\n  TITLE:=A Perl Compatible Regular Expression library (32bit support)\nendef\n\ndefine Package/libpcrecpp\n  $(call Package/libpcre/default)\n  TITLE:=C++ wrapper for Perl Compatible Regular Expression library\n  DEPENDS:=+libpcre +libstdcpp\nendef\n\nHOST_CONFIGURE_ARGS += \\\n\t--disable-shared \\\n\t--enable-utf8 \\\n\t--enable-unicode-properties \\\n\t--enable-pcre16 \\\n\t--with-match-limit-recursion=16000 \\\n\t--enable-cpp \\\n\t--with-pic\n\nCONFIGURE_ARGS += \\\n\t--enable-utf8 \\\n\t--enable-unicode-properties \\\n\t--enable-pcre16 \\\n\t--enable-pcre32 \\\n\t$(if $(CONFIG_PCRE_JIT_ENABLED),--enable-jit,--disable-jit) \\\n\t--with-match-limit-recursion=16000 \\\n\t--$(if $(CONFIG_PACKAGE_libpcrecpp),en,dis)able-cpp \\\n\t--with-pic\n\nMAKE_FLAGS += \\\n\tCFLAGS=\"$(TARGET_CFLAGS)\"\n\ndefine Build/InstallDev\n\t$(INSTALL_DIR) $(1)/usr/bin\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/bin/pcre-config $(1)/usr/bin/\n\t$(SED) 's,^\\(prefix\\|exec_prefix\\)=.*,\\1=$(STAGING_DIR)/usr,g' $(1)/usr/bin/pcre-config\n\n\t$(INSTALL_DIR) $(2)/bin\n\t$(LN) $(STAGING_DIR)/usr/bin/pcre-config $(2)/bin\n\n\t$(INSTALL_DIR) $(1)/usr/include\n\t$(CP) $(PKG_INSTALL_DIR)/usr/include/pcre*.h $(1)/usr/include/\n\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/libpcre*.{a,so*} $(1)/usr/lib/\n\n\t$(INSTALL_DIR) $(1)/usr/lib/pkgconfig\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/pkgconfig/libpcre*.pc $(1)/usr/lib/pkgconfig/\nendef\n\ndefine Package/libpcre/install\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/libpcre{,posix}.so.* $(1)/usr/lib/\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/libpcre.so $(1)/usr/lib/\nendef\n\ndefine Package/libpcre16/install\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/libpcre16.so* $(1)/usr/lib/\nendef\n\ndefine Package/libpcre32/install\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/libpcre32.so* $(1)/usr/lib/\nendef\n\ndefine Package/libpcrecpp/install\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/libpcrecpp.so.* $(1)/usr/lib/\nendef\n\n$(eval $(call BuildPackage,libpcre))\n$(eval $(call BuildPackage,libpcre16))\n$(eval $(call BuildPackage,libpcre32))\n$(eval $(call BuildPackage,libpcrecpp))\n$(eval $(call HostBuild))\n"
  },
  {
    "path": "package/libs/popt/Makefile",
    "content": "#\n# Copyright (C) 2006-2010 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=popt\nPKG_VERSION:=1.16\nPKG_RELEASE:=2\n\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz\nPKG_SOURCE_URL:= \\\n\thttp://distfiles.gentoo.org/distfiles/ \\\n\thttp://distcache.freebsd.org/ports-distfiles/ \\\n\thttp://rpm5.org/files/popt/\nPKG_HASH:=e728ed296fe9f069a0e005003c3d6b2dde3d9cad453422a10d6558616d304cc8\nPKG_LICENSE:=MIT\n\nPKG_FIXUP:=autoreconf\nPKG_REMOVE_FILES:=autogen.sh aclocal.m4\n\nPKG_INSTALL:=1\nPKG_BUILD_PARALLEL:=1\n\ninclude $(INCLUDE_DIR)/package.mk\n\nTARGET_CFLAGS += $(FPIC)\n\ndefine Package/libpopt\n  SECTION:=libs\n  CATEGORY:=Libraries\n  TITLE:=A command line option parsing library\n  URL:=http://rpm5.org/files/popt/\n  ABI_VERSION:=0\nendef\n\nCONFIGURE_ARGS += --enable-shared --enable-static\n\ndefine Build/InstallDev\n\t$(INSTALL_DIR) $(1)/usr/include\n\t$(CP) $(PKG_INSTALL_DIR)/usr/include/popt.h $(1)/usr/include/\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/libpopt.{a,so*} $(1)/usr/lib/\n\t$(INSTALL_DIR) $(1)/usr/lib/pkgconfig\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/pkgconfig/popt.pc $(1)/usr/lib/pkgconfig/\nendef\n\ndefine Package/libpopt/install\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/libpopt.so.* $(1)/usr/lib/\nendef\n\n$(eval $(call BuildPackage,libpopt))\n\n"
  },
  {
    "path": "package/libs/readline/Makefile",
    "content": "#\n# Copyright (C) 2006-2014 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=readline\nPKG_VERSION:=8.1\nPKG_RELEASE:=1\n\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz\nPKG_SOURCE_URL:=@GNU/readline\nPKG_HASH:=f8ceb4ee131e3232226a17f51b164afc46cd0b9e6cef344be87c65962cb82b02\n\nPKG_LICENSE:=GPL-3.0-or-later\nPKG_LICENSE_FILES:=COPYING\nPKG_CPE_ID:=cpe:/a:gnu:readline\n\nPKG_BUILD_PARALLEL:=1\nPKG_INSTALL:=1\n\ninclude $(INCLUDE_DIR)/package.mk\ninclude $(INCLUDE_DIR)/host-build.mk\n\nHOST_BUILD_DEPENDS:=ncurses/host\n\ndefine Package/libreadline\n  SECTION:=libs\n  CATEGORY:=Libraries\n  TITLE:=Command lines edition library\n  DEPENDS:=+libncursesw\n  URL:=http://cnswww.cns.cwru.edu/php/chet/readline/rltop.html\n  ABI_VERSION:=8\nendef\n\ndefine Package/libreadline/description\n\tThe Readline library provides a set of functions for use by applications\n\tthat allow users to edit command lines as they are typed in. Both Emacs\n\tand vi editing modes are available. The Readline library includes\n\tadditional functions to maintain a list of previously-entered command\n\tlines, to recall and perhaps reedit those lines, and perform csh-like\n\thistory expansion on previous commands.\nendef\n\nHOST_CONFIGURE_ARGS += --disable-shared --with-pic\nCONFIGURE_ARGS += --with-curses --disable-install-examples\n\nCONFIGURE_VARS += \\\n\tbash_cv_wcwidth_broken=no \\\n\tbash_cv_func_sigsetjmp=yes \\\n\nTARGET_CFLAGS += $(FPIC)\nHOST_CFLAGS += $(FPIC)\n\ndefine Build/InstallDev\n\t$(INSTALL_DIR) $(1)/usr/include\n\t$(CP) $(PKG_INSTALL_DIR)/usr/include/readline $(1)/usr/include/\n\t$(INSTALL_DIR) $(1)/usr/lib/pkgconfig\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/lib{history,readline}.{a,so*} $(1)/usr/lib/\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/pkgconfig/readline.pc $(1)/usr/lib/pkgconfig/\nendef\n\ndefine Package/libreadline/install\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/lib{history,readline}.so.* $(1)/usr/lib/\nendef\n\n$(eval $(call HostBuild))\n$(eval $(call BuildPackage,libreadline))\n"
  },
  {
    "path": "package/libs/readline/patches/001-curses-link.patch",
    "content": "link readline directly to ncurses since it needs symbols from it\n\nupstream readline does this on purpose (no direct linking), but\nit doesn't make much sense in a Linux world\n\n--- a/support/shobj-conf\n+++ b/support/shobj-conf\n@@ -42,7 +42,7 @@ SHOBJ_XLDFLAGS=\n SHOBJ_LIBS=\n \n SHLIB_XLDFLAGS=\n-SHLIB_LIBS=\n+SHLIB_LIBS=-lncurses\n \n SHLIB_DOT='.'\n SHLIB_LIBPREF='lib'\n"
  },
  {
    "path": "package/libs/sysfsutils/Makefile",
    "content": "#\n# Copyright (C) 2006-2012 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=sysfsutils\nPKG_VERSION:=2.1.0\nPKG_RELEASE:=3\n\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz\nPKG_SOURCE_URL:=@SF/linux-diag\nPKG_HASH:=e865de2c1f559fff0d3fc936e660c0efaf7afe662064f2fb97ccad1ec28d208a\nPKG_MAINTAINER:=Jo-Philipp Wich <jo@mein.io>\n\nPKG_LICENSE:=LGPL-2.1\nPKG_LICENSE_FILES:=COPYING cmd/GPL lib/LGPL\n\nPKG_FIXUP:=autoreconf\n\nPKG_INSTALL:=1\n\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine Package/libsysfs\n  SECTION:=libs\n  CATEGORY:=Libraries\n  SUBMENU:=Filesystem\n  TITLE:=Sysfs library\n  URL:=http://linux-diag.sourceforge.net/Sysfsutils.html\n  ABI_VERSION:=2\nendef\n\ndefine Package/sysfsutils\n  SECTION:=utils\n  CATEGORY:=Utilities\n  SUBMENU:=Filesystem\n  DEPENDS:=+libsysfs\n  TITLE:=System Utilities Based on Sysfs\n  URL:=http://linux-diag.sourceforge.net/Sysfsutils.html\nendef\n\ndefine Package/libsysfs/description\nThe library's purpose is to provide a consistant and stable interface for\nquerying system device information exposed through sysfs.\nendef\n\ndefine Package/sysfsutils/description\nA utility built upon libsysfs that lists devices by bus, class, and topology.\nendef\n\ndefine Build/InstallDev\n\t$(INSTALL_DIR) $(1)/usr/include\n\t$(CP) $(PKG_INSTALL_DIR)/usr/include/sysfs $(1)/usr/include/\n\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/libsysfs.{a,so*,la} $(1)/usr/lib/\nendef\n\ndefine Package/libsysfs/install\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/libsysfs.so.* $(1)/usr/lib/\nendef\n\ndefine Package/sysfsutils/install\n\t$(INSTALL_DIR) $(1)/etc/init.d\n\t$(INSTALL_BIN) ./files/sysfsutils $(1)/etc/init.d/\n\n\t$(INSTALL_DATA) ./files/sysfs.conf $(1)/etc/\n\t$(INSTALL_DIR) $(1)/etc/sysfs.d\n\t$(INSTALL_DATA) ./files/local.conf $(1)/etc/sysfs.d/\n\n\t$(INSTALL_DIR) $(1)/usr/bin\n\t$(CP) $(PKG_INSTALL_DIR)/usr/bin/systool $(1)/usr/bin/\nendef\n\ndefine Package/sysfsutils/conffiles\n/etc/sysfs.conf\n/etc/sysfs.d/local.conf\nendef\n\n$(eval $(call BuildPackage,libsysfs))\n$(eval $(call BuildPackage,sysfsutils))\n"
  },
  {
    "path": "package/libs/sysfsutils/files/local.conf",
    "content": "# local sysctl settings can be stored in this directory\n"
  },
  {
    "path": "package/libs/sysfsutils/files/sysfs.conf",
    "content": "#\n# /etc/sysfs.conf - Configuration file for setting sysfs attributes.\n#\n# The sysfs mount directory is automatically prepended to the attribute paths.\n#\n# Syntax:\n# attribute = value\n# mode attribute = 0600 # (any valid argument for chmod)\n# owner attribute = root:wheel # (any valid argument for chown)\n#\n# Examples:\n#\n# Always use the powersave CPU frequency governor\n# devices/system/cpu/cpu0/cpufreq/scaling_governor = powersave\n#\n# Use userspace CPU frequency governor and set initial speed\n# devices/system/cpu/cpu0/cpufreq/scaling_governor = userspace\n# devices/system/cpu/cpu0/cpufreq/scaling_setspeed = 600000\n#\n# Set permissions of suspend control file\n# mode power/state = 0660\n# owner power/state = root:power\n"
  },
  {
    "path": "package/libs/sysfsutils/files/sysfsutils",
    "content": "#!/bin/sh /etc/rc.common\n# Copyright (C) 2017 Rodolfo Giometti <giometti@enneenne.com>\n#\n# Based on Debian's script /etc/init.d/sysfsutils by\n# Martin Pitt <mpitt@debian.org>\n\nload_conffile() {\n\tFILE=\"$1\"\n\tsed  's/#.*$//; /^[[:space:]]*$/d;\n\t  s/^[[:space:]]*\\([^=[:space:]]*\\)[[:space:]]*\\([^=[:space:]]*\\)[[:space:]]*=[[:space:]]*\\(.*\\)/\\1 \\2 \\3/' \\\n\t  $FILE | {\n\twhile read f1 f2 f3; do\n\t\tif [ \"$f1\" = \"mode\" -a -n \"$f2\" -a -n \"$f3\" ]; then\n\t\t\tif [ -f \"/sys/$f2\" ] || [ -d \"/sys/$f2\" ]; then\n\t\t\t\tchmod \"$f3\" \"/sys/$f2\"\n\t\t\telse\n\t\t\t\techo \"unknown attribute $f2\"\n\t\t\tfi\n\t\telif [ \"$f1\" = \"owner\" -a -n \"$f2\" -a -n \"$f3\" ]; then\n\t\t\tif [ -f \"/sys/$f2\" ]; then\n\t\t\t\tchown \"$f3\" \"/sys/$f2\"\n\t\t\telse\n\t\t\t\techo \"unknown attribute $f2\"\n\t\t\tfi\n\t\telif [ \"$f1\" -a -n \"$f2\" -a -z \"$f3\" ]; then\n\t\t\tif [ -f \"/sys/$f1\" ]; then\n\t\t\t\t# Some fields need a terminating newline, others\n\t\t\t\t# need the terminating newline to be absent :-(\n\t\t\t\techo -n \"$f2\" > \"/sys/$f1\" 2>/dev/null ||\n\t\t\t\t\techo \"$f2\" > \"/sys/$f1\"\n\t\t\telse\n\t\t\t\techo \"unknown attribute $f1\"\n\t\t\tfi\n\t\telse\n\t\t\techo \"syntax error in $CONFFILE: '$f1' '$f2' '$f3'\"\n\t\t\texit 1\n\t\tfi\n\tdone\n\t}\n}\n\nSTART=11\nstart() {\n\tfor file in /etc/sysfs.conf /etc/sysfs.d/*.conf; do\n\t\t[ -r \"$file\" ] || continue\n\t\tload_conffile \"$file\"\n\tdone\n}\n"
  },
  {
    "path": "package/libs/sysfsutils/patches/200-mnt_path_check.patch",
    "content": "--- a/lib/sysfs_utils.c\n+++ b/lib/sysfs_utils.c\n@@ -22,6 +22,7 @@\n  */\n #include \"libsysfs.h\"\n #include \"sysfs.h\"\n+#include <mntent.h>\n \n /**\n  * sysfs_remove_trailing_slash: Removes any trailing '/' in the given path\n@@ -53,6 +54,9 @@ int sysfs_get_mnt_path(char *mnt_path, s\n {\n \tstatic char sysfs_path[SYSFS_PATH_MAX] = \"\";\n \tconst char *sysfs_path_env;\n+\tFILE *mnt;\n+\tstruct mntent *mntent;\n+\tint ret;\n \n \tif (len == 0 || mnt_path == NULL)\n \t\treturn -1;\n@@ -64,12 +68,31 @@ int sysfs_get_mnt_path(char *mnt_path, s\n \t\tif (sysfs_path_env != NULL) {\n \t\t\tsafestrcpymax(mnt_path, sysfs_path_env, len);\n \t\t\tsysfs_remove_trailing_slash(mnt_path);\n-\t\t\treturn 0;\n+\t\t} else {\n+\t\t\tsafestrcpymax(mnt_path, SYSFS_MNT_PATH, len);\n \t\t}\n-\t\tsafestrcpymax(mnt_path, SYSFS_MNT_PATH, len);\n \t}\n \n-\treturn 0;\n+\t/* check that mount point is indeed mounted */\n+\tret = -1;\n+\tif ((mnt = setmntent(SYSFS_PROC_MNTS, \"r\")) == NULL) {\n+\t\tdprintf(\"Error getting mount information\\n\");\n+\t\treturn -1;\n+\t}\n+\twhile ((mntent = getmntent(mnt)) != NULL) {\n+\t\tif (strcmp(mntent->mnt_type, SYSFS_FSTYPE_NAME) == 0 &&\n+\t\t\tstrcmp(mntent->mnt_dir, mnt_path) == 0) {\n+\t\t\tret = 0;\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\t\n+\tendmntent(mnt);\n+\n+\tif (ret < 0)\n+\t\terrno = ENOENT;\n+\n+\treturn ret;\n }\n \n /**\n"
  },
  {
    "path": "package/libs/toolchain/Makefile",
    "content": "#\n# Copyright (C) 2007-2014 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\nPKG_NAME:=toolchain\nPKG_RELEASE:=4\n\nPKG_MAINTAINER:=Felix Fietkau <nbd@nbd.name>\nPKG_LICENSE:=GPL-3.0-with-GCC-exception\n\nPKG_FLAGS:=hold essential nonshared\n\ninclude $(INCLUDE_DIR)/package.mk\n\nifneq ($(DUMP),1)\n  LIBGCC_VERSION:=$(GCC_VERSION)\nelse\n  LIBC_VERSION:=<LIBC_VERSION>\n  LIBGCC_VERSION:=<LIBGCC_VERSION>\nendif\n\ndefine Package/gcc/Default\n  SECTION:=libs\n  CATEGORY:=Base system\n  URL:=http://gcc.gnu.org/\n  VERSION:=$(LIBGCC_VERSION)-$(PKG_RELEASE)\nendef\n\ndefine Package/libgcc\n$(call Package/gcc/Default)\n  TITLE:=GCC support library\n  ABI_VERSION:=1\nendef\n\ndefine Package/libgcc/config\n\tmenu \"Configuration\"\n\t\tdepends on EXTERNAL_TOOLCHAIN && PACKAGE_libgcc\n\n\tconfig LIBGCC_ROOT_DIR\n\t\tstring\n\t\tprompt \"libgcc shared library base directory\"\n\t\tdepends on EXTERNAL_TOOLCHAIN && PACKAGE_libgcc\n\t\tdefault TOOLCHAIN_ROOT  if !NATIVE_TOOLCHAIN\n\t\tdefault \"/\"  if NATIVE_TOOLCHAIN\n\n\tconfig LIBGCC_FILE_SPEC\n\t\tstring\n\t\tprompt \"libgcc shared library files (use wildcards)\"\n\t\tdepends on EXTERNAL_TOOLCHAIN && PACKAGE_libgcc\n\t\tdefault \"./lib/libgcc_s.so.*\"\n\n\tendmenu\nendef\n\ndefine Package/libatomic\n$(call Package/gcc/Default)\n  DEPENDS:=+libgcc\n  TITLE:=Atomic support library\n  ABI_VERSION:=1\nendef\n\ndefine Package/libatomic/config\n\tmenu \"Configuration\"\n\t\tdepends on EXTERNAL_TOOLCHAIN && PACKAGE_libatomic\n\n\tconfig LIBATOMIC_ROOT_DIR\n\t\tstring\n\t\tprompt \"libatomic shared library base directory\"\n\t\tdepends on EXTERNAL_TOOLCHAIN && PACKAGE_libatomic\n\t\tdefault TOOLCHAIN_ROOT  if !NATIVE_TOOLCHAIN\n\t\tdefault \"/\"  if NATIVE_TOOLCHAIN\n\n\tconfig LIBATOMIC_FILE_SPEC\n\t\tstring\n\t\tprompt \"libatomic shared library files (use wildcards)\"\n\t\tdepends on EXTERNAL_TOOLCHAIN && PACKAGE_libatomic\n\t\tdefault \"./lib/libatomic.so.*\"\n\n\tendmenu\nendef\n\ndefine Package/libstdcpp\n$(call Package/gcc/Default)\n  NAME:=libstdc++\n  TITLE:=GNU Standard C++ Library v3\n  ABI_VERSION:=6\nendef\n\ndefine Package/libstdcpp/config\n\tmenu \"Configuration\"\n\tdepends on EXTERNAL_TOOLCHAIN && PACKAGE_libstdcpp\n\n\tconfig LIBSTDCPP_ROOT_DIR\n\t\tstring\n\t\tprompt \"libstdcpp shared library base directory\"\n\t\tdepends on EXTERNAL_TOOLCHAIN && PACKAGE_libstdcpp\n\t\tdefault TOOLCHAIN_ROOT  if !NATIVE_TOOLCHAIN\n\t\tdefault \"/\"  if NATIVE_TOOLCHAIN\n\n\tconfig LIBSTDCPP_FILE_SPEC\n\t\tstring\n\t\tprompt \"libstdc++ shared library files (use wildcards)\"\n\t\tdepends on EXTERNAL_TOOLCHAIN && PACKAGE_libstdcpp\n\t\tdefault \"./lib/libstdc++.so.*\"\n\n\tendmenu\nendef\n\n\ndefine Package/libasan\n$(call Package/gcc/Default)\n  NAME:=libasan\n  TITLE:=Runtime library for AddressSanitizer in GCC\n  DEPENDS:=@USE_GLIBC +librt +libstdcpp @!mips64 @!mips64el @!arc\n  ABI_VERSION:=5\nendef\n\ndefine Package/libasan/config\n\tmenu \"Configuration\"\n\tdepends on EXTERNAL_TOOLCHAIN && PACKAGE_libasan\n\n\tconfig LIBASAN_ROOT_DIR\n\t\tstring\n\t\tprompt \"libasan shared library base directory\"\n\t\tdepends on EXTERNAL_TOOLCHAIN && PACKAGE_libasan\n\t\tdefault TOOLCHAIN_ROOT  if !NATIVE_TOOLCHAIN\n\t\tdefault \"/\"  if NATIVE_TOOLCHAIN\n\n\tconfig LIBASAN_FILE_SPEC\n\t\tstring\n\t\tprompt \"libasan shared library files (use wildcards)\"\n\t\tdepends on EXTERNAL_TOOLCHAIN && PACKAGE_libasan\n\t\tdefault \"./lib/libasan.so.*\"\n\n\tendmenu\nendef\n\n\ndefine Package/libtsan\n$(call Package/gcc/Default)\n  NAME:=libtsan\n  TITLE:=Runtime library for ThreadSanitizer in GCC\n  DEPENDS:=@USE_GLIBC +librt +libstdcpp @!mips @!mipsel @!mips64 @!mips64el @!arc\n  ABI_VERSION:=0\nendef\n\ndefine Package/libtsan/config\n\tmenu \"Configuration\"\n\tdepends on EXTERNAL_TOOLCHAIN && PACKAGE_libtsan\n\n\tconfig LIBTSAN_ROOT_DIR\n\t\tstring\n\t\tprompt \"libtsan shared library base directory\"\n\t\tdepends on EXTERNAL_TOOLCHAIN && PACKAGE_libtsan\n\t\tdefault TOOLCHAIN_ROOT  if !NATIVE_TOOLCHAIN\n\t\tdefault \"/\"  if NATIVE_TOOLCHAIN\n\n\tconfig LIBTSAN_FILE_SPEC\n\t\tstring\n\t\tprompt \"libtsan shared library files (use wildcards)\"\n\t\tdepends on EXTERNAL_TOOLCHAIN && PACKAGE_libtsan\n\t\tdefault \"./lib/libtsan.so.*\"\n\n\tendmenu\nendef\n\n\ndefine Package/liblsan\n$(call Package/gcc/Default)\n  NAME:=liblsan\n  TITLE:=Runtime library for LeakSanitizer in GCC\n  DEPENDS:=@USE_GLIBC +librt +libstdcpp @!mips @!mipsel @!mips64 @!mips64el @!arc\n  ABI_VERSION:=0\nendef\n\ndefine Package/liblsan/config\n\tmenu \"Configuration\"\n\tdepends on EXTERNAL_TOOLCHAIN && PACKAGE_liblsan\n\n\tconfig LIBLSAN_ROOT_DIR\n\t\tstring\n\t\tprompt \"liblsan shared library base directory\"\n\t\tdepends on EXTERNAL_TOOLCHAIN && PACKAGE_liblsan\n\t\tdefault TOOLCHAIN_ROOT  if !NATIVE_TOOLCHAIN\n\t\tdefault \"/\"  if NATIVE_TOOLCHAIN\n\n\tconfig LIBLSAN_FILE_SPEC\n\t\tstring\n\t\tprompt \"liblsan shared library files (use wildcards)\"\n\t\tdepends on EXTERNAL_TOOLCHAIN && PACKAGE_liblsan\n\t\tdefault \"./lib/liblsan.so.*\"\n\n\tendmenu\nendef\n\n\ndefine Package/libubsan\n$(call Package/gcc/Default)\n  NAME:=libubsan\n  TITLE:=Runtime library for UndefinedBehaviorSanitizer in GCC\n  DEPENDS:=@USE_GLIBC +librt +libstdcpp @!mips64 @!mips64el @!arc\n  ABI_VERSION:=1\nendef\n\ndefine Package/libubsan/config\n\tmenu \"Configuration\"\n\tdepends on EXTERNAL_TOOLCHAIN && PACKAGE_libubsan\n\n\tconfig LIBUBSAN_ROOT_DIR\n\t\tstring\n\t\tprompt \"libubsan shared library base directory\"\n\t\tdepends on EXTERNAL_TOOLCHAIN && PACKAGE_libubsan\n\t\tdefault TOOLCHAIN_ROOT  if !NATIVE_TOOLCHAIN\n\t\tdefault \"/\"  if NATIVE_TOOLCHAIN\n\n\tconfig LIBUBSAN_FILE_SPEC\n\t\tstring\n\t\tprompt \"libubsan shared library files (use wildcards)\"\n\t\tdepends on EXTERNAL_TOOLCHAIN && PACKAGE_libubsan\n\t\tdefault \"./lib/libubsan.so.*\"\n\n\tendmenu\nendef\n\n\ndefine Package/libc/Default\n  SECTION:=libs\n  CATEGORY:=Base system\n  VERSION:=$(LIBC_VERSION)-$(PKG_RELEASE)\n  DEPENDS:=+libgcc\n  URL:=$(LIBC_URL)\nendef\n\n\ndefine Package/libc\n$(call Package/libc/Default)\n  TITLE:=C library\nendef\n\ndefine Package/libc/config\n\tmenu \"Configuration\"\n\tdepends on EXTERNAL_TOOLCHAIN && PACKAGE_libc\n\n\tconfig LIBC_ROOT_DIR\n\t\tstring\n\t\tprompt \"libc shared library base directory\"\n\t\tdepends on EXTERNAL_TOOLCHAIN && PACKAGE_libc\n\t\tdefault TOOLCHAIN_ROOT  if !NATIVE_TOOLCHAIN\n\t\tdefault \"/\"  if NATIVE_TOOLCHAIN\n\n\tconfig LIBC_FILE_SPEC\n\t\tstring\n\t\tprompt \"libc shared library files (use wildcards)\"\n\t\tdepends on EXTERNAL_TOOLCHAIN && PACKAGE_libc\n\t\tdefault \"./lib/ld{*.so*,-linux*.so.*} ./lib/lib{anl,c,cidn,crypt,dl,m,nsl,nss_dns,nss_files,resolv,util}{-*.so,.so.*,.so}\"\n\n\tendmenu\nendef\n\n\ndefine Package/libpthread\n$(call Package/libc/Default)\n  TITLE:=POSIX thread library\nendef\n\ndefine Package/libpthread/config\n\tmenu \"Configuration\"\n\tdepends on EXTERNAL_TOOLCHAIN && PACKAGE_libpthread\n\n\tconfig LIBPTHREAD_ROOT_DIR\n\t\tstring\n\t\tprompt \"libpthread shared library base directory\"\n\t\tdepends on EXTERNAL_TOOLCHAIN && PACKAGE_libpthread\n\t\tdefault TOOLCHAIN_ROOT  if !NATIVE_TOOLCHAIN\n\t\tdefault \"/\"  if NATIVE_TOOLCHAIN\n\n\tconfig LIBPTHREAD_FILE_SPEC\n\t\tstring\n\t\tprompt \"libpthread shared library files (use wildcards)\"\n\t\tdepends on EXTERNAL_TOOLCHAIN && PACKAGE_libpthread\n\t\tdefault \"./lib/libpthread{-*.so,.so.*}\"\n\n\tendmenu\nendef\n\n\ndefine Package/libthread-db\n$(call Package/libc/Default)\n  DEPENDS:=@!USE_MUSL\n  TITLE:=POSIX thread library debugging support\nendef\n\ndefine Package/libthread-db/config\n\tmenu \"Configuration\"\n\tdepends on EXTERNAL_TOOLCHAIN && PACKAGE_libthread-db\n\n\tconfig LIBTHREAD_DB_ROOT_DIR\n\t\tstring\n\t\tprompt \"POSIX thread debugging shared library base directory\"\n\t\tdepends on EXTERNAL_TOOLCHAIN && PACKAGE_libthread-db\n\t\tdefault TOOLCHAIN_ROOT  if !NATIVE_TOOLCHAIN\n\t\tdefault \"/\"  if NATIVE_TOOLCHAIN\n\n\tconfig LIBTHREAD_DB_FILE_SPEC\n\t\tstring\n\t\tprompt \"POSIX thread debugging shared library files (use wildcards)\"\n\t\tdepends on EXTERNAL_TOOLCHAIN && PACKAGE_libthread-db\n\t\tdefault \"./lib/libthread_db{-*.so,.so.*}\"\n\n\tendmenu\nendef\n\ndefine Package/librt\n$(call Package/libc/Default)\n  TITLE:=POSIX.1b RealTime extension library\n  DEPENDS:=+libpthread\nendef\n\ndefine Package/librt/config\n\tmenu \"Configuration\"\n\tdepends on EXTERNAL_TOOLCHAIN && PACKAGE_librt\n\n\tconfig LIBRT_ROOT_DIR\n\t\tstring\n\t\tprompt \"librt shared library base directory\"\n\t\tdepends on EXTERNAL_TOOLCHAIN && PACKAGE_librt\n\t\tdefault TOOLCHAIN_ROOT  if !NATIVE_TOOLCHAIN\n\t\tdefault \"/\"  if NATIVE_TOOLCHAIN\n\n\tconfig LIBRT_FILE_SPEC\n\t\tstring\n\t\tprompt \"librt shared library files (use wildcards)\"\n\t\tdepends on EXTERNAL_TOOLCHAIN && PACKAGE_librt\n\t\tdefault \"./lib/librt{-*.so,.so.*}\"\n\n\tendmenu\nendef\n\n\ndefine Package/libgfortran\n$(call Package/gcc/Default)\n  TITLE:=GFortran support library\n  DEPENDS+=@INSTALL_GFORTRAN\nendef\n\ndefine Package/libgfortran/config\n\tmenu \"Configuration\"\n\t\tdepends on EXTERNAL_TOOLCHAIN && PACKAGE_libgfortran\n\n\tconfig LIBGFORTRAN_ROOT_DIR\n\t\tstring\n\t\tprompt \"libgfortran shared library base directory\"\n\t\tdepends on EXTERNAL_TOOLCHAIN && PACKAGE_libgfortran\n\t\tdefault TOOLCHAIN_ROOT  if !NATIVE_TOOLCHAIN\n\t\tdefault \"/\"  if NATIVE_TOOLCHAIN\n\n\tconfig LIBGFORTRAN_FILE_SPEC\n\t\tstring\n\t\tprompt \"libgfortran shared library files (use wildcards)\"\n\t\tdepends on EXTERNAL_TOOLCHAIN && PACKAGE_libgfortran\n\t\tdefault \"./usr/lib/libgfortran.so.*\"\n\n\tendmenu\nendef\n\ndefine Package/libgomp\n$(call Package/gcc/Default)\n  TITLE:=OpenMP support library\nendef\n\ndefine Package/libgomp/config\n\tmenu \"Configuration\"\n\t\tdepends on EXTERNAL_TOOLCHAIN && PACKAGE_libgomp\n\n\tconfig LIBGOMP_ROOT_DIR\n\t\tstring\n\t\tprompt \"libgomp shared library base directory\"\n\t\tdepends on EXTERNAL_TOOLCHAIN && PACKAGE_libgomp\n\t\tdefault TOOLCHAIN_ROOT  if !NATIVE_TOOLCHAIN\n\t\tdefault \"/\"  if NATIVE_TOOLCHAIN\n\n\tconfig LIBGOMP_FILE_SPEC\n\t\tstring\n\t\tprompt \"libgomp shared library files (use wildcards)\"\n\t\tdepends on EXTERNAL_TOOLCHAIN && PACKAGE_libgomp\n\t\tdefault \"./lib/libgomp.so*\"\n\n\tendmenu\nendef\n\n\ndefine Package/ldd\n$(call Package/libc/Default)\n  DEPENDS:=@!USE_MUSL\n  SECTION:=utils\n  CATEGORY:=Utilities\n  TITLE:=LDD trace utility\nendef\n\ndefine Package/ldd/config\n\tmenu \"Configuration\"\n\t\tdepends on EXTERNAL_TOOLCHAIN && PACKAGE_ldd\n\n\tconfig LDD_ROOT_DIR\n\t\tstring\n\t\tprompt \"ldd trace utility base directory\"\n\t\tdepends on EXTERNAL_TOOLCHAIN && PACKAGE_ldd\n\t\tdefault TOOLCHAIN_ROOT  if !NATIVE_TOOLCHAIN\n\t\tdefault \"/\"  if NATIVE_TOOLCHAIN\n\n\tconfig LDD_FILE_SPEC\n\t\tstring\n\t\tprompt \"ldd trace utility file\"\n\t\tdepends on EXTERNAL_TOOLCHAIN && PACKAGE_ldd\n\t\tdefault \"./usr/bin/ldd\"\n\n\tendmenu\nendef\n\n\ndefine Package/ldconfig\n$(call Package/libc/Default)\n  DEPENDS:=@!USE_MUSL\n  SECTION:=utils\n  CATEGORY:=Utilities\n  TITLE:=Shared library path configuration\nendef\n\ndefine Package/ldconfig/config\n\tmenu \"Configuration\"\n\t\tdepends on EXTERNAL_TOOLCHAIN && PACKAGE_ldconfig\n\n\tconfig LDCONFIG_ROOT_DIR\n\t\tstring\n\t\tprompt \"ldconfig base directory\"\n\t\tdepends on EXTERNAL_TOOLCHAIN && PACKAGE_ldconfig\n\t\tdefault TOOLCHAIN_ROOT  if !NATIVE_TOOLCHAIN\n\t\tdefault \"/\"  if NATIVE_TOOLCHAIN\n\n\tconfig LDCONFIG_FILE_SPEC\n\t\tstring\n\t\tprompt \"ldconfig file\"\n\t\tdepends on EXTERNAL_TOOLCHAIN && PACKAGE_ldconfig\n\t\tdefault \"./sbin/ldconfig\"\n\n\tendmenu\nendef\n\ndefine Build/Prepare\n\tmkdir -p $(PKG_BUILD_DIR)\nendef\n\nLIBGCC_A=$(lastword $(wildcard $(TOOLCHAIN_DIR)/lib/gcc/*/*/libgcc_pic.a))\nLIBGCC_MAP=$(lastword $(wildcard $(TOOLCHAIN_DIR)/lib/gcc/*/*/libgcc.map))\nLIBGCC_SO=$(lastword $(wildcard $(TOOLCHAIN_DIR)/lib/libgcc_s.so.*))\n\nifneq ($(LIBGCC_SO),)\n    define Build/Compile/libgcc\n\t$(CP) $(LIBGCC_SO) $(PKG_BUILD_DIR)/\n    endef\nendif\n\ndefine Build/Compile/Default\n\t$(call Build/Compile/libgcc)\n\t$(call Build/Compile/$(LIBC))\nendef\nBuild/Compile = $(Build/Compile/Default)\n\nifeq ($(CONFIG_EXTERNAL_TOOLCHAIN),)\n\n  define Package/libgcc/install\n\t$(INSTALL_DIR) $(1)/lib\n\t$(CP) $(TOOLCHAIN_DIR)/lib/libgcc_s.so.* $(1)/lib/\n  endef\n\n  define Package/libatomic/install\n\t$(INSTALL_DIR) $(1)/lib\n\t$(CP) $(TOOLCHAIN_DIR)/lib/libatomic.so.* $(1)/lib/\n  endef\n\n  define Package/libgfortran/install\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(CP) $(TOOLCHAIN_DIR)/lib/libgfortran.so.* $(1)/usr/lib/\n  endef\n\n  define Package/libstdcpp/install\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(CP) $(TOOLCHAIN_DIR)/lib/libstdc++.so.* $(1)/usr/lib/\n\trm -rf $(1)/usr/lib/*-gdb.py\n  endef\n\n  define Package/libasan/install\n\t$(INSTALL_DIR) $(1)/lib\n\t$(CP) $(TOOLCHAIN_DIR)/lib/libasan.so.* $(1)/lib/\n  endef\n\n  define Package/libtsan/install\n\t$(INSTALL_DIR) $(1)/lib\n\t$(CP) $(TOOLCHAIN_DIR)/lib/libtsan.so.* $(1)/lib/\n  endef\n\n  define Package/liblsan/install\n\t$(INSTALL_DIR) $(1)/lib\n\t$(CP) $(TOOLCHAIN_DIR)/lib/liblsan.so.* $(1)/lib/\n  endef\n\n  define Package/libubsan/install\n\t$(INSTALL_DIR) $(1)/lib\n\t$(CP) $(TOOLCHAIN_DIR)/lib/libubsan.so.* $(1)/lib/\n  endef\n\n  define Package/glibc/install\n\t$(CP) ./glibc-files/* $(1)/\n\trm -f $(1)/etc/localtime\n\t$(LN) /tmp/localtime $(1)/etc/localtime\n\t$(INSTALL_DIR) $(1)/lib\n\t$(CP) \\\n\t\t$(TOOLCHAIN_DIR)/lib/ld*.so.* \\\n\t\t$(1)/lib/\n\tfor file in libanl libc libcidn libcrypt libdl libm libnsl libnss_dns libnss_files libresolv libutil; do \\\n\t\tfor file in $(TOOLCHAIN_DIR)/lib/$$$$file.so.*; do \\\n\t\t\tif [ -e \"$$$$file\" ]; then \\\n\t\t\t\t$(CP) $$$$file $(1)/lib/; \\\n\t\t\tfi; \\\n\t\tdone; \\\n\tdone\n  endef\n\n  LD_MUSL_NAME = $(notdir $(firstword $(wildcard $(TOOLCHAIN_DIR)/lib/libc.so*)))\n\n  define Package/musl/install\n\t$(INSTALL_DIR) $(1)/lib $(1)/usr/bin\n\t$(CP) \\\n\t\t$(TOOLCHAIN_DIR)/lib/ld-musl-*.so* \\\n\t\t$(1)/lib/\n\t$(CP) \\\n\t\t$(TOOLCHAIN_DIR)/lib/libc.so* \\\n\t\t$(1)/lib/\n\t$(LN) ../../lib/$(LD_MUSL_NAME) $(1)/usr/bin/ldd\n  endef\n\n  define Package/libc/install\n    $(call Package/$(LIBC)/install,$1)\n  endef\n\n  define Package/libc/install_lib\n\t$(CP) $(filter-out %/libdl_pic.a %/libpthread_pic.a %/libresolv_pic.a,$(wildcard $(TOOLCHAIN_DIR)/lib/lib*.a)) $(1)/lib/\n\t$(if $(wildcard $(TOOLCHAIN_DIR)/lib/libc_so.a),$(CP) $(TOOLCHAIN_DIR)/lib/libc_so.a $(1)/lib/libc_pic.a)\n\t$(if $(LIBGCC_MAP), \\\n\t\t$(CP) $(LIBGCC_A) $(1)/lib/libgcc_s_pic.a; \\\n\t\t$(CP) $(LIBGCC_MAP) $(1)/lib/libgcc_s_pic.map \\\n\t)\n  endef\n\n  define Package/libpthread/install\n\t$(INSTALL_DIR) $(1)/lib\n  ifneq ($(CONFIG_USE_MUSL),y)\n\t$(CP) \\\n\t\t$(TOOLCHAIN_DIR)/lib/libpthread.so.* \\\n\t\t$(1)/lib/\n  endif\n  endef\n\n  define Package/libthread-db/install\n\t$(INSTALL_DIR) $(1)/lib\n\t$(CP) \\\n\t\t$(TOOLCHAIN_DIR)/lib/libthread_db.so.* $(1)/lib\n  endef\n\n  define Package/libpthread/install_lib\n\t$(if $(wildcard $(TOOLCHAIN_DIR)/lib/libpthread_so.a),$(CP) $(TOOLCHAIN_DIR)/lib/libpthread_so.a $(1)/lib/libpthread_pic.a)\n  endef\n\n  define Package/librt/install\n\t$(INSTALL_DIR) $(1)/lib\n  ifneq ($(CONFIG_USE_MUSL),y)\n\t$(CP) \\\n\t\t$(TOOLCHAIN_DIR)/lib/librt.so.* \\\n\t\t$(1)/lib/\n  endif\n  endef\n\n  define Package/ldd/install\n\t$(INSTALL_DIR) $(1)/usr/bin/\n\t$(CP) $(TOOLCHAIN_DIR)/bin/ldd $(1)/usr/bin/\n\tsed -i 's,^#!.*,#!/bin/sh,' $(1)/usr/bin/ldd\n  endef\n\n  define Package/ldconfig/install\n\t$(INSTALL_DIR) $(1)/sbin/\n\t$(CP) $(TOOLCHAIN_DIR)/sbin/ldconfig $(1)/sbin/\n  endef\n\nelse\n\n  define Package/libgcc/install\n\tfor file in $(call qstrip,$(CONFIG_LIBGCC_FILE_SPEC)); do \\\n\t\t$(INSTALL_DIR) $(1)/lib ; \\\n\t\t$(CP) $(call qstrip,$(CONFIG_LIBGCC_ROOT_DIR))/$$$$file $(1)/lib/ ; \\\n\tdone ; \\\n\texit 0\n  endef\n\n  define Package/libgfortran/install\n\tfor file in $(call qstrip,$(CONFIG_LIBGFORTRAN_FILE_SPEC)); do \\\n\t\t$(INSTALL_DIR) $(1)/lib ; \\\n\t\t$(CP) $(call qstrip,$(CONFIG_LIBGFORTRAN_ROOT_DIR))/$$$$file $(1)/lib/ ; \\\n\tdone\n  endef\n\n  define Package/libstdcpp/install\n\tfor file in $(call qstrip,$(CONFIG_LIBSTDCPP_FILE_SPEC)); do \\\n\t\t$(INSTALL_DIR) $(1)/lib ; \\\n\t\t$(CP) $(call qstrip,$(CONFIG_LIBSTDCPP_ROOT_DIR))/$$$$file $(1)/lib/ ; \\\n\tdone ; \\\n\texit 0\n  endef\n\n  define Package/libasan/install\n\tfor file in $(call qstrip,$(CONFIG_LIBASAN_FILE_SPEC)); do \\\n\t\t$(INSTALL_DIR) $(1)/lib ; \\\n\t\t$(CP) $(call qstrip,$(CONFIG_LIBASAN_ROOT_DIR))/$$$$file $(1)/lib/ ; \\\n\tdone ; \\\n\texit 0\n  endef\n\n  define Package/libtsan/install\n\tfor file in $(call qstrip,$(CONFIG_LIBTSAN_FILE_SPEC)); do \\\n\t\t$(INSTALL_DIR) $(1)/lib ; \\\n\t\t$(CP) $(call qstrip,$(CONFIG_LIBTSAN_ROOT_DIR))/$$$$file $(1)/lib/ ; \\\n\tdone ; \\\n\texit 0\n  endef\n\n  define Package/liblsan/install\n\tfor file in $(call qstrip,$(CONFIG_LIBLSAN_FILE_SPEC)); do \\\n\t\t$(INSTALL_DIR) $(1)/lib ; \\\n\t\t$(CP) $(call qstrip,$(CONFIG_LIBLSAN_ROOT_DIR))/$$$$file $(1)/lib/ ; \\\n\tdone ; \\\n\texit 0\n  endef\n\n  define Package/libubsan/install\n\tfor file in $(call qstrip,$(CONFIG_LIBUBSAN_FILE_SPEC)); do \\\n\t\t$(INSTALL_DIR) $(1)/lib ; \\\n\t\t$(CP) $(call qstrip,$(CONFIG_LIBUBSAN_ROOT_DIR))/$$$$file $(1)/lib/ ; \\\n\tdone ; \\\n\texit 0\n  endef\n\n  define Package/libc/install\n\tfor file in $(call qstrip,$(CONFIG_LIBC_FILE_SPEC)); do \\\n\t\t$(INSTALL_DIR) $(1)/lib ; \\\n\t\t$(CP) $(call qstrip,$(CONFIG_LIBC_ROOT_DIR))/$$$$file $(1)/lib/ ; \\\n\tdone ; \\\n\texit 0\n  endef\n\n  define Package/libpthread/install\n\tfor file in $(call qstrip,$(CONFIG_LIBPTHREAD_FILE_SPEC)); do \\\n\t\t$(INSTALL_DIR) $(1)/lib ; \\\n\t\t$(CP) $(call qstrip,$(CONFIG_LIBPTHREAD_ROOT_DIR))/$$$$file $(1)/lib/ ; \\\n\tdone ; \\\n\texit 0\n  endef\n\n  define Package/libthread-db/install\n\tfor file in $(call qstrip,$(CONFIG_LIBTHREAD_DB_FILE_SPEC)); do \\\n\t\t$(INSTALL_DIR) $(1)/lib ; \\\n\t\t$(CP) $(call qstrip,$(CONFIG_LIBTHREAD_DB_ROOT_DIR))/$$$$file $(1)/lib/ ; \\\n\tdone ; \\\n\texit 0\n  endef\n\n  define Package/librt/install\n\tfor file in $(call qstrip,$(CONFIG_LIBRT_FILE_SPEC)); do \\\n\t\t$(INSTALL_DIR) $(1)/lib ; \\\n\t\t$(CP) $(call qstrip,$(CONFIG_LIBRT_ROOT_DIR))/$$$$file $(1)/lib/ ; \\\n\tdone ; \\\n\texit 0\n  endef\n\n  define Package/libatomic/install\n\tfor file in $(call qstrip,$(CONFIG_LIBATOMIC_FILE_SPEC)); do \\\n\t\t$(INSTALL_DIR) $(1)/lib ; \\\n\t\t$(CP) $(call qstrip,$(CONFIG_LIBATOMIC_ROOT_DIR))/$$$$file $(1)/lib/ ; \\\n\tdone ; \\\n\texit 0\n  endef\n\n  define Package/libgomp/install\n\tfor file in $(call qstrip,$(CONFIG_LIBGOMP_FILE_SPEC)); do \\\n\t\t$(INSTALL_DIR) $(1)/lib ; \\\n\t\t$(CP) $(call qstrip,$(CONFIG_LIBGOMP_ROOT_DIR))/$$$$file $(1)/lib/ ; \\\n\tdone ; \\\n\texit 0\n  endef\n\n  define Package/ldd/install\n\tfor file in $(call qstrip,$(CONFIG_LDD_FILE_SPEC)); do \\\n\t\tdir=`dirname $$$$file` ; \\\n\t\t$(INSTALL_DIR) $(1)/$$$$dir ; \\\n\t\t$(CP) $(call qstrip,$(CONFIG_LDD_ROOT_DIR))/$$$$file $(1)/$$$$dir/ ; \\\n\tdone ; \\\n\texit 0\n  endef\n\n  define Package/ldconfig/install\n\tfor file in $(call qstrip,$(CONFIG_LDCONFIG_FILE_SPEC)); do \\\n\t\tdir=`dirname $$$$file` ; \\\n\t\t$(INSTALL_DIR) $(1)/$$$$dir ; \\\n\t\t$(CP) $(call qstrip,$(CONFIG_LDCONFIG_ROOT_DIR))/$$$$file $(1)/$$$$dir/ ; \\\n\tdone ; \\\n\texit 0\n  endef\n\nendif\n\n$(eval $(call BuildPackage,libc))\n$(eval $(call BuildPackage,libgcc))\n$(eval $(call BuildPackage,libatomic))\n$(eval $(call BuildPackage,libstdcpp))\n$(eval $(call BuildPackage,libasan))\n$(eval $(call BuildPackage,libtsan))\n$(eval $(call BuildPackage,liblsan))\n$(eval $(call BuildPackage,libubsan))\n$(eval $(call BuildPackage,libpthread))\n$(eval $(call BuildPackage,libthread-db))\n$(eval $(call BuildPackage,librt))\n$(eval $(call BuildPackage,libgfortran))\n$(eval $(call BuildPackage,libgomp))\n$(eval $(call BuildPackage,ldd))\n$(eval $(call BuildPackage,ldconfig))\n"
  },
  {
    "path": "package/libs/toolchain/glibc-files/etc/nsswitch.conf",
    "content": "passwd:files\nshadow:files\ngroup:files\nhosts:dns files\nbootparams:files\nethers:files\nnetmasks:files\nnetworks:files\nprotocols:files\nrpc:files\nservices:files\nautomount:files\naliases:files\n"
  },
  {
    "path": "package/libs/uclient/Makefile",
    "content": "include $(TOPDIR)/rules.mk\n\nPKG_NAME:=uclient\nPKG_RELEASE=1\n\nPKG_SOURCE_PROTO:=git\nPKG_SOURCE_URL=$(PROJECT_GIT)/project/uclient.git\nPKG_MIRROR_HASH:=7c443cac02a734dd312c65618f4de17248d188317f30a9fac192c1503b3d5c05\nPKG_SOURCE_DATE:=2021-05-14\nPKG_SOURCE_VERSION:=6a6011df3429ffa5958d12b1327eeda4fd9daa47\nCMAKE_INSTALL:=1\n\nPKG_BUILD_DEPENDS:=ustream-ssl\n\nPKG_LICENSE:=ISC\nPKG_LICENSE_FILES:=\n\nPKG_MAINTAINER:=Felix Fietkau <nbd@nbd.name>\n\ninclude $(INCLUDE_DIR)/package.mk\ninclude $(INCLUDE_DIR)/cmake.mk\n\ndefine Package/libuclient\n  SECTION:=libs\n  CATEGORY:=Libraries\n  TITLE:=HTTP/1.1 client library\n  ABI_VERSION:=20201210\n  DEPENDS:=+libubox\nendef\n\ndefine Package/uclient-fetch\n  SECTION:=net\n  CATEGORY:=Network\n  TITLE:=Tiny wget replacement using libuclient\n  ALTERNATIVES:=200:/usr/bin/wget:/bin/uclient-fetch\n  PROVIDES:=wget\n  DEPENDS:=+libuclient\nendef\n\ndefine Package/libuclient/install\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(INSTALL_DATA) $(PKG_INSTALL_DIR)/usr/lib/libuclient.so $(1)/usr/lib/\nendef\n\ndefine Package/uclient-fetch/install\n\t$(INSTALL_DIR) $(1)/bin\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/bin/uclient-fetch $(1)/bin/\nendef\n\n$(eval $(call BuildPackage,libuclient))\n$(eval $(call BuildPackage,uclient-fetch))\n"
  },
  {
    "path": "package/libs/ustream-ssl/Makefile",
    "content": "include $(TOPDIR)/rules.mk\n\nPKG_NAME:=ustream-ssl\nPKG_RELEASE:=1\n\nPKG_SOURCE_PROTO:=git\nPKG_SOURCE_URL=$(PROJECT_GIT)/project/ustream-ssl.git\nPKG_SOURCE_DATE:=2022-01-16\nPKG_SOURCE_VERSION:=868fd8812f477c110f9c6c5252c0bd172167b94c\nPKG_MIRROR_HASH:=dd28d5e846b391917cf83d66176653bdfa4e8a0d5b11144b65a012fe7693ddeb\nCMAKE_INSTALL:=1\n\nPKG_LICENSE:=ISC\nPKG_LICENSE_FILES:=\n\nPKG_MAINTAINER:=Felix Fietkau <nbd@nbd.name>\n\ninclude $(INCLUDE_DIR)/package.mk\ninclude $(INCLUDE_DIR)/cmake.mk\n\ndefine Package/libustream/default\n  SECTION:=libs\n  CATEGORY:=Libraries\n  TITLE:=ustream SSL Library\n  DEPENDS:=+libubox\n  ABI_VERSION:=20201210\nendef\n\ndefine Package/libustream-openssl\n  $(Package/libustream/default)\n  TITLE += (openssl)\n  DEPENDS += +PACKAGE_libustream-openssl:libopenssl\n  VARIANT:=openssl\nendef\n\ndefine Package/libustream-wolfssl\n  $(Package/libustream/default)\n  TITLE += (wolfssl)\n  DEPENDS += +PACKAGE_libustream-wolfssl:libwolfssl\n  CONFLICTS := libustream-openssl\n  VARIANT:=wolfssl\nendef\n\ndefine Package/libustream-mbedtls\n  $(Package/libustream/default)\n  TITLE += (mbedtls)\n  DEPENDS += +libmbedtls\n  CONFLICTS := libustream-openssl libustream-wolfssl\n  VARIANT:=mbedtls\n  DEFAULT_VARIANT:=1\nendef\n\nifeq ($(BUILD_VARIANT),wolfssl)\n  TARGET_CFLAGS += -I$(STAGING_DIR)/usr/include/wolfssl\n  CMAKE_OPTIONS += -DWOLFSSL=on\nendif\nifeq ($(BUILD_VARIANT),mbedtls)\n  CMAKE_OPTIONS += -DMBEDTLS=on\nendif\n\ndefine Package/libustream/default/install\n\t$(INSTALL_DIR) $(1)/lib/\n\t$(INSTALL_DATA) $(PKG_INSTALL_DIR)/usr/lib/libustream-ssl.so $(1)/lib/\nendef\n\nPackage/libustream-openssl/install = $(Package/libustream/default/install)\nPackage/libustream-wolfssl/install = $(Package/libustream/default/install)\nPackage/libustream-mbedtls/install = $(Package/libustream/default/install)\n\n$(eval $(call BuildPackage,libustream-mbedtls))\n$(eval $(call BuildPackage,libustream-wolfssl))\n$(eval $(call BuildPackage,libustream-openssl))\n"
  },
  {
    "path": "package/libs/wolfssl/Config.in",
    "content": "if PACKAGE_libwolfssl\n\nconfig WOLFSSL_HAS_AES_CCM\n\tbool \"Include AES-CCM support\"\n\tdefault y\n\nconfig WOLFSSL_HAS_CHACHA_POLY\n\tbool \"Include ChaCha20-Poly1305 cipher suite support\"\n\tdefault y\n\nconfig WOLFSSL_HAS_DH\n\tbool \"Include DH (Diffie-Hellman) support\"\n\tdefault y\n\nconfig WOLFSSL_HAS_ARC4\n\tbool \"Include ARC4 support\"\n\tdefault y\n\nconfig WOLFSSL_HAS_CERTGEN\n\tbool \"Include certificate generation support\"\n\tdefault y\n\nconfig WOLFSSL_HAS_TLSV10\n\tbool \"Include TLS 1.0 support\"\n\tdefault y\n\nconfig WOLFSSL_HAS_TLSV13\n\tbool \"Include TLS 1.3 support\"\n\tdefault y\n\nconfig WOLFSSL_HAS_SESSION_TICKET\n\tbool \"Include session ticket support\"\n\tdefault y\n\nconfig WOLFSSL_HAS_DTLS\n\tbool \"Include DTLS support\"\n\tdefault n\n\nconfig WOLFSSL_HAS_OCSP\n\tbool \"Include OSCP stapling support\"\n\tdefault y\n\nconfig WOLFSSL_HAS_WPAS\n\tbool \"Include wpa_supplicant support\"\n\tselect WOLFSSL_HAS_ARC4\n\tselect WOLFSSL_HAS_OCSP\n\tselect WOLFSSL_HAS_SESSION_TICKET\n\tdefault y\n\nconfig WOLFSSL_HAS_ECC25519\n\tbool \"Include ECC Curve 25519 support\"\n\tdefault y\n\nconfig WOLFSSL_HAS_OPENVPN\n\tbool \"Include OpenVPN support\"\n\tdefault n\n\nconfig WOLFSSL_ALT_NAMES\n\tbool \"Include SAN (Subject Alternative Name) support\"\n\tdefault y\n\nconfig WOLFSSL_HAS_DEVCRYPTO\n\tbool\n\nchoice\n\tprompt \"Hardware Acceleration\"\n\tdefault WOLFSSL_HAS_NO_HW\n\n\tconfig WOLFSSL_HAS_NO_HW\n\t\tbool \"None\"\n\n\tconfig WOLFSSL_HAS_AFALG\n\t\tbool \"AF_ALG\"\n\n\tconfig WOLFSSL_HAS_DEVCRYPTO_CBC\n\t\tbool \"/dev/crytpo - AES-CBC-only\"\n\t\tselect WOLFSSL_HAS_DEVCRYPTO\n\n\tconfig WOLFSSL_HAS_DEVCRYPTO_AES\n\t\tbool \"/dev/crypto - AES-only (all supported modes)\"\n\t\tselect WOLFSSL_HAS_DEVCRYPTO\n\n\tconfig WOLFSSL_HAS_DEVCRYPTO_FULL\n\t\tbool \"/dev/crypto - full\"\n\t\tselect WOLFSSL_HAS_DEVCRYPTO\nendchoice\n\nendif\n"
  },
  {
    "path": "package/libs/wolfssl/Makefile",
    "content": "#\n# Copyright (C) 2006-2017 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=wolfssl\nPKG_VERSION:=5.2.0-stable\nPKG_RELEASE:=$(AUTORELEASE)\n\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz\nPKG_SOURCE_URL:=https://github.com/wolfSSL/wolfssl/archive/v$(PKG_VERSION)\nPKG_HASH:=409b4646c5f54f642de0e9f3544c3b83de7238134f5b1ff93fb44527bf119d05\n\nPKG_FIXUP:=libtool libtool-abiver\nPKG_INSTALL:=1\nPKG_USE_MIPS16:=0\nPKG_BUILD_PARALLEL:=1\nPKG_LICENSE:=GPL-2.0-or-later\nPKG_LICENSE_FILES:=LICENSING COPYING\nPKG_MAINTAINER:=Eneas U de Queiroz <cotequeiroz@gmail.com>\nPKG_CPE_ID:=cpe:/a:wolfssl:wolfssl\n\nPKG_CONFIG_DEPENDS:=\\\n\tCONFIG_WOLFSSL_HAS_AES_CCM CONFIG_WOLFSSL_HAS_AFALG \\\n\tCONFIG_WOLFSSL_HAS_ARC4 CONFIG_WOLFSSL_HAS_CHACHA_POLY \\\n\tCONFIG_WOLFSSL_HAS_DEVCRYPTO_AES CONFIG_WOLFSSL_HAS_DEVCRYPTO_FULL \\\n\tCONFIG_WOLFSSL_HAS_DH CONFIG_WOLFSSL_HAS_DTLS \\\n\tCONFIG_WOLFSSL_HAS_ECC25519 CONFIG_WOLFSSL_HAS_OCSP \\\n\tCONFIG_WOLFSSL_HAS_SESSION_TICKET CONFIG_WOLFSSL_HAS_TLSV10 \\\n\tCONFIG_WOLFSSL_HAS_TLSV13 CONFIG_WOLFSSL_HAS_WPAS CONFIG_WOLFSSL_HAS_CERTGEN \\\n\tCONFIG_WOLFSSL_HAS_OPENVPN CONFIG_WOLFSSL_ALT_NAMES\n\nPKG_ABI_VERSION=$(patsubst %-stable,%,$(PKG_VERSION)).$(call version_abbrev,$(call confvar,$(PKG_CONFIG_DEPENDS)))\n\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine Package/libwolfssl\n  SECTION:=libs\n  SUBMENU:=SSL\n  CATEGORY:=Libraries\n  TITLE:=wolfSSL library\n  URL:=http://www.wolfssl.com/\n  MENU:=1\n  PROVIDES:=libcyassl\n  DEPENDS:=+WOLFSSL_HAS_DEVCRYPTO:kmod-cryptodev +WOLFSSL_HAS_AFALG:kmod-crypto-user\n  ABI_VERSION:=$(PKG_ABI_VERSION)\nendef\n\ndefine Package/libwolfssl/description\nwolfSSL (formerly CyaSSL) is an SSL library optimized for small\nfootprint, both on disk and for memory use.\nendef\n\ndefine Package/libwolfssl/config\n\tsource \"$(SOURCE)/Config.in\"\nendef\n\nTARGET_CFLAGS += \\\n\t$(FPIC) \\\n\t-fomit-frame-pointer \\\n\t-flto \\\n\t-DFP_MAX_BITS=8192 \\\n\t$(if $(CONFIG_WOLFSSL_ALT_NAMES),-DWOLFSSL_ALT_NAMES)\n\nTARGET_LDFLAGS += -flto\n\n# --enable-stunnel needed for OpenSSL API compatibility bits\nCONFIGURE_ARGS += \\\n\t--enable-reproducible-build \\\n\t--enable-lighty \\\n\t--enable-opensslall \\\n\t--enable-opensslextra \\\n\t--enable-sni \\\n\t--enable-stunnel \\\n\t--enable-altcertchains \\\n\t--disable-crypttests \\\n\t--disable-examples \\\n\t--disable-jobserver \\\n\t--$(if $(CONFIG_IPV6),enable,disable)-ipv6 \\\n\t--$(if $(CONFIG_WOLFSSL_HAS_AES_CCM),enable,disable)-aesccm \\\n\t--$(if $(CONFIG_WOLFSSL_HAS_CERTGEN),enable,disable)-certgen \\\n\t--$(if $(CONFIG_WOLFSSL_HAS_CHACHA_POLY),enable,disable)-chacha \\\n\t--$(if $(CONFIG_WOLFSSL_HAS_CHACHA_POLY),enable,disable)-poly1305 \\\n\t--$(if $(CONFIG_WOLFSSL_HAS_DH),enable,disable)-dh \\\n\t--$(if $(CONFIG_WOLFSSL_HAS_ARC4),enable,disable)-arc4 \\\n\t--$(if $(CONFIG_WOLFSSL_HAS_TLSV10),enable,disable)-tlsv10 \\\n\t--$(if $(CONFIG_WOLFSSL_HAS_TLSV13),enable,disable)-tls13 \\\n\t--$(if $(CONFIG_WOLFSSL_HAS_SESSION_TICKET),enable,disable)-session-ticket \\\n\t--$(if $(CONFIG_WOLFSSL_HAS_DTLS),enable,disable)-dtls \\\n\t--$(if $(CONFIG_WOLFSSL_HAS_ECC25519),enable,disable)-curve25519 \\\n\t--$(if $(CONFIG_WOLFSSL_HAS_AFALG),enable,disable)-afalg \\\n\t--$(if $(CONFIG_WOLFSSL_HAS_OPENVPN),enable,disable)-openvpn \\\n\t--enable-devcrypto=$(if $(CONFIG_WOLFSSL_HAS_DEVCRYPTO_CBC),cbc\\\n\t\t\t  ,$(if $(CONFIG_WOLFSSL_HAS_DEVCRYPTO_AES),aes\\\n\t\t\t  ,$(if $(CONFIG_WOLFSSL_HAS_DEVCRYPTO_FULL),yes,no)))\n\nifeq ($(CONFIG_WOLFSSL_HAS_OCSP),y)\nCONFIGURE_ARGS += \\\n\t--enable-ocsp --enable-ocspstapling --enable-ocspstapling2\nendif\n\nifeq ($(CONFIG_WOLFSSL_HAS_WPAS),y)\nCONFIGURE_ARGS += \\\n\t--enable-wpas --enable-fortress --enable-fastmath\nendif\n\ndefine Build/InstallDev\n\t$(INSTALL_DIR) $(1)/usr/include $(1)/usr/lib/pkgconfig\n\t$(CP) $(PKG_INSTALL_DIR)/usr/include/* $(1)/usr/include/\n\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/libwolfssl.{so*,la} $(1)/usr/lib/\n\tln -s libwolfssl.so $(1)/usr/lib/libcyassl.so\n\tln -s libwolfssl.la $(1)/usr/lib/libcyassl.la\n\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/pkgconfig/*.pc $(1)/usr/lib/pkgconfig\nendef\n\ndefine Package/libwolfssl/install\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/libwolfssl.so.* $(1)/usr/lib/\nendef\n\n$(eval $(call BuildPackage,libwolfssl))\n"
  },
  {
    "path": "package/libs/wolfssl/patches/100-disable-hardening-check.patch",
    "content": "--- a/wolfssl/wolfcrypt/settings.h\n+++ b/wolfssl/wolfcrypt/settings.h\n@@ -2338,7 +2338,7 @@ extern void uITRON4_free(void *p) ;\n #endif\n \n /* warning for not using harden build options (default with ./configure) */\n-#ifndef WC_NO_HARDEN\n+#if 0\n     #if (defined(USE_FAST_MATH) && !defined(TFM_TIMING_RESISTANT)) || \\\n         (defined(HAVE_ECC) && !defined(ECC_TIMING_RESISTANT)) || \\\n         (!defined(NO_RSA) && !defined(WC_RSA_BLINDING) && !defined(HAVE_FIPS) && \\\n"
  },
  {
    "path": "package/libs/wolfssl/patches/200-ecc-rng.patch",
    "content": "Since commit 6467de5a8840 (\"Randomize z ordinates in scalar\nmult when timing resistant\") wolfssl requires a RNG for an EC\nkey when the hardened built option is selected.\n\nwc_ecc_set_rng is only available when built hardened, so there\nis no safe way to install the RNG to the key regardless whether\nor not wolfssl is compiled hardened.\n\nAlways export wc_ecc_set_rng so tools such as hostapd can install\nRNG regardless of the built settings for wolfssl.\n\n--- a/wolfcrypt/src/ecc.c\n+++ b/wolfcrypt/src/ecc.c\n@@ -11655,21 +11655,21 @@ void wc_ecc_fp_free(void)\n \n #endif /* FP_ECC */\n \n-#ifdef ECC_TIMING_RESISTANT\n int wc_ecc_set_rng(ecc_key* key, WC_RNG* rng)\n {\n     int err = 0;\n \n+#ifdef ECC_TIMING_RESISTANT\n     if (key == NULL) {\n         err = BAD_FUNC_ARG;\n     }\n     else {\n         key->rng = rng;\n     }\n+#endif\n \n     return err;\n }\n-#endif\n \n #ifdef HAVE_ECC_ENCRYPT\n \n--- a/wolfssl/wolfcrypt/ecc.h\n+++ b/wolfssl/wolfcrypt/ecc.h\n@@ -650,10 +650,8 @@ WOLFSSL_API\n void wc_ecc_fp_free(void);\n WOLFSSL_LOCAL\n void wc_ecc_fp_init(void);\n-#ifdef ECC_TIMING_RESISTANT\n WOLFSSL_API\n int wc_ecc_set_rng(ecc_key* key, WC_RNG* rng);\n-#endif\n \n WOLFSSL_API\n int wc_ecc_set_curve(ecc_key* key, int keysize, int curve_id);\n"
  },
  {
    "path": "package/libs/wolfssl/patches/300-fix-SSL_get_verify_result-regression.patch",
    "content": "From 87e43dd63ba429297e439f2dfd1ee8b45981e18b Mon Sep 17 00:00:00 2001\nFrom: Juliusz Sosinowicz <juliusz@wolfssl.com>\nDate: Sat, 12 Feb 2022 00:34:24 +0100\nSubject: [PATCH] Reported in ZD13631\n\n`ssl->peerVerifyRet` wasn't being cleared when retrying with an alternative cert chain\n\nReferences: https://github.com/wolfSSL/wolfssl/issues/4879\n---\n src/internal.c | 3 +++\n 1 file changed, 3 insertions(+)\n\n--- a/src/internal.c\n+++ b/src/internal.c\n@@ -12342,6 +12342,9 @@ int ProcessPeerCerts(WOLFSSL* ssl, byte*\n                             }\n \n                             ret = 0; /* clear errors and continue */\n+                    #if defined(OPENSSL_EXTRA) || defined(OPENSSL_EXTRA_X509_SMALL)\n+                            ssl->peerVerifyRet = 0;\n+                    #endif\n                             args->verifyErr = 0;\n                         }\n \n"
  },
  {
    "path": "package/libs/wolfssl/patches/400-wolfcrypt-src-port-devcrypto-devcrypto_aes.c-remove-.patch",
    "content": "From 096889927d9528d4fbeb3aab56d1fe8225d2e7ec Mon Sep 17 00:00:00 2001\nFrom: Daniel Pouzzner <douzzer@wolfssl.com>\nDate: Thu, 14 Apr 2022 20:23:31 -0500\nSubject: [PATCH] wolfcrypt/src/port/devcrypto/devcrypto_aes.c: remove\n redundant \"int ret\" in wc_AesCtrEncrypt() (supersedes #5052).\n\n\ndiff --git a/wolfcrypt/src/port/devcrypto/devcrypto_aes.c b/wolfcrypt/src/port/devcrypto/devcrypto_aes.c\nindex 3bc1d5bb1..28e145e27 100644\n--- a/wolfcrypt/src/port/devcrypto/devcrypto_aes.c\n+++ b/wolfcrypt/src/port/devcrypto/devcrypto_aes.c\n@@ -208,7 +208,6 @@ int wc_AesCtrEncrypt(Aes* aes, byte* out, const byte* in, word32 sz)\n     int ret;\n     struct crypt_op crt;\n     byte* tmp;\n-    int ret;\n \n     if (aes == NULL || out == NULL || in == NULL) {\n         return BAD_FUNC_ARG;\n"
  },
  {
    "path": "package/libs/zlib/Config.in",
    "content": "menu \"Configuration\"\n\tdepends on PACKAGE_zlib\n\nconfig ZLIB_OPTIMIZE_SPEED\n\tbool \"Optimize for speed\"\n\thelp\n\t\tThis enables additional optimization and \n\t\tincreases performance considerably at \n\t\tthe expense of binary size.\n\nendmenu\n"
  },
  {
    "path": "package/libs/zlib/Makefile",
    "content": "#\n# Copyright (C) 2006-2013 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=zlib\nPKG_VERSION:=1.2.12\nPKG_RELEASE:=$(AUTORELEASE)\n\nPKG_SOURCE_PROTO:=git\nPKG_SOURCE_URL:=https://github.com/madler/zlib\nPKG_MIRROR_HASH:=a162fc219763635f0c1591ec515d4b08684e4b0bfb4b1c8e65e4eab18d597c27\nPKG_SOURCE_VERSION:=21767c654d31d2dccdde4330529775c6c5fd5389\n\nPKG_LICENSE:=Zlib\nPKG_LICENSE_FILES:=README\nPKG_CPE_ID:=cpe:/a:gnu:zlib\n\nPKG_CONFIG_DEPENDS:= CONFIG_ZLIB_OPTIMIZE_SPEED\n\ninclude $(INCLUDE_DIR)/package.mk\ninclude $(INCLUDE_DIR)/cmake.mk\n\ndefine Package/zlib\n  SECTION:=libs\n  CATEGORY:=Libraries\n  TITLE:=Library implementing the deflate compression method\n  URL:=http://www.zlib.net/\nendef\n\ndefine Package/zlib-dev\n  SECTION:=devel\n  CATEGORY:=Development\n  SUBMENU:=Libraries\n  DEPENDS:=zlib\n  TITLE:=Development files for the zlib library\nendef\n\ndefine Package/zlib/description\n zlib is a lossless data-compression library.\n This package includes the shared library.\nendef\n\ndefine Package/zlib-dev/description\n zlib is a lossless data-compression library.\n This package includes the development support files.\nendef\n\ndefine Package/zlib/config\n\tsource \"$(SOURCE)/Config.in\"\nendef\n\nTARGET_CFLAGS += $(FPIC)\n\nifeq ($(CONFIG_ZLIB_OPTIMIZE_SPEED),y)\n\tTARGET_CFLAGS := $(filter-out -O%,$(TARGET_CFLAGS)) -O3\nendif\n\nCMAKE_OPTIONS += \\\n\t-DARMv8=$$$$(echo -e '\\#ifdef __ARM_NEON__\\nON\\n\\#else\\nOFF\\n\\#endif' | $$(TARGET_CC) $$(TARGET_CFLAGS) -x c -E - | grep -xE 'ON|OFF')\n\ndefine Build/InstallDev\n\tmkdir -p $(1)/usr/include\n\t$(CP)\t$(PKG_INSTALL_DIR)/usr/include/z{conf,lib}.h \\\n\t\t$(1)/usr/include/\n\tmkdir -p $(1)/usr/lib\n\t$(CP)\t$(PKG_INSTALL_DIR)/usr/lib/libz.{a,so*} \\\n\t\t$(1)/usr/lib/\n\tmkdir -p $(1)/usr/lib/pkgconfig\n\t$(CP)\t$(PKG_INSTALL_DIR)/usr/share/pkgconfig/zlib.pc \\\n\t\t$(1)/usr/lib/pkgconfig/\nendef\n\n# libz.so is needed for openssl (zlib-dynamic)\ndefine Package/zlib/install\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/libz.so $(1)/usr/lib/\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/libz.so.* $(1)/usr/lib/\nendef\n\ndefine Package/zlib-dev/install\n\t$(INSTALL_DIR) $(1)/usr/include\n\t$(INSTALL_DATA) $(PKG_INSTALL_DIR)/usr/include/zconf.h \\\n\t  $(1)/usr/include/\n\t$(INSTALL_DATA) $(PKG_INSTALL_DIR)/usr/include/zlib.h \\\n\t  $(1)/usr/include/\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/libz.a $(1)/usr/lib/\n\t$(INSTALL_DIR) $(1)/usr/lib/pkgconfig\n\t$(INSTALL_DATA) $(PKG_INSTALL_DIR)/usr/share/pkgconfig/zlib.pc \\\n\t  $(1)/usr/lib/pkgconfig/\nendef\n\n$(eval $(call BuildPackage,zlib))\n$(eval $(call BuildPackage,zlib-dev))\n"
  },
  {
    "path": "package/libs/zlib/patches/001-neon-implementation-of-adler32.patch",
    "content": "From d2f06cd65d7ac39c6dd6761eef162abc946b155b Mon Sep 17 00:00:00 2001\nFrom: Adenilson Cavalcanti <adenilson.cavalcanti@arm.com>\nDate: Tue, 11 Apr 2017 17:13:02 -0700\nSubject: [PATCH] NEON implementation for Adler32\n\nThe checksum is calculated in the uncompressed PNG data\nand can be made much faster by using SIMD.\n\nTests in ARMv8 yielded an improvement of about 3x\n(e.g. walltime was 350ms x 125ms for a 4096x4096 bytes\nexecuted 30 times). That results in at least 18% improvement\nin image decoding in Chromium.\n\nFurther details at:\nhttps://bugs.chromium.org/p/chromium/issues/detail?id=688601\n---\n CMakeLists.txt             |  29 +++++++---\n adler32.c                  |   5 ++\n contrib/README.contrib     |   3 +\n contrib/arm/neon_adler32.c | 137 +++++++++++++++++++++++++++++++++++++++++++++\n 4 files changed, 166 insertions(+), 8 deletions(-)\n create mode 100644 contrib/arm/neon_adler32.c\n\n--- a/CMakeLists.txt\n+++ b/CMakeLists.txt\n@@ -7,6 +7,7 @@ set(VERSION \"1.2.12\")\n \n option(ASM686 \"Enable building i686 assembly implementation\")\n option(AMD64 \"Enable building amd64 assembly implementation\")\n+option(ARMv8 \"Enable building ARM NEON intrinsics implementation\")\n \n set(INSTALL_BIN_DIR \"${CMAKE_INSTALL_PREFIX}/bin\" CACHE PATH \"Installation directory for executables\")\n set(INSTALL_LIB_DIR \"${CMAKE_INSTALL_PREFIX}/lib\" CACHE PATH \"Installation directory for libraries\")\n@@ -132,14 +133,26 @@ endif()\n if(CMAKE_COMPILER_IS_GNUCC)\n     if(ASM686)\n         set(ZLIB_ASMS contrib/asm686/match.S)\n-    elseif (AMD64)\n+    elseif(AMD64)\n         set(ZLIB_ASMS contrib/amd64/amd64-match.S)\n-    endif ()\n+    elseif(ARMv8)\n+        set(ZLIB_ARMv8 contrib/arm/neon_adler32.c)\n+    endif()\n \n-\tif(ZLIB_ASMS)\n-\t\tadd_definitions(-DASMV)\n-\t\tset_source_files_properties(${ZLIB_ASMS} PROPERTIES LANGUAGE C COMPILE_FLAGS -DNO_UNDERLINE)\n-\tendif()\n+    if(ZLIB_ASMS)\n+        add_definitions(-DASMV)\n+\t    set_source_files_properties(${ZLIB_ASMS} PROPERTIES LANGUAGE C COMPILE_FLAGS -DNO_UNDERLINE)\n+    elseif(ZLIB_ARMv8)\n+        add_definitions(-DARMv8)\n+        set(COMPILER ${CMAKE_C_COMPILER})\n+        # NEON is mandatory in ARMv8.\n+        if(${COMPILER} MATCHES \"aarch64\")\n+            set_source_files_properties(${ZLIB_ARMv8} PROPERTIES LANGUAGE C COMPILE_FLAGS -march=armv8-a)\n+        # But it was optional for ARMv7.\n+        elseif(${COMPILER} MATCHES \"arm\")\n+            set_source_files_properties(${ZLIB_ARMv8} PROPERTIES LANGUAGE C COMPILE_FLAGS -mfpu=neon)\n+        endif()\n+    endif()\n endif()\n \n if(MSVC)\n@@ -183,8 +196,8 @@ if(MINGW)\n     set(ZLIB_DLL_SRCS ${CMAKE_CURRENT_BINARY_DIR}/zlib1rc.obj)\n endif(MINGW)\n \n-add_library(zlib SHARED ${ZLIB_SRCS} ${ZLIB_ASMS} ${ZLIB_DLL_SRCS} ${ZLIB_PUBLIC_HDRS} ${ZLIB_PRIVATE_HDRS})\n-add_library(zlibstatic STATIC ${ZLIB_SRCS} ${ZLIB_ASMS} ${ZLIB_PUBLIC_HDRS} ${ZLIB_PRIVATE_HDRS})\n+add_library(zlib SHARED ${ZLIB_SRCS} ${ZLIB_ASMS} ${ZLIB_ARMv8} ${ZLIB_DLL_SRCS} ${ZLIB_PUBLIC_HDRS} ${ZLIB_PRIVATE_HDRS})\n+add_library(zlibstatic STATIC ${ZLIB_SRCS} ${ZLIB_ASMS} ${ZLIB_ARMv8} ${ZLIB_PUBLIC_HDRS} ${ZLIB_PRIVATE_HDRS})\n set_target_properties(zlib PROPERTIES DEFINE_SYMBOL ZLIB_DLL)\n set_target_properties(zlib PROPERTIES SOVERSION 1)\n \n--- a/adler32.c\n+++ b/adler32.c\n@@ -136,7 +136,14 @@ uLong ZEXPORT adler32(adler, buf, len)\n     const Bytef *buf;\n     uInt len;\n {\n+#ifdef ARMv8\n+#  pragma message(\"Using NEON-ized Adler32.\")\n+unsigned long NEON_adler32(unsigned long adler, const unsigned char *buf,\n+                                  const unsigned int len);\n+    return NEON_adler32(adler, buf, len);\n+#else\n     return adler32_z(adler, buf, len);\n+#endif\n }\n \n /* ========================================================================= */\n--- a/contrib/README.contrib\n+++ b/contrib/README.contrib\n@@ -8,6 +8,9 @@ ada/        by Dmitriy Anisimkov <anisim\n         Support for Ada\n         See http://zlib-ada.sourceforge.net/\n \n+arm/        by Adenilson Cavalcanti <cavalcantii@chromium.org>\n+        ARM optimizations (NEON and ARMv8 code).\n+\n blast/      by Mark Adler <madler@alumni.caltech.edu>\n         Decompressor for output of PKWare Data Compression Library (DCL)\n \n--- /dev/null\n+++ b/contrib/arm/neon_adler32.c\n@@ -0,0 +1,137 @@\n+/* Copyright (C) 1995-2011, 2016 Mark Adler\n+ * Copyright (C) 2017 ARM Holdings Inc.\n+ * Authors: Adenilson Cavalcanti <adenilson.cavalcanti@arm.com>\n+ *          Simon Hosie <simon.hosie@arm.com>\n+ * This software is provided 'as-is', without any express or implied\n+ * warranty.  In no event will the authors be held liable for any damages\n+ * arising from the use of this software.\n+ * Permission is granted to anyone to use this software for any purpose,\n+ * including commercial applications, and to alter it and redistribute it\n+ * freely, subject to the following restrictions:\n+ * 1. The origin of this software must not be misrepresented; you must not\n+ *  claim that you wrote the original software. If you use this software\n+ *    in a product, an acknowledgment in the product documentation would be\n+ *    appreciated but is not required.\n+ * 2. Altered source versions must be plainly marked as such, and must not be\n+ *    misrepresented as being the original software.\n+ * 3. This notice may not be removed or altered from any source distribution.\n+ */\n+\n+#if (defined(__ARM_NEON__) || defined(__ARM_NEON))\n+#include <arm_neon.h>\n+\n+static void NEON_accum32(uint32_t *s, const unsigned char *buf,\n+                         unsigned int len)\n+{\n+    static const uint8_t taps[32] = {\n+        32, 31, 30, 29, 28, 27, 26, 25,\n+        24, 23, 22, 21, 20, 19, 18, 17,\n+        16, 15, 14, 13, 12, 11, 10, 9,\n+        8, 7, 6, 5, 4, 3, 2, 1 };\n+\n+    uint32x2_t adacc2, s2acc2, as;\n+    uint8x16_t t0 = vld1q_u8(taps), t1 = vld1q_u8(taps + 16);\n+\n+    uint32x4_t adacc = vdupq_n_u32(0), s2acc = vdupq_n_u32(0);\n+    adacc = vsetq_lane_u32(s[0], adacc, 0);\n+    s2acc = vsetq_lane_u32(s[1], s2acc, 0);\n+\n+    while (len >= 2) {\n+        uint8x16_t d0 = vld1q_u8(buf), d1 = vld1q_u8(buf + 16);\n+        uint16x8_t adler, sum2;\n+        s2acc = vaddq_u32(s2acc, vshlq_n_u32(adacc, 5));\n+        adler = vpaddlq_u8(       d0);\n+        adler = vpadalq_u8(adler, d1);\n+        sum2 = vmull_u8(      vget_low_u8(t0), vget_low_u8(d0));\n+        sum2 = vmlal_u8(sum2, vget_high_u8(t0), vget_high_u8(d0));\n+        sum2 = vmlal_u8(sum2, vget_low_u8(t1), vget_low_u8(d1));\n+        sum2 = vmlal_u8(sum2, vget_high_u8(t1), vget_high_u8(d1));\n+        adacc = vpadalq_u16(adacc, adler);\n+        s2acc = vpadalq_u16(s2acc, sum2);\n+        len -= 2;\n+        buf += 32;\n+    }\n+\n+    while (len > 0) {\n+        uint8x16_t d0 = vld1q_u8(buf);\n+        uint16x8_t adler, sum2;\n+        s2acc = vaddq_u32(s2acc, vshlq_n_u32(adacc, 4));\n+        adler = vpaddlq_u8(d0);\n+        sum2 = vmull_u8(      vget_low_u8(t1), vget_low_u8(d0));\n+        sum2 = vmlal_u8(sum2, vget_high_u8(t1), vget_high_u8(d0));\n+        adacc = vpadalq_u16(adacc, adler);\n+        s2acc = vpadalq_u16(s2acc, sum2);\n+        buf += 16;\n+        len--;\n+    }\n+\n+    adacc2 = vpadd_u32(vget_low_u32(adacc), vget_high_u32(adacc));\n+    s2acc2 = vpadd_u32(vget_low_u32(s2acc), vget_high_u32(s2acc));\n+    as = vpadd_u32(adacc2, s2acc2);\n+    s[0] = vget_lane_u32(as, 0);\n+    s[1] = vget_lane_u32(as, 1);\n+}\n+\n+static void NEON_handle_tail(uint32_t *pair, const unsigned char *buf,\n+                             unsigned int len)\n+{\n+    /* Oldie K&R code integration. */\n+    unsigned int i;\n+    for (i = 0; i < len; ++i) {\n+        pair[0] += buf[i];\n+        pair[1] += pair[0];\n+    }\n+}\n+\n+extern unsigned long NEON_adler32(unsigned long adler, const unsigned char *buf,\n+                                  const unsigned int len)\n+{\n+    /* initial Adler-32 value (deferred check for len == 1 speed) */\n+    if (!buf)\n+        return 1L;\n+\n+    /* The largest prime smaller than 65536. */\n+    const uint32_t M_BASE = 65521;\n+    /* This is the threshold where doing accumulation may overflow. */\n+    const int M_NMAX = 5552;\n+\n+    unsigned long sum2;\n+    uint32_t pair[2];\n+    int n = M_NMAX;\n+    unsigned int done = 0;\n+    /* Oldie K&R code integration. */\n+    unsigned int i;\n+\n+    /* Split Adler-32 into component sums, it can be supplied by\n+     * the caller sites (e.g. in a PNG file).\n+     */\n+    sum2 = (adler >> 16) & 0xffff;\n+    adler &= 0xffff;\n+    pair[0] = adler;\n+    pair[1] = sum2;\n+\n+    for (i = 0; i < len; i += n) {\n+        if ((i + n) > len)\n+            n = len - i;\n+\n+        if (n < 16)\n+            break;\n+\n+        NEON_accum32(pair, buf + i, n / 16);\n+        pair[0] %= M_BASE;\n+        pair[1] %= M_BASE;\n+\n+        done += (n / 16) * 16;\n+    }\n+\n+    /* Handle the tail elements. */\n+    if (done < len) {\n+        NEON_handle_tail(pair, (buf + done), len - done);\n+        pair[0] %= M_BASE;\n+        pair[1] %= M_BASE;\n+    }\n+\n+    /* D = B * 65536 + A, see: https://en.wikipedia.org/wiki/Adler-32. */\n+    return (pair[1] << 16) | pair[0];\n+}\n+#endif\n"
  },
  {
    "path": "package/libs/zlib/patches/002-arm-specific-optimisations-for-inflate.patch",
    "content": "From 6bac7a3e0ebcd3147294b73acb34606eba18ae7f Mon Sep 17 00:00:00 2001\nFrom: Simon Hosie <simon.hosie@arm.com>\nDate: Wed, 12 Apr 2017 12:52:33 -0700\nSubject: [PATCH 1/2] Prepare ARM-specific contrib directory.\n\nChange-Id: Id4cda552b39bfb39ab35ec499dbe122b43b6d1a1\n---\n contrib/arm/inffast.c |  323 ++++++++++\n contrib/arm/inflate.c | 1561 +++++++++++++++++++++++++++++++++++++++++++++++++\n 2 files changed, 1884 insertions(+)\n create mode 100644 contrib/arm/inffast.c\n create mode 100644 contrib/arm/inflate.c\n\ndiff --git a/contrib/arm/inffast.c b/contrib/arm/inffast.c\nnew file mode 100644\nindex 00000000..0dbd1dbc\n--- /dev/null\n+++ b/contrib/arm/inffast.c\n@@ -0,0 +1,323 @@\n+/* inffast.c -- fast decoding\n+ * Copyright (C) 1995-2017 Mark Adler\n+ * For conditions of distribution and use, see copyright notice in zlib.h\n+ */\n+\n+#include \"zutil.h\"\n+#include \"inftrees.h\"\n+#include \"inflate.h\"\n+#include \"inffast.h\"\n+\n+#ifdef ASMINF\n+#  pragma message(\"Assembler code may have bugs -- use at your own risk\")\n+#else\n+\n+/*\n+   Decode literal, length, and distance codes and write out the resulting\n+   literal and match bytes until either not enough input or output is\n+   available, an end-of-block is encountered, or a data error is encountered.\n+   When large enough input and output buffers are supplied to inflate(), for\n+   example, a 16K input buffer and a 64K output buffer, more than 95% of the\n+   inflate execution time is spent in this routine.\n+\n+   Entry assumptions:\n+\n+        state->mode == LEN\n+        strm->avail_in >= 6\n+        strm->avail_out >= 258\n+        start >= strm->avail_out\n+        state->bits < 8\n+\n+   On return, state->mode is one of:\n+\n+        LEN -- ran out of enough output space or enough available input\n+        TYPE -- reached end of block code, inflate() to interpret next block\n+        BAD -- error in block data\n+\n+   Notes:\n+\n+    - The maximum input bits used by a length/distance pair is 15 bits for the\n+      length code, 5 bits for the length extra, 15 bits for the distance code,\n+      and 13 bits for the distance extra.  This totals 48 bits, or six bytes.\n+      Therefore if strm->avail_in >= 6, then there is enough input to avoid\n+      checking for available input while decoding.\n+\n+    - The maximum bytes that a single length/distance pair can output is 258\n+      bytes, which is the maximum length that can be coded.  inflate_fast()\n+      requires strm->avail_out >= 258 for each loop to avoid checking for\n+      output space.\n+ */\n+void ZLIB_INTERNAL inflate_fast(strm, start)\n+z_streamp strm;\n+unsigned start;         /* inflate()'s starting value for strm->avail_out */\n+{\n+    struct inflate_state FAR *state;\n+    z_const unsigned char FAR *in;      /* local strm->next_in */\n+    z_const unsigned char FAR *last;    /* have enough input while in < last */\n+    unsigned char FAR *out;     /* local strm->next_out */\n+    unsigned char FAR *beg;     /* inflate()'s initial strm->next_out */\n+    unsigned char FAR *end;     /* while out < end, enough space available */\n+#ifdef INFLATE_STRICT\n+    unsigned dmax;              /* maximum distance from zlib header */\n+#endif\n+    unsigned wsize;             /* window size or zero if not using window */\n+    unsigned whave;             /* valid bytes in the window */\n+    unsigned wnext;             /* window write index */\n+    unsigned char FAR *window;  /* allocated sliding window, if wsize != 0 */\n+    unsigned long hold;         /* local strm->hold */\n+    unsigned bits;              /* local strm->bits */\n+    code const FAR *lcode;      /* local strm->lencode */\n+    code const FAR *dcode;      /* local strm->distcode */\n+    unsigned lmask;             /* mask for first level of length codes */\n+    unsigned dmask;             /* mask for first level of distance codes */\n+    code here;                  /* retrieved table entry */\n+    unsigned op;                /* code bits, operation, extra bits, or */\n+                                /*  window position, window bytes to copy */\n+    unsigned len;               /* match length, unused bytes */\n+    unsigned dist;              /* match distance */\n+    unsigned char FAR *from;    /* where to copy match from */\n+\n+    /* copy state to local variables */\n+    state = (struct inflate_state FAR *)strm->state;\n+    in = strm->next_in;\n+    last = in + (strm->avail_in - 5);\n+    out = strm->next_out;\n+    beg = out - (start - strm->avail_out);\n+    end = out + (strm->avail_out - 257);\n+#ifdef INFLATE_STRICT\n+    dmax = state->dmax;\n+#endif\n+    wsize = state->wsize;\n+    whave = state->whave;\n+    wnext = state->wnext;\n+    window = state->window;\n+    hold = state->hold;\n+    bits = state->bits;\n+    lcode = state->lencode;\n+    dcode = state->distcode;\n+    lmask = (1U << state->lenbits) - 1;\n+    dmask = (1U << state->distbits) - 1;\n+\n+    /* decode literals and length/distances until end-of-block or not enough\n+       input data or output space */\n+    do {\n+        if (bits < 15) {\n+            hold += (unsigned long)(*in++) << bits;\n+            bits += 8;\n+            hold += (unsigned long)(*in++) << bits;\n+            bits += 8;\n+        }\n+        here = lcode[hold & lmask];\n+      dolen:\n+        op = (unsigned)(here.bits);\n+        hold >>= op;\n+        bits -= op;\n+        op = (unsigned)(here.op);\n+        if (op == 0) {                          /* literal */\n+            Tracevv((stderr, here.val >= 0x20 && here.val < 0x7f ?\n+                    \"inflate:         literal '%c'\\n\" :\n+                    \"inflate:         literal 0x%02x\\n\", here.val));\n+            *out++ = (unsigned char)(here.val);\n+        }\n+        else if (op & 16) {                     /* length base */\n+            len = (unsigned)(here.val);\n+            op &= 15;                           /* number of extra bits */\n+            if (op) {\n+                if (bits < op) {\n+                    hold += (unsigned long)(*in++) << bits;\n+                    bits += 8;\n+                }\n+                len += (unsigned)hold & ((1U << op) - 1);\n+                hold >>= op;\n+                bits -= op;\n+            }\n+            Tracevv((stderr, \"inflate:         length %u\\n\", len));\n+            if (bits < 15) {\n+                hold += (unsigned long)(*in++) << bits;\n+                bits += 8;\n+                hold += (unsigned long)(*in++) << bits;\n+                bits += 8;\n+            }\n+            here = dcode[hold & dmask];\n+          dodist:\n+            op = (unsigned)(here.bits);\n+            hold >>= op;\n+            bits -= op;\n+            op = (unsigned)(here.op);\n+            if (op & 16) {                      /* distance base */\n+                dist = (unsigned)(here.val);\n+                op &= 15;                       /* number of extra bits */\n+                if (bits < op) {\n+                    hold += (unsigned long)(*in++) << bits;\n+                    bits += 8;\n+                    if (bits < op) {\n+                        hold += (unsigned long)(*in++) << bits;\n+                        bits += 8;\n+                    }\n+                }\n+                dist += (unsigned)hold & ((1U << op) - 1);\n+#ifdef INFLATE_STRICT\n+                if (dist > dmax) {\n+                    strm->msg = (char *)\"invalid distance too far back\";\n+                    state->mode = BAD;\n+                    break;\n+                }\n+#endif\n+                hold >>= op;\n+                bits -= op;\n+                Tracevv((stderr, \"inflate:         distance %u\\n\", dist));\n+                op = (unsigned)(out - beg);     /* max distance in output */\n+                if (dist > op) {                /* see if copy from window */\n+                    op = dist - op;             /* distance back in window */\n+                    if (op > whave) {\n+                        if (state->sane) {\n+                            strm->msg =\n+                                (char *)\"invalid distance too far back\";\n+                            state->mode = BAD;\n+                            break;\n+                        }\n+#ifdef INFLATE_ALLOW_INVALID_DISTANCE_TOOFAR_ARRR\n+                        if (len <= op - whave) {\n+                            do {\n+                                *out++ = 0;\n+                            } while (--len);\n+                            continue;\n+                        }\n+                        len -= op - whave;\n+                        do {\n+                            *out++ = 0;\n+                        } while (--op > whave);\n+                        if (op == 0) {\n+                            from = out - dist;\n+                            do {\n+                                *out++ = *from++;\n+                            } while (--len);\n+                            continue;\n+                        }\n+#endif\n+                    }\n+                    from = window;\n+                    if (wnext == 0) {           /* very common case */\n+                        from += wsize - op;\n+                        if (op < len) {         /* some from window */\n+                            len -= op;\n+                            do {\n+                                *out++ = *from++;\n+                            } while (--op);\n+                            from = out - dist;  /* rest from output */\n+                        }\n+                    }\n+                    else if (wnext < op) {      /* wrap around window */\n+                        from += wsize + wnext - op;\n+                        op -= wnext;\n+                        if (op < len) {         /* some from end of window */\n+                            len -= op;\n+                            do {\n+                                *out++ = *from++;\n+                            } while (--op);\n+                            from = window;\n+                            if (wnext < len) {  /* some from start of window */\n+                                op = wnext;\n+                                len -= op;\n+                                do {\n+                                    *out++ = *from++;\n+                                } while (--op);\n+                                from = out - dist;      /* rest from output */\n+                            }\n+                        }\n+                    }\n+                    else {                      /* contiguous in window */\n+                        from += wnext - op;\n+                        if (op < len) {         /* some from window */\n+                            len -= op;\n+                            do {\n+                                *out++ = *from++;\n+                            } while (--op);\n+                            from = out - dist;  /* rest from output */\n+                        }\n+                    }\n+                    while (len > 2) {\n+                        *out++ = *from++;\n+                        *out++ = *from++;\n+                        *out++ = *from++;\n+                        len -= 3;\n+                    }\n+                    if (len) {\n+                        *out++ = *from++;\n+                        if (len > 1)\n+                            *out++ = *from++;\n+                    }\n+                }\n+                else {\n+                    from = out - dist;          /* copy direct from output */\n+                    do {                        /* minimum length is three */\n+                        *out++ = *from++;\n+                        *out++ = *from++;\n+                        *out++ = *from++;\n+                        len -= 3;\n+                    } while (len > 2);\n+                    if (len) {\n+                        *out++ = *from++;\n+                        if (len > 1)\n+                            *out++ = *from++;\n+                    }\n+                }\n+            }\n+            else if ((op & 64) == 0) {          /* 2nd level distance code */\n+                here = dcode[here.val + (hold & ((1U << op) - 1))];\n+                goto dodist;\n+            }\n+            else {\n+                strm->msg = (char *)\"invalid distance code\";\n+                state->mode = BAD;\n+                break;\n+            }\n+        }\n+        else if ((op & 64) == 0) {              /* 2nd level length code */\n+            here = lcode[here.val + (hold & ((1U << op) - 1))];\n+            goto dolen;\n+        }\n+        else if (op & 32) {                     /* end-of-block */\n+            Tracevv((stderr, \"inflate:         end of block\\n\"));\n+            state->mode = TYPE;\n+            break;\n+        }\n+        else {\n+            strm->msg = (char *)\"invalid literal/length code\";\n+            state->mode = BAD;\n+            break;\n+        }\n+    } while (in < last && out < end);\n+\n+    /* return unused bytes (on entry, bits < 8, so in won't go too far back) */\n+    len = bits >> 3;\n+    in -= len;\n+    bits -= len << 3;\n+    hold &= (1U << bits) - 1;\n+\n+    /* update state and return */\n+    strm->next_in = in;\n+    strm->next_out = out;\n+    strm->avail_in = (unsigned)(in < last ? 5 + (last - in) : 5 - (in - last));\n+    strm->avail_out = (unsigned)(out < end ?\n+                                 257 + (end - out) : 257 - (out - end));\n+    state->hold = hold;\n+    state->bits = bits;\n+    return;\n+}\n+\n+/*\n+   inflate_fast() speedups that turned out slower (on a PowerPC G3 750CXe):\n+   - Using bit fields for code structure\n+   - Different op definition to avoid & for extra bits (do & for table bits)\n+   - Three separate decoding do-loops for direct, window, and wnext == 0\n+   - Special case for distance > 1 copies to do overlapped load and store copy\n+   - Explicit branch predictions (based on measured branch probabilities)\n+   - Deferring match copy and interspersed it with decoding subsequent codes\n+   - Swapping literal/length else\n+   - Swapping window/direct else\n+   - Larger unrolled copy loops (three is about right)\n+   - Moving len -= 3 statement into middle of loop\n+ */\n+\n+#endif /* !ASMINF */\ndiff --git a/contrib/arm/inflate.c b/contrib/arm/inflate.c\nnew file mode 100644\nindex 00000000..ac333e8c\n--- /dev/null\n+++ b/contrib/arm/inflate.c\n@@ -0,0 +1,1561 @@\n+/* inflate.c -- zlib decompression\n+ * Copyright (C) 1995-2016 Mark Adler\n+ * For conditions of distribution and use, see copyright notice in zlib.h\n+ */\n+\n+/*\n+ * Change history:\n+ *\n+ * 1.2.beta0    24 Nov 2002\n+ * - First version -- complete rewrite of inflate to simplify code, avoid\n+ *   creation of window when not needed, minimize use of window when it is\n+ *   needed, make inffast.c even faster, implement gzip decoding, and to\n+ *   improve code readability and style over the previous zlib inflate code\n+ *\n+ * 1.2.beta1    25 Nov 2002\n+ * - Use pointers for available input and output checking in inffast.c\n+ * - Remove input and output counters in inffast.c\n+ * - Change inffast.c entry and loop from avail_in >= 7 to >= 6\n+ * - Remove unnecessary second byte pull from length extra in inffast.c\n+ * - Unroll direct copy to three copies per loop in inffast.c\n+ *\n+ * 1.2.beta2    4 Dec 2002\n+ * - Change external routine names to reduce potential conflicts\n+ * - Correct filename to inffixed.h for fixed tables in inflate.c\n+ * - Make hbuf[] unsigned char to match parameter type in inflate.c\n+ * - Change strm->next_out[-state->offset] to *(strm->next_out - state->offset)\n+ *   to avoid negation problem on Alphas (64 bit) in inflate.c\n+ *\n+ * 1.2.beta3    22 Dec 2002\n+ * - Add comments on state->bits assertion in inffast.c\n+ * - Add comments on op field in inftrees.h\n+ * - Fix bug in reuse of allocated window after inflateReset()\n+ * - Remove bit fields--back to byte structure for speed\n+ * - Remove distance extra == 0 check in inflate_fast()--only helps for lengths\n+ * - Change post-increments to pre-increments in inflate_fast(), PPC biased?\n+ * - Add compile time option, POSTINC, to use post-increments instead (Intel?)\n+ * - Make MATCH copy in inflate() much faster for when inflate_fast() not used\n+ * - Use local copies of stream next and avail values, as well as local bit\n+ *   buffer and bit count in inflate()--for speed when inflate_fast() not used\n+ *\n+ * 1.2.beta4    1 Jan 2003\n+ * - Split ptr - 257 statements in inflate_table() to avoid compiler warnings\n+ * - Move a comment on output buffer sizes from inffast.c to inflate.c\n+ * - Add comments in inffast.c to introduce the inflate_fast() routine\n+ * - Rearrange window copies in inflate_fast() for speed and simplification\n+ * - Unroll last copy for window match in inflate_fast()\n+ * - Use local copies of window variables in inflate_fast() for speed\n+ * - Pull out common wnext == 0 case for speed in inflate_fast()\n+ * - Make op and len in inflate_fast() unsigned for consistency\n+ * - Add FAR to lcode and dcode declarations in inflate_fast()\n+ * - Simplified bad distance check in inflate_fast()\n+ * - Added inflateBackInit(), inflateBack(), and inflateBackEnd() in new\n+ *   source file infback.c to provide a call-back interface to inflate for\n+ *   programs like gzip and unzip -- uses window as output buffer to avoid\n+ *   window copying\n+ *\n+ * 1.2.beta5    1 Jan 2003\n+ * - Improved inflateBack() interface to allow the caller to provide initial\n+ *   input in strm.\n+ * - Fixed stored blocks bug in inflateBack()\n+ *\n+ * 1.2.beta6    4 Jan 2003\n+ * - Added comments in inffast.c on effectiveness of POSTINC\n+ * - Typecasting all around to reduce compiler warnings\n+ * - Changed loops from while (1) or do {} while (1) to for (;;), again to\n+ *   make compilers happy\n+ * - Changed type of window in inflateBackInit() to unsigned char *\n+ *\n+ * 1.2.beta7    27 Jan 2003\n+ * - Changed many types to unsigned or unsigned short to avoid warnings\n+ * - Added inflateCopy() function\n+ *\n+ * 1.2.0        9 Mar 2003\n+ * - Changed inflateBack() interface to provide separate opaque descriptors\n+ *   for the in() and out() functions\n+ * - Changed inflateBack() argument and in_func typedef to swap the length\n+ *   and buffer address return values for the input function\n+ * - Check next_in and next_out for Z_NULL on entry to inflate()\n+ *\n+ * The history for versions after 1.2.0 are in ChangeLog in zlib distribution.\n+ */\n+\n+#include \"zutil.h\"\n+#include \"inftrees.h\"\n+#include \"inflate.h\"\n+#include \"inffast.h\"\n+\n+#ifdef MAKEFIXED\n+#  ifndef BUILDFIXED\n+#    define BUILDFIXED\n+#  endif\n+#endif\n+\n+/* function prototypes */\n+local int inflateStateCheck OF((z_streamp strm));\n+local void fixedtables OF((struct inflate_state FAR *state));\n+local int updatewindow OF((z_streamp strm, const unsigned char FAR *end,\n+                           unsigned copy));\n+#ifdef BUILDFIXED\n+   void makefixed OF((void));\n+#endif\n+local unsigned syncsearch OF((unsigned FAR *have, const unsigned char FAR *buf,\n+                              unsigned len));\n+\n+local int inflateStateCheck(strm)\n+z_streamp strm;\n+{\n+    struct inflate_state FAR *state;\n+    if (strm == Z_NULL ||\n+        strm->zalloc == (alloc_func)0 || strm->zfree == (free_func)0)\n+        return 1;\n+    state = (struct inflate_state FAR *)strm->state;\n+    if (state == Z_NULL || state->strm != strm ||\n+        state->mode < HEAD || state->mode > SYNC)\n+        return 1;\n+    return 0;\n+}\n+\n+int ZEXPORT inflateResetKeep(strm)\n+z_streamp strm;\n+{\n+    struct inflate_state FAR *state;\n+\n+    if (inflateStateCheck(strm)) return Z_STREAM_ERROR;\n+    state = (struct inflate_state FAR *)strm->state;\n+    strm->total_in = strm->total_out = state->total = 0;\n+    strm->msg = Z_NULL;\n+    if (state->wrap)        /* to support ill-conceived Java test suite */\n+        strm->adler = state->wrap & 1;\n+    state->mode = HEAD;\n+    state->last = 0;\n+    state->havedict = 0;\n+    state->dmax = 32768U;\n+    state->head = Z_NULL;\n+    state->hold = 0;\n+    state->bits = 0;\n+    state->lencode = state->distcode = state->next = state->codes;\n+    state->sane = 1;\n+    state->back = -1;\n+    Tracev((stderr, \"inflate: reset\\n\"));\n+    return Z_OK;\n+}\n+\n+int ZEXPORT inflateReset(strm)\n+z_streamp strm;\n+{\n+    struct inflate_state FAR *state;\n+\n+    if (inflateStateCheck(strm)) return Z_STREAM_ERROR;\n+    state = (struct inflate_state FAR *)strm->state;\n+    state->wsize = 0;\n+    state->whave = 0;\n+    state->wnext = 0;\n+    return inflateResetKeep(strm);\n+}\n+\n+int ZEXPORT inflateReset2(strm, windowBits)\n+z_streamp strm;\n+int windowBits;\n+{\n+    int wrap;\n+    struct inflate_state FAR *state;\n+\n+    /* get the state */\n+    if (inflateStateCheck(strm)) return Z_STREAM_ERROR;\n+    state = (struct inflate_state FAR *)strm->state;\n+\n+    /* extract wrap request from windowBits parameter */\n+    if (windowBits < 0) {\n+        wrap = 0;\n+        windowBits = -windowBits;\n+    }\n+    else {\n+        wrap = (windowBits >> 4) + 5;\n+#ifdef GUNZIP\n+        if (windowBits < 48)\n+            windowBits &= 15;\n+#endif\n+    }\n+\n+    /* set number of window bits, free window if different */\n+    if (windowBits && (windowBits < 8 || windowBits > 15))\n+        return Z_STREAM_ERROR;\n+    if (state->window != Z_NULL && state->wbits != (unsigned)windowBits) {\n+        ZFREE(strm, state->window);\n+        state->window = Z_NULL;\n+    }\n+\n+    /* update state and reset the rest of it */\n+    state->wrap = wrap;\n+    state->wbits = (unsigned)windowBits;\n+    return inflateReset(strm);\n+}\n+\n+int ZEXPORT inflateInit2_(strm, windowBits, version, stream_size)\n+z_streamp strm;\n+int windowBits;\n+const char *version;\n+int stream_size;\n+{\n+    int ret;\n+    struct inflate_state FAR *state;\n+\n+    if (version == Z_NULL || version[0] != ZLIB_VERSION[0] ||\n+        stream_size != (int)(sizeof(z_stream)))\n+        return Z_VERSION_ERROR;\n+    if (strm == Z_NULL) return Z_STREAM_ERROR;\n+    strm->msg = Z_NULL;                 /* in case we return an error */\n+    if (strm->zalloc == (alloc_func)0) {\n+#ifdef Z_SOLO\n+        return Z_STREAM_ERROR;\n+#else\n+        strm->zalloc = zcalloc;\n+        strm->opaque = (voidpf)0;\n+#endif\n+    }\n+    if (strm->zfree == (free_func)0)\n+#ifdef Z_SOLO\n+        return Z_STREAM_ERROR;\n+#else\n+        strm->zfree = zcfree;\n+#endif\n+    state = (struct inflate_state FAR *)\n+            ZALLOC(strm, 1, sizeof(struct inflate_state));\n+    if (state == Z_NULL) return Z_MEM_ERROR;\n+    Tracev((stderr, \"inflate: allocated\\n\"));\n+    strm->state = (struct internal_state FAR *)state;\n+    state->strm = strm;\n+    state->window = Z_NULL;\n+    state->mode = HEAD;     /* to pass state test in inflateReset2() */\n+    ret = inflateReset2(strm, windowBits);\n+    if (ret != Z_OK) {\n+        ZFREE(strm, state);\n+        strm->state = Z_NULL;\n+    }\n+    return ret;\n+}\n+\n+int ZEXPORT inflateInit_(strm, version, stream_size)\n+z_streamp strm;\n+const char *version;\n+int stream_size;\n+{\n+    return inflateInit2_(strm, DEF_WBITS, version, stream_size);\n+}\n+\n+int ZEXPORT inflatePrime(strm, bits, value)\n+z_streamp strm;\n+int bits;\n+int value;\n+{\n+    struct inflate_state FAR *state;\n+\n+    if (inflateStateCheck(strm)) return Z_STREAM_ERROR;\n+    state = (struct inflate_state FAR *)strm->state;\n+    if (bits < 0) {\n+        state->hold = 0;\n+        state->bits = 0;\n+        return Z_OK;\n+    }\n+    if (bits > 16 || state->bits + (uInt)bits > 32) return Z_STREAM_ERROR;\n+    value &= (1L << bits) - 1;\n+    state->hold += (unsigned)value << state->bits;\n+    state->bits += (uInt)bits;\n+    return Z_OK;\n+}\n+\n+/*\n+   Return state with length and distance decoding tables and index sizes set to\n+   fixed code decoding.  Normally this returns fixed tables from inffixed.h.\n+   If BUILDFIXED is defined, then instead this routine builds the tables the\n+   first time it's called, and returns those tables the first time and\n+   thereafter.  This reduces the size of the code by about 2K bytes, in\n+   exchange for a little execution time.  However, BUILDFIXED should not be\n+   used for threaded applications, since the rewriting of the tables and virgin\n+   may not be thread-safe.\n+ */\n+local void fixedtables(state)\n+struct inflate_state FAR *state;\n+{\n+#ifdef BUILDFIXED\n+    static int virgin = 1;\n+    static code *lenfix, *distfix;\n+    static code fixed[544];\n+\n+    /* build fixed huffman tables if first call (may not be thread safe) */\n+    if (virgin) {\n+        unsigned sym, bits;\n+        static code *next;\n+\n+        /* literal/length table */\n+        sym = 0;\n+        while (sym < 144) state->lens[sym++] = 8;\n+        while (sym < 256) state->lens[sym++] = 9;\n+        while (sym < 280) state->lens[sym++] = 7;\n+        while (sym < 288) state->lens[sym++] = 8;\n+        next = fixed;\n+        lenfix = next;\n+        bits = 9;\n+        inflate_table(LENS, state->lens, 288, &(next), &(bits), state->work);\n+\n+        /* distance table */\n+        sym = 0;\n+        while (sym < 32) state->lens[sym++] = 5;\n+        distfix = next;\n+        bits = 5;\n+        inflate_table(DISTS, state->lens, 32, &(next), &(bits), state->work);\n+\n+        /* do this just once */\n+        virgin = 0;\n+    }\n+#else /* !BUILDFIXED */\n+#   include \"inffixed.h\"\n+#endif /* BUILDFIXED */\n+    state->lencode = lenfix;\n+    state->lenbits = 9;\n+    state->distcode = distfix;\n+    state->distbits = 5;\n+}\n+\n+#ifdef MAKEFIXED\n+#include <stdio.h>\n+\n+/*\n+   Write out the inffixed.h that is #include'd above.  Defining MAKEFIXED also\n+   defines BUILDFIXED, so the tables are built on the fly.  makefixed() writes\n+   those tables to stdout, which would be piped to inffixed.h.  A small program\n+   can simply call makefixed to do this:\n+\n+    void makefixed(void);\n+\n+    int main(void)\n+    {\n+        makefixed();\n+        return 0;\n+    }\n+\n+   Then that can be linked with zlib built with MAKEFIXED defined and run:\n+\n+    a.out > inffixed.h\n+ */\n+void makefixed()\n+{\n+    unsigned low, size;\n+    struct inflate_state state;\n+\n+    fixedtables(&state);\n+    puts(\"    /* inffixed.h -- table for decoding fixed codes\");\n+    puts(\"     * Generated automatically by makefixed().\");\n+    puts(\"     */\");\n+    puts(\"\");\n+    puts(\"    /* WARNING: this file should *not* be used by applications.\");\n+    puts(\"       It is part of the implementation of this library and is\");\n+    puts(\"       subject to change. Applications should only use zlib.h.\");\n+    puts(\"     */\");\n+    puts(\"\");\n+    size = 1U << 9;\n+    printf(\"    static const code lenfix[%u] = {\", size);\n+    low = 0;\n+    for (;;) {\n+        if ((low % 7) == 0) printf(\"\\n        \");\n+        printf(\"{%u,%u,%d}\", (low & 127) == 99 ? 64 : state.lencode[low].op,\n+               state.lencode[low].bits, state.lencode[low].val);\n+        if (++low == size) break;\n+        putchar(',');\n+    }\n+    puts(\"\\n    };\");\n+    size = 1U << 5;\n+    printf(\"\\n    static const code distfix[%u] = {\", size);\n+    low = 0;\n+    for (;;) {\n+        if ((low % 6) == 0) printf(\"\\n        \");\n+        printf(\"{%u,%u,%d}\", state.distcode[low].op, state.distcode[low].bits,\n+               state.distcode[low].val);\n+        if (++low == size) break;\n+        putchar(',');\n+    }\n+    puts(\"\\n    };\");\n+}\n+#endif /* MAKEFIXED */\n+\n+/*\n+   Update the window with the last wsize (normally 32K) bytes written before\n+   returning.  If window does not exist yet, create it.  This is only called\n+   when a window is already in use, or when output has been written during this\n+   inflate call, but the end of the deflate stream has not been reached yet.\n+   It is also called to create a window for dictionary data when a dictionary\n+   is loaded.\n+\n+   Providing output buffers larger than 32K to inflate() should provide a speed\n+   advantage, since only the last 32K of output is copied to the sliding window\n+   upon return from inflate(), and since all distances after the first 32K of\n+   output will fall in the output data, making match copies simpler and faster.\n+   The advantage may be dependent on the size of the processor's data caches.\n+ */\n+local int updatewindow(strm, end, copy)\n+z_streamp strm;\n+const Bytef *end;\n+unsigned copy;\n+{\n+    struct inflate_state FAR *state;\n+    unsigned dist;\n+\n+    state = (struct inflate_state FAR *)strm->state;\n+\n+    /* if it hasn't been done already, allocate space for the window */\n+    if (state->window == Z_NULL) {\n+        state->window = (unsigned char FAR *)\n+                        ZALLOC(strm, 1U << state->wbits,\n+                               sizeof(unsigned char));\n+        if (state->window == Z_NULL) return 1;\n+    }\n+\n+    /* if window not in use yet, initialize */\n+    if (state->wsize == 0) {\n+        state->wsize = 1U << state->wbits;\n+        state->wnext = 0;\n+        state->whave = 0;\n+    }\n+\n+    /* copy state->wsize or less output bytes into the circular window */\n+    if (copy >= state->wsize) {\n+        zmemcpy(state->window, end - state->wsize, state->wsize);\n+        state->wnext = 0;\n+        state->whave = state->wsize;\n+    }\n+    else {\n+        dist = state->wsize - state->wnext;\n+        if (dist > copy) dist = copy;\n+        zmemcpy(state->window + state->wnext, end - copy, dist);\n+        copy -= dist;\n+        if (copy) {\n+            zmemcpy(state->window, end - copy, copy);\n+            state->wnext = copy;\n+            state->whave = state->wsize;\n+        }\n+        else {\n+            state->wnext += dist;\n+            if (state->wnext == state->wsize) state->wnext = 0;\n+            if (state->whave < state->wsize) state->whave += dist;\n+        }\n+    }\n+    return 0;\n+}\n+\n+/* Macros for inflate(): */\n+\n+/* check function to use adler32() for zlib or crc32() for gzip */\n+#ifdef GUNZIP\n+#  define UPDATE(check, buf, len) \\\n+    (state->flags ? crc32(check, buf, len) : adler32(check, buf, len))\n+#else\n+#  define UPDATE(check, buf, len) adler32(check, buf, len)\n+#endif\n+\n+/* check macros for header crc */\n+#ifdef GUNZIP\n+#  define CRC2(check, word) \\\n+    do { \\\n+        hbuf[0] = (unsigned char)(word); \\\n+        hbuf[1] = (unsigned char)((word) >> 8); \\\n+        check = crc32(check, hbuf, 2); \\\n+    } while (0)\n+\n+#  define CRC4(check, word) \\\n+    do { \\\n+        hbuf[0] = (unsigned char)(word); \\\n+        hbuf[1] = (unsigned char)((word) >> 8); \\\n+        hbuf[2] = (unsigned char)((word) >> 16); \\\n+        hbuf[3] = (unsigned char)((word) >> 24); \\\n+        check = crc32(check, hbuf, 4); \\\n+    } while (0)\n+#endif\n+\n+/* Load registers with state in inflate() for speed */\n+#define LOAD() \\\n+    do { \\\n+        put = strm->next_out; \\\n+        left = strm->avail_out; \\\n+        next = strm->next_in; \\\n+        have = strm->avail_in; \\\n+        hold = state->hold; \\\n+        bits = state->bits; \\\n+    } while (0)\n+\n+/* Restore state from registers in inflate() */\n+#define RESTORE() \\\n+    do { \\\n+        strm->next_out = put; \\\n+        strm->avail_out = left; \\\n+        strm->next_in = next; \\\n+        strm->avail_in = have; \\\n+        state->hold = hold; \\\n+        state->bits = bits; \\\n+    } while (0)\n+\n+/* Clear the input bit accumulator */\n+#define INITBITS() \\\n+    do { \\\n+        hold = 0; \\\n+        bits = 0; \\\n+    } while (0)\n+\n+/* Get a byte of input into the bit accumulator, or return from inflate()\n+   if there is no input available. */\n+#define PULLBYTE() \\\n+    do { \\\n+        if (have == 0) goto inf_leave; \\\n+        have--; \\\n+        hold += (unsigned long)(*next++) << bits; \\\n+        bits += 8; \\\n+    } while (0)\n+\n+/* Assure that there are at least n bits in the bit accumulator.  If there is\n+   not enough available input to do that, then return from inflate(). */\n+#define NEEDBITS(n) \\\n+    do { \\\n+        while (bits < (unsigned)(n)) \\\n+            PULLBYTE(); \\\n+    } while (0)\n+\n+/* Return the low n bits of the bit accumulator (n < 16) */\n+#define BITS(n) \\\n+    ((unsigned)hold & ((1U << (n)) - 1))\n+\n+/* Remove n bits from the bit accumulator */\n+#define DROPBITS(n) \\\n+    do { \\\n+        hold >>= (n); \\\n+        bits -= (unsigned)(n); \\\n+    } while (0)\n+\n+/* Remove zero to seven bits as needed to go to a byte boundary */\n+#define BYTEBITS() \\\n+    do { \\\n+        hold >>= bits & 7; \\\n+        bits -= bits & 7; \\\n+    } while (0)\n+\n+/*\n+   inflate() uses a state machine to process as much input data and generate as\n+   much output data as possible before returning.  The state machine is\n+   structured roughly as follows:\n+\n+    for (;;) switch (state) {\n+    ...\n+    case STATEn:\n+        if (not enough input data or output space to make progress)\n+            return;\n+        ... make progress ...\n+        state = STATEm;\n+        break;\n+    ...\n+    }\n+\n+   so when inflate() is called again, the same case is attempted again, and\n+   if the appropriate resources are provided, the machine proceeds to the\n+   next state.  The NEEDBITS() macro is usually the way the state evaluates\n+   whether it can proceed or should return.  NEEDBITS() does the return if\n+   the requested bits are not available.  The typical use of the BITS macros\n+   is:\n+\n+        NEEDBITS(n);\n+        ... do something with BITS(n) ...\n+        DROPBITS(n);\n+\n+   where NEEDBITS(n) either returns from inflate() if there isn't enough\n+   input left to load n bits into the accumulator, or it continues.  BITS(n)\n+   gives the low n bits in the accumulator.  When done, DROPBITS(n) drops\n+   the low n bits off the accumulator.  INITBITS() clears the accumulator\n+   and sets the number of available bits to zero.  BYTEBITS() discards just\n+   enough bits to put the accumulator on a byte boundary.  After BYTEBITS()\n+   and a NEEDBITS(8), then BITS(8) would return the next byte in the stream.\n+\n+   NEEDBITS(n) uses PULLBYTE() to get an available byte of input, or to return\n+   if there is no input available.  The decoding of variable length codes uses\n+   PULLBYTE() directly in order to pull just enough bytes to decode the next\n+   code, and no more.\n+\n+   Some states loop until they get enough input, making sure that enough\n+   state information is maintained to continue the loop where it left off\n+   if NEEDBITS() returns in the loop.  For example, want, need, and keep\n+   would all have to actually be part of the saved state in case NEEDBITS()\n+   returns:\n+\n+    case STATEw:\n+        while (want < need) {\n+            NEEDBITS(n);\n+            keep[want++] = BITS(n);\n+            DROPBITS(n);\n+        }\n+        state = STATEx;\n+    case STATEx:\n+\n+   As shown above, if the next state is also the next case, then the break\n+   is omitted.\n+\n+   A state may also return if there is not enough output space available to\n+   complete that state.  Those states are copying stored data, writing a\n+   literal byte, and copying a matching string.\n+\n+   When returning, a \"goto inf_leave\" is used to update the total counters,\n+   update the check value, and determine whether any progress has been made\n+   during that inflate() call in order to return the proper return code.\n+   Progress is defined as a change in either strm->avail_in or strm->avail_out.\n+   When there is a window, goto inf_leave will update the window with the last\n+   output written.  If a goto inf_leave occurs in the middle of decompression\n+   and there is no window currently, goto inf_leave will create one and copy\n+   output to the window for the next call of inflate().\n+\n+   In this implementation, the flush parameter of inflate() only affects the\n+   return code (per zlib.h).  inflate() always writes as much as possible to\n+   strm->next_out, given the space available and the provided input--the effect\n+   documented in zlib.h of Z_SYNC_FLUSH.  Furthermore, inflate() always defers\n+   the allocation of and copying into a sliding window until necessary, which\n+   provides the effect documented in zlib.h for Z_FINISH when the entire input\n+   stream available.  So the only thing the flush parameter actually does is:\n+   when flush is set to Z_FINISH, inflate() cannot return Z_OK.  Instead it\n+   will return Z_BUF_ERROR if it has not reached the end of the stream.\n+ */\n+\n+int ZEXPORT inflate(strm, flush)\n+z_streamp strm;\n+int flush;\n+{\n+    struct inflate_state FAR *state;\n+    z_const unsigned char FAR *next;    /* next input */\n+    unsigned char FAR *put;     /* next output */\n+    unsigned have, left;        /* available input and output */\n+    unsigned long hold;         /* bit buffer */\n+    unsigned bits;              /* bits in bit buffer */\n+    unsigned in, out;           /* save starting available input and output */\n+    unsigned copy;              /* number of stored or match bytes to copy */\n+    unsigned char FAR *from;    /* where to copy match bytes from */\n+    code here;                  /* current decoding table entry */\n+    code last;                  /* parent table entry */\n+    unsigned len;               /* length to copy for repeats, bits to drop */\n+    int ret;                    /* return code */\n+#ifdef GUNZIP\n+    unsigned char hbuf[4];      /* buffer for gzip header crc calculation */\n+#endif\n+    static const unsigned short order[19] = /* permutation of code lengths */\n+        {16, 17, 18, 0, 8, 7, 9, 6, 10, 5, 11, 4, 12, 3, 13, 2, 14, 1, 15};\n+\n+    if (inflateStateCheck(strm) || strm->next_out == Z_NULL ||\n+        (strm->next_in == Z_NULL && strm->avail_in != 0))\n+        return Z_STREAM_ERROR;\n+\n+    state = (struct inflate_state FAR *)strm->state;\n+    if (state->mode == TYPE) state->mode = TYPEDO;      /* skip check */\n+    LOAD();\n+    in = have;\n+    out = left;\n+    ret = Z_OK;\n+    for (;;)\n+        switch (state->mode) {\n+        case HEAD:\n+            if (state->wrap == 0) {\n+                state->mode = TYPEDO;\n+                break;\n+            }\n+            NEEDBITS(16);\n+#ifdef GUNZIP\n+            if ((state->wrap & 2) && hold == 0x8b1f) {  /* gzip header */\n+                if (state->wbits == 0)\n+                    state->wbits = 15;\n+                state->check = crc32(0L, Z_NULL, 0);\n+                CRC2(state->check, hold);\n+                INITBITS();\n+                state->mode = FLAGS;\n+                break;\n+            }\n+            state->flags = 0;           /* expect zlib header */\n+            if (state->head != Z_NULL)\n+                state->head->done = -1;\n+            if (!(state->wrap & 1) ||   /* check if zlib header allowed */\n+#else\n+            if (\n+#endif\n+                ((BITS(8) << 8) + (hold >> 8)) % 31) {\n+                strm->msg = (char *)\"incorrect header check\";\n+                state->mode = BAD;\n+                break;\n+            }\n+            if (BITS(4) != Z_DEFLATED) {\n+                strm->msg = (char *)\"unknown compression method\";\n+                state->mode = BAD;\n+                break;\n+            }\n+            DROPBITS(4);\n+            len = BITS(4) + 8;\n+            if (state->wbits == 0)\n+                state->wbits = len;\n+            if (len > 15 || len > state->wbits) {\n+                strm->msg = (char *)\"invalid window size\";\n+                state->mode = BAD;\n+                break;\n+            }\n+            state->dmax = 1U << len;\n+            Tracev((stderr, \"inflate:   zlib header ok\\n\"));\n+            strm->adler = state->check = adler32(0L, Z_NULL, 0);\n+            state->mode = hold & 0x200 ? DICTID : TYPE;\n+            INITBITS();\n+            break;\n+#ifdef GUNZIP\n+        case FLAGS:\n+            NEEDBITS(16);\n+            state->flags = (int)(hold);\n+            if ((state->flags & 0xff) != Z_DEFLATED) {\n+                strm->msg = (char *)\"unknown compression method\";\n+                state->mode = BAD;\n+                break;\n+            }\n+            if (state->flags & 0xe000) {\n+                strm->msg = (char *)\"unknown header flags set\";\n+                state->mode = BAD;\n+                break;\n+            }\n+            if (state->head != Z_NULL)\n+                state->head->text = (int)((hold >> 8) & 1);\n+            if ((state->flags & 0x0200) && (state->wrap & 4))\n+                CRC2(state->check, hold);\n+            INITBITS();\n+            state->mode = TIME;\n+        case TIME:\n+            NEEDBITS(32);\n+            if (state->head != Z_NULL)\n+                state->head->time = hold;\n+            if ((state->flags & 0x0200) && (state->wrap & 4))\n+                CRC4(state->check, hold);\n+            INITBITS();\n+            state->mode = OS;\n+        case OS:\n+            NEEDBITS(16);\n+            if (state->head != Z_NULL) {\n+                state->head->xflags = (int)(hold & 0xff);\n+                state->head->os = (int)(hold >> 8);\n+            }\n+            if ((state->flags & 0x0200) && (state->wrap & 4))\n+                CRC2(state->check, hold);\n+            INITBITS();\n+            state->mode = EXLEN;\n+        case EXLEN:\n+            if (state->flags & 0x0400) {\n+                NEEDBITS(16);\n+                state->length = (unsigned)(hold);\n+                if (state->head != Z_NULL)\n+                    state->head->extra_len = (unsigned)hold;\n+                if ((state->flags & 0x0200) && (state->wrap & 4))\n+                    CRC2(state->check, hold);\n+                INITBITS();\n+            }\n+            else if (state->head != Z_NULL)\n+                state->head->extra = Z_NULL;\n+            state->mode = EXTRA;\n+        case EXTRA:\n+            if (state->flags & 0x0400) {\n+                copy = state->length;\n+                if (copy > have) copy = have;\n+                if (copy) {\n+                    if (state->head != Z_NULL &&\n+                        state->head->extra != Z_NULL) {\n+                        len = state->head->extra_len - state->length;\n+                        zmemcpy(state->head->extra + len, next,\n+                                len + copy > state->head->extra_max ?\n+                                state->head->extra_max - len : copy);\n+                    }\n+                    if ((state->flags & 0x0200) && (state->wrap & 4))\n+                        state->check = crc32(state->check, next, copy);\n+                    have -= copy;\n+                    next += copy;\n+                    state->length -= copy;\n+                }\n+                if (state->length) goto inf_leave;\n+            }\n+            state->length = 0;\n+            state->mode = NAME;\n+        case NAME:\n+            if (state->flags & 0x0800) {\n+                if (have == 0) goto inf_leave;\n+                copy = 0;\n+                do {\n+                    len = (unsigned)(next[copy++]);\n+                    if (state->head != Z_NULL &&\n+                            state->head->name != Z_NULL &&\n+                            state->length < state->head->name_max)\n+                        state->head->name[state->length++] = (Bytef)len;\n+                } while (len && copy < have);\n+                if ((state->flags & 0x0200) && (state->wrap & 4))\n+                    state->check = crc32(state->check, next, copy);\n+                have -= copy;\n+                next += copy;\n+                if (len) goto inf_leave;\n+            }\n+            else if (state->head != Z_NULL)\n+                state->head->name = Z_NULL;\n+            state->length = 0;\n+            state->mode = COMMENT;\n+        case COMMENT:\n+            if (state->flags & 0x1000) {\n+                if (have == 0) goto inf_leave;\n+                copy = 0;\n+                do {\n+                    len = (unsigned)(next[copy++]);\n+                    if (state->head != Z_NULL &&\n+                            state->head->comment != Z_NULL &&\n+                            state->length < state->head->comm_max)\n+                        state->head->comment[state->length++] = (Bytef)len;\n+                } while (len && copy < have);\n+                if ((state->flags & 0x0200) && (state->wrap & 4))\n+                    state->check = crc32(state->check, next, copy);\n+                have -= copy;\n+                next += copy;\n+                if (len) goto inf_leave;\n+            }\n+            else if (state->head != Z_NULL)\n+                state->head->comment = Z_NULL;\n+            state->mode = HCRC;\n+        case HCRC:\n+            if (state->flags & 0x0200) {\n+                NEEDBITS(16);\n+                if ((state->wrap & 4) && hold != (state->check & 0xffff)) {\n+                    strm->msg = (char *)\"header crc mismatch\";\n+                    state->mode = BAD;\n+                    break;\n+                }\n+                INITBITS();\n+            }\n+            if (state->head != Z_NULL) {\n+                state->head->hcrc = (int)((state->flags >> 9) & 1);\n+                state->head->done = 1;\n+            }\n+            strm->adler = state->check = crc32(0L, Z_NULL, 0);\n+            state->mode = TYPE;\n+            break;\n+#endif\n+        case DICTID:\n+            NEEDBITS(32);\n+            strm->adler = state->check = ZSWAP32(hold);\n+            INITBITS();\n+            state->mode = DICT;\n+        case DICT:\n+            if (state->havedict == 0) {\n+                RESTORE();\n+                return Z_NEED_DICT;\n+            }\n+            strm->adler = state->check = adler32(0L, Z_NULL, 0);\n+            state->mode = TYPE;\n+        case TYPE:\n+            if (flush == Z_BLOCK || flush == Z_TREES) goto inf_leave;\n+        case TYPEDO:\n+            if (state->last) {\n+                BYTEBITS();\n+                state->mode = CHECK;\n+                break;\n+            }\n+            NEEDBITS(3);\n+            state->last = BITS(1);\n+            DROPBITS(1);\n+            switch (BITS(2)) {\n+            case 0:                             /* stored block */\n+                Tracev((stderr, \"inflate:     stored block%s\\n\",\n+                        state->last ? \" (last)\" : \"\"));\n+                state->mode = STORED;\n+                break;\n+            case 1:                             /* fixed block */\n+                fixedtables(state);\n+                Tracev((stderr, \"inflate:     fixed codes block%s\\n\",\n+                        state->last ? \" (last)\" : \"\"));\n+                state->mode = LEN_;             /* decode codes */\n+                if (flush == Z_TREES) {\n+                    DROPBITS(2);\n+                    goto inf_leave;\n+                }\n+                break;\n+            case 2:                             /* dynamic block */\n+                Tracev((stderr, \"inflate:     dynamic codes block%s\\n\",\n+                        state->last ? \" (last)\" : \"\"));\n+                state->mode = TABLE;\n+                break;\n+            case 3:\n+                strm->msg = (char *)\"invalid block type\";\n+                state->mode = BAD;\n+            }\n+            DROPBITS(2);\n+            break;\n+        case STORED:\n+            BYTEBITS();                         /* go to byte boundary */\n+            NEEDBITS(32);\n+            if ((hold & 0xffff) != ((hold >> 16) ^ 0xffff)) {\n+                strm->msg = (char *)\"invalid stored block lengths\";\n+                state->mode = BAD;\n+                break;\n+            }\n+            state->length = (unsigned)hold & 0xffff;\n+            Tracev((stderr, \"inflate:       stored length %u\\n\",\n+                    state->length));\n+            INITBITS();\n+            state->mode = COPY_;\n+            if (flush == Z_TREES) goto inf_leave;\n+        case COPY_:\n+            state->mode = COPY;\n+        case COPY:\n+            copy = state->length;\n+            if (copy) {\n+                if (copy > have) copy = have;\n+                if (copy > left) copy = left;\n+                if (copy == 0) goto inf_leave;\n+                zmemcpy(put, next, copy);\n+                have -= copy;\n+                next += copy;\n+                left -= copy;\n+                put += copy;\n+                state->length -= copy;\n+                break;\n+            }\n+            Tracev((stderr, \"inflate:       stored end\\n\"));\n+            state->mode = TYPE;\n+            break;\n+        case TABLE:\n+            NEEDBITS(14);\n+            state->nlen = BITS(5) + 257;\n+            DROPBITS(5);\n+            state->ndist = BITS(5) + 1;\n+            DROPBITS(5);\n+            state->ncode = BITS(4) + 4;\n+            DROPBITS(4);\n+#ifndef PKZIP_BUG_WORKAROUND\n+            if (state->nlen > 286 || state->ndist > 30) {\n+                strm->msg = (char *)\"too many length or distance symbols\";\n+                state->mode = BAD;\n+                break;\n+            }\n+#endif\n+            Tracev((stderr, \"inflate:       table sizes ok\\n\"));\n+            state->have = 0;\n+            state->mode = LENLENS;\n+        case LENLENS:\n+            while (state->have < state->ncode) {\n+                NEEDBITS(3);\n+                state->lens[order[state->have++]] = (unsigned short)BITS(3);\n+                DROPBITS(3);\n+            }\n+            while (state->have < 19)\n+                state->lens[order[state->have++]] = 0;\n+            state->next = state->codes;\n+            state->lencode = (const code FAR *)(state->next);\n+            state->lenbits = 7;\n+            ret = inflate_table(CODES, state->lens, 19, &(state->next),\n+                                &(state->lenbits), state->work);\n+            if (ret) {\n+                strm->msg = (char *)\"invalid code lengths set\";\n+                state->mode = BAD;\n+                break;\n+            }\n+            Tracev((stderr, \"inflate:       code lengths ok\\n\"));\n+            state->have = 0;\n+            state->mode = CODELENS;\n+        case CODELENS:\n+            while (state->have < state->nlen + state->ndist) {\n+                for (;;) {\n+                    here = state->lencode[BITS(state->lenbits)];\n+                    if ((unsigned)(here.bits) <= bits) break;\n+                    PULLBYTE();\n+                }\n+                if (here.val < 16) {\n+                    DROPBITS(here.bits);\n+                    state->lens[state->have++] = here.val;\n+                }\n+                else {\n+                    if (here.val == 16) {\n+                        NEEDBITS(here.bits + 2);\n+                        DROPBITS(here.bits);\n+                        if (state->have == 0) {\n+                            strm->msg = (char *)\"invalid bit length repeat\";\n+                            state->mode = BAD;\n+                            break;\n+                        }\n+                        len = state->lens[state->have - 1];\n+                        copy = 3 + BITS(2);\n+                        DROPBITS(2);\n+                    }\n+                    else if (here.val == 17) {\n+                        NEEDBITS(here.bits + 3);\n+                        DROPBITS(here.bits);\n+                        len = 0;\n+                        copy = 3 + BITS(3);\n+                        DROPBITS(3);\n+                    }\n+                    else {\n+                        NEEDBITS(here.bits + 7);\n+                        DROPBITS(here.bits);\n+                        len = 0;\n+                        copy = 11 + BITS(7);\n+                        DROPBITS(7);\n+                    }\n+                    if (state->have + copy > state->nlen + state->ndist) {\n+                        strm->msg = (char *)\"invalid bit length repeat\";\n+                        state->mode = BAD;\n+                        break;\n+                    }\n+                    while (copy--)\n+                        state->lens[state->have++] = (unsigned short)len;\n+                }\n+            }\n+\n+            /* handle error breaks in while */\n+            if (state->mode == BAD) break;\n+\n+            /* check for end-of-block code (better have one) */\n+            if (state->lens[256] == 0) {\n+                strm->msg = (char *)\"invalid code -- missing end-of-block\";\n+                state->mode = BAD;\n+                break;\n+            }\n+\n+            /* build code tables -- note: do not change the lenbits or distbits\n+               values here (9 and 6) without reading the comments in inftrees.h\n+               concerning the ENOUGH constants, which depend on those values */\n+            state->next = state->codes;\n+            state->lencode = (const code FAR *)(state->next);\n+            state->lenbits = 9;\n+            ret = inflate_table(LENS, state->lens, state->nlen, &(state->next),\n+                                &(state->lenbits), state->work);\n+            if (ret) {\n+                strm->msg = (char *)\"invalid literal/lengths set\";\n+                state->mode = BAD;\n+                break;\n+            }\n+            state->distcode = (const code FAR *)(state->next);\n+            state->distbits = 6;\n+            ret = inflate_table(DISTS, state->lens + state->nlen, state->ndist,\n+                            &(state->next), &(state->distbits), state->work);\n+            if (ret) {\n+                strm->msg = (char *)\"invalid distances set\";\n+                state->mode = BAD;\n+                break;\n+            }\n+            Tracev((stderr, \"inflate:       codes ok\\n\"));\n+            state->mode = LEN_;\n+            if (flush == Z_TREES) goto inf_leave;\n+        case LEN_:\n+            state->mode = LEN;\n+        case LEN:\n+            if (have >= 6 && left >= 258) {\n+                RESTORE();\n+                inflate_fast(strm, out);\n+                LOAD();\n+                if (state->mode == TYPE)\n+                    state->back = -1;\n+                break;\n+            }\n+            state->back = 0;\n+            for (;;) {\n+                here = state->lencode[BITS(state->lenbits)];\n+                if ((unsigned)(here.bits) <= bits) break;\n+                PULLBYTE();\n+            }\n+            if (here.op && (here.op & 0xf0) == 0) {\n+                last = here;\n+                for (;;) {\n+                    here = state->lencode[last.val +\n+                            (BITS(last.bits + last.op) >> last.bits)];\n+                    if ((unsigned)(last.bits + here.bits) <= bits) break;\n+                    PULLBYTE();\n+                }\n+                DROPBITS(last.bits);\n+                state->back += last.bits;\n+            }\n+            DROPBITS(here.bits);\n+            state->back += here.bits;\n+            state->length = (unsigned)here.val;\n+            if ((int)(here.op) == 0) {\n+                Tracevv((stderr, here.val >= 0x20 && here.val < 0x7f ?\n+                        \"inflate:         literal '%c'\\n\" :\n+                        \"inflate:         literal 0x%02x\\n\", here.val));\n+                state->mode = LIT;\n+                break;\n+            }\n+            if (here.op & 32) {\n+                Tracevv((stderr, \"inflate:         end of block\\n\"));\n+                state->back = -1;\n+                state->mode = TYPE;\n+                break;\n+            }\n+            if (here.op & 64) {\n+                strm->msg = (char *)\"invalid literal/length code\";\n+                state->mode = BAD;\n+                break;\n+            }\n+            state->extra = (unsigned)(here.op) & 15;\n+            state->mode = LENEXT;\n+        case LENEXT:\n+            if (state->extra) {\n+                NEEDBITS(state->extra);\n+                state->length += BITS(state->extra);\n+                DROPBITS(state->extra);\n+                state->back += state->extra;\n+            }\n+            Tracevv((stderr, \"inflate:         length %u\\n\", state->length));\n+            state->was = state->length;\n+            state->mode = DIST;\n+        case DIST:\n+            for (;;) {\n+                here = state->distcode[BITS(state->distbits)];\n+                if ((unsigned)(here.bits) <= bits) break;\n+                PULLBYTE();\n+            }\n+            if ((here.op & 0xf0) == 0) {\n+                last = here;\n+                for (;;) {\n+                    here = state->distcode[last.val +\n+                            (BITS(last.bits + last.op) >> last.bits)];\n+                    if ((unsigned)(last.bits + here.bits) <= bits) break;\n+                    PULLBYTE();\n+                }\n+                DROPBITS(last.bits);\n+                state->back += last.bits;\n+            }\n+            DROPBITS(here.bits);\n+            state->back += here.bits;\n+            if (here.op & 64) {\n+                strm->msg = (char *)\"invalid distance code\";\n+                state->mode = BAD;\n+                break;\n+            }\n+            state->offset = (unsigned)here.val;\n+            state->extra = (unsigned)(here.op) & 15;\n+            state->mode = DISTEXT;\n+        case DISTEXT:\n+            if (state->extra) {\n+                NEEDBITS(state->extra);\n+                state->offset += BITS(state->extra);\n+                DROPBITS(state->extra);\n+                state->back += state->extra;\n+            }\n+#ifdef INFLATE_STRICT\n+            if (state->offset > state->dmax) {\n+                strm->msg = (char *)\"invalid distance too far back\";\n+                state->mode = BAD;\n+                break;\n+            }\n+#endif\n+            Tracevv((stderr, \"inflate:         distance %u\\n\", state->offset));\n+            state->mode = MATCH;\n+        case MATCH:\n+            if (left == 0) goto inf_leave;\n+            copy = out - left;\n+            if (state->offset > copy) {         /* copy from window */\n+                copy = state->offset - copy;\n+                if (copy > state->whave) {\n+                    if (state->sane) {\n+                        strm->msg = (char *)\"invalid distance too far back\";\n+                        state->mode = BAD;\n+                        break;\n+                    }\n+#ifdef INFLATE_ALLOW_INVALID_DISTANCE_TOOFAR_ARRR\n+                    Trace((stderr, \"inflate.c too far\\n\"));\n+                    copy -= state->whave;\n+                    if (copy > state->length) copy = state->length;\n+                    if (copy > left) copy = left;\n+                    left -= copy;\n+                    state->length -= copy;\n+                    do {\n+                        *put++ = 0;\n+                    } while (--copy);\n+                    if (state->length == 0) state->mode = LEN;\n+                    break;\n+#endif\n+                }\n+                if (copy > state->wnext) {\n+                    copy -= state->wnext;\n+                    from = state->window + (state->wsize - copy);\n+                }\n+                else\n+                    from = state->window + (state->wnext - copy);\n+                if (copy > state->length) copy = state->length;\n+            }\n+            else {                              /* copy from output */\n+                from = put - state->offset;\n+                copy = state->length;\n+            }\n+            if (copy > left) copy = left;\n+            left -= copy;\n+            state->length -= copy;\n+            do {\n+                *put++ = *from++;\n+            } while (--copy);\n+            if (state->length == 0) state->mode = LEN;\n+            break;\n+        case LIT:\n+            if (left == 0) goto inf_leave;\n+            *put++ = (unsigned char)(state->length);\n+            left--;\n+            state->mode = LEN;\n+            break;\n+        case CHECK:\n+            if (state->wrap) {\n+                NEEDBITS(32);\n+                out -= left;\n+                strm->total_out += out;\n+                state->total += out;\n+                if ((state->wrap & 4) && out)\n+                    strm->adler = state->check =\n+                        UPDATE(state->check, put - out, out);\n+                out = left;\n+                if ((state->wrap & 4) && (\n+#ifdef GUNZIP\n+                     state->flags ? hold :\n+#endif\n+                     ZSWAP32(hold)) != state->check) {\n+                    strm->msg = (char *)\"incorrect data check\";\n+                    state->mode = BAD;\n+                    break;\n+                }\n+                INITBITS();\n+                Tracev((stderr, \"inflate:   check matches trailer\\n\"));\n+            }\n+#ifdef GUNZIP\n+            state->mode = LENGTH;\n+        case LENGTH:\n+            if (state->wrap && state->flags) {\n+                NEEDBITS(32);\n+                if (hold != (state->total & 0xffffffffUL)) {\n+                    strm->msg = (char *)\"incorrect length check\";\n+                    state->mode = BAD;\n+                    break;\n+                }\n+                INITBITS();\n+                Tracev((stderr, \"inflate:   length matches trailer\\n\"));\n+            }\n+#endif\n+            state->mode = DONE;\n+        case DONE:\n+            ret = Z_STREAM_END;\n+            goto inf_leave;\n+        case BAD:\n+            ret = Z_DATA_ERROR;\n+            goto inf_leave;\n+        case MEM:\n+            return Z_MEM_ERROR;\n+        case SYNC:\n+        default:\n+            return Z_STREAM_ERROR;\n+        }\n+\n+    /*\n+       Return from inflate(), updating the total counts and the check value.\n+       If there was no progress during the inflate() call, return a buffer\n+       error.  Call updatewindow() to create and/or update the window state.\n+       Note: a memory error from inflate() is non-recoverable.\n+     */\n+  inf_leave:\n+    RESTORE();\n+    if (state->wsize || (out != strm->avail_out && state->mode < BAD &&\n+            (state->mode < CHECK || flush != Z_FINISH)))\n+        if (updatewindow(strm, strm->next_out, out - strm->avail_out)) {\n+            state->mode = MEM;\n+            return Z_MEM_ERROR;\n+        }\n+    in -= strm->avail_in;\n+    out -= strm->avail_out;\n+    strm->total_in += in;\n+    strm->total_out += out;\n+    state->total += out;\n+    if ((state->wrap & 4) && out)\n+        strm->adler = state->check =\n+            UPDATE(state->check, strm->next_out - out, out);\n+    strm->data_type = (int)state->bits + (state->last ? 64 : 0) +\n+                      (state->mode == TYPE ? 128 : 0) +\n+                      (state->mode == LEN_ || state->mode == COPY_ ? 256 : 0);\n+    if (((in == 0 && out == 0) || flush == Z_FINISH) && ret == Z_OK)\n+        ret = Z_BUF_ERROR;\n+    return ret;\n+}\n+\n+int ZEXPORT inflateEnd(strm)\n+z_streamp strm;\n+{\n+    struct inflate_state FAR *state;\n+    if (inflateStateCheck(strm))\n+        return Z_STREAM_ERROR;\n+    state = (struct inflate_state FAR *)strm->state;\n+    if (state->window != Z_NULL) ZFREE(strm, state->window);\n+    ZFREE(strm, strm->state);\n+    strm->state = Z_NULL;\n+    Tracev((stderr, \"inflate: end\\n\"));\n+    return Z_OK;\n+}\n+\n+int ZEXPORT inflateGetDictionary(strm, dictionary, dictLength)\n+z_streamp strm;\n+Bytef *dictionary;\n+uInt *dictLength;\n+{\n+    struct inflate_state FAR *state;\n+\n+    /* check state */\n+    if (inflateStateCheck(strm)) return Z_STREAM_ERROR;\n+    state = (struct inflate_state FAR *)strm->state;\n+\n+    /* copy dictionary */\n+    if (state->whave && dictionary != Z_NULL) {\n+        zmemcpy(dictionary, state->window + state->wnext,\n+                state->whave - state->wnext);\n+        zmemcpy(dictionary + state->whave - state->wnext,\n+                state->window, state->wnext);\n+    }\n+    if (dictLength != Z_NULL)\n+        *dictLength = state->whave;\n+    return Z_OK;\n+}\n+\n+int ZEXPORT inflateSetDictionary(strm, dictionary, dictLength)\n+z_streamp strm;\n+const Bytef *dictionary;\n+uInt dictLength;\n+{\n+    struct inflate_state FAR *state;\n+    unsigned long dictid;\n+    int ret;\n+\n+    /* check state */\n+    if (inflateStateCheck(strm)) return Z_STREAM_ERROR;\n+    state = (struct inflate_state FAR *)strm->state;\n+    if (state->wrap != 0 && state->mode != DICT)\n+        return Z_STREAM_ERROR;\n+\n+    /* check for correct dictionary identifier */\n+    if (state->mode == DICT) {\n+        dictid = adler32(0L, Z_NULL, 0);\n+        dictid = adler32(dictid, dictionary, dictLength);\n+        if (dictid != state->check)\n+            return Z_DATA_ERROR;\n+    }\n+\n+    /* copy dictionary to window using updatewindow(), which will amend the\n+       existing dictionary if appropriate */\n+    ret = updatewindow(strm, dictionary + dictLength, dictLength);\n+    if (ret) {\n+        state->mode = MEM;\n+        return Z_MEM_ERROR;\n+    }\n+    state->havedict = 1;\n+    Tracev((stderr, \"inflate:   dictionary set\\n\"));\n+    return Z_OK;\n+}\n+\n+int ZEXPORT inflateGetHeader(strm, head)\n+z_streamp strm;\n+gz_headerp head;\n+{\n+    struct inflate_state FAR *state;\n+\n+    /* check state */\n+    if (inflateStateCheck(strm)) return Z_STREAM_ERROR;\n+    state = (struct inflate_state FAR *)strm->state;\n+    if ((state->wrap & 2) == 0) return Z_STREAM_ERROR;\n+\n+    /* save header structure */\n+    state->head = head;\n+    head->done = 0;\n+    return Z_OK;\n+}\n+\n+/*\n+   Search buf[0..len-1] for the pattern: 0, 0, 0xff, 0xff.  Return when found\n+   or when out of input.  When called, *have is the number of pattern bytes\n+   found in order so far, in 0..3.  On return *have is updated to the new\n+   state.  If on return *have equals four, then the pattern was found and the\n+   return value is how many bytes were read including the last byte of the\n+   pattern.  If *have is less than four, then the pattern has not been found\n+   yet and the return value is len.  In the latter case, syncsearch() can be\n+   called again with more data and the *have state.  *have is initialized to\n+   zero for the first call.\n+ */\n+local unsigned syncsearch(have, buf, len)\n+unsigned FAR *have;\n+const unsigned char FAR *buf;\n+unsigned len;\n+{\n+    unsigned got;\n+    unsigned next;\n+\n+    got = *have;\n+    next = 0;\n+    while (next < len && got < 4) {\n+        if ((int)(buf[next]) == (got < 2 ? 0 : 0xff))\n+            got++;\n+        else if (buf[next])\n+            got = 0;\n+        else\n+            got = 4 - got;\n+        next++;\n+    }\n+    *have = got;\n+    return next;\n+}\n+\n+int ZEXPORT inflateSync(strm)\n+z_streamp strm;\n+{\n+    unsigned len;               /* number of bytes to look at or looked at */\n+    unsigned long in, out;      /* temporary to save total_in and total_out */\n+    unsigned char buf[4];       /* to restore bit buffer to byte string */\n+    struct inflate_state FAR *state;\n+\n+    /* check parameters */\n+    if (inflateStateCheck(strm)) return Z_STREAM_ERROR;\n+    state = (struct inflate_state FAR *)strm->state;\n+    if (strm->avail_in == 0 && state->bits < 8) return Z_BUF_ERROR;\n+\n+    /* if first time, start search in bit buffer */\n+    if (state->mode != SYNC) {\n+        state->mode = SYNC;\n+        state->hold <<= state->bits & 7;\n+        state->bits -= state->bits & 7;\n+        len = 0;\n+        while (state->bits >= 8) {\n+            buf[len++] = (unsigned char)(state->hold);\n+            state->hold >>= 8;\n+            state->bits -= 8;\n+        }\n+        state->have = 0;\n+        syncsearch(&(state->have), buf, len);\n+    }\n+\n+    /* search available input */\n+    len = syncsearch(&(state->have), strm->next_in, strm->avail_in);\n+    strm->avail_in -= len;\n+    strm->next_in += len;\n+    strm->total_in += len;\n+\n+    /* return no joy or set up to restart inflate() on a new block */\n+    if (state->have != 4) return Z_DATA_ERROR;\n+    in = strm->total_in;  out = strm->total_out;\n+    inflateReset(strm);\n+    strm->total_in = in;  strm->total_out = out;\n+    state->mode = TYPE;\n+    return Z_OK;\n+}\n+\n+/*\n+   Returns true if inflate is currently at the end of a block generated by\n+   Z_SYNC_FLUSH or Z_FULL_FLUSH. This function is used by one PPP\n+   implementation to provide an additional safety check. PPP uses\n+   Z_SYNC_FLUSH but removes the length bytes of the resulting empty stored\n+   block. When decompressing, PPP checks that at the end of input packet,\n+   inflate is waiting for these length bytes.\n+ */\n+int ZEXPORT inflateSyncPoint(strm)\n+z_streamp strm;\n+{\n+    struct inflate_state FAR *state;\n+\n+    if (inflateStateCheck(strm)) return Z_STREAM_ERROR;\n+    state = (struct inflate_state FAR *)strm->state;\n+    return state->mode == STORED && state->bits == 0;\n+}\n+\n+int ZEXPORT inflateCopy(dest, source)\n+z_streamp dest;\n+z_streamp source;\n+{\n+    struct inflate_state FAR *state;\n+    struct inflate_state FAR *copy;\n+    unsigned char FAR *window;\n+    unsigned wsize;\n+\n+    /* check input */\n+    if (inflateStateCheck(source) || dest == Z_NULL)\n+        return Z_STREAM_ERROR;\n+    state = (struct inflate_state FAR *)source->state;\n+\n+    /* allocate space */\n+    copy = (struct inflate_state FAR *)\n+           ZALLOC(source, 1, sizeof(struct inflate_state));\n+    if (copy == Z_NULL) return Z_MEM_ERROR;\n+    window = Z_NULL;\n+    if (state->window != Z_NULL) {\n+        window = (unsigned char FAR *)\n+                 ZALLOC(source, 1U << state->wbits, sizeof(unsigned char));\n+        if (window == Z_NULL) {\n+            ZFREE(source, copy);\n+            return Z_MEM_ERROR;\n+        }\n+    }\n+\n+    /* copy state */\n+    zmemcpy((voidpf)dest, (voidpf)source, sizeof(z_stream));\n+    zmemcpy((voidpf)copy, (voidpf)state, sizeof(struct inflate_state));\n+    copy->strm = dest;\n+    if (state->lencode >= state->codes &&\n+        state->lencode <= state->codes + ENOUGH - 1) {\n+        copy->lencode = copy->codes + (state->lencode - state->codes);\n+        copy->distcode = copy->codes + (state->distcode - state->codes);\n+    }\n+    copy->next = copy->codes + (state->next - state->codes);\n+    if (window != Z_NULL) {\n+        wsize = 1U << state->wbits;\n+        zmemcpy(window, state->window, wsize);\n+    }\n+    copy->window = window;\n+    dest->state = (struct internal_state FAR *)copy;\n+    return Z_OK;\n+}\n+\n+int ZEXPORT inflateUndermine(strm, subvert)\n+z_streamp strm;\n+int subvert;\n+{\n+    struct inflate_state FAR *state;\n+\n+    if (inflateStateCheck(strm)) return Z_STREAM_ERROR;\n+    state = (struct inflate_state FAR *)strm->state;\n+#ifdef INFLATE_ALLOW_INVALID_DISTANCE_TOOFAR_ARRR\n+    state->sane = !subvert;\n+    return Z_OK;\n+#else\n+    (void)subvert;\n+    state->sane = 1;\n+    return Z_DATA_ERROR;\n+#endif\n+}\n+\n+int ZEXPORT inflateValidate(strm, check)\n+z_streamp strm;\n+int check;\n+{\n+    struct inflate_state FAR *state;\n+\n+    if (inflateStateCheck(strm)) return Z_STREAM_ERROR;\n+    state = (struct inflate_state FAR *)strm->state;\n+    if (check)\n+        state->wrap |= 4;\n+    else\n+        state->wrap &= ~4;\n+    return Z_OK;\n+}\n+\n+long ZEXPORT inflateMark(strm)\n+z_streamp strm;\n+{\n+    struct inflate_state FAR *state;\n+\n+    if (inflateStateCheck(strm))\n+        return -(1L << 16);\n+    state = (struct inflate_state FAR *)strm->state;\n+    return (long)(((unsigned long)((long)state->back)) << 16) +\n+        (state->mode == COPY ? state->length :\n+            (state->mode == MATCH ? state->was - state->length : 0));\n+}\n+\n+unsigned long ZEXPORT inflateCodesUsed(strm)\n+z_streamp strm;\n+{\n+    struct inflate_state FAR *state;\n+    if (inflateStateCheck(strm)) return (unsigned long)-1;\n+    state = (struct inflate_state FAR *)strm->state;\n+    return (unsigned long)(state->next - state->codes);\n+}\n"
  },
  {
    "path": "package/libs/zlib/patches/003-arm-specific-optimisations-for-inflate.patch",
    "content": "From 247147654fe5cd11cf15d8dff91440405ea57040 Mon Sep 17 00:00:00 2001\nFrom: Simon Hosie <simon.hosie@arm.com>\nDate: Wed, 12 Apr 2017 15:44:21 -0700\nSubject: [PATCH 2/2] Inflate using wider loads and stores\n\nIn inflate_fast() the output pointer always has plenty of room to write. This\nmeans that so long as the target is capable, wide un-aligned loads and stores\ncan be used to transfer several bytes at once. When the reference distance is\ntoo short simply unroll the data a little to increase the distance.\n\nChange-Id: I59854eb25d2b1e43561c8a2afaf9175bf10cf674\n---\n contrib/arm/chunkcopy.h | 279 ++++++++++++++++++++++++++++++++++++++++++++++++\n contrib/arm/inffast.c   |  96 +++++++----------\n contrib/arm/inflate.c   |  22 ++--\n 3 files changed, 335 insertions(+), 62 deletions(-)\n create mode 100644 contrib/arm/chunkcopy.h\n\ndiff --git a/contrib/arm/chunkcopy.h b/contrib/arm/chunkcopy.h\nnew file mode 100644\nindex 00000000..2d6fd6f9\n--- /dev/null\n+++ b/contrib/arm/chunkcopy.h\n@@ -0,0 +1,279 @@\n+/* chunkcopy.h -- fast copies and sets\n+ * Copyright (C) 2017 ARM, Inc.\n+ * For conditions of distribution and use, see copyright notice in zlib.h\n+ */\n+\n+#ifndef CHUNKCOPY_H\n+#define CHUNKCOPY_H\n+\n+#include \"zutil.h\"\n+#include <arm_neon.h>\n+\n+#if __STDC_VERSION__ >= 199901L\n+#define Z_RESTRICT restrict\n+#else\n+#define Z_RESTRICT\n+#endif\n+\n+typedef uint8x16_t chunkcopy_chunk_t;\n+#define CHUNKCOPY_CHUNK_SIZE sizeof(chunkcopy_chunk_t)\n+\n+/*\n+   Ask the compiler to perform a wide, unaligned load with an machine\n+   instruction appropriate for the chunkcopy_chunk_t type.\n+ */\n+static inline chunkcopy_chunk_t loadchunk(const unsigned char FAR *s) {\n+    chunkcopy_chunk_t c;\n+    __builtin_memcpy(&c, s, sizeof(c));\n+    return c;\n+}\n+\n+/*\n+   Ask the compiler to perform a wide, unaligned store with an machine\n+   instruction appropriate for the chunkcopy_chunk_t type.\n+ */\n+static inline void storechunk(unsigned char FAR *d, chunkcopy_chunk_t c) {\n+    __builtin_memcpy(d, &c, sizeof(c));\n+}\n+\n+/*\n+   Perform a memcpy-like operation, but assume that length is non-zero and that\n+   it's OK to overwrite at least CHUNKCOPY_CHUNK_SIZE bytes of output even if\n+   the length is shorter than this.\n+\n+   It also guarantees that it will properly unroll the data if the distance\n+   between `out` and `from` is at least CHUNKCOPY_CHUNK_SIZE, which we rely on\n+   in chunkcopy_relaxed().\n+\n+   Aside from better memory bus utilisation, this means that short copies\n+   (CHUNKCOPY_CHUNK_SIZE bytes or fewer) will fall straight through the loop\n+   without iteration, which will hopefully make the branch prediction more\n+   reliable.\n+ */\n+static inline unsigned char FAR *chunkcopy_core(unsigned char FAR *out,\n+                                                const unsigned char FAR *from,\n+                                                unsigned len) {\n+    int bump = (--len % CHUNKCOPY_CHUNK_SIZE) + 1;\n+    storechunk(out, loadchunk(from));\n+    out += bump;\n+    from += bump;\n+    len /= CHUNKCOPY_CHUNK_SIZE;\n+    while (len-- > 0) {\n+        storechunk(out, loadchunk(from));\n+        out += CHUNKCOPY_CHUNK_SIZE;\n+        from += CHUNKCOPY_CHUNK_SIZE;\n+    }\n+    return out;\n+}\n+\n+/*\n+   Like chunkcopy_core, but avoid writing beyond of legal output.\n+\n+   Accepts an additional pointer to the end of safe output.  A generic safe\n+   copy would use (out + len), but it's normally the case that the end of the\n+   output buffer is beyond the end of the current copy, and this can still be\n+   exploited.\n+ */\n+static inline unsigned char FAR *chunkcopy_core_safe(unsigned char FAR *out,\n+                                                     const unsigned char FAR * from,\n+                                                     unsigned len,\n+                                                     unsigned char FAR *limit) {\n+    Assert(out + len <= limit, \"chunk copy exceeds safety limit\");\n+    if (limit - out < CHUNKCOPY_CHUNK_SIZE) {\n+        const unsigned char FAR * Z_RESTRICT rfrom = from;\n+        if (len & 8) { __builtin_memcpy(out, rfrom, 8); out += 8; rfrom += 8; }\n+        if (len & 4) { __builtin_memcpy(out, rfrom, 4); out += 4; rfrom += 4; }\n+        if (len & 2) { __builtin_memcpy(out, rfrom, 2); out += 2; rfrom += 2; }\n+        if (len & 1) { *out++ = *rfrom++; }\n+        return out;\n+    }\n+    return chunkcopy_core(out, from, len);\n+}\n+\n+/*\n+   Perform short copies until distance can be rewritten as being at least\n+   CHUNKCOPY_CHUNK_SIZE.\n+\n+   This assumes that it's OK to overwrite at least the first\n+   2*CHUNKCOPY_CHUNK_SIZE bytes of output even if the copy is shorter than\n+   this.  This assumption holds within inflate_fast() which starts every\n+   iteration with at least 258 bytes of output space available (258 being the\n+   maximum length output from a single token; see inffast.c).\n+ */\n+static inline unsigned char FAR *chunkunroll_relaxed(unsigned char FAR *out,\n+                                                     unsigned FAR *dist,\n+                                                     unsigned FAR *len) {\n+    const unsigned char FAR *from = out - *dist;\n+    while (*dist < *len && *dist < CHUNKCOPY_CHUNK_SIZE) {\n+        storechunk(out, loadchunk(from));\n+        out += *dist;\n+        *len -= *dist;\n+        *dist += *dist;\n+    }\n+    return out;\n+}\n+\n+\n+static inline uint8x16_t chunkset_vld1q_dup_u8x8(const unsigned char FAR * Z_RESTRICT from) {\n+#if defined(__clang__) || defined(__aarch64__)\n+    return vreinterpretq_u8_u64(vld1q_dup_u64((void *)from));\n+#else\n+    /* 32-bit GCC uses an alignment hint for vld1q_dup_u64, even when given a\n+     * void pointer, so here's an alternate implementation.\n+     */\n+    uint8x8_t h = vld1_u8(from);\n+    return vcombine_u8(h, h);\n+#endif\n+}\n+\n+/*\n+   Perform an overlapping copy which behaves as a memset() operation, but\n+   supporting periods other than one, and assume that length is non-zero and\n+   that it's OK to overwrite at least CHUNKCOPY_CHUNK_SIZE*3 bytes of output\n+   even if the length is shorter than this.\n+ */\n+static inline unsigned char FAR *chunkset_core(unsigned char FAR *out,\n+                                               unsigned period,\n+                                               unsigned len) {\n+    uint8x16_t f;\n+    int bump = ((len - 1) % sizeof(f)) + 1;\n+\n+    switch (period) {\n+    case 1:\n+        f = vld1q_dup_u8(out - 1);\n+        vst1q_u8(out, f);\n+        out += bump;\n+        len -= bump;\n+        while (len > 0) {\n+            vst1q_u8(out, f);\n+            out += sizeof(f);\n+            len -= sizeof(f);\n+        }\n+        return out;\n+    case 2:\n+        f = vreinterpretq_u8_u16(vld1q_dup_u16((void *)(out - 2)));\n+        vst1q_u8(out, f);\n+        out += bump;\n+        len -= bump;\n+        if (len > 0) {\n+            f = vreinterpretq_u8_u16(vld1q_dup_u16((void *)(out - 2)));\n+            do {\n+                vst1q_u8(out, f);\n+                out += sizeof(f);\n+                len -= sizeof(f);\n+            } while (len > 0);\n+        }\n+        return out;\n+    case 4:\n+        f = vreinterpretq_u8_u32(vld1q_dup_u32((void *)(out - 4)));\n+        vst1q_u8(out, f);\n+        out += bump;\n+        len -= bump;\n+        if (len > 0) {\n+            f = vreinterpretq_u8_u32(vld1q_dup_u32((void *)(out - 4)));\n+            do {\n+                vst1q_u8(out, f);\n+                out += sizeof(f);\n+                len -= sizeof(f);\n+            } while (len > 0);\n+        }\n+        return out;\n+    case 8:\n+        f = chunkset_vld1q_dup_u8x8(out - 8);\n+        vst1q_u8(out, f);\n+        out += bump;\n+        len -= bump;\n+        if (len > 0) {\n+            f = chunkset_vld1q_dup_u8x8(out - 8);\n+            do {\n+                vst1q_u8(out, f);\n+                out += sizeof(f);\n+                len -= sizeof(f);\n+            } while (len > 0);\n+        }\n+        return out;\n+    }\n+    out = chunkunroll_relaxed(out, &period, &len);\n+    return chunkcopy_core(out, out - period, len);\n+}\n+\n+/*\n+   Perform a memcpy-like operation, but assume that length is non-zero and that\n+   it's OK to overwrite at least CHUNKCOPY_CHUNK_SIZE bytes of output even if\n+   the length is shorter than this.\n+\n+   Unlike chunkcopy_core() above, no guarantee is made regarding the behaviour\n+   of overlapping buffers, regardless of the distance between the pointers.\n+   This is reflected in the `restrict`-qualified pointers, allowing the\n+   compiler to reorder loads and stores.\n+ */\n+static inline unsigned char FAR *chunkcopy_relaxed(unsigned char FAR * Z_RESTRICT out,\n+                                                   const unsigned char FAR * Z_RESTRICT from,\n+                                                   unsigned len) {\n+    return chunkcopy_core(out, from, len);\n+}\n+\n+/*\n+   Like chunkcopy_relaxed, but avoid writing beyond of legal output.\n+\n+   Unlike chunkcopy_core_safe() above, no guarantee is made regarding the\n+   behaviour of overlapping buffers, regardless of the distance between the\n+   pointers.  This is reflected in the `restrict`-qualified pointers, allowing\n+   the compiler to reorder loads and stores.\n+\n+   Accepts an additional pointer to the end of safe output.  A generic safe\n+   copy would use (out + len), but it's normally the case that the end of the\n+   output buffer is beyond the end of the current copy, and this can still be\n+   exploited.\n+ */\n+static inline unsigned char FAR *chunkcopy_safe(unsigned char FAR *out,\n+                                                const unsigned char FAR * Z_RESTRICT from,\n+                                                unsigned len,\n+                                                unsigned char FAR *limit) {\n+    Assert(out + len <= limit, \"chunk copy exceeds safety limit\");\n+    return chunkcopy_core_safe(out, from, len, limit);\n+}\n+\n+/*\n+   Perform chunky copy within the same buffer, where the source and destination\n+   may potentially overlap.\n+\n+   Assumes that len > 0 on entry, and that it's safe to write at least\n+   CHUNKCOPY_CHUNK_SIZE*3 bytes to the output.\n+ */\n+static inline unsigned char FAR *chunkcopy_lapped_relaxed(unsigned char FAR *out,\n+                                                          unsigned dist,\n+                                                          unsigned len) {\n+    if (dist < len && dist < CHUNKCOPY_CHUNK_SIZE) {\n+        return chunkset_core(out, dist, len);\n+    }\n+    return chunkcopy_core(out, out - dist, len);\n+}\n+\n+/*\n+   Behave like chunkcopy_lapped_relaxed, but avoid writing beyond of legal output.\n+\n+   Accepts an additional pointer to the end of safe output.  A generic safe\n+   copy would use (out + len), but it's normally the case that the end of the\n+   output buffer is beyond the end of the current copy, and this can still be\n+   exploited.\n+ */\n+static inline unsigned char FAR *chunkcopy_lapped_safe(unsigned char FAR *out,\n+                                                       unsigned dist,\n+                                                       unsigned len,\n+                                                       unsigned char FAR *limit) {\n+    Assert(out + len <= limit, \"chunk copy exceeds safety limit\");\n+    if (limit - out < CHUNKCOPY_CHUNK_SIZE * 3) {\n+        /* TODO: try harder to optimise this */\n+        while (len-- > 0) {\n+            *out = *(out - dist);\n+            out++;\n+        }\n+        return out;\n+    }\n+    return chunkcopy_lapped_relaxed(out, dist, len);\n+}\n+\n+#undef Z_RESTRICT\n+\n+#endif /* CHUNKCOPY_H */\ndiff --git a/contrib/arm/inffast.c b/contrib/arm/inffast.c\nindex 0dbd1dbc..f7f50071 100644\n--- a/contrib/arm/inffast.c\n+++ b/contrib/arm/inffast.c\n@@ -7,6 +7,7 @@\n #include \"inftrees.h\"\n #include \"inflate.h\"\n #include \"inffast.h\"\n+#include \"chunkcopy.h\"\n \n #ifdef ASMINF\n #  pragma message(\"Assembler code may have bugs -- use at your own risk\")\n@@ -57,6 +58,7 @@ unsigned start;         /* inflate()'s starting value for strm->avail_out */\n     unsigned char FAR *out;     /* local strm->next_out */\n     unsigned char FAR *beg;     /* inflate()'s initial strm->next_out */\n     unsigned char FAR *end;     /* while out < end, enough space available */\n+    unsigned char FAR *limit;   /* safety limit for chunky copies */\n #ifdef INFLATE_STRICT\n     unsigned dmax;              /* maximum distance from zlib header */\n #endif\n@@ -84,12 +86,13 @@ unsigned start;         /* inflate()'s starting value for strm->avail_out */\n     out = strm->next_out;\n     beg = out - (start - strm->avail_out);\n     end = out + (strm->avail_out - 257);\n+    limit = out + strm->avail_out;\n #ifdef INFLATE_STRICT\n     dmax = state->dmax;\n #endif\n     wsize = state->wsize;\n     whave = state->whave;\n-    wnext = state->wnext;\n+    wnext = (state->wnext == 0 && whave >= wsize) ? wsize : state->wnext;\n     window = state->window;\n     hold = state->hold;\n     bits = state->bits;\n@@ -197,70 +200,51 @@ unsigned start;         /* inflate()'s starting value for strm->avail_out */\n #endif\n                     }\n                     from = window;\n-                    if (wnext == 0) {           /* very common case */\n-                        from += wsize - op;\n-                        if (op < len) {         /* some from window */\n-                            len -= op;\n-                            do {\n-                                *out++ = *from++;\n-                            } while (--op);\n-                            from = out - dist;  /* rest from output */\n-                        }\n+                    if (wnext >= op) {          /* contiguous in window */\n+                        from += wnext - op;\n                     }\n-                    else if (wnext < op) {      /* wrap around window */\n-                        from += wsize + wnext - op;\n+                    else {                      /* wrap around window */\n                         op -= wnext;\n+                        from += wsize - op;\n                         if (op < len) {         /* some from end of window */\n                             len -= op;\n-                            do {\n-                                *out++ = *from++;\n-                            } while (--op);\n-                            from = window;\n-                            if (wnext < len) {  /* some from start of window */\n-                                op = wnext;\n-                                len -= op;\n-                                do {\n-                                    *out++ = *from++;\n-                                } while (--op);\n-                                from = out - dist;      /* rest from output */\n-                            }\n+                            out = chunkcopy_safe(out, from, op, limit);\n+                            from = window;      /* more from start of window */\n+                            op = wnext;\n+                            /* This (rare) case can create a situation where\n+                               the first chunkcopy below must be checked.\n+                             */\n                         }\n                     }\n-                    else {                      /* contiguous in window */\n-                        from += wnext - op;\n-                        if (op < len) {         /* some from window */\n-                            len -= op;\n-                            do {\n-                                *out++ = *from++;\n-                            } while (--op);\n-                            from = out - dist;  /* rest from output */\n-                        }\n-                    }\n-                    while (len > 2) {\n-                        *out++ = *from++;\n-                        *out++ = *from++;\n-                        *out++ = *from++;\n-                        len -= 3;\n-                    }\n-                    if (len) {\n-                        *out++ = *from++;\n-                        if (len > 1)\n-                            *out++ = *from++;\n+                    if (op < len) {             /* still need some from output */\n+                        out = chunkcopy_safe(out, from, op, limit);\n+                        len -= op;\n+                        /* When dist is small the amount of data that can be\n+                           copied from the window is also small, and progress\n+                           towards the dangerous end of the output buffer is\n+                           also small.  This means that for trivial memsets and\n+                           for chunkunroll_relaxed() a safety check is\n+                           unnecessary.  However, these conditions may not be\n+                           entered at all, and in that case it's possible that\n+                           the main copy is near the end.\n+                          */\n+                        out = chunkunroll_relaxed(out, &dist, &len);\n+                        out = chunkcopy_safe(out, out - dist, len, limit);\n+                    } else {\n+                        /* from points to window, so there is no risk of\n+                           overlapping pointers requiring memset-like behaviour\n+                         */\n+                        out = chunkcopy_safe(out, from, len, limit);\n                     }\n                 }\n                 else {\n-                    from = out - dist;          /* copy direct from output */\n-                    do {                        /* minimum length is three */\n-                        *out++ = *from++;\n-                        *out++ = *from++;\n-                        *out++ = *from++;\n-                        len -= 3;\n-                    } while (len > 2);\n-                    if (len) {\n-                        *out++ = *from++;\n-                        if (len > 1)\n-                            *out++ = *from++;\n-                    }\n+                    /* Whole reference is in range of current output.  No\n+                       range checks are necessary because we start with room\n+                       for at least 258 bytes of output, so unroll and roundoff\n+                       operations can write beyond `out+len` so long as they\n+                       stay within 258 bytes of `out`.\n+                     */\n+                    out = chunkcopy_lapped_relaxed(out, dist, len);\n                 }\n             }\n             else if ((op & 64) == 0) {          /* 2nd level distance code */\ndiff --git a/contrib/arm/inflate.c b/contrib/arm/inflate.c\nindex ac333e8c..e40322c3 100644\n--- a/contrib/arm/inflate.c\n+++ b/contrib/arm/inflate.c\n@@ -84,6 +84,7 @@\n #include \"inftrees.h\"\n #include \"inflate.h\"\n #include \"inffast.h\"\n+#include \"contrib/arm/chunkcopy.h\"\n \n #ifdef MAKEFIXED\n #  ifndef BUILDFIXED\n@@ -405,10 +406,20 @@ unsigned copy;\n \n     /* if it hasn't been done already, allocate space for the window */\n     if (state->window == Z_NULL) {\n+        unsigned wsize = 1U << state->wbits;\n         state->window = (unsigned char FAR *)\n-                        ZALLOC(strm, 1U << state->wbits,\n+                        ZALLOC(strm, wsize + CHUNKCOPY_CHUNK_SIZE,\n                                sizeof(unsigned char));\n         if (state->window == Z_NULL) return 1;\n+#ifdef INFLATE_CLEAR_UNUSED_UNDEFINED\n+        /* Copies from the overflow portion of this buffer are undefined and\n+           may cause analysis tools to raise a warning if we don't initialize\n+           it.  However, this undefined data overwrites other undefined data\n+           and is subsequently either overwritten or left deliberately\n+           undefined at the end of decode; so there's really no point.\n+         */\n+        memset(state->window + wsize, 0, CHUNKCOPY_CHUNK_SIZE);\n+#endif\n     }\n \n     /* if window not in use yet, initialize */\n@@ -1175,17 +1186,16 @@ int flush;\n                 else\n                     from = state->window + (state->wnext - copy);\n                 if (copy > state->length) copy = state->length;\n+                if (copy > left) copy = left;\n+                put = chunkcopy_safe(put, from, copy, put + left);\n             }\n             else {                              /* copy from output */\n-                from = put - state->offset;\n                 copy = state->length;\n+                if (copy > left) copy = left;\n+                put = chunkcopy_lapped_safe(put, state->offset, copy, put + left);\n             }\n-            if (copy > left) copy = left;\n             left -= copy;\n             state->length -= copy;\n-            do {\n-                *put++ = *from++;\n-            } while (--copy);\n             if (state->length == 0) state->mode = LEN;\n             break;\n         case LIT:\n"
  },
  {
    "path": "package/libs/zlib/patches/004-attach-sourcefiles-in-patch-002-to-buildsystem.patch",
    "content": "diff --git a/CMakeLists.txt b/CMakeLists.txt\nindex 8e75f66..24d7329 100644\n--- a/CMakeLists.txt\n+++ b/CMakeLists.txt\n@@ -95,34 +95,67 @@ set(ZLIB_PUBLIC_HDRS\n     ${CMAKE_CURRENT_BINARY_DIR}/zconf.h\n     zlib.h\n )\n-set(ZLIB_PRIVATE_HDRS\n-    crc32.h\n-    deflate.h\n-    gzguts.h\n-    inffast.h\n-    inffixed.h\n-    inflate.h\n-    inftrees.h\n-    trees.h\n-    zutil.h\n-)\n-set(ZLIB_SRCS\n-    adler32.c\n-    compress.c\n-    crc32.c\n-    deflate.c\n-    gzclose.c\n-    gzlib.c\n-    gzread.c\n-    gzwrite.c\n-    inflate.c\n-    infback.c\n-    inftrees.c\n-    inffast.c\n-    trees.c\n-    uncompr.c\n-    zutil.c\n-)\n+\n+if(ARMv8)\n+    set(ZLIB_PRIVATE_HDRS\n+\tcrc32.h\n+\tdeflate.h\n+\tgzguts.h\n+\tinffast.h\n+\tinffixed.h\n+\tinflate.h\n+\tinftrees.h\n+\ttrees.h\n+\tzutil.h\n+\tcontrib/arm/chunkcopy.h\n+    )\n+    set(ZLIB_SRCS\n+\tadler32.c\n+\tcompress.c\n+\tcrc32.c\n+\tdeflate.c\n+\tgzclose.c\n+\tgzlib.c\n+\tgzread.c\n+\tgzwrite.c\n+\tinfback.c\n+\tinftrees.c\n+\tcontrib/arm/inflate.c\n+\tcontrib/arm/inffast.c\n+\ttrees.c\n+\tuncompr.c\n+\tzutil.c\n+    )\n+    else()\n+    set(ZLIB_PRIVATE_HDRS\n+\tcrc32.h\n+\tdeflate.h\n+\tgzguts.h\n+\tinffast.h\n+\tinffixed.h\n+\tinflate.h\n+\tinftrees.h\n+\ttrees.h\n+\tzutil.h\n+    )\n+    set(ZLIB_SRCS\n+\tadler32.c\n+\tcompress.c\n+\tcrc32.c\n+\tdeflate.c\n+\tgzclose.c\n+\tgzlib.c\n+\tgzread.c\n+\tgzwrite.c\n+\tinflate.c\n+\tinfback.c\n+\tinftrees.c\n+\tinffast.c\n+\ttrees.c\n+\tuncompr.c\n+\tzutil.c\n+    )\n+endif()\n \n if(NOT MINGW)\n     set(ZLIB_DLL_SRCS\n"
  },
  {
    "path": "package/libs/zlib/patches/005-relative-pkg-config-paths.patch",
    "content": "--- a/zlib.pc.cmakein\n+++ b/zlib.pc.cmakein\n@@ -1,8 +1,8 @@\n prefix=@CMAKE_INSTALL_PREFIX@\n exec_prefix=@CMAKE_INSTALL_PREFIX@\n-libdir=@INSTALL_LIB_DIR@\n-sharedlibdir=@INSTALL_LIB_DIR@\n-includedir=@INSTALL_INC_DIR@\n+libdir=${exec_prefix}/lib\n+sharedlibdir=${exec_prefix}/lib\n+includedir=${prefix}/include\n \n Name: zlib\n Description: zlib compression library\n"
  },
  {
    "path": "package/network/config/firewall/Makefile",
    "content": "#\n# Copyright (C) 2013-2016 OpenWrt.org\n# Copyright (C) 2016 LEDE project\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=firewall\nPKG_RELEASE:=3\n\nPKG_SOURCE_PROTO:=git\nPKG_SOURCE_URL=$(PROJECT_GIT)/project/firewall3.git\nPKG_SOURCE_DATE:=2022-02-17\nPKG_SOURCE_VERSION:=4cd7d4f36bea731bf901cb067456f1d460294926\nPKG_MIRROR_HASH:=307baf09c61ce727b4edb4283144b0d8128ebba34b858cc6389571421f829a24\nPKG_MAINTAINER:=Jo-Philipp Wich <jo@mein.io>\nPKG_LICENSE:=ISC\n\nPKG_CONFIG_DEPENDS := CONFIG_IPV6\n\ninclude $(INCLUDE_DIR)/package.mk\ninclude $(INCLUDE_DIR)/cmake.mk\n\ndefine Package/firewall\n  SECTION:=net\n  CATEGORY:=Base system\n  TITLE:=OpenWrt C Firewall\n  DEPENDS:=+libubox +libubus +libuci +libip4tc +IPV6:libip6tc +libiptext +IPV6:libiptext6 +libxtables +kmod-ipt-core +kmod-ipt-conntrack +IPV6:kmod-nf-conntrack6 +kmod-ipt-nat\n  PROVIDES:=uci-firewall\n  CONFLICTS:=firewall4\nendef\n\ndefine Package/firewall/description\n This package provides a config-compatible C implementation of the UCI firewall.\nendef\n\ndefine Package/firewall/conffiles\n/etc/config/firewall\n/etc/firewall.user\nendef\n\nTARGET_CFLAGS += -ffunction-sections -fdata-sections -flto\nTARGET_LDFLAGS += -Wl,--gc-sections -flto\nCMAKE_OPTIONS += $(if $(CONFIG_IPV6),,-DDISABLE_IPV6=1)\n\ndefine Package/firewall/install\n\t$(INSTALL_DIR) $(1)/sbin\n\t$(INSTALL_BIN) $(PKG_BUILD_DIR)/firewall3 $(1)/sbin/fw3\n\t$(INSTALL_DIR) $(1)/etc/init.d\n\t$(INSTALL_BIN) ./files/firewall.init $(1)/etc/init.d/firewall\n\t$(INSTALL_DIR) $(1)/etc/hotplug.d/iface\n\t$(INSTALL_CONF) ./files/firewall.hotplug $(1)/etc/hotplug.d/iface/20-firewall\n\t$(INSTALL_DIR) $(1)/etc/config/\n\t$(INSTALL_CONF) ./files/firewall.config $(1)/etc/config/firewall\n\t$(INSTALL_DIR) $(1)/etc/\n\t$(INSTALL_CONF) ./files/firewall.user $(1)/etc/firewall.user\n\t$(INSTALL_DIR) $(1)/usr/share/fw3\n\t$(INSTALL_CONF) $(PKG_BUILD_DIR)/helpers.conf $(1)/usr/share/fw3\nendef\n\n$(eval $(call BuildPackage,firewall))\n"
  },
  {
    "path": "package/network/config/firewall/files/firewall.config",
    "content": "config defaults\n\toption syn_flood\t1\n\toption input\t\tACCEPT\n\toption output\t\tACCEPT\n\toption forward\t\tREJECT\n# Uncomment this line to disable ipv6 rules\n#\toption disable_ipv6\t1\n\nconfig zone\n\toption name\t\tlan\n\tlist   network\t\t'lan'\n\toption input\t\tACCEPT\n\toption output\t\tACCEPT\n\toption forward\t\tACCEPT\n\nconfig zone\n\toption name\t\twan\n\tlist   network\t\t'wan'\n\tlist   network\t\t'wan6'\n\toption input\t\tACCEPT\n\toption output\t\tACCEPT\n\toption forward\t\tACCEPT\n\toption masq\t\t1\n\toption mtu_fix\t\t1\n\nconfig forwarding\n\toption src\t\tlan\n\toption dest\t\twan\n\n# We need to accept udp packets on port 68,\n# see https://dev.openwrt.org/ticket/4108\nconfig rule\n\toption name\t\tAllow-DHCP-Renew\n\toption src\t\twan\n\toption proto\t\tudp\n\toption dest_port\t68\n\toption target\t\tACCEPT\n\toption family\t\tipv4\n\n# Allow IPv4 ping\nconfig rule\n\toption name\t\tAllow-Ping\n\toption src\t\twan\n\toption proto\t\ticmp\n\toption icmp_type\techo-request\n\toption family\t\tipv4\n\toption target\t\tACCEPT\n\nconfig rule\n\toption name\t\tAllow-IGMP\n\toption src\t\twan\n\toption proto\t\tigmp\n\toption family\t\tipv4\n\toption target\t\tACCEPT\n\n# Allow DHCPv6 replies\n# see https://github.com/openwrt/openwrt/issues/5066\nconfig rule\n\toption name\t\tAllow-DHCPv6\n\toption src\t\twan\n\toption proto\t\tudp\n\toption dest_port\t546\n\toption family\t\tipv6\n\toption target\t\tACCEPT\n\nconfig rule\n\toption name\t\tAllow-MLD\n\toption src\t\twan\n\toption proto\t\ticmp\n\toption src_ip\t\tfe80::/10\n\tlist icmp_type\t\t'130/0'\n\tlist icmp_type\t\t'131/0'\n\tlist icmp_type\t\t'132/0'\n\tlist icmp_type\t\t'143/0'\n\toption family\t\tipv6\n\toption target\t\tACCEPT\n\n# Allow essential incoming IPv6 ICMP traffic\nconfig rule\n\toption name\t\tAllow-ICMPv6-Input\n\toption src\t\twan\n\toption proto\ticmp\n\tlist icmp_type\t\techo-request\n\tlist icmp_type\t\techo-reply\n\tlist icmp_type\t\tdestination-unreachable\n\tlist icmp_type\t\tpacket-too-big\n\tlist icmp_type\t\ttime-exceeded\n\tlist icmp_type\t\tbad-header\n\tlist icmp_type\t\tunknown-header-type\n\tlist icmp_type\t\trouter-solicitation\n\tlist icmp_type\t\tneighbour-solicitation\n\tlist icmp_type\t\trouter-advertisement\n\tlist icmp_type\t\tneighbour-advertisement\n\toption limit\t\t1000/sec\n\toption family\t\tipv6\n\toption target\t\tACCEPT\n\n# Allow essential forwarded IPv6 ICMP traffic\nconfig rule\n\toption name\t\tAllow-ICMPv6-Forward\n\toption src\t\twan\n\toption dest\t\t*\n\toption proto\t\ticmp\n\tlist icmp_type\t\techo-request\n\tlist icmp_type\t\techo-reply\n\tlist icmp_type\t\tdestination-unreachable\n\tlist icmp_type\t\tpacket-too-big\n\tlist icmp_type\t\ttime-exceeded\n\tlist icmp_type\t\tbad-header\n\tlist icmp_type\t\tunknown-header-type\n\toption limit\t\t1000/sec\n\toption family\t\tipv6\n\toption target\t\tACCEPT\n\nconfig rule\n\toption name\t\tAllow-IPSec-ESP\n\toption src\t\twan\n\toption dest\t\tlan\n\toption proto\t\tesp\n\toption target\t\tACCEPT\n\nconfig rule\n\toption name\t\tAllow-ISAKMP\n\toption src\t\twan\n\toption dest\t\tlan\n\toption dest_port\t500\n\toption proto\t\tudp\n\toption target\t\tACCEPT\n\n# allow interoperability with traceroute classic\n# note that traceroute uses a fixed port range, and depends on getting\n# back ICMP Unreachables.  if we're operating in DROP mode, it won't\n# work so we explicitly REJECT packets on these ports.\nconfig rule\n\toption name\t\tSupport-UDP-Traceroute\n\toption src\t\twan\n\toption dest_port\t33434:33689\n\toption proto\t\tudp\n\toption family\t\tipv4\n\toption target\t\tREJECT\n\toption enabled\t\tfalse\n\n# include a file with users custom iptables rules\nconfig include\n\toption path /etc/firewall.user\n\n\n### EXAMPLE CONFIG SECTIONS\n# do not allow a specific ip to access wan\n#config rule\n#\toption src\t\tlan\n#\toption src_ip\t192.168.45.2\n#\toption dest\t\twan\n#\toption proto\ttcp\n#\toption target\tREJECT\n\n# block a specific mac on wan\n#config rule\n#\toption dest\t\twan\n#\toption src_mac\t00:11:22:33:44:66\n#\toption target\tREJECT\n\n# block incoming ICMP traffic on a zone\n#config rule\n#\toption src\t\tlan\n#\toption proto\tICMP\n#\toption target\tDROP\n\n# port redirect port coming in on wan to lan\n#config redirect\n#\toption src\t\t\twan\n#\toption src_dport\t80\n#\toption dest\t\t\tlan\n#\toption dest_ip\t\t192.168.16.235\n#\toption dest_port\t80\n#\toption proto\t\ttcp\n\n# port redirect of remapped ssh port (22001) on wan\n#config redirect\n#\toption src\t\twan\n#\toption src_dport\t22001\n#\toption dest\t\tlan\n#\toption dest_port\t22\n#\toption proto\t\ttcp\n\n### FULL CONFIG SECTIONS\n#config rule\n#\toption src\t\tlan\n#\toption src_ip\t192.168.45.2\n#\toption src_mac\t00:11:22:33:44:55\n#\toption src_port\t80\n#\toption dest\t\twan\n#\toption dest_ip\t194.25.2.129\n#\toption dest_port\t120\n#\toption proto\ttcp\n#\toption target\tREJECT\n\n#config redirect\n#\toption src\t\tlan\n#\toption src_ip\t192.168.45.2\n#\toption src_mac\t00:11:22:33:44:55\n#\toption src_port\t\t1024\n#\toption src_dport\t80\n#\toption dest_ip\t194.25.2.129\n#\toption dest_port\t120\n#\toption proto\ttcp\n"
  },
  {
    "path": "package/network/config/firewall/files/firewall.hotplug",
    "content": "#!/bin/sh\n\n[ \"$ACTION\" = ifup -o \"$ACTION\" = ifupdate ] || exit 0\n[ \"$ACTION\" = ifupdate -a -z \"$IFUPDATE_ADDRESSES\" -a -z \"$IFUPDATE_DATA\" ] && exit 0\n\n/etc/init.d/firewall enabled || exit 0\n\nfw3 -q network \"$INTERFACE\" >/dev/null || exit 0\n\nlogger -t firewall \"Reloading firewall due to $ACTION of $INTERFACE ($DEVICE)\"\nfw3 -q reload\n"
  },
  {
    "path": "package/network/config/firewall/files/firewall.init",
    "content": "#!/bin/sh /etc/rc.common\n\nSTART=19\nUSE_PROCD=1\nQUIET=\"\"\n\nvalidate_firewall_redirect()\n{\n\tuci_validate_section firewall redirect \"${1}\" \\\n\t\t'proto:or(uinteger, string)' \\\n\t\t'src:string' \\\n\t\t'src_ip:cidr' \\\n\t\t'src_dport:or(port, portrange)' \\\n\t\t'dest:string' \\\n\t\t'dest_ip:cidr' \\\n\t\t'dest_port:or(port, portrange)' \\\n\t\t'target:or(\"SNAT\", \"DNAT\")'\n}\n\nvalidate_firewall_rule()\n{\n\tuci_validate_section firewall rule \"${1}\" \\\n\t\t'proto:or(uinteger, string)' \\\n\t\t'src:string' \\\n\t\t'dest:string' \\\n\t\t'src_port:or(port, portrange)' \\\n\t\t'dest_port:or(port, portrange)' \\\n\t\t'target:string'\n}\n\nservice_triggers() {\n\tprocd_add_reload_trigger firewall\t\n\n\tprocd_open_validate\n\tvalidate_firewall_redirect\n\tvalidate_firewall_rule\n\tprocd_close_validate\n}\n\nrestart() {\n\tfw3 restart\n}\n\nstart_service() {\n\tfw3 ${QUIET} start\n}\n\nstop_service() {\n\tfw3 flush\n}\n\nreload_service() {\n\tfw3 reload\n}\n\nboot() {\n\t# Be silent on boot, firewall might be started by hotplug already,\n\t# so don't complain in syslog.\n\tQUIET=-q\n\tstart\n}\n"
  },
  {
    "path": "package/network/config/firewall/files/firewall.user",
    "content": "# This file is interpreted as shell script.\n# Put your custom iptables rules here, they will\n# be executed with each firewall (re-)start.\n\n# Internal uci firewall chains are flushed and recreated on reload, so\n# put custom rules into the root chains e.g. INPUT or FORWARD or into the\n# special user chains, e.g. input_wan_rule or postrouting_lan_rule.\n"
  },
  {
    "path": "package/network/config/firewall4/Makefile",
    "content": "#\n# Copyright (C) 2021 Jo-Philipp Wich <jo@mein.io>\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=firewall4\nPKG_RELEASE:=$(AUTORELEASE)\n\nPKG_SOURCE_PROTO:=git\nPKG_SOURCE_URL=$(PROJECT_GIT)/project/firewall4.git\nPKG_SOURCE_DATE:=2022-04-21\nPKG_SOURCE_VERSION:=fc83d462621476be3b2861a93ac3a641e3f717c8\nPKG_MIRROR_HASH:=ca0438e04951d2c2ed58ccfca4f4a5b74f7ae96fa5560e98f8d8c5e9d083f451\nPKG_MAINTAINER:=Jo-Philipp Wich <jo@mein.io>\nPKG_LICENSE:=ISC\n\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine Package/firewall4\n  SECTION:=net\n  CATEGORY:=Base system\n  TITLE:=OpenWrt 4th gen firewall\n  DEPENDS:= \\\n\t+kmod-nft-core +kmod-nft-fib +kmod-nft-offload \\\n\t+kmod-nft-nat +kmod-nft-nat6 \\\n\t+nftables-json \\\n\t+ucode +ucode-mod-fs +ucode-mod-ubus +ucode-mod-uci\n  EXTRA_DEPENDS:=ucode (>= 2022-03-22)\n  PROVIDES:=uci-firewall\nendef\n\ndefine Package/firewall4/description\n This package provides an nftables-based implementation of the UCI firewall\n sharing the same configuration format.\nendef\n\ndefine Package/firewall4/conffiles\n/etc/config/firewall\n/etc/nftables.d/\nendef\n\ndefine Package/firewall4/install\n\t$(CP) -a $(PKG_BUILD_DIR)/root/* $(1)/\nendef\n\ndefine Build/Compile\nendef\n\n$(eval $(call BuildPackage,firewall4))\n"
  },
  {
    "path": "package/network/config/gre/Makefile",
    "content": "#\n# Copyright (C) 2014 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=gre\nPKG_RELEASE:=13\nPKG_LICENSE:=GPL-2.0\n\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine Package/gre/Default\nendef\n\ndefine Package/gre\n  SECTION:=net\n  CATEGORY:=Network\n  MAINTAINER:=Hans Dedecker <dedeckeh@gmail.com>\n  TITLE:=Generic Routing Encapsulation config support\n  DEPENDS:=+kmod-gre +IPV6:kmod-gre6 +resolveip\n  PROVIDES:=grev4 grev6\n  PKGARCH:=all\nendef\n\ndefine Package/gre/description\n Generic Routing Encapsulation config support (IPv4 and IPv6) in /etc/config/network.\nendef\n\ndefine Build/Compile\nendef\n\ndefine Build/Configure\nendef\n\ndefine Package/gre/install\n\t$(INSTALL_DIR) $(1)/lib/netifd/proto\n\t$(INSTALL_BIN) ./files/gre.sh $(1)/lib/netifd/proto/gre.sh\nendef\n\n$(eval $(call BuildPackage,gre))\n"
  },
  {
    "path": "package/network/config/gre/files/gre.sh",
    "content": "#!/bin/sh\n\n[ -n \"$INCLUDE_ONLY\" ] || {\n\t. /lib/functions.sh\n\t. /lib/functions/network.sh\n\t. ../netifd-proto.sh\n\tinit_proto \"$@\"\n}\n\ngre_generic_setup() {\n\tlocal cfg=\"$1\"\n\tlocal mode=\"$2\"\n\tlocal local=\"$3\"\n\tlocal remote=\"$4\"\n\tlocal link=\"$5\"\n\tlocal mtu ipv6 ttl tos zone ikey okey icsum ocsum iseqno oseqno multicast\n\tjson_get_vars mtu ipv6 ttl tos zone ikey okey icsum ocsum iseqno oseqno multicast\n\n\t[ -z \"$multicast\" ] && multicast=1\n\n\tproto_init_update \"$link\" 1\n\n\tproto_add_tunnel\n\tjson_add_string mode \"$mode\"\n\tjson_add_int mtu \"${mtu:-1280}\"\n\tjson_add_boolean ipv6 \"${ipv6:-1}\"\n\t[ -n \"$df\" ] && json_add_boolean df \"$df\"\n\t[ -n \"$ttl\" ] && json_add_int ttl \"$ttl\"\n\t[ -n \"$tos\" ] && json_add_string tos \"$tos\"\n\tjson_add_boolean multicast \"$multicast\"\n\tjson_add_string local \"$local\"\n\tjson_add_string remote \"$remote\"\n\t[ -n \"$tunlink\" ] && json_add_string link \"$tunlink\"\n\n\tjson_add_object 'data'\n\t[ -n \"$ikey\" ] && json_add_int ikey \"$ikey\"\n\t[ -n \"$okey\" ] && json_add_int okey \"$okey\"\n\t[ -n \"$icsum\" ] && json_add_boolean icsum \"$icsum\"\n\t[ -n \"$ocsum\" ] && json_add_boolean ocsum \"$ocsum\"\n\t[ -n \"$iseqno\" ] && json_add_boolean iseqno \"$iseqno\"\n\t[ -n \"$oseqno\" ] && json_add_boolean oseqno \"$oseqno\"\n\t[ -n \"$encaplimit\" ] && json_add_string encaplimit \"$encaplimit\"\n\tjson_close_object\n\n\tproto_close_tunnel\n\n\tproto_add_data\n\t[ -n \"$zone\" ] && json_add_string zone \"$zone\"\n\tproto_close_data\n\n\tproto_send_update \"$cfg\"\n}\n\ngre_setup() {\n\tlocal cfg=\"$1\"\n\tlocal mode=\"$2\"\n\tlocal remoteip\n\n\tlocal ipaddr peeraddr\n\tjson_get_vars df ipaddr peeraddr tunlink nohostroute\n\n\t[ -z \"$peeraddr\" ] && {\n\t\tproto_notify_error \"$cfg\" \"MISSING_PEER_ADDRESS\"\n\t\tproto_block_restart \"$cfg\"\n\t\texit\n\t}\n\n\tremoteip=$(resolveip -t 10 -4 \"$peeraddr\")\n\n\tif [ -z \"$remoteip\" ]; then\n\t\tproto_notify_error \"$cfg\" \"PEER_RESOLVE_FAIL\"\n\t\texit\n\tfi\n\n\tfor ip in $remoteip; do\n\t\tpeeraddr=$ip\n\t\tbreak\n\tdone\n\n\tif [ \"${nohostroute}\" != \"1\" ]; then\n\t\t( proto_add_host_dependency \"$cfg\" \"$peeraddr\" \"$tunlink\" )\n\tfi\n\n\t[ -z \"$ipaddr\" ] && {\n\t\tlocal wanif=\"$tunlink\"\n\t\tif [ -z $wanif ] && ! network_find_wan wanif; then\n\t\t\tproto_notify_error \"$cfg\" \"NO_WAN_LINK\"\n\t\t\texit\n\t\tfi\n\n\t\tif ! network_get_ipaddr ipaddr \"$wanif\"; then\n\t\t\tproto_notify_error \"$cfg\" \"NO_WAN_LINK\"\n\t\t\texit\n\t\tfi\n\t}\n\n\t[ -z \"$df\" ] && df=\"1\"\n\n\tcase \"$mode\" in\n\t\tgretapip)\n\t\t\tgre_generic_setup $cfg $mode $ipaddr $peeraddr \"gre4t-$cfg\"\n\t\t\t;;\n\t\t*)\n\t\t\tgre_generic_setup $cfg $mode $ipaddr $peeraddr \"gre4-$cfg\"\n\t\t\t;;\n\tesac\n}\n\nproto_gre_setup() {\n\tlocal cfg=\"$1\"\n\n\tgre_setup $cfg \"greip\"\n}\n\nproto_gretap_setup() {\n\tlocal cfg=\"$1\"\n\n\tlocal network\n\tjson_get_vars network\n\n\tgre_setup $cfg \"gretapip\"\n\n\tjson_init\n\tjson_add_string name \"gre4t-$cfg\"\n\tjson_add_boolean link-ext 0\n\tjson_close_object\n\n\tfor i in $network; do\n\t\tubus call network.interface.\"$i\" add_device \"$(json_dump)\"\n\tdone\n}\n\ngrev6_setup() {\n\tlocal cfg=\"$1\"\n\tlocal mode=\"$2\"\n\tlocal remoteip6\n\n\tlocal ip6addr peer6addr weakif\n\tjson_get_vars ip6addr peer6addr tunlink weakif encaplimit nohostroute\n\n\t[ -z \"$peer6addr\" ] && {\n\t\tproto_notify_error \"$cfg\" \"MISSING_PEER_ADDRESS\"\n\t\tproto_block_restart \"$cfg\"\n\t\texit\n\t}\n\n\tremoteip6=$(resolveip -t 10 -6 \"$peer6addr\")\n\n\tif [ -z \"$remoteip6\" ]; then\n\t\tproto_notify_error \"$cfg\" \"PEER_RESOLVE_FAIL\"\n\t\texit\n\tfi\n\n\tfor ip6 in $remoteip6; do\n\t\tpeer6addr=$ip6\n\t\tbreak\n\tdone\n\n\tif [ \"${nohostroute}\" != \"1\" ]; then\n\t\t( proto_add_host_dependency \"$cfg\" \"$peer6addr\" \"$tunlink\" )\n\tfi\n\n\t[ -z \"$ip6addr\" ] && {\n\t\tlocal wanif=\"$tunlink\"\n\t\tif [ -z $wanif ] && ! network_find_wan6 wanif; then\n\t\t\tproto_notify_error \"$cfg\" \"NO_WAN_LINK\"\n\t\t\texit\n\t\tfi\n\n\t\tif ! network_get_ipaddr6 ip6addr \"$wanif\"; then\n\t\t\t[ -z \"$weakif\" ] && weakif=\"lan\"\n\t\t\tif ! network_get_ipaddr6 ip6addr \"$weakif\"; then\n\t\t\t\tproto_notify_error \"$cfg\" \"NO_WAN_LINK\"\n\t\t\t\texit\n\t\t\tfi\n\t\tfi\n\t}\n\n\tcase \"$mode\" in\n\t\tgretapip6)\n\t\t\tgre_generic_setup $cfg $mode $ip6addr $peer6addr \"gre6t-$cfg\"\n\t\t\t;;\n\t\t*)\n\t\t\tgre_generic_setup $cfg $mode $ip6addr $peer6addr \"gre6-$cfg\"\n\t\t\t;;\n\tesac\n}\n\nproto_grev6_setup() {\n\tlocal cfg=\"$1\"\n\n\tgrev6_setup $cfg \"greip6\"\n}\n\nproto_grev6tap_setup() {\n\tlocal cfg=\"$1\"\n\n\tlocal network\n\tjson_get_vars network\n\n\tgrev6_setup $cfg \"gretapip6\"\n\n\tjson_init\n\tjson_add_string name \"gre6t-$cfg\"\n\tjson_add_boolean link-ext 0\n\tjson_close_object\n\n\tfor i in $network; do\n\t\tubus call network.interface.\"$i\" add_device \"$(json_dump)\"\n\tdone\n}\n\ngretap_generic_teardown() {\n\tlocal network\n\tjson_get_vars network\n\n\tjson_init\n\tjson_add_string name \"$1\"\n\tjson_add_boolean link-ext 0\n\tjson_close_object\n\n\tfor i in $network; do\n\t\tubus call network.interface.\"$i\" remove_device \"$(json_dump)\"\n\tdone\n}\n\nproto_gre_teardown() {\n\tlocal cfg=\"$1\"\n}\n\nproto_gretap_teardown() {\n\tlocal cfg=\"$1\"\n\n\tgretap_generic_teardown \"gre4t-$cfg\"\n}\n\nproto_grev6_teardown() {\n\tlocal cfg=\"$1\"\n}\n\nproto_grev6tap_teardown() {\n\tlocal cfg=\"$1\"\n\n\tgretap_generic_teardown \"gre6t-$cfg\"\n}\n\ngre_generic_init_config() {\n\tno_device=1\n\tavailable=1\n\n\tproto_config_add_int \"mtu\"\n\tproto_config_add_boolean \"ipv6\"\n\tproto_config_add_int \"ttl\"\n\tproto_config_add_string \"tos\"\n\tproto_config_add_string \"tunlink\"\n\tproto_config_add_string \"zone\"\n\tproto_config_add_int \"ikey\"\n\tproto_config_add_int \"okey\"\n\tproto_config_add_boolean \"icsum\"\n\tproto_config_add_boolean \"ocsum\"\n\tproto_config_add_boolean \"iseqno\"\n\tproto_config_add_boolean \"oseqno\"\n\tproto_config_add_boolean \"multicast\"\n}\n\nproto_gre_init_config() {\n\tgre_generic_init_config\n\tproto_config_add_string \"ipaddr\"\n\tproto_config_add_string \"peeraddr\"\n\tproto_config_add_boolean \"df\"\n\tproto_config_add_boolean \"nohostroute\"\n}\n\nproto_gretap_init_config() {\n\tproto_gre_init_config\n\tproto_config_add_string \"network\"\n}\n\nproto_grev6_init_config() {\n\tgre_generic_init_config\n\tproto_config_add_string \"ip6addr\"\n\tproto_config_add_string \"peer6addr\"\n\tproto_config_add_string \"weakif\"\n\tproto_config_add_string \"encaplimit\"\n\tproto_config_add_boolean \"nohostroute\"\n}\n\nproto_grev6tap_init_config() {\n\tproto_grev6_init_config\n\tproto_config_add_string \"network\"\n}\n\n[ -n \"$INCLUDE_ONLY\" ] || {\n\t[ -d /sys/module/ip_gre ] && { add_protocol gre; add_protocol gretap; }\n\t[ -d /sys/module/ip6_gre ] && { add_protocol grev6; add_protocol grev6tap; }\n}\n"
  },
  {
    "path": "package/network/config/ipip/Makefile",
    "content": "#\n# Copyright (C) 2014 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=ipip\nPKG_RELEASE:=4\nPKG_LICENSE:=GPL-2.0\n\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine Package/ipip\n  SECTION:=net\n  CATEGORY:=Network\n  MAINTAINER:=Hans Dedecker <dedeckeh@gmail.com>\n  TITLE:=IP in IP Tunnel config support\n  DEPENDS:= +kmod-ipip +resolveip\n  PKGARCH:=all\nendef\n\ndefine Package/ipip/description\n IP in IP Tunnel config support in /etc/config/network.\nendef\n\ndefine Build/Compile\nendef\n\ndefine Build/Configure\nendef\n\ndefine Package/ipip/install\n\t$(INSTALL_DIR) $(1)/lib/netifd/proto\n\t$(INSTALL_BIN) ./files/ipip.sh $(1)/lib/netifd/proto/ipip.sh\nendef\n\n$(eval $(call BuildPackage,ipip))\n"
  },
  {
    "path": "package/network/config/ipip/files/ipip.sh",
    "content": "#!/bin/sh\n\n[ -n \"$INCLUDE_ONLY\" ] || {\n\t. /lib/functions.sh\n\t. /lib/functions/network.sh\n\t. ../netifd-proto.sh\n\tinit_proto \"$@\"\n}\n\nproto_ipip_setup() {\n\tlocal cfg=\"$1\"\n\tlocal remoteip\n\n\tlocal df ipaddr peeraddr tunlink ttl tos zone mtu\n\tjson_get_vars df ipaddr peeraddr tunlink ttl tos zone mtu nohostroute\n\n\t[ -z \"$peeraddr\" ] && {\n\t\tproto_notify_error \"$cfg\" \"MISSING_PEER_ADDRESS\"\n\t\tproto_block_restart \"$cfg\"\n\t\treturn\n\t}\n\n\tremoteip=$(resolveip -t 10 -4 \"$peeraddr\")\n\n\tif [ -z \"$remoteip\" ]; then\n\t\tproto_notify_error \"$cfg\" \"PEER_RESOLVE_FAIL\"\n\t\treturn\n\tfi\n\n\tfor ip in $remoteip; do\n\t\tpeeraddr=$ip\n\t\tbreak\n\tdone\n\n\tif [ \"${nohostroute}\" != \"1\" ]; then\n\t\t( proto_add_host_dependency \"$cfg\" \"$peeraddr\" \"$tunlink\" )\n\tfi\n\n\t[ -z \"$ipaddr\" ] && {\n\t\tlocal wanif=\"$tunlink\"\n\t\tif [ -z $wanif ] && ! network_find_wan wanif; then\n\t\t\tproto_notify_error \"$cfg\" \"NO_WAN_LINK\"\n\t\t\treturn\n\t\tfi\n\n\t\tif ! network_get_ipaddr ipaddr \"$wanif\"; then\n\t\t\tproto_notify_error \"$cfg\" \"NO_WAN_LINK\"\n\t\t\treturn\n\t\tfi\n\t}\n\n\tproto_init_update \"ipip-$cfg\" 1\n\n\tproto_add_tunnel\n\tjson_add_string mode \"ipip\"\n\tjson_add_int mtu \"${mtu:-1280}\"\n\tjson_add_int ttl \"${ttl:-64}\"\n\t[ -n \"$tos\" ] && json_add_string tos \"$tos\"\n\tjson_add_string local \"$ipaddr\"\n\tjson_add_string remote \"$peeraddr\"\n\t[ -n \"$tunlink\" ] && json_add_string link \"$tunlink\"\n\tjson_add_boolean df \"${df:-1}\"\n\n\tproto_close_tunnel\n\n\tproto_add_data\n\t[ -n \"$zone\" ] && json_add_string zone \"$zone\"\n\tproto_close_data\n\n\tproto_send_update \"$cfg\"\n}\n\nproto_ipip_teardown() {\n\tlocal cfg=\"$1\"\n}\n\nproto_ipip_init_config() {\n\tno_device=1\n\tavailable=1\n\n\tproto_config_add_int \"mtu\"\n\tproto_config_add_int \"ttl\"\n\tproto_config_add_string \"tos\"\n\tproto_config_add_string \"tunlink\"\n\tproto_config_add_string \"zone\"\n\tproto_config_add_string \"ipaddr\"\n\tproto_config_add_string \"peeraddr\"\n\tproto_config_add_boolean \"df\"\n\tproto_config_add_boolean \"nohostroute\"\n}\n\n[ -n \"$INCLUDE_ONLY\" ] || {\n\tadd_protocol ipip\n}\n"
  },
  {
    "path": "package/network/config/ltq-adsl-app/Makefile",
    "content": "#\n# Copyright (C) 2011-2012 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\ninclude $(INCLUDE_DIR)/kernel.mk\n\nPKG_NAME:=dsl_cpe_control_danube\nPKG_VERSION:=3.24.4.4\nPKG_RELEASE:=10\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz\nPKG_BUILD_DIR:=$(BUILD_DIR)/dsl_cpe_control-$(PKG_VERSION)\nPKG_SOURCE_URL:=@OPENWRT\nPKG_HASH:=af0bdf45cc7a62e2b38d39aad4924dd83c24fae170ae5bbd8190c2a3d9106257\nPKG_MAINTAINER:=John Crispin <john@phrozen.org>\nPKG_LICENSE:=BSD-3-Clause\n\nPKG_FIXUP:=autoreconf\n\nPKG_CONFIG_DEPENDS:=\\\n\tCONFIG_LTQ_DSL_ENABLE_SOAP \\\n\tCONFIG_LTQ_DSL_ENABLE_DSL_EVENT_POLLING\n\nPKG_BUILD_DEPENDS:=ltq-adsl\n\nPKG_FLAGS:=nonshared\n\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine Package/ltq-adsl-app\n  SECTION:=net\n  CATEGORY:=Network\n  TITLE:=Lantiq DSL userland tool\n  URL:=http://www.lantiq.com/\n  DEPENDS:=@(TARGET_lantiq_xway||TARGET_lantiq_xway_legacy||TARGET_lantiq_ase) +libpthread +ltq-dsl-base +libubox +libubus\n  MENU:=1\nendef\n\ndefine Package/ltq-adsl-app/description\n\tInfineon DSL CPE API for Amazon SE, Danube and Vinax.\nendef\n\nLTQ_DSL_MAX_DEVICE=1\nLTQ_DSL_LINES_PER_DEVICE=1\nLTQ_DSL_CHANNELS_PER_LINE=1\n\nCONFIGURE_ARGS += \\\n\t--with-max-device=\"$(LTQ_DSL_MAX_DEVICE)\" \\\n\t--with-lines-per-device=\"$(LTQ_DSL_LINES_PER_DEVICE)\" \\\n\t--with-channels-per-line=\"$(LTQ_DSL_CHANNELS_PER_LINE)\" \\\n\t--enable-danube \\\n\t--enable-driver-include=\"-I$(STAGING_DIR)/usr/include/adsl/\" \\\n\t--enable-debug-prints \\\n\t--enable-add-appl-cflags=\"-DMAX_CLI_PIPES=2\" \\\n\t--enable-cli-support \\\n\t--enable-cmv-scripts \\\n\t--enable-debug-tool-interface \\\n\t--enable-adsl-led \\\n\t--enable-dsl-ceoc \\\n\t--enable-script-notification \\\n\t--enable-dsl-pm \\\n\t--enable-dsl-pm-total \\\n\t--enable-dsl-pm-history \\\n\t--enable-dsl-pm-showtime \\\n\t--enable-dsl-pm-channel-counters \\\n\t--enable-dsl-pm-datapath-counters \\\n\t--enable-dsl-pm-line-counters \\\n\t--enable-dsl-pm-channel-thresholds \\\n\t--enable-dsl-pm-datapath-thresholds \\\n\t--enable-dsl-pm-line-thresholds \\\n\t--enable-dsl-pm-optional-parameters\n\nTARGET_CFLAGS += -I$(LINUX_DIR)/include\n\ndefine Build/Prepare\n\t$(call Build/Prepare/Default)\n\t$(CP) ../ltq-vdsl-app/src/src/dsl_cpe_ubus.c $(PKG_BUILD_DIR)/src/\nendef\n\ndefine Package/ltq-adsl-app/install\n\t$(INSTALL_DIR) $(1)/etc/init.d $(1)/sbin $(1)/etc/hotplug.d/dsl\n\t$(INSTALL_BIN) ./files/dsl_control $(1)/etc/init.d/\n\t$(INSTALL_BIN) ./files/10_atm.sh $(1)/etc/hotplug.d/dsl\n\t$(INSTALL_BIN) ./files/10_ptm.sh $(1)/etc/hotplug.d/dsl\n\t$(INSTALL_BIN) $(PKG_BUILD_DIR)/src/dsl_cpe_control $(1)/sbin\nendef\n\n$(eval $(call BuildPackage,ltq-adsl-app))\n"
  },
  {
    "path": "package/network/config/ltq-adsl-app/files/10_atm.sh",
    "content": "#!/bin/sh\n\n[ \"$DSL_NOTIFICATION_TYPE\" = \"DSL_STATUS\" ] && \\\n[ \"$DSL_TC_LAYER_STATUS\" = \"ATM\" ] && \\\n! grep -q \"ltq_atm_ar9\\|ltq_atm_ase\\|ltq_atm_danube\" /proc/modules || exit 0\n\nlogger -p daemon.notice -t \"dsl-notify\" \"Switching to TC-Layer ATM\"\n\nif grep -q \"ltq_ptm_ar9\\|ltq_ptm_ase\\|ltq_ptm_danube\" /proc/modules ; then\n\tlogger -p daemon.notice -t \"dsl-notify\" \"Loading ATM driver while EFM/PTM driver is loaded is not possible. Reboot is needed.\"\n\texit\nfi\n\ncase \"$(strings /proc/device-tree/compatible)\" in\n*lantiq,ar9*)\n\tsoc=\"ar9\"\n\t;;\n*lantiq,ase*)\n\tsoc=\"ase\"\n\t;;\n*lantiq,danube*)\n\tsoc=\"danube\"\n\t;;\n*)\n\tlogger -p daemon.notice -t \"dsl-notify\" \"Unsupported SoC\"\n\texit\nesac\n\nmodprobe ltq_atm_${soc}\n"
  },
  {
    "path": "package/network/config/ltq-adsl-app/files/10_ptm.sh",
    "content": "#!/bin/sh\n\n[ \"$DSL_NOTIFICATION_TYPE\" = \"DSL_STATUS\" ] && \\\n[ \"$DSL_TC_LAYER_STATUS\" = \"EFM\" ] && \\\n! grep -q \"ltq_ptm_ar9\\|ltq_ptm_ase\\|ltq_ptm_danube\" /proc/modules || exit 0\n\nlogger -p daemon.notice -t \"dsl-notify\" \"Switching to TC-Layer EFM/PTM\"\n\nif grep -q \"ltq_atm_ar9\\|ltq_atm_ase\\|ltq_atm_danube\" /proc/modules ; then\n\tlogger -p daemon.notice -t \"dsl-notify\" \"Loading EFM/PTM driver while ATM driver is loaded is not possible. Reboot is needed.\"\n\texit\nfi\n\ncase \"$(strings /proc/device-tree/compatible)\" in\n*lantiq,ar9*)\n\tsoc=\"ar9\"\n\t;;\n*lantiq,ase*)\n\tsoc=\"ase\"\n\t;;\n*lantiq,danube*)\n\tsoc=\"danube\"\n\t;;\n*)\n\tlogger -p daemon.notice -t \"dsl-notify\" \"Unsupported SoC\"\n\texit\nesac\n\nmodprobe ltq_ptm_${soc}\n"
  },
  {
    "path": "package/network/config/ltq-adsl-app/files/dsl_control",
    "content": "#!/bin/sh /etc/rc.common\n# Copyright (C) 2012 OpenWrt.org\n\nSTART=97\nUSE_PROCD=1\n\ndslstat() {\n\tubus call dsl metrics\n}\n\nextra_command \"dslstat\" \"Get DSL status information\"\n\nannex_b=10_00_10_00_00_04_00_00\nannex_bdmt=10_00_00_00_00_00_00_00\nannex_b2=00_00_10_00_00_00_00_00\nannex_b2p=00_00_00_00_00_04_00_00\nannex_a=05_01_04_00_4C_01_04_00\nannex_at1=01_00_00_00_00_00_00_00\nannex_alite=00_01_00_00_00_00_00_00\nannex_admt=04_00_00_00_00_00_00_00\nannex_a2=00_00_04_00_00_00_00_00\nannex_a2p=00_00_00_00_00_01_00_00\nannex_l=00_00_00_00_0C_00_00_00\nannex_m=00_00_00_00_40_00_04_00\nannex_m2=00_00_00_00_40_00_00_00\nannex_m2p=00_00_00_00_00_00_04_00\nannex_j=10_00_10_40_00_04_01_00\n\nservice_triggers() {\n\tprocd_add_reload_trigger network\n}\n\nstart_service() {\n\tlocal annex\n\tlocal firmware\n\tlocal xtu\n\tconfig_load network\n\tconfig_get annex dsl annex\n\tconfig_get firmware dsl firmware\n\n\teval \"xtu=\\\"\\${annex_$annex}\\\"\"\n\n\t[ -z \"${firmware}\" ] &&\n\t\tfirmware=/lib/firmware/adsl.bin\n\t[ -f \"${firmware}\" ] || {\n\t\techo failed to find $firmware\n\t\treturn 1\n\t}\n\n\tprocd_open_instance\n\tprocd_set_param command /sbin/dsl_cpe_control \\\n\t\t\t-i${xtu} \\\n\t\t\t-n /sbin/dsl_notify.sh \\\n\t\t\t-f ${firmware}\n\tprocd_close_instance\n}\n\nstop_service() {\n\tDSL_NOTIFICATION_TYPE=\"DSL_INTERFACE_STATUS\" \\\n\tDSL_INTERFACE_STATUS=\"DOWN\" \\\n\t\t/sbin/dsl_notify.sh\n\n\tservice_stop /sbin/dsl_cpe_control\n}\n\n"
  },
  {
    "path": "package/network/config/ltq-adsl-app/patches/001-stupid_breakage_fix.patch",
    "content": "--- a/src/dsl_cpe_cli_access.c\t2016-05-27 12:34:43.612485449 -0700\n+++ b/src/dsl_cpe_cli_access.c\t2016-05-27 12:45:37.491727862 -0700\n@@ -1142,7 +1142,7 @@\n \n       if ((ret < 0) && (autobootCtrl.accessCtl.nReturn < DSL_SUCCESS))\n       {\n-         DSL_CPE_FPrintf (out, sFailureReturn, autobootCtrl.accessCtl.nReturn);\n+         DSL_CPE_FPrintf (out, sFailureReturn, autobootCtrl.accessCtl.nReturn, DSL_CPE_Fd2DevStr(fd));\n       }\n       else\n       {\n@@ -1213,7 +1213,7 @@\n \n    if ((ret < 0) && (pData.accessCtl.nReturn < DSL_SUCCESS))\n    {\n-      DSL_CPE_FPrintf (out, sFailureReturn, pData.accessCtl.nReturn);\n+      DSL_CPE_FPrintf (out, sFailureReturn, pData.accessCtl.nReturn, DSL_CPE_Fd2DevStr(fd));\n    }\n    else\n    {\n@@ -1290,7 +1290,7 @@\n \n    if ((ret < 0) && (pData.accessCtl.nReturn < DSL_SUCCESS))\n    {\n-      DSL_CPE_FPrintf (out, sFailureReturn, pData.accessCtl.nReturn);\n+      DSL_CPE_FPrintf (out, sFailureReturn, pData.accessCtl.nReturn, DSL_CPE_Fd2DevStr(fd));\n    }\n    else\n    {\n@@ -1355,7 +1355,7 @@\n                   pCtx, &resourceUsageStatisticsData);\n          if (ret < 0)\n          {\n-            DSL_CPE_FPrintf (out, sFailureReturn, ret);\n+            DSL_CPE_FPrintf (out, sFailureReturn, ret, DSL_CPE_Fd2DevStr(fd));\n          }\n          else\n          {\n@@ -3084,7 +3084,7 @@\n \n    if ((ret < 0) && (pData->accessCtl.nReturn < DSL_SUCCESS))\n    {\n-      DSL_CPE_FPrintf (out, sFailureReturn, pData->accessCtl.nReturn);\n+      DSL_CPE_FPrintf (out, sFailureReturn, pData->accessCtl.nReturn, DSL_CPE_Fd2DevStr(fd));\n    }\n    else\n    {\n@@ -4654,7 +4654,7 @@\n \n    if ((ret < 0) && (pData.accessCtl.nReturn < DSL_SUCCESS))\n    {\n-      DSL_CPE_FPrintf (out, sFailureReturn, pData.accessCtl.nReturn);\n+      DSL_CPE_FPrintf (out, sFailureReturn, pData.accessCtl.nReturn, DSL_CPE_Fd2DevStr(fd));\n    }\n    else\n    {\n@@ -5714,7 +5714,7 @@\n \n    if ((ret < 0) && (pData.accessCtl.nReturn < DSL_SUCCESS))\n    {\n-      DSL_CPE_FPrintf (out, sFailureReturn, pData.accessCtl.nReturn);\n+      DSL_CPE_FPrintf (out, sFailureReturn, pData.accessCtl.nReturn, DSL_CPE_Fd2DevStr(fd));\n    }\n    else\n    {\n"
  },
  {
    "path": "package/network/config/ltq-adsl-app/patches/010-eglibc_compile_fix.patch",
    "content": "--- a/configure.in\n+++ b/configure.in\n@@ -29,6 +29,8 @@ AC_C_VOLATILE\n #AC_FUNC_STRTOD\n #AC_CHECK_FUNCS([ftime gethostbyname gettimeofday localtime_r memset select socket strchr strerror strstr strtoull])\n \n+AC_SEARCH_LIBS([clock_gettime],[rt])\n+\n #\n # save the configure arguments\n #\n--- a/src/dsl_cpe_linux.h\n+++ b/src/dsl_cpe_linux.h\n@@ -45,7 +45,8 @@\n #include <arpa/inet.h>\n #include <sys/socket.h>          /* socket */\n #include <sys/sem.h>             /* semget */\n-#include <semaphore.h>           /* sem_t */ \n+#include <semaphore.h>           /* sem_t */\n+#include <limits.h>\n \n #ifdef DSL_DEBUG_TOOL_INTERFACE\n #include <sys/socket.h>\n"
  },
  {
    "path": "package/network/config/ltq-adsl-app/patches/100-add-more-script-notifications.patch",
    "content": "From 9d4f86ba2cf10304303011f4f5628fa68dc77624 Mon Sep 17 00:00:00 2001\nFrom: Mathias Kresin <dev@kresin.me>\nDate: Mon, 16 Oct 2017 21:08:26 +0200\nSubject: ltq-adsl-app: add more script notifications\n\nBackport HANDSHAKE and TRAINING notification from ltq-vdsl-app. It\nunifies the dsl led blinking pattern accross all subtargets and allows\nto get the current line status from the dsl led.\n\nSigned-off-by: Mathias Kresin <dev@kresin.me>\n---\n .../100-add-more-script-notifications.patch        | 27 ++++++++++++++++++++++\n 1 file changed, 27 insertions(+)\n create mode 100644 package/network/config/ltq-adsl-app/patches/100-add-more-script-notifications.patch\n\n--- a/src/dsl_cpe_control.c\n+++ b/src/dsl_cpe_control.c\n@@ -3273,7 +3273,23 @@ DSL_CPE_STATIC DSL_int_t DSL_CPE_Event_S\n #ifdef INCLUDE_SCRIPT_NOTIFICATION\n    if (g_sRcScript != DSL_NULL)\n    {\n-      if ( (nLineState == DSL_LINESTATE_SHOWTIME_TC_SYNC) &&\n+      if ( (nLineState == DSL_LINESTATE_HANDSHAKE) &&\n+                (g_nPrevLineState[nDevice] != DSL_LINESTATE_HANDSHAKE) )\n+      {\n+         if (DSL_CPE_SetEnv(\"DSL_INTERFACE_STATUS\", \"HANDSHAKE\") == DSL_SUCCESS)\n+         {\n+            bExec = DSL_TRUE;\n+         }\n+      }\n+      else if ( (nLineState == DSL_LINESTATE_FULL_INIT) &&\n+                (g_nPrevLineState[nDevice] != DSL_LINESTATE_FULL_INIT) )\n+      {\n+         if (DSL_CPE_SetEnv(\"DSL_INTERFACE_STATUS\", \"TRAINING\") == DSL_SUCCESS)\n+         {\n+            bExec = DSL_TRUE;\n+         }\n+      }\n+      else if ( (nLineState == DSL_LINESTATE_SHOWTIME_TC_SYNC) &&\n            (g_nPrevLineState[nDevice] != DSL_LINESTATE_SHOWTIME_TC_SYNC) )\n       {\n          if (DSL_CPE_SetEnv(\"DSL_INTERFACE_STATUS\", \"UP\") == DSL_SUCCESS)\n"
  },
  {
    "path": "package/network/config/ltq-adsl-app/patches/300-ubus.patch",
    "content": "--- a/src/dsl_cpe_control.c\n+++ b/src/dsl_cpe_control.c\n@@ -139,6 +139,9 @@ extern DSL_Error_t DSL_CPE_Pipe_StaticRe\n #endif /* INCLUDE_DSL_RESOURCE_STATISTICS*/\n #endif\n \n+extern void ubus_init();\n+extern void ubus_deinit();\n+\n DSL_char_t *g_sFirmwareName1 = DSL_NULL;\n DSL_char_t *g_sFirmwareName2 = DSL_NULL;\n #ifdef INCLUDE_SCRIPT_NOTIFICATION\n@@ -5343,6 +5346,8 @@ DSL_int_t dsl_cpe_daemon (\n    signal (SIGINT, DSL_CPE_TerminationHandler);\n #endif /* RTEMS*/\n \n+   ubus_init();\n+\n    /* Open DSL_CPE_MAX_DEVICE_NUMBER devices*/\n    for (nDevice = 0; nDevice < DSL_CPE_MAX_DEVICE_NUMBER; nDevice++)\n    {\n@@ -5738,6 +5743,7 @@ DSL_int_t dsl_cpe_daemon (\n #endif /* INCLUDE_DSL_CPE_CLI_SUPPORT */\n \n DSL_CPE_CONTROL_EXIT:\n+   ubus_deinit();\n \n #ifdef INCLUDE_DSL_BONDING\n    DSL_CPE_BND_Stop((DSL_CPE_BND_Context_t*)pCtrlCtx->pBnd);\n--- a/src/Makefile.am\n+++ b/src/Makefile.am\n@@ -11,7 +11,7 @@ else\n dsl_cpe_control_common_ldflags =\n endif\n \n-dsl_cpe_control_LDADD = -lpthread\n+dsl_cpe_control_LDADD = -lpthread -lubox -lubus\n \n if INCLUDE_DSL_CPE_SOAP_SUPPORT\n     dsl_cpe_control_LDADD += -lm\n@@ -70,7 +70,8 @@ dsl_cpe_control_SOURCES = \\\n \tdsl_cpe_control.c \\\n \tdsl_cpe_init_cfg.c \\\n \tdsl_cpe_linux.c \\\n-\tdsl_cpe_debug.c\n+\tdsl_cpe_debug.c \\\n+\tdsl_cpe_ubus.c\n \n dsl_cpe_control_SOURCES += \\\n \t$(dsl_cpe_control_dti_sources)\n"
  },
  {
    "path": "package/network/config/ltq-vdsl-app/Makefile",
    "content": "# Copyright (C) 2010 OpenWrt.org\n# Copyright (C) 2015-2016 Lantiq Beteiligungs GmbH & Co KG.\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n\ninclude $(TOPDIR)/rules.mk\ninclude $(INCLUDE_DIR)/kernel.mk\n\nPKG_NAME:=ltq-vdsl-app\nPKG_VERSION:=4.17.18.6\nPKG_RELEASE:=$(AUTORELEASE)\nPKG_BASE_NAME:=dsl_cpe_control\nPKG_SOURCE:=$(PKG_BASE_NAME)_vrx-$(PKG_VERSION).tar.gz\nPKG_SOURCE_URL:=@OPENWRT\nPKG_HASH:=da8bb929526a61aea0e153ef524331fcd472a1ebbc6d88ca017735a4f82ece02\nPKG_BUILD_DIR:=$(KERNEL_BUILD_DIR)/$(PKG_BASE_NAME)-$(PKG_VERSION)\nPKG_LICENSE:=BSD-2-Clause\n\nPKG_BUILD_DEPENDS:=ltq-vdsl\n\nPKG_FLAGS:=nonshared\nPKG_FIXUP:=autoreconf\n\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine Package/ltq-vdsl-app\n  SECTION:=net\n  CATEGORY:=Network\n  TITLE:=Lantiq VDSL userland tool\n  URL:=http://www.lantiq.com/\n  DEPENDS:=@TARGET_lantiq_xrx200 +libpthread +librt +ltq-dsl-base +libubox +libubus\nendef\n\ndefine Package/ltq-vdsl-app/description\n  Userland tool needed to control Lantiq VDSL CPE\nendef\n\n# ltq-vdsl-app uses a header provided by the MEI driver which has some\n# conditionals.\n#\n# Define them here with the default values they would get in the MEI driver,\n# have the same view on both sides.\n#\n# If you change them, you need to change them for the ltq-vdsl-app as well\nVDSL_APP_CFLAGS = \\\n\t-DMAX_CLI_PIPES=1 \\\n\t-DMEI_SUPPORT_DEBUG_STREAMS=1 \\\n\t-DMEI_SUPPORT_OPTIMIZED_FW_DL=1\n\nCONFIGURE_ARGS += \\\n\t--enable-vrx \\\n\t--enable-vrx-device=vr9 \\\n\t--enable-driver-include=\"-I$(STAGING_DIR)/usr/include/drv_vdsl_cpe_api\" \\\n\t--enable-device-driver-include=\"-I$(STAGING_DIR)/usr/include/vdsl/\" \\\n\t--enable-ifxos \\\n\t--enable-ifxos-include=\"-I$(STAGING_DIR)/usr/include/ifxos\" \\\n\t--enable-ifxos-library=\"-I$(STAGING_DIR)/usr/lib\" \\\n\t--enable-add-appl-cflags=\"$(VDSL_APP_CFLAGS)\"  \\\n\t--enable-debug \\\n\t--disable-dti \\\n\t--with-channels-per-line=\"1\"\n\nCONFIGURE_ARGS += \\\n\t--enable-model=full \\\n\t--enable-dsl-ceoc=no\n#CONFIGURE_ARGS += --enable-model=lite\n#CONFIGURE_ARGS += --enable-model=footprint\n#CONFIGURE_ARGS += --enable-model=typical\n#CONFIGURE_ARGS += --enable-model=debug\n\ndefine Package/ltq-vdsl-app/install\n\t$(INSTALL_DIR) $(1)/etc/init.d $(1)/sbin $(1)/etc/hotplug.d/dsl\n\t$(INSTALL_BIN) ./files/dsl_control $(1)/etc/init.d/\n\t$(INSTALL_BIN) ./files/10_atm.sh $(1)/etc/hotplug.d/dsl\n\t$(INSTALL_BIN) ./files/10_ptm.sh $(1)/etc/hotplug.d/dsl\n\n\t$(INSTALL_BIN) $(PKG_BUILD_DIR)/src/dsl_cpe_control $(1)/sbin/vdsl_cpe_control\n\t$(INSTALL_BIN) ./files/dsl_cpe_pipe.sh $(1)/sbin/\nendef\n\n$(eval $(call BuildPackage,ltq-vdsl-app))\n"
  },
  {
    "path": "package/network/config/ltq-vdsl-app/files/10_atm.sh",
    "content": "#!/bin/sh\n\n[ \"$DSL_NOTIFICATION_TYPE\" = \"DSL_STATUS\" ] && \\\n[ \"$DSL_TC_LAYER_STATUS\" = \"ATM\" ] && \\\n! grep -q \"ltq_atm_vr9\" /proc/modules || exit 0\n\nlogger -p daemon.notice -t \"dsl-notify\" \"Switching to TC-Layer ATM\"\n\nif grep -q \"ltq_ptm_vr9\" /proc/modules ; then\n\tlogger -p daemon.notice -t \"dsl-notify\" \"Loading ATM driver while EFM/PTM driver is loaded is not possible. Reboot is needed.\"\n\texit\nfi\n\nmodprobe ltq_atm_vr9\n"
  },
  {
    "path": "package/network/config/ltq-vdsl-app/files/10_ptm.sh",
    "content": "#!/bin/sh\n\n[ \"$DSL_NOTIFICATION_TYPE\" = \"DSL_STATUS\" ] && \\\n[ \"$DSL_TC_LAYER_STATUS\" = \"EFM\" ] && \\\n! grep -q \"ltq_ptm_vr9\" /proc/modules || exit 0\n\nlogger -p daemon.notice -t \"dsl-notify\" \"Switching to TC-Layer EFM/PTM\"\n\nif grep -q \"ltq_atm_vr9\" /proc/modules ; then\n\tlogger -p daemon.notice -t \"dsl-notify\" \"Loading EFM/PTM driver while ATM driver is loaded is not possible. Reboot is needed.\"\n\texit\nfi\n\nmodprobe ltq_ptm_vr9\n"
  },
  {
    "path": "package/network/config/ltq-vdsl-app/files/dsl_control",
    "content": "#!/bin/sh /etc/rc.common\n# Copyright (C) 2012 OpenWrt.org\n\nSTART=97\nUSE_PROCD=1\n\ndslstat() {\n\tubus call dsl metrics\n}\n\nextra_command \"dslstat\" \"Get DSL status information\"\n\n#\n# ITU-T G.997.1 (06/2012) - Section 7.3.1.1.1 (xTU transmission system enabling (XTSE))\n# ITU-T G.997.1 Amendment 2 (04/2013) - Section 2.1 - (Vectoring mode enable (VECTORMODE_ENABLE))\n#\n# G.992.1 Annex A\n# G.992.2 Annex A\n# G.992.3 Annex A / L-US1 / L_US-2 / M\n# G.992.5 Annex A / M\n# G.993.2 Annex A/B/C\n# G.993.5 Annex A/B/C\nxtse_xdsl_a=\"05_01_04_00_4C_01_04_07\"\n\n# G.992.1 Annex B\n# G.992.3 Annex B\n# G.992.5 Annex B\n# G.993.2 Annex A/B/C\n# G.993.5 Annex A/B/C\nxtse_xdsl_b=\"10_00_10_00_00_04_00_07\"\n\n# G.992.1 Annex B\n# G.992.3 Annex B\n# G.992.3 Annex J\n# G.992.5 Annex B\n# G.992.5 Annex J\n# G.993.2 Annex A/B/C\n# G.993.5 Annex A/B/C\nxtse_xdsl_j=\"10_00_10_40_00_04_01_07\"\n\n# G.992.1 Annex B\nxtse_xdsl_bdmt=\"10_00_00_00_00_00_00_00\"\n\n# G.992.3 Annex B\nxtse_xdsl_b2=\"00_00_10_00_00_00_00_00\"\n\n# G.992.5 Annex B\nxtse_xdsl_b2p=\"00_00_00_00_00_04_00_00\"\n\n# ANSI T1.413\nxtse_xdsl_at1=\"01_00_00_00_00_00_00_00\"\n\n# G.992.2 Annex A\nxtse_xdsl_alite=\"00_01_00_00_00_00_00_00\"\n\n# G.992.1 Annex A\nxtse_xdsl_admt=\"04_00_00_00_00_00_00_00\"\n\n# G.992.3 Annex A\nxtse_xdsl_a2=\"00_00_04_00_00_00_00_00\"\n\n# G.992.5 Annex A\nxtse_xdsl_a2p=\"00_00_00_00_00_01_00_00\"\n\n# G.992.3 Annex L\nxtse_xdsl_l=\"00_00_00_00_0C_00_00_00\"\n\n# G.992.3 Annex M\n# G.992.5 Annex M\nxtse_xdsl_m=\"00_00_00_00_40_00_04_00\"\n\n# G.992.3 Annex M\nxtse_xdsl_m2=\"00_00_00_00_40_00_00_00\"\n\n# G.992.5 Annex M\nxtse_xdsl_m2p=\"00_00_00_00_00_00_04_00\"\n\n#\n# ITU-T G.994.1 (06/2012) - Table 2 (Mandatory carrier sets)\n#\n\n# A43\ntone_adsl_a=\"0x142\" # A43C + J43 + A43\ntone_vdsl_a=\"0x142\" # A43C + J43 + A43\n\n# A43 + V43\ntone_adsl_av=\"0x142\" # A43C + J43 + A43\ntone_vdsl_av=\"0x146\" # A43C + J43 + A43 + V43\n\n# B43\ntone_adsl_b=\"0x81\" # B43 + B43c\ntone_vdsl_b=\"0x1\" # B43\n\n# B43 + V43\ntone_adsl_bv=\"0x81\" # B43 + B43c\ntone_vdsl_bv=\"0x5\" # B43 + V43\n\n# create DSL autoboot script. Used for SNR margin tweak and to set MAC address for vectoring error reports\nautoboot_script() {\n    echo \"[WaitForConfiguration]={\nlocs 0 $1\ndsmmcs $2\n}\n\n[WaitForLinkActivate]={\n}\n\n[WaitForRestart]={\n}\n\n[Common]={\n}\" > /tmp/dsl.scr\n}\n\nlowlevel_cfg() {\n\techo \"# VRX Low Level Configuration File\n#\n# Parameters must be separated by tabs or spaces.\n# Empty lines and comments will be ignored.\n#\n\n# nFilter\n#\n# NA     = -1\n# OFF    = 0\n# ISDN   = 1\n# POTS   = 2\n# POTS_2 = 3\n# POTS_3 = 4\n#\n#  (dec)\n    -1\n\n# nHsToneGroupMode nHsToneGroup_A       nHsToneGroup_V    nHsToneGroup_AV\n#\n# NA     = -1      NA         = -1      see               see\n# AUTO   = 0       VDSL2_B43  = 0x0001  nHsToneGroup_A    nHsToneGroup_A\n# MANUAL = 1       VDSL2_A43  = 0x0002\n#                  VDSL2_V43  = 0x0004\n#                  VDSL1_V43P = 0x0008\n#                  VDSL1_V43I = 0x0010\n#                  ADSL1_C43  = 0x0020\n#                  ADSL2_J43  = 0x0040\n#                  ADSL2_B43C = 0x0080\n#                  ADSL2_A43C = 0x0100\n#\n#  (dec)           (hex)                (hex)             (hex)\n     1             $1\t\t\t$2\t\t 0x0\n\n#   nBaseAddr     nIrqNum\n#\n#     (hex)        (dec)\n    0x1e116000      63\n\n# nUtopiaPhyAdr   nUtopiaBusWidth      nPosPhyParity\n#                 default(16b) = 0     NA   = -1\n#                 8-bit        = 1     ODD  = 0\n#                 16-bit       = 2\n#\n#\n#    (hex)            (dec)                (dec)\n      0xFF              0                    0\n\n# bNtrEnable\n#\n#  (dec)\n    0\" > /tmp/lowlevel.cfg\n}\n\nget_macaddr() {\n\tlocal name\n\tconfig_get name $1 name\n\t[ \"$name\" = \"dsl0\" ] && config_get $2 $1 macaddr\n}\n\nservice_triggers() {\n\tprocd_add_reload_trigger network\n}\n\nstart_service() {\n\tlocal annex\n\tlocal firmware\n\tlocal tone\n\tlocal tone_adsl\n\tlocal tone_vdsl\n\tlocal xtse\n\tlocal xfer_mode\n\tlocal line_mode\n\tlocal tc_layer\n\tlocal mode\n\tlocal lowlevel\n\tlocal snr\n\tlocal macaddr\n\n\tconfig_load network\n\tconfig_get tone dsl tone\n\tconfig_get annex dsl annex\n\tconfig_get firmware dsl firmware\n\tconfig_get xfer_mode dsl xfer_mode\n\tconfig_get line_mode dsl line_mode\n\tconfig_get snr dsl ds_snr_offset\n\tconfig_foreach get_macaddr device macaddr\n\n\teval \"xtse=\\\"\\${xtse_xdsl_$annex}\\\"\"\n\n\tcase \"${xfer_mode}\" in\n\tatm)\n\t\ttc_layer=\"-T1:0x1:0x1_1:0x1:0x1\"\n\t\t;;\n\tptm)\n\t\ttc_layer=\"-T2:0x1:0x1_2:0x1:0x1\"\n\t\t;;\n\tesac\n\n\tcase \"${line_mode}\" in\n\tadsl)\n\t\tmode=\"-M1\"\n\n\t\t# mask out VDSL bits when ADSL is requested\n\t\txtse=\"${xtse%_*}_00\"\n\t\t;;\n\tvdsl)\n\t\tmode=\"-M2\"\n\n\t\t# mask out ADSL bits when VDSL is requested\n\t\txtse=\"00_00_00_00_00_00_00_${xtse##*_}\"\n\t\t;;\n\tesac\n\n\tlocal annexgpio=\"/sys/class/gpio/annex\"\n\tif [ -d \"${annexgpio}a\" ] && [ -d \"${annexgpio}b\" ]; then\n\t\tcase \"${annex}\" in\n\t\t\ta*|l*|m*)\n\t\t\t\techo 1 > \"${annexgpio}a/value\"\n\t\t\t\techo 0 > \"${annexgpio}b/value\"\n\t\t\t\t;;\n\t\t\tb*|j*)\n\t\t\t\techo 0 > \"${annexgpio}a/value\"\n\t\t\t\techo 1 > \"${annexgpio}b/value\"\n\t\t\t\t;;\n\t\tesac\n\tfi\n\n\tif [ -z \"${firmware}\" ]; then\n\t\t# search for the firmware provided by dsl-vrx200-firmware-xdsl-*\n\t\tif grep -qE \"system type.*: (VR9|xRX200)\" /proc/cpuinfo; then\n\t\t\tcase \"${annex}\" in\n\t\t\ta*|l*|m*)\n\t\t\t\tif [ -f \"/lib/firmware/lantiq-vrx200-a.bin\" ]; then\n\t\t\t\t\tfirmware=\"/lib/firmware/lantiq-vrx200-a.bin\"\n\t\t\t\telif [ -f \"/tmp/lantiq-vrx200-a.bin\" ]; then\n\t\t\t\t\tfirmware=\"/tmp/lantiq-vrx200-a.bin\"\n\t\t\t\telif [ -f \"/lib/firmware/lantiq-vrx200-b.bin\" ] && [ -f \"/lib/firmware/lantiq-vrx200-b-to-a.bspatch\" ]; then\n\t\t\t\t\tbspatch /lib/firmware/lantiq-vrx200-b.bin \\\n\t\t\t\t\t\t/tmp/lantiq-vrx200-a.bin \\\n\t\t\t\t\t\t/lib/firmware/lantiq-vrx200-b-to-a.bspatch\n\t\t\t\t\tfirmware=\"/tmp/lantiq-vrx200-a.bin\"\n\t\t\t\telse\n\t\t\t\t\techo \"firmware for annex a not found\"\n\t\t\t\t\treturn 1\n\t\t\t\tfi\n\t\t\t\t;;\n\t\t\tb*|j*)\n\t\t\t\tif [ -f \"/lib/firmware/vr9_dsl_fw_annex_b.bin\" ]; then\n\t\t\t\t\tfirmware=\"/lib/firmware/vr9_dsl_fw_annex_b.bin\"\n\t\t\t\telif [ -f \"/lib/firmware/lantiq-vrx200-b.bin\" ]; then\n\t\t\t\t\tfirmware=\"/lib/firmware/lantiq-vrx200-b.bin\"\n\t\t\t\telif [ -f \"/tmp/lantiq-vrx200-b.bin\" ]; then\n\t\t\t\t\tfirmware=\"/tmp/lantiq-vrx200-b.bin\"\n\t\t\t\telif [ -f \"/lib/firmware/lantiq-vrx200-a.bin\" ] && [ -f \"/lib/firmware/lantiq-vrx200-a-to-b.bspatch\" ]; then\n\t\t\t\t\tbspatch /lib/firmware/lantiq-vrx200-a.bin \\\n\t\t\t\t\t\t/tmp/lantiq-vrx200-b.bin \\\n\t\t\t\t\t\t/lib/firmware/lantiq-vrx200-a-to-b.bspatch\n\t\t\t\t\tfirmware=\"/tmp/lantiq-vrx200-b.bin\"\n\t\t\t\telse\n\t\t\t\t\techo \"firmware for annex b not found\"\n\t\t\t\t\treturn 1\n\t\t\t\tfi\n\t\t\t\t;;\n\t\t\t*)\n\t\t\t\techo \"annex type not supported use a or b\"\n\t\t\t\treturn 1\n\t\t\t\t;;\n\t\t\tesac\n\t\tfi\n\tfi\n\n\t[ -z \"${firmware}\" ] && firmware=/lib/firmware/vdsl.bin\n\t[ -f \"${firmware}\" ] || {\n\t\techo failed to find $firmware\n\t\treturn 1\n\t}\n\n\teval \"tone_adsl=\\\"\\${tone_adsl_$tone}\\\"\"\n\teval \"tone_vdsl=\\\"\\${tone_vdsl_$tone}\\\"\"\n\t[ -n \"${tone_adsl}\" ] && [ -n \"${tone_vdsl}\" ] && {\n\t\tlowlevel_cfg \"${tone_adsl}\" \"${tone_vdsl}\"\n\t\tlowlevel=\"-l /tmp/lowlevel.cfg\"\n\t}\n\n\t[ -z \"${snr}\" ] && snr=0\n\t[ -z \"${macaddr}\" ] && macaddr=\"00:00:00:00:00:00\"\n\tautoboot_script \"$snr\" \"$macaddr\"\n\tautoboot=\"-a /tmp/dsl.scr -A /tmp/dsl.scr\"\n\n\tprocd_open_instance\n\tprocd_set_param command /sbin/vdsl_cpe_control \\\n\t\t\t-i$xtse \\\n\t\t\t-n /sbin/dsl_notify.sh \\\n\t\t\t-f ${firmware} \\\n\t\t\t$lowlevel \\\n\t\t\t${mode} \\\n\t\t\t${tc_layer} \\\n\t\t\t$autoboot\n\tprocd_close_instance\n}\n\nstop_service() {\n\tDSL_NOTIFICATION_TYPE=\"DSL_INTERFACE_STATUS\" \\\n\tDSL_INTERFACE_STATUS=\"DOWN\" \\\n\t\t/sbin/dsl_notify.sh\n}\n"
  },
  {
    "path": "package/network/config/ltq-vdsl-app/files/dsl_cpe_pipe.sh",
    "content": "#!/bin/sh\n\npipe_no=0\n\n# use specified pipe no\ncase \"$1\" in\n0|1|2)\npipe_no=$1; shift; ;;\nesac\n\n\n#echo \"Call dsl_pipe with $*\"\nlock /var/lock/dsl_pipe\necho $* > /tmp/pipe/dsl_cpe${pipe_no}_cmd\nresult=$(cat /tmp/pipe/dsl_cpe${pipe_no}_ack)\nlock -u /var/lock/dsl_pipe\n\necho \"$result\"\n"
  },
  {
    "path": "package/network/config/ltq-vdsl-app/patches/100-compat.patch",
    "content": "--- a/src/dsl_cpe_init_cfg.c\n+++ b/src/dsl_cpe_init_cfg.c\n@@ -38,7 +38,7 @@ DSL_InitData_t gInitCfgData =\n       DSL_DEV_HS_TONE_GROUP_CLEANED, \\\n       DSL_DEV_HS_TONE_GROUP_CLEANED, \\\n       DSL_DEV_HS_TONE_GROUP_CLEANED, \\\n-      0x1E116000, 0x37, -1),\n+      0x1E116000, 0x3f, -1),\n    DSL_CPE_SIC_SET(DSL_TC_ATM, DSL_EMF_TC_CLEANED, DSL_EMF_TC_CLEANED, DSL_SYSTEMIF_MII, \\\n                    DSL_TC_EFM, DSL_EMF_TC_CLEANED, DSL_EMF_TC_CLEANED, DSL_SYSTEMIF_MII),\n    DSL_CPE_MAC_CFG_SET(DSL_EFM_SPEED_100, DSL_EFM_DUPLEX_FULL, DSL_EFM_FLOWCTRL_ON, DSL_EFM_AUTONEG_OFF, \\\n"
  },
  {
    "path": "package/network/config/ltq-vdsl-app/patches/101-musl.patch",
    "content": "--- a/src/dsl_cpe_control.c\n+++ b/src/dsl_cpe_control.c\n@@ -11,6 +11,7 @@\n /*\n Includes\n */\n+#include <limits.h>\n #include \"dsl_cpe_control.h\"\n #include \"dsl_cpe_cli.h\"\n #include \"dsl_cpe_cli_console.h\"\n"
  },
  {
    "path": "package/network/config/ltq-vdsl-app/patches/200-autoboot.patch",
    "content": "This enables automatic connection after the control daemon is started,\nand also stops the connection on termination.\n\nUsing the autoboot restart command is necessary because the stop command\ndoesn't actually stop the connection, and would also leave the driver in\na state where an explicit start command is necessary to connect again.\n\n--- a/src/dsl_cpe_init_cfg.c\n+++ b/src/dsl_cpe_init_cfg.c\n@@ -27,7 +27,7 @@ DSL_InitData_t gInitCfgData =\n    DSL_CPE_FW2_SET(DSL_NULL, 0x0),\n    DSL_CPE_XTU_SET(0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x7),\n    DSL_CPE_LINE_INV_NE_SET(DSL_NULL),\n-   DSL_CPE_AUTOBOOT_CTRL_SET(DSL_AUTOBOOT_CTRL_STOP),\n+   DSL_CPE_AUTOBOOT_CTRL_SET(DSL_AUTOBOOT_CTRL_START),\n    DSL_CPE_AUTOBOOT_CFG_SET(DSL_FALSE, DSL_FALSE, DSL_FALSE),\n    DSL_CPE_TEST_MODE_CTRL_SET(DSL_TESTMODE_DISABLE),\n    DSL_CPE_LINE_ACTIVATE_CTRL_SET(DSL_G997_INHIBIT_LDSF, DSL_G997_INHIBIT_ACSF, DSL_G997_NORMAL_STARTUP),\n--- a/src/dsl_cpe_control.c\n+++ b/src/dsl_cpe_control.c\n@@ -6515,10 +6515,13 @@ DSL_CPE_STATIC  void DSL_CPE_Termination\n DSL_CPE_STATIC  DSL_void_t DSL_CPE_Termination (void)\n {\n #ifdef INCLUDE_DSL_CPE_CLI_SUPPORT\n-   DSL_int_t nDevice = 0;\n    DSL_char_t buf[32] = \"quit\";\n #endif\n \n+   DSL_Error_t nRet = DSL_SUCCESS;\n+   DSL_int_t nDevice = 0;\n+   DSL_AutobootConfig_t sAutobootCfg;\n+   DSL_AutobootControl_t sAutobootCtl;\n    DSL_CPE_Control_Context_t *pCtrlCtx;\n \n    pCtrlCtx = DSL_CPE_GetGlobalContext();\n@@ -6527,6 +6530,50 @@ DSL_CPE_STATIC  DSL_void_t DSL_CPE_Termi\n       pCtrlCtx->bRun = DSL_FALSE;\n    }\n \n+   for (nDevice = 0; nDevice < DSL_CPE_MAX_DSL_ENTITIES; ++nDevice)\n+   {\n+      g_bWaitBeforeConfigWrite[nDevice]    = DSL_TRUE;\n+      g_bWaitBeforeLinkActivation[nDevice] = DSL_TRUE;\n+      g_bWaitBeforeRestart[nDevice]        = DSL_TRUE;\n+\n+      g_bAutoContinueWaitBeforeConfigWrite[nDevice]    = DSL_FALSE;\n+      g_bAutoContinueWaitBeforeLinkActivation[nDevice] = DSL_FALSE;\n+      g_bAutoContinueWaitBeforeRestart[nDevice]        = DSL_FALSE;\n+\n+      memset(&sAutobootCfg, 0x0, sizeof(DSL_AutobootConfig_t));\n+      sAutobootCfg.data.nStateMachineOptions.bWaitBeforeConfigWrite    = DSL_TRUE;\n+      sAutobootCfg.data.nStateMachineOptions.bWaitBeforeLinkActivation = DSL_TRUE;\n+      sAutobootCfg.data.nStateMachineOptions.bWaitBeforeRestart        = DSL_TRUE;\n+\n+      nRet = (DSL_Error_t)DSL_CPE_Ioctl(\n+         DSL_CPE_GetGlobalContext()->fd[nDevice],\n+         DSL_FIO_AUTOBOOT_CONFIG_SET, (DSL_int_t)&sAutobootCfg);\n+\n+      if (nRet < DSL_SUCCESS)\n+      {\n+         DSL_CCA_DEBUG(DSL_CCA_DBG_ERR, (DSL_CPE_PREFIX\n+            \"Autoboot configuration for device (%d) failed!, nRet = %d!\"\n+            DSL_CPE_CRLF, nDevice, sAutobootCtl.accessCtl.nReturn));\n+      }\n+\n+      memset(&sAutobootCtl, 0, sizeof(DSL_AutobootControl_t));\n+      sAutobootCtl.data.nCommand = DSL_AUTOBOOT_CTRL_RESTART;\n+\n+      nRet = (DSL_Error_t)DSL_CPE_Ioctl(\n+         DSL_CPE_GetGlobalContext()->fd[nDevice],\n+         DSL_FIO_AUTOBOOT_CONTROL_SET, (DSL_int_t)&sAutobootCtl);\n+\n+      if (nRet < DSL_SUCCESS)\n+      {\n+         DSL_CCA_DEBUG(DSL_CCA_DBG_ERR, (DSL_CPE_PREFIX\n+            \"Autoboot restart for device (%d) failed!, nRet = %d!\"\n+            DSL_CPE_CRLF, nDevice, sAutobootCtl.accessCtl.nReturn));\n+      }\n+   }\n+\n+   DSL_CCA_DEBUG(DSL_CCA_DBG_MSG, (DSL_CPE_PREFIX\n+      \"Autoboot restart executed\" DSL_CPE_CRLF));\n+\n #ifdef INCLUDE_DSL_CPE_CLI_SUPPORT\n    for (nDevice = 0; nDevice < DSL_CPE_MAX_DSL_ENTITIES; nDevice++)\n    {\n"
  },
  {
    "path": "package/network/config/ltq-vdsl-app/patches/201-sigterm.patch",
    "content": "--- a/src/dsl_cpe_control.c\n+++ b/src/dsl_cpe_control.c\n@@ -6504,7 +6504,7 @@ DSL_CPE_STATIC  void DSL_CPE_Termination\n    /* ignore the signal, we'll handle by ourself */\n    signal (sig, SIG_IGN);\n \n-   if (sig == SIGINT)\n+   if (sig == SIGINT || sig == SIGTERM)\n    {\n       DSL_CCA_DEBUG(DSL_CCA_DBG_MSG, (DSL_CPE_PREFIX \"terminated\" DSL_CPE_CRLF));\n       DSL_CPE_Termination ();\n@@ -6803,6 +6803,7 @@ DSL_int_t dsl_cpe_daemon (\n \n #ifndef RTEMS\n    signal (SIGINT, DSL_CPE_TerminationHandler);\n+   signal (SIGTERM, DSL_CPE_TerminationHandler);\n #endif /* RTEMS*/\n \n    /* Open DSL_CPE_MAX_DSL_ENTITIES devices*/\n"
  },
  {
    "path": "package/network/config/ltq-vdsl-app/patches/300-ubus.patch",
    "content": "--- a/src/dsl_cpe_control.c\n+++ b/src/dsl_cpe_control.c\n@@ -177,6 +177,9 @@ extern DSL_Error_t DSL_CPE_Pipe_StaticRe\n #endif /* INCLUDE_DSL_RESOURCE_STATISTICS*/\n #endif\n \n+extern void ubus_init();\n+extern void ubus_deinit();\n+\n DSL_char_t *g_sFirmwareName1 = DSL_NULL;\n DSL_FirmwareFeatures_t g_nFwFeatures1 = {DSL_FW_XDSLMODE_CLEANED, DSL_FW_XDSLFEATURE_CLEANED,\n    DSL_FW_XDSLFEATURE_CLEANED};\n@@ -6806,6 +6809,8 @@ DSL_int_t dsl_cpe_daemon (\n    signal (SIGTERM, DSL_CPE_TerminationHandler);\n #endif /* RTEMS*/\n \n+   ubus_init();\n+\n    /* Open DSL_CPE_MAX_DSL_ENTITIES devices*/\n    for (nDevice = 0; nDevice < DSL_CPE_MAX_DSL_ENTITIES; nDevice++)\n    {\n@@ -7260,6 +7265,7 @@ DSL_int_t dsl_cpe_daemon (\n #endif /* INCLUDE_DSL_CPE_CLI_SUPPORT */\n \n DSL_CPE_CONTROL_EXIT:\n+   ubus_deinit();\n \n #ifdef INCLUDE_DSL_BONDING\n    DSL_CPE_BND_Stop((DSL_CPE_BND_Context_t*)pCtrlCtx->pBnd);\n--- a/src/Makefile.am\n+++ b/src/Makefile.am\n@@ -11,7 +11,7 @@ else\n dsl_cpe_control_common_ldflags =\n endif\n \n-dsl_cpe_control_LDADD = -lpthread -lrt\n+dsl_cpe_control_LDADD = -lpthread -lrt -lubox -lubus\n \n if INCLUDE_DSL_CPE_DTI_SUPPORT\n     dsl_cpe_control_LDADD += -ldti_agent\n@@ -66,7 +66,8 @@ dsl_cpe_control_SOURCES = \\\n \tdsl_cpe_control.c \\\n \tdsl_cpe_init_cfg.c \\\n \tdsl_cpe_linux.c \\\n-\tdsl_cpe_debug.c\n+\tdsl_cpe_debug.c \\\n+\tdsl_cpe_ubus.c\n \n dsl_cpe_control_SOURCES += \\\n \t$(dsl_cpe_control_dti_sources)\n"
  },
  {
    "path": "package/network/config/ltq-vdsl-app/src/src/dsl_cpe_ubus.c",
    "content": "// SPDX-License-Identifier: BSD-2-Clause\n/*\n * Copyright (C) 2020 Andre Heider <a.heider@gmail.com>\n */\n\n#include <sys/ioctl.h>\n#include <sys/stat.h>\n#include <sys/types.h>\n#include <fcntl.h>\n#include <libubus.h>\n#include <stdint.h>\n#include <stdio.h>\n#include <string.h>\n#include <unistd.h>\n\n#include \"dsl_cpe_control.h\"\n#include <drv_dsl_cpe_api_ioctl.h>\n#ifdef INCLUDE_DSL_CPE_API_VRX\n#include <drv_mei_cpe_interface.h>\n#endif\n\n#define U16(v1, v2) ( \\\n\t((uint16_t)(v1) << 8) | \\\n\t((uint16_t)(v2)))\n\n#define U32(v1, v2, v3, v4) ( \\\n\t((uint32_t)(v1) << 24) | \\\n\t((uint32_t)(v2) << 16) | \\\n\t((uint32_t)(v3) << 8) | \\\n\t((uint32_t)(v4)))\n\n#define STR_CASE(id, text) \\\n\tcase id: \\\n\t\tstr = text; \\\n\t\tbreak;\n\n#define STR_CASE_MAP(id, text, number) \\\n\tcase id: \\\n\t\tstr = text; \\\n\t\tmap = number; \\\n\t\tbreak;\n\n#define IOCTL(type, request) \\\n\ttype out; \\\n\tmemset(&out, 0, sizeof(type)); \\\n\tif (ioctl(fd, request, &out)) \\\n\t\treturn;\n\n#define IOCTL_DIR(type, request, dir) \\\n\ttype out; \\\n\tmemset(&out, 0, sizeof(type)); \\\n\tout.nDirection = dir; \\\n\tif (ioctl(fd, request, &out)) \\\n\t\treturn;\n\n#define IOCTL_DIR_DELT(type, request, dir, delt) \\\n\ttype out; \\\n\tmemset(&out, 0, sizeof(type)); \\\n\tout.nDirection = dir; \\\n\tout.nDeltDataType = delt; \\\n\tif (ioctl(fd, request, &out)) \\\n\t\treturn;\n\ntypedef enum {\n\tANNEX_UNKNOWN = 0,\n\tANNEX_A,\n\tANNEX_B,\n\tANNEX_C,\n\tANNEX_I,\n\tANNEX_J,\n\tANNEX_L,\n\tANNEX_M,\n} annex_t;\n\ntypedef enum {\n\tSTD_UNKNOWN = 0,\n\tSTD_T1_413,\n\tSTD_TS_101_388,\n\tSTD_G_992_1,\n\tSTD_G_992_2,\n\tSTD_G_992_3,\n\tSTD_G_992_4,\n\tSTD_G_992_5,\n\tSTD_G_993_1,\n\tSTD_G_993_2,\n} standard_t;\n\ntypedef enum {\n\tVECTOR_UNKNOWN = 0,\n\tVECTOR_OFF,\n\tVECTOR_ON_DS,\n\tVECTOR_ON_DS_US,\n} vector_t;\n\ntypedef enum {\n\tPROFILE_UNKNOWN = 0,\n\tPROFILE_8A,\n\tPROFILE_8B,\n\tPROFILE_8C,\n\tPROFILE_8D,\n\tPROFILE_12A,\n\tPROFILE_12B,\n\tPROFILE_17A,\n\tPROFILE_30A,\n\tPROFILE_35B,\n} profile_t;\n\n/* These values are exported via ubus and backwards compability\n * needs to be kept!\n */\nenum {\n\tLSTATE_MAP_UNKNOWN = -1,\n\tLSTATE_MAP_NOT_INITIALIZED,\n\tLSTATE_MAP_EXCEPTION,\n\tLSTATE_MAP_IDLE,\n\tLSTATE_MAP_SILENT,\n\tLSTATE_MAP_HANDSHAKE,\n\tLSTATE_MAP_FULL_INIT,\n\tLSTATE_MAP_SHOWTIME_NO_SYNC,\n\tLSTATE_MAP_SHOWTIME_TC_SYNC,\n\tLSTATE_MAP_RESYNC,\n};\n\n/* These values are exported via ubus and backwards compability\n * needs to be kept!\n */\nenum {\n\tPSTATE_MAP_UNKNOWN = -2,\n\tPSTATE_MAP_NA,\n\tPSTATE_MAP_L0,\n\tPSTATE_MAP_L1,\n\tPSTATE_MAP_L2,\n\tPSTATE_MAP_L3,\n};\n\nstatic DSL_CPE_ThreadCtrl_t thread;\nstatic struct ubus_context *ctx;\nstatic struct blob_buf b;\n\nstatic inline void m_double(const char *id, double value) {\n\tblobmsg_add_double(&b, id, value);\n}\n\nstatic inline void m_bool(const char *id, bool value) {\n\tblobmsg_add_u8(&b, id, value);\n}\n\nstatic inline void m_u32(const char *id, uint32_t value) {\n\tblobmsg_add_u32(&b, id, value);\n}\n\nstatic inline void m_str(const char *id, const char *value) {\n\tblobmsg_add_string(&b, id, value);\n}\n\nstatic inline void m_db(const char *id, int value) {\n\tm_double(id, (double)value / 10);\n}\n\nstatic inline void m_array(const char *id, const uint8_t *value, uint8_t len) {\n\tvoid *c = blobmsg_open_array(&b, id);\n\n\tfor (uint8_t i = 0; i < len; ++i)\n\t\tblobmsg_add_u16(&b, \"\", value[i]);\n\n\tblobmsg_close_array(&b, c);\n}\n\nstatic void m_vendor(const char *id, const uint8_t *value) {\n\t// ITU-T T.35: U.S.\n\tif (U16(value[0], value[1]) != 0xb500)\n\t\treturn;\n\n\tconst char *str = NULL;\n\tswitch (U32(value[2], value[3], value[4], value[5])) {\n\tSTR_CASE(0x414C4342, \"Alcatel\")\n\tSTR_CASE(0x414E4456, \"Analog Devices\")\n\tSTR_CASE(0x4244434D, \"Broadcom\")\n\tSTR_CASE(0x43454E54, \"Centillium\")\n\tSTR_CASE(0x4753504E, \"Globespan\")\n\tSTR_CASE(0x494B4E53, \"Ikanos\")\n\tSTR_CASE(0x4946544E, \"Infineon\")\n\tSTR_CASE(0x54535443, \"Texas Instruments\")\n\tSTR_CASE(0x544D4D42, \"Thomson MultiMedia Broadband\")\n\tSTR_CASE(0x5443544E, \"Trend Chip Technologies\")\n\tSTR_CASE(0x53544D49, \"ST Micro\")\n\t};\n\n\tif (!str)\n\t\treturn;\n\n\tif ((value[6] == 0) && (value[7] == 0)) {\n\t\tm_str(id, str);\n\t\treturn;\n\t}\n\n\tchar buf[64];\n\tsprintf(buf, \"%s %d.%d\", str, value[6], value[7]);\n\tm_str(id, buf);\n\n\treturn;\n}\n\nannex_t get_annex(const uint8_t *xtse) {\n\tif ((xtse[0] & XTSE_1_01_A_T1_413) ||\n\t    (xtse[0] & XTSE_1_03_A_1_NO) ||\n\t    (xtse[0] & XTSE_1_04_A_1_O) ||\n\t    (xtse[1] & XTSE_2_01_A_2_NO) ||\n\t    (xtse[2] & XTSE_3_03_A_3_NO) ||\n\t    (xtse[2] & XTSE_3_04_A_3_O) ||\n\t    (xtse[3] & XTSE_4_01_A_4_NO) ||\n\t    (xtse[3] & XTSE_4_02_A_4_O) ||\n\t    (xtse[5] & XTSE_6_01_A_5_NO) ||\n\t    (xtse[5] & XTSE_6_02_A_5_O) ||\n\t    (xtse[7] & XTSE_8_01_A))\n\t\treturn ANNEX_A;\n\n\tif ((xtse[0] & XTSE_1_05_B_1_NO) ||\n\t    (xtse[0] & XTSE_1_06_B_1_O) ||\n\t    (xtse[1] & XTSE_2_02_B_2_O) ||\n\t    (xtse[2] & XTSE_3_05_B_3_NO) ||\n\t    (xtse[2] & XTSE_3_06_B_3_O) ||\n\t    (xtse[5] & XTSE_6_03_B_5_NO) ||\n\t    (xtse[5] & XTSE_6_04_B_5_O) ||\n\t    (xtse[7] & XTSE_8_02_B))\n\t\treturn ANNEX_B;\n\n\tif ((xtse[0] & XTSE_1_02_C_TS_101388) ||\n\t    (xtse[0] & XTSE_1_07_C_1_NO) ||\n\t    (xtse[0] & XTSE_1_08_C_1_O) ||\n\t    (xtse[1] & XTSE_2_03_C_2_NO) ||\n\t    (xtse[1] & XTSE_2_04_C_2_O) ||\n\t    (xtse[7] & XTSE_8_03_C))\n\t\treturn ANNEX_C;\n\n\tif ((xtse[3] & XTSE_4_05_I_3_NO) ||\n\t    (xtse[3] & XTSE_4_06_I_3_O) ||\n\t    (xtse[4] & XTSE_5_01_I_4_NO) ||\n\t    (xtse[4] & XTSE_5_02_I_4_O) ||\n\t    (xtse[5] & XTSE_6_07_I_5_NO) ||\n\t    (xtse[5] & XTSE_6_08_I_5_O))\n\t\treturn ANNEX_I;\n\n\tif ((xtse[3] & XTSE_4_07_J_3_NO) ||\n\t    (xtse[3] & XTSE_4_08_J_3_O) ||\n\t    (xtse[6] & XTSE_7_01_J_5_NO) ||\n\t    (xtse[6] & XTSE_7_02_J_5_O))\n\t\treturn ANNEX_J;\n\n\tif ((xtse[4] & XTSE_5_03_L_3_NO) ||\n\t    (xtse[4] & XTSE_5_04_L_3_NO) ||\n\t    (xtse[4] & XTSE_5_05_L_3_O) ||\n\t    (xtse[4] & XTSE_5_06_L_3_O))\n\t\treturn ANNEX_L;\n\n\tif ((xtse[4] & XTSE_5_07_M_3_NO) ||\n\t    (xtse[4] & XTSE_5_08_M_3_O) ||\n\t    (xtse[6] & XTSE_7_03_M_5_NO) ||\n\t    (xtse[6] & XTSE_7_04_M_5_O))\n\t\treturn ANNEX_M;\n\n\treturn ANNEX_UNKNOWN;\n}\n\nstatic standard_t get_standard(const uint8_t *xtse) {\n\tif (xtse[0] & XTSE_1_01_A_T1_413)\n\t\treturn STD_T1_413;\n\n\tif (xtse[0] & XTSE_1_02_C_TS_101388)\n\t\treturn STD_TS_101_388;\n\n\tif ((xtse[0] & XTSE_1_03_A_1_NO) ||\n\t    (xtse[0] & XTSE_1_04_A_1_O) ||\n\t    (xtse[0] & XTSE_1_05_B_1_NO) ||\n\t    (xtse[0] & XTSE_1_06_B_1_O) ||\n\t    (xtse[0] & XTSE_1_07_C_1_NO) ||\n\t    (xtse[0] & XTSE_1_08_C_1_O))\n\t\treturn STD_G_992_1;\n\n\tif ((xtse[1] & XTSE_2_01_A_2_NO) ||\n\t    (xtse[1] & XTSE_2_02_B_2_O) ||\n\t    (xtse[1] & XTSE_2_03_C_2_NO) ||\n\t    (xtse[1] & XTSE_2_04_C_2_O))\n\t\treturn STD_G_992_2;\n\n\tif ((xtse[2] & XTSE_3_03_A_3_NO) ||\n\t    (xtse[2] & XTSE_3_04_A_3_O) ||\n\t    (xtse[2] & XTSE_3_05_B_3_NO) ||\n\t    (xtse[2] & XTSE_3_06_B_3_O) ||\n\t    (xtse[3] & XTSE_4_05_I_3_NO) ||\n\t    (xtse[3] & XTSE_4_06_I_3_O) ||\n\t    (xtse[3] & XTSE_4_07_J_3_NO) ||\n\t    (xtse[3] & XTSE_4_08_J_3_O) ||\n\t    (xtse[4] & XTSE_5_03_L_3_NO) ||\n\t    (xtse[4] & XTSE_5_04_L_3_NO) ||\n\t    (xtse[4] & XTSE_5_05_L_3_O) ||\n\t    (xtse[4] & XTSE_5_06_L_3_O) ||\n\t    (xtse[4] & XTSE_5_07_M_3_NO) ||\n\t    (xtse[4] & XTSE_5_08_M_3_O))\n\t\treturn STD_G_992_3;\n\n\tif ((xtse[3] & XTSE_4_01_A_4_NO) ||\n\t    (xtse[3] & XTSE_4_02_A_4_O) ||\n\t    (xtse[4] & XTSE_5_01_I_4_NO) ||\n\t    (xtse[4] & XTSE_5_02_I_4_O))\n\t\treturn STD_G_992_4;\n\n\tif ((xtse[5] & XTSE_6_01_A_5_NO) ||\n\t    (xtse[5] & XTSE_6_02_A_5_O) ||\n\t    (xtse[5] & XTSE_6_03_B_5_NO) ||\n\t    (xtse[5] & XTSE_6_04_B_5_O) ||\n\t    (xtse[5] & XTSE_6_07_I_5_NO) ||\n\t    (xtse[5] & XTSE_6_08_I_5_O) ||\n\t    (xtse[6] & XTSE_7_01_J_5_NO) ||\n\t    (xtse[6] & XTSE_7_02_J_5_O) ||\n\t    (xtse[6] & XTSE_7_03_M_5_NO) ||\n\t    (xtse[6] & XTSE_7_04_M_5_O))\n\t\treturn STD_G_992_5;\n\n\tif (xtse[7] & XTSE_8_08)\n\t\treturn STD_G_993_1;\n\n\tif ((xtse[7] & XTSE_8_01_A) ||\n\t    (xtse[7] & XTSE_8_02_B) ||\n\t    (xtse[7] & XTSE_8_03_C))\n\t\treturn STD_G_993_2;\n\n\treturn STD_UNKNOWN;\n}\n\nstatic void version_information(int fd) {\n\tIOCTL(DSL_VersionInformation_t, DSL_FIO_VERSION_INFORMATION_GET)\n\n\tm_str(\"api_version\", out.data.DSL_DriverVersionApi);\n\tm_str(\"firmware_version\", out.data.DSL_ChipSetFWVersion);\n\tm_str(\"chipset\", out.data.DSL_ChipSetType);\n\tm_str(\"driver_version\", out.data.DSL_DriverVersionMeiBsp);\n}\n\nstatic void line_state(int fd) {\n\tIOCTL(DSL_LineState_t, DSL_FIO_LINE_STATE_GET)\n\n\tint map = LSTATE_MAP_UNKNOWN;\n\tconst char *str;\n\tswitch (out.data.nLineState) {\n\tSTR_CASE_MAP(DSL_LINESTATE_NOT_INITIALIZED, \"Not initialized\", LSTATE_MAP_NOT_INITIALIZED)\n\tSTR_CASE_MAP(DSL_LINESTATE_EXCEPTION, \"Exception\", LSTATE_MAP_EXCEPTION)\n\tSTR_CASE(DSL_LINESTATE_NOT_UPDATED, \"Not updated\")\n\tSTR_CASE(DSL_LINESTATE_IDLE_REQUEST, \"Idle request\")\n\tSTR_CASE_MAP(DSL_LINESTATE_IDLE, \"Idle\", LSTATE_MAP_IDLE)\n\tSTR_CASE(DSL_LINESTATE_SILENT_REQUEST, \"Silent request\")\n\tSTR_CASE_MAP(DSL_LINESTATE_SILENT, \"Silent\", LSTATE_MAP_SILENT)\n\tSTR_CASE_MAP(DSL_LINESTATE_HANDSHAKE, \"Handshake\", LSTATE_MAP_HANDSHAKE)\n\tSTR_CASE(DSL_LINESTATE_BONDING_CLR, \"Bonding CLR\")\n\tSTR_CASE_MAP(DSL_LINESTATE_FULL_INIT, \"Full init\", LSTATE_MAP_FULL_INIT)\n\tSTR_CASE(DSL_LINESTATE_SHORT_INIT_ENTRY, \"Short init entry\")\n\tSTR_CASE(DSL_LINESTATE_DISCOVERY, \"Discovery\")\n\tSTR_CASE(DSL_LINESTATE_TRAINING, \"Training\")\n\tSTR_CASE(DSL_LINESTATE_ANALYSIS, \"Analysis\")\n\tSTR_CASE(DSL_LINESTATE_EXCHANGE, \"Exchange\")\n\tSTR_CASE_MAP(DSL_LINESTATE_SHOWTIME_NO_SYNC, \"Showtime without TC-Layer sync\", LSTATE_MAP_SHOWTIME_NO_SYNC)\n\tSTR_CASE_MAP(DSL_LINESTATE_SHOWTIME_TC_SYNC, \"Showtime with TC-Layer sync\", LSTATE_MAP_SHOWTIME_TC_SYNC)\n\tSTR_CASE(DSL_LINESTATE_FASTRETRAIN, \"Fastretrain\")\n\tSTR_CASE(DSL_LINESTATE_LOWPOWER_L2, \"Lowpower L2\")\n\tSTR_CASE(DSL_LINESTATE_LOOPDIAGNOSTIC_ACTIVE, \"Loopdiagnostic active\")\n\tSTR_CASE(DSL_LINESTATE_LOOPDIAGNOSTIC_DATA_EXCHANGE, \"Loopdiagnostic data exchange\")\n\tSTR_CASE(DSL_LINESTATE_LOOPDIAGNOSTIC_DATA_REQUEST, \"Loopdiagnostic data request\")\n\tSTR_CASE(DSL_LINESTATE_LOOPDIAGNOSTIC_COMPLETE, \"Loopdiagnostic complete\")\n\tSTR_CASE_MAP(DSL_LINESTATE_RESYNC, \"Resync\", LSTATE_MAP_RESYNC)\n\tSTR_CASE(DSL_LINESTATE_TEST, \"Test\")\n\tSTR_CASE(DSL_LINESTATE_TEST_LOOP, \"Test loop\")\n\tSTR_CASE(DSL_LINESTATE_TEST_REVERB, \"Test reverb\")\n\tSTR_CASE(DSL_LINESTATE_TEST_MEDLEY, \"Test medley\")\n\tSTR_CASE(DSL_LINESTATE_TEST_SHOWTIME_LOCK, \"Showtime lock\")\n\tSTR_CASE(DSL_LINESTATE_TEST_QUIET, \"Quiet\")\n\tSTR_CASE(DSL_LINESTATE_LOWPOWER_L3, \"Lowpower L3\")\n#ifndef INCLUDE_DSL_CPE_API_DANUBE\n\tSTR_CASE(DSL_LINESTATE_DISABLED, \"Disabled\")\n\tSTR_CASE(DSL_LINESTATE_T1413, \"T1413\")\n\tSTR_CASE(DSL_LINESTATE_ORDERLY_SHUTDOWN_REQUEST, \"Orderly shutdown request\")\n\tSTR_CASE(DSL_LINESTATE_ORDERLY_SHUTDOWN, \"Orderly shutdown\")\n\tSTR_CASE(DSL_LINESTATE_TEST_FILTERDETECTION_ACTIVE, \"Test filterdetection active\")\n\tSTR_CASE(DSL_LINESTATE_TEST_FILTERDETECTION_COMPLETE, \"Test filterdetection complete\")\n#endif\n\tdefault:\n\t\tstr = NULL;\n\t\tbreak;\n\t};\n\n\tif (str)\n\t\tm_str(\"state\", str);\n\n\tif (map != LSTATE_MAP_UNKNOWN )\n\t\tm_u32(\"state_num\", map);\n\n\tm_bool(\"up\", out.data.nLineState == DSL_LINESTATE_SHOWTIME_TC_SYNC);\n}\n\nstatic void pm_channel_counters_showtime(int fd) {\n\tIOCTL_DIR(DSL_PM_ChannelCounters_t, DSL_FIO_PM_CHANNEL_COUNTERS_SHOWTIME_GET, DSL_NEAR_END);\n\n\tm_u32(\"uptime\", out.interval.nElapsedTime);\n}\n\nstatic void g997_line_inventory(int fd) {\n\tIOCTL_DIR(DSL_G997_LineInventory_t, DSL_FIO_G997_LINE_INVENTORY_GET, DSL_DOWNSTREAM)\n\n\tm_array(\"vendor_id\", out.data.G994VendorID, DSL_G997_LI_MAXLEN_VENDOR_ID);\n\tm_vendor(\"vendor\", out.data.G994VendorID);\n\tm_array(\"system_vendor_id\", out.data.SystemVendorID, DSL_G997_LI_MAXLEN_VENDOR_ID);\n\tm_vendor(\"system_vendor\", out.data.SystemVendorID);\n\tm_array(\"version\", out.data.VersionNumber, DSL_G997_LI_MAXLEN_VERSION);\n\tm_array(\"serial\", out.data.SerialNumber, DSL_G997_LI_MAXLEN_SERIAL);\n}\n\nstatic void g997_power_management_status(int fd) {\n\tIOCTL(DSL_G997_PowerManagementStatus_t, DSL_FIO_G997_POWER_MANAGEMENT_STATUS_GET)\n\n\tint map = PSTATE_MAP_UNKNOWN;\n\tconst char *str;\n\tswitch (out.data.nPowerManagementStatus) {\n\tSTR_CASE_MAP(DSL_G997_PMS_NA, \"Power management state is not available\", PSTATE_MAP_NA)\n\tSTR_CASE_MAP(DSL_G997_PMS_L0, \"L0 - Synchronized\", PSTATE_MAP_L0)\n\tSTR_CASE_MAP(DSL_G997_PMS_L1, \"L1 - Power Down Data transmission (G.992.2)\", PSTATE_MAP_L1)\n\tSTR_CASE_MAP(DSL_G997_PMS_L2, \"L2 - Power Down Data transmission (G.992.3 and G.992.4)\", PSTATE_MAP_L2)\n\tSTR_CASE_MAP(DSL_G997_PMS_L3, \"L3 - No power\", PSTATE_MAP_L3)\n\tdefault:\n\t\tstr = NULL;\n\t\tbreak;\n\t};\n\n\tif (str)\n\t\tm_str(\"power_state\", str);\n\n\tif (map != PSTATE_MAP_UNKNOWN)\n\t\tm_u32(\"power_state_num\", map);\n}\n\nstatic void g997_xtu_system_enabling(int fd, standard_t *standard) {\n\tIOCTL(DSL_G997_XTUSystemEnabling_t, DSL_FIO_G997_XTU_SYSTEM_ENABLING_STATUS_GET)\n\n\tm_array(\"xtse\", out.data.XTSE, DSL_G997_NUM_XTSE_OCTETS);\n\n\tconst char *str;\n\tswitch (get_annex(out.data.XTSE)) {\n\tSTR_CASE(ANNEX_A, \"A\")\n\tSTR_CASE(ANNEX_B, \"B\")\n\tSTR_CASE(ANNEX_C, \"C\")\n\tSTR_CASE(ANNEX_I, \"I\")\n\tSTR_CASE(ANNEX_J, \"J\")\n\tSTR_CASE(ANNEX_L, \"L\")\n\tSTR_CASE(ANNEX_M, \"M\")\n\tdefault:\n\t\tstr = NULL;\n\t\tbreak;\n\t};\n\tif (str)\n\t\tm_str(\"annex\", str);\n\n\t*standard = get_standard(out.data.XTSE);\n\n\tswitch (*standard) {\n\tSTR_CASE(STD_T1_413, \"T1.413\")\n\tSTR_CASE(STD_TS_101_388, \"TS 101 388\")\n\tSTR_CASE(STD_G_992_1, \"G.992.1\")\n\tSTR_CASE(STD_G_992_2, \"G.992.2\")\n\tSTR_CASE(STD_G_992_3, \"G.992.3\")\n\tSTR_CASE(STD_G_992_4, \"G.992.4\")\n\tSTR_CASE(STD_G_992_5, \"G.992.5\")\n\tSTR_CASE(STD_G_993_1, \"G.993.1\")\n\tSTR_CASE(STD_G_993_2, \"G.993.2\")\n\tdefault:\n\t\tstr = NULL;\n\t\tbreak;\n\t}\n\tif (str)\n\t\tm_str(\"standard\", str);\n}\n\nstatic void get_vector_status(int fd, vector_t *status) {\n\t*status = VECTOR_UNKNOWN;\n\n#ifdef INCLUDE_DSL_CPE_API_VRX\n\tif (fd < 0)\n\t\treturn;\n\n\tIOCTL(IOCTL_MEI_dsmStatus_t, FIO_MEI_DSM_STATUS_GET);\n\n\tswitch (out.eVectorStatus) {\n\tcase e_MEI_VECTOR_STAT_OFF:\n\t\t*status = VECTOR_OFF;\n\t\tbreak;\n\tcase e_MEI_VECTOR_STAT_ON_DS:\n\t\t*status = VECTOR_ON_DS;\n\t\tbreak;\n\tcase e_MEI_VECTOR_STAT_ON_DS_US:\n\t\t*status = VECTOR_ON_DS_US;\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t};\n#endif\n}\n\nstatic void vector_erb(int fd) {\n#ifdef INCLUDE_DSL_CPE_API_VRX\n\tif (fd < 0)\n\t\treturn;\n\n\tIOCTL(IOCTL_MEI_dsmStatistics_t, FIO_MEI_DSM_STATISTICS_GET);\n\n\tm_u32(\"sent\", out.n_processed);\n\tm_u32(\"discarded\", out.n_fw_dropped_size + out.n_mei_dropped_size + out.n_mei_dropped_no_pp_cb + out.n_pp_dropped);\n#endif\n}\n\nstatic void band_plan_status(int fd, profile_t *profile) {\n#if (INCLUDE_DSL_CPE_API_VDSL_SUPPORT == 1)\n\tIOCTL(DSL_BandPlanStatus_t, DSL_FIO_BAND_PLAN_STATUS_GET)\n\n\tswitch (out.data.nProfile) {\n\tcase DSL_PROFILE_8A:\n\t\t*profile = PROFILE_8A;\n\t\tbreak;\n\tcase DSL_PROFILE_8B:\n\t\t*profile = PROFILE_8B;\n\t\tbreak;\n\tcase DSL_PROFILE_8C:\n\t\t*profile = PROFILE_8C;\n\t\tbreak;\n\tcase DSL_PROFILE_8D:\n\t\t*profile = PROFILE_8D;\n\t\tbreak;\n\tcase DSL_PROFILE_12A:\n\t\t*profile = PROFILE_12A;\n\t\tbreak;\n\tcase DSL_PROFILE_12B:\n\t\t*profile = PROFILE_12B;\n\t\tbreak;\n\tcase DSL_PROFILE_17A:\n\t\t*profile = PROFILE_17A;\n\t\tbreak;\n\tcase DSL_PROFILE_30A:\n\t\t*profile = PROFILE_30A;\n\t\tbreak;\n\tcase DSL_PROFILE_35B:\n\t\t*profile = PROFILE_35B;\n\t\tbreak;\n\tdefault:\n\t\t*profile = PROFILE_UNKNOWN;\n\t\tbreak;\n\t};\n\n\tconst char *str;\n\tswitch (*profile) {\n\tSTR_CASE(PROFILE_8A, \"8a\")\n\tSTR_CASE(PROFILE_8B, \"8b\")\n\tSTR_CASE(PROFILE_8C, \"8c\")\n\tSTR_CASE(PROFILE_8D, \"8d\")\n\tSTR_CASE(PROFILE_12A, \"12a\")\n\tSTR_CASE(PROFILE_12B, \"12b\")\n\tSTR_CASE(PROFILE_17A, \"17a\")\n\tSTR_CASE(PROFILE_30A, \"30a\")\n\tSTR_CASE(PROFILE_35B, \"35b\")\n\tdefault:\n\t\tstr = NULL;\n\t\tbreak;\n\t};\n\tif (str)\n\t\tm_str(\"profile\", str);\n#endif\n}\n\nstatic void line_feature_config(int fd, DSL_AccessDir_t direction) {\n\tIOCTL_DIR(DSL_LineFeature_t, DSL_FIO_LINE_FEATURE_STATUS_GET, direction)\n\n\tm_bool(\"trellis\", out.data.bTrellisEnable);\n\tm_bool(\"bitswap\", out.data.bBitswapEnable);\n\tm_bool(\"retx\", out.data.bReTxEnable);\n\tm_bool(\"virtual_noise\", out.data.bVirtualNoiseSupport);\n}\n\nstatic void g997_channel_status(int fd, DSL_AccessDir_t direction) {\n\tIOCTL_DIR(DSL_G997_ChannelStatus_t, DSL_FIO_G997_CHANNEL_STATUS_GET, direction);\n\n\tm_u32(\"interleave_delay\", out.data.ActualInterleaveDelay * 10);\n#ifndef INCLUDE_DSL_CPE_API_DANUBE\n\t// prefer ACTNDR, see comments in drv_dsl_cpe_api_g997.h\n\tm_u32(\"data_rate\", out.data.ActualNetDataRate);\n#else\n\tm_u32(\"data_rate\", out.data.ActualDataRate);\n#endif\n}\n\nstatic void g997_line_status(int fd, DSL_AccessDir_t direction) {\n\tIOCTL_DIR_DELT(DSL_G997_LineStatus_t, DSL_FIO_G997_LINE_STATUS_GET, direction, DSL_DELT_DATA_SHOWTIME);\n\n\tm_db(\"latn\", out.data.LATN);\n\tm_db(\"satn\", out.data.SATN);\n\tm_db(\"snr\", out.data.SNR);\n\tm_db(\"actps\", out.data.ACTPS);\n\tm_db(\"actatp\", out.data.ACTATP);\n\tm_u32(\"attndr\", out.data.ATTNDR);\n}\n\nstatic void pm_line_sec_counters_total(int fd, DSL_XTUDir_t direction) {\n\tIOCTL_DIR(DSL_PM_LineSecCountersTotal_t, DSL_FIO_PM_LINE_SEC_COUNTERS_TOTAL_GET, direction)\n\n\tm_u32(\"es\", out.data.nES);\n\tm_u32(\"ses\", out.data.nSES);\n\tm_u32(\"loss\", out.data.nLOSS);\n\tm_u32(\"uas\", out.data.nUAS);\n\tm_u32(\"lofs\", out.data.nLOFS);\n#ifndef INCLUDE_DSL_CPE_API_DANUBE\n\tm_u32(\"fecs\", out.data.nFECS);\n#endif\n}\n\nstatic void pm_data_path_counters_total(int fd, DSL_XTUDir_t direction) {\n\tIOCTL_DIR(DSL_PM_DataPathCountersTotal_t, DSL_FIO_PM_DATA_PATH_COUNTERS_TOTAL_GET, direction);\n\n\tm_u32(\"hec\", out.data.nHEC);\n\tm_u32(\"ibe\", out.data.nIBE);\n\tm_u32(\"crc_p\", out.data.nCRC_P);\n\tm_u32(\"crcp_p\", out.data.nCRCP_P);\n\tm_u32(\"cv_p\", out.data.nCV_P);\n\tm_u32(\"cvp_p\", out.data.nCVP_P);\n}\n\nstatic void retx_statistics(int fd, DSL_XTUDir_t direction) {\n#ifdef INCLUDE_DSL_CPE_PM_RETX_COUNTERS\n#ifdef INCLUDE_DSL_CPE_PM_RETX_THRESHOLDS\n\tIOCTL_DIR(DSL_ReTxStatistics_t, DSL_FIO_RETX_STATISTICS_GET, direction);\n\n\tm_u32(\"rx_corrupted\", out.data.nRxCorruptedTotal);\n\tm_u32(\"rx_uncorrected_protected\", out.data.nRxUncorrectedProtected);\n\tm_u32(\"rx_retransmitted\", out.data.nRxRetransmitted);\n\tm_u32(\"rx_corrected\", out.data.nRxCorrected);\n\tm_u32(\"tx_retransmitted\", out.data.nTxRetransmitted);\n#endif\n#endif\n}\n\nstatic void describe_mode(standard_t standard, profile_t profile, vector_t vector) {\n\tchar buf[128];\n\n\tswitch (standard) {\n\tcase STD_T1_413:\n\t\tstrcpy(buf, \"T1.413\");\n\t\tbreak;\n\tcase STD_TS_101_388:\n\t\tstrcpy(buf, \"TS 101 388\");\n\t\tbreak;\n\tcase STD_G_992_1:\n\t\tstrcpy(buf, \"G.992.1 (ADSL)\");\n\t\tbreak;\n\tcase STD_G_992_2:\n\t\tstrcpy(buf, \"G.992.2 (ADSL lite)\");\n\t\tbreak;\n\tcase STD_G_992_3:\n\t\tstrcpy(buf, \"G.992.3 (ADSL2)\");\n\t\tbreak;\n\tcase STD_G_992_4:\n\t\tstrcpy(buf, \"G.992.4 (ADSL2 lite)\");\n\t\tbreak;\n\tcase STD_G_992_5:\n\t\tstrcpy(buf, \"G.992.5 (ADSL2+)\");\n\t\tbreak;\n\tcase STD_G_993_1:\n\t\tstrcpy(buf, \"G.993.1 (VDSL)\");\n\t\tbreak;\n\tcase STD_G_993_2:\n\t\tstrcpy(buf, \"G.993.2 (VDSL2\");\n\n\t\tswitch (profile) {\n\t\tcase PROFILE_8A:\n\t\t\tstrcat(buf, \", Profile 8a\");\n\t\t\tbreak;\n\t\tcase PROFILE_8B:\n\t\t\tstrcat(buf, \", Profile 8b\");\n\t\t\tbreak;\n\t\tcase PROFILE_8C:\n\t\t\tstrcat(buf, \", Profile 8c\");\n\t\t\tbreak;\n\t\tcase PROFILE_8D:\n\t\t\tstrcat(buf, \", Profile 8d\");\n\t\t\tbreak;\n\t\tcase PROFILE_12A:\n\t\t\tstrcat(buf, \", Profile 12a\");\n\t\t\tbreak;\n\t\tcase PROFILE_12B:\n\t\t\tstrcat(buf, \", Profile 12b\");\n\t\t\tbreak;\n\t\tcase PROFILE_17A:\n\t\t\tstrcat(buf, \", Profile 17a\");\n\t\t\tbreak;\n\t\tcase PROFILE_30A:\n\t\t\tstrcat(buf, \", Profile 30a\");\n\t\t\tbreak;\n\t\tcase PROFILE_35B:\n\t\t\tstrcat(buf, \", Profile 35b\");\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tbreak;\n\t\t};\n\n\t\tswitch (vector) {\n\t\tcase VECTOR_ON_DS:\n\t\t\tstrcat(buf, \", with downstream vectoring\");\n\t\t\tbreak;\n\t\tcase VECTOR_ON_DS_US:\n\t\t\tstrcat(buf, \", with down- and upstream vectoring\");\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tbreak;\n\t\t};\n\n\t\tstrcat(buf, \")\");\n\t\tbreak;\n\tdefault:\n\t\treturn;\n\t};\n\n\tm_str(\"mode\", buf);\n}\n\nstatic int metrics(struct ubus_context *ctx, struct ubus_object *obj,\n\t\t   struct ubus_request_data *req, const char *method,\n\t\t   struct blob_attr *msg)\n{\n\tint fd, fd_mei;\n\tvoid *c, *c2;\n\tstandard_t standard = STD_UNKNOWN;\n\tprofile_t profile = PROFILE_UNKNOWN;\n\tvector_t vector = VECTOR_UNKNOWN;\n\n#ifndef INCLUDE_DSL_CPE_API_DANUBE\n\tfd = open(DSL_CPE_DEVICE_NAME \"/0\", O_RDWR, 0644);\n#else\n\tfd = open(DSL_CPE_DEVICE_NAME, O_RDWR, 0644);\n#endif\n\tif (fd < 0)\n\t\treturn UBUS_STATUS_UNKNOWN_ERROR;\n\n#ifdef INCLUDE_DSL_CPE_API_VRX\n\tfd_mei = open(DSL_CPE_DSL_LOW_DEV \"/0\", O_RDWR, 0644);\n#else\n\tfd_mei = -1;\n#endif\n\n\tblob_buf_init(&b, 0);\n\n\tversion_information(fd);\n\tline_state(fd);\n\tpm_channel_counters_showtime(fd);\n\n\tc = blobmsg_open_table(&b, \"atu_c\");\n\tg997_line_inventory(fd);\n\tblobmsg_close_table(&b, c);\n\n\tg997_power_management_status(fd);\n\tg997_xtu_system_enabling(fd, &standard);\n\n\tif (standard == STD_G_993_2) {\n\t\tband_plan_status(fd, &profile);\n\t\tget_vector_status(fd_mei, &vector);\n\t}\n\n\tdescribe_mode(standard, profile, vector);\n\n\tc = blobmsg_open_table(&b, \"upstream\");\n\tswitch (vector) {\n\tcase VECTOR_OFF:\n\t\tm_bool(\"vector\", false);\n\t\tbreak;\n\tcase VECTOR_ON_DS_US:\n\t\tm_bool(\"vector\", true);\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t};\n\tline_feature_config(fd, DSL_UPSTREAM);\n\tg997_channel_status(fd, DSL_UPSTREAM);\n\tg997_line_status(fd, DSL_UPSTREAM);\n\tblobmsg_close_table(&b, c);\n\n\tc = blobmsg_open_table(&b, \"downstream\");\n\tswitch (vector) {\n\tcase VECTOR_OFF:\n\t\tm_bool(\"vector\", false);\n\t\tbreak;\n\tcase VECTOR_ON_DS:\n\tcase VECTOR_ON_DS_US:\n\t\tm_bool(\"vector\", true);\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t};\n\tline_feature_config(fd, DSL_DOWNSTREAM);\n\tg997_channel_status(fd, DSL_DOWNSTREAM);\n\tg997_line_status(fd, DSL_DOWNSTREAM);\n\tblobmsg_close_table(&b, c);\n\n\tc = blobmsg_open_table(&b, \"errors\");\n\tc2 = blobmsg_open_table(&b, \"near\");\n\tpm_line_sec_counters_total(fd, DSL_NEAR_END);\n\tpm_data_path_counters_total(fd, DSL_NEAR_END);\n\tretx_statistics(fd, DSL_NEAR_END);\n\tblobmsg_close_table(&b, c2);\n\n\tc2 = blobmsg_open_table(&b, \"far\");\n\tpm_line_sec_counters_total(fd, DSL_FAR_END);\n\tpm_data_path_counters_total(fd, DSL_FAR_END);\n\tretx_statistics(fd, DSL_FAR_END);\n\tblobmsg_close_table(&b, c2);\n\tblobmsg_close_table(&b, c);\n\n\tswitch (vector) {\n\tcase VECTOR_ON_DS:\n\tcase VECTOR_ON_DS_US:\n\t\tc = blobmsg_open_table(&b, \"erb\");\n\t\tvector_erb(fd_mei);\n\t\tblobmsg_close_table(&b, c);\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t};\n\n\tubus_send_reply(ctx, req, b.head);\n\n\tif (fd_mei >= 0)\n\t\tclose(fd_mei);\n\tclose(fd);\n\n\treturn 0;\n}\n\nstatic const struct ubus_method dsl_methods[] = {\n\tUBUS_METHOD_NOARG(\"metrics\", metrics),\n};\n\nstatic struct ubus_object_type dsl_object_type =\n\tUBUS_OBJECT_TYPE(\"dsl\", dsl_methods);\n\nstatic struct ubus_object dsl_object = {\n\t.name = \"dsl\",\n\t.type = &dsl_object_type,\n\t.methods = dsl_methods,\n\t.n_methods = ARRAY_SIZE(dsl_methods),\n};\n\nstatic DSL_int_t ubus_main(DSL_CPE_Thread_Params_t *params) {\n\tuloop_run();\n\treturn 0;\n}\n\nvoid ubus_init() {\n\tuloop_init();\n\n\tctx = ubus_connect(NULL);\n\tif (!ctx)\n\t\treturn;\n\n\tif (ubus_add_object(ctx, &dsl_object)) {\n\t\tubus_free(ctx);\n\t\tctx = NULL;\n\t\treturn;\n\t}\n\n\tubus_add_uloop(ctx);\n\n\tDSL_CPE_ThreadInit(&thread, \"ubus\", ubus_main, DSL_CPE_PIPE_STACK_SIZE, DSL_CPE_PIPE_PRIORITY, 0, 0);\n}\n\nvoid ubus_deinit() {\n\tif (!ctx)\n\t\treturn;\n\n\tubus_free(ctx);\n\tuloop_done();\n\n\tDSL_CPE_ThreadShutdown(&thread, 1000);\n}\n"
  },
  {
    "path": "package/network/config/netifd/Makefile",
    "content": "include $(TOPDIR)/rules.mk\n\nPKG_NAME:=netifd\nPKG_RELEASE:=1\n\nPKG_SOURCE_PROTO:=git\nPKG_SOURCE_URL=$(PROJECT_GIT)/project/netifd.git\nPKG_SOURCE_DATE:=2022-02-20\nPKG_SOURCE_VERSION:=136006b88826feff4f0a36ffab511d1366483cf2\nPKG_MIRROR_HASH:=6358738d20e6df27b82c3bdb575fba0fdad8bef45a3c7479b93a5587c465dba4\nPKG_MAINTAINER:=Felix Fietkau <nbd@nbd.name>\n\nPKG_LICENSE:=GPL-2.0\nPKG_LICENSE_FILES:=\n\ninclude $(INCLUDE_DIR)/package.mk\ninclude $(INCLUDE_DIR)/cmake.mk\n\ndefine Package/netifd\n  SECTION:=base\n  CATEGORY:=Base system\n  DEPENDS:=+libuci +libnl-tiny +libubus +ubus +ubusd +jshn +libubox\n  TITLE:=OpenWrt Network Interface Configuration Daemon\nendef\n\ndefine Package/netifd/conffiles\n/etc/udhcpc.user\n/etc/udhcpc.user.d/\nendef\n\nTARGET_CFLAGS += \\\n\t-I$(STAGING_DIR)/usr/include/libnl-tiny \\\n\t-I$(STAGING_DIR)/usr/include \\\n\t-flto\n\nTARGET_LDFLAGS += -flto -fuse-linker-plugin\n\nCMAKE_OPTIONS += \\\n\t-DLIBNL_LIBS=-lnl-tiny \\\n\t-DDEBUG=1\n\ndefine Package/netifd/install\n\t$(INSTALL_DIR) $(1)/sbin\n\t$(INSTALL_BIN) $(PKG_BUILD_DIR)/netifd $(1)/sbin/\n\t$(CP) ./files/* $(1)/\n\t$(INSTALL_DIR) $(1)/etc/udhcpc.user.d/\n\t$(CP) $(PKG_BUILD_DIR)/scripts/* $(1)/lib/netifd/\nendef\n\n$(eval $(call BuildPackage,netifd))\n"
  },
  {
    "path": "package/network/config/netifd/files/etc/hotplug.d/iface/00-netstate",
    "content": "[ ifup = \"$ACTION\" ] && {\n\tuci_toggle_state network \"$INTERFACE\" up 1\n\t[ -n \"$DEVICE\" ] && {\n\t\tuci_toggle_state network \"$INTERFACE\" ifname \"$DEVICE\"\n\t}\n}\n"
  },
  {
    "path": "package/network/config/netifd/files/etc/hotplug.d/net/20-smp-packet-steering",
    "content": "#!/bin/sh\n[ \"$ACTION\" = add ] || exit\n\nNPROCS=\"$(grep -c \"^processor.*:\" /proc/cpuinfo)\"\n[ \"$NPROCS\" -gt 1 ] || exit\n\nPROC_MASK=\"$(( (1 << $NPROCS) - 1 ))\"\n\nfind_irq_cpu() {\n\tlocal dev=\"$1\"\n\tlocal match=\"$(grep -m 1 \"$dev\\$\" /proc/interrupts)\"\n\tlocal cpu=0\n\n\t[ -n \"$match\" ] && {\n\t\tset -- $match\n\t\tshift\n\t\tfor cur in $(seq 1 $NPROCS); do\n\t\t\t[ \"$1\" -gt 0 ] && {\n\t\t\t\tcpu=$(($cur - 1))\n\t\t\t\tbreak\n\t\t\t}\n\t\t\tshift\n\t\tdone\n\t}\n\n\techo \"$cpu\"\n}\n\nset_hex_val() {\n\tlocal file=\"$1\"\n\tlocal val=\"$2\"\n\tval=\"$(printf %x \"$val\")\"\n\t[ -n \"$DEBUG\" ] && echo \"$file = $val\"\n\techo \"$val\" > \"$file\"\n}\n\npacket_steering=\"$(uci get \"network.@globals[0].packet_steering\")\"\n[ \"$packet_steering\" != 1 ] && exit 0\n\nexec 512>/var/lock/smp_tune.lock\nflock 512 || exit 1\n\nfor dev in /sys/class/net/*; do\n\t[ -d \"$dev\" ] || continue\n\n\t# ignore virtual interfaces\n\t[ -n \"$(ls \"${dev}/\" | grep '^lower_')\" ] && continue\n\t[ -d \"${dev}/device\" ] || continue\n\n\tdevice=\"$(readlink \"${dev}/device\")\"\n\tdevice=\"$(basename \"$device\")\"\n\tirq_cpu=\"$(find_irq_cpu \"$device\")\"\n\tirq_cpu_mask=\"$((1 << $irq_cpu))\"\n\n\tfor q in ${dev}/queues/tx-*; do\n\t\tset_hex_val \"$q/xps_cpus\" \"$PROC_MASK\"\n\tdone\n\n\t# ignore dsa slave ports for RPS\n\tsubsys=\"$(readlink \"${dev}/device/subsystem\")\"\n\tsubsys=\"$(basename \"$subsys\")\"\n\t[ \"$subsys\" = \"mdio_bus\" ] && continue\n\n\tfor q in ${dev}/queues/rx-*; do\n\t\tset_hex_val \"$q/rps_cpus\" \"$PROC_MASK\"\n\tdone\ndone\n"
  },
  {
    "path": "package/network/config/netifd/files/etc/init.d/network",
    "content": "#!/bin/sh /etc/rc.common\n\nSTART=20\nSTOP=90\n\nUSE_PROCD=1\n\ninit_switch() {\n\tsetup_switch() { return 0; }\n\n\tinclude /lib/network\n\tsetup_switch\n}\n\nstart_service() {\n\tinit_switch\n\n\tprocd_open_instance\n\tprocd_set_param command /sbin/netifd\n\tprocd_set_param respawn\n\tprocd_set_param watch network.interface\n\t[ -e /proc/sys/kernel/core_pattern ] && {\n\t\tprocd_set_param limits core=\"unlimited\"\n\t}\n\tprocd_close_instance\n}\n\nreload_service() {\n\tlocal rv=0\n\n\tinit_switch\n\tubus call network reload || rv=1\n\t/sbin/wifi reload_legacy\n\treturn $rv\n}\n\nstop_service() {\n\t/sbin/wifi down\n\tifdown -a\n\tsleep 1\n}\n\nvalidate_atm_bridge_section()\n{\n\tuci_validate_section network \"atm-bridge\" \"${1}\" \\\n\t\t'unit:uinteger:0' \\\n\t\t'vci:range(32, 65535):35' \\\n\t\t'vpi:range(0, 255):8' \\\n\t\t'atmdev:uinteger:0' \\\n\t\t'encaps:or(\"llc\", \"vc\"):llc' \\\n\t\t'payload:or(\"bridged\", \"routed\"):bridged'\n}\n\nvalidate_route_section()\n{\n\tuci_validate_section network route \"${1}\" \\\n\t\t'interface:string' \\\n\t\t'target:cidr4' \\\n\t\t'netmask:netmask4' \\\n\t\t'gateway:ip4addr' \\\n\t\t'metric:uinteger' \\\n\t\t'mtu:uinteger' \\\n\t\t'table:or(range(0,65535),string)'\n}\n\nvalidate_route6_section()\n{\n\tuci_validate_section network route6 \"${1}\" \\\n\t\t'interface:string' \\\n\t\t'target:cidr6' \\\n\t\t'gateway:ip6addr' \\\n\t\t'metric:uinteger' \\\n\t\t'mtu:uinteger' \\\n\t\t'table:or(range(0,65535),string)'\n}\n\nvalidate_rule_section()\n{\n\tuci_validate_section network rule \"${1}\" \\\n\t\t'in:string' \\\n\t\t'out:string' \\\n\t\t'src:cidr4' \\\n\t\t'dest:cidr4' \\\n\t\t'tos:range(0,31)' \\\n\t\t'mark:string' \\\n\t\t'invert:bool' \\\n\t\t'lookup:or(range(0,65535),string)' \\\n\t\t'goto:range(0,65535)' \\\n\t\t'action:or(\"prohibit\", \"unreachable\", \"blackhole\", \"throw\")'\n}\n\nvalidate_rule6_section()\n{\n\tuci_validate_section network rule6 \"${1}\" \\\n\t\t'in:string' \\\n\t\t'out:string' \\\n\t\t'src:cidr6' \\\n\t\t'dest:cidr6' \\\n\t\t'tos:range(0,31)' \\\n\t\t'mark:string' \\\n\t\t'invert:bool' \\\n\t\t'lookup:or(range(0,65535),string)' \\\n\t\t'goto:range(0,65535)' \\\n\t\t'action:or(\"prohibit\", \"unreachable\", \"blackhole\", \"throw\")'\n}\n\nvalidate_switch_section()\n{\n\tuci_validate_section network switch \"${1}\" \\\n\t\t'name:string' \\\n\t\t'enable:bool' \\\n\t\t'enable_vlan:bool' \\\n\t\t'reset:bool' \\\n\t\t'ar8xxx_mib_poll_interval:uinteger' \\\n\t\t'ar8xxx_mib_type:range(0,1)'\n}\n\nvalidate_switch_vlan()\n{\n\tuci_validate_section network switch_vlan \"${1}\" \\\n\t\t'device:string' \\\n\t\t'vlan:uinteger' \\\n\t\t'ports:list(ports)'\n}\n\nservice_triggers()\n{\n\tprocd_add_reload_trigger network wireless\n\n\tprocd_open_validate\n\tvalidate_atm_bridge_section\n\tvalidate_route_section\n\t[ -e /proc/sys/net/ipv6 ] && validate_route6_section\n\tvalidate_rule_section\n\t[ -e /proc/sys/net/ipv6 ] && validate_rule6_section\n\tvalidate_switch_section\n\tvalidate_switch_vlan\n\tprocd_close_validate\n}\n\nshutdown() {\n\tifdown -a\n\tsleep 1\n}\n"
  },
  {
    "path": "package/network/config/netifd/files/etc/uci-defaults/14_migrate-dhcp-release",
    "content": ". /lib/functions.sh\n\nmigrate_release() {\n\tlocal config=\"$1\"\n\tlocal proto\n\tlocal release\n\n\tconfig_get proto \"$config\" proto\n\tconfig_get release \"$config\" release\n\n\t[ \"$proto\" = \"dhcp\" ] && [ -n \"$release\" ] && {\n\t\tnorelease=\"$((!$release))\"\n\t\tuci_set network \"$config\" norelease \"$norelease\"\n\t\tuci_remove network \"$config\" release\n\t}\n\n}\n\nconfig_load network\nconfig_foreach migrate_release interface\nuci commit network\n\nexit 0\n"
  },
  {
    "path": "package/network/config/netifd/files/etc/udhcpc.user",
    "content": "# This script is sourced by udhcpc's dhcp.script at every DHCP event.\n"
  },
  {
    "path": "package/network/config/netifd/files/lib/netifd/dhcp.script",
    "content": "#!/bin/sh\n[ -z \"$1\" ] && echo \"Error: should be run by udhcpc\" && exit 1\n\n. /lib/functions.sh\n. /lib/netifd/netifd-proto.sh\n\nset_classless_routes() {\n\tlocal max=128\n\twhile [ -n \"$1\" -a -n \"$2\" -a $max -gt 0 ]; do\n\t\tproto_add_ipv4_route \"${1%%/*}\" \"${1##*/}\" \"$2\" \"$ip\"\n\t\tmax=$(($max-1))\n\t\tshift 2\n\tdone\n}\n\nsetup_interface () {\n\tproto_init_update \"*\" 1\n\tproto_add_ipv4_address \"$ip\" \"${subnet:-255.255.255.0}\"\n\t# TODO: apply $broadcast\n\n\tlocal ip_net\n\teval \"$(ipcalc.sh \"$ip/$mask\")\";ip_net=\"$NETWORK\"\n\n\tlocal i\n\tfor i in $router; do\n\t\tlocal gw_net\n\t\teval \"$(ipcalc.sh \"$i/$mask\")\";gw_net=\"$NETWORK\"\n\n\t\t[ \"$ip_net\" != \"$gw_net\" ] && proto_add_ipv4_route \"$i\" 32 \"\" \"$ip\"\n\t\tproto_add_ipv4_route 0.0.0.0 0 \"$i\" \"$ip\"\n\n\t\tlocal r\n\t\tfor r in $CUSTOMROUTES; do\n\t\t\tproto_add_ipv4_route \"${r%%/*}\" \"${r##*/}\" \"$i\" \"$ip\"\n\t\tdone\n\tdone\n\n\t# CIDR STATIC ROUTES (rfc3442)\n\t[ -n \"$staticroutes\" ] && set_classless_routes $staticroutes\n\t[ -n \"$msstaticroutes\" ] && set_classless_routes $msstaticroutes\n\n\tfor i in $dns; do\n\t\tproto_add_dns_server \"$i\"\n\tdone\n\tfor i in $domain; do\n\t\tproto_add_dns_search \"$i\"\n\tdone\n\n\t# TODO: Deprecate timesvr in favor of timesrv\n\tif [ -n \"$timesvr\" -a -z \"$timesrv\" ]; then\n\t\ttimesrv=\"$timesvr\"\n\t\techo \"Environment variable 'timesvr' will be deprecated; use 'timesrv' instead.\"\n\tfi\n\n\tproto_add_data\n\t[ -n \"$ZONE\" ]     && json_add_string zone \"$ZONE\"\n\t[ -n \"$ntpsrv\" ]   && json_add_string ntpserver \"$ntpsrv\"\n\t[ -n \"$timesrv\" ]  && json_add_string timeserver \"$timesrv\"\n\t[ -n \"$hostname\" ] && json_add_string hostname \"$hostname\"\n\t[ -n \"$message\" ]  && json_add_string message \"$message\"\n\t[ -n \"$timezone\" ] && json_add_int timezone \"$timezone\"\n\t[ -n \"$lease\" ]    && json_add_int leasetime \"$lease\"\n\t[ -n \"$serverid\" ] && json_add_string dhcpserver \"$serverid\"\n\tproto_close_data\n\n\tproto_send_update \"$INTERFACE\"\n\n\n\tif [ \"$IFACE6RD\" != 0 -a -n \"$ip6rd\" ]; then\n\t\tlocal v4mask=\"${ip6rd%% *}\"\n\t\tip6rd=\"${ip6rd#* }\"\n\t\tlocal ip6rdprefixlen=\"${ip6rd%% *}\"\n\t\tip6rd=\"${ip6rd#* }\"\n\t\tlocal ip6rdprefix=\"${ip6rd%% *}\"\n\t\tip6rd=\"${ip6rd#* }\"\n\t\tlocal ip6rdbr=\"${ip6rd%% *}\"\n\n\t\t[ -n \"$ZONE\" ] || ZONE=$(fw3 -q network $INTERFACE 2>/dev/null)\n\t\t[ -z \"$IFACE6RD\" -o \"$IFACE6RD\" = 1 ] && IFACE6RD=${INTERFACE}_6\n\n\t\tjson_init\n\t\tjson_add_string name \"$IFACE6RD\"\n\t\tjson_add_string ifname \"@$INTERFACE\"\n\t\tjson_add_string proto \"6rd\"\n\t\tjson_add_string peeraddr \"$ip6rdbr\"\n\t\tjson_add_int ip4prefixlen \"$v4mask\"\n\t\tjson_add_string ip6prefix \"$ip6rdprefix\"\n\t\tjson_add_int ip6prefixlen \"$ip6rdprefixlen\"\n\t\tjson_add_string tunlink \"$INTERFACE\"\n\t\t[ -n \"$IFACE6RD_DELEGATE\" ] && json_add_boolean delegate \"$IFACE6RD_DELEGATE\"\n\t\t[ -n \"$ZONE6RD\" ] || ZONE6RD=$ZONE\n\t\t[ -n \"$ZONE6RD\" ] && json_add_string zone \"$ZONE6RD\"\n\t\t[ -n \"$MTU6RD\" ] && json_add_string mtu \"$MTU6RD\"\n\t\tjson_close_object\n\n\t\tubus call network add_dynamic \"$(json_dump)\"\n\tfi\n}\n\ndeconfig_interface() {\n\tproto_init_update \"*\" 0\n\tproto_send_update \"$INTERFACE\"\n}\n\ncase \"$1\" in\n\tdeconfig)\n\t\tdeconfig_interface\n\t;;\n\trenew|bound)\n\t\tsetup_interface\n\t;;\nesac\n\n# user rules\n[ -f /etc/udhcpc.user ] && . /etc/udhcpc.user \"$@\"\nfor f in /etc/udhcpc.user.d/*; do\n\t[ -f \"$f\" ] && (. \"$f\" \"$@\")\ndone\n\nexit 0\n"
  },
  {
    "path": "package/network/config/netifd/files/lib/netifd/proto/dhcp.sh",
    "content": "#!/bin/sh\n\n[ -x /sbin/udhcpc ] || exit 0\n\n. /lib/functions.sh\n. ../netifd-proto.sh\ninit_proto \"$@\"\n\nproto_dhcp_init_config() {\n\trenew_handler=1\n\n\tproto_config_add_string 'ipaddr:ipaddr'\n\tproto_config_add_string 'hostname:hostname'\n\tproto_config_add_string clientid\n\tproto_config_add_string vendorid\n\tproto_config_add_boolean 'broadcast:bool'\n\tproto_config_add_boolean 'norelease:bool'\n\tproto_config_add_string 'reqopts:list(string)'\n\tproto_config_add_boolean 'defaultreqopts:bool'\n\tproto_config_add_string iface6rd\n\tproto_config_add_array 'sendopts:list(string)'\n\tproto_config_add_boolean delegate\n\tproto_config_add_string zone6rd\n\tproto_config_add_string zone\n\tproto_config_add_string mtu6rd\n\tproto_config_add_string customroutes\n\tproto_config_add_boolean classlessroute\n}\n\nproto_dhcp_add_sendopts() {\n\t[ -n \"$1\" ] && append \"$3\" \"-x $1\"\n}\n\nproto_dhcp_setup() {\n\tlocal config=\"$1\"\n\tlocal iface=\"$2\"\n\n\tlocal ipaddr hostname clientid vendorid broadcast norelease reqopts defaultreqopts iface6rd sendopts delegate zone6rd zone mtu6rd customroutes classlessroute\n\tjson_get_vars ipaddr hostname clientid vendorid broadcast norelease reqopts defaultreqopts iface6rd delegate zone6rd zone mtu6rd customroutes classlessroute\n\n\tlocal opt dhcpopts\n\tfor opt in $reqopts; do\n\t\tappend dhcpopts \"-O $opt\"\n\tdone\n\n\tjson_for_each_item proto_dhcp_add_sendopts sendopts dhcpopts\n\n\t[ -z \"$hostname\" ] && hostname=\"$(cat /proc/sys/kernel/hostname)\"\n\t[ \"$hostname\" = \"*\" ] && hostname=\n\n\t[ \"$defaultreqopts\" = 0 ] && defaultreqopts=\"-o\" || defaultreqopts=\n\t[ \"$broadcast\" = 1 ] && broadcast=\"-B\" || broadcast=\n\t[ \"$norelease\" = 1 ] && norelease=\"\" || norelease=\"-R\"\n\t[ -n \"$clientid\" ] && clientid=\"-x 0x3d:${clientid//:/}\" || clientid=\"-C\"\n\t[ -n \"$iface6rd\" ] && proto_export \"IFACE6RD=$iface6rd\"\n\t[ \"$iface6rd\" != 0 -a -f /lib/netifd/proto/6rd.sh ] && append dhcpopts \"-O 212\"\n\t[ -n \"$zone6rd\" ] && proto_export \"ZONE6RD=$zone6rd\"\n\t[ -n \"$zone\" ] && proto_export \"ZONE=$zone\"\n\t[ -n \"$mtu6rd\" ] && proto_export \"MTU6RD=$mtu6rd\"\n\t[ -n \"$customroutes\" ] && proto_export \"CUSTOMROUTES=$customroutes\"\n\t[ \"$delegate\" = \"0\" ] && proto_export \"IFACE6RD_DELEGATE=0\"\n\t# Request classless route option (see RFC 3442) by default\n\t[ \"$classlessroute\" = \"0\" ] || append dhcpopts \"-O 121\"\n\n\tproto_export \"INTERFACE=$config\"\n\tproto_run_command \"$config\" udhcpc \\\n\t\t-p /var/run/udhcpc-$iface.pid \\\n\t\t-s /lib/netifd/dhcp.script \\\n\t\t-f -t 0 -i \"$iface\" \\\n\t\t${ipaddr:+-r $ipaddr} \\\n\t\t${hostname:+-x \"hostname:$hostname\"} \\\n\t\t${vendorid:+-V \"$vendorid\"} \\\n\t\t$clientid $defaultreqopts $broadcast $norelease $dhcpopts\n}\n\nproto_dhcp_renew() {\n\tlocal interface=\"$1\"\n\t# SIGUSR1 forces udhcpc to renew its lease\n\tlocal sigusr1=\"$(kill -l SIGUSR1)\"\n\t[ -n \"$sigusr1\" ] && proto_kill_command \"$interface\" $sigusr1\n}\n\nproto_dhcp_teardown() {\n\tlocal interface=\"$1\"\n\tproto_kill_command \"$interface\"\n}\n\nadd_protocol dhcp\n"
  },
  {
    "path": "package/network/config/netifd/files/lib/network/config.sh",
    "content": "#!/bin/sh\n# Copyright (C) 2011 OpenWrt.org\n\n. /usr/share/libubox/jshn.sh\n\nfind_config() {\n\tlocal device=\"$1\"\n\tlocal ifdev ifl3dev ifobj\n\tfor ifobj in $(ubus list network.interface.\\*); do\n\t\tinterface=\"${ifobj##network.interface.}\"\n\t\t(\n\t\t\tjson_load \"$(ifstatus $interface)\"\n\t\t\tjson_get_var ifdev device\n\t\t\tjson_get_var ifl3dev l3_device\n\t\t\tif [ \"$device\" = \"$ifdev\" ] || [ \"$device\" = \"$ifl3dev\" ]; then\n\t\t\t\techo \"$interface\"\n\t\t\t\texit 0\n\t\t\telse\n\t\t\t\texit 1\n\t\t\tfi\n\t\t) && return\n\tdone\n}\n\nunbridge() {\n\treturn\n}\n\nubus_call() {\n\tjson_init\n\tlocal _data=\"$(ubus -S call \"$1\" \"$2\")\"\n\t[ -z \"$_data\" ] && return 1\n\tjson_load \"$_data\"\n\treturn 0\n}\n\n\nfixup_interface() {\n\tlocal config=\"$1\"\n\tlocal ifname type device l3dev\n\n\tconfig_get type \"$config\" type\n\tconfig_get ifname \"$config\" ifname\n\t[ \"bridge\" = \"$type\" ] && ifname=\"br-$config\"\n\tubus_call \"network.interface.$config\" status || return 0\n\tjson_get_var l3dev l3_device\n\t[ -n \"$l3dev\" ] && ifname=\"$l3dev\"\n\tjson_init\n\tconfig_set \"$config\" ifname \"$ifname\"\n}\n\nscan_interfaces() {\n\tconfig_load network\n\tconfig_foreach fixup_interface interface\n}\n\nprepare_interface_bridge() {\n\tlocal config=\"$1\"\n\n\t[ -n \"$config\" ] || return 0\n\tubus call network.interface.\"$config\" prepare\n}\n\nsetup_interface() {\n\tlocal iface=\"$1\"\n\tlocal config=\"$2\"\n\n\t[ -n \"$config\" ] || return 0\n\tubus call network.interface.\"$config\" add_device \"{ \\\"name\\\": \\\"$iface\\\" }\"\n}\n\ndo_sysctl() {\n\t[ -n \"$2\" ] && \\\n\t\tsysctl -n -e -w \"$1=$2\" >/dev/null || \\\n\t\tsysctl -n -e \"$1\"\n}\n"
  },
  {
    "path": "package/network/config/netifd/files/sbin/devstatus",
    "content": "#!/bin/sh\n. /usr/share/libubox/jshn.sh\nDEVICE=\"$1\"\n\n[ -n \"$DEVICE\" ] || {\n\techo \"Usage: $0 <device>\"\n\texit 1\n}\n\njson_init\njson_add_string name \"$DEVICE\"\nubus call network.device status \"$(json_dump)\"\n"
  },
  {
    "path": "package/network/config/netifd/files/sbin/ifstatus",
    "content": "#!/bin/sh\nINTERFACE=\"$1\"\n\n[ -n \"$INTERFACE\" ] || {\n\techo \"Usage: $0 <interface>\"\n\texit 1\n}\n\nubus -S list \"network.interface.$INTERFACE\" >/dev/null || {\n\techo \"Interface $INTERFACE not found\"\n\texit 1\n}\nubus call network.interface status \"{ \\\"interface\\\" : \\\"$INTERFACE\\\" }\"\n"
  },
  {
    "path": "package/network/config/netifd/files/sbin/ifup",
    "content": "#!/bin/sh\n\nifup_all=\nsetup_wifi=\n\nif_call() {\n\tlocal interface=\"$1\"\n\tfor mode in $modes; do\n\t\tubus call network.interface $mode \"{ \\\"interface\\\" : \\\"$interface\\\" }\"\n\tdone\n}\n\ncase \"$0\" in\n\t*ifdown) modes=down;;\n\t*ifup)\n\t\tmodes=\"down up\"\n\t\tsetup_wifi=1\n\t;;\n\t*) echo \"Invalid command: $0\";;\nesac\n\nwhile :; do\n\tcase \"$1\" in\n\t\t-a)\n\t\t\tifup_all=1\n\t\t\tshift\n\t\t;;\n\t\t-w)\n\t\t\tsetup_wifi=\n\t\t\tshift\n\t\t;;\n\t\t*)\n\t\t\tbreak\n\t\t;;\n\tesac\ndone\n\n[ \"$modes\" = \"down up\" ] && ubus call network reload\nif [ -n \"$ifup_all\" ]; then\n\tfor interface in $(ubus -S list 'network.interface.*'); do\n\t\tif_call \"${interface##network.interface.}\"\n\tdone\n\t[ -n \"$setup_wifi\" ] && /sbin/wifi up\n\texit\nelse\n\tubus -S list \"network.interface.$1\" > /dev/null || {\n\t\techo \"Interface $1 not found\"\n\t\texit\n\t}\n\tif_call \"$1\"\nfi\n\nif [ -n \"$setup_wifi\" ] && grep -sq config /etc/config/wireless; then\n\t. /lib/functions.sh\n\n\tfind_related_radios() {\n\t\tlocal wdev wnet\n\t\tconfig_get wdev \"$1\" device\n\t\tconfig_get wnet \"$1\" network\n\n\t\tif [ -n \"$wdev\" ]; then\n\t\t\tfor wnet in $wnet; do\n\t\t\t\tif [ \"$wnet\" = \"$network\" ]; then\n\t\t\t\t\tappend radio_devs \"$wdev\" \"$N\"\n\t\t\t\tfi\n\t\t\tdone\n\t\tfi\n\t}\n\n\tnetwork=\"$1\"\n\tconfig_load wireless\n\tconfig_foreach find_related_radios wifi-iface\n\n\tfor dev in $(echo \"$radio_devs\" | sort -u); do\n\t\t/sbin/wifi up \"$dev\"\n\tdone\nfi\n"
  },
  {
    "path": "package/network/config/netifd/files/usr/share/udhcpc/default.script",
    "content": "#!/bin/sh\n[ -z \"$1\" ] && echo \"Error: should be run by udhcpc\" && exit 1\n\nset_classless_routes() {\n\tlocal max=128\n\tlocal type\n\twhile [ -n \"$1\" -a -n \"$2\" -a $max -gt 0 ]; do\n\t\t[ ${1##*/} -eq 32 ] && type=host || type=net\n\t\techo \"udhcpc: adding route for $type $1 via $2\"\n\t\troute add -$type \"$1\" gw \"$2\" dev \"$interface\"\n\t\tmax=$(($max-1))\n\t\tshift 2\n\tdone\n}\n\nsetup_interface() {\n\techo \"udhcpc: ip addr add $ip/${subnet:-255.255.255.0} broadcast ${broadcast:-+} dev $interface\"\n\tip addr add $ip/${subnet:-255.255.255.0} broadcast ${broadcast:-+} dev $interface\n\n\t[ -n \"$router\" ] && [ \"$router\" != \"0.0.0.0\" ] && [ \"$router\" != \"255.255.255.255\" ] && {\n\t\techo \"udhcpc: setting default routers: $router\"\n\n\t\tlocal valid_gw=\"\"\n\t\tfor i in $router ; do\n\t\t\troute add default gw $i dev $interface\n\t\t\tvalid_gw=\"${valid_gw:+$valid_gw|}$i\"\n\t\tdone\n\t\t\n\t\teval $(route -n | awk '\n\t\t\t/^0.0.0.0\\W{9}('$valid_gw')\\W/ {next}\n\t\t\t/^0.0.0.0/ {print \"route del -net \"$1\" gw \"$2\";\"}\n\t\t')\n\t}\n\n\t# CIDR STATIC ROUTES (rfc3442)\n\t[ -n \"$staticroutes\" ] && set_classless_routes $staticroutes\n\t[ -n \"$msstaticroutes\" ] && set_classless_routes $msstaticroutes\n}\n\n\napplied=\ncase \"$1\" in\n\tdeconfig)\n\t\tip -4 addr flush dev \"$interface\"\n\t;;\n\trenew)\n\t\tsetup_interface update\n\t;;\n\tbound)\n\t\tsetup_interface ifup\n\t;;\nesac\n\n# user rules\n[ -f /etc/udhcpc.user ] && . /etc/udhcpc.user\n\nexit 0\n"
  },
  {
    "path": "package/network/config/qos-scripts/Makefile",
    "content": "#\n# Copyright (C) 2006-2015 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=qos-scripts\nPKG_VERSION:=1.3.1\nPKG_RELEASE:=$(AUTORELEASE)\nPKG_LICENSE:=GPL-2.0\n\nPKG_MAINTAINER:=Felix Fietkau <nbd@nbd.name>\n\nPKG_BUILD_DIR := $(BUILD_DIR)/$(PKG_NAME)\n\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine Package/qos-scripts\n  SECTION:=utils\n  CATEGORY:=Base system\n  DEPENDS:=+tc +kmod-sched-core +kmod-sched-connmark +kmod-ifb +iptables +iptables-mod-ipopt +iptables-mod-conntrack-extra\n  TITLE:=QoS scripts\n  PKGARCH:=all\nendef\n\ndefine Package/qos-scripts/description\n A set of scripts that abstract QoS configuration into a simple \n configuration file supporting stanzas that specify any number of QoS \n entries.\nendef\n\ndefine Package/qos-scripts/conffiles\n/etc/config/qos\nendef\n\ndefine Build/Prepare\nendef\n\ndefine Build/Configure\nendef\n\ndefine Build/Compile\nendef\n\ndefine Package/qos-scripts/install\n\t$(INSTALL_DIR) $(1)\n\t$(CP) ./files/* $(1)/\nendef\n\n$(eval $(call BuildPackage,qos-scripts))\n"
  },
  {
    "path": "package/network/config/qos-scripts/files/etc/config/qos",
    "content": "# QoS configuration for OpenWrt\n\n# INTERFACES:\nconfig interface wan\n\toption classgroup  \"Default\"\n\toption enabled      0\n\toption upload       128\n\toption download     1024\n\n# RULES:\nconfig classify\n\toption target       \"Priority\"\n\toption ports        \"22,53\"\n\toption comment      \"ssh, dns\"\nconfig classify\n\toption target       \"Normal\"\n\toption proto        \"tcp\"\n\toption ports        \"20,21,25,80,110,443,993,995\"\n\toption comment      \"ftp, smtp, http(s), imap\"\nconfig classify\n\toption target       \"Express\"\n\toption ports        \"5190\"\n\toption comment      \"AOL, iChat, ICQ\"\nconfig default\n\toption target       \"Express\"\n\toption proto        \"udp\"\n\toption pktsize      \"-500\"\nconfig reclassify\n\toption target       \"Priority\"\n\toption proto        \"icmp\"\nconfig default\n\toption target       \"Bulk\"\n\toption portrange    \"1024-65535\"\n\n\n# Don't change the stuff below unless you\n# really know what it means :)\n\nconfig classgroup \"Default\"\n\toption classes      \"Priority Express Normal Bulk\"\n\toption default      \"Normal\"\n\n\nconfig class \"Priority\"\n\toption packetsize  400\n\toption avgrate     10\n\toption priority    20\nconfig class \"Priority_down\"\n\toption packetsize  1000\n\toption avgrate     10\n\n\nconfig class \"Express\"\n\toption packetsize  1000\n\toption avgrate     50\n\toption priority    10\n\nconfig class \"Normal\"\n\toption packetsize  1500\n\toption packetdelay 100\n\toption avgrate     10\n\toption priority    5\nconfig class \"Normal_down\"\n\toption avgrate     20\n\nconfig class \"Bulk\"\n\toption avgrate     1\n\toption packetdelay 200\n"
  },
  {
    "path": "package/network/config/qos-scripts/files/etc/hotplug.d/iface/10-qos",
    "content": "#!/bin/sh\n[ \"$ACTION\" = ifup ] && /etc/init.d/qos enabled && /usr/lib/qos/generate.sh interface \"$INTERFACE\" | sh\n"
  },
  {
    "path": "package/network/config/qos-scripts/files/etc/init.d/qos",
    "content": "#!/bin/sh /etc/rc.common\n# Copyright (C) 2006 OpenWrt.org\n\nSTART=50\nUSE_PROCD=1\n\nvalidate_qos_section()\n{\n\tuci_validate_section qos interface \"${1}\" \\\n\t\t'enabled:bool' \\\n\t\t'upload:uinteger' \\\n\t\t'download:uinteger'\n}\n\nservice_triggers()\n{\n\tprocd_add_reload_trigger \"qos\"\n\tprocd_add_validation validate_qos_section\n\tqos-start\n}\n\nstart_service() {\n\tqos-start\n}\n\nreload_service() {\n\tqos-start\n}\n"
  },
  {
    "path": "package/network/config/qos-scripts/files/usr/bin/qos-start",
    "content": "#!/bin/sh\n\nqos-stop \n/usr/lib/qos/generate.sh all | sh\n"
  },
  {
    "path": "package/network/config/qos-scripts/files/usr/bin/qos-stat",
    "content": "#!/bin/sh\n# Copyright (C) 2011 OpenWrt.org\n\n. /lib/functions.sh\n\ninclude /lib/network\n\nget_ifname() {\n\tlocal interface=\"$1\"\n\tlocal cfgt\n\n\tscan_interfaces\n\tconfig_get cfgt \"$interface\" TYPE\n\t[ \"$cfgt\" = \"interface\" ] && config_get \"$interface\" ifname\n}\n\nqos_set_device() {\n\tconfig_get TYPE \"$1\" TYPE\n\t[ \"interface\" = \"$TYPE\" ] && {\n\t\tconfig_get device \"$1\" ifname\n\t\t[ -z \"$device\" ] && device=\"$(get_ifname $1)\"\n\t\tconfig_set \"$1\" device \"$device\"\n\t}\n}\n\nconfig_load qos\nconfig_foreach qos_set_device\n\nprint_comments() {\n\techo ''\n\techo '# Interface: '\"$1\"\n\techo '# Direction: '\"$2\"\n\techo '# Stats:     '\"$3\"\n\techo ''\n}\t\n\nget_device() {\n\t( config_load network; scan_interfaces; config_get \"$1\" ifname )\n}\n\ninterface_stats() {\n\tlocal interface=\"$1\"\n\tlocal device\n\n\tdevice=\"$(get_device \"$interface\")\"\n\t[ -z \"$device\" ] && config_get device \"$interface\" device\n\tconfig_get_bool enabled \"$interface\" enabled 1\n\t[ -z \"$device\" -o 1 -ne \"$enabled\" ] && {\n\t\treturn 1\n\t}\n\tconfig_get_bool halfduplex \"$interface\" halfduplex 0\n\n\tif [ 1 -ne \"$halfduplex\" ]; then\n\t\tunset halfduplex\n\t\tprint_comments \"$interface\" \"Egress\" \"Start\"\n\t\ttc -s class show dev \"$device\"\n\t\tprint_comments \"$interface\" \"Egress\" \"End\"\n\t\tid=\"root\"\n\telse\n\t\tid=\"\"\n\tfi\n\n\tprint_comments \"$interface\" \"Ingress${halfduplex:+/Egress}\" \"Start\"\n\ttc -s class show dev \"$(tc filter show dev $device $id | grep mirred | sed -e 's,.*\\(ifb.*\\)).*,\\1,')\"\n\tprint_comments \"$interface\" \"Ingress${halfduplex:+/Egress}\" \"End\"\n}\n\n[ -z \"$1\" ] && config_foreach interface_stats interface || interface_stats \"$1\"\n"
  },
  {
    "path": "package/network/config/qos-scripts/files/usr/bin/qos-stop",
    "content": "#!/bin/sh\n\nfor iface in $(tc qdisc show | grep -E '(hfsc|ingress)' | awk '{print $5}'); do\n\ttc qdisc del dev \"$iface\" ingress 2>&- >&-\n\ttc qdisc del dev \"$iface\" root 2>&- >&-\ndone\n/usr/lib/qos/generate.sh firewall stop | sh\n"
  },
  {
    "path": "package/network/config/qos-scripts/files/usr/lib/qos/generate.sh",
    "content": "#!/bin/sh\n[ -e /lib/functions.sh ] && . /lib/functions.sh || . ./functions.sh\n[ -x /sbin/modprobe ] && {\n\tinsmod=\"modprobe\"\n\trmmod=\"$insmod -r\"\n} || {\n\tinsmod=\"insmod\"\n\trmmod=\"rmmod\"\n}\n\nadd_insmod() {\n\teval \"export isset=\\${insmod_$1}\"\n\tcase \"$isset\" in\n\t\t1) ;;\n\t\t*) {\n\t\t\t[ \"$2\" ] && append INSMOD \"$rmmod $1 >&- 2>&-\" \"$N\"\n\t\t\tappend INSMOD \"$insmod $* >&- 2>&-\" \"$N\"; export insmod_$1=1\n\t\t};;\n\tesac\n}\n\n[ -e /etc/config/network ] && {\n\t# only try to parse network config on openwrt\n\n\t. /lib/functions/network.sh\n\n\tfind_ifname() {\n\t\tlocal ifname\n\t\tif network_get_device ifname \"$1\"; then\n\t\t\techo \"$ifname\"\n\t\telse\n\t\t\techo \"Device for interface $1 not found.\" >&2\n\t\t\texit 1\n\t\tfi\n\t}\n} || {\n\tfind_ifname() {\n\t\techo \"Interface not found.\" >&2\n\t\texit 1\n\t}\n}\n\nparse_matching_rule() {\n\tlocal var=\"$1\"\n\tlocal section=\"$2\"\n\tlocal options=\"$3\"\n\tlocal prefix=\"$4\"\n\tlocal suffix=\"$5\"\n\tlocal proto=\"$6\"\n\tlocal mport=\"\"\n\tlocal ports=\"\"\n\n\tappend \"$var\" \"$prefix\" \"$N\"\n\tfor option in $options; do\n\t\tcase \"$option\" in\n\t\t\tproto) config_get value \"$section\" proto; proto=\"${proto:-$value}\";;\n\t\tesac\n\tdone\n\tconfig_get type \"$section\" TYPE\n\tcase \"$type\" in\n\t\tclassify) unset pkt; append \"$var\" \"-m mark --mark 0/0x0f\";;\n\t\tdefault) pkt=1; append \"$var\" \"-m mark --mark 0/0xf0\";;\n\t\treclassify) pkt=1;;\n\tesac\n\tappend \"$var\" \"${proto:+-p $proto}\"\n\tfor option in $options; do\n\t\tconfig_get value \"$section\" \"$option\"\n\t\t\n\t\tcase \"$pkt:$option\" in\n\t\t\t*:srchost)\n\t\t\t\tappend \"$var\" \"-s $value\"\n\t\t\t;;\n\t\t\t*:dsthost)\n\t\t\t\tappend \"$var\" \"-d $value\"\n\t\t\t;;\n\t\t\t*:ports|*:srcports|*:dstports)\n\t\t\t\tvalue=\"$(echo \"$value\" | sed -e 's,-,:,g')\"\n\t\t\t\tlproto=${lproto:-tcp}\n\t\t\t\tcase \"$proto\" in\n\t\t\t\t\t\"\"|tcp|udp) append \"$var\" \"-m ${proto:-tcp -p tcp} -m multiport\";;\n\t\t\t\t\t*) unset \"$var\"; return 0;;\n\t\t\t\tesac\n\t\t\t\tcase \"$option\" in\n\t\t\t\t\tports)\n\t\t\t\t\t\tconfig_set \"$section\" srcports \"\"\n\t\t\t\t\t\tconfig_set \"$section\" dstports \"\"\n\t\t\t\t\t\tconfig_set \"$section\" portrange \"\"\n\t\t\t\t\t\tappend \"$var\" \"--ports $value\"\n\t\t\t\t\t;;\n\t\t\t\t\tsrcports)\n\t\t\t\t\t\tconfig_set \"$section\" ports \"\"\n\t\t\t\t\t\tconfig_set \"$section\" dstports \"\"\n\t\t\t\t\t\tconfig_set \"$section\" portrange \"\"\n\t\t\t\t\t\tappend \"$var\" \"--sports $value\"\n\t\t\t\t\t;;\n\t\t\t\t\tdstports)\n\t\t\t\t\t\tconfig_set \"$section\" ports \"\"\n\t\t\t\t\t\tconfig_set \"$section\" srcports \"\"\n\t\t\t\t\t\tconfig_set \"$section\" portrange \"\"\n\t\t\t\t\t\tappend \"$var\" \"--dports $value\"\n\t\t\t\t\t;;\n\t\t\t\tesac\n\t\t\t\tports=1\n\t\t\t;;\n\t\t\t*:portrange)\n\t\t\t\tconfig_set \"$section\" ports \"\"\n\t\t\t\tconfig_set \"$section\" srcports \"\"\n\t\t\t\tconfig_set \"$section\" dstports \"\"\n\t\t\t\tvalue=\"$(echo \"$value\" | sed -e 's,-,:,g')\"\n\t\t\t\tcase \"$proto\" in\n\t\t\t\t\t\"\"|tcp|udp) append \"$var\" \"-m ${proto:-tcp -p tcp} --sport $value --dport $value\";;\n\t\t\t\t\t*) unset \"$var\"; return 0;;\n\t\t\t\tesac\n\t\t\t\tports=1\n\t\t\t;;\n\t\t\t*:connbytes)\n\t\t\t\tvalue=\"$(echo \"$value\" | sed -e 's,-,:,g')\"\n\t\t\t\tadd_insmod xt_connbytes\n\t\t\t\tappend \"$var\" \"-m connbytes --connbytes $value --connbytes-dir both --connbytes-mode bytes\"\n\t\t\t;;\n\t\t\t*:comment)\n\t\t\t\tadd_insmod xt_comment\n\t\t\t\tappend \"$var\" \"-m comment --comment '$value'\"\n\t\t\t;;\n\t\t\t*:tos)\n\t\t\t\tadd_insmod xt_dscp\n\t\t\t\tcase \"$value\" in\n\t\t\t\t\t!*) append \"$var\" \"-m tos ! --tos $value\";;\n\t\t\t\t\t*) append \"$var\" \"-m tos --tos $value\"\n\t\t\t\tesac\n\t\t\t;;\n\t\t\t*:dscp)\n\t\t\t\tadd_insmod xt_dscp\n\t\t\t\tdscp_option=\"--dscp\"\n\t\t\t\t[ -z \"${value%%[EBCA]*}\" ] && dscp_option=\"--dscp-class\"\n\t\t\t\tcase \"$value\" in\n\t\t\t\t\t!*) append \"$var\" \"-m dscp ! $dscp_option $value\";;\n\t\t\t\t\t*) append \"$var\" \"-m dscp $dscp_option $value\"\n\t\t\t\tesac\n\t\t\t;;\n\t\t\t*:direction)\n\t\t\t\tvalue=\"$(echo \"$value\" | sed -e 's,-,:,g')\"\n\t\t\t\tif [ \"$value\" = \"out\" ]; then\n\t\t\t\t\tappend \"$var\" \"-o $device\"\n\t\t\t\telif [ \"$value\" = \"in\" ]; then\n\t\t\t\t\tappend \"$var\" \"-i $device\"\n\t\t\t\tfi\n\t\t\t;;\n\t\t\t*:srciface)\n\t\t\t\tappend \"$var\" \"-i $value\"\n\t\t\t;;\n\t\t\t1:pktsize)\n\t\t\t\tvalue=\"$(echo \"$value\" | sed -e 's,-,:,g')\"\n\t\t\t\tadd_insmod xt_length\n\t\t\t\tappend \"$var\" \"-m length --length $value\"\n\t\t\t;;\n\t\t\t1:limit)\n\t\t\t\tadd_insmod xt_limit\n\t\t\t\tappend \"$var\" \"-m limit --limit $value\"\n\t\t\t;;\n\t\t\t1:tcpflags)\n\t\t\t\tcase \"$proto\" in\n\t\t\t\t\ttcp) append \"$var\" \"-m tcp --tcp-flags ALL $value\";;\n\t\t\t\t\t*) unset $var; return 0;;\n\t\t\t\tesac\n\t\t\t;;\n\t\t\t1:mark)\n\t\t\t\tconfig_get class \"${value##!}\" classnr\n\t\t\t\t[ -z \"$class\" ] && continue;\n\t\t\t\tcase \"$value\" in\n\t\t\t\t\t!*) append \"$var\" \"-m mark ! --mark $class/0x0f\";;\n\t\t\t\t\t*) append \"$var\" \"-m mark --mark $class/0x0f\";;\n\t\t\t\tesac\n\t\t\t;;\n\t\t\t1:TOS)\n\t\t\t\tadd_insmod xt_DSCP\n\t\t\t\tconfig_get TOS \"$rule\" 'TOS'\n\t\t\t\tsuffix=\"-j TOS --set-tos \"${TOS:-\"Normal-Service\"}\n\t\t\t;;\n\t\t\t1:DSCP)\n\t\t\t\tadd_insmod xt_DSCP\n\t\t\t\tconfig_get DSCP \"$rule\" 'DSCP'\n\t\t\t\t[ -z \"${DSCP%%[EBCA]*}\" ] && set_value=\"--set-dscp-class $DSCP\" \\\n\t\t\t\t|| set_value=\"--set-dscp $DSCP\"\n\t\t\t\tsuffix=\"-j DSCP $set_value\"\n\t\t\t;;\n\t\tesac\n\tdone\n\tappend \"$var\" \"$suffix\"\n\tcase \"$ports:$proto\" in\n\t\t1:)\tparse_matching_rule \"$var\" \"$section\" \"$options\" \"$prefix\" \"$suffix\" \"udp\";;\n\tesac\n}\n\nconfig_cb() {\n\toption_cb() {\n\t\treturn 0\n\t}\n\tcase \"$1\" in\n\t\tinterface)\n\t\t\tconfig_set \"$2\" \"classgroup\" \"Default\"\n\t\t\tconfig_set \"$2\" \"upload\" \"128\"\n\t\t;;\n\t\tclassify|default|reclassify)\n\t\t\toption_cb() {\n\t\t\t\tappend \"CONFIG_${CONFIG_SECTION}_options\" \"$1\"\n\t\t\t}\n\t\t;;\n\tesac\n}\n\nqos_parse_config() {\n\tconfig_get TYPE \"$1\" TYPE\n\tcase \"$TYPE\" in\n\t\tinterface)\n\t\t\tconfig_get_bool enabled \"$1\" enabled 1\n\t\t\t[ 1 -eq \"$enabled\" ] && {\n\t\t\t\tconfig_get classgroup \"$1\" classgroup\n\t\t\t\tconfig_set \"$1\" ifbdev \"$C\"\n\t\t\t\tC=$(($C+1))\n\t\t\t\tappend INTERFACES \"$1\"\n\t\t\t\tconfig_set \"$classgroup\" enabled 1\n\t\t\t\tconfig_get device \"$1\" device\n\t\t\t\t[ -z \"$device\" ] && {\n\t\t\t\t\tdevice=\"$(find_ifname $1)\"\n\t\t\t\t\t[ -z \"$device\" ] && exit 1\n\t\t\t\t\tconfig_set \"$1\" device \"$device\"\n\t\t\t\t}\n\t\t\t}\n\t\t;;\n\t\tclassgroup) append CG \"$1\";;\n\t\tclassify|default|reclassify)\n\t\t\tcase \"$TYPE\" in\n\t\t\t\tclassify) var=\"ctrules\";;\n\t\t\t\t*) var=\"rules\";;\n\t\t\tesac\n\t\t\tappend \"$var\" \"$1\"\n\t\t;;\n\tesac\n}\n\nenum_classes() {\n\tlocal c=\"0\"\n\tconfig_get classes \"$1\" classes\n\tconfig_get default \"$1\" default\n\tfor class in $classes; do\n\t\tc=\"$(($c + 1))\"\n\t\tconfig_set \"${class}\" classnr $c\n\t\tcase \"$class\" in\n\t\t\t$default) class_default=$c;;\n\t\tesac\n\tdone\n\tclass_default=\"${class_default:-$c}\"\n}\n\ncls_var() {\n\tlocal varname=\"$1\"\n\tlocal class=\"$2\"\n\tlocal name=\"$3\"\n\tlocal type=\"$4\"\n\tlocal default=\"$5\"\n\tlocal tmp tmp1 tmp2\n\tconfig_get tmp1 \"$class\" \"$name\"\n\tconfig_get tmp2 \"${class}_${type}\" \"$name\"\n\ttmp=\"${tmp2:-$tmp1}\"\n\ttmp=\"${tmp:-$tmp2}\"\n\texport ${varname}=\"${tmp:-$default}\"\n}\n\ntcrules() {\n\t_dir=/usr/lib/qos\n\t[ -e $_dir/tcrules.awk ] || _dir=.\n\techo \"$cstr\" | awk \\\n\t\t-v device=\"$dev\" \\\n\t\t-v linespeed=\"$rate\" \\\n\t\t-v direction=\"$dir\" \\\n\t\t-f $_dir/tcrules.awk\n}\n\nstart_interface() {\n\tlocal iface=\"$1\"\n\tlocal num_ifb=\"$2\"\n\tconfig_get device \"$iface\" device\n\tconfig_get_bool enabled \"$iface\" enabled 1\n\t[ -z \"$device\" -o 1 -ne \"$enabled\" ] && {\n\t\treturn 1 \n\t}\n\tconfig_get upload \"$iface\" upload\n\tconfig_get_bool halfduplex \"$iface\" halfduplex\n\tconfig_get download \"$iface\" download\n\tconfig_get classgroup \"$iface\" classgroup\n\tconfig_get_bool overhead \"$iface\" overhead 0\n\t\n\tdownload=\"${download:-${halfduplex:+$upload}}\"\n\tenum_classes \"$classgroup\"\n\tfor dir in ${halfduplex:-up} ${download:+down}; do\n\t\tcase \"$dir\" in\n\t\t\tup)\n\t\t\t\t[ \"$overhead\" = 1 ] && upload=$(($upload * 98 / 100 - (15 * 128 / $upload)))\n\t\t\t\tdev=\"$device\"\n\t\t\t\trate=\"$upload\"\n\t\t\t\tdl_mode=\"\"\n\t\t\t\tprefix=\"cls\"\n\t\t\t;;\n\t\t\tdown)\n\t\t\t\t[ \"$(ls -d /proc/sys/net/ipv4/conf/ifb* 2>&- | wc -l)\" -ne \"$num_ifb\" ] && add_insmod ifb numifbs=\"$num_ifb\"\n\t\t\t\tconfig_get ifbdev \"$iface\" ifbdev\n\t\t\t\t[ \"$overhead\" = 1 ] && download=$(($download * 98 / 100 - (80 * 1024 / $download)))\n\t\t\t\tdev=\"ifb$ifbdev\"\n\t\t\t\trate=\"$download\"\n\t\t\t\tdl_mode=1\n\t\t\t\tprefix=\"d_cls\"\n\t\t\t;;\n\t\t\t*) continue;;\n\t\tesac\n\t\tcstr=\n\t\tfor class in $classes; do\n\t\t\tcls_var pktsize \"$class\" packetsize $dir 1500\n\t\t\tcls_var pktdelay \"$class\" packetdelay $dir 0\n\t\t\tcls_var maxrate \"$class\" limitrate $dir 100\n\t\t\tcls_var prio \"$class\" priority $dir 1\n\t\t\tcls_var avgrate \"$class\" avgrate $dir 0\n\t\t\tcls_var qdisc \"$class\" qdisc $dir \"\"\n\t\t\tcls_var filter \"$class\" filter $dir \"\"\n\t\t\tconfig_get classnr \"$class\" classnr\n\t\t\tappend cstr \"$classnr:$prio:$avgrate:$pktsize:$pktdelay:$maxrate:$qdisc:$filter\" \"$N\"\n\t\tdone\n\t\tappend ${prefix}q \"$(tcrules)\" \"$N\"\n\t\texport dev_${dir}=\"ip link add ${dev} type ifb >&- 2>&-\nip link set $dev up >&- 2>&-\ntc qdisc del dev $dev root >&- 2>&-\ntc qdisc add dev $dev root handle 1: hfsc default ${class_default}0\ntc class add dev $dev parent 1: classid 1:1 hfsc sc rate ${rate}kbit ul rate ${rate}kbit\"\n\tdone\n\t[ -n \"$download\" ] && {\n\t\tadd_insmod cls_u32\n\t\tadd_insmod em_u32\n\t\tadd_insmod act_connmark\n\t\tadd_insmod act_mirred\n\t\tadd_insmod sch_ingress\n\t}\n\tif [ -n \"$halfduplex\" ]; then\n\t\texport dev_up=\"tc qdisc del dev $device root >&- 2>&-\ntc qdisc add dev $device root handle 1: hfsc\ntc filter add dev $device parent 1: prio 10 u32 match u32 0 0 flowid 1:1 action mirred egress redirect dev ifb$ifbdev\"\n\telif [ -n \"$download\" ]; then\n\t\tappend dev_${dir} \"tc qdisc del dev $device ingress >&- 2>&-\ntc qdisc add dev $device ingress\ntc filter add dev $device parent ffff: prio 1 u32 match u32 0 0 flowid 1:1 action connmark action mirred egress redirect dev ifb$ifbdev\" \"$N\"\n\tfi\n\tadd_insmod cls_fw\n\tadd_insmod sch_hfsc\n\n\tcat <<EOF\n${INSMOD:+$INSMOD$N}${dev_up:+$dev_up\n$clsq\n}${ifbdev:+$dev_down\n$d_clsq\n$d_clsl\n$d_clsf\n}\nEOF\n\tunset INSMOD clsq clsf clsl d_clsq d_clsl d_clsf dev_up dev_down\n}\n\nstart_interfaces() {\n\tlocal C=\"$1\"\n\tfor iface in $INTERFACES; do\n\t\tstart_interface \"$iface\" \"$C\"\n\tdone\n}\n\nadd_rules() {\n\tlocal var=\"$1\"\n\tlocal rules=\"$2\"\n\tlocal prefix=\"$3\"\n\t\n\tfor rule in $rules; do\n\t\tunset iptrule\n\t\tconfig_get target \"$rule\" target\n\t\tconfig_get target \"$target\" classnr\n\t\tconfig_get options \"$rule\" options\n\n\t\t## If we want to override the TOS field, let's clear the DSCP field first.\n\t\t[ ! -z \"$(echo $options | grep 'TOS')\" ] && {\n\t\t\ts_options=${options%%TOS}\n\t\t\tadd_insmod xt_DSCP\n\t\t\tparse_matching_rule iptrule \"$rule\" \"$s_options\" \"$prefix\" \"-j DSCP --set-dscp 0\"\n\t\t\tappend \"$var\" \"$iptrule\" \"$N\"\n\t\t\tunset iptrule\n\t\t}\n\n\t\ttarget=$(($target | ($target << 4)))\n\t\tparse_matching_rule iptrule \"$rule\" \"$options\" \"$prefix\" \"-j MARK --set-mark $target/0xff\"\n\t\tappend \"$var\" \"$iptrule\" \"$N\"\n\tdone\n}\n\nstart_cg() {\n\tlocal cg=\"$1\"\n\tlocal iptrules\n\tlocal pktrules\n\tlocal sizerules\n\tenum_classes \"$cg\"\n\tfor command in $iptables; do\n\t\tadd_rules iptrules \"$ctrules\" \"$command -w -t mangle -A qos_${cg}_ct\"\n\tdone\n\tconfig_get classes \"$cg\" classes\n\tfor class in $classes; do\n\t\tconfig_get mark \"$class\" classnr\n\t\tconfig_get maxsize \"$class\" maxsize\n\t\t[ -z \"$maxsize\" -o -z \"$mark\" ] || {\n\t\t\tadd_insmod xt_length\n\t\t\tfor command in $iptables; do\n\t\t\t\tappend pktrules \"$command -w -t mangle -A qos_${cg} -m mark --mark $mark/0x0f -m length --length $maxsize: -j MARK --set-mark 0/0xff\" \"$N\"\n\t\t\tdone\n\t\t}\n\tdone\n\tfor command in $iptables; do\n\t\tadd_rules pktrules \"$rules\" \"$command -w -t mangle -A qos_${cg}\"\n\tdone\n\tfor iface in $INTERFACES; do\n\t\tconfig_get classgroup \"$iface\" classgroup\n\t\tconfig_get device \"$iface\" device\n\t\tconfig_get ifbdev \"$iface\" ifbdev\n\t\tconfig_get upload \"$iface\" upload\n\t\tconfig_get download \"$iface\" download\n\t\tconfig_get halfduplex \"$iface\" halfduplex\n\t\tdownload=\"${download:-${halfduplex:+$upload}}\"\n\t\tfor command in $iptables; do\n\t\t\tappend up \"$command -w -t mangle -A OUTPUT -o $device -j qos_${cg}\" \"$N\"\n\t\t\tappend up \"$command -w -t mangle -A FORWARD -o $device -j qos_${cg}\" \"$N\"\n\t\tdone\n\tdone\n\tcat <<EOF\n$INSMOD\nEOF\n\nfor command in $iptables; do\n\tcat <<EOF\n\t$command -w -t mangle -N qos_${cg} \n\t$command -w -t mangle -N qos_${cg}_ct\nEOF\ndone\ncat <<EOF\n\t${iptrules:+${iptrules}${N}}\nEOF\nfor command in $iptables; do\n\tcat <<EOF\n\t$command -w -t mangle -A qos_${cg}_ct -j CONNMARK --save-mark --mask 0xff\n\t$command -w -t mangle -A qos_${cg} -j CONNMARK --restore-mark --mask 0x0f\n\t$command -w -t mangle -A qos_${cg} -m mark --mark 0/0x0f -j qos_${cg}_ct\nEOF\ndone\ncat <<EOF\n$pktrules\nEOF\nfor command in $iptables; do\n\tcat <<EOF\n\t$command -w -t mangle -A qos_${cg} -j CONNMARK --save-mark --mask 0xff\nEOF\ndone\ncat <<EOF\n$up$N${down:+${down}$N}\nEOF\n\tunset INSMOD\n}\n\nstart_firewall() {\n\tadd_insmod xt_multiport\n\tadd_insmod xt_connmark\n\tstop_firewall\n\tfor group in $CG; do\n\t\tstart_cg $group\n\tdone\n}\n\nstop_firewall() {\n\t# Builds up a list of iptables commands to flush the qos_* chains,\n\t# remove rules referring to them, then delete them\n\n\t# Print rules in the mangle table, like iptables-save\n\tfor command in $iptables; do\n\t\t$command -w -t mangle -S |\n\t\t\t# Find rules for the qos_* chains\n\t\t\tgrep -E '(^-N qos_|-j qos_)' |\n\t\t\t# Exclude rules in qos_* chains (inter-qos_* refs)\n\t\t\tgrep -v '^-A qos_' |\n\t\t\t# Replace -N with -X and hold, with -F and print\n\t\t\t# Replace -A with -D\n\t\t\t# Print held lines at the end (note leading newline)\n\t\t\tsed -e '/^-N/{s/^-N/-X/;H;s/^-X/-F/}' \\\n\t\t\t\t-e 's/^-A/-D/' \\\n\t\t\t\t-e '${p;g}' |\n\t\t\t# Make into proper iptables calls\n\t\t\t# Note: awkward in previous call due to hold space usage\n\t\t\tsed -n -e \"s/^./${command} -w -t mangle &/p\"\n\tdone\n}\n\nC=\"0\"\nINTERFACES=\"\"\n[ -e ./qos.conf ] && {\n\t. ./qos.conf\n\tconfig_cb\n} || {\n\tconfig_load qos\n\tconfig_foreach qos_parse_config\n}\n\nC=\"0\"\nfor iface in $INTERFACES; do\n\texport C=\"$(($C + 1))\"\ndone\n\n[ -x /usr/sbin/ip6tables ] && {\n\tiptables=\"ip6tables iptables\"\n} || {\n\tiptables=\"iptables\"\n}\n\ncase \"$1\" in\n\tall)\n\t\tstart_interfaces \"$C\"\n\t\tstart_firewall\n\t;;\n\tinterface)\n\t\tstart_interface \"$2\" \"$C\"\n\t;;\n\tinterfaces)\n\t\tstart_interfaces\n\t;;\n\tfirewall)\n\t\tcase \"$2\" in\n\t\t\tstop)\n\t\t\t\tstop_firewall\n\t\t\t;;\n\t\t\tstart|\"\")\n\t\t\t\tstart_firewall\n\t\t\t;;\n\t\tesac\n\t;;\nesac\n"
  },
  {
    "path": "package/network/config/qos-scripts/files/usr/lib/qos/tcrules.awk",
    "content": "BEGIN {\n\tdmax=100\n\tif (!(linespeed > 0)) linespeed = 128\n\tFS=\":\"\n\tn = 0\n}\n\n($1 != \"\") {\n\tn++\n\tclass[n] = $1\n\tprio[n] = $2\n\tavgrate[n] = ($3 * linespeed / 100)\n\tpktsize[n] = $4\n\tdelay[n] = $5\n\tmaxrate[n] = ($6 * linespeed / 100)\n\tqdisc[n] = $7\n\tfilter[n] = $8\n}\n\nEND {\n\tallocated = 0\n\tmaxdelay = 0\n\n\tfor (i = 1; i <= n; i++) {\n\t\t# set defaults\n\t\tif (!(pktsize[i] > 0)) pktsize[i] = 1500\n\t\tif (!(prio[i] > 0)) prio[i] = 1\n\n\t\tallocated += avgrate[i]\n\t\tsum_prio += prio[i]\n\t\tif ((avgrate[i] > 0) && !(delay[i] > 0)) {\n\t\t\tsum_rtprio += prio[i]\n\t\t}\n\t}\n\n\t# allocation of m1 in rt classes:\n\t# sum(d * m1) must not exceed dmax * (linespeed - allocated)\n\tdmax = 0\n\tfor (i = 1; i <= n; i++) {\n\t\tif (avgrate[i] > 0) {\n\t\t\trtm2[i] = avgrate[i]\n\t\t\tif (delay[i] > 0) {\n\t\t\t\td[i] = delay[i]\n\t\t\t} else {\n\t\t\t\td[i] = 2 * pktsize[i] * 1000 / (linespeed * 1024)\n\t\t\t\tif (d[i] > dmax) dmax = d[i]\n\t\t\t}\n\t\t}\n\t}\n\n\tds_avail = dmax * (linespeed - allocated)\n\tfor (i = 1; i <= n; i++) {\n\t\tlsm1[i] = 0\n\t\trtm1[i] = 0\n\t\tlsm2[i] = linespeed * prio[i] / sum_prio\n\t\tif ((avgrate[i] > 0) && (d[i] > 0)) {\n\t\t\tif (!(delay[i] > 0)) {\n\t\t\t\tds = ds_avail * prio[i] / sum_rtprio\n\t\t\t\tds_avail -= ds\n\t\t\t\trtm1[i] = rtm2[i] + ds/d[i]\n\t\t\t}\n\t\t\tlsm1[i] = rtm1[i]\n\t\t}\n\t\telse {\n\t\t\td[i] = 0\n\t\t}\n\t}\n\n\t# main qdisc\n\tfor (i = 1; i <= n; i++) {\n\t\tprintf \"tc class add dev \"device\" parent 1:1 classid 1:\"class[i]\"0 hfsc\"\n\t\tif (rtm1[i] > 0) {\n\t\t\tprintf \" rt m1 \" int(rtm1[i]) \"kbit d \" int(d[i] * 1000) \"us m2 \" int(rtm2[i])\"kbit\"\n\t\t}\n\t\tprintf \" ls m1 \" int(lsm1[i]) \"kbit d \" int(d[i] * 1000) \"us m2 \" int(lsm2[i]) \"kbit\"\n\t\tprint \" ul rate \" int(maxrate[i]) \"kbit\"\n\t}\n\n\t# leaf qdisc\n\tavpkt = 1200\n\tfor (i = 1; i <= n; i++) {\n\t\tprint \"tc qdisc add dev \"device\" parent 1:\"class[i]\"0 handle \"class[i]\"00: fq_codel limit 800 quantum 300 noecn\"\n\t}\n\n\t# filter rule\n\tfor (i = 1; i <= n; i++) {\n\t\tfilter_cmd = \"tc filter add dev \"device\" parent 1: prio %d handle %s fw flowid 1:%d0\\n\";\n\t\tif (direction == \"up\") {\n\t\t\tfilter_1 = sprintf(\"0x%x0/0xf0\", class[i])\n\t\t\tfilter_2 = sprintf(\"0x0%x/0x0f\", class[i])\n\t\t} else {\n\t\t\tfilter_1 = sprintf(\"0x0%x/0x0f\", class[i])\n\t\t\tfilter_2 = sprintf(\"0x%x0/0xf0\", class[i])\n\t\t}\n\n\t\tprintf filter_cmd, class[i] * 2, filter_1, class[i]\n\t\tprintf filter_cmd, class[i] * 2 + 1, filter_2, class[i]\n\n\t\tfilterc=1\n\t\tif (filter[i] != \"\") {\n\t\t\tprint \" tc filter add dev \"device\" parent \"class[i]\"00: handle \"filterc\"0 \"filter[i]\n\t\t\tfilterc=filterc+1\n\t\t}\n\t}\n}\n\n"
  },
  {
    "path": "package/network/config/qosify/Makefile",
    "content": "#\n# Copyright (C) 2021 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\ninclude $(INCLUDE_DIR)/kernel.mk\n\nPKG_NAME:=qosify\nPKG_SOURCE_URL=$(PROJECT_GIT)/project/qosify.git\nPKG_SOURCE_PROTO:=git\nPKG_SOURCE_DATE:=2022-04-08\nPKG_SOURCE_VERSION:=ef82defaae26619e5b2ebddfdd86e9de61c399f1\nPKG_MIRROR_HASH:=8e4ca65d23a85aad774af51dc62cfaa4615111ffd2c7922258ac8f026a62b013\nPKG_RELEASE:=$(AUTORELEASE)\n\nPKG_LICENSE:=GPL-2.0\nPKG_MAINTAINER:=Felix Fietkau <nbd@nbd.name>\n\nPKG_BUILD_DEPENDS:=bpf-headers\nPKG_FLAGS:=nonshared\n\ninclude $(INCLUDE_DIR)/package.mk\ninclude $(INCLUDE_DIR)/cmake.mk\ninclude $(INCLUDE_DIR)/bpf.mk\ninclude $(INCLUDE_DIR)/nls.mk\n\ndefine Package/qosify\n  SECTION:=utils\n  CATEGORY:=Base system\n  TITLE:=A simple QoS solution based eBPF + CAKE\n  DEPENDS:=+libbpf +libubox +libubus +libnl-tiny +kmod-sched-cake +kmod-sched-bpf +kmod-ifb +tc $(BPF_DEPENDS)\nendef\n\nTARGET_CFLAGS += \\\n\t-Wno-error=deprecated-declarations \\\n\t-I$(STAGING_DIR)/usr/include/libnl-tiny \\\n\t-I$(STAGING_DIR)/usr/include\n\nCMAKE_OPTIONS += \\\n\t-DLIBNL_LIBS=-lnl-tiny\n\ndefine Build/Compile\n\t$(call CompileBPF,$(PKG_BUILD_DIR)/qosify-bpf.c)\n\t$(Build/Compile/Default)\nendef\n\ndefine Package/qosify/conffiles\n/etc/config/qosify\n/etc/qosify/00-defaults.conf\nendef\n\ndefine Package/qosify/install\n\t$(INSTALL_DIR) \\\n\t\t$(1)/lib/bpf \\\n\t\t$(1)/usr/sbin \\\n\t\t$(1)/etc/init.d \\\n\t\t$(1)/etc/config \\\n\t\t$(1)/etc/qosify \\\n\t\t$(1)/etc/hotplug.d/net \\\n\t\t$(1)/etc/hotplug.d/iface\n\t$(INSTALL_DATA) $(PKG_BUILD_DIR)/qosify-bpf.o $(1)/lib/bpf\n\t$(INSTALL_BIN) \\\n\t\t$(PKG_INSTALL_DIR)/usr/bin/qosify \\\n\t\t./files/qosify-status \\\n\t\t$(1)/usr/sbin/\n\t$(INSTALL_BIN) ./files/qosify.init $(1)/etc/init.d/qosify\n\t$(INSTALL_DATA) ./files/qosify-defaults.conf $(1)/etc/qosify/00-defaults.conf\n\t$(INSTALL_DATA) ./files/qosify.conf $(1)/etc/config/qosify\n\t$(INSTALL_DATA) ./files/qosify.hotplug $(1)/etc/hotplug.d/net/10-qosify\n\t$(INSTALL_DATA) ./files/qosify.hotplug $(1)/etc/hotplug.d/iface/10-qosify\nendef\n\n$(eval $(call BuildPackage,qosify))\n"
  },
  {
    "path": "package/network/config/qosify/files/qosify-defaults.conf",
    "content": "# DNS\ntcp:53\t\tvoice\ntcp:5353\tvoice\nudp:53\t\tvoice\nudp:5353\tvoice\n\n# NTP\nudp:123\t\tvoice\n\n# SSH\ntcp:22\t\t+video\n\n# HTTP/QUIC\ntcp:80\t\t+besteffort\ntcp:443\t\t+besteffort\nudp:80\t\t+besteffort\nudp:443\t\t+besteffort\n"
  },
  {
    "path": "package/network/config/qosify/files/qosify-status",
    "content": "#!/bin/sh\n. /usr/share/libubox/jshn.sh\n\ndev_status() {\n\ttc -s qdisc sh dev \"$1\" root\n\techo\n}\n\ncommon_status() {\n\tjson_get_vars ifname ingress egress\n\n\t[ -n \"$ifname\" ] || return\n\n\t[ \"$egress\" -gt 0 ] && {\n\t\techo \"egress status:\"\n\t\tdev_status \"$ifname\"\n\t}\n\t[ \"$ingress\" -gt 0 ] && {\n\t\techo \"ingress status:\"\n\t\tdev_status \"$(printf %.16s \"ifb-$ifname\")\"\n\t}\n}\n\nis_active() {\n\tjson_get_vars active\n\n\t[ \"${active:-0}\" -gt 0 ]\n}\n\ndevice_status() {\n\tlocal name=\"$2\"\n\n\tjson_select \"$name\"\n\n\tif is_active; then\n\t\tstatus=\"active\"\n\telse\n\t\tstatus=\"not found\"\n\tfi\n\n\techo \"===== device $name: $status =====\"\n\n\tis_active && common_status\n\n\tjson_select ..\n}\n\ninterface_status() {\n\tlocal name=\"$2\"\n\n\tjson_select \"$name\"\n\n\tif is_active; then\n\t\tstatus=\"active\"\n\telif ubus -S -t 0 wait_for \"network.interface.$name\"; then\n\t\tstatus=\"down\"\n\telse\n\t\tstatus=\"not found\"\n\tfi\n\n\techo \"===== interface $name: $status =====\"\n\n\tis_active && common_status\n\n\tjson_select ..\n}\n\njson_load \"$(ubus call qosify status)\"\njson_for_each_item device_status devices\njson_for_each_item interface_status interfaces\n"
  },
  {
    "path": "package/network/config/qosify/files/qosify.conf",
    "content": "config defaults\n\tlist defaults /etc/qosify/*.conf\n\toption dscp_prio video\n\toption dscp_icmp +besteffort\n\toption dscp_default_udp besteffort\n\toption prio_max_avg_pkt_len 500\n\nconfig class besteffort\n\toption ingress CS0\n\toption egress CS0\n\nconfig class bulk\n\toption ingress LE\n\toption egress LE\n\nconfig class video\n\toption ingress AF41\n\toption egress AF41\n\nconfig class voice\n\toption ingress CS6\n\toption egress CS6\n\toption bulk_trigger_pps 100\n\toption bulk_trigger_timeout 5\n\toption dscp_bulk CS0\n\nconfig interface wan\n\toption name wan\n\toption disabled 1\n\toption bandwidth_up 100mbit\n\toption bandwidth_down 100mbit\n\toption overhead_type none\n\t# defaults:\n\toption ingress 1\n\toption egress 1\n\toption mode diffserv4\n\toption nat 1\n\toption host_isolate 1\n\toption autorate_ingress 0\n\toption ingress_options \"\"\n\toption egress_options \"\"\n\toption options \"\"\n\nconfig device wandev\n\toption disabled 1\n\toption name wan\n\toption bandwidth 100mbit\n\n"
  },
  {
    "path": "package/network/config/qosify/files/qosify.hotplug",
    "content": "#!/bin/sh\nubus call qosify check_devices\n"
  },
  {
    "path": "package/network/config/qosify/files/qosify.init",
    "content": "#!/bin/sh /etc/rc.common\n# Copyright (c) 2021 OpenWrt.org\n\nSTART=19\n\nUSE_PROCD=1\nPROG=/usr/sbin/qosify\n\nadd_option() {\n\tlocal type=\"$1\"\n\tlocal name=\"$2\"\n\n\tconfig_get val \"$cfg\" \"$name\"\n\n\t[ -n \"$val\" ] && json_add_$type \"$name\" \"$val\"\n}\n\nadd_flow_config() {\n\tlocal cfg=\"$1\"\n\n\tadd_option string dscp_prio\n\tadd_option string dscp_bulk\n\tadd_option int bulk_trigger_timeout\n\tadd_option int bulk_trigger_pps\n\tadd_option int prio_max_avg_pkt_len\n}\n\nadd_defaults() {\n\tcfg=\"$1\"\n\n\tjson_add_boolean reset 1\n\n\tconfig_get files \"$cfg\" defaults\n\tjson_add_array files\n\tfor i in $files; do\n\t\tjson_add_string \"\" \"$i\"\n\tdone\n\tjson_close_array\n\n\tadd_flow_config \"$cfg\"\n\tadd_option int timeout\n\tadd_option string dscp_icmp\n\tadd_option string dscp_default_udp\n\tadd_option string dscp_default_tcp\n}\n\nadd_interface() {\n\tlocal cfg=\"$1\"\n\n\tconfig_get_bool disabled \"$cfg\" disabled 0\n\t[ \"$disabled\" -gt 0 ] && return\n\n\tconfig_get name \"$cfg\" name\n\tjson_add_object \"$name\"\n\n\tconfig_get bw \"$cfg\" bandwidth\n\n\tconfig_get bw_up \"$cfg\" bandwidth_up\n\tbw_up=\"${bw_up:-$bw}\"\n\t[ -n \"$bw_up\" ] && json_add_string bandwidth_up \"$bw_up\"\n\n\tconfig_get bw_down \"$cfg\" bandwidth_down\n\tbw_down=\"${bw_down:-$bw}\"\n\t[ -n \"$bw_down\" ] && json_add_string bandwidth_down \"$bw_down\"\n\n\tadd_option string bandwidth\n\tadd_option boolean ingress\n\tadd_option boolean egress\n\tadd_option string mode\n\tadd_option boolean nat\n\tadd_option boolean host_isolate\n\tadd_option boolean autorate_ingress\n\tadd_option string ingress_options\n\tadd_option string egress_options\n\n\tconfig_get user_options \"$cfg\" options\n\n\tconfig_get otype \"$cfg\" overhead_type\n\toptions=\n\tcase \"$otype\" in\n\t\tnone);;\n\t\tmanual)\n\t\t\tconfig_get overhead \"$cfg\" overhead\n\t\t\t[ -n \"$overhead\" ] && append options \"overhead $overhead\"\n\n\t\t\tconfig_get encap \"$cfg\" overhead_encap\n\t\t\t[ -n \"$encap\" ] && append options \"$encap\"\n\t\t;;\n\t\tconservative|\\\n\t\tpppoa-vcmux|\\\n\t\tpppoa-llc|\\\n\t\tpppoe-vcmux|\\\n\t\tpppoe-llcsnap|\\\n\t\tbridged-vcmux|\\\n\t\tbridged-llcsnap|\\\n\t\tipoa-vcmux|\\\n\t\tipoa-llcsnap|\\\n\t\tpppoe-ptm|\\\n\t\tbridged-ptm|\\\n\t\tdocsis|\\\n\t\tethernet)\n\t\t\tappend options \"$otype\"\n\t\t;;\n\tesac\n\n\tconfig_get mpu \"$cfg\" overhead_mpu\n\t[ -n \"$mpu\" ] && append options \"mpu $mpu\"\n\n\tconfig_get ovlan \"$cfg\" overhead_vlan\n\t[ \"${ovlan:-0}\" -ge 2 ] && append options \"ether-vlan\"\n\t[ \"${ovlan:-0}\" -ge 1 ] && append options \"ether-vlan\"\n\n\t[ -n \"$user_options\" ] && append options \"$user_options\"\n\t[ -n \"$options\" ] && json_add_string options \"$options\"\n\n\tjson_close_object\n}\n\nadd_class() {\n\tlocal cfg=\"$1\"\n\n\tconfig_get value \"$cfg\" value\n\tconfig_get ingress \"$cfg\" ingress\n\tconfig_get egress \"$cfg\" egress\n\n\tjson_add_object \"$cfg\"\n\tjson_add_string ingress \"${ingress:-$value}\"\n\tjson_add_string egress \"${egress:-$value}\"\n\tadd_flow_config \"$cfg\"\n\tjson_close_object\n}\n\n\nreload_service() {\n\tjson_init\n\n\tconfig_load qosify\n\n\tconfig_foreach add_defaults defaults\n\n\tjson_add_object interfaces\n\tconfig_foreach add_interface interface\n\tjson_close_object\n\n\tjson_add_object classes\n\tconfig_foreach add_class class\n\tconfig_foreach add_class alias\n\tjson_close_object\n\n\tjson_add_object devices\n\tconfig_foreach add_interface device\n\tjson_close_object\n\n\tubus call qosify config \"$(json_dump)\"\n}\n\nservice_triggers() {\n\tprocd_add_reload_trigger qosify\n}\n\nstart_service() {\n\tprocd_open_instance\n\tprocd_set_param command \"$PROG\"\n\tprocd_set_param respawn\n\tprocd_close_instance\n}\n\nservice_started() {\n\tubus -t 10 wait_for qosify\n\t[ $? = 0 ] && reload_service\n}\n"
  },
  {
    "path": "package/network/config/soloscli/Makefile",
    "content": "#\n# Copyright (C) 2006-2014 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=soloscli\nPKG_VERSION:=1.04\nPKG_RELEASE:=3\n\nPKG_SOURCE:=solos-pci-$(PKG_VERSION).tar.gz\nPKG_SOURCE_URL:=@SF/openadsl\nPKG_HASH:=6379e6970a5c97fd5a223d024138ebb71b15d70e2ad1fe9da09edc5b2d760e1d\nPKG_LICENSE:=GPL-2.0\n\nPKG_BUILD_DIR:=$(BUILD_DIR)/solos-pci-$(PKG_VERSION)\nPKG_BUILD_PARALLEL:=1\n\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine Package/soloscli\n  SECTION:=net\n  CATEGORY:=Network\n  TITLE:=Configuration utility for Solos ADSL2+ modems\n  DEPENDS:=+kmod-solos-pci\n  URL:=http://sourceforge.net/projects/openadsl\nendef\n\ndefine Package/soloscli/description\n  This package contains the soloscli utility\n  for interrogating Traverse Technologies' Solos ADSL2+ modems.\nendef\n\ndefine Package/soloscli/install\n\t$(INSTALL_DIR) $(1)/usr/bin\n\t$(INSTALL_BIN) $(PKG_BUILD_DIR)/soloscli/soloscli $(1)/usr/bin/\n\t$(INSTALL_BIN) ./files/solos-log-stats $(1)/usr/bin/\n\t$(INSTALL_DIR) $(1)/etc/hotplug.d/atm\n\t$(INSTALL_CONF) ./files/etc/hotplug.d/atm/15-solos-init $(1)/etc/hotplug.d/atm/\nendef\n\n$(eval $(call BuildPackage,soloscli))\n"
  },
  {
    "path": "package/network/config/soloscli/files/etc/hotplug.d/atm/15-solos-init",
    "content": "#!/bin/sh\n\ndialog() {\n\tlocal tag=\"$(echo \"$1\" | cut -d= -f1)\"\n\tlocal value=\"$(echo \"$1\" | cut -d= -f2-)\"\n\tlocal response\n\t\n\tresponse=\"$(soloscli -s \"$port\" \"$tag\" \"$value\")\"\n\t[ $? -ne 0 ] && {\n\t\tlogger \"soloscli($port): $tag '$value' returns $response\"\n\t}\n}\n\nif [ \"$ACTION\" = \"add\" ]; then\n\tinclude /lib/network\n\tscan_interfaces\n\n\tcase $DEVICENAME in\n\tsolos-pci[0-3])\n\t\tport=\"${DEVICENAME#solos-pci}\"\n\t\tdevice=\"solos${port}\"\n\n\t\tconfig_list_foreach wan \"$device\" dialog\n\t\t;;\n\tesac\nfi\n"
  },
  {
    "path": "package/network/config/soloscli/files/etc/uci-defaults/solos",
    "content": "uci batch <<__EOF__\n\ndelete network.wan.solos0\n\nadd_list network.wan.solos0=\"ActivateLine=Abort\"\nadd_list network.wan.solos0=\"Retrain=EnableAll\"\nadd_list network.wan.solos0=\"DetectNoise=Enable\"\nadd_list network.wan.solos0=\"BisMCapability=Disable\"\nadd_list network.wan.solos0=\"BisACapability=Disable\"\nadd_list network.wan.solos0=\"ActivateLine=Start\"\n\ncommit network\n__EOF__\n"
  },
  {
    "path": "package/network/config/soloscli/files/solos-log-stats",
    "content": "#!/bin/sh\n\ncd /sys/class/atm/ || exit 1\n\nfor PORT in solos-pci* ; do\n\n    RXRATE=`cat $PORT/parameters/RxBitRate`\n    TXRATE=`cat $PORT/parameters/TxBitRate`\n    RXSNR=`cat $PORT/parameters/LocalSNRMargin | sed \"s/ dB//\"`\n    TXSNR=`cat $PORT/parameters/RemoteSNRMargin | sed \"s/ dB//\"`\n    RXERR=`cat $PORT/parameters/RSUnCorrectedErrorsDn`\n    TXERR=`cat $PORT/parameters/RSUnCorrectedErrorsUp`\n    RXFEC=`cat $PORT/parameters/RSCorrectedErrorsDn`\n    TXFEC=`cat $PORT/parameters/RSCorrectedErrorsUp`\n\n    echo \"$RXRATE $RXSNR $RXERR $RXFEC / $TXRATE $TXSNR $TXERR $TXFEC\" |\n       logger -t $PORT\ndone\n\n"
  },
  {
    "path": "package/network/config/soloscli/patches/001-no-driver.patch",
    "content": "--- a/Makefile\n+++ b/Makefile\n@@ -11,7 +11,7 @@ else\n KDIR\t?= /lib/modules/$(shell uname -r)/build\n PWD\t:= $(shell pwd)\n \n-all: soloscli driver\n+all: soloscli\n \n soloscli: soloscli/soloscli\n \n"
  },
  {
    "path": "package/network/config/soloscli/patches/002-cflags.patch",
    "content": "--- a/soloscli/Makefile\n+++ b/soloscli/Makefile\n@@ -4,9 +4,6 @@\n # Last Mod: 2009-06-16\n #\n \n-CC=gcc\n-CFLAGS=-Wall\n-\n soloscli: soloscli.c soloscli.h\n \n clean:\n"
  },
  {
    "path": "package/network/config/swconfig/Makefile",
    "content": "#\n# Copyright (C) 2008-2010 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=swconfig\nPKG_RELEASE:=12\n\nPKG_MAINTAINER:=Felix Fietkau <nbd@nbd.name>\nPKG_LICENSE:=GPL-2.0\n\ninclude $(INCLUDE_DIR)/package.mk\ninclude $(INCLUDE_DIR)/kernel.mk\n\ndefine Package/swconfig\n  SECTION:=base\n  CATEGORY:=Base system\n  DEPENDS:=+libuci +libnl-tiny\n  TITLE:=Switch configuration utility\nendef\n\nTARGET_CFLAGS += -flto\nTARGET_LDFLAGS += -flto=jobserver\n\nTARGET_CPPFLAGS := \\\n\t-D_GNU_SOURCE \\\n\t-I$(STAGING_DIR)/usr/include/libnl-tiny \\\n\t-I$(PKG_BUILD_DIR) \\\n\t$(TARGET_CPPFLAGS) \\\n\t-I$(LINUX_DIR)/user_headers/include\n\ndefine Build/Compile\n\tCFLAGS=\"$(TARGET_CPPFLAGS) $(TARGET_CFLAGS)\" \\\n\t$(MAKE) -C $(PKG_BUILD_DIR) \\\n\t\t$(TARGET_CONFIGURE_OPTS) \\\n\t\tLIBS=\"$(TARGET_LDFLAGS) -lnl-tiny -lm -luci -lubox\"\nendef\n\ndefine Build/InstallDev\n\t$(INSTALL_DIR) $(1)/usr/include\n\t$(CP) $(PKG_BUILD_DIR)/swlib.h $(1)/usr/include/\n\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(CP) $(PKG_BUILD_DIR)/libsw.a $(1)/usr/lib/\nendef\n\ndefine Package/swconfig/install\n\t$(INSTALL_DIR) $(1)/sbin $(1)/lib/network\n\t$(INSTALL_BIN) $(PKG_BUILD_DIR)/swconfig $(1)/sbin/swconfig\n\t$(INSTALL_DATA) ./files/switch.sh $(1)/lib/network/\nendef\n\n$(eval $(call BuildPackage,swconfig))\n"
  },
  {
    "path": "package/network/config/swconfig/files/switch.sh",
    "content": "#!/bin/sh\n# Copyright (C) 2009 OpenWrt.org\n\nsetup_switch_dev() {\n\tlocal name\n\tconfig_get name \"$1\" name\n\tname=\"${name:-$1}\"\n\t[ -d \"/sys/class/net/$name\" ] && ip link set dev \"$name\" up\n\tswconfig dev \"$name\" load network\n}\n\nsetup_switch() {\n\tconfig_load network\n\tconfig_foreach setup_switch_dev switch\n}\n"
  },
  {
    "path": "package/network/config/swconfig/src/Makefile",
    "content": "ifndef CFLAGS\nCFLAGS = -O2 -g -I ../src\nendif\nLIBS=-lnl -lnl-genl\n\nall: swconfig\n\n%.o: %.c\n\t$(CC) $(CFLAGS) -fPIC -c -o $@ $^\n\nlibsw.a: swlib.o\n\t$(AR) rcu $@ swlib.o\n\t$(RANLIB) $@\n\nswconfig: libsw.a cli.o uci.o\n\t$(CC) $(LDFLAGS) -o $@ $^ $(LIBS) -L./ -lsw\n"
  },
  {
    "path": "package/network/config/swconfig/src/cli.c",
    "content": "/*\n * swconfig.c: Switch configuration utility\n *\n * Copyright (C) 2008 Felix Fietkau <nbd@nbd.name>\n * Copyright (C) 2010 Martin Mares <mj@ucw.cz>\n *\n * This program is free software; you can redistribute it and/or\n * modify it under the terms of the GNU General Public License\n * version 2 as published by the Free Software Foundatio.\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n * GNU General Public License for more details.\n */\n\n#include <stdio.h>\n#include <string.h>\n#include <stdlib.h>\n#include <inttypes.h>\n#include <errno.h>\n#include <stdint.h>\n#include <getopt.h>\n#include <sys/types.h>\n#include <sys/socket.h>\n#include <uci.h>\n\n#include <linux/types.h>\n#include <linux/netlink.h>\n#include <linux/genetlink.h>\n#include <netlink/netlink.h>\n#include <netlink/genl/genl.h>\n#include <netlink/genl/ctrl.h>\n#include <linux/switch.h>\n#include \"swlib.h\"\n\nenum {\n\tCMD_NONE,\n\tCMD_GET,\n\tCMD_SET,\n\tCMD_LOAD,\n\tCMD_HELP,\n\tCMD_SHOW,\n\tCMD_PORTMAP,\n};\n\nstatic void\nprint_attrs(const struct switch_attr *attr)\n{\n\tint i = 0;\n\twhile (attr) {\n\t\tconst char *type;\n\t\tswitch(attr->type) {\n\t\t\tcase SWITCH_TYPE_INT:\n\t\t\t\ttype = \"int\";\n\t\t\t\tbreak;\n\t\t\tcase SWITCH_TYPE_STRING:\n\t\t\t\ttype = \"string\";\n\t\t\t\tbreak;\n\t\t\tcase SWITCH_TYPE_PORTS:\n\t\t\t\ttype = \"ports\";\n\t\t\t\tbreak;\n\t\t\tcase SWITCH_TYPE_NOVAL:\n\t\t\t\ttype = \"none\";\n\t\t\t\tbreak;\n\t\t\tdefault:\n\t\t\t\ttype = \"unknown\";\n\t\t\t\tbreak;\n\t\t}\n\t\tprintf(\"\\tAttribute %d (%s): %s (%s)\\n\", ++i, type, attr->name, attr->description);\n\t\tattr = attr->next;\n\t}\n}\n\nstatic void\nlist_attributes(struct switch_dev *dev)\n{\n\tprintf(\"%s: %s(%s), ports: %d (cpu @ %d), vlans: %d\\n\", dev->dev_name, dev->alias, dev->name, dev->ports, dev->cpu_port, dev->vlans);\n\tprintf(\"     --switch\\n\");\n\tprint_attrs(dev->ops);\n\tprintf(\"     --vlan\\n\");\n\tprint_attrs(dev->vlan_ops);\n\tprintf(\"     --port\\n\");\n\tprint_attrs(dev->port_ops);\n}\n\nstatic const char *\nspeed_str(int speed)\n{\n\tswitch (speed) {\n\tcase 10:\n\t\treturn \"10baseT\";\n\tcase 100:\n\t\treturn \"100baseT\";\n\tcase 1000:\n\t\treturn \"1000baseT\";\n\tdefault:\n\t\tbreak;\n\t}\n\n\treturn \"unknown\";\n}\n\nstatic void\nprint_attr_val(const struct switch_attr *attr, const struct switch_val *val)\n{\n\tstruct switch_port_link *link;\n\tint i;\n\n\tswitch (attr->type) {\n\tcase SWITCH_TYPE_INT:\n\t\tprintf(\"%d\", val->value.i);\n\t\tbreak;\n\tcase SWITCH_TYPE_STRING:\n\t\tprintf(\"%s\", val->value.s);\n\t\tbreak;\n\tcase SWITCH_TYPE_PORTS:\n\t\tfor(i = 0; i < val->len; i++) {\n\t\t\tprintf(\"%d%s \",\n\t\t\t\tval->value.ports[i].id,\n\t\t\t\t(val->value.ports[i].flags &\n\t\t\t\t SWLIB_PORT_FLAG_TAGGED) ? \"t\" : \"\");\n\t\t}\n\t\tbreak;\n\tcase SWITCH_TYPE_LINK:\n\t\tlink = val->value.link;\n\t\tif (link->link)\n\t\t\tprintf(\"port:%d link:up speed:%s %s-duplex %s%s%s%s%s\",\n\t\t\t\tval->port_vlan,\n\t\t\t\tspeed_str(link->speed),\n\t\t\t\tlink->duplex ? \"full\" : \"half\",\n\t\t\t\tlink->tx_flow ? \"txflow \" : \"\",\n\t\t\t\tlink->rx_flow ? \"rxflow \" : \"\",\n\t\t\t\tlink->eee & SWLIB_LINK_FLAG_EEE_100BASET ? \"eee100 \" : \"\",\n\t\t\t\tlink->eee & SWLIB_LINK_FLAG_EEE_1000BASET ? \"eee1000 \" : \"\",\n\t\t\t\tlink->aneg ? \"auto\" : \"\");\n\t\telse\n\t\t\tprintf(\"port:%d link:down\", val->port_vlan);\n\t\tbreak;\n\tdefault:\n\t\tprintf(\"?unknown-type?\");\n\t}\n}\n\nstatic void\nshow_attrs(struct switch_dev *dev, struct switch_attr *attr, struct switch_val *val)\n{\n\twhile (attr) {\n\t\tif (attr->type != SWITCH_TYPE_NOVAL) {\n\t\t\tprintf(\"\\t%s: \", attr->name);\n\t\t\tif (swlib_get_attr(dev, attr, val) < 0)\n\t\t\t\tprintf(\"???\");\n\t\t\telse\n\t\t\t\tprint_attr_val(attr, val);\n\t\t\tputchar('\\n');\n\t\t}\n\t\tattr = attr->next;\n\t}\n}\n\nstatic void\nshow_global(struct switch_dev *dev)\n{\n\tstruct switch_val val;\n\n\tprintf(\"Global attributes:\\n\");\n\tshow_attrs(dev, dev->ops, &val);\n}\n\nstatic void\nshow_port(struct switch_dev *dev, int port)\n{\n\tstruct switch_val val;\n\n\tprintf(\"Port %d:\\n\", port);\n\tval.port_vlan = port;\n\tshow_attrs(dev, dev->port_ops, &val);\n}\n\nstatic void\nshow_vlan(struct switch_dev *dev, int vlan, bool all)\n{\n\tstruct switch_val val;\n\tstruct switch_attr *attr;\n\n\tval.port_vlan = vlan;\n\n\tif (all) {\n\t\tattr = swlib_lookup_attr(dev, SWLIB_ATTR_GROUP_VLAN, \"ports\");\n\t\tif (swlib_get_attr(dev, attr, &val) < 0)\n\t\t\treturn;\n\n\t\tif (!val.len)\n\t\t\treturn;\n\t}\n\n\tprintf(\"VLAN %d:\\n\", vlan);\n\tshow_attrs(dev, dev->vlan_ops, &val);\n}\n\nstatic void\nprint_usage(void)\n{\n\tprintf(\"swconfig list\\n\");\n\tprintf(\"swconfig dev <dev> [port <port>|vlan <vlan>] (help|set <key> <value>|get <key>|load <config>|show)\\n\");\n\texit(1);\n}\n\nstatic void\nswconfig_load_uci(struct switch_dev *dev, const char *name)\n{\n\tstruct uci_context *ctx;\n\tstruct uci_package *p = NULL;\n\tint ret = -1;\n\n\tctx = uci_alloc_context();\n\tif (!ctx)\n\t\treturn;\n\n\tuci_load(ctx, name, &p);\n\tif (!p) {\n\t\tuci_perror(ctx, \"Failed to load config file: \");\n\t\tgoto out;\n\t}\n\n\tret = swlib_apply_from_uci(dev, p);\n\tif (ret < 0)\n\t\tfprintf(stderr, \"Failed to apply configuration for switch '%s'\\n\", dev->dev_name);\n\nout:\n\tuci_free_context(ctx);\n\texit(ret);\n}\n\nint main(int argc, char **argv)\n{\n\tint retval = 0;\n\tstruct switch_dev *dev;\n\tstruct switch_attr *a;\n\tstruct switch_val val;\n\tint i;\n\n\tint cmd = CMD_NONE;\n\tchar *cdev = NULL;\n\tint cport = -1;\n\tint cvlan = -1;\n\tchar *ckey = NULL;\n\tchar *cvalue = NULL;\n\tchar *csegment = NULL;\n\n\tif((argc == 2) && !strcmp(argv[1], \"list\")) {\n\t\tswlib_list();\n\t\treturn 0;\n\t}\n\n\tif(argc < 4)\n\t\tprint_usage();\n\n\tif(strcmp(argv[1], \"dev\"))\n\t\tprint_usage();\n\n\tcdev = argv[2];\n\n\tfor(i = 3; i < argc; i++)\n\t{\n\t\tchar *arg = argv[i];\n\t\tif (cmd != CMD_NONE) {\n\t\t\tprint_usage();\n\t\t} else if (!strcmp(arg, \"port\") && i+1 < argc) {\n\t\t\tcport = atoi(argv[++i]);\n\t\t} else if (!strcmp(arg, \"vlan\") && i+1 < argc) {\n\t\t\tcvlan = atoi(argv[++i]);\n\t\t} else if (!strcmp(arg, \"help\")) {\n\t\t\tcmd = CMD_HELP;\n\t\t} else if (!strcmp(arg, \"set\") && i+1 < argc) {\n\t\t\tcmd = CMD_SET;\n\t\t\tckey = argv[++i];\n\t\t\tif (i+1 < argc)\n\t\t\t\tcvalue = argv[++i];\n\t\t} else if (!strcmp(arg, \"get\") && i+1 < argc) {\n\t\t\tcmd = CMD_GET;\n\t\t\tckey = argv[++i];\n\t\t} else if (!strcmp(arg, \"load\") && i+1 < argc) {\n\t\t\tif ((cport >= 0) || (cvlan >= 0))\n\t\t\t\tprint_usage();\n\t\t\tcmd = CMD_LOAD;\n\t\t\tckey = argv[++i];\n\t\t} else if (!strcmp(arg, \"portmap\")) {\n\t\t\tif (i + 1 < argc)\n\t\t\t\tcsegment = argv[++i];\n\t\t\tcmd = CMD_PORTMAP;\n\t\t} else if (!strcmp(arg, \"show\")) {\n\t\t\tcmd = CMD_SHOW;\n\t\t} else {\n\t\t\tprint_usage();\n\t\t}\n\t}\n\n\tif (cmd == CMD_NONE)\n\t\tprint_usage();\n\tif (cport > -1 && cvlan > -1)\n\t\tprint_usage();\n\n\tdev = swlib_connect(cdev);\n\tif (!dev) {\n\t\tfprintf(stderr, \"Failed to connect to the switch. Use the \\\"list\\\" command to see which switches are available.\\n\");\n\t\treturn 1;\n\t}\n\n\tswlib_scan(dev);\n\n\tif (cmd == CMD_GET || cmd == CMD_SET) {\n\t\tif(cport > -1)\n\t\t\ta = swlib_lookup_attr(dev, SWLIB_ATTR_GROUP_PORT, ckey);\n\t\telse if(cvlan > -1)\n\t\t\ta = swlib_lookup_attr(dev, SWLIB_ATTR_GROUP_VLAN, ckey);\n\t\telse\n\t\t\ta = swlib_lookup_attr(dev, SWLIB_ATTR_GROUP_GLOBAL, ckey);\n\n\t\tif(!a)\n\t\t{\n\t\t\tfprintf(stderr, \"Unknown attribute \\\"%s\\\"\\n\", ckey);\n\t\t\tretval = -1;\n\t\t\tgoto out;\n\t\t}\n\t}\n\n\tswitch(cmd)\n\t{\n\tcase CMD_SET:\n\t\tif ((a->type != SWITCH_TYPE_NOVAL) &&\n\t\t\t\t(cvalue == NULL))\n\t\t\tprint_usage();\n\n\t\tif(cvlan > -1)\n\t\t\tcport = cvlan;\n\n\t\tretval = swlib_set_attr_string(dev, a, cport, cvalue);\n\t\tif (retval < 0)\n\t\t{\n\t\t\tnl_perror(-retval, \"Failed to set attribute\");\n\t\t\tgoto out;\n\t\t}\n\t\tbreak;\n\tcase CMD_GET:\n\t\tif(cvlan > -1)\n\t\t\tval.port_vlan = cvlan;\n\t\tif(cport > -1)\n\t\t\tval.port_vlan = cport;\n\t\tretval = swlib_get_attr(dev, a, &val);\n\t\tif (retval < 0)\n\t\t{\n\t\t\tnl_perror(-retval, \"Failed to get attribute\");\n\t\t\tgoto out;\n\t\t}\n\t\tprint_attr_val(a, &val);\n\t\tputchar('\\n');\n\t\tbreak;\n\tcase CMD_LOAD:\n\t\tswconfig_load_uci(dev, ckey);\n\t\tbreak;\n\tcase CMD_HELP:\n\t\tlist_attributes(dev);\n\t\tbreak;\n\tcase CMD_PORTMAP:\n\t\tswlib_print_portmap(dev, csegment);\n\t\tbreak;\n\tcase CMD_SHOW:\n\t\tif (cport >= 0 || cvlan >= 0) {\n\t\t\tif (cport >= 0)\n\t\t\t\tshow_port(dev, cport);\n\t\t\telse\n\t\t\t\tshow_vlan(dev, cvlan, false);\n\t\t} else {\n\t\t\tshow_global(dev);\n\t\t\tfor (i=0; i < dev->ports; i++)\n\t\t\t\tshow_port(dev, i);\n\t\t\tfor (i=0; i < dev->vlans; i++)\n\t\t\t\tshow_vlan(dev, i, true);\n\t\t}\n\t\tbreak;\n\t}\n\nout:\n\tswlib_free_all(dev);\n\treturn retval;\n}\n"
  },
  {
    "path": "package/network/config/swconfig/src/swlib.c",
    "content": "/*\n * swlib.c: Switch configuration API (user space part)\n *\n * Copyright (C) 2008 Felix Fietkau <nbd@nbd.name>\n *\n * This program is free software; you can redistribute it and/or\n * modify it under the terms of the GNU Lesser General Public License\n * version 2.1 as published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n * GNU General Public License for more details.\n */\n\n#include <stdio.h>\n#include <string.h>\n#include <stdlib.h>\n#include <ctype.h>\n#include <inttypes.h>\n#include <errno.h>\n#include <stdint.h>\n#include <getopt.h>\n#include <sys/types.h>\n#include <sys/socket.h>\n#include <linux/switch.h>\n#include \"swlib.h\"\n#include <netlink/netlink.h>\n#include <netlink/genl/genl.h>\n#include <netlink/genl/family.h>\n\n//#define DEBUG 1\n#ifdef DEBUG\n#define DPRINTF(fmt, ...) fprintf(stderr, \"%s(%d): \" fmt, __func__, __LINE__, ##__VA_ARGS__)\n#else\n#define DPRINTF(fmt, ...) do {} while (0)\n#endif\n\nstatic struct nl_sock *handle;\nstatic struct nl_cache *cache;\nstatic struct genl_family *family;\nstatic struct nlattr *tb[SWITCH_ATTR_MAX + 1];\nstatic int refcount = 0;\n\nstatic struct nla_policy port_policy[SWITCH_ATTR_MAX] = {\n\t[SWITCH_PORT_ID] = { .type = NLA_U32 },\n\t[SWITCH_PORT_FLAG_TAGGED] = { .type = NLA_FLAG },\n};\n\nstatic struct nla_policy portmap_policy[SWITCH_PORTMAP_MAX] = {\n\t[SWITCH_PORTMAP_SEGMENT] = { .type = NLA_STRING },\n\t[SWITCH_PORTMAP_VIRT] = { .type = NLA_U32 },\n};\n\nstatic struct nla_policy link_policy[SWITCH_LINK_ATTR_MAX] = {\n\t[SWITCH_LINK_FLAG_LINK] = { .type = NLA_FLAG },\n\t[SWITCH_LINK_FLAG_DUPLEX] = { .type = NLA_FLAG },\n\t[SWITCH_LINK_FLAG_ANEG] = { .type = NLA_FLAG },\n\t[SWITCH_LINK_SPEED] = { .type = NLA_U32 },\n\t[SWITCH_LINK_FLAG_EEE_100BASET] = { .type = NLA_FLAG },\n\t[SWITCH_LINK_FLAG_EEE_1000BASET] = { .type = NLA_FLAG },\n};\n\nstatic inline void *\nswlib_alloc(size_t size)\n{\n\tvoid *ptr;\n\n\tptr = malloc(size);\n\tif (!ptr)\n\t\tgoto done;\n\tmemset(ptr, 0, size);\n\ndone:\n\treturn ptr;\n}\n\nstatic int\nwait_handler(struct nl_msg *msg, void *arg)\n{\n\tint *finished = arg;\n\n\t*finished = 1;\n\treturn NL_STOP;\n}\n\n/* helper function for performing netlink requests */\nstatic int\nswlib_call(int cmd, int (*call)(struct nl_msg *, void *),\n\t\tint (*data)(struct nl_msg *, void *), void *arg)\n{\n\tstruct nl_msg *msg;\n\tstruct nl_cb *cb = NULL;\n\tint finished;\n\tint flags = 0;\n\tint err = 0;\n\n\tmsg = nlmsg_alloc();\n\tif (!msg) {\n\t\tfprintf(stderr, \"Out of memory!\\n\");\n\t\texit(1);\n\t}\n\n\tif (!data)\n\t\tflags |= NLM_F_DUMP;\n\n\tgenlmsg_put(msg, NL_AUTO_PID, NL_AUTO_SEQ, genl_family_get_id(family), 0, flags, cmd, 0);\n\tif (data) {\n\t\terr = data(msg, arg);\n\t\tif (err < 0)\n\t\t\tgoto nla_put_failure;\n\t}\n\n\tcb = nl_cb_alloc(NL_CB_CUSTOM);\n\tif (!cb) {\n\t\tfprintf(stderr, \"nl_cb_alloc failed.\\n\");\n\t\texit(1);\n\t}\n\n\terr = nl_send_auto_complete(handle, msg);\n\tif (err < 0) {\n\t\tfprintf(stderr, \"nl_send_auto_complete failed: %d\\n\", err);\n\t\tgoto out;\n\t}\n\n\tfinished = 0;\n\n\tif (call)\n\t\tnl_cb_set(cb, NL_CB_VALID, NL_CB_CUSTOM, call, arg);\n\n\tif (data)\n\t\tnl_cb_set(cb, NL_CB_ACK, NL_CB_CUSTOM, wait_handler, &finished);\n\telse\n\t\tnl_cb_set(cb, NL_CB_FINISH, NL_CB_CUSTOM, wait_handler, &finished);\n\n\terr = nl_recvmsgs(handle, cb);\n\tif (err < 0) {\n\t\tgoto out;\n\t}\n\n\tif (!finished)\n\t\terr = nl_wait_for_ack(handle);\n\nout:\n\tif (cb)\n\t\tnl_cb_put(cb);\nnla_put_failure:\n\tnlmsg_free(msg);\n\treturn err;\n}\n\nstatic int\nsend_attr(struct nl_msg *msg, void *arg)\n{\n\tstruct switch_val *val = arg;\n\tstruct switch_attr *attr = val->attr;\n\n\tNLA_PUT_U32(msg, SWITCH_ATTR_ID, attr->dev->id);\n\tNLA_PUT_U32(msg, SWITCH_ATTR_OP_ID, attr->id);\n\tswitch(attr->atype) {\n\tcase SWLIB_ATTR_GROUP_PORT:\n\t\tNLA_PUT_U32(msg, SWITCH_ATTR_OP_PORT, val->port_vlan);\n\t\tbreak;\n\tcase SWLIB_ATTR_GROUP_VLAN:\n\t\tNLA_PUT_U32(msg, SWITCH_ATTR_OP_VLAN, val->port_vlan);\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\n\treturn 0;\n\nnla_put_failure:\n\treturn -1;\n}\n\nstatic int\nstore_port_val(struct nl_msg *msg, struct nlattr *nla, struct switch_val *val)\n{\n\tstruct nlattr *p;\n\tint ports = val->attr->dev->ports;\n\tint err = 0;\n\tint remaining;\n\n\tif (!val->value.ports)\n\t\tval->value.ports = malloc(sizeof(struct switch_port) * ports);\n\n\tnla_for_each_nested(p, nla, remaining) {\n\t\tstruct nlattr *tb[SWITCH_PORT_ATTR_MAX+1];\n\t\tstruct switch_port *port;\n\n\t\tif (val->len >= ports)\n\t\t\tbreak;\n\n\t\terr = nla_parse_nested(tb, SWITCH_PORT_ATTR_MAX, p, port_policy);\n\t\tif (err < 0)\n\t\t\tgoto out;\n\n\t\tif (!tb[SWITCH_PORT_ID])\n\t\t\tcontinue;\n\n\t\tport = &val->value.ports[val->len];\n\t\tport->id = nla_get_u32(tb[SWITCH_PORT_ID]);\n\t\tport->flags = 0;\n\t\tif (tb[SWITCH_PORT_FLAG_TAGGED])\n\t\t\tport->flags |= SWLIB_PORT_FLAG_TAGGED;\n\n\t\tval->len++;\n\t}\n\nout:\n\treturn err;\n}\n\nstatic int\nstore_link_val(struct nl_msg *msg, struct nlattr *nla, struct switch_val *val)\n{\n\tstruct nlattr *tb[SWITCH_LINK_ATTR_MAX + 1];\n\tstruct switch_port_link *link;\n\tint err = 0;\n\n\tif (!val->value.link)\n\t\tval->value.link = malloc(sizeof(struct switch_port_link));\n\n\terr = nla_parse_nested(tb, SWITCH_LINK_ATTR_MAX, nla, link_policy);\n\tif (err < 0)\n\t\tgoto out;\n\n\tlink = val->value.link;\n\tlink->link = !!tb[SWITCH_LINK_FLAG_LINK];\n\tlink->duplex = !!tb[SWITCH_LINK_FLAG_DUPLEX];\n\tlink->aneg = !!tb[SWITCH_LINK_FLAG_ANEG];\n\tlink->tx_flow = !!tb[SWITCH_LINK_FLAG_TX_FLOW];\n\tlink->rx_flow = !!tb[SWITCH_LINK_FLAG_RX_FLOW];\n\tlink->speed = nla_get_u32(tb[SWITCH_LINK_SPEED]);\n\tlink->eee = 0;\n\tif (tb[SWITCH_LINK_FLAG_EEE_100BASET])\n\t\tlink->eee |= SWLIB_LINK_FLAG_EEE_100BASET;\n\tif (tb[SWITCH_LINK_FLAG_EEE_1000BASET])\n\t\tlink->eee |= SWLIB_LINK_FLAG_EEE_1000BASET;\n\nout:\n\treturn err;\n}\n\nstatic int\nstore_val(struct nl_msg *msg, void *arg)\n{\n\tstruct genlmsghdr *gnlh = nlmsg_data(nlmsg_hdr(msg));\n\tstruct switch_val *val = arg;\n\n\tif (!val)\n\t\tgoto error;\n\n\tif (nla_parse(tb, SWITCH_ATTR_MAX - 1, genlmsg_attrdata(gnlh, 0),\n\t\t\tgenlmsg_attrlen(gnlh, 0), NULL) < 0) {\n\t\tgoto error;\n\t}\n\n\tif (tb[SWITCH_ATTR_OP_VALUE_INT])\n\t\tval->value.i = nla_get_u32(tb[SWITCH_ATTR_OP_VALUE_INT]);\n\telse if (tb[SWITCH_ATTR_OP_VALUE_STR])\n\t\tval->value.s = strdup(nla_get_string(tb[SWITCH_ATTR_OP_VALUE_STR]));\n\telse if (tb[SWITCH_ATTR_OP_VALUE_PORTS])\n\t\tval->err = store_port_val(msg, tb[SWITCH_ATTR_OP_VALUE_PORTS], val);\n\telse if (tb[SWITCH_ATTR_OP_VALUE_LINK])\n\t\tval->err = store_link_val(msg, tb[SWITCH_ATTR_OP_VALUE_LINK], val);\n\n\tval->err = 0;\n\treturn 0;\n\nerror:\n\treturn NL_SKIP;\n}\n\nint\nswlib_get_attr(struct switch_dev *dev, struct switch_attr *attr, struct switch_val *val)\n{\n\tint cmd;\n\tint err;\n\n\tswitch(attr->atype) {\n\tcase SWLIB_ATTR_GROUP_GLOBAL:\n\t\tcmd = SWITCH_CMD_GET_GLOBAL;\n\t\tbreak;\n\tcase SWLIB_ATTR_GROUP_PORT:\n\t\tcmd = SWITCH_CMD_GET_PORT;\n\t\tbreak;\n\tcase SWLIB_ATTR_GROUP_VLAN:\n\t\tcmd = SWITCH_CMD_GET_VLAN;\n\t\tbreak;\n\tdefault:\n\t\treturn -EINVAL;\n\t}\n\n\tmemset(&val->value, 0, sizeof(val->value));\n\tval->len = 0;\n\tval->attr = attr;\n\tval->err = -EINVAL;\n\terr = swlib_call(cmd, store_val, send_attr, val);\n\tif (!err)\n\t\terr = val->err;\n\n\treturn err;\n}\n\nstatic int\nsend_attr_ports(struct nl_msg *msg, struct switch_val *val)\n{\n\tstruct nlattr *n;\n\tint i;\n\n\t/* TODO implement multipart? */\n\tif (val->len == 0)\n\t\tgoto done;\n\tn = nla_nest_start(msg, SWITCH_ATTR_OP_VALUE_PORTS);\n\tif (!n)\n\t\tgoto nla_put_failure;\n\tfor (i = 0; i < val->len; i++) {\n\t\tstruct switch_port *port = &val->value.ports[i];\n\t\tstruct nlattr *np;\n\n\t\tnp = nla_nest_start(msg, SWITCH_ATTR_PORT);\n\t\tif (!np)\n\t\t\tgoto nla_put_failure;\n\n\t\tNLA_PUT_U32(msg, SWITCH_PORT_ID, port->id);\n\t\tif (port->flags & SWLIB_PORT_FLAG_TAGGED)\n\t\t\tNLA_PUT_FLAG(msg, SWITCH_PORT_FLAG_TAGGED);\n\n\t\tnla_nest_end(msg, np);\n\t}\n\tnla_nest_end(msg, n);\ndone:\n\treturn 0;\n\nnla_put_failure:\n\treturn -1;\n}\n\nstatic int\nsend_attr_link(struct nl_msg *msg, struct switch_val *val)\n{\n\tstruct switch_port_link *link = val->value.link;\n\tstruct nlattr *n;\n\n\tn = nla_nest_start(msg, SWITCH_ATTR_OP_VALUE_LINK);\n\tif (!n)\n\t\tgoto nla_put_failure;\n\n\tif (link->duplex)\n\t\tNLA_PUT_FLAG(msg, SWITCH_LINK_FLAG_DUPLEX);\n\tif (link->aneg)\n\t\tNLA_PUT_FLAG(msg, SWITCH_LINK_FLAG_ANEG);\n\tNLA_PUT_U32(msg, SWITCH_LINK_SPEED, link->speed);\n\n\tnla_nest_end(msg, n);\n\n\treturn 0;\n\nnla_put_failure:\n\treturn -1;\n}\n\nstatic int\nsend_attr_val(struct nl_msg *msg, void *arg)\n{\n\tstruct switch_val *val = arg;\n\tstruct switch_attr *attr = val->attr;\n\n\tif (send_attr(msg, arg))\n\t\tgoto nla_put_failure;\n\n\tswitch(attr->type) {\n\tcase SWITCH_TYPE_NOVAL:\n\t\tbreak;\n\tcase SWITCH_TYPE_INT:\n\t\tNLA_PUT_U32(msg, SWITCH_ATTR_OP_VALUE_INT, val->value.i);\n\t\tbreak;\n\tcase SWITCH_TYPE_STRING:\n\t\tif (!val->value.s)\n\t\t\tgoto nla_put_failure;\n\t\tNLA_PUT_STRING(msg, SWITCH_ATTR_OP_VALUE_STR, val->value.s);\n\t\tbreak;\n\tcase SWITCH_TYPE_PORTS:\n\t\tif (send_attr_ports(msg, val) < 0)\n\t\t\tgoto nla_put_failure;\n\t\tbreak;\n\tcase SWITCH_TYPE_LINK:\n\t\tif (send_attr_link(msg, val))\n\t\t\tgoto nla_put_failure;\n\t\tbreak;\n\tdefault:\n\t\tgoto nla_put_failure;\n\t}\n\treturn 0;\n\nnla_put_failure:\n\treturn -1;\n}\n\nint\nswlib_set_attr(struct switch_dev *dev, struct switch_attr *attr, struct switch_val *val)\n{\n\tint cmd;\n\n\tswitch(attr->atype) {\n\tcase SWLIB_ATTR_GROUP_GLOBAL:\n\t\tcmd = SWITCH_CMD_SET_GLOBAL;\n\t\tbreak;\n\tcase SWLIB_ATTR_GROUP_PORT:\n\t\tcmd = SWITCH_CMD_SET_PORT;\n\t\tbreak;\n\tcase SWLIB_ATTR_GROUP_VLAN:\n\t\tcmd = SWITCH_CMD_SET_VLAN;\n\t\tbreak;\n\tdefault:\n\t\treturn -EINVAL;\n\t}\n\n\tval->attr = attr;\n\treturn swlib_call(cmd, NULL, send_attr_val, val);\n}\n\nenum {\n\tCMD_NONE,\n\tCMD_DUPLEX,\n\tCMD_ANEG,\n\tCMD_SPEED,\n};\n\nint swlib_set_attr_string(struct switch_dev *dev, struct switch_attr *a, int port_vlan, const char *str)\n{\n\tstruct switch_port *ports;\n\tstruct switch_port_link *link;\n\tstruct switch_val val;\n\tchar *ptr;\n\tint cmd = CMD_NONE;\n\n\tmemset(&val, 0, sizeof(val));\n\tval.port_vlan = port_vlan;\n\tswitch(a->type) {\n\tcase SWITCH_TYPE_INT:\n\t\tval.value.i = atoi(str);\n\t\tbreak;\n\tcase SWITCH_TYPE_STRING:\n\t\tval.value.s = (char *)str;\n\t\tbreak;\n\tcase SWITCH_TYPE_PORTS:\n\t\tports = alloca(sizeof(struct switch_port) * dev->ports);\n\t\tmemset(ports, 0, sizeof(struct switch_port) * dev->ports);\n\t\tval.len = 0;\n\t\tptr = (char *)str;\n\t\twhile(ptr && *ptr)\n\t\t{\n\t\t\twhile(*ptr && isspace(*ptr))\n\t\t\t\tptr++;\n\n\t\t\tif (!*ptr)\n\t\t\t\tbreak;\n\n\t\t\tif (!isdigit(*ptr))\n\t\t\t\treturn -1;\n\n\t\t\tif (val.len >= dev->ports)\n\t\t\t\treturn -1;\n\n\t\t\tports[val.len].flags = 0;\n\t\t\tports[val.len].id = strtoul(ptr, &ptr, 10);\n\t\t\twhile(*ptr && !isspace(*ptr)) {\n\t\t\t\tif (*ptr == 't')\n\t\t\t\t\tports[val.len].flags |= SWLIB_PORT_FLAG_TAGGED;\n\t\t\t\telse\n\t\t\t\t\treturn -1;\n\n\t\t\t\tptr++;\n\t\t\t}\n\t\t\tif (*ptr)\n\t\t\t\tptr++;\n\t\t\tval.len++;\n\t\t}\n\t\tval.value.ports = ports;\n\t\tbreak;\n\tcase SWITCH_TYPE_LINK:\n\t\tlink = malloc(sizeof(struct switch_port_link));\n\t\tmemset(link, 0, sizeof(struct switch_port_link));\n\t\tptr = (char *)str;\n\t\tfor (ptr = strtok(ptr,\" \"); ptr; ptr = strtok(NULL, \" \")) {\n\t\t\tswitch (cmd) {\n\t\t\tcase CMD_NONE:\n\t\t\t\tif (!strcmp(ptr, \"duplex\"))\n\t\t\t\t\tcmd = CMD_DUPLEX;\n\t\t\t\telse if (!strcmp(ptr, \"autoneg\"))\n\t\t\t\t\tcmd = CMD_ANEG;\n\t\t\t\telse if (!strcmp(ptr, \"speed\"))\n\t\t\t\t\tcmd = CMD_SPEED;\n\t\t\t\telse\n\t\t\t\t\tfprintf(stderr, \"Unsupported option %s\\n\", ptr);\n\t\t\t\tbreak;\n\t\t\tcase CMD_DUPLEX:\n\t\t\t\tif (!strcmp(ptr, \"half\"))\n\t\t\t\t\tlink->duplex = 0;\n\t\t\t\telse if (!strcmp(ptr, \"full\"))\n\t\t\t\t\tlink->duplex = 1;\n\t\t\t\telse\n\t\t\t\t\tfprintf(stderr, \"Unsupported value %s\\n\", ptr);\n\t\t\t\tcmd = CMD_NONE;\n\t\t\t\tbreak;\n\t\t\tcase CMD_ANEG:\n\t\t\t\tif (!strcmp(ptr, \"on\"))\n\t\t\t\t\tlink->aneg = 1;\n\t\t\t\telse if (!strcmp(ptr, \"off\"))\n\t\t\t\t\tlink->aneg = 0;\n\t\t\t\telse\n\t\t\t\t\tfprintf(stderr, \"Unsupported value %s\\n\", ptr);\n\t\t\t\tcmd = CMD_NONE;\n\t\t\t\tbreak;\n\t\t\tcase CMD_SPEED:\n\t\t\t\tlink->speed = atoi(ptr);\n\t\t\t\tcmd = CMD_NONE;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t\tval.value.link = link;\n\t\tbreak;\n\tcase SWITCH_TYPE_NOVAL:\n\t\tif (str && !strcmp(str, \"0\"))\n\t\t\treturn 0;\n\n\t\tbreak;\n\tdefault:\n\t\treturn -1;\n\t}\n\treturn swlib_set_attr(dev, a, &val);\n}\n\n\nstruct attrlist_arg {\n\tint id;\n\tint atype;\n\tstruct switch_dev *dev;\n\tstruct switch_attr *prev;\n\tstruct switch_attr **head;\n};\n\nstatic int\nadd_id(struct nl_msg *msg, void *arg)\n{\n\tstruct attrlist_arg *l = arg;\n\n\tNLA_PUT_U32(msg, SWITCH_ATTR_ID, l->id);\n\n\treturn 0;\nnla_put_failure:\n\treturn -1;\n}\n\nstatic int\nadd_attr(struct nl_msg *msg, void *ptr)\n{\n\tstruct genlmsghdr *gnlh = nlmsg_data(nlmsg_hdr(msg));\n\tstruct attrlist_arg *arg = ptr;\n\tstruct switch_attr *new;\n\n\tif (nla_parse(tb, SWITCH_ATTR_MAX - 1, genlmsg_attrdata(gnlh, 0),\n\t\t\tgenlmsg_attrlen(gnlh, 0), NULL) < 0)\n\t\tgoto done;\n\n\tnew = swlib_alloc(sizeof(struct switch_attr));\n\tif (!new)\n\t\tgoto done;\n\n\tnew->dev = arg->dev;\n\tnew->atype = arg->atype;\n\tif (arg->prev) {\n\t\targ->prev->next = new;\n\t} else {\n\t\targ->prev = *arg->head;\n\t}\n\t*arg->head = new;\n\targ->head = &new->next;\n\n\tif (tb[SWITCH_ATTR_OP_ID])\n\t\tnew->id = nla_get_u32(tb[SWITCH_ATTR_OP_ID]);\n\tif (tb[SWITCH_ATTR_OP_TYPE])\n\t\tnew->type = nla_get_u32(tb[SWITCH_ATTR_OP_TYPE]);\n\tif (tb[SWITCH_ATTR_OP_NAME])\n\t\tnew->name = strdup(nla_get_string(tb[SWITCH_ATTR_OP_NAME]));\n\tif (tb[SWITCH_ATTR_OP_DESCRIPTION])\n\t\tnew->description = strdup(nla_get_string(tb[SWITCH_ATTR_OP_DESCRIPTION]));\n\ndone:\n\treturn NL_SKIP;\n}\n\nint\nswlib_scan(struct switch_dev *dev)\n{\n\tstruct attrlist_arg arg;\n\n\tif (dev->ops || dev->port_ops || dev->vlan_ops)\n\t\treturn 0;\n\n\targ.atype = SWLIB_ATTR_GROUP_GLOBAL;\n\targ.dev = dev;\n\targ.id = dev->id;\n\targ.prev = NULL;\n\targ.head = &dev->ops;\n\tswlib_call(SWITCH_CMD_LIST_GLOBAL, add_attr, add_id, &arg);\n\n\targ.atype = SWLIB_ATTR_GROUP_PORT;\n\targ.prev = NULL;\n\targ.head = &dev->port_ops;\n\tswlib_call(SWITCH_CMD_LIST_PORT, add_attr, add_id, &arg);\n\n\targ.atype = SWLIB_ATTR_GROUP_VLAN;\n\targ.prev = NULL;\n\targ.head = &dev->vlan_ops;\n\tswlib_call(SWITCH_CMD_LIST_VLAN, add_attr, add_id, &arg);\n\n\treturn 0;\n}\n\nstruct switch_attr *swlib_lookup_attr(struct switch_dev *dev,\n\t\tenum swlib_attr_group atype, const char *name)\n{\n\tstruct switch_attr *head;\n\n\tif (!name || !dev)\n\t\treturn NULL;\n\n\tswitch(atype) {\n\tcase SWLIB_ATTR_GROUP_GLOBAL:\n\t\thead = dev->ops;\n\t\tbreak;\n\tcase SWLIB_ATTR_GROUP_PORT:\n\t\thead = dev->port_ops;\n\t\tbreak;\n\tcase SWLIB_ATTR_GROUP_VLAN:\n\t\thead = dev->vlan_ops;\n\t\tbreak;\n\t}\n\twhile(head) {\n\t\tif (!strcmp(name, head->name))\n\t\t\treturn head;\n\t\thead = head->next;\n\t}\n\n\treturn NULL;\n}\n\nstatic void\nswlib_priv_free(void)\n{\n\tif (family)\n\t\tnl_object_put((struct nl_object*)family);\n\tif (cache)\n\t\tnl_cache_free(cache);\n\tif (handle)\n\t\tnl_socket_free(handle);\n\tfamily = NULL;\n\thandle = NULL;\n\tcache = NULL;\n}\n\nstatic int\nswlib_priv_init(void)\n{\n\tint ret;\n\n\thandle = nl_socket_alloc();\n\tif (!handle) {\n\t\tDPRINTF(\"Failed to create handle\\n\");\n\t\tgoto err;\n\t}\n\n\tif (genl_connect(handle)) {\n\t\tDPRINTF(\"Failed to connect to generic netlink\\n\");\n\t\tgoto err;\n\t}\n\n\tret = genl_ctrl_alloc_cache(handle, &cache);\n\tif (ret < 0) {\n\t\tDPRINTF(\"Failed to allocate netlink cache\\n\");\n\t\tgoto err;\n\t}\n\n\tfamily = genl_ctrl_search_by_name(cache, \"switch\");\n\tif (!family) {\n\t\tDPRINTF(\"Switch API not present\\n\");\n\t\tgoto err;\n\t}\n\treturn 0;\n\nerr:\n\tswlib_priv_free();\n\treturn -EINVAL;\n}\n\nstruct swlib_scan_arg {\n\tconst char *name;\n\tstruct switch_dev *head;\n\tstruct switch_dev *ptr;\n};\n\nstatic int\nadd_port_map(struct switch_dev *dev, struct nlattr *nla)\n{\n\tstruct nlattr *p;\n\tint err = 0, idx = 0;\n\tint remaining;\n\n\tdev->maps = malloc(sizeof(struct switch_portmap) * dev->ports);\n\tif (!dev->maps)\n\t\treturn -1;\n\tmemset(dev->maps, 0, sizeof(struct switch_portmap) * dev->ports);\n\n\tnla_for_each_nested(p, nla, remaining) {\n\t\tstruct nlattr *tb[SWITCH_PORTMAP_MAX+1];\n\n\t\tif (idx >= dev->ports)\n\t\t\tcontinue;\n\n\t\terr = nla_parse_nested(tb, SWITCH_PORTMAP_MAX, p, portmap_policy);\n\t\tif (err < 0)\n\t\t\tcontinue;\n\n\n\t\tif (tb[SWITCH_PORTMAP_SEGMENT] && tb[SWITCH_PORTMAP_VIRT]) {\n\t\t\tdev->maps[idx].segment = strdup(nla_get_string(tb[SWITCH_PORTMAP_SEGMENT]));\n\t\t\tdev->maps[idx].virt = nla_get_u32(tb[SWITCH_PORTMAP_VIRT]);\n\t\t}\n\t\tidx++;\n\t}\n\nout:\n\treturn err;\n}\n\n\nstatic int\nadd_switch(struct nl_msg *msg, void *arg)\n{\n\tstruct swlib_scan_arg *sa = arg;\n\tstruct genlmsghdr *gnlh = nlmsg_data(nlmsg_hdr(msg));\n\tstruct switch_dev *dev;\n\tconst char *name;\n\tconst char *alias;\n\n\tif (nla_parse(tb, SWITCH_ATTR_MAX, genlmsg_attrdata(gnlh, 0), genlmsg_attrlen(gnlh, 0), NULL) < 0)\n\t\tgoto done;\n\n\tif (!tb[SWITCH_ATTR_DEV_NAME])\n\t\tgoto done;\n\n\tname = nla_get_string(tb[SWITCH_ATTR_DEV_NAME]);\n\talias = nla_get_string(tb[SWITCH_ATTR_ALIAS]);\n\n\tif (sa->name && (strcmp(name, sa->name) != 0) && (strcmp(alias, sa->name) != 0))\n\t\tgoto done;\n\n\tdev = swlib_alloc(sizeof(struct switch_dev));\n\tif (!dev)\n\t\tgoto done;\n\n\tstrncpy(dev->dev_name, name, IFNAMSIZ - 1);\n\tdev->alias = strdup(alias);\n\tif (tb[SWITCH_ATTR_ID])\n\t\tdev->id = nla_get_u32(tb[SWITCH_ATTR_ID]);\n\tif (tb[SWITCH_ATTR_NAME])\n\t\tdev->name = strdup(nla_get_string(tb[SWITCH_ATTR_NAME]));\n\tif (tb[SWITCH_ATTR_PORTS])\n\t\tdev->ports = nla_get_u32(tb[SWITCH_ATTR_PORTS]);\n\tif (tb[SWITCH_ATTR_VLANS])\n\t\tdev->vlans = nla_get_u32(tb[SWITCH_ATTR_VLANS]);\n\tif (tb[SWITCH_ATTR_CPU_PORT])\n\t\tdev->cpu_port = nla_get_u32(tb[SWITCH_ATTR_CPU_PORT]);\n\tif (tb[SWITCH_ATTR_PORTMAP])\n\t\tadd_port_map(dev, tb[SWITCH_ATTR_PORTMAP]);\n\n\tif (!sa->head) {\n\t\tsa->head = dev;\n\t\tsa->ptr = dev;\n\t} else {\n\t\tsa->ptr->next = dev;\n\t\tsa->ptr = dev;\n\t}\n\n\trefcount++;\ndone:\n\treturn NL_SKIP;\n}\n\nstatic int\nlist_switch(struct nl_msg *msg, void *arg)\n{\n\tstruct genlmsghdr *gnlh = nlmsg_data(nlmsg_hdr(msg));\n\n\tif (nla_parse(tb, SWITCH_ATTR_MAX, genlmsg_attrdata(gnlh, 0), genlmsg_attrlen(gnlh, 0), NULL) < 0)\n\t\tgoto done;\n\n\tif (!tb[SWITCH_ATTR_DEV_NAME] || !tb[SWITCH_ATTR_NAME])\n\t\tgoto done;\n\n\tprintf(\"Found: %s - %s\\n\", nla_get_string(tb[SWITCH_ATTR_DEV_NAME]),\n\t\tnla_get_string(tb[SWITCH_ATTR_ALIAS]));\n\ndone:\n\treturn NL_SKIP;\n}\n\nvoid\nswlib_list(void)\n{\n\tif (swlib_priv_init() < 0)\n\t\treturn;\n\tswlib_call(SWITCH_CMD_GET_SWITCH, list_switch, NULL, NULL);\n\tswlib_priv_free();\n}\n\nvoid\nswlib_print_portmap(struct switch_dev *dev, char *segment)\n{\n\tint i;\n\n\tif (segment) {\n\t\tif (!strcmp(segment, \"cpu\")) {\n\t\t\tprintf(\"%d \", dev->cpu_port);\n\t\t} else if (!strcmp(segment, \"disabled\")) {\n\t\t\tfor (i = 0; i < dev->ports; i++)\n\t\t\t\tif (!dev->maps[i].segment)\n\t\t\t\t\tprintf(\"%d \", i);\n\t\t} else for (i = 0; i < dev->ports; i++) {\n\t\t\tif (dev->maps[i].segment && !strcmp(dev->maps[i].segment, segment))\n\t\t\t\tprintf(\"%d \", i);\n\t\t}\n\t} else {\n\t\tprintf(\"%s - %s\\n\", dev->dev_name, dev->name);\n\t\tfor (i = 0; i < dev->ports; i++)\n\t\t\tif (i == dev->cpu_port)\n\t\t\t\tprintf(\"port%d:\\tcpu\\n\", i);\n\t\t\telse if (dev->maps[i].segment)\n\t\t\t\tprintf(\"port%d:\\t%s.%d\\n\", i, dev->maps[i].segment, dev->maps[i].virt);\n\t\t\telse\n\t\t\t\tprintf(\"port%d:\\tdisabled\\n\", i);\n\t}\n}\n\nstruct switch_dev *\nswlib_connect(const char *name)\n{\n\tstruct swlib_scan_arg arg;\n\n\tif (!refcount) {\n\t\tif (swlib_priv_init() < 0)\n\t\t\treturn NULL;\n\t};\n\n\targ.head = NULL;\n\targ.ptr = NULL;\n\targ.name = name;\n\tswlib_call(SWITCH_CMD_GET_SWITCH, add_switch, NULL, &arg);\n\n\tif (!refcount)\n\t\tswlib_priv_free();\n\n\treturn arg.head;\n}\n\nstatic void\nswlib_free_attributes(struct switch_attr **head)\n{\n\tstruct switch_attr *a = *head;\n\tstruct switch_attr *next;\n\n\twhile (a) {\n\t\tnext = a->next;\n\t\tfree(a->name);\n\t\tfree(a->description);\n\t\tfree(a);\n\t\ta = next;\n\t}\n\t*head = NULL;\n}\n\nstatic void\nswlib_free_port_map(struct switch_dev *dev)\n{\n\tint i;\n\n\tif (!dev || !dev->maps)\n\t\treturn;\n\n\tfor (i = 0; i < dev->ports; i++)\n\t\tfree(dev->maps[i].segment);\n\tfree(dev->maps);\n}\n\nvoid\nswlib_free(struct switch_dev *dev)\n{\n\tswlib_free_attributes(&dev->ops);\n\tswlib_free_attributes(&dev->port_ops);\n\tswlib_free_attributes(&dev->vlan_ops);\n\tswlib_free_port_map(dev);\n\tfree(dev->name);\n\tfree(dev->alias);\n\tfree(dev);\n\n\tif (--refcount == 0)\n\t\tswlib_priv_free();\n}\n\nvoid\nswlib_free_all(struct switch_dev *dev)\n{\n\tstruct switch_dev *p;\n\n\twhile (dev) {\n\t\tp = dev->next;\n\t\tswlib_free(dev);\n\t\tdev = p;\n\t}\n}\n"
  },
  {
    "path": "package/network/config/swconfig/src/swlib.h",
    "content": "/*\n * swlib.h: Switch configuration API (user space part)\n *\n * Copyright (C) 2008-2009 Felix Fietkau <nbd@nbd.name>\n *\n * This program is free software; you can redistribute it and/or\n * modify it under the terms of the GNU Lesser General Public License\n * version 2.1 as published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n * GNU General Public License for more details.\n *\n\nUsage of the library functions:\n\n  The main datastructure for a switch is the struct switch_device\n  To get started, you first need to use switch_connect() to probe\n  for switches and allocate an instance of this struct.\n\n  There are two possible usage modes:\n    dev = switch_connect(\"eth0\");\n      - this call will look for a switch registered for the linux device\n  \t  \"eth0\" and only allocate a switch_device for this particular switch.\n\n    dev = switch_connect(NULL)\n      - this will return one switch_device struct for each available\n  \t  switch. The switch_device structs are chained with by ->next pointer\n\n  Then to query a switch for all available attributes, use:\n    swlib_scan(dev);\n\n  All allocated datastructures for the switch_device struct can be freed with\n    swlib_free(dev);\n  or\n    swlib_free_all(dev);\n\n  The latter traverses a whole chain of switch_device structs and frees them all\n\n  Switch attributes (struct switch_attr) are divided into three groups:\n    dev->ops:\n      - global settings\n    dev->port_ops:\n      - per-port settings\n    dev->vlan_ops:\n      - per-vlan settings\n\n  switch_lookup_attr() is a small helper function to locate attributes\n  by name.\n\n  switch_set_attr() and switch_get_attr() can alter or request the values\n  of attributes.\n\nUsage of the switch_attr struct:\n\n  ->atype: attribute group, one of:\n    - SWLIB_ATTR_GROUP_GLOBAL\n    - SWLIB_ATTR_GROUP_VLAN\n    - SWLIB_ATTR_GROUP_PORT\n\n  ->id: identifier for the attribute\n\n  ->type: data type, one of:\n    - SWITCH_TYPE_INT\n    - SWITCH_TYPE_STRING\n    - SWITCH_TYPE_PORT\n\n  ->name: short name of the attribute\n  ->description: longer description\n  ->next: pointer to the next attribute of the current group\n\n\nUsage of the switch_val struct:\n\n  When setting attributes, following members of the struct switch_val need\n  to be set up:\n\n    ->len (for attr->type == SWITCH_TYPE_PORT)\n    ->port_vlan:\n      - port number (for attr->atype == SWLIB_ATTR_GROUP_PORT), or:\n      - vlan number (for attr->atype == SWLIB_ATTR_GROUP_VLAN)\n    ->value.i (for attr->type == SWITCH_TYPE_INT)\n    ->value.s (for attr->type == SWITCH_TYPE_STRING)\n      - owned by the caller, not stored in the library internally\n    ->value.ports (for attr->type == SWITCH_TYPE_PORT)\n      - must point to an array of at lest val->len * sizeof(struct switch_port)\n\n  When getting string attributes, val->value.s must be freed by the caller\n  When getting port list attributes, an internal static buffer is used,\n  which changes from call to call.\n\n */\n\n#ifndef __SWLIB_H\n#define __SWLIB_H\n\nenum swlib_attr_group {\n\tSWLIB_ATTR_GROUP_GLOBAL,\n\tSWLIB_ATTR_GROUP_VLAN,\n\tSWLIB_ATTR_GROUP_PORT,\n};\n\nenum swlib_port_flags {\n\tSWLIB_PORT_FLAG_TAGGED = (1 << 0),\n};\n\nenum swlib_link_flags {\n\tSWLIB_LINK_FLAG_EEE_100BASET = (1 << 0),\n\tSWLIB_LINK_FLAG_EEE_1000BASET = (1 << 1),\n};\n\nstruct switch_dev;\nstruct switch_attr;\nstruct switch_port;\nstruct switch_port_map;\nstruct switch_port_link;\nstruct switch_val;\nstruct uci_package;\n\nstruct switch_dev {\n\tint id;\n\tchar dev_name[IFNAMSIZ];\n\tchar *name;\n\tchar *alias;\n\tint ports;\n\tint vlans;\n\tint cpu_port;\n\tstruct switch_attr *ops;\n\tstruct switch_attr *port_ops;\n\tstruct switch_attr *vlan_ops;\n\tstruct switch_portmap *maps;\n\tstruct switch_dev *next;\n\tvoid *priv;\n};\n\nstruct switch_val {\n\tstruct switch_attr *attr;\n\tint len;\n\tint err;\n\tint port_vlan;\n\tunion {\n\t\tchar *s;\n\t\tint i;\n\t\tstruct switch_port *ports;\n\t\tstruct switch_port_link *link;\n\t} value;\n};\n\nstruct switch_attr {\n\tstruct switch_dev *dev;\n\tint atype;\n\tint id;\n\tint type;\n\tchar *name;\n\tchar *description;\n\tstruct switch_attr *next;\n};\n\nstruct switch_port {\n\tunsigned int id;\n\tunsigned int flags;\n};\n\nstruct switch_portmap {\n\tunsigned int virt;\n\tchar *segment;\n};\n\nstruct switch_port_link {\n\tint link:1;\n\tint duplex:1;\n\tint aneg:1;\n\tint tx_flow:1;\n\tint rx_flow:1;\n\tint speed;\n\t/* in ethtool adv_t format */\n\tuint32_t eee;\n};\n\n/**\n * swlib_list: list all switches\n */\nvoid swlib_list(void);\n\n/**\n * swlib_print_portmap: get portmap\n * @dev: switch device struct\n */\nvoid swlib_print_portmap(struct switch_dev *dev, char *segment);\n\n/**\n * swlib_connect: connect to the switch through netlink\n * @name: name of the ethernet interface,\n *\n * if name is NULL, it connect and builds a chain of all switches\n */\nstruct switch_dev *swlib_connect(const char *name);\n\n/**\n * swlib_free: free all dynamically allocated data for the switch connection\n * @dev: switch device struct\n *\n * all members of a switch device chain (generated by swlib_connect(NULL))\n * must be freed individually\n */\nvoid swlib_free(struct switch_dev *dev);\n\n/**\n * swlib_free_all: run swlib_free on all devices in the chain\n * @dev: switch device struct\n */\nvoid swlib_free_all(struct switch_dev *dev);\n\n/**\n * swlib_scan: probe the switch driver for available commands/attributes\n * @dev: switch device struct\n */\nint swlib_scan(struct switch_dev *dev);\n\n/**\n * swlib_lookup_attr: look up a switch attribute\n * @dev: switch device struct\n * @type: global, port or vlan\n * @name: name of the attribute\n */\nstruct switch_attr *swlib_lookup_attr(struct switch_dev *dev,\n\t\tenum swlib_attr_group atype, const char *name);\n\n/**\n * swlib_set_attr: set the value for an attribute\n * @dev: switch device struct\n * @attr: switch attribute struct\n * @val: attribute value pointer\n * returns 0 on success\n */\nint swlib_set_attr(struct switch_dev *dev, struct switch_attr *attr,\n\t\tstruct switch_val *val);\n\n/**\n * swlib_set_attr_string: set the value for an attribute with type conversion\n * @dev: switch device struct\n * @attr: switch attribute struct\n * @port_vlan: port or vlan (if applicable)\n * @str: string value\n * returns 0 on success\n */\nint swlib_set_attr_string(struct switch_dev *dev, struct switch_attr *attr,\n\t\tint port_vlan, const char *str);\n\n/**\n * swlib_get_attr: get the value for an attribute\n * @dev: switch device struct\n * @attr: switch attribute struct\n * @val: attribute value pointer\n * returns 0 on success\n * for string attributes, the result string must be freed by the caller\n */\nint swlib_get_attr(struct switch_dev *dev, struct switch_attr *attr,\n\t\tstruct switch_val *val);\n\n/**\n * swlib_apply_from_uci: set up the switch from a uci configuration\n * @dev: switch device struct\n * @p: uci package which contains the desired global config\n */\nint swlib_apply_from_uci(struct switch_dev *dev, struct uci_package *p);\n\n#endif\n"
  },
  {
    "path": "package/network/config/swconfig/src/uci.c",
    "content": "/*\n * uci.c: UCI binding for the switch configuration utility\n *\n * Copyright (C) 2009 Felix Fietkau <nbd@nbd.name>\n *\n * This program is free software; you can redistribute it and/or\n * modify it under the terms of the GNU General Public License\n * version 2 as published by the Free Software Foundatio.\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n * GNU General Public License for more details.\n */\n\n#include <stdio.h>\n#include <string.h>\n#include <stdlib.h>\n#include <inttypes.h>\n#include <errno.h>\n#include <stdint.h>\n#include <getopt.h>\n#include <sys/types.h>\n#include <sys/socket.h>\n#include <uci.h>\n\n#include <linux/types.h>\n#include <linux/netlink.h>\n#include <linux/genetlink.h>\n#include <netlink/netlink.h>\n#include <netlink/genl/genl.h>\n#include <netlink/genl/ctrl.h>\n#include <linux/switch.h>\n#include \"swlib.h\"\n\n#ifndef ARRAY_SIZE\n#define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0]))\n#endif\n\nstruct swlib_setting {\n\tstruct switch_attr *attr;\n\tconst char *name;\n\tint port_vlan;\n\tconst char *val;\n\tstruct swlib_setting *next;\n};\n\nstruct swlib_setting early_settings[] = {\n\t{ .name = \"reset\", .val = \"1\" },\n\t{ .name = \"enable_vlan\", .val = \"1\" },\n};\n\nstatic struct swlib_setting *settings;\nstatic struct swlib_setting **head;\n\nstatic bool swlib_match_name(struct switch_dev *dev, const char *name)\n{\n\treturn (strcmp(name, dev->dev_name) == 0 ||\n\t\tstrcmp(name, dev->alias) == 0);\n}\n\nstatic void\nswlib_map_settings(struct switch_dev *dev, int type, int port_vlan, struct uci_section *s)\n{\n\tstruct swlib_setting *setting;\n\tstruct switch_attr *attr;\n\tstruct uci_element *e;\n\tstruct uci_option *o;\n\n\tuci_foreach_element(&s->options, e) {\n\t\to = uci_to_option(e);\n\n\t\tif (o->type != UCI_TYPE_STRING)\n\t\t\tcontinue;\n\n\t\tif (!strcmp(e->name, \"device\"))\n\t\t\tcontinue;\n\n\t\t/* map early settings */\n\t\tif (type == SWLIB_ATTR_GROUP_GLOBAL) {\n\t\t\tint i;\n\n\t\t\tfor (i = 0; i < ARRAY_SIZE(early_settings); i++) {\n\t\t\t\tif (strcmp(e->name, early_settings[i].name) != 0)\n\t\t\t\t\tcontinue;\n\n\t\t\t\tearly_settings[i].val = o->v.string;\n\t\t\t\tgoto skip;\n\t\t\t}\n\t\t}\n\n\t\tattr = swlib_lookup_attr(dev, type, e->name);\n\t\tif (!attr)\n\t\t\tcontinue;\n\n\t\tsetting = malloc(sizeof(struct swlib_setting));\n\t\tmemset(setting, 0, sizeof(struct swlib_setting));\n\t\tsetting->attr = attr;\n\t\tsetting->port_vlan = port_vlan;\n\t\tsetting->val = o->v.string;\n\t\t*head = setting;\n\t\thead = &setting->next;\nskip:\n\t\tcontinue;\n\t}\n}\n\nint swlib_apply_from_uci(struct switch_dev *dev, struct uci_package *p)\n{\n\tstruct switch_attr *attr;\n\tstruct uci_element *e;\n\tstruct uci_section *s;\n\tstruct uci_option *o;\n\tstruct uci_ptr ptr;\n\tstruct switch_val val;\n\tint i;\n\n\tsettings = NULL;\n\thead = &settings;\n\n\tuci_foreach_element(&p->sections, e) {\n\t\tstruct uci_element *n;\n\n\t\ts = uci_to_section(e);\n\n\t\tif (strcmp(s->type, \"switch\") != 0)\n\t\t\tcontinue;\n\n\t\tuci_foreach_element(&s->options, n) {\n\t\t\tstruct uci_option *o = uci_to_option(n);\n\n\t\t\tif (strcmp(n->name, \"name\") != 0)\n\t\t\t\tcontinue;\n\n\t\t\tif (o->type != UCI_TYPE_STRING)\n\t\t\t\tcontinue;\n\n\t\t\tif (swlib_match_name(dev, o->v.string))\n\t\t\t\tgoto found;\n\n\t\t\tbreak;\n\t\t}\n\n\t\tif (!swlib_match_name(dev, e->name))\n\t\t\tcontinue;\n\n\t\tgoto found;\n\t}\n\n\t/* not found */\n\treturn -1;\n\nfound:\n\t/* look up available early options, which need to be taken care\n\t * of in the correct order */\n\tfor (i = 0; i < ARRAY_SIZE(early_settings); i++) {\n\t\tearly_settings[i].attr = swlib_lookup_attr(dev,\n\t\t\tSWLIB_ATTR_GROUP_GLOBAL, early_settings[i].name);\n\t}\n\tswlib_map_settings(dev, SWLIB_ATTR_GROUP_GLOBAL, 0, s);\n\n\t/* look for port or vlan sections */\n\tuci_foreach_element(&p->sections, e) {\n\t\tstruct uci_element *os;\n\t\ts = uci_to_section(e);\n\n\t\tif (!strcmp(s->type, \"switch_port\")) {\n\t\t\tchar *devn = NULL, *port = NULL, *port_err = NULL;\n\t\t\tint port_n;\n\n\t\t\tuci_foreach_element(&s->options, os) {\n\t\t\t\to = uci_to_option(os);\n\t\t\t\tif (o->type != UCI_TYPE_STRING)\n\t\t\t\t\tcontinue;\n\n\t\t\t\tif (!strcmp(os->name, \"device\")) {\n\t\t\t\t\tdevn = o->v.string;\n\t\t\t\t\tif (!swlib_match_name(dev, devn))\n\t\t\t\t\t\tdevn = NULL;\n\t\t\t\t} else if (!strcmp(os->name, \"port\")) {\n\t\t\t\t\tport = o->v.string;\n\t\t\t\t}\n\t\t\t}\n\t\t\tif (!devn || !port || !port[0])\n\t\t\t\tcontinue;\n\n\t\t\tport_n = strtoul(port, &port_err, 0);\n\t\t\tif (port_err && port_err[0])\n\t\t\t\tcontinue;\n\n\t\t\tswlib_map_settings(dev, SWLIB_ATTR_GROUP_PORT, port_n, s);\n\t\t} else if (!strcmp(s->type, \"switch_vlan\")) {\n\t\t\tchar *devn = NULL, *vlan = NULL, *vlan_err = NULL;\n\t\t\tint vlan_n;\n\n\t\t\tuci_foreach_element(&s->options, os) {\n\t\t\t\to = uci_to_option(os);\n\t\t\t\tif (o->type != UCI_TYPE_STRING)\n\t\t\t\t\tcontinue;\n\n\t\t\t\tif (!strcmp(os->name, \"device\")) {\n\t\t\t\t\tdevn = o->v.string;\n\t\t\t\t\tif (!swlib_match_name(dev, devn))\n\t\t\t\t\t\tdevn = NULL;\n\t\t\t\t} else if (!strcmp(os->name, \"vlan\")) {\n\t\t\t\t\tvlan = o->v.string;\n\t\t\t\t}\n\t\t\t}\n\t\t\tif (!devn || !vlan || !vlan[0])\n\t\t\t\tcontinue;\n\n\t\t\tvlan_n = strtoul(vlan, &vlan_err, 0);\n\t\t\tif (vlan_err && vlan_err[0])\n\t\t\t\tcontinue;\n\n\t\t\tswlib_map_settings(dev, SWLIB_ATTR_GROUP_VLAN, vlan_n, s);\n\t\t}\n\t}\n\n\tfor (i = 0; i < ARRAY_SIZE(early_settings); i++) {\n\t\tstruct swlib_setting *st = &early_settings[i];\n\t\tif (!st->attr || !st->val)\n\t\t\tcontinue;\n\t\tswlib_set_attr_string(dev, st->attr, st->port_vlan, st->val);\n\n\t}\n\n\twhile (settings) {\n\t\tstruct swlib_setting *st = settings;\n\n\t\tswlib_set_attr_string(dev, st->attr, st->port_vlan, st->val);\n\t\tst = st->next;\n\t\tfree(settings);\n\t\tsettings = st;\n\t}\n\n\t/* Apply the config */\n\tattr = swlib_lookup_attr(dev, SWLIB_ATTR_GROUP_GLOBAL, \"apply\");\n\tif (!attr)\n\t\treturn 0;\n\n\tmemset(&val, 0, sizeof(val));\n\tswlib_set_attr(dev, attr, &val);\n\n\treturn 0;\n}\n"
  },
  {
    "path": "package/network/config/vti/Makefile",
    "content": "#\n# Copyright (C) 2014 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=vti\nPKG_RELEASE:=5\nPKG_LICENSE:=GPL-2.0\n\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine Package/vti/Default\nendef\n\ndefine Package/vti\n  SECTION:=net\n  CATEGORY:=Network\n  MAINTAINER:=Andre Valentin <avalentin@marcant.net>\n  TITLE:=Virtual IPsec Tunnel Interface config support\n  DEPENDS:=+kmod-ip-vti +IPV6:kmod-ip6-vti\n  PROVIDES:=vtiv4 vtiv6\n  PKGARCH:=all\nendef\n\ndefine Package/vti/description\n Virtual IPsec Tunnel Interface config support (IPv4 and IPv6) in /etc/config/network.\nendef\n\ndefine Build/Compile\nendef\n\ndefine Build/Configure\nendef\n\ndefine Package/vti/install\n\t$(INSTALL_DIR) $(1)/lib/netifd/proto\n\t$(INSTALL_BIN) ./files/vti.sh $(1)/lib/netifd/proto/vti.sh\nendef\n\n$(eval $(call BuildPackage,vti))\n"
  },
  {
    "path": "package/network/config/vti/files/vti.sh",
    "content": "#!/bin/sh\n\n[ -n \"$INCLUDE_ONLY\" ] || {\n\t. /lib/functions.sh\n\t. /lib/functions/network.sh\n\t. ../netifd-proto.sh\n\tinit_proto \"$@\"\n}\n\nvti_generic_setup() {\n\tlocal cfg=\"$1\"\n\tlocal mode=\"$2\"\n\tlocal local=\"$3\"\n\tlocal remote=\"$4\"\n\tlocal link=\"$5\"\n\tlocal mtu zone ikey\n\tjson_get_vars mtu zone ikey okey\n\n\tproto_init_update \"$link\" 1\n\n\tproto_add_tunnel\n\tjson_add_string mode \"$mode\"\n\tjson_add_int mtu \"${mtu:-1280}\"\n\tjson_add_string local \"$local\"\n\tjson_add_string remote \"$remote\"\n\t[ -n \"$tunlink\" ] && json_add_string link \"$tunlink\"\n\n\tjson_add_object 'data'\n\t[ -n \"$ikey\" ] && json_add_int ikey \"$ikey\"\n\t[ -n \"$okey\" ] && json_add_int okey \"$okey\"\n\tjson_close_object\n\n\tproto_close_tunnel\n\n\tproto_add_data\n\t[ -n \"$zone\" ] && json_add_string zone \"$zone\"\n\tproto_close_data\n\n\tproto_send_update \"$cfg\"\n}\n\nvti_setup() {\n\tlocal cfg=\"$1\"\n\tlocal mode=\"$2\"\n\n\tlocal ipaddr peeraddr\n\tjson_get_vars df ipaddr peeraddr tunlink\n\n\t[ -z \"$peeraddr\" ] && {\n\t\tproto_notify_error \"$cfg\" \"MISSING_ADDRESS\"\n\t\tproto_block_restart \"$cfg\"\n\t\texit\n\t}\n\n\t( proto_add_host_dependency \"$cfg\" \"$peeraddr\" \"$tunlink\" )\n\n\t[ -z \"$ipaddr\" ] && {\n\t\tlocal wanif=\"$tunlink\"\n\t\tif [ -z $wanif ] && ! network_find_wan wanif; then\n\t\t\tproto_notify_error \"$cfg\" \"NO_WAN_LINK\"\n\t\t\texit\n\t\tfi\n\n\t\tif ! network_get_ipaddr ipaddr \"$wanif\"; then\n\t\t\tproto_notify_error \"$cfg\" \"NO_WAN_LINK\"\n\t\t\texit\n\t\tfi\n\t}\n\n\tvti_generic_setup $cfg $mode $ipaddr $peeraddr \"vti-$cfg\"\n}\n\nproto_vti_setup() {\n\tlocal cfg=\"$1\"\n\n\tvti_setup $cfg \"vtiip\"\n}\n\nvti6_setup() {\n\tlocal cfg=\"$1\"\n\tlocal mode=\"$2\"\n\n\tlocal ip6addr peer6addr weakif\n\tjson_get_vars ip6addr peer6addr tunlink weakif\n\n\t[ -z \"$peer6addr\" ] && {\n\t\tproto_notify_error \"$cfg\" \"MISSING_ADDRESS\"\n\t\tproto_block_restart \"$cfg\"\n\t\texit\n\t}\n\n\t( proto_add_host_dependency \"$cfg\" \"$peer6addr\" \"$tunlink\" )\n\n\t[ -z \"$ip6addr\" ] && {\n\t\tlocal wanif=\"$tunlink\"\n\t\tif [ -z $wanif ] && ! network_find_wan6 wanif; then\n\t\t\tproto_notify_error \"$cfg\" \"NO_WAN_LINK\"\n\t\t\texit\n\t\tfi\n\n\t\tif ! network_get_ipaddr6 ip6addr \"$wanif\"; then\n\t\t\t[ -z \"$weakif\" ] && weakif=\"lan\"\n\t\t\tif ! network_get_ipaddr6 ip6addr \"$weakif\"; then\n\t\t\t\tproto_notify_error \"$cfg\" \"NO_WAN_LINK\"\n\t\t\t\texit\n\t\t\tfi\n\t\tfi\n\t}\n\n\tvti_generic_setup $cfg $mode $ip6addr $peer6addr \"vti6-$cfg\"\n}\n\nproto_vti6_setup() {\n\tlocal cfg=\"$1\"\n\n\tvti6_setup $cfg \"vtiip6\"\n}\n\nproto_vti_teardown() {\n\tlocal cfg=\"$1\"\n}\n\nproto_vti6_teardown() {\n\tlocal cfg=\"$1\"\n}\n\nvti_generic_init_config() {\n\tno_device=1\n\tavailable=1\n\n\tproto_config_add_int \"mtu\"\n\tproto_config_add_string \"tunlink\"\n\tproto_config_add_string \"zone\"\n\tproto_config_add_int \"ikey\"\n\tproto_config_add_int \"okey\"\n}\n\nproto_vti_init_config() {\n\tvti_generic_init_config\n\tproto_config_add_string \"ipaddr\"\n\tproto_config_add_string \"peeraddr\"\n}\n\nproto_vti6_init_config() {\n\tvti_generic_init_config\n\tproto_config_add_string \"ip6addr\"\n\tproto_config_add_string \"peer6addr\"\n\tproto_config_add_string \"weakif\"\n}\n\n[ -n \"$INCLUDE_ONLY\" ] || {\n\t[ -d /sys/module/ip_vti ] && add_protocol vti\n\t[ -d /sys/module/ip6_vti ] && add_protocol vti6\n}\n"
  },
  {
    "path": "package/network/config/vxlan/Makefile",
    "content": "include $(TOPDIR)/rules.mk\n\nPKG_NAME:=vxlan\nPKG_RELEASE:=7\nPKG_LICENSE:=GPL-2.0\n\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine Package/vxlan\n  SECTION:=net\n  CATEGORY:=Network\n  MAINTAINER:=Matthias Schiffer <mschiffer@universe-factory.net>\n  TITLE:=Virtual eXtensible LAN config support\n  DEPENDS:=+kmod-vxlan\n  PKGARCH:=all\nendef\n\ndefine Package/vxlan/description\n Virtual eXtensible LAN config support in /etc/config/network.\nendef\n\ndefine Build/Compile\nendef\n\ndefine Build/Configure\nendef\n\ndefine Package/vxlan/install\n\t$(INSTALL_DIR) $(1)/lib/netifd/proto\n\t$(INSTALL_BIN) ./files/vxlan.sh $(1)/lib/netifd/proto/vxlan.sh\nendef\n\n$(eval $(call BuildPackage,vxlan))\n"
  },
  {
    "path": "package/network/config/vxlan/files/vxlan.sh",
    "content": "#!/bin/sh\n\n[ -n \"$INCLUDE_ONLY\" ] || {\n\t. /lib/functions.sh\n\t. /lib/functions/network.sh\n\t. ../netifd-proto.sh\n\tinit_proto \"$@\"\n}\n\nproto_vxlan_setup_peer() {\n\ttype bridge &> /dev/null || {\n\t\tproto_notify_error \"$cfg\" \"MISSING_BRIDGE_COMMAND\"\n\t\texit\n\t}\n\n\tlocal peer_config=\"$1\"\n\n\tlocal vxlan\n\tlocal lladdr\n\tlocal dst\n\tlocal src_vni\n\tlocal vni\n\tlocal port\n\tlocal via\n\n\tconfig_get vxlan   \"${peer_config}\" \"vxlan\"\n\tconfig_get lladdr  \"${peer_config}\" \"lladdr\"\n\tconfig_get dst     \"${peer_config}\" \"dst\"\n\tconfig_get src_vni \"${peer_config}\" \"src_vni\"\n\tconfig_get vni     \"${peer_config}\" \"vni\"\n\tconfig_get port    \"${peer_config}\" \"port\"\n\tconfig_get via     \"${peer_config}\" \"via\"\n\n\t[ \"$cfg\" = \"$vxlan\" ] || {\n\t\t# This peer section belongs to another device\n\t\treturn\n\t}\n\n\t[ -n \"${dst}\" ] || {\n\t\tproto_notify_error \"$cfg\" \"MISSING_PEER_ADDRESS\"\n\t\texit\n\t}\n\n\tbridge fdb append \\\n\t\t${lladdr:-00:00:00:00:00:00} \\\n\t\tdev ${cfg}                   \\\n\t\tdst ${dst}                   \\\n\t\t${src_vni:+src_vni $src_vni} \\\n\t\t${vni:+vni $vni}             \\\n\t\t${port:+port $port}          \\\n\t\t${via:+via $via}\n}\n\nvxlan_generic_setup() {\n\tlocal cfg=\"$1\"\n\tlocal mode=\"$2\"\n\tlocal local=\"$3\"\n\tlocal remote=\"$4\"\n\n\tlocal link=\"$cfg\"\n\n\tlocal port vid ttl tos mtu macaddr zone rxcsum txcsum srcportmin srcportmax ageing maxaddress learning rsc proxy l2miss l3miss gbp\n\tjson_get_vars port vid ttl tos mtu macaddr zone rxcsum txcsum srcportmin srcportmax ageing maxaddress learning rsc proxy l2miss l3miss gbp\n\n\tproto_init_update \"$link\" 1\n\n\tproto_add_tunnel\n\tjson_add_string mode \"$mode\"\n\n\t[ -n \"$tunlink\" ] && json_add_string link \"$tunlink\"\n\t[ -n \"$local\" ] && json_add_string local \"$local\"\n\t[ -n \"$remote\" ] && json_add_string remote \"$remote\"\n\n\t[ -n \"$ttl\" ] && json_add_int ttl \"$ttl\"\n\t[ -n \"$tos\" ] && json_add_string tos \"$tos\"\n\t[ -n \"$mtu\" ] && json_add_int mtu \"$mtu\"\n\n\tjson_add_object 'data'\n\t[ -n \"$port\" ] && json_add_int port \"$port\"\n\t[ -n \"$vid\" ] && json_add_int id \"$vid\"\n\t[ -n \"$srcportmin\" ] && json_add_int srcportmin \"$srcportmin\"\n\t[ -n \"$srcportmax\" ] && json_add_int srcportmax \"$srcportmax\"\n\t[ -n \"$ageing\" ] && json_add_int ageing \"$ageing\"\n\t[ -n \"$maxaddress\" ] && json_add_int maxaddress \"$maxaddress\"\n\t[ -n \"$macaddr\" ] && json_add_string macaddr \"$macaddr\"\n\t[ -n \"$rxcsum\" ] && json_add_boolean rxcsum \"$rxcsum\"\n\t[ -n \"$txcsum\" ] && json_add_boolean txcsum \"$txcsum\"\n\t[ -n \"$learning\" ] && json_add_boolean learning \"$learning\"\n\t[ -n \"$rsc\" ] && json_add_boolean rsc \"$rsc\"\n\t[ -n \"$proxy\" ] && json_add_boolean proxy \"$proxy\"\n\t[ -n \"$l2miss\" ] && json_add_boolean l2miss \"$l2miss\"\n\t[ -n \"$l3miss\" ] && json_add_boolean l3miss \"$l3miss\"\n\t[ -n \"$gbp\" ] && json_add_boolean gbp \"$gbp\"\n\n\tjson_close_object\n\n\tproto_close_tunnel\n\n\tproto_add_data\n\t[ -n \"$zone\" ] && json_add_string zone \"$zone\"\n\tproto_close_data\n\n\tproto_send_update \"$cfg\"\n\n\tconfig_load network\n\tconfig_foreach proto_vxlan_setup_peer \"vxlan_peer\"\n}\n\nproto_vxlan_setup() {\n\tlocal cfg=\"$1\"\n\n\tlocal ipaddr peeraddr\n\tjson_get_vars ipaddr peeraddr tunlink\n\n\t( proto_add_host_dependency \"$cfg\" '' \"$tunlink\" )\n\n\tcase \"$ipaddr\" in\n\t\t\"auto\"|\"\")\n\t\t\tipaddr=\"0.0.0.0\"\n\t\t\t;;\n\tesac\n\n\tvxlan_generic_setup \"$cfg\" 'vxlan' \"$ipaddr\" \"$peeraddr\"\n}\n\nproto_vxlan6_setup() {\n\tlocal cfg=\"$1\"\n\n\tlocal ip6addr peer6addr\n\tjson_get_vars ip6addr peer6addr tunlink\n\n\t( proto_add_host_dependency \"$cfg\" '' \"$tunlink\" )\n\n\tcase \"$ip6addr\" in\n\t\t\"auto\"|\"\")\n\t\t\t# ensure tunnel via ipv6\n\t\t\tip6addr=\"::\"\n\t\t\t;;\n\tesac\n\n\tvxlan_generic_setup \"$cfg\" 'vxlan6' \"$ip6addr\" \"$peer6addr\"\n}\n\nproto_vxlan_teardown() {\n\tlocal cfg=\"$1\"\n}\n\nproto_vxlan6_teardown() {\n\tlocal cfg=\"$1\"\n}\n\nvxlan_generic_init_config() {\n\tno_device=1\n\tavailable=1\n\n\tproto_config_add_string \"tunlink\"\n\tproto_config_add_string \"zone\"\n\n\tproto_config_add_int \"vid\"\n\tproto_config_add_int \"port\"\n\tproto_config_add_int \"ttl\"\n\tproto_config_add_int \"tos\"\n\tproto_config_add_int \"mtu\"\n\tproto_config_add_int \"srcportmin\"\n\tproto_config_add_int \"srcportmax\"\n\tproto_config_add_int \"ageing\"\n\tproto_config_add_int \"maxaddress\"\n\tproto_config_add_boolean \"rxcsum\"\n\tproto_config_add_boolean \"txcsum\"\n\tproto_config_add_boolean \"learning\"\n\tproto_config_add_boolean \"rsc\"\n\tproto_config_add_boolean \"proxy\"\n\tproto_config_add_boolean \"l2miss\"\n\tproto_config_add_boolean \"l3miss\"\n\tproto_config_add_boolean \"gbp\"\n\tproto_config_add_string \"macaddr\"\n\n}\n\nproto_vxlan_init_config() {\n\tvxlan_generic_init_config\n\tproto_config_add_string \"ipaddr\"\n\tproto_config_add_string \"peeraddr\"\n}\n\nproto_vxlan6_init_config() {\n\tvxlan_generic_init_config\n\tproto_config_add_string \"ip6addr\"\n\tproto_config_add_string \"peer6addr\"\n}\n\n[ -n \"$INCLUDE_ONLY\" ] || {\n\tadd_protocol vxlan\n\tadd_protocol vxlan6\n}\n"
  },
  {
    "path": "package/network/config/xfrm/Makefile",
    "content": "\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=xfrm\nPKG_RELEASE:=4\nPKG_LICENSE:=GPL-2.0\n\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine Package/xfrm/Default\n  SECTION:=net\n  CATEGORY:=Network\n  MAINTAINER:=Andre Valentin <avalentin@marcant.net>\n  PKGARCH:=all\nendef\n\ndefine Package/xfrm\n$(call Package/xfrm/Default)\n  TITLE:=XFRM IPsec Tunnel Interface config support\n  DEPENDS:=+kmod-xfrm-interface\nendef\n\ndefine Package/xfrm/description\n XFRM IPsec Tunnel Interface config support (IPv4 and IPv6) in /etc/config/network.\nendef\n\ndefine Build/Compile\nendef\n\ndefine Build/Configure\nendef\n\ndefine Package/xfrm/install\n\t$(INSTALL_DIR) $(1)/lib/netifd/proto\n\t$(INSTALL_BIN) ./files/xfrm.sh $(1)/lib/netifd/proto/xfrm.sh\nendef\n\n$(eval $(call BuildPackage,xfrm))\n"
  },
  {
    "path": "package/network/config/xfrm/files/xfrm.sh",
    "content": "#!/bin/sh\n\n[ -n \"$INCLUDE_ONLY\" ] || {\n\t. /lib/functions.sh\n\t. /lib/functions/network.sh\n\t. ../netifd-proto.sh\n\tinit_proto \"$@\"\n}\n\nproto_xfrm_setup() {\n\tlocal cfg=\"$1\"\n\tlocal mode=\"xfrm\"\n\n\tlocal tunlink ifid mtu zone multicast\n\tjson_get_vars tunlink ifid mtu zone multicast\n\n\t[ -z \"$tunlink\" ] && {\n\t\tproto_notify_error \"$cfg\" NO_TUNLINK\n\t\tproto_block_restart \"$cfg\"\n\t\texit\n\t}\n\n\t[ -z \"$ifid\" ] && {\n\t\tproto_notify_error \"$cfg\" NO_IFID\n\t\tproto_block_restart \"$cfg\"\n\t\texit\n\t}\n\n\t( proto_add_host_dependency \"$cfg\" '' \"$tunlink\" )\n\n\tproto_init_update \"$cfg\" 1\n\n\tproto_add_tunnel\n\tjson_add_string mode \"$mode\"\n\tjson_add_int mtu \"${mtu:-1280}\"\n\n\tjson_add_string link \"$tunlink\"\n\n\tjson_add_boolean multicast \"${multicast:-1}\"\n\n\tjson_add_object 'data'\n\t[ -n \"$ifid\" ] && json_add_int ifid \"$ifid\"\n\tjson_close_object\n\n\tproto_close_tunnel\n\n\tproto_add_data\n\t[ -n \"$zone\" ] && json_add_string zone \"$zone\"\n\tproto_close_data\n\n\tproto_send_update \"$cfg\"\n}\n\nproto_xfrm_teardown() {\n\tlocal cfg=\"$1\"\n}\n\nproto_xfrm_init_config() {\n\tno_device=1\n\tavailable=1\n\n\tproto_config_add_int \"mtu\"\n\tproto_config_add_string \"tunlink\"\n\tproto_config_add_string \"zone\"\n\tproto_config_add_int \"ifid\"\n\tproto_config_add_boolean \"multicast\"\n}\n\n\n[ -n \"$INCLUDE_ONLY\" ] || {\n\t[ -d /sys/module/xfrm_interface ] && add_protocol xfrm\n}\n"
  },
  {
    "path": "package/network/ipv6/464xlat/Makefile",
    "content": "include $(TOPDIR)/rules.mk\n\nPKG_NAME:=464xlat\nPKG_RELEASE:=12\n\nPKG_SOURCE_DATE:=2018-01-16\nPKG_MAINTAINER:=Hans Dedecker <dedeckeh@gmail.com>\nPKG_LICENSE:=GPL-2.0\n\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine Package/464xlat\n  SECTION:=net\n  CATEGORY:=Network\n  DEPENDS:=@IPV6 +kmod-nat46 +ip\n  TITLE:=464xlat CLAT support\nendef\n\ndefine Build/Prepare\n\t$(call Build/Prepare/Default)\n\t$(CP) ./src/* $(PKG_BUILD_DIR)/\nendef\n\ndefine Build/Compile\n\t$(MAKE) -C $(PKG_BUILD_DIR) \\\n\t\tCC=\"$(TARGET_CC)\" \\\n\t\tCFLAGS=\"$(TARGET_CFLAGS) -Wall\" \\\n\t\tLDFLAGS=\"$(TARGET_LDFLAGS)\"\nendef\n\ndefine Package/464xlat/description\n  464xlat provides support to deploy limited IPv4 access services to mobile\n  and wireline IPv6-only edge networks without encapsulation (RFC6877)\nendef\n\ndefine Package/464xlat/install\n\t$(INSTALL_DIR) $(1)/lib/netifd/proto\n\t$(INSTALL_BIN) ./files/464xlat.sh $(1)/lib/netifd/proto/464xlat.sh\n\t$(INSTALL_DIR) $(1)/sbin\n\t$(INSTALL_BIN) $(PKG_BUILD_DIR)/464xlatcfg $(1)/sbin\nendef\n\n$(eval $(call BuildPackage,464xlat))\n"
  },
  {
    "path": "package/network/ipv6/464xlat/files/464xlat.sh",
    "content": "#!/bin/sh\n# 464xlat.sh - 464xlat CLAT\n#\n# Copyright (c) 2015 Steven Barth <cyrus@openwrt.org>\n#\n# This program is free software; you can redistribute it and/or modify\n# it under the terms of the GNU General Public License version 2\n# as published by the Free Software Foundation\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n# GNU General Public License for more details.\n\n[ -n \"$INCLUDE_ONLY\" ] || {\n\t. /lib/functions.sh\n\t. /lib/functions/network.sh\n\t. ../netifd-proto.sh\n\tinit_proto \"$@\"\n}\n\nproto_464xlat_setup() {\n\tlocal cfg=\"$1\"\n\tlocal iface=\"$2\"\n\tlocal link=\"464-$cfg\"\n\n\tlocal ip6addr ip6prefix tunlink zone\n\tjson_get_vars ip6addr ip6prefix tunlink zone\n\n\t[ \"$zone\" = \"-\" ] && zone=\"\"\n\n\t( proto_add_host_dependency \"$cfg\" \"::\" \"$tunlink\" )\n\n\tif [ -z \"$tunlink\" ] && ! network_find_wan6 tunlink; then\n\t\tproto_notify_error \"$cfg\" \"NO_WAN_LINK\"\n\t\treturn\n\tfi\n\tnetwork_get_device tundev \"$tunlink\"\n\n\tip6addr=$(464xlatcfg \"$link\" \"$tundev\" \"$ip6prefix\" 192.0.0.1 $ip6addr)\n\tif [ -z \"$ip6addr\" ]; then\n\t\tproto_notify_error \"$cfg\" \"CLAT_CONFIG_FAILED\"\n\t\treturn\n\tfi\n\n\tip -6 rule del from all lookup local\n\tip -6 rule add from all lookup local pref 1\n\tip -6 rule add to $ip6addr lookup prelocal pref 0\n\techo \"$ip6addr\" > /tmp/464-$cfg-anycast\n\n\tproto_init_update \"$link\" 1\n\tproto_add_ipv4_route \"0.0.0.0\" 0 \"\" \"\" 2048\n\tproto_add_ipv6_route $ip6addr 128 \"\" \"\" \"\" \"\" 128\n\n\tproto_add_data\n\t[ -n \"$zone\" ] && json_add_string zone \"$zone\"\n\n\tjson_add_array firewall\n\t\t[ -z \"$zone\" ] && zone=$(fw3 -q network $iface 2>/dev/null)\n\n\t\tjson_add_object \"\"\n\t\t\tjson_add_string type nat\n\t\t\tjson_add_string target SNAT\n\t\t\tjson_add_string family inet\n\t\t\tjson_add_string snat_ip 192.0.0.1\n\t\tjson_close_object\n\t\t[ -n \"$zone\" ] && {\n\t\t\tjson_add_object \"\"\n\t\t\t\tjson_add_string type rule\n\t\t\t\tjson_add_string family inet6\n\t\t\t\tjson_add_string proto all\n\t\t\t\tjson_add_string direction in\n\t\t\t\tjson_add_string dest \"$zone\"\n\t\t\t\tjson_add_string src \"$zone\"\n\t\t\t\tjson_add_string src_ip $ip6addr\n\t\t\t\tjson_add_string target ACCEPT\n\t\t\tjson_close_object\n\t\t}\n\tjson_close_array\n\tproto_close_data\n\n\tproto_send_update \"$cfg\"\n}\n\nproto_464xlat_teardown() {\n\tlocal cfg=\"$1\"\n\tlocal link=\"464-$cfg\"\n\n\t[ -f /tmp/464-$cfg-anycast ] || return\n\tlocal ip6addr=$(cat /tmp/464-$cfg-anycast)\n\n\t464xlatcfg \"$link\"\n\n\trm -rf /tmp/464-$cfg-anycast\n\t[ -n \"$ip6addr\" ] && ip -6 rule del to $ip6addr lookup prelocal\n\n\tif [ -z \"$(ls /tmp/464-*-anycast 2>&-)\" ]; then\n\t\tip -6 rule del from all lookup local\n\t\tip -6 rule add from all lookup local pref 0\n\tfi\n}\n\nproto_464xlat_init_config() {\n\tno_device=1\n\tavailable=1\n\n\tproto_config_add_string \"ip6prefix\"\n\tproto_config_add_string \"ip6addr\"\n\tproto_config_add_string \"tunlink\"\n\tproto_config_add_string \"zone\"\n}\n\n[ -n \"$INCLUDE_ONLY\" ] || {\n        add_protocol 464xlat\n}\n"
  },
  {
    "path": "package/network/ipv6/464xlat/src/464xlatcfg.c",
    "content": "/* 464xlatcfg.c\n *\n * Copyright (c) 2015 Steven Barth <cyrus@openwrt.org>\n * Copyright (c) 2017 Hans Dedecker <dedeckeh@gmail.com>\n *\n * This program is free software; you can redistribute it and/or modify\n * it under the terms of the GNU General Public License version 2\n * as published by the Free Software Foundation\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n * GNU General Public License for more details.\n */\n\n#include <netinet/icmp6.h>\n#include <netinet/in.h>\n#include <sys/socket.h>\n#include <arpa/inet.h>\n#include <net/if.h>\n#include <unistd.h>\n#include <stdlib.h>\n#include <signal.h>\n#include <stdio.h>\n#include <netdb.h>\n\nstatic void sighandler(__attribute__((unused)) int signal)\n{\n}\n\nint main(int argc, const char *argv[])\n{\n\tchar buf[INET6_ADDRSTRLEN], prefix[INET6_ADDRSTRLEN + 4];\n\tint pid;\n\n\tif (argc <= 1) {\n\t\tfprintf(stderr, \"Usage: %s <name> [ifname] [ipv6prefix] [ipv4addr] [ipv6addr]\\n\", argv[0]);\n\t\treturn 1;\n\t}\n\n\tsnprintf(buf, sizeof(buf), \"/var/run/%s.pid\", argv[1]);\n\tFILE *fp = fopen(buf, \"r\");\n\tif (fp) {\n\t\tif (fscanf(fp, \"%d\", &pid) == 1)\n\t\t\tkill(pid, SIGTERM);\n\n\t\tunlink(buf);\n\t\tfclose(fp);\n\t}\n\n\tif (!argv[2])\n\t\treturn 0;\n\n\tif (!argv[3] || !argv[4] || !(fp = fopen(buf, \"wx\")))\n\t\treturn 1;\n\n\tsignal(SIGTERM, SIG_DFL);\n\tsetvbuf(fp, NULL, _IOLBF, 0);\n\tfprintf(fp, \"%d\\n\", getpid());\n\n\tprefix[sizeof(prefix) - 1] = 0;\n\tstrncpy(prefix, argv[3], sizeof(prefix) - 1);\n\n\tif (!prefix[0]) {\n\t\tstruct addrinfo hints = { .ai_family = AF_INET6 }, *res;\n\t\tif (getaddrinfo(\"ipv4only.arpa\", NULL, &hints, &res) || !res) {\n\t\t\tsleep(3);\n\t\t\tif (getaddrinfo(\"ipv4only.arpa\", NULL, &hints, &res) || !res)\n\t\t\t\treturn 2;\n\t\t}\n\n\t\tstruct sockaddr_in6 *sin6 = (struct sockaddr_in6*)res->ai_addr;\n\t\tinet_ntop(AF_INET6, &sin6->sin6_addr, prefix, sizeof(prefix) - 4);\n\t\tstrcat(prefix, \"/96\");\n\t\tfreeaddrinfo(res);\n\t}\n\n\tint i = 0;\n\tint sock;\n\tstruct sockaddr_in6 saddr;\n\n\tdo {\n\t\tsocklen_t saddrlen = sizeof(saddr);\n\t\tstruct icmp6_filter filt;\n\n\t\tsock = socket(AF_INET6, SOCK_RAW, IPPROTO_ICMPV6);\n\t\tICMP6_FILTER_SETBLOCKALL(&filt);\n\t\tsetsockopt(sock, IPPROTO_ICMPV6, ICMP6_FILTER, &filt, sizeof(filt));\n\t\tsetsockopt(sock, SOL_SOCKET, SO_BINDTODEVICE, argv[2], strlen(argv[2]));\n\t\tmemset(&saddr, 0, sizeof(saddr));\n\t\tsaddr.sin6_family = AF_INET6;\n\t\tsaddr.sin6_addr.s6_addr32[0] = htonl(0x2001);\n\t\tsaddr.sin6_addr.s6_addr32[1] = htonl(0xdb8);\n\t\tif (connect(sock, (struct sockaddr*)&saddr, sizeof(saddr)) ||\n\t\t\t\tgetsockname(sock, (struct sockaddr*)&saddr, &saddrlen))\n\t\t\treturn 3;\n\n\t\tif (!IN6_IS_ADDR_LINKLOCAL(&saddr.sin6_addr) || argv[5])\n\t\t\tbreak;\n\n\t\tclose(sock);\n\t\tsleep(3);\n\t\ti++;\n\t} while (i < 3);\n\n\tstruct ipv6_mreq mreq = {saddr.sin6_addr, if_nametoindex(argv[2])};\n\tif (!argv[5]) {\n\t\tif (IN6_IS_ADDR_LINKLOCAL(&mreq.ipv6mr_multiaddr))\n\t\t\treturn 5;\n\n\t\tsrandom(mreq.ipv6mr_multiaddr.s6_addr32[0] ^ mreq.ipv6mr_multiaddr.s6_addr32[1] ^\n\t\t\t\tmreq.ipv6mr_multiaddr.s6_addr32[2] ^ mreq.ipv6mr_multiaddr.s6_addr32[3]);\n\t\tmreq.ipv6mr_multiaddr.s6_addr32[2] = random();\n\t\tmreq.ipv6mr_multiaddr.s6_addr32[3] = random();\n\t} else if (inet_pton(AF_INET6, argv[5], &mreq.ipv6mr_multiaddr) != 1) {\n\t\treturn 1;\n\t}\n\n\tif (setsockopt(sock, SOL_IPV6, IPV6_JOIN_ANYCAST, &mreq, sizeof(mreq)))\n\t\treturn 3;\n\n\tinet_ntop(AF_INET6, &mreq.ipv6mr_multiaddr, buf, sizeof(buf));\n\tfputs(buf, stdout);\n\tfputc('\\n', stdout);\n\tfflush(stdout);\n\n\tFILE *nat46 = fopen(\"/proc/net/nat46/control\", \"w\");\n\tif (!nat46 || fprintf(nat46, \"add %s\\nconfig %s local.style NONE local.v4 %s/32 local.v6 %s/128 \"\n\t\t\t\"remote.style RFC6052 remote.v6 %s\\n\", argv[1], argv[1], argv[4], buf, prefix) < 0 ||\n\t\t\tfclose(nat46))\n\t\treturn 4;\n\n\tif (!(pid = fork())) {\n\t\tfclose(fp);\n\t\tfclose(stdin);\n\t\tfclose(stdout);\n\t\tfclose(stderr);\n\t\tchdir(\"/\");\n\t\tsetsid();\n\t\tsignal(SIGTERM, sighandler);\n\t\tpause();\n\n\t\tnat46 = fopen(\"/proc/net/nat46/control\", \"w\");\n\t\tif (nat46) {\n\t\t\tfprintf(nat46, \"del %s\\n\", argv[1]);\n\t\t\tfclose(nat46);\n\t\t}\n\t} else {\n\t\trewind(fp);\n\t\tfprintf(fp, \"%d\\n\", pid);\n\t}\n\n\treturn 0;\n}\n"
  },
  {
    "path": "package/network/ipv6/464xlat/src/Makefile",
    "content": "all: 464xlatcfg\n\n464xlatcfg: 464xlatcfg.c\n\t$(CC) $(CFLAGS) $(LDFLAGS) -o $@ $<\n\nclean:\n\trm -f 464xlatcfg\n\n"
  },
  {
    "path": "package/network/ipv6/6in4/Makefile",
    "content": "#\n# Copyright (C) 2010-2015 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=6in4\nPKG_RELEASE:=28\nPKG_LICENSE:=GPL-2.0\n\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine Package/6in4\n  SECTION:=net\n  CATEGORY:=Network\n  DEPENDS:=@IPV6 +kmod-sit +uclient-fetch\n  TITLE:=IPv6-in-IPv4 configuration support\n  MAINTAINER:=Jo-Philipp Wich <jo@mein.io>\n  PKGARCH:=all\nendef\n\ndefine Package/6in4/description\nProvides support for 6in4 tunnels in /etc/config/network.\nRefer to http://wiki.openwrt.org/doc/uci/network for\nconfiguration details.\nendef\n\ndefine Build/Compile\nendef\n\ndefine Build/Configure\nendef\n\ndefine Package/6in4/install\n\t$(INSTALL_DIR) $(1)/lib/netifd/proto\n\t$(INSTALL_BIN) ./files/6in4.sh $(1)/lib/netifd/proto/6in4.sh\nendef\n\n$(eval $(call BuildPackage,6in4))\n"
  },
  {
    "path": "package/network/ipv6/6in4/files/6in4.sh",
    "content": "#!/bin/sh\n# 6in4.sh - IPv6-in-IPv4 tunnel backend\n# Copyright (c) 2010-2015 OpenWrt.org\n\n[ -n \"$INCLUDE_ONLY\" ] || {\n\t. /lib/functions.sh\n\t. /lib/functions/network.sh\n\t. ../netifd-proto.sh\n\tinit_proto \"$@\"\n}\n\n# Function taken from 6to4 package (6to4.sh), flipped returns\ntest_6in4_rfc1918()\n{\n\tlocal oIFS=\"$IFS\"; IFS=\".\"; set -- $1; IFS=\"$oIFS\"\n\t[ $1 -eq  10 ] && return 1\n\t[ $1 -eq 192 ] && [ $2 -eq 168 ] && return 1\n\t[ $1 -eq 172 ] && [ $2 -ge  16 ] && [ $2 -le  31 ] && return 1\n\n\t# RFC 6598\n\t[ $1 -eq 100 ] && [ $2 -ge  64 ] && [ $2 -le 127 ] && return 1\n\n\treturn 0\n}\n\nproto_6in4_update() {\n\tsh -c '\n\t\ttimeout=5\n\n\t\t(while [ $((timeout--)) -gt 0 ]; do\n\t\t\tsleep 1\n\t\t\tkill -0 $$ || exit 0\n\t\tdone; kill -9 $$) 2>/dev/null &\n\n\t\texec \"$@\"\n\t' \"$1\" \"$@\"\n}\n\nproto_6in4_add_prefix() {\n\tappend \"$3\" \"$1\"\n}\n\nproto_6in4_setup() {\n\tlocal cfg=\"$1\"\n\tlocal iface=\"$2\"\n\tlocal link=\"6in4-$cfg\"\n\n\tlocal mtu ttl tos ipaddr peeraddr ip6addr ip6prefix ip6prefixes tunlink tunnelid username password updatekey\n\tjson_get_vars mtu ttl tos ipaddr peeraddr ip6addr tunlink tunnelid username password updatekey\n\tjson_for_each_item proto_6in4_add_prefix ip6prefix ip6prefixes\n\n\t[ -z \"$peeraddr\" ] && {\n\t\tproto_notify_error \"$cfg\" \"MISSING_ADDRESS\"\n\t\tproto_block_restart \"$cfg\"\n\t\treturn\n\t}\n\n\t( proto_add_host_dependency \"$cfg\" \"$peeraddr\" \"$tunlink\" )\n\n\t[ -z \"$ipaddr\" ] && {\n\t\tlocal wanif=\"$tunlink\"\n\t\tif [ -z \"$wanif\" ] && ! network_find_wan wanif; then\n\t\t\tproto_notify_error \"$cfg\" \"NO_WAN_LINK\"\n\t\t\treturn\n\t\tfi\n\n\t\tif ! network_get_ipaddr ipaddr \"$wanif\"; then\n\t\t\tproto_notify_error \"$cfg\" \"NO_WAN_LINK\"\n\t\t\treturn\n\t\tfi\n\t}\n\n\tproto_init_update \"$link\" 1\n\n\t[ -n \"$ip6addr\" ] && {\n\t\tlocal local6=\"${ip6addr%%/*}\"\n\t\tlocal mask6=\"${ip6addr##*/}\"\n\t\t[ \"$local6\" = \"$mask6\" ] && mask6=\n\t\tproto_add_ipv6_address \"$local6\" \"$mask6\"\n\t\tproto_add_ipv6_route \"::\" 0 \"\" \"\" \"\" \"$local6/$mask6\"\n\t}\n\n\tfor ip6prefix in $ip6prefixes; do\n\t\tproto_add_ipv6_prefix \"$ip6prefix\"\n\t\tproto_add_ipv6_route \"::\" 0 \"\" \"\" \"\" \"$ip6prefix\"\n\tdone\n\n\tproto_add_tunnel\n\tjson_add_string mode sit\n\tjson_add_int mtu \"${mtu:-1280}\"\n\tjson_add_int ttl \"${ttl:-64}\"\n\t[ -n \"$tos\" ] && json_add_string tos \"$tos\"\n\tjson_add_string local \"$ipaddr\"\n\tjson_add_string remote \"$peeraddr\"\n\t[ -n \"$tunlink\" ] && json_add_string link \"$tunlink\"\n\tproto_close_tunnel\n\n\tproto_send_update \"$cfg\"\n\n\t[ -n \"$tunnelid\" -a -n \"$username\" -a \\( -n \"$password\" -o -n \"$updatekey\" \\) ] && {\n\t\t[ -n \"$updatekey\" ] && password=\"$updatekey\"\n\n\t\tlocal http=\"http\"\n\t\tlocal urlget=\"uclient-fetch\"\n\t\tlocal urlget_opts=\"-qO-\"\n\t\tlocal ca_path=\"${SSL_CERT_DIR:-/etc/ssl/certs}\"\n\n\t\t[ -f /lib/libustream-ssl.so ] && http=https\n\t\t[ \"$http\" = \"https\" -a -z \"$(find $ca_path -name \"*.0\" 2>/dev/null)\" ] && {\n\t\t\turlget_opts=\"$urlget_opts --no-check-certificate\"\n\t\t}\n\n\t\tlocal url=\"$http://ipv4.tunnelbroker.net/nic/update?hostname=$tunnelid\"\n\t\t\n\t\ttest_6in4_rfc1918 \"$ipaddr\" && {\n\t\t\tlocal url=\"${url}&myip=${ipaddr}\"\n\t\t}\n\n\t\tlocal try=0\n\t\tlocal max=3\n\n\t\t(\n\t\t\tset -o pipefail\n\t\t\twhile [ $((++try)) -le $max ]; do\n\t\t\t\tif proto_6in4_update $urlget $urlget_opts --user=\"$username\" --password=\"$password\" \"$url\" 2>&1 | \\\n\t\t\t\t\tsed -e 's,^Killed$,timeout,' -e \"s,^,update $try/$max: ,\" | \\\n\t\t\t\t\tlogger -t \"$link\";\n\t\t\t\tthen\n\t\t\t\t\tlogger -t \"$link\" \"updated\"\n\t\t\t\t\treturn 0\n\t\t\t\tfi\n\t\t\t\tsleep 5\n\t\t\tdone\n\t\t\tlogger -t \"$link\" \"update failed\"\n\t\t)\n\t}\n}\n\nproto_6in4_teardown() {\n\tlocal cfg=\"$1\"\n}\n\nproto_6in4_init_config() {\n\tno_device=1\n\tavailable=1\n\n\tproto_config_add_string \"ipaddr\"\n\tproto_config_add_string \"ip6addr\"\n\tproto_config_add_array \"ip6prefix\"\n\tproto_config_add_string \"peeraddr\"\n\tproto_config_add_string \"tunlink\"\n\tproto_config_add_string \"tunnelid\"\n\tproto_config_add_string \"username\"\n\tproto_config_add_string \"password\"\n\tproto_config_add_string \"updatekey\"\n\tproto_config_add_int \"mtu\"\n\tproto_config_add_int \"ttl\"\n\tproto_config_add_string \"tos\"\n}\n\n[ -n \"$INCLUDE_ONLY\" ] || {\n\tadd_protocol 6in4\n}\n"
  },
  {
    "path": "package/network/ipv6/6rd/Makefile",
    "content": "#\n# Copyright (C) 2010-2012 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=6rd\nPKG_RELEASE:=12\nPKG_LICENSE:=GPL-2.0\n\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine Package/6rd\n  SECTION:=net\n  CATEGORY:=Network\n  DEPENDS:=@IPV6 +kmod-sit\n  TITLE:=6rd configuration support\n  MAINTAINER:=Steven Barth <cyrus@openwrt.org>\n  PKGARCH:=all\nendef\n\ndefine Package/6rd/description\nProvides support for 6rd tunnels in /etc/config/network.\nRefer to http://wiki.openwrt.org/doc/uci/network for\nconfiguration details.\nendef\n\ndefine Build/Configure\nendef\n\ndefine Build/Compile\n\t$(MAKE) -C $(PKG_BUILD_DIR) \\\n\t\tCC=\"$(TARGET_CC)\" \\\n\t\tCFLAGS=\"$(TARGET_CFLAGS) -Wall\" \\\n\t\tLDFLAGS=\"$(TARGET_LDFLAGS)\"\nendef\n\ndefine Package/6rd/install\n\t$(INSTALL_DIR) $(1)/usr/sbin\n\t$(INSTALL_BIN) $(PKG_BUILD_DIR)/6rdcalc $(1)/usr/sbin/\n\t$(INSTALL_DIR) $(1)/lib/netifd/proto\n\t$(INSTALL_BIN) ./files/6rd.sh $(1)/lib/netifd/proto/6rd.sh\nendef\n\n$(eval $(call BuildPackage,6rd))\n"
  },
  {
    "path": "package/network/ipv6/6rd/files/6rd.sh",
    "content": "#!/bin/sh\n# 6rd.sh - IPv6-in-IPv4 tunnel backend\n# Copyright (c) 2010-2012 OpenWrt.org\n\n[ -n \"$INCLUDE_ONLY\" ] || {\n\t. /lib/functions.sh\n\t. /lib/functions/network.sh\n\t. ../netifd-proto.sh\n\tinit_proto \"$@\"\n}\n\nproto_6rd_setup() {\n\tlocal cfg=\"$1\"\n\tlocal iface=\"$2\"\n\tlocal link=\"6rd-$cfg\"\n\n\tlocal mtu df ttl tos ipaddr peeraddr ip6prefix ip6prefixlen ip4prefixlen tunlink zone\n\tjson_get_vars mtu df ttl tos ipaddr peeraddr ip6prefix ip6prefixlen ip4prefixlen tunlink zone\n\n\t[ -z \"$ip6prefix\" -o -z \"$peeraddr\" ] && {\n\t\tproto_notify_error \"$cfg\" \"MISSING_ADDRESS\"\n\t\tproto_block_restart \"$cfg\"\n\t\treturn\n\t}\n\n\t( proto_add_host_dependency \"$cfg\" \"$peeraddr\" \"$tunlink\" )\n\n\t[ -z \"$ipaddr\" ] && {\n\t\tlocal wanif=\"$tunlink\"\n\t\tif [ -z $wanif ] && ! network_find_wan wanif; then\n\t\t\tproto_notify_error \"$cfg\" \"NO_WAN_LINK\"\n\t\t\treturn\n\t\tfi\n\n\t\tif ! network_get_ipaddr ipaddr \"$wanif\"; then\n\t\t\tproto_notify_error \"$cfg\" \"NO_WAN_LINK\"\n\t\t\treturn\n\t\tfi\n\t}\n\n\t# Determine the relay prefix.\n\tlocal ip4prefixlen=\"${ip4prefixlen:-0}\"\n\tlocal ip4prefix\n\teval \"$(ipcalc.sh \"$ipaddr/$ip4prefixlen\")\";ip4prefix=$NETWORK\n\n\t# Determine our IPv6 address.\n\tlocal ip6subnet=$(6rdcalc \"$ip6prefix/$ip6prefixlen\" \"$ipaddr/$ip4prefixlen\")\n\tlocal ip6addr=\"${ip6subnet%%::*}::1\"\n\n\t# Determine the IPv6 prefix\n\tlocal ip6lanprefix=\"$ip6subnet/$(($ip6prefixlen + 32 - $ip4prefixlen))\"\n\n\tproto_init_update \"$link\" 1\n\tproto_add_ipv6_address \"$ip6addr\" \"$ip6prefixlen\"\n\tproto_add_ipv6_prefix \"$ip6lanprefix\"\n\n\tproto_add_ipv6_route \"::\" 0 \"::$peeraddr\" 4096 \"\" \"$ip6addr/$ip6prefixlen\"\n\tproto_add_ipv6_route \"::\" 0 \"::$peeraddr\" 4096 \"\" \"$ip6lanprefix\"\n\n\tproto_add_tunnel\n\tjson_add_string mode sit\n\tjson_add_int mtu \"${mtu:-1280}\"\n\tjson_add_boolean df \"${df:-1}\"\n\tjson_add_int ttl \"${ttl:-64}\"\n\t[ -n \"$tos\" ] && json_add_string tos \"$tos\"\n\tjson_add_string local \"$ipaddr\"\n\t[ -n \"$tunlink\" ] && json_add_string link \"$tunlink\"\n\n\tjson_add_object 'data'\n\tjson_add_string prefix \"$ip6prefix/$ip6prefixlen\"\n\tjson_add_string relay-prefix \"$ip4prefix/$ip4prefixlen\"\n\tjson_close_object\n\n\tproto_close_tunnel\n\n\tproto_add_data\n\t[ -n \"$zone\" ] && json_add_string zone \"$zone\"\n\tproto_close_data\n\n\tproto_send_update \"$cfg\"\n}\n\nproto_6rd_teardown() {\n\tlocal cfg=\"$1\"\n}\n\nproto_6rd_init_config() {\n\tno_device=1\n\tavailable=1\n\n\tproto_config_add_int \"mtu\"\n\tproto_config_add_boolean \"df\"\n\tproto_config_add_int \"ttl\"\n\tproto_config_add_string \"tos\"\n\tproto_config_add_string \"ipaddr\"\n\tproto_config_add_string \"peeraddr\"\n\tproto_config_add_string \"ip6prefix\"\n\tproto_config_add_string \"ip6prefixlen\"\n\tproto_config_add_string \"ip4prefixlen\"\n\tproto_config_add_string \"tunlink\"\n\tproto_config_add_string \"zone\"\n}\n\n[ -n \"$INCLUDE_ONLY\" ] || {\n\tadd_protocol 6rd\n}\n"
  },
  {
    "path": "package/network/ipv6/6rd/src/6rdcalc.c",
    "content": "/*\n * Utility used to calculate the 6rd subnet.\n *\n * Copyright 2012, Stéphan Kochen <stephan@kochen.nl>\n *\n * This program is free software; you can redistribute it and/or\n * modify it under the terms of the GNU General Public License\n * as published by the Free Software Foundation; either version 2\n * of the License, or (at your option) any later version.\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n * GNU General Public License for more details.\n *\n * You should have received a copy of the GNU General Public License\n * along with this program; if not, write to the Free Software\n * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.\n */\n\n#include <stdio.h>\n#include <stdlib.h>\n#include <string.h>\n#include <sys/errno.h>\n#include <arpa/inet.h>\n#include <netinet/in.h>\n\n#define INET_PREFIXSTRLEN (INET_ADDRSTRLEN+3)\n#define INET6_PREFIXSTRLEN (INET6_ADDRSTRLEN+4)\n\nstatic void print_usage()\n{\n\tfprintf(stderr, \"Usage: 6rdcalc <v6 prefix>/<mask> <v4 address>/<mask>\\n\");\n\texit(1);\n}\n\nstatic void print_error()\n{\n\tfprintf(stderr, \"%s\", strerror(errno));\n\texit(1);\n}\n\nstatic void parse_str(int af, char *str, void *addr, unsigned long *mask)\n{\n\tint ret;\n\tchar *slash;\n\n\t/* Split the address at the slash. */\n\tif ((slash = strchr(str, '/')) == NULL)\n\t\tprint_usage();\n\t*slash = '\\0';\n\n\t/* Parse the address. */\n\tif ((ret = inet_pton(af, str, addr)) != 1) {\n\t\tif (ret == 0)\n\t\t\tprint_usage();\n\t\telse\n\t\t\tprint_error();\n\t}\n\n\t/* Parse the mask. */\n\t*mask = strtoul(slash+1, NULL, 10);\n\tif ((af == AF_INET  && *mask >  32) ||\n\t\t(af == AF_INET6 && *mask > 128))\n\t\tprint_usage();\n}\n\nint main(int argc, const char **argv)\n{\n\tchar v6str[INET6_PREFIXSTRLEN], v4str[INET_PREFIXSTRLEN];\n\tstruct in6_addr v6;\n\tstruct in_addr v4;\n\tunsigned long v6it, v4it, mask;\n\tunsigned char *byte4, *byte6;\n\tunsigned char bit4, bit6;\n\n\t/* Check parameters. */\n\tif (argc != 3)\n\t\tprint_usage();\n\n\t/* Parse the v6 address. */\n\tstrncpy(v6str, argv[1], INET6_PREFIXSTRLEN);\n\tv6str[INET6_PREFIXSTRLEN-1] = '\\0';\n\tparse_str(AF_INET6, v6str, &v6, &v6it);\n\n\t/* Parse the v4 address */\n\tstrncpy(v4str, argv[2], INET_PREFIXSTRLEN);\n\tv6str[INET_PREFIXSTRLEN-1] = '\\0';\n\tparse_str(AF_INET, v4str, &v4, &v4it);\n\n\t/* Check if the combined mask is within bounds. */\n\tmask = (32 - v4it) + v6it;\n\tif (mask > 128)\n\t\tprint_usage();\n\n\t/* Combine the addresses. */\n\twhile (v4it < 32) {\n\t\tbyte6 = (unsigned char *)(&v6.s6_addr) + (v6it >> 3);\n\t\tbyte4 = (unsigned char *)(&v4.s_addr)  + (v4it >> 3);\n\t\tbit6 = 128 >> (v6it & 0x07);\n\t\tbit4 = 128 >> (v4it & 0x07);\n\n\t\tif (*byte4 & bit4)\n\t\t\t*byte6 |= bit6;\n\t\telse\n\t\t\t*byte6 &= ~bit6;\n\n\t\tv4it++; v6it++;\n\t}\n\n\t/* Clear remaining bits. */\n\twhile (v6it < 128) {\n\t\tbyte6 = (unsigned char *)(&v6.s6_addr) + (v6it >> 3);\n\t\tbit6 = 128 >> (v6it & 0x07);\n\n\t\t*byte6 &= ~bit6;\n\n\t\tv6it++;\n\t}\n\n\t/* Print the subnet prefix. */\n\tif (inet_ntop(AF_INET6, &v6, v6str, sizeof(v6str)) == NULL)\n\t\tprint_error();\n\tprintf(\"%s/%lu\\n\", v6str, mask);\n\treturn 0;\n}\n"
  },
  {
    "path": "package/network/ipv6/6rd/src/Makefile",
    "content": "all: 6rdcalc\n\n6rdcalc: 6rdcalc.c\n\t$(CC) $(CFLAGS) $(LDFLAGS) -o $@ $<\n\nclean:\n\trm -f 6rdcalc\n"
  },
  {
    "path": "package/network/ipv6/6to4/Makefile",
    "content": "#\n# Copyright (C) 2010-2012 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=6to4\nPKG_RELEASE:=13\nPKG_LICENSE:=GPL-2.0\n\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine Package/6to4\n  SECTION:=net\n  CATEGORY:=Network\n  DEPENDS:=@IPV6 +kmod-sit\n  TITLE:=IPv6-to-IPv4 configuration support\n  MAINTAINER:=Jo-Philipp Wich <xm@subsignal.org>\n  PKGARCH:=all\nendef\n\ndefine Package/6to4/description\nProvides support for 6to4 tunnels in /etc/config/network.\nRefer to https://openwrt.org/docs/guide-user/base-system/basic-networking\nconfiguration details.\nendef\n\ndefine Build/Compile\nendef\n\ndefine Build/Configure\nendef\n\ndefine Package/6to4/install\n\t$(INSTALL_DIR) $(1)/lib/netifd/proto\n\t$(INSTALL_BIN) ./files/6to4.sh $(1)/lib/netifd/proto/6to4.sh\nendef\n\n$(eval $(call BuildPackage,6to4))\n"
  },
  {
    "path": "package/network/ipv6/6to4/files/6to4.sh",
    "content": "#!/bin/sh\n# 6to4.sh - IPv6-in-IPv4 tunnel backend\n# Copyright (c) 2010-2012 OpenWrt.org\n\n[ -n \"$INCLUDE_ONLY\" ] || {\n\t. /lib/functions.sh\n\t. /lib/functions/network.sh\n\t. ../netifd-proto.sh\n\tinit_proto \"$@\"\n}\n\nfind_6to4_prefix() {\n\tlocal ip4=\"$1\"\n\tlocal oIFS=\"$IFS\"; IFS=\".\"; set -- $ip4; IFS=\"$oIFS\"\n\n\tprintf \"2002:%02x%02x:%02x%02x\\n\" $1 $2 $3 $4\n}\n\ntest_6to4_rfc1918()\n{\n\tlocal oIFS=\"$IFS\"; IFS=\".\"; set -- $1; IFS=\"$oIFS\"\n\t[ $1 -eq  10 ] && return 0\n\t[ $1 -eq 192 ] && [ $2 -eq 168 ] && return 0\n\t[ $1 -eq 172 ] && [ $2 -ge  16 ] && [ $2 -le  31 ] && return 0\n\n\t# RFC 6598\n\t[ $1 -eq 100 ] && [ $2 -ge  64 ] && [ $2 -le 127 ] && return 0\n\n\treturn 1\n}\n\nproto_6to4_setup() {\n\tlocal cfg=\"$1\"\n\tlocal iface=\"$2\"\n\tlocal link=\"6to4-$cfg\"\n\n\tlocal mtu ttl tos ipaddr\n\tjson_get_vars mtu ttl tos ipaddr\n\n\t( proto_add_host_dependency \"$cfg\" 0.0.0.0 )\n\n\tlocal wanif\n\tif ! network_find_wan wanif; then\n\t\tproto_notify_error \"$cfg\" \"NO_WAN_LINK\"\n\t\treturn\n\tfi\n\n\t[ -z \"$ipaddr\" ] && {\n\t\tif ! network_get_ipaddr ipaddr \"$wanif\"; then\n\t\t\tproto_notify_error \"$cfg\" \"NO_WAN_ADDRESS\"\n\t\t\treturn\n\t\tfi\n\t}\n\n\ttest_6to4_rfc1918 \"$ipaddr\" && {\n\t\tproto_notify_error \"$cfg\" \"INVALID_LOCAL_ADDRESS\"\n\t\treturn\n\t}\n\n\t# find our local prefix\n\tlocal prefix6=$(find_6to4_prefix \"$ipaddr\")\n\tlocal local6=\"$prefix6::1\"\n\n\tproto_init_update \"$link\" 1\n\tproto_add_ipv6_address \"$local6\" 16\n\tproto_add_ipv6_prefix \"$prefix6::/48\"\n\n\tproto_add_ipv6_route \"::\" 0 \"::192.88.99.1\" \"\" \"\" \"$local6/16\"\n\tproto_add_ipv6_route \"::\" 0 \"::192.88.99.1\" \"\" \"\" \"$prefix6::/48\"\n\n\tproto_add_tunnel\n\tjson_add_string mode sit\n\tjson_add_int mtu \"${mtu:-1280}\"\n\tjson_add_int ttl \"${ttl:-64}\"\n\t[ -n \"$tos\" ] && json_add_string tos \"$tos\"\n\tjson_add_string local \"$ipaddr\"\n\tproto_close_tunnel\n\n\tproto_send_update \"$cfg\"\n}\n\nproto_6to4_teardown() {\n\tlocal cfg=\"$1\"\n}\n\nproto_6to4_init_config() {\n\tno_device=1\n\tavailable=1\n\n\tproto_config_add_string \"ipaddr\"\n\tproto_config_add_int \"mtu\"\n\tproto_config_add_int \"ttl\"\n\tproto_config_add_string \"tos\"\n}\n\n[ -n \"$INCLUDE_ONLY\" ] || {\n\tadd_protocol 6to4\n}\n"
  },
  {
    "path": "package/network/ipv6/ds-lite/Makefile",
    "content": "#\n# Copyright (C) 2013 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=ds-lite\nPKG_RELEASE:=8\nPKG_LICENSE:=GPL-2.0\n\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine Package/ds-lite\n  SECTION:=net\n  CATEGORY:=Network\n  DEPENDS:=@IPV6 +kmod-ip6-tunnel +resolveip\n  TITLE:=Dual-Stack Lite (DS-Lite) configuration support\n  MAINTAINER:=Steven Barth <steven@midlink.org>\n  PKGARCH:=all\nendef\n\ndefine Package/ds-lite/description\nProvides support for Dual-Stack Lite in /etc/config/network.\nRefer to http://wiki.openwrt.org/doc/uci/network for\nconfiguration details.\nendef\n\ndefine Build/Compile\nendef\n\ndefine Build/Configure\nendef\n\ndefine Package/ds-lite/install\n\t$(INSTALL_DIR) $(1)/lib/netifd/proto\n\t$(INSTALL_BIN) ./files/dslite.sh $(1)/lib/netifd/proto/dslite.sh\nendef\n\n$(eval $(call BuildPackage,ds-lite))\n"
  },
  {
    "path": "package/network/ipv6/ds-lite/files/dslite.sh",
    "content": "#!/bin/sh\n# dslite.sh - IPv4-in-IPv6 tunnel backend\n# Copyright (c) 2013 OpenWrt.org\n\n[ -n \"$INCLUDE_ONLY\" ] || {\n\t. /lib/functions.sh\n\t. /lib/functions/network.sh\n\t. ../netifd-proto.sh\n\tinit_proto \"$@\"\n}\n\nproto_dslite_setup() {\n\tlocal cfg=\"$1\"\n\tlocal iface=\"$2\"\n\tlocal link=\"ds-$cfg\"\n\tlocal remoteip6\n\n\tlocal mtu ttl peeraddr ip6addr tunlink zone weakif encaplimit\n\tjson_get_vars mtu ttl peeraddr ip6addr tunlink zone weakif encaplimit\n\n\t[ -z \"$peeraddr\" ] && {\n\t\tproto_notify_error \"$cfg\" \"MISSING_ADDRESS\"\n\t\tproto_block_restart \"$cfg\"\n\t\treturn\n\t}\n\n\t( proto_add_host_dependency \"$cfg\" \"::\" \"$tunlink\" )\n\n\tremoteip6=$(resolveip -6 \"$peeraddr\")\n\tif [ -z \"$remoteip6\" ]; then\n\t\tsleep 3\n\t\tremoteip6=$(resolveip -6 \"$peeraddr\")\n\t\tif [ -z \"$remoteip6\" ]; then\n\t\t\tproto_notify_error \"$cfg\" \"AFTR_DNS_FAIL\"\n\t\t\treturn\n\t\tfi\n\tfi\n\n\tfor ip6 in $remoteip6; do\n\t\tpeeraddr=$ip6\n\t\tbreak\n\tdone\n\n\t[ -z \"$ip6addr\" ] && {\n\t\tlocal wanif=\"$tunlink\"\n\t\tif [ -z \"$wanif\" ] && ! network_find_wan6 wanif; then\n\t\t\tproto_notify_error \"$cfg\" \"NO_WAN_LINK\"\n\t\t\treturn\n\t\tfi\n\n\t\tif ! network_get_ipaddr6 ip6addr \"$wanif\"; then\n\t\t\t[ -z \"$weakif\" ] && weakif=\"lan\"\n\t\t\tif ! network_get_ipaddr6 ip6addr \"$weakif\"; then\n\t\t\t\tproto_notify_error \"$cfg\" \"NO_WAN_LINK\"\n\t\t\t\treturn\n\t\t\tfi\n\t\tfi\n\t}\n\n\tproto_init_update \"$link\" 1\n\tproto_add_ipv4_route \"0.0.0.0\" 0\n\tproto_add_ipv4_address \"192.0.0.2\" \"\" \"\" \"192.0.0.1\"\n\n\tproto_add_tunnel\n\tjson_add_string mode ipip6\n\tjson_add_int mtu \"${mtu:-1280}\"\n\tjson_add_int ttl \"${ttl:-64}\"\n\tjson_add_string local \"$ip6addr\"\n\tjson_add_string remote \"$peeraddr\"\n\t[ -n \"$tunlink\" ] && json_add_string link \"$tunlink\"\n\tjson_add_object \"data\"\n\t  [ -n \"$encaplimit\" ] && json_add_string encaplimit \"$encaplimit\"\n\tjson_close_object\n\tproto_close_tunnel\n\n\tproto_add_data\n\t[ -n \"$zone\" ] && json_add_string zone \"$zone\"\n\n\tjson_add_array firewall\n\t  json_add_object \"\"\n\t    json_add_string type nat\n\t    json_add_string target ACCEPT\n\t  json_close_object\n\tjson_close_array\n\tproto_close_data\n\n\tproto_send_update \"$cfg\"\n}\n\nproto_dslite_teardown() {\n\tlocal cfg=\"$1\"\n}\n\nproto_dslite_init_config() {\n\tno_device=1             \n\tavailable=1\n\n\tproto_config_add_string \"ip6addr\"\n\tproto_config_add_string \"peeraddr\"\n\tproto_config_add_string \"tunlink\"\n\tproto_config_add_int \"mtu\"\n\tproto_config_add_int \"ttl\"\n\tproto_config_add_string \"encaplimit\"\n\tproto_config_add_string \"zone\"\n\tproto_config_add_string \"weakif\"\n}\n\n[ -n \"$INCLUDE_ONLY\" ] || {\n        add_protocol dslite\n}\n"
  },
  {
    "path": "package/network/ipv6/map/Makefile",
    "content": "#\n# Copyright (C) 2014-2015 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=map\nPKG_RELEASE:=7\nPKG_LICENSE:=GPL-2.0\n\ninclude $(INCLUDE_DIR)/package.mk\ninclude $(INCLUDE_DIR)/cmake.mk\n\ndefine Package/map\n  SECTION:=net\n  CATEGORY:=Network\n  DEPENDS:=@IPV6 +kmod-ip6-tunnel +libubox +libubus +iptables-mod-conntrack-extra +kmod-nat46\n  TITLE:=MAP-E/MAP-T and Lightweight 4over6 configuration support\n  MAINTAINER:=Hans Dedecker <dedeckeh@gmail.com>\n  PROVIDES:=map-t\nendef\n\ndefine Package/map/description\n Provides support for MAP-E (RFC7597), MAP-T (RFC7599) and\n Lightweight 4over6 (RFC7596) in /etc/config/network.\n MAP combines address and port translation with the tunneling\n of IPv4 packets over an IPv6 network\nendef\n\ndefine Package/map/install\n\t$(INSTALL_DIR) $(1)/lib/netifd/proto\n\t$(INSTALL_BIN) ./files/map.sh $(1)/lib/netifd/proto/map.sh\n\t$(INSTALL_DIR) $(1)/usr/sbin\n\t$(INSTALL_BIN) $(PKG_BUILD_DIR)/mapcalc $(1)/usr/sbin/\nendef\n\n$(eval $(call BuildPackage,map))\n"
  },
  {
    "path": "package/network/ipv6/map/files/map.sh",
    "content": "#!/bin/sh\n# map.sh - IPv4-in-IPv6 tunnel backend\n#\n# Author: Steven Barth <cyrus@openwrt.org>\n# Copyright (c) 2014 cisco Systems, Inc.\n#\n# This program is free software; you can redistribute it and/or modify\n# it under the terms of the GNU General Public License version 2\n# as published by the Free Software Foundation\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n# GNU General Public License for more details.\n\n[ -n \"$INCLUDE_ONLY\" ] || {\n\t. /lib/functions.sh\n\t. /lib/functions/network.sh\n\t. ../netifd-proto.sh\n\tinit_proto \"$@\"\n}\n\nproto_map_setup() {\n\tlocal cfg=\"$1\"\n\tlocal iface=\"$2\"\n\tlocal link=\"map-$cfg\"\n\n\tlocal maptype type legacymap mtu ttl tunlink zone encaplimit\n\tlocal rule ipaddr ip4prefixlen ip6prefix ip6prefixlen peeraddr ealen psidlen psid offset\n\tjson_get_vars maptype type legacymap mtu ttl tunlink zone encaplimit\n\tjson_get_vars rule ipaddr ip4prefixlen ip6prefix ip6prefixlen peeraddr ealen psidlen psid offset\n\n\t[ \"$zone\" = \"-\" ] && zone=\"\"\n\n\t# Compatibility with older config: use $type if $maptype is missing\n\t[ -z \"$maptype\" ] && maptype=\"$type\"\n\t[ -z \"$maptype\" ] && maptype=\"map-e\"\n\t[ -z \"$ip4prefixlen\" ] && ip4prefixlen=32\n\n\t( proto_add_host_dependency \"$cfg\" \"::\" \"$tunlink\" )\n\n\t# fixme: handle RA/DHCPv6 address race for LW\n\t[ \"$maptype\" = lw4o6 ] && sleep 5\n\n\tif [ -z \"$rule\" ]; then\n\t\trule=\"type=$maptype,ipv6prefix=$ip6prefix,prefix6len=$ip6prefixlen,ipv4prefix=$ipaddr,prefix4len=$ip4prefixlen\"\n\t\t[ -n \"$psid\" ] && rule=\"$rule,psid=$psid\"\n\t\t[ -n \"$psidlen\" ] && rule=\"$rule,psidlen=$psidlen\"\n\t\t[ -n \"$offset\" ] && rule=\"$rule,offset=$offset\"\n\t\t[ -n \"$ealen\" ] && rule=\"$rule,ealen=$ealen\"\n\t\tif [ \"$maptype\" = \"map-t\" ]; then\n\t\t\trule=\"$rule,dmr=$peeraddr\"\n\t\telse\n\t\t\trule=\"$rule,br=$peeraddr\"\n\t\tfi\n\tfi\n\n\techo \"rule=$rule\" > /tmp/map-$cfg.rules\n\tRULE_DATA=$(LEGACY=\"$legacymap\" mapcalc ${tunlink:-\\*} $rule)\n\tif [ \"$?\" != 0 ]; then\n\t\tproto_notify_error \"$cfg\" \"INVALID_MAP_RULE\"\n\t\tproto_block_restart \"$cfg\"\n\t\treturn\n\tfi\n\n\techo \"$RULE_DATA\" >> /tmp/map-$cfg.rules\n\teval $RULE_DATA\n\n\tif [ -z \"$RULE_BMR\" ]; then\n\t\tproto_notify_error \"$cfg\" \"NO_MATCHING_PD\"\n\t\tproto_block_restart \"$cfg\"\n\t\treturn\n\tfi\n\n\tk=$RULE_BMR\n\tif [ \"$maptype\" = \"lw4o6\" -o \"$maptype\" = \"map-e\" ]; then\n\t\tproto_init_update \"$link\" 1\n\t\tproto_add_ipv4_address $(eval \"echo \\$RULE_${k}_IPV4ADDR\") \"\" \"\" \"\"\n\n\t\tproto_add_tunnel\n\t\tjson_add_string mode ipip6\n\t\tjson_add_int mtu \"${mtu:-1280}\"\n\t\tjson_add_int ttl \"${ttl:-64}\"\n\t\tjson_add_string local $(eval \"echo \\$RULE_${k}_IPV6ADDR\")\n\t\tjson_add_string remote $(eval \"echo \\$RULE_${k}_BR\")\n\t\tjson_add_string link $(eval \"echo \\$RULE_${k}_PD6IFACE\")\n\t\tjson_add_object \"data\"\n\t\t\t[ -n \"$encaplimit\" ] && json_add_string encaplimit \"$encaplimit\"\n\t\t\tif [ \"$maptype\" = \"map-e\" ]; then\n\t\t\t\tjson_add_array \"fmrs\"\n\t\t\t\tfor i in $(seq $RULE_COUNT); do\n\t\t\t\t\t[ \"$(eval \"echo \\$RULE_${i}_FMR\")\" != 1 ] && continue\n\t\t\t\t\tjson_add_object \"\"\n\t\t\t\t\tjson_add_string prefix6 \"$(eval \"echo \\$RULE_${i}_IPV6PREFIX\")/$(eval \"echo \\$RULE_${i}_PREFIX6LEN\")\"\n\t\t\t\t\tjson_add_string prefix4 \"$(eval \"echo \\$RULE_${i}_IPV4PREFIX\")/$(eval \"echo \\$RULE_${i}_PREFIX4LEN\")\"\n\t\t\t\t\tjson_add_int ealen $(eval \"echo \\$RULE_${i}_EALEN\")\n\t\t\t\t\tjson_add_int offset $(eval \"echo \\$RULE_${i}_OFFSET\")\n\t\t\t\t\tjson_close_object\n\t\t\t\tdone\n\t\t\t\tjson_close_array\n\t\t\tfi\n\t\tjson_close_object\n\n\n\t\tproto_close_tunnel\n\telif [ \"$maptype\" = \"map-t\" -a -f \"/proc/net/nat46/control\" ]; then\n\t\tproto_init_update \"$link\" 1\n\t\tlocal style=\"MAP\"\n\t\t[ \"$legacymap\" = 1 ] && style=\"MAP0\"\n\n\t\techo add $link > /proc/net/nat46/control\n\t\tlocal cfgstr=\"local.style $style local.v4 $(eval \"echo \\$RULE_${k}_IPV4PREFIX\")/$(eval \"echo \\$RULE_${k}_PREFIX4LEN\")\"\n\t\tcfgstr=\"$cfgstr local.v6 $(eval \"echo \\$RULE_${k}_IPV6PREFIX\")/$(eval \"echo \\$RULE_${k}_PREFIX6LEN\")\"\n\t\tcfgstr=\"$cfgstr local.ea-len $(eval \"echo \\$RULE_${k}_EALEN\") local.psid-offset $(eval \"echo \\$RULE_${k}_OFFSET\")\"\n\t\tcfgstr=\"$cfgstr remote.v4 0.0.0.0/0 remote.v6 $(eval \"echo \\$RULE_${k}_DMR\") remote.style RFC6052 remote.ea-len 0 remote.psid-offset 0\"\n\t\techo config $link $cfgstr > /proc/net/nat46/control\n\n\t\tfor i in $(seq $RULE_COUNT); do\n\t\t\t[ \"$(eval \"echo \\$RULE_${i}_FMR\")\" != 1 ] && continue\n\t\t\tlocal cfgstr=\"remote.style $style remote.v4 $(eval \"echo \\$RULE_${i}_IPV4PREFIX\")/$(eval \"echo \\$RULE_${i}_PREFIX4LEN\")\"\n\t\t\tcfgstr=\"$cfgstr remote.v6 $(eval \"echo \\$RULE_${i}_IPV6PREFIX\")/$(eval \"echo \\$RULE_${i}_PREFIX6LEN\")\"\n\t\t\tcfgstr=\"$cfgstr remote.ea-len $(eval \"echo \\$RULE_${i}_EALEN\") remote.psid-offset $(eval \"echo \\$RULE_${i}_OFFSET\")\"\n\t\t\techo insert $link $cfgstr > /proc/net/nat46/control\n\t\tdone\n\telse\n\t\tproto_notify_error \"$cfg\" \"UNSUPPORTED_TYPE\"\n\t\tproto_block_restart \"$cfg\"\n\tfi\n\n\tproto_add_ipv4_route \"0.0.0.0\" 0\n\tproto_add_data\n\t[ -n \"$zone\" ] && json_add_string zone \"$zone\"\n\n\tjson_add_array firewall\n\t  if [ -z \"$(eval \"echo \\$RULE_${k}_PORTSETS\")\" ]; then\n\t    json_add_object \"\"\n\t      json_add_string type nat\n\t      json_add_string target SNAT\n\t      json_add_string family inet\n\t      json_add_string snat_ip $(eval \"echo \\$RULE_${k}_IPV4ADDR\")\n\t    json_close_object\n\t  else\n\t    for portset in $(eval \"echo \\$RULE_${k}_PORTSETS\"); do\n              for proto in icmp tcp udp; do\n\t        json_add_object \"\"\n\t          json_add_string type nat\n\t          json_add_string target SNAT\n\t          json_add_string family inet\n\t          json_add_string proto \"$proto\"\n                  json_add_boolean connlimit_ports 1\n                  json_add_string snat_ip $(eval \"echo \\$RULE_${k}_IPV4ADDR\")\n                  json_add_string snat_port \"$portset\"\n\t        json_close_object\n              done\n\t    done\n\t  fi\n\t  if [ \"$maptype\" = \"map-t\" ]; then\n\t\t[ -z \"$zone\" ] && zone=$(fw3 -q network $iface 2>/dev/null)\n\n\t\t[ -n \"$zone\" ] && {\n\t\t\tjson_add_object \"\"\n\t\t\t\tjson_add_string type rule\n\t\t\t\tjson_add_string family inet6\n\t\t\t\tjson_add_string proto all\n\t\t\t\tjson_add_string direction in\n\t\t\t\tjson_add_string dest \"$zone\"\n\t\t\t\tjson_add_string src \"$zone\"\n\t\t\t\tjson_add_string src_ip $(eval \"echo \\$RULE_${k}_IPV6ADDR\")\n\t\t\t\tjson_add_string target ACCEPT\n\t\t\tjson_close_object\n\t\t\tjson_add_object \"\"\n\t\t\t\tjson_add_string type rule\n\t\t\t\tjson_add_string family inet6\n\t\t\t\tjson_add_string proto all\n\t\t\t\tjson_add_string direction out\n\t\t\t\tjson_add_string dest \"$zone\"\n\t\t\t\tjson_add_string src \"$zone\"\n\t\t\t\tjson_add_string dest_ip $(eval \"echo \\$RULE_${k}_IPV6ADDR\")\n\t\t\t\tjson_add_string target ACCEPT\n\t\t\tjson_close_object\n\t\t}\n\t\tproto_add_ipv6_route $(eval \"echo \\$RULE_${k}_IPV6ADDR\") 128\n\t  fi\n\tjson_close_array\n\tproto_close_data\n\n\tproto_send_update \"$cfg\"\n\n\tif [ \"$maptype\" = \"lw4o6\" -o \"$maptype\" = \"map-e\" ]; then\n\t\tjson_init\n\t\tjson_add_string name \"${cfg}_\"\n\t\tjson_add_string ifname \"@$(eval \"echo \\$RULE_${k}_PD6IFACE\")\"\n\t\tjson_add_string proto \"static\"\n\t\tjson_add_array ip6addr\n\t\tjson_add_string \"\" \"$(eval \"echo \\$RULE_${k}_IPV6ADDR\")\"\n\t\tjson_close_array\n\t\tjson_close_object\n\t\tubus call network add_dynamic \"$(json_dump)\"\n\tfi\n}\n\nproto_map_teardown() {\n\tlocal cfg=\"$1\"\n\tlocal link=\"map-$cfg\"\n\n\tjson_get_var type type\n\n\t[ -z \"$maptype\" ] && maptype=\"$type\"\n\t[ -z \"$maptype\" ] && maptype=\"map-e\"\n\n\tcase \"$maptype\" in\n\t\t\"map-e\"|\"lw4o6\") ifdown \"${cfg}_\" ;;\n\t\t\"map-t\") [ -f \"/proc/net/nat46/control\" ] && echo del $link > /proc/net/nat46/control ;;\n\tesac\n\n\trm -f /tmp/map-$cfg.rules\n}\n\nproto_map_init_config() {\n\tno_device=1\n\tavailable=1\n\n\tproto_config_add_string \"maptype\"\n\tproto_config_add_string \"rule\"\n\tproto_config_add_string \"ipaddr\"\n\tproto_config_add_int \"ip4prefixlen\"\n\tproto_config_add_string \"ip6prefix\"\n\tproto_config_add_int \"ip6prefixlen\"\n\tproto_config_add_string \"peeraddr\"\n\tproto_config_add_int \"ealen\"\n\tproto_config_add_int \"psidlen\"\n\tproto_config_add_int \"psid\"\n\tproto_config_add_int \"offset\"\n\tproto_config_add_boolean \"legacymap\"\n\n\tproto_config_add_string \"tunlink\"\n\tproto_config_add_int \"mtu\"\n\tproto_config_add_int \"ttl\"\n\tproto_config_add_string \"zone\"\n\tproto_config_add_string \"encaplimit\"\n}\n\n[ -n \"$INCLUDE_ONLY\" ] || {\n        add_protocol map\n}\n"
  },
  {
    "path": "package/network/ipv6/map/src/CMakeLists.txt",
    "content": "cmake_minimum_required(VERSION 2.8.1)\n\nproject(mapcalc C)\n\nset(CMAKE_SHARED_LIBRARY_LINK_C_FLAGS \"\")\nset(CMAKE_C_FLAGS \"${CMAKE_C_FLAGS} -g -std=c99\")\n\nFIND_PATH(ubus_include_dir libubus.h)\nINCLUDE_DIRECTORIES(${ubus_include_dir})\n\nadd_definitions(-D_GNU_SOURCE -Wall -Wno-gnu -Wextra)\n\nadd_executable(mapcalc mapcalc.c)\ntarget_link_libraries(mapcalc ubus ubox)\n\ninstall(TARGETS mapcalc DESTINATION sbin/)\n\n\n# Packaging rules\nset(CPACK_PACKAGE_VERSION \"1\")\nset(CPACK_PACKAGE_CONTACT \"Steven Barth <steven@midlink.org>\")\nset(CPACK_PACKAGE_DESCRIPTION_SUMMARY \"hnetd\")\nset(CPACK_GENERATOR \"DEB;RPM;STGZ\")\nset(CPACK_STRIP_FILES true)\n\nSET(CPACK_DEBIAN_PACKAGE_VERSION ${CPACK_PACKAGE_VERSION})\nset(CPACK_PACKAGE_FILE_NAME \"${PROJECT_NAME}_${CPACK_DEBIAN_PACKAGE_VERSION}\")\n\ninclude(CPack)\n"
  },
  {
    "path": "package/network/ipv6/map/src/mapcalc.c",
    "content": "/*\n * mapcalc - MAP parameter calculation\n *\n * Author: Steven Barth <cyrus@openwrt.org>\n * Copyright (c) 2014-2015 cisco Systems, Inc.\n * Copyright (c) 2015 Steven Barth <cyrus@openwrt.org>\n * Copyright (c) 2018 Hans Dedecker <dedeckeh@gmail.com>\n *\n * This program is free software; you can redistribute it and/or modify\n * it under the terms of the GNU General Public License version 2\n * as published by the Free Software Foundation\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n * GNU General Public License for more details.\n */\n\n#include <stdlib.h>\n#include <stdio.h>\n#include <arpa/inet.h>\n#include <errno.h>\n#include <libubus.h>\n#include <libubox/utils.h>\n\n\nstruct blob_attr *dump = NULL;\n\nenum {\n\tDUMP_ATTR_INTERFACE,\n\tDUMP_ATTR_MAX\n};\n\nstatic const struct blobmsg_policy dump_attrs[DUMP_ATTR_MAX] = {\n\t[DUMP_ATTR_INTERFACE] = { .name = \"interface\", .type = BLOBMSG_TYPE_ARRAY },\n};\n\n\nenum {\n\tIFACE_ATTR_INTERFACE,\n\tIFACE_ATTR_PREFIX,\n\tIFACE_ATTR_ADDRESS,\n\tIFACE_ATTR_MAX,\n};\n\nstatic const struct blobmsg_policy iface_attrs[IFACE_ATTR_MAX] = {\n\t[IFACE_ATTR_INTERFACE] = { .name = \"interface\", .type = BLOBMSG_TYPE_STRING },\n\t[IFACE_ATTR_PREFIX] = { .name = \"ipv6-prefix\", .type = BLOBMSG_TYPE_ARRAY },\n\t[IFACE_ATTR_ADDRESS] = { .name = \"ipv6-address\", .type = BLOBMSG_TYPE_ARRAY },\n};\n\n\nenum {\n\tPREFIX_ATTR_ADDRESS,\n\tPREFIX_ATTR_MASK,\n\tPREFIX_ATTR_MAX,\n};\n\nstatic const struct blobmsg_policy prefix_attrs[PREFIX_ATTR_MAX] = {\n\t[PREFIX_ATTR_ADDRESS] = { .name = \"address\", .type = BLOBMSG_TYPE_STRING },\n\t[PREFIX_ATTR_MASK] = { .name = \"mask\", .type = BLOBMSG_TYPE_INT32 },\n};\n\nstatic int bmemcmp(const void *av, const void *bv, size_t bits)\n{\n\tconst uint8_t *a = av, *b = bv;\n\tsize_t bytes = bits / 8;\n\tbits %= 8;\n\n\tint res = memcmp(a, b, bytes);\n\tif (res == 0 && bits > 0)\n\t\tres = (a[bytes] >> (8 - bits)) - (b[bytes] >> (8 - bits));\n\n\treturn res;\n}\n\nstatic void bmemcpy(void *av, const void *bv, size_t bits)\n{\n\tuint8_t *a = av;\n\tconst uint8_t *b = bv;\n\n\tsize_t bytes = bits / 8;\n\tbits %= 8;\n\tmemcpy(a, b, bytes);\n\n\tif (bits > 0) {\n\t\tuint8_t mask = (1 << (8 - bits)) - 1;\n\t\ta[bytes] = (a[bytes] & mask) | ((~mask) & b[bytes]);\n\t}\n}\n\nstatic void bmemcpys64(void *av, const void *bv, size_t frombits, size_t nbits)\n{\n\tuint64_t buf = 0;\n\tconst uint8_t *b = bv;\n\tsize_t frombyte = frombits / 8, tobyte = (frombits + nbits) / 8;\n\n\tmemcpy(&buf, &b[frombyte], tobyte - frombyte + 1);\n\tbuf = cpu_to_be64(be64_to_cpu(buf) << (frombits % 8));\n\n\tbmemcpy(av, &buf, nbits);\n}\n\nstatic void handle_dump(struct ubus_request *req __attribute__((unused)),\n\t\tint type __attribute__((unused)), struct blob_attr *msg)\n{\n\tstruct blob_attr *tb[DUMP_ATTR_INTERFACE];\n\tblobmsg_parse(dump_attrs, DUMP_ATTR_MAX, tb, blob_data(msg), blob_len(msg));\n\n\tif (!tb[DUMP_ATTR_INTERFACE])\n\t\treturn;\n\n\tdump = blob_memdup(tb[DUMP_ATTR_INTERFACE]);\n}\n\nstatic void match_prefix(int *pdlen, struct in6_addr *pd, struct blob_attr *cur,\n\t\tconst struct in6_addr *ipv6prefix, int prefix6len, bool lw4o6)\n{\n\tstruct blob_attr *d;\n\tunsigned drem;\n\n\tif (!cur || blobmsg_type(cur) != BLOBMSG_TYPE_ARRAY || !blobmsg_check_attr(cur, false))\n\t\treturn;\n\n\tblobmsg_for_each_attr(d, cur, drem) {\n\t\tstruct blob_attr *ptb[PREFIX_ATTR_MAX];\n\t\tblobmsg_parse(prefix_attrs, PREFIX_ATTR_MAX, ptb,\n\t\t\t\tblobmsg_data(d), blobmsg_data_len(d));\n\n\t\tif (!ptb[PREFIX_ATTR_ADDRESS] || !ptb[PREFIX_ATTR_MASK])\n\t\t\tcontinue;\n\n\t\tstruct in6_addr prefix = IN6ADDR_ANY_INIT;\n\t\tint mask = blobmsg_get_u32(ptb[PREFIX_ATTR_MASK]);\n\t\tinet_pton(AF_INET6, blobmsg_get_string(ptb[PREFIX_ATTR_ADDRESS]), &prefix);\n\n\t\t// lw4over6 /128-address-as-PD matching madness workaround\n\t\tif (lw4o6 && mask == 128)\n\t\t\tmask = 64;\n\n\t\tif (*pdlen < mask && mask >= prefix6len &&\n\t\t\t\t!bmemcmp(&prefix, ipv6prefix, prefix6len)) {\n\t\t\tbmemcpy(pd, &prefix, mask);\n\t\t\t*pdlen = mask;\n\t\t} else if (lw4o6 && *pdlen < prefix6len && mask < prefix6len &&\n\t\t\t\t!bmemcmp(&prefix, ipv6prefix, mask)) {\n\t\t\tbmemcpy(pd, ipv6prefix, prefix6len);\n\t\t\t*pdlen = prefix6len;\n\t\t}\n\t}\n}\n\nenum {\n\tOPT_TYPE,\n\tOPT_FMR,\n\tOPT_EALEN,\n\tOPT_PREFIX4LEN,\n\tOPT_PREFIX6LEN,\n\tOPT_IPV6PREFIX,\n\tOPT_IPV4PREFIX,\n\tOPT_OFFSET,\n\tOPT_PSIDLEN,\n\tOPT_PSID,\n\tOPT_BR,\n\tOPT_DMR,\n\tOPT_PD,\n\tOPT_PDLEN,\n\tOPT_MAX\n};\n\nstatic char *const token[] = {\n\t[OPT_TYPE] = \"type\",\n\t[OPT_FMR] = \"fmr\",\n\t[OPT_EALEN] = \"ealen\",\n\t[OPT_PREFIX4LEN] = \"prefix4len\",\n\t[OPT_PREFIX6LEN] = \"prefix6len\",\n\t[OPT_IPV6PREFIX] = \"ipv6prefix\",\n\t[OPT_IPV4PREFIX] = \"ipv4prefix\",\n\t[OPT_OFFSET] = \"offset\",\n\t[OPT_PSIDLEN] = \"psidlen\",\n\t[OPT_PSID] = \"psid\",\n\t[OPT_BR] = \"br\",\n\t[OPT_DMR] = \"dmr\",\n\t[OPT_PD] = \"pd\",\n\t[OPT_PDLEN] = \"pdlen\",\n\t[OPT_MAX] = NULL\n};\n\n\nint main(int argc, char *argv[])\n{\n\tint status = 0;\n\tconst char *iface = argv[1];\n\n\tconst char *legacy_env = getenv(\"LEGACY\");\n\tbool legacy = legacy_env && atoi(legacy_env);\n\n\n\tif (argc < 3) {\n\t\tfprintf(stderr, \"Usage: %s <interface|*> <rule1> [rule2] [...]\\n\", argv[0]);\n\t\treturn 1;\n\t}\n\n\tuint32_t network_interface;\n\tstruct ubus_context *ubus = ubus_connect(NULL);\n\tif (ubus) {\n\t\tubus_lookup_id(ubus, \"network.interface\", &network_interface);\n\t\tubus_invoke(ubus, network_interface, \"dump\", NULL, handle_dump, NULL, 5000);\n\t}\n\n\tint rulecnt = 0;\n\tfor (int i = 2; i < argc; ++i) {\n\t\tbool lw4o6 = false;\n\t\tbool fmr = false;\n\t\tint ealen = -1;\n\t\tint addr4len = 32;\n\t\tint prefix4len = 32;\n\t\tint prefix6len = -1;\n\t\tint pdlen = -1;\n\t\tstruct in_addr ipv4prefix = {INADDR_ANY};\n\t\tstruct in_addr ipv4addr = {INADDR_ANY};\n\t\tstruct in6_addr ipv6addr = IN6ADDR_ANY_INIT;\n\t\tstruct in6_addr ipv6prefix = IN6ADDR_ANY_INIT;\n\t\tstruct in6_addr pd = IN6ADDR_ANY_INIT;\n\t\tint offset = -1;\n\t\tint psidlen = -1;\n\t\tint psid = -1;\n\t\tuint16_t psid16 = 0;\n\t\tconst char *dmr = NULL;\n\t\tconst char *br = NULL;\n\n\t\tfor (char *rule = strdup(argv[i]); *rule; ) {\n\t\t\tchar *value;\n\t\t\tint intval;\n\t\t\tint idx = getsubopt(&rule, token, &value);\n\t\t\terrno = 0;\n\n\t\t\tif (idx == OPT_TYPE) {\n\t\t\t\tlw4o6 = (value && !strcmp(value, \"lw4o6\"));\n\t\t\t} else if (idx == OPT_FMR) {\n\t\t\t\tfmr = true;\n\t\t\t} else if (idx == OPT_EALEN && (intval = strtoul(value, NULL, 0)) <= 48 && !errno) {\n\t\t\t\tealen = intval;\n\t\t\t} else if (idx == OPT_PREFIX4LEN && (intval = strtoul(value, NULL, 0)) <= 32 && !errno) {\n\t\t\t\tprefix4len = intval;\n\t\t\t} else if (idx == OPT_PREFIX6LEN && (intval = strtoul(value, NULL, 0)) <= 128 && !errno) {\n\t\t\t\tprefix6len = intval;\n\t\t\t} else if (idx == OPT_IPV4PREFIX && inet_pton(AF_INET, value, &ipv4prefix) == 1) {\n\t\t\t\t// dummy\n\t\t\t} else if (idx == OPT_IPV6PREFIX && inet_pton(AF_INET6, value, &ipv6prefix) == 1) {\n\t\t\t\t// dummy\n\t\t\t} else if (idx == OPT_PD && inet_pton(AF_INET6, value, &pd) == 1) {\n\t\t\t\t// dummy\n\t\t\t} else if (idx == OPT_OFFSET && (intval = strtoul(value, NULL, 0)) <= 16 && !errno) {\n\t\t\t\toffset = intval;\n\t\t\t} else if (idx == OPT_PSIDLEN && (intval = strtoul(value, NULL, 0)) <= 16 && !errno) {\n\t\t\t\tpsidlen = intval;\n\t\t\t} else if (idx == OPT_PDLEN && (intval = strtoul(value, NULL, 0)) <= 128 && !errno) {\n\t\t\t\tpdlen = intval;\n\t\t\t} else if (idx == OPT_PSID && (intval = strtoul(value, NULL, 0)) <= 65535 && !errno) {\n\t\t\t\tpsid = intval;\n\t\t\t} else if (idx == OPT_DMR) {\n\t\t\t\tdmr = value;\n\t\t\t} else if (idx == OPT_BR) {\n\t\t\t\tbr = value;\n\t\t\t} else {\n\t\t\t\tif (idx == -1 || idx >= OPT_MAX)\n\t\t\t\t\tfprintf(stderr, \"Skipped invalid option: %s\\n\", value);\n\t\t\t\telse\n\t\t\t\t\tfprintf(stderr, \"Skipped invalid value %s for option %s\\n\",\n\t\t\t\t\t\t\tvalue, token[idx]);\n\t\t\t}\n\t\t}\n\n\t\tif (offset < 0)\n\t\t\toffset = (lw4o6) ? 0 : (legacy) ? 4 : 6;\n\n\t\t// LW4over6 doesn't have an EALEN and has no psid-autodetect\n\t\tif (lw4o6) {\n\t\t\tif (psidlen < 0)\n\t\t\t\tpsidlen = 0;\n\n\t\t\tealen = psidlen;\n\t\t}\n\n\t\t// Find PD\n\t\tif (pdlen < 0) {\n\t\t\tstruct blob_attr *c;\n\t\t\tunsigned rem;\n\t\t\tblobmsg_for_each_attr(c, dump, rem) {\n\t\t\t\tstruct blob_attr *tb[IFACE_ATTR_MAX];\n\t\t\t\tblobmsg_parse(iface_attrs, IFACE_ATTR_MAX, tb, blobmsg_data(c), blobmsg_data_len(c));\n\n\t\t\t\tif (!tb[IFACE_ATTR_INTERFACE] || (strcmp(argv[1], \"*\") && strcmp(argv[1],\n\t\t\t\t\t\tblobmsg_get_string(tb[IFACE_ATTR_INTERFACE]))))\n\t\t\t\t\tcontinue;\n\n\t\t\t\tmatch_prefix(&pdlen, &pd, tb[IFACE_ATTR_PREFIX], &ipv6prefix, prefix6len, lw4o6);\n\n\t\t\t\tif (lw4o6)\n\t\t\t\t\tmatch_prefix(&pdlen, &pd, tb[IFACE_ATTR_ADDRESS], &ipv6prefix, prefix6len, lw4o6);\n\n\t\t\t\tif (pdlen >= 0) {\n\t\t\t\t\tiface = blobmsg_get_string(tb[IFACE_ATTR_INTERFACE]);\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n\t\tif (ealen < 0 && pdlen >= 0)\n\t\t\tealen = pdlen - prefix6len;\n\n\t\tif (psidlen <= 0) {\n\t\t\tpsidlen = ealen - (32 - prefix4len);\n\t\t\tif (psidlen < 0)\n\t\t\t\tpsidlen = 0;\n\n\t\t\tpsid = -1;\n\t\t}\n\n\t\tif (prefix4len < 0 || prefix6len < 0 || ealen < 0 || psidlen > 16 || ealen < psidlen) {\n\t\t\tfprintf(stderr, \"Skipping invalid or incomplete rule: %s\\n\", argv[i]);\n\t\t\tstatus = 1;\n\t\t\tcontinue;\n\t\t}\n\n\t\tif (psid < 0 && psidlen >= 0 && pdlen >= 0) {\n\t\t\tbmemcpys64(&psid16, &pd, prefix6len + ealen - psidlen, psidlen);\n\t\t\tpsid = be16_to_cpu(psid16);\n\t\t}\n\n\t\tif (psidlen > 0) {\n\t\t\tpsid = psid >> (16 - psidlen);\n\t\t\tpsid16 = cpu_to_be16(psid);\n\t\t\tpsid = psid << (16 - psidlen);\n\t\t}\n\n\t\tif (pdlen >= 0 || ealen == psidlen) {\n\t\t\tbmemcpys64(&ipv4addr, &pd, prefix6len, ealen - psidlen);\n\t\t\tipv4addr.s_addr = htonl(ntohl(ipv4addr.s_addr) >> prefix4len);\n\t\t\tbmemcpy(&ipv4addr, &ipv4prefix, prefix4len);\n\n\t\t\tif (prefix4len + ealen < 32)\n\t\t\t\taddr4len = prefix4len + ealen;\n\t\t}\n\n\t\tif (pdlen < 0 && !fmr) {\n\t\t\tfprintf(stderr, \"Skipping non-FMR without matching PD: %s\\n\", argv[i]);\n\t\t\tstatus = 1;\n\t\t\tcontinue;\n\t\t} else if (pdlen >= 0) {\n\t\t\tsize_t v4offset = (legacy) ? 9 : 10;\n\t\t\tmemcpy(&ipv6addr.s6_addr[v4offset], &ipv4addr, 4);\n\t\t\tmemcpy(&ipv6addr.s6_addr[v4offset + 4], &psid16, 2);\n\t\t\tbmemcpy(&ipv6addr, &pd, pdlen);\n\t\t}\n\n\t\t++rulecnt;\n\t\tchar ipv4addrbuf[INET_ADDRSTRLEN];\n\t\tchar ipv4prefixbuf[INET_ADDRSTRLEN];\n\t\tchar ipv6prefixbuf[INET6_ADDRSTRLEN];\n\t\tchar ipv6addrbuf[INET6_ADDRSTRLEN];\n\t\tchar pdbuf[INET6_ADDRSTRLEN];\n\n\t\tinet_ntop(AF_INET, &ipv4addr, ipv4addrbuf, sizeof(ipv4addrbuf));\n\t\tinet_ntop(AF_INET, &ipv4prefix, ipv4prefixbuf, sizeof(ipv4prefixbuf));\n\t\tinet_ntop(AF_INET6, &ipv6prefix, ipv6prefixbuf, sizeof(ipv6prefixbuf));\n\t\tinet_ntop(AF_INET6, &ipv6addr, ipv6addrbuf, sizeof(ipv6addrbuf));\n\t\tinet_ntop(AF_INET6, &pd, pdbuf, sizeof(pdbuf));\n\n\t\tprintf(\"RULE_%d_FMR=%d\\n\", rulecnt, fmr);\n\t\tprintf(\"RULE_%d_EALEN=%d\\n\", rulecnt, ealen);\n\t\tprintf(\"RULE_%d_PSIDLEN=%d\\n\", rulecnt, psidlen);\n\t\tprintf(\"RULE_%d_OFFSET=%d\\n\", rulecnt, offset);\n\t\tprintf(\"RULE_%d_PREFIX4LEN=%d\\n\", rulecnt, prefix4len);\n\t\tprintf(\"RULE_%d_PREFIX6LEN=%d\\n\", rulecnt, prefix6len);\n\t\tprintf(\"RULE_%d_IPV4PREFIX=%s\\n\", rulecnt, ipv4prefixbuf);\n\t\tprintf(\"RULE_%d_IPV6PREFIX=%s\\n\", rulecnt, ipv6prefixbuf);\n\n\t\tif (pdlen >= 0) {\n\t\t\tprintf(\"RULE_%d_IPV6PD=%s\\n\", rulecnt, pdbuf);\n\t\t\tprintf(\"RULE_%d_PD6LEN=%d\\n\", rulecnt, pdlen);\n\t\t\tprintf(\"RULE_%d_PD6IFACE=%s\\n\", rulecnt, iface);\n\t\t\tprintf(\"RULE_%d_IPV6ADDR=%s\\n\", rulecnt, ipv6addrbuf);\n\t\t\tprintf(\"RULE_BMR=%d\\n\", rulecnt);\n\t\t}\n\n\t\tif (ipv4addr.s_addr) {\n\t\t\tprintf(\"RULE_%d_IPV4ADDR=%s\\n\", rulecnt, ipv4addrbuf);\n\t\t\tprintf(\"RULE_%d_ADDR4LEN=%d\\n\", rulecnt, addr4len);\n\t\t}\n\n\n\t\tif (psidlen > 0 && psid >= 0) {\n\t\t\tprintf(\"RULE_%d_PORTSETS='\", rulecnt);\n\t\t\tfor (int k = (offset) ? 1 : 0; k < (1 << offset); ++k) {\n\t\t\t\tint start = (k << (16 - offset)) | (psid >> offset);\n\t\t\t\tint end = start + (1 << (16 - offset - psidlen)) - 1;\n\n\t\t\t\tif (start == 0)\n\t\t\t\t\tstart = 1;\n\n\t\t\t\tif (start <= end)\n\t\t\t\t\tprintf(\"%d-%d \", start, end);\n\t\t\t}\n\t\t\tprintf(\"'\\n\");\n\t\t}\n\n\t\tif (dmr)\n\t\t\tprintf(\"RULE_%d_DMR=%s\\n\", rulecnt, dmr);\n\n\t\tif (br)\n\t\t\tprintf(\"RULE_%d_BR=%s\\n\", rulecnt, br);\n\t}\n\n\tprintf(\"RULE_COUNT=%d\\n\", rulecnt);\n\treturn status;\n}\n"
  },
  {
    "path": "package/network/ipv6/odhcp6c/Makefile",
    "content": "#\n# Copyright (C) 2012-2015 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=odhcp6c\nPKG_RELEASE:=18\n\nPKG_SOURCE_PROTO:=git\nPKG_SOURCE_URL=$(PROJECT_GIT)/project/odhcp6c.git\nPKG_SOURCE_DATE:=2021-12-05\nPKG_SOURCE_VERSION:=39b584bcac8770619b545d6ae344758f87028612\nPKG_MIRROR_HASH:=f2092bd3ff3481f842da6735f8e36e237e163e8b7cdec80a17385c31e064c8f0\nPKG_MAINTAINER:=Hans Dedecker <dedeckeh@gmail.com>\nPKG_LICENSE:=GPL-2.0\n\ninclude $(INCLUDE_DIR)/package.mk\ninclude $(INCLUDE_DIR)/cmake.mk\n\nCMAKE_OPTIONS += \\\n\t-DUSE_LIBUBOX=on\n\nifneq ($(CONFIG_PACKAGE_odhcp6c_ext_cer_id),0)\n  CMAKE_OPTIONS += -DEXT_CER_ID=$(CONFIG_PACKAGE_odhcp6c_ext_cer_id)\nendif\n\ndefine Package/odhcp6c\n  SECTION:=net\n  CATEGORY:=Network\n  TITLE:=Embedded DHCPv6-client for OpenWrt\n  DEPENDS:=@IPV6 +libubox\nendef\n\ndefine Package/odhcp6c/config\n  config PACKAGE_odhcp6c_ext_cer_id\n    int \"CER-ID Extension ID (0 = disabled)\"\n    depends on PACKAGE_odhcp6c\n    default 0\nendef\n\ndefine Package/odhcp6c/conffiles\n/etc/odhcp6c.user\n/etc/odhcp6c.user.d/\nendef\n\ndefine Package/odhcp6c/install\n\t$(INSTALL_DIR) $(1)/usr/sbin/\n\t$(INSTALL_BIN) $(PKG_BUILD_DIR)/odhcp6c $(1)/usr/sbin/\n\t$(INSTALL_DIR) $(1)/lib/netifd/proto\n\t$(INSTALL_BIN) ./files/dhcpv6.sh $(1)/lib/netifd/proto/dhcpv6.sh\n\t$(INSTALL_BIN) ./files/dhcpv6.script $(1)/lib/netifd/\n\t$(INSTALL_DIR) $(1)/etc/odhcp6c.user.d/\n\t$(INSTALL_CONF) ./files/odhcp6c.user $(1)/etc/\nendef\n\n$(eval $(call BuildPackage,odhcp6c))\n"
  },
  {
    "path": "package/network/ipv6/odhcp6c/files/dhcpv6.script",
    "content": "#!/bin/sh\n[ -z \"$2\" ] && echo \"Error: should be run by odhcpc6c\" && exit 1\n. /lib/functions.sh\n. /lib/netifd/netifd-proto.sh\n\nsetup_interface () {\n\tlocal device=\"$1\"\n\tlocal prefsig=\"\"\n\tlocal addrsig=\"\"\n\n\t# Apply IPv6 / ND configuration\n\tHOPLIMIT=$(cat /proc/sys/net/ipv6/conf/$device/hop_limit)\n\t[ -n \"$RA_HOPLIMIT\" -a -n \"$HOPLIMIT\" ] && [ \"$RA_HOPLIMIT\" -gt \"$HOPLIMIT\" ] && echo \"$RA_HOPLIMIT\" > /proc/sys/net/ipv6/conf/$device/hop_limit\n\t[ -n \"$RA_MTU\" ] && [ \"$RA_MTU\" -ge 1280 ] && echo \"$RA_MTU\" > /proc/sys/net/ipv6/conf/$device/mtu 2>/dev/null\n\t[ -n \"$RA_REACHABLE\" ] && [ \"$RA_REACHABLE\" -gt 0 ] && echo \"$RA_REACHABLE\" > /proc/sys/net/ipv6/neigh/$device/base_reachable_time_ms\n\t[ -n \"$RA_RETRANSMIT\" ] && [ \"$RA_RETRANSMIT\" -gt 0 ] && echo \"$RA_RETRANSMIT\" > /proc/sys/net/ipv6/neigh/$device/retrans_time_ms\n\n\tproto_init_update \"*\" 1\n\n\t# Merge RA-DNS\n\tfor radns in $RA_DNS; do\n\t\tlocal duplicate=0\n\t\tfor dns in $RDNSS; do\n\t\t\t[ \"$radns\" = \"$dns\" ] && duplicate=1\n\t\tdone\n\t\t[ \"$duplicate\" = 0 ] && RDNSS=\"$RDNSS $radns\"\n\tdone\n\n\tfor dns in $RDNSS; do\n\t\tproto_add_dns_server \"$dns\"\n\tdone\n\n\tfor radomain in $RA_DOMAINS; do\n\t\tlocal duplicate=0\n\t\tfor domain in $DOMAINS; do\n\t\t\t[ \"$radomain\" = \"$domain\" ] && duplicate=1\n\t\tdone\n\t\t[ \"$duplicate\" = 0 ] && DOMAINS=\"$DOMAINS $radomain\"\n\tdone\n\n\tfor domain in $DOMAINS; do\n\t\tproto_add_dns_search \"$domain\"\n\tdone\n\n\tfor prefix in $PREFIXES; do\n\t\tproto_add_ipv6_prefix \"$prefix\"\n\t\tprefsig=\"$prefsig ${prefix%%,*}\"\n\t\tlocal entry=\"${prefix#*/}\"\n\t\tentry=\"${entry#*,}\"\n\t\tentry=\"${entry#*,}\"\n\t\tlocal valid=\"${entry%%,*}\"\n\n\t\tif [ -z \"$RA_ADDRESSES\" -a -z \"$RA_ROUTES\" -a \\\n\t\t\t\t-z \"$RA_DNS\" -a \"$FAKE_ROUTES\" = 1 ]; then\n\t\t\tRA_ROUTES=\"::/0,$SERVER,$valid,4096\"\n\t\tfi\n\tdone\n\n\tfor prefix in $USERPREFIX; do\n\t\tproto_add_ipv6_prefix \"$prefix\"\n\tdone\n\n\t# Merge addresses\n\tfor entry in $RA_ADDRESSES; do\n\t\tlocal duplicate=0\n\t\tlocal addr=\"${entry%%/*}\"\n\t\tfor dentry in $ADDRESSES; do\n\t\t\tlocal daddr=\"${dentry%%/*}\"\n\t\t\t[ \"$addr\" = \"$daddr\" ] && duplicate=1\n\t\tdone\n\t\t[ \"$duplicate\" = \"0\" ] && ADDRESSES=\"$ADDRESSES $entry\"\n\tdone\n\n\tfor entry in $ADDRESSES; do\n\t\tlocal addr=\"${entry%%/*}\"\n\t\tentry=\"${entry#*/}\"\n\t\tlocal mask=\"${entry%%,*}\"\n\t\tentry=\"${entry#*,}\"\n\t\tlocal preferred=\"${entry%%,*}\"\n\t\tentry=\"${entry#*,}\"\n\t\tlocal valid=\"${entry%%,*}\"\n\n\t\tproto_add_ipv6_address \"$addr\" \"$mask\" \"$preferred\" \"$valid\" 1\n\t\taddrsig=\"$addrsig $addr/$mask\"\n\n\t\tif [ -z \"$RA_ADDRESSES\" -a -z \"$RA_ROUTES\" -a \\\n\t\t\t\t-z \"$RA_DNS\" -a \"$FAKE_ROUTES\" = 1 ]; then\n\t\t\tRA_ROUTES=\"::/0,$SERVER,$valid,4096\"\n\t\tfi\n\n\t\t# RFC 7278\n\t\tif [ \"$mask\" -eq 64 -a -z \"$PREFIXES\" -a -n \"$EXTENDPREFIX\" ]; then\n\t\t\tproto_add_ipv6_prefix \"$addr/$mask,$preferred,$valid\"\n\n\t\t\tlocal raroutes=\"\"\n\t\t\tfor route in $RA_ROUTES; do\n\t\t\t\tlocal prefix=\"${route%%/*}\"\n\t\t\t\tlocal entry=\"${route#*/}\"\n\t\t\t\tlocal pmask=\"${entry%%,*}\"\n\t\t\t\tentry=\"${entry#*,}\"\n\t\t\t\tlocal gw=\"${entry%%,*}\"\n\n\t\t\t\t[ -z \"$gw\" -a \"$mask\" = \"$pmask\" ] && {\n\t\t\t\t\tcase \"$addr\" in\n\t\t\t\t\t\t\"${prefix%*::}\"*) continue;;\n\t\t\t\t\tesac\n\t\t\t\t}\n\t\t\t\traroutes=\"$raroutes $route\"\n\t\t\tdone\n\t\t\tRA_ROUTES=\"$raroutes\"\n\t\tfi\n\tdone\n\n\tfor entry in $RA_ROUTES; do\n\t\tlocal duplicate=$NOSOURCEFILTER\n\t\tlocal addr=\"${entry%%/*}\"\n\t\tentry=\"${entry#*/}\"\n\t\tlocal mask=\"${entry%%,*}\"\n\t\tentry=\"${entry#*,}\"\n\t\tlocal gw=\"${entry%%,*}\"\n\t\tentry=\"${entry#*,}\"\n\t\tlocal valid=\"${entry%%,*}\"\n\t\tentry=\"${entry#*,}\"\n\t\tlocal metric=\"${entry%%,*}\"\n\n\t\tfor xentry in $RA_ROUTES; do\n\t\t\tlocal xprefix=\"${xentry%%,*}\"\n\t\t\txentry=\"${xentry#*,}\"\n\t\t\tlocal xgw=\"${xentry%%,*}\"\n\n\t\t\t[ -n \"$gw\" -a -z \"$xgw\" -a \"$addr/$mask\" = \"$xprefix\" ] && duplicate=1\n\t\tdone\n\n\t\tif [ -z \"$gw\" -o \"$duplicate\" = 1 ]; then\n\t\t\tproto_add_ipv6_route \"$addr\" \"$mask\" \"$gw\" \"$metric\" \"$valid\"\n\t\telse\n\t\t\tfor prefix in $PREFIXES $ADDRESSES; do\n\t\t\t\tlocal paddr=\"${prefix%%,*}\"\n\t\t\t\tproto_add_ipv6_route \"$addr\" \"$mask\" \"$gw\" \"$metric\" \"$valid\" \"$paddr\"\n\t\t\tdone\n\t\tfi\n\tdone\n\n\tproto_add_data\n\t[ -n \"$CER\" ] && json_add_string cer \"$CER\"\n\t[ -n \"$PASSTHRU\" ] && json_add_string passthru \"$PASSTHRU\"\n\t[ -n \"$ZONE\" ] && json_add_string zone \"$ZONE\"\n\tproto_close_data\n\n\tproto_send_update \"$INTERFACE\"\n\n\tMAPTYPE=\"\"\n\tMAPRULE=\"\"\n\n\tif [ -n \"$MAPE\" -a -f /lib/netifd/proto/map.sh ]; then\n\t\tMAPTYPE=\"map-e\"\n\t\tMAPRULE=\"$MAPE\"\n\telif [ -n \"$MAPT\" -a -f /lib/netifd/proto/map.sh -a -f /proc/net/nat46/control ]; then\n\t\tMAPTYPE=\"map-t\"\n\t\tMAPRULE=\"$MAPT\"\n\telif [ -n \"$LW4O6\" -a -f /lib/netifd/proto/map.sh ]; then\n\t\tMAPTYPE=\"lw4o6\"\n\t\tMAPRULE=\"$LW4O6\"\n\tfi\n\n\t[ -n \"$ZONE\" ] || ZONE=$(fw3 -q network $INTERFACE 2>/dev/null)\n\n\tif [ \"$IFACE_MAP\" != 0 -a -n \"$MAPTYPE\" -a -n \"$MAPRULE\" ]; then\n\t\t[ -z \"$IFACE_MAP\" -o \"$IFACE_MAP\" = 1 ] && IFACE_MAP=${INTERFACE}_4\n\t\tjson_init\n\t\tjson_add_string name \"$IFACE_MAP\"\n\t\tjson_add_string ifname \"@$INTERFACE\"\n\t\tjson_add_string proto map\n\t\tjson_add_string type \"$MAPTYPE\"\n\t\tjson_add_string _prefsig \"$prefsig\"\n\t\t[ \"$MAPTYPE\" = lw4o6 ] && json_add_string _addrsig \"$addrsig\"\n\t\tjson_add_string rule \"$MAPRULE\"\n\t\tjson_add_string tunlink \"$INTERFACE\"\n\t\t[ -n \"$ZONE_MAP\" ] || ZONE_MAP=$ZONE\n\t\t[ -n \"$ZONE_MAP\" ] && json_add_string zone \"$ZONE_MAP\"\n\t\t[ -n \"$ENCAPLIMIT_MAP\" ] && json_add_string encaplimit \"$ENCAPLIMIT_MAP\"\n\t\t[ -n \"$IFACE_MAP_DELEGATE\" ] && json_add_boolean delegate \"$IFACE_MAP_DELEGATE\"\n\t\tjson_close_object\n\t\tubus call network add_dynamic \"$(json_dump)\"\n\telif [ -n \"$AFTR\" -a \"$IFACE_DSLITE\" != 0 -a -f /lib/netifd/proto/dslite.sh ]; then\n\t\t[ -z \"$IFACE_DSLITE\" -o \"$IFACE_DSLITE\" = 1 ] && IFACE_DSLITE=${INTERFACE}_4\n\t\tjson_init\n\t\tjson_add_string name \"$IFACE_DSLITE\"\n\t\tjson_add_string ifname \"@$INTERFACE\"\n\t\tjson_add_string proto \"dslite\"\n\t\tjson_add_string peeraddr \"$AFTR\"\n\t\tjson_add_string tunlink \"$INTERFACE\"\n\t\t[ -n \"$ZONE_DSLITE\" ] || ZONE_DSLITE=$ZONE\n\t\t[ -n \"$ZONE_DSLITE\" ] && json_add_string zone \"$ZONE_DSLITE\"\n\t\t[ -n \"$ENCAPLIMIT_DSLITE\" ] && json_add_string encaplimit \"$ENCAPLIMIT_DSLITE\"\n\t\t[ -n \"$IFACE_DSLITE_DELEGATE\" ] && json_add_boolean delegate \"$IFACE_DSLITE_DELEGATE\"\n\t\tjson_close_object\n\t\tubus call network add_dynamic \"$(json_dump)\"\n\telif [ \"$IFACE_464XLAT\" != 0 -a -f /lib/netifd/proto/464xlat.sh ]; then\n\t\t[ -z \"$IFACE_464XLAT\" -o \"$IFACE_464XLAT\" = 1 ] && IFACE_464XLAT=${INTERFACE}_4\n\t\tjson_init\n\t\tjson_add_string name \"$IFACE_464XLAT\"\n\t\tjson_add_string ifname \"@$INTERFACE\"\n\t\tjson_add_string proto \"464xlat\"\n\t\tjson_add_string tunlink \"$INTERFACE\"\n\t\tjson_add_string _addrsig \"$addrsig\"\n\t\t[ -n \"$ZONE_464XLAT\" ] || ZONE_464XLAT=$ZONE\n\t\t[ -n \"$ZONE_464XLAT\" ] && json_add_string zone \"$ZONE_464XLAT\"\n\t\t[ -n \"$IFACE_464XLAT_DELEGATE\" ] && json_add_boolean delegate \"$IFACE_464XLAT_DELEGATE\"\n\t\tjson_close_object\n\t\tubus call network add_dynamic \"$(json_dump)\"\n\tfi\n\n\t# TODO: $SNTP_IP $SIP_IP $SNTP_FQDN $SIP_DOMAIN\n}\n\nteardown_interface() {\n\tproto_init_update \"*\" 0\n\tproto_send_update \"$INTERFACE\"\n}\n\ncase \"$2\" in\n\tbound)\n\t\tteardown_interface \"$1\"\n\t\tsetup_interface \"$1\"\n\t;;\n\tinformed|updated|rebound)\n\t\tsetup_interface \"$1\"\n\t;;\n\tra-updated)\n\t\t[ -n \"$ADDRESSES$RA_ADDRESSES$PREFIXES$USERPREFIX\" ] && setup_interface \"$1\"\n\t;;\n\tstarted|stopped|unbound)\n\t\tteardown_interface \"$1\"\n\t;;\nesac\n\n# user rules\n[ -f /etc/odhcp6c.user ] && . /etc/odhcp6c.user \"$@\"\nfor f in /etc/odhcp6c.user.d/*; do\n  [ -f \"$f\" ] && (. \"$f\" \"$@\")\ndone\n\nexit 0\n"
  },
  {
    "path": "package/network/ipv6/odhcp6c/files/dhcpv6.sh",
    "content": "#!/bin/sh\n\n. /lib/functions.sh\n. ../netifd-proto.sh\ninit_proto \"$@\"\n\nproto_dhcpv6_init_config() {\n\trenew_handler=1\n\n\tproto_config_add_string 'reqaddress:or(\"try\",\"force\",\"none\")'\n\tproto_config_add_string 'reqprefix:or(\"auto\",\"no\",range(0, 64))'\n\tproto_config_add_string clientid\n\tproto_config_add_string 'reqopts:list(uinteger)'\n\tproto_config_add_string 'defaultreqopts:bool'\n\tproto_config_add_string 'noslaaconly:bool'\n\tproto_config_add_string 'forceprefix:bool'\n\tproto_config_add_string 'extendprefix:bool'\n\tproto_config_add_string 'norelease:bool'\n\tproto_config_add_string 'noserverunicast:bool'\n\tproto_config_add_string 'noclientfqdn:bool'\n\tproto_config_add_string 'noacceptreconfig:bool'\n\tproto_config_add_array 'ip6prefix:list(ip6addr)'\n\tproto_config_add_string iface_dslite\n\tproto_config_add_string zone_dslite\n\tproto_config_add_string encaplimit_dslite\n\tproto_config_add_string iface_map\n\tproto_config_add_string zone_map\n\tproto_config_add_string encaplimit_map\n\tproto_config_add_string iface_464xlat\n\tproto_config_add_string zone_464xlat\n\tproto_config_add_string zone\n\tproto_config_add_string 'ifaceid:ip6addr'\n\tproto_config_add_string \"userclass\"\n\tproto_config_add_string \"vendorclass\"\n\tproto_config_add_array \"sendopts:list(string)\"\n\tproto_config_add_boolean delegate\n\tproto_config_add_int \"soltimeout\"\n\tproto_config_add_boolean fakeroutes\n\tproto_config_add_boolean sourcefilter\n\tproto_config_add_boolean keep_ra_dnslifetime\n\tproto_config_add_int \"ra_holdoff\"\n}\n\nproto_dhcpv6_add_prefix() {\n\tappend \"$3\" \"$1\"\n}\n\nproto_dhcpv6_add_sendopts() {\n\t[ -n \"$1\" ] && append \"$3\" \"-x$1\"\n}\n\nproto_dhcpv6_setup() {\n\tlocal config=\"$1\"\n\tlocal iface=\"$2\"\n\n\tlocal reqaddress reqprefix clientid reqopts defaultreqopts noslaaconly forceprefix extendprefix norelease noserverunicast noclientfqdn noacceptreconfig ip6prefix ip6prefixes iface_dslite iface_map iface_464xlat ifaceid userclass vendorclass sendopts delegate zone_dslite zone_map zone_464xlat zone encaplimit_dslite encaplimit_map soltimeout fakeroutes sourcefilter keep_ra_dnslifetime ra_holdoff\n\tjson_get_vars reqaddress reqprefix clientid reqopts defaultreqopts noslaaconly forceprefix extendprefix norelease noserverunicast noclientfqdn noacceptreconfig iface_dslite iface_map iface_464xlat ifaceid userclass vendorclass delegate zone_dslite zone_map zone_464xlat zone encaplimit_dslite encaplimit_map soltimeout fakeroutes sourcefilter keep_ra_dnslifetime ra_holdoff\n\tjson_for_each_item proto_dhcpv6_add_prefix ip6prefix ip6prefixes\n\n\t# Configure\n\tlocal opts=\"\"\n\t[ -n \"$reqaddress\" ] && append opts \"-N$reqaddress\"\n\n\t[ -z \"$reqprefix\" -o \"$reqprefix\" = \"auto\" ] && reqprefix=0\n\t[ \"$reqprefix\" != \"no\" ] && append opts \"-P$reqprefix\"\n\n\t[ -n \"$clientid\" ] && append opts \"-c$clientid\"\n\n\t[ \"$defaultreqopts\" = \"0\" ] && append opts \"-R\"\n\n\t[ \"$noslaaconly\" = \"1\" ] && append opts \"-S\"\n\n\t[ \"$forceprefix\" = \"1\" ] && append opts \"-F\"\n\n\t[ \"$norelease\" = \"1\" ] && append opts \"-k\"\n\n\t[ \"$noserverunicast\" = \"1\" ] && append opts \"-U\"\n\n\t[ \"$noclientfqdn\" = \"1\" ] && append opts \"-f\"\n\n\t[ \"$noacceptreconfig\" = \"1\" ] && append opts \"-a\"\n\n\t[ -n \"$ifaceid\" ] && append opts \"-i$ifaceid\"\n\n\t[ -n \"$vendorclass\" ] && append opts \"-V$vendorclass\"\n\n\t[ -n \"$userclass\" ] && append opts \"-u$userclass\"\n\n\t[ \"$keep_ra_dnslifetime\" = \"1\" ] && append opts \"-L\"\n\n\t[ -n \"$ra_holdoff\" ] && append opts \"-m$ra_holdoff\"\n\n\tlocal opt\n\tfor opt in $reqopts; do\n\t\tappend opts \"-r$opt\"\n\tdone\n\n\tjson_for_each_item proto_dhcpv6_add_sendopts sendopts opts\n\n\tappend opts \"-t${soltimeout:-120}\"\n\n\t[ -n \"$ip6prefixes\" ] && proto_export \"USERPREFIX=$ip6prefixes\"\n\t[ -n \"$iface_dslite\" ] && proto_export \"IFACE_DSLITE=$iface_dslite\"\n\t[ -n \"$iface_map\" ] && proto_export \"IFACE_MAP=$iface_map\"\n\t[ -n \"$iface_464xlat\" ] && proto_export \"IFACE_464XLAT=$iface_464xlat\"\n\t[ \"$delegate\" = \"0\" ] && proto_export \"IFACE_DSLITE_DELEGATE=0\"\n\t[ \"$delegate\" = \"0\" ] && proto_export \"IFACE_MAP_DELEGATE=0\"\n\t[ -n \"$zone_dslite\" ] && proto_export \"ZONE_DSLITE=$zone_dslite\"\n\t[ -n \"$zone_map\" ] && proto_export \"ZONE_MAP=$zone_map\"\n\t[ -n \"$zone_464xlat\" ] && proto_export \"ZONE_464XLAT=$zone_464xlat\"\n\t[ -n \"$zone\" ] && proto_export \"ZONE=$zone\"\n\t[ -n \"$encaplimit_dslite\" ] && proto_export \"ENCAPLIMIT_DSLITE=$encaplimit_dslite\"\n\t[ -n \"$encaplimit_map\" ] && proto_export \"ENCAPLIMIT_MAP=$encaplimit_map\"\n\t[ \"$fakeroutes\" != \"0\" ] && proto_export \"FAKE_ROUTES=1\"\n\t[ \"$sourcefilter\" = \"0\" ] && proto_export \"NOSOURCEFILTER=1\"\n\t[ \"$extendprefix\" = \"1\" ] && proto_export \"EXTENDPREFIX=1\"\n\n\tproto_export \"INTERFACE=$config\"\n\tproto_run_command \"$config\" odhcp6c \\\n\t\t-s /lib/netifd/dhcpv6.script \\\n\t\t$opts $iface\n}\n\nproto_dhcpv6_renew() {\n\tlocal interface=\"$1\"\n\t# SIGUSR1 forces odhcp6c to renew its lease\n\tlocal sigusr1=\"$(kill -l SIGUSR1)\"\n\t[ -n \"$sigusr1\" ] && proto_kill_command \"$interface\" $sigusr1\n}\n\nproto_dhcpv6_teardown() {\n\tlocal interface=\"$1\"\n\tproto_kill_command \"$interface\"\n}\n\nadd_protocol dhcpv6\n\n"
  },
  {
    "path": "package/network/ipv6/odhcp6c/files/odhcp6c.user",
    "content": "# This script is sourced by odhcp6c's dhcpv6.script at every DHCPv6 event.\n"
  },
  {
    "path": "package/network/ipv6/thc-ipv6/Makefile",
    "content": "#\n# Copyright (C) 2009-2015 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=thc-ipv6\nPKG_VERSION:=2.7\nPKG_RELEASE:=1\nPKG_LICENSE:=GPL-3.0\n\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz\nPKG_SOURCE_URL:=@GITHUB/vanhauser-thc/THC-Archive/master/Tools\nPKG_HASH:=440a3ae98b57100c397ec4f8634468dbbb0c3b48788c6b74af2a597a90544a96\n\nPKG_MAINTAINER:=Jo-Philipp Wich <jo@mein.io>\n\ninclude $(INCLUDE_DIR)/package.mk\n\nTHC_APPLETS := \\\n\taddress6 alive6 covert_send6 covert_send6d denial6 detect-new-ip6     \\\n\tdetect_sniffer6 dnsdict6 dnsrevenum6 dos-new-ip6                      \\\n\tdump_router6 exploit6 fake_advertise6 fake_dhcps6 fake_dns6d          \\\n\tfake_dnsupdate6 fake_mipv6 fake_mld26 fake_mld6 fake_mldrouter6       \\\n\tfake_router26 fake_router6 fake_solicitate6 flood_advertise6          \\\n\tflood_dhcpc6 flood_mld26 flood_mld6 flood_mldrouter6 flood_router26   \\\n\tflood_router6 flood_solicitate6 fragmentation6 fuzz_ip6 fuzz_dhcpc6   \\\n\tfuzz_dhcps6 implementation6 implementation6d inverse_lookup6          \\\n\tkill_router6 ndpexhaust6 node_query6 parasite6 passive_discovery6     \\\n\trandicmp6 redir6 rsmurf6 sendpees6 sendpeesmp6 smurf6 thcping6        \\\n\ttoobig6 trace6\n\nTHC_DEPENDS_dnsdict6 := +libpthread\nTHC_DEPENDS_thcping6 := +librt\n\ndefine BuildTool\n  define Package/thc-ipv6-$(subst _,-,$(1))\n    TITLE:=THC-IPv6 $(1) utility\n    SECTION:=net\n    CATEGORY:=Network\n    DEPENDS:=+libpcap $(THC_DEPENDS_$(1))\n    URL:=https://github.com/vanhauser-thc/thc-ipv6\n    SUBMENU:=THC-IPv6 attack and analyzing toolkit\n  endef\n\n  define Package/thc-ipv6-$(subst _,-,$(1))/description\n    This package contains the $(1) utility of the THC-IPv6 toolkit.\n  endef\n\n  define Package/thc-ipv6-$(subst _,-,$(1))/install\n\t$(INSTALL_DIR) $$(1)/usr/sbin\n\t$(INSTALL_BIN) $(PKG_BUILD_DIR)/$(1) $$(1)/usr/sbin/$(1)\n  endef\n\n  $$(eval $$(call BuildPackage,thc-ipv6-$(subst _,-,$(1))))\nendef\n\n$(foreach a,$(THC_APPLETS),$(eval $(call BuildTool,$(a))))\n"
  },
  {
    "path": "package/network/ipv6/thc-ipv6/patches/000-cflags_override.patch",
    "content": "diff -urN thc-ipv6-2.7/Makefile thc-ipv6-2.7.new/Makefile\n--- thc-ipv6-2.7/Makefile\t2014-12-27 05:05:30.000000000 -0800\n+++ thc-ipv6-2.7.new/Makefile\t2017-02-04 20:55:51.679898101 -0800\n@@ -3,7 +3,7 @@\n \n CC=gcc\n #CFLAGS=-g\n-CFLAGS=-O2\n+CFLAGS?=-O2\n CFLAGS+=$(if $(HAVE_SSL),-D_HAVE_SSL,)\n LDFLAGS+=-lpcap $(if $(HAVE_SSL),-lssl -lcrypto,)\n PROGRAMS=parasite6 dos-new-ip6 detect-new-ip6 fake_router6 fake_advertise6 fake_solicitate6 fake_mld6 fake_mld26 fake_mldrouter6 flood_mldrouter6 fake_mipv6 redir6 smurf6 alive6 toobig6 rsmurf6 implementation6 implementation6d sendpees6 sendpeesmp6 randicmp6 fuzz_ip6 flood_mld6 flood_mld26 flood_router6 flood_advertise6 flood_solicitate6 trace6 exploit6 denial6 fake_dhcps6 flood_dhcpc6 fake_dns6d fragmentation6 kill_router6 fake_dnsupdate6 ndpexhaust6 detect_sniffer6 dump_router6 fake_router26 flood_router26 passive_discovery6 dnsrevenum6 inverse_lookup6 node_query6 address6 covert_send6 covert_send6d inject_alive6 firewall6 ndpexhaust26 fake_pim6 thcsyn6 redirsniff6 flood_redir6 four2six dump_dhcp6 fuzz_dhcps6 flood_rs6 fuzz_dhcpc6\n"
  },
  {
    "path": "package/network/ipv6/thc-ipv6/patches/100-no-ssl.patch",
    "content": "--- a/Makefile\n+++ b/Makefile\n@@ -1,5 +1,5 @@\n # Comment out if openssl-dev is not present\n-HAVE_SSL=yes\n+#HAVE_SSL=yes\n \n CC=gcc\n #CFLAGS=-g\n"
  },
  {
    "path": "package/network/services/bridger/Makefile",
    "content": "#\n# Copyright (C) 2022 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=bridger\nPKG_SOURCE_PROTO:=git\nPKG_SOURCE_URL=https://github.com/nbd168/bridger\nPKG_SOURCE_DATE:=2022-04-06\nPKG_SOURCE_VERSION:=e8f6814a85b4ea951657e7018c5d77597400f44a\nPKG_MIRROR_HASH:=f917e099a9ab2a55745a7254239efabe695a722d5c448342198cdc847a4a24ac\n\nPKG_LICENSE:=GPL-2.0\nPKG_MAINTAINER:=Felix Fietkau <nbd@nbd.name>\n\nPKG_BUILD_DEPENDS:=bpf-headers\n\nPKG_BUILD_PARALLEL:=1\n\ninclude $(INCLUDE_DIR)/package.mk\ninclude $(INCLUDE_DIR)/cmake.mk\ninclude $(INCLUDE_DIR)/bpf.mk\ninclude $(INCLUDE_DIR)/nls.mk\n\ndefine Package/bridger\n  SECTION:=utils\n  CATEGORY:=Base system\n  TITLE:=Bridge forwarding accelerator\n  DEPENDS:=+libbpf +libubox +libubus +libnl-tiny +kmod-sched-core +kmod-sched-flower +kmod-sched-bpf +kmod-sched-act-vlan $(BPF_DEPENDS)\nendef\n\nTARGET_CFLAGS += \\\n\t-I$(STAGING_DIR)/usr/include/libnl-tiny \\\n\t-I$(STAGING_DIR)/usr/include\n\nCMAKE_OPTIONS += \\\n\t-DLIBNL_LIBS=-lnl-tiny\n\ndefine Build/Compile\n\t$(call CompileBPF,$(PKG_BUILD_DIR)/bridger-bpf.c)\n\t$(Build/Compile/Default)\nendef\n\ndefine Package/bridger/install\n\t$(INSTALL_DIR) \\\n\t\t$(1)/etc/config \\\n\t\t$(1)/etc/init.d \\\n\t\t$(1)/lib/bpf \\\n\t\t$(1)/usr/sbin\n\t$(INSTALL_DATA) $(PKG_BUILD_DIR)/bridger-bpf.o $(1)/lib/bpf\n\t$(INSTALL_BIN) \\\n\t\t$(PKG_INSTALL_DIR)/usr/bin/bridger \\\n\t\t$(1)/usr/sbin/\n\t$(INSTALL_DATA) ./files/bridger.conf $(1)/etc/config/bridger\n\t$(INSTALL_BIN) ./files/bridger.init $(1)/etc/init.d/bridger\nendef\n\n$(eval $(call BuildPackage,bridger))\n"
  },
  {
    "path": "package/network/services/bridger/files/bridger.conf",
    "content": "config defaults\n\t# example for blacklisting individual devices or bridges\n\t# list blacklist eth0\n"
  },
  {
    "path": "package/network/services/bridger/files/bridger.init",
    "content": "#!/bin/sh /etc/rc.common\n# Copyright (c) 2021 OpenWrt.org\n\nSTART=19\n\nUSE_PROCD=1\nPROG=/usr/sbin/bridger\n\nadd_blacklist() {\n\tcfg=\"$1\"\n\n\tconfig_get blacklist \"$cfg\" blacklist\n\tfor i in $blacklist; do\n\t\tjson_add_string \"\" \"$i\"\n\tdone\n}\n\nreload_service() {\n\tconfig_load bridger\n\n\tjson_init\n\tjson_add_string name \"config\"\n\tjson_add_array devices\n\tconfig_foreach add_blacklist defaults\n\tjson_close_array\n\n\tubus call bridger set_blacklist \"$(json_dump)\"\n}\n\nservice_triggers() {\n\tprocd_add_reload_trigger bridger\n}\n\nstart_service() {\n\tprocd_open_instance\n\tprocd_set_param command \"$PROG\"\n\tprocd_set_param respawn\n\tprocd_close_instance\n}\n\nservice_started() {\n\tubus -t 10 wait_for bridger\n\t[ $? = 0 ] && reload_service\n}\n"
  },
  {
    "path": "package/network/services/dnsmasq/Makefile",
    "content": "#\n# Copyright (C) 2006-2016 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=dnsmasq\nPKG_UPSTREAM_VERSION:=2.86\nPKG_VERSION:=$(subst test,~~test,$(subst rc,~rc,$(PKG_UPSTREAM_VERSION)))\nPKG_RELEASE:=$(AUTORELEASE)\n\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_UPSTREAM_VERSION).tar.xz\nPKG_SOURCE_URL:=http://thekelleys.org.uk/dnsmasq\nPKG_HASH:=28d52cfc9e2004ac4f85274f52b32e1647b4dbc9761b82e7de1e41c49907eb08\n\nPKG_LICENSE:=GPL-2.0\nPKG_LICENSE_FILES:=COPYING\nPKG_CPE_ID:=cpe:/a:thekelleys:dnsmasq\n\nPKG_BUILD_DIR:=$(BUILD_DIR)/$(PKG_NAME)-$(BUILD_VARIANT)/$(PKG_NAME)-$(PKG_UPSTREAM_VERSION)\n\nPKG_INSTALL:=1\nPKG_BUILD_PARALLEL:=1\nPKG_ASLR_PIE_REGULAR:=1\nPKG_CONFIG_DEPENDS:= CONFIG_PACKAGE_dnsmasq_$(BUILD_VARIANT)_dhcp \\\n\tCONFIG_PACKAGE_dnsmasq_$(BUILD_VARIANT)_dhcpv6 \\\n\tCONFIG_PACKAGE_dnsmasq_$(BUILD_VARIANT)_dnssec \\\n\tCONFIG_PACKAGE_dnsmasq_$(BUILD_VARIANT)_auth \\\n\tCONFIG_PACKAGE_dnsmasq_$(BUILD_VARIANT)_ipset \\\n\tCONFIG_PACKAGE_dnsmasq_$(BUILD_VARIANT)_conntrack \\\n\tCONFIG_PACKAGE_dnsmasq_$(BUILD_VARIANT)_noid \\\n\tCONFIG_PACKAGE_dnsmasq_$(BUILD_VARIANT)_broken_rtc \\\n\tCONFIG_PACKAGE_dnsmasq_$(BUILD_VARIANT)_tftp\n\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine Package/dnsmasq/Default\n  SECTION:=net\n  CATEGORY:=Base system\n  TITLE:=DNS and DHCP server\n  URL:=http://www.thekelleys.org.uk/dnsmasq/\n  DEPENDS:=+libubus\n  USERID:=dnsmasq=453:dnsmasq=453\nendef\n\ndefine Package/dnsmasq\n$(call Package/dnsmasq/Default)\n  VARIANT:=nodhcpv6\nendef\n\ndefine Package/dnsmasq-dhcpv6\n$(call Package/dnsmasq/Default)\n  TITLE += (with DHCPv6 support)\n  DEPENDS+=@IPV6\n  VARIANT:=dhcpv6\n  PROVIDES:=dnsmasq\nendef\n\ndefine Package/dnsmasq-full\n$(call Package/dnsmasq/Default)\n  TITLE += (with DNSSEC, DHCPv6, Auth DNS, IPset, Conntrack, NO_ID enabled by default)\n  DEPENDS+=+PACKAGE_dnsmasq_full_dnssec:libnettle \\\n\t+PACKAGE_dnsmasq_full_ipset:kmod-ipt-ipset \\\n\t+PACKAGE_dnsmasq_full_conntrack:libnetfilter-conntrack\n  VARIANT:=full\n  PROVIDES:=dnsmasq\nendef\n\ndefine Package/dnsmasq/description\n  It is intended to provide coupled DNS and DHCP service to a LAN.\nendef\n\ndefine Package/dnsmasq-dhcpv6/description\n$(call Package/dnsmasq/description)\n\nThis is a variant with DHCPv6 support\nendef\n\ndefine Package/dnsmasq-full/description\n$(call Package/dnsmasq/description)\n\nThis is a fully configurable variant with DHCPv4, DHCPv6, DNSSEC, Authoritative DNS\nand IPset, Conntrack support & NO_ID enabled by default.\nendef\n\ndefine Package/dnsmasq/conffiles\n/etc/config/dhcp\n/etc/dnsmasq.conf\n/etc/dnsmasq.d/\nendef\n\ndefine Package/dnsmasq-full/config\n\tif PACKAGE_dnsmasq-full\n\tconfig PACKAGE_dnsmasq_full_dhcp\n\t\tbool \"Build with DHCP support.\"\n\t\tdefault y\n\tconfig PACKAGE_dnsmasq_full_dhcpv6\n\t\tbool \"Build with DHCPv6 support.\"\n\t\tdepends on IPV6 && PACKAGE_dnsmasq_full_dhcp\n\t\tdefault y\n\tconfig PACKAGE_dnsmasq_full_dnssec\n\t\tbool \"Build with DNSSEC support.\"\n\t\tdefault y\n\tconfig PACKAGE_dnsmasq_full_auth\n\t\tbool \"Build with the facility to act as an authoritative DNS server.\"\n\t\tdefault y\n\tconfig PACKAGE_dnsmasq_full_ipset\n\t\tbool \"Build with IPset support.\"\n\t\tdefault y\n\tconfig PACKAGE_dnsmasq_full_conntrack\n\t\tbool \"Build with Conntrack support.\"\n\t\tdefault y\n\tconfig PACKAGE_dnsmasq_full_noid\n\t\tbool \"Build with NO_ID. (hide *.bind pseudo domain)\"\n\t\tdefault y\n\tconfig PACKAGE_dnsmasq_full_broken_rtc\n\t\tbool \"Build with HAVE_BROKEN_RTC.\"\n\t\tdefault n\n\tconfig PACKAGE_dnsmasq_full_tftp\n\t\tbool \"Build with TFTP server support.\"\n\t\tdefault y\n\tendif\nendef\n\nPackage/dnsmasq-dhcpv6/conffiles = $(Package/dnsmasq/conffiles)\nPackage/dnsmasq-full/conffiles = $(Package/dnsmasq/conffiles)\n\nTARGET_CFLAGS += -flto\nTARGET_LDFLAGS += -flto=jobserver\n\nCOPTS = -DHAVE_UBUS -DHAVE_POLL_H \\\n\t$(if $(CONFIG_IPV6),,-DNO_IPV6)\n\nifeq ($(BUILD_VARIANT),nodhcpv6)\n\tCOPTS += -DNO_DHCP6\nendif\n\nifeq ($(BUILD_VARIANT),full)\n\tCOPTS += $(if $(CONFIG_PACKAGE_dnsmasq_$(BUILD_VARIANT)_dhcp),,-DNO_DHCP) \\\n\t\t$(if $(CONFIG_PACKAGE_dnsmasq_$(BUILD_VARIANT)_dhcpv6),,-DNO_DHCP6) \\\n\t\t$(if $(CONFIG_PACKAGE_dnsmasq_$(BUILD_VARIANT)_dnssec),-DHAVE_DNSSEC) \\\n\t\t$(if $(CONFIG_PACKAGE_dnsmasq_$(BUILD_VARIANT)_auth),,-DNO_AUTH) \\\n\t\t$(if $(CONFIG_PACKAGE_dnsmasq_$(BUILD_VARIANT)_ipset),,-DNO_IPSET) \\\n\t\t$(if $(CONFIG_PACKAGE_dnsmasq_$(BUILD_VARIANT)_conntrack),-DHAVE_CONNTRACK,) \\\n\t\t$(if $(CONFIG_PACKAGE_dnsmasq_$(BUILD_VARIANT)_noid),-DNO_ID,) \\\n\t\t$(if $(CONFIG_PACKAGE_dnsmasq_$(BUILD_VARIANT)_broken_rtc),-DHAVE_BROKEN_RTC) \\\n\t\t$(if $(CONFIG_PACKAGE_dnsmasq_$(BUILD_VARIANT)_tftp),,-DNO_TFTP)\n\tCOPTS += $(if $(CONFIG_LIBNETTLE_MINI),-DNO_GMP,)\nelse\n\tCOPTS += -DNO_AUTH -DNO_IPSET -DNO_ID\nendif\n\nMAKE_FLAGS := \\\n\t$(TARGET_CONFIGURE_OPTS) \\\n\tCFLAGS=\"$(TARGET_CFLAGS) $(TARGET_CPPFLAGS)\" \\\n\tLDFLAGS=\"$(TARGET_LDFLAGS)\" \\\n\tCOPTS=\"$(COPTS)\" \\\n\tPREFIX=\"/usr\"\n\ndefine Package/dnsmasq/install\n\t$(INSTALL_DIR) $(1)/usr/sbin\n\t$(CP) $(PKG_INSTALL_DIR)/usr/sbin/dnsmasq $(1)/usr/sbin/\n\t$(INSTALL_DIR) $(1)/etc/config\n\t$(INSTALL_CONF) ./files/dhcp.conf $(1)/etc/config/dhcp\n\t$(INSTALL_CONF) ./files/dnsmasq.conf $(1)/etc/dnsmasq.conf\n\t$(INSTALL_DIR) $(1)/etc/init.d\n\t$(INSTALL_BIN) ./files/dnsmasq.init $(1)/etc/init.d/dnsmasq\n\t$(INSTALL_DIR) $(1)/etc/hotplug.d/dhcp\n\t$(INSTALL_DIR) $(1)/etc/hotplug.d/neigh\n\t$(INSTALL_DIR) $(1)/etc/hotplug.d/ntp\n\t$(INSTALL_DIR) $(1)/etc/hotplug.d/tftp\n\t$(INSTALL_DATA) ./files/dnsmasqsec.hotplug $(1)/etc/hotplug.d/ntp/25-dnsmasqsec\n\t$(INSTALL_DIR) $(1)/usr/share/dnsmasq\n\t$(INSTALL_CONF) ./files/dhcpbogushostname.conf $(1)/usr/share/dnsmasq/\n\t$(INSTALL_CONF) ./files/rfc6761.conf $(1)/usr/share/dnsmasq/\n\t$(INSTALL_DIR) $(1)/usr/lib/dnsmasq\n\t$(INSTALL_BIN) ./files/dhcp-script.sh $(1)/usr/lib/dnsmasq/dhcp-script.sh\n\t$(INSTALL_DIR) $(1)/usr/share/acl.d\n\t$(INSTALL_DATA) ./files/dnsmasq_acl.json $(1)/usr/share/acl.d/\n\t$(INSTALL_DIR) $(1)/etc/uci-defaults\n\t$(INSTALL_BIN) ./files/50-dnsmasq-migrate-resolv-conf-auto.sh $(1)/etc/uci-defaults\nendef\n\nPackage/dnsmasq-dhcpv6/install = $(Package/dnsmasq/install)\n\ndefine Package/dnsmasq-full/install\n$(call Package/dnsmasq/install,$(1))\nifneq ($(CONFIG_PACKAGE_dnsmasq_full_dnssec),)\n\t$(INSTALL_DIR) $(1)/usr/share/dnsmasq\n\t$(INSTALL_CONF) $(PKG_BUILD_DIR)/trust-anchors.conf $(1)/usr/share/dnsmasq\nendif\nendef\n\n$(eval $(call BuildPackage,dnsmasq))\n$(eval $(call BuildPackage,dnsmasq-dhcpv6))\n$(eval $(call BuildPackage,dnsmasq-full))\n"
  },
  {
    "path": "package/network/services/dnsmasq/files/50-dnsmasq-migrate-resolv-conf-auto.sh",
    "content": "#!/bin/sh\n\n[ \"$(uci get dhcp.@dnsmasq[0].resolvfile)\" = \"/tmp/resolv.conf.auto\" ] && {\n\tuci set dhcp.@dnsmasq[0].resolvfile=\"/tmp/resolv.conf.d/resolv.conf.auto\"\n\tuci commit dhcp\n}\n\nexit 0\n"
  },
  {
    "path": "package/network/services/dnsmasq/files/dhcp-script.sh",
    "content": "#!/bin/sh\n\n[ -f \"$USER_DHCPSCRIPT\" ] && . \"$USER_DHCPSCRIPT\" \"$@\"\n\n. /usr/share/libubox/jshn.sh\n\njson_init\njson_add_array env\nhotplugobj=\"\"\n\ncase \"$1\" in\n\tadd | del | old | arp-add | arp-del)\n\t\tjson_add_string \"\" \"MACADDR=$2\"\n\t\tjson_add_string \"\" \"IPADDR=$3\"\n\t;;\nesac\n\ncase \"$1\" in\n\tadd)\n\t\tjson_add_string \"\" \"ACTION=add\"\n\t\tjson_add_string \"\" \"HOSTNAME=$4\"\n\t\thotplugobj=\"dhcp\"\n\t;;\n\tdel)\n\t\tjson_add_string \"\" \"ACTION=remove\"\n\t\tjson_add_string \"\" \"HOSTNAME=$4\"\n\t\thotplugobj=\"dhcp\"\n\t;;\n\told)\n\t\tjson_add_string \"\" \"ACTION=update\"\n\t\tjson_add_string \"\" \"HOSTNAME=$4\"\n\t\thotplugobj=\"dhcp\"\n\t;;\n\tarp-add)\n\t\tjson_add_string \"\" \"ACTION=add\"\n\t\thotplugobj=\"neigh\"\n\t;;\n\tarp-del)\n\t\tjson_add_string \"\" \"ACTION=remove\"\n\t\thotplugobj=\"neigh\"\n\t;;\n\ttftp)\n\t\tjson_add_string \"\" \"ACTION=add\"\n\t\tjson_add_string \"\" \"TFTP_SIZE=$2\"\n\t\tjson_add_string \"\" \"TFTP_ADDR=$3\"\n\t\tjson_add_string \"\" \"TFTP_PATH=$4\"\n\t\thotplugobj=\"tftp\"\n\t;;\nesac\n\njson_close_array env\n\n[ -n \"$hotplugobj\" ] && ubus call hotplug.${hotplugobj} call \"$(json_dump)\"\n"
  },
  {
    "path": "package/network/services/dnsmasq/files/dhcp.conf",
    "content": "config dnsmasq\n\toption domainneeded\t1\n\toption boguspriv\t1\n\toption filterwin2k\t0  # enable for dial on demand\n\toption localise_queries\t1\n\toption rebind_protection 1  # disable if upstream must serve RFC1918 addresses\n\toption rebind_localhost 1  # enable for RBL checking and similar services\n\t#list rebind_domain example.lan  # whitelist RFC1918 responses for domains\n\toption local\t'/lan/'\n\toption domain\t'lan'\n\toption expandhosts\t1\n\toption nonegcache\t0\n\toption authoritative\t1\n\toption readethers\t1\n\toption leasefile\t'/tmp/dhcp.leases'\n\toption resolvfile\t'/tmp/resolv.conf.d/resolv.conf.auto'\n\t#list server\t\t'/mycompany.local/1.2.3.4'\n\toption nonwildcard\t1 # bind to & keep track of interfaces\n\t#list interface\t\tbr-lan\n\t#list notinterface\tlo\n\t#list bogusnxdomain     '64.94.110.11'\n\toption localservice\t1  # disable to allow DNS requests from non-local subnets\n\toption ednspacket_max\t1232\n\nconfig dhcp lan\n\toption interface\tlan\n\toption start \t100\n\toption limit\t150\n\toption leasetime\t12h\n\nconfig dhcp wan\n\toption interface\twan\n\toption ignore\t1\n"
  },
  {
    "path": "package/network/services/dnsmasq/files/dhcpbogushostname.conf",
    "content": "# dhcpbogushostname.conf included configuration file for dnsmasq\n#\n# includes a list of hostnames that should not be associated with dhcp leases\n# in response to CERT VU#598349\n# file included by default, option dhcpbogushostname 0  to disable\n\ndhcp-name-match=set:dhcp_bogus_hostname,localhost\ndhcp-name-match=set:dhcp_bogus_hostname,wpad\n"
  },
  {
    "path": "package/network/services/dnsmasq/files/dnsmasq.conf",
    "content": "# Change the following lines if you want dnsmasq to serve SRV\n# records.\n# You may add multiple srv-host lines.\n# The fields are <name>,<target>,<port>,<priority>,<weight>\n\n# A SRV record sending LDAP for the example.com domain to\n# ldapserver.example.com port 289\n#srv-host=_ldap._tcp.example.com,ldapserver.example.com,389\n\n# Two SRV records for LDAP, each with different priorities\n#srv-host=_ldap._tcp.example.com,ldapserver.example.com,389,1\n#srv-host=_ldap._tcp.example.com,ldapserver.example.com,389,2\n\n# A SRV record indicating that there is no LDAP server for the domain\n# example.com\n#srv-host=_ldap._tcp.example.com\n\n# The following line shows how to make dnsmasq serve an arbitrary PTR\n# record. This is useful for DNS-SD.\n# The fields are <name>,<target>\n#ptr-record=_http._tcp.dns-sd-services,\"New Employee Page._http._tcp.dns-sd-services\"\n\n# Change the following lines to enable dnsmasq to serve TXT records.\n# These are used for things like SPF and zeroconf.\n# The fields are <name>,<text>,<text>...\n\n#Example SPF.\n#txt-record=example.com,\"v=spf1 a -all\"\n\n#Example zeroconf\n#txt-record=_http._tcp.example.com,name=value,paper=A4\n\n# Provide an alias for a \"local\" DNS name. Note that this _only_ works\n# for targets which are names from DHCP or /etc/hosts. Give host\n# \"bert\" another name, bertrand\n# The fields are <cname>,<target>\n#cname=bertand,bert\n"
  },
  {
    "path": "package/network/services/dnsmasq/files/dnsmasq.init",
    "content": "#!/bin/sh /etc/rc.common\n# Copyright (C) 2007-2012 OpenWrt.org\n\nSTART=19\n\nUSE_PROCD=1\nPROG=/usr/sbin/dnsmasq\n\nADD_LOCAL_DOMAIN=1\nADD_LOCAL_HOSTNAME=1\nADD_WAN_FQDN=0\nADD_LOCAL_FQDN=\"\"\n\nBASECONFIGFILE=\"/var/etc/dnsmasq.conf\"\nBASEHOSTFILE=\"/tmp/hosts/dhcp\"\nTRUSTANCHORSFILE=\"/usr/share/dnsmasq/trust-anchors.conf\"\nTIMEVALIDFILE=\"/var/state/dnsmasqsec\"\nBASEDHCPSTAMPFILE=\"/var/run/dnsmasq\"\nDHCPBOGUSHOSTNAMEFILE=\"/usr/share/dnsmasq/dhcpbogushostname.conf\"\nRFC6761FILE=\"/usr/share/dnsmasq/rfc6761.conf\"\nDHCPSCRIPT=\"/usr/lib/dnsmasq/dhcp-script.sh\"\nDHCPSCRIPT_DEPENDS=\"/usr/share/libubox/jshn.sh /usr/bin/jshn /bin/ubus\"\n\nDNSMASQ_DHCP_VER=4\n\ndnsmasq_ignore_opt() {\n\tlocal opt=\"$1\"\n\n\tif [ -z \"$dnsmasq_features\" ]; then\n\t\tdnsmasq_features=\"$(dnsmasq --version | grep -m1 'Compile time options:' | cut -d: -f2) \"\n\t\t[ \"${dnsmasq_features#* DHCP }\" = \"$dnsmasq_features\" ] || dnsmasq_has_dhcp=1\n\t\t[ \"${dnsmasq_features#* DHCPv6 }\" = \"$dnsmasq_features\" ] || dnsmasq_has_dhcp6=1\n\t\t[ \"${dnsmasq_features#* DNSSEC }\" = \"$dnsmasq_features\" ] || dnsmasq_has_dnssec=1\n\t\t[ \"${dnsmasq_features#* TFTP }\" = \"$dnsmasq_features\" ] || dnsmasq_has_tftp=1\n\t\t[ \"${dnsmasq_features#* ipset }\" = \"$dnsmasq_features\" ] || dnsmasq_has_ipset=1\n\tfi\n\n\tcase \"$opt\" in\n\t\tdhcp-duid|\\\n\t\tra-param)\n\t\t\t[ -z \"$dnsmasq_has_dhcp6\" ] ;;\n\t\tdhcp-*|\\\n\t\tbootp-*|\\\n\t\tpxe-*)\n\t\t\t[ -z \"$dnsmasq_has_dhcp\" ] ;;\n\t\tdnssec*|\\\n\t\ttrust-anchor)\n\t\t\tif [ -z \"$dnsmasq_has_dnssec\" ]; then\n\t\t\t\techo \"dnsmasq: \\\"$opt\\\" requested, but dnssec support is not available\" >&2\n\t\t\t\texit 1\n\t\t\tfi\n\t\t\treturn 1\n\t\t\t;;\n\t\ttftp-*)\n\t\t\t[ -z \"$dnsmasq_has_tftp\" ] ;;\n\t\tipset)\n\t\t\t[ -z \"$dnsmasq_has_ipset\" ] ;;\n\t\t*)\n\t\t\treturn 1\n\tesac\n}\n\nxappend() {\n\tlocal value=\"${1#--}\"\n\tlocal opt=\"${value%%=*}\"\n\n\tif ! dnsmasq_ignore_opt \"$opt\"; then\n\t\techo \"$value\" >>$CONFIGFILE_TMP\n\tfi\n}\n\nhex_to_hostid() {\n\tlocal var=\"$1\"\n\tlocal hex=\"${2#0x}\" # strip optional \"0x\" prefix\n\n\tif [ -n \"${hex//[0-9a-fA-F]/}\" ]; then\n\t\t# is invalid hex literal\n\t\treturn 1\n\tfi\n\n\t# convert into host id\n\texport \"$var=$(\n\t\tprintf \"%0x:%0x\" \\\n\t\t$(((0x$hex >> 16) % 65536)) \\\n\t\t$(( 0x$hex        % 65536))\n\t\t)\"\n\n\treturn 0\n}\n\ndhcp_calc() {\n\tlocal ip=\"$1\"\n\tlocal res=0\n\n\twhile [ -n \"$ip\" ]; do\n\t\tpart=\"${ip%%.*}\"\n\t\tres=\"$(($res * 256))\"\n\t\tres=\"$(($res + $part))\"\n\t\t[ \"${ip%.*}\" != \"$ip\" ] && ip=\"${ip#*.}\" || ip=\n\tdone\n\techo \"$res\"\n}\n\ndhcp_check() {\n\tlocal ifname=\"$1\"\n\tlocal stamp=\"${BASEDHCPSTAMPFILE_CFG}.${ifname}.dhcp\"\n\tlocal rv=0\n\n\t[ -s \"$stamp\" ] && return $(cat \"$stamp\")\n\n\t# If interface is down, skip it.\n\t# The init script will be called again once the link is up\n\tcase \"$(devstatus \"$ifname\" | jsonfilter -e @.up)\" in\n\t\tfalse) return 1;;\n\tesac\n\n\tudhcpc -n -q -s /bin/true -t 1 -i \"$ifname\" >&- && rv=1 || rv=0\n\n\techo $rv > \"$stamp\"\n\treturn $rv\n}\n\nlog_once() {\n\tpidof dnsmasq >/dev/null || \\\n\t\tlogger -t dnsmasq \"$@\"\n}\n\nhas_handler() {\n\tlocal file\n\n\tfor file in /etc/hotplug.d/dhcp/* /etc/hotplug.d/tftp/* /etc/hotplug.d/neigh/*; do\n\t\t[ -f \"$file\" ] && return 0\n\tdone\n\n\treturn 1\n}\n\nappend_bool() {\n\tlocal section=\"$1\"\n\tlocal option=\"$2\"\n\tlocal value=\"$3\"\n\tlocal default=\"$4\"\n\tlocal _loctmp\n\t[ -z \"$default\" ] && default=\"0\"\n\tconfig_get_bool _loctmp \"$section\" \"$option\" \"$default\"\n\t[ $_loctmp -gt 0 ] && xappend \"$value\"\n}\n\nappend_parm() {\n\tlocal section=\"$1\"\n\tlocal option=\"$2\"\n\tlocal switch=\"$3\"\n\tlocal default=\"$4\"\n\tlocal _loctmp\n\tconfig_get _loctmp \"$section\" \"$option\" \"$default\"\n\t[ -z \"$_loctmp\" ] && return 0\n\txappend \"$switch=$_loctmp\"\n}\n\nappend_server() {\n\txappend \"--server=$1\"\n}\n\nappend_rev_server() {\n\txappend \"--rev-server=$1\"\n}\n\nappend_address() {\n\txappend \"--address=$1\"\n}\n\nappend_ipset() {\n\txappend \"--ipset=$1\"\n}\n\nappend_connmark_allowlist() {\n\txappend \"--connmark-allowlist=$1\"\n}\n\nappend_interface() {\n\tnetwork_get_device ifname \"$1\" || ifname=\"$1\"\n\txappend \"--interface=$ifname\"\n}\n\nappend_listenaddress() {\n\txappend \"--listen-address=$1\"\n}\n\nappend_notinterface() {\n\tnetwork_get_device ifname \"$1\" || ifname=\"$1\"\n\txappend \"--except-interface=$ifname\"\n}\n\nismounted() {\n\tlocal filename=\"$1\"\n\tlocal dirname\n\tfor dirname in $EXTRA_MOUNT ; do\n\t\tcase \"$filename\" in\n\t\t\t\"${dirname}/\"* | \"${dirname}\" )\n\t\t\t\treturn 0\n\t\t\t\t;;\n\t\tesac\n\tdone\n\n\treturn 1\n}\n\nappend_addnhosts() {\n\tismounted \"$1\" || append EXTRA_MOUNT \"$1\"\n\txappend \"--addn-hosts=$1\"\n}\n\nappend_bogusnxdomain() {\n\txappend \"--bogus-nxdomain=$1\"\n}\n\nappend_pxe_service() {\n\txappend \"--pxe-service=$1\"\n}\n\nappend_interface_name() {\n\txappend \"--interface-name=$1,$2\"\n}\n\nfilter_dnsmasq() {\n\tlocal cfg=\"$1\" func=\"$2\" match_cfg=\"$3\" found_cfg\n\n\t# use entry when no instance entry set, or if it matches\n\tconfig_get found_cfg \"$cfg\" \"instance\"\n\tif [ -z \"$found_cfg\" ] || [ \"$found_cfg\" = \"$match_cfg\" ]; then\n\t\t$func $cfg\n\tfi\n}\n\ndhcp_subscrid_add() {\n\tlocal cfg=\"$1\"\n\n\tconfig_get networkid \"$cfg\" networkid\n\t[ -n \"$networkid\" ] || return 0\n\n\tconfig_get subscriberid \"$cfg\" subscriberid\n\t[ -n \"$subscriberid\" ] || return 0\n\n\txappend \"--dhcp-subscrid=set:$networkid,$subscriberid\"\n\n\tconfig_get_bool force \"$cfg\" force 0\n\n\tdhcp_option_add \"$cfg\" \"$networkid\" \"$force\"\n}\n\ndhcp_remoteid_add() {\n\tlocal cfg=\"$1\"\n\n\tconfig_get networkid \"$cfg\" networkid\n\t[ -n \"$networkid\" ] || return 0\n\n\tconfig_get remoteid \"$cfg\" remoteid\n\t[ -n \"$remoteid\" ] || return 0\n\n\txappend \"--dhcp-remoteid=set:$networkid,$remoteid\"\n\n\tconfig_get_bool force \"$cfg\" force 0\n\n\tdhcp_option_add \"$cfg\" \"$networkid\" \"$force\"\n}\n\ndhcp_circuitid_add() {\n\t# TODO: DHCPV6 does not have circuitid; catch \"option6:\"\n\tlocal cfg=\"$1\"\n\n\tconfig_get networkid \"$cfg\" networkid\n\t[ -n \"$networkid\" ] || return 0\n\n\tconfig_get circuitid \"$cfg\" circuitid\n\t[ -n \"$circuitid\" ] || return 0\n\n\txappend \"--dhcp-circuitid=set:$networkid,$circuitid\"\n\n\tconfig_get_bool force \"$cfg\" force 0\n\n\tdhcp_option_add \"$cfg\" \"$networkid\" \"$force\"\n}\n\ndhcp_userclass_add() {\n\tlocal cfg=\"$1\"\n\n\tconfig_get networkid \"$cfg\" networkid\n\t[ -n \"$networkid\" ] || return 0\n\n\tconfig_get userclass \"$cfg\" userclass\n\t[ -n \"$userclass\" ] || return 0\n\n\txappend \"--dhcp-userclass=set:$networkid,$userclass\"\n\n\tconfig_get_bool force \"$cfg\" force 0\n\n\tdhcp_option_add \"$cfg\" \"$networkid\" \"$force\"\n}\n\ndhcp_vendorclass_add() {\n\t# TODO: DHCPV6 vendor class has stricter definitions; catch? fixup?\n\tlocal cfg=\"$1\"\n\n\tconfig_get networkid \"$cfg\" networkid\n\t[ -n \"$networkid\" ] || return 0\n\n\tconfig_get vendorclass \"$cfg\" vendorclass\n\t[ -n \"$vendorclass\" ] || return 0\n\n\txappend \"--dhcp-vendorclass=set:$networkid,$vendorclass\"\n\n\tconfig_get_bool force \"$cfg\" force 0\n\n\tdhcp_option_add \"$cfg\" \"$networkid\" \"$force\"\n}\n\ndhcp_match_add() {\n\tlocal cfg=\"$1\"\n\n\tconfig_get networkid \"$cfg\" networkid\n\t[ -n \"$networkid\" ] || return 0\n\n\tconfig_get match \"$cfg\" match\n\t[ -n \"$match\" ] || return 0\n\n\txappend \"--dhcp-match=set:$networkid,$match\"\n\n\tconfig_get_bool force \"$cfg\" force 0\n\n\tdhcp_option_add \"$cfg\" \"$networkid\" \"$force\"\n}\n\ndhcp_host_add() {\n\tlocal cfg=\"$1\"\n\tlocal hosttag nametime addrs duids macs tags mtags\n\n\tconfig_get_bool force \"$cfg\" force 0\n\n\tconfig_get networkid \"$cfg\" networkid\n\t[ -n \"$networkid\" ] && dhcp_option_add \"$cfg\" \"$networkid\" \"$force\"\n\n\tconfig_get_bool enable \"$cfg\" enable 1\n\t[ \"$enable\" = \"0\" ] && return 0\n\n\tconfig_get name \"$cfg\" name\n\tconfig_get ip \"$cfg\" ip\n\tconfig_get hostid \"$cfg\" hostid\n\n\t[ -z \"$ip\" ] && [ -z \"$name\" ] && [ -z \"$hostid\" ] && return 0\n\n\tconfig_get_bool dns \"$cfg\" dns 0\n\t[ \"$dns\" = \"1\" ] && [ -n \"$ip\" ] && [ -n \"$name\" ] && {\n\t\techo \"$ip $name${DOMAIN:+.$DOMAIN}\" >> $HOSTFILE_TMP\n\t}\n\n\tconfig_get mac \"$cfg\" mac\n\tconfig_get duid \"$cfg\" duid\n\tconfig_get tag \"$cfg\" tag\n\n\tadd_tag() {\n\t\tmtags=\"${mtags}tag:$1,\"\n\t}\n\tconfig_list_foreach \"$cfg\" match_tag add_tag\n\n\tif [ -n \"$mac\" ]; then\n\t\t# --dhcp-host=00:20:e0:3b:13:af,192.168.0.199,lap\n\t\t# many MAC are possible to track a laptop ON/OFF dock\n\t\tfor m in $mac; do append macs \"$m\" \",\"; done\n\tfi\n\n\tif [ $DNSMASQ_DHCP_VER -eq 6 ] && [ -n \"$duid\" ]; then\n\t\t# --dhcp-host=id:00:03:00:01:12:00:00:01:02:03,[::beef],lap\n\t\t# one (virtual) machine gets one DUID per RFC3315\n\t\tduids=\"id:${duid// */}\"\n\tfi\n\n\tif [ -z \"$macs\" ] && [ -z \"$duids\" ]; then\n\t\t# --dhcp-host=lap,192.168.0.199,[::beef]\n\t\t[ -n \"$name\" ] || return 0\n\t\tmacs=\"$name\"\n\t\tname=\"\"\n\tfi\n\n\tif [ -n \"$hostid\" ]; then\n\t\thex_to_hostid hostid \"$hostid\"\n\tfi\n\n\tif [ -n \"$tag\" ]; then\n\t\tfor t in $tag; do append tags \"$t\" \",set:\"; done\n\tfi\n\n\tconfig_get_bool broadcast \"$cfg\" broadcast 0\n\tconfig_get leasetime \"$cfg\" leasetime\n\n\t[ \"$broadcast\" = \"0\" ] && broadcast= || broadcast=\",set:needs-broadcast\"\n\n\thosttag=\"${networkid:+,set:${networkid}}${tags:+,set:${tags}}$broadcast\"\n\tnametime=\"${name:+,$name}${leasetime:+,$leasetime}\"\n\n\tif [ $DNSMASQ_DHCP_VER -eq 6 ]; then\n\t\taddrs=\"${ip:+,$ip}${hostid:+,[::$hostid]}\"\n\t\txappend \"--dhcp-host=$mtags$macs${duids:+,$duids}$hosttag$addrs$nametime\"\n\telse\n\t\txappend \"--dhcp-host=$mtags$macs$hosttag${ip:+,$ip}$nametime\"\n\tfi\n}\n\ndhcp_this_host_add() {\n\tlocal net=\"$1\"\n\tlocal ifname=\"$2\"\n\tlocal mode=\"$3\"\n\tlocal routerstub routername ifdashname\n\tlocal lanaddr lanaddr6 lanaddrs6 ulaprefix\n\n\tif [ \"$mode\" -gt 0 ] ; then\n\t\tifdashname=\"${ifname//./-}\"\n\t\trouterstub=\"$( md5sum /etc/os-release )\"\n\t\trouterstub=\"router-${routerstub// */}\"\n\t\troutername=\"$( uci_get system @system[0] hostname $routerstub )\"\n\n\t\tif [ \"$mode\" -gt 1 ] ; then\n\t\t\tif [ \"$mode\" -gt 2 ] ; then\n\t\t\t\tif [ \"$mode\" -gt 3 ] ; then\n\t\t\t\t\tappend_interface_name \"$ifdashname.$routername.$DOMAIN\" \"$ifname\"\n\t\t\t\tfi\n\n\t\t\t\tappend_interface_name \"$routername.$DOMAIN\" \"$ifname\"\n\t\t\tfi\n\n\t\t\t# All IP addresses discovered by dnsmasq will be labeled (except fe80::)\n\t\t\tappend_interface_name \"$routername\" \"$ifname\"\n\n\t\telse\n\t\t\t# This uses a static host file entry for only limited addresses.\n\t\t\t# Use dnsmasq option \"--expandhosts\" to enable FQDN on host files.\n\t\t\tulaprefix=\"$(uci_get network @globals[0] ula_prefix)\"\n\t\t\tnetwork_get_ipaddr lanaddr \"$net\"\n\t\t\tnetwork_get_ipaddrs6 lanaddrs6 \"$net\"\n\n\t\t\tif [ -n \"$lanaddr\" ] ; then\n\t\t\t\tdhcp_domain_add \"\" \"$routername\" \"$lanaddr\"\n\t\t\tfi\n\n\t\t\tif [ -n \"$ulaprefix\" ] && [ -n \"$lanaddrs6\" ] ; then\n\t\t\t\tfor lanaddr6 in $lanaddrs6 ; do\n\t\t\t\t\tcase \"$lanaddr6\" in\n\t\t\t\t\t\"${ulaprefix%%:/*}\"*)\n\t\t\t\t\t\tdhcp_domain_add \"\" \"$routername\" \"$lanaddr6\"\n\t\t\t\t\t\t;;\n\t\t\t\t\tesac\n\t\t\t\tdone\n\t\t\tfi\n\t\tfi\n\tfi\n}\n\ndhcp_tag_add() {\n\t# NOTE: dnsmasq has explicit \"option6:\" prefix for DHCPv6 so no collisions\n\tlocal cfg=\"$1\"\n\n\ttag=\"$cfg\"\n\n\t[ -n \"$tag\" ] || return 0\n\n\tconfig_get_bool force \"$cfg\" force 0\n\t[ \"$force\" = \"0\" ] && force=\n\n\tconfig_get option \"$cfg\" dhcp_option\n\tfor o in $option; do\n\t\txappend \"--dhcp-option${force:+-force}=tag:$tag,$o\"\n\tdone\n}\n\ndhcp_mac_add() {\n\tlocal cfg=\"$1\"\n\n\tconfig_get networkid \"$cfg\" networkid\n\t[ -n \"$networkid\" ] || return 0\n\n\tconfig_get mac \"$cfg\" mac\n\t[ -n \"$mac\" ] || return 0\n\n\txappend \"--dhcp-mac=$networkid,$mac\"\n\n\tdhcp_option_add \"$cfg\" \"$networkid\"\n}\n\ndhcp_boot_add() {\n\t# TODO: BOOTURL is different between DHCPv4 and DHCPv6\n\tlocal cfg=\"$1\"\n\n\tconfig_get networkid \"$cfg\" networkid\n\n\tconfig_get filename \"$cfg\" filename\n\t[ -n \"$filename\" ] || return 0\n\n\tconfig_get servername \"$cfg\" servername\n\tconfig_get serveraddress \"$cfg\" serveraddress\n\n\t[ -n \"$serveraddress\" ] && [ ! -n \"$servername\" ] && return 0\n\n\txappend \"--dhcp-boot=${networkid:+net:$networkid,}${filename}${servername:+,$servername}${serveraddress:+,$serveraddress}\"\n\n\tconfig_get_bool force \"$cfg\" force 0\n\n\tdhcp_option_add \"$cfg\" \"$networkid\" \"$force\"\n}\n\n\ndhcp_add() {\n\tlocal cfg=\"$1\"\n\tlocal dhcp6range=\"::\"\n\tlocal nettag\n\tlocal tags\n\n\tconfig_get net \"$cfg\" interface\n\t[ -n \"$net\" ] || return 0\n\n\tconfig_get networkid \"$cfg\" networkid\n\t[ -n \"$networkid\" ] || networkid=\"$net\"\n\n\tnetwork_get_device ifname \"$net\" || return 0\n\n\t[ \"$cachelocal\" = \"0\" ] && network_get_dnsserver dnsserver \"$net\" && {\n\t\tDNS_SERVERS=\"$DNS_SERVERS $dnsserver\"\n\t}\n\n\tappend_bool \"$cfg\" ignore \"--no-dhcp-interface=$ifname\" && {\n\t\t# Many ISP do not have useful names for DHCP customers (your WAN).\n\t\tdhcp_this_host_add \"$net\" \"$ifname\" \"$ADD_WAN_FQDN\"\n\t\treturn 0\n\t}\n\n\tnetwork_get_subnet subnet \"$net\" || return 0\n\tnetwork_get_protocol proto \"$net\" || return 0\n\n\t# Do not support non-static interfaces for now\n\t[ static = \"$proto\" ] || return 0\n\n\t# Override interface netmask with dhcp config if applicable\n\tconfig_get netmask \"$cfg\" netmask \"${subnet##*/}\"\n\n\t#check for an already active dhcp server on the interface, unless 'force' is set\n\tconfig_get_bool force \"$cfg\" force 0\n\t[ $force -gt 0 ] || dhcp_check \"$ifname\" || {\n\t\tlogger -t dnsmasq \\\n\t\t\t\"found already running DHCP-server on interface '$ifname'\" \\\n\t\t\t\"refusing to start, use 'option force 1' to override\"\n\t\treturn 0\n\t}\n\n\tconfig_get start \"$cfg\" start 100\n\tconfig_get limit \"$cfg\" limit 150\n\tconfig_get leasetime \"$cfg\" leasetime 12h\n\tconfig_get options \"$cfg\" options\n\tconfig_get_bool dynamicdhcp \"$cfg\" dynamicdhcp 1\n\n\tconfig_get dhcpv4 \"$cfg\" dhcpv4\n\tconfig_get dhcpv6 \"$cfg\" dhcpv6\n\n\tconfig_get ra \"$cfg\" ra\n\tconfig_get ra_management \"$cfg\" ra_management\n\tconfig_get ra_preference \"$cfg\" ra_preference\n\tconfig_get dns \"$cfg\" dns\n\n\tconfig_list_foreach \"$cfg\" \"interface_name\" append_interface_name \"$ifname\"\n\n\t# Put the router host name on this DHCP served interface address(es)\n\tdhcp_this_host_add \"$net\" \"$ifname\" \"$ADD_LOCAL_FQDN\"\n\n\tstart=\"$( dhcp_calc \"$start\" )\"\n\n\tadd_tag() {\n\t\ttags=\"${tags}tag:$1,\"\n\t}\n\tconfig_list_foreach \"$cfg\" tag add_tag\n\n\tnettag=\"${networkid:+set:${networkid},}\"\n\n\tif [ \"$limit\" -gt 0 ] ; then\n\t\tlimit=$((limit-1))\n\tfi\n\n\teval \"$(ipcalc.sh \"${subnet%%/*}\" $netmask $start $limit)\"\n\n\tif [ \"$dynamicdhcp\" = \"0\" ] ; then\n\t\tEND=\"static\"\n\t\tdhcp6range=\"::,static\"\n\telse\n\t\tdhcp6range=\"::1000,::ffff\"\n\tfi\n\n\n\tif [ \"$dhcpv4\" != \"disabled\" ] ; then\n\t\txappend \"--dhcp-range=$tags$nettag$START,$END,$NETMASK,$leasetime${options:+ $options}\"\n\tfi\n\n\n\tif [ $DNSMASQ_DHCP_VER -eq 6 ] && [ \"$ra\" = \"server\" ] ; then\n\t\t# Note: dnsmasq cannot just be a DHCPv6 server (all-in-1)\n\t\t# and let some other machine(s) send RA pointing to it.\n\n\t\tcase $ra_preference in\n\t\t*high*)\n\t\t\txappend \"--ra-param=$ifname,high,0,7200\"\n\t\t\t;;\n\t\t*low*)\n\t\t\txappend \"--ra-param=$ifname,low,0,7200\"\n\t\t\t;;\n\t\t*)\n\t\t\t# Send UNSOLICITED RA at default interval and live for 2 hours.\n\t\t\t# TODO: convert flexible lease time into route life time (only seconds).\n\t\t\txappend \"--ra-param=$ifname,0,7200\"\n\t\t\t;;\n\t\tesac\n\n\t\tif [ \"$dhcpv6\" = \"disabled\" ] ; then\n\t\t\tra_management=\"3\"\n\t\tfi\n\n\n\t\tcase $ra_management in\n\t\t0)\n\t\t\t# SLACC with DCHP for extended options\n\t\t\txappend \"--dhcp-range=$nettag::,constructor:$ifname,ra-stateless,ra-names\"\n\t\t\t;;\n\t\t2)\n\t\t\t# DHCP address and RA only for management redirection\n\t\t\txappend \"--dhcp-range=$nettag$dhcp6range,constructor:$ifname,$leasetime\"\n\t\t\t;;\n\t\t3)\n\t\t\t# SLAAC only but dnsmasq attempts to link HOSTNAME, DHCPv4 MAC, and SLAAC\n\t\t\txappend \"--dhcp-range=$nettag::,constructor:$ifname,ra-only,ra-names\"\n\t\t\t;;\n\t\t*)\n\t\t\t# SLAAC and full DHCP\n\t\t\txappend \"--dhcp-range=$nettag$dhcp6range,constructor:$ifname,slaac,ra-names,$leasetime\"\n\t\t\t;;\n\t\tesac\n\n\t\tif [ -n \"$dns\" ]; then\n\t\t\tdnss=\"\"\n\t\t\tfor d in $dns; do append dnss \"[$d]\" \",\"; done\n\t\telse\n\t\t\tdnss=\"[::]\"\n\t\tfi\n\n\t\tdhcp_option_append \"option6:dns-server,$dnss\" \"$networkid\"\n\tfi\n\n\tdhcp_option_add \"$cfg\" \"$networkid\" 0\n\tdhcp_option_add \"$cfg\" \"$networkid\" 2\n}\n\ndhcp_option_append() {\n\tlocal option=\"$1\"\n\tlocal networkid=\"$2\"\n\tlocal force=\"$3\"\n\n\txappend \"--dhcp-option${force:+-force}=${networkid:+$networkid,}$option\"\n}\n\ndhcp_option_add() {\n\t# NOTE: dnsmasq has explicit \"option6:\" prefix for DHCPv6 so no collisions\n\tlocal cfg=\"$1\"\n\tlocal networkid=\"$2\"\n\tlocal force=\"$3\"\n\tlocal opt=\"dhcp_option\"\n\n\t[ \"$force\" = \"0\" ] && force=\n\t[ \"$force\" = \"2\" ] && opt=\"dhcp_option_force\"\n\n\tlocal list_len\n\tconfig_get list_len \"$cfg\" \"${opt}_LENGTH\"\n\n\tif [ -n \"$list_len\" ]; then\n\t\tconfig_list_foreach \"$cfg\" \"$opt\" dhcp_option_append \"$networkid\" \"$force\"\n\telse\n\t\tconfig_get dhcp_option \"$cfg\" \"$opt\"\n\n\t\t[ -n \"$dhcp_option\" ] && echo \"Warning: the 'option $opt' syntax is deprecated, use 'list $opt'\" >&2\n\n\t\tlocal option\n\t\tfor option in $dhcp_option; do\n\t\t\tdhcp_option_append \"$option\" \"$networkid\" \"$force\"\n\t\tdone\n\tfi\n}\n\ndhcp_domain_add() {\n\tlocal cfg=\"$1\"\n\tlocal ip name names record\n\n\tconfig_get names \"$cfg\" name \"$2\"\n\t[ -n \"$names\" ] || return 0\n\n\tconfig_get ip \"$cfg\" ip \"$3\"\n\t[ -n \"$ip\" ] || return 0\n\n\tfor name in $names; do\n\t\trecord=\"${record:+$record }$name\"\n\tdone\n\n\techo \"$ip $record\" >> $HOSTFILE_TMP\n}\n\ndhcp_srv_add() {\n\tlocal cfg=\"$1\"\n\n\tconfig_get srv \"$cfg\" srv\n\t[ -n \"$srv\" ] || return 0\n\n\tconfig_get target \"$cfg\" target\n\t[ -n \"$target\" ] || return 0\n\n\tconfig_get port \"$cfg\" port\n\t[ -n \"$port\" ] || return 0\n\n\tconfig_get class \"$cfg\" class\n\tconfig_get weight \"$cfg\" weight\n\n\tlocal service=\"$srv,$target,$port${class:+,$class${weight:+,$weight}}\"\n\n\txappend \"--srv-host=$service\"\n}\n\ndhcp_mx_add() {\n\tlocal cfg=\"$1\"\n\tlocal domain relay pref\n\n\tconfig_get domain \"$cfg\" domain\n\t[ -n \"$domain\" ] || return 0\n\n\tconfig_get relay \"$cfg\" relay\n\t[ -n \"$relay\" ] || return 0\n\n\tconfig_get pref \"$cfg\" pref 0\n\n\tlocal service=\"$domain,$relay,$pref\"\n\n\txappend \"--mx-host=$service\"\n}\n\ndhcp_cname_add() {\n\tlocal cfg=\"$1\"\n\tlocal cname target\n\n\tconfig_get cname \"$cfg\" cname\n\t[ -n \"$cname\" ] || return 0\n\n\tconfig_get target \"$cfg\" target\n\t[ -n \"$target\" ] || return 0\n\n\txappend \"--cname=${cname},${target}\"\n}\n\ndhcp_hostrecord_add() {\n\tlocal cfg=\"$1\"\n\tlocal names addresses record val\n\n\tconfig_get names \"$cfg\" name \"$2\"\n\tif [ -z \"$names\" ]; then\n\t\treturn 0\n\tfi\n\n\tconfig_get addresses \"$cfg\" ip \"$3\"\n\tif [ -z \"$addresses\" ]; then\n\t\treturn 0\n\tfi\n\n\tfor val in $names $addresses; do\n\t\trecord=\"${record:+$record,}$val\"\n\tdone\n\n\txappend \"--host-record=$record\"\n}\n\ndhcp_relay_add() {\n\tlocal cfg=\"$1\"\n\tlocal local_addr server_addr interface\n\n\tconfig_get local_addr \"$cfg\" local_addr\n\t[ -n \"$local_addr\" ] || return 0\n\n\tconfig_get server_addr \"$cfg\" server_addr\n\t[ -n \"$server_addr\" ] || return 0\n\n\tconfig_get interface \"$cfg\" interface\n\tif [ -z \"$interface\" ]; then\n\t\txappend \"--dhcp-relay=$local_addr,$server_addr\"\n\telse\n\t\tnetwork_get_device ifname \"$interface\" || return\n\t\txappend \"--dhcp-relay=$local_addr,$server_addr,$ifname\"\n\tfi\n}\n\ndnsmasq_ipset_add() {\n\tlocal cfg=\"$1\"\n\tlocal ipsets domains\n\n\tadd_ipset() {\n\t\tipsets=\"${ipsets:+$ipsets,}$1\"\n\t}\n\n\tadd_domain() {\n\t\t# leading '/' is expected\n\t\tdomains=\"$domains/$1\"\n\t}\n\n\tconfig_list_foreach \"$cfg\" \"name\" add_ipset\n\tconfig_list_foreach \"$cfg\" \"domain\" add_domain\n\n\tif [ -z \"$ipsets\" ] || [ -z \"$domains\" ]; then\n\t\treturn 0\n\tfi\n\n\txappend \"--ipset=$domains/$ipsets\"\n}\n\ndnsmasq_start()\n{\n\tlocal cfg=\"$1\"\n\tlocal disabled user_dhcpscript logfacility\n\tlocal resolvfile resolvdir localuse=0\n\n\tconfig_get_bool disabled \"$cfg\" disabled 0\n\t[ \"$disabled\" -gt 0 ] && return 0\n\n\t# reset list of DOMAINS, DNS servers and EXTRA mounts (for each dnsmasq instance)\n\tDNS_SERVERS=\"\"\n\tDOMAIN=\"\"\n\tEXTRA_MOUNT=\"\"\n\tCONFIGFILE=\"${BASECONFIGFILE}.${cfg}\"\n\tCONFIGFILE_TMP=\"${CONFIGFILE}.$$\"\n\tHOSTFILE=\"${BASEHOSTFILE}.${cfg}\"\n\tHOSTFILE_TMP=\"${HOSTFILE}.$$\"\n\tHOSTFILE_DIR=\"$(dirname \"$HOSTFILE\")\"\n\tBASEDHCPSTAMPFILE_CFG=\"${BASEDHCPSTAMPFILE}.${cfg}\"\n\n\t# before we can call xappend\n\tumask u=rwx,g=rx,o=rx\n\tmkdir -p /var/run/dnsmasq/\n\tmkdir -p $(dirname $CONFIGFILE)\n\tmkdir -p \"$HOSTFILE_DIR\"\n\tmkdir -p /var/lib/misc\n\tchown dnsmasq:dnsmasq /var/run/dnsmasq\n\n\techo \"# auto-generated config file from /etc/config/dhcp\" > $CONFIGFILE_TMP\n\techo \"# auto-generated config file from /etc/config/dhcp\" > $HOSTFILE_TMP\n\n\tlocal dnsmasqconffile=\"/etc/dnsmasq.${cfg}.conf\"\n\tif [ ! -r \"$dnsmasqconffile\" ]; then\n\t\tdnsmasqconffile=/etc/dnsmasq.conf\n\tfi\n\n\t# if we did this last, we could override auto-generated config\n\t[ -f \"${dnsmasqconffile}\" ] && {\n\t\txappend \"--conf-file=${dnsmasqconffile}\"\n\t}\n\n\t$PROG --version | grep -osqE \"^Compile time options:.* DHCPv6( |$)\" && DHCPv6CAPABLE=1 || DHCPv6CAPABLE=0\n\n\n\tif [ -x /usr/sbin/odhcpd ] && [ -x /etc/init.d/odhcpd ] ; then\n\t\tlocal odhcpd_is_main odhcpd_is_enabled\n\t\tconfig_get odhcpd_is_main odhcpd maindhcp 0\n\t\t/etc/init.d/odhcpd enabled && odhcpd_is_enabled=1 || odhcpd_is_enabled=0\n\n\n\t\tif [ \"$odhcpd_is_enabled\" -eq 0 ] && [ \"$DHCPv6CAPABLE\" -eq 1 ] ; then\n\t\t\t# DHCP V4 and V6 in DNSMASQ\n\t\t\tDNSMASQ_DHCP_VER=6\n\t\telif [ \"$odhcpd_is_main\" -gt 0 ] ; then\n\t\t\t# ODHCPD is doing it all\n\t\t\tDNSMASQ_DHCP_VER=0\n\t\telse\n\t\t\t# You have ODHCPD but use DNSMASQ for DHCPV4\n\t\t\tDNSMASQ_DHCP_VER=4\n\t\tfi\n\n\telif [ \"$DHCPv6CAPABLE\" -eq 1 ] ; then\n\t\t# DHCP V4 and V6 in DNSMASQ\n\t\tDNSMASQ_DHCP_VER=6\n\telse\n\t\tDNSMASQ_DHCP_VER=4\n\tfi\n\n\t# Allow DHCP/DHCPv6 to be handled by ISC DHCPD\n\tif [ -x /usr/sbin/dhcpd ] ; then\n\t\tif [ -x /etc/init.d/dhcpd ] ; then\n\t\t\t/etc/init.d/dhcpd enabled && DNSMASQ_DHCP_VER=0\n\t\tfi\n\t\tif [ -x /etc/init.d/dhcpd6 ] && [ \"$DNSMASQ_DHCP_VER\" -gt 0 ] ; then\n\t\t\t/etc/init.d/dhcpd6 enabled && DNSMASQ_DHCP_VER=4\n\t\tfi\n\tfi\n\n\tappend_bool \"$cfg\" authoritative \"--dhcp-authoritative\"\n\tappend_bool \"$cfg\" nodaemon \"--no-daemon\"\n\tappend_bool \"$cfg\" domainneeded \"--domain-needed\"\n\tappend_bool \"$cfg\" filterwin2k \"--filterwin2k\"\n\tappend_bool \"$cfg\" nohosts \"--no-hosts\"\n\tappend_bool \"$cfg\" nonegcache \"--no-negcache\"\n\tappend_bool \"$cfg\" strictorder \"--strict-order\"\n\tappend_bool \"$cfg\" logqueries \"--log-queries=extra\"\n\tappend_bool \"$cfg\" noresolv \"--no-resolv\"\n\tappend_bool \"$cfg\" localise_queries \"--localise-queries\"\n\tappend_bool \"$cfg\" readethers \"--read-ethers\"\n\n\tlocal instance_name=\"dnsmasq.$cfg\"\n\tif [ \"$cfg\" = \"$DEFAULT_INSTANCE\" ]; then\n\t\tinstance_name=\"dnsmasq\"\n\tfi\n\tconfig_get_bool dbus \"$cfg\" \"dbus\" 0\n\t[ $dbus -gt 0 ] && xappend \"--enable-dbus=uk.org.thekelleys.$instance_name\"\n\tconfig_get_bool ubus \"$cfg\" \"ubus\" 1\n\t[ $ubus -gt 0 ] && xappend \"--enable-ubus=$instance_name\"\n\n\tappend_bool \"$cfg\" expandhosts \"--expand-hosts\"\n\tconfig_get tftp_root \"$cfg\" \"tftp_root\"\n\t[ -n \"$tftp_root\" ] && mkdir -p \"$tftp_root\" && append_bool \"$cfg\" enable_tftp \"--enable-tftp\"\n\tappend_bool \"$cfg\" tftp_no_fail \"--tftp-no-fail\"\n\tappend_bool \"$cfg\" nonwildcard \"--bind-dynamic\" 1\n\tappend_bool \"$cfg\" fqdn \"--dhcp-fqdn\"\n\tappend_bool \"$cfg\" proxydnssec \"--proxy-dnssec\"\n\tappend_bool \"$cfg\" localservice \"--local-service\"\n\tappend_bool \"$cfg\" logdhcp \"--log-dhcp\"\n\tappend_bool \"$cfg\" quietdhcp \"--quiet-dhcp\"\n\tappend_bool \"$cfg\" sequential_ip \"--dhcp-sequential-ip\"\n\tappend_bool \"$cfg\" allservers \"--all-servers\"\n\tappend_bool \"$cfg\" noping \"--no-ping\"\n\tappend_bool \"$cfg\" rapidcommit \"--dhcp-rapid-commit\"\n\tappend_bool \"$cfg\" scriptarp \"--script-arp\"\n\n\tappend_parm \"$cfg\" logfacility \"--log-facility\"\n\tconfig_get logfacility \"$cfg\" \"logfacility\"\n\tappend_parm \"$cfg\" cachesize \"--cache-size\"\n\tappend_parm \"$cfg\" dnsforwardmax \"--dns-forward-max\"\n\tappend_parm \"$cfg\" port \"--port\"\n\tappend_parm \"$cfg\" ednspacket_max \"--edns-packet-max\"\n\tappend_parm \"$cfg\" dhcpleasemax \"--dhcp-lease-max\"\n\tappend_parm \"$cfg\" \"queryport\" \"--query-port\"\n\tappend_parm \"$cfg\" \"minport\" \"--min-port\"\n\tappend_parm \"$cfg\" \"maxport\" \"--max-port\"\n\tappend_parm \"$cfg\" \"domain\" \"--domain\"\n\tappend_parm \"$cfg\" \"local\" \"--local\"\n\tconfig_list_foreach \"$cfg\" \"listen_address\" append_listenaddress\n\tconfig_list_foreach \"$cfg\" \"server\" append_server\n\tconfig_list_foreach \"$cfg\" \"rev_server\" append_rev_server\n\tconfig_list_foreach \"$cfg\" \"address\" append_address\n\tconfig_list_foreach \"$cfg\" \"ipset\" append_ipset\n\n\tlocal connmark_allowlist_enable\n\tconfig_get connmark_allowlist_enable \"$cfg\" connmark_allowlist_enable 0\n\t[ \"$connmark_allowlist_enable\" -gt 0 ] && {\n\t\tappend_parm \"$cfg\" \"connmark_allowlist_enable\" \"--connmark-allowlist-enable\"\n\t\tconfig_list_foreach \"$cfg\" \"connmark_allowlist\" append_connmark_allowlist\n\t}\n\n\t[ -n \"$BOOT\" ] || {\n\t\tconfig_list_foreach \"$cfg\" \"interface\" append_interface\n\t\tconfig_list_foreach \"$cfg\" \"notinterface\" append_notinterface\n\t}\n\tconfig_get_bool ignore_hosts_dir \"$cfg\" ignore_hosts_dir 0\n\tif [ \"$ignore_hosts_dir\" = \"1\" ]; then\n\t\txappend \"--addn-hosts=$HOSTFILE\"\n\t\tappend EXTRA_MOUNT \"$HOSTFILE\"\n\telse\n\t\txappend \"--addn-hosts=$HOSTFILE_DIR\"\n\t\tappend EXTRA_MOUNT \"$HOSTFILE_DIR\"\n\tfi\n\tconfig_list_foreach \"$cfg\" \"addnhosts\" append_addnhosts\n\tconfig_list_foreach \"$cfg\" \"bogusnxdomain\" append_bogusnxdomain\n\tappend_parm \"$cfg\" \"leasefile\" \"--dhcp-leasefile\" \"/tmp/dhcp.leases\"\n\n\tlocal serversfile\n\tconfig_get serversfile \"$cfg\" \"serversfile\"\n\t[ -n \"$serversfile\" ] && {\n\t\txappend \"--servers-file=$serversfile\"\n\t\tappend EXTRA_MOUNT \"$serversfile\"\n\t}\n\n\tappend_parm \"$cfg\" \"tftp_root\" \"--tftp-root\"\n\tappend_parm \"$cfg\" \"dhcp_boot\" \"--dhcp-boot\"\n\tappend_parm \"$cfg\" \"local_ttl\" \"--local-ttl\"\n\tappend_parm \"$cfg\" \"max_ttl\" \"--max-ttl\"\n\tappend_parm \"$cfg\" \"min_cache_ttl\" \"--min-cache-ttl\"\n\tappend_parm \"$cfg\" \"max_cache_ttl\" \"--max-cache-ttl\"\n\tappend_parm \"$cfg\" \"pxe_prompt\" \"--pxe-prompt\"\n\tappend_parm \"$cfg\" \"tftp_unique_root\" \"--tftp-unique-root\"\n\tconfig_list_foreach \"$cfg\" \"pxe_service\" append_pxe_service\n\tconfig_get DOMAIN \"$cfg\" domain\n\n\tconfig_get_bool ADD_LOCAL_DOMAIN \"$cfg\" add_local_domain 1\n\tconfig_get_bool ADD_LOCAL_HOSTNAME \"$cfg\" add_local_hostname 1\n\tconfig_get ADD_LOCAL_FQDN \"$cfg\" add_local_fqdn \"\"\n\tconfig_get ADD_WAN_FQDN \"$cfg\" add_wan_fqdn 0\n\n\tif [ -z \"$ADD_LOCAL_FQDN\" ] ; then\n\t\t# maintain support for previous UCI\n\t\tADD_LOCAL_FQDN=\"$ADD_LOCAL_HOSTNAME\"\n\tfi\n\n\tconfig_get user_dhcpscript $cfg dhcpscript\n\tif has_handler || [ -n \"$user_dhcpscript\" ]; then\n\t\txappend \"--dhcp-script=$DHCPSCRIPT\"\n\t\txappend \"--script-arp\"\n\tfi\n\n\tconfig_get leasefile $cfg leasefile \"/tmp/dhcp.leases\"\n\t[ -n \"$leasefile\" ] && [ ! -e \"$leasefile\" ] && touch \"$leasefile\"\n\tconfig_get_bool cachelocal \"$cfg\" cachelocal 1\n\n\tconfig_get_bool noresolv \"$cfg\" noresolv 0\n\tif [ \"$noresolv\" != \"1\" ]; then\n\t\tconfig_get resolvfile \"$cfg\" resolvfile /tmp/resolv.conf.d/resolv.conf.auto\n\t\t[ -n \"$resolvfile\" ] && [ ! -e \"$resolvfile\" ] && touch \"$resolvfile\"\n\t\txappend \"--resolv-file=$resolvfile\"\n\t\t[ \"$resolvfile\" = \"/tmp/resolv.conf.d/resolv.conf.auto\" ] && localuse=1\n\t\tresolvdir=\"$(dirname \"$resolvfile\")\"\n\tfi\n\tconfig_get_bool localuse \"$cfg\" localuse \"$localuse\"\n\n\tconfig_get hostsfile \"$cfg\" dhcphostsfile\n\t[ -e \"$hostsfile\" ] && xappend \"--dhcp-hostsfile=$hostsfile\"\n\n\tlocal rebind\n\tconfig_get_bool rebind \"$cfg\" rebind_protection 1\n\t[ $rebind -gt 0 ] && {\n\t\tlog_once \\\n\t\t\t\"DNS rebinding protection is active,\" \\\n\t\t\t\"will discard upstream RFC1918 responses!\"\n\t\txappend \"--stop-dns-rebind\"\n\n\t\tlocal rebind_localhost\n\t\tconfig_get_bool rebind_localhost \"$cfg\" rebind_localhost 0\n\t\t[ $rebind_localhost -gt 0 ] && {\n\t\t\tlog_once \"Allowing 127.0.0.0/8 responses\"\n\t\t\txappend \"--rebind-localhost-ok\"\n\t\t}\n\n\t\tappend_rebind_domain() {\n\t\t\tlog_once \"Allowing RFC1918 responses for domain $1\"\n\t\t\txappend \"--rebind-domain-ok=$1\"\n\t\t}\n\n\t\tconfig_list_foreach \"$cfg\" rebind_domain append_rebind_domain\n\t}\n\n\tconfig_get_bool dnssec \"$cfg\" dnssec 0\n\t[ \"$dnssec\" -gt 0 ] && {\n\t\txappend \"--conf-file=$TRUSTANCHORSFILE\"\n\t\txappend \"--dnssec\"\n\t\t[ -x /etc/init.d/sysntpd ] && {\n\t\t\tif /etc/init.d/sysntpd enabled || [ \"$(uci_get system.ntp.enabled)\" = \"1\" ] ; then\n\t\t\t\t[ -f \"$TIMEVALIDFILE\" ] || xappend \"--dnssec-no-timecheck\"\n\t\t\tfi\n\t\t}\n\t\tconfig_get_bool dnsseccheckunsigned \"$cfg\" dnsseccheckunsigned 1\n\t\t[ \"$dnsseccheckunsigned\" -eq 0 ] && xappend \"--dnssec-check-unsigned=no\"\n\t}\n\n\tconfig_get addmac \"$cfg\" addmac 0\n\t[ \"$addmac\" != \"0\" ] && {\n\t\t[ \"$addmac\" = \"1\" ] && addmac=\n\t\txappend \"--add-mac${addmac:+=\"$addmac\"}\"\n\t}\n\n\tdhcp_option_add \"$cfg\" \"\" 0\n\tdhcp_option_add \"$cfg\" \"\" 2\n\n\txappend \"--dhcp-broadcast=tag:needs-broadcast\"\n\n\n\tconfig_get dnsmasqconfdir \"$cfg\" confdir \"/tmp/dnsmasq.d\"\n\txappend \"--conf-dir=$dnsmasqconfdir\"\n\tdnsmasqconfdir=\"${dnsmasqconfdir%%,*}\"\n\t[ ! -d \"$dnsmasqconfdir\" ] && mkdir -p $dnsmasqconfdir\n\txappend \"--user=dnsmasq\"\n\txappend \"--group=dnsmasq\"\n\techo >> $CONFIGFILE_TMP\n\n\tconfig_get_bool enable_tftp \"$cfg\" enable_tftp 0\n\t[ \"$enable_tftp\" -gt 0 ] && {\n\t\tconfig_get tftp_root \"$cfg\" tftp_root\n\t\tappend EXTRA_MOUNT $tftp_root\n\t}\n\n\tconfig_foreach filter_dnsmasq host dhcp_host_add \"$cfg\"\n\techo >> $CONFIGFILE_TMP\n\n\tconfig_get_bool dhcpbogushostname \"$cfg\" dhcpbogushostname 1\n\t[ \"$dhcpbogushostname\" -gt 0 ] && {\n\t\txappend \"--dhcp-ignore-names=tag:dhcp_bogus_hostname\"\n\t\t[ -r \"$DHCPBOGUSHOSTNAMEFILE\" ] && xappend \"--conf-file=$DHCPBOGUSHOSTNAMEFILE\"\n\t}\n\n\tconfig_foreach filter_dnsmasq boot dhcp_boot_add \"$cfg\"\n\tconfig_foreach filter_dnsmasq mac dhcp_mac_add \"$cfg\"\n\tconfig_foreach filter_dnsmasq tag dhcp_tag_add \"$cfg\"\n\tconfig_foreach filter_dnsmasq vendorclass dhcp_vendorclass_add \"$cfg\"\n\tconfig_foreach filter_dnsmasq userclass dhcp_userclass_add \"$cfg\"\n\tconfig_foreach filter_dnsmasq circuitid dhcp_circuitid_add \"$cfg\"\n\tconfig_foreach filter_dnsmasq remoteid dhcp_remoteid_add \"$cfg\"\n\tconfig_foreach filter_dnsmasq subscrid dhcp_subscrid_add \"$cfg\"\n\tconfig_foreach filter_dnsmasq match dhcp_match_add \"$cfg\"\n\tconfig_foreach filter_dnsmasq domain dhcp_domain_add \"$cfg\"\n\tconfig_foreach filter_dnsmasq hostrecord dhcp_hostrecord_add \"$cfg\"\n\t[ -n \"$BOOT\" ] || config_foreach filter_dnsmasq relay dhcp_relay_add \"$cfg\"\n\n\techo >> $CONFIGFILE_TMP\n\tconfig_foreach filter_dnsmasq srvhost dhcp_srv_add \"$cfg\"\n\tconfig_foreach filter_dnsmasq mxhost dhcp_mx_add \"$cfg\"\n\techo >> $CONFIGFILE_TMP\n\n\tconfig_get_bool boguspriv \"$cfg\" boguspriv 1\n\t[ \"$boguspriv\" -gt 0 ] && {\n\t\txappend \"--bogus-priv\"\n\t\t[ -r \"$RFC6761FILE\" ] && xappend \"--conf-file=$RFC6761FILE\"\n\t}\n\n\tif [ \"$DNSMASQ_DHCP_VER\" -gt 4 ] ; then\n\t\t# Enable RA feature for when/if it is constructed,\n\t\t# and RA is selected per interface pool (RA, DHCP, or both),\n\t\t# but no one (should) want RA broadcast in syslog\n\t\t[ -n \"$BOOT\" ] || config_foreach filter_dnsmasq dhcp dhcp_add \"$cfg\"\n\t\txappend \"--enable-ra\"\n\t\txappend \"--quiet-ra\"\n\t\tappend_bool \"$cfg\" quietdhcp \"--quiet-dhcp6\"\n\n\telif [ \"$DNSMASQ_DHCP_VER\" -gt 0 ] ; then\n\t\t[ -n \"$BOOT\" ] || config_foreach filter_dnsmasq dhcp dhcp_add \"$cfg\"\n\tfi\n\n\n\techo >> $CONFIGFILE_TMP\n\tconfig_foreach filter_dnsmasq cname dhcp_cname_add \"$cfg\"\n\techo >> $CONFIGFILE_TMP\n\n\techo >> $CONFIGFILE_TMP\n\tconfig_foreach filter_dnsmasq ipset dnsmasq_ipset_add \"$cfg\"\n\techo >> $CONFIGFILE_TMP\n\n\techo >> $CONFIGFILE_TMP\n\tmv -f $CONFIGFILE_TMP $CONFIGFILE\n\tmv -f $HOSTFILE_TMP $HOSTFILE\n\n\t[ \"$localuse\" -gt 0 ] && {\n\t\trm -f /tmp/resolv.conf\n\t\t[ $ADD_LOCAL_DOMAIN -eq 1 ] && [ -n \"$DOMAIN\" ] && {\n\t\t\techo \"search $DOMAIN\" >> /tmp/resolv.conf\n\t\t}\n\t\tDNS_SERVERS=\"$DNS_SERVERS 127.0.0.1\"\n\t\t[ -e /proc/sys/net/ipv6 ] && DNS_SERVERS=\"$DNS_SERVERS ::1\"\n\t\tfor DNS_SERVER in $DNS_SERVERS ; do\n\t\t\techo \"nameserver $DNS_SERVER\" >> /tmp/resolv.conf\n\t\tdone\n\t}\n\n\tprocd_open_instance $cfg\n\tprocd_set_param command $PROG -C $CONFIGFILE -k -x /var/run/dnsmasq/dnsmasq.\"${cfg}\".pid\n\tprocd_set_param file $CONFIGFILE\n\t[ -n \"$user_dhcpscript\" ] && procd_set_param env USER_DHCPSCRIPT=\"$user_dhcpscript\"\n\tprocd_set_param respawn\n\n\tlocal instance_ifc instance_netdev\n\tconfig_get instance_ifc \"$cfg\" interface\n\t[ -n \"$instance_ifc\" ] && network_get_device instance_netdev \"$instance_ifc\" &&\n\t\t[ -n \"$instance_netdev\" ] && procd_set_param netdev $instance_netdev\n\n\tprocd_add_jail dnsmasq ubus log\n\tprocd_add_jail_mount $CONFIGFILE $DHCPBOGUSHOSTNAMEFILE $DHCPSCRIPT $DHCPSCRIPT_DEPENDS\n\tprocd_add_jail_mount $EXTRA_MOUNT $RFC6761FILE $TRUSTANCHORSFILE\n\tprocd_add_jail_mount $dnsmasqconffile $dnsmasqconfdir $resolvdir $user_dhcpscript\n\tprocd_add_jail_mount /etc/passwd /etc/group /etc/TZ /etc/hosts /etc/ethers\n\tprocd_add_jail_mount_rw /var/run/dnsmasq/ $leasefile\n\tcase \"$logfacility\" in */*)\n\t\t[ ! -e \"$logfacility\" ] && touch \"$logfacility\"\n\t\tprocd_add_jail_mount_rw \"$logfacility\"\n\tesac\n\n\tprocd_close_instance\n}\n\ndnsmasq_stop()\n{\n\tlocal cfg=\"$1\"\n\tlocal noresolv resolvfile localuse=0\n\n\tconfig_get_bool noresolv \"$cfg\" noresolv 0\n\tconfig_get resolvfile \"$cfg\" \"resolvfile\"\n\n\t[ \"$noresolv\" = 0 ] && [ \"$resolvfile\" = \"/tmp/resolv.conf.d/resolv.conf.auto\" ] && localuse=1\n\tconfig_get_bool localuse \"$cfg\" localuse \"$localuse\"\n\t[ \"$localuse\" -gt 0 ] && ln -sf \"/tmp/resolv.conf.d/resolv.conf.auto\" /tmp/resolv.conf\n\n\trm -f ${BASEDHCPSTAMPFILE}.${cfg}.*.dhcp\n}\n\nadd_interface_trigger()\n{\n\tlocal interface ignore\n\n\tconfig_get interface \"$1\" interface\n\tconfig_get_bool ignore \"$1\" ignore 0\n\n\t[ -n \"$interface\" ] && [ $ignore -eq 0 ] && procd_add_interface_trigger \"interface.*\" \"$interface\" /etc/init.d/dnsmasq reload\n}\n\nservice_triggers()\n{\n\tprocd_add_reload_trigger \"dhcp\" \"system\"\n\n\tconfig_load dhcp\n\tconfig_foreach add_interface_trigger dhcp\n\tconfig_foreach add_interface_trigger relay\n}\n\nboot()\n{\n\tBOOT=1\n\tstart \"$@\"\n}\n\nstart_service() {\n\tlocal instance=\"$1\"\n\tlocal instance_found=0\n\tlocal first_instance=\"\"\n\n\t. /lib/functions/network.sh\n\n\tconfig_cb() {\n\t\tlocal type=\"$1\"\n\t\tlocal name=\"$2\"\n\t\tif [ \"$type\" = \"dnsmasq\" ]; then\n\t\t\tif [ -n \"$instance\" ] && [ \"$instance\" = \"$name\" ]; then\n\t\t\t\tinstance_found=1\n\t\t\tfi\n\t\t\tif [ -z \"$DEFAULT_INSTANCE\" ]; then\n\t\t\t\tlocal disabled\n\t\t\t\tconfig_get_bool disabled \"$name\" disabled 0\n\t\t\t\tif [ \"$disabled\" -eq 0 ]; then\n\t\t\t\t\t# First enabled section will be assigned default instance name.\n\t\t\t\t\t# Unnamed sections get precedence over named sections.\n\t\t\t\t\tif expr \"$cfg\" : 'cfg[0-9a-f]*$' >/dev/null = \"9\"; then # See uci_fixup_section.\n\t\t\t\t\t\tDEFAULT_INSTANCE=\"$name\" # Unnamed config section.\n\t\t\t\t\telif [ -z \"$first_instance\" ]; then\n\t\t\t\t\t\tfirst_instance=\"$name\"\n\t\t\t\t\tfi\n\t\t\t\tfi\n\t\t\tfi\n\t\tfi\n\t}\n\n\tDEFAULT_INSTANCE=\"\"\n\tconfig_load dhcp\n\tif [ -z \"$DEFAULT_INSTANCE\" ]; then\n\t\tDEFAULT_INSTANCE=\"$first_instance\" # No unnamed config section was found.\n\tfi\n\n\tif [ -n \"$instance\" ]; then\n\t\t[ \"$instance_found\" -gt 0 ] || return\n\t\tdnsmasq_start \"$instance\"\n\telse\n\t\tconfig_foreach dnsmasq_start dnsmasq\n\tfi\n}\n\nreload_service() {\n\trc_procd start_service \"$@\"\n\tprocd_send_signal dnsmasq \"$@\"\n}\n\nstop_service() {\n\tlocal instance=\"$1\"\n\tlocal instance_found=0\n\n\tconfig_cb() {\n\t\tlocal type=\"$1\"\n\t\tlocal name=\"$2\"\n\t\tif [ \"$type\" = \"dnsmasq\" ]; then\n\t\t\tif [ -n \"$instance\" ] && [ \"$instance\" = \"$name\" ]; then\n\t\t\t\tinstance_found=1\n\t\t\tfi\n\t\tfi\n\t}\n\n\tconfig_load dhcp\n\n\tif [ -n \"$instance\" ]; then\n\t\t[ \"$instance_found\" -gt 0 ] || return\n\t\tdnsmasq_stop \"$instance\"\n\telse\n\t\tconfig_foreach dnsmasq_stop dnsmasq\n\tfi\n}\n"
  },
  {
    "path": "package/network/services/dnsmasq/files/dnsmasq_acl.json",
    "content": "{\n\t\"user\": \"dnsmasq\",\n\t\"publish\": [ \"dnsmasq\" ],\n\t\"access\": {\n\t\t\"hotplug.dhcp\": {\n\t\t\t\"methods\": [ \"call\" ]\n\t\t},\n\t\t\"hotplug.neigh\": {\n\t\t\t\"methods\": [ \"call\" ]\n\t\t},\n\t\t\"hotplug.tftp\": {\n\t\t\t\"methods\": [ \"call\" ]\n\t\t}\n\t}\n}\n"
  },
  {
    "path": "package/network/services/dnsmasq/files/dnsmasqsec.hotplug",
    "content": "TIMEVALIDFILE=\"/var/state/dnsmasqsec\"\n\n[ \"$ACTION\" = \"stratum\" ] || exit 0\n\n[ -f \"$TIMEVALIDFILE\" ] || {\n\techo \"ntpd says time is valid\" >$TIMEVALIDFILE\n\t/etc/init.d/dnsmasq enabled && {\n\t\tinitscript=dnsmasq\n\t\t. /lib/functions/procd.sh\n\t\tprocd_send_signal dnsmasq '*' INT\n\t}\n}\n"
  },
  {
    "path": "package/network/services/dnsmasq/files/rfc6761.conf",
    "content": "# RFC6761 included configuration file for dnsmasq\n#\n# includes a list of domains that should not be forwarded to Internet name servers\n# to reduce burden on them, asking questions that they won't know the answer to.\n\nserver=/bind/\nserver=/invalid/\nserver=/local/\nserver=/localhost/\nserver=/onion/\nserver=/test/\n"
  },
  {
    "path": "package/network/services/dnsmasq/patches/100-remove-old-runtime-kernel-support.patch",
    "content": "From 02fbe60e1c7e74d2ba57109575e7bfc238b1b5d4 Mon Sep 17 00:00:00 2001\nFrom: Kevin Darbyshire-Bryant <ldir@darbyshire-bryant.me.uk>\nDate: Sun, 5 Apr 2020 17:18:23 +0100\nSubject: [PATCH] drop runtime old kernel support\n\nSigned-off-by: Kevin Darbyshire-Bryant <ldir@darbyshire-bryant.me.uk>\n---\n src/dnsmasq.c |  4 ----\n src/dnsmasq.h |  5 +---\n src/ipset.c   | 64 ++++-----------------------------------------------\n src/util.c    | 19 ---------------\n 4 files changed, 5 insertions(+), 87 deletions(-)\n\n--- a/src/dnsmasq.c\n+++ b/src/dnsmasq.c\n@@ -95,10 +95,6 @@ int main (int argc, char **argv)\n   \n   read_opts(argc, argv, compile_opts);\n  \n-#ifdef HAVE_LINUX_NETWORK\n-  daemon->kernel_version = kernel_version();\n-#endif\n-\n   if (daemon->edns_pktsz < PACKETSZ)\n     daemon->edns_pktsz = PACKETSZ;\n \n--- a/src/dnsmasq.h\n+++ b/src/dnsmasq.h\n@@ -1201,7 +1201,7 @@ extern struct daemon {\n   int inotifyfd;\n #endif\n #if defined(HAVE_LINUX_NETWORK)\n-  int netlinkfd, kernel_version;\n+  int netlinkfd;\n #elif defined(HAVE_BSD_NETWORK)\n   int dhcp_raw_fd, dhcp_icmp_fd, routefd;\n #endif\n@@ -1388,9 +1388,6 @@ int read_write(int fd, unsigned char *pa\n void close_fds(long max_fd, int spare1, int spare2, int spare3);\n int wildcard_match(const char* wildcard, const char* match);\n int wildcard_matchn(const char* wildcard, const char* match, int num);\n-#ifdef HAVE_LINUX_NETWORK\n-int kernel_version(void);\n-#endif\n \n /* log.c */\n void die(char *message, char *arg1, int exit_code) ATTRIBUTE_NORETURN;\n--- a/src/ipset.c\n+++ b/src/ipset.c\n@@ -70,7 +70,7 @@ struct my_nfgenmsg {\n \n #define NL_ALIGN(len) (((len)+3) & ~(3))\n static const struct sockaddr_nl snl = { .nl_family = AF_NETLINK };\n-static int ipset_sock, old_kernel;\n+static int ipset_sock;\n static char *buffer;\n \n static inline void add_attr(struct nlmsghdr *nlh, uint16_t type, size_t len, const void *data)\n@@ -85,12 +85,7 @@ static inline void add_attr(struct nlmsg\n \n void ipset_init(void)\n {\n-  old_kernel = (daemon->kernel_version < KERNEL_VERSION(2,6,32));\n-  \n-  if (old_kernel && (ipset_sock = socket(AF_INET, SOCK_RAW, IPPROTO_RAW)) != -1)\n-    return;\n-  \n-  if (!old_kernel && \n+  if (\n       (buffer = safe_malloc(BUFF_SZ)) &&\n       (ipset_sock = socket(AF_NETLINK, SOCK_RAW, NETLINK_NETFILTER)) != -1 &&\n       (bind(ipset_sock, (struct sockaddr *)&snl, sizeof(snl)) != -1))\n@@ -147,65 +142,14 @@ static int new_add_to_ipset(const char *\n   return errno == 0 ? 0 : -1;\n }\n \n-\n-static int old_add_to_ipset(const char *setname, const union all_addr *ipaddr, int remove)\n-{\n-  socklen_t size;\n-  struct ip_set_req_adt_get {\n-    unsigned op;\n-    unsigned version;\n-    union {\n-      char name[IPSET_MAXNAMELEN];\n-      uint16_t index;\n-    } set;\n-    char typename[IPSET_MAXNAMELEN];\n-  } req_adt_get;\n-  struct ip_set_req_adt {\n-    unsigned op;\n-    uint16_t index;\n-    uint32_t ip;\n-  } req_adt;\n-  \n-  if (strlen(setname) >= sizeof(req_adt_get.set.name)) \n-    {\n-      errno = ENAMETOOLONG;\n-      return -1;\n-    }\n-  \n-  req_adt_get.op = 0x10;\n-  req_adt_get.version = 3;\n-  strcpy(req_adt_get.set.name, setname);\n-  size = sizeof(req_adt_get);\n-  if (getsockopt(ipset_sock, SOL_IP, 83, &req_adt_get, &size) < 0)\n-    return -1;\n-  req_adt.op = remove ? 0x102 : 0x101;\n-  req_adt.index = req_adt_get.set.index;\n-  req_adt.ip = ntohl(ipaddr->addr4.s_addr);\n-  if (setsockopt(ipset_sock, SOL_IP, 83, &req_adt, sizeof(req_adt)) < 0)\n-    return -1;\n-  \n-  return 0;\n-}\n-\n-\n-\n int add_to_ipset(const char *setname, const union all_addr *ipaddr, int flags, int remove)\n {\n   int ret = 0, af = AF_INET;\n \n   if (flags & F_IPV6)\n-    {\n       af = AF_INET6;\n-      /* old method only supports IPv4 */\n-      if (old_kernel)\n-\t{\n-\t  errno = EAFNOSUPPORT ;\n-\t  ret = -1;\n-\t}\n-    }\n-  \n-  if (ret != -1) \n-    ret = old_kernel ? old_add_to_ipset(setname, ipaddr, remove) : new_add_to_ipset(setname, ipaddr, af, remove);\n+\n+  ret = new_add_to_ipset(setname, ipaddr, af, remove);\n \n   if (ret == -1)\n      my_syslog(LOG_ERR, _(\"failed to update ipset %s: %s\"), setname, strerror(errno));\n--- a/src/util.c\n+++ b/src/util.c\n@@ -796,22 +796,3 @@ int wildcard_matchn(const char* wildcard\n \n   return (!num) || (*wildcard == *match);\n }\n-\n-#ifdef HAVE_LINUX_NETWORK\n-int kernel_version(void)\n-{\n-  struct utsname utsname;\n-  int version;\n-  char *split;\n-  \n-  if (uname(&utsname) < 0)\n-    die(_(\"failed to find kernel version: %s\"), NULL, EC_MISC);\n-  \n-  split = strtok(utsname.release, \".\");\n-  version = (split ? atoi(split) : 0);\n-  split = strtok(NULL, \".\");\n-  version = version * 256 + (split ? atoi(split) : 0);\n-  split = strtok(NULL, \".\");\n-  return version * 256 + (split ? atoi(split) : 0);\n-}\n-#endif\n"
  },
  {
    "path": "package/network/services/dnsmasq/patches/200-ubus_dns.patch",
    "content": "--- a/src/dnsmasq.h\n+++ b/src/dnsmasq.h\n@@ -1564,14 +1564,26 @@ void emit_dbus_signal(int action, struct\n \n /* ubus.c */\n #ifdef HAVE_UBUS\n+struct blob_attr;\n+typedef void (*ubus_dns_notify_cb)(struct blob_attr *msg, void *priv);\n+\n char *ubus_init(void);\n void set_ubus_listeners(void);\n void check_ubus_listeners(void);\n+void drop_ubus_listeners(void);\n+struct blob_buf *ubus_dns_notify_prepare(void);\n+int ubus_dns_notify(const char *type, ubus_dns_notify_cb cb, void *priv);\n void ubus_event_bcast(const char *type, const char *mac, const char *ip, const char *name, const char *interface);\n #  ifdef HAVE_CONNTRACK\n void ubus_event_bcast_connmark_allowlist_refused(u32 mark, const char *name);\n void ubus_event_bcast_connmark_allowlist_resolved(u32 mark, const char *pattern, const char *ip, u32 ttl);\n #  endif\n+#else\n+struct blob_buf;\n+static inline struct blob_buf *ubus_dns_notify_prepare(void)\n+{\n+\treturn NULL;\n+}\n #endif\n \n /* ipset.c */\n--- a/src/rfc1035.c\n+++ b/src/rfc1035.c\n@@ -13,8 +13,10 @@\n    You should have received a copy of the GNU General Public License\n    along with this program.  If not, see <http://www.gnu.org/licenses/>.\n */\n-\n #include \"dnsmasq.h\"\n+#ifdef HAVE_UBUS\n+#include <libubox/blobmsg.h>\n+#endif\n \n int extract_name(struct dns_header *header, size_t plen, unsigned char **pp, \n \t\t char *name, int isExtract, int extrabytes)\n@@ -394,9 +396,64 @@ static int private_net6(struct in6_addr\n     ((u32 *)a)[0] == htonl(0x20010db8); /* RFC 6303 4.6 */\n }\n \n+#ifdef HAVE_UBUS\n+static void ubus_dns_doctor_cb(struct blob_attr *msg, void *priv)\n+{\n+\tstatic const struct blobmsg_policy policy = {\n+\t\t.name = \"address\",\n+\t\t.type = BLOBMSG_TYPE_STRING,\n+\t};\n+\tstruct blob_attr *val;\n+\tchar **dest = priv;\n+\n+\tblobmsg_parse(&policy, 1, &val, blobmsg_data(msg), blobmsg_data_len(msg));\n+\tif (val)\n+\t\t*dest = blobmsg_get_string(val);\n+}\n+\n+static int ubus_dns_doctor(const char *name, int ttl, void *p, int af)\n+{\n+\tstruct blob_buf *b;\n+\tchar *addr;\n+\n+\tif (!name)\n+\t\treturn 0;\n+\n+\tb = ubus_dns_notify_prepare();\n+\tif (!b)\n+\t\treturn 0;\n+\n+\tblobmsg_add_string(b, \"name\", name);\n+\n+\tblobmsg_add_u32(b, \"ttl\", ttl);\n+\n+\tblobmsg_add_string(b, \"type\", af == AF_INET6 ? \"AAAA\" : \"A\");\n+\n+\taddr = blobmsg_alloc_string_buffer(b, \"address\", INET6_ADDRSTRLEN);\n+\tif (!addr)\n+\t\treturn 0;\n+\n+\tinet_ntop(af, p, addr, INET6_ADDRSTRLEN);\n+\tblobmsg_add_string_buffer(b);\n+\n+\taddr = NULL;\n+\tubus_dns_notify(\"dns_result\", ubus_dns_doctor_cb, &addr);\n+\n+\tif (!addr)\n+\t\treturn 0;\n+\n+\treturn inet_pton(af, addr, p) == 1;\n+}\n+#else\n+static int ubus_dns_doctor(const char *name, int ttl, void *p, int af)\n+{\n+\treturn 0;\n+}\n+#endif\n+\n static unsigned char *do_doctor(unsigned char *p, int count, struct dns_header *header, size_t qlen, int *doctored)\n {\n-  int i, qtype, qclass, rdlen;\n+  int i, qtype, qclass, rdlen, ttl;\n \n   for (i = count; i != 0; i--)\n     {\n@@ -405,7 +462,7 @@ static unsigned char *do_doctor(unsigned\n       \n       GETSHORT(qtype, p); \n       GETSHORT(qclass, p);\n-      p += 4; /* ttl */\n+      GETLONG(ttl, p); /* ttl */\n       GETSHORT(rdlen, p);\n       \n       if (qclass == C_IN && qtype == T_A)\n@@ -416,6 +473,9 @@ static unsigned char *do_doctor(unsigned\n \t  if (!CHECK_LEN(header, p, qlen, INADDRSZ))\n \t    return 0;\n \t  \n+\t  if (ubus_dns_doctor(daemon->namebuff, ttl, p, AF_INET))\n+\t    *doctored = 1;\n+\n \t  /* alignment */\n \t  memcpy(&addr, p, INADDRSZ);\n \t  \n@@ -433,13 +493,22 @@ static unsigned char *do_doctor(unsigned\n \t      addr.s_addr &= ~doctor->mask.s_addr;\n \t      addr.s_addr |= (doctor->out.s_addr & doctor->mask.s_addr);\n \t      /* Since we munged the data, the server it came from is no longer authoritative */\n-\t      header->hb3 &= ~HB3_AA;\n \t      *doctored = 1;\n \t      memcpy(p, &addr, INADDRSZ);\n \t      break;\n \t    }\n \t}\n-      \n+      else if (qclass == C_IN && qtype == T_AAAA)\n+        {\n+\t  if (!CHECK_LEN(header, p, qlen, IN6ADDRSZ))\n+\t    return 0;\n+\n+\t  if (ubus_dns_doctor(daemon->namebuff, ttl, p, AF_INET6))\n+\t    *doctored = 1;\n+\t}\n+\n+      if (*doctored)\n+        header->hb3 &= ~HB3_AA;\n       if (!ADD_RDLEN(header, p, qlen, rdlen))\n \t return 0; /* bad packet */\n     }\n@@ -563,7 +632,7 @@ int extract_addresses(struct dns_header\n   cache_start_insert();\n \n   /* find_soa is needed for dns_doctor side effects, so don't call it lazily if there are any. */\n-  if (daemon->doctors || option_bool(OPT_DNSSEC_VALID))\n+  if (daemon->doctors || option_bool(OPT_DNSSEC_VALID) || ubus_dns_notify_prepare())\n     {\n       searched_soa = 1;\n       ttl = find_soa(header, qlen, doctored);\n--- a/src/ubus.c\n+++ b/src/ubus.c\n@@ -72,6 +72,13 @@ static struct ubus_object ubus_object =\n   .subscribe_cb = ubus_subscribe_cb,\n };\n \n+static struct ubus_object_type ubus_dns_object_type =\n+   { .name = \"dnsmasq.dns\" };\n+\n+static struct ubus_object ubus_dns_object = {\n+\t.type = &ubus_dns_object_type,\n+};\n+\n static void ubus_subscribe_cb(struct ubus_context *ctx, struct ubus_object *obj)\n {\n   (void)ctx;\n@@ -105,13 +112,21 @@ static void ubus_disconnect_cb(struct ub\n char *ubus_init()\n {\n   struct ubus_context *ubus = NULL;\n+  char *dns_name;\n   int ret = 0;\n \n   if (!(ubus = ubus_connect(NULL)))\n     return NULL;\n   \n+  dns_name = whine_malloc(strlen(daemon->ubus_name) + 5);\n+  sprintf(dns_name, \"%s.dns\", daemon->ubus_name);\n+\n   ubus_object.name = daemon->ubus_name;\n+  ubus_dns_object.name = dns_name;\n+\n   ret = ubus_add_object(ubus, &ubus_object);\n+  if (!ret)\n+    ret = ubus_add_object(ubus, &ubus_dns_object);\n   if (ret)\n     {\n       ubus_destroy(ubus);\n@@ -181,6 +196,17 @@ void check_ubus_listeners()\n       } \\\n   } while (0)\n \n+void drop_ubus_listeners()\n+{\n+  struct ubus_context *ubus = (struct ubus_context *)daemon->ubus;\n+\n+  if (!ubus)\n+    return;\n+\n+  ubus_free(ubus);\n+  ubus = NULL;\n+}\n+\n static int ubus_handle_metrics(struct ubus_context *ctx, struct ubus_object *obj,\n \t\t\t       struct ubus_request_data *req, const char *method,\n \t\t\t       struct blob_attr *msg)\n@@ -328,6 +354,50 @@ fail:\n       } \\\n   } while (0)\n \n+struct blob_buf *ubus_dns_notify_prepare(void)\n+{\n+  struct ubus_context *ubus = (struct ubus_context *)daemon->ubus;\n+\n+\tif (!ubus || !ubus_dns_object.has_subscribers)\n+\t\treturn NULL;\n+\n+\tblob_buf_init(&b, 0);\n+\treturn &b;\n+}\n+\n+struct ubus_dns_notify_req {\n+\tstruct ubus_notify_request req;\n+\tubus_dns_notify_cb cb;\n+\tvoid *priv;\n+};\n+\n+static void dns_notify_cb(struct ubus_notify_request *req, int type, struct blob_attr *msg)\n+{\n+\tstruct ubus_dns_notify_req *dreq = container_of(req, struct ubus_dns_notify_req, req);\n+\n+\tdreq->cb(msg, dreq->priv);\n+}\n+\n+int ubus_dns_notify(const char *type, ubus_dns_notify_cb cb, void *priv)\n+{\n+\tstruct ubus_context *ubus = (struct ubus_context *)daemon->ubus;\n+\tstruct ubus_dns_notify_req dreq;\n+\tint ret;\n+\n+\tif (!ubus || !ubus_dns_object.has_subscribers)\n+\t\treturn 0;\n+\n+\tret = ubus_notify_async(ubus, &ubus_dns_object, type, b.head, &dreq.req);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tdreq.req.data_cb = dns_notify_cb;\n+\tdreq.cb = cb;\n+\tdreq.priv = priv;\n+\n+\treturn ubus_complete_request(ubus, &dreq.req.req, 100);\n+}\n+\n void ubus_event_bcast(const char *type, const char *mac, const char *ip, const char *name, const char *interface)\n {\n   struct ubus_context *ubus = (struct ubus_context *)daemon->ubus;\n--- a/src/dnsmasq.c\n+++ b/src/dnsmasq.c\n@@ -1972,6 +1972,10 @@ static void check_dns_listeners(time_t n\n \t\t  daemon->pipe_to_parent = pipefd[1];\n \t\t}\n \n+#ifdef HAVE_UBUS\n+\t      drop_ubus_listeners();\n+#endif\n+\n \t      /* start with no upstream connections. */\n \t      for (s = daemon->servers; s; s = s->next)\n \t\t s->tcpfd = -1; \n"
  },
  {
    "path": "package/network/services/dropbear/Config.in",
    "content": "menu \"Configuration\"\n\tdepends on PACKAGE_dropbear\n\nconfig DROPBEAR_CURVE25519\n\tbool \"Curve25519 support\"\n\tdefault y\n\thelp\n\t\tThis enables the following key exchange algorithm:\n\t\t  curve25519-sha256@libssh.org\n\n\t\tIncreases binary size by about 4 kB (MIPS).\n\nconfig DROPBEAR_ECC\n\tbool \"Elliptic curve cryptography (ECC)\"\n\tdefault n\n\thelp\n\t\tEnables basic support for elliptic curve cryptography (ECC)\n\t\tin key exchange and public key authentication.\n\n\t\tKey exchange algorithms:\n\t\t  ecdh-sha2-nistp256\n\n\t\tPublic key algorithms:\n\t\t  ecdsa-sha2-nistp256\n\n\t\tIncreases binary size by about 24 kB (MIPS).\n\n\t\tIf full ECC support is required, also select DROPBEAR_ECC_FULL.\n\nconfig DROPBEAR_ECC_FULL\n\tbool \"Elliptic curve cryptography (ECC), full support\"\n\tdefault n\n\tdepends on DROPBEAR_ECC\n\thelp\n\t\tEnables full support for elliptic curve cryptography (ECC)\n\t\tin key exchange and public key authentication.\n\n\t\tKey exchange algorithms:\n\t\t  ecdh-sha2-nistp256 (*)\n\t\t  ecdh-sha2-nistp384\n\t\t  ecdh-sha2-nistp521\n\n\t\tPublic key algorithms:\n\t\t  ecdsa-sha2-nistp256 (*)\n\t\t  ecdsa-sha2-nistp384\n\t\t  ecdsa-sha2-nistp521\n\n\t\t(*) - basic ECC support; provided by DROPBEAR_ECC.\n\n\t\tIncreases binary size by about 4 kB (MIPS).\n\nconfig DROPBEAR_ED25519\n\tbool \"Ed25519 support\"\n\tdefault y if !SMALL_FLASH\n\thelp\n\t\tThis enables the following public key algorithm:\n\t\t  ssh-ed25519\n\n\t\tIncreases binary size by about 12 kB (MIPS).\n\nconfig DROPBEAR_CHACHA20POLY1305\n\tbool \"Chacha20-Poly1305 support\"\n\tdefault y\n\thelp\n\t\tThis enables the following authenticated encryption cipher:\n\t\t  chacha20-poly1305@openssh.com\n\n\t\tIncreases binary size by about 4 kB (MIPS).\n\nconfig DROPBEAR_ZLIB\n\tbool \"Enable compression\"\n\tdefault n\n\thelp\n\t\tEnables compression using shared zlib library.\n\n\t\tIncreases binary size by about 0.1 kB (MIPS) and requires additional 62 kB (MIPS)\n\t\tfor a shared zlib library.\n\nconfig DROPBEAR_UTMP\n\tbool \"Utmp support\"\n\tdefault n\n\tdepends on BUSYBOX_CONFIG_FEATURE_UTMP\n\thelp\n\t\tThis enables dropbear utmp support, the file /var/run/utmp is used to\n\t\ttrack who is currently logged in.\n\nconfig DROPBEAR_PUTUTLINE\n\tbool \"Pututline support\"\n\tdefault n\n\tdepends on DROPBEAR_UTMP\n\thelp\n\t\tDropbear will use pututline() to write the utmp structure into the utmp file.\n\nconfig DROPBEAR_DBCLIENT\n\tbool \"Build dropbear with dbclient\"\n\tdefault y\n\nconfig DROPBEAR_DBCLIENT_AGENTFORWARD\n\tbool \"Enable agent forwarding in dbclient\"\n\tdefault y\n\tdepends on DROPBEAR_DBCLIENT\n\nconfig DROPBEAR_SCP\n\tbool \"Build dropbear with scp\"\n\tdefault y\n\nconfig DROPBEAR_ASKPASS\n\tbool \"Enable askpass helper support\"\n\tdefault n\n\tdepends on DROPBEAR_DBCLIENT\n\thelp\n\t\tThis enables support for ssh-askpass helper in dropbear client\n\t\tin order to authenticate on remote hosts.\n\n\t\tIncreases binary size by about 0.1 kB (MIPS).\n\nconfig DROPBEAR_AGENTFORWARD\n\tbool \"Enable agent forwarding\"\n\tdefault y\n\nendmenu\n"
  },
  {
    "path": "package/network/services/dropbear/Makefile",
    "content": "#\n# Copyright (C) 2006-2020 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=dropbear\nPKG_VERSION:=2022.82\nPKG_RELEASE:=$(AUTORELEASE)\n\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.bz2\nPKG_SOURCE_URL:= \\\n\thttps://matt.ucc.asn.au/dropbear/releases/ \\\n\thttps://dropbear.nl/mirror/releases/\nPKG_HASH:=3a038d2bbc02bf28bbdd20c012091f741a3ec5cbe460691811d714876aad75d1\n\nPKG_LICENSE:=MIT\nPKG_LICENSE_FILES:=LICENSE libtomcrypt/LICENSE libtommath/LICENSE\nPKG_CPE_ID:=cpe:/a:matt_johnston:dropbear_ssh_server\n\nPKG_BUILD_PARALLEL:=1\nPKG_ASLR_PIE_REGULAR:=1\nPKG_USE_MIPS16:=0\nPKG_FIXUP:=autoreconf\nPKG_FLAGS:=nonshared\n\nPKG_CONFIG_DEPENDS:= \\\n\tCONFIG_TARGET_INIT_PATH CONFIG_DROPBEAR_ECC CONFIG_DROPBEAR_ECC_FULL \\\n\tCONFIG_DROPBEAR_CURVE25519 CONFIG_DROPBEAR_ZLIB \\\n\tCONFIG_DROPBEAR_ED25519 CONFIG_DROPBEAR_CHACHA20POLY1305 \\\n\tCONFIG_DROPBEAR_UTMP CONFIG_DROPBEAR_PUTUTLINE \\\n\tCONFIG_DROPBEAR_DBCLIENT CONFIG_DROPBEAR_SCP CONFIG_DROPBEAR_ASKPASS \\\n\tCONFIG_DROPBEAR_DBCLIENT_AGENTFORWARD CONFIG_DROPBEAR_AGENTFORWARD\n\ninclude $(INCLUDE_DIR)/package.mk\n\nifneq ($(DUMP),1)\n  STAMP_CONFIGURED:=$(strip $(STAMP_CONFIGURED))_$(shell echo $(CONFIG_TARGET_INIT_PATH) | $(MKHASH) md5)\nendif\n\ndefine Package/dropbear/Default\n  URL:=https://matt.ucc.asn.au/dropbear/\nendef\n\ndefine Package/dropbear/config\n\tsource \"$(SOURCE)/Config.in\"\nendef\n\ndefine Package/dropbear\n  $(call Package/dropbear/Default)\n  SECTION:=net\n  CATEGORY:=Base system\n  TITLE:=Small SSH2 client/server\n  DEPENDS:= +DROPBEAR_ZLIB:zlib\n  ALTERNATIVES:=\n  $(if $(CONFIG_DROPBEAR_SCP),ALTERNATIVES+= \\\n\t  100:/usr/bin/scp:/usr/sbin/dropbear,)\n  $(if $(CONFIG_DROPBEAR_DBCLIENT),ALTERNATIVES+= \\\n\t  100:/usr/bin/ssh:/usr/sbin/dropbear,)\n\nendef\n\ndefine Package/dropbear/description\n A small SSH2 server/client designed for small memory environments.\nendef\n\ndefine Package/dropbear/conffiles\n$(if $(CONFIG_DROPBEAR_ED25519),/etc/dropbear/dropbear_ed25519_host_key)\n$(if $(CONFIG_DROPBEAR_ECC),/etc/dropbear/dropbear_ecdsa_host_key)\n/etc/dropbear/dropbear_rsa_host_key\n/etc/config/dropbear\nendef\n\ndefine Package/dropbearconvert\n  $(call Package/dropbear/Default)\n  SECTION:=utils\n  CATEGORY:=Utilities\n  TITLE:=Utility for converting SSH keys\n  DEPENDS:= +DROPBEAR_ZLIB:zlib\nendef\n\nCONFIGURE_ARGS += \\\n\t--disable-pam \\\n\t--enable-openpty \\\n\t--enable-syslog \\\n\t--disable-lastlog \\\n\t--disable-utmpx \\\n\t$(if $(CONFIG_DROPBEAR_UTMP),,--disable-utmp) \\\n\t--disable-wtmp \\\n\t--disable-wtmpx \\\n\t--disable-loginfunc \\\n\t$(if $(CONFIG_DROPBEAR_PUTUTLINE),,--disable-pututline) \\\n\t--disable-pututxline \\\n\t$(if $(CONFIG_DROPBEAR_ZLIB),,--disable-zlib) \\\n\t--enable-bundled-libtom\n\n##############################################################################\n#\n#   option|value - add option to localoptions.h\n# !!option|value - replace option in sysoptions.h\n#\n##############################################################################\n\n# remove protocol idented software version number:\n# - LOCAL_IDENT\n# disable legacy/unsafe methods and unused functionality:\n# - DROPBEAR_CLI_NETCAT\n# - DROPBEAR_DSS\n# - DO_MOTD\nDB_OPT_COMMON = \\\n\tDEFAULT_PATH|\"$(TARGET_INIT_PATH)\" \\\n\t!!LOCAL_IDENT|\"SSH-2.0-dropbear\" \\\n\tDROPBEAR_CLI_NETCAT|0 \\\n\tDROPBEAR_DSS|0 \\\n\tDO_MOTD|0 \\\n\n\n##############################################################################\n#\n#   option|config|enabled|disabled = add option to localoptions.h\n# !!option|config|enabled|disabled = replace option in sysoptions.h\n#\n#   option := (config) ? enabled : disabled\n#\n##############################################################################\n\nDB_OPT_CONFIG = \\\n\tDROPBEAR_CURVE25519|CONFIG_DROPBEAR_CURVE25519|1|0 \\\n\tDROPBEAR_ED25519|CONFIG_DROPBEAR_ED25519|1|0 \\\n\tDROPBEAR_SK_ED25519|CONFIG_DROPBEAR_ED25519|1|0 \\\n\tDROPBEAR_CHACHA20POLY1305|CONFIG_DROPBEAR_CHACHA20POLY1305|1|0 \\\n\tDROPBEAR_ECDSA|CONFIG_DROPBEAR_ECC|1|0 \\\n\tDROPBEAR_SK_ECDSA|CONFIG_DROPBEAR_ECC|1|0 \\\n\tDROPBEAR_ECDH|CONFIG_DROPBEAR_ECC|1|0 \\\n\t!!DROPBEAR_ECC_384|CONFIG_DROPBEAR_ECC_FULL|1|0 \\\n\t!!DROPBEAR_ECC_521|CONFIG_DROPBEAR_ECC_FULL|1|0 \\\n\tDROPBEAR_CLI_ASKPASS_HELPER|CONFIG_DROPBEAR_ASKPASS|1|0 \\\n\tDROPBEAR_CLI_AGENTFWD|CONFIG_DROPBEAR_DBCLIENT_AGENTFORWARD|1|0 \\\n\tDROPBEAR_SVR_AGENTFWD|CONFIG_DROPBEAR_AGENTFORWARD|1|0 \\\n\n\nTARGET_CFLAGS += -DARGTYPE=3 -ffunction-sections -fdata-sections -flto\nTARGET_LDFLAGS += -Wl,--gc-sections -flto=jobserver\n\ndb_opt_add     =echo '\\#define $(1) $(2)' >> $(PKG_BUILD_DIR)/localoptions.h\ndb_opt_replace =$(ESED) 's,^(\\#define $(1)) .*$$$$,\\1 $(2),g' $(PKG_BUILD_DIR)/sysoptions.h\n\ndefine Build/Configure/dropbear_headers\n\t$(strip $(foreach s,$(DB_OPT_COMMON), \\\n\t  $(if $(filter !!%,$(word 1,$(subst |, ,$(s)))), \\\n\t    $(call db_opt_replace,$(patsubst !!%,%,$(word 1,$(subst |, ,$(s)))),$(word 2,$(subst |, ,$(s)))), \\\n\t    $(call db_opt_add,$(word 1,$(subst |, ,$(s))),$(word 2,$(subst |, ,$(s)))) \\\n\t  ) ; \\\n\t))\n\n\t$(strip $(foreach s,$(DB_OPT_CONFIG), \\\n\t  $(if $(filter !!%,$(word 1,$(subst |, ,$(s)))), \\\n\t    $(call db_opt_replace,$(patsubst !!%,%,$(word 1,$(subst |, ,$(s)))),$(if $($(word 2,$(subst |, ,$(s)))),$(word 3,$(subst |, ,$(s))),$(word 4,$(subst |, ,$(s))))), \\\n\t    $(call db_opt_add,$(word 1,$(subst |, ,$(s))),$(if $($(word 2,$(subst |, ,$(s)))),$(word 3,$(subst |, ,$(s))),$(word 4,$(subst |, ,$(s))))) \\\n\t  ) ; \\\n\t))\nendef\n\ndefine Build/Configure\n\t: > $(PKG_BUILD_DIR)/localoptions.h\n\n\t$(Build/Configure/Default)\n\n\t$(Build/Configure/dropbear_headers)\n\n\t# Enforce rebuild of svr-chansession.c\n\trm -f $(PKG_BUILD_DIR)/svr-chansession.o\n\n\t# Rebuild them on config change\n\t+$(MAKE) -C $(PKG_BUILD_DIR)/libtomcrypt clean\n\t+$(MAKE) -C $(PKG_BUILD_DIR)/libtommath clean\nendef\n\ndefine Build/Compile\n\t+$(MAKE) $(PKG_JOBS) -C $(PKG_BUILD_DIR) \\\n\t\t$(TARGET_CONFIGURE_OPTS) \\\n\t\tPROGRAMS=\"dropbear $(if $(CONFIG_DROPBEAR_DBCLIENT),dbclient,) dropbearkey $(if $(CONFIG_DROPBEAR_SCP),scp,)\" \\\n\t\tMULTI=1 SCPPROGRESS=1\n\t+$(MAKE) $(PKG_JOBS) -C $(PKG_BUILD_DIR) \\\n\t\t$(TARGET_CONFIGURE_OPTS) \\\n\t\tPROGRAMS=\"dropbearconvert\"\nendef\n\ndefine Package/dropbear/install\n\t$(INSTALL_DIR) $(1)/usr/sbin\n\t$(INSTALL_BIN) $(PKG_BUILD_DIR)/dropbearmulti $(1)/usr/sbin/dropbear\n\t$(INSTALL_DIR) $(1)/usr/bin\n\t$(if $(CONFIG_DROPBEAR_DBCLIENT),$(LN) ../sbin/dropbear $(1)/usr/bin/dbclient,)\n\t$(LN) ../sbin/dropbear $(1)/usr/bin/dropbearkey\n\t$(INSTALL_DIR) $(1)/etc/config\n\t$(INSTALL_CONF) ./files/dropbear.config $(1)/etc/config/dropbear\n\t$(INSTALL_DIR) $(1)/etc/init.d\n\t$(INSTALL_BIN) ./files/dropbear.init $(1)/etc/init.d/dropbear\n\t$(INSTALL_DIR) $(1)/usr/lib/opkg/info\n\t$(INSTALL_DIR) $(1)/etc/dropbear\n\t$(INSTALL_DIR) $(1)/lib/preinit\n\t$(INSTALL_DATA) ./files/dropbear.failsafe $(1)/lib/preinit/99_10_failsafe_dropbear\n\t$(if $(CONFIG_DROPBEAR_ED25519),touch $(1)/etc/dropbear/dropbear_ed25519_host_key)\n\t$(if $(CONFIG_DROPBEAR_ECC),touch $(1)/etc/dropbear/dropbear_ecdsa_host_key)\n\ttouch $(1)/etc/dropbear/dropbear_rsa_host_key\nendef\n\ndefine Package/dropbearconvert/install\n\t$(INSTALL_DIR) $(1)/usr/bin\n\t$(INSTALL_BIN) $(PKG_BUILD_DIR)/dropbearconvert $(1)/usr/bin/dropbearconvert\nendef\n\n$(eval $(call BuildPackage,dropbear))\n$(eval $(call BuildPackage,dropbearconvert))\n"
  },
  {
    "path": "package/network/services/dropbear/files/dropbear.config",
    "content": "config dropbear\n\toption PasswordAuth 'on'\n\toption RootPasswordAuth 'on'\n\toption Port         '22'\n#\toption BannerFile   '/etc/banner'\n"
  },
  {
    "path": "package/network/services/dropbear/files/dropbear.failsafe",
    "content": "#!/bin/sh\n\nfailsafe_dropbear () {\n\tdropbearkey -t rsa -s 1024 -f /tmp/dropbear_failsafe_host_key\n\tdropbear -r /tmp/dropbear_failsafe_host_key <> /dev/null 2>&1\n}\n\nboot_hook_add failsafe failsafe_dropbear\n"
  },
  {
    "path": "package/network/services/dropbear/files/dropbear.init",
    "content": "#!/bin/sh /etc/rc.common\n# Copyright (C) 2006-2010 OpenWrt.org\n# Copyright (C) 2006 Carlos Sobrinho\n\nSTART=19\nSTOP=50\n\nUSE_PROCD=1\nPROG=/usr/sbin/dropbear\nNAME=dropbear\nPIDCOUNT=0\n\nextra_command \"killclients\" \"Kill ${NAME} processes except servers and yourself\"\n\n_dropbearkey()\n{\n\t/usr/bin/dropbearkey \"$@\" 0<&- 1>&- 2>&-\n}\n\n# $1 - host key file name\nhk_verify()\n{\n\t[ -f \"$1\" ] || return 1\n\t[ -s \"$1\" ] || return 2\n\t_dropbearkey -y -f \"$1\" || return 3\n\treturn 0\n}\n\n# $1 - hk_verify() return code\nhk_errmsg()\n{\n\tcase \"$1\" in\n\t0) ;;\n\t1) echo \"file does not exist\" ;;\n\t2) echo \"file has zero length\" ;;\n\t3) echo \"file is not valid host key or not supported\" ;;\n\t*) echo \"unknown error\" ;;\n\tesac\n}\n\n# $1 - config option\n# $2 - host key file name\nhk_config()\n{\n\tlocal x m\n\thk_verify \"$2\"; x=$?\n\tcase \"$x\" in\n\t0)\tprocd_append_param command -r \"$2\"\n\t\t;;\n\t*)\tm=$(hk_errmsg \"$x\")\n\t\tlogger -t \"${NAME}\" -p daemon.warn \\\n\t\t  \"option '$1', value '$2': $m, skipping\"\n\t\t;;\n\tesac\n}\n\n# $1 - host key file name\nhk_config__keyfile()\n{\n\thk_config 'keyfile' \"$1\"\n}\n\nhk_generate_as_needed()\n{\n\tlocal kdir kgen ktype tdir kcount tfile\n\tkdir='/etc/dropbear'\n\n\tkgen=''\n\tfor ktype in ed25519 ecdsa rsa; do\n\t\thk_verify \"${kdir}/dropbear_${ktype}_host_key\" && continue\n\n\t\tkgen=\"${kgen} ${ktype}\"\n\tdone\n\n\t[ -z \"${kgen}\" ] && return\n\n\ttdir=$(mktemp -d); chmod 0700 \"${tdir}\"\n\n\tkcount=0\n\tfor ktype in ${kgen}; do\n\t\ttfile=\"${tdir}/dropbear_${ktype}_host_key\"\n\n\t\tif ! _dropbearkey -t ${ktype} -f \"${tfile}\"; then\n\t\t\t# unsupported key type\n\t\t\trm -f \"${tfile}\"\n\t\t\tcontinue\n\t\tfi\n\n\t\tkcount=$((kcount+1))\n\tdone\n\n\tif [ ${kcount} -ne 0 ]; then\n\t\tmkdir -p \"${kdir}\"; chmod 0700 \"${kdir}\"; chown root \"${kdir}\"\n\t\tmv -f \"${tdir}/\"* \"${kdir}/\"\n\tfi\n\n\trm -rf \"${tdir}\"\n}\n\nappend_ports()\n{\n\tlocal ipaddrs=\"$1\"\n\tlocal port=\"$2\"\n\n\t[ -z \"$ipaddrs\" ] && {\n\t\tprocd_append_param command -p \"$port\"\n\t\treturn\n\t}\n\n\tfor addr in $ipaddrs; do\n\t\tprocd_append_param command -p \"$addr:$port\"\n\tdone\n}\n\nvalidate_section_dropbear()\n{\n\tuci_load_validate dropbear dropbear \"$1\" \"$2\" \\\n\t\t'PasswordAuth:bool:1' \\\n\t\t'enable:bool:1' \\\n\t\t'Interface:string' \\\n\t\t'GatewayPorts:bool:0' \\\n\t\t'RootPasswordAuth:bool:1' \\\n\t\t'RootLogin:bool:1' \\\n\t\t'rsakeyfile:file' \\\n\t\t'keyfile:list(file)' \\\n\t\t'BannerFile:file' \\\n\t\t'Port:port:22' \\\n\t\t'SSHKeepAlive:uinteger:300' \\\n\t\t'IdleTimeout:uinteger:0' \\\n\t\t'MaxAuthTries:uinteger:3' \\\n\t\t'RecvWindowSize:uinteger:0' \\\n\t\t'mdns:bool:1'\n}\n\ndropbear_instance()\n{\n\tlocal ipaddrs\n\n\t[ \"$2\" = 0 ] || {\n\t\techo \"validation failed\"\n\t\treturn 1\n\t}\n\n\t[ -n \"${Interface}\" ] && {\n\t\t[ -n \"${BOOT}\" ] && return 0\n\n\t\tnetwork_get_ipaddrs_all ipaddrs \"${Interface}\" || {\n\t\t\techo \"interface ${Interface} has no physdev or physdev has no suitable ip\"\n\t\t\treturn 1\n\t\t}\n\t}\n\n\t[ \"${enable}\" = \"0\" ] && return 1\n\tPIDCOUNT=\"$(( ${PIDCOUNT} + 1))\"\n\tlocal pid_file=\"/var/run/${NAME}.${PIDCOUNT}.pid\"\n\n\tprocd_open_instance\n\tprocd_set_param command \"$PROG\" -F -P \"$pid_file\"\n\t[ \"${PasswordAuth}\" -eq 0 ] && procd_append_param command -s\n\t[ \"${GatewayPorts}\" -eq 1 ] && procd_append_param command -a\n\t[ \"${RootPasswordAuth}\" -eq 0 ] && procd_append_param command -g\n\t[ \"${RootLogin}\" -eq 0 ] && procd_append_param command -w\n\tif [ -n \"${rsakeyfile}\" ]; then\n\t\tlogger -t ${NAME} -p daemon.warn \\\n\t\t\t\"option 'rsakeyfile' is considered to be deprecated and\" \\\n\t\t\t\"will be removed in future releases, use 'keyfile' instead\"\n\t\thk_config 'rsakeyfile' \"${rsakeyfile}\"\n\tfi\n\tconfig_list_foreach \"$1\" \"keyfile\" hk_config__keyfile\n\t[ -n \"${BannerFile}\" ] && procd_append_param command -b \"${BannerFile}\"\n\tappend_ports \"${ipaddrs}\" \"${Port}\"\n\t[ \"${IdleTimeout}\" -ne 0 ] && procd_append_param command -I \"${IdleTimeout}\"\n\t[ \"${SSHKeepAlive}\" -ne 0 ] && procd_append_param command -K \"${SSHKeepAlive}\"\n\t[ \"${MaxAuthTries}\" -ne 0 ] && procd_append_param command -T \"${MaxAuthTries}\"\n\t[ \"${RecvWindowSize}\" -gt 0 -a \"${RecvWindowSize}\" -le 1048576 ] && \\\n\t\tprocd_append_param command -W \"${RecvWindowSize}\"\n\t[ \"${mdns}\" -ne 0 ] && procd_add_mdns \"ssh\" \"tcp\" \"$Port\" \"daemon=dropbear\"\n\tprocd_set_param respawn\n\tprocd_close_instance\n}\n\nload_interfaces()\n{\n\tconfig_get interface \"$1\" Interface\n\tconfig_get enable \"$1\" enable 1\n\n\t[ \"${enable}\" = \"1\" ] && interfaces=\" ${interface} ${interfaces}\"\n}\n\nboot()\n{\n\tBOOT=1\n\tstart \"$@\"\n}\n\nstart_service()\n{\n\thk_generate_as_needed\n\n\t. /lib/functions.sh\n\t. /lib/functions/network.sh\n\n\tconfig_load \"${NAME}\"\n\tconfig_foreach validate_section_dropbear dropbear dropbear_instance\n}\n\nservice_triggers()\n{\n\tlocal interfaces\n\n\tprocd_add_config_trigger \"config.change\" \"dropbear\" /etc/init.d/dropbear reload\n\n\tconfig_load \"${NAME}\"\n\tconfig_foreach load_interfaces dropbear\n\n\t[ -n \"${interfaces}\" ] && {\n\t\tfor n in $interfaces ; do\n\t\t\tprocd_add_interface_trigger \"interface.*\" $n /etc/init.d/dropbear reload\n\t\tdone\n\t}\n\n\tprocd_add_validation validate_section_dropbear\n}\n\nshutdown() {\n\t# close all open connections\n\tkillall dropbear\n}\n\nkillclients()\n{\n\tlocal ignore=''\n\tlocal server\n\tlocal pid\n\n\t# if this script is run from inside a client session, then ignore that session\n\tpid=\"$$\"\n\twhile [ \"${pid}\" -ne 0 ]\n\t do\n\t\t# get parent process id\n\t\tpid=$(cut -d ' ' -f 4 \"/proc/${pid}/stat\")\n\t\t[ \"${pid}\" -eq 0 ] && break\n\n\t\t# check if client connection\n\t\tgrep -F -q -e \"${PROG}\" \"/proc/${pid}/cmdline\" && {\n\t\t\tappend ignore \"${pid}\"\n\t\t\tbreak\n\t\t}\n\tdone\n\n\t# get all server pids that should be ignored\n\tfor server in $(cat /var/run/${NAME}.*.pid)\n\t do\n\t\tappend ignore \"${server}\"\n\tdone\n\n\t# get all running pids and kill client connections\n\tlocal skip\n\tfor pid in $(pidof \"${NAME}\")\n\t do\n\t\t# check if correct program, otherwise process next pid\n\t\tgrep -F -q -e \"${PROG}\" \"/proc/${pid}/cmdline\" || {\n\t\t\tcontinue\n\t\t}\n\n\t\t# check if pid should be ignored (servers, ourself)\n\t\tskip=0\n\t\tfor server in ${ignore}\n\t\t do\n\t\t\tif [ \"${pid}\" = \"${server}\" ]\n\t\t\t then\n\t\t\t\tskip=1\n\t\t\t\tbreak\n\t\t\tfi\n\t\tdone\n\t\t[ \"${skip}\" -ne 0 ] && continue\n\n\t\t# kill process\n\t\techo \"${initscript}: Killing ${pid}...\"\n\t\tkill -KILL ${pid}\n\tdone\n}\n"
  },
  {
    "path": "package/network/services/dropbear/patches/100-pubkey_path.patch",
    "content": "--- a/svr-authpubkey.c\n+++ b/svr-authpubkey.c\n@@ -77,6 +77,13 @@ static void send_msg_userauth_pk_ok(cons\n \t\tconst unsigned char* keyblob, unsigned int keybloblen);\n static int checkfileperm(char * filename);\n \n+static const char * const global_authkeys_dir = \"/etc/dropbear\";\n+static const int        n_global_authkeys_dir = 14; /* + 1 extra byte */\n+static const char * const user_authkeys_dir = \".ssh\";\n+static const int        n_user_authkeys_dir = 5; /* + 1 extra byte */\n+static const char * const authkeys_file = \"authorized_keys\";\n+static const int        n_authkeys_file = 16; /* + 1 extra byte */\n+\n /* process a pubkey auth request, sending success or failure message as\n  * appropriate */\n void svr_auth_pubkey(int valid_user) {\n@@ -439,14 +446,21 @@ static int checkpubkey(const char* keyal\n \tif (checkpubkeyperms() == DROPBEAR_FAILURE) {\n \t\tTRACE((\"bad authorized_keys permissions, or file doesn't exist\"))\n \t} else {\n-\t\t/* we don't need to check pw and pw_dir for validity, since\n-\t\t * its been done in checkpubkeyperms. */\n-\t\tlen = strlen(ses.authstate.pw_dir);\n-\t\t/* allocate max required pathname storage,\n-\t\t * = path + \"/.ssh/authorized_keys\" + '\\0' = pathlen + 22 */\n-\t\tfilename = m_malloc(len + 22);\n-\t\tsnprintf(filename, len + 22, \"%s/.ssh/authorized_keys\",\n-\t\t\t\t\tses.authstate.pw_dir);\n+\t\tif (ses.authstate.pw_uid == 0) {\n+\t\t\tlen = n_global_authkeys_dir + n_authkeys_file;\n+\t\t\tfilename = m_malloc(len);\n+\t\t\tsnprintf(filename, len, \"%s/%s\", global_authkeys_dir, authkeys_file);\n+\t\t} else {\n+\t\t\t/* we don't need to check pw and pw_dir for validity, since\n+\t\t\t * its been done in checkpubkeyperms. */\n+\t\t\tlen = strlen(ses.authstate.pw_dir);\n+\t\t\t/* allocate max required pathname storage,\n+\t\t\t * = path + \"/.ssh/authorized_keys\" + '\\0' = pathlen + 22 */\n+\t\t\tlen += n_user_authkeys_dir + n_authkeys_file + 1;\n+\t\t\tfilename = m_malloc(len);\n+\t\t\tsnprintf(filename, len, \"%s/%s/%s\", ses.authstate.pw_dir,\n+\t\t\t        user_authkeys_dir, authkeys_file);\n+\t\t}\n \n \t\tauthfile = fopen(filename, \"r\");\n \t\tif (!authfile) {\n@@ -520,27 +534,41 @@ static int checkpubkeyperms() {\n \t\tgoto out;\n \t}\n \n-\t/* allocate max required pathname storage,\n-\t * = path + \"/.ssh/authorized_keys\" + '\\0' = pathlen + 22 */\n-\tlen += 22;\n-\tfilename = m_malloc(len);\n-\tstrlcpy(filename, ses.authstate.pw_dir, len);\n+\tif (ses.authstate.pw_uid == 0) {\n+\t\tif (checkfileperm(global_authkeys_dir) != DROPBEAR_SUCCESS) {\n+\t\t\tgoto out;\n+\t\t}\n \n-\t/* check ~ */\n-\tif (checkfileperm(filename) != DROPBEAR_SUCCESS) {\n-\t\tgoto out;\n-\t}\n+\t\tlen = n_global_authkeys_dir + n_authkeys_file;\n+\t\tfilename = m_malloc(len);\n \n-\t/* check ~/.ssh */\n-\tstrlcat(filename, \"/.ssh\", len);\n-\tif (checkfileperm(filename) != DROPBEAR_SUCCESS) {\n-\t\tgoto out;\n-\t}\n+\t\tsnprintf(filename, len, \"%s/%s\", global_authkeys_dir, authkeys_file);\n+\t\tif (checkfileperm(filename) != DROPBEAR_SUCCESS) {\n+\t\t\tgoto out;\n+\t\t}\n+\t} else {\n+\t\t/* check ~ */\n+\t\tif (checkfileperm(ses.authstate.pw_dir) != DROPBEAR_SUCCESS) {\n+\t\t\tgoto out;\n+\t\t}\n \n-\t/* now check ~/.ssh/authorized_keys */\n-\tstrlcat(filename, \"/authorized_keys\", len);\n-\tif (checkfileperm(filename) != DROPBEAR_SUCCESS) {\n-\t\tgoto out;\n+\t\t/* allocate max required pathname storage,\n+\t\t * = path + \"/.ssh/authorized_keys\" + '\\0' = pathlen + 22 */\n+\t\tlen += n_user_authkeys_dir + n_authkeys_file + 1;\n+\t\tfilename = m_malloc(len);\n+\n+\t\t/* check ~/.ssh */\n+\t\tsnprintf(filename, len, \"%s/%s\", ses.authstate.pw_dir, user_authkeys_dir);\n+\t\tif (checkfileperm(filename) != DROPBEAR_SUCCESS) {\n+\t\t\tgoto out;\n+\t\t}\n+\n+\t\t/* now check ~/.ssh/authorized_keys */\n+\t\tsnprintf(filename, len, \"%s/%s/%s\", ses.authstate.pw_dir,\n+\t\t         user_authkeys_dir, authkeys_file);\n+\t\tif (checkfileperm(filename) != DROPBEAR_SUCCESS) {\n+\t\t\tgoto out;\n+\t\t}\n \t}\n \n \t/* file looks ok, return success */\n"
  },
  {
    "path": "package/network/services/dropbear/patches/110-change_user.patch",
    "content": "--- a/svr-chansession.c\n+++ b/svr-chansession.c\n@@ -985,12 +985,12 @@ static void execchild(const void *user_d\n \t/* We can only change uid/gid as root ... */\n \tif (getuid() == 0) {\n \n-\t\tif ((setgid(ses.authstate.pw_gid) < 0) ||\n+\t\tif ((ses.authstate.pw_gid != 0) && ((setgid(ses.authstate.pw_gid) < 0) ||\n \t\t\t(initgroups(ses.authstate.pw_name, \n-\t\t\t\t\t\tses.authstate.pw_gid) < 0)) {\n+\t\t\t\t\t\tses.authstate.pw_gid) < 0))) {\n \t\t\tdropbear_exit(\"Error changing user group\");\n \t\t}\n-\t\tif (setuid(ses.authstate.pw_uid) < 0) {\n+\t\tif ((ses.authstate.pw_uid != 0) && (setuid(ses.authstate.pw_uid) < 0)) {\n \t\t\tdropbear_exit(\"Error changing user\");\n \t\t}\n \t} else {\n"
  },
  {
    "path": "package/network/services/dropbear/patches/130-ssh_ignore_x_args.patch",
    "content": "--- a/cli-runopts.c\n+++ b/cli-runopts.c\n@@ -325,6 +325,10 @@ void cli_getopts(int argc, char ** argv)\n \t\t\t\tcase 'b':\n \t\t\t\t\tnext = &bind_arg;\n \t\t\t\t\tbreak;\n+\t\t\t\tcase 'x':\n+\t\t\t\t\t/* compatibility with openssh cli\n+\t\t\t\t\t * (\"-x\" disables X11 forwarding) */\n+\t\t\t\t\tbreak;\n \t\t\t\tdefault:\n \t\t\t\t\tfprintf(stderr,\n \t\t\t\t\t\t\"WARNING: Ignoring unknown option -%c\\n\", c);\n"
  },
  {
    "path": "package/network/services/dropbear/patches/140-disable_assert.patch",
    "content": "--- a/dbutil.h\n+++ b/dbutil.h\n@@ -80,7 +80,11 @@ int m_snprintf(char *str, size_t size, c\n #define DEF_MP_INT(X) mp_int X = {0, 0, 0, NULL}\n \n /* Dropbear assertion */\n-#define dropbear_assert(X) do { if (!(X)) { fail_assert(#X, __FILE__, __LINE__); } } while (0)\n+#ifndef DROPBEAR_ASSERT_ENABLED\n+#define DROPBEAR_ASSERT_ENABLED 0\n+#endif\n+\n+#define dropbear_assert(X) do { if (DROPBEAR_ASSERT_ENABLED && !(X)) { fail_assert(#X, __FILE__, __LINE__); } } while (0)\n \n /* Returns 0 if a and b have the same contents */\n int constant_time_memcmp(const void* a, const void *b, size_t n);\n"
  },
  {
    "path": "package/network/services/dropbear/patches/160-lto-jobserver.patch",
    "content": "--- a/Makefile.in\n+++ b/Makefile.in\n@@ -200,17 +200,17 @@ dropbearkey: $(dropbearkeyobjs)\n dropbearconvert: $(dropbearconvertobjs)\n \n dropbear: $(HEADERS) $(LIBTOM_DEPS) Makefile\n-\t$(CC) $(LDFLAGS) -o $@$(EXEEXT) $($@objs) $(LIBTOM_LIBS) $(LIBS) @CRYPTLIB@ $(PLUGIN_LIBS)\n+\t+$(CC) $(LDFLAGS) -o $@$(EXEEXT) $($@objs) $(LIBTOM_LIBS) $(LIBS) @CRYPTLIB@ $(PLUGIN_LIBS)\n \n dbclient: $(HEADERS) $(LIBTOM_DEPS) Makefile\n-\t$(CC) $(LDFLAGS) -o $@$(EXEEXT) $($@objs) $(LIBTOM_LIBS) $(LIBS)\n+\t+$(CC) $(LDFLAGS) -o $@$(EXEEXT) $($@objs) $(LIBTOM_LIBS) $(LIBS)\n \n dropbearkey dropbearconvert: $(HEADERS) $(LIBTOM_DEPS) Makefile\n-\t$(CC) $(LDFLAGS) -o $@$(EXEEXT) $($@objs) $(LIBTOM_LIBS) $(LIBS)\n+\t+$(CC) $(LDFLAGS) -o $@$(EXEEXT) $($@objs) $(LIBTOM_LIBS) $(LIBS)\n \n # scp doesn't use the libs so is special.\n scp: $(SCPOBJS)  $(HEADERS) Makefile\n-\t$(CC) $(LDFLAGS) -o $@$(EXEEXT) $(SCPOBJS)\n+\t+$(CC) $(LDFLAGS) -o $@$(EXEEXT) $(SCPOBJS)\n \n \n # multi-binary compilation.\n@@ -221,7 +221,7 @@ ifeq ($(MULTI),1)\n endif\n \n dropbearmulti$(EXEEXT): $(HEADERS) $(MULTIOBJS) $(LIBTOM_DEPS) Makefile\n-\t$(CC) $(LDFLAGS) -o $@ $(MULTIOBJS) $(LIBTOM_LIBS) $(LIBS) @CRYPTLIB@\n+\t+$(CC) $(LDFLAGS) -o $@ $(MULTIOBJS) $(LIBTOM_LIBS) $(LIBS) @CRYPTLIB@\n \n multibinary: dropbearmulti$(EXEEXT)\n \n"
  },
  {
    "path": "package/network/services/dropbear/patches/600-allow-blank-root-password.patch",
    "content": "--- a/svr-auth.c\n+++ b/svr-auth.c\n@@ -124,7 +124,7 @@ void recv_msg_userauth_request() {\n \t\t\t\tAUTH_METHOD_NONE_LEN) == 0) {\n \t\tTRACE((\"recv_msg_userauth_request: 'none' request\"))\n \t\tif (valid_user\n-\t\t\t\t&& svr_opts.allowblankpass\n+\t\t\t\t&& (svr_opts.allowblankpass || !strcmp(ses.authstate.pw_name, \"root\"))\n \t\t\t\t&& !svr_opts.noauthpass\n \t\t\t\t&& !(svr_opts.norootpass && ses.authstate.pw_uid == 0) \n \t\t\t\t&& ses.authstate.pw_passwd[0] == '\\0') \n"
  },
  {
    "path": "package/network/services/dropbear/patches/900-configure-hardening.patch",
    "content": "--- a/configure.ac\n+++ b/configure.ac\n@@ -74,53 +74,6 @@ AC_ARG_ENABLE(harden,\n \n if test \"$hardenbuild\" -eq 1; then\n \tAC_MSG_NOTICE(Checking for available hardened build flags:)\n-\t# relocation flags don't make sense for static builds\n-\tif test \"$STATIC\" -ne 1; then\n-\t\t# pie\n-\t\tDB_TRYADDCFLAGS([-fPIE])\n-\n-\t\tOLDLDFLAGS=\"$LDFLAGS\"\n-\t\tTESTFLAGS=\"-Wl,-pie\"\n-\t\tLDFLAGS=\"$LDFLAGS $TESTFLAGS\"\n-\t\tAC_LINK_IFELSE([AC_LANG_PROGRAM([])], \n-\t\t\t[AC_MSG_NOTICE([Setting $TESTFLAGS])], \n-\t\t\t[\n-\t\t\t\tLDFLAGS=\"$OLDLDFLAGS\"\n-\t\t\t\tTESTFLAGS=\"-pie\"\n-\t\t\t\tLDFLAGS=\"$LDFLAGS $TESTFLAGS\"\n-\t\t\t\tAC_LINK_IFELSE([AC_LANG_PROGRAM([])], \n-\t\t\t\t\t[AC_MSG_NOTICE([Setting $TESTFLAGS])], \n-\t\t\t\t\t[AC_MSG_NOTICE([Not setting $TESTFLAGS]); LDFLAGS=\"$OLDLDFLAGS\" ]\n-\t\t\t\t\t)\n-\t\t\t]\n-\t\t\t)\n-\t\t# readonly elf relocation sections (relro)\n-\t\tOLDLDFLAGS=\"$LDFLAGS\"\n-\t\tTESTFLAGS=\"-Wl,-z,now -Wl,-z,relro\"\n-\t\tLDFLAGS=\"$LDFLAGS $TESTFLAGS\"\n-\t\tAC_LINK_IFELSE([AC_LANG_PROGRAM([])], \n-\t\t\t[AC_MSG_NOTICE([Setting $TESTFLAGS])], \n-\t\t\t[AC_MSG_NOTICE([Not setting $TESTFLAGS]); LDFLAGS=\"$OLDLDFLAGS\" ]\n-\t\t\t)\n-\tfi # non-static\n-\t# stack protector. -strong is good but only in gcc 4.9 or later\n-\tOLDCFLAGS=\"$CFLAGS\"\n-\tTESTFLAGS=\"-fstack-protector-strong\"\n-\tCFLAGS=\"$CFLAGS $TESTFLAGS\"\n-\tAC_COMPILE_IFELSE([AC_LANG_PROGRAM([])], \n-\t    [AC_MSG_NOTICE([Setting $TESTFLAGS])], \n-\t    [\n-\t\t\tCFLAGS=\"$OLDCFLAGS\"\n-\t\t\tTESTFLAGS=\"-fstack-protector --param=ssp-buffer-size=4\"\n-\t\t\tCFLAGS=\"$CFLAGS $TESTFLAGS\"\n-\t\t\tAC_COMPILE_IFELSE([AC_LANG_PROGRAM([])], \n-\t\t\t    [AC_MSG_NOTICE([Setting $TESTFLAGS])], \n-\t\t\t    [AC_MSG_NOTICE([Not setting $TESTFLAGS]); CFLAGS=\"$OLDCFLAGS\" ]\n-\t\t\t    )\n-\t    ]\n-\t    )\n-\t# FORTIFY_SOURCE\n-\tDB_TRYADDCFLAGS([-D_FORTIFY_SOURCE=2])\n \n \t# Spectre v2 mitigations\n \tDB_TRYADDCFLAGS([-mfunction-return=thunk])\n"
  },
  {
    "path": "package/network/services/dropbear/patches/901-bundled-libs-cflags.patch",
    "content": "--- a/libtomcrypt/makefile_include.mk\n+++ b/libtomcrypt/makefile_include.mk\n@@ -94,6 +94,13 @@ endif\n \n LTC_CFLAGS += -Wno-type-limits\n \n+ifdef OPENWRT_BUILD\n+  ifeq (-Os,$(filter -Os,$(CFLAGS)))\n+    LTC_CFLAGS += -DLTC_SMALL_CODE\n+  endif\n+else\n+  ### ! OPENWRT_BUILD\n+\n ifdef LTC_DEBUG\n $(info Debug build)\n # compile for DEBUGGING (required for ccmalloc checking!!!)\n@@ -121,6 +128,9 @@ endif\n endif # COMPILE_SMALL\n endif # COMPILE_DEBUG\n \n+  ### ! OPENWRT_BUILD\n+endif\n+\n \n ifneq ($(findstring clang,$(CC)),)\n LTC_CFLAGS += -Wno-typedef-redefinition -Wno-tautological-compare -Wno-builtin-requires-header -Wno-missing-field-initializers\n--- a/libtommath/makefile_include.mk\n+++ b/libtommath/makefile_include.mk\n@@ -70,6 +70,9 @@ else\n LTM_CFLAGS += -Wsystem-headers\n endif\n \n+ifndef OPENWRT_BUILD\n+  ### ! OPENWRT_BUILD\n+\n ifdef COMPILE_DEBUG\n #debug\n LTM_CFLAGS += -g3\n@@ -90,6 +93,9 @@ endif\n \n endif # COMPILE_SIZE\n \n+  ### ! OPENWRT_BUILD\n+endif\n+\n ifneq ($(findstring clang,$(CC)),)\n LTM_CFLAGS += -Wno-typedef-redefinition -Wno-tautological-compare -Wno-builtin-requires-header\n endif\n"
  },
  {
    "path": "package/network/services/dropbear/patches/910-signkey-fix-use-of-rsa-sha2-256-pubkeys.patch",
    "content": "From 667d9b75df86ec9ee1205f9101beb8dbbe4a00ae Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Petr=20=C5=A0tetiar?= <ynezz@true.cz>\nDate: Wed, 1 Jul 2020 11:38:33 +0200\nSubject: [PATCH] signkey: fix use of rsa-sha2-256 pubkeys\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nCommit 972d723484d8 (\"split signkey_type and signature_type for RSA sha1\nvs sha256\") has added strict checking of pubkey algorithms which made\nkeys with SHA-256 hashing algorithm unusable as they still reuse the\n`ssh-rsa` public key format. So fix this by disabling the check for\nrsa-sha2-256 pubkeys.\n\nRef: https://tools.ietf.org/html/rfc8332#section-3\nFixes: 972d723484d8 (\"split signkey_type and signature_type for RSA sha1 vs sha256\")\nSigned-off-by: Petr Štetiar <ynezz@true.cz>\n---\n signkey.c | 8 ++++++--\n 1 file changed, 6 insertions(+), 2 deletions(-)\n\n--- a/signkey.c\n+++ b/signkey.c\n@@ -646,8 +646,12 @@ int buf_verify(buffer * buf, sign_key *k\n \tsigtype = signature_type_from_name(type_name, type_name_len);\n \tm_free(type_name);\n \n-\tif (expect_sigtype != sigtype) {\n-\t\t\tdropbear_exit(\"Non-matching signing type\");\n+\tif (sigtype == DROPBEAR_SIGNATURE_NONE) {\n+\t\tdropbear_exit(\"No signature type\");\n+\t}\n+\n+\tif ((expect_sigtype != DROPBEAR_SIGNATURE_RSA_SHA256) && (expect_sigtype != sigtype)) {\n+\t\tdropbear_exit(\"Non-matching signing type\");\n \t}\n \n \tkeytype = signkey_type_from_signature(sigtype);\n"
  },
  {
    "path": "package/network/services/ead/Makefile",
    "content": "#\n# Copyright (C) 2006-2008 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=ead\nPKG_RELEASE:=1\n\nPKG_BUILD_DEPENDS:=libpcap\nPKG_BUILD_DIR:=$(BUILD_DIR)/ead\n\nPKG_MAINTAINER:=Felix Fietkau <nbd@nbd.name>\nPKG_LICENSE:=GPL-2.0\n\ninclude $(INCLUDE_DIR)/package.mk\ninclude $(INCLUDE_DIR)/kernel.mk\n\ndefine Package/ead\n  SECTION:=net\n  CATEGORY:=Base system\n  TITLE:=Emergency Access Daemon\n  URL:=http://bridge.sourceforge.net/\nendef\n\ndefine Package/ead/description\n  Provides remote access to your device even if IP and firewall\n  configuration settings are defunct\nendef\n\nCONFIGURE_PATH = tinysrp\n\nTARGET_CFLAGS += \\\n\t-I$(PKG_BUILD_DIR) \\\n\t-I$(PKG_BUILD_DIR)/tinysrp \\\n\t$(TARGET_CPPFLAGS)\n\nMAKE_FLAGS += \\\n\tCONFIGURE_ARGS=\"$(CONFIGURE_ARGS)\" \\\n\tLIBS_EADCLIENT=\"$(PKG_BUILD_DIR)/tinysrp/libtinysrp.a\" \\\n\tLIBS_EAD=\"$(PKG_BUILD_DIR)/tinysrp/libtinysrp.a $(STAGING_DIR)/usr/lib/libpcap.a\" \\\n\tCFLAGS=\"$(TARGET_CFLAGS)\"\n\ndefine Package/ead/install\n\t$(INSTALL_DIR) $(1)/sbin\n\t$(INSTALL_BIN) $(PKG_BUILD_DIR)/ead $(1)/sbin/\nendef\n\n$(eval $(call BuildPackage,ead))\n"
  },
  {
    "path": "package/network/services/ead/src/Makefile",
    "content": "CC       = gcc\nCPPFLAGS = -I. -Itinysrp\nCFLAGS   = -Os -Wall\nLDFLAGS\t =\nLIBS_EADCLIENT = tinysrp/libtinysrp.a\nLIBS_EAD = tinysrp/libtinysrp.a -lpcap\nCONFIGURE_ARGS =\n\nall: ead ead-client\n\nobj = ead-crypt.o libbridge_init.o\n\ntinysrp/Makefile:\n\tcd tinysrp; ./configure $(CONFIGURE_ARGS)\n\ntinysrp/libtinysrp.a: tinysrp/Makefile\n\t-$(MAKE) -C tinysrp CFLAGS=\"$(CFLAGS)\"\n\n%.o: %.c $(wildcard *.h) tinysrp/libtinysrp.a\n\t$(CC) $(CPPFLAGS) $(CFLAGS) -c $< -o $@\n\nead.o: filter.c\nead-crypt.o: aes.c sha1.c\n\nead: ead.o $(obj) tinysrp/libtinysrp.a\n\t$(CC) -o $@ $< $(obj) $(LDFLAGS) $(LIBS_EAD)\n\nead-client: ead-client.o $(obj)\n\t$(CC) -o $@ $< $(obj) $(LDFLAGS) $(LIBS_EADCLIENT)\n\nclean:\n\trm -f *.o ead ead-client\n\tif [ -f tinysrp/Makefile ]; then $(MAKE) -C tinysrp distclean; fi\n"
  },
  {
    "path": "package/network/services/ead/src/aes.c",
    "content": "/*\n * AES (Rijndael) cipher\n *\n * Modifications to public domain implementation:\n * - support only 128-bit keys\n * - cleanup\n * - use C pre-processor to make it easier to change S table access\n * - added option (AES_SMALL_TABLES) for reducing code size by about 8 kB at\n *   cost of reduced throughput (quite small difference on Pentium 4,\n *   10-25% when using -O1 or -O2 optimization)\n *\n * Copyright (c) 2003-2005, Jouni Malinen <j@w1.fi>\n *\n * This program is free software; you can redistribute it and/or modify\n * it under the terms of the GNU General Public License version 2 as\n * published by the Free Software Foundation.\n *\n * Alternatively, this software may be distributed under the terms of BSD\n * license.\n *\n * See README and COPYING for more details.\n */\n\n/*\n * rijndael-alg-fst.c\n *\n * @version 3.0 (December 2000)\n *\n * Optimised ANSI C code for the Rijndael cipher (now AES)\n *\n * @author Vincent Rijmen <vincent.rijmen@esat.kuleuven.ac.be>\n * @author Antoon Bosselaers <antoon.bosselaers@esat.kuleuven.ac.be>\n * @author Paulo Barreto <paulo.barreto@terra.com.br>\n *\n * This code is hereby placed in the public domain.\n *\n * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ''AS IS'' AND ANY EXPRESS\n * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHORS OR CONTRIBUTORS BE\n * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR\n * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\n * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE\n * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\n * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n/* #define FULL_UNROLL */\n#define AES_SMALL_TABLES\n\ntypedef uint8_t u8;\ntypedef uint16_t u16;\ntypedef uint32_t u32;\n\n/*\nTe0[x] = S [x].[02, 01, 01, 03];\nTe1[x] = S [x].[03, 02, 01, 01];\nTe2[x] = S [x].[01, 03, 02, 01];\nTe3[x] = S [x].[01, 01, 03, 02];\nTe4[x] = S [x].[01, 01, 01, 01];\n\nTd0[x] = Si[x].[0e, 09, 0d, 0b];\nTd1[x] = Si[x].[0b, 0e, 09, 0d];\nTd2[x] = Si[x].[0d, 0b, 0e, 09];\nTd3[x] = Si[x].[09, 0d, 0b, 0e];\nTd4[x] = Si[x].[01, 01, 01, 01];\n*/\n\nstatic const u32 Te0[256] = {\n    0xc66363a5U, 0xf87c7c84U, 0xee777799U, 0xf67b7b8dU,\n    0xfff2f20dU, 0xd66b6bbdU, 0xde6f6fb1U, 0x91c5c554U,\n    0x60303050U, 0x02010103U, 0xce6767a9U, 0x562b2b7dU,\n    0xe7fefe19U, 0xb5d7d762U, 0x4dababe6U, 0xec76769aU,\n    0x8fcaca45U, 0x1f82829dU, 0x89c9c940U, 0xfa7d7d87U,\n    0xeffafa15U, 0xb25959ebU, 0x8e4747c9U, 0xfbf0f00bU,\n    0x41adadecU, 0xb3d4d467U, 0x5fa2a2fdU, 0x45afafeaU,\n    0x239c9cbfU, 0x53a4a4f7U, 0xe4727296U, 0x9bc0c05bU,\n    0x75b7b7c2U, 0xe1fdfd1cU, 0x3d9393aeU, 0x4c26266aU,\n    0x6c36365aU, 0x7e3f3f41U, 0xf5f7f702U, 0x83cccc4fU,\n    0x6834345cU, 0x51a5a5f4U, 0xd1e5e534U, 0xf9f1f108U,\n    0xe2717193U, 0xabd8d873U, 0x62313153U, 0x2a15153fU,\n    0x0804040cU, 0x95c7c752U, 0x46232365U, 0x9dc3c35eU,\n    0x30181828U, 0x379696a1U, 0x0a05050fU, 0x2f9a9ab5U,\n    0x0e070709U, 0x24121236U, 0x1b80809bU, 0xdfe2e23dU,\n    0xcdebeb26U, 0x4e272769U, 0x7fb2b2cdU, 0xea75759fU,\n    0x1209091bU, 0x1d83839eU, 0x582c2c74U, 0x341a1a2eU,\n    0x361b1b2dU, 0xdc6e6eb2U, 0xb45a5aeeU, 0x5ba0a0fbU,\n    0xa45252f6U, 0x763b3b4dU, 0xb7d6d661U, 0x7db3b3ceU,\n    0x5229297bU, 0xdde3e33eU, 0x5e2f2f71U, 0x13848497U,\n    0xa65353f5U, 0xb9d1d168U, 0x00000000U, 0xc1eded2cU,\n    0x40202060U, 0xe3fcfc1fU, 0x79b1b1c8U, 0xb65b5bedU,\n    0xd46a6abeU, 0x8dcbcb46U, 0x67bebed9U, 0x7239394bU,\n    0x944a4adeU, 0x984c4cd4U, 0xb05858e8U, 0x85cfcf4aU,\n    0xbbd0d06bU, 0xc5efef2aU, 0x4faaaae5U, 0xedfbfb16U,\n    0x864343c5U, 0x9a4d4dd7U, 0x66333355U, 0x11858594U,\n    0x8a4545cfU, 0xe9f9f910U, 0x04020206U, 0xfe7f7f81U,\n    0xa05050f0U, 0x783c3c44U, 0x259f9fbaU, 0x4ba8a8e3U,\n    0xa25151f3U, 0x5da3a3feU, 0x804040c0U, 0x058f8f8aU,\n    0x3f9292adU, 0x219d9dbcU, 0x70383848U, 0xf1f5f504U,\n    0x63bcbcdfU, 0x77b6b6c1U, 0xafdada75U, 0x42212163U,\n    0x20101030U, 0xe5ffff1aU, 0xfdf3f30eU, 0xbfd2d26dU,\n    0x81cdcd4cU, 0x180c0c14U, 0x26131335U, 0xc3ecec2fU,\n    0xbe5f5fe1U, 0x359797a2U, 0x884444ccU, 0x2e171739U,\n    0x93c4c457U, 0x55a7a7f2U, 0xfc7e7e82U, 0x7a3d3d47U,\n    0xc86464acU, 0xba5d5de7U, 0x3219192bU, 0xe6737395U,\n    0xc06060a0U, 0x19818198U, 0x9e4f4fd1U, 0xa3dcdc7fU,\n    0x44222266U, 0x542a2a7eU, 0x3b9090abU, 0x0b888883U,\n    0x8c4646caU, 0xc7eeee29U, 0x6bb8b8d3U, 0x2814143cU,\n    0xa7dede79U, 0xbc5e5ee2U, 0x160b0b1dU, 0xaddbdb76U,\n    0xdbe0e03bU, 0x64323256U, 0x743a3a4eU, 0x140a0a1eU,\n    0x924949dbU, 0x0c06060aU, 0x4824246cU, 0xb85c5ce4U,\n    0x9fc2c25dU, 0xbdd3d36eU, 0x43acacefU, 0xc46262a6U,\n    0x399191a8U, 0x319595a4U, 0xd3e4e437U, 0xf279798bU,\n    0xd5e7e732U, 0x8bc8c843U, 0x6e373759U, 0xda6d6db7U,\n    0x018d8d8cU, 0xb1d5d564U, 0x9c4e4ed2U, 0x49a9a9e0U,\n    0xd86c6cb4U, 0xac5656faU, 0xf3f4f407U, 0xcfeaea25U,\n    0xca6565afU, 0xf47a7a8eU, 0x47aeaee9U, 0x10080818U,\n    0x6fbabad5U, 0xf0787888U, 0x4a25256fU, 0x5c2e2e72U,\n    0x381c1c24U, 0x57a6a6f1U, 0x73b4b4c7U, 0x97c6c651U,\n    0xcbe8e823U, 0xa1dddd7cU, 0xe874749cU, 0x3e1f1f21U,\n    0x964b4bddU, 0x61bdbddcU, 0x0d8b8b86U, 0x0f8a8a85U,\n    0xe0707090U, 0x7c3e3e42U, 0x71b5b5c4U, 0xcc6666aaU,\n    0x904848d8U, 0x06030305U, 0xf7f6f601U, 0x1c0e0e12U,\n    0xc26161a3U, 0x6a35355fU, 0xae5757f9U, 0x69b9b9d0U,\n    0x17868691U, 0x99c1c158U, 0x3a1d1d27U, 0x279e9eb9U,\n    0xd9e1e138U, 0xebf8f813U, 0x2b9898b3U, 0x22111133U,\n    0xd26969bbU, 0xa9d9d970U, 0x078e8e89U, 0x339494a7U,\n    0x2d9b9bb6U, 0x3c1e1e22U, 0x15878792U, 0xc9e9e920U,\n    0x87cece49U, 0xaa5555ffU, 0x50282878U, 0xa5dfdf7aU,\n    0x038c8c8fU, 0x59a1a1f8U, 0x09898980U, 0x1a0d0d17U,\n    0x65bfbfdaU, 0xd7e6e631U, 0x844242c6U, 0xd06868b8U,\n    0x824141c3U, 0x299999b0U, 0x5a2d2d77U, 0x1e0f0f11U,\n    0x7bb0b0cbU, 0xa85454fcU, 0x6dbbbbd6U, 0x2c16163aU,\n};\n#ifndef AES_SMALL_TABLES\nstatic const u32 Te1[256] = {\n    0xa5c66363U, 0x84f87c7cU, 0x99ee7777U, 0x8df67b7bU,\n    0x0dfff2f2U, 0xbdd66b6bU, 0xb1de6f6fU, 0x5491c5c5U,\n    0x50603030U, 0x03020101U, 0xa9ce6767U, 0x7d562b2bU,\n    0x19e7fefeU, 0x62b5d7d7U, 0xe64dababU, 0x9aec7676U,\n    0x458fcacaU, 0x9d1f8282U, 0x4089c9c9U, 0x87fa7d7dU,\n    0x15effafaU, 0xebb25959U, 0xc98e4747U, 0x0bfbf0f0U,\n    0xec41adadU, 0x67b3d4d4U, 0xfd5fa2a2U, 0xea45afafU,\n    0xbf239c9cU, 0xf753a4a4U, 0x96e47272U, 0x5b9bc0c0U,\n    0xc275b7b7U, 0x1ce1fdfdU, 0xae3d9393U, 0x6a4c2626U,\n    0x5a6c3636U, 0x417e3f3fU, 0x02f5f7f7U, 0x4f83ccccU,\n    0x5c683434U, 0xf451a5a5U, 0x34d1e5e5U, 0x08f9f1f1U,\n    0x93e27171U, 0x73abd8d8U, 0x53623131U, 0x3f2a1515U,\n    0x0c080404U, 0x5295c7c7U, 0x65462323U, 0x5e9dc3c3U,\n    0x28301818U, 0xa1379696U, 0x0f0a0505U, 0xb52f9a9aU,\n    0x090e0707U, 0x36241212U, 0x9b1b8080U, 0x3ddfe2e2U,\n    0x26cdebebU, 0x694e2727U, 0xcd7fb2b2U, 0x9fea7575U,\n    0x1b120909U, 0x9e1d8383U, 0x74582c2cU, 0x2e341a1aU,\n    0x2d361b1bU, 0xb2dc6e6eU, 0xeeb45a5aU, 0xfb5ba0a0U,\n    0xf6a45252U, 0x4d763b3bU, 0x61b7d6d6U, 0xce7db3b3U,\n    0x7b522929U, 0x3edde3e3U, 0x715e2f2fU, 0x97138484U,\n    0xf5a65353U, 0x68b9d1d1U, 0x00000000U, 0x2cc1ededU,\n    0x60402020U, 0x1fe3fcfcU, 0xc879b1b1U, 0xedb65b5bU,\n    0xbed46a6aU, 0x468dcbcbU, 0xd967bebeU, 0x4b723939U,\n    0xde944a4aU, 0xd4984c4cU, 0xe8b05858U, 0x4a85cfcfU,\n    0x6bbbd0d0U, 0x2ac5efefU, 0xe54faaaaU, 0x16edfbfbU,\n    0xc5864343U, 0xd79a4d4dU, 0x55663333U, 0x94118585U,\n    0xcf8a4545U, 0x10e9f9f9U, 0x06040202U, 0x81fe7f7fU,\n    0xf0a05050U, 0x44783c3cU, 0xba259f9fU, 0xe34ba8a8U,\n    0xf3a25151U, 0xfe5da3a3U, 0xc0804040U, 0x8a058f8fU,\n    0xad3f9292U, 0xbc219d9dU, 0x48703838U, 0x04f1f5f5U,\n    0xdf63bcbcU, 0xc177b6b6U, 0x75afdadaU, 0x63422121U,\n    0x30201010U, 0x1ae5ffffU, 0x0efdf3f3U, 0x6dbfd2d2U,\n    0x4c81cdcdU, 0x14180c0cU, 0x35261313U, 0x2fc3ececU,\n    0xe1be5f5fU, 0xa2359797U, 0xcc884444U, 0x392e1717U,\n    0x5793c4c4U, 0xf255a7a7U, 0x82fc7e7eU, 0x477a3d3dU,\n    0xacc86464U, 0xe7ba5d5dU, 0x2b321919U, 0x95e67373U,\n    0xa0c06060U, 0x98198181U, 0xd19e4f4fU, 0x7fa3dcdcU,\n    0x66442222U, 0x7e542a2aU, 0xab3b9090U, 0x830b8888U,\n    0xca8c4646U, 0x29c7eeeeU, 0xd36bb8b8U, 0x3c281414U,\n    0x79a7dedeU, 0xe2bc5e5eU, 0x1d160b0bU, 0x76addbdbU,\n    0x3bdbe0e0U, 0x56643232U, 0x4e743a3aU, 0x1e140a0aU,\n    0xdb924949U, 0x0a0c0606U, 0x6c482424U, 0xe4b85c5cU,\n    0x5d9fc2c2U, 0x6ebdd3d3U, 0xef43acacU, 0xa6c46262U,\n    0xa8399191U, 0xa4319595U, 0x37d3e4e4U, 0x8bf27979U,\n    0x32d5e7e7U, 0x438bc8c8U, 0x596e3737U, 0xb7da6d6dU,\n    0x8c018d8dU, 0x64b1d5d5U, 0xd29c4e4eU, 0xe049a9a9U,\n    0xb4d86c6cU, 0xfaac5656U, 0x07f3f4f4U, 0x25cfeaeaU,\n    0xafca6565U, 0x8ef47a7aU, 0xe947aeaeU, 0x18100808U,\n    0xd56fbabaU, 0x88f07878U, 0x6f4a2525U, 0x725c2e2eU,\n    0x24381c1cU, 0xf157a6a6U, 0xc773b4b4U, 0x5197c6c6U,\n    0x23cbe8e8U, 0x7ca1ddddU, 0x9ce87474U, 0x213e1f1fU,\n    0xdd964b4bU, 0xdc61bdbdU, 0x860d8b8bU, 0x850f8a8aU,\n    0x90e07070U, 0x427c3e3eU, 0xc471b5b5U, 0xaacc6666U,\n    0xd8904848U, 0x05060303U, 0x01f7f6f6U, 0x121c0e0eU,\n    0xa3c26161U, 0x5f6a3535U, 0xf9ae5757U, 0xd069b9b9U,\n    0x91178686U, 0x5899c1c1U, 0x273a1d1dU, 0xb9279e9eU,\n    0x38d9e1e1U, 0x13ebf8f8U, 0xb32b9898U, 0x33221111U,\n    0xbbd26969U, 0x70a9d9d9U, 0x89078e8eU, 0xa7339494U,\n    0xb62d9b9bU, 0x223c1e1eU, 0x92158787U, 0x20c9e9e9U,\n    0x4987ceceU, 0xffaa5555U, 0x78502828U, 0x7aa5dfdfU,\n    0x8f038c8cU, 0xf859a1a1U, 0x80098989U, 0x171a0d0dU,\n    0xda65bfbfU, 0x31d7e6e6U, 0xc6844242U, 0xb8d06868U,\n    0xc3824141U, 0xb0299999U, 0x775a2d2dU, 0x111e0f0fU,\n    0xcb7bb0b0U, 0xfca85454U, 0xd66dbbbbU, 0x3a2c1616U,\n};\nstatic const u32 Te2[256] = {\n    0x63a5c663U, 0x7c84f87cU, 0x7799ee77U, 0x7b8df67bU,\n    0xf20dfff2U, 0x6bbdd66bU, 0x6fb1de6fU, 0xc55491c5U,\n    0x30506030U, 0x01030201U, 0x67a9ce67U, 0x2b7d562bU,\n    0xfe19e7feU, 0xd762b5d7U, 0xabe64dabU, 0x769aec76U,\n    0xca458fcaU, 0x829d1f82U, 0xc94089c9U, 0x7d87fa7dU,\n    0xfa15effaU, 0x59ebb259U, 0x47c98e47U, 0xf00bfbf0U,\n    0xadec41adU, 0xd467b3d4U, 0xa2fd5fa2U, 0xafea45afU,\n    0x9cbf239cU, 0xa4f753a4U, 0x7296e472U, 0xc05b9bc0U,\n    0xb7c275b7U, 0xfd1ce1fdU, 0x93ae3d93U, 0x266a4c26U,\n    0x365a6c36U, 0x3f417e3fU, 0xf702f5f7U, 0xcc4f83ccU,\n    0x345c6834U, 0xa5f451a5U, 0xe534d1e5U, 0xf108f9f1U,\n    0x7193e271U, 0xd873abd8U, 0x31536231U, 0x153f2a15U,\n    0x040c0804U, 0xc75295c7U, 0x23654623U, 0xc35e9dc3U,\n    0x18283018U, 0x96a13796U, 0x050f0a05U, 0x9ab52f9aU,\n    0x07090e07U, 0x12362412U, 0x809b1b80U, 0xe23ddfe2U,\n    0xeb26cdebU, 0x27694e27U, 0xb2cd7fb2U, 0x759fea75U,\n    0x091b1209U, 0x839e1d83U, 0x2c74582cU, 0x1a2e341aU,\n    0x1b2d361bU, 0x6eb2dc6eU, 0x5aeeb45aU, 0xa0fb5ba0U,\n    0x52f6a452U, 0x3b4d763bU, 0xd661b7d6U, 0xb3ce7db3U,\n    0x297b5229U, 0xe33edde3U, 0x2f715e2fU, 0x84971384U,\n    0x53f5a653U, 0xd168b9d1U, 0x00000000U, 0xed2cc1edU,\n    0x20604020U, 0xfc1fe3fcU, 0xb1c879b1U, 0x5bedb65bU,\n    0x6abed46aU, 0xcb468dcbU, 0xbed967beU, 0x394b7239U,\n    0x4ade944aU, 0x4cd4984cU, 0x58e8b058U, 0xcf4a85cfU,\n    0xd06bbbd0U, 0xef2ac5efU, 0xaae54faaU, 0xfb16edfbU,\n    0x43c58643U, 0x4dd79a4dU, 0x33556633U, 0x85941185U,\n    0x45cf8a45U, 0xf910e9f9U, 0x02060402U, 0x7f81fe7fU,\n    0x50f0a050U, 0x3c44783cU, 0x9fba259fU, 0xa8e34ba8U,\n    0x51f3a251U, 0xa3fe5da3U, 0x40c08040U, 0x8f8a058fU,\n    0x92ad3f92U, 0x9dbc219dU, 0x38487038U, 0xf504f1f5U,\n    0xbcdf63bcU, 0xb6c177b6U, 0xda75afdaU, 0x21634221U,\n    0x10302010U, 0xff1ae5ffU, 0xf30efdf3U, 0xd26dbfd2U,\n    0xcd4c81cdU, 0x0c14180cU, 0x13352613U, 0xec2fc3ecU,\n    0x5fe1be5fU, 0x97a23597U, 0x44cc8844U, 0x17392e17U,\n    0xc45793c4U, 0xa7f255a7U, 0x7e82fc7eU, 0x3d477a3dU,\n    0x64acc864U, 0x5de7ba5dU, 0x192b3219U, 0x7395e673U,\n    0x60a0c060U, 0x81981981U, 0x4fd19e4fU, 0xdc7fa3dcU,\n    0x22664422U, 0x2a7e542aU, 0x90ab3b90U, 0x88830b88U,\n    0x46ca8c46U, 0xee29c7eeU, 0xb8d36bb8U, 0x143c2814U,\n    0xde79a7deU, 0x5ee2bc5eU, 0x0b1d160bU, 0xdb76addbU,\n    0xe03bdbe0U, 0x32566432U, 0x3a4e743aU, 0x0a1e140aU,\n    0x49db9249U, 0x060a0c06U, 0x246c4824U, 0x5ce4b85cU,\n    0xc25d9fc2U, 0xd36ebdd3U, 0xacef43acU, 0x62a6c462U,\n    0x91a83991U, 0x95a43195U, 0xe437d3e4U, 0x798bf279U,\n    0xe732d5e7U, 0xc8438bc8U, 0x37596e37U, 0x6db7da6dU,\n    0x8d8c018dU, 0xd564b1d5U, 0x4ed29c4eU, 0xa9e049a9U,\n    0x6cb4d86cU, 0x56faac56U, 0xf407f3f4U, 0xea25cfeaU,\n    0x65afca65U, 0x7a8ef47aU, 0xaee947aeU, 0x08181008U,\n    0xbad56fbaU, 0x7888f078U, 0x256f4a25U, 0x2e725c2eU,\n    0x1c24381cU, 0xa6f157a6U, 0xb4c773b4U, 0xc65197c6U,\n    0xe823cbe8U, 0xdd7ca1ddU, 0x749ce874U, 0x1f213e1fU,\n    0x4bdd964bU, 0xbddc61bdU, 0x8b860d8bU, 0x8a850f8aU,\n    0x7090e070U, 0x3e427c3eU, 0xb5c471b5U, 0x66aacc66U,\n    0x48d89048U, 0x03050603U, 0xf601f7f6U, 0x0e121c0eU,\n    0x61a3c261U, 0x355f6a35U, 0x57f9ae57U, 0xb9d069b9U,\n    0x86911786U, 0xc15899c1U, 0x1d273a1dU, 0x9eb9279eU,\n    0xe138d9e1U, 0xf813ebf8U, 0x98b32b98U, 0x11332211U,\n    0x69bbd269U, 0xd970a9d9U, 0x8e89078eU, 0x94a73394U,\n    0x9bb62d9bU, 0x1e223c1eU, 0x87921587U, 0xe920c9e9U,\n    0xce4987ceU, 0x55ffaa55U, 0x28785028U, 0xdf7aa5dfU,\n    0x8c8f038cU, 0xa1f859a1U, 0x89800989U, 0x0d171a0dU,\n    0xbfda65bfU, 0xe631d7e6U, 0x42c68442U, 0x68b8d068U,\n    0x41c38241U, 0x99b02999U, 0x2d775a2dU, 0x0f111e0fU,\n    0xb0cb7bb0U, 0x54fca854U, 0xbbd66dbbU, 0x163a2c16U,\n};\nstatic const u32 Te3[256] = {\n\n    0x6363a5c6U, 0x7c7c84f8U, 0x777799eeU, 0x7b7b8df6U,\n    0xf2f20dffU, 0x6b6bbdd6U, 0x6f6fb1deU, 0xc5c55491U,\n    0x30305060U, 0x01010302U, 0x6767a9ceU, 0x2b2b7d56U,\n    0xfefe19e7U, 0xd7d762b5U, 0xababe64dU, 0x76769aecU,\n    0xcaca458fU, 0x82829d1fU, 0xc9c94089U, 0x7d7d87faU,\n    0xfafa15efU, 0x5959ebb2U, 0x4747c98eU, 0xf0f00bfbU,\n    0xadadec41U, 0xd4d467b3U, 0xa2a2fd5fU, 0xafafea45U,\n    0x9c9cbf23U, 0xa4a4f753U, 0x727296e4U, 0xc0c05b9bU,\n    0xb7b7c275U, 0xfdfd1ce1U, 0x9393ae3dU, 0x26266a4cU,\n    0x36365a6cU, 0x3f3f417eU, 0xf7f702f5U, 0xcccc4f83U,\n    0x34345c68U, 0xa5a5f451U, 0xe5e534d1U, 0xf1f108f9U,\n    0x717193e2U, 0xd8d873abU, 0x31315362U, 0x15153f2aU,\n    0x04040c08U, 0xc7c75295U, 0x23236546U, 0xc3c35e9dU,\n    0x18182830U, 0x9696a137U, 0x05050f0aU, 0x9a9ab52fU,\n    0x0707090eU, 0x12123624U, 0x80809b1bU, 0xe2e23ddfU,\n    0xebeb26cdU, 0x2727694eU, 0xb2b2cd7fU, 0x75759feaU,\n    0x09091b12U, 0x83839e1dU, 0x2c2c7458U, 0x1a1a2e34U,\n    0x1b1b2d36U, 0x6e6eb2dcU, 0x5a5aeeb4U, 0xa0a0fb5bU,\n    0x5252f6a4U, 0x3b3b4d76U, 0xd6d661b7U, 0xb3b3ce7dU,\n    0x29297b52U, 0xe3e33eddU, 0x2f2f715eU, 0x84849713U,\n    0x5353f5a6U, 0xd1d168b9U, 0x00000000U, 0xeded2cc1U,\n    0x20206040U, 0xfcfc1fe3U, 0xb1b1c879U, 0x5b5bedb6U,\n    0x6a6abed4U, 0xcbcb468dU, 0xbebed967U, 0x39394b72U,\n    0x4a4ade94U, 0x4c4cd498U, 0x5858e8b0U, 0xcfcf4a85U,\n    0xd0d06bbbU, 0xefef2ac5U, 0xaaaae54fU, 0xfbfb16edU,\n    0x4343c586U, 0x4d4dd79aU, 0x33335566U, 0x85859411U,\n    0x4545cf8aU, 0xf9f910e9U, 0x02020604U, 0x7f7f81feU,\n    0x5050f0a0U, 0x3c3c4478U, 0x9f9fba25U, 0xa8a8e34bU,\n    0x5151f3a2U, 0xa3a3fe5dU, 0x4040c080U, 0x8f8f8a05U,\n    0x9292ad3fU, 0x9d9dbc21U, 0x38384870U, 0xf5f504f1U,\n    0xbcbcdf63U, 0xb6b6c177U, 0xdada75afU, 0x21216342U,\n    0x10103020U, 0xffff1ae5U, 0xf3f30efdU, 0xd2d26dbfU,\n    0xcdcd4c81U, 0x0c0c1418U, 0x13133526U, 0xecec2fc3U,\n    0x5f5fe1beU, 0x9797a235U, 0x4444cc88U, 0x1717392eU,\n    0xc4c45793U, 0xa7a7f255U, 0x7e7e82fcU, 0x3d3d477aU,\n    0x6464acc8U, 0x5d5de7baU, 0x19192b32U, 0x737395e6U,\n    0x6060a0c0U, 0x81819819U, 0x4f4fd19eU, 0xdcdc7fa3U,\n    0x22226644U, 0x2a2a7e54U, 0x9090ab3bU, 0x8888830bU,\n    0x4646ca8cU, 0xeeee29c7U, 0xb8b8d36bU, 0x14143c28U,\n    0xdede79a7U, 0x5e5ee2bcU, 0x0b0b1d16U, 0xdbdb76adU,\n    0xe0e03bdbU, 0x32325664U, 0x3a3a4e74U, 0x0a0a1e14U,\n    0x4949db92U, 0x06060a0cU, 0x24246c48U, 0x5c5ce4b8U,\n    0xc2c25d9fU, 0xd3d36ebdU, 0xacacef43U, 0x6262a6c4U,\n    0x9191a839U, 0x9595a431U, 0xe4e437d3U, 0x79798bf2U,\n    0xe7e732d5U, 0xc8c8438bU, 0x3737596eU, 0x6d6db7daU,\n    0x8d8d8c01U, 0xd5d564b1U, 0x4e4ed29cU, 0xa9a9e049U,\n    0x6c6cb4d8U, 0x5656faacU, 0xf4f407f3U, 0xeaea25cfU,\n    0x6565afcaU, 0x7a7a8ef4U, 0xaeaee947U, 0x08081810U,\n    0xbabad56fU, 0x787888f0U, 0x25256f4aU, 0x2e2e725cU,\n    0x1c1c2438U, 0xa6a6f157U, 0xb4b4c773U, 0xc6c65197U,\n    0xe8e823cbU, 0xdddd7ca1U, 0x74749ce8U, 0x1f1f213eU,\n    0x4b4bdd96U, 0xbdbddc61U, 0x8b8b860dU, 0x8a8a850fU,\n    0x707090e0U, 0x3e3e427cU, 0xb5b5c471U, 0x6666aaccU,\n    0x4848d890U, 0x03030506U, 0xf6f601f7U, 0x0e0e121cU,\n    0x6161a3c2U, 0x35355f6aU, 0x5757f9aeU, 0xb9b9d069U,\n    0x86869117U, 0xc1c15899U, 0x1d1d273aU, 0x9e9eb927U,\n    0xe1e138d9U, 0xf8f813ebU, 0x9898b32bU, 0x11113322U,\n    0x6969bbd2U, 0xd9d970a9U, 0x8e8e8907U, 0x9494a733U,\n    0x9b9bb62dU, 0x1e1e223cU, 0x87879215U, 0xe9e920c9U,\n    0xcece4987U, 0x5555ffaaU, 0x28287850U, 0xdfdf7aa5U,\n    0x8c8c8f03U, 0xa1a1f859U, 0x89898009U, 0x0d0d171aU,\n    0xbfbfda65U, 0xe6e631d7U, 0x4242c684U, 0x6868b8d0U,\n    0x4141c382U, 0x9999b029U, 0x2d2d775aU, 0x0f0f111eU,\n    0xb0b0cb7bU, 0x5454fca8U, 0xbbbbd66dU, 0x16163a2cU,\n};\nstatic const u32 Te4[256] = {\n    0x63636363U, 0x7c7c7c7cU, 0x77777777U, 0x7b7b7b7bU,\n    0xf2f2f2f2U, 0x6b6b6b6bU, 0x6f6f6f6fU, 0xc5c5c5c5U,\n    0x30303030U, 0x01010101U, 0x67676767U, 0x2b2b2b2bU,\n    0xfefefefeU, 0xd7d7d7d7U, 0xababababU, 0x76767676U,\n    0xcacacacaU, 0x82828282U, 0xc9c9c9c9U, 0x7d7d7d7dU,\n    0xfafafafaU, 0x59595959U, 0x47474747U, 0xf0f0f0f0U,\n    0xadadadadU, 0xd4d4d4d4U, 0xa2a2a2a2U, 0xafafafafU,\n    0x9c9c9c9cU, 0xa4a4a4a4U, 0x72727272U, 0xc0c0c0c0U,\n    0xb7b7b7b7U, 0xfdfdfdfdU, 0x93939393U, 0x26262626U,\n    0x36363636U, 0x3f3f3f3fU, 0xf7f7f7f7U, 0xccccccccU,\n    0x34343434U, 0xa5a5a5a5U, 0xe5e5e5e5U, 0xf1f1f1f1U,\n    0x71717171U, 0xd8d8d8d8U, 0x31313131U, 0x15151515U,\n    0x04040404U, 0xc7c7c7c7U, 0x23232323U, 0xc3c3c3c3U,\n    0x18181818U, 0x96969696U, 0x05050505U, 0x9a9a9a9aU,\n    0x07070707U, 0x12121212U, 0x80808080U, 0xe2e2e2e2U,\n    0xebebebebU, 0x27272727U, 0xb2b2b2b2U, 0x75757575U,\n    0x09090909U, 0x83838383U, 0x2c2c2c2cU, 0x1a1a1a1aU,\n    0x1b1b1b1bU, 0x6e6e6e6eU, 0x5a5a5a5aU, 0xa0a0a0a0U,\n    0x52525252U, 0x3b3b3b3bU, 0xd6d6d6d6U, 0xb3b3b3b3U,\n    0x29292929U, 0xe3e3e3e3U, 0x2f2f2f2fU, 0x84848484U,\n    0x53535353U, 0xd1d1d1d1U, 0x00000000U, 0xededededU,\n    0x20202020U, 0xfcfcfcfcU, 0xb1b1b1b1U, 0x5b5b5b5bU,\n    0x6a6a6a6aU, 0xcbcbcbcbU, 0xbebebebeU, 0x39393939U,\n    0x4a4a4a4aU, 0x4c4c4c4cU, 0x58585858U, 0xcfcfcfcfU,\n    0xd0d0d0d0U, 0xefefefefU, 0xaaaaaaaaU, 0xfbfbfbfbU,\n    0x43434343U, 0x4d4d4d4dU, 0x33333333U, 0x85858585U,\n    0x45454545U, 0xf9f9f9f9U, 0x02020202U, 0x7f7f7f7fU,\n    0x50505050U, 0x3c3c3c3cU, 0x9f9f9f9fU, 0xa8a8a8a8U,\n    0x51515151U, 0xa3a3a3a3U, 0x40404040U, 0x8f8f8f8fU,\n    0x92929292U, 0x9d9d9d9dU, 0x38383838U, 0xf5f5f5f5U,\n    0xbcbcbcbcU, 0xb6b6b6b6U, 0xdadadadaU, 0x21212121U,\n    0x10101010U, 0xffffffffU, 0xf3f3f3f3U, 0xd2d2d2d2U,\n    0xcdcdcdcdU, 0x0c0c0c0cU, 0x13131313U, 0xececececU,\n    0x5f5f5f5fU, 0x97979797U, 0x44444444U, 0x17171717U,\n    0xc4c4c4c4U, 0xa7a7a7a7U, 0x7e7e7e7eU, 0x3d3d3d3dU,\n    0x64646464U, 0x5d5d5d5dU, 0x19191919U, 0x73737373U,\n    0x60606060U, 0x81818181U, 0x4f4f4f4fU, 0xdcdcdcdcU,\n    0x22222222U, 0x2a2a2a2aU, 0x90909090U, 0x88888888U,\n    0x46464646U, 0xeeeeeeeeU, 0xb8b8b8b8U, 0x14141414U,\n    0xdedededeU, 0x5e5e5e5eU, 0x0b0b0b0bU, 0xdbdbdbdbU,\n    0xe0e0e0e0U, 0x32323232U, 0x3a3a3a3aU, 0x0a0a0a0aU,\n    0x49494949U, 0x06060606U, 0x24242424U, 0x5c5c5c5cU,\n    0xc2c2c2c2U, 0xd3d3d3d3U, 0xacacacacU, 0x62626262U,\n    0x91919191U, 0x95959595U, 0xe4e4e4e4U, 0x79797979U,\n    0xe7e7e7e7U, 0xc8c8c8c8U, 0x37373737U, 0x6d6d6d6dU,\n    0x8d8d8d8dU, 0xd5d5d5d5U, 0x4e4e4e4eU, 0xa9a9a9a9U,\n    0x6c6c6c6cU, 0x56565656U, 0xf4f4f4f4U, 0xeaeaeaeaU,\n    0x65656565U, 0x7a7a7a7aU, 0xaeaeaeaeU, 0x08080808U,\n    0xbabababaU, 0x78787878U, 0x25252525U, 0x2e2e2e2eU,\n    0x1c1c1c1cU, 0xa6a6a6a6U, 0xb4b4b4b4U, 0xc6c6c6c6U,\n    0xe8e8e8e8U, 0xddddddddU, 0x74747474U, 0x1f1f1f1fU,\n    0x4b4b4b4bU, 0xbdbdbdbdU, 0x8b8b8b8bU, 0x8a8a8a8aU,\n    0x70707070U, 0x3e3e3e3eU, 0xb5b5b5b5U, 0x66666666U,\n    0x48484848U, 0x03030303U, 0xf6f6f6f6U, 0x0e0e0e0eU,\n    0x61616161U, 0x35353535U, 0x57575757U, 0xb9b9b9b9U,\n    0x86868686U, 0xc1c1c1c1U, 0x1d1d1d1dU, 0x9e9e9e9eU,\n    0xe1e1e1e1U, 0xf8f8f8f8U, 0x98989898U, 0x11111111U,\n    0x69696969U, 0xd9d9d9d9U, 0x8e8e8e8eU, 0x94949494U,\n    0x9b9b9b9bU, 0x1e1e1e1eU, 0x87878787U, 0xe9e9e9e9U,\n    0xcecececeU, 0x55555555U, 0x28282828U, 0xdfdfdfdfU,\n    0x8c8c8c8cU, 0xa1a1a1a1U, 0x89898989U, 0x0d0d0d0dU,\n    0xbfbfbfbfU, 0xe6e6e6e6U, 0x42424242U, 0x68686868U,\n    0x41414141U, 0x99999999U, 0x2d2d2d2dU, 0x0f0f0f0fU,\n    0xb0b0b0b0U, 0x54545454U, 0xbbbbbbbbU, 0x16161616U,\n};\n#endif /* AES_SMALL_TABLES */\nstatic const u32 Td0[256] = {\n    0x51f4a750U, 0x7e416553U, 0x1a17a4c3U, 0x3a275e96U,\n    0x3bab6bcbU, 0x1f9d45f1U, 0xacfa58abU, 0x4be30393U,\n    0x2030fa55U, 0xad766df6U, 0x88cc7691U, 0xf5024c25U,\n    0x4fe5d7fcU, 0xc52acbd7U, 0x26354480U, 0xb562a38fU,\n    0xdeb15a49U, 0x25ba1b67U, 0x45ea0e98U, 0x5dfec0e1U,\n    0xc32f7502U, 0x814cf012U, 0x8d4697a3U, 0x6bd3f9c6U,\n    0x038f5fe7U, 0x15929c95U, 0xbf6d7aebU, 0x955259daU,\n    0xd4be832dU, 0x587421d3U, 0x49e06929U, 0x8ec9c844U,\n    0x75c2896aU, 0xf48e7978U, 0x99583e6bU, 0x27b971ddU,\n    0xbee14fb6U, 0xf088ad17U, 0xc920ac66U, 0x7dce3ab4U,\n    0x63df4a18U, 0xe51a3182U, 0x97513360U, 0x62537f45U,\n    0xb16477e0U, 0xbb6bae84U, 0xfe81a01cU, 0xf9082b94U,\n    0x70486858U, 0x8f45fd19U, 0x94de6c87U, 0x527bf8b7U,\n    0xab73d323U, 0x724b02e2U, 0xe31f8f57U, 0x6655ab2aU,\n    0xb2eb2807U, 0x2fb5c203U, 0x86c57b9aU, 0xd33708a5U,\n    0x302887f2U, 0x23bfa5b2U, 0x02036abaU, 0xed16825cU,\n    0x8acf1c2bU, 0xa779b492U, 0xf307f2f0U, 0x4e69e2a1U,\n    0x65daf4cdU, 0x0605bed5U, 0xd134621fU, 0xc4a6fe8aU,\n    0x342e539dU, 0xa2f355a0U, 0x058ae132U, 0xa4f6eb75U,\n    0x0b83ec39U, 0x4060efaaU, 0x5e719f06U, 0xbd6e1051U,\n    0x3e218af9U, 0x96dd063dU, 0xdd3e05aeU, 0x4de6bd46U,\n    0x91548db5U, 0x71c45d05U, 0x0406d46fU, 0x605015ffU,\n    0x1998fb24U, 0xd6bde997U, 0x894043ccU, 0x67d99e77U,\n    0xb0e842bdU, 0x07898b88U, 0xe7195b38U, 0x79c8eedbU,\n    0xa17c0a47U, 0x7c420fe9U, 0xf8841ec9U, 0x00000000U,\n    0x09808683U, 0x322bed48U, 0x1e1170acU, 0x6c5a724eU,\n    0xfd0efffbU, 0x0f853856U, 0x3daed51eU, 0x362d3927U,\n    0x0a0fd964U, 0x685ca621U, 0x9b5b54d1U, 0x24362e3aU,\n    0x0c0a67b1U, 0x9357e70fU, 0xb4ee96d2U, 0x1b9b919eU,\n    0x80c0c54fU, 0x61dc20a2U, 0x5a774b69U, 0x1c121a16U,\n    0xe293ba0aU, 0xc0a02ae5U, 0x3c22e043U, 0x121b171dU,\n    0x0e090d0bU, 0xf28bc7adU, 0x2db6a8b9U, 0x141ea9c8U,\n    0x57f11985U, 0xaf75074cU, 0xee99ddbbU, 0xa37f60fdU,\n    0xf701269fU, 0x5c72f5bcU, 0x44663bc5U, 0x5bfb7e34U,\n    0x8b432976U, 0xcb23c6dcU, 0xb6edfc68U, 0xb8e4f163U,\n    0xd731dccaU, 0x42638510U, 0x13972240U, 0x84c61120U,\n    0x854a247dU, 0xd2bb3df8U, 0xaef93211U, 0xc729a16dU,\n    0x1d9e2f4bU, 0xdcb230f3U, 0x0d8652ecU, 0x77c1e3d0U,\n    0x2bb3166cU, 0xa970b999U, 0x119448faU, 0x47e96422U,\n    0xa8fc8cc4U, 0xa0f03f1aU, 0x567d2cd8U, 0x223390efU,\n    0x87494ec7U, 0xd938d1c1U, 0x8ccaa2feU, 0x98d40b36U,\n    0xa6f581cfU, 0xa57ade28U, 0xdab78e26U, 0x3fadbfa4U,\n    0x2c3a9de4U, 0x5078920dU, 0x6a5fcc9bU, 0x547e4662U,\n    0xf68d13c2U, 0x90d8b8e8U, 0x2e39f75eU, 0x82c3aff5U,\n    0x9f5d80beU, 0x69d0937cU, 0x6fd52da9U, 0xcf2512b3U,\n    0xc8ac993bU, 0x10187da7U, 0xe89c636eU, 0xdb3bbb7bU,\n    0xcd267809U, 0x6e5918f4U, 0xec9ab701U, 0x834f9aa8U,\n    0xe6956e65U, 0xaaffe67eU, 0x21bccf08U, 0xef15e8e6U,\n    0xbae79bd9U, 0x4a6f36ceU, 0xea9f09d4U, 0x29b07cd6U,\n    0x31a4b2afU, 0x2a3f2331U, 0xc6a59430U, 0x35a266c0U,\n    0x744ebc37U, 0xfc82caa6U, 0xe090d0b0U, 0x33a7d815U,\n    0xf104984aU, 0x41ecdaf7U, 0x7fcd500eU, 0x1791f62fU,\n    0x764dd68dU, 0x43efb04dU, 0xccaa4d54U, 0xe49604dfU,\n    0x9ed1b5e3U, 0x4c6a881bU, 0xc12c1fb8U, 0x4665517fU,\n    0x9d5eea04U, 0x018c355dU, 0xfa877473U, 0xfb0b412eU,\n    0xb3671d5aU, 0x92dbd252U, 0xe9105633U, 0x6dd64713U,\n    0x9ad7618cU, 0x37a10c7aU, 0x59f8148eU, 0xeb133c89U,\n    0xcea927eeU, 0xb761c935U, 0xe11ce5edU, 0x7a47b13cU,\n    0x9cd2df59U, 0x55f2733fU, 0x1814ce79U, 0x73c737bfU,\n    0x53f7cdeaU, 0x5ffdaa5bU, 0xdf3d6f14U, 0x7844db86U,\n    0xcaaff381U, 0xb968c43eU, 0x3824342cU, 0xc2a3405fU,\n    0x161dc372U, 0xbce2250cU, 0x283c498bU, 0xff0d9541U,\n    0x39a80171U, 0x080cb3deU, 0xd8b4e49cU, 0x6456c190U,\n    0x7bcb8461U, 0xd532b670U, 0x486c5c74U, 0xd0b85742U,\n};\n#ifndef AES_SMALL_TABLES\nstatic const u32 Td1[256] = {\n    0x5051f4a7U, 0x537e4165U, 0xc31a17a4U, 0x963a275eU,\n    0xcb3bab6bU, 0xf11f9d45U, 0xabacfa58U, 0x934be303U,\n    0x552030faU, 0xf6ad766dU, 0x9188cc76U, 0x25f5024cU,\n    0xfc4fe5d7U, 0xd7c52acbU, 0x80263544U, 0x8fb562a3U,\n    0x49deb15aU, 0x6725ba1bU, 0x9845ea0eU, 0xe15dfec0U,\n    0x02c32f75U, 0x12814cf0U, 0xa38d4697U, 0xc66bd3f9U,\n    0xe7038f5fU, 0x9515929cU, 0xebbf6d7aU, 0xda955259U,\n    0x2dd4be83U, 0xd3587421U, 0x2949e069U, 0x448ec9c8U,\n    0x6a75c289U, 0x78f48e79U, 0x6b99583eU, 0xdd27b971U,\n    0xb6bee14fU, 0x17f088adU, 0x66c920acU, 0xb47dce3aU,\n    0x1863df4aU, 0x82e51a31U, 0x60975133U, 0x4562537fU,\n    0xe0b16477U, 0x84bb6baeU, 0x1cfe81a0U, 0x94f9082bU,\n    0x58704868U, 0x198f45fdU, 0x8794de6cU, 0xb7527bf8U,\n    0x23ab73d3U, 0xe2724b02U, 0x57e31f8fU, 0x2a6655abU,\n    0x07b2eb28U, 0x032fb5c2U, 0x9a86c57bU, 0xa5d33708U,\n    0xf2302887U, 0xb223bfa5U, 0xba02036aU, 0x5ced1682U,\n    0x2b8acf1cU, 0x92a779b4U, 0xf0f307f2U, 0xa14e69e2U,\n    0xcd65daf4U, 0xd50605beU, 0x1fd13462U, 0x8ac4a6feU,\n    0x9d342e53U, 0xa0a2f355U, 0x32058ae1U, 0x75a4f6ebU,\n    0x390b83ecU, 0xaa4060efU, 0x065e719fU, 0x51bd6e10U,\n    0xf93e218aU, 0x3d96dd06U, 0xaedd3e05U, 0x464de6bdU,\n    0xb591548dU, 0x0571c45dU, 0x6f0406d4U, 0xff605015U,\n    0x241998fbU, 0x97d6bde9U, 0xcc894043U, 0x7767d99eU,\n    0xbdb0e842U, 0x8807898bU, 0x38e7195bU, 0xdb79c8eeU,\n    0x47a17c0aU, 0xe97c420fU, 0xc9f8841eU, 0x00000000U,\n    0x83098086U, 0x48322bedU, 0xac1e1170U, 0x4e6c5a72U,\n    0xfbfd0effU, 0x560f8538U, 0x1e3daed5U, 0x27362d39U,\n    0x640a0fd9U, 0x21685ca6U, 0xd19b5b54U, 0x3a24362eU,\n    0xb10c0a67U, 0x0f9357e7U, 0xd2b4ee96U, 0x9e1b9b91U,\n    0x4f80c0c5U, 0xa261dc20U, 0x695a774bU, 0x161c121aU,\n    0x0ae293baU, 0xe5c0a02aU, 0x433c22e0U, 0x1d121b17U,\n    0x0b0e090dU, 0xadf28bc7U, 0xb92db6a8U, 0xc8141ea9U,\n    0x8557f119U, 0x4caf7507U, 0xbbee99ddU, 0xfda37f60U,\n    0x9ff70126U, 0xbc5c72f5U, 0xc544663bU, 0x345bfb7eU,\n    0x768b4329U, 0xdccb23c6U, 0x68b6edfcU, 0x63b8e4f1U,\n    0xcad731dcU, 0x10426385U, 0x40139722U, 0x2084c611U,\n    0x7d854a24U, 0xf8d2bb3dU, 0x11aef932U, 0x6dc729a1U,\n    0x4b1d9e2fU, 0xf3dcb230U, 0xec0d8652U, 0xd077c1e3U,\n    0x6c2bb316U, 0x99a970b9U, 0xfa119448U, 0x2247e964U,\n    0xc4a8fc8cU, 0x1aa0f03fU, 0xd8567d2cU, 0xef223390U,\n    0xc787494eU, 0xc1d938d1U, 0xfe8ccaa2U, 0x3698d40bU,\n    0xcfa6f581U, 0x28a57adeU, 0x26dab78eU, 0xa43fadbfU,\n    0xe42c3a9dU, 0x0d507892U, 0x9b6a5fccU, 0x62547e46U,\n    0xc2f68d13U, 0xe890d8b8U, 0x5e2e39f7U, 0xf582c3afU,\n    0xbe9f5d80U, 0x7c69d093U, 0xa96fd52dU, 0xb3cf2512U,\n    0x3bc8ac99U, 0xa710187dU, 0x6ee89c63U, 0x7bdb3bbbU,\n    0x09cd2678U, 0xf46e5918U, 0x01ec9ab7U, 0xa8834f9aU,\n    0x65e6956eU, 0x7eaaffe6U, 0x0821bccfU, 0xe6ef15e8U,\n    0xd9bae79bU, 0xce4a6f36U, 0xd4ea9f09U, 0xd629b07cU,\n    0xaf31a4b2U, 0x312a3f23U, 0x30c6a594U, 0xc035a266U,\n    0x37744ebcU, 0xa6fc82caU, 0xb0e090d0U, 0x1533a7d8U,\n    0x4af10498U, 0xf741ecdaU, 0x0e7fcd50U, 0x2f1791f6U,\n    0x8d764dd6U, 0x4d43efb0U, 0x54ccaa4dU, 0xdfe49604U,\n    0xe39ed1b5U, 0x1b4c6a88U, 0xb8c12c1fU, 0x7f466551U,\n    0x049d5eeaU, 0x5d018c35U, 0x73fa8774U, 0x2efb0b41U,\n    0x5ab3671dU, 0x5292dbd2U, 0x33e91056U, 0x136dd647U,\n    0x8c9ad761U, 0x7a37a10cU, 0x8e59f814U, 0x89eb133cU,\n    0xeecea927U, 0x35b761c9U, 0xede11ce5U, 0x3c7a47b1U,\n    0x599cd2dfU, 0x3f55f273U, 0x791814ceU, 0xbf73c737U,\n    0xea53f7cdU, 0x5b5ffdaaU, 0x14df3d6fU, 0x867844dbU,\n    0x81caaff3U, 0x3eb968c4U, 0x2c382434U, 0x5fc2a340U,\n    0x72161dc3U, 0x0cbce225U, 0x8b283c49U, 0x41ff0d95U,\n    0x7139a801U, 0xde080cb3U, 0x9cd8b4e4U, 0x906456c1U,\n    0x617bcb84U, 0x70d532b6U, 0x74486c5cU, 0x42d0b857U,\n};\nstatic const u32 Td2[256] = {\n    0xa75051f4U, 0x65537e41U, 0xa4c31a17U, 0x5e963a27U,\n    0x6bcb3babU, 0x45f11f9dU, 0x58abacfaU, 0x03934be3U,\n    0xfa552030U, 0x6df6ad76U, 0x769188ccU, 0x4c25f502U,\n    0xd7fc4fe5U, 0xcbd7c52aU, 0x44802635U, 0xa38fb562U,\n    0x5a49deb1U, 0x1b6725baU, 0x0e9845eaU, 0xc0e15dfeU,\n    0x7502c32fU, 0xf012814cU, 0x97a38d46U, 0xf9c66bd3U,\n    0x5fe7038fU, 0x9c951592U, 0x7aebbf6dU, 0x59da9552U,\n    0x832dd4beU, 0x21d35874U, 0x692949e0U, 0xc8448ec9U,\n    0x896a75c2U, 0x7978f48eU, 0x3e6b9958U, 0x71dd27b9U,\n    0x4fb6bee1U, 0xad17f088U, 0xac66c920U, 0x3ab47dceU,\n    0x4a1863dfU, 0x3182e51aU, 0x33609751U, 0x7f456253U,\n    0x77e0b164U, 0xae84bb6bU, 0xa01cfe81U, 0x2b94f908U,\n    0x68587048U, 0xfd198f45U, 0x6c8794deU, 0xf8b7527bU,\n    0xd323ab73U, 0x02e2724bU, 0x8f57e31fU, 0xab2a6655U,\n    0x2807b2ebU, 0xc2032fb5U, 0x7b9a86c5U, 0x08a5d337U,\n    0x87f23028U, 0xa5b223bfU, 0x6aba0203U, 0x825ced16U,\n    0x1c2b8acfU, 0xb492a779U, 0xf2f0f307U, 0xe2a14e69U,\n    0xf4cd65daU, 0xbed50605U, 0x621fd134U, 0xfe8ac4a6U,\n    0x539d342eU, 0x55a0a2f3U, 0xe132058aU, 0xeb75a4f6U,\n    0xec390b83U, 0xefaa4060U, 0x9f065e71U, 0x1051bd6eU,\n\n    0x8af93e21U, 0x063d96ddU, 0x05aedd3eU, 0xbd464de6U,\n    0x8db59154U, 0x5d0571c4U, 0xd46f0406U, 0x15ff6050U,\n    0xfb241998U, 0xe997d6bdU, 0x43cc8940U, 0x9e7767d9U,\n    0x42bdb0e8U, 0x8b880789U, 0x5b38e719U, 0xeedb79c8U,\n    0x0a47a17cU, 0x0fe97c42U, 0x1ec9f884U, 0x00000000U,\n    0x86830980U, 0xed48322bU, 0x70ac1e11U, 0x724e6c5aU,\n    0xfffbfd0eU, 0x38560f85U, 0xd51e3daeU, 0x3927362dU,\n    0xd9640a0fU, 0xa621685cU, 0x54d19b5bU, 0x2e3a2436U,\n    0x67b10c0aU, 0xe70f9357U, 0x96d2b4eeU, 0x919e1b9bU,\n    0xc54f80c0U, 0x20a261dcU, 0x4b695a77U, 0x1a161c12U,\n    0xba0ae293U, 0x2ae5c0a0U, 0xe0433c22U, 0x171d121bU,\n    0x0d0b0e09U, 0xc7adf28bU, 0xa8b92db6U, 0xa9c8141eU,\n    0x198557f1U, 0x074caf75U, 0xddbbee99U, 0x60fda37fU,\n    0x269ff701U, 0xf5bc5c72U, 0x3bc54466U, 0x7e345bfbU,\n    0x29768b43U, 0xc6dccb23U, 0xfc68b6edU, 0xf163b8e4U,\n    0xdccad731U, 0x85104263U, 0x22401397U, 0x112084c6U,\n    0x247d854aU, 0x3df8d2bbU, 0x3211aef9U, 0xa16dc729U,\n    0x2f4b1d9eU, 0x30f3dcb2U, 0x52ec0d86U, 0xe3d077c1U,\n    0x166c2bb3U, 0xb999a970U, 0x48fa1194U, 0x642247e9U,\n    0x8cc4a8fcU, 0x3f1aa0f0U, 0x2cd8567dU, 0x90ef2233U,\n    0x4ec78749U, 0xd1c1d938U, 0xa2fe8ccaU, 0x0b3698d4U,\n    0x81cfa6f5U, 0xde28a57aU, 0x8e26dab7U, 0xbfa43fadU,\n    0x9de42c3aU, 0x920d5078U, 0xcc9b6a5fU, 0x4662547eU,\n    0x13c2f68dU, 0xb8e890d8U, 0xf75e2e39U, 0xaff582c3U,\n    0x80be9f5dU, 0x937c69d0U, 0x2da96fd5U, 0x12b3cf25U,\n    0x993bc8acU, 0x7da71018U, 0x636ee89cU, 0xbb7bdb3bU,\n    0x7809cd26U, 0x18f46e59U, 0xb701ec9aU, 0x9aa8834fU,\n    0x6e65e695U, 0xe67eaaffU, 0xcf0821bcU, 0xe8e6ef15U,\n    0x9bd9bae7U, 0x36ce4a6fU, 0x09d4ea9fU, 0x7cd629b0U,\n    0xb2af31a4U, 0x23312a3fU, 0x9430c6a5U, 0x66c035a2U,\n    0xbc37744eU, 0xcaa6fc82U, 0xd0b0e090U, 0xd81533a7U,\n    0x984af104U, 0xdaf741ecU, 0x500e7fcdU, 0xf62f1791U,\n    0xd68d764dU, 0xb04d43efU, 0x4d54ccaaU, 0x04dfe496U,\n    0xb5e39ed1U, 0x881b4c6aU, 0x1fb8c12cU, 0x517f4665U,\n    0xea049d5eU, 0x355d018cU, 0x7473fa87U, 0x412efb0bU,\n    0x1d5ab367U, 0xd25292dbU, 0x5633e910U, 0x47136dd6U,\n    0x618c9ad7U, 0x0c7a37a1U, 0x148e59f8U, 0x3c89eb13U,\n    0x27eecea9U, 0xc935b761U, 0xe5ede11cU, 0xb13c7a47U,\n    0xdf599cd2U, 0x733f55f2U, 0xce791814U, 0x37bf73c7U,\n    0xcdea53f7U, 0xaa5b5ffdU, 0x6f14df3dU, 0xdb867844U,\n    0xf381caafU, 0xc43eb968U, 0x342c3824U, 0x405fc2a3U,\n    0xc372161dU, 0x250cbce2U, 0x498b283cU, 0x9541ff0dU,\n    0x017139a8U, 0xb3de080cU, 0xe49cd8b4U, 0xc1906456U,\n    0x84617bcbU, 0xb670d532U, 0x5c74486cU, 0x5742d0b8U,\n};\nstatic const u32 Td3[256] = {\n    0xf4a75051U, 0x4165537eU, 0x17a4c31aU, 0x275e963aU,\n    0xab6bcb3bU, 0x9d45f11fU, 0xfa58abacU, 0xe303934bU,\n    0x30fa5520U, 0x766df6adU, 0xcc769188U, 0x024c25f5U,\n    0xe5d7fc4fU, 0x2acbd7c5U, 0x35448026U, 0x62a38fb5U,\n    0xb15a49deU, 0xba1b6725U, 0xea0e9845U, 0xfec0e15dU,\n    0x2f7502c3U, 0x4cf01281U, 0x4697a38dU, 0xd3f9c66bU,\n    0x8f5fe703U, 0x929c9515U, 0x6d7aebbfU, 0x5259da95U,\n    0xbe832dd4U, 0x7421d358U, 0xe0692949U, 0xc9c8448eU,\n    0xc2896a75U, 0x8e7978f4U, 0x583e6b99U, 0xb971dd27U,\n    0xe14fb6beU, 0x88ad17f0U, 0x20ac66c9U, 0xce3ab47dU,\n    0xdf4a1863U, 0x1a3182e5U, 0x51336097U, 0x537f4562U,\n    0x6477e0b1U, 0x6bae84bbU, 0x81a01cfeU, 0x082b94f9U,\n    0x48685870U, 0x45fd198fU, 0xde6c8794U, 0x7bf8b752U,\n    0x73d323abU, 0x4b02e272U, 0x1f8f57e3U, 0x55ab2a66U,\n    0xeb2807b2U, 0xb5c2032fU, 0xc57b9a86U, 0x3708a5d3U,\n    0x2887f230U, 0xbfa5b223U, 0x036aba02U, 0x16825cedU,\n    0xcf1c2b8aU, 0x79b492a7U, 0x07f2f0f3U, 0x69e2a14eU,\n    0xdaf4cd65U, 0x05bed506U, 0x34621fd1U, 0xa6fe8ac4U,\n    0x2e539d34U, 0xf355a0a2U, 0x8ae13205U, 0xf6eb75a4U,\n    0x83ec390bU, 0x60efaa40U, 0x719f065eU, 0x6e1051bdU,\n    0x218af93eU, 0xdd063d96U, 0x3e05aeddU, 0xe6bd464dU,\n    0x548db591U, 0xc45d0571U, 0x06d46f04U, 0x5015ff60U,\n    0x98fb2419U, 0xbde997d6U, 0x4043cc89U, 0xd99e7767U,\n    0xe842bdb0U, 0x898b8807U, 0x195b38e7U, 0xc8eedb79U,\n    0x7c0a47a1U, 0x420fe97cU, 0x841ec9f8U, 0x00000000U,\n    0x80868309U, 0x2bed4832U, 0x1170ac1eU, 0x5a724e6cU,\n    0x0efffbfdU, 0x8538560fU, 0xaed51e3dU, 0x2d392736U,\n    0x0fd9640aU, 0x5ca62168U, 0x5b54d19bU, 0x362e3a24U,\n    0x0a67b10cU, 0x57e70f93U, 0xee96d2b4U, 0x9b919e1bU,\n    0xc0c54f80U, 0xdc20a261U, 0x774b695aU, 0x121a161cU,\n    0x93ba0ae2U, 0xa02ae5c0U, 0x22e0433cU, 0x1b171d12U,\n    0x090d0b0eU, 0x8bc7adf2U, 0xb6a8b92dU, 0x1ea9c814U,\n    0xf1198557U, 0x75074cafU, 0x99ddbbeeU, 0x7f60fda3U,\n    0x01269ff7U, 0x72f5bc5cU, 0x663bc544U, 0xfb7e345bU,\n    0x4329768bU, 0x23c6dccbU, 0xedfc68b6U, 0xe4f163b8U,\n    0x31dccad7U, 0x63851042U, 0x97224013U, 0xc6112084U,\n    0x4a247d85U, 0xbb3df8d2U, 0xf93211aeU, 0x29a16dc7U,\n    0x9e2f4b1dU, 0xb230f3dcU, 0x8652ec0dU, 0xc1e3d077U,\n    0xb3166c2bU, 0x70b999a9U, 0x9448fa11U, 0xe9642247U,\n    0xfc8cc4a8U, 0xf03f1aa0U, 0x7d2cd856U, 0x3390ef22U,\n    0x494ec787U, 0x38d1c1d9U, 0xcaa2fe8cU, 0xd40b3698U,\n    0xf581cfa6U, 0x7ade28a5U, 0xb78e26daU, 0xadbfa43fU,\n    0x3a9de42cU, 0x78920d50U, 0x5fcc9b6aU, 0x7e466254U,\n    0x8d13c2f6U, 0xd8b8e890U, 0x39f75e2eU, 0xc3aff582U,\n    0x5d80be9fU, 0xd0937c69U, 0xd52da96fU, 0x2512b3cfU,\n    0xac993bc8U, 0x187da710U, 0x9c636ee8U, 0x3bbb7bdbU,\n    0x267809cdU, 0x5918f46eU, 0x9ab701ecU, 0x4f9aa883U,\n    0x956e65e6U, 0xffe67eaaU, 0xbccf0821U, 0x15e8e6efU,\n    0xe79bd9baU, 0x6f36ce4aU, 0x9f09d4eaU, 0xb07cd629U,\n    0xa4b2af31U, 0x3f23312aU, 0xa59430c6U, 0xa266c035U,\n    0x4ebc3774U, 0x82caa6fcU, 0x90d0b0e0U, 0xa7d81533U,\n    0x04984af1U, 0xecdaf741U, 0xcd500e7fU, 0x91f62f17U,\n    0x4dd68d76U, 0xefb04d43U, 0xaa4d54ccU, 0x9604dfe4U,\n    0xd1b5e39eU, 0x6a881b4cU, 0x2c1fb8c1U, 0x65517f46U,\n    0x5eea049dU, 0x8c355d01U, 0x877473faU, 0x0b412efbU,\n    0x671d5ab3U, 0xdbd25292U, 0x105633e9U, 0xd647136dU,\n    0xd7618c9aU, 0xa10c7a37U, 0xf8148e59U, 0x133c89ebU,\n    0xa927eeceU, 0x61c935b7U, 0x1ce5ede1U, 0x47b13c7aU,\n    0xd2df599cU, 0xf2733f55U, 0x14ce7918U, 0xc737bf73U,\n    0xf7cdea53U, 0xfdaa5b5fU, 0x3d6f14dfU, 0x44db8678U,\n    0xaff381caU, 0x68c43eb9U, 0x24342c38U, 0xa3405fc2U,\n    0x1dc37216U, 0xe2250cbcU, 0x3c498b28U, 0x0d9541ffU,\n    0xa8017139U, 0x0cb3de08U, 0xb4e49cd8U, 0x56c19064U,\n    0xcb84617bU, 0x32b670d5U, 0x6c5c7448U, 0xb85742d0U,\n};\nstatic const u32 Td4[256] = {\n    0x52525252U, 0x09090909U, 0x6a6a6a6aU, 0xd5d5d5d5U,\n    0x30303030U, 0x36363636U, 0xa5a5a5a5U, 0x38383838U,\n    0xbfbfbfbfU, 0x40404040U, 0xa3a3a3a3U, 0x9e9e9e9eU,\n    0x81818181U, 0xf3f3f3f3U, 0xd7d7d7d7U, 0xfbfbfbfbU,\n    0x7c7c7c7cU, 0xe3e3e3e3U, 0x39393939U, 0x82828282U,\n    0x9b9b9b9bU, 0x2f2f2f2fU, 0xffffffffU, 0x87878787U,\n    0x34343434U, 0x8e8e8e8eU, 0x43434343U, 0x44444444U,\n    0xc4c4c4c4U, 0xdedededeU, 0xe9e9e9e9U, 0xcbcbcbcbU,\n    0x54545454U, 0x7b7b7b7bU, 0x94949494U, 0x32323232U,\n    0xa6a6a6a6U, 0xc2c2c2c2U, 0x23232323U, 0x3d3d3d3dU,\n    0xeeeeeeeeU, 0x4c4c4c4cU, 0x95959595U, 0x0b0b0b0bU,\n    0x42424242U, 0xfafafafaU, 0xc3c3c3c3U, 0x4e4e4e4eU,\n    0x08080808U, 0x2e2e2e2eU, 0xa1a1a1a1U, 0x66666666U,\n    0x28282828U, 0xd9d9d9d9U, 0x24242424U, 0xb2b2b2b2U,\n    0x76767676U, 0x5b5b5b5bU, 0xa2a2a2a2U, 0x49494949U,\n    0x6d6d6d6dU, 0x8b8b8b8bU, 0xd1d1d1d1U, 0x25252525U,\n    0x72727272U, 0xf8f8f8f8U, 0xf6f6f6f6U, 0x64646464U,\n    0x86868686U, 0x68686868U, 0x98989898U, 0x16161616U,\n    0xd4d4d4d4U, 0xa4a4a4a4U, 0x5c5c5c5cU, 0xccccccccU,\n    0x5d5d5d5dU, 0x65656565U, 0xb6b6b6b6U, 0x92929292U,\n    0x6c6c6c6cU, 0x70707070U, 0x48484848U, 0x50505050U,\n    0xfdfdfdfdU, 0xededededU, 0xb9b9b9b9U, 0xdadadadaU,\n    0x5e5e5e5eU, 0x15151515U, 0x46464646U, 0x57575757U,\n    0xa7a7a7a7U, 0x8d8d8d8dU, 0x9d9d9d9dU, 0x84848484U,\n    0x90909090U, 0xd8d8d8d8U, 0xababababU, 0x00000000U,\n    0x8c8c8c8cU, 0xbcbcbcbcU, 0xd3d3d3d3U, 0x0a0a0a0aU,\n    0xf7f7f7f7U, 0xe4e4e4e4U, 0x58585858U, 0x05050505U,\n    0xb8b8b8b8U, 0xb3b3b3b3U, 0x45454545U, 0x06060606U,\n    0xd0d0d0d0U, 0x2c2c2c2cU, 0x1e1e1e1eU, 0x8f8f8f8fU,\n    0xcacacacaU, 0x3f3f3f3fU, 0x0f0f0f0fU, 0x02020202U,\n    0xc1c1c1c1U, 0xafafafafU, 0xbdbdbdbdU, 0x03030303U,\n    0x01010101U, 0x13131313U, 0x8a8a8a8aU, 0x6b6b6b6bU,\n    0x3a3a3a3aU, 0x91919191U, 0x11111111U, 0x41414141U,\n    0x4f4f4f4fU, 0x67676767U, 0xdcdcdcdcU, 0xeaeaeaeaU,\n    0x97979797U, 0xf2f2f2f2U, 0xcfcfcfcfU, 0xcecececeU,\n    0xf0f0f0f0U, 0xb4b4b4b4U, 0xe6e6e6e6U, 0x73737373U,\n    0x96969696U, 0xacacacacU, 0x74747474U, 0x22222222U,\n    0xe7e7e7e7U, 0xadadadadU, 0x35353535U, 0x85858585U,\n    0xe2e2e2e2U, 0xf9f9f9f9U, 0x37373737U, 0xe8e8e8e8U,\n    0x1c1c1c1cU, 0x75757575U, 0xdfdfdfdfU, 0x6e6e6e6eU,\n    0x47474747U, 0xf1f1f1f1U, 0x1a1a1a1aU, 0x71717171U,\n    0x1d1d1d1dU, 0x29292929U, 0xc5c5c5c5U, 0x89898989U,\n    0x6f6f6f6fU, 0xb7b7b7b7U, 0x62626262U, 0x0e0e0e0eU,\n    0xaaaaaaaaU, 0x18181818U, 0xbebebebeU, 0x1b1b1b1bU,\n    0xfcfcfcfcU, 0x56565656U, 0x3e3e3e3eU, 0x4b4b4b4bU,\n    0xc6c6c6c6U, 0xd2d2d2d2U, 0x79797979U, 0x20202020U,\n    0x9a9a9a9aU, 0xdbdbdbdbU, 0xc0c0c0c0U, 0xfefefefeU,\n    0x78787878U, 0xcdcdcdcdU, 0x5a5a5a5aU, 0xf4f4f4f4U,\n    0x1f1f1f1fU, 0xddddddddU, 0xa8a8a8a8U, 0x33333333U,\n    0x88888888U, 0x07070707U, 0xc7c7c7c7U, 0x31313131U,\n    0xb1b1b1b1U, 0x12121212U, 0x10101010U, 0x59595959U,\n    0x27272727U, 0x80808080U, 0xececececU, 0x5f5f5f5fU,\n    0x60606060U, 0x51515151U, 0x7f7f7f7fU, 0xa9a9a9a9U,\n    0x19191919U, 0xb5b5b5b5U, 0x4a4a4a4aU, 0x0d0d0d0dU,\n    0x2d2d2d2dU, 0xe5e5e5e5U, 0x7a7a7a7aU, 0x9f9f9f9fU,\n    0x93939393U, 0xc9c9c9c9U, 0x9c9c9c9cU, 0xefefefefU,\n    0xa0a0a0a0U, 0xe0e0e0e0U, 0x3b3b3b3bU, 0x4d4d4d4dU,\n    0xaeaeaeaeU, 0x2a2a2a2aU, 0xf5f5f5f5U, 0xb0b0b0b0U,\n    0xc8c8c8c8U, 0xebebebebU, 0xbbbbbbbbU, 0x3c3c3c3cU,\n    0x83838383U, 0x53535353U, 0x99999999U, 0x61616161U,\n    0x17171717U, 0x2b2b2b2bU, 0x04040404U, 0x7e7e7e7eU,\n    0xbabababaU, 0x77777777U, 0xd6d6d6d6U, 0x26262626U,\n    0xe1e1e1e1U, 0x69696969U, 0x14141414U, 0x63636363U,\n    0x55555555U, 0x21212121U, 0x0c0c0c0cU, 0x7d7d7d7dU,\n};\nstatic const u32 rcon[] = {\n\t0x01000000, 0x02000000, 0x04000000, 0x08000000,\n\t0x10000000, 0x20000000, 0x40000000, 0x80000000,\n\t0x1B000000, 0x36000000, /* for 128-bit blocks, Rijndael never uses more than 10 rcon values */\n};\n#else /* AES_SMALL_TABLES */\nstatic const u8 Td4s[256] = {\n    0x52U, 0x09U, 0x6aU, 0xd5U, 0x30U, 0x36U, 0xa5U, 0x38U,\n    0xbfU, 0x40U, 0xa3U, 0x9eU, 0x81U, 0xf3U, 0xd7U, 0xfbU,\n    0x7cU, 0xe3U, 0x39U, 0x82U, 0x9bU, 0x2fU, 0xffU, 0x87U,\n    0x34U, 0x8eU, 0x43U, 0x44U, 0xc4U, 0xdeU, 0xe9U, 0xcbU,\n    0x54U, 0x7bU, 0x94U, 0x32U, 0xa6U, 0xc2U, 0x23U, 0x3dU,\n    0xeeU, 0x4cU, 0x95U, 0x0bU, 0x42U, 0xfaU, 0xc3U, 0x4eU,\n    0x08U, 0x2eU, 0xa1U, 0x66U, 0x28U, 0xd9U, 0x24U, 0xb2U,\n    0x76U, 0x5bU, 0xa2U, 0x49U, 0x6dU, 0x8bU, 0xd1U, 0x25U,\n    0x72U, 0xf8U, 0xf6U, 0x64U, 0x86U, 0x68U, 0x98U, 0x16U,\n    0xd4U, 0xa4U, 0x5cU, 0xccU, 0x5dU, 0x65U, 0xb6U, 0x92U,\n    0x6cU, 0x70U, 0x48U, 0x50U, 0xfdU, 0xedU, 0xb9U, 0xdaU,\n    0x5eU, 0x15U, 0x46U, 0x57U, 0xa7U, 0x8dU, 0x9dU, 0x84U,\n    0x90U, 0xd8U, 0xabU, 0x00U, 0x8cU, 0xbcU, 0xd3U, 0x0aU,\n    0xf7U, 0xe4U, 0x58U, 0x05U, 0xb8U, 0xb3U, 0x45U, 0x06U,\n    0xd0U, 0x2cU, 0x1eU, 0x8fU, 0xcaU, 0x3fU, 0x0fU, 0x02U,\n    0xc1U, 0xafU, 0xbdU, 0x03U, 0x01U, 0x13U, 0x8aU, 0x6bU,\n    0x3aU, 0x91U, 0x11U, 0x41U, 0x4fU, 0x67U, 0xdcU, 0xeaU,\n    0x97U, 0xf2U, 0xcfU, 0xceU, 0xf0U, 0xb4U, 0xe6U, 0x73U,\n    0x96U, 0xacU, 0x74U, 0x22U, 0xe7U, 0xadU, 0x35U, 0x85U,\n    0xe2U, 0xf9U, 0x37U, 0xe8U, 0x1cU, 0x75U, 0xdfU, 0x6eU,\n    0x47U, 0xf1U, 0x1aU, 0x71U, 0x1dU, 0x29U, 0xc5U, 0x89U,\n    0x6fU, 0xb7U, 0x62U, 0x0eU, 0xaaU, 0x18U, 0xbeU, 0x1bU,\n    0xfcU, 0x56U, 0x3eU, 0x4bU, 0xc6U, 0xd2U, 0x79U, 0x20U,\n    0x9aU, 0xdbU, 0xc0U, 0xfeU, 0x78U, 0xcdU, 0x5aU, 0xf4U,\n    0x1fU, 0xddU, 0xa8U, 0x33U, 0x88U, 0x07U, 0xc7U, 0x31U,\n    0xb1U, 0x12U, 0x10U, 0x59U, 0x27U, 0x80U, 0xecU, 0x5fU,\n    0x60U, 0x51U, 0x7fU, 0xa9U, 0x19U, 0xb5U, 0x4aU, 0x0dU,\n    0x2dU, 0xe5U, 0x7aU, 0x9fU, 0x93U, 0xc9U, 0x9cU, 0xefU,\n    0xa0U, 0xe0U, 0x3bU, 0x4dU, 0xaeU, 0x2aU, 0xf5U, 0xb0U,\n    0xc8U, 0xebU, 0xbbU, 0x3cU, 0x83U, 0x53U, 0x99U, 0x61U,\n    0x17U, 0x2bU, 0x04U, 0x7eU, 0xbaU, 0x77U, 0xd6U, 0x26U,\n    0xe1U, 0x69U, 0x14U, 0x63U, 0x55U, 0x21U, 0x0cU, 0x7dU,\n};\nstatic const u8 rcons[] = {\n\t0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0x1B, 0x36\n\t/* for 128-bit blocks, Rijndael never uses more than 10 rcon values */\n};\n#endif /* AES_SMALL_TABLES */\n\n\n#ifndef AES_SMALL_TABLES\n\n#define RCON(i) rcon[(i)]\n\n#define TE0(i) Te0[((i) >> 24) & 0xff]\n#define TE1(i) Te1[((i) >> 16) & 0xff]\n#define TE2(i) Te2[((i) >> 8) & 0xff]\n#define TE3(i) Te3[(i) & 0xff]\n#define TE41(i) (Te4[((i) >> 24) & 0xff] & 0xff000000)\n#define TE42(i) (Te4[((i) >> 16) & 0xff] & 0x00ff0000)\n#define TE43(i) (Te4[((i) >> 8) & 0xff] & 0x0000ff00)\n#define TE44(i) (Te4[(i) & 0xff] & 0x000000ff)\n#define TE421(i) (Te4[((i) >> 16) & 0xff] & 0xff000000)\n#define TE432(i) (Te4[((i) >> 8) & 0xff] & 0x00ff0000)\n#define TE443(i) (Te4[(i) & 0xff] & 0x0000ff00)\n#define TE414(i) (Te4[((i) >> 24) & 0xff] & 0x000000ff)\n#define TE4(i) (Te4[(i)] & 0x000000ff)\n\n#define TD0(i) Td0[((i) >> 24) & 0xff]\n#define TD1(i) Td1[((i) >> 16) & 0xff]\n#define TD2(i) Td2[((i) >> 8) & 0xff]\n#define TD3(i) Td3[(i) & 0xff]\n#define TD41(i) (Td4[((i) >> 24) & 0xff] & 0xff000000)\n#define TD42(i) (Td4[((i) >> 16) & 0xff] & 0x00ff0000)\n#define TD43(i) (Td4[((i) >> 8) & 0xff] & 0x0000ff00)\n#define TD44(i) (Td4[(i) & 0xff] & 0x000000ff)\n#define TD0_(i) Td0[(i) & 0xff]\n#define TD1_(i) Td1[(i) & 0xff]\n#define TD2_(i) Td2[(i) & 0xff]\n#define TD3_(i) Td3[(i) & 0xff]\n\n#else /* AES_SMALL_TABLES */\n\n#define RCON(i) (rcons[(i)] << 24)\n\nstatic inline u32 rotr(u32 val, int bits)\n{\n\treturn (val >> bits) | (val << (32 - bits));\n}\n\n#define TE0(i) Te0[((i) >> 24) & 0xff]\n#define TE1(i) rotr(Te0[((i) >> 16) & 0xff], 8)\n#define TE2(i) rotr(Te0[((i) >> 8) & 0xff], 16)\n#define TE3(i) rotr(Te0[(i) & 0xff], 24)\n#define TE41(i) ((Te0[((i) >> 24) & 0xff] << 8) & 0xff000000)\n#define TE42(i) (Te0[((i) >> 16) & 0xff] & 0x00ff0000)\n#define TE43(i) (Te0[((i) >> 8) & 0xff] & 0x0000ff00)\n#define TE44(i) ((Te0[(i) & 0xff] >> 8) & 0x000000ff)\n#define TE421(i) ((Te0[((i) >> 16) & 0xff] << 8) & 0xff000000)\n#define TE432(i) (Te0[((i) >> 8) & 0xff] & 0x00ff0000)\n#define TE443(i) (Te0[(i) & 0xff] & 0x0000ff00)\n#define TE414(i) ((Te0[((i) >> 24) & 0xff] >> 8) & 0x000000ff)\n#define TE4(i) ((Te0[(i)] >> 8) & 0x000000ff)\n\n#define TD0(i) Td0[((i) >> 24) & 0xff]\n#define TD1(i) rotr(Td0[((i) >> 16) & 0xff], 8)\n#define TD2(i) rotr(Td0[((i) >> 8) & 0xff], 16)\n#define TD3(i) rotr(Td0[(i) & 0xff], 24)\n#define TD41(i) (Td4s[((i) >> 24) & 0xff] << 24)\n#define TD42(i) (Td4s[((i) >> 16) & 0xff] << 16)\n#define TD43(i) (Td4s[((i) >> 8) & 0xff] << 8)\n#define TD44(i) (Td4s[(i) & 0xff])\n#define TD0_(i) Td0[(i) & 0xff]\n#define TD1_(i) rotr(Td0[(i) & 0xff], 8)\n#define TD2_(i) rotr(Td0[(i) & 0xff], 16)\n#define TD3_(i) rotr(Td0[(i) & 0xff], 24)\n\n#endif /* AES_SMALL_TABLES */\n\n#define SWAP(x) (_lrotl(x, 8) & 0x00ff00ff | _lrotr(x, 8) & 0xff00ff00)\n\n#ifdef _MSC_VER\n#define GETU32(p) SWAP(*((u32 *)(p)))\n#define PUTU32(ct, st) { *((u32 *)(ct)) = SWAP((st)); }\n#else\n#define GETU32(pt) (((u32)(pt)[0] << 24) ^ ((u32)(pt)[1] << 16) ^ \\\n((u32)(pt)[2] <<  8) ^ ((u32)(pt)[3]))\n#define PUTU32(ct, st) { \\\n(ct)[0] = (u8)((st) >> 24); (ct)[1] = (u8)((st) >> 16); \\\n(ct)[2] = (u8)((st) >>  8); (ct)[3] = (u8)(st); }\n#endif\n\n/**\n * Expand the cipher key into the encryption key schedule.\n *\n * @return\tthe number of rounds for the given cipher key size.\n */\nstatic void rijndaelKeySetupEnc(u32 rk[/*44*/], const u8 cipherKey[])\n{\n\tint i;\n\tu32 temp;\n\n\trk[0] = GETU32(cipherKey     );\n\trk[1] = GETU32(cipherKey +  4);\n\trk[2] = GETU32(cipherKey +  8);\n\trk[3] = GETU32(cipherKey + 12);\n\tfor (i = 0; i < 10; i++) {\n\t\ttemp  = rk[3];\n\t\trk[4] = rk[0] ^\n\t\t\tTE421(temp) ^ TE432(temp) ^ TE443(temp) ^ TE414(temp) ^\n\t\t\tRCON(i);\n\t\trk[5] = rk[1] ^ rk[4];\n\t\trk[6] = rk[2] ^ rk[5];\n\t\trk[7] = rk[3] ^ rk[6];\n\t\trk += 4;\n\t}\n}\n\n#ifndef CONFIG_NO_AES_DECRYPT\n/**\n * Expand the cipher key into the decryption key schedule.\n *\n * @return\tthe number of rounds for the given cipher key size.\n */\nstatic void rijndaelKeySetupDec(u32 rk[/*44*/], const u8 cipherKey[])\n{\n\tint Nr = 10, i, j;\n\tu32 temp;\n\n\t/* expand the cipher key: */\n\trijndaelKeySetupEnc(rk, cipherKey);\n\t/* invert the order of the round keys: */\n\tfor (i = 0, j = 4*Nr; i < j; i += 4, j -= 4) {\n\t\ttemp = rk[i    ]; rk[i    ] = rk[j    ]; rk[j    ] = temp;\n\t\ttemp = rk[i + 1]; rk[i + 1] = rk[j + 1]; rk[j + 1] = temp;\n\t\ttemp = rk[i + 2]; rk[i + 2] = rk[j + 2]; rk[j + 2] = temp;\n\t\ttemp = rk[i + 3]; rk[i + 3] = rk[j + 3]; rk[j + 3] = temp;\n\t}\n\t/* apply the inverse MixColumn transform to all round keys but the\n\t * first and the last: */\n\tfor (i = 1; i < Nr; i++) {\n\t\trk += 4;\n\t\tfor (j = 0; j < 4; j++) {\n\t\t\trk[j] = TD0_(TE4((rk[j] >> 24)       )) ^\n\t\t\t\tTD1_(TE4((rk[j] >> 16) & 0xff)) ^\n\t\t\t\tTD2_(TE4((rk[j] >>  8) & 0xff)) ^\n\t\t\t\tTD3_(TE4((rk[j]      ) & 0xff));\n\t\t}\n\t}\n}\n#endif /* CONFIG_NO_AES_DECRYPT */\n\n#ifndef CONFIG_NO_AES_ENCRYPT\nstatic void rijndaelEncrypt(const u32 rk[/*44*/], const u8 pt[16], u8 ct[16])\n{\n\tu32 s0, s1, s2, s3, t0, t1, t2, t3;\n\tconst int Nr = 10;\n#ifndef FULL_UNROLL\n\tint r;\n#endif /* ?FULL_UNROLL */\n\n\t/*\n\t * map byte array block to cipher state\n\t * and add initial round key:\n\t */\n\ts0 = GETU32(pt     ) ^ rk[0];\n\ts1 = GETU32(pt +  4) ^ rk[1];\n\ts2 = GETU32(pt +  8) ^ rk[2];\n\ts3 = GETU32(pt + 12) ^ rk[3];\n\n#define ROUND(i,d,s) \\\nd##0 = TE0(s##0) ^ TE1(s##1) ^ TE2(s##2) ^ TE3(s##3) ^ rk[4 * i]; \\\nd##1 = TE0(s##1) ^ TE1(s##2) ^ TE2(s##3) ^ TE3(s##0) ^ rk[4 * i + 1]; \\\nd##2 = TE0(s##2) ^ TE1(s##3) ^ TE2(s##0) ^ TE3(s##1) ^ rk[4 * i + 2]; \\\nd##3 = TE0(s##3) ^ TE1(s##0) ^ TE2(s##1) ^ TE3(s##2) ^ rk[4 * i + 3]\n\n#ifdef FULL_UNROLL\n\n\tROUND(1,t,s);\n\tROUND(2,s,t);\n\tROUND(3,t,s);\n\tROUND(4,s,t);\n\tROUND(5,t,s);\n\tROUND(6,s,t);\n\tROUND(7,t,s);\n\tROUND(8,s,t);\n\tROUND(9,t,s);\n\n\trk += Nr << 2;\n\n#else  /* !FULL_UNROLL */\n\n\t/* Nr - 1 full rounds: */\n\tr = Nr >> 1;\n\tfor (;;) {\n\t\tROUND(1,t,s);\n\t\trk += 8;\n\t\tif (--r == 0)\n\t\t\tbreak;\n\t\tROUND(0,s,t);\n\t}\n\n#endif /* ?FULL_UNROLL */\n\n#undef ROUND\n\n\t/*\n\t * apply last round and\n\t * map cipher state to byte array block:\n\t */\n\ts0 = TE41(t0) ^ TE42(t1) ^ TE43(t2) ^ TE44(t3) ^ rk[0];\n\tPUTU32(ct     , s0);\n\ts1 = TE41(t1) ^ TE42(t2) ^ TE43(t3) ^ TE44(t0) ^ rk[1];\n\tPUTU32(ct +  4, s1);\n\ts2 = TE41(t2) ^ TE42(t3) ^ TE43(t0) ^ TE44(t1) ^ rk[2];\n\tPUTU32(ct +  8, s2);\n\ts3 = TE41(t3) ^ TE42(t0) ^ TE43(t1) ^ TE44(t2) ^ rk[3];\n\tPUTU32(ct + 12, s3);\n}\n#endif /* CONFIG_NO_AES_ENCRYPT */\n\nstatic void rijndaelDecrypt(const u32 rk[/*44*/], const u8 ct[16], u8 pt[16])\n{\n\tu32 s0, s1, s2, s3, t0, t1, t2, t3;\n\tconst int Nr = 10;\n#ifndef FULL_UNROLL\n\tint r;\n#endif /* ?FULL_UNROLL */\n\n\t/*\n\t * map byte array block to cipher state\n\t * and add initial round key:\n\t */\n\ts0 = GETU32(ct     ) ^ rk[0];\n\ts1 = GETU32(ct +  4) ^ rk[1];\n\ts2 = GETU32(ct +  8) ^ rk[2];\n\ts3 = GETU32(ct + 12) ^ rk[3];\n\n#define ROUND(i,d,s) \\\nd##0 = TD0(s##0) ^ TD1(s##3) ^ TD2(s##2) ^ TD3(s##1) ^ rk[4 * i]; \\\nd##1 = TD0(s##1) ^ TD1(s##0) ^ TD2(s##3) ^ TD3(s##2) ^ rk[4 * i + 1]; \\\nd##2 = TD0(s##2) ^ TD1(s##1) ^ TD2(s##0) ^ TD3(s##3) ^ rk[4 * i + 2]; \\\nd##3 = TD0(s##3) ^ TD1(s##2) ^ TD2(s##1) ^ TD3(s##0) ^ rk[4 * i + 3]\n\n#ifdef FULL_UNROLL\n\n\tROUND(1,t,s);\n\tROUND(2,s,t);\n\tROUND(3,t,s);\n\tROUND(4,s,t);\n\tROUND(5,t,s);\n\tROUND(6,s,t);\n\tROUND(7,t,s);\n\tROUND(8,s,t);\n\tROUND(9,t,s);\n\n\trk += Nr << 2;\n\n#else  /* !FULL_UNROLL */\n\n\t/* Nr - 1 full rounds: */\n\tr = Nr >> 1;\n\tfor (;;) {\n\t\tROUND(1,t,s);\n\t\trk += 8;\n\t\tif (--r == 0)\n\t\t\tbreak;\n\t\tROUND(0,s,t);\n\t}\n\n#endif /* ?FULL_UNROLL */\n\n#undef ROUND\n\n\t/*\n\t * apply last round and\n\t * map cipher state to byte array block:\n\t */\n\ts0 = TD41(t0) ^ TD42(t3) ^ TD43(t2) ^ TD44(t1) ^ rk[0];\n\tPUTU32(pt     , s0);\n\ts1 = TD41(t1) ^ TD42(t0) ^ TD43(t3) ^ TD44(t2) ^ rk[1];\n\tPUTU32(pt +  4, s1);\n\ts2 = TD41(t2) ^ TD42(t1) ^ TD43(t0) ^ TD44(t3) ^ rk[2];\n\tPUTU32(pt +  8, s2);\n\ts3 = TD41(t3) ^ TD42(t2) ^ TD43(t1) ^ TD44(t0) ^ rk[3];\n\tPUTU32(pt + 12, s3);\n}\n\n#define AES_PRIV_SIZE 44\n"
  },
  {
    "path": "package/network/services/ead/src/ead-client.c",
    "content": "/*\n * Client for the Emergency Access Daemon\n * Copyright (C) 2008 Felix Fietkau <nbd@nbd.name>\n *\n * This program is free software; you can redistribute it and/or modify\n * it under the terms of the GNU General Public License version 2\n * as published by the Free Software Foundation\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n * GNU General Public License for more details.\n */\n\n#include <sys/types.h>\n#include <sys/socket.h>\n#include <sys/time.h>\n#include <netinet/in.h>\n#include <arpa/inet.h>\n#include <stdio.h>\n#include <stddef.h>\n#include <stdint.h>\n#include <stdlib.h>\n#include <stdbool.h>\n#include <string.h>\n#include <fcntl.h>\n#include <unistd.h>\n#include <t_pwd.h>\n#include <t_read.h>\n#include <t_sha.h>\n#include <t_defines.h>\n#include <t_client.h>\n#include \"ead.h\"\n#include \"ead-crypt.h\"\n\n#include \"pw_encrypt_md5.c\"\n\n#define EAD_TIMEOUT\t400\n#define EAD_TIMEOUT_LONG 2000\n\nstatic char msgbuf[1500];\nstatic struct ead_msg *msg = (struct ead_msg *) msgbuf;\nstatic uint16_t nid = 0xffff;\nstruct sockaddr_in local, remote;\nstatic int s = 0;\nstatic int sockflags;\nstatic struct in_addr serverip = {\n\t.s_addr = 0x01010101 /* dummy */\n};\n\nstatic unsigned char *skey = NULL;\nstatic unsigned char bbuf[MAXPARAMLEN];\nstatic unsigned char saltbuf[MAXSALTLEN];\nstatic char *username = NULL;\nstatic char password[MAXPARAMLEN] = \"\";\nstatic char pw_md5[MD5_OUT_BUFSIZE];\nstatic char pw_salt[MAXSALTLEN];\n\nstatic struct t_client *tc = NULL;\nstatic struct t_num salt = { .data = saltbuf };\nstatic struct t_num *A, B;\nstatic struct t_preconf *tcp;\nstatic int auth_type = EAD_AUTH_DEFAULT;\nstatic int timeout = EAD_TIMEOUT;\nstatic uint16_t sid = 0;\n\nstatic void\nset_nonblock(int enable)\n{\n\tif (enable == !!(sockflags & O_NONBLOCK))\n\t\treturn;\n\n\tsockflags ^= O_NONBLOCK;\n\tfcntl(s, F_SETFL, sockflags);\n}\n\nstatic int\nsend_packet(int type, bool (*handler)(void), unsigned int max)\n{\n\tstruct timeval tv;\n\tfd_set fds;\n\tint nfds;\n\tint len;\n\tint res = 0;\n\n\ttype = htonl(type);\n\tmemcpy(&msg->ip, &serverip.s_addr, sizeof(msg->ip));\n\tset_nonblock(0);\n\tsendto(s, msgbuf, sizeof(struct ead_msg) + ntohl(msg->len), 0, (struct sockaddr *) &remote, sizeof(remote));\n\tset_nonblock(1);\n\n\ttv.tv_sec = timeout / 1000;\n\ttv.tv_usec = (timeout % 1000) * 1000;\n\n\tFD_ZERO(&fds);\n\tdo {\n\t\tFD_SET(s, &fds);\n\t\tnfds = select(s + 1, &fds, NULL, NULL, &tv);\n\n\t\tif (nfds <= 0)\n\t\t\tbreak;\n\n\t\tif (!FD_ISSET(s, &fds))\n\t\t\tbreak;\n\n\t\tlen = read(s, msgbuf, sizeof(msgbuf));\n\t\tif (len < 0)\n\t\t\tbreak;\n\n\t\tif (len < sizeof(struct ead_msg))\n\t\t\tcontinue;\n\n\t\tif (len < sizeof(struct ead_msg) + ntohl(msg->len))\n\t\t\tcontinue;\n\n\t\tif (msg->magic != htonl(EAD_MAGIC))\n\t\t\tcontinue;\n\n\t\tif ((nid != 0xffff) && (ntohs(msg->nid) != nid))\n\t\t\tcontinue;\n\n\t\tif (msg->type != type)\n\t\t\tcontinue;\n\n\t\tif (handler())\n\t\t\tres++;\n\n\t\tif ((max > 0) && (res >= max))\n\t\t\tbreak;\n\t} while (1);\n\n\treturn res;\n}\n\nstatic void\nprepare_password(void)\n{\n\tswitch(auth_type) {\n\tcase EAD_AUTH_DEFAULT:\n\t\tbreak;\n\tcase EAD_AUTH_MD5:\n\t\tmd5_crypt(pw_md5, (unsigned char *) password, (unsigned char *) pw_salt);\n\t\tstrncpy(password, pw_md5, sizeof(password));\n\t\tbreak;\n\t}\n}\n\nstatic bool\nhandle_pong(void)\n{\n\tstruct ead_msg_pong *pong = EAD_DATA(msg, pong);\n\tint len = ntohl(msg->len) - sizeof(struct ead_msg_pong);\n\n\tif (len <= 0)\n\t\treturn false;\n\n\tpong->name[len] = 0;\n\tauth_type = ntohs(pong->auth_type);\n\tif (nid == 0xffff)\n\t\tprintf(\"%04x: %s\\n\", ntohs(msg->nid), pong->name);\n\tsid = msg->sid;\n\treturn true;\n}\n\nstatic bool\nhandle_prime(void)\n{\n\tstruct ead_msg_salt *sb = EAD_DATA(msg, salt);\n\n\tsalt.len = sb->len;\n\tmemcpy(salt.data, sb->salt, salt.len);\n\n\tif (auth_type == EAD_AUTH_MD5) {\n\t\tmemcpy(pw_salt, sb->ext_salt, MAXSALTLEN);\n\t\tpw_salt[MAXSALTLEN - 1] = 0;\n\t}\n\n\ttcp = t_getpreparam(sb->prime);\n\ttc = t_clientopen(username, &tcp->modulus, &tcp->generator, &salt);\n\tif (!tc) {\n\t\tfprintf(stderr, \"Client open failed\\n\");\n\t\treturn false;\n\t}\n\n\treturn true;\n}\n\nstatic bool\nhandle_b(void)\n{\n\tstruct ead_msg_number *num = EAD_DATA(msg, number);\n\tint len = ntohl(msg->len) - sizeof(struct ead_msg_number);\n\n\tB.data = bbuf;\n\tB.len = len;\n\tmemcpy(bbuf, num->data, len);\n\treturn true;\n}\n\nstatic bool\nhandle_none(void)\n{\n\treturn true;\n}\n\nstatic bool\nhandle_done_auth(void)\n{\n\tstruct ead_msg_auth *auth = EAD_DATA(msg, auth);\n\tif (t_clientverify(tc, auth->data) != 0) {\n\t\tfprintf(stderr, \"Client auth verify failed\\n\");\n\t\treturn false;\n\t}\n\treturn true;\n}\n\nstatic bool\nhandle_cmd_data(void)\n{\n\tstruct ead_msg_cmd_data *cmd = EAD_ENC_DATA(msg, cmd_data);\n\tint datalen = ead_decrypt_message(msg) - sizeof(struct ead_msg_cmd_data);\n\n\tif (datalen < 0)\n\t\treturn false;\n\n\tif (datalen > 0) {\n\t\twrite(1, cmd->data, datalen);\n\t}\n\n\treturn !!cmd->done;\n}\nstatic int\nsend_ping(void)\n{\n\tmsg->type = htonl(EAD_TYPE_PING);\n\tmsg->len = 0;\n\treturn send_packet(EAD_TYPE_PONG, handle_pong, (nid == 0xffff ? 0 : 1));\n}\n\nstatic int\nsend_username(void)\n{\n\tmsg->type = htonl(EAD_TYPE_SET_USERNAME);\n\tmsg->len = htonl(sizeof(struct ead_msg_user));\n\tstrcpy(EAD_DATA(msg, user)->username, username);\n\treturn send_packet(EAD_TYPE_ACK_USERNAME, handle_none, 1);\n}\n\nstatic int\nget_prime(void)\n{\n\tmsg->type = htonl(EAD_TYPE_GET_PRIME);\n\tmsg->len = 0;\n\treturn send_packet(EAD_TYPE_PRIME, handle_prime, 1);\n}\n\nstatic int\nsend_a(void)\n{\n\tstruct ead_msg_number *num = EAD_DATA(msg, number);\n\tA = t_clientgenexp(tc);\n\tmsg->type = htonl(EAD_TYPE_SEND_A);\n\tmsg->len = htonl(sizeof(struct ead_msg_number) + A->len);\n\tmemcpy(num->data, A->data, A->len);\n\treturn send_packet(EAD_TYPE_SEND_B, handle_b, 1);\n}\n\nstatic int\nsend_auth(void)\n{\n\tstruct ead_msg_auth *auth = EAD_DATA(msg, auth);\n\n\tprepare_password();\n\tt_clientpasswd(tc, password);\n\tskey = t_clientgetkey(tc, &B);\n\tif (!skey)\n\t\treturn 0;\n\n\tead_set_key(skey);\n\tmsg->type = htonl(EAD_TYPE_SEND_AUTH);\n\tmsg->len = htonl(sizeof(struct ead_msg_auth));\n\tmemcpy(auth->data, t_clientresponse(tc), sizeof(auth->data));\n\treturn send_packet(EAD_TYPE_DONE_AUTH, handle_done_auth, 1);\n}\n\nstatic int\nsend_command(const char *command)\n{\n\tstruct ead_msg_cmd *cmd = EAD_ENC_DATA(msg, cmd);\n\n\tmsg->type = htonl(EAD_TYPE_SEND_CMD);\n\tcmd->type = htons(EAD_CMD_NORMAL);\n\tcmd->timeout = htons(10);\n\tstrncpy((char *)cmd->data, command, 1024);\n\tead_encrypt_message(msg, sizeof(struct ead_msg_cmd) + strlen(command) + 1);\n\treturn send_packet(EAD_TYPE_RESULT_CMD, handle_cmd_data, 1);\n}\n\n\nstatic int\nusage(const char *prog)\n{\n\tfprintf(stderr, \"Usage: %s [-s <addr>] [-b <addr>] <node> <username>[:<password>] <command>\\n\"\n\t\t\"\\n\"\n\t\t\"\\t-s <addr>:  Set the server's source address to <addr>\\n\"\n\t\t\"\\t-b <addr>:  Set the broadcast address to <addr>\\n\"\n\t\t\"\\t<node>:     Node ID (4 digits hex)\\n\"\n\t\t\"\\t<username>: Username to authenticate with\\n\"\n\t\t\"\\n\"\n\t\t\"\\tPassing no arguments shows a list of active nodes on the network\\n\"\n\t\t\"\\n\", prog);\n\treturn -1;\n}\n\n\nint main(int argc, char **argv)\n{\n\tint val = 1;\n\tchar *st = NULL;\n\tconst char *command = NULL;\n\tconst char *prog = argv[0];\n\tint ch;\n\n\tmsg->magic = htonl(EAD_MAGIC);\n\tmsg->sid = 0;\n\n\tmemset(&local, 0, sizeof(local));\n\tmemset(&remote, 0, sizeof(remote));\n\n\tremote.sin_family = AF_INET;\n\tremote.sin_addr.s_addr = 0xffffffff;\n\tremote.sin_port = htons(EAD_PORT);\n\n\tlocal.sin_family = AF_INET;\n\tlocal.sin_addr.s_addr = INADDR_ANY;\n\tlocal.sin_port = 0;\n\n\twhile ((ch = getopt(argc, argv, \"b:s:h\")) != -1) {\n\t\tswitch(ch) {\n\t\tcase 's':\n\t\t\tinet_aton(optarg, &serverip);\n\t\t\tbreak;\n\t\tcase 'b':\n\t\t\tinet_aton(optarg, &remote.sin_addr);\n\t\t\tbreak;\n\t\tcase 'h':\n\t\t\treturn usage(prog);\n\t\t}\n\t}\n\targv += optind;\n\targc -= optind;\n\n\tswitch(argc) {\n\tcase 3:\n\t\tcommand = argv[2];\n\t\t/* fall through */\n\tcase 2:\n\t\tusername = argv[1];\n\t\tst = strchr(username, ':');\n\t\tif (st) {\n\t\t\t*st = 0;\n\t\t\tst++;\n\t\t\tstrncpy(password, st, sizeof(password));\n\t\t\tpassword[sizeof(password) - 1] = 0;\n\t\t\t/* hide command line password */\n\t\t\tmemset(st, 0, strlen(st));\n\t\t}\n\t\t/* fall through */\n\tcase 1:\n\t\tnid = strtoul(argv[0], &st, 16);\n\t\tif (st && st[0] != 0)\n\t\t\treturn usage(prog);\n\t\t/* fall through */\n\tcase 0:\n\t\tbreak;\n\tdefault:\n\t\treturn usage(prog);\n\t}\n\n\tmsg->nid = htons(nid);\n\ts = socket(AF_INET, SOCK_DGRAM, IPPROTO_UDP);\n\tif (s < 0) {\n\t\tperror(\"socket\");\n\t\treturn -1;\n\t}\n\n\tsetsockopt(s, SOL_SOCKET, SO_BROADCAST, &val, sizeof(val));\n\n\tif (bind(s, (struct sockaddr *)&local, sizeof(local)) < 0) {\n\t\tperror(\"bind\");\n\t\treturn -1;\n\t}\n\tsockflags = fcntl(s, F_GETFL);\n\n\tif (!send_ping()) {\n\t\tfprintf(stderr, \"No devices found\\n\");\n\t\treturn 1;\n\t}\n\n\tif (nid == 0xffff)\n\t\treturn 0;\n\n\tif (!username || !password[0])\n\t\treturn 0;\n\n\tif (!send_username()) {\n\t\tfprintf(stderr, \"Device did not accept user name\\n\");\n\t\treturn 1;\n\t}\n\ttimeout = EAD_TIMEOUT_LONG;\n\tif (!get_prime()) {\n\t\tfprintf(stderr, \"Failed to get user password info\\n\");\n\t\treturn 1;\n\t}\n\tif (!send_a()) {\n\t\tfprintf(stderr, \"Failed to send local authentication data\\n\");\n\t\treturn 1;\n\t}\n\tif (!send_auth()) {\n\t\tfprintf(stderr, \"Authentication failed\\n\");\n\t\treturn 1;\n\t}\n\tif (!command) {\n\t\tfprintf(stderr, \"Authentication succesful\\n\");\n\t\treturn 0;\n\t}\n\tif (!send_command(command)) {\n\t\tfprintf(stderr, \"Command failed\\n\");\n\t\treturn 1;\n\t}\n\n\treturn 0;\n}\n"
  },
  {
    "path": "package/network/services/ead/src/ead-crypt.c",
    "content": "/*\n * Copyright (C) 2008 Felix Fietkau <nbd@nbd.name>\n *\n * This program is free software; you can redistribute it and/or modify\n * it under the terms of the GNU General Public License version 2\n * as published by the Free Software Foundation\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n * GNU General Public License for more details.\n */\n\n#include <stddef.h>\n#include <stdint.h>\n#include <stdlib.h>\n#include <stdbool.h>\n#include <string.h>\n#include <unistd.h>\n#include <stdio.h>\n#include \"ead.h\"\n\n#include \"sha1.c\"\n#include \"aes.c\"\n\n#if EAD_DEBUGLEVEL >= 1\n#define DEBUG(n, format, ...) do { \\\n\tif (EAD_DEBUGLEVEL >= n) \\\n\t\tfprintf(stderr, format, ##__VA_ARGS__); \\\n} while (0);\n\n#else\n#define DEBUG(n, format, ...) do {} while(0)\n#endif\n\n\nstatic uint32_t aes_enc_ctx[AES_PRIV_SIZE];\nstatic uint32_t aes_dec_ctx[AES_PRIV_SIZE];\nstatic uint32_t ead_rx_iv;\nstatic uint32_t ead_tx_iv;\nstatic uint32_t ivofs_vec;\nstatic unsigned int ivofs_idx = 0;\nstatic uint32_t W[80]; /* work space for sha1 */\n\n#define EAD_ENC_PAD\t64\n\nvoid\nead_set_key(unsigned char *skey)\n{\n\tuint32_t *ivp = (uint32_t *)skey;\n\n\tmemset(aes_enc_ctx, 0, sizeof(aes_enc_ctx));\n\tmemset(aes_dec_ctx, 0, sizeof(aes_dec_ctx));\n\n\t/* first 32 bytes of skey are used as aes key for\n\t * encryption and decryption */\n\trijndaelKeySetupEnc(aes_enc_ctx, skey);\n\trijndaelKeySetupDec(aes_dec_ctx, skey);\n\n\t/* the following bytes are used as initialization vector for messages\n\t * (highest byte cleared to avoid overflow) */\n\tivp += 8;\n\tead_rx_iv = ntohl(*ivp) & 0x00ffffff;\n\tead_tx_iv = ead_rx_iv;\n\n\t/* the last bytes are used to feed the random iv increment */\n\tivp++;\n\tivofs_vec = *ivp;\n}\n\n\nstatic bool\nead_check_rx_iv(uint32_t iv)\n{\n\tif (iv <= ead_rx_iv)\n\t\treturn false;\n\n\tif (iv > ead_rx_iv + EAD_MAX_IV_INCR)\n\t\treturn false;\n\n\tead_rx_iv = iv;\n\treturn true;\n}\n\n\nstatic uint32_t\nead_get_tx_iv(void)\n{\n\tunsigned int ofs;\n\n\tofs = 1 + ((ivofs_vec >> 2 * ivofs_idx) & 0x3);\n\tivofs_idx = (ivofs_idx + 1) % 16;\n\tead_tx_iv += ofs;\n\n\treturn ead_tx_iv;\n}\n\nstatic void\nead_hash_message(struct ead_msg_encrypted *enc, uint32_t *hash, int len)\n{\n\tunsigned char *data = (unsigned char *) enc;\n\n\t/* hash the packet with the stored hash part initialized to zero */\n\tsha_init(hash);\n\tmemset(enc->hash, 0, sizeof(enc->hash));\n\twhile (len > 0) {\n\t\tsha_transform(hash, data, W);\n\t\tlen -= 64;\n\t\tdata += 64;\n\t}\n}\n\nvoid\nead_encrypt_message(struct ead_msg *msg, unsigned int len)\n{\n\tstruct ead_msg_encrypted *enc = EAD_DATA(msg, enc);\n\tunsigned char *data = (unsigned char *) enc;\n\tuint32_t hash[5];\n\tint enclen, i;\n\n\tlen += sizeof(struct ead_msg_encrypted);\n\tenc->pad = (EAD_ENC_PAD - (len % EAD_ENC_PAD)) % EAD_ENC_PAD;\n\tenclen = len + enc->pad;\n\tmsg->len = htonl(enclen);\n\tenc->iv = htonl(ead_get_tx_iv());\n\n\tead_hash_message(enc, hash, enclen);\n\tfor (i = 0; i < 5; i++)\n\t\tenc->hash[i] = htonl(hash[i]);\n\tDEBUG(2, \"SHA1 generate (0x%08x), len=%d\\n\", enc->hash[0], enclen);\n\n\twhile (enclen > 0) {\n\t\trijndaelEncrypt(aes_enc_ctx, data, data);\n\t\tdata += 16;\n\t\tenclen -= 16;\n\t}\n}\n\nint\nead_decrypt_message(struct ead_msg *msg)\n{\n\tstruct ead_msg_encrypted *enc = EAD_DATA(msg, enc);\n\tunsigned char *data = (unsigned char *) enc;\n\tuint32_t hash_old[5], hash_new[5];\n\tint len = ntohl(msg->len);\n\tint i, enclen = len;\n\n\tif (!len || (len % EAD_ENC_PAD > 0))\n\t\treturn 0;\n\n\twhile (len > 0) {\n\t\trijndaelDecrypt(aes_dec_ctx, data, data);\n\t\tdata += 16;\n\t\tlen -= 16;\n\t}\n\n\tdata = (unsigned char *) enc;\n\n\tif (enc->pad >= EAD_ENC_PAD) {\n\t\tDEBUG(2, \"Invalid padding length\\n\");\n\t\treturn 0;\n\t}\n\n\tif (!ead_check_rx_iv(ntohl(enc->iv))) {\n\t\tDEBUG(2, \"RX IV mismatch (0x%08x <> 0x%08x)\\n\", ead_rx_iv, ntohl(enc->iv));\n\t\treturn 0;\n\t}\n\n\tfor (i = 0; i < 5; i++)\n\t\thash_old[i] = ntohl(enc->hash[i]);\n\tead_hash_message(enc, hash_new, enclen);\n\tif (memcmp(hash_old, hash_new, sizeof(hash_old)) != 0) {\n\t\tDEBUG(2, \"SHA1 mismatch (0x%08x != 0x%08x), len=%d\\n\", hash_old[0], hash_new[0], enclen);\n\t\treturn 0;\n\t}\n\n\tenclen -= enc->pad + sizeof(struct ead_msg_encrypted);\n\treturn enclen;\n}\n"
  },
  {
    "path": "package/network/services/ead/src/ead-crypt.h",
    "content": "/*\n * Copyright (C) 2008 Felix Fietkau <nbd@nbd.name>\n *\n * This program is free software; you can redistribute it and/or modify\n * it under the terms of the GNU General Public License version 2\n * as published by the Free Software Foundation\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n * GNU General Public License for more details.\n */\n\n#ifndef __EAD_CRYPT_H\n#define __EAD_CRYPT_H\n\nextern void ead_set_key(unsigned char *skey);\nextern void ead_encrypt_message(struct ead_msg *msg, unsigned int len);\nextern int ead_decrypt_message(struct ead_msg *msg);\n\n#endif\n"
  },
  {
    "path": "package/network/services/ead/src/ead-pcap.h",
    "content": "/*\n * Copyright (c) 2001-2003, Adam Dunkels.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. The name of the author may not be used to endorse or promote\n *    products derived from this software without specific prior\n *    written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS\n * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY\n * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE\n * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\n * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\n * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n *\n * This file was part of the uIP TCP/IP stack.\n *\n */\n#ifndef __EAD_PCAP_H\n#define __EAD_PCAP_H\n\n#include <net/ethernet.h>\n#include <stdint.h>\n#include \"ead.h\"\n\ntypedef uint8_t u8_t;\ntypedef uint16_t u16_t;\n\n/* The UDP and IP headers. */\nstruct ead_packet {\n  struct ether_header eh;\n  /* IP header. */\n  u8_t vhl,\n    tos,\n    len[2],\n    ipid[2],\n    ipoffset[2],\n    ttl,\n    proto;\n  u16_t ipchksum;\n  u16_t srcipaddr[2],\n    destipaddr[2];\n\n  /* UDP header. */\n  u16_t srcport,\n    destport;\n  u16_t udplen;\n  u16_t udpchksum;\n\n  struct ead_msg msg;\n} __attribute__((packed));\n\n#define UIP_PROTO_UDP  17\n#define UIP_IPH_LEN    20    /* Size of IP header */\n#define UIP_UDPH_LEN   8    /* Size of UDP header */\n#define UIP_IPUDPH_LEN (UIP_UDPH_LEN + UIP_IPH_LEN)\n\n#endif\n"
  },
  {
    "path": "package/network/services/ead/src/ead.c",
    "content": "/*\n * Emergency Access Daemon\n * Copyright (C) 2008 Felix Fietkau <nbd@nbd.name>\n *\n * This program is free software; you can redistribute it and/or modify\n * it under the terms of the GNU General Public License version 2\n * as published by the Free Software Foundation\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n * GNU General Public License for more details.\n */\n\n#include <sys/types.h>\n#include <sys/time.h>\n#include <sys/select.h>\n#include <stdio.h>\n#include <stddef.h>\n#include <stdlib.h>\n#include <string.h>\n#include <unistd.h>\n#include <stdbool.h>\n#include <fcntl.h>\n#include <signal.h>\n#include <pcap.h>\n#include <pcap-bpf.h>\n#include <t_pwd.h>\n#include <t_read.h>\n#include <t_sha.h>\n#include <t_defines.h>\n#include <t_server.h>\n#include <net/if.h>\n\n#include \"list.h\"\n#include \"ead.h\"\n#include \"ead-pcap.h\"\n#include \"ead-crypt.h\"\n#include \"libbridge.h\"\n\n#include \"filter.c\"\n\n#ifdef linux\n#include <linux/if_packet.h>\n#endif\n\n#define PASSWD_FILE\t\"/etc/passwd\"\n\n#ifndef DEFAULT_IFNAME\n#define DEFAULT_IFNAME \"eth0\"\n#endif\n\n#ifndef DEFAULT_DEVNAME\n#define DEFAULT_DEVNAME \"Unknown\"\n#endif\n\n#define PCAP_MRU\t\t1600\n#define PCAP_TIMEOUT\t200\n\n#if EAD_DEBUGLEVEL >= 1\n#define DEBUG(n, format, ...) do { \\\n\tif (EAD_DEBUGLEVEL >= n) \\\n\t\tfprintf(stderr, format, ##__VA_ARGS__); \\\n} while (0);\n\n#else\n#define DEBUG(n, format, ...) do {} while(0)\n#endif\n\nstruct ead_instance {\n\tstruct list_head list;\n\tchar ifname[16];\n\tint pid;\n\tchar id;\n\tchar bridge[16];\n\tbool br_check;\n};\n\nstatic char ethmac[6] = \"\\x00\\x13\\x37\\x00\\x00\\x00\"; /* last 3 bytes will be randomized */\nstatic pcap_t *pcap_fp = NULL;\nstatic pcap_t *pcap_fp_rx = NULL;\nstatic char pktbuf_b[PCAP_MRU];\nstatic struct ead_packet *pktbuf = (struct ead_packet *)pktbuf_b;\nstatic u16_t nid = 0xffff; /* node id */\nstatic char username[32] = \"\";\nstatic int state = EAD_TYPE_SET_USERNAME;\nstatic const char *passwd_file = PASSWD_FILE;\nstatic const char password[MAXPARAMLEN];\nstatic bool child_pending = false;\n\nstatic unsigned char abuf[MAXPARAMLEN + 1];\nstatic unsigned char pwbuf[MAXPARAMLEN];\nstatic unsigned char saltbuf[MAXSALTLEN];\nstatic unsigned char pw_saltbuf[MAXSALTLEN];\nstatic struct list_head instances;\nstatic const char *dev_name = DEFAULT_DEVNAME;\nstatic bool nonfork = false;\nstatic struct ead_instance *instance = NULL;\n\nstatic struct t_pwent tpe = {\n\t.name = username,\n\t.index = 1,\n\t.password.data = pwbuf,\n\t.password.len = 0,\n\t.salt.data = saltbuf,\n\t.salt.len = 0,\n};\nstruct t_confent *tce = NULL;\nstatic struct t_server *ts = NULL;\nstatic struct t_num A, *B = NULL;\nunsigned char *skey;\n\nstatic void\nset_recv_type(pcap_t *p, bool rx)\n{\n#ifdef PACKET_RECV_TYPE\n\tstruct sockaddr_ll sll;\n\tstruct ifreq ifr;\n\tint mask;\n\tint fd;\n\n\tfd = pcap_get_selectable_fd(p);\n\tif (fd < 0)\n\t\treturn;\n\n\tif (rx)\n\t\tmask = 1 << PACKET_BROADCAST;\n\telse\n\t\tmask = 0;\n\n\tsetsockopt(fd, SOL_PACKET, PACKET_RECV_TYPE, &mask, sizeof(mask));\n#endif\n}\n\n\nstatic pcap_t *\nead_open_pcap(const char *ifname, char *errbuf, bool rx)\n{\n\tpcap_t *p;\n\n\tp = pcap_create(ifname, errbuf);\n\tif (p == NULL)\n\t\tgoto out;\n\n\tpcap_set_snaplen(p, PCAP_MRU);\n\tpcap_set_promisc(p, rx);\n\tpcap_set_timeout(p, PCAP_TIMEOUT);\n\tpcap_set_protocol_linux(p, (rx ? htons(ETH_P_IP) : 0));\n\tpcap_set_buffer_size(p, (rx ? 10 : 1) * PCAP_MRU);\n\tpcap_activate(p);\n\tset_recv_type(p, rx);\nout:\n\treturn p;\n}\n\nstatic void\nget_random_bytes(void *ptr, int len)\n{\n\tint fd;\n\n\tfd = open(\"/dev/urandom\", O_RDONLY);\n\tif (fd < 0) {\n\t\tperror(\"open\");\n\t\texit(1);\n\t}\n\tread(fd, ptr, len);\n\tclose(fd);\n}\n\nstatic bool\nprepare_password(void)\n{\n\tstatic char lbuf[1024];\n\tunsigned char dig[SHA_DIGESTSIZE];\n\tBigInteger x, v, n, g;\n\tSHA1_CTX ctxt;\n\tint ulen = strlen(username);\n\tFILE *f;\n\n\tlbuf[sizeof(lbuf) - 1] = 0;\n\n\tf = fopen(passwd_file, \"r\");\n\tif (!f)\n\t\treturn false;\n\n\twhile (fgets(lbuf, sizeof(lbuf) - 1, f) != NULL) {\n\t\tchar *str, *s2;\n\n\t\tif (strncmp(lbuf, username, ulen) != 0)\n\t\t\tcontinue;\n\n\t\tif (lbuf[ulen] != ':')\n\t\t\tcontinue;\n\n\t\tstr = &lbuf[ulen + 1];\n\n\t\tif (strncmp(str, \"$1$\", 3) != 0)\n\t\t\tcontinue;\n\n\t\ts2 = strchr(str + 3, '$');\n\t\tif (!s2)\n\t\t\tcontinue;\n\n\t\tif (s2 - str >= MAXSALTLEN)\n\t\t\tcontinue;\n\n\t\tstrncpy((char *) pw_saltbuf, str, s2 - str);\n\t\tpw_saltbuf[s2 - str] = 0;\n\n\t\ts2 = strchr(s2, ':');\n\t\tif (!s2)\n\t\t\tcontinue;\n\n\t\t*s2 = 0;\n\t\tif (s2 - str >= MAXPARAMLEN)\n\t\t\tcontinue;\n\n\t\tstrncpy((char *)password, str, MAXPARAMLEN);\n\t\tfclose(f);\n\t\tgoto hash_password;\n\t}\n\n\t/* not found */\n\tfclose(f);\n\treturn false;\n\nhash_password:\n\ttce = gettcid(tpe.index);\n\tdo {\n\t\tt_random(tpe.password.data, SALTLEN);\n\t} while (memcmp(saltbuf, (char *)dig, sizeof(saltbuf)) == 0);\n\tif (saltbuf[0] == 0)\n\t\tsaltbuf[0] = 0xff;\n\n\tn = BigIntegerFromBytes(tce->modulus.data, tce->modulus.len);\n\tg = BigIntegerFromBytes(tce->generator.data, tce->generator.len);\n\tv = BigIntegerFromInt(0);\n\n\tSHA1Init(&ctxt);\n\tSHA1Update(&ctxt, (unsigned char *) username, strlen(username));\n\tSHA1Update(&ctxt, (unsigned char *) \":\", 1);\n\tSHA1Update(&ctxt, (unsigned char *) password, strlen(password));\n\tSHA1Final(dig, &ctxt);\n\n\tSHA1Init(&ctxt);\n\tSHA1Update(&ctxt, saltbuf, tpe.salt.len);\n\tSHA1Update(&ctxt, dig, sizeof(dig));\n\tSHA1Final(dig, &ctxt);\n\n\t/* x = H(s, H(u, ':', p)) */\n\tx = BigIntegerFromBytes(dig, sizeof(dig));\n\n\tBigIntegerModExp(v, g, x, n);\n\ttpe.password.len = BigIntegerToBytes(v, (unsigned char *)pwbuf);\n\n\tBigIntegerFree(v);\n\tBigIntegerFree(x);\n\tBigIntegerFree(g);\n\tBigIntegerFree(n);\n\treturn true;\n}\n\nstatic u16_t\nchksum(u16_t sum, const u8_t *data, u16_t len)\n{\n\tu16_t t;\n\tconst u8_t *dataptr;\n\tconst u8_t *last_byte;\n\n\tdataptr = data;\n\tlast_byte = data + len - 1;\n\n\twhile(dataptr < last_byte) {\t/* At least two more bytes */\n\t\tt = (dataptr[0] << 8) + dataptr[1];\n\t\tsum += t;\n\t\tif(sum < t) {\n\t\t\tsum++;\t\t/* carry */\n\t\t}\n\t\tdataptr += 2;\n\t}\n\n\tif(dataptr == last_byte) {\n\t\tt = (dataptr[0] << 8) + 0;\n\t\tsum += t;\n\t\tif(sum < t) {\n\t\t\tsum++;\t\t/* carry */\n\t\t}\n\t}\n\n\t/* Return sum in host byte order. */\n\treturn sum;\n}\n\nstatic void\nead_send_packet_clone(struct ead_packet *pkt)\n{\n\tu16_t len, sum;\n\n\tmemcpy(pktbuf, pkt, offsetof(struct ead_packet, msg));\n\tmemcpy(pktbuf->eh.ether_shost, ethmac, 6);\n\tmemcpy(pktbuf->eh.ether_dhost, pkt->eh.ether_shost, 6);\n\n\t/* ip header */\n\tlen = sizeof(struct ead_packet) - sizeof(struct ether_header) + ntohl(pktbuf->msg.len);\n\tpktbuf->len[0] = len >> 8;\n\tpktbuf->len[1] = len & 0xff;\n\tmemcpy(pktbuf->srcipaddr, &pkt->msg.ip, 4);\n\tmemcpy(pktbuf->destipaddr, pkt->srcipaddr, 4);\n\n\t/* ip checksum */\n\tpktbuf->ipchksum = 0;\n\tsum = chksum(0, (void *) &pktbuf->vhl, UIP_IPH_LEN);\n\tif (sum == 0)\n\t\tsum = 0xffff;\n\tpktbuf->ipchksum = htons(~sum);\n\n\t/* udp header */\n\tpktbuf->srcport = pkt->destport;\n\tpktbuf->destport = pkt->srcport;\n\n\t/* udp checksum */\n\tlen -= UIP_IPH_LEN;\n\tpktbuf->udplen = htons(len);\n\tpktbuf->udpchksum = 0;\n\tsum = len + UIP_PROTO_UDP;\n\tsum = chksum(sum, (void *) &pktbuf->srcipaddr[0], 8); /* src, dest ip */\n\tsum = chksum(sum, (void *) &pktbuf->srcport, len);\n\tif (sum == 0)\n\t\tsum = 0xffff;\n\tpktbuf->udpchksum = htons(~sum);\n\tpcap_sendpacket(pcap_fp, (void *) pktbuf, sizeof(struct ead_packet) + ntohl(pktbuf->msg.len));\n}\n\nstatic void\nset_state(int nstate)\n{\n\tif (state == nstate)\n\t\treturn;\n\n\tif (nstate < state) {\n\t\tif ((nstate < EAD_TYPE_GET_PRIME) &&\n\t\t\t(state >= EAD_TYPE_GET_PRIME)) {\n\t\t\tt_serverclose(ts);\n\t\t\tts = NULL;\n\t\t}\n\t\tgoto done;\n\t}\n\n\tswitch(state) {\n\tcase EAD_TYPE_SET_USERNAME:\n\t\tif (!prepare_password())\n\t\t\tgoto error;\n\t\tts = t_serveropenraw(&tpe, tce);\n\t\tif (!ts)\n\t\t\tgoto error;\n\t\tbreak;\n\tcase EAD_TYPE_GET_PRIME:\n\t\tB = t_servergenexp(ts);\n\t\tbreak;\n\tcase EAD_TYPE_SEND_A:\n\t\tskey = t_servergetkey(ts, &A);\n\t\tif (!skey)\n\t\t\tgoto error;\n\n\t\tead_set_key(skey);\n\t\tbreak;\n\t}\ndone:\n\tstate = nstate;\nerror:\n\treturn;\n}\n\nstatic bool\nhandle_ping(struct ead_packet *pkt, int len, int *nstate)\n{\n\tstruct ead_msg *msg = &pktbuf->msg;\n\tstruct ead_msg_pong *pong = EAD_DATA(msg, pong);\n\tint slen;\n\n\tslen = strlen(dev_name);\n\tif (slen > 1024)\n\t\tslen = 1024;\n\n\tmsg->len = htonl(sizeof(struct ead_msg_pong) + slen);\n\tstrncpy(pong->name, dev_name, slen);\n\tpong->name[slen] = 0;\n\tpong->auth_type = htons(EAD_AUTH_MD5);\n\n\treturn true;\n}\n\nstatic bool\nhandle_set_username(struct ead_packet *pkt, int len, int *nstate)\n{\n\tstruct ead_msg *msg = &pkt->msg;\n\tstruct ead_msg_user *user = EAD_DATA(msg, user);\n\n\tset_state(EAD_TYPE_SET_USERNAME); /* clear old state */\n\tstrncpy(username, user->username, sizeof(username));\n\tusername[sizeof(username) - 1] = 0;\n\n\tmsg = &pktbuf->msg;\n\tmsg->len = 0;\n\n\t*nstate = EAD_TYPE_GET_PRIME;\n\treturn true;\n}\n\nstatic bool\nhandle_get_prime(struct ead_packet *pkt, int len, int *nstate)\n{\n\tstruct ead_msg *msg = &pktbuf->msg;\n\tstruct ead_msg_salt *salt = EAD_DATA(msg, salt);\n\n\tmsg->len = htonl(sizeof(struct ead_msg_salt));\n\tsalt->prime = tce->index - 1;\n\tsalt->len = ts->s.len;\n\tmemcpy(salt->salt, ts->s.data, ts->s.len);\n\tmemcpy(salt->ext_salt, pw_saltbuf, MAXSALTLEN);\n\n\t*nstate = EAD_TYPE_SEND_A;\n\treturn true;\n}\n\nstatic bool\nhandle_send_a(struct ead_packet *pkt, int len, int *nstate)\n{\n\tstruct ead_msg *msg = &pkt->msg;\n\tstruct ead_msg_number *number = EAD_DATA(msg, number);\n\tlen = ntohl(msg->len) - sizeof(struct ead_msg_number);\n\n\tif (len > MAXPARAMLEN + 1)\n\t\treturn false;\n\n\tA.len = len;\n\tA.data = abuf;\n\tmemcpy(A.data, number->data, len);\n\n\tmsg = &pktbuf->msg;\n\tnumber = EAD_DATA(msg, number);\n\tmsg->len = htonl(sizeof(struct ead_msg_number) + B->len);\n\tmemcpy(number->data, B->data, B->len);\n\n\t*nstate = EAD_TYPE_SEND_AUTH;\n\treturn true;\n}\n\nstatic bool\nhandle_send_auth(struct ead_packet *pkt, int len, int *nstate)\n{\n\tstruct ead_msg *msg = &pkt->msg;\n\tstruct ead_msg_auth *auth = EAD_DATA(msg, auth);\n\n\tif (t_serververify(ts, auth->data) != 0) {\n\t\tDEBUG(2, \"Client authentication failed\\n\");\n\t\t*nstate = EAD_TYPE_SET_USERNAME;\n\t\treturn false;\n\t}\n\n\tmsg = &pktbuf->msg;\n\tauth = EAD_DATA(msg, auth);\n\tmsg->len = htonl(sizeof(struct ead_msg_auth));\n\n\tDEBUG(2, \"Client authentication successful\\n\");\n\tmemcpy(auth->data, t_serverresponse(ts), sizeof(auth->data));\n\n\t*nstate = EAD_TYPE_SEND_CMD;\n\treturn true;\n}\n\nstatic bool\nhandle_send_cmd(struct ead_packet *pkt, int len, int *nstate)\n{\n\tstruct ead_msg *msg = &pkt->msg;\n\tstruct ead_msg_cmd *cmd = EAD_ENC_DATA(msg, cmd);\n\tstruct ead_msg_cmd_data *cmddata;\n\tstruct timeval tv, to, tn;\n\tint pfd[2], fd;\n\tfd_set fds;\n\tpid_t pid;\n\tbool stream = false;\n\tint timeout;\n\tint type;\n\tint datalen;\n\n\tdatalen = ead_decrypt_message(msg) - sizeof(struct ead_msg_cmd);\n\tif (datalen <= 0)\n\t\treturn false;\n\n\ttype = ntohs(cmd->type);\n\ttimeout = ntohs(cmd->timeout);\n\n\tFD_ZERO(&fds);\n\tcmd->data[datalen] = 0;\n\tswitch(type) {\n\tcase EAD_CMD_NORMAL:\n\t\tif (pipe(pfd) < 0)\n\t\t\treturn false;\n\n\t\tfcntl(pfd[0], F_SETFL, O_NONBLOCK | fcntl(pfd[0], F_GETFL));\n\t\tchild_pending = true;\n\t\tpid = fork();\n\t\tif (pid == 0) {\n\t\t\tclose(pfd[0]);\n\t\t\tfd = open(\"/dev/null\", O_RDWR);\n\t\t\tif (fd > 0) {\n\t\t\t\tdup2(fd, 0);\n\t\t\t\tdup2(pfd[1], 1);\n\t\t\t\tdup2(pfd[1], 2);\n\t\t\t}\n\t\t\tsystem((char *)cmd->data);\n\t\t\texit(0);\n\t\t} else if (pid > 0) {\n\t\t\tclose(pfd[1]);\n\t\t\tif (!timeout)\n\t\t\t\ttimeout = EAD_CMD_TIMEOUT;\n\n\t\t\tstream = true;\n\t\t\tbreak;\n\t\t}\n\t\treturn false;\n\tcase EAD_CMD_BACKGROUND:\n\t\tpid = fork();\n\t\tif (pid == 0) {\n\t\t\t/* close stdin, stdout, stderr, replace with fd to /dev/null */\n\t\t\tfd = open(\"/dev/null\", O_RDWR);\n\t\t\tif (fd > 0) {\n\t\t\t\tdup2(fd, 0);\n\t\t\t\tdup2(fd, 1);\n\t\t\t\tdup2(fd, 2);\n\t\t\t}\n\t\t\tsystem((char *)cmd->data);\n\t\t\texit(0);\n\t\t} else if (pid > 0) {\n\t\t\tbreak;\n\t\t}\n\t\treturn false;\n\tdefault:\n\t\treturn false;\n\t}\n\n\tmsg = &pktbuf->msg;\n\tcmddata = EAD_ENC_DATA(msg, cmd_data);\n\n\tif (stream) {\n\t\tint nfds, bytes;\n\n\t\t/* send keepalive packets every 200 ms so that the client doesn't timeout */\n\t\tgettimeofday(&to, NULL);\n\t\tmemcpy(&tn, &to, sizeof(tn));\n\t\ttv.tv_usec = PCAP_TIMEOUT * 1000;\n\t\ttv.tv_sec = 0;\n\t\tdo {\n\t\t\tcmddata->done = 0;\n\t\t\tFD_SET(pfd[0], &fds);\n\t\t\tnfds = select(pfd[0] + 1, &fds, NULL, NULL, &tv);\n\t\t\tbytes = 0;\n\t\t\tif (nfds > 0) {\n\t\t\t\tbytes = read(pfd[0], cmddata->data, 1024);\n\t\t\t\tif (bytes < 0)\n\t\t\t\t\tbytes = 0;\n\t\t\t}\n\t\t\tif (!bytes && !child_pending)\n\t\t\t\tbreak;\n\t\t\tDEBUG(3, \"Sending %d bytes of console data, type=%d, timeout=%d\\n\", bytes, ntohl(msg->type), timeout);\n\t\t\tead_encrypt_message(msg, sizeof(struct ead_msg_cmd_data) + bytes);\n\t\t\tead_send_packet_clone(pkt);\n\t\t\tgettimeofday(&tn, NULL);\n\t\t} while (tn.tv_sec < to.tv_sec + timeout);\n\t\tif (child_pending) {\n\t\t\tkill(pid, SIGKILL);\n\t\t\treturn false;\n\t\t}\n\t}\n\tcmddata->done = 1;\n\tead_encrypt_message(msg, sizeof(struct ead_msg_cmd_data));\n\n\treturn true;\n}\n\n\n\nstatic void\nparse_message(struct ead_packet *pkt, int len)\n{\n\tbool (*handler)(struct ead_packet *pkt, int len, int *nstate);\n\tint min_len = sizeof(struct ead_packet);\n\tint nstate = state;\n\tint type = ntohl(pkt->msg.type);\n\n\tif ((type >= EAD_TYPE_GET_PRIME) &&\n\t\t(state != type))\n\t\treturn;\n\n\tif ((type != EAD_TYPE_PING) &&\n\t\t((ntohs(pkt->msg.sid) & EAD_INSTANCE_MASK) >>\n\t\t EAD_INSTANCE_SHIFT) != instance->id)\n\t\treturn;\n\n\tswitch(type) {\n\tcase EAD_TYPE_PING:\n\t\thandler = handle_ping;\n\t\tbreak;\n\tcase EAD_TYPE_SET_USERNAME:\n\t\thandler = handle_set_username;\n\t\tmin_len += sizeof(struct ead_msg_user);\n\t\tbreak;\n\tcase EAD_TYPE_GET_PRIME:\n\t\thandler = handle_get_prime;\n\t\tbreak;\n\tcase EAD_TYPE_SEND_A:\n\t\thandler = handle_send_a;\n\t\tmin_len += sizeof(struct ead_msg_number);\n\t\tbreak;\n\tcase EAD_TYPE_SEND_AUTH:\n\t\thandler = handle_send_auth;\n\t\tmin_len += sizeof(struct ead_msg_auth);\n\t\tbreak;\n\tcase EAD_TYPE_SEND_CMD:\n\t\thandler = handle_send_cmd;\n\t\tmin_len += sizeof(struct ead_msg_cmd) + sizeof(struct ead_msg_encrypted);\n\t\tbreak;\n\tdefault:\n\t\treturn;\n\t}\n\n\tif (len < min_len) {\n\t\tDEBUG(2, \"discarding packet: message too small\\n\");\n\t\treturn;\n\t}\n\n\tpktbuf->msg.magic = htonl(EAD_MAGIC);\n\tpktbuf->msg.type = htonl(type + 1);\n\tpktbuf->msg.nid = htons(nid);\n\tpktbuf->msg.sid = pkt->msg.sid;\n\tpktbuf->msg.len = 0;\n\n\tif (handler(pkt, len, &nstate)) {\n\t\tDEBUG(2, \"sending response to packet type %d: %d\\n\", type + 1, ntohl(pktbuf->msg.len));\n\t\t/* format response packet */\n\t\tead_send_packet_clone(pkt);\n\t}\n\tset_state(nstate);\n}\n\nstatic void\nhandle_packet(u_char *user, const struct pcap_pkthdr *h, const u_char *bytes)\n{\n\tstruct ead_packet *pkt = (struct ead_packet *) bytes;\n\n\tif (h->len < sizeof(struct ead_packet))\n\t\treturn;\n\n\tif (pkt->eh.ether_type != htons(ETHERTYPE_IP))\n\t\treturn;\n\n\tif (memcmp(pkt->eh.ether_dhost, \"\\xff\\xff\\xff\\xff\\xff\\xff\", 6) != 0)\n\t\treturn;\n\n\tif (pkt->proto != UIP_PROTO_UDP)\n\t\treturn;\n\n\tif (pkt->destport != htons(EAD_PORT))\n\t\treturn;\n\n\tif (pkt->msg.magic != htonl(EAD_MAGIC))\n\t\treturn;\n\n\tif (h->len < sizeof(struct ead_packet) + ntohl(pkt->msg.len))\n\t\treturn;\n\n\tif ((pkt->msg.nid != 0xffff) &&\n\t\t(pkt->msg.nid != htons(nid)))\n\t\treturn;\n\n\tparse_message(pkt, h->len);\n}\n\nstatic void\nead_pcap_reopen(bool first)\n{\n\tstatic char errbuf[PCAP_ERRBUF_SIZE] = \"\";\n\n\tif (pcap_fp_rx && (pcap_fp_rx != pcap_fp))\n\t\tpcap_close(pcap_fp_rx);\n\n\tif (pcap_fp)\n\t\tpcap_close(pcap_fp);\n\n\tpcap_fp_rx = NULL;\n\tdo {\n\t\tif (instance->bridge[0]) {\n\t\t\tpcap_fp_rx = ead_open_pcap(instance->bridge, errbuf, 1);\n\t\t\tpcap_fp = ead_open_pcap(instance->ifname, errbuf, 0);\n\t\t} else {\n\t\t\tpcap_fp = ead_open_pcap(instance->ifname, errbuf, 1);\n\t\t}\n\n\t\tif (!pcap_fp_rx)\n\t\t\tpcap_fp_rx = pcap_fp;\n\t\tif (first && !pcap_fp) {\n\t\t\tDEBUG(1, \"WARNING: unable to open interface '%s'\\n\", instance->ifname);\n\t\t\tfirst = false;\n\t\t}\n\t\tif (!pcap_fp)\n\t\t\tsleep(1);\n\t} while (!pcap_fp);\n\tpcap_setfilter(pcap_fp_rx, &pktfilter);\n}\n\n\nstatic void\nead_pktloop(void)\n{\n\twhile (1) {\n\t\tif (pcap_dispatch(pcap_fp_rx, 1, handle_packet, NULL) < 0) {\n\t\t\tead_pcap_reopen(false);\n\t\t\tcontinue;\n\t\t}\n\t}\n}\n\n\nstatic int\nusage(const char *prog)\n{\n\tfprintf(stderr, \"Usage: %s [<options>]\\n\"\n\t\t\"Options:\\n\"\n\t\t\"\\t-B             Run in background mode\\n\"\n\t\t\"\\t-d <device>    Set the device to listen on\\n\"\n\t\t\"\\t-D <name>      Set the name of the device visible to clients\\n\"\n\t\t\"\\t-p <file>      Set the password file for authenticating\\n\"\n\t\t\"\\t-P <file>      Write a pidfile\\n\"\n\t\t\"\\n\", prog);\n\treturn -1;\n}\n\nstatic void\nserver_handle_sigchld(int sig)\n{\n\tstruct ead_instance *in;\n\tstruct list_head *p;\n\tint pid = 0;\n\twait(&pid);\n\n\tlist_for_each(p, &instances) {\n\t\tin = list_entry(p, struct ead_instance, list);\n\t\tif (pid != in->pid)\n\t\t\tcontinue;\n\n\t\tin->pid = 0;\n\t\tbreak;\n\t}\n}\n\nstatic void\ninstance_handle_sigchld(int sig)\n{\n\tint pid = 0;\n\twait(&pid);\n\tchild_pending = false;\n}\n\nstatic void\nstart_server(struct ead_instance *i)\n{\n\tif (!nonfork) {\n\t\ti->pid = fork();\n\t\tif (i->pid != 0) {\n\t\t\tif (i->pid < 0)\n\t\t\t\ti->pid = 0;\n\t\t\treturn;\n\t\t}\n\t}\n\n\tinstance = i;\n\tsignal(SIGCHLD, instance_handle_sigchld);\n\tead_pcap_reopen(true);\n\tead_pktloop();\n\tpcap_close(pcap_fp);\n\tif (pcap_fp_rx != pcap_fp)\n\t\tpcap_close(pcap_fp_rx);\n\n\texit(0);\n}\n\n\nstatic void\nstart_servers(bool restart)\n{\n\tstruct ead_instance *in;\n\tstruct list_head *p;\n\n\tlist_for_each(p, &instances) {\n\t\tin = list_entry(p, struct ead_instance, list);\n\t\tif (in->pid > 0)\n\t\t\tcontinue;\n\n\t\tsleep(1);\n\t\tstart_server(in);\n\t}\n}\n\nstatic void\nstop_server(struct ead_instance *in, bool do_free)\n{\n\tif (in->pid > 0)\n\t\tkill(in->pid, SIGKILL);\n\tin->pid = 0;\n\tif (do_free) {\n\t\tlist_del(&in->list);\n\t\tfree(in);\n\t}\n}\n\nstatic void\nserver_handle_sigint(int sig)\n{\n\tstruct ead_instance *in;\n\tstruct list_head *p, *tmp;\n\n\tlist_for_each_safe(p, tmp, &instances) {\n\t\tin = list_entry(p, struct ead_instance, list);\n\t\tstop_server(in, true);\n\t}\n\texit(1);\n}\n\nstatic int\ncheck_bridge_port(const char *br, const char *port, void *arg)\n{\n\tstruct ead_instance *in;\n\tstruct list_head *p;\n\n\tlist_for_each(p, &instances) {\n\t\tin = list_entry(p, struct ead_instance, list);\n\n\t\tif (strcmp(in->ifname, port) != 0)\n\t\t\tcontinue;\n\n\t\tin->br_check = true;\n\t\tif (strcmp(in->bridge, br) == 0)\n\t\t\tbreak;\n\n\t\tstrncpy(in->bridge, br, sizeof(in->bridge));\n\t\tDEBUG(2, \"assigning port %s to bridge %s\\n\", in->ifname, in->bridge);\n\t\tstop_server(in, false);\n\t}\n\treturn 0;\n}\n\nstatic int\ncheck_bridge(const char *name, void *arg)\n{\n\tbr_foreach_port(name, check_bridge_port, arg);\n\treturn 0;\n}\n\nstatic void\ncheck_all_interfaces(void)\n{\n\tstruct ead_instance *in;\n\tstruct list_head *p;\n\n\tbr_foreach_bridge(check_bridge, NULL);\n\n\t/* look for interfaces that are no longer part of a bridge */\n\tlist_for_each(p, &instances) {\n\t\tin = list_entry(p, struct ead_instance, list);\n\n\t\tif (in->br_check) {\n\t\t\tin->br_check = false;\n\t\t} else if (in->bridge[0]) {\n\t\t\tDEBUG(2, \"removing port %s from bridge %s\\n\", in->ifname, in->bridge);\n\t\t\tin->bridge[0] = 0;\n\t\t\tstop_server(in, false);\n\t\t}\n\t}\n}\n\n\nint main(int argc, char **argv)\n{\n\tstruct ead_instance *in;\n\tstruct timeval tv;\n\tconst char *pidfile = NULL;\n\tbool background = false;\n\tint n_iface = 0;\n\tint fd, ch;\n\n\tif (argc == 1)\n\t\treturn usage(argv[0]);\n\n\tINIT_LIST_HEAD(&instances);\n\twhile ((ch = getopt(argc, argv, \"Bd:D:fhp:P:\")) != -1) {\n\t\tswitch(ch) {\n\t\tcase 'B':\n\t\t\tbackground = true;\n\t\t\tbreak;\n\t\tcase 'f':\n\t\t\tnonfork = true;\n\t\t\tbreak;\n\t\tcase 'h':\n\t\t\treturn usage(argv[0]);\n\t\tcase 'd':\n\t\t\tin = malloc(sizeof(struct ead_instance));\n\t\t\tmemset(in, 0, sizeof(struct ead_instance));\n\t\t\tINIT_LIST_HEAD(&in->list);\n\t\t\tstrncpy(in->ifname, optarg, sizeof(in->ifname) - 1);\n\t\t\tlist_add(&in->list, &instances);\n\t\t\tin->id = n_iface++;\n\t\t\tbreak;\n\t\tcase 'D':\n\t\t\tdev_name = optarg;\n\t\t\tbreak;\n\t\tcase 'p':\n\t\t\tpasswd_file = optarg;\n\t\t\tbreak;\n\t\tcase 'P':\n\t\t\tpidfile = optarg;\n\t\t\tbreak;\n\t\t}\n\t}\n\tsignal(SIGCHLD, server_handle_sigchld);\n\tsignal(SIGINT, server_handle_sigint);\n\tsignal(SIGTERM, server_handle_sigint);\n\tsignal(SIGKILL, server_handle_sigint);\n\n\tif (!n_iface) {\n\t\tfprintf(stderr, \"Error: ead needs at least one interface\\n\");\n\t\treturn -1;\n\t}\n\n\tif (background) {\n\t\tif (fork() > 0)\n\t\t\texit(0);\n\n\t\tfd = open(\"/dev/null\", O_RDWR);\n\t\tdup2(fd, 0);\n\t\tdup2(fd, 1);\n\t\tdup2(fd, 2);\n\t}\n\n\tif (pidfile) {\n\t\tchar pid[8];\n\t\tint len;\n\n\t\tunlink(pidfile);\n\t\tfd = open(pidfile, O_CREAT|O_WRONLY|O_EXCL, 0644);\n\t\tif (fd > 0) {\n\t\t\tlen = sprintf(pid, \"%d\\n\", getpid());\n\t\t\twrite(fd, pid, len);\n\t\t\tclose(fd);\n\t\t}\n\t}\n\n\t/* randomize the mac address */\n\tget_random_bytes(ethmac + 3, 3);\n\tnid = *(((u16_t *) ethmac) + 2);\n\n\tstart_servers(false);\n\tbr_init();\n\ttv.tv_sec = 1;\n\ttv.tv_usec = 0;\n\twhile (1) {\n\t\tcheck_all_interfaces();\n\t\tstart_servers(true);\n\t\tsleep(1);\n\t}\n\tbr_shutdown();\n\n\treturn 0;\n}\n"
  },
  {
    "path": "package/network/services/ead/src/ead.h",
    "content": "/*\n * Copyright (C) 2008 Felix Fietkau <nbd@nbd.name>\n *\n * This program is free software; you can redistribute it and/or modify\n * it under the terms of the GNU General Public License version 2\n * as published by the Free Software Foundation\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n * GNU General Public License for more details.\n */\n\n#ifndef __EAD_H\n#define __EAD_H\n\n#define EAD_DEBUGLEVEL\t1\n\n#include <stdint.h>\n#include <stddef.h>\n\n#ifndef MAXSALTLEN\n#define MAXSALTLEN 32\n#endif\n\n#define EAD_PORT\t56026UL\n#define EAD_MAGIC\t3671771902UL\n#define EAD_CMD_TIMEOUT\t10\n\n#define EAD_MAX_IV_INCR\t128\n\n/* request/response types */\n/* response id == request id + 1 */\nenum ead_type {\n\tEAD_TYPE_PING,\n\tEAD_TYPE_PONG,\n\n\tEAD_TYPE_SET_USERNAME,\n\tEAD_TYPE_ACK_USERNAME,\n\n\tEAD_TYPE_GET_PRIME,\n\tEAD_TYPE_PRIME,\n\n\tEAD_TYPE_SEND_A,\n\tEAD_TYPE_SEND_B,\n\n\tEAD_TYPE_SEND_AUTH,\n\tEAD_TYPE_DONE_AUTH,\n\n\tEAD_TYPE_SEND_CMD,\n\tEAD_TYPE_RESULT_CMD,\n\n\tEAD_TYPE_LAST\n};\n\nenum ead_auth_type {\n\tEAD_AUTH_DEFAULT,\n\tEAD_AUTH_MD5\n};\n\nenum ead_cmd_type {\n\tEAD_CMD_NORMAL,\n\tEAD_CMD_BACKGROUND,\n\tEAD_CMD_LAST\n};\n\nstruct ead_msg_pong {\n\tuint16_t auth_type;\n\tchar name[];\n} __attribute__((packed));\n\nstruct ead_msg_number {\n\tuint8_t id;\n\tunsigned char data[];\n} __attribute__((packed));\n\nstruct ead_msg_salt {\n\tuint8_t prime;\n\tuint8_t len;\n\tunsigned char salt[MAXSALTLEN];\n\tunsigned char ext_salt[MAXSALTLEN];\n} __attribute__((packed));\n\nstruct ead_msg_user {\n\tchar username[32];\n} __attribute__((packed));\n\nstruct ead_msg_auth {\n\tunsigned char data[20];\n} __attribute__((packed));\n\nstruct ead_msg_cmd {\n\tuint8_t type;\n\tuint16_t timeout;\n\tunsigned char data[];\n} __attribute__((packed));\n\nstruct ead_msg_cmd_data {\n\tuint8_t done;\n\tunsigned char data[];\n} __attribute__((packed));\n\nstruct ead_msg_encrypted {\n\tuint32_t hash[5];\n\tuint32_t iv;\n\tuint8_t pad;\n\tunion {\n\t\tstruct ead_msg_cmd cmd;\n\t\tstruct ead_msg_cmd_data cmd_data;\n\t} data[];\n} __attribute__((packed));\n\n\n#define EAD_DATA(_msg, _type) (&((_msg)->data[0]._type))\n#define EAD_ENC_DATA(_msg, _type) (&((_msg)->data[0].enc.data[0]._type))\n\n/* for ead_msg::sid */\n#define EAD_INSTANCE_MASK\t0xf000\n#define EAD_INSTANCE_SHIFT\t12\n\nstruct ead_msg {\n\tuint32_t magic;\n\tuint32_t len;\n\tuint32_t type;\n\tuint16_t nid; /* node id */\n\tuint16_t sid; /* session id */\n\tuint32_t ip; /* source ip for responses from the server */\n\tunion {\n\t\tstruct ead_msg_pong pong;\n\t\tstruct ead_msg_user user;\n\t\tstruct ead_msg_number number;\n\t\tstruct ead_msg_auth auth;\n\t\tstruct ead_msg_salt salt;\n\t\tstruct ead_msg_encrypted enc;\n\t} data[];\n} __attribute__((packed));\n\n\n#endif\n"
  },
  {
    "path": "package/network/services/ead/src/filter.c",
    "content": "/* precompiled expression: udp and dst port 56026 */\n\nstatic struct bpf_insn pktfilter_insns[] = {\n\t{ .code = 0x0028, .jt = 0x00, .jf = 0x00, .k = 0x0000000c },\n\t{ .code = 0x0015, .jt = 0x00, .jf = 0x04, .k = 0x000086dd },\n\t{ .code = 0x0030, .jt = 0x00, .jf = 0x00, .k = 0x00000014 },\n\t{ .code = 0x0015, .jt = 0x00, .jf = 0x0b, .k = 0x00000011 },\n\t{ .code = 0x0028, .jt = 0x00, .jf = 0x00, .k = 0x00000038 },\n\t{ .code = 0x0015, .jt = 0x08, .jf = 0x09, .k = 0x0000dada },\n\t{ .code = 0x0015, .jt = 0x00, .jf = 0x08, .k = 0x00000800 },\n\t{ .code = 0x0030, .jt = 0x00, .jf = 0x00, .k = 0x00000017 },\n\t{ .code = 0x0015, .jt = 0x00, .jf = 0x06, .k = 0x00000011 },\n\t{ .code = 0x0028, .jt = 0x00, .jf = 0x00, .k = 0x00000014 },\n\t{ .code = 0x0045, .jt = 0x04, .jf = 0x00, .k = 0x00001fff },\n\t{ .code = 0x00b1, .jt = 0x00, .jf = 0x00, .k = 0x0000000e },\n\t{ .code = 0x0048, .jt = 0x00, .jf = 0x00, .k = 0x00000010 },\n\t{ .code = 0x0015, .jt = 0x00, .jf = 0x01, .k = 0x0000dada },\n\t{ .code = 0x0006, .jt = 0x00, .jf = 0x00, .k = 0x000005dc },\n\t{ .code = 0x0006, .jt = 0x00, .jf = 0x00, .k = 0x00000000 },\n};\n\nstatic struct bpf_program pktfilter = {\n\t.bf_len = 16,\n\t.bf_insns = pktfilter_insns,\n};\n"
  },
  {
    "path": "package/network/services/ead/src/libbridge.h",
    "content": "/*\n * Copyright (C) 2000 Lennert Buytenhek\n *\n * This program is free software; you can redistribute it and/or\n * modify it under the terms of the GNU General Public License as\n * published by the Free Software Foundation; either version 2 of the\n * License, or (at your option) any later version.\n *\n * This program is distributed in the hope that it will be useful, but\n * WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\n * General Public License for more details.\n *\n * You should have received a copy of the GNU General Public License\n * along with this program; if not, write to the Free Software\n * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.\n */\n\n#ifndef _LIBBRIDGE_H\n#define _LIBBRIDGE_H\n\n#ifdef linux\n\nint br_init(void);\nvoid br_shutdown(void);\n\nint br_foreach_port(const char *brname,\n\t\t    int (*iterator)(const char *br, const char *port, void *arg),\n\t\t    void *arg);\n\nint br_foreach_bridge(int (*iterator)(const char *, void *), void *arg);\n\n#else\n\nstatic inline int br_init(void)\n{\n\treturn 0;\n}\n\nstatic inline void br_shutdown(void)\n{\n}\n\nstatic inline int\nbr_foreach_port(const char *brname,\n\t\t    int (*iterator)(const char *br, const char *port, void *arg),\n\t\t    void *arg)\n{\n\treturn 0;\n}\n\nstatic inline int\nbr_foreach_bridge(int (*iterator)(const char *, void *), void *arg)\n{\n\treturn 0;\n}\n\n#endif\n\n#endif\n"
  },
  {
    "path": "package/network/services/ead/src/libbridge_init.c",
    "content": "/*\n * Copyright (C) 2000 Lennert Buytenhek\n *\n * This program is free software; you can redistribute it and/or\n * modify it under the terms of the GNU General Public License as\n * published by the Free Software Foundation; either version 2 of the\n * License, or (at your option) any later version.\n *\n * This program is distributed in the hope that it will be useful, but\n * WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\n * General Public License for more details.\n *\n * You should have received a copy of the GNU General Public License\n * along with this program; if not, write to the Free Software\n * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.\n */\n\n#ifdef linux\n\n#include <stdio.h>\n#include <stdlib.h>\n#include <unistd.h>\n#include <errno.h>\n#include <string.h>\n#include <dirent.h>\n#include <sys/types.h>\n#include <sys/stat.h>\n#include <sys/socket.h>\n#include <linux/if.h>\n#include <linux/in6.h>\n#include <linux/if_bridge.h>\n\n#include \"libbridge.h\"\n#include \"libbridge_private.h\"\n\nstatic int br_socket_fd = -1;\n\nint br_init(void)\n{\n\tif ((br_socket_fd = socket(AF_LOCAL, SOCK_STREAM, 0)) < 0)\n\t\treturn errno;\n\treturn 0;\n}\n\nvoid br_shutdown(void)\n{\n\tclose(br_socket_fd);\n\tbr_socket_fd = -1;\n}\n\n/* If /sys/class/net/XXX/bridge exists then it must be a bridge */\nstatic int isbridge(const struct dirent *entry)\n{\n\tchar path[SYSFS_PATH_MAX];\n\tstruct stat st;\n\n\tsnprintf(path, SYSFS_PATH_MAX, SYSFS_CLASS_NET \"%s/bridge\", entry->d_name);\n\treturn stat(path, &st) == 0 && S_ISDIR(st.st_mode);\n}\n\n/*\n * New interface uses sysfs to find bridges\n */\nstatic int new_foreach_bridge(int (*iterator)(const char *name, void *),\n\t\t\t      void *arg)\n{\n\tstruct dirent **namelist;\n\tint i, count = 0;\n\n\tcount = scandir(SYSFS_CLASS_NET, &namelist, isbridge, alphasort);\n\tif (count < 0)\n\t\treturn -1;\n\n\tfor (i = 0; i < count; i++) {\n\t\tif (iterator(namelist[i]->d_name, arg))\n\t\t\tbreak;\n\t}\n\n\tfor (i = 0; i < count; i++)\n\t\tfree(namelist[i]);\n\tfree(namelist);\n\n\treturn count;\n}\n\n/*\n * Go over all bridges and call iterator function.\n * if iterator returns non-zero then stop.\n */\nint br_foreach_bridge(int (*iterator)(const char *, void *), void *arg)\n{\n\treturn new_foreach_bridge(iterator, arg);\n}\n\n/*\n * Iterate over all ports in bridge (using sysfs).\n */\nint br_foreach_port(const char *brname,\n\t\t    int (*iterator)(const char *br, const char *port, void *arg),\n\t\t    void *arg)\n{\n\tint i, count;\n\tstruct dirent **namelist;\n\tchar path[SYSFS_PATH_MAX];\n\n\tsnprintf(path, SYSFS_PATH_MAX, SYSFS_CLASS_NET \"%s/brif\", brname);\n\tcount = scandir(path, &namelist, 0, alphasort);\n\n\tfor (i = 0; i < count; i++) {\n\t\tif (namelist[i]->d_name[0] == '.'\n\t\t    && (namelist[i]->d_name[1] == '\\0'\n\t\t\t|| (namelist[i]->d_name[1] == '.'\n\t\t\t    && namelist[i]->d_name[2] == '\\0')))\n\t\t\tcontinue;\n\n\t\tif (iterator(brname, namelist[i]->d_name, arg))\n\t\t\tbreak;\n\t}\n\tfor (i = 0; i < count; i++)\n\t\tfree(namelist[i]);\n\tfree(namelist);\n\n\treturn count;\n}\n\n#endif\n"
  },
  {
    "path": "package/network/services/ead/src/libbridge_private.h",
    "content": "/*\n * Copyright (C) 2000 Lennert Buytenhek\n *\n * This program is free software; you can redistribute it and/or\n * modify it under the terms of the GNU General Public License as\n * published by the Free Software Foundation; either version 2 of the\n * License, or (at your option) any later version.\n *\n * This program is distributed in the hope that it will be useful, but\n * WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\n * General Public License for more details.\n *\n * You should have received a copy of the GNU General Public License\n * along with this program; if not, write to the Free Software\n * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.\n */\n\n#ifndef _LIBBRIDGE_PRIVATE_H\n#define _LIBBRIDGE_PRIVATE_H\n\n#include <linux/sockios.h>\n#include <sys/time.h>\n#include <sys/ioctl.h>\n#include <linux/if_bridge.h>\n\n#define MAX_BRIDGES\t1024\n#define MAX_PORTS\t1024\n\n#define SYSFS_CLASS_NET \"/sys/class/net/\"\n#define SYSFS_PATH_MAX\t256\n\n#define dprintf(fmt,arg...)\n\n#endif\n"
  },
  {
    "path": "package/network/services/ead/src/list.h",
    "content": "/* GPL v2, adapted from the Linux kernel */\n#ifndef _LINUX_LIST_H\n#define _LINUX_LIST_H\n\n#include <stddef.h>\n/**\n * container_of - cast a member of a structure out to the containing structure\n * @ptr:\tthe pointer to the member.\n * @type:\tthe type of the container struct this is embedded in.\n * @member:\tthe name of the member within the struct.\n *\n */\n#ifndef container_of\n#define container_of(ptr, type, member) (\t\t\t\\\n\t(type *)( (char *)ptr - offsetof(type,member) ))\n#endif\n\n\n/*\n * Simple doubly linked list implementation.\n *\n * Some of the internal functions (\"__xxx\") are useful when\n * manipulating whole lists rather than single entries, as\n * sometimes we already know the next/prev entries and we can\n * generate better code by using them directly rather than\n * using the generic single-entry routines.\n */\n\nstruct list_head {\n\tstruct list_head *next, *prev;\n};\n\n#define LIST_HEAD_INIT(name) { &(name), &(name) }\n\n#define LIST_HEAD(name) \\\n\tstruct list_head name = LIST_HEAD_INIT(name)\n\nstatic inline void INIT_LIST_HEAD(struct list_head *list)\n{\n\tlist->next = list;\n\tlist->prev = list;\n}\n\n/*\n * Insert a new entry between two known consecutive entries.\n *\n * This is only for internal list manipulation where we know\n * the prev/next entries already!\n */\nstatic inline void __list_add(struct list_head *new,\n\t\t\t      struct list_head *prev,\n\t\t\t      struct list_head *next)\n{\n\tnext->prev = new;\n\tnew->next = next;\n\tnew->prev = prev;\n\tprev->next = new;\n}\n\n/**\n * list_add - add a new entry\n * @new: new entry to be added\n * @head: list head to add it after\n *\n * Insert a new entry after the specified head.\n * This is good for implementing stacks.\n */\nstatic inline void list_add(struct list_head *new, struct list_head *head)\n{\n\t__list_add(new, head, head->next);\n}\n\n\n/**\n * list_add_tail - add a new entry\n * @new: new entry to be added\n * @head: list head to add it before\n *\n * Insert a new entry before the specified head.\n * This is useful for implementing queues.\n */\nstatic inline void list_add_tail(struct list_head *new, struct list_head *head)\n{\n\t__list_add(new, head->prev, head);\n}\n\n\n/*\n * Delete a list entry by making the prev/next entries\n * point to each other.\n *\n * This is only for internal list manipulation where we know\n * the prev/next entries already!\n */\nstatic inline void __list_del(struct list_head * prev, struct list_head * next)\n{\n\tnext->prev = prev;\n\tprev->next = next;\n}\n\n/**\n * list_del - deletes entry from list.\n * @entry: the element to delete from the list.\n * Note: list_empty() on entry does not return true after this, the entry is\n * in an undefined state.\n */\nstatic inline void list_del(struct list_head *entry)\n{\n\t__list_del(entry->prev, entry->next);\n\tentry->next = NULL;\n\tentry->prev = NULL;\n}\n\n/**\n * list_replace - replace old entry by new one\n * @old : the element to be replaced\n * @new : the new element to insert\n *\n * If @old was empty, it will be overwritten.\n */\nstatic inline void list_replace(struct list_head *old,\n\t\t\t\tstruct list_head *new)\n{\n\tnew->next = old->next;\n\tnew->next->prev = new;\n\tnew->prev = old->prev;\n\tnew->prev->next = new;\n}\n\nstatic inline void list_replace_init(struct list_head *old,\n\t\t\t\t\tstruct list_head *new)\n{\n\tlist_replace(old, new);\n\tINIT_LIST_HEAD(old);\n}\n\n/**\n * list_del_init - deletes entry from list and reinitialize it.\n * @entry: the element to delete from the list.\n */\nstatic inline void list_del_init(struct list_head *entry)\n{\n\t__list_del(entry->prev, entry->next);\n\tINIT_LIST_HEAD(entry);\n}\n\n/**\n * list_move - delete from one list and add as another's head\n * @list: the entry to move\n * @head: the head that will precede our entry\n */\nstatic inline void list_move(struct list_head *list, struct list_head *head)\n{\n\t__list_del(list->prev, list->next);\n\tlist_add(list, head);\n}\n\n/**\n * list_move_tail - delete from one list and add as another's tail\n * @list: the entry to move\n * @head: the head that will follow our entry\n */\nstatic inline void list_move_tail(struct list_head *list,\n\t\t\t\t  struct list_head *head)\n{\n\t__list_del(list->prev, list->next);\n\tlist_add_tail(list, head);\n}\n\n/**\n * list_is_last - tests whether @list is the last entry in list @head\n * @list: the entry to test\n * @head: the head of the list\n */\nstatic inline int list_is_last(const struct list_head *list,\n\t\t\t\tconst struct list_head *head)\n{\n\treturn list->next == head;\n}\n\n/**\n * list_empty - tests whether a list is empty\n * @head: the list to test.\n */\nstatic inline int list_empty(const struct list_head *head)\n{\n\treturn head->next == head;\n}\n\n/**\n * list_empty_careful - tests whether a list is empty and not being modified\n * @head: the list to test\n *\n * Description:\n * tests whether a list is empty _and_ checks that no other CPU might be\n * in the process of modifying either member (next or prev)\n *\n * NOTE: using list_empty_careful() without synchronization\n * can only be safe if the only activity that can happen\n * to the list entry is list_del_init(). Eg. it cannot be used\n * if another CPU could re-list_add() it.\n */\nstatic inline int list_empty_careful(const struct list_head *head)\n{\n\tstruct list_head *next = head->next;\n\treturn (next == head) && (next == head->prev);\n}\n\nstatic inline void __list_splice(struct list_head *list,\n\t\t\t\t struct list_head *head)\n{\n\tstruct list_head *first = list->next;\n\tstruct list_head *last = list->prev;\n\tstruct list_head *at = head->next;\n\n\tfirst->prev = head;\n\thead->next = first;\n\n\tlast->next = at;\n\tat->prev = last;\n}\n\n/**\n * list_splice - join two lists\n * @list: the new list to add.\n * @head: the place to add it in the first list.\n */\nstatic inline void list_splice(struct list_head *list, struct list_head *head)\n{\n\tif (!list_empty(list))\n\t\t__list_splice(list, head);\n}\n\n/**\n * list_splice_init - join two lists and reinitialise the emptied list.\n * @list: the new list to add.\n * @head: the place to add it in the first list.\n *\n * The list at @list is reinitialised\n */\nstatic inline void list_splice_init(struct list_head *list,\n\t\t\t\t    struct list_head *head)\n{\n\tif (!list_empty(list)) {\n\t\t__list_splice(list, head);\n\t\tINIT_LIST_HEAD(list);\n\t}\n}\n\n/**\n * list_entry - get the struct for this entry\n * @ptr:\tthe &struct list_head pointer.\n * @type:\tthe type of the struct this is embedded in.\n * @member:\tthe name of the list_struct within the struct.\n */\n#define list_entry(ptr, type, member) \\\n\tcontainer_of(ptr, type, member)\n\n/**\n * list_first_entry - get the first element from a list\n * @ptr:\tthe list head to take the element from.\n * @type:\tthe type of the struct this is embedded in.\n * @member:\tthe name of the list_struct within the struct.\n *\n * Note, that list is expected to be not empty.\n */\n#define list_first_entry(ptr, type, member) \\\n\tlist_entry((ptr)->next, type, member)\n\n/**\n * list_for_each\t-\titerate over a list\n * @pos:\tthe &struct list_head to use as a loop cursor.\n * @head:\tthe head for your list.\n */\n#define list_for_each(pos, head) \\\n\tfor (pos = (head)->next; pos != (head); \\\n        \tpos = pos->next)\n\n/**\n * __list_for_each\t-\titerate over a list\n * @pos:\tthe &struct list_head to use as a loop cursor.\n * @head:\tthe head for your list.\n *\n * This variant differs from list_for_each() in that it's the\n * simplest possible list iteration code, no prefetching is done.\n * Use this for code that knows the list to be very short (empty\n * or 1 entry) most of the time.\n */\n#define __list_for_each(pos, head) \\\n\tfor (pos = (head)->next; pos != (head); pos = pos->next)\n\n/**\n * list_for_each_prev\t-\titerate over a list backwards\n * @pos:\tthe &struct list_head to use as a loop cursor.\n * @head:\tthe head for your list.\n */\n#define list_for_each_prev(pos, head) \\\n\tfor (pos = (head)->prev; pos != (head); \\\n        \tpos = pos->prev)\n\n/**\n * list_for_each_safe - iterate over a list safe against removal of list entry\n * @pos:\tthe &struct list_head to use as a loop cursor.\n * @n:\t\tanother &struct list_head to use as temporary storage\n * @head:\tthe head for your list.\n */\n#define list_for_each_safe(pos, n, head) \\\n\tfor (pos = (head)->next, n = pos->next; pos != (head); \\\n\t\tpos = n, n = pos->next)\n\n/**\n * list_for_each_prev_safe - iterate over a list backwards safe against removal of list entry\n * @pos:\tthe &struct list_head to use as a loop cursor.\n * @n:\t\tanother &struct list_head to use as temporary storage\n * @head:\tthe head for your list.\n */\n#define list_for_each_prev_safe(pos, n, head) \\\n\tfor (pos = (head)->prev, n = pos->prev; \\\n\t     pos != (head); \\\n\t     pos = n, n = pos->prev)\n\n/**\n * list_for_each_entry\t-\titerate over list of given type\n * @pos:\tthe type * to use as a loop cursor.\n * @head:\tthe head for your list.\n * @member:\tthe name of the list_struct within the struct.\n */\n#define list_for_each_entry(pos, head, member)\t\t\t\t\\\n\tfor (pos = list_entry((head)->next, typeof(*pos), member);\t\\\n\t     &pos->member != (head); \t\\\n\t     pos = list_entry(pos->member.next, typeof(*pos), member))\n\n/**\n * list_for_each_entry_reverse - iterate backwards over list of given type.\n * @pos:\tthe type * to use as a loop cursor.\n * @head:\tthe head for your list.\n * @member:\tthe name of the list_struct within the struct.\n */\n#define list_for_each_entry_reverse(pos, head, member)\t\t\t\\\n\tfor (pos = list_entry((head)->prev, typeof(*pos), member);\t\\\n\t     &pos->member != (head); \t\\\n\t     pos = list_entry(pos->member.prev, typeof(*pos), member))\n\n/**\n * list_prepare_entry - prepare a pos entry for use in list_for_each_entry_continue()\n * @pos:\tthe type * to use as a start point\n * @head:\tthe head of the list\n * @member:\tthe name of the list_struct within the struct.\n *\n * Prepares a pos entry for use as a start point in list_for_each_entry_continue().\n */\n#define list_prepare_entry(pos, head, member) \\\n\t((pos) ? : list_entry(head, typeof(*pos), member))\n\n/**\n * list_for_each_entry_continue - continue iteration over list of given type\n * @pos:\tthe type * to use as a loop cursor.\n * @head:\tthe head for your list.\n * @member:\tthe name of the list_struct within the struct.\n *\n * Continue to iterate over list of given type, continuing after\n * the current position.\n */\n#define list_for_each_entry_continue(pos, head, member) \t\t\\\n\tfor (pos = list_entry(pos->member.next, typeof(*pos), member);\t\\\n\t     &pos->member != (head);\t\\\n\t     pos = list_entry(pos->member.next, typeof(*pos), member))\n\n/**\n * list_for_each_entry_continue_reverse - iterate backwards from the given point\n * @pos:\tthe type * to use as a loop cursor.\n * @head:\tthe head for your list.\n * @member:\tthe name of the list_struct within the struct.\n *\n * Start to iterate over list of given type backwards, continuing after\n * the current position.\n */\n#define list_for_each_entry_continue_reverse(pos, head, member)\t\t\\\n\tfor (pos = list_entry(pos->member.prev, typeof(*pos), member);\t\\\n\t     &pos->member != (head);\t\\\n\t     pos = list_entry(pos->member.prev, typeof(*pos), member))\n\n/**\n * list_for_each_entry_from - iterate over list of given type from the current point\n * @pos:\tthe type * to use as a loop cursor.\n * @head:\tthe head for your list.\n * @member:\tthe name of the list_struct within the struct.\n *\n * Iterate over list of given type, continuing from current position.\n */\n#define list_for_each_entry_from(pos, head, member) \t\t\t\\\n\tfor (; &pos->member != (head);\t\\\n\t     pos = list_entry(pos->member.next, typeof(*pos), member))\n\n/**\n * list_for_each_entry_safe - iterate over list of given type safe against removal of list entry\n * @pos:\tthe type * to use as a loop cursor.\n * @n:\t\tanother type * to use as temporary storage\n * @head:\tthe head for your list.\n * @member:\tthe name of the list_struct within the struct.\n */\n#define list_for_each_entry_safe(pos, n, head, member)\t\t\t\\\n\tfor (pos = list_entry((head)->next, typeof(*pos), member),\t\\\n\t\tn = list_entry(pos->member.next, typeof(*pos), member);\t\\\n\t     &pos->member != (head); \t\t\t\t\t\\\n\t     pos = n, n = list_entry(n->member.next, typeof(*n), member))\n\n/**\n * list_for_each_entry_safe_continue\n * @pos:\tthe type * to use as a loop cursor.\n * @n:\t\tanother type * to use as temporary storage\n * @head:\tthe head for your list.\n * @member:\tthe name of the list_struct within the struct.\n *\n * Iterate over list of given type, continuing after current point,\n * safe against removal of list entry.\n */\n#define list_for_each_entry_safe_continue(pos, n, head, member) \t\t\\\n\tfor (pos = list_entry(pos->member.next, typeof(*pos), member), \t\t\\\n\t\tn = list_entry(pos->member.next, typeof(*pos), member);\t\t\\\n\t     &pos->member != (head);\t\t\t\t\t\t\\\n\t     pos = n, n = list_entry(n->member.next, typeof(*n), member))\n\n/**\n * list_for_each_entry_safe_from\n * @pos:\tthe type * to use as a loop cursor.\n * @n:\t\tanother type * to use as temporary storage\n * @head:\tthe head for your list.\n * @member:\tthe name of the list_struct within the struct.\n *\n * Iterate over list of given type from current point, safe against\n * removal of list entry.\n */\n#define list_for_each_entry_safe_from(pos, n, head, member) \t\t\t\\\n\tfor (n = list_entry(pos->member.next, typeof(*pos), member);\t\t\\\n\t     &pos->member != (head);\t\t\t\t\t\t\\\n\t     pos = n, n = list_entry(n->member.next, typeof(*n), member))\n\n/**\n * list_for_each_entry_safe_reverse\n * @pos:\tthe type * to use as a loop cursor.\n * @n:\t\tanother type * to use as temporary storage\n * @head:\tthe head for your list.\n * @member:\tthe name of the list_struct within the struct.\n *\n * Iterate backwards over list of given type, safe against removal\n * of list entry.\n */\n#define list_for_each_entry_safe_reverse(pos, n, head, member)\t\t\\\n\tfor (pos = list_entry((head)->prev, typeof(*pos), member),\t\\\n\t\tn = list_entry(pos->member.prev, typeof(*pos), member);\t\\\n\t     &pos->member != (head); \t\t\t\t\t\\\n\t     pos = n, n = list_entry(n->member.prev, typeof(*n), member))\n\n/*\n * Double linked lists with a single pointer list head.\n * Mostly useful for hash tables where the two pointer list head is\n * too wasteful.\n * You lose the ability to access the tail in O(1).\n */\n\nstruct hlist_head {\n\tstruct hlist_node *first;\n};\n\nstruct hlist_node {\n\tstruct hlist_node *next, **pprev;\n};\n\n#define HLIST_HEAD_INIT { .first = NULL }\n#define HLIST_HEAD(name) struct hlist_head name = {  .first = NULL }\n#define INIT_HLIST_HEAD(ptr) ((ptr)->first = NULL)\nstatic inline void INIT_HLIST_NODE(struct hlist_node *h)\n{\n\th->next = NULL;\n\th->pprev = NULL;\n}\n\nstatic inline int hlist_unhashed(const struct hlist_node *h)\n{\n\treturn !h->pprev;\n}\n\nstatic inline int hlist_empty(const struct hlist_head *h)\n{\n\treturn !h->first;\n}\n\nstatic inline void __hlist_del(struct hlist_node *n)\n{\n\tstruct hlist_node *next = n->next;\n\tstruct hlist_node **pprev = n->pprev;\n\t*pprev = next;\n\tif (next)\n\t\tnext->pprev = pprev;\n}\n\nstatic inline void hlist_del(struct hlist_node *n)\n{\n\t__hlist_del(n);\n\tn->next = NULL;\n\tn->pprev = NULL;\n}\n\nstatic inline void hlist_del_init(struct hlist_node *n)\n{\n\tif (!hlist_unhashed(n)) {\n\t\t__hlist_del(n);\n\t\tINIT_HLIST_NODE(n);\n\t}\n}\n\n\nstatic inline void hlist_add_head(struct hlist_node *n, struct hlist_head *h)\n{\n\tstruct hlist_node *first = h->first;\n\tn->next = first;\n\tif (first)\n\t\tfirst->pprev = &n->next;\n\th->first = n;\n\tn->pprev = &h->first;\n}\n\n\n/* next must be != NULL */\nstatic inline void hlist_add_before(struct hlist_node *n,\n\t\t\t\t\tstruct hlist_node *next)\n{\n\tn->pprev = next->pprev;\n\tn->next = next;\n\tnext->pprev = &n->next;\n\t*(n->pprev) = n;\n}\n\nstatic inline void hlist_add_after(struct hlist_node *n,\n\t\t\t\t\tstruct hlist_node *next)\n{\n\tnext->next = n->next;\n\tn->next = next;\n\tnext->pprev = &n->next;\n\n\tif(next->next)\n\t\tnext->next->pprev  = &next->next;\n}\n\n#define hlist_entry(ptr, type, member) container_of(ptr,type,member)\n\n#define hlist_for_each(pos, head) \\\n\tfor (pos = (head)->first; pos; pos = pos->next)\n\n#define hlist_for_each_safe(pos, n, head) \\\n\tfor (pos = (head)->first; pos; pos = n)\n\n/**\n * hlist_for_each_entry\t- iterate over list of given type\n * @tpos:\tthe type * to use as a loop cursor.\n * @pos:\tthe &struct hlist_node to use as a loop cursor.\n * @head:\tthe head for your list.\n * @member:\tthe name of the hlist_node within the struct.\n */\n#define hlist_for_each_entry(tpos, pos, head, member)\t\t\t \\\n\tfor (pos = (head)->first; pos &&\t\t\t\t \\\n\t\t({ tpos = hlist_entry(pos, typeof(*tpos), member); 1;}); \\\n\t     pos = pos->next)\n\n/**\n * hlist_for_each_entry_continue - iterate over a hlist continuing after current point\n * @tpos:\tthe type * to use as a loop cursor.\n * @pos:\tthe &struct hlist_node to use as a loop cursor.\n * @member:\tthe name of the hlist_node within the struct.\n */\n#define hlist_for_each_entry_continue(tpos, pos, member)\t\t\\\n\tfor (pos = (pos)->next; pos &&\t\t\t\t\t\\\n\t     ({ tpos = hlist_entry(pos, typeof(*tpos), member); 1;});   \\\n\t     pos = pos->next)\n\n/**\n * hlist_for_each_entry_from - iterate over a hlist continuing from current point\n * @tpos:\tthe type * to use as a loop cursor.\n * @pos:\tthe &struct hlist_node to use as a loop cursor.\n * @member:\tthe name of the hlist_node within the struct.\n */\n#define hlist_for_each_entry_from(tpos, pos, member)\t\t\t \\\n\tfor (; pos &&\t\t\t \\\n\t\t({ tpos = hlist_entry(pos, typeof(*tpos), member); 1;}); \\\n\t     pos = pos->next)\n\n/**\n * hlist_for_each_entry_safe - iterate over list of given type safe against removal of list entry\n * @tpos:\tthe type * to use as a loop cursor.\n * @pos:\tthe &struct hlist_node to use as a loop cursor.\n * @n:\t\tanother &struct hlist_node to use as temporary storage\n * @head:\tthe head for your list.\n * @member:\tthe name of the hlist_node within the struct.\n */\n#define hlist_for_each_entry_safe(tpos, pos, n, head, member) \t\t \\\n\tfor (pos = (head)->first;\t\t\t\t\t \\\n\t     pos && ({ n = pos->next; 1; }) && \t\t\t\t \\\n\t\t({ tpos = hlist_entry(pos, typeof(*tpos), member); 1;}); \\\n\t     pos = n)\n\n#endif\n"
  },
  {
    "path": "package/network/services/ead/src/passwd",
    "content": "root:$1$MCGAgYw.$Ip1GcyeUliId3wzVcKR/e/:0:0:root:/root:/bin/ash\nnobody:*:65534:65534:nobody:/var:/bin/false\ndaemon:*:65534:65534:daemon:/var:/bin/false\n"
  },
  {
    "path": "package/network/services/ead/src/pfc.c",
    "content": "/*\n * Small pcap precompiler\n * Copyright (C) 2008 Felix Fietkau <nbd@nbd.name>\n *\n * This program is free software; you can redistribute it and/or modify\n * it under the terms of the GNU General Public License version 2\n * as published by the Free Software Foundation\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n * GNU General Public License for more details.\n */\n\n#include <sys/types.h>\n#include <sys/time.h>\n#include <string.h>\n#include <stdlib.h>\n#include <pcap.h>\n\nint main (int argc, char ** argv)\n{\n\tstruct bpf_program filter;\n\tpcap_t *pc;\n\tint i;\n\n\tif (argc != 2)\n\t{\n\t\tprintf (\"Usage: %s <expression>\\n\", argv[0]);\n\t\treturn 1;\n\t}\n\n\tpc = pcap_open_dead(DLT_EN10MB, 1500);\n\tif (pcap_compile(pc, &filter, argv[1], 1, 0) != 0) {\n\t\tprintf(\"error in active-filter expression: %s\\n\", pcap_geterr(pc));\n\t\treturn 1;\n\t}\n\n\tprintf(\"/* precompiled expression: %s */\\n\\n\"\n\t\t\"static struct bpf_insn pktfilter_insns[] = {\\n\",\n\t\targv[1]);\n\n\tfor (i = 0; i < filter.bf_len; i++) {\n\t\tstruct bpf_insn *in = &filter.bf_insns[i];\n\t\tprintf(\"\\t{ .code = 0x%04x, .jt = 0x%02x, .jf = 0x%02x, .k = 0x%08x },\\n\", in->code, in->jt, in->jf, in->k);\n\t}\n\tprintf(\"};\\n\\n\"\n\t\t\"static struct bpf_program pktfilter = {\\n\"\n\t\t\"\\t.bf_len = %d,\\n\"\n\t\t\"\\t.bf_insns = pktfilter_insns,\\n\"\n\t\t\"};\\n\", filter.bf_len);\n\treturn 0;\n\n}\n"
  },
  {
    "path": "package/network/services/ead/src/pw_encrypt_md5.c",
    "content": "/*\n * MD5C.C - RSA Data Security, Inc., MD5 message-digest algorithm\n *\n * Copyright (C) 1991-2, RSA Data Security, Inc. Created 1991. All\n * rights reserved.\n *\n * License to copy and use this software is granted provided that it\n * is identified as the \"RSA Data Security, Inc. MD5 Message-Digest\n * Algorithm\" in all material mentioning or referencing this software\n * or this function.\n *\n * License is also granted to make and use derivative works provided\n * that such works are identified as \"derived from the RSA Data\n * Security, Inc. MD5 Message-Digest Algorithm\" in all material\n * mentioning or referencing the derived work.\n *\n * RSA Data Security, Inc. makes no representations concerning either\n * the merchantability of this software or the suitability of this\n * software for any particular purpose. It is provided \"as is\"\n * without express or implied warranty of any kind.\n *\n * These notices must be retained in any copies of any part of this\n * documentation and/or software.\n *\n * $FreeBSD: src/lib/libmd/md5c.c,v 1.9.2.1 1999/08/29 14:57:12 peter Exp $\n *\n * This code is the same as the code published by RSA Inc.  It has been\n * edited for clarity and style only.\n *\n * ----------------------------------------------------------------------------\n * The md5_crypt() function was taken from freeBSD's libcrypt and contains\n * this license:\n *    \"THE BEER-WARE LICENSE\" (Revision 42):\n *     <phk@login.dknet.dk> wrote this file.  As long as you retain this notice you\n *     can do whatever you want with this stuff. If we meet some day, and you think\n *     this stuff is worth it, you can buy me a beer in return.   Poul-Henning Kamp\n *\n * $FreeBSD: src/lib/libcrypt/crypt.c,v 1.7.2.1 1999/08/29 14:56:33 peter Exp $\n *\n * ----------------------------------------------------------------------------\n * On April 19th, 2001 md5_crypt() was modified to make it reentrant\n * by Erik Andersen <andersen@uclibc.org>\n *\n *\n * June 28, 2001             Manuel Novoa III\n *\n * \"Un-inlined\" code using loops and static const tables in order to\n * reduce generated code size (on i386 from approx 4k to approx 2.5k).\n *\n * June 29, 2001             Manuel Novoa III\n *\n * Completely removed static PADDING array.\n *\n * Reintroduced the loop unrolling in MD5_Transform and added the\n * MD5_SIZE_OVER_SPEED option for configurability.  Define below as:\n *       0    fully unrolled loops\n *       1    partially unrolled (4 ops per loop)\n *       2    no unrolling -- introduces the need to swap 4 variables (slow)\n *       3    no unrolling and all 4 loops merged into one with switch\n *               in each loop (glacial)\n * On i386, sizes are roughly (-Os -fno-builtin):\n *     0: 3k     1: 2.5k     2: 2.2k     3: 2k\n *\n *\n * Since SuSv3 does not require crypt_r, modified again August 7, 2002\n * by Erik Andersen to remove reentrance stuff...\n */\n\nstatic const uint8_t ascii64[] = \"./0123456789ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz\";\n\n/*\n * Valid values are  1 (fastest/largest) to 3 (smallest/slowest).\n */\n#define MD5_SIZE_OVER_SPEED 3\n\n/**********************************************************************/\n\n/* MD5 context. */\nstruct MD5Context {\n\tuint32_t state[4];\t/* state (ABCD) */\n\tuint32_t count[2];\t/* number of bits, modulo 2^64 (lsb first) */\n\tunsigned char buffer[64];\t/* input buffer */\n};\n\nstatic void __md5_Init(struct MD5Context *);\nstatic void __md5_Update(struct MD5Context *, const unsigned char *, unsigned int);\nstatic void __md5_Pad(struct MD5Context *);\nstatic void __md5_Final(unsigned char [16], struct MD5Context *);\nstatic void __md5_Transform(uint32_t [4], const unsigned char [64]);\n\n\n#define MD5_MAGIC_STR \"$1$\"\n#define MD5_MAGIC_LEN (sizeof(MD5_MAGIC_STR) - 1)\nstatic const unsigned char __md5__magic[] = MD5_MAGIC_STR;\n\n\n#ifdef i386\n#define __md5_Encode memcpy\n#define __md5_Decode memcpy\n#else /* i386 */\n\n/*\n * __md5_Encodes input (uint32_t) into output (unsigned char). Assumes len is\n * a multiple of 4.\n */\nstatic void\n__md5_Encode(unsigned char *output, uint32_t *input, unsigned int len)\n{\n\tunsigned int i, j;\n\n\tfor (i = 0, j = 0; j < len; i++, j += 4) {\n\t\toutput[j] = input[i];\n\t\toutput[j+1] = (input[i] >> 8);\n\t\toutput[j+2] = (input[i] >> 16);\n\t\toutput[j+3] = (input[i] >> 24);\n\t}\n}\n\n/*\n * __md5_Decodes input (unsigned char) into output (uint32_t). Assumes len is\n * a multiple of 4.\n */\nstatic void\n__md5_Decode(uint32_t *output, const unsigned char *input, unsigned int len)\n{\n\tunsigned int i, j;\n\n\tfor (i = 0, j = 0; j < len; i++, j += 4)\n\t\toutput[i] = ((uint32_t)input[j]) | (((uint32_t)input[j+1]) << 8) |\n\t\t    (((uint32_t)input[j+2]) << 16) | (((uint32_t)input[j+3]) << 24);\n}\n#endif /* i386 */\n\n/* F, G, H and I are basic MD5 functions. */\n#define F(x, y, z) (((x) & (y)) | (~(x) & (z)))\n#define G(x, y, z) (((x) & (z)) | ((y) & ~(z)))\n#define H(x, y, z) ((x) ^ (y) ^ (z))\n#define I(x, y, z) ((y) ^ ((x) | ~(z)))\n\n/* ROTATE_LEFT rotates x left n bits. */\n#define ROTATE_LEFT(x, n) (((x) << (n)) | ((x) >> (32-(n))))\n\n/*\n * FF, GG, HH, and II transformations for rounds 1, 2, 3, and 4.\n * Rotation is separate from addition to prevent recomputation.\n */\n#define FF(a, b, c, d, x, s, ac) { \\\n\t(a) += F ((b), (c), (d)) + (x) + (uint32_t)(ac); \\\n\t(a) = ROTATE_LEFT((a), (s)); \\\n\t(a) += (b); \\\n\t}\n#define GG(a, b, c, d, x, s, ac) { \\\n\t(a) += G ((b), (c), (d)) + (x) + (uint32_t)(ac); \\\n\t(a) = ROTATE_LEFT((a), (s)); \\\n\t(a) += (b); \\\n\t}\n#define HH(a, b, c, d, x, s, ac) { \\\n\t(a) += H ((b), (c), (d)) + (x) + (uint32_t)(ac); \\\n\t(a) = ROTATE_LEFT((a), (s)); \\\n\t(a) += (b); \\\n\t}\n#define II(a, b, c, d, x, s, ac) { \\\n\t(a) += I ((b), (c), (d)) + (x) + (uint32_t)(ac); \\\n\t(a) = ROTATE_LEFT((a), (s)); \\\n\t(a) += (b); \\\n\t}\n\n/* MD5 initialization. Begins an MD5 operation, writing a new context. */\nstatic void __md5_Init(struct MD5Context *context)\n{\n\tcontext->count[0] = context->count[1] = 0;\n\n\t/* Load magic initialization constants.  */\n\tcontext->state[0] = 0x67452301;\n\tcontext->state[1] = 0xefcdab89;\n\tcontext->state[2] = 0x98badcfe;\n\tcontext->state[3] = 0x10325476;\n}\n\n/*\n * MD5 block update operation. Continues an MD5 message-digest\n * operation, processing another message block, and updating the\n * context.\n */\nstatic void __md5_Update(struct MD5Context *context, const unsigned char *input, unsigned int inputLen)\n{\n\tunsigned int i, idx, partLen;\n\n\t/* Compute number of bytes mod 64 */\n\tidx = (context->count[0] >> 3) & 0x3F;\n\n\t/* Update number of bits */\n\tcontext->count[0] += (inputLen << 3);\n\tif (context->count[0] < (inputLen << 3))\n\t\tcontext->count[1]++;\n\tcontext->count[1] += (inputLen >> 29);\n\n\tpartLen = 64 - idx;\n\n\t/* Transform as many times as possible. */\n\tif (inputLen >= partLen) {\n\t\tmemcpy(&context->buffer[idx], input, partLen);\n\t\t__md5_Transform(context->state, context->buffer);\n\n\t\tfor (i = partLen; i + 63 < inputLen; i += 64)\n\t\t\t__md5_Transform(context->state, &input[i]);\n\n\t\tidx = 0;\n\t} else\n\t\ti = 0;\n\n\t/* Buffer remaining input */\n\tmemcpy(&context->buffer[idx], &input[i], inputLen - i);\n}\n\n/*\n * MD5 padding. Adds padding followed by original length.\n */\nstatic void __md5_Pad(struct MD5Context *context)\n{\n\tunsigned char bits[8];\n\tunsigned int idx, padLen;\n\tunsigned char PADDING[64];\n\n\tmemset(PADDING, 0, sizeof(PADDING));\n\tPADDING[0] = 0x80;\n\n\t/* Save number of bits */\n\t__md5_Encode(bits, context->count, 8);\n\n\t/* Pad out to 56 mod 64. */\n\tidx = (context->count[0] >> 3) & 0x3f;\n\tpadLen = (idx < 56) ? (56 - idx) : (120 - idx);\n\t__md5_Update(context, PADDING, padLen);\n\n\t/* Append length (before padding) */\n\t__md5_Update(context, bits, 8);\n}\n\n/*\n * MD5 finalization. Ends an MD5 message-digest operation, writing the\n * the message digest and zeroizing the context.\n */\nstatic void __md5_Final(unsigned char digest[16], struct MD5Context *context)\n{\n\t/* Do padding. */\n\t__md5_Pad(context);\n\n\t/* Store state in digest */\n\t__md5_Encode(digest, context->state, 16);\n\n\t/* Zeroize sensitive information. */\n\tmemset(context, 0, sizeof(*context));\n}\n\n/* MD5 basic transformation. Transforms state based on block. */\nstatic void __md5_Transform(uint32_t state[4], const unsigned char block[64])\n{\n\tuint32_t a, b, c, d, x[16];\n#if MD5_SIZE_OVER_SPEED > 1\n\tuint32_t temp;\n\tconst unsigned char *ps;\n\n\tstatic const unsigned char S[] = {\n\t\t7, 12, 17, 22,\n\t\t5, 9, 14, 20,\n\t\t4, 11, 16, 23,\n\t\t6, 10, 15, 21\n\t};\n#endif /* MD5_SIZE_OVER_SPEED > 1 */\n\n#if MD5_SIZE_OVER_SPEED > 0\n\tconst uint32_t *pc;\n\tconst unsigned char *pp;\n\tint i;\n\n\tstatic const uint32_t C[] = {\n\t\t\t\t\t\t\t\t/* round 1 */\n\t\t0xd76aa478, 0xe8c7b756, 0x242070db, 0xc1bdceee,\n\t\t0xf57c0faf, 0x4787c62a, 0xa8304613, 0xfd469501,\n\t\t0x698098d8, 0x8b44f7af, 0xffff5bb1, 0x895cd7be,\n\t\t0x6b901122, 0xfd987193, 0xa679438e, 0x49b40821,\n\t\t\t\t\t\t\t\t/* round 2 */\n\t\t0xf61e2562, 0xc040b340, 0x265e5a51, 0xe9b6c7aa,\n\t\t0xd62f105d, 0x2441453,  0xd8a1e681, 0xe7d3fbc8,\n\t\t0x21e1cde6, 0xc33707d6, 0xf4d50d87, 0x455a14ed,\n\t\t0xa9e3e905, 0xfcefa3f8, 0x676f02d9, 0x8d2a4c8a,\n\t\t\t\t\t\t\t\t/* round 3 */\n\t\t0xfffa3942, 0x8771f681, 0x6d9d6122, 0xfde5380c,\n\t\t0xa4beea44, 0x4bdecfa9, 0xf6bb4b60, 0xbebfbc70,\n\t\t0x289b7ec6, 0xeaa127fa, 0xd4ef3085, 0x4881d05,\n\t\t0xd9d4d039, 0xe6db99e5, 0x1fa27cf8, 0xc4ac5665,\n\t\t\t\t\t\t\t\t/* round 4 */\n\t\t0xf4292244, 0x432aff97, 0xab9423a7, 0xfc93a039,\n\t\t0x655b59c3, 0x8f0ccc92, 0xffeff47d, 0x85845dd1,\n\t\t0x6fa87e4f, 0xfe2ce6e0, 0xa3014314, 0x4e0811a1,\n\t\t0xf7537e82, 0xbd3af235, 0x2ad7d2bb, 0xeb86d391\n\t};\n\n\tstatic const unsigned char P[] = {\n\t\t0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, /* 1 */\n\t\t1, 6, 11, 0, 5, 10, 15, 4, 9, 14, 3, 8, 13, 2, 7, 12, /* 2 */\n\t\t5, 8, 11, 14, 1, 4, 7, 10, 13, 0, 3, 6, 9, 12, 15, 2, /* 3 */\n\t\t0, 7, 14, 5, 12, 3, 10, 1, 8, 15, 6, 13, 4, 11, 2, 9  /* 4 */\n\t};\n\n#endif /* MD5_SIZE_OVER_SPEED > 0 */\n\n\t__md5_Decode(x, block, 64);\n\n\ta = state[0]; b = state[1]; c = state[2]; d = state[3];\n\n#if MD5_SIZE_OVER_SPEED > 2\n\tpc = C; pp = P; ps = S - 4;\n\n\tfor (i = 0; i < 64; i++) {\n\t\tif ((i & 0x0f) == 0) ps += 4;\n\t\ttemp = a;\n\t\tswitch (i>>4) {\n\t\t\tcase 0:\n\t\t\t\ttemp += F(b, c, d);\n\t\t\t\tbreak;\n\t\t\tcase 1:\n\t\t\t\ttemp += G(b, c, d);\n\t\t\t\tbreak;\n\t\t\tcase 2:\n\t\t\t\ttemp += H(b, c, d);\n\t\t\t\tbreak;\n\t\t\tcase 3:\n\t\t\t\ttemp += I(b, c, d);\n\t\t\t\tbreak;\n\t\t}\n\t\ttemp += x[*pp++] + *pc++;\n\t\ttemp = ROTATE_LEFT(temp, ps[i & 3]);\n\t\ttemp += b;\n\t\ta = d; d = c; c = b; b = temp;\n\t}\n#elif MD5_SIZE_OVER_SPEED > 1\n\tpc = C; pp = P; ps = S;\n\n\t/* Round 1 */\n\tfor (i = 0; i < 16; i++) {\n\t\tFF(a, b, c, d, x[*pp], ps[i & 0x3], *pc); pp++; pc++;\n\t\ttemp = d; d = c; c = b; b = a; a = temp;\n\t}\n\n\t/* Round 2 */\n\tps += 4;\n\tfor (; i < 32; i++) {\n\t\tGG(a, b, c, d, x[*pp], ps[i & 0x3], *pc); pp++; pc++;\n\t\ttemp = d; d = c; c = b; b = a; a = temp;\n\t}\n\t/* Round 3 */\n\tps += 4;\n\tfor (; i < 48; i++) {\n\t\tHH(a, b, c, d, x[*pp], ps[i & 0x3], *pc); pp++; pc++;\n\t\ttemp = d; d = c; c = b; b = a; a = temp;\n\t}\n\n\t/* Round 4 */\n\tps += 4;\n\tfor (; i < 64; i++) {\n\t\tII(a, b, c, d, x[*pp], ps[i & 0x3], *pc); pp++; pc++;\n\t\ttemp = d; d = c; c = b; b = a; a = temp;\n\t}\n#elif MD5_SIZE_OVER_SPEED > 0\n\tpc = C; pp = P;\n\n\t/* Round 1 */\n\tfor (i = 0; i < 4; i++) {\n\t\tFF(a, b, c, d, x[*pp],  7, *pc); pp++; pc++;\n\t\tFF(d, a, b, c, x[*pp], 12, *pc); pp++; pc++;\n\t\tFF(c, d, a, b, x[*pp], 17, *pc); pp++; pc++;\n\t\tFF(b, c, d, a, x[*pp], 22, *pc); pp++; pc++;\n\t}\n\n\t/* Round 2 */\n\tfor (i = 0; i < 4; i++) {\n\t\tGG(a, b, c, d, x[*pp],  5, *pc); pp++; pc++;\n\t\tGG(d, a, b, c, x[*pp],  9, *pc); pp++; pc++;\n\t\tGG(c, d, a, b, x[*pp], 14, *pc); pp++; pc++;\n\t\tGG(b, c, d, a, x[*pp], 20, *pc); pp++; pc++;\n\t}\n\t/* Round 3 */\n\tfor (i = 0; i < 4; i++) {\n\t\tHH(a, b, c, d, x[*pp],  4, *pc); pp++; pc++;\n\t\tHH(d, a, b, c, x[*pp], 11, *pc); pp++; pc++;\n\t\tHH(c, d, a, b, x[*pp], 16, *pc); pp++; pc++;\n\t\tHH(b, c, d, a, x[*pp], 23, *pc); pp++; pc++;\n\t}\n\n\t/* Round 4 */\n\tfor (i = 0; i < 4; i++) {\n\t\tII(a, b, c, d, x[*pp],  6, *pc); pp++; pc++;\n\t\tII(d, a, b, c, x[*pp], 10, *pc); pp++; pc++;\n\t\tII(c, d, a, b, x[*pp], 15, *pc); pp++; pc++;\n\t\tII(b, c, d, a, x[*pp], 21, *pc); pp++; pc++;\n\t}\n#else\n\t/* Round 1 */\n#define S11 7\n#define S12 12\n#define S13 17\n#define S14 22\n\tFF(a, b, c, d, x[ 0], S11, 0xd76aa478); /* 1 */\n\tFF(d, a, b, c, x[ 1], S12, 0xe8c7b756); /* 2 */\n\tFF(c, d, a, b, x[ 2], S13, 0x242070db); /* 3 */\n\tFF(b, c, d, a, x[ 3], S14, 0xc1bdceee); /* 4 */\n\tFF(a, b, c, d, x[ 4], S11, 0xf57c0faf); /* 5 */\n\tFF(d, a, b, c, x[ 5], S12, 0x4787c62a); /* 6 */\n\tFF(c, d, a, b, x[ 6], S13, 0xa8304613); /* 7 */\n\tFF(b, c, d, a, x[ 7], S14, 0xfd469501); /* 8 */\n\tFF(a, b, c, d, x[ 8], S11, 0x698098d8); /* 9 */\n\tFF(d, a, b, c, x[ 9], S12, 0x8b44f7af); /* 10 */\n\tFF(c, d, a, b, x[10], S13, 0xffff5bb1); /* 11 */\n\tFF(b, c, d, a, x[11], S14, 0x895cd7be); /* 12 */\n\tFF(a, b, c, d, x[12], S11, 0x6b901122); /* 13 */\n\tFF(d, a, b, c, x[13], S12, 0xfd987193); /* 14 */\n\tFF(c, d, a, b, x[14], S13, 0xa679438e); /* 15 */\n\tFF(b, c, d, a, x[15], S14, 0x49b40821); /* 16 */\n\n\t/* Round 2 */\n#define S21 5\n#define S22 9\n#define S23 14\n#define S24 20\n\tGG(a, b, c, d, x[ 1], S21, 0xf61e2562); /* 17 */\n\tGG(d, a, b, c, x[ 6], S22, 0xc040b340); /* 18 */\n\tGG(c, d, a, b, x[11], S23, 0x265e5a51); /* 19 */\n\tGG(b, c, d, a, x[ 0], S24, 0xe9b6c7aa); /* 20 */\n\tGG(a, b, c, d, x[ 5], S21, 0xd62f105d); /* 21 */\n\tGG(d, a, b, c, x[10], S22,  0x2441453); /* 22 */\n\tGG(c, d, a, b, x[15], S23, 0xd8a1e681); /* 23 */\n\tGG(b, c, d, a, x[ 4], S24, 0xe7d3fbc8); /* 24 */\n\tGG(a, b, c, d, x[ 9], S21, 0x21e1cde6); /* 25 */\n\tGG(d, a, b, c, x[14], S22, 0xc33707d6); /* 26 */\n\tGG(c, d, a, b, x[ 3], S23, 0xf4d50d87); /* 27 */\n\tGG(b, c, d, a, x[ 8], S24, 0x455a14ed); /* 28 */\n\tGG(a, b, c, d, x[13], S21, 0xa9e3e905); /* 29 */\n\tGG(d, a, b, c, x[ 2], S22, 0xfcefa3f8); /* 30 */\n\tGG(c, d, a, b, x[ 7], S23, 0x676f02d9); /* 31 */\n\tGG(b, c, d, a, x[12], S24, 0x8d2a4c8a); /* 32 */\n\n\t/* Round 3 */\n#define S31 4\n#define S32 11\n#define S33 16\n#define S34 23\n\tHH(a, b, c, d, x[ 5], S31, 0xfffa3942); /* 33 */\n\tHH(d, a, b, c, x[ 8], S32, 0x8771f681); /* 34 */\n\tHH(c, d, a, b, x[11], S33, 0x6d9d6122); /* 35 */\n\tHH(b, c, d, a, x[14], S34, 0xfde5380c); /* 36 */\n\tHH(a, b, c, d, x[ 1], S31, 0xa4beea44); /* 37 */\n\tHH(d, a, b, c, x[ 4], S32, 0x4bdecfa9); /* 38 */\n\tHH(c, d, a, b, x[ 7], S33, 0xf6bb4b60); /* 39 */\n\tHH(b, c, d, a, x[10], S34, 0xbebfbc70); /* 40 */\n\tHH(a, b, c, d, x[13], S31, 0x289b7ec6); /* 41 */\n\tHH(d, a, b, c, x[ 0], S32, 0xeaa127fa); /* 42 */\n\tHH(c, d, a, b, x[ 3], S33, 0xd4ef3085); /* 43 */\n\tHH(b, c, d, a, x[ 6], S34,  0x4881d05); /* 44 */\n\tHH(a, b, c, d, x[ 9], S31, 0xd9d4d039); /* 45 */\n\tHH(d, a, b, c, x[12], S32, 0xe6db99e5); /* 46 */\n\tHH(c, d, a, b, x[15], S33, 0x1fa27cf8); /* 47 */\n\tHH(b, c, d, a, x[ 2], S34, 0xc4ac5665); /* 48 */\n\n\t/* Round 4 */\n#define S41 6\n#define S42 10\n#define S43 15\n#define S44 21\n\tII(a, b, c, d, x[ 0], S41, 0xf4292244); /* 49 */\n\tII(d, a, b, c, x[ 7], S42, 0x432aff97); /* 50 */\n\tII(c, d, a, b, x[14], S43, 0xab9423a7); /* 51 */\n\tII(b, c, d, a, x[ 5], S44, 0xfc93a039); /* 52 */\n\tII(a, b, c, d, x[12], S41, 0x655b59c3); /* 53 */\n\tII(d, a, b, c, x[ 3], S42, 0x8f0ccc92); /* 54 */\n\tII(c, d, a, b, x[10], S43, 0xffeff47d); /* 55 */\n\tII(b, c, d, a, x[ 1], S44, 0x85845dd1); /* 56 */\n\tII(a, b, c, d, x[ 8], S41, 0x6fa87e4f); /* 57 */\n\tII(d, a, b, c, x[15], S42, 0xfe2ce6e0); /* 58 */\n\tII(c, d, a, b, x[ 6], S43, 0xa3014314); /* 59 */\n\tII(b, c, d, a, x[13], S44, 0x4e0811a1); /* 60 */\n\tII(a, b, c, d, x[ 4], S41, 0xf7537e82); /* 61 */\n\tII(d, a, b, c, x[11], S42, 0xbd3af235); /* 62 */\n\tII(c, d, a, b, x[ 2], S43, 0x2ad7d2bb); /* 63 */\n\tII(b, c, d, a, x[ 9], S44, 0xeb86d391); /* 64 */\n#endif\n\n\tstate[0] += a;\n\tstate[1] += b;\n\tstate[2] += c;\n\tstate[3] += d;\n\n\t/* Zeroize sensitive information. */\n\tmemset(x, 0, sizeof(x));\n}\n\n\nstatic char*\n__md5_to64(char *s, unsigned v, int n)\n{\n\twhile (--n >= 0) {\n\t\t*s++ = ascii64[v & 0x3f];\n\t\tv >>= 6;\n\t}\n\treturn s;\n}\n\n/*\n * UNIX password\n *\n * Use MD5 for what it is best at...\n */\n#define MD5_OUT_BUFSIZE 36\nstatic char *\nmd5_crypt(char passwd[MD5_OUT_BUFSIZE], const unsigned char *pw, const unsigned char *salt)\n{\n\tconst unsigned char *sp, *ep;\n\tchar *p;\n\tunsigned char final[17];\t/* final[16] exists only to aid in looping */\n\tint sl, pl, i, pw_len;\n\tstruct MD5Context ctx, ctx1;\n\n\t/* Refine the Salt first */\n\tsp = salt;\n\n\tsp += MD5_MAGIC_LEN;\n\n\t/* It stops at the first '$', max 8 chars */\n\tfor (ep = sp; *ep && *ep != '$' && ep < (sp+8); ep++)\n\t\tcontinue;\n\n\t/* get the length of the true salt */\n\tsl = ep - sp;\n\n\t__md5_Init(&ctx);\n\n\t/* The password first, since that is what is most unknown */\n\tpw_len = strlen((char*)pw);\n\t__md5_Update(&ctx, pw, pw_len);\n\n\t/* Then our magic string */\n\t__md5_Update(&ctx, __md5__magic, MD5_MAGIC_LEN);\n\n\t/* Then the raw salt */\n\t__md5_Update(&ctx, sp, sl);\n\n\t/* Then just as many characters of the MD5(pw, salt, pw) */\n\t__md5_Init(&ctx1);\n\t__md5_Update(&ctx1, pw, pw_len);\n\t__md5_Update(&ctx1, sp, sl);\n\t__md5_Update(&ctx1, pw, pw_len);\n\t__md5_Final(final, &ctx1);\n\tfor (pl = pw_len; pl > 0; pl -= 16)\n\t\t__md5_Update(&ctx, final, pl > 16 ? 16 : pl);\n\n\t/* Don't leave anything around in vm they could use. */\n//TODO: the above comment seems to be wrong. final is used later.\n\tmemset(final, 0, sizeof(final));\n\n\t/* Then something really weird... */\n\tfor (i = pw_len; i; i >>= 1) {\n\t\t__md5_Update(&ctx, ((i & 1) ? final : (const unsigned char *) pw), 1);\n\t}\n\n\t/* Now make the output string */\n\tpasswd[0] = '$';\n\tpasswd[1] = '1';\n\tpasswd[2] = '$';\n\tstrncpy(passwd + 3, (char*)sp, sl);\n\tpasswd[sl + 3] = '$';\n\n\t__md5_Final(final, &ctx);\n\n\t/*\n\t * and now, just to make sure things don't run too fast\n\t * On a 60 Mhz Pentium this takes 34 msec, so you would\n\t * need 30 seconds to build a 1000 entry dictionary...\n\t */\n\tfor (i = 0; i < 1000; i++) {\n\t\t__md5_Init(&ctx1);\n\t\tif (i & 1)\n\t\t\t__md5_Update(&ctx1, pw, pw_len);\n\t\telse\n\t\t\t__md5_Update(&ctx1, final, 16);\n\n\t\tif (i % 3)\n\t\t\t__md5_Update(&ctx1, sp, sl);\n\n\t\tif (i % 7)\n\t\t\t__md5_Update(&ctx1, pw, pw_len);\n\n\t\tif (i & 1)\n\t\t\t__md5_Update(&ctx1, final, 16);\n\t\telse\n\t\t\t__md5_Update(&ctx1, pw, pw_len);\n\t\t__md5_Final(final, &ctx1);\n\t}\n\n\tp = passwd + sl + 4; /* 12 bytes max (sl is up to 8 bytes) */\n\n\t/* Add 5*4+2 = 22 bytes of hash, + NUL byte. */\n\tfinal[16] = final[5];\n\tfor (i = 0; i < 5; i++) {\n\t\tunsigned l = (final[i] << 16) | (final[i+6] << 8) | final[i+12];\n\t\tp = __md5_to64(p, l, 4);\n\t}\n\tp = __md5_to64(p, final[11], 2);\n\t*p = '\\0';\n\n\t/* Don't leave anything around in vm they could use. */\n\tmemset(final, 0, sizeof(final));\n\n\treturn passwd;\n}\n\n#undef MD5_SIZE_OVER_SPEED\n#undef MD5_MAGIC_STR\n#undef MD5_MAGIC_LEN\n#undef __md5_Encode\n#undef __md5_Decode\n#undef F\n#undef G\n#undef H\n#undef I\n#undef ROTATE_LEFT\n#undef FF\n#undef GG\n#undef HH\n#undef II\n#undef S11\n#undef S12\n#undef S13\n#undef S14\n#undef S21\n#undef S22\n#undef S23\n#undef S24\n#undef S31\n#undef S32\n#undef S33\n#undef S34\n#undef S41\n#undef S42\n#undef S43\n#undef S44\n"
  },
  {
    "path": "package/network/services/ead/src/sha1.c",
    "content": "/*\n * SHA transform algorithm, originally taken from code written by\n * Peter Gutmann, and placed in the public domain.\n */\n\nstatic  uint32_t\nrol32(uint32_t word, int shift)\n{\n\treturn (word << shift) | (word >> (32 - shift));\n}\n\n/* The SHA f()-functions.  */\n\n#define f1(x,y,z)   (z ^ (x & (y ^ z)))\t\t/* x ? y : z */\n#define f2(x,y,z)   (x ^ y ^ z)\t\t\t/* XOR */\n#define f3(x,y,z)   ((x & y) + (z & (x ^ y)))\t/* majority */\n\n/* The SHA Mysterious Constants */\n\n#define K1  0x5A827999L\t\t\t/* Rounds  0-19: sqrt(2) * 2^30 */\n#define K2  0x6ED9EBA1L\t\t\t/* Rounds 20-39: sqrt(3) * 2^30 */\n#define K3  0x8F1BBCDCL\t\t\t/* Rounds 40-59: sqrt(5) * 2^30 */\n#define K4  0xCA62C1D6L\t\t\t/* Rounds 60-79: sqrt(10) * 2^30 */\n\n/**\n * sha_transform - single block SHA1 transform\n *\n * @digest: 160 bit digest to update\n * @data:   512 bits of data to hash\n * @W:      80 words of workspace (see note)\n *\n * This function generates a SHA1 digest for a single 512-bit block.\n * Be warned, it does not handle padding and message digest, do not\n * confuse it with the full FIPS 180-1 digest algorithm for variable\n * length messages.\n *\n * Note: If the hash is security sensitive, the caller should be sure\n * to clear the workspace. This is left to the caller to avoid\n * unnecessary clears between chained hashing operations.\n */\nstatic void sha_transform(uint32_t *digest, const unsigned char *in, uint32_t *W)\n{\n\tuint32_t a, b, c, d, e, t, i;\n\n\tfor (i = 0; i < 16; i++) {\n\t\tint ofs = 4 * i;\n\n\t\t/* word load/store may be unaligned here, so use bytes instead */\n\t\tW[i] =\n\t\t\t(in[ofs+0] << 24) |\n\t\t\t(in[ofs+1] << 16) |\n\t\t\t(in[ofs+2] << 8) |\n\t\t\t in[ofs+3];\n\t}\n\n\tfor (i = 0; i < 64; i++)\n\t\tW[i+16] = rol32(W[i+13] ^ W[i+8] ^ W[i+2] ^ W[i], 1);\n\n\ta = digest[0];\n\tb = digest[1];\n\tc = digest[2];\n\td = digest[3];\n\te = digest[4];\n\n\tfor (i = 0; i < 20; i++) {\n\t\tt = f1(b, c, d) + K1 + rol32(a, 5) + e + W[i];\n\t\te = d; d = c; c = rol32(b, 30); b = a; a = t;\n\t}\n\n\tfor (; i < 40; i ++) {\n\t\tt = f2(b, c, d) + K2 + rol32(a, 5) + e + W[i];\n\t\te = d; d = c; c = rol32(b, 30); b = a; a = t;\n\t}\n\n\tfor (; i < 60; i ++) {\n\t\tt = f3(b, c, d) + K3 + rol32(a, 5) + e + W[i];\n\t\te = d; d = c; c = rol32(b, 30); b = a; a = t;\n\t}\n\n\tfor (; i < 80; i ++) {\n\t\tt = f2(b, c, d) + K4 + rol32(a, 5) + e + W[i];\n\t\te = d; d = c; c = rol32(b, 30); b = a; a = t;\n\t}\n\n\tdigest[0] += a;\n\tdigest[1] += b;\n\tdigest[2] += c;\n\tdigest[3] += d;\n\tdigest[4] += e;\n}\n\n/**\n * sha_init - initialize the vectors for a SHA1 digest\n * @buf: vector to initialize\n */\nstatic void sha_init(uint32_t *buf)\n{\n\tbuf[0] = 0x67452301;\n\tbuf[1] = 0xefcdab89;\n\tbuf[2] = 0x98badcfe;\n\tbuf[3] = 0x10325476;\n\tbuf[4] = 0xc3d2e1f0;\n}\n\n"
  },
  {
    "path": "package/network/services/ead/src/tinysrp/Makefile.am",
    "content": "AUTOMAKE_OPTIONS = foreign no-dependencies\n\nnoinst_HEADERS = t_client.h t_pwd.h t_server.h t_sha.h \\\n  bn.h bn_lcl.h bn_prime.h t_defines.h t_read.h\n\ninclude_HEADERS = tinysrp.h\n\nlib_LIBRARIES = libtinysrp.a\n\nCFLAGS = -O2 @signed@\n\nlibtinysrp_a_SOURCES = \\\n  tinysrp.c t_client.c t_getconf.c t_conv.c t_getpass.c t_sha.c t_math.c \\\n  t_misc.c t_pw.c t_read.c t_server.c t_truerand.c \\\n  bn_add.c bn_ctx.c bn_div.c bn_exp.c bn_mul.c bn_word.c bn_asm.c bn_lib.c \\\n  bn_shift.c bn_sqr.c\n\nnoinst_PROGRAMS = srvtest clitest\nsrvtest_SOURCES = srvtest.c\nclitest_SOURCES = clitest.c\n\nbin_PROGRAMS = tconf tphrase\ntconf_SOURCES = tconf.c t_conf.c\ntphrase_SOURCES = tphrase.c\n\nLDADD = libtinysrp.a\n\nEXTRA_DIST = tpasswd Notes\n"
  },
  {
    "path": "package/network/services/ead/src/tinysrp/Makefile.in",
    "content": "# Makefile.in generated automatically by automake 1.4a from Makefile.am\n\n# Copyright (C) 1994, 1995-8, 1999 Free Software Foundation, Inc.\n# This Makefile.in is free software; the Free Software Foundation\n# gives unlimited permission to copy and/or distribute it,\n# with or without modifications, as long as this notice is preserved.\n\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY, to the extent permitted by law; without\n# even the implied warranty of MERCHANTABILITY or FITNESS FOR A\n# PARTICULAR PURPOSE.\n\n\nSHELL = @SHELL@\n\nsrcdir = @srcdir@\ntop_srcdir = @top_srcdir@\nVPATH = @srcdir@\nprefix = @prefix@\nexec_prefix = @exec_prefix@\n\nbindir = @bindir@\nsbindir = @sbindir@\nlibexecdir = @libexecdir@\ndatadir = @datadir@\nsysconfdir = @sysconfdir@\nsharedstatedir = @sharedstatedir@\nlocalstatedir = @localstatedir@\nlibdir = @libdir@\ninfodir = @infodir@\nmandir = @mandir@\nincludedir = @includedir@\noldincludedir = /usr/include\n\nDESTDIR =\n\npkgdatadir = $(datadir)/@PACKAGE@\npkglibdir = $(libdir)/@PACKAGE@\npkgincludedir = $(includedir)/@PACKAGE@\n\ntop_builddir = .\n\nACLOCAL = @ACLOCAL@\nAUTOCONF = @AUTOCONF@\nAUTOMAKE = @AUTOMAKE@\nAUTOHEADER = @AUTOHEADER@\n\nINSTALL = @INSTALL@\nINSTALL_PROGRAM = @INSTALL_PROGRAM@\nINSTALL_DATA = @INSTALL_DATA@\nINSTALL_SCRIPT = @INSTALL_SCRIPT@\nINSTALL_STRIP_FLAG =\ntransform = @program_transform_name@\n\nNORMAL_INSTALL = :\nPRE_INSTALL = :\nPOST_INSTALL = :\nNORMAL_UNINSTALL = :\nPRE_UNINSTALL = :\nPOST_UNINSTALL = :\nCC = @CC@\nLN_S = @LN_S@\nMAKEINFO = @MAKEINFO@\nPACKAGE = @PACKAGE@\nRANLIB = @RANLIB@\nVERSION = @VERSION@\nsigned = @signed@\n\nAUTOMAKE_OPTIONS = foreign no-dependencies\n\nnoinst_HEADERS = t_client.h t_pwd.h t_server.h t_sha.h   bn.h bn_lcl.h bn_prime.h t_defines.h t_read.h\n\n\ninclude_HEADERS = tinysrp.h\n\nlib_LIBRARIES = libtinysrp.a\n\nCFLAGS = -O2 @signed@\n\nlibtinysrp_a_SOURCES =    tinysrp.c t_client.c t_getconf.c t_conv.c t_getpass.c t_sha.c t_math.c   t_misc.c t_pw.c t_read.c t_server.c t_truerand.c   bn_add.c bn_ctx.c bn_div.c bn_exp.c bn_mul.c bn_word.c bn_asm.c bn_lib.c   bn_shift.c bn_sqr.c\n\n\nnoinst_PROGRAMS = srvtest clitest\nsrvtest_SOURCES = srvtest.c\nclitest_SOURCES = clitest.c\n\nbin_PROGRAMS = tconf tphrase\ntconf_SOURCES = tconf.c t_conf.c\ntphrase_SOURCES = tphrase.c\n\nLDADD = libtinysrp.a\n\nEXTRA_DIST = tpasswd Notes\nACLOCAL_M4 = $(top_srcdir)/aclocal.m4\nmkinstalldirs = $(SHELL) $(top_srcdir)/mkinstalldirs\nCONFIG_HEADER = config.h\nCONFIG_CLEAN_FILES = \nLIBRARIES =  $(lib_LIBRARIES)\n\n\nDEFS = @DEFS@ -I. -I$(srcdir) -I.\nCPPFLAGS = @CPPFLAGS@\nLDFLAGS = @LDFLAGS@\nLIBS = @LIBS@\nlibtinysrp_a_LIBADD = \nlibtinysrp_a_OBJECTS =  tinysrp.o t_client.o t_getconf.o t_conv.o \\\nt_getpass.o t_sha.o t_math.o t_misc.o t_pw.o t_read.o t_server.o \\\nt_truerand.o bn_add.o bn_ctx.o bn_div.o bn_exp.o bn_mul.o bn_word.o \\\nbn_asm.o bn_lib.o bn_shift.o bn_sqr.o\nAR = ar\nPROGRAMS =  $(bin_PROGRAMS) $(noinst_PROGRAMS)\n\ntconf_OBJECTS =  tconf.o t_conf.o\ntconf_LDADD = $(LDADD)\ntconf_DEPENDENCIES =  libtinysrp.a\ntconf_LDFLAGS = \ntphrase_OBJECTS =  tphrase.o\ntphrase_LDADD = $(LDADD)\ntphrase_DEPENDENCIES =  libtinysrp.a\ntphrase_LDFLAGS = \nsrvtest_OBJECTS =  srvtest.o\nsrvtest_LDADD = $(LDADD)\nsrvtest_DEPENDENCIES =  libtinysrp.a\nsrvtest_LDFLAGS = \nclitest_OBJECTS =  clitest.o\nclitest_LDADD = $(LDADD)\nclitest_DEPENDENCIES =  libtinysrp.a\nclitest_LDFLAGS = \nCOMPILE = $(CC) $(DEFS) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS)\nCCLD = $(CC)\nLINK = $(CCLD) $(AM_CFLAGS) $(CFLAGS) $(LDFLAGS) -o $@\nHEADERS =  $(include_HEADERS) $(noinst_HEADERS)\n\nDIST_COMMON =  ./stamp-h.in Makefile.am Makefile.in acconfig.h \\\nacinclude.m4 aclocal.m4 config.h.in configure configure.in install-sh \\\nmissing mkinstalldirs\n\n\nDISTFILES = $(DIST_COMMON) $(SOURCES) $(HEADERS) $(TEXINFOS) $(EXTRA_DIST)\n\nTAR = gtar\nGZIP_ENV = --best\nSOURCES = $(libtinysrp_a_SOURCES) $(tconf_SOURCES) $(tphrase_SOURCES) $(srvtest_SOURCES) $(clitest_SOURCES)\nOBJECTS = $(libtinysrp_a_OBJECTS) $(tconf_OBJECTS) $(tphrase_OBJECTS) $(srvtest_OBJECTS) $(clitest_OBJECTS)\n\nall: all-redirect\n.SUFFIXES:\n.SUFFIXES: .S .c .o .s\n\nMakefile: $(srcdir)/Makefile.in  $(top_builddir)/config.status\n\tcd $(top_builddir) \\\n\t  && CONFIG_FILES=$@ CONFIG_HEADERS= $(SHELL) ./config.status\n\n$(ACLOCAL_M4):  configure.in  acinclude.m4\n\tcd $(srcdir) && $(ACLOCAL)\n\n$(srcdir)/configure: $(srcdir)/configure.in $(ACLOCAL_M4) $(CONFIGURE_DEPENDENCIES)\n\tcd $(srcdir) && $(AUTOCONF)\n\nconfig.h: stamp-h\n\t@if test ! -f $@; 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  },
  {
    "path": "package/network/services/ead/src/tinysrp/Notes",
    "content": "t_* stuff is from the srp 1.7.1 dist\nbn_* stuff is from openssl 0.9.6\n\n(The 7 in libtinysrp's version number reflects the srp version.)\n\nLicensing and copyright for srp and openssl are as indicated in the relevant\nsource files.  Everything else here is GPL, including the tinysrp protocol.\n\nChangelog since initial release:\n\n0.7.4   more robust terminal modes in t_getpass\n\ta potential buffer overflow in tinysrp\n0.7.5   uninitialized pointer bug in tconf\n\nChanges from the base srp and openssl distributions:\n\nI've removed everything that's not needed for client/server operations, and\nall the bn_* stuff that's only used for prime generation has been moved to\nt_conf.c, which isn't part of the library anymore.  Also, all the routines\nused for passphrase file maintenance have been moved to tphrase.c.\n\nThe library has been optimized (a bit) for space instead of speed.  Since\nauthentication is usually only done once, this isn't a big problem.  Modern\nCPUs are plenty fast for this task, and even 100 MHz CPUs are fine.  If you\nreally need the speed, get the regular distributions.\n\nNote that if the server sends the client a prime that the client doesn't\nknow about, the client MUST test for primality.  Since this is pretty\nexpensive, and takes 30 seconds on a 100 MHz machine, and uses lots of code,\nI've removed that ability from the client.  So only KNOWN primes can be\nused.  You can still generate new ones with tconf, but you have to install\nthem in the table of known primes (pre_params) in t_getconf.c that's common\nto the client and server, and recompile.  The configuration file is gone.\n\nThe default prime (the last entry in the table) is 1024 bits; there are\nothers with more bits but they will be correspondingly slower.\n\nThe default tpasswd file (which is an ascii file that may be editted with a\nregular text editor) contains two users: moo (passphrase \"glub glub\") and\n\"new user\" (passphrase \"this is a test\").  Passphrases may be added or\nchanged with tphrase; you can also change the user's prime.  To delete a\nuser, edit the tpasswd file and remove that line.  The tpasswd file's\ndefault name is DEFAULT_PASSWD in t_pwd.h.  Note that you can't change a\nuser's username by editting the file: the username is encoded in the\nverifier.  If you change a username you must set a new passphrase with\ntphrase.\n\nHere is an example session, using the supplied srvtest and clitest.  First,\nstart both programs in different windows, and enter the user names.  Normally,\nthe client would send the username to the server.  Server lines are marked\nwith S>, client lines with C>.\n\nS> % srvtest\nS> Enter username: moo\nS> index (to client): 5\nS> salt (to client): 19AI0Hc9jEkdFc\n\nC> % clitest\nC> Enter username: moo\nC> Enter index (from server): 5\nC> Enter salt (from server): 19AI0Hc9jEkdFc\n\nThe server reports the index and salt values used for that user.  They\nare sent over the network to the client.  (Simulate this by cutting and\npasting from one window to the other.)\n\nC> A (to server): 5wCDXRxLIv/zLazYfKupV/OY3BlhTZuJ71wVgI0HcL1kSJEpkMuWF.xEz/BV2wlJl7vk5Eoz9KMS1ccnaatsVP5D6CBm7UA.yVB59EQFN0dNBirvX29NAFdtdMsMppo5tHRy987XjJWrWSLpeibq6emr.gP8nYyX75GQqSiMY1j\nC> Enter password:\n\nS> Enter A (from client): 5wCDXRxLIv/zLazYfKupV/OY3BlhTZuJ71wVgI0HcL1kSJEpkMuWF.xEz/BV2wlJl7vk5Eoz9KMS1ccnaatsVP5D6CBm7UA.yVB59EQFN0dNBirvX29NAFdtdMsMppo5tHRy987XjJWrWSLpeibq6emr.gP8nYyX75GQqSiMY1j\n\nNow the client calculates A and sends it to the server, and while the\nserver is munching on that, the client gets the password from the user.\n\nS> B (to client): 9dcCpulxQAbaDXI0NHWY6B.QH6B9fsoXs/x/5SCNBNJm/6H6bYfbVrwNmdquhLZjYMvpcgGc2mBYqL77RNfw1kVQo17//GfsByECBIjRnrAn02ffX9Y/llJcfscAQiii0hyZhJf9PT5wE7pC7WUjIgSqckIZ0JLNDbSr7fJcrgw\nS> Session key: ebbcf3a45c968defdcfff6e144ad8d4f5412167c9716e79cbf7cacfe18257947ad46fa5d6418a1fd\n\nThe server now calculates B and sends it to the client.  The session key\nis not sent -- it is a shared secret that can be used for encryption.\n\nC> Enter B (from server): 9dcCpulxQAbaDXI0NHWY6B.QH6B9fsoXs/x/5SCNBNJm/6H6bYfbVrwNmdquhLZjYMvpcgGc2mBYqL77RNfw1kVQo17//GfsByECBIjRnrAn02ffX9Y/llJcfscAQiii0hyZhJf9PT5wE7pC7WUjIgSqckIZ0JLNDbSr7fJcrgw\nC> Session key: ebbcf3a45c968defdcfff6e144ad8d4f5412167c9716e79cbf7cacfe18257947ad46fa5d6418a1fd\nC> Response (to server): b9ea99094a176c4be28eb469982066cc7146d180\n\nThe client uses the B value to calculate its own copy of the shared secret\nsession key, and sends a response to the server proving that it does know\nthe correct key.\n\nS> Enter response (from client): b9ea99094a176c4be28eb469982066cc7146d180\nS> Authentication successful.\nS> Response (to client): cd46c839ccad2d0c76f3ca1905ae8ceda8d1c1dc\n\nThe server authenticates the client.  (You're in!)\n\nC> Enter server response: cd46c839ccad2d0c76f3ca1905ae8ceda8d1c1dc\nC> Server authentication successful.\n\nThe client authenticates the server (prevents server spoofing in the case\nwhere the session key isn't used to encrypt the channel -- a spoofed server\nmight just respond with random values and _pretend_ to authenticate the\nclient; but the spoofed server won't know the session key and this check\ncatches that).\n\nFinal note:\n\nRemember that many breaches of security involve buggy software, such as\nservers susceptible to buffer overflow exploits that totally bypass any\npassphrase, secure or not.  If an attacker roots your client, or the server,\nno form of authentication will work.  Consider MAC-based schemes if this\nworries you.\n"
  },
  {
    "path": "package/network/services/ead/src/tinysrp/acconfig.h",
    "content": "#undef SHA1HANDSOFF\n\n#undef POSIX_TERMIOS\n\n#undef POSIX_SIGTYPE\n\n#undef VERSION\n\n#undef volatile\n"
  },
  {
    "path": "package/network/services/ead/src/tinysrp/acinclude.m4",
    "content": "dnl\ndnl check for signal type\ndnl\ndnl AC_RETSIGTYPE isn't quite right, but almost.\ndnl\ndefine(TYPE_SIGNAL,[\nAC_MSG_CHECKING([POSIX signal handlers])\nAC_CACHE_VAL(cv_has_posix_signals,\n[AC_TRY_COMPILE(\n[#include <sys/types.h>\n#include <signal.h>\n#ifdef signal\n#undef signal\n#endif\nextern void (*signal ()) ();], [],\ncv_has_posix_signals=yes, cv_has_posix_signals=no)])\nAC_MSG_RESULT($cv_has_posix_signals)\nif test $cv_has_posix_signals = yes; then\n   AC_DEFINE(RETSIGTYPE, void, [Return type is void])\n   AC_DEFINE(POSIX_SIGTYPE, [], [Have POSIX signals])\nelse\n  if test $ac_cv_type_signal = void; then\n     AC_DEFINE(RETSIGTYPE, void, [Return type is void])\n  else\n     AC_DEFINE(RETSIGTYPE, int, [Return type is int])\n  fi\nfi])dnl\n"
  },
  {
    "path": "package/network/services/ead/src/tinysrp/aclocal.m4",
    "content": "dnl aclocal.m4 generated automatically by aclocal 1.4a\n\ndnl Copyright (C) 1994, 1995-8, 1999 Free Software Foundation, Inc.\ndnl This file is free software; the Free Software Foundation\ndnl gives unlimited permission to copy and/or distribute it,\ndnl with or without modifications, as long as this notice is preserved.\n\ndnl This program is distributed in the hope that it will be useful,\ndnl but WITHOUT ANY WARRANTY, to the extent permitted by law; without\ndnl even the implied warranty of MERCHANTABILITY or FITNESS FOR A\ndnl PARTICULAR PURPOSE.\n\ndnl\ndnl check for signal type\ndnl\ndnl AC_RETSIGTYPE isn't quite right, but almost.\ndnl\ndefine(TYPE_SIGNAL,[\nAC_MSG_CHECKING([POSIX signal handlers])\nAC_CACHE_VAL(cv_has_posix_signals,\n[AC_TRY_COMPILE(\n[#include <sys/types.h>\n#include <signal.h>\n#ifdef signal\n#undef signal\n#endif\nextern void (*signal ()) ();], [],\ncv_has_posix_signals=yes, cv_has_posix_signals=no)])\nAC_MSG_RESULT($cv_has_posix_signals)\nif test $cv_has_posix_signals = yes; then\n   AC_DEFINE(RETSIGTYPE, void, [Return type is void])\n   AC_DEFINE(POSIX_SIGTYPE, [], [Have POSIX signals])\nelse\n  if test $ac_cv_type_signal = void; then\n     AC_DEFINE(RETSIGTYPE, void, [Return type is void])\n  else\n     AC_DEFINE(RETSIGTYPE, int, [Return type is int])\n  fi\nfi])dnl\n\n# Like AC_CONFIG_HEADER, but automatically create stamp file.\n\nAC_DEFUN(AM_CONFIG_HEADER,\n[AC_PREREQ([2.12])\nAC_CONFIG_HEADER([$1])\ndnl When config.status generates a header, we must update the stamp-h file.\ndnl This file resides in the same directory as the config header\ndnl that is generated.  We must strip everything past the first \":\",\ndnl and everything past the last \"/\".\nAC_OUTPUT_COMMANDS(changequote(<<,>>)dnl\nifelse(patsubst(<<$1>>, <<[^ ]>>, <<>>), <<>>,\n<<test -z \"<<$>>CONFIG_HEADERS\" || echo timestamp > patsubst(<<$1>>, <<^\\([^:]*/\\)?.*>>, <<\\1>>)stamp-h<<>>dnl>>,\n<<am_indx=1\nfor am_file in <<$1>>; do\n  case \" <<$>>CONFIG_HEADERS \" in\n  *\" <<$>>am_file \"*<<)>>\n    echo timestamp > `echo <<$>>am_file | sed -e 's%:.*%%' -e 's%[^/]*$%%'`stamp-h$am_indx\n    ;;\n  esac\n  am_indx=`expr \"<<$>>am_indx\" + 1`\ndone<<>>dnl>>)\nchangequote([,]))])\n\n# Do all the work for Automake.  This macro actually does too much --\n# some checks are only needed if your package does certain things.\n# But this isn't really a big deal.\n\n# serial 1\n\ndnl Usage:\ndnl AM_INIT_AUTOMAKE(package,version, [no-define])\n\nAC_DEFUN(AM_INIT_AUTOMAKE,\n[AC_REQUIRE([AC_PROG_INSTALL])\ndnl We require 2.13 because we rely on SHELL being computed by configure.\nAC_PREREQ([2.13])\nPACKAGE=[$1]\nAC_SUBST(PACKAGE)\nVERSION=[$2]\nAC_SUBST(VERSION)\ndnl test to see if srcdir already configured\nif test \"`cd $srcdir && pwd`\" != \"`pwd`\" && test -f $srcdir/config.status; then\n  AC_MSG_ERROR([source directory already configured; run \"make distclean\" there first])\nfi\nifelse([$3],,\nAC_DEFINE_UNQUOTED(PACKAGE, \"$PACKAGE\", [Name of package])\nAC_DEFINE_UNQUOTED(VERSION, \"$VERSION\", [Version number of package]))\nAC_REQUIRE([AM_SANITY_CHECK])\nAC_REQUIRE([AC_ARG_PROGRAM])\ndnl FIXME This is truly gross.\nmissing_dir=`cd $ac_aux_dir && pwd`\nAM_MISSING_PROG(ACLOCAL, aclocal, $missing_dir)\nAM_MISSING_PROG(AUTOCONF, autoconf, $missing_dir)\nAM_MISSING_PROG(AUTOMAKE, automake, $missing_dir)\nAM_MISSING_PROG(AUTOHEADER, autoheader, $missing_dir)\nAM_MISSING_PROG(MAKEINFO, makeinfo, $missing_dir)\nAC_REQUIRE([AC_PROG_MAKE_SET])])\n\n#\n# Check to make sure that the build environment is sane.\n#\n\nAC_DEFUN(AM_SANITY_CHECK,\n[AC_MSG_CHECKING([whether build environment is sane])\n# Just in case\nsleep 1\necho timestamp > conftestfile\n# Do `set' in a subshell so we don't clobber the current shell's\n# arguments.  Must try -L first in case configure is actually a\n# symlink; some systems play weird games with the mod time of symlinks\n# (eg FreeBSD returns the mod time of the symlink's containing\n# directory).\nif (\n   set X `ls -Lt $srcdir/configure conftestfile 2> /dev/null`\n   if test \"[$]*\" = \"X\"; then\n      # -L didn't work.\n      set X `ls -t $srcdir/configure conftestfile`\n   fi\n   if test \"[$]*\" != \"X $srcdir/configure conftestfile\" \\\n      && test \"[$]*\" != \"X conftestfile $srcdir/configure\"; then\n\n      # If neither matched, then we have a broken ls.  This can happen\n      # if, for instance, CONFIG_SHELL is bash and it inherits a\n      # broken ls alias from the environment.  This has actually\n      # happened.  Such a system could not be considered \"sane\".\n      AC_MSG_ERROR([ls -t appears to fail.  Make sure there is not a broken\nalias in your environment])\n   fi\n\n   test \"[$]2\" = conftestfile\n   )\nthen\n   # Ok.\n   :\nelse\n   AC_MSG_ERROR([newly created file is older than distributed files!\nCheck your system clock])\nfi\nrm -f conftest*\nAC_MSG_RESULT(yes)])\n\ndnl AM_MISSING_PROG(NAME, PROGRAM, DIRECTORY)\ndnl The program must properly implement --version.\nAC_DEFUN(AM_MISSING_PROG,\n[AC_MSG_CHECKING(for working $2)\n# Run test in a subshell; some versions of sh will print an error if\n# an executable is not found, even if stderr is redirected.\n# Redirect stdin to placate older versions of autoconf.  Sigh.\nif ($2 --version) < /dev/null > /dev/null 2>&1; then\n   $1=$2\n   AC_MSG_RESULT(found)\nelse\n   $1=\"$3/missing $2\"\n   AC_MSG_RESULT(missing)\nfi\nAC_SUBST($1)])\n\n"
  },
  {
    "path": "package/network/services/ead/src/tinysrp/bn.h",
    "content": "/* crypto/bn/bn.h */\n/* Copyright (C) 1995-1997 Eric Young (eay@cryptsoft.com)\n * All rights reserved.\n *\n * This package is an SSL implementation written\n * by Eric Young (eay@cryptsoft.com).\n * The implementation was written so as to conform with Netscapes SSL.\n *\n * This library is free for commercial and non-commercial use as long as\n * the following conditions are aheared to.  The following conditions\n * apply to all code found in this distribution, be it the RC4, RSA,\n * lhash, DES, etc., code; not just the SSL code.  The SSL documentation\n * included with this distribution is covered by the same copyright terms\n * except that the holder is Tim Hudson (tjh@cryptsoft.com).\n *\n * Copyright remains Eric Young's, and as such any Copyright notices in\n * the code are not to be removed.\n * If this package is used in a product, Eric Young should be given attribution\n * as the author of the parts of the library used.\n * This can be in the form of a textual message at program startup or\n * in documentation (online or textual) provided with the package.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. All advertising materials mentioning features or use of this software\n *    must display the following acknowledgement:\n *    \"This product includes cryptographic software written by\n *     Eric Young (eay@cryptsoft.com)\"\n *    The word 'cryptographic' can be left out if the rouines from the library\n *    being used are not cryptographic related :-).\n * 4. If you include any Windows specific code (or a derivative thereof) from\n *    the apps directory (application code) you must include an acknowledgement:\n *    \"This product includes software written by Tim Hudson (tjh@cryptsoft.com)\"\n *\n * THIS SOFTWARE IS PROVIDED BY ERIC YOUNG ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n *\n * The licence and distribution terms for any publically available version or\n * derivative of this code cannot be changed.  i.e. this code cannot simply be\n * copied and put under another distribution licence\n * [including the GNU Public Licence.]\n */\n\n#ifndef HEADER_BN_H\n#define HEADER_BN_H\n\n#include <stdio.h> /* FILE */\n#include \"config.h\"\n\n#ifdef  __cplusplus\nextern \"C\" {\n#endif\n\n#ifdef VMS\n#undef BN_LLONG /* experimental, so far... */\n#endif\n\n#undef BN_MUL_COMBA\n#undef BN_SQR_COMBA\n#undef BN_RECURSION\n#undef RECP_MUL_MOD\n#undef MONT_MUL_MOD\n\n#if defined(SIZEOF_LONG_LONG) && SIZEOF_LONG_LONG == 8\n# if SIZEOF_LONG == 4\n#  define THIRTY_TWO_BIT\n# else\n#  define SIXTY_FOUR_BIT_LONG\n# endif\n#else\n# if SIZEOF_LONG == 4\n#  define THIRTY_TWO_BIT\n# endif\n#endif\n\n#undef BN_LLONG\n\n/* assuming long is 64bit - this is the DEC Alpha\n * unsigned long long is only 64 bits :-(, don't define\n * BN_LLONG for the DEC Alpha */\n#ifdef SIXTY_FOUR_BIT_LONG\n#define BN_ULLONG       unsigned long long\n#define BN_ULONG        unsigned long\n#define BN_LONG         long\n#define BN_BITS         128\n#define BN_BYTES        8\n#define BN_BITS2        64\n#define BN_BITS4        32\n#define BN_MASK         (0xffffffffffffffffffffffffffffffffLL)\n#define BN_MASK2        (0xffffffffffffffffL)\n#define BN_MASK2l       (0xffffffffL)\n#define BN_MASK2h       (0xffffffff00000000L)\n#define BN_MASK2h1      (0xffffffff80000000L)\n#define BN_TBIT         (0x8000000000000000L)\n#define BN_DEC_CONV     (10000000000000000000UL)\n#define BN_DEC_FMT1     \"%lu\"\n#define BN_DEC_FMT2     \"%019lu\"\n#define BN_DEC_NUM      19\n#endif\n\n/* This is where the long long data type is 64 bits, but long is 32.\n * For machines where there are 64bit registers, this is the mode to use.\n * IRIX, on R4000 and above should use this mode, along with the relevant\n * assembler code :-).  Do NOT define BN_LLONG.\n */\n#ifdef SIXTY_FOUR_BIT\n#undef BN_LLONG\n#undef BN_ULLONG\n#define BN_ULONG        unsigned long long\n#define BN_LONG         long long\n#define BN_BITS         128\n#define BN_BYTES        8\n#define BN_BITS2        64\n#define BN_BITS4        32\n#define BN_MASK2        (0xffffffffffffffffLL)\n#define BN_MASK2l       (0xffffffffL)\n#define BN_MASK2h       (0xffffffff00000000LL)\n#define BN_MASK2h1      (0xffffffff80000000LL)\n#define BN_TBIT         (0x8000000000000000LL)\n#define BN_DEC_CONV     (10000000000000000000LL)\n#define BN_DEC_FMT1     \"%llu\"\n#define BN_DEC_FMT2     \"%019llu\"\n#define BN_DEC_NUM      19\n#endif\n\n#ifdef THIRTY_TWO_BIT\n#if defined(WIN32) && !defined(__GNUC__)\n#define BN_ULLONG       unsigned _int64\n#else\n#define BN_ULLONG       unsigned long long\n#endif\n#define BN_ULONG        unsigned long\n#define BN_LONG         long\n#define BN_BITS         64\n#define BN_BYTES        4\n#define BN_BITS2        32\n#define BN_BITS4        16\n#ifdef WIN32\n/* VC++ doesn't like the LL suffix */\n#define BN_MASK         (0xffffffffffffffffL)\n#else\n#define BN_MASK         (0xffffffffffffffffLL)\n#endif\n#define BN_MASK2        (0xffffffffL)\n#define BN_MASK2l       (0xffff)\n#define BN_MASK2h1      (0xffff8000L)\n#define BN_MASK2h       (0xffff0000L)\n#define BN_TBIT         (0x80000000L)\n#define BN_DEC_CONV     (1000000000L)\n#define BN_DEC_FMT1     \"%lu\"\n#define BN_DEC_FMT2     \"%09lu\"\n#define BN_DEC_NUM      9\n#endif\n\n#ifdef SIXTEEN_BIT\n#ifndef BN_DIV2W\n#define BN_DIV2W\n#endif\n#define BN_ULLONG       unsigned long\n#define BN_ULONG        unsigned short\n#define BN_LONG         short\n#define BN_BITS         32\n#define BN_BYTES        2\n#define BN_BITS2        16\n#define BN_BITS4        8\n#define BN_MASK         (0xffffffff)\n#define BN_MASK2        (0xffff)\n#define BN_MASK2l       (0xff)\n#define BN_MASK2h1      (0xff80)\n#define BN_MASK2h       (0xff00)\n#define BN_TBIT         (0x8000)\n#define BN_DEC_CONV     (100000)\n#define BN_DEC_FMT1     \"%u\"\n#define BN_DEC_FMT2     \"%05u\"\n#define BN_DEC_NUM      5\n#endif\n\n#ifdef EIGHT_BIT\n#ifndef BN_DIV2W\n#define BN_DIV2W\n#endif\n#define BN_ULLONG       unsigned short\n#define BN_ULONG        unsigned char\n#define BN_LONG         char\n#define BN_BITS         16\n#define BN_BYTES        1\n#define BN_BITS2        8\n#define BN_BITS4        4\n#define BN_MASK         (0xffff)\n#define BN_MASK2        (0xff)\n#define BN_MASK2l       (0xf)\n#define BN_MASK2h1      (0xf8)\n#define BN_MASK2h       (0xf0)\n#define BN_TBIT         (0x80)\n#define BN_DEC_CONV     (100)\n#define BN_DEC_FMT1     \"%u\"\n#define BN_DEC_FMT2     \"%02u\"\n#define BN_DEC_NUM      2\n#endif\n\n#define BN_DEFAULT_BITS 1280\n\n#ifdef BIGNUM\n#undef BIGNUM\n#endif\n\n#define BN_FLG_MALLOCED         0x01\n#define BN_FLG_STATIC_DATA      0x02\n#define BN_FLG_FREE             0x8000  /* used for debuging */\n#define BN_set_flags(b,n)       ((b)->flags|=(n))\n#define BN_get_flags(b,n)       ((b)->flags&(n))\n\ntypedef struct bignum_st\n\t{\n\tBN_ULONG *d;    /* Pointer to an array of 'BN_BITS2' bit chunks. */\n\tint top;        /* Index of last used d +1. */\n\t/* The next are internal book keeping for bn_expand. */\n\tint dmax;       /* Size of the d array. */\n\tint neg;        /* one if the number is negative */\n\tint flags;\n\t} BIGNUM;\n\n/* Used for temp variables */\n#define BN_CTX_NUM      12\n#define BN_CTX_NUM_POS  12\ntypedef struct bignum_ctx\n\t{\n\tint tos;\n\tBIGNUM bn[BN_CTX_NUM];\n\tint flags;\n\tint depth;\n\tint pos[BN_CTX_NUM_POS];\n\tint too_many;\n\t} BN_CTX;\n\n/* Used for montgomery multiplication */\ntypedef struct bn_mont_ctx_st\n\t{\n\tint ri;        /* number of bits in R */\n\tBIGNUM RR;     /* used to convert to montgomery form */\n\tBIGNUM N;      /* The modulus */\n\tBIGNUM Ni;     /* R*(1/R mod N) - N*Ni = 1\n\t\t\t* (Ni is only stored for bignum algorithm) */\n\tBN_ULONG n0;   /* least significant word of Ni */\n\tint flags;\n\t} BN_MONT_CTX;\n\n/* Used for reciprocal division/mod functions\n * It cannot be shared between threads\n */\ntypedef struct bn_recp_ctx_st\n\t{\n\tBIGNUM N;       /* the divisor */\n\tBIGNUM Nr;      /* the reciprocal */\n\tint num_bits;\n\tint shift;\n\tint flags;\n\t} BN_RECP_CTX;\n\n#define BN_to_montgomery(r,a,mont,ctx)  BN_mod_mul_montgomery(\\\n\tr,a,&((mont)->RR),(mont),ctx)\n\n#define BN_prime_checks 0 /* default: select number of iterations\n\t\t\t     based on the size of the number */\n\n/* number of Miller-Rabin iterations for an error rate  of less than 2^-80\n * for random 'b'-bit input, b >= 100 (taken from table 4.4 in the Handbook\n * of Applied Cryptography [Menezes, van Oorschot, Vanstone; CRC Press 1996];\n * original paper: Damgaard, Landrock, Pomerance: Average case error estimates\n * for the strong probable prime test. -- Math. Comp. 61 (1993) 177-194) */\n#define BN_prime_checks_for_size(b) ((b) >= 1300 ?  2 : \\\n\t\t\t\t(b) >=  850 ?  3 : \\\n\t\t\t\t(b) >=  650 ?  4 : \\\n\t\t\t\t(b) >=  550 ?  5 : \\\n\t\t\t\t(b) >=  450 ?  6 : \\\n\t\t\t\t(b) >=  400 ?  7 : \\\n\t\t\t\t(b) >=  350 ?  8 : \\\n\t\t\t\t(b) >=  300 ?  9 : \\\n\t\t\t\t(b) >=  250 ? 12 : \\\n\t\t\t\t(b) >=  200 ? 15 : \\\n\t\t\t\t(b) >=  150 ? 18 : \\\n\t\t\t\t/* b >= 100 */ 27)\n\n#define BN_num_bytes(a) ((BN_num_bits(a)+7)/8)\n#define BN_is_word(a,w) (((a)->top == 1) && ((a)->d[0] == (BN_ULONG)(w)))\n#define BN_is_zero(a)   (((a)->top == 0) || BN_is_word(a,0))\n#define BN_is_one(a)    (BN_is_word((a),1))\n#define BN_is_odd(a)    (((a)->top > 0) && ((a)->d[0] & 1))\n#define BN_one(a)       (BN_set_word((a),1))\n#define BN_zero(a)      (BN_set_word((a),0))\n\nBIGNUM *BN_value_one(void);\nchar *  BN_options(void);\nBN_CTX *BN_CTX_new(void);\nvoid    BN_CTX_init(BN_CTX *c);\nvoid    BN_CTX_free(BN_CTX *c);\nvoid    BN_CTX_start(BN_CTX *ctx);\nBIGNUM *BN_CTX_get(BN_CTX *ctx);\nvoid    BN_CTX_end(BN_CTX *ctx);\nint     BN_rand(BIGNUM *rnd, int bits, int top,int bottom);\nint     BN_pseudo_rand(BIGNUM *rnd, int bits, int top,int bottom);\nint     BN_num_bits(const BIGNUM *a);\nint     BN_num_bits_word(BN_ULONG);\nBIGNUM *BN_new(void);\nvoid    BN_init(BIGNUM *);\nvoid    BN_clear_free(BIGNUM *a);\nBIGNUM *BN_copy(BIGNUM *a, const BIGNUM *b);\nBIGNUM *BN_bin2bn(const unsigned char *s,int len,BIGNUM *ret);\nint     BN_bn2bin(const BIGNUM *a, unsigned char *to);\nint     BN_sub(BIGNUM *r, const BIGNUM *a, const BIGNUM *b);\nint     BN_usub(BIGNUM *r, const BIGNUM *a, const BIGNUM *b);\nint     BN_uadd(BIGNUM *r, const BIGNUM *a, const BIGNUM *b);\nint     BN_add(BIGNUM *r, const BIGNUM *a, const BIGNUM *b);\nint     BN_mod(BIGNUM *rem, const BIGNUM *m, const BIGNUM *d, BN_CTX *ctx);\nint     BN_div(BIGNUM *dv, BIGNUM *rem, const BIGNUM *m, const BIGNUM *d,\n\t       BN_CTX *ctx);\nint     BN_mul(BIGNUM *r, BIGNUM *a, BIGNUM *b, BN_CTX *ctx);\nint     BN_sqr(BIGNUM *r, BIGNUM *a,BN_CTX *ctx);\nBN_ULONG BN_mod_word(const BIGNUM *a, BN_ULONG w);\nBN_ULONG BN_div_word(BIGNUM *a, BN_ULONG w);\nint     BN_mul_word(BIGNUM *a, BN_ULONG w);\nint     BN_add_word(BIGNUM *a, BN_ULONG w);\nint     BN_sub_word(BIGNUM *a, BN_ULONG w);\nint     BN_set_word(BIGNUM *a, BN_ULONG w);\nBN_ULONG BN_get_word(BIGNUM *a);\nint     BN_cmp(const BIGNUM *a, const BIGNUM *b);\nvoid    BN_free(BIGNUM *a);\nint     BN_is_bit_set(const BIGNUM *a, int n);\nint     BN_lshift(BIGNUM *r, const BIGNUM *a, int n);\nint     BN_lshift1(BIGNUM *r, BIGNUM *a);\nint     BN_exp(BIGNUM *r, BIGNUM *a, BIGNUM *p,BN_CTX *ctx);\nint     BN_mod_exp(BIGNUM *r, BIGNUM *a, const BIGNUM *p,\n\t\t   const BIGNUM *m,BN_CTX *ctx);\nint     BN_mod_exp_mont(BIGNUM *r, BIGNUM *a, const BIGNUM *p,\n\t\t\tconst BIGNUM *m, BN_CTX *ctx, BN_MONT_CTX *m_ctx);\nint     BN_mod_exp_mont_word(BIGNUM *r, BN_ULONG a, const BIGNUM *p,\n\t\t\tconst BIGNUM *m, BN_CTX *ctx, BN_MONT_CTX *m_ctx);\nint     BN_mod_exp_simple(BIGNUM *r, const BIGNUM *a, const BIGNUM *p,\n\tconst BIGNUM *m,BN_CTX *ctx);\nint     BN_mask_bits(BIGNUM *a,int n);\nint     BN_mod_mul(BIGNUM *ret, BIGNUM *a, BIGNUM *b, const BIGNUM *m, BN_CTX *ctx);\nint     BN_reciprocal(BIGNUM *r, BIGNUM *m, int len, BN_CTX *ctx);\nint     BN_rshift(BIGNUM *r, BIGNUM *a, int n);\nint     BN_rshift1(BIGNUM *r, BIGNUM *a);\nvoid    BN_clear(BIGNUM *a);\nBIGNUM *BN_dup(const BIGNUM *a);\nint     BN_ucmp(const BIGNUM *a, const BIGNUM *b);\nint     BN_set_bit(BIGNUM *a, int n);\nint     BN_clear_bit(BIGNUM *a, int n);\nint     BN_gcd(BIGNUM *r,BIGNUM *in_a,BIGNUM *in_b,BN_CTX *ctx);\nBIGNUM *BN_mod_inverse(BIGNUM *ret,BIGNUM *a, const BIGNUM *n,BN_CTX *ctx);\nBIGNUM *BN_generate_prime(BIGNUM *ret,int bits,int safe,BIGNUM *add,\n\t\tBIGNUM *rem,void (*callback)(int,int,void *),void *cb_arg);\nint     BN_is_prime(const BIGNUM *p,int nchecks,\n\t\tvoid (*callback)(int,int,void *),\n\t\tBN_CTX *ctx,void *cb_arg);\nint     BN_is_prime_fasttest(const BIGNUM *p,int nchecks,\n\t\tvoid (*callback)(int,int,void *),BN_CTX *ctx,void *cb_arg,\n\t\tint do_trial_division);\n\nBN_MONT_CTX *BN_MONT_CTX_new(void );\nvoid BN_MONT_CTX_init(BN_MONT_CTX *ctx);\nint BN_mod_mul_montgomery(BIGNUM *r,BIGNUM *a,BIGNUM *b,BN_MONT_CTX *mont,\n\t\t\t  BN_CTX *ctx);\nint BN_from_montgomery(BIGNUM *r,BIGNUM *a,BN_MONT_CTX *mont,BN_CTX *ctx);\nvoid BN_MONT_CTX_free(BN_MONT_CTX *mont);\nint BN_MONT_CTX_set(BN_MONT_CTX *mont,const BIGNUM *modulus,BN_CTX *ctx);\nBN_MONT_CTX *BN_MONT_CTX_copy(BN_MONT_CTX *to,BN_MONT_CTX *from);\n\nvoid BN_set_params(int mul,int high,int low,int mont);\nint BN_get_params(int which); /* 0, mul, 1 high, 2 low, 3 mont */\n\nvoid    BN_RECP_CTX_init(BN_RECP_CTX *recp);\nBN_RECP_CTX *BN_RECP_CTX_new(void);\nvoid    BN_RECP_CTX_free(BN_RECP_CTX *recp);\nint     BN_RECP_CTX_set(BN_RECP_CTX *recp,const BIGNUM *rdiv,BN_CTX *ctx);\nint     BN_mod_mul_reciprocal(BIGNUM *r, BIGNUM *x, BIGNUM *y,\n\t\tBN_RECP_CTX *recp,BN_CTX *ctx);\nint     BN_mod_exp_recp(BIGNUM *r, const BIGNUM *a, const BIGNUM *p,\n\t\t\tconst BIGNUM *m, BN_CTX *ctx);\nint     BN_div_recp(BIGNUM *dv, BIGNUM *rem, BIGNUM *m,\n\t\tBN_RECP_CTX *recp, BN_CTX *ctx);\n\n/* library internal functions */\n\n#define bn_expand(a,bits) ((((((bits+BN_BITS2-1))/BN_BITS2)) <= (a)->dmax)?\\\n\t(a):bn_expand2((a),(bits)/BN_BITS2+1))\n#define bn_wexpand(a,words) (((words) <= (a)->dmax)?(a):bn_expand2((a),(words)))\nBIGNUM *bn_expand2(BIGNUM *a, int words);\n\n#define bn_fix_top(a) \\\n\t{ \\\n\tBN_ULONG *ftl; \\\n\tif ((a)->top > 0) \\\n\t\t{ \\\n\t\tfor (ftl= &((a)->d[(a)->top-1]); (a)->top > 0; (a)->top--) \\\n\t\tif (*(ftl--)) break; \\\n\t\t} \\\n\t}\n\nBN_ULONG bn_mul_add_words(BN_ULONG *rp, BN_ULONG *ap, int num, BN_ULONG w);\nBN_ULONG bn_mul_words(BN_ULONG *rp, BN_ULONG *ap, int num, BN_ULONG w);\nvoid     bn_sqr_words(BN_ULONG *rp, BN_ULONG *ap, int num);\nBN_ULONG bn_div_words(BN_ULONG h, BN_ULONG l, BN_ULONG d);\nBN_ULONG bn_add_words(BN_ULONG *rp, BN_ULONG *ap, BN_ULONG *bp,int num);\nBN_ULONG bn_sub_words(BN_ULONG *rp, BN_ULONG *ap, BN_ULONG *bp,int num);\n\n#ifdef BN_DEBUG\n  void bn_dump1(FILE *o, const char *a, BN_ULONG *b,int n);\n# define bn_print(a) {fprintf(stderr, #a \"=\"); BN_print_fp(stderr,a); \\\n   fprintf(stderr,\"\\n\");}\n# define bn_dump(a,n) bn_dump1(stderr,#a,a,n);\n#else\n# define bn_print(a)\n# define bn_dump(a,b)\n#endif\n\n/* BEGIN ERROR CODES */\n/* The following lines are auto generated by the script mkerr.pl. Any changes\n * made after this point may be overwritten when the script is next run.\n */\n\n/* Error codes for the BN functions. */\n\n/* Function codes. */\n#define BN_F_BN_CTX_GET                                  116\n#define BN_F_BN_CTX_NEW                                  106\n#define BN_F_BN_DIV                                      107\n#define BN_F_BN_EXPAND2                                  108\n#define BN_F_BN_MOD_EXP2_MONT                            118\n#define BN_F_BN_MOD_EXP_MONT                             109\n#define BN_F_BN_MOD_EXP_MONT_WORD                        117\n#define BN_F_BN_MOD_INVERSE                              110\n#define BN_F_BN_MOD_MUL_RECIPROCAL                       111\n#define BN_F_BN_MPI2BN                                   112\n#define BN_F_BN_NEW                                      113\n#define BN_F_BN_RAND                                     114\n#define BN_F_BN_USUB                                     115\n\n/* Reason codes. */\n#define BN_R_ARG2_LT_ARG3                                100\n#define BN_R_BAD_RECIPROCAL                              101\n#define BN_R_CALLED_WITH_EVEN_MODULUS                    102\n#define BN_R_DIV_BY_ZERO                                 103\n#define BN_R_ENCODING_ERROR                              104\n#define BN_R_EXPAND_ON_STATIC_BIGNUM_DATA                105\n#define BN_R_INVALID_LENGTH                              106\n#define BN_R_NOT_INITIALIZED                             107\n#define BN_R_NO_INVERSE                                  108\n#define BN_R_TOO_MANY_TEMPORARY_VARIABLES                109\n\n#ifdef  __cplusplus\n}\n#endif\n#endif\n\n"
  },
  {
    "path": "package/network/services/ead/src/tinysrp/bn_add.c",
    "content": "/* crypto/bn/bn_add.c */\n/* Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)\n * All rights reserved.\n *\n * This package is an SSL implementation written\n * by Eric Young (eay@cryptsoft.com).\n * The implementation was written so as to conform with Netscapes SSL.\n *\n * This library is free for commercial and non-commercial use as long as\n * the following conditions are aheared to.  The following conditions\n * apply to all code found in this distribution, be it the RC4, RSA,\n * lhash, DES, etc., code; not just the SSL code.  The SSL documentation\n * included with this distribution is covered by the same copyright terms\n * except that the holder is Tim Hudson (tjh@cryptsoft.com).\n *\n * Copyright remains Eric Young's, and as such any Copyright notices in\n * the code are not to be removed.\n * If this package is used in a product, Eric Young should be given attribution\n * as the author of the parts of the library used.\n * This can be in the form of a textual message at program startup or\n * in documentation (online or textual) provided with the package.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. All advertising materials mentioning features or use of this software\n *    must display the following acknowledgement:\n *    \"This product includes cryptographic software written by\n *     Eric Young (eay@cryptsoft.com)\"\n *    The word 'cryptographic' can be left out if the rouines from the library\n *    being used are not cryptographic related :-).\n * 4. If you include any Windows specific code (or a derivative thereof) from\n *    the apps directory (application code) you must include an acknowledgement:\n *    \"This product includes software written by Tim Hudson (tjh@cryptsoft.com)\"\n *\n * THIS SOFTWARE IS PROVIDED BY ERIC YOUNG ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n *\n * The licence and distribution terms for any publically available version or\n * derivative of this code cannot be changed.  i.e. this code cannot simply be\n * copied and put under another distribution licence\n * [including the GNU Public Licence.]\n */\n\n#include <stdio.h>\n#include \"bn_lcl.h\"\n\n/* r can == a or b */\nint BN_add(BIGNUM *r, const BIGNUM *a, const BIGNUM *b)\n\t{\n\tconst BIGNUM *tmp;\n\n\tbn_check_top(a);\n\tbn_check_top(b);\n\n\t/*  a +  b      a+b\n\t *  a + -b      a-b\n\t * -a +  b      b-a\n\t * -a + -b      -(a+b)\n\t */\n\tif (a->neg ^ b->neg)\n\t\t{\n\t\t/* only one is negative */\n\t\tif (a->neg)\n\t\t\t{ tmp=a; a=b; b=tmp; }\n\n\t\t/* we are now a - b */\n\n\t\tif (BN_ucmp(a,b) < 0)\n\t\t\t{\n\t\t\tif (!BN_usub(r,b,a)) return(0);\n\t\t\tr->neg=1;\n\t\t\t}\n\t\telse\n\t\t\t{\n\t\t\tif (!BN_usub(r,a,b)) return(0);\n\t\t\tr->neg=0;\n\t\t\t}\n\t\treturn(1);\n\t\t}\n\n\tif (a->neg) /* both are neg */\n\t\tr->neg=1;\n\telse\n\t\tr->neg=0;\n\n\tif (!BN_uadd(r,a,b)) return(0);\n\treturn(1);\n\t}\n\n/* unsigned add of b to a, r must be large enough */\nint BN_uadd(BIGNUM *r, const BIGNUM *a, const BIGNUM *b)\n\t{\n\tregister int i;\n\tint max,min;\n\tBN_ULONG *ap,*bp,*rp,carry,t1;\n\tconst BIGNUM *tmp;\n\n\tbn_check_top(a);\n\tbn_check_top(b);\n\n\tif (a->top < b->top)\n\t\t{ tmp=a; a=b; b=tmp; }\n\tmax=a->top;\n\tmin=b->top;\n\n\tif (bn_wexpand(r,max+1) == NULL)\n\t\treturn(0);\n\n\tr->top=max;\n\n\n\tap=a->d;\n\tbp=b->d;\n\trp=r->d;\n\tcarry=0;\n\n\tcarry=bn_add_words(rp,ap,bp,min);\n\trp+=min;\n\tap+=min;\n\tbp+=min;\n\ti=min;\n\n\tif (carry)\n\t\t{\n\t\twhile (i < max)\n\t\t\t{\n\t\t\ti++;\n\t\t\tt1= *(ap++);\n\t\t\tif ((*(rp++)=(t1+1)&BN_MASK2) >= t1)\n\t\t\t\t{\n\t\t\t\tcarry=0;\n\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t}\n\t\tif ((i >= max) && carry)\n\t\t\t{\n\t\t\t*(rp++)=1;\n\t\t\tr->top++;\n\t\t\t}\n\t\t}\n\tif (rp != ap)\n\t\t{\n\t\tfor (; i<max; i++)\n\t\t\t*(rp++)= *(ap++);\n\t\t}\n\t/* memcpy(rp,ap,sizeof(*ap)*(max-i));*/\n\treturn(1);\n\t}\n\n/* unsigned subtraction of b from a, a must be larger than b. */\nint BN_usub(BIGNUM *r, const BIGNUM *a, const BIGNUM *b)\n\t{\n\tint max,min;\n\tregister BN_ULONG t1,t2,*ap,*bp,*rp;\n\tint i,carry;\n#if defined(IRIX_CC_BUG) && !defined(LINT)\n\tint dummy;\n#endif\n\n\tbn_check_top(a);\n\tbn_check_top(b);\n\n\tif (a->top < b->top) /* hmm... should not be happening */\n\t\t{\n\t\treturn(0);\n\t\t}\n\n\tmax=a->top;\n\tmin=b->top;\n\tif (bn_wexpand(r,max) == NULL) return(0);\n\n\tap=a->d;\n\tbp=b->d;\n\trp=r->d;\n\n#if 1\n\tcarry=0;\n\tfor (i=0; i<min; i++)\n\t\t{\n\t\tt1= *(ap++);\n\t\tt2= *(bp++);\n\t\tif (carry)\n\t\t\t{\n\t\t\tcarry=(t1 <= t2);\n\t\t\tt1=(t1-t2-1)&BN_MASK2;\n\t\t\t}\n\t\telse\n\t\t\t{\n\t\t\tcarry=(t1 < t2);\n\t\t\tt1=(t1-t2)&BN_MASK2;\n\t\t\t}\n#if defined(IRIX_CC_BUG) && !defined(LINT)\n\t\tdummy=t1;\n#endif\n\t\t*(rp++)=t1&BN_MASK2;\n\t\t}\n#else\n\tcarry=bn_sub_words(rp,ap,bp,min);\n\tap+=min;\n\tbp+=min;\n\trp+=min;\n\ti=min;\n#endif\n\tif (carry) /* subtracted */\n\t\t{\n\t\twhile (i < max)\n\t\t\t{\n\t\t\ti++;\n\t\t\tt1= *(ap++);\n\t\t\tt2=(t1-1)&BN_MASK2;\n\t\t\t*(rp++)=t2;\n\t\t\tif (t1 > t2) break;\n\t\t\t}\n\t\t}\n#if 0\n\tmemcpy(rp,ap,sizeof(*rp)*(max-i));\n#else\n\tif (rp != ap)\n\t\t{\n\t\tfor (;;)\n\t\t\t{\n\t\t\tif (i++ >= max) break;\n\t\t\trp[0]=ap[0];\n\t\t\tif (i++ >= max) break;\n\t\t\trp[1]=ap[1];\n\t\t\tif (i++ >= max) break;\n\t\t\trp[2]=ap[2];\n\t\t\tif (i++ >= max) break;\n\t\t\trp[3]=ap[3];\n\t\t\trp+=4;\n\t\t\tap+=4;\n\t\t\t}\n\t\t}\n#endif\n\n\tr->top=max;\n\tbn_fix_top(r);\n\treturn(1);\n\t}\n\nint BN_sub(BIGNUM *r, const BIGNUM *a, const BIGNUM *b)\n\t{\n\tint max;\n\tint add=0,neg=0;\n\tconst BIGNUM *tmp;\n\n\tbn_check_top(a);\n\tbn_check_top(b);\n\n\t/*  a -  b      a-b\n\t *  a - -b      a+b\n\t * -a -  b      -(a+b)\n\t * -a - -b      b-a\n\t */\n\tif (a->neg)\n\t\t{\n\t\tif (b->neg)\n\t\t\t{ tmp=a; a=b; b=tmp; }\n\t\telse\n\t\t\t{ add=1; neg=1; }\n\t\t}\n\telse\n\t\t{\n\t\tif (b->neg) { add=1; neg=0; }\n\t\t}\n\n\tif (add)\n\t\t{\n\t\tif (!BN_uadd(r,a,b)) return(0);\n\t\tr->neg=neg;\n\t\treturn(1);\n\t\t}\n\n\t/* We are actually doing a - b :-) */\n\n\tmax=(a->top > b->top)?a->top:b->top;\n\tif (bn_wexpand(r,max) == NULL) return(0);\n\tif (BN_ucmp(a,b) < 0)\n\t\t{\n\t\tif (!BN_usub(r,b,a)) return(0);\n\t\tr->neg=1;\n\t\t}\n\telse\n\t\t{\n\t\tif (!BN_usub(r,a,b)) return(0);\n\t\tr->neg=0;\n\t\t}\n\treturn(1);\n\t}\n\n"
  },
  {
    "path": "package/network/services/ead/src/tinysrp/bn_asm.c",
    "content": "/* crypto/bn/bn_asm.c */\n/* Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)\n * All rights reserved.\n *\n * This package is an SSL implementation written\n * by Eric Young (eay@cryptsoft.com).\n * The implementation was written so as to conform with Netscapes SSL.\n *\n * This library is free for commercial and non-commercial use as long as\n * the following conditions are aheared to.  The following conditions\n * apply to all code found in this distribution, be it the RC4, RSA,\n * lhash, DES, etc., code; not just the SSL code.  The SSL documentation\n * included with this distribution is covered by the same copyright terms\n * except that the holder is Tim Hudson (tjh@cryptsoft.com).\n *\n * Copyright remains Eric Young's, and as such any Copyright notices in\n * the code are not to be removed.\n * If this package is used in a product, Eric Young should be given attribution\n * as the author of the parts of the library used.\n * This can be in the form of a textual message at program startup or\n * in documentation (online or textual) provided with the package.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. All advertising materials mentioning features or use of this software\n *    must display the following acknowledgement:\n *    \"This product includes cryptographic software written by\n *     Eric Young (eay@cryptsoft.com)\"\n *    The word 'cryptographic' can be left out if the rouines from the library\n *    being used are not cryptographic related :-).\n * 4. If you include any Windows specific code (or a derivative thereof) from\n *    the apps directory (application code) you must include an acknowledgement:\n *    \"This product includes software written by Tim Hudson (tjh@cryptsoft.com)\"\n *\n * THIS SOFTWARE IS PROVIDED BY ERIC YOUNG ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n *\n * The licence and distribution terms for any publically available version or\n * derivative of this code cannot be changed.  i.e. this code cannot simply be\n * copied and put under another distribution licence\n * [including the GNU Public Licence.]\n */\n\n#ifndef BN_DEBUG\n# undef NDEBUG /* avoid conflicting definitions */\n# define NDEBUG\n#endif\n\n#include <stdio.h>\n#include <assert.h>\n#include \"bn_lcl.h\"\n\n#if defined(BN_LLONG) || defined(BN_UMULT_HIGH)\n\nBN_ULONG bn_mul_add_words(BN_ULONG *rp, BN_ULONG *ap, int num, BN_ULONG w)\n\t{\n\tBN_ULONG c1=0;\n\n\tassert(num >= 0);\n\tif (num <= 0) return(c1);\n\n\twhile (num&~3)\n\t\t{\n\t\tmul_add(rp[0],ap[0],w,c1);\n\t\tmul_add(rp[1],ap[1],w,c1);\n\t\tmul_add(rp[2],ap[2],w,c1);\n\t\tmul_add(rp[3],ap[3],w,c1);\n\t\tap+=4; rp+=4; num-=4;\n\t\t}\n\tif (num)\n\t\t{\n\t\tmul_add(rp[0],ap[0],w,c1); if (--num==0) return c1;\n\t\tmul_add(rp[1],ap[1],w,c1); if (--num==0) return c1;\n\t\tmul_add(rp[2],ap[2],w,c1); return c1;\n\t\t}\n\n\treturn(c1);\n\t}\n\nBN_ULONG bn_mul_words(BN_ULONG *rp, BN_ULONG *ap, int num, BN_ULONG w)\n\t{\n\tBN_ULONG c1=0;\n\n\tassert(num >= 0);\n\tif (num <= 0) return(c1);\n\n\twhile (num&~3)\n\t\t{\n\t\tmul(rp[0],ap[0],w,c1);\n\t\tmul(rp[1],ap[1],w,c1);\n\t\tmul(rp[2],ap[2],w,c1);\n\t\tmul(rp[3],ap[3],w,c1);\n\t\tap+=4; rp+=4; num-=4;\n\t\t}\n\tif (num)\n\t\t{\n\t\tmul(rp[0],ap[0],w,c1); if (--num == 0) return c1;\n\t\tmul(rp[1],ap[1],w,c1); if (--num == 0) return c1;\n\t\tmul(rp[2],ap[2],w,c1);\n\t\t}\n\treturn(c1);\n\t}\n\nvoid bn_sqr_words(BN_ULONG *r, BN_ULONG *a, int n)\n\t{\n\tassert(n >= 0);\n\tif (n <= 0) return;\n\twhile (n&~3)\n\t\t{\n\t\tsqr(r[0],r[1],a[0]);\n\t\tsqr(r[2],r[3],a[1]);\n\t\tsqr(r[4],r[5],a[2]);\n\t\tsqr(r[6],r[7],a[3]);\n\t\ta+=4; r+=8; n-=4;\n\t\t}\n\tif (n)\n\t\t{\n\t\tsqr(r[0],r[1],a[0]); if (--n == 0) return;\n\t\tsqr(r[2],r[3],a[1]); if (--n == 0) return;\n\t\tsqr(r[4],r[5],a[2]);\n\t\t}\n\t}\n\n#else /* !(defined(BN_LLONG) || defined(BN_UMULT_HIGH)) */\n\nBN_ULONG bn_mul_add_words(BN_ULONG *rp, BN_ULONG *ap, int num, BN_ULONG w)\n\t{\n\tBN_ULONG c=0;\n\tBN_ULONG bl,bh;\n\n\tassert(num >= 0);\n\tif (num <= 0) return((BN_ULONG)0);\n\n\tbl=LBITS(w);\n\tbh=HBITS(w);\n\n\tfor (;;)\n\t\t{\n\t\tmul_add(rp[0],ap[0],bl,bh,c);\n\t\tif (--num == 0) break;\n\t\tmul_add(rp[1],ap[1],bl,bh,c);\n\t\tif (--num == 0) break;\n\t\tmul_add(rp[2],ap[2],bl,bh,c);\n\t\tif (--num == 0) break;\n\t\tmul_add(rp[3],ap[3],bl,bh,c);\n\t\tif (--num == 0) break;\n\t\tap+=4;\n\t\trp+=4;\n\t\t}\n\treturn(c);\n\t}\n\nBN_ULONG bn_mul_words(BN_ULONG *rp, BN_ULONG *ap, int num, BN_ULONG w)\n\t{\n\tBN_ULONG carry=0;\n\tBN_ULONG bl,bh;\n\n\tassert(num >= 0);\n\tif (num <= 0) return((BN_ULONG)0);\n\n\tbl=LBITS(w);\n\tbh=HBITS(w);\n\n\tfor (;;)\n\t\t{\n\t\tmul(rp[0],ap[0],bl,bh,carry);\n\t\tif (--num == 0) break;\n\t\tmul(rp[1],ap[1],bl,bh,carry);\n\t\tif (--num == 0) break;\n\t\tmul(rp[2],ap[2],bl,bh,carry);\n\t\tif (--num == 0) break;\n\t\tmul(rp[3],ap[3],bl,bh,carry);\n\t\tif (--num == 0) break;\n\t\tap+=4;\n\t\trp+=4;\n\t\t}\n\treturn(carry);\n\t}\n\nvoid bn_sqr_words(BN_ULONG *r, BN_ULONG *a, int n)\n\t{\n\tassert(n >= 0);\n\tif (n <= 0) return;\n\tfor (;;)\n\t\t{\n\t\tsqr64(r[0],r[1],a[0]);\n\t\tif (--n == 0) break;\n\n\t\tsqr64(r[2],r[3],a[1]);\n\t\tif (--n == 0) break;\n\n\t\tsqr64(r[4],r[5],a[2]);\n\t\tif (--n == 0) break;\n\n\t\tsqr64(r[6],r[7],a[3]);\n\t\tif (--n == 0) break;\n\n\t\ta+=4;\n\t\tr+=8;\n\t\t}\n\t}\n\n#endif /* !(defined(BN_LLONG) || defined(BN_UMULT_HIGH)) */\n\n#if defined(BN_LLONG) && defined(BN_DIV2W)\n\nBN_ULONG bn_div_words(BN_ULONG h, BN_ULONG l, BN_ULONG d)\n\t{\n\treturn((BN_ULONG)(((((BN_ULLONG)h)<<BN_BITS2)|l)/(BN_ULLONG)d));\n\t}\n\n#else\n\n/* Divide h,l by d and return the result. */\n/* I need to test this some more :-( */\nBN_ULONG bn_div_words(BN_ULONG h, BN_ULONG l, BN_ULONG d)\n\t{\n\tBN_ULONG dh,dl,q,ret=0,th,tl,t;\n\tint i,count=2;\n\n\tif (d == 0) return(BN_MASK2);\n\n\ti=BN_num_bits_word(d);\n\tassert((i == BN_BITS2) || (h > (BN_ULONG)1<<i));\n\n\ti=BN_BITS2-i;\n\tif (h >= d) h-=d;\n\n\tif (i)\n\t\t{\n\t\td<<=i;\n\t\th=(h<<i)|(l>>(BN_BITS2-i));\n\t\tl<<=i;\n\t\t}\n\tdh=(d&BN_MASK2h)>>BN_BITS4;\n\tdl=(d&BN_MASK2l);\n\tfor (;;)\n\t\t{\n\t\tif ((h>>BN_BITS4) == dh)\n\t\t\tq=BN_MASK2l;\n\t\telse\n\t\t\tq=h/dh;\n\n\t\tth=q*dh;\n\t\ttl=dl*q;\n\t\tfor (;;)\n\t\t\t{\n\t\t\tt=h-th;\n\t\t\tif ((t&BN_MASK2h) ||\n\t\t\t\t((tl) <= (\n\t\t\t\t\t(t<<BN_BITS4)|\n\t\t\t\t\t((l&BN_MASK2h)>>BN_BITS4))))\n\t\t\t\tbreak;\n\t\t\tq--;\n\t\t\tth-=dh;\n\t\t\ttl-=dl;\n\t\t\t}\n\t\tt=(tl>>BN_BITS4);\n\t\ttl=(tl<<BN_BITS4)&BN_MASK2h;\n\t\tth+=t;\n\n\t\tif (l < tl) th++;\n\t\tl-=tl;\n\t\tif (h < th)\n\t\t\t{\n\t\t\th+=d;\n\t\t\tq--;\n\t\t\t}\n\t\th-=th;\n\n\t\tif (--count == 0) break;\n\n\t\tret=q<<BN_BITS4;\n\t\th=((h<<BN_BITS4)|(l>>BN_BITS4))&BN_MASK2;\n\t\tl=(l&BN_MASK2l)<<BN_BITS4;\n\t\t}\n\tret|=q;\n\treturn(ret);\n\t}\n#endif /* !defined(BN_LLONG) && defined(BN_DIV2W) */\n\n#ifdef BN_LLONG\nBN_ULONG bn_add_words(BN_ULONG *r, BN_ULONG *a, BN_ULONG *b, int n)\n\t{\n\tBN_ULLONG ll=0;\n\n\tassert(n >= 0);\n\tif (n <= 0) return((BN_ULONG)0);\n\n\tfor (;;)\n\t\t{\n\t\tll+=(BN_ULLONG)a[0]+b[0];\n\t\tr[0]=(BN_ULONG)ll&BN_MASK2;\n\t\tll>>=BN_BITS2;\n\t\tif (--n <= 0) break;\n\n\t\tll+=(BN_ULLONG)a[1]+b[1];\n\t\tr[1]=(BN_ULONG)ll&BN_MASK2;\n\t\tll>>=BN_BITS2;\n\t\tif (--n <= 0) break;\n\n\t\tll+=(BN_ULLONG)a[2]+b[2];\n\t\tr[2]=(BN_ULONG)ll&BN_MASK2;\n\t\tll>>=BN_BITS2;\n\t\tif (--n <= 0) break;\n\n\t\tll+=(BN_ULLONG)a[3]+b[3];\n\t\tr[3]=(BN_ULONG)ll&BN_MASK2;\n\t\tll>>=BN_BITS2;\n\t\tif (--n <= 0) break;\n\n\t\ta+=4;\n\t\tb+=4;\n\t\tr+=4;\n\t\t}\n\treturn((BN_ULONG)ll);\n\t}\n#else /* !BN_LLONG */\nBN_ULONG bn_add_words(BN_ULONG *r, BN_ULONG *a, BN_ULONG *b, int n)\n\t{\n\tBN_ULONG c,l,t;\n\n\tassert(n >= 0);\n\tif (n <= 0) return((BN_ULONG)0);\n\n\tc=0;\n\tfor (;;)\n\t\t{\n\t\tt=a[0];\n\t\tt=(t+c)&BN_MASK2;\n\t\tc=(t < c);\n\t\tl=(t+b[0])&BN_MASK2;\n\t\tc+=(l < t);\n\t\tr[0]=l;\n\t\tif (--n <= 0) break;\n\n\t\tt=a[1];\n\t\tt=(t+c)&BN_MASK2;\n\t\tc=(t < c);\n\t\tl=(t+b[1])&BN_MASK2;\n\t\tc+=(l < t);\n\t\tr[1]=l;\n\t\tif (--n <= 0) break;\n\n\t\tt=a[2];\n\t\tt=(t+c)&BN_MASK2;\n\t\tc=(t < c);\n\t\tl=(t+b[2])&BN_MASK2;\n\t\tc+=(l < t);\n\t\tr[2]=l;\n\t\tif (--n <= 0) break;\n\n\t\tt=a[3];\n\t\tt=(t+c)&BN_MASK2;\n\t\tc=(t < c);\n\t\tl=(t+b[3])&BN_MASK2;\n\t\tc+=(l < t);\n\t\tr[3]=l;\n\t\tif (--n <= 0) break;\n\n\t\ta+=4;\n\t\tb+=4;\n\t\tr+=4;\n\t\t}\n\treturn((BN_ULONG)c);\n\t}\n#endif /* !BN_LLONG */\n"
  },
  {
    "path": "package/network/services/ead/src/tinysrp/bn_ctx.c",
    "content": "/* crypto/bn/bn_ctx.c */\n/* Written by Ulf Moeller for the OpenSSL project. */\n/* ====================================================================\n * Copyright (c) 1998-2000 The OpenSSL Project.  All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n *\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in\n *    the documentation and/or other materials provided with the\n *    distribution.\n *\n * 3. All advertising materials mentioning features or use of this\n *    software must display the following acknowledgment:\n *    \"This product includes software developed by the OpenSSL Project\n *    for use in the OpenSSL Toolkit. (http://www.openssl.org/)\"\n *\n * 4. The names \"OpenSSL Toolkit\" and \"OpenSSL Project\" must not be used to\n *    endorse or promote products derived from this software without\n *    prior written permission. For written permission, please contact\n *    openssl-core@openssl.org.\n *\n * 5. Products derived from this software may not be called \"OpenSSL\"\n *    nor may \"OpenSSL\" appear in their names without prior written\n *    permission of the OpenSSL Project.\n *\n * 6. Redistributions of any form whatsoever must retain the following\n *    acknowledgment:\n *    \"This product includes software developed by the OpenSSL Project\n *    for use in the OpenSSL Toolkit (http://www.openssl.org/)\"\n *\n * THIS SOFTWARE IS PROVIDED BY THE OpenSSL PROJECT ``AS IS'' AND ANY\n * EXPRESSED OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\n * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE OpenSSL PROJECT OR\n * ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT\n * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\n * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED\n * OF THE POSSIBILITY OF SUCH DAMAGE.\n * ====================================================================\n *\n * This product includes cryptographic software written by Eric Young\n * (eay@cryptsoft.com).  This product includes software written by Tim\n * Hudson (tjh@cryptsoft.com).\n *\n */\n\n#ifndef BN_CTX_DEBUG\n# undef NDEBUG /* avoid conflicting definitions */\n# define NDEBUG\n#endif\n\n#include <stdio.h>\n#include <stdlib.h>\n#include <assert.h>\n#include <bn.h>\n\n\nBN_CTX *BN_CTX_new(void)\n\t{\n\tBN_CTX *ret;\n\n\tret=(BN_CTX *)malloc(sizeof(BN_CTX));\n\tif (ret == NULL)\n\t\t{\n\t\treturn(NULL);\n\t\t}\n\n\tBN_CTX_init(ret);\n\tret->flags=BN_FLG_MALLOCED;\n\treturn(ret);\n\t}\n\nvoid BN_CTX_init(BN_CTX *ctx)\n\t{\n\tint i;\n\tctx->tos = 0;\n\tctx->flags = 0;\n\tctx->depth = 0;\n\tctx->too_many = 0;\n\tfor (i = 0; i < BN_CTX_NUM; i++)\n\t\tBN_init(&(ctx->bn[i]));\n\t}\n\nvoid BN_CTX_free(BN_CTX *ctx)\n\t{\n\tint i;\n\n\tif (ctx == NULL) return;\n\tassert(ctx->depth == 0);\n\n\tfor (i=0; i < BN_CTX_NUM; i++)\n\t\tBN_clear_free(&(ctx->bn[i]));\n\tif (ctx->flags & BN_FLG_MALLOCED)\n\t\tfree(ctx);\n\t}\n\nvoid BN_CTX_start(BN_CTX *ctx)\n\t{\n\tif (ctx->depth < BN_CTX_NUM_POS)\n\t\tctx->pos[ctx->depth] = ctx->tos;\n\tctx->depth++;\n\t}\n\nBIGNUM *BN_CTX_get(BN_CTX *ctx)\n\t{\n\tif (ctx->depth > BN_CTX_NUM_POS || ctx->tos >= BN_CTX_NUM)\n\t\t{\n\t\tif (!ctx->too_many)\n\t\t\t{\n\t\t\t/* disable error code until BN_CTX_end is called: */\n\t\t\tctx->too_many = 1;\n\t\t\t}\n\t\treturn NULL;\n\t\t}\n\treturn (&(ctx->bn[ctx->tos++]));\n\t}\n\nvoid BN_CTX_end(BN_CTX *ctx)\n\t{\n\tif (ctx == NULL) return;\n\tassert(ctx->depth > 0);\n\tif (ctx->depth == 0)\n\t\t/* should never happen, but we can tolerate it if not in\n\t\t * debug mode (could be a 'goto err' in the calling function\n\t\t * before BN_CTX_start was reached) */\n\t\tBN_CTX_start(ctx);\n\n\tctx->too_many = 0;\n\tctx->depth--;\n\tif (ctx->depth < BN_CTX_NUM_POS)\n\t\tctx->tos = ctx->pos[ctx->depth];\n\t}\n"
  },
  {
    "path": "package/network/services/ead/src/tinysrp/bn_div.c",
    "content": "/* crypto/bn/bn_div.c */\n/* Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)\n * All rights reserved.\n *\n * This package is an SSL implementation written\n * by Eric Young (eay@cryptsoft.com).\n * The implementation was written so as to conform with Netscapes SSL.\n *\n * This library is free for commercial and non-commercial use as long as\n * the following conditions are aheared to.  The following conditions\n * apply to all code found in this distribution, be it the RC4, RSA,\n * lhash, DES, etc., code; not just the SSL code.  The SSL documentation\n * included with this distribution is covered by the same copyright terms\n * except that the holder is Tim Hudson (tjh@cryptsoft.com).\n *\n * Copyright remains Eric Young's, and as such any Copyright notices in\n * the code are not to be removed.\n * If this package is used in a product, Eric Young should be given attribution\n * as the author of the parts of the library used.\n * This can be in the form of a textual message at program startup or\n * in documentation (online or textual) provided with the package.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. All advertising materials mentioning features or use of this software\n *    must display the following acknowledgement:\n *    \"This product includes cryptographic software written by\n *     Eric Young (eay@cryptsoft.com)\"\n *    The word 'cryptographic' can be left out if the rouines from the library\n *    being used are not cryptographic related :-).\n * 4. If you include any Windows specific code (or a derivative thereof) from\n *    the apps directory (application code) you must include an acknowledgement:\n *    \"This product includes software written by Tim Hudson (tjh@cryptsoft.com)\"\n *\n * THIS SOFTWARE IS PROVIDED BY ERIC YOUNG ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n *\n * The licence and distribution terms for any publically available version or\n * derivative of this code cannot be changed.  i.e. this code cannot simply be\n * copied and put under another distribution licence\n * [including the GNU Public Licence.]\n */\n\n#include <stdio.h>\n#include \"bn_lcl.h\"\n\n#define NO_ASM\n\n/* The old slow way */\n#if 0\nint BN_div(BIGNUM *dv, BIGNUM *rem, const BIGNUM *m, const BIGNUM *d,\n\t   BN_CTX *ctx)\n\t{\n\tint i,nm,nd;\n\tint ret = 0;\n\tBIGNUM *D;\n\n\tbn_check_top(m);\n\tbn_check_top(d);\n\tif (BN_is_zero(d))\n\t\t{\n\t\treturn(0);\n\t\t}\n\n\tif (BN_ucmp(m,d) < 0)\n\t\t{\n\t\tif (rem != NULL)\n\t\t\t{ if (BN_copy(rem,m) == NULL) return(0); }\n\t\tif (dv != NULL) BN_zero(dv);\n\t\treturn(1);\n\t\t}\n\n\tBN_CTX_start(ctx);\n\tD = BN_CTX_get(ctx);\n\tif (dv == NULL) dv = BN_CTX_get(ctx);\n\tif (rem == NULL) rem = BN_CTX_get(ctx);\n\tif (D == NULL || dv == NULL || rem == NULL)\n\t\tgoto end;\n\n\tnd=BN_num_bits(d);\n\tnm=BN_num_bits(m);\n\tif (BN_copy(D,d) == NULL) goto end;\n\tif (BN_copy(rem,m) == NULL) goto end;\n\n\t/* The next 2 are needed so we can do a dv->d[0]|=1 later\n\t * since BN_lshift1 will only work once there is a value :-) */\n\tBN_zero(dv);\n\tbn_wexpand(dv,1);\n\tdv->top=1;\n\n\tif (!BN_lshift(D,D,nm-nd)) goto end;\n\tfor (i=nm-nd; i>=0; i--)\n\t\t{\n\t\tif (!BN_lshift1(dv,dv)) goto end;\n\t\tif (BN_ucmp(rem,D) >= 0)\n\t\t\t{\n\t\t\tdv->d[0]|=1;\n\t\t\tif (!BN_usub(rem,rem,D)) goto end;\n\t\t\t}\n/* CAN IMPROVE (and have now :=) */\n\t\tif (!BN_rshift1(D,D)) goto end;\n\t\t}\n\trem->neg=BN_is_zero(rem)?0:m->neg;\n\tdv->neg=m->neg^d->neg;\n\tret = 1;\n end:\n\tBN_CTX_end(ctx);\n\treturn(ret);\n\t}\n\n#else\n\n#if !defined(NO_ASM) && !defined(NO_INLINE_ASM) && !defined(PEDANTIC) && !defined(BN_DIV3W)\n# if defined(__GNUC__) && __GNUC__>=2\n#  if defined(__i386)\n   /*\n    * There were two reasons for implementing this template:\n    * - GNU C generates a call to a function (__udivdi3 to be exact)\n    *   in reply to ((((BN_ULLONG)n0)<<BN_BITS2)|n1)/d0 (I fail to\n    *   understand why...);\n    * - divl doesn't only calculate quotient, but also leaves\n    *   remainder in %edx which we can definitely use here:-)\n    *\n    *                                   <appro@fy.chalmers.se>\n    */\n#  define bn_div_words(n0,n1,d0)                \\\n\t({  asm volatile (                      \\\n\t\t\"divl   %4\"                     \\\n\t\t: \"=a\"(q), \"=d\"(rem)            \\\n\t\t: \"a\"(n1), \"d\"(n0), \"g\"(d0)     \\\n\t\t: \"cc\");                        \\\n\t    q;                                  \\\n\t})\n#  define REMAINDER_IS_ALREADY_CALCULATED\n#  endif /* __<cpu> */\n# endif /* __GNUC__ */\n#endif /* NO_ASM */\n\nint BN_div(BIGNUM *dv, BIGNUM *rm, const BIGNUM *num, const BIGNUM *divisor,\n\t   BN_CTX *ctx)\n\t{\n\tint norm_shift,i,j,loop;\n\tBIGNUM *tmp,wnum,*snum,*sdiv,*res;\n\tBN_ULONG *resp,*wnump;\n\tBN_ULONG d0,d1;\n\tint num_n,div_n;\n\n\tbn_check_top(num);\n\tbn_check_top(divisor);\n\n\tif (BN_is_zero(divisor))\n\t\t{\n\t\treturn(0);\n\t\t}\n\n\tif (BN_ucmp(num,divisor) < 0)\n\t\t{\n\t\tif (rm != NULL)\n\t\t\t{ if (BN_copy(rm,num) == NULL) return(0); }\n\t\tif (dv != NULL) BN_zero(dv);\n\t\treturn(1);\n\t\t}\n\n\tBN_CTX_start(ctx);\n\ttmp=BN_CTX_get(ctx);\n\ttmp->neg=0;\n\tsnum=BN_CTX_get(ctx);\n\tsdiv=BN_CTX_get(ctx);\n\tif (dv == NULL)\n\t\tres=BN_CTX_get(ctx);\n\telse    res=dv;\n\tif (res == NULL) goto err;\n\n\t/* First we normalise the numbers */\n\tnorm_shift=BN_BITS2-((BN_num_bits(divisor))%BN_BITS2);\n\tBN_lshift(sdiv,divisor,norm_shift);\n\tsdiv->neg=0;\n\tnorm_shift+=BN_BITS2;\n\tBN_lshift(snum,num,norm_shift);\n\tsnum->neg=0;\n\tdiv_n=sdiv->top;\n\tnum_n=snum->top;\n\tloop=num_n-div_n;\n\n\t/* Lets setup a 'window' into snum\n\t * This is the part that corresponds to the current\n\t * 'area' being divided */\n\tBN_init(&wnum);\n\twnum.d=  &(snum->d[loop]);\n\twnum.top= div_n;\n\twnum.dmax= snum->dmax+1; /* a bit of a lie */\n\n\t/* Get the top 2 words of sdiv */\n\t/* i=sdiv->top; */\n\td0=sdiv->d[div_n-1];\n\td1=(div_n == 1)?0:sdiv->d[div_n-2];\n\n\t/* pointer to the 'top' of snum */\n\twnump= &(snum->d[num_n-1]);\n\n\t/* Setup to 'res' */\n\tres->neg= (num->neg^divisor->neg);\n\tif (!bn_wexpand(res,(loop+1))) goto err;\n\tres->top=loop;\n\tresp= &(res->d[loop-1]);\n\n\t/* space for temp */\n\tif (!bn_wexpand(tmp,(div_n+1))) goto err;\n\n\tif (BN_ucmp(&wnum,sdiv) >= 0)\n\t\t{\n\t\tif (!BN_usub(&wnum,&wnum,sdiv)) goto err;\n\t\t*resp=1;\n\t\tres->d[res->top-1]=1;\n\t\t}\n\telse\n\t\tres->top--;\n\tresp--;\n\n\tfor (i=0; i<loop-1; i++)\n\t\t{\n\t\tBN_ULONG q,l0;\n#ifdef BN_DIV3W\n\t\tq=bn_div_3_words(wnump,d1,d0);\n#else\n\t\tBN_ULONG n0,n1,rem=0;\n\n\t\tn0=wnump[0];\n\t\tn1=wnump[-1];\n\t\tif (n0 == d0)\n\t\t\tq=BN_MASK2;\n\t\telse                    /* n0 < d0 */\n\t\t\t{\n#ifdef BN_LLONG\n\t\t\tBN_ULLONG t2;\n\n#if defined(BN_LLONG) && defined(BN_DIV2W) && !defined(bn_div_words)\n\t\t\tq=(BN_ULONG)(((((BN_ULLONG)n0)<<BN_BITS2)|n1)/d0);\n#else\n\t\t\tq=bn_div_words(n0,n1,d0);\n#endif\n\n#ifndef REMAINDER_IS_ALREADY_CALCULATED\n\t\t\t/*\n\t\t\t * rem doesn't have to be BN_ULLONG. The least we\n\t\t\t * know it's less that d0, isn't it?\n\t\t\t */\n\t\t\trem=(n1-q*d0)&BN_MASK2;\n#endif\n\t\t\tt2=(BN_ULLONG)d1*q;\n\n\t\t\tfor (;;)\n\t\t\t\t{\n\t\t\t\tif (t2 <= ((((BN_ULLONG)rem)<<BN_BITS2)|wnump[-2]))\n\t\t\t\t\tbreak;\n\t\t\t\tq--;\n\t\t\t\trem += d0;\n\t\t\t\tif (rem < d0) break; /* don't let rem overflow */\n\t\t\t\tt2 -= d1;\n\t\t\t\t}\n#else /* !BN_LLONG */\n\t\t\tBN_ULONG t2l,t2h,ql,qh;\n\n\t\t\tq=bn_div_words(n0,n1,d0);\n#ifndef REMAINDER_IS_ALREADY_CALCULATED\n\t\t\trem=(n1-q*d0)&BN_MASK2;\n#endif\n\n#ifdef BN_UMULT_HIGH\n\t\t\tt2l = d1 * q;\n\t\t\tt2h = BN_UMULT_HIGH(d1,q);\n#else\n\t\t\tt2l=LBITS(d1); t2h=HBITS(d1);\n\t\t\tql =LBITS(q);  qh =HBITS(q);\n\t\t\tmul64(t2l,t2h,ql,qh); /* t2=(BN_ULLONG)d1*q; */\n#endif\n\n\t\t\tfor (;;)\n\t\t\t\t{\n\t\t\t\tif ((t2h < rem) ||\n\t\t\t\t\t((t2h == rem) && (t2l <= wnump[-2])))\n\t\t\t\t\tbreak;\n\t\t\t\tq--;\n\t\t\t\trem += d0;\n\t\t\t\tif (rem < d0) break; /* don't let rem overflow */\n\t\t\t\tif (t2l < d1) t2h--; t2l -= d1;\n\t\t\t\t}\n#endif /* !BN_LLONG */\n\t\t\t}\n#endif /* !BN_DIV3W */\n\n\t\tl0=bn_mul_words(tmp->d,sdiv->d,div_n,q);\n\t\twnum.d--; wnum.top++;\n\t\ttmp->d[div_n]=l0;\n\t\tfor (j=div_n+1; j>0; j--)\n\t\t\tif (tmp->d[j-1]) break;\n\t\ttmp->top=j;\n\n\t\tj=wnum.top;\n\t\tBN_sub(&wnum,&wnum,tmp);\n\n\t\tsnum->top=snum->top+wnum.top-j;\n\n\t\tif (wnum.neg)\n\t\t\t{\n\t\t\tq--;\n\t\t\tj=wnum.top;\n\t\t\tBN_add(&wnum,&wnum,sdiv);\n\t\t\tsnum->top+=wnum.top-j;\n\t\t\t}\n\t\t*(resp--)=q;\n\t\twnump--;\n\t\t}\n\tif (rm != NULL)\n\t\t{\n\t\tBN_rshift(rm,snum,norm_shift);\n\t\trm->neg=num->neg;\n\t\t}\n\tBN_CTX_end(ctx);\n\treturn(1);\nerr:\n\tBN_CTX_end(ctx);\n\treturn(0);\n\t}\n\n#endif\n\n/* rem != m */\nint BN_mod(BIGNUM *rem, const BIGNUM *m, const BIGNUM *d, BN_CTX *ctx)\n\t{\n#if 0 /* The old slow way */\n\tint i,nm,nd;\n\tBIGNUM *dv;\n\n\tif (BN_ucmp(m,d) < 0)\n\t\treturn((BN_copy(rem,m) == NULL)?0:1);\n\n\tBN_CTX_start(ctx);\n\tdv=BN_CTX_get(ctx);\n\n\tif (!BN_copy(rem,m)) goto err;\n\n\tnm=BN_num_bits(rem);\n\tnd=BN_num_bits(d);\n\tif (!BN_lshift(dv,d,nm-nd)) goto err;\n\tfor (i=nm-nd; i>=0; i--)\n\t\t{\n\t\tif (BN_cmp(rem,dv) >= 0)\n\t\t\t{\n\t\t\tif (!BN_sub(rem,rem,dv)) goto err;\n\t\t\t}\n\t\tif (!BN_rshift1(dv,dv)) goto err;\n\t\t}\n\tBN_CTX_end(ctx);\n\treturn(1);\n err:\n\tBN_CTX_end(ctx);\n\treturn(0);\n#else\n\treturn(BN_div(NULL,rem,m,d,ctx));\n#endif\n\t}\n\n"
  },
  {
    "path": "package/network/services/ead/src/tinysrp/bn_exp.c",
    "content": "/* crypto/bn/bn_exp.c */\n/* Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)\n * All rights reserved.\n *\n * This package is an SSL implementation written\n * by Eric Young (eay@cryptsoft.com).\n * The implementation was written so as to conform with Netscapes SSL.\n *\n * This library is free for commercial and non-commercial use as long as\n * the following conditions are aheared to.  The following conditions\n * apply to all code found in this distribution, be it the RC4, RSA,\n * lhash, DES, etc., code; not just the SSL code.  The SSL documentation\n * included with this distribution is covered by the same copyright terms\n * except that the holder is Tim Hudson (tjh@cryptsoft.com).\n *\n * Copyright remains Eric Young's, and as such any Copyright notices in\n * the code are not to be removed.\n * If this package is used in a product, Eric Young should be given attribution\n * as the author of the parts of the library used.\n * This can be in the form of a textual message at program startup or\n * in documentation (online or textual) provided with the package.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. All advertising materials mentioning features or use of this software\n *    must display the following acknowledgement:\n *    \"This product includes cryptographic software written by\n *     Eric Young (eay@cryptsoft.com)\"\n *    The word 'cryptographic' can be left out if the rouines from the library\n *    being used are not cryptographic related :-).\n * 4. If you include any Windows specific code (or a derivative thereof) from\n *    the apps directory (application code) you must include an acknowledgement:\n *    \"This product includes software written by Tim Hudson (tjh@cryptsoft.com)\"\n *\n * THIS SOFTWARE IS PROVIDED BY ERIC YOUNG ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n *\n * The licence and distribution terms for any publically available version or\n * derivative of this code cannot be changed.  i.e. this code cannot simply be\n * copied and put under another distribution licence\n * [including the GNU Public Licence.]\n */\n/* ====================================================================\n * Copyright (c) 1998-2000 The OpenSSL Project.  All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n *\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in\n *    the documentation and/or other materials provided with the\n *    distribution.\n *\n * 3. All advertising materials mentioning features or use of this\n *    software must display the following acknowledgment:\n *    \"This product includes software developed by the OpenSSL Project\n *    for use in the OpenSSL Toolkit. (http://www.openssl.org/)\"\n *\n * 4. The names \"OpenSSL Toolkit\" and \"OpenSSL Project\" must not be used to\n *    endorse or promote products derived from this software without\n *    prior written permission. For written permission, please contact\n *    openssl-core@openssl.org.\n *\n * 5. Products derived from this software may not be called \"OpenSSL\"\n *    nor may \"OpenSSL\" appear in their names without prior written\n *    permission of the OpenSSL Project.\n *\n * 6. Redistributions of any form whatsoever must retain the following\n *    acknowledgment:\n *    \"This product includes software developed by the OpenSSL Project\n *    for use in the OpenSSL Toolkit (http://www.openssl.org/)\"\n *\n * THIS SOFTWARE IS PROVIDED BY THE OpenSSL PROJECT ``AS IS'' AND ANY\n * EXPRESSED OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\n * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE OpenSSL PROJECT OR\n * ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT\n * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\n * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED\n * OF THE POSSIBILITY OF SUCH DAMAGE.\n * ====================================================================\n *\n * This product includes cryptographic software written by Eric Young\n * (eay@cryptsoft.com).  This product includes software written by Tim\n * Hudson (tjh@cryptsoft.com).\n *\n */\n\n\n#include <stdio.h>\n#include \"bn_lcl.h\"\n\n#define TABLE_SIZE      32\n\n/* slow but works */\nint BN_mod_mul(BIGNUM *ret, BIGNUM *a, BIGNUM *b, const BIGNUM *m, BN_CTX *ctx)\n\t{\n\tBIGNUM *t;\n\tint r=0;\n\n\tbn_check_top(a);\n\tbn_check_top(b);\n\tbn_check_top(m);\n\n\tBN_CTX_start(ctx);\n\tif ((t = BN_CTX_get(ctx)) == NULL) goto err;\n\tif (a == b)\n\t\t{ if (!BN_sqr(t,a,ctx)) goto err; }\n\telse\n\t\t{ if (!BN_mul(t,a,b,ctx)) goto err; }\n\tif (!BN_mod(ret,t,m,ctx)) goto err;\n\tr=1;\nerr:\n\tBN_CTX_end(ctx);\n\treturn(r);\n\t}\n\nint BN_mod_exp(BIGNUM *r, BIGNUM *a, const BIGNUM *p, const BIGNUM *m,\n\t       BN_CTX *ctx)\n\t{\n\tint ret;\n\n\tbn_check_top(a);\n\tbn_check_top(p);\n\tbn_check_top(m);\n\n#ifdef MONT_MUL_MOD\n\t/* I have finally been able to take out this pre-condition of\n\t * the top bit being set.  It was caused by an error in BN_div\n\t * with negatives.  There was also another problem when for a^b%m\n\t * a >= m.  eay 07-May-97 */\n/*      if ((m->d[m->top-1]&BN_TBIT) && BN_is_odd(m)) */\n\n\tif (BN_is_odd(m))\n\t\t{\n\t\tif (a->top == 1)\n\t\t\t{\n\t\t\tBN_ULONG A = a->d[0];\n\t\t\tret=BN_mod_exp_mont_word(r,A,p,m,ctx,NULL);\n\t\t\t}\n\t\telse\n\t\t\tret=BN_mod_exp_mont(r,a,p,m,ctx,NULL);\n\t\t}\n\telse\n#endif\n#ifdef RECP_MUL_MOD\n\t\t{ ret=BN_mod_exp_recp(r,a,p,m,ctx); }\n#else\n\t\t{ ret=BN_mod_exp_simple(r,a,p,m,ctx); }\n#endif\n\n\treturn(ret);\n\t}\n\n\n#ifdef RECP_MUL_MOD\nint BN_mod_exp_recp(BIGNUM *r, const BIGNUM *a, const BIGNUM *p,\n\t\t    const BIGNUM *m, BN_CTX *ctx)\n\t{\n\tint i,j,bits,ret=0,wstart,wend,window,wvalue;\n\tint start=1,ts=0;\n\tBIGNUM *aa;\n\tBIGNUM val[TABLE_SIZE];\n\tBN_RECP_CTX recp;\n\n\tbits=BN_num_bits(p);\n\n\tif (bits == 0)\n\t\t{\n\t\tBN_one(r);\n\t\treturn(1);\n\t\t}\n\n\tBN_CTX_start(ctx);\n\tif ((aa = BN_CTX_get(ctx)) == NULL) goto err;\n\n\tBN_RECP_CTX_init(&recp);\n\tif (BN_RECP_CTX_set(&recp,m,ctx) <= 0) goto err;\n\n\tBN_init(&(val[0]));\n\tts=1;\n\n\tif (!BN_mod(&(val[0]),a,m,ctx)) goto err;               /* 1 */\n\n\twindow = BN_window_bits_for_exponent_size(bits);\n\tif (window > 1)\n\t\t{\n\t\tif (!BN_mod_mul_reciprocal(aa,&(val[0]),&(val[0]),&recp,ctx))\n\t\t\tgoto err;                               /* 2 */\n\t\tj=1<<(window-1);\n\t\tfor (i=1; i<j; i++)\n\t\t\t{\n\t\t\tBN_init(&val[i]);\n\t\t\tif (!BN_mod_mul_reciprocal(&(val[i]),&(val[i-1]),aa,&recp,ctx))\n\t\t\t\tgoto err;\n\t\t\t}\n\t\tts=i;\n\t\t}\n\n\tstart=1;        /* This is used to avoid multiplication etc\n\t\t\t * when there is only the value '1' in the\n\t\t\t * buffer. */\n\twvalue=0;       /* The 'value' of the window */\n\twstart=bits-1;  /* The top bit of the window */\n\twend=0;         /* The bottom bit of the window */\n\n\tif (!BN_one(r)) goto err;\n\n\tfor (;;)\n\t\t{\n\t\tif (BN_is_bit_set(p,wstart) == 0)\n\t\t\t{\n\t\t\tif (!start)\n\t\t\t\tif (!BN_mod_mul_reciprocal(r,r,r,&recp,ctx))\n\t\t\t\tgoto err;\n\t\t\tif (wstart == 0) break;\n\t\t\twstart--;\n\t\t\tcontinue;\n\t\t\t}\n\t\t/* We now have wstart on a 'set' bit, we now need to work out\n\t\t * how bit a window to do.  To do this we need to scan\n\t\t * forward until the last set bit before the end of the\n\t\t * window */\n\t\tj=wstart;\n\t\twvalue=1;\n\t\twend=0;\n\t\tfor (i=1; i<window; i++)\n\t\t\t{\n\t\t\tif (wstart-i < 0) break;\n\t\t\tif (BN_is_bit_set(p,wstart-i))\n\t\t\t\t{\n\t\t\t\twvalue<<=(i-wend);\n\t\t\t\twvalue|=1;\n\t\t\t\twend=i;\n\t\t\t\t}\n\t\t\t}\n\n\t\t/* wend is the size of the current window */\n\t\tj=wend+1;\n\t\t/* add the 'bytes above' */\n\t\tif (!start)\n\t\t\tfor (i=0; i<j; i++)\n\t\t\t\t{\n\t\t\t\tif (!BN_mod_mul_reciprocal(r,r,r,&recp,ctx))\n\t\t\t\t\tgoto err;\n\t\t\t\t}\n\n\t\t/* wvalue will be an odd number < 2^window */\n\t\tif (!BN_mod_mul_reciprocal(r,r,&(val[wvalue>>1]),&recp,ctx))\n\t\t\tgoto err;\n\n\t\t/* move the 'window' down further */\n\t\twstart-=wend+1;\n\t\twvalue=0;\n\t\tstart=0;\n\t\tif (wstart < 0) break;\n\t\t}\n\tret=1;\nerr:\n\tBN_CTX_end(ctx);\n\tfor (i=0; i<ts; i++)\n\t\tBN_clear_free(&(val[i]));\n\tBN_RECP_CTX_free(&recp);\n\treturn(ret);\n\t}\n#else\n\n/* The old fallback, simple version :-) */\nint BN_mod_exp_simple(BIGNUM *r, const BIGNUM *a, const BIGNUM *p,\n\t     const BIGNUM *m, BN_CTX *ctx)\n\t{\n\tint i,j,bits,ret=0,wstart,wend,window,wvalue,ts=0;\n\tint start=1;\n\tBIGNUM *d;\n\tBIGNUM val[TABLE_SIZE];\n\n\tbits=BN_num_bits(p);\n\n\tif (bits == 0)\n\t\t{\n\t\tBN_one(r);\n\t\treturn(1);\n\t\t}\n\n\tBN_CTX_start(ctx);\n\tif ((d = BN_CTX_get(ctx)) == NULL) goto err;\n\n\tBN_init(&(val[0]));\n\tts=1;\n\tif (!BN_mod(&(val[0]),a,m,ctx)) goto err;               /* 1 */\n\n\twindow = BN_window_bits_for_exponent_size(bits);\n\tif (window > 1)\n\t\t{\n\t\tif (!BN_mod_mul(d,&(val[0]),&(val[0]),m,ctx))\n\t\t\tgoto err;                               /* 2 */\n\t\tj=1<<(window-1);\n\t\tfor (i=1; i<j; i++)\n\t\t\t{\n\t\t\tBN_init(&(val[i]));\n\t\t\tif (!BN_mod_mul(&(val[i]),&(val[i-1]),d,m,ctx))\n\t\t\t\tgoto err;\n\t\t\t}\n\t\tts=i;\n\t\t}\n\n\tstart=1;        /* This is used to avoid multiplication etc\n\t\t\t * when there is only the value '1' in the\n\t\t\t * buffer. */\n\twvalue=0;       /* The 'value' of the window */\n\twstart=bits-1;  /* The top bit of the window */\n\twend=0;         /* The bottom bit of the window */\n\n\tif (!BN_one(r)) goto err;\n\n\tfor (;;)\n\t\t{\n\t\tif (BN_is_bit_set(p,wstart) == 0)\n\t\t\t{\n\t\t\tif (!start)\n\t\t\t\tif (!BN_mod_mul(r,r,r,m,ctx))\n\t\t\t\tgoto err;\n\t\t\tif (wstart == 0) break;\n\t\t\twstart--;\n\t\t\tcontinue;\n\t\t\t}\n\t\t/* We now have wstart on a 'set' bit, we now need to work out\n\t\t * how bit a window to do.  To do this we need to scan\n\t\t * forward until the last set bit before the end of the\n\t\t * window */\n\t\tj=wstart;\n\t\twvalue=1;\n\t\twend=0;\n\t\tfor (i=1; i<window; i++)\n\t\t\t{\n\t\t\tif (wstart-i < 0) break;\n\t\t\tif (BN_is_bit_set(p,wstart-i))\n\t\t\t\t{\n\t\t\t\twvalue<<=(i-wend);\n\t\t\t\twvalue|=1;\n\t\t\t\twend=i;\n\t\t\t\t}\n\t\t\t}\n\n\t\t/* wend is the size of the current window */\n\t\tj=wend+1;\n\t\t/* add the 'bytes above' */\n\t\tif (!start)\n\t\t\tfor (i=0; i<j; i++)\n\t\t\t\t{\n\t\t\t\tif (!BN_mod_mul(r,r,r,m,ctx))\n\t\t\t\t\tgoto err;\n\t\t\t\t}\n\n\t\t/* wvalue will be an odd number < 2^window */\n\t\tif (!BN_mod_mul(r,r,&(val[wvalue>>1]),m,ctx))\n\t\t\tgoto err;\n\n\t\t/* move the 'window' down further */\n\t\twstart-=wend+1;\n\t\twvalue=0;\n\t\tstart=0;\n\t\tif (wstart < 0) break;\n\t\t}\n\tret=1;\nerr:\n\tBN_CTX_end(ctx);\n\tfor (i=0; i<ts; i++)\n\t\tBN_clear_free(&(val[i]));\n\treturn(ret);\n\t}\n#endif\n"
  },
  {
    "path": "package/network/services/ead/src/tinysrp/bn_lcl.h",
    "content": "/* crypto/bn/bn_lcl.h */\n/* Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)\n * All rights reserved.\n *\n * This package is an SSL implementation written\n * by Eric Young (eay@cryptsoft.com).\n * The implementation was written so as to conform with Netscapes SSL.\n *\n * This library is free for commercial and non-commercial use as long as\n * the following conditions are aheared to.  The following conditions\n * apply to all code found in this distribution, be it the RC4, RSA,\n * lhash, DES, etc., code; not just the SSL code.  The SSL documentation\n * included with this distribution is covered by the same copyright terms\n * except that the holder is Tim Hudson (tjh@cryptsoft.com).\n *\n * Copyright remains Eric Young's, and as such any Copyright notices in\n * the code are not to be removed.\n * If this package is used in a product, Eric Young should be given attribution\n * as the author of the parts of the library used.\n * This can be in the form of a textual message at program startup or\n * in documentation (online or textual) provided with the package.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. All advertising materials mentioning features or use of this software\n *    must display the following acknowledgement:\n *    \"This product includes cryptographic software written by\n *     Eric Young (eay@cryptsoft.com)\"\n *    The word 'cryptographic' can be left out if the rouines from the library\n *    being used are not cryptographic related :-).\n * 4. If you include any Windows specific code (or a derivative thereof) from\n *    the apps directory (application code) you must include an acknowledgement:\n *    \"This product includes software written by Tim Hudson (tjh@cryptsoft.com)\"\n *\n * THIS SOFTWARE IS PROVIDED BY ERIC YOUNG ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n *\n * The licence and distribution terms for any publically available version or\n * derivative of this code cannot be changed.  i.e. this code cannot simply be\n * copied and put under another distribution licence\n * [including the GNU Public Licence.]\n */\n/* ====================================================================\n * Copyright (c) 1998-2000 The OpenSSL Project.  All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n *\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in\n *    the documentation and/or other materials provided with the\n *    distribution.\n *\n * 3. All advertising materials mentioning features or use of this\n *    software must display the following acknowledgment:\n *    \"This product includes software developed by the OpenSSL Project\n *    for use in the OpenSSL Toolkit. (http://www.openssl.org/)\"\n *\n * 4. The names \"OpenSSL Toolkit\" and \"OpenSSL Project\" must not be used to\n *    endorse or promote products derived from this software without\n *    prior written permission. For written permission, please contact\n *    openssl-core@openssl.org.\n *\n * 5. Products derived from this software may not be called \"OpenSSL\"\n *    nor may \"OpenSSL\" appear in their names without prior written\n *    permission of the OpenSSL Project.\n *\n * 6. Redistributions of any form whatsoever must retain the following\n *    acknowledgment:\n *    \"This product includes software developed by the OpenSSL Project\n *    for use in the OpenSSL Toolkit (http://www.openssl.org/)\"\n *\n * THIS SOFTWARE IS PROVIDED BY THE OpenSSL PROJECT ``AS IS'' AND ANY\n * EXPRESSED OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\n * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE OpenSSL PROJECT OR\n * ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT\n * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\n * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED\n * OF THE POSSIBILITY OF SUCH DAMAGE.\n * ====================================================================\n *\n * This product includes cryptographic software written by Eric Young\n * (eay@cryptsoft.com).  This product includes software written by Tim\n * Hudson (tjh@cryptsoft.com).\n *\n */\n\n#ifndef HEADER_BN_LCL_H\n#define HEADER_BN_LCL_H\n\n#include <bn.h>\n\n#ifdef  __cplusplus\nextern \"C\" {\n#endif\n\n\n/*\n * BN_window_bits_for_exponent_size -- macro for sliding window mod_exp functions\n *\n *\n * For window size 'w' (w >= 2) and a random 'b' bits exponent,\n * the number of multiplications is a constant plus on average\n *\n *    2^(w-1) + (b-w)/(w+1);\n *\n * here  2^(w-1)  is for precomputing the table (we actually need\n * entries only for windows that have the lowest bit set), and\n * (b-w)/(w+1)  is an approximation for the expected number of\n * w-bit windows, not counting the first one.\n *\n * Thus we should use\n *\n *    w >= 6  if        b > 671\n *     w = 5  if  671 > b > 239\n *     w = 4  if  239 > b >  79\n *     w = 3  if   79 > b >  23\n *    w <= 2  if   23 > b\n *\n * (with draws in between).  Very small exponents are often selected\n * with low Hamming weight, so we use  w = 1  for b <= 23.\n */\n#if 1\n#define BN_window_bits_for_exponent_size(b) \\\n\t\t((b) > 671 ? 6 : \\\n\t\t (b) > 239 ? 5 : \\\n\t\t (b) >  79 ? 4 : \\\n\t\t (b) >  23 ? 3 : 1)\n#else\n/* Old SSLeay/OpenSSL table.\n * Maximum window size was 5, so this table differs for b==1024;\n * but it coincides for other interesting values (b==160, b==512).\n */\n#define BN_window_bits_for_exponent_size(b) \\\n\t\t((b) > 255 ? 5 : \\\n\t\t (b) > 127 ? 4 : \\\n\t\t (b) >  17 ? 3 : 1)\n#endif\n\n\n\n/* Pentium pro 16,16,16,32,64 */\n/* Alpha       16,16,16,16.64 */\n#define BN_MULL_SIZE_NORMAL                     (16) /* 32 */\n#define BN_MUL_RECURSIVE_SIZE_NORMAL            (16) /* 32 less than */\n#define BN_SQR_RECURSIVE_SIZE_NORMAL            (16) /* 32 */\n#define BN_MUL_LOW_RECURSIVE_SIZE_NORMAL        (32) /* 32 */\n#define BN_MONT_CTX_SET_SIZE_WORD               (64) /* 32 */\n\n#if !defined(NO_ASM) && !defined(NO_INLINE_ASM) && !defined(PEDANTIC)\n/*\n * BN_UMULT_HIGH section.\n *\n * No, I'm not trying to overwhelm you when stating that the\n * product of N-bit numbers is 2*N bits wide:-) No, I don't expect\n * you to be impressed when I say that if the compiler doesn't\n * support 2*N integer type, then you have to replace every N*N\n * multiplication with 4 (N/2)*(N/2) accompanied by some shifts\n * and additions which unavoidably results in severe performance\n * penalties. Of course provided that the hardware is capable of\n * producing 2*N result... That's when you normally start\n * considering assembler implementation. However! It should be\n * pointed out that some CPUs (most notably Alpha, PowerPC and\n * upcoming IA-64 family:-) provide *separate* instruction\n * calculating the upper half of the product placing the result\n * into a general purpose register. Now *if* the compiler supports\n * inline assembler, then it's not impossible to implement the\n * \"bignum\" routines (and have the compiler optimize 'em)\n * exhibiting \"native\" performance in C. That's what BN_UMULT_HIGH\n * macro is about:-)\n *\n *                                      <appro@fy.chalmers.se>\n */\n# if defined(__alpha) && (defined(SIXTY_FOUR_BIT_LONG) || defined(SIXTY_FOUR_BIT))\n#  if defined(__DECC)\n#   include <c_asm.h>\n#   define BN_UMULT_HIGH(a,b)   (BN_ULONG)asm(\"umulh %a0,%a1,%v0\",(a),(b))\n#  elif defined(__GNUC__)\n#   define BN_UMULT_HIGH(a,b)   ({      \\\n\tregister BN_ULONG ret;          \\\n\tasm (\"umulh     %1,%2,%0\"       \\\n\t     : \"=r\"(ret)                \\\n\t     : \"r\"(a), \"r\"(b));         \\\n\tret;                    })\n#  endif        /* compiler */\n# elif defined(_ARCH_PPC) && defined(__64BIT__) && defined(SIXTY_FOUR_BIT_LONG)\n#  if defined(__GNUC__)\n#   define BN_UMULT_HIGH(a,b)   ({      \\\n\tregister BN_ULONG ret;          \\\n\tasm (\"mulhdu    %0,%1,%2\"       \\\n\t     : \"=r\"(ret)                \\\n\t     : \"r\"(a), \"r\"(b));         \\\n\tret;                    })\n#  endif        /* compiler */\n# endif         /* cpu */\n#endif          /* NO_ASM */\n\n/*************************************************************\n * Using the long long type\n */\n#define Lw(t)    (((BN_ULONG)(t))&BN_MASK2)\n#define Hw(t)    (((BN_ULONG)((t)>>BN_BITS2))&BN_MASK2)\n\n/* This is used for internal error checking and is not normally used */\n#ifdef BN_DEBUG\n# include <assert.h>\n# define bn_check_top(a) assert ((a)->top >= 0 && (a)->top <= (a)->dmax);\n#else\n# define bn_check_top(a)\n#endif\n\n/* This macro is to add extra stuff for development checking */\n#ifdef BN_DEBUG\n#define bn_set_max(r) ((r)->max=(r)->top,BN_set_flags((r),BN_FLG_STATIC_DATA))\n#else\n#define bn_set_max(r)\n#endif\n\n/* These macros are used to 'take' a section of a bignum for read only use */\n#define bn_set_low(r,a,n) \\\n\t{ \\\n\t(r)->top=((a)->top > (n))?(n):(a)->top; \\\n\t(r)->d=(a)->d; \\\n\t(r)->neg=(a)->neg; \\\n\t(r)->flags|=BN_FLG_STATIC_DATA; \\\n\tbn_set_max(r); \\\n\t}\n\n#define bn_set_high(r,a,n) \\\n\t{ \\\n\tif ((a)->top > (n)) \\\n\t\t{ \\\n\t\t(r)->top=(a)->top-n; \\\n\t\t(r)->d= &((a)->d[n]); \\\n\t\t} \\\n\telse \\\n\t\t(r)->top=0; \\\n\t(r)->neg=(a)->neg; \\\n\t(r)->flags|=BN_FLG_STATIC_DATA; \\\n\tbn_set_max(r); \\\n\t}\n\n#ifdef BN_LLONG\n#define mul_add(r,a,w,c) { \\\n\tBN_ULLONG t; \\\n\tt=(BN_ULLONG)w * (a) + (r) + (c); \\\n\t(r)= Lw(t); \\\n\t(c)= Hw(t); \\\n\t}\n\n#define mul(r,a,w,c) { \\\n\tBN_ULLONG t; \\\n\tt=(BN_ULLONG)w * (a) + (c); \\\n\t(r)= Lw(t); \\\n\t(c)= Hw(t); \\\n\t}\n\n#define sqr(r0,r1,a) { \\\n\tBN_ULLONG t; \\\n\tt=(BN_ULLONG)(a)*(a); \\\n\t(r0)=Lw(t); \\\n\t(r1)=Hw(t); \\\n\t}\n\n#elif defined(BN_UMULT_HIGH)\n#define mul_add(r,a,w,c) {              \\\n\tBN_ULONG high,low,ret,tmp=(a);  \\\n\tret =  (r);                     \\\n\thigh=  BN_UMULT_HIGH(w,tmp);    \\\n\tret += (c);                     \\\n\tlow =  (w) * tmp;               \\\n\t(c) =  (ret<(c))?1:0;           \\\n\t(c) += high;                    \\\n\tret += low;                     \\\n\t(c) += (ret<low)?1:0;           \\\n\t(r) =  ret;                     \\\n\t}\n\n#define mul(r,a,w,c)    {               \\\n\tBN_ULONG high,low,ret,ta=(a);   \\\n\tlow =  (w) * ta;                \\\n\thigh=  BN_UMULT_HIGH(w,ta);     \\\n\tret =  low + (c);               \\\n\t(c) =  high;                    \\\n\t(c) += (ret<low)?1:0;           \\\n\t(r) =  ret;                     \\\n\t}\n\n#define sqr(r0,r1,a)    {               \\\n\tBN_ULONG tmp=(a);               \\\n\t(r0) = tmp * tmp;               \\\n\t(r1) = BN_UMULT_HIGH(tmp,tmp);  \\\n\t}\n\n#else\n/*************************************************************\n * No long long type\n */\n\n#define LBITS(a)        ((a)&BN_MASK2l)\n#define HBITS(a)        (((a)>>BN_BITS4)&BN_MASK2l)\n#define L2HBITS(a)      ((BN_ULONG)((a)&BN_MASK2l)<<BN_BITS4)\n\n#define LLBITS(a)       ((a)&BN_MASKl)\n#define LHBITS(a)       (((a)>>BN_BITS2)&BN_MASKl)\n#define LL2HBITS(a)     ((BN_ULLONG)((a)&BN_MASKl)<<BN_BITS2)\n\n#define mul64(l,h,bl,bh) \\\n\t{ \\\n\tBN_ULONG m,m1,lt,ht; \\\n \\\n\tlt=l; \\\n\tht=h; \\\n\tm =(bh)*(lt); \\\n\tlt=(bl)*(lt); \\\n\tm1=(bl)*(ht); \\\n\tht =(bh)*(ht); \\\n\tm=(m+m1)&BN_MASK2; if (m < m1) ht+=L2HBITS(1L); \\\n\tht+=HBITS(m); \\\n\tm1=L2HBITS(m); \\\n\tlt=(lt+m1)&BN_MASK2; if (lt < m1) ht++; \\\n\t(l)=lt; \\\n\t(h)=ht; \\\n\t}\n\n#define sqr64(lo,ho,in) \\\n\t{ \\\n\tBN_ULONG l,h,m; \\\n \\\n\th=(in); \\\n\tl=LBITS(h); \\\n\th=HBITS(h); \\\n\tm =(l)*(h); \\\n\tl*=l; \\\n\th*=h; \\\n\th+=(m&BN_MASK2h1)>>(BN_BITS4-1); \\\n\tm =(m&BN_MASK2l)<<(BN_BITS4+1); \\\n\tl=(l+m)&BN_MASK2; if (l < m) h++; \\\n\t(lo)=l; \\\n\t(ho)=h; \\\n\t}\n\n#define mul_add(r,a,bl,bh,c) { \\\n\tBN_ULONG l,h; \\\n \\\n\th= (a); \\\n\tl=LBITS(h); \\\n\th=HBITS(h); \\\n\tmul64(l,h,(bl),(bh)); \\\n \\\n\t/* non-multiply part */ \\\n\tl=(l+(c))&BN_MASK2; if (l < (c)) h++; \\\n\t(c)=(r); \\\n\tl=(l+(c))&BN_MASK2; if (l < (c)) h++; \\\n\t(c)=h&BN_MASK2; \\\n\t(r)=l; \\\n\t}\n\n#define mul(r,a,bl,bh,c) { \\\n\tBN_ULONG l,h; \\\n \\\n\th= (a); \\\n\tl=LBITS(h); \\\n\th=HBITS(h); \\\n\tmul64(l,h,(bl),(bh)); \\\n \\\n\t/* non-multiply part */ \\\n\tl+=(c); if ((l&BN_MASK2) < (c)) h++; \\\n\t(c)=h&BN_MASK2; \\\n\t(r)=l&BN_MASK2; \\\n\t}\n#endif /* !BN_LLONG */\n\nvoid bn_mul_normal(BN_ULONG *r,BN_ULONG *a,int na,BN_ULONG *b,int nb);\nvoid bn_mul_comba8(BN_ULONG *r,BN_ULONG *a,BN_ULONG *b);\nvoid bn_mul_comba4(BN_ULONG *r,BN_ULONG *a,BN_ULONG *b);\nvoid bn_sqr_normal(BN_ULONG *r, BN_ULONG *a, int n, BN_ULONG *tmp);\nvoid bn_sqr_comba8(BN_ULONG *r,BN_ULONG *a);\nvoid bn_sqr_comba4(BN_ULONG *r,BN_ULONG *a);\nint bn_cmp_words(BN_ULONG *a,BN_ULONG *b,int n);\nvoid bn_mul_recursive(BN_ULONG *r,BN_ULONG *a,BN_ULONG *b,int n2,BN_ULONG *t);\nvoid bn_mul_part_recursive(BN_ULONG *r,BN_ULONG *a,BN_ULONG *b,\n\tint tn, int n,BN_ULONG *t);\nvoid bn_sqr_recursive(BN_ULONG *r,BN_ULONG *a, int n2, BN_ULONG *t);\nvoid bn_mul_low_normal(BN_ULONG *r,BN_ULONG *a,BN_ULONG *b, int n);\nvoid bn_mul_low_recursive(BN_ULONG *r,BN_ULONG *a,BN_ULONG *b,int n2,\n\tBN_ULONG *t);\nvoid bn_mul_high(BN_ULONG *r,BN_ULONG *a,BN_ULONG *b,BN_ULONG *l,int n2,\n\tBN_ULONG *t);\n\n#ifdef  __cplusplus\n}\n#endif\n\n#endif\n"
  },
  {
    "path": "package/network/services/ead/src/tinysrp/bn_lib.c",
    "content": "/* crypto/bn/bn_lib.c */\n/* Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)\n * All rights reserved.\n *\n * This package is an SSL implementation written\n * by Eric Young (eay@cryptsoft.com).\n * The implementation was written so as to conform with Netscapes SSL.\n *\n * This library is free for commercial and non-commercial use as long as\n * the following conditions are aheared to.  The following conditions\n * apply to all code found in this distribution, be it the RC4, RSA,\n * lhash, DES, etc., code; not just the SSL code.  The SSL documentation\n * included with this distribution is covered by the same copyright terms\n * except that the holder is Tim Hudson (tjh@cryptsoft.com).\n *\n * Copyright remains Eric Young's, and as such any Copyright notices in\n * the code are not to be removed.\n * If this package is used in a product, Eric Young should be given attribution\n * as the author of the parts of the library used.\n * This can be in the form of a textual message at program startup or\n * in documentation (online or textual) provided with the package.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. All advertising materials mentioning features or use of this software\n *    must display the following acknowledgement:\n *    \"This product includes cryptographic software written by\n *     Eric Young (eay@cryptsoft.com)\"\n *    The word 'cryptographic' can be left out if the rouines from the library\n *    being used are not cryptographic related :-).\n * 4. If you include any Windows specific code (or a derivative thereof) from\n *    the apps directory (application code) you must include an acknowledgement:\n *    \"This product includes software written by Tim Hudson (tjh@cryptsoft.com)\"\n *\n * THIS SOFTWARE IS PROVIDED BY ERIC YOUNG ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n *\n * The licence and distribution terms for any publically available version or\n * derivative of this code cannot be changed.  i.e. this code cannot simply be\n * copied and put under another distribution licence\n * [including the GNU Public Licence.]\n */\n\n#ifndef BN_DEBUG\n# undef NDEBUG /* avoid conflicting definitions */\n# define NDEBUG\n#endif\n\n#include <assert.h>\n#include <stdio.h>\n#include <stdlib.h>\n#include <string.h>\n#include \"bn_lcl.h\"\n\nconst char *BN_version=\"Big Number\";\n\n/* For a 32 bit machine\n * 2 -   4 ==  128\n * 3 -   8 ==  256\n * 4 -  16 ==  512\n * 5 -  32 == 1024\n * 6 -  64 == 2048\n * 7 - 128 == 4096\n * 8 - 256 == 8192\n */\nstatic int bn_limit_bits=0;\nstatic int bn_limit_num=8;        /* (1<<bn_limit_bits) */\nstatic int bn_limit_bits_low=0;\nstatic int bn_limit_num_low=8;    /* (1<<bn_limit_bits_low) */\nstatic int bn_limit_bits_high=0;\nstatic int bn_limit_num_high=8;   /* (1<<bn_limit_bits_high) */\nstatic int bn_limit_bits_mont=0;\nstatic int bn_limit_num_mont=8;   /* (1<<bn_limit_bits_mont) */\n\nint BN_num_bits_word(BN_ULONG l)\n\t{\n\tstatic const char bits[256]={\n\t\t0,1,2,2,3,3,3,3,4,4,4,4,4,4,4,4,\n\t\t5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,\n\t\t6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,\n\t\t6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,\n\t\t7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,\n\t\t7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,\n\t\t7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,\n\t\t7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,\n\t\t8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,\n\t\t8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,\n\t\t8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,\n\t\t8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,\n\t\t8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,\n\t\t8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,\n\t\t8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,\n\t\t8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,\n\t\t};\n\n#if defined(SIXTY_FOUR_BIT_LONG)\n\tif (l & 0xffffffff00000000L)\n\t\t{\n\t\tif (l & 0xffff000000000000L)\n\t\t\t{\n\t\t\tif (l & 0xff00000000000000L)\n\t\t\t\t{\n\t\t\t\treturn(bits[(int)(l>>56)]+56);\n\t\t\t\t}\n\t\t\telse    return(bits[(int)(l>>48)]+48);\n\t\t\t}\n\t\telse\n\t\t\t{\n\t\t\tif (l & 0x0000ff0000000000L)\n\t\t\t\t{\n\t\t\t\treturn(bits[(int)(l>>40)]+40);\n\t\t\t\t}\n\t\t\telse    return(bits[(int)(l>>32)]+32);\n\t\t\t}\n\t\t}\n\telse\n#else\n#ifdef SIXTY_FOUR_BIT\n\tif (l & 0xffffffff00000000LL)\n\t\t{\n\t\tif (l & 0xffff000000000000LL)\n\t\t\t{\n\t\t\tif (l & 0xff00000000000000LL)\n\t\t\t\t{\n\t\t\t\treturn(bits[(int)(l>>56)]+56);\n\t\t\t\t}\n\t\t\telse    return(bits[(int)(l>>48)]+48);\n\t\t\t}\n\t\telse\n\t\t\t{\n\t\t\tif (l & 0x0000ff0000000000LL)\n\t\t\t\t{\n\t\t\t\treturn(bits[(int)(l>>40)]+40);\n\t\t\t\t}\n\t\t\telse    return(bits[(int)(l>>32)]+32);\n\t\t\t}\n\t\t}\n\telse\n#endif\n#endif\n\t\t{\n#if defined(THIRTY_TWO_BIT) || defined(SIXTY_FOUR_BIT) || defined(SIXTY_FOUR_BIT_LONG)\n\t\tif (l & 0xffff0000L)\n\t\t\t{\n\t\t\tif (l & 0xff000000L)\n\t\t\t\treturn(bits[(int)(l>>24L)]+24);\n\t\t\telse    return(bits[(int)(l>>16L)]+16);\n\t\t\t}\n\t\telse\n#endif\n\t\t\t{\n#if defined(SIXTEEN_BIT) || defined(THIRTY_TWO_BIT) || defined(SIXTY_FOUR_BIT) || defined(SIXTY_FOUR_BIT_LONG)\n\t\t\tif (l & 0xff00L)\n\t\t\t\treturn(bits[(int)(l>>8)]+8);\n\t\t\telse\n#endif\n\t\t\t\treturn(bits[(int)(l   )]  );\n\t\t\t}\n\t\t}\n\t}\n\nint BN_num_bits(const BIGNUM *a)\n\t{\n\tBN_ULONG l;\n\tint i;\n\n\tbn_check_top(a);\n\n\tif (a->top == 0) return(0);\n\tl=a->d[a->top-1];\n\tassert(l != 0);\n\ti=(a->top-1)*BN_BITS2;\n\treturn(i+BN_num_bits_word(l));\n\t}\n\nvoid BN_clear_free(BIGNUM *a)\n\t{\n\tint i;\n\n\tif (a == NULL) return;\n\tif (a->d != NULL)\n\t\t{\n\t\tmemset(a->d,0,a->dmax*sizeof(a->d[0]));\n\t\tif (!(BN_get_flags(a,BN_FLG_STATIC_DATA)))\n\t\t\tfree(a->d);\n\t\t}\n\ti=BN_get_flags(a,BN_FLG_MALLOCED);\n\tmemset(a,0,sizeof(BIGNUM));\n\tif (i)\n\t\tfree(a);\n\t}\n\nvoid BN_free(BIGNUM *a)\n\t{\n\tif (a == NULL) return;\n\tif ((a->d != NULL) && !(BN_get_flags(a,BN_FLG_STATIC_DATA)))\n\t\tfree(a->d);\n\ta->flags|=BN_FLG_FREE; /* REMOVE? */\n\tif (a->flags & BN_FLG_MALLOCED)\n\t\tfree(a);\n\t}\n\nvoid BN_init(BIGNUM *a)\n\t{\n\tmemset(a,0,sizeof(BIGNUM));\n\t}\n\nBIGNUM *BN_new(void)\n\t{\n\tBIGNUM *ret;\n\n\tif ((ret=(BIGNUM *)malloc(sizeof(BIGNUM))) == NULL)\n\t\t{\n\t\treturn(NULL);\n\t\t}\n\tret->flags=BN_FLG_MALLOCED;\n\tret->top=0;\n\tret->neg=0;\n\tret->dmax=0;\n\tret->d=NULL;\n\treturn(ret);\n\t}\n\n/* This is an internal function that should not be used in applications.\n * It ensures that 'b' has enough room for a 'words' word number number.\n * It is mostly used by the various BIGNUM routines. If there is an error,\n * NULL is returned. If not, 'b' is returned. */\n\nBIGNUM *bn_expand2(BIGNUM *b, int words)\n\t{\n\tBN_ULONG *A,*a;\n\tconst BN_ULONG *B;\n\tint i;\n\n\tbn_check_top(b);\n\n\tif (words > b->dmax)\n\t\t{\n\t\tbn_check_top(b);\n\t\tif (BN_get_flags(b,BN_FLG_STATIC_DATA))\n\t\t\t{\n\t\t\treturn(NULL);\n\t\t\t}\n\t\ta=A=(BN_ULONG *)malloc(sizeof(BN_ULONG)*(words+1));\n\t\tif (A == NULL)\n\t\t\t{\n\t\t\treturn(NULL);\n\t\t\t}\n#if 1\n\t\tB=b->d;\n\t\t/* Check if the previous number needs to be copied */\n\t\tif (B != NULL)\n\t\t\t{\n#if 0\n\t\t\t/* This lot is an unrolled loop to copy b->top\n\t\t\t * BN_ULONGs from B to A\n\t\t\t */\n/*\n * I have nothing against unrolling but it's usually done for\n * several reasons, namely:\n * - minimize percentage of decision making code, i.e. branches;\n * - avoid cache trashing;\n * - make it possible to schedule loads earlier;\n * Now let's examine the code below. The cornerstone of C is\n * \"programmer is always right\" and that's what we love it for:-)\n * For this very reason C compilers have to be paranoid when it\n * comes to data aliasing and assume the worst. Yeah, but what\n * does it mean in real life? This means that loop body below will\n * be compiled to sequence of loads immediately followed by stores\n * as compiler assumes the worst, something in A==B+1 style. As a\n * result CPU pipeline is going to starve for incoming data. Secondly\n * if A and B happen to share same cache line such code is going to\n * cause severe cache trashing. Both factors have severe impact on\n * performance of modern CPUs and this is the reason why this\n * particular piece of code is #ifdefed away and replaced by more\n * \"friendly\" version found in #else section below. This comment\n * also applies to BN_copy function.\n *\n *                                      <appro@fy.chalmers.se>\n */\n\t\t\tfor (i=b->top&(~7); i>0; i-=8)\n\t\t\t\t{\n\t\t\t\tA[0]=B[0]; A[1]=B[1]; A[2]=B[2]; A[3]=B[3];\n\t\t\t\tA[4]=B[4]; A[5]=B[5]; A[6]=B[6]; A[7]=B[7];\n\t\t\t\tA+=8;\n\t\t\t\tB+=8;\n\t\t\t\t}\n\t\t\tswitch (b->top&7)\n\t\t\t\t{\n\t\t\tcase 7:\n\t\t\t\tA[6]=B[6];\n\t\t\tcase 6:\n\t\t\t\tA[5]=B[5];\n\t\t\tcase 5:\n\t\t\t\tA[4]=B[4];\n\t\t\tcase 4:\n\t\t\t\tA[3]=B[3];\n\t\t\tcase 3:\n\t\t\t\tA[2]=B[2];\n\t\t\tcase 2:\n\t\t\t\tA[1]=B[1];\n\t\t\tcase 1:\n\t\t\t\tA[0]=B[0];\n\t\t\tcase 0:\n\t\t\t\t/* I need the 'case 0' entry for utrix cc.\n\t\t\t\t * If the optimizer is turned on, it does the\n\t\t\t\t * switch table by doing\n\t\t\t\t * a=top&7\n\t\t\t\t * a--;\n\t\t\t\t * goto jump_table[a];\n\t\t\t\t * If top is 0, this makes us jump to 0xffffffc\n\t\t\t\t * which is rather bad :-(.\n\t\t\t\t * eric 23-Apr-1998\n\t\t\t\t */\n\t\t\t\t;\n\t\t\t\t}\n#else\n\t\t\tfor (i=b->top>>2; i>0; i--,A+=4,B+=4)\n\t\t\t\t{\n\t\t\t\t/*\n\t\t\t\t * The fact that the loop is unrolled\n\t\t\t\t * 4-wise is a tribute to Intel. It's\n\t\t\t\t * the one that doesn't have enough\n\t\t\t\t * registers to accomodate more data.\n\t\t\t\t * I'd unroll it 8-wise otherwise:-)\n\t\t\t\t *\n\t\t\t\t *              <appro@fy.chalmers.se>\n\t\t\t\t */\n\t\t\t\tBN_ULONG a0,a1,a2,a3;\n\t\t\t\ta0=B[0]; a1=B[1]; a2=B[2]; a3=B[3];\n\t\t\t\tA[0]=a0; A[1]=a1; A[2]=a2; A[3]=a3;\n\t\t\t\t}\n\t\t\tswitch (b->top&3)\n\t\t\t\t{\n\t\t\t\tcase 3: A[2]=B[2];\n\t\t\t\tcase 2: A[1]=B[1];\n\t\t\t\tcase 1: A[0]=B[0];\n\t\t\t\tcase 0: ; /* ultrix cc workaround, see above */\n\t\t\t\t}\n#endif\n\t\t\tfree(b->d);\n\t\t\t}\n\n\t\tb->d=a;\n\t\tb->dmax=words;\n\n\t\t/* Now need to zero any data between b->top and b->max */\n\n\t\tA= &(b->d[b->top]);\n\t\tfor (i=(b->dmax - b->top)>>3; i>0; i--,A+=8)\n\t\t\t{\n\t\t\tA[0]=0; A[1]=0; A[2]=0; A[3]=0;\n\t\t\tA[4]=0; A[5]=0; A[6]=0; A[7]=0;\n\t\t\t}\n\t\tfor (i=(b->dmax - b->top)&7; i>0; i--,A++)\n\t\t\tA[0]=0;\n#else\n\t\t\tmemset(A,0,sizeof(BN_ULONG)*(words+1));\n\t\t\tmemcpy(A,b->d,sizeof(b->d[0])*b->top);\n\t\t\tb->d=a;\n\t\t\tb->max=words;\n#endif\n\n/*              memset(&(p[b->max]),0,((words+1)-b->max)*sizeof(BN_ULONG)); */\n/*      { int i; for (i=b->max; i<words+1; i++) p[i]=i;} */\n\n\t\t}\n\treturn(b);\n\t}\n\nBIGNUM *BN_copy(BIGNUM *a, const BIGNUM *b)\n\t{\n\tint i;\n\tBN_ULONG *A;\n\tconst BN_ULONG *B;\n\n\tbn_check_top(b);\n\n\tif (a == b) return(a);\n\tif (bn_wexpand(a,b->top) == NULL) return(NULL);\n\n#if 1\n\tA=a->d;\n\tB=b->d;\n\tfor (i=b->top>>2; i>0; i--,A+=4,B+=4)\n\t\t{\n\t\tBN_ULONG a0,a1,a2,a3;\n\t\ta0=B[0]; a1=B[1]; a2=B[2]; a3=B[3];\n\t\tA[0]=a0; A[1]=a1; A[2]=a2; A[3]=a3;\n\t\t}\n\tswitch (b->top&3)\n\t\t{\n\t\tcase 3: A[2]=B[2];\n\t\tcase 2: A[1]=B[1];\n\t\tcase 1: A[0]=B[0];\n\t\tcase 0: ; /* ultrix cc workaround, see comments in bn_expand2 */\n\t\t}\n#else\n\tmemcpy(a->d,b->d,sizeof(b->d[0])*b->top);\n#endif\n\n/*      memset(&(a->d[b->top]),0,sizeof(a->d[0])*(a->max-b->top));*/\n\ta->top=b->top;\n\tif ((a->top == 0) && (a->d != NULL))\n\t\ta->d[0]=0;\n\ta->neg=b->neg;\n\treturn(a);\n\t}\n\nint BN_set_word(BIGNUM *a, BN_ULONG w)\n\t{\n\tint i,n;\n\tif (bn_expand(a,sizeof(BN_ULONG)*8) == NULL) return(0);\n\n\tn=sizeof(BN_ULONG)/BN_BYTES;\n\ta->neg=0;\n\ta->top=0;\n\ta->d[0]=(BN_ULONG)w&BN_MASK2;\n\tif (a->d[0] != 0) a->top=1;\n\tfor (i=1; i<n; i++)\n\t\t{\n\t\t/* the following is done instead of\n\t\t * w>>=BN_BITS2 so compilers don't complain\n\t\t * on builds where sizeof(long) == BN_TYPES */\n#ifndef SIXTY_FOUR_BIT /* the data item > unsigned long */\n\t\tw>>=BN_BITS4;\n\t\tw>>=BN_BITS4;\n#else\n\t\tw=0;\n#endif\n\t\ta->d[i]=(BN_ULONG)w&BN_MASK2;\n\t\tif (a->d[i] != 0) a->top=i+1;\n\t\t}\n\treturn(1);\n\t}\n\n/* ignore negative */\nBIGNUM *BN_bin2bn(const unsigned char *s, int len, BIGNUM *ret)\n\t{\n\tunsigned int i,m;\n\tunsigned int n;\n\tBN_ULONG l;\n\n\tif (ret == NULL) ret=BN_new();\n\tif (ret == NULL) return(NULL);\n\tl=0;\n\tn=len;\n\tif (n == 0)\n\t\t{\n\t\tret->top=0;\n\t\treturn(ret);\n\t\t}\n\tif (bn_expand(ret,(int)(n+2)*8) == NULL)\n\t\treturn(NULL);\n\ti=((n-1)/BN_BYTES)+1;\n\tm=((n-1)%(BN_BYTES));\n\tret->top=i;\n\twhile (n-- > 0)\n\t\t{\n\t\tl=(l<<8L)| *(s++);\n\t\tif (m-- == 0)\n\t\t\t{\n\t\t\tret->d[--i]=l;\n\t\t\tl=0;\n\t\t\tm=BN_BYTES-1;\n\t\t\t}\n\t\t}\n\t/* need to call this due to clear byte at top if avoiding\n\t * having the top bit set (-ve number) */\n\tbn_fix_top(ret);\n\treturn(ret);\n\t}\n\n/* ignore negative */\nint BN_bn2bin(const BIGNUM *a, unsigned char *to)\n\t{\n\tint n,i;\n\tBN_ULONG l;\n\n\tn=i=BN_num_bytes(a);\n\twhile (i-- > 0)\n\t\t{\n\t\tl=a->d[i/BN_BYTES];\n\t\t*(to++)=(unsigned char)(l>>(8*(i%BN_BYTES)))&0xff;\n\t\t}\n\treturn(n);\n\t}\n\nint BN_ucmp(const BIGNUM *a, const BIGNUM *b)\n\t{\n\tint i;\n\tBN_ULONG t1,t2,*ap,*bp;\n\n\tbn_check_top(a);\n\tbn_check_top(b);\n\n\ti=a->top-b->top;\n\tif (i != 0) return(i);\n\tap=a->d;\n\tbp=b->d;\n\tfor (i=a->top-1; i>=0; i--)\n\t\t{\n\t\tt1= ap[i];\n\t\tt2= bp[i];\n\t\tif (t1 != t2)\n\t\t\treturn(t1 > t2?1:-1);\n\t\t}\n\treturn(0);\n\t}\n\nint BN_cmp(const BIGNUM *a, const BIGNUM *b)\n\t{\n\tint i;\n\tint gt,lt;\n\tBN_ULONG t1,t2;\n\n\tif ((a == NULL) || (b == NULL))\n\t\t{\n\t\tif (a != NULL)\n\t\t\treturn(-1);\n\t\telse if (b != NULL)\n\t\t\treturn(1);\n\t\telse\n\t\t\treturn(0);\n\t\t}\n\n\tbn_check_top(a);\n\tbn_check_top(b);\n\n\tif (a->neg != b->neg)\n\t\t{\n\t\tif (a->neg)\n\t\t\treturn(-1);\n\t\telse    return(1);\n\t\t}\n\tif (a->neg == 0)\n\t\t{ gt=1; lt= -1; }\n\telse    { gt= -1; lt=1; }\n\n\tif (a->top > b->top) return(gt);\n\tif (a->top < b->top) return(lt);\n\tfor (i=a->top-1; i>=0; i--)\n\t\t{\n\t\tt1=a->d[i];\n\t\tt2=b->d[i];\n\t\tif (t1 > t2) return(gt);\n\t\tif (t1 < t2) return(lt);\n\t\t}\n\treturn(0);\n\t}\n\nint BN_is_bit_set(const BIGNUM *a, int n)\n\t{\n\tint i,j;\n\n\tif (n < 0) return(0);\n\ti=n/BN_BITS2;\n\tj=n%BN_BITS2;\n\tif (a->top <= i) return(0);\n\treturn((a->d[i]&(((BN_ULONG)1)<<j))?1:0);\n\t}\n"
  },
  {
    "path": "package/network/services/ead/src/tinysrp/bn_mul.c",
    "content": "/* crypto/bn/bn_mul.c */\n/* Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)\n * All rights reserved.\n *\n * This package is an SSL implementation written\n * by Eric Young (eay@cryptsoft.com).\n * The implementation was written so as to conform with Netscapes SSL.\n *\n * This library is free for commercial and non-commercial use as long as\n * the following conditions are aheared to.  The following conditions\n * apply to all code found in this distribution, be it the RC4, RSA,\n * lhash, DES, etc., code; not just the SSL code.  The SSL documentation\n * included with this distribution is covered by the same copyright terms\n * except that the holder is Tim Hudson (tjh@cryptsoft.com).\n *\n * Copyright remains Eric Young's, and as such any Copyright notices in\n * the code are not to be removed.\n * If this package is used in a product, Eric Young should be given attribution\n * as the author of the parts of the library used.\n * This can be in the form of a textual message at program startup or\n * in documentation (online or textual) provided with the package.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. All advertising materials mentioning features or use of this software\n *    must display the following acknowledgement:\n *    \"This product includes cryptographic software written by\n *     Eric Young (eay@cryptsoft.com)\"\n *    The word 'cryptographic' can be left out if the rouines from the library\n *    being used are not cryptographic related :-).\n * 4. If you include any Windows specific code (or a derivative thereof) from\n *    the apps directory (application code) you must include an acknowledgement:\n *    \"This product includes software written by Tim Hudson (tjh@cryptsoft.com)\"\n *\n * THIS SOFTWARE IS PROVIDED BY ERIC YOUNG ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n *\n * The licence and distribution terms for any publically available version or\n * derivative of this code cannot be changed.  i.e. this code cannot simply be\n * copied and put under another distribution licence\n * [including the GNU Public Licence.]\n */\n\n#include <stdio.h>\n#include <string.h>\n#include \"bn_lcl.h\"\n\nint BN_mul(BIGNUM *r, BIGNUM *a, BIGNUM *b, BN_CTX *ctx)\n\t{\n\tint top,al,bl;\n\tBIGNUM *rr;\n\tint ret = 0;\n#if defined(BN_MUL_COMBA) || defined(BN_RECURSION)\n\tint i;\n#endif\n\n#ifdef BN_COUNT\n\tprintf(\"BN_mul %d * %d\\n\",a->top,b->top);\n#endif\n\n\tbn_check_top(a);\n\tbn_check_top(b);\n\tbn_check_top(r);\n\n\tal=a->top;\n\tbl=b->top;\n\n\tif ((al == 0) || (bl == 0))\n\t\t{\n\t\tBN_zero(r);\n\t\treturn(1);\n\t\t}\n\ttop=al+bl;\n\n\tBN_CTX_start(ctx);\n\tif ((r == a) || (r == b))\n\t\t{\n\t\tif ((rr = BN_CTX_get(ctx)) == NULL) goto err;\n\t\t}\n\telse\n\t\trr = r;\n\trr->neg=a->neg^b->neg;\n\n#if defined(BN_MUL_COMBA) || defined(BN_RECURSION)\n\ti = al-bl;\n#endif\n#ifdef BN_MUL_COMBA\n\tif (i == 0)\n\t\t{\n# if 0\n\t\tif (al == 4)\n\t\t\t{\n\t\t\tif (bn_wexpand(rr,8) == NULL) goto err;\n\t\t\trr->top=8;\n\t\t\tbn_mul_comba4(rr->d,a->d,b->d);\n\t\t\tgoto end;\n\t\t\t}\n# endif\n\t\tif (al == 8)\n\t\t\t{\n\t\t\tif (bn_wexpand(rr,16) == NULL) goto err;\n\t\t\trr->top=16;\n\t\t\tbn_mul_comba8(rr->d,a->d,b->d);\n\t\t\tgoto end;\n\t\t\t}\n\t\t}\n#endif /* BN_MUL_COMBA */\n\tif (bn_wexpand(rr,top) == NULL) goto err;\n\trr->top=top;\n\tbn_mul_normal(rr->d,a->d,al,b->d,bl);\n\n#if defined(BN_MUL_COMBA) || defined(BN_RECURSION)\nend:\n#endif\n\tbn_fix_top(rr);\n\tif (r != rr) BN_copy(r,rr);\n\tret=1;\nerr:\n\tBN_CTX_end(ctx);\n\treturn(ret);\n\t}\n\nvoid bn_mul_normal(BN_ULONG *r, BN_ULONG *a, int na, BN_ULONG *b, int nb)\n\t{\n\tBN_ULONG *rr;\n\n#ifdef BN_COUNT\n\tprintf(\" bn_mul_normal %d * %d\\n\",na,nb);\n#endif\n\n\tif (na < nb)\n\t\t{\n\t\tint itmp;\n\t\tBN_ULONG *ltmp;\n\n\t\titmp=na; na=nb; nb=itmp;\n\t\tltmp=a;   a=b;   b=ltmp;\n\n\t\t}\n\trr= &(r[na]);\n\trr[0]=bn_mul_words(r,a,na,b[0]);\n\n\tfor (;;)\n\t\t{\n\t\tif (--nb <= 0) return;\n\t\trr[1]=bn_mul_add_words(&(r[1]),a,na,b[1]);\n\t\tif (--nb <= 0) return;\n\t\trr[2]=bn_mul_add_words(&(r[2]),a,na,b[2]);\n\t\tif (--nb <= 0) return;\n\t\trr[3]=bn_mul_add_words(&(r[3]),a,na,b[3]);\n\t\tif (--nb <= 0) return;\n\t\trr[4]=bn_mul_add_words(&(r[4]),a,na,b[4]);\n\t\trr+=4;\n\t\tr+=4;\n\t\tb+=4;\n\t\t}\n\t}\n"
  },
  {
    "path": "package/network/services/ead/src/tinysrp/bn_prime.h",
    "content": "/* Auto generated by bn_prime.pl */\n/* Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)\n * All rights reserved.\n *\n * This package is an SSL implementation written\n * by Eric Young (eay@cryptsoft.com).\n * The implementation was written so as to conform with Netscapes SSL.\n * \n * This library is free for commercial and non-commercial use as long as\n * the following conditions are aheared to.  The following conditions\n * apply to all code found in this distribution, be it the RC4, RSA,\n * lhash, DES, etc., code; not just the SSL code.  The SSL documentation\n * included with this distribution is covered by the same copyright terms\n * except that the holder is Tim Hudson (tjh@cryptsoft.com).\n * \n * Copyright remains Eric Young's, and as such any Copyright notices in\n * the code are not to be removed.\n * If this package is used in a product, Eric Young should be given attribution\n * as the author of the parts of the library used.\n * This can be in the form of a textual message at program startup or\n * in documentation (online or textual) provided with the package.\n * \n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. All advertising materials mentioning features or use of this software\n *    must display the following acknowledgement:\n *    \"This product includes cryptographic software written by\n *     Eric Young (eay@cryptsoft.com)\"\n *    The word 'cryptographic' can be left out if the rouines from the library\n *    being used are not cryptographic related :-).\n * 4. If you include any Windows specific code (or a derivative thereof) from \n *    the apps directory (application code) you must include an acknowledgement:\n *    \"This product includes software written by Tim Hudson (tjh@cryptsoft.com)\"\n * \n * THIS SOFTWARE IS PROVIDED BY ERIC YOUNG ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n * \n * The licence and distribution terms for any publically available version or\n * derivative of this code cannot be changed.  i.e. this code cannot simply be\n * copied and put under another distribution licence\n * [including the GNU Public Licence.]\n */\n\n#ifndef EIGHT_BIT\n#define NUMPRIMES 2048\n#else\n#define NUMPRIMES 54\n#endif\nstatic const unsigned int primes[NUMPRIMES]=\n\t{\n\t   2,   3,   5,   7,  11,  13,  17,  19,\n\t  23,  29,  31,  37,  41,  43,  47,  53,\n\t  59,  61,  67,  71,  73,  79,  83,  89,\n\t  97, 101, 103, 107, 109, 113, 127, 131,\n\t 137, 139, 149, 151, 157, 163, 167, 173,\n\t 179, 181, 191, 193, 197, 199, 211, 223,\n\t 227, 229, 233, 239, 241, 251,\n#ifndef EIGHT_BIT\n\t 257, 263,\n\t 269, 271, 277, 281, 283, 293, 307, 311,\n\t 313, 317, 331, 337, 347, 349, 353, 359,\n\t 367, 373, 379, 383, 389, 397, 401, 409,\n\t 419, 421, 431, 433, 439, 443, 449, 457,\n\t 461, 463, 467, 479, 487, 491, 499, 503,\n\t 509, 521, 523, 541, 547, 557, 563, 569,\n\t 571, 577, 587, 593, 599, 601, 607, 613,\n\t 617, 619, 631, 641, 643, 647, 653, 659,\n\t 661, 673, 677, 683, 691, 701, 709, 719,\n\t 727, 733, 739, 743, 751, 757, 761, 769,\n\t 773, 787, 797, 809, 811, 821, 823, 827,\n\t 829, 839, 853, 857, 859, 863, 877, 881,\n\t 883, 887, 907, 911, 919, 929, 937, 941,\n\t 947, 953, 967, 971, 977, 983, 991, 997,\n\t1009,1013,1019,1021,1031,1033,1039,1049,\n\t1051,1061,1063,1069,1087,1091,1093,1097,\n\t1103,1109,1117,1123,1129,1151,1153,1163,\n\t1171,1181,1187,1193,1201,1213,1217,1223,\n\t1229,1231,1237,1249,1259,1277,1279,1283,\n\t1289,1291,1297,1301,1303,1307,1319,1321,\n\t1327,1361,1367,1373,1381,1399,1409,1423,\n\t1427,1429,1433,1439,1447,1451,1453,1459,\n\t1471,1481,1483,1487,1489,1493,1499,1511,\n\t1523,1531,1543,1549,1553,1559,1567,1571,\n\t1579,1583,1597,1601,1607,1609,1613,1619,\n\t1621,1627,1637,1657,1663,1667,1669,1693,\n\t1697,1699,1709,1721,1723,1733,1741,1747,\n\t1753,1759,1777,1783,1787,1789,1801,1811,\n\t1823,1831,1847,1861,1867,1871,1873,1877,\n\t1879,1889,1901,1907,1913,1931,1933,1949,\n\t1951,1973,1979,1987,1993,1997,1999,2003,\n\t2011,2017,2027,2029,2039,2053,2063,2069,\n\t2081,2083,2087,2089,2099,2111,2113,2129,\n\t2131,2137,2141,2143,2153,2161,2179,2203,\n\t2207,2213,2221,2237,2239,2243,2251,2267,\n\t2269,2273,2281,2287,2293,2297,2309,2311,\n\t2333,2339,2341,2347,2351,2357,2371,2377,\n\t2381,2383,2389,2393,2399,2411,2417,2423,\n\t2437,2441,2447,2459,2467,2473,2477,2503,\n\t2521,2531,2539,2543,2549,2551,2557,2579,\n\t2591,2593,2609,2617,2621,2633,2647,2657,\n\t2659,2663,2671,2677,2683,2687,2689,2693,\n\t2699,2707,2711,2713,2719,2729,2731,2741,\n\t2749,2753,2767,2777,2789,2791,2797,2801,\n\t2803,2819,2833,2837,2843,2851,2857,2861,\n\t2879,2887,2897,2903,2909,2917,2927,2939,\n\t2953,2957,2963,2969,2971,2999,3001,3011,\n\t3019,3023,3037,3041,3049,3061,3067,3079,\n\t3083,3089,3109,3119,3121,3137,3163,3167,\n\t3169,3181,3187,3191,3203,3209,3217,3221,\n\t3229,3251,3253,3257,3259,3271,3299,3301,\n\t3307,3313,3319,3323,3329,3331,3343,3347,\n\t3359,3361,3371,3373,3389,3391,3407,3413,\n\t3433,3449,3457,3461,3463,3467,3469,3491,\n\t3499,3511,3517,3527,3529,3533,3539,3541,\n\t3547,3557,3559,3571,3581,3583,3593,3607,\n\t3613,3617,3623,3631,3637,3643,3659,3671,\n\t3673,3677,3691,3697,3701,3709,3719,3727,\n\t3733,3739,3761,3767,3769,3779,3793,3797,\n\t3803,3821,3823,3833,3847,3851,3853,3863,\n\t3877,3881,3889,3907,3911,3917,3919,3923,\n\t3929,3931,3943,3947,3967,3989,4001,4003,\n\t4007,4013,4019,4021,4027,4049,4051,4057,\n\t4073,4079,4091,4093,4099,4111,4127,4129,\n\t4133,4139,4153,4157,4159,4177,4201,4211,\n\t4217,4219,4229,4231,4241,4243,4253,4259,\n\t4261,4271,4273,4283,4289,4297,4327,4337,\n\t4339,4349,4357,4363,4373,4391,4397,4409,\n\t4421,4423,4441,4447,4451,4457,4463,4481,\n\t4483,4493,4507,4513,4517,4519,4523,4547,\n\t4549,4561,4567,4583,4591,4597,4603,4621,\n\t4637,4639,4643,4649,4651,4657,4663,4673,\n\t4679,4691,4703,4721,4723,4729,4733,4751,\n\t4759,4783,4787,4789,4793,4799,4801,4813,\n\t4817,4831,4861,4871,4877,4889,4903,4909,\n\t4919,4931,4933,4937,4943,4951,4957,4967,\n\t4969,4973,4987,4993,4999,5003,5009,5011,\n\t5021,5023,5039,5051,5059,5077,5081,5087,\n\t5099,5101,5107,5113,5119,5147,5153,5167,\n\t5171,5179,5189,5197,5209,5227,5231,5233,\n\t5237,5261,5273,5279,5281,5297,5303,5309,\n\t5323,5333,5347,5351,5381,5387,5393,5399,\n\t5407,5413,5417,5419,5431,5437,5441,5443,\n\t5449,5471,5477,5479,5483,5501,5503,5507,\n\t5519,5521,5527,5531,5557,5563,5569,5573,\n\t5581,5591,5623,5639,5641,5647,5651,5653,\n\t5657,5659,5669,5683,5689,5693,5701,5711,\n\t5717,5737,5741,5743,5749,5779,5783,5791,\n\t5801,5807,5813,5821,5827,5839,5843,5849,\n\t5851,5857,5861,5867,5869,5879,5881,5897,\n\t5903,5923,5927,5939,5953,5981,5987,6007,\n\t6011,6029,6037,6043,6047,6053,6067,6073,\n\t6079,6089,6091,6101,6113,6121,6131,6133,\n\t6143,6151,6163,6173,6197,6199,6203,6211,\n\t6217,6221,6229,6247,6257,6263,6269,6271,\n\t6277,6287,6299,6301,6311,6317,6323,6329,\n\t6337,6343,6353,6359,6361,6367,6373,6379,\n\t6389,6397,6421,6427,6449,6451,6469,6473,\n\t6481,6491,6521,6529,6547,6551,6553,6563,\n\t6569,6571,6577,6581,6599,6607,6619,6637,\n\t6653,6659,6661,6673,6679,6689,6691,6701,\n\t6703,6709,6719,6733,6737,6761,6763,6779,\n\t6781,6791,6793,6803,6823,6827,6829,6833,\n\t6841,6857,6863,6869,6871,6883,6899,6907,\n\t6911,6917,6947,6949,6959,6961,6967,6971,\n\t6977,6983,6991,6997,7001,7013,7019,7027,\n\t7039,7043,7057,7069,7079,7103,7109,7121,\n\t7127,7129,7151,7159,7177,7187,7193,7207,\n\t7211,7213,7219,7229,7237,7243,7247,7253,\n\t7283,7297,7307,7309,7321,7331,7333,7349,\n\t7351,7369,7393,7411,7417,7433,7451,7457,\n\t7459,7477,7481,7487,7489,7499,7507,7517,\n\t7523,7529,7537,7541,7547,7549,7559,7561,\n\t7573,7577,7583,7589,7591,7603,7607,7621,\n\t7639,7643,7649,7669,7673,7681,7687,7691,\n\t7699,7703,7717,7723,7727,7741,7753,7757,\n\t7759,7789,7793,7817,7823,7829,7841,7853,\n\t7867,7873,7877,7879,7883,7901,7907,7919,\n\t7927,7933,7937,7949,7951,7963,7993,8009,\n\t8011,8017,8039,8053,8059,8069,8081,8087,\n\t8089,8093,8101,8111,8117,8123,8147,8161,\n\t8167,8171,8179,8191,8209,8219,8221,8231,\n\t8233,8237,8243,8263,8269,8273,8287,8291,\n\t8293,8297,8311,8317,8329,8353,8363,8369,\n\t8377,8387,8389,8419,8423,8429,8431,8443,\n\t8447,8461,8467,8501,8513,8521,8527,8537,\n\t8539,8543,8563,8573,8581,8597,8599,8609,\n\t8623,8627,8629,8641,8647,8663,8669,8677,\n\t8681,8689,8693,8699,8707,8713,8719,8731,\n\t8737,8741,8747,8753,8761,8779,8783,8803,\n\t8807,8819,8821,8831,8837,8839,8849,8861,\n\t8863,8867,8887,8893,8923,8929,8933,8941,\n\t8951,8963,8969,8971,8999,9001,9007,9011,\n\t9013,9029,9041,9043,9049,9059,9067,9091,\n\t9103,9109,9127,9133,9137,9151,9157,9161,\n\t9173,9181,9187,9199,9203,9209,9221,9227,\n\t9239,9241,9257,9277,9281,9283,9293,9311,\n\t9319,9323,9337,9341,9343,9349,9371,9377,\n\t9391,9397,9403,9413,9419,9421,9431,9433,\n\t9437,9439,9461,9463,9467,9473,9479,9491,\n\t9497,9511,9521,9533,9539,9547,9551,9587,\n\t9601,9613,9619,9623,9629,9631,9643,9649,\n\t9661,9677,9679,9689,9697,9719,9721,9733,\n\t9739,9743,9749,9767,9769,9781,9787,9791,\n\t9803,9811,9817,9829,9833,9839,9851,9857,\n\t9859,9871,9883,9887,9901,9907,9923,9929,\n\t9931,9941,9949,9967,9973,10007,10009,10037,\n\t10039,10061,10067,10069,10079,10091,10093,10099,\n\t10103,10111,10133,10139,10141,10151,10159,10163,\n\t10169,10177,10181,10193,10211,10223,10243,10247,\n\t10253,10259,10267,10271,10273,10289,10301,10303,\n\t10313,10321,10331,10333,10337,10343,10357,10369,\n\t10391,10399,10427,10429,10433,10453,10457,10459,\n\t10463,10477,10487,10499,10501,10513,10529,10531,\n\t10559,10567,10589,10597,10601,10607,10613,10627,\n\t10631,10639,10651,10657,10663,10667,10687,10691,\n\t10709,10711,10723,10729,10733,10739,10753,10771,\n\t10781,10789,10799,10831,10837,10847,10853,10859,\n\t10861,10867,10883,10889,10891,10903,10909,10937,\n\t10939,10949,10957,10973,10979,10987,10993,11003,\n\t11027,11047,11057,11059,11069,11071,11083,11087,\n\t11093,11113,11117,11119,11131,11149,11159,11161,\n\t11171,11173,11177,11197,11213,11239,11243,11251,\n\t11257,11261,11273,11279,11287,11299,11311,11317,\n\t11321,11329,11351,11353,11369,11383,11393,11399,\n\t11411,11423,11437,11443,11447,11467,11471,11483,\n\t11489,11491,11497,11503,11519,11527,11549,11551,\n\t11579,11587,11593,11597,11617,11621,11633,11657,\n\t11677,11681,11689,11699,11701,11717,11719,11731,\n\t11743,11777,11779,11783,11789,11801,11807,11813,\n\t11821,11827,11831,11833,11839,11863,11867,11887,\n\t11897,11903,11909,11923,11927,11933,11939,11941,\n\t11953,11959,11969,11971,11981,11987,12007,12011,\n\t12037,12041,12043,12049,12071,12073,12097,12101,\n\t12107,12109,12113,12119,12143,12149,12157,12161,\n\t12163,12197,12203,12211,12227,12239,12241,12251,\n\t12253,12263,12269,12277,12281,12289,12301,12323,\n\t12329,12343,12347,12373,12377,12379,12391,12401,\n\t12409,12413,12421,12433,12437,12451,12457,12473,\n\t12479,12487,12491,12497,12503,12511,12517,12527,\n\t12539,12541,12547,12553,12569,12577,12583,12589,\n\t12601,12611,12613,12619,12637,12641,12647,12653,\n\t12659,12671,12689,12697,12703,12713,12721,12739,\n\t12743,12757,12763,12781,12791,12799,12809,12821,\n\t12823,12829,12841,12853,12889,12893,12899,12907,\n\t12911,12917,12919,12923,12941,12953,12959,12967,\n\t12973,12979,12983,13001,13003,13007,13009,13033,\n\t13037,13043,13049,13063,13093,13099,13103,13109,\n\t13121,13127,13147,13151,13159,13163,13171,13177,\n\t13183,13187,13217,13219,13229,13241,13249,13259,\n\t13267,13291,13297,13309,13313,13327,13331,13337,\n\t13339,13367,13381,13397,13399,13411,13417,13421,\n\t13441,13451,13457,13463,13469,13477,13487,13499,\n\t13513,13523,13537,13553,13567,13577,13591,13597,\n\t13613,13619,13627,13633,13649,13669,13679,13681,\n\t13687,13691,13693,13697,13709,13711,13721,13723,\n\t13729,13751,13757,13759,13763,13781,13789,13799,\n\t13807,13829,13831,13841,13859,13873,13877,13879,\n\t13883,13901,13903,13907,13913,13921,13931,13933,\n\t13963,13967,13997,13999,14009,14011,14029,14033,\n\t14051,14057,14071,14081,14083,14087,14107,14143,\n\t14149,14153,14159,14173,14177,14197,14207,14221,\n\t14243,14249,14251,14281,14293,14303,14321,14323,\n\t14327,14341,14347,14369,14387,14389,14401,14407,\n\t14411,14419,14423,14431,14437,14447,14449,14461,\n\t14479,14489,14503,14519,14533,14537,14543,14549,\n\t14551,14557,14561,14563,14591,14593,14621,14627,\n\t14629,14633,14639,14653,14657,14669,14683,14699,\n\t14713,14717,14723,14731,14737,14741,14747,14753,\n\t14759,14767,14771,14779,14783,14797,14813,14821,\n\t14827,14831,14843,14851,14867,14869,14879,14887,\n\t14891,14897,14923,14929,14939,14947,14951,14957,\n\t14969,14983,15013,15017,15031,15053,15061,15073,\n\t15077,15083,15091,15101,15107,15121,15131,15137,\n\t15139,15149,15161,15173,15187,15193,15199,15217,\n\t15227,15233,15241,15259,15263,15269,15271,15277,\n\t15287,15289,15299,15307,15313,15319,15329,15331,\n\t15349,15359,15361,15373,15377,15383,15391,15401,\n\t15413,15427,15439,15443,15451,15461,15467,15473,\n\t15493,15497,15511,15527,15541,15551,15559,15569,\n\t15581,15583,15601,15607,15619,15629,15641,15643,\n\t15647,15649,15661,15667,15671,15679,15683,15727,\n\t15731,15733,15737,15739,15749,15761,15767,15773,\n\t15787,15791,15797,15803,15809,15817,15823,15859,\n\t15877,15881,15887,15889,15901,15907,15913,15919,\n\t15923,15937,15959,15971,15973,15991,16001,16007,\n\t16033,16057,16061,16063,16067,16069,16073,16087,\n\t16091,16097,16103,16111,16127,16139,16141,16183,\n\t16187,16189,16193,16217,16223,16229,16231,16249,\n\t16253,16267,16273,16301,16319,16333,16339,16349,\n\t16361,16363,16369,16381,16411,16417,16421,16427,\n\t16433,16447,16451,16453,16477,16481,16487,16493,\n\t16519,16529,16547,16553,16561,16567,16573,16603,\n\t16607,16619,16631,16633,16649,16651,16657,16661,\n\t16673,16691,16693,16699,16703,16729,16741,16747,\n\t16759,16763,16787,16811,16823,16829,16831,16843,\n\t16871,16879,16883,16889,16901,16903,16921,16927,\n\t16931,16937,16943,16963,16979,16981,16987,16993,\n\t17011,17021,17027,17029,17033,17041,17047,17053,\n\t17077,17093,17099,17107,17117,17123,17137,17159,\n\t17167,17183,17189,17191,17203,17207,17209,17231,\n\t17239,17257,17291,17293,17299,17317,17321,17327,\n\t17333,17341,17351,17359,17377,17383,17387,17389,\n\t17393,17401,17417,17419,17431,17443,17449,17467,\n\t17471,17477,17483,17489,17491,17497,17509,17519,\n\t17539,17551,17569,17573,17579,17581,17597,17599,\n\t17609,17623,17627,17657,17659,17669,17681,17683,\n\t17707,17713,17729,17737,17747,17749,17761,17783,\n\t17789,17791,17807,17827,17837,17839,17851,17863,\n#endif\n\t};\n"
  },
  {
    "path": "package/network/services/ead/src/tinysrp/bn_shift.c",
    "content": "/* crypto/bn/bn_shift.c */\n/* Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)\n * All rights reserved.\n *\n * This package is an SSL implementation written\n * by Eric Young (eay@cryptsoft.com).\n * The implementation was written so as to conform with Netscapes SSL.\n *\n * This library is free for commercial and non-commercial use as long as\n * the following conditions are aheared to.  The following conditions\n * apply to all code found in this distribution, be it the RC4, RSA,\n * lhash, DES, etc., code; not just the SSL code.  The SSL documentation\n * included with this distribution is covered by the same copyright terms\n * except that the holder is Tim Hudson (tjh@cryptsoft.com).\n *\n * Copyright remains Eric Young's, and as such any Copyright notices in\n * the code are not to be removed.\n * If this package is used in a product, Eric Young should be given attribution\n * as the author of the parts of the library used.\n * This can be in the form of a textual message at program startup or\n * in documentation (online or textual) provided with the package.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. All advertising materials mentioning features or use of this software\n *    must display the following acknowledgement:\n *    \"This product includes cryptographic software written by\n *     Eric Young (eay@cryptsoft.com)\"\n *    The word 'cryptographic' can be left out if the rouines from the library\n *    being used are not cryptographic related :-).\n * 4. If you include any Windows specific code (or a derivative thereof) from\n *    the apps directory (application code) you must include an acknowledgement:\n *    \"This product includes software written by Tim Hudson (tjh@cryptsoft.com)\"\n *\n * THIS SOFTWARE IS PROVIDED BY ERIC YOUNG ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n *\n * The licence and distribution terms for any publically available version or\n * derivative of this code cannot be changed.  i.e. this code cannot simply be\n * copied and put under another distribution licence\n * [including the GNU Public Licence.]\n */\n\n#include <stdio.h>\n#include <string.h>\n#include \"bn_lcl.h\"\n\nint BN_lshift(BIGNUM *r, const BIGNUM *a, int n)\n\t{\n\tint i,nw,lb,rb;\n\tBN_ULONG *t,*f;\n\tBN_ULONG l;\n\n\tr->neg=a->neg;\n\tif (bn_wexpand(r,a->top+(n/BN_BITS2)+1) == NULL) return(0);\n\tnw=n/BN_BITS2;\n\tlb=n%BN_BITS2;\n\trb=BN_BITS2-lb;\n\tf=a->d;\n\tt=r->d;\n\tt[a->top+nw]=0;\n\tif (lb == 0)\n\t\tfor (i=a->top-1; i>=0; i--)\n\t\t\tt[nw+i]=f[i];\n\telse\n\t\tfor (i=a->top-1; i>=0; i--)\n\t\t\t{\n\t\t\tl=f[i];\n\t\t\tt[nw+i+1]|=(l>>rb)&BN_MASK2;\n\t\t\tt[nw+i]=(l<<lb)&BN_MASK2;\n\t\t\t}\n\tmemset(t,0,nw*sizeof(t[0]));\n/*      for (i=0; i<nw; i++)\n\t\tt[i]=0;*/\n\tr->top=a->top+nw+1;\n\tbn_fix_top(r);\n\treturn(1);\n\t}\n\nint BN_rshift(BIGNUM *r, BIGNUM *a, int n)\n\t{\n\tint i,j,nw,lb,rb;\n\tBN_ULONG *t,*f;\n\tBN_ULONG l,tmp;\n\n\tnw=n/BN_BITS2;\n\trb=n%BN_BITS2;\n\tlb=BN_BITS2-rb;\n\tif (nw > a->top || a->top == 0)\n\t\t{\n\t\tBN_zero(r);\n\t\treturn(1);\n\t\t}\n\tif (r != a)\n\t\t{\n\t\tr->neg=a->neg;\n\t\tif (bn_wexpand(r,a->top-nw+1) == NULL) return(0);\n\t\t}\n\n\tf= &(a->d[nw]);\n\tt=r->d;\n\tj=a->top-nw;\n\tr->top=j;\n\n\tif (rb == 0)\n\t\t{\n\t\tfor (i=j+1; i > 0; i--)\n\t\t\t*(t++)= *(f++);\n\t\t}\n\telse\n\t\t{\n\t\tl= *(f++);\n\t\tfor (i=1; i<j; i++)\n\t\t\t{\n\t\t\ttmp =(l>>rb)&BN_MASK2;\n\t\t\tl= *(f++);\n\t\t\t*(t++) =(tmp|(l<<lb))&BN_MASK2;\n\t\t\t}\n\t\t*(t++) =(l>>rb)&BN_MASK2;\n\t\t}\n\t*t=0;\n\tbn_fix_top(r);\n\treturn(1);\n\t}\n"
  },
  {
    "path": "package/network/services/ead/src/tinysrp/bn_sqr.c",
    "content": "/* crypto/bn/bn_sqr.c */\n/* Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)\n * All rights reserved.\n *\n * This package is an SSL implementation written\n * by Eric Young (eay@cryptsoft.com).\n * The implementation was written so as to conform with Netscapes SSL.\n *\n * This library is free for commercial and non-commercial use as long as\n * the following conditions are aheared to.  The following conditions\n * apply to all code found in this distribution, be it the RC4, RSA,\n * lhash, DES, etc., code; not just the SSL code.  The SSL documentation\n * included with this distribution is covered by the same copyright terms\n * except that the holder is Tim Hudson (tjh@cryptsoft.com).\n *\n * Copyright remains Eric Young's, and as such any Copyright notices in\n * the code are not to be removed.\n * If this package is used in a product, Eric Young should be given attribution\n * as the author of the parts of the library used.\n * This can be in the form of a textual message at program startup or\n * in documentation (online or textual) provided with the package.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. All advertising materials mentioning features or use of this software\n *    must display the following acknowledgement:\n *    \"This product includes cryptographic software written by\n *     Eric Young (eay@cryptsoft.com)\"\n *    The word 'cryptographic' can be left out if the rouines from the library\n *    being used are not cryptographic related :-).\n * 4. If you include any Windows specific code (or a derivative thereof) from\n *    the apps directory (application code) you must include an acknowledgement:\n *    \"This product includes software written by Tim Hudson (tjh@cryptsoft.com)\"\n *\n * THIS SOFTWARE IS PROVIDED BY ERIC YOUNG ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n *\n * The licence and distribution terms for any publically available version or\n * derivative of this code cannot be changed.  i.e. this code cannot simply be\n * copied and put under another distribution licence\n * [including the GNU Public Licence.]\n */\n\n#include <stdio.h>\n#include <string.h>\n#include \"bn_lcl.h\"\n\n/* r must not be a */\n/* I've just gone over this and it is now %20 faster on x86 - eay - 27 Jun 96 */\nint BN_sqr(BIGNUM *r, BIGNUM *a, BN_CTX *ctx)\n\t{\n\tint max,al;\n\tint ret = 0;\n\tBIGNUM *tmp,*rr;\n\n#ifdef BN_COUNT\nprintf(\"BN_sqr %d * %d\\n\",a->top,a->top);\n#endif\n\tbn_check_top(a);\n\n\tal=a->top;\n\tif (al <= 0)\n\t\t{\n\t\tr->top=0;\n\t\treturn(1);\n\t\t}\n\n\tBN_CTX_start(ctx);\n\trr=(a != r) ? r : BN_CTX_get(ctx);\n\ttmp=BN_CTX_get(ctx);\n\tif (tmp == NULL) goto err;\n\n\tmax=(al+al);\n\tif (bn_wexpand(rr,max+1) == NULL) goto err;\n\n\tr->neg=0;\n\tif (al == 4)\n\t\t{\n#ifndef BN_SQR_COMBA\n\t\tBN_ULONG t[8];\n\t\tbn_sqr_normal(rr->d,a->d,4,t);\n#else\n\t\tbn_sqr_comba4(rr->d,a->d);\n#endif\n\t\t}\n\telse if (al == 8)\n\t\t{\n#ifndef BN_SQR_COMBA\n\t\tBN_ULONG t[16];\n\t\tbn_sqr_normal(rr->d,a->d,8,t);\n#else\n\t\tbn_sqr_comba8(rr->d,a->d);\n#endif\n\t\t}\n\telse\n\t\t{\n\t\tif (bn_wexpand(tmp,max) == NULL) goto err;\n\t\tbn_sqr_normal(rr->d,a->d,al,tmp->d);\n\t\t}\n\n\trr->top=max;\n\tif ((max > 0) && (rr->d[max-1] == 0)) rr->top--;\n\tif (rr != r) BN_copy(r,rr);\n\tret = 1;\n err:\n\tBN_CTX_end(ctx);\n\treturn(ret);\n\t}\n\n/* tmp must have 2*n words */\nvoid bn_sqr_normal(BN_ULONG *r, BN_ULONG *a, int n, BN_ULONG *tmp)\n\t{\n\tint i,j,max;\n\tBN_ULONG *ap,*rp;\n\n\tmax=n*2;\n\tap=a;\n\trp=r;\n\trp[0]=rp[max-1]=0;\n\trp++;\n\tj=n;\n\n\tif (--j > 0)\n\t\t{\n\t\tap++;\n\t\trp[j]=bn_mul_words(rp,ap,j,ap[-1]);\n\t\trp+=2;\n\t\t}\n\n\tfor (i=n-2; i>0; i--)\n\t\t{\n\t\tj--;\n\t\tap++;\n\t\trp[j]=bn_mul_add_words(rp,ap,j,ap[-1]);\n\t\trp+=2;\n\t\t}\n\n\tbn_add_words(r,r,r,max);\n\n\t/* There will not be a carry */\n\n\tbn_sqr_words(tmp,a,n);\n\n\tbn_add_words(r,r,tmp,max);\n\t}\n"
  },
  {
    "path": "package/network/services/ead/src/tinysrp/bn_word.c",
    "content": "/* crypto/bn/bn_word.c */\n/* Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)\n * All rights reserved.\n *\n * This package is an SSL implementation written\n * by Eric Young (eay@cryptsoft.com).\n * The implementation was written so as to conform with Netscapes SSL.\n *\n * This library is free for commercial and non-commercial use as long as\n * the following conditions are aheared to.  The following conditions\n * apply to all code found in this distribution, be it the RC4, RSA,\n * lhash, DES, etc., code; not just the SSL code.  The SSL documentation\n * included with this distribution is covered by the same copyright terms\n * except that the holder is Tim Hudson (tjh@cryptsoft.com).\n *\n * Copyright remains Eric Young's, and as such any Copyright notices in\n * the code are not to be removed.\n * If this package is used in a product, Eric Young should be given attribution\n * as the author of the parts of the library used.\n * This can be in the form of a textual message at program startup or\n * in documentation (online or textual) provided with the package.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. All advertising materials mentioning features or use of this software\n *    must display the following acknowledgement:\n *    \"This product includes cryptographic software written by\n *     Eric Young (eay@cryptsoft.com)\"\n *    The word 'cryptographic' can be left out if the rouines from the library\n *    being used are not cryptographic related :-).\n * 4. If you include any Windows specific code (or a derivative thereof) from\n *    the apps directory (application code) you must include an acknowledgement:\n *    \"This product includes software written by Tim Hudson (tjh@cryptsoft.com)\"\n *\n * THIS SOFTWARE IS PROVIDED BY ERIC YOUNG ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n *\n * The licence and distribution terms for any publically available version or\n * derivative of this code cannot be changed.  i.e. this code cannot simply be\n * copied and put under another distribution licence\n * [including the GNU Public Licence.]\n */\n\n#include <stdio.h>\n#include \"bn_lcl.h\"\n\nint BN_add_word(BIGNUM *a, BN_ULONG w)\n\t{\n\tBN_ULONG l;\n\tint i;\n\n\tif (a->neg)\n\t\t{\n\t\ta->neg=0;\n\t\ti=BN_sub_word(a,w);\n\t\tif (!BN_is_zero(a))\n\t\t\ta->neg=!(a->neg);\n\t\treturn(i);\n\t\t}\n\tw&=BN_MASK2;\n\tif (bn_wexpand(a,a->top+1) == NULL) return(0);\n\ti=0;\n\tfor (;;)\n\t\t{\n\t\tl=(a->d[i]+(BN_ULONG)w)&BN_MASK2;\n\t\ta->d[i]=l;\n\t\tif (w > l)\n\t\t\tw=1;\n\t\telse\n\t\t\tbreak;\n\t\ti++;\n\t\t}\n\tif (i >= a->top)\n\t\ta->top++;\n\treturn(1);\n\t}\n\nint BN_sub_word(BIGNUM *a, BN_ULONG w)\n\t{\n\tint i;\n\n\tif (BN_is_zero(a) || a->neg)\n\t\t{\n\t\ta->neg=0;\n\t\ti=BN_add_word(a,w);\n\t\ta->neg=1;\n\t\treturn(i);\n\t\t}\n\n\tw&=BN_MASK2;\n\tif ((a->top == 1) && (a->d[0] < w))\n\t\t{\n\t\ta->d[0]=w-a->d[0];\n\t\ta->neg=1;\n\t\treturn(1);\n\t\t}\n\ti=0;\n\tfor (;;)\n\t\t{\n\t\tif (a->d[i] >= w)\n\t\t\t{\n\t\t\ta->d[i]-=w;\n\t\t\tbreak;\n\t\t\t}\n\t\telse\n\t\t\t{\n\t\t\ta->d[i]=(a->d[i]-w)&BN_MASK2;\n\t\t\ti++;\n\t\t\tw=1;\n\t\t\t}\n\t\t}\n\tif ((a->d[i] == 0) && (i == (a->top-1)))\n\t\ta->top--;\n\treturn(1);\n\t}\n"
  },
  {
    "path": "package/network/services/ead/src/tinysrp/clitest.c",
    "content": "/*\n * Copyright (c) 1997-1999  The Stanford SRP Authentication Project\n * All Rights Reserved.\n *\n * Permission is hereby granted, free of charge, to any person obtaining\n * a copy of this software and associated documentation files (the\n * \"Software\"), to deal in the Software without restriction, including\n * without limitation the rights to use, copy, modify, merge, publish,\n * distribute, sublicense, and/or sell copies of the Software, and to\n * permit persons to whom the Software is furnished to do so, subject to\n * the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS-IS\" AND WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS, IMPLIED OR OTHERWISE, INCLUDING WITHOUT LIMITATION, ANY\n * WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.\n *\n * IN NO EVENT SHALL STANFORD BE LIABLE FOR ANY SPECIAL, INCIDENTAL,\n * INDIRECT OR CONSEQUENTIAL DAMAGES OF ANY KIND, OR ANY DAMAGES WHATSOEVER\n * RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER OR NOT ADVISED OF\n * THE POSSIBILITY OF DAMAGE, AND ON ANY THEORY OF LIABILITY, ARISING OUT\n * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n * In addition, the following conditions apply:\n *\n * 1. Any software that incorporates the SRP authentication technology\n *    must display the following acknowlegment:\n *    \"This product uses the 'Secure Remote Password' cryptographic\n *     authentication system developed by Tom Wu (tjw@CS.Stanford.EDU).\"\n *\n * 2. Any software that incorporates all or part of the SRP distribution\n *    itself must also display the following acknowledgment:\n *    \"This product includes software developed by Tom Wu and Eugene\n *     Jhong for the SRP Distribution (http://srp.stanford.edu/srp/).\"\n *\n * 3. Redistributions in source or binary form must retain an intact copy\n *    of this copyright notice and list of conditions.\n */\n\n#include <stdio.h>\n#include \"t_defines.h\"\n#include \"t_pwd.h\"\n#include \"t_client.h\"\n\nint\nmain()\n{\n  int index;\n  struct t_client * tc;\n  struct t_preconf *tcp;\n  struct t_num s;\n  struct t_num B;\n  char username[MAXUSERLEN];\n  char hexbuf[MAXHEXPARAMLEN];\n  char buf1[MAXPARAMLEN], buf2[MAXPARAMLEN], buf3[MAXSALTLEN];\n  unsigned char cbuf[20];\n  struct t_num * A;\n  unsigned char * skey;\n  char pass[128];\n\n  printf(\"Enter username: \");\n  fgets(username, sizeof(username), stdin);\n  username[strlen(username) - 1] = '\\0';\n  printf(\"Enter index (from server): \");\n  fgets(hexbuf, sizeof(hexbuf), stdin);\n  index = atoi(hexbuf);\n  tcp = t_getpreparam(index - 1);\n  printf(\"Enter salt (from server): \");\n  fgets(hexbuf, sizeof(hexbuf), stdin);\n  s.data = buf3;\n  s.len = t_fromb64(s.data, hexbuf);\n\n  tc = t_clientopen(username, &tcp->modulus, &tcp->generator, &s);\n  if (tc == 0) {\n    printf(\"invalid n, g\\n\");\n    exit(1);\n  }\n\n  A = t_clientgenexp(tc);\n  printf(\"A (to server): %s\\n\", t_tob64(hexbuf, A->data, A->len));\n\n  t_getpass(pass, 128, \"Enter password:\");\n  t_clientpasswd(tc, pass);\n\n  printf(\"Enter B (from server): \");\n  fgets(hexbuf, sizeof(hexbuf), stdin);\n  B.data = buf1;\n  B.len = t_fromb64(B.data, hexbuf);\n\n  skey = t_clientgetkey(tc, &B);\n  printf(\"Session key: %s\\n\", t_tohex(hexbuf, skey, 40));\n  printf(\"Response (to server): %s\\n\",\n    t_tohex(hexbuf, t_clientresponse(tc), RESPONSE_LEN));\n\n  printf(\"Enter server response: \");\n  fgets(hexbuf, sizeof(hexbuf), stdin);\n  hexbuf[strlen(hexbuf) - 1] = '\\0';\n  t_fromhex(cbuf, hexbuf);\n\n  if (t_clientverify(tc, cbuf) == 0)\n    printf(\"Server authentication successful.\\n\");\n  else\n    printf(\"Server authentication failed.\\n\");\n\n  t_clientclose(tc);\n\n  return 0;\n}\n"
  },
  {
    "path": "package/network/services/ead/src/tinysrp/config.h.in",
    "content": "/* config.h.in.  Generated automatically from configure.in by autoheader.  */\n\n/* Define if type char is unsigned and you are not using gcc.  */\n#ifndef __CHAR_UNSIGNED__\n#undef __CHAR_UNSIGNED__\n#endif\n\n/* Define to empty if the keyword does not work.  */\n#undef const\n\n/* Define as __inline if that's what the C compiler calls it.  */\n#undef inline\n\n/* Define as the return type of signal handlers (int or void).  */\n#undef RETSIGTYPE\n\n/* Define if you have the ANSI C header files.  */\n#undef STDC_HEADERS\n\n/* Define if you can safely include both <sys/time.h> and <time.h>.  */\n#undef TIME_WITH_SYS_TIME\n\n/* Define if your processor stores words with the most significant\n   byte first (like Motorola and SPARC, unlike Intel and VAX).  */\n#undef WORDS_BIGENDIAN\n\n#undef SHA1HANDSOFF\n\n#undef POSIX_TERMIOS\n\n#undef POSIX_SIGTYPE\n\n#undef volatile\n\n/* The number of bytes in a int.  */\n#undef SIZEOF_INT\n\n/* The number of bytes in a long.  */\n#undef SIZEOF_LONG\n\n/* The number of bytes in a long long.  */\n#undef SIZEOF_LONG_LONG\n\n/* The number of bytes in a short.  */\n#undef SIZEOF_SHORT\n\n/* Define if you have the memcpy function.  */\n#undef HAVE_MEMCPY\n\n/* Define if you have the sigaction function.  */\n#undef HAVE_SIGACTION\n\n/* Define if you have the strchr function.  */\n#undef HAVE_STRCHR\n\n/* Define if you have the <sgtty.h> header file.  */\n#undef HAVE_SGTTY_H\n\n/* Define if you have the <sys/ioctl.h> header file.  */\n#undef HAVE_SYS_IOCTL_H\n\n/* Define if you have the <sys/time.h> header file.  */\n#undef HAVE_SYS_TIME_H\n\n/* Define if you have the <termio.h> header file.  */\n#undef HAVE_TERMIO_H\n\n/* Define if you have the <termios.h> header file.  */\n#undef HAVE_TERMIOS_H\n\n/* Define if you have the <unistd.h> header file.  */\n#undef HAVE_UNISTD_H\n\n/* Name of package */\n#undef PACKAGE\n\n/* Version number of package */\n#undef VERSION\n\n"
  },
  {
    "path": "package/network/services/ead/src/tinysrp/configure",
    "content": "#! /bin/sh\n\n# Guess values for system-dependent variables and create Makefiles.\n# Generated automatically using autoconf version 2.13 \n# Copyright (C) 1992, 93, 94, 95, 96 Free Software Foundation, Inc.\n#\n# This configure script is free software; the Free Software Foundation\n# gives unlimited permission to copy, distribute and modify it.\n\n# Defaults:\nac_help=\nac_default_prefix=/usr/local\n# Any additions from configure.in:\n\n# Initialize some variables set by options.\n# The variables have the same names as the options, with\n# dashes changed to underlines.\nbuild=NONE\ncache_file=./config.cache\nexec_prefix=NONE\nhost=NONE\nno_create=\nnonopt=NONE\nno_recursion=\nprefix=NONE\nprogram_prefix=NONE\nprogram_suffix=NONE\nprogram_transform_name=s,x,x,\nsilent=\nsite=\nsrcdir=\ntarget=NONE\nverbose=\nx_includes=NONE\nx_libraries=NONE\nbindir='${exec_prefix}/bin'\nsbindir='${exec_prefix}/sbin'\nlibexecdir='${exec_prefix}/libexec'\ndatadir='${prefix}/share'\nsysconfdir='${prefix}/etc'\nsharedstatedir='${prefix}/com'\nlocalstatedir='${prefix}/var'\nlibdir='${exec_prefix}/lib'\nincludedir='${prefix}/include'\noldincludedir='/usr/include'\ninfodir='${prefix}/info'\nmandir='${prefix}/man'\n\n# Initialize some other variables.\nsubdirs=\nMFLAGS= MAKEFLAGS=\nSHELL=${CONFIG_SHELL-/bin/sh}\n# Maximum number of lines to put in a shell here document.\nac_max_here_lines=12\n\nac_prev=\nfor ac_option\ndo\n\n  # If the previous option needs an argument, assign it.\n  if test -n \"$ac_prev\"; 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These must not be set unconditionally\n# because not all systems understand e.g. LANG=C (notably SCO).\n# Fixing LC_MESSAGES prevents Solaris sh from translating var values in `set'!\n# Non-C LC_CTYPE values break the ctype check.\nif test \"${LANG+set}\"   = set; then LANG=C;   export LANG;   fi\nif test \"${LC_ALL+set}\" = set; then LC_ALL=C; export LC_ALL; fi\nif test \"${LC_MESSAGES+set}\" = set; then LC_MESSAGES=C; export LC_MESSAGES; fi\nif test \"${LC_CTYPE+set}\"    = set; then LC_CTYPE=C;    export LC_CTYPE;    fi\n\n# confdefs.h avoids OS command line length limits that DEFS can exceed.\nrm -rf conftest* confdefs.h\n# AIX cpp loses on an empty file, so make sure it contains at least a newline.\necho > confdefs.h\n\n# A filename unique to this package, relative to the directory that\n# configure is in, which we can look for to find out if srcdir is correct.\nac_unique_file=t_pwd.h\n\n# Find the source files, if location was not specified.\nif test -z \"$srcdir\"; then\n  ac_srcdir_defaulted=yes\n  # Try the directory containing this script, then its parent.\n  ac_prog=$0\n  ac_confdir=`echo $ac_prog|sed 's%/[^/][^/]*$%%'`\n  test \"x$ac_confdir\" = \"x$ac_prog\" && ac_confdir=.\n  srcdir=$ac_confdir\n  if test ! -r $srcdir/$ac_unique_file; then\n    srcdir=..\n  fi\nelse\n  ac_srcdir_defaulted=no\nfi\nif test ! -r $srcdir/$ac_unique_file; then\n  if test \"$ac_srcdir_defaulted\" = yes; then\n    { echo \"configure: error: can not find sources in $ac_confdir or ..\" 1>&2; exit 1; }\n  else\n    { echo \"configure: error: can not find sources in $srcdir\" 1>&2; exit 1; }\n  fi\nfi\nsrcdir=`echo \"${srcdir}\" | sed 's%\\([^/]\\)/*$%\\1%'`\n\n# Prefer explicitly selected file to automatically selected ones.\nif test -z \"$CONFIG_SITE\"; then\n  if test \"x$prefix\" != xNONE; then\n    CONFIG_SITE=\"$prefix/share/config.site $prefix/etc/config.site\"\n  else\n    CONFIG_SITE=\"$ac_default_prefix/share/config.site $ac_default_prefix/etc/config.site\"\n  fi\nfi\nfor ac_site_file in $CONFIG_SITE; do\n  if test -r \"$ac_site_file\"; then\n    echo \"loading site script $ac_site_file\"\n    . \"$ac_site_file\"\n  fi\ndone\n\nif test -r \"$cache_file\"; then\n  echo \"loading cache $cache_file\"\n  . $cache_file\nelse\n  echo \"creating cache $cache_file\"\n  > $cache_file\nfi\n\nac_ext=c\n# CFLAGS is not in ac_cpp because -g, -O, etc. are not valid cpp options.\nac_cpp='$CPP $CPPFLAGS'\nac_compile='${CC-cc} -c $CFLAGS $CPPFLAGS conftest.$ac_ext 1>&5'\nac_link='${CC-cc} -o conftest${ac_exeext} $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS 1>&5'\ncross_compiling=$ac_cv_prog_cc_cross\n\nac_exeext=\nac_objext=o\nif (echo \"testing\\c\"; echo 1,2,3) | grep c >/dev/null; then\n  # Stardent Vistra SVR4 grep lacks -e, says ghazi@caip.rutgers.edu.\n  if (echo -n testing; echo 1,2,3) | sed s/-n/xn/ | grep xn >/dev/null; then\n    ac_n= ac_c='\n' ac_t='\t'\n  else\n    ac_n=-n ac_c= ac_t=\n  fi\nelse\n  ac_n= ac_c='\\c' ac_t=\nfi\n\n\n\n\n\nac_aux_dir=\nfor ac_dir in $srcdir $srcdir/.. $srcdir/../..; do\n  if test -f $ac_dir/install-sh; then\n    ac_aux_dir=$ac_dir\n    ac_install_sh=\"$ac_aux_dir/install-sh -c\"\n    break\n  elif test -f $ac_dir/install.sh; then\n    ac_aux_dir=$ac_dir\n    ac_install_sh=\"$ac_aux_dir/install.sh -c\"\n    break\n  fi\ndone\nif test -z \"$ac_aux_dir\"; then\n  { echo \"configure: error: can not find install-sh or install.sh in $srcdir $srcdir/.. $srcdir/../..\" 1>&2; exit 1; }\nfi\nac_config_guess=$ac_aux_dir/config.guess\nac_config_sub=$ac_aux_dir/config.sub\nac_configure=$ac_aux_dir/configure # This should be Cygnus configure.\n\n# Find a good install program.  We prefer a C program (faster),\n# so one script is as good as another.  But avoid the broken or\n# incompatible versions:\n# SysV /etc/install, /usr/sbin/install\n# SunOS /usr/etc/install\n# IRIX /sbin/install\n# AIX /bin/install\n# AIX 4 /usr/bin/installbsd, which doesn't work without a -g flag\n# AFS /usr/afsws/bin/install, which mishandles nonexistent args\n# SVR4 /usr/ucb/install, which tries to use the nonexistent group \"staff\"\n# ./install, which can be erroneously created by make from ./install.sh.\necho $ac_n \"checking for a BSD compatible install\"\"... $ac_c\" 1>&6\necho \"configure:559: checking for a BSD compatible install\" >&5\nif test -z \"$INSTALL\"; then\nif eval \"test \\\"`echo '$''{'ac_cv_path_install'+set}'`\\\" = set\"; then\n  echo $ac_n \"(cached) $ac_c\" 1>&6\nelse\n    IFS=\"${IFS= \t}\"; ac_save_IFS=\"$IFS\"; IFS=\":\"\n  for ac_dir in $PATH; do\n    # Account for people who put trailing slashes in PATH elements.\n    case \"$ac_dir/\" in\n    /|./|.//|/etc/*|/usr/sbin/*|/usr/etc/*|/sbin/*|/usr/afsws/bin/*|/usr/ucb/*) ;;\n    *)\n      # OSF1 and SCO ODT 3.0 have their own names for install.\n      # Don't use installbsd from OSF since it installs stuff as root\n      # by default.\n      for ac_prog in ginstall scoinst install; do\n        if test -f $ac_dir/$ac_prog; then\n\t  if test $ac_prog = install &&\n            grep dspmsg $ac_dir/$ac_prog >/dev/null 2>&1; then\n\t    # AIX install.  It has an incompatible calling convention.\n\t    :\n\t  else\n\t    ac_cv_path_install=\"$ac_dir/$ac_prog -c\"\n\t    break 2\n\t  fi\n\tfi\n      done\n      ;;\n    esac\n  done\n  IFS=\"$ac_save_IFS\"\n\nfi\n  if test \"${ac_cv_path_install+set}\" = set; then\n    INSTALL=\"$ac_cv_path_install\"\n  else\n    # As a last resort, use the slow shell script.  We don't cache a\n    # path for INSTALL within a source directory, because that will\n    # break other packages using the cache if that directory is\n    # removed, or if the path is relative.\n    INSTALL=\"$ac_install_sh\"\n  fi\nfi\necho \"$ac_t\"\"$INSTALL\" 1>&6\n\n# Use test -z because SunOS4 sh mishandles braces in ${var-val}.\n# It thinks the first close brace ends the variable substitution.\ntest -z \"$INSTALL_PROGRAM\" && INSTALL_PROGRAM='${INSTALL}'\n\ntest -z \"$INSTALL_SCRIPT\" && INSTALL_SCRIPT='${INSTALL_PROGRAM}'\n\ntest -z \"$INSTALL_DATA\" && INSTALL_DATA='${INSTALL} -m 644'\n\necho $ac_n \"checking whether build environment is sane\"\"... $ac_c\" 1>&6\necho \"configure:612: checking whether build environment is sane\" >&5\n# Just in case\nsleep 1\necho timestamp > conftestfile\n# Do `set' in a subshell so we don't clobber the current shell's\n# arguments.  Must try -L first in case configure is actually a\n# symlink; some systems play weird games with the mod time of symlinks\n# (eg FreeBSD returns the mod time of the symlink's containing\n# directory).\nif (\n   set X `ls -Lt $srcdir/configure conftestfile 2> /dev/null`\n   if test \"$*\" = \"X\"; then\n      # -L didn't work.\n      set X `ls -t $srcdir/configure conftestfile`\n   fi\n   if test \"$*\" != \"X $srcdir/configure conftestfile\" \\\n      && test \"$*\" != \"X conftestfile $srcdir/configure\"; then\n\n      # If neither matched, then we have a broken ls.  This can happen\n      # if, for instance, CONFIG_SHELL is bash and it inherits a\n      # broken ls alias from the environment.  This has actually\n      # happened.  Such a system could not be considered \"sane\".\n      { echo \"configure: error: ls -t appears to fail.  Make sure there is not a broken\nalias in your environment\" 1>&2; exit 1; }\n   fi\n\n   test \"$2\" = conftestfile\n   )\nthen\n   # Ok.\n   :\nelse\n   { echo \"configure: error: newly created file is older than distributed files!\nCheck your system clock\" 1>&2; exit 1; }\nfi\nrm -f conftest*\necho \"$ac_t\"\"yes\" 1>&6\nif test \"$program_transform_name\" = s,x,x,; then\n  program_transform_name=\nelse\n  # Double any \\ or $.  echo might interpret backslashes.\n  cat <<\\EOF_SED > conftestsed\ns,\\\\,\\\\\\\\,g; s,\\$,$$,g\nEOF_SED\n  program_transform_name=\"`echo $program_transform_name|sed -f conftestsed`\"\n  rm -f conftestsed\nfi\ntest \"$program_prefix\" != NONE &&\n  program_transform_name=\"s,^,${program_prefix},; $program_transform_name\"\n# Use a double $ so make ignores it.\ntest \"$program_suffix\" != NONE &&\n  program_transform_name=\"s,\\$\\$,${program_suffix},; $program_transform_name\"\n\n# sed with no file args requires a program.\ntest \"$program_transform_name\" = \"\" && program_transform_name=\"s,x,x,\"\n\necho $ac_n \"checking whether ${MAKE-make} sets \\${MAKE}\"\"... $ac_c\" 1>&6\necho \"configure:669: checking whether ${MAKE-make} sets \\${MAKE}\" >&5\nset dummy ${MAKE-make}; ac_make=`echo \"$2\" | sed 'y%./+-%__p_%'`\nif eval \"test \\\"`echo '$''{'ac_cv_prog_make_${ac_make}_set'+set}'`\\\" = set\"; then\n  echo $ac_n \"(cached) $ac_c\" 1>&6\nelse\n  cat > conftestmake <<\\EOF\nall:\n\t@echo 'ac_maketemp=\"${MAKE}\"'\nEOF\n# GNU make sometimes prints \"make[1]: Entering...\", which would confuse us.\neval `${MAKE-make} -f conftestmake 2>/dev/null | grep temp=`\nif test -n \"$ac_maketemp\"; then\n  eval ac_cv_prog_make_${ac_make}_set=yes\nelse\n  eval ac_cv_prog_make_${ac_make}_set=no\nfi\nrm -f conftestmake\nfi\nif eval \"test \\\"`echo '$ac_cv_prog_make_'${ac_make}_set`\\\" = yes\"; then\n  echo \"$ac_t\"\"yes\" 1>&6\n  SET_MAKE=\nelse\n  echo \"$ac_t\"\"no\" 1>&6\n  SET_MAKE=\"MAKE=${MAKE-make}\"\nfi\n\n\n\nPACKAGE=libtinysrp\n\nVERSION=0.7.5\n\nif test \"`cd $srcdir && pwd`\" != \"`pwd`\" && test -f $srcdir/config.status; then\n  { echo \"configure: error: source directory already configured; run \"make distclean\" there first\" 1>&2; exit 1; }\nfi\ncat >> confdefs.h <<EOF\n#define PACKAGE \"$PACKAGE\"\nEOF\n\ncat >> confdefs.h <<EOF\n#define VERSION \"$VERSION\"\nEOF\n\n\n\nmissing_dir=`cd $ac_aux_dir && pwd`\necho $ac_n \"checking for working aclocal\"\"... $ac_c\" 1>&6\necho \"configure:716: checking for working aclocal\" >&5\n# Run test in a subshell; some versions of sh will print an error if\n# an executable is not found, even if stderr is redirected.\n# Redirect stdin to placate older versions of autoconf.  Sigh.\nif (aclocal --version) < /dev/null > /dev/null 2>&1; then\n   ACLOCAL=aclocal\n   echo \"$ac_t\"\"found\" 1>&6\nelse\n   ACLOCAL=\"$missing_dir/missing aclocal\"\n   echo \"$ac_t\"\"missing\" 1>&6\nfi\n\necho $ac_n \"checking for working autoconf\"\"... $ac_c\" 1>&6\necho \"configure:729: checking for working autoconf\" >&5\n# Run test in a subshell; some versions of sh will print an error if\n# an executable is not found, even if stderr is redirected.\n# Redirect stdin to placate older versions of autoconf.  Sigh.\nif (autoconf --version) < /dev/null > /dev/null 2>&1; then\n   AUTOCONF=autoconf\n   echo \"$ac_t\"\"found\" 1>&6\nelse\n   AUTOCONF=\"$missing_dir/missing autoconf\"\n   echo \"$ac_t\"\"missing\" 1>&6\nfi\n\necho $ac_n \"checking for working automake\"\"... $ac_c\" 1>&6\necho \"configure:742: checking for working automake\" >&5\n# Run test in a subshell; some versions of sh will print an error if\n# an executable is not found, even if stderr is redirected.\n# Redirect stdin to placate older versions of autoconf.  Sigh.\nif (automake --version) < /dev/null > /dev/null 2>&1; then\n   AUTOMAKE=automake\n   echo \"$ac_t\"\"found\" 1>&6\nelse\n   AUTOMAKE=\"$missing_dir/missing automake\"\n   echo \"$ac_t\"\"missing\" 1>&6\nfi\n\necho $ac_n \"checking for working autoheader\"\"... $ac_c\" 1>&6\necho \"configure:755: checking for working autoheader\" >&5\n# Run test in a subshell; some versions of sh will print an error if\n# an executable is not found, even if stderr is redirected.\n# Redirect stdin to placate older versions of autoconf.  Sigh.\nif (autoheader --version) < /dev/null > /dev/null 2>&1; then\n   AUTOHEADER=autoheader\n   echo \"$ac_t\"\"found\" 1>&6\nelse\n   AUTOHEADER=\"$missing_dir/missing autoheader\"\n   echo \"$ac_t\"\"missing\" 1>&6\nfi\n\necho $ac_n \"checking for working makeinfo\"\"... $ac_c\" 1>&6\necho \"configure:768: checking for working makeinfo\" >&5\n# Run test in a subshell; some versions of sh will print an error if\n# an executable is not found, even if stderr is redirected.\n# Redirect stdin to placate older versions of autoconf.  Sigh.\nif (makeinfo --version) < /dev/null > /dev/null 2>&1; then\n   MAKEINFO=makeinfo\n   echo \"$ac_t\"\"found\" 1>&6\nelse\n   MAKEINFO=\"$missing_dir/missing makeinfo\"\n   echo \"$ac_t\"\"missing\" 1>&6\nfi\n\n\n\ntest \"$CFLAGS\" = \"\" && CFLAGS=\"-O2\"\n\n\n# Extract the first word of \"gcc\", so it can be a program name with args.\nset dummy gcc; ac_word=$2\necho $ac_n \"checking for $ac_word\"\"... $ac_c\" 1>&6\necho \"configure:788: checking for $ac_word\" >&5\nif eval \"test \\\"`echo '$''{'ac_cv_prog_CC'+set}'`\\\" = set\"; then\n  echo $ac_n \"(cached) $ac_c\" 1>&6\nelse\n  if test -n \"$CC\"; then\n  ac_cv_prog_CC=\"$CC\" # Let the user override the test.\nelse\n  IFS=\"${IFS= \t}\"; ac_save_ifs=\"$IFS\"; IFS=\":\"\n  ac_dummy=\"$PATH\"\n  for ac_dir in $ac_dummy; do\n    test -z \"$ac_dir\" && ac_dir=.\n    if test -f $ac_dir/$ac_word; then\n      ac_cv_prog_CC=\"gcc\"\n      break\n    fi\n  done\n  IFS=\"$ac_save_ifs\"\nfi\nfi\nCC=\"$ac_cv_prog_CC\"\nif test -n \"$CC\"; then\n  echo \"$ac_t\"\"$CC\" 1>&6\nelse\n  echo \"$ac_t\"\"no\" 1>&6\nfi\n\nif test -z \"$CC\"; then\n  # Extract the first word of \"cc\", so it can be a program name with args.\nset dummy cc; ac_word=$2\necho $ac_n \"checking for $ac_word\"\"... $ac_c\" 1>&6\necho \"configure:818: checking for $ac_word\" >&5\nif eval \"test \\\"`echo '$''{'ac_cv_prog_CC'+set}'`\\\" = set\"; then\n  echo $ac_n \"(cached) $ac_c\" 1>&6\nelse\n  if test -n \"$CC\"; then\n  ac_cv_prog_CC=\"$CC\" # Let the user override the test.\nelse\n  IFS=\"${IFS= \t}\"; ac_save_ifs=\"$IFS\"; IFS=\":\"\n  ac_prog_rejected=no\n  ac_dummy=\"$PATH\"\n  for ac_dir in $ac_dummy; do\n    test -z \"$ac_dir\" && ac_dir=.\n    if test -f $ac_dir/$ac_word; then\n      if test \"$ac_dir/$ac_word\" = \"/usr/ucb/cc\"; then\n        ac_prog_rejected=yes\n\tcontinue\n      fi\n      ac_cv_prog_CC=\"cc\"\n      break\n    fi\n  done\n  IFS=\"$ac_save_ifs\"\nif test $ac_prog_rejected = yes; then\n  # We found a bogon in the path, so make sure we never use it.\n  set dummy $ac_cv_prog_CC\n  shift\n  if test $# -gt 0; then\n    # We chose a different compiler from the bogus one.\n    # However, it has the same basename, so the bogon will be chosen\n    # first if we set CC to just the basename; use the full file name.\n    shift\n    set dummy \"$ac_dir/$ac_word\" \"$@\"\n    shift\n    ac_cv_prog_CC=\"$@\"\n  fi\nfi\nfi\nfi\nCC=\"$ac_cv_prog_CC\"\nif test -n \"$CC\"; then\n  echo \"$ac_t\"\"$CC\" 1>&6\nelse\n  echo \"$ac_t\"\"no\" 1>&6\nfi\n\n  if test -z \"$CC\"; then\n    case \"`uname -s`\" in\n    *win32* | *WIN32*)\n      # Extract the first word of \"cl\", so it can be a program name with args.\nset dummy cl; ac_word=$2\necho $ac_n \"checking for $ac_word\"\"... $ac_c\" 1>&6\necho \"configure:869: checking for $ac_word\" >&5\nif eval \"test \\\"`echo '$''{'ac_cv_prog_CC'+set}'`\\\" = set\"; then\n  echo $ac_n \"(cached) $ac_c\" 1>&6\nelse\n  if test -n \"$CC\"; then\n  ac_cv_prog_CC=\"$CC\" # Let the user override the test.\nelse\n  IFS=\"${IFS= \t}\"; ac_save_ifs=\"$IFS\"; IFS=\":\"\n  ac_dummy=\"$PATH\"\n  for ac_dir in $ac_dummy; do\n    test -z \"$ac_dir\" && ac_dir=.\n    if test -f $ac_dir/$ac_word; then\n      ac_cv_prog_CC=\"cl\"\n      break\n    fi\n  done\n  IFS=\"$ac_save_ifs\"\nfi\nfi\nCC=\"$ac_cv_prog_CC\"\nif test -n \"$CC\"; then\n  echo \"$ac_t\"\"$CC\" 1>&6\nelse\n  echo \"$ac_t\"\"no\" 1>&6\nfi\n ;;\n    esac\n  fi\n  test -z \"$CC\" && { echo \"configure: error: no acceptable cc found in \\$PATH\" 1>&2; exit 1; }\nfi\n\necho $ac_n \"checking whether the C compiler ($CC $CFLAGS $LDFLAGS) works\"\"... $ac_c\" 1>&6\necho \"configure:901: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) works\" >&5\n\nac_ext=c\n# CFLAGS is not in ac_cpp because -g, -O, etc. are not valid cpp options.\nac_cpp='$CPP $CPPFLAGS'\nac_compile='${CC-cc} -c $CFLAGS $CPPFLAGS conftest.$ac_ext 1>&5'\nac_link='${CC-cc} -o conftest${ac_exeext} $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS 1>&5'\ncross_compiling=$ac_cv_prog_cc_cross\n\ncat > conftest.$ac_ext << EOF\n\n#line 912 \"configure\"\n#include \"confdefs.h\"\n\nmain(){return(0);}\nEOF\nif { (eval echo configure:917: \\\"$ac_link\\\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then\n  ac_cv_prog_cc_works=yes\n  # If we can't run a trivial program, we are probably using a cross compiler.\n  if (./conftest; exit) 2>/dev/null; then\n    ac_cv_prog_cc_cross=no\n  else\n    ac_cv_prog_cc_cross=yes\n  fi\nelse\n  echo \"configure: failed program was:\" >&5\n  cat conftest.$ac_ext >&5\n  ac_cv_prog_cc_works=no\nfi\nrm -fr conftest*\nac_ext=c\n# CFLAGS is not in ac_cpp because -g, -O, etc. are not valid cpp options.\nac_cpp='$CPP $CPPFLAGS'\nac_compile='${CC-cc} -c $CFLAGS $CPPFLAGS conftest.$ac_ext 1>&5'\nac_link='${CC-cc} -o conftest${ac_exeext} $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS 1>&5'\ncross_compiling=$ac_cv_prog_cc_cross\n\necho \"$ac_t\"\"$ac_cv_prog_cc_works\" 1>&6\nif test $ac_cv_prog_cc_works = no; then\n  { echo \"configure: error: installation or configuration problem: C compiler cannot create executables.\" 1>&2; exit 1; }\nfi\necho $ac_n \"checking whether the C compiler ($CC $CFLAGS $LDFLAGS) is a cross-compiler\"\"... $ac_c\" 1>&6\necho \"configure:943: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) is a cross-compiler\" >&5\necho \"$ac_t\"\"$ac_cv_prog_cc_cross\" 1>&6\ncross_compiling=$ac_cv_prog_cc_cross\n\necho $ac_n \"checking whether we are using GNU C\"\"... $ac_c\" 1>&6\necho \"configure:948: checking whether we are using GNU C\" >&5\nif eval \"test \\\"`echo '$''{'ac_cv_prog_gcc'+set}'`\\\" = set\"; then\n  echo $ac_n \"(cached) $ac_c\" 1>&6\nelse\n  cat > conftest.c <<EOF\n#ifdef __GNUC__\n  yes;\n#endif\nEOF\nif { ac_try='${CC-cc} -E conftest.c'; { (eval echo configure:957: \\\"$ac_try\\\") 1>&5; (eval $ac_try) 2>&5; }; } | egrep yes >/dev/null 2>&1; then\n  ac_cv_prog_gcc=yes\nelse\n  ac_cv_prog_gcc=no\nfi\nfi\n\necho \"$ac_t\"\"$ac_cv_prog_gcc\" 1>&6\n\nif test $ac_cv_prog_gcc = yes; then\n  GCC=yes\nelse\n  GCC=\nfi\n\nac_test_CFLAGS=\"${CFLAGS+set}\"\nac_save_CFLAGS=\"$CFLAGS\"\nCFLAGS=\necho $ac_n \"checking whether ${CC-cc} accepts -g\"\"... $ac_c\" 1>&6\necho \"configure:976: checking whether ${CC-cc} accepts -g\" >&5\nif eval \"test \\\"`echo '$''{'ac_cv_prog_cc_g'+set}'`\\\" = set\"; then\n  echo $ac_n \"(cached) $ac_c\" 1>&6\nelse\n  echo 'void f(){}' > conftest.c\nif test -z \"`${CC-cc} -g -c conftest.c 2>&1`\"; then\n  ac_cv_prog_cc_g=yes\nelse\n  ac_cv_prog_cc_g=no\nfi\nrm -f conftest*\n\nfi\n\necho \"$ac_t\"\"$ac_cv_prog_cc_g\" 1>&6\nif test \"$ac_test_CFLAGS\" = set; then\n  CFLAGS=\"$ac_save_CFLAGS\"\nelif test $ac_cv_prog_cc_g = yes; then\n  if test \"$GCC\" = yes; then\n    CFLAGS=\"-g -O2\"\n  else\n    CFLAGS=\"-g\"\n  fi\nelse\n  if test \"$GCC\" = yes; then\n    CFLAGS=\"-O2\"\n  else\n    CFLAGS=\n  fi\nfi\n\n# Find a good install program.  We prefer a C program (faster),\n# so one script is as good as another.  But avoid the broken or\n# incompatible versions:\n# SysV /etc/install, /usr/sbin/install\n# SunOS /usr/etc/install\n# IRIX /sbin/install\n# AIX /bin/install\n# AIX 4 /usr/bin/installbsd, which doesn't work without a -g flag\n# AFS /usr/afsws/bin/install, which mishandles nonexistent args\n# SVR4 /usr/ucb/install, which tries to use the nonexistent group \"staff\"\n# ./install, which can be erroneously created by make from ./install.sh.\necho $ac_n \"checking for a BSD compatible install\"\"... $ac_c\" 1>&6\necho \"configure:1019: checking for a BSD compatible install\" >&5\nif test -z \"$INSTALL\"; then\nif eval \"test \\\"`echo '$''{'ac_cv_path_install'+set}'`\\\" = set\"; then\n  echo $ac_n \"(cached) $ac_c\" 1>&6\nelse\n    IFS=\"${IFS= \t}\"; ac_save_IFS=\"$IFS\"; IFS=\":\"\n  for ac_dir in $PATH; do\n    # Account for people who put trailing slashes in PATH elements.\n    case \"$ac_dir/\" in\n    /|./|.//|/etc/*|/usr/sbin/*|/usr/etc/*|/sbin/*|/usr/afsws/bin/*|/usr/ucb/*) ;;\n    *)\n      # OSF1 and SCO ODT 3.0 have their own names for install.\n      # Don't use installbsd from OSF since it installs stuff as root\n      # by default.\n      for ac_prog in ginstall scoinst install; do\n        if test -f $ac_dir/$ac_prog; then\n\t  if test $ac_prog = install &&\n            grep dspmsg $ac_dir/$ac_prog >/dev/null 2>&1; then\n\t    # AIX install.  It has an incompatible calling convention.\n\t    :\n\t  else\n\t    ac_cv_path_install=\"$ac_dir/$ac_prog -c\"\n\t    break 2\n\t  fi\n\tfi\n      done\n      ;;\n    esac\n  done\n  IFS=\"$ac_save_IFS\"\n\nfi\n  if test \"${ac_cv_path_install+set}\" = set; then\n    INSTALL=\"$ac_cv_path_install\"\n  else\n    # As a last resort, use the slow shell script.  We don't cache a\n    # path for INSTALL within a source directory, because that will\n    # break other packages using the cache if that directory is\n    # removed, or if the path is relative.\n    INSTALL=\"$ac_install_sh\"\n  fi\nfi\necho \"$ac_t\"\"$INSTALL\" 1>&6\n\n# Use test -z because SunOS4 sh mishandles braces in ${var-val}.\n# It thinks the first close brace ends the variable substitution.\ntest -z \"$INSTALL_PROGRAM\" && INSTALL_PROGRAM='${INSTALL}'\n\ntest -z \"$INSTALL_SCRIPT\" && INSTALL_SCRIPT='${INSTALL_PROGRAM}'\n\ntest -z \"$INSTALL_DATA\" && INSTALL_DATA='${INSTALL} -m 644'\n\necho $ac_n \"checking whether ln -s works\"\"... $ac_c\" 1>&6\necho \"configure:1072: checking whether ln -s works\" >&5\nif eval \"test \\\"`echo '$''{'ac_cv_prog_LN_S'+set}'`\\\" = set\"; then\n  echo $ac_n \"(cached) $ac_c\" 1>&6\nelse\n  rm -f conftestdata\nif ln -s X conftestdata 2>/dev/null\nthen\n  rm -f conftestdata\n  ac_cv_prog_LN_S=\"ln -s\"\nelse\n  ac_cv_prog_LN_S=ln\nfi\nfi\nLN_S=\"$ac_cv_prog_LN_S\"\nif test \"$ac_cv_prog_LN_S\" = \"ln -s\"; then\n  echo \"$ac_t\"\"yes\" 1>&6\nelse\n  echo \"$ac_t\"\"no\" 1>&6\nfi\n\n# Extract the first word of \"ranlib\", so it can be a program name with args.\nset dummy ranlib; ac_word=$2\necho $ac_n \"checking for $ac_word\"\"... $ac_c\" 1>&6\necho \"configure:1095: checking for $ac_word\" >&5\nif eval \"test \\\"`echo '$''{'ac_cv_prog_RANLIB'+set}'`\\\" = set\"; then\n  echo $ac_n \"(cached) $ac_c\" 1>&6\nelse\n  if test -n \"$RANLIB\"; then\n  ac_cv_prog_RANLIB=\"$RANLIB\" # Let the user override the test.\nelse\n  IFS=\"${IFS= \t}\"; ac_save_ifs=\"$IFS\"; IFS=\":\"\n  ac_dummy=\"$PATH\"\n  for ac_dir in $ac_dummy; do\n    test -z \"$ac_dir\" && ac_dir=.\n    if test -f $ac_dir/$ac_word; then\n      ac_cv_prog_RANLIB=\"ranlib\"\n      break\n    fi\n  done\n  IFS=\"$ac_save_ifs\"\n  test -z \"$ac_cv_prog_RANLIB\" && ac_cv_prog_RANLIB=\":\"\nfi\nfi\nRANLIB=\"$ac_cv_prog_RANLIB\"\nif test -n \"$RANLIB\"; then\n  echo \"$ac_t\"\"$RANLIB\" 1>&6\nelse\n  echo \"$ac_t\"\"no\" 1>&6\nfi\n\nif test \"$program_transform_name\" = s,x,x,; then\n  program_transform_name=\nelse\n  # Double any \\ or $.  echo might interpret backslashes.\n  cat <<\\EOF_SED > conftestsed\ns,\\\\,\\\\\\\\,g; s,\\$,$$,g\nEOF_SED\n  program_transform_name=\"`echo $program_transform_name|sed -f conftestsed`\"\n  rm -f conftestsed\nfi\ntest \"$program_prefix\" != NONE &&\n  program_transform_name=\"s,^,${program_prefix},; $program_transform_name\"\n# Use a double $ so make ignores it.\ntest \"$program_suffix\" != NONE &&\n  program_transform_name=\"s,\\$\\$,${program_suffix},; $program_transform_name\"\n\n# sed with no file args requires a program.\ntest \"$program_transform_name\" = \"\" && program_transform_name=\"s,x,x,\"\n\n\n\necho $ac_n \"checking how to run the C preprocessor\"\"... $ac_c\" 1>&6\necho \"configure:1144: checking how to run the C preprocessor\" >&5\n# On Suns, sometimes $CPP names a directory.\nif test -n \"$CPP\" && test -d \"$CPP\"; then\n  CPP=\nfi\nif test -z \"$CPP\"; then\nif eval \"test \\\"`echo '$''{'ac_cv_prog_CPP'+set}'`\\\" = set\"; then\n  echo $ac_n \"(cached) $ac_c\" 1>&6\nelse\n    # This must be in double quotes, not single quotes, because CPP may get\n  # substituted into the Makefile and \"${CC-cc}\" will confuse make.\n  CPP=\"${CC-cc} -E\"\n  # On the NeXT, cc -E runs the code through the compiler's parser,\n  # not just through cpp.\n  cat > conftest.$ac_ext <<EOF\n#line 1159 \"configure\"\n#include \"confdefs.h\"\n#include <assert.h>\nSyntax Error\nEOF\nac_try=\"$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out\"\n{ (eval echo configure:1165: \\\"$ac_try\\\") 1>&5; (eval $ac_try) 2>&5; }\nac_err=`grep -v '^ *+' conftest.out | grep -v \"^conftest.${ac_ext}\\$\"`\nif test -z \"$ac_err\"; then\n  :\nelse\n  echo \"$ac_err\" >&5\n  echo \"configure: failed program was:\" >&5\n  cat conftest.$ac_ext >&5\n  rm -rf conftest*\n  CPP=\"${CC-cc} -E -traditional-cpp\"\n  cat > conftest.$ac_ext <<EOF\n#line 1176 \"configure\"\n#include \"confdefs.h\"\n#include <assert.h>\nSyntax Error\nEOF\nac_try=\"$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out\"\n{ (eval echo configure:1182: \\\"$ac_try\\\") 1>&5; (eval $ac_try) 2>&5; }\nac_err=`grep -v '^ *+' conftest.out | grep -v \"^conftest.${ac_ext}\\$\"`\nif test -z \"$ac_err\"; then\n  :\nelse\n  echo \"$ac_err\" >&5\n  echo \"configure: failed program was:\" >&5\n  cat conftest.$ac_ext >&5\n  rm -rf conftest*\n  CPP=\"${CC-cc} -nologo -E\"\n  cat > conftest.$ac_ext <<EOF\n#line 1193 \"configure\"\n#include \"confdefs.h\"\n#include <assert.h>\nSyntax Error\nEOF\nac_try=\"$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out\"\n{ (eval echo configure:1199: \\\"$ac_try\\\") 1>&5; (eval $ac_try) 2>&5; }\nac_err=`grep -v '^ *+' conftest.out | grep -v \"^conftest.${ac_ext}\\$\"`\nif test -z \"$ac_err\"; then\n  :\nelse\n  echo \"$ac_err\" >&5\n  echo \"configure: failed program was:\" >&5\n  cat conftest.$ac_ext >&5\n  rm -rf conftest*\n  CPP=/lib/cpp\nfi\nrm -f conftest*\nfi\nrm -f conftest*\nfi\nrm -f conftest*\n  ac_cv_prog_CPP=\"$CPP\"\nfi\n  CPP=\"$ac_cv_prog_CPP\"\nelse\n  ac_cv_prog_CPP=\"$CPP\"\nfi\necho \"$ac_t\"\"$CPP\" 1>&6\n\necho $ac_n \"checking for ANSI C header files\"\"... $ac_c\" 1>&6\necho \"configure:1224: checking for ANSI C header files\" >&5\nif eval \"test \\\"`echo '$''{'ac_cv_header_stdc'+set}'`\\\" = set\"; then\n  echo $ac_n \"(cached) $ac_c\" 1>&6\nelse\n  cat > conftest.$ac_ext <<EOF\n#line 1229 \"configure\"\n#include \"confdefs.h\"\n#include <stdlib.h>\n#include <stdarg.h>\n#include <string.h>\n#include <float.h>\nEOF\nac_try=\"$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out\"\n{ (eval echo configure:1237: \\\"$ac_try\\\") 1>&5; (eval $ac_try) 2>&5; }\nac_err=`grep -v '^ *+' conftest.out | grep -v \"^conftest.${ac_ext}\\$\"`\nif test -z \"$ac_err\"; then\n  rm -rf conftest*\n  ac_cv_header_stdc=yes\nelse\n  echo \"$ac_err\" >&5\n  echo \"configure: failed program was:\" >&5\n  cat conftest.$ac_ext >&5\n  rm -rf conftest*\n  ac_cv_header_stdc=no\nfi\nrm -f conftest*\n\nif test $ac_cv_header_stdc = yes; then\n  # SunOS 4.x string.h does not declare mem*, contrary to ANSI.\ncat > conftest.$ac_ext <<EOF\n#line 1254 \"configure\"\n#include \"confdefs.h\"\n#include <string.h>\nEOF\nif (eval \"$ac_cpp conftest.$ac_ext\") 2>&5 |\n  egrep \"memchr\" >/dev/null 2>&1; then\n  :\nelse\n  rm -rf conftest*\n  ac_cv_header_stdc=no\nfi\nrm -f conftest*\n\nfi\n\nif test $ac_cv_header_stdc = yes; then\n  # ISC 2.0.2 stdlib.h does not declare free, contrary to ANSI.\ncat > conftest.$ac_ext <<EOF\n#line 1272 \"configure\"\n#include \"confdefs.h\"\n#include <stdlib.h>\nEOF\nif (eval \"$ac_cpp conftest.$ac_ext\") 2>&5 |\n  egrep \"free\" >/dev/null 2>&1; then\n  :\nelse\n  rm -rf conftest*\n  ac_cv_header_stdc=no\nfi\nrm -f conftest*\n\nfi\n\nif test $ac_cv_header_stdc = yes; then\n  # /bin/cc in Irix-4.0.5 gets non-ANSI ctype macros unless using -ansi.\nif test \"$cross_compiling\" = yes; then\n  :\nelse\n  cat > conftest.$ac_ext <<EOF\n#line 1293 \"configure\"\n#include \"confdefs.h\"\n#include <ctype.h>\n#define ISLOWER(c) ('a' <= (c) && (c) <= 'z')\n#define TOUPPER(c) (ISLOWER(c) ? 'A' + ((c) - 'a') : (c))\n#define XOR(e, f) (((e) && !(f)) || (!(e) && (f)))\nint main () { int i; for (i = 0; i < 256; i++)\nif (XOR (islower (i), ISLOWER (i)) || toupper (i) != TOUPPER (i)) exit(2);\nexit (0); }\n\nEOF\nif { (eval echo configure:1304: \\\"$ac_link\\\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null\nthen\n  :\nelse\n  echo \"configure: failed program was:\" >&5\n  cat conftest.$ac_ext >&5\n  rm -fr conftest*\n  ac_cv_header_stdc=no\nfi\nrm -fr conftest*\nfi\n\nfi\nfi\n\necho \"$ac_t\"\"$ac_cv_header_stdc\" 1>&6\nif test $ac_cv_header_stdc = yes; then\n  cat >> confdefs.h <<\\EOF\n#define STDC_HEADERS 1\nEOF\n\nfi\n\nfor ac_hdr in sgtty.h sys/ioctl.h sys/time.h termio.h termios.h unistd.h\ndo\nac_safe=`echo \"$ac_hdr\" | sed 'y%./+-%__p_%'`\necho $ac_n \"checking for $ac_hdr\"\"... $ac_c\" 1>&6\necho \"configure:1331: checking for $ac_hdr\" >&5\nif eval \"test \\\"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\\\" = set\"; then\n  echo $ac_n \"(cached) $ac_c\" 1>&6\nelse\n  cat > conftest.$ac_ext <<EOF\n#line 1336 \"configure\"\n#include \"confdefs.h\"\n#include <$ac_hdr>\nEOF\nac_try=\"$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out\"\n{ (eval echo configure:1341: \\\"$ac_try\\\") 1>&5; (eval $ac_try) 2>&5; }\nac_err=`grep -v '^ *+' conftest.out | grep -v \"^conftest.${ac_ext}\\$\"`\nif test -z \"$ac_err\"; then\n  rm -rf conftest*\n  eval \"ac_cv_header_$ac_safe=yes\"\nelse\n  echo \"$ac_err\" >&5\n  echo \"configure: failed program was:\" >&5\n  cat conftest.$ac_ext >&5\n  rm -rf conftest*\n  eval \"ac_cv_header_$ac_safe=no\"\nfi\nrm -f conftest*\nfi\nif eval \"test \\\"`echo '$ac_cv_header_'$ac_safe`\\\" = yes\"; then\n  echo \"$ac_t\"\"yes\" 1>&6\n    ac_tr_hdr=HAVE_`echo $ac_hdr | sed 'y%abcdefghijklmnopqrstuvwxyz./-%ABCDEFGHIJKLMNOPQRSTUVWXYZ___%'`\n  cat >> confdefs.h <<EOF\n#define $ac_tr_hdr 1\nEOF\n \nelse\n  echo \"$ac_t\"\"no\" 1>&6\nfi\ndone\n\n\n\necho $ac_n \"checking for working const\"\"... $ac_c\" 1>&6\necho \"configure:1370: checking for working const\" >&5\nif eval \"test \\\"`echo '$''{'ac_cv_c_const'+set}'`\\\" = set\"; then\n  echo $ac_n \"(cached) $ac_c\" 1>&6\nelse\n  cat > conftest.$ac_ext <<EOF\n#line 1375 \"configure\"\n#include \"confdefs.h\"\n\nint main() {\n\n/* Ultrix mips cc rejects this.  */\ntypedef int charset[2]; const charset x;\n/* SunOS 4.1.1 cc rejects this.  */\nchar const *const *ccp;\nchar **p;\n/* NEC SVR4.0.2 mips cc rejects this.  */\nstruct point {int x, y;};\nstatic struct point const zero = {0,0};\n/* AIX XL C 1.02.0.0 rejects this.\n   It does not let you subtract one const X* pointer from another in an arm\n   of an if-expression whose if-part is not a constant expression */\nconst char *g = \"string\";\nccp = &g + (g ? g-g : 0);\n/* HPUX 7.0 cc rejects these. */\n++ccp;\np = (char**) ccp;\nccp = (char const *const *) p;\n{ /* SCO 3.2v4 cc rejects this.  */\n  char *t;\n  char const *s = 0 ? (char *) 0 : (char const *) 0;\n\n  *t++ = 0;\n}\n{ /* Someone thinks the Sun supposedly-ANSI compiler will reject this.  */\n  int x[] = {25, 17};\n  const int *foo = &x[0];\n  ++foo;\n}\n{ /* Sun SC1.0 ANSI compiler rejects this -- but not the above. */\n  typedef const int *iptr;\n  iptr p = 0;\n  ++p;\n}\n{ /* AIX XL C 1.02.0.0 rejects this saying\n     \"k.c\", line 2.27: 1506-025 (S) Operand must be a modifiable lvalue. */\n  struct s { int j; const int *ap[3]; };\n  struct s *b; b->j = 5;\n}\n{ /* ULTRIX-32 V3.1 (Rev 9) vcc rejects this */\n  const int foo = 10;\n}\n\n; return 0; }\nEOF\nif { (eval echo configure:1424: \\\"$ac_compile\\\") 1>&5; (eval $ac_compile) 2>&5; }; then\n  rm -rf conftest*\n  ac_cv_c_const=yes\nelse\n  echo \"configure: failed program was:\" >&5\n  cat conftest.$ac_ext >&5\n  rm -rf conftest*\n  ac_cv_c_const=no\nfi\nrm -f conftest*\nfi\n\necho \"$ac_t\"\"$ac_cv_c_const\" 1>&6\nif test $ac_cv_c_const = no; then\n  cat >> confdefs.h <<\\EOF\n#define const \nEOF\n\nfi\n\necho $ac_n \"checking for inline\"\"... $ac_c\" 1>&6\necho \"configure:1445: checking for inline\" >&5\nif eval \"test \\\"`echo '$''{'ac_cv_c_inline'+set}'`\\\" = set\"; then\n  echo $ac_n \"(cached) $ac_c\" 1>&6\nelse\n  ac_cv_c_inline=no\nfor ac_kw in inline __inline__ __inline; do\n  cat > conftest.$ac_ext <<EOF\n#line 1452 \"configure\"\n#include \"confdefs.h\"\n\nint main() {\n} $ac_kw foo() {\n; return 0; }\nEOF\nif { (eval echo configure:1459: \\\"$ac_compile\\\") 1>&5; (eval $ac_compile) 2>&5; }; then\n  rm -rf conftest*\n  ac_cv_c_inline=$ac_kw; break\nelse\n  echo \"configure: failed program was:\" >&5\n  cat conftest.$ac_ext >&5\nfi\nrm -f conftest*\ndone\n\nfi\n\necho \"$ac_t\"\"$ac_cv_c_inline\" 1>&6\ncase \"$ac_cv_c_inline\" in\n  inline | yes) ;;\n  no) cat >> confdefs.h <<\\EOF\n#define inline \nEOF\n ;;\n  *)  cat >> confdefs.h <<EOF\n#define inline $ac_cv_c_inline\nEOF\n ;;\nesac\n\necho $ac_n \"checking whether time.h and sys/time.h may both be included\"\"... $ac_c\" 1>&6\necho \"configure:1485: checking whether time.h and sys/time.h may both be included\" >&5\nif eval \"test \\\"`echo '$''{'ac_cv_header_time'+set}'`\\\" = set\"; then\n  echo $ac_n \"(cached) $ac_c\" 1>&6\nelse\n  cat > conftest.$ac_ext <<EOF\n#line 1490 \"configure\"\n#include \"confdefs.h\"\n#include <sys/types.h>\n#include <sys/time.h>\n#include <time.h>\nint main() {\nstruct tm *tp;\n; return 0; }\nEOF\nif { (eval echo configure:1499: \\\"$ac_compile\\\") 1>&5; (eval $ac_compile) 2>&5; }; then\n  rm -rf conftest*\n  ac_cv_header_time=yes\nelse\n  echo \"configure: failed program was:\" >&5\n  cat conftest.$ac_ext >&5\n  rm -rf conftest*\n  ac_cv_header_time=no\nfi\nrm -f conftest*\nfi\n\necho \"$ac_t\"\"$ac_cv_header_time\" 1>&6\nif test $ac_cv_header_time = yes; then\n  cat >> confdefs.h <<\\EOF\n#define TIME_WITH_SYS_TIME 1\nEOF\n\nfi\n\necho $ac_n \"checking whether byte ordering is bigendian\"\"... $ac_c\" 1>&6\necho \"configure:1520: checking whether byte ordering is bigendian\" >&5\nif eval \"test \\\"`echo '$''{'ac_cv_c_bigendian'+set}'`\\\" = set\"; then\n  echo $ac_n \"(cached) $ac_c\" 1>&6\nelse\n  ac_cv_c_bigendian=unknown\n# See if sys/param.h defines the BYTE_ORDER macro.\ncat > conftest.$ac_ext <<EOF\n#line 1527 \"configure\"\n#include \"confdefs.h\"\n#include <sys/types.h>\n#include <sys/param.h>\nint main() {\n\n#if !BYTE_ORDER || !BIG_ENDIAN || !LITTLE_ENDIAN\n bogus endian macros\n#endif\n; return 0; }\nEOF\nif { (eval echo configure:1538: \\\"$ac_compile\\\") 1>&5; (eval $ac_compile) 2>&5; }; then\n  rm -rf conftest*\n  # It does; now see whether it defined to BIG_ENDIAN or not.\ncat > conftest.$ac_ext <<EOF\n#line 1542 \"configure\"\n#include \"confdefs.h\"\n#include <sys/types.h>\n#include <sys/param.h>\nint main() {\n\n#if BYTE_ORDER != BIG_ENDIAN\n not big endian\n#endif\n; return 0; }\nEOF\nif { (eval echo configure:1553: \\\"$ac_compile\\\") 1>&5; (eval $ac_compile) 2>&5; }; then\n  rm -rf conftest*\n  ac_cv_c_bigendian=yes\nelse\n  echo \"configure: failed program was:\" >&5\n  cat conftest.$ac_ext >&5\n  rm -rf conftest*\n  ac_cv_c_bigendian=no\nfi\nrm -f conftest*\nelse\n  echo \"configure: failed program was:\" >&5\n  cat conftest.$ac_ext >&5\nfi\nrm -f conftest*\nif test $ac_cv_c_bigendian = unknown; then\nif test \"$cross_compiling\" = yes; then\n    { echo \"configure: error: can not run test program while cross compiling\" 1>&2; exit 1; }\nelse\n  cat > conftest.$ac_ext <<EOF\n#line 1573 \"configure\"\n#include \"confdefs.h\"\nmain () {\n  /* Are we little or big endian?  From Harbison&Steele.  */\n  union\n  {\n    long l;\n    char c[sizeof (long)];\n  } u;\n  u.l = 1;\n  exit (u.c[sizeof (long) - 1] == 1);\n}\nEOF\nif { (eval echo configure:1586: \\\"$ac_link\\\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null\nthen\n  ac_cv_c_bigendian=no\nelse\n  echo \"configure: failed program was:\" >&5\n  cat conftest.$ac_ext >&5\n  rm -fr conftest*\n  ac_cv_c_bigendian=yes\nfi\nrm -fr conftest*\nfi\n\nfi\nfi\n\necho \"$ac_t\"\"$ac_cv_c_bigendian\" 1>&6\nif test $ac_cv_c_bigendian = yes; then\n  cat >> confdefs.h <<\\EOF\n#define WORDS_BIGENDIAN 1\nEOF\n\nfi\n\necho $ac_n \"checking size of short\"\"... $ac_c\" 1>&6\necho \"configure:1610: checking size of short\" >&5\nif eval \"test \\\"`echo '$''{'ac_cv_sizeof_short'+set}'`\\\" = set\"; then\n  echo $ac_n \"(cached) $ac_c\" 1>&6\nelse\n  if test \"$cross_compiling\" = yes; then\n    { echo \"configure: error: can not run test program while cross compiling\" 1>&2; exit 1; }\nelse\n  cat > conftest.$ac_ext <<EOF\n#line 1618 \"configure\"\n#include \"confdefs.h\"\n#include <stdio.h>\nmain()\n{\n  FILE *f=fopen(\"conftestval\", \"w\");\n  if (!f) exit(1);\n  fprintf(f, \"%d\\n\", sizeof(short));\n  exit(0);\n}\nEOF\nif { (eval echo configure:1629: \\\"$ac_link\\\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null\nthen\n  ac_cv_sizeof_short=`cat conftestval`\nelse\n  echo \"configure: failed program was:\" >&5\n  cat conftest.$ac_ext >&5\n  rm -fr conftest*\n  ac_cv_sizeof_short=0\nfi\nrm -fr conftest*\nfi\n\nfi\necho \"$ac_t\"\"$ac_cv_sizeof_short\" 1>&6\ncat >> confdefs.h <<EOF\n#define SIZEOF_SHORT $ac_cv_sizeof_short\nEOF\n\n\necho $ac_n \"checking size of int\"\"... $ac_c\" 1>&6\necho \"configure:1649: checking size of int\" >&5\nif eval \"test \\\"`echo '$''{'ac_cv_sizeof_int'+set}'`\\\" = set\"; then\n  echo $ac_n \"(cached) $ac_c\" 1>&6\nelse\n  if test \"$cross_compiling\" = yes; then\n    { echo \"configure: error: can not run test program while cross compiling\" 1>&2; exit 1; }\nelse\n  cat > conftest.$ac_ext <<EOF\n#line 1657 \"configure\"\n#include \"confdefs.h\"\n#include <stdio.h>\nmain()\n{\n  FILE *f=fopen(\"conftestval\", \"w\");\n  if (!f) exit(1);\n  fprintf(f, \"%d\\n\", sizeof(int));\n  exit(0);\n}\nEOF\nif { (eval echo configure:1668: \\\"$ac_link\\\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null\nthen\n  ac_cv_sizeof_int=`cat conftestval`\nelse\n  echo \"configure: failed program was:\" >&5\n  cat conftest.$ac_ext >&5\n  rm -fr conftest*\n  ac_cv_sizeof_int=0\nfi\nrm -fr conftest*\nfi\n\nfi\necho \"$ac_t\"\"$ac_cv_sizeof_int\" 1>&6\ncat >> confdefs.h <<EOF\n#define SIZEOF_INT $ac_cv_sizeof_int\nEOF\n\n\necho $ac_n \"checking size of long\"\"... $ac_c\" 1>&6\necho \"configure:1688: checking size of long\" >&5\nif eval \"test \\\"`echo '$''{'ac_cv_sizeof_long'+set}'`\\\" = set\"; then\n  echo $ac_n \"(cached) $ac_c\" 1>&6\nelse\n  if test \"$cross_compiling\" = yes; then\n    { echo \"configure: error: can not run test program while cross compiling\" 1>&2; exit 1; }\nelse\n  cat > conftest.$ac_ext <<EOF\n#line 1696 \"configure\"\n#include \"confdefs.h\"\n#include <stdio.h>\nmain()\n{\n  FILE *f=fopen(\"conftestval\", \"w\");\n  if (!f) exit(1);\n  fprintf(f, \"%d\\n\", sizeof(long));\n  exit(0);\n}\nEOF\nif { (eval echo configure:1707: \\\"$ac_link\\\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null\nthen\n  ac_cv_sizeof_long=`cat conftestval`\nelse\n  echo \"configure: failed program was:\" >&5\n  cat conftest.$ac_ext >&5\n  rm -fr conftest*\n  ac_cv_sizeof_long=0\nfi\nrm -fr conftest*\nfi\n\nfi\necho \"$ac_t\"\"$ac_cv_sizeof_long\" 1>&6\ncat >> confdefs.h <<EOF\n#define SIZEOF_LONG $ac_cv_sizeof_long\nEOF\n\n\necho $ac_n \"checking size of long long\"\"... $ac_c\" 1>&6\necho \"configure:1727: checking size of long long\" >&5\nif eval \"test \\\"`echo '$''{'ac_cv_sizeof_long_long'+set}'`\\\" = set\"; then\n  echo $ac_n \"(cached) $ac_c\" 1>&6\nelse\n  if test \"$cross_compiling\" = yes; then\n    { echo \"configure: error: can not run test program while cross compiling\" 1>&2; exit 1; }\nelse\n  cat > conftest.$ac_ext <<EOF\n#line 1735 \"configure\"\n#include \"confdefs.h\"\n#include <stdio.h>\nmain()\n{\n  FILE *f=fopen(\"conftestval\", \"w\");\n  if (!f) exit(1);\n  fprintf(f, \"%d\\n\", sizeof(long long));\n  exit(0);\n}\nEOF\nif { (eval echo configure:1746: \\\"$ac_link\\\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null\nthen\n  ac_cv_sizeof_long_long=`cat conftestval`\nelse\n  echo \"configure: failed program was:\" >&5\n  cat conftest.$ac_ext >&5\n  rm -fr conftest*\n  ac_cv_sizeof_long_long=0\nfi\nrm -fr conftest*\nfi\n\nfi\necho \"$ac_t\"\"$ac_cv_sizeof_long_long\" 1>&6\ncat >> confdefs.h <<EOF\n#define SIZEOF_LONG_LONG $ac_cv_sizeof_long_long\nEOF\n\n\ncat > conftest.$ac_ext <<EOF\n#line 1766 \"configure\"\n#include \"confdefs.h\"\n\nint main() {\nvolatile int i;\n; return 0; }\nEOF\nif { (eval echo configure:1773: \\\"$ac_compile\\\") 1>&5; (eval $ac_compile) 2>&5; }; then\n  :\nelse\n  echo \"configure: failed program was:\" >&5\n  cat conftest.$ac_ext >&5\n  rm -rf conftest*\n  cat >> confdefs.h <<\\EOF\n#define volatile \nEOF\n\nfi\nrm -f conftest*\necho $ac_n \"checking whether char is unsigned\"\"... $ac_c\" 1>&6\necho \"configure:1786: checking whether char is unsigned\" >&5\nif eval \"test \\\"`echo '$''{'ac_cv_c_char_unsigned'+set}'`\\\" = set\"; then\n  echo $ac_n \"(cached) $ac_c\" 1>&6\nelse\n  if test \"$GCC\" = yes; then\n  # GCC predefines this symbol on systems where it applies.\ncat > conftest.$ac_ext <<EOF\n#line 1793 \"configure\"\n#include \"confdefs.h\"\n#ifdef __CHAR_UNSIGNED__\n  yes\n#endif\n\nEOF\nif (eval \"$ac_cpp conftest.$ac_ext\") 2>&5 |\n  egrep \"yes\" >/dev/null 2>&1; then\n  rm -rf conftest*\n  ac_cv_c_char_unsigned=yes\nelse\n  rm -rf conftest*\n  ac_cv_c_char_unsigned=no\nfi\nrm -f conftest*\n\nelse\nif test \"$cross_compiling\" = yes; then\n    { echo \"configure: error: can not run test program while cross compiling\" 1>&2; exit 1; }\nelse\n  cat > conftest.$ac_ext <<EOF\n#line 1815 \"configure\"\n#include \"confdefs.h\"\n/* volatile prevents gcc2 from optimizing the test away on sparcs.  */\n#if !defined(__STDC__) || __STDC__ != 1\n#define volatile\n#endif\nmain() {\n  volatile char c = 255; exit(c < 0);\n}\nEOF\nif { (eval echo configure:1825: \\\"$ac_link\\\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null\nthen\n  ac_cv_c_char_unsigned=yes\nelse\n  echo \"configure: failed program was:\" >&5\n  cat conftest.$ac_ext >&5\n  rm -fr conftest*\n  ac_cv_c_char_unsigned=no\nfi\nrm -fr conftest*\nfi\n\nfi\nfi\n\necho \"$ac_t\"\"$ac_cv_c_char_unsigned\" 1>&6\nif test $ac_cv_c_char_unsigned = yes && test \"$GCC\" != yes; then\n  cat >> confdefs.h <<\\EOF\n#define __CHAR_UNSIGNED__ 1\nEOF\n\nfi\n\n\nif test \"$ac_cv_c_char_unsigned\" = \"yes\"; then\n  signed=-signed\nfi\n\n\nfor ac_func in sigaction strchr memcpy\ndo\necho $ac_n \"checking for $ac_func\"\"... $ac_c\" 1>&6\necho \"configure:1857: checking for $ac_func\" >&5\nif eval \"test \\\"`echo '$''{'ac_cv_func_$ac_func'+set}'`\\\" = set\"; then\n  echo $ac_n \"(cached) $ac_c\" 1>&6\nelse\n  cat > conftest.$ac_ext <<EOF\n#line 1862 \"configure\"\n#include \"confdefs.h\"\n/* System header to define __stub macros and hopefully few prototypes,\n    which can conflict with char $ac_func(); below.  */\n#include <assert.h>\n/* Override any gcc2 internal prototype to avoid an error.  */\n/* We use char because int might match the return type of a gcc2\n    builtin and then its argument prototype would still apply.  */\nchar $ac_func();\n\nint main() {\n\n/* The GNU C library defines this for functions which it implements\n    to always fail with ENOSYS.  Some functions are actually named\n    something starting with __ and the normal name is an alias.  */\n#if defined (__stub_$ac_func) || defined (__stub___$ac_func)\nchoke me\n#else\n$ac_func();\n#endif\n\n; return 0; }\nEOF\nif { (eval echo configure:1885: \\\"$ac_link\\\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then\n  rm -rf conftest*\n  eval \"ac_cv_func_$ac_func=yes\"\nelse\n  echo \"configure: failed program was:\" >&5\n  cat conftest.$ac_ext >&5\n  rm -rf conftest*\n  eval \"ac_cv_func_$ac_func=no\"\nfi\nrm -f conftest*\nfi\n\nif eval \"test \\\"`echo '$ac_cv_func_'$ac_func`\\\" = yes\"; then\n  echo \"$ac_t\"\"yes\" 1>&6\n    ac_tr_func=HAVE_`echo $ac_func | tr 'abcdefghijklmnopqrstuvwxyz' 'ABCDEFGHIJKLMNOPQRSTUVWXYZ'`\n  cat >> confdefs.h <<EOF\n#define $ac_tr_func 1\nEOF\n \nelse\n  echo \"$ac_t\"\"no\" 1>&6\nfi\ndone\n\n\necho $ac_n \"checking POSIX signal handlers\"\"... $ac_c\" 1>&6\necho \"configure:1911: checking POSIX signal handlers\" >&5\nif eval \"test \\\"`echo '$''{'ac_cv_has_posix_signals'+set}'`\\\" = set\"; then\n  echo $ac_n \"(cached) $ac_c\" 1>&6\nelse\n  cat > conftest.$ac_ext <<EOF\n#line 1916 \"configure\"\n#include \"confdefs.h\"\n#include <sys/types.h>\n#include <signal.h>\n#ifdef signal\n#undef signal\n#endif\nextern void (*signal ()) ();\nint main() {\n\n; return 0; }\nEOF\nif { (eval echo configure:1928: \\\"$ac_compile\\\") 1>&5; (eval $ac_compile) 2>&5; }; then\n  rm -rf conftest*\n  ac_cv_has_posix_signals=yes\nelse\n  echo \"configure: failed program was:\" >&5\n  cat conftest.$ac_ext >&5\n  rm -rf conftest*\n  ac_cv_has_posix_signals=no\nfi\nrm -f conftest*\nfi\n\necho \"$ac_t\"\"$ac_cv_has_posix_signals\" 1>&6\nif test $ac_cv_has_posix_signals = yes; then\n   cat >> confdefs.h <<\\EOF\n#define RETSIGTYPE void\nEOF\n cat >> confdefs.h <<\\EOF\n#define POSIX_SIGTYPE 1\nEOF\n\nelse\n  if test $ac_cv_type_signal = void; then\n     cat >> confdefs.h <<\\EOF\n#define RETSIGTYPE void\nEOF\n\n  else\n     cat >> confdefs.h <<\\EOF\n#define RETSIGTYPE int\nEOF\n\n  fi\nfi\nac_safe=`echo \"termios.h\" | sed 'y%./+-%__p_%'`\necho $ac_n \"checking for termios.h\"\"... $ac_c\" 1>&6\necho \"configure:1964: checking for termios.h\" >&5\nif eval \"test \\\"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\\\" = set\"; then\n  echo $ac_n \"(cached) $ac_c\" 1>&6\nelse\n  cat > conftest.$ac_ext <<EOF\n#line 1969 \"configure\"\n#include \"confdefs.h\"\n#include <termios.h>\nEOF\nac_try=\"$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out\"\n{ (eval echo configure:1974: \\\"$ac_try\\\") 1>&5; (eval $ac_try) 2>&5; }\nac_err=`grep -v '^ *+' conftest.out | grep -v \"^conftest.${ac_ext}\\$\"`\nif test -z \"$ac_err\"; then\n  rm -rf conftest*\n  eval \"ac_cv_header_$ac_safe=yes\"\nelse\n  echo \"$ac_err\" >&5\n  echo \"configure: failed program was:\" >&5\n  cat conftest.$ac_ext >&5\n  rm -rf conftest*\n  eval \"ac_cv_header_$ac_safe=no\"\nfi\nrm -f conftest*\nfi\nif eval \"test \\\"`echo '$ac_cv_header_'$ac_safe`\\\" = yes\"; then\n  echo \"$ac_t\"\"yes\" 1>&6\n  echo $ac_n \"checking for cfsetispeed\"\"... $ac_c\" 1>&6\necho \"configure:1991: checking for cfsetispeed\" >&5\nif eval \"test \\\"`echo '$''{'ac_cv_func_cfsetispeed'+set}'`\\\" = set\"; then\n  echo $ac_n \"(cached) $ac_c\" 1>&6\nelse\n  cat > conftest.$ac_ext <<EOF\n#line 1996 \"configure\"\n#include \"confdefs.h\"\n/* System header to define __stub macros and hopefully few prototypes,\n    which can conflict with char cfsetispeed(); below.  */\n#include <assert.h>\n/* Override any gcc2 internal prototype to avoid an error.  */\n/* We use char because int might match the return type of a gcc2\n    builtin and then its argument prototype would still apply.  */\nchar cfsetispeed();\n\nint main() {\n\n/* The GNU C library defines this for functions which it implements\n    to always fail with ENOSYS.  Some functions are actually named\n    something starting with __ and the normal name is an alias.  */\n#if defined (__stub_cfsetispeed) || defined (__stub___cfsetispeed)\nchoke me\n#else\ncfsetispeed();\n#endif\n\n; return 0; }\nEOF\nif { (eval echo configure:2019: \\\"$ac_link\\\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then\n  rm -rf conftest*\n  eval \"ac_cv_func_cfsetispeed=yes\"\nelse\n  echo \"configure: failed program was:\" >&5\n  cat conftest.$ac_ext >&5\n  rm -rf conftest*\n  eval \"ac_cv_func_cfsetispeed=no\"\nfi\nrm -f conftest*\nfi\n\nif eval \"test \\\"`echo '$ac_cv_func_'cfsetispeed`\\\" = yes\"; then\n  echo \"$ac_t\"\"yes\" 1>&6\n  cat >> confdefs.h <<\\EOF\n#define POSIX_TERMIOS 1\nEOF\n\nelse\n  echo \"$ac_t\"\"no\" 1>&6\nfi\n\nelse\n  echo \"$ac_t\"\"no\" 1>&6\nfi\n\n\n\n\ncat >> confdefs.h <<\\EOF\n#define SHA1HANDSOFF 1\nEOF\n\n\ntrap '' 1 2 15\ncat > confcache <<\\EOF\n# This file is a shell script that caches the results of configure\n# tests run on this system so they can be shared between configure\n# scripts and configure runs.  It is not useful on other systems.\n# If it contains results you don't want to keep, you may remove or edit it.\n#\n# By default, configure uses ./config.cache as the cache file,\n# creating it if it does not exist already.  You can give configure\n# the --cache-file=FILE option to use a different cache file; that is\n# what configure does when it calls configure scripts in\n# subdirectories, so they share the cache.\n# Giving --cache-file=/dev/null disables caching, for debugging configure.\n# config.status only pays attention to the cache file if you give it the\n# --recheck option to rerun configure.\n#\nEOF\n# The following way of writing the cache mishandles newlines in values,\n# but we know of no workaround that is simple, portable, and efficient.\n# So, don't put newlines in cache variables' values.\n# Ultrix sh set writes to stderr and can't be redirected directly,\n# and sets the high bit in the cache file unless we assign to the vars.\n(set) 2>&1 |\n  case `(ac_space=' '; set | grep ac_space) 2>&1` in\n  *ac_space=\\ *)\n    # `set' does not quote correctly, so add quotes (double-quote substitution\n    # turns \\\\\\\\ into \\\\, and sed turns \\\\ into \\).\n    sed -n \\\n      -e \"s/'/'\\\\\\\\''/g\" \\\n      -e \"s/^\\\\([a-zA-Z0-9_]*_cv_[a-zA-Z0-9_]*\\\\)=\\\\(.*\\\\)/\\\\1=\\${\\\\1='\\\\2'}/p\"\n    ;;\n  *)\n    # `set' quotes correctly as required by POSIX, so do not add quotes.\n    sed -n -e 's/^\\([a-zA-Z0-9_]*_cv_[a-zA-Z0-9_]*\\)=\\(.*\\)/\\1=${\\1=\\2}/p'\n    ;;\n  esac >> confcache\nif cmp -s $cache_file confcache; then\n  :\nelse\n  if test -w $cache_file; then\n    echo \"updating cache $cache_file\"\n    cat confcache > $cache_file\n  else\n    echo \"not updating unwritable cache $cache_file\"\n  fi\nfi\nrm -f confcache\n\ntrap 'rm -fr conftest* confdefs* core core.* *.core $ac_clean_files; exit 1' 1 2 15\n\ntest \"x$prefix\" = xNONE && prefix=$ac_default_prefix\n# Let make expand exec_prefix.\ntest \"x$exec_prefix\" = xNONE && exec_prefix='${prefix}'\n\n# Any assignment to VPATH causes Sun make to only execute\n# the first set of double-colon rules, so remove it if not needed.\n# If there is a colon in the path, we need to keep it.\nif test \"x$srcdir\" = x.; then\n  ac_vpsub='/^[ \t]*VPATH[ \t]*=[^:]*$/d'\nfi\n\ntrap 'rm -f $CONFIG_STATUS conftest*; exit 1' 1 2 15\n\nDEFS=-DHAVE_CONFIG_H\n\n# Without the \"./\", some shells look in PATH for config.status.\n: ${CONFIG_STATUS=./config.status}\n\necho creating $CONFIG_STATUS\nrm -f $CONFIG_STATUS\ncat > $CONFIG_STATUS <<EOF\n#! /bin/sh\n# Generated automatically by configure.\n# Run this file to recreate the current configuration.\n# This directory was configured as follows,\n# on host `(hostname || uname -n) 2>/dev/null | sed 1q`:\n#\n# $0 $ac_configure_args\n#\n# Compiler output produced by configure, useful for debugging\n# configure, is in ./config.log if it exists.\n\nac_cs_usage=\"Usage: $CONFIG_STATUS [--recheck] [--version] [--help]\"\nfor ac_option\ndo\n  case \"\\$ac_option\" in\n  -recheck | --recheck | --rechec | --reche | --rech | --rec | --re | --r)\n    echo \"running \\${CONFIG_SHELL-/bin/sh} $0 $ac_configure_args --no-create --no-recursion\"\n    exec \\${CONFIG_SHELL-/bin/sh} $0 $ac_configure_args --no-create --no-recursion ;;\n  -version | --version | --versio | --versi | --vers | --ver | --ve | --v)\n    echo \"$CONFIG_STATUS generated by autoconf version 2.13\"\n    exit 0 ;;\n  -help | --help | --hel | --he | --h)\n    echo \"\\$ac_cs_usage\"; exit 0 ;;\n  *) echo \"\\$ac_cs_usage\"; exit 1 ;;\n  esac\ndone\n\nac_given_srcdir=$srcdir\nac_given_INSTALL=\"$INSTALL\"\n\ntrap 'rm -fr `echo \"Makefile config.h\" | sed \"s/:[^ ]*//g\"` conftest*; exit 1' 1 2 15\nEOF\ncat >> $CONFIG_STATUS <<EOF\n\n# Protect against being on the right side of a sed subst in config.status.\nsed 's/%@/@@/; s/@%/@@/; s/%g\\$/@g/; /@g\\$/s/[\\\\\\\\&%]/\\\\\\\\&/g;\n s/@@/%@/; s/@@/@%/; s/@g\\$/%g/' > conftest.subs <<\\\\CEOF\n$ac_vpsub\n$extrasub\ns%@SHELL@%$SHELL%g\ns%@CFLAGS@%$CFLAGS%g\ns%@CPPFLAGS@%$CPPFLAGS%g\ns%@CXXFLAGS@%$CXXFLAGS%g\ns%@FFLAGS@%$FFLAGS%g\ns%@DEFS@%$DEFS%g\ns%@LDFLAGS@%$LDFLAGS%g\ns%@LIBS@%$LIBS%g\ns%@exec_prefix@%$exec_prefix%g\ns%@prefix@%$prefix%g\ns%@program_transform_name@%$program_transform_name%g\ns%@bindir@%$bindir%g\ns%@sbindir@%$sbindir%g\ns%@libexecdir@%$libexecdir%g\ns%@datadir@%$datadir%g\ns%@sysconfdir@%$sysconfdir%g\ns%@sharedstatedir@%$sharedstatedir%g\ns%@localstatedir@%$localstatedir%g\ns%@libdir@%$libdir%g\ns%@includedir@%$includedir%g\ns%@oldincludedir@%$oldincludedir%g\ns%@infodir@%$infodir%g\ns%@mandir@%$mandir%g\ns%@INSTALL_PROGRAM@%$INSTALL_PROGRAM%g\ns%@INSTALL_SCRIPT@%$INSTALL_SCRIPT%g\ns%@INSTALL_DATA@%$INSTALL_DATA%g\ns%@PACKAGE@%$PACKAGE%g\ns%@VERSION@%$VERSION%g\ns%@ACLOCAL@%$ACLOCAL%g\ns%@AUTOCONF@%$AUTOCONF%g\ns%@AUTOMAKE@%$AUTOMAKE%g\ns%@AUTOHEADER@%$AUTOHEADER%g\ns%@MAKEINFO@%$MAKEINFO%g\ns%@SET_MAKE@%$SET_MAKE%g\ns%@CC@%$CC%g\ns%@LN_S@%$LN_S%g\ns%@RANLIB@%$RANLIB%g\ns%@CPP@%$CPP%g\ns%@signed@%$signed%g\n\nCEOF\nEOF\n\ncat >> $CONFIG_STATUS <<\\EOF\n\n# Split the substitutions into bite-sized pieces for seds with\n# small command number limits, like on Digital OSF/1 and HP-UX.\nac_max_sed_cmds=90 # Maximum number of lines to put in a sed script.\nac_file=1 # Number of current file.\nac_beg=1 # First line for current file.\nac_end=$ac_max_sed_cmds # Line after last line for current file.\nac_more_lines=:\nac_sed_cmds=\"\"\nwhile $ac_more_lines; do\n  if test $ac_beg -gt 1; then\n    sed \"1,${ac_beg}d; ${ac_end}q\" conftest.subs > conftest.s$ac_file\n  else\n    sed \"${ac_end}q\" conftest.subs > conftest.s$ac_file\n  fi\n  if test ! -s conftest.s$ac_file; then\n    ac_more_lines=false\n    rm -f conftest.s$ac_file\n  else\n    if test -z \"$ac_sed_cmds\"; then\n      ac_sed_cmds=\"sed -f conftest.s$ac_file\"\n    else\n      ac_sed_cmds=\"$ac_sed_cmds | sed -f conftest.s$ac_file\"\n    fi\n    ac_file=`expr $ac_file + 1`\n    ac_beg=$ac_end\n    ac_end=`expr $ac_end + $ac_max_sed_cmds`\n  fi\ndone\nif test -z \"$ac_sed_cmds\"; then\n  ac_sed_cmds=cat\nfi\nEOF\n\ncat >> $CONFIG_STATUS <<EOF\n\nCONFIG_FILES=\\${CONFIG_FILES-\"Makefile\"}\nEOF\ncat >> $CONFIG_STATUS <<\\EOF\nfor ac_file in .. $CONFIG_FILES; do if test \"x$ac_file\" != x..; then\n  # Support \"outfile[:infile[:infile...]]\", defaulting infile=\"outfile.in\".\n  case \"$ac_file\" in\n  *:*) ac_file_in=`echo \"$ac_file\"|sed 's%[^:]*:%%'`\n       ac_file=`echo \"$ac_file\"|sed 's%:.*%%'` ;;\n  *) ac_file_in=\"${ac_file}.in\" ;;\n  esac\n\n  # Adjust a relative srcdir, top_srcdir, and INSTALL for subdirectories.\n\n  # Remove last slash and all that follows it.  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And first:\n# Protect against being on the right side of a sed subst in config.status.\n# Protect against being in an unquoted here document in config.status.\nrm -f conftest.vals\ncat > conftest.hdr <<\\EOF\ns/[\\\\&%]/\\\\&/g\ns%[\\\\$`]%\\\\&%g\ns%#define \\([A-Za-z_][A-Za-z0-9_]*\\) *\\(.*\\)%${ac_dA}\\1${ac_dB}\\1${ac_dC}\\2${ac_dD}%gp\ns%ac_d%ac_u%gp\ns%ac_u%ac_e%gp\nEOF\nsed -n -f conftest.hdr confdefs.h > conftest.vals\nrm -f conftest.hdr\n\n# This sed command replaces #undef with comments.  This is necessary, for\n# example, in the case of _POSIX_SOURCE, which is predefined and required\n# on some systems where configure will not decide to define it.\ncat >> conftest.vals <<\\EOF\ns%^[ \t]*#[ \t]*undef[ \t][ \t]*[a-zA-Z_][a-zA-Z_0-9]*%/* & */%\nEOF\n\n# Break up conftest.vals because some shells have a limit on\n# the size of here documents, and old seds have small limits too.\n\nrm -f conftest.tail\nwhile :\ndo\n  ac_lines=`grep -c . conftest.vals`\n  # grep -c gives empty output for an empty file on some AIX systems.\n  if test -z \"$ac_lines\" || test \"$ac_lines\" -eq 0; then break; fi\n  # Write a limited-size here document to conftest.frag.\n  echo '  cat > conftest.frag <<CEOF' >> $CONFIG_STATUS\n  sed ${ac_max_here_lines}q conftest.vals >> $CONFIG_STATUS\n  echo 'CEOF\n  sed -f conftest.frag conftest.in > conftest.out\n  rm -f conftest.in\n  mv conftest.out conftest.in\n' >> $CONFIG_STATUS\n  sed 1,${ac_max_here_lines}d conftest.vals > conftest.tail\n  rm -f conftest.vals\n  mv conftest.tail conftest.vals\ndone\nrm -f conftest.vals\n\ncat >> $CONFIG_STATUS <<\\EOF\n  rm -f conftest.frag conftest.h\n  echo \"/* $ac_file.  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  },
  {
    "path": "package/network/services/ead/src/tinysrp/configure.in",
    "content": "dnl Process this file with autoconf to produce a configure script.\n\nAC_INIT(t_pwd.h)\nAM_CONFIG_HEADER(config.h)\nAM_INIT_AUTOMAKE(libtinysrp, 0.7.5)\n\ntest \"$CFLAGS\" = \"\" && CFLAGS=\"-O2\"\n\ndnl Checks for programs.\n\nAC_PROG_CC\nAC_PROG_INSTALL\nAC_PROG_LN_S\nAC_PROG_RANLIB\nAC_ARG_PROGRAM\n\ndnl Checks for header files.\n\nAC_HEADER_STDC\nAC_CHECK_HEADERS(sgtty.h sys/ioctl.h sys/time.h termio.h termios.h unistd.h)\n\ndnl Checks for typedefs, structures, and compiler characteristics.\n\nAC_C_CONST\nAC_C_INLINE\nAC_HEADER_TIME\nAC_C_BIGENDIAN\nAC_CHECK_SIZEOF(short)\nAC_CHECK_SIZEOF(int)\nAC_CHECK_SIZEOF(long)\nAC_CHECK_SIZEOF(long long)\nAC_TRY_COMPILE(, [volatile int i;], , AC_DEFINE(volatile, ))\nAC_C_CHAR_UNSIGNED\n\nAC_SUBST(signed)dnl\nif test \"$ac_cv_c_char_unsigned\" = \"yes\"; then\n  signed=-signed\nfi\n\ndnl Checks for library functions.\n\nAC_CHECK_FUNCS(sigaction strchr memcpy)\nTYPE_SIGNAL\nAC_HEADER_CHECK(termios.h,AC_FUNC_CHECK(cfsetispeed,AC_DEFINE(POSIX_TERMIOS)))\n\ndnl User options\n\ndnl Some defines for now.\n\nAC_DEFINE(SHA1HANDSOFF)\n\nAC_OUTPUT(Makefile)\n"
  },
  {
    "path": "package/network/services/ead/src/tinysrp/install-sh",
    "content": "#!/bin/sh\n#\n# install - install a program, script, or datafile\n# This comes from X11R5 (mit/util/scripts/install.sh).\n#\n# Copyright 1991 by the Massachusetts Institute of Technology\n#\n# Permission to use, copy, modify, distribute, and sell this software and its\n# documentation for any purpose is hereby granted without fee, provided that\n# the above copyright notice appear in all copies and that both that\n# copyright notice and this permission notice appear in supporting\n# documentation, and that the name of M.I.T. not be used in advertising or\n# publicity pertaining to distribution of the software without specific,\n# written prior permission.  M.I.T. makes no representations about the\n# suitability of this software for any purpose.  It is provided \"as is\"\n# without express or implied warranty.\n#\n# Calling this script install-sh is preferred over install.sh, to prevent\n# `make' implicit rules from creating a file called install from it\n# when there is no Makefile.\n#\n# This script is compatible with the BSD install script, but was written\n# from scratch.  It can only install one file at a time, a restriction\n# shared with many OS's install programs.\n\n\n# set DOITPROG to echo to test this script\n\n# Don't use :- since 4.3BSD and earlier shells don't like it.\ndoit=\"${DOITPROG-}\"\n\n\n# put in absolute paths if you don't have them in your path; or use env. vars.\n\nmvprog=\"${MVPROG-mv}\"\ncpprog=\"${CPPROG-cp}\"\nchmodprog=\"${CHMODPROG-chmod}\"\nchownprog=\"${CHOWNPROG-chown}\"\nchgrpprog=\"${CHGRPPROG-chgrp}\"\nstripprog=\"${STRIPPROG-strip}\"\nrmprog=\"${RMPROG-rm}\"\nmkdirprog=\"${MKDIRPROG-mkdir}\"\n\ntransformbasename=\"\"\ntransform_arg=\"\"\ninstcmd=\"$mvprog\"\nchmodcmd=\"$chmodprog 0755\"\nchowncmd=\"\"\nchgrpcmd=\"\"\nstripcmd=\"\"\nrmcmd=\"$rmprog -f\"\nmvcmd=\"$mvprog\"\nsrc=\"\"\ndst=\"\"\ndir_arg=\"\"\n\nwhile [ x\"$1\" != x ]; do\n    case $1 in\n\t-c) instcmd=\"$cpprog\"\n\t    shift\n\t    continue;;\n\n\t-d) dir_arg=true\n\t    shift\n\t    continue;;\n\n\t-m) chmodcmd=\"$chmodprog $2\"\n\t    shift\n\t    shift\n\t    continue;;\n\n\t-o) chowncmd=\"$chownprog $2\"\n\t    shift\n\t    shift\n\t    continue;;\n\n\t-g) chgrpcmd=\"$chgrpprog $2\"\n\t    shift\n\t    shift\n\t    continue;;\n\n\t-s) stripcmd=\"$stripprog\"\n\t    shift\n\t    continue;;\n\n\t-t=*) transformarg=`echo $1 | sed 's/-t=//'`\n\t    shift\n\t    continue;;\n\n\t-b=*) transformbasename=`echo $1 | sed 's/-b=//'`\n\t    shift\n\t    continue;;\n\n\t*)  if [ x\"$src\" = x ]\n\t    then\n\t\tsrc=$1\n\t    else\n\t\t# this colon is to work around a 386BSD /bin/sh bug\n\t\t:\n\t\tdst=$1\n\t    fi\n\t    shift\n\t    continue;;\n    esac\ndone\n\nif [ x\"$src\" = x ]\nthen\n\techo \"install:\tno input file specified\"\n\texit 1\nelse\n\ttrue\nfi\n\nif [ x\"$dir_arg\" != x ]; then\n\tdst=$src\n\tsrc=\"\"\n\t\n\tif [ -d $dst ]; then\n\t\tinstcmd=:\n\telse\n\t\tinstcmd=mkdir\n\tfi\nelse\n\n# Waiting for this to be detected by the \"$instcmd $src $dsttmp\" command\n# might cause directories to be created, which would be especially bad \n# if $src (and thus $dsttmp) contains '*'.\n\n\tif [ -f $src -o -d $src ]\n\tthen\n\t\ttrue\n\telse\n\t\techo \"install:  $src does not exist\"\n\t\texit 1\n\tfi\n\t\n\tif [ x\"$dst\" = x ]\n\tthen\n\t\techo \"install:\tno destination specified\"\n\t\texit 1\n\telse\n\t\ttrue\n\tfi\n\n# If destination is a directory, append the input filename; if your system\n# does not like double slashes in filenames, you may need to add some logic\n\n\tif [ -d $dst ]\n\tthen\n\t\tdst=\"$dst\"/`basename $src`\n\telse\n\t\ttrue\n\tfi\nfi\n\n## this sed command emulates the dirname command\ndstdir=`echo $dst | sed -e 's,[^/]*$,,;s,/$,,;s,^$,.,'`\n\n# Make sure that the destination directory exists.\n#  this part is taken from Noah Friedman's mkinstalldirs script\n\n# Skip lots of stat calls in the usual case.\nif [ ! -d \"$dstdir\" ]; then\ndefaultIFS='\t\n'\nIFS=\"${IFS-${defaultIFS}}\"\n\noIFS=\"${IFS}\"\n# Some sh's can't handle IFS=/ for some reason.\nIFS='%'\nset - `echo ${dstdir} | sed -e 's@/@%@g' -e 's@^%@/@'`\nIFS=\"${oIFS}\"\n\npathcomp=''\n\nwhile [ $# -ne 0 ] ; do\n\tpathcomp=\"${pathcomp}${1}\"\n\tshift\n\n\tif [ ! -d \"${pathcomp}\" ] ;\n        then\n\t\t$mkdirprog \"${pathcomp}\"\n\telse\n\t\ttrue\n\tfi\n\n\tpathcomp=\"${pathcomp}/\"\ndone\nfi\n\nif [ x\"$dir_arg\" != x ]\nthen\n\t$doit $instcmd $dst &&\n\n\tif [ x\"$chowncmd\" != x ]; then $doit $chowncmd $dst; else true ; fi &&\n\tif [ x\"$chgrpcmd\" != x ]; then $doit $chgrpcmd $dst; else true ; fi &&\n\tif [ x\"$stripcmd\" != x ]; then $doit $stripcmd $dst; else true ; fi &&\n\tif [ x\"$chmodcmd\" != x ]; then $doit $chmodcmd $dst; else true ; fi\nelse\n\n# If we're going to rename the final executable, determine the name now.\n\n\tif [ x\"$transformarg\" = x ] \n\tthen\n\t\tdstfile=`basename $dst`\n\telse\n\t\tdstfile=`basename $dst $transformbasename | \n\t\t\tsed $transformarg`$transformbasename\n\tfi\n\n# don't allow the sed command to completely eliminate the filename\n\n\tif [ x\"$dstfile\" = x ] \n\tthen\n\t\tdstfile=`basename $dst`\n\telse\n\t\ttrue\n\tfi\n\n# Make a temp file name in the proper directory.\n\n\tdsttmp=$dstdir/#inst.$$#\n\n# Move or copy the file name to the temp name\n\n\t$doit $instcmd $src $dsttmp &&\n\n\ttrap \"rm -f ${dsttmp}\" 0 &&\n\n# and set any options; do chmod last to preserve setuid bits\n\n# If any of these fail, we abort the whole thing.  If we want to\n# ignore errors from any of these, just make sure not to ignore\n# errors from the above \"$doit $instcmd $src $dsttmp\" command.\n\n\tif [ x\"$chowncmd\" != x ]; then $doit $chowncmd $dsttmp; else true;fi &&\n\tif [ x\"$chgrpcmd\" != x ]; then $doit $chgrpcmd $dsttmp; else true;fi &&\n\tif [ x\"$stripcmd\" != x ]; then $doit $stripcmd $dsttmp; else true;fi &&\n\tif [ x\"$chmodcmd\" != x ]; then $doit $chmodcmd $dsttmp; else true;fi &&\n\n# Now rename the file to the real destination.\n\n\t$doit $rmcmd -f $dstdir/$dstfile &&\n\t$doit $mvcmd $dsttmp $dstdir/$dstfile \n\nfi &&\n\n\nexit 0\n"
  },
  {
    "path": "package/network/services/ead/src/tinysrp/missing",
    "content": "#! /bin/sh\n# Common stub for a few missing GNU programs while installing.\n# Copyright (C) 1996, 1997 Free Software Foundation, Inc.\n# Franc,ois Pinard <pinard@iro.umontreal.ca>, 1996.\n\n# This program is free software; you can redistribute it and/or modify\n# it under the terms of the GNU General Public License as published by\n# the Free Software Foundation; either version 2, or (at your option)\n# any later version.\n\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n# GNU General Public License for more details.\n\n# You should have received a copy of the GNU General Public License\n# along with this program; if not, write to the Free Software\n# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA\n# 02111-1307, USA.\n\nif test $# -eq 0; then\n  echo 1>&2 \"Try \\`$0 --help' for more information\"\n  exit 1\nfi\n\ncase \"$1\" in\n\n  -h|--h|--he|--hel|--help)\n    echo \"\\\n$0 [OPTION]... PROGRAM [ARGUMENT]...\n\nHandle \\`PROGRAM [ARGUMENT]...' for when PROGRAM is missing, or return an\nerror status if there is no known handling for PROGRAM.\n\nOptions:\n  -h, --help      display this help and exit\n  -v, --version   output version information and exit\n\nSupported PROGRAM values:\n  aclocal      touch file \\`aclocal.m4'\n  autoconf     touch file \\`configure'\n  autoheader   touch file \\`config.h.in'\n  automake     touch all \\`Makefile.in' files\n  bison        touch file \\`y.tab.c'\n  makeinfo     touch the output file\n  yacc         touch file \\`y.tab.c'\"\n    ;;\n\n  -v|--v|--ve|--ver|--vers|--versi|--versio|--version)\n    echo \"missing - GNU libit 0.0\"\n    ;;\n\n  -*)\n    echo 1>&2 \"$0: Unknown \\`$1' option\"\n    echo 1>&2 \"Try \\`$0 --help' for more information\"\n    exit 1\n    ;;\n\n  aclocal)\n    echo 1>&2 \"\\\nWARNING: \\`$1' is missing on your system.  You should only need it if\n         you modified \\`acinclude.m4' or \\`configure.in'.  You might want\n         to install the \\`Automake' and \\`Perl' packages.  Grab them from\n         any GNU archive site.\"\n    touch aclocal.m4\n    ;;\n\n  autoconf)\n    echo 1>&2 \"\\\nWARNING: \\`$1' is missing on your system.  You should only need it if\n         you modified \\`configure.in'.  You might want to install the\n         \\`Autoconf' and \\`GNU m4' packages.  Grab them from any GNU\n         archive site.\"\n    touch configure\n    ;;\n\n  autoheader)\n    echo 1>&2 \"\\\nWARNING: \\`$1' is missing on your system.  You should only need it if\n         you modified \\`acconfig.h' or \\`configure.in'.  You might want\n         to install the \\`Autoconf' and \\`GNU m4' packages.  Grab them\n         from any GNU archive site.\"\n    touch config.h.in\n    ;;\n\n  automake)\n    echo 1>&2 \"\\\nWARNING: \\`$1' is missing on your system.  You should only need it if\n         you modified \\`Makefile.am', \\`acinclude.m4' or \\`configure.in'.\n         You might want to install the \\`Automake' and \\`Perl' packages.\n         Grab them from any GNU archive site.\"\n    find . -type f -name Makefile.am -print \\\n      | sed 's/^\\(.*\\).am$/touch \\1.in/' \\\n      | sh\n    ;;\n\n  bison|yacc)\n    echo 1>&2 \"\\\nWARNING: \\`$1' is missing on your system.  You should only need it if\n         you modified a \\`.y' file.  You may need the \\`Bison' package\n         in order for those modifications to take effect.  You can get\n         \\`Bison' from any GNU archive site.\"\n    touch y.tab.c\n    ;;\n\n  makeinfo)\n    echo 1>&2 \"\\\nWARNING: \\`$1' is missing on your system.  You should only need it if\n         you modified a \\`.texi' or \\`.texinfo' file, or any other file\n         indirectly affecting the aspect of the manual.  The spurious\n         call might also be the consequence of using a buggy \\`make' (AIX,\n         DU, IRIX).  You might want to install the \\`Texinfo' package or\n         the \\`GNU make' package.  Grab either from any GNU archive site.\"\n    file=`echo \"$*\" | sed -n 's/.*-o \\([^ ]*\\).*/\\1/p'`\n    if test -z \"$file\"; then\n      file=`echo \"$*\" | sed 's/.* \\([^ ]*\\) *$/\\1/'`\n      file=`sed -n '/^@setfilename/ { s/.* \\([^ ]*\\) *$/\\1/; p; q; }' $file`\n    fi\n    touch $file\n    ;;\n\n  *)\n    echo 1>&2 \"\\\nWARNING: \\`$1' is needed, and you do not seem to have it handy on your\n         system.  You might have modified some files without having the\n         proper tools for further handling them.  Check the \\`README' file,\n         it often tells you about the needed prerequirements for installing\n         this package.  You may also peek at any GNU archive site, in case\n         some other package would contain this missing \\`$1' program.\"\n    exit 1\n    ;;\nesac\n\nexit 0\n"
  },
  {
    "path": "package/network/services/ead/src/tinysrp/mkinstalldirs",
    "content": "#! /bin/sh\n# mkinstalldirs --- make directory hierarchy\n# Author: Noah Friedman <friedman@prep.ai.mit.edu>\n# Created: 1993-05-16\n# Public domain\n\n\nerrstatus=0\n\nfor file\ndo\n   set fnord `echo \":$file\" | sed -ne 's/^:\\//#/;s/^://;s/\\// /g;s/^#/\\//;p'`\n   shift\n\n   pathcomp=\n   for d\n   do\n     pathcomp=\"$pathcomp$d\"\n     case \"$pathcomp\" in\n       -* ) pathcomp=./$pathcomp ;;\n     esac\n\n     if test ! -d \"$pathcomp\"; then\n        echo \"mkdir $pathcomp\" 1>&2\n\n        mkdir \"$pathcomp\" || lasterr=$?\n\n        if test ! -d \"$pathcomp\"; then\n  \t  errstatus=$lasterr\n        fi\n     fi\n\n     pathcomp=\"$pathcomp/\"\n   done\ndone\n\nexit $errstatus\n\n# mkinstalldirs ends here\n"
  },
  {
    "path": "package/network/services/ead/src/tinysrp/srvtest.c",
    "content": "/*\n * Copyright (c) 1997-1999  The Stanford SRP Authentication Project\n * All Rights Reserved.\n *\n * Permission is hereby granted, free of charge, to any person obtaining\n * a copy of this software and associated documentation files (the\n * \"Software\"), to deal in the Software without restriction, including\n * without limitation the rights to use, copy, modify, merge, publish,\n * distribute, sublicense, and/or sell copies of the Software, and to\n * permit persons to whom the Software is furnished to do so, subject to\n * the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS-IS\" AND WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS, IMPLIED OR OTHERWISE, INCLUDING WITHOUT LIMITATION, ANY\n * WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.\n *\n * IN NO EVENT SHALL STANFORD BE LIABLE FOR ANY SPECIAL, INCIDENTAL,\n * INDIRECT OR CONSEQUENTIAL DAMAGES OF ANY KIND, OR ANY DAMAGES WHATSOEVER\n * RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER OR NOT ADVISED OF\n * THE POSSIBILITY OF DAMAGE, AND ON ANY THEORY OF LIABILITY, ARISING OUT\n * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n * In addition, the following conditions apply:\n *\n * 1. Any software that incorporates the SRP authentication technology\n *    must display the following acknowlegment:\n *    \"This product uses the 'Secure Remote Password' cryptographic\n *     authentication system developed by Tom Wu (tjw@CS.Stanford.EDU).\"\n *\n * 2. Any software that incorporates all or part of the SRP distribution\n *    itself must also display the following acknowledgment:\n *    \"This product includes software developed by Tom Wu and Eugene\n *     Jhong for the SRP Distribution (http://srp.stanford.edu/srp/).\"\n *\n * 3. Redistributions in source or binary form must retain an intact copy\n *    of this copyright notice and list of conditions.\n */\n\n#include <stdio.h>\n#include \"t_defines.h\"\n#include \"t_pwd.h\"\n#include \"t_server.h\"\n\nint\nmain(argc, argv)\n     int argc;\n     char * argv[];\n{\n  struct t_server * ts;\n  struct t_pw * tpw;\n  struct t_conf * tcnf;\n  struct t_num * B;\n  char username[MAXUSERLEN];\n  char hexbuf[MAXHEXPARAMLEN];\n  char buf[MAXPARAMLEN];\n  struct t_num A;\n  unsigned char * skey;\n  unsigned char cbuf[20];\n  FILE * fp;\n  FILE * fp2;\n  char confname[256];\n\n  printf(\"Enter username: \");\n  fgets(username, sizeof(username), stdin);\n  username[strlen(username) - 1] = '\\0';\n  ts = t_serveropen(username);\n\n  if(ts == NULL) {\n    fprintf(stderr, \"User %s not found\\n\", username);\n    exit(1);\n  }\n\n#if 0\n  printf(\"n: %s\\n\", t_tob64(hexbuf, ts->n.data, ts->n.len));\n  printf(\"g: %s\\n\", t_tob64(hexbuf, ts->g.data, ts->g.len));\n#endif\n  printf(\"index (to client): %d\\n\", ts->index);\n  printf(\"salt (to client): %s\\n\", t_tob64(hexbuf, ts->s.data, ts->s.len));\n\n  B = t_servergenexp(ts);\n  printf(\"Enter A (from client): \");\n  fgets(hexbuf, sizeof(hexbuf), stdin);\n  A.data = buf;\n  A.len = t_fromb64(A.data, hexbuf);\n\n  printf(\"B (to client): %s\\n\", t_tob64(hexbuf, B->data, B->len));\n\n  skey = t_servergetkey(ts, &A);\n  printf(\"Session key: %s\\n\", t_tohex(hexbuf, skey, 40));\n\n  /* printf(\"[Expected response: %s]\\n\", t_tohex(hexbuf, cbuf, 16)); */\n\n  printf(\"Enter response (from client): \");\n  fgets(hexbuf, sizeof(hexbuf), stdin);\n  hexbuf[strlen(hexbuf) - 1] = '\\0';\n  t_fromhex(cbuf, hexbuf);\n\n  if(t_serververify(ts, cbuf) == 0) {\n    printf(\"Authentication successful.\\n\");\n    printf(\"Response (to client): %s\\n\",\n      t_tohex(hexbuf, t_serverresponse(ts), RESPONSE_LEN));\n  } else\n    printf(\"Authentication failed.\\n\");\n\n  t_serverclose(ts);\n\n  return 0;\n}\n"
  },
  {
    "path": "package/network/services/ead/src/tinysrp/stamp-h.in",
    "content": "timestamp\n"
  },
  {
    "path": "package/network/services/ead/src/tinysrp/t_client.c",
    "content": "/*\n * Copyright (c) 1997-1999  The Stanford SRP Authentication Project\n * All Rights Reserved.\n *\n * Permission is hereby granted, free of charge, to any person obtaining\n * a copy of this software and associated documentation files (the\n * \"Software\"), to deal in the Software without restriction, including\n * without limitation the rights to use, copy, modify, merge, publish,\n * distribute, sublicense, and/or sell copies of the Software, and to\n * permit persons to whom the Software is furnished to do so, subject to\n * the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS-IS\" AND WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS, IMPLIED OR OTHERWISE, INCLUDING WITHOUT LIMITATION, ANY\n * WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.\n *\n * IN NO EVENT SHALL STANFORD BE LIABLE FOR ANY SPECIAL, INCIDENTAL,\n * INDIRECT OR CONSEQUENTIAL DAMAGES OF ANY KIND, OR ANY DAMAGES WHATSOEVER\n * RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER OR NOT ADVISED OF\n * THE POSSIBILITY OF DAMAGE, AND ON ANY THEORY OF LIABILITY, ARISING OUT\n * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n * In addition, the following conditions apply:\n *\n * 1. Any software that incorporates the SRP authentication technology\n *    must display the following acknowlegment:\n *    \"This product uses the 'Secure Remote Password' cryptographic\n *     authentication system developed by Tom Wu (tjw@CS.Stanford.EDU).\"\n *\n * 2. Any software that incorporates all or part of the SRP distribution\n *    itself must also display the following acknowledgment:\n *    \"This product includes software developed by Tom Wu and Eugene\n *     Jhong for the SRP Distribution (http://srp.stanford.edu/srp/).\"\n *\n * 3. Redistributions in source or binary form must retain an intact copy\n *    of this copyright notice and list of conditions.\n */\n\n#include <stdio.h>\n#include \"t_defines.h\"\n#include \"t_pwd.h\"\n#include \"t_client.h\"\n#include \"t_sha.h\"\n\n_TYPE( struct t_client * )\nt_clientopen(u, n, g, s)\n     const char * u;\n     struct t_num * n;\n     struct t_num * g;\n     struct t_num * s;\n{\n  struct t_client * tc;\n  unsigned char buf1[SHA_DIGESTSIZE], buf2[SHA_DIGESTSIZE];\n  SHA1_CTX ctxt;\n  int i, validated;\n  struct t_preconf * tpc;\n\n  validated = 0;\n  if(n->len < MIN_MOD_BYTES)\n    return 0;\n  for(i = 0; i < t_getprecount(); ++i) {\n    tpc = t_getpreparam(i);\n    if(tpc->modulus.len == n->len && tpc->generator.len == g->len &&\n       memcmp(tpc->modulus.data, n->data, n->len) == 0 &&\n       memcmp(tpc->generator.data, g->data, g->len) == 0) {\n      validated = 1;    /* Match found, done */\n      break;\n    }\n  }\n\n  if(validated == 0)\n    return 0;\n\n  if((tc = malloc(sizeof(struct t_client))) == 0)\n    return 0;\n\n  strncpy(tc->username, u, MAXUSERLEN);\n\n  SHA1Init(&tc->hash);\n\n  tc->n.len = n->len;\n  tc->n.data = tc->nbuf;\n  memcpy(tc->n.data, n->data, tc->n.len);\n\n  SHA1Init(&ctxt);\n  SHA1Update(&ctxt, tc->n.data, tc->n.len);\n  SHA1Final(buf1, &ctxt);\n\n  tc->g.len = g->len;\n  tc->g.data = tc->gbuf;\n  memcpy(tc->g.data, g->data, tc->g.len);\n\n  SHA1Init(&ctxt);\n  SHA1Update(&ctxt, tc->g.data, tc->g.len);\n  SHA1Final(buf2, &ctxt);\n\n  for(i = 0; i < sizeof(buf1); ++i)\n    buf1[i] ^= buf2[i];\n\n  SHA1Update(&tc->hash, buf1, sizeof(buf1));\n\n  SHA1Init(&ctxt);\n  SHA1Update(&ctxt, tc->username, strlen(tc->username));\n  SHA1Final(buf1, &ctxt);\n\n  SHA1Update(&tc->hash, buf1, sizeof(buf1));\n\n  tc->s.len = s->len;\n  tc->s.data = tc->sbuf;\n  memcpy(tc->s.data, s->data, tc->s.len);\n\n  SHA1Update(&tc->hash, tc->s.data, tc->s.len);\n\n  tc->a.data = tc->abuf;\n  tc->A.data = tc->Abuf;\n  tc->p.data = tc->pbuf;\n  tc->v.data = tc->vbuf;\n\n  SHA1Init(&tc->ckhash);\n\n  return tc;\n}\n\n_TYPE( struct t_num * )\nt_clientgenexp(tc)\n     struct t_client * tc;\n{\n  BigInteger a, A, n, g;\n\n  if(tc->n.len < ALEN)\n    tc->a.len = tc->n.len;\n  else\n    tc->a.len = ALEN;\n\n  t_random(tc->a.data, tc->a.len);\n  a = BigIntegerFromBytes(tc->a.data, tc->a.len);\n  n = BigIntegerFromBytes(tc->n.data, tc->n.len);\n  g = BigIntegerFromBytes(tc->g.data, tc->g.len);\n  A = BigIntegerFromInt(0);\n  BigIntegerModExp(A, g, a, n);\n  tc->A.len = BigIntegerToBytes(A, tc->A.data);\n\n  BigIntegerFree(A);\n  BigIntegerFree(a);\n  BigIntegerFree(g);\n  BigIntegerFree(n);\n\n  SHA1Update(&tc->hash, tc->A.data, tc->A.len);\n  SHA1Update(&tc->ckhash, tc->A.data, tc->A.len);\n\n  return &tc->A;\n}\n\n_TYPE( void )\nt_clientpasswd(tc, password)\n     struct t_client * tc;\n     char * password;\n{\n  BigInteger n, g, p, v;\n  SHA1_CTX ctxt;\n  unsigned char dig[SHA_DIGESTSIZE];\n\n  n = BigIntegerFromBytes(tc->n.data, tc->n.len);\n  g = BigIntegerFromBytes(tc->g.data, tc->g.len);\n\n  SHA1Init(&ctxt);\n  SHA1Update(&ctxt, tc->username, strlen(tc->username));\n  SHA1Update(&ctxt, \":\", 1);\n  SHA1Update(&ctxt, password, strlen(password));\n  SHA1Final(dig, &ctxt);\n\n  SHA1Init(&ctxt);\n  SHA1Update(&ctxt, tc->s.data, tc->s.len);\n  SHA1Update(&ctxt, dig, sizeof(dig));\n  SHA1Final(dig, &ctxt);\n\n  p = BigIntegerFromBytes(dig, sizeof(dig));\n\n  v = BigIntegerFromInt(0);\n  BigIntegerModExp(v, g, p, n);\n\n  tc->p.len = BigIntegerToBytes(p, tc->p.data);\n  BigIntegerFree(p);\n\n  tc->v.len = BigIntegerToBytes(v, tc->v.data);\n  BigIntegerFree(v);\n}\n\n_TYPE( unsigned char * )\nt_clientgetkey(tc, serverval)\n     struct t_client * tc;\n     struct t_num * serverval;\n{\n  BigInteger n, B, v, p, a, sum, S;\n  unsigned char sbuf[MAXPARAMLEN];\n  unsigned char dig[SHA_DIGESTSIZE];\n  unsigned slen;\n  unsigned int u;\n  SHA1_CTX ctxt;\n\n  SHA1Init(&ctxt);\n  SHA1Update(&ctxt, serverval->data, serverval->len);\n  SHA1Final(dig, &ctxt);\n  u = (dig[0] << 24) | (dig[1] << 16) | (dig[2] << 8) | dig[3];\n  if(u == 0)\n    return NULL;\n\n  SHA1Update(&tc->hash, serverval->data, serverval->len);\n\n  B = BigIntegerFromBytes(serverval->data, serverval->len);\n  n = BigIntegerFromBytes(tc->n.data, tc->n.len);\n\n  if(BigIntegerCmp(B, n) >= 0 || BigIntegerCmpInt(B, 0) == 0) {\n    BigIntegerFree(B);\n    BigIntegerFree(n);\n    return NULL;\n  }\n  v = BigIntegerFromBytes(tc->v.data, tc->v.len);\n  if(BigIntegerCmp(B, v) < 0)\n    BigIntegerAdd(B, B, n);\n  BigIntegerSub(B, B, v);\n  BigIntegerFree(v);\n\n  a = BigIntegerFromBytes(tc->a.data, tc->a.len);\n  p = BigIntegerFromBytes(tc->p.data, tc->p.len);\n\n  sum = BigIntegerFromInt(0);\n  BigIntegerMulInt(sum, p, u);\n  BigIntegerAdd(sum, sum, a);\n\n  BigIntegerFree(p);\n  BigIntegerFree(a);\n\n  S = BigIntegerFromInt(0);\n  BigIntegerModExp(S, B, sum, n);\n  slen = BigIntegerToBytes(S, sbuf);\n\n  BigIntegerFree(S);\n  BigIntegerFree(sum);\n  BigIntegerFree(B);\n  BigIntegerFree(n);\n\n  t_sessionkey(tc->session_key, sbuf, slen);\n  memset(sbuf, 0, slen);\n\n  SHA1Update(&tc->hash, tc->session_key, sizeof(tc->session_key));\n\n  SHA1Final(tc->session_response, &tc->hash);\n  SHA1Update(&tc->ckhash, tc->session_response, sizeof(tc->session_response));\n  SHA1Update(&tc->ckhash, tc->session_key, sizeof(tc->session_key));\n\n  return tc->session_key;\n}\n\n_TYPE( int )\nt_clientverify(tc, resp)\n    struct t_client * tc;\n    unsigned char * resp;\n{\n  unsigned char expected[SHA_DIGESTSIZE];\n\n  SHA1Final(expected, &tc->ckhash);\n  return memcmp(expected, resp, sizeof(expected));\n}\n\n_TYPE( unsigned char * )\nt_clientresponse(tc)\n    struct t_client * tc;\n{\n  return tc->session_response;\n}\n\n_TYPE( void )\nt_clientclose(tc)\n     struct t_client * tc;\n{\n  memset(tc->abuf, 0, sizeof(tc->abuf));\n  memset(tc->pbuf, 0, sizeof(tc->pbuf));\n  memset(tc->vbuf, 0, sizeof(tc->vbuf));\n  memset(tc->session_key, 0, sizeof(tc->session_key));\n  free(tc);\n}\n"
  },
  {
    "path": "package/network/services/ead/src/tinysrp/t_client.h",
    "content": "/*\n * Copyright (c) 1997-1999  The Stanford SRP Authentication Project\n * All Rights Reserved.\n *\n * Permission is hereby granted, free of charge, to any person obtaining\n * a copy of this software and associated documentation files (the\n * \"Software\"), to deal in the Software without restriction, including\n * without limitation the rights to use, copy, modify, merge, publish,\n * distribute, sublicense, and/or sell copies of the Software, and to\n * permit persons to whom the Software is furnished to do so, subject to\n * the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS-IS\" AND WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS, IMPLIED OR OTHERWISE, INCLUDING WITHOUT LIMITATION, ANY\n * WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.\n *\n * IN NO EVENT SHALL STANFORD BE LIABLE FOR ANY SPECIAL, INCIDENTAL,\n * INDIRECT OR CONSEQUENTIAL DAMAGES OF ANY KIND, OR ANY DAMAGES WHATSOEVER\n * RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER OR NOT ADVISED OF\n * THE POSSIBILITY OF DAMAGE, AND ON ANY THEORY OF LIABILITY, ARISING OUT\n * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n * In addition, the following conditions apply:\n *\n * 1. Any software that incorporates the SRP authentication technology\n *    must display the following acknowlegment:\n *    \"This product uses the 'Secure Remote Password' cryptographic\n *     authentication system developed by Tom Wu (tjw@CS.Stanford.EDU).\"\n *\n * 2. Any software that incorporates all or part of the SRP distribution\n *    itself must also display the following acknowledgment:\n *    \"This product includes software developed by Tom Wu and Eugene\n *     Jhong for the SRP Distribution (http://srp.stanford.edu/srp/).\"\n *\n * 3. Redistributions in source or binary form must retain an intact copy\n *    of this copyright notice and list of conditions.\n */\n\n#ifndef T_CLIENT_H\n#define T_CLIENT_H\n\n#include \"t_sha.h\"\n\n#if     !defined(P)\n#ifdef  __STDC__\n#define P(x)    x\n#else\n#define P(x)    ()\n#endif\n#endif\n\n/*      For building dynamic link libraries under windows, windows NT\n *      using MSVC1.5 or MSVC2.0\n */\n\n#ifndef _DLLDECL\n#define _DLLDECL\n\n#ifdef MSVC15   /* MSVC1.5 support for 16 bit apps */\n#define _MSVC15EXPORT _export\n#define _MSVC20EXPORT\n#define _DLLAPI _export _pascal\n#define _TYPE(a) a _MSVC15EXPORT\n#define DLLEXPORT 1\n\n#elif MSVC20\n#define _MSVC15EXPORT\n#define _MSVC20EXPORT _declspec(dllexport)\n#define _DLLAPI\n#define _TYPE(a) _MSVC20EXPORT a\n#define DLLEXPORT 1\n\n#else                   /* Default, non-dll.  Use this for Unix or DOS */\n#define _MSVC15DEXPORT\n#define _MSVC20EXPORT\n#define _DLLAPI\n#define _TYPE(a) a\n#endif\n#endif\n\n#define ALEN 32\n#define MIN_MOD_BYTES 64        /* 512 bits */\n\nstruct t_client {\n  struct t_num n;\n  struct t_num g;\n  struct t_num s;\n\n  struct t_num a;\n  struct t_num A;\n\n  struct t_num p;\n  struct t_num v;\n\n  SHA1_CTX hash, ckhash;\n\n  char username[MAXUSERLEN];\n  unsigned char session_key[SESSION_KEY_LEN];\n  unsigned char session_response[RESPONSE_LEN];\n\n  unsigned char nbuf[MAXPARAMLEN], gbuf[MAXPARAMLEN], sbuf[MAXSALTLEN];\n  unsigned char pbuf[MAXPARAMLEN], vbuf[MAXPARAMLEN];\n  unsigned char abuf[ALEN], Abuf[MAXPARAMLEN];\n};\n\n/*\n * SRP client-side negotiation\n *\n * This code negotiates the client side of an SRP exchange.\n * \"t_clientopen\" accepts a username, and N, g, and s parameters,\n *   which are usually sent by the server in the first round.\n *   The client should then call...\n * \"t_clientgenexp\" will generate a random 256-bit exponent and\n *   raise g to that power, returning the result.  This result\n *   should be sent to the server as w(p).\n * \"t_clientpasswd\" accepts the user's password, which should be\n *   entered locally and updates the client's state.\n * \"t_clientgetkey\" accepts the exponential y(p), which should\n *   be sent by the server in the next round and computes the\n *   256-bit session key.  This data should be saved before the\n *   session is closed.\n * \"t_clientresponse\" computes the session key proof as SHA(y(p), K).\n * \"t_clientclose\" closes the session and frees its memory.\n *\n * Note that authentication is not performed per se; it is up\n * to either/both sides of the protocol to now verify securely\n * that their session keys agree in order to establish authenticity.\n * One possible way is through \"oracle hashing\"; one side sends\n * r, the other replies with H(r,K), where H() is a hash function.\n *\n * t_clientresponse and t_clientverify now implement a version of\n * the session-key verification described above.\n */\n_TYPE( struct t_client * )\n  t_clientopen P((const char *, struct t_num *, struct t_num *,\n\t\t  struct t_num *));\n_TYPE( struct t_num * ) t_clientgenexp P((struct t_client *));\n_TYPE( void ) t_clientpasswd P((struct t_client *, char *));\n_TYPE( unsigned char * )\n  t_clientgetkey P((struct t_client *, struct t_num *));\n_TYPE( int ) t_clientverify P((struct t_client *, unsigned char *));\n_TYPE( unsigned char * ) t_clientresponse P((struct t_client *));\n_TYPE( void ) t_clientclose P((struct t_client *));\n\n#endif\n"
  },
  {
    "path": "package/network/services/ead/src/tinysrp/t_conf.c",
    "content": "/*\n * Copyright (c) 1997-1999  The Stanford SRP Authentication Project\n * All Rights Reserved.\n *\n * Permission is hereby granted, free of charge, to any person obtaining\n * a copy of this software and associated documentation files (the\n * \"Software\"), to deal in the Software without restriction, including\n * without limitation the rights to use, copy, modify, merge, publish,\n * distribute, sublicense, and/or sell copies of the Software, and to\n * permit persons to whom the Software is furnished to do so, subject to\n * the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS-IS\" AND WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS, IMPLIED OR OTHERWISE, INCLUDING WITHOUT LIMITATION, ANY\n * WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.\n *\n * IN NO EVENT SHALL STANFORD BE LIABLE FOR ANY SPECIAL, INCIDENTAL,\n * INDIRECT OR CONSEQUENTIAL DAMAGES OF ANY KIND, OR ANY DAMAGES WHATSOEVER\n * RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER OR NOT ADVISED OF\n * THE POSSIBILITY OF DAMAGE, AND ON ANY THEORY OF LIABILITY, ARISING OUT\n * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n * In addition, the following conditions apply:\n *\n * 1. Any software that incorporates the SRP authentication technology\n *    must display the following acknowlegment:\n *    \"This product uses the 'Secure Remote Password' cryptographic\n *     authentication system developed by Tom Wu (tjw@CS.Stanford.EDU).\"\n *\n * 2. Any software that incorporates all or part of the SRP distribution\n *    itself must also display the following acknowledgment:\n *    \"This product includes software developed by Tom Wu and Eugene\n *     Jhong for the SRP Distribution (http://srp.stanford.edu/srp/).\"\n *\n * 3. Redistributions in source or binary form must retain an intact copy\n *    of this copyright notice and list of conditions.\n */\n\n#include <stdio.h>\n\n#include \"t_defines.h\"\n#include \"t_pwd.h\"\n#include \"t_read.h\"\n#include \"bn.h\"\n#include \"bn_lcl.h\"\n#include \"bn_prime.h\"\n\n#define TABLE_SIZE      32\n\nstatic int witness(BIGNUM *w, const BIGNUM *a, const BIGNUM *a1,\n\tconst BIGNUM *a1_odd, int k, BN_CTX *ctx, BN_MONT_CTX *mont);\n\n/*\n * This is the safe prime generation logic.\n * To generate a safe prime p (where p = 2q+1 and q is prime), we start\n * with a random odd q that is one bit shorter than the desired length\n * of p.  We use a simple 30-element sieve to filter the values of q\n * and consider only those that are 11, 23, or 29 (mod 30).  (If q were\n * anything else, either q or p would be divisible by 2, 3, or 5).\n * For the values of q that are left, we apply the following tests in\n * this order:\n *\n *   trial divide q\n *   let p = 2q + 1\n *   trial divide p\n *   apply Fermat test to q (2^q == 2 (mod q))\n *   apply Fermat test to p (2^p == 2 (mod p))\n *   apply real probablistic primality test to q\n *   apply real probablistic primality test to p\n *\n * A number that passes all these tests is considered a safe prime for\n * our purposes.  The tests are ordered this way for efficiency; the\n * slower tests are run rarely if ever at all.\n */\n\nstatic int\ntrialdiv(x)\n     const BigInteger x;\n{\n  static int primes[] = {               /* All odd primes < 256 */\n      3,   5,   7,  11,  13,  17,  19,  23,  29,\n     31,  37,  41,  43,  47,  53,  59,  61,  67,\n     71,  73,  79,  83,  89,  97, 101, 103,\n    107, 109, 113, 127, 131, 137, 139, 149, 151,\n    157, 163, 167, 173, 179, 181, 191, 193, 197,\n    199, 211, 223, 227, 229, 233, 239, 241, 251\n  };\n  static int nprimes = sizeof(primes) / sizeof(int);\n  int i;\n\n  for(i = 0; i < nprimes; ++i) {\n    if(BigIntegerModInt(x, primes[i]) == 0)\n      return primes[i];\n  }\n  return 1;\n}\n\n/* x + sieve30[x%30] == 11, 23, or 29 (mod 30) */\n\nstatic int sieve30[] =\n{  11, 10,  9,  8,  7,  6,  5,  4,  3,  2,\n    1, 12, 11, 10,  9,  8,  7,  6,  5,  4,\n    3,  2,  1,  6,  5,  4,  3,  2,  1, 12\n};\n\n/* Find a Sophie-Germain prime between \"lo\" and \"hi\".  NOTE: this is not\n   a \"safe prime\", but the smaller prime.  Take 2q+1 to get the safe prime. */\n\nstatic void\nsophie_germain(q, lo, hi)\n     BigInteger q;              /* assumed initialized */\n     const BigInteger lo;\n     const BigInteger hi;\n{\n  BigInteger m, p, r;\n  char parambuf[MAXPARAMLEN];\n  int foundprime = 0;\n  int i, mod30;\n\n  m = BigIntegerFromInt(0);\n  BigIntegerSub(m, hi, lo);\n  i = (BigIntegerBitLen(m) + 7) / 8;\n  t_random(parambuf, i);\n  r = BigIntegerFromBytes(parambuf, i);\n  BigIntegerMod(r, r, m);\n\n  BigIntegerAdd(q, r, lo);\n  if(BigIntegerModInt(q, 2) == 0)\n    BigIntegerAddInt(q, q, 1);          /* make q odd */\n\n  mod30 = BigIntegerModInt(q, 30);      /* mod30 = q % 30 */\n\n  BigIntegerFree(m);\n  m = BigIntegerFromInt(2);                     /* m = 2 */\n  p = BigIntegerFromInt(0);\n\n  while(BigIntegerCmp(q, hi) < 0) {\n    if(trialdiv(q) < 2) {\n      BigIntegerMulInt(p, q, 2);                        /* p = 2 * q */\n      BigIntegerAddInt(p, p, 1);                /* p += 1 */\n      if(trialdiv(p) < 2) {\n\tBigIntegerModExp(r, m, q, q);           /* r = 2^q % q */\n\tif(BigIntegerCmpInt(r, 2) == 0) {       /* if(r == 2) */\n\t  BigIntegerModExp(r, m, p, p);         /* r = 2^p % p */\n\t  if(BigIntegerCmpInt(r, 2) == 0) {     /* if(r == 2) */\n\t    if(BigIntegerCheckPrime(q) && BigIntegerCheckPrime(p)) {\n\t      ++foundprime;\n\t      break;\n\t    }\n\t  }\n\t}\n      }\n    }\n\n    i = sieve30[mod30];\n    BigIntegerAddInt(q, q, i);          /* q += i */\n    mod30 = (mod30 + i) % 30;\n  }\n\n  /* should wrap around on failure */\n  if(!foundprime) {\n    fprintf(stderr, \"Prime generation failed!\\n\");\n    exit(1);\n  }\n\n  BigIntegerFree(r);\n  BigIntegerFree(m);\n  BigIntegerFree(p);\n}\n\n_TYPE( struct t_confent * )\nt_makeconfent(tc, nsize)\n     struct t_conf * tc;\n     int nsize;\n{\n  BigInteger n, g, q, t, u;\n\n  t = BigIntegerFromInt(0);\n  u = BigIntegerFromInt(1);             /* u = 1 */\n  BigIntegerLShift(t, u, nsize - 2);    /* t = 2^(nsize-2) */\n  BigIntegerMulInt(u, t, 2);            /* u = 2^(nsize-1) */\n\n  q = BigIntegerFromInt(0);\n  sophie_germain(q, t, u);\n\n  n = BigIntegerFromInt(0);\n  BigIntegerMulInt(n, q, 2);\n  BigIntegerAddInt(n, n, 1);\n\n  /* Look for a generator mod n */\n  g = BigIntegerFromInt(2);\n  while(1) {\n    BigIntegerModExp(t, g, q, n);               /* t = g^q % n */\n    if(BigIntegerCmpInt(t, 1) == 0)             /* if(t == 1) */\n      BigIntegerAddInt(g, g, 1);                /* ++g */\n    else\n      break;\n  }\n  BigIntegerFree(t);\n  BigIntegerFree(u);\n  BigIntegerFree(q);\n\n  tc->tcbuf.modulus.data = tc->modbuf;\n  tc->tcbuf.modulus.len = BigIntegerToBytes(n, tc->tcbuf.modulus.data);\n  BigIntegerFree(n);\n\n  tc->tcbuf.generator.data = tc->genbuf;\n  tc->tcbuf.generator.len = BigIntegerToBytes(g, tc->tcbuf.generator.data);\n  BigIntegerFree(g);\n\n  tc->tcbuf.index = 1;\n  return &tc->tcbuf;\n}\n\n_TYPE( struct t_confent * )\nt_makeconfent_c(tc, nsize)\n     struct t_conf * tc;\n     int nsize;\n{\n  BigInteger g, n, p, q, j, k, t, u;\n  int psize, qsize;\n\n  psize = nsize / 2;\n  qsize = nsize - psize;\n\n  t = BigIntegerFromInt(1);             /* t = 1 */\n  u = BigIntegerFromInt(0);\n  BigIntegerLShift(u, t, psize - 3);    /* u = t*2^(psize-3) = 2^(psize-3) */\n  BigIntegerMulInt(t, u, 3);                    /* t = 3*u = 1.5*2^(psize-2) */\n  BigIntegerAdd(u, u, t);                       /* u += t [u = 2^(psize-1)] */\n  j = BigIntegerFromInt(0);\n  sophie_germain(j, t, u);\n\n  k = BigIntegerFromInt(0);\n  if(qsize != psize) {\n    BigIntegerFree(t);\n    t = BigIntegerFromInt(1);           /* t = 1 */\n    BigIntegerLShift(u, t, qsize - 3);  /* u = t*2^(qsize-3) = 2^(qsize-3) */\n    BigIntegerMulInt(t, u, 3);          /* t = 3*u = 1.5*2^(qsize-2) */\n    BigIntegerAdd(u, u, t);             /* u += t [u = 2^(qsize-1)] */\n  }\n  sophie_germain(k, t, u);\n\n  p = BigIntegerFromInt(0);\n  BigIntegerMulInt(p, j, 2);            /* p = 2 * j */\n  BigIntegerAddInt(p, p, 1);            /* p += 1 */\n\n  q = BigIntegerFromInt(0);\n  BigIntegerMulInt(q, k, 2);            /* q = 2 * k */\n  BigIntegerAddInt(q, q, 1);            /* q += 1 */\n\n  n = BigIntegerFromInt(0);\n  BigIntegerMul(n, p, q);               /* n = p * q */\n  BigIntegerMul(u, j, k);               /* u = j * k */\n\n  BigIntegerFree(p);\n  BigIntegerFree(q);\n  BigIntegerFree(j);\n  BigIntegerFree(k);\n\n  g = BigIntegerFromInt(2);             /* g = 2 */\n\n  /* Look for a generator mod n */\n  while(1) {\n    BigIntegerModExp(t, g, u, n);       /* t = g^u % n */\n    if(BigIntegerCmpInt(t, 1) == 0)\n      BigIntegerAddInt(g, g, 1);        /* ++g */\n    else\n      break;\n  }\n\n  BigIntegerFree(u);\n  BigIntegerFree(t);\n\n  tc->tcbuf.modulus.data = tc->modbuf;\n  tc->tcbuf.modulus.len = BigIntegerToBytes(n, tc->tcbuf.modulus.data);\n  BigIntegerFree(n);\n\n  tc->tcbuf.generator.data = tc->genbuf;\n  tc->tcbuf.generator.len = BigIntegerToBytes(g, tc->tcbuf.generator.data);\n  BigIntegerFree(g);\n\n  tc->tcbuf.index = 1;\n  return &tc->tcbuf;\n}\n\n_TYPE( struct t_confent * )\nt_newconfent(tc)\n    struct t_conf * tc;\n{\n  tc->tcbuf.index = 0;\n  tc->tcbuf.modulus.data = tc->modbuf;\n  tc->tcbuf.modulus.len = 0;\n  tc->tcbuf.generator.data = tc->genbuf;\n  tc->tcbuf.generator.len = 0;\n  return &tc->tcbuf;\n}\n\n_TYPE( void )\nt_putconfent(ent, fp)\n     const struct t_confent * ent;\n     FILE * fp;\n{\n  char strbuf[MAXB64PARAMLEN];\n\n  fprintf(fp, \"%d:%s:\", ent->index,\n\t  t_tob64(strbuf, ent->modulus.data, ent->modulus.len));\n  fprintf(fp, \"%s\\n\",\n\t  t_tob64(strbuf, ent->generator.data, ent->generator.len));\n}\n\nint\nBigIntegerBitLen(b)\n     BigInteger b;\n{\n  return BN_num_bits(b);\n}\n\nint\nBigIntegerCheckPrime(n)\n     BigInteger n;\n{\n  BN_CTX * ctx = BN_CTX_new();\n  int rv = BN_is_prime(n, 25, NULL, ctx, NULL);\n  BN_CTX_free(ctx);\n  return rv;\n}\n\nunsigned int\nBigIntegerModInt(d, m)\n     BigInteger d;\n     unsigned int m;\n{\n  return BN_mod_word(d, m);\n}\n\nvoid\nBigIntegerMod(result, d, m)\n     BigInteger result, d, m;\n{\n  BN_CTX * ctx = BN_CTX_new();\n  BN_mod(result, d, m, ctx);\n  BN_CTX_free(ctx);\n}\n\nvoid\nBigIntegerMul(result, m1, m2)\n     BigInteger result, m1, m2;\n{\n  BN_CTX * ctx = BN_CTX_new();\n  BN_mul(result, m1, m2, ctx);\n  BN_CTX_free(ctx);\n}\n\nvoid\nBigIntegerLShift(result, x, bits)\n     BigInteger result, x;\n     unsigned int bits;\n{\n  BN_lshift(result, x, bits);\n}\n\nint BN_is_prime(const BIGNUM *a, int checks, void (*callback)(int,int,void *),\n\tBN_CTX *ctx_passed, void *cb_arg)\n\t{\n\treturn BN_is_prime_fasttest(a, checks, callback, ctx_passed, cb_arg, 0);\n\t}\n\nint BN_is_prime_fasttest(const BIGNUM *a, int checks,\n\t\tvoid (*callback)(int,int,void *),\n\t\tBN_CTX *ctx_passed, void *cb_arg,\n\t\tint do_trial_division)\n\t{\n\tint i, j, ret = -1;\n\tint k;\n\tBN_CTX *ctx = NULL;\n\tBIGNUM *A1, *A1_odd, *check; /* taken from ctx */\n\tBN_MONT_CTX *mont = NULL;\n\tconst BIGNUM *A = NULL;\n\n\tif (checks == BN_prime_checks)\n\t\tchecks = BN_prime_checks_for_size(BN_num_bits(a));\n\n\t/* first look for small factors */\n\tif (!BN_is_odd(a))\n\t\treturn(0);\n\tif (do_trial_division)\n\t\t{\n\t\tfor (i = 1; i < NUMPRIMES; i++)\n\t\t\tif (BN_mod_word(a, primes[i]) == 0)\n\t\t\t\treturn 0;\n\t\tif (callback != NULL) callback(1, -1, cb_arg);\n\t\t}\n\n\tif (ctx_passed != NULL)\n\t\tctx = ctx_passed;\n\telse\n\t\tif ((ctx=BN_CTX_new()) == NULL)\n\t\t\tgoto err;\n\tBN_CTX_start(ctx);\n\n\t/* A := abs(a) */\n\tif (a->neg)\n\t\t{\n\t\tBIGNUM *t;\n\t\tif ((t = BN_CTX_get(ctx)) == NULL) goto err;\n\t\tBN_copy(t, a);\n\t\tt->neg = 0;\n\t\tA = t;\n\t\t}\n\telse\n\t\tA = a;\n\tA1 = BN_CTX_get(ctx);\n\tA1_odd = BN_CTX_get(ctx);\n\tcheck = BN_CTX_get(ctx);\n\tif (check == NULL) goto err;\n\n\t/* compute A1 := A - 1 */\n\tif (!BN_copy(A1, A))\n\t\tgoto err;\n\tif (!BN_sub_word(A1, 1))\n\t\tgoto err;\n\tif (BN_is_zero(A1))\n\t\t{\n\t\tret = 0;\n\t\tgoto err;\n\t\t}\n\n\t/* write  A1  as  A1_odd * 2^k */\n\tk = 1;\n\twhile (!BN_is_bit_set(A1, k))\n\t\tk++;\n\tif (!BN_rshift(A1_odd, A1, k))\n\t\tgoto err;\n\n\t/* Montgomery setup for computations mod A */\n\tmont = BN_MONT_CTX_new();\n\tif (mont == NULL)\n\t\tgoto err;\n\tif (!BN_MONT_CTX_set(mont, A, ctx))\n\t\tgoto err;\n\n\tfor (i = 0; i < checks; i++)\n\t\t{\n\t\tif (!BN_pseudo_rand(check, BN_num_bits(A1), 0, 0))\n\t\t\tgoto err;\n\t\tif (BN_cmp(check, A1) >= 0)\n\t\t\tif (!BN_sub(check, check, A1))\n\t\t\t\tgoto err;\n\t\tif (!BN_add_word(check, 1))\n\t\t\tgoto err;\n\t\t/* now 1 <= check < A */\n\n\t\tj = witness(check, A, A1, A1_odd, k, ctx, mont);\n\t\tif (j == -1) goto err;\n\t\tif (j)\n\t\t\t{\n\t\t\tret=0;\n\t\t\tgoto err;\n\t\t\t}\n\t\tif (callback != NULL) callback(1,i,cb_arg);\n\t\t}\n\tret=1;\nerr:\n\tif (ctx != NULL)\n\t\t{\n\t\tBN_CTX_end(ctx);\n\t\tif (ctx_passed == NULL)\n\t\t\tBN_CTX_free(ctx);\n\t\t}\n\tif (mont != NULL)\n\t\tBN_MONT_CTX_free(mont);\n\n\treturn(ret);\n\t}\n\nstatic int witness(BIGNUM *w, const BIGNUM *a, const BIGNUM *a1,\n\tconst BIGNUM *a1_odd, int k, BN_CTX *ctx, BN_MONT_CTX *mont)\n\t{\n\tif (!BN_mod_exp_mont(w, w, a1_odd, a, ctx, mont)) /* w := w^a1_odd mod a */\n\t\treturn -1;\n\tif (BN_is_one(w))\n\t\treturn 0; /* probably prime */\n\tif (BN_cmp(w, a1) == 0)\n\t\treturn 0; /* w == -1 (mod a),  'a' is probably prime */\n\twhile (--k)\n\t\t{\n\t\tif (!BN_mod_mul(w, w, w, a, ctx)) /* w := w^2 mod a */\n\t\t\treturn -1;\n\t\tif (BN_is_one(w))\n\t\t\treturn 1; /* 'a' is composite, otherwise a previous 'w' would\n\t\t\t\t   * have been == -1 (mod 'a') */\n\t\tif (BN_cmp(w, a1) == 0)\n\t\t\treturn 0; /* w == -1 (mod a), 'a' is probably prime */\n\t\t}\n\t/* If we get here, 'w' is the (a-1)/2-th power of the original 'w',\n\t * and it is neither -1 nor +1 -- so 'a' cannot be prime */\n\treturn 1;\n\t}\n\nint BN_mod_exp_mont(BIGNUM *rr, BIGNUM *a, const BIGNUM *p,\n\t\t    const BIGNUM *m, BN_CTX *ctx, BN_MONT_CTX *in_mont)\n\t{\n\tint i,j,bits,ret=0,wstart,wend,window,wvalue;\n\tint start=1,ts=0;\n\tBIGNUM *d,*r;\n\tBIGNUM *aa;\n\tBIGNUM val[TABLE_SIZE];\n\tBN_MONT_CTX *mont=NULL;\n\n\tbn_check_top(a);\n\tbn_check_top(p);\n\tbn_check_top(m);\n\n\tif (!(m->d[0] & 1))\n\t\t{\n\t\treturn(0);\n\t\t}\n\tbits=BN_num_bits(p);\n\tif (bits == 0)\n\t\t{\n\t\tBN_one(rr);\n\t\treturn(1);\n\t\t}\n\tBN_CTX_start(ctx);\n\td = BN_CTX_get(ctx);\n\tr = BN_CTX_get(ctx);\n\tif (d == NULL || r == NULL) goto err;\n\n\t/* If this is not done, things will break in the montgomery\n\t * part */\n\n\tif (in_mont != NULL)\n\t\tmont=in_mont;\n\telse\n\t\t{\n\t\tif ((mont=BN_MONT_CTX_new()) == NULL) goto err;\n\t\tif (!BN_MONT_CTX_set(mont,m,ctx)) goto err;\n\t\t}\n\n\tBN_init(&val[0]);\n\tts=1;\n\tif (BN_ucmp(a,m) >= 0)\n\t\t{\n\t\tif (!BN_mod(&(val[0]),a,m,ctx))\n\t\t\tgoto err;\n\t\taa= &(val[0]);\n\t\t}\n\telse\n\t\taa=a;\n\tif (!BN_to_montgomery(&(val[0]),aa,mont,ctx)) goto err; /* 1 */\n\n\twindow = BN_window_bits_for_exponent_size(bits);\n\tif (window > 1)\n\t\t{\n\t\tif (!BN_mod_mul_montgomery(d,&(val[0]),&(val[0]),mont,ctx)) goto err; /* 2 */\n\t\tj=1<<(window-1);\n\t\tfor (i=1; i<j; i++)\n\t\t\t{\n\t\t\tBN_init(&(val[i]));\n\t\t\tif (!BN_mod_mul_montgomery(&(val[i]),&(val[i-1]),d,mont,ctx))\n\t\t\t\tgoto err;\n\t\t\t}\n\t\tts=i;\n\t\t}\n\n\tstart=1;        /* This is used to avoid multiplication etc\n\t\t\t * when there is only the value '1' in the\n\t\t\t * buffer. */\n\twvalue=0;       /* The 'value' of the window */\n\twstart=bits-1;  /* The top bit of the window */\n\twend=0;         /* The bottom bit of the window */\n\n\tif (!BN_to_montgomery(r,BN_value_one(),mont,ctx)) goto err;\n\tfor (;;)\n\t\t{\n\t\tif (BN_is_bit_set(p,wstart) == 0)\n\t\t\t{\n\t\t\tif (!start)\n\t\t\t\t{\n\t\t\t\tif (!BN_mod_mul_montgomery(r,r,r,mont,ctx))\n\t\t\t\tgoto err;\n\t\t\t\t}\n\t\t\tif (wstart == 0) break;\n\t\t\twstart--;\n\t\t\tcontinue;\n\t\t\t}\n\t\t/* We now have wstart on a 'set' bit, we now need to work out\n\t\t * how bit a window to do.  To do this we need to scan\n\t\t * forward until the last set bit before the end of the\n\t\t * window */\n\t\tj=wstart;\n\t\twvalue=1;\n\t\twend=0;\n\t\tfor (i=1; i<window; i++)\n\t\t\t{\n\t\t\tif (wstart-i < 0) break;\n\t\t\tif (BN_is_bit_set(p,wstart-i))\n\t\t\t\t{\n\t\t\t\twvalue<<=(i-wend);\n\t\t\t\twvalue|=1;\n\t\t\t\twend=i;\n\t\t\t\t}\n\t\t\t}\n\n\t\t/* wend is the size of the current window */\n\t\tj=wend+1;\n\t\t/* add the 'bytes above' */\n\t\tif (!start)\n\t\t\tfor (i=0; i<j; i++)\n\t\t\t\t{\n\t\t\t\tif (!BN_mod_mul_montgomery(r,r,r,mont,ctx))\n\t\t\t\t\tgoto err;\n\t\t\t\t}\n\n\t\t/* wvalue will be an odd number < 2^window */\n\t\tif (!BN_mod_mul_montgomery(r,r,&(val[wvalue>>1]),mont,ctx))\n\t\t\tgoto err;\n\n\t\t/* move the 'window' down further */\n\t\twstart-=wend+1;\n\t\twvalue=0;\n\t\tstart=0;\n\t\tif (wstart < 0) break;\n\t\t}\n\tif (!BN_from_montgomery(rr,r,mont,ctx)) goto err;\n\tret=1;\nerr:\n\tif ((in_mont == NULL) && (mont != NULL)) BN_MONT_CTX_free(mont);\n\tBN_CTX_end(ctx);\n\tfor (i=0; i<ts; i++)\n\t\tBN_clear_free(&(val[i]));\n\treturn(ret);\n\t}\n\nBN_ULONG BN_mod_word(const BIGNUM *a, BN_ULONG w)\n\t{\n#ifndef BN_LLONG\n\tBN_ULONG ret=0;\n#else\n\tBN_ULLONG ret=0;\n#endif\n\tint i;\n\n\tw&=BN_MASK2;\n\tfor (i=a->top-1; i>=0; i--)\n\t\t{\n#ifndef BN_LLONG\n\t\tret=((ret<<BN_BITS4)|((a->d[i]>>BN_BITS4)&BN_MASK2l))%w;\n\t\tret=((ret<<BN_BITS4)|(a->d[i]&BN_MASK2l))%w;\n#else\n\t\tret=(BN_ULLONG)(((ret<<(BN_ULLONG)BN_BITS2)|a->d[i])%\n\t\t\t(BN_ULLONG)w);\n#endif\n\t\t}\n\treturn((BN_ULONG)ret);\n\t}\n\nstatic int bnrand(int pseudorand, BIGNUM *rnd, int bits, int top, int bottom)\n\t{\n\tunsigned char *buf=NULL;\n\tint ret=0,bit,bytes,mask;\n\n\tif (bits == 0)\n\t\t{\n\t\tBN_zero(rnd);\n\t\treturn 1;\n\t\t}\n\n\tbytes=(bits+7)/8;\n\tbit=(bits-1)%8;\n\tmask=0xff<<bit;\n\n\tbuf=(unsigned char *)malloc(bytes);\n\tif (buf == NULL)\n\t\t{\n\t\tgoto err;\n\t\t}\n\n\t/* make a random number and set the top and bottom bits */\n\t/* this ignores the pseudorand flag */\n\n\tt_random(buf, bytes);\n\n\tif (top)\n\t\t{\n\t\tif (bit == 0)\n\t\t\t{\n\t\t\tbuf[0]=1;\n\t\t\tbuf[1]|=0x80;\n\t\t\t}\n\t\telse\n\t\t\t{\n\t\t\tbuf[0]|=(3<<(bit-1));\n\t\t\tbuf[0]&= ~(mask<<1);\n\t\t\t}\n\t\t}\n\telse\n\t\t{\n\t\tbuf[0]|=(1<<bit);\n\t\tbuf[0]&= ~(mask<<1);\n\t\t}\n\tif (bottom) /* set bottom bits to whatever odd is */\n\t\tbuf[bytes-1]|=1;\n\tif (!BN_bin2bn(buf,bytes,rnd)) goto err;\n\tret=1;\nerr:\n\tif (buf != NULL)\n\t\t{\n\t\tmemset(buf,0,bytes);\n\t\tfree(buf);\n\t\t}\n\treturn(ret);\n\t}\n\n/* BN_pseudo_rand is the same as BN_rand, now. */\n\nint     BN_pseudo_rand(BIGNUM *rnd, int bits, int top, int bottom)\n\t{\n\treturn bnrand(1, rnd, bits, top, bottom);\n\t}\n\n#define MONT_WORD /* use the faster word-based algorithm */\n\nint BN_mod_mul_montgomery(BIGNUM *r, BIGNUM *a, BIGNUM *b,\n\t\t\t  BN_MONT_CTX *mont, BN_CTX *ctx)\n\t{\n\tBIGNUM *tmp,*tmp2;\n\tint ret=0;\n\n\tBN_CTX_start(ctx);\n\ttmp = BN_CTX_get(ctx);\n\ttmp2 = BN_CTX_get(ctx);\n\tif (tmp == NULL || tmp2 == NULL) goto err;\n\n\tbn_check_top(tmp);\n\tbn_check_top(tmp2);\n\n\tif (a == b)\n\t\t{\n\t\tif (!BN_sqr(tmp,a,ctx)) goto err;\n\t\t}\n\telse\n\t\t{\n\t\tif (!BN_mul(tmp,a,b,ctx)) goto err;\n\t\t}\n\t/* reduce from aRR to aR */\n\tif (!BN_from_montgomery(r,tmp,mont,ctx)) goto err;\n\tret=1;\nerr:\n\tBN_CTX_end(ctx);\n\treturn(ret);\n\t}\n\nint BN_from_montgomery(BIGNUM *ret, BIGNUM *a, BN_MONT_CTX *mont,\n\t     BN_CTX *ctx)\n\t{\n\tint retn=0;\n\n#ifdef MONT_WORD\n\tBIGNUM *n,*r;\n\tBN_ULONG *ap,*np,*rp,n0,v,*nrp;\n\tint al,nl,max,i,x,ri;\n\n\tBN_CTX_start(ctx);\n\tif ((r = BN_CTX_get(ctx)) == NULL) goto err;\n\n\tif (!BN_copy(r,a)) goto err;\n\tn= &(mont->N);\n\n\tap=a->d;\n\t/* mont->ri is the size of mont->N in bits (rounded up\n\t   to the word size) */\n\tal=ri=mont->ri/BN_BITS2;\n\n\tnl=n->top;\n\tif ((al == 0) || (nl == 0)) { r->top=0; return(1); }\n\n\tmax=(nl+al+1); /* allow for overflow (no?) XXX */\n\tif (bn_wexpand(r,max) == NULL) goto err;\n\tif (bn_wexpand(ret,max) == NULL) goto err;\n\n\tr->neg=a->neg^n->neg;\n\tnp=n->d;\n\trp=r->d;\n\tnrp= &(r->d[nl]);\n\n\t/* clear the top words of T */\n#if 1\n\tfor (i=r->top; i<max; i++) /* memset? XXX */\n\t\tr->d[i]=0;\n#else\n\tmemset(&(r->d[r->top]),0,(max-r->top)*sizeof(BN_ULONG));\n#endif\n\n\tr->top=max;\n\tn0=mont->n0;\n\n#ifdef BN_COUNT\n\tprintf(\"word BN_from_montgomery %d * %d\\n\",nl,nl);\n#endif\n\tfor (i=0; i<nl; i++)\n\t\t{\n#ifdef __TANDEM\n\t\t{\n\t\t   long long t1;\n\t\t   long long t2;\n\t\t   long long t3;\n\t\t   t1 = rp[0] * (n0 & 0177777);\n\t\t   t2 = 037777600000l;\n\t\t   t2 = n0 & t2;\n\t\t   t3 = rp[0] & 0177777;\n\t\t   t2 = (t3 * t2) & BN_MASK2;\n\t\t   t1 = t1 + t2;\n\t\t   v=bn_mul_add_words(rp,np,nl,(BN_ULONG) t1);\n\t\t}\n#else\n\t\tv=bn_mul_add_words(rp,np,nl,(rp[0]*n0)&BN_MASK2);\n#endif\n\t\tnrp++;\n\t\trp++;\n\t\tif (((nrp[-1]+=v)&BN_MASK2) >= v)\n\t\t\tcontinue;\n\t\telse\n\t\t\t{\n\t\t\tif (((++nrp[0])&BN_MASK2) != 0) continue;\n\t\t\tif (((++nrp[1])&BN_MASK2) != 0) continue;\n\t\t\tfor (x=2; (((++nrp[x])&BN_MASK2) == 0); x++) ;\n\t\t\t}\n\t\t}\n\tbn_fix_top(r);\n\n\t/* mont->ri will be a multiple of the word size */\n#if 0\n\tBN_rshift(ret,r,mont->ri);\n#else\n\tret->neg = r->neg;\n\tx=ri;\n\trp=ret->d;\n\tap= &(r->d[x]);\n\tif (r->top < x)\n\t\tal=0;\n\telse\n\t\tal=r->top-x;\n\tret->top=al;\n\tal-=4;\n\tfor (i=0; i<al; i+=4)\n\t\t{\n\t\tBN_ULONG t1,t2,t3,t4;\n\n\t\tt1=ap[i+0];\n\t\tt2=ap[i+1];\n\t\tt3=ap[i+2];\n\t\tt4=ap[i+3];\n\t\trp[i+0]=t1;\n\t\trp[i+1]=t2;\n\t\trp[i+2]=t3;\n\t\trp[i+3]=t4;\n\t\t}\n\tal+=4;\n\tfor (; i<al; i++)\n\t\trp[i]=ap[i];\n#endif\n#else /* !MONT_WORD */\n\tBIGNUM *t1,*t2;\n\n\tBN_CTX_start(ctx);\n\tt1 = BN_CTX_get(ctx);\n\tt2 = BN_CTX_get(ctx);\n\tif (t1 == NULL || t2 == NULL) goto err;\n\n\tif (!BN_copy(t1,a)) goto err;\n\tBN_mask_bits(t1,mont->ri);\n\n\tif (!BN_mul(t2,t1,&mont->Ni,ctx)) goto err;\n\tBN_mask_bits(t2,mont->ri);\n\n\tif (!BN_mul(t1,t2,&mont->N,ctx)) goto err;\n\tif (!BN_add(t2,a,t1)) goto err;\n\tBN_rshift(ret,t2,mont->ri);\n#endif /* MONT_WORD */\n\n\tif (BN_ucmp(ret, &(mont->N)) >= 0)\n\t\t{\n\t\tBN_usub(ret,ret,&(mont->N));\n\t\t}\n\tretn=1;\n err:\n\tBN_CTX_end(ctx);\n\treturn(retn);\n\t}\n\nvoid BN_MONT_CTX_init(BN_MONT_CTX *ctx)\n\t{\n\tctx->ri=0;\n\tBN_init(&(ctx->RR));\n\tBN_init(&(ctx->N));\n\tBN_init(&(ctx->Ni));\n\tctx->flags=0;\n\t}\n\nBN_MONT_CTX *BN_MONT_CTX_new(void)\n\t{\n\tBN_MONT_CTX *ret;\n\n\tif ((ret=(BN_MONT_CTX *)malloc(sizeof(BN_MONT_CTX))) == NULL)\n\t\treturn(NULL);\n\n\tBN_MONT_CTX_init(ret);\n\tret->flags=BN_FLG_MALLOCED;\n\treturn(ret);\n\t}\n\nvoid BN_MONT_CTX_free(BN_MONT_CTX *mont)\n\t{\n\tif(mont == NULL)\n\t    return;\n\n\tBN_free(&(mont->RR));\n\tBN_free(&(mont->N));\n\tBN_free(&(mont->Ni));\n\tif (mont->flags & BN_FLG_MALLOCED)\n\t\tfree(mont);\n\t}\n\nint BN_MONT_CTX_set(BN_MONT_CTX *mont, const BIGNUM *mod, BN_CTX *ctx)\n\t{\n\tBIGNUM Ri,*R;\n\n\tBN_init(&Ri);\n\tR= &(mont->RR);                                 /* grab RR as a temp */\n\tBN_copy(&(mont->N),mod);                        /* Set N */\n\n#ifdef MONT_WORD\n\t\t{\n\t\tBIGNUM tmod;\n\t\tBN_ULONG buf[2];\n\n\t\tmont->ri=(BN_num_bits(mod)+(BN_BITS2-1))/BN_BITS2*BN_BITS2;\n\t\tBN_zero(R);\n\t\tBN_set_bit(R,BN_BITS2);                 /* R */\n\n\t\tbuf[0]=mod->d[0]; /* tmod = N mod word size */\n\t\tbuf[1]=0;\n\t\ttmod.d=buf;\n\t\ttmod.top=1;\n\t\ttmod.dmax=2;\n\t\ttmod.neg=mod->neg;\n\t\t\t\t\t\t\t/* Ri = R^-1 mod N*/\n\t\tif ((BN_mod_inverse(&Ri,R,&tmod,ctx)) == NULL)\n\t\t\tgoto err;\n\t\tBN_lshift(&Ri,&Ri,BN_BITS2);            /* R*Ri */\n\t\tif (!BN_is_zero(&Ri))\n\t\t\tBN_sub_word(&Ri,1);\n\t\telse /* if N mod word size == 1 */\n\t\t\tBN_set_word(&Ri,BN_MASK2);  /* Ri-- (mod word size) */\n\t\tBN_div(&Ri,NULL,&Ri,&tmod,ctx); /* Ni = (R*Ri-1)/N,\n\t\t\t\t\t\t * keep only least significant word: */\n\t\tmont->n0=Ri.d[0];\n\t\tBN_free(&Ri);\n\t\t}\n#else /* !MONT_WORD */\n\t\t{ /* bignum version */\n\t\tmont->ri=BN_num_bits(mod);\n\t\tBN_zero(R);\n\t\tBN_set_bit(R,mont->ri);                 /* R = 2^ri */\n\t\t\t\t\t\t\t/* Ri = R^-1 mod N*/\n\t\tif ((BN_mod_inverse(&Ri,R,mod,ctx)) == NULL)\n\t\t\tgoto err;\n\t\tBN_lshift(&Ri,&Ri,mont->ri);            /* R*Ri */\n\t\tBN_sub_word(&Ri,1);\n\t\t\t\t\t\t\t/* Ni = (R*Ri-1) / N */\n\t\tBN_div(&(mont->Ni),NULL,&Ri,mod,ctx);\n\t\tBN_free(&Ri);\n\t\t}\n#endif\n\n\t/* setup RR for conversions */\n\tBN_zero(&(mont->RR));\n\tBN_set_bit(&(mont->RR),mont->ri*2);\n\tBN_mod(&(mont->RR),&(mont->RR),&(mont->N),ctx);\n\n\treturn(1);\nerr:\n\treturn(0);\n\t}\n\nBIGNUM *BN_value_one(void)\n\t{\n\tstatic BN_ULONG data_one=1L;\n\tstatic BIGNUM const_one={&data_one,1,1,0};\n\n\treturn(&const_one);\n\t}\n\n/* solves ax == 1 (mod n) */\nBIGNUM *BN_mod_inverse(BIGNUM *in, BIGNUM *a, const BIGNUM *n, BN_CTX *ctx)\n\t{\n\tBIGNUM *A,*B,*X,*Y,*M,*D,*R=NULL;\n\tBIGNUM *T,*ret=NULL;\n\tint sign;\n\n\tbn_check_top(a);\n\tbn_check_top(n);\n\n\tBN_CTX_start(ctx);\n\tA = BN_CTX_get(ctx);\n\tB = BN_CTX_get(ctx);\n\tX = BN_CTX_get(ctx);\n\tD = BN_CTX_get(ctx);\n\tM = BN_CTX_get(ctx);\n\tY = BN_CTX_get(ctx);\n\tif (Y == NULL) goto err;\n\n\tif (in == NULL)\n\t\tR=BN_new();\n\telse\n\t\tR=in;\n\tif (R == NULL) goto err;\n\n\tBN_zero(X);\n\tBN_one(Y);\n\tif (BN_copy(A,a) == NULL) goto err;\n\tif (BN_copy(B,n) == NULL) goto err;\n\tsign=1;\n\n\twhile (!BN_is_zero(B))\n\t\t{\n\t\tif (!BN_div(D,M,A,B,ctx)) goto err;\n\t\tT=A;\n\t\tA=B;\n\t\tB=M;\n\t\t/* T has a struct, M does not */\n\n\t\tif (!BN_mul(T,D,X,ctx)) goto err;\n\t\tif (!BN_add(T,T,Y)) goto err;\n\t\tM=Y;\n\t\tY=X;\n\t\tX=T;\n\t\tsign= -sign;\n\t\t}\n\tif (sign < 0)\n\t\t{\n\t\tif (!BN_sub(Y,n,Y)) goto err;\n\t\t}\n\n\tif (BN_is_one(A))\n\t\t{ if (!BN_mod(R,Y,n,ctx)) goto err; }\n\telse\n\t\t{\n\t\tgoto err;\n\t\t}\n\tret=R;\nerr:\n\tif ((ret == NULL) && (in == NULL)) BN_free(R);\n\tBN_CTX_end(ctx);\n\treturn(ret);\n\t}\n\nint BN_set_bit(BIGNUM *a, int n)\n\t{\n\tint i,j,k;\n\n\ti=n/BN_BITS2;\n\tj=n%BN_BITS2;\n\tif (a->top <= i)\n\t\t{\n\t\tif (bn_wexpand(a,i+1) == NULL) return(0);\n\t\tfor(k=a->top; k<i+1; k++)\n\t\t\ta->d[k]=0;\n\t\ta->top=i+1;\n\t\t}\n\n\ta->d[i]|=(((BN_ULONG)1)<<j);\n\treturn(1);\n\t}\n\n"
  },
  {
    "path": "package/network/services/ead/src/tinysrp/t_conv.c",
    "content": "/*\n * Copyright (c) 1997-1999  The Stanford SRP Authentication Project\n * All Rights Reserved.\n *\n * Permission is hereby granted, free of charge, to any person obtaining\n * a copy of this software and associated documentation files (the\n * \"Software\"), to deal in the Software without restriction, including\n * without limitation the rights to use, copy, modify, merge, publish,\n * distribute, sublicense, and/or sell copies of the Software, and to\n * permit persons to whom the Software is furnished to do so, subject to\n * the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS-IS\" AND WITHOUT WARRANTY OF ANY KIND, \n * EXPRESS, IMPLIED OR OTHERWISE, INCLUDING WITHOUT LIMITATION, ANY \n * WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.  \n *\n * IN NO EVENT SHALL STANFORD BE LIABLE FOR ANY SPECIAL, INCIDENTAL,\n * INDIRECT OR CONSEQUENTIAL DAMAGES OF ANY KIND, OR ANY DAMAGES WHATSOEVER\n * RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER OR NOT ADVISED OF\n * THE POSSIBILITY OF DAMAGE, AND ON ANY THEORY OF LIABILITY, ARISING OUT\n * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n * In addition, the following conditions apply:\n *\n * 1. Any software that incorporates the SRP authentication technology\n *    must display the following acknowlegment:\n *    \"This product uses the 'Secure Remote Password' cryptographic\n *     authentication system developed by Tom Wu (tjw@CS.Stanford.EDU).\"\n *\n * 2. Any software that incorporates all or part of the SRP distribution\n *    itself must also display the following acknowledgment:\n *    \"This product includes software developed by Tom Wu and Eugene\n *     Jhong for the SRP Distribution (http://srp.stanford.edu/srp/).\"\n *\n * 3. Redistributions in source or binary form must retain an intact copy\n *    of this copyright notice and list of conditions.\n */\n\n/*#define _POSIX_SOURCE*/\n#include <stdio.h>\n#include \"t_defines.h\"\n\nstatic int\nhexDigitToInt(c)\n     char c;\n{\n  if(c >= '0' && c <= '9')\n    return c - '0';\n  else if(c >= 'a' && c <= 'f')\n    return c - 'a' + 10;\n  else if(c >= 'A' && c <= 'F')\n    return c - 'A' + 10;\n  else\n    return 0;\n}\n\n/*\n * Convert a hex string to a string of bytes; return size of dst\n */\n_TYPE( int )\nt_fromhex(dst, src)\n     register char *dst, *src;\n{\n  register char *chp = dst;\n  register unsigned size = strlen(src);\n\n  /* FIXME: handle whitespace and non-hex digits by setting size and src\n     appropriately. */\n\n  if(size % 2 == 1) {\n    *chp++ = hexDigitToInt(*src++);\n    --size;\n  }\n  while(size > 0) {\n    *chp++ = (hexDigitToInt(*src) << 4) | hexDigitToInt(*(src + 1));\n    src += 2;\n    size -= 2;\n  }\n  return chp - dst;\n}\n\n/*\n * Convert a string of bytes to their hex representation\n */\n_TYPE( char * )\nt_tohex(dst, src, size)\n     register char *dst, *src;\n     register unsigned size;\n{\n   int notleading = 0;\n\n   register char *chp = dst;\n   if (size != 0) do {\n      if(notleading || *src != '\\0') {\n\tnotleading = 1;\n\tsprintf(chp, \"%.2x\", * (unsigned char *) src);\n\tchp += 2;\n      }\n      ++src;\n   } while (--size != 0);\n   return dst;\n}\n\nstatic char b64table[] =\n  \"0123456789ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz./\";\n\n/*\n * Convert a base64 string into raw byte array representation.\n */\n_TYPE( int )\nt_fromb64(dst, src)\n     register char *dst, *src;\n{\n  unsigned char *a;\n  char *loc;\n  int i, j;\n  unsigned int size;\n\n  while(*src && (*src == ' ' || *src == '\\t' || *src == '\\n'))\n      ++src;\n  size = strlen(src);\n\n  a = malloc((size + 1) * sizeof(unsigned char));\n  if(a == (unsigned char *) 0)\n    return -1;\n\n  i = 0;\n  while(i < size) {\n    loc = strchr(b64table, src[i]);\n    if(loc == (char *) 0)\n      break;\n    else\n      a[i] = loc - b64table;\n    ++i;\n  }\n  size = i;\n\n  i = size - 1;\n  j = size;\n  while(1) {\n    a[j] = a[i];\n    if(--i < 0)\n      break;\n    a[j] |= (a[i] & 3) << 6;\n    --j;\n    a[j] = (unsigned char) ((a[i] & 0x3c) >> 2);\n    if(--i < 0)\n      break;\n    a[j] |= (a[i] & 0xf) << 4;\n    --j;\n    a[j] = (unsigned char) ((a[i] & 0x30) >> 4);\n    if(--i < 0)\n      break;\n    a[j] |= (a[i] << 2);\n\n    a[--j] = 0;\n    if(--i < 0)\n      break;\n  }\n\n  while(j <= size && a[j] == 0)\n    ++j;\n\n  memcpy(dst, a + j, size - j + 1);\n  free(a);\n  return size - j + 1;\n}\n\n/*\n * Convert a raw byte string into a null-terminated base64 ASCII string.\n */\n_TYPE( char * )\nt_tob64(dst, src, size)\n     register char *dst, *src;\n     register unsigned size;\n{\n  int c, pos = size % 3;\n  unsigned char b0 = 0, b1 = 0, b2 = 0, notleading = 0;\n  char *olddst = dst;\n\n  switch(pos) {\n  case 1:\n    b2 = src[0];\n    break;\n  case 2:\n    b1 = src[0];\n    b2 = src[1];\n    break;\n  }\n\n  while(1) {\n    c = (b0 & 0xfc) >> 2;\n    if(notleading || c != 0) {\n      *dst++ = b64table[c];\n      notleading = 1;\n    }\n    c = ((b0 & 3) << 4) | ((b1 & 0xf0) >> 4);\n    if(notleading || c != 0) {\n      *dst++ = b64table[c];\n      notleading = 1;\n    }\n    c = ((b1 & 0xf) << 2) | ((b2 & 0xc0) >> 6);\n    if(notleading || c != 0) {\n      *dst++ = b64table[c];\n      notleading = 1;\n    }\n    c = b2 & 0x3f;\n    if(notleading || c != 0) {\n      *dst++ = b64table[c];\n      notleading = 1;\n    }\n    if(pos >= size)\n      break;\n    else {\n      b0 = src[pos++];\n      b1 = src[pos++];\n      b2 = src[pos++];\n    }\n  }\n\n  *dst++ = '\\0';\n  return olddst;\n}\n"
  },
  {
    "path": "package/network/services/ead/src/tinysrp/t_defines.h",
    "content": "/*\n * Copyright (c) 1997-1999  The Stanford SRP Authentication Project\n * All Rights Reserved.\n *\n * Permission is hereby granted, free of charge, to any person obtaining\n * a copy of this software and associated documentation files (the\n * \"Software\"), to deal in the Software without restriction, including\n * without limitation the rights to use, copy, modify, merge, publish,\n * distribute, sublicense, and/or sell copies of the Software, and to\n * permit persons to whom the Software is furnished to do so, subject to\n * the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS-IS\" AND WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS, IMPLIED OR OTHERWISE, INCLUDING WITHOUT LIMITATION, ANY\n * WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.\n *\n * IN NO EVENT SHALL STANFORD BE LIABLE FOR ANY SPECIAL, INCIDENTAL,\n * INDIRECT OR CONSEQUENTIAL DAMAGES OF ANY KIND, OR ANY DAMAGES WHATSOEVER\n * RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER OR NOT ADVISED OF\n * THE POSSIBILITY OF DAMAGE, AND ON ANY THEORY OF LIABILITY, ARISING OUT\n * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n * In addition, the following conditions apply:\n *\n * 1. Any software that incorporates the SRP authentication technology\n *    must display the following acknowlegment:\n *    \"This product uses the 'Secure Remote Password' cryptographic\n *     authentication system developed by Tom Wu (tjw@CS.Stanford.EDU).\"\n *\n * 2. Any software that incorporates all or part of the SRP distribution\n *    itself must also display the following acknowledgment:\n *    \"This product includes software developed by Tom Wu and Eugene\n *     Jhong for the SRP Distribution (http://srp.stanford.edu/srp/).\"\n *\n * 3. Redistributions in source or binary form must retain an intact copy\n *    of this copyright notice and list of conditions.\n */\n\n#ifndef T_DEFINES_H\n#define T_DEFINES_H\n\n#ifndef P\n#if defined(__STDC__) || defined(__cplusplus)\n#define P(x) x\n#else\n#define P(x) ()\n#endif\n#endif\n\n#ifdef HAVE_CONFIG_H\n#include \"config.h\"\n#endif /* HAVE_CONFIG_H */\n\n#ifndef _DLLDECL\n#define _DLLDECL\n\n#ifdef MSVC15   /* MSVC1.5 support for 16 bit apps */\n#define _MSVC15EXPORT _export\n#define _MSVC20EXPORT\n#define _DLLAPI _export _pascal\n#define _TYPE(a) a _MSVC15EXPORT\n#define DLLEXPORT 1\n\n#elif MSVC20\n#define _MSVC15EXPORT\n#define _MSVC20EXPORT _declspec(dllexport)\n#define _DLLAPI\n#define _TYPE(a) _MSVC20EXPORT a\n#define DLLEXPORT 1\n\n#else                   /* Default, non-dll.  Use this for Unix or DOS */\n#define _MSVC15DEXPORT\n#define _MSVC20EXPORT\n#define _DLLAPI\n#define _TYPE(a) a\n#endif\n#endif\n\n#if STDC_HEADERS\n#include <stdlib.h>\n#include <string.h>\n#else /* not STDC_HEADERS */\n#ifndef HAVE_STRCHR\n#define strchr index\n#define strrchr rindex\n#endif\nchar *strchr(), *strrchr(), *strtok();\n#ifndef HAVE_MEMCPY\n#define memcpy(d, s, n) bcopy((s), (d), (n))\n#endif\n#endif /* not STDC_HEADERS */\n\n#include <sys/types.h>\n\n#if TIME_WITH_SYS_TIME\n#include <sys/time.h>\n#include <time.h>\n#else  /* not TIME_WITH_SYS_TIME */\n#if HAVE_SYS_TIME_H\n#include <sys/time.h>\n#else\n#include <time.h>\n#endif\n#endif /* not TIME_WITH_SYS_TIME */\n\n#if HAVE_TERMIOS_H\n#include <termios.h>\n#define STTY(fd, termio) tcsetattr(fd, TCSANOW, termio)\n#define GTTY(fd, termio) tcgetattr(fd, termio)\n#define TERMIO struct termios\n#define USE_TERMIOS\n#elif HAVE_TERMIO_H\n#include <sys/ioctl.h>\n#include <termio.h>\n#define STTY(fd, termio) ioctl(fd, TCSETA, termio)\n#define GTTY(fd, termio) ioctl(fd, TCGETA, termio)\n#define TEMRIO struct termio\n#define USE_TERMIO\n#elif HAVE_SGTTY_H\n#include <sgtty.h>\n#define STTY(fd, termio) stty(fd, termio)\n#define GTTY(fd, termio) gtty(fd, termio)\n#define TERMIO struct sgttyb\n#define USE_SGTTY\n#endif\n\n#ifdef USE_FTIME\n#include <sys/timeb.h>\n#endif\n\n#ifndef MATH_PRIV\ntypedef void * BigInteger;\n#endif\n\n_TYPE( BigInteger ) BigIntegerFromInt P((unsigned int number));\n_TYPE( BigInteger ) BigIntegerFromBytes P((unsigned char * bytes, int length));\n_TYPE( int ) BigIntegerToBytes P((BigInteger src, unsigned char * dest));\n_TYPE( int ) BigIntegerBitLen P((BigInteger b));\n_TYPE( int ) BigIntegerCmp P((BigInteger c1, BigInteger c2));\n_TYPE( int ) BigIntegerCmpInt P((BigInteger c1, unsigned int c2));\n_TYPE( void ) BigIntegerLShift P((BigInteger result, BigInteger x,\n\t\t\t\tunsigned int bits));\n_TYPE( void ) BigIntegerAdd P((BigInteger result, BigInteger a1, BigInteger a2));\n_TYPE( void ) BigIntegerAddInt P((BigInteger result,\n\t\t\t\tBigInteger a1, unsigned int a2));\n_TYPE( void ) BigIntegerSub P((BigInteger result, BigInteger s1, BigInteger s2));\n_TYPE( void ) BigIntegerSubInt P((BigInteger result,\n\t\t\t\tBigInteger s1, unsigned int s2));\n/* For BigIntegerMul{,Int}: result != m1, m2 */\n_TYPE( void ) BigIntegerMul P((BigInteger result, BigInteger m1, BigInteger m2));\n_TYPE( void ) BigIntegerMulInt P((BigInteger result,\n\t\t\t\tBigInteger m1, unsigned int m2));\n_TYPE( void ) BigIntegerDivInt P((BigInteger result,\n\t\t\t\tBigInteger d, unsigned int m));\n_TYPE( void ) BigIntegerMod P((BigInteger result, BigInteger d, BigInteger m));\n_TYPE( unsigned int ) BigIntegerModInt P((BigInteger d, unsigned int m));\n_TYPE( void ) BigIntegerModMul P((BigInteger result,\n\t\t\t\tBigInteger m1, BigInteger m2, BigInteger m));\n_TYPE( void ) BigIntegerModExp P((BigInteger result, BigInteger base,\n\t\t\t\tBigInteger expt, BigInteger modulus));\n_TYPE( void ) BigIntegerModExpInt P((BigInteger result, BigInteger base,\n\t\t\t\t   unsigned int expt, BigInteger modulus));\n_TYPE( int ) BigIntegerCheckPrime P((BigInteger n));\n_TYPE( void ) BigIntegerFree P((BigInteger b));\n\n#endif\n"
  },
  {
    "path": "package/network/services/ead/src/tinysrp/t_getconf.c",
    "content": "/*\n * Copyright (c) 1997-1999  The Stanford SRP Authentication Project\n * All Rights Reserved.\n *\n * Permission is hereby granted, free of charge, to any person obtaining\n * a copy of this software and associated documentation files (the\n * \"Software\"), to deal in the Software without restriction, including\n * without limitation the rights to use, copy, modify, merge, publish,\n * distribute, sublicense, and/or sell copies of the Software, and to\n * permit persons to whom the Software is furnished to do so, subject to\n * the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS-IS\" AND WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS, IMPLIED OR OTHERWISE, INCLUDING WITHOUT LIMITATION, ANY\n * WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.\n *\n * IN NO EVENT SHALL STANFORD BE LIABLE FOR ANY SPECIAL, INCIDENTAL,\n * INDIRECT OR CONSEQUENTIAL DAMAGES OF ANY KIND, OR ANY DAMAGES WHATSOEVER\n * RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER OR NOT ADVISED OF\n * THE POSSIBILITY OF DAMAGE, AND ON ANY THEORY OF LIABILITY, ARISING OUT\n * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n * In addition, the following conditions apply:\n *\n * 1. Any software that incorporates the SRP authentication technology\n *    must display the following acknowlegment:\n *    \"This product uses the 'Secure Remote Password' cryptographic\n *     authentication system developed by Tom Wu (tjw@CS.Stanford.EDU).\"\n *\n * 2. Any software that incorporates all or part of the SRP distribution\n *    itself must also display the following acknowledgment:\n *    \"This product includes software developed by Tom Wu and Eugene\n *     Jhong for the SRP Distribution (http://srp.stanford.edu/srp/).\"\n *\n * 3. Redistributions in source or binary form must retain an intact copy\n *    of this copyright notice and list of conditions.\n */\n\n#include <stdio.h>\n\n#include \"t_defines.h\"\n#include \"t_pwd.h\"\n#include \"t_read.h\"\n\n/* Master builtin parameter storage object.  The default that tphrase\nuses is the last one. */\n\nstatic struct pre_struct {\n  struct t_preconf preconf;\n  int state;    /* 0 == uninitialized/first time */\n  unsigned char modbuf[MAXPARAMLEN];\n  unsigned char genbuf[MAXPARAMLEN];\n} pre_params[] = {\n  { { \"2iQzj1CagQc/5ctbuJYLWlhtAsPHc7xWVyCPAKFRLWKADpASkqe9djWPFWTNTdeJtL8nAhImCn3Sr/IAdQ1FrGw0WvQUstPx3FO9KNcXOwisOQ1VlL.gheAHYfbYyBaxXL.NcJx9TUwgWDT0hRzFzqSrdGGTN3FgSTA1v4QnHtEygNj3eZ.u0MThqWUaDiP87nqha7XnT66bkTCkQ8.7T8L4KZjIImrNrUftedTTBi.WCi.zlrBxDuOM0da0JbUkQlXqvp0yvJAPpC11nxmmZOAbQOywZGmu9nhZNuwTlxjfIro0FOdthaDTuZRL9VL7MRPUDo/DQEyW.d4H.UIlzp\",\n      \"2\",\n      NULL }, 0 },\n  { { \"dUyyhxav9tgnyIg65wHxkzkb7VIPh4o0lkwfOKiPp4rVJrzLRYVBtb76gKlaO7ef5LYGEw3G.4E0jbMxcYBetDy2YdpiP/3GWJInoBbvYHIRO9uBuxgsFKTKWu7RnR7yTau/IrFTdQ4LY/q.AvoCzMxV0PKvD9Odso/LFIItn8PbTov3VMn/ZEH2SqhtpBUkWtmcIkEflhX/YY/fkBKfBbe27/zUaKUUZEUYZ2H2nlCL60.JIPeZJSzsu/xHDVcx\",\n      \"2\",\n      NULL }, 0 },\n  { { \"3NUKQ2Re4P5BEK0TLg2dX3gETNNNECPoe92h4OVMaDn3Xo/0QdjgG/EvM.hiVV1BdIGklSI14HA38Mpe5k04juR5/EXMU0r1WtsLhNXwKBlf2zEfoOh0zVmDvqInpU695f29Iy7sNW3U5RIogcs740oUp2Kdv5wuITwnIx84cnO.e467/IV1lPnvMCr0pd1dgS0a.RV5eBJr03Q65Xy61R\",\n      \"2\",\n      NULL }, 0 },\n  { { \"F//////////oG/QeY5emZJ4ncABWDmSqIa2JWYAPynq0Wk.fZiJco9HIWXvZZG4tU.L6RFDEaCRC2iARV9V53TFuJLjRL72HUI5jNPYNdx6z4n2wQOtxMiB/rosz0QtxUuuQ/jQYP.bhfya4NnB7.P9A6PHxEPJWV//////////\",\n      \"5\",\n      \"oakley prime 2\" }, 0 },\n  { { \"Ewl2hcjiutMd3Fu2lgFnUXWSc67TVyy2vwYCKoS9MLsrdJVT9RgWTCuEqWJrfB6uE3LsE9GkOlaZabS7M29sj5TnzUqOLJMjiwEzArfiLr9WbMRANlF68N5AVLcPWvNx6Zjl3m5Scp0BzJBz9TkgfhzKJZ.WtP3Mv/67I/0wmRZ\",\n      \"2\",\n      NULL }, 0 },\n};\n\n_TYPE( int )\nt_getprecount()\n{\n  return (sizeof(pre_params) / sizeof(struct pre_struct));\n}\n\nstatic struct t_confent sysconf;\n\n/* id is index origin 1 */\n\n_TYPE( struct t_confent * )\ngettcid\n(id)\n     int id;\n{\n\tstruct t_preconf *tcp;\n\n\tif (id <= 0 || id > t_getprecount()) {\n\t\treturn NULL;\n\t}\n\ttcp = t_getpreparam(id - 1);\n\tsysconf.index = id;\n\tsysconf.modulus = tcp->modulus;\n\tsysconf.generator = tcp->generator;\n\n\treturn &sysconf;\n}\n\n_TYPE( struct t_preconf * )\nt_getpreparam(idx)\n     int idx;\n{\n  if(pre_params[idx].state == 0) {\n    /* Wire up storage */\n    pre_params[idx].preconf.modulus.data = pre_params[idx].modbuf;\n    pre_params[idx].preconf.generator.data = pre_params[idx].genbuf;\n\n    /* Convert from b64 to t_num */\n    pre_params[idx].preconf.modulus.len = t_fromb64(pre_params[idx].preconf.modulus.data, pre_params[idx].preconf.mod_b64);\n    pre_params[idx].preconf.generator.len = t_fromb64(pre_params[idx].preconf.generator.data, pre_params[idx].preconf.gen_b64);\n\n    pre_params[idx].state = 1;\n  }\n  return &(pre_params[idx].preconf);\n}\n"
  },
  {
    "path": "package/network/services/ead/src/tinysrp/t_getpass.c",
    "content": "/*\n * Copyright 1990 - 1995, Julianne Frances Haugh\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. Neither the name of Julianne F. Haugh nor the names of its contributors\n *    may be used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY JULIE HAUGH AND CONTRIBUTORS ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED.  IN NO EVENT SHALL JULIE HAUGH OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n */\n\n#include \"t_defines.h\"\n#ifdef _WIN32\n#include <windows.h>\n#include <io.h>\n#endif /* _WIN32 */\n#ifdef HAVE_UNISTD_H\n#include <unistd.h>\n#endif /* HAVE_UNISTD_H */\n#include <signal.h>\n#include <stdio.h>\n\nstatic  int     sig_caught;\n#ifdef HAVE_SIGACTION\nstatic  struct  sigaction sigact;\n#endif\n\n/*ARGSUSED*/\nstatic RETSIGTYPE\nsig_catch (sig)\nint     sig;\n{\n\tsig_caught = 1;\n}\n\n_TYPE( int )\nt_getpass (buf, maxlen, prompt)\n\tchar *buf;\n\tunsigned maxlen;\n\tconst char *prompt;\n{\n\tchar    *cp;\n#ifdef _WIN32\n    HANDLE handle = (HANDLE) _get_osfhandle(_fileno(stdin));\n    DWORD  mode;\n\n    GetConsoleMode( handle, &mode );\n    SetConsoleMode( handle, mode & ~ENABLE_ECHO_INPUT );\n\n    if(fputs(prompt, stdout) == EOF ||\n\tfgets(buf, maxlen, stdin) == NULL) {\n\tSetConsoleMode(handle,mode);\n\treturn -1;\n    }\n    cp = buf + strlen(buf) - 1;\n    if ( *cp == 0x0a )\n\t*cp = '\\0';\n    printf(\"\\n\");\n    SetConsoleMode(handle,mode);\n#else\n\tFILE    *fp;\n\tint     tty_opened = 0;\n\n#ifdef HAVE_SIGACTION\n\tstruct  sigaction old_sigact;\n#else\n\tRETSIGTYPE      (*old_signal)();\n#endif\n\tTERMIO  new_modes;\n\tTERMIO  old_modes;\n\n\t/*\n\t * set a flag so the SIGINT signal can be re-sent if it\n\t * is caught\n\t */\n\n\tsig_caught = 0;\n\n\t/*\n\t * if /dev/tty can't be opened, getpass() needs to read\n\t * from stdin instead.\n\t */\n\n\tif ((fp = fopen (\"/dev/tty\", \"r\")) == 0) {\n\t\tfp = stdin;\n\t\tsetbuf (fp, (char *) 0);\n\t} else {\n\t\ttty_opened = 1;\n\t}\n\n\t/*\n\t * the current tty modes must be saved so they can be\n\t * restored later on.  echo will be turned off, except\n\t * for the newline character (BSD has to punt on this)\n\t */\n\n\tif (GTTY (fileno (fp), &new_modes))\n\t\treturn -1;\n\n\told_modes = new_modes;\n\n#ifdef HAVE_SIGACTION\n\tsigact.sa_handler = sig_catch;\n\t(void) sigaction (SIGINT, &sigact, &old_sigact);\n#else\n\told_signal = signal (SIGINT, sig_catch);\n#endif\n\n#ifdef USE_SGTTY\n\tnew_modes.sg_flags &= ~ECHO;\n#else\n\tnew_modes.c_iflag &= ~IGNCR;\n\tnew_modes.c_iflag |= ICRNL;\n\tnew_modes.c_oflag |= OPOST|ONLCR;\n\tnew_modes.c_lflag &= ~(ECHO|ECHOE|ECHOK);\n\tnew_modes.c_lflag |= ICANON|ECHONL;\n#endif\n\n\tif (STTY (fileno (fp), &new_modes))\n\t\tgoto out;\n\n\t/*\n\t * the prompt is output, and the response read without\n\t * echoing.  the trailing newline must be removed.  if\n\t * the fgets() returns an error, a NULL pointer is\n\t * returned.\n\t */\n\n\tif (fputs (prompt, stdout) == EOF)\n\t\tgoto out;\n\n\t(void) fflush (stdout);\n\n\tif (fgets (buf, maxlen, fp) == buf) {\n\t\tif ((cp = strchr (buf, '\\n')))\n\t\t\t*cp = '\\0';\n\t\telse\n\t\t\tbuf[maxlen - 1] = '\\0';\n\n#ifdef USE_SGTTY\n\t\tputc ('\\n', stdout);\n#endif\n\t}\n\telse buf[0] = '\\0';\nout:\n\t/*\n\t * the old SIGINT handler is restored after the tty\n\t * modes.  then /dev/tty is closed if it was opened in\n\t * the beginning.  finally, if a signal was caught it\n\t * is sent to this process for normal processing.\n\t */\n\n\tif (STTY (fileno (fp), &old_modes))\n\t{ memset (buf, 0, maxlen); return -1; }\n\n#ifdef HAVE_SIGACTION\n\t(void) sigaction (SIGINT, &old_sigact, NULL);\n#else\n\t(void) signal (SIGINT, old_signal);\n#endif\n\n\tif (tty_opened)\n\t\t(void) fclose (fp);\n\n\tif (sig_caught) {\n\t\tkill (getpid (), SIGINT);\n\t\tmemset (buf, 0, maxlen);\n\t\treturn -1;\n\t}\n#endif\n\n\treturn 0;\n}\n"
  },
  {
    "path": "package/network/services/ead/src/tinysrp/t_math.c",
    "content": "/*\n * Copyright (c) 1997-1999  The Stanford SRP Authentication Project\n * All Rights Reserved.\n *\n * Permission is hereby granted, free of charge, to any person obtaining\n * a copy of this software and associated documentation files (the\n * \"Software\"), to deal in the Software without restriction, including\n * without limitation the rights to use, copy, modify, merge, publish,\n * distribute, sublicense, and/or sell copies of the Software, and to\n * permit persons to whom the Software is furnished to do so, subject to\n * the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS-IS\" AND WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS, IMPLIED OR OTHERWISE, INCLUDING WITHOUT LIMITATION, ANY\n * WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.\n *\n * IN NO EVENT SHALL STANFORD BE LIABLE FOR ANY SPECIAL, INCIDENTAL,\n * INDIRECT OR CONSEQUENTIAL DAMAGES OF ANY KIND, OR ANY DAMAGES WHATSOEVER\n * RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER OR NOT ADVISED OF\n * THE POSSIBILITY OF DAMAGE, AND ON ANY THEORY OF LIABILITY, ARISING OUT\n * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n * In addition, the following conditions apply:\n *\n * 1. Any software that incorporates the SRP authentication technology\n *    must display the following acknowlegment:\n *    \"This product uses the 'Secure Remote Password' cryptographic\n *     authentication system developed by Tom Wu (tjw@CS.Stanford.EDU).\"\n *\n * 2. Any software that incorporates all or part of the SRP distribution\n *    itself must also display the following acknowledgment:\n *    \"This product includes software developed by Tom Wu and Eugene\n *     Jhong for the SRP Distribution (http://srp.stanford.edu/srp/).\"\n *\n * 3. Redistributions in source or binary form must retain an intact copy\n *    of this copyright notice and list of conditions.\n */\n\n#include <stdio.h>\n#include <sys/types.h>\n\n#include \"config.h\"\n\n#include \"bn.h\"\ntypedef BIGNUM * BigInteger;\n#define MATH_PRIV\n\n#include \"t_defines.h\"\n#include \"t_pwd.h\"\n\n/* Math library interface stubs */\n\nBigInteger\nBigIntegerFromInt(n)\n     unsigned int n;\n{\n  BIGNUM * a = BN_new();\n  BN_set_word(a, n);\n  return a;\n}\n\nBigInteger\nBigIntegerFromBytes(bytes, length)\n     unsigned char * bytes;\n     int length;\n{\n  BIGNUM * a = BN_new();\n  BN_bin2bn(bytes, length, a);\n  return a;\n}\n\nint\nBigIntegerToBytes(src, dest)\n     BigInteger src;\n     unsigned char * dest;\n{\n  return BN_bn2bin(src, dest);\n}\n\nint\nBigIntegerCmp(c1, c2)\n     BigInteger c1, c2;\n{\n  return BN_cmp(c1, c2);\n}\n\nint\nBigIntegerCmpInt(c1, c2)\n     BigInteger c1;\n     unsigned int c2;\n{\n  BIGNUM * a = BN_new();\n  int rv;\n  BN_set_word(a, c2);\n  rv = BN_cmp(c1, a);\n  BN_free(a);\n  return rv;\n}\n\nvoid\nBigIntegerAdd(result, a1, a2)\n     BigInteger result, a1, a2;\n{\n  BN_add(result, a1, a2);\n}\n\nvoid\nBigIntegerAddInt(result, a1, a2)\n     BigInteger result, a1;\n     unsigned int a2;\n{\n  BIGNUM * a = BN_new();\n  BN_set_word(a, a2);\n  BN_add(result, a1, a);\n  BN_free(a);\n}\n\nvoid\nBigIntegerSub(result, s1, s2)\n     BigInteger result, s1, s2;\n{\n  BN_sub(result, s1, s2);\n}\n\nvoid\nBigIntegerMulInt(result, m1, m2)\n     BigInteger result, m1;\n     unsigned int m2;\n{\n  BN_CTX * ctx = BN_CTX_new();\n  BIGNUM * m = BN_new();\n  BN_set_word(m, m2);\n  BN_mul(result, m1, m, ctx);\n  BN_CTX_free(ctx);\n}\n\nvoid\nBigIntegerModMul(r, m1, m2, modulus)\n     BigInteger r, m1, m2, modulus;\n{\n  BN_CTX * ctx = BN_CTX_new();\n  BN_mod_mul(r, m1, m2, modulus, ctx);\n  BN_CTX_free(ctx);\n}\n\nvoid\nBigIntegerModExp(r, b, e, m)\n     BigInteger r, b, e, m;\n{\n  BN_CTX * ctx = BN_CTX_new();\n  BN_mod_exp(r, b, e, m, ctx);\n  BN_CTX_free(ctx);\n}\n\nvoid\nBigIntegerModExpInt(r, b, e, m)\n     BigInteger r, b;\n     unsigned int e;\n     BigInteger m;\n{\n  BN_CTX * ctx = BN_CTX_new();\n  BIGNUM * p = BN_new();\n  BN_set_word(p, e);\n  BN_mod_exp(r, b, p, m, ctx);\n  BN_free(p);\n  BN_CTX_free(ctx);\n}\n\nvoid\nBigIntegerFree(b)\n     BigInteger b;\n{\n  BN_free(b);\n}\n"
  },
  {
    "path": "package/network/services/ead/src/tinysrp/t_misc.c",
    "content": "/*\n * Copyright (c) 1997-1999  The Stanford SRP Authentication Project\n * All Rights Reserved.\n *\n * Permission is hereby granted, free of charge, to any person obtaining\n * a copy of this software and associated documentation files (the\n * \"Software\"), to deal in the Software without restriction, including\n * without limitation the rights to use, copy, modify, merge, publish,\n * distribute, sublicense, and/or sell copies of the Software, and to\n * permit persons to whom the Software is furnished to do so, subject to\n * the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS-IS\" AND WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS, IMPLIED OR OTHERWISE, INCLUDING WITHOUT LIMITATION, ANY\n * WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.\n *\n * IN NO EVENT SHALL STANFORD BE LIABLE FOR ANY SPECIAL, INCIDENTAL,\n * INDIRECT OR CONSEQUENTIAL DAMAGES OF ANY KIND, OR ANY DAMAGES WHATSOEVER\n * RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER OR NOT ADVISED OF\n * THE POSSIBILITY OF DAMAGE, AND ON ANY THEORY OF LIABILITY, ARISING OUT\n * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n * In addition, the following conditions apply:\n *\n * 1. Any software that incorporates the SRP authentication technology\n *    must display the following acknowlegment:\n *    \"This product uses the 'Secure Remote Password' cryptographic\n *     authentication system developed by Tom Wu (tjw@CS.Stanford.EDU).\"\n *\n * 2. Any software that incorporates all or part of the SRP distribution\n *    itself must also display the following acknowledgment:\n *    \"This product includes software developed by Tom Wu and Eugene\n *     Jhong for the SRP Distribution (http://srp.stanford.edu/srp/).\"\n *\n * 3. Redistributions in source or binary form must retain an intact copy\n *    of this copyright notice and list of conditions.\n */\n\n#include \"t_defines.h\"\n\n#ifdef HAVE_UNISTD_H\n#include <unistd.h>\n#endif /* HAVE_UNISTD_H */\n\n#include <stdio.h>\n#include <sys/types.h>\n#include <sys/stat.h>\n#include <fcntl.h>\n\n#include \"t_sha.h\"\n\n#ifndef NULL\n#define NULL 0\n#endif\n\nstatic unsigned char randpool[SHA_DIGESTSIZE], randout[SHA_DIGESTSIZE];\nstatic unsigned long randcnt = 0;\nstatic unsigned int outpos = 0;\nSHA1_CTX randctxt;\n\n/*\n * t_envhash - Generate a 160-bit SHA hash of the environment\n *\n * This routine performs an SHA hash of all the \"name=value\" pairs\n * in the environment concatenated together and dumps them in the\n * output.  While it is true that anyone on the system can see\n * your environment, someone not on the system will have a very\n * difficult time guessing it, especially since some systems play\n * tricks with variable ordering and sometimes define quirky\n * environment variables like $WINDOWID or $_.\n */\nextern char ** environ;\n\nstatic void\nt_envhash(out)\n     unsigned char * out;\n{\n  char ** ptr;\n  char ebuf[256];\n  SHA1_CTX ctxt;\n\n  SHA1Init(&ctxt);\n  for(ptr = environ; *ptr; ++ptr) {\n    strncpy(ebuf, *ptr, 255);\n    ebuf[255] = '\\0';\n    SHA1Update(&ctxt, ebuf, strlen(ebuf));\n  }\n  SHA1Final(out, &ctxt);\n}\n\n/*\n * t_fshash - Generate a 160-bit SHA hash from the file system\n *\n * This routine climbs up the directory tree from the current\n * directory, running stat() on each directory until it hits the\n * root directory.  This information is sensitive to the last\n * access/modification times of all the directories above you,\n * so someone who lists one of those directories injects some\n * entropy into the system.  Obviously, this hash is very sensitive\n * to your current directory when the program is run.\n *\n * For good measure, it also performs an fstat on the standard input,\n * usually your tty, throws that into the buffer, creates a file in\n * /tmp (the inode is unpredictable on a busy system), and runs stat()\n * on that before deleting it.\n *\n * The entire buffer is run once through SHA to obtain the final result.\n */\nstatic void\nt_fshash(out)\n     unsigned char * out;\n{\n  char dotpath[128];\n  struct stat st;\n  SHA1_CTX ctxt;\n  int i, pinode;\n  dev_t pdev;\n\n  SHA1Init(&ctxt);\n  if(stat(\".\", &st) >= 0) {\n    SHA1Update(&ctxt, (unsigned char *) &st, sizeof(st));\n    pinode = st.st_ino;\n    pdev = st.st_dev;\n    strcpy(dotpath, \"..\");\n    for(i = 0; i < 40; ++i) {\n      if(stat(dotpath, &st) < 0)\n\tbreak;\n      if(st.st_ino == pinode && st.st_dev == pdev)\n\tbreak;\n      SHA1Update(&ctxt, (unsigned char *) &st, sizeof(st));\n      pinode = st.st_ino;\n      pdev = st.st_dev;\n      strcat(dotpath, \"/..\");\n    }\n  }\n\n  if(fstat(0, &st) >= 0)\n    SHA1Update(&ctxt, (unsigned char *) &st, sizeof(st));\n\n  sprintf(dotpath, \"/tmp/rnd.%d\", getpid());\n  if(creat(dotpath, 0600) >= 0 && stat(dotpath, &st) >= 0)\n    SHA1Update(&ctxt, (unsigned char *) &st, sizeof(st));\n  unlink(dotpath);\n\n  SHA1Final(out, &ctxt);\n}\n\n/*\n * Generate a high-entropy seed for the strong random number generator.\n * This uses a wide variety of quickly gathered and somewhat unpredictable\n * system information.  The 'preseed' structure is assembled from:\n *\n *   The system time in seconds\n *   The system time in microseconds\n *   The current process ID\n *   The parent process ID\n *   A hash of the user's environment\n *   A hash gathered from the file system\n *   Input from a random device, if available\n *   Timings of system interrupts\n *\n * The entire structure (60 bytes on most systems) is fed to SHA to produce\n * a 160-bit seed for the strong random number generator.  It is believed\n * that in the worst case (on a quiet system with no random device versus\n * an attacker who has access to the system already), the seed contains at\n * least about 80 bits of entropy.  Versus an attacker who does not have\n * access to the system, the entropy should be slightly over 128 bits.\n */\nstatic char initialized = 0;\n\nstatic struct {\n  unsigned int trand1;\n  time_t sec;\n  time_t usec;\n  short pid;\n  short ppid;\n  unsigned char envh[SHA_DIGESTSIZE];\n  unsigned char fsh[SHA_DIGESTSIZE];\n  unsigned char devrand[20];\n  unsigned int trand2;\n} preseed;\n\nunsigned long raw_truerand();\n\nvoid\nt_initrand()\n{\n  SHA1_CTX ctxt;\n#ifdef USE_FTIME\n  struct timeb t;\n#else\n  struct timeval t;\n#endif\n  int i, r=0;\n\n  if(initialized)\n    return;\n\n  initialized = 1;\n\n  i = open(\"/dev/urandom\", O_RDONLY);\n  if(i > 0) {\n    r += read(i, preseed.devrand, sizeof(preseed.devrand));\n    close(i);\n  }\n\n  /* Resort to truerand only if desperate for some Real entropy */\n  if(r == 0)\n    preseed.trand1 = raw_truerand();\n\n#ifdef USE_FTIME\n  ftime(&t);\n#else\n  gettimeofday(&t, NULL);\n#endif\n\n#ifdef USE_FTIME\n  preseed.sec = t.time;\n  preseed.usec = t.millitm;\n#else\n  preseed.sec = t.tv_sec;\n  preseed.usec = t.tv_usec;\n#endif\n  preseed.pid = getpid();\n  preseed.ppid = getppid();\n  t_envhash(preseed.envh);\n  t_fshash(preseed.fsh);\n\n  if(r == 0)\n    preseed.trand2 = raw_truerand();\n\n  SHA1Init(&ctxt);\n  SHA1Update(&ctxt, (unsigned char *) &preseed, sizeof(preseed));\n  SHA1Final(randpool, &ctxt);\n  outpos = 0;\n  memset((unsigned char *) &preseed, 0, sizeof(preseed));\n  memset((unsigned char *) &ctxt, 0, sizeof(ctxt));\n}\n\n#define NUM_RANDOMS 12\n\n/*\n * The strong random number generator.  This uses a 160-bit seed\n * and uses SHA-1 in a feedback configuration to generate successive\n * outputs.  If S[0] is set to the initial seed, then:\n *\n *         S[i+1] = SHA-1(i || S[i])\n *         A[i] = SHA-1(S[i])\n *\n * where the A[i] are the output blocks starting with i=0.\n * Each cycle generates 20 bytes of new output.\n */\n_TYPE( void )\nt_random(data, size)\n     unsigned char * data;\n     unsigned size;\n{\n  if(!initialized)\n    t_initrand();\n\n  if(size <= 0)         /* t_random(NULL, 0) forces seed initialization */\n    return;\n\n  while(size > outpos) {\n    if(outpos > 0) {\n      memcpy(data, randout + (sizeof(randout) - outpos), outpos);\n      data += outpos;\n      size -= outpos;\n    }\n\n    /* Recycle */\n    SHA1Init(&randctxt);\n    SHA1Update(&randctxt, randpool, sizeof(randpool));\n    SHA1Final(randout, &randctxt);\n    SHA1Init(&randctxt);\n    SHA1Update(&randctxt, (unsigned char *) &randcnt, sizeof(randcnt));\n    SHA1Update(&randctxt, randpool, sizeof(randpool));\n    SHA1Final(randpool, &randctxt);\n    ++randcnt;\n    outpos = sizeof(randout);\n  }\n\n  if(size > 0) {\n    memcpy(data, randout + (sizeof(randout) - outpos), size);\n    outpos -= size;\n  }\n}\n\n/*\n * The interleaved session-key hash.  This separates the even and the odd\n * bytes of the input (ignoring the first byte if the input length is odd),\n * hashes them separately, and re-interleaves the two outputs to form a\n * single 320-bit value.\n */\n_TYPE( unsigned char * )\nt_sessionkey(key, sk, sklen)\n     unsigned char * key;\n     unsigned char * sk;\n     unsigned sklen;\n{\n  unsigned i, klen;\n  unsigned char * hbuf;\n  unsigned char hout[SHA_DIGESTSIZE];\n  SHA1_CTX ctxt;\n\n  while(sklen > 0 && *sk == 0) {        /* Skip leading 0's */\n    --sklen;\n    ++sk;\n  }\n\n  klen = sklen / 2;\n  if((hbuf = malloc(klen * sizeof(char))) == 0)\n    return 0;\n\n  for(i = 0; i < klen; ++i)\n    hbuf[i] = sk[sklen - 2 * i - 1];\n  SHA1Init(&ctxt);\n  SHA1Update(&ctxt, hbuf, klen);\n  SHA1Final(hout, &ctxt);\n  for(i = 0; i < sizeof(hout); ++i)\n    key[2 * i] = hout[i];\n\n  for(i = 0; i < klen; ++i)\n    hbuf[i] = sk[sklen - 2 * i - 2];\n  SHA1Init(&ctxt);\n  SHA1Update(&ctxt, hbuf, klen);\n  SHA1Final(hout, &ctxt);\n  for(i = 0; i < sizeof(hout); ++i)\n    key[2 * i + 1] = hout[i];\n\n  memset(hout, 0, sizeof(hout));\n  memset(hbuf, 0, klen);\n  free(hbuf);\n  return key;\n}\n"
  },
  {
    "path": "package/network/services/ead/src/tinysrp/t_pw.c",
    "content": "/*\n * Copyright (c) 1997-2000  The Stanford SRP Authentication Project\n * All Rights Reserved.\n *\n * Permission is hereby granted, free of charge, to any person obtaining\n * a copy of this software and associated documentation files (the\n * \"Software\"), to deal in the Software without restriction, including\n * without limitation the rights to use, copy, modify, merge, publish,\n * distribute, sublicense, and/or sell copies of the Software, and to\n * permit persons to whom the Software is furnished to do so, subject to\n * the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS-IS\" AND WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS, IMPLIED OR OTHERWISE, INCLUDING WITHOUT LIMITATION, ANY\n * WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.\n *\n * IN NO EVENT SHALL STANFORD BE LIABLE FOR ANY SPECIAL, INCIDENTAL,\n * INDIRECT OR CONSEQUENTIAL DAMAGES OF ANY KIND, OR ANY DAMAGES WHATSOEVER\n * RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER OR NOT ADVISED OF\n * THE POSSIBILITY OF DAMAGE, AND ON ANY THEORY OF LIABILITY, ARISING OUT\n * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n * In addition, the following conditions apply:\n *\n * 1. Any software that incorporates the SRP authentication technology\n *    must display the following acknowlegment:\n *    \"This product uses the 'Secure Remote Password' cryptographic\n *     authentication system developed by Tom Wu (tjw@CS.Stanford.EDU).\"\n *\n * 2. Any software that incorporates all or part of the SRP distribution\n *    itself must also display the following acknowledgment:\n *    \"This product includes software developed by Tom Wu and Eugene\n *     Jhong for the SRP Distribution (http://srp.stanford.edu/srp/).\"\n *\n * 3. Redistributions in source or binary form must retain an intact copy\n *    of this copyright notice and list of conditions.\n */\n\n#include \"t_defines.h\"\n\n#ifdef HAVE_UNISTD_H\n#include <unistd.h>\n#endif /* HAVE_UNISTD_H */\n\n#include <stdio.h>\n#include <sys/types.h>\n#include <sys/stat.h>\n#ifdef USE_HOMEDIR\n#include <pwd.h>\n#endif\n#ifdef WIN32\n#include <io.h>\n#endif\n\n#include \"t_pwd.h\"\n#include \"t_read.h\"\n#include \"t_sha.h\"\n#include \"t_server.h\"\n\nstatic struct t_pw * syspw = NULL;\nstatic struct t_passwd tpass;\n\n_TYPE( struct t_server * )\nt_serveropen(username)\n     const char * username;\n{\n  struct t_passwd * p;\n  p = gettpnam(username);\n  if(p == NULL) {\n    return NULL;\n  } else {\n    return t_serveropenraw(&p->tp, &p->tc);\n  }\n}\n\n\n/* t_openpw(NULL) is deprecated - use settpent()/gettpnam() instead */\n\n_TYPE( struct t_pw * )\nt_openpw(fp)\n     FILE * fp;\n{\n  struct t_pw * tpw;\n  char close_flag = 0;\n\n  if(fp == NULL) { /* Deprecated */\n    if((fp = fopen(DEFAULT_PASSWD, \"r\")) == NULL)\n      return NULL;\n    close_flag = 1;\n  }\n  else\n    close_flag = 0;\n\n  if((tpw = malloc(sizeof(struct t_pw))) == NULL) {\n    fclose(fp);\n    return NULL;\n  }\n  tpw->instream = fp;\n  tpw->close_on_exit = close_flag;\n  tpw->state = FILE_ONLY;\n\n  return tpw;\n}\n\n_TYPE( struct t_pw * )\nt_openpwbyname(pwname)\n     const char * pwname;\n{\n  FILE * fp;\n  struct t_pw * t;\n\n  if(pwname == NULL)            /* Deprecated */\n    return t_openpw(NULL);\n\n  if((fp = fopen(pwname, \"r\")) == NULL)\n    return NULL;\n\n  t = t_openpw(fp);\n  t->close_on_exit = 1;\n  return t;\n}\n\n_TYPE( void )\nt_closepw(tpw)\n     struct t_pw * tpw;\n{\n  if(tpw->close_on_exit)\n    fclose(tpw->instream);\n  free(tpw);\n}\n\n_TYPE( void )\nt_rewindpw(tpw)\n     struct t_pw * tpw;\n{\n#ifdef ENABLE_YP\n  if(tpw->state == IN_NIS)\n    tpw->state = FILE_NIS;\n#endif\n  rewind(tpw->instream);\n}\n\n#ifdef ENABLE_YP\nstatic void\nsavepwent(tpw, pwent)\n     struct t_pw * tpw;\n     struct t_pwent *pwent;\n{\n  tpw->pebuf.name = tpw->userbuf;\n  tpw->pebuf.password.data = tpw->pwbuf;\n  tpw->pebuf.salt.data = tpw->saltbuf;\n  strcpy(tpw->pebuf.name, pwent->name);\n  tpw->pebuf.password.len = pwent->password.len;\n  memcpy(tpw->pebuf.password.data, pwent->password.data, pwent->password.len);\n  tpw->pebuf.salt.len = pwent->salt.len;\n  memcpy(tpw->pebuf.salt.data, pwent->salt.data, pwent->salt.len);\n  tpw->pebuf.index = pwent->index;\n}\n#endif /* ENABLE_YP */\n\n_TYPE( struct t_pwent * )\nt_getpwbyname(tpw, user)\n     struct t_pw * tpw;\n     const char * user;\n{\n  char indexbuf[16];\n  char passbuf[MAXB64PARAMLEN];\n  char saltstr[MAXB64SALTLEN];\n  char username[MAXUSERLEN];\n#ifdef ENABLE_YP\n  struct t_passwd * nisent;\n#endif\n\n  t_rewindpw(tpw);\n\n  while(t_nextfield(tpw->instream, username, MAXUSERLEN) > 0) {\n#ifdef ENABLE_YP\n    if(tpw->state == FILE_NIS && *username == '+') {\n      if(strlen(username) == 1 || strcmp(user, username+1) == 0) {\n\tnisent = _yp_gettpnam(user);    /* Entry is +username or + */\n\tif(nisent != NULL) {\n\t  savepwent(tpw, &nisent->tp);\n\t  return &tpw->pebuf;\n\t}\n      }\n    }\n#endif\n    if(strcmp(user, username) == 0)\n      if(t_nextfield(tpw->instream, passbuf, MAXB64PARAMLEN) > 0 &&\n\t (tpw->pebuf.password.len = t_fromb64(tpw->pwbuf, passbuf)) > 0 &&\n\t t_nextfield(tpw->instream, saltstr, MAXB64SALTLEN) > 0 &&\n\t (tpw->pebuf.salt.len = t_fromb64(tpw->saltbuf, saltstr)) > 0 &&\n\t t_nextfield(tpw->instream, indexbuf, 16) > 0 &&\n\t (tpw->pebuf.index = atoi(indexbuf)) > 0) {\n\tstrcpy(tpw->userbuf, username);\n\ttpw->pebuf.name = tpw->userbuf;\n\ttpw->pebuf.password.data = tpw->pwbuf;\n\ttpw->pebuf.salt.data = tpw->saltbuf;\n\tt_nextline(tpw->instream);\n\treturn &tpw->pebuf;\n      }\n    if(t_nextline(tpw->instream) < 0)\n      return NULL;\n  }\n  return NULL;\n}\n\n/* System password file accessors */\n\nstatic int\npwinit()\n{\n  if(syspw == NULL) {\n    if((syspw = t_openpwbyname(DEFAULT_PASSWD)) == NULL)\n      return -1;\n    syspw->state = FILE_NIS;\n  }\n  return 0;\n}\n\nstatic void\npwsetup(out, tpwd, tcnf)\n     struct t_passwd * out;\n     struct t_pwent * tpwd;\n     struct t_confent * tcnf;\n{\n  out->tp.name = tpwd->name;\n  out->tp.password.len = tpwd->password.len;\n  out->tp.password.data = tpwd->password.data;\n  out->tp.salt.len = tpwd->salt.len;\n  out->tp.salt.data = tpwd->salt.data;\n  out->tp.index = tpwd->index;\n\n  out->tc.index = tcnf->index;\n  out->tc.modulus.len = tcnf->modulus.len;\n  out->tc.modulus.data = tcnf->modulus.data;\n  out->tc.generator.len = tcnf->generator.len;\n  out->tc.generator.data = tcnf->generator.data;\n}\n\n_TYPE( struct t_passwd * )\ngettpnam\n(user)\n     const char * user;\n{\n  struct t_pwent * tpptr;\n  struct t_confent * tcptr;\n\n  if(pwinit() < 0)\n    return NULL;\n  tpptr = t_getpwbyname(syspw, user);\n  if(tpptr == NULL)\n    return NULL;\n  tcptr =\n    gettcid\n    (tpptr->index);\n  if(tcptr == NULL)\n    return NULL;\n  pwsetup(&tpass, tpptr, tcptr);\n  return &tpass;\n}\n"
  },
  {
    "path": "package/network/services/ead/src/tinysrp/t_pwd.h",
    "content": "/*\n * Copyright (c) 1997-1999  The Stanford SRP Authentication Project\n * All Rights Reserved.\n *\n * Permission is hereby granted, free of charge, to any person obtaining\n * a copy of this software and associated documentation files (the\n * \"Software\"), to deal in the Software without restriction, including\n * without limitation the rights to use, copy, modify, merge, publish,\n * distribute, sublicense, and/or sell copies of the Software, and to\n * permit persons to whom the Software is furnished to do so, subject to\n * the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS-IS\" AND WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS, IMPLIED OR OTHERWISE, INCLUDING WITHOUT LIMITATION, ANY\n * WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.\n *\n * IN NO EVENT SHALL STANFORD BE LIABLE FOR ANY SPECIAL, INCIDENTAL,\n * INDIRECT OR CONSEQUENTIAL DAMAGES OF ANY KIND, OR ANY DAMAGES WHATSOEVER\n * RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER OR NOT ADVISED OF\n * THE POSSIBILITY OF DAMAGE, AND ON ANY THEORY OF LIABILITY, ARISING OUT\n * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n * In addition, the following conditions apply:\n *\n * 1. Any software that incorporates the SRP authentication technology\n *    must display the following acknowlegment:\n *    \"This product uses the 'Secure Remote Password' cryptographic\n *     authentication system developed by Tom Wu (tjw@CS.Stanford.EDU).\"\n *\n * 2. Any software that incorporates all or part of the SRP distribution\n *    itself must also display the following acknowledgment:\n *    \"This product includes software developed by Tom Wu and Eugene\n *     Jhong for the SRP Distribution (http://srp.stanford.edu/srp/).\"\n *\n * 3. Redistributions in source or binary form must retain an intact copy\n *    of this copyright notice and list of conditions.\n */\n\n#ifndef T_PWD_H\n#define T_PWD_H\n\n#ifndef P\n#if defined (__STDC__) || defined (__cplusplus)\n#define P(x) x\n#else\n#define P(x) ()\n#endif\n#endif\n\n/*      For building dynamic link libraries under windows, windows NT\n *      using MSVC1.5 or MSVC2.0\n */\n\n#ifndef _DLLDECL\n#define _DLLDECL\n\n#ifdef MSVC15   /* MSVC1.5 support for 16 bit apps */\n#define _MSVC15EXPORT _export\n#define _MSVC20EXPORT\n#define _DLLAPI _export _pascal\n#define _TYPE(a) a _MSVC15EXPORT\n#define DLLEXPORT 1\n\n#elif MSVC20\n#define _MSVC15EXPORT\n#define _MSVC20EXPORT _declspec(dllexport)\n#define _DLLAPI\n#define _TYPE(a) _MSVC20EXPORT a\n#define DLLEXPORT 1\n\n#else                   /* Default, non-dll.  Use this for Unix or DOS */\n#define _MSVC15DEXPORT\n#define _MSVC20EXPORT\n#define _DLLAPI\n#define _TYPE(a) a\n#endif\n#endif\n\n#define MAXPARAMBITS    2048\n#define MAXPARAMLEN     ((MAXPARAMBITS + 7) / 8)\n#define MAXB64PARAMLEN  ((MAXPARAMBITS + 5) / 6 + 1)\n#define MAXHEXPARAMLEN  ((MAXPARAMBITS + 3) / 4 + 1)\n#define MAXOCTPARAMLEN  ((MAXPARAMBITS + 2) / 3 + 1)\n\n#define MAXUSERLEN      32\n#define MAXSALTLEN      32\n#define MAXB64SALTLEN   44      /* 256 bits in b64 + null */\n#define SALTLEN         10      /* Normally 80 bits */\n\n#define RESPONSE_LEN    20      /* 160-bit proof hashes */\n#define SESSION_KEY_LEN (2 * RESPONSE_LEN)      /* 320-bit session key */\n\n#define DEFAULT_PASSWD  \"tpasswd\"\n\nstruct t_num {  /* Standard byte-oriented integer representation */\n  int len;\n  unsigned char * data;\n};\n\nstruct t_preconf {      /* Structure returned by t_getpreparam() */\n  char * mod_b64;\n  char * gen_b64;\n  char * comment;\n\n  struct t_num modulus;\n  struct t_num generator;\n};\n\n/*\n * The built-in (known good) parameters access routines\n *\n * \"t_getprecount\" returns the number of precompiled parameter sets.\n * \"t_getpreparam\" returns the indicated parameter set.\n * Memory is statically allocated - callers need not perform any memory mgmt.\n */\n_TYPE( int ) t_getprecount();\n_TYPE( struct t_preconf * ) t_getpreparam P((int));\n\nstruct t_confent {      /* One configuration file entry (index, N, g) */\n  int index;\n  struct t_num modulus;\n  struct t_num generator;\n};\n\nstruct t_conf {         /* An open configuration file */\n  FILE * instream;\n  char close_on_exit;\n  unsigned char modbuf[MAXPARAMLEN];\n  unsigned char genbuf[MAXPARAMLEN];\n  struct t_confent tcbuf;\n};\n\n/*\n * The configuration file routines are designed along the lines of the\n * \"getpw\" functions in the standard C library.\n *\n * \"t_openconf\" accepts a stdio stream and interprets it as a config file.\n * \"t_openconfbyname\" accepts a filename and does the same thing.\n * \"t_closeconf\" closes the config file.\n * \"t_getconfent\" fetches the next sequential configuration entry.\n * \"t_getconfbyindex\" fetches the configuration entry whose index\n *   matches the one supplied, or NULL if one can't be found.\n * \"t_getconflast\" fetches the last configuration entry in the file.\n * \"t_makeconfent\" generates a set of configuration entry parameters\n *   randomly.\n * \"t_newconfent\" returns an empty configuration entry.\n * \"t_cmpconfent\" compares two configuration entries a la strcmp.\n * \"t_checkconfent\" verifies that a set of configuration parameters\n *   are suitable.  N must be prime and should be a safe prime.\n * \"t_putconfent\" writes a configuration entry to a stream.\n */\n_TYPE( struct t_conf * ) t_openconf P((FILE *));\n_TYPE( struct t_conf * ) t_openconfbyname P((const char *));\n_TYPE( void ) t_closeconf P((struct t_conf *));\n_TYPE( void ) t_rewindconf P((struct t_conf *));\n_TYPE( struct t_confent * ) t_getconfent P((struct t_conf *));\n_TYPE( struct t_confent * ) t_getconfbyindex P((struct t_conf *, int));\n_TYPE( struct t_confent * ) t_getconflast P((struct t_conf *));\n_TYPE( struct t_confent * ) t_makeconfent P((struct t_conf *, int));\n_TYPE( struct t_confent * ) t_makeconfent_c P((struct t_conf *, int));\n_TYPE( struct t_confent * ) t_newconfent P((struct t_conf *));\n_TYPE( int ) t_cmpconfent P((const struct t_confent *, const struct t_confent *));\n_TYPE( int ) t_checkconfent P((const struct t_confent *));\n_TYPE( void ) t_putconfent P((const struct t_confent *, FILE *));\n\n/* libc-style system conf file access */\n_TYPE( struct t_confent *) gettcent();\n_TYPE( struct t_confent *) gettcid P((int));\n_TYPE( void ) settcent();\n_TYPE( void ) endtcent();\n\n#ifdef ENABLE_NSW\nextern struct t_confent * _gettcent();\nextern struct t_confent * _gettcid P((int));\nextern void _settcent();\nextern void _endtcent();\n#endif\n\n/* A hack to support '+'-style entries in the passwd file */\n\ntypedef enum fstate {\n  FILE_ONLY,    /* Ordinary file, don't consult NIS ever */\n  FILE_NIS,     /* Currently accessing file, use NIS if encountered */\n  IN_NIS,       /* Currently in a '+' entry; use NIS for getXXent */\n} FILE_STATE;\n\nstruct t_pwent {        /* A single password file entry */\n  char * name;\n  struct t_num password;\n  struct t_num salt;\n  int index;\n};\n\nstruct t_pw {           /* An open password file */\n  FILE * instream;\n  char close_on_exit;\n  FILE_STATE state;\n  char userbuf[MAXUSERLEN];\n  unsigned char pwbuf[MAXPARAMLEN];\n  unsigned char saltbuf[SALTLEN];\n  struct t_pwent pebuf;\n};\n\n/*\n * The password manipulation routines are patterned after the getpw*\n * standard C library function calls.\n *\n * \"t_openpw\" reads a stream as if it were a password file.\n * \"t_openpwbyname\" opens the named file as a password file.\n * \"t_closepw\" closes an open password file.\n * \"t_rewindpw\" starts the internal file pointer from the beginning\n *   of the password file.\n * \"t_getpwent\" retrieves the next sequential password entry.\n * \"t_getpwbyname\" looks up the password entry corresponding to the\n *   specified user.\n * \"t_makepwent\" constructs a password entry from a username, password,\n *   numeric salt, and configuration entry.\n * \"t_putpwent\" writes a password entry to a stream.\n */\n_TYPE( struct t_pw * ) t_openpw P((FILE *));\n_TYPE( struct t_pw * ) t_openpwbyname P((const char *));\n_TYPE( void ) t_closepw P((struct t_pw *));\n_TYPE( void ) t_rewindpw P((struct t_pw *));\n_TYPE( struct t_pwent * ) t_getpwent P((struct t_pw *));\n_TYPE( struct t_pwent * ) t_getpwbyname P((struct t_pw *, const char *));\n_TYPE( struct t_pwent * ) t_makepwent P((struct t_pw *, const char *,\n\t\t\t\t\t const char *, const struct t_num *,\n\t\t\t\t\t const struct t_confent *));\n_TYPE( void ) t_putpwent P((const struct t_pwent *, FILE *));\n\nstruct t_passwd {\n  struct t_pwent tp;\n  struct t_confent tc;\n};\n\n/* libc-style system password file access */\n_TYPE( struct t_passwd * ) gettpent();\n_TYPE( struct t_passwd * ) gettpnam P((const char *));\n_TYPE( void ) settpent();\n_TYPE( void ) endtpent();\n\n#ifdef ENABLE_NSW\nextern struct t_passwd * _gettpent();\nextern struct t_passwd * _gettpnam P((const char *));\nextern void _settpent();\nextern void _endtpent();\n#endif\n\n/*\n * Utility functions\n *\n * \"t_verifypw\" accepts a username and password, and checks against the\n *   system password file to see if the password for that user is correct.\n *   Returns > 0 if it is correct, 0 if not, and -1 if some error occurred\n *   (i.e. the user doesn't exist on the system).  This is intended ONLY\n *   for local authentication; for remote authentication, look at the\n *   t_client and t_server source.  (That's the whole point of SRP!)\n * \"t_changepw\" modifies the specified file, substituting the given password\n *   entry for the one already in the file.  If no matching entry is found,\n *   the new entry is simply appended to the file.\n * \"t_deletepw\" removes the specified user from the specified file.\n */\n_TYPE( int ) t_verifypw P((const char *, const char *));\n_TYPE( int ) t_changepw P((const char *, const struct t_pwent *));\n_TYPE( int ) t_deletepw P((const char *, const char *));\n\n/* Conversion utilities */\n\n/*\n * All these calls accept output as the first parameter.  In the case of\n * t_tohex and t_tob64, the last argument is the length of the byte-string\n * input.\n */\n_TYPE( char * t_tohex ) P((char *, char *, unsigned));\n_TYPE( int ) t_fromhex P((char *, char *));\n_TYPE( char * ) t_tob64 P((char *, char *, unsigned));\n_TYPE( int ) t_fromb64 P((char *, char *));\n\n/* Miscellaneous utilities */\n\n/*\n * \"t_random\" is a cryptographic random number generator, which is seeded\n *   from various high-entropy sources and uses a one-way hash function\n *   in a feedback configuration.\n * \"t_sessionkey\" is the interleaved hash used to generate session keys\n *   from a large integer.\n * \"t_getpass\" reads a password from the terminal without echoing.\n */\n_TYPE( void ) t_random P((unsigned char *, unsigned));\n_TYPE( void ) t_stronginitrand();\n_TYPE( unsigned char * )\n  t_sessionkey P((unsigned char *, unsigned char *, unsigned));\n_TYPE( int ) t_getpass P((char *, unsigned, const char *));\n\n/*\n * Return value of t_checkprime:\n *   < 0 : not prime\n *   = 0 : prime, but not safe\n *   > 0 : safe\n */\n#define NUM_NOTPRIME    -1\n#define NUM_NOTSAFE     0\n#define NUM_SAFE        1\n\n_TYPE( int ) t_checkprime P((const struct t_num *));\n\n#endif\n"
  },
  {
    "path": "package/network/services/ead/src/tinysrp/t_read.c",
    "content": "/*\n * Copyright (c) 1997-1999  The Stanford SRP Authentication Project\n * All Rights Reserved.\n *\n * Permission is hereby granted, free of charge, to any person obtaining\n * a copy of this software and associated documentation files (the\n * \"Software\"), to deal in the Software without restriction, including\n * without limitation the rights to use, copy, modify, merge, publish,\n * distribute, sublicense, and/or sell copies of the Software, and to\n * permit persons to whom the Software is furnished to do so, subject to\n * the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS-IS\" AND WITHOUT WARRANTY OF ANY KIND, \n * EXPRESS, IMPLIED OR OTHERWISE, INCLUDING WITHOUT LIMITATION, ANY \n * WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.  \n *\n * IN NO EVENT SHALL STANFORD BE LIABLE FOR ANY SPECIAL, INCIDENTAL,\n * INDIRECT OR CONSEQUENTIAL DAMAGES OF ANY KIND, OR ANY DAMAGES WHATSOEVER\n * RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER OR NOT ADVISED OF\n * THE POSSIBILITY OF DAMAGE, AND ON ANY THEORY OF LIABILITY, ARISING OUT\n * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n * In addition, the following conditions apply:\n *\n * 1. Any software that incorporates the SRP authentication technology\n *    must display the following acknowlegment:\n *    \"This product uses the 'Secure Remote Password' cryptographic\n *     authentication system developed by Tom Wu (tjw@CS.Stanford.EDU).\"\n *\n * 2. Any software that incorporates all or part of the SRP distribution\n *    itself must also display the following acknowledgment:\n *    \"This product includes software developed by Tom Wu and Eugene\n *     Jhong for the SRP Distribution (http://srp.stanford.edu/srp/).\"\n *\n * 3. Redistributions in source or binary form must retain an intact copy\n *    of this copyright notice and list of conditions.\n */\n\n#include <stdio.h>\n#include \"config.h\"\n\n#define FSEPARATOR\t':'\n\nint\nt_nextfield(fp, s, max)\nFILE * fp;\nchar * s;\nunsigned max;\n{\n  int c, count = 0;\n\n  while((c = getc(fp)) != EOF) {\n    if(c == '\\n') {\n      ungetc(c, fp);\n      break;\n    }\n    else if(c == FSEPARATOR)\n      break;\n    if(count < max - 1) {\n      *s++ = c;\n      ++count;\n    }\n  }\n  *s++ = '\\0';\n  return count;\n}\n\nint\nt_nextline(fp)\nFILE * fp;\n{\n  int c;\n\n  while((c = getc(fp)) != '\\n')\n    if(c == EOF)\n      return -1;\n  return 0;\n}\n"
  },
  {
    "path": "package/network/services/ead/src/tinysrp/t_read.h",
    "content": "/*\n * Copyright (c) 1997-1999  The Stanford SRP Authentication Project\n * All Rights Reserved.\n *\n * Permission is hereby granted, free of charge, to any person obtaining\n * a copy of this software and associated documentation files (the\n * \"Software\"), to deal in the Software without restriction, including\n * without limitation the rights to use, copy, modify, merge, publish,\n * distribute, sublicense, and/or sell copies of the Software, and to\n * permit persons to whom the Software is furnished to do so, subject to\n * the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS-IS\" AND WITHOUT WARRANTY OF ANY KIND, \n * EXPRESS, IMPLIED OR OTHERWISE, INCLUDING WITHOUT LIMITATION, ANY \n * WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.  \n *\n * IN NO EVENT SHALL STANFORD BE LIABLE FOR ANY SPECIAL, INCIDENTAL,\n * INDIRECT OR CONSEQUENTIAL DAMAGES OF ANY KIND, OR ANY DAMAGES WHATSOEVER\n * RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER OR NOT ADVISED OF\n * THE POSSIBILITY OF DAMAGE, AND ON ANY THEORY OF LIABILITY, ARISING OUT\n * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n * In addition, the following conditions apply:\n *\n * 1. Any software that incorporates the SRP authentication technology\n *    must display the following acknowlegment:\n *    \"This product uses the 'Secure Remote Password' cryptographic\n *     authentication system developed by Tom Wu (tjw@CS.Stanford.EDU).\"\n *\n * 2. Any software that incorporates all or part of the SRP distribution\n *    itself must also display the following acknowledgment:\n *    \"This product includes software developed by Tom Wu and Eugene\n *     Jhong for the SRP Distribution (http://srp.stanford.edu/srp/).\"\n *\n * 3. Redistributions in source or binary form must retain an intact copy\n *    of this copyright notice and list of conditions.\n */\n\n#ifndef _T_READ_H_\n#define _T_READ_H_\n\n#if     !defined(P)\n#ifdef  __STDC__\n#define P(x)    x\n#else\n#define P(x)    ()\n#endif\n#endif\n\nextern int t_nextfield P((FILE *, char *, unsigned));\nextern int t_nextline P((FILE *));\n#endif\n"
  },
  {
    "path": "package/network/services/ead/src/tinysrp/t_server.c",
    "content": "/*\n * Copyright (c) 1997-1999  The Stanford SRP Authentication Project\n * All Rights Reserved.\n *\n * Permission is hereby granted, free of charge, to any person obtaining\n * a copy of this software and associated documentation files (the\n * \"Software\"), to deal in the Software without restriction, including\n * without limitation the rights to use, copy, modify, merge, publish,\n * distribute, sublicense, and/or sell copies of the Software, and to\n * permit persons to whom the Software is furnished to do so, subject to\n * the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS-IS\" AND WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS, IMPLIED OR OTHERWISE, INCLUDING WITHOUT LIMITATION, ANY\n * WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.\n *\n * IN NO EVENT SHALL STANFORD BE LIABLE FOR ANY SPECIAL, INCIDENTAL,\n * INDIRECT OR CONSEQUENTIAL DAMAGES OF ANY KIND, OR ANY DAMAGES WHATSOEVER\n * RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER OR NOT ADVISED OF\n * THE POSSIBILITY OF DAMAGE, AND ON ANY THEORY OF LIABILITY, ARISING OUT\n * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n * In addition, the following conditions apply:\n *\n * 1. Any software that incorporates the SRP authentication technology\n *    must display the following acknowlegment:\n *    \"This product uses the 'Secure Remote Password' cryptographic\n *     authentication system developed by Tom Wu (tjw@CS.Stanford.EDU).\"\n *\n * 2. Any software that incorporates all or part of the SRP distribution\n *    itself must also display the following acknowledgment:\n *    \"This product includes software developed by Tom Wu and Eugene\n *     Jhong for the SRP Distribution (http://srp.stanford.edu/srp/).\"\n *\n * 3. Redistributions in source or binary form must retain an intact copy\n *    of this copyright notice and list of conditions.\n */\n\n#include <stdio.h>\n#include \"t_defines.h\"\n#include \"t_pwd.h\"\n#include \"t_server.h\"\n\n_TYPE( struct t_server * )\nt_serveropenraw(ent, tce)\n     struct t_pwent * ent;\n     struct t_confent * tce;\n{\n  struct t_server * ts;\n  unsigned char buf1[SHA_DIGESTSIZE], buf2[SHA_DIGESTSIZE];\n  SHA1_CTX ctxt;\n  int i;\n\n  if((ts = malloc(sizeof(struct t_server))) == 0)\n    return 0;\n\n  SHA1Init(&ts->ckhash);\n\n  ts->index = ent->index;\n  ts->n.len = tce->modulus.len;\n  ts->n.data = ts->nbuf;\n  memcpy(ts->n.data, tce->modulus.data, ts->n.len);\n\n  SHA1Init(&ctxt);\n  SHA1Update(&ctxt, ts->n.data, ts->n.len);\n  SHA1Final(buf1, &ctxt);\n\n  ts->g.len = tce->generator.len;\n  ts->g.data = ts->gbuf;\n  memcpy(ts->g.data, tce->generator.data, ts->g.len);\n\n  SHA1Init(&ctxt);\n  SHA1Update(&ctxt, ts->g.data, ts->g.len);\n  SHA1Final(buf2, &ctxt);\n\n  for(i = 0; i < sizeof(buf1); ++i)\n    buf1[i] ^= buf2[i];\n\n  SHA1Update(&ts->ckhash, buf1, sizeof(buf1));\n\n  SHA1Init(&ctxt);\n  SHA1Update(&ctxt, ent->name, strlen(ent->name));\n  SHA1Final(buf1, &ctxt);\n\n  SHA1Update(&ts->ckhash, buf1, sizeof(buf1));\n\n  ts->v.len = ent->password.len;\n  ts->v.data = ts->vbuf;\n  memcpy(ts->v.data, ent->password.data, ts->v.len);\n\n  ts->s.len = ent->salt.len;\n  ts->s.data = ts->saltbuf;\n  memcpy(ts->s.data, ent->salt.data, ts->s.len);\n\n  SHA1Update(&ts->ckhash, ts->s.data, ts->s.len);\n\n  ts->b.data = ts->bbuf;\n  ts->B.data = ts->Bbuf;\n\n  SHA1Init(&ts->hash);\n  SHA1Init(&ts->oldhash);\n  SHA1Init(&ts->oldckhash);\n\n  return ts;\n}\n\n_TYPE( struct t_num * )\nt_servergenexp(ts)\n     struct t_server * ts;\n{\n  BigInteger b, B, v, n, g;\n\n  if(ts->n.len < BLEN)\n    ts->b.len = ts->n.len;\n  else\n    ts->b.len = BLEN;\n\n  t_random(ts->b.data, ts->b.len);\n  b = BigIntegerFromBytes(ts->b.data, ts->b.len);\n  n = BigIntegerFromBytes(ts->n.data, ts->n.len);\n  g = BigIntegerFromBytes(ts->g.data, ts->g.len);\n  B = BigIntegerFromInt(0);\n  BigIntegerModExp(B, g, b, n);\n\n  v = BigIntegerFromBytes(ts->v.data, ts->v.len);\n  BigIntegerAdd(B, B, v);\n  if(BigIntegerCmp(B, n) > 0)\n    BigIntegerSub(B, B, n);\n\n  ts->B.len = BigIntegerToBytes(B, ts->B.data);\n\n  BigIntegerFree(v);\n  BigIntegerFree(B);\n  BigIntegerFree(b);\n  BigIntegerFree(g);\n  BigIntegerFree(n);\n\n  SHA1Update(&ts->oldckhash, ts->B.data, ts->B.len);\n\n  return &ts->B;\n}\n\n_TYPE( unsigned char * )\nt_servergetkey(ts, clientval)\n     struct t_server * ts;\n     struct t_num * clientval;\n{\n  BigInteger n, v, A, b, prod, res, S;\n  SHA1_CTX ctxt;\n  unsigned char sbuf[MAXPARAMLEN];\n  unsigned char dig[SHA_DIGESTSIZE];\n  unsigned slen;\n  unsigned int u;\n\n  SHA1Update(&ts->ckhash, clientval->data, clientval->len);\n  SHA1Update(&ts->ckhash, ts->B.data, ts->B.len);\n\n  SHA1Init(&ctxt);\n  SHA1Update(&ctxt, ts->B.data, ts->B.len);\n  SHA1Final(dig, &ctxt);\n  u = (dig[0] << 24) | (dig[1] << 16) | (dig[2] << 8) | dig[3];\n\n  SHA1Update(&ts->oldhash, clientval->data, clientval->len);\n  SHA1Update(&ts->hash, clientval->data, clientval->len);\n\n  n = BigIntegerFromBytes(ts->n.data, ts->n.len);\n  b = BigIntegerFromBytes(ts->b.data, ts->b.len);\n  v = BigIntegerFromBytes(ts->v.data, ts->v.len);\n  A = BigIntegerFromBytes(clientval->data, clientval->len);\n\n  prod = BigIntegerFromInt(0);\n  BigIntegerModExpInt(prod, v, u, n);\n  res = BigIntegerFromInt(0);\n  BigIntegerModMul(res, prod, A, n);\n\n  BigIntegerFree(A);\n  BigIntegerFree(v);\n  BigIntegerFree(prod);\n\n  if(BigIntegerCmpInt(res, 1) <= 0) {   /* Check for Av^u == 1 (mod n) */\n    BigIntegerFree(res);\n    BigIntegerFree(b);\n    BigIntegerFree(n);\n    return NULL;\n  }\n\n  S = BigIntegerFromInt(0);\n\n  BigIntegerAddInt(S, res, 1);\n  if(BigIntegerCmp(S, n) == 0) {        /* Check for Av^u == -1 (mod n) */\n    BigIntegerFree(res);\n    BigIntegerFree(b);\n    BigIntegerFree(n);\n    BigIntegerFree(S);\n    return NULL;\n  }\n\n  BigIntegerModExp(S, res, b, n);\n  slen = BigIntegerToBytes(S, sbuf);\n\n  BigIntegerFree(S);\n  BigIntegerFree(res);\n  BigIntegerFree(b);\n  BigIntegerFree(n);\n\n  t_sessionkey(ts->session_key, sbuf, slen);\n  memset(sbuf, 0, slen);\n\n  SHA1Update(&ts->oldhash, ts->session_key, sizeof(ts->session_key));\n  SHA1Update(&ts->oldckhash, ts->session_key, sizeof(ts->session_key));\n  SHA1Update(&ts->ckhash, ts->session_key, sizeof(ts->session_key));\n\n  return ts->session_key;\n}\n\n_TYPE( int )\nt_serververify(ts, resp)\n    struct t_server * ts;\n    unsigned char * resp;\n{\n  unsigned char expected[SHA_DIGESTSIZE];\n  int i;\n\n  SHA1Final(expected, &ts->oldckhash);\n  i = memcmp(expected, resp, sizeof(expected));\n  if(i == 0) {\n    SHA1Final(ts->session_response, &ts->oldhash);\n    return 0;\n  }\n  SHA1Final(expected, &ts->ckhash);\n  i = memcmp(expected, resp, sizeof(expected));\n  if(i == 0) {\n    SHA1Update(&ts->hash, expected, sizeof(expected));\n    SHA1Update(&ts->hash, ts->session_key, sizeof(ts->session_key));\n    SHA1Final(ts->session_response, &ts->hash);\n  }\n  return i;\n}\n\n_TYPE( unsigned char * )\nt_serverresponse(ts)\n    struct t_server * ts;\n{\n  return ts->session_response;\n}\n\n_TYPE( void )\nt_serverclose(ts)\n     struct t_server * ts;\n{\n  memset(ts->bbuf, 0, sizeof(ts->bbuf));\n  memset(ts->vbuf, 0, sizeof(ts->vbuf));\n  memset(ts->saltbuf, 0, sizeof(ts->saltbuf));\n  memset(ts->session_key, 0, sizeof(ts->session_key));\n  free(ts);\n}\n"
  },
  {
    "path": "package/network/services/ead/src/tinysrp/t_server.h",
    "content": "/*\n * Copyright (c) 1997-1999  The Stanford SRP Authentication Project\n * All Rights Reserved.\n *\n * Permission is hereby granted, free of charge, to any person obtaining\n * a copy of this software and associated documentation files (the\n * \"Software\"), to deal in the Software without restriction, including\n * without limitation the rights to use, copy, modify, merge, publish,\n * distribute, sublicense, and/or sell copies of the Software, and to\n * permit persons to whom the Software is furnished to do so, subject to\n * the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS-IS\" AND WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS, IMPLIED OR OTHERWISE, INCLUDING WITHOUT LIMITATION, ANY\n * WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.\n *\n * IN NO EVENT SHALL STANFORD BE LIABLE FOR ANY SPECIAL, INCIDENTAL,\n * INDIRECT OR CONSEQUENTIAL DAMAGES OF ANY KIND, OR ANY DAMAGES WHATSOEVER\n * RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER OR NOT ADVISED OF\n * THE POSSIBILITY OF DAMAGE, AND ON ANY THEORY OF LIABILITY, ARISING OUT\n * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n * In addition, the following conditions apply:\n *\n * 1. Any software that incorporates the SRP authentication technology\n *    must display the following acknowlegment:\n *    \"This product uses the 'Secure Remote Password' cryptographic\n *     authentication system developed by Tom Wu (tjw@CS.Stanford.EDU).\"\n *\n * 2. Any software that incorporates all or part of the SRP distribution\n *    itself must also display the following acknowledgment:\n *    \"This product includes software developed by Tom Wu and Eugene\n *     Jhong for the SRP Distribution (http://srp.stanford.edu/srp/).\"\n *\n * 3. Redistributions in source or binary form must retain an intact copy\n *    of this copyright notice and list of conditions.\n */\n\n#ifndef T_SERVER_H\n#define T_SERVER_H\n\n#include \"t_sha.h\"\n\n#if     !defined(P)\n#ifdef  __STDC__\n#define P(x)    x\n#else\n#define P(x)    ()\n#endif\n#endif\n\n#ifndef _DLLDECL\n#define _DLLDECL\n\n#ifdef MSVC15   /* MSVC1.5 support for 16 bit apps */\n#define _MSVC15EXPORT _export\n#define _MSVC20EXPORT\n#define _DLLAPI _export _pascal\n#define _TYPE(a) a _MSVC15EXPORT\n#define DLLEXPORT 1\n\n#elif MSVC20\n#define _MSVC15EXPORT\n#define _MSVC20EXPORT _declspec(dllexport)\n#define _DLLAPI\n#define _TYPE(a) _MSVC20EXPORT a\n#define DLLEXPORT 1\n\n#else                   /* Default, non-dll.  Use this for Unix or DOS */\n#define _MSVC15DEXPORT\n#define _MSVC20EXPORT\n#define _DLLAPI\n#define _TYPE(a) a\n#endif\n#endif\n\n#define BLEN 32\n\nstruct t_server {\n  int index;\n  struct t_num n;\n  struct t_num g;\n  struct t_num v;\n  struct t_num s;\n\n  struct t_num b;\n  struct t_num B;\n\n  SHA1_CTX oldhash, hash, oldckhash, ckhash;\n\n  unsigned char session_key[SESSION_KEY_LEN];\n  unsigned char session_response[RESPONSE_LEN];\n\n  unsigned char nbuf[MAXPARAMLEN], gbuf[MAXPARAMLEN], vbuf[MAXPARAMLEN];\n  unsigned char saltbuf[MAXSALTLEN], bbuf[BLEN], Bbuf[MAXPARAMLEN];\n};\n\n/*\n * SRP server-side negotiation\n *\n * This code negotiates the server side of an SRP exchange.\n * \"t_serveropen\" accepts a username (sent by the client), a pointer\n *   to an open password file, and a pointer to an open configuration\n *   file.  The server should then call...\n * \"t_servergenexp\" will generate a random 256-bit exponent and\n *   raise g (from the configuration file) to that power, returning\n *   the result.  This result should be sent to the client as y(p).\n * \"t_servergetkey\" accepts the exponential w(p), which should be\n *   sent by the client, and computes the 256-bit session key.\n *   This data should be saved before the session is closed.\n * \"t_serverresponse\" computes the session key proof as SHA(w(p), K).\n * \"t_serverclose\" closes the session and frees its memory.\n *\n * Note that authentication is not performed per se; it is up\n * to either/both sides of the protocol to now verify securely\n * that their session keys agree in order to establish authenticity.\n * One possible way is through \"oracle hashing\"; one side sends\n * r, the other replies with H(r,K), where H() is a hash function.\n *\n * t_serverresponse and t_serververify now implement a version of\n * the session-key verification described above.\n */\n_TYPE( struct t_server * )\n  t_serveropen P((const char *));\n_TYPE( struct t_server * )\n  t_serveropenfromfiles P((const char *, struct t_pw *, struct t_conf *));\n_TYPE( struct t_server * )\n  t_serveropenraw P((struct t_pwent *, struct t_confent *));\n_TYPE( struct t_num * ) t_servergenexp P((struct t_server *));\n_TYPE( unsigned char * ) t_servergetkey P((struct t_server *, struct t_num *));\n_TYPE( int ) t_serververify P((struct t_server *, unsigned char *));\n_TYPE( unsigned char * ) t_serverresponse P((struct t_server *));\n_TYPE( void ) t_serverclose P((struct t_server *));\n\n#endif\n"
  },
  {
    "path": "package/network/services/ead/src/tinysrp/t_sha.c",
    "content": "#include \"t_defines.h\"\n#include \"t_sha.h\"\n\n/*\nSHA-1 in C\nBy Steve Reid <steve@edmweb.com>\n100% Public Domain\n\nTest Vectors (from FIPS PUB 180-1)\n\"abc\"\n  A9993E36 4706816A BA3E2571 7850C26C 9CD0D89D\n\"abcdbcdecdefdefgefghfghighijhijkijkljklmklmnlmnomnopnopq\"\n  84983E44 1C3BD26E BAAE4AA1 F95129E5 E54670F1\nA million repetitions of \"a\"\n  34AA973C D4C4DAA4 F61EEB2B DBAD2731 6534016F\n*/\n\n/* #define WORDS_BIGENDIAN * This should be #define'd if true. */\n/* #define SHA1HANDSOFF * Copies data before messing with it. */\n\n#include <stdio.h>\n#include <string.h>\n\nstatic void SHA1Transform(uint32 state[5], const unsigned char buffer[64]);\n\n#define rol(value, bits) (((value) << (bits)) | ((value) >> (32 - (bits))))\n\n/* blk0() and blk() perform the initial expand. */\n/* I got the idea of expanding during the round function from SSLeay */\n#ifndef WORDS_BIGENDIAN\n#define blk0(i) (block->l[i] = (rol(block->l[i],24)&0xFF00FF00) \\\n    |(rol(block->l[i],8)&0x00FF00FF))\n#else\n#define blk0(i) block->l[i]\n#endif\n#define blk(i) (block->l[i&15] = rol(block->l[(i+13)&15]^block->l[(i+8)&15] \\\n    ^block->l[(i+2)&15]^block->l[i&15],1))\n\n/* (R0+R1), R2, R3, R4 are the different operations used in SHA1 */\n#define R0(v,w,x,y,z,i) z+=((w&(x^y))^y)+blk0(i)+0x5A827999+rol(v,5);w=rol(w,30);\n#define R1(v,w,x,y,z,i) z+=((w&(x^y))^y)+blk(i)+0x5A827999+rol(v,5);w=rol(w,30);\n#define R2(v,w,x,y,z,i) z+=(w^x^y)+blk(i)+0x6ED9EBA1+rol(v,5);w=rol(w,30);\n#define R3(v,w,x,y,z,i) z+=(((w|x)&y)|(w&x))+blk(i)+0x8F1BBCDC+rol(v,5);w=rol(w,30);\n#define R4(v,w,x,y,z,i) z+=(w^x^y)+blk(i)+0xCA62C1D6+rol(v,5);w=rol(w,30);\n\n/* Hash a single 512-bit block. This is the core of the algorithm. */\n\nstatic void SHA1Transform(uint32 state[5], const unsigned char buffer[64])\n{\nuint32 a, b, c, d, e;\ntypedef union {\n    unsigned char c[64];\n    uint32 l[16];\n} CHAR64LONG16;\nCHAR64LONG16* block;\n#ifdef SHA1HANDSOFF\nstatic unsigned char workspace[64];\n    block = (CHAR64LONG16*)workspace;\n    memcpy(block, buffer, 64);\n#else\n    block = (CHAR64LONG16*)buffer;\n#endif\n    /* Copy context->state[] to working vars */\n    a = state[0];\n    b = state[1];\n    c = state[2];\n    d = state[3];\n    e = state[4];\n    /* 4 rounds of 20 operations each. Loop unrolled. */\n    R0(a,b,c,d,e, 0); R0(e,a,b,c,d, 1); R0(d,e,a,b,c, 2); R0(c,d,e,a,b, 3);\n    R0(b,c,d,e,a, 4); R0(a,b,c,d,e, 5); R0(e,a,b,c,d, 6); R0(d,e,a,b,c, 7);\n    R0(c,d,e,a,b, 8); R0(b,c,d,e,a, 9); R0(a,b,c,d,e,10); R0(e,a,b,c,d,11);\n    R0(d,e,a,b,c,12); R0(c,d,e,a,b,13); R0(b,c,d,e,a,14); R0(a,b,c,d,e,15);\n    R1(e,a,b,c,d,16); R1(d,e,a,b,c,17); R1(c,d,e,a,b,18); R1(b,c,d,e,a,19);\n    R2(a,b,c,d,e,20); R2(e,a,b,c,d,21); R2(d,e,a,b,c,22); R2(c,d,e,a,b,23);\n    R2(b,c,d,e,a,24); R2(a,b,c,d,e,25); R2(e,a,b,c,d,26); R2(d,e,a,b,c,27);\n    R2(c,d,e,a,b,28); R2(b,c,d,e,a,29); R2(a,b,c,d,e,30); R2(e,a,b,c,d,31);\n    R2(d,e,a,b,c,32); R2(c,d,e,a,b,33); R2(b,c,d,e,a,34); R2(a,b,c,d,e,35);\n    R2(e,a,b,c,d,36); R2(d,e,a,b,c,37); R2(c,d,e,a,b,38); R2(b,c,d,e,a,39);\n    R3(a,b,c,d,e,40); R3(e,a,b,c,d,41); R3(d,e,a,b,c,42); R3(c,d,e,a,b,43);\n    R3(b,c,d,e,a,44); R3(a,b,c,d,e,45); R3(e,a,b,c,d,46); R3(d,e,a,b,c,47);\n    R3(c,d,e,a,b,48); R3(b,c,d,e,a,49); R3(a,b,c,d,e,50); R3(e,a,b,c,d,51);\n    R3(d,e,a,b,c,52); R3(c,d,e,a,b,53); R3(b,c,d,e,a,54); R3(a,b,c,d,e,55);\n    R3(e,a,b,c,d,56); R3(d,e,a,b,c,57); R3(c,d,e,a,b,58); R3(b,c,d,e,a,59);\n    R4(a,b,c,d,e,60); R4(e,a,b,c,d,61); R4(d,e,a,b,c,62); R4(c,d,e,a,b,63);\n    R4(b,c,d,e,a,64); R4(a,b,c,d,e,65); R4(e,a,b,c,d,66); R4(d,e,a,b,c,67);\n    R4(c,d,e,a,b,68); R4(b,c,d,e,a,69); R4(a,b,c,d,e,70); R4(e,a,b,c,d,71);\n    R4(d,e,a,b,c,72); R4(c,d,e,a,b,73); R4(b,c,d,e,a,74); R4(a,b,c,d,e,75);\n    R4(e,a,b,c,d,76); R4(d,e,a,b,c,77); R4(c,d,e,a,b,78); R4(b,c,d,e,a,79);\n    /* Add the working vars back into context.state[] */\n    state[0] += a;\n    state[1] += b;\n    state[2] += c;\n    state[3] += d;\n    state[4] += e;\n    /* Wipe variables */\n    a = b = c = d = e = 0;\n}\n\n\n/* SHA1Init - Initialize new context */\n\nvoid SHA1Init(SHA1_CTX* context)\n{\n    /* SHA1 initialization constants */\n    context->state[0] = 0x67452301;\n    context->state[1] = 0xEFCDAB89;\n    context->state[2] = 0x98BADCFE;\n    context->state[3] = 0x10325476;\n    context->state[4] = 0xC3D2E1F0;\n    context->count[0] = context->count[1] = 0;\n}\n\n\n/* Run your data through this. */\n\nvoid SHA1Update(SHA1_CTX* context, const unsigned char* data, unsigned int len)\n{\nunsigned int i, j;\n\n    j = (context->count[0] >> 3) & 63;\n    if ((context->count[0] += len << 3) < (len << 3)) context->count[1]++;\n    context->count[1] += (len >> 29);\n    if ((j + len) > 63) {\n\tmemcpy(&context->buffer[j], data, (i = 64-j));\n\tSHA1Transform(context->state, context->buffer);\n\tfor ( ; i + 63 < len; i += 64) {\n\t    SHA1Transform(context->state, &data[i]);\n\t}\n\tj = 0;\n    }\n    else i = 0;\n    memcpy(&context->buffer[j], &data[i], len - i);\n}\n\n\n/* Add padding and return the message digest. */\n\nvoid SHA1Final(unsigned char digest[20], SHA1_CTX* context)\n{\nuint32 i, j;\nunsigned char finalcount[8];\n\n    for (i = 0; i < 8; i++) {\n\tfinalcount[i] = (unsigned char)((context->count[(i >= 4 ? 0 : 1)]\n\t >> ((3-(i & 3)) * 8) ) & 255);  /* Endian independent */\n    }\n    SHA1Update(context, (unsigned char *)\"\\200\", 1);\n    while ((context->count[0] & 504) != 448) {\n\tSHA1Update(context, (unsigned char *)\"\\0\", 1);\n    }\n    SHA1Update(context, finalcount, 8);  /* Should cause a SHA1Transform() */\n    for (i = 0; i < 20; i++) {\n\tdigest[i] = (unsigned char)\n\t ((context->state[i>>2] >> ((3-(i & 3)) * 8) ) & 255);\n    }\n    /* Wipe variables */\n    i = j = 0;\n    memset(context->buffer, 0, 64);\n    memset(context->state, 0, 20);\n    memset(context->count, 0, 8);\n    memset(&finalcount, 0, 8);\n#ifdef SHA1HANDSOFF  /* make SHA1Transform overwrite its own static vars */\n    SHA1Transform(context->state, context->buffer);\n#endif\n}\n"
  },
  {
    "path": "package/network/services/ead/src/tinysrp/t_sha.h",
    "content": "#ifndef T_SHA_H\n#define T_SHA_H\n\n#if     !defined(P)\n#ifdef  __STDC__\n#define P(x)    x\n#else\n#define P(x)    ()\n#endif\n#endif\n\n#define SHA_DIGESTSIZE 20\n\ntypedef unsigned int uint32;\n\ntypedef struct {\n    uint32 state[5];\n    uint32 count[2];\n    unsigned char buffer[64];\n} SHA1_CTX;\n\nvoid SHA1Init P((SHA1_CTX* context));\nvoid SHA1Update P((SHA1_CTX* context, const unsigned char* data, unsigned int len));\nvoid SHA1Final P((unsigned char digest[20], SHA1_CTX* context));\n\n#endif /* T_SHA_H */\n"
  },
  {
    "path": "package/network/services/ead/src/tinysrp/t_truerand.c",
    "content": "/*\n *      Physically random numbers (very nearly uniform)\n *      D. P. Mitchell\n *      Modified by Matt Blaze 7/95\n */\n/*\n * The authors of this software are Don Mitchell and Matt Blaze.\n *              Copyright (c) 1995 by AT&T.\n * Permission to use, copy, and modify this software without fee\n * is hereby granted, provided that this entire notice is included in\n * all copies of any software which is or includes a copy or\n * modification of this software and in all copies of the supporting\n * documentation for such software.\n *\n * This software may be subject to United States export controls.\n *\n * THIS SOFTWARE IS BEING PROVIDED \"AS IS\", WITHOUT ANY EXPRESS OR IMPLIED\n * WARRANTY.  IN PARTICULAR, NEITHER THE AUTHORS NOR AT&T MAKE ANY\n * REPRESENTATION OR WARRANTY OF ANY KIND CONCERNING THE MERCHANTABILITY\n * OF THIS SOFTWARE OR ITS FITNESS FOR ANY PARTICULAR PURPOSE.\n */\n\n/*\n * WARNING: depending on the particular platform, raw_truerand()\n * output may be biased or correlated.  In general, you can expect\n * about 16 bits of \"pseudo-entropy\" out of each 32 bit word returned\n * by truerand(), but it may not be uniformly diffused.  You should\n * raw_therefore run the output through some post-whitening function\n * (like MD5 or DES or whatever) before using it to generate key\n * material.  (RSAREF's random package does this for you when you feed\n * raw_truerand() bits to the seed input function.)\n *\n * The application interface, for 8, 16, and 32 bit properly \"whitened\"\n * random numbers, can be found in trand8(), trand16(), and trand32().\n * Use those instead of calling raw_truerand() directly.\n *\n * The basic idea here is that between clock \"skew\" and various\n * hard-to-predict OS event arrivals, counting a tight loop will yield\n * a little (maybe a third of a bit or so) of \"good\" randomness per\n * interval clock tick.  This seems to work well even on unloaded\n * machines.  If there is a human operator at the machine, you should\n * augment truerand with other measure, like keyboard event timing.\n * On server machines (e.g., when you need to generate a\n * Diffie-Hellman secret) truerand alone may be good enough.\n *\n * Test these assumptions on your own platform before fielding a\n * system based on this software or these techniques.\n *\n * This software seems to work well (at 10 or so bits per\n * raw_truerand() call) on a Sun Sparc-20 under SunOS 4.1.3 and on a\n * P100 under BSDI 2.0.  You're on your own elsewhere.\n *\n */\n\n#include \"t_defines.h\"\n\n#include <signal.h>\n#include <setjmp.h>\n#include <sys/time.h>\n#include <math.h>\n#include <stdio.h>\n\n#ifdef OLD_TRUERAND\nstatic jmp_buf env;\n#endif\nstatic unsigned volatile count\n#ifndef OLD_TRUERAND\n  , done = 0\n#endif\n;\n\nstatic unsigned ocount;\nstatic unsigned buffer;\n\nstatic void\ntick()\n{\n\tstruct itimerval it, oit;\n\n\tit.it_interval.tv_sec = 0;\n\tit.it_interval.tv_usec = 0;\n\tit.it_value.tv_sec = 0;\n\tit.it_value.tv_usec = 16665;\n\tif (setitimer(ITIMER_REAL, &it, &oit) < 0)\n\t\tperror(\"tick\");\n}\n\nstatic void\ninterrupt()\n{\n\tif (count) {\n#ifdef OLD_TRUERAND\n\t\tlongjmp(env, 1);\n#else\n\t\t++done;\n\t\treturn;\n#endif\n\t}\n\n\t(void) signal(SIGALRM, interrupt);\n\ttick();\n}\n\nstatic unsigned long\nroulette()\n{\n#ifdef OLD_TRUERAND\n\tif (setjmp(env)) {\n\t\tcount ^= (count>>3) ^ (count>>6) ^ ocount;\n\t\tcount &= 0x7;\n\t\tocount=count;\n\t\tbuffer = (buffer<<3) ^ count;\n\t\treturn buffer;\n\t}\n#else\n\tdone = 0;\n#endif\n\t(void) signal(SIGALRM, interrupt);\n\tcount = 0;\n\ttick();\n#ifdef OLD_TRUERAND\n\tfor (;;)\n#else\n\twhile(done == 0)\n#endif\n\t\tcount++;        /* about 1 MHz on VAX 11/780 */\n#ifndef OLD_TRUERAND\n\tcount ^= (count>>3) ^ (count>>6) ^ ocount;\n\tcount &= 0x7;\n\tocount=count;\n\tbuffer = (buffer<<3) ^ count;\n\treturn buffer;\n#endif\n}\n\nunsigned long\nraw_truerand()\n{\n\tcount=0;\n\t(void) roulette();\n\t(void) roulette();\n\t(void) roulette();\n\t(void) roulette();\n\t(void) roulette();\n\t(void) roulette();\n\t(void) roulette();\n\t(void) roulette();\n\t(void) roulette();\n\t(void) roulette();\n\treturn roulette();\n}\n"
  },
  {
    "path": "package/network/services/ead/src/tinysrp/tconf.c",
    "content": "/*\n * Copyright (c) 1997-2000  The Stanford SRP Authentication Project\n * All Rights Reserved.\n *\n * Permission is hereby granted, free of charge, to any person obtaining\n * a copy of this software and associated documentation files (the\n * \"Software\"), to deal in the Software without restriction, including\n * without limitation the rights to use, copy, modify, merge, publish,\n * distribute, sublicense, and/or sell copies of the Software, and to\n * permit persons to whom the Software is furnished to do so, subject to\n * the following conditions:\n *\n * The above copyright notice and this permission notice shall be\n * included in all copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS-IS\" AND WITHOUT WARRANTY OF ANY KIND,\n * EXPRESS, IMPLIED OR OTHERWISE, INCLUDING WITHOUT LIMITATION, ANY\n * WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.\n *\n * IN NO EVENT SHALL STANFORD BE LIABLE FOR ANY SPECIAL, INCIDENTAL,\n * INDIRECT OR CONSEQUENTIAL DAMAGES OF ANY KIND, OR ANY DAMAGES WHATSOEVER\n * RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER OR NOT ADVISED OF\n * THE POSSIBILITY OF DAMAGE, AND ON ANY THEORY OF LIABILITY, ARISING OUT\n * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n * In addition, the following conditions apply:\n *\n * 1. Any software that incorporates the SRP authentication technology\n *    must display the following acknowlegment:\n *    \"This product uses the 'Secure Remote Password' cryptographic\n *     authentication system developed by Tom Wu (tjw@CS.Stanford.EDU).\"\n *\n * 2. Any software that incorporates all or part of the SRP distribution\n *    itself must also display the following acknowledgment:\n *    \"This product includes software developed by Tom Wu and Eugene\n *     Jhong for the SRP Distribution (http://srp.stanford.edu/srp/).\"\n *\n * 3. Redistributions in source or binary form must retain an intact copy\n *    of this copyright notice and list of conditions.\n */\n\n#include <unistd.h>     /* close getlogin */\n#include <stdlib.h>     /* atexit exit */\n#include <stdio.h>\n#include <string.h>\n\n#include \"t_pwd.h\"\n\n#define MIN_BASIS_BITS 512\n#define BASIS_BITS 2048\n\nextern int  optind;\nextern char *optarg;\n\nextern int errno;\n\nchar *progName;\n\nint  debug   = 0;\nint  verbose = 0;\nint  composite = 0;\n\nint main(argc, argv)\n     int argc;\n     char *argv[];\n{\n  char *chp;\n  char *configFile = NULL;\n  char cbuf[256];\n  char b64buf[MAXB64PARAMLEN];\n  int c, ch, i, lastidx, keylen, yesno, fsize, status, nparams;\n  FILE *efp;\n\n  struct t_preconf * tpc;\n  struct t_conf tcs;\n  struct t_conf * tc = &tcs;\n  struct t_confent * tcent;\n\n  progName = *argv;\n  if ((chp = strrchr(progName, '/')) != (char *) 0) progName = chp + 1;\n\n  while ((ch = getopt(argc, argv, \"dv2c:\")) != EOF)\n    switch(ch) {\n    case 'c':\n      configFile = optarg;\n      break;\n    case 'v':\n      verbose++;\n      break;\n    case 'd':\n      debug++;\n      break;\n    case '2':\n      composite++;\n      break;\n    default:\n      fprintf(stderr, \"usage: %s [-dv2] [-c configfile]\\n\", progName);\n      exit(1);\n    }\n\n  argc -= optind;\n  argv += optind;\n\n  lastidx = 0;\n  keylen = 0;\n\n  tcent = t_newconfent(tc);\n\n  printf(\"\\nThis program will generate a set of parameters for the EPS\\n\");\n  printf(\"password file.  The size of these parameters, measured in bits,\\n\");\n  printf(\"determines the level of security offered by SRP, and is related\\n\");\n  printf(\"to the security of similarly-sized RSA or Diffie-Hellman keys.\\n\");\n  printf(\"Choosing a predefined field is generally preferable to generating\\n\");\n  printf(\"a new field because clients can avoid costly parameter verification.\\n\");\n  printf(\"Either way, the values generated by this program are public and\\n\");\n  printf(\"can even shared between systems.\\n\");\n\n  printf(\"\\nEnter the new field size, in bits.  Suggested sizes:\\n\\n\");\n  printf(\" 512 (fast, minimally secure)\\n\");\n  printf(\" 768 (moderate security)\\n\");\n  printf(\"1024 (most popular default)\\n\");\n  printf(\"1536 (additional security, possibly slow)\\n\");\n  printf(\"2048 (maximum supported security level)\\n\");\n  printf(\"\\nField size (%d to %d): \", MIN_BASIS_BITS, BASIS_BITS);\n\n  fgets(cbuf, sizeof(cbuf), stdin);\n  fsize = atoi(cbuf);\n  if(fsize < MIN_BASIS_BITS || fsize > BASIS_BITS) {\n    fprintf(stderr, \"%s: field size must be between %d and %d\\n\",\n\t    progName, MIN_BASIS_BITS, BASIS_BITS);\n    exit(1);\n  }\n\n  if(fsize <= keylen)\n    fprintf(stderr, \"Warning: new field size is not larger than old field size\\n\");\n\n  printf(\"\\nInitializing random number generator...\");\n  fflush(stdout);\n  t_initrand();\n\n  if(composite)\n    printf(\"done.\\n\\nGenerating a %d-bit composite with safe prime factors.  This may take a while.\\n\", fsize);\n  else\n    printf(\"done.\\n\\nGenerating a %d-bit safe prime.  This may take a while.\\n\", fsize);\n\n  while((tcent = (composite ? t_makeconfent_c(tc, fsize) :\n\t\t\t      t_makeconfent(tc, fsize))) == NULL)\n    printf(\"Parameter generation failed, retrying...\\n\");\n  tcent->index = lastidx + 1;\n\n  printf(\"\\nParameters successfully generated.\\n\");\n  printf(\"N = [%s]\\n\", t_tob64(b64buf,\n\t\t\t       tcent->modulus.data, tcent->modulus.len));\n  printf(\"g = [%s]\\n\", t_tob64(b64buf,\n\t\t\t       tcent->generator.data, tcent->generator.len));\n  printf(\"\\nYou must update the pre_params array in t_getconf.c\\n\");\n}\n"
  },
  {
    "path": "package/network/services/ead/src/tinysrp/tinysrp.c",
    "content": "/* This bit implements a simple API for using the SRP library over sockets. */\n\n#include <stdio.h>\n#include <string.h>\n#include <stdlib.h>\n#include <unistd.h>\n#include <sys/types.h>\n#include <sys/socket.h>\n#include \"t_defines.h\"\n#include \"t_pwd.h\"\n#include \"t_server.h\"\n#include \"t_client.h\"\n#include \"tinysrp.h\"\n\n#ifndef MSG_WAITALL\n#ifdef linux\n#define MSG_WAITALL 0x100       /* somehow not defined on my box */\n#endif\n#endif\n\n/* This is called by the client with a connected socket, username, and\npassphrase.  pass can be NULL in which case the user is queried. */\n\nint tsrp_client_authenticate(int s, char *user, char *pass, TSRP_SESSION *tsrp)\n{\n\tint i, index;\n\tunsigned char username[MAXUSERLEN + 1], sbuf[MAXSALTLEN];\n\tunsigned char msgbuf[MAXPARAMLEN + 1], bbuf[MAXPARAMLEN];\n\tunsigned char passbuf[128], *skey;\n\tstruct t_client *tc;\n\tstruct t_preconf *tcp;          /* @@@ should go away */\n\tstruct t_num salt, *A, B;\n\n\t/* Send the username. */\n\n\ti = strlen(user);\n\tif (i > MAXUSERLEN) {\n\t\ti = MAXUSERLEN;\n\t}\n\tmsgbuf[0] = i;\n\tmemcpy(msgbuf + 1, user, i);\n\tif (send(s, msgbuf, i + 1, 0) < 0) {\n\t\treturn 0;\n\t}\n\tmemcpy(username, user, i);\n\tusername[i] = '\\0';\n\n\t/* Get the prime index and salt. */\n\n\ti = recv(s, msgbuf, 2, MSG_WAITALL);\n\tif (i <= 0) {\n\t\treturn 0;\n\t}\n\tindex = msgbuf[0];\n\tif (index <= 0 || index > t_getprecount()) {\n\t\treturn 0;\n\t}\n\ttcp = t_getpreparam(index - 1);\n\tsalt.len = msgbuf[1];\n\tif (salt.len > MAXSALTLEN) {\n\t\treturn 0;\n\t}\n\tsalt.data = sbuf;\n\ti = recv(s, sbuf, salt.len, MSG_WAITALL);\n\tif (i <= 0) {\n\t\treturn 0;\n\t}\n\n\t/* @@@ t_clientopen() needs a variant that takes the index */\n\n\ttc = t_clientopen(username, &tcp->modulus, &tcp->generator, &salt);\n\tif (tc == NULL) {\n\t\treturn 0;\n\t}\n\n\t/* Calculate A and send it to the server. */\n\n\tA = t_clientgenexp(tc);\n\tmsgbuf[0] = A->len - 1;         /* len is max 256 */\n\tmemcpy(msgbuf + 1, A->data, A->len);\n\tif (send(s, msgbuf, A->len + 1, 0) < 0) {\n\t\treturn 0;\n\t}\n\n\t/* Ask the user for the passphrase. */\n\n\tif (pass == NULL) {\n\t\tt_getpass(passbuf, sizeof(passbuf), \"Enter password:\");\n\t\tpass = passbuf;\n\t}\n\tt_clientpasswd(tc, pass);\n\n\t/* Get B from the server. */\n\n\ti = recv(s, msgbuf, 1, 0);\n\tif (i <= 0) {\n\t\treturn 0;\n\t}\n\tB.len = msgbuf[0] + 1;\n\tB.data = bbuf;\n\ti = recv(s, bbuf, B.len, MSG_WAITALL);\n\tif (i <= 0) {\n\t\treturn 0;\n\t}\n\n\t/* Compute the session key. */\n\n\tskey = t_clientgetkey(tc, &B);\n\tif (skey == NULL) {\n\t\treturn 0;\n\t}\n\n\t/* Send the response. */\n\n\tif (send(s, t_clientresponse(tc), RESPONSE_LEN, 0) < 0) {\n\t\treturn 0;\n\t}\n\n\t/* Get the server's response. */\n\n\ti = recv(s, msgbuf, RESPONSE_LEN, MSG_WAITALL);\n\tif (i <= 0) {\n\t\treturn 0;\n\t}\n\tif (t_clientverify(tc, msgbuf) != 0) {\n\t\treturn 0;\n\t}\n\n\t/* All done.  Now copy the key and clean up. */\n\n\tif (tsrp) {\n\t\tmemcpy(tsrp->username, username, strlen(username) + 1);\n\t\tmemcpy(tsrp->key, skey, SESSION_KEY_LEN);\n\t}\n\tt_clientclose(tc);\n\n\treturn 1;\n}\n\n/* This is called by the server with a connected socket. */\n\nint tsrp_server_authenticate(int s, TSRP_SESSION *tsrp)\n{\n\tint i, j;\n\tunsigned char username[MAXUSERLEN], *skey;\n\tunsigned char msgbuf[MAXPARAMLEN + 1], abuf[MAXPARAMLEN];\n\tstruct t_server *ts;\n\tstruct t_num A, *B;\n\n\t/* Get the username. */\n\n\ti = recv(s, msgbuf, 1, 0);\n\tif (i <= 0) {\n\t\treturn 0;\n\t}\n\tj = msgbuf[0];\n\ti = recv(s, username, j, MSG_WAITALL);\n\tif (i <= 0) {\n\t\treturn 0;\n\t}\n\tusername[j] = '\\0';\n\n\tts = t_serveropen(username);\n\tif (ts == NULL) {\n\t\treturn 0;\n\t}\n\n\t/* Send the prime index and the salt. */\n\n\tmsgbuf[0] = ts->index;                  /* max 256 primes... */\n\ti = ts->s.len;\n\tmsgbuf[1] = i;\n\tmemcpy(msgbuf + 2, ts->s.data, i);\n\tif (send(s, msgbuf, i + 2, 0) < 0) {\n\t\treturn 0;\n\t}\n\n\t/* Calculate B while we're waiting. */\n\n\tB = t_servergenexp(ts);\n\n\t/* Get A from the client. */\n\n\ti = recv(s, msgbuf, 1, 0);\n\tif (i <= 0) {\n\t\treturn 0;\n\t}\n\tA.len = msgbuf[0] + 1;\n\tA.data = abuf;\n\ti = recv(s, abuf, A.len, MSG_WAITALL);\n\tif (i <= 0) {\n\t\treturn 0;\n\t}\n\n\t/* Now send B. */\n\n\tmsgbuf[0] = B->len - 1;\n\tmemcpy(msgbuf + 1, B->data, B->len);\n\tif (send(s, msgbuf, B->len + 1, 0) < 0) {\n\t\treturn 0;\n\t}\n\n\t/* Calculate the session key while we're waiting. */\n\n\tskey = t_servergetkey(ts, &A);\n\tif (skey == NULL) {\n\t\treturn 0;\n\t}\n\n\t/* Get the response from the client. */\n\n\ti = recv(s, msgbuf, RESPONSE_LEN, MSG_WAITALL);\n\tif (i <= 0) {\n\t\treturn 0;\n\t}\n\tif (t_serververify(ts, msgbuf) != 0) {\n\t\treturn 0;\n\t}\n\n\t/* Client authenticated.  Now authenticate ourselves to the client. */\n\n\tif (send(s, t_serverresponse(ts), RESPONSE_LEN, 0) < 0) {\n\t\treturn 0;\n\t}\n\n\t/* Copy the key and clean up. */\n\n\tif (tsrp) {\n\t\tmemcpy(tsrp->username, username, strlen(username) + 1);\n\t\tmemcpy(tsrp->key, skey, SESSION_KEY_LEN);\n\t}\n\tt_serverclose(ts);\n\n\treturn 1;\n}\n"
  },
  {
    "path": "package/network/services/ead/src/tinysrp/tinysrp.h",
    "content": "/* Simple API for the tinysrp library. */\n\n#ifndef T_PWD_H\n#define MAXUSERLEN      32\n#define SESSION_KEY_LEN 40      /* 320-bit session key */\n#endif\n\ntypedef struct {\n\tchar username[MAXUSERLEN + 1];\n\tunsigned char key[SESSION_KEY_LEN];\n} TSRP_SESSION;\n\n/* These functions are passed a connected socket, and return true for a\nsuccessful authentication.  If tsrp is not NULL, the username and key\nfields are filled in. */\n\nextern int tsrp_server_authenticate(int s, TSRP_SESSION *tsrp);\nextern int tsrp_client_authenticate(int s, char *user, char *pass, TSRP_SESSION *tsrp);\n"
  },
  {
    "path": "package/network/services/ead/src/tinysrp/tpasswd",
    "content": "moo:A9lHvOGAMJvw1m3vcDsQRUFovh6/QUmLDKqwhv.drKQzbE9nS7HrOZLUPx2MmS6ewwybN8RHqpWqnUJRCMFT14FMbYXR7kYNUUQNx43A7F.xrVOU7tlFq5NjoK9sfFtp6PMdbIOP5wzWmipiNFlCOu4sjlSZb.o7C1chLzTKU.0:19AI0Hc9jEkdFc:5\nnew user:1FsanML2fbTOEsa072bLjyRD1LEqoRD2GwElfN0VmHeR.FAg5A.2.G5bTjIHmMmHL60kgoAHJZhRrgopalYmujlyAuQoKiHJb98SHm1oJaQ9nl/DrZCvfyw5LpVMqg.CupdiWz6OtmOz8fwC96ItExFnNDt6SmsVDIOn4HqXG6C0lLaqEvcqlN3gFDlJXyP2yldM.LJ1TkHTHmA3DjRkmWEUL3mWEgzkEHyPcRB3Jd5ncDT7jaNbJTTLRoOtgRsaqE7OXuPADoK8MGBcUquYBRrGwyU4Y/wW4gLc3QmV793zxkk.P3.dxkLSjro/Kk94D7kC6fx3K9tadLJyzd94rr:3v/KRlxT0.oYF1:1\n"
  },
  {
    "path": "package/network/services/ead/src/tinysrp/tphrase.c",
    "content": "/* Add passphrases to the tpasswd file.  Use the last entry in the config\nfile by default or a particular one specified by index. */\n\n#include <stdio.h>\n#include <stdlib.h>\n#include <string.h>\n#include <unistd.h>\n#include <sys/types.h>\n#include <sys/stat.h>\n#include \"config.h\"\n#include \"t_pwd.h\"\n#include \"t_read.h\"\n#include \"t_sha.h\"\n#include \"t_defines.h\"\n\nchar *Progname;\nchar Usage[] = \"usage: %s [-n configindex] [-p passfile] user\\n\";\n#define USAGE() fprintf(stderr, Usage, Progname)\n\nvoid doit(char *);\n\nint Configindex = -1;\nchar *Passfile = DEFAULT_PASSWD;\n\nint main(int argc, char **argv)\n{\n\tint c;\n\n\tProgname = *argv;\n\n\t/* Parse option arguments. */\n\n\twhile ((c = getopt(argc, argv, \"n:p:\")) != EOF) {\n\t\tswitch (c) {\n\n\t\tcase 'n':\n\t\t\tConfigindex = atoi(optarg);\n\t\t\tbreak;\n\n\t\tcase 'p':\n\t\t\tPassfile = optarg;\n\t\t\tbreak;\n\n\t\tdefault:\n\t\t\tUSAGE();\n\t\t\texit(1);\n\t\t}\n\t}\n\targc -= optind;\n\targv += optind;\n\n\tif (argc != 1) {\n\t\tUSAGE();\n\t\texit(1);\n\t}\n\tdoit(argv[0]);\n\n\treturn 0;\n}\n\nvoid doit(char *name)\n{\n\tchar passphrase[128], passphrase1[128];\n\tFILE *f;\n\tstruct t_confent *tcent;\n\tstruct t_pw eps_passwd;\n\n\t/* Get the config entry. */\n\n\tif (Configindex <= 0) {\n\t\tConfigindex = t_getprecount();\n\t}\n\ttcent = gettcid(Configindex);\n\tif (tcent == NULL) {\n\t\tfprintf(stderr, \"Invalid configuration file entry.\\n\");\n\t\texit(1);\n\t}\n\n\t/* Ask for the passphrase twice. */\n\n\tprintf(\"Setting passphrase for %s\\n\", name);\n\n\tif (t_getpass(passphrase, sizeof(passphrase), \"Enter passphrase: \") < 0) {\n\t\texit(1);\n\t}\n\tif (t_getpass(passphrase1, sizeof(passphrase1), \"Verify: \") < 0) {\n\t\texit(1);\n\t}\n\tif (strcmp(passphrase, passphrase1) != 0) {\n\t\tfprintf(stderr, \"mismatch\\n\");\n\t\texit(1);\n\t}\n\n\t/* Create the passphrase verifier. */\n\n\tt_makepwent(&eps_passwd, name, passphrase, NULL, tcent);\n\n\t/* Don't need these anymore. */\n\n\tmemset(passphrase, 0, sizeof(passphrase));\n\tmemset(passphrase1, 0, sizeof(passphrase1));\n\n\t/* See if the passphrase file is there; create it if not. */\n\n\tif ((f = fopen(Passfile, \"r+\")) == NULL) {\n\t\tcreat(Passfile, 0400);\n\t} else {\n\t\tfclose(f);\n\t}\n\n\t/* Change the passphrase. */\n\n\tif (t_changepw(Passfile, &eps_passwd.pebuf) < 0) {\n\t\tfprintf(stderr, \"Error changing passphrase\\n\");\n\t\texit(1);\n\t}\n}\n\n/* TODO: Implement a more general method to handle delete/change */\n\n_TYPE( int )\nt_changepw(pwname, diff)\n     const char * pwname;\n     const struct t_pwent * diff;\n{\n  char * bakfile;\n  char * bakfile2;\n  struct stat st;\n  FILE * passfp;\n  FILE * bakfp;\n\n  if(pwname == NULL)\n    pwname = DEFAULT_PASSWD;\n\n  if((passfp = fopen(pwname, \"rb\")) == NULL || fstat(fileno(passfp), &st) < 0)\n    return -1;\n\n  if((bakfile = malloc(strlen(pwname) + 5)) == NULL) {\n    fclose(passfp);\n    return -1;\n  }\n  else if((bakfile2 = malloc(strlen(pwname) + 5)) == NULL) {\n    fclose(passfp);\n    free(bakfile);\n    return -1;\n  }\n\n  sprintf(bakfile, \"%s.bak\", pwname);\n  sprintf(bakfile2, \"%s.sav\", pwname);\n\n  if((bakfp = fopen(bakfile2, \"wb\")) == NULL &&\n     (unlink(bakfile2) < 0 || (bakfp = fopen(bakfile2, \"wb\")) == NULL)) {\n    fclose(passfp);\n    free(bakfile);\n    free(bakfile2);\n    return -1;\n  }\n\n#ifdef NO_FCHMOD\n  chmod(bakfile2, st.st_mode & 0777);\n#else\n  fchmod(fileno(bakfp), st.st_mode & 0777);\n#endif\n\n  t_pwcopy(bakfp, passfp, diff);\n\n  fclose(bakfp);\n  fclose(passfp);\n\n#ifdef USE_RENAME\n  unlink(bakfile);\n  if(rename(pwname, bakfile) < 0) {\n    free(bakfile);\n    free(bakfile2);\n    return -1;\n  }\n  if(rename(bakfile2, pwname) < 0) {\n    free(bakfile);\n    free(bakfile2);\n    return -1;\n  }\n#else\n  unlink(bakfile);\n  link(pwname, bakfile);\n  unlink(pwname);\n  link(bakfile2, pwname);\n  unlink(bakfile2);\n#endif\n  free(bakfile);\n  free(bakfile2);\n\n  return 0;\n}\n\n_TYPE( struct t_pwent * )\nt_makepwent(tpw, user, pass, salt, confent)\n     struct t_pw * tpw;\n     const char * user;\n     const char * pass;\n     const struct t_num * salt;\n     const struct t_confent * confent;\n{\n  BigInteger x, v, n, g;\n  unsigned char dig[SHA_DIGESTSIZE];\n  SHA1_CTX ctxt;\n\n  tpw->pebuf.name = tpw->userbuf;\n  tpw->pebuf.password.data = tpw->pwbuf;\n  tpw->pebuf.salt.data = tpw->saltbuf;\n\n  strncpy(tpw->pebuf.name, user, MAXUSERLEN);\n  tpw->pebuf.index = confent->index;\n\n  if(salt) {\n    tpw->pebuf.salt.len = salt->len;\n    memcpy(tpw->pebuf.salt.data, salt->data, salt->len);\n  }\n  else {\n    memset(dig, 0, SALTLEN);            /* salt is 80 bits */\n    tpw->pebuf.salt.len = SALTLEN;\n    do {\n      t_random(tpw->pebuf.salt.data, SALTLEN);\n    } while(memcmp(tpw->pebuf.salt.data, dig, SALTLEN) == 0);\n    if(tpw->pebuf.salt.data[0] == 0)\n      tpw->pebuf.salt.data[0] = 0xff;\n  }\n\n  n = BigIntegerFromBytes(confent->modulus.data, confent->modulus.len);\n  g = BigIntegerFromBytes(confent->generator.data, confent->generator.len);\n  v = BigIntegerFromInt(0);\n\n  SHA1Init(&ctxt);\n  SHA1Update(&ctxt, user, strlen(user));\n  SHA1Update(&ctxt, \":\", 1);\n  SHA1Update(&ctxt, pass, strlen(pass));\n  SHA1Final(dig, &ctxt);\n\n  SHA1Init(&ctxt);\n  SHA1Update(&ctxt, tpw->pebuf.salt.data, tpw->pebuf.salt.len);\n  SHA1Update(&ctxt, dig, sizeof(dig));\n  SHA1Final(dig, &ctxt);\n\n  /* x = H(s, H(u, ':', p)) */\n  x = BigIntegerFromBytes(dig, sizeof(dig));\n\n  BigIntegerModExp(v, g, x, n);\n  tpw->pebuf.password.len = BigIntegerToBytes(v, tpw->pebuf.password.data);\n\n  BigIntegerFree(v);\n  BigIntegerFree(x);\n  BigIntegerFree(g);\n  BigIntegerFree(n);\n\n  return &tpw->pebuf;\n}\n\nint\nt_pwcopy(pwdest, pwsrc, diff)\n     FILE * pwdest;\n     FILE * pwsrc;\n     struct t_pwent * diff;\n{\n  struct t_pw * src;\n  struct t_pwent * ent;\n\n  if((src = t_openpw(pwsrc)) == NULL)\n    return -1;\n\n  while((ent = t_getpwent(src)) != NULL)\n    if(diff && strcmp(diff->name, ent->name) == 0) {\n      t_putpwent(diff, pwdest);\n      diff = NULL;\n    }\n    else\n      t_putpwent(ent, pwdest);\n\n  if(diff)\n    t_putpwent(diff, pwdest);\n\n  return 0;\n}\n\n_TYPE( struct t_pwent * )\nt_getpwent(tpw)\n     struct t_pw * tpw;\n{\n  char indexbuf[16];\n  char passbuf[MAXB64PARAMLEN];\n  char saltstr[MAXB64SALTLEN];\n\n#ifdef ENABLE_YP\n  struct t_passwd * nisent;\n  /* FIXME: should tell caller to get conf entry from NIS also */\n\n  if(tpw->state == IN_NIS) {\n    nisent = _yp_gettpent();\n    if(nisent != NULL) {\n      savepwent(tpw, &nisent->tp);\n      return &tpw->pebuf;\n    }\n    tpw->state = FILE_NIS;\n  }\n#endif\n\n  while(1) {\n    if(t_nextfield(tpw->instream, tpw->userbuf, MAXUSERLEN) > 0) {\n#ifdef ENABLE_YP\n      if(tpw->state == FILE_NIS && *tpw->userbuf == '+') {\n\tt_nextline(tpw->instream);\n\tif(strlen(tpw->userbuf) > 1) {  /* +name:... */\n\t  nisent = _yp_gettpnam(tpw->userbuf + 1);\n\t  if(nisent != NULL) {\n\t    savepwent(tpw, nisent);\n\t    return &tpw->pebuf;\n\t  }\n\t}\n\telse {  /* +:... */\n\t  tpw->state = IN_NIS;\n\t  _yp_settpent();\n\t  return t_getpwent(tpw);\n\t}\n      }\n#endif\n      if(t_nextfield(tpw->instream, passbuf, MAXB64PARAMLEN) > 0 &&\n\t (tpw->pebuf.password.len = t_fromb64(tpw->pwbuf, passbuf)) > 0 &&\n\t t_nextfield(tpw->instream, saltstr, MAXB64SALTLEN) > 0 &&\n\t (tpw->pebuf.salt.len = t_fromb64(tpw->saltbuf, saltstr)) > 0 &&\n\t t_nextfield(tpw->instream, indexbuf, 16) > 0 &&\n\t (tpw->pebuf.index = atoi(indexbuf)) > 0) {\n\ttpw->pebuf.name = tpw->userbuf;\n\ttpw->pebuf.password.data = tpw->pwbuf;\n\ttpw->pebuf.salt.data = tpw->saltbuf;\n\tt_nextline(tpw->instream);\n\treturn &tpw->pebuf;\n      }\n    }\n    if(t_nextline(tpw->instream) < 0)\n      return NULL;\n  }\n}\n\n_TYPE( void )\nt_putpwent(ent, fp)\n     const struct t_pwent * ent;\n     FILE * fp;\n{\n  char strbuf[MAXB64PARAMLEN];\n  char saltbuf[MAXB64SALTLEN];\n\n  fprintf(fp, \"%s:%s:%s:%d\\n\", ent->name,\n\t  t_tob64(strbuf, ent->password.data, ent->password.len),\n\t  t_tob64(saltbuf, ent->salt.data, ent->salt.len), ent->index);\n}\n\n"
  },
  {
    "path": "package/network/services/hostapd/Config.in",
    "content": "# wpa_supplicant config\nconfig WPA_RFKILL_SUPPORT\n\tbool \"Add rfkill support\"\n\tdepends on PACKAGE_wpa-supplicant || \\\n\t\t   PACKAGE_wpa-supplicant-openssl || \\\n\t\t   PACKAGE_wpa-supplicant-wolfssl || \\\n\t\t   PACKAGE_wpa-supplicant-mesh-openssl || \\\n\t\t   PACKAGE_wpa-supplicant-mesh-wolfssl || \\\n\t\t   PACKAGE_wpa-supplicant-basic || \\\n\t\t   PACKAGE_wpa-supplicant-mini || \\\n\t\t   PACKAGE_wpa-supplicant-p2p || \\\n\t\t   PACKAGE_wpad || \\\n\t\t   PACKAGE_wpad-openssl || \\\n\t\t   PACKAGE_wpad-wolfssl || \\\n\t\t   PACKAGE_wpad-basic || \\\n\t\t   PACKAGE_wpad-basic-openssl || \\\n\t\t   PACKAGE_wpad-basic-wolfssl || \\\n\t\t   PACKAGE_wpad-mini || \\\n\t\t   PACKAGE_wpad-mesh-openssl || \\\n\t\t   PACKAGE_wpad-mesh-wolfssl\n\tdefault n\n\nconfig WPA_MSG_MIN_PRIORITY\n\tint \"Minimum debug message priority\"\n\tdepends on PACKAGE_wpa-supplicant || \\\n\t\t   PACKAGE_wpa-supplicant-openssl || \\\n\t\t   PACKAGE_wpa-supplicant-wolfssl || \\\n\t\t   PACKAGE_wpa-supplicant-mesh-openssl || \\\n\t\t   PACKAGE_wpa-supplicant-mesh-wolfssl || \\\n\t\t   PACKAGE_wpa-supplicant-basic || \\\n\t\t   PACKAGE_wpa-supplicant-mini || \\\n\t\t   PACKAGE_wpa-supplicant-p2p || \\\n\t\t   PACKAGE_wpad || \\\n\t\t   PACKAGE_wpad-openssl || \\\n\t\t   PACKAGE_wpad-wolfssl || \\\n\t\t   PACKAGE_wpad-basic || \\\n\t\t   PACKAGE_wpad-basic-openssl || \\\n\t\t   PACKAGE_wpad-basic-wolfssl || \\\n\t\t   PACKAGE_wpad-mini || \\\n\t\t   PACKAGE_wpad-mesh-openssl || \\\n\t\t   PACKAGE_wpad-mesh-wolfssl\n\tdefault 3\n\thelp\n\t  Useful values are:\n\t    0 = all messages\n\t\t1 = raw message dumps\n\t\t2 = most debugging messages\n\t\t3 = info messages\n\t\t4 = warnings\n\t\t5 = errors\n\nconfig WPA_WOLFSSL\n\tbool\n\tdefault PACKAGE_wpa-supplicant-wolfssl ||\\\n\t        PACKAGE_wpad-wolfssl ||\\\n\t        PACKAGE_wpad-basic-wolfssl || \\\n\t        PACKAGE_wpad-mesh-wolfssl ||\\\n\t        PACKAGE_eapol-test-wolfssl\n\tselect WOLFSSL_HAS_AES_CCM\n\tselect WOLFSSL_HAS_ARC4\n\tselect WOLFSSL_HAS_DH\n\tselect WOLFSSL_HAS_OCSP\n\tselect WOLFSSL_HAS_SESSION_TICKET\n\tselect WOLFSSL_HAS_WPAS\n\nconfig DRIVER_WEXT_SUPPORT\n\tbool\n\tdefault n\n\nconfig DRIVER_11N_SUPPORT\n\tbool\n\tdefault n\n\nconfig DRIVER_11AC_SUPPORT\n\tbool\n\tdefault n\n\nconfig DRIVER_11AX_SUPPORT\n\tbool\n\tdefault n\n\nconfig WPA_ENABLE_WEP\n\tbool \"Enable support for unsecure and obsolete WEP\"\n\thelp\n\t  Wired equivalent privacy (WEP) is an obsolete cryptographic data\n\t  confidentiality algorithm that is not considered secure. It should not be used\n\t  for anything anymore. The functionality needed to use WEP is available in the\n\t  current hostapd release under this optional build parameter and completely\n\t  removed in a future release.\n"
  },
  {
    "path": "package/network/services/hostapd/Makefile",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2006-2021 OpenWrt.org\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=hostapd\nPKG_RELEASE:=$(AUTORELEASE)\n\nPKG_SOURCE_URL:=http://w1.fi/hostap.git\nPKG_SOURCE_PROTO:=git\nPKG_SOURCE_DATE:=2022-01-16\nPKG_SOURCE_VERSION:=cff80b4f7d3c0a47c052e8187d671710f48939e4\nPKG_MIRROR_HASH:=712965bfa11a2e601d3e1c9a51a2cf3cffc6db89abafb3df3eb0cfd83c64705b\n\nPKG_MAINTAINER:=Felix Fietkau <nbd@nbd.name>\nPKG_LICENSE:=BSD-3-Clause\nPKG_CPE_ID:=cpe:/a:w1.fi:hostapd\n\nPKG_BUILD_PARALLEL:=1\nPKG_ASLR_PIE_REGULAR:=1\n\nPKG_CONFIG_DEPENDS:= \\\n\tCONFIG_PACKAGE_kmod-ath9k \\\n\tCONFIG_PACKAGE_kmod-cfg80211 \\\n\tCONFIG_PACKAGE_hostapd \\\n\tCONFIG_PACKAGE_hostapd-basic \\\n\tCONFIG_PACKAGE_hostapd-mini \\\n\tCONFIG_WPA_RFKILL_SUPPORT \\\n\tCONFIG_DRIVER_WEXT_SUPPORT \\\n\tCONFIG_DRIVER_11N_SUPPORT \\\n\tCONFIG_DRIVER_11AC_SUPPORT \\\n\tCONFIG_DRIVER_11AX_SUPPORT \\\n\tCONFIG_WPA_ENABLE_WEP\n\nEAPOL_TEST_PROVIDERS:=eapol-test eapol-test-openssl eapol-test-wolfssl\n\nSUPPLICANT_PROVIDERS:=\nHOSTAPD_PROVIDERS:=\n\nLOCAL_TYPE=$(strip \\\n\t\t$(if $(findstring wpad,$(BUILD_VARIANT)),wpad, \\\n\t\t$(if $(findstring supplicant,$(BUILD_VARIANT)),supplicant, \\\n\t\thostapd \\\n\t\t)))\n\nLOCAL_AND_LIB_VARIANT=$(patsubst hostapd-%,%,\\\n\t\t      $(patsubst wpad-%,%,\\\n\t\t      $(patsubst supplicant-%,%,\\\n\t\t      $(BUILD_VARIANT)\\\n\t\t      )))\n\nLOCAL_VARIANT=$(patsubst %-internal,%,\\\n\t      $(patsubst %-openssl,%,\\\n\t      $(patsubst %-wolfssl,%,\\\n\t      $(LOCAL_AND_LIB_VARIANT)\\\n\t      )))\n\nSSL_VARIANT=$(strip \\\n\t\t$(if $(findstring openssl,$(LOCAL_AND_LIB_VARIANT)),openssl,\\\n\t\t$(if $(findstring wolfssl,$(LOCAL_AND_LIB_VARIANT)),wolfssl,\\\n\t\tinternal\\\n\t\t)))\n\nCONFIG_VARIANT:=$(LOCAL_VARIANT)\nifeq ($(LOCAL_VARIANT),mesh)\n  CONFIG_VARIANT:=full\nendif\n\ninclude $(INCLUDE_DIR)/package.mk\n\nSTAMP_CONFIGURED:=$(STAMP_CONFIGURED)_$(CONFIG_WPA_MSG_MIN_PRIORITY)\n\n\nifneq ($(CONFIG_DRIVER_11N_SUPPORT),)\n  HOSTAPD_IEEE80211N:=y\nendif\n\nifneq ($(CONFIG_DRIVER_11AC_SUPPORT),)\n  HOSTAPD_IEEE80211AC:=y\nendif\n\nifneq ($(CONFIG_DRIVER_11AX_SUPPORT),)\n  HOSTAPD_IEEE80211AX:=y\nendif\n\nDRIVER_MAKEOPTS= \\\n\tCONFIG_ACS=$(CONFIG_PACKAGE_kmod-cfg80211) \\\n\tCONFIG_DRIVER_NL80211=$(CONFIG_PACKAGE_kmod-cfg80211) \\\n\tCONFIG_IEEE80211N=$(HOSTAPD_IEEE80211N) \\\n\tCONFIG_IEEE80211AC=$(HOSTAPD_IEEE80211AC) \\\n\tCONFIG_IEEE80211AX=$(HOSTAPD_IEEE80211AX) \\\n\tCONFIG_DRIVER_WEXT=$(CONFIG_DRIVER_WEXT_SUPPORT) \\\n\nifeq ($(SSL_VARIANT),openssl)\n  DRIVER_MAKEOPTS += CONFIG_TLS=openssl CONFIG_SAE=y\n  TARGET_LDFLAGS += -lcrypto -lssl\n\n  ifeq ($(LOCAL_VARIANT),basic)\n    DRIVER_MAKEOPTS += CONFIG_OWE=y\n  endif\n  ifeq ($(LOCAL_VARIANT),mesh)\n    DRIVER_MAKEOPTS += CONFIG_AP=y CONFIG_MESH=y\n  endif\n  ifeq ($(LOCAL_VARIANT),full)\n    DRIVER_MAKEOPTS += CONFIG_OWE=y CONFIG_SUITEB192=y CONFIG_AP=y CONFIG_MESH=y\n  endif\nendif\n\nifeq ($(SSL_VARIANT),wolfssl)\n  DRIVER_MAKEOPTS += CONFIG_TLS=wolfssl CONFIG_SAE=y\n  TARGET_LDFLAGS += -lwolfssl\n\n  ifeq ($(LOCAL_VARIANT),basic)\n    DRIVER_MAKEOPTS += CONFIG_OWE=y\n  endif\n  ifeq ($(LOCAL_VARIANT),mesh)\n    DRIVER_MAKEOPTS += CONFIG_AP=y CONFIG_MESH=y CONFIG_WPS_NFC=1\n  endif\n  ifeq ($(LOCAL_VARIANT),full)\n    DRIVER_MAKEOPTS += CONFIG_OWE=y CONFIG_SUITEB192=y CONFIG_AP=y CONFIG_MESH=y CONFIG_WPS_NFC=1\n  endif\nendif\n\nifneq ($(LOCAL_TYPE),hostapd)\n  ifdef CONFIG_WPA_RFKILL_SUPPORT\n    DRIVER_MAKEOPTS += NEED_RFKILL=y\n  endif\nendif\n\nifdef CONFIG_USE_GLIBC\n  TARGET_LDFLAGS += -lrt\n  TARGET_LDFLAGS_C += -lrt\nendif\n\nDRV_DEPENDS:=+PACKAGE_kmod-cfg80211:libnl-tiny\n\n\ndefine Package/hostapd/Default\n  SECTION:=net\n  CATEGORY:=Network\n  SUBMENU:=WirelessAPD\n  TITLE:=IEEE 802.1x Authenticator\n  URL:=http://hostap.epitest.fi/\n  DEPENDS:=$(DRV_DEPENDS) +hostapd-common +libubus\n  EXTRA_DEPENDS:=hostapd-common (=$(PKG_VERSION)-$(PKG_RELEASE))\n  USERID:=network=101:network=101\n  PROVIDES:=hostapd\n  CONFLICTS:=$(HOSTAPD_PROVIDERS)\n  HOSTAPD_PROVIDERS+=$(1)\nendef\n\ndefine Package/hostapd\n$(call Package/hostapd/Default,$(1))\n  TITLE+= (built-in full)\n  VARIANT:=full-internal\nendef\n\ndefine Package/hostapd/description\n This package contains a full featured IEEE 802.1x/WPA/EAP/RADIUS\n Authenticator.\nendef\n\ndefine Package/hostapd-openssl\n$(call Package/hostapd/Default,$(1))\n  TITLE+= (OpenSSL full)\n  VARIANT:=full-openssl\n  DEPENDS+=+libopenssl\nendef\n\nPackage/hostapd-openssl/description = $(Package/hostapd/description)\n\ndefine Package/hostapd-wolfssl\n$(call Package/hostapd/Default,$(1))\n  TITLE+= (wolfSSL full)\n  VARIANT:=full-wolfssl\n  DEPENDS+=+libwolfssl\nendef\n\nPackage/hostapd-wolfssl/description = $(Package/hostapd/description)\n\ndefine Package/hostapd-basic\n$(call Package/hostapd/Default,$(1))\n  TITLE+= (WPA-PSK, 11r, 11w)\n  VARIANT:=basic\nendef\n\ndefine Package/hostapd-basic/description\n This package contains a basic IEEE 802.1x/WPA Authenticator with WPA-PSK, 802.11r and 802.11w support.\nendef\n\ndefine Package/hostapd-basic-openssl\n$(call Package/hostapd/Default,$(1))\n  TITLE+= (WPA-PSK, 11r and 11w)\n  VARIANT:=basic-openssl\n  DEPENDS+=+libopenssl\nendef\n\ndefine Package/hostapd-basic-openssl/description\n This package contains a basic IEEE 802.1x/WPA Authenticator with WPA-PSK, 802.11r and 802.11w support.\nendef\n\ndefine Package/hostapd-basic-wolfssl\n$(call Package/hostapd/Default,$(1))\n  TITLE+= (WPA-PSK, 11r and 11w)\n  VARIANT:=basic-wolfssl\n  DEPENDS+=+libwolfssl\nendef\n\ndefine Package/hostapd-basic-wolfssl/description\n This package contains a basic IEEE 802.1x/WPA Authenticator with WPA-PSK, 802.11r and 802.11w support.\nendef\n\ndefine Package/hostapd-mini\n$(call Package/hostapd/Default,$(1))\n  TITLE+= (WPA-PSK only)\n  VARIANT:=mini\nendef\n\ndefine Package/hostapd-mini/description\n This package contains a minimal IEEE 802.1x/WPA Authenticator (WPA-PSK only).\nendef\n\n\ndefine Package/wpad/Default\n  SECTION:=net\n  CATEGORY:=Network\n  SUBMENU:=WirelessAPD\n  TITLE:=IEEE 802.1x Auth/Supplicant\n  DEPENDS:=$(DRV_DEPENDS) +hostapd-common +libubus\n  EXTRA_DEPENDS:=hostapd-common (=$(PKG_VERSION)-$(PKG_RELEASE))\n  USERID:=network=101:network=101\n  URL:=http://hostap.epitest.fi/\n  PROVIDES:=hostapd wpa-supplicant\n  CONFLICTS:=$(HOSTAPD_PROVIDERS) $(SUPPLICANT_PROVIDERS)\n  HOSTAPD_PROVIDERS+=$(1)\n  SUPPLICANT_PROVIDERS+=$(1)\nendef\n\ndefine Package/wpad\n$(call Package/wpad/Default,$(1))\n  TITLE+= (built-in full)\n  VARIANT:=wpad-full-internal\nendef\n\ndefine Package/wpad/description\n This package contains a full featured IEEE 802.1x/WPA/EAP/RADIUS\n Authenticator and Supplicant\nendef\n\ndefine Package/wpad-openssl\n$(call Package/wpad/Default,$(1))\n  TITLE+= (OpenSSL full)\n  VARIANT:=wpad-full-openssl\n  DEPENDS+=+libopenssl\nendef\n\nPackage/wpad-openssl/description = $(Package/wpad/description)\n\ndefine Package/wpad-wolfssl\n$(call Package/wpad/Default,$(1))\n  TITLE+= (wolfSSL full)\n  VARIANT:=wpad-full-wolfssl\n  DEPENDS+=+libwolfssl\nendef\n\nPackage/wpad-wolfssl/description = $(Package/wpad/description)\n\ndefine Package/wpad-basic\n$(call Package/wpad/Default,$(1))\n  TITLE+= (WPA-PSK, 11r, 11w)\n  VARIANT:=wpad-basic\nendef\n\ndefine Package/wpad-basic/description\n This package contains a basic IEEE 802.1x/WPA Authenticator and Supplicant with WPA-PSK, 802.11r and 802.11w support.\nendef\n\ndefine Package/wpad-basic-openssl\n$(call Package/wpad/Default,$(1))\n  TITLE+= (OpenSSL, 11r, 11w)\n  VARIANT:=wpad-basic-openssl\n  DEPENDS+=+libopenssl\nendef\n\ndefine Package/wpad-basic-openssl/description\n This package contains a basic IEEE 802.1x/WPA Authenticator and Supplicant with WPA-PSK, SAE (WPA3-Personal), 802.11r and 802.11w support.\nendef\n\ndefine Package/wpad-basic-wolfssl\n$(call Package/wpad/Default,$(1))\n  TITLE+= (wolfSSL, 11r, 11w)\n  VARIANT:=wpad-basic-wolfssl\n  DEPENDS+=+libwolfssl\nendef\n\ndefine Package/wpad-basic-wolfssl/description\n This package contains a basic IEEE 802.1x/WPA Authenticator and Supplicant with WPA-PSK, SAE (WPA3-Personal), 802.11r and 802.11w support.\nendef\n\ndefine Package/wpad-mini\n$(call Package/wpad/Default,$(1))\n  TITLE+= (WPA-PSK only)\n  VARIANT:=wpad-mini\nendef\n\ndefine Package/wpad-mini/description\n This package contains a minimal IEEE 802.1x/WPA Authenticator and Supplicant (WPA-PSK only).\nendef\n\ndefine Package/wpad-mesh\n$(call Package/wpad/Default,$(1))\n  DEPENDS+=@PACKAGE_kmod-cfg80211 @(!TARGET_uml||BROKEN)\n  PROVIDES+=wpa-supplicant-mesh wpad-mesh\nendef\n\ndefine Package/wpad-mesh/description\n This package contains a minimal IEEE 802.1x/WPA Authenticator and Supplicant (with 802.11s mesh and SAE support).\nendef\n\ndefine Package/wpad-mesh-openssl\n$(call Package/wpad-mesh,$(1))\n  TITLE+= (OpenSSL, 11s, SAE)\n  DEPENDS+=+libopenssl\n  VARIANT:=wpad-mesh-openssl\nendef\n\nPackage/wpad-mesh-openssl/description = $(Package/wpad-mesh/description)\n\ndefine Package/wpad-mesh-wolfssl\n$(call Package/wpad-mesh,$(1))\n  TITLE+= (wolfSSL, 11s, SAE)\n  DEPENDS+=+libwolfssl\n  VARIANT:=wpad-mesh-wolfssl\nendef\n\nPackage/wpad-mesh-wolfssl/description = $(Package/wpad-mesh/description)\n\n\ndefine Package/wpa-supplicant/Default\n  SECTION:=net\n  CATEGORY:=Network\n  SUBMENU:=WirelessAPD\n  TITLE:=WPA Supplicant\n  URL:=http://hostap.epitest.fi/wpa_supplicant/\n  DEPENDS:=$(DRV_DEPENDS) +hostapd-common +libubus\n  EXTRA_DEPENDS:=hostapd-common (=$(PKG_VERSION)-$(PKG_RELEASE))\n  USERID:=network=101:network=101\n  PROVIDES:=wpa-supplicant\n  CONFLICTS:=$(SUPPLICANT_PROVIDERS)\n  SUPPLICANT_PROVIDERS+=$(1)\nendef\n\ndefine Package/wpa-supplicant\n$(call Package/wpa-supplicant/Default,$(1))\n  TITLE+= (built-in full)\n  VARIANT:=supplicant-full-internal\nendef\n\ndefine Package/wpa-supplicant-openssl\n$(call Package/wpa-supplicant/Default,$(1))\n  TITLE+= (OpenSSL full)\n  VARIANT:=supplicant-full-openssl\n  DEPENDS+=+libopenssl\nendef\n\ndefine Package/wpa-supplicant-wolfssl\n$(call Package/wpa-supplicant/Default,$(1))\n  TITLE+= (wolfSSL full)\n  VARIANT:=supplicant-full-wolfssl\n  DEPENDS+=+libwolfssl\nendef\n\ndefine Package/wpa-supplicant/config\n\tsource \"$(SOURCE)/Config.in\"\nendef\n\ndefine Package/wpa-supplicant-p2p\n$(call Package/wpa-supplicant/Default,$(1))\n  TITLE+= (Wi-Fi P2P support)\n  DEPENDS+=@PACKAGE_kmod-cfg80211\n  VARIANT:=supplicant-p2p-internal\nendef\n\ndefine Package/wpa-supplicant-mesh/Default\n$(call Package/wpa-supplicant/Default,$(1))\n  DEPENDS+=@PACKAGE_kmod-cfg80211 @(!TARGET_uml||BROKEN)\n  PROVIDES+=wpa-supplicant-mesh\nendef\n\ndefine Package/wpa-supplicant-mesh-openssl\n$(call Package/wpa-supplicant-mesh/Default,$(1))\n  TITLE+= (OpenSSL, 11s, SAE)\n  VARIANT:=supplicant-mesh-openssl\n  DEPENDS+=+libopenssl\nendef\n\ndefine Package/wpa-supplicant-mesh-wolfssl\n$(call Package/wpa-supplicant-mesh/Default,$(1))\n  TITLE+= (wolfSSL, 11s, SAE)\n  VARIANT:=supplicant-mesh-wolfssl\n  DEPENDS+=+libwolfssl\nendef\n\ndefine Package/wpa-supplicant-basic\n$(call Package/wpa-supplicant/Default,$(1))\n  TITLE+= (11r, 11w)\n  VARIANT:=supplicant-basic\nendef\n\ndefine Package/wpa-supplicant-mini\n$(call Package/wpa-supplicant/Default,$(1))\n  TITLE+= (minimal)\n  VARIANT:=supplicant-mini\nendef\n\n\ndefine Package/hostapd-common\n  TITLE:=hostapd/wpa_supplicant common support files\n  SECTION:=net\n  CATEGORY:=Network\n  SUBMENU:=WirelessAPD\nendef\n\ndefine Package/hostapd-utils\n  SECTION:=net\n  CATEGORY:=Network\n  SUBMENU:=WirelessAPD\n  TITLE:=IEEE 802.1x Authenticator (utils)\n  URL:=http://hostap.epitest.fi/\n  DEPENDS:=@$(subst $(space),||,$(foreach pkg,$(HOSTAPD_PROVIDERS),PACKAGE_$(pkg)))\n  VARIANT:=*\nendef\n\ndefine Package/hostapd-utils/description\n This package contains a command line utility to control the\n IEEE 802.1x/WPA/EAP/RADIUS Authenticator.\nendef\n\ndefine Package/wpa-cli\n  SECTION:=net\n  CATEGORY:=Network\n  SUBMENU:=WirelessAPD\n  DEPENDS:=@$(subst $(space),||,$(foreach pkg,$(SUPPLICANT_PROVIDERS),PACKAGE_$(pkg)))\n  TITLE:=WPA Supplicant command line control utility\n  VARIANT:=*\nendef\n\ndefine Package/eapol-test/Default\n  TITLE:=802.1x auth test utility\n  SECTION:=net\n  SUBMENU:=WirelessAPD\n  CATEGORY:=Network\n  DEPENDS:=$(DRV_DEPENDS) +libubus\nendef\n\ndefine Package/eapol-test\n  $(call Package/eapol-test/Default,$(1))\n  TITLE+= (built-in full)\n  VARIANT:=supplicant-full-internal\nendef\n\ndefine Package/eapol-test-openssl\n  $(call Package/eapol-test/Default,$(1))\n  TITLE+= (OpenSSL full)\n  VARIANT:=supplicant-full-openssl\n  CONFLICTS:=$(filter-out eapol-test-openssl ,$(EAPOL_TEST_PROVIDERS))\n  DEPENDS+=+libopenssl\n  PROVIDES:=eapol-test\nendef\n\ndefine Package/eapol-test-wolfssl\n  $(call Package/eapol-test/Default,$(1))\n  TITLE+= (wolfSSL full)\n  VARIANT:=supplicant-full-wolfssl\n  CONFLICTS:=$(filter-out eapol-test-openssl ,$(filter-out eapol-test-wolfssl ,$(EAPOL_TEST_PROVIDERS)))\n  DEPENDS+=+libwolfssl\n  PROVIDES:=eapol-test\nendef\n\n\nifneq ($(wildcard $(PKG_BUILD_DIR)/.config_*),$(subst .configured_,.config_,$(STAMP_CONFIGURED)))\n  define Build/Configure/rebuild\n\t$(FIND) $(PKG_BUILD_DIR) -name \\*.o -or -name \\*.a | $(XARGS) rm -f\n\trm -f $(PKG_BUILD_DIR)/hostapd/hostapd\n\trm -f $(PKG_BUILD_DIR)/wpa_supplicant/wpa_supplicant\n\trm -f $(PKG_BUILD_DIR)/.config_*\n\ttouch $(subst .configured_,.config_,$(STAMP_CONFIGURED))\n  endef\nendif\n\ndefine Build/Configure\n\t$(Build/Configure/rebuild)\n\t$(if $(wildcard ./files/hostapd-$(CONFIG_VARIANT).config), \\\n\t\t$(CP) ./files/hostapd-$(CONFIG_VARIANT).config $(PKG_BUILD_DIR)/hostapd/.config \\\n\t)\n\t$(if $(wildcard ./files/wpa_supplicant-$(CONFIG_VARIANT).config), \\\n\t\t$(CP) ./files/wpa_supplicant-$(CONFIG_VARIANT).config $(PKG_BUILD_DIR)/wpa_supplicant/.config\n\t)\nendef\n\nTARGET_CPPFLAGS := \\\n\t-I$(STAGING_DIR)/usr/include/libnl-tiny \\\n\t-I$(PKG_BUILD_DIR)/src/crypto \\\n\t$(TARGET_CPPFLAGS) \\\n\t-DCONFIG_LIBNL20 \\\n\t-D_GNU_SOURCE \\\n\t$(if $(CONFIG_WPA_MSG_MIN_PRIORITY),-DCONFIG_MSG_MIN_PRIORITY=$(CONFIG_WPA_MSG_MIN_PRIORITY))\n\nTARGET_CFLAGS += -ffunction-sections -fdata-sections -flto\nTARGET_LDFLAGS += -Wl,--gc-sections -flto=jobserver -fuse-linker-plugin -lubox -lubus\n\nifdef CONFIG_PACKAGE_kmod-cfg80211\n  TARGET_LDFLAGS += -lm -lnl-tiny\nendif\n\nifdef CONFIG_WPA_ENABLE_WEP\n    DRIVER_MAKEOPTS += CONFIG_WEP=y\nendif\n\ndefine Build/RunMake\n\tCFLAGS=\"$(TARGET_CPPFLAGS) $(TARGET_CFLAGS)\" \\\n\t$(MAKE) $(PKG_JOBS) -C $(PKG_BUILD_DIR)/$(1) \\\n\t\t$(TARGET_CONFIGURE_OPTS) \\\n\t\t$(DRIVER_MAKEOPTS) \\\n\t\tLIBS=\"$(TARGET_LDFLAGS)\" \\\n\t\tLIBS_c=\"$(TARGET_LDFLAGS_C)\" \\\n\t\tAR=\"$(TARGET_CROSS)gcc-ar\" \\\n\t\tBCHECK= \\\n\t\t$(if $(findstring s,$(OPENWRT_VERBOSE)),V=1) \\\n\t\t$(2)\nendef\n\ndefine Build/Compile/wpad\n\techo ` \\\n\t\t$(call Build/RunMake,hostapd,-s MULTICALL=1 dump_cflags); \\\n\t\t$(call Build/RunMake,wpa_supplicant,-s MULTICALL=1 dump_cflags) | \\\n\t\tsed -e 's,-n ,,g' -e 's^$(TARGET_CFLAGS)^^' \\\n\t` > $(PKG_BUILD_DIR)/.cflags\n\tsed -i 's/\"/\\\\\"/g' $(PKG_BUILD_DIR)/.cflags\n\t+$(call Build/RunMake,hostapd, \\\n\t\tCFLAGS=\"$$$$(cat $(PKG_BUILD_DIR)/.cflags)\" \\\n\t\tMULTICALL=1 \\\n\t\thostapd_cli hostapd_multi.a \\\n\t)\n\t+$(call Build/RunMake,wpa_supplicant, \\\n\t\tCFLAGS=\"$$$$(cat $(PKG_BUILD_DIR)/.cflags)\" \\\n\t\tMULTICALL=1 \\\n\t\twpa_cli wpa_supplicant_multi.a \\\n\t)\n\t+export MAKEFLAGS=\"$(MAKE_JOBSERVER)\"; $(TARGET_CC) -o $(PKG_BUILD_DIR)/wpad \\\n\t\t$(TARGET_CFLAGS) \\\n\t\t./files/multicall.c \\\n\t\t$(PKG_BUILD_DIR)/hostapd/hostapd_multi.a \\\n\t\t$(PKG_BUILD_DIR)/wpa_supplicant/wpa_supplicant_multi.a \\\n\t\t$(TARGET_LDFLAGS)\nendef\n\ndefine Build/Compile/hostapd\n\t+$(call Build/RunMake,hostapd, \\\n\t\thostapd hostapd_cli \\\n\t)\nendef\n\ndefine Build/Compile/supplicant\n\t+$(call Build/RunMake,wpa_supplicant, \\\n\t\twpa_cli wpa_supplicant \\\n\t)\nendef\n\ndefine Build/Compile/supplicant-full-internal\n\t+$(call Build/RunMake,wpa_supplicant, \\\n\t\teapol_test \\\n\t)\nendef\n\ndefine Build/Compile/supplicant-full-openssl\n\t+$(call Build/RunMake,wpa_supplicant, \\\n\t\teapol_test \\\n\t)\nendef\n\ndefine Build/Compile/supplicant-full-wolfssl\n\t+$(call Build/RunMake,wpa_supplicant, \\\n\t\teapol_test \\\n\t)\nendef\n\ndefine Build/Compile\n\t$(Build/Compile/$(LOCAL_TYPE))\n\t$(Build/Compile/$(BUILD_VARIANT))\nendef\n\ndefine Install/hostapd\n\t$(INSTALL_DIR) $(1)/usr/sbin\nendef\n\ndefine Install/supplicant\n\t$(INSTALL_DIR) $(1)/usr/sbin\nendef\n\ndefine Package/hostapd-common/install\n\t$(INSTALL_DIR) $(1)/etc/capabilities $(1)/etc/rc.button $(1)/etc/hotplug.d/ieee80211 $(1)/etc/init.d $(1)/lib/netifd  $(1)/usr/share/acl.d\n\t$(INSTALL_BIN) ./files/dhcp-get-server.sh $(1)/lib/netifd/dhcp-get-server.sh\n\t$(INSTALL_DATA) ./files/hostapd.sh $(1)/lib/netifd/hostapd.sh\n\t$(INSTALL_BIN) ./files/wpad.init $(1)/etc/init.d/wpad\n\t$(INSTALL_BIN) ./files/wps-hotplug.sh $(1)/etc/rc.button/wps\n\t$(INSTALL_DATA) ./files/wpad_acl.json $(1)/usr/share/acl.d\n\t$(INSTALL_DATA) ./files/wpad.json $(1)/etc/capabilities\nendef\n\ndefine Package/hostapd/install\n\t$(call Install/hostapd,$(1))\n\t$(INSTALL_BIN) $(PKG_BUILD_DIR)/hostapd/hostapd $(1)/usr/sbin/\nendef\nPackage/hostapd-basic/install = $(Package/hostapd/install)\nPackage/hostapd-basic-openssl/install = $(Package/hostapd/install)\nPackage/hostapd-basic-wolfssl/install = $(Package/hostapd/install)\nPackage/hostapd-mini/install = $(Package/hostapd/install)\nPackage/hostapd-openssl/install = $(Package/hostapd/install)\nPackage/hostapd-wolfssl/install = $(Package/hostapd/install)\n\nifneq ($(LOCAL_TYPE),supplicant)\n  define Package/hostapd-utils/install\n\t$(INSTALL_DIR) $(1)/usr/sbin\n\t$(INSTALL_BIN) $(PKG_BUILD_DIR)/hostapd/hostapd_cli $(1)/usr/sbin/\n  endef\nendif\n\ndefine Package/wpad/install\n\t$(call Install/hostapd,$(1))\n\t$(call Install/supplicant,$(1))\n\t$(INSTALL_BIN) $(PKG_BUILD_DIR)/wpad $(1)/usr/sbin/\n\t$(LN) wpad $(1)/usr/sbin/hostapd\n\t$(LN) wpad $(1)/usr/sbin/wpa_supplicant\nendef\nPackage/wpad-basic/install = $(Package/wpad/install)\nPackage/wpad-basic-openssl/install = $(Package/wpad/install)\nPackage/wpad-basic-wolfssl/install = $(Package/wpad/install)\nPackage/wpad-mini/install = $(Package/wpad/install)\nPackage/wpad-openssl/install = $(Package/wpad/install)\nPackage/wpad-wolfssl/install = $(Package/wpad/install)\nPackage/wpad-mesh-openssl/install = $(Package/wpad/install)\nPackage/wpad-mesh-wolfssl/install = $(Package/wpad/install)\n\ndefine Package/wpa-supplicant/install\n\t$(call Install/supplicant,$(1))\n\t$(INSTALL_BIN) $(PKG_BUILD_DIR)/wpa_supplicant/wpa_supplicant $(1)/usr/sbin/\nendef\nPackage/wpa-supplicant-basic/install = $(Package/wpa-supplicant/install)\nPackage/wpa-supplicant-mini/install = $(Package/wpa-supplicant/install)\nPackage/wpa-supplicant-p2p/install = $(Package/wpa-supplicant/install)\nPackage/wpa-supplicant-openssl/install = $(Package/wpa-supplicant/install)\nPackage/wpa-supplicant-wolfssl/install = $(Package/wpa-supplicant/install)\nPackage/wpa-supplicant-mesh-openssl/install = $(Package/wpa-supplicant/install)\nPackage/wpa-supplicant-mesh-wolfssl/install = $(Package/wpa-supplicant/install)\n\nifneq ($(LOCAL_TYPE),hostapd)\n  define Package/wpa-cli/install\n\t$(INSTALL_DIR) $(1)/usr/sbin\n\t$(CP) $(PKG_BUILD_DIR)/wpa_supplicant/wpa_cli $(1)/usr/sbin/\n  endef\nendif\n\nifeq ($(BUILD_VARIANT),supplicant-full-internal)\n  define Package/eapol-test/install\n\t$(INSTALL_DIR) $(1)/usr/sbin\n\t$(CP) $(PKG_BUILD_DIR)/wpa_supplicant/eapol_test $(1)/usr/sbin/\n  endef\nendif\n\nifeq ($(BUILD_VARIANT),supplicant-full-openssl)\n  define Package/eapol-test-openssl/install\n\t$(INSTALL_DIR) $(1)/usr/sbin\n\t$(CP) $(PKG_BUILD_DIR)/wpa_supplicant/eapol_test $(1)/usr/sbin/\n  endef\nendif\n\nifeq ($(BUILD_VARIANT),supplicant-full-wolfssl)\n  define Package/eapol-test-wolfssl/install\n\t$(INSTALL_DIR) $(1)/usr/sbin\n\t$(CP) $(PKG_BUILD_DIR)/wpa_supplicant/eapol_test $(1)/usr/sbin/\n  endef\nendif\n\n# Build hostapd-common before its dependents, to avoid\n# spurious rebuilds when building multiple variants.\n$(eval $(call BuildPackage,hostapd-common))\n$(eval $(call BuildPackage,hostapd))\n$(eval $(call BuildPackage,hostapd-basic))\n$(eval $(call BuildPackage,hostapd-basic-openssl))\n$(eval $(call BuildPackage,hostapd-basic-wolfssl))\n$(eval $(call BuildPackage,hostapd-mini))\n$(eval $(call BuildPackage,hostapd-openssl))\n$(eval $(call BuildPackage,hostapd-wolfssl))\n$(eval $(call BuildPackage,wpad))\n$(eval $(call BuildPackage,wpad-mesh-openssl))\n$(eval $(call BuildPackage,wpad-mesh-wolfssl))\n$(eval $(call BuildPackage,wpad-basic))\n$(eval $(call BuildPackage,wpad-basic-openssl))\n$(eval $(call BuildPackage,wpad-basic-wolfssl))\n$(eval $(call BuildPackage,wpad-mini))\n$(eval $(call BuildPackage,wpad-openssl))\n$(eval $(call BuildPackage,wpad-wolfssl))\n$(eval $(call BuildPackage,wpa-supplicant))\n$(eval $(call BuildPackage,wpa-supplicant-mesh-openssl))\n$(eval $(call BuildPackage,wpa-supplicant-mesh-wolfssl))\n$(eval $(call BuildPackage,wpa-supplicant-basic))\n$(eval $(call BuildPackage,wpa-supplicant-mini))\n$(eval $(call BuildPackage,wpa-supplicant-p2p))\n$(eval $(call BuildPackage,wpa-supplicant-openssl))\n$(eval $(call BuildPackage,wpa-supplicant-wolfssl))\n$(eval $(call BuildPackage,wpa-cli))\n$(eval $(call BuildPackage,hostapd-utils))\n$(eval $(call BuildPackage,eapol-test))\n$(eval $(call BuildPackage,eapol-test-openssl))\n$(eval $(call BuildPackage,eapol-test-wolfssl))\n"
  },
  {
    "path": "package/network/services/hostapd/files/dhcp-get-server.sh",
    "content": "#!/bin/sh\n[ \"$1\" = bound ] && echo \"$serverid\"\n"
  },
  {
    "path": "package/network/services/hostapd/files/hostapd-basic.config",
    "content": "# Example hostapd build time configuration\n#\n# This file lists the configuration options that are used when building the\n# hostapd binary. All lines starting with # are ignored. Configuration option\n# lines must be commented out complete, if they are not to be included, i.e.,\n# just setting VARIABLE=n is not disabling that variable.\n#\n# This file is included in Makefile, so variables like CFLAGS and LIBS can also\n# be modified from here. In most cass, these lines should use += in order not\n# to override previous values of the variables.\n\n# Driver interface for Host AP driver\n#CONFIG_DRIVER_HOSTAP=y\n\n# Driver interface for wired authenticator\nCONFIG_DRIVER_WIRED=y\n\n# Driver interface for drivers using the nl80211 kernel interface\nCONFIG_DRIVER_NL80211=y\n\n# QCA vendor extensions to nl80211\n#CONFIG_DRIVER_NL80211_QCA=y\n\n# driver_nl80211.c requires libnl. If you are compiling it yourself\n# you may need to point hostapd to your version of libnl.\n#\n#CFLAGS += -I$<path to libnl include files>\n#LIBS += -L$<path to libnl library files>\n\n# Use libnl v2.0 (or 3.0) libraries.\n#CONFIG_LIBNL20=y\n\n# Use libnl 3.2 libraries (if this is selected, CONFIG_LIBNL20 is ignored)\n#CONFIG_LIBNL32=y\n\n\n# Driver interface for FreeBSD net80211 layer (e.g., Atheros driver)\n#CONFIG_DRIVER_BSD=y\n#CFLAGS += -I/usr/local/include\n#LIBS += -L/usr/local/lib\n#LIBS_p += -L/usr/local/lib\n#LIBS_c += -L/usr/local/lib\n\n# Driver interface for no driver (e.g., RADIUS server only)\n#CONFIG_DRIVER_NONE=y\n\n# IEEE 802.11F/IAPP\n#CONFIG_IAPP=y\n\n# WPA2/IEEE 802.11i RSN pre-authentication\nCONFIG_RSN_PREAUTH=y\n\n# IEEE 802.11w (management frame protection)\n#CONFIG_IEEE80211W=y\n\n# Support Operating Channel Validation\n#CONFIG_OCV=y\n\n# Integrated EAP server\n#CONFIG_EAP=y\n\n# EAP Re-authentication Protocol (ERP) in integrated EAP server\n#CONFIG_ERP=y\n\n# EAP-MD5 for the integrated EAP server\n#CONFIG_EAP_MD5=y\n\n# EAP-TLS for the integrated EAP server\n#CONFIG_EAP_TLS=y\n\n# EAP-MSCHAPv2 for the integrated EAP server\n#CONFIG_EAP_MSCHAPV2=y\n\n# EAP-PEAP for the integrated EAP server\n#CONFIG_EAP_PEAP=y\n\n# EAP-GTC for the integrated EAP server\n#CONFIG_EAP_GTC=y\n\n# EAP-TTLS for the integrated EAP server\n#CONFIG_EAP_TTLS=y\n\n# EAP-SIM for the integrated EAP server\n#CONFIG_EAP_SIM=y\n\n# EAP-AKA for the integrated EAP server\n#CONFIG_EAP_AKA=y\n\n# EAP-AKA' for the integrated EAP server\n# This requires CONFIG_EAP_AKA to be enabled, too.\n#CONFIG_EAP_AKA_PRIME=y\n\n# EAP-PAX for the integrated EAP server\n#CONFIG_EAP_PAX=y\n\n# EAP-PSK for the integrated EAP server (this is _not_ needed for WPA-PSK)\n#CONFIG_EAP_PSK=y\n\n# EAP-pwd for the integrated EAP server (secure authentication with a password)\n#CONFIG_EAP_PWD=y\n\n# EAP-SAKE for the integrated EAP server\n#CONFIG_EAP_SAKE=y\n\n# EAP-GPSK for the integrated EAP server\n#CONFIG_EAP_GPSK=y\n# Include support for optional SHA256 cipher suite in EAP-GPSK\n#CONFIG_EAP_GPSK_SHA256=y\n\n# EAP-FAST for the integrated EAP server\n#CONFIG_EAP_FAST=y\n\n# EAP-TEAP for the integrated EAP server\n# Note: The current EAP-TEAP implementation is experimental and should not be\n# enabled for production use. The IETF RFC 7170 that defines EAP-TEAP has number\n# of conflicting statements and missing details and the implementation has\n# vendor specific workarounds for those and as such, may not interoperate with\n# any other implementation. This should not be used for anything else than\n# experimentation and interoperability testing until those issues has been\n# resolved.\n#CONFIG_EAP_TEAP=y\n\n# Wi-Fi Protected Setup (WPS)\n#CONFIG_WPS=y\n# Enable UPnP support for external WPS Registrars\n#CONFIG_WPS_UPNP=y\n# Enable WPS support with NFC config method\n#CONFIG_WPS_NFC=y\n\n# EAP-IKEv2\n#CONFIG_EAP_IKEV2=y\n\n# Trusted Network Connect (EAP-TNC)\n#CONFIG_EAP_TNC=y\n\n# EAP-EKE for the integrated EAP server\n#CONFIG_EAP_EKE=y\n\n# PKCS#12 (PFX) support (used to read private key and certificate file from\n# a file that usually has extension .p12 or .pfx)\n#CONFIG_PKCS12=y\n\n# RADIUS authentication server. This provides access to the integrated EAP\n# server from external hosts using RADIUS.\n#CONFIG_RADIUS_SERVER=y\n\n# Build IPv6 support for RADIUS operations\n#CONFIG_IPV6=y\n\n# IEEE Std 802.11r-2008 (Fast BSS Transition)\nCONFIG_IEEE80211R=y\n\n# Use the hostapd's IEEE 802.11 authentication (ACL), but without\n# the IEEE 802.11 Management capability (e.g., FreeBSD/net80211)\n#CONFIG_DRIVER_RADIUS_ACL=y\n\n# IEEE 802.11n (High Throughput) support\nCONFIG_IEEE80211N=y\n\n# Wireless Network Management (IEEE Std 802.11v-2011)\n# Note: This is experimental and not complete implementation.\n#CONFIG_WNM=y\n\n# IEEE 802.11ac (Very High Throughput) support\nCONFIG_IEEE80211AC=y\n\n# IEEE 802.11ax HE support\n# Note: This is experimental and work in progress. The definitions are still\n# subject to change and this should not be expected to interoperate with the\n# final IEEE 802.11ax version.\n#CONFIG_IEEE80211AX=y\n\n# Remove debugging code that is printing out debug messages to stdout.\n# This can be used to reduce the size of the hostapd considerably if debugging\n# code is not needed.\n#CONFIG_NO_STDOUT_DEBUG=y\n\n# Add support for writing debug log to a file: -f /tmp/hostapd.log\n# Disabled by default.\n#CONFIG_DEBUG_FILE=y\n\n# Send debug messages to syslog instead of stdout\nCONFIG_DEBUG_SYSLOG=y\n\n# Add support for sending all debug messages (regardless of debug verbosity)\n# to the Linux kernel tracing facility. This helps debug the entire stack by\n# making it easy to record everything happening from the driver up into the\n# same file, e.g., using trace-cmd.\n#CONFIG_DEBUG_LINUX_TRACING=y\n\n# Remove support for RADIUS accounting\nCONFIG_NO_ACCOUNTING=y\n\n# Remove support for RADIUS\nCONFIG_NO_RADIUS=y\n\n# Remove support for VLANs\n#CONFIG_NO_VLAN=y\n\n# Enable support for fully dynamic VLANs. This enables hostapd to\n# automatically create bridge and VLAN interfaces if necessary.\n#CONFIG_FULL_DYNAMIC_VLAN=y\n\n# Use netlink-based kernel API for VLAN operations instead of ioctl()\n# Note: This requires libnl 3.1 or newer.\n#CONFIG_VLAN_NETLINK=y\n\n# Remove support for dumping internal state through control interface commands\n# This can be used to reduce binary size at the cost of disabling a debugging\n# option.\nCONFIG_NO_DUMP_STATE=y\n\n# Enable tracing code for developer debugging\n# This tracks use of memory allocations and other registrations and reports\n# incorrect use with a backtrace of call (or allocation) location.\n#CONFIG_WPA_TRACE=y\n# For BSD, comment out these.\n#LIBS += -lexecinfo\n#LIBS_p += -lexecinfo\n#LIBS_c += -lexecinfo\n\n# Use libbfd to get more details for developer debugging\n# This enables use of libbfd to get more detailed symbols for the backtraces\n# generated by CONFIG_WPA_TRACE=y.\n#CONFIG_WPA_TRACE_BFD=y\n# For BSD, comment out these.\n#LIBS += -lbfd -liberty -lz\n#LIBS_p += -lbfd -liberty -lz\n#LIBS_c += -lbfd -liberty -lz\n\n# hostapd depends on strong random number generation being available from the\n# operating system. os_get_random() function is used to fetch random data when\n# needed, e.g., for key generation. On Linux and BSD systems, this works by\n# reading /dev/urandom. It should be noted that the OS entropy pool needs to be\n# properly initialized before hostapd is started. This is important especially\n# on embedded devices that do not have a hardware random number generator and\n# may by default start up with minimal entropy available for random number\n# generation.\n#\n# As a safety net, hostapd is by default trying to internally collect\n# additional entropy for generating random data to mix in with the data\n# fetched from the OS. This by itself is not considered to be very strong, but\n# it may help in cases where the system pool is not initialized properly.\n# However, it is very strongly recommended that the system pool is initialized\n# with enough entropy either by using hardware assisted random number\n# generator or by storing state over device reboots.\n#\n# hostapd can be configured to maintain its own entropy store over restarts to\n# enhance random number generation. This is not perfect, but it is much more\n# secure than using the same sequence of random numbers after every reboot.\n# This can be enabled with -e<entropy file> command line option. The specified\n# file needs to be readable and writable by hostapd.\n#\n# If the os_get_random() is known to provide strong random data (e.g., on\n# Linux/BSD, the board in question is known to have reliable source of random\n# data from /dev/urandom), the internal hostapd random pool can be disabled.\n# This will save some in binary size and CPU use. However, this should only be\n# considered for builds that are known to be used on devices that meet the\n# requirements described above.\nCONFIG_NO_RANDOM_POOL=y\n\n# Should we attempt to use the getrandom(2) call that provides more reliable\n# yet secure randomness source than /dev/random on Linux 3.17 and newer.\n# Requires glibc 2.25 to build, falls back to /dev/random if unavailable.\nCONFIG_GETRANDOM=y\n\n# Should we use poll instead of select? Select is used by default.\n#CONFIG_ELOOP_POLL=y\n\n# Should we use epoll instead of select? Select is used by default.\nCONFIG_ELOOP_EPOLL=y\n\n# Should we use kqueue instead of select? Select is used by default.\n#CONFIG_ELOOP_KQUEUE=y\n\n# Select TLS implementation\n# openssl = OpenSSL (default)\n# gnutls = GnuTLS\n# internal = Internal TLSv1 implementation (experimental)\n# linux = Linux kernel AF_ALG and internal TLSv1 implementation (experimental)\n# none = Empty template\nCONFIG_TLS=internal\n\n# TLS-based EAP methods require at least TLS v1.0. Newer version of TLS (v1.1)\n# can be enabled to get a stronger construction of messages when block ciphers\n# are used.\n#CONFIG_TLSV11=y\n\n# TLS-based EAP methods require at least TLS v1.0. Newer version of TLS (v1.2)\n# can be enabled to enable use of stronger crypto algorithms.\n#CONFIG_TLSV12=y\n\n# Select which ciphers to use by default with OpenSSL if the user does not\n# specify them.\n#CONFIG_TLS_DEFAULT_CIPHERS=\"DEFAULT:!EXP:!LOW\"\n\n# If CONFIG_TLS=internal is used, additional library and include paths are\n# needed for LibTomMath. Alternatively, an integrated, minimal version of\n# LibTomMath can be used. See beginning of libtommath.c for details on benefits\n# and drawbacks of this option.\n#CONFIG_INTERNAL_LIBTOMMATH=y\n#ifndef CONFIG_INTERNAL_LIBTOMMATH\n#LTM_PATH=/usr/src/libtommath-0.39\n#CFLAGS += -I$(LTM_PATH)\n#LIBS += -L$(LTM_PATH)\n#LIBS_p += -L$(LTM_PATH)\n#endif\n# At the cost of about 4 kB of additional binary size, the internal LibTomMath\n# can be configured to include faster routines for exptmod, sqr, and div to\n# speed up DH and RSA calculation considerably\n#CONFIG_INTERNAL_LIBTOMMATH_FAST=y\n\n# Interworking (IEEE 802.11u)\n# This can be used to enable functionality to improve interworking with\n# external networks.\n#CONFIG_INTERWORKING=y\n\n# Hotspot 2.0\n#CONFIG_HS20=y\n\n# Enable SQLite database support in hlr_auc_gw, EAP-SIM DB, and eap_user_file\n#CONFIG_SQLITE=y\n\n# Enable Fast Session Transfer (FST)\n#CONFIG_FST=y\n\n# Enable CLI commands for FST testing\n#CONFIG_FST_TEST=y\n\n# Testing options\n# This can be used to enable some testing options (see also the example\n# configuration file) that are really useful only for testing clients that\n# connect to this hostapd. These options allow, for example, to drop a\n# certain percentage of probe requests or auth/(re)assoc frames.\n#\n#CONFIG_TESTING_OPTIONS=y\n\n# Automatic Channel Selection\n# This will allow hostapd to pick the channel automatically when channel is set\n# to \"acs_survey\" or \"0\". Eventually, other ACS algorithms can be added in\n# similar way.\n#\n# Automatic selection is currently only done through initialization, later on\n# we hope to do background checks to keep us moving to more ideal channels as\n# time goes by. ACS is currently only supported through the nl80211 driver and\n# your driver must have survey dump capability that is filled by the driver\n# during scanning.\n#\n# You can customize the ACS survey algorithm with the hostapd.conf variable\n# acs_num_scans.\n#\n# Supported ACS drivers:\n# * ath9k\n# * ath5k\n# * ath10k\n#\n# For more details refer to:\n# http://wireless.kernel.org/en/users/Documentation/acs\n#\n#CONFIG_ACS=y\n\n# Multiband Operation support\n# These extentions facilitate efficient use of multiple frequency bands\n# available to the AP and the devices that may associate with it.\n#CONFIG_MBO=y\n\n# Client Taxonomy\n# Has the AP retain the Probe Request and (Re)Association Request frames from\n# a client, from which a signature can be produced which can identify the model\n# of client device like \"Nexus 6P\" or \"iPhone 5s\".\n#CONFIG_TAXONOMY=y\n\n# Fast Initial Link Setup (FILS) (IEEE 802.11ai)\n#CONFIG_FILS=y\n# FILS shared key authentication with PFS\n#CONFIG_FILS_SK_PFS=y\n\n# Include internal line edit mode in hostapd_cli. This can be used to provide\n# limited command line editing and history support.\n#CONFIG_WPA_CLI_EDIT=y\n\n# Opportunistic Wireless Encryption (OWE)\n# Experimental implementation of draft-harkins-owe-07.txt\n#CONFIG_OWE=y\n\n# Airtime policy support\nCONFIG_AIRTIME_POLICY=y\n\n# Proxy ARP support\n#CONFIG_PROXYARP=y\n\n# Override default value for the wpa_disable_eapol_key_retries configuration\n# parameter. See that parameter in hostapd.conf for more details.\n#CFLAGS += -DDEFAULT_WPA_DISABLE_EAPOL_KEY_RETRIES=1\n\n# uBus IPC/RPC System\n# Services can connect to the bus and provide methods\n# that can be called by other services or clients.\nCONFIG_UBUS=y\n\n# OpenWrt patch 380-disable-ctrl-iface-mib.patch\n# leads to the MIB only being compiled in if\n# CONFIG_CTRL_IFACE_MIB is enabled.\n#CONFIG_CTRL_IFACE_MIB=y\n"
  },
  {
    "path": "package/network/services/hostapd/files/hostapd-full.config",
    "content": "# Example hostapd build time configuration\n#\n# This file lists the configuration options that are used when building the\n# hostapd binary. All lines starting with # are ignored. Configuration option\n# lines must be commented out complete, if they are not to be included, i.e.,\n# just setting VARIABLE=n is not disabling that variable.\n#\n# This file is included in Makefile, so variables like CFLAGS and LIBS can also\n# be modified from here. In most cass, these lines should use += in order not\n# to override previous values of the variables.\n\n# Driver interface for Host AP driver\n#CONFIG_DRIVER_HOSTAP=y\n\n# Driver interface for wired authenticator\nCONFIG_DRIVER_WIRED=y\n\n# Driver interface for drivers using the nl80211 kernel interface\nCONFIG_DRIVER_NL80211=y\n\n# QCA vendor extensions to nl80211\n#CONFIG_DRIVER_NL80211_QCA=y\n\n# driver_nl80211.c requires libnl. If you are compiling it yourself\n# you may need to point hostapd to your version of libnl.\n#\n#CFLAGS += -I$<path to libnl include files>\n#LIBS += -L$<path to libnl library files>\n\n# Use libnl v2.0 (or 3.0) libraries.\n#CONFIG_LIBNL20=y\n\n# Use libnl 3.2 libraries (if this is selected, CONFIG_LIBNL20 is ignored)\n#CONFIG_LIBNL32=y\n\n\n# Driver interface for FreeBSD net80211 layer (e.g., Atheros driver)\n#CONFIG_DRIVER_BSD=y\n#CFLAGS += -I/usr/local/include\n#LIBS += -L/usr/local/lib\n#LIBS_p += -L/usr/local/lib\n#LIBS_c += -L/usr/local/lib\n\n# Driver interface for no driver (e.g., RADIUS server only)\n#CONFIG_DRIVER_NONE=y\n\n# IEEE 802.11F/IAPP\nCONFIG_IAPP=y\n\n# WPA2/IEEE 802.11i RSN pre-authentication\nCONFIG_RSN_PREAUTH=y\n\n# IEEE 802.11w (management frame protection)\n#CONFIG_IEEE80211W=y\n\n# Support Operating Channel Validation\n#CONFIG_OCV=y\n\n# Integrated EAP server\nCONFIG_EAP=y\n\n# EAP Re-authentication Protocol (ERP) in integrated EAP server\nCONFIG_ERP=y\n\n# EAP-MD5 for the integrated EAP server\nCONFIG_EAP_MD5=y\n\n# EAP-TLS for the integrated EAP server\nCONFIG_EAP_TLS=y\n\n# EAP-MSCHAPv2 for the integrated EAP server\nCONFIG_EAP_MSCHAPV2=y\n\n# EAP-PEAP for the integrated EAP server\nCONFIG_EAP_PEAP=y\n\n# EAP-GTC for the integrated EAP server\nCONFIG_EAP_GTC=y\n\n# EAP-TTLS for the integrated EAP server\nCONFIG_EAP_TTLS=y\n\n# EAP-SIM for the integrated EAP server\n#CONFIG_EAP_SIM=y\n\n# EAP-AKA for the integrated EAP server\n#CONFIG_EAP_AKA=y\n\n# EAP-AKA' for the integrated EAP server\n# This requires CONFIG_EAP_AKA to be enabled, too.\n#CONFIG_EAP_AKA_PRIME=y\n\n# EAP-PAX for the integrated EAP server\n#CONFIG_EAP_PAX=y\n\n# EAP-PSK for the integrated EAP server (this is _not_ needed for WPA-PSK)\n#CONFIG_EAP_PSK=y\n\n# EAP-pwd for the integrated EAP server (secure authentication with a password)\n#CONFIG_EAP_PWD=y\n\n# EAP-SAKE for the integrated EAP server\n#CONFIG_EAP_SAKE=y\n\n# EAP-GPSK for the integrated EAP server\n#CONFIG_EAP_GPSK=y\n# Include support for optional SHA256 cipher suite in EAP-GPSK\n#CONFIG_EAP_GPSK_SHA256=y\n\n# EAP-FAST for the integrated EAP server\nCONFIG_EAP_FAST=y\n\n# EAP-TEAP for the integrated EAP server\n# Note: The current EAP-TEAP implementation is experimental and should not be\n# enabled for production use. The IETF RFC 7170 that defines EAP-TEAP has number\n# of conflicting statements and missing details and the implementation has\n# vendor specific workarounds for those and as such, may not interoperate with\n# any other implementation. This should not be used for anything else than\n# experimentation and interoperability testing until those issues has been\n# resolved.\n#CONFIG_EAP_TEAP=y\n\n# Wi-Fi Protected Setup (WPS)\nCONFIG_WPS=y\n# Enable UPnP support for external WPS Registrars\n#CONFIG_WPS_UPNP=y\n# Enable WPS support with NFC config method\n#CONFIG_WPS_NFC=y\n\n# EAP-IKEv2\n#CONFIG_EAP_IKEV2=y\n\n# Trusted Network Connect (EAP-TNC)\n#CONFIG_EAP_TNC=y\n\n# EAP-EKE for the integrated EAP server\n#CONFIG_EAP_EKE=y\n\n# PKCS#12 (PFX) support (used to read private key and certificate file from\n# a file that usually has extension .p12 or .pfx)\nCONFIG_PKCS12=y\n\n# RADIUS authentication server. This provides access to the integrated EAP\n# server from external hosts using RADIUS.\n#CONFIG_RADIUS_SERVER=y\n\n# Build IPv6 support for RADIUS operations\nCONFIG_IPV6=y\n\n# IEEE Std 802.11r-2008 (Fast BSS Transition)\nCONFIG_IEEE80211R=y\n\n# Use the hostapd's IEEE 802.11 authentication (ACL), but without\n# the IEEE 802.11 Management capability (e.g., FreeBSD/net80211)\n#CONFIG_DRIVER_RADIUS_ACL=y\n\n# IEEE 802.11n (High Throughput) support\nCONFIG_IEEE80211N=y\n\n# Wireless Network Management (IEEE Std 802.11v-2011)\n# Note: This is experimental and not complete implementation.\nCONFIG_WNM=y\n\n# IEEE 802.11ac (Very High Throughput) support\nCONFIG_IEEE80211AC=y\n\n# IEEE 802.11ax HE support\n# Note: This is experimental and work in progress. The definitions are still\n# subject to change and this should not be expected to interoperate with the\n# final IEEE 802.11ax version.\n#CONFIG_IEEE80211AX=y\n\n# Remove debugging code that is printing out debug messages to stdout.\n# This can be used to reduce the size of the hostapd considerably if debugging\n# code is not needed.\n#CONFIG_NO_STDOUT_DEBUG=y\n\n# Add support for writing debug log to a file: -f /tmp/hostapd.log\n# Disabled by default.\n#CONFIG_DEBUG_FILE=y\n\n# Send debug messages to syslog instead of stdout\nCONFIG_DEBUG_SYSLOG=y\n\n# Add support for sending all debug messages (regardless of debug verbosity)\n# to the Linux kernel tracing facility. This helps debug the entire stack by\n# making it easy to record everything happening from the driver up into the\n# same file, e.g., using trace-cmd.\n#CONFIG_DEBUG_LINUX_TRACING=y\n\n# Remove support for RADIUS accounting\n#CONFIG_NO_ACCOUNTING=y\n\n# Remove support for RADIUS\n#CONFIG_NO_RADIUS=y\n\n# Remove support for VLANs\n#CONFIG_NO_VLAN=y\n\n# Enable support for fully dynamic VLANs. This enables hostapd to\n# automatically create bridge and VLAN interfaces if necessary.\nCONFIG_FULL_DYNAMIC_VLAN=y\n\n# Use netlink-based kernel API for VLAN operations instead of ioctl()\n# Note: This requires libnl 3.1 or newer.\n#CONFIG_VLAN_NETLINK=y\n\n# Remove support for dumping internal state through control interface commands\n# This can be used to reduce binary size at the cost of disabling a debugging\n# option.\nCONFIG_NO_DUMP_STATE=y\n\n# Enable tracing code for developer debugging\n# This tracks use of memory allocations and other registrations and reports\n# incorrect use with a backtrace of call (or allocation) location.\n#CONFIG_WPA_TRACE=y\n# For BSD, comment out these.\n#LIBS += -lexecinfo\n#LIBS_p += -lexecinfo\n#LIBS_c += -lexecinfo\n\n# Use libbfd to get more details for developer debugging\n# This enables use of libbfd to get more detailed symbols for the backtraces\n# generated by CONFIG_WPA_TRACE=y.\n#CONFIG_WPA_TRACE_BFD=y\n# For BSD, comment out these.\n#LIBS += -lbfd -liberty -lz\n#LIBS_p += -lbfd -liberty -lz\n#LIBS_c += -lbfd -liberty -lz\n\n# hostapd depends on strong random number generation being available from the\n# operating system. os_get_random() function is used to fetch random data when\n# needed, e.g., for key generation. On Linux and BSD systems, this works by\n# reading /dev/urandom. It should be noted that the OS entropy pool needs to be\n# properly initialized before hostapd is started. This is important especially\n# on embedded devices that do not have a hardware random number generator and\n# may by default start up with minimal entropy available for random number\n# generation.\n#\n# As a safety net, hostapd is by default trying to internally collect\n# additional entropy for generating random data to mix in with the data\n# fetched from the OS. This by itself is not considered to be very strong, but\n# it may help in cases where the system pool is not initialized properly.\n# However, it is very strongly recommended that the system pool is initialized\n# with enough entropy either by using hardware assisted random number\n# generator or by storing state over device reboots.\n#\n# hostapd can be configured to maintain its own entropy store over restarts to\n# enhance random number generation. This is not perfect, but it is much more\n# secure than using the same sequence of random numbers after every reboot.\n# This can be enabled with -e<entropy file> command line option. The specified\n# file needs to be readable and writable by hostapd.\n#\n# If the os_get_random() is known to provide strong random data (e.g., on\n# Linux/BSD, the board in question is known to have reliable source of random\n# data from /dev/urandom), the internal hostapd random pool can be disabled.\n# This will save some in binary size and CPU use. However, this should only be\n# considered for builds that are known to be used on devices that meet the\n# requirements described above.\nCONFIG_NO_RANDOM_POOL=y\n\n# Should we attempt to use the getrandom(2) call that provides more reliable\n# yet secure randomness source than /dev/random on Linux 3.17 and newer.\n# Requires glibc 2.25 to build, falls back to /dev/random if unavailable.\nCONFIG_GETRANDOM=y\n\n# Should we use poll instead of select? Select is used by default.\n#CONFIG_ELOOP_POLL=y\n\n# Should we use epoll instead of select? Select is used by default.\nCONFIG_ELOOP_EPOLL=y\n\n# Should we use kqueue instead of select? Select is used by default.\n#CONFIG_ELOOP_KQUEUE=y\n\n# Select TLS implementation\n# openssl = OpenSSL (default)\n# gnutls = GnuTLS\n# internal = Internal TLSv1 implementation (experimental)\n# linux = Linux kernel AF_ALG and internal TLSv1 implementation (experimental)\n# none = Empty template\nCONFIG_TLS=internal\n\n# TLS-based EAP methods require at least TLS v1.0. Newer version of TLS (v1.1)\n# can be enabled to get a stronger construction of messages when block ciphers\n# are used.\n#CONFIG_TLSV11=y\n\n# TLS-based EAP methods require at least TLS v1.0. Newer version of TLS (v1.2)\n# can be enabled to enable use of stronger crypto algorithms.\n#CONFIG_TLSV12=y\n\n# Select which ciphers to use by default with OpenSSL if the user does not\n# specify them.\n#CONFIG_TLS_DEFAULT_CIPHERS=\"DEFAULT:!EXP:!LOW\"\n\n# If CONFIG_TLS=internal is used, additional library and include paths are\n# needed for LibTomMath. Alternatively, an integrated, minimal version of\n# LibTomMath can be used. See beginning of libtommath.c for details on benefits\n# and drawbacks of this option.\nCONFIG_INTERNAL_LIBTOMMATH=y\n#ifndef CONFIG_INTERNAL_LIBTOMMATH\n#LTM_PATH=/usr/src/libtommath-0.39\n#CFLAGS += -I$(LTM_PATH)\n#LIBS += -L$(LTM_PATH)\n#LIBS_p += -L$(LTM_PATH)\n#endif\n# At the cost of about 4 kB of additional binary size, the internal LibTomMath\n# can be configured to include faster routines for exptmod, sqr, and div to\n# speed up DH and RSA calculation considerably\n#CONFIG_INTERNAL_LIBTOMMATH_FAST=y\n\n# Interworking (IEEE 802.11u)\n# This can be used to enable functionality to improve interworking with\n# external networks.\nCONFIG_INTERWORKING=y\n\n# Hotspot 2.0\n#CONFIG_HS20=y\n\n# Enable SQLite database support in hlr_auc_gw, EAP-SIM DB, and eap_user_file\n#CONFIG_SQLITE=y\n\n# Enable Fast Session Transfer (FST)\n#CONFIG_FST=y\n\n# Enable CLI commands for FST testing\n#CONFIG_FST_TEST=y\n\n# Testing options\n# This can be used to enable some testing options (see also the example\n# configuration file) that are really useful only for testing clients that\n# connect to this hostapd. These options allow, for example, to drop a\n# certain percentage of probe requests or auth/(re)assoc frames.\n#\n#CONFIG_TESTING_OPTIONS=y\n\n# Automatic Channel Selection\n# This will allow hostapd to pick the channel automatically when channel is set\n# to \"acs_survey\" or \"0\". Eventually, other ACS algorithms can be added in\n# similar way.\n#\n# Automatic selection is currently only done through initialization, later on\n# we hope to do background checks to keep us moving to more ideal channels as\n# time goes by. ACS is currently only supported through the nl80211 driver and\n# your driver must have survey dump capability that is filled by the driver\n# during scanning.\n#\n# You can customize the ACS survey algorithm with the hostapd.conf variable\n# acs_num_scans.\n#\n# Supported ACS drivers:\n# * ath9k\n# * ath5k\n# * ath10k\n#\n# For more details refer to:\n# http://wireless.kernel.org/en/users/Documentation/acs\n#\n#CONFIG_ACS=y\n\n# Multiband Operation support\n# These extentions facilitate efficient use of multiple frequency bands\n# available to the AP and the devices that may associate with it.\n#CONFIG_MBO=y\n\n# Client Taxonomy\n# Has the AP retain the Probe Request and (Re)Association Request frames from\n# a client, from which a signature can be produced which can identify the model\n# of client device like \"Nexus 6P\" or \"iPhone 5s\".\nCONFIG_TAXONOMY=y\n\n# Fast Initial Link Setup (FILS) (IEEE 802.11ai)\n#CONFIG_FILS=y\n# FILS shared key authentication with PFS\n#CONFIG_FILS_SK_PFS=y\n\n# Include internal line edit mode in hostapd_cli. This can be used to provide\n# limited command line editing and history support.\n#CONFIG_WPA_CLI_EDIT=y\n\n# Opportunistic Wireless Encryption (OWE)\n# Experimental implementation of draft-harkins-owe-07.txt\n#CONFIG_OWE=y\n\n# Airtime policy support\nCONFIG_AIRTIME_POLICY=y\n\n# Proxy ARP support\nCONFIG_PROXYARP=y\n\n# Override default value for the wpa_disable_eapol_key_retries configuration\n# parameter. See that parameter in hostapd.conf for more details.\n#CFLAGS += -DDEFAULT_WPA_DISABLE_EAPOL_KEY_RETRIES=1\n\n# uBus IPC/RPC System\n# Services can connect to the bus and provide methods\n# that can be called by other services or clients.\nCONFIG_UBUS=y\n\n# OpenWrt patch 380-disable-ctrl-iface-mib.patch\n# leads to the MIB only being compiled in if\n# CONFIG_CTRL_IFACE_MIB is enabled.\nCONFIG_CTRL_IFACE_MIB=y\n"
  },
  {
    "path": "package/network/services/hostapd/files/hostapd-mini.config",
    "content": "# Example hostapd build time configuration\n#\n# This file lists the configuration options that are used when building the\n# hostapd binary. All lines starting with # are ignored. Configuration option\n# lines must be commented out complete, if they are not to be included, i.e.,\n# just setting VARIABLE=n is not disabling that variable.\n#\n# This file is included in Makefile, so variables like CFLAGS and LIBS can also\n# be modified from here. In most cass, these lines should use += in order not\n# to override previous values of the variables.\n\n# Driver interface for Host AP driver\n#CONFIG_DRIVER_HOSTAP=y\n\n# Driver interface for wired authenticator\nCONFIG_DRIVER_WIRED=y\n\n# Driver interface for drivers using the nl80211 kernel interface\nCONFIG_DRIVER_NL80211=y\n\n# QCA vendor extensions to nl80211\n#CONFIG_DRIVER_NL80211_QCA=y\n\n# driver_nl80211.c requires libnl. If you are compiling it yourself\n# you may need to point hostapd to your version of libnl.\n#\n#CFLAGS += -I$<path to libnl include files>\n#LIBS += -L$<path to libnl library files>\n\n# Use libnl v2.0 (or 3.0) libraries.\n#CONFIG_LIBNL20=y\n\n# Use libnl 3.2 libraries (if this is selected, CONFIG_LIBNL20 is ignored)\n#CONFIG_LIBNL32=y\n\n\n# Driver interface for FreeBSD net80211 layer (e.g., Atheros driver)\n#CONFIG_DRIVER_BSD=y\n#CFLAGS += -I/usr/local/include\n#LIBS += -L/usr/local/lib\n#LIBS_p += -L/usr/local/lib\n#LIBS_c += -L/usr/local/lib\n\n# Driver interface for no driver (e.g., RADIUS server only)\n#CONFIG_DRIVER_NONE=y\n\n# IEEE 802.11F/IAPP\n#CONFIG_IAPP=y\n\n# WPA2/IEEE 802.11i RSN pre-authentication\nCONFIG_RSN_PREAUTH=y\n\n# IEEE 802.11w (management frame protection)\n#CONFIG_IEEE80211W=y\n\n# Support Operating Channel Validation\n#CONFIG_OCV=y\n\n# Integrated EAP server\n#CONFIG_EAP=y\n\n# EAP Re-authentication Protocol (ERP) in integrated EAP server\n#CONFIG_ERP=y\n\n# EAP-MD5 for the integrated EAP server\n#CONFIG_EAP_MD5=y\n\n# EAP-TLS for the integrated EAP server\n#CONFIG_EAP_TLS=y\n\n# EAP-MSCHAPv2 for the integrated EAP server\n#CONFIG_EAP_MSCHAPV2=y\n\n# EAP-PEAP for the integrated EAP server\n#CONFIG_EAP_PEAP=y\n\n# EAP-GTC for the integrated EAP server\n#CONFIG_EAP_GTC=y\n\n# EAP-TTLS for the integrated EAP server\n#CONFIG_EAP_TTLS=y\n\n# EAP-SIM for the integrated EAP server\n#CONFIG_EAP_SIM=y\n\n# EAP-AKA for the integrated EAP server\n#CONFIG_EAP_AKA=y\n\n# EAP-AKA' for the integrated EAP server\n# This requires CONFIG_EAP_AKA to be enabled, too.\n#CONFIG_EAP_AKA_PRIME=y\n\n# EAP-PAX for the integrated EAP server\n#CONFIG_EAP_PAX=y\n\n# EAP-PSK for the integrated EAP server (this is _not_ needed for WPA-PSK)\n#CONFIG_EAP_PSK=y\n\n# EAP-pwd for the integrated EAP server (secure authentication with a password)\n#CONFIG_EAP_PWD=y\n\n# EAP-SAKE for the integrated EAP server\n#CONFIG_EAP_SAKE=y\n\n# EAP-GPSK for the integrated EAP server\n#CONFIG_EAP_GPSK=y\n# Include support for optional SHA256 cipher suite in EAP-GPSK\n#CONFIG_EAP_GPSK_SHA256=y\n\n# EAP-FAST for the integrated EAP server\n#CONFIG_EAP_FAST=y\n\n# EAP-TEAP for the integrated EAP server\n# Note: The current EAP-TEAP implementation is experimental and should not be\n# enabled for production use. The IETF RFC 7170 that defines EAP-TEAP has number\n# of conflicting statements and missing details and the implementation has\n# vendor specific workarounds for those and as such, may not interoperate with\n# any other implementation. This should not be used for anything else than\n# experimentation and interoperability testing until those issues has been\n# resolved.\n#CONFIG_EAP_TEAP=y\n\n# Wi-Fi Protected Setup (WPS)\n#CONFIG_WPS=y\n# Enable UPnP support for external WPS Registrars\n#CONFIG_WPS_UPNP=y\n# Enable WPS support with NFC config method\n#CONFIG_WPS_NFC=y\n\n# EAP-IKEv2\n#CONFIG_EAP_IKEV2=y\n\n# Trusted Network Connect (EAP-TNC)\n#CONFIG_EAP_TNC=y\n\n# EAP-EKE for the integrated EAP server\n#CONFIG_EAP_EKE=y\n\n# PKCS#12 (PFX) support (used to read private key and certificate file from\n# a file that usually has extension .p12 or .pfx)\n#CONFIG_PKCS12=y\n\n# RADIUS authentication server. This provides access to the integrated EAP\n# server from external hosts using RADIUS.\n#CONFIG_RADIUS_SERVER=y\n\n# Build IPv6 support for RADIUS operations\n#CONFIG_IPV6=y\n\n# IEEE Std 802.11r-2008 (Fast BSS Transition)\n#CONFIG_IEEE80211R=y\n\n# Use the hostapd's IEEE 802.11 authentication (ACL), but without\n# the IEEE 802.11 Management capability (e.g., FreeBSD/net80211)\n#CONFIG_DRIVER_RADIUS_ACL=y\n\n# IEEE 802.11n (High Throughput) support\nCONFIG_IEEE80211N=y\n\n# Wireless Network Management (IEEE Std 802.11v-2011)\n# Note: This is experimental and not complete implementation.\n#CONFIG_WNM=y\n\n# IEEE 802.11ac (Very High Throughput) support\nCONFIG_IEEE80211AC=y\n\n# IEEE 802.11ax HE support\n# Note: This is experimental and work in progress. The definitions are still\n# subject to change and this should not be expected to interoperate with the\n# final IEEE 802.11ax version.\n#CONFIG_IEEE80211AX=y\n\n# Remove debugging code that is printing out debug messages to stdout.\n# This can be used to reduce the size of the hostapd considerably if debugging\n# code is not needed.\n#CONFIG_NO_STDOUT_DEBUG=y\n\n# Add support for writing debug log to a file: -f /tmp/hostapd.log\n# Disabled by default.\n#CONFIG_DEBUG_FILE=y\n\n# Send debug messages to syslog instead of stdout\nCONFIG_DEBUG_SYSLOG=y\n\n# Add support for sending all debug messages (regardless of debug verbosity)\n# to the Linux kernel tracing facility. This helps debug the entire stack by\n# making it easy to record everything happening from the driver up into the\n# same file, e.g., using trace-cmd.\n#CONFIG_DEBUG_LINUX_TRACING=y\n\n# Remove support for RADIUS accounting\nCONFIG_NO_ACCOUNTING=y\n\n# Remove support for RADIUS\nCONFIG_NO_RADIUS=y\n\n# Remove support for VLANs\n#CONFIG_NO_VLAN=y\n\n# Enable support for fully dynamic VLANs. This enables hostapd to\n# automatically create bridge and VLAN interfaces if necessary.\n#CONFIG_FULL_DYNAMIC_VLAN=y\n\n# Use netlink-based kernel API for VLAN operations instead of ioctl()\n# Note: This requires libnl 3.1 or newer.\n#CONFIG_VLAN_NETLINK=y\n\n# Remove support for dumping internal state through control interface commands\n# This can be used to reduce binary size at the cost of disabling a debugging\n# option.\nCONFIG_NO_DUMP_STATE=y\n\n# Enable tracing code for developer debugging\n# This tracks use of memory allocations and other registrations and reports\n# incorrect use with a backtrace of call (or allocation) location.\n#CONFIG_WPA_TRACE=y\n# For BSD, comment out these.\n#LIBS += -lexecinfo\n#LIBS_p += -lexecinfo\n#LIBS_c += -lexecinfo\n\n# Use libbfd to get more details for developer debugging\n# This enables use of libbfd to get more detailed symbols for the backtraces\n# generated by CONFIG_WPA_TRACE=y.\n#CONFIG_WPA_TRACE_BFD=y\n# For BSD, comment out these.\n#LIBS += -lbfd -liberty -lz\n#LIBS_p += -lbfd -liberty -lz\n#LIBS_c += -lbfd -liberty -lz\n\n# hostapd depends on strong random number generation being available from the\n# operating system. os_get_random() function is used to fetch random data when\n# needed, e.g., for key generation. On Linux and BSD systems, this works by\n# reading /dev/urandom. It should be noted that the OS entropy pool needs to be\n# properly initialized before hostapd is started. This is important especially\n# on embedded devices that do not have a hardware random number generator and\n# may by default start up with minimal entropy available for random number\n# generation.\n#\n# As a safety net, hostapd is by default trying to internally collect\n# additional entropy for generating random data to mix in with the data\n# fetched from the OS. This by itself is not considered to be very strong, but\n# it may help in cases where the system pool is not initialized properly.\n# However, it is very strongly recommended that the system pool is initialized\n# with enough entropy either by using hardware assisted random number\n# generator or by storing state over device reboots.\n#\n# hostapd can be configured to maintain its own entropy store over restarts to\n# enhance random number generation. This is not perfect, but it is much more\n# secure than using the same sequence of random numbers after every reboot.\n# This can be enabled with -e<entropy file> command line option. The specified\n# file needs to be readable and writable by hostapd.\n#\n# If the os_get_random() is known to provide strong random data (e.g., on\n# Linux/BSD, the board in question is known to have reliable source of random\n# data from /dev/urandom), the internal hostapd random pool can be disabled.\n# This will save some in binary size and CPU use. However, this should only be\n# considered for builds that are known to be used on devices that meet the\n# requirements described above.\nCONFIG_NO_RANDOM_POOL=y\n\n# Should we attempt to use the getrandom(2) call that provides more reliable\n# yet secure randomness source than /dev/random on Linux 3.17 and newer.\n# Requires glibc 2.25 to build, falls back to /dev/random if unavailable.\nCONFIG_GETRANDOM=y\n\n# Should we use poll instead of select? Select is used by default.\n#CONFIG_ELOOP_POLL=y\n\n# Should we use epoll instead of select? Select is used by default.\nCONFIG_ELOOP_EPOLL=y\n\n# Should we use kqueue instead of select? Select is used by default.\n#CONFIG_ELOOP_KQUEUE=y\n\n# Select TLS implementation\n# openssl = OpenSSL (default)\n# gnutls = GnuTLS\n# internal = Internal TLSv1 implementation (experimental)\n# linux = Linux kernel AF_ALG and internal TLSv1 implementation (experimental)\n# none = Empty template\nCONFIG_TLS=internal\n\n# TLS-based EAP methods require at least TLS v1.0. Newer version of TLS (v1.1)\n# can be enabled to get a stronger construction of messages when block ciphers\n# are used.\n#CONFIG_TLSV11=y\n\n# TLS-based EAP methods require at least TLS v1.0. Newer version of TLS (v1.2)\n# can be enabled to enable use of stronger crypto algorithms.\n#CONFIG_TLSV12=y\n\n# Select which ciphers to use by default with OpenSSL if the user does not\n# specify them.\n#CONFIG_TLS_DEFAULT_CIPHERS=\"DEFAULT:!EXP:!LOW\"\n\n# If CONFIG_TLS=internal is used, additional library and include paths are\n# needed for LibTomMath. Alternatively, an integrated, minimal version of\n# LibTomMath can be used. See beginning of libtommath.c for details on benefits\n# and drawbacks of this option.\n#CONFIG_INTERNAL_LIBTOMMATH=y\n#ifndef CONFIG_INTERNAL_LIBTOMMATH\n#LTM_PATH=/usr/src/libtommath-0.39\n#CFLAGS += -I$(LTM_PATH)\n#LIBS += -L$(LTM_PATH)\n#LIBS_p += -L$(LTM_PATH)\n#endif\n# At the cost of about 4 kB of additional binary size, the internal LibTomMath\n# can be configured to include faster routines for exptmod, sqr, and div to\n# speed up DH and RSA calculation considerably\n#CONFIG_INTERNAL_LIBTOMMATH_FAST=y\n\n# Interworking (IEEE 802.11u)\n# This can be used to enable functionality to improve interworking with\n# external networks.\n#CONFIG_INTERWORKING=y\n\n# Hotspot 2.0\n#CONFIG_HS20=y\n\n# Enable SQLite database support in hlr_auc_gw, EAP-SIM DB, and eap_user_file\n#CONFIG_SQLITE=y\n\n# Enable Fast Session Transfer (FST)\n#CONFIG_FST=y\n\n# Enable CLI commands for FST testing\n#CONFIG_FST_TEST=y\n\n# Testing options\n# This can be used to enable some testing options (see also the example\n# configuration file) that are really useful only for testing clients that\n# connect to this hostapd. These options allow, for example, to drop a\n# certain percentage of probe requests or auth/(re)assoc frames.\n#\n#CONFIG_TESTING_OPTIONS=y\n\n# Automatic Channel Selection\n# This will allow hostapd to pick the channel automatically when channel is set\n# to \"acs_survey\" or \"0\". Eventually, other ACS algorithms can be added in\n# similar way.\n#\n# Automatic selection is currently only done through initialization, later on\n# we hope to do background checks to keep us moving to more ideal channels as\n# time goes by. ACS is currently only supported through the nl80211 driver and\n# your driver must have survey dump capability that is filled by the driver\n# during scanning.\n#\n# You can customize the ACS survey algorithm with the hostapd.conf variable\n# acs_num_scans.\n#\n# Supported ACS drivers:\n# * ath9k\n# * ath5k\n# * ath10k\n#\n# For more details refer to:\n# http://wireless.kernel.org/en/users/Documentation/acs\n#\n#CONFIG_ACS=y\n\n# Multiband Operation support\n# These extentions facilitate efficient use of multiple frequency bands\n# available to the AP and the devices that may associate with it.\n#CONFIG_MBO=y\n\n# Client Taxonomy\n# Has the AP retain the Probe Request and (Re)Association Request frames from\n# a client, from which a signature can be produced which can identify the model\n# of client device like \"Nexus 6P\" or \"iPhone 5s\".\n#CONFIG_TAXONOMY=y\n\n# Fast Initial Link Setup (FILS) (IEEE 802.11ai)\n#CONFIG_FILS=y\n# FILS shared key authentication with PFS\n#CONFIG_FILS_SK_PFS=y\n\n# Include internal line edit mode in hostapd_cli. This can be used to provide\n# limited command line editing and history support.\n#CONFIG_WPA_CLI_EDIT=y\n\n# Opportunistic Wireless Encryption (OWE)\n# Experimental implementation of draft-harkins-owe-07.txt\n#CONFIG_OWE=y\n\n# Airtime policy support\n#CONFIG_AIRTIME_POLICY=y\n\n# Proxy ARP support\n#CONFIG_PROXYARP=y\n\n# Override default value for the wpa_disable_eapol_key_retries configuration\n# parameter. See that parameter in hostapd.conf for more details.\n#CFLAGS += -DDEFAULT_WPA_DISABLE_EAPOL_KEY_RETRIES=1\n\n# uBus IPC/RPC System\n# Services can connect to the bus and provide methods\n# that can be called by other services or clients.\nCONFIG_UBUS=y\n\n# OpenWrt patch 380-disable-ctrl-iface-mib.patch\n# leads to the MIB only being compiled in if\n# CONFIG_CTRL_IFACE_MIB is enabled.\n#CONFIG_CTRL_IFACE_MIB=y\n"
  },
  {
    "path": "package/network/services/hostapd/files/hostapd.sh",
    "content": ". /lib/functions/network.sh\n. /lib/functions.sh\n\nwpa_supplicant_add_rate() {\n\tlocal var=\"$1\"\n\tlocal val=\"$(($2 / 1000))\"\n\tlocal sub=\"$((($2 / 100) % 10))\"\n\tappend $var \"$val\" \",\"\n\t[ $sub -gt 0 ] && append $var \".\"\n}\n\nhostapd_add_rate() {\n\tlocal var=\"$1\"\n\tlocal val=\"$(($2 / 100))\"\n\tappend $var \"$val\" \" \"\n}\n\nhostapd_append_wep_key() {\n\tlocal var=\"$1\"\n\n\twep_keyidx=0\n\tset_default key 1\n\tcase \"$key\" in\n\t\t[1234])\n\t\t\tfor idx in 1 2 3 4; do\n\t\t\t\tlocal zidx\n\t\t\t\tzidx=$(($idx - 1))\n\t\t\t\tjson_get_var ckey \"key${idx}\"\n\t\t\t\t[ -n \"$ckey\" ] && \\\n\t\t\t\t\tappend $var \"wep_key${zidx}=$(prepare_key_wep \"$ckey\")\" \"$N$T\"\n\t\t\tdone\n\t\t\twep_keyidx=$((key - 1))\n\t\t;;\n\t\t*)\n\t\t\tappend $var \"wep_key0=$(prepare_key_wep \"$key\")\" \"$N$T\"\n\t\t;;\n\tesac\n}\n\nhostapd_append_wpa_key_mgmt() {\n\tlocal auth_type_l=\"$(echo $auth_type | tr 'a-z' 'A-Z')\"\n\n\tcase \"$auth_type\" in\n\t\tpsk|eap)\n\t\t\tappend wpa_key_mgmt \"WPA-$auth_type_l\"\n\t\t\t[ \"${ieee80211r:-0}\" -gt 0 ] && append wpa_key_mgmt \"FT-${auth_type_l}\"\n\t\t\t[ \"${ieee80211w:-0}\" -gt 0 ] && append wpa_key_mgmt \"WPA-${auth_type_l}-SHA256\"\n\t\t;;\n\t\teap192)\n\t\t\tappend wpa_key_mgmt \"WPA-EAP-SUITE-B-192\"\n\t\t\t[ \"${ieee80211r:-0}\" -gt 0 ] && append wpa_key_mgmt \"FT-EAP\"\n\t\t;;\n\t\teap-eap192)\n\t\t\tappend wpa_key_mgmt \"WPA-EAP-SUITE-B-192\"\n\t\t\tappend wpa_key_mgmt \"WPA-EAP\"\n\t\t\t[ \"${ieee80211r:-0}\" -gt 0 ] && append wpa_key_mgmt \"FT-EAP\"\n\t\t\t[ \"${ieee80211w:-0}\" -gt 0 ] && append wpa_key_mgmt \"WPA-EAP-SHA256\"\n\t\t;;\n\t\tsae)\n\t\t\tappend wpa_key_mgmt \"SAE\"\n\t\t\t[ \"${ieee80211r:-0}\" -gt 0 ] && append wpa_key_mgmt \"FT-SAE\"\n\t\t;;\n\t\tpsk-sae)\n\t\t\tappend wpa_key_mgmt \"WPA-PSK\"\n\t\t\t[ \"${ieee80211r:-0}\" -gt 0 ] && append wpa_key_mgmt \"FT-PSK\"\n\t\t\t[ \"${ieee80211w:-0}\" -gt 0 ] && append wpa_key_mgmt \"WPA-PSK-SHA256\"\n\t\t\tappend wpa_key_mgmt \"SAE\"\n\t\t\t[ \"${ieee80211r:-0}\" -gt 0 ] && append wpa_key_mgmt \"FT-SAE\"\n\t\t;;\n\t\towe)\n\t\t\tappend wpa_key_mgmt \"OWE\"\n\t\t;;\n\tesac\n\n\t[ \"$fils\" -gt 0 ] && {\n\t\tcase \"$auth_type\" in\n\t\t\teap*)\n\t\t\t\tappend wpa_key_mgmt FILS-SHA256\n\t\t\t\t[ \"${ieee80211r:-0}\" -gt 0 ] && append wpa_key_mgmt FT-FILS-SHA256\n\t\t\t;;\n\t\tesac\n\t}\n\n\t[ \"$auth_osen\" = \"1\" ] && append wpa_key_mgmt \"OSEN\"\n}\n\nhostapd_add_log_config() {\n\tconfig_add_boolean \\\n\t\tlog_80211 \\\n\t\tlog_8021x \\\n\t\tlog_radius \\\n\t\tlog_wpa \\\n\t\tlog_driver \\\n\t\tlog_iapp \\\n\t\tlog_mlme\n\n\tconfig_add_int log_level\n}\n\nhostapd_common_add_device_config() {\n\tconfig_add_array basic_rate\n\tconfig_add_array supported_rates\n\tconfig_add_string beacon_rate\n\n\tconfig_add_string country country3\n\tconfig_add_boolean country_ie doth\n\tconfig_add_boolean spectrum_mgmt_required\n\tconfig_add_int local_pwr_constraint\n\tconfig_add_string require_mode\n\tconfig_add_boolean legacy_rates\n\tconfig_add_int cell_density\n\tconfig_add_int rts_threshold\n\tconfig_add_int rssi_reject_assoc_rssi\n\tconfig_add_int rssi_ignore_probe_request\n\tconfig_add_int maxassoc\n\n\tconfig_add_string acs_chan_bias\n\tconfig_add_array hostapd_options\n\n\tconfig_add_int airtime_mode\n\n\thostapd_add_log_config\n}\n\nhostapd_prepare_device_config() {\n\tlocal config=\"$1\"\n\tlocal driver=\"$2\"\n\n\tlocal base_cfg=\n\n\tjson_get_vars country country3 country_ie beacon_int:100 dtim_period:2 doth require_mode legacy_rates \\\n\t\tacs_chan_bias local_pwr_constraint spectrum_mgmt_required airtime_mode cell_density \\\n\t\trts_threshold beacon_rate rssi_reject_assoc_rssi rssi_ignore_probe_request maxassoc\n\n\thostapd_set_log_options base_cfg\n\n\tset_default country_ie 1\n\tset_default spectrum_mgmt_required 0\n\tset_default doth 1\n\tset_default legacy_rates 0\n\tset_default airtime_mode 0\n\tset_default cell_density 0\n\n\t[ -n \"$country\" ] && {\n\t\tappend base_cfg \"country_code=$country\" \"$N\"\n\t\t[ -n \"$country3\" ] && append base_cfg \"country3=$country3\" \"$N\"\n\n\t\t[ \"$country_ie\" -gt 0 ] && {\n\t\t\tappend base_cfg \"ieee80211d=1\" \"$N\"\n\t\t\t[ -n \"$local_pwr_constraint\" ] && append base_cfg \"local_pwr_constraint=$local_pwr_constraint\" \"$N\"\n\t\t\t[ \"$spectrum_mgmt_required\" -gt 0 ] && append base_cfg \"spectrum_mgmt_required=$spectrum_mgmt_required\" \"$N\"\n\t\t}\n\t\t[ \"$hwmode\" = \"a\" -a \"$doth\" -gt 0 ] && append base_cfg \"ieee80211h=1\" \"$N\"\n\t}\n\n\t[ -n \"$acs_chan_bias\" ] && append base_cfg \"acs_chan_bias=$acs_chan_bias\" \"$N\"\n\n\tlocal brlist= br\n\tjson_get_values basic_rate_list basic_rate\n\tlocal rlist= r\n\tjson_get_values rate_list supported_rates\n\n\t[ -n \"$hwmode\" ] && append base_cfg \"hw_mode=$hwmode\" \"$N\"\n\tif [ \"$hwmode\" = \"g\" ] || [ \"$hwmode\" = \"a\" ]; then\n\t\t[ -n \"$require_mode\" ] && legacy_rates=0\n\t\tcase \"$require_mode\" in\n\t\t\tn) append base_cfg \"require_ht=1\" \"$N\";;\n\t\t\tac) append base_cfg \"require_vht=1\" \"$N\";;\n\t\tesac\n\tfi\n\tcase \"$hwmode\" in\n\t\tb)\n\t\t\tif [ \"$cell_density\" -eq 1 ]; then\n\t\t\t\tset_default rate_list \"5500 11000\"\n\t\t\t\tset_default basic_rate_list \"5500 11000\"\n\t\t\telif [ \"$cell_density\" -ge 2 ]; then\n\t\t\t\tset_default rate_list \"11000\"\n\t\t\t\tset_default basic_rate_list \"11000\"\n\t\t\tfi\n\t\t;;\n\t\tg)\n\t\t\tif [ \"$cell_density\" -eq 0 ] || [ \"$cell_density\" -eq 1 ]; then\n\t\t\t\tif [ \"$legacy_rates\" -eq 0 ]; then\n\t\t\t\t\tset_default rate_list \"6000 9000 12000 18000 24000 36000 48000 54000\"\n\t\t\t\t\tset_default basic_rate_list \"6000 12000 24000\"\n\t\t\t\telif [ \"$cell_density\" -eq 1 ]; then\n\t\t\t\t\tset_default rate_list \"5500 6000 9000 11000 12000 18000 24000 36000 48000 54000\"\n\t\t\t\t\tset_default basic_rate_list \"5500 11000\"\n\t\t\t\tfi\n\t\t\telif [ \"$cell_density\" -ge 3 ] && [ \"$legacy_rates\" -ne 0 ] || [ \"$cell_density\" -eq 2 ]; then\n\t\t\t\tif [ \"$legacy_rates\" -eq 0 ]; then\n\t\t\t\t\tset_default rate_list \"12000 18000 24000 36000 48000 54000\"\n\t\t\t\t\tset_default basic_rate_list \"12000 24000\"\n\t\t\t\telse\n\t\t\t\t\tset_default rate_list \"11000 12000 18000 24000 36000 48000 54000\"\n\t\t\t\t\tset_default basic_rate_list \"11000\"\n\t\t\t\tfi\n\t\t\telif [ \"$cell_density\" -ge 3 ]; then\n\t\t\t\tset_default rate_list \"24000 36000 48000 54000\"\n\t\t\t\tset_default basic_rate_list \"24000\"\n\t\t\tfi\n\t\t;;\n\t\ta)\n\t\t\tif [ \"$cell_density\" -eq 1 ]; then\n\t\t\t\tset_default rate_list \"6000 9000 12000 18000 24000 36000 48000 54000\"\n\t\t\t\tset_default basic_rate_list \"6000 12000 24000\"\n\t\t\telif [ \"$cell_density\" -eq 2 ]; then\n\t\t\t\tset_default rate_list \"12000 18000 24000 36000 48000 54000\"\n\t\t\t\tset_default basic_rate_list \"12000 24000\"\n\t\t\telif [ \"$cell_density\" -ge 3 ]; then\n\t\t\t\tset_default rate_list \"24000 36000 48000 54000\"\n\t\t\t\tset_default basic_rate_list \"24000\"\n\t\t\tfi\n\t\t;;\n\tesac\n\n\tfor r in $rate_list; do\n\t\thostapd_add_rate rlist \"$r\"\n\tdone\n\n\tfor br in $basic_rate_list; do\n\t\thostapd_add_rate brlist \"$br\"\n\tdone\n\n\t[ -n \"$rssi_reject_assoc_rssi\" ] && append base_cfg \"rssi_reject_assoc_rssi=$rssi_reject_assoc_rssi\" \"$N\"\n\t[ -n \"$rssi_ignore_probe_request\" ] && append base_cfg \"rssi_ignore_probe_request=$rssi_ignore_probe_request\" \"$N\"\n\t[ -n \"$beacon_rate\" ] && append base_cfg \"beacon_rate=$beacon_rate\" \"$N\"\n\t[ -n \"$rlist\" ] && append base_cfg \"supported_rates=$rlist\" \"$N\"\n\t[ -n \"$brlist\" ] && append base_cfg \"basic_rates=$brlist\" \"$N\"\n\tappend base_cfg \"beacon_int=$beacon_int\" \"$N\"\n\t[ -n \"$rts_threshold\" ] && append base_cfg \"rts_threshold=$rts_threshold\" \"$N\"\n\tappend base_cfg \"dtim_period=$dtim_period\" \"$N\"\n\t[ \"$airtime_mode\" -gt 0 ] && append base_cfg \"airtime_mode=$airtime_mode\" \"$N\"\n\t[ -n \"$maxassoc\" ] && append base_cfg \"iface_max_num_sta=$maxassoc\" \"$N\"\n\n\tjson_get_values opts hostapd_options\n\tfor val in $opts; do\n\t\tappend base_cfg \"$val\" \"$N\"\n\tdone\n\n\tcat > \"$config\" <<EOF\ndriver=$driver\n$base_cfg\nEOF\n}\n\nhostapd_common_add_bss_config() {\n\tconfig_add_string 'bssid:macaddr' 'ssid:string'\n\tconfig_add_boolean wds wmm uapsd hidden utf8_ssid\n\n\tconfig_add_int maxassoc max_inactivity\n\tconfig_add_boolean disassoc_low_ack isolate short_preamble skip_inactivity_poll\n\n\tconfig_add_int \\\n\t\twep_rekey eap_reauth_period \\\n\t\twpa_group_rekey wpa_pair_rekey wpa_master_rekey\n\tconfig_add_boolean wpa_strict_rekey\n\tconfig_add_boolean wpa_disable_eapol_key_retries\n\n\tconfig_add_boolean tdls_prohibit\n\n\tconfig_add_boolean rsn_preauth auth_cache\n\tconfig_add_int ieee80211w\n\tconfig_add_int eapol_version\n\n\tconfig_add_string 'auth_server:host' 'server:host'\n\tconfig_add_string auth_secret key\n\tconfig_add_int 'auth_port:port' 'port:port'\n\n\tconfig_add_string acct_server\n\tconfig_add_string acct_secret\n\tconfig_add_int acct_port\n\tconfig_add_int acct_interval\n\n\tconfig_add_int bss_load_update_period chan_util_avg_period\n\n\tconfig_add_string dae_client\n\tconfig_add_string dae_secret\n\tconfig_add_int dae_port\n\n\tconfig_add_string nasid\n\tconfig_add_string ownip\n\tconfig_add_string radius_client_addr\n\tconfig_add_string iapp_interface\n\tconfig_add_string eap_type ca_cert client_cert identity anonymous_identity auth priv_key priv_key_pwd\n\tconfig_add_boolean ca_cert_usesystem ca_cert2_usesystem\n\tconfig_add_string subject_match subject_match2\n\tconfig_add_array altsubject_match altsubject_match2\n\tconfig_add_array domain_match domain_match2 domain_suffix_match domain_suffix_match2\n\tconfig_add_string ieee80211w_mgmt_cipher\n\n\tconfig_add_int dynamic_vlan vlan_naming vlan_no_bridge\n\tconfig_add_string vlan_tagged_interface vlan_bridge\n\tconfig_add_string vlan_file\n\n\tconfig_add_string 'key1:wepkey' 'key2:wepkey' 'key3:wepkey' 'key4:wepkey' 'password:wpakey'\n\n\tconfig_add_string wpa_psk_file\n\n\tconfig_add_int multi_ap\n\n\tconfig_add_boolean wps_pushbutton wps_label ext_registrar wps_pbc_in_m1\n\tconfig_add_int wps_ap_setup_locked wps_independent\n\tconfig_add_string wps_device_type wps_device_name wps_manufacturer wps_pin\n\tconfig_add_string multi_ap_backhaul_ssid multi_ap_backhaul_key\n\n\tconfig_add_boolean wnm_sleep_mode wnm_sleep_mode_no_keys bss_transition\n\tconfig_add_int time_advertisement\n\tconfig_add_string time_zone\n\tconfig_add_string vendor_elements\n\n\tconfig_add_boolean ieee80211k rrm_neighbor_report rrm_beacon_report\n\n\tconfig_add_boolean ftm_responder stationary_ap\n\tconfig_add_string lci civic\n\n\tconfig_add_boolean ieee80211r pmk_r1_push ft_psk_generate_local ft_over_ds\n\tconfig_add_int r0_key_lifetime reassociation_deadline\n\tconfig_add_string mobility_domain r1_key_holder\n\tconfig_add_array r0kh r1kh\n\n\tconfig_add_int ieee80211w_max_timeout ieee80211w_retry_timeout\n\n\tconfig_add_string macfilter 'macfile:file'\n\tconfig_add_array 'maclist:list(macaddr)'\n\n\tconfig_add_array bssid_blacklist\n\tconfig_add_array bssid_whitelist\n\n\tconfig_add_int mcast_rate\n\tconfig_add_array basic_rate\n\tconfig_add_array supported_rates\n\n\tconfig_add_boolean sae_require_mfp\n\tconfig_add_int sae_pwe\n\n\tconfig_add_string 'owe_transition_bssid:macaddr' 'owe_transition_ssid:string'\n\n\tconfig_add_boolean iw_enabled iw_internet iw_asra iw_esr iw_uesa\n\tconfig_add_int iw_access_network_type iw_venue_group iw_venue_type\n\tconfig_add_int iw_ipaddr_type_availability iw_gas_address3\n\tconfig_add_string iw_hessid iw_network_auth_type iw_qos_map_set\n\tconfig_add_array iw_roaming_consortium iw_domain_name iw_anqp_3gpp_cell_net iw_nai_realm\n\tconfig_add_array iw_anqp_elem iw_venue_name iw_venue_url\n\n\tconfig_add_boolean hs20 disable_dgaf osen\n\tconfig_add_int anqp_domain_id\n\tconfig_add_int hs20_deauth_req_timeout\n\tconfig_add_array hs20_oper_friendly_name\n\tconfig_add_array osu_provider\n\tconfig_add_array operator_icon\n\tconfig_add_array hs20_conn_capab\n\tconfig_add_string osu_ssid hs20_wan_metrics hs20_operating_class hs20_t_c_filename hs20_t_c_timestamp\n\n\tconfig_add_string hs20_t_c_server_url\n\n\tconfig_add_array airtime_sta_weight\n\tconfig_add_int airtime_bss_weight airtime_bss_limit\n\n\tconfig_add_boolean multicast_to_unicast proxy_arp per_sta_vif\n\n\tconfig_add_array hostapd_bss_options\n\tconfig_add_boolean default_disabled\n\n\tconfig_add_boolean request_cui\n\tconfig_add_array radius_auth_req_attr\n\tconfig_add_array radius_acct_req_attr\n\n\tconfig_add_int eap_server\n\tconfig_add_string eap_user_file ca_cert server_cert private_key private_key_passwd server_id\n\n\tconfig_add_boolean fils\n\tconfig_add_string fils_dhcp\n}\n\nhostapd_set_vlan_file() {\n\tlocal ifname=\"$1\"\n\tlocal vlan=\"$2\"\n\tjson_get_vars name vid\n\techo \"${vid} ${ifname}-${name}\" >> /var/run/hostapd-${ifname}.vlan\n\twireless_add_vlan \"${vlan}\" \"${ifname}-${name}\"\n}\n\nhostapd_set_vlan() {\n\tlocal ifname=\"$1\"\n\n\trm -f /var/run/hostapd-${ifname}.vlan\n\tfor_each_vlan hostapd_set_vlan_file ${ifname}\n}\n\nhostapd_set_psk_file() {\n\tlocal ifname=\"$1\"\n\tlocal vlan=\"$2\"\n\tlocal vlan_id=\"\"\n\n\tjson_get_vars mac vid key\n\tset_default mac \"00:00:00:00:00:00\"\n\t[ -n \"$vid\" ] && vlan_id=\"vlanid=$vid \"\n\techo \"${vlan_id} ${mac} ${key}\" >> /var/run/hostapd-${ifname}.psk\n}\n\nhostapd_set_psk() {\n\tlocal ifname=\"$1\"\n\n\trm -f /var/run/hostapd-${ifname}.psk\n\tfor_each_station hostapd_set_psk_file ${ifname}\n}\n\nappend_iw_roaming_consortium() {\n\t[ -n \"$1\" ] && append bss_conf \"roaming_consortium=$1\" \"$N\"\n}\n\nappend_iw_domain_name() {\n\tif [ -z \"$iw_domain_name_conf\" ]; then\n\t\tiw_domain_name_conf=\"$1\"\n\telse\n\t\tiw_domain_name_conf=\"$iw_domain_name_conf,$1\"\n\tfi\n}\n\nappend_iw_anqp_3gpp_cell_net() {\n\tif [ -z \"$iw_anqp_3gpp_cell_net_conf\" ]; then\n\t\tiw_anqp_3gpp_cell_net_conf=\"$1\"\n\telse\n\t\tiw_anqp_3gpp_cell_net_conf=\"$iw_anqp_3gpp_cell_net_conf:$1\"\n\tfi\n}\n\nappend_iw_anqp_elem() {\n\t[ -n \"$1\" ] && append bss_conf \"anqp_elem=$1\" \"$N\"\n}\n\nappend_iw_nai_realm() {\n\t[ -n \"$1\" ] && append bss_conf \"nai_realm=$1\" \"$N\"\n}\n\nappend_iw_venue_name() {\n\tappend bss_conf \"venue_name=$1\" \"$N\"\n}\n\nappend_iw_venue_url() {\n\tappend bss_conf \"venue_url=$1\" \"$N\"\n}\n\nappend_hs20_oper_friendly_name() {\n\tappend bss_conf \"hs20_oper_friendly_name=$1\" \"$N\"\n}\n\nappend_osu_provider_friendly_name() {\n\tappend bss_conf \"osu_friendly_name=$1\" \"$N\"\n}\n\nappend_osu_provider_service_desc() {\n\tappend bss_conf \"osu_service_desc=$1\" \"$N\"\n}\n\nappend_hs20_icon() {\n\tlocal width height lang type path\n\tconfig_get width \"$1\" width\n\tconfig_get height \"$1\" height\n\tconfig_get lang \"$1\" lang\n\tconfig_get type \"$1\" type\n\tconfig_get path \"$1\" path\n\n\tappend bss_conf \"hs20_icon=$width:$height:$lang:$type:$1:$path\" \"$N\"\n}\n\nappend_hs20_icons() {\n\tconfig_load wireless\n\tconfig_foreach append_hs20_icon hs20-icon\n}\n\nappend_operator_icon() {\n\tappend bss_conf \"operator_icon=$1\" \"$N\"\n}\n\nappend_osu_icon() {\n\tappend bss_conf \"osu_icon=$1\" \"$N\"\n}\n\nappend_osu_provider() {\n\tlocal cfgtype osu_server_uri osu_friendly_name osu_nai osu_nai2 osu_method_list\n\n\tconfig_load wireless\n\tconfig_get cfgtype \"$1\" TYPE\n\t[ \"$cfgtype\" != \"osu-provider\" ] && return\n\n\tappend bss_conf \"# provider $1\" \"$N\"\n\tconfig_get osu_server_uri \"$1\" osu_server_uri\n\tconfig_get osu_nai \"$1\" osu_nai\n\tconfig_get osu_nai2 \"$1\" osu_nai2\n\tconfig_get osu_method_list \"$1\" osu_method\n\n\tappend bss_conf \"osu_server_uri=$osu_server_uri\" \"$N\"\n\tappend bss_conf \"osu_nai=$osu_nai\" \"$N\"\n\tappend bss_conf \"osu_nai2=$osu_nai2\" \"$N\"\n\tappend bss_conf \"osu_method_list=$osu_method_list\" \"$N\"\n\n\tconfig_list_foreach \"$1\" osu_service_desc append_osu_provider_service_desc\n\tconfig_list_foreach \"$1\" osu_friendly_name append_osu_friendly_name\n\tconfig_list_foreach \"$1\" osu_icon append_osu_icon\n\n\tappend bss_conf \"$N\"\n}\n\nappend_hs20_conn_capab() {\n\t[ -n \"$1\" ] && append bss_conf \"hs20_conn_capab=$1\" \"$N\"\n}\n\nappend_radius_acct_req_attr() {\n\t[ -n \"$1\" ] && append bss_conf \"radius_acct_req_attr=$1\" \"$N\"\n}\n\nappend_radius_auth_req_attr() {\n\t[ -n \"$1\" ] && append bss_conf \"radius_auth_req_attr=$1\" \"$N\"\n}\n\nappend_airtime_sta_weight() {\n\t[ -n \"$1\" ] && append bss_conf \"airtime_sta_weight=$1\" \"$N\"\n}\n\nhostapd_set_bss_options() {\n\tlocal var=\"$1\"\n\tlocal phy=\"$2\"\n\tlocal vif=\"$3\"\n\n\twireless_vif_parse_encryption\n\n\tlocal bss_conf bss_md5sum ft_key\n\tlocal wep_rekey wpa_group_rekey wpa_pair_rekey wpa_master_rekey wpa_key_mgmt\n\n\tjson_get_vars \\\n\t\twep_rekey wpa_group_rekey wpa_pair_rekey wpa_master_rekey wpa_strict_rekey \\\n\t\twpa_disable_eapol_key_retries tdls_prohibit \\\n\t\tmaxassoc max_inactivity disassoc_low_ack isolate auth_cache \\\n\t\twps_pushbutton wps_label ext_registrar wps_pbc_in_m1 wps_ap_setup_locked \\\n\t\twps_independent wps_device_type wps_device_name wps_manufacturer wps_pin \\\n\t\tmacfilter ssid utf8_ssid wmm uapsd hidden short_preamble rsn_preauth \\\n\t\tiapp_interface eapol_version dynamic_vlan ieee80211w nasid \\\n\t\tacct_server acct_secret acct_port acct_interval \\\n\t\tbss_load_update_period chan_util_avg_period sae_require_mfp sae_pwe \\\n\t\tmulti_ap multi_ap_backhaul_ssid multi_ap_backhaul_key skip_inactivity_poll \\\n\t\tairtime_bss_weight airtime_bss_limit airtime_sta_weight \\\n\t\tmulticast_to_unicast proxy_arp per_sta_vif \\\n\t\teap_server eap_user_file ca_cert server_cert private_key private_key_passwd server_id \\\n\t\tvendor_elements fils\n\n\tset_default fils 0\n\tset_default isolate 0\n\tset_default maxassoc 0\n\tset_default max_inactivity 0\n\tset_default short_preamble 1\n\tset_default disassoc_low_ack 1\n\tset_default skip_inactivity_poll 0\n\tset_default hidden 0\n\tset_default wmm 1\n\tset_default uapsd 1\n\tset_default wpa_disable_eapol_key_retries 0\n\tset_default tdls_prohibit 0\n\tset_default eapol_version $((wpa & 1))\n\tset_default acct_port 1813\n\tset_default bss_load_update_period 60\n\tset_default chan_util_avg_period 600\n\tset_default utf8_ssid 1\n\tset_default multi_ap 0\n\tset_default airtime_bss_weight 0\n\tset_default airtime_bss_limit 0\n\tset_default eap_server 0\n\n\t/usr/sbin/hostapd -vfils || fils=0\n\n\tappend bss_conf \"ctrl_interface=/var/run/hostapd\"\n\tif [ \"$isolate\" -gt 0 ]; then\n\t\tappend bss_conf \"ap_isolate=$isolate\" \"$N\"\n\tfi\n\tif [ \"$maxassoc\" -gt 0 ]; then\n\t\tappend bss_conf \"max_num_sta=$maxassoc\" \"$N\"\n\tfi\n\tif [ \"$max_inactivity\" -gt 0 ]; then\n\t\tappend bss_conf \"ap_max_inactivity=$max_inactivity\" \"$N\"\n\tfi\n\n\t[ \"$airtime_bss_weight\" -gt 0 ] && append bss_conf \"airtime_bss_weight=$airtime_bss_weight\" \"$N\"\n\t[ \"$airtime_bss_limit\" -gt 0 ] && append bss_conf \"airtime_bss_limit=$airtime_bss_limit\" \"$N\"\n\tjson_for_each_item append_airtime_sta_weight airtime_sta_weight\n\n\tappend bss_conf \"bss_load_update_period=$bss_load_update_period\" \"$N\"\n\tappend bss_conf \"chan_util_avg_period=$chan_util_avg_period\" \"$N\"\n\tappend bss_conf \"disassoc_low_ack=$disassoc_low_ack\" \"$N\"\n\tappend bss_conf \"skip_inactivity_poll=$skip_inactivity_poll\" \"$N\"\n\tappend bss_conf \"preamble=$short_preamble\" \"$N\"\n\tappend bss_conf \"wmm_enabled=$wmm\" \"$N\"\n\tappend bss_conf \"ignore_broadcast_ssid=$hidden\" \"$N\"\n\tappend bss_conf \"uapsd_advertisement_enabled=$uapsd\" \"$N\"\n\tappend bss_conf \"utf8_ssid=$utf8_ssid\" \"$N\"\n\tappend bss_conf \"multi_ap=$multi_ap\" \"$N\"\n\t[ -n \"$vendor_elements\" ] && append bss_conf \"vendor_elements=$vendor_elements\" \"$N\"\n\n\t[ \"$tdls_prohibit\" -gt 0 ] && append bss_conf \"tdls_prohibit=$tdls_prohibit\" \"$N\"\n\n\t[ \"$wpa\" -gt 0 ] && {\n\t\t[ -n \"$wpa_group_rekey\"  ] && append bss_conf \"wpa_group_rekey=$wpa_group_rekey\" \"$N\"\n\t\t[ -n \"$wpa_pair_rekey\"   ] && append bss_conf \"wpa_ptk_rekey=$wpa_pair_rekey\"    \"$N\"\n\t\t[ -n \"$wpa_master_rekey\" ] && append bss_conf \"wpa_gmk_rekey=$wpa_master_rekey\"  \"$N\"\n\t\t[ -n \"$wpa_strict_rekey\" ] && append bss_conf \"wpa_strict_rekey=$wpa_strict_rekey\" \"$N\"\n\t}\n\n\t[ -n \"$nasid\" ] && append bss_conf \"nas_identifier=$nasid\" \"$N\"\n\t[ -n \"$acct_server\" ] && {\n\t\tappend bss_conf \"acct_server_addr=$acct_server\" \"$N\"\n\t\tappend bss_conf \"acct_server_port=$acct_port\" \"$N\"\n\t\t[ -n \"$acct_secret\" ] && \\\n\t\t\tappend bss_conf \"acct_server_shared_secret=$acct_secret\" \"$N\"\n\t\t[ -n \"$acct_interval\" ] && \\\n\t\t\tappend bss_conf \"radius_acct_interim_interval=$acct_interval\" \"$N\"\n\t\tjson_for_each_item append_radius_acct_req_attr radius_acct_req_attr\n\t}\n\n\tcase \"$auth_type\" in\n\t\tsae|owe|eap192|eap-eap192)\n\t\t\tset_default ieee80211w 2\n\t\t\tset_default sae_require_mfp 1\n\t\t\tset_default sae_pwe 2\n\t\t;;\n\t\tpsk-sae)\n\t\t\tset_default ieee80211w 1\n\t\t\tset_default sae_require_mfp 1\n\t\t\tset_default sae_pwe 2\n\t\t;;\n\tesac\n\t[ -n \"$sae_require_mfp\" ] && append bss_conf \"sae_require_mfp=$sae_require_mfp\" \"$N\"\n\t[ -n \"$sae_pwe\" ] && append bss_conf \"sae_pwe=$sae_pwe\" \"$N\"\n\n\tlocal vlan_possible=\"\"\n\n\tcase \"$auth_type\" in\n\t\tnone|owe)\n\t\t\tjson_get_vars owe_transition_bssid owe_transition_ssid\n\n\t\t\t[ -n \"$owe_transition_ssid\" ] && append bss_conf \"owe_transition_ssid=\\\"$owe_transition_ssid\\\"\" \"$N\"\n\t\t\t[ -n \"$owe_transition_bssid\" ] && append bss_conf \"owe_transition_bssid=$owe_transition_bssid\" \"$N\"\n\n\t\t\twps_possible=1\n\t\t\t# Here we make the assumption that if we're in open mode\n\t\t\t# with WPS enabled, we got to be in unconfigured state.\n\t\t\twps_not_configured=1\n\t\t;;\n\t\tpsk|sae|psk-sae)\n\t\t\tjson_get_vars key wpa_psk_file\n\t\t\tif [ ${#key} -eq 64 ]; then\n\t\t\t\tappend bss_conf \"wpa_psk=$key\" \"$N\"\n\t\t\telif [ ${#key} -ge 8 ] && [ ${#key} -le 63 ]; then\n\t\t\t\tappend bss_conf \"wpa_passphrase=$key\" \"$N\"\n\t\t\telif [ -n \"$key\" ] || [ -z \"$wpa_psk_file\" ]; then\n\t\t\t\twireless_setup_vif_failed INVALID_WPA_PSK\n\t\t\t\treturn 1\n\t\t\tfi\n\t\t\t[ -z \"$wpa_psk_file\" ] && set_default wpa_psk_file /var/run/hostapd-$ifname.psk\n\t\t\t[ -n \"$wpa_psk_file\" ] && {\n\t\t\t\t[ -e \"$wpa_psk_file\" ] || touch \"$wpa_psk_file\"\n\t\t\t\tappend bss_conf \"wpa_psk_file=$wpa_psk_file\" \"$N\"\n\t\t\t}\n\t\t\t[ \"$eapol_version\" -ge \"1\" -a \"$eapol_version\" -le \"2\" ] && append bss_conf \"eapol_version=$eapol_version\" \"$N\"\n\n\t\t\tset_default dynamic_vlan 0\n\t\t\tvlan_possible=1\n\t\t\twps_possible=1\n\t\t;;\n\t\teap|eap192|eap-eap192)\n\t\t\tjson_get_vars \\\n\t\t\t\tauth_server auth_secret auth_port \\\n\t\t\t\tdae_client dae_secret dae_port \\\n\t\t\t\townip radius_client_addr \\\n\t\t\t\teap_reauth_period request_cui \\\n\t\t\t\terp_domain mobility_domain \\\n\t\t\t\tfils_realm fils_dhcp\n\n\t\t\t# radius can provide VLAN ID for clients\n\t\t\tvlan_possible=1\n\n\t\t\t# legacy compatibility\n\t\t\t[ -n \"$auth_server\" ] || json_get_var auth_server server\n\t\t\t[ -n \"$auth_port\" ] || json_get_var auth_port port\n\t\t\t[ -n \"$auth_secret\" ] || json_get_var auth_secret key\n\n\t\t\t[ \"$fils\" -gt 0 ] && {\n\t\t\t\tset_default erp_domain \"$mobility_domain\"\n\t\t\t\tset_default erp_domain \"$(echo \"$ssid\" | md5sum | head -c 8)\"\n\t\t\t\tset_default fils_realm \"$erp_domain\"\n\n\t\t\t\tappend bss_conf \"erp_send_reauth_start=1\" \"$N\"\n\t\t\t\tappend bss_conf \"erp_domain=$erp_domain\" \"$N\"\n\t\t\t\tappend bss_conf \"fils_realm=$fils_realm\" \"$N\"\n\t\t\t\tappend bss_conf \"fils_cache_id=$(echo \"$fils_realm\" | md5sum | head -c 4)\" \"$N\"\n\n\t\t\t\t[ \"$fils_dhcp\" = \"*\" ] && {\n\t\t\t\t\tjson_get_values network network\n\t\t\t\t\tfils_dhcp=\n\t\t\t\t\tfor net in $network; do\n\t\t\t\t\t\tfils_dhcp=\"$(ifstatus \"$net\" | jsonfilter -e '@.data.dhcpserver')\"\n\t\t\t\t\t\t[ -n \"$fils_dhcp\" ] && break\n\t\t\t\t\tdone\n\n\t\t\t\t\t[ -z \"$fils_dhcp\" -a -n \"$network_bridge\" -a -n \"$network_ifname\" ] && \\\n\t\t\t\t\t\tfils_dhcp=\"$(udhcpc -B -n -q -s /lib/netifd/dhcp-get-server.sh -t 1 -i \"$network_ifname\" 2>/dev/null)\"\n\t\t\t\t}\n\t\t\t\t[ -n \"$fils_dhcp\" ] && append bss_conf \"dhcp_server=$fils_dhcp\" \"$N\"\n\t\t\t}\n\n\t\t\tset_default auth_port 1812\n\t\t\tset_default dae_port 3799\n\t\t\tset_default request_cui 0\n\n\t\t\t[ \"$eap_server\" -eq 0 ] && {\n\t\t\t\tappend bss_conf \"auth_server_addr=$auth_server\" \"$N\"\n\t\t\t\tappend bss_conf \"auth_server_port=$auth_port\" \"$N\"\n\t\t\t\tappend bss_conf \"auth_server_shared_secret=$auth_secret\" \"$N\"\n\t\t\t}\n\n\t\t\t[ \"$request_cui\" -gt 0 ] && append bss_conf \"radius_request_cui=$request_cui\" \"$N\"\n\t\t\t[ -n \"$eap_reauth_period\" ] && append bss_conf \"eap_reauth_period=$eap_reauth_period\" \"$N\"\n\n\t\t\t[ -n \"$dae_client\" -a -n \"$dae_secret\" ] && {\n\t\t\t\tappend bss_conf \"radius_das_port=$dae_port\" \"$N\"\n\t\t\t\tappend bss_conf \"radius_das_client=$dae_client $dae_secret\" \"$N\"\n\t\t\t}\n\t\t\tjson_for_each_item append_radius_auth_req_attr radius_auth_req_attr\n\n\t\t\t[ -n \"$ownip\" ] && append bss_conf \"own_ip_addr=$ownip\" \"$N\"\n\t\t\t[ -n \"$radius_client_addr\" ] && append bss_conf \"radius_client_addr=$radius_client_addr\" \"$N\"\n\t\t\tappend bss_conf \"eapol_key_index_workaround=1\" \"$N\"\n\t\t\tappend bss_conf \"ieee8021x=1\" \"$N\"\n\n\t\t\t[ \"$eapol_version\" -ge \"1\" -a \"$eapol_version\" -le \"2\" ] && append bss_conf \"eapol_version=$eapol_version\" \"$N\"\n\t\t;;\n\t\twep)\n\t\t\tlocal wep_keyidx=0\n\t\t\tjson_get_vars key\n\t\t\thostapd_append_wep_key bss_conf\n\t\t\tappend bss_conf \"wep_default_key=$wep_keyidx\" \"$N\"\n\t\t\t[ -n \"$wep_rekey\" ] && append bss_conf \"wep_rekey_period=$wep_rekey\" \"$N\"\n\t\t;;\n\tesac\n\n\tlocal auth_algs=$((($auth_mode_shared << 1) | $auth_mode_open))\n\tappend bss_conf \"auth_algs=${auth_algs:-1}\" \"$N\"\n\tappend bss_conf \"wpa=$wpa\" \"$N\"\n\t[ -n \"$wpa_pairwise\" ] && append bss_conf \"wpa_pairwise=$wpa_pairwise\" \"$N\"\n\n\tset_default wps_pushbutton 0\n\tset_default wps_label 0\n\tset_default wps_pbc_in_m1 0\n\n\tconfig_methods=\n\t[ \"$wps_pushbutton\" -gt 0 ] && append config_methods push_button\n\t[ \"$wps_label\" -gt 0 ] && append config_methods label\n\n\t# WPS not possible on Multi-AP backhaul-only SSID\n\t[ \"$multi_ap\" = 1 ] && wps_possible=\n\n\t[ -n \"$wps_possible\" -a -n \"$config_methods\" ] && {\n\t\tset_default ext_registrar 0\n\t\tset_default wps_device_type \"6-0050F204-1\"\n\t\tset_default wps_device_name \"OpenWrt AP\"\n\t\tset_default wps_manufacturer \"www.openwrt.org\"\n\t\tset_default wps_independent 1\n\n\t\twps_state=2\n\t\t[ -n \"$wps_not_configured\" ] && wps_state=1\n\n\t\t[ \"$ext_registrar\" -gt 0 -a -n \"$network_bridge\" ] && append bss_conf \"upnp_iface=$network_bridge\" \"$N\"\n\n\t\tappend bss_conf \"eap_server=1\" \"$N\"\n\t\t[ -n \"$wps_pin\" ] && append bss_conf \"ap_pin=$wps_pin\" \"$N\"\n\t\tappend bss_conf \"wps_state=$wps_state\" \"$N\"\n\t\tappend bss_conf \"device_type=$wps_device_type\" \"$N\"\n\t\tappend bss_conf \"device_name=$wps_device_name\" \"$N\"\n\t\tappend bss_conf \"manufacturer=$wps_manufacturer\" \"$N\"\n\t\tappend bss_conf \"config_methods=$config_methods\" \"$N\"\n\t\tappend bss_conf \"wps_independent=$wps_independent\" \"$N\"\n\t\t[ -n \"$wps_ap_setup_locked\" ] && append bss_conf \"ap_setup_locked=$wps_ap_setup_locked\" \"$N\"\n\t\t[ \"$wps_pbc_in_m1\" -gt 0 ] && append bss_conf \"pbc_in_m1=$wps_pbc_in_m1\" \"$N\"\n\t\t[ \"$multi_ap\" -gt 0 ] && [ -n \"$multi_ap_backhaul_ssid\" ] && {\n\t\t\tappend bss_conf \"multi_ap_backhaul_ssid=\\\"$multi_ap_backhaul_ssid\\\"\" \"$N\"\n\t\t\tif [ -z \"$multi_ap_backhaul_key\" ]; then\n\t\t\t\t:\n\t\t\telif [ ${#multi_ap_backhaul_key} -lt 8 ]; then\n\t\t\t\twireless_setup_vif_failed INVALID_WPA_PSK\n\t\t\t\treturn 1\n\t\t\telif [ ${#multi_ap_backhaul_key} -eq 64 ]; then\n\t\t\t\tappend bss_conf \"multi_ap_backhaul_wpa_psk=$multi_ap_backhaul_key\" \"$N\"\n\t\t\telse\n\t\t\t\tappend bss_conf \"multi_ap_backhaul_wpa_passphrase=$multi_ap_backhaul_key\" \"$N\"\n\t\t\tfi\n\t\t}\n\t}\n\n\tappend bss_conf \"ssid=$ssid\" \"$N\"\n\t[ -n \"$network_bridge\" ] && append bss_conf \"bridge=$network_bridge${N}wds_bridge=\" \"$N\"\n\t[ -n \"$network_ifname\" ] && append bss_conf \"snoop_iface=$network_ifname\" \"$N\"\n\t[ -n \"$iapp_interface\" ] && {\n\t\tlocal ifname\n\t\tnetwork_get_device ifname \"$iapp_interface\" || ifname=\"$iapp_interface\"\n\t\tappend bss_conf \"iapp_interface=$ifname\" \"$N\"\n\t}\n\n\tjson_get_vars time_advertisement time_zone wnm_sleep_mode wnm_sleep_mode_no_keys bss_transition\n\tset_default bss_transition 0\n\tset_default wnm_sleep_mode 0\n\tset_default wnm_sleep_mode_no_keys 0\n\n\t[ -n \"$time_advertisement\" ] && append bss_conf \"time_advertisement=$time_advertisement\" \"$N\"\n\t[ -n \"$time_zone\" ] && append bss_conf \"time_zone=$time_zone\" \"$N\"\n\tif [ \"$wnm_sleep_mode\" -eq \"1\" ]; then\n\t\tappend bss_conf \"wnm_sleep_mode=1\" \"$N\"\n\t\t[ \"$wnm_sleep_mode_no_keys\" -eq \"1\" ] && append bss_conf \"wnm_sleep_mode_no_keys=1\" \"$N\"\n\tfi\n\t[ \"$bss_transition\" -eq \"1\" ] && append bss_conf \"bss_transition=1\" \"$N\"\n\n\tjson_get_vars ieee80211k rrm_neighbor_report rrm_beacon_report\n\tset_default ieee80211k 0\n\tif [ \"$ieee80211k\" -eq \"1\" ]; then\n\t\tset_default rrm_neighbor_report 1\n\t\tset_default rrm_beacon_report 1\n\telse\n\t\tset_default rrm_neighbor_report 0\n\t\tset_default rrm_beacon_report 0\n\tfi\n\n\t[ \"$rrm_neighbor_report\" -eq \"1\" ] && append bss_conf \"rrm_neighbor_report=1\" \"$N\"\n\t[ \"$rrm_beacon_report\" -eq \"1\" ] && append bss_conf \"rrm_beacon_report=1\" \"$N\"\n\n\tjson_get_vars ftm_responder stationary_ap lci civic\n\tset_default ftm_responder 0\n\tif [ \"$ftm_responder\" -eq \"1\" ]; then\n\t\tset_default stationary_ap 0\n\t\tiw phy \"$phy\" info | grep -q \"ENABLE_FTM_RESPONDER\" && {\n\t\t\tappend bss_conf \"ftm_responder=1\" \"$N\"\n\t\t\t[ \"$stationary_ap\" -eq \"1\" ] && append bss_conf \"stationary_ap=1\" \"$N\"\n\t\t\t[ -n \"$lci\" ] && append bss_conf \"lci=$lci\" \"$N\"\n\t\t\t[ -n \"$civic\" ] && append bss_conf \"civic=$civic\" \"$N\"\n\t\t}\n\tfi\n\n\tif [ \"$wpa\" -ge \"1\" ]; then\n\t\tjson_get_vars ieee80211r\n\t\tset_default ieee80211r 0\n\n\t\tif [ \"$ieee80211r\" -gt \"0\" ]; then\n\t\t\tjson_get_vars mobility_domain ft_psk_generate_local ft_over_ds reassociation_deadline\n\n\t\t\tset_default mobility_domain \"$(echo \"$ssid\" | md5sum | head -c 4)\"\n\t\t\tset_default ft_over_ds 1\n\t\t\tset_default reassociation_deadline 1000\n\n\t\t\tcase \"$auth_type\" in\n\t\t\t\tpsk|sae|psk-sae)\n\t\t\t\t\tset_default ft_psk_generate_local 1\n\t\t\t\t;;\n\t\t\t\t*)\n\t\t\t\t\tset_default ft_psk_generate_local 0\n\t\t\t\t;;\n\t\t\tesac\n\n\t\t\t[ -n \"$network_ifname\" ] && append bss_conf \"ft_iface=$network_ifname\" \"$N\"\n\t\t\tappend bss_conf \"mobility_domain=$mobility_domain\" \"$N\"\n\t\t\tappend bss_conf \"ft_psk_generate_local=$ft_psk_generate_local\" \"$N\"\n\t\t\tappend bss_conf \"ft_over_ds=$ft_over_ds\" \"$N\"\n\t\t\tappend bss_conf \"reassociation_deadline=$reassociation_deadline\" \"$N\"\n\t\t\t[ -n \"$nasid\" ] || append bss_conf \"nas_identifier=${macaddr//\\:}\" \"$N\"\n\n\t\t\tif [ \"$ft_psk_generate_local\" -eq \"0\" ]; then\n\t\t\t\tjson_get_vars r0_key_lifetime r1_key_holder pmk_r1_push\n\t\t\t\tjson_get_values r0kh r0kh\n\t\t\t\tjson_get_values r1kh r1kh\n\n\t\t\t\tset_default r0_key_lifetime 10000\n\t\t\t\tset_default pmk_r1_push 0\n\n\t\t\t\t[ -n \"$r0kh\" -a -n \"$r1kh\" ] || {\n\t\t\t\t\tft_key=`echo -n \"$mobility_domain/${auth_secret:-${key}}\" | md5sum | awk '{print $1}'`\n\n\t\t\t\t\tset_default r0kh \"ff:ff:ff:ff:ff:ff,*,$ft_key\"\n\t\t\t\t\tset_default r1kh \"00:00:00:00:00:00,00:00:00:00:00:00,$ft_key\"\n\t\t\t\t}\n\n\t\t\t\t[ -n \"$r1_key_holder\" ] && append bss_conf \"r1_key_holder=$r1_key_holder\" \"$N\"\n\t\t\t\tappend bss_conf \"r0_key_lifetime=$r0_key_lifetime\" \"$N\"\n\t\t\t\tappend bss_conf \"pmk_r1_push=$pmk_r1_push\" \"$N\"\n\n\t\t\t\tfor kh in $r0kh; do\n\t\t\t\t\tappend bss_conf \"r0kh=${kh//,/ }\" \"$N\"\n\t\t\t\tdone\n\t\t\t\tfor kh in $r1kh; do\n\t\t\t\t\tappend bss_conf \"r1kh=${kh//,/ }\" \"$N\"\n\t\t\t\tdone\n\t\t\tfi\n\t\tfi\n\t\tif [ \"$fils\" -gt 0 ]; then\n\t\t\tjson_get_vars fils_realm\n\t\t\tset_default fils_realm \"$(echo \"$ssid\" | md5sum | head -c 8)\"\n\t\tfi\n\n\t\tappend bss_conf \"wpa_disable_eapol_key_retries=$wpa_disable_eapol_key_retries\" \"$N\"\n\n\t\thostapd_append_wpa_key_mgmt\n\t\t[ -n \"$wpa_key_mgmt\" ] && append bss_conf \"wpa_key_mgmt=$wpa_key_mgmt\" \"$N\"\n\tfi\n\n\tif [ \"$wpa\" -ge \"2\" ]; then\n\t\tif [ -n \"$network_bridge\" -a \"$rsn_preauth\" = 1 ]; then\n\t\t\tset_default auth_cache 1\n\t\t\tappend bss_conf \"rsn_preauth=1\" \"$N\"\n\t\t\tappend bss_conf \"rsn_preauth_interfaces=$network_bridge\" \"$N\"\n\t\telse\n\t\t\tcase \"$auth_type\" in\n\t\t\tsae|psk-sae|owe)\n\t\t\t\tset_default auth_cache 1\n\t\t\t;;\n\t\t\t*)\n\t\t\t\tset_default auth_cache 0\n\t\t\t;;\n\t\t\tesac\n\t\tfi\n\n\t\tappend bss_conf \"okc=$auth_cache\" \"$N\"\n\t\t[ \"$auth_cache\" = 0 -a \"$fils\" = 0 ] && append bss_conf \"disable_pmksa_caching=1\" \"$N\"\n\n\t\t# RSN -> allow management frame protection\n\t\tcase \"$ieee80211w\" in\n\t\t\t[012])\n\t\t\t\tjson_get_vars ieee80211w_mgmt_cipher ieee80211w_max_timeout ieee80211w_retry_timeout\n\t\t\t\tappend bss_conf \"ieee80211w=$ieee80211w\" \"$N\"\n\t\t\t\t[ \"$ieee80211w\" -gt \"0\" ] && {\n\t\t\t\t\tappend bss_conf \"group_mgmt_cipher=${ieee80211w_mgmt_cipher:-AES-128-CMAC}\" \"$N\"\n\t\t\t\t\t[ -n \"$ieee80211w_max_timeout\" ] && \\\n\t\t\t\t\t\tappend bss_conf \"assoc_sa_query_max_timeout=$ieee80211w_max_timeout\" \"$N\"\n\t\t\t\t\t[ -n \"$ieee80211w_retry_timeout\" ] && \\\n\t\t\t\t\t\tappend bss_conf \"assoc_sa_query_retry_timeout=$ieee80211w_retry_timeout\" \"$N\"\n\t\t\t\t}\n\t\t\t;;\n\t\tesac\n\tfi\n\n\t_macfile=\"/var/run/hostapd-$ifname.maclist\"\n\tcase \"$macfilter\" in\n\t\tallow)\n\t\t\tappend bss_conf \"macaddr_acl=1\" \"$N\"\n\t\t\tappend bss_conf \"accept_mac_file=$_macfile\" \"$N\"\n\t\t\t# accept_mac_file can be used to set MAC to VLAN ID mapping\n\t\t\tvlan_possible=1\n\t\t;;\n\t\tdeny)\n\t\t\tappend bss_conf \"macaddr_acl=0\" \"$N\"\n\t\t\tappend bss_conf \"deny_mac_file=$_macfile\" \"$N\"\n\t\t;;\n\t\t*)\n\t\t\t_macfile=\"\"\n\t\t;;\n\tesac\n\n\t[ -n \"$_macfile\" ] && {\n\t\tjson_get_vars macfile\n\t\tjson_get_values maclist maclist\n\n\t\trm -f \"$_macfile\"\n\t\t(\n\t\t\tfor mac in $maclist; do\n\t\t\t\techo \"$mac\"\n\t\t\tdone\n\t\t\t[ -n \"$macfile\" -a -f \"$macfile\" ] && cat \"$macfile\"\n\t\t) > \"$_macfile\"\n\t}\n\n\t[ -n \"$vlan_possible\" -a -n \"$dynamic_vlan\" ] && {\n\t\tjson_get_vars vlan_naming vlan_tagged_interface vlan_bridge vlan_file vlan_no_bridge\n\t\tset_default vlan_naming 1\n\t\t[ -z \"$vlan_file\" ] && set_default vlan_file /var/run/hostapd-$ifname.vlan\n\t\tappend bss_conf \"dynamic_vlan=$dynamic_vlan\" \"$N\"\n\t\tappend bss_conf \"vlan_naming=$vlan_naming\" \"$N\"\n\t\tif [ -n \"$vlan_bridge\" ]; then\n\t\t\tappend bss_conf \"vlan_bridge=$vlan_bridge\" \"$N\"\n\t\telse\n\t\t\tset_default vlan_no_bridge 1\n\t\tfi\n\t\tappend bss_conf \"vlan_no_bridge=$vlan_no_bridge\" \"$N\"\n\t\t[ -n \"$vlan_tagged_interface\" ] && \\\n\t\t\tappend bss_conf \"vlan_tagged_interface=$vlan_tagged_interface\" \"$N\"\n\t\t[ -n \"$vlan_file\" ] && {\n\t\t\t[ -e \"$vlan_file\" ] || touch \"$vlan_file\"\n\t\t\tappend bss_conf \"vlan_file=$vlan_file\" \"$N\"\n\t\t}\n\t}\n\n\tjson_get_vars iw_enabled iw_internet iw_asra iw_esr iw_uesa iw_access_network_type\n\tjson_get_vars iw_hessid iw_venue_group iw_venue_type iw_network_auth_type\n\tjson_get_vars iw_roaming_consortium iw_domain_name iw_anqp_3gpp_cell_net iw_nai_realm\n\tjson_get_vars iw_anqp_elem iw_qos_map_set iw_ipaddr_type_availability iw_gas_address3\n\tjson_get_vars iw_venue_name iw_venue_url\n\n\tset_default iw_enabled 0\n\tif [ \"$iw_enabled\" = \"1\" ]; then\n\t\tappend bss_conf \"interworking=1\" \"$N\"\n\t\tset_default iw_internet 1\n\t\tset_default iw_asra 0\n\t\tset_default iw_esr 0\n\t\tset_default iw_uesa 0\n\n\t\tappend bss_conf \"internet=$iw_internet\" \"$N\"\n\t\tappend bss_conf \"asra=$iw_asra\" \"$N\"\n\t\tappend bss_conf \"esr=$iw_esr\" \"$N\"\n\t\tappend bss_conf \"uesa=$iw_uesa\" \"$N\"\n\n\t\t[ -n \"$iw_access_network_type\" ] && \\\n\t\t\tappend bss_conf \"access_network_type=$iw_access_network_type\" \"$N\"\n\t\t[ -n \"$iw_hessid\" ] && append bss_conf \"hessid=$iw_hessid\" \"$N\"\n\t\t[ -n \"$iw_venue_group\" ] && \\\n\t\t\tappend bss_conf \"venue_group=$iw_venue_group\" \"$N\"\n\t\t[ -n \"$iw_venue_type\" ] && append bss_conf \"venue_type=$iw_venue_type\" \"$N\"\n\t\t[ -n \"$iw_network_auth_type\" ] && \\\n\t\t\tappend bss_conf \"network_auth_type=$iw_network_auth_type\" \"$N\"\n\t\t[ -n \"$iw_gas_address3\" ] && append bss_conf \"gas_address3=$iw_gas_address3\" \"$N\"\n\n\t\tjson_for_each_item append_iw_roaming_consortium iw_roaming_consortium\n\t\tjson_for_each_item append_iw_anqp_elem iw_anqp_elem\n\t\tjson_for_each_item append_iw_nai_realm iw_nai_realm\n\t\tjson_for_each_item append_iw_venue_name iw_venue_name\n\t\tjson_for_each_item append_iw_venue_url iw_venue_url\n\n\t\tiw_domain_name_conf=\n\t\tjson_for_each_item append_iw_domain_name iw_domain_name\n\t\t[ -n \"$iw_domain_name_conf\" ] && \\\n\t\t\tappend bss_conf \"domain_name=$iw_domain_name_conf\" \"$N\"\n\n\t\tiw_anqp_3gpp_cell_net_conf=\n\t\tjson_for_each_item append_iw_anqp_3gpp_cell_net iw_anqp_3gpp_cell_net\n\t\t[ -n \"$iw_anqp_3gpp_cell_net_conf\" ] && \\\n\t\t\tappend bss_conf \"anqp_3gpp_cell_net=$iw_anqp_3gpp_cell_net_conf\" \"$N\"\n\tfi\n\n\tset_default iw_qos_map_set 0,0,2,16,1,1,255,255,18,22,24,38,40,40,44,46,48,56\n\tcase \"$iw_qos_map_set\" in\n\t\t*,*);;\n\t\t*) iw_qos_map_set=\"\";;\n\tesac\n\t[ -n \"$iw_qos_map_set\" ] && append bss_conf \"qos_map_set=$iw_qos_map_set\" \"$N\"\n\n\tlocal hs20 disable_dgaf osen anqp_domain_id hs20_deauth_req_timeout \\\n\t\tosu_ssid hs20_wan_metrics hs20_operating_class hs20_t_c_filename hs20_t_c_timestamp \\\n\t\ths20_t_c_server_url\n\tjson_get_vars hs20 disable_dgaf osen anqp_domain_id hs20_deauth_req_timeout \\\n\t\tosu_ssid hs20_wan_metrics hs20_operating_class hs20_t_c_filename hs20_t_c_timestamp \\\n\t\ths20_t_c_server_url\n\n\tset_default hs20 0\n\tset_default disable_dgaf $hs20\n\tset_default osen 0\n\tset_default anqp_domain_id 0\n\tset_default hs20_deauth_req_timeout 60\n\tif [ \"$hs20\" = \"1\" ]; then\n\t\tappend bss_conf \"hs20=1\" \"$N\"\n\t\tappend_hs20_icons\n\t\tappend bss_conf \"disable_dgaf=$disable_dgaf\" \"$N\"\n\t\tappend bss_conf \"osen=$osen\" \"$N\"\n\t\tappend bss_conf \"anqp_domain_id=$anqp_domain_id\" \"$N\"\n\t\tappend bss_conf \"hs20_deauth_req_timeout=$hs20_deauth_req_timeout\" \"$N\"\n\t\t[ -n \"$osu_ssid\" ] && append bss_conf \"osu_ssid=$osu_ssid\" \"$N\"\n\t\t[ -n \"$hs20_wan_metrics\" ] && append bss_conf \"hs20_wan_metrics=$hs20_wan_metrics\" \"$N\"\n\t\t[ -n \"$hs20_operating_class\" ] && append bss_conf \"hs20_operating_class=$hs20_operating_class\" \"$N\"\n\t\t[ -n \"$hs20_t_c_filename\" ] && append bss_conf \"hs20_t_c_filename=$hs20_t_c_filename\" \"$N\"\n\t\t[ -n \"$hs20_t_c_timestamp\" ] && append bss_conf \"hs20_t_c_timestamp=$hs20_t_c_timestamp\" \"$N\"\n\t\t[ -n \"$hs20_t_c_server_url\" ] && append bss_conf \"hs20_t_c_server_url=$hs20_t_c_server_url\" \"$N\"\n\t\tjson_for_each_item append_hs20_oper_friendly_name hs20_oper_friendly_name\n\t\tjson_for_each_item append_hs20_conn_capab hs20_conn_capab\n\t\tjson_for_each_item append_osu_provider osu_provider\n\t\tjson_for_each_item append_operator_icon operator_icon\n\tfi\n\n\tif [ \"$eap_server\" = \"1\" ]; then\n\t\tappend bss_conf \"eap_server=1\" \"$N\"\n\t\tappend bss_conf \"eap_server_erp=1\" \"$N\"\n\t\t[ -n \"$eap_user_file\" ] && append bss_conf \"eap_user_file=$eap_user_file\" \"$N\"\n\t\t[ -n \"$ca_cert\" ] && append bss_conf \"ca_cert=$ca_cert\" \"$N\"\n\t\t[ -n \"$server_cert\" ] && append bss_conf \"server_cert=$server_cert\" \"$N\"\n\t\t[ -n \"$private_key\" ] && append bss_conf \"private_key=$private_key\" \"$N\"\n\t\t[ -n \"$private_key_passwd\" ] && append bss_conf \"private_key_passwd=$private_key_passwd\" \"$N\"\n\t\t[ -n \"$server_id\" ] && append bss_conf \"server_id=$server_id\" \"$N\"\n\tfi\n\n\tset_default multicast_to_unicast 0\n\tif [ \"$multicast_to_unicast\" -gt 0 ]; then\n\t\tappend bss_conf \"multicast_to_unicast=$multicast_to_unicast\" \"$N\"\n\tfi\n\tset_default proxy_arp 0\n\tif [ \"$proxy_arp\" -gt 0 ]; then\n\t\tappend bss_conf \"proxy_arp=$proxy_arp\" \"$N\"\n\tfi\n\n\tset_default per_sta_vif 0\n\tif [ \"$per_sta_vif\" -gt 0 ]; then\n\t\tappend bss_conf \"per_sta_vif=$per_sta_vif\" \"$N\"\n\tfi\n\n\tjson_get_values opts hostapd_bss_options\n\tfor val in $opts; do\n\t\tappend bss_conf \"$val\" \"$N\"\n\tdone\n\n\tbss_md5sum=$(echo $bss_conf | md5sum | cut -d\" \" -f1)\n\tappend bss_conf \"config_id=$bss_md5sum\" \"$N\"\n\n\tappend \"$var\" \"$bss_conf\" \"$N\"\n\treturn 0\n}\n\nhostapd_set_log_options() {\n\tlocal var=\"$1\"\n\n\tlocal log_level log_80211 log_8021x log_radius log_wpa log_driver log_iapp log_mlme\n\tjson_get_vars log_level log_80211 log_8021x log_radius log_wpa log_driver log_iapp log_mlme\n\n\tset_default log_level 2\n\tset_default log_80211  1\n\tset_default log_8021x  1\n\tset_default log_radius 1\n\tset_default log_wpa    1\n\tset_default log_driver 1\n\tset_default log_iapp   1\n\tset_default log_mlme   1\n\n\tlocal log_mask=$(( \\\n\t\t($log_80211  << 0) | \\\n\t\t($log_8021x  << 1) | \\\n\t\t($log_radius << 2) | \\\n\t\t($log_wpa    << 3) | \\\n\t\t($log_driver << 4) | \\\n\t\t($log_iapp   << 5) | \\\n\t\t($log_mlme   << 6)   \\\n\t))\n\n\tappend \"$var\" \"logger_syslog=$log_mask\" \"$N\"\n\tappend \"$var\" \"logger_syslog_level=$log_level\" \"$N\"\n\tappend \"$var\" \"logger_stdout=$log_mask\" \"$N\"\n\tappend \"$var\" \"logger_stdout_level=$log_level\" \"$N\"\n\n\treturn 0\n}\n\n_wpa_supplicant_common() {\n\tlocal ifname=\"$1\"\n\n\t_rpath=\"/var/run/wpa_supplicant\"\n\t_config=\"${_rpath}-$ifname.conf\"\n}\n\nwpa_supplicant_teardown_interface() {\n\t_wpa_supplicant_common \"$1\"\n\trm -rf \"$_rpath/$1\" \"$_config\"\n}\n\nwpa_supplicant_prepare_interface() {\n\tlocal ifname=\"$1\"\n\t_w_driver=\"$2\"\n\n\t_wpa_supplicant_common \"$1\"\n\n\tjson_get_vars mode wds multi_ap\n\n\t[ -n \"$network_bridge\" ] && {\n\t\tfail=\n\t\tcase \"$mode\" in\n\t\t\tadhoc)\n\t\t\t\tfail=1\n\t\t\t;;\n\t\t\tsta)\n\t\t\t\t[ \"$wds\" = 1 -o \"$multi_ap\" = 1 ] || fail=1\n\t\t\t;;\n\t\tesac\n\n\t\t[ -n \"$fail\" ] && {\n\t\t\twireless_setup_vif_failed BRIDGE_NOT_ALLOWED\n\t\t\treturn 1\n\t\t}\n\t}\n\n\tlocal ap_scan=\n\n\t_w_mode=\"$mode\"\n\n\t[ \"$mode\" = adhoc ] && {\n\t\tap_scan=\"ap_scan=2\"\n\t}\n\n\tlocal country_str=\n\t[ -n \"$country\" ] && {\n\t\tcountry_str=\"country=$country\"\n\t}\n\n\tmultiap_flag_file=\"${_config}.is_multiap\"\n\tif [ \"$multi_ap\" = \"1\" ]; then\n\t\ttouch \"$multiap_flag_file\"\n\telse\n\t\t[ -e \"$multiap_flag_file\" ] && rm \"$multiap_flag_file\"\n\tfi\n\twpa_supplicant_teardown_interface \"$ifname\"\n\tcat > \"$_config\" <<EOF\n${scan_list:+freq_list=$scan_list}\n$ap_scan\n$country_str\nEOF\n\treturn 0\n}\n\nwpa_supplicant_set_fixed_freq() {\n\tlocal freq=\"$1\"\n\tlocal htmode=\"$2\"\n\n\tappend network_data \"fixed_freq=1\" \"$N$T\"\n\tappend network_data \"frequency=$freq\" \"$N$T\"\n\tcase \"$htmode\" in\n\t\tNOHT) append network_data \"disable_ht=1\" \"$N$T\";;\n\t\tHE20|HT20|VHT20) append network_data \"disable_ht40=1\" \"$N$T\";;\n\t\tHT40*|VHT40|VHT80|VHT160|HE40|HE80|HE160) append network_data \"ht40=1\" \"$N$T\";;\n\tesac\n\tcase \"$htmode\" in\n\t\tVHT*) append network_data \"vht=1\" \"$N$T\";;\n\tesac\n\tcase \"$htmode\" in\n\t\tHE80|VHT80) append network_data \"max_oper_chwidth=1\" \"$N$T\";;\n\t\tHE160|VHT160) append network_data \"max_oper_chwidth=2\" \"$N$T\";;\n\t\tHE20|HE40|VHT20|VHT40) append network_data \"max_oper_chwidth=0\" \"$N$T\";;\n\t\t*) append network_data \"disable_vht=1\" \"$N$T\";;\n\tesac\n}\n\nwpa_supplicant_add_network() {\n\tlocal ifname=\"$1\"\n\tlocal freq=\"$2\"\n\tlocal htmode=\"$3\"\n\tlocal noscan=\"$4\"\n\n\t_wpa_supplicant_common \"$1\"\n\twireless_vif_parse_encryption\n\n\tjson_get_vars \\\n\t\tssid bssid key \\\n\t\tbasic_rate mcast_rate \\\n\t\tieee80211w ieee80211r fils \\\n\t\tmulti_ap \\\n\t\tdefault_disabled\n\n\tcase \"$auth_type\" in\n\t\tsae|owe|eap192|eap-eap192)\n\t\t\tset_default ieee80211w 2\n\t\t;;\n\t\tpsk-sae)\n\t\t\tset_default ieee80211w 1\n\t\t;;\n\tesac\n\n\tset_default ieee80211r 0\n\tset_default multi_ap 0\n\tset_default default_disabled 0\n\n\tlocal key_mgmt='NONE'\n\tlocal network_data=\n\tlocal T=\"\t\"\n\n\tlocal scan_ssid=\"scan_ssid=1\"\n\tlocal freq wpa_key_mgmt\n\n\t[ \"$_w_mode\" = \"adhoc\" ] && {\n\t\tappend network_data \"mode=1\" \"$N$T\"\n\t\t[ -n \"$freq\" ] && wpa_supplicant_set_fixed_freq \"$freq\" \"$htmode\"\n\t\t[ \"$noscan\" = \"1\" ] && append network_data \"noscan=1\" \"$N$T\"\n\n\t\tscan_ssid=\"scan_ssid=0\"\n\n\t\t[ \"$_w_driver\" = \"nl80211\" ] ||\tappend wpa_key_mgmt \"WPA-NONE\"\n\t}\n\n\t[ \"$_w_mode\" = \"mesh\" ] && {\n\t\tjson_get_vars mesh_id mesh_fwding mesh_rssi_threshold\n\t\t[ -n \"$mesh_id\" ] && ssid=\"${mesh_id}\"\n\n\t\tappend network_data \"mode=5\" \"$N$T\"\n\t\t[ -n \"$mesh_fwding\" ] && append network_data \"mesh_fwding=${mesh_fwding}\" \"$N$T\"\n\t\t[ -n \"$mesh_rssi_threshold\" ] && append network_data \"mesh_rssi_threshold=${mesh_rssi_threshold}\" \"$N$T\"\n\t\t[ -n \"$freq\" ] && wpa_supplicant_set_fixed_freq \"$freq\" \"$htmode\"\n\t\t[ \"$noscan\" = \"1\" ] && append network_data \"noscan=1\" \"$N$T\"\n\t\tappend wpa_key_mgmt \"SAE\"\n\t\tscan_ssid=\"\"\n\t}\n\n\t[ \"$_w_mode\" = \"sta\" ] && {\n\t\t[ \"$multi_ap\" = 1 ] && append network_data \"multi_ap_backhaul_sta=1\" \"$N$T\"\n\t\t[ \"$default_disabled\" = 1 ] && append network_data \"disabled=1\" \"$N$T\"\n\t}\n\n\tcase \"$auth_type\" in\n\t\tnone) ;;\n\t\towe)\n\t\t\thostapd_append_wpa_key_mgmt\n\t\t\tkey_mgmt=\"$wpa_key_mgmt\"\n\t\t;;\n\t\twep)\n\t\t\tlocal wep_keyidx=0\n\t\t\thostapd_append_wep_key network_data\n\t\t\tappend network_data \"wep_tx_keyidx=$wep_keyidx\" \"$N$T\"\n\t\t;;\n\t\twps)\n\t\t\tkey_mgmt='WPS'\n\t\t;;\n\t\tpsk|sae|psk-sae)\n\t\t\tlocal passphrase\n\n\t\t\tif [ \"$_w_mode\" != \"mesh\" ]; then\n\t\t\t\thostapd_append_wpa_key_mgmt\n\t\t\tfi\n\n\t\t\tkey_mgmt=\"$wpa_key_mgmt\"\n\n\t\t\tif [ ${#key} -eq 64 ]; then\n\t\t\t\tpassphrase=\"psk=${key}\"\n\t\t\telse\n\t\t\t\tif [ \"$_w_mode\" = \"mesh\" ]; then\n\t\t\t\t\tpassphrase=\"sae_password=\\\"${key}\\\"\"\n\t\t\t\telse\n\t\t\t\t\tpassphrase=\"psk=\\\"${key}\\\"\"\n\t\t\t\tfi\n\t\t\tfi\n\t\t\tappend network_data \"$passphrase\" \"$N$T\"\n\t\t;;\n\t\teap|eap192|eap-eap192)\n\t\t\thostapd_append_wpa_key_mgmt\n\t\t\tkey_mgmt=\"$wpa_key_mgmt\"\n\n\t\t\tjson_get_vars eap_type identity anonymous_identity ca_cert ca_cert_usesystem\n\n\t\t\t[ \"$fils\" -gt 0 ] && append network_data \"erp=1\" \"$N$T\"\n\t\t\tif [ \"$ca_cert_usesystem\" -eq \"1\" -a -f \"/etc/ssl/certs/ca-certificates.crt\" ]; then\n\t\t\t\tappend network_data \"ca_cert=\\\"/etc/ssl/certs/ca-certificates.crt\\\"\" \"$N$T\"\n\t\t\telse\n\t\t\t\t[ -n \"$ca_cert\" ] && append network_data \"ca_cert=\\\"$ca_cert\\\"\" \"$N$T\"\n\t\t\tfi\n\t\t\t[ -n \"$identity\" ] && append network_data \"identity=\\\"$identity\\\"\" \"$N$T\"\n\t\t\t[ -n \"$anonymous_identity\" ] && append network_data \"anonymous_identity=\\\"$anonymous_identity\\\"\" \"$N$T\"\n\t\t\tcase \"$eap_type\" in\n\t\t\t\ttls)\n\t\t\t\t\tjson_get_vars client_cert priv_key priv_key_pwd\n\t\t\t\t\tappend network_data \"client_cert=\\\"$client_cert\\\"\" \"$N$T\"\n\t\t\t\t\tappend network_data \"private_key=\\\"$priv_key\\\"\" \"$N$T\"\n\t\t\t\t\tappend network_data \"private_key_passwd=\\\"$priv_key_pwd\\\"\" \"$N$T\"\n\n\t\t\t\t\tjson_get_vars subject_match\n\t\t\t\t\t[ -n \"$subject_match\" ] && append network_data \"subject_match=\\\"$subject_match\\\"\" \"$N$T\"\n\n\t\t\t\t\tjson_get_values altsubject_match altsubject_match\n\t\t\t\t\tif [ -n \"$altsubject_match\" ]; then\n\t\t\t\t\t\tlocal list=\n\t\t\t\t\t\tfor x in $altsubject_match; do\n\t\t\t\t\t\t\tappend list \"$x\" \";\"\n\t\t\t\t\t\tdone\n\t\t\t\t\t\tappend network_data \"altsubject_match=\\\"$list\\\"\" \"$N$T\"\n\t\t\t\t\tfi\n\n\t\t\t\t\tjson_get_values domain_match domain_match\n\t\t\t\t\tif [ -n \"$domain_match\" ]; then\n\t\t\t\t\t\tlocal list=\n\t\t\t\t\t\tfor x in $domain_match; do\n\t\t\t\t\t\t\tappend list \"$x\" \";\"\n\t\t\t\t\t\tdone\n\t\t\t\t\t\tappend network_data \"domain_match=\\\"$list\\\"\" \"$N$T\"\n\t\t\t\t\tfi\n\n\t\t\t\t\tjson_get_values domain_suffix_match domain_suffix_match\n\t\t\t\t\tif [ -n \"$domain_suffix_match\" ]; then\n\t\t\t\t\t\tlocal list=\n\t\t\t\t\t\tfor x in $domain_suffix_match; do\n\t\t\t\t\t\t\tappend list \"$x\" \";\"\n\t\t\t\t\t\tdone\n\t\t\t\t\t\tappend network_data \"domain_suffix_match=\\\"$list\\\"\" \"$N$T\"\n\t\t\t\t\tfi\n\t\t\t\t;;\n\t\t\t\tfast|peap|ttls)\n\t\t\t\t\tjson_get_vars auth password ca_cert2 ca_cert2_usesystem client_cert2 priv_key2 priv_key2_pwd\n\t\t\t\t\tset_default auth MSCHAPV2\n\n\t\t\t\t\tif [ \"$auth\" = \"EAP-TLS\" ]; then\n\t\t\t\t\t\tif [ \"$ca_cert2_usesystem\" -eq \"1\" -a -f \"/etc/ssl/certs/ca-certificates.crt\" ]; then\n\t\t\t\t\t\t\tappend network_data \"ca_cert2=\\\"/etc/ssl/certs/ca-certificates.crt\\\"\" \"$N$T\"\n\t\t\t\t\t\telse\n\t\t\t\t\t\t\t[ -n \"$ca_cert2\" ] && append network_data \"ca_cert2=\\\"$ca_cert2\\\"\" \"$N$T\"\n\t\t\t\t\t\tfi\n\t\t\t\t\t\tappend network_data \"client_cert2=\\\"$client_cert2\\\"\" \"$N$T\"\n\t\t\t\t\t\tappend network_data \"private_key2=\\\"$priv_key2\\\"\" \"$N$T\"\n\t\t\t\t\t\tappend network_data \"private_key2_passwd=\\\"$priv_key2_pwd\\\"\" \"$N$T\"\n\t\t\t\t\telse\n\t\t\t\t\t\tappend network_data \"password=\\\"$password\\\"\" \"$N$T\"\n\t\t\t\t\tfi\n\n\t\t\t\t\tjson_get_vars subject_match\n\t\t\t\t\t[ -n \"$subject_match\" ] && append network_data \"subject_match=\\\"$subject_match\\\"\" \"$N$T\"\n\n\t\t\t\t\tjson_get_values altsubject_match altsubject_match\n\t\t\t\t\tif [ -n \"$altsubject_match\" ]; then\n\t\t\t\t\t\tlocal list=\n\t\t\t\t\t\tfor x in $altsubject_match; do\n\t\t\t\t\t\t\tappend list \"$x\" \";\"\n\t\t\t\t\t\tdone\n\t\t\t\t\t\tappend network_data \"altsubject_match=\\\"$list\\\"\" \"$N$T\"\n\t\t\t\t\tfi\n\n\t\t\t\t\tjson_get_values domain_match domain_match\n\t\t\t\t\tif [ -n \"$domain_match\" ]; then\n\t\t\t\t\t\tlocal list=\n\t\t\t\t\t\tfor x in $domain_match; do\n\t\t\t\t\t\t\tappend list \"$x\" \";\"\n\t\t\t\t\t\tdone\n\t\t\t\t\t\tappend network_data \"domain_match=\\\"$list\\\"\" \"$N$T\"\n\t\t\t\t\tfi\n\n\t\t\t\t\tjson_get_values domain_suffix_match domain_suffix_match\n\t\t\t\t\tif [ -n \"$domain_suffix_match\" ]; then\n\t\t\t\t\t\tlocal list=\n\t\t\t\t\t\tfor x in $domain_suffix_match; do\n\t\t\t\t\t\t\tappend list \"$x\" \";\"\n\t\t\t\t\t\tdone\n\t\t\t\t\t\tappend network_data \"domain_suffix_match=\\\"$list\\\"\" \"$N$T\"\n\t\t\t\t\tfi\n\n\t\t\t\t\tphase2proto=\"auth=\"\n\t\t\t\t\tcase \"$auth\" in\n\t\t\t\t\t\t\"auth\"*)\n\t\t\t\t\t\t\tphase2proto=\"\"\n\t\t\t\t\t\t;;\n\t\t\t\t\t\t\"EAP-\"*)\n\t\t\t\t\t\t\tauth=\"$(echo $auth | cut -b 5- )\"\n\t\t\t\t\t\t\t[ \"$eap_type\" = \"ttls\" ] &&\n\t\t\t\t\t\t\t\tphase2proto=\"autheap=\"\n\t\t\t\t\t\t\tjson_get_vars subject_match2\n\t\t\t\t\t\t\t[ -n \"$subject_match2\" ] && append network_data \"subject_match2=\\\"$subject_match2\\\"\" \"$N$T\"\n\n\t\t\t\t\t\t\tjson_get_values altsubject_match2 altsubject_match2\n\t\t\t\t\t\t\tif [ -n \"$altsubject_match2\" ]; then\n\t\t\t\t\t\t\t\tlocal list=\n\t\t\t\t\t\t\t\tfor x in $altsubject_match2; do\n\t\t\t\t\t\t\t\t\tappend list \"$x\" \";\"\n\t\t\t\t\t\t\t\tdone\n\t\t\t\t\t\t\t\tappend network_data \"altsubject_match2=\\\"$list\\\"\" \"$N$T\"\n\t\t\t\t\t\t\tfi\n\n\t\t\t\t\t\t\tjson_get_values domain_match2 domain_match2\n\t\t\t\t\t\t\tif [ -n \"$domain_match2\" ]; then\n\t\t\t\t\t\t\t\tlocal list=\n\t\t\t\t\t\t\t\tfor x in $domain_match2; do\n\t\t\t\t\t\t\t\t\tappend list \"$x\" \";\"\n\t\t\t\t\t\t\t\tdone\n\t\t\t\t\t\t\t\tappend network_data \"domain_match2=\\\"$list\\\"\" \"$N$T\"\n\t\t\t\t\t\t\tfi\n\n\t\t\t\t\t\t\tjson_get_values domain_suffix_match2 domain_suffix_match2\n\t\t\t\t\t\t\tif [ -n \"$domain_suffix_match2\" ]; then\n\t\t\t\t\t\t\t\tlocal list=\n\t\t\t\t\t\t\t\tfor x in $domain_suffix_match2; do\n\t\t\t\t\t\t\t\t\tappend list \"$x\" \";\"\n\t\t\t\t\t\t\t\tdone\n\t\t\t\t\t\t\t\tappend network_data \"domain_suffix_match2=\\\"$list\\\"\" \"$N$T\"\n\t\t\t\t\t\t\tfi\n\t\t\t\t\t\t;;\n\t\t\t\t\tesac\n\t\t\t\t\tappend network_data \"phase2=\\\"$phase2proto$auth\\\"\" \"$N$T\"\n\t\t\t\t;;\n\t\t\tesac\n\t\t\tappend network_data \"eap=$(echo $eap_type | tr 'a-z' 'A-Z')\" \"$N$T\"\n\t\t;;\n\tesac\n\n\t[ \"$wpa_cipher\" = GCMP ] && {\n\t\tappend network_data \"pairwise=GCMP\" \"$N$T\"\n\t\tappend network_data \"group=GCMP\" \"$N$T\"\n\t}\n\n\t[ \"$mode\" = mesh ] || {\n\t\tcase \"$wpa\" in\n\t\t\t1)\n\t\t\t\tappend network_data \"proto=WPA\" \"$N$T\"\n\t\t\t;;\n\t\t\t2)\n\t\t\t\tappend network_data \"proto=RSN\" \"$N$T\"\n\t\t\t;;\n\t\tesac\n\n\t\tcase \"$ieee80211w\" in\n\t\t\t[012])\n\t\t\t\t[ \"$wpa\" -ge 2 ] && append network_data \"ieee80211w=$ieee80211w\" \"$N$T\"\n\t\t\t;;\n\t\tesac\n\t}\n\t[ -n \"$bssid\" ] && append network_data \"bssid=$bssid\" \"$N$T\"\n\t[ -n \"$beacon_int\" ] && append network_data \"beacon_int=$beacon_int\" \"$N$T\"\n\n\tlocal bssid_blacklist bssid_whitelist\n\tjson_get_values bssid_blacklist bssid_blacklist\n\tjson_get_values bssid_whitelist bssid_whitelist\n\n\t[ -n \"$bssid_blacklist\" ] && append network_data \"bssid_blacklist=$bssid_blacklist\" \"$N$T\"\n\t[ -n \"$bssid_whitelist\" ] && append network_data \"bssid_whitelist=$bssid_whitelist\" \"$N$T\"\n\n\t[ -n \"$basic_rate\" ] && {\n\t\tlocal br rate_list=\n\t\tfor br in $basic_rate; do\n\t\t\twpa_supplicant_add_rate rate_list \"$br\"\n\t\tdone\n\t\t[ -n \"$rate_list\" ] && append network_data \"rates=$rate_list\" \"$N$T\"\n\t}\n\n\t[ -n \"$mcast_rate\" ] && {\n\t\tlocal mc_rate=\n\t\twpa_supplicant_add_rate mc_rate \"$mcast_rate\"\n\t\tappend network_data \"mcast_rate=$mc_rate\" \"$N$T\"\n\t}\n\n\tif [ \"$key_mgmt\" = \"WPS\" ]; then\n\t\techo \"wps_cred_processing=1\" >> \"$_config\"\n\telse\n\t\tcat >> \"$_config\" <<EOF\nnetwork={\n\t$scan_ssid\n\tssid=\"$ssid\"\n\tkey_mgmt=$key_mgmt\n\t$network_data\n}\nEOF\n\tfi\n\treturn 0\n}\n\nwpa_supplicant_run() {\n\tlocal ifname=\"$1\"\n\tlocal hostapd_ctrl=\"$2\"\n\n\t_wpa_supplicant_common \"$ifname\"\n\n\tubus wait_for wpa_supplicant\n\tlocal supplicant_res=\"$(ubus call wpa_supplicant config_add \"{ \\\n\t\t\\\"driver\\\": \\\"${_w_driver:-wext}\\\", \\\"ctrl\\\": \\\"$_rpath\\\", \\\n\t\t\\\"iface\\\": \\\"$ifname\\\", \\\"config\\\": \\\"$_config\\\" \\\n\t\t${network_bridge:+, \\\"bridge\\\": \\\"$network_bridge\\\"} \\\n\t\t${hostapd_ctrl:+, \\\"hostapd_ctrl\\\": \\\"$hostapd_ctrl\\\"} \\\n\t\t}\")\"\n\n\tret=\"$?\"\n\n\t[ \"$ret\" != 0 -o -z \"$supplicant_res\" ] && wireless_setup_vif_failed WPA_SUPPLICANT_FAILED\n\n\twireless_add_process \"$(jsonfilter -s \"$supplicant_res\" -l 1 -e @.pid)\" \"/usr/sbin/wpa_supplicant\" 1 1\n\n\treturn $ret\n}\n\nhostapd_common_cleanup() {\n\tkillall meshd-nl80211\n}\n"
  },
  {
    "path": "package/network/services/hostapd/files/multicall.c",
    "content": "#include <stdio.h>\n#include <string.h>\n#include <stdbool.h>\n\nextern int hostapd_main(int argc, char **argv);\nextern int wpa_supplicant_main(int argc, char **argv);\n\nint main(int argc, char **argv)\n{\n\tbool restart = false;\n\tconst char *prog = argv[0];\n\nrestart:\n\tif (strstr(argv[0], \"hostapd\"))\n\t\treturn hostapd_main(argc, argv);\n\telse if (strstr(argv[0], \"wpa_supplicant\"))\n\t\treturn wpa_supplicant_main(argc, argv);\n\n\tif (!restart && argc > 1) {\n\t\targv++;\n\t\targc--;\n\t\trestart = true;\n\t\tgoto restart;\n\t}\n\n\tfprintf(stderr, \"Invalid command.\\nUsage: %s wpa_supplicant|hostapd [<arguments>]\\n\", prog);\n\treturn 255;\n}\n"
  },
  {
    "path": "package/network/services/hostapd/files/wpa_supplicant-basic.config",
    "content": "# Example wpa_supplicant build time configuration\n#\n# This file lists the configuration options that are used when building the\n# wpa_supplicant binary. All lines starting with # are ignored. Configuration\n# option lines must be commented out complete, if they are not to be included,\n# i.e., just setting VARIABLE=n is not disabling that variable.\n#\n# This file is included in Makefile, so variables like CFLAGS and LIBS can also\n# be modified from here. In most cases, these lines should use += in order not\n# to override previous values of the variables.\n\n\n# Uncomment following two lines and fix the paths if you have installed OpenSSL\n# or GnuTLS in non-default location\n#CFLAGS += -I/usr/local/openssl/include\n#LIBS += -L/usr/local/openssl/lib\n\n# Some Red Hat versions seem to include kerberos header files from OpenSSL, but\n# the kerberos files are not in the default include path. Following line can be\n# used to fix build issues on such systems (krb5.h not found).\n#CFLAGS += -I/usr/include/kerberos\n\n# Driver interface for generic Linux wireless extensions\n# Note: WEXT is deprecated in the current Linux kernel version and no new\n# functionality is added to it. nl80211-based interface is the new\n# replacement for WEXT and its use allows wpa_supplicant to properly control\n# the driver to improve existing functionality like roaming and to support new\n# functionality.\nCONFIG_DRIVER_WEXT=y\n\n# Driver interface for Linux drivers using the nl80211 kernel interface\nCONFIG_DRIVER_NL80211=y\n\n# QCA vendor extensions to nl80211\n#CONFIG_DRIVER_NL80211_QCA=y\n\n# driver_nl80211.c requires libnl. If you are compiling it yourself\n# you may need to point hostapd to your version of libnl.\n#\n#CFLAGS += -I$<path to libnl include files>\n#LIBS += -L$<path to libnl library files>\n\n# Use libnl v2.0 (or 3.0) libraries.\n#CONFIG_LIBNL20=y\n\n# Use libnl 3.2 libraries (if this is selected, CONFIG_LIBNL20 is ignored)\n#CONFIG_LIBNL32=y\n\n\n# Driver interface for FreeBSD net80211 layer (e.g., Atheros driver)\n#CONFIG_DRIVER_BSD=y\n#CFLAGS += -I/usr/local/include\n#LIBS += -L/usr/local/lib\n#LIBS_p += -L/usr/local/lib\n#LIBS_c += -L/usr/local/lib\n\n# Driver interface for Windows NDIS\n#CONFIG_DRIVER_NDIS=y\n#CFLAGS += -I/usr/include/w32api/ddk\n#LIBS += -L/usr/local/lib\n# For native build using mingw\n#CONFIG_NATIVE_WINDOWS=y\n# Additional directories for cross-compilation on Linux host for mingw target\n#CFLAGS += -I/opt/mingw/mingw32/include/ddk\n#LIBS += -L/opt/mingw/mingw32/lib\n#CC=mingw32-gcc\n# By default, driver_ndis uses WinPcap for low-level operations. This can be\n# replaced with the following option which replaces WinPcap calls with NDISUIO.\n# However, this requires that WZC is disabled (net stop wzcsvc) before starting\n# wpa_supplicant.\n# CONFIG_USE_NDISUIO=y\n\n# Driver interface for wired Ethernet drivers\nCONFIG_DRIVER_WIRED=y\n\n# Driver interface for MACsec capable Qualcomm Atheros drivers\n#CONFIG_DRIVER_MACSEC_QCA=y\n\n# Driver interface for Linux MACsec drivers\n#CONFIG_DRIVER_MACSEC_LINUX=y\n\n# Driver interface for the Broadcom RoboSwitch family\n#CONFIG_DRIVER_ROBOSWITCH=y\n\n# Driver interface for no driver (e.g., WPS ER only)\n#CONFIG_DRIVER_NONE=y\n\n# Solaris libraries\n#LIBS += -lsocket -ldlpi -lnsl\n#LIBS_c += -lsocket\n\n# Enable IEEE 802.1X Supplicant (automatically included if any EAP method or\n# MACsec is included)\n#CONFIG_IEEE8021X_EAPOL=y\n\n# EAP-MD5\n#CONFIG_EAP_MD5=y\n\n# EAP-MSCHAPv2\n#CONFIG_EAP_MSCHAPV2=y\n\n# EAP-TLS\n#CONFIG_EAP_TLS=y\n\n# EAL-PEAP\n#CONFIG_EAP_PEAP=y\n\n# EAP-TTLS\n#CONFIG_EAP_TTLS=y\n\n# EAP-FAST\n#CONFIG_EAP_FAST=y\n\n# EAP-TEAP\n# Note: The current EAP-TEAP implementation is experimental and should not be\n# enabled for production use. The IETF RFC 7170 that defines EAP-TEAP has number\n# of conflicting statements and missing details and the implementation has\n# vendor specific workarounds for those and as such, may not interoperate with\n# any other implementation. This should not be used for anything else than\n# experimentation and interoperability testing until those issues has been\n# resolved.\n#CONFIG_EAP_TEAP=y\n\n# EAP-GTC\n#CONFIG_EAP_GTC=y\n\n# EAP-OTP\n#CONFIG_EAP_OTP=y\n\n# EAP-SIM (enable CONFIG_PCSC, if EAP-SIM is used)\n#CONFIG_EAP_SIM=y\n\n# Enable SIM simulator (Milenage) for EAP-SIM\n#CONFIG_SIM_SIMULATOR=y\n\n# EAP-PSK (experimental; this is _not_ needed for WPA-PSK)\n#CONFIG_EAP_PSK=y\n\n# EAP-pwd (secure authentication using only a password)\n#CONFIG_EAP_PWD=y\n\n# EAP-PAX\n#CONFIG_EAP_PAX=y\n\n# LEAP\n#CONFIG_EAP_LEAP=y\n\n# EAP-AKA (enable CONFIG_PCSC, if EAP-AKA is used)\n#CONFIG_EAP_AKA=y\n\n# EAP-AKA' (enable CONFIG_PCSC, if EAP-AKA' is used).\n# This requires CONFIG_EAP_AKA to be enabled, too.\n#CONFIG_EAP_AKA_PRIME=y\n\n# Enable USIM simulator (Milenage) for EAP-AKA\n#CONFIG_USIM_SIMULATOR=y\n\n# EAP-SAKE\n#CONFIG_EAP_SAKE=y\n\n# EAP-GPSK\n#CONFIG_EAP_GPSK=y\n# Include support for optional SHA256 cipher suite in EAP-GPSK\n#CONFIG_EAP_GPSK_SHA256=y\n\n# EAP-TNC and related Trusted Network Connect support (experimental)\n#CONFIG_EAP_TNC=y\n\n# Wi-Fi Protected Setup (WPS)\n#CONFIG_WPS=y\n# Enable WPS external registrar functionality\n#CONFIG_WPS_ER=y\n# Disable credentials for an open network by default when acting as a WPS\n# registrar.\n#CONFIG_WPS_REG_DISABLE_OPEN=y\n# Enable WPS support with NFC config method\n#CONFIG_WPS_NFC=y\n\n# EAP-IKEv2\n#CONFIG_EAP_IKEV2=y\n\n# EAP-EKE\n#CONFIG_EAP_EKE=y\n\n# MACsec\n#CONFIG_MACSEC=y\n\n# PKCS#12 (PFX) support (used to read private key and certificate file from\n# a file that usually has extension .p12 or .pfx)\n#CONFIG_PKCS12=y\n\n# Smartcard support (i.e., private key on a smartcard), e.g., with openssl\n# engine.\n#CONFIG_SMARTCARD=y\n\n# PC/SC interface for smartcards (USIM, GSM SIM)\n# Enable this if EAP-SIM or EAP-AKA is included\n#CONFIG_PCSC=y\n\n# Support HT overrides (disable HT/HT40, mask MCS rates, etc.)\nCONFIG_HT_OVERRIDES=y\n\n# Support VHT overrides (disable VHT, mask MCS rates, etc.)\nCONFIG_VHT_OVERRIDES=y\n\n# Development testing\n#CONFIG_EAPOL_TEST=y\n\n# Select control interface backend for external programs, e.g, wpa_cli:\n# unix = UNIX domain sockets (default for Linux/*BSD)\n# udp = UDP sockets using localhost (127.0.0.1)\n# udp6 = UDP IPv6 sockets using localhost (::1)\n# named_pipe = Windows Named Pipe (default for Windows)\n# udp-remote = UDP sockets with remote access (only for tests systems/purpose)\n# udp6-remote = UDP IPv6 sockets with remote access (only for tests purpose)\n# y = use default (backwards compatibility)\n# If this option is commented out, control interface is not included in the\n# build.\nCONFIG_CTRL_IFACE=y\n\n# Include support for GNU Readline and History Libraries in wpa_cli.\n# When building a wpa_cli binary for distribution, please note that these\n# libraries are licensed under GPL and as such, BSD license may not apply for\n# the resulting binary.\n#CONFIG_READLINE=y\n\n# Include internal line edit mode in wpa_cli. This can be used as a replacement\n# for GNU Readline to provide limited command line editing and history support.\n#CONFIG_WPA_CLI_EDIT=y\n\n# Remove debugging code that is printing out debug message to stdout.\n# This can be used to reduce the size of the wpa_supplicant considerably\n# if debugging code is not needed. The size reduction can be around 35%\n# (e.g., 90 kB).\n#CONFIG_NO_STDOUT_DEBUG=y\n\n# Remove WPA support, e.g., for wired-only IEEE 802.1X supplicant, to save\n# 35-50 kB in code size.\n#CONFIG_NO_WPA=y\n\n# Remove IEEE 802.11i/WPA-Personal ASCII passphrase support\n# This option can be used to reduce code size by removing support for\n# converting ASCII passphrases into PSK. If this functionality is removed, the\n# PSK can only be configured as the 64-octet hexstring (e.g., from\n# wpa_passphrase). This saves about 0.5 kB in code size.\n#CONFIG_NO_WPA_PASSPHRASE=y\n\n# Simultaneous Authentication of Equals (SAE), WPA3-Personal\n#CONFIG_SAE=y\n\n# Disable scan result processing (ap_mode=1) to save code size by about 1 kB.\n# This can be used if ap_scan=1 mode is never enabled.\n#CONFIG_NO_SCAN_PROCESSING=y\n\n# Select configuration backend:\n# file = text file (e.g., wpa_supplicant.conf; note: the configuration file\n#\tpath is given on command line, not here; this option is just used to\n#\tselect the backend that allows configuration files to be used)\n# winreg = Windows registry (see win_example.reg for an example)\nCONFIG_BACKEND=file\n\n# Remove configuration write functionality (i.e., to allow the configuration\n# file to be updated based on runtime configuration changes). The runtime\n# configuration can still be changed, the changes are just not going to be\n# persistent over restarts. This option can be used to reduce code size by\n# about 3.5 kB.\nCONFIG_NO_CONFIG_WRITE=y\n\n# Remove support for configuration blobs to reduce code size by about 1.5 kB.\n#CONFIG_NO_CONFIG_BLOBS=y\n\n# Select program entry point implementation:\n# main = UNIX/POSIX like main() function (default)\n# main_winsvc = Windows service (read parameters from registry)\n# main_none = Very basic example (development use only)\n#CONFIG_MAIN=main\n\n# Select wrapper for operating system and C library specific functions\n# unix = UNIX/POSIX like systems (default)\n# win32 = Windows systems\n# none = Empty template\n#CONFIG_OS=unix\n\n# Select event loop implementation\n# eloop = select() loop (default)\n# eloop_win = Windows events and WaitForMultipleObject() loop\n#CONFIG_ELOOP=eloop\n\n# Should we use poll instead of select? Select is used by default.\n#CONFIG_ELOOP_POLL=y\n\n# Should we use epoll instead of select? Select is used by default.\nCONFIG_ELOOP_EPOLL=y\n\n# Should we use kqueue instead of select? Select is used by default.\n#CONFIG_ELOOP_KQUEUE=y\n\n# Select layer 2 packet implementation\n# linux = Linux packet socket (default)\n# pcap = libpcap/libdnet/WinPcap\n# freebsd = FreeBSD libpcap\n# winpcap = WinPcap with receive thread\n# ndis = Windows NDISUIO (note: requires CONFIG_USE_NDISUIO=y)\n# none = Empty template\n#CONFIG_L2_PACKET=linux\n\n# Disable Linux packet socket workaround applicable for station interface\n# in a bridge for EAPOL frames. This should be uncommented only if the kernel\n# is known to not have the regression issue in packet socket behavior with\n# bridge interfaces (commit 'bridge: respect RFC2863 operational state')').\nCONFIG_NO_LINUX_PACKET_SOCKET_WAR=y\n\n# IEEE 802.11w (management frame protection), also known as PMF\n# Driver support is also needed for IEEE 802.11w.\n#CONFIG_IEEE80211W=y\n\n# Support Operating Channel Validation\n#CONFIG_OCV=y\n\n# Select TLS implementation\n# openssl = OpenSSL (default)\n# gnutls = GnuTLS\n# internal = Internal TLSv1 implementation (experimental)\n# linux = Linux kernel AF_ALG and internal TLSv1 implementation (experimental)\n# none = Empty template\nCONFIG_TLS=internal\n\n# TLS-based EAP methods require at least TLS v1.0. Newer version of TLS (v1.1)\n# can be enabled to get a stronger construction of messages when block ciphers\n# are used. It should be noted that some existing TLS v1.0 -based\n# implementation may not be compatible with TLS v1.1 message (ClientHello is\n# sent prior to negotiating which version will be used)\n#CONFIG_TLSV11=y\n\n# TLS-based EAP methods require at least TLS v1.0. Newer version of TLS (v1.2)\n# can be enabled to enable use of stronger crypto algorithms. It should be\n# noted that some existing TLS v1.0 -based implementation may not be compatible\n# with TLS v1.2 message (ClientHello is sent prior to negotiating which version\n# will be used)\n#CONFIG_TLSV12=y\n\n# Select which ciphers to use by default with OpenSSL if the user does not\n# specify them.\n#CONFIG_TLS_DEFAULT_CIPHERS=\"DEFAULT:!EXP:!LOW\"\n\n# If CONFIG_TLS=internal is used, additional library and include paths are\n# needed for LibTomMath. Alternatively, an integrated, minimal version of\n# LibTomMath can be used. See beginning of libtommath.c for details on benefits\n# and drawbacks of this option.\n#CONFIG_INTERNAL_LIBTOMMATH=y\n#ifndef CONFIG_INTERNAL_LIBTOMMATH\n#LTM_PATH=/usr/src/libtommath-0.39\n#CFLAGS += -I$(LTM_PATH)\n#LIBS += -L$(LTM_PATH)\n#LIBS_p += -L$(LTM_PATH)\n#endif\n# At the cost of about 4 kB of additional binary size, the internal LibTomMath\n# can be configured to include faster routines for exptmod, sqr, and div to\n# speed up DH and RSA calculation considerably\n#CONFIG_INTERNAL_LIBTOMMATH_FAST=y\n\n# Include NDIS event processing through WMI into wpa_supplicant/wpasvc.\n# This is only for Windows builds and requires WMI-related header files and\n# WbemUuid.Lib from Platform SDK even when building with MinGW.\n#CONFIG_NDIS_EVENTS_INTEGRATED=y\n#PLATFORMSDKLIB=\"/opt/Program Files/Microsoft Platform SDK/Lib\"\n\n# Add support for new DBus control interface\n# (fi.w1.hostap.wpa_supplicant1)\n#CONFIG_CTRL_IFACE_DBUS_NEW=y\n\n# Add introspection support for new DBus control interface\n#CONFIG_CTRL_IFACE_DBUS_INTRO=y\n\n# Add support for loading EAP methods dynamically as shared libraries.\n# When this option is enabled, each EAP method can be either included\n# statically (CONFIG_EAP_<method>=y) or dynamically (CONFIG_EAP_<method>=dyn).\n# Dynamic EAP methods are build as shared objects (eap_*.so) and they need to\n# be loaded in the beginning of the wpa_supplicant configuration file\n# (see load_dynamic_eap parameter in the example file) before being used in\n# the network blocks.\n#\n# Note that some shared parts of EAP methods are included in the main program\n# and in order to be able to use dynamic EAP methods using these parts, the\n# main program must have been build with the EAP method enabled (=y or =dyn).\n# This means that EAP-TLS/PEAP/TTLS/FAST cannot be added as dynamic libraries\n# unless at least one of them was included in the main build to force inclusion\n# of the shared code. Similarly, at least one of EAP-SIM/AKA must be included\n# in the main build to be able to load these methods dynamically.\n#\n# Please also note that using dynamic libraries will increase the total binary\n# size. Thus, it may not be the best option for targets that have limited\n# amount of memory/flash.\n#CONFIG_DYNAMIC_EAP_METHODS=y\n\n# IEEE Std 802.11r-2008 (Fast BSS Transition) for station mode\nCONFIG_IEEE80211R=y\n\n# Add support for writing debug log to a file (/tmp/wpa_supplicant-log-#.txt)\n#CONFIG_DEBUG_FILE=y\n\n# Send debug messages to syslog instead of stdout\nCONFIG_DEBUG_SYSLOG=y\n# Set syslog facility for debug messages\nCONFIG_DEBUG_SYSLOG_FACILITY=LOG_DAEMON\n\n# Add support for sending all debug messages (regardless of debug verbosity)\n# to the Linux kernel tracing facility. This helps debug the entire stack by\n# making it easy to record everything happening from the driver up into the\n# same file, e.g., using trace-cmd.\n#CONFIG_DEBUG_LINUX_TRACING=y\n\n# Add support for writing debug log to Android logcat instead of standard\n# output\n#CONFIG_ANDROID_LOG=y\n\n# Enable privilege separation (see README 'Privilege separation' for details)\n#CONFIG_PRIVSEP=y\n\n# Enable mitigation against certain attacks against TKIP by delaying Michael\n# MIC error reports by a random amount of time between 0 and 60 seconds\n#CONFIG_DELAYED_MIC_ERROR_REPORT=y\n\n# Enable tracing code for developer debugging\n# This tracks use of memory allocations and other registrations and reports\n# incorrect use with a backtrace of call (or allocation) location.\n#CONFIG_WPA_TRACE=y\n# For BSD, uncomment these.\n#LIBS += -lexecinfo\n#LIBS_p += -lexecinfo\n#LIBS_c += -lexecinfo\n\n# Use libbfd to get more details for developer debugging\n# This enables use of libbfd to get more detailed symbols for the backtraces\n# generated by CONFIG_WPA_TRACE=y.\n#CONFIG_WPA_TRACE_BFD=y\n# For BSD, uncomment these.\n#LIBS += -lbfd -liberty -lz\n#LIBS_p += -lbfd -liberty -lz\n#LIBS_c += -lbfd -liberty -lz\n\n# wpa_supplicant depends on strong random number generation being available\n# from the operating system. os_get_random() function is used to fetch random\n# data when needed, e.g., for key generation. On Linux and BSD systems, this\n# works by reading /dev/urandom. It should be noted that the OS entropy pool\n# needs to be properly initialized before wpa_supplicant is started. This is\n# important especially on embedded devices that do not have a hardware random\n# number generator and may by default start up with minimal entropy available\n# for random number generation.\n#\n# As a safety net, wpa_supplicant is by default trying to internally collect\n# additional entropy for generating random data to mix in with the data fetched\n# from the OS. This by itself is not considered to be very strong, but it may\n# help in cases where the system pool is not initialized properly. However, it\n# is very strongly recommended that the system pool is initialized with enough\n# entropy either by using hardware assisted random number generator or by\n# storing state over device reboots.\n#\n# wpa_supplicant can be configured to maintain its own entropy store over\n# restarts to enhance random number generation. This is not perfect, but it is\n# much more secure than using the same sequence of random numbers after every\n# reboot. This can be enabled with -e<entropy file> command line option. The\n# specified file needs to be readable and writable by wpa_supplicant.\n#\n# If the os_get_random() is known to provide strong random data (e.g., on\n# Linux/BSD, the board in question is known to have reliable source of random\n# data from /dev/urandom), the internal wpa_supplicant random pool can be\n# disabled. This will save some in binary size and CPU use. However, this\n# should only be considered for builds that are known to be used on devices\n# that meet the requirements described above.\nCONFIG_NO_RANDOM_POOL=y\n\n# Should we attempt to use the getrandom(2) call that provides more reliable\n# yet secure randomness source than /dev/random on Linux 3.17 and newer.\n# Requires glibc 2.25 to build, falls back to /dev/random if unavailable.\nCONFIG_GETRANDOM=y\n\n# IEEE 802.11n (High Throughput) support (mainly for AP mode)\n#CONFIG_IEEE80211N=y\n\n# IEEE 802.11ac (Very High Throughput) support (mainly for AP mode)\n# (depends on CONFIG_IEEE80211N)\n#CONFIG_IEEE80211AC=y\n\n# Wireless Network Management (IEEE Std 802.11v-2011)\n# Note: This is experimental and not complete implementation.\n#CONFIG_WNM=y\n\n# Interworking (IEEE 802.11u)\n# This can be used to enable functionality to improve interworking with\n# external networks (GAS/ANQP to learn more about the networks and network\n# selection based on available credentials).\n#CONFIG_INTERWORKING=y\n\n# Hotspot 2.0\n#CONFIG_HS20=y\n\n# Enable interface matching in wpa_supplicant\n#CONFIG_MATCH_IFACE=y\n\n# Disable roaming in wpa_supplicant\n#CONFIG_NO_ROAMING=y\n\n# AP mode operations with wpa_supplicant\n# This can be used for controlling AP mode operations with wpa_supplicant. It\n# should be noted that this is mainly aimed at simple cases like\n# WPA2-Personal while more complex configurations like WPA2-Enterprise with an\n# external RADIUS server can be supported with hostapd.\n#CONFIG_AP=y\n\n# P2P (Wi-Fi Direct)\n# This can be used to enable P2P support in wpa_supplicant. See README-P2P for\n# more information on P2P operations.\n#CONFIG_P2P=y\n\n# Enable TDLS support\n#CONFIG_TDLS=y\n\n# Wi-Fi Display\n# This can be used to enable Wi-Fi Display extensions for P2P using an external\n# program to control the additional information exchanges in the messages.\n#CONFIG_WIFI_DISPLAY=y\n\n# Autoscan\n# This can be used to enable automatic scan support in wpa_supplicant.\n# See wpa_supplicant.conf for more information on autoscan usage.\n#\n# Enabling directly a module will enable autoscan support.\n# For exponential module:\n#CONFIG_AUTOSCAN_EXPONENTIAL=y\n# For periodic module:\n#CONFIG_AUTOSCAN_PERIODIC=y\n\n# Password (and passphrase, etc.) backend for external storage\n# These optional mechanisms can be used to add support for storing passwords\n# and other secrets in external (to wpa_supplicant) location. This allows, for\n# example, operating system specific key storage to be used\n#\n# External password backend for testing purposes (developer use)\n#CONFIG_EXT_PASSWORD_TEST=y\n\n# Enable Fast Session Transfer (FST)\n#CONFIG_FST=y\n\n# Enable CLI commands for FST testing\n#CONFIG_FST_TEST=y\n\n# OS X builds. This is only for building eapol_test.\n#CONFIG_OSX=y\n\n# Automatic Channel Selection\n# This will allow wpa_supplicant to pick the channel automatically when channel\n# is set to \"0\".\n#\n# TODO: Extend parser to be able to parse \"channel=acs_survey\" as an alternative\n# to \"channel=0\". This would enable us to eventually add other ACS algorithms in\n# similar way.\n#\n# Automatic selection is currently only done through initialization, later on\n# we hope to do background checks to keep us moving to more ideal channels as\n# time goes by. ACS is currently only supported through the nl80211 driver and\n# your driver must have survey dump capability that is filled by the driver\n# during scanning.\n#\n# TODO: In analogy to hostapd be able to customize the ACS survey algorithm with\n# a newly to create wpa_supplicant.conf variable acs_num_scans.\n#\n# Supported ACS drivers:\n# * ath9k\n# * ath5k\n# * ath10k\n#\n# For more details refer to:\n# http://wireless.kernel.org/en/users/Documentation/acs\n#CONFIG_ACS=y\n\n# Support Multi Band Operation\n#CONFIG_MBO=y\n\n# Fast Initial Link Setup (FILS) (IEEE 802.11ai)\n#CONFIG_FILS=y\n# FILS shared key authentication with PFS\n#CONFIG_FILS_SK_PFS=y\n\n# Support RSN on IBSS networks\n# This is needed to be able to use mode=1 network profile with proto=RSN and\n# key_mgmt=WPA-PSK (i.e., full key management instead of WPA-None).\n#CONFIG_IBSS_RSN=y\n\n# External PMKSA cache control\n# This can be used to enable control interface commands that allow the current\n# PMKSA cache entries to be fetched and new entries to be added.\n#CONFIG_PMKSA_CACHE_EXTERNAL=y\n\n# Mesh Networking (IEEE 802.11s)\n#CONFIG_MESH=y\n\n# Background scanning modules\n# These can be used to request wpa_supplicant to perform background scanning\n# operations for roaming within an ESS (same SSID). See the bgscan parameter in\n# the wpa_supplicant.conf file for more details.\n# Periodic background scans based on signal strength\n#CONFIG_BGSCAN_SIMPLE=y\n# Learn channels used by the network and try to avoid bgscans on other\n# channels (experimental)\n#CONFIG_BGSCAN_LEARN=y\n\n# Opportunistic Wireless Encryption (OWE)\n# Experimental implementation of draft-harkins-owe-07.txt\n#CONFIG_OWE=y\n\n# Device Provisioning Protocol (DPP)\n# This requires CONFIG_IEEE80211W=y to be enabled, too. (see\n# wpa_supplicant/README-DPP for details)\n#CONFIG_DPP=y\n\n# uBus IPC/RPC System\n# Services can connect to the bus and provide methods\n# that can be called by other services or clients.\nCONFIG_UBUS=y\n\n# OpenWrt patch 380-disable-ctrl-iface-mib.patch\n# leads to the MIB only being compiled in if\n# CONFIG_CTRL_IFACE_MIB is enabled.\n#CONFIG_CTRL_IFACE_MIB=y\n"
  },
  {
    "path": "package/network/services/hostapd/files/wpa_supplicant-full.config",
    "content": "# Example wpa_supplicant build time configuration\n#\n# This file lists the configuration options that are used when building the\n# wpa_supplicant binary. All lines starting with # are ignored. Configuration\n# option lines must be commented out complete, if they are not to be included,\n# i.e., just setting VARIABLE=n is not disabling that variable.\n#\n# This file is included in Makefile, so variables like CFLAGS and LIBS can also\n# be modified from here. In most cases, these lines should use += in order not\n# to override previous values of the variables.\n\n\n# Uncomment following two lines and fix the paths if you have installed OpenSSL\n# or GnuTLS in non-default location\n#CFLAGS += -I/usr/local/openssl/include\n#LIBS += -L/usr/local/openssl/lib\n\n# Some Red Hat versions seem to include kerberos header files from OpenSSL, but\n# the kerberos files are not in the default include path. Following line can be\n# used to fix build issues on such systems (krb5.h not found).\n#CFLAGS += -I/usr/include/kerberos\n\n# Driver interface for generic Linux wireless extensions\n# Note: WEXT is deprecated in the current Linux kernel version and no new\n# functionality is added to it. nl80211-based interface is the new\n# replacement for WEXT and its use allows wpa_supplicant to properly control\n# the driver to improve existing functionality like roaming and to support new\n# functionality.\nCONFIG_DRIVER_WEXT=y\n\n# Driver interface for Linux drivers using the nl80211 kernel interface\nCONFIG_DRIVER_NL80211=y\n\n# QCA vendor extensions to nl80211\n#CONFIG_DRIVER_NL80211_QCA=y\n\n# driver_nl80211.c requires libnl. If you are compiling it yourself\n# you may need to point hostapd to your version of libnl.\n#\n#CFLAGS += -I$<path to libnl include files>\n#LIBS += -L$<path to libnl library files>\n\n# Use libnl v2.0 (or 3.0) libraries.\n#CONFIG_LIBNL20=y\n\n# Use libnl 3.2 libraries (if this is selected, CONFIG_LIBNL20 is ignored)\n#CONFIG_LIBNL32=y\n\n\n# Driver interface for FreeBSD net80211 layer (e.g., Atheros driver)\n#CONFIG_DRIVER_BSD=y\n#CFLAGS += -I/usr/local/include\n#LIBS += -L/usr/local/lib\n#LIBS_p += -L/usr/local/lib\n#LIBS_c += -L/usr/local/lib\n\n# Driver interface for Windows NDIS\n#CONFIG_DRIVER_NDIS=y\n#CFLAGS += -I/usr/include/w32api/ddk\n#LIBS += -L/usr/local/lib\n# For native build using mingw\n#CONFIG_NATIVE_WINDOWS=y\n# Additional directories for cross-compilation on Linux host for mingw target\n#CFLAGS += -I/opt/mingw/mingw32/include/ddk\n#LIBS += -L/opt/mingw/mingw32/lib\n#CC=mingw32-gcc\n# By default, driver_ndis uses WinPcap for low-level operations. This can be\n# replaced with the following option which replaces WinPcap calls with NDISUIO.\n# However, this requires that WZC is disabled (net stop wzcsvc) before starting\n# wpa_supplicant.\n# CONFIG_USE_NDISUIO=y\n\n# Driver interface for wired Ethernet drivers\nCONFIG_DRIVER_WIRED=y\n\n# Driver interface for MACsec capable Qualcomm Atheros drivers\n#CONFIG_DRIVER_MACSEC_QCA=y\n\n# Driver interface for Linux MACsec drivers\n#CONFIG_DRIVER_MACSEC_LINUX=y\n\n# Driver interface for the Broadcom RoboSwitch family\n#CONFIG_DRIVER_ROBOSWITCH=y\n\n# Driver interface for no driver (e.g., WPS ER only)\n#CONFIG_DRIVER_NONE=y\n\n# Solaris libraries\n#LIBS += -lsocket -ldlpi -lnsl\n#LIBS_c += -lsocket\n\n# Enable IEEE 802.1X Supplicant (automatically included if any EAP method or\n# MACsec is included)\nCONFIG_IEEE8021X_EAPOL=y\n\n# EAP-MD5\nCONFIG_EAP_MD5=y\n\n# EAP-MSCHAPv2\nCONFIG_EAP_MSCHAPV2=y\n\n# EAP-TLS\nCONFIG_EAP_TLS=y\n\n# EAL-PEAP\nCONFIG_EAP_PEAP=y\n\n# EAP-TTLS\nCONFIG_EAP_TTLS=y\n\n# EAP-FAST\nCONFIG_EAP_FAST=y\n\n# EAP-TEAP\n# Note: The current EAP-TEAP implementation is experimental and should not be\n# enabled for production use. The IETF RFC 7170 that defines EAP-TEAP has number\n# of conflicting statements and missing details and the implementation has\n# vendor specific workarounds for those and as such, may not interoperate with\n# any other implementation. This should not be used for anything else than\n# experimentation and interoperability testing until those issues has been\n# resolved.\n#CONFIG_EAP_TEAP=y\n\n# EAP-GTC\nCONFIG_EAP_GTC=y\n\n# EAP-OTP\nCONFIG_EAP_OTP=y\n\n# EAP-SIM (enable CONFIG_PCSC, if EAP-SIM is used)\n#CONFIG_EAP_SIM=y\n\n# Enable SIM simulator (Milenage) for EAP-SIM\n#CONFIG_SIM_SIMULATOR=y\n\n# EAP-PSK (experimental; this is _not_ needed for WPA-PSK)\n#CONFIG_EAP_PSK=y\n\n# EAP-pwd (secure authentication using only a password)\n#CONFIG_EAP_PWD=y\n\n# EAP-PAX\n#CONFIG_EAP_PAX=y\n\n# LEAP\nCONFIG_EAP_LEAP=y\n\n# EAP-AKA (enable CONFIG_PCSC, if EAP-AKA is used)\n#CONFIG_EAP_AKA=y\n\n# EAP-AKA' (enable CONFIG_PCSC, if EAP-AKA' is used).\n# This requires CONFIG_EAP_AKA to be enabled, too.\n#CONFIG_EAP_AKA_PRIME=y\n\n# Enable USIM simulator (Milenage) for EAP-AKA\n#CONFIG_USIM_SIMULATOR=y\n\n# EAP-SAKE\n#CONFIG_EAP_SAKE=y\n\n# EAP-GPSK\n#CONFIG_EAP_GPSK=y\n# Include support for optional SHA256 cipher suite in EAP-GPSK\n#CONFIG_EAP_GPSK_SHA256=y\n\n# EAP-TNC and related Trusted Network Connect support (experimental)\n#CONFIG_EAP_TNC=y\n\n# Wi-Fi Protected Setup (WPS)\nCONFIG_WPS=y\n# Enable WPS external registrar functionality\n#CONFIG_WPS_ER=y\n# Disable credentials for an open network by default when acting as a WPS\n# registrar.\n#CONFIG_WPS_REG_DISABLE_OPEN=y\n# Enable WPS support with NFC config method\n#CONFIG_WPS_NFC=y\n\n# EAP-IKEv2\n#CONFIG_EAP_IKEV2=y\n\n# EAP-EKE\n#CONFIG_EAP_EKE=y\n\n# MACsec\n#CONFIG_MACSEC=y\n\n# PKCS#12 (PFX) support (used to read private key and certificate file from\n# a file that usually has extension .p12 or .pfx)\nCONFIG_PKCS12=y\n\n# Smartcard support (i.e., private key on a smartcard), e.g., with openssl\n# engine.\nCONFIG_SMARTCARD=y\n\n# PC/SC interface for smartcards (USIM, GSM SIM)\n# Enable this if EAP-SIM or EAP-AKA is included\n#CONFIG_PCSC=y\n\n# Support HT overrides (disable HT/HT40, mask MCS rates, etc.)\nCONFIG_HT_OVERRIDES=y\n\n# Support VHT overrides (disable VHT, mask MCS rates, etc.)\nCONFIG_VHT_OVERRIDES=y\n\n# Development testing\n#CONFIG_EAPOL_TEST=y\n\n# Select control interface backend for external programs, e.g, wpa_cli:\n# unix = UNIX domain sockets (default for Linux/*BSD)\n# udp = UDP sockets using localhost (127.0.0.1)\n# udp6 = UDP IPv6 sockets using localhost (::1)\n# named_pipe = Windows Named Pipe (default for Windows)\n# udp-remote = UDP sockets with remote access (only for tests systems/purpose)\n# udp6-remote = UDP IPv6 sockets with remote access (only for tests purpose)\n# y = use default (backwards compatibility)\n# If this option is commented out, control interface is not included in the\n# build.\nCONFIG_CTRL_IFACE=y\n\n# Include support for GNU Readline and History Libraries in wpa_cli.\n# When building a wpa_cli binary for distribution, please note that these\n# libraries are licensed under GPL and as such, BSD license may not apply for\n# the resulting binary.\n#CONFIG_READLINE=y\n\n# Include internal line edit mode in wpa_cli. This can be used as a replacement\n# for GNU Readline to provide limited command line editing and history support.\n#CONFIG_WPA_CLI_EDIT=y\n\n# Remove debugging code that is printing out debug message to stdout.\n# This can be used to reduce the size of the wpa_supplicant considerably\n# if debugging code is not needed. The size reduction can be around 35%\n# (e.g., 90 kB).\n#CONFIG_NO_STDOUT_DEBUG=y\n\n# Remove WPA support, e.g., for wired-only IEEE 802.1X supplicant, to save\n# 35-50 kB in code size.\n#CONFIG_NO_WPA=y\n\n# Remove IEEE 802.11i/WPA-Personal ASCII passphrase support\n# This option can be used to reduce code size by removing support for\n# converting ASCII passphrases into PSK. If this functionality is removed, the\n# PSK can only be configured as the 64-octet hexstring (e.g., from\n# wpa_passphrase). This saves about 0.5 kB in code size.\n#CONFIG_NO_WPA_PASSPHRASE=y\n\n# Simultaneous Authentication of Equals (SAE), WPA3-Personal\n#CONFIG_SAE=y\n\n# Disable scan result processing (ap_mode=1) to save code size by about 1 kB.\n# This can be used if ap_scan=1 mode is never enabled.\n#CONFIG_NO_SCAN_PROCESSING=y\n\n# Select configuration backend:\n# file = text file (e.g., wpa_supplicant.conf; note: the configuration file\n#\tpath is given on command line, not here; this option is just used to\n#\tselect the backend that allows configuration files to be used)\n# winreg = Windows registry (see win_example.reg for an example)\nCONFIG_BACKEND=file\n\n# Remove configuration write functionality (i.e., to allow the configuration\n# file to be updated based on runtime configuration changes). The runtime\n# configuration can still be changed, the changes are just not going to be\n# persistent over restarts. This option can be used to reduce code size by\n# about 3.5 kB.\n#CONFIG_NO_CONFIG_WRITE=y\n\n# Remove support for configuration blobs to reduce code size by about 1.5 kB.\n#CONFIG_NO_CONFIG_BLOBS=y\n\n# Select program entry point implementation:\n# main = UNIX/POSIX like main() function (default)\n# main_winsvc = Windows service (read parameters from registry)\n# main_none = Very basic example (development use only)\n#CONFIG_MAIN=main\n\n# Select wrapper for operating system and C library specific functions\n# unix = UNIX/POSIX like systems (default)\n# win32 = Windows systems\n# none = Empty template\n#CONFIG_OS=unix\n\n# Select event loop implementation\n# eloop = select() loop (default)\n# eloop_win = Windows events and WaitForMultipleObject() loop\n#CONFIG_ELOOP=eloop\n\n# Should we use poll instead of select? Select is used by default.\n#CONFIG_ELOOP_POLL=y\n\n# Should we use epoll instead of select? Select is used by default.\nCONFIG_ELOOP_EPOLL=y\n\n# Should we use kqueue instead of select? Select is used by default.\n#CONFIG_ELOOP_KQUEUE=y\n\n# Select layer 2 packet implementation\n# linux = Linux packet socket (default)\n# pcap = libpcap/libdnet/WinPcap\n# freebsd = FreeBSD libpcap\n# winpcap = WinPcap with receive thread\n# ndis = Windows NDISUIO (note: requires CONFIG_USE_NDISUIO=y)\n# none = Empty template\n#CONFIG_L2_PACKET=linux\n\n# Disable Linux packet socket workaround applicable for station interface\n# in a bridge for EAPOL frames. This should be uncommented only if the kernel\n# is known to not have the regression issue in packet socket behavior with\n# bridge interfaces (commit 'bridge: respect RFC2863 operational state')').\nCONFIG_NO_LINUX_PACKET_SOCKET_WAR=y\n\n# IEEE 802.11w (management frame protection), also known as PMF\n# Driver support is also needed for IEEE 802.11w.\n#CONFIG_IEEE80211W=y\n\n# Support Operating Channel Validation\n#CONFIG_OCV=y\n\n# Select TLS implementation\n# openssl = OpenSSL (default)\n# gnutls = GnuTLS\n# internal = Internal TLSv1 implementation (experimental)\n# linux = Linux kernel AF_ALG and internal TLSv1 implementation (experimental)\n# none = Empty template\nCONFIG_TLS=internal\n\n# TLS-based EAP methods require at least TLS v1.0. Newer version of TLS (v1.1)\n# can be enabled to get a stronger construction of messages when block ciphers\n# are used. It should be noted that some existing TLS v1.0 -based\n# implementation may not be compatible with TLS v1.1 message (ClientHello is\n# sent prior to negotiating which version will be used)\n#CONFIG_TLSV11=y\n\n# TLS-based EAP methods require at least TLS v1.0. Newer version of TLS (v1.2)\n# can be enabled to enable use of stronger crypto algorithms. It should be\n# noted that some existing TLS v1.0 -based implementation may not be compatible\n# with TLS v1.2 message (ClientHello is sent prior to negotiating which version\n# will be used)\n#CONFIG_TLSV12=y\n\n# Select which ciphers to use by default with OpenSSL if the user does not\n# specify them.\n#CONFIG_TLS_DEFAULT_CIPHERS=\"DEFAULT:!EXP:!LOW\"\n\n# If CONFIG_TLS=internal is used, additional library and include paths are\n# needed for LibTomMath. Alternatively, an integrated, minimal version of\n# LibTomMath can be used. See beginning of libtommath.c for details on benefits\n# and drawbacks of this option.\nCONFIG_INTERNAL_LIBTOMMATH=y\n#ifndef CONFIG_INTERNAL_LIBTOMMATH\n#LTM_PATH=/usr/src/libtommath-0.39\n#CFLAGS += -I$(LTM_PATH)\n#LIBS += -L$(LTM_PATH)\n#LIBS_p += -L$(LTM_PATH)\n#endif\n# At the cost of about 4 kB of additional binary size, the internal LibTomMath\n# can be configured to include faster routines for exptmod, sqr, and div to\n# speed up DH and RSA calculation considerably\nCONFIG_INTERNAL_LIBTOMMATH_FAST=y\n\n# Include NDIS event processing through WMI into wpa_supplicant/wpasvc.\n# This is only for Windows builds and requires WMI-related header files and\n# WbemUuid.Lib from Platform SDK even when building with MinGW.\n#CONFIG_NDIS_EVENTS_INTEGRATED=y\n#PLATFORMSDKLIB=\"/opt/Program Files/Microsoft Platform SDK/Lib\"\n\n# Add support for new DBus control interface\n# (fi.w1.hostap.wpa_supplicant1)\n#CONFIG_CTRL_IFACE_DBUS_NEW=y\n\n# Add introspection support for new DBus control interface\n#CONFIG_CTRL_IFACE_DBUS_INTRO=y\n\n# Add support for loading EAP methods dynamically as shared libraries.\n# When this option is enabled, each EAP method can be either included\n# statically (CONFIG_EAP_<method>=y) or dynamically (CONFIG_EAP_<method>=dyn).\n# Dynamic EAP methods are build as shared objects (eap_*.so) and they need to\n# be loaded in the beginning of the wpa_supplicant configuration file\n# (see load_dynamic_eap parameter in the example file) before being used in\n# the network blocks.\n#\n# Note that some shared parts of EAP methods are included in the main program\n# and in order to be able to use dynamic EAP methods using these parts, the\n# main program must have been build with the EAP method enabled (=y or =dyn).\n# This means that EAP-TLS/PEAP/TTLS/FAST cannot be added as dynamic libraries\n# unless at least one of them was included in the main build to force inclusion\n# of the shared code. Similarly, at least one of EAP-SIM/AKA must be included\n# in the main build to be able to load these methods dynamically.\n#\n# Please also note that using dynamic libraries will increase the total binary\n# size. Thus, it may not be the best option for targets that have limited\n# amount of memory/flash.\n#CONFIG_DYNAMIC_EAP_METHODS=y\n\n# IEEE Std 802.11r-2008 (Fast BSS Transition) for station mode\nCONFIG_IEEE80211R=y\n\n# Add support for writing debug log to a file (/tmp/wpa_supplicant-log-#.txt)\n#CONFIG_DEBUG_FILE=y\n\n# Send debug messages to syslog instead of stdout\nCONFIG_DEBUG_SYSLOG=y\n# Set syslog facility for debug messages\nCONFIG_DEBUG_SYSLOG_FACILITY=LOG_DAEMON\n\n# Add support for sending all debug messages (regardless of debug verbosity)\n# to the Linux kernel tracing facility. This helps debug the entire stack by\n# making it easy to record everything happening from the driver up into the\n# same file, e.g., using trace-cmd.\n#CONFIG_DEBUG_LINUX_TRACING=y\n\n# Add support for writing debug log to Android logcat instead of standard\n# output\n#CONFIG_ANDROID_LOG=y\n\n# Enable privilege separation (see README 'Privilege separation' for details)\n#CONFIG_PRIVSEP=y\n\n# Enable mitigation against certain attacks against TKIP by delaying Michael\n# MIC error reports by a random amount of time between 0 and 60 seconds\n#CONFIG_DELAYED_MIC_ERROR_REPORT=y\n\n# Enable tracing code for developer debugging\n# This tracks use of memory allocations and other registrations and reports\n# incorrect use with a backtrace of call (or allocation) location.\n#CONFIG_WPA_TRACE=y\n# For BSD, uncomment these.\n#LIBS += -lexecinfo\n#LIBS_p += -lexecinfo\n#LIBS_c += -lexecinfo\n\n# Use libbfd to get more details for developer debugging\n# This enables use of libbfd to get more detailed symbols for the backtraces\n# generated by CONFIG_WPA_TRACE=y.\n#CONFIG_WPA_TRACE_BFD=y\n# For BSD, uncomment these.\n#LIBS += -lbfd -liberty -lz\n#LIBS_p += -lbfd -liberty -lz\n#LIBS_c += -lbfd -liberty -lz\n\n# wpa_supplicant depends on strong random number generation being available\n# from the operating system. os_get_random() function is used to fetch random\n# data when needed, e.g., for key generation. On Linux and BSD systems, this\n# works by reading /dev/urandom. It should be noted that the OS entropy pool\n# needs to be properly initialized before wpa_supplicant is started. This is\n# important especially on embedded devices that do not have a hardware random\n# number generator and may by default start up with minimal entropy available\n# for random number generation.\n#\n# As a safety net, wpa_supplicant is by default trying to internally collect\n# additional entropy for generating random data to mix in with the data fetched\n# from the OS. This by itself is not considered to be very strong, but it may\n# help in cases where the system pool is not initialized properly. However, it\n# is very strongly recommended that the system pool is initialized with enough\n# entropy either by using hardware assisted random number generator or by\n# storing state over device reboots.\n#\n# wpa_supplicant can be configured to maintain its own entropy store over\n# restarts to enhance random number generation. This is not perfect, but it is\n# much more secure than using the same sequence of random numbers after every\n# reboot. This can be enabled with -e<entropy file> command line option. The\n# specified file needs to be readable and writable by wpa_supplicant.\n#\n# If the os_get_random() is known to provide strong random data (e.g., on\n# Linux/BSD, the board in question is known to have reliable source of random\n# data from /dev/urandom), the internal wpa_supplicant random pool can be\n# disabled. This will save some in binary size and CPU use. However, this\n# should only be considered for builds that are known to be used on devices\n# that meet the requirements described above.\nCONFIG_NO_RANDOM_POOL=y\n\n# Should we attempt to use the getrandom(2) call that provides more reliable\n# yet secure randomness source than /dev/random on Linux 3.17 and newer.\n# Requires glibc 2.25 to build, falls back to /dev/random if unavailable.\nCONFIG_GETRANDOM=y\n\n# IEEE 802.11n (High Throughput) support (mainly for AP mode)\n#CONFIG_IEEE80211N=y\n\n# IEEE 802.11ac (Very High Throughput) support (mainly for AP mode)\n# (depends on CONFIG_IEEE80211N)\n#CONFIG_IEEE80211AC=y\n\n# Wireless Network Management (IEEE Std 802.11v-2011)\n# Note: This is experimental and not complete implementation.\nCONFIG_WNM=y\n\n# Interworking (IEEE 802.11u)\n# This can be used to enable functionality to improve interworking with\n# external networks (GAS/ANQP to learn more about the networks and network\n# selection based on available credentials).\nCONFIG_INTERWORKING=y\n\n# Hotspot 2.0\nCONFIG_HS20=y\n\n# Enable interface matching in wpa_supplicant\n#CONFIG_MATCH_IFACE=y\n\n# Disable roaming in wpa_supplicant\n#CONFIG_NO_ROAMING=y\n\n# AP mode operations with wpa_supplicant\n# This can be used for controlling AP mode operations with wpa_supplicant. It\n# should be noted that this is mainly aimed at simple cases like\n# WPA2-Personal while more complex configurations like WPA2-Enterprise with an\n# external RADIUS server can be supported with hostapd.\n#CONFIG_AP=y\n\n# P2P (Wi-Fi Direct)\n# This can be used to enable P2P support in wpa_supplicant. See README-P2P for\n# more information on P2P operations.\n#CONFIG_P2P=y\n\n# Enable TDLS support\n#CONFIG_TDLS=y\n\n# Wi-Fi Display\n# This can be used to enable Wi-Fi Display extensions for P2P using an external\n# program to control the additional information exchanges in the messages.\n#CONFIG_WIFI_DISPLAY=y\n\n# Autoscan\n# This can be used to enable automatic scan support in wpa_supplicant.\n# See wpa_supplicant.conf for more information on autoscan usage.\n#\n# Enabling directly a module will enable autoscan support.\n# For exponential module:\n#CONFIG_AUTOSCAN_EXPONENTIAL=y\n# For periodic module:\n#CONFIG_AUTOSCAN_PERIODIC=y\n\n# Password (and passphrase, etc.) backend for external storage\n# These optional mechanisms can be used to add support for storing passwords\n# and other secrets in external (to wpa_supplicant) location. This allows, for\n# example, operating system specific key storage to be used\n#\n# External password backend for testing purposes (developer use)\n#CONFIG_EXT_PASSWORD_TEST=y\n\n# Enable Fast Session Transfer (FST)\n#CONFIG_FST=y\n\n# Enable CLI commands for FST testing\n#CONFIG_FST_TEST=y\n\n# OS X builds. This is only for building eapol_test.\n#CONFIG_OSX=y\n\n# Automatic Channel Selection\n# This will allow wpa_supplicant to pick the channel automatically when channel\n# is set to \"0\".\n#\n# TODO: Extend parser to be able to parse \"channel=acs_survey\" as an alternative\n# to \"channel=0\". This would enable us to eventually add other ACS algorithms in\n# similar way.\n#\n# Automatic selection is currently only done through initialization, later on\n# we hope to do background checks to keep us moving to more ideal channels as\n# time goes by. ACS is currently only supported through the nl80211 driver and\n# your driver must have survey dump capability that is filled by the driver\n# during scanning.\n#\n# TODO: In analogy to hostapd be able to customize the ACS survey algorithm with\n# a newly to create wpa_supplicant.conf variable acs_num_scans.\n#\n# Supported ACS drivers:\n# * ath9k\n# * ath5k\n# * ath10k\n#\n# For more details refer to:\n# http://wireless.kernel.org/en/users/Documentation/acs\n#CONFIG_ACS=y\n\n# Support Multi Band Operation\n#CONFIG_MBO=y\n\n# Fast Initial Link Setup (FILS) (IEEE 802.11ai)\nCONFIG_FILS=y\n# FILS shared key authentication with PFS\n#CONFIG_FILS_SK_PFS=y\n\n# Support RSN on IBSS networks\n# This is needed to be able to use mode=1 network profile with proto=RSN and\n# key_mgmt=WPA-PSK (i.e., full key management instead of WPA-None).\nCONFIG_IBSS_RSN=y\n\n# External PMKSA cache control\n# This can be used to enable control interface commands that allow the current\n# PMKSA cache entries to be fetched and new entries to be added.\n#CONFIG_PMKSA_CACHE_EXTERNAL=y\n\n# Mesh Networking (IEEE 802.11s)\n#CONFIG_MESH=y\n\n# Background scanning modules\n# These can be used to request wpa_supplicant to perform background scanning\n# operations for roaming within an ESS (same SSID). See the bgscan parameter in\n# the wpa_supplicant.conf file for more details.\n# Periodic background scans based on signal strength\n#CONFIG_BGSCAN_SIMPLE=y\n# Learn channels used by the network and try to avoid bgscans on other\n# channels (experimental)\n#CONFIG_BGSCAN_LEARN=y\n\n# Opportunistic Wireless Encryption (OWE)\n# Experimental implementation of draft-harkins-owe-07.txt\n#CONFIG_OWE=y\n\n# Device Provisioning Protocol (DPP)\n# This requires CONFIG_IEEE80211W=y to be enabled, too. (see\n# wpa_supplicant/README-DPP for details)\n#CONFIG_DPP=y\n\n# uBus IPC/RPC System\n# Services can connect to the bus and provide methods\n# that can be called by other services or clients.\nCONFIG_UBUS=y\n\n# OpenWrt patch 380-disable-ctrl-iface-mib.patch\n# leads to the MIB only being compiled in if\n# CONFIG_CTRL_IFACE_MIB is enabled.\nCONFIG_CTRL_IFACE_MIB=y\n"
  },
  {
    "path": "package/network/services/hostapd/files/wpa_supplicant-mini.config",
    "content": "# Example wpa_supplicant build time configuration\n#\n# This file lists the configuration options that are used when building the\n# wpa_supplicant binary. All lines starting with # are ignored. Configuration\n# option lines must be commented out complete, if they are not to be included,\n# i.e., just setting VARIABLE=n is not disabling that variable.\n#\n# This file is included in Makefile, so variables like CFLAGS and LIBS can also\n# be modified from here. In most cases, these lines should use += in order not\n# to override previous values of the variables.\n\n\n# Uncomment following two lines and fix the paths if you have installed OpenSSL\n# or GnuTLS in non-default location\n#CFLAGS += -I/usr/local/openssl/include\n#LIBS += -L/usr/local/openssl/lib\n\n# Some Red Hat versions seem to include kerberos header files from OpenSSL, but\n# the kerberos files are not in the default include path. Following line can be\n# used to fix build issues on such systems (krb5.h not found).\n#CFLAGS += -I/usr/include/kerberos\n\n# Driver interface for generic Linux wireless extensions\n# Note: WEXT is deprecated in the current Linux kernel version and no new\n# functionality is added to it. nl80211-based interface is the new\n# replacement for WEXT and its use allows wpa_supplicant to properly control\n# the driver to improve existing functionality like roaming and to support new\n# functionality.\nCONFIG_DRIVER_WEXT=y\n\n# Driver interface for Linux drivers using the nl80211 kernel interface\nCONFIG_DRIVER_NL80211=y\n\n# QCA vendor extensions to nl80211\n#CONFIG_DRIVER_NL80211_QCA=y\n\n# driver_nl80211.c requires libnl. If you are compiling it yourself\n# you may need to point hostapd to your version of libnl.\n#\n#CFLAGS += -I$<path to libnl include files>\n#LIBS += -L$<path to libnl library files>\n\n# Use libnl v2.0 (or 3.0) libraries.\n#CONFIG_LIBNL20=y\n\n# Use libnl 3.2 libraries (if this is selected, CONFIG_LIBNL20 is ignored)\n#CONFIG_LIBNL32=y\n\n\n# Driver interface for FreeBSD net80211 layer (e.g., Atheros driver)\n#CONFIG_DRIVER_BSD=y\n#CFLAGS += -I/usr/local/include\n#LIBS += -L/usr/local/lib\n#LIBS_p += -L/usr/local/lib\n#LIBS_c += -L/usr/local/lib\n\n# Driver interface for Windows NDIS\n#CONFIG_DRIVER_NDIS=y\n#CFLAGS += -I/usr/include/w32api/ddk\n#LIBS += -L/usr/local/lib\n# For native build using mingw\n#CONFIG_NATIVE_WINDOWS=y\n# Additional directories for cross-compilation on Linux host for mingw target\n#CFLAGS += -I/opt/mingw/mingw32/include/ddk\n#LIBS += -L/opt/mingw/mingw32/lib\n#CC=mingw32-gcc\n# By default, driver_ndis uses WinPcap for low-level operations. This can be\n# replaced with the following option which replaces WinPcap calls with NDISUIO.\n# However, this requires that WZC is disabled (net stop wzcsvc) before starting\n# wpa_supplicant.\n# CONFIG_USE_NDISUIO=y\n\n# Driver interface for wired Ethernet drivers\nCONFIG_DRIVER_WIRED=y\n\n# Driver interface for MACsec capable Qualcomm Atheros drivers\n#CONFIG_DRIVER_MACSEC_QCA=y\n\n# Driver interface for Linux MACsec drivers\n#CONFIG_DRIVER_MACSEC_LINUX=y\n\n# Driver interface for the Broadcom RoboSwitch family\n#CONFIG_DRIVER_ROBOSWITCH=y\n\n# Driver interface for no driver (e.g., WPS ER only)\n#CONFIG_DRIVER_NONE=y\n\n# Solaris libraries\n#LIBS += -lsocket -ldlpi -lnsl\n#LIBS_c += -lsocket\n\n# Enable IEEE 802.1X Supplicant (automatically included if any EAP method or\n# MACsec is included)\n#CONFIG_IEEE8021X_EAPOL=y\n\n# EAP-MD5\n#CONFIG_EAP_MD5=y\n\n# EAP-MSCHAPv2\n#CONFIG_EAP_MSCHAPV2=y\n\n# EAP-TLS\n#CONFIG_EAP_TLS=y\n\n# EAL-PEAP\n#CONFIG_EAP_PEAP=y\n\n# EAP-TTLS\n#CONFIG_EAP_TTLS=y\n\n# EAP-FAST\n#CONFIG_EAP_FAST=y\n\n# EAP-TEAP\n# Note: The current EAP-TEAP implementation is experimental and should not be\n# enabled for production use. The IETF RFC 7170 that defines EAP-TEAP has number\n# of conflicting statements and missing details and the implementation has\n# vendor specific workarounds for those and as such, may not interoperate with\n# any other implementation. This should not be used for anything else than\n# experimentation and interoperability testing until those issues has been\n# resolved.\n#CONFIG_EAP_TEAP=y\n\n# EAP-GTC\n#CONFIG_EAP_GTC=y\n\n# EAP-OTP\n#CONFIG_EAP_OTP=y\n\n# EAP-SIM (enable CONFIG_PCSC, if EAP-SIM is used)\n#CONFIG_EAP_SIM=y\n\n# Enable SIM simulator (Milenage) for EAP-SIM\n#CONFIG_SIM_SIMULATOR=y\n\n# EAP-PSK (experimental; this is _not_ needed for WPA-PSK)\n#CONFIG_EAP_PSK=y\n\n# EAP-pwd (secure authentication using only a password)\n#CONFIG_EAP_PWD=y\n\n# EAP-PAX\n#CONFIG_EAP_PAX=y\n\n# LEAP\n#CONFIG_EAP_LEAP=y\n\n# EAP-AKA (enable CONFIG_PCSC, if EAP-AKA is used)\n#CONFIG_EAP_AKA=y\n\n# EAP-AKA' (enable CONFIG_PCSC, if EAP-AKA' is used).\n# This requires CONFIG_EAP_AKA to be enabled, too.\n#CONFIG_EAP_AKA_PRIME=y\n\n# Enable USIM simulator (Milenage) for EAP-AKA\n#CONFIG_USIM_SIMULATOR=y\n\n# EAP-SAKE\n#CONFIG_EAP_SAKE=y\n\n# EAP-GPSK\n#CONFIG_EAP_GPSK=y\n# Include support for optional SHA256 cipher suite in EAP-GPSK\n#CONFIG_EAP_GPSK_SHA256=y\n\n# EAP-TNC and related Trusted Network Connect support (experimental)\n#CONFIG_EAP_TNC=y\n\n# Wi-Fi Protected Setup (WPS)\n#CONFIG_WPS=y\n# Enable WPS external registrar functionality\n#CONFIG_WPS_ER=y\n# Disable credentials for an open network by default when acting as a WPS\n# registrar.\n#CONFIG_WPS_REG_DISABLE_OPEN=y\n# Enable WPS support with NFC config method\n#CONFIG_WPS_NFC=y\n\n# EAP-IKEv2\n#CONFIG_EAP_IKEV2=y\n\n# EAP-EKE\n#CONFIG_EAP_EKE=y\n\n# MACsec\n#CONFIG_MACSEC=y\n\n# PKCS#12 (PFX) support (used to read private key and certificate file from\n# a file that usually has extension .p12 or .pfx)\n#CONFIG_PKCS12=y\n\n# Smartcard support (i.e., private key on a smartcard), e.g., with openssl\n# engine.\n#CONFIG_SMARTCARD=y\n\n# PC/SC interface for smartcards (USIM, GSM SIM)\n# Enable this if EAP-SIM or EAP-AKA is included\n#CONFIG_PCSC=y\n\n# Support HT overrides (disable HT/HT40, mask MCS rates, etc.)\nCONFIG_HT_OVERRIDES=y\n\n# Support VHT overrides (disable VHT, mask MCS rates, etc.)\nCONFIG_VHT_OVERRIDES=y\n\n# Development testing\n#CONFIG_EAPOL_TEST=y\n\n# Select control interface backend for external programs, e.g, wpa_cli:\n# unix = UNIX domain sockets (default for Linux/*BSD)\n# udp = UDP sockets using localhost (127.0.0.1)\n# udp6 = UDP IPv6 sockets using localhost (::1)\n# named_pipe = Windows Named Pipe (default for Windows)\n# udp-remote = UDP sockets with remote access (only for tests systems/purpose)\n# udp6-remote = UDP IPv6 sockets with remote access (only for tests purpose)\n# y = use default (backwards compatibility)\n# If this option is commented out, control interface is not included in the\n# build.\nCONFIG_CTRL_IFACE=y\n\n# Include support for GNU Readline and History Libraries in wpa_cli.\n# When building a wpa_cli binary for distribution, please note that these\n# libraries are licensed under GPL and as such, BSD license may not apply for\n# the resulting binary.\n#CONFIG_READLINE=y\n\n# Include internal line edit mode in wpa_cli. This can be used as a replacement\n# for GNU Readline to provide limited command line editing and history support.\n#CONFIG_WPA_CLI_EDIT=y\n\n# Remove debugging code that is printing out debug message to stdout.\n# This can be used to reduce the size of the wpa_supplicant considerably\n# if debugging code is not needed. The size reduction can be around 35%\n# (e.g., 90 kB).\n#CONFIG_NO_STDOUT_DEBUG=y\n\n# Remove WPA support, e.g., for wired-only IEEE 802.1X supplicant, to save\n# 35-50 kB in code size.\n#CONFIG_NO_WPA=y\n\n# Remove IEEE 802.11i/WPA-Personal ASCII passphrase support\n# This option can be used to reduce code size by removing support for\n# converting ASCII passphrases into PSK. If this functionality is removed, the\n# PSK can only be configured as the 64-octet hexstring (e.g., from\n# wpa_passphrase). This saves about 0.5 kB in code size.\n#CONFIG_NO_WPA_PASSPHRASE=y\n\n# Simultaneous Authentication of Equals (SAE), WPA3-Personal\n#CONFIG_SAE=y\n\n# Disable scan result processing (ap_mode=1) to save code size by about 1 kB.\n# This can be used if ap_scan=1 mode is never enabled.\n#CONFIG_NO_SCAN_PROCESSING=y\n\n# Select configuration backend:\n# file = text file (e.g., wpa_supplicant.conf; note: the configuration file\n#\tpath is given on command line, not here; this option is just used to\n#\tselect the backend that allows configuration files to be used)\n# winreg = Windows registry (see win_example.reg for an example)\nCONFIG_BACKEND=file\n\n# Remove configuration write functionality (i.e., to allow the configuration\n# file to be updated based on runtime configuration changes). The runtime\n# configuration can still be changed, the changes are just not going to be\n# persistent over restarts. This option can be used to reduce code size by\n# about 3.5 kB.\nCONFIG_NO_CONFIG_WRITE=y\n\n# Remove support for configuration blobs to reduce code size by about 1.5 kB.\n#CONFIG_NO_CONFIG_BLOBS=y\n\n# Select program entry point implementation:\n# main = UNIX/POSIX like main() function (default)\n# main_winsvc = Windows service (read parameters from registry)\n# main_none = Very basic example (development use only)\n#CONFIG_MAIN=main\n\n# Select wrapper for operating system and C library specific functions\n# unix = UNIX/POSIX like systems (default)\n# win32 = Windows systems\n# none = Empty template\n#CONFIG_OS=unix\n\n# Select event loop implementation\n# eloop = select() loop (default)\n# eloop_win = Windows events and WaitForMultipleObject() loop\n#CONFIG_ELOOP=eloop\n\n# Should we use poll instead of select? Select is used by default.\n#CONFIG_ELOOP_POLL=y\n\n# Should we use epoll instead of select? Select is used by default.\nCONFIG_ELOOP_EPOLL=y\n\n# Should we use kqueue instead of select? Select is used by default.\n#CONFIG_ELOOP_KQUEUE=y\n\n# Select layer 2 packet implementation\n# linux = Linux packet socket (default)\n# pcap = libpcap/libdnet/WinPcap\n# freebsd = FreeBSD libpcap\n# winpcap = WinPcap with receive thread\n# ndis = Windows NDISUIO (note: requires CONFIG_USE_NDISUIO=y)\n# none = Empty template\n#CONFIG_L2_PACKET=linux\n\n# Disable Linux packet socket workaround applicable for station interface\n# in a bridge for EAPOL frames. This should be uncommented only if the kernel\n# is known to not have the regression issue in packet socket behavior with\n# bridge interfaces (commit 'bridge: respect RFC2863 operational state')').\nCONFIG_NO_LINUX_PACKET_SOCKET_WAR=y\n\n# IEEE 802.11w (management frame protection), also known as PMF\n# Driver support is also needed for IEEE 802.11w.\n#CONFIG_IEEE80211W=y\n\n# Support Operating Channel Validation\n#CONFIG_OCV=y\n\n# Select TLS implementation\n# openssl = OpenSSL (default)\n# gnutls = GnuTLS\n# internal = Internal TLSv1 implementation (experimental)\n# linux = Linux kernel AF_ALG and internal TLSv1 implementation (experimental)\n# none = Empty template\nCONFIG_TLS=internal\n\n# TLS-based EAP methods require at least TLS v1.0. Newer version of TLS (v1.1)\n# can be enabled to get a stronger construction of messages when block ciphers\n# are used. It should be noted that some existing TLS v1.0 -based\n# implementation may not be compatible with TLS v1.1 message (ClientHello is\n# sent prior to negotiating which version will be used)\n#CONFIG_TLSV11=y\n\n# TLS-based EAP methods require at least TLS v1.0. Newer version of TLS (v1.2)\n# can be enabled to enable use of stronger crypto algorithms. It should be\n# noted that some existing TLS v1.0 -based implementation may not be compatible\n# with TLS v1.2 message (ClientHello is sent prior to negotiating which version\n# will be used)\n#CONFIG_TLSV12=y\n\n# Select which ciphers to use by default with OpenSSL if the user does not\n# specify them.\n#CONFIG_TLS_DEFAULT_CIPHERS=\"DEFAULT:!EXP:!LOW\"\n\n# If CONFIG_TLS=internal is used, additional library and include paths are\n# needed for LibTomMath. Alternatively, an integrated, minimal version of\n# LibTomMath can be used. See beginning of libtommath.c for details on benefits\n# and drawbacks of this option.\n#CONFIG_INTERNAL_LIBTOMMATH=y\n#ifndef CONFIG_INTERNAL_LIBTOMMATH\n#LTM_PATH=/usr/src/libtommath-0.39\n#CFLAGS += -I$(LTM_PATH)\n#LIBS += -L$(LTM_PATH)\n#LIBS_p += -L$(LTM_PATH)\n#endif\n# At the cost of about 4 kB of additional binary size, the internal LibTomMath\n# can be configured to include faster routines for exptmod, sqr, and div to\n# speed up DH and RSA calculation considerably\n#CONFIG_INTERNAL_LIBTOMMATH_FAST=y\n\n# Include NDIS event processing through WMI into wpa_supplicant/wpasvc.\n# This is only for Windows builds and requires WMI-related header files and\n# WbemUuid.Lib from Platform SDK even when building with MinGW.\n#CONFIG_NDIS_EVENTS_INTEGRATED=y\n#PLATFORMSDKLIB=\"/opt/Program Files/Microsoft Platform SDK/Lib\"\n\n# Add support for new DBus control interface\n# (fi.w1.hostap.wpa_supplicant1)\n#CONFIG_CTRL_IFACE_DBUS_NEW=y\n\n# Add introspection support for new DBus control interface\n#CONFIG_CTRL_IFACE_DBUS_INTRO=y\n\n# Add support for loading EAP methods dynamically as shared libraries.\n# When this option is enabled, each EAP method can be either included\n# statically (CONFIG_EAP_<method>=y) or dynamically (CONFIG_EAP_<method>=dyn).\n# Dynamic EAP methods are build as shared objects (eap_*.so) and they need to\n# be loaded in the beginning of the wpa_supplicant configuration file\n# (see load_dynamic_eap parameter in the example file) before being used in\n# the network blocks.\n#\n# Note that some shared parts of EAP methods are included in the main program\n# and in order to be able to use dynamic EAP methods using these parts, the\n# main program must have been build with the EAP method enabled (=y or =dyn).\n# This means that EAP-TLS/PEAP/TTLS/FAST cannot be added as dynamic libraries\n# unless at least one of them was included in the main build to force inclusion\n# of the shared code. Similarly, at least one of EAP-SIM/AKA must be included\n# in the main build to be able to load these methods dynamically.\n#\n# Please also note that using dynamic libraries will increase the total binary\n# size. Thus, it may not be the best option for targets that have limited\n# amount of memory/flash.\n#CONFIG_DYNAMIC_EAP_METHODS=y\n\n# IEEE Std 802.11r-2008 (Fast BSS Transition) for station mode\n#CONFIG_IEEE80211R=y\n\n# Add support for writing debug log to a file (/tmp/wpa_supplicant-log-#.txt)\n#CONFIG_DEBUG_FILE=y\n\n# Send debug messages to syslog instead of stdout\nCONFIG_DEBUG_SYSLOG=y\n# Set syslog facility for debug messages\nCONFIG_DEBUG_SYSLOG_FACILITY=LOG_DAEMON\n\n# Add support for sending all debug messages (regardless of debug verbosity)\n# to the Linux kernel tracing facility. This helps debug the entire stack by\n# making it easy to record everything happening from the driver up into the\n# same file, e.g., using trace-cmd.\n#CONFIG_DEBUG_LINUX_TRACING=y\n\n# Add support for writing debug log to Android logcat instead of standard\n# output\n#CONFIG_ANDROID_LOG=y\n\n# Enable privilege separation (see README 'Privilege separation' for details)\n#CONFIG_PRIVSEP=y\n\n# Enable mitigation against certain attacks against TKIP by delaying Michael\n# MIC error reports by a random amount of time between 0 and 60 seconds\n#CONFIG_DELAYED_MIC_ERROR_REPORT=y\n\n# Enable tracing code for developer debugging\n# This tracks use of memory allocations and other registrations and reports\n# incorrect use with a backtrace of call (or allocation) location.\n#CONFIG_WPA_TRACE=y\n# For BSD, uncomment these.\n#LIBS += -lexecinfo\n#LIBS_p += -lexecinfo\n#LIBS_c += -lexecinfo\n\n# Use libbfd to get more details for developer debugging\n# This enables use of libbfd to get more detailed symbols for the backtraces\n# generated by CONFIG_WPA_TRACE=y.\n#CONFIG_WPA_TRACE_BFD=y\n# For BSD, uncomment these.\n#LIBS += -lbfd -liberty -lz\n#LIBS_p += -lbfd -liberty -lz\n#LIBS_c += -lbfd -liberty -lz\n\n# wpa_supplicant depends on strong random number generation being available\n# from the operating system. os_get_random() function is used to fetch random\n# data when needed, e.g., for key generation. On Linux and BSD systems, this\n# works by reading /dev/urandom. It should be noted that the OS entropy pool\n# needs to be properly initialized before wpa_supplicant is started. This is\n# important especially on embedded devices that do not have a hardware random\n# number generator and may by default start up with minimal entropy available\n# for random number generation.\n#\n# As a safety net, wpa_supplicant is by default trying to internally collect\n# additional entropy for generating random data to mix in with the data fetched\n# from the OS. This by itself is not considered to be very strong, but it may\n# help in cases where the system pool is not initialized properly. However, it\n# is very strongly recommended that the system pool is initialized with enough\n# entropy either by using hardware assisted random number generator or by\n# storing state over device reboots.\n#\n# wpa_supplicant can be configured to maintain its own entropy store over\n# restarts to enhance random number generation. This is not perfect, but it is\n# much more secure than using the same sequence of random numbers after every\n# reboot. This can be enabled with -e<entropy file> command line option. The\n# specified file needs to be readable and writable by wpa_supplicant.\n#\n# If the os_get_random() is known to provide strong random data (e.g., on\n# Linux/BSD, the board in question is known to have reliable source of random\n# data from /dev/urandom), the internal wpa_supplicant random pool can be\n# disabled. This will save some in binary size and CPU use. However, this\n# should only be considered for builds that are known to be used on devices\n# that meet the requirements described above.\nCONFIG_NO_RANDOM_POOL=y\n\n# Should we attempt to use the getrandom(2) call that provides more reliable\n# yet secure randomness source than /dev/random on Linux 3.17 and newer.\n# Requires glibc 2.25 to build, falls back to /dev/random if unavailable.\nCONFIG_GETRANDOM=y\n\n# IEEE 802.11n (High Throughput) support (mainly for AP mode)\n#CONFIG_IEEE80211N=y\n\n# IEEE 802.11ac (Very High Throughput) support (mainly for AP mode)\n# (depends on CONFIG_IEEE80211N)\n#CONFIG_IEEE80211AC=y\n\n# Wireless Network Management (IEEE Std 802.11v-2011)\n# Note: This is experimental and not complete implementation.\n#CONFIG_WNM=y\n\n# Interworking (IEEE 802.11u)\n# This can be used to enable functionality to improve interworking with\n# external networks (GAS/ANQP to learn more about the networks and network\n# selection based on available credentials).\n#CONFIG_INTERWORKING=y\n\n# Hotspot 2.0\n#CONFIG_HS20=y\n\n# Enable interface matching in wpa_supplicant\n#CONFIG_MATCH_IFACE=y\n\n# Disable roaming in wpa_supplicant\n#CONFIG_NO_ROAMING=y\n\n# AP mode operations with wpa_supplicant\n# This can be used for controlling AP mode operations with wpa_supplicant. It\n# should be noted that this is mainly aimed at simple cases like\n# WPA2-Personal while more complex configurations like WPA2-Enterprise with an\n# external RADIUS server can be supported with hostapd.\n#CONFIG_AP=y\n\n# P2P (Wi-Fi Direct)\n# This can be used to enable P2P support in wpa_supplicant. See README-P2P for\n# more information on P2P operations.\n#CONFIG_P2P=y\n\n# Enable TDLS support\n#CONFIG_TDLS=y\n\n# Wi-Fi Display\n# This can be used to enable Wi-Fi Display extensions for P2P using an external\n# program to control the additional information exchanges in the messages.\n#CONFIG_WIFI_DISPLAY=y\n\n# Autoscan\n# This can be used to enable automatic scan support in wpa_supplicant.\n# See wpa_supplicant.conf for more information on autoscan usage.\n#\n# Enabling directly a module will enable autoscan support.\n# For exponential module:\n#CONFIG_AUTOSCAN_EXPONENTIAL=y\n# For periodic module:\n#CONFIG_AUTOSCAN_PERIODIC=y\n\n# Password (and passphrase, etc.) backend for external storage\n# These optional mechanisms can be used to add support for storing passwords\n# and other secrets in external (to wpa_supplicant) location. This allows, for\n# example, operating system specific key storage to be used\n#\n# External password backend for testing purposes (developer use)\n#CONFIG_EXT_PASSWORD_TEST=y\n\n# Enable Fast Session Transfer (FST)\n#CONFIG_FST=y\n\n# Enable CLI commands for FST testing\n#CONFIG_FST_TEST=y\n\n# OS X builds. This is only for building eapol_test.\n#CONFIG_OSX=y\n\n# Automatic Channel Selection\n# This will allow wpa_supplicant to pick the channel automatically when channel\n# is set to \"0\".\n#\n# TODO: Extend parser to be able to parse \"channel=acs_survey\" as an alternative\n# to \"channel=0\". This would enable us to eventually add other ACS algorithms in\n# similar way.\n#\n# Automatic selection is currently only done through initialization, later on\n# we hope to do background checks to keep us moving to more ideal channels as\n# time goes by. ACS is currently only supported through the nl80211 driver and\n# your driver must have survey dump capability that is filled by the driver\n# during scanning.\n#\n# TODO: In analogy to hostapd be able to customize the ACS survey algorithm with\n# a newly to create wpa_supplicant.conf variable acs_num_scans.\n#\n# Supported ACS drivers:\n# * ath9k\n# * ath5k\n# * ath10k\n#\n# For more details refer to:\n# http://wireless.kernel.org/en/users/Documentation/acs\n#CONFIG_ACS=y\n\n# Support Multi Band Operation\n#CONFIG_MBO=y\n\n# Fast Initial Link Setup (FILS) (IEEE 802.11ai)\n#CONFIG_FILS=y\n# FILS shared key authentication with PFS\n#CONFIG_FILS_SK_PFS=y\n\n# Support RSN on IBSS networks\n# This is needed to be able to use mode=1 network profile with proto=RSN and\n# key_mgmt=WPA-PSK (i.e., full key management instead of WPA-None).\n#CONFIG_IBSS_RSN=y\n\n# External PMKSA cache control\n# This can be used to enable control interface commands that allow the current\n# PMKSA cache entries to be fetched and new entries to be added.\n#CONFIG_PMKSA_CACHE_EXTERNAL=y\n\n# Mesh Networking (IEEE 802.11s)\n#CONFIG_MESH=y\n\n# Background scanning modules\n# These can be used to request wpa_supplicant to perform background scanning\n# operations for roaming within an ESS (same SSID). See the bgscan parameter in\n# the wpa_supplicant.conf file for more details.\n# Periodic background scans based on signal strength\n#CONFIG_BGSCAN_SIMPLE=y\n# Learn channels used by the network and try to avoid bgscans on other\n# channels (experimental)\n#CONFIG_BGSCAN_LEARN=y\n\n# Opportunistic Wireless Encryption (OWE)\n# Experimental implementation of draft-harkins-owe-07.txt\n#CONFIG_OWE=y\n\n# Device Provisioning Protocol (DPP)\n# This requires CONFIG_IEEE80211W=y to be enabled, too. (see\n# wpa_supplicant/README-DPP for details)\n#CONFIG_DPP=y\n\n# uBus IPC/RPC System\n# Services can connect to the bus and provide methods\n# that can be called by other services or clients.\nCONFIG_UBUS=y\n\n# OpenWrt patch 380-disable-ctrl-iface-mib.patch\n# leads to the MIB only being compiled in if\n# CONFIG_CTRL_IFACE_MIB is enabled.\n#CONFIG_CTRL_IFACE_MIB=y\n"
  },
  {
    "path": "package/network/services/hostapd/files/wpa_supplicant-p2p.config",
    "content": "# Example wpa_supplicant build time configuration\n#\n# This file lists the configuration options that are used when building the\n# wpa_supplicant binary. All lines starting with # are ignored. Configuration\n# option lines must be commented out complete, if they are not to be included,\n# i.e., just setting VARIABLE=n is not disabling that variable.\n#\n# This file is included in Makefile, so variables like CFLAGS and LIBS can also\n# be modified from here. In most cases, these lines should use += in order not\n# to override previous values of the variables.\n\n\n# Uncomment following two lines and fix the paths if you have installed OpenSSL\n# or GnuTLS in non-default location\n#CFLAGS += -I/usr/local/openssl/include\n#LIBS += -L/usr/local/openssl/lib\n\n# Some Red Hat versions seem to include kerberos header files from OpenSSL, but\n# the kerberos files are not in the default include path. Following line can be\n# used to fix build issues on such systems (krb5.h not found).\n#CFLAGS += -I/usr/include/kerberos\n\n# Driver interface for generic Linux wireless extensions\n# Note: WEXT is deprecated in the current Linux kernel version and no new\n# functionality is added to it. nl80211-based interface is the new\n# replacement for WEXT and its use allows wpa_supplicant to properly control\n# the driver to improve existing functionality like roaming and to support new\n# functionality.\nCONFIG_DRIVER_WEXT=y\n\n# Driver interface for Linux drivers using the nl80211 kernel interface\nCONFIG_DRIVER_NL80211=y\n\n# QCA vendor extensions to nl80211\n#CONFIG_DRIVER_NL80211_QCA=y\n\n# driver_nl80211.c requires libnl. If you are compiling it yourself\n# you may need to point hostapd to your version of libnl.\n#\n#CFLAGS += -I$<path to libnl include files>\n#LIBS += -L$<path to libnl library files>\n\n# Use libnl v2.0 (or 3.0) libraries.\n#CONFIG_LIBNL20=y\n\n# Use libnl 3.2 libraries (if this is selected, CONFIG_LIBNL20 is ignored)\n#CONFIG_LIBNL32=y\n\n\n# Driver interface for FreeBSD net80211 layer (e.g., Atheros driver)\n#CONFIG_DRIVER_BSD=y\n#CFLAGS += -I/usr/local/include\n#LIBS += -L/usr/local/lib\n#LIBS_p += -L/usr/local/lib\n#LIBS_c += -L/usr/local/lib\n\n# Driver interface for Windows NDIS\n#CONFIG_DRIVER_NDIS=y\n#CFLAGS += -I/usr/include/w32api/ddk\n#LIBS += -L/usr/local/lib\n# For native build using mingw\n#CONFIG_NATIVE_WINDOWS=y\n# Additional directories for cross-compilation on Linux host for mingw target\n#CFLAGS += -I/opt/mingw/mingw32/include/ddk\n#LIBS += -L/opt/mingw/mingw32/lib\n#CC=mingw32-gcc\n# By default, driver_ndis uses WinPcap for low-level operations. This can be\n# replaced with the following option which replaces WinPcap calls with NDISUIO.\n# However, this requires that WZC is disabled (net stop wzcsvc) before starting\n# wpa_supplicant.\n# CONFIG_USE_NDISUIO=y\n\n# Driver interface for wired Ethernet drivers\nCONFIG_DRIVER_WIRED=y\n\n# Driver interface for MACsec capable Qualcomm Atheros drivers\n#CONFIG_DRIVER_MACSEC_QCA=y\n\n# Driver interface for Linux MACsec drivers\n#CONFIG_DRIVER_MACSEC_LINUX=y\n\n# Driver interface for the Broadcom RoboSwitch family\n#CONFIG_DRIVER_ROBOSWITCH=y\n\n# Driver interface for no driver (e.g., WPS ER only)\n#CONFIG_DRIVER_NONE=y\n\n# Solaris libraries\n#LIBS += -lsocket -ldlpi -lnsl\n#LIBS_c += -lsocket\n\n# Enable IEEE 802.1X Supplicant (automatically included if any EAP method or\n# MACsec is included)\nCONFIG_IEEE8021X_EAPOL=y\n\n# EAP-MD5\nCONFIG_EAP_MD5=y\n\n# EAP-MSCHAPv2\nCONFIG_EAP_MSCHAPV2=y\n\n# EAP-TLS\nCONFIG_EAP_TLS=y\n\n# EAL-PEAP\nCONFIG_EAP_PEAP=y\n\n# EAP-TTLS\nCONFIG_EAP_TTLS=y\n\n# EAP-FAST\nCONFIG_EAP_FAST=y\n\n# EAP-TEAP\n# Note: The current EAP-TEAP implementation is experimental and should not be\n# enabled for production use. The IETF RFC 7170 that defines EAP-TEAP has number\n# of conflicting statements and missing details and the implementation has\n# vendor specific workarounds for those and as such, may not interoperate with\n# any other implementation. This should not be used for anything else than\n# experimentation and interoperability testing until those issues has been\n# resolved.\n#CONFIG_EAP_TEAP=y\n\n# EAP-GTC\nCONFIG_EAP_GTC=y\n\n# EAP-OTP\nCONFIG_EAP_OTP=y\n\n# EAP-SIM (enable CONFIG_PCSC, if EAP-SIM is used)\n#CONFIG_EAP_SIM=y\n\n# Enable SIM simulator (Milenage) for EAP-SIM\n#CONFIG_SIM_SIMULATOR=y\n\n# EAP-PSK (experimental; this is _not_ needed for WPA-PSK)\n#CONFIG_EAP_PSK=y\n\n# EAP-pwd (secure authentication using only a password)\n#CONFIG_EAP_PWD=y\n\n# EAP-PAX\n#CONFIG_EAP_PAX=y\n\n# LEAP\nCONFIG_EAP_LEAP=y\n\n# EAP-AKA (enable CONFIG_PCSC, if EAP-AKA is used)\n#CONFIG_EAP_AKA=y\n\n# EAP-AKA' (enable CONFIG_PCSC, if EAP-AKA' is used).\n# This requires CONFIG_EAP_AKA to be enabled, too.\n#CONFIG_EAP_AKA_PRIME=y\n\n# Enable USIM simulator (Milenage) for EAP-AKA\n#CONFIG_USIM_SIMULATOR=y\n\n# EAP-SAKE\n#CONFIG_EAP_SAKE=y\n\n# EAP-GPSK\n#CONFIG_EAP_GPSK=y\n# Include support for optional SHA256 cipher suite in EAP-GPSK\n#CONFIG_EAP_GPSK_SHA256=y\n\n# EAP-TNC and related Trusted Network Connect support (experimental)\n#CONFIG_EAP_TNC=y\n\n# Wi-Fi Protected Setup (WPS)\nCONFIG_WPS=y\n# Enable WPS external registrar functionality\n#CONFIG_WPS_ER=y\n# Disable credentials for an open network by default when acting as a WPS\n# registrar.\n#CONFIG_WPS_REG_DISABLE_OPEN=y\n# Enable WPS support with NFC config method\n#CONFIG_WPS_NFC=y\n\n# EAP-IKEv2\n#CONFIG_EAP_IKEV2=y\n\n# EAP-EKE\n#CONFIG_EAP_EKE=y\n\n# MACsec\n#CONFIG_MACSEC=y\n\n# PKCS#12 (PFX) support (used to read private key and certificate file from\n# a file that usually has extension .p12 or .pfx)\nCONFIG_PKCS12=y\n\n# Smartcard support (i.e., private key on a smartcard), e.g., with openssl\n# engine.\nCONFIG_SMARTCARD=y\n\n# PC/SC interface for smartcards (USIM, GSM SIM)\n# Enable this if EAP-SIM or EAP-AKA is included\n#CONFIG_PCSC=y\n\n# Support HT overrides (disable HT/HT40, mask MCS rates, etc.)\nCONFIG_HT_OVERRIDES=y\n\n# Support VHT overrides (disable VHT, mask MCS rates, etc.)\nCONFIG_VHT_OVERRIDES=y\n\n# Development testing\n#CONFIG_EAPOL_TEST=y\n\n# Select control interface backend for external programs, e.g, wpa_cli:\n# unix = UNIX domain sockets (default for Linux/*BSD)\n# udp = UDP sockets using localhost (127.0.0.1)\n# udp6 = UDP IPv6 sockets using localhost (::1)\n# named_pipe = Windows Named Pipe (default for Windows)\n# udp-remote = UDP sockets with remote access (only for tests systems/purpose)\n# udp6-remote = UDP IPv6 sockets with remote access (only for tests purpose)\n# y = use default (backwards compatibility)\n# If this option is commented out, control interface is not included in the\n# build.\nCONFIG_CTRL_IFACE=y\n\n# Include support for GNU Readline and History Libraries in wpa_cli.\n# When building a wpa_cli binary for distribution, please note that these\n# libraries are licensed under GPL and as such, BSD license may not apply for\n# the resulting binary.\n#CONFIG_READLINE=y\n\n# Include internal line edit mode in wpa_cli. This can be used as a replacement\n# for GNU Readline to provide limited command line editing and history support.\n#CONFIG_WPA_CLI_EDIT=y\n\n# Remove debugging code that is printing out debug message to stdout.\n# This can be used to reduce the size of the wpa_supplicant considerably\n# if debugging code is not needed. The size reduction can be around 35%\n# (e.g., 90 kB).\n#CONFIG_NO_STDOUT_DEBUG=y\n\n# Remove WPA support, e.g., for wired-only IEEE 802.1X supplicant, to save\n# 35-50 kB in code size.\n#CONFIG_NO_WPA=y\n\n# Remove IEEE 802.11i/WPA-Personal ASCII passphrase support\n# This option can be used to reduce code size by removing support for\n# converting ASCII passphrases into PSK. If this functionality is removed, the\n# PSK can only be configured as the 64-octet hexstring (e.g., from\n# wpa_passphrase). This saves about 0.5 kB in code size.\n#CONFIG_NO_WPA_PASSPHRASE=y\n\n# Simultaneous Authentication of Equals (SAE), WPA3-Personal\n#CONFIG_SAE=y\n\n# Disable scan result processing (ap_mode=1) to save code size by about 1 kB.\n# This can be used if ap_scan=1 mode is never enabled.\n#CONFIG_NO_SCAN_PROCESSING=y\n\n# Select configuration backend:\n# file = text file (e.g., wpa_supplicant.conf; note: the configuration file\n#\tpath is given on command line, not here; this option is just used to\n#\tselect the backend that allows configuration files to be used)\n# winreg = Windows registry (see win_example.reg for an example)\nCONFIG_BACKEND=file\n\n# Remove configuration write functionality (i.e., to allow the configuration\n# file to be updated based on runtime configuration changes). The runtime\n# configuration can still be changed, the changes are just not going to be\n# persistent over restarts. This option can be used to reduce code size by\n# about 3.5 kB.\n#CONFIG_NO_CONFIG_WRITE=y\n\n# Remove support for configuration blobs to reduce code size by about 1.5 kB.\n#CONFIG_NO_CONFIG_BLOBS=y\n\n# Select program entry point implementation:\n# main = UNIX/POSIX like main() function (default)\n# main_winsvc = Windows service (read parameters from registry)\n# main_none = Very basic example (development use only)\n#CONFIG_MAIN=main\n\n# Select wrapper for operating system and C library specific functions\n# unix = UNIX/POSIX like systems (default)\n# win32 = Windows systems\n# none = Empty template\n#CONFIG_OS=unix\n\n# Select event loop implementation\n# eloop = select() loop (default)\n# eloop_win = Windows events and WaitForMultipleObject() loop\n#CONFIG_ELOOP=eloop\n\n# Should we use poll instead of select? Select is used by default.\n#CONFIG_ELOOP_POLL=y\n\n# Should we use epoll instead of select? Select is used by default.\nCONFIG_ELOOP_EPOLL=y\n\n# Should we use kqueue instead of select? Select is used by default.\n#CONFIG_ELOOP_KQUEUE=y\n\n# Select layer 2 packet implementation\n# linux = Linux packet socket (default)\n# pcap = libpcap/libdnet/WinPcap\n# freebsd = FreeBSD libpcap\n# winpcap = WinPcap with receive thread\n# ndis = Windows NDISUIO (note: requires CONFIG_USE_NDISUIO=y)\n# none = Empty template\n#CONFIG_L2_PACKET=linux\n\n# Disable Linux packet socket workaround applicable for station interface\n# in a bridge for EAPOL frames. This should be uncommented only if the kernel\n# is known to not have the regression issue in packet socket behavior with\n# bridge interfaces (commit 'bridge: respect RFC2863 operational state')').\nCONFIG_NO_LINUX_PACKET_SOCKET_WAR=y\n\n# IEEE 802.11w (management frame protection), also known as PMF\n# Driver support is also needed for IEEE 802.11w.\nCONFIG_IEEE80211W=y\n\n# Support Operating Channel Validation\n#CONFIG_OCV=y\n\n# Select TLS implementation\n# openssl = OpenSSL (default)\n# gnutls = GnuTLS\n# internal = Internal TLSv1 implementation (experimental)\n# linux = Linux kernel AF_ALG and internal TLSv1 implementation (experimental)\n# none = Empty template\nCONFIG_TLS=internal\n\n# TLS-based EAP methods require at least TLS v1.0. Newer version of TLS (v1.1)\n# can be enabled to get a stronger construction of messages when block ciphers\n# are used. It should be noted that some existing TLS v1.0 -based\n# implementation may not be compatible with TLS v1.1 message (ClientHello is\n# sent prior to negotiating which version will be used)\n#CONFIG_TLSV11=y\n\n# TLS-based EAP methods require at least TLS v1.0. Newer version of TLS (v1.2)\n# can be enabled to enable use of stronger crypto algorithms. It should be\n# noted that some existing TLS v1.0 -based implementation may not be compatible\n# with TLS v1.2 message (ClientHello is sent prior to negotiating which version\n# will be used)\n#CONFIG_TLSV12=y\n\n# Select which ciphers to use by default with OpenSSL if the user does not\n# specify them.\n#CONFIG_TLS_DEFAULT_CIPHERS=\"DEFAULT:!EXP:!LOW\"\n\n# If CONFIG_TLS=internal is used, additional library and include paths are\n# needed for LibTomMath. Alternatively, an integrated, minimal version of\n# LibTomMath can be used. See beginning of libtommath.c for details on benefits\n# and drawbacks of this option.\nCONFIG_INTERNAL_LIBTOMMATH=y\n#ifndef CONFIG_INTERNAL_LIBTOMMATH\n#LTM_PATH=/usr/src/libtommath-0.39\n#CFLAGS += -I$(LTM_PATH)\n#LIBS += -L$(LTM_PATH)\n#LIBS_p += -L$(LTM_PATH)\n#endif\n# At the cost of about 4 kB of additional binary size, the internal LibTomMath\n# can be configured to include faster routines for exptmod, sqr, and div to\n# speed up DH and RSA calculation considerably\nCONFIG_INTERNAL_LIBTOMMATH_FAST=y\n\n# Include NDIS event processing through WMI into wpa_supplicant/wpasvc.\n# This is only for Windows builds and requires WMI-related header files and\n# WbemUuid.Lib from Platform SDK even when building with MinGW.\n#CONFIG_NDIS_EVENTS_INTEGRATED=y\n#PLATFORMSDKLIB=\"/opt/Program Files/Microsoft Platform SDK/Lib\"\n\n# Add support for new DBus control interface\n# (fi.w1.hostap.wpa_supplicant1)\n#CONFIG_CTRL_IFACE_DBUS_NEW=y\n\n# Add introspection support for new DBus control interface\n#CONFIG_CTRL_IFACE_DBUS_INTRO=y\n\n# Add support for loading EAP methods dynamically as shared libraries.\n# When this option is enabled, each EAP method can be either included\n# statically (CONFIG_EAP_<method>=y) or dynamically (CONFIG_EAP_<method>=dyn).\n# Dynamic EAP methods are build as shared objects (eap_*.so) and they need to\n# be loaded in the beginning of the wpa_supplicant configuration file\n# (see load_dynamic_eap parameter in the example file) before being used in\n# the network blocks.\n#\n# Note that some shared parts of EAP methods are included in the main program\n# and in order to be able to use dynamic EAP methods using these parts, the\n# main program must have been build with the EAP method enabled (=y or =dyn).\n# This means that EAP-TLS/PEAP/TTLS/FAST cannot be added as dynamic libraries\n# unless at least one of them was included in the main build to force inclusion\n# of the shared code. Similarly, at least one of EAP-SIM/AKA must be included\n# in the main build to be able to load these methods dynamically.\n#\n# Please also note that using dynamic libraries will increase the total binary\n# size. Thus, it may not be the best option for targets that have limited\n# amount of memory/flash.\n#CONFIG_DYNAMIC_EAP_METHODS=y\n\n# IEEE Std 802.11r-2008 (Fast BSS Transition) for station mode\n#CONFIG_IEEE80211R=y\n\n# Add support for writing debug log to a file (/tmp/wpa_supplicant-log-#.txt)\n#CONFIG_DEBUG_FILE=y\n\n# Send debug messages to syslog instead of stdout\nCONFIG_DEBUG_SYSLOG=y\n# Set syslog facility for debug messages\nCONFIG_DEBUG_SYSLOG_FACILITY=LOG_DAEMON\n\n# Add support for sending all debug messages (regardless of debug verbosity)\n# to the Linux kernel tracing facility. This helps debug the entire stack by\n# making it easy to record everything happening from the driver up into the\n# same file, e.g., using trace-cmd.\n#CONFIG_DEBUG_LINUX_TRACING=y\n\n# Add support for writing debug log to Android logcat instead of standard\n# output\n#CONFIG_ANDROID_LOG=y\n\n# Enable privilege separation (see README 'Privilege separation' for details)\n#CONFIG_PRIVSEP=y\n\n# Enable mitigation against certain attacks against TKIP by delaying Michael\n# MIC error reports by a random amount of time between 0 and 60 seconds\n#CONFIG_DELAYED_MIC_ERROR_REPORT=y\n\n# Enable tracing code for developer debugging\n# This tracks use of memory allocations and other registrations and reports\n# incorrect use with a backtrace of call (or allocation) location.\n#CONFIG_WPA_TRACE=y\n# For BSD, uncomment these.\n#LIBS += -lexecinfo\n#LIBS_p += -lexecinfo\n#LIBS_c += -lexecinfo\n\n# Use libbfd to get more details for developer debugging\n# This enables use of libbfd to get more detailed symbols for the backtraces\n# generated by CONFIG_WPA_TRACE=y.\n#CONFIG_WPA_TRACE_BFD=y\n# For BSD, uncomment these.\n#LIBS += -lbfd -liberty -lz\n#LIBS_p += -lbfd -liberty -lz\n#LIBS_c += -lbfd -liberty -lz\n\n# wpa_supplicant depends on strong random number generation being available\n# from the operating system. os_get_random() function is used to fetch random\n# data when needed, e.g., for key generation. On Linux and BSD systems, this\n# works by reading /dev/urandom. It should be noted that the OS entropy pool\n# needs to be properly initialized before wpa_supplicant is started. This is\n# important especially on embedded devices that do not have a hardware random\n# number generator and may by default start up with minimal entropy available\n# for random number generation.\n#\n# As a safety net, wpa_supplicant is by default trying to internally collect\n# additional entropy for generating random data to mix in with the data fetched\n# from the OS. This by itself is not considered to be very strong, but it may\n# help in cases where the system pool is not initialized properly. However, it\n# is very strongly recommended that the system pool is initialized with enough\n# entropy either by using hardware assisted random number generator or by\n# storing state over device reboots.\n#\n# wpa_supplicant can be configured to maintain its own entropy store over\n# restarts to enhance random number generation. This is not perfect, but it is\n# much more secure than using the same sequence of random numbers after every\n# reboot. This can be enabled with -e<entropy file> command line option. The\n# specified file needs to be readable and writable by wpa_supplicant.\n#\n# If the os_get_random() is known to provide strong random data (e.g., on\n# Linux/BSD, the board in question is known to have reliable source of random\n# data from /dev/urandom), the internal wpa_supplicant random pool can be\n# disabled. This will save some in binary size and CPU use. However, this\n# should only be considered for builds that are known to be used on devices\n# that meet the requirements described above.\nCONFIG_NO_RANDOM_POOL=y\n\n# Should we attempt to use the getrandom(2) call that provides more reliable\n# yet secure randomness source than /dev/random on Linux 3.17 and newer.\n# Requires glibc 2.25 to build, falls back to /dev/random if unavailable.\nCONFIG_GETRANDOM=y\n\n# IEEE 802.11n (High Throughput) support (mainly for AP mode)\n#CONFIG_IEEE80211N=y\n\n# IEEE 802.11ac (Very High Throughput) support (mainly for AP mode)\n# (depends on CONFIG_IEEE80211N)\n#CONFIG_IEEE80211AC=y\n\n# Wireless Network Management (IEEE Std 802.11v-2011)\n# Note: This is experimental and not complete implementation.\n#CONFIG_WNM=y\n\n# Interworking (IEEE 802.11u)\n# This can be used to enable functionality to improve interworking with\n# external networks (GAS/ANQP to learn more about the networks and network\n# selection based on available credentials).\n#CONFIG_INTERWORKING=y\n\n# Hotspot 2.0\n#CONFIG_HS20=y\n\n# Enable interface matching in wpa_supplicant\n#CONFIG_MATCH_IFACE=y\n\n# Disable roaming in wpa_supplicant\n#CONFIG_NO_ROAMING=y\n\n# AP mode operations with wpa_supplicant\n# This can be used for controlling AP mode operations with wpa_supplicant. It\n# should be noted that this is mainly aimed at simple cases like\n# WPA2-Personal while more complex configurations like WPA2-Enterprise with an\n# external RADIUS server can be supported with hostapd.\nCONFIG_AP=y\n\n# P2P (Wi-Fi Direct)\n# This can be used to enable P2P support in wpa_supplicant. See README-P2P for\n# more information on P2P operations.\nCONFIG_P2P=y\n\n# Enable TDLS support\n#CONFIG_TDLS=y\n\n# Wi-Fi Display\n# This can be used to enable Wi-Fi Display extensions for P2P using an external\n# program to control the additional information exchanges in the messages.\n#CONFIG_WIFI_DISPLAY=y\n\n# Autoscan\n# This can be used to enable automatic scan support in wpa_supplicant.\n# See wpa_supplicant.conf for more information on autoscan usage.\n#\n# Enabling directly a module will enable autoscan support.\n# For exponential module:\n#CONFIG_AUTOSCAN_EXPONENTIAL=y\n# For periodic module:\n#CONFIG_AUTOSCAN_PERIODIC=y\n\n# Password (and passphrase, etc.) backend for external storage\n# These optional mechanisms can be used to add support for storing passwords\n# and other secrets in external (to wpa_supplicant) location. This allows, for\n# example, operating system specific key storage to be used\n#\n# External password backend for testing purposes (developer use)\n#CONFIG_EXT_PASSWORD_TEST=y\n\n# Enable Fast Session Transfer (FST)\n#CONFIG_FST=y\n\n# Enable CLI commands for FST testing\n#CONFIG_FST_TEST=y\n\n# OS X builds. This is only for building eapol_test.\n#CONFIG_OSX=y\n\n# Automatic Channel Selection\n# This will allow wpa_supplicant to pick the channel automatically when channel\n# is set to \"0\".\n#\n# TODO: Extend parser to be able to parse \"channel=acs_survey\" as an alternative\n# to \"channel=0\". This would enable us to eventually add other ACS algorithms in\n# similar way.\n#\n# Automatic selection is currently only done through initialization, later on\n# we hope to do background checks to keep us moving to more ideal channels as\n# time goes by. ACS is currently only supported through the nl80211 driver and\n# your driver must have survey dump capability that is filled by the driver\n# during scanning.\n#\n# TODO: In analogy to hostapd be able to customize the ACS survey algorithm with\n# a newly to create wpa_supplicant.conf variable acs_num_scans.\n#\n# Supported ACS drivers:\n# * ath9k\n# * ath5k\n# * ath10k\n#\n# For more details refer to:\n# http://wireless.kernel.org/en/users/Documentation/acs\n#CONFIG_ACS=y\n\n# Support Multi Band Operation\n#CONFIG_MBO=y\n\n# Fast Initial Link Setup (FILS) (IEEE 802.11ai)\nCONFIG_FILS=y\n# FILS shared key authentication with PFS\n#CONFIG_FILS_SK_PFS=y\n\n# Support RSN on IBSS networks\n# This is needed to be able to use mode=1 network profile with proto=RSN and\n# key_mgmt=WPA-PSK (i.e., full key management instead of WPA-None).\nCONFIG_IBSS_RSN=y\n\n# External PMKSA cache control\n# This can be used to enable control interface commands that allow the current\n# PMKSA cache entries to be fetched and new entries to be added.\n#CONFIG_PMKSA_CACHE_EXTERNAL=y\n\n# Mesh Networking (IEEE 802.11s)\n#CONFIG_MESH=y\n\n# Background scanning modules\n# These can be used to request wpa_supplicant to perform background scanning\n# operations for roaming within an ESS (same SSID). See the bgscan parameter in\n# the wpa_supplicant.conf file for more details.\n# Periodic background scans based on signal strength\n#CONFIG_BGSCAN_SIMPLE=y\n# Learn channels used by the network and try to avoid bgscans on other\n# channels (experimental)\n#CONFIG_BGSCAN_LEARN=y\n\n# Opportunistic Wireless Encryption (OWE)\n# Experimental implementation of draft-harkins-owe-07.txt\n#CONFIG_OWE=y\n\n# Device Provisioning Protocol (DPP)\n# This requires CONFIG_IEEE80211W=y to be enabled, too. (see\n# wpa_supplicant/README-DPP for details)\n#CONFIG_DPP=y\n\n# uBus IPC/RPC System\n# Services can connect to the bus and provide methods\n# that can be called by other services or clients.\nCONFIG_UBUS=y\n\n# OpenWrt patch 380-disable-ctrl-iface-mib.patch\n# leads to the MIB only being compiled in if\n# CONFIG_CTRL_IFACE_MIB is enabled.\n#CONFIG_CTRL_IFACE_MIB=y\n"
  },
  {
    "path": "package/network/services/hostapd/files/wpad.init",
    "content": "#!/bin/sh /etc/rc.common\n\nSTART=19\nSTOP=21\n\nUSE_PROCD=1\nNAME=wpad\n\nstart_service() {\n\tif [ -x \"/usr/sbin/hostapd\" ]; then\n\t\tmkdir -p /var/run/hostapd\n\t\tchown network:network /var/run/hostapd\n\t\tprocd_open_instance hostapd\n\t\tprocd_set_param command /usr/sbin/hostapd -s -g /var/run/hostapd/global\n\t\tprocd_set_param respawn 3600 1 0\n\t\t[ -x /sbin/ujail -a -e /etc/capabilities/wpad.json ] && {\n\t\t\tprocd_add_jail hostapd\n\t\t\tprocd_set_param capabilities /etc/capabilities/wpad.json\n\t\t\tprocd_set_param user network\n\t\t\tprocd_set_param group network\n\t\t\tprocd_set_param no_new_privs 1\n\t\t}\n\t\tprocd_close_instance\n\tfi\n\n\tif [ -x \"/usr/sbin/wpa_supplicant\" ]; then\n\t\tmkdir -p /var/run/wpa_supplicant\n\t\tchown network:network /var/run/wpa_supplicant\n\t\tprocd_open_instance supplicant\n\t\tprocd_set_param command /usr/sbin/wpa_supplicant -n -s -g /var/run/wpa_supplicant/global\n\t\tprocd_set_param respawn 3600 1 0\n\t\t[ -x /sbin/ujail -a -e /etc/capabilities/wpad.json ] && {\n\t\t\tprocd_add_jail wpa_supplicant\n\t\t\tprocd_set_param capabilities /etc/capabilities/wpad.json\n\t\t\tprocd_set_param user network\n\t\t\tprocd_set_param group network\n\t\t\tprocd_set_param no_new_privs 1\n\t\t}\n\t\tprocd_close_instance\n\tfi\n}\n"
  },
  {
    "path": "package/network/services/hostapd/files/wpad.json",
    "content": "{\n\t\"bounding\": [\n\t\t\"CAP_NET_ADMIN\",\n\t\t\"CAP_NET_RAW\"\n\t],\n\t\"effective\": [\n\t\t\"CAP_NET_ADMIN\",\n\t\t\"CAP_NET_RAW\"\n\t],\n\t\"ambient\": [\n\t\t\"CAP_NET_ADMIN\",\n\t\t\"CAP_NET_RAW\"\n\t],\n\t\"permitted\": [\n\t\t\"CAP_NET_ADMIN\",\n\t\t\"CAP_NET_RAW\"\n\t],\n\t\"inheritable\": [\n\t\t\"CAP_NET_ADMIN\",\n\t\t\"CAP_NET_RAW\"\n\t]\n}\n"
  },
  {
    "path": "package/network/services/hostapd/files/wpad_acl.json",
    "content": "{\n\t\"user\": \"network\",\n\t\"access\": {\n\t\t\"service\": {\n\t\t\t\"methods\": [ \"event\" ]\n\t\t}\n\t},\n\t\"publish\": [ \"hostapd\", \"hostapd.*\", \"wpa_supplicant\", \"wpa_supplicant.*\" ],\n\t\"send\": [ \"bss.*\", \"wps_credentials\" ]\n}\n"
  },
  {
    "path": "package/network/services/hostapd/files/wps-hotplug.sh",
    "content": "#!/bin/sh\n\nwps_catch_credentials() {\n\tlocal iface ifaces ifc ifname ssid encryption key radio radios\n\tlocal found=0\n\n\t. /usr/share/libubox/jshn.sh\n\tubus -S -t 30 listen wps_credentials | while read creds; do\n\t\tjson_init\n\t\tjson_load \"$creds\"\n\t\tjson_select wps_credentials || continue\n\t\tjson_get_vars ifname ssid key encryption\n\t\tlocal ifcname=\"$ifname\"\n\t\tjson_init\n\t\tjson_load \"$(ubus -S call network.wireless status)\"\n\t\tjson_get_keys radios\n\t\tfor radio in $radios; do\n\t\t\tjson_select $radio\n\t\t\tjson_select interfaces\n\t\t\tjson_get_keys ifaces\n\t\t\tfor ifc in $ifaces; do\n\t\t\t\tjson_select $ifc\n\t\t\t\tjson_get_vars ifname\n\t\t\t\t[ \"$ifname\" = \"$ifcname\" ] && {\n\t\t\t\t\tubus -S call uci set \"{\\\"config\\\":\\\"wireless\\\", \\\"type\\\":\\\"wifi-iface\\\",\t\t\\\n\t\t\t\t\t\t\t\t\\\"match\\\": { \\\"device\\\": \\\"$radio\\\", \\\"encryption\\\": \\\"wps\\\" },\t\\\n\t\t\t\t\t\t\t\t\\\"values\\\": { \\\"encryption\\\": \\\"$encryption\\\", \t\t\t\\\n\t\t\t\t\t\t\t\t\t\t\\\"ssid\\\": \\\"$ssid\\\", \t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\t\\\"key\\\": \\\"$key\\\" } }\"\n\t\t\t\t\tubus -S call uci commit '{\"config\": \"wireless\"}'\n\t\t\t\t\tubus -S call uci apply\n\t\t\t\t}\n\t\t\t\tjson_select ..\n\t\t\tdone\n\t\t\tjson_select ..\n\t\t\tjson_select ..\n\t\tdone\n\tdone\n}\n\nif [ \"$ACTION\" = \"released\" ] && [ \"$BUTTON\" = \"wps\" ]; then\n\t# If the button was pressed for 3 seconds or more, trigger WPS on\n\t# wpa_supplicant only, no matter if hostapd is running or not.  If\n\t# was pressed for less than 3 seconds, try triggering on\n\t# hostapd. If there is no hostapd instance to trigger it on or WPS\n\t# is not enabled on them, trigger it on wpa_supplicant.\n\tif [ \"$SEEN\" -lt 3 ] ; then\n\t\twps_done=0\n\t\tubusobjs=\"$( ubus -S list hostapd.* )\"\n\t\tfor ubusobj in $ubusobjs; do\n\t\t\tubus -S call $ubusobj wps_start && wps_done=1\n\t\tdone\n\t\t[ $wps_done = 0 ] || return 0\n\tfi\n\twps_done=0\n\tubusobjs=\"$( ubus -S list wpa_supplicant.* )\"\n\tfor ubusobj in $ubusobjs; do\n\t\tifname=\"$(echo $ubusobj | cut -d'.' -f2 )\"\n\t\tmulti_ap=\"\"\n\t\tif [ -e \"/var/run/wpa_supplicant-${ifname}.conf.is_multiap\" ]; then\n\t\t\tubus -S call $ubusobj wps_start '{ \"multi_ap\": true }' && wps_done=1\n\t\telse\n\t\t\tubus -S call $ubusobj wps_start && wps_done=1\n\t\tfi\n\tdone\n\t[ $wps_done = 0 ] || wps_catch_credentials &\nfi\n\nreturn 0\n"
  },
  {
    "path": "package/network/services/hostapd/patches/001-wolfssl-init-RNG-with-ECC-key.patch",
    "content": "From 21ce83b4ae2b9563175fdb4fc4312096cc399cf8 Mon Sep 17 00:00:00 2001\nFrom: David Bauer <mail@david-bauer.net>\nDate: Wed, 5 May 2021 00:44:34 +0200\nSubject: [PATCH] wolfssl: add RNG to EC key\n\nSince upstream commit 6467de5a8840 (\"Randomize z ordinates in\nscalar mult when timing resistant\") WolfSSL requires a RNG for\nthe EC key when built hardened which is the default.\n\nSet the RNG for the EC key to fix connections for OWE clients.\n\nSigned-off-by: David Bauer <mail@david-bauer.net>\n---\n src/crypto/crypto_wolfssl.c | 4 ++++\n 1 file changed, 4 insertions(+)\n\n--- a/src/crypto/crypto_wolfssl.c\n+++ b/src/crypto/crypto_wolfssl.c\n@@ -1307,6 +1307,7 @@ int ecc_projective_add_point(ecc_point *\n \n struct crypto_ec {\n \tecc_key key;\n+\tWC_RNG rng;\n \tmp_int a;\n \tmp_int prime;\n \tmp_int order;\n@@ -1361,6 +1362,8 @@ struct crypto_ec * crypto_ec_init(int gr\n \t\treturn NULL;\n \n \tif (wc_ecc_init(&e->key) != 0 ||\n+\t    wc_InitRng(&e->rng) != 0 ||\n+\t    wc_ecc_set_rng(&e->key, &e->rng) != 0 ||\n \t    wc_ecc_set_curve(&e->key, 0, curve_id) != 0 ||\n \t    mp_init(&e->a) != MP_OKAY ||\n \t    mp_init(&e->prime) != MP_OKAY ||\n@@ -1392,6 +1395,7 @@ void crypto_ec_deinit(struct crypto_ec*\n \tmp_clear(&e->order);\n \tmp_clear(&e->prime);\n \tmp_clear(&e->a);\n+\twc_FreeRng(&e->rng);\n \twc_ecc_free(&e->key);\n \tos_free(e);\n }\n"
  },
  {
    "path": "package/network/services/hostapd/patches/010-mesh-Allow-DFS-channels-to-be-selected-if-dfs-is-ena.patch",
    "content": "From 8de8cd8380af0c43d4fde67a668d79ef73b26b26 Mon Sep 17 00:00:00 2001\nFrom: Peter Oh <peter.oh@bowerswilkins.com>\nDate: Tue, 30 Jun 2020 14:18:58 +0200\nSubject: [PATCH 10/19] mesh: Allow DFS channels to be selected if dfs is\n enabled\n\nNote: DFS is assumed to be usable if a country code has been set\n\nSigned-off-by: Benjamin Berg <benjamin@sipsolutions.net>\nSigned-off-by: Peter Oh <peter.oh@bowerswilkins.com>\n---\n wpa_supplicant/wpa_supplicant.c | 25 +++++++++++++++++++------\n 1 file changed, 19 insertions(+), 6 deletions(-)\n\n--- a/wpa_supplicant/wpa_supplicant.c\n+++ b/wpa_supplicant/wpa_supplicant.c\n@@ -2409,7 +2409,7 @@ static int drv_supports_vht(struct wpa_s\n }\n \n \n-static bool ibss_mesh_is_80mhz_avail(int channel, struct hostapd_hw_modes *mode)\n+static bool ibss_mesh_is_80mhz_avail(int channel, struct hostapd_hw_modes *mode, bool dfs_enabled)\n {\n \tint i;\n \n@@ -2418,7 +2418,10 @@ static bool ibss_mesh_is_80mhz_avail(int\n \n \t\tchan = hw_get_channel_chan(mode, i, NULL);\n \t\tif (!chan ||\n-\t\t    chan->flag & (HOSTAPD_CHAN_DISABLED | HOSTAPD_CHAN_NO_IR))\n+\t\t    chan->flag & HOSTAPD_CHAN_DISABLED)\n+\t\t\treturn false;\n+\t\t\n+\t\tif (!dfs_enabled && chan->flag & (HOSTAPD_CHAN_RADAR | HOSTAPD_CHAN_NO_IR))\n \t\t\treturn false;\n \t}\n \n@@ -2447,6 +2450,8 @@ void ibss_mesh_setup_freq(struct wpa_sup\n \tint chwidth, seg0, seg1;\n \tu32 vht_caps = 0;\n \tbool is_24ghz, is_6ghz;\n+\tbool dfs_enabled = wpa_s->conf->country[0] &&\n+\t\t\t   (wpa_s->drv_flags & WPA_DRIVER_FLAGS_RADAR);\n \n \tfreq->freq = ssid->frequency;\n \n@@ -2543,8 +2548,11 @@ void ibss_mesh_setup_freq(struct wpa_sup\n \t\treturn;\n \n \t/* Check primary channel flags */\n-\tif (pri_chan->flag & (HOSTAPD_CHAN_DISABLED | HOSTAPD_CHAN_NO_IR))\n+\tif (pri_chan->flag & HOSTAPD_CHAN_DISABLED)\n \t\treturn;\n+\tif (pri_chan->flag & (HOSTAPD_CHAN_RADAR | HOSTAPD_CHAN_NO_IR))\n+\t\tif (!dfs_enabled)\n+\t\t\treturn;\n \n \tfreq->channel = pri_chan->chan;\n \n@@ -2577,8 +2585,11 @@ void ibss_mesh_setup_freq(struct wpa_sup\n \t\treturn;\n \n \t/* Check secondary channel flags */\n-\tif (sec_chan->flag & (HOSTAPD_CHAN_DISABLED | HOSTAPD_CHAN_NO_IR))\n+\tif (sec_chan->flag & HOSTAPD_CHAN_DISABLED)\n \t\treturn;\n+\tif (sec_chan->flag & (HOSTAPD_CHAN_RADAR | HOSTAPD_CHAN_NO_IR))\n+\t\tif (!dfs_enabled)\n+\t\t\treturn;\n \n \tif (ht40 == -1) {\n \t\tif (!(pri_chan->flag & HOSTAPD_CHAN_HT40MINUS))\n@@ -2667,7 +2678,7 @@ skip_to_6ghz:\n \t\treturn;\n \n \t/* Back to HT configuration if channel not usable */\n-\tif (!ibss_mesh_is_80mhz_avail(channel, mode))\n+\tif (!ibss_mesh_is_80mhz_avail(channel, mode, dfs_enabled))\n \t\treturn;\n \n \tchwidth = CHANWIDTH_80MHZ;\n@@ -2681,7 +2692,7 @@ skip_to_6ghz:\n \t\t * above; check the remaining four 20 MHz channels for the total\n \t\t * of 160 MHz bandwidth.\n \t\t */\n-\t\tif (!ibss_mesh_is_80mhz_avail(channel + 16, mode))\n+\t\tif (!ibss_mesh_is_80mhz_avail(channel + 16, mode, dfs_enabled))\n \t\t\treturn;\n \n \t\tfor (j = 0; j < ARRAY_SIZE(bw160); j++) {\n@@ -2711,10 +2722,12 @@ skip_to_6ghz:\n \t\t\t\tif (!chan)\n \t\t\t\t\tcontinue;\n \n-\t\t\t\tif (chan->flag & (HOSTAPD_CHAN_DISABLED |\n-\t\t\t\t\t\t  HOSTAPD_CHAN_NO_IR |\n-\t\t\t\t\t\t  HOSTAPD_CHAN_RADAR))\n+\t\t\t\tif (chan->flag & HOSTAPD_CHAN_DISABLED)\n \t\t\t\t\tcontinue;\n+\t\t\t\tif (chan->flag & (HOSTAPD_CHAN_RADAR |\n+\t\t\t\t\t\t  HOSTAPD_CHAN_NO_IR))\n+\t\t\t\t\tif (!dfs_enabled)\n+\t\t\t\t\t\tcontinue;\n \n \t\t\t\t/* Found a suitable second segment for 80+80 */\n \t\t\t\tchwidth = CHANWIDTH_80P80MHZ;\n"
  },
  {
    "path": "package/network/services/hostapd/patches/011-mesh-use-deterministic-channel-on-channel-switch.patch",
    "content": "From fc8ea40f6130ac18d9c66797de2cf1d5af55d496 Mon Sep 17 00:00:00 2001\nFrom: Markus Theil <markus.theil@tu-ilmenau.de>\nDate: Tue, 30 Jun 2020 14:19:07 +0200\nSubject: [PATCH 19/19] mesh: use deterministic channel on channel switch\n\nThis patch uses a deterministic channel on DFS channel switch\nin mesh networks. Otherwise, when switching to a usable but not\navailable channel, no CSA can be sent and a random channel is choosen\nwithout notification of other nodes. It is then quite likely, that\nthe mesh network gets disconnected.\n\nFix this by using a deterministic number, based on the sha256 hash\nof the mesh ID, in order to use at least a different number in each\nmesh network.\n\nSigned-off-by: Markus Theil <markus.theil@tu-ilmenau.de>\n---\n src/ap/dfs.c                 | 20 +++++++++++++++++++-\n src/drivers/driver_nl80211.c |  4 ++++\n 2 files changed, 23 insertions(+), 1 deletion(-)\n\n--- a/src/ap/dfs.c\n+++ b/src/ap/dfs.c\n@@ -17,6 +17,7 @@\n #include \"ap_drv_ops.h\"\n #include \"drivers/driver.h\"\n #include \"dfs.h\"\n+#include \"crypto/crypto.h\"\n \n \n static int dfs_get_used_n_chans(struct hostapd_iface *iface, int *seg1)\n@@ -483,9 +484,14 @@ dfs_get_valid_channel(struct hostapd_ifa\n \tint num_available_chandefs;\n \tint chan_idx, chan_idx2;\n \tint sec_chan_idx_80p80 = -1;\n+\tbool is_mesh = false;\n \tint i;\n \tu32 _rand;\n \n+#ifdef CONFIG_MESH\n+\tis_mesh = iface->mconf;\n+#endif\n+\n \twpa_printf(MSG_DEBUG, \"DFS: Selecting random channel\");\n \t*secondary_channel = 0;\n \t*oper_centr_freq_seg0_idx = 0;\n@@ -505,8 +511,20 @@ dfs_get_valid_channel(struct hostapd_ifa\n \tif (num_available_chandefs == 0)\n \t\treturn NULL;\n \n-\tif (os_get_random((u8 *) &_rand, sizeof(_rand)) < 0)\n+\t/* try to use deterministic channel in mesh, so that both sides\n+\t * have a chance to switch to the same channel */\n+\tif (is_mesh) {\n+#ifdef CONFIG_MESH\n+\t\tu64 hash[4];\n+\t\tconst u8 *meshid[1] = { &iface->mconf->meshid[0] };\n+\t\tconst size_t meshid_len = iface->mconf->meshid_len;\n+\n+\t\tsha256_vector(1, meshid, &meshid_len, (u8 *)&hash[0]);\n+\t\t_rand = hash[0] + hash[1] + hash[2] + hash[3];\n+#endif\n+\t} else if (os_get_random((u8 *) &_rand, sizeof(_rand)) < 0)\n \t\treturn NULL;\n+\n \tchan_idx = _rand % num_available_chandefs;\n \tdfs_find_channel(iface, &chan, chan_idx, skip_radar);\n \tif (!chan) {\n--- a/src/drivers/driver_nl80211.c\n+++ b/src/drivers/driver_nl80211.c\n@@ -9895,6 +9895,10 @@ static int nl80211_switch_channel(void *\n \tif (ret)\n \t\tgoto error;\n \n+\tif (drv->nlmode == NL80211_IFTYPE_MESH_POINT) {\n+\t\tnla_put_flag(msg, NL80211_ATTR_HANDLE_DFS);\n+\t}\n+\n \t/* beacon_csa params */\n \tbeacon_csa = nla_nest_start(msg, NL80211_ATTR_CSA_IES);\n \tif (!beacon_csa)\n"
  },
  {
    "path": "package/network/services/hostapd/patches/021-fix-sta-add-after-previous-connection.patch",
    "content": "--- a/src/ap/ieee802_11.c\n+++ b/src/ap/ieee802_11.c\n@@ -4944,6 +4944,13 @@ static int add_associated_sta(struct hos\n \t * drivers to accept the STA parameter configuration. Since this is\n \t * after a new FT-over-DS exchange, a new TK has been derived, so key\n \t * reinstallation is not a concern for this case.\n+\t *\n+\t * If the STA was associated and authorized earlier, but came for a new\n+\t * connection (!added_unassoc + !reassoc), remove the existing STA entry\n+\t * so that it can be re-added. This case is rarely seen when the AP could\n+\t * not receive the deauth/disassoc frame from the STA. And the STA comes\n+\t * back with new connection within a short period or before the inactive\n+\t * STA entry is removed from the list.\n \t */\n \twpa_printf(MSG_DEBUG, \"Add associated STA \" MACSTR\n \t\t   \" (added_unassoc=%d auth_alg=%u ft_over_ds=%u reassoc=%d authorized=%d ft_tk=%d fils_tk=%d)\",\n@@ -4957,7 +4964,8 @@ static int add_associated_sta(struct hos\n \t    (!(sta->flags & WLAN_STA_AUTHORIZED) ||\n \t     (reassoc && sta->ft_over_ds && sta->auth_alg == WLAN_AUTH_FT) ||\n \t     (!wpa_auth_sta_ft_tk_already_set(sta->wpa_sm) &&\n-\t      !wpa_auth_sta_fils_tk_already_set(sta->wpa_sm)))) {\n+\t      !wpa_auth_sta_fils_tk_already_set(sta->wpa_sm)) ||\n+\t     (!reassoc && (sta->flags & WLAN_STA_AUTHORIZED)))) {\n \t\thostapd_drv_sta_remove(hapd, sta->addr);\n \t\twpa_auth_sm_event(sta->wpa_sm, WPA_DRV_STA_REMOVED);\n \t\tset = 0;\n"
  },
  {
    "path": "package/network/services/hostapd/patches/022-hostapd-fix-use-of-uninitialized-stack-variables.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nDate: Thu, 8 Jul 2021 16:33:03 +0200\nSubject: [PATCH] hostapd: fix use of uninitialized stack variables\n\nWhen a CSA is performed on an 80 MHz channel, hostapd_change_config_freq\nunconditionally calls hostapd_set_oper_centr_freq_seg0/1_idx with seg0/1\nfilled by ieee80211_freq_to_chan.\nHowever, if ieee80211_freq_to_chan fails (because the freq is 0 or invalid),\nseg0/1 remains uninitialized and filled with stack garbage, causing errors\nsuch as \"hostapd: 80 MHz: center segment 1 configured\"\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n\n--- a/src/ap/hostapd.c\n+++ b/src/ap/hostapd.c\n@@ -3431,7 +3431,7 @@ static int hostapd_change_config_freq(st\n \t\t\t\t      struct hostapd_freq_params *old_params)\n {\n \tint channel;\n-\tu8 seg0, seg1;\n+\tu8 seg0 = 0, seg1 = 0;\n \tstruct hostapd_hw_modes *mode;\n \n \tif (!params->channel) {\n"
  },
  {
    "path": "package/network/services/hostapd/patches/023-ndisc_snoop-call-dl_list_del-before-freeing-ipv6-add.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nDate: Wed, 28 Jul 2021 05:43:29 +0200\nSubject: [PATCH] ndisc_snoop: call dl_list_del before freeing ipv6 addresses\n\nFixes a segmentation fault on sta disconnect\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n\n--- a/src/ap/ndisc_snoop.c\n+++ b/src/ap/ndisc_snoop.c\n@@ -61,6 +61,7 @@ void sta_ip6addr_del(struct hostapd_data\n \tdl_list_for_each_safe(ip6addr, prev, &sta->ip6addr, struct ip6addr,\n \t\t\t      list) {\n \t\thostapd_drv_br_delete_ip_neigh(hapd, 6, (u8 *) &ip6addr->addr);\n+\t\tdl_list_del(&ip6addr->list);\n \t\tos_free(ip6addr);\n \t}\n }\n"
  },
  {
    "path": "package/network/services/hostapd/patches/030-driver_nl80211-rewrite-neigh-code-to-not-depend-on-l.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nDate: Wed, 28 Jul 2021 05:49:46 +0200\nSubject: [PATCH] driver_nl80211: rewrite neigh code to not depend on\n libnl3-route\n\nRemoves an unnecessary dependency and also makes the code smaller\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n\n--- a/src/drivers/driver_nl80211.c\n+++ b/src/drivers/driver_nl80211.c\n@@ -16,9 +16,6 @@\n #include <net/if.h>\n #include <netlink/genl/genl.h>\n #include <netlink/genl/ctrl.h>\n-#ifdef CONFIG_LIBNL3_ROUTE\n-#include <netlink/route/neighbour.h>\n-#endif /* CONFIG_LIBNL3_ROUTE */\n #include <linux/rtnetlink.h>\n #include <netpacket/packet.h>\n #include <linux/errqueue.h>\n@@ -5300,26 +5297,29 @@ fail:\n \n static void rtnl_neigh_delete_fdb_entry(struct i802_bss *bss, const u8 *addr)\n {\n-#ifdef CONFIG_LIBNL3_ROUTE\n \tstruct wpa_driver_nl80211_data *drv = bss->drv;\n-\tstruct rtnl_neigh *rn;\n-\tstruct nl_addr *nl_addr;\n+\tstruct ndmsg nhdr = {\n+\t\t.ndm_state = NUD_PERMANENT,\n+\t\t.ndm_ifindex = bss->ifindex,\n+\t\t.ndm_family = AF_BRIDGE,\n+\t};\n+\tstruct nl_msg *msg;\n \tint err;\n \n-\trn = rtnl_neigh_alloc();\n-\tif (!rn)\n+\tmsg = nlmsg_alloc_simple(RTM_DELNEIGH, NLM_F_CREATE);\n+\tif (!msg)\n \t\treturn;\n \n-\trtnl_neigh_set_family(rn, AF_BRIDGE);\n-\trtnl_neigh_set_ifindex(rn, bss->ifindex);\n-\tnl_addr = nl_addr_build(AF_BRIDGE, (void *) addr, ETH_ALEN);\n-\tif (!nl_addr) {\n-\t\trtnl_neigh_put(rn);\n-\t\treturn;\n-\t}\n-\trtnl_neigh_set_lladdr(rn, nl_addr);\n+\tif (nlmsg_append(msg, &nhdr, sizeof(nhdr), NLMSG_ALIGNTO) < 0)\n+\t\tgoto errout;\n+\n+\tif (nla_put(msg, NDA_LLADDR, ETH_ALEN, (void *)addr))\n+\t\tgoto errout;\n+\n+\tif (nl_send_auto_complete(drv->rtnl_sk, msg) < 0)\n+\t\tgoto errout;\n \n-\terr = rtnl_neigh_delete(drv->rtnl_sk, rn, 0);\n+\terr = nl_wait_for_ack(drv->rtnl_sk);\n \tif (err < 0) {\n \t\twpa_printf(MSG_DEBUG, \"nl80211: bridge FDB entry delete for \"\n \t\t\t   MACSTR \" ifindex=%d failed: %s\", MAC2STR(addr),\n@@ -5329,9 +5329,8 @@ static void rtnl_neigh_delete_fdb_entry(\n \t\t\t   MACSTR, MAC2STR(addr));\n \t}\n \n-\tnl_addr_put(nl_addr);\n-\trtnl_neigh_put(rn);\n-#endif /* CONFIG_LIBNL3_ROUTE */\n+errout:\n+\tnlmsg_free(msg);\n }\n \n \n@@ -7714,7 +7713,6 @@ static void *i802_init(struct hostapd_da\n \t    (params->num_bridge == 0 || !params->bridge[0]))\n \t\tadd_ifidx(drv, br_ifindex, drv->ifindex);\n \n-#ifdef CONFIG_LIBNL3_ROUTE\n \tif (bss->added_if_into_bridge || bss->already_in_bridge) {\n \t\tint err;\n \n@@ -7731,7 +7729,6 @@ static void *i802_init(struct hostapd_da\n \t\t\tgoto failed;\n \t\t}\n \t}\n-#endif /* CONFIG_LIBNL3_ROUTE */\n \n \tif (drv->capa.flags2 & WPA_DRIVER_FLAGS2_CONTROL_PORT_RX) {\n \t\twpa_printf(MSG_DEBUG,\n@@ -10678,13 +10675,14 @@ static int wpa_driver_br_add_ip_neigh(vo\n \t\t\t\t      const u8 *ipaddr, int prefixlen,\n \t\t\t\t      const u8 *addr)\n {\n-#ifdef CONFIG_LIBNL3_ROUTE\n \tstruct i802_bss *bss = priv;\n \tstruct wpa_driver_nl80211_data *drv = bss->drv;\n-\tstruct rtnl_neigh *rn;\n-\tstruct nl_addr *nl_ipaddr = NULL;\n-\tstruct nl_addr *nl_lladdr = NULL;\n-\tint family, addrsize;\n+\tstruct ndmsg nhdr = {\n+\t\t.ndm_state = NUD_PERMANENT,\n+\t\t.ndm_ifindex = bss->br_ifindex,\n+\t};\n+\tstruct nl_msg *msg;\n+\tint addrsize;\n \tint res;\n \n \tif (!ipaddr || prefixlen == 0 || !addr)\n@@ -10703,85 +10701,66 @@ static int wpa_driver_br_add_ip_neigh(vo\n \t}\n \n \tif (version == 4) {\n-\t\tfamily = AF_INET;\n+\t\tnhdr.ndm_family = AF_INET;\n \t\taddrsize = 4;\n \t} else if (version == 6) {\n-\t\tfamily = AF_INET6;\n+\t\tnhdr.ndm_family = AF_INET6;\n \t\taddrsize = 16;\n \t} else {\n \t\treturn -EINVAL;\n \t}\n \n-\trn = rtnl_neigh_alloc();\n-\tif (rn == NULL)\n+\tmsg = nlmsg_alloc_simple(RTM_NEWNEIGH, NLM_F_CREATE);\n+\tif (!msg)\n \t\treturn -ENOMEM;\n \n-\t/* set the destination ip address for neigh */\n-\tnl_ipaddr = nl_addr_build(family, (void *) ipaddr, addrsize);\n-\tif (nl_ipaddr == NULL) {\n-\t\twpa_printf(MSG_DEBUG, \"nl80211: nl_ipaddr build failed\");\n-\t\tres = -ENOMEM;\n+\tres = -ENOMEM;\n+\tif (nlmsg_append(msg, &nhdr, sizeof(nhdr), NLMSG_ALIGNTO) < 0)\n \t\tgoto errout;\n-\t}\n-\tnl_addr_set_prefixlen(nl_ipaddr, prefixlen);\n-\tres = rtnl_neigh_set_dst(rn, nl_ipaddr);\n-\tif (res) {\n-\t\twpa_printf(MSG_DEBUG,\n-\t\t\t   \"nl80211: neigh set destination addr failed\");\n+\n+\tif (nla_put(msg, NDA_DST, addrsize, (void *)ipaddr))\n \t\tgoto errout;\n-\t}\n \n-\t/* set the corresponding lladdr for neigh */\n-\tnl_lladdr = nl_addr_build(AF_BRIDGE, (u8 *) addr, ETH_ALEN);\n-\tif (nl_lladdr == NULL) {\n-\t\twpa_printf(MSG_DEBUG, \"nl80211: neigh set lladdr failed\");\n-\t\tres = -ENOMEM;\n+\tif (nla_put(msg, NDA_LLADDR, ETH_ALEN, (void *)addr))\n \t\tgoto errout;\n-\t}\n-\trtnl_neigh_set_lladdr(rn, nl_lladdr);\n \n-\trtnl_neigh_set_ifindex(rn, bss->br_ifindex);\n-\trtnl_neigh_set_state(rn, NUD_PERMANENT);\n+\tres = nl_send_auto_complete(drv->rtnl_sk, msg);\n+\tif (res < 0)\n+\t\tgoto errout;\n \n-\tres = rtnl_neigh_add(drv->rtnl_sk, rn, NLM_F_CREATE);\n+\tres = nl_wait_for_ack(drv->rtnl_sk);\n \tif (res) {\n \t\twpa_printf(MSG_DEBUG,\n \t\t\t   \"nl80211: Adding bridge ip neigh failed: %s\",\n \t\t\t   nl_geterror(res));\n \t}\n errout:\n-\tif (nl_lladdr)\n-\t\tnl_addr_put(nl_lladdr);\n-\tif (nl_ipaddr)\n-\t\tnl_addr_put(nl_ipaddr);\n-\tif (rn)\n-\t\trtnl_neigh_put(rn);\n+\tnlmsg_free(msg);\n \treturn res;\n-#else /* CONFIG_LIBNL3_ROUTE */\n-\treturn -1;\n-#endif /* CONFIG_LIBNL3_ROUTE */\n }\n \n \n static int wpa_driver_br_delete_ip_neigh(void *priv, u8 version,\n \t\t\t\t\t const u8 *ipaddr)\n {\n-#ifdef CONFIG_LIBNL3_ROUTE\n \tstruct i802_bss *bss = priv;\n \tstruct wpa_driver_nl80211_data *drv = bss->drv;\n-\tstruct rtnl_neigh *rn;\n-\tstruct nl_addr *nl_ipaddr;\n-\tint family, addrsize;\n+\tstruct ndmsg nhdr = {\n+\t\t.ndm_state = NUD_PERMANENT,\n+\t\t.ndm_ifindex = bss->br_ifindex,\n+\t};\n+\tstruct nl_msg *msg;\n+\tint addrsize;\n \tint res;\n \n \tif (!ipaddr)\n \t\treturn -EINVAL;\n \n \tif (version == 4) {\n-\t\tfamily = AF_INET;\n+\t\tnhdr.ndm_family = AF_INET;\n \t\taddrsize = 4;\n \t} else if (version == 6) {\n-\t\tfamily = AF_INET6;\n+\t\tnhdr.ndm_family = AF_INET6;\n \t\taddrsize = 16;\n \t} else {\n \t\treturn -EINVAL;\n@@ -10799,41 +10778,30 @@ static int wpa_driver_br_delete_ip_neigh\n \t\treturn -1;\n \t}\n \n-\trn = rtnl_neigh_alloc();\n-\tif (rn == NULL)\n+\tmsg = nlmsg_alloc_simple(RTM_DELNEIGH, NLM_F_CREATE);\n+\tif (!msg)\n \t\treturn -ENOMEM;\n \n-\t/* set the destination ip address for neigh */\n-\tnl_ipaddr = nl_addr_build(family, (void *) ipaddr, addrsize);\n-\tif (nl_ipaddr == NULL) {\n-\t\twpa_printf(MSG_DEBUG, \"nl80211: nl_ipaddr build failed\");\n-\t\tres = -ENOMEM;\n+\tres = -ENOMEM;\n+\tif (nlmsg_append(msg, &nhdr, sizeof(nhdr), NLMSG_ALIGNTO) < 0)\n \t\tgoto errout;\n-\t}\n-\tres = rtnl_neigh_set_dst(rn, nl_ipaddr);\n-\tif (res) {\n-\t\twpa_printf(MSG_DEBUG,\n-\t\t\t   \"nl80211: neigh set destination addr failed\");\n+\n+\tif (nla_put(msg, NDA_DST, addrsize, (void *)ipaddr))\n \t\tgoto errout;\n-\t}\n \n-\trtnl_neigh_set_ifindex(rn, bss->br_ifindex);\n+\tres = nl_send_auto_complete(drv->rtnl_sk, msg);\n+\tif (res < 0)\n+\t\tgoto errout;\n \n-\tres = rtnl_neigh_delete(drv->rtnl_sk, rn, 0);\n+\tres = nl_wait_for_ack(drv->rtnl_sk);\n \tif (res) {\n \t\twpa_printf(MSG_DEBUG,\n \t\t\t   \"nl80211: Deleting bridge ip neigh failed: %s\",\n \t\t\t   nl_geterror(res));\n \t}\n errout:\n-\tif (nl_ipaddr)\n-\t\tnl_addr_put(nl_ipaddr);\n-\tif (rn)\n-\t\trtnl_neigh_put(rn);\n+\tnlmsg_free(msg);\n \treturn res;\n-#else /* CONFIG_LIBNL3_ROUTE */\n-\treturn -1;\n-#endif /* CONFIG_LIBNL3_ROUTE */\n }\n \n \n"
  },
  {
    "path": "package/network/services/hostapd/patches/040-mesh-allow-processing-authentication-frames-in-block.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nDate: Mon, 18 Feb 2019 12:57:11 +0100\nSubject: [PATCH] mesh: allow processing authentication frames in blocked state\n\nIf authentication fails repeatedly e.g. because of a weak signal, the link\ncan end up in blocked state. If one of the nodes tries to establish a link\nagain before it is unblocked on the other side, it will block the link to\nthat other side. The same happens on the other side when it unblocks the\nlink. In that scenario, the link never recovers on its own.\n\nTo fix this, allow restarting authentication even if the link is in blocked\nstate, but don't initiate the attempt until the blocked period is over.\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n\n--- a/src/ap/ieee802_11.c\n+++ b/src/ap/ieee802_11.c\n@@ -3761,15 +3761,6 @@ static void handle_auth(struct hostapd_d\n \t\t\t\t       seq_ctrl);\n \t\t\treturn;\n \t\t}\n-#ifdef CONFIG_MESH\n-\t\tif ((hapd->conf->mesh & MESH_ENABLED) &&\n-\t\t    sta->plink_state == PLINK_BLOCKED) {\n-\t\t\twpa_printf(MSG_DEBUG, \"Mesh peer \" MACSTR\n-\t\t\t\t   \" is blocked - drop Authentication frame\",\n-\t\t\t\t   MAC2STR(mgmt->sa));\n-\t\t\treturn;\n-\t\t}\n-#endif /* CONFIG_MESH */\n #ifdef CONFIG_PASN\n \t\tif (auth_alg == WLAN_AUTH_PASN &&\n \t\t    (sta->flags & WLAN_STA_ASSOC)) {\n"
  },
  {
    "path": "package/network/services/hostapd/patches/050-build_fix.patch",
    "content": "--- a/hostapd/Makefile\n+++ b/hostapd/Makefile\n@@ -323,6 +323,7 @@ ifdef CONFIG_FILS\n CFLAGS += -DCONFIG_FILS\n OBJS += ../src/ap/fils_hlp.o\n NEED_SHA384=y\n+NEED_HMAC_SHA384_KDF=y\n NEED_AES_SIV=y\n ifdef CONFIG_FILS_SK_PFS\n CFLAGS += -DCONFIG_FILS_SK_PFS\n--- a/wpa_supplicant/Makefile\n+++ b/wpa_supplicant/Makefile\n@@ -312,6 +312,7 @@ endif\n ifdef CONFIG_FILS\n CFLAGS += -DCONFIG_FILS\n NEED_SHA384=y\n+NEED_HMAC_SHA384_KDF=y\n NEED_AES_SIV=y\n ifdef CONFIG_FILS_SK_PFS\n CFLAGS += -DCONFIG_FILS_SK_PFS\n"
  },
  {
    "path": "package/network/services/hostapd/patches/100-daemonize_fix.patch",
    "content": "--- a/src/utils/os_unix.c\n+++ b/src/utils/os_unix.c\n@@ -10,6 +10,7 @@\n \n #include <time.h>\n #include <sys/wait.h>\n+#include <fcntl.h>\n \n #ifdef ANDROID\n #include <sys/capability.h>\n@@ -188,59 +189,46 @@ int os_gmtime(os_time_t t, struct os_tm\n \treturn 0;\n }\n \n-\n-#ifdef __APPLE__\n-#include <fcntl.h>\n-static int os_daemon(int nochdir, int noclose)\n+int os_daemonize(const char *pid_file)\n {\n-\tint devnull;\n+\tint pid = 0, i, devnull;\n \n-\tif (chdir(\"/\") < 0)\n-\t\treturn -1;\n+#if defined(__uClinux__) || defined(__sun__)\n+\treturn -1;\n+#else /* defined(__uClinux__) || defined(__sun__) */\n \n-\tdevnull = open(\"/dev/null\", O_RDWR);\n-\tif (devnull < 0)\n+#ifndef __APPLE__\n+\tpid = fork();\n+\tif (pid < 0)\n \t\treturn -1;\n+#endif\n \n-\tif (dup2(devnull, STDIN_FILENO) < 0) {\n-\t\tclose(devnull);\n-\t\treturn -1;\n+\tif (pid > 0) {\n+\t\tif (pid_file) {\n+\t\t\tFILE *f = fopen(pid_file, \"w\");\n+\t\t\tif (f) {\n+\t\t\t\tfprintf(f, \"%u\\n\", pid);\n+\t\t\t\tfclose(f);\n+\t\t\t}\n+\t\t}\n+\t\t_exit(0);\n \t}\n \n-\tif (dup2(devnull, STDOUT_FILENO) < 0) {\n-\t\tclose(devnull);\n+\tif (setsid() < 0)\n \t\treturn -1;\n-\t}\n \n-\tif (dup2(devnull, STDERR_FILENO) < 0) {\n-\t\tclose(devnull);\n+\tif (chdir(\"/\") < 0)\n \t\treturn -1;\n-\t}\n-\n-\treturn 0;\n-}\n-#else /* __APPLE__ */\n-#define os_daemon daemon\n-#endif /* __APPLE__ */\n \n-\n-int os_daemonize(const char *pid_file)\n-{\n-#if defined(__uClinux__) || defined(__sun__)\n-\treturn -1;\n-#else /* defined(__uClinux__) || defined(__sun__) */\n-\tif (os_daemon(0, 0)) {\n-\t\tperror(\"daemon\");\n+\tdevnull = open(\"/dev/null\", O_RDWR);\n+\tif (devnull < 0)\n \t\treturn -1;\n-\t}\n \n-\tif (pid_file) {\n-\t\tFILE *f = fopen(pid_file, \"w\");\n-\t\tif (f) {\n-\t\t\tfprintf(f, \"%u\\n\", getpid());\n-\t\t\tfclose(f);\n-\t\t}\n-\t}\n+\tfor (i = 0; i <= STDERR_FILENO; i++)\n+\t\tdup2(devnull, i);\n+\n+\tif (devnull > 2)\n+\t\tclose(devnull);\n \n \treturn -0;\n #endif /* defined(__uClinux__) || defined(__sun__) */\n"
  },
  {
    "path": "package/network/services/hostapd/patches/200-multicall.patch",
    "content": "--- a/hostapd/Makefile\n+++ b/hostapd/Makefile\n@@ -1,6 +1,7 @@\n ALL=hostapd hostapd_cli\n CONFIG_FILE = .config\n \n+-include $(if $(MULTICALL), ../wpa_supplicant/.config)\n include ../src/build.rules\n \n ifdef LIBS\n@@ -199,7 +200,8 @@ endif\n \n ifdef CONFIG_NO_VLAN\n CFLAGS += -DCONFIG_NO_VLAN\n-else\n+endif\n+ifneq ($(findstring CONFIG_NO_VLAN,$(CFLAGS)), CONFIG_NO_VLAN)\n OBJS += ../src/ap/vlan_init.o\n OBJS += ../src/ap/vlan_ifconfig.o\n OBJS += ../src/ap/vlan.o\n@@ -350,10 +352,14 @@ CFLAGS += -DCONFIG_MBO\n OBJS += ../src/ap/mbo_ap.o\n endif\n \n+ifndef MULTICALL\n+CFLAGS += -DNO_SUPPLICANT\n+endif\n+\n include ../src/drivers/drivers.mak\n-OBJS += $(DRV_AP_OBJS)\n-CFLAGS += $(DRV_AP_CFLAGS)\n-LDFLAGS += $(DRV_AP_LDFLAGS)\n+OBJS += $(sort $(DRV_AP_OBJS) $(if $(MULTICALL),$(DRV_WPA_OBJS)))\n+CFLAGS += $(DRV_AP_CFLAGS) $(if $(MULTICALL),$(DRV_WPA_CFLAGS))\n+LDFLAGS += $(DRV_AP_LDFLAGS) $(if $(MULTICALL),$(DRV_WPA_LDFLAGS))\n LIBS += $(DRV_AP_LIBS)\n \n ifdef CONFIG_L2_PACKET\n@@ -1281,6 +1287,12 @@ install: $(addprefix $(DESTDIR)$(BINDIR)\n _OBJS_VAR := OBJS\n include ../src/objs.mk\n \n+hostapd_multi.a: $(BCHECK) $(OBJS)\n+\t$(Q)$(CC) -c -o hostapd_multi.o -Dmain=hostapd_main $(CFLAGS) main.c\n+\t@$(E) \"  CC \" $<\n+\t@rm -f $@\n+\t@$(AR) cr $@ hostapd_multi.o $(OBJS)\n+\n hostapd: $(OBJS)\n \t$(Q)$(CC) $(LDFLAGS) -o hostapd $(OBJS) $(LIBS)\n \t@$(E) \"  LD \" $@\n@@ -1355,6 +1367,12 @@ include ../src/objs.mk\n _OBJS_VAR := SOBJS\n include ../src/objs.mk\n \n+dump_cflags:\n+\t@printf \"%s \" \"$(CFLAGS)\"\n+\n+dump_ldflags:\n+\t@printf \"%s \" \"$(LDFLAGS) $(LIBS) $(EXTRALIBS)\"\n+\n nt_password_hash: $(NOBJS)\n \t$(Q)$(CC) $(LDFLAGS) -o nt_password_hash $(NOBJS) $(LIBS_n)\n \t@$(E) \"  LD \" $@\n--- a/wpa_supplicant/Makefile\n+++ b/wpa_supplicant/Makefile\n@@ -17,6 +17,7 @@ endif\n EXTRA_TARGETS=dynamic_eap_methods\n \n CONFIG_FILE=.config\n+-include $(if $(MULTICALL),../hostapd/.config)\n include ../src/build.rules\n \n ifdef LIBS\n@@ -363,7 +364,9 @@ endif\n ifdef CONFIG_IBSS_RSN\n NEED_RSN_AUTHENTICATOR=y\n CFLAGS += -DCONFIG_IBSS_RSN\n+ifndef MULTICALL\n CFLAGS += -DCONFIG_NO_VLAN\n+endif\n OBJS += ibss_rsn.o\n endif\n \n@@ -900,6 +903,10 @@ ifdef CONFIG_DYNAMIC_EAP_METHODS\n CFLAGS += -DCONFIG_DYNAMIC_EAP_METHODS\n LIBS += -ldl -rdynamic\n endif\n+else\n+  ifdef MULTICALL\n+    OBJS += ../src/eap_common/eap_common.o\n+  endif\n endif\n \n ifdef CONFIG_AP\n@@ -907,9 +914,11 @@ NEED_EAP_COMMON=y\n NEED_RSN_AUTHENTICATOR=y\n CFLAGS += -DCONFIG_AP\n OBJS += ap.o\n+ifndef MULTICALL\n CFLAGS += -DCONFIG_NO_RADIUS\n CFLAGS += -DCONFIG_NO_ACCOUNTING\n CFLAGS += -DCONFIG_NO_VLAN\n+endif\n OBJS += ../src/ap/hostapd.o\n OBJS += ../src/ap/wpa_auth_glue.o\n OBJS += ../src/ap/utils.o\n@@ -989,6 +998,12 @@ endif\n ifdef CONFIG_HS20\n OBJS += ../src/ap/hs20.o\n endif\n+else\n+  ifdef MULTICALL\n+    OBJS += ../src/eap_server/eap_server.o\n+    OBJS += ../src/eap_server/eap_server_identity.o\n+    OBJS += ../src/eap_server/eap_server_methods.o\n+  endif\n endif\n \n ifdef CONFIG_MBO\n@@ -997,7 +1012,9 @@ CFLAGS += -DCONFIG_MBO\n endif\n \n ifdef NEED_RSN_AUTHENTICATOR\n+ifndef MULTICALL\n CFLAGS += -DCONFIG_NO_RADIUS\n+endif\n NEED_AES_WRAP=y\n OBJS += ../src/ap/wpa_auth.o\n OBJS += ../src/ap/wpa_auth_ie.o\n@@ -1891,6 +1908,12 @@ wpa_priv: $(BCHECK) $(OBJS_priv)\n \n _OBJS_VAR := OBJS\n include ../src/objs.mk\n+wpa_supplicant_multi.a: .config $(BCHECK) $(OBJS) $(EXTRA_progs)\n+\t$(Q)$(CC) -c -o wpa_supplicant_multi.o -Dmain=wpa_supplicant_main $(CFLAGS) main.c\n+\t@$(E) \"  CC \" $<\n+\t@rm -f $@\n+\t@$(AR) cr $@ wpa_supplicant_multi.o $(OBJS)\n+\n wpa_supplicant: $(BCHECK) $(OBJS) $(EXTRA_progs)\n \t$(Q)$(LDO) $(LDFLAGS) -o wpa_supplicant $(OBJS) $(LIBS) $(EXTRALIBS)\n \t@$(E) \"  LD \" $@\n@@ -2023,6 +2046,12 @@ eap_gpsk.so: $(SRC_EAP_GPSK)\n \t$(Q)sed -e 's|\\@BINDIR\\@|$(BINDIR)|g' $< >$@\n \t@$(E) \"  sed\" $<\n \n+dump_cflags:\n+\t@printf \"%s \" \"$(CFLAGS)\"\n+\n+dump_ldflags:\n+\t@printf \"%s \" \"$(LDFLAGS) $(LIBS) $(EXTRALIBS)\"\n+\n wpa_supplicant.exe: wpa_supplicant\n \tmv -f $< $@\n wpa_cli.exe: wpa_cli\n--- a/src/drivers/driver.h\n+++ b/src/drivers/driver.h\n@@ -6033,8 +6033,8 @@ union wpa_event_data {\n  * Driver wrapper code should call this function whenever an event is received\n  * from the driver.\n  */\n-void wpa_supplicant_event(void *ctx, enum wpa_event_type event,\n-\t\t\t  union wpa_event_data *data);\n+extern void (*wpa_supplicant_event)(void *ctx, enum wpa_event_type event,\n+\t\t\t\t    union wpa_event_data *data);\n \n /**\n  * wpa_supplicant_event_global - Report a driver event for wpa_supplicant\n@@ -6046,7 +6046,7 @@ void wpa_supplicant_event(void *ctx, enu\n  * Same as wpa_supplicant_event(), but we search for the interface in\n  * wpa_global.\n  */\n-void wpa_supplicant_event_global(void *ctx, enum wpa_event_type event,\n+extern void (*wpa_supplicant_event_global)(void *ctx, enum wpa_event_type event,\n \t\t\t\t union wpa_event_data *data);\n \n /*\n--- a/src/ap/drv_callbacks.c\n+++ b/src/ap/drv_callbacks.c\n@@ -1842,8 +1842,8 @@ err:\n #endif /* CONFIG_OWE */\n \n \n-void wpa_supplicant_event(void *ctx, enum wpa_event_type event,\n-\t\t\t  union wpa_event_data *data)\n+void hostapd_wpa_event(void *ctx, enum wpa_event_type event,\n+\t\t       union wpa_event_data *data)\n {\n \tstruct hostapd_data *hapd = ctx;\n #ifndef CONFIG_NO_STDOUT_DEBUG\n@@ -2088,7 +2088,7 @@ void wpa_supplicant_event(void *ctx, enu\n }\n \n \n-void wpa_supplicant_event_global(void *ctx, enum wpa_event_type event,\n+void hostapd_wpa_event_global(void *ctx, enum wpa_event_type event,\n \t\t\t\t union wpa_event_data *data)\n {\n \tstruct hapd_interfaces *interfaces = ctx;\n--- a/wpa_supplicant/wpa_priv.c\n+++ b/wpa_supplicant/wpa_priv.c\n@@ -1038,8 +1038,8 @@ static void wpa_priv_send_ft_response(st\n }\n \n \n-void wpa_supplicant_event(void *ctx, enum wpa_event_type event,\n-\t\t\t  union wpa_event_data *data)\n+static void supplicant_event(void *ctx, enum wpa_event_type event,\n+\t\t\t     union wpa_event_data *data)\n {\n \tstruct wpa_priv_interface *iface = ctx;\n \n@@ -1102,7 +1102,7 @@ void wpa_supplicant_event(void *ctx, enu\n }\n \n \n-void wpa_supplicant_event_global(void *ctx, enum wpa_event_type event,\n+void supplicant_event_global(void *ctx, enum wpa_event_type event,\n \t\t\t\t union wpa_event_data *data)\n {\n \tstruct wpa_priv_global *global = ctx;\n@@ -1215,6 +1215,8 @@ int main(int argc, char *argv[])\n \tif (os_program_init())\n \t\treturn -1;\n \n+\twpa_supplicant_event = supplicant_event;\n+\twpa_supplicant_event_global = supplicant_event_global;\n \twpa_priv_fd_workaround();\n \n \tos_memset(&global, 0, sizeof(global));\n--- a/wpa_supplicant/events.c\n+++ b/wpa_supplicant/events.c\n@@ -4891,8 +4891,8 @@ static void wpas_event_unprot_beacon(str\n }\n \n \n-void wpa_supplicant_event(void *ctx, enum wpa_event_type event,\n-\t\t\t  union wpa_event_data *data)\n+void supplicant_event(void *ctx, enum wpa_event_type event,\n+\t\t      union wpa_event_data *data)\n {\n \tstruct wpa_supplicant *wpa_s = ctx;\n \tint resched;\n@@ -5745,7 +5745,7 @@ void wpa_supplicant_event(void *ctx, enu\n }\n \n \n-void wpa_supplicant_event_global(void *ctx, enum wpa_event_type event,\n+void supplicant_event_global(void *ctx, enum wpa_event_type event,\n \t\t\t\t union wpa_event_data *data)\n {\n \tstruct wpa_supplicant *wpa_s;\n--- a/wpa_supplicant/wpa_supplicant.c\n+++ b/wpa_supplicant/wpa_supplicant.c\n@@ -7043,7 +7043,6 @@ struct wpa_interface * wpa_supplicant_ma\n \treturn NULL;\n }\n \n-\n /**\n  * wpa_supplicant_match_existing - Match existing interfaces\n  * @global: Pointer to global data from wpa_supplicant_init()\n@@ -7078,6 +7077,11 @@ static int wpa_supplicant_match_existing\n \n #endif /* CONFIG_MATCH_IFACE */\n \n+extern void supplicant_event(void *ctx, enum wpa_event_type event,\n+\t\t\t     union wpa_event_data *data);\n+\n+extern void supplicant_event_global(void *ctx, enum wpa_event_type event,\n+ \t\t\t\t union wpa_event_data *data);\n \n /**\n  * wpa_supplicant_add_iface - Add a new network interface\n@@ -7334,6 +7338,8 @@ struct wpa_global * wpa_supplicant_init(\n #ifndef CONFIG_NO_WPA_MSG\n \twpa_msg_register_ifname_cb(wpa_supplicant_msg_ifname_cb);\n #endif /* CONFIG_NO_WPA_MSG */\n+\twpa_supplicant_event = supplicant_event;\n+\twpa_supplicant_event_global = supplicant_event_global;\n \n \tif (params->wpa_debug_file_path)\n \t\twpa_debug_open_file(params->wpa_debug_file_path);\n--- a/hostapd/main.c\n+++ b/hostapd/main.c\n@@ -590,6 +590,11 @@ fail:\n \treturn -1;\n }\n \n+void hostapd_wpa_event(void *ctx, enum wpa_event_type event,\n+                       union wpa_event_data *data);\n+\n+void hostapd_wpa_event_global(void *ctx, enum wpa_event_type event,\n+ \t\t\t\t union wpa_event_data *data);\n \n #ifdef CONFIG_WPS\n static int gen_uuid(const char *txt_addr)\n@@ -683,6 +688,8 @@ int main(int argc, char *argv[])\n \t\treturn -1;\n #endif /* CONFIG_DPP */\n \n+\twpa_supplicant_event = hostapd_wpa_event;\n+\twpa_supplicant_event_global = hostapd_wpa_event_global;\n \tfor (;;) {\n \t\tc = getopt(argc, argv, \"b:Bde:f:hi:KP:sSTtu:vg:G:\");\n \t\tif (c < 0)\n--- a/src/drivers/drivers.c\n+++ b/src/drivers/drivers.c\n@@ -10,6 +10,10 @@\n #include \"utils/common.h\"\n #include \"driver.h\"\n \n+void (*wpa_supplicant_event)(void *ctx, enum wpa_event_type event,\n+\t\t\t     union wpa_event_data *data);\n+void (*wpa_supplicant_event_global)(void *ctx, enum wpa_event_type event,\n+\t\t\t     union wpa_event_data *data);\n \n const struct wpa_driver_ops *const wpa_drivers[] =\n {\n--- a/wpa_supplicant/eapol_test.c\n+++ b/wpa_supplicant/eapol_test.c\n@@ -30,7 +30,12 @@\n #include \"ctrl_iface.h\"\n #include \"pcsc_funcs.h\"\n #include \"wpas_glue.h\"\n+#include \"drivers/driver.h\"\n \n+void (*wpa_supplicant_event)(void *ctx, enum wpa_event_type event,\n+\t\t\t     union wpa_event_data *data);\n+void (*wpa_supplicant_event_global)(void *ctx, enum wpa_event_type event,\n+\t\t\t     union wpa_event_data *data);\n \n const struct wpa_driver_ops *const wpa_drivers[] = { NULL };\n \n@@ -1291,6 +1296,10 @@ static void usage(void)\n \t       \"option several times.\\n\");\n }\n \n+extern void supplicant_event(void *ctx, enum wpa_event_type event,\n+\t\t\t     union wpa_event_data *data);\n+extern void supplicant_event_global(void *ctx, enum wpa_event_type event,\n+\t\t\t     union wpa_event_data *data);\n \n int main(int argc, char *argv[])\n {\n@@ -1311,6 +1320,8 @@ int main(int argc, char *argv[])\n \tif (os_program_init())\n \t\treturn -1;\n \n+\twpa_supplicant_event = supplicant_event;\n+\twpa_supplicant_event_global = supplicant_event_global;\n \thostapd_logger_register_cb(hostapd_logger_cb);\n \n \tos_memset(&eapol_test, 0, sizeof(eapol_test));\n"
  },
  {
    "path": "package/network/services/hostapd/patches/300-noscan.patch",
    "content": "--- a/hostapd/config_file.c\n+++ b/hostapd/config_file.c\n@@ -3474,6 +3474,10 @@ static int hostapd_config_fill(struct ho\n \t\tif (bss->ocv && !bss->ieee80211w)\n \t\t\tbss->ieee80211w = 1;\n #endif /* CONFIG_OCV */\n+\t} else if (os_strcmp(buf, \"noscan\") == 0) {\n+\t\tconf->noscan = atoi(pos);\n+\t} else if (os_strcmp(buf, \"ht_coex\") == 0) {\n+\t\tconf->no_ht_coex = !atoi(pos);\n \t} else if (os_strcmp(buf, \"ieee80211n\") == 0) {\n \t\tconf->ieee80211n = atoi(pos);\n \t} else if (os_strcmp(buf, \"ht_capab\") == 0) {\n--- a/src/ap/ap_config.h\n+++ b/src/ap/ap_config.h\n@@ -1014,6 +1014,8 @@ struct hostapd_config {\n \n \tint ht_op_mode_fixed;\n \tu16 ht_capab;\n+\tint noscan;\n+\tint no_ht_coex;\n \tint ieee80211n;\n \tint secondary_channel;\n \tint no_pri_sec_switch;\n--- a/src/ap/hw_features.c\n+++ b/src/ap/hw_features.c\n@@ -517,7 +517,8 @@ static int ieee80211n_check_40mhz(struct\n \tint ret;\n \n \t/* Check that HT40 is used and PRI / SEC switch is allowed */\n-\tif (!iface->conf->secondary_channel || iface->conf->no_pri_sec_switch)\n+\tif (!iface->conf->secondary_channel || iface->conf->no_pri_sec_switch ||\n+\t\tiface->conf->noscan)\n \t\treturn 0;\n \n \thostapd_set_state(iface, HAPD_IFACE_HT_SCAN);\n--- a/src/ap/ieee802_11_ht.c\n+++ b/src/ap/ieee802_11_ht.c\n@@ -230,6 +230,9 @@ void hostapd_2040_coex_action(struct hos\n \t\treturn;\n \t}\n \n+\tif (iface->conf->noscan || iface->conf->no_ht_coex)\n+\t\treturn;\n+\n \tif (len < IEEE80211_HDRLEN + 2 + sizeof(*bc_ie)) {\n \t\twpa_printf(MSG_DEBUG,\n \t\t\t   \"Ignore too short 20/40 BSS Coexistence Management frame\");\n@@ -390,6 +393,9 @@ void ht40_intolerant_add(struct hostapd_\n \tif (iface->current_mode->mode != HOSTAPD_MODE_IEEE80211G)\n \t\treturn;\n \n+\tif (iface->conf->noscan || iface->conf->no_ht_coex)\n+\t\treturn;\n+\n \twpa_printf(MSG_INFO, \"HT: Forty MHz Intolerant is set by STA \" MACSTR\n \t\t   \" in Association Request\", MAC2STR(sta->addr));\n \n"
  },
  {
    "path": "package/network/services/hostapd/patches/301-mesh-noscan.patch",
    "content": "--- a/wpa_supplicant/config.c\n+++ b/wpa_supplicant/config.c\n@@ -2532,6 +2532,7 @@ static const struct parse_data ssid_fiel\n #else /* CONFIG_MESH */\n \t{ INT_RANGE(mode, 0, 4) },\n #endif /* CONFIG_MESH */\n+\t{ INT_RANGE(noscan, 0, 1) },\n \t{ INT_RANGE(proactive_key_caching, 0, 1) },\n \t{ INT_RANGE(disabled, 0, 2) },\n \t{ STR(id_str) },\n--- a/wpa_supplicant/config_file.c\n+++ b/wpa_supplicant/config_file.c\n@@ -769,6 +769,7 @@ static void wpa_config_write_network(FIL\n #endif /* IEEE8021X_EAPOL */\n \tINT(mode);\n \tINT(no_auto_peer);\n+\tINT(noscan);\n \tINT(mesh_fwding);\n \tINT(frequency);\n \tINT(enable_edmg);\n--- a/wpa_supplicant/mesh.c\n+++ b/wpa_supplicant/mesh.c\n@@ -505,6 +505,8 @@ static int wpa_supplicant_mesh_init(stru\n \t\t\t   frequency);\n \t\tgoto out_free;\n \t}\n+\tif (ssid->noscan)\n+\t\tconf->noscan = 1;\n \n \tif (ssid->mesh_basic_rates == NULL) {\n \t\t/*\n--- a/wpa_supplicant/wpa_supplicant.c\n+++ b/wpa_supplicant/wpa_supplicant.c\n@@ -2436,7 +2436,7 @@ void ibss_mesh_setup_freq(struct wpa_sup\n \tint ieee80211_mode = wpas_mode_to_ieee80211_mode(ssid->mode);\n \tenum hostapd_hw_mode hw_mode;\n \tstruct hostapd_hw_modes *mode = NULL;\n-\tint ht40plus[] = { 36, 44, 52, 60, 100, 108, 116, 124, 132, 149, 157,\n+\tint ht40plus[] = { 1, 2, 3, 4, 5, 6, 36, 44, 52, 60, 100, 108, 116, 124, 132, 149, 157,\n \t\t\t   184, 192 };\n \tint bw80[] = { 5180, 5260, 5500, 5580, 5660, 5745, 5955,\n \t\t       6035, 6115, 6195, 6275, 6355, 6435, 6515,\n@@ -2444,7 +2444,7 @@ void ibss_mesh_setup_freq(struct wpa_sup\n \tint bw160[] = { 5955, 6115, 6275, 6435, 6595, 6755, 6915 };\n \tstruct hostapd_channel_data *pri_chan = NULL, *sec_chan = NULL;\n \tu8 channel;\n-\tint i, chan_idx, ht40 = -1, res, obss_scan = 1;\n+\tint i, chan_idx, ht40 = -1, res, obss_scan = !(ssid->noscan);\n \tunsigned int j, k;\n \tstruct hostapd_freq_params vht_freq;\n \tint chwidth, seg0, seg1;\n@@ -2535,7 +2535,7 @@ void ibss_mesh_setup_freq(struct wpa_sup\n #endif /* CONFIG_HE_OVERRIDES */\n \n \t/* Setup higher BW only for 5 GHz */\n-\tif (mode->mode != HOSTAPD_MODE_IEEE80211A)\n+\tif (mode->mode != HOSTAPD_MODE_IEEE80211A && !(ssid->noscan))\n \t\treturn;\n \n \tfor (chan_idx = 0; chan_idx < mode->num_channels; chan_idx++) {\n--- a/wpa_supplicant/config_ssid.h\n+++ b/wpa_supplicant/config_ssid.h\n@@ -974,6 +974,8 @@ struct wpa_ssid {\n \t */\n \tint no_auto_peer;\n \n+\tint noscan;\n+\n \t/**\n \t * mesh_rssi_threshold - Set mesh parameter mesh_rssi_threshold (dBm)\n \t *\n"
  },
  {
    "path": "package/network/services/hostapd/patches/310-rescan_immediately.patch",
    "content": "--- a/wpa_supplicant/wpa_supplicant.c\n+++ b/wpa_supplicant/wpa_supplicant.c\n@@ -5377,7 +5377,7 @@ wpa_supplicant_alloc(struct wpa_supplica\n \tif (wpa_s == NULL)\n \t\treturn NULL;\n \twpa_s->scan_req = INITIAL_SCAN_REQ;\n-\twpa_s->scan_interval = 5;\n+\twpa_s->scan_interval = 1;\n \twpa_s->new_connection = 1;\n \twpa_s->parent = parent ? parent : wpa_s;\n \twpa_s->p2pdev = wpa_s->parent;\n"
  },
  {
    "path": "package/network/services/hostapd/patches/320-optional_rfkill.patch",
    "content": "--- a/src/drivers/drivers.mak\n+++ b/src/drivers/drivers.mak\n@@ -54,7 +54,6 @@ NEED_SME=y\n NEED_AP_MLME=y\n NEED_NETLINK=y\n NEED_LINUX_IOCTL=y\n-NEED_RFKILL=y\n NEED_RADIOTAP=y\n NEED_LIBNL=y\n endif\n@@ -111,7 +110,6 @@ DRV_WPA_CFLAGS += -DCONFIG_DRIVER_WEXT\n CONFIG_WIRELESS_EXTENSION=y\n NEED_NETLINK=y\n NEED_LINUX_IOCTL=y\n-NEED_RFKILL=y\n endif\n \n ifdef CONFIG_DRIVER_NDIS\n@@ -137,7 +135,6 @@ endif\n ifdef CONFIG_WIRELESS_EXTENSION\n DRV_WPA_CFLAGS += -DCONFIG_WIRELESS_EXTENSION\n DRV_WPA_OBJS += ../src/drivers/driver_wext.o\n-NEED_RFKILL=y\n endif\n \n ifdef NEED_NETLINK\n@@ -146,6 +143,7 @@ endif\n \n ifdef NEED_RFKILL\n DRV_OBJS += ../src/drivers/rfkill.o\n+DRV_WPA_CFLAGS += -DCONFIG_RFKILL\n endif\n \n ifdef NEED_RADIOTAP\n--- a/src/drivers/rfkill.h\n+++ b/src/drivers/rfkill.h\n@@ -18,8 +18,24 @@ struct rfkill_config {\n \tvoid (*unblocked_cb)(void *ctx);\n };\n \n+#ifdef CONFIG_RFKILL\n struct rfkill_data * rfkill_init(struct rfkill_config *cfg);\n void rfkill_deinit(struct rfkill_data *rfkill);\n int rfkill_is_blocked(struct rfkill_data *rfkill);\n+#else\n+static inline struct rfkill_data * rfkill_init(struct rfkill_config *cfg)\n+{\n+\treturn (void *) 1;\n+}\n+\n+static inline void rfkill_deinit(struct rfkill_data *rfkill)\n+{\n+}\n+\n+static inline int rfkill_is_blocked(struct rfkill_data *rfkill)\n+{\n+\treturn 0;\n+}\n+#endif\n \n #endif /* RFKILL_H */\n"
  },
  {
    "path": "package/network/services/hostapd/patches/330-nl80211_fix_set_freq.patch",
    "content": "--- a/src/drivers/driver_nl80211.c\n+++ b/src/drivers/driver_nl80211.c\n@@ -4986,7 +4986,7 @@ static int nl80211_set_channel(struct i8\n \t\t   freq->freq, freq->ht_enabled, freq->vht_enabled, freq->he_enabled,\n \t\t   freq->bandwidth, freq->center_freq1, freq->center_freq2);\n \n-\tmsg = nl80211_drv_msg(drv, 0, set_chan ? NL80211_CMD_SET_CHANNEL :\n+\tmsg = nl80211_bss_msg(bss, 0, set_chan ? NL80211_CMD_SET_CHANNEL :\n \t\t\t      NL80211_CMD_SET_WIPHY);\n \tif (!msg || nl80211_put_freq_params(msg, freq) < 0) {\n \t\tnlmsg_free(msg);\n"
  },
  {
    "path": "package/network/services/hostapd/patches/340-reload_freq_change.patch",
    "content": "--- a/src/ap/hostapd.c\n+++ b/src/ap/hostapd.c\n@@ -115,6 +115,28 @@ static void hostapd_reload_bss(struct ho\n #endif /* CONFIG_NO_RADIUS */\n \n \tssid = &hapd->conf->ssid;\n+\n+\thostapd_set_freq(hapd, hapd->iconf->hw_mode, hapd->iface->freq,\n+\t\t\t hapd->iconf->channel,\n+\t\t\t hapd->iconf->enable_edmg,\n+\t\t\t hapd->iconf->edmg_channel,\n+\t\t\t hapd->iconf->ieee80211n,\n+\t\t\t hapd->iconf->ieee80211ac,\n+\t\t\t hapd->iconf->ieee80211ax,\n+\t\t\t hapd->iconf->secondary_channel,\n+\t\t\t hostapd_get_oper_chwidth(hapd->iconf),\n+\t\t\t hostapd_get_oper_centr_freq_seg0_idx(hapd->iconf),\n+\t\t\t hostapd_get_oper_centr_freq_seg1_idx(hapd->iconf));\n+\n+\tif (hapd->iface->current_mode) {\n+\t\tif (hostapd_prepare_rates(hapd->iface, hapd->iface->current_mode)) {\n+\t\t\twpa_printf(MSG_ERROR, \"Failed to prepare rates table.\");\n+\t\t\thostapd_logger(hapd, NULL, HOSTAPD_MODULE_IEEE80211,\n+\t\t\t\t       HOSTAPD_LEVEL_WARNING,\n+\t\t\t\t       \"Failed to prepare rates table.\");\n+\t\t}\n+\t}\n+\n \tif (!ssid->wpa_psk_set && ssid->wpa_psk && !ssid->wpa_psk->next &&\n \t    ssid->wpa_passphrase_set && ssid->wpa_passphrase) {\n \t\t/*\n@@ -216,6 +238,7 @@ int hostapd_reload_config(struct hostapd\n \tstruct hostapd_data *hapd = iface->bss[0];\n \tstruct hostapd_config *newconf, *oldconf;\n \tsize_t j;\n+\tint i;\n \n \tif (iface->config_fname == NULL) {\n \t\t/* Only in-memory config in use - assume it has been updated */\n@@ -266,24 +289,20 @@ int hostapd_reload_config(struct hostapd\n \t}\n \tiface->conf = newconf;\n \n+\tfor (i = 0; i < iface->num_hw_features; i++) {\n+\t\tstruct hostapd_hw_modes *mode = &iface->hw_features[i];\n+\t\tif (mode->mode == iface->conf->hw_mode) {\n+\t\t\tiface->current_mode = mode;\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\n+\tif (iface->conf->channel)\n+\t\tiface->freq = hostapd_hw_get_freq(hapd, iface->conf->channel);\n+\n \tfor (j = 0; j < iface->num_bss; j++) {\n \t\thapd = iface->bss[j];\n \t\thapd->iconf = newconf;\n-\t\thapd->iconf->channel = oldconf->channel;\n-\t\thapd->iconf->acs = oldconf->acs;\n-\t\thapd->iconf->secondary_channel = oldconf->secondary_channel;\n-\t\thapd->iconf->ieee80211n = oldconf->ieee80211n;\n-\t\thapd->iconf->ieee80211ac = oldconf->ieee80211ac;\n-\t\thapd->iconf->ht_capab = oldconf->ht_capab;\n-\t\thapd->iconf->vht_capab = oldconf->vht_capab;\n-\t\thostapd_set_oper_chwidth(hapd->iconf,\n-\t\t\t\t\t hostapd_get_oper_chwidth(oldconf));\n-\t\thostapd_set_oper_centr_freq_seg0_idx(\n-\t\t\thapd->iconf,\n-\t\t\thostapd_get_oper_centr_freq_seg0_idx(oldconf));\n-\t\thostapd_set_oper_centr_freq_seg1_idx(\n-\t\t\thapd->iconf,\n-\t\t\thostapd_get_oper_centr_freq_seg1_idx(oldconf));\n \t\thapd->conf = newconf->bss[j];\n \t\thostapd_reload_bss(hapd);\n \t}\n"
  },
  {
    "path": "package/network/services/hostapd/patches/341-mesh-ctrl-iface-channel-switch.patch",
    "content": "--- a/wpa_supplicant/ap.c\n+++ b/wpa_supplicant/ap.c\n@@ -1611,15 +1611,35 @@ int ap_switch_channel(struct wpa_supplic\n \n \n #ifdef CONFIG_CTRL_IFACE\n+\n+static int __ap_ctrl_iface_chanswitch(struct hostapd_iface *iface,\n+\t\t\t\t      struct csa_settings *settings)\n+{\n+#ifdef NEED_AP_MLME\n+\tif (!iface || !iface->bss[0])\n+\t\treturn 0;\n+\n+\treturn hostapd_switch_channel(iface->bss[0], settings);\n+#else\n+\treturn -1;\n+#endif\n+}\n+\n+\n int ap_ctrl_iface_chanswitch(struct wpa_supplicant *wpa_s, const char *pos)\n {\n \tstruct csa_settings settings;\n \tint ret = hostapd_parse_csa_settings(pos, &settings);\n \n+\tif (!(wpa_s->ap_iface && wpa_s->ap_iface->bss[0]) &&\n+\t    !(wpa_s->ifmsh && wpa_s->ifmsh->bss[0]))\n+\t\treturn -1;\n+\n+\tret = __ap_ctrl_iface_chanswitch(wpa_s->ap_iface, &settings);\n \tif (ret)\n \t\treturn ret;\n \n-\treturn ap_switch_channel(wpa_s, &settings);\n+\treturn __ap_ctrl_iface_chanswitch(wpa_s->ifmsh, &settings);\n }\n #endif /* CONFIG_CTRL_IFACE */\n \n"
  },
  {
    "path": "package/network/services/hostapd/patches/350-nl80211_del_beacon_bss.patch",
    "content": "--- a/src/drivers/driver_nl80211.c\n+++ b/src/drivers/driver_nl80211.c\n@@ -2931,10 +2931,15 @@ static int wpa_driver_nl80211_del_beacon\n \tstruct nl_msg *msg;\n \tstruct wpa_driver_nl80211_data *drv = bss->drv;\n \n+\tif (!bss->beacon_set)\n+\t\treturn 0;\n+\n+\tbss->beacon_set = 0;\n+\n \twpa_printf(MSG_DEBUG, \"nl80211: Remove beacon (ifindex=%d)\",\n-\t\t   drv->ifindex);\n+\t\t   bss->ifindex);\n \tnl80211_put_wiphy_data_ap(bss);\n-\tmsg = nl80211_drv_msg(drv, 0, NL80211_CMD_DEL_BEACON);\n+\tmsg = nl80211_bss_msg(bss, 0, NL80211_CMD_DEL_BEACON);\n \treturn send_and_recv_msgs(drv, msg, NULL, NULL, NULL, NULL);\n }\n \n@@ -5617,7 +5622,7 @@ static void nl80211_teardown_ap(struct i\n \t\tnl80211_mgmt_unsubscribe(bss, \"AP teardown\");\n \n \tnl80211_put_wiphy_data_ap(bss);\n-\tbss->beacon_set = 0;\n+\twpa_driver_nl80211_del_beacon(bss);\n }\n \n \n@@ -8071,8 +8076,6 @@ static int wpa_driver_nl80211_if_remove(\n \t} else {\n \t\twpa_printf(MSG_DEBUG, \"nl80211: First BSS - reassign context\");\n \t\tnl80211_teardown_ap(bss);\n-\t\tif (!bss->added_if && !drv->first_bss->next)\n-\t\t\twpa_driver_nl80211_del_beacon(bss);\n \t\tnl80211_destroy_bss(bss);\n \t\tif (!bss->added_if)\n \t\t\ti802_set_iface_flags(bss, 0);\n@@ -8469,7 +8472,6 @@ static int wpa_driver_nl80211_deinit_ap(\n \tif (!is_ap_interface(drv->nlmode))\n \t\treturn -1;\n \twpa_driver_nl80211_del_beacon(bss);\n-\tbss->beacon_set = 0;\n \n \t/*\n \t * If the P2P GO interface was dynamically added, then it is\n@@ -8489,7 +8491,6 @@ static int wpa_driver_nl80211_stop_ap(vo\n \tif (!is_ap_interface(drv->nlmode))\n \t\treturn -1;\n \twpa_driver_nl80211_del_beacon(bss);\n-\tbss->beacon_set = 0;\n \treturn 0;\n }\n \n"
  },
  {
    "path": "package/network/services/hostapd/patches/360-ctrl_iface_reload.patch",
    "content": "--- a/hostapd/ctrl_iface.c\n+++ b/hostapd/ctrl_iface.c\n@@ -67,6 +67,7 @@\n #include \"fst/fst_ctrl_iface.h\"\n #include \"config_file.h\"\n #include \"ctrl_iface.h\"\n+#include \"config_file.h\"\n \n \n #define HOSTAPD_CLI_DUP_VALUE_MAX_LEN 256\n@@ -82,6 +83,7 @@ static void hostapd_ctrl_iface_send(stru\n \t\t\t\t    enum wpa_msg_type type,\n \t\t\t\t    const char *buf, size_t len);\n \n+static char *reload_opts = NULL;\n \n static int hostapd_ctrl_iface_attach(struct hostapd_data *hapd,\n \t\t\t\t     struct sockaddr_storage *from,\n@@ -133,6 +135,61 @@ static int hostapd_ctrl_iface_new_sta(st\n \treturn 0;\n }\n \n+static char *get_option(char *opt, char *str)\n+{\n+\tint len = strlen(str);\n+\n+\tif (!strncmp(opt, str, len))\n+\t\treturn opt + len;\n+\telse\n+\t\treturn NULL;\n+}\n+\n+static struct hostapd_config *hostapd_ctrl_iface_config_read(const char *fname)\n+{\n+\tstruct hostapd_config *conf;\n+\tchar *opt, *val;\n+\n+\tconf = hostapd_config_read(fname);\n+\tif (!conf)\n+\t\treturn NULL;\n+\n+\tfor (opt = strtok(reload_opts, \" \");\n+\t     opt;\n+\t\t opt = strtok(NULL, \" \")) {\n+\n+\t\tif ((val = get_option(opt, \"channel=\")))\n+\t\t\tconf->channel = atoi(val);\n+\t\telse if ((val = get_option(opt, \"ht_capab=\")))\n+\t\t\tconf->ht_capab = atoi(val);\n+\t\telse if ((val = get_option(opt, \"ht_capab_mask=\")))\n+\t\t\tconf->ht_capab &= atoi(val);\n+\t\telse if ((val = get_option(opt, \"sec_chan=\")))\n+\t\t\tconf->secondary_channel = atoi(val);\n+\t\telse if ((val = get_option(opt, \"hw_mode=\")))\n+\t\t\tconf->hw_mode = atoi(val);\n+\t\telse if ((val = get_option(opt, \"ieee80211n=\")))\n+\t\t\tconf->ieee80211n = atoi(val);\n+\t\telse\n+\t\t\tbreak;\n+\t}\n+\n+\treturn conf;\n+}\n+\n+static int hostapd_ctrl_iface_update(struct hostapd_data *hapd, char *txt)\n+{\n+\tstruct hostapd_config * (*config_read_cb)(const char *config_fname);\n+\tstruct hostapd_iface *iface = hapd->iface;\n+\n+\tconfig_read_cb = iface->interfaces->config_read_cb;\n+\tiface->interfaces->config_read_cb = hostapd_ctrl_iface_config_read;\n+\treload_opts = txt;\n+\n+\thostapd_reload_config(iface);\n+\n+\tiface->interfaces->config_read_cb = config_read_cb;\n+}\n \n #ifdef NEED_AP_MLME\n static int hostapd_ctrl_iface_sa_query(struct hostapd_data *hapd,\n@@ -3771,6 +3828,8 @@ static int hostapd_ctrl_iface_receive_pr\n \t} else if (os_strncmp(buf, \"VENDOR \", 7) == 0) {\n \t\treply_len = hostapd_ctrl_iface_vendor(hapd, buf + 7, reply,\n \t\t\t\t\t\t      reply_size);\n+\t} else if (os_strncmp(buf, \"UPDATE \", 7) == 0) {\n+\t\thostapd_ctrl_iface_update(hapd, buf + 7);\n \t} else if (os_strcmp(buf, \"ERP_FLUSH\") == 0) {\n \t\tieee802_1x_erp_flush(hapd);\n #ifdef RADIUS_SERVER\n--- a/src/ap/ctrl_iface_ap.c\n+++ b/src/ap/ctrl_iface_ap.c\n@@ -927,7 +927,13 @@ int hostapd_parse_csa_settings(const cha\n \n int hostapd_ctrl_iface_stop_ap(struct hostapd_data *hapd)\n {\n-\treturn hostapd_drv_stop_ap(hapd);\n+\tstruct hostapd_iface *iface = hapd->iface;\n+\tint i;\n+\n+\tfor (i = 0; i < iface->num_bss; i++)\n+\t\thostapd_drv_stop_ap(iface->bss[i]);\n+\n+\treturn 0;\n }\n \n \n"
  },
  {
    "path": "package/network/services/hostapd/patches/370-ap_sta_support.patch",
    "content": "--- a/wpa_supplicant/Makefile\n+++ b/wpa_supplicant/Makefile\n@@ -108,6 +108,8 @@ OBJS_c += ../src/utils/common.o\n OBJS_c += ../src/common/cli.o\n OBJS += wmm_ac.o\n \n+OBJS += ../src/common/wpa_ctrl.o\n+\n ifndef CONFIG_OS\n ifdef CONFIG_NATIVE_WINDOWS\n CONFIG_OS=win32\n--- a/wpa_supplicant/bss.c\n+++ b/wpa_supplicant/bss.c\n@@ -11,6 +11,7 @@\n #include \"utils/common.h\"\n #include \"utils/eloop.h\"\n #include \"common/ieee802_11_defs.h\"\n+#include \"common/ieee802_11_common.h\"\n #include \"drivers/driver.h\"\n #include \"eap_peer/eap.h\"\n #include \"wpa_supplicant_i.h\"\n@@ -282,6 +283,10 @@ void calculate_update_time(const struct\n static void wpa_bss_copy_res(struct wpa_bss *dst, struct wpa_scan_res *src,\n \t\t\t     struct os_reltime *fetch_time)\n {\n+\tstruct ieee80211_ht_capabilities *capab;\n+\tstruct ieee80211_ht_operation *oper;\n+\tstruct ieee802_11_elems elems;\n+\n \tdst->flags = src->flags;\n \tos_memcpy(dst->bssid, src->bssid, ETH_ALEN);\n \tdst->freq = src->freq;\n@@ -294,6 +299,15 @@ static void wpa_bss_copy_res(struct wpa_\n \tdst->est_throughput = src->est_throughput;\n \tdst->snr = src->snr;\n \n+\tmemset(&elems, 0, sizeof(elems));\n+\tieee802_11_parse_elems((u8 *) (src + 1), src->ie_len, &elems, 0);\n+\tcapab = (struct ieee80211_ht_capabilities *) elems.ht_capabilities;\n+\toper = (struct ieee80211_ht_operation *) elems.ht_operation;\n+\tif (capab)\n+\t\tdst->ht_capab = le_to_host16(capab->ht_capabilities_info);\n+\tif (oper)\n+\t\tdst->ht_param = oper->ht_param;\n+\n \tcalculate_update_time(fetch_time, src->age, &dst->last_update);\n }\n \n--- a/wpa_supplicant/bss.h\n+++ b/wpa_supplicant/bss.h\n@@ -94,6 +94,10 @@ struct wpa_bss {\n \tu8 ssid[SSID_MAX_LEN];\n \t/** Length of SSID */\n \tsize_t ssid_len;\n+\t/** HT capabilities */\n+\tu16 ht_capab;\n+\t/* Five octets of HT Operation Information */\n+\tu8 ht_param;\n \t/** Frequency of the channel in MHz (e.g., 2412 = channel 1) */\n \tint freq;\n \t/** Beacon interval in TUs (host byte order) */\n--- a/wpa_supplicant/main.c\n+++ b/wpa_supplicant/main.c\n@@ -34,7 +34,7 @@ static void usage(void)\n \t       \"vW] [-P<pid file>] \"\n \t       \"[-g<global ctrl>] \\\\\\n\"\n \t       \"        [-G<group>] \\\\\\n\"\n-\t       \"        -i<ifname> -c<config file> [-C<ctrl>] [-D<driver>] \"\n+\t       \"        -i<ifname> -c<config file> [-C<ctrl>] [-D<driver>] [-H<hostapd path>] \"\n \t       \"[-p<driver_param>] \\\\\\n\"\n \t       \"        [-b<br_ifname>] [-e<entropy file>]\"\n #ifdef CONFIG_DEBUG_FILE\n@@ -74,6 +74,7 @@ static void usage(void)\n \t       \"  -g = global ctrl_interface\\n\"\n \t       \"  -G = global ctrl_interface group\\n\"\n \t       \"  -h = show this help text\\n\"\n+\t       \"  -H = connect to a hostapd instance to manage state changes\\n\"\n \t       \"  -i = interface name\\n\"\n \t       \"  -I = additional configuration file\\n\"\n \t       \"  -K = include keys (passwords, etc.) in debug output\\n\"\n@@ -201,7 +202,7 @@ int main(int argc, char *argv[])\n \n \tfor (;;) {\n \t\tc = getopt(argc, argv,\n-\t\t\t   \"b:Bc:C:D:de:f:g:G:hi:I:KLMm:No:O:p:P:qsTtuvW\");\n+\t\t\t   \"b:Bc:C:D:de:f:g:G:hH:i:I:KLMm:No:O:p:P:qsTtuvW\");\n \t\tif (c < 0)\n \t\t\tbreak;\n \t\tswitch (c) {\n@@ -248,6 +249,9 @@ int main(int argc, char *argv[])\n \t\t\tusage();\n \t\t\texitcode = 0;\n \t\t\tgoto out;\n+\t\tcase 'H':\n+\t\t\tiface->hostapd_ctrl = optarg;\n+\t\t\tbreak;\n \t\tcase 'i':\n \t\t\tiface->ifname = optarg;\n \t\t\tbreak;\n--- a/wpa_supplicant/wpa_supplicant.c\n+++ b/wpa_supplicant/wpa_supplicant.c\n@@ -130,6 +130,54 @@ static void wpas_update_fils_connect_par\n static void wpas_update_owe_connect_params(struct wpa_supplicant *wpa_s);\n #endif /* CONFIG_OWE */\n \n+static int hostapd_stop(struct wpa_supplicant *wpa_s)\n+{\n+\tconst char *cmd = \"STOP_AP\";\n+\tchar buf[256];\n+\tsize_t len = sizeof(buf);\n+\n+\tif (wpa_ctrl_request(wpa_s->hostapd, cmd, os_strlen(cmd), buf, &len, NULL) < 0) {\n+\t\twpa_printf(MSG_ERROR, \"\\nFailed to stop hostapd AP interfaces\\n\");\n+\t\treturn -1;\n+\t}\n+\treturn 0;\n+}\n+\n+static int hostapd_reload(struct wpa_supplicant *wpa_s, struct wpa_bss *bss)\n+{\n+\tchar *cmd = NULL;\n+\tchar buf[256];\n+\tsize_t len = sizeof(buf);\n+\tenum hostapd_hw_mode hw_mode;\n+\tu8 channel;\n+\tint sec_chan = 0;\n+\tint ret;\n+\n+\tif (!bss)\n+\t\treturn -1;\n+\n+\tif (bss->ht_param & HT_INFO_HT_PARAM_STA_CHNL_WIDTH) {\n+\t\tint sec = bss->ht_param & HT_INFO_HT_PARAM_SECONDARY_CHNL_OFF_MASK;\n+\t\tif (sec == HT_INFO_HT_PARAM_SECONDARY_CHNL_ABOVE)\n+\t\t\tsec_chan = 1;\n+\t\telse if (sec ==  HT_INFO_HT_PARAM_SECONDARY_CHNL_BELOW)\n+\t\t\tsec_chan = -1;\n+\t}\n+\n+\thw_mode = ieee80211_freq_to_chan(bss->freq, &channel);\n+\tif (asprintf(&cmd, \"UPDATE channel=%d sec_chan=%d hw_mode=%d\",\n+\t\t     channel, sec_chan, hw_mode) < 0)\n+\t\treturn -1;\n+\n+\tret = wpa_ctrl_request(wpa_s->hostapd, cmd, os_strlen(cmd), buf, &len, NULL);\n+\tfree(cmd);\n+\n+\tif (ret < 0) {\n+\t\twpa_printf(MSG_ERROR, \"\\nFailed to reload hostapd AP interfaces\\n\");\n+\t\treturn -1;\n+\t}\n+\treturn 0;\n+}\n \n #ifdef CONFIG_WEP\n /* Configure default/group WEP keys for static WEP */\n@@ -1015,6 +1063,8 @@ void wpa_supplicant_set_state(struct wpa\n \n \t\tsme_sched_obss_scan(wpa_s, 1);\n \n+\t\tif (wpa_s->hostapd)\n+\t\t\thostapd_reload(wpa_s, wpa_s->current_bss);\n #if defined(CONFIG_FILS) && defined(IEEE8021X_EAPOL)\n \t\tif (!fils_hlp_sent && ssid && ssid->eap.erp)\n \t\t\tupdate_fils_connect_params = true;\n@@ -1025,6 +1075,8 @@ void wpa_supplicant_set_state(struct wpa\n #endif /* CONFIG_OWE */\n \t} else if (state == WPA_DISCONNECTED || state == WPA_ASSOCIATING ||\n \t\t   state == WPA_ASSOCIATED) {\n+\t\tif (wpa_s->hostapd)\n+\t\t\thostapd_stop(wpa_s);\n \t\twpa_s->new_connection = 1;\n \t\twpa_drv_set_operstate(wpa_s, 0);\n #ifndef IEEE8021X_EAPOL\n@@ -2308,6 +2360,8 @@ void wpa_supplicant_associate(struct wpa\n \t\t\treturn;\n \t\t}\n \t\twpa_s->current_bss = bss;\n+\t\tif (wpa_s->hostapd)\n+\t\t\thostapd_reload(wpa_s, wpa_s->current_bss);\n #else /* CONFIG_MESH */\n \t\twpa_msg(wpa_s, MSG_ERROR,\n \t\t\t\"mesh mode support not included in the build\");\n@@ -6650,6 +6704,16 @@ static int wpa_supplicant_init_iface(str\n \t\t\t   sizeof(wpa_s->bridge_ifname));\n \t}\n \n+\tif (iface->hostapd_ctrl) {\n+\t\twpa_s->hostapd = wpa_ctrl_open(iface->hostapd_ctrl);\n+\t\tif (!wpa_s->hostapd) {\n+\t\t\twpa_printf(MSG_ERROR, \"\\nFailed to connect to hostapd\\n\");\n+\t\t\treturn -1;\n+\t\t}\n+\t\tif (hostapd_stop(wpa_s) < 0)\n+\t\t\treturn -1;\n+\t}\n+\n \t/* RSNA Supplicant Key Management - INITIALIZE */\n \teapol_sm_notify_portEnabled(wpa_s->eapol, false);\n \teapol_sm_notify_portValid(wpa_s->eapol, false);\n@@ -6987,6 +7051,11 @@ static void wpa_supplicant_deinit_iface(\n \tif (terminate)\n \t\twpa_msg(wpa_s, MSG_INFO, WPA_EVENT_TERMINATING);\n \n+\tif (wpa_s->hostapd) {\n+\t\twpa_ctrl_close(wpa_s->hostapd);\n+\t\twpa_s->hostapd = NULL;\n+\t}\n+\n \twpa_supplicant_ctrl_iface_deinit(wpa_s, wpa_s->ctrl_iface);\n \twpa_s->ctrl_iface = NULL;\n \n--- a/wpa_supplicant/wpa_supplicant_i.h\n+++ b/wpa_supplicant/wpa_supplicant_i.h\n@@ -104,6 +104,11 @@ struct wpa_interface {\n \tconst char *ifname;\n \n \t/**\n+\t * hostapd_ctrl - path to hostapd control socket for notification\n+\t */\n+\tconst char *hostapd_ctrl;\n+\n+\t/**\n \t * bridge_ifname - Optional bridge interface name\n \t *\n \t * If the driver interface (ifname) is included in a Linux bridge\n@@ -718,6 +723,8 @@ struct wpa_supplicant {\n #endif /* CONFIG_CTRL_IFACE_BINDER */\n \tchar bridge_ifname[16];\n \n+\tstruct wpa_ctrl *hostapd;\n+\n \tchar *confname;\n \tchar *confanother;\n \n--- a/hostapd/ctrl_iface.c\n+++ b/hostapd/ctrl_iface.c\n@@ -2889,6 +2889,12 @@ static int hostapd_ctrl_iface_chan_switc\n \t\treturn 0;\n \t}\n \n+\tif (os_strstr(pos, \" auto-ht\")) {\n+\t\tsettings.freq_params.ht_enabled = iface->conf->ieee80211n;\n+\t\tsettings.freq_params.vht_enabled = iface->conf->ieee80211ac;\n+\t\tsettings.freq_params.he_enabled = iface->conf->ieee80211ax;\n+\t}\n+\n \tfor (i = 0; i < iface->num_bss; i++) {\n \n \t\t/* Save CHAN_SWITCH VHT and HE config */\n--- a/src/ap/beacon.c\n+++ b/src/ap/beacon.c\n@@ -1791,11 +1791,6 @@ static int __ieee802_11_set_beacon(struc\n \t\treturn -1;\n \t}\n \n-\tif (hapd->csa_in_progress) {\n-\t\twpa_printf(MSG_ERROR, \"Cannot set beacons during CSA period\");\n-\t\treturn -1;\n-\t}\n-\n \thapd->beacon_set_done = 1;\n \n \tif (ieee802_11_build_ap_params(hapd, &params) < 0)\n--- a/wpa_supplicant/events.c\n+++ b/wpa_supplicant/events.c\n@@ -4891,6 +4891,60 @@ static void wpas_event_unprot_beacon(str\n }\n \n \n+static void\n+supplicant_ch_switch_started(struct wpa_supplicant *wpa_s,\n+\t\t\t    union wpa_event_data *data)\n+{\n+\tchar buf[256];\n+\tsize_t len = sizeof(buf);\n+\tchar *cmd = NULL;\n+\tint width = 20;\n+\tint ret;\n+\n+\tif (!wpa_s->hostapd)\n+\t\treturn;\n+\n+\twpa_msg(wpa_s, MSG_INFO, WPA_EVENT_CHANNEL_SWITCH\n+\t\t\"count=%d freq=%d ht_enabled=%d ch_offset=%d ch_width=%s cf1=%d cf2=%d\",\n+\t\tdata->ch_switch.count,\n+\t\tdata->ch_switch.freq,\n+\t\tdata->ch_switch.ht_enabled,\n+\t\tdata->ch_switch.ch_offset,\n+\t\tchannel_width_to_string(data->ch_switch.ch_width),\n+\t\tdata->ch_switch.cf1,\n+\t\tdata->ch_switch.cf2);\n+\n+\tswitch (data->ch_switch.ch_width) {\n+\tcase CHAN_WIDTH_20_NOHT:\n+\tcase CHAN_WIDTH_20:\n+\t\twidth = 20;\n+\t\tbreak;\n+\tcase CHAN_WIDTH_40:\n+\t\twidth = 40;\n+\t\tbreak;\n+\tcase CHAN_WIDTH_80:\n+\t\twidth = 80;\n+\t\tbreak;\n+\tcase CHAN_WIDTH_160:\n+\tcase CHAN_WIDTH_80P80:\n+\t\twidth = 160;\n+\t\tbreak;\n+\t}\n+\n+\tasprintf(&cmd, \"CHAN_SWITCH %d %d sec_channel_offset=%d center_freq1=%d center_freq2=%d, bandwidth=%d auto-ht\\n\",\n+\t\tdata->ch_switch.count - 1,\n+\t\tdata->ch_switch.freq,\n+\t\tdata->ch_switch.ch_offset,\n+\t\tdata->ch_switch.cf1,\n+\t\tdata->ch_switch.cf2,\n+\t\twidth);\n+\tret = wpa_ctrl_request(wpa_s->hostapd, cmd, os_strlen(cmd), buf, &len, NULL);\n+\tfree(cmd);\n+\n+\tif (ret < 0)\n+\t\twpa_printf(MSG_ERROR, \"\\nFailed to reload hostapd AP interfaces\\n\");\n+}\n+\n void supplicant_event(void *ctx, enum wpa_event_type event,\n \t\t      union wpa_event_data *data)\n {\n@@ -5206,8 +5260,10 @@ void supplicant_event(void *ctx, enum wp\n \t\t\tchannel_width_to_string(data->ch_switch.ch_width),\n \t\t\tdata->ch_switch.cf1,\n \t\t\tdata->ch_switch.cf2);\n-\t\tif (event == EVENT_CH_SWITCH_STARTED)\n+\t\tif (event == EVENT_CH_SWITCH_STARTED) {\n+\t\t\tsupplicant_ch_switch_started(wpa_s, data);\n \t\t\tbreak;\n+\t\t}\n \n \t\twpa_s->assoc_freq = data->ch_switch.freq;\n \t\twpa_s->current_ssid->frequency = data->ch_switch.freq;\n--- a/src/drivers/driver.h\n+++ b/src/drivers/driver.h\n@@ -5837,6 +5837,7 @@ union wpa_event_data {\n \n \t/**\n \t * struct ch_switch\n+\t * @count: Count until channel switch activates\n \t * @freq: Frequency of new channel in MHz\n \t * @ht_enabled: Whether this is an HT channel\n \t * @ch_offset: Secondary channel offset\n@@ -5845,6 +5846,7 @@ union wpa_event_data {\n \t * @cf2: Center frequency 2\n \t */\n \tstruct ch_switch {\n+\t\tint count;\n \t\tint freq;\n \t\tint ht_enabled;\n \t\tint ch_offset;\n--- a/src/drivers/driver_nl80211_event.c\n+++ b/src/drivers/driver_nl80211_event.c\n@@ -684,7 +684,7 @@ static void mlme_event_ch_switch(struct\n \t\t\t\t struct nlattr *ifindex, struct nlattr *freq,\n \t\t\t\t struct nlattr *type, struct nlattr *bw,\n \t\t\t\t struct nlattr *cf1, struct nlattr *cf2,\n-\t\t\t\t int finished)\n+\t\t\t\t struct nlattr *count, int finished)\n {\n \tstruct i802_bss *bss;\n \tunion wpa_event_data data;\n@@ -745,6 +745,8 @@ static void mlme_event_ch_switch(struct\n \t\tdata.ch_switch.cf1 = nla_get_u32(cf1);\n \tif (cf2)\n \t\tdata.ch_switch.cf2 = nla_get_u32(cf2);\n+\tif (count)\n+\t\tdata.ch_switch.count = nla_get_u32(count);\n \n \tif (finished)\n \t\tbss->freq = data.ch_switch.freq;\n@@ -3003,6 +3005,7 @@ static void do_process_drv_event(struct\n \t\t\t\t     tb[NL80211_ATTR_CHANNEL_WIDTH],\n \t\t\t\t     tb[NL80211_ATTR_CENTER_FREQ1],\n \t\t\t\t     tb[NL80211_ATTR_CENTER_FREQ2],\n+\t\t\t\t     tb[NL80211_ATTR_CH_SWITCH_COUNT],\n \t\t\t\t     0);\n \t\tbreak;\n \tcase NL80211_CMD_CH_SWITCH_NOTIFY:\n@@ -3013,6 +3016,7 @@ static void do_process_drv_event(struct\n \t\t\t\t     tb[NL80211_ATTR_CHANNEL_WIDTH],\n \t\t\t\t     tb[NL80211_ATTR_CENTER_FREQ1],\n \t\t\t\t     tb[NL80211_ATTR_CENTER_FREQ2],\n+\t\t\t\t     NULL,\n \t\t\t\t     1);\n \t\tbreak;\n \tcase NL80211_CMD_DISCONNECT:\n"
  },
  {
    "path": "package/network/services/hostapd/patches/380-disable_ctrl_iface_mib.patch",
    "content": "--- a/hostapd/Makefile\n+++ b/hostapd/Makefile\n@@ -221,6 +221,9 @@ endif\n ifdef CONFIG_NO_CTRL_IFACE\n CFLAGS += -DCONFIG_NO_CTRL_IFACE\n else\n+ifdef CONFIG_CTRL_IFACE_MIB\n+CFLAGS += -DCONFIG_CTRL_IFACE_MIB\n+endif\n ifeq ($(CONFIG_CTRL_IFACE), udp)\n CFLAGS += -DCONFIG_CTRL_IFACE_UDP\n else\n--- a/hostapd/ctrl_iface.c\n+++ b/hostapd/ctrl_iface.c\n@@ -3587,6 +3587,7 @@ static int hostapd_ctrl_iface_receive_pr\n \t\t\t\t\t\t      reply_size);\n \t} else if (os_strcmp(buf, \"STATUS-DRIVER\") == 0) {\n \t\treply_len = hostapd_drv_status(hapd, reply, reply_size);\n+#ifdef CONFIG_CTRL_IFACE_MIB\n \t} else if (os_strcmp(buf, \"MIB\") == 0) {\n \t\treply_len = ieee802_11_get_mib(hapd, reply, reply_size);\n \t\tif (reply_len >= 0) {\n@@ -3628,6 +3629,7 @@ static int hostapd_ctrl_iface_receive_pr\n \t} else if (os_strncmp(buf, \"STA-NEXT \", 9) == 0) {\n \t\treply_len = hostapd_ctrl_iface_sta_next(hapd, buf + 9, reply,\n \t\t\t\t\t\t\treply_size);\n+#endif\n \t} else if (os_strcmp(buf, \"ATTACH\") == 0) {\n \t\tif (hostapd_ctrl_iface_attach(hapd, from, fromlen, NULL))\n \t\t\treply_len = -1;\n--- a/wpa_supplicant/Makefile\n+++ b/wpa_supplicant/Makefile\n@@ -958,6 +958,9 @@ ifdef CONFIG_FILS\n OBJS += ../src/ap/fils_hlp.o\n endif\n ifdef CONFIG_CTRL_IFACE\n+ifdef CONFIG_CTRL_IFACE_MIB\n+CFLAGS += -DCONFIG_CTRL_IFACE_MIB\n+endif\n OBJS += ../src/ap/ctrl_iface_ap.o\n endif\n \n--- a/wpa_supplicant/ctrl_iface.c\n+++ b/wpa_supplicant/ctrl_iface.c\n@@ -2314,7 +2314,7 @@ static int wpa_supplicant_ctrl_iface_sta\n \t\t\tpos += ret;\n \t\t}\n \n-#ifdef CONFIG_AP\n+#if defined(CONFIG_AP) && defined(CONFIG_CTRL_IFACE_MIB)\n \t\tif (wpa_s->ap_iface) {\n \t\t\tpos += ap_ctrl_iface_wpa_get_status(wpa_s, pos,\n \t\t\t\t\t\t\t    end - pos,\n@@ -11494,6 +11494,7 @@ char * wpa_supplicant_ctrl_iface_process\n \t\t\treply_len = -1;\n \t} else if (os_strncmp(buf, \"NOTE \", 5) == 0) {\n \t\twpa_printf(MSG_INFO, \"NOTE: %s\", buf + 5);\n+#ifdef CONFIG_CTRL_IFACE_MIB\n \t} else if (os_strcmp(buf, \"MIB\") == 0) {\n \t\treply_len = wpa_sm_get_mib(wpa_s->wpa, reply, reply_size);\n \t\tif (reply_len >= 0) {\n@@ -11506,6 +11507,7 @@ char * wpa_supplicant_ctrl_iface_process\n \t\t\t\treply_size - reply_len);\n #endif /* CONFIG_MACSEC */\n \t\t}\n+#endif\n \t} else if (os_strncmp(buf, \"STATUS\", 6) == 0) {\n \t\treply_len = wpa_supplicant_ctrl_iface_status(\n \t\t\twpa_s, buf + 6, reply, reply_size);\n@@ -11994,6 +11996,7 @@ char * wpa_supplicant_ctrl_iface_process\n \t\treply_len = wpa_supplicant_ctrl_iface_bss(\n \t\t\twpa_s, buf + 4, reply, reply_size);\n #ifdef CONFIG_AP\n+#ifdef CONFIG_CTRL_IFACE_MIB\n \t} else if (os_strcmp(buf, \"STA-FIRST\") == 0) {\n \t\treply_len = ap_ctrl_iface_sta_first(wpa_s, reply, reply_size);\n \t} else if (os_strncmp(buf, \"STA \", 4) == 0) {\n@@ -12002,12 +12005,15 @@ char * wpa_supplicant_ctrl_iface_process\n \t} else if (os_strncmp(buf, \"STA-NEXT \", 9) == 0) {\n \t\treply_len = ap_ctrl_iface_sta_next(wpa_s, buf + 9, reply,\n \t\t\t\t\t\t   reply_size);\n+#endif\n+#ifdef CONFIG_CTRL_IFACE_MIB\n \t} else if (os_strncmp(buf, \"DEAUTHENTICATE \", 15) == 0) {\n \t\tif (ap_ctrl_iface_sta_deauthenticate(wpa_s, buf + 15))\n \t\t\treply_len = -1;\n \t} else if (os_strncmp(buf, \"DISASSOCIATE \", 13) == 0) {\n \t\tif (ap_ctrl_iface_sta_disassociate(wpa_s, buf + 13))\n \t\t\treply_len = -1;\n+#endif\n \t} else if (os_strncmp(buf, \"CHAN_SWITCH \", 12) == 0) {\n \t\tif (ap_ctrl_iface_chanswitch(wpa_s, buf + 12))\n \t\t\treply_len = -1;\n--- a/src/ap/ctrl_iface_ap.c\n+++ b/src/ap/ctrl_iface_ap.c\n@@ -25,6 +25,7 @@\n #include \"mbo_ap.h\"\n #include \"taxonomy.h\"\n \n+#ifdef CONFIG_CTRL_IFACE_MIB\n \n static size_t hostapd_write_ht_mcs_bitmask(char *buf, size_t buflen,\n \t\t\t\t\t   size_t curr_len, const u8 *mcs_set)\n@@ -459,6 +460,7 @@ int hostapd_ctrl_iface_sta_next(struct h\n \treturn hostapd_ctrl_iface_sta_mib(hapd, sta->next, buf, buflen);\n }\n \n+#endif\n \n #ifdef CONFIG_P2P_MANAGER\n static int p2p_manager_disconnect(struct hostapd_data *hapd, u16 stype,\n@@ -815,12 +817,12 @@ int hostapd_ctrl_iface_status(struct hos\n \t\t\treturn len;\n \t\tlen += ret;\n \t}\n-\n+#ifdef CONFIG_CTRL_IFACE_MIB\n \tif (iface->conf->ieee80211n && !hapd->conf->disable_11n && mode) {\n \t\tlen = hostapd_write_ht_mcs_bitmask(buf, buflen, len,\n \t\t\t\t\t\t   mode->mcs_set);\n \t}\n-\n+#endif /* CONFIG_CTRL_IFACE_MIB */\n \tif (iface->current_rates && iface->num_rates) {\n \t\tret = os_snprintf(buf + len, buflen - len, \"supported_rates=\");\n \t\tif (os_snprintf_error(buflen - len, ret))\n--- a/src/ap/ieee802_1x.c\n+++ b/src/ap/ieee802_1x.c\n@@ -2712,6 +2712,7 @@ static const char * bool_txt(bool val)\n \treturn val ? \"TRUE\" : \"FALSE\";\n }\n \n+#ifdef CONFIG_CTRL_IFACE_MIB\n \n int ieee802_1x_get_mib(struct hostapd_data *hapd, char *buf, size_t buflen)\n {\n@@ -2898,6 +2899,7 @@ int ieee802_1x_get_mib_sta(struct hostap\n \treturn len;\n }\n \n+#endif\n \n #ifdef CONFIG_HS20\n static void ieee802_1x_wnm_notif_send(void *eloop_ctx, void *timeout_ctx)\n--- a/src/ap/wpa_auth.c\n+++ b/src/ap/wpa_auth.c\n@@ -4519,6 +4519,7 @@ static const char * wpa_bool_txt(int val\n \treturn val ? \"TRUE\" : \"FALSE\";\n }\n \n+#ifdef CONFIG_CTRL_IFACE_MIB\n \n #define RSN_SUITE \"%02x-%02x-%02x-%d\"\n #define RSN_SUITE_ARG(s) \\\n@@ -4669,7 +4670,7 @@ int wpa_get_mib_sta(struct wpa_state_mac\n \n \treturn len;\n }\n-\n+#endif\n \n void wpa_auth_countermeasures_start(struct wpa_authenticator *wpa_auth)\n {\n--- a/src/rsn_supp/wpa.c\n+++ b/src/rsn_supp/wpa.c\n@@ -2777,6 +2777,8 @@ static u32 wpa_key_mgmt_suite(struct wpa\n }\n \n \n+#ifdef CONFIG_CTRL_IFACE_MIB\n+\n #define RSN_SUITE \"%02x-%02x-%02x-%d\"\n #define RSN_SUITE_ARG(s) \\\n ((s) >> 24) & 0xff, ((s) >> 16) & 0xff, ((s) >> 8) & 0xff, (s) & 0xff\n@@ -2858,6 +2860,7 @@ int wpa_sm_get_mib(struct wpa_sm *sm, ch\n \n \treturn (int) len;\n }\n+#endif\n #endif /* CONFIG_CTRL_IFACE */\n \n \n--- a/wpa_supplicant/ap.c\n+++ b/wpa_supplicant/ap.c\n@@ -1462,7 +1462,7 @@ int wpas_ap_wps_nfc_report_handover(stru\n #endif /* CONFIG_WPS */\n \n \n-#ifdef CONFIG_CTRL_IFACE\n+#if defined(CONFIG_CTRL_IFACE) && defined(CONFIG_CTRL_IFACE_MIB)\n \n int ap_ctrl_iface_sta_first(struct wpa_supplicant *wpa_s,\n \t\t\t    char *buf, size_t buflen)\n"
  },
  {
    "path": "package/network/services/hostapd/patches/381-hostapd_cli_UNKNOWN-COMMAND.patch",
    "content": "--- a/hostapd/hostapd_cli.c\n+++ b/hostapd/hostapd_cli.c\n@@ -744,7 +744,7 @@ static int wpa_ctrl_command_sta(struct w\n \t}\n \n \tbuf[len] = '\\0';\n-\tif (memcmp(buf, \"FAIL\", 4) == 0)\n+\tif (memcmp(buf, \"FAIL\", 4) == 0 || memcmp(buf, \"UNKNOWN COMMAND\", 15) == 0)\n \t\treturn -1;\n \tif (print)\n \t\tprintf(\"%s\", buf);\n"
  },
  {
    "path": "package/network/services/hostapd/patches/390-wpa_ie_cap_workaround.patch",
    "content": "--- a/src/common/wpa_common.c\n+++ b/src/common/wpa_common.c\n@@ -2444,6 +2444,31 @@ u32 wpa_akm_to_suite(int akm)\n }\n \n \n+static void wpa_fixup_wpa_ie_rsn(u8 *assoc_ie, const u8 *wpa_msg_ie,\n+\t\t\t\t size_t rsn_ie_len)\n+{\n+\tint pos, count;\n+\n+\tpos = sizeof(struct rsn_ie_hdr) + RSN_SELECTOR_LEN;\n+\tif (rsn_ie_len < pos + 2)\n+\t\treturn;\n+\n+\tcount = WPA_GET_LE16(wpa_msg_ie + pos);\n+\tpos += 2 + count * RSN_SELECTOR_LEN;\n+\tif (rsn_ie_len < pos + 2)\n+\t\treturn;\n+\n+\tcount = WPA_GET_LE16(wpa_msg_ie + pos);\n+\tpos += 2 + count * RSN_SELECTOR_LEN;\n+\tif (rsn_ie_len < pos + 2)\n+\t\treturn;\n+\n+\tif (!assoc_ie[pos] && !assoc_ie[pos + 1] &&\n+\t    (wpa_msg_ie[pos] || wpa_msg_ie[pos + 1]))\n+\t\tmemcpy(&assoc_ie[pos], &wpa_msg_ie[pos], 2);\n+}\n+\n+\n int wpa_compare_rsn_ie(int ft_initial_assoc,\n \t\t       const u8 *ie1, size_t ie1len,\n \t\t       const u8 *ie2, size_t ie2len)\n@@ -2451,8 +2476,19 @@ int wpa_compare_rsn_ie(int ft_initial_as\n \tif (ie1 == NULL || ie2 == NULL)\n \t\treturn -1;\n \n-\tif (ie1len == ie2len && os_memcmp(ie1, ie2, ie1len) == 0)\n-\t\treturn 0; /* identical IEs */\n+\tif (ie1len == ie2len) {\n+\t\tu8 *ie_tmp;\n+\n+\t\tif (os_memcmp(ie1, ie2, ie1len) == 0)\n+\t\t\treturn 0; /* identical IEs */\n+\n+\t\tie_tmp = alloca(ie1len);\n+\t\tmemcpy(ie_tmp, ie1, ie1len);\n+\t\twpa_fixup_wpa_ie_rsn(ie_tmp, ie2, ie1len);\n+\n+\t\tif (os_memcmp(ie_tmp, ie2, ie1len) == 0)\n+\t\t\treturn 0; /* only mismatch in RSN capabilties */\n+\t}\n \n #ifdef CONFIG_IEEE80211R\n \tif (ft_initial_assoc) {\n"
  },
  {
    "path": "package/network/services/hostapd/patches/400-wps_single_auth_enc_type.patch",
    "content": "--- a/src/ap/wps_hostapd.c\n+++ b/src/ap/wps_hostapd.c\n@@ -394,9 +394,8 @@ static int hapd_wps_reconfig_in_memory(s\n \t\t\t\tbss->wpa_pairwise |= WPA_CIPHER_GCMP;\n \t\t\telse\n \t\t\t\tbss->wpa_pairwise |= WPA_CIPHER_CCMP;\n-\t\t}\n #ifndef CONFIG_NO_TKIP\n-\t\tif (cred->encr_type & WPS_ENCR_TKIP)\n+\t\t} else if (cred->encr_type & WPS_ENCR_TKIP)\n \t\t\tbss->wpa_pairwise |= WPA_CIPHER_TKIP;\n #endif /* CONFIG_NO_TKIP */\n \t\tbss->rsn_pairwise = bss->wpa_pairwise;\n@@ -1180,8 +1179,7 @@ int hostapd_init_wps(struct hostapd_data\n \t\t\t\t\t  WPA_CIPHER_GCMP_256)) {\n \t\t\twps->encr_types |= WPS_ENCR_AES;\n \t\t\twps->encr_types_rsn |= WPS_ENCR_AES;\n-\t\t}\n-\t\tif (conf->rsn_pairwise & WPA_CIPHER_TKIP) {\n+\t\t} else if (conf->rsn_pairwise & WPA_CIPHER_TKIP) {\n #ifdef CONFIG_NO_TKIP\n \t\t\twpa_printf(MSG_INFO, \"WPS: TKIP not supported\");\n \t\t\tgoto fail;\n"
  },
  {
    "path": "package/network/services/hostapd/patches/410-limit_debug_messages.patch",
    "content": "--- a/src/utils/wpa_debug.c\n+++ b/src/utils/wpa_debug.c\n@@ -206,7 +206,7 @@ void wpa_debug_close_linux_tracing(void)\n  *\n  * Note: New line '\\n' is added to the end of the text when printing to stdout.\n  */\n-void wpa_printf(int level, const char *fmt, ...)\n+void _wpa_printf(int level, const char *fmt, ...)\n {\n \tva_list ap;\n \n@@ -255,7 +255,7 @@ void wpa_printf(int level, const char *f\n }\n \n \n-static void _wpa_hexdump(int level, const char *title, const u8 *buf,\n+void _wpa_hexdump(int level, const char *title, const u8 *buf,\n \t\t\t size_t len, int show, int only_syslog)\n {\n \tsize_t i;\n@@ -382,19 +382,7 @@ static void _wpa_hexdump(int level, cons\n #endif /* CONFIG_ANDROID_LOG */\n }\n \n-void wpa_hexdump(int level, const char *title, const void *buf, size_t len)\n-{\n-\t_wpa_hexdump(level, title, buf, len, 1, 0);\n-}\n-\n-\n-void wpa_hexdump_key(int level, const char *title, const void *buf, size_t len)\n-{\n-\t_wpa_hexdump(level, title, buf, len, wpa_debug_show_keys, 0);\n-}\n-\n-\n-static void _wpa_hexdump_ascii(int level, const char *title, const void *buf,\n+void _wpa_hexdump_ascii(int level, const char *title, const void *buf,\n \t\t\t       size_t len, int show)\n {\n \tsize_t i, llen;\n@@ -507,20 +495,6 @@ file_done:\n }\n \n \n-void wpa_hexdump_ascii(int level, const char *title, const void *buf,\n-\t\t       size_t len)\n-{\n-\t_wpa_hexdump_ascii(level, title, buf, len, 1);\n-}\n-\n-\n-void wpa_hexdump_ascii_key(int level, const char *title, const void *buf,\n-\t\t\t   size_t len)\n-{\n-\t_wpa_hexdump_ascii(level, title, buf, len, wpa_debug_show_keys);\n-}\n-\n-\n #ifdef CONFIG_DEBUG_FILE\n static char *last_path = NULL;\n #endif /* CONFIG_DEBUG_FILE */\n@@ -636,7 +610,7 @@ void wpa_msg_register_ifname_cb(wpa_msg_\n }\n \n \n-void wpa_msg(void *ctx, int level, const char *fmt, ...)\n+void _wpa_msg(void *ctx, int level, const char *fmt, ...)\n {\n \tva_list ap;\n \tchar *buf;\n@@ -674,7 +648,7 @@ void wpa_msg(void *ctx, int level, const\n }\n \n \n-void wpa_msg_ctrl(void *ctx, int level, const char *fmt, ...)\n+void _wpa_msg_ctrl(void *ctx, int level, const char *fmt, ...)\n {\n \tva_list ap;\n \tchar *buf;\n--- a/src/utils/wpa_debug.h\n+++ b/src/utils/wpa_debug.h\n@@ -50,6 +50,17 @@ int wpa_debug_reopen_file(void);\n void wpa_debug_close_file(void);\n void wpa_debug_setup_stdout(void);\n \n+/* internal */\n+void _wpa_hexdump(int level, const char *title, const u8 *buf,\n+\t\t  size_t len, int show, int only_syslog);\n+void _wpa_hexdump_ascii(int level, const char *title, const void *buf,\n+\t\t\tsize_t len, int show);\n+extern int wpa_debug_show_keys;\n+\n+#ifndef CONFIG_MSG_MIN_PRIORITY\n+#define CONFIG_MSG_MIN_PRIORITY 0\n+#endif\n+\n /**\n  * wpa_debug_printf_timestamp - Print timestamp for debug output\n  *\n@@ -70,9 +81,15 @@ void wpa_debug_print_timestamp(void);\n  *\n  * Note: New line '\\n' is added to the end of the text when printing to stdout.\n  */\n-void wpa_printf(int level, const char *fmt, ...)\n+void _wpa_printf(int level, const char *fmt, ...)\n PRINTF_FORMAT(2, 3);\n \n+#define wpa_printf(level, ...)\t\t\t\t\t\t\\\n+\tdo {\t\t\t\t\t\t\t\t\\\n+\t\tif (level >= CONFIG_MSG_MIN_PRIORITY)\t\t\t\\\n+\t\t\t_wpa_printf(level, __VA_ARGS__);\t\t\\\n+\t} while(0)\n+\n /**\n  * wpa_hexdump - conditional hex dump\n  * @level: priority level (MSG_*) of the message\n@@ -84,7 +101,13 @@ PRINTF_FORMAT(2, 3);\n  * output may be directed to stdout, stderr, and/or syslog based on\n  * configuration. The contents of buf is printed out has hex dump.\n  */\n-void wpa_hexdump(int level, const char *title, const void *buf, size_t len);\n+static inline void wpa_hexdump(int level, const char *title, const void *buf, size_t len)\n+{\n+\tif (level < CONFIG_MSG_MIN_PRIORITY)\n+\t\treturn;\n+\n+\t_wpa_hexdump(level, title, buf, len, 1, 1);\n+}\n \n static inline void wpa_hexdump_buf(int level, const char *title,\n \t\t\t\t   const struct wpabuf *buf)\n@@ -106,7 +129,13 @@ static inline void wpa_hexdump_buf(int l\n  * like wpa_hexdump(), but by default, does not include secret keys (passwords,\n  * etc.) in debug output.\n  */\n-void wpa_hexdump_key(int level, const char *title, const void *buf, size_t len);\n+static inline void wpa_hexdump_key(int level, const char *title, const u8 *buf, size_t len)\n+{\n+\tif (level < CONFIG_MSG_MIN_PRIORITY)\n+\t\treturn;\n+\n+\t_wpa_hexdump(level, title, buf, len, wpa_debug_show_keys, 1);\n+}\n \n static inline void wpa_hexdump_buf_key(int level, const char *title,\n \t\t\t\t       const struct wpabuf *buf)\n@@ -128,8 +157,14 @@ static inline void wpa_hexdump_buf_key(i\n  * the hex numbers and ASCII characters (for printable range) are shown. 16\n  * bytes per line will be shown.\n  */\n-void wpa_hexdump_ascii(int level, const char *title, const void *buf,\n-\t\t       size_t len);\n+static inline void wpa_hexdump_ascii(int level, const char *title,\n+\t\t\t\t     const u8 *buf, size_t len)\n+{\n+\tif (level < CONFIG_MSG_MIN_PRIORITY)\n+\t\treturn;\n+\n+\t_wpa_hexdump_ascii(level, title, buf, len, 1);\n+}\n \n /**\n  * wpa_hexdump_ascii_key - conditional hex dump, hide keys\n@@ -145,8 +180,14 @@ void wpa_hexdump_ascii(int level, const\n  * bytes per line will be shown. This works like wpa_hexdump_ascii(), but by\n  * default, does not include secret keys (passwords, etc.) in debug output.\n  */\n-void wpa_hexdump_ascii_key(int level, const char *title, const void *buf,\n-\t\t\t   size_t len);\n+static inline void wpa_hexdump_ascii_key(int level, const char *title,\n+\t\t\t\t\t const u8 *buf, size_t len)\n+{\n+\tif (level < CONFIG_MSG_MIN_PRIORITY)\n+\t\treturn;\n+\n+\t_wpa_hexdump_ascii(level, title, buf, len, wpa_debug_show_keys);\n+}\n \n /*\n  * wpa_dbg() behaves like wpa_msg(), but it can be removed from build to reduce\n@@ -183,7 +224,12 @@ void wpa_hexdump_ascii_key(int level, co\n  *\n  * Note: New line '\\n' is added to the end of the text when printing to stdout.\n  */\n-void wpa_msg(void *ctx, int level, const char *fmt, ...) PRINTF_FORMAT(3, 4);\n+void _wpa_msg(void *ctx, int level, const char *fmt, ...) PRINTF_FORMAT(3, 4);\n+#define wpa_msg(ctx, level, ...)\t\t\t\t\t\\\n+\tdo {\t\t\t\t\t\t\t\t\\\n+\t\tif (level >= CONFIG_MSG_MIN_PRIORITY)\t\t\t\\\n+\t\t\t_wpa_msg(ctx, level, __VA_ARGS__);\t\t\\\n+\t} while(0)\n \n /**\n  * wpa_msg_ctrl - Conditional printf for ctrl_iface monitors\n@@ -197,8 +243,13 @@ void wpa_msg(void *ctx, int level, const\n  * attached ctrl_iface monitors. In other words, it can be used for frequent\n  * events that do not need to be sent to syslog.\n  */\n-void wpa_msg_ctrl(void *ctx, int level, const char *fmt, ...)\n+void _wpa_msg_ctrl(void *ctx, int level, const char *fmt, ...)\n PRINTF_FORMAT(3, 4);\n+#define wpa_msg_ctrl(ctx, level, ...)\t\t\t\t\t\\\n+\tdo {\t\t\t\t\t\t\t\t\\\n+\t\tif (level >= CONFIG_MSG_MIN_PRIORITY)\t\t\t\\\n+\t\t\t_wpa_msg_ctrl(ctx, level, __VA_ARGS__);\t\t\\\n+\t} while(0)\n \n /**\n  * wpa_msg_global - Global printf for ctrl_iface monitors\n"
  },
  {
    "path": "package/network/services/hostapd/patches/420-indicate-features.patch",
    "content": "--- a/hostapd/main.c\n+++ b/hostapd/main.c\n@@ -15,6 +15,7 @@\n #include \"utils/common.h\"\n #include \"utils/eloop.h\"\n #include \"utils/uuid.h\"\n+#include \"utils/build_features.h\"\n #include \"crypto/random.h\"\n #include \"crypto/tls.h\"\n #include \"common/version.h\"\n@@ -691,7 +692,7 @@ int main(int argc, char *argv[])\n \twpa_supplicant_event = hostapd_wpa_event;\n \twpa_supplicant_event_global = hostapd_wpa_event_global;\n \tfor (;;) {\n-\t\tc = getopt(argc, argv, \"b:Bde:f:hi:KP:sSTtu:vg:G:\");\n+\t\tc = getopt(argc, argv, \"b:Bde:f:hi:KP:sSTtu:g:G:v::\");\n \t\tif (c < 0)\n \t\t\tbreak;\n \t\tswitch (c) {\n@@ -728,6 +729,8 @@ int main(int argc, char *argv[])\n \t\t\tbreak;\n #endif /* CONFIG_DEBUG_LINUX_TRACING */\n \t\tcase 'v':\n+\t\t\tif (optarg)\n+\t\t\t\texit(!has_feature(optarg));\n \t\t\tshow_version();\n \t\t\texit(1);\n \t\t\tbreak;\n--- a/wpa_supplicant/main.c\n+++ b/wpa_supplicant/main.c\n@@ -12,6 +12,7 @@\n #endif /* __linux__ */\n \n #include \"common.h\"\n+#include \"build_features.h\"\n #include \"fst/fst.h\"\n #include \"wpa_supplicant_i.h\"\n #include \"driver_i.h\"\n@@ -202,7 +203,7 @@ int main(int argc, char *argv[])\n \n \tfor (;;) {\n \t\tc = getopt(argc, argv,\n-\t\t\t   \"b:Bc:C:D:de:f:g:G:hH:i:I:KLMm:No:O:p:P:qsTtuvW\");\n+\t\t\t   \"b:Bc:C:D:de:f:g:G:hH:i:I:KLMm:No:O:p:P:qsTtuv::W\");\n \t\tif (c < 0)\n \t\t\tbreak;\n \t\tswitch (c) {\n@@ -305,8 +306,12 @@ int main(int argc, char *argv[])\n \t\t\tbreak;\n #endif /* CONFIG_CTRL_IFACE_DBUS_NEW */\n \t\tcase 'v':\n-\t\t\tprintf(\"%s\\n\", wpa_supplicant_version);\n-\t\t\texitcode = 0;\n+\t\t\tif (optarg) {\n+\t\t\t\texitcode = !has_feature(optarg);\n+\t\t\t} else {\n+\t\t\t\tprintf(\"%s\\n\", wpa_supplicant_version);\n+\t\t\t\texitcode = 0;\n+\t\t\t}\n \t\t\tgoto out;\n \t\tcase 'W':\n \t\t\tparams.wait_for_monitor++;\n"
  },
  {
    "path": "package/network/services/hostapd/patches/430-hostapd_cli_ifdef.patch",
    "content": "--- a/hostapd/hostapd_cli.c\n+++ b/hostapd/hostapd_cli.c\n@@ -388,7 +388,6 @@ static int hostapd_cli_cmd_disassociate(\n }\n \n \n-#ifdef CONFIG_TAXONOMY\n static int hostapd_cli_cmd_signature(struct wpa_ctrl *ctrl, int argc,\n \t\t\t\t     char *argv[])\n {\n@@ -401,7 +400,6 @@ static int hostapd_cli_cmd_signature(str\n \tos_snprintf(buf, sizeof(buf), \"SIGNATURE %s\", argv[0]);\n \treturn wpa_ctrl_command(ctrl, buf);\n }\n-#endif /* CONFIG_TAXONOMY */\n \n \n static int hostapd_cli_cmd_sa_query(struct wpa_ctrl *ctrl, int argc,\n@@ -418,7 +416,6 @@ static int hostapd_cli_cmd_sa_query(stru\n }\n \n \n-#ifdef CONFIG_WPS\n static int hostapd_cli_cmd_wps_pin(struct wpa_ctrl *ctrl, int argc,\n \t\t\t\t   char *argv[])\n {\n@@ -644,7 +641,6 @@ static int hostapd_cli_cmd_wps_config(st\n \t\t\t ssid_hex, argv[1]);\n \treturn wpa_ctrl_command(ctrl, buf);\n }\n-#endif /* CONFIG_WPS */\n \n \n static int hostapd_cli_cmd_disassoc_imminent(struct wpa_ctrl *ctrl, int argc,\n@@ -1579,13 +1575,10 @@ static const struct hostapd_cli_cmd host\n \t{ \"disassociate\", hostapd_cli_cmd_disassociate,\n \t  hostapd_complete_stations,\n \t  \"<addr> = disassociate a station\" },\n-#ifdef CONFIG_TAXONOMY\n \t{ \"signature\", hostapd_cli_cmd_signature, hostapd_complete_stations,\n \t  \"<addr> = get taxonomy signature for a station\" },\n-#endif /* CONFIG_TAXONOMY */\n \t{ \"sa_query\", hostapd_cli_cmd_sa_query, hostapd_complete_stations,\n \t  \"<addr> = send SA Query to a station\" },\n-#ifdef CONFIG_WPS\n \t{ \"wps_pin\", hostapd_cli_cmd_wps_pin, NULL,\n \t  \"<uuid> <pin> [timeout] [addr] = add WPS Enrollee PIN\" },\n \t{ \"wps_check_pin\", hostapd_cli_cmd_wps_check_pin, NULL,\n@@ -1610,7 +1603,6 @@ static const struct hostapd_cli_cmd host\n \t  \"<SSID> <auth> <encr> <key> = configure AP\" },\n \t{ \"wps_get_status\", hostapd_cli_cmd_wps_get_status, NULL,\n \t  \"= show current WPS status\" },\n-#endif /* CONFIG_WPS */\n \t{ \"disassoc_imminent\", hostapd_cli_cmd_disassoc_imminent, NULL,\n \t  \"= send Disassociation Imminent notification\" },\n \t{ \"ess_disassoc\", hostapd_cli_cmd_ess_disassoc, NULL,\n"
  },
  {
    "path": "package/network/services/hostapd/patches/431-wpa_cli_ifdef.patch",
    "content": "--- a/wpa_supplicant/wpa_cli.c\n+++ b/wpa_supplicant/wpa_cli.c\n@@ -26,6 +26,15 @@\n #include <cutils/properties.h>\n #endif /* ANDROID */\n \n+#ifndef CONFIG_P2P\n+#define CONFIG_P2P\n+#endif\n+#ifndef CONFIG_AP\n+#define CONFIG_AP\n+#endif\n+#ifndef CONFIG_MESH\n+#define CONFIG_MESH\n+#endif\n \n static const char *const wpa_cli_version =\n \"wpa_cli v\" VERSION_STR \"\\n\"\n"
  },
  {
    "path": "package/network/services/hostapd/patches/432-missing-typedef.patch",
    "content": "--- a/src/drivers/linux_wext.h\n+++ b/src/drivers/linux_wext.h\n@@ -26,6 +26,7 @@ typedef int32_t __s32;\n typedef uint16_t __u16;\n typedef int16_t __s16;\n typedef uint8_t __u8;\n+typedef int8_t __s8;\n #ifndef __user\n #define __user\n #endif /* __user */\n"
  },
  {
    "path": "package/network/services/hostapd/patches/450-scan_wait.patch",
    "content": "--- a/hostapd/main.c\n+++ b/hostapd/main.c\n@@ -39,6 +39,8 @@ struct hapd_global {\n };\n \n static struct hapd_global global;\n+static int daemonize = 0;\n+static char *pid_file = NULL;\n \n \n #ifndef CONFIG_NO_HOSTAPD_LOGGER\n@@ -146,6 +148,14 @@ static void hostapd_logger_cb(void *ctx,\n }\n #endif /* CONFIG_NO_HOSTAPD_LOGGER */\n \n+static void hostapd_setup_complete_cb(void *ctx)\n+{\n+\tif (daemonize && os_daemonize(pid_file)) {\n+\t\tperror(\"daemon\");\n+\t\treturn;\n+\t}\n+\tdaemonize = 0;\n+}\n \n /**\n  * hostapd_driver_init - Preparate driver interface\n@@ -164,6 +174,8 @@ static int hostapd_driver_init(struct ho\n \t\treturn -1;\n \t}\n \n+\thapd->setup_complete_cb = hostapd_setup_complete_cb;\n+\n \t/* Initialize the driver interface */\n \tif (!(b[0] | b[1] | b[2] | b[3] | b[4] | b[5]))\n \t\tb = NULL;\n@@ -404,8 +416,6 @@ static void hostapd_global_deinit(const\n #endif /* CONFIG_NATIVE_WINDOWS */\n \n \teap_server_unregister_methods();\n-\n-\tos_daemonize_terminate(pid_file);\n }\n \n \n@@ -431,18 +441,6 @@ static int hostapd_global_run(struct hap\n \t}\n #endif /* EAP_SERVER_TNC */\n \n-\tif (daemonize) {\n-\t\tif (os_daemonize(pid_file)) {\n-\t\t\twpa_printf(MSG_ERROR, \"daemon: %s\", strerror(errno));\n-\t\t\treturn -1;\n-\t\t}\n-\t\tif (eloop_sock_requeue()) {\n-\t\t\twpa_printf(MSG_ERROR, \"eloop_sock_requeue: %s\",\n-\t\t\t\t   strerror(errno));\n-\t\t\treturn -1;\n-\t\t}\n-\t}\n-\n \teloop_run();\n \n \treturn 0;\n@@ -645,8 +643,7 @@ int main(int argc, char *argv[])\n \tstruct hapd_interfaces interfaces;\n \tint ret = 1;\n \tsize_t i, j;\n-\tint c, debug = 0, daemonize = 0;\n-\tchar *pid_file = NULL;\n+\tint c, debug = 0;\n \tconst char *log_file = NULL;\n \tconst char *entropy_file = NULL;\n \tchar **bss_config = NULL, **tmp_bss;\n"
  },
  {
    "path": "package/network/services/hostapd/patches/460-wpa_supplicant-add-new-config-params-to-be-used-with.patch",
    "content": "From 4bb69d15477e0f2b00e166845341dc933de47c58 Mon Sep 17 00:00:00 2001\nFrom: Antonio Quartulli <ordex@autistici.org>\nDate: Sun, 3 Jun 2012 18:22:56 +0200\nSubject: [PATCHv2 601/602] wpa_supplicant: add new config params to be used\n with the ibss join command\n\nSigned-hostap: Antonio Quartulli <ordex@autistici.org>\n---\n src/drivers/driver.h            |    6 +++\n wpa_supplicant/config.c         |   96 +++++++++++++++++++++++++++++++++++++++\n wpa_supplicant/config_ssid.h    |    6 +++\n wpa_supplicant/wpa_supplicant.c |   23 +++++++---\n 4 files changed, 124 insertions(+), 7 deletions(-)\n\n--- a/src/drivers/driver.h\n+++ b/src/drivers/driver.h\n@@ -19,6 +19,7 @@\n \n #define WPA_SUPPLICANT_DRIVER_VERSION 4\n \n+#include \"ap/sta_info.h\"\n #include \"common/defs.h\"\n #include \"common/ieee802_11_defs.h\"\n #include \"common/wpa_common.h\"\n@@ -857,6 +858,9 @@ struct wpa_driver_associate_params {\n \t * responsible for selecting with which BSS to associate. */\n \tconst u8 *bssid;\n \n+\tunsigned char rates[WLAN_SUPP_RATES_MAX];\n+\tint mcast_rate;\n+\n \t/**\n \t * bssid_hint - BSSID of a proposed AP\n \t *\n--- a/wpa_supplicant/config.c\n+++ b/wpa_supplicant/config.c\n@@ -18,6 +18,7 @@\n #include \"eap_peer/eap.h\"\n #include \"p2p/p2p.h\"\n #include \"fst/fst.h\"\n+#include \"ap/sta_info.h\"\n #include \"config.h\"\n \n \n@@ -2321,6 +2322,97 @@ static char * wpa_config_write_peerkey(c\n #endif /* NO_CONFIG_WRITE */\n \n \n+static int wpa_config_parse_mcast_rate(const struct parse_data *data,\n+\t\t\t\t       struct wpa_ssid *ssid, int line,\n+\t\t\t\t       const char *value)\n+{\n+\tssid->mcast_rate = (int)(strtod(value, NULL) * 10);\n+\n+\treturn 0;\n+}\n+\n+#ifndef NO_CONFIG_WRITE\n+static char * wpa_config_write_mcast_rate(const struct parse_data *data,\n+\t\t\t\t\t  struct wpa_ssid *ssid)\n+{\n+\tchar *value;\n+\tint res;\n+\n+\tif (!ssid->mcast_rate == 0)\n+\t\treturn NULL;\n+\n+\tvalue = os_malloc(6); /* longest: 300.0 */\n+\tif (value == NULL)\n+\t\treturn NULL;\n+\tres = os_snprintf(value, 5, \"%.1f\", (double)ssid->mcast_rate / 10);\n+\tif (res < 0) {\n+\t\tos_free(value);\n+\t\treturn NULL;\n+\t}\n+\treturn value;\n+}\n+#endif /* NO_CONFIG_WRITE */\n+\n+static int wpa_config_parse_rates(const struct parse_data *data,\n+\t\t\t\t  struct wpa_ssid *ssid, int line,\n+\t\t\t\t  const char *value)\n+{\n+\tint i;\n+\tchar *pos, *r, *sptr, *end;\n+\tdouble rate;\n+\n+\tpos = (char *)value;\n+\tr = strtok_r(pos, \",\", &sptr);\n+\ti = 0;\n+\twhile (pos && i < WLAN_SUPP_RATES_MAX) {\n+\t\trate = 0.0;\n+\t\tif (r)\n+\t\t\trate = strtod(r, &end);\n+\t\tssid->rates[i] = rate * 2;\n+\t\tif (*end != '\\0' || rate * 2 != ssid->rates[i])\n+\t\t\treturn 1;\n+\n+\t\ti++;\n+\t\tr = strtok_r(NULL, \",\", &sptr);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+#ifndef NO_CONFIG_WRITE\n+static char * wpa_config_write_rates(const struct parse_data *data,\n+\t\t\t\t     struct wpa_ssid *ssid)\n+{\n+\tchar *value, *pos;\n+\tint res, i;\n+\n+\tif (ssid->rates[0] <= 0)\n+\t\treturn NULL;\n+\n+\tvalue = os_malloc(6 * WLAN_SUPP_RATES_MAX + 1);\n+\tif (value == NULL)\n+\t\treturn NULL;\n+\tpos = value;\n+\tfor (i = 0; i < WLAN_SUPP_RATES_MAX - 1; i++) {\n+\t\tres = os_snprintf(pos, 6, \"%.1f,\", (double)ssid->rates[i] / 2);\n+\t\tif (res < 0) {\n+\t\t\tos_free(value);\n+\t\t\treturn NULL;\n+\t\t}\n+\t\tpos += res;\n+\t}\n+\tres = os_snprintf(pos, 6, \"%.1f\",\n+\t\t\t  (double)ssid->rates[WLAN_SUPP_RATES_MAX - 1] / 2);\n+\tif (res < 0) {\n+\t\tos_free(value);\n+\t\treturn NULL;\n+\t}\n+\n+\tvalue[6 * WLAN_SUPP_RATES_MAX] = '\\0';\n+\treturn value;\n+}\n+#endif /* NO_CONFIG_WRITE */\n+\n /* Helper macros for network block parser */\n \n #ifdef OFFSET\n@@ -2606,6 +2698,8 @@ static const struct parse_data ssid_fiel\n \t{ INT(ap_max_inactivity) },\n \t{ INT(dtim_period) },\n \t{ INT(beacon_int) },\n+\t{ FUNC(rates) },\n+\t{ FUNC(mcast_rate) },\n #ifdef CONFIG_MACSEC\n \t{ INT_RANGE(macsec_policy, 0, 1) },\n \t{ INT_RANGE(macsec_integ_only, 0, 1) },\n--- a/wpa_supplicant/config_ssid.h\n+++ b/wpa_supplicant/config_ssid.h\n@@ -10,8 +10,10 @@\n #define CONFIG_SSID_H\n \n #include \"common/defs.h\"\n+#include \"ap/sta_info.h\"\n #include \"utils/list.h\"\n #include \"eap_peer/eap_config.h\"\n+#include \"drivers/nl80211_copy.h\"\n \n \n #define DEFAULT_EAP_WORKAROUND ((unsigned int) -1)\n@@ -846,6 +848,9 @@ struct wpa_ssid {\n \t */\n \tvoid *parent_cred;\n \n+\tunsigned char rates[WLAN_SUPP_RATES_MAX];\n+\tdouble mcast_rate;\n+\n #ifdef CONFIG_MACSEC\n \t/**\n \t * macsec_policy - Determines the policy for MACsec secure session\n--- a/wpa_supplicant/wpa_supplicant.c\n+++ b/wpa_supplicant/wpa_supplicant.c\n@@ -3865,6 +3865,12 @@ static void wpas_start_assoc_cb(struct w\n \t\t\tparams.beacon_int = ssid->beacon_int;\n \t\telse\n \t\t\tparams.beacon_int = wpa_s->conf->beacon_int;\n+\t\tint i = 0;\n+\t\twhile (i < WLAN_SUPP_RATES_MAX) {\n+\t\t\tparams.rates[i] = ssid->rates[i];\n+\t\t\ti++;\n+\t\t}\n+\t\tparams.mcast_rate = ssid->mcast_rate;\n \t}\n \n \tif (bss && ssid->enable_edmg)\n"
  },
  {
    "path": "package/network/services/hostapd/patches/461-driver_nl80211-use-new-parameters-during-ibss-join.patch",
    "content": "From ffc4445958a3ed4064f2e1bf73fa478a61c5cf7b Mon Sep 17 00:00:00 2001\nFrom: Antonio Quartulli <ordex@autistici.org>\nDate: Sun, 3 Jun 2012 18:42:25 +0200\nSubject: [PATCHv2 602/602] driver_nl80211: use new parameters during ibss join\n\nSigned-hostap: Antonio Quartulli <ordex@autistici.org>\n---\n src/drivers/driver_nl80211.c |   33 ++++++++++++++++++++++++++++++++-\n 1 file changed, 32 insertions(+), 1 deletion(-)\n\n--- a/src/drivers/driver_nl80211.c\n+++ b/src/drivers/driver_nl80211.c\n@@ -5966,7 +5966,7 @@ static int wpa_driver_nl80211_ibss(struc\n \t\t\t\t   struct wpa_driver_associate_params *params)\n {\n \tstruct nl_msg *msg;\n-\tint ret = -1;\n+\tint ret = -1, i;\n \tint count = 0;\n \n \twpa_printf(MSG_DEBUG, \"nl80211: Join IBSS (ifindex=%d)\", drv->ifindex);\n@@ -5993,6 +5993,37 @@ retry:\n \t    nl80211_put_beacon_int(msg, params->beacon_int))\n \t\tgoto fail;\n \n+\tif (params->fixed_freq) {\n+\t\twpa_printf(MSG_DEBUG, \"  * fixed_freq\");\n+\t\tnla_put_flag(msg, NL80211_ATTR_FREQ_FIXED);\n+\t}\n+\n+\tif (params->beacon_int > 0) {\n+\t\twpa_printf(MSG_DEBUG, \"  * beacon_int=%d\",\n+\t\t\t   params->beacon_int);\n+\t\tnla_put_u32(msg, NL80211_ATTR_BEACON_INTERVAL,\n+\t\t\t    params->beacon_int);\n+\t}\n+\n+\tif (params->rates[0] > 0) {\n+\t\twpa_printf(MSG_DEBUG, \"  * basic_rates:\");\n+\t\ti = 0;\n+\t\twhile (i < NL80211_MAX_SUPP_RATES &&\n+\t\t       params->rates[i] > 0) {\n+\t\t\twpa_printf(MSG_DEBUG, \"    %.1f\",\n+\t\t\t\t   (double)params->rates[i] / 2);\n+\t\t\ti++;\n+\t\t}\n+\t\tnla_put(msg, NL80211_ATTR_BSS_BASIC_RATES, i,\n+\t\t\tparams->rates);\n+\t}\n+\n+\tif (params->mcast_rate > 0) {\n+\t\twpa_printf(MSG_DEBUG, \"  * mcast_rate=%.1f\",\n+\t\t\t   (double)params->mcast_rate / 10);\n+\t\tnla_put_u32(msg, NL80211_ATTR_MCAST_RATE, params->mcast_rate);\n+\t}\n+\n \tret = nl80211_set_conn_keys(params, msg);\n \tif (ret)\n \t\tgoto fail;\n"
  },
  {
    "path": "package/network/services/hostapd/patches/463-add-mcast_rate-to-11s.patch",
    "content": "From: Sven Eckelmann <sven.eckelmann@openmesh.com>\nDate: Thu, 11 May 2017 08:21:45 +0200\nSubject: [PATCH] set mcast_rate in mesh mode\n\nThe wpa_supplicant code for IBSS allows to set the mcast rate. It is\nrecommended to increase this value from 1 or 6 Mbit/s to something higher\nwhen using a mesh protocol on top which uses the multicast packet loss as\nindicator for the link quality.\n\nThis setting was unfortunately not applied for mesh mode. But it would be\nbeneficial when wpa_supplicant would behave similar to IBSS mode and set\nthis argument during mesh join like authsae already does. At least it is\nhelpful for companies/projects which are currently switching to 802.11s\n(without mesh_fwding and with mesh_ttl set to 1) as replacement for IBSS\nbecause newer drivers seem to support 802.11s but not IBSS anymore.\n\nSigned-off-by: Sven Eckelmann <sven.eckelmann@openmesh.com>\nTested-by: Simon Wunderlich <simon.wunderlich@openmesh.com>\n\n--- a/src/drivers/driver.h\n+++ b/src/drivers/driver.h\n@@ -1624,6 +1624,7 @@ struct wpa_driver_mesh_join_params {\n #define WPA_DRIVER_MESH_FLAG_AMPE\t0x00000008\n \tunsigned int flags;\n \tbool handle_dfs;\n+\tint mcast_rate;\n };\n \n struct wpa_driver_set_key_params {\n--- a/src/drivers/driver_nl80211.c\n+++ b/src/drivers/driver_nl80211.c\n@@ -10496,6 +10496,18 @@ static int nl80211_put_mesh_id(struct nl\n }\n \n \n+static int nl80211_put_mcast_rate(struct nl_msg *msg, int mcast_rate)\n+{\n+\tif (mcast_rate > 0) {\n+\t\twpa_printf(MSG_DEBUG, \"  * mcast_rate=%.1f\",\n+\t\t\t   (double)mcast_rate / 10);\n+\t\treturn nla_put_u32(msg, NL80211_ATTR_MCAST_RATE, mcast_rate);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+\n static int nl80211_put_mesh_config(struct nl_msg *msg,\n \t\t\t\t   struct wpa_driver_mesh_bss_params *params)\n {\n@@ -10557,6 +10569,7 @@ static int nl80211_join_mesh(struct i802\n \t    nl80211_put_basic_rates(msg, params->basic_rates) ||\n \t    nl80211_put_mesh_id(msg, params->meshid, params->meshid_len) ||\n \t    nl80211_put_beacon_int(msg, params->beacon_int) ||\n+\t    nl80211_put_mcast_rate(msg, params->mcast_rate) ||\n \t    nl80211_put_dtim_period(msg, params->dtim_period))\n \t\tgoto fail;\n \n--- a/wpa_supplicant/mesh.c\n+++ b/wpa_supplicant/mesh.c\n@@ -631,6 +631,7 @@ int wpa_supplicant_join_mesh(struct wpa_\n \n \tparams->meshid = ssid->ssid;\n \tparams->meshid_len = ssid->ssid_len;\n+\tparams->mcast_rate = ssid->mcast_rate;\n \tibss_mesh_setup_freq(wpa_s, ssid, &params->freq);\n \twpa_s->mesh_ht_enabled = !!params->freq.ht_enabled;\n \twpa_s->mesh_vht_enabled = !!params->freq.vht_enabled;\n"
  },
  {
    "path": "package/network/services/hostapd/patches/464-fix-mesh-obss-check.patch",
    "content": "--- a/wpa_supplicant/wpa_supplicant.c\n+++ b/wpa_supplicant/wpa_supplicant.c\n@@ -2512,11 +2512,13 @@ void ibss_mesh_setup_freq(struct wpa_sup\n \tfor (j = 0; j < wpa_s->last_scan_res_used; j++) {\n \t\tstruct wpa_bss *bss = wpa_s->last_scan_res[j];\n \n-\t\tif (ssid->mode != WPAS_MODE_IBSS)\n+\t\t/* Don't adjust control freq in case of fixed_freq */\n+\t\tif (ssid->fixed_freq) {\n+\t\t\tobss_scan = 0;\n \t\t\tbreak;\n+\t\t}\n \n-\t\t/* Don't adjust control freq in case of fixed_freq */\n-\t\tif (ssid->fixed_freq)\n+\t\tif (ssid->mode != WPAS_MODE_IBSS)\n \t\t\tbreak;\n \n \t\tif (!bss_is_ibss(bss))\n"
  },
  {
    "path": "package/network/services/hostapd/patches/470-survey_data_fallback.patch",
    "content": "--- a/src/ap/acs.c\n+++ b/src/ap/acs.c\n@@ -420,20 +420,19 @@ static int acs_usable_bw160_chan(const s\n static int acs_survey_is_sufficient(struct freq_survey *survey)\n {\n \tif (!(survey->filled & SURVEY_HAS_NF)) {\n+\t\tsurvey->nf = -95;\n \t\twpa_printf(MSG_INFO, \"ACS: Survey is missing noise floor\");\n-\t\treturn 0;\n \t}\n \n \tif (!(survey->filled & SURVEY_HAS_CHAN_TIME)) {\n+\t\tsurvey->channel_time = 0;\n \t\twpa_printf(MSG_INFO, \"ACS: Survey is missing channel time\");\n-\t\treturn 0;\n \t}\n \n \tif (!(survey->filled & SURVEY_HAS_CHAN_TIME_BUSY) &&\n \t    !(survey->filled & SURVEY_HAS_CHAN_TIME_RX)) {\n \t\twpa_printf(MSG_INFO,\n \t\t\t   \"ACS: Survey is missing RX and busy time (at least one is required)\");\n-\t\treturn 0;\n \t}\n \n \treturn 1;\n"
  },
  {
    "path": "package/network/services/hostapd/patches/500-lto-jobserver-support.patch",
    "content": "--- a/hostapd/Makefile\n+++ b/hostapd/Makefile\n@@ -1297,7 +1297,7 @@ hostapd_multi.a: $(BCHECK) $(OBJS)\n \t@$(AR) cr $@ hostapd_multi.o $(OBJS)\n \n hostapd: $(OBJS)\n-\t$(Q)$(CC) $(LDFLAGS) -o hostapd $(OBJS) $(LIBS)\n+\t+$(Q)$(CC) $(LDFLAGS) -o hostapd $(OBJS) $(LIBS)\n \t@$(E) \"  LD \" $@\n \n ifdef CONFIG_WPA_TRACE\n@@ -1308,7 +1308,7 @@ _OBJS_VAR := OBJS_c\n include ../src/objs.mk\n \n hostapd_cli: $(OBJS_c)\n-\t$(Q)$(CC) $(LDFLAGS) -o hostapd_cli $(OBJS_c) $(LIBS_c)\n+\t+$(Q)$(CC) $(LDFLAGS) -o hostapd_cli $(OBJS_c) $(LIBS_c)\n \t@$(E) \"  LD \" $@\n \n NOBJS = nt_password_hash.o ../src/crypto/ms_funcs.o $(SHA1OBJS)\n--- a/wpa_supplicant/Makefile\n+++ b/wpa_supplicant/Makefile\n@@ -1920,31 +1920,31 @@ wpa_supplicant_multi.a: .config $(BCHECK\n \t@$(AR) cr $@ wpa_supplicant_multi.o $(OBJS)\n \n wpa_supplicant: $(BCHECK) $(OBJS) $(EXTRA_progs)\n-\t$(Q)$(LDO) $(LDFLAGS) -o wpa_supplicant $(OBJS) $(LIBS) $(EXTRALIBS)\n+\t+$(Q)$(LDO) $(LDFLAGS) -o wpa_supplicant $(OBJS) $(LIBS) $(EXTRALIBS)\n \t@$(E) \"  LD \" $@\n \n _OBJS_VAR := OBJS_t\n include ../src/objs.mk\n eapol_test: $(OBJS_t)\n-\t$(Q)$(LDO) $(LDFLAGS) -o eapol_test $(OBJS_t) $(LIBS)\n+\t+$(Q)$(LDO) $(LDFLAGS) -o eapol_test $(OBJS_t) $(LIBS)\n \t@$(E) \"  LD \" $@\n \n _OBJS_VAR := OBJS_t2\n include ../src/objs.mk\n preauth_test: $(OBJS_t2)\n-\t$(Q)$(LDO) $(LDFLAGS) -o preauth_test $(OBJS_t2) $(LIBS)\n+\t+$(Q)$(LDO) $(LDFLAGS) -o preauth_test $(OBJS_t2) $(LIBS)\n \t@$(E) \"  LD \" $@\n \n _OBJS_VAR := OBJS_p\n include ../src/objs.mk\n wpa_passphrase: $(OBJS_p)\n-\t$(Q)$(LDO) $(LDFLAGS) -o wpa_passphrase $(OBJS_p) $(LIBS_p) $(LIBS)\n+\t+$(Q)$(LDO) $(LDFLAGS) -o wpa_passphrase $(OBJS_p) $(LIBS_p) $(LIBS)\n \t@$(E) \"  LD \" $@\n \n _OBJS_VAR := OBJS_c\n include ../src/objs.mk\n wpa_cli: $(OBJS_c)\n-\t$(Q)$(LDO) $(LDFLAGS) -o wpa_cli $(OBJS_c) $(LIBS_c)\n+\t+$(Q)$(LDO) $(LDFLAGS) -o wpa_cli $(OBJS_c) $(LIBS_c)\n \t@$(E) \"  LD \" $@\n \n LIBCTRL += ../src/common/wpa_ctrl.o\n"
  },
  {
    "path": "package/network/services/hostapd/patches/590-rrm-wnm-statistics.patch",
    "content": "--- a/src/ap/hostapd.h\n+++ b/src/ap/hostapd.h\n@@ -150,6 +150,21 @@ struct hostapd_sae_commit_queue {\n };\n \n /**\n+ * struct hostapd_openwrt_stats - OpenWrt custom STA/AP statistics\n+ */\n+struct hostapd_openwrt_stats {\n+\tstruct {\n+\t\tu64 neighbor_report_tx;\n+\t} rrm;\n+\n+\tstruct {\n+\t\tu64 bss_transition_query_rx;\n+\t\tu64 bss_transition_request_tx;\n+\t\tu64 bss_transition_response_rx;\n+\t} wnm;\n+};\n+\n+/**\n  * struct hostapd_data - hostapd per-BSS data structure\n  */\n struct hostapd_data {\n@@ -163,6 +178,9 @@ struct hostapd_data {\n \n \tu8 own_addr[ETH_ALEN];\n \n+\t/* OpenWrt specific statistics */\n+\tstruct hostapd_openwrt_stats openwrt_stats;\n+\n \tint num_sta; /* number of entries in sta_list */\n \tstruct sta_info *sta_list; /* STA info list head */\n #define STA_HASH_SIZE 256\n--- a/src/ap/wnm_ap.c\n+++ b/src/ap/wnm_ap.c\n@@ -386,6 +386,7 @@ static int ieee802_11_send_bss_trans_mgm\n \tmgmt->u.action.u.bss_tm_req.validity_interval = 1;\n \tpos = mgmt->u.action.u.bss_tm_req.variable;\n \n+\thapd->openwrt_stats.wnm.bss_transition_request_tx++;\n \twpa_printf(MSG_DEBUG, \"WNM: Send BSS Transition Management Request to \"\n \t\t   MACSTR \" dialog_token=%u req_mode=0x%x disassoc_timer=%u \"\n \t\t   \"validity_interval=%u\",\n@@ -646,10 +647,12 @@ int ieee802_11_rx_wnm_action_ap(struct h\n \n \tswitch (action) {\n \tcase WNM_BSS_TRANS_MGMT_QUERY:\n+\t\thapd->openwrt_stats.wnm.bss_transition_query_rx++;\n \t\tieee802_11_rx_bss_trans_mgmt_query(hapd, mgmt->sa, payload,\n \t\t\t\t\t\t   plen);\n \t\treturn 0;\n \tcase WNM_BSS_TRANS_MGMT_RESP:\n+\t\thapd->openwrt_stats.wnm.bss_transition_response_rx++;\n \t\tieee802_11_rx_bss_trans_mgmt_resp(hapd, mgmt->sa, payload,\n \t\t\t\t\t\t  plen);\n \t\treturn 0;\n@@ -696,6 +699,7 @@ int wnm_send_disassoc_imminent(struct ho\n \n \tpos = mgmt->u.action.u.bss_tm_req.variable;\n \n+\thapd->openwrt_stats.wnm.bss_transition_request_tx++;\n \twpa_printf(MSG_DEBUG, \"WNM: Send BSS Transition Management Request frame to indicate imminent disassociation (disassoc_timer=%d) to \"\n \t\t   MACSTR, disassoc_timer, MAC2STR(sta->addr));\n \tif (hostapd_drv_send_mlme(hapd, buf, pos - buf, 0, NULL, 0, 0) < 0) {\n@@ -777,6 +781,7 @@ int wnm_send_ess_disassoc_imminent(struc\n \t\treturn -1;\n \t}\n \n+\thapd->openwrt_stats.wnm.bss_transition_request_tx++;\n \tif (disassoc_timer) {\n \t\t/* send disassociation frame after time-out */\n \t\tset_disassoc_timer(hapd, sta, disassoc_timer);\n@@ -857,6 +862,7 @@ int wnm_send_bss_tm_req(struct hostapd_d\n \t}\n \tos_free(buf);\n \n+\thapd->openwrt_stats.wnm.bss_transition_request_tx++;\n \tif (disassoc_timer) {\n \t\t/* send disassociation frame after time-out */\n \t\tset_disassoc_timer(hapd, sta, disassoc_timer);\n--- a/src/ap/rrm.c\n+++ b/src/ap/rrm.c\n@@ -269,6 +269,8 @@ static void hostapd_send_nei_report_resp\n \t\t}\n \t}\n \n+\thapd->openwrt_stats.rrm.neighbor_report_tx++;\n+\n \thostapd_drv_send_action(hapd, hapd->iface->freq, 0, addr,\n \t\t\t\twpabuf_head(buf), wpabuf_len(buf));\n \twpabuf_free(buf);\n"
  },
  {
    "path": "package/network/services/hostapd/patches/599-wpa_supplicant-fix-warnings.patch",
    "content": "--- a/wpa_supplicant/wps_supplicant.h\n+++ b/wpa_supplicant/wps_supplicant.h\n@@ -9,6 +9,7 @@\n #ifndef WPS_SUPPLICANT_H\n #define WPS_SUPPLICANT_H\n \n+struct wpa_bss;\n struct wpa_scan_results;\n \n #ifdef CONFIG_WPS\n@@ -16,8 +17,6 @@ struct wpa_scan_results;\n #include \"wps/wps.h\"\n #include \"wps/wps_defs.h\"\n \n-struct wpa_bss;\n-\n struct wps_new_ap_settings {\n \tconst char *ssid_hex;\n \tconst char *auth;\n"
  },
  {
    "path": "package/network/services/hostapd/patches/600-ubus_support.patch",
    "content": "--- a/hostapd/Makefile\n+++ b/hostapd/Makefile\n@@ -166,6 +166,11 @@ OBJS += ../src/common/hw_features_common\n \n OBJS += ../src/eapol_auth/eapol_auth_sm.o\n \n+ifdef CONFIG_UBUS\n+CFLAGS += -DUBUS_SUPPORT\n+OBJS += ../src/ap/ubus.o\n+LIBS += -lubox -lubus\n+endif\n \n ifdef CONFIG_CODE_COVERAGE\n CFLAGS += -O0 -fprofile-arcs -ftest-coverage\n--- a/src/ap/hostapd.h\n+++ b/src/ap/hostapd.h\n@@ -17,6 +17,7 @@\n #include \"utils/list.h\"\n #include \"ap_config.h\"\n #include \"drivers/driver.h\"\n+#include \"ubus.h\"\n \n #define OCE_STA_CFON_ENABLED(hapd) \\\n \t((hapd->conf->oce & OCE_STA_CFON) && \\\n@@ -80,7 +81,7 @@ struct hapd_interfaces {\n #ifdef CONFIG_CTRL_IFACE_UDP\n        unsigned char ctrl_iface_cookie[CTRL_IFACE_COOKIE_LEN];\n #endif /* CONFIG_CTRL_IFACE_UDP */\n-\n+\tstruct ubus_object ubus;\n };\n \n enum hostapd_chan_status {\n@@ -171,6 +172,7 @@ struct hostapd_data {\n \tstruct hostapd_iface *iface;\n \tstruct hostapd_config *iconf;\n \tstruct hostapd_bss_config *conf;\n+\tstruct hostapd_ubus_bss ubus;\n \tint interface_added; /* virtual interface added for this BSS */\n \tunsigned int started:1;\n \tunsigned int disabled:1;\n@@ -630,6 +632,7 @@ hostapd_alloc_bss_data(struct hostapd_if\n \t\t       struct hostapd_bss_config *bss);\n int hostapd_setup_interface(struct hostapd_iface *iface);\n int hostapd_setup_interface_complete(struct hostapd_iface *iface, int err);\n+void hostapd_set_own_neighbor_report(struct hostapd_data *hapd);\n void hostapd_interface_deinit(struct hostapd_iface *iface);\n void hostapd_interface_free(struct hostapd_iface *iface);\n struct hostapd_iface * hostapd_alloc_iface(void);\n--- a/src/ap/hostapd.c\n+++ b/src/ap/hostapd.c\n@@ -396,6 +396,7 @@ void hostapd_free_hapd_data(struct hosta\n \thapd->beacon_set_done = 0;\n \n \twpa_printf(MSG_DEBUG, \"%s(%s)\", __func__, hapd->conf->iface);\n+\thostapd_ubus_free_bss(hapd);\n \taccounting_deinit(hapd);\n \thostapd_deinit_wpa(hapd);\n \tvlan_deinit(hapd);\n@@ -1422,6 +1423,8 @@ static int hostapd_setup_bss(struct host\n \tif (hapd->driver && hapd->driver->set_operstate)\n \t\thapd->driver->set_operstate(hapd->drv_priv, 1);\n \n+\thostapd_ubus_add_bss(hapd);\n+\n \treturn 0;\n }\n \n@@ -2028,6 +2031,7 @@ static int hostapd_setup_interface_compl\n \tif (err)\n \t\tgoto fail;\n \n+\thostapd_ubus_add_iface(iface);\n \twpa_printf(MSG_DEBUG, \"Completing interface initialization\");\n \tif (iface->freq) {\n #ifdef NEED_AP_MLME\n@@ -2225,6 +2229,7 @@ dfs_offload:\n \n fail:\n \twpa_printf(MSG_ERROR, \"Interface initialization failed\");\n+\thostapd_ubus_free_iface(iface);\n \thostapd_set_state(iface, HAPD_IFACE_DISABLED);\n \twpa_msg(hapd->msg_ctx, MSG_INFO, AP_EVENT_DISABLED);\n #ifdef CONFIG_FST\n@@ -2700,6 +2705,7 @@ void hostapd_interface_deinit_free(struc\n \t\t   (unsigned int) iface->conf->num_bss);\n \tdriver = iface->bss[0]->driver;\n \tdrv_priv = iface->bss[0]->drv_priv;\n+\thostapd_ubus_free_iface(iface);\n \thostapd_interface_deinit(iface);\n \twpa_printf(MSG_DEBUG, \"%s: driver=%p drv_priv=%p -> hapd_deinit\",\n \t\t   __func__, driver, drv_priv);\n--- a/src/ap/ieee802_11.c\n+++ b/src/ap/ieee802_11.c\n@@ -3553,13 +3553,18 @@ static void handle_auth(struct hostapd_d\n \tu16 auth_alg, auth_transaction, status_code;\n \tu16 resp = WLAN_STATUS_SUCCESS;\n \tstruct sta_info *sta = NULL;\n-\tint res, reply_res;\n+\tint res, reply_res, ubus_resp;\n \tu16 fc;\n \tconst u8 *challenge = NULL;\n \tu8 resp_ies[2 + WLAN_AUTH_CHALLENGE_LEN];\n \tsize_t resp_ies_len = 0;\n \tu16 seq_ctrl;\n \tstruct radius_sta rad_info;\n+\tstruct hostapd_ubus_request req = {\n+\t\t.type = HOSTAPD_UBUS_AUTH_REQ,\n+\t\t.mgmt_frame = mgmt,\n+\t\t.ssi_signal = rssi,\n+\t};\n \n \tif (len < IEEE80211_HDRLEN + sizeof(mgmt->u.auth)) {\n \t\twpa_printf(MSG_INFO, \"handle_auth - too short payload (len=%lu)\",\n@@ -3727,6 +3732,13 @@ static void handle_auth(struct hostapd_d\n \t\tresp = WLAN_STATUS_UNSPECIFIED_FAILURE;\n \t\tgoto fail;\n \t}\n+\tubus_resp = hostapd_ubus_handle_event(hapd, &req);\n+\tif (ubus_resp) {\n+\t\twpa_printf(MSG_DEBUG, \"Station \" MACSTR \" rejected by ubus handler.\\n\",\n+\t\t\tMAC2STR(mgmt->sa));\n+\t\tresp = ubus_resp > 0 ? (u16) ubus_resp : WLAN_STATUS_UNSPECIFIED_FAILURE;\n+\t\tgoto fail;\n+\t}\n \tif (res == HOSTAPD_ACL_PENDING)\n \t\treturn;\n \n@@ -5447,7 +5459,7 @@ static void handle_assoc(struct hostapd_\n \tint resp = WLAN_STATUS_SUCCESS;\n \tu16 reply_res = WLAN_STATUS_UNSPECIFIED_FAILURE;\n \tconst u8 *pos;\n-\tint left, i;\n+\tint left, i, ubus_resp;\n \tstruct sta_info *sta;\n \tu8 *tmp = NULL;\n #ifdef CONFIG_FILS\n@@ -5660,6 +5672,11 @@ static void handle_assoc(struct hostapd_\n \t\tleft = res;\n \t}\n #endif /* CONFIG_FILS */\n+\tstruct hostapd_ubus_request req = {\n+\t\t.type = HOSTAPD_UBUS_ASSOC_REQ,\n+\t\t.mgmt_frame = mgmt,\n+\t\t.ssi_signal = rssi,\n+\t};\n \n \t/* followed by SSID and Supported rates; and HT capabilities if 802.11n\n \t * is used */\n@@ -5758,6 +5775,13 @@ static void handle_assoc(struct hostapd_\n \t}\n #endif /* CONFIG_FILS */\n \n+\tubus_resp = hostapd_ubus_handle_event(hapd, &req);\n+\tif (ubus_resp) {\n+\t\twpa_printf(MSG_DEBUG, \"Station \" MACSTR \" assoc rejected by ubus handler.\\n\",\n+\t\t       MAC2STR(mgmt->sa));\n+\t\tresp = ubus_resp > 0 ? (u16) ubus_resp : WLAN_STATUS_UNSPECIFIED_FAILURE;\n+\t\tgoto fail;\n+\t}\n  fail:\n \n \t/*\n@@ -5851,6 +5875,7 @@ static void handle_disassoc(struct hosta\n \twpa_printf(MSG_DEBUG, \"disassocation: STA=\" MACSTR \" reason_code=%d\",\n \t\t   MAC2STR(mgmt->sa),\n \t\t   le_to_host16(mgmt->u.disassoc.reason_code));\n+\thostapd_ubus_notify(hapd, \"disassoc\", mgmt->sa);\n \n \tsta = ap_get_sta(hapd, mgmt->sa);\n \tif (sta == NULL) {\n@@ -5920,6 +5945,8 @@ static void handle_deauth(struct hostapd\n \t/* Clear the PTKSA cache entries for PASN */\n \tptksa_cache_flush(hapd->ptksa, mgmt->sa, WPA_CIPHER_NONE);\n \n+\thostapd_ubus_notify(hapd, \"deauth\", mgmt->sa);\n+\n \tsta = ap_get_sta(hapd, mgmt->sa);\n \tif (sta == NULL) {\n \t\twpa_msg(hapd->msg_ctx, MSG_DEBUG, \"Station \" MACSTR \" trying \"\n--- a/src/ap/beacon.c\n+++ b/src/ap/beacon.c\n@@ -852,6 +852,12 @@ void handle_probe_req(struct hostapd_dat\n \tu16 csa_offs[2];\n \tsize_t csa_offs_len;\n \tstruct radius_sta rad_info;\n+\tstruct hostapd_ubus_request req = {\n+\t\t.type = HOSTAPD_UBUS_PROBE_REQ,\n+\t\t.mgmt_frame = mgmt,\n+\t\t.ssi_signal = ssi_signal,\n+\t\t.elems = &elems,\n+\t};\n \n \tif (hapd->iconf->rssi_ignore_probe_request && ssi_signal &&\n \t    ssi_signal < hapd->iconf->rssi_ignore_probe_request)\n@@ -1038,6 +1044,12 @@ void handle_probe_req(struct hostapd_dat\n \t}\n #endif /* CONFIG_P2P */\n \n+\tif (hostapd_ubus_handle_event(hapd, &req)) {\n+\t\twpa_printf(MSG_DEBUG, \"Probe request for \" MACSTR \" rejected by ubus handler.\\n\",\n+\t\t       MAC2STR(mgmt->sa));\n+\t\treturn;\n+\t}\n+\n \t/* TODO: verify that supp_rates contains at least one matching rate\n \t * with AP configuration */\n \n--- a/src/ap/drv_callbacks.c\n+++ b/src/ap/drv_callbacks.c\n@@ -145,6 +145,10 @@ int hostapd_notif_assoc(struct hostapd_d\n \tu16 reason = WLAN_REASON_UNSPECIFIED;\n \tint status = WLAN_STATUS_SUCCESS;\n \tconst u8 *p2p_dev_addr = NULL;\n+\tstruct hostapd_ubus_request req = {\n+\t\t.type = HOSTAPD_UBUS_ASSOC_REQ,\n+\t\t.addr = addr,\n+\t};\n \n \tif (addr == NULL) {\n \t\t/*\n@@ -237,6 +241,12 @@ int hostapd_notif_assoc(struct hostapd_d\n \t\tgoto fail;\n \t}\n \n+\tif (hostapd_ubus_handle_event(hapd, &req)) {\n+\t\twpa_printf(MSG_DEBUG, \"Station \" MACSTR \" assoc rejected by ubus handler.\\n\",\n+\t\t\t   MAC2STR(req.addr));\n+\t\tgoto fail;\n+\t}\n+\n #ifdef CONFIG_P2P\n \tif (elems.p2p) {\n \t\twpabuf_free(sta->p2p_ie);\n--- a/src/ap/sta_info.c\n+++ b/src/ap/sta_info.c\n@@ -458,6 +458,7 @@ void ap_handle_timer(void *eloop_ctx, vo\n \t\thostapd_logger(hapd, sta->addr, HOSTAPD_MODULE_IEEE80211,\n \t\t\t       HOSTAPD_LEVEL_INFO, \"deauthenticated due to \"\n \t\t\t       \"local deauth request\");\n+\t\thostapd_ubus_notify(hapd, \"local-deauth\", sta->addr);\n \t\tap_free_sta(hapd, sta);\n \t\treturn;\n \t}\n@@ -613,6 +614,7 @@ skip_poll:\n \t\tmlme_deauthenticate_indication(\n \t\t\thapd, sta,\n \t\t\tWLAN_REASON_PREV_AUTH_NOT_VALID);\n+\t\thostapd_ubus_notify(hapd, \"inactive-deauth\", sta->addr);\n \t\tap_free_sta(hapd, sta);\n \t\tbreak;\n \t}\n@@ -1329,6 +1331,7 @@ void ap_sta_set_authorized(struct hostap\n \t\t\t\t\t  buf, ip_addr, keyid_buf);\n \t} else {\n \t\twpa_msg(hapd->msg_ctx, MSG_INFO, AP_STA_DISCONNECTED \"%s\", buf);\n+\t\thostapd_ubus_notify(hapd, \"disassoc\", sta->addr);\n \n \t\tif (hapd->msg_ctx_parent &&\n \t\t    hapd->msg_ctx_parent != hapd->msg_ctx)\n--- a/src/ap/wpa_auth_glue.c\n+++ b/src/ap/wpa_auth_glue.c\n@@ -265,6 +265,7 @@ static void hostapd_wpa_auth_psk_failure\n \tstruct hostapd_data *hapd = ctx;\n \twpa_msg(hapd->msg_ctx, MSG_INFO, AP_STA_POSSIBLE_PSK_MISMATCH MACSTR,\n \t\tMAC2STR(addr));\n+\thostapd_ubus_notify(hapd, \"key-mismatch\", addr);\n }\n \n \n--- a/wpa_supplicant/Makefile\n+++ b/wpa_supplicant/Makefile\n@@ -176,6 +176,12 @@ ifdef CONFIG_EAPOL_TEST\n CFLAGS += -Werror -DEAPOL_TEST\n endif\n \n+ifdef CONFIG_UBUS\n+CFLAGS += -DUBUS_SUPPORT\n+OBJS += ubus.o\n+LIBS += -lubox -lubus\n+endif\n+\n ifdef CONFIG_CODE_COVERAGE\n CFLAGS += -O0 -fprofile-arcs -ftest-coverage\n LIBS += -lgcov\n@@ -962,6 +968,9 @@ ifdef CONFIG_CTRL_IFACE_MIB\n CFLAGS += -DCONFIG_CTRL_IFACE_MIB\n endif\n OBJS += ../src/ap/ctrl_iface_ap.o\n+ifdef CONFIG_UBUS\n+OBJS += ../src/ap/ubus.o\n+endif\n endif\n \n CFLAGS += -DEAP_SERVER -DEAP_SERVER_IDENTITY\n--- a/wpa_supplicant/wpa_supplicant.c\n+++ b/wpa_supplicant/wpa_supplicant.c\n@@ -7241,6 +7241,8 @@ struct wpa_supplicant * wpa_supplicant_a\n \t}\n #endif /* CONFIG_P2P */\n \n+\twpas_ubus_add_bss(wpa_s);\n+\n \treturn wpa_s;\n }\n \n@@ -7267,6 +7269,8 @@ int wpa_supplicant_remove_iface(struct w\n \tstruct wpa_supplicant *parent = wpa_s->parent;\n #endif /* CONFIG_MESH */\n \n+\twpas_ubus_free_bss(wpa_s);\n+\n \t/* Remove interface from the global list of interfaces */\n \tprev = global->ifaces;\n \tif (prev == wpa_s) {\n@@ -7570,8 +7574,12 @@ int wpa_supplicant_run(struct wpa_global\n \teloop_register_signal_terminate(wpa_supplicant_terminate, global);\n \teloop_register_signal_reconfig(wpa_supplicant_reconfig, global);\n \n+\twpas_ubus_add(global);\n+\n \teloop_run();\n \n+\twpas_ubus_free(global);\n+\n \treturn 0;\n }\n \n--- a/wpa_supplicant/wpa_supplicant_i.h\n+++ b/wpa_supplicant/wpa_supplicant_i.h\n@@ -19,6 +19,7 @@\n #include \"wps/wps_defs.h\"\n #include \"config_ssid.h\"\n #include \"wmm_ac.h\"\n+#include \"ubus.h\"\n \n extern const char *const wpa_supplicant_version;\n extern const char *const wpa_supplicant_license;\n@@ -322,6 +323,8 @@ struct wpa_global {\n #endif /* CONFIG_WIFI_DISPLAY */\n \n \tstruct psk_list_entry *add_psk; /* From group formation */\n+\n+\tstruct ubus_object ubus_global;\n };\n \n \n@@ -708,6 +711,7 @@ struct wpa_supplicant {\n \tunsigned char own_addr[ETH_ALEN];\n \tunsigned char perm_addr[ETH_ALEN];\n \tchar ifname[100];\n+\tstruct wpas_ubus_bss ubus;\n #ifdef CONFIG_MATCH_IFACE\n \tint matched;\n #endif /* CONFIG_MATCH_IFACE */\n--- a/wpa_supplicant/wps_supplicant.c\n+++ b/wpa_supplicant/wps_supplicant.c\n@@ -33,6 +33,7 @@\n #include \"p2p/p2p.h\"\n #include \"p2p_supplicant.h\"\n #include \"wps_supplicant.h\"\n+#include \"ubus.h\"\n \n \n #ifndef WPS_PIN_SCAN_IGNORE_SEL_REG\n@@ -393,6 +394,8 @@ static int wpa_supplicant_wps_cred(void\n \twpa_hexdump_key(MSG_DEBUG, \"WPS: Received Credential attribute\",\n \t\t\tcred->cred_attr, cred->cred_attr_len);\n \n+\twpas_ubus_notify(wpa_s, cred);\n+\n \tif (wpa_s->conf->wps_cred_processing == 1)\n \t\treturn 0;\n \n--- a/hostapd/main.c\n+++ b/hostapd/main.c\n@@ -895,6 +895,7 @@ int main(int argc, char *argv[])\n \t}\n \n \thostapd_global_ctrl_iface_init(&interfaces);\n+\thostapd_ubus_add(&interfaces);\n \n \tif (hostapd_global_run(&interfaces, daemonize, pid_file)) {\n \t\twpa_printf(MSG_ERROR, \"Failed to start eloop\");\n@@ -904,6 +905,7 @@ int main(int argc, char *argv[])\n \tret = 0;\n \n  out:\n+\thostapd_ubus_free(&interfaces);\n \thostapd_global_ctrl_iface_deinit(&interfaces);\n \t/* Deinitialize all interfaces */\n \tfor (i = 0; i < interfaces.count; i++) {\n--- a/wpa_supplicant/main.c\n+++ b/wpa_supplicant/main.c\n@@ -203,7 +203,7 @@ int main(int argc, char *argv[])\n \n \tfor (;;) {\n \t\tc = getopt(argc, argv,\n-\t\t\t   \"b:Bc:C:D:de:f:g:G:hH:i:I:KLMm:No:O:p:P:qsTtuv::W\");\n+\t\t\t   \"b:Bc:C:D:de:f:g:G:hH:i:I:KLMm:nNo:O:p:P:qsTtuv::W\");\n \t\tif (c < 0)\n \t\t\tbreak;\n \t\tswitch (c) {\n@@ -271,6 +271,9 @@ int main(int argc, char *argv[])\n \t\t\tparams.conf_p2p_dev = optarg;\n \t\t\tbreak;\n #endif /* CONFIG_P2P */\n+\t\tcase 'n':\n+\t\t\tiface_count = 0;\n+\t\t\tbreak;\n \t\tcase 'o':\n \t\t\tparams.override_driver = optarg;\n \t\t\tbreak;\n--- a/src/ap/rrm.c\n+++ b/src/ap/rrm.c\n@@ -89,6 +89,9 @@ static void hostapd_handle_beacon_report\n \t\treturn;\n \twpa_msg(hapd->msg_ctx, MSG_INFO, BEACON_RESP_RX MACSTR \" %u %02x %s\",\n \t\tMAC2STR(addr), token, rep_mode, report);\n+\tif (len < sizeof(struct rrm_measurement_beacon_report))\n+\t\treturn;\n+\thostapd_ubus_notify_beacon_report(hapd, addr, token, rep_mode, (struct rrm_measurement_beacon_report*) pos, len);\n }\n \n \n@@ -352,6 +355,9 @@ void hostapd_handle_radio_measurement(st\n \t\t   mgmt->u.action.u.rrm.action, MAC2STR(mgmt->sa));\n \n \tswitch (mgmt->u.action.u.rrm.action) {\n+\tcase WLAN_RRM_LINK_MEASUREMENT_REPORT:\n+\t\thostapd_ubus_handle_link_measurement(hapd, buf, len);\n+\t\tbreak;\n \tcase WLAN_RRM_RADIO_MEASUREMENT_REPORT:\n \t\thostapd_handle_radio_msmt_report(hapd, buf, len);\n \t\tbreak;\n--- a/src/ap/vlan_init.c\n+++ b/src/ap/vlan_init.c\n@@ -22,6 +22,7 @@\n static int vlan_if_add(struct hostapd_data *hapd, struct hostapd_vlan *vlan,\n \t\t       int existsok)\n {\n+\tbool vlan_exists = iface_exists(vlan->ifname);\n \tint ret;\n #ifdef CONFIG_WEP\n \tint i;\n@@ -36,7 +37,7 @@ static int vlan_if_add(struct hostapd_da\n \t}\n #endif /* CONFIG_WEP */\n \n-\tif (!iface_exists(vlan->ifname))\n+\tif (!vlan_exists)\n \t\tret = hostapd_vlan_if_add(hapd, vlan->ifname);\n \telse if (!existsok)\n \t\treturn -1;\n@@ -51,6 +52,9 @@ static int vlan_if_add(struct hostapd_da\n \tif (hapd->wpa_auth)\n \t\tret = wpa_auth_ensure_group(hapd->wpa_auth, vlan->vlan_id);\n \n+\tif (!ret && !vlan_exists)\n+\t\thostapd_ubus_add_vlan(hapd, vlan);\n+\n \tif (ret == 0)\n \t\treturn ret;\n \n@@ -77,6 +81,8 @@ int vlan_if_remove(struct hostapd_data *\n \t\t\t   \"WPA deinitialization for VLAN %d failed (%d)\",\n \t\t\t   vlan->vlan_id, ret);\n \n+\thostapd_ubus_remove_vlan(hapd, vlan);\n+\n \treturn hostapd_vlan_if_remove(hapd, vlan->ifname);\n }\n \n--- a/src/ap/dfs.c\n+++ b/src/ap/dfs.c\n@@ -1196,6 +1196,8 @@ int hostapd_dfs_radar_detected(struct ho\n \t\t\"freq=%d ht_enabled=%d chan_offset=%d chan_width=%d cf1=%d cf2=%d\",\n \t\tfreq, ht_enabled, chan_offset, chan_width, cf1, cf2);\n \n+\thostapd_ubus_notify_radar_detected(iface, freq, chan_width, cf1, cf2);\n+\n \t/* Proceed only if DFS is not offloaded to the driver */\n \tif (iface->drv_flags & WPA_DRIVER_FLAGS_DFS_OFFLOAD)\n \t\treturn 0;\n--- a/src/ap/airtime_policy.c\n+++ b/src/ap/airtime_policy.c\n@@ -112,8 +112,14 @@ static void set_sta_weights(struct hosta\n {\n \tstruct sta_info *sta;\n \n-\tfor (sta = hapd->sta_list; sta; sta = sta->next)\n-\t\tsta_set_airtime_weight(hapd, sta, weight);\n+\tfor (sta = hapd->sta_list; sta; sta = sta->next) {\n+\t\tunsigned int sta_weight = weight;\n+\n+\t\tif (sta->dyn_airtime_weight)\n+\t\t\tsta_weight = (weight * sta->dyn_airtime_weight) / 256;\n+\n+\t\tsta_set_airtime_weight(hapd, sta, sta_weight);\n+\t}\n }\n \n \n@@ -244,7 +250,10 @@ int airtime_policy_new_sta(struct hostap\n \tunsigned int weight;\n \n \tif (hapd->iconf->airtime_mode == AIRTIME_MODE_STATIC) {\n-\t\tweight = get_weight_for_sta(hapd, sta->addr);\n+\t\tif (sta->dyn_airtime_weight)\n+\t\t\tweight = sta->dyn_airtime_weight;\n+\t\telse\n+\t\t\tweight = get_weight_for_sta(hapd, sta->addr);\n \t\tif (weight)\n \t\t\treturn sta_set_airtime_weight(hapd, sta, weight);\n \t}\n--- a/src/ap/sta_info.h\n+++ b/src/ap/sta_info.h\n@@ -324,6 +324,7 @@ struct sta_info {\n #endif /* CONFIG_TESTING_OPTIONS */\n #ifdef CONFIG_AIRTIME_POLICY\n \tunsigned int airtime_weight;\n+\tunsigned int dyn_airtime_weight;\n \tstruct os_reltime backlogged_until;\n #endif /* CONFIG_AIRTIME_POLICY */\n \n--- a/src/ap/wnm_ap.c\n+++ b/src/ap/wnm_ap.c\n@@ -442,7 +442,8 @@ static void ieee802_11_rx_bss_trans_mgmt\n \twpa_hexdump(MSG_DEBUG, \"WNM: BSS Transition Candidate List Entries\",\n \t\t    pos, end - pos);\n \n-\tieee802_11_send_bss_trans_mgmt_request(hapd, addr, dialog_token);\n+\tif (!hostapd_ubus_notify_bss_transition_query(hapd, addr, dialog_token, reason, pos, end - pos))\n+\t\tieee802_11_send_bss_trans_mgmt_request(hapd, addr, dialog_token);\n }\n \n \n@@ -464,7 +465,7 @@ static void ieee802_11_rx_bss_trans_mgmt\n \t\t\t\t\t      size_t len)\n {\n \tu8 dialog_token, status_code, bss_termination_delay;\n-\tconst u8 *pos, *end;\n+\tconst u8 *pos, *end, *target_bssid = NULL;\n \tint enabled = hapd->conf->bss_transition;\n \tstruct sta_info *sta;\n \n@@ -511,6 +512,7 @@ static void ieee802_11_rx_bss_trans_mgmt\n \t\t\twpa_printf(MSG_DEBUG, \"WNM: not enough room for Target BSSID field\");\n \t\t\treturn;\n \t\t}\n+\t\ttarget_bssid = pos;\n \t\tsta->agreed_to_steer = 1;\n \t\teloop_cancel_timeout(ap_sta_reset_steer_flag_timer, hapd, sta);\n \t\teloop_register_timeout(2, 0, ap_sta_reset_steer_flag_timer,\n@@ -530,6 +532,10 @@ static void ieee802_11_rx_bss_trans_mgmt\n \t\t\tMAC2STR(addr), status_code, bss_termination_delay);\n \t}\n \n+\thostapd_ubus_notify_bss_transition_response(hapd, sta->addr, dialog_token,\n+\t\t\t\t\t\t    status_code, bss_termination_delay,\n+\t\t\t\t\t\t    target_bssid, pos, end - pos);\n+\n \twpa_hexdump(MSG_DEBUG, \"WNM: BSS Transition Candidate List Entries\",\n \t\t    pos, end - pos);\n }\n"
  },
  {
    "path": "package/network/services/hostapd/patches/610-hostapd_cli_ujail_permission.patch",
    "content": "--- a/src/common/wpa_ctrl.c\n+++ b/src/common/wpa_ctrl.c\n@@ -135,7 +135,7 @@ try_again:\n \t\treturn NULL;\n \t}\n \ttries++;\n-#ifdef ANDROID\n+\n \t/* Set client socket file permissions so that bind() creates the client\n \t * socket with these permissions and there is no need to try to change\n \t * them with chmod() after bind() which would have potential issues with\n@@ -147,7 +147,7 @@ try_again:\n \t * operations to allow the response to go through. Those are using the\n \t * no-deference-symlinks version to avoid races. */\n \tfchmod(ctrl->s, S_IRUSR | S_IWUSR | S_IRGRP | S_IWGRP);\n-#endif /* ANDROID */\n+\n \tif (bind(ctrl->s, (struct sockaddr *) &ctrl->local,\n \t\t    sizeof(ctrl->local)) < 0) {\n \t\tif (errno == EADDRINUSE && tries < 2) {\n@@ -165,7 +165,11 @@ try_again:\n \t\treturn NULL;\n \t}\n \n-#ifdef ANDROID\n+#ifndef ANDROID\n+\t/* Set group even if we do not have privileges to change owner */\n+\tlchown(ctrl->local.sun_path, -1, 101);\n+\tlchown(ctrl->local.sun_path, 101, 101);\n+#else\n \t/* Set group even if we do not have privileges to change owner */\n \tlchown(ctrl->local.sun_path, -1, AID_WIFI);\n \tlchown(ctrl->local.sun_path, AID_SYSTEM, AID_WIFI);\n"
  },
  {
    "path": "package/network/services/hostapd/patches/700-wifi-reload.patch",
    "content": "--- a/hostapd/config_file.c\n+++ b/hostapd/config_file.c\n@@ -2458,6 +2458,8 @@ static int hostapd_config_fill(struct ho\n \t\tbss->isolate = atoi(pos);\n \t} else if (os_strcmp(buf, \"ap_max_inactivity\") == 0) {\n \t\tbss->ap_max_inactivity = atoi(pos);\n+\t} else if (os_strcmp(buf, \"config_id\") == 0) {\n+\t\tbss->config_id = os_strdup(pos);\n \t} else if (os_strcmp(buf, \"skip_inactivity_poll\") == 0) {\n \t\tbss->skip_inactivity_poll = atoi(pos);\n \t} else if (os_strcmp(buf, \"country_code\") == 0) {\n@@ -3158,6 +3160,8 @@ static int hostapd_config_fill(struct ho\n \t\t}\n \t} else if (os_strcmp(buf, \"acs_exclude_dfs\") == 0) {\n \t\tconf->acs_exclude_dfs = atoi(pos);\n+\t} else if (os_strcmp(buf, \"radio_config_id\") == 0) {\n+\t\t\tconf->config_id = os_strdup(pos);\n \t} else if (os_strcmp(buf, \"op_class\") == 0) {\n \t\tconf->op_class = atoi(pos);\n \t} else if (os_strcmp(buf, \"channel\") == 0) {\n--- a/src/ap/ap_config.c\n+++ b/src/ap/ap_config.c\n@@ -792,6 +792,7 @@ void hostapd_config_free_bss(struct host\n \tos_free(conf->radius_req_attr_sqlite);\n \tos_free(conf->rsn_preauth_interfaces);\n \tos_free(conf->ctrl_interface);\n+\tos_free(conf->config_id);\n \tos_free(conf->ca_cert);\n \tos_free(conf->server_cert);\n \tos_free(conf->server_cert2);\n@@ -988,6 +989,7 @@ void hostapd_config_free(struct hostapd_\n \n \tfor (i = 0; i < conf->num_bss; i++)\n \t\thostapd_config_free_bss(conf->bss[i]);\n+\tos_free(conf->config_id);\n \tos_free(conf->bss);\n \tos_free(conf->supported_rates);\n \tos_free(conf->basic_rates);\n--- a/src/ap/ap_config.h\n+++ b/src/ap/ap_config.h\n@@ -279,6 +279,8 @@ struct hostapd_bss_config {\n \tchar vlan_bridge[IFNAMSIZ + 1];\n \tchar wds_bridge[IFNAMSIZ + 1];\n \n+\tchar *config_id;\n+\n \tenum hostapd_logger_level logger_syslog_level, logger_stdout_level;\n \n \tunsigned int logger_syslog; /* module bitfield */\n@@ -942,6 +944,7 @@ struct spatial_reuse {\n struct hostapd_config {\n \tstruct hostapd_bss_config **bss, *last_bss;\n \tsize_t num_bss;\n+\tchar *config_id;\n \n \tu16 beacon_int;\n \tint rts_threshold;\n--- a/src/ap/hostapd.c\n+++ b/src/ap/hostapd.c\n@@ -219,6 +219,10 @@ static int hostapd_iface_conf_changed(st\n {\n \tsize_t i;\n \n+\tif (newconf->config_id != oldconf->config_id)\n+\t\tif (strcmp(newconf->config_id, oldconf->config_id))\n+\t\t\treturn 1;\n+\n \tif (newconf->num_bss != oldconf->num_bss)\n \t\treturn 1;\n \n@@ -232,7 +236,7 @@ static int hostapd_iface_conf_changed(st\n }\n \n \n-int hostapd_reload_config(struct hostapd_iface *iface)\n+int hostapd_reload_config(struct hostapd_iface *iface, int reconf)\n {\n \tstruct hapd_interfaces *interfaces = iface->interfaces;\n \tstruct hostapd_data *hapd = iface->bss[0];\n@@ -255,13 +259,16 @@ int hostapd_reload_config(struct hostapd\n \tif (newconf == NULL)\n \t\treturn -1;\n \n-\thostapd_clear_old(iface);\n-\n \toldconf = hapd->iconf;\n \tif (hostapd_iface_conf_changed(newconf, oldconf)) {\n \t\tchar *fname;\n \t\tint res;\n \n+\t\tif (reconf)\n+\t\t\treturn -1;\n+\n+\t\thostapd_clear_old(iface);\n+\n \t\twpa_printf(MSG_DEBUG,\n \t\t\t   \"Configuration changes include interface/BSS modification - force full disable+enable sequence\");\n \t\tfname = os_strdup(iface->config_fname);\n@@ -286,6 +293,24 @@ int hostapd_reload_config(struct hostapd\n \t\t\twpa_printf(MSG_ERROR,\n \t\t\t\t   \"Failed to enable interface on config reload\");\n \t\treturn res;\n+\t} else {\n+\t\tfor (j = 0; j < iface->num_bss; j++) {\n+\t\t\thapd = iface->bss[j];\n+\t\t\tif (!hapd->config_id || strcmp(hapd->config_id, newconf->bss[j]->config_id)) {\n+\t\t\t\thostapd_flush_old_stations(iface->bss[j],\n+\t\t\t\t\t\t\t   WLAN_REASON_PREV_AUTH_NOT_VALID);\n+#ifdef CONFIG_WEP\n+\t\t\t\thostapd_broadcast_wep_clear(iface->bss[j]);\n+#endif\n+\n+#ifndef CONFIG_NO_RADIUS\n+\t\t\t\t/* TODO: update dynamic data based on changed configuration\n+\t\t\t\t * items (e.g., open/close sockets, etc.) */\n+\t\t\t\tradius_client_flush(iface->bss[j]->radius, 0);\n+#endif /* CONFIG_NO_RADIUS */\n+\t\t\t\twpa_printf(MSG_INFO, \"bss %zu changed\", j);\n+\t\t\t}\n+\t\t}\n \t}\n \tiface->conf = newconf;\n \n@@ -302,6 +327,12 @@ int hostapd_reload_config(struct hostapd\n \n \tfor (j = 0; j < iface->num_bss; j++) {\n \t\thapd = iface->bss[j];\n+\t\tif (hapd->config_id) {\n+\t\t\tos_free(hapd->config_id);\n+\t\t\thapd->config_id = NULL;\n+\t\t}\n+\t\tif (newconf->bss[j]->config_id)\n+\t\t\thapd->config_id = strdup(newconf->bss[j]->config_id);\n \t\thapd->iconf = newconf;\n \t\thapd->conf = newconf->bss[j];\n \t\thostapd_reload_bss(hapd);\n@@ -2397,6 +2428,10 @@ hostapd_alloc_bss_data(struct hostapd_if\n \thapd->iconf = conf;\n \thapd->conf = bss;\n \thapd->iface = hapd_iface;\n+\tif (bss && bss->config_id)\n+\t\thapd->config_id = strdup(bss->config_id);\n+\telse\n+\t\thapd->config_id = NULL;\n \tif (conf)\n \t\thapd->driver = conf->driver;\n \thapd->ctrl_sock = -1;\n--- a/src/ap/hostapd.h\n+++ b/src/ap/hostapd.h\n@@ -46,7 +46,7 @@ struct mesh_conf;\n struct hostapd_iface;\n \n struct hapd_interfaces {\n-\tint (*reload_config)(struct hostapd_iface *iface);\n+\tint (*reload_config)(struct hostapd_iface *iface, int reconf);\n \tstruct hostapd_config * (*config_read_cb)(const char *config_fname);\n \tint (*ctrl_iface_init)(struct hostapd_data *hapd);\n \tvoid (*ctrl_iface_deinit)(struct hostapd_data *hapd);\n@@ -173,6 +173,7 @@ struct hostapd_data {\n \tstruct hostapd_config *iconf;\n \tstruct hostapd_bss_config *conf;\n \tstruct hostapd_ubus_bss ubus;\n+\tchar *config_id;\n \tint interface_added; /* virtual interface added for this BSS */\n \tunsigned int started:1;\n \tunsigned int disabled:1;\n@@ -624,7 +625,7 @@ struct hostapd_iface {\n int hostapd_for_each_interface(struct hapd_interfaces *interfaces,\n \t\t\t       int (*cb)(struct hostapd_iface *iface,\n \t\t\t\t\t void *ctx), void *ctx);\n-int hostapd_reload_config(struct hostapd_iface *iface);\n+int hostapd_reload_config(struct hostapd_iface *iface, int reconf);\n void hostapd_reconfig_encryption(struct hostapd_data *hapd);\n struct hostapd_data *\n hostapd_alloc_bss_data(struct hostapd_iface *hapd_iface,\n--- a/src/drivers/driver_nl80211.c\n+++ b/src/drivers/driver_nl80211.c\n@@ -4833,6 +4833,9 @@ static int wpa_driver_nl80211_set_ap(voi\n \tif (ret) {\n \t\twpa_printf(MSG_DEBUG, \"nl80211: Beacon set failed: %d (%s)\",\n \t\t\t   ret, strerror(-ret));\n+\t\tif (!bss->beacon_set)\n+\t\t\tret = 0;\n+\t\tbss->beacon_set = 0;\n \t} else {\n \t\tbss->beacon_set = 1;\n \t\tnl80211_set_bss(bss, params->cts_protect, params->preamble,\n--- a/hostapd/ctrl_iface.c\n+++ b/hostapd/ctrl_iface.c\n@@ -186,7 +186,7 @@ static int hostapd_ctrl_iface_update(str\n \tiface->interfaces->config_read_cb = hostapd_ctrl_iface_config_read;\n \treload_opts = txt;\n \n-\thostapd_reload_config(iface);\n+\thostapd_reload_config(iface, 0);\n \n \tiface->interfaces->config_read_cb = config_read_cb;\n }\n--- a/hostapd/main.c\n+++ b/hostapd/main.c\n@@ -317,7 +317,7 @@ static void handle_term(int sig, void *s\n \n static int handle_reload_iface(struct hostapd_iface *iface, void *ctx)\n {\n-\tif (hostapd_reload_config(iface) < 0) {\n+\tif (hostapd_reload_config(iface, 0) < 0) {\n \t\twpa_printf(MSG_WARNING, \"Failed to read new configuration \"\n \t\t\t   \"file - continuing with old.\");\n \t}\n--- a/src/ap/wps_hostapd.c\n+++ b/src/ap/wps_hostapd.c\n@@ -315,7 +315,7 @@ static void wps_reload_config(void *eloo\n \n \twpa_printf(MSG_DEBUG, \"WPS: Reload configuration data\");\n \tif (iface->interfaces == NULL ||\n-\t    iface->interfaces->reload_config(iface) < 0) {\n+\t    iface->interfaces->reload_config(iface, 1) < 0) {\n \t\twpa_printf(MSG_WARNING, \"WPS: Failed to reload the updated \"\n \t\t\t   \"configuration\");\n \t}\n"
  },
  {
    "path": "package/network/services/hostapd/patches/710-vlan_no_bridge.patch",
    "content": "--- a/src/ap/ap_config.h\n+++ b/src/ap/ap_config.h\n@@ -115,6 +115,7 @@ struct hostapd_ssid {\n #define DYNAMIC_VLAN_OPTIONAL 1\n #define DYNAMIC_VLAN_REQUIRED 2\n \tint dynamic_vlan;\n+\tint vlan_no_bridge;\n #define DYNAMIC_VLAN_NAMING_WITHOUT_DEVICE 0\n #define DYNAMIC_VLAN_NAMING_WITH_DEVICE 1\n #define DYNAMIC_VLAN_NAMING_END 2\n--- a/src/ap/vlan_full.c\n+++ b/src/ap/vlan_full.c\n@@ -475,6 +475,9 @@ void vlan_newlink(const char *ifname, st\n \tif (!vlan)\n \t\treturn;\n \n+\tif (hapd->conf->ssid.vlan_no_bridge)\n+\t\tgoto out;\n+\n \tvlan->configured = 1;\n \n \tnotempty = vlan->vlan_desc.notempty;\n@@ -506,6 +509,7 @@ void vlan_newlink(const char *ifname, st\n \t\t\t\t    ifname, br_name, tagged[i], hapd);\n \t}\n \n+out:\n \tifconfig_up(ifname);\n }\n \n--- a/hostapd/config_file.c\n+++ b/hostapd/config_file.c\n@@ -3381,6 +3381,8 @@ static int hostapd_config_fill(struct ho\n #ifndef CONFIG_NO_VLAN\n \t} else if (os_strcmp(buf, \"dynamic_vlan\") == 0) {\n \t\tbss->ssid.dynamic_vlan = atoi(pos);\n+\t} else if (os_strcmp(buf, \"vlan_no_bridge\") == 0) {\n+\t\tbss->ssid.vlan_no_bridge = atoi(pos);\n \t} else if (os_strcmp(buf, \"per_sta_vif\") == 0) {\n \t\tbss->ssid.per_sta_vif = atoi(pos);\n \t} else if (os_strcmp(buf, \"vlan_file\") == 0) {\n"
  },
  {
    "path": "package/network/services/hostapd/patches/711-wds_bridge_force.patch",
    "content": "--- a/hostapd/config_file.c\n+++ b/hostapd/config_file.c\n@@ -2358,6 +2358,8 @@ static int hostapd_config_fill(struct ho\n \t\t\t   sizeof(conf->bss[0]->iface));\n \t} else if (os_strcmp(buf, \"bridge\") == 0) {\n \t\tos_strlcpy(bss->bridge, pos, sizeof(bss->bridge));\n+\t\tif (!bss->wds_bridge[0])\n+\t\t\tos_strlcpy(bss->wds_bridge, pos, sizeof(bss->wds_bridge));\n \t} else if (os_strcmp(buf, \"vlan_bridge\") == 0) {\n \t\tos_strlcpy(bss->vlan_bridge, pos, sizeof(bss->vlan_bridge));\n \t} else if (os_strcmp(buf, \"wds_bridge\") == 0) {\n--- a/src/ap/ap_drv_ops.c\n+++ b/src/ap/ap_drv_ops.c\n@@ -340,8 +340,6 @@ int hostapd_set_wds_sta(struct hostapd_d\n \t\treturn -1;\n \tif (hapd->conf->wds_bridge[0])\n \t\tbridge = hapd->conf->wds_bridge;\n-\telse if (hapd->conf->bridge[0])\n-\t\tbridge = hapd->conf->bridge;\n \treturn hapd->driver->set_wds_sta(hapd->drv_priv, addr, aid, val,\n \t\t\t\t\t bridge, ifname_wds);\n }\n"
  },
  {
    "path": "package/network/services/hostapd/patches/720-iface_max_num_sta.patch",
    "content": "--- a/hostapd/config_file.c\n+++ b/hostapd/config_file.c\n@@ -2880,6 +2880,14 @@ static int hostapd_config_fill(struct ho\n \t\t\t\t   line, bss->max_num_sta, MAX_STA_COUNT);\n \t\t\treturn 1;\n \t\t}\n+\t} else if (os_strcmp(buf, \"iface_max_num_sta\") == 0) {\n+\t\tconf->max_num_sta = atoi(pos);\n+\t\tif (conf->max_num_sta < 0 ||\n+\t\t    conf->max_num_sta > MAX_STA_COUNT) {\n+\t\t\twpa_printf(MSG_ERROR, \"Line %d: Invalid max_num_sta=%d; allowed range 0..%d\",\n+\t\t\t\t   line, conf->max_num_sta, MAX_STA_COUNT);\n+\t\t\treturn 1;\n+\t\t}\n \t} else if (os_strcmp(buf, \"wpa\") == 0) {\n \t\tbss->wpa = atoi(pos);\n \t} else if (os_strcmp(buf, \"extended_key_id\") == 0) {\n--- a/src/ap/hostapd.h\n+++ b/src/ap/hostapd.h\n@@ -668,6 +668,7 @@ void hostapd_cleanup_cs_params(struct ho\n void hostapd_periodic_iface(struct hostapd_iface *iface);\n int hostapd_owe_trans_get_info(struct hostapd_data *hapd);\n void hostapd_ocv_check_csa_sa_query(void *eloop_ctx, void *timeout_ctx);\n+int hostapd_check_max_sta(struct hostapd_data *hapd);\n \n /* utils.c */\n int hostapd_register_probereq_cb(struct hostapd_data *hapd,\n--- a/src/ap/hostapd.c\n+++ b/src/ap/hostapd.c\n@@ -236,6 +236,30 @@ static int hostapd_iface_conf_changed(st\n }\n \n \n+static inline int hostapd_iface_num_sta(struct hostapd_iface *iface)\n+{\n+\tint num_sta = 0;\n+\tint i;\n+\n+\tfor (i = 0; i < iface->num_bss; i++)\n+\t\tnum_sta += iface->bss[i]->num_sta;\n+\n+\treturn num_sta;\n+}\n+\n+\n+int hostapd_check_max_sta(struct hostapd_data *hapd)\n+{\n+\tif (hapd->num_sta >= hapd->conf->max_num_sta)\n+\t\treturn 1;\n+\n+\tif (hapd->iconf->max_num_sta &&\n+\t    hostapd_iface_num_sta(hapd->iface) >= hapd->iconf->max_num_sta)\n+\t\treturn 1;\n+\n+\treturn 0;\n+}\n+\n int hostapd_reload_config(struct hostapd_iface *iface, int reconf)\n {\n \tstruct hapd_interfaces *interfaces = iface->interfaces;\n--- a/src/ap/beacon.c\n+++ b/src/ap/beacon.c\n@@ -1068,7 +1068,7 @@ void handle_probe_req(struct hostapd_dat\n \tif (hapd->conf->no_probe_resp_if_max_sta &&\n \t    is_multicast_ether_addr(mgmt->da) &&\n \t    is_multicast_ether_addr(mgmt->bssid) &&\n-\t    hapd->num_sta >= hapd->conf->max_num_sta &&\n+\t    hostapd_check_max_sta(hapd) &&\n \t    !ap_get_sta(hapd, mgmt->sa)) {\n \t\twpa_printf(MSG_MSGDUMP, \"%s: Ignore Probe Request from \" MACSTR\n \t\t\t   \" since no room for additional STA\",\n--- a/src/ap/ap_config.h\n+++ b/src/ap/ap_config.h\n@@ -981,6 +981,8 @@ struct hostapd_config {\n \tunsigned int track_sta_max_num;\n \tunsigned int track_sta_max_age;\n \n+\tint max_num_sta;\n+\n \tchar country[3]; /* first two octets: country code as described in\n \t\t\t  * ISO/IEC 3166-1. Third octet:\n \t\t\t  * ' ' (ascii 32): all environments\n"
  },
  {
    "path": "package/network/services/hostapd/patches/730-ft_iface.patch",
    "content": "--- a/hostapd/config_file.c\n+++ b/hostapd/config_file.c\n@@ -3038,6 +3038,8 @@ static int hostapd_config_fill(struct ho\n \t\twpa_printf(MSG_INFO,\n \t\t\t   \"Line %d: Obsolete peerkey parameter ignored\", line);\n #ifdef CONFIG_IEEE80211R_AP\n+\t} else if (os_strcmp(buf, \"ft_iface\") == 0) {\n+\t\tos_strlcpy(bss->ft_iface, pos, sizeof(bss->ft_iface));\n \t} else if (os_strcmp(buf, \"mobility_domain\") == 0) {\n \t\tif (os_strlen(pos) != 2 * MOBILITY_DOMAIN_ID_LEN ||\n \t\t    hexstr2bin(pos, bss->mobility_domain,\n--- a/src/ap/ap_config.h\n+++ b/src/ap/ap_config.h\n@@ -277,6 +277,7 @@ struct airtime_sta_weight {\n struct hostapd_bss_config {\n \tchar iface[IFNAMSIZ + 1];\n \tchar bridge[IFNAMSIZ + 1];\n+\tchar ft_iface[IFNAMSIZ + 1];\n \tchar vlan_bridge[IFNAMSIZ + 1];\n \tchar wds_bridge[IFNAMSIZ + 1];\n \n--- a/src/ap/wpa_auth_glue.c\n+++ b/src/ap/wpa_auth_glue.c\n@@ -1566,8 +1566,12 @@ int hostapd_setup_wpa(struct hostapd_dat\n \t    wpa_key_mgmt_ft(hapd->conf->wpa_key_mgmt)) {\n \t\tconst char *ft_iface;\n \n-\t\tft_iface = hapd->conf->bridge[0] ? hapd->conf->bridge :\n-\t\t\t   hapd->conf->iface;\n+\t\tif (hapd->conf->ft_iface[0])\n+\t\t\tft_iface = hapd->conf->ft_iface;\n+\t\telse if (hapd->conf->bridge[0])\n+\t\t\tft_iface = hapd->conf->bridge;\n+\t\telse\n+\t\t\tft_iface = hapd->conf->iface;\n \t\thapd->l2 = l2_packet_init(ft_iface, NULL, ETH_P_RRB,\n \t\t\t\t\t  hostapd_rrb_receive, hapd, 1);\n \t\tif (!hapd->l2) {\n"
  },
  {
    "path": "package/network/services/hostapd/patches/740-snoop_iface.patch",
    "content": "--- a/src/ap/ap_config.h\n+++ b/src/ap/ap_config.h\n@@ -278,6 +278,7 @@ struct hostapd_bss_config {\n \tchar iface[IFNAMSIZ + 1];\n \tchar bridge[IFNAMSIZ + 1];\n \tchar ft_iface[IFNAMSIZ + 1];\n+\tchar snoop_iface[IFNAMSIZ + 1];\n \tchar vlan_bridge[IFNAMSIZ + 1];\n \tchar wds_bridge[IFNAMSIZ + 1];\n \n--- a/src/ap/x_snoop.c\n+++ b/src/ap/x_snoop.c\n@@ -31,14 +31,16 @@ int x_snoop_init(struct hostapd_data *ha\n \t\treturn -1;\n \t}\n \n-\tif (hostapd_drv_br_port_set_attr(hapd, DRV_BR_PORT_ATTR_HAIRPIN_MODE,\n+\tif (!conf->snoop_iface[0] &&\n+\t    hostapd_drv_br_port_set_attr(hapd, DRV_BR_PORT_ATTR_HAIRPIN_MODE,\n \t\t\t\t\t 1)) {\n \t\twpa_printf(MSG_DEBUG,\n \t\t\t   \"x_snoop: Failed to enable hairpin_mode on the bridge port\");\n \t\treturn -1;\n \t}\n \n-\tif (hostapd_drv_br_port_set_attr(hapd, DRV_BR_PORT_ATTR_PROXYARP, 1)) {\n+\tif (!conf->snoop_iface[0] &&\n+\t    hostapd_drv_br_port_set_attr(hapd, DRV_BR_PORT_ATTR_PROXYARP, 1)) {\n \t\twpa_printf(MSG_DEBUG,\n \t\t\t   \"x_snoop: Failed to enable proxyarp on the bridge port\");\n \t\treturn -1;\n@@ -52,7 +54,8 @@ int x_snoop_init(struct hostapd_data *ha\n \t}\n \n #ifdef CONFIG_IPV6\n-\tif (hostapd_drv_br_set_net_param(hapd, DRV_BR_MULTICAST_SNOOPING, 1)) {\n+\tif (!conf->snoop_iface[0] &&\n+\t    hostapd_drv_br_set_net_param(hapd, DRV_BR_MULTICAST_SNOOPING, 1)) {\n \t\twpa_printf(MSG_DEBUG,\n \t\t\t   \"x_snoop: Failed to enable multicast snooping on the bridge\");\n \t\treturn -1;\n@@ -71,8 +74,12 @@ x_snoop_get_l2_packet(struct hostapd_dat\n {\n \tstruct hostapd_bss_config *conf = hapd->conf;\n \tstruct l2_packet_data *l2;\n+\tconst char *ifname = conf->bridge;\n \n-\tl2 = l2_packet_init(conf->bridge, NULL, ETH_P_ALL, handler, hapd, 1);\n+\tif (conf->snoop_iface[0])\n+\t\tifname = conf->snoop_iface;\n+\n+\tl2 = l2_packet_init(ifname, NULL, ETH_P_ALL, handler, hapd, 1);\n \tif (l2 == NULL) {\n \t\twpa_printf(MSG_DEBUG,\n \t\t\t   \"x_snoop: Failed to initialize L2 packet processing %s\",\n--- a/hostapd/config_file.c\n+++ b/hostapd/config_file.c\n@@ -2360,6 +2360,8 @@ static int hostapd_config_fill(struct ho\n \t\tos_strlcpy(bss->bridge, pos, sizeof(bss->bridge));\n \t\tif (!bss->wds_bridge[0])\n \t\t\tos_strlcpy(bss->wds_bridge, pos, sizeof(bss->wds_bridge));\n+\t} else if (os_strcmp(buf, \"snoop_iface\") == 0) {\n+\t\tos_strlcpy(bss->snoop_iface, pos, sizeof(bss->snoop_iface));\n \t} else if (os_strcmp(buf, \"vlan_bridge\") == 0) {\n \t\tos_strlcpy(bss->vlan_bridge, pos, sizeof(bss->vlan_bridge));\n \t} else if (os_strcmp(buf, \"wds_bridge\") == 0) {\n"
  },
  {
    "path": "package/network/services/hostapd/patches/750-qos_map_set_without_interworking.patch",
    "content": "--- a/hostapd/config_file.c\n+++ b/hostapd/config_file.c\n@@ -1644,6 +1644,8 @@ static int parse_anqp_elem(struct hostap\n \treturn 0;\n }\n \n+#endif /* CONFIG_INTERWORKING */\n+\n \n static int parse_qos_map_set(struct hostapd_bss_config *bss,\n \t\t\t     char *buf, int line)\n@@ -1685,8 +1687,6 @@ static int parse_qos_map_set(struct host\n \treturn 0;\n }\n \n-#endif /* CONFIG_INTERWORKING */\n-\n \n #ifdef CONFIG_HS20\n static int hs20_parse_conn_capab(struct hostapd_bss_config *bss, char *buf,\n@@ -4077,10 +4077,10 @@ static int hostapd_config_fill(struct ho\n \t\tbss->gas_frag_limit = val;\n \t} else if (os_strcmp(buf, \"gas_comeback_delay\") == 0) {\n \t\tbss->gas_comeback_delay = atoi(pos);\n+#endif /* CONFIG_INTERWORKING */\n \t} else if (os_strcmp(buf, \"qos_map_set\") == 0) {\n \t\tif (parse_qos_map_set(bss, pos, line) < 0)\n \t\t\treturn 1;\n-#endif /* CONFIG_INTERWORKING */\n #ifdef CONFIG_RADIUS_TEST\n \t} else if (os_strcmp(buf, \"dump_msk_file\") == 0) {\n \t\tos_free(bss->dump_msk_file);\n--- a/src/ap/hostapd.c\n+++ b/src/ap/hostapd.c\n@@ -1415,6 +1415,7 @@ static int hostapd_setup_bss(struct host\n \t\twpa_printf(MSG_ERROR, \"GAS server initialization failed\");\n \t\treturn -1;\n \t}\n+#endif /* CONFIG_INTERWORKING */\n \n \tif (conf->qos_map_set_len &&\n \t    hostapd_drv_set_qos_map(hapd, conf->qos_map_set,\n@@ -1422,7 +1423,6 @@ static int hostapd_setup_bss(struct host\n \t\twpa_printf(MSG_ERROR, \"Failed to initialize QoS Map\");\n \t\treturn -1;\n \t}\n-#endif /* CONFIG_INTERWORKING */\n \n \tif (conf->bss_load_update_period && bss_load_update_init(hapd)) {\n \t\twpa_printf(MSG_ERROR, \"BSS Load initialization failed\");\n--- a/src/ap/drv_callbacks.c\n+++ b/src/ap/drv_callbacks.c\n@@ -271,12 +271,10 @@ int hostapd_notif_assoc(struct hostapd_d\n \t}\n #endif /* NEED_AP_MLME */\n \n-#ifdef CONFIG_INTERWORKING\n \tif (elems.ext_capab && elems.ext_capab_len > 4) {\n \t\tif (elems.ext_capab[4] & 0x01)\n \t\t\tsta->qos_map_enabled = 1;\n \t}\n-#endif /* CONFIG_INTERWORKING */\n \n #ifdef CONFIG_HS20\n \twpabuf_free(sta->hs20_ie);\n--- a/src/ap/ieee802_11.c\n+++ b/src/ap/ieee802_11.c\n@@ -4129,13 +4129,11 @@ static u16 copy_supp_rates(struct hostap\n static u16 check_ext_capab(struct hostapd_data *hapd, struct sta_info *sta,\n \t\t\t   const u8 *ext_capab_ie, size_t ext_capab_ie_len)\n {\n-#ifdef CONFIG_INTERWORKING\n \t/* check for QoS Map support */\n \tif (ext_capab_ie_len >= 5) {\n \t\tif (ext_capab_ie[4] & 0x01)\n \t\t\tsta->qos_map_enabled = 1;\n \t}\n-#endif /* CONFIG_INTERWORKING */\n \n \tif (ext_capab_ie_len > 0) {\n \t\tsta->ecsa_supported = !!(ext_capab_ie[0] & BIT(2));\n--- a/wpa_supplicant/events.c\n+++ b/wpa_supplicant/events.c\n@@ -2540,8 +2540,6 @@ void wnm_bss_keep_alive_deinit(struct wp\n }\n \n \n-#ifdef CONFIG_INTERWORKING\n-\n static int wpas_qos_map_set(struct wpa_supplicant *wpa_s, const u8 *qos_map,\n \t\t\t    size_t len)\n {\n@@ -2574,8 +2572,6 @@ static void interworking_process_assoc_r\n \t}\n }\n \n-#endif /* CONFIG_INTERWORKING */\n-\n \n static void multi_ap_process_assoc_resp(struct wpa_supplicant *wpa_s,\n \t\t\t\t\tconst u8 *ies, size_t ies_len)\n@@ -2908,10 +2904,8 @@ static int wpa_supplicant_event_associnf\n \t\twnm_process_assoc_resp(wpa_s, data->assoc_info.resp_ies,\n \t\t\t\t       data->assoc_info.resp_ies_len);\n #endif /* CONFIG_WNM */\n-#ifdef CONFIG_INTERWORKING\n \t\tinterworking_process_assoc_resp(wpa_s, data->assoc_info.resp_ies,\n \t\t\t\t\t\tdata->assoc_info.resp_ies_len);\n-#endif /* CONFIG_INTERWORKING */\n \t\tif (wpa_s->hw_capab == CAPAB_VHT &&\n \t\t    get_ie(data->assoc_info.resp_ies,\n \t\t\t   data->assoc_info.resp_ies_len, WLAN_EID_VHT_CAP))\n"
  },
  {
    "path": "package/network/services/hostapd/patches/751-qos_map_ignore_when_unsupported.patch",
    "content": "--- a/src/ap/ap_drv_ops.c\n+++ b/src/ap/ap_drv_ops.c\n@@ -850,7 +850,8 @@ int hostapd_start_dfs_cac(struct hostapd\n int hostapd_drv_set_qos_map(struct hostapd_data *hapd,\n \t\t\t    const u8 *qos_map_set, u8 qos_map_set_len)\n {\n-\tif (!hapd->driver || !hapd->driver->set_qos_map || !hapd->drv_priv)\n+\tif (!hapd->driver || !hapd->driver->set_qos_map || !hapd->drv_priv ||\n+\t    !(hapd->iface->drv_flags & WPA_DRIVER_FLAGS_QOS_MAPPING))\n \t\treturn 0;\n \treturn hapd->driver->set_qos_map(hapd->drv_priv, qos_map_set,\n \t\t\t\t\t qos_map_set_len);\n"
  },
  {
    "path": "package/network/services/hostapd/src/src/ap/ubus.c",
    "content": "/*\n * hostapd / ubus support\n * Copyright (c) 2013, Felix Fietkau <nbd@nbd.name>\n *\n * This software may be distributed under the terms of the BSD license.\n * See README for more details.\n */\n\n#include \"utils/includes.h\"\n#include \"utils/common.h\"\n#include \"utils/eloop.h\"\n#include \"utils/wpabuf.h\"\n#include \"common/ieee802_11_defs.h\"\n#include \"common/hw_features_common.h\"\n#include \"hostapd.h\"\n#include \"neighbor_db.h\"\n#include \"wps_hostapd.h\"\n#include \"sta_info.h\"\n#include \"ubus.h\"\n#include \"ap_drv_ops.h\"\n#include \"beacon.h\"\n#include \"rrm.h\"\n#include \"wnm_ap.h\"\n#include \"taxonomy.h\"\n#include \"airtime_policy.h\"\n#include \"hw_features.h\"\n\nstatic struct ubus_context *ctx;\nstatic struct blob_buf b;\nstatic int ctx_ref;\n\nstatic inline struct hapd_interfaces *get_hapd_interfaces_from_object(struct ubus_object *obj)\n{\n\treturn container_of(obj, struct hapd_interfaces, ubus);\n}\n\nstatic inline struct hostapd_data *get_hapd_from_object(struct ubus_object *obj)\n{\n\treturn container_of(obj, struct hostapd_data, ubus.obj);\n}\n\nstruct ubus_banned_client {\n\tstruct avl_node avl;\n\tu8 addr[ETH_ALEN];\n};\n\nstatic void ubus_receive(int sock, void *eloop_ctx, void *sock_ctx)\n{\n\tstruct ubus_context *ctx = eloop_ctx;\n\tubus_handle_event(ctx);\n}\n\nstatic void ubus_reconnect_timeout(void *eloop_data, void *user_ctx)\n{\n\tif (ubus_reconnect(ctx, NULL)) {\n\t\teloop_register_timeout(1, 0, ubus_reconnect_timeout, ctx, NULL);\n\t\treturn;\n\t}\n\n\teloop_register_read_sock(ctx->sock.fd, ubus_receive, ctx, NULL);\n}\n\nstatic void hostapd_ubus_connection_lost(struct ubus_context *ctx)\n{\n\teloop_unregister_read_sock(ctx->sock.fd);\n\teloop_register_timeout(1, 0, ubus_reconnect_timeout, ctx, NULL);\n}\n\nstatic bool hostapd_ubus_init(void)\n{\n\tif (ctx)\n\t\treturn true;\n\n\tctx = ubus_connect(NULL);\n\tif (!ctx)\n\t\treturn false;\n\n\tctx->connection_lost = hostapd_ubus_connection_lost;\n\teloop_register_read_sock(ctx->sock.fd, ubus_receive, ctx, NULL);\n\treturn true;\n}\n\nstatic void hostapd_ubus_ref_inc(void)\n{\n\tctx_ref++;\n}\n\nstatic void hostapd_ubus_ref_dec(void)\n{\n\tctx_ref--;\n\tif (!ctx)\n\t\treturn;\n\n\tif (ctx_ref)\n\t\treturn;\n\n\teloop_unregister_read_sock(ctx->sock.fd);\n\tubus_free(ctx);\n\tctx = NULL;\n}\n\nvoid hostapd_ubus_add_iface(struct hostapd_iface *iface)\n{\n\tif (!hostapd_ubus_init())\n\t\treturn;\n}\n\nvoid hostapd_ubus_free_iface(struct hostapd_iface *iface)\n{\n\tif (!ctx)\n\t\treturn;\n}\n\nstatic void hostapd_notify_ubus(struct ubus_object *obj, char *bssname, char *event)\n{\n\tchar *event_type;\n\n\tif (!ctx || !obj)\n\t\treturn;\n\n\tif (asprintf(&event_type, \"bss.%s\", event) < 0)\n\t\treturn;\n\n\tblob_buf_init(&b, 0);\n\tblobmsg_add_string(&b, \"name\", bssname);\n\tubus_notify(ctx, obj, event_type, b.head, -1);\n\tfree(event_type);\n}\n\nstatic void hostapd_send_procd_event(char *bssname, char *event)\n{\n\tchar *name, *s;\n\tuint32_t id;\n\tvoid *v;\n\n\tif (!ctx || ubus_lookup_id(ctx, \"service\", &id))\n\t\treturn;\n\n\tif (asprintf(&name, \"hostapd.%s.%s\", bssname, event) < 0)\n\t\treturn;\n\n\tblob_buf_init(&b, 0);\n\n\ts = blobmsg_alloc_string_buffer(&b, \"type\", strlen(name) + 1);\n\tsprintf(s, \"%s\", name);\n\tblobmsg_add_string_buffer(&b);\n\n\tv = blobmsg_open_table(&b, \"data\");\n\tblobmsg_close_table(&b, v);\n\n\tubus_invoke(ctx, id, \"event\", b.head, NULL, NULL, 1000);\n\n\tfree(name);\n}\n\nstatic void hostapd_send_shared_event(struct ubus_object *obj, char *bssname, char *event)\n{\n\thostapd_send_procd_event(bssname, event);\n\thostapd_notify_ubus(obj, bssname, event);\n}\n\nstatic void\nhostapd_bss_del_ban(void *eloop_data, void *user_ctx)\n{\n\tstruct ubus_banned_client *ban = eloop_data;\n\tstruct hostapd_data *hapd = user_ctx;\n\n\tavl_delete(&hapd->ubus.banned, &ban->avl);\n\tfree(ban);\n}\n\nstatic void\nhostapd_bss_ban_client(struct hostapd_data *hapd, u8 *addr, int time)\n{\n\tstruct ubus_banned_client *ban;\n\n\tif (time < 0)\n\t\ttime = 0;\n\n\tban = avl_find_element(&hapd->ubus.banned, addr, ban, avl);\n\tif (!ban) {\n\t\tif (!time)\n\t\t\treturn;\n\n\t\tban = os_zalloc(sizeof(*ban));\n\t\tmemcpy(ban->addr, addr, sizeof(ban->addr));\n\t\tban->avl.key = ban->addr;\n\t\tavl_insert(&hapd->ubus.banned, &ban->avl);\n\t} else {\n\t\teloop_cancel_timeout(hostapd_bss_del_ban, ban, hapd);\n\t\tif (!time) {\n\t\t\thostapd_bss_del_ban(ban, hapd);\n\t\t\treturn;\n\t\t}\n\t}\n\n\teloop_register_timeout(0, time * 1000, hostapd_bss_del_ban, ban, hapd);\n}\n\nstatic int\nhostapd_bss_reload(struct ubus_context *ctx, struct ubus_object *obj,\n\t\t   struct ubus_request_data *req, const char *method,\n\t\t   struct blob_attr *msg)\n{\n\tstruct hostapd_data *hapd = container_of(obj, struct hostapd_data, ubus.obj);\n\tint ret = hostapd_reload_config(hapd->iface, 1);\n\n\thostapd_send_shared_event(&hapd->iface->interfaces->ubus, hapd->conf->iface, \"reload\");\n\treturn ret;\n}\n\n\nstatic void\nhostapd_parse_vht_map_blobmsg(uint16_t map)\n{\n\tchar label[4];\n\tint16_t val;\n\tint i;\n\n\tfor (i = 0; i < 8; i++) {\n\t\tsnprintf(label, 4, \"%dss\", i + 1);\n\n\t\tval = (map & (BIT(1) | BIT(0))) + 7;\n\t\tblobmsg_add_u16(&b, label, val == 10 ? -1 : val);\n\t\tmap = map >> 2;\n\t}\n}\n\nstatic void\nhostapd_parse_vht_capab_blobmsg(struct ieee80211_vht_capabilities *vhtc)\n{\n\tvoid *supported_mcs;\n\tvoid *map;\n\tint i;\n\n\tstatic const struct {\n\t\tconst char *name;\n\t\tuint32_t flag;\n\t} vht_capas[] = {\n\t\t{ \"su_beamformee\", VHT_CAP_SU_BEAMFORMEE_CAPABLE },\n\t\t{ \"mu_beamformee\", VHT_CAP_MU_BEAMFORMEE_CAPABLE },\n\t};\n\n\tfor (i = 0; i < ARRAY_SIZE(vht_capas); i++)\n\t\tblobmsg_add_u8(&b, vht_capas[i].name,\n\t\t\t\t!!(vhtc->vht_capabilities_info & vht_capas[i].flag));\n\n\tsupported_mcs = blobmsg_open_table(&b, \"mcs_map\");\n\n\t/* RX map */\n\tmap = blobmsg_open_table(&b, \"rx\");\n\thostapd_parse_vht_map_blobmsg(le_to_host16(vhtc->vht_supported_mcs_set.rx_map));\n\tblobmsg_close_table(&b, map);\n\n\t/* TX map */\n\tmap = blobmsg_open_table(&b, \"tx\");\n\thostapd_parse_vht_map_blobmsg(le_to_host16(vhtc->vht_supported_mcs_set.tx_map));\n\tblobmsg_close_table(&b, map);\n\n\tblobmsg_close_table(&b, supported_mcs);\n}\n\nstatic void\nhostapd_parse_capab_blobmsg(struct sta_info *sta)\n{\n\tvoid *r, *v;\n\n\tv = blobmsg_open_table(&b, \"capabilities\");\n\n\tif (sta->vht_capabilities) {\n\t\tr = blobmsg_open_table(&b, \"vht\");\n\t\thostapd_parse_vht_capab_blobmsg(sta->vht_capabilities);\n\t\tblobmsg_close_table(&b, r);\n\t}\n\n\t/* ToDo: Add HT / HE capability parsing */\n\n\tblobmsg_close_table(&b, v);\n}\n\nstatic int\nhostapd_bss_get_clients(struct ubus_context *ctx, struct ubus_object *obj,\n\t\t\tstruct ubus_request_data *req, const char *method,\n\t\t\tstruct blob_attr *msg)\n{\n\tstruct hostapd_data *hapd = container_of(obj, struct hostapd_data, ubus.obj);\n\tstruct hostap_sta_driver_data sta_driver_data;\n\tstruct sta_info *sta;\n\tvoid *list, *c;\n\tchar mac_buf[20];\n\tstatic const struct {\n\t\tconst char *name;\n\t\tuint32_t flag;\n\t} sta_flags[] = {\n\t\t{ \"auth\", WLAN_STA_AUTH },\n\t\t{ \"assoc\", WLAN_STA_ASSOC },\n\t\t{ \"authorized\", WLAN_STA_AUTHORIZED },\n\t\t{ \"preauth\", WLAN_STA_PREAUTH },\n\t\t{ \"wds\", WLAN_STA_WDS },\n\t\t{ \"wmm\", WLAN_STA_WMM },\n\t\t{ \"ht\", WLAN_STA_HT },\n\t\t{ \"vht\", WLAN_STA_VHT },\n\t\t{ \"he\", WLAN_STA_HE },\n\t\t{ \"wps\", WLAN_STA_WPS },\n\t\t{ \"mfp\", WLAN_STA_MFP },\n\t};\n\n\tblob_buf_init(&b, 0);\n\tblobmsg_add_u32(&b, \"freq\", hapd->iface->freq);\n\tlist = blobmsg_open_table(&b, \"clients\");\n\tfor (sta = hapd->sta_list; sta; sta = sta->next) {\n\t\tvoid *r;\n\t\tint i;\n\n\t\tsprintf(mac_buf, MACSTR, MAC2STR(sta->addr));\n\t\tc = blobmsg_open_table(&b, mac_buf);\n\t\tfor (i = 0; i < ARRAY_SIZE(sta_flags); i++)\n\t\t\tblobmsg_add_u8(&b, sta_flags[i].name,\n\t\t\t\t       !!(sta->flags & sta_flags[i].flag));\n\n\t\tr = blobmsg_open_array(&b, \"rrm\");\n\t\tfor (i = 0; i < ARRAY_SIZE(sta->rrm_enabled_capa); i++)\n\t\t\tblobmsg_add_u32(&b, \"\", sta->rrm_enabled_capa[i]);\n\t\tblobmsg_close_array(&b, r);\n\n\t\tr = blobmsg_open_array(&b, \"extended_capabilities\");\n\t\t/* Check if client advertises extended capabilities */\n\t\tif (sta->ext_capability && sta->ext_capability[0] > 0) {\n\t\t\tfor (i = 0; i < sta->ext_capability[0]; i++) {\n\t\t\t\tblobmsg_add_u32(&b, \"\", sta->ext_capability[1 + i]);\n\t\t\t}\n\t\t}\n\t\tblobmsg_close_array(&b, r);\n\n\t\tblobmsg_add_u32(&b, \"aid\", sta->aid);\n#ifdef CONFIG_TAXONOMY\n\t\tr = blobmsg_alloc_string_buffer(&b, \"signature\", 1024);\n\t\tif (retrieve_sta_taxonomy(hapd, sta, r, 1024) > 0)\n\t\t\tblobmsg_add_string_buffer(&b);\n#endif\n\n\t\t/* Driver information */\n\t\tif (hostapd_drv_read_sta_data(hapd, &sta_driver_data, sta->addr) >= 0) {\n\t\t\tr = blobmsg_open_table(&b, \"bytes\");\n\t\t\tblobmsg_add_u64(&b, \"rx\", sta_driver_data.rx_bytes);\n\t\t\tblobmsg_add_u64(&b, \"tx\", sta_driver_data.tx_bytes);\n\t\t\tblobmsg_close_table(&b, r);\n\t\t\tr = blobmsg_open_table(&b, \"airtime\");\n\t\t\tblobmsg_add_u64(&b, \"rx\", sta_driver_data.rx_airtime);\n\t\t\tblobmsg_add_u64(&b, \"tx\", sta_driver_data.tx_airtime);\n\t\t\tblobmsg_close_table(&b, r);\n\t\t\tr = blobmsg_open_table(&b, \"packets\");\n\t\t\tblobmsg_add_u32(&b, \"rx\", sta_driver_data.rx_packets);\n\t\t\tblobmsg_add_u32(&b, \"tx\", sta_driver_data.tx_packets);\n\t\t\tblobmsg_close_table(&b, r);\n\t\t\tr = blobmsg_open_table(&b, \"rate\");\n\t\t\t/* Rate in kbits */\n\t\t\tblobmsg_add_u32(&b, \"rx\", sta_driver_data.current_rx_rate * 100);\n\t\t\tblobmsg_add_u32(&b, \"tx\", sta_driver_data.current_tx_rate * 100);\n\t\t\tblobmsg_close_table(&b, r);\n\t\t\tblobmsg_add_u32(&b, \"signal\", sta_driver_data.signal);\n\t\t}\n\n\t\thostapd_parse_capab_blobmsg(sta);\n\n\t\tblobmsg_close_table(&b, c);\n\t}\n\tblobmsg_close_array(&b, list);\n\tubus_send_reply(ctx, req, b.head);\n\n\treturn 0;\n}\n\nstatic int\nhostapd_bss_get_features(struct ubus_context *ctx, struct ubus_object *obj,\n\t\t\tstruct ubus_request_data *req, const char *method,\n\t\t\tstruct blob_attr *msg)\n{\n\tstruct hostapd_data *hapd = container_of(obj, struct hostapd_data, ubus.obj);\n\n\tblob_buf_init(&b, 0);\n\tblobmsg_add_u8(&b, \"ht_supported\", ht_supported(hapd->iface->hw_features));\n\tblobmsg_add_u8(&b, \"vht_supported\", vht_supported(hapd->iface->hw_features));\n\tubus_send_reply(ctx, req, b.head);\n\n\treturn 0;\n}\n\n/* Imported from iw/util.c\n *  https://git.kernel.org/pub/scm/linux/kernel/git/jberg/iw.git/tree/util.c?id=4b25ae3537af48dbf9d0abf94132e5ba01b32c18#n200\n */\nint ieee80211_frequency_to_channel(int freq)\n{\n\t/* see 802.11-2007 17.3.8.3.2 and Annex J */\n\tif (freq == 2484)\n\t\treturn 14;\n\t/* see 802.11ax D6.1 27.3.23.2 and Annex E */\n\telse if (freq == 5935)\n\t\treturn 2;\n\telse if (freq < 2484)\n\t\treturn (freq - 2407) / 5;\n\telse if (freq >= 4910 && freq <= 4980)\n\t\treturn (freq - 4000) / 5;\n\telse if (freq < 5950)\n\t\treturn (freq - 5000) / 5;\n\telse if (freq <= 45000) /* DMG band lower limit */\n\t\t/* see 802.11ax D6.1 27.3.23.2 */\n\t\treturn (freq - 5950) / 5;\n\telse if (freq >= 58320 && freq <= 70200)\n\t\treturn (freq - 56160) / 2160;\n\telse\n\t\treturn 0;\n}\n\nstatic int\nhostapd_bss_get_status(struct ubus_context *ctx, struct ubus_object *obj,\n\t\t       struct ubus_request_data *req, const char *method,\n\t\t       struct blob_attr *msg)\n{\n\tstruct hostapd_data *hapd = container_of(obj, struct hostapd_data, ubus.obj);\n\tvoid *airtime_table, *dfs_table, *rrm_table, *wnm_table;\n\tstruct os_reltime now;\n\tchar ssid[SSID_MAX_LEN + 1];\n\tchar phy_name[17];\n\tsize_t ssid_len = SSID_MAX_LEN;\n\tu8 channel = 0, op_class = 0;\n\n\tif (hapd->conf->ssid.ssid_len < SSID_MAX_LEN)\n\t\tssid_len = hapd->conf->ssid.ssid_len;\n\t\n\tieee80211_freq_to_channel_ext(hapd->iface->freq,\n\t\t\t\t      hapd->iconf->secondary_channel,\n\t\t\t\t      hostapd_get_oper_chwidth(hapd->iconf),\n\t\t\t\t      &op_class, &channel);\n\n\tblob_buf_init(&b, 0);\n\tblobmsg_add_string(&b, \"status\", hostapd_state_text(hapd->iface->state));\n\tblobmsg_printf(&b, \"bssid\", MACSTR, MAC2STR(hapd->conf->bssid));\n\n\tmemset(ssid, 0, SSID_MAX_LEN + 1);\n\tmemcpy(ssid, hapd->conf->ssid.ssid, ssid_len);\n\tblobmsg_add_string(&b, \"ssid\", ssid);\n\n\tblobmsg_add_u32(&b, \"freq\", hapd->iface->freq);\n\tblobmsg_add_u32(&b, \"channel\", channel);\n\tblobmsg_add_u32(&b, \"op_class\", op_class);\n\tblobmsg_add_u32(&b, \"beacon_interval\", hapd->iconf->beacon_int);\n\n\tsnprintf(phy_name, 17, \"%s\", hapd->iface->phy);\n\tblobmsg_add_string(&b, \"phy\", phy_name);\n\n\t/* RRM */\n\trrm_table = blobmsg_open_table(&b, \"rrm\");\n\tblobmsg_add_u64(&b, \"neighbor_report_tx\", hapd->openwrt_stats.rrm.neighbor_report_tx);\n\tblobmsg_close_table(&b, rrm_table);\n\n\t/* WNM */\n\twnm_table = blobmsg_open_table(&b, \"wnm\");\n\tblobmsg_add_u64(&b, \"bss_transition_query_rx\", hapd->openwrt_stats.wnm.bss_transition_query_rx);\n\tblobmsg_add_u64(&b, \"bss_transition_request_tx\", hapd->openwrt_stats.wnm.bss_transition_request_tx);\n\tblobmsg_add_u64(&b, \"bss_transition_response_rx\", hapd->openwrt_stats.wnm.bss_transition_response_rx);\n\tblobmsg_close_table(&b, wnm_table);\n\n\t/* Airtime */\n\tairtime_table = blobmsg_open_table(&b, \"airtime\");\n\tblobmsg_add_u64(&b, \"time\", hapd->iface->last_channel_time);\n\tblobmsg_add_u64(&b, \"time_busy\", hapd->iface->last_channel_time_busy);\n\tblobmsg_add_u16(&b, \"utilization\", hapd->iface->channel_utilization);\n\tblobmsg_close_table(&b, airtime_table);\n\n\t/* DFS */\n\tdfs_table = blobmsg_open_table(&b, \"dfs\");\n\tblobmsg_add_u32(&b, \"cac_seconds\", hapd->iface->dfs_cac_ms / 1000);\n\tblobmsg_add_u8(&b, \"cac_active\", !!(hapd->iface->cac_started));\n\tos_reltime_age(&hapd->iface->dfs_cac_start, &now);\n\tblobmsg_add_u32(&b, \"cac_seconds_left\",\n\t\t\thapd->iface->cac_started ? hapd->iface->dfs_cac_ms / 1000 - now.sec : 0);\n\tblobmsg_close_table(&b, dfs_table);\n\n\tubus_send_reply(ctx, req, b.head);\n\n\treturn 0;\n}\n\nenum {\n\tNOTIFY_RESPONSE,\n\t__NOTIFY_MAX\n};\n\nstatic const struct blobmsg_policy notify_policy[__NOTIFY_MAX] = {\n\t[NOTIFY_RESPONSE] = { \"notify_response\", BLOBMSG_TYPE_INT32 },\n};\n\nstatic int\nhostapd_notify_response(struct ubus_context *ctx, struct ubus_object *obj,\n\t\t\tstruct ubus_request_data *req, const char *method,\n\t\t\tstruct blob_attr *msg)\n{\n\tstruct blob_attr *tb[__NOTIFY_MAX];\n\tstruct hostapd_data *hapd = get_hapd_from_object(obj);\n\tstruct wpabuf *elems;\n\tconst char *pos;\n\tsize_t len;\n\n\tblobmsg_parse(notify_policy, __NOTIFY_MAX, tb,\n\t\t      blob_data(msg), blob_len(msg));\n\n\tif (!tb[NOTIFY_RESPONSE])\n\t\treturn UBUS_STATUS_INVALID_ARGUMENT;\n\n\thapd->ubus.notify_response = blobmsg_get_u32(tb[NOTIFY_RESPONSE]);\n\n\treturn UBUS_STATUS_OK;\n}\n\nenum {\n\tDEL_CLIENT_ADDR,\n\tDEL_CLIENT_REASON,\n\tDEL_CLIENT_DEAUTH,\n\tDEL_CLIENT_BAN_TIME,\n\t__DEL_CLIENT_MAX\n};\n\nstatic const struct blobmsg_policy del_policy[__DEL_CLIENT_MAX] = {\n\t[DEL_CLIENT_ADDR] = { \"addr\", BLOBMSG_TYPE_STRING },\n\t[DEL_CLIENT_REASON] = { \"reason\", BLOBMSG_TYPE_INT32 },\n\t[DEL_CLIENT_DEAUTH] = { \"deauth\", BLOBMSG_TYPE_INT8 },\n\t[DEL_CLIENT_BAN_TIME] = { \"ban_time\", BLOBMSG_TYPE_INT32 },\n};\n\nstatic int\nhostapd_bss_del_client(struct ubus_context *ctx, struct ubus_object *obj,\n\t\t\tstruct ubus_request_data *req, const char *method,\n\t\t\tstruct blob_attr *msg)\n{\n\tstruct blob_attr *tb[__DEL_CLIENT_MAX];\n\tstruct hostapd_data *hapd = container_of(obj, struct hostapd_data, ubus.obj);\n\tstruct sta_info *sta;\n\tbool deauth = false;\n\tint reason;\n\tu8 addr[ETH_ALEN];\n\n\tblobmsg_parse(del_policy, __DEL_CLIENT_MAX, tb, blob_data(msg), blob_len(msg));\n\n\tif (!tb[DEL_CLIENT_ADDR])\n\t\treturn UBUS_STATUS_INVALID_ARGUMENT;\n\n\tif (hwaddr_aton(blobmsg_data(tb[DEL_CLIENT_ADDR]), addr))\n\t\treturn UBUS_STATUS_INVALID_ARGUMENT;\n\n\tif (tb[DEL_CLIENT_REASON])\n\t\treason = blobmsg_get_u32(tb[DEL_CLIENT_REASON]);\n\n\tif (tb[DEL_CLIENT_DEAUTH])\n\t\tdeauth = blobmsg_get_bool(tb[DEL_CLIENT_DEAUTH]);\n\n\tsta = ap_get_sta(hapd, addr);\n\tif (sta) {\n\t\tif (deauth) {\n\t\t\thostapd_drv_sta_deauth(hapd, addr, reason);\n\t\t\tap_sta_deauthenticate(hapd, sta, reason);\n\t\t} else {\n\t\t\thostapd_drv_sta_disassoc(hapd, addr, reason);\n\t\t\tap_sta_disassociate(hapd, sta, reason);\n\t\t}\n\t}\n\n\tif (tb[DEL_CLIENT_BAN_TIME])\n\t\thostapd_bss_ban_client(hapd, addr, blobmsg_get_u32(tb[DEL_CLIENT_BAN_TIME]));\n\n\treturn 0;\n}\n\nstatic void\nblobmsg_add_macaddr(struct blob_buf *buf, const char *name, const u8 *addr)\n{\n\tchar *s;\n\n\ts = blobmsg_alloc_string_buffer(buf, name, 20);\n\tsprintf(s, MACSTR, MAC2STR(addr));\n\tblobmsg_add_string_buffer(buf);\n}\n\nstatic int\nhostapd_bss_list_bans(struct ubus_context *ctx, struct ubus_object *obj,\n\t\t      struct ubus_request_data *req, const char *method,\n\t\t      struct blob_attr *msg)\n{\n\tstruct hostapd_data *hapd = container_of(obj, struct hostapd_data, ubus.obj);\n\tstruct ubus_banned_client *ban;\n\tvoid *c;\n\n\tblob_buf_init(&b, 0);\n\tc = blobmsg_open_array(&b, \"clients\");\n\tavl_for_each_element(&hapd->ubus.banned, ban, avl)\n\t\tblobmsg_add_macaddr(&b, NULL, ban->addr);\n\tblobmsg_close_array(&b, c);\n\tubus_send_reply(ctx, req, b.head);\n\n\treturn 0;\n}\n\n#ifdef CONFIG_WPS\nstatic int\nhostapd_bss_wps_start(struct ubus_context *ctx, struct ubus_object *obj,\n\t\t\tstruct ubus_request_data *req, const char *method,\n\t\t\tstruct blob_attr *msg)\n{\n\tint rc;\n\tstruct hostapd_data *hapd = container_of(obj, struct hostapd_data, ubus.obj);\n\n\trc = hostapd_wps_button_pushed(hapd, NULL);\n\n\tif (rc != 0)\n\t\treturn UBUS_STATUS_NOT_SUPPORTED;\n\n\treturn 0;\n}\n\n\nstatic const char * pbc_status_enum_str(enum pbc_status status)\n{\n\tswitch (status) {\n\tcase WPS_PBC_STATUS_DISABLE:\n\t\treturn \"Disabled\";\n\tcase WPS_PBC_STATUS_ACTIVE:\n\t\treturn \"Active\";\n\tcase WPS_PBC_STATUS_TIMEOUT:\n\t\treturn \"Timed-out\";\n\tcase WPS_PBC_STATUS_OVERLAP:\n\t\treturn \"Overlap\";\n\tdefault:\n\t\treturn \"Unknown\";\n\t}\n}\n\nstatic int\nhostapd_bss_wps_status(struct ubus_context *ctx, struct ubus_object *obj,\n\t\t\tstruct ubus_request_data *req, const char *method,\n\t\t\tstruct blob_attr *msg)\n{\n\tint rc;\n\tstruct hostapd_data *hapd = container_of(obj, struct hostapd_data, ubus.obj);\n\n\tblob_buf_init(&b, 0);\n\n\tblobmsg_add_string(&b, \"pbc_status\", pbc_status_enum_str(hapd->wps_stats.pbc_status));\n\tblobmsg_add_string(&b, \"last_wps_result\",\n\t\t\t   (hapd->wps_stats.status == WPS_STATUS_SUCCESS ?\n\t\t\t    \"Success\":\n\t\t\t    (hapd->wps_stats.status == WPS_STATUS_FAILURE ?\n\t\t\t     \"Failed\" : \"None\")));\n\n\t/* If status == Failure - Add possible Reasons */\n\tif(hapd->wps_stats.status == WPS_STATUS_FAILURE &&\n\t   hapd->wps_stats.failure_reason > 0)\n\t\tblobmsg_add_string(&b, \"reason\", wps_ei_str(hapd->wps_stats.failure_reason));\n\n\tif (hapd->wps_stats.status)\n\t\tblobmsg_printf(&b, \"peer_address\", MACSTR, MAC2STR(hapd->wps_stats.peer_addr));\n\n\tubus_send_reply(ctx, req, b.head);\n\n\treturn 0;\n}\n\nstatic int\nhostapd_bss_wps_cancel(struct ubus_context *ctx, struct ubus_object *obj,\n\t\t\tstruct ubus_request_data *req, const char *method,\n\t\t\tstruct blob_attr *msg)\n{\n\tint rc;\n\tstruct hostapd_data *hapd = container_of(obj, struct hostapd_data, ubus.obj);\n\n\trc = hostapd_wps_cancel(hapd);\n\n\tif (rc != 0)\n\t\treturn UBUS_STATUS_NOT_SUPPORTED;\n\n\treturn 0;\n}\n#endif /* CONFIG_WPS */\n\nstatic int\nhostapd_bss_update_beacon(struct ubus_context *ctx, struct ubus_object *obj,\n\t\t\tstruct ubus_request_data *req, const char *method,\n\t\t\tstruct blob_attr *msg)\n{\n\tint rc;\n\tstruct hostapd_data *hapd = container_of(obj, struct hostapd_data, ubus.obj);\n\n\trc = ieee802_11_set_beacon(hapd);\n\n\tif (rc != 0)\n\t\treturn UBUS_STATUS_NOT_SUPPORTED;\n\n\treturn 0;\n}\n\nenum {\n\tCONFIG_IFACE,\n\tCONFIG_FILE,\n\t__CONFIG_MAX\n};\n\nstatic const struct blobmsg_policy config_add_policy[__CONFIG_MAX] = {\n\t[CONFIG_IFACE] = { \"iface\", BLOBMSG_TYPE_STRING },\n\t[CONFIG_FILE] = { \"config\", BLOBMSG_TYPE_STRING },\n};\n\nstatic int\nhostapd_config_add(struct ubus_context *ctx, struct ubus_object *obj,\n\t\t   struct ubus_request_data *req, const char *method,\n\t\t   struct blob_attr *msg)\n{\n\tstruct blob_attr *tb[__CONFIG_MAX];\n\tstruct hapd_interfaces *interfaces = get_hapd_interfaces_from_object(obj);\n\tchar buf[128];\n\n\tblobmsg_parse(config_add_policy, __CONFIG_MAX, tb, blob_data(msg), blob_len(msg));\n\n\tif (!tb[CONFIG_FILE] || !tb[CONFIG_IFACE])\n\t\treturn UBUS_STATUS_INVALID_ARGUMENT;\n\n\tsnprintf(buf, sizeof(buf), \"bss_config=%s:%s\",\n\t\tblobmsg_get_string(tb[CONFIG_IFACE]),\n\t\tblobmsg_get_string(tb[CONFIG_FILE]));\n\n\tif (hostapd_add_iface(interfaces, buf))\n\t\treturn UBUS_STATUS_INVALID_ARGUMENT;\n\n\tblob_buf_init(&b, 0);\n\tblobmsg_add_u32(&b, \"pid\", getpid());\n\tubus_send_reply(ctx, req, b.head);\n\n\treturn UBUS_STATUS_OK;\n}\n\nenum {\n\tCONFIG_REM_IFACE,\n\t__CONFIG_REM_MAX\n};\n\nstatic const struct blobmsg_policy config_remove_policy[__CONFIG_REM_MAX] = {\n\t[CONFIG_REM_IFACE] = { \"iface\", BLOBMSG_TYPE_STRING },\n};\n\nstatic int\nhostapd_config_remove(struct ubus_context *ctx, struct ubus_object *obj,\n\t\t      struct ubus_request_data *req, const char *method,\n\t\t      struct blob_attr *msg)\n{\n\tstruct blob_attr *tb[__CONFIG_REM_MAX];\n\tstruct hapd_interfaces *interfaces = get_hapd_interfaces_from_object(obj);\n\tchar buf[128];\n\n\tblobmsg_parse(config_remove_policy, __CONFIG_REM_MAX, tb, blob_data(msg), blob_len(msg));\n\n\tif (!tb[CONFIG_REM_IFACE])\n\t\treturn UBUS_STATUS_INVALID_ARGUMENT;\n\n\tif (hostapd_remove_iface(interfaces, blobmsg_get_string(tb[CONFIG_REM_IFACE])))\n\t\treturn UBUS_STATUS_INVALID_ARGUMENT;\n\n\treturn UBUS_STATUS_OK;\n}\n\nenum {\n\tCSA_FREQ,\n\tCSA_BCN_COUNT,\n\tCSA_CENTER_FREQ1,\n\tCSA_CENTER_FREQ2,\n\tCSA_BANDWIDTH,\n\tCSA_SEC_CHANNEL_OFFSET,\n\tCSA_HT,\n\tCSA_VHT,\n\tCSA_HE,\n\tCSA_BLOCK_TX,\n\tCSA_FORCE,\n\t__CSA_MAX\n};\n\nstatic const struct blobmsg_policy csa_policy[__CSA_MAX] = {\n\t[CSA_FREQ] = { \"freq\", BLOBMSG_TYPE_INT32 },\n\t[CSA_BCN_COUNT] = { \"bcn_count\", BLOBMSG_TYPE_INT32 },\n\t[CSA_CENTER_FREQ1] = { \"center_freq1\", BLOBMSG_TYPE_INT32 },\n\t[CSA_CENTER_FREQ2] = { \"center_freq2\", BLOBMSG_TYPE_INT32 },\n\t[CSA_BANDWIDTH] = { \"bandwidth\", BLOBMSG_TYPE_INT32 },\n\t[CSA_SEC_CHANNEL_OFFSET] = { \"sec_channel_offset\", BLOBMSG_TYPE_INT32 },\n\t[CSA_HT] = { \"ht\", BLOBMSG_TYPE_BOOL },\n\t[CSA_VHT] = { \"vht\", BLOBMSG_TYPE_BOOL },\n\t[CSA_HE] = { \"he\", BLOBMSG_TYPE_BOOL },\n\t[CSA_BLOCK_TX] = { \"block_tx\", BLOBMSG_TYPE_BOOL },\n\t[CSA_FORCE] = { \"force\", BLOBMSG_TYPE_BOOL },\n};\n\n\nstatic void switch_chan_fallback_cb(void *eloop_data, void *user_ctx)\n{\n\tstruct hostapd_iface *iface = eloop_data;\n\tstruct hostapd_freq_params *freq_params = user_ctx;\n\n\thostapd_switch_channel_fallback(iface, freq_params);\n}\n\n#ifdef NEED_AP_MLME\nstatic int\nhostapd_switch_chan(struct ubus_context *ctx, struct ubus_object *obj,\n\t\t    struct ubus_request_data *req, const char *method,\n\t\t    struct blob_attr *msg)\n{\n\tstruct blob_attr *tb[__CSA_MAX];\n\tstruct hostapd_data *hapd = get_hapd_from_object(obj);\n\tstruct hostapd_config *iconf = hapd->iface->conf;\n\tstruct hostapd_freq_params *freq_params;\n\tstruct hostapd_hw_modes *mode = hapd->iface->current_mode;\n\tstruct csa_settings css = {\n\t\t.freq_params = {\n\t\t\t.ht_enabled = iconf->ieee80211n,\n\t\t\t.vht_enabled = iconf->ieee80211ac,\n\t\t\t.he_enabled = iconf->ieee80211ax,\n\t\t\t.sec_channel_offset = iconf->secondary_channel,\n\t\t}\n\t};\n\tu8 chwidth = hostapd_get_oper_chwidth(iconf);\n\tu8 seg0 = 0, seg1 = 0;\n\tint ret = UBUS_STATUS_OK;\n\tint i;\n\n\tblobmsg_parse(csa_policy, __CSA_MAX, tb, blob_data(msg), blob_len(msg));\n\n\tif (!tb[CSA_FREQ])\n\t\treturn UBUS_STATUS_INVALID_ARGUMENT;\n\n\tswitch (iconf->vht_oper_chwidth) {\n\tcase CHANWIDTH_USE_HT:\n\t\tif (iconf->secondary_channel)\n\t\t\tcss.freq_params.bandwidth = 40;\n\t\telse\n\t\t\tcss.freq_params.bandwidth = 20;\n\t\tbreak;\n\tcase CHANWIDTH_160MHZ:\n\t\tcss.freq_params.bandwidth = 160;\n\t\tbreak;\n\tdefault:\n\t\tcss.freq_params.bandwidth = 80;\n\t\tbreak;\n\t}\n\n\tcss.freq_params.freq = blobmsg_get_u32(tb[CSA_FREQ]);\n\n#define SET_CSA_SETTING(name, field, type) \\\n\tdo { \\\n\t\tif (tb[name]) \\\n\t\t\tcss.field = blobmsg_get_ ## type(tb[name]); \\\n\t} while(0)\n\n\tSET_CSA_SETTING(CSA_BCN_COUNT, cs_count, u32);\n\tSET_CSA_SETTING(CSA_CENTER_FREQ1, freq_params.center_freq1, u32);\n\tSET_CSA_SETTING(CSA_CENTER_FREQ2, freq_params.center_freq2, u32);\n\tSET_CSA_SETTING(CSA_BANDWIDTH, freq_params.bandwidth, u32);\n\tSET_CSA_SETTING(CSA_SEC_CHANNEL_OFFSET, freq_params.sec_channel_offset, u32);\n\tSET_CSA_SETTING(CSA_HT, freq_params.ht_enabled, bool);\n\tSET_CSA_SETTING(CSA_VHT, freq_params.vht_enabled, bool);\n\tSET_CSA_SETTING(CSA_HE, freq_params.he_enabled, bool);\n\tSET_CSA_SETTING(CSA_BLOCK_TX, block_tx, bool);\n\n\tcss.freq_params.channel = hostapd_hw_get_channel(hapd, css.freq_params.freq);\n\tif (!css.freq_params.channel)\n\t\treturn UBUS_STATUS_NOT_SUPPORTED;\n\n\tswitch (css.freq_params.bandwidth) {\n\tcase 160:\n\t\tchwidth = CHANWIDTH_160MHZ;\n\t\tbreak;\n\tcase 80:\n\t\tchwidth = css.freq_params.center_freq2 ? CHANWIDTH_80P80MHZ : CHANWIDTH_80MHZ;\n\t\tbreak;\n\tdefault:\n\t\tchwidth = CHANWIDTH_USE_HT;\n\t\tbreak;\n\t}\n\n\thostapd_set_freq_params(&css.freq_params, iconf->hw_mode,\n\t\t\t\tcss.freq_params.freq,\n\t\t\t\tcss.freq_params.channel, iconf->enable_edmg,\n\t\t\t\ticonf->edmg_channel,\n\t\t\t\tcss.freq_params.ht_enabled,\n\t\t\t\tcss.freq_params.vht_enabled,\n\t\t\t\tcss.freq_params.he_enabled,\n\t\t\t\tcss.freq_params.sec_channel_offset,\n\t\t\t\tchwidth, seg0, seg1,\n\t\t\t\ticonf->vht_capab,\n\t\t\t\tmode ? &mode->he_capab[IEEE80211_MODE_AP] :\n\t\t\t\tNULL);\n\n\tfor (i = 0; i < hapd->iface->num_bss; i++) {\n\t\tstruct hostapd_data *bss = hapd->iface->bss[i];\n\n\t\tif (hostapd_switch_channel(bss, &css) != 0)\n\t\t\tret = UBUS_STATUS_NOT_SUPPORTED;\n\t}\n\n\tif (!ret || !tb[CSA_FORCE] || !blobmsg_get_bool(tb[CSA_FORCE]))\n\t\treturn ret;\n\n\tfreq_params = malloc(sizeof(*freq_params));\n\tmemcpy(freq_params, &css.freq_params, sizeof(*freq_params));\n\teloop_register_timeout(0, 1, switch_chan_fallback_cb,\n\t\t\t       hapd->iface, freq_params);\n\n\treturn 0;\n#undef SET_CSA_SETTING\n}\n#endif\n\nenum {\n\tVENDOR_ELEMENTS,\n\t__VENDOR_ELEMENTS_MAX\n};\n\nstatic const struct blobmsg_policy ve_policy[__VENDOR_ELEMENTS_MAX] = {\n\t/* vendor elements are provided as hex-string */\n\t[VENDOR_ELEMENTS] = { \"vendor_elements\", BLOBMSG_TYPE_STRING },\n};\n\nstatic int\nhostapd_vendor_elements(struct ubus_context *ctx, struct ubus_object *obj,\n\t\t\tstruct ubus_request_data *req, const char *method,\n\t\t\tstruct blob_attr *msg)\n{\n\tstruct blob_attr *tb[__VENDOR_ELEMENTS_MAX];\n\tstruct hostapd_data *hapd = get_hapd_from_object(obj);\n\tstruct hostapd_bss_config *bss = hapd->conf;\n\tstruct wpabuf *elems;\n\tconst char *pos;\n\tsize_t len;\n\n\tblobmsg_parse(ve_policy, __VENDOR_ELEMENTS_MAX, tb,\n\t\t      blob_data(msg), blob_len(msg));\n\n\tif (!tb[VENDOR_ELEMENTS])\n\t\treturn UBUS_STATUS_INVALID_ARGUMENT;\n\n\tpos = blobmsg_data(tb[VENDOR_ELEMENTS]);\n\tlen = os_strlen(pos);\n\tif (len & 0x01)\n\t\t\treturn UBUS_STATUS_INVALID_ARGUMENT;\n\n\tlen /= 2;\n\tif (len == 0) {\n\t\twpabuf_free(bss->vendor_elements);\n\t\tbss->vendor_elements = NULL;\n\t\treturn 0;\n\t}\n\n\telems = wpabuf_alloc(len);\n\tif (elems == NULL)\n\t\treturn 1;\n\n\tif (hexstr2bin(pos, wpabuf_put(elems, len), len)) {\n\t\twpabuf_free(elems);\n\t\treturn UBUS_STATUS_INVALID_ARGUMENT;\n\t}\n\n\twpabuf_free(bss->vendor_elements);\n\tbss->vendor_elements = elems;\n\n\t/* update beacons if vendor elements were set successfully */\n\tif (ieee802_11_update_beacons(hapd->iface) != 0)\n\t\treturn UBUS_STATUS_NOT_SUPPORTED;\n\treturn UBUS_STATUS_OK;\n}\n\nstatic void\nhostapd_rrm_print_nr(struct hostapd_neighbor_entry *nr)\n{\n\tconst u8 *data;\n\tchar *str;\n\tint len;\n\n\tblobmsg_printf(&b, \"\", MACSTR, MAC2STR(nr->bssid));\n\n\tstr = blobmsg_alloc_string_buffer(&b, \"\", nr->ssid.ssid_len + 1);\n\tmemcpy(str, nr->ssid.ssid, nr->ssid.ssid_len);\n\tstr[nr->ssid.ssid_len] = 0;\n\tblobmsg_add_string_buffer(&b);\n\n\tlen = wpabuf_len(nr->nr);\n\tstr = blobmsg_alloc_string_buffer(&b, \"\", 2 * len + 1);\n\twpa_snprintf_hex(str, 2 * len + 1, wpabuf_head_u8(nr->nr), len);\n\tblobmsg_add_string_buffer(&b);\n}\n\nenum {\n\tBSS_MGMT_EN_NEIGHBOR,\n\tBSS_MGMT_EN_BEACON,\n\tBSS_MGMT_EN_LINK_MEASUREMENT,\n#ifdef CONFIG_WNM_AP\n\tBSS_MGMT_EN_BSS_TRANSITION,\n#endif\n\t__BSS_MGMT_EN_MAX\n};\n\nstatic bool\n__hostapd_bss_mgmt_enable_f(struct hostapd_data *hapd, int flag)\n{\n\tstruct hostapd_bss_config *bss = hapd->conf;\n\tuint32_t flags;\n\n\tswitch (flag) {\n\tcase BSS_MGMT_EN_NEIGHBOR:\n\t\tif (bss->radio_measurements[0] &\n\t\t    WLAN_RRM_CAPS_NEIGHBOR_REPORT)\n\t\t\treturn false;\n\n\t\tbss->radio_measurements[0] |=\n\t\t\tWLAN_RRM_CAPS_NEIGHBOR_REPORT;\n\t\thostapd_neighbor_set_own_report(hapd);\n\t\treturn true;\n\tcase BSS_MGMT_EN_BEACON:\n\t\tflags = WLAN_RRM_CAPS_BEACON_REPORT_PASSIVE |\n\t\t\tWLAN_RRM_CAPS_BEACON_REPORT_ACTIVE |\n\t\t\tWLAN_RRM_CAPS_BEACON_REPORT_TABLE;\n\n\t\tif (bss->radio_measurements[0] & flags == flags)\n\t\t\treturn false;\n\n\t\tbss->radio_measurements[0] |= (u8) flags;\n\t\treturn true;\n\tcase BSS_MGMT_EN_LINK_MEASUREMENT:\n\t\tflags = WLAN_RRM_CAPS_LINK_MEASUREMENT;\n\n\t\tif (bss->radio_measurements[0] & flags == flags)\n\t\t\treturn false;\n\n\t\tbss->radio_measurements[0] |= (u8) flags;\n\t\treturn true;\n#ifdef CONFIG_WNM_AP\n\tcase BSS_MGMT_EN_BSS_TRANSITION:\n\t\tif (bss->bss_transition)\n\t\t\treturn false;\n\n\t\tbss->bss_transition = 1;\n\t\treturn true;\n#endif\n\t}\n}\n\nstatic void\n__hostapd_bss_mgmt_enable(struct hostapd_data *hapd, uint32_t flags)\n{\n\tbool update = false;\n\tint i;\n\n\tfor (i = 0; i < __BSS_MGMT_EN_MAX; i++) {\n\t\tif (!(flags & (1 << i)))\n\t\t\tcontinue;\n\n\t\tupdate |= __hostapd_bss_mgmt_enable_f(hapd, i);\n\t}\n\n\tif (update)\n\t\tieee802_11_update_beacons(hapd->iface);\n}\n\n\nstatic const struct blobmsg_policy bss_mgmt_enable_policy[__BSS_MGMT_EN_MAX] = {\n\t[BSS_MGMT_EN_NEIGHBOR] = { \"neighbor_report\", BLOBMSG_TYPE_BOOL },\n\t[BSS_MGMT_EN_BEACON] = { \"beacon_report\", BLOBMSG_TYPE_BOOL },\n\t[BSS_MGMT_EN_LINK_MEASUREMENT] = { \"link_measurement\", BLOBMSG_TYPE_BOOL },\n#ifdef CONFIG_WNM_AP\n\t[BSS_MGMT_EN_BSS_TRANSITION] = { \"bss_transition\", BLOBMSG_TYPE_BOOL },\n#endif\n};\n\nstatic int\nhostapd_bss_mgmt_enable(struct ubus_context *ctx, struct ubus_object *obj,\n\t\t   struct ubus_request_data *req, const char *method,\n\t\t   struct blob_attr *msg)\n\n{\n\tstruct hostapd_data *hapd = get_hapd_from_object(obj);\n\tstruct blob_attr *tb[__BSS_MGMT_EN_MAX];\n\tstruct blob_attr *cur;\n\tuint32_t flags = 0;\n\tint i;\n\tbool neigh = false, beacon = false;\n\n\tblobmsg_parse(bss_mgmt_enable_policy, __BSS_MGMT_EN_MAX, tb, blob_data(msg), blob_len(msg));\n\n\tfor (i = 0; i < ARRAY_SIZE(tb); i++) {\n\t\tif (!tb[i] || !blobmsg_get_bool(tb[i]))\n\t\t\tcontinue;\n\n\t\tflags |= (1 << i);\n\t}\n\n\t__hostapd_bss_mgmt_enable(hapd, flags);\n}\n\n\nstatic void\nhostapd_rrm_nr_enable(struct hostapd_data *hapd)\n{\n\t__hostapd_bss_mgmt_enable(hapd, 1 << BSS_MGMT_EN_NEIGHBOR);\n}\n\nstatic int\nhostapd_rrm_nr_get_own(struct ubus_context *ctx, struct ubus_object *obj,\n\t\t       struct ubus_request_data *req, const char *method,\n\t\t       struct blob_attr *msg)\n{\n\tstruct hostapd_data *hapd = get_hapd_from_object(obj);\n\tstruct hostapd_neighbor_entry *nr;\n\tvoid *c;\n\n\thostapd_rrm_nr_enable(hapd);\n\n\tnr = hostapd_neighbor_get(hapd, hapd->own_addr, NULL);\n\tif (!nr)\n\t\treturn UBUS_STATUS_NOT_FOUND;\n\n\tblob_buf_init(&b, 0);\n\n\tc = blobmsg_open_array(&b, \"value\");\n\thostapd_rrm_print_nr(nr);\n\tblobmsg_close_array(&b, c);\n\n\tubus_send_reply(ctx, req, b.head);\n\n\treturn 0;\n}\n\nstatic int\nhostapd_rrm_nr_list(struct ubus_context *ctx, struct ubus_object *obj,\n\t\t    struct ubus_request_data *req, const char *method,\n\t\t    struct blob_attr *msg)\n{\n\tstruct hostapd_data *hapd = get_hapd_from_object(obj);\n\tstruct hostapd_neighbor_entry *nr;\n\tvoid *c;\n\n\thostapd_rrm_nr_enable(hapd);\n\tblob_buf_init(&b, 0);\n\n\tc = blobmsg_open_array(&b, \"list\");\n\tdl_list_for_each(nr, &hapd->nr_db, struct hostapd_neighbor_entry, list) {\n\t\tvoid *cur;\n\n\t\tif (!memcmp(nr->bssid, hapd->own_addr, ETH_ALEN))\n\t\t\tcontinue;\n\n\t\tcur = blobmsg_open_array(&b, NULL);\n\t\thostapd_rrm_print_nr(nr);\n\t\tblobmsg_close_array(&b, cur);\n\t}\n\tblobmsg_close_array(&b, c);\n\n\tubus_send_reply(ctx, req, b.head);\n\n\treturn 0;\n}\n\nenum {\n\tNR_SET_LIST,\n\t__NR_SET_LIST_MAX\n};\n\nstatic const struct blobmsg_policy nr_set_policy[__NR_SET_LIST_MAX] = {\n\t[NR_SET_LIST] = { \"list\", BLOBMSG_TYPE_ARRAY },\n};\n\n\nstatic void\nhostapd_rrm_nr_clear(struct hostapd_data *hapd)\n{\n\tstruct hostapd_neighbor_entry *nr;\n\nrestart:\n\tdl_list_for_each(nr, &hapd->nr_db, struct hostapd_neighbor_entry, list) {\n\t\tif (!memcmp(nr->bssid, hapd->own_addr, ETH_ALEN))\n\t\t\tcontinue;\n\n\t\thostapd_neighbor_remove(hapd, nr->bssid, &nr->ssid);\n\t\tgoto restart;\n\t}\n}\n\nstatic int\nhostapd_rrm_nr_set(struct ubus_context *ctx, struct ubus_object *obj,\n\t\t   struct ubus_request_data *req, const char *method,\n\t\t   struct blob_attr *msg)\n{\n\tstatic const struct blobmsg_policy nr_e_policy[] = {\n\t\t{ .type = BLOBMSG_TYPE_STRING },\n\t\t{ .type = BLOBMSG_TYPE_STRING },\n\t\t{ .type = BLOBMSG_TYPE_STRING },\n\t};\n\tstruct hostapd_data *hapd = get_hapd_from_object(obj);\n\tstruct blob_attr *tb_l[__NR_SET_LIST_MAX];\n\tstruct blob_attr *tb[ARRAY_SIZE(nr_e_policy)];\n\tstruct blob_attr *cur;\n\tint rem;\n\n\thostapd_rrm_nr_enable(hapd);\n\n\tblobmsg_parse(nr_set_policy, __NR_SET_LIST_MAX, tb_l, blob_data(msg), blob_len(msg));\n\tif (!tb_l[NR_SET_LIST])\n\t\treturn UBUS_STATUS_INVALID_ARGUMENT;\n\n\thostapd_rrm_nr_clear(hapd);\n\tblobmsg_for_each_attr(cur, tb_l[NR_SET_LIST], rem) {\n\t\tstruct wpa_ssid_value ssid;\n\t\tstruct wpabuf *data;\n\t\tu8 bssid[ETH_ALEN];\n\t\tchar *s, *nr_s;\n\n\t\tblobmsg_parse_array(nr_e_policy, ARRAY_SIZE(nr_e_policy), tb, blobmsg_data(cur), blobmsg_data_len(cur));\n\t\tif (!tb[0] || !tb[1] || !tb[2])\n\t\t\tgoto invalid;\n\n\t\t/* Neighbor Report binary */\n\t\tnr_s = blobmsg_get_string(tb[2]);\n\t\tdata = wpabuf_parse_bin(nr_s);\n\t\tif (!data)\n\t\t\tgoto invalid;\n\n\t\t/* BSSID */\n\t\ts = blobmsg_get_string(tb[0]);\n\t\tif (strlen(s) == 0) {\n\t\t\t/* Copy BSSID from neighbor report */\n\t\t\tif (hwaddr_compact_aton(nr_s, bssid))\n\t\t\t\tgoto invalid;\n\t\t} else if (hwaddr_aton(s, bssid)) {\n\t\t\tgoto invalid;\n\t\t}\n\n\t\t/* SSID */\n\t\ts = blobmsg_get_string(tb[1]);\n\t\tif (strlen(s) == 0) {\n\t\t\t/* Copy SSID from hostapd BSS conf */\n\t\t\tmemcpy(&ssid, &hapd->conf->ssid, sizeof(ssid));\n\t\t} else {\n\t\t\tssid.ssid_len = strlen(s);\n\t\t\tif (ssid.ssid_len > sizeof(ssid.ssid))\n\t\t\t\tgoto invalid;\n\n\t\t\tmemcpy(&ssid, s, ssid.ssid_len);\n\t\t}\n\n\t\thostapd_neighbor_set(hapd, bssid, &ssid, data, NULL, NULL, 0, 0);\n\t\twpabuf_free(data);\n\t\tcontinue;\n\ninvalid:\n\t\treturn UBUS_STATUS_INVALID_ARGUMENT;\n\t}\n\n\treturn 0;\n}\n\nenum {\n\tBEACON_REQ_ADDR,\n\tBEACON_REQ_MODE,\n\tBEACON_REQ_OP_CLASS,\n\tBEACON_REQ_CHANNEL,\n\tBEACON_REQ_DURATION,\n\tBEACON_REQ_BSSID,\n\tBEACON_REQ_SSID,\n\t__BEACON_REQ_MAX,\n};\n\nstatic const struct blobmsg_policy beacon_req_policy[__BEACON_REQ_MAX] = {\n\t[BEACON_REQ_ADDR] = { \"addr\", BLOBMSG_TYPE_STRING },\n\t[BEACON_REQ_OP_CLASS] { \"op_class\", BLOBMSG_TYPE_INT32 },\n\t[BEACON_REQ_CHANNEL] { \"channel\", BLOBMSG_TYPE_INT32 },\n\t[BEACON_REQ_DURATION] { \"duration\", BLOBMSG_TYPE_INT32 },\n\t[BEACON_REQ_MODE] { \"mode\", BLOBMSG_TYPE_INT32 },\n\t[BEACON_REQ_BSSID] { \"bssid\", BLOBMSG_TYPE_STRING },\n\t[BEACON_REQ_SSID] { \"ssid\", BLOBMSG_TYPE_STRING },\n};\n\nstatic int\nhostapd_rrm_beacon_req(struct ubus_context *ctx, struct ubus_object *obj,\n\t\t       struct ubus_request_data *ureq, const char *method,\n\t\t       struct blob_attr *msg)\n{\n\tstruct hostapd_data *hapd = container_of(obj, struct hostapd_data, ubus.obj);\n\tstruct blob_attr *tb[__BEACON_REQ_MAX];\n\tstruct blob_attr *cur;\n\tstruct wpabuf *req;\n\tu8 bssid[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };\n\tu8 addr[ETH_ALEN];\n\tint mode, rem, ret;\n\tint buf_len = 13;\n\n\tblobmsg_parse(beacon_req_policy, __BEACON_REQ_MAX, tb, blob_data(msg), blob_len(msg));\n\n\tif (!tb[BEACON_REQ_ADDR] || !tb[BEACON_REQ_MODE] || !tb[BEACON_REQ_DURATION] ||\n\t    !tb[BEACON_REQ_OP_CLASS] || !tb[BEACON_REQ_CHANNEL])\n\t\treturn UBUS_STATUS_INVALID_ARGUMENT;\n\n\tif (tb[BEACON_REQ_SSID])\n\t\tbuf_len += blobmsg_data_len(tb[BEACON_REQ_SSID]) + 2 - 1;\n\n\tmode = blobmsg_get_u32(tb[BEACON_REQ_MODE]);\n\tif (hwaddr_aton(blobmsg_data(tb[BEACON_REQ_ADDR]), addr))\n\t\treturn UBUS_STATUS_INVALID_ARGUMENT;\n\n\tif (tb[BEACON_REQ_BSSID] &&\n\t    hwaddr_aton(blobmsg_data(tb[BEACON_REQ_BSSID]), bssid))\n\t\treturn UBUS_STATUS_INVALID_ARGUMENT;\n\n\treq = wpabuf_alloc(buf_len);\n\tif (!req)\n\t\treturn UBUS_STATUS_UNKNOWN_ERROR;\n\n\t/* 1: regulatory class */\n\twpabuf_put_u8(req, blobmsg_get_u32(tb[BEACON_REQ_OP_CLASS]));\n\n\t/* 2: channel number */\n\twpabuf_put_u8(req, blobmsg_get_u32(tb[BEACON_REQ_CHANNEL]));\n\n\t/* 3-4: randomization interval */\n\twpabuf_put_le16(req, 0);\n\n\t/* 5-6: duration */\n\twpabuf_put_le16(req, blobmsg_get_u32(tb[BEACON_REQ_DURATION]));\n\n\t/* 7: mode */\n\twpabuf_put_u8(req, blobmsg_get_u32(tb[BEACON_REQ_MODE]));\n\n\t/* 8-13: BSSID */\n\twpabuf_put_data(req, bssid, ETH_ALEN);\n\n\tif ((cur = tb[BEACON_REQ_SSID]) != NULL) {\n\t\twpabuf_put_u8(req, WLAN_EID_SSID);\n\t\twpabuf_put_u8(req, blobmsg_data_len(cur) - 1);\n\t\twpabuf_put_data(req, blobmsg_data(cur), blobmsg_data_len(cur) - 1);\n\t}\n\n\tret = hostapd_send_beacon_req(hapd, addr, 0, req);\n\tif (ret < 0)\n\t\treturn -ret;\n\n\treturn 0;\n}\n\nenum {\n\tLM_REQ_ADDR,\n\tLM_REQ_TX_POWER_USED,\n\tLM_REQ_TX_POWER_MAX,\n\t__LM_REQ_MAX,\n};\n\nstatic const struct blobmsg_policy lm_req_policy[__LM_REQ_MAX] = {\n\t[LM_REQ_ADDR] = { \"addr\", BLOBMSG_TYPE_STRING },\n\t[LM_REQ_TX_POWER_USED] = { \"tx-power-used\", BLOBMSG_TYPE_INT32 },\n\t[LM_REQ_TX_POWER_MAX] = { \"tx-power-max\", BLOBMSG_TYPE_INT32 },\n};\n\nstatic int\nhostapd_rrm_lm_req(struct ubus_context *ctx, struct ubus_object *obj,\n\t\t   struct ubus_request_data *ureq, const char *method,\n\t\t   struct blob_attr *msg)\n{\n\tstruct hostapd_data *hapd = container_of(obj, struct hostapd_data, ubus.obj);\n\tstruct blob_attr *tb[__LM_REQ_MAX];\n\tstruct wpabuf *buf;\n\tu8 addr[ETH_ALEN];\n\tint ret;\n\tint8_t txp_used, txp_max;\n\n\ttxp_used = 0;\n\ttxp_max = 0;\n\n\tblobmsg_parse(lm_req_policy, __LM_REQ_MAX, tb, blob_data(msg), blob_len(msg));\n\n\tif (!tb[LM_REQ_ADDR])\n\t\treturn UBUS_STATUS_INVALID_ARGUMENT;\n\n\tif (tb[LM_REQ_TX_POWER_USED])\n\t\ttxp_used = (int8_t) blobmsg_get_u32(tb[LM_REQ_TX_POWER_USED]);\n\n\tif (tb[LM_REQ_TX_POWER_MAX])\n\t\ttxp_max = (int8_t) blobmsg_get_u32(tb[LM_REQ_TX_POWER_MAX]);\n\n\tif (hwaddr_aton(blobmsg_data(tb[LM_REQ_ADDR]), addr))\n\t\treturn UBUS_STATUS_INVALID_ARGUMENT;\n\n\tbuf = wpabuf_alloc(5);\n\tif (!buf)\n\t\treturn UBUS_STATUS_UNKNOWN_ERROR;\n\n\twpabuf_put_u8(buf, WLAN_ACTION_RADIO_MEASUREMENT);\n\twpabuf_put_u8(buf, WLAN_RRM_LINK_MEASUREMENT_REQUEST);\n\twpabuf_put_u8(buf, 1);\n\t/* TX-Power used */\n\twpabuf_put_u8(buf, txp_used);\n\t/* Max TX Power */\n\twpabuf_put_u8(buf, txp_max);\n\n\tret = hostapd_drv_send_action(hapd, hapd->iface->freq, 0, addr,\n\t\t\t\t      wpabuf_head(buf), wpabuf_len(buf));\n\n\twpabuf_free(buf);\n\tif (ret < 0)\n\t\treturn -ret;\n\n\treturn 0;\n}\n\n\nvoid hostapd_ubus_handle_link_measurement(struct hostapd_data *hapd, const u8 *data, size_t len)\n{\n\tconst struct ieee80211_mgmt *mgmt = (const struct ieee80211_mgmt *) data;\n\tconst u8 *pos, *end;\n\tu8 token;\n\n\tend = data + len;\n\ttoken = mgmt->u.action.u.rrm.dialog_token;\n\tpos = mgmt->u.action.u.rrm.variable;\n\n\tif (end - pos < 8)\n\t\treturn;\n\n\tif (!hapd->ubus.obj.has_subscribers)\n\t\treturn;\n\n\tblob_buf_init(&b, 0);\n\tblobmsg_add_macaddr(&b, \"address\", mgmt->sa);\n\tblobmsg_add_u16(&b, \"dialog-token\", token);\n\tblobmsg_add_u16(&b, \"rx-antenna-id\", pos[4]);\n\tblobmsg_add_u16(&b, \"tx-antenna-id\", pos[5]);\n\tblobmsg_add_u16(&b, \"rcpi\", pos[6]);\n\tblobmsg_add_u16(&b, \"rsni\", pos[7]);\n\n\tubus_notify(ctx, &hapd->ubus.obj, \"link-measurement-report\", b.head, -1);\n}\n\n\n#ifdef CONFIG_WNM_AP\n\nstatic int\nhostapd_bss_tr_send(struct hostapd_data *hapd, u8 *addr, bool disassoc_imminent, bool abridged,\n\t\t    u16 disassoc_timer, u8 validity_period, u8 dialog_token,\n\t\t    struct blob_attr *neighbors)\n{\n\tstruct blob_attr *cur;\n\tstruct sta_info *sta;\n\tint nr_len = 0;\n\tint rem;\n\tu8 *nr = NULL;\n\tu8 req_mode = 0;\n\n\tsta = ap_get_sta(hapd, addr);\n\tif (!sta)\n\t\treturn UBUS_STATUS_NOT_FOUND;\n\n\tif (neighbors) {\n\t\tu8 *nr_cur;\n\n\t\tif (blobmsg_check_array(neighbors,\n\t\t\t\t\tBLOBMSG_TYPE_STRING) < 0)\n\t\t\treturn UBUS_STATUS_INVALID_ARGUMENT;\n\n\t\tblobmsg_for_each_attr(cur, neighbors, rem) {\n\t\t\tint len = strlen(blobmsg_get_string(cur));\n\n\t\t\tif (len % 2)\n\t\t\t\treturn UBUS_STATUS_INVALID_ARGUMENT;\n\n\t\t\tnr_len += (len / 2) + 2;\n\t\t}\n\n\t\tif (nr_len) {\n\t\t\tnr = os_zalloc(nr_len);\n\t\t\tif (!nr)\n\t\t\t\treturn UBUS_STATUS_UNKNOWN_ERROR;\n\t\t}\n\n\t\tnr_cur = nr;\n\t\tblobmsg_for_each_attr(cur, neighbors, rem) {\n\t\t\tint len = strlen(blobmsg_get_string(cur)) / 2;\n\n\t\t\t*nr_cur++ = WLAN_EID_NEIGHBOR_REPORT;\n\t\t\t*nr_cur++ = (u8) len;\n\t\t\tif (hexstr2bin(blobmsg_data(cur), nr_cur, len)) {\n\t\t\t\tfree(nr);\n\t\t\t\treturn UBUS_STATUS_INVALID_ARGUMENT;\n\t\t\t}\n\n\t\t\tnr_cur += len;\n\t\t}\n\t}\n\n\tif (nr)\n\t\treq_mode |= WNM_BSS_TM_REQ_PREF_CAND_LIST_INCLUDED;\n\n\tif (abridged)\n\t\treq_mode |= WNM_BSS_TM_REQ_ABRIDGED;\n\n\tif (disassoc_imminent)\n\t\treq_mode |= WNM_BSS_TM_REQ_DISASSOC_IMMINENT;\n\n\tif (wnm_send_bss_tm_req(hapd, sta, req_mode, disassoc_timer, validity_period, NULL,\n\t\t\t\tdialog_token, NULL, nr, nr_len, NULL, 0))\n\t\treturn UBUS_STATUS_UNKNOWN_ERROR;\n\n\treturn 0;\n}\n\nenum {\n\tBSS_TR_ADDR,\n\tBSS_TR_DA_IMMINENT,\n\tBSS_TR_DA_TIMER,\n\tBSS_TR_VALID_PERIOD,\n\tBSS_TR_NEIGHBORS,\n\tBSS_TR_ABRIDGED,\n\tBSS_TR_DIALOG_TOKEN,\n\t__BSS_TR_DISASSOC_MAX\n};\n\nstatic const struct blobmsg_policy bss_tr_policy[__BSS_TR_DISASSOC_MAX] = {\n\t[BSS_TR_ADDR] = { \"addr\", BLOBMSG_TYPE_STRING },\n\t[BSS_TR_DA_IMMINENT] = { \"disassociation_imminent\", BLOBMSG_TYPE_BOOL },\n\t[BSS_TR_DA_TIMER] = { \"disassociation_timer\", BLOBMSG_TYPE_INT32 },\n\t[BSS_TR_VALID_PERIOD] = { \"validity_period\", BLOBMSG_TYPE_INT32 },\n\t[BSS_TR_NEIGHBORS] = { \"neighbors\", BLOBMSG_TYPE_ARRAY },\n\t[BSS_TR_ABRIDGED] = { \"abridged\", BLOBMSG_TYPE_BOOL },\n\t[BSS_TR_DIALOG_TOKEN] = { \"dialog_token\", BLOBMSG_TYPE_INT32 },\n};\n\nstatic int\nhostapd_bss_transition_request(struct ubus_context *ctx, struct ubus_object *obj,\n\t\t\t       struct ubus_request_data *ureq, const char *method,\n\t\t\t       struct blob_attr *msg)\n{\n\tstruct hostapd_data *hapd = container_of(obj, struct hostapd_data, ubus.obj);\n\tstruct blob_attr *tb[__BSS_TR_DISASSOC_MAX];\n\tstruct sta_info *sta;\n\tu32 da_timer = 0;\n\tu32 valid_period = 0;\n\tu8 addr[ETH_ALEN];\n\tu32 dialog_token = 1;\n\tbool abridged;\n\tbool da_imminent;\n\n\tblobmsg_parse(bss_tr_policy, __BSS_TR_DISASSOC_MAX, tb, blob_data(msg), blob_len(msg));\n\n\tif (!tb[BSS_TR_ADDR])\n\t\treturn UBUS_STATUS_INVALID_ARGUMENT;\n\n\tif (hwaddr_aton(blobmsg_data(tb[BSS_TR_ADDR]), addr))\n\t\treturn UBUS_STATUS_INVALID_ARGUMENT;\n\n\tif (tb[BSS_TR_DA_TIMER])\n\t\tda_timer = blobmsg_get_u32(tb[BSS_TR_DA_TIMER]);\n\n\tif (tb[BSS_TR_VALID_PERIOD])\n\t\tvalid_period = blobmsg_get_u32(tb[BSS_TR_VALID_PERIOD]);\n\n\tif (tb[BSS_TR_DIALOG_TOKEN])\n\t\tdialog_token = blobmsg_get_u32(tb[BSS_TR_DIALOG_TOKEN]);\n\n\tda_imminent = !!(tb[BSS_TR_DA_IMMINENT] && blobmsg_get_bool(tb[BSS_TR_DA_IMMINENT]));\n\tabridged = !!(tb[BSS_TR_ABRIDGED] && blobmsg_get_bool(tb[BSS_TR_ABRIDGED]));\n\n\treturn hostapd_bss_tr_send(hapd, addr, da_imminent, abridged, da_timer, valid_period,\n\t\t\t\t   dialog_token, tb[BSS_TR_NEIGHBORS]);\n}\n\nenum {\n\tWNM_DISASSOC_ADDR,\n\tWNM_DISASSOC_DURATION,\n\tWNM_DISASSOC_NEIGHBORS,\n\tWNM_DISASSOC_ABRIDGED,\n\t__WNM_DISASSOC_MAX,\n};\n\nstatic const struct blobmsg_policy wnm_disassoc_policy[__WNM_DISASSOC_MAX] = {\n\t[WNM_DISASSOC_ADDR] = { \"addr\", BLOBMSG_TYPE_STRING },\n\t[WNM_DISASSOC_DURATION] { \"duration\", BLOBMSG_TYPE_INT32 },\n\t[WNM_DISASSOC_NEIGHBORS] { \"neighbors\", BLOBMSG_TYPE_ARRAY },\n\t[WNM_DISASSOC_ABRIDGED] { \"abridged\", BLOBMSG_TYPE_BOOL },\n};\n\nstatic int\nhostapd_wnm_disassoc_imminent(struct ubus_context *ctx, struct ubus_object *obj,\n\t\t\t      struct ubus_request_data *ureq, const char *method,\n\t\t\t      struct blob_attr *msg)\n{\n\tstruct hostapd_data *hapd = container_of(obj, struct hostapd_data, ubus.obj);\n\tstruct blob_attr *tb[__WNM_DISASSOC_MAX];\n\tstruct sta_info *sta;\n\tint duration = 10;\n\tu8 addr[ETH_ALEN];\n\tbool abridged;\n\n\tblobmsg_parse(wnm_disassoc_policy, __WNM_DISASSOC_MAX, tb, blob_data(msg), blob_len(msg));\n\n\tif (!tb[WNM_DISASSOC_ADDR])\n\t\treturn UBUS_STATUS_INVALID_ARGUMENT;\n\n\tif (hwaddr_aton(blobmsg_data(tb[WNM_DISASSOC_ADDR]), addr))\n\t\treturn UBUS_STATUS_INVALID_ARGUMENT;\n\n\tif (tb[WNM_DISASSOC_DURATION])\n\t\tduration = blobmsg_get_u32(tb[WNM_DISASSOC_DURATION]);\n\n\tabridged = !!(tb[WNM_DISASSOC_ABRIDGED] && blobmsg_get_bool(tb[WNM_DISASSOC_ABRIDGED]));\n\n\treturn hostapd_bss_tr_send(hapd, addr, true, abridged, duration, duration,\n\t\t\t\t   1, tb[WNM_DISASSOC_NEIGHBORS]);\n}\n#endif\n\n#ifdef CONFIG_AIRTIME_POLICY\nenum {\n\tUPDATE_AIRTIME_STA,\n\tUPDATE_AIRTIME_WEIGHT,\n\t__UPDATE_AIRTIME_MAX,\n};\n\n\nstatic const struct blobmsg_policy airtime_policy[__UPDATE_AIRTIME_MAX] = {\n\t[UPDATE_AIRTIME_STA] = { \"sta\", BLOBMSG_TYPE_STRING },\n\t[UPDATE_AIRTIME_WEIGHT] = { \"weight\", BLOBMSG_TYPE_INT32 },\n};\n\nstatic int\nhostapd_bss_update_airtime(struct ubus_context *ctx, struct ubus_object *obj,\n\t\t\t   struct ubus_request_data *ureq, const char *method,\n\t\t\t   struct blob_attr *msg)\n{\n\tstruct hostapd_data *hapd = container_of(obj, struct hostapd_data, ubus.obj);\n\tstruct blob_attr *tb[__UPDATE_AIRTIME_MAX];\n\tstruct sta_info *sta = NULL;\n\tu8 addr[ETH_ALEN];\n\tint weight;\n\n\tblobmsg_parse(airtime_policy, __UPDATE_AIRTIME_MAX, tb, blob_data(msg), blob_len(msg));\n\n\tif (!tb[UPDATE_AIRTIME_WEIGHT])\n\t\treturn UBUS_STATUS_INVALID_ARGUMENT;\n\n\tweight = blobmsg_get_u32(tb[UPDATE_AIRTIME_WEIGHT]);\n\n\tif (!tb[UPDATE_AIRTIME_STA]) {\n\t\tif (!weight)\n\t\t\treturn UBUS_STATUS_INVALID_ARGUMENT;\n\n\t\thapd->conf->airtime_weight = weight;\n\t\treturn 0;\n\t}\n\n\tif (hwaddr_aton(blobmsg_data(tb[UPDATE_AIRTIME_STA]), addr))\n\t\treturn UBUS_STATUS_INVALID_ARGUMENT;\n\n\tsta = ap_get_sta(hapd, addr);\n\tif (!sta)\n\t\treturn UBUS_STATUS_NOT_FOUND;\n\n\tsta->dyn_airtime_weight = weight;\n\tairtime_policy_new_sta(hapd, sta);\n\n\treturn 0;\n}\n#endif\n\n\nstatic const struct ubus_method bss_methods[] = {\n\tUBUS_METHOD_NOARG(\"reload\", hostapd_bss_reload),\n\tUBUS_METHOD_NOARG(\"get_clients\", hostapd_bss_get_clients),\n\tUBUS_METHOD_NOARG(\"get_status\", hostapd_bss_get_status),\n\tUBUS_METHOD(\"del_client\", hostapd_bss_del_client, del_policy),\n#ifdef CONFIG_AIRTIME_POLICY\n\tUBUS_METHOD(\"update_airtime\", hostapd_bss_update_airtime, airtime_policy),\n#endif\n\tUBUS_METHOD_NOARG(\"list_bans\", hostapd_bss_list_bans),\n#ifdef CONFIG_WPS\n\tUBUS_METHOD_NOARG(\"wps_start\", hostapd_bss_wps_start),\n\tUBUS_METHOD_NOARG(\"wps_status\", hostapd_bss_wps_status),\n\tUBUS_METHOD_NOARG(\"wps_cancel\", hostapd_bss_wps_cancel),\n#endif\n\tUBUS_METHOD_NOARG(\"update_beacon\", hostapd_bss_update_beacon),\n\tUBUS_METHOD_NOARG(\"get_features\", hostapd_bss_get_features),\n#ifdef NEED_AP_MLME\n\tUBUS_METHOD(\"switch_chan\", hostapd_switch_chan, csa_policy),\n#endif\n\tUBUS_METHOD(\"set_vendor_elements\", hostapd_vendor_elements, ve_policy),\n\tUBUS_METHOD(\"notify_response\", hostapd_notify_response, notify_policy),\n\tUBUS_METHOD(\"bss_mgmt_enable\", hostapd_bss_mgmt_enable, bss_mgmt_enable_policy),\n\tUBUS_METHOD_NOARG(\"rrm_nr_get_own\", hostapd_rrm_nr_get_own),\n\tUBUS_METHOD_NOARG(\"rrm_nr_list\", hostapd_rrm_nr_list),\n\tUBUS_METHOD(\"rrm_nr_set\", hostapd_rrm_nr_set, nr_set_policy),\n\tUBUS_METHOD(\"rrm_beacon_req\", hostapd_rrm_beacon_req, beacon_req_policy),\n\tUBUS_METHOD(\"link_measurement_req\", hostapd_rrm_lm_req, lm_req_policy),\n#ifdef CONFIG_WNM_AP\n\tUBUS_METHOD(\"wnm_disassoc_imminent\", hostapd_wnm_disassoc_imminent, wnm_disassoc_policy),\n\tUBUS_METHOD(\"bss_transition_request\", hostapd_bss_transition_request, bss_tr_policy),\n#endif\n};\n\nstatic struct ubus_object_type bss_object_type =\n\tUBUS_OBJECT_TYPE(\"hostapd_bss\", bss_methods);\n\nstatic int avl_compare_macaddr(const void *k1, const void *k2, void *ptr)\n{\n\treturn memcmp(k1, k2, ETH_ALEN);\n}\n\nvoid hostapd_ubus_add_bss(struct hostapd_data *hapd)\n{\n\tstruct ubus_object *obj = &hapd->ubus.obj;\n\tchar *name;\n\tint ret;\n\n#ifdef CONFIG_MESH\n\tif (hapd->conf->mesh & MESH_ENABLED)\n\t\treturn;\n#endif\n\n\tif (!hostapd_ubus_init())\n\t\treturn;\n\n\tif (asprintf(&name, \"hostapd.%s\", hapd->conf->iface) < 0)\n\t\treturn;\n\n\tavl_init(&hapd->ubus.banned, avl_compare_macaddr, false, NULL);\n\tobj->name = name;\n\tobj->type = &bss_object_type;\n\tobj->methods = bss_object_type.methods;\n\tobj->n_methods = bss_object_type.n_methods;\n\tret = ubus_add_object(ctx, obj);\n\thostapd_ubus_ref_inc();\n\n\thostapd_send_shared_event(&hapd->iface->interfaces->ubus, hapd->conf->iface, \"add\");\n}\n\nvoid hostapd_ubus_free_bss(struct hostapd_data *hapd)\n{\n\tstruct ubus_object *obj = &hapd->ubus.obj;\n\tchar *name = (char *) obj->name;\n\n#ifdef CONFIG_MESH\n\tif (hapd->conf->mesh & MESH_ENABLED)\n\t\treturn;\n#endif\n\n\tif (!ctx)\n\t\treturn;\n\n\thostapd_send_shared_event(&hapd->iface->interfaces->ubus, hapd->conf->iface, \"remove\");\n\n\tif (obj->id) {\n\t\tubus_remove_object(ctx, obj);\n\t\thostapd_ubus_ref_dec();\n\t}\n\n\tfree(name);\n}\n\nstatic void\nhostapd_ubus_vlan_action(struct hostapd_data *hapd, struct hostapd_vlan *vlan,\n\t\t\t const char *action)\n{\n\tstruct vlan_description *desc = &vlan->vlan_desc;\n\tvoid *c;\n\tint i;\n\n\tif (!hapd->ubus.obj.has_subscribers)\n\t\treturn;\n\n\tblob_buf_init(&b, 0);\n\tblobmsg_add_string(&b, \"ifname\", vlan->ifname);\n\tblobmsg_add_string(&b, \"bridge\", vlan->bridge);\n\tblobmsg_add_u32(&b, \"vlan_id\", vlan->vlan_id);\n\n\tif (desc->notempty) {\n\t\tblobmsg_add_u32(&b, \"untagged\", desc->untagged);\n\t\tc = blobmsg_open_array(&b, \"tagged\");\n\t\tfor (i = 0; i < ARRAY_SIZE(desc->tagged) && desc->tagged[i]; i++)\n\t\t\tblobmsg_add_u32(&b, \"\", desc->tagged[i]);\n\t\tblobmsg_close_array(&b, c);\n\t}\n\n\tubus_notify(ctx, &hapd->ubus.obj, action, b.head, -1);\n}\n\nvoid hostapd_ubus_add_vlan(struct hostapd_data *hapd, struct hostapd_vlan *vlan)\n{\n\thostapd_ubus_vlan_action(hapd, vlan, \"vlan_add\");\n}\n\nvoid hostapd_ubus_remove_vlan(struct hostapd_data *hapd, struct hostapd_vlan *vlan)\n{\n\thostapd_ubus_vlan_action(hapd, vlan, \"vlan_remove\");\n}\n\nstatic const struct ubus_method daemon_methods[] = {\n\tUBUS_METHOD(\"config_add\", hostapd_config_add, config_add_policy),\n\tUBUS_METHOD(\"config_remove\", hostapd_config_remove, config_remove_policy),\n};\n\nstatic struct ubus_object_type daemon_object_type =\n\tUBUS_OBJECT_TYPE(\"hostapd\", daemon_methods);\n\nvoid hostapd_ubus_add(struct hapd_interfaces *interfaces)\n{\n\tstruct ubus_object *obj = &interfaces->ubus;\n\tint ret;\n\n\tif (!hostapd_ubus_init())\n\t\treturn;\n\n\tobj->name = strdup(\"hostapd\");\n\n\tobj->type = &daemon_object_type;\n\tobj->methods = daemon_object_type.methods;\n\tobj->n_methods = daemon_object_type.n_methods;\n\tret = ubus_add_object(ctx, obj);\n\thostapd_ubus_ref_inc();\n}\n\nvoid hostapd_ubus_free(struct hapd_interfaces *interfaces)\n{\n\tstruct ubus_object *obj = &interfaces->ubus;\n\tchar *name = (char *) obj->name;\n\n\tif (!ctx)\n\t\treturn;\n\n\tif (obj->id) {\n\t\tubus_remove_object(ctx, obj);\n\t\thostapd_ubus_ref_dec();\n\t}\n\n\tfree(name);\n}\n\nstruct ubus_event_req {\n\tstruct ubus_notify_request nreq;\n\tint resp;\n};\n\nstatic void\nubus_event_cb(struct ubus_notify_request *req, int idx, int ret)\n{\n\tstruct ubus_event_req *ureq = container_of(req, struct ubus_event_req, nreq);\n\n\tureq->resp = ret;\n}\n\nint hostapd_ubus_handle_event(struct hostapd_data *hapd, struct hostapd_ubus_request *req)\n{\n\tstruct ubus_banned_client *ban;\n\tconst char *types[HOSTAPD_UBUS_TYPE_MAX] = {\n\t\t[HOSTAPD_UBUS_PROBE_REQ] = \"probe\",\n\t\t[HOSTAPD_UBUS_AUTH_REQ] = \"auth\",\n\t\t[HOSTAPD_UBUS_ASSOC_REQ] = \"assoc\",\n\t};\n\tconst char *type = \"mgmt\";\n\tstruct ubus_event_req ureq = {};\n\tconst u8 *addr;\n\n\tif (req->mgmt_frame)\n\t\taddr = req->mgmt_frame->sa;\n\telse\n\t\taddr = req->addr;\n\n\tban = avl_find_element(&hapd->ubus.banned, addr, ban, avl);\n\tif (ban)\n\t\treturn WLAN_STATUS_AP_UNABLE_TO_HANDLE_NEW_STA;\n\n\tif (!hapd->ubus.obj.has_subscribers)\n\t\treturn WLAN_STATUS_SUCCESS;\n\n\tif (req->type < ARRAY_SIZE(types))\n\t\ttype = types[req->type];\n\n\tblob_buf_init(&b, 0);\n\tblobmsg_add_macaddr(&b, \"address\", addr);\n\tif (req->mgmt_frame)\n\t\tblobmsg_add_macaddr(&b, \"target\", req->mgmt_frame->da);\n\tif (req->ssi_signal)\n\t\tblobmsg_add_u32(&b, \"signal\", req->ssi_signal);\n\tblobmsg_add_u32(&b, \"freq\", hapd->iface->freq);\n\n\tif (req->elems) {\n\t\tif(req->elems->ht_capabilities)\n\t\t{\n\t\t\tstruct ieee80211_ht_capabilities *ht_capabilities;\n\t\t\tvoid *ht_cap, *ht_cap_mcs_set, *mcs_set;\n\n\n\t\t\tht_capabilities = (struct ieee80211_ht_capabilities*) req->elems->ht_capabilities;\n\t\t\tht_cap = blobmsg_open_table(&b, \"ht_capabilities\");\n\t\t\tblobmsg_add_u16(&b, \"ht_capabilities_info\", ht_capabilities->ht_capabilities_info);\n\t\t\tht_cap_mcs_set = blobmsg_open_table(&b, \"supported_mcs_set\");\n\t\t\tblobmsg_add_u16(&b, \"a_mpdu_params\", ht_capabilities->a_mpdu_params);\n\t\t\tblobmsg_add_u16(&b, \"ht_extended_capabilities\", ht_capabilities->ht_extended_capabilities);\n\t\t\tblobmsg_add_u32(&b, \"tx_bf_capability_info\", ht_capabilities->tx_bf_capability_info);\n\t\t\tblobmsg_add_u16(&b, \"asel_capabilities\", ht_capabilities->asel_capabilities);\n\t\t\tmcs_set = blobmsg_open_array(&b, \"supported_mcs_set\");\n\t\t\tfor (int i = 0; i < 16; i++) {\n\t\t\t\tblobmsg_add_u16(&b, NULL, (u16) ht_capabilities->supported_mcs_set[i]);\n\t\t\t}\n\t\t\tblobmsg_close_array(&b, mcs_set);\n\t\t\tblobmsg_close_table(&b, ht_cap_mcs_set);\n\t\t\tblobmsg_close_table(&b, ht_cap);\n\t\t}\n\t\tif(req->elems->vht_capabilities)\n\t\t{\n\t\t\tstruct ieee80211_vht_capabilities *vht_capabilities;\n\t\t\tvoid *vht_cap, *vht_cap_mcs_set;\n\n\t\t\tvht_capabilities = (struct ieee80211_vht_capabilities*) req->elems->vht_capabilities;\n\t\t\tvht_cap = blobmsg_open_table(&b, \"vht_capabilities\");\n\t\t\tblobmsg_add_u32(&b, \"vht_capabilities_info\", vht_capabilities->vht_capabilities_info);\n\t\t\tvht_cap_mcs_set = blobmsg_open_table(&b, \"vht_supported_mcs_set\");\n\t\t\tblobmsg_add_u16(&b, \"rx_map\", vht_capabilities->vht_supported_mcs_set.rx_map);\n\t\t\tblobmsg_add_u16(&b, \"rx_highest\", vht_capabilities->vht_supported_mcs_set.rx_highest);\n\t\t\tblobmsg_add_u16(&b, \"tx_map\", vht_capabilities->vht_supported_mcs_set.tx_map);\n\t\t\tblobmsg_add_u16(&b, \"tx_highest\", vht_capabilities->vht_supported_mcs_set.tx_highest);\n\t\t\tblobmsg_close_table(&b, vht_cap_mcs_set);\n\t\t\tblobmsg_close_table(&b, vht_cap);\n\t\t}\n\t}\n\n\tif (!hapd->ubus.notify_response) {\n\t\tubus_notify(ctx, &hapd->ubus.obj, type, b.head, -1);\n\t\treturn WLAN_STATUS_SUCCESS;\n\t}\n\n\tif (ubus_notify_async(ctx, &hapd->ubus.obj, type, b.head, &ureq.nreq))\n\t\treturn WLAN_STATUS_SUCCESS;\n\n\tureq.nreq.status_cb = ubus_event_cb;\n\tubus_complete_request(ctx, &ureq.nreq.req, 100);\n\n\tif (ureq.resp)\n\t\treturn ureq.resp;\n\n\treturn WLAN_STATUS_SUCCESS;\n}\n\nvoid hostapd_ubus_notify(struct hostapd_data *hapd, const char *type, const u8 *addr)\n{\n\tif (!hapd->ubus.obj.has_subscribers)\n\t\treturn;\n\n\tif (!addr)\n\t\treturn;\n\n\tblob_buf_init(&b, 0);\n\tblobmsg_add_macaddr(&b, \"address\", addr);\n\n\tubus_notify(ctx, &hapd->ubus.obj, type, b.head, -1);\n}\n\nvoid hostapd_ubus_notify_beacon_report(\n\tstruct hostapd_data *hapd, const u8 *addr, u8 token, u8 rep_mode,\n\tstruct rrm_measurement_beacon_report *rep, size_t len)\n{\n\tif (!hapd->ubus.obj.has_subscribers)\n\t\treturn;\n\n\tif (!addr || !rep)\n\t\treturn;\n\n\tblob_buf_init(&b, 0);\n\tblobmsg_add_macaddr(&b, \"address\", addr);\n\tblobmsg_add_u16(&b, \"op-class\", rep->op_class);\n\tblobmsg_add_u16(&b, \"channel\", rep->channel);\n\tblobmsg_add_u64(&b, \"start-time\", rep->start_time);\n\tblobmsg_add_u16(&b, \"duration\", rep->duration);\n\tblobmsg_add_u16(&b, \"report-info\", rep->report_info);\n\tblobmsg_add_u16(&b, \"rcpi\", rep->rcpi);\n\tblobmsg_add_u16(&b, \"rsni\", rep->rsni);\n\tblobmsg_add_macaddr(&b, \"bssid\", rep->bssid);\n\tblobmsg_add_u16(&b, \"antenna-id\", rep->antenna_id);\n\tblobmsg_add_u16(&b, \"parent-tsf\", rep->parent_tsf);\n\n\tubus_notify(ctx, &hapd->ubus.obj, \"beacon-report\", b.head, -1);\n}\n\nvoid hostapd_ubus_notify_radar_detected(struct hostapd_iface *iface, int frequency,\n\t\t\t\t\tint chan_width, int cf1, int cf2)\n{\n\tstruct hostapd_data *hapd;\n\tint i;\n\n\tblob_buf_init(&b, 0);\n\tblobmsg_add_u16(&b, \"frequency\", frequency);\n\tblobmsg_add_u16(&b, \"width\", chan_width);\n\tblobmsg_add_u16(&b, \"center1\", cf1);\n\tblobmsg_add_u16(&b, \"center2\", cf2);\n\n\tfor (i = 0; i < iface->num_bss; i++) {\n\t\thapd = iface->bss[i];\n\t\tubus_notify(ctx, &hapd->ubus.obj, \"radar-detected\", b.head, -1);\n\t}\n}\n\n#ifdef CONFIG_WNM_AP\nstatic void hostapd_ubus_notify_bss_transition_add_candidate_list(\n\tconst u8 *candidate_list, u16 candidate_list_len)\n{\n\tchar *cl_str;\n\tint i;\n\n\tif (candidate_list_len == 0)\n\t\treturn;\n\n\tcl_str = blobmsg_alloc_string_buffer(&b, \"candidate-list\", candidate_list_len * 2 + 1);\n\tfor (i = 0; i < candidate_list_len; i++)\n\t\tsnprintf(&cl_str[i*2], 3, \"%02X\", candidate_list[i]);\n\tblobmsg_add_string_buffer(&b);\n\n}\n#endif\n\nvoid hostapd_ubus_notify_bss_transition_response(\n\tstruct hostapd_data *hapd, const u8 *addr, u8 dialog_token, u8 status_code,\n\tu8 bss_termination_delay, const u8 *target_bssid,\n\tconst u8 *candidate_list, u16 candidate_list_len)\n{\n#ifdef CONFIG_WNM_AP\n\tu16 i;\n\n\tif (!hapd->ubus.obj.has_subscribers)\n\t\treturn;\n\n\tif (!addr)\n\t\treturn;\n\n\tblob_buf_init(&b, 0);\n\tblobmsg_add_macaddr(&b, \"address\", addr);\n\tblobmsg_add_u8(&b, \"dialog-token\", dialog_token);\n\tblobmsg_add_u8(&b, \"status-code\", status_code);\n\tblobmsg_add_u8(&b, \"bss-termination-delay\", bss_termination_delay);\n\tif (target_bssid)\n\t\tblobmsg_add_macaddr(&b, \"target-bssid\", target_bssid);\n\t\n\thostapd_ubus_notify_bss_transition_add_candidate_list(candidate_list, candidate_list_len);\n\n\tubus_notify(ctx, &hapd->ubus.obj, \"bss-transition-response\", b.head, -1);\n#endif\n}\n\nint hostapd_ubus_notify_bss_transition_query(\n\tstruct hostapd_data *hapd, const u8 *addr, u8 dialog_token, u8 reason,\n\tconst u8 *candidate_list, u16 candidate_list_len)\n{\n#ifdef CONFIG_WNM_AP\n\tstruct ubus_event_req ureq = {};\n\tchar *cl_str;\n\tu16 i;\n\n\tif (!hapd->ubus.obj.has_subscribers)\n\t\treturn 0;\n\n\tif (!addr)\n\t\treturn 0;\n\n\tblob_buf_init(&b, 0);\n\tblobmsg_add_macaddr(&b, \"address\", addr);\n\tblobmsg_add_u8(&b, \"dialog-token\", dialog_token);\n\tblobmsg_add_u8(&b, \"reason\", reason);\n\thostapd_ubus_notify_bss_transition_add_candidate_list(candidate_list, candidate_list_len);\n\n\tif (!hapd->ubus.notify_response) {\n\t\tubus_notify(ctx, &hapd->ubus.obj, \"bss-transition-query\", b.head, -1);\n\t\treturn 0;\n\t}\n\n\tif (ubus_notify_async(ctx, &hapd->ubus.obj, \"bss-transition-query\", b.head, &ureq.nreq))\n\t\treturn 0;\n\n\tureq.nreq.status_cb = ubus_event_cb;\n\tubus_complete_request(ctx, &ureq.nreq.req, 100);\n\n\treturn ureq.resp;\n#endif\n}\n"
  },
  {
    "path": "package/network/services/hostapd/src/src/ap/ubus.h",
    "content": "/*\n * hostapd / ubus support\n * Copyright (c) 2013, Felix Fietkau <nbd@nbd.name>\n *\n * This software may be distributed under the terms of the BSD license.\n * See README for more details.\n */\n#ifndef __HOSTAPD_UBUS_H\n#define __HOSTAPD_UBUS_H\n\nenum hostapd_ubus_event_type {\n\tHOSTAPD_UBUS_PROBE_REQ,\n\tHOSTAPD_UBUS_AUTH_REQ,\n\tHOSTAPD_UBUS_ASSOC_REQ,\n\tHOSTAPD_UBUS_TYPE_MAX\n};\n\nstruct hostapd_ubus_request {\n\tenum hostapd_ubus_event_type type;\n\tconst struct ieee80211_mgmt *mgmt_frame;\n\tconst struct ieee802_11_elems *elems;\n\tint ssi_signal; /* dBm */\n\tconst u8 *addr;\n};\n\nstruct hostapd_iface;\nstruct hostapd_data;\nstruct hapd_interfaces;\nstruct rrm_measurement_beacon_report;\n\n#ifdef UBUS_SUPPORT\n\n#include <libubox/avl.h>\n#include <libubus.h>\n\nstruct hostapd_ubus_bss {\n\tstruct ubus_object obj;\n\tstruct avl_tree banned;\n\tint notify_response;\n};\n\nvoid hostapd_ubus_add_iface(struct hostapd_iface *iface);\nvoid hostapd_ubus_free_iface(struct hostapd_iface *iface);\nvoid hostapd_ubus_add_bss(struct hostapd_data *hapd);\nvoid hostapd_ubus_free_bss(struct hostapd_data *hapd);\nvoid hostapd_ubus_add_vlan(struct hostapd_data *hapd, struct hostapd_vlan *vlan);\nvoid hostapd_ubus_remove_vlan(struct hostapd_data *hapd, struct hostapd_vlan *vlan);\n\nint hostapd_ubus_handle_event(struct hostapd_data *hapd, struct hostapd_ubus_request *req);\nvoid hostapd_ubus_handle_link_measurement(struct hostapd_data *hapd, const u8 *data, size_t len);\nvoid hostapd_ubus_notify(struct hostapd_data *hapd, const char *type, const u8 *mac);\nvoid hostapd_ubus_notify_beacon_report(struct hostapd_data *hapd,\n\t\t\t\t       const u8 *addr, u8 token, u8 rep_mode,\n\t\t\t\t       struct rrm_measurement_beacon_report *rep,\n\t\t\t\t       size_t len);\nvoid hostapd_ubus_notify_radar_detected(struct hostapd_iface *iface, int frequency,\n\t\t\t\t\tint chan_width, int cf1, int cf2);\n\nvoid hostapd_ubus_notify_bss_transition_response(\n\tstruct hostapd_data *hapd, const u8 *addr, u8 dialog_token, u8 status_code,\n\tu8 bss_termination_delay, const u8 *target_bssid,\n\tconst u8 *candidate_list, u16 candidate_list_len);\nvoid hostapd_ubus_add(struct hapd_interfaces *interfaces);\nvoid hostapd_ubus_free(struct hapd_interfaces *interfaces);\nint hostapd_ubus_notify_bss_transition_query(\n\tstruct hostapd_data *hapd, const u8 *addr, u8 dialog_token, u8 reason,\n\tconst u8 *candidate_list, u16 candidate_list_len);\n\n#else\n\nstruct hostapd_ubus_bss {};\n\nstatic inline void hostapd_ubus_add_iface(struct hostapd_iface *iface)\n{\n}\n\nstatic inline void hostapd_ubus_free_iface(struct hostapd_iface *iface)\n{\n}\n\nstatic inline void hostapd_ubus_add_bss(struct hostapd_data *hapd)\n{\n}\n\nstatic inline void hostapd_ubus_free_bss(struct hostapd_data *hapd)\n{\n}\n\nstatic inline void hostapd_ubus_add_vlan(struct hostapd_data *hapd, struct hostapd_vlan *vlan)\n{\n}\n\nstatic inline void hostapd_ubus_remove_vlan(struct hostapd_data *hapd, struct hostapd_vlan *vlan)\n{\n}\n\nstatic inline int hostapd_ubus_handle_event(struct hostapd_data *hapd, struct hostapd_ubus_request *req)\n{\n\treturn 0;\n}\n\nstatic inline void hostapd_ubus_handle_link_measurement(struct hostapd_data *hapd, const u8 *data, size_t len)\n{\n}\n\nstatic inline void hostapd_ubus_notify(struct hostapd_data *hapd, const char *type, const u8 *mac)\n{\n}\n\nstatic inline void hostapd_ubus_notify_beacon_report(struct hostapd_data *hapd,\n\t\t\t\t\t\t     const u8 *addr, u8 token,\n\t\t\t\t\t\t     u8 rep_mode,\n\t\t\t\t\t\t     struct rrm_measurement_beacon_report *rep,\n\t\t\t\t\t\t     size_t len)\n{\n}\nstatic inline void hostapd_ubus_notify_radar_detected(struct hostapd_iface *iface, int frequency,\n\t\t\t\t\t\t      int chan_width, int cf1, int cf2)\n{\n}\n\nstatic inline void hostapd_ubus_notify_bss_transition_response(\n\tstruct hostapd_data *hapd, const u8 *addr, u8 dialog_token, u8 status_code,\n\tu8 bss_termination_delay, const u8 *target_bssid,\n\tconst u8 *candidate_list, u16 candidate_list_len)\n{\n}\n\nstatic inline void hostapd_ubus_add(struct hapd_interfaces *interfaces)\n{\n}\n\nstatic inline void hostapd_ubus_free(struct hapd_interfaces *interfaces)\n{\n}\n\nstatic inline int hostapd_ubus_notify_bss_transition_query(\n\tstruct hostapd_data *hapd, const u8 *addr, u8 dialog_token, u8 reason,\n\tconst u8 *candidate_list, u16 candidate_list_len)\n{\n\treturn 0;\n}\n#endif\n\n#endif\n"
  },
  {
    "path": "package/network/services/hostapd/src/src/utils/build_features.h",
    "content": "#ifndef BUILD_FEATURES_H\n#define BUILD_FEATURES_H\n\nstatic inline int has_feature(const char *feat)\n{\n#if defined(IEEE8021X_EAPOL) || (defined(HOSTAPD) && !defined(CONFIG_NO_RADIUS))\n\tif (!strcmp(feat, \"eap\"))\n\t\treturn 1;\n#endif\n#ifdef CONFIG_IEEE80211N\n\tif (!strcmp(feat, \"11n\"))\n\t\treturn 1;\n#endif\n#ifdef CONFIG_IEEE80211AC\n\tif (!strcmp(feat, \"11ac\"))\n\t\treturn 1;\n#endif\n#ifdef CONFIG_IEEE80211AX\n\tif (!strcmp(feat, \"11ax\"))\n\t\treturn 1;\n#endif\n#ifdef CONFIG_IEEE80211R\n\tif (!strcmp(feat, \"11r\"))\n\t\treturn 1;\n#endif\n#ifdef CONFIG_ACS\n\tif (!strcmp(feat, \"acs\"))\n\t\treturn 1;\n#endif\n#ifdef CONFIG_SAE\n\tif (!strcmp(feat, \"sae\"))\n\t\treturn 1;\n#endif\n#ifdef CONFIG_OWE\n\tif (!strcmp(feat, \"owe\"))\n\t\treturn 1;\n#endif\n#ifdef CONFIG_SUITEB192\n\tif (!strcmp(feat, \"suiteb192\"))\n\t\treturn 1;\n#endif\n#ifdef CONFIG_WEP\n\tif (!strcmp(feat, \"wep\"))\n\t\treturn 1;\n#endif\n#ifdef CONFIG_HS20\n\tif (!strcmp(feat, \"hs20\"))\n\t\treturn 1;\n#endif\n#ifdef CONFIG_WPS\n\tif (!strcmp(feat, \"wps\"))\n\t\treturn 1;\n#endif\n#ifdef CONFIG_FILS\n\tif (!strcmp(feat, \"fils\"))\n\t\treturn 1;\n#endif\n\treturn 0;\n}\n\n#endif /* BUILD_FEATURES_H */\n"
  },
  {
    "path": "package/network/services/hostapd/src/wpa_supplicant/ubus.c",
    "content": "/*\n * wpa_supplicant / ubus support\n * Copyright (c) 2018, Daniel Golle <daniel@makrotopia.org>\n * Copyright (c) 2013, Felix Fietkau <nbd@nbd.name>\n *\n * This software may be distributed under the terms of the BSD license.\n * See README for more details.\n */\n\n#include \"utils/includes.h\"\n#include \"utils/common.h\"\n#include \"utils/eloop.h\"\n#include \"utils/wpabuf.h\"\n#include \"common/ieee802_11_defs.h\"\n#include \"wpa_supplicant_i.h\"\n#include \"wps_supplicant.h\"\n#include \"ubus.h\"\n\nstatic struct ubus_context *ctx;\nstatic struct blob_buf b;\nstatic int ctx_ref;\n\nstatic inline struct wpa_global *get_wpa_global_from_object(struct ubus_object *obj)\n{\n\treturn container_of(obj, struct wpa_global, ubus_global);\n}\n\nstatic inline struct wpa_supplicant *get_wpas_from_object(struct ubus_object *obj)\n{\n\treturn container_of(obj, struct wpa_supplicant, ubus.obj);\n}\n\nstatic void ubus_receive(int sock, void *eloop_ctx, void *sock_ctx)\n{\n\tstruct ubus_context *ctx = eloop_ctx;\n\tubus_handle_event(ctx);\n}\n\nstatic void ubus_reconnect_timeout(void *eloop_data, void *user_ctx)\n{\n\tif (ubus_reconnect(ctx, NULL)) {\n\t\teloop_register_timeout(1, 0, ubus_reconnect_timeout, ctx, NULL);\n\t\treturn;\n\t}\n\n\teloop_register_read_sock(ctx->sock.fd, ubus_receive, ctx, NULL);\n}\n\nstatic void wpas_ubus_connection_lost(struct ubus_context *ctx)\n{\n\teloop_unregister_read_sock(ctx->sock.fd);\n\teloop_register_timeout(1, 0, ubus_reconnect_timeout, ctx, NULL);\n}\n\nstatic bool wpas_ubus_init(void)\n{\n\tif (ctx)\n\t\treturn true;\n\n\tctx = ubus_connect(NULL);\n\tif (!ctx)\n\t\treturn false;\n\n\tctx->connection_lost = wpas_ubus_connection_lost;\n\teloop_register_read_sock(ctx->sock.fd, ubus_receive, ctx, NULL);\n\treturn true;\n}\n\nstatic void wpas_ubus_ref_inc(void)\n{\n\tctx_ref++;\n}\n\nstatic void wpas_ubus_ref_dec(void)\n{\n\tctx_ref--;\n\tif (!ctx)\n\t\treturn;\n\n\tif (ctx_ref)\n\t\treturn;\n\n\teloop_unregister_read_sock(ctx->sock.fd);\n\tubus_free(ctx);\n\tctx = NULL;\n}\n\nstatic int\nwpas_bss_get_features(struct ubus_context *ctx, struct ubus_object *obj,\n\t\t\tstruct ubus_request_data *req, const char *method,\n\t\t\tstruct blob_attr *msg)\n{\n\tstruct wpa_supplicant *wpa_s = get_wpas_from_object(obj);\n\n\tblob_buf_init(&b, 0);\n\tblobmsg_add_u8(&b, \"ht_supported\", ht_supported(wpa_s->hw.modes));\n\tblobmsg_add_u8(&b, \"vht_supported\", vht_supported(wpa_s->hw.modes));\n\tubus_send_reply(ctx, req, b.head);\n\n\treturn 0;\n}\n\nstatic int\nwpas_bss_reload(struct ubus_context *ctx, struct ubus_object *obj,\n\t\tstruct ubus_request_data *req, const char *method,\n\t\tstruct blob_attr *msg)\n{\n\tstruct wpa_supplicant *wpa_s = get_wpas_from_object(obj);\n\n\tif (wpa_supplicant_reload_configuration(wpa_s))\n\t\treturn UBUS_STATUS_UNKNOWN_ERROR;\n\telse\n\t\treturn 0;\n}\n\n#ifdef CONFIG_WPS\nenum {\n\tWPS_START_MULTI_AP,\n\t__WPS_START_MAX\n};\n\nstatic const struct blobmsg_policy wps_start_policy[] = {\n\t[WPS_START_MULTI_AP] = { \"multi_ap\", BLOBMSG_TYPE_BOOL },\n};\n\nstatic int\nwpas_bss_wps_start(struct ubus_context *ctx, struct ubus_object *obj,\n\t\t\tstruct ubus_request_data *req, const char *method,\n\t\t\tstruct blob_attr *msg)\n{\n\tint rc;\n\tstruct wpa_supplicant *wpa_s = get_wpas_from_object(obj);\n\tstruct blob_attr *tb[__WPS_START_MAX], *cur;\n\tint multi_ap = 0;\n\n\tblobmsg_parse(wps_start_policy, __WPS_START_MAX, tb, blobmsg_data(msg), blobmsg_data_len(msg));\n\n\tif (tb[WPS_START_MULTI_AP])\n\t\tmulti_ap = blobmsg_get_bool(tb[WPS_START_MULTI_AP]);\n\n\trc = wpas_wps_start_pbc(wpa_s, NULL, 0, multi_ap);\n\n\tif (rc != 0)\n\t\treturn UBUS_STATUS_NOT_SUPPORTED;\n\n\treturn 0;\n}\n\nstatic int\nwpas_bss_wps_cancel(struct ubus_context *ctx, struct ubus_object *obj,\n\t\t\tstruct ubus_request_data *req, const char *method,\n\t\t\tstruct blob_attr *msg)\n{\n\tint rc;\n\tstruct wpa_supplicant *wpa_s = get_wpas_from_object(obj);\n\n\trc = wpas_wps_cancel(wpa_s);\n\n\tif (rc != 0)\n\t\treturn UBUS_STATUS_NOT_SUPPORTED;\n\n\treturn 0;\n}\n#endif\n\nstatic const struct ubus_method bss_methods[] = {\n\tUBUS_METHOD_NOARG(\"reload\", wpas_bss_reload),\n\tUBUS_METHOD_NOARG(\"get_features\", wpas_bss_get_features),\n#ifdef CONFIG_WPS\n\tUBUS_METHOD_NOARG(\"wps_start\", wpas_bss_wps_start),\n\tUBUS_METHOD_NOARG(\"wps_cancel\", wpas_bss_wps_cancel),\n#endif\n};\n\nstatic struct ubus_object_type bss_object_type =\n\tUBUS_OBJECT_TYPE(\"wpas_bss\", bss_methods);\n\nvoid wpas_ubus_add_bss(struct wpa_supplicant *wpa_s)\n{\n\tstruct ubus_object *obj = &wpa_s->ubus.obj;\n\tchar *name;\n\tint ret;\n\n\tif (!wpas_ubus_init())\n\t\treturn;\n\n\tif (asprintf(&name, \"wpa_supplicant.%s\", wpa_s->ifname) < 0)\n\t\treturn;\n\n\tobj->name = name;\n\tobj->type = &bss_object_type;\n\tobj->methods = bss_object_type.methods;\n\tobj->n_methods = bss_object_type.n_methods;\n\tret = ubus_add_object(ctx, obj);\n\twpas_ubus_ref_inc();\n}\n\nvoid wpas_ubus_free_bss(struct wpa_supplicant *wpa_s)\n{\n\tstruct ubus_object *obj = &wpa_s->ubus.obj;\n\tchar *name = (char *) obj->name;\n\n\tif (!ctx)\n\t\treturn;\n\n\tif (obj->id) {\n\t\tubus_remove_object(ctx, obj);\n\t\twpas_ubus_ref_dec();\n\t}\n\n\tfree(name);\n}\n\nenum {\n\tWPAS_CONFIG_DRIVER,\n\tWPAS_CONFIG_IFACE,\n\tWPAS_CONFIG_BRIDGE,\n\tWPAS_CONFIG_HOSTAPD_CTRL,\n\tWPAS_CONFIG_CTRL,\n\tWPAS_CONFIG_FILE,\n\t__WPAS_CONFIG_MAX\n};\n\nstatic const struct blobmsg_policy wpas_config_add_policy[__WPAS_CONFIG_MAX] = {\n\t[WPAS_CONFIG_DRIVER] = { \"driver\", BLOBMSG_TYPE_STRING },\n\t[WPAS_CONFIG_IFACE] = { \"iface\", BLOBMSG_TYPE_STRING },\n\t[WPAS_CONFIG_BRIDGE] = { \"bridge\", BLOBMSG_TYPE_STRING },\n\t[WPAS_CONFIG_HOSTAPD_CTRL] = { \"hostapd_ctrl\", BLOBMSG_TYPE_STRING },\n\t[WPAS_CONFIG_CTRL] = { \"ctrl\", BLOBMSG_TYPE_STRING },\n\t[WPAS_CONFIG_FILE] = { \"config\", BLOBMSG_TYPE_STRING },\n};\n\nstatic int\nwpas_config_add(struct ubus_context *ctx, struct ubus_object *obj,\n\t\tstruct ubus_request_data *req, const char *method,\n\t\tstruct blob_attr *msg)\n{\n\tstruct blob_attr *tb[__WPAS_CONFIG_MAX];\n\tstruct wpa_global *global = get_wpa_global_from_object(obj);\n\tstruct wpa_interface *iface;\n\n\tblobmsg_parse(wpas_config_add_policy, __WPAS_CONFIG_MAX, tb, blob_data(msg), blob_len(msg));\n\n\tif (!tb[WPAS_CONFIG_FILE] || !tb[WPAS_CONFIG_IFACE] || !tb[WPAS_CONFIG_DRIVER])\n\t\treturn UBUS_STATUS_INVALID_ARGUMENT;\n\n\tiface = os_zalloc(sizeof(struct wpa_interface));\n\tif (iface == NULL)\n\t\treturn UBUS_STATUS_UNKNOWN_ERROR;\n\n\tiface->driver = blobmsg_get_string(tb[WPAS_CONFIG_DRIVER]);\n\tiface->ifname = blobmsg_get_string(tb[WPAS_CONFIG_IFACE]);\n\tiface->confname = blobmsg_get_string(tb[WPAS_CONFIG_FILE]);\n\n\tif (tb[WPAS_CONFIG_BRIDGE])\n\t\tiface->bridge_ifname = blobmsg_get_string(tb[WPAS_CONFIG_BRIDGE]);\n\n\tif (tb[WPAS_CONFIG_CTRL])\n\t\tiface->ctrl_interface = blobmsg_get_string(tb[WPAS_CONFIG_CTRL]);\n\n\tif (tb[WPAS_CONFIG_HOSTAPD_CTRL])\n\t\tiface->hostapd_ctrl = blobmsg_get_string(tb[WPAS_CONFIG_HOSTAPD_CTRL]);\n\n\tif (!wpa_supplicant_add_iface(global, iface, NULL))\n\t\treturn UBUS_STATUS_INVALID_ARGUMENT;\n\n\tblob_buf_init(&b, 0);\n\tblobmsg_add_u32(&b, \"pid\", getpid());\n\tubus_send_reply(ctx, req, b.head);\n\n\treturn UBUS_STATUS_OK;\n}\n\nenum {\n\tWPAS_CONFIG_REM_IFACE,\n\t__WPAS_CONFIG_REM_MAX\n};\n\nstatic const struct blobmsg_policy wpas_config_remove_policy[__WPAS_CONFIG_REM_MAX] = {\n\t[WPAS_CONFIG_REM_IFACE] = { \"iface\", BLOBMSG_TYPE_STRING },\n};\n\nstatic int\nwpas_config_remove(struct ubus_context *ctx, struct ubus_object *obj,\n\t\t   struct ubus_request_data *req, const char *method,\n\t\t   struct blob_attr *msg)\n{\n\tstruct blob_attr *tb[__WPAS_CONFIG_REM_MAX];\n\tstruct wpa_global *global = get_wpa_global_from_object(obj);\n\tstruct wpa_supplicant *wpa_s = NULL;\n\tunsigned int found = 0;\n\n\tblobmsg_parse(wpas_config_remove_policy, __WPAS_CONFIG_REM_MAX, tb, blob_data(msg), blob_len(msg));\n\n\tif (!tb[WPAS_CONFIG_REM_IFACE])\n\t\treturn UBUS_STATUS_INVALID_ARGUMENT;\n\n\t/* find wpa_s object for to-be-removed interface */\n\tfor (wpa_s = global->ifaces; wpa_s; wpa_s = wpa_s->next) {\n\t\tif (!strncmp(wpa_s->ifname,\n\t\t\t     blobmsg_get_string(tb[WPAS_CONFIG_REM_IFACE]),\n\t\t\t     sizeof(wpa_s->ifname)))\n\t\t{\n\t\t\tfound = 1;\n\t\t\tbreak;\n\t\t}\n\t}\n\n\tif (!found)\n\t\treturn UBUS_STATUS_INVALID_ARGUMENT;\n\n\tif (wpa_supplicant_remove_iface(global, wpa_s, 0))\n\t\treturn UBUS_STATUS_INVALID_ARGUMENT;\n\n\treturn UBUS_STATUS_OK;\n}\n\nstatic const struct ubus_method wpas_daemon_methods[] = {\n\tUBUS_METHOD(\"config_add\", wpas_config_add, wpas_config_add_policy),\n\tUBUS_METHOD(\"config_remove\", wpas_config_remove, wpas_config_remove_policy),\n};\n\nstatic struct ubus_object_type wpas_daemon_object_type =\n\tUBUS_OBJECT_TYPE(\"wpa_supplicant\", wpas_daemon_methods);\n\nvoid wpas_ubus_add(struct wpa_global *global)\n{\n\tstruct ubus_object *obj = &global->ubus_global;\n\tint ret;\n\n\tif (!wpas_ubus_init())\n\t\treturn;\n\n\tobj->name = strdup(\"wpa_supplicant\");\n\n\tobj->type = &wpas_daemon_object_type;\n\tobj->methods = wpas_daemon_object_type.methods;\n\tobj->n_methods = wpas_daemon_object_type.n_methods;\n\tret = ubus_add_object(ctx, obj);\n\twpas_ubus_ref_inc();\n}\n\nvoid wpas_ubus_free(struct wpa_global *global)\n{\n\tstruct ubus_object *obj = &global->ubus_global;\n\tchar *name = (char *) obj->name;\n\n\tif (!ctx)\n\t\treturn;\n\n\tif (obj->id) {\n\t\tubus_remove_object(ctx, obj);\n\t\twpas_ubus_ref_dec();\n\t}\n\n\tfree(name);\n}\n\n\n#ifdef CONFIG_WPS\nvoid wpas_ubus_notify(struct wpa_supplicant *wpa_s, const struct wps_credential *cred)\n{\n\tu16 auth_type;\n\tchar *ifname, *encryption, *ssid, *key;\n\tsize_t ifname_len;\n\n\tif (!cred)\n\t\treturn;\n\n\tauth_type = cred->auth_type;\n\n\tif (auth_type == (WPS_AUTH_WPAPSK | WPS_AUTH_WPA2PSK))\n\t\tauth_type = WPS_AUTH_WPA2PSK;\n\n\tif (auth_type != WPS_AUTH_OPEN &&\n\t    auth_type != WPS_AUTH_WPAPSK &&\n\t    auth_type != WPS_AUTH_WPA2PSK) {\n\t\twpa_printf(MSG_DEBUG, \"WPS: Ignored credentials for \"\n\t\t\t   \"unsupported authentication type 0x%x\",\n\t\t\t   auth_type);\n\t\treturn;\n\t}\n\n\tif (auth_type == WPS_AUTH_WPAPSK || auth_type == WPS_AUTH_WPA2PSK) {\n\t\tif (cred->key_len < 8 || cred->key_len > 2 * PMK_LEN) {\n\t\t\twpa_printf(MSG_ERROR, \"WPS: Reject PSK credential with \"\n\t\t\t\t   \"invalid Network Key length %lu\",\n\t\t\t\t   (unsigned long) cred->key_len);\n\t\t\treturn;\n\t\t}\n\t}\n\n\tblob_buf_init(&b, 0);\n\n\tifname_len = strlen(wpa_s->ifname);\n\tifname = blobmsg_alloc_string_buffer(&b, \"ifname\", ifname_len + 1);\n\tmemcpy(ifname, wpa_s->ifname, ifname_len + 1);\n\tifname[ifname_len] = '\\0';\n\tblobmsg_add_string_buffer(&b);\n\n\tswitch (auth_type) {\n\t\tcase WPS_AUTH_WPA2PSK:\n\t\t\tencryption = \"psk2\";\n\t\t\tbreak;\n\t\tcase WPS_AUTH_WPAPSK:\n\t\t\tencryption = \"psk\";\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tencryption = \"none\";\n\t\t\tbreak;\n\t}\n\n\tblobmsg_add_string(&b, \"encryption\", encryption);\n\n\tssid = blobmsg_alloc_string_buffer(&b, \"ssid\", cred->ssid_len + 1);\n\tmemcpy(ssid, cred->ssid, cred->ssid_len);\n\tssid[cred->ssid_len] = '\\0';\n\tblobmsg_add_string_buffer(&b);\n\n\tif (cred->key_len > 0) {\n\t\tkey = blobmsg_alloc_string_buffer(&b, \"key\", cred->key_len + 1);\n\t\tmemcpy(key, cred->key, cred->key_len);\n\t\tkey[cred->key_len] = '\\0';\n\t\tblobmsg_add_string_buffer(&b);\n\t}\n\n//\tubus_notify(ctx, &wpa_s->ubus.obj, \"wps_credentials\", b.head, -1);\n\tubus_send_event(ctx, \"wps_credentials\", b.head);\n}\n#endif /* CONFIG_WPS */\n"
  },
  {
    "path": "package/network/services/hostapd/src/wpa_supplicant/ubus.h",
    "content": "/*\n * wpa_supplicant / ubus support\n * Copyright (c) 2018, Daniel Golle <daniel@makrotopia.org>\n * Copyright (c) 2013, Felix Fietkau <nbd@nbd.name>\n *\n * This software may be distributed under the terms of the BSD license.\n * See README for more details.\n */\n#ifndef __WPAS_UBUS_H\n#define __WPAS_UBUS_H\n\nstruct wpa_supplicant;\nstruct wpa_global;\n\n#include \"wps_supplicant.h\"\n\n#ifdef UBUS_SUPPORT\n#include <libubus.h>\n\nstruct wpas_ubus_bss {\n\tstruct ubus_object obj;\n};\n\nvoid wpas_ubus_add_bss(struct wpa_supplicant *wpa_s);\nvoid wpas_ubus_free_bss(struct wpa_supplicant *wpa_s);\n\nvoid wpas_ubus_add(struct wpa_global *global);\nvoid wpas_ubus_free(struct wpa_global *global);\n\n#ifdef CONFIG_WPS\nvoid wpas_ubus_notify(struct wpa_supplicant *wpa_s, const struct wps_credential *cred);\n#endif\n\n#else\nstruct wpas_ubus_bss {};\n\nstatic inline void wpas_ubus_add_iface(struct wpa_supplicant *wpa_s)\n{\n}\n\nstatic inline void wpas_ubus_free_iface(struct wpa_supplicant *wpa_s)\n{\n}\n\nstatic inline void wpas_ubus_add_bss(struct wpa_supplicant *wpa_s)\n{\n}\n\nstatic inline void wpas_ubus_free_bss(struct wpa_supplicant *wpa_s)\n{\n}\n\nstatic inline void wpas_ubus_notify(struct wpa_supplicant *wpa_s, struct wps_credential *cred)\n{\n}\n\nstatic inline void wpas_ubus_add(struct wpa_global *global)\n{\n}\n\nstatic inline void wpas_ubus_free(struct wpa_global *global)\n{\n}\n#endif\n\n#endif\n"
  },
  {
    "path": "package/network/services/ipset-dns/Makefile",
    "content": "#\n# Copyright (C) 2013 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=ipset-dns\nPKG_RELEASE:=1\n\nPKG_SOURCE_PROTO:=git\nPKG_SOURCE_URL:=http://git.zx2c4.com/ipset-dns\nPKG_SOURCE_DATE:=2017-10-08\nPKG_SOURCE_VERSION:=ade2cf88e933f4f90451e0a6171f0aa4a523f989\nPKG_MIRROR_HASH:=34ad1f5c7d2eab90b795f2a512102891428216e3d439d918a8992846550e9697\nPKG_MAINTAINER:=Jo-Philipp Wich <jo@mein.io>\n\nPKG_LICENSE:=GPL-2.0\nPKG_LICENSE_FILES:=COPYING\n\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine Package/ipset-dns/Default\nendef\n\ndefine Package/ipset-dns\n  SECTION:=net\n  CATEGORY:=Network\n  TITLE:=A lightweight DNS forwarder to populate ipsets\n  URL:=http://git.zx2c4.com/ipset-dns/about/\n  DEPENDS:=+libmnl\nendef\n\ndefine Package/ipset-dns/description\n The ipset-dns daemon is a lightweight DNS forwarding server that adds all\n resolved IPs to a given netfilter ipset. It is designed to be used in\n conjunction with dnsmasq's upstream server directive.\n\n Practical use cases include routing over a given gateway traffic for\n particular web services or webpages that do not have a priori predictable\n IP addresses and instead rely on dizzying arrays of DNS resolutions.\nendef\n\ndefine Package/ipset-dns/conffiles\n/etc/config/ipset-dns\nendef\n\ndefine Package/ipset-dns/install\n\t$(INSTALL_DIR) $(1)/usr/sbin\n\t$(INSTALL_BIN) $(PKG_BUILD_DIR)/ipset-dns $(1)/usr/sbin/ipset-dns\n\t$(INSTALL_DIR) $(1)/etc/init.d\n\t$(INSTALL_BIN) ./files/ipset-dns.init $(1)/etc/init.d/ipset-dns\n\t$(INSTALL_DIR) $(1)/etc/config\n\t$(INSTALL_CONF) ./files/ipset-dns.config $(1)/etc/config/ipset-dns\nendef\n\n$(eval $(call BuildPackage,ipset-dns))\n"
  },
  {
    "path": "package/network/services/ipset-dns/files/ipset-dns.config",
    "content": "# declare an ipset-dns listener instance, multiple allowed\nconfig ipset-dns\n\t# use given ipset for type A (IPv4) responses\n\toption ipset 'domain-filter-ipv4'\n\n\t# use given ipset for type AAAA (IPv6) responses\n\toption ipset6 'domain-filter-ipv6'\n\n\t# use given listening port\n\t# defaults to 53000 + instance number\n\t#option port  '53001'\n\n\t# use given upstream DNS server,\n\t# defaults to first entry in /tmp/resolv.conf.d/resolv.conf.auto\n\t#option dns   '8.8.8.8'\n\n"
  },
  {
    "path": "package/network/services/ipset-dns/files/ipset-dns.init",
    "content": "#!/bin/sh /etc/rc.common\n# Copyright (C) 2013 OpenWrt.org\n\nSTART=61\n\nUSE_PROCD=1\n\nfind_nameserver() {\n\t. /lib/functions/network.sh\n\n\tlocal tmp\n\tif network_find_wan tmp && network_get_dnsserver tmp \"$tmp\"; then\n\t\techo \"${tmp%% *}\"\n\t\treturn 0\n\tfi\n\n\treturn 1\n}\n\nstart_instance() {\n\tlocal cfg=\"$1\"\n\tlocal ipset ipset6 port dns\n\n\tconfig_get ipset \"$cfg\" ipset\n\tconfig_get ipset6 \"$cfg\" ipset6\n\t[ -n \"$ipset$ipset6\" ] || {\n\t\techo \"No ipset specified for instance $cfg\" >&2\n\t\treturn 1\n\t}\n\n\tconfig_get dns \"$cfg\" dns \"$DEFNS\"\n\t[ -n \"$dns\" ] || {\n\t\techo \"No DNS server specified for instance $cfg\" >&2\n\t\treturn 1\n\t}\n\n\tconfig_get port \"$cfg\" port $((PORT++))\n\n\tprocd_open_instance\n\tprocd_set_param command /usr/sbin/ipset-dns \"$ipset\" \"$ipset6\" \"$port\" \"$dns\"\n\tprocd_set_param env NO_DAEMONIZE=1\n\tprocd_set_param respawn\n\tprocd_close_instance\n}\n\nservice_triggers()\n{\n\tprocd_add_reload_trigger \"ipset-dns\"\n}\n\nstart_service() {\n\tPORT=53001\n\tDEFNS=\"$(find_nameserver)\"\n\n\tconfig_load ipset-dns\n\tconfig_foreach start_instance ipset-dns\n}\n"
  },
  {
    "path": "package/network/services/lldpd/Config.in",
    "content": "menu \"Configuration\"\n\tdepends on PACKAGE_lldpd\n\nconfig LLDPD_WITH_PRIVSEP\n\tbool\n\tdefault y\n\tprompt \"Enable privilege separation (run lldpd with a chrooted 'lldp' user)\"\n\nconfig LLDPD_WITH_CDP\n\tbool\n\tdefault y\n\tprompt \"Enable support for the Cisco Discovery Protocol (CDP) version 1 and 2\"\n\nconfig LLDPD_WITH_FDP\n\tbool\n\tdefault y\n\tprompt \"Enable support for the Foundry Discovery Protocol (FDP)\"\n\nconfig LLDPD_WITH_EDP\n\tbool\n\tdefault y\n\tprompt \"Enable support for the Extreme Discovery Protocol (EDP)\"\n\nconfig LLDPD_WITH_SONMP\n\tbool\n\tdefault y\n\tprompt \"Enable support for the SynOptics Network Management Protocol\"\n\nconfig LLDPD_WITH_LLDPMED\n\tbool\n\tprompt \"Enable LLDP-MED extension\"\n\tdefault y\n\nconfig LLDPD_WITH_DOT1\n\tbool\n\tprompt \"Enable Dot1 extension (VLAN stuff)\"\n\tdefault y\n\nconfig LLDPD_WITH_DOT3\n\tbool\n\tprompt \"Enable Dot3 extension (PHY stuff)\"\n\tdefault y\n\nconfig LLDPD_WITH_CUSTOM\n\tbool\n\tprompt \"Enable Custom TLVs\"\n\tdefault y\n\nconfig LLDPD_WITH_JSON\n\tbool\n\tprompt \"Enable JSON output for the LLDP Command-Line Interface\"\n\tdefault n\n\nconfig LLDPD_WITH_SNMP\n\tbool\n\tdefault n\n\tprompt \"Enable the use of SNMP\"\nendmenu\n"
  },
  {
    "path": "package/network/services/lldpd/Makefile",
    "content": "#\n# Copyright (C) 2008-2015 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=lldpd\nPKG_VERSION:=1.0.13\nPKG_RELEASE:=3\n\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz\nPKG_SOURCE_URL:=https://media.luffy.cx/files/lldpd\nPKG_HASH:=d639827fd8a27720d1bfd94bc52eca24af63ddcc3c9d2da60788778889d84701\n\nPKG_MAINTAINER:=Stijn Tintel <stijn@linux-ipv6.be>\nPKG_LICENSE:=ISC\n\nPKG_FIXUP:=autoreconf\nPKG_BUILD_PARALLEL:=1\nPKG_INSTALL:=1\n\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine Package/lldpd\n  SECTION:=net\n  CATEGORY:=Network\n  SUBMENU:=Routing and Redirection\n  TITLE:=Link Layer Discovery Protocol daemon\n  URL:=https://vincentbernat.github.io/lldpd/\n  DEPENDS:=+libcap +libevent2 +USE_GLIBC:libbsd +LLDPD_WITH_JSON:libjson-c +LLDPD_WITH_SNMP:libnetsnmp\n  USERID:=lldp=121:lldp=129\n  MENU:=1\nendef\n\ndefine Package/lldpd/config\nsource \"$(SOURCE)/Config.in\"\nendef\n\ndefine Package/lldpd/description\n\tLLDP (Link Layer Discovery Protocol) is an industry standard protocol designed\n\tto supplant proprietary Link-Layer protocols such as\n\tExtreme's EDP (Extreme Discovery Protocol) and\n\tCDP (Cisco Discovery Protocol).\n\tThe goal of LLDP is to provide an inter-vendor compatible mechanism to deliver\n\tLink-Layer notifications to adjacent network devices.\nendef\n\ndefine Build/InstallDev\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/liblldpctl.so* $(1)/usr/lib/\n\t$(INSTALL_DIR) $(1)/usr/include\n\t$(CP) $(PKG_INSTALL_DIR)/usr/include/lldpctl.h $(1)/usr/include/lldpctl.h\n\t$(CP) $(PKG_INSTALL_DIR)/usr/include/lldp-const.h $(1)/usr/include/lldp-const.h\nendef\n\ndefine Package/lldpd/install\n\t$(INSTALL_DIR) $(1)/etc/init.d\n\t$(INSTALL_DIR) $(1)/etc/lldpd.d\n\t$(INSTALL_DIR) $(1)/etc/config\n\t$(INSTALL_DIR) $(1)/usr/lib $(1)/usr/sbin\n\t$(CP) $(PKG_INSTALL_DIR)/usr/sbin/lldp{cli,ctl,d} $(1)/usr/sbin/\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/liblldpctl.so* $(1)/usr/lib/\n\t$(INSTALL_BIN) ./files/lldpd.init $(1)/etc/init.d/lldpd\n\t$(INSTALL_CONF) ./files/lldpd.config $(1)/etc/config/lldpd\nifneq ($(CONFIG_LLDPD_WITH_CDP),y)\n\tsed -i -e '/cdp/d' $(1)/etc/init.d/lldpd $(1)/etc/config/lldpd\nendif\nifneq ($(CONFIG_LLDPD_WITH_FDP),y)\n\tsed -i -e '/fdp/d' $(1)/etc/init.d/lldpd $(1)/etc/config/lldpd\nendif\nifneq ($(CONFIG_LLDPD_WITH_EDP),y)\n\tsed -i -e '/edp/d' $(1)/etc/init.d/lldpd $(1)/etc/config/lldpd\nendif\nifneq ($(CONFIG_LLDPD_WITH_SONMP),y)\n\tsed -i -e '/sonmp/d' $(1)/etc/init.d/lldpd $(1)/etc/config/lldpd\nendif\nifneq ($(CONFIG_LLDPD_WITH_SNMP),y)\n\tsed -i -e '/agentxsocket/d' $(1)/etc/init.d/lldpd $(1)/etc/config/lldpd\nendif\nendef\n\ndefine Package/lldpd/conffiles\n/etc/config/lldpd\nendef\n\nCONFIGURE_ARGS += \\\n\t$(if $(CONFIG_LLDPD_WITH_PRIVSEP), \\\n\t--with-privsep-user=lldp \\\n\t--with-privsep-group=lldp \\\n\t--with-privsep-chroot=/var/run/lldp \\\n\t,--disable-privsep) \\\n\t--with-readline=no \\\n\t--with-embedded-libevent=no \\\n\t--disable-hardening \\\n\t--without-xml \\\n\t--disable-doxygen-doc \\\n\t--sysconfdir=/tmp \\\n\t$(if $(CONFIG_LLDPD_WITH_CDP),,--disable-cdp) \\\n\t$(if $(CONFIG_LLDPD_WITH_FDP),,--disable-fdp) \\\n\t$(if $(CONFIG_LLDPD_WITH_EDP),,--disable-edp) \\\n\t$(if $(CONFIG_LLDPD_WITH_LLDPMED),,--disable-lldpmed) \\\n\t$(if $(CONFIG_LLDPD_WITH_DOT1),,--disable-dot1) \\\n\t$(if $(CONFIG_LLDPD_WITH_DOT3),,--disable-dot3) \\\n\t$(if $(CONFIG_LLDPD_WITH_CUSTOM),,--disable-custom) \\\n\t$(if $(CONFIG_LLDPD_WITH_SONMP),,--disable-sonmp) \\\n\t$(if $(CONFIG_LLDPD_WITH_JSON),--enable-json0,) \\\n\t$(if $(CONFIG_LLDPD_WITH_SNMP),--with-snmp,) \\\n\t$(if $(CONFIG_USE_GLIBC),,--without-libbsd)\n\nTARGET_CFLAGS += -flto\nTARGET_LDFLAGS += -flto -Wl,--gc-sections,--as-needed\n\n$(eval $(call BuildPackage,lldpd))\n"
  },
  {
    "path": "package/network/services/lldpd/files/lldpd.config",
    "content": "config lldpd config\n\toption enable_cdp 1\n\toption enable_fdp 1\n\toption enable_sonmp 1\n\toption enable_edp 1\n\n\toption agentxsocket /var/run/agentx.sock\n\n\toption lldp_class 4\n\toption lldp_location \"2:FR:6:Commercial Rd:3:Roseville:19:4\"\n\n\t# if empty, the distribution description is sent\n\t#option lldp_description \"OpenWrt System\"\n\t#option lldp_hostname \"Modified Hostname\"\n\n\t#option lldp_mgmt_ip \"!192.168.1.1\"\n\n\t# interfaces to listen on\n\tlist interface \"loopback\"\n\tlist interface \"lan\"\n"
  },
  {
    "path": "package/network/services/lldpd/files/lldpd.init",
    "content": "#!/bin/sh /etc/rc.common\n# Copyright (C) 2008-2015 OpenWrt.org\n\nSTART=90\nSTOP=01\n\nUSE_PROCD=1\nLLDPCLI=/usr/sbin/lldpcli\nLLDPSOCKET=/var/run/lldpd.socket\nLLDPD_CONF=/tmp/lldpd.conf\nLLDPD_CONFS_DIR=/tmp/lldpd.d\n\nfind_release_info()\n{\n\t[ -s /etc/os-release ] && . /etc/os-release\n\t[ -z \"$PRETTY_NAME\" ] && [ -s /etc/openwrt_version ] && \\\n\t\tPRETTY_NAME=\"$(cat /etc/openwrt_version)\"\n\n\techo \"${PRETTY_NAME:-Unknown OpenWrt release} @ $(cat /proc/sys/kernel/hostname)\"\n}\n\nwrite_lldpd_conf()\n{\n\t. /lib/functions/network.sh\n\n\tlocal lldp_description\n\n\tconfig_load 'lldpd'\n\tconfig_get lldp_description 'config' 'lldp_description' \"$(find_release_info)\"\n\n\tlocal lldp_hostname\n\tconfig_get lldp_hostname 'config' 'lldp_hostname' \"$(cat /proc/sys/kernel/hostname)\"\n\n\tlocal ifaces\n\tconfig_get ifaces 'config' 'interface'\n\n\tlocal iface ifnames=\"\"\n\tfor iface in $ifaces; do\n\t\tlocal ifname=\"\"\n\t\tif network_get_device ifname \"$iface\" || [ -e \"/sys/class/net/$iface\" ]; then\n\t\t\tappend ifnames \"${ifname:-$iface}\" \",\"\n\t\tfi\n\tdone\n\n\tlocal lldp_mgmt_ip\n\tconfig_get lldp_mgmt_ip 'config' 'lldp_mgmt_ip'\n\n\t# Clear out the config file first\n\techo -n > \"$LLDPD_CONF\"\n\t[ -n \"$ifnames\" ] && echo \"configure system interface pattern\" \"$ifnames\" >> \"$LLDPD_CONF\"\n\t[ -n \"$lldp_description\" ] && echo \"configure system description\" \"\\\"$lldp_description\\\"\" >> \"$LLDPD_CONF\"\n\t[ -n \"$lldp_hostname\" ] && echo \"configure system hostname\" \"\\\"$lldp_hostname\\\"\" >> \"$LLDPD_CONF\"\n\t[ -n \"$lldp_mgmt_ip\" ] && echo \"configure system ip management pattern\" \"\\\"$lldp_mgmt_ip\\\"\" >> \"$LLDPD_CONF\"\n\n\t# Since lldpd's sysconfdir is /tmp, we'll symlink /etc/lldpd.d to /tmp/$LLDPD_CONFS_DIR\n\t[ -e $LLDPD_CONFS_DIR ] || ln -s /etc/lldpd.d $LLDPD_CONFS_DIR\n}\n\nservice_triggers() {\n\tprocd_add_reload_trigger \"lldpd\"\n}\n\nstart_service() {\n\n\tlocal enable_cdp\n\tlocal enable_fdp\n\tlocal enable_sonmp\n\tlocal enable_edp\n\tlocal lldp_class\n\tlocal lldp_location\n\tlocal readonly_mode\n\tlocal agentxsocket\n\n\tconfig_load 'lldpd'\n\tconfig_get_bool enable_cdp 'config' 'enable_cdp' 0\n\tconfig_get_bool enable_fdp 'config' 'enable_fdp' 0\n\tconfig_get_bool enable_sonmp 'config' 'enable_sonmp' 0\n\tconfig_get_bool enable_edp 'config' 'enable_edp' 0\n\tconfig_get lldp_class 'config' 'lldp_class'\n\tconfig_get lldp_location 'config' 'lldp_location'\n\tconfig_get_bool readonly_mode 'config' 'readonly_mode' 0\n\tconfig_get agentxsocket 'config' 'agentxsocket'\n\n\tmkdir -p /var/run/lldp\n\tchown lldp:lldp /var/run/lldp\n\n\t# When lldpd starts, it also loads up what we write in this config file\n\twrite_lldpd_conf\n\n\tprocd_open_instance\n\tprocd_set_param command /usr/sbin/lldpd -d\n\n\t[ $enable_cdp -gt 0 ] && procd_append_param command '-c'\n\t[ $enable_fdp -gt 0 ] && procd_append_param command '-f'\n\t[ $enable_sonmp -gt 0 ] && procd_append_param command '-s'\n\t[ $enable_edp -gt 0 ] && procd_append_param command '-e'\n\t[ $readonly_mode -gt 0 ] && procd_append_param command '-r'\n\t[ -n \"$lldp_class\" ] && procd_append_param command -M \"$lldp_class\"\n\t[ -n \"$agentxsocket\" ] && procd_append_param command -x -X \"$agentxsocket\"\n\n\t# set auto respawn behavior\n\tprocd_set_param respawn\n\tprocd_close_instance\n}\n\nreload_service() {\n\trunning || return 1\n\t$LLDPCLI -u $LLDPSOCKET &> /dev/null <<-EOF\n\t\tpause\n\t\tunconfigure lldp custom-tlv\n\t\tunconfigure system interface pattern\n\t\tunconfigure system description\n\t\tunconfigure system hostname\n\t\tunconfigure system ip management pattern\n\tEOF\n\t# Rewrite lldpd.conf\n\t# If something changed it should be included by the lldpcli call\n\twrite_lldpd_conf\n\t$LLDPCLI -u $LLDPSOCKET -c $LLDPD_CONF -c $LLDPD_CONFS_DIR &> /dev/null\n\t# Broadcast update over the wire\n\t$LLDPCLI -u $LLDPSOCKET &> /dev/null <<-EOF\n\t\tresume\n\t\tupdate\n\tEOF\n\treturn 0\n}\n\nstop_service() {\n\trm -rf /var/run/lldp $LLDPSOCKET\n}\n"
  },
  {
    "path": "package/network/services/odhcpd/Makefile",
    "content": "#\n# Copyright (C) 2013-2015 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=odhcpd\nPKG_RELEASE:=$(AUTORELEASE)\n\nPKG_SOURCE_PROTO:=git\nPKG_SOURCE_URL=$(PROJECT_GIT)/project/odhcpd.git\nPKG_SOURCE_DATE:=2022-03-22\nPKG_SOURCE_VERSION:=860ca900e41c5d0f98cc85e67b39977f6f2cb355\nPKG_MIRROR_HASH:=555712a1e25d197e52808a0d5e42bf0d48a8b61fe7c8aad1a02a7c09f0b8b8a3\n\nPKG_MAINTAINER:=Hans Dedecker <dedeckeh@gmail.com>\nPKG_LICENSE:=GPL-2.0\n\nPKG_CONFIG_DEPENDS:=CONFIG_PACKAGE_odhcpd_$(BUILD_VARIANT)_ext_cer_id\nPKG_ASLR_PIE_REGULAR:=1\n\ninclude $(INCLUDE_DIR)/package.mk\ninclude $(INCLUDE_DIR)/cmake.mk\n\ndefine Package/odhcpd/default\n  SECTION:=net\n  CATEGORY:=Network\n  TITLE:=OpenWrt DHCPv6(-PD)/RA Server & Relay\n  DEPENDS:=+libubox +libuci +libubus +libnl-tiny\nendef\n\ndefine Package/odhcpd/default/description\n odhcpd is a daemon for serving and relaying IP management protocols to\n configure clients and downstream routers. It tries to follow the RFC 6204\n requirements for IPv6 home routers.\nendef\n\ndefine Package/odhcpd/default/config\nmenu \"Configuration\"\n\tdepends on PACKAGE_$(1)\n\nconfig PACKAGE_odhcpd_$(2)_ext_cer_id\n\tint\n\tdefault 0\n\tprompt \"CER-ID Extension ID (0 = disabled)\"\nendmenu\nendef\n\ndefine Package/odhcpd\n  $(call Package/odhcpd/default)\n  TITLE += and DHCPv4 server\n  VARIANT:=full\nendef\n\nPackage/odhcpd/config=$(call Package/odhcpd/default/config,odhcpd,full)\n\ndefine Package/odhcpd/description\n $(call Package/odhcpd/default/description)\n\n This is a variant providing server services for DHCPv4, RA, stateless and\n stateful DHCPv6,  prefix delegation and can be used to relay RA, DHCPv6 and\n NDP between routed (non-bridged) interfaces in case no delegated prefixes\n are available.\nendef\n\ndefine Package/odhcpd-ipv6only\n  $(call Package/odhcpd/default)\n  VARIANT:=ipv6only\n  DEPENDS+= @IPV6\nendef\n\nPackage/odhcpd-ipv6only/config=$(call Package/odhcpd/default/config,odhcpd-ipv6only,ipv6only)\n\ndefine Package/odhcpd-ipv6only/description\n $(call Package/odhcpd/default/description)\n\n This is a variant providing server services for RA, stateless and stateful\n DHCPv6,  prefix delegation and can be used to relay RA, DHCPv6 and NDP between\n routed (non-bridged) interfaces in case no delegated prefixes are available.\nendef\n\nCMAKE_OPTIONS += -DUBUS=1\n\nifeq ($(BUILD_VARIANT),full)\n  CMAKE_OPTIONS += -DDHCPV4_SUPPORT=1\nendif\n\nifneq ($(CONFIG_PACKAGE_odhcpd_$(BUILD_VARIANT)_ext_cer_id),0)\n  CMAKE_OPTIONS += -DEXT_CER_ID=$(CONFIG_PACKAGE_odhcpd_$(BUILD_VARIANT)_ext_cer_id)\nendif\n\ndefine Package/odhcpd/install\n\t$(INSTALL_DIR) $(1)/usr/sbin/\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/sbin/odhcpd $(1)/usr/sbin/\n\t$(INSTALL_BIN) ./files/odhcpd-update $(1)/usr/sbin/\n\t$(INSTALL_DIR) $(1)/etc/init.d\n\t$(INSTALL_BIN) ./files/odhcpd.init $(1)/etc/init.d/odhcpd\n\t$(INSTALL_DIR) $(1)/etc/uci-defaults\n\t$(INSTALL_BIN) ./files/odhcpd.defaults $(1)/etc/uci-defaults/15_odhcpd\nendef\n\nPackage/odhcpd-ipv6only/install = $(Package/odhcpd/install)\n\n$(eval $(call BuildPackage,odhcpd))\n$(eval $(call BuildPackage,odhcpd-ipv6only))\n"
  },
  {
    "path": "package/network/services/odhcpd/files/odhcpd-update",
    "content": "#!/bin/sh\n# Make dnsmasq reread hostfile by sending SIGHUP signal\n\n. /lib/functions/procd.sh\n\nprocd_send_signal dnsmasq\n"
  },
  {
    "path": "package/network/services/odhcpd/files/odhcpd.defaults",
    "content": "#!/bin/sh\nuci -q get dhcp.odhcpd && exit 0\ntouch /etc/config/dhcp\n\n. /usr/share/libubox/jshn.sh\n\njson_load \"$(cat /etc/board.json)\"\njson_select network\njson_select lan\njson_get_vars protocol\njson_select ..\njson_select ..\n\nODHCPDONLY=0\nV4MODE=disabled\nV6MODE=disabled\n\n[ -e /usr/sbin/dnsmasq ] || ODHCPDONLY=1\n\ncase \"$protocol\" in\n# only enable server mode on statically addressed lan ports\n\"static\")\n\tV4MODE=server\n\t[ -e /proc/sys/net/ipv6 ] && V6MODE=server\n\t;;\nesac\n\nuci get dhcp.lan 1>/dev/null 2>/dev/null || {\nuci batch <<EOF\nset dhcp.lan=dhcp\nset dhcp.lan.interface='lan'\nset dhcp.lan.start='100'\nset dhcp.lan.limit='150'\nset dhcp.lan.leasetime='12h'\nset dhcp.lan.domain='lan'\nEOF\n}\n\nuci batch <<EOF\nset dhcp.odhcpd=odhcpd\nset dhcp.odhcpd.maindhcp=$ODHCPDONLY\nset dhcp.odhcpd.leasefile=/tmp/hosts/odhcpd\nset dhcp.odhcpd.leasetrigger=/usr/sbin/odhcpd-update\nset dhcp.odhcpd.loglevel=4\nset dhcp.lan.dhcpv4=$V4MODE\nset dhcp.lan.dhcpv6=$V6MODE\nset dhcp.lan.ra=$V6MODE\nset dhcp.lan.ra_slaac=1\nadd_list dhcp.lan.ra_flags=managed-config\nadd_list dhcp.lan.ra_flags=other-config\ncommit dhcp\nEOF\n"
  },
  {
    "path": "package/network/services/odhcpd/files/odhcpd.init",
    "content": "#!/bin/sh /etc/rc.common\n\nSTART=35\nSTOP=85\nUSE_PROCD=1\n\nstart_service() {\n\tprocd_open_instance\n\tprocd_set_param command /usr/sbin/odhcpd\n\tprocd_set_param respawn\n\tprocd_close_instance\n}\n\nreload_service() {\n\tprocd_send_signal odhcpd\n}\n\nservice_triggers()\n{\n\tprocd_add_reload_trigger \"dhcp\"\n}\n\n"
  },
  {
    "path": "package/network/services/omcproxy/Makefile",
    "content": "#\n# Copyright (C) 2015 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=omcproxy\nPKG_RELEASE:=9\n\nPKG_SOURCE_PROTO:=git\nPKG_SOURCE_URL=$(PROJECT_GIT)/project/omcproxy.git\nPKG_MIRROR_HASH:=6443276368dc7d45ee58bd7067da6c3a85396d9996039232cae3bdd426382f0c\nPKG_SOURCE_DATE:=2021-11-04\nPKG_SOURCE_VERSION:=bfba2aa75802ff1a70ef2fd3eba53409a8c6e93a\nPKG_MAINTAINER:=Steven Barth <cyrus@openwrt.org>\nPKG_LICENSE:=Apache-2.0\n\ninclude $(INCLUDE_DIR)/package.mk\ninclude $(INCLUDE_DIR)/cmake.mk\n\ndefine Package/omcproxy\n  SECTION:=net\n  CATEGORY:=Network\n  DEPENDS:=+libubox +libubus\n  TITLE:=IGMPv3 and MLDv2 Multicast Proxy\nendef\n\ndefine Package/omcproxy/conffiles\n/etc/config/omcproxy\nendef\n\nCMAKE_OPTIONS += -DWITH_LIBUBOX=1\n\ndefine Package/omcproxy/install\n\t$(INSTALL_DIR) $(1)/etc/config\n\t$(INSTALL_CONF) ./files/omcproxy.config $(1)/etc/config/omcproxy\n\t$(INSTALL_DIR) $(1)/etc/init.d\n\t$(INSTALL_BIN) ./files/omcproxy.init $(1)/etc/init.d/omcproxy\n\t$(INSTALL_DIR) $(1)/usr/sbin\n\t$(INSTALL_BIN) $(PKG_BUILD_DIR)/omcproxy $(1)/usr/sbin/\nendef\n\n$(eval $(call BuildPackage,omcproxy))\n"
  },
  {
    "path": "package/network/services/omcproxy/files/omcproxy.config",
    "content": "config proxy\n\toption scope global\n\toption uplink wan\n\tlist downlink lan\n\nconfig proxy\n\toption scope global\n\toption uplink wan6\n\tlist downlink lan\n"
  },
  {
    "path": "package/network/services/omcproxy/files/omcproxy.init",
    "content": "#!/bin/sh /etc/rc.common\n# Copyright (C) 2018 OpenWrt.org\n\nSTART=99\nUSE_PROCD=1\nPROG=/usr/sbin/omcproxy\n\n# Uncomment to enable verbosity\n#OPTIONS=\"-v\"\nPROXIES=\"\"\n\nomcproxy_add_proxy() {\n\tlocal proxy scope uplink updevice downlinks\n\n\tconfig_get uplink $1 uplink\n\t[ -n \"$uplink\" ] || return\n\n\tnetwork_get_device updevice \"$uplink\" || {\n\t\tprocd_append_param error \"$uplink is not up\"\n\t\treturn;\n\t}\n\n\tconfig_get downlinks $1 downlink\n\tfor downlink in $downlinks; do\n\t\tlocal device\n\n\t\tnetwork_get_device device \"$downlink\" || {\n\t\t\tprocd_append_param error \"$downlink is not up\"\n\t\t\tcontinue;\n\t\t}\n\n\t\tproxy=\"$proxy,$device\"\n\n\t\t# Disable in-kernel querier while ours is active, default is 1.\n\t\t[ -f /sys/class/net/$device/bridge/multicast_querier ] && \\\n\t\t\techo 0 > /sys/class/net/$device/bridge/multicast_querier\n\tdone\n\n\t[ -n \"$proxy\" ] || return 0\n\n\tconfig_get scope $1 scope\n\t[ -n \"$scope\" ] && proxy=\"$proxy,scope=$scope\"\n\n\tPROXIES=\"$PROXIES $updevice$proxy\"\n}\n\nomcproxy_add_network_triggers() {\n\tlocal uplink downlinks\n\n\tconfig_get uplink $1 uplink\n\tconfig_get downlinks $1 downlink\n\n\tfor link in $uplink $downlinks; do\n\t\tlocal duplicate=0\n\n\t\tfor l in $LINKS; do\n\t\t\t[ \"$l\" = \"$link\" ] && duplicate=1\n\t\tdone\n\n\t\t[ \"$duplicate\" = 0 ] && {\n\t\t\tLINKS=\"$LINKS $link\"\n\t\t\tprocd_add_interface_trigger \"interface.*\" $link /etc/init.d/omcproxy restart\n\t\t}\n\tdone\n}\n\nomcproxy_add_firewall_rules() {\n\tlocal uplink downlinks\n\n\tconfig_get uplink $1 uplink\n\tconfig_get downlinks $1 downlink\n\n\tupzone=$(fw3 -q network $uplink 2>/dev/null)\n\t[ -n \"$upzone\" ] || return 0\n\n\tjson_add_object \"\"\n\tjson_add_string type rule\n\tjson_add_string src \"$upzone\"\n\tjson_add_string family ipv4\n\tjson_add_string proto igmp\n\tjson_add_string target ACCEPT\n\tjson_close_object\n\n\tjson_add_object \"\"\n\tjson_add_string type rule\n\tjson_add_string family ipv6\n\tjson_add_string src \"$upzone\"\n\tjson_add_string proto icmp\n\tjson_add_string src_ip fe80::/10\n\tjson_add_array icmp_type\n\t\tjson_add_string \"\" 130/0\n\t\tjson_add_string \"\" 131/0\n\t\tjson_add_string \"\" 132/0\n\t\tjson_add_string \"\" 143/0\n\tjson_close_array\n\tjson_add_string target ACCEPT\n\tjson_close_object\n\n\tfor downlink in $downlinks; do\n\t\tdownzone=$(fw3 -q network $downlink 2>/dev/null)\n\t\t[ -n \"$downzone\" ] || continue\n\n\t\tjson_add_object \"\"\n\t\tjson_add_string type rule\n\t\tjson_add_string src \"$upzone\"\n\t\tjson_add_string dest \"$downzone\"\n\t\tjson_add_string family ipv4\n\t\tjson_add_string proto udp\n\t\tjson_add_string dest_ip \"224.0.0.0/4\"\n\t\tjson_add_string target ACCEPT\n\t\tjson_close_object\n\n\t\tjson_add_object \"\"\n\t\tjson_add_string type rule\n\t\tjson_add_string src \"$upzone\"\n\t\tjson_add_string dest \"$downzone\"\n\t\tjson_add_string family ipv6\n\t\tjson_add_string proto udp\n\t\tjson_add_string dest_ip \"ff00::/8\"\n\t\tjson_add_string target ACCEPT\n\t\tjson_close_object\n\tdone\n}\n\nservice_triggers() {\n\tLINKS=\"\"\n\n\tprocd_add_reload_trigger \"omcproxy\"\n\tconfig_foreach omcproxy_add_network_triggers proxy\n}\n\nstart_service() {\n\t. /lib/functions/network.sh\n\n\tconfig_load omcproxy\n\n\tconfig_foreach omcproxy_add_proxy proxy\n\t[ -n \"$PROXIES\" ] || return 0\n\n\tprocd_open_instance\n\tprocd_set_param command $PROG\n\t[ -n \"$OPTIONS\" ] && procd_append_param command $OPTIONS\n\tprocd_append_param command $PROXIES\n\tprocd_set_param respawn\n\n\tprocd_open_data\n\n\tjson_add_array firewall\n\tconfig_foreach omcproxy_add_firewall_rules proxy\n\tjson_close_array\n\n\tprocd_close_data\n\n\tprocd_close_instance\n\n\t# Increase maximum IPv4 group memberships per socket, default is 100.\n\techo 128 > /proc/sys/net/ipv4/igmp_max_memberships\n}\n\nservice_started() {\n\tprocd_set_config_changed firewall\n}\n\nstop_service() {\n\tprocd_set_config_changed firewall\n}\n"
  },
  {
    "path": "package/network/services/ppp/Makefile",
    "content": "#\n# Copyright (C) 2006-2015 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\ninclude $(INCLUDE_DIR)/kernel.mk\n\nPKG_NAME:=ppp\nPKG_RELEASE:=3\n\nPKG_SOURCE_PROTO:=git\nPKG_SOURCE_URL:=https://github.com/paulusmack/ppp\nPKG_SOURCE_DATE:=2021-01-04\nPKG_SOURCE_VERSION:=4fb319056f168bb8379865b91b4fd3e1ada73f1e\nPKG_MIRROR_HASH:=429cb5fcff36e1d8698766130711d4764347f08b83233dfb4831bea21616efef\nPKG_MAINTAINER:=Felix Fietkau <nbd@nbd.name>\nPKG_LICENSE:=BSD-4-Clause\nPKG_CPE_ID:=cpe:/a:samba:ppp\n\nPKG_RELEASE_VERSION:=2.4.9\nPKG_VERSION:=$(PKG_RELEASE_VERSION).git-$(PKG_SOURCE_DATE)\n\nPKG_BUILD_DEPENDS:=libpcap\n\nPKG_ASLR_PIE_REGULAR:=1\nPKG_BUILD_PARALLEL:=1\nPKG_INSTALL:=1\n\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine Package/ppp/Default\n  SECTION:=net\n  CATEGORY:=Network\n  URL:=https://ppp.samba.org/\nendef\n\ndefine Package/ppp\n$(call Package/ppp/Default)\n  DEPENDS:=+kmod-ppp\n  TITLE:=PPP daemon\n  VARIANT:=default\nendef\n\ndefine Package/ppp-multilink\n$(call Package/ppp/Default)\n  DEPENDS:=+kmod-ppp\n  TITLE:=PPP daemon (with multilink support)\n  VARIANT:=multilink\nendef\n\ndefine Package/ppp/description\nThis package contains the PPP (Point-to-Point Protocol) daemon.\nendef\n\ndefine Package/ppp/conffiles\n/etc/ppp/chap-secrets\n/etc/ppp/filter\n/etc/ppp/ip-down\n/etc/ppp/ip-up\n/etc/ppp/ipv6-down\n/etc/ppp/ipv6-up\n/etc/ppp/options\nendef\n\ndefine Package/ppp-mod-pppoa\n$(call Package/ppp/Default)\n  DEPENDS:=@(PACKAGE_ppp||PACKAGE_ppp-multilink) +linux-atm +kmod-pppoa\n  TITLE:=PPPoA plugin\nendef\n\ndefine Package/ppp-mod-pppoa/description\nThis package contains a PPPoA (PPP over ATM) plugin for ppp.\nendef\n\ndefine Package/ppp-mod-pppoe\n$(call Package/ppp/Default)\n  DEPENDS:=@(PACKAGE_ppp||PACKAGE_ppp-multilink) +kmod-pppoe\n  TITLE:=PPPoE plugin\nendef\n\ndefine Package/ppp-mod-pppoe/description\nThis package contains a PPPoE (PPP over Ethernet) plugin for ppp.\nendef\n\ndefine Package/ppp-mod-radius\n$(call Package/ppp/Default)\n  DEPENDS:=@(PACKAGE_ppp||PACKAGE_ppp-multilink)\n  TITLE:=RADIUS plugin\nendef\n\ndefine Package/ppp-mod-radius/description\nThis package contains a RADIUS (Remote Authentication Dial-In User Service)\nplugin for ppp.\nendef\n\ndefine Package/ppp-mod-radius/conffiles\n/etc/ppp/radius.conf\n/etc/ppp/radius/\nendef\n\ndefine Package/ppp-mod-pppol2tp\n$(call Package/ppp/Default)\n  DEPENDS:=@(PACKAGE_ppp||PACKAGE_ppp-multilink) +kmod-pppol2tp\n  TITLE:=PPPoL2TP plugin\nendef\n\ndefine Package/ppp-mod-pppol2tp/description\nThis package contains a PPPoL2TP (PPP over L2TP) plugin for ppp.\nendef\n\ndefine Package/ppp-mod-pptp\n$(call Package/ppp/Default)\n  DEPENDS:=@(PACKAGE_ppp||PACKAGE_ppp-multilink) +kmod-pptp +kmod-mppe +resolveip\n  TITLE:=PPtP plugin\nendef\n\ndefine Package/ppp-mod-pptp/description\nThis package contains a PPtP plugin for ppp.\nendef\n\ndefine Package/ppp-mod-passwordfd\n$(call Package/ppp/Default)\n  DEPENDS:=@(PACKAGE_ppp||PACKAGE_ppp-multilink)\n  TITLE:=pap/chap secret from filedescriptor\nendef\n\ndefine Package/ppp-mod-passwordfd/description\nThis package allows to pass the PAP/CHAP secret from a filedescriptor.\nEliminates the need for a secrets file.\nendef\n\ndefine Package/chat\n$(call Package/ppp/Default)\n  TITLE:=Establish conversation with a modem\nendef\n\ndefine Package/chat/description\nThis package contains an utility to establish conversation with other PPP servers\n(via a modem).\nendef\n\ndefine Package/pppdump\n$(call Package/ppp/Default)\n  DEPENDS:=@(PACKAGE_ppp||PACKAGE_ppp-multilink)\n  TITLE:=Read PPP record file\nendef\n\ndefine Package/pppdump/description\nThis package contains an utility to read PPP record file.\nendef\n\ndefine Package/pppstats\n$(call Package/ppp/Default)\n  DEPENDS:=@(PACKAGE_ppp||PACKAGE_ppp-multilink)\n  TITLE:=Report PPP statistics\nendef\n\ndefine Package/pppstats/description\nThis package contains an utility to report PPP statistics.\nendef\n\ndefine Package/pppoe-discovery\n$(call Package/ppp/Default)\n  DEPENDS:=@(PACKAGE_ppp||PACKAGE_ppp-multilink) +ppp-mod-pppoe\n  TITLE:=Perform a PPPoE-discovery process\nendef\n\ndefine Package/pppoe-discovery/description\nThis tool performs the same discovery process as pppoe, but does\nnot initiate a session. Can be useful to debug pppoe.\nendef\n\n\ndefine Build/Configure\n$(call Build/Configure/Default,, \\\n\tUNAME_S=\"Linux\" \\\n\tUNAME_R=\"$(LINUX_VERSION)\" \\\n\tUNAME_M=\"$(ARCH)\" \\\n)\n\tmkdir -p $(PKG_BUILD_DIR)/pppd/plugins/pppoatm/linux\n\t$(CP) \\\n\t\t$(LINUX_DIR)/include/linux/compiler.h \\\n\t\t$(LINUX_DIR)/include/$(LINUX_UAPI_DIR)linux/atm*.h \\\n\t\t$(PKG_BUILD_DIR)/pppd/plugins/pppoatm/linux/\n\n\t# Kernel 4.14.9+ only, ignore the exit status of cp in case the file\n\t# doesn't exits\n\t-$(CP) $(LINUX_DIR)/include/linux/compiler_types.h \\\n\t\t$(PKG_BUILD_DIR)/pppd/plugins/pppoatm/linux/\nendef\n\nTARGET_CFLAGS += -ffunction-sections -fdata-sections -flto\nTARGET_LDFLAGS += -Wl,--gc-sections -flto -fuse-linker-plugin\n\nMAKE_FLAGS += COPTS=\"$(TARGET_CFLAGS)\" \\\n\t\tPRECOMPILED_FILTER=1 \\\n\t\tSTAGING_DIR=\"$(STAGING_DIR)\"\n\nifeq ($(BUILD_VARIANT),multilink)\n  MAKE_FLAGS += HAVE_MULTILINK=y\nelse\n  MAKE_FLAGS += HAVE_MULTILINK=\nendif\n\nifdef CONFIG_USE_MUSL\n  MAKE_FLAGS += USE_LIBUTIL=\nendif\n\ndefine Build/InstallDev\n\t$(INSTALL_DIR) $(1)/usr/include\n\t$(CP) $(PKG_INSTALL_DIR)/include/pppd $(1)/usr/include/\nendef\n\ndefine Package/ppp/script_install\nendef\n\ndefine Package/ppp/install\n\t$(INSTALL_DIR) $(1)/usr/lib/pppd/$(PKG_RELEASE_VERSION)\n\t$(INSTALL_DIR) $(1)/usr/sbin\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/sbin/pppd $(1)/usr/sbin/\n\t$(INSTALL_DIR) $(1)/etc/ppp\n\t$(INSTALL_CONF) ./files/etc/ppp/chap-secrets $(1)/etc/ppp/\n\t$(INSTALL_DATA) ./files/etc/ppp/filter $(1)/etc/ppp/\n\t$(INSTALL_DATA) ./files/etc/ppp/options $(1)/etc/ppp/\n\t$(LN) /tmp/resolv.conf.ppp $(1)/etc/ppp/resolv.conf\n\t$(INSTALL_DIR) $(1)/lib/netifd/proto\n\t$(INSTALL_BIN) ./files/ppp.sh $(1)/lib/netifd/proto/\n\t$(INSTALL_BIN) ./files/lib/netifd/ppp-up $(1)/lib/netifd/\n\t$(INSTALL_BIN) ./files/lib/netifd/ppp6-up $(1)/lib/netifd/\n\t$(INSTALL_BIN) ./files/lib/netifd/ppp-down $(1)/lib/netifd/\nendef\nPackage/ppp-multilink/install=$(Package/ppp/install)\n\ndefine Package/ppp-mod-pppoa/install\n\t$(INSTALL_DIR) $(1)/usr/lib/pppd/$(PKG_RELEASE_VERSION)\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/lib/pppd/$(PKG_RELEASE_VERSION)/pppoatm.so \\\n\t\t$(1)/usr/lib/pppd/$(PKG_RELEASE_VERSION)/\nendef\n\ndefine Package/ppp-mod-pppoe/install\n\t$(INSTALL_DIR) $(1)/usr/lib/pppd/$(PKG_RELEASE_VERSION)\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/lib/pppd/$(PKG_RELEASE_VERSION)/pppoe.so \\\n\t\t$(1)/usr/lib/pppd/$(PKG_RELEASE_VERSION)/\nendef\n\ndefine Package/ppp-mod-radius/install\n\t$(INSTALL_DIR) $(1)/usr/lib/pppd/$(PKG_RELEASE_VERSION)\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/lib/pppd/$(PKG_RELEASE_VERSION)/radius.so \\\n\t\t$(1)/usr/lib/pppd/$(PKG_RELEASE_VERSION)/\n\t$(INSTALL_DIR) $(1)/etc/ppp\n\t$(INSTALL_DATA) ./files/etc/ppp/radius.conf $(1)/etc/ppp/\n\t$(INSTALL_DIR) $(1)/etc/ppp/radius\n\t$(INSTALL_DATA) ./files/etc/ppp/radius/dictionary* \\\n\t\t$(1)/etc/ppp/radius/\n\t$(INSTALL_CONF) ./files/etc/ppp/radius/servers \\\n\t\t$(1)/etc/ppp/radius/\nendef\n\ndefine Package/ppp-mod-pppol2tp/install\n\t$(INSTALL_DIR) $(1)/usr/lib/pppd/$(PKG_RELEASE_VERSION)\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/lib/pppd/$(PKG_RELEASE_VERSION)/pppol2tp.so \\\n\t\t$(1)/usr/lib/pppd/$(PKG_RELEASE_VERSION)/\nendef\n\ndefine Package/ppp-mod-pptp/install\n\t$(INSTALL_DIR) $(1)/usr/lib/pppd/$(PKG_RELEASE_VERSION)\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/lib/pppd/$(PKG_RELEASE_VERSION)/pptp.so \\\n\t\t$(1)/usr/lib/pppd/$(PKG_RELEASE_VERSION)/\n\t$(INSTALL_DIR) $(1)/etc/ppp\n\t$(INSTALL_DATA) ./files/etc/ppp/options.pptp $(1)/etc/ppp/\nendef\n\ndefine Package/ppp-mod-passwordfd/install\n\t$(INSTALL_DIR) $(1)/usr/lib/pppd/$(PKG_RELEASE_VERSION)\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/lib/pppd/$(PKG_RELEASE_VERSION)/passwordfd.so \\\n\t\t$(1)/usr/lib/pppd/$(PKG_RELEASE_VERSION)/\nendef\n\ndefine Package/chat/install\n\t$(INSTALL_DIR) $(1)/usr/sbin\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/sbin/chat $(1)/usr/sbin/\nendef\n\ndefine Package/pppdump/install\n\t$(INSTALL_DIR) $(1)/usr/sbin\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/sbin/pppdump $(1)/usr/sbin/\nendef\n\ndefine Package/pppstats/install\n\t$(INSTALL_DIR) $(1)/usr/sbin\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/sbin/pppstats $(1)/usr/sbin/\nendef\n\ndefine Package/pppoe-discovery/install\n\t$(INSTALL_DIR) $(1)/usr/sbin\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/sbin/pppoe-discovery $(1)/usr/sbin/\nendef\n\n$(eval $(call BuildPackage,ppp))\n$(eval $(call BuildPackage,ppp-multilink))\n$(eval $(call BuildPackage,ppp-mod-pppoa))\n$(eval $(call BuildPackage,ppp-mod-pppoe))\n$(eval $(call BuildPackage,ppp-mod-radius))\n$(eval $(call BuildPackage,ppp-mod-pppol2tp))\n$(eval $(call BuildPackage,ppp-mod-pptp))\n$(eval $(call BuildPackage,ppp-mod-passwordfd))\n$(eval $(call BuildPackage,chat))\n$(eval $(call BuildPackage,pppdump))\n$(eval $(call BuildPackage,pppstats))\n$(eval $(call BuildPackage,pppoe-discovery))\n"
  },
  {
    "path": "package/network/services/ppp/files/etc/ppp/chap-secrets",
    "content": "#USERNAME  PROVIDER  PASSWORD  IPADDRESS\n"
  },
  {
    "path": "package/network/services/ppp/files/etc/ppp/filter",
    "content": "#\n# Expression: outbound and not icmp[0] != 8 and not tcp[13] & 4 != 0\n#\n19\n48 0 0 0\n21 0 16 1\n40 0 0 2\n21 0 13 33\n48 0 0 13\n21 0 5 1\n40 0 0 10\n69 9 0 8191\n177 0 0 4\n80 0 0 4\n21 6 7 8\n21 0 5 6\n40 0 0 10\n69 3 0 8191\n177 0 0 4\n80 0 0 17\n69 1 0 4\n6 0 0 4\n6 0 0 0\n"
  },
  {
    "path": "package/network/services/ppp/files/etc/ppp/options",
    "content": "#debug\nlogfile /dev/null\nnoipdefault\nnoaccomp\nnopcomp\nnocrtscts\nlock\nmaxfail 0\n"
  },
  {
    "path": "package/network/services/ppp/files/etc/ppp/options.pptp",
    "content": "noipdefault\nnoauth\nnobsdcomp\nnodeflate\nidle 0\nmppe required,no40,no56,stateless\nmaxfail 0\n"
  },
  {
    "path": "package/network/services/ppp/files/etc/ppp/radius/dictionary",
    "content": "#\n# Updated 97/06/13 to livingston-radius-2.01 miquels@cistron.nl\n#\n#\tThis file contains dictionary translations for parsing\n#\trequests and generating responses.  All transactions are\n#\tcomposed of Attribute/Value Pairs.  The value of each attribute\n#\tis specified as one of 4 data types.  Valid data types are:\n#\n#\tstring - 0-253 octets\n#\tipaddr - 4 octets in network byte order\n#\tinteger - 32 bit value in big endian order (high byte first)\n#\tdate - 32 bit value in big endian order - seconds since\n#\t\t\t\t\t00:00:00 GMT,  Jan.  1,  1970\n#\n#\tEnumerated values are stored in the user file with dictionary\n#\tVALUE translations for easy administration.\n#\n#\tExample:\n#\n#\tATTRIBUTE\t  VALUE\n#\t---------------   -----\n#\tFramed-Protocol = PPP\n#\t7\t\t= 1\t(integer encoding)\n#\n\n# The dictionary format now supports vendor-specific attributes.\n# Vendors are introduced like this:\n#\n#\tVENDOR vendor_name vendor_number\n#\n# For example:\n#\n#\tVENDOR RoaringPenguin 10055\n#\n# Vendor-specific attributes have a fifth field with the name of the\n# vendor.  For example:\n#\n#       ATTRIBUTE RP-Upstream-Speed-Limit 1 integer RoaringPenguin\n#\n# introduces a Roaring Penguin vendor-specific attribbute with name\n# RP-Upstream-Speed-Limit, number 1, type integer and vendor RoaringPenguin.\n\n#\n#\tFollowing are the proper new names. Use these.\n#\nATTRIBUTE\tUser-Name\t\t1\tstring\nATTRIBUTE\tPassword\t\t2\tstring\nATTRIBUTE\tCHAP-Password\t\t3\tstring\nATTRIBUTE\tNAS-IP-Address\t\t4\tipaddr\nATTRIBUTE\tNAS-Port-Id\t\t5\tinteger\nATTRIBUTE\tService-Type\t\t6\tinteger\nATTRIBUTE\tFramed-Protocol\t\t7\tinteger\nATTRIBUTE\tFramed-IP-Address\t8\tipaddr\nATTRIBUTE\tFramed-IP-Netmask\t9\tipaddr\nATTRIBUTE\tFramed-Routing\t\t10\tinteger\nATTRIBUTE\tFilter-Id\t\t11\tstring\nATTRIBUTE\tFramed-MTU\t\t12\tinteger\nATTRIBUTE\tFramed-Compression\t13\tinteger\nATTRIBUTE\tLogin-IP-Host\t\t14\tipaddr\nATTRIBUTE\tLogin-Service\t\t15\tinteger\nATTRIBUTE\tLogin-TCP-Port\t\t16\tinteger\nATTRIBUTE\tReply-Message\t\t18\tstring\nATTRIBUTE\tCallback-Number\t\t19\tstring\nATTRIBUTE\tCallback-Id\t\t20\tstring\nATTRIBUTE\tFramed-Route\t\t22\tstring\nATTRIBUTE\tFramed-IPX-Network\t23\tipaddr\nATTRIBUTE\tState\t\t\t24\tstring\nATTRIBUTE\tClass\t\t\t25\tstring\nATTRIBUTE\tSession-Timeout\t\t27\tinteger\nATTRIBUTE\tIdle-Timeout\t\t28\tinteger\nATTRIBUTE\tTermination-Action\t29\tinteger\nATTRIBUTE\tCalled-Station-Id\t30\tstring\nATTRIBUTE\tCalling-Station-Id\t31\tstring\nATTRIBUTE\tNAS-Identifier\t\t32\tstring\nATTRIBUTE\tAcct-Status-Type\t40\tinteger\nATTRIBUTE\tAcct-Delay-Time\t\t41\tinteger\nATTRIBUTE\tAcct-Input-Octets\t42\tinteger\nATTRIBUTE\tAcct-Output-Octets\t43\tinteger\nATTRIBUTE\tAcct-Session-Id\t\t44\tstring\nATTRIBUTE\tAcct-Authentic\t\t45\tinteger\nATTRIBUTE\tAcct-Session-Time\t46\tinteger\nATTRIBUTE\tAcct-Input-Packets\t47\tinteger\nATTRIBUTE\tAcct-Output-Packets\t48\tinteger\nATTRIBUTE\tAcct-Terminate-Cause\t49\tinteger\nATTRIBUTE\tChap-Challenge\t\t60\tstring\nATTRIBUTE\tNAS-Port-Type\t\t61\tinteger\nATTRIBUTE\tPort-Limit\t\t62\tinteger\nATTRIBUTE\tConnect-Info\t\t77\tstring\n\n# RFC 2869\nATTRIBUTE\tAcct-Interim-Interval\t85\tinteger\n\n#\n#\tExperimental Non Protocol Attributes used by Cistron-Radiusd\n#\nATTRIBUTE\tHuntgroup-Name\t\t221\tstring\nATTRIBUTE\tUser-Category\t\t1029\tstring\nATTRIBUTE\tGroup-Name\t\t1030\tstring\nATTRIBUTE\tSimultaneous-Use\t1034\tinteger\nATTRIBUTE\tStrip-User-Name\t\t1035\tinteger\nATTRIBUTE\tFall-Through\t\t1036\tinteger\nATTRIBUTE\tAdd-Port-To-IP-Address\t1037\tinteger\nATTRIBUTE\tExec-Program\t\t1038\tstring\nATTRIBUTE\tExec-Program-Wait\t1039\tstring\nATTRIBUTE\tHint\t\t\t1040\tstring\n\n#\n#\tNon-Protocol Attributes\n#\tThese attributes are used internally by the server\n#\nATTRIBUTE\tExpiration\t\t  21\tdate\nATTRIBUTE\tAuth-Type\t\t1000\tinteger\nATTRIBUTE\tMenu\t\t\t1001\tstring\nATTRIBUTE\tTermination-Menu\t1002\tstring\nATTRIBUTE\tPrefix\t\t\t1003\tstring\nATTRIBUTE\tSuffix\t\t\t1004\tstring\nATTRIBUTE\tGroup\t\t\t1005\tstring\nATTRIBUTE\tCrypt-Password\t\t1006\tstring\nATTRIBUTE\tConnect-Rate\t\t1007\tinteger\n\n#\n#       Experimental, implementation specific attributes\n#\n# Limit session traffic\nATTRIBUTE\tSession-Octets-Limit\t227\tinteger\n# What to assume as limit - 0 in+out, 1 in, 2 out, 3 max(in,out)\nATTRIBUTE\tOctets-Direction\t228\tinteger\n\n#\n#\tInteger Translations\n#\n\n#\tUser Types\n\nVALUE\t\tService-Type\t\tLogin-User\t\t1\nVALUE\t\tService-Type\t\tFramed-User\t\t2\nVALUE\t\tService-Type\t\tCallback-Login-User\t3\nVALUE\t\tService-Type\t\tCallback-Framed-User\t4\nVALUE\t\tService-Type\t\tOutbound-User\t\t5\nVALUE\t\tService-Type\t\tAdministrative-User\t6\nVALUE\t\tService-Type\t\tNAS-Prompt-User\t\t7\n\n#\tFramed Protocols\n\nVALUE\t\tFramed-Protocol\t\tPPP\t\t\t1\nVALUE\t\tFramed-Protocol\t\tSLIP\t\t\t2\n\n#\tFramed Routing Values\n\nVALUE\t\tFramed-Routing\t\tNone\t\t\t0\nVALUE\t\tFramed-Routing\t\tBroadcast\t\t1\nVALUE\t\tFramed-Routing\t\tListen\t\t\t2\nVALUE\t\tFramed-Routing\t\tBroadcast-Listen\t3\n\n#\tFramed Compression Types\n\nVALUE\t\tFramed-Compression\tNone\t\t\t0\nVALUE\t\tFramed-Compression\tVan-Jacobson-TCP-IP\t1\n\n#\tLogin Services\n\nVALUE\t\tLogin-Service\t\tTelnet\t\t\t0\nVALUE\t\tLogin-Service\t\tRlogin\t\t\t1\nVALUE\t\tLogin-Service\t\tTCP-Clear\t\t2\nVALUE\t\tLogin-Service\t\tPortMaster\t\t3\n\n#\tStatus Types\n\nVALUE\t\tAcct-Status-Type\tStart\t\t\t1\nVALUE\t\tAcct-Status-Type\tStop\t\t\t2\nVALUE\t\tAcct-Status-Type\tAccounting-On\t\t7\nVALUE\t\tAcct-Status-Type\tAccounting-Off\t\t8\n\n#\tAuthentication Types\n\nVALUE\t\tAcct-Authentic\t\tRADIUS\t\t\t1\nVALUE\t\tAcct-Authentic\t\tLocal\t\t\t2\nVALUE\t\tAcct-Authentic\t\tPowerLink128\t\t100\n\n#\tTermination Options\n\nVALUE\t\tTermination-Action\tDefault\t\t\t0\nVALUE\t\tTermination-Action\tRADIUS-Request\t\t1\n\n#\tNAS Port Types, available in 3.3.1 and later\n\nVALUE\t\tNAS-Port-Type\t\tAsync\t\t\t0\nVALUE\t\tNAS-Port-Type\t\tSync\t\t\t1\nVALUE\t\tNAS-Port-Type\t\tISDN\t\t\t2\nVALUE\t\tNAS-Port-Type\t\tISDN-V120\t\t3\nVALUE\t\tNAS-Port-Type\t\tISDN-V110\t\t4\n\n#\tAcct Terminate Causes, available in 3.3.2 and later\n\nVALUE           Acct-Terminate-Cause    User-Request            1\nVALUE           Acct-Terminate-Cause    Lost-Carrier            2\nVALUE           Acct-Terminate-Cause    Lost-Service            3\nVALUE           Acct-Terminate-Cause    Idle-Timeout            4\nVALUE           Acct-Terminate-Cause    Session-Timeout         5\nVALUE           Acct-Terminate-Cause    Admin-Reset             6\nVALUE           Acct-Terminate-Cause    Admin-Reboot            7\nVALUE           Acct-Terminate-Cause    Port-Error              8\nVALUE           Acct-Terminate-Cause    NAS-Error               9\nVALUE           Acct-Terminate-Cause    NAS-Request             10\nVALUE           Acct-Terminate-Cause    NAS-Reboot              11\nVALUE           Acct-Terminate-Cause    Port-Unneeded           12\nVALUE           Acct-Terminate-Cause    Port-Preempted          13\nVALUE           Acct-Terminate-Cause    Port-Suspended          14\nVALUE           Acct-Terminate-Cause    Service-Unavailable     15\nVALUE           Acct-Terminate-Cause    Callback                16\nVALUE           Acct-Terminate-Cause    User-Error              17\nVALUE           Acct-Terminate-Cause    Host-Request            18\n\n#\n#\tNon-Protocol Integer Translations\n#\n\nVALUE\t\tAuth-Type\t\tLocal\t\t\t0\nVALUE\t\tAuth-Type\t\tSystem\t\t\t1\nVALUE\t\tAuth-Type\t\tSecurID\t\t\t2\nVALUE\t\tAuth-Type\t\tCrypt-Local\t\t3\nVALUE\t\tAuth-Type\t\tReject\t\t\t4\n\n#\n#\tCistron extensions\n#\nVALUE\t\tAuth-Type\t\tPam\t\t\t253\nVALUE\t\tAuth-Type\t\tNone\t\t\t254\n\n#\n#\tExperimental Non-Protocol Integer Translations for Cistron-Radiusd\n#\nVALUE\t\tFall-Through\t\tNo\t\t\t0\nVALUE\t\tFall-Through\t\tYes\t\t\t1\nVALUE\t\tAdd-Port-To-IP-Address\tNo\t\t\t0\nVALUE\t\tAdd-Port-To-IP-Address\tYes\t\t\t1\n\n#\n#\tConfiguration Values\n#\tuncomment these two lines to turn account expiration on\n#\n\n#VALUE\t\tServer-Config\t\tPassword-Expiration\t30\n#VALUE\t\tServer-Config\t\tPassword-Warning\t5\n\n#       Octets-Direction\nVALUE\t\tOctets-Direction        Sum\t\t\t0\nVALUE\t\tOctets-Direction        Input\t\t\t1\nVALUE\t\tOctets-Direction        Output\t\t\t2\nVALUE\t\tOctets-Direction        MaxOveral\t\t3\nVALUE\t\tOctets-Direction        MaxSession\t\t4\n\nINCLUDE /etc/ppp/radius/dictionary.microsoft\n"
  },
  {
    "path": "package/network/services/ppp/files/etc/ppp/radius/dictionary.asnet",
    "content": "VENDOR\t\tASNET\t\t50000\nATTRIBUTE\tSpeed-Down\t\t1\tstring\tASNET\nATTRIBUTE\tSpeed-Up\t\t2\tstring\tASNET\n"
  },
  {
    "path": "package/network/services/ppp/files/etc/ppp/radius/dictionary.microsoft",
    "content": "#\n#\tMicrosoft's VSA's, from RFC 2548\n#\n#\n\nVENDOR\t\tMicrosoft\t311\tMicrosoft\n\nATTRIBUTE\tMS-CHAP-Response\t1\tstring\tMicrosoft\nATTRIBUTE\tMS-CHAP-Error\t\t2\tstring\tMicrosoft\nATTRIBUTE\tMS-CHAP-CPW-1\t\t3\tstring\tMicrosoft\nATTRIBUTE\tMS-CHAP-CPW-2\t\t4\tstring\tMicrosoft\nATTRIBUTE\tMS-CHAP-LM-Enc-PW\t5\tstring\tMicrosoft\nATTRIBUTE\tMS-CHAP-NT-Enc-PW\t6\tstring\tMicrosoft\nATTRIBUTE\tMS-MPPE-Encryption-Policy 7\tstring\tMicrosoft\n# This is referred to as both singular and plural in the RFC.\n# Plural seems to make more sense.\nATTRIBUTE\tMS-MPPE-Encryption-Type 8\tstring\tMicrosoft\nATTRIBUTE\tMS-MPPE-Encryption-Types  8\tstring\tMicrosoft\nATTRIBUTE\tMS-RAS-Vendor\t\t9\tinteger\tMicrosoft\nATTRIBUTE\tMS-CHAP-Domain\t\t10\tstring\tMicrosoft\nATTRIBUTE\tMS-CHAP-Challenge\t11\tstring\tMicrosoft\nATTRIBUTE\tMS-CHAP-MPPE-Keys\t12\tstring\tMicrosoft\nATTRIBUTE\tMS-BAP-Usage\t\t13\tinteger\tMicrosoft\nATTRIBUTE\tMS-Link-Utilization-Threshold 14 integer\tMicrosoft\nATTRIBUTE\tMS-Link-Drop-Time-Limit\t15\tinteger\tMicrosoft\nATTRIBUTE\tMS-MPPE-Send-Key\t16\tstring\tMicrosoft\nATTRIBUTE\tMS-MPPE-Recv-Key\t17\tstring\tMicrosoft\nATTRIBUTE\tMS-RAS-Version\t\t18\tstring\tMicrosoft\nATTRIBUTE\tMS-Old-ARAP-Password\t19\tstring\tMicrosoft\nATTRIBUTE\tMS-New-ARAP-Password\t20\tstring\tMicrosoft\nATTRIBUTE\tMS-ARAP-PW-Change-Reason 21\tinteger\tMicrosoft\n\nATTRIBUTE\tMS-Filter\t\t22\tstring\tMicrosoft\nATTRIBUTE\tMS-Acct-Auth-Type\t23\tinteger\tMicrosoft\nATTRIBUTE\tMS-Acct-EAP-Type\t24\tinteger\tMicrosoft\n\nATTRIBUTE\tMS-CHAP2-Response\t25\tstring\tMicrosoft\nATTRIBUTE\tMS-CHAP2-Success\t26\tstring\tMicrosoft\nATTRIBUTE\tMS-CHAP2-CPW\t\t27\tstring\tMicrosoft\n\nATTRIBUTE\tMS-Primary-DNS-Server\t28\tipaddr\tMicrosoft\nATTRIBUTE\tMS-Secondary-DNS-Server\t29\tipaddr\tMicrosoft\nATTRIBUTE\tMS-Primary-NBNS-Server\t30\tipaddr\tMicrosoft\nATTRIBUTE\tMS-Secondary-NBNS-Server 31\tipaddr\tMicrosoft\n\n#ATTRIBUTE\tMS-ARAP-Challenge\t33\tstring\tMicrosoft\n\n\n#\n#\tInteger Translations\n#\n\n#\tMS-BAP-Usage Values\n\nVALUE\t\tMS-BAP-Usage\t\tNot-Allowed\t0\nVALUE\t\tMS-BAP-Usage\t\tAllowed\t\t1\nVALUE\t\tMS-BAP-Usage\t\tRequired\t2\n\n#\tMS-ARAP-Password-Change-Reason Values\n\nVALUE\tMS-ARAP-PW-Change-Reason\tJust-Change-Password\t\t1\nVALUE\tMS-ARAP-PW-Change-Reason\tExpired-Password\t\t2\nVALUE\tMS-ARAP-PW-Change-Reason\tAdmin-Requires-Password-Change\t3\nVALUE\tMS-ARAP-PW-Change-Reason\tPassword-Too-Short\t\t4\n\n#\tMS-Acct-Auth-Type Values\n\nVALUE\t\tMS-Acct-Auth-Type\tPAP\t\t1\nVALUE\t\tMS-Acct-Auth-Type\tCHAP\t\t2\nVALUE\t\tMS-Acct-Auth-Type\tMS-CHAP-1\t3\nVALUE\t\tMS-Acct-Auth-Type\tMS-CHAP-2\t4\nVALUE\t\tMS-Acct-Auth-Type\tEAP\t\t5\n\n#\tMS-Acct-EAP-Type Values\n\nVALUE\t\tMS-Acct-EAP-Type\tMD5\t\t4\nVALUE\t\tMS-Acct-EAP-Type\tOTP\t\t5\nVALUE\t\tMS-Acct-EAP-Type\tGeneric-Token-Card\t6\nVALUE\t\tMS-Acct-EAP-Type\tTLS\t\t13\n\n"
  },
  {
    "path": "package/network/services/ppp/files/etc/ppp/radius/servers",
    "content": "# SERVER SECRET\nlocalhost secret\n"
  },
  {
    "path": "package/network/services/ppp/files/etc/ppp/radius.conf",
    "content": "authserver localhost:1812\nacctserver localhost:1813\ndictionary /etc/ppp/radius/dictionary\nservers /etc/ppp/radius/servers\nmapfile /dev/null\nseqfile /tmp/radius.seq\nradius_timeout 5\nradius_retries 3\n"
  },
  {
    "path": "package/network/services/ppp/files/lib/netifd/ppp-down",
    "content": "#!/bin/sh\nPPP_IPPARAM=\"$6\"\n\n. /lib/netifd/netifd-proto.sh\nproto_init_update \"$IFNAME\" 0\nproto_send_update \"$PPP_IPPARAM\"\n\n[ -d /etc/ppp/ip-down.d ] && {\n\tfor SCRIPT in /etc/ppp/ip-down.d/*\n\tdo\n\t\t[ -x \"$SCRIPT\" ] && \"$SCRIPT\" \"$@\"\n\tdone\n}\n"
  },
  {
    "path": "package/network/services/ppp/files/lib/netifd/ppp-up",
    "content": "#!/bin/sh\nPPP_IPPARAM=\"$6\"\n\n. /lib/netifd/netifd-proto.sh\nproto_init_update \"$IFNAME\" 1 1\nproto_set_keep 1\n[ -n \"$PPP_IPPARAM\" ] && {\n\t[ -n \"$IPLOCAL\" ] && proto_add_ipv4_address \"$IPLOCAL\" 32 \"\" \"${IPREMOTE:-2.2.2.2}\"\n\t[ -n \"$IPREMOTE\" ] && proto_add_ipv4_route 0.0.0.0 0 \"$IPREMOTE\"\n\t[ -n \"$DNS1\" ] && proto_add_dns_server \"$DNS1\"\n\t[ -n \"$DNS2\" -a \"$DNS1\" != \"$DNS2\" ] && proto_add_dns_server \"$DNS2\"\n}\nproto_send_update \"$PPP_IPPARAM\"\n\n[ -d /etc/ppp/ip-up.d ] && {\n\tfor SCRIPT in /etc/ppp/ip-up.d/*\n\tdo\n\t\t[ -x \"$SCRIPT\" ] && \"$SCRIPT\" \"$@\"\n\tdone\n}\n"
  },
  {
    "path": "package/network/services/ppp/files/lib/netifd/ppp6-up",
    "content": "#!/bin/sh\nPPP_IPPARAM=\"$6\"\n\n. /lib/netifd/netifd-proto.sh\nproto_init_update \"$IFNAME\" 1 1\nproto_set_keep 1\n[ -n \"$PPP_IPPARAM\" ] && {\n\t[ -n \"$LLLOCAL\" ] && proto_add_ipv6_address \"$LLLOCAL\" 128\n}\nproto_send_update \"$PPP_IPPARAM\"\n\n[ -d /etc/ppp/ip-up.d ] && {\n\tfor SCRIPT in /etc/ppp/ip-up.d/*\n\tdo\n\t\t[ -x \"$SCRIPT\" ] && \"$SCRIPT\" \"$@\"\n\tdone\n}\n\nif [ -n \"$AUTOIPV6\" ]; then\n\tZONE=$(fw3 -q network $PPP_IPPARAM 2>/dev/null)\n\n\tjson_init\n\tjson_add_string name \"${PPP_IPPARAM}_6\"\n\tjson_add_string ifname \"@$PPP_IPPARAM\"\n\tjson_add_string proto \"dhcpv6\"\n\t[ -n \"$ZONE\" ] && json_add_string zone \"$ZONE\"\n\t[ -n \"$EXTENDPREFIX\" ] && json_add_string extendprefix 1\n\t[ -n \"$IP6TABLE\" ] && json_add_string ip6table $IP6TABLE\n\t[ -n \"$PEERDNS\" ] && json_add_boolean peerdns $PEERDNS\n\tjson_close_object\n\tubus call network add_dynamic \"$(json_dump)\"\nfi\n"
  },
  {
    "path": "package/network/services/ppp/files/ppp.sh",
    "content": "#!/bin/sh\n\n[ -x /usr/sbin/pppd ] || exit 0\n\n[ -n \"$INCLUDE_ONLY\" ] || {\n\t. /lib/functions.sh\n\t. /lib/functions/network.sh\n\t. ../netifd-proto.sh\n\tinit_proto \"$@\"\n}\n\nppp_select_ipaddr()\n{\n\tlocal subnets=$1\n\tlocal res\n\tlocal res_mask\n\n\tfor subnet in $subnets; do\n\t\tlocal addr=\"${subnet%%/*}\"\n\t\tlocal mask=\"${subnet#*/}\"\n\n\t\tif [ -n \"$res_mask\" -a \"$mask\" != 32 ]; then\n\t\t\t[ \"$mask\" -gt \"$res_mask\" ] || [ \"$res_mask\" = 32 ] && {\n\t\t\t\tres=\"$addr\"\n\t\t\t\tres_mask=\"$mask\"\n\t\t\t}\n\t\telif [ -z \"$res_mask\" ]; then\n\t\t\tres=\"$addr\"\n\t\t\tres_mask=\"$mask\"\n\t\tfi\n\tdone\n\n\techo \"$res\"\n}\n\nppp_exitcode_tostring()\n{\n\tlocal errorcode=$1\n\t[ -n \"$errorcode\" ] || errorcode=5\n\n\tcase \"$errorcode\" in\n\t\t0) echo \"OK\" ;;\n\t\t1) echo \"FATAL_ERROR\" ;;\n\t\t2) echo \"OPTION_ERROR\" ;;\n\t\t3) echo \"NOT_ROOT\" ;;\n\t\t4) echo \"NO_KERNEL_SUPPORT\" ;;\n\t\t5) echo \"USER_REQUEST\" ;;\n\t\t6) echo \"LOCK_FAILED\" ;;\n\t\t7) echo \"OPEN_FAILED\" ;;\n\t\t8) echo \"CONNECT_FAILED\" ;;\n\t\t9) echo \"PTYCMD_FAILED\" ;;\n\t\t10) echo \"NEGOTIATION_FAILED\" ;;\n\t\t11) echo \"PEER_AUTH_FAILED\" ;;\n\t\t12) echo \"IDLE_TIMEOUT\" ;;\n\t\t13) echo \"CONNECT_TIME\" ;;\n\t\t14) echo \"CALLBACK\" ;;\n\t\t15) echo \"PEER_DEAD\" ;;\n\t\t16) echo \"HANGUP\" ;;\n\t\t17) echo \"LOOPBACK\" ;;\n\t\t18) echo \"INIT_FAILED\" ;;\n\t\t19) echo \"AUTH_TOPEER_FAILED\" ;;\n\t\t20) echo \"TRAFFIC_LIMIT\" ;;\n\t\t21) echo \"CNID_AUTH_FAILED\";;\n\t\t*) echo \"UNKNOWN_ERROR\" ;;\n\tesac\n}\n\nppp_generic_init_config() {\n\tproto_config_add_string username\n\tproto_config_add_string password\n\tproto_config_add_string keepalive\n\tproto_config_add_boolean keepalive_adaptive\n\tproto_config_add_int demand\n\tproto_config_add_string pppd_options\n\tproto_config_add_string 'connect:file'\n\tproto_config_add_string 'disconnect:file'\n\t[ -e /proc/sys/net/ipv6 ] && proto_config_add_string ipv6\n\tproto_config_add_boolean authfail\n\tproto_config_add_int mtu\n\tproto_config_add_string pppname\n\tproto_config_add_string unnumbered\n\tproto_config_add_boolean persist\n\tproto_config_add_int maxfail\n\tproto_config_add_int holdoff\n}\n\nppp_generic_setup() {\n\tlocal config=\"$1\"; shift\n\tlocal localip\n\n\tjson_get_vars ip6table demand keepalive keepalive_adaptive username password pppd_options pppname unnumbered persist maxfail holdoff peerdns\n\n\t[ ! -e /proc/sys/net/ipv6 ] && ipv6=0 || json_get_var ipv6 ipv6\n\n\tif [ \"$ipv6\" = 0 ]; then\n\t\tipv6=\"\"\n\telif [ -z \"$ipv6\" -o \"$ipv6\" = auto ]; then\n\t\tipv6=1\n\t\tautoipv6=1\n\tfi\n\n\tif [ \"${demand:-0}\" -gt 0 ]; then\n\t\tdemand=\"precompiled-active-filter /etc/ppp/filter demand idle $demand\"\n\telse\n\t\tdemand=\"\"\n\tfi\n\tif [ -n \"$persist\" ]; then\n\t\t[ \"${persist}\" -lt 1 ] && persist=\"nopersist\" || persist=\"persist\"\n\tfi\n\tif [ -z \"$maxfail\" ]; then\n\t\t[ \"$persist\" = \"persist\" ] && maxfail=0 || maxfail=1\n\tfi\n\t[ -n \"$mtu\" ] || json_get_var mtu mtu\n\t[ -n \"$pppname\" ] || pppname=\"${proto:-ppp}-$config\"\n\t[ -n \"$unnumbered\" ] && {\n\t\tlocal subnets\n\t\t( proto_add_host_dependency \"$config\" \"\" \"$unnumbered\" )\n\t\tnetwork_get_subnets subnets \"$unnumbered\"\n\t\tlocalip=$(ppp_select_ipaddr \"$subnets\")\n\t\t[ -n \"$localip\" ] || {\n\t\t\tproto_block_restart \"$config\"\n\t\t\treturn\n\t\t}\n\t}\n\n\t[ -n \"$keepalive\" ] || keepalive=\"5 1\"\n\n\tlocal lcp_failure=\"${keepalive%%[, ]*}\"\n\tlocal lcp_interval=\"${keepalive##*[, ]}\"\n\tlocal lcp_adaptive=\"lcp-echo-adaptive\"\n\t[ \"${lcp_failure:-0}\" -lt 1 ] && lcp_failure=\"\"\n\t[ \"$lcp_interval\" != \"$keepalive\" ] || lcp_interval=5\n\t[ \"${keepalive_adaptive:-1}\" -lt 1 ] && lcp_adaptive=\"\"\n\t[ -n \"$connect\" ] || json_get_var connect connect\n\t[ -n \"$disconnect\" ] || json_get_var disconnect disconnect\n\n\tproto_run_command \"$config\" /usr/sbin/pppd \\\n\t\tnodetach ipparam \"$config\" \\\n\t\tifname \"$pppname\" \\\n\t\t${localip:+$localip:} \\\n\t\t${lcp_failure:+lcp-echo-interval $lcp_interval lcp-echo-failure $lcp_failure $lcp_adaptive} \\\n\t\t${ipv6:++ipv6} \\\n\t\t${autoipv6:+set AUTOIPV6=1} \\\n\t\t${ip6table:+set IP6TABLE=$ip6table} \\\n\t\t${peerdns:+set PEERDNS=$peerdns} \\\n\t\tnodefaultroute \\\n\t\tusepeerdns \\\n\t\t$demand $persist maxfail $maxfail \\\n\t\t${holdoff:+holdoff \"$holdoff\"} \\\n\t\t${username:+user \"$username\" password \"$password\"} \\\n\t\t${connect:+connect \"$connect\"} \\\n\t\t${disconnect:+disconnect \"$disconnect\"} \\\n\t\tip-up-script /lib/netifd/ppp-up \\\n\t\t${ipv6:+ipv6-up-script /lib/netifd/ppp6-up} \\\n\t\tip-down-script /lib/netifd/ppp-down \\\n\t\t${ipv6:+ipv6-down-script /lib/netifd/ppp-down} \\\n\t\t${mtu:+mtu $mtu mru $mtu} \\\n\t\t\"$@\" $pppd_options\n}\n\nppp_generic_teardown() {\n\tlocal interface=\"$1\"\n\tlocal errorstring=$(ppp_exitcode_tostring $ERROR)\n\n\tcase \"$ERROR\" in\n\t\t0)\n\t\t;;\n\t\t2)\n\t\t\tproto_notify_error \"$interface\" \"$errorstring\"\n\t\t\tproto_block_restart \"$interface\"\n\t\t;;\n\t\t11|19)\n\t\t\tjson_get_var authfail authfail\n\t\t\tproto_notify_error \"$interface\" \"$errorstring\"\n\t\t\tif [ \"${authfail:-0}\" -gt 0 ]; then\n\t\t\t\tproto_block_restart \"$interface\"\n\t\t\tfi\n\t\t;;\n\t\t*)\n\t\t\tproto_notify_error \"$interface\" \"$errorstring\"\n\t\t;;\n\tesac\n\n\tproto_kill_command \"$interface\"\n}\n\n# PPP on serial device\n\nproto_ppp_init_config() {\n\tproto_config_add_string \"device\"\n\tppp_generic_init_config\n\tno_device=1\n\tavailable=1\n\tlasterror=1\n}\n\nproto_ppp_setup() {\n\tlocal config=\"$1\"\n\n\tjson_get_var device device\n\tppp_generic_setup \"$config\" \"$device\"\n}\n\nproto_ppp_teardown() {\n\tppp_generic_teardown \"$@\"\n}\n\nproto_pppoe_init_config() {\n\tppp_generic_init_config\n\tproto_config_add_string \"ac\"\n\tproto_config_add_string \"service\"\n\tproto_config_add_string \"host_uniq\"\n\tproto_config_add_int \"padi_attempts\"\n\tproto_config_add_int \"padi_timeout\"\n\n\tlasterror=1\n}\n\nproto_pppoe_setup() {\n\tlocal config=\"$1\"\n\tlocal iface=\"$2\"\n\n\tfor module in slhc ppp_generic pppox pppoe; do\n\t\t/sbin/insmod $module 2>&- >&-\n\tdone\n\n\tjson_get_var mtu mtu\n\tmtu=\"${mtu:-1492}\"\n\n\tjson_get_var ac ac\n\tjson_get_var service service\n\tjson_get_var host_uniq host_uniq\n\tjson_get_var padi_attempts padi_attempts\n\tjson_get_var padi_timeout padi_timeout\n\n\tppp_generic_setup \"$config\" \\\n\t\tplugin pppoe.so \\\n\t\t${ac:+rp_pppoe_ac \"$ac\"} \\\n\t\t${service:+rp_pppoe_service \"$service\"} \\\n\t\t${host_uniq:+host-uniq \"$host_uniq\"} \\\n\t\t${padi_attempts:+pppoe-padi-attempts $padi_attempts} \\\n\t\t${padi_timeout:+pppoe-padi-timeout $padi_timeout} \\\n\t\t\"nic-$iface\"\n}\n\nproto_pppoe_teardown() {\n\tppp_generic_teardown \"$@\"\n}\n\nproto_pppoa_init_config() {\n\tppp_generic_init_config\n\tproto_config_add_int \"atmdev\"\n\tproto_config_add_int \"vci\"\n\tproto_config_add_int \"vpi\"\n\tproto_config_add_string \"encaps\"\n\tno_device=1\n\tavailable=1\n\tlasterror=1\n}\n\nproto_pppoa_setup() {\n\tlocal config=\"$1\"\n\tlocal iface=\"$2\"\n\n\tfor module in slhc ppp_generic pppox pppoatm; do\n\t\t/sbin/insmod $module 2>&- >&-\n\tdone\n\n\tjson_get_vars atmdev vci vpi encaps\n\n\tcase \"$encaps\" in\n\t\t1|vc) encaps=\"vc-encaps\" ;;\n\t\t*) encaps=\"llc-encaps\" ;;\n\tesac\n\n\tppp_generic_setup \"$config\" \\\n\t\tplugin pppoatm.so \\\n\t\t${atmdev:+$atmdev.}${vpi:-8}.${vci:-35} \\\n\t\t${encaps}\n}\n\nproto_pppoa_teardown() {\n\tppp_generic_teardown \"$@\"\n}\n\nproto_pptp_init_config() {\n\tppp_generic_init_config\n\tproto_config_add_string \"server\"\n\tproto_config_add_string \"interface\"\n\tavailable=1\n\tno_device=1\n\tlasterror=1\n}\n\nproto_pptp_setup() {\n\tlocal config=\"$1\"\n\tlocal iface=\"$2\"\n\n\tlocal ip serv_addr server interface\n\tjson_get_vars interface server\n\t[ -n \"$server\" ] && {\n\t\tfor ip in $(resolveip -t 5 \"$server\"); do\n\t\t\t( proto_add_host_dependency \"$config\" \"$ip\" $interface )\n\t\t\tserv_addr=1\n\t\tdone\n\t}\n\t[ -n \"$serv_addr\" ] || {\n\t\techo \"Could not resolve server address\"\n\t\tsleep 5\n\t\tproto_setup_failed \"$config\"\n\t\texit 1\n\t}\n\n\tlocal load\n\tfor module in slhc ppp_generic ppp_async ppp_mppe ip_gre gre pptp; do\n\t\tgrep -q \"^$module \" /proc/modules && continue\n\t\t/sbin/insmod $module 2>&- >&-\n\t\tload=1\n\tdone\n\t[ \"$load\" = \"1\" ] && sleep 1\n\n\tppp_generic_setup \"$config\" \\\n\t\tplugin pptp.so \\\n\t\tpptp_server $server \\\n\t\tfile /etc/ppp/options.pptp\n}\n\nproto_pptp_teardown() {\n\tppp_generic_teardown \"$@\"\n}\n\n[ -n \"$INCLUDE_ONLY\" ] || {\n\tadd_protocol ppp\n\t[ -f /usr/lib/pppd/*/pppoe.so ] && add_protocol pppoe\n\t[ -f /usr/lib/pppd/*/pppoatm.so ] && add_protocol pppoa\n\t[ -f /usr/lib/pppd/*/pptp.so ] && add_protocol pptp\n}\n\n"
  },
  {
    "path": "package/network/services/ppp/patches/010-use_target_for_configure.patch",
    "content": "configure: Allow overriding uname results\n\nIn a cross compile setting it makes no sense to rely on the \"uname\" values\nreported by the build host system. This patch allows overriding the\n\"uname -r\", \"uname -s\" and \"uname -m\" results with the \"UNAME_R\", \"UNAME_S\"\nand \"UNAME_M\" environment variables.\n\nSigned-off-by: Jo-Philipp Wich <jo@mein.io>\n\n--- a/configure\n+++ b/configure\n@@ -10,9 +10,9 @@ CROSS_COMPILE=\n CC=cc\n CFLAGS=\n \n-system=`uname -s`\n-release=`uname -r`\n-arch=`uname -m`\n+system=${UNAME_S:-`uname -s`}\n+release=${UNAME_R:-`uname -r`}\n+arch=${UNAME_M:-`uname -m`}\n state=\"unknown\"\n \n case $system in\n"
  },
  {
    "path": "package/network/services/ppp/patches/105-debian_demand.patch",
    "content": "--- a/pppd/demand.c\n+++ b/pppd/demand.c\n@@ -36,6 +36,8 @@\n #include <errno.h>\n #include <fcntl.h>\n #include <netdb.h>\n+#include <unistd.h>\n+#include <syslog.h>\n #include <sys/param.h>\n #include <sys/types.h>\n #include <sys/wait.h>\n@@ -43,6 +45,8 @@\n #include <sys/resource.h>\n #include <sys/stat.h>\n #include <sys/socket.h>\n+#include <netinet/in.h>\n+#include <arpa/inet.h>\n #ifdef PPP_FILTER\n #include <pcap-bpf.h>\n #endif\n@@ -218,6 +222,14 @@ loop_chars(unsigned char *p, int n)\n     int c, rv;\n \n     rv = 0;\n+\n+/* check for synchronous connection... */\n+\n+    if ( (p[0] == 0xFF) && (p[1] == 0x03) ) {\n+        rv = loop_frame(p,n);\n+        return rv;\n+    }\n+\n     for (; n > 0; --n) {\n \tc = *p++;\n \tif (c == PPP_FLAG) {\n@@ -294,16 +306,100 @@ loop_frame(unsigned char *frame, int len\n  * loopback, now that the real serial link is up.\n  */\n void\n-demand_rexmit(int proto)\n+demand_rexmit(int proto, u_int32_t newip)\n {\n     struct packet *pkt, *prev, *nextpkt;\n+    unsigned short checksum;\n+    unsigned short pkt_checksum = 0;\n+    unsigned iphdr;\n+    struct timeval tv;\n+    char cv = 0;\n+    char ipstr[16];\n \n     prev = NULL;\n     pkt = pend_q;\n     pend_q = NULL;\n+    tv.tv_sec = 1;\n+    tv.tv_usec = 0;\n+    select(0,NULL,NULL,NULL,&tv);\t/* Sleep for 1 Seconds */\n     for (; pkt != NULL; pkt = nextpkt) {\n \tnextpkt = pkt->next;\n \tif (PPP_PROTOCOL(pkt->data) == proto) {\n+            if ( (proto == PPP_IP) && newip ) {\n+\t\t/* Get old checksum */\n+\n+\t\tiphdr = (pkt->data[4] & 15) << 2;\n+\t\tchecksum = *((unsigned short *) (pkt->data+14));\n+                if (checksum == 0xFFFF) {\n+                    checksum = 0;\n+                }\n+\n+ \n+                if (pkt->data[13] == 17) {\n+                    pkt_checksum =  *((unsigned short *) (pkt->data+10+iphdr));\n+\t\t    if (pkt_checksum) {\n+                        cv = 1;\n+                        if (pkt_checksum == 0xFFFF) {\n+                            pkt_checksum = 0;\n+                        }\n+                    }\n+                    else {\n+                       cv = 0;\n+                    }\n+                }\n+\n+\t\tif (pkt->data[13] == 6) {\n+\t\t    pkt_checksum = *((unsigned short *) (pkt->data+20+iphdr));\n+\t\t    cv = 1;\n+                    if (pkt_checksum == 0xFFFF) {\n+                        pkt_checksum = 0;\n+                    }\n+\t\t}\n+\n+\t\t/* Delete old Source-IP-Address */\n+                checksum -= *((unsigned short *) (pkt->data+16)) ^ 0xFFFF;\n+                checksum -= *((unsigned short *) (pkt->data+18)) ^ 0xFFFF;\n+\n+\t\tpkt_checksum -= *((unsigned short *) (pkt->data+16)) ^ 0xFFFF;\n+\t\tpkt_checksum -= *((unsigned short *) (pkt->data+18)) ^ 0xFFFF;\n+\n+\t\t/* Change Source-IP-Address */\n+                * ((u_int32_t *) (pkt->data + 16)) = newip;\n+\n+\t\t/* Add new Source-IP-Address */\n+                checksum += *((unsigned short *) (pkt->data+16)) ^ 0xFFFF;\n+                checksum += *((unsigned short *) (pkt->data+18)) ^ 0xFFFF;\n+\n+                pkt_checksum += *((unsigned short *) (pkt->data+16)) ^ 0xFFFF;\n+                pkt_checksum += *((unsigned short *) (pkt->data+18)) ^ 0xFFFF;\n+\n+\t\t/* Write new checksum */\n+                if (!checksum) {\n+                    checksum = 0xFFFF;\n+                }\n+                *((unsigned short *) (pkt->data+14)) = checksum;\n+\t\tif (pkt->data[13] == 6) {\n+\t\t    *((unsigned short *) (pkt->data+20+iphdr)) = pkt_checksum;\n+\t\t}\n+\t\tif (cv && (pkt->data[13] == 17) ) {\n+\t\t    *((unsigned short *) (pkt->data+10+iphdr)) = pkt_checksum;\n+\t\t}\n+\n+\t\t/* Log Packet */\n+\t\tstrcpy(ipstr,inet_ntoa(*( (struct in_addr *) (pkt->data+16))));\n+\t\tif (pkt->data[13] == 1) {\n+\t\t    syslog(LOG_INFO,\"Open ICMP %s -> %s\\n\",\n+\t\t\tipstr,\n+\t\t\tinet_ntoa(*( (struct in_addr *) (pkt->data+20))));\n+\t\t} else {\n+\t\t    syslog(LOG_INFO,\"Open %s %s:%d -> %s:%d\\n\",\n+\t\t\tpkt->data[13] == 6 ? \"TCP\" : \"UDP\",\n+\t\t\tipstr,\n+\t\t\tntohs(*( (short *) (pkt->data+iphdr+4))),\n+\t\t\tinet_ntoa(*( (struct in_addr *) (pkt->data+20))),\n+\t\t\tntohs(*( (short *) (pkt->data+iphdr+6))));\n+                }\n+            }\n \t    output(0, pkt->data, pkt->length);\n \t    free(pkt);\n \t} else {\n--- a/pppd/ipcp.c\n+++ b/pppd/ipcp.c\n@@ -1850,7 +1850,7 @@ ipcp_up(fsm *f)\n \t\t    proxy_arp_set[f->unit] = 1;\n \n \t}\n-\tdemand_rexmit(PPP_IP);\n+\tdemand_rexmit(PPP_IP,go->ouraddr);\n \tsifnpmode(f->unit, PPP_IP, NPMODE_PASS);\n \n     } else {\n--- a/pppd/ipv6cp.c\n+++ b/pppd/ipv6cp.c\n@@ -1253,7 +1253,7 @@ ipv6cp_up(fsm *f)\n \t\tif (sif6defaultroute(f->unit, go->ourid, ho->hisid))\n \t\t    default_route_set[f->unit] = 1;\n \t}\n-\tdemand_rexmit(PPP_IPV6);\n+\tdemand_rexmit(PPP_IPV6,0);\n \tsifnpmode(f->unit, PPP_IPV6, NPMODE_PASS);\n \n     } else {\n--- a/pppd/pppd.h\n+++ b/pppd/pppd.h\n@@ -598,7 +598,7 @@ void demand_conf(void);\t/* config interf\n void demand_block(void);\t/* set all NPs to queue up packets */\n void demand_unblock(void); /* set all NPs to pass packets */\n void demand_discard(void); /* set all NPs to discard packets */\n-void demand_rexmit(int);\t/* retransmit saved frames for an NP */\n+void demand_rexmit(int, u_int32_t); /* retransmit saved frames for an NP*/\n int  loop_chars(unsigned char *, int); /* process chars from loopback */\n int  loop_frame(unsigned char *, int); /* should we bring link up? */\n \n"
  },
  {
    "path": "package/network/services/ppp/patches/120-debian_ipv6_updown_option.patch",
    "content": "pppd: Allow specifying ipv6-up and ipv6-down scripts\n\nThis patch implements the \"ipv6-up-script\" and \"ipv6-down-script\" options\nwhich allow to specify the path of the ipv6-up and ipv6-down scripts to call.\n\nThese options default to _PATH_IPV6UP and _PATH_IPV6DOWN to retain the\nexisting behaviour.\n\nThe patch originated from the Debian project.\n\nSigned-off-by: Jo-Philipp Wich <jo@mein.io>\n\n--- a/pppd/main.c\n+++ b/pppd/main.c\n@@ -295,6 +295,8 @@ main(int argc, char *argv[])\n \n     strlcpy(path_ipup, _PATH_IPUP, sizeof(path_ipup));\n     strlcpy(path_ipdown, _PATH_IPDOWN, sizeof(path_ipdown));\n+    strlcpy(path_ipv6up, _PATH_IPV6UP, sizeof(path_ipv6up));\n+    strlcpy(path_ipv6down, _PATH_IPV6DOWN, sizeof(path_ipv6down));\n \n     link_stats_valid = 0;\n     new_phase(PHASE_INITIALIZE);\n--- a/pppd/options.c\n+++ b/pppd/options.c\n@@ -118,6 +118,8 @@ int\treq_unit = -1;\t\t/* requested interfa\n char\tpath_ipup[MAXPATHLEN];\t/* pathname of ip-up script */\n char\tpath_ipdown[MAXPATHLEN];/* pathname of ip-down script */\n char\treq_ifname[MAXIFNAMELEN];\t/* requested interface name */\n+char\tpath_ipv6up[MAXPATHLEN];\t/* pathname of ipv6-up script */\n+char\tpath_ipv6down[MAXPATHLEN];/* pathname of ipv6-down script */\n bool\tmultilink = 0;\t\t/* Enable multilink operation */\n char\t*bundle_name = NULL;\t/* bundle name for multilink */\n bool\tdump_options;\t\t/* print out option values */\n@@ -324,6 +326,13 @@ option_t general_options[] = {\n       \"Set pathname of ip-down script\",\n       OPT_PRIV|OPT_STATIC, NULL, MAXPATHLEN },\n \n+    { \"ipv6-up-script\", o_string, path_ipv6up,\n+      \"Set pathname of ipv6-up script\",\n+      OPT_PRIV|OPT_STATIC, NULL, MAXPATHLEN },\n+    { \"ipv6-down-script\", o_string, path_ipv6down,\n+      \"Set pathname of ipv6-down script\",\n+      OPT_PRIV|OPT_STATIC, NULL, MAXPATHLEN },\n+\n #ifdef HAVE_MULTILINK\n     { \"multilink\", o_bool, &multilink,\n       \"Enable multilink operation\", OPT_PRIO | 1 },\n--- a/pppd/ipv6cp.c\n+++ b/pppd/ipv6cp.c\n@@ -1295,7 +1295,7 @@ ipv6cp_up(fsm *f)\n      */\n     if (ipv6cp_script_state == s_down && ipv6cp_script_pid == 0) {\n \tipv6cp_script_state = s_up;\n-\tipv6cp_script(_PATH_IPV6UP);\n+\tipv6cp_script(path_ipv6up);\n     }\n }\n \n@@ -1346,7 +1346,7 @@ ipv6cp_down(fsm *f)\n     /* Execute the ipv6-down script */\n     if (ipv6cp_script_state == s_up && ipv6cp_script_pid == 0) {\n \tipv6cp_script_state = s_down;\n-\tipv6cp_script(_PATH_IPV6DOWN);\n+\tipv6cp_script(path_ipv6down);\n     }\n }\n \n@@ -1384,13 +1384,13 @@ ipv6cp_script_done(void *arg)\n     case s_up:\n \tif (ipv6cp_fsm[0].state != OPENED) {\n \t    ipv6cp_script_state = s_down;\n-\t    ipv6cp_script(_PATH_IPV6DOWN);\n+\t    ipv6cp_script(path_ipv6down);\n \t}\n \tbreak;\n     case s_down:\n \tif (ipv6cp_fsm[0].state == OPENED) {\n \t    ipv6cp_script_state = s_up;\n-\t    ipv6cp_script(_PATH_IPV6UP);\n+\t    ipv6cp_script(path_ipv6up);\n \t}\n \tbreak;\n     }\n--- a/pppd/pppd.h\n+++ b/pppd/pppd.h\n@@ -328,6 +328,8 @@ extern int\treq_unit;\t/* interface unit n\n extern char\tpath_ipup[MAXPATHLEN]; /* pathname of ip-up script */\n extern char\tpath_ipdown[MAXPATHLEN]; /* pathname of ip-down script */\n extern char\treq_ifname[MAXIFNAMELEN]; /* interface name to use */\n+extern char\tpath_ipv6up[MAXPATHLEN]; /* pathname of ipv6-up script */\n+extern char\tpath_ipv6down[MAXPATHLEN]; /* pathname of ipv6-down script */\n extern bool\tmultilink;\t/* enable multilink operation */\n extern bool\tnoendpoint;\t/* don't send or accept endpt. discrim. */\n extern char\t*bundle_name;\t/* bundle name for multilink */\n"
  },
  {
    "path": "package/network/services/ppp/patches/133-fix_sha1_include.patch",
    "content": "--- a/pppd/sha1.c\n+++ b/pppd/sha1.c\n@@ -19,7 +19,7 @@\n #include <string.h>\n #include <time.h>\n #include <netinet/in.h>\t/* htonl() */\n-#include <net/ppp_defs.h>\n+#include \"pppd.h\"\n #include \"sha1.h\"\n \n static void\n"
  },
  {
    "path": "package/network/services/ppp/patches/200-makefile.patch",
    "content": "pppd: tune Linux config defaults for OpenWrt\n\nThis patch adjusts a number defaults to properly match the OpenWrt environment.\nIt is not intended for upstream.\n\nSigned-off-by: Jo-Philipp Wich <jo@mein.io>\n\n--- a/pppd/Makefile.linux\n+++ b/pppd/Makefile.linux\n@@ -49,7 +49,7 @@ MPPE=y\n # Uncomment the next line to include support for PPP packet filtering.\n # This requires that the libpcap library and headers be installed\n # and that the kernel driver support PPP packet filtering.\n-FILTER=y\n+#FILTER=y\n \n # Uncomment the next line to enable multilink PPP (enabled by default)\n # Linux distributions: Please leave multilink ENABLED in your builds\n@@ -59,7 +59,7 @@ HAVE_MULTILINK=y\n # Uncomment the next line to enable the TDB database (enabled by default.)\n # If you enable multilink, then TDB is automatically enabled also.\n # Linux distributions: Please leave TDB ENABLED in your builds.\n-USE_TDB=y\n+#USE_TDB=y\n \n # Uncomment the next line to enable Type=notify services in systemd\n # If enabled, and the user sets the up_sdnotify option, then\n@@ -85,13 +85,13 @@ USE_LIBUTIL=y\n endif\n \n # Enable EAP-TLS authentication (requires MPPE support, libssl and libcrypto)\n-USE_EAPTLS=y\n+#USE_EAPTLS=y\n \n MAXOCTETS=y\n \n INCLUDE_DIRS= -I../include\n \n-COMPILE_FLAGS= -DHAVE_PATHS_H -DIPX_CHANGE -DHAVE_MMAP -pipe\n+COMPILE_FLAGS= -DHAVE_PATHS_H -DHAVE_MMAP -pipe\n \n CFLAGS= $(COPTS) $(COMPILE_FLAGS) $(INCLUDE_DIRS) '-DDESTDIR=\"@DESTDIR@\"'\n \n@@ -143,10 +143,10 @@ CFLAGS   += -DHAS_SHADOW\n #LIBS     += -lshadow $(LIBS)\n endif\n \n-ifeq ($(shell echo '\\#include <crypt.h>' | $(CC) -E - >/dev/null 2>&1 && echo yes),yes)\n+#ifeq ($(shell echo '\\#include <crypt.h>' | $(CC) -E - >/dev/null 2>&1 && echo yes),yes)\n CFLAGS  += -DHAVE_CRYPT_H=1\n LIBS\t+= -lcrypt\n-endif\n+#endif\n \n ifdef USE_LIBUTIL\n CFLAGS\t+= -DHAVE_LOGWTMP=1\n"
  },
  {
    "path": "package/network/services/ppp/patches/201-mppe_mppc_1.1.patch",
    "content": "pppd: add support for MPPE and MPPC encryption and compression protocols\n\nThis is a forward ported version of ppp-2.4.3-mppe-mppc-1.1.patch.gz found on\nhttp://mppe-mppc.alphacron.de/ .\n\nSigned-off-by: Jo-Philipp Wich <jo@mein.io>\n\n--- a/include/linux/ppp-comp.h\n+++ b/include/linux/ppp-comp.h\n@@ -36,7 +36,7 @@\n  */\n \n /*\n- *  ==FILEVERSION 20020319==\n+ *  ==FILEVERSION 20020715==\n  *\n  *  NOTE TO MAINTAINERS:\n  *     If you modify this file at all, please set the above date.\n@@ -201,6 +201,33 @@ struct compressor {\n #define CI_MPPE\t\t\t18\t/* config option for MPPE */\n #define CILEN_MPPE\t\t6\t/* length of config option */\n \n+/* MPPE/MPPC definitions by J.D.*/\n+#define MPPE_STATELESS          MPPE_H_BIT\t/* configuration bit H */\n+#define MPPE_40BIT              MPPE_L_BIT\t/* configuration bit L */\n+#define MPPE_56BIT              MPPE_M_BIT\t/* configuration bit M */\n+#define MPPE_128BIT             MPPE_S_BIT\t/* configuration bit S */\n+#define MPPE_MPPC               MPPE_C_BIT\t/* configuration bit C */\n+\n+/*\n+ * Definitions for Stac LZS.\n+ */\n+\n+#define CI_LZS\t\t\t17\t/* config option for Stac LZS */\n+#define CILEN_LZS\t\t5\t/* length of config option */\n+\n+#define LZS_OVHD\t\t4\t/* max. LZS overhead */\n+#define LZS_HIST_LEN\t\t2048\t/* LZS history size */\n+#define LZS_MAX_CCOUNT\t\t0x0FFF\t/* max. coherency counter value */\n+\n+#define LZS_MODE_NONE\t\t0\n+#define LZS_MODE_LCB\t\t1\n+#define LZS_MODE_CRC\t\t2\n+#define LZS_MODE_SEQ\t\t3\n+#define LZS_MODE_EXT\t\t4\n+\n+#define LZS_EXT_BIT_FLUSHED\t0x80\t/* bit A */\n+#define LZS_EXT_BIT_COMP\t0x20\t/* bit C */\n+\n /*\n  * Definitions for other, as yet unsupported, compression methods.\n  */\n--- a/include/net/ppp-comp.h\n+++ b/include/net/ppp-comp.h\n@@ -168,6 +168,33 @@ struct compressor {\n #define CI_MPPE\t\t\t18\t/* config option for MPPE */\n #define CILEN_MPPE\t\t6\t/* length of config option */\n \n+/* MPPE/MPPC definitions by J.D.*/\n+#define MPPE_STATELESS          MPPE_H_BIT\t/* configuration bit H */\n+#define MPPE_40BIT              MPPE_L_BIT\t/* configuration bit L */\n+#define MPPE_56BIT              MPPE_M_BIT\t/* configuration bit M */\n+#define MPPE_128BIT             MPPE_S_BIT\t/* configuration bit S */\n+#define MPPE_MPPC               MPPE_C_BIT\t/* configuration bit C */\n+\n+/*\n+ * Definitions for Stac LZS.\n+ */\n+\n+#define CI_LZS\t\t\t17\t/* config option for Stac LZS */\n+#define CILEN_LZS\t\t5\t/* length of config option */\n+\n+#define LZS_OVHD\t\t4\t/* max. LZS overhead */\n+#define LZS_HIST_LEN\t\t2048\t/* LZS history size */\n+#define LZS_MAX_CCOUNT\t\t0x0FFF\t/* max. coherency counter value */\n+\n+#define LZS_MODE_NONE\t\t0\n+#define LZS_MODE_LCB\t\t1\n+#define LZS_MODE_CRC\t\t2\n+#define LZS_MODE_SEQ\t\t3\n+#define LZS_MODE_EXT\t\t4\n+\n+#define LZS_EXT_BIT_FLUSHED\t0x80\t/* bit A */\n+#define LZS_EXT_BIT_COMP\t0x20\t/* bit C */\n+\n /*\n  * Definitions for other, as yet unsupported, compression methods.\n  */\n--- a/pppd/ccp.c\n+++ b/pppd/ccp.c\n@@ -61,12 +61,10 @@ static int setdeflate (char **);\n static char bsd_value[8];\n static char deflate_value[8];\n \n-/*\n- * Option variables.\n- */\n #ifdef MPPE\n-bool refuse_mppe_stateful = 1;\t\t/* Allow stateful mode? */\n-#endif\n+static int setmppe(char **);\n+static int setnomppe(void);\n+#endif /* MPPE */\n \n static option_t ccp_option_list[] = {\n     { \"noccp\", o_bool, &ccp_protent.enabled_flag,\n@@ -107,54 +105,36 @@ static option_t ccp_option_list[] = {\n       \"don't allow Predictor-1\", OPT_ALIAS | OPT_PRIOSUB | OPT_A2CLR,\n       &ccp_allowoptions[0].predictor_1 },\n \n+    { \"lzs\", o_bool, &ccp_wantoptions[0].lzs,\n+      \"request Stac LZS\", 1, &ccp_allowoptions[0].lzs, OPT_PRIO },\n+    { \"+lzs\", o_bool, &ccp_wantoptions[0].lzs,\n+      \"request Stac LZS\", 1, &ccp_allowoptions[0].lzs, OPT_ALIAS | OPT_PRIO },\n+    { \"nolzs\", o_bool, &ccp_wantoptions[0].lzs,\n+      \"don't allow Stac LZS\", OPT_PRIOSUB | OPT_A2CLR,\n+      &ccp_allowoptions[0].lzs },\n+    { \"-lzs\", o_bool, &ccp_wantoptions[0].lzs,\n+      \"don't allow Stac LZS\", OPT_ALIAS | OPT_PRIOSUB | OPT_A2CLR,\n+      &ccp_allowoptions[0].lzs },\n+\n #ifdef MPPE\n-    /* MPPE options are symmetrical ... we only set wantoptions here */\n-    { \"require-mppe\", o_bool, &ccp_wantoptions[0].mppe,\n-      \"require MPPE encryption\",\n-      OPT_PRIO | MPPE_OPT_40 | MPPE_OPT_128 },\n-    { \"+mppe\", o_bool, &ccp_wantoptions[0].mppe,\n-      \"require MPPE encryption\",\n-      OPT_ALIAS | OPT_PRIO | MPPE_OPT_40 | MPPE_OPT_128 },\n-    { \"nomppe\", o_bool, &ccp_wantoptions[0].mppe,\n-      \"don't allow MPPE encryption\", OPT_PRIO },\n-    { \"-mppe\", o_bool, &ccp_wantoptions[0].mppe,\n-      \"don't allow MPPE encryption\", OPT_ALIAS | OPT_PRIO },\n-\n-    /* We use ccp_allowoptions[0].mppe as a junk var ... it is reset later */\n-    { \"require-mppe-40\", o_bool, &ccp_allowoptions[0].mppe,\n-      \"require MPPE 40-bit encryption\", OPT_PRIO | OPT_A2OR | MPPE_OPT_40,\n-      &ccp_wantoptions[0].mppe },\n-    { \"+mppe-40\", o_bool, &ccp_allowoptions[0].mppe,\n-      \"require MPPE 40-bit encryption\", OPT_PRIO | OPT_A2OR | MPPE_OPT_40,\n-      &ccp_wantoptions[0].mppe },\n-    { \"nomppe-40\", o_bool, &ccp_allowoptions[0].mppe,\n-      \"don't allow MPPE 40-bit encryption\",\n-      OPT_PRIOSUB | OPT_A2CLRB | MPPE_OPT_40, &ccp_wantoptions[0].mppe },\n-    { \"-mppe-40\", o_bool, &ccp_allowoptions[0].mppe,\n-      \"don't allow MPPE 40-bit encryption\",\n-      OPT_ALIAS | OPT_PRIOSUB | OPT_A2CLRB | MPPE_OPT_40,\n-      &ccp_wantoptions[0].mppe },\n-\n-    { \"require-mppe-128\", o_bool, &ccp_allowoptions[0].mppe,\n-      \"require MPPE 128-bit encryption\", OPT_PRIO | OPT_A2OR | MPPE_OPT_128,\n-      &ccp_wantoptions[0].mppe },\n-    { \"+mppe-128\", o_bool, &ccp_allowoptions[0].mppe,\n-      \"require MPPE 128-bit encryption\",\n-      OPT_ALIAS | OPT_PRIO | OPT_A2OR | MPPE_OPT_128,\n-      &ccp_wantoptions[0].mppe },\n-    { \"nomppe-128\", o_bool, &ccp_allowoptions[0].mppe,\n-      \"don't allow MPPE 128-bit encryption\",\n-      OPT_PRIOSUB | OPT_A2CLRB | MPPE_OPT_128, &ccp_wantoptions[0].mppe },\n-    { \"-mppe-128\", o_bool, &ccp_allowoptions[0].mppe,\n-      \"don't allow MPPE 128-bit encryption\",\n-      OPT_ALIAS | OPT_PRIOSUB | OPT_A2CLRB | MPPE_OPT_128,\n-      &ccp_wantoptions[0].mppe },\n-\n-    /* strange one; we always request stateless, but will we allow stateful? */\n-    { \"mppe-stateful\", o_bool, &refuse_mppe_stateful,\n-      \"allow MPPE stateful mode\", OPT_PRIO },\n-    { \"nomppe-stateful\", o_bool, &refuse_mppe_stateful,\n-      \"disallow MPPE stateful mode\", OPT_PRIO | 1 },\n+    { \"mppc\", o_bool, &ccp_wantoptions[0].mppc,\n+      \"request MPPC compression\", 1, &ccp_allowoptions[0].mppc },\n+    { \"+mppc\", o_bool, &ccp_wantoptions[0].mppc,\n+      \"request MPPC compression\", 1, &ccp_allowoptions[0].mppc, OPT_ALIAS },\n+    { \"nomppc\", o_bool, &ccp_wantoptions[0].mppc,\n+      \"don't allow MPPC compression\", OPT_PRIOSUB | OPT_A2CLR,\n+      &ccp_allowoptions[0].mppc },\n+    { \"-mppc\", o_bool, &ccp_wantoptions[0].mppc,\n+      \"don't allow MPPC compression\", OPT_ALIAS | OPT_PRIOSUB | OPT_A2CLR,\n+      &ccp_allowoptions[0].mppc },\n+    { \"mppe\", o_special, (void *)setmppe,\n+      \"request MPPE encryption\" },\n+    { \"+mppe\", o_special, (void *)setmppe,\n+      \"request MPPE encryption\" },\n+    { \"nomppe\", o_special_noarg, (void *)setnomppe,\n+      \"don't allow MPPE encryption\" },\n+    { \"-mppe\", o_special_noarg, (void *)setnomppe,\n+      \"don't allow MPPE encryption\" },\n #endif /* MPPE */\n \n     { NULL }\n@@ -240,7 +220,7 @@ static fsm_callbacks ccp_callbacks = {\n  */\n #define ANY_COMPRESS(opt)\t((opt).deflate || (opt).bsd_compress \\\n \t\t\t\t || (opt).predictor_1 || (opt).predictor_2 \\\n-\t\t\t\t || (opt).mppe)\n+\t\t\t\t || (opt).lzs || (opt).mppc || (opt).mppe)\n \n /*\n  * Local state (mainly for handling reset-reqs and reset-acks).\n@@ -341,6 +321,100 @@ setdeflate(char **argv)\n     return 1;\n }\n \n+#ifdef MPPE\n+/*\n+ * Functions called from config options\n+ */\n+/* \n+   MPPE suboptions:\n+\trequired - require MPPE; disconnect if peer doesn't support it\n+\tstateless - use stateless mode\n+\tno40 - disable 40 bit keys\n+\tno56 - disable 56 bit keys\n+\tno128 - disable 128 bit keys\n+*/\n+int setmppe(char **argv)\n+{\n+    int i;\n+    char *str, cmdbuf[16];\n+\n+    ccp_allowoptions[0].mppe = 1;\n+    ccp_allowoptions[0].mppe_40 = 1;\n+    ccp_allowoptions[0].mppe_56 = 1;\n+    ccp_allowoptions[0].mppe_128 = 1;\n+    ccp_allowoptions[0].mppe_stateless = 0;\n+    ccp_wantoptions[0].mppe = 0;\n+\n+    str = *argv;\n+\n+    while (1) {\n+\ti = 0;\n+\tmemset(cmdbuf, '\\0', 16);\n+\twhile ((i < 16) && (*str != ',') && (*str != '\\0'))\n+\t    cmdbuf[i++] = *str++;\n+\tcmdbuf[i] = '\\0';\n+\tif (!strncasecmp(cmdbuf, \"no40\", strlen(\"no40\"))) {\n+\t    ccp_allowoptions[0].mppe_40 = 0;\n+\t    goto next_param;\n+\t} else if (!strncasecmp(cmdbuf, \"no56\", strlen(\"no56\"))) {\n+\t    ccp_allowoptions[0].mppe_56 = 0;\n+\t    goto next_param;\n+\t} else if (!strncasecmp(cmdbuf, \"no128\", strlen(\"no128\"))) {\n+\t    ccp_allowoptions[0].mppe_128 = 0;\n+\t    goto next_param;\n+\t} else if (!strncasecmp(cmdbuf, \"stateless\", strlen(\"stateless\"))) {\n+\t    ccp_allowoptions[0].mppe_stateless = 1;\n+\t    goto next_param;\n+\t} else if (!strncasecmp(cmdbuf, \"required\", strlen(\"required\"))) {\n+\t    ccp_wantoptions[0].mppe = 1;\n+\t    goto next_param;\n+\t} else {\n+\t    option_error(\"invalid parameter '%s' for mppe option\", cmdbuf);\n+\t    return 0;\n+\t}\n+\n+    next_param:\n+\tif (*str == ',') {\n+\t    str++;\n+\t    continue;\n+\t}\n+\tif (*str == '\\0') {\n+\t    if (!(ccp_allowoptions[0].mppe_40 || ccp_allowoptions[0].mppe_56 ||\n+\t\t  ccp_allowoptions[0].mppe_128)) {\n+\t\tif (ccp_wantoptions[0].mppe == 1) {\n+\t\t    option_error(\"You require MPPE but you have switched off \"\n+\t\t\t\t \"all encryption key lengths.\");\n+\t\t    return 0;\n+\t\t}\n+\t\tccp_wantoptions[0].mppe = ccp_allowoptions[0].mppe = 0;\n+\t\tccp_wantoptions[0].mppe_stateless =\n+\t\t    ccp_allowoptions[0].mppe_stateless = 0;\n+\t    } else {\n+\t\tccp_allowoptions[0].mppe = 1;\n+\t\tccp_wantoptions[0].mppe_stateless =\n+\t\t    ccp_allowoptions[0].mppe_stateless;\n+\t\tif (ccp_wantoptions[0].mppe == 1) {\n+\t\t    ccp_wantoptions[0].mppe_40 = ccp_allowoptions[0].mppe_40;\n+\t\t    ccp_wantoptions[0].mppe_56 = ccp_allowoptions[0].mppe_56;\n+\t\t    ccp_wantoptions[0].mppe_128 = ccp_allowoptions[0].mppe_128;\n+\t\t}\n+\t    }\n+\t    return 1;\n+\t}\n+    }\n+}\n+\n+int setnomppe(void)\n+{\n+    ccp_wantoptions[0].mppe = ccp_allowoptions[0].mppe = 0;\n+    ccp_wantoptions[0].mppe_40 = ccp_allowoptions[0].mppe_40 = 0;\n+    ccp_wantoptions[0].mppe_56 = ccp_allowoptions[0].mppe_56 = 0;\n+    ccp_wantoptions[0].mppe_128 = ccp_allowoptions[0].mppe_128 = 0;\n+    ccp_wantoptions[0].mppe_stateless = ccp_allowoptions[0].mppe_stateless = 0;\n+    return 1;\n+}\n+#endif /* MPPE */\n+\n /*\n  * ccp_init - initialize CCP.\n  */\n@@ -374,6 +448,30 @@ ccp_init(int unit)\n     ccp_allowoptions[0].bsd_bits = BSD_MAX_BITS;\n \n     ccp_allowoptions[0].predictor_1 = 1;\n+\n+    ccp_wantoptions[0].lzs = 0; /* Stac LZS  - will be enabled in the future */\n+    ccp_wantoptions[0].lzs_mode = LZS_MODE_SEQ;\n+    ccp_wantoptions[0].lzs_hists = 1;\n+    ccp_allowoptions[0].lzs = 0; /* Stac LZS  - will be enabled in the future */\n+    ccp_allowoptions[0].lzs_mode = LZS_MODE_SEQ;\n+    ccp_allowoptions[0].lzs_hists = 1;\n+\n+#ifdef MPPE\n+    /* by default allow and request MPPC... */\n+    ccp_wantoptions[0].mppc = ccp_allowoptions[0].mppc = 1;\n+\n+    /* ... and allow but don't request MPPE */\n+    ccp_allowoptions[0].mppe = 1;\n+    ccp_allowoptions[0].mppe_40 = 1;\n+    ccp_allowoptions[0].mppe_56 = 1;\n+    ccp_allowoptions[0].mppe_128 = 1;\n+    ccp_allowoptions[0].mppe_stateless = 1;\n+    ccp_wantoptions[0].mppe = 0;\n+    ccp_wantoptions[0].mppe_40 = 0;\n+    ccp_wantoptions[0].mppe_56 = 0;\n+    ccp_wantoptions[0].mppe_128 = 0;\n+    ccp_wantoptions[0].mppe_stateless = 0;\n+#endif /* MPPE */\n }\n \n /*\n@@ -443,11 +541,11 @@ ccp_input(int unit, u_char *p, int len)\n     if (oldstate == OPENED && p[0] == TERMREQ && f->state != OPENED) {\n \tnotice(\"Compression disabled by peer.\");\n #ifdef MPPE\n-\tif (ccp_gotoptions[unit].mppe) {\n+\tif (ccp_wantoptions[unit].mppe) {\n \t    error(\"MPPE disabled, closing LCP\");\n \t    lcp_close(unit, \"MPPE disabled by peer\");\n \t}\n-#endif\n+#endif /* MPPE */\n     }\n \n     /*\n@@ -471,6 +569,15 @@ ccp_extcode(fsm *f, int code, int id, u_\n \t    break;\n \t/* send a reset-ack, which the transmitter will see and\n \t   reset its compression state. */\n+\n+\t/* In case of MPPE/MPPC or LZS we shouldn't send CCP_RESETACK,\n+\t   but we do it in order to reset compressor; CCP_RESETACK is\n+\t   then silently discarded. See functions ppp_send_frame and\n+\t   ppp_ccp_peek in ppp_generic.c (Linux only !!!). All the\n+\t   confusion is caused by the fact that CCP code is splited\n+\t   into two parts - one part is handled by pppd, the other one\n+\t   is handled by kernel. */\n+\n \tfsm_sdata(f, CCP_RESETACK, id, NULL, 0);\n \tbreak;\n \n@@ -498,12 +605,11 @@ ccp_protrej(int unit)\n     fsm_lowerdown(&ccp_fsm[unit]);\n \n #ifdef MPPE\n-    if (ccp_gotoptions[unit].mppe) {\n+    if (ccp_wantoptions[unit].mppe) {\n \terror(\"MPPE required but peer negotiation failed\");\n \tlcp_close(unit, \"MPPE required but peer negotiation failed\");\n     }\n-#endif\n-\n+#endif /* MPPE */\n }\n \n /*\n@@ -519,7 +625,7 @@ ccp_resetci(fsm *f)\n     all_rejected[f->unit] = 0;\n \n #ifdef MPPE\n-    if (go->mppe) {\n+    if (go->mppe || go->mppc) {\n \tccp_options *ao = &ccp_allowoptions[f->unit];\n \tint auth_mschap_bits = auth_done[f->unit];\n #ifdef USE_EAPTLS\n@@ -536,95 +642,124 @@ ccp_resetci(fsm *f)\n \t * NB: If MPPE is required, all other compression opts are invalid.\n \t *     So, we return right away if we can't do it.\n \t */\n-\n-\t/* Leave only the mschap auth bits set */\n-\tauth_mschap_bits &= (CHAP_MS_WITHPEER  | CHAP_MS_PEER |\n-\t\t\t     CHAP_MS2_WITHPEER | CHAP_MS2_PEER);\n-\t/* Count the mschap auths */\n-\tauth_mschap_bits >>= CHAP_MS_SHIFT;\n-\tnumbits = 0;\n-\tdo {\n-\t    numbits += auth_mschap_bits & 1;\n-\t    auth_mschap_bits >>= 1;\n-\t} while (auth_mschap_bits);\n-\tif (numbits > 1) {\n-\t    error(\"MPPE required, but auth done in both directions.\");\n-\t    lcp_close(f->unit, \"MPPE required but not available\");\n-\t    return;\n-\t}\n+\tif (ccp_wantoptions[f->unit].mppe) {\n+\t    /* Leave only the mschap auth bits set */\n+\t    auth_mschap_bits &= (CHAP_MS_WITHPEER  | CHAP_MS_PEER |\n+\t\t\t\t CHAP_MS2_WITHPEER | CHAP_MS2_PEER);\n+\t    /* Count the mschap auths */\n+\t    auth_mschap_bits >>= CHAP_MS_SHIFT;\n+\t    numbits = 0;\n+\t    do {\n+\t\tnumbits += auth_mschap_bits & 1;\n+\t\tauth_mschap_bits >>= 1;\n+\t    } while (auth_mschap_bits);\n+\t    if (numbits > 1) {\n+\t\terror(\"MPPE required, but auth done in both directions.\");\n+\t\tlcp_close(f->unit, \"MPPE required but not available\");\n+\t\treturn;\n+\t    }\n \n #ifdef USE_EAPTLS\n-    /*\n-     * MPPE is also possible in combination with EAP-TLS.\n-     * It is not possible to detect if we're doing EAP or EAP-TLS\n-     * at this stage, hence we accept all forms of EAP. If TLS is\n-     * not used then the MPPE keys will not be derived anyway.\n-     */\n-\t/* Leave only the eap auth bits set */\n-\tauth_eap_bits &= (EAP_WITHPEER | EAP_PEER );\n+\t    /*\n+\t     * MPPE is also possible in combination with EAP-TLS.\n+\t     * It is not possible to detect if we're doing EAP or EAP-TLS\n+\t     * at this stage, hence we accept all forms of EAP. If TLS is\n+\t     * not used then the MPPE keys will not be derived anyway.\n+\t     */\n+\t\t/* Leave only the eap auth bits set */\n+\t\tauth_eap_bits &= (EAP_WITHPEER | EAP_PEER );\n \n-\tif ((numbits == 0) && (auth_eap_bits == 0)) {\n-\t    error(\"MPPE required, but MS-CHAP[v2] nor EAP-TLS auth are performed.\");\n+\t\tif ((numbits == 0) && (auth_eap_bits == 0)) {\n+\t\t    error(\"MPPE required, but MS-CHAP[v2] nor EAP-TLS auth are performed.\");\n #else\n-\tif (!numbits) {\n-\t    error(\"MPPE required, but MS-CHAP[v2] auth not performed.\");\n+\t    if (!numbits) {\n+\t\terror(\"MPPE required, but MS-CHAP[v2] auth not performed.\");\n #endif\n-\t    lcp_close(f->unit, \"MPPE required but not available\");\n-\t    return;\n-\t}\n+\t\tlcp_close(f->unit, \"MPPE required but not available\");\n+\t\treturn;\n+\t    }\n \n-\t/* A plugin (eg radius) may not have obtained key material. */\n-\tif (!mppe_keys_set) {\n-\t    error(\"MPPE required, but keys are not available.  \"\n-\t\t  \"Possible plugin problem?\");\n-\t    lcp_close(f->unit, \"MPPE required but not available\");\n-\t    return;\n-\t}\n-\n-\t/* LM auth not supported for MPPE */\n-\tif (auth_done[f->unit] & (CHAP_MS_WITHPEER | CHAP_MS_PEER)) {\n-\t    /* This might be noise */\n-\t    if (go->mppe & MPPE_OPT_40) {\n-\t\tnotice(\"Disabling 40-bit MPPE; MS-CHAP LM not supported\");\n-\t\tgo->mppe &= ~MPPE_OPT_40;\n-\t\tccp_wantoptions[f->unit].mppe &= ~MPPE_OPT_40;\n+\t    /* A plugin (eg radius) may not have obtained key material. */\n+\t    if (!mppe_keys_set) {\n+\t\terror(\"MPPE required, but keys are not available.  \"\n+\t\t      \"Possible plugin problem?\");\n+\t\tlcp_close(f->unit, \"MPPE required but not available\");\n+\t\treturn;\n \t    }\n \t}\n \n-\t/* Last check: can we actually negotiate something? */\n-\tif (!(go->mppe & (MPPE_OPT_40 | MPPE_OPT_128))) {\n-\t    /* Could be misconfig, could be 40-bit disabled above. */\n-\t    error(\"MPPE required, but both 40-bit and 128-bit disabled.\");\n-\t    lcp_close(f->unit, \"MPPE required but not available\");\n-\t    return;\n+\t/*\n+\t * Check whether the kernel knows about the various\n+\t * compression methods we might request. Key material\n+\t * unimportant here.\n+\t */\n+\tif (go->mppc) {\n+\t    opt_buf[0] = CI_MPPE;\n+\t    opt_buf[1] = CILEN_MPPE;\n+\t    opt_buf[2] = 0;\n+\t    opt_buf[3] = 0;\n+\t    opt_buf[4] = 0;\n+\t    opt_buf[5] = MPPE_MPPC;\n+\t    if (ccp_test(f->unit, opt_buf, CILEN_MPPE, 0) <= 0)\n+\t\tgo->mppc = 0;\n+\t}\n+\tif (go->mppe_40) {\n+\t    opt_buf[0] = CI_MPPE;\n+\t    opt_buf[1] = CILEN_MPPE;\n+\t    opt_buf[2] = MPPE_STATELESS;\n+\t    opt_buf[3] = 0;\n+\t    opt_buf[4] = 0;\n+\t    opt_buf[5] = MPPE_40BIT;\n+\t    if (ccp_test(f->unit, opt_buf, CILEN_MPPE + MPPE_MAX_KEY_LEN, 0) <= 0)\n+\t\tgo->mppe_40 = 0;\n+\t}\n+\tif (go->mppe_56) {\n+\t    opt_buf[0] = CI_MPPE;\n+\t    opt_buf[1] = CILEN_MPPE;\n+\t    opt_buf[2] = MPPE_STATELESS;\n+\t    opt_buf[3] = 0;\n+\t    opt_buf[4] = 0;\n+\t    opt_buf[5] = MPPE_56BIT;\n+\t    if (ccp_test(f->unit, opt_buf, CILEN_MPPE + MPPE_MAX_KEY_LEN, 0) <= 0)\n+\t\tgo->mppe_56 = 0;\n+\t}\n+\tif (go->mppe_128) {\n+\t    opt_buf[0] = CI_MPPE;\n+\t    opt_buf[1] = CILEN_MPPE;\n+\t    opt_buf[2] = MPPE_STATELESS;\n+\t    opt_buf[3] = 0;\n+\t    opt_buf[4] = 0;\n+\t    opt_buf[5] = MPPE_128BIT;\n+\t    if (ccp_test(f->unit, opt_buf, CILEN_MPPE + MPPE_MAX_KEY_LEN, 0) <= 0)\n+\t\tgo->mppe_128 = 0;\n+\t}\n+\tif (!go->mppe_40 && !go->mppe_56 && !go->mppe_128) {\n+\t    if (ccp_wantoptions[f->unit].mppe) {\n+\t\terror(\"MPPE required, but kernel has no support.\");\n+\t\tlcp_close(f->unit, \"MPPE required but not available\");\n+\t    }\n+\t    go->mppe = go->mppe_stateless = 0;\n+\t} else {\n+\t    /* MPPE is not compatible with other compression types */\n+\t    if (ccp_wantoptions[f->unit].mppe) {\n+\t\tao->bsd_compress = go->bsd_compress = 0;\n+\t\tao->predictor_1  = go->predictor_1  = 0;\n+\t\tao->predictor_2  = go->predictor_2  = 0;\n+\t\tao->deflate\t = go->deflate\t    = 0;\n+\t\tao->lzs\t\t = go->lzs\t    = 0;\n+\t    }\n \t}\n-\n-\t/* sync options */\n-\tao->mppe = go->mppe;\n-\t/* MPPE is not compatible with other compression types */\n-\tao->bsd_compress = go->bsd_compress = 0;\n-\tao->predictor_1  = go->predictor_1  = 0;\n-\tao->predictor_2  = go->predictor_2  = 0;\n-\tao->deflate      = go->deflate      = 0;\n     }\n #endif /* MPPE */\n-\n-    /*\n-     * Check whether the kernel knows about the various\n-     * compression methods we might request.\n-     */\n-#ifdef MPPE\n-    if (go->mppe) {\n-\topt_buf[0] = CI_MPPE;\n-\topt_buf[1] = CILEN_MPPE;\n-\tMPPE_OPTS_TO_CI(go->mppe, &opt_buf[2]);\n-\t/* Key material unimportant here. */\n-\tif (ccp_test(f->unit, opt_buf, CILEN_MPPE + MPPE_MAX_KEY_LEN, 0) <= 0) {\n-\t    error(\"MPPE required, but kernel has no support.\");\n-\t    lcp_close(f->unit, \"MPPE required but not available\");\n-\t}\n+    if (go->lzs) {\n+\topt_buf[0] = CI_LZS;\n+\topt_buf[1] = CILEN_LZS;\n+\topt_buf[2] = go->lzs_hists >> 8;\n+\topt_buf[3] = go->lzs_hists & 0xff;\n+\topt_buf[4] = LZS_MODE_SEQ;\n+\tif (ccp_test(f->unit, opt_buf, CILEN_LZS, 0) <= 0)\n+\t    go->lzs = 0;\n     }\n-#endif\n     if (go->bsd_compress) {\n \topt_buf[0] = CI_BSD_COMPRESS;\n \topt_buf[1] = CILEN_BSD_COMPRESS;\n@@ -679,7 +814,8 @@ static int\n \t+ (go->deflate && go->deflate_draft? CILEN_DEFLATE: 0)\n \t+ (go->predictor_1? CILEN_PREDICTOR_1: 0)\n \t+ (go->predictor_2? CILEN_PREDICTOR_2: 0)\n-\t+ (go->mppe? CILEN_MPPE: 0);\n+\t+ (go->lzs? CILEN_LZS: 0)\n+\t+ ((go->mppe || go->mppc)? CILEN_MPPE: 0);\n }\n \n /*\n@@ -690,6 +826,8 @@ static void\n {\n     int res;\n     ccp_options *go = &ccp_gotoptions[f->unit];\n+    ccp_options *ao = &ccp_allowoptions[f->unit];\n+    ccp_options *wo = &ccp_wantoptions[f->unit];\n     u_char *p0 = p;\n \n     /*\n@@ -698,22 +836,43 @@ static void\n      * in case it gets Acked.\n      */\n #ifdef MPPE\n-    if (go->mppe) {\n+    if (go->mppe || go->mppc || (!wo->mppe && ao->mppe)) {\n \tu_char opt_buf[CILEN_MPPE + MPPE_MAX_KEY_LEN];\n \n-\tp[0] = opt_buf[0] = CI_MPPE;\n-\tp[1] = opt_buf[1] = CILEN_MPPE;\n-\tMPPE_OPTS_TO_CI(go->mppe, &p[2]);\n-\tMPPE_OPTS_TO_CI(go->mppe, &opt_buf[2]);\n+\tp[0] = CI_MPPE;\n+\tp[1] = CILEN_MPPE;\n+\tp[2] = (go->mppe_stateless ? MPPE_STATELESS : 0);\n+\tp[3] = 0;\n+\tp[4] = 0;\n+\tp[5] = (go->mppe_40 ? MPPE_40BIT : 0) | (go->mppe_56 ? MPPE_56BIT : 0) |\n+\t    (go->mppe_128 ? MPPE_128BIT : 0) | (go->mppc ? MPPE_MPPC : 0);\n+\n+\tBCOPY(p, opt_buf, CILEN_MPPE);\n \tBCOPY(mppe_recv_key, &opt_buf[CILEN_MPPE], MPPE_MAX_KEY_LEN);\n \tres = ccp_test(f->unit, opt_buf, CILEN_MPPE + MPPE_MAX_KEY_LEN, 0);\n-\tif (res > 0)\n+\tif (res > 0) {\n \t    p += CILEN_MPPE;\n-\telse\n+\t} else {\n \t    /* This shouldn't happen, we've already tested it! */\n-\t    lcp_close(f->unit, \"MPPE required but not available in kernel\");\n+\t    go->mppe = go->mppe_40 = go->mppe_56 = go->mppe_128 =\n+\t\tgo->mppe_stateless = go->mppc = 0;\n+\t    if (ccp_wantoptions[f->unit].mppe)\n+\t\tlcp_close(f->unit, \"MPPE required but not available in kernel\");\n+\t}\n+    }\n+#endif /* MPPE */\n+    if (go->lzs) {\n+\tp[0] = CI_LZS;\n+\tp[1] = CILEN_LZS;\n+\tp[2] = go->lzs_hists >> 8;\n+\tp[3] = go->lzs_hists & 0xff;\n+\tp[4] = LZS_MODE_SEQ;\n+\tres = ccp_test(f->unit, p, CILEN_LZS, 0);\n+\tif (res > 0) {\n+\t    p += CILEN_LZS;\n+\t} else\n+\t    go->lzs = 0;\n     }\n-#endif\n     if (go->deflate) {\n \tp[0] = go->deflate_correct? CI_DEFLATE: CI_DEFLATE_DRAFT;\n \tp[1] = CILEN_DEFLATE;\n@@ -799,30 +958,50 @@ static void\n \n /*\n  * ccp_ackci - process a received configure-ack, and return\n- * 1 iff the packet was OK.\n+ * 1 if the packet was OK.\n  */\n static int\n   ccp_ackci(fsm *f, u_char *p, int len)\n {\n     ccp_options *go = &ccp_gotoptions[f->unit];\n+    ccp_options *ao = &ccp_allowoptions[f->unit];\n+    ccp_options *wo = &ccp_wantoptions[f->unit];\n     u_char *p0 = p;\n \n #ifdef MPPE\n-    if (go->mppe) {\n-\tu_char opt_buf[CILEN_MPPE];\n-\n-\topt_buf[0] = CI_MPPE;\n-\topt_buf[1] = CILEN_MPPE;\n-\tMPPE_OPTS_TO_CI(go->mppe, &opt_buf[2]);\n-\tif (len < CILEN_MPPE || memcmp(opt_buf, p, CILEN_MPPE))\n+    if (go->mppe || go->mppc || (!wo->mppe && ao->mppe)) {\n+\tif (len < CILEN_MPPE\n+\t    || p[1] != CILEN_MPPE || p[0] != CI_MPPE\n+\t    || p[2] != (go->mppe_stateless ? MPPE_STATELESS : 0)\n+\t    || p[3] != 0\n+\t    || p[4] != 0\n+\t    || (p[5] != ((go->mppe_40 ? MPPE_40BIT : 0) |\n+\t\t\t (go->mppc ? MPPE_MPPC : 0))\n+\t\t&& p[5] != ((go->mppe_56 ? MPPE_56BIT : 0) |\n+\t\t\t    (go->mppc ? MPPE_MPPC : 0))\n+\t\t&& p[5] != ((go->mppe_128 ? MPPE_128BIT : 0) |\n+\t\t\t    (go->mppc ? MPPE_MPPC : 0))))\n \t    return 0;\n+\tif (go->mppe_40 || go->mppe_56 || go->mppe_128)\n+\t    go->mppe = 1;\n \tp += CILEN_MPPE;\n \tlen -= CILEN_MPPE;\n+\t/* Cope with first/fast ack */\n+\tif (p == p0 && len == 0)\n+\t    return 1;\n+    }\n+#endif /* MPPE */\n+    if (go->lzs) {\n+\tif (len < CILEN_LZS || p[0] != CI_LZS || p[1] != CILEN_LZS\n+\t    || p[2] != go->lzs_hists>>8 || p[3] != (go->lzs_hists&0xff)\n+\t    || p[4] != LZS_MODE_SEQ)\n+\t    return 0;\n+\tp += CILEN_LZS;\n+\tlen -= CILEN_LZS;\n \t/* XXX Cope with first/fast ack */\n-\tif (len == 0)\n+\tif (p == p0 && len == 0)\n \t    return 1;\n     }\n-#endif\n     if (go->deflate) {\n \tif (len < CILEN_DEFLATE\n \t    || p[0] != (go->deflate_correct? CI_DEFLATE: CI_DEFLATE_DRAFT)\n@@ -891,6 +1070,8 @@ static int\n   ccp_nakci(fsm *f, u_char *p, int len, int treat_as_reject)\n {\n     ccp_options *go = &ccp_gotoptions[f->unit];\n+    ccp_options *ao = &ccp_allowoptions[f->unit];\n+    ccp_options *wo = &ccp_wantoptions[f->unit];\n     ccp_options no;\t\t/* options we've seen already */\n     ccp_options try;\t\t/* options to ask for next time */\n \n@@ -898,28 +1079,100 @@ static int\n     try = *go;\n \n #ifdef MPPE\n-    if (go->mppe && len >= CILEN_MPPE\n-\t&& p[0] == CI_MPPE && p[1] == CILEN_MPPE) {\n-\tno.mppe = 1;\n-\t/*\n-\t * Peer wants us to use a different strength or other setting.\n-\t * Fail if we aren't willing to use his suggestion.\n-\t */\n-\tMPPE_CI_TO_OPTS(&p[2], try.mppe);\n-\tif ((try.mppe & MPPE_OPT_STATEFUL) && refuse_mppe_stateful) {\n-\t    error(\"Refusing MPPE stateful mode offered by peer\");\n-\t    try.mppe = 0;\n-\t} else if (((go->mppe | MPPE_OPT_STATEFUL) & try.mppe) != try.mppe) {\n-\t    /* Peer must have set options we didn't request (suggest) */\n-\t    try.mppe = 0;\n-\t}\n+    if ((go->mppe || go->mppc || (!wo->mppe && ao->mppe)) &&\n+\tlen >= CILEN_MPPE && p[0] == CI_MPPE && p[1] == CILEN_MPPE) {\n \n-\tif (!try.mppe) {\n-\t    error(\"MPPE required but peer negotiation failed\");\n-\t    lcp_close(f->unit, \"MPPE required but peer negotiation failed\");\n+\tif (go->mppc) {\n+\t    no.mppc = 1;\n+\t    if (!(p[5] & MPPE_MPPC))\n+\t\ttry.mppc = 0;\n+\t}\n+\n+\tif (go->mppe)\n+\t    no.mppe = 1;\n+\tif (go->mppe_40)\n+\t    no.mppe_40 = 1;\n+\tif (go->mppe_56)\n+\t    no.mppe_56 = 1;\n+\tif (go->mppe_128)\n+\t    no.mppe_128 = 1;\n+\tif (go->mppe_stateless)\n+\t    no.mppe_stateless = 1;\n+\n+\tif (ao->mppe_40) {\n+\t    if ((p[5] & MPPE_40BIT))\n+\t\ttry.mppe_40 = 1;\n+\t    else\n+\t\ttry.mppe_40 = (p[5] == 0) ? 1 : 0;\n+\t}\n+\tif (ao->mppe_56) {\n+\t    if ((p[5] & MPPE_56BIT))\n+\t\ttry.mppe_56 = 1;\n+\t    else\n+\t\ttry.mppe_56 = (p[5] == 0) ? 1 : 0;\n+\t}\n+\tif (ao->mppe_128) {\n+\t    if ((p[5] & MPPE_128BIT))\n+\t\ttry.mppe_128 = 1;\n+\t    else\n+\t\ttry.mppe_128 = (p[5] == 0) ? 1 : 0;\n+\t}\n+\n+\tif (ao->mppe_stateless) {\n+\t    if ((p[2] & MPPE_STATELESS) || wo->mppe_stateless)\n+\t\ttry.mppe_stateless = 1;\n+\t    else\n+\t\ttry.mppe_stateless = 0;\n+\t}\n+\n+\tif (!try.mppe_56 && !try.mppe_40 && !try.mppe_128) {\n+\t    try.mppe = try.mppe_stateless = 0;\n+\t    if (wo->mppe) {\n+\t\t/* we require encryption, but peer doesn't support it\n+\t\t   so we close connection */\n+\t\two->mppc = wo->mppe = wo->mppe_stateless = wo->mppe_40 =\n+\t\t    wo->mppe_56 = wo->mppe_128 = 0;\n+\t\tlcp_close(f->unit, \"MPPE required but cannot negotiate MPPE \"\n+\t\t\t  \"key length\");\n+\t    }\n+        }\n+\tif (wo->mppe && (wo->mppe_40 != try.mppe_40) &&\n+\t    (wo->mppe_56 != try.mppe_56) && (wo->mppe_128 != try.mppe_128)) {\n+\t    /* cannot negotiate key length */\n+\t    wo->mppc = wo->mppe = wo->mppe_stateless = wo->mppe_40 =\n+\t\two->mppe_56 = wo->mppe_128 = 0;\n+\t    lcp_close(f->unit, \"Cannot negotiate MPPE key length\");\n \t}\n+\tif (try.mppe_40 && try.mppe_56 && try.mppe_128)\n+\t    try.mppe_40 = try.mppe_56 = 0;\n+\telse\n+\t    if (try.mppe_56 && try.mppe_128)\n+\t\ttry.mppe_56 = 0;\n+\t    else\n+\t\tif (try.mppe_40 && try.mppe_128)\n+\t\t    try.mppe_40 = 0;\n+\t\telse\n+\t\t    if (try.mppe_40 && try.mppe_56)\n+\t\t\ttry.mppe_40 = 0;\n+\n+\tp += CILEN_MPPE;\n+\tlen -= CILEN_MPPE;\n     }\n #endif /* MPPE */\n+\n+    if (go->lzs && len >= CILEN_LZS && p[0] == CI_LZS && p[1] == CILEN_LZS) {\n+\tno.lzs = 1;\n+\tif (((p[2]<<8)|p[3]) > 1 || (p[4] != LZS_MODE_SEQ &&\n+\t\t\t\t     p[4] != LZS_MODE_EXT))\n+\t    try.lzs = 0;\n+\telse {\n+\t    try.lzs_mode = p[4];\n+\t    try.lzs_hists = (p[2] << 8) | p[3];\n+\t}\n+\tp += CILEN_LZS;\n+\tlen -= CILEN_LZS;\n+    }\n+\n     if (go->deflate && len >= CILEN_DEFLATE\n \t&& p[0] == (go->deflate_correct? CI_DEFLATE: CI_DEFLATE_DRAFT)\n \t&& p[1] == CILEN_DEFLATE) {\n@@ -989,14 +1242,50 @@ ccp_rejci(fsm *f, u_char *p, int len)\n \treturn -1;\n \n #ifdef MPPE\n-    if (go->mppe && len >= CILEN_MPPE\n+    if ((go->mppe || go->mppc) && len >= CILEN_MPPE\n \t&& p[0] == CI_MPPE && p[1] == CILEN_MPPE) {\n-\terror(\"MPPE required but peer refused\");\n-\tlcp_close(f->unit, \"MPPE required but peer refused\");\n+\tccp_options *wo = &ccp_wantoptions[f->unit];\n+\tif (p[2] != (go->mppe_stateless ? MPPE_STATELESS : 0) ||\n+\t    p[3] != 0 ||\n+\t    p[4] != 0 ||\n+\t    p[5] != ((go->mppe_40 ? MPPE_40BIT : 0) |\n+\t\t     (go->mppe_56 ? MPPE_56BIT : 0) |\n+\t\t     (go->mppe_128 ? MPPE_128BIT : 0) |\n+\t\t     (go->mppc ? MPPE_MPPC : 0)))\n+\t    return 0;\n+\tif (go->mppc)\n+\t    try.mppc = 0;\n+\tif (go->mppe) {\n+\t    try.mppe = 0;\n+\t    if (go->mppe_40)\n+\t\ttry.mppe_40 = 0;\n+\t    if (go->mppe_56)\n+\t\ttry.mppe_56 = 0;\n+\t    if (go->mppe_128)\n+\t\ttry.mppe_128 = 0;\n+\t    if (go->mppe_stateless)\n+\t\ttry.mppe_stateless = 0;\n+\t    if (!try.mppe_56 && !try.mppe_40 && !try.mppe_128)\n+\t\ttry.mppe = try.mppe_stateless = 0;\n+\t    if (wo->mppe) { /* we want MPPE but cannot negotiate key length */\n+\t\two->mppc = wo->mppe = wo->mppe_stateless = wo->mppe_40 =\n+\t\t    wo->mppe_56 = wo->mppe_128 = 0;\n+\t\tlcp_close(f->unit, \"MPPE required but cannot negotiate MPPE \"\n+\t\t\t  \"key length\");\n+\t    }\n+\t}\n \tp += CILEN_MPPE;\n \tlen -= CILEN_MPPE;\n     }\n-#endif\n+#endif /* MPPE */\n+    if (go->lzs && len >= CILEN_LZS && p[0] == CI_LZS && p[1] == CILEN_LZS) {\n+\tif (p[2] != go->lzs_hists>>8 || p[3] != (go->lzs_hists&0xff) \n+\t    || p[4] != go->lzs_mode)\n+\t    return 0;\n+\ttry.lzs = 0;\n+\tp += CILEN_LZS;\n+\tlen -= CILEN_LZS;\n+    }\n     if (go->deflate_correct && len >= CILEN_DEFLATE\n \t&& p[0] == CI_DEFLATE && p[1] == CILEN_DEFLATE) {\n \tif (p[2] != DEFLATE_MAKE_OPT(go->deflate_size)\n@@ -1056,14 +1345,15 @@ static int\n ccp_reqci(fsm *f, u_char *p, int *lenp, int dont_nak)\n {\n     int ret, newret, res;\n-    u_char *p0, *retp;\n+    u_char *p0, *retp, p2, p5;\n     int len, clen, type, nb;\n     ccp_options *ho = &ccp_hisoptions[f->unit];\n     ccp_options *ao = &ccp_allowoptions[f->unit];\n+    ccp_options *wo = &ccp_wantoptions[f->unit];\n #ifdef MPPE\n-    bool rej_for_ci_mppe = 1;\t/* Are we rejecting based on a bad/missing */\n-\t\t\t\t/* CI_MPPE, or due to other options?       */\n-#endif\n+    u_char opt_buf[CILEN_MPPE + MPPE_MAX_KEY_LEN];\n+/*     int mtu; */\n+#endif /* MPPE */\n \n     ret = CONFACK;\n     retp = p0 = p;\n@@ -1086,106 +1376,302 @@ ccp_reqci(fsm *f, u_char *p, int *lenp,\n \t    switch (type) {\n #ifdef MPPE\n \t    case CI_MPPE:\n-\t\tif (!ao->mppe || clen != CILEN_MPPE) {\n+ \t\tif ((!ao->mppc && !ao->mppe) || clen != CILEN_MPPE) {\n \t\t    newret = CONFREJ;\n \t\t    break;\n \t\t}\n-\t\tMPPE_CI_TO_OPTS(&p[2], ho->mppe);\n-\n-\t\t/* Nak if anything unsupported or unknown are set. */\n-\t\tif (ho->mppe & MPPE_OPT_UNSUPPORTED) {\n+ \t\tp2 = p[2];\n+ \t\tp5 = p[5];\n+ \t\t/* not sure what they want, tell 'em what we got */\n+ \t\tif (((p[2] & ~MPPE_STATELESS) != 0 || p[3] != 0 || p[4] != 0 ||\n+ \t\t     (p[5] & ~(MPPE_40BIT | MPPE_56BIT | MPPE_128BIT |\n+ \t\t\t       MPPE_MPPC)) != 0 || p[5] == 0) ||\n+ \t\t    (p[2] == 0 && p[3] == 0 && p[4] == 0 &&  p[5] == 0)) {\n \t\t    newret = CONFNAK;\n-\t\t    ho->mppe &= ~MPPE_OPT_UNSUPPORTED;\n-\t\t}\n-\t\tif (ho->mppe & MPPE_OPT_UNKNOWN) {\n-\t\t    newret = CONFNAK;\n-\t\t    ho->mppe &= ~MPPE_OPT_UNKNOWN;\n-\t\t}\n-\n-\t\t/* Check state opt */\n-\t\tif (ho->mppe & MPPE_OPT_STATEFUL) {\n-\t\t    /*\n-\t\t     * We can Nak and request stateless, but it's a\n-\t\t     * lot easier to just assume the peer will request\n-\t\t     * it if he can do it; stateful mode is bad over\n-\t\t     * the Internet -- which is where we expect MPPE.\n-\t\t     */\n-\t\t   if (refuse_mppe_stateful) {\n-\t\t\terror(\"Refusing MPPE stateful mode offered by peer\");\n-\t\t\tnewret = CONFREJ;\n-\t\t\tbreak;\n+ \t\t    p[2] = (wo->mppe_stateless ? MPPE_STATELESS : 0);\n+\t\t    p[3] = 0;\n+ \t\t    p[4] = 0;\n+ \t\t    p[5] = (wo->mppe_40 ? MPPE_40BIT : 0) |\n+ \t\t\t(wo->mppe_56 ? MPPE_56BIT : 0) |\n+ \t\t\t(wo->mppe_128 ? MPPE_128BIT : 0) |\n+ \t\t\t(wo->mppc ? MPPE_MPPC : 0);\n+ \t\t    break;\n+  \t\t}\n+\n+ \t\tif ((p[5] & MPPE_MPPC)) {\n+ \t\t    if (ao->mppc) {\n+ \t\t\tho->mppc = 1;\n+ \t\t\tBCOPY(p, opt_buf, CILEN_MPPE);\n+ \t\t\topt_buf[2] = opt_buf[3] = opt_buf[4] = 0;\n+ \t\t\topt_buf[5] = MPPE_MPPC;\n+ \t\t\tif (ccp_test(f->unit, opt_buf, CILEN_MPPE, 1) <= 0) {\n+ \t\t\t    ho->mppc = 0;\n+ \t\t\t    p[5] &= ~MPPE_MPPC;\n+ \t\t\t    newret = CONFNAK;\n+ \t\t\t}\n+ \t\t    } else {\n+\t\t      newret = CONFREJ;\n+ \t\t\tif (wo->mppe || ao->mppe) {\n+ \t\t\t    p[5] &= ~MPPE_MPPC;\n+ \t\t\t    newret = CONFNAK;\n+ \t\t\t}\n \t\t    }\n \t\t}\n-\n-\t\t/* Find out which of {S,L} are set. */\n-\t\tif ((ho->mppe & MPPE_OPT_128)\n-\t\t     && (ho->mppe & MPPE_OPT_40)) {\n-\t\t    /* Both are set, negotiate the strongest. */\n-\t\t    newret = CONFNAK;\n-\t\t    if (ao->mppe & MPPE_OPT_128)\n-\t\t\tho->mppe &= ~MPPE_OPT_40;\n-\t\t    else if (ao->mppe & MPPE_OPT_40)\n-\t\t\tho->mppe &= ~MPPE_OPT_128;\n-\t\t    else {\n-\t\t\tnewret = CONFREJ;\n-\t\t\tbreak;\n-\t\t    }\n-\t\t} else if (ho->mppe & MPPE_OPT_128) {\n-\t\t    if (!(ao->mppe & MPPE_OPT_128)) {\n-\t\t\tnewret = CONFREJ;\n-\t\t\tbreak;\n-\t\t    }\n-\t\t} else if (ho->mppe & MPPE_OPT_40) {\n-\t\t    if (!(ao->mppe & MPPE_OPT_40)) {\n-\t\t\tnewret = CONFREJ;\n-\t\t\tbreak;\n-\t\t    }\n+ \t\tif (ao->mppe)\n+ \t\t    ho->mppe = 1;\n+ \n+ \t\tif ((p[2] & MPPE_STATELESS)) {\n+ \t\t    if (ao->mppe_stateless) {\n+ \t\t\tif (wo->mppe_stateless)\n+ \t\t\t    ho->mppe_stateless = 1;\n+ \t\t\telse {\n+ \t\t\t    newret = CONFNAK;\n+ \t\t\t    if (!dont_nak)\n+ \t\t\t\tp[2] &= ~MPPE_STATELESS;\n+ \t\t\t}\n+ \t\t    } else {\n+ \t\t\tnewret = CONFNAK;\n+ \t\t\tif (!dont_nak)\n+ \t\t\t    p[2] &= ~MPPE_STATELESS;\n+ \t\t    }\n+ \t\t} else {\n+ \t\t    if (wo->mppe_stateless && !dont_nak) {\n+ \t\t\two->mppe_stateless = 0;\n+ \t\t\tnewret = CONFNAK;\n+ \t\t\tp[2] |= MPPE_STATELESS;\n+  \t\t    }\n+  \t\t}\n+  \n+ \t\tif ((p[5] & ~MPPE_MPPC) == (MPPE_40BIT|MPPE_56BIT|MPPE_128BIT)) {\n+  \t\t    newret = CONFNAK;\n+ \t\t    if (ao->mppe_128) {\n+ \t\t\tho->mppe_128 = 1;\n+ \t\t\tp[5] &= ~(MPPE_40BIT|MPPE_56BIT);\n+ \t\t\tBCOPY(p, opt_buf, CILEN_MPPE);\n+ \t\t\tBCOPY(mppe_send_key, &opt_buf[CILEN_MPPE],\n+ \t\t\t      MPPE_MAX_KEY_LEN);\n+ \t\t\tif (ccp_test(f->unit, opt_buf, CILEN_MPPE +\n+ \t\t\t\t     MPPE_MAX_KEY_LEN, 1) <= 0) {\n+ \t\t\t    ho->mppe_128 = 0;\n+ \t\t\t    p[5] |= (MPPE_40BIT|MPPE_56BIT);\n+ \t\t\t    p[5] &= ~MPPE_128BIT;\n+ \t\t\t    goto check_mppe_56_40;\n+ \t\t\t}\n+ \t\t\tgoto check_mppe;\n+  \t\t    }\n+ \t\t    p[5] &= ~MPPE_128BIT;\n+ \t\t    goto check_mppe_56_40;\n+ \t\t}\n+ \t\tif ((p[5] & ~MPPE_MPPC) == (MPPE_56BIT|MPPE_128BIT)) {\n+ \t\t    newret = CONFNAK;\n+ \t\t    if (ao->mppe_128) {\n+ \t\t\tho->mppe_128 = 1;\n+ \t\t\tp[5] &= ~MPPE_56BIT;\n+ \t\t\tBCOPY(p, opt_buf, CILEN_MPPE);\n+\t\t\tBCOPY(mppe_send_key, &opt_buf[CILEN_MPPE],\n+ \t\t\t      MPPE_MAX_KEY_LEN);\n+ \t\t\tif (ccp_test(f->unit, opt_buf, CILEN_MPPE +\n+ \t\t\t\t     MPPE_MAX_KEY_LEN, 1) <= 0) {\n+ \t\t\t    ho->mppe_128 = 0;\n+ \t\t\t    p[5] |= MPPE_56BIT;\n+ \t\t\t    p[5] &= ~MPPE_128BIT;\n+ \t\t\t    goto check_mppe_56;\n+ \t\t\t}\n+ \t\t\tgoto check_mppe;\n+  \t\t    }\n+ \t\t    p[5] &= ~MPPE_128BIT;\n+ \t\t    goto check_mppe_56;\n+ \t\t}\n+ \t\tif ((p[5] & ~MPPE_MPPC) == (MPPE_40BIT|MPPE_128BIT)) {\n+ \t\t    newret = CONFNAK;\n+ \t\t    if (ao->mppe_128) {\n+ \t\t\tho->mppe_128 = 1;\n+ \t\t\tp[5] &= ~MPPE_40BIT;\n+ \t\t\tBCOPY(p, opt_buf, CILEN_MPPE);\n+ \t\t\tBCOPY(mppe_send_key, &opt_buf[CILEN_MPPE],\n+ \t\t\t      MPPE_MAX_KEY_LEN);\n+ \t\t\tif (ccp_test(f->unit, opt_buf, CILEN_MPPE +\n+ \t\t\t\t     MPPE_MAX_KEY_LEN, 1) <= 0) {\n+ \t\t\t    ho->mppe_128 = 0;\n+ \t\t\t    p[5] |= MPPE_40BIT;\n+ \t\t\t    p[5] &= ~MPPE_128BIT;\n+ \t\t\t    goto check_mppe_40;\n+ \t\t\t}\n+ \t\t\tgoto check_mppe;\n+ \t\t    }\n+ \t\t    p[5] &= ~MPPE_128BIT;\n+ \t\t    goto check_mppe_40;\n+ \t\t}\n+ \t\tif ((p[5] & ~MPPE_MPPC) == MPPE_128BIT) {\n+ \t\t    if (ao->mppe_128) {\n+ \t\t\tho->mppe_128 = 1;\n+ \t\t\tBCOPY(p, opt_buf, CILEN_MPPE);\n+ \t\t\tBCOPY(mppe_send_key, &opt_buf[CILEN_MPPE],\n+ \t\t\t      MPPE_MAX_KEY_LEN);\n+ \t\t\tif (ccp_test(f->unit, opt_buf, CILEN_MPPE +\n+ \t\t\t\t     MPPE_MAX_KEY_LEN, 1) <= 0) {\n+ \t\t\t    ho->mppe_128 = 0;\n+ \t\t\t    p[5] &= ~MPPE_128BIT;\n+ \t\t\t    newret = CONFNAK;\n+ \t\t\t}\n+ \t\t\tgoto check_mppe;\n+ \t\t    }\n+\t\t    p[5] &= ~MPPE_128BIT;\n+ \t\t    newret = CONFNAK;\n+ \t\t    goto check_mppe;\n+ \t\t}\n+ \t    check_mppe_56_40:\n+\t\tif ((p[5] & ~MPPE_MPPC) == (MPPE_40BIT|MPPE_56BIT)) {\n+ \t\t    newret = CONFNAK;\n+ \t\t    if (ao->mppe_56) {\n+ \t\t\tho->mppe_56 = 1;\n+ \t\t\tp[5] &= ~MPPE_40BIT;\n+\t\t\tBCOPY(p, opt_buf, CILEN_MPPE);\n+ \t\t\tBCOPY(mppe_send_key, &opt_buf[CILEN_MPPE],\n+ \t\t\t      MPPE_MAX_KEY_LEN);\n+ \t\t\tif (ccp_test(f->unit, opt_buf, CILEN_MPPE +\n+\t\t\t\t     MPPE_MAX_KEY_LEN, 1) <= 0) {\n+ \t\t\t    ho->mppe_56 = 0;\n+ \t\t\t    p[5] |= MPPE_40BIT;\n+ \t\t\t    p[5] &= ~MPPE_56BIT;\n+\t\t\t    newret = CONFNAK;\n+ \t\t\t    goto check_mppe_40;\n+ \t\t\t}\n+\t\t\tgoto check_mppe;\n+ \t\t    }\n+\t\t    p[5] &= ~MPPE_56BIT;\n+ \t\t    goto check_mppe_40;\n+ \t\t}\n+ \t    check_mppe_56:\n+\t\tif ((p[5] & ~MPPE_MPPC) == MPPE_56BIT) {\n+ \t\t    if (ao->mppe_56) {\n+ \t\t\tho->mppe_56 = 1;\n+ \t\t\tBCOPY(p, opt_buf, CILEN_MPPE);\n+ \t\t\tBCOPY(mppe_send_key, &opt_buf[CILEN_MPPE],\n+\t\t\t      MPPE_MAX_KEY_LEN);\n+ \t\t\tif (ccp_test(f->unit, opt_buf, CILEN_MPPE +\n+ \t\t\t\t     MPPE_MAX_KEY_LEN, 1) <= 0) {\n+ \t\t\t    ho->mppe_56 = 0;\n+ \t\t\t    p[5] &= ~MPPE_56BIT;\n+\t\t\t    newret = CONFNAK;\n+ \t\t\t}\n+\t\t\tgoto check_mppe;\n+ \t\t    }\n+ \t\t    p[5] &= ~MPPE_56BIT;\n+ \t\t    newret = CONFNAK;\n+\t\t    goto check_mppe;\n+ \t\t}\n+ \t    check_mppe_40:\n+\t\tif ((p[5] & ~MPPE_MPPC) == MPPE_40BIT) {\n+ \t\t    if (ao->mppe_40) {\n+ \t\t\tho->mppe_40 = 1;\n+ \t\t\tBCOPY(p, opt_buf, CILEN_MPPE);\n+\t\t\tBCOPY(mppe_send_key, &opt_buf[CILEN_MPPE],\n+ \t\t\t      MPPE_MAX_KEY_LEN);\n+ \t\t\tif (ccp_test(f->unit, opt_buf, CILEN_MPPE +\n+ \t\t\t\t     MPPE_MAX_KEY_LEN, 1) <= 0) {\n+ \t\t\t    ho->mppe_40 = 0;\n+\t\t\t    p[5] &= ~MPPE_40BIT;\n+ \t\t\t    newret = CONFNAK;\n+ \t\t\t}\n+ \t\t\tgoto check_mppe;\n+ \t\t    }\n+ \t\t    p[5] &= ~MPPE_40BIT;\n+ \t\t}\n+ \n+ \t    check_mppe:\n+ \t\tif (!ho->mppe_40 && !ho->mppe_56 && !ho->mppe_128) {\n+ \t\t    if (wo->mppe_40 || wo->mppe_56 || wo->mppe_128) {\n+ \t\t\tnewret = CONFNAK;\n+ \t\t\tp[2] |= (wo->mppe_stateless ? MPPE_STATELESS : 0);\n+\t\t\tp[5] |= (wo->mppe_40 ? MPPE_40BIT : 0) |\n+ \t\t\t    (wo->mppe_56 ? MPPE_56BIT : 0) |\n+ \t\t\t    (wo->mppe_128 ? MPPE_128BIT : 0) |\n+ \t\t\t    (wo->mppc ? MPPE_MPPC : 0);\n+ \t\t    } else {\n+ \t\t\tho->mppe = ho->mppe_stateless = 0;\n+ \t\t    }\n \t\t} else {\n-\t\t    /* Neither are set. */\n-\t\t    /* We cannot accept this.  */\n-\t\t    newret = CONFNAK;\n-\t\t    /* Give the peer our idea of what can be used,\n-\t\t       so it can choose and confirm */\n-\t\t    ho->mppe = ao->mppe;\n-\t\t}\n-\n-\t\t/* rebuild the opts */\n-\t\tMPPE_OPTS_TO_CI(ho->mppe, &p[2]);\n-\t\tif (newret == CONFACK) {\n-\t\t    u_char opt_buf[CILEN_MPPE + MPPE_MAX_KEY_LEN];\n-\t\t    int mtu;\n-\n-\t\t    BCOPY(p, opt_buf, CILEN_MPPE);\n-\t\t    BCOPY(mppe_send_key, &opt_buf[CILEN_MPPE],\n-\t\t\t  MPPE_MAX_KEY_LEN);\n-\t\t    if (ccp_test(f->unit, opt_buf,\n-\t\t\t\t CILEN_MPPE + MPPE_MAX_KEY_LEN, 1) <= 0) {\n-\t\t\t/* This shouldn't happen, we've already tested it! */\n-\t\t\terror(\"MPPE required, but kernel has no support.\");\n-\t\t\tlcp_close(f->unit, \"MPPE required but not available\");\n-\t\t\tnewret = CONFREJ;\n-\t\t\tbreak;\n-\t\t    }\n-\t\t    /*\n-\t\t     * We need to decrease the interface MTU by MPPE_PAD\n-\t\t     * because MPPE frames **grow**.  The kernel [must]\n-\t\t     * allocate MPPE_PAD extra bytes in xmit buffers.\n-\t\t     */\n-\t\t    mtu = netif_get_mtu(f->unit);\n-\t\t    if (mtu)\n-\t\t\tnetif_set_mtu(f->unit, mtu - MPPE_PAD);\n-\t\t    else\n-\t\t\tnewret = CONFREJ;\n-\t\t}\n-\n-\t\t/*\n-\t\t * We have accepted MPPE or are willing to negotiate\n-\t\t * MPPE parameters.  A CONFREJ is due to subsequent\n-\t\t * (non-MPPE) processing.\n-\t\t */\n-\t\trej_for_ci_mppe = 0;\n-\t\tbreak;\n-#endif /* MPPE */\n+ \t\t    /* MPPE is not compatible with other compression types */\n+ \t\t    if (wo->mppe) {\n+ \t\t\tao->bsd_compress = 0;\n+ \t\t\tao->predictor_1 = 0;\n+ \t\t\tao->predictor_2 = 0;\n+\t\t\tao->deflate = 0;\n+ \t\t\tao->lzs = 0;\n+ \t\t    }\n+ \t\t}\n+ \t\tif ((!ho->mppc || !ao->mppc) && !ho->mppe) {\n+ \t\t    p[2] = p2;\n+ \t\t    p[5] = p5;\n+  \t\t    newret = CONFREJ;\n+  \t\t    break;\n+  \t\t}\n+  \n+ \t\t/*\n+ \t\t * I have commented the code below because according to RFC1547\n+ \t\t * MTU is only information for higher level protocols about\n+ \t\t * \"the maximum allowable length for a packet (q.v.) transmitted\n+ \t\t * over a point-to-point link without incurring network layer\n+ \t\t * fragmentation.\" Of course a PPP implementation should be able\n+ \t\t * to handle overhead added by MPPE - in our case apropriate code\n+ \t\t * is located in drivers/net/ppp_generic.c in the kernel sources.\n+\t\t *\n+ \t\t * According to RFC1661:\n+ \t\t * - when negotiated MRU is less than 1500 octets, a PPP\n+ \t\t *   implementation must still be able to receive at least 1500\n+ \t\t *   octets,\n+ \t\t * - when PFC is negotiated, a PPP implementation is still\n+ \t\t *   required to receive frames with uncompressed protocol field.\n+\t\t *\n+ \t\t * So why not to handle MPPE overhead without changing MTU value?\n+ \t\t * I am sure that RFC3078, unfortunately silently, assumes that.\n+ \t\t */\n+ \n+ \t\t/*\n+ \t\t * We need to decrease the interface MTU by MPPE_PAD\n+ \t\t * because MPPE frames **grow**.  The kernel [must]\n+ \t\t * allocate MPPE_PAD extra bytes in xmit buffers.\n+ \t\t */\n+ /*\n+ \t\tmtu = netif_get_mtu(f->unit);\n+ \t\tif (mtu) {\n+ \t\t    netif_set_mtu(f->unit, mtu - MPPE_PAD);\n+ \t\t} else {\n+\t\t    newret = CONFREJ;\n+ \t\t    if (ccp_wantoptions[f->unit].mppe) {\n+ \t\t\terror(\"Cannot adjust MTU needed by MPPE.\");\n+ \t\t\tlcp_close(f->unit, \"Cannot adjust MTU needed by MPPE.\");\n+ \t\t    }\n+ \t\t}\n+ */\n+ \t\tbreak;\n+  #endif /* MPPE */\n+ \n+\t    case CI_LZS:\n+ \t\tif (!ao->lzs || clen != CILEN_LZS) {\n+ \t\t    newret = CONFREJ;\n+ \t\t    break;\n+ \t\t}\n+ \n+ \t\tho->lzs = 1;\n+\t\tho->lzs_hists = (p[2] << 8) | p[3];\n+ \t\tho->lzs_mode = p[4];\n+\tif ((ho->lzs_hists != ao->lzs_hists) ||\n+\t\t    (ho->lzs_mode != ao->lzs_mode)) {\n+ \t\t    newret = CONFNAK;\n+ \t\t    if (!dont_nak) {\n+ \t\t\tp[2] = ao->lzs_hists >> 8;\n+ \t\t\tp[3] = ao->lzs_hists & 0xff;\n+ \t\t\tp[4] = ao->lzs_mode;\n+\t    } else\n+ \t\t\tbreak;\n+ \t\t}\n+ \n+ \t\tif (p == p0 && ccp_test(f->unit, p, CILEN_LZS, 1) <= 0) {\n+ \t\t    newret = CONFREJ;\n+ \t\t}\n+ \t\tbreak;\n \t    case CI_DEFLATE:\n \t    case CI_DEFLATE_DRAFT:\n \t\tif (!ao->deflate || clen != CILEN_DEFLATE\n@@ -1327,12 +1813,6 @@ ccp_reqci(fsm *f, u_char *p, int *lenp,\n \telse\n \t    *lenp = retp - p0;\n     }\n-#ifdef MPPE\n-    if (ret == CONFREJ && ao->mppe && rej_for_ci_mppe) {\n-\terror(\"MPPE required but peer negotiation failed\");\n-\tlcp_close(f->unit, \"MPPE required but peer negotiation failed\");\n-    }\n-#endif\n     return ret;\n }\n \n@@ -1353,24 +1833,35 @@ method_name(ccp_options *opt, ccp_option\n \tchar *p = result;\n \tchar *q = result + sizeof(result); /* 1 past result */\n \n-\tslprintf(p, q - p, \"MPPE \");\n-\tp += 5;\n-\tif (opt->mppe & MPPE_OPT_128) {\n-\t    slprintf(p, q - p, \"128-bit \");\n-\t    p += 8;\n-\t}\n-\tif (opt->mppe & MPPE_OPT_40) {\n-\t    slprintf(p, q - p, \"40-bit \");\n-\t    p += 7;\n-\t}\n-\tif (opt->mppe & MPPE_OPT_STATEFUL)\n-\t    slprintf(p, q - p, \"stateful\");\n-\telse\n-\t    slprintf(p, q - p, \"stateless\");\n-\n+\tif (opt->mppe) {\n+\t    if (opt->mppc) {\n+\t\tslprintf(p, q - p, \"MPPC/MPPE \");\n+\t\tp += 10;\n+\t    } else {\n+\t\tslprintf(p, q - p, \"MPPE \");\n+\t\tp += 5;\n+\t    }\n+\t    if (opt->mppe_128) {\n+\t\tslprintf(p, q - p, \"128-bit \");\n+\t\tp += 8;\n+\t    } else if (opt->mppe_56) {\n+\t\tslprintf(p, q - p, \"56-bit \");\n+\t\tp += 7;\n+\t    } else if (opt->mppe_40) {\n+\t\tslprintf(p, q - p, \"40-bit \");\n+\t\tp += 7;\n+\t    }\n+\t    if (opt->mppe_stateless)\n+\t\tslprintf(p, q - p, \"stateless\");\n+\t    else\n+\t\tslprintf(p, q - p, \"stateful\");\n+\t} else if (opt->mppc)\n+\t    slprintf(p, q - p, \"MPPC\");\n \tbreak;\n     }\n-#endif\n+#endif /* MPPE */\n+    case CI_LZS:\n+\treturn \"Stac LZS\";\n     case CI_DEFLATE:\n     case CI_DEFLATE_DRAFT:\n \tif (opt2 != NULL && opt2->deflate_size != opt->deflate_size)\n@@ -1425,12 +1916,12 @@ ccp_up(fsm *f)\n     } else if (ANY_COMPRESS(*ho))\n \tnotice(\"%s transmit compression enabled\", method_name(ho, NULL));\n #ifdef MPPE\n-    if (go->mppe) {\n+    if (go->mppe || go->mppc) {\n \tBZERO(mppe_recv_key, MPPE_MAX_KEY_LEN);\n \tBZERO(mppe_send_key, MPPE_MAX_KEY_LEN);\n \tcontinue_networks(f->unit);\t\t/* Bring up IP et al */\n     }\n-#endif\n+#endif /* MPPE */\n }\n \n /*\n@@ -1452,7 +1943,7 @@ ccp_down(fsm *f)\n \t    lcp_close(f->unit, \"MPPE disabled\");\n \t}\n     }\n-#endif\n+#endif /* MPPE */\n }\n \n /*\n@@ -1509,24 +2000,28 @@ ccp_printpkt(u_char *p, int plen,\n #ifdef MPPE\n \t    case CI_MPPE:\n \t\tif (optlen >= CILEN_MPPE) {\n-\t\t    u_char mppe_opts;\n-\n-\t\t    MPPE_CI_TO_OPTS(&p[2], mppe_opts);\n-\t\t    printer(arg, \"mppe %s %s %s %s %s %s%s\",\n-\t\t\t    (p[2] & MPPE_H_BIT)? \"+H\": \"-H\",\n-\t\t\t    (p[5] & MPPE_M_BIT)? \"+M\": \"-M\",\n-\t\t\t    (p[5] & MPPE_S_BIT)? \"+S\": \"-S\",\n-\t\t\t    (p[5] & MPPE_L_BIT)? \"+L\": \"-L\",\n+\t\t    printer(arg, \"mppe %s %s %s %s %s %s\",\n+\t\t\t    (p[2] & MPPE_STATELESS)? \"+H\": \"-H\",\n+\t\t\t    (p[5] & MPPE_56BIT)? \"+M\": \"-M\",\n+\t\t\t    (p[5] & MPPE_128BIT)? \"+S\": \"-S\",\n+\t\t\t    (p[5] & MPPE_40BIT)? \"+L\": \"-L\",\n \t\t\t    (p[5] & MPPE_D_BIT)? \"+D\": \"-D\",\n-\t\t\t    (p[5] & MPPE_C_BIT)? \"+C\": \"-C\",\n-\t\t\t    (mppe_opts & MPPE_OPT_UNKNOWN)? \" +U\": \"\");\n-\t\t    if (mppe_opts & MPPE_OPT_UNKNOWN)\n+\t\t\t    (p[5] & MPPE_MPPC)? \"+C\": \"-C\");\n+\t\t    if ((p[5] & ~(MPPE_56BIT | MPPE_128BIT | MPPE_40BIT |\n+\t\t\t\t  MPPE_D_BIT | MPPE_MPPC)) ||\n+\t\t\t(p[2] & ~MPPE_STATELESS))\n \t\t\tprinter(arg, \" (%.2x %.2x %.2x %.2x)\",\n \t\t\t\tp[2], p[3], p[4], p[5]);\n \t\t    p += CILEN_MPPE;\n \t\t}\n \t\tbreak;\n-#endif\n+#endif /* MPPE */\n+\t    case CI_LZS:\n+\t\tif (optlen >= CILEN_LZS) {\n+\t\t    printer(arg, \"lzs %.2x %.2x %.2x\", p[2], p[3], p[4]);\n+\t\t    p += CILEN_LZS;\n+\t\t}\n+\t\tbreak;\n \t    case CI_DEFLATE:\n \t    case CI_DEFLATE_DRAFT:\n \t\tif (optlen >= CILEN_DEFLATE) {\n@@ -1609,6 +2104,7 @@ ccp_datainput(int unit, u_char *pkt, int\n \t    error(\"Lost compression sync: disabling compression\");\n \t    ccp_close(unit, \"Lost compression sync\");\n #ifdef MPPE\n+\t    /* My module dosn't need this. J.D., 2003-07-06 */\n \t    /*\n \t     * If we were doing MPPE, we must also take the link down.\n \t     */\n@@ -1616,9 +2112,18 @@ ccp_datainput(int unit, u_char *pkt, int\n \t\terror(\"Too many MPPE errors, closing LCP\");\n \t\tlcp_close(unit, \"Too many MPPE errors\");\n \t    }\n-#endif\n+#endif /* MPPE */\n \t} else {\n \t    /*\n+\t     * When LZS or MPPE/MPPC is negotiated we just send CCP_RESETREQ\n+\t     * and don't wait for CCP_RESETACK\n+\t     */\n+\t    if ((ccp_gotoptions[f->unit].method == CI_LZS) ||\n+\t\t(ccp_gotoptions[f->unit].method == CI_MPPE)) {\n+\t\tfsm_sdata(f, CCP_RESETREQ, f->reqid = ++f->id, NULL, 0);\n+\t\treturn;\n+\t    }\n+\t    /*\n \t     * Send a reset-request to reset the peer's compressor.\n \t     * We don't do that if we are still waiting for an\n \t     * acknowledgement to a previous reset-request.\n--- a/pppd/ccp.h\n+++ b/pppd/ccp.h\n@@ -37,9 +37,17 @@ typedef struct ccp_options {\n     bool predictor_2;\t\t/* do Predictor-2? */\n     bool deflate_correct;\t/* use correct code for deflate? */\n     bool deflate_draft;\t\t/* use draft RFC code for deflate? */\n+    bool lzs;\t\t\t/* do Stac LZS? */\n+    bool mppc;\t\t\t/* do MPPC? */\n     u_char mppe;\t\t/* MPPE bitfield */\n+    bool mppe_40;\t\t/* allow 40 bit encryption? */\n+    bool mppe_56;\t\t/* allow 56 bit encryption? */\n+    bool mppe_128;\t\t/* allow 128 bit encryption? */\n+    bool mppe_stateless;\t/* allow stateless encryption */\n     u_short bsd_bits;\t\t/* # bits/code for BSD Compress */\n     u_short deflate_size;\t/* lg(window size) for Deflate */\n+    u_short lzs_mode;\t\t/* LZS check mode */\n+    u_short lzs_hists;\t\t/* number of LZS histories */\n     short method;\t\t/* code for chosen compression method */\n } ccp_options;\n \n--- a/pppd/chap_ms.c\n+++ b/pppd/chap_ms.c\n@@ -964,13 +964,17 @@ set_mppe_enc_types(int policy, int types\n     /*\n      * Disable undesirable encryption types.  Note that we don't ENABLE\n      * any encryption types, to avoid overriding manual configuration.\n+     *\n+     * It seems that 56 bit keys are unsupported in MS-RADIUS (see RFC 2548)\n      */\n     switch(types) {\n \tcase MPPE_ENC_TYPES_RC4_40:\n-\t    ccp_wantoptions[0].mppe &= ~MPPE_OPT_128;\t/* disable 128-bit */\n+\t    ccp_wantoptions[0].mppe_128 = 0;\t/* disable 128-bit */\n+\t    ccp_wantoptions[0].mppe_56 = 0;\t/* disable 56-bit */\n \t    break;\n \tcase MPPE_ENC_TYPES_RC4_128:\n-\t    ccp_wantoptions[0].mppe &= ~MPPE_OPT_40;\t/* disable 40-bit */\n+\t    ccp_wantoptions[0].mppe_56 = 0;\t/* disable 56-bit */\n+\t    ccp_wantoptions[0].mppe_40 = 0;\t/* disable 40-bit */\n \t    break;\n \tdefault:\n \t    break;\n"
  },
  {
    "path": "package/network/services/ppp/patches/203-opt_flags.patch",
    "content": "build: Move optimization flags into a separate variable\n\nIsolate optimization related compiler flags from CFLAGS and move them into a\nseparate COPTS variable so that it is easier to override optimizations from\nthe environment.\n\nSigned-off-by: Jo-Philipp Wich <jo@mein.io>\n\n--- a/pppd/plugins/radius/Makefile.linux\n+++ b/pppd/plugins/radius/Makefile.linux\n@@ -47,13 +47,13 @@ install: all\n \t$(INSTALL) -c -m 444 pppd-radattr.8 $(MANDIR)\n \n radius.so: radius.o libradiusclient.a\n-\t$(CC) $(LDFLAGS) -o radius.so -shared radius.o libradiusclient.a\n+\t$(CC) $(LDFLAGS) -fPIC -o radius.so -shared radius.o libradiusclient.a\n \n radattr.so: radattr.o\n-\t$(CC) $(LDFLAGS) -o radattr.so -shared radattr.o\n+\t$(CC) $(LDFLAGS) -fPIC -o radattr.so -shared radattr.o\n \n radrealms.so: radrealms.o\n-\t$(CC) $(LDFLAGS) -o radrealms.so -shared radrealms.o\n+\t$(CC) $(LDFLAGS) -fPIC -o radrealms.so -shared radrealms.o\n \n CLIENTOBJS = avpair.o buildreq.o config.o dict.o ip_util.o \\\n \tclientid.o sendserver.o lock.o util.o md5.o\n--- a/pppd/plugins/pppoe/Makefile.linux\n+++ b/pppd/plugins/pppoe/Makefile.linux\n@@ -38,7 +38,7 @@ debug.o: debug.c\n \t$(CC) $(CFLAGS) -I../../.. -c -o debug.o debug.c\n \n pppoe.so: plugin.o discovery.o if.o common.o\n-\t$(CC) $(LDFLAGS) -o pppoe.so -shared plugin.o discovery.o if.o common.o\n+\t$(CC) $(LDFLAGS) -fPIC -o pppoe.so -shared plugin.o discovery.o if.o common.o\n \n install: all\n \t$(INSTALL) -d -m 755 $(LIBDIR)\n"
  },
  {
    "path": "package/network/services/ppp/patches/204-radius_config.patch",
    "content": "--- a/pppd/plugins/radius/config.c\n+++ b/pppd/plugins/radius/config.c\n@@ -371,31 +371,37 @@ static int test_config(char *filename)\n \t}\n #endif\n \n+#if 0\n \tif (rc_conf_int(\"login_tries\") <= 0)\n \t{\n \t\terror(\"%s: login_tries <= 0 is illegal\", filename);\n \t\treturn (-1);\n \t}\n+#endif\n \tif (rc_conf_str(\"seqfile\") == NULL)\n \t{\n \t\terror(\"%s: seqfile not specified\", filename);\n \t\treturn (-1);\n \t}\n+#if 0\n \tif (rc_conf_int(\"login_timeout\") <= 0)\n \t{\n \t\terror(\"%s: login_timeout <= 0 is illegal\", filename);\n \t\treturn (-1);\n \t}\n+#endif\n \tif (rc_conf_str(\"mapfile\") == NULL)\n \t{\n \t\terror(\"%s: mapfile not specified\", filename);\n \t\treturn (-1);\n \t}\n+#if 0\n \tif (rc_conf_str(\"nologin\") == NULL)\n \t{\n \t\terror(\"%s: nologin not specified\", filename);\n \t\treturn (-1);\n \t}\n+#endif\n \n \treturn 0;\n }\n--- a/pppd/plugins/radius/options.h\n+++ b/pppd/plugins/radius/options.h\n@@ -31,24 +31,21 @@ typedef struct _option {\n static SERVER acctserver = {0};\n static SERVER authserver = {0};\n \n-int default_tries = 4;\n-int default_timeout = 60;\n-\n static OPTION config_options[] = {\n /* internally used options */\n {\"config_file\",\t\tOT_STR, ST_UNDEF, NULL},\n /* General options */\n {\"auth_order\",\t \tOT_AUO, ST_UNDEF, NULL},\n-{\"login_tries\",\t \tOT_INT, ST_UNDEF, &default_tries},\n-{\"login_timeout\",\tOT_INT, ST_UNDEF, &default_timeout},\n-{\"nologin\",\t\tOT_STR, ST_UNDEF, \"/etc/nologin\"},\n-{\"issue\",\t\tOT_STR, ST_UNDEF, \"/etc/radiusclient/issue\"},\n+{\"login_tries\",\t \tOT_INT, ST_UNDEF, NULL},\n+{\"login_timeout\",\tOT_INT, ST_UNDEF, NULL},\n+{\"nologin\",\t\tOT_STR, ST_UNDEF, NULL},\n+{\"issue\",\t\tOT_STR, ST_UNDEF, NULL},\n /* RADIUS specific options */\n {\"authserver\",\t\tOT_SRV, ST_UNDEF, &authserver},\n {\"acctserver\",\t\tOT_SRV, ST_UNDEF, &acctserver},\n {\"servers\",\t\tOT_STR, ST_UNDEF, NULL},\n {\"dictionary\",\t\tOT_STR, ST_UNDEF, NULL},\n-{\"login_radius\",\tOT_STR, ST_UNDEF, \"/usr/sbin/login.radius\"},\n+{\"login_radius\",\tOT_STR, ST_UNDEF, NULL},\n {\"seqfile\",\t\tOT_STR, ST_UNDEF, NULL},\n {\"mapfile\",\t\tOT_STR, ST_UNDEF, NULL},\n {\"default_realm\",\tOT_STR, ST_UNDEF, NULL},\n"
  },
  {
    "path": "package/network/services/ppp/patches/205-no_exponential_timeout.patch",
    "content": "pppd: Don't use exponential timeout in discovery phase\n\nThis patch removes the exponential timeout increase between PADO or PADS\ndiscovery attempts.\n\nSigned-off-by: Jo-Philipp Wich <jo@mein.io>\n\n--- a/pppd/plugins/pppoe/discovery.c\n+++ b/pppd/plugins/pppoe/discovery.c\n@@ -632,7 +632,9 @@ discovery(PPPoEConnection *conn)\n \tconn->discoveryState = STATE_SENT_PADI;\n \twaitForPADO(conn, timeout);\n \n+#if 0\n \ttimeout *= 2;\n+#endif\n     } while (conn->discoveryState == STATE_SENT_PADI);\n \n     timeout = conn->discoveryTimeout;\n@@ -647,7 +649,9 @@ discovery(PPPoEConnection *conn)\n \tsendPADR(conn);\n \tconn->discoveryState = STATE_SENT_PADR;\n \twaitForPADS(conn, timeout);\n+#if 0\n \ttimeout *= 2;\n+#endif\n     } while (conn->discoveryState == STATE_SENT_PADR);\n \n     if (!conn->seenMaxPayload) {\n"
  },
  {
    "path": "package/network/services/ppp/patches/207-lcp_mtu_max.patch",
    "content": "pppd: Cap MTU to the user configured value\n\nThis patchs caps the calculated MTU value in lcp.c to the user specified \"mru\"\noption value. Without this patch pppd would advertise a different MTU value\ncompared to what is set on the local interface in some cases.\n\nSigned-off-by: Jo-Philipp Wich <jo@mein.io>\n\n--- a/pppd/lcp.c\n+++ b/pppd/lcp.c\n@@ -1862,12 +1862,12 @@ lcp_up(fsm *f)\n      * the interface MTU is set to the lowest of that, the\n      * MTU we want to use, and our link MRU.\n      */\n-    mtu = ho->neg_mru? ho->mru: PPP_MRU;\n+    mtu = MIN(ho->neg_mru? ho->mru: PPP_MRU, ao->mru);\n     mru = go->neg_mru? MAX(wo->mru, go->mru): PPP_MRU;\n #ifdef HAVE_MULTILINK\n     if (!(multilink && go->neg_mrru && ho->neg_mrru))\n #endif /* HAVE_MULTILINK */\n-\tnetif_set_mtu(f->unit, MIN(MIN(mtu, mru), ao->mru));\n+\tnetif_set_mtu(f->unit, MIN(mtu, mru));\n     ppp_send_config(f->unit, mtu,\n \t\t    (ho->neg_asyncmap? ho->asyncmap: 0xffffffff),\n \t\t    ho->neg_pcompression, ho->neg_accompression);\n"
  },
  {
    "path": "package/network/services/ppp/patches/208-fix_status_code.patch",
    "content": "pppd: Do not clobber exit codes on hangup\n\nWhen a modem hangup occurs, pppd unconditionally sets the exit status code\nto EXIT_HANGUP. This patch only sets EXIT_HANGUP if the exit status code is\nnot already set to an error value.\n\nThe motiviation of this patch is to allow applications which remote control\npppd to react properly on errors, e.g. only redial (relaunch pppd) if there\nwas a hangup, but not if the CHAP authentication failed.\n\nSigned-off-by: Jo-Philipp Wich <jo@mein.io>\n\n--- a/pppd/main.c\n+++ b/pppd/main.c\n@@ -1034,7 +1034,8 @@ get_input(void)\n \t}\n \tnotice(\"Modem hangup\");\n \thungup = 1;\n-\tstatus = EXIT_HANGUP;\n+\tif (status == EXIT_OK)\n+\t\tstatus = EXIT_HANGUP;\n \tlcp_lowerdown(0);\t/* serial link is no longer available */\n \tlink_terminated(0);\n \treturn;\n"
  },
  {
    "path": "package/network/services/ppp/patches/300-filter-pcap-includes-lib.patch",
    "content": "build: Add required CFLAGS for libpcap\n\nThis patch adds some flags to required to properly link libpcap within the\nOpenWrt environment.\n\nSigned-off-by: Jo-Philipp Wich <jo@mein.io>\n\n--- a/pppd/Makefile.linux\n+++ b/pppd/Makefile.linux\n@@ -210,8 +210,8 @@ LIBS\t+= -ldl\n endif\n \n ifdef FILTER\n-LIBS    += -lpcap\n-CFLAGS  += -DPPP_FILTER\n+LIBS    += -lpcap -L$(STAGING_DIR)/usr/lib\n+CFLAGS  += -DPPP_FILTER -I$(STAGING_DIR)/usr/include\n endif\n \n ifdef HAVE_INET6\n"
  },
  {
    "path": "package/network/services/ppp/patches/310-precompile_filter.patch",
    "content": "pppd: Implement support for precompiled pcap filters\n\nThis patch implements support for precompiled pcap filters which is useful to\nsupport dial-on-demand on memory constrained embedded devices without having\nto link the full libpcap into pppd to generate the filters during runtime.\n\nTwo new options are introduced; \"precompiled-pass-filter\" specifies a pre-\ncompiled filter file containing rules to match packets which should be passed,\n\"precompiled-active-filter\" specifies a filter file containing rules to match\npackets which are treated as active.\n\nSigned-off-by: Jo-Philipp Wich <jo@mein.io>\n\n--- a/pppd/Makefile.linux\n+++ b/pppd/Makefile.linux\n@@ -51,6 +51,9 @@ MPPE=y\n # and that the kernel driver support PPP packet filtering.\n #FILTER=y\n \n+# Support for precompiled filters\n+PRECOMPILED_FILTER=y\n+\n # Uncomment the next line to enable multilink PPP (enabled by default)\n # Linux distributions: Please leave multilink ENABLED in your builds\n # of pppd!\n@@ -214,6 +217,14 @@ LIBS    += -lpcap -L$(STAGING_DIR)/usr/l\n CFLAGS  += -DPPP_FILTER -I$(STAGING_DIR)/usr/include\n endif\n \n+ifdef PRECOMPILED_FILTER\n+PPPDSRCS += pcap_pcc.c\n+HEADERS  += pcap_pcc.h\n+PPPDOBJS += pcap_pcc.o\n+LIBS\t+= $(STAGING_DIR)/usr/lib/libpcap.a\n+CFLAGS\t+= -DPPP_FILTER -DPPP_PRECOMPILED_FILTER -I$(STAGING_DIR)/usr/include\n+endif\n+\n ifdef HAVE_INET6\n      PPPDSRCS += ipv6cp.c eui64.c\n      HEADERS  += ipv6cp.h eui64.h\n--- a/pppd/options.c\n+++ b/pppd/options.c\n@@ -56,6 +56,7 @@\n \n #ifdef PPP_FILTER\n #include <pcap.h>\n+#include <pcap-bpf.h>\n /*\n  * There have been 3 or 4 different names for this in libpcap CVS, but\n  * this seems to be what they have settled on...\n@@ -168,6 +169,13 @@ static int setlogfile(char **);\n static int loadplugin(char **);\n #endif\n \n+#ifdef PPP_PRECOMPILED_FILTER\n+#include \"pcap_pcc.h\"\n+static int setprecompiledpassfilter(char **);\n+static int setprecompiledactivefilter(char **);\n+#undef PPP_FILTER\n+#endif\n+\n #ifdef PPP_FILTER\n static int setpassfilter(char **);\n static int setactivefilter(char **);\n@@ -360,6 +368,14 @@ option_t general_options[] = {\n       \"set filter for active pkts\", OPT_PRIO },\n #endif\n \n+#ifdef PPP_PRECOMPILED_FILTER\n+    { \"precompiled-pass-filter\", 1, setprecompiledpassfilter,\n+      \"set precompiled filter for packets to pass\", OPT_PRIO },\n+\n+    { \"precompiled-active-filter\", 1, setprecompiledactivefilter,\n+      \"set precompiled filter for active pkts\", OPT_PRIO },\n+#endif\n+\n #ifdef MAXOCTETS\n     { \"maxoctets\", o_int, &maxoctets,\n       \"Set connection traffic limit\",\n@@ -1468,6 +1484,27 @@ callfile(char **argv)\n     return ok;\n }\n \n+#ifdef PPP_PRECOMPILED_FILTER\n+/*\n+ * setprecompiledpassfilter - Set the pass filter for packets using a\n+ * precompiled expression\n+ */\n+static int\n+setprecompiledpassfilter(char **argv)\n+{\n+    return pcap_pre_compiled (*argv, &pass_filter);\n+}\n+\n+/*\n+ * setactivefilter - Set the active filter for packets\n+ */\n+static int\n+setprecompiledactivefilter(char **argv)\n+{\n+    return pcap_pre_compiled (*argv, &active_filter);\n+}\n+#endif\n+\n #ifdef PPP_FILTER\n /*\n  * setpassfilter - Set the pass filter for packets\n--- /dev/null\n+++ b/pppd/pcap_pcc.c\n@@ -0,0 +1,74 @@\n+#include <pcap.h>\n+#include <pcap-bpf.h>\n+#include <stdio.h>\n+#include <stdlib.h>\n+#include <string.h>\n+#include <errno.h>\n+#include \"pppd.h\"\n+\n+int pcap_pre_compiled (char * fname, struct bpf_program *p)\n+{\n+    char buf[128];\n+    int line = 0, size = 0, index=0, ret=1;\n+    FILE *f = fopen (fname, \"r\");\n+    if (!f)\n+    {\n+       option_error(\"error opening precompiled active-filter '%s': %s\",\n+                    fname, strerror (errno));\n+       return 0;\n+    }\n+    while (fgets (buf, 127, f))\n+    {\n+       line++;\n+       if (*buf == '#')\n+           continue;\n+       if (size)\n+       {\n+           /*\n+             struct bpf_insn {\n+             u_short   code;\n+             u_char    jt;\n+             u_char    jf;\n+             bpf_int32 k;\n+             }\n+           */\n+           struct bpf_insn * insn = & p->bf_insns[index];\n+           unsigned code, jt, jf, k;\n+           if (sscanf (buf, \"%u %u %u %u\", &code, &jt, &jf, &k) != 4)\n+           {\n+               goto err;\n+           }\n+           insn->code = code;\n+           insn->jt = jt;\n+           insn->jf = jf;\n+           insn->k  = k;\n+           index++;\n+       }\n+       else\n+       {\n+           if (sscanf (buf, \"%u\", &size) != 1)\n+           {\n+               goto err;\n+           }\n+           p->bf_len = size;\n+           p->bf_insns = (struct bpf_insn *) \n+               malloc (size * sizeof (struct bpf_insn));\n+       }\n+    } \n+    if (size != index)\n+    {\n+       option_error(\"error in precompiled active-filter,\"\n+                    \" expected %d expressions, got %dn\",\n+                    size, index);\n+       ret = 0;\n+    }\n+    fclose(f);\n+    return ret;\n+\n+err:\n+  option_error(\"error in precompiled active-filter\"\n+              \" expression line %s:%d (wrong size)\\n\", \n+              fname, line);\n+  fclose (f);\n+  return 0;\n+}\n--- /dev/null\n+++ b/pppd/pcap_pcc.h\n@@ -0,0 +1,7 @@\n+#ifndef PCAP_PCC_H\n+#define PCAP_PCC_H\n+\n+#include <pcap.h>\n+\n+int pcap_pre_compiled (char * fname, struct bpf_program *p);\n+#endif /* PCAP_PCC_H */\n"
  },
  {
    "path": "package/network/services/ppp/patches/321-multilink_support_custom_iface_names.patch",
    "content": "From: George Kashperko <george@znau.edu.ua>\n\nMake mlppp support more generic interface naming other than pppX\nSigned-off-by: George Kashperko <george@znau.edu.ua>\n---\n pppd/multilink.c |   55 +++++++++++++++++++++++++++++++++------------\n pppd/sys-linux.c |   12 +++++++++\n 2 files changed, 53 insertions(+), 14 deletions(-)\n--- a/pppd/multilink.c\n+++ b/pppd/multilink.c\n@@ -35,6 +35,7 @@\n #include <signal.h>\n #include <netinet/in.h>\n #include <unistd.h>\n+#include <net/if.h>\n \n #include \"pppd.h\"\n #include \"fsm.h\"\n@@ -56,7 +57,8 @@ static void iterate_bundle_links(void (*\n \n static int get_default_epdisc(struct epdisc *);\n static int parse_num(char *str, const char *key, int *valp);\n-static int owns_unit(TDB_DATA pid, int unit);\n+static int parse_str(char *str, const char *key, char *buf, int buflen);\n+static int owns_link(TDB_DATA pid, char *ifname);\n \n #define set_ip_epdisc(ep, addr) do {\t\\\n \tep->length = 4;\t\t\t\\\n@@ -197,35 +199,38 @@ mp_join_bundle(void)\n \tkey.dptr = bundle_id;\n \tkey.dsize = p - bundle_id;\n \tpid = tdb_fetch(pppdb, key);\n+\n \tif (pid.dptr != NULL) {\n+\t\tchar tmp[IFNAMSIZ];\n+\n \t\t/* bundle ID exists, see if the pppd record exists */\n \t\trec = tdb_fetch(pppdb, pid);\n+\n \t\tif (rec.dptr != NULL && rec.dsize > 0) {\n \t\t\t/* make sure the string is null-terminated */\n \t\t\trec.dptr[rec.dsize-1] = 0;\n-\t\t\t/* parse the interface number */\n-\t\t\tparse_num(rec.dptr, \"UNIT=\", &unit);\n+\n \t\t\t/* check the pid value */\n \t\t\tif (!parse_num(rec.dptr, \"PPPD_PID=\", &pppd_pid)\n+\t\t\t    || !parse_str(rec.dptr, \"IFNAME=\", tmp, sizeof(tmp))\n+\t\t\t    || !parse_num(rec.dptr, \"IFUNIT=\", &unit)\n \t\t\t    || !process_exists(pppd_pid)\n-\t\t\t    || !owns_unit(pid, unit))\n+\t\t\t    || !owns_link(pid, tmp))\n \t\t\t\tunit = -1;\n \t\t\tfree(rec.dptr);\n \t\t}\n \t\tfree(pid.dptr);\n-\t}\n \n-\tif (unit >= 0) {\n \t\t/* attach to existing unit */\n-\t\tif (bundle_attach(unit)) {\n+\t\tif (unit >= 0 && bundle_attach(unit)) {\n \t\t\tset_ifunit(0);\n \t\t\tscript_setenv(\"BUNDLE\", bundle_id + 7, 0);\n \t\t\tmake_bundle_links(1);\n \t\t\tunlock_db();\n-\t\t\tinfo(\"Link attached to %s\", ifname);\n+\t\t\tinfo(\"Link attached to %s\", tmp);\n \t\t\treturn 1;\n+\t\t\t/* attach failed because bundle doesn't exist */\n \t\t}\n-\t\t/* attach failed because bundle doesn't exist */\n \t}\n \n \t/* we have to make a new bundle */\n@@ -405,20 +410,39 @@ parse_num(char *str, const char *key, in\n \treturn 0;\n }\n \n+static int\n+parse_str(char *str, const char *key, char *buf, int buflen)\n+{\n+\tchar *p, *endp;\n+\tint i;\n+\n+\tp = strstr(str, key);\n+\tif (p) {\n+\t\tp += strlen(key);\n+\t\twhile (--buflen && *p != 0 && *p != ';')\n+\t\t\t*(buf++) = *(p++);\n+\t\t*buf = 0;\n+\t\treturn 1;\n+\t}\n+\treturn 0;\n+}\n+\n /*\n- * Check whether the pppd identified by `key' still owns ppp unit `unit'.\n+ * Check whether the pppd identified by `key' still owns ppp link `ifname'.\n  */\n static int\n-owns_unit(TDB_DATA key, int unit)\n+owns_link(TDB_DATA key, char *ifname)\n {\n-\tchar ifkey[32];\n+\tchar ifkey[7 + IFNAMSIZ];\n \tTDB_DATA kd, vd;\n \tint ret = 0;\n \n-\tslprintf(ifkey, sizeof(ifkey), \"UNIT=%d\", unit);\n+\tslprintf(ifkey, sizeof(ifkey), \"IFNAME=%s\", ifname);\n+\n \tkd.dptr = ifkey;\n \tkd.dsize = strlen(ifkey);\n \tvd = tdb_fetch(pppdb, kd);\n+\n \tif (vd.dptr != NULL) {\n \t\tret = vd.dsize == key.dsize\n \t\t\t&& memcmp(vd.dptr, key.dptr, vd.dsize) == 0;\n--- a/pppd/sys-linux.c\n+++ b/pppd/sys-linux.c\n@@ -706,6 +706,16 @@ void cfg_bundle(int mrru, int mtru, int\n \tadd_fd(ppp_dev_fd);\n }\n \n+static void\n+setenv_ifunit(void)\n+{\n+#ifdef USE_TDB\n+\tchar tmp[11];\n+\tslprintf(tmp, sizeof(tmp), \"%d\", ifunit);\n+\tscript_setenv(\"IFUNIT\", tmp, 0);\n+#endif\n+}\n+\n /*\n  * make_new_bundle - create a new PPP unit (i.e. a bundle)\n  * and connect our channel to it.  This should only get called\n@@ -724,6 +734,8 @@ void make_new_bundle(int mrru, int mtru,\n \n \t/* set the mrru and flags */\n \tcfg_bundle(mrru, mtru, rssn, tssn);\n+\n+\tsetenv_ifunit();\n }\n \n /*\n"
  },
  {
    "path": "package/network/services/ppp/patches/330-retain_foreign_default_routes.patch",
    "content": "pppd: Retain foreign default routes on Linux\n\nOn Linux, when pppd attempts to delete its default route it does not fill\nthe rt_dev field of the struct rtentry used to match the system default route.\nAs a consequence, pppd happily deletes any default route even if it belongs\nto another interface.\n\nThis patch makes pppd fill out the rt_dev field so that only own default\nroutes are ever matched.\n\nSigned-off-by: Jo-Philipp Wich <jo@mein.io>\n\n--- a/pppd/sys-linux.c\n+++ b/pppd/sys-linux.c\n@@ -1770,6 +1770,7 @@ int cifdefaultroute (int unit, u_int32_t\n \tSIN_ADDR(rt.rt_genmask) = 0L;\n     }\n \n+    rt.rt_dev = ifname;\n     rt.rt_flags = RTF_UP;\n     if (ioctl(sock_fd, SIOCDELRT, &rt) < 0 && errno != ESRCH) {\n \tif (still_ppp()) {\n"
  },
  {
    "path": "package/network/services/ppp/patches/340-populate_default_gateway.patch",
    "content": "pppd: Fill in default gateway on Linux\n\nOn Linux, when pppd creates the default route, it does not set the peer\naddress as gateway, leading to a default route without gateway address.\n\nThis behaviour breaks various downstream programs which attempt to infer\nthe default gateway IP address from the system default route entry.\n\nThis patch addresses the issue by filling in the peer address as gateway\nwhen generating the default route entry.\n\nSigned-off-by: Jo-Philipp Wich <jo@mein.io>\n\n--- a/pppd/sys-linux.c\n+++ b/pppd/sys-linux.c\n@@ -1720,6 +1720,9 @@ int sifdefaultroute (int unit, u_int32_t\n     memset (&rt, 0, sizeof (rt));\n     SET_SA_FAMILY (rt.rt_dst, AF_INET);\n \n+    SET_SA_FAMILY(rt.rt_gateway, AF_INET);\n+    SIN_ADDR(rt.rt_gateway) = gateway;\n+\n     rt.rt_dev = ifname;\n     rt.rt_metric = dfl_route_metric + 1; /* +1 for binary compatibility */\n \n@@ -1728,7 +1731,7 @@ int sifdefaultroute (int unit, u_int32_t\n \tSIN_ADDR(rt.rt_genmask) = 0L;\n     }\n \n-    rt.rt_flags = RTF_UP;\n+    rt.rt_flags = RTF_UP | RTF_GATEWAY;\n     if (ioctl(sock_fd, SIOCADDRT, &rt) < 0) {\n \tif ( ! ok_error ( errno ))\n \t    error(\"default route ioctl(SIOCADDRT): %m\");\n"
  },
  {
    "path": "package/network/services/ppp/patches/400-simplify_kernel_checks.patch",
    "content": "pppd: Remove runtime kernel checks\n\nOn embedded system distributions the required kernel features for pppd are\nmore or less guaranteed to be present, so there is not much point in\nperforming runtime checks, it just increases the binary size.\n\nThis patch removes the runtime kernel feature checks.\n\nSigned-off-by: Jo-Philipp Wich <jo@mein.io>\n\n--- a/pppd/sys-linux.c\n+++ b/pppd/sys-linux.c\n@@ -206,7 +206,7 @@ static int driver_is_old       = 0;\n static int restore_term        = 0;\t/* 1 => we've munged the terminal */\n static struct termios inittermios;\t/* Initial TTY termios */\n \n-int new_style_driver = 0;\n+static const int new_style_driver = 1;\n \n static char loop_name[20];\n static unsigned char inbuf[512]; /* buffer for chars read from loopback */\n@@ -225,8 +225,8 @@ static int\tlooped;\t\t\t/* 1 if using loop\n static int\tlink_mtu;\t\t/* mtu for the link (not bundle) */\n \n static struct utsname utsname;\t/* for the kernel version */\n-static int kernel_version;\n #define KVERSION(j,n,p)\t((j)*1000000 + (n)*1000 + (p))\n+static const int kernel_version = KVERSION(2,6,37);\n \n #define MAX_IFS\t\t100\n \n@@ -1455,11 +1455,12 @@ int ccp_fatal_error (int unit)\n  *\n  * path_to_procfs - find the path to the proc file system mount point\n  */\n-static char proc_path[MAXPATHLEN];\n-static int proc_path_len;\n+static char proc_path[MAXPATHLEN] = \"/proc\";\n+static int proc_path_len = 5;\n \n static char *path_to_procfs(const char *tail)\n {\n+#if 0\n     struct mntent *mntent;\n     FILE *fp;\n \n@@ -1481,6 +1482,7 @@ static char *path_to_procfs(const char *\n \t    fclose (fp);\n \t}\n     }\n+#endif\n \n     strlcpy(proc_path + proc_path_len, tail,\n \t    sizeof(proc_path) - proc_path_len);\n@@ -2365,15 +2367,19 @@ int ppp_available(void)\n     int    my_version, my_modification, my_patch;\n     int osmaj, osmin, ospatch;\n \n+#if 0\n     /* get the kernel version now, since we are called before sys_init */\n     uname(&utsname);\n     osmaj = osmin = ospatch = 0;\n     sscanf(utsname.release, \"%d.%d.%d\", &osmaj, &osmin, &ospatch);\n     kernel_version = KVERSION(osmaj, osmin, ospatch);\n+#endif\n \n     fd = open(\"/dev/ppp\", O_RDWR);\n     if (fd >= 0) {\n+#if 0\n \tnew_style_driver = 1;\n+#endif\n \n \t/* XXX should get from driver */\n \tdriver_version = 2;\n@@ -2433,6 +2439,7 @@ int ppp_available(void)\n \n     if (ok && ((ifr.ifr_hwaddr.sa_family & ~0xFF) != ARPHRD_PPP))\n \tok = 0;\n+\treturn ok;\n \n /*\n  *  This is the PPP device. Validate the version of the driver at this\n@@ -3106,6 +3113,7 @@ get_pty(int *master_fdp, int *slave_fdp,\n     }\n #endif /* TIOCGPTN */\n \n+#if 0\n     if (sfd < 0) {\n \t/* the old way - scan through the pty name space */\n \tfor (i = 0; i < 64; ++i) {\n@@ -3124,6 +3132,7 @@ get_pty(int *master_fdp, int *slave_fdp,\n \t    }\n \t}\n     }\n+#endif\n \n     if (sfd < 0)\n \treturn 0;\n--- a/pppd/plugins/pppoatm/pppoatm.c\n+++ b/pppd/plugins/pppoatm/pppoatm.c\n@@ -171,14 +171,6 @@ static void disconnect_pppoatm(void)\n \n void plugin_init(void)\n {\n-#ifdef linux\n-\textern int new_style_driver;\t/* From sys-linux.c */\n-\tif (!ppp_available() && !new_style_driver)\n-\t\tfatal(\"Kernel doesn't support ppp_generic - \"\n-\t\t    \"needed for PPPoATM\");\n-#else\n-\tfatal(\"No PPPoATM support on this OS\");\n-#endif\n \tadd_options(pppoa_options);\n }\n \n--- a/pppd/plugins/pppoe/plugin.c\n+++ b/pppd/plugins/pppoe/plugin.c\n@@ -58,9 +58,6 @@ static char const RCSID[] =\n \n char pppd_version[] = VERSION;\n \n-/* From sys-linux.c in pppd -- MUST FIX THIS! */\n-extern int new_style_driver;\n-\n char *pppd_pppoe_service = NULL;\n static char *acName = NULL;\n static char *existingSession = NULL;\n@@ -407,10 +404,6 @@ PPPoEDevnameHook(char *cmd, char **argv,\n void\n plugin_init(void)\n {\n-    if (!ppp_available() && !new_style_driver) {\n-\tfatal(\"Linux kernel does not support PPPoE -- are you running 2.4.x?\");\n-    }\n-\n     add_options(Options);\n \n     info(\"PPPoE plugin from pppd %s\", VERSION);\n--- a/pppd/plugins/pppol2tp/pppol2tp.c\n+++ b/pppd/plugins/pppol2tp/pppol2tp.c\n@@ -490,12 +490,7 @@ static void pppol2tp_cleanup(void)\n \n void plugin_init(void)\n {\n-#if defined(__linux__)\n-\textern int new_style_driver;\t/* From sys-linux.c */\n-\tif (!ppp_available() && !new_style_driver)\n-\t\tfatal(\"Kernel doesn't support ppp_generic - \"\n-\t\t    \"needed for PPPoL2TP\");\n-#else\n+#if !defined(__linux__)\n \tfatal(\"No PPPoL2TP support on this OS\");\n #endif\n \tadd_options(pppol2tp_options);\n"
  },
  {
    "path": "package/network/services/ppp/patches/401-no_record_file.patch",
    "content": "pppd: Remove the \"record\" option\n\nOn many embedded systems there is not enough space to record PPP session\ninformation to the permanent storage, therfore remove this option.\n\nSigned-off-by: Jo-Philipp Wich <jo@mein.io>\n\n--- a/pppd/pppd.h\n+++ b/pppd/pppd.h\n@@ -317,7 +317,6 @@ extern int\tholdoff;\t/* Dead time before\n extern bool\tholdoff_specified; /* true if user gave a holdoff value */\n extern bool\tnotty;\t\t/* Stdin/out is not a tty */\n extern char\t*pty_socket;\t/* Socket to connect to pty */\n-extern char\t*record_file;\t/* File to record chars sent/received */\n extern bool\tsync_serial;\t/* Device is synchronous serial device */\n extern int\tmaxfail;\t/* Max # of unsuccessful connection attempts */\n extern char\tlinkname[MAXPATHLEN]; /* logical name for link */\n--- a/pppd/tty.c\n+++ b/pppd/tty.c\n@@ -143,7 +143,7 @@ char\t*disconnect_script = NULL; /* Scrip\n char\t*welcomer = NULL;\t/* Script to run after phys link estab. */\n char\t*ptycommand = NULL;\t/* Command to run on other side of pty */\n bool\tnotty = 0;\t\t/* Stdin/out is not a tty */\n-char\t*record_file = NULL;\t/* File to record chars sent/received */\n+static  char\t*const record_file = NULL;\t/* File to record chars sent/received */\n int\tmax_data_rate;\t\t/* max bytes/sec through charshunt */\n bool\tsync_serial = 0;\t/* Device is synchronous serial device */\n char\t*pty_socket = NULL;\t/* Socket to connect to pty */\n@@ -199,8 +199,10 @@ option_t tty_options[] = {\n       \"Send and receive over socket, arg is host:port\",\n       OPT_PRIO | OPT_DEVNAM },\n \n+#if 0\n     { \"record\", o_string, &record_file,\n       \"Record characters sent/received to file\", OPT_PRIO },\n+#endif\n \n     { \"crtscts\", o_int, &crtscts,\n       \"Set hardware (RTS/CTS) flow control\",\n"
  },
  {
    "path": "package/network/services/ppp/patches/403-no_wtmp.patch",
    "content": "pppd: Disable wtmp support\n\nMany uClibc based environments lack wtmp and utmp support, therfore remove\nthe code updating the wtmp information.\n\nSigned-off-by: Jo-Philipp Wich <jo@mein.io>\n\n--- a/pppd/sys-linux.c\n+++ b/pppd/sys-linux.c\n@@ -2503,6 +2503,7 @@ int ppp_available(void)\n \n void logwtmp (const char *line, const char *name, const char *host)\n {\n+#if 0\n     struct utmp ut, *utp;\n     pid_t  mypid = getpid();\n #if __GLIBC__ < 2\n@@ -2568,6 +2569,7 @@ void logwtmp (const char *line, const ch\n \tclose (wtmp);\n     }\n #endif\n+#endif\n }\n #endif /* HAVE_LOGWTMP */\n \n"
  },
  {
    "path": "package/network/services/ppp/patches/404-remove_obsolete_protocol_names.patch",
    "content": "pppd: Remove historical protocol names\n\nRemove a number of historical protocol entries from pppd's builtin list, this\nreduced the binary size without loss of features.\n\nSigned-off-by: Jo-Philipp Wich <jo@mein.io>\n\n--- a/pppd/main.c\n+++ b/pppd/main.c\n@@ -866,14 +866,17 @@ struct protocol_list {\n     const char\t*name;\n } protocol_list[] = {\n     { 0x21,\t\"IP\" },\n+#if 0\n     { 0x23,\t\"OSI Network Layer\" },\n     { 0x25,\t\"Xerox NS IDP\" },\n     { 0x27,\t\"DECnet Phase IV\" },\n     { 0x29,\t\"Appletalk\" },\n     { 0x2b,\t\"Novell IPX\" },\n+#endif\n     { 0x2d,\t\"VJ compressed TCP/IP\" },\n     { 0x2f,\t\"VJ uncompressed TCP/IP\" },\n     { 0x31,\t\"Bridging PDU\" },\n+#if 0\n     { 0x33,\t\"Stream Protocol ST-II\" },\n     { 0x35,\t\"Banyan Vines\" },\n     { 0x39,\t\"AppleTalk EDDP\" },\n@@ -887,8 +890,11 @@ struct protocol_list {\n     { 0x49,\t\"Serial Data Transport Protocol (PPP-SDTP)\" },\n     { 0x4b,\t\"SNA over 802.2\" },\n     { 0x4d,\t\"SNA\" },\n+#endif\n     { 0x4f,\t\"IP6 Header Compression\" },\n+#if 0\n     { 0x51,\t\"KNX Bridging Data\" },\n+#endif\n     { 0x53,\t\"Encryption\" },\n     { 0x55,\t\"Individual Link Encryption\" },\n     { 0x57,\t\"IPv6\" },\n@@ -899,12 +905,15 @@ struct protocol_list {\n     { 0x65,\t\"RTP IPHC Compressed non-TCP\" },\n     { 0x67,\t\"RTP IPHC Compressed UDP 8\" },\n     { 0x69,\t\"RTP IPHC Compressed RTP 8\" },\n+#if 0\n     { 0x6f,\t\"Stampede Bridging\" },\n     { 0x73,\t\"MP+\" },\n     { 0xc1,\t\"NTCITS IPI\" },\n+#endif\n     { 0xfb,\t\"single-link compression\" },\n     { 0xfd,\t\"Compressed Datagram\" },\n     { 0x0201,\t\"802.1d Hello Packets\" },\n+#if 0\n     { 0x0203,\t\"IBM Source Routing BPDU\" },\n     { 0x0205,\t\"DEC LANBridge100 Spanning Tree\" },\n     { 0x0207,\t\"Cisco Discovery Protocol\" },\n@@ -916,15 +925,19 @@ struct protocol_list {\n     { 0x0231,\t\"Luxcom\" },\n     { 0x0233,\t\"Sigma Network Systems\" },\n     { 0x0235,\t\"Apple Client Server Protocol\" },\n+#endif\n     { 0x0281,\t\"MPLS Unicast\" },\n     { 0x0283,\t\"MPLS Multicast\" },\n+#if 0\n     { 0x0285,\t\"IEEE p1284.4 standard - data packets\" },\n     { 0x0287,\t\"ETSI TETRA Network Protocol Type 1\" },\n+#endif\n     { 0x0289,\t\"Multichannel Flow Treatment Protocol\" },\n     { 0x2063,\t\"RTP IPHC Compressed TCP No Delta\" },\n     { 0x2065,\t\"RTP IPHC Context State\" },\n     { 0x2067,\t\"RTP IPHC Compressed UDP 16\" },\n     { 0x2069,\t\"RTP IPHC Compressed RTP 16\" },\n+#if 0\n     { 0x4001,\t\"Cray Communications Control Protocol\" },\n     { 0x4003,\t\"CDPD Mobile Network Registration Protocol\" },\n     { 0x4005,\t\"Expand accelerator protocol\" },\n@@ -935,8 +948,10 @@ struct protocol_list {\n     { 0x4023,\t\"RefTek Protocol\" },\n     { 0x4025,\t\"Fibre Channel\" },\n     { 0x4027,\t\"EMIT Protocols\" },\n+#endif\n     { 0x405b,\t\"Vendor-Specific Protocol (VSP)\" },\n     { 0x8021,\t\"Internet Protocol Control Protocol\" },\n+#if 0\n     { 0x8023,\t\"OSI Network Layer Control Protocol\" },\n     { 0x8025,\t\"Xerox NS IDP Control Protocol\" },\n     { 0x8027,\t\"DECnet Phase IV Control Protocol\" },\n@@ -945,7 +960,9 @@ struct protocol_list {\n     { 0x8031,\t\"Bridging NCP\" },\n     { 0x8033,\t\"Stream Protocol Control Protocol\" },\n     { 0x8035,\t\"Banyan Vines Control Protocol\" },\n+#endif\n     { 0x803d,\t\"Multi-Link Control Protocol\" },\n+#if 0\n     { 0x803f,\t\"NETBIOS Framing Control Protocol\" },\n     { 0x8041,\t\"Cisco Systems Control Protocol\" },\n     { 0x8043,\t\"Ascom Timeplex\" },\n@@ -954,18 +971,24 @@ struct protocol_list {\n     { 0x8049,\t\"Serial Data Control Protocol (PPP-SDCP)\" },\n     { 0x804b,\t\"SNA over 802.2 Control Protocol\" },\n     { 0x804d,\t\"SNA Control Protocol\" },\n+#endif\n     { 0x804f,\t\"IP6 Header Compression Control Protocol\" },\n+#if 0\n     { 0x8051,\t\"KNX Bridging Control Protocol\" },\n+#endif\n     { 0x8053,\t\"Encryption Control Protocol\" },\n     { 0x8055,\t\"Individual Link Encryption Control Protocol\" },\n     { 0x8057,\t\"IPv6 Control Protocol\" },\n     { 0x8059,\t\"PPP Muxing Control Protocol\" },\n     { 0x805b,\t\"Vendor-Specific Network Control Protocol (VSNCP)\" },\n+#if 0\n     { 0x806f,\t\"Stampede Bridging Control Protocol\" },\n     { 0x8073,\t\"MP+ Control Protocol\" },\n     { 0x80c1,\t\"NTCITS IPI Control Protocol\" },\n+#endif\n     { 0x80fb,\t\"Single Link Compression Control Protocol\" },\n     { 0x80fd,\t\"Compression Control Protocol\" },\n+#if 0\n     { 0x8207,\t\"Cisco Discovery Protocol Control\" },\n     { 0x8209,\t\"Netcs Twin Routing\" },\n     { 0x820b,\t\"STP - Control Protocol\" },\n@@ -974,24 +997,29 @@ struct protocol_list {\n     { 0x8281,\t\"MPLSCP\" },\n     { 0x8285,\t\"IEEE p1284.4 standard - Protocol Control\" },\n     { 0x8287,\t\"ETSI TETRA TNP1 Control Protocol\" },\n+#endif\n     { 0x8289,\t\"Multichannel Flow Treatment Protocol\" },\n     { 0xc021,\t\"Link Control Protocol\" },\n     { 0xc023,\t\"Password Authentication Protocol\" },\n     { 0xc025,\t\"Link Quality Report\" },\n+#if 0\n     { 0xc027,\t\"Shiva Password Authentication Protocol\" },\n     { 0xc029,\t\"CallBack Control Protocol (CBCP)\" },\n     { 0xc02b,\t\"BACP Bandwidth Allocation Control Protocol\" },\n     { 0xc02d,\t\"BAP\" },\n+#endif\n     { 0xc05b,\t\"Vendor-Specific Authentication Protocol (VSAP)\" },\n     { 0xc081,\t\"Container Control Protocol\" },\n     { 0xc223,\t\"Challenge Handshake Authentication Protocol\" },\n     { 0xc225,\t\"RSA Authentication Protocol\" },\n     { 0xc227,\t\"Extensible Authentication Protocol\" },\n+#if 0\n     { 0xc229,\t\"Mitsubishi Security Info Exch Ptcl (SIEP)\" },\n     { 0xc26f,\t\"Stampede Bridging Authorization Protocol\" },\n     { 0xc281,\t\"Proprietary Authentication Protocol\" },\n     { 0xc283,\t\"Proprietary Authentication Protocol\" },\n     { 0xc481,\t\"Proprietary Node ID Authentication Protocol\" },\n+#endif\n     { 0,\tNULL },\n };\n \n"
  },
  {
    "path": "package/network/services/ppp/patches/405-no_multilink_option.patch",
    "content": "pppd: Support \"nomp\" option even if multilink support is off\n\nThis patch moves the \"nomp\" option entry outside of the defines protecting\nthe multilink specific code. The motivation is to allow \"nomp\" even if pppd\ndoes not support multilink, so that controlling programs can unconditionally\npass it to pppd regardless of the compile time features.\n\nSigned-off-by: Jo-Philipp Wich <jo@mein.io>\n\n--- a/pppd/options.c\n+++ b/pppd/options.c\n@@ -348,13 +348,14 @@ option_t general_options[] = {\n       \"Enable multilink operation\", OPT_PRIOSUB | OPT_ALIAS | 1 },\n     { \"nomultilink\", o_bool, &multilink,\n       \"Disable multilink operation\", OPT_PRIOSUB | 0 },\n-    { \"nomp\", o_bool, &multilink,\n-      \"Disable multilink operation\", OPT_PRIOSUB | OPT_ALIAS | 0 },\n \n     { \"bundle\", o_string, &bundle_name,\n       \"Bundle name for multilink\", OPT_PRIO },\n #endif /* HAVE_MULTILINK */\n \n+    { \"nomp\", o_bool, &multilink,\n+      \"Disable multilink operation\", OPT_PRIOSUB | OPT_ALIAS | 0 },\n+\n #ifdef PLUGIN\n     { \"plugin\", o_special, (void *)loadplugin,\n       \"Load a plug-in module into pppd\", OPT_PRIV | OPT_A2LIST },\n"
  },
  {
    "path": "package/network/services/ppp/patches/500-add-pptp-plugin.patch",
    "content": "--- a/configure\n+++ b/configure\n@@ -133,7 +133,7 @@ if [ -d \"$ksrc\" ]; then\n     mkmkf $ksrc/Makedefs$compiletype Makedefs.com\n     for dir in pppd pppstats chat pppdump pppd/plugins pppd/plugins/pppoe \\\n \t       pppd/plugins/radius pppd/plugins/pppoatm \\\n-\t       pppd/plugins/pppol2tp; do\n+\t       pppd/plugins/pppol2tp pppd/plugins/pptp ; do\n \tmkmkf $dir/Makefile.$makext $dir/Makefile\n     done\n     if [ -f $ksrc/Makefile.$makext$archvariant ]; then\n--- a/pppd/plugins/Makefile.linux\n+++ b/pppd/plugins/Makefile.linux\n@@ -14,7 +14,7 @@ INSTALL\t= install\n # EAP-TLS\n CFLAGS += -DUSE_EAPTLS=1\n \n-SUBDIRS := pppoe pppoatm pppol2tp\n+SUBDIRS := pppoe pppoatm pppol2tp pptp\n # Uncomment the next line to include the radius authentication plugin\n SUBDIRS += radius\n PLUGINS := minconn.so passprompt.so passwordfd.so winbind.so\n--- /dev/null\n+++ b/pppd/plugins/pptp/Makefile.linux\n@@ -0,0 +1,31 @@\n+#\n+# This program may be distributed according to the terms of the GNU\n+# General Public License, version 2 or (at your option) any later version.\n+#\n+# $Id: Makefile.linux,v 1.9 2012/05/04 21:48:00 dgolle Exp $\n+#***********************************************************************\n+\n+DESTDIR = $(INSTROOT)@DESTDIR@\n+LIBDIR = $(DESTDIR)/lib/pppd/$(PPPDVERSION)\n+\n+PPPDVERSION = $(shell awk -F '\"' '/VERSION/ { print $$2; }' ../../patchlevel.h)\n+\n+INSTALL\t= install\n+\n+COPTS=-O2 -g\n+CFLAGS  = $(COPTS) -I. -I../.. -I../../../include -fPIC -DPPPD_VERSION=\\\"$(PPPDVERSION)\\\"\n+all: pptp.so\n+\n+%.o: %.c\n+\t$(CC) $(CFLAGS) -c -o $@ $<\n+\n+pptp.so: dirutil.o orckit_quirks.o pptp.o pptp_callmgr.o pptp_ctrl.o pptp_quirks.o util.o vector.o\n+\t$(CC) -o pptp.so -shared dirutil.o orckit_quirks.o pptp.o pptp_callmgr.o pptp_ctrl.o pptp_quirks.o util.o vector.o\n+\n+install: all\n+\t$(INSTALL) -d -m 755 $(LIBDIR)\n+\t$(INSTALL) -c -m 4550 pptp.so $(LIBDIR)\n+\n+clean:\n+\trm -f *.o *.so\n+\n--- /dev/null\n+++ b/pppd/plugins/pptp/dirutil.c\n@@ -0,0 +1,68 @@\n+/* dirutil.c ... directory utilities.\n+ *               C. Scott Ananian <cananian@alumni.princeton.edu>\n+ *\n+ * $Id: dirutil.c,v 1.2 2003/06/17 17:25:47 reink Exp $\n+ */\n+\n+#include <sys/stat.h>\n+#include <sys/types.h>\n+#include <unistd.h>\n+#include <string.h>\n+#include <stdlib.h>\n+#include \"dirutil.h\"\n+\n+/* Returned malloc'ed string representing basename */\n+char *basenamex(char *pathname)\n+{\n+    char *dup = strdup(pathname);\n+    char *ptr = strrchr(stripslash(dup), '/');\n+    if (ptr == NULL) return dup;\n+    ptr = strdup(ptr+1);\n+    free(dup);\n+    return ptr;\n+}\n+\n+/* Return malloc'ed string representing directory name (no trailing slash) */\n+char *dirnamex(char *pathname)\n+{\n+    char *dup = strdup(pathname);\n+    char *ptr = strrchr(stripslash(dup), '/');\n+    if (ptr == NULL) { free(dup); return strdup(\".\"); }\n+    if (ptr == dup && dup[0] == '/') ptr++;\n+    *ptr = '\\0';\n+    return dup;\n+}\n+\n+/* In-place modify a string to remove trailing slashes.  Returns arg.\n+ * stripslash(\"/\") returns \"/\";\n+ */\n+char *stripslash(char *pathname) {\n+    int len = strlen(pathname);\n+    while (len > 1 && pathname[len - 1] == '/')\n+        pathname[--len] = '\\0';\n+    return pathname;\n+}\n+\n+/* ensure dirname exists, creating it if necessary. */\n+int make_valid_path(char *dir, mode_t mode)\n+{\n+    struct stat st;\n+    char *tmp = NULL, *path = stripslash(strdup(dir));\n+    int retval;\n+    if (stat(path, &st) == 0) { /* file exists */\n+        if (S_ISDIR(st.st_mode)) { retval = 1; goto end; }\n+        else { retval = 0; goto end; } /* not a directory.  Oops. */\n+    }\n+    /* Directory doesn't exist.  Let's make it. */\n+    /*   Make parent first. */\n+    if (!make_valid_path(tmp = dirnamex(path), mode)) { retval = 0; goto end; }\n+    /*   Now make this 'un. */\n+    if (mkdir(path, mode) < 0) { retval = 0; goto end; }\n+    /* Success. */\n+    retval = 1;\n+\n+end:\n+    if (tmp != NULL) free(tmp);\n+    if (path != NULL) free(path);\n+    return retval;\n+}\n--- /dev/null\n+++ b/pppd/plugins/pptp/dirutil.h\n@@ -0,0 +1,14 @@\n+/* dirutil.h ... directory utilities.\n+ *               C. Scott Ananian <cananian@alumni.princeton.edu>\n+ *\n+ * $Id: dirutil.h,v 1.1.1.1 2000/12/23 08:19:51 scott Exp $\n+ */\n+\n+/* Returned malloc'ed string representing basename */\n+char *basenamex(char *pathname);\n+/* Return malloc'ed string representing directory name (no trailing slash) */\n+char *dirnamex(char *pathname);\n+/* In-place modify a string to remove trailing slashes.  Returns arg. */\n+char *stripslash(char *pathname);\n+/* ensure dirname exists, creating it if necessary. */\n+int make_valid_path(char *dirname, mode_t mode);\n--- /dev/null\n+++ b/pppd/plugins/pptp/orckit_quirks.c\n@@ -0,0 +1,86 @@\n+/* orckit_quirks.c ...... fix quirks in orckit adsl modems\n+ *                        mulix <mulix@actcom.co.il>\n+ *\n+ * $Id: orckit_quirks.c,v 1.3 2002/03/01 01:23:36 quozl Exp $\n+ */\n+\n+#include <string.h>\n+#include <sys/types.h>\n+#include <netinet/in.h>\n+#include \"pptp_msg.h\"\n+#include \"pptp_options.h\"\n+#include \"pptp_ctrl.h\"\n+#include \"util.h\"\n+\n+\n+\n+/* return 0 on success, non zero otherwise */\n+int\n+orckit_atur3_build_hook(struct pptp_out_call_rqst* packet)\n+{\n+    unsigned int name_length = 10;\n+\n+    struct pptp_out_call_rqst fixed_packet = {\n+\tPPTP_HEADER_CTRL(PPTP_OUT_CALL_RQST),\n+\t0, /* hton16(call->callid) */\n+\t0, /* hton16(call->sernum) */\n+\thton32(PPTP_BPS_MIN), hton32(PPTP_BPS_MAX),\n+\thton32(PPTP_BEARER_DIGITAL), hton32(PPTP_FRAME_ANY),\n+\thton16(PPTP_WINDOW), 0, hton16(name_length), 0,\n+\t{'R','E','L','A','Y','_','P','P','P','1',0}, {0}\n+    };\n+\n+    if (!packet)\n+\treturn -1;\n+\n+    memcpy(packet, &fixed_packet, sizeof(*packet));\n+\n+    return 0;\n+}\n+\n+/* return 0 on success, non zero otherwise */\n+int\n+orckit_atur3_set_link_hook(struct pptp_set_link_info* packet,\n+\t\t\t   int peer_call_id)\n+{\n+    struct pptp_set_link_info fixed_packet = {\n+\tPPTP_HEADER_CTRL(PPTP_SET_LINK_INFO),\n+\thton16(peer_call_id),\n+\t0,\n+\t0xffffffff,\n+\t0xffffffff};\n+\n+    if (!packet)\n+\treturn -1;\n+\n+    memcpy(packet, &fixed_packet, sizeof(*packet));\n+    return 0;\n+}\n+\n+/* return 0 on success, non 0 otherwise */\n+int\n+orckit_atur3_start_ctrl_conn_hook(struct pptp_start_ctrl_conn* packet)\n+{\n+    struct pptp_start_ctrl_conn fixed_packet = {\n+\t{0}, /* we'll set the header later */\n+\thton16(PPTP_VERSION), 0, 0,\n+\thton32(PPTP_FRAME_ASYNC), hton32(PPTP_BEARER_ANALOG),\n+\thton16(0) /* max channels */,\n+\thton16(0x6021),\n+\t{'R','E','L','A','Y','_','P','P','P','1',0}, /* hostname */\n+\t{'M','S',' ','W','i','n',' ','N','T',0} /* vendor */\n+    };\n+\n+    if (!packet)\n+\treturn -1;\n+\n+    /* grab the header from the original packet, since we dont\n+       know if this is a request or a reply */\n+    memcpy(&fixed_packet.header, &packet->header, sizeof(struct pptp_header));\n+\n+    /* and now overwrite the full packet, effectively preserving the header */\n+    memcpy(packet, &fixed_packet, sizeof(*packet));\n+    return 0;\n+}\n+\n+\n--- /dev/null\n+++ b/pppd/plugins/pptp/orckit_quirks.h\n@@ -0,0 +1,27 @@\n+/* orckit_quirks.h ...... fix quirks in orckit adsl modems\n+ *                        mulix <mulix@actcom.co.il>\n+ *\n+ * $Id: orckit_quirks.h,v 1.2 2001/11/23 03:42:51 quozl Exp $\n+ */\n+\n+#ifndef INC_ORCKIT_QUIRKS_H_\n+#define INC_ORCKIT_QUIRKS_H_\n+\n+#include \"pptp_options.h\"\n+#include \"pptp_ctrl.h\"\n+#include \"pptp_msg.h\"\n+\n+/* return 0 on success, non zero otherwise */\n+int\n+orckit_atur3_build_hook(struct pptp_out_call_rqst* packt);\n+\n+/* return 0 on success, non zero otherwise */\n+int\n+orckit_atur3_set_link_hook(struct pptp_set_link_info* packet,\n+\t\t\t   int peer_call_id);\n+\n+/* return 0 on success, non zero otherwise */\n+int\n+orckit_atur3_start_ctrl_conn_hook(struct pptp_start_ctrl_conn* packet);\n+\n+#endif /* INC_ORCKIT_QUIRKS_H_ */\n--- /dev/null\n+++ b/pppd/plugins/pptp/pppd-pptp.8\n@@ -0,0 +1,68 @@\n+.\\\" manual page [] for PPTP plugin for pppd 2.4\n+.\\\" $Id: pppd-pptp.8,v 1.0 2007/10/17 13:27:17 kad Exp $\n+.\\\" SH section heading\n+.\\\" SS subsection heading\n+.\\\" LP paragraph\n+.\\\" IP indented paragraph\n+.\\\" TP hanging label\n+.TH PPPD-PPTP 8\n+.SH NAME\n+pptp.so \\- PPTP VPN plugin for\n+.BR pppd (8)\n+.SH SYNOPSIS\n+.B pppd\n+[\n+.I options\n+]\n+plugin pptp.so\n+.SH DESCRIPTION\n+.LP\n+The PPTP plugin for pppd performs interaction with pptp kernel module\n+and has built-in call manager (client part of PPTP).\n+It pasees necessary paremeters from \\fIoptions\\fR into kernel module \n+to configure ppp-pptp channel. If it runs in client mode, then additionally \n+call manager starts up. PPTPD daemon automaticaly invokes this plugin\n+in server mode and passes necessary options, so additional configuration\n+is not needed.\n+\n+.SH OPTIONS for client mode\n+The PPTP plugin introduces one additional pppd option:\n+.TP\n+.BI \"pptp_server \" server \" (required)\"\n+Specifies ip address or hostname of pptp server.\n+.TP\n+.BI \"pptp_window \" packets \" (optional)\"\n+The amount of sliding window size. \n+Set to 0 to turn off sliding window.\n+    to 3-10 for low speed connections.\n+    to >10 for hi speed connections.\n+Default is 50\n+.TP\n+.BI \"pptp_phone \" phone \" (optional)\"\n+The phone string that sended to pptp server.\n+.SH USAGE\n+Sample configuration file:\n+.nf\n+plugin \"pptp.so\"\n+pptp_server 192.168.0.1\n+pptp_window 100\n+name myname\n+remotename pptp\n+noauth\n+refuse-eap\n+refuse-chap\n+refuse-mschap\n+nobsdcomp\n+nodeflate\n+novj\n+novjccomp\n+require-mppe-128\n+lcp-echo-interval 20\n+lcp-echo-failure  3\n+.fi\n+\n+.SH SEE ALSO\n+.BR pppd (8) \"  \" pptpd (8) \"  \" pptpd.conf (5)\n+\n+.SH AUTHOR\n+xeb xeb@mail.ru\n--- /dev/null\n+++ b/pppd/plugins/pptp/pptp.c\n@@ -0,0 +1,323 @@\n+/***************************************************************************\n+ *   Copyright (C) 2006 by Kozlov D. <xeb@mail.ru>                         *\n+ *   some cleanup done (C) 2012 by Daniel Golle <dgolle@allnet.de>         *\n+ *                                                                         *\n+ *   This program is free software; you can redistribute it and/or modify  *\n+ *   it under the terms of the GNU General Public License as published by  *\n+ *   the Free Software Foundation; either version 2 of the License, or     *\n+ *   (at your option) any later version.                                   *\n+ *                                                                         *\n+ *   This program is distributed in the hope that it will be useful,       *\n+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *\n+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *\n+ *   GNU General Public License for more details.                          *\n+ *                                                                         *\n+ *   You should have received a copy of the GNU General Public License     *\n+ *   along with this program; if not, write to the                         *\n+ *   Free Software Foundation, Inc.,                                       *\n+ *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *\n+ ***************************************************************************/\n+\n+#define PPTP_VERSION \"1.00\"\n+\n+#ifdef HAVE_CONFIG_H\n+#include <config.h>\n+#endif\n+\n+#include <netinet/in.h>\n+#include <arpa/inet.h>\n+#include <sys/un.h>\n+#include <netdb.h>\n+#include <stdio.h>\n+#include <string.h>\n+#include <stdlib.h>\n+#include <syslog.h>\n+#include <unistd.h>\n+#include <signal.h>\n+#include <errno.h>\n+#include <fcntl.h>\n+#include <sys/wait.h>\n+#include <sys/ioctl.h>\n+\n+#include \"pppd.h\"\n+#include \"fsm.h\"\n+#include \"lcp.h\"\n+#include \"ipcp.h\"\n+#include \"ccp.h\"\n+#include \"pathnames.h\"\n+\n+#include \"pptp_callmgr.h\"\n+#include <net/if.h>\n+#include <net/ethernet.h>\n+#include <linux/if_pppox.h>\n+\n+#include <stdio.h>\n+#include <stdlib.h>\n+\n+\n+\n+extern char** environ;\n+\n+char pppd_version[] = PPPD_VERSION;\n+extern int new_style_driver;\n+\n+\n+char *pptp_server = NULL;\n+char *pptp_client = NULL;\n+char *pptp_phone = NULL;\n+int pptp_window=50;\n+int pptp_sock=-1;\n+struct in_addr localbind = { INADDR_NONE };\n+\n+static int callmgr_sock;\n+static int pptp_fd;\n+int call_ID;\n+\n+static int open_callmgr(int call_id,struct in_addr inetaddr, char *phonenr,int window);\n+static void launch_callmgr(int call_is,struct in_addr inetaddr, char *phonenr,int window);\n+static int get_call_id(int sock, pid_t gre, pid_t pppd, u_int16_t *peer_call_id);\n+\n+static option_t Options[] =\n+{\n+    { \"pptp_server\", o_string, &pptp_server,\n+      \"PPTP Server\" },\n+    { \"pptp_client\", o_string, &pptp_client,\n+      \"PPTP Client\" },\n+    { \"pptp_sock\",o_int, &pptp_sock,\n+      \"PPTP socket\" },\n+    { \"pptp_phone\", o_string, &pptp_phone,\n+      \"PPTP Phone number\" },\n+    { \"pptp_window\",o_int, &pptp_window,\n+      \"PPTP window\" },\n+    { NULL }\n+};\n+\n+static int pptp_connect(void);\n+static void pptp_disconnect(void);\n+\n+struct channel pptp_channel = {\n+    options: Options,\n+    check_options: NULL,\n+    connect: &pptp_connect,\n+    disconnect: &pptp_disconnect,\n+    establish_ppp: &generic_establish_ppp,\n+    disestablish_ppp: &generic_disestablish_ppp,\n+    close: NULL,\n+    cleanup: NULL\n+};\n+\n+static int pptp_start_server(void)\n+{\n+\tpptp_fd=pptp_sock;\n+\tsprintf(ppp_devnam,\"pptp (%s)\",pptp_client);\n+\n+\treturn pptp_fd;\n+}\n+static int pptp_start_client(void)\n+{\n+\tsocklen_t len;\n+\tstruct sockaddr_pppox src_addr,dst_addr;\n+\tstruct hostent *hostinfo;\n+\n+\thostinfo=gethostbyname(pptp_server);\n+  if (!hostinfo)\n+\t{\n+\t\terror(\"PPTP: Unknown host %s\\n\", pptp_server);\n+\t\treturn -1;\n+\t}\n+\tdst_addr.sa_addr.pptp.sin_addr=*(struct in_addr*)hostinfo->h_addr;\n+\t{\n+\t\tint sock;\n+\t\tstruct sockaddr_in addr;\n+\t\tlen=sizeof(addr);\n+\t\taddr.sin_addr=dst_addr.sa_addr.pptp.sin_addr;\n+\t\taddr.sin_family=AF_INET;\n+\t\taddr.sin_port=htons(1700);\n+\t\tsock=socket(AF_INET,SOCK_DGRAM,0);\n+\t\tif (connect(sock,(struct sockaddr*)&addr,sizeof(addr)))\n+\t\t{\n+\t\t\tclose(sock);\n+\t\t\terror(\"PPTP: connect failed (%s)\\n\",strerror(errno));\n+\t\t\treturn -1;\n+\t\t}\n+\t\tgetsockname(sock,(struct sockaddr*)&addr,&len);\n+\t\tsrc_addr.sa_addr.pptp.sin_addr=addr.sin_addr;\n+\t\tclose(sock);\n+\t}\n+\n+\tsrc_addr.sa_family=AF_PPPOX;\n+\tsrc_addr.sa_protocol=PX_PROTO_PPTP;\n+\tsrc_addr.sa_addr.pptp.call_id=0;\n+\n+\tdst_addr.sa_family=AF_PPPOX;\n+\tdst_addr.sa_protocol=PX_PROTO_PPTP;\n+\tdst_addr.sa_addr.pptp.call_id=0;\n+\n+\tpptp_fd=socket(AF_PPPOX,SOCK_STREAM,PX_PROTO_PPTP);\n+\tif (pptp_fd<0)\n+\t{\n+\t\terror(\"PPTP: failed to create PPTP socket (%s)\\n\",strerror(errno));\n+\t\treturn -1;\n+\t}\n+\tif (bind(pptp_fd,(struct sockaddr*)&src_addr,sizeof(src_addr)))\n+\t{\n+\t\tclose(pptp_fd);\n+\t\terror(\"PPTP: failed to bind PPTP socket (%s)\\n\",strerror(errno));\n+\t\treturn -1;\n+\t}\n+\tlen=sizeof(src_addr);\n+\tgetsockname(pptp_fd,(struct sockaddr*)&src_addr,&len);\n+\tcall_ID=src_addr.sa_addr.pptp.call_id;\n+\n+  do {\n+        /*\n+         * Open connection to call manager (Launch call manager if necessary.)\n+         */\n+        callmgr_sock = open_callmgr(src_addr.sa_addr.pptp.call_id,dst_addr.sa_addr.pptp.sin_addr, pptp_phone, pptp_window);\n+\tif (callmgr_sock<0)\n+\t{\n+\t\tclose(pptp_fd);\n+\t\treturn -1;\n+        }\n+        /* Exchange PIDs, get call ID */\n+    } while (get_call_id(callmgr_sock, getpid(), getpid(), &dst_addr.sa_addr.pptp.call_id) < 0);\n+\n+\tif (connect(pptp_fd,(struct sockaddr*)&dst_addr,sizeof(dst_addr)))\n+\t{\n+\t\tclose(callmgr_sock);\n+\t\tclose(pptp_fd);\n+\t\terror(\"PPTP: failed to connect PPTP socket (%s)\\n\",strerror(errno));\n+\t\treturn -1;\n+\t}\n+\n+\tsprintf(ppp_devnam,\"pptp (%s)\",pptp_server);\n+\n+\treturn pptp_fd;\n+}\n+static int pptp_connect(void)\n+{\n+\tif ((!pptp_server && !pptp_client) || (pptp_server && pptp_client))\n+\t{\n+\t\tfatal(\"PPTP: unknown mode (you must specify pptp_server or pptp_client option)\");\n+\t\treturn -1;\n+\t}\n+\n+\tif (pptp_server) return pptp_start_client();\n+\treturn pptp_start_server();\n+}\n+\n+static void pptp_disconnect(void)\n+{\n+\tif (pptp_server) close(callmgr_sock);\n+\tclose(pptp_fd);\n+}\n+\n+static int open_callmgr(int call_id,struct in_addr inetaddr, char *phonenr,int window)\n+{\n+    /* Try to open unix domain socket to call manager. */\n+    struct sockaddr_un where;\n+    const int NUM_TRIES = 3;\n+    int i, fd;\n+    pid_t pid;\n+    int status;\n+    /* Open socket */\n+    if ((fd = socket(AF_UNIX, SOCK_STREAM, 0)) < 0)\n+    {\n+        fatal(\"Could not create unix domain socket: %s\", strerror(errno));\n+    }\n+    /* Make address */\n+    callmgr_name_unixsock(&where, inetaddr, localbind);\n+    for (i = 0; i < NUM_TRIES; i++)\n+    {\n+        if (connect(fd, (struct sockaddr *) &where, sizeof(where)) < 0)\n+        {\n+            /* couldn't connect.  We'll have to launch this guy. */\n+\n+            unlink (where.sun_path);\n+\n+            /* fork and launch call manager process */\n+            switch (pid = fork())\n+            {\n+                case -1: /* failure */\n+                    fatal(\"fork() to launch call manager failed.\");\n+                case 0: /* child */\n+                {\n+                    /* close the pty and gre in the call manager */\n+                    close(fd);\n+                    close(pptp_fd);\n+                    launch_callmgr(call_id,inetaddr,phonenr,window);\n+                }\n+                default: /* parent */\n+                    waitpid(pid, &status, 0);\n+                    if (status!= 0)\n+\t\t    {\n+\t\t\tclose(fd);\n+\t\t\terror(\"Call manager exited with error %d\", status);\n+\t\t\treturn -1;\n+\t\t    }\n+                    break;\n+            }\n+            sleep(1);\n+        }\n+        else return fd;\n+    }\n+    close(fd);\n+    error(\"Could not launch call manager after %d tries.\", i);\n+    return -1;   /* make gcc happy */\n+}\n+\n+/*** call the call manager main ***********************************************/\n+static void launch_callmgr(int call_id,struct in_addr inetaddr, char *phonenr,int window)\n+{\n+    dbglog(\"pptp: call manager for %s\\n\", inet_ntoa(inetaddr));\n+    dbglog(\"window size:\\t%d\\n\",window);\n+    if (phonenr) dbglog(\"phone number:\\t'%s'\\n\",phonenr);\n+    dbglog(\"call id:\\t%d\\n\",call_id);\n+    exit(callmgr_main(inetaddr, phonenr, window, call_id));\n+}\n+\n+/*** exchange data with the call manager  *************************************/\n+/* XXX need better error checking XXX */\n+static int get_call_id(int sock, pid_t gre, pid_t pppd,\n+\t\tu_int16_t *peer_call_id)\n+{\n+    u_int16_t m_call_id, m_peer_call_id;\n+    /* write pid's to socket */\n+    /* don't bother with network byte order, because pid's are meaningless\n+     * outside the local host.\n+     */\n+    int rc;\n+    rc = write(sock, &gre, sizeof(gre));\n+    if (rc != sizeof(gre))\n+        return -1;\n+    rc = write(sock, &pppd, sizeof(pppd));\n+    if (rc != sizeof(pppd))\n+        return -1;\n+    rc = read(sock,  &m_call_id, sizeof(m_call_id));\n+    if (rc != sizeof(m_call_id))\n+        return -1;\n+    rc = read(sock,  &m_peer_call_id, sizeof(m_peer_call_id));\n+    if (rc != sizeof(m_peer_call_id))\n+        return -1;\n+    /*\n+     * XXX FIXME ... DO ERROR CHECKING & TIME-OUTS XXX\n+     * (Rhialto: I am assuming for now that timeouts are not relevant\n+     * here, because the read and write calls would return -1 (fail) when\n+     * the peer goes away during the process. We know it is (or was)\n+     * running because the connect() call succeeded.)\n+     * (James: on the other hand, if the route to the peer goes away, we\n+     * wouldn't get told by read() or write() for quite some time.)\n+     */\n+    *peer_call_id = m_peer_call_id;\n+    return 0;\n+}\n+\n+void plugin_init(void)\n+{\n+    add_options(Options);\n+\n+    info(\"PPTP plugin version %s\", PPTP_VERSION);\n+\n+    the_channel = &pptp_channel;\n+    modem = 0;\n+}\n--- /dev/null\n+++ b/pppd/plugins/pptp/pptp_callmgr.c\n@@ -0,0 +1,381 @@\n+/* pptp_callmgr.c ... Call manager for PPTP connections.\n+ *                    Handles TCP port 1723 protocol.\n+ *                    C. Scott Ananian <cananian@alumni.princeton.edu>\n+ *\n+ * $Id: pptp_callmgr.c,v 1.20 2005/03/31 07:42:39 quozl Exp $\n+ */\n+#include <signal.h>\n+#include <sys/time.h>\n+#include <sys/types.h>\n+#include <sys/stat.h>\n+#include <sys/socket.h>\n+#include <netinet/in.h>\n+#include <arpa/inet.h>\n+#include <sys/un.h>\n+#include <unistd.h>\n+#include <stdlib.h>\n+#include <string.h>\n+#include <assert.h>\n+#include <setjmp.h>\n+#include <stdio.h>\n+#include <errno.h>\n+#include \"pptp_callmgr.h\"\n+#include \"pptp_ctrl.h\"\n+#include \"pptp_msg.h\"\n+#include \"dirutil.h\"\n+#include \"vector.h\"\n+#include \"util.h\"\n+#include \"pppd.h\"\n+\n+extern struct in_addr localbind; /* from pptp.c */\n+extern int call_ID;\n+\n+int open_inetsock(struct in_addr inetaddr);\n+int open_unixsock(struct in_addr inetaddr);\n+void close_inetsock(int fd, struct in_addr inetaddr);\n+void close_unixsock(int fd, struct in_addr inetaddr);\n+\n+sigjmp_buf callmgr_env;\n+\n+void callmgr_sighandler(int sig) {\n+    /* TODO: according to signal(2), siglongjmp() is unsafe used here */\n+    siglongjmp (callmgr_env, 1);\n+}\n+\n+void callmgr_do_nothing(int sig) {\n+    /* do nothing signal handler */\n+}\n+\n+struct local_callinfo {\n+    int unix_sock;\n+    pid_t pid[2];\n+};\n+\n+struct local_conninfo {\n+    VECTOR * call_list;\n+    fd_set * call_set;\n+};\n+\n+/* Call callback */\n+void call_callback(PPTP_CONN *conn, PPTP_CALL *call, enum call_state state)\n+{\n+    struct local_callinfo *lci;\n+    struct local_conninfo *conninfo;\n+    u_int16_t call_id[2];\n+    switch(state) {\n+        case CALL_OPEN_DONE:\n+            /* okey dokey.  This means that the call_id and peer_call_id are\n+             * now valid, so lets send them on to our friends who requested\n+             * this call.  */\n+            lci = pptp_call_closure_get(conn, call); assert(lci != NULL);\n+            pptp_call_get_ids(conn, call, &call_id[0], &call_id[1]);\n+            write(lci->unix_sock, &call_id, sizeof(call_id));\n+            /* Our duty to the fatherland is now complete. */\n+            break;\n+        case CALL_OPEN_FAIL:\n+        case CALL_CLOSE_RQST:\n+        case CALL_CLOSE_DONE:\n+            /* don't need to do anything here, except make sure tables\n+             * are sync'ed */\n+            dbglog(\"Closing connection (call state)\");\n+            conninfo = pptp_conn_closure_get(conn);\n+            lci = pptp_call_closure_get(conn, call);\n+            assert(lci != NULL && conninfo != NULL);\n+            if (vector_contains(conninfo->call_list, lci->unix_sock)) {\n+                vector_remove(conninfo->call_list, lci->unix_sock);\n+                close(lci->unix_sock);\n+                FD_CLR(lci->unix_sock, conninfo->call_set);\n+            }\n+            break;\n+        default:\n+            dbglog(\"Unhandled call callback state [%d].\", (int) state);\n+            break;\n+    }\n+}\n+\n+/******************************************************************************\n+ * NOTE ABOUT 'VOLATILE':\n+ * several variables here get a volatile qualifier to silence warnings\n+ * from older (before 3.0) gccs. if the longjmp stuff is removed,\n+ * the volatile qualifiers should be removed as well.\n+ *****************************************************************************/\n+\n+/*** Call Manager *************************************************************/\n+int callmgr_main(struct in_addr inetaddr, char phonenr[], int window, int pcallid)\n+{\n+    int inet_sock, unix_sock;\n+    fd_set call_set;\n+    PPTP_CONN * conn;\n+    VECTOR * call_list;\n+    int max_fd = 0;\n+    volatile int first = 1;\n+    int retval;\n+    int i;\n+    if (pcallid>0) call_ID=pcallid;\n+\n+    /* Step 1: Open sockets. */\n+    if ((inet_sock = open_inetsock(inetaddr)) < 0)\n+        fatal(\"Could not open control connection to %s\", inet_ntoa(inetaddr));\n+    dbglog(\"control connection\");\n+    if ((unix_sock = open_unixsock(inetaddr)) < 0)\n+        fatal(\"Could not open unix socket for %s\", inet_ntoa(inetaddr));\n+    /* Step 1b: FORK and return status to calling process. */\n+    dbglog(\"unix_sock\");\n+\n+    switch (fork()) {\n+        case 0: /* child. stick around. */\n+            break;\n+        case -1: /* failure.  Fatal. */\n+            fatal(\"Could not fork.\");\n+        default: /* Parent. Return status to caller. */\n+            exit(0);\n+    }\n+    /* re-open stderr as /dev/null to release it */\n+    file2fd(\"/dev/null\", \"wb\", STDERR_FILENO);\n+    /* Step 1c: Clean up unix socket on TERM */\n+    if (sigsetjmp(callmgr_env, 1) != 0)\n+        goto cleanup;\n+    signal(SIGINT, callmgr_sighandler);\n+    signal(SIGTERM, callmgr_sighandler);\n+    signal(SIGPIPE, callmgr_do_nothing);\n+    signal(SIGUSR1, callmgr_do_nothing); /* signal state change\n+                                            wake up accept */\n+    /* Step 2: Open control connection and register callback */\n+    if ((conn = pptp_conn_open(inet_sock, 1, NULL/* callback */)) == NULL) {\n+        close(unix_sock); close(inet_sock); fatal(\"Could not open connection.\");\n+    }\n+    FD_ZERO(&call_set);\n+    call_list = vector_create();\n+    {\n+        struct local_conninfo *conninfo = malloc(sizeof(*conninfo));\n+        if (conninfo == NULL) {\n+            close(unix_sock); close(inet_sock); fatal(\"No memory.\");\n+        }\n+        conninfo->call_list = call_list;\n+        conninfo->call_set  = &call_set;\n+        pptp_conn_closure_put(conn, conninfo);\n+    }\n+    if (sigsetjmp(callmgr_env, 1) != 0) goto shutdown;\n+    /* Step 3: Get FD_SETs */\n+    max_fd = unix_sock;\n+    do {\n+        int rc;\n+        fd_set read_set = call_set, write_set;\n+        FD_ZERO (&write_set);\n+        if (pptp_conn_established(conn)) {\n+\t  FD_SET (unix_sock, &read_set);\n+\t  if (unix_sock > max_fd) max_fd = unix_sock;\n+\t}\n+        pptp_fd_set(conn, &read_set, &write_set, &max_fd);\n+        for (; max_fd > 0 ; max_fd--) {\n+            if (FD_ISSET (max_fd, &read_set) ||\n+                    FD_ISSET (max_fd, &write_set))\n+                break;\n+        }\n+        /* Step 4: Wait on INET or UNIX event */\n+        if ((rc = select(max_fd + 1, &read_set, &write_set, NULL, NULL)) <0) {\n+\t  if (errno == EBADF) break;\n+\t  /* a signal or somesuch. */\n+\t  continue;\n+\t}\n+        /* Step 5a: Handle INET events */\n+        rc = pptp_dispatch(conn, &read_set, &write_set);\n+\tif (rc < 0)\n+\t    break;\n+        /* Step 5b: Handle new connection to UNIX socket */\n+        if (FD_ISSET(unix_sock, &read_set)) {\n+            /* New call! */\n+            struct sockaddr_un from;\n+            int len = sizeof(from);\n+            PPTP_CALL * call;\n+            struct local_callinfo *lci;\n+            int s;\n+            /* Accept the socket */\n+            FD_CLR (unix_sock, &read_set);\n+            if ((s = accept(unix_sock, (struct sockaddr *) &from, &len)) < 0) {\n+                warn(\"Socket not accepted: %s\", strerror(errno));\n+                goto skip_accept;\n+            }\n+            /* Allocate memory for local call information structure. */\n+            if ((lci = malloc(sizeof(*lci))) == NULL) {\n+                warn(\"Out of memory.\"); close(s); goto skip_accept;\n+            }\n+            lci->unix_sock = s;\n+            /* Give the initiator time to write the PIDs while we open\n+             * the call */\n+            call = pptp_call_open(conn, call_ID,call_callback, phonenr,window);\n+            /* Read and store the associated pids */\n+            read(s, &lci->pid[0], sizeof(lci->pid[0]));\n+            read(s, &lci->pid[1], sizeof(lci->pid[1]));\n+            /* associate the local information with the call */\n+            pptp_call_closure_put(conn, call, (void *) lci);\n+            /* The rest is done on callback. */\n+            /* Keep alive; wait for close */\n+            retval = vector_insert(call_list, s, call); assert(retval);\n+            if (s > max_fd) max_fd = s;\n+            FD_SET(s, &call_set);\n+            first = 0;\n+        }\n+skip_accept: /* Step 5c: Handle socket close */\n+        for (i = 0; i < max_fd + 1; i++)\n+            if (FD_ISSET(i, &read_set)) {\n+                /* close it */\n+                PPTP_CALL * call;\n+                retval = vector_search(call_list, i, &call);\n+                if (retval) {\n+                    struct local_callinfo *lci =\n+                        pptp_call_closure_get(conn, call);\n+                    dbglog(\"Closing connection (unhandled)\");\n+                    free(lci);\n+                    /* soft shutdown.  Callback will do hard shutdown later */\n+                    pptp_call_close(conn, call);\n+                    vector_remove(call_list, i);\n+                }\n+                FD_CLR(i, &call_set);\n+                close(i);\n+            }\n+    } while (vector_size(call_list) > 0 || first);\n+shutdown:\n+    {\n+        int rc;\n+        fd_set read_set, write_set;\n+        struct timeval tv;\n+\tsignal(SIGINT, callmgr_do_nothing);\n+\tsignal(SIGTERM, callmgr_do_nothing);\n+        /* warn(\"Shutdown\"); */\n+        /* kill all open calls */\n+        for (i = 0; i < vector_size(call_list); i++) {\n+            PPTP_CALL *call = vector_get_Nth(call_list, i);\n+            dbglog(\"Closing connection (shutdown)\");\n+            pptp_call_close(conn, call);\n+        }\n+        /* attempt to dispatch these messages */\n+        FD_ZERO(&read_set);\n+        FD_ZERO(&write_set);\n+        pptp_fd_set(conn, &read_set, &write_set, &max_fd);\n+\ttv.tv_sec = 0;\n+\ttv.tv_usec = 0;\n+\tselect(max_fd + 1, &read_set, &write_set, NULL, &tv);\n+        rc = pptp_dispatch(conn, &read_set, &write_set);\n+\tif (rc > 0) {\n+\t  /* wait for a respond, a timeout because there might not be one */\n+\t  FD_ZERO(&read_set);\n+\t  FD_ZERO(&write_set);\n+\t  pptp_fd_set(conn, &read_set, &write_set, &max_fd);\n+\t  tv.tv_sec = 2;\n+\t  tv.tv_usec = 0;\n+\t  select(max_fd + 1, &read_set, &write_set, NULL, &tv);\n+\t  rc = pptp_dispatch(conn, &read_set, &write_set);\n+\t  if (rc > 0) {\n+\t    if (i > 0) sleep(2);\n+\t    /* no more open calls.  Close the connection. */\n+\t    pptp_conn_close(conn, PPTP_STOP_LOCAL_SHUTDOWN);\n+\t    /* wait for a respond, a timeout because there might not be one */\n+\t    FD_ZERO(&read_set);\n+\t    FD_ZERO(&write_set);\n+\t    pptp_fd_set(conn, &read_set, &write_set, &max_fd);\n+\t    tv.tv_sec = 2;\n+\t    tv.tv_usec = 0;\n+\t    select(max_fd + 1, &read_set, &write_set, NULL, &tv);\n+\t    pptp_dispatch(conn, &read_set, &write_set);\n+\t    if (rc > 0) sleep(2);\n+\t  }\n+\t}\n+        /* with extreme prejudice */\n+        pptp_conn_destroy(conn);\n+        vector_destroy(call_list);\n+    }\n+cleanup:\n+    signal(SIGINT, callmgr_do_nothing);\n+    signal(SIGTERM, callmgr_do_nothing);\n+    close_inetsock(inet_sock, inetaddr);\n+    close_unixsock(unix_sock, inetaddr);\n+    return 0;\n+}\n+\n+/*** open_inetsock ************************************************************/\n+int open_inetsock(struct in_addr inetaddr)\n+{\n+    struct sockaddr_in dest, src;\n+    int s;\n+    dest.sin_family = AF_INET;\n+    dest.sin_port   = htons(PPTP_PORT);\n+    dest.sin_addr   = inetaddr;\n+    if ((s = socket(AF_INET, SOCK_STREAM, 0)) < 0) {\n+        warn(\"socket: %s\", strerror(errno));\n+        return s;\n+    }\n+    if (localbind.s_addr != INADDR_NONE) {\n+        bzero(&src, sizeof(src));\n+        src.sin_family = AF_INET;\n+        src.sin_addr   = localbind;\n+        if (bind(s, (struct sockaddr *) &src, sizeof(src)) != 0) {\n+            warn(\"bind: %s\", strerror(errno));\n+            close(s); return -1;\n+        }\n+    }\n+    if (connect(s, (struct sockaddr *) &dest, sizeof(dest)) < 0) {\n+        warn(\"connect: %s\", strerror(errno));\n+        close(s); return -1;\n+    }\n+    return s;\n+}\n+\n+/*** open_unixsock ************************************************************/\n+int open_unixsock(struct in_addr inetaddr)\n+{\n+    struct sockaddr_un where;\n+    struct stat st;\n+    char *dir;\n+    int s;\n+    if ((s = socket(AF_UNIX, SOCK_STREAM, 0)) < 0) {\n+        warn(\"socket: %s\", strerror(errno));\n+        return s;\n+    }\n+    callmgr_name_unixsock( &where, inetaddr, localbind);\n+    if (stat(where.sun_path, &st) >= 0)\n+    {\n+        warn(\"Call manager for %s is already running.\", inet_ntoa(inetaddr));\n+        close(s); return -1;\n+    }\n+   /* Make sure path is valid. */\n+    dir = dirnamex(where.sun_path);\n+    if (!make_valid_path(dir, 0770))\n+        fatal(\"Could not make path to %s: %s\", where.sun_path, strerror(errno));\n+    free(dir);\n+    if (bind(s, (struct sockaddr *) &where, sizeof(where)) < 0) {\n+        warn(\"bind: %s\", strerror(errno));\n+        close(s); return -1;\n+    }\n+    chmod(where.sun_path, 0777);\n+    listen(s, 127);\n+    return s;\n+}\n+\n+/*** close_inetsock ***********************************************************/\n+void close_inetsock(int fd, struct in_addr inetaddr)\n+{\n+    close(fd);\n+}\n+\n+/*** close_unixsock ***********************************************************/\n+void close_unixsock(int fd, struct in_addr inetaddr)\n+{\n+    struct sockaddr_un where;\n+    close(fd);\n+    callmgr_name_unixsock(&where, inetaddr, localbind);\n+    unlink(where.sun_path);\n+}\n+\n+/*** make a unix socket address ***********************************************/\n+void callmgr_name_unixsock(struct sockaddr_un *where,\n+\t\t\t   struct in_addr inetaddr,\n+\t\t\t   struct in_addr localbind)\n+{\n+    char localaddr[16], remoteaddr[16];\n+    where->sun_family = AF_UNIX;\n+    strncpy(localaddr,  inet_ntoa(localbind), 16);\n+    strncpy(remoteaddr, inet_ntoa(inetaddr),  16);\n+    snprintf(where->sun_path, sizeof(where->sun_path),\n+            PPTP_SOCKET_PREFIX \"%s:%i\", remoteaddr,call_ID);\n+}\n--- /dev/null\n+++ b/pppd/plugins/pptp/pptp_callmgr.h\n@@ -0,0 +1,17 @@\n+/* pptp_callmgr.h ... Call manager for PPTP connections.\n+ *                    Handles TCP port 1723 protocol.\n+ *                    C. Scott Ananian <cananian@alumni.princeton.edu>\n+ *\n+ * $Id: pptp_callmgr.h,v 1.3 2003/02/17 00:22:17 quozl Exp $\n+ */\n+\n+#define PPTP_SOCKET_PREFIX \"/var/run/pptp/\"\n+\n+int callmgr_main(struct in_addr inetaddr,\n+\t\tchar phonenr[],\n+\t\tint window,\n+\t\tint pcallid);\n+\n+void callmgr_name_unixsock(struct sockaddr_un *where,\n+\t\t\t   struct in_addr inetaddr,\n+\t\t\t   struct in_addr localbind);\n--- /dev/null\n+++ b/pppd/plugins/pptp/pptp_ctrl.c\n@@ -0,0 +1,1078 @@\n+/* pptp_ctrl.c ... handle PPTP control connection.\n+ *                 C. Scott Ananian <cananian@alumni.princeton.edu>\n+ *\n+ * $Id: pptp_ctrl.c,v 1.31 2005/03/31 07:42:39 quozl Exp $\n+ */\n+\n+#include <errno.h>\n+#include <sys/time.h>\n+#include <sys/types.h>\n+#include <sys/socket.h>\n+#include <netinet/in.h>\n+#include <unistd.h>\n+#include <stdlib.h>\n+#include <assert.h>\n+#include <signal.h>\n+#include <string.h>\n+#include <ctype.h>\n+#include <fcntl.h>\n+#include \"pppd.h\"\n+#include \"pptp_msg.h\"\n+#include \"pptp_ctrl.h\"\n+#include \"pptp_options.h\"\n+#include \"vector.h\"\n+#include \"util.h\"\n+#include \"pptp_quirks.h\"\n+\n+/* BECAUSE OF SIGNAL LIMITATIONS, EACH PROCESS CAN ONLY MANAGE ONE\n+ * CONNECTION.  SO THIS 'PPTP_CONN' STRUCTURE IS A BIT MISLEADING.\n+ * WE'LL KEEP CONNECTION-SPECIFIC INFORMATION IN THERE ANYWAY (AS\n+ * OPPOSED TO USING GLOBAL VARIABLES), BUT BEWARE THAT THE ENTIRE\n+ * UNIX SIGNAL-HANDLING SEMANTICS WOULD HAVE TO CHANGE (OR THE\n+ * TIME-OUT CODE DRASTICALLY REWRITTEN) BEFORE YOU COULD DO A\n+ * PPTP_CONN_OPEN MORE THAN ONCE PER PROCESS AND GET AWAY WITH IT.\n+ */\n+\n+/* This structure contains connection-specific information that the\n+ * signal handler needs to see.  Thus, it needs to be in a global\n+ * variable.  If you end up using pthreads or something (why not\n+ * just processes?), this would have to be placed in a thread-specific\n+ * data area, using pthread_get|set_specific, etc., so I've\n+ * conveniently encapsulated it for you.\n+ * [linux threads will have to support thread-specific signals\n+ *  before this would work at all, which, as of this writing\n+ *  (linux-threads v0.6, linux kernel 2.1.72), it does not.]\n+ */\n+\n+/* Globals */\n+\n+/* control the number of times echo packets will be logged */\n+static int nlogecho = 10;\n+\n+static struct thread_specific {\n+    struct sigaction old_sigaction; /* evil signals */\n+    PPTP_CONN * conn;\n+} global;\n+\n+#define INITIAL_BUFSIZE 512 /* initial i/o buffer size. */\n+\n+struct PPTP_CONN {\n+    int inet_sock;\n+    /* Connection States */\n+    enum {\n+        CONN_IDLE, CONN_WAIT_CTL_REPLY, CONN_WAIT_STOP_REPLY, CONN_ESTABLISHED\n+    } conn_state; /* on startup: CONN_IDLE */\n+    /* Keep-alive states */\n+    enum {\n+        KA_NONE, KA_OUTSTANDING\n+    } ka_state;  /* on startup: KA_NONE */\n+    /* Keep-alive ID; monotonically increasing (watch wrap-around!) */\n+    u_int32_t ka_id; /* on startup: 1 */\n+    /* Other properties. */\n+    u_int16_t version;\n+    u_int16_t firmware_rev;\n+    u_int8_t  hostname[64], vendor[64];\n+    /* XXX these are only PNS properties, currently XXX */\n+    /* Call assignment information. */\n+    u_int16_t call_serial_number;\n+    VECTOR *call;\n+    void * closure;\n+    pptp_conn_cb callback;\n+    /******* IO buffers ******/\n+    char * read_buffer, *write_buffer;\n+    size_t read_alloc,   write_alloc;\n+    size_t read_size,    write_size;\n+};\n+\n+struct PPTP_CALL {\n+    /* Call properties */\n+    enum {\n+        PPTP_CALL_PAC, PPTP_CALL_PNS\n+    } call_type;\n+    union {\n+        enum pptp_pac_state {\n+            PAC_IDLE, PAC_WAIT_REPLY, PAC_ESTABLISHED, PAC_WAIT_CS_ANS\n+        } pac;\n+        enum pptp_pns_state {\n+            PNS_IDLE, PNS_WAIT_REPLY, PNS_ESTABLISHED, PNS_WAIT_DISCONNECT\n+        } pns;\n+    } state;\n+    u_int16_t call_id, peer_call_id;\n+    u_int16_t sernum;\n+    u_int32_t speed;\n+    /* For user data: */\n+    pptp_call_cb callback;\n+    void * closure;\n+};\n+\n+\n+/* PPTP error codes: ----------------------------------------------*/\n+\n+/* (General Error Codes) */\n+static const struct {\n+    const char *name, *desc;\n+} pptp_general_errors[] = {\n+#define PPTP_GENERAL_ERROR_NONE                 0\n+    { \"(None)\", \"No general error\" },\n+#define PPTP_GENERAL_ERROR_NOT_CONNECTED        1\n+    { \"(Not-Connected)\", \"No control connection exists yet for this \"\n+        \"PAC-PNS pair\" },\n+#define PPTP_GENERAL_ERROR_BAD_FORMAT           2\n+    { \"(Bad-Format)\", \"Length is wrong or Magic Cookie value is incorrect\" },\n+#define PPTP_GENERAL_ERROR_BAD_VALUE            3\n+    { \"(Bad-Value)\", \"One of the field values was out of range or \"\n+            \"reserved field was non-zero\" },\n+#define PPTP_GENERAL_ERROR_NO_RESOURCE          4\n+    { \"(No-Resource)\", \"Insufficient resources to handle this command now\" },\n+#define PPTP_GENERAL_ERROR_BAD_CALLID           5\n+    { \"(Bad-Call ID)\", \"The Call ID is invalid in this context\" },\n+#define PPTP_GENERAL_ERROR_PAC_ERROR            6\n+    { \"(PAC-Error)\", \"A generic vendor-specific error occured in the PAC\" }\n+};\n+\n+#define  MAX_GENERAL_ERROR ( sizeof(pptp_general_errors) / \\\n+        sizeof(pptp_general_errors[0]) - 1)\n+\n+/* Outgoing Call Reply Result Codes */\n+static const char *pptp_out_call_reply_result[] = {\n+/* 0 */\t\"Unknown Result Code\",\n+/* 1 */\t\"Connected\",\n+/* 2 */\t\"General Error\",\n+/* 3 */\t\"No Carrier Detected\",\n+/* 4 */\t\"Busy Signal\",\n+/* 5 */\t\"No Dial Tone\",\n+/* 6 */\t\"Time Out\",\n+/* 7 */\t\"Not Accepted, Call is administratively prohibited\" };\n+\n+#define MAX_OUT_CALL_REPLY_RESULT 7\n+\n+/* Call Disconnect Notify  Result Codes */\n+static const char *pptp_call_disc_ntfy[] = {\n+/* 0 */\t\"Unknown Result Code\",\n+/* 1 */\t\"Lost Carrier\",\n+/* 2 */\t\"General Error\",\n+/* 3 */\t\"Administrative Shutdown\",\n+/* 4 */\t\"(your) Request\" };\n+\n+#define MAX_CALL_DISC_NTFY 4\n+\n+/* Call Disconnect Notify  Result Codes */\n+static const char *pptp_start_ctrl_conn_rply[] = {\n+/* 0 */\t\"Unknown Result Code\",\n+/* 1 */\t\"Successful Channel Establishment\",\n+/* 2 */\t\"General Error\",\n+/* 3 */\t\"Command Channel Already Exists\",\n+/* 4 */\t\"Requester is not Authorized\" };\n+\n+#define MAX_START_CTRL_CONN_REPLY 4\n+\n+/* timing options */\n+int idle_wait = PPTP_TIMEOUT;\n+int max_echo_wait = PPTP_TIMEOUT;\n+\n+/* Local prototypes */\n+static void pptp_reset_timer(void);\n+static void pptp_handle_timer();\n+/* Write/read as much as we can without blocking. */\n+int pptp_write_some(PPTP_CONN * conn);\n+int pptp_read_some(PPTP_CONN * conn);\n+/* Make valid packets from read_buffer */\n+int pptp_make_packet(PPTP_CONN * conn, void **buf, size_t *size);\n+/* Add packet to write_buffer */\n+int pptp_send_ctrl_packet(PPTP_CONN * conn, void * buffer, size_t size);\n+/* Dispatch packets (general) */\n+int pptp_dispatch_packet(PPTP_CONN * conn, void * buffer, size_t size);\n+/* Dispatch packets (control messages) */\n+int ctrlp_disp(PPTP_CONN * conn, void * buffer, size_t size);\n+/* Set link info, for pptp servers that need it.\n+   this is a noop, unless the user specified a quirk and\n+   there's a set_link hook defined in the quirks table\n+   for that quirk */\n+void pptp_set_link(PPTP_CONN * conn, int peer_call_id);\n+\n+/*** log error information in control packets *********************************/\n+static void ctrlp_error( int result, int error, int cause,\n+        const char *result_text[], int max_result)\n+{\n+    if( cause >= 0)\n+        warn(\"Result code is %d '%s'. Error code is %d, Cause code is %d\",\n+                result, result_text[result <= max_result ?  result : 0], error,\n+                cause );\n+    else\n+        warn(\"Reply result code is %d '%s'. Error code is %d\",\n+                result, result_text[result <= max_result ?  result : 0], error);\n+    if ((error > 0) && (error <= MAX_GENERAL_ERROR)){\n+        if( result != PPTP_RESULT_GENERAL_ERROR )\n+            warn(\"Result code is something else then \\\"general error\\\", \"\n+                    \"so the following error is probably bogus.\");\n+        warn(\"Error is '%s', Error message: '%s'\",\n+                pptp_general_errors[error].name,\n+                pptp_general_errors[error].desc);\n+    }\n+}\n+\n+static const char *ctrl_msg_types[] = {\n+         \"invalid control message type\",\n+/*         (Control Connection Management) */\n+         \"Start-Control-Connection-Request\",            /* 1 */\n+         \"Start-Control-Connection-Reply\",              /* 2 */\n+         \"Stop-Control-Connection-Request\",             /* 3 */\n+         \"Stop-Control-Connection-Reply\",               /* 4 */\n+         \"Echo-Request\",                                /* 5 */\n+         \"Echo-Reply\",                                  /* 6 */\n+/*         (Call Management) */\n+         \"Outgoing-Call-Request\",                       /* 7 */\n+         \"Outgoing-Call-Reply\",                         /* 8 */\n+         \"Incoming-Call-Request\",                       /* 9 */\n+         \"Incoming-Call-Reply\",                        /* 10 */\n+         \"Incoming-Call-Connected\",                    /* 11 */\n+         \"Call-Clear-Request\",                         /* 12 */\n+         \"Call-Disconnect-Notify\",                     /* 13 */\n+/*         (Error Reporting) */\n+         \"WAN-Error-Notify\",                           /* 14 */\n+/*         (PPP Session Control) */\n+         \"Set-Link-Info\"                              /* 15 */\n+};\n+#define MAX_CTRLMSG_TYPE 15\n+\n+/*** report a sent packet ****************************************************/\n+static void ctrlp_rep( void * buffer, int size, int isbuff)\n+{\n+    struct pptp_header *packet = buffer;\n+    unsigned int type;\n+    if(size < sizeof(struct pptp_header)) return;\n+    type = ntoh16(packet->ctrl_type);\n+    /* FIXME: do not report sending echo requests as long as they are\n+     * sent in a signal handler. This may dead lock as the syslog call\n+     * is not reentrant */\n+    if( type ==  PPTP_ECHO_RQST ) return;\n+    /* don't keep reporting sending of echo's */\n+    if( (type == PPTP_ECHO_RQST || type == PPTP_ECHO_RPLY) && nlogecho <= 0 ) return;\n+    dbglog(\"%s control packet type is %d '%s'\\n\",isbuff ? \"Buffered\" : \"Sent\",\n+            type, ctrl_msg_types[type <= MAX_CTRLMSG_TYPE ? type : 0]);\n+\n+}\n+\n+\n+\n+/* Open new pptp_connection.  Returns NULL on failure. */\n+PPTP_CONN * pptp_conn_open(int inet_sock, int isclient, pptp_conn_cb callback)\n+{\n+    PPTP_CONN *conn;\n+    /* Allocate structure */\n+    if ((conn = malloc(sizeof(*conn))) == NULL) return NULL;\n+    if ((conn->call = vector_create()) == NULL) { free(conn); return NULL; }\n+    /* Initialize */\n+    conn->inet_sock = inet_sock;\n+    conn->conn_state = CONN_IDLE;\n+    conn->ka_state  = KA_NONE;\n+    conn->ka_id     = 1;\n+    conn->call_serial_number = 0;\n+    conn->callback  = callback;\n+    /* Create I/O buffers */\n+    conn->read_size = conn->write_size = 0;\n+    conn->read_alloc = conn->write_alloc = INITIAL_BUFSIZE;\n+    conn->read_buffer =\n+        malloc(sizeof(*(conn->read_buffer)) * conn->read_alloc);\n+    conn->write_buffer =\n+        malloc(sizeof(*(conn->write_buffer)) * conn->write_alloc);\n+    if (conn->read_buffer == NULL || conn->write_buffer == NULL) {\n+        if (conn->read_buffer  != NULL) free(conn->read_buffer);\n+        if (conn->write_buffer != NULL) free(conn->write_buffer);\n+        vector_destroy(conn->call); free(conn); return NULL;\n+    }\n+    /* Make this socket non-blocking. */\n+    fcntl(conn->inet_sock, F_SETFL, O_NONBLOCK);\n+    /* Request connection from server, if this is a client */\n+    if (isclient) {\n+        struct pptp_start_ctrl_conn packet = {\n+            PPTP_HEADER_CTRL(PPTP_START_CTRL_CONN_RQST),\n+            hton16(PPTP_VERSION), 0, 0,\n+            hton32(PPTP_FRAME_CAP), hton32(PPTP_BEARER_CAP),\n+            hton16(PPTP_MAX_CHANNELS), hton16(PPTP_FIRMWARE_VERSION),\n+            PPTP_HOSTNAME, PPTP_VENDOR\n+        };\n+        /* fix this packet, if necessary */\n+        int idx, rc;\n+        idx = get_quirk_index();\n+        if (idx != -1 && pptp_fixups[idx].start_ctrl_conn) {\n+            if ((rc = pptp_fixups[idx].start_ctrl_conn(&packet)))\n+                warn(\"calling the start_ctrl_conn hook failed (%d)\", rc);\n+        }\n+        if (pptp_send_ctrl_packet(conn, &packet, sizeof(packet)))\n+            conn->conn_state = CONN_WAIT_CTL_REPLY;\n+        else\n+            return NULL; /* could not send initial start request. */\n+    }\n+    /* Set up interval/keep-alive timer */\n+    /*   First, register handler for SIGALRM */\n+    sigpipe_create();\n+    sigpipe_assign(SIGALRM);\n+    global.conn = conn;\n+    /* Reset event timer */\n+    pptp_reset_timer();\n+    /* all done. */\n+    return conn;\n+}\n+\n+int pptp_conn_established(PPTP_CONN *conn) {\n+  return (conn->conn_state == CONN_ESTABLISHED);\n+}\n+\n+/* This currently *only* works for client call requests.\n+ * We need to do something else to allocate calls for incoming requests.\n+ */\n+PPTP_CALL * pptp_call_open(PPTP_CONN * conn, int call_id,pptp_call_cb callback,\n+        char *phonenr,int window)\n+{\n+    PPTP_CALL * call;\n+    int idx, rc;\n+    /* Send off the call request */\n+    struct pptp_out_call_rqst packet = {\n+        PPTP_HEADER_CTRL(PPTP_OUT_CALL_RQST),\n+        0,0, /*call_id, sernum */\n+        hton32(PPTP_BPS_MIN), hton32(PPTP_BPS_MAX),\n+        hton32(PPTP_BEARER_CAP), hton32(PPTP_FRAME_CAP),\n+        hton16(window), 0, 0, 0, {0}, {0}\n+    };\n+    assert(conn && conn->call);\n+    assert(conn->conn_state == CONN_ESTABLISHED);\n+    /* Assign call id */\n+    if (!call_id && !vector_scan(conn->call, 0, PPTP_MAX_CHANNELS - 1, &call_id))\n+        /* no more calls available! */\n+        return NULL;\n+    /* allocate structure. */\n+    if ((call = malloc(sizeof(*call))) == NULL) return NULL;\n+    /* Initialize call structure */\n+    call->call_type = PPTP_CALL_PNS;\n+    call->state.pns = PNS_IDLE;\n+    call->call_id   = (u_int16_t) call_id;\n+    call->sernum    = conn->call_serial_number++;\n+    call->callback  = callback;\n+    call->closure   = NULL;\n+    packet.call_id = htons(call->call_id);\n+    packet.call_sernum = htons(call->sernum);\n+    /* if we have a quirk, build a new packet to fit it */\n+    idx = get_quirk_index();\n+    if (idx != -1 && pptp_fixups[idx].out_call_rqst_hook) {\n+        if ((rc = pptp_fixups[idx].out_call_rqst_hook(&packet)))\n+            warn(\"calling the out_call_rqst hook failed (%d)\", rc);\n+    }\n+    /* fill in the phone number if it was specified */\n+    if (phonenr) {\n+        strncpy(packet.phone_num, phonenr, sizeof(packet.phone_num));\n+        packet.phone_len = strlen(phonenr);\n+        if( packet.phone_len > sizeof(packet.phone_num))\n+            packet.phone_len = sizeof(packet.phone_num);\n+        packet.phone_len = hton16 (packet.phone_len);\n+    }\n+    if (pptp_send_ctrl_packet(conn, &packet, sizeof(packet))) {\n+        pptp_reset_timer();\n+        call->state.pns = PNS_WAIT_REPLY;\n+        /* and add it to the call vector */\n+        vector_insert(conn->call, call_id, call);\n+        return call;\n+    } else { /* oops, unsuccessful. Deallocate. */\n+        free(call);\n+        return NULL;\n+    }\n+}\n+\n+/*** pptp_call_close **********************************************************/\n+void pptp_call_close(PPTP_CONN * conn, PPTP_CALL * call)\n+{\n+    struct pptp_call_clear_rqst rqst = {\n+        PPTP_HEADER_CTRL(PPTP_CALL_CLEAR_RQST), 0, 0\n+    };\n+    assert(conn && conn->call); assert(call);\n+    assert(vector_contains(conn->call, call->call_id));\n+    /* haven't thought about PAC yet */\n+    assert(call->call_type == PPTP_CALL_PNS);\n+    assert(call->state.pns != PNS_IDLE);\n+    rqst.call_id = hton16(call->call_id);\n+    /* don't check state against WAIT_DISCONNECT... allow multiple disconnect\n+     * requests to be made.\n+     */\n+    pptp_send_ctrl_packet(conn, &rqst, sizeof(rqst));\n+    pptp_reset_timer();\n+    call->state.pns = PNS_WAIT_DISCONNECT;\n+    /* call structure will be freed when we have confirmation of disconnect. */\n+}\n+\n+/*** hard close ***************************************************************/\n+void pptp_call_destroy(PPTP_CONN *conn, PPTP_CALL *call)\n+{\n+    assert(conn && conn->call); assert(call);\n+    assert(vector_contains(conn->call, call->call_id));\n+    /* notify */\n+    if (call->callback != NULL) call->callback(conn, call, CALL_CLOSE_DONE);\n+    /* deallocate */\n+    vector_remove(conn->call, call->call_id);\n+    free(call);\n+}\n+\n+/*** this is a soft close *****************************************************/\n+void pptp_conn_close(PPTP_CONN * conn, u_int8_t close_reason)\n+{\n+    struct pptp_stop_ctrl_conn rqst = {\n+        PPTP_HEADER_CTRL(PPTP_STOP_CTRL_CONN_RQST),\n+        hton8(close_reason), 0, 0\n+    };\n+    int i;\n+    assert(conn && conn->call);\n+    /* avoid repeated close attempts */\n+    if (conn->conn_state == CONN_IDLE || conn->conn_state == CONN_WAIT_STOP_REPLY)\n+        return;\n+    /* close open calls, if any */\n+    for (i = 0; i < vector_size(conn->call); i++)\n+        pptp_call_close(conn, vector_get_Nth(conn->call, i));\n+    /* now close connection */\n+    info(\"Closing PPTP connection\");\n+    pptp_send_ctrl_packet(conn, &rqst, sizeof(rqst));\n+    pptp_reset_timer(); /* wait 60 seconds for reply */\n+    conn->conn_state = CONN_WAIT_STOP_REPLY;\n+    return;\n+}\n+\n+/*** this is a hard close *****************************************************/\n+void pptp_conn_destroy(PPTP_CONN * conn)\n+{\n+    int i;\n+    assert(conn != NULL); assert(conn->call != NULL);\n+    /* destroy all open calls */\n+    for (i = 0; i < vector_size(conn->call); i++)\n+        pptp_call_destroy(conn, vector_get_Nth(conn->call, i));\n+    /* notify */\n+    if (conn->callback != NULL) conn->callback(conn, CONN_CLOSE_DONE);\n+    sigpipe_close();\n+    close(conn->inet_sock);\n+    /* deallocate */\n+    vector_destroy(conn->call);\n+    free(conn);\n+}\n+\n+/*** Deal with messages, in a non-blocking manner\n+ * Add file descriptors used by pptp to fd_set.\n+ */\n+void pptp_fd_set(PPTP_CONN * conn, fd_set * read_set, fd_set * write_set,\n+                 int * max_fd)\n+{\n+    assert(conn && conn->call);\n+    /* Add fd to write_set if there are outstanding writes. */\n+    if (conn->write_size > 0)\n+        FD_SET(conn->inet_sock, write_set);\n+    /* Always add fd to read_set. (always want something to read) */\n+    FD_SET(conn->inet_sock, read_set);\n+    if (*max_fd < conn->inet_sock) *max_fd = conn->inet_sock;\n+    /* Add signal pipe file descriptor to set */\n+    int sig_fd = sigpipe_fd();\n+    FD_SET(sig_fd, read_set);\n+    if (*max_fd < sig_fd) *max_fd = sig_fd;\n+}\n+\n+/*** handle any pptp file descriptors set in fd_set, and clear them ***********/\n+int pptp_dispatch(PPTP_CONN * conn, fd_set * read_set, fd_set * write_set)\n+{\n+    int r = 0;\n+    assert(conn && conn->call);\n+    /* Check for signals */\n+    if (FD_ISSET(sigpipe_fd(), read_set)) {\n+        if (sigpipe_read() == SIGALRM) pptp_handle_timer();\n+\tFD_CLR(sigpipe_fd(), read_set);\n+    }\n+    /* Check write_set could be set. */\n+    if (FD_ISSET(conn->inet_sock, write_set)) {\n+        FD_CLR(conn->inet_sock, write_set);\n+        if (conn->write_size > 0)\n+            r = pptp_write_some(conn);/* write as much as we can without blocking */\n+    }\n+    /* Check read_set */\n+    if (r >= 0 && FD_ISSET(conn->inet_sock, read_set)) {\n+        void *buffer; size_t size;\n+        FD_CLR(conn->inet_sock, read_set);\n+        r = pptp_read_some(conn); /* read as much as we can without blocking */\n+\tif (r < 0)\n+\t    return r;\n+        /* make packets of the buffer, while we can. */\n+        while (r >= 0 && pptp_make_packet(conn, &buffer, &size)) {\n+            r = pptp_dispatch_packet(conn, buffer, size);\n+            free(buffer);\n+        }\n+    }\n+    /* That's all, folks.  Simple, eh? */\n+    return r;\n+}\n+\n+/*** Non-blocking write *******************************************************/\n+int pptp_write_some(PPTP_CONN * conn) {\n+    ssize_t retval;\n+    assert(conn && conn->call);\n+    retval = write(conn->inet_sock, conn->write_buffer, conn->write_size);\n+    if (retval < 0) { /* error. */\n+        if (errno == EAGAIN || errno == EINTR) {\n+            return 0;\n+        } else { /* a real error */\n+            warn(\"write error: %s\", strerror(errno));\n+\t    return -1;\n+        }\n+    }\n+    assert(retval <= conn->write_size);\n+    conn->write_size -= retval;\n+    memmove(conn->write_buffer, conn->write_buffer + retval, conn->write_size);\n+    ctrlp_rep(conn->write_buffer, retval, 0);\n+    return 0;\n+}\n+\n+/*** Non-blocking read ********************************************************/\n+int pptp_read_some(PPTP_CONN * conn)\n+{\n+    ssize_t retval;\n+    assert(conn && conn->call);\n+    if (conn->read_size == conn->read_alloc) { /* need to alloc more memory */\n+        char *new_buffer = realloc(conn->read_buffer,\n+                sizeof(*(conn->read_buffer)) * conn->read_alloc * 2);\n+        if (new_buffer == NULL) {\n+            warn(\"Out of memory\"); return -1;\n+        }\n+        conn->read_alloc *= 2;\n+        conn->read_buffer = new_buffer;\n+    }\n+    retval = read(conn->inet_sock, conn->read_buffer + conn->read_size,\n+            conn->read_alloc  - conn->read_size);\n+    if (retval == 0) {\n+        warn(\"read returned zero, peer has closed\");\n+        return -1;\n+    }\n+    if (retval < 0) {\n+        if (errno == EINTR || errno == EAGAIN)\n+\t    return 0;\n+        else { /* a real error */\n+            warn(\"read error: %s\", strerror(errno));\n+            return -1;\n+        }\n+    }\n+    conn->read_size += retval;\n+    assert(conn->read_size <= conn->read_alloc);\n+    return 0;\n+}\n+\n+/*** Packet formation *********************************************************/\n+int pptp_make_packet(PPTP_CONN * conn, void **buf, size_t *size)\n+{\n+    struct pptp_header *header;\n+    size_t bad_bytes = 0;\n+    assert(conn && conn->call); assert(buf != NULL); assert(size != NULL);\n+    /* Give up unless there are at least sizeof(pptp_header) bytes */\n+    while ((conn->read_size-bad_bytes) >= sizeof(struct pptp_header)) {\n+        /* Throw out bytes until we have a valid header. */\n+        header = (struct pptp_header *) (conn->read_buffer + bad_bytes);\n+        if (ntoh32(header->magic) != PPTP_MAGIC) goto throwitout;\n+        if (ntoh16(header->reserved0) != 0)\n+            warn(\"reserved0 field is not zero! (0x%x) Cisco feature? \\n\",\n+                    ntoh16(header->reserved0));\n+        if (ntoh16(header->length) < sizeof(struct pptp_header)) goto throwitout;\n+        if (ntoh16(header->length) > PPTP_CTRL_SIZE_MAX) goto throwitout;\n+        /* well.  I guess it's good. Let's see if we've got it all. */\n+        if (ntoh16(header->length) > (conn->read_size-bad_bytes))\n+            /* nope.  Let's wait until we've got it, then. */\n+            goto flushbadbytes;\n+        /* One last check: */\n+        if ((ntoh16(header->pptp_type) == PPTP_MESSAGE_CONTROL) &&\n+                (ntoh16(header->length) !=\n+                         PPTP_CTRL_SIZE(ntoh16(header->ctrl_type))))\n+            goto throwitout;\n+        /* well, I guess we've got it. */\n+        *size = ntoh16(header->length);\n+        *buf = malloc(*size);\n+        if (*buf == NULL) { warn(\"Out of memory.\"); return 0; /* ack! */ }\n+        memcpy(*buf, conn->read_buffer + bad_bytes, *size);\n+        /* Delete this packet from the read_buffer. */\n+        conn->read_size -= (bad_bytes + *size);\n+        memmove(conn->read_buffer, conn->read_buffer + bad_bytes + *size,\n+                conn->read_size);\n+        if (bad_bytes > 0)\n+            warn(\"%lu bad bytes thrown away.\", (unsigned long) bad_bytes);\n+        return 1;\n+throwitout:\n+        bad_bytes++;\n+    }\n+flushbadbytes:\n+    /* no more packets.  Let's get rid of those bad bytes */\n+    conn->read_size -= bad_bytes;\n+    memmove(conn->read_buffer, conn->read_buffer + bad_bytes, conn->read_size);\n+    if (bad_bytes > 0)\n+        warn(\"%lu bad bytes thrown away.\", (unsigned long) bad_bytes);\n+    return 0;\n+}\n+\n+/*** pptp_send_ctrl_packet ****************************************************/\n+int pptp_send_ctrl_packet(PPTP_CONN * conn, void * buffer, size_t size)\n+{\n+    assert(conn && conn->call); assert(buffer);\n+    if( conn->write_size > 0) pptp_write_some( conn);\n+    if( conn->write_size == 0) {\n+        ssize_t retval;\n+        retval = write(conn->inet_sock, buffer, size);\n+        if (retval < 0) { /* error. */\n+            if (errno == EAGAIN || errno == EINTR) {\n+                /* ignore */;\n+                retval = 0;\n+            } else { /* a real error */\n+                warn(\"write error: %s\", strerror(errno));\n+                pptp_conn_destroy(conn); /* shut down fast. */\n+                return 0;\n+            }\n+        }\n+        ctrlp_rep( buffer, retval, 0);\n+        size -= retval;\n+        if( size <= 0) return 1;\n+    }\n+    /* Shove anything not written into the write buffer */\n+    if (conn->write_size + size > conn->write_alloc) { /* need more memory */\n+        char *new_buffer = realloc(conn->write_buffer,\n+                sizeof(*(conn->write_buffer)) * conn->write_alloc * 2);\n+        if (new_buffer == NULL) {\n+            warn(\"Out of memory\"); return 0;\n+        }\n+        conn->write_alloc *= 2;\n+        conn->write_buffer = new_buffer;\n+    }\n+    memcpy(conn->write_buffer + conn->write_size, buffer, size);\n+    conn->write_size += size;\n+    ctrlp_rep( buffer,size,1);\n+    return 1;\n+}\n+\n+/*** Packet Dispatch **********************************************************/\n+int pptp_dispatch_packet(PPTP_CONN * conn, void * buffer, size_t size)\n+{\n+    int r = 0;\n+    struct pptp_header *header = (struct pptp_header *)buffer;\n+    assert(conn && conn->call); assert(buffer);\n+    assert(ntoh32(header->magic) == PPTP_MAGIC);\n+    assert(ntoh16(header->length) == size);\n+    switch (ntoh16(header->pptp_type)) {\n+        case PPTP_MESSAGE_CONTROL:\n+            r = ctrlp_disp(conn, buffer, size);\n+            break;\n+        case PPTP_MESSAGE_MANAGE:\n+            /* MANAGEMENT messages aren't even part of the spec right now. */\n+            dbglog(\"PPTP management message received, but not understood.\");\n+            break;\n+        default:\n+            dbglog(\"Unknown PPTP control message type received: %u\",\n+                    (unsigned int) ntoh16(header->pptp_type));\n+            break;\n+    }\n+    return r;\n+}\n+\n+/*** log echo request/replies *************************************************/\n+static void logecho( int type)\n+{\n+    /* hack to stop flooding the log files (the most interesting part is right\n+     * after the connection built-up) */\n+    if( nlogecho > 0) {\n+        dbglog(\"Echo Re%s received.\", type == PPTP_ECHO_RQST ? \"quest\" :\"ply\");\n+        if( --nlogecho == 0)\n+            dbglog(\"no more Echo Reply/Request packets will be reported.\");\n+    }\n+}\n+\n+/*** pptp_dispatch_ctrl_packet ************************************************/\n+int ctrlp_disp(PPTP_CONN * conn, void * buffer, size_t size)\n+{\n+    struct pptp_header *header = (struct pptp_header *)buffer;\n+    u_int8_t close_reason = PPTP_STOP_NONE;\n+    assert(conn && conn->call); assert(buffer);\n+    assert(ntoh32(header->magic) == PPTP_MAGIC);\n+    assert(ntoh16(header->length) == size);\n+    assert(ntoh16(header->pptp_type) == PPTP_MESSAGE_CONTROL);\n+    if (size < PPTP_CTRL_SIZE(ntoh16(header->ctrl_type))) {\n+        warn(\"Invalid packet received [type: %d; length: %d].\",\n+                (int) ntoh16(header->ctrl_type), (int) size);\n+        return 0;\n+    }\n+    switch (ntoh16(header->ctrl_type)) {\n+        /* ----------- STANDARD Start-Session MESSAGES ------------ */\n+        case PPTP_START_CTRL_CONN_RQST:\n+        {\n+            struct pptp_start_ctrl_conn *packet =\n+                (struct pptp_start_ctrl_conn *) buffer;\n+            struct pptp_start_ctrl_conn reply = {\n+                PPTP_HEADER_CTRL(PPTP_START_CTRL_CONN_RPLY),\n+                hton16(PPTP_VERSION), 0, 0,\n+                hton32(PPTP_FRAME_CAP), hton32(PPTP_BEARER_CAP),\n+                hton16(PPTP_MAX_CHANNELS), hton16(PPTP_FIRMWARE_VERSION),\n+                PPTP_HOSTNAME, PPTP_VENDOR };\n+            int idx, rc;\n+            dbglog(\"Received Start Control Connection Request\");\n+            /* fix this packet, if necessary */\n+            idx = get_quirk_index();\n+            if (idx != -1 && pptp_fixups[idx].start_ctrl_conn) {\n+                if ((rc = pptp_fixups[idx].start_ctrl_conn(&reply)))\n+                    warn(\"calling the start_ctrl_conn hook failed (%d)\", rc);\n+            }\n+            if (conn->conn_state == CONN_IDLE) {\n+                if (ntoh16(packet->version) < PPTP_VERSION) {\n+                    /* Can't support this (earlier) PPTP_VERSION */\n+                    reply.version = packet->version;\n+                    /* protocol version not supported */\n+                    reply.result_code = hton8(5);\n+                    pptp_send_ctrl_packet(conn, &reply, sizeof(reply));\n+                    pptp_reset_timer(); /* give sender a chance for a retry */\n+                } else { /* same or greater version */\n+                    if (pptp_send_ctrl_packet(conn, &reply, sizeof(reply))) {\n+                        conn->conn_state = CONN_ESTABLISHED;\n+                        dbglog(\"server connection ESTABLISHED.\");\n+                        pptp_reset_timer();\n+                    }\n+                }\n+            }\n+            break;\n+        }\n+        case PPTP_START_CTRL_CONN_RPLY:\n+        {\n+            struct pptp_start_ctrl_conn *packet =\n+                (struct pptp_start_ctrl_conn *) buffer;\n+            dbglog(\"Received Start Control Connection Reply\");\n+            if (conn->conn_state == CONN_WAIT_CTL_REPLY) {\n+                /* XXX handle collision XXX [see rfc] */\n+                if (ntoh16(packet->version) != PPTP_VERSION) {\n+                    if (conn->callback != NULL)\n+                        conn->callback(conn, CONN_OPEN_FAIL);\n+                    close_reason = PPTP_STOP_PROTOCOL;\n+                    goto pptp_conn_close;\n+                }\n+                if (ntoh8(packet->result_code) != 1 &&\n+                    /* J'ai change le if () afin que la connection ne se ferme\n+                     * pas pour un \"rien\" :p adel@cybercable.fr -\n+                     *\n+                     * Don't close the connection if the result code is zero\n+                     * (feature found in certain ADSL modems)\n+                     */\n+                        ntoh8(packet->result_code) != 0) {\n+                    dbglog(\"Negative reply received to our Start Control \"\n+                            \"Connection Request\");\n+                    ctrlp_error(packet->result_code, packet->error_code,\n+                            -1, pptp_start_ctrl_conn_rply,\n+                            MAX_START_CTRL_CONN_REPLY);\n+                    if (conn->callback != NULL)\n+                        conn->callback(conn, CONN_OPEN_FAIL);\n+                    close_reason = PPTP_STOP_PROTOCOL;\n+                    goto pptp_conn_close;\n+                }\n+                conn->conn_state = CONN_ESTABLISHED;\n+                /* log session properties */\n+                conn->version      = ntoh16(packet->version);\n+                conn->firmware_rev = ntoh16(packet->firmware_rev);\n+                memcpy(conn->hostname, packet->hostname, sizeof(conn->hostname));\n+                memcpy(conn->vendor, packet->vendor, sizeof(conn->vendor));\n+                pptp_reset_timer(); /* 60 seconds until keep-alive */\n+                dbglog(\"Client connection established.\");\n+                if (conn->callback != NULL)\n+                    conn->callback(conn, CONN_OPEN_DONE);\n+            } /* else goto pptp_conn_close; */\n+            break;\n+        }\n+            /* ----------- STANDARD Stop-Session MESSAGES ------------ */\n+        case PPTP_STOP_CTRL_CONN_RQST:\n+        {\n+            /* conn_state should be CONN_ESTABLISHED, but it could be\n+             * something else */\n+            struct pptp_stop_ctrl_conn reply = {\n+                PPTP_HEADER_CTRL(PPTP_STOP_CTRL_CONN_RPLY),\n+                hton8(1), hton8(PPTP_GENERAL_ERROR_NONE), 0\n+            };\n+            dbglog(\"Received Stop Control Connection Request.\");\n+            if (conn->conn_state == CONN_IDLE) break;\n+            if (pptp_send_ctrl_packet(conn, &reply, sizeof(reply))) {\n+                if (conn->callback != NULL)\n+                    conn->callback(conn, CONN_CLOSE_RQST);\n+                conn->conn_state = CONN_IDLE;\n+\t\treturn -1;\n+            }\n+            break;\n+        }\n+        case PPTP_STOP_CTRL_CONN_RPLY:\n+        {\n+            dbglog(\"Received Stop Control Connection Reply.\");\n+            /* conn_state should be CONN_WAIT_STOP_REPLY, but it\n+             * could be something else */\n+            if (conn->conn_state == CONN_IDLE) break;\n+            conn->conn_state = CONN_IDLE;\n+\t    return -1;\n+        }\n+            /* ----------- STANDARD Echo/Keepalive MESSAGES ------------ */\n+        case PPTP_ECHO_RPLY:\n+        {\n+            struct pptp_echo_rply *packet =\n+                (struct pptp_echo_rply *) buffer;\n+            logecho( PPTP_ECHO_RPLY);\n+            if ((conn->ka_state == KA_OUTSTANDING) &&\n+                    (ntoh32(packet->identifier) == conn->ka_id)) {\n+                conn->ka_id++;\n+                conn->ka_state = KA_NONE;\n+                pptp_reset_timer();\n+            }\n+            break;\n+        }\n+        case PPTP_ECHO_RQST:\n+        {\n+            struct pptp_echo_rqst *packet =\n+                (struct pptp_echo_rqst *) buffer;\n+            struct pptp_echo_rply reply = {\n+                PPTP_HEADER_CTRL(PPTP_ECHO_RPLY),\n+                packet->identifier, /* skip hton32(ntoh32(id)) */\n+                hton8(1), hton8(PPTP_GENERAL_ERROR_NONE), 0\n+            };\n+            logecho( PPTP_ECHO_RQST);\n+            pptp_send_ctrl_packet(conn, &reply, sizeof(reply));\n+            pptp_reset_timer();\n+            break;\n+        }\n+            /* ----------- OUTGOING CALL MESSAGES ------------ */\n+        case PPTP_OUT_CALL_RQST:\n+        {\n+            struct pptp_out_call_rqst *packet =\n+                (struct pptp_out_call_rqst *)buffer;\n+            struct pptp_out_call_rply reply = {\n+                PPTP_HEADER_CTRL(PPTP_OUT_CALL_RPLY),\n+                0 /* callid */, packet->call_id, 1, PPTP_GENERAL_ERROR_NONE, 0,\n+                hton32(PPTP_CONNECT_SPEED),\n+                hton16(PPTP_WINDOW), hton16(PPTP_DELAY), 0\n+            };\n+            dbglog(\"Received Outgoing Call Request.\");\n+            /* XXX PAC: eventually this should make an outgoing call. XXX */\n+            reply.result_code = hton8(7); /* outgoing calls verboten */\n+            pptp_send_ctrl_packet(conn, &reply, sizeof(reply));\n+            break;\n+        }\n+        case PPTP_OUT_CALL_RPLY:\n+        {\n+            struct pptp_out_call_rply *packet =\n+                (struct pptp_out_call_rply *)buffer;\n+            PPTP_CALL * call;\n+            u_int16_t callid = ntoh16(packet->call_id_peer);\n+            dbglog(\"Received Outgoing Call Reply.\");\n+            if (!vector_search(conn->call, (int) callid, &call)) {\n+                dbglog(\"PPTP_OUT_CALL_RPLY received for non-existant call: \"\n+                        \"peer call ID (us)  %d call ID (them) %d.\",\n+                        callid, ntoh16(packet->call_id));\n+                break;\n+            }\n+            if (call->call_type != PPTP_CALL_PNS) {\n+                dbglog(\"Ack!  How did this call_type get here?\"); /* XXX? */\n+                break;\n+            }\n+            if (call->state.pns != PNS_WAIT_REPLY) {\n+                warn(\"Unexpected(?) Outgoing Call Reply will be ignored.\");\n+                break;\n+            }\n+            /* check for errors */\n+            if (packet->result_code != 1) {\n+                /* An error.  Log it verbosely. */\n+                dbglog(\"Our outgoing call request [callid %d] has not been \"\n+                        \"accepted.\", (int) callid);\n+                ctrlp_error(packet->result_code, packet->error_code,\n+                        packet->cause_code, pptp_out_call_reply_result,\n+                        MAX_OUT_CALL_REPLY_RESULT);\n+                call->state.pns = PNS_IDLE;\n+                if (call->callback != NULL)\n+                    call->callback(conn, call, CALL_OPEN_FAIL);\n+                pptp_call_destroy(conn, call);\n+            } else {\n+                /* connection established */\n+                call->state.pns = PNS_ESTABLISHED;\n+                call->peer_call_id = ntoh16(packet->call_id);\n+                call->speed        = ntoh32(packet->speed);\n+                pptp_reset_timer();\n+                /* call pptp_set_link. unless the user specified a quirk\n+                   and this quirk has a set_link hook, this is a noop */\n+                pptp_set_link(conn, call->peer_call_id);\n+                if (call->callback != NULL)\n+                    call->callback(conn, call, CALL_OPEN_DONE);\n+                dbglog(\"Outgoing call established (call ID %u, peer's \"\n+                        \"call ID %u).\\n\", call->call_id, call->peer_call_id);\n+            }\n+            break;\n+        }\n+            /* ----------- INCOMING CALL MESSAGES ------------ */\n+            /* XXX write me XXX */\n+            /* ----------- CALL CONTROL MESSAGES ------------ */\n+        case PPTP_CALL_CLEAR_RQST:\n+        {\n+            struct pptp_call_clear_rqst *packet =\n+                (struct pptp_call_clear_rqst *)buffer;\n+            struct pptp_call_clear_ntfy reply = {\n+                PPTP_HEADER_CTRL(PPTP_CALL_CLEAR_NTFY), packet->call_id,\n+                1, PPTP_GENERAL_ERROR_NONE, 0, 0, {0}\n+            };\n+            dbglog(\"Received Call Clear Request.\");\n+            if (vector_contains(conn->call, ntoh16(packet->call_id))) {\n+                PPTP_CALL * call;\n+                vector_search(conn->call, ntoh16(packet->call_id), &call);\n+                if (call->callback != NULL)\n+                    call->callback(conn, call, CALL_CLOSE_RQST);\n+                pptp_send_ctrl_packet(conn, &reply, sizeof(reply));\n+                pptp_call_destroy(conn, call);\n+                dbglog(\"Call closed (RQST) (call id %d)\", (int) call->call_id);\n+            }\n+            break;\n+        }\n+        case PPTP_CALL_CLEAR_NTFY:\n+        {\n+            struct pptp_call_clear_ntfy *packet =\n+                (struct pptp_call_clear_ntfy *)buffer;\n+            dbglog(\"Call disconnect notification received (call id %d)\",\n+                    ntoh16(packet->call_id));\n+            if (vector_contains(conn->call, ntoh16(packet->call_id))) {\n+                PPTP_CALL * call;\n+                ctrlp_error(packet->result_code, packet->error_code,\n+                        packet->cause_code, pptp_call_disc_ntfy,\n+                        MAX_CALL_DISC_NTFY);\n+                vector_search(conn->call, ntoh16(packet->call_id), &call);\n+                pptp_call_destroy(conn, call);\n+            }\n+            /* XXX we could log call stats here XXX */\n+            /* XXX not all servers send this XXX */\n+            break;\n+        }\n+        case PPTP_SET_LINK_INFO:\n+        {\n+            /* I HAVE NO CLUE WHAT TO DO IF send_accm IS NOT 0! */\n+            /* this is really dealt with in the HDLC deencapsulation, anyway. */\n+            struct pptp_set_link_info *packet =\n+                (struct pptp_set_link_info *)buffer;\n+            /* log it. */\n+            dbglog(\"PPTP_SET_LINK_INFO received from peer_callid %u\",\n+                    (unsigned int) ntoh16(packet->call_id_peer));\n+            dbglog(\"  send_accm is %08lX, recv_accm is %08lX\",\n+                    (unsigned long) ntoh32(packet->send_accm),\n+                    (unsigned long) ntoh32(packet->recv_accm));\n+            if (!(ntoh32(packet->send_accm) == 0 &&\n+                    ntoh32(packet->recv_accm) == 0))\n+                warn(\"Non-zero Async Control Character Maps are not supported!\");\n+            break;\n+        }\n+        default:\n+            dbglog(\"Unrecognized Packet %d received.\",\n+                    (int) ntoh16(((struct pptp_header *)buffer)->ctrl_type));\n+            /* goto pptp_conn_close; */\n+            break;\n+    }\n+    return 0;\n+pptp_conn_close:\n+    warn(\"pptp_conn_close(%d)\", (int) close_reason);\n+    pptp_conn_close(conn, close_reason);\n+    return 0;\n+}\n+\n+/*** pptp_set_link **************************************************************/\n+void pptp_set_link(PPTP_CONN* conn, int peer_call_id)\n+{\n+    int idx, rc;\n+    /* if we need to send a set_link packet because of buggy\n+       hardware or pptp server, do it now */\n+    if ((idx = get_quirk_index()) != -1 && pptp_fixups[idx].set_link_hook) {\n+        struct pptp_set_link_info packet;\n+        if ((rc = pptp_fixups[idx].set_link_hook(&packet, peer_call_id)))\n+            warn(\"calling the set_link hook failed (%d)\", rc);\n+        if (pptp_send_ctrl_packet(conn, &packet, sizeof(packet))) {\n+            pptp_reset_timer();\n+        }\n+    }\n+}\n+\n+/*** Get info from call structure *********************************************/\n+/* NOTE: The peer_call_id is undefined until we get a server response. */\n+void pptp_call_get_ids(PPTP_CONN * conn, PPTP_CALL * call,\n+\t\t       u_int16_t * call_id, u_int16_t * peer_call_id)\n+{\n+    assert(conn != NULL); assert(call != NULL);\n+    *call_id = call->call_id;\n+    *peer_call_id = call->peer_call_id;\n+}\n+\n+/*** pptp_call_closure_put ****************************************************/\n+void   pptp_call_closure_put(PPTP_CONN * conn, PPTP_CALL * call, void *cl)\n+{\n+    assert(conn != NULL); assert(call != NULL);\n+    call->closure = cl;\n+}\n+\n+/*** pptp_call_closure_get ****************************************************/\n+void * pptp_call_closure_get(PPTP_CONN * conn, PPTP_CALL * call)\n+{\n+    assert(conn != NULL); assert(call != NULL);\n+    return call->closure;\n+}\n+\n+/*** pptp_conn_closure_put ****************************************************/\n+void   pptp_conn_closure_put(PPTP_CONN * conn, void *cl)\n+{\n+    assert(conn != NULL);\n+    conn->closure = cl;\n+}\n+\n+/*** pptp_conn_closure_get ****************************************************/\n+void * pptp_conn_closure_get(PPTP_CONN * conn)\n+{\n+    assert(conn != NULL);\n+    return conn->closure;\n+}\n+\n+/*** Reset keep-alive timer ***************************************************/\n+static void pptp_reset_timer(void)\n+{\n+    const struct itimerval tv = { {  0, 0 },   /* stop on time-out */\n+        { idle_wait, 0 } };\n+    if (idle_wait) setitimer(ITIMER_REAL, &tv, NULL);\n+}\n+\n+\n+/*** Handle keep-alive timer **************************************************/\n+static void pptp_handle_timer()\n+{\n+    int i;\n+    /* \"Keep Alives and Timers, 1\": check connection state */\n+    if (global.conn->conn_state != CONN_ESTABLISHED) {\n+        if (global.conn->conn_state == CONN_WAIT_STOP_REPLY)\n+            /* hard close. */\n+            pptp_conn_destroy(global.conn);\n+        else /* soft close */\n+            pptp_conn_close(global.conn, PPTP_STOP_NONE);\n+    }\n+    /* \"Keep Alives and Timers, 2\": check echo status */\n+    if (global.conn->ka_state == KA_OUTSTANDING) {\n+        /* no response to keep-alive */\n+        info(\"closing control connection due to missing echo reply\");\n+\tpptp_conn_close(global.conn, PPTP_STOP_NONE);\n+    } else { /* ka_state == NONE */ /* send keep-alive */\n+        struct pptp_echo_rqst rqst = {\n+            PPTP_HEADER_CTRL(PPTP_ECHO_RQST), hton32(global.conn->ka_id) };\n+        pptp_send_ctrl_packet(global.conn, &rqst, sizeof(rqst));\n+        global.conn->ka_state = KA_OUTSTANDING;\n+    }\n+    /* check incoming/outgoing call states for !IDLE && !ESTABLISHED */\n+    for (i = 0; i < vector_size(global.conn->call); i++) {\n+        PPTP_CALL * call = vector_get_Nth(global.conn->call, i);\n+        if (call->call_type == PPTP_CALL_PNS) {\n+            if (call->state.pns == PNS_WAIT_REPLY) {\n+                /* send close request */\n+                pptp_call_close(global.conn, call);\n+                assert(call->state.pns == PNS_WAIT_DISCONNECT);\n+            } else if (call->state.pns == PNS_WAIT_DISCONNECT) {\n+                /* hard-close the call */\n+                pptp_call_destroy(global.conn, call);\n+            }\n+        } else if (call->call_type == PPTP_CALL_PAC) {\n+            if (call->state.pac == PAC_WAIT_REPLY) {\n+                /* XXX FIXME -- drop the PAC connection XXX */\n+            } else if (call->state.pac == PAC_WAIT_CS_ANS) {\n+                /* XXX FIXME -- drop the PAC connection XXX */\n+            }\n+        }\n+    }\n+    pptp_reset_timer();\n+}\n--- /dev/null\n+++ b/pppd/plugins/pptp/pptp_ctrl.h\n@@ -0,0 +1,57 @@\n+/* pptp_ctrl.h ... handle PPTP control connection.\n+ *                 C. Scott Ananian <cananian@alumni.princeton.edu>\n+ *\n+ * $Id: pptp_ctrl.h,v 1.5 2004/11/09 01:42:32 quozl Exp $\n+ */\n+\n+#ifndef INC_PPTP_CTRL_H\n+#define INC_PPTP_CTRL_H\n+#include <sys/types.h>\n+\n+typedef struct PPTP_CONN PPTP_CONN;\n+typedef struct PPTP_CALL PPTP_CALL;\n+\n+enum call_state { CALL_OPEN_RQST,  CALL_OPEN_DONE, CALL_OPEN_FAIL,\n+\t\t  CALL_CLOSE_RQST, CALL_CLOSE_DONE };\n+enum conn_state { CONN_OPEN_RQST,  CONN_OPEN_DONE, CONN_OPEN_FAIL,\n+\t\t  CONN_CLOSE_RQST, CONN_CLOSE_DONE };\n+\n+typedef void (*pptp_call_cb)(PPTP_CONN*, PPTP_CALL*, enum call_state);\n+typedef void (*pptp_conn_cb)(PPTP_CONN*, enum conn_state);\n+\n+/* if 'isclient' is true, then will send 'conn open' packet to other host.\n+ * not necessary if this is being opened by a server process after\n+ * receiving a conn_open packet from client.\n+ */\n+PPTP_CONN * pptp_conn_open(int inet_sock, int isclient,\n+\t\t\t   pptp_conn_cb callback);\n+PPTP_CALL * pptp_call_open(PPTP_CONN * conn, int call_id,\n+\t\t\t   pptp_call_cb callback, char *phonenr,int window);\n+int pptp_conn_established(PPTP_CONN * conn);\n+/* soft close.  Will callback on completion. */\n+void pptp_call_close(PPTP_CONN * conn, PPTP_CALL * call);\n+/* hard close. */\n+void pptp_call_destroy(PPTP_CONN *conn, PPTP_CALL *call);\n+/* soft close.  Will callback on completion. */\n+void pptp_conn_close(PPTP_CONN * conn, u_int8_t close_reason);\n+/* hard close */\n+void pptp_conn_destroy(PPTP_CONN * conn);\n+\n+/* Add file descriptors used by pptp to fd_set. */\n+void pptp_fd_set(PPTP_CONN * conn, fd_set * read_set, fd_set * write_set, int *max_fd);\n+/* handle any pptp file descriptors set in fd_set, and clear them */\n+int pptp_dispatch(PPTP_CONN * conn, fd_set * read_set, fd_set * write_set);\n+\n+/* Get info about connection, call */\n+void pptp_call_get_ids(PPTP_CONN * conn, PPTP_CALL * call,\n+\t\t       u_int16_t * call_id, u_int16_t * peer_call_id);\n+/* Arbitrary user data about this call/connection.\n+ * It is the caller's responsibility to free this data before calling\n+ * pptp_call|conn_close()\n+ */\n+void * pptp_conn_closure_get(PPTP_CONN * conn);\n+void   pptp_conn_closure_put(PPTP_CONN * conn, void *cl);\n+void * pptp_call_closure_get(PPTP_CONN * conn, PPTP_CALL * call);\n+void   pptp_call_closure_put(PPTP_CONN * conn, PPTP_CALL * call, void *cl);\n+\n+#endif /* INC_PPTP_CTRL_H */\n--- /dev/null\n+++ b/pppd/plugins/pptp/pptp_msg.h\n@@ -0,0 +1,303 @@\n+/*  pptp.h:  packet structures and magic constants for the PPTP protocol \n+ *           C. Scott Ananian <cananian@alumni.princeton.edu>            \n+ *\n+ * $Id: pptp_msg.h,v 1.3 2003/02/15 10:37:21 quozl Exp $\n+ */\n+\n+#ifndef INC_PPTP_H\n+#define INC_PPTP_H\n+\n+/* Grab definitions of int16, int32, etc. */\n+#include <sys/types.h>\n+/* define \"portable\" htons, etc. */\n+#define hton8(x)  (x)\n+#define ntoh8(x)  (x)\n+#define hton16(x) htons(x)\n+#define ntoh16(x) ntohs(x)\n+#define hton32(x) htonl(x)\n+#define ntoh32(x) ntohl(x)\n+\n+/* PPTP magic numbers: ----------------------------------------- */\n+\n+#define PPTP_MAGIC 0x1A2B3C4D /* Magic cookie for PPTP datagrams */\n+#define PPTP_PORT  1723       /* PPTP TCP port number            */\n+#define PPTP_PROTO 47         /* PPTP IP protocol number         */\n+\n+/* Control Connection Message Types: --------------------------- */\n+\n+#define PPTP_MESSAGE_CONTROL\t\t1\n+#define PPTP_MESSAGE_MANAGE\t\t2\n+\n+/* Control Message Types: -------------------------------------- */\n+\n+/* (Control Connection Management) */\n+#define PPTP_START_CTRL_CONN_RQST\t1\n+#define PPTP_START_CTRL_CONN_RPLY\t2\n+#define PPTP_STOP_CTRL_CONN_RQST\t3\n+#define PPTP_STOP_CTRL_CONN_RPLY\t4\n+#define PPTP_ECHO_RQST\t\t\t5\n+#define PPTP_ECHO_RPLY\t\t\t6\n+\n+/* (Call Management) */\n+#define PPTP_OUT_CALL_RQST\t\t7\n+#define PPTP_OUT_CALL_RPLY\t\t8\n+#define PPTP_IN_CALL_RQST\t\t9\n+#define PPTP_IN_CALL_RPLY\t\t10\n+#define PPTP_IN_CALL_CONNECT\t\t11\n+#define PPTP_CALL_CLEAR_RQST\t\t12\n+#define PPTP_CALL_CLEAR_NTFY\t\t13\n+\n+/* (Error Reporting) */\n+#define PPTP_WAN_ERR_NTFY\t\t14\n+\n+/* (PPP Session Control) */\n+#define PPTP_SET_LINK_INFO\t\t15\n+\n+/* PPTP version information: --------------------------------------*/\n+#define PPTP_VERSION_STRING\t\"1.00\"\n+#define PPTP_VERSION\t\t0x100\n+#define PPTP_FIRMWARE_STRING\t\"0.01\"\n+#define PPTP_FIRMWARE_VERSION\t0x001\n+\n+/* PPTP capabilities: ---------------------------------------------*/\n+\n+/* (Framing capabilities for msg sender) */\n+#define PPTP_FRAME_ASYNC\t1\n+#define PPTP_FRAME_SYNC\t\t2\n+#define PPTP_FRAME_ANY          3\n+\n+/* (Bearer capabilities for msg sender) */\n+#define PPTP_BEARER_ANALOG\t1\n+#define PPTP_BEARER_DIGITAL \t2\n+#define PPTP_BEARER_ANY\t\t3\n+\n+#define PPTP_RESULT_GENERAL_ERROR 2\n+\n+/* (Reasons to close a connection) */\n+#define PPTP_STOP_NONE\t\t  1 /* no good reason                        */\n+#define PPTP_STOP_PROTOCOL\t  2 /* can't support peer's protocol version */\n+#define PPTP_STOP_LOCAL_SHUTDOWN  3 /* requester is being shut down          */\n+\n+/* PPTP datagram structures (all data in network byte order): ----------*/\n+\n+struct pptp_header {\n+  u_int16_t length;\t  /* message length in octets, including header */\n+  u_int16_t pptp_type;\t  /* PPTP message type. 1 for control message.  */\n+  u_int32_t magic;\t  /* this should be PPTP_MAGIC.                 */\n+  u_int16_t ctrl_type;\t  /* Control message type (0-15)                */\n+  u_int16_t reserved0;\t  /* reserved.  MUST BE ZERO.                   */\n+};\n+\n+struct pptp_start_ctrl_conn { /* for control message types 1 and 2 */\n+  struct pptp_header header;\n+\n+  u_int16_t version;      /* PPTP protocol version.  = PPTP_VERSION     */\n+  u_int8_t  result_code;  /* these two fields should be zero on rqst msg*/\n+  u_int8_t  error_code;   /* 0 unless result_code==2 (General Error)    */\n+  u_int32_t framing_cap;  /* Framing capabilities                       */\n+  u_int32_t bearer_cap;   /* Bearer Capabilities                        */\n+  u_int16_t max_channels; /* Maximum Channels (=0 for PNS, PAC ignores) */\n+  u_int16_t firmware_rev; /* Firmware or Software Revision              */\n+  u_int8_t  hostname[64]; /* Host Name (64 octets, zero terminated)     */\n+  u_int8_t  vendor[64];   /* Vendor string (64 octets, zero term.)      */\n+  /* MS says that end of hostname/vendor fields should be filled with   */\n+  /* octets of value 0, but Win95 PPTP driver doesn't do this.          */\n+};\n+\n+struct pptp_stop_ctrl_conn { /* for control message types 3 and 4 */\n+  struct pptp_header header;\n+\n+  u_int8_t reason_result; /* reason for rqst, result for rply          */\n+  u_int8_t error_code;\t  /* MUST be 0, unless rply result==2 (general err)*/\n+  u_int16_t reserved1;    /* MUST be 0                                */\n+};\n+\n+struct pptp_echo_rqst { /* for control message type 5 */\n+  struct pptp_header header;\n+  u_int32_t identifier;   /* arbitrary value set by sender which is used */\n+                          /* to match up reply and request               */\n+};\n+\n+struct pptp_echo_rply { /* for control message type 6 */\n+  struct pptp_header header;\n+  u_int32_t identifier;\t  /* should correspond to id of rqst             */\n+  u_int8_t result_code;\n+  u_int8_t error_code;    /* =0, unless result_code==2 (general error)   */\n+  u_int16_t reserved1;    /* MUST BE ZERO                                */\n+};\n+\n+struct pptp_out_call_rqst { /* for control message type 7 */\n+  struct pptp_header header;\n+  u_int16_t call_id;\t  /* Call ID (unique id used to multiplex data)  */\n+  u_int16_t call_sernum;  /* Call Serial Number (used for logging)       */\n+  u_int32_t bps_min;      /* Minimum BPS (lowest acceptable line speed)  */\n+  u_int32_t bps_max;\t  /* Maximum BPS (highest acceptable line speed) */\n+  u_int32_t bearer;\t  /* Bearer type                                 */\n+  u_int32_t framing;      /* Framing type                                */\n+  u_int16_t recv_size;\t  /* Recv. Window Size (no. of buffered packets) */\n+  u_int16_t delay;\t  /* Packet Processing Delay (in 1/10 sec)       */\n+  u_int16_t phone_len;\t  /* Phone Number Length (num. of valid digits)  */\n+  u_int16_t reserved1;    /* MUST BE ZERO\t\t\t\t */\n+  u_int8_t  phone_num[64]; /* Phone Number (64 octets, null term.)       */\n+  u_int8_t subaddress[64]; /* Subaddress (64 octets, null term.)         */\n+};\n+\n+struct pptp_out_call_rply { /* for control message type 8 */\n+  struct pptp_header header;\n+  u_int16_t call_id;      /* Call ID (used to multiplex data over tunnel)*/\n+  u_int16_t call_id_peer; /* Peer's Call ID (call_id of pptp_out_call_rqst)*/\n+  u_int8_t  result_code;  /* Result Code (1 is no errors)                */\n+  u_int8_t  error_code;   /* Error Code (=0 unless result_code==2)       */\n+  u_int16_t cause_code;   /* Cause Code (addt'l failure information)     */\n+  u_int32_t speed;        /* Connect Speed (in BPS)                      */\n+  u_int16_t recv_size;    /* Recv. Window Size (no. of buffered packets) */\n+  u_int16_t delay;\t  /* Packet Processing Delay (in 1/10 sec)       */\n+  u_int32_t channel;      /* Physical Channel ID (for logging)           */\n+};\n+\n+struct pptp_in_call_rqst { /* for control message type 9 */\n+  struct pptp_header header;\n+  u_int16_t call_id;\t  /* Call ID (unique id used to multiplex data)  */\n+  u_int16_t call_sernum;  /* Call Serial Number (used for logging)       */\n+  u_int32_t bearer;\t  /* Bearer type                                 */\n+  u_int32_t channel;      /* Physical Channel ID (for logging)           */\n+  u_int16_t dialed_len;   /* Dialed Number Length (# of valid digits)    */\n+  u_int16_t dialing_len;  /* Dialing Number Length (# of valid digits)   */\n+  u_int8_t dialed_num[64]; /* Dialed Number (64 octets, zero term.)      */\n+  u_int8_t dialing_num[64]; /* Dialing Number (64 octets, zero term.)    */\n+  u_int8_t subaddress[64];  /* Subaddress (64 octets, zero term.)        */\n+};\n+\n+struct pptp_in_call_rply { /* for control message type 10 */\n+  struct pptp_header header;\n+  u_int16_t call_id;      /* Call ID (used to multiplex data over tunnel)*/\n+  u_int16_t call_id_peer; /* Peer's Call ID (call_id of pptp_out_call_rqst)*/\n+  u_int8_t  result_code;  /* Result Code (1 is no errors)                */\n+  u_int8_t  error_code;   /* Error Code (=0 unless result_code==2)       */\n+  u_int16_t recv_size;    /* Recv. Window Size (no. of buffered packets) */\n+  u_int16_t delay;\t  /* Packet Processing Delay (in 1/10 sec)       */\n+  u_int16_t reserved1;    /* MUST BE ZERO                                */\n+};\n+\n+struct pptp_in_call_connect { /* for control message type 11 */\n+  struct pptp_header header;\n+  u_int16_t call_id_peer; /* Peer's Call ID (call_id of pptp_out_call_rqst)*/\n+  u_int16_t reserved1;    /* MUST BE ZERO                                */\n+  u_int32_t speed;        /* Connect Speed (in BPS)                      */\n+  u_int16_t recv_size;    /* Recv. Window Size (no. of buffered packets) */\n+  u_int16_t delay;\t  /* Packet Processing Delay (in 1/10 sec)       */\n+  u_int32_t framing;      /* Framing type                                */\n+};\n+\n+struct pptp_call_clear_rqst { /* for control message type 12 */\n+  struct pptp_header header;\n+  u_int16_t call_id;      /* Call ID (used to multiplex data over tunnel)*/\n+  u_int16_t reserved1;    /* MUST BE ZERO                                */\n+};\n+\n+struct pptp_call_clear_ntfy { /* for control message type 13 */\n+  struct pptp_header header;\n+  u_int16_t call_id;      /* Call ID (used to multiplex data over tunnel)*/\n+  u_int8_t  result_code;  /* Result Code                                 */\n+  u_int8_t  error_code;   /* Error Code (=0 unless result_code==2)       */\n+  u_int16_t cause_code;   /* Cause Code (for ISDN, is Q.931 cause code)  */\n+  u_int16_t reserved1;    /* MUST BE ZERO                                */\n+  u_int8_t call_stats[128]; /* Call Statistics: 128 octets, ascii, 0-term */\n+};\n+\n+struct pptp_wan_err_ntfy {    /* for control message type 14 */\n+  struct pptp_header header;\n+  u_int16_t call_id_peer; /* Peer's Call ID (call_id of pptp_out_call_rqst)*/\n+  u_int16_t reserved1;    /* MUST BE ZERO                                */\n+  u_int32_t crc_errors;   /* CRC errors \t\t\t\t */\n+  u_int32_t frame_errors; /* Framing errors \t\t\t\t */\n+  u_int32_t hard_errors;  /* Hardware overruns \t\t\t\t */\n+  u_int32_t buff_errors;  /* Buffer overruns\t\t\t\t */\n+  u_int32_t time_errors;  /* Time-out errors\t\t\t\t */\n+  u_int32_t align_errors; /* Alignment errors\t\t\t\t */\n+};\n+\n+struct pptp_set_link_info {   /* for control message type 15 */\n+  struct pptp_header header;\n+  u_int16_t call_id_peer; /* Peer's Call ID (call_id of pptp_out_call_rqst) */\n+  u_int16_t reserved1;    /* MUST BE ZERO                                   */\n+  u_int32_t send_accm;    /* Send ACCM (for PPP packets; default 0xFFFFFFFF)*/\n+  u_int32_t recv_accm;    /* Receive ACCM (for PPP pack.;default 0xFFFFFFFF)*/\n+};\n+\n+/* helpful #defines: -------------------------------------------- */\n+#define pptp_isvalid_ctrl(header, type, length) \\\n+ (!( ( ntoh16(((struct pptp_header *)header)->length)    < (length)  ) ||   \\\n+     ( ntoh16(((struct pptp_header *)header)->pptp_type) !=(type)    ) ||   \\\n+     ( ntoh32(((struct pptp_header *)header)->magic)     !=PPTP_MAGIC) ||   \\\n+     ( ntoh16(((struct pptp_header *)header)->ctrl_type) > PPTP_SET_LINK_INFO) || \\\n+     ( ntoh16(((struct pptp_header *)header)->reserved0) !=0         ) ))\n+\n+#define PPTP_HEADER_CTRL(type)  \\\n+{ hton16(PPTP_CTRL_SIZE(type)), \\\n+  hton16(PPTP_MESSAGE_CONTROL), \\\n+  hton32(PPTP_MAGIC),           \\\n+  hton16(type), 0 }             \n+\n+#define PPTP_CTRL_SIZE(type) ( \\\n+(type==PPTP_START_CTRL_CONN_RQST)?sizeof(struct pptp_start_ctrl_conn):\t\\\n+(type==PPTP_START_CTRL_CONN_RPLY)?sizeof(struct pptp_start_ctrl_conn):\t\\\n+(type==PPTP_STOP_CTRL_CONN_RQST )?sizeof(struct pptp_stop_ctrl_conn):\t\\\n+(type==PPTP_STOP_CTRL_CONN_RPLY )?sizeof(struct pptp_stop_ctrl_conn):\t\\\n+(type==PPTP_ECHO_RQST           )?sizeof(struct pptp_echo_rqst):\t\\\n+(type==PPTP_ECHO_RPLY           )?sizeof(struct pptp_echo_rply):\t\\\n+(type==PPTP_OUT_CALL_RQST       )?sizeof(struct pptp_out_call_rqst):\t\\\n+(type==PPTP_OUT_CALL_RPLY       )?sizeof(struct pptp_out_call_rply):\t\\\n+(type==PPTP_IN_CALL_RQST        )?sizeof(struct pptp_in_call_rqst):\t\\\n+(type==PPTP_IN_CALL_RPLY        )?sizeof(struct pptp_in_call_rply):\t\\\n+(type==PPTP_IN_CALL_CONNECT     )?sizeof(struct pptp_in_call_connect):\t\\\n+(type==PPTP_CALL_CLEAR_RQST     )?sizeof(struct pptp_call_clear_rqst):\t\\\n+(type==PPTP_CALL_CLEAR_NTFY     )?sizeof(struct pptp_call_clear_ntfy):\t\\\n+(type==PPTP_WAN_ERR_NTFY        )?sizeof(struct pptp_wan_err_ntfy):\t\\\n+(type==PPTP_SET_LINK_INFO       )?sizeof(struct pptp_set_link_info):\t\\\n+0)\n+#define max(a,b) (((a)>(b))?(a):(b))\n+#define PPTP_CTRL_SIZE_MAX (\t\t\t\\\n+max(sizeof(struct pptp_start_ctrl_conn),\t\\\n+max(sizeof(struct pptp_echo_rqst),\t\t\\\n+max(sizeof(struct pptp_echo_rply),\t\t\\\n+max(sizeof(struct pptp_out_call_rqst),\t\t\\\n+max(sizeof(struct pptp_out_call_rply),\t\t\\\n+max(sizeof(struct pptp_in_call_rqst),\t\t\\\n+max(sizeof(struct pptp_in_call_rply),\t\t\\\n+max(sizeof(struct pptp_in_call_connect),\t\\\n+max(sizeof(struct pptp_call_clear_rqst),\t\\\n+max(sizeof(struct pptp_call_clear_ntfy),\t\\\n+max(sizeof(struct pptp_wan_err_ntfy),\t\t\\\n+max(sizeof(struct pptp_set_link_info), 0)))))))))))))\n+\n+\n+/* gre header structure: -------------------------------------------- */\n+\n+#define PPTP_GRE_PROTO  0x880B\n+#define PPTP_GRE_VER    0x1\n+\n+#define PPTP_GRE_FLAG_C\t0x80\n+#define PPTP_GRE_FLAG_R\t0x40\n+#define PPTP_GRE_FLAG_K\t0x20\n+#define PPTP_GRE_FLAG_S\t0x10\n+#define PPTP_GRE_FLAG_A\t0x80\n+\n+#define PPTP_GRE_IS_C(f) ((f)&PPTP_GRE_FLAG_C)\n+#define PPTP_GRE_IS_R(f) ((f)&PPTP_GRE_FLAG_R)\n+#define PPTP_GRE_IS_K(f) ((f)&PPTP_GRE_FLAG_K)\n+#define PPTP_GRE_IS_S(f) ((f)&PPTP_GRE_FLAG_S)\n+#define PPTP_GRE_IS_A(f) ((f)&PPTP_GRE_FLAG_A)\n+\n+struct pptp_gre_header {\n+  u_int8_t flags;\t\t/* bitfield */\n+  u_int8_t ver;\t\t\t/* should be PPTP_GRE_VER (enhanced GRE) */\n+  u_int16_t protocol;\t\t/* should be PPTP_GRE_PROTO (ppp-encaps) */\n+  u_int16_t payload_len;\t/* size of ppp payload, not inc. gre header */\n+  u_int16_t call_id;\t\t/* peer's call_id for this session */\n+  u_int32_t seq;\t\t/* sequence number.  Present if S==1 */\n+  u_int32_t ack;\t\t/* seq number of highest packet recieved by */\n+  \t\t\t\t/*  sender in this session */\n+};\n+\n+#endif /* INC_PPTP_H */\n--- /dev/null\n+++ b/pppd/plugins/pptp/pptp_options.h\n@@ -0,0 +1,41 @@\n+/* pptp_options.h ...... various constants used in the PPTP protocol.\n+ *                       #define STANDARD to emulate NT 4.0 exactly.\n+ *                       C. Scott Ananian <cananian@alumni.princeton.edu>\n+ *\n+ * $Id: pptp_options.h,v 1.3 2004/11/09 01:42:32 quozl Exp $\n+ */\n+\n+#ifndef INC_PPTP_OPTIONS_H\n+#define INC_PPTP_OPTIONS_H\n+\n+#undef  PPTP_FIRMWARE_STRING\n+#undef  PPTP_FIRMWARE_VERSION\n+#define PPTP_BUF_MAX 65536\n+#define PPTP_TIMEOUT 60 /* seconds */\n+extern int idle_wait;\n+extern int max_echo_wait;\n+#define PPTP_CONNECT_SPEED 1000000000\n+#define PPTP_WINDOW 3\n+#define PPTP_DELAY  0\n+#define PPTP_BPS_MIN 2400\n+#define PPTP_BPS_MAX 1000000000\n+\n+#ifndef STANDARD\n+#define PPTP_MAX_CHANNELS 65535\n+#define PPTP_FIRMWARE_STRING \"0.01\"\n+#define PPTP_FIRMWARE_VERSION 0x001\n+#define PPTP_HOSTNAME {'l','o','c','a','l',0}\n+#define PPTP_VENDOR   {'c','a','n','a','n','i','a','n',0}\n+#define PPTP_FRAME_CAP  PPTP_FRAME_ANY\n+#define PPTP_BEARER_CAP PPTP_BEARER_ANY\n+#else\n+#define PPTP_MAX_CHANNELS 5\n+#define PPTP_FIRMWARE_STRING \"0.01\"\n+#define PPTP_FIRMWARE_VERSION 0\n+#define PPTP_HOSTNAME {'l','o','c','a','l',0}\n+#define PPTP_VENDOR   {'N','T',0}\n+#define PPTP_FRAME_CAP  2\n+#define PPTP_BEARER_CAP 1\n+#endif\n+\n+#endif /* INC_PPTP_OPTIONS_H */\n--- /dev/null\n+++ b/pppd/plugins/pptp/pptp_quirks.c\n@@ -0,0 +1,54 @@\n+/* pptp_quirks.c ...... various options to fix quirks found in buggy adsl modems\n+ *                      mulix <mulix@actcom.co.il>\n+ *\n+ * $Id: pptp_quirks.c,v 1.2 2001/11/23 03:42:51 quozl Exp $\n+ */\n+\n+#include <string.h>\n+#include \"orckit_quirks.h\"\n+#include \"pptp_quirks.h\"\n+\n+static int quirk_index = -1;\n+\n+struct pptp_fixup pptp_fixups[] = {\n+    {BEZEQ_ISRAEL, ORCKIT, ORCKIT_ATUR3,\n+     orckit_atur3_build_hook,\n+     orckit_atur3_start_ctrl_conn_hook,\n+     orckit_atur3_set_link_hook}\n+};\n+\n+static int fixups_sz = sizeof(pptp_fixups)/sizeof(pptp_fixups[0]);\n+\n+/* return 0 on success, non 0 otherwise */\n+int set_quirk_index(int index)\n+{\n+    if (index >= 0 && index < fixups_sz) {\n+\tquirk_index = index;\n+\treturn 0;\n+    }\n+\n+    return -1;\n+}\n+\n+int get_quirk_index()\n+{\n+    return quirk_index;\n+}\n+\n+/* return the index for this isp in the quirks table, -1 if not found */\n+int find_quirk(const char* isp_name)\n+{\n+    int i = 0;\n+    if (isp_name) {\n+\twhile (i < fixups_sz && pptp_fixups[i].isp) {\n+\t    if (!strcmp(pptp_fixups[i].isp, isp_name)) {\n+\t\treturn i;\n+\t    }\n+\t    ++i;\n+\t}\n+    }\n+\n+    return -1;\n+}\n+\n+\n--- /dev/null\n+++ b/pppd/plugins/pptp/pptp_quirks.h\n@@ -0,0 +1,59 @@\n+/* pptp_quirks.h ...... various options to fix quirks found in buggy adsl modems\n+ *                      mulix <mulix@actcom.co.il>\n+ *\n+ * $Id: pptp_quirks.h,v 1.1 2001/11/20 06:30:10 quozl Exp $\n+ */\n+\n+#ifndef INC_PPTP_QUIRKS_H\n+#define INC_PPTP_QUIRKS_H\n+\n+/* isp defs - correspond to slots in the fixups table */\n+#define BEZEQ_ISRAEL \"BEZEQ_ISRAEL\"\n+\n+/* vendor defs */\n+\n+#define ORCKIT 1\n+#define ALCATEL 2\n+\n+/* device defs */\n+\n+#define ORCKIT_ATUR2 1\n+#define ORCKIT_ATUR3 2\n+\n+#include \"pptp_msg.h\"\n+#include \"pptp_ctrl.h\"\n+\n+struct pptp_fixup {\n+    const char* isp;    /* which isp? e.g. Bezeq in Israel */\n+    int vendor; /* which vendor? e.g. Orckit */\n+    int device; /* which device? e.g. Orckit Atur3 */\n+\n+    /* use this hook to build your own out call request packet */\n+    int (*out_call_rqst_hook)(struct pptp_out_call_rqst* packet);\n+\n+    /* use this hook to build your own start control connection packet */\n+    /* note that this hook is called from two different places, depending\n+       on whether this is a request or reply */\n+    int (*start_ctrl_conn)(struct pptp_start_ctrl_conn* packet);\n+\n+    /* use this hook if you need to send a 'set_link' packet once\n+       the connection is established */\n+    int (*set_link_hook)(struct pptp_set_link_info* packet,\n+\t\t\t int peer_call_id);\n+};\n+\n+extern struct pptp_fixup pptp_fixups[];\n+\n+/* find the index for this isp in the quirks table */\n+/* return the index on success, -1 if not found */\n+int find_quirk(const char* isp_name);\n+\n+/* set the global quirk index. return 0 on success, non 0 otherwise */\n+int set_quirk_index(int index);\n+\n+/* get the global quirk index. return the index on success,\n+   -1 if no quirk is defined */\n+int get_quirk_index();\n+\n+\n+#endif /* INC_PPTP_QUIRKS_H */\n--- /dev/null\n+++ b/pppd/plugins/pptp/util.c\n@@ -0,0 +1,109 @@\n+/* util.c ....... error message utilities.\n+ *                C. Scott Ananian <cananian@alumni.princeton.edu>\n+ *\n+ * $Id: util.c,v 1.11 2005/08/22 00:49:48 quozl Exp $\n+ */\n+\n+#include <stdio.h>\n+#include <stdarg.h>\n+#include <syslog.h>\n+#include <unistd.h>\n+#include <stdlib.h>\n+#include \"util.h\"\n+\n+#define MAKE_STRING(label) \t\t\t\t\\\n+va_list ap;\t\t\t\t\t\t\\\n+char buf[256], string[256];\t\t\t\t\\\n+va_start(ap, format);\t\t\t\t\t\\\n+vsnprintf(buf, sizeof(buf), format, ap);\t\t\\\n+snprintf(string, sizeof(string), \"%s %s[%s:%s:%d]: %s\",\t\\\n+\t log_string, label, func, file, line, buf);\t\\\n+va_end(ap)\n+\n+/*** connect a file to a file descriptor **************************************/\n+int file2fd(const char *path, const char *mode, int fd)\n+{\n+    int ok = 0;\n+    FILE *file = NULL;\n+    file = fopen(path, mode);\n+    if (file != NULL && dup2(fileno(file), fd) != -1)\n+        ok = 1;\n+    if (file) fclose(file);\n+    return ok;\n+}\n+\n+/* signal to pipe delivery implementation */\n+#include <unistd.h>\n+#include <fcntl.h>\n+#include <signal.h>\n+#include <string.h>\n+\n+/* pipe private to process */\n+static int sigpipe[2];\n+\n+/* create a signal pipe, returns 0 for success, -1 with errno for failure */\n+int sigpipe_create()\n+{\n+  int rc;\n+  \n+  rc = pipe(sigpipe);\n+  if (rc < 0) return rc;\n+  \n+  fcntl(sigpipe[0], F_SETFD, FD_CLOEXEC);\n+  fcntl(sigpipe[1], F_SETFD, FD_CLOEXEC);\n+  \n+#ifdef O_NONBLOCK\n+#define FLAG_TO_SET O_NONBLOCK\n+#else\n+#ifdef SYSV\n+#define FLAG_TO_SET O_NDELAY\n+#else /* BSD */\n+#define FLAG_TO_SET FNDELAY\n+#endif\n+#endif\n+  \n+  rc = fcntl(sigpipe[1], F_GETFL);\n+  if (rc != -1)\n+    rc = fcntl(sigpipe[1], F_SETFL, rc | FLAG_TO_SET);\n+  if (rc < 0) return rc;\n+  return 0;\n+#undef FLAG_TO_SET\n+}\n+\n+/* generic handler for signals, writes signal number to pipe */\n+void sigpipe_handler(int signum)\n+{\n+  write(sigpipe[1], &signum, sizeof(signum));\n+  signal(signum, sigpipe_handler);\n+}\n+\n+/* assign a signal number to the pipe */\n+void sigpipe_assign(int signum)\n+{\n+  struct sigaction sa;\n+\n+  memset(&sa, 0, sizeof(sa));\n+  sa.sa_handler = sigpipe_handler;\n+  sigaction(signum, &sa, NULL);\n+}\n+\n+/* return the signal pipe read file descriptor for select(2) */\n+int sigpipe_fd()\n+{\n+  return sigpipe[0];\n+}\n+\n+/* read and return the pending signal from the pipe */\n+int sigpipe_read()\n+{\n+  int signum;\n+  read(sigpipe[0], &signum, sizeof(signum));\n+  return signum;\n+}\n+\n+void sigpipe_close()\n+{\n+  close(sigpipe[0]);\n+  close(sigpipe[1]);\n+}\n+\n--- /dev/null\n+++ b/pppd/plugins/pptp/util.h\n@@ -0,0 +1,31 @@\n+/* util.h ....... error message utilities.\n+ *                C. Scott Ananian <cananian@alumni.princeton.edu>\n+ *\n+ * $Id: util.h,v 1.6 2005/03/10 01:18:20 quozl Exp $\n+ */\n+\n+#ifndef INC_UTIL_H\n+#define INC_UTIL_H\n+\n+int file2fd(const char *path, const char *mode, int fd);\n+\n+/* signal to pipe delivery implementation */\n+\n+/* create a signal pipe, returns 0 for success, -1 with errno for failure */\n+int sigpipe_create();\n+\n+/* generic handler for signals, writes signal number to pipe */\n+void sigpipe_handler(int signum);\n+\n+/* assign a signal number to the pipe */\n+void sigpipe_assign(int signum);\n+\n+/* return the signal pipe read file descriptor for select(2) */\n+int sigpipe_fd();\n+\n+/* read and return the pending signal from the pipe */\n+int sigpipe_read();\n+\n+void sigpipe_close();\n+\n+#endif /* INC_UTIL_H */\n--- /dev/null\n+++ b/pppd/plugins/pptp/vector.c\n@@ -0,0 +1,209 @@\n+/* vector.c ..... store a vector of PPTP_CALL information and search it\n+ *                efficiently.\n+ *                C. Scott Ananian <cananian@alumni.princeton.edu>\n+ *\n+ * $Id: vector.c,v 1.3 2003/06/17 10:12:55 reink Exp $\n+ */\n+\n+#include <stdlib.h>\n+#include <string.h>\n+#include <assert.h>\n+#include \"pptp_ctrl.h\"\n+#include \"vector.h\"\n+/* #define VECTOR_DEBUG */\n+#ifndef TRUE\n+#define TRUE 1\n+#endif\n+#ifndef FALSE\n+#define FALSE 0\n+#endif\n+\n+struct vector_item {\n+    int key;\n+    PPTP_CALL *call;\n+};\n+\n+struct vector_struct {\n+    struct vector_item *item;\n+    int size;\n+    int alloc;\n+#ifdef VECTOR_DEBUG\n+    int key_max;\n+#endif\n+};\n+\n+static struct vector_item *binary_search(VECTOR *v, int key);\n+\n+/*** vector_create ************************************************************/\n+VECTOR *vector_create()\n+{\n+    const int INITIAL_SIZE = 4;\n+\n+    VECTOR *v = malloc(sizeof(*v));\n+    if (v == NULL) return v;\n+\n+    v->size = 0;\n+    v->alloc = INITIAL_SIZE;\n+    v->item = malloc(sizeof(*(v->item)) * (v->alloc));\n+#ifdef VECTOR_DEBUG\n+    v->key_max = -1;\n+#endif\n+    if (v->item == NULL) { free(v); return NULL; }\n+    else return v;\n+}\n+\n+/*** vector_destroy ***********************************************************/\n+void vector_destroy(VECTOR *v)\n+{\n+    free(v->item);\n+#ifdef VECTOR_DEBUG\n+    v->item = NULL;\n+#endif\n+    free(v);\n+}\n+\n+/*** vector_size **************************************************************/\n+int vector_size(VECTOR *v)\n+{\n+    assert(v != NULL);\n+    return v->size;\n+}\n+\n+/*** vector_insert*************************************************************\n+ * nice thing about file descriptors is that we are assured by POSIX \n+ * that they are monotonically increasing.\n+ */\n+int vector_insert(VECTOR *v, int key, PPTP_CALL * call)\n+{\n+    int i;\n+    assert(v != NULL && call != NULL);\n+    assert(!vector_contains(v, key));\n+#ifdef VECTOR_DEBUG\n+    assert(v->key_max < key);\n+#endif\n+    if (!(v->size < v->alloc)) {\n+        void *tmp = realloc(v->item, sizeof(*(v->item)) * 2 * v->alloc);\n+        if (tmp != NULL) {\n+            v->alloc *= 2;\n+            v->item = tmp;\n+        } else return FALSE; /* failed to alloc memory. */\n+    }\n+    assert(v->size < v->alloc);\n+    /* for safety, we make this work in the general case;\n+     * but this is optimized for adding call to the end of the vector.\n+     */\n+    for(i = v->size - 1; i >= 0; i--)\n+        if (v->item[i].key < key)\n+            break;\n+    /* insert after item i */\n+    memmove(&v->item[i + 2], &v->item[i + 1],\n+            (v->size - i - 1) * sizeof(*(v->item)));\n+    v->item[i + 1].key  = key;\n+    v->item[i + 1].call = call;\n+    v->size++;\n+#ifdef VECTOR_DEBUG\n+    if (v->key_max < key) /* ie, always. */\n+        v->key_max = key;\n+#endif\n+    return TRUE;\n+}\n+\n+/*** vector_remove ************************************************************/\n+int  vector_remove(VECTOR *v, int key)\n+{\n+    struct vector_item *tmp;\n+    assert(v != NULL);\n+    if ((tmp =binary_search(v,key)) == NULL) return FALSE;\n+    assert(tmp >= v->item && tmp < v->item + v->size);\n+    memmove(tmp, tmp + 1, (v->size - (v->item - tmp) - 1) * sizeof(*(v->item)));\n+    v->size--;\n+    return TRUE;\n+}\n+\n+/*** vector_search ************************************************************/\n+int  vector_search(VECTOR *v, int key, PPTP_CALL **call)\n+{\n+    struct vector_item *tmp;\n+    assert(v != NULL);\n+    tmp = binary_search(v, key);\n+    if (tmp ==NULL) return FALSE;\n+    *call = tmp->call;\n+    return TRUE;\n+}\n+\n+/*** vector_contains **********************************************************/\n+int  vector_contains(VECTOR *v, int key)\n+{\n+    assert(v != NULL);\n+    return (binary_search(v, key) != NULL);\n+}\n+\n+/*** vector_item **************************************************************/\n+static struct vector_item *binary_search(VECTOR *v, int key)\n+{\n+    int l,r,x;\n+    l = 0;\n+    r = v->size - 1;\n+    while (r >= l) {\n+        x = (l + r)/2;\n+        if (key <  v->item[x].key) r = x - 1; else l = x + 1;\n+        if (key == v->item[x].key) return &(v->item[x]);\n+    }\n+    return NULL;\n+}\n+\n+/*** vector_scan ***************************************************************\n+ * Hmm.  Let's be fancy and use a binary search for the first\n+ * unused key, taking advantage of the list is stored sorted; ie\n+ * we can look at pointers and keys at two different locations, \n+ * and if (ptr1 - ptr2) = (key1 - key2) then all the slots\n+ * between ptr1 and ptr2 are filled.  Note that ptr1-ptr2 should\n+ * never be greater than key1-key2 (no duplicate keys!)... we\n+ * check for this.\n+ */\n+int vector_scan(VECTOR *v, int lo, int hi, int *key)\n+{\n+    int l,r,x;\n+    assert(v != NULL);\n+    assert(key != NULL);\n+    if ((v->size<1) || (lo < v->item[0].key)) { *key = lo; return TRUE; }\n+    /* our array bounds */\n+    l = 0;  r = v->size - 1;\n+    while (r > l) {\n+        /* check for a free spot right after l */\n+        if (v->item[l].key + 1 < v->item[l + 1].key) { /* found it! */\n+            *key = v->item[l].key + 1;\n+            return TRUE;\n+        }\n+        /* no dice. Let's see if the free spot is before or after the midpoint */\n+        x = (l + r)/2;\n+        /* Okay, we have right (r), left (l) and the probe (x). */\n+        assert(x - l <= v->item[x].key - v->item[l].key);\n+        assert(r - x <= v->item[r].key - v->item[x].key);\n+        if (x - l < v->item[x].key - v->item[l].key)\n+            /* room between l and x */\n+            r = x;\n+        else /* no room between l and x */\n+            if (r - x < v->item[r].key - v->item[x].key)\n+                /* room between x and r */\n+                l = x;\n+            else /* no room between x and r, either */\n+                break; /* game over, man. */\n+    }\n+    /* no room found in already allocated space.  Check to see if\n+     * there's free space above allocated entries. */\n+    if (v->item[v->size - 1].key < hi) {\n+        *key = v->item[v->size - 1].key + 1;\n+        return TRUE;\n+    }\n+    /* outta luck */\n+    return FALSE;\n+}\n+\n+/*** vector_get_Nth ***********************************************************/\n+PPTP_CALL * vector_get_Nth(VECTOR *v, int n)\n+{\n+    assert(v != NULL);\n+    assert(0 <= n && n < vector_size(v));\n+    return v->item[n].call;\n+}\n--- /dev/null\n+++ b/pppd/plugins/pptp/vector.h\n@@ -0,0 +1,31 @@\n+/* vector.h ..... store a vector of PPTP_CALL information and search it\n+ *                efficiently.\n+ *                C. Scott Ananian <cananian@alumni.princeton.edu>\n+ *\n+ * $Id: vector.h,v 1.1.1.1 2000/12/23 08:19:51 scott Exp $\n+ */\n+\n+#ifndef INC_VECTOR_H\n+#define INC_VECTOR_H\n+\n+#include \"pptp_ctrl.h\" /* for definition of PPTP_CALL */\n+\n+typedef struct vector_struct VECTOR;\n+\n+VECTOR *vector_create();\n+void vector_destroy(VECTOR *v);\n+\n+int vector_size(VECTOR *v);\n+\n+/* vector_insert and vector_search return TRUE on success, FALSE on failure. */\n+int  vector_insert(VECTOR *v, int key, PPTP_CALL * call);\n+int  vector_remove(VECTOR *v, int key);\n+int  vector_search(VECTOR *v, int key, PPTP_CALL ** call);\n+/* vector_contains returns FALSE if not found, TRUE if found. */\n+int  vector_contains(VECTOR *v, int key);\n+/* find first unused key. Returns TRUE on success, FALSE if no. */\n+int  vector_scan(VECTOR *v, int lo, int hi, int *key);\n+/* get a specific PPTP_CALL ... useful only when iterating. */\n+PPTP_CALL * vector_get_Nth(VECTOR *v, int n);\n+\n+#endif /* INC_VECTOR_H */\n"
  },
  {
    "path": "package/network/services/ppp/patches/510-pptp_compile_fix.patch",
    "content": "--- a/pppd/plugins/pptp/pptp.c\n+++ b/pppd/plugins/pptp/pptp.c\n@@ -48,7 +48,7 @@\n \n #include \"pptp_callmgr.h\"\n #include <net/if.h>\n-#include <net/ethernet.h>\n+#include <linux/if_ether.h>\n #include <linux/if_pppox.h>\n \n #include <stdio.h>\n"
  },
  {
    "path": "package/network/services/ppp/patches/511-pptp_cflags.patch",
    "content": "--- a/pppd/plugins/pptp/Makefile.linux\n+++ b/pppd/plugins/pptp/Makefile.linux\n@@ -20,7 +20,7 @@ all: pptp.so\n \t$(CC) $(CFLAGS) -c -o $@ $<\n \n pptp.so: dirutil.o orckit_quirks.o pptp.o pptp_callmgr.o pptp_ctrl.o pptp_quirks.o util.o vector.o\n-\t$(CC) -o pptp.so -shared dirutil.o orckit_quirks.o pptp.o pptp_callmgr.o pptp_ctrl.o pptp_quirks.o util.o vector.o\n+\t$(CC) -fPIC -o pptp.so -shared dirutil.o orckit_quirks.o pptp.o pptp_callmgr.o pptp_ctrl.o pptp_quirks.o util.o vector.o\n \n install: all\n \t$(INSTALL) -d -m 755 $(LIBDIR)\n"
  },
  {
    "path": "package/network/services/ppp/patches/600-Revert-pppd-Use-openssl-for-the-DES-instead-of-the-l.patch",
    "content": "From 831dca008699d485f2c8e91749657ef2d0b06166 Mon Sep 17 00:00:00 2001\nFrom: Martin Schiller <ms@dev.tdt.de>\nDate: Thu, 6 Dec 2018 08:43:17 +0100\nSubject: [PATCH] Revert \"pppd: Use openssl for the DES instead of the libcrypt\n / glibc\"\n\nFor musl and glibc2.27 we can keep linking to crypt; however if we\nswitch to glibc 2.28 we will have to link to one of the SSL libraries.\n\nThis reverts commit 3c7b86229f7bd2600d74db14b1fe5b3896be3875.\n---\n pppd/Makefile.linux |  7 +++----\n pppd/pppcrypt.c     | 18 +++++++++---------\n 2 files changed, 12 insertions(+), 13 deletions(-)\n\n--- a/pppd/Makefile.linux\n+++ b/pppd/Makefile.linux\n@@ -36,10 +36,10 @@ endif\n \n LIBS = -lrt\n \n-# Uncomment the next line to include support for Microsoft's\n+# Uncomment the next 2 lines to include support for Microsoft's\n # MS-CHAP authentication protocol.  Also, edit plugins/radius/Makefile.linux.\n CHAPMS=y\n-#USE_CRYPT=y\n+USE_CRYPT=y\n # Don't use MSLANMAN unless you really know what you're doing.\n #MSLANMAN=y\n # Uncomment the next line to include support for MPPE.  CHAPMS (above) must\n@@ -158,8 +158,7 @@ endif\n \n ifdef NEEDDES\n ifndef USE_CRYPT\n-CFLAGS   += -I$(shell $(CC) --print-sysroot)/usr/include/openssl\n-NEEDCRYPTOLIB = y\n+LIBS     += -ldes $(LIBS)\n else\n CFLAGS   += -DUSE_CRYPT=1\n endif\n--- a/pppd/pppcrypt.c\n+++ b/pppd/pppcrypt.c\n@@ -62,7 +62,7 @@ MakeKey(u_char *key, u_char *des_key)\n \tdes_key[7] = Get7Bits(key, 49);\n \n #ifndef USE_CRYPT\n-\tDES_set_odd_parity((DES_cblock *)des_key);\n+\tdes_set_odd_parity((des_cblock *)des_key);\n #endif\n }\n \n@@ -147,30 +147,30 @@ DesDecrypt(u_char *cipher, u_char *clear\n }\n \n #else /* USE_CRYPT */\n-static DES_key_schedule\tkey_schedule;\n+static des_key_schedule\tkey_schedule;\n \n bool\n DesSetkey(u_char *key)\n {\n-\tDES_cblock des_key;\n+\tdes_cblock des_key;\n \tMakeKey(key, des_key);\n-\tDES_set_key(&des_key, &key_schedule);\n+\tdes_set_key(&des_key, key_schedule);\n \treturn (1);\n }\n \n bool\n DesEncrypt(u_char *clear, u_char *cipher)\n {\n-\tDES_ecb_encrypt((DES_cblock *)clear, (DES_cblock *)cipher,\n-\t    &key_schedule, 1);\n+\tdes_ecb_encrypt((des_cblock *)clear, (des_cblock *)cipher,\n+\t    key_schedule, 1);\n \treturn (1);\n }\n \n bool\n DesDecrypt(u_char *cipher, u_char *clear)\n {\n-\tDES_ecb_encrypt((DES_cblock *)cipher, (DES_cblock *)clear,\n-\t    &key_schedule, 0);\n+\tdes_ecb_encrypt((des_cblock *)cipher, (des_cblock *)clear,\n+\t    key_schedule, 0);\n \treturn (1);\n }\n \n"
  },
  {
    "path": "package/network/services/ppp/patches/610-pppd_compile_fix.patch",
    "content": "--- a/pppd/Makefile.linux\n+++ b/pppd/Makefile.linux\n@@ -49,7 +49,8 @@ MPPE=y\n # Uncomment the next line to include support for PPP packet filtering.\n # This requires that the libpcap library and headers be installed\n # and that the kernel driver support PPP packet filtering.\n-#FILTER=y\n+# libpcap statically linked in OpenWRT, hence disabled here.\n+FILTER=\n \n # Support for precompiled filters\n PRECOMPILED_FILTER=y\n"
  },
  {
    "path": "package/network/services/ppp/utils/pfc.c",
    "content": "/* \n * Taken from fli4l 3.0\n * Make sure you compile it against the same libpcap version used in OpenWrt\n */\n\n#include <stdlib.h>\n#include <sys/types.h>\n#include <sys/time.h>\n#include <string.h>\n\n#include <linux/types.h>\n#include <linux/ppp_defs.h>\n\n#include <pcap.h>\n#include <pcap-bpf.h>\n\nint main (int argc, char ** argv)\n{\n    pcap_t  *pc; /* Fake struct pcap so we can compile expr */\n    struct  bpf_program filter; /* Filter program for link-active pkts */\n    u_int32_t netmask=0;\n\n    int dflag = 3;\n    if (argc == 4)\n    {\n\tif (!strcmp (argv[1], \"-d\"))\n\t{\n\t    dflag = atoi (argv[2]);\n\t    argv += 2;\n\t    argc -=2;\n\t}\n    }\n    if (argc != 2)\n    {\n\tprintf (\"usage; %s [ -d <debug_level> ] expression\\n\", argv[0]);\n\treturn 1;\n    }\n\n    pc = pcap_open_dead(DLT_PPP_PPPD, PPP_HDRLEN);\n    if (pcap_compile(pc, &filter, argv[1], 1, netmask) == 0)\n    {\n\tprintf (\"#\\n# Expression: %s\\n#\\n\", argv[1]);\n\tbpf_dump (&filter, dflag);\n\treturn 0;\n    }\n    else\n    {\n\tprintf(\"error in active-filter expression: %s\\n\", pcap_geterr(pc));\n    }\n    return 1;\n}\n"
  },
  {
    "path": "package/network/services/relayd/Makefile",
    "content": "#\n# Copyright (C) 2010-2011 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=relayd\nPKG_RELEASE:=1\n\nPKG_SOURCE_URL=$(PROJECT_GIT)/project/relayd.git\nPKG_SOURCE_PROTO:=git\nPKG_SOURCE_DATE:=2020-04-25\nPKG_SOURCE_VERSION:=f4d759be54ceb37714e9a6ca320d5b50c95e9ce9\nPKG_MIRROR_HASH:=b1ff6e99072867be0975ba0be52ba9da3a876c8b8da893d68301e8238243a51e\n\nPKG_MAINTAINER:=Felix Fietkau <nbd@nbd.name>\nPKG_LICENSE:=GPL-2.0\n\ninclude $(INCLUDE_DIR)/package.mk\ninclude $(INCLUDE_DIR)/cmake.mk\n\ndefine Package/relayd\n  SECTION:=net\n  CATEGORY:=Network\n  SUBMENU:=Routing and Redirection\n  TITLE:=Transparent routing / relay daemon\n  DEPENDS:=+libubox\nendef\n\nTARGET_CFLAGS += -I$(STAGING_DIR)/usr/include\n\ndefine Package/relayd/install\n\t$(INSTALL_DIR) $(1)/usr/sbin\n\t$(INSTALL_BIN) $(PKG_BUILD_DIR)/relayd $(1)/usr/sbin/relayd\n\t$(INSTALL_DIR) $(1)/etc/init.d\n\t$(INSTALL_BIN) ./files/relay.init $(1)/etc/init.d/relayd\nendef\n\n$(eval $(call BuildPackage,relayd))\n"
  },
  {
    "path": "package/network/services/relayd/files/relay.init",
    "content": "#!/bin/sh /etc/rc.common\n# Copyright (c) 2011-2012 OpenWrt.org\n\nSTART=80\n\nUSE_PROCD=1\nPROG=/usr/sbin/relayd\n\nvalidate_proto_relayd()\n{\n\tuci_validate_section network \"interface\" \"${1}\" \\\n\t\t'network:list(string)' \\\n\t\t'expiry:uinteger:30' \\\n\t\t'retry:uinteger:5' \\\n\t\t'table:range(0, 65535):16800' \\\n\t\t'forward_bcast:bool:1' \\\n\t\t'forward_dhcp:bool:1'\n}\n\nresolve_ifname() {\n\tgrep -qs \"^ *$1:\" /proc/net/dev && {\n\t\tappend resolved_ifnames \"$1\"\n\t}\n}\n\nresolve_network() {\n\tlocal ifn\n\tfixup_interface \"$1\"\n\tconfig_get ifn \"$1\" ifname\n\t[ -z \"$ifn\" ] && return 1\n\tresolve_ifname \"$ifn\"\n}\n\nstart_relay() {\n\tlocal cfg=\"$1\"\n\tlocal proto disabled\n\n\tconfig_get proto \"$cfg\" proto\n\t[ \"$proto\" = \"relay\" ] || return 0\n\n\tconfig_get_bool disabled \"$cfg\" disabled 0\n\t[ \"$disabled\" -gt 0 ] && return 0\n\n\tlocal resolved_ifnames\n\tlocal net networks\n\tconfig_get networks \"$cfg\" network\n\tfor net in $networks; do\n\t\tresolve_network \"$net\" || {\n\t\t\treturn 1\n\t\t}\n\tdone\n\n\tlocal ifn ifnames\n\tconfig_get ifnames \"$cfg\" ifname\n\tfor ifn in $ifnames; do\n\t\tresolve_ifname \"$ifn\" || {\n\t\t\treturn 1\n\t\t}\n\tdone\n\n\tprocd_open_instance\n\tprocd_set_param command \"$PROG\"\n\n\tfor ifn in $resolved_ifnames; do\n\t\tprocd_append_param command -I \"$ifn\"\n\t\tprocd_append_param netdev \"$ifn\"\n\tdone\n\tlocal ipaddr\n\tconfig_get ipaddr \"$cfg\" ipaddr\n\t[ -n \"$ipaddr\" ] && procd_append_param command -L \"$ipaddr\"\n\n\tlocal gateway\n\tconfig_get gateway \"$cfg\" gateway\n\t[ -n \"$gateway\" ] && procd_append_param command -G \"$gateway\"\n\n\tlocal expiry # = 30\n\tconfig_get expiry \"$cfg\" expiry\n\t[ -n \"$expiry\" ] && procd_append_param command -t \"$expiry\"\n\n\tlocal retry # = 5\n\tconfig_get retry \"$cfg\" retry\n\t[ -n \"$retry\" ] && procd_append_param command -p \"$retry\"\n\n\tlocal table # = 16800\n\tconfig_get table \"$cfg\" table\n\t[ -n \"$table\" ] && procd_append_param command -T \"$table\"\n\n\tlocal fwd_bcast # = 1\n\tconfig_get_bool fwd_bcast \"$cfg\" forward_bcast 1\n\t[ $fwd_bcast -eq 1 ] && procd_append_param command \"-B\"\n\n\tlocal fwd_dhcp # = 1\n\tconfig_get_bool fwd_dhcp \"$cfg\" forward_dhcp 1\n\t[ $fwd_dhcp -eq 1 ] && procd_append_param command \"-D\"\n\n\tprocd_close_instance\n}\n\nservice_triggers()\n{\n\tprocd_add_reload_trigger \"network\"\n\tprocd_add_raw_trigger \"interface.*\" 2000 /etc/init.d/relayd reload\n}\n\nstart_service() {\n\tinclude /lib/network\n\tconfig_load network\n\tconfig_foreach start_relay interface\n}\n"
  },
  {
    "path": "package/network/services/uhttpd/Makefile",
    "content": "#\n# Copyright (C) 2010-2015 Jo-Philipp Wich <jo@mein.io>\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=uhttpd\nPKG_RELEASE:=1\n\nPKG_SOURCE_PROTO:=git\nPKG_SOURCE_URL=$(PROJECT_GIT)/project/uhttpd.git\nPKG_SOURCE_DATE:=2022-02-07\nPKG_SOURCE_VERSION:=2f8b1360df25bab375ec60bbba2dce8dd796161c\nPKG_MIRROR_HASH:=fe9c57492e4da493e9955994d1af6cf0086305633fa8febef7ab6df10c4798fa\nPKG_MAINTAINER:=Felix Fietkau <nbd@nbd.name>\nPKG_LICENSE:=ISC\n\nPKG_ASLR_PIE_REGULAR:=1\nPKG_BUILD_DEPENDS = ustream-ssl\nPKG_CONFIG_DEPENDS:= CONFIG_uhttpd_lua CONFIG_uhttpd_ucode\n\ninclude $(INCLUDE_DIR)/package.mk\ninclude $(INCLUDE_DIR)/cmake.mk\ninclude $(INCLUDE_DIR)/version.mk\n\ndefine Package/uhttpd/default\n  SECTION:=net\n  CATEGORY:=Network\n  SUBMENU:=Web Servers/Proxies\n  TITLE:=uHTTPd - tiny, single threaded HTTP server\nendef\n\ndefine Package/uhttpd\n  $(Package/uhttpd/default)\n  DEPENDS:=+libubox +libblobmsg-json +libjson-script +libjson-c\nendef\n\ndefine Package/uhttpd/description\n uHTTPd is a tiny single threaded HTTP server with TLS, CGI and Lua\n support. It is intended as a drop-in replacement for the Busybox\n HTTP daemon.\nendef\n\ndefine Package/uhttpd/config\n  config uhttpd_lua\n    depends on PACKAGE_uhttpd-mod-lua\n    bool \"Enable Integrated Lua interpreter\"\n\tdefault y\n\n  config uhttpd_ucode\n    depends on PACKAGE_uhttpd-mod-ucode\n    bool \"Enable Integrated ucode interpreter\"\n\tdefault y\nendef\n\ndefine Package/uhttpd/conffiles\n/etc/config/uhttpd\n/etc/uhttpd.crt\n/etc/uhttpd.key\nendef\n\n\ndefine Package/uhttpd-mod-lua\n  $(Package/uhttpd/default)\n  TITLE+= (Lua plugin)\n  DEPENDS:=uhttpd +liblua\nendef\n\ndefine Package/uhttpd-mod-lua/description\n The Lua plugin adds a CGI-like Lua runtime interface to uHTTPd.\nendef\n\n\ndefine Package/uhttpd-mod-ubus\n  $(Package/uhttpd/default)\n  TITLE+= (ubus plugin)\n  DEPENDS:=uhttpd +libubus +libblobmsg-json\nendef\n\ndefine Package/uhttpd-mod-ubus/description\n The ubus plugin adds a HTTP/JSON RPC proxy for ubus and publishes the\n session.* namespace and procedures.\nendef\n\n\ndefine Package/uhttpd-mod-ucode\n  $(Package/uhttpd/default)\n  TITLE+= (ucode plugin)\n  DEPENDS:=uhttpd +libucode\nendef\n\ndefine Package/uhttpd-mod-ucode/description\n The ucode plugin adds a CGI-like ucode runtime interface to uHTTPd.\nendef\n\n\nifneq ($(CONFIG_USE_GLIBC),)\n  TARGET_CFLAGS += -D_DEFAULT_SOURCE\nendif\n\nTARGET_LDFLAGS += -lcrypt\n\nCMAKE_OPTIONS += -DTLS_SUPPORT=on\n\ndefine Package/uhttpd/install\n\t$(INSTALL_DIR) $(1)/etc/init.d\n\t$(INSTALL_BIN) ./files/uhttpd.init $(1)/etc/init.d/uhttpd\n\t$(INSTALL_DIR) $(1)/etc/config\n\t$(INSTALL_CONF) ./files/uhttpd.config $(1)/etc/config/uhttpd\n\t$(VERSION_SED_SCRIPT) $(1)/etc/config/uhttpd\n\t$(INSTALL_DIR) $(1)/usr/sbin\n\t$(INSTALL_BIN) $(PKG_BUILD_DIR)/uhttpd $(1)/usr/sbin/uhttpd\nendef\n\ndefine Package/uhttpd-mod-lua/install\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(INSTALL_BIN) $(PKG_BUILD_DIR)/uhttpd_lua.so $(1)/usr/lib/\nendef\n\ndefine Package/uhttpd-mod-ubus/install\n\t$(INSTALL_DIR) $(1)/usr/lib $(1)/etc/uci-defaults\n\t$(INSTALL_BIN) $(PKG_BUILD_DIR)/uhttpd_ubus.so $(1)/usr/lib/\n\t$(INSTALL_DATA) ./files/ubus.default $(1)/etc/uci-defaults/00_uhttpd_ubus\nendef\n\ndefine Package/uhttpd-mod-ucode/install\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(INSTALL_BIN) $(PKG_BUILD_DIR)/uhttpd_ucode.so $(1)/usr/lib/\nendef\n\n\n$(eval $(call BuildPackage,uhttpd))\n$(eval $(call BuildPackage,uhttpd-mod-lua))\n$(eval $(call BuildPackage,uhttpd-mod-ubus))\n$(eval $(call BuildPackage,uhttpd-mod-ucode))\n"
  },
  {
    "path": "package/network/services/uhttpd/files/ubus.default",
    "content": "#!/bin/sh\n\ncommit=0\n\nif [ -z \"$(uci -q get uhttpd.main.ubus_prefix)\" ]; then\n\tuci set uhttpd.main.ubus_prefix=/ubus\n\tcommit=1\nfi\n\n[ \"$(uci -q get uhttpd.main.ubus_socket)\" = \"/var/run/ubus.sock\" ] && {\n\tuci set uhttpd.main.ubus_socket='/var/run/ubus/ubus.sock'\n\tcommit=1\n}\n\n[ \"$commit\" = 1 ] && uci commit uhttpd && /etc/init.d/uhttpd reload\n\nexit 0\n"
  },
  {
    "path": "package/network/services/uhttpd/files/uhttpd.config",
    "content": "# Server configuration\nconfig uhttpd main\n\n\t# HTTP listen addresses, multiple allowed\n\tlist listen_http\t0.0.0.0:80\n\tlist listen_http\t[::]:80\n\n\t# HTTPS listen addresses, multiple allowed\n\tlist listen_https\t0.0.0.0:443\n\tlist listen_https\t[::]:443\n\n\t# Redirect HTTP requests to HTTPS if possible\n\toption redirect_https\t0\n\n\t# Server document root\n\toption home\t\t/www\n\n\t# Reject requests from RFC1918 IP addresses\n\t# directed to the servers public IP(s).\n\t# This is a DNS rebinding countermeasure.\n\toption rfc1918_filter 1\n\n\t# Maximum number of concurrent requests.\n\t# If this number is exceeded, further requests are\n\t# queued until the number of running requests drops\n\t# below the limit again.\n\toption max_requests 3\n\n\t# Maximum number of concurrent connections.\n\t# If this number is exceeded, further TCP connection\n\t# attempts are queued until the number of active\n\t# connections drops below the limit again.\n\toption max_connections 100\n\n\t# Certificate and private key for HTTPS.\n\t# If no listen_https addresses are given,\n\t# the key options are ignored.\n\toption cert\t\t/etc/uhttpd.crt\n\toption key\t\t/etc/uhttpd.key\n\n\t# CGI url prefix, will be searched in docroot.\n\t# Default is /cgi-bin\n\toption cgi_prefix\t/cgi-bin\n\n\t# List of extension->interpreter mappings.\n\t# Files with an associated interpreter can\n\t# be called outside of the CGI prefix and do\n\t# not need to be executable.\n#\tlist interpreter\t\".php=/usr/bin/php-cgi\"\n#\tlist interpreter\t\".cgi=/usr/bin/perl\"\n\n\t# List of prefix->Lua handler mappings.\n\t# Any request to an URL beneath the prefix\n\t# will be dispatched to the associated Lua\n\t# handler script. Lua support is disabled when\n\t# no handler mappings are specified. Lua prefix\n\t# matches have precedence over the CGI prefix.\n\tlist lua_prefix\t\t\"/cgi-bin/luci=/usr/lib/lua/luci/sgi/uhttpd.lua\"\n\n\t# List of prefix->ucode handler mappings.\n\t# Any request to an URL beneath the prefix\n\t# will be dispatched to the associated ucode\n\t# handler script. Ucode support is disabled when\n\t# no handler mappings are specified. Ucode prefix\n\t# matches have precedence over the CGI prefix.\n#\tlist ucode_prefix\t\t\"/ucode/example=/usr/share/example.uc\"\n\n\t# Specify the ubus-rpc prefix and socket path.\n#\toption ubus_prefix\t/ubus\n#\toption ubus_socket\t/var/run/ubus/ubus.sock\n\n\t# CGI/Lua timeout, if the called script does not\n\t# write data within the given amount of seconds,\n\t# the server will terminate the request with\n\t# 504 Gateway Timeout response.\n\toption script_timeout\t60\n\n\t# Network timeout, if the current connection is\n\t# blocked for the specified amount of seconds,\n\t# the server will terminate the associated\n\t# request process.\n\toption network_timeout\t30\n\n\t# HTTP Keep-Alive, specifies the timeout for persistent\n\t# HTTP/1.1 connections. Setting this to 0 will disable\n\t# persistent HTTP connections.\n\toption http_keepalive\t20\n\n\t# TCP Keep-Alive, send periodic keep-alive probes\n\t# over established connections to detect dead peers.\n\t# The value is given in seconds to specify the\n\t# interval between subsequent probes.\n\t# Setting this to 0 will disable TCP keep-alive.\n\toption tcp_keepalive\t1\n\n\t# Basic auth realm, defaults to local hostname\n#\toption realm\tOpenWrt\n\n\t# Configuration file in busybox httpd format\n#\toption config\t/etc/httpd.conf\n\n\t# Do not follow symlinks that point outside of the\n\t# home directory.\n#\toption no_symlinks\t0\n\n\t# Do not produce directory listings but send 403\n\t# instead if a client requests an url pointing to\n\t# a directory without any index file.\n#\toption no_dirlists\t0\n\n\t# Do not authenticate any ubus-rpc requests against\n\t# the ubus session/access procedure.\n\t# This is dangerous and should be always left off\n\t# except for development and debug purposes!\n#\toption no_ubusauth\t0\n\n\t# For this instance of uhttpd use the listed httpauth\n\t# sections to require Basic auth to the specified\n\t# resources.\n#\tlist httpauth prefix_user\n\n\n# Defaults for automatic certificate and key generation\nconfig cert defaults\n\n\t# Validity time\n\toption days\t\t730\n\n\t# key type: rsa or ec\n\toption key_type\t\tec\n\n\t# RSA key size\n\toption bits\t\t2048\n\n\t# EC curve name\n\t# Curve names vary between px5g-{wolfssl,mbedtls} and openssl\n\t# P-256 or P-384 are guaranteed to work\n\toption ec_curve\t\tP-256\n\n\t# Location\n\toption country\t\tZZ\n\toption state\t\tSomewhere\n\toption location\t\tUnknown\n\n\t# Common name\n\toption commonname\t'%D'\n\n# config httpauth prefix_user\n#\toption prefix /protected/url/path\n#\toption username user\n#\toption password 'plaintext_or_md5_or_$p$user_for_system_user'\n"
  },
  {
    "path": "package/network/services/uhttpd/files/uhttpd.init",
    "content": "#!/bin/sh /etc/rc.common\n# Copyright (C) 2010 Jo-Philipp Wich\n\nSTART=50\n\nUSE_PROCD=1\n\nUHTTPD_BIN=\"/usr/sbin/uhttpd\"\nPX5G_BIN=\"/usr/sbin/px5g\"\nOPENSSL_BIN=\"/usr/bin/openssl\"\n\nappend_arg() {\n\tlocal cfg=\"$1\"\n\tlocal var=\"$2\"\n\tlocal opt=\"$3\"\n\tlocal def=\"$4\"\n\tlocal val\n\n\tconfig_get val \"$cfg\" \"$var\"\n\t[ -n \"$val\" -o -n \"$def\" ] && procd_append_param command \"$opt\" \"${val:-$def}\"\n}\n\nappend_bool() {\n\tlocal cfg=\"$1\"\n\tlocal var=\"$2\"\n\tlocal opt=\"$3\"\n\tlocal def=\"$4\"\n\tlocal val\n\n\tconfig_get_bool val \"$cfg\" \"$var\" \"$def\"\n\t[ \"$val\" = 1 ] && procd_append_param command \"$opt\"\n}\n\ngenerate_keys() {\n\tlocal cfg=\"$1\"\n\tlocal key=\"$2\"\n\tlocal crt=\"$3\"\n\tlocal days bits country state location organization commonname\n\n\tconfig_get days       \"$cfg\" days\n\tconfig_get bits       \"$cfg\" bits\n\tconfig_get country    \"$cfg\" country\n\tconfig_get state      \"$cfg\" state\n\tconfig_get location   \"$cfg\" location\n\tconfig_get organization \"$cfg\" organization\n\tconfig_get commonname \"$cfg\" commonname\n\tconfig_get key_type   \"$cfg\" key_type\n\tconfig_get ec_curve   \"$cfg\" ec_curve\n\n\t# Prefer px5g for certificate generation (existence evaluated last)\n\tlocal GENKEY_CMD=\"\"\n\tlocal KEY_OPTS=\"rsa:${bits:-2048}\"\n\tlocal UNIQUEID=$(dd if=/dev/urandom bs=1 count=4 | hexdump -e '1/1 \"%02x\"')\n\t[ \"$key_type\" = \"ec\" ] && KEY_OPTS=\"ec -pkeyopt ec_paramgen_curve:${ec_curve:-P-256}\"\n\t[ -x \"$OPENSSL_BIN\" ] && GENKEY_CMD=\"$OPENSSL_BIN req -x509 -sha256 -outform der -nodes\"\n\t[ -x \"$PX5G_BIN\" ] && GENKEY_CMD=\"$PX5G_BIN selfsigned -der\"\n\t[ -n \"$GENKEY_CMD\" ] && {\n\t\t$GENKEY_CMD \\\n\t\t\t-days ${days:-730} -newkey ${KEY_OPTS} -keyout \"${UHTTPD_KEY}.new\" -out \"${UHTTPD_CERT}.new\" \\\n\t\t\t-subj /C=\"${country:-ZZ}\"/ST=\"${state:-Somewhere}\"/L=\"${location:-Unknown}\"/O=\"${organization:-OpenWrt$UNIQUEID}\"/CN=\"${commonname:-OpenWrt}\"\n\t\tsync\n\t\tmv \"${UHTTPD_KEY}.new\" \"${UHTTPD_KEY}\"\n\t\tmv \"${UHTTPD_CERT}.new\" \"${UHTTPD_CERT}\"\n\t}\n}\n\ncreate_httpauth() {\n\tlocal cfg=\"$1\"\n\tlocal prefix username password\n\n\tconfig_get prefix \"$cfg\" prefix\n\tconfig_get username \"$cfg\" username\n\tconfig_get password \"$cfg\" password\n\n\tif [ -z \"$prefix\" ] || [ -z \"$username\" ] || [ -z \"$password\" ]; then\n\t\treturn\n\tfi\n\techo \"${prefix}:${username}:${password}\" >>$httpdconf\n\thaveauth=1\n}\n\nappend_lua_prefix() {\n\tlocal v=\"$1\"\n\tlocal prefix=\"${v%%=*}\"\n\tlocal handler=\"${v#*=}\"\n\n\tif [ \"$prefix\" != \"$handler\" ] && [ -n \"$prefix\" ] && [ -f \"$handler\" ]; then\n\t\tprocd_append_param command -l \"$prefix\" -L \"$handler\"\n\telse\n\t\techo \"Skipping invalid Lua prefix \\\"$v\\\"\" >&2\n\tfi\n}\n\nappend_ucode_prefix() {\n\tlocal v=\"$1\"\n\tlocal prefix=\"${v%%=*}\"\n\tlocal handler=\"${v#*=}\"\n\n\tif [ \"$prefix\" != \"$handler\" ] && [ -n \"$prefix\" ] && [ -f \"$handler\" ]; then\n\t\tprocd_append_param command -o \"$prefix\" -O \"$handler\"\n\telse\n\t\techo \"Skipping invalid ucode prefix \\\"$v\\\"\" >&2\n\tfi\n}\n\nstart_instance()\n{\n\tUHTTPD_CERT=\"\"\n\tUHTTPD_KEY=\"\"\n\n\tlocal cfg=\"$1\"\n\tlocal realm=\"$(uci_get system.@system[0].hostname)\"\n\tlocal listen http https interpreter indexes path handler httpdconf haveauth\n\tlocal enabled\n\n\tconfig_get_bool enabled \"$cfg\" 'enabled' 1\n\t[ $enabled -gt 0 ] || return\n\n\tprocd_open_instance\n\tprocd_set_param respawn\n\tprocd_set_param stderr 1\n\tprocd_set_param command \"$UHTTPD_BIN\" -f\n\n\tconfig_get config \"$cfg\" config\n\tif [ -z \"$config\" ]; then\n\t\tmkdir -p /var/etc/uhttpd\n\t\thttpdconf=\"/var/etc/uhttpd/httpd.${cfg}.conf\"\n\t\trm -f ${httpdconf}\n\t\tconfig_list_foreach \"$cfg\" httpauth create_httpauth\n\t\tif [ \"$haveauth\" = \"1\" ]; then\n\t\t\tprocd_append_param command -c ${httpdconf}\n\t\t\t[ -r /etc/httpd.conf ] && cat /etc/httpd.conf >>/var/etc/uhttpd/httpd.${cfg}.conf\n\t\tfi\n\tfi\n\n\tappend_arg \"$cfg\" home \"-h\"\n\tappend_arg \"$cfg\" realm \"-r\" \"${realm:-OpenWrt}\"\n\tappend_arg \"$cfg\" config \"-c\"\n\tappend_arg \"$cfg\" cgi_prefix \"-x\"\n\t[ -f /usr/lib/uhttpd_lua.so ] && {\n\t\tlocal len\n\t\tconfig_get len \"$cfg\" lua_prefix_LENGTH\n\n\t\tif [ -n \"$len\" ]; then\n\t\t\tconfig_list_foreach \"$cfg\" lua_prefix append_lua_prefix\n\t\telse\n\t\t\tconfig_get prefix \"$cfg\" lua_prefix\n\t\t\tconfig_get handler \"$cfg\" lua_handler\n\t\t\tappend_lua_prefix \"$prefix=$handler\"\n\t\tfi\n\t}\n\t[ -f /usr/lib/uhttpd_ubus.so ] && {\n\t\tappend_arg \"$cfg\" ubus_prefix \"-u\"\n\t\tappend_arg \"$cfg\" ubus_socket \"-U\"\n\t\tappend_bool \"$cfg\" ubus_cors \"-X\" 0\n\t}\n\t[ -f /usr/lib/uhttpd_ucode.so ] && {\n\t\tconfig_list_foreach \"$cfg\" ucode_prefix append_ucode_prefix\n\t}\n\tappend_arg \"$cfg\" script_timeout \"-t\"\n\tappend_arg \"$cfg\" network_timeout \"-T\"\n\tappend_arg \"$cfg\" http_keepalive \"-k\"\n\tappend_arg \"$cfg\" tcp_keepalive \"-A\"\n\tappend_arg \"$cfg\" error_page \"-E\"\n\tappend_arg \"$cfg\" max_requests \"-n\" 3\n\tappend_arg \"$cfg\" max_connections \"-N\"\n\n\tappend_bool \"$cfg\" no_ubusauth \"-a\" 0\n\tappend_bool \"$cfg\" no_symlinks \"-S\" 0\n\tappend_bool \"$cfg\" no_dirlists \"-D\" 0\n\tappend_bool \"$cfg\" rfc1918_filter \"-R\" 0\n\n\tconfig_get alias_list \"$cfg\" alias\n\tfor alias in $alias_list; do\n\t\t procd_append_param command -y \"$alias\"\n\tdone\n\n\tconfig_get http \"$cfg\" listen_http\n\tfor listen in $http; do\n\t\t procd_append_param command -p \"$listen\"\n\tdone\n\n\tconfig_get interpreter \"$cfg\" interpreter\n\tfor path in $interpreter; do\n\t\tprocd_append_param command -i \"$path\"\n\tdone\n\n\tconfig_get indexes \"$cfg\" index_page\n\tfor path in $indexes; do\n\t\tprocd_append_param command -I \"$path\"\n\tdone\n\n\tconfig_get https \"$cfg\" listen_https\n\tconfig_get UHTTPD_KEY  \"$cfg\" key  /etc/uhttpd.key\n\tconfig_get UHTTPD_CERT \"$cfg\" cert /etc/uhttpd.crt\n\n\t[ -f /lib/libustream-ssl.so ] && [ -n \"$https\" ] && {\n\t\t[ -s \"$UHTTPD_CERT\" -a -s \"$UHTTPD_KEY\" ] || {\n\t\t\tconfig_foreach generate_keys cert\n\t\t}\n\n\t\t[ -f \"$UHTTPD_CERT\" -a -f \"$UHTTPD_KEY\" ] && {\n\t\t\tappend_arg \"$cfg\" cert \"-C\"\n\t\t\tappend_arg \"$cfg\" key  \"-K\"\n\n\t\t\tfor listen in $https; do\n\t\t\t\tprocd_append_param command -s \"$listen\"\n\t\t\tdone\n\t\t}\n\n\t\tappend_bool \"$cfg\" redirect_https \"-q\" 0\n\t}\n\n\tconfig_get json_script \"$cfg\" json_script\n\tfor file in $json_script; do\n\t\t[ -s \"$file\" ] && procd_append_param command -H \"$file\"\n\tdone\n\n\tprocd_close_instance\n}\n\nservice_triggers()\n{\n\tprocd_add_reload_trigger \"uhttpd\"\n}\n\nstart_service() {\n\tconfig_load uhttpd\n\tconfig_foreach start_instance uhttpd\n}\n"
  },
  {
    "path": "package/network/services/umdns/Makefile",
    "content": "#\n# Copyright (C) 2014-2021 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=umdns\nPKG_RELEASE:=$(AUTORELEASE)\n\nPKG_SOURCE_URL=$(PROJECT_GIT)/project/mdnsd.git\nPKG_SOURCE_PROTO:=git\nPKG_SOURCE_DATE:=2021-05-13\nPKG_SOURCE_VERSION:=b777a0b53f7d89ab2a60e3eed7d98036806da9a4\nPKG_MIRROR_HASH:=54992acf7edd32610de7bcb0ea7c58b20f69bf1ac20be69e76abcff41f25e775\n\nPKG_MAINTAINER:=John Crispin <john@phrozen.org>\nPKG_LICENSE:=LGPL-2.1\n\ninclude $(INCLUDE_DIR)/package-seccomp.mk\ninclude $(INCLUDE_DIR)/package.mk\ninclude $(INCLUDE_DIR)/cmake.mk\n\ndefine Package/umdns\n  SECTION:=net\n  CATEGORY:=Network\n  TITLE:=OpenWrt Multicast DNS Daemon\n  DEPENDS:=+libubox +libubus +libblobmsg-json\nendef\n\nTARGET_CFLAGS += -I$(STAGING_DIR)/usr/include\n\ndefine Package/umdns/conffiles\n/etc/config/umdns\nendef\n\ndefine Package/umdns/install\n\t$(INSTALL_DIR) $(1)/usr/sbin $(1)/etc/init.d $(1)/etc/config\n\t$(INSTALL_BIN) $(PKG_BUILD_DIR)/umdns $(1)/usr/sbin/\n\t$(INSTALL_BIN) ./files/umdns.init $(1)/etc/init.d/umdns\n\t$(INSTALL_CONF) ./files/umdns.config $(1)/etc/config/umdns\n\t$(call InstallSeccomp,$(1),./files/umdns.json)\nendef\n\n$(eval $(call BuildPackage,umdns))\n"
  },
  {
    "path": "package/network/services/umdns/files/umdns.config",
    "content": "config umdns\n\toption jail 1\n\tlist network lan\n"
  },
  {
    "path": "package/network/services/umdns/files/umdns.init",
    "content": "#!/bin/sh /etc/rc.common\n# Copyright (c) 2014 OpenWrt.org\n\nSTART=80\n\nUSE_PROCD=1\nPROG=/usr/sbin/umdns\nIFACES=\"\"\n\nload_ifaces() {\n\tlocal network=\"$(uci get umdns.@umdns[-1].network)\"\n\tfor n in $network; do\n\t\tlocal device\n\t\tjson_load \"$(ifstatus $n)\"\n\t\tjson_get_var device l3_device\n\t\techo -n \"$device \"\n\tdone\n}\n\nreload_service() {\n\tjson_init\n\tjson_add_array interfaces\n\tfor i in $(load_ifaces); do\n\t\tjson_add_string \"\" \"$i\"\n\tdone\n\tjson_close_array\n\n\tubus call umdns set_config \"$(json_dump)\"\n}\n\nstart_service() {\n\tlocal network=\"$(uci get umdns.@umdns[-1].network)\"\n\n\tprocd_open_instance\n\tprocd_set_param command \"$PROG\"\n\t[ -f /etc/seccomp/umdns.json ] && procd_set_param seccomp /etc/seccomp/umdns.json\n\tprocd_set_param respawn\n\tprocd_open_trigger\n\tprocd_add_config_trigger \"config.change\" \"umdns\" /etc/init.d/umdns reload\n\tfor n in $network; do\n\t\tprocd_add_interface_trigger \"interface.*\" $n /etc/init.d/umdns reload\n\tdone\n\tprocd_add_raw_trigger \"instance.update\" 5000 \"/bin/ubus\" \"call\" \"umdns\" \"reload\"\n\tprocd_close_trigger\n\t[ \"$(uci get umdns.@umdns[-1].jail)\" = 1 ] && procd_add_jail umdns ubus log\n\tprocd_close_instance\n}\n\nservice_started() {\n\tubus -t 10 wait_for umdns\n\t[ $? = 0 ] && reload_service\n}\n"
  },
  {
    "path": "package/network/services/umdns/files/umdns.json",
    "content": "{\n\t\"defaultAction\": \"SCMP_ACT_KILL_PROCESS\",\n\t\"syscalls\": [\n\t\t{\n\t\t\t\"names\": [\n\t\t\t\t\"bind\",\n\t\t\t\t\"brk\",\n\t\t\t\t\"clock_gettime\",\n\t\t\t\t\"clock_gettime64\",\n\t\t\t\t\"close\",\n\t\t\t\t\"connect\",\n\t\t\t\t\"epoll_create\",\n\t\t\t\t\"epoll_create1\",\n\t\t\t\t\"epoll_ctl\",\n\t\t\t\t\"epoll_pwait\",\n\t\t\t\t\"epoll_wait\",\n\t\t\t\t\"exit\",\n\t\t\t\t\"exit_group\",\n\t\t\t\t\"fcntl\",\n\t\t\t\t\"fcntl64\",\n\t\t\t\t\"fstat\",\n\t\t\t\t\"getsockname\",\n\t\t\t\t\"ioctl\",\n\t\t\t\t\"madvise\",\n\t\t\t\t\"mmap\",\n\t\t\t\t\"mmap2\",\n\t\t\t\t\"munmap\",\n\t\t\t\t\"open\",\n\t\t\t\t\"openat\",\n\t\t\t\t\"pipe\",\n\t\t\t\t\"pipe2\",\n\t\t\t\t\"poll\",\n\t\t\t\t\"ppoll\",\n\t\t\t\t\"read\",\n\t\t\t\t\"recvfrom\",\n\t\t\t\t\"recvmsg\",\n\t\t\t\t\"rt_sigaction\",\n\t\t\t\t\"rt_sigprocmask\",\n\t\t\t\t\"rt_sigreturn\",\n\t\t\t\t\"sendmsg\",\n\t\t\t\t\"sendto\",\n\t\t\t\t\"setsockopt\",\n\t\t\t\t\"sigreturn\",\n\t\t\t\t\"socket\",\n\t\t\t\t\"time\",\n\t\t\t\t\"uname\",\n\t\t\t\t\"write\",\n\t\t\t\t\"writev\"\n\t\t\t],\n\t\t\t\"action\": \"SCMP_ACT_ALLOW\"\n\t\t}\n\t]\n}\n"
  },
  {
    "path": "package/network/services/ustp/Makefile",
    "content": "#\n# Copyright (C) 2021 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=ustp\nPKG_RELEASE:=1\n\nPKG_SOURCE_URL=$(PROJECT_GIT)/project/ustp.git\nPKG_SOURCE_PROTO:=git\nPKG_SOURCE_DATE:=2021-09-21\nPKG_SOURCE_VERSION:=462b3a491347e452c15220861949b1d6371fa59e\nPKG_MIRROR_HASH:=0e96edc983cf437b95874e5715d743f30bb826d8757dc3771ff872ab9cf18f35\n\nPKG_MAINTAINER:=Felix Fietkau <nbd@nbd.name>\nPKG_LICENSE:=GPL-2.0\n\ninclude $(INCLUDE_DIR)/package.mk\ninclude $(INCLUDE_DIR)/cmake.mk\n\ndefine Package/ustp\n  SECTION:=net\n  CATEGORY:=Network\n  TITLE:=OpenWrt STP/RSTP daemon\n  DEPENDS:=+libubox +libubus\nendef\n\nTARGET_CFLAGS += -I$(STAGING_DIR)/usr/include -flto\nTARGET_LDFLAGS += -flto -fuse-linker-plugin\n\ndefine Package/ustp/install\n\t$(INSTALL_DIR) $(1)/sbin $(1)/etc/init.d\n\t$(INSTALL_BIN) $(PKG_BUILD_DIR)/ipkg-install/sbin/* $(1)/sbin/\n\t$(INSTALL_BIN) ./files/ustpd.init $(1)/etc/init.d/ustpd\nendef\n\n$(eval $(call BuildPackage,ustp))\n"
  },
  {
    "path": "package/network/services/ustp/files/ustpd.init",
    "content": "#!/bin/sh /etc/rc.common\n# Copyright (c) 2021 OpenWrt.org\n\nSTART=50\n\nUSE_PROCD=1\nPROG=/sbin/ustpd\n\nstart_service() {\n\tprocd_open_instance\n\tprocd_set_param command \"$PROG\"\n\tprocd_set_param respawn\n\tprocd_close_instance\n}\n"
  },
  {
    "path": "package/network/utils/adb-enablemodem/Makefile",
    "content": "include $(TOPDIR)/rules.mk\n\nPKG_NAME:=adb-enablemodem\nPKG_VERSION:=2017-03-05\nPKG_RELEASE:=1\n\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine Package/adb-enablemodem\n  SECTION:=net\n  CATEGORY:=Network\n  SUBMENU:=WWAN\n  TITLE:=Enable modem via adb\n  DEPENDS:=+adb\nendef\n\ndefine Build/Compile\n        true\nendef\n\ndefine Package/adb-enablemodem/install\n\t$(INSTALL_DIR)\t$(1)/etc/init.d\n\t$(INSTALL_BIN)\t./files/adb-enablemodem\t$(1)/etc/init.d/adb-enablemodem\nendef\n\n$(eval $(call BuildPackage,adb-enablemodem))\n"
  },
  {
    "path": "package/network/utils/adb-enablemodem/files/adb-enablemodem",
    "content": "#!/bin/sh /etc/rc.common\n\nSTART=99\n\nadb_exec() {\n\tadb -s \"$serial\" shell \"( $1 ) >/dev/null 2>&1\"'; printf \"\\nEXIT_CODE: %i\\n\" $?' | head -c 64 | grep -qx 'EXIT_CODE: 0\\r\\?'\n}\n\nenablemodem_do() {\n\tlogger -t adb-enablemodem 'INFO: waiting for device'\n\tadb wait-for-device\n\tserial=\"$(adb get-serialno)\"\n\n\tvendor_id=\"$(adb -s \"$serial\" shell 'uci get product.usb.vid' | head -c 16 | tr -d '\\r\\n')\"\n\tproduct_id=\"$(adb -s \"$serial\" shell 'uci get product.usb.pid' | head -c 16 | tr -d '\\r\\n')\"\n\n\tcase \"$vendor_id:$product_id\" in\n\t\"0x2357:0x000D\") # TP-LINK LTE MODULE\n\t\tcase \"$1\" in\n\t\tstart)\n\t\t\tif adb_exec '\n\t\t\t\tchmod +x /WEBSERVER/www/cgi-bin/*\n\t\t\t\tfds=\"$(ls /proc/$$/fd | grep -v \"^[012]$\")\"\n\t\t\t\tfor fd in $fds; do\n\t\t\t\t\teval \"exec $fd>&-\"\n\t\t\t\tdone\n\t\t\t\tstart-stop-daemon -x httpd -S -- -h /WEBSERVER/www/\n\t\t\t'; then\n\t\t\t\tlogger -t adb-enablemodem 'INFO: httpd on modem started'\n\t\t\telse\n\t\t\t\tlogger -t adb-enablemodem 'ERROR: failed to start httpd on modem'\n\t\t\tfi\n\t\t\toption_newid='/sys/bus/usb-serial/drivers/option1/new_id'\n\t\t\tif [ -e \"$option_newid\" ]; then\n\t\t\t\tprintf '%s %s' \"$vendor_id\" \"$product_id\" > \"$option_newid\"\n\t\t\tfi\n\t\t\t;;\n\t\tstop)\n\t\t\tif adb_exec 'start-stop-daemon -x httpd -K'; then\n\t\t\t\tlogger -t adb-enablemodem 'INFO: httpd on modem stopped'\n\t\t\telse\n\t\t\t\tlogger -t adb-enablemodem 'ERROR: failed to stop httpd on modem'\n\t\t\tfi\n\t\t\t;;\n\t\tesac\n\t\t;;\n\t*)\n\t\tlogger -t adb-enablemodem \"ERROR: unknown device $vendor_id:$product_id\"\n\t\t;;\n\tesac\n}\n\nstart() {\n\t( enablemodem_do start ) &\n}\n\nstop() {\n\t( enablemodem_do stop ) &\n}\n\nrestart() {\n\t( enablemodem_do stop; enablemodem_do start ) &\n}\n\n"
  },
  {
    "path": "package/network/utils/arptables/Makefile",
    "content": "# Copyright (C) 2006-2016 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=arptables\nPKG_RELEASE:=1\n\nPKG_SOURCE_URL:=https://git.netfilter.org/arptables\nPKG_SOURCE_PROTO:=git\nPKG_SOURCE_DATE:=2015-05-20\nPKG_SOURCE_VERSION:=f4ab8f63f11a72f14687a6646d04ae1bae3fa45f\nPKG_MIRROR_HASH:=84bc660be4c9f70be91046acfd87785add930eceab7c543036058e1a9de2e9d9\n\nPKG_LICENSE:=GPL-2.0\n\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine Package/arptables-legacy\n  SECTION:=net\n  CATEGORY:=Network\n  SUBMENU:=Firewall\n  TITLE:=ARP firewalling software\n  DEPENDS:=+kmod-arptables\n  URL:=https://git.netfilter.org/arptables/\n  PROVIDES:=arptables\n  ALTERNATIVES:=\\\n    200:/usr/sbin/arptables:/usr/sbin/arptables-legacy\nendef\n\nMAKE_FLAGS += \\\n\tCOPT_FLAGS=\"$(TARGET_CFLAGS) -D__OPTIMIZE__=1\" \\\n\tKERNEL_DIR=\"$(LINUX_DIR)\"\n\ndefine Package/arptables-legacy/install\n\t$(INSTALL_DIR) $(1)/usr/sbin\n\t$(INSTALL_BIN) $(PKG_BUILD_DIR)/arptables $(1)/usr/sbin/arptables-legacy\nendef\n\n$(eval $(call BuildPackage,arptables-legacy))\n"
  },
  {
    "path": "package/network/utils/bpftools/Makefile",
    "content": "#\n# Copyright (C) 2020 Tony Ambardar <itugrok@yahoo.com>\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=bpftools\nPKG_RELEASE:=1\n\nPKG_SOURCE_URL:=https://github.com/libbpf/bpftool\nPKG_SOURCE_PROTO:=git\nPKG_SOURCE_DATE:=2022-03-08\nPKG_SOURCE_VERSION:=04c465fd1f561f67796dc68bbfe1aa7cfa956c3c\nPKG_MIRROR_HASH:=e22a954cd186f43228a96586bbdc120b11e6c87360ab88ae96ba37afb9c7cb58\nPKG_ABI_VERSION:=$(call abi_version_str,$(PKG_SOURCE_DATE))\n\nPKG_MAINTAINER:=Tony Ambardar <itugrok@yahoo.com>\n\nPKG_USE_MIPS16:=0\nPKG_BUILD_PARALLEL:=1\nPKG_INSTALL:=1\n\ninclude $(INCLUDE_DIR)/package.mk\ninclude $(INCLUDE_DIR)/nls.mk\n\ndefine Package/bpftool/Default\n  SECTION:=net\n  CATEGORY:=Network\n  TITLE:=bpftool - eBPF subsystem utility\n  LICENSE:=GPL-2.0-only OR BSD-2-Clause\n  URL:=http://www.kernel.org\n  DEPENDS:=+libelf\nendef\n\ndefine Package/bpftool-minimal\n  $(call Package/bpftool/Default)\n  TITLE+= (Minimal)\n  VARIANT:=minimal\n  DEFAULT_VARIANT:=1\n  PROVIDES:=bpftool\n  ALTERNATIVES:=200:/usr/sbin/bpftool:/usr/libexec/bpftool-minimal\nendef\n\ndefine Package/bpftool-full\n  $(call Package/bpftool/Default)\n  TITLE+= (Full)\n  VARIANT:=full\n  PROVIDES:=bpftool\n  ALTERNATIVES:=300:/usr/sbin/bpftool:/usr/libexec/bpftool-full\n  DEPENDS+= +libbfd +libopcodes\nendef\n\ndefine Package/bpftool-minimal/description\n  A tool for inspection and simple manipulation of eBPF programs and maps.\nendef\n\ndefine Package/bpftool-full/description\n  A tool for inspection and simple manipulation of eBPF programs and maps.\n  This full version uses libbfd and libopcodes to support disassembly of\n  eBPF programs and jited code.\nendef\n\ndefine Package/libbpf\n  SECTION:=libs\n  CATEGORY:=Libraries\n  TITLE:=libbpf - eBPF helper library\n  VARIANT:=lib\n  LICENSE:=LGPL-2.1 OR BSD-2-Clause\n  ABI_VERSION:=$(PKG_ABI_VERSION)\n  URL:=http://www.kernel.org\n  DEPENDS:=+libelf\nendef\n\ndefine Package/libbpf/description\n  libbpf is a library for loading eBPF programs and reading and manipulating eBPF objects from user-space.\nendef\n\n\n# LTO not compatible with DSO using PIC\nifneq ($(BUILD_VARIANT),lib)\n  TARGET_CFLAGS += -ffunction-sections -fdata-sections -flto\n  TARGET_LDFLAGS += -Wl,--gc-sections\nendif\n\nifeq ($(BUILD_VARIANT),full)\n  full:=1\nelse\n  full:=0\nendif\n\nMAKE_VARS = \\\n\tEXTRA_CFLAGS=\"$(TARGET_CFLAGS) $(TARGET_CPPFLAGS)\" \\\n\tLDFLAGS=\"$(TARGET_LDFLAGS)\"\n\nMAKE_FLAGS += \\\n\tOUTPUT=\"$(PKG_BUILD_DIR)/\" \\\n\tprefix=\"/usr\" \\\n\t$(if $(findstring c,$(OPENWRT_VERBOSE)),V=1,V='') \\\n\tLIBSUBDIR=lib \\\n\tcheck_feat=0 \\\n\tfeature-clang-bpf-co-re=0 \\\n\tfeature-reallocarray=1 \\\n\tfeature-zlib=1 \\\n\tfeature-libbfd=$(full) \\\n\tfeature-libcap=0 \\\n\tfeature-disassembler-four-args=$(full)\n\nifeq ($(BUILD_VARIANT),lib)\n  MAKE_PATH = libbpf/src\nelse\n  MAKE_PATH = src\nendif\n\ndefine Build/InstallDev/libbpf\n\t$(INSTALL_DIR) $(1)/usr/include/bpf\n\t$(CP) $(PKG_INSTALL_DIR)/usr/include/bpf/*.h $(1)/usr/include/bpf/\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/libbpf.{a,so*} \\\n\t\t$(1)/usr/lib/\n\t$(INSTALL_DIR) $(1)/usr/lib/pkgconfig\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/pkgconfig/libbpf.pc \\\n\t\t$(1)/usr/lib/pkgconfig/\n\t$(SED) 's,/usr/include,$$$${prefix}/include,g' \\\n\t\t$(1)/usr/lib/pkgconfig/libbpf.pc\n\t$(SED) 's,/usr/lib,$$$${exec_prefix}/lib,g' \\\n\t\t$(1)/usr/lib/pkgconfig/libbpf.pc\nendef\n\nifeq ($(BUILD_VARIANT),lib)\n  Build/InstallDev=$(Build/InstallDev/libbpf)\nendif\n\ndefine Package/bpftool-$(BUILD_VARIANT)/install\n\t$(INSTALL_DIR) $(1)/usr/libexec\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/sbin/bpftool \\\n\t\t$(1)/usr/libexec/bpftool-$(BUILD_VARIANT)\nendef\n\ndefine Package/libbpf/install\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/libbpf.so.* $(1)/usr/lib/\nendef\n\n$(eval $(call BuildPackage,libbpf))\n$(eval $(call BuildPackage,bpftool-full))\n$(eval $(call BuildPackage,bpftool-minimal))\n"
  },
  {
    "path": "package/network/utils/bpftools/patches/001-cflags.patch",
    "content": "--- a/libbpf/src/Makefile\n+++ b/libbpf/src/Makefile\n@@ -25,6 +25,7 @@ ALL_CFLAGS := $(INCLUDES)\n \n SHARED_CFLAGS += -fPIC -fvisibility=hidden -DSHARED\n \n+CFLAGS = $(EXTRA_CFLAGS)\n CFLAGS ?= -g -O2 -Werror -Wall -std=gnu89\n ALL_CFLAGS += $(CFLAGS) -D_LARGEFILE64_SOURCE -D_FILE_OFFSET_BITS=64\n ALL_LDFLAGS += $(LDFLAGS)\n"
  },
  {
    "path": "package/network/utils/bpftools/patches/002-includes.patch",
    "content": "--- a/libbpf/include/linux/list.h\n+++ b/libbpf/include/linux/list.h\n@@ -3,6 +3,8 @@\n #ifndef __LINUX_LIST_H\n #define __LINUX_LIST_H\n \n+#include <linux/types.h>\n+\n #define LIST_HEAD_INIT(name) { &(name), &(name) }\n #define LIST_HEAD(name) \\\n         struct list_head name = LIST_HEAD_INIT(name)\n--- a/src/Makefile\n+++ b/src/Makefile\n@@ -73,10 +73,10 @@ CFLAGS += -W -Wall -Wextra -Wno-unused-p\n CFLAGS += $(filter-out -Wswitch-enum -Wnested-externs,$(EXTRA_WARNINGS))\n CFLAGS += -DPACKAGE='\"bpftool\"' -D__EXPORTED_HEADERS__ \\\n \t-I$(if $(OUTPUT),$(OUTPUT),.) \\\n-\t-I$(LIBBPF_INCLUDE) \\\n \t-I$(srctree)/src/kernel/bpf/ \\\n \t-I$(srctree)/include \\\n-\t-I$(srctree)/include/uapi\n+\t-I$(srctree)/include/uapi \\\n+\t-I$(LIBBPF_INCLUDE)\n ifneq ($(BPFTOOL_VERSION),)\n CFLAGS += -DBPFTOOL_VERSION='\"$(BPFTOOL_VERSION)\"'\n endif\n"
  },
  {
    "path": "package/network/utils/comgt/Makefile",
    "content": "#\n# Copyright (C) 2006-2014 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=comgt\nPKG_VERSION:=0.32\nPKG_RELEASE:=34\n\nPKG_SOURCE:=$(PKG_NAME).$(PKG_VERSION).tgz\nPKG_SOURCE_URL:=@SF/comgt\nPKG_HASH:=0cedb2a5aa608510da66a99aab74df3db363df495032e57e791a2ff55f1d7913\n\nPKG_MAINTAINER:=Felix Fietkau <nbd@nbd.name>\nPKG_LICENSE:=GPL-2.0+\n\nPKG_BUILD_DIR:=$(BUILD_DIR)/$(PKG_NAME).$(PKG_VERSION)\nPKG_CHECK_FORMAT_SECURITY:=0\n\nPKG_FLAGS:=nonshared\n\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine Package/comgt/Default\n  SECTION:=net\n  CATEGORY:=Network\n  SUBMENU:=WWAN\nendef\n\ndefine Package/comgt\n$(call Package/comgt/Default)\n  TITLE:=Option/Vodafone 3G/GPRS control tool\n  DEPENDS:=+chat\n  URL:=http://manpages.ubuntu.com/manpages/trusty/man1/comgt.1.html\nendef\n\ndefine Package/comgt-directip\n$(call Package/comgt/Default)\n  TITLE:=Sierra Wireless Direct-IP support\n  DEPENDS:=+comgt +kmod-usb-serial +kmod-usb-serial-sierrawireless +kmod-usb-net +kmod-usb-net-sierrawireless\nendef\n\ndefine Package/comgt-ncm\n$(call Package/comgt/Default)\n  TITLE+=NCM 3G/4G Support\n  DEPENDS:=+comgt +wwan +kmod-usb-serial-option +kmod-usb-net-huawei-cdc-ncm\nendef\n\ndefine Package/comgt/description\n comgt is a scripting language interpreter useful for establishing \n communications on serial lines and through PCMCIA modems as well as GPRS \n and 3G datacards.\nendef\n\ndefine Build/Compile\n\t$(MAKE) -C $(PKG_BUILD_DIR) \\\n\t\t$(TARGET_CONFIGURE_OPTS) \\\n\t\tCFLAGS=\"$(TARGET_CFLAGS)\" \\\n\t\tLDFLAGS=\"\" \\\n\t\tcomgt\nendef\n\ndefine Package/comgt/install\n\t$(INSTALL_DIR) $(1)/usr/bin\n\t$(INSTALL_BIN) $(PKG_BUILD_DIR)/comgt $(1)/usr/bin/\n\t$(LN) comgt $(1)/usr/bin/gcom\n\t$(INSTALL_DIR) $(1)/etc/chatscripts\n\t$(INSTALL_DATA) ./files/3g.chat $(1)/etc/chatscripts/3g.chat\n\t$(INSTALL_DATA) ./files/evdo.chat $(1)/etc/chatscripts/evdo.chat\n\t$(INSTALL_DIR) $(1)/etc/gcom\n\t$(INSTALL_DATA) ./files/setpin.gcom $(1)/etc/gcom/setpin.gcom\n\t$(INSTALL_DATA) ./files/setmode.gcom $(1)/etc/gcom/setmode.gcom\n\t$(INSTALL_DATA) ./files/getcardinfo.gcom $(1)/etc/gcom/getcardinfo.gcom\n\t$(INSTALL_DATA) ./files/getstrength.gcom $(1)/etc/gcom/getstrength.gcom\n\t$(INSTALL_DATA) ./files/getcarrier.gcom $(1)/etc/gcom/getcarrier.gcom\n\t$(INSTALL_DATA) ./files/getcnum.gcom $(1)/etc/gcom/getcnum.gcom\n\t$(INSTALL_DATA) ./files/getimsi.gcom $(1)/etc/gcom/getimsi.gcom\n\t$(INSTALL_DIR) $(1)/etc/hotplug.d/tty\n\t$(INSTALL_CONF) ./files/3g.usb $(1)/etc/hotplug.d/tty/30-3g\n\t$(INSTALL_DIR) $(1)/lib/netifd/proto\n\t$(INSTALL_BIN) ./files/3g.sh $(1)/lib/netifd/proto/3g.sh\nendef\n\ndefine Package/comgt-directip/install\n\t$(INSTALL_DIR) $(1)/etc/gcom\n\t$(INSTALL_DATA) ./files/directip.gcom $(1)/etc/gcom/directip.gcom\n\t$(INSTALL_DATA) ./files/directip-stop.gcom $(1)/etc/gcom/directip-stop.gcom\n\t$(INSTALL_DIR) $(1)/lib/netifd/proto\n\t$(INSTALL_BIN) ./files/directip.sh $(1)/lib/netifd/proto/directip.sh\nendef\n\ndefine Package/comgt-ncm/install\n\t$(INSTALL_DIR) $(1)/etc/gcom\n\t$(INSTALL_DATA) ./files/ncm.json $(1)/etc/gcom/ncm.json\n\t$(INSTALL_DATA) ./files/runcommand.gcom $(1)/etc/gcom/runcommand.gcom\n\t$(INSTALL_DIR) $(1)/lib/netifd/proto\n\t$(INSTALL_BIN) ./files/ncm.sh $(1)/lib/netifd/proto/ncm.sh\nendef\n\n$(eval $(call BuildPackage,comgt))\n$(eval $(call BuildPackage,comgt-directip))\n$(eval $(call BuildPackage,comgt-ncm))\n"
  },
  {
    "path": "package/network/utils/comgt/files/3g.chat",
    "content": "ABORT   BUSY\nABORT   'NO CARRIER'\nABORT   ERROR\nREPORT  CONNECT\nTIMEOUT 10\n\"\"      \"AT&F\"\nOK      \"ATE1\"\nOK      'AT+CGDCONT=1,\"IP\",\"$USE_APN\"'\nSAY     \"Calling UMTS/GPRS\"\nTIMEOUT 30\nOK      \"ATD$DIALNUMBER\"\nCONNECT ' '\n"
  },
  {
    "path": "package/network/utils/comgt/files/3g.sh",
    "content": "#!/bin/sh\n\n[ -n \"$INCLUDE_ONLY\" ] || {\n\tNOT_INCLUDED=1\n\tINCLUDE_ONLY=1\n\n\t. ../netifd-proto.sh\n\t. ./ppp.sh\n\tinit_proto \"$@\"\n}\n\nproto_3g_init_config() {\n\tno_device=1\n\tavailable=1\n\tppp_generic_init_config\n\tproto_config_add_string \"device:device\"\n\tproto_config_add_string \"apn\"\n\tproto_config_add_string \"service\"\n\tproto_config_add_string \"pincode\"\n\tproto_config_add_string \"delay\"\n\tproto_config_add_string \"dialnumber\"\n}\n\nproto_3g_setup() {\n\tlocal interface=\"$1\"\n\tlocal chat\n\n\tjson_get_var device device\n\tjson_get_var apn apn\n\tjson_get_var service service\n\tjson_get_var pincode pincode\n\tjson_get_var dialnumber dialnumber\n\tjson_get_var delay delay\n\n\t[ -n \"$dat_device\" ] && device=$dat_device\n\n\tdevice=\"$(readlink -f $device)\"\n\t[ -e \"$device\" ] || {\n\t\tproto_set_available \"$interface\" 0\n\t\treturn 1\n\t}\n\n\t[ -n \"$delay\" ] && sleep \"$delay\"\n\n\tcase \"$service\" in\n\t\tcdma|evdo)\n\t\t\tchat=\"/etc/chatscripts/evdo.chat\"\n\t\t;;\n\t\t*)\n\t\t\tchat=\"/etc/chatscripts/3g.chat\"\n\t\t\tcardinfo=$(gcom -d \"$device\" -s /etc/gcom/getcardinfo.gcom)\n\t\t\tif echo \"$cardinfo\" | grep -q Novatel; then\n\t\t\t\tcase \"$service\" in\n\t\t\t\t\tumts_only) CODE=2;;\n\t\t\t\t\tgprs_only) CODE=1;;\n\t\t\t\t\t*) CODE=0;;\n\t\t\t\tesac\n\t\t\t\texport MODE=\"AT\\$NWRAT=${CODE},2\"\n\t\t\telif echo \"$cardinfo\" | grep -q Option; then\n\t\t\t\tcase \"$service\" in\n\t\t\t\t\tumts_only) CODE=1;;\n\t\t\t\t\tgprs_only) CODE=0;;\n\t\t\t\t\t*) CODE=3;;\n\t\t\t\tesac\n\t\t\t\texport MODE=\"AT_OPSYS=${CODE}\"\n\t\t\telif echo \"$cardinfo\" | grep -q \"Sierra Wireless\"; then\n\t\t\t\tSIERRA=1\n\t\t\telif echo \"$cardinfo\" | grep -qi huawei; then\n\t\t\t\tcase \"$service\" in\n\t\t\t\t\tumts_only) CODE=\"14,2\";;\n\t\t\t\t\tgprs_only) CODE=\"13,1\";;\n\t\t\t\t\t*) CODE=\"2,2\";;\n\t\t\t\tesac\n\t\t\t\texport MODE=\"AT^SYSCFG=${CODE},3FFFFFFF,2,4\"\n\t\t\tfi\n\n\t\t\tif [ -n \"$pincode\" ]; then\n\t\t\t\tPINCODE=\"$pincode\" gcom -d \"$device\" -s /etc/gcom/setpin.gcom || {\n\t\t\t\t\tproto_notify_error \"$interface\" PIN_FAILED\n\t\t\t\t\tproto_block_restart \"$interface\"\n\t\t\t\t\treturn 1\n\t\t\t\t}\n\t\t\tfi\n\t\t\t[ -n \"$MODE\" ] && gcom -d \"$device\" -s /etc/gcom/setmode.gcom\n\n\t\t\t# wait for carrier to avoid firmware stability bugs\n\t\t\t[ -n \"$SIERRA\" ] && {\n\t\t\t\tgcom -d \"$device\" -s /etc/gcom/getcarrier.gcom || return 1\n\t\t\t}\n\n\t\t\tif [ -z \"$dialnumber\" ]; then\n\t\t\t\tdialnumber=\"*99***1#\"\n\t\t\tfi\n\n\t\t;;\n\tesac\n\n\tconnect=\"${apn:+USE_APN=$apn }DIALNUMBER=$dialnumber /usr/sbin/chat -t5 -v -E -f $chat\"\n\tppp_generic_setup \"$interface\" \\\n\t\tnoaccomp \\\n\t\tnopcomp \\\n\t\tnovj \\\n\t\tnobsdcomp \\\n\t\tnoauth \\\n\t\tset EXTENDPREFIX=1 \\\n\t\tlock \\\n\t\tcrtscts \\\n\t\t115200 \"$device\"\n\treturn 0\n}\n\nproto_3g_teardown() {\n\tproto_kill_command \"$interface\"\n}\n\n[ -z \"$NOT_INCLUDED\" ] || add_protocol 3g\n"
  },
  {
    "path": "package/network/utils/comgt/files/3g.usb",
    "content": "#!/bin/sh\n. /lib/functions.sh\n. /lib/netifd/netifd-proto.sh\n\nfind_3g_iface() {\n\tlocal cfg=\"$1\"\n\tlocal tty=\"$2\"\n\n\tlocal proto\n\tconfig_get proto \"$cfg\" proto\n\t[ \"$proto\" = 3g ] || [ \"$proto\" = ncm ] || return 0\n\n\t# bypass state vars here because 00-netstate could clobber .device\n\tlocal dev=$(uci_get network \"$cfg\" device)\n\n\tif [ \"${dev##*/}\" = \"${tty##*/}\" ]; then\n\t\tif [ \"$ACTION\" = add ]; then\n\t\t\tproto_set_available \"$cfg\" 1\n\t\tfi\n\t\tif [ \"$ACTION\" = remove ]; then\n\t\t\tproto_set_available \"$cfg\" 0\n\t\tfi\n\tfi\n}\n\n[ \"$ACTION\" = add ] || [ \"$ACTION\" = remove ] || exit 0\n\ncase \"$DEVICENAME\" in\n\ttty*)\n\t\t[ -e \"/dev/$DEVICENAME\" ] || [ \"$ACTION\" = remove ] || exit 0\n\t\tconfig_load network\n\t\tconfig_foreach find_3g_iface interface \"/dev/$DEVICENAME\"\n\t;;\nesac\n\n"
  },
  {
    "path": "package/network/utils/comgt/files/directip-stop.gcom",
    "content": "opengt\nset com 115200n81\nset comecho off\nset senddelay 0.05\nwaitquiet 1 0.2\n\n:start\n send \"AT!SCACT=0,3^m\"\n waitfor 5 \"OK\"\n if % = 0 goto hangupok\n print \"WWAN error. Hangup failed.\\r\\n\"\n exit 1\n\n:hangupok\n print \"WWAN connection established.\\r\\n\"\n exit 0\n"
  },
  {
    "path": "package/network/utils/comgt/files/directip.gcom",
    "content": "opengt\nset com 115200n81\nset comecho off\nset senddelay 0.05\nwaitquiet 1 0.2\n\n:start\n if $env(\"USE_AUTH\") = \"0\" goto connect\n send \"AT$QCPDPP=3,\"\n send $env(\"USE_AUTH\")\n send \",\\\"\"\n if $env(\"USE_USER\") <> \"\" send $env(\"USE_USER\")\n send \"\\\",\\\"\"\n if $env(\"USE_PASS\") <> \"\" send $env(\"USE_PASS\")\n send \"\\\"^m\"\n waitfor 5 \"OK\"\n if % = 0 goto connect\n print \"WWAN error. Auth failed.\\r\\n\"\n exit 1\n\n:connect\n send \"AT+CFUN=1^m\"\n send \"AT+CGDCONT=3,\\\"IP\\\",\\\"\"\n send $env(\"USE_APN\")\n send \"\\\"^m\"\n waitfor 5 \"OK\"\n if % = 0 goto connok\n print \"WWAN error. Connection failed.\\r\\n\"\n exit 1\n\n:connok\n let c=1\n:loop\n sleep 2\n send \"AT+CGATT?^m\"\n waitfor 5 \"+CGATT: 1\"\n if % = 0 goto carrierok\n if c > 10 goto carriererr\n inc c\n goto loop\n\n:carriererr\n print \"WWAN error. No carrier.\\r\\n\"\n exit 1\n\n:carrierok\n send \"AT!SCACT=1,3^m\"\n waitfor 5 \"OK\"\n if % = 0 goto dialok\n print \"WWAN error. Dialing failed.\\r\\n\"\n exit 1\n\n:dialok\n print \"WWAN connection established.\\r\\n\"\n exit 0\n"
  },
  {
    "path": "package/network/utils/comgt/files/directip.sh",
    "content": "#!/bin/sh\n\n[ -n \"$INCLUDE_ONLY\" ] || {\n\t. /lib/functions.sh\n\t. ../netifd-proto.sh\n\tinit_proto \"$@\"\n}\n\nproto_directip_init_config() {\n\tavailable=1\n\tno_device=1\n\tproto_config_add_string \"device:device\"\n\tproto_config_add_string \"apn\"\n\tproto_config_add_string \"pincode\"\n\tproto_config_add_string \"auth\"\n\tproto_config_add_string \"username\"\n\tproto_config_add_string \"password\"\n\tproto_config_add_defaults\n}\n\nproto_directip_setup() {\n\tlocal interface=\"$1\"\n\tlocal chat devpath devname\n\n\tlocal device apn pincode ifname auth username password $PROTO_DEFAULT_OPTIONS\n\tjson_get_vars device apn pincode auth username password $PROTO_DEFAULT_OPTIONS\n\n\t[ -n \"$ctl_device\" ] && device=$ctl_device\n\n\tdevice=\"$(readlink -f $device)\"\n\t[ -e \"$device\" ] || {\n\t\tproto_notify_error \"$interface\" NO_DEVICE\n\t\tproto_set_available \"$interface\" 0\n\t\treturn 1\n\t}\n\n\tdevname=\"$(basename \"$device\")\"\n\tdevpath=\"$(readlink -f /sys/class/tty/$devname/device)\"\n\tifname=\"$( ls \"$devpath\"/../../*/net )\"\n\n\t[ -n \"$ifname\" ] || {\n\t\tproto_notify_error \"$interface\" NO_IFNAME\n\t\tproto_set_available \"$interface\" 0\n\t\treturn 1\n\t}\n\n\tgcom -d \"$device\" -s /etc/gcom/getcardinfo.gcom | grep -q \"Sierra Wireless\" || {\n\t\tproto_notify_error \"$interface\" BAD_DEVICE\n\t\tproto_block_restart \"$interface\"\n\t\treturn 1\n\t}\n\n\tif [ -n \"$pincode\" ]; then\n\t\tPINCODE=\"$pincode\" gcom -d \"$device\" -s /etc/gcom/setpin.gcom || {\n\t\t\tproto_notify_error \"$interface\" PIN_FAILED\n\t\t\tproto_block_restart \"$interface\"\n\t\t\treturn 1\n\t\t}\n\tfi\n\t# wait for carrier to avoid firmware stability bugs\n\tgcom -d \"$device\" -s /etc/gcom/getcarrier.gcom || return 1\n\n\tlocal auth_type=0\n\tcase $auth in\n\tpap) auth_type=1;;\n\tchap) auth_type=2;;\n\tesac\n\n\tUSE_APN=\"$apn\" USE_USER=\"$username\" USE_PASS=\"$password\" USE_AUTH=\"$auth_type\" \\\n\t\t\tgcom -d \"$device\" -s /etc/gcom/directip.gcom || {\n\t\tproto_notify_error \"$interface\" CONNECT_FAILED\n\t\tproto_block_restart \"$interface\"\n\t\treturn 1\n\t}\n\n\tlogger -p daemon.info -t \"directip[$$]\" \"Connected, starting DHCP\"\n\tproto_init_update \"$ifname\" 1\n\tproto_send_update \"$interface\"\n\n\tjson_init\n\tjson_add_string name \"${interface}_4\"\n\tjson_add_string ifname \"@$interface\"\n\tjson_add_string proto \"dhcp\"\n\tproto_add_dynamic_defaults\n\tubus call network add_dynamic \"$(json_dump)\"\n\n\tjson_init\n\tjson_add_string name \"${interface}_6\"\n\tjson_add_string ifname \"@$interface\"\n\tjson_add_string proto \"dhcpv6\"\n\tjson_add_string extendprefix 1\n\tproto_add_dynamic_defaults\n\tubus call network add_dynamic \"$(json_dump)\"\n\n\treturn 0\n}\n\nproto_directip_teardown() {\n\tlocal interface=\"$1\"\n\n\tlocal device\n\tjson_get_vars device\n\n\t[ -n \"$ctl_device\" ] && device=$ctl_device\n\n\tgcom -d \"$device\" -s /etc/gcom/directip-stop.gcom || proto_notify_error \"$interface\" CONNECT_FAILED\n\n\tproto_init_update \"*\" 0\n\tproto_send_update \"$interface\"\n}\n\n[ -n \"$INCLUDE_ONLY\" ] || {\n\tadd_protocol directip\n}\n"
  },
  {
    "path": "package/network/utils/comgt/files/evdo.chat",
    "content": "# This is a simple chat script based off of the one provided by Sierra Wireless\n# for CDMA connections.  It should work for both Sprint and Verizon networks.\n\nABORT\tBUSY\nABORT \t'NO CARRIER'\nABORT\tERROR\nABORT \t'NO DIAL TONE'\nABORT \t'NO ANSWER'\nABORT \tDELAYED\nREPORT\tCONNECT\nTIMEOUT\t10\n'' \t\tAT\nOK \t\tATZ\nSAY     'Calling CDMA/EVDO'\nTIMEOUT\t30\nOK\t\tATDT#777\nCONNECT\t''\n"
  },
  {
    "path": "package/network/utils/comgt/files/getcardinfo.gcom",
    "content": "opengt\n set com 115200n81\n set comecho off\n set senddelay 0.02\n waitquiet 0.2 0.2\n flash 0.1\n\n:start\n send \"AT+CGMI^m\"\n get 1 \"\" $s\n print $s\n\n:continue\n exit 0\n"
  },
  {
    "path": "package/network/utils/comgt/files/getcarrier.gcom",
    "content": "opengt\n  set senddelay 0.05\n  waitquiet 1 0.2\n  let c=1\n :loop\n    inc c\n    send \"AT+CGATT?^m\"\n    waitfor 5 \"+CGATT: 1\",\"+CGATT: 0\"\n    print \"\\n.\"\n    if % = -1 goto error\n    if c > 10 goto toolong\n    if % = 0 goto out\n    sleep 2\n    if % = 1 goto loop\n  :toolong\n  exit 1\n  :error\n  exit 0\n  :out\n exit 0\n"
  },
  {
    "path": "package/network/utils/comgt/files/getcnum.gcom",
    "content": "opengt\n set com 115200n81\n set comecho off\n set senddelay 0.02\n waitquiet 0.2 0.2\n flash 0.1\n\n:start\n send \"AT+CNUM^m\"\n get 1 \"^m\" $n\n get 1 \":\" $n\n get 1 \"\\\"\" $n\n get 1 \"\\\"\" $n\n get 1 \"\\\"\" $n\n get 1 \"\\\"\" $n\n let n = len($n)\n if n<1 goto continue\n print $n\n:continue\n exit 0\n"
  },
  {
    "path": "package/network/utils/comgt/files/getimsi.gcom",
    "content": "opengt\n set com 115200n81\n set comecho off\n set senddelay 0.02\n waitquiet 0.2 0.2\n flash 0.1\n\n:start\n send \"AT+CIMI^m\"\n get 1 \"^m\" $s\n get 1 \"^m\" $s\n let x = len($s)\n if x<2 goto continue\n let $s = $right($s, x-1)\n print $s\n:continue\n exit 0\n"
  },
  {
    "path": "package/network/utils/comgt/files/getstrength.gcom",
    "content": "opengt\n set com 115200n81\n set comecho off\n set senddelay 0.02\n waitquiet 0.2 0.2\n flash 0.1\n\n:start\n send \"AT+CSQ^m\"\n get 1 \"\" $s\n print $s\n\n:continue\n exit 0\n"
  },
  {
    "path": "package/network/utils/comgt/files/ncm.json",
    "content": "{\n\t\"huawei\": {\n\t\t\"initialize\": [\n\t\t\t\"AT\",\n\t\t\t\"ATZ\",\n\t\t\t\"ATQ0\",\n\t\t\t\"ATV1\",\n\t\t\t\"ATE1\",\n\t\t\t\"ATS0=0\",\n\t\t\t\"AT+CGDCONT=${profile},\\\\\\\"${pdptype}\\\\\\\"${apn:+,\\\\\\\"$apn\\\\\\\"}\"\n\t\t],\n\t\t\"modes\": {\n\t\t\t\"preferlte\": \"AT^SYSCFGEX=\\\\\\\"030201\\\\\\\",3fffffff,2,4,7fffffffffffffff,,\",\n\t\t\t\"preferumts\": \"AT^SYSCFGEX=\\\\\\\"0201\\\\\\\",3fffffff,2,4,7fffffffffffffff,,\",\n\t\t\t\"lte\": \"AT^SYSCFGEX=\\\\\\\"03\\\\\\\",3fffffff,2,4,7fffffffffffffff,,\",\n\t\t\t\"umts\": \"AT^SYSCFGEX=\\\\\\\"02\\\\\\\",3fffffff,2,4,7fffffffffffffff,,\",\n\t\t\t\"gsm\": \"AT^SYSCFGEX=\\\\\\\"01\\\\\\\",3fffffff,2,4,7fffffffffffffff,,\",\n\t\t\t\"auto\": \"AT^SYSCFGEX=\\\\\\\"00\\\\\\\",3fffffff,2,4,7fffffffffffffff,,\"\n\t\t},\n\t\t\"connect\": \"AT^NDISDUP=${profile},1${apn:+,\\\\\\\"$apn\\\\\\\"}${username:+,\\\\\\\"$username\\\\\\\"}${password:+,\\\\\\\"$password\\\\\\\"}${auth:+,$auth}\",\n\t\t\"disconnect\": \"AT^NDISDUP=${profile},0\"\n\t},\n\t\"samsung\": {\n\t\t\"initialize\": [\n\t\t\t\"AT\",\n\t\t\t\"AT+CGREG=2\",\n\t\t\t\"AT+CFUN=5\",\n\t\t\t\"AT+MODESELECT=3\",\n\t\t\t\"AT+CGDCONT=${profile},\\\\\\\"${pdptype}\\\\\\\"${apn:+,\\\\\\\"$apn\\\\\\\"}\"\n\t\t],\n\t\t\"modes\": {\n\t\t\t\"umts\": \"AT+CHANGEALLPATH=1\"\n\t\t},\n\t\t\"connect\": \"AT+CGATT=1\",\n\t\t\"disconnect\": \"AT+CGATT=0\"\n\t},\n\t\"sierra\": {\n\t\t\"initialize\": [\n\t\t\t\"AT+CFUN=1\",\n\t\t\t\"AT+CGDCONT=${profile},\\\\\\\"${pdptype}\\\\\\\"${apn:+,\\\\\\\"$apn\\\\\\\"}\",\n\t\t\t\"AT$QCPDPP=${profile},${auth:-0}${password:+,\\\\\\\"$password\\\\\\\"}${username:+,\\\\\\\"$username\\\\\\\"}\"\n\t\t],\n\t\t\"modes\": {\n\t\t\t\"preferlte\": \"AT!SELRAT=07\",\n\t\t\t\"preferumts\": \"AT!SELRAT=05\",\n\t\t\t\"lte\": \"AT!SELRAT=06\",\n\t\t\t\"umts\": \"AT!SELRAT=01\",\n\t\t\t\"gsm\": \"AT!SELRAT=02\",\n\t\t\t\"auto\": \"AT!SELRAT=00\"\n\t\t},\n\t\t\"connect\": \"AT!SCACT=1,${profile}\",\n\t\t\"disconnect\": \"AT!SCACT=0,${profile}\"\n\t},\n\t\"sony\": {\n\t\t\"initialize\": [\n\t\t\t\"AT+CFUN=1\",\n\t\t\t\"AT+CGDCONT=${profile},\\\\\\\"${pdptype}\\\\\\\"${apn:+,\\\\\\\"$apn\\\\\\\"}\",\n\t\t\t\"AT*EIAAUW=${profile},1,\\\\\\\"${username}\\\\\\\",\\\\\\\"${password}\\\\\\\",${auth:-00111}\"\n\t\t],\n\t\t\"modes\": {\n\t\t\t\"umts\": \"AT+CFUN=6\",\n\t\t\t\"gsm\": \"AT+CFUN=5\"\n\t\t},\n\t\t\"connect\": \"AT*ENAP=1,${profile}\",\n\t\t\"disconnect\": \"AT*ENAP=0\"\n\t},\n\t\"mtk1\": {\n\t\t\"initialize\": [\n\t\t\t\"AT+CFUN=1\"\n\t\t],\n\t\t\"configure\": [\n\t\t\t\"AT+CGDCONT=${profile},\\\\\\\"${pdptype}\\\\\\\",\\\\\\\"${apn}\\\\\\\",0,0\"\n\t\t],\n\t\t\"connect\": \"AT+CGACT=1,${profile}\",\n\t\t\"finalize\": \"AT+CGDATA=\\\\\\\"M-MBIM\\\\\\\",${profile},1\",\n\t\t\"disconnect\": \"AT+CGACT=0,${profile}\"\n\t},\n\t\"\\\"zte\": {\n\t\t\"initialize\": [\n\t\t\t\"AT+CFUN=1\"\n\t\t],\n\t\t\"configure\": [\n\t\t\t\"AT+ZGDCONT=${profile},\\\\\\\"${pdptype}\\\\\\\",\\\\\\\"${apn}\\\\\\\",\\\\\\\"\\\\\\\",0,0\",\n\t\t\t\"AT+ZGPCOAUTH=${profile},\\\\\\\"${username}\\\\\\\",\\\\\\\"${password}\\\\\\\",0\"\n\t\t],\n\t\t\"connect\": \"AT+ZGACT=1,${profile}\",\n\t\t\"disconnect\": \"AT+ZGACT=0,${profile}\"\n\t},\n\t\"\\\"marvell\\\"\": {\n\t\t\"initialize\": [\n\t\t\t\"AT+CFUN=1\"\n\t\t],\n\t\t\"configure\": [\n\t\t\t\"AT+ZGDCONT=${profile},\\\\\\\"${pdptype}\\\\\\\",\\\\\\\"${apn}\\\\\\\",\\\\\\\"\\\\\\\",0,0\",\n\t\t\t\"AT+ZGPCOAUTH=${profile},\\\\\\\"${username}\\\\\\\",\\\\\\\"${password}\\\\\\\",0\"\n\t\t],\n\t\t\"connect\": \"AT+ZGACT=1,${profile}\",\n\t\t\"disconnect\": \"AT+ZGACT=0,${profile}\"\n\t}\n}\n"
  },
  {
    "path": "package/network/utils/comgt/files/ncm.sh",
    "content": "#!/bin/sh\n\n[ -n \"$INCLUDE_ONLY\" ] || {\n\t. /lib/functions.sh\n\t. ../netifd-proto.sh\n\tinit_proto \"$@\"\n}\n\nproto_ncm_init_config() {\n\tno_device=1\n\tavailable=1\n\tproto_config_add_string \"device:device\"\n\tproto_config_add_string ifname\n\tproto_config_add_string apn\n\tproto_config_add_string auth\n\tproto_config_add_string username\n\tproto_config_add_string password\n\tproto_config_add_string pincode\n\tproto_config_add_string delay\n\tproto_config_add_string mode\n\tproto_config_add_string pdptype\n\tproto_config_add_int profile\n\tproto_config_add_defaults\n}\n\nproto_ncm_setup() {\n\tlocal interface=\"$1\"\n\n\tlocal manufacturer initialize setmode connect finalize devname devpath ifpath\n\n\tlocal device ifname  apn auth username password pincode delay mode pdptype profile $PROTO_DEFAULT_OPTIONS\n\tjson_get_vars device ifname apn auth username password pincode delay mode pdptype profile $PROTO_DEFAULT_OPTIONS\n\n\t[ \"$metric\" = \"\" ] && metric=\"0\"\n\n\t[ -n \"$profile\" ] || profile=1\n\n\tpdptype=$(echo \"$pdptype\" | awk '{print toupper($0)}')\n\t[ \"$pdptype\" = \"IP\" -o \"$pdptype\" = \"IPV6\" -o \"$pdptype\" = \"IPV4V6\" ] || pdptype=\"IP\"\n\n\t[ -n \"$ctl_device\" ] && device=$ctl_device\n\n\t[ -n \"$device\" ] || {\n\t\techo \"No control device specified\"\n\t\tproto_notify_error \"$interface\" NO_DEVICE\n\t\tproto_set_available \"$interface\" 0\n\t\treturn 1\n\t}\n\n\tdevice=\"$(readlink -f $device)\"\n\t[ -e \"$device\" ] || {\n\t\techo \"Control device not valid\"\n\t\tproto_set_available \"$interface\" 0\n\t\treturn 1\n\t}\n\n\t[ -z \"$ifname\" ] && {\n\t\tdevname=\"$(basename \"$device\")\"\n\t\tcase \"$devname\" in\n\t\t'ttyACM'*)\n\t\t\tdevpath=\"$(readlink -f /sys/class/tty/$devname/device)\"\n\t\t\tifpath=\"$devpath/../*/net\"\n\t\t\t;;\n\t\t'tty'*)\n\t\t\tdevpath=\"$(readlink -f /sys/class/tty/$devname/device)\"\n\t\t\tifpath=\"$devpath/../../*/net\"\n\t\t\t;;\n\t\t*)\n\t\t\tdevpath=\"$(readlink -f /sys/class/usbmisc/$devname/device/)\"\n\t\t\tifpath=\"$devpath/net\"\n\t\t\t;;\n\t\tesac\n\t\tifname=\"$(ls $(ls -1 -d $ifpath | head -n 1))\"\n\t}\n\n\t[ -n \"$ifname\" ] || {\n\t\techo \"The interface could not be found.\"\n\t\tproto_notify_error \"$interface\" NO_IFACE\n\t\tproto_set_available \"$interface\" 0\n\t\treturn 1\n\t}\n\n\t[ -n \"$delay\" ] && sleep \"$delay\"\n\n\tmanufacturer=$(gcom -d \"$device\" -s /etc/gcom/getcardinfo.gcom | awk 'NF && $0 !~ /AT\\+CGMI/ { sub(/\\+CGMI: /,\"\"); print tolower($1); exit; }')\n\t[ $? -ne 0 -o -z \"$manufacturer\" ] && {\n\t\techo \"Failed to get modem information\"\n\t\tproto_notify_error \"$interface\" GETINFO_FAILED\n\t\treturn 1\n\t}\n\n\tjson_load \"$(cat /etc/gcom/ncm.json)\"\n\tjson_select \"$manufacturer\"\n\t[ $? -ne 0 ] && {\n\t\techo \"Unsupported modem\"\n\t\tproto_notify_error \"$interface\" UNSUPPORTED_MODEM\n\t\tproto_set_available \"$interface\" 0\n\t\treturn 1\n\t}\n\n\tjson_get_values initialize initialize\n\tfor i in $initialize; do\n\t\teval COMMAND=\"$i\" gcom -d \"$device\" -s /etc/gcom/runcommand.gcom || {\n\t\t\techo \"Failed to initialize modem\"\n\t\t\tproto_notify_error \"$interface\" INITIALIZE_FAILED\n\t\t\treturn 1\n\t\t}\n\tdone\n\n\t[ -n \"$pincode\" ] && {\n\t\tPINCODE=\"$pincode\" gcom -d \"$device\" -s /etc/gcom/setpin.gcom || {\n\t\t\techo \"Unable to verify PIN\"\n\t\t\tproto_notify_error \"$interface\" PIN_FAILED\n\t\t\tproto_block_restart \"$interface\"\n\t\t\treturn 1\n\t\t}\n\t}\n\n\tjson_get_values configure configure\n\techo \"Configuring modem\"\n\tfor i in $configure; do\n\t\teval COMMAND=\"$i\" gcom -d \"$device\" -s /etc/gcom/runcommand.gcom || {\n\t\t\techo \"Failed to configure modem\"\n\t\t\tproto_notify_error \"$interface\" CONFIGURE_FAILED\n\t\t\treturn 1\n\t\t}\n\tdone\n\n\t[ -n \"$mode\" ] && {\n\t\tjson_select modes\n\t\tjson_get_var setmode \"$mode\"\n\t\t[ -n \"$setmode\" ] && {\n\t\t\techo \"Setting mode\"\n\t\t\teval COMMAND=\"$setmode\" gcom -d \"$device\" -s /etc/gcom/runcommand.gcom || {\n\t\t\t\techo \"Failed to set operating mode\"\n\t\t\t\tproto_notify_error \"$interface\" SETMODE_FAILED\n\t\t\t\treturn 1\n\t\t\t}\n\t\t}\n\t\tjson_select ..\n\t}\n\n\techo \"Starting network $interface\"\n\tjson_get_vars connect\n\t[ -n \"$connect\" ] && {\n\t\techo \"Connecting modem\"\n\t\teval COMMAND=\"$connect\" gcom -d \"$device\" -s /etc/gcom/runcommand.gcom || {\n\t\t\techo \"Failed to connect\"\n\t\t\tproto_notify_error \"$interface\" CONNECT_FAILED\n\t\t\treturn 1\n\t\t}\n\t}\n\n\tjson_get_vars finalize\n\n\techo \"Setting up $ifname\"\n\tproto_init_update \"$ifname\" 1\n\tproto_add_data\n\tjson_add_string \"manufacturer\" \"$manufacturer\"\n\tproto_close_data\n\tproto_send_update \"$interface\"\n\n\tlocal zone=\"$(fw3 -q network \"$interface\" 2>/dev/null)\"\n\n\t[ \"$pdptype\" = \"IP\" -o \"$pdptype\" = \"IPV4V6\" ] && {\n\t\tjson_init\n\t\tjson_add_string name \"${interface}_4\"\n\t\tjson_add_string ifname \"@$interface\"\n\t\tjson_add_string proto \"dhcp\"\n\t\tproto_add_dynamic_defaults\n\t\t[ -n \"$zone\" ] && {\n\t\t\tjson_add_string zone \"$zone\"\n\t\t}\n\t\tjson_close_object\n\t\tubus call network add_dynamic \"$(json_dump)\"\n\t}\n\n\t[ \"$pdptype\" = \"IPV6\" -o \"$pdptype\" = \"IPV4V6\" ] && {\n\t\tjson_init\n\t\tjson_add_string name \"${interface}_6\"\n\t\tjson_add_string ifname \"@$interface\"\n\t\tjson_add_string proto \"dhcpv6\"\n\t\tjson_add_string extendprefix 1\n\t\tproto_add_dynamic_defaults\n\t\t[ -n \"$zone\" ] && {\n\t\t\tjson_add_string zone \"$zone\"\n\t\t}\n\t\tjson_close_object\n\t\tubus call network add_dynamic \"$(json_dump)\"\n\t}\n\n\t[ -n \"$finalize\" ] && {\n\t\teval COMMAND=\"$finalize\" gcom -d \"$device\" -s /etc/gcom/runcommand.gcom || {\n\t\t\techo \"Failed to configure modem\"\n\t\t\tproto_notify_error \"$interface\" FINALIZE_FAILED\n\t\t\treturn 1\n\t\t}\n\t}\n}\n\nproto_ncm_teardown() {\n\tlocal interface=\"$1\"\n\n\tlocal manufacturer disconnect\n\n\tlocal device profile\n\tjson_get_vars device profile\n\n\t[ -n \"$ctl_device\" ] && device=$ctl_device\n\n\t[ -n \"$device\" ] || {\n\t\techo \"No control device specified\"\n\t\tproto_notify_error \"$interface\" NO_DEVICE\n\t\tproto_set_available \"$interface\" 0\n\t\treturn 1\n\t}\n\n\tdevice=\"$(readlink -f $device)\"\n\t[ -e \"$device\" ] || {\n\t\techo \"Control device not valid\"\n\t\tproto_set_available \"$interface\" 0\n\t\treturn 1\n\t}\n\n\t[ -n \"$profile\" ] || profile=1\n\n\techo \"Stopping network $interface\"\n\n\tjson_load \"$(ubus call network.interface.$interface status)\"\n\tjson_select data\n\tjson_get_vars manufacturer\n\t[ $? -ne 0 -o -z \"$manufacturer\" ] && {\n\t\t# Fallback to direct detect, for proper handle device replug.\n\t\tmanufacturer=$(gcom -d \"$device\" -s /etc/gcom/getcardinfo.gcom | awk 'NF && $0 !~ /AT\\+CGMI/ { sub(/\\+CGMI: /,\"\"); print tolower($1); exit; }')\n\t\t[ $? -ne 0 -o -z \"$manufacturer\" ] && {\n\t\t\techo \"Failed to get modem information\"\n\t\t\tproto_notify_error \"$interface\" GETINFO_FAILED\n\t\t\treturn 1\n\t\t}\n\t\tjson_add_string \"manufacturer\" \"$manufacturer\"\n\t}\n\n\tjson_load \"$(cat /etc/gcom/ncm.json)\"\n\tjson_select \"$manufacturer\" || {\n\t\techo \"Unsupported modem\"\n\t\tproto_notify_error \"$interface\" UNSUPPORTED_MODEM\n\t\treturn 1\n\t}\n\n\tjson_get_vars disconnect\n\t[ -n \"$disconnect\" ] && {\n\t\teval COMMAND=\"$disconnect\" gcom -d \"$device\" -s /etc/gcom/runcommand.gcom || {\n\t\t\techo \"Failed to disconnect\"\n\t\t\tproto_notify_error \"$interface\" DISCONNECT_FAILED\n\t\t\treturn 1\n\t\t}\n\t}\n\n\tproto_init_update \"*\" 0\n\tproto_send_update \"$interface\"\n}\n[ -n \"$INCLUDE_ONLY\" ] || {\n\tadd_protocol ncm\n}\n"
  },
  {
    "path": "package/network/utils/comgt/files/runcommand.gcom",
    "content": "# run AT-command from environment\nopengt\n set com 115200n81\n set senddelay 0.02\n waitquiet 1 0.2\n flash 0.1\n\n:start\n print \"sending -> \",$env(\"COMMAND\"),\"\\n\"\n send $env(\"COMMAND\")\n send \"^m\"\n\n waitfor 25 \"OK\",\"ERR\",\"ERROR\",\"COMMAND NOT SUPPORT\"\n if % = 0 goto continue\n if % = 1 goto error\n if % = 2 goto error\n if % = 3 goto notsupported\n\n print \"Timeout running AT-command\\n\"\n exit 1\n\n:error\n print \"Error running AT-command\\n\"\n exit 1\n\n:notsupported\n print \"AT-command not supported\\n\"\n exit 1\n\n:continue\n exit 0\n"
  },
  {
    "path": "package/network/utils/comgt/files/setmode.gcom",
    "content": "# set wwan mode from environment\nopengt\n set com 115200n81\n set senddelay 0.02\n waitquiet 1 0.2\n flash 0.1\n\n:start\n print \"Trying to set mode\\n\"\n send $env(\"MODE\")\n send \"^m\"\n\n waitfor 15 \"OK\",\"ERR\",\"ERROR\"\n if % = 0 goto continue\n if % = 1 goto modeerror\n if % = 2 goto modeerror\n\n print \"Timeout setting WWAN mode!\\n\"\n exit 1\n\n:modeerror\n print \"Error setting WWAN mode!\\n\"\n exit 1\n\n:continue\n exit 0\n"
  },
  {
    "path": "package/network/utils/comgt/files/setpin.gcom",
    "content": "# set pin code from evnironment \"$PINCODE\"\nopengt\n set com 115200n81\n set senddelay 0.05\n waitquiet 3 0.5\n flash 0.1\n\n let c=0\n:start\n send \"AT+CFUN=1^m\"\n send \"AT+CPIN?^m\"\n waitfor 15 \"SIM PUK\",\"SIM PIN\",\"READY\",\"ERROR\",\"ERR\"\n if % = -1 goto timeout\n if % = 0 goto ready\n if % = 1 goto setpin\n if % = 2 goto ready\n if % = 3 goto checkrepeat\n if % = 4 goto checkrepeat\n\n:checkrepeat\n inc c\n if c>3 goto pinerror\n waitquiet 12 0.5\n goto start\n\n:timeout\n print \"timeout checking for PIN.\"\n exit 1\n\n:ready\n print \"SIM ready\\n\"\n goto continue\n exit 0\n\n:setpin\n # check if output was \"SIM PIN2\", that's ok.\n waitfor 1 \"2\"\n if % = 0 goto ready\n\n print \"Trying to set PIN\\n\"\n send \"AT+CPIN=\\\"\"\n send $env(\"PINCODE\")\n send \"\\\"^m\"\n\n waitfor 20 \"OK\",\"ERR\"\n if % = -1 goto pinerror\n if % = 0 goto continue\n if % = 1 goto pinerror\n\n:pinerror\n print \"Error setting PIN, check card manually\\n\"\n exit 1\n\n:continue\n print \"PIN set successfully\\n\"\n exit 0\n"
  },
  {
    "path": "package/network/utils/comgt/files/ussd.gcom",
    "content": "opengt\n set com 115200n81\n set comecho off\n set senddelay 0.02\n waitquiet 0.2 0.2\n flash 0.1\n\n:start\n send \"AT+CUSD=1,\"\n send $env(\"ussd\")\n send \",15\"\n send \"^m\"\n waitfor 120 \"+CUSD:\"\n if % = -1 goto timeout\n get 1 \"^m\" $s\n print $s\n exit 0\n\n:timeout\n print \"ERROR: no USSD response, timeout.\\n\"\n exit 1\n"
  },
  {
    "path": "package/network/utils/comgt/patches/001-compile_fix.patch",
    "content": "--- a/Makefile\n+++ b/Makefile\n@@ -32,6 +32,7 @@ SCRIPTPATH = /etc/comgt/\n SCRIPTSRC = ./scripts/\n BIN     = $(CPROG) \n MANP\t= comgt.1 sigmon.1\n+CC\t= cc\n \n CFLAGS  = -c\n LDFLAGS =\n@@ -70,10 +71,5 @@ clean:\n \t-rm *~\n \t-rm $(SCRIPTSRC)*~\n \n-\n-comgt: comgt.o\n-\tcc comgt.o $(LDFLAGS) -o comgt\n-\n-comgt.o: comgt.c comgt.h\n-\tcc comgt.c $(CFLAGS) \n-\n+comgt:  comgt.c comgt.h\n+\t$(CC) $(CFLAGS) -o comgt $< $(LDFLAGS)\n"
  },
  {
    "path": "package/network/utils/comgt/patches/002-termios.patch",
    "content": "--- a/comgt.c\n+++ b/comgt.c\n@@ -30,7 +30,7 @@\n #include <stdio.h>\n #include <stdlib.h>\n #include <signal.h>\n-#include <termio.h>\n+#include <termios.h>\n #include <fcntl.h>\n #include <unistd.h>\n #include <string.h>\n@@ -81,7 +81,7 @@ char token[MAXTOKEN];   /* For gettoken(\n char scriptfile[MAXPATH]; /* Script file name */\n char scriptfilepath[MAXPATH]; /* temp storage for full path */\n BOOL verbose=0; /* Log actions */\n-struct termio cons, stbuf, svbuf;  /* termios: svbuf=before, stbuf=while */\n+struct termios cons, stbuf, svbuf;  /* termios: svbuf=before, stbuf=while */\n int comfd=0; /* Communication file descriptor.  Defaults to stdin. */\n char msg[STRINGL]; /* Massage messages here */\n int preturn,returns[MAXGOSUBS];\n@@ -172,7 +172,7 @@ void dotestkey(void) {\n \n /* Exit after resetting terminal settings */\n void ext(long xtc) {\n-  ioctl(1, TCSETA, &cons);\n+  ioctl(1, TCSETS, &cons);\n   exit(xtc);\n }\n \n@@ -920,24 +920,24 @@ BOOL getonoroff(void) {\n void setcom(void) {\n   stbuf.c_cflag &= ~(CBAUD | CSIZE | CSTOPB | CLOCAL | PARENB);\n   stbuf.c_cflag |= (speed | bits | CREAD | clocal | parity | stopbits );\n-  if (ioctl(comfd, TCSETA, &stbuf) < 0) {\n+  if (ioctl(comfd, TCSETS, &stbuf) < 0) {\n     serror(\"Can't ioctl set device\",1);\n   }\n }\n \n void doset(void) {\n-  struct termio console;\n+  struct termios console;\n   int a,b;\n   gettoken();\n   if(strcmp(token,\"echo\")==0) {\n     a=0;\n     if(getonoroff()) a=ECHO|ECHOE;\n-    if(ioctl(0, TCGETA, &console)<0) {\n+    if(ioctl(0, TCGETS, &console)<0) {\n       serror(\"Can't ioctl FD zero!\\n\",2);\n     }\n     console.c_lflag &= ~(ECHO | ECHOE);\n     console.c_lflag |= a;\n-    ioctl(0, TCSETA, &console);\n+    ioctl(0, TCSETS, &console);\n   }\n   else if(strcmp(token,\"senddelay\")==0) {\n     senddelay=10000L*getdvalue();\n@@ -1224,7 +1224,7 @@ void doclose(void) {\n   if(strcmp(token,\"hardcom\")==0) {\n     if(comfd== -1) serror(\"Com device not open\",1);\n     vmsg(\"Closing device\");\n-    if (ioctl(comfd, TCSETA, &svbuf) < 0) {\n+    if (ioctl(comfd, TCSETS, &svbuf) < 0) {\n       sprintf(msg,\"Can't ioctl set device %s.\\n\",device);\n       serror(msg,1);\n     }\n@@ -1266,12 +1266,12 @@ void opengt(void) {\n       ext(1);\n     }\n   }\n-  if (ioctl (comfd, TCGETA, &svbuf) < 0) {\n+  if (ioctl (comfd, TCGETS, &svbuf) < 0) {\n     sprintf(msg,\"Can't control %s, please try again.\\n\",device);\n     serror(msg,1);\n   }\n   setenv(\"COMGTDEVICE\",device,1);\n-  ioctl(comfd, TCGETA, &stbuf);\n+  ioctl(comfd, TCGETS, &stbuf);\n   speed=stbuf.c_cflag & CBAUD;\n   if (high_speed == 0)  strcpy(cspeed,\"115200\");\n   else strcpy(cspeed,\"57600\");\n@@ -1303,11 +1303,11 @@ void opendevice(void) {\n   }\n   else comfd=0;\n \n-  if (ioctl (comfd, TCGETA, &svbuf) < 0) {\n+  if (ioctl (comfd, TCGETS, &svbuf) < 0) {\n     sprintf(msg,\"Can't ioctl get device %s.\\n\",device);\n     serror(msg,1);\n   }\n-  ioctl(comfd, TCGETA, &stbuf);\n+  ioctl(comfd, TCGETS, &stbuf);\n   speed=stbuf.c_cflag & CBAUD;\n   switch(speed) {\n     case B0: strcpy(cspeed,\"0\");break;\n@@ -1553,7 +1553,7 @@ int main(int argc,char **argv) {\n   skip_default=0;\n   filep=NULL;\n   scriptspace=4096;\n-  ioctl(1, TCGETA, &cons);\n+  ioctl(1, TCGETS, &cons);\n   if((script=( char *)malloc(scriptspace))==NULL) {\n     serror(\"Could not malloc()\",3);\n   }\n"
  },
  {
    "path": "package/network/utils/comgt/patches/003-no_XCASE.patch",
    "content": "--- a/comgt.c\n+++ b/comgt.c\n@@ -1281,7 +1281,7 @@ void opengt(void) {\n   parity=stbuf.c_cflag & (PARENB | PARODD);\n   stbuf.c_iflag &= ~(IGNCR | ICRNL | IUCLC | INPCK | IXON | IXANY | IGNPAR );\n   stbuf.c_oflag &= ~(OPOST | OLCUC | OCRNL | ONLCR | ONLRET);\n-  stbuf.c_lflag &= ~(ICANON | XCASE | ECHO | ECHOE | ECHONL);\n+  stbuf.c_lflag &= ~(ICANON | ECHO | ECHOE | ECHONL);\n   stbuf.c_lflag &= ~(ECHO | ECHOE);\n   stbuf.c_cc[VMIN] = 1;\n   stbuf.c_cc[VTIME] = 0;\n@@ -1336,7 +1336,7 @@ void opendevice(void) {\n   parity=stbuf.c_cflag & (PARENB | PARODD);\n   stbuf.c_iflag &= ~(IGNCR | ICRNL | IUCLC | INPCK | IXON | IXANY | IGNPAR );\n   stbuf.c_oflag &= ~(OPOST | OLCUC | OCRNL | ONLCR | ONLRET);\n-  stbuf.c_lflag &= ~(ICANON | XCASE | ECHO | ECHOE | ECHONL);\n+  stbuf.c_lflag &= ~(ICANON | ECHO | ECHOE | ECHONL);\n   stbuf.c_lflag &= ~(ECHO | ECHOE);\n   stbuf.c_cc[VMIN] = 1;\n   stbuf.c_cc[VTIME] = 0;\n"
  },
  {
    "path": "package/network/utils/comgt/patches/004-check_tty.patch",
    "content": "--- a/comgt.c\n+++ b/comgt.c\n@@ -91,6 +91,7 @@ unsigned long hstart,hset;\n char NullString[]={ \"\" };\n BOOL lastcharnl=1; /* Indicate that last char printed from getonebyte\n                                was a nl, so no new one is needed */\n+BOOL tty=1;\n \n \n //\"open com \\\"/dev/modem\\\"\\nset com 38400n81\\nset senddelay 0.05\\nsend \\\"ATi^m\\\"\\nget 2 \\\" ^m\\\" $s\\nprint \\\"Response : \\\",$s,\\\"\\\\n\\\"\\nget 2 \\\" ^m\\\" $s\\nprint \\\"Response :\\\",$s,\\\"\\\\n\\\"\\nget 2 \\\" ^m\\\" $s\\nprint \\\"Response : \\\",$s,\\\"\\\\n\\\"\\n\\n\";\n@@ -920,7 +921,7 @@ BOOL getonoroff(void) {\n void setcom(void) {\n   stbuf.c_cflag &= ~(CBAUD | CSIZE | CSTOPB | CLOCAL | PARENB);\n   stbuf.c_cflag |= (speed | bits | CREAD | clocal | parity | stopbits );\n-  if (ioctl(comfd, TCSETS, &stbuf) < 0) {\n+  if (tty && ioctl(comfd, TCSETS, &stbuf) < 0) {\n     serror(\"Can't ioctl set device\",1);\n   }\n }\n@@ -1224,7 +1225,7 @@ void doclose(void) {\n   if(strcmp(token,\"hardcom\")==0) {\n     if(comfd== -1) serror(\"Com device not open\",1);\n     vmsg(\"Closing device\");\n-    if (ioctl(comfd, TCSETS, &svbuf) < 0) {\n+    if (tty && ioctl(comfd, TCSETS, &svbuf) < 0) {\n       sprintf(msg,\"Can't ioctl set device %s.\\n\",device);\n       serror(msg,1);\n     }\n@@ -1266,12 +1267,17 @@ void opengt(void) {\n       ext(1);\n     }\n   }\n-  if (ioctl (comfd, TCGETS, &svbuf) < 0) {\n+  if (isatty (comfd))\n+    tty=1;\n+  else\n+    tty=0;\n+  if (tty && ioctl (comfd, TCGETS, &svbuf) < 0) {\n     sprintf(msg,\"Can't control %s, please try again.\\n\",device);\n     serror(msg,1);\n   }\n   setenv(\"COMGTDEVICE\",device,1);\n-  ioctl(comfd, TCGETS, &stbuf);\n+  if (tty)\n+    ioctl(comfd, TCGETS, &stbuf);\n   speed=stbuf.c_cflag & CBAUD;\n   if (high_speed == 0)  strcpy(cspeed,\"115200\");\n   else strcpy(cspeed,\"57600\");\n@@ -1302,12 +1308,16 @@ void opendevice(void) {\n     }\n   }\n   else comfd=0;\n-\n-  if (ioctl (comfd, TCGETS, &svbuf) < 0) {\n+  if (isatty (comfd))\n+    tty=1;\n+  else\n+    tty=0;\n+  if (tty && ioctl (comfd, TCGETS, &svbuf) < 0) {\n     sprintf(msg,\"Can't ioctl get device %s.\\n\",device);\n     serror(msg,1);\n   }\n-  ioctl(comfd, TCGETS, &stbuf);\n+  if (tty)\n+    ioctl(comfd, TCGETS, &stbuf);\n   speed=stbuf.c_cflag & CBAUD;\n   switch(speed) {\n     case B0: strcpy(cspeed,\"0\");break;\n"
  },
  {
    "path": "package/network/utils/ebtables/Makefile",
    "content": "#\n# Copyright (C) 2006-2015 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=ebtables\nPKG_SOURCE_DATE:=2018-06-27\nPKG_RELEASE:=1\n\nPKG_SOURCE_URL:=https://git.netfilter.org/ebtables\nPKG_SOURCE_PROTO:=git\nPKG_SOURCE_VERSION:=48cff25dfea5b37e16ba5dc6601e98ab140f5f99\nPKG_MIRROR_HASH:=1327cdc3402e5e3056819e4e9b6f9d4a5bfd401f2c4f58447afb2c3c73fc8aac\n\nPKG_LICENSE:=GPL-2.0\n\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine Package/ebtables-legacy\n  SECTION:=net\n  CATEGORY:=Network\n  SUBMENU:=Firewall\n  DEPENDS:=+kmod-ebtables\n  TITLE:=Ethernet bridge firewall administration utility\n  URL:=http://ebtables.sourceforge.net/\n  PROVIDES:=ebtables\n  ALTERNATIVES:=\\\n    200:/usr/sbin/ebtables:/usr/sbin/ebtables-legacy\nendef\n\ndefine Package/ebtables-legacy-utils\n  $(call Package/ebtables-legacy)\n  DEPENDS:=ebtables-legacy\n  TITLE:=ebtables save/restore utilities\n  PROVIDES:=ebtables-utils\n  ALTERNATIVES:=\\\n    200:/usr/sbin/ebtables-restore:/usr/sbin/ebtables-legacy-restore\nendef\n\ndefine Package/ebtables-legacy/description\n\tThe ebtables program is a filtering tool for a bridging firewall. The\n\tfiltering is focussed on the Link Layer Ethernet frame fields. Apart\n\tfrom filtering, it also gives the ability to alter the Ethernet MAC\n\taddresses and implement a brouter.\nendef\n\ndefine Package/ebtables-legacy-utils/description\n\t$(call Package/ebtables-legacy/description)\nendef\n\nMAKE_VARS += EXT_LIBSI=\"$(LIBGCC_S)\"\n\nMAKE_FLAGS += \\\n\tCFLAGS=\"$(TARGET_CFLAGS)\" \\\n\tLIBDIR=\"/usr/lib/ebtables\"\n\ndefine Package/ebtables-legacy/install\n\t$(INSTALL_DIR) $(1)/etc\n\t$(INSTALL_DATA) $(PKG_BUILD_DIR)/ethertypes $(1)/etc/\n\t$(INSTALL_DIR) $(1)/usr/lib/ebtables\n\t$(INSTALL_BIN) $(PKG_BUILD_DIR)/lib*.so $(1)/usr/lib/\n\t$(INSTALL_BIN) $(PKG_BUILD_DIR)/extensions/*.so $(1)/usr/lib/ebtables/\n\t$(INSTALL_DIR) $(1)/usr/sbin\n\t$(INSTALL_BIN) $(PKG_BUILD_DIR)/ebtables $(1)/usr/sbin/ebtables-legacy\nendef\n\ndefine Package/ebtables-legacy-utils/install\n\t$(INSTALL_DIR) $(1)/usr/sbin\n\t#ebtables-save depends on perl and is just broken\n\t#$(INSTALL_BIN) $(PKG_BUILD_DIR)/ebtables-save $(1)/usr/sbin/ebtables-legacy-save\n\t$(INSTALL_BIN) $(PKG_BUILD_DIR)/ebtables-restore $(1)/usr/sbin/ebtables-legacy-restore\nendef\n\n$(eval $(call BuildPackage,ebtables-legacy))\n$(eval $(call BuildPackage,ebtables-legacy-utils))\n"
  },
  {
    "path": "package/network/utils/ebtables/patches/100-musl_fix.patch",
    "content": "--- a/include/ebtables_u.h\n+++ b/include/ebtables_u.h\n@@ -23,6 +23,7 @@\n \n #ifndef EBTABLES_U_H\n #define EBTABLES_U_H\n+#define _NETINET_IF_ETHER_H\n #include <netinet/in.h>\n #include <netinet/ether.h>\n #include <linux/netfilter_bridge/ebtables.h>\n"
  },
  {
    "path": "package/network/utils/ebtables/patches/200-fix-extension-init.patch",
    "content": "--- a/extensions/Makefile\n+++ b/extensions/Makefile\n@@ -11,13 +11,13 @@ EXT_LIBSI+=$(foreach T,$(EXT_FUNC), -leb\n EXT_LIBSI+=$(foreach T,$(EXT_TABLES), -lebtable_$(T))\n \n extensions/ebt_%.so: extensions/ebt_%.o\n-\t$(CC) $(LDFLAGS) -shared -o $@ -lc $< -nostartfiles\n+\t$(CC) $(LDFLAGS) -shared -o $@ -lc $<\n \n extensions/libebt_%.so: extensions/ebt_%.so\n \tmv $< $@\n \n extensions/ebtable_%.so: extensions/ebtable_%.o\n-\t$(CC) $(LDFLAGS) -shared -o $@ -lc $< -nostartfiles\n+\t$(CC) $(LDFLAGS) -shared -o $@ -lc $<\n \n extensions/libebtable_%.so: extensions/ebtable_%.so\n \tmv $< $@\n--- a/extensions/ebt_802_3.c\n+++ b/extensions/ebt_802_3.c\n@@ -141,7 +141,7 @@ static struct ebt_u_match _802_3_match =\n \t.extra_ops\t= opts,\n };\n \n-void _init(void)\n+__attribute__((constructor)) static void extension_init(void)\n {\n \tebt_register_match(&_802_3_match);\n }\n--- a/extensions/ebt_among.c\n+++ b/extensions/ebt_among.c\n@@ -491,7 +491,7 @@ static struct ebt_u_match among_match =\n \t.extra_ops \t= opts,\n };\n \n-void _init(void)\n+__attribute__((constructor)) static void extension_init(void)\n {\n \tebt_register_match(&among_match);\n }\n--- a/extensions/ebt_arp.c\n+++ b/extensions/ebt_arp.c\n@@ -362,7 +362,7 @@ static struct ebt_u_match arp_match =\n \t.extra_ops\t= opts,\n };\n \n-void _init(void)\n+__attribute__((constructor)) static void extension_init(void)\n {\n \tebt_register_match(&arp_match);\n }\n--- a/extensions/ebt_arpreply.c\n+++ b/extensions/ebt_arpreply.c\n@@ -133,7 +133,7 @@ static struct ebt_u_target arpreply_targ\n \t.extra_ops\t= opts,\n };\n \n-void _init(void)\n+__attribute__((constructor)) static void extension_init(void)\n {\n \tebt_register_target(&arpreply_target);\n }\n--- a/extensions/ebt_ip.c\n+++ b/extensions/ebt_ip.c\n@@ -472,7 +472,7 @@ static struct ebt_u_match ip_match =\n \t.extra_ops\t= opts,\n };\n \n-void _init(void)\n+__attribute__((constructor)) static void extension_init(void)\n {\n \tebt_register_match(&ip_match);\n }\n--- a/extensions/ebt_ip6.c\n+++ b/extensions/ebt_ip6.c\n@@ -413,7 +413,7 @@ static struct ebt_u_match ip6_match =\n \t.extra_ops\t= opts,\n };\n \n-void _init(void)\n+__attribute__((constructor)) static void extension_init(void)\n {\n \tebt_register_match(&ip6_match);\n }\n--- a/extensions/ebt_limit.c\n+++ b/extensions/ebt_limit.c\n@@ -212,7 +212,7 @@ static struct ebt_u_match limit_match =\n \t.extra_ops\t= opts,\n };\n \n-void _init(void)\n+__attribute__((constructor)) static void extension_init(void)\n {\n \tebt_register_match(&limit_match);\n }\n--- a/extensions/ebt_log.c\n+++ b/extensions/ebt_log.c\n@@ -217,7 +217,7 @@ static struct ebt_u_watcher log_watcher\n \t.extra_ops\t= opts,\n };\n \n-void _init(void)\n+__attribute__((constructor)) static void extension_init(void)\n {\n \tebt_register_watcher(&log_watcher);\n }\n--- a/extensions/ebt_mark.c\n+++ b/extensions/ebt_mark.c\n@@ -172,7 +172,7 @@ static struct ebt_u_target mark_target =\n \t.extra_ops\t= opts,\n };\n \n-void _init(void)\n+__attribute__((constructor)) static void extension_init(void)\n {\n \tebt_register_target(&mark_target);\n }\n--- a/extensions/ebt_mark_m.c\n+++ b/extensions/ebt_mark_m.c\n@@ -121,7 +121,7 @@ static struct ebt_u_match mark_match =\n \t.extra_ops\t= opts,\n };\n \n-void _init(void)\n+__attribute__((constructor)) static void extension_init(void)\n {\n \tebt_register_match(&mark_match);\n }\n--- a/extensions/ebt_nat.c\n+++ b/extensions/ebt_nat.c\n@@ -231,7 +231,7 @@ static struct ebt_u_target dnat_target =\n \t.extra_ops\t= opts_d,\n };\n \n-void _init(void)\n+__attribute__((constructor)) static void extension_init(void)\n {\n \tebt_register_target(&snat_target);\n \tebt_register_target(&dnat_target);\n--- a/extensions/ebt_nflog.c\n+++ b/extensions/ebt_nflog.c\n@@ -166,7 +166,7 @@ static struct ebt_u_watcher nflog_watche\n \t.extra_ops = nflog_opts,\n };\n \n-void _init(void)\n+__attribute__((constructor)) static void extension_init(void)\n {\n \tebt_register_watcher(&nflog_watcher);\n }\n--- a/extensions/ebt_pkttype.c\n+++ b/extensions/ebt_pkttype.c\n@@ -125,7 +125,7 @@ static struct ebt_u_match pkttype_match\n \t.extra_ops\t= opts,\n };\n \n-void _init(void)\n+__attribute__((constructor)) static void extension_init(void)\n {\n \tebt_register_match(&pkttype_match);\n }\n--- a/extensions/ebt_redirect.c\n+++ b/extensions/ebt_redirect.c\n@@ -108,7 +108,7 @@ static struct ebt_u_target redirect_targ\n \t.extra_ops\t= opts,\n };\n \n-void _init(void)\n+__attribute__((constructor)) static void extension_init(void)\n {\n \tebt_register_target(&redirect_target);\n }\n--- a/extensions/ebt_standard.c\n+++ b/extensions/ebt_standard.c\n@@ -84,7 +84,7 @@ static struct ebt_u_target standard =\n \t.extra_ops\t= opts,\n };\n \n-void _init(void)\n+__attribute__((constructor)) static void extension_init(void)\n {\n \tebt_register_target(&standard);\n }\n--- a/extensions/ebt_stp.c\n+++ b/extensions/ebt_stp.c\n@@ -337,7 +337,7 @@ static struct ebt_u_match stp_match =\n \t.extra_ops\t= opts,\n };\n \n-void _init(void)\n+__attribute__((constructor)) static void extension_init(void)\n {\n \tebt_register_match(&stp_match);\n }\n--- a/extensions/ebt_ulog.c\n+++ b/extensions/ebt_ulog.c\n@@ -180,7 +180,7 @@ static struct ebt_u_watcher ulog_watcher\n \t.extra_ops\t= opts,\n };\n \n-void _init(void)\n+__attribute__((constructor)) static void extension_init(void)\n {\n \tebt_register_watcher(&ulog_watcher);\n }\n--- a/extensions/ebt_vlan.c\n+++ b/extensions/ebt_vlan.c\n@@ -181,7 +181,7 @@ static struct ebt_u_match vlan_match = {\n \t.extra_ops\t= opts,\n };\n \n-void _init(void)\n+__attribute__((constructor)) static void extension_init(void)\n {\n \tebt_register_match(&vlan_match);\n }\n--- a/extensions/ebtable_broute.c\n+++ b/extensions/ebtable_broute.c\n@@ -23,7 +23,7 @@ ebt_u_table table =\n \t.help\t\t= print_help,\n };\n \n-void _init(void)\n+__attribute__((constructor)) static void extension_init(void)\n {\n \tebt_register_table(&table);\n }\n--- a/extensions/ebtable_filter.c\n+++ b/extensions/ebtable_filter.c\n@@ -29,7 +29,7 @@ static struct ebt_u_table table =\n \t.help\t\t= print_help,\n };\n \n-void _init(void)\n+__attribute__((constructor)) static void extension_init(void)\n {\n \tebt_register_table(&table);\n }\n--- a/extensions/ebtable_nat.c\n+++ b/extensions/ebtable_nat.c\n@@ -30,7 +30,7 @@ ebt_u_table table =\n \t.help\t\t= print_help,\n };\n \n-void _init(void)\n+__attribute__((constructor)) static void extension_init(void)\n {\n \tebt_register_table(&table);\n }\n--- a/extensions/ebt_string.c\n+++ b/extensions/ebt_string.c\n@@ -312,7 +312,7 @@ static struct ebt_u_match string_match =\n \t.extra_ops\t= opts,\n };\n \n-void _init(void)\n+__attribute__((constructor)) static void extension_init(void)\n {\n \tebt_register_match(&string_match);\n }\n"
  },
  {
    "path": "package/network/utils/ethtool/Makefile",
    "content": "#\n# Copyright (C) 2006-2014 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=ethtool\nPKG_VERSION:=5.16\nPKG_RELEASE:=1\n\nPKG_MAINTAINER:=Felix Fietkau <nbd@nbd.name>\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz\nPKG_SOURCE_URL:=@KERNEL/software/network/ethtool\nPKG_HASH:=aa2fef1936dd4a11755dfa0bdb93f0ec5bea45208d27c9754bc3abe1aa42c1cb\n\nPKG_LICENSE:=GPL-2.0\nPKG_LICENSE_FILES:=COPYING\n\nPKG_FIXUP:=autoreconf\nPKG_INSTALL:=1\nPKG_BUILD_PARALLEL:=1\n\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine Package/ethtool\n  SECTION:=net\n  CATEGORY:=Network\n  TITLE:=Display or change ethernet card settings\n  URL:=http://www.kernel.org/pub/software/network/ethtool/\n  VARIANT:=tiny\n  CONFLICTS:=ethtool-full\nendef\n\ndefine Package/ethtool-full\n  $(Package/ethtool)\n  TITLE += (full)\n  VARIANT:=full\n  PROVIDES:=ethtool\n  DEPENDS:=+libmnl\n  CONFLICTS:=\nendef\n\ndefine Package/ethtool/description\n ethtool is a small utility for examining and tuning your ethernet-based\n network interface\nendef\n\nPackage/ethtool-full/description:=$(Package/ethtool/description)\n\nifeq ($(BUILD_VARIANT),full)\nCONFIGURE_ARGS += --enable-netlink --enable-pretty-dump\nelse\nCONFIGURE_ARGS += --disable-netlink --disable-pretty-dump\nendif\n\ndefine Package/ethtool/install\n\t$(INSTALL_DIR) $(1)/usr/sbin\n\t$(INSTALL_BIN) $(PKG_BUILD_DIR)/ethtool $(1)/usr/sbin\nendef\n\nPackage/ethtool-full/install=$(Package/ethtool/install)\n\n$(eval $(call BuildPackage,ethtool))\n$(eval $(call BuildPackage,ethtool-full))\n"
  },
  {
    "path": "package/network/utils/iproute2/Makefile",
    "content": "#\n# Copyright (C) 2006-2015 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=iproute2\nPKG_VERSION:=5.15.0\nPKG_RELEASE:=$(AUTORELEASE)\n\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz\nPKG_SOURCE_URL:=@KERNEL/linux/utils/net/iproute2\nPKG_HASH:=38e3e4a5f9a7f5575c015027a10df097c149111eeb739993128e5b2b35b291ff\nPKG_BUILD_PARALLEL:=1\nPKG_BUILD_DEPENDS:=iptables\nPKG_LICENSE:=GPL-2.0\nPKG_CPE_ID:=cpe:/a:iproute2_project:iproute2\n\ninclude $(INCLUDE_DIR)/kernel.mk\ninclude $(INCLUDE_DIR)/package.mk\ninclude $(INCLUDE_DIR)/nls.mk\n\ndefine Package/iproute2/Default\n  SECTION:=net\n  CATEGORY:=Network\n  URL:=http://www.linuxfoundation.org/collaborate/workgroups/networking/iproute2\n  SUBMENU:=Routing and Redirection\n  MAINTAINER:=Russell Senior <russell@personaltelco.net>\nendef\n\ndefine Package/ip-tiny\n$(call Package/iproute2/Default)\n  TITLE:=Routing control utility (minimal)\n  VARIANT:=iptiny\n  DEFAULT_VARIANT:=1\n  PROVIDES:=ip\n  ALTERNATIVES:=200:/sbin/ip:/usr/libexec/ip-tiny\n  DEPENDS:=+libnl-tiny +(PACKAGE_devlink||PACKAGE_rdma):libmnl\nendef\n\ndefine Package/ip-full\n$(call Package/iproute2/Default)\n  TITLE:=Routing control utility (full)\n  VARIANT:=ipfull\n  PROVIDES:=ip\n  ALTERNATIVES:=300:/sbin/ip:/usr/libexec/ip-full\n  DEPENDS:=+libnl-tiny +libbpf +(PACKAGE_devlink||PACKAGE_rdma):libmnl\nendef\n\ndefine Package/tc-tiny\n$(call Package/iproute2/Default)\n  TITLE:=Traffic control utility (minimal)\n  VARIANT:=tctiny\n  DEFAULT_VARIANT:=1\n  PROVIDES:=tc\n  ALTERNATIVES:=200:/sbin/tc:/usr/libexec/tc-tiny\n  DEPENDS:=+kmod-sched-core +(PACKAGE_devlink||PACKAGE_rdma):libmnl\nendef\n\ndefine Package/tc-bpf\n$(call Package/iproute2/Default)\n  TITLE:=Traffic control utility (bpf)\n  VARIANT:=tcbpf\n  PROVIDES:=tc\n  ALTERNATIVES:=300:/sbin/tc:/usr/libexec/tc-bpf\n  DEPENDS:=+kmod-sched-core +(PACKAGE_devlink||PACKAGE_rdma):libmnl +libbpf\nendef\n\ndefine Package/tc-full\n$(call Package/iproute2/Default)\n  TITLE:=Traffic control utility (full)\n  VARIANT:=tcfull\n  PROVIDES:=tc\n  ALTERNATIVES:=400:/sbin/tc:/usr/libexec/tc-full\n  DEPENDS:=+kmod-sched-core +(PACKAGE_devlink||PACKAGE_rdma):libmnl +libbpf +libxtables +tc-mod-iptables\nendef\n\ndefine Package/tc-mod-iptables\n$(call Package/iproute2/Default)\n  TITLE:=Traffic control module - iptables action\n  VARIANT:=tcfull\n  DEPENDS:=+libxtables\nendef\n\ndefine Package/genl\n$(call Package/iproute2/Default)\n  TITLE:=General netlink utility frontend\n  DEPENDS:=+libnl-tiny +(PACKAGE_devlink||PACKAGE_rdma):libmnl\nendef\n\ndefine Package/ip-bridge\n$(call Package/iproute2/Default)\n  TITLE:=Bridge configuration utility from iproute2\n  DEPENDS:=+libnl-tiny +(PACKAGE_devlink||PACKAGE_rdma):libmnl\nendef\n\ndefine Package/ss\n$(call Package/iproute2/Default)\n  TITLE:=Socket statistics utility\n  DEPENDS:=+libnl-tiny +(PACKAGE_devlink||PACKAGE_rdma):libmnl +kmod-netlink-diag\nendef\n\ndefine Package/nstat\n$(call Package/iproute2/Default)\n  TITLE:=Network statistics utility\n  DEPENDS:=+libnl-tiny +(PACKAGE_devlink||PACKAGE_rdma):libmnl\nendef\n\ndefine Package/devlink\n$(call Package/iproute2/Default)\n  TITLE:=Network devlink utility\n  DEPENDS:=+libmnl\nendef\n\ndefine Package/rdma\n$(call Package/iproute2/Default)\n  TITLE:=Network rdma utility\n  DEPENDS:=+libmnl\nendef\n\nifeq ($(BUILD_VARIANT),iptiny)\n  IP_CONFIG_TINY:=y\n  LIBBPF_FORCE:=off\nendif\n\nifeq ($(BUILD_VARIANT),ipfull)\n  HAVE_ELF:=y\n  LIBBPF_FORCE:=on\nendif\n\nifeq ($(BUILD_VARIANT),tctiny)\n  LIBBPF_FORCE:=off\nendif\n\nifeq ($(BUILD_VARIANT),tcbpf)\n  HAVE_ELF:=y\n  LIBBPF_FORCE:=on\n  SHARED_LIBS:=y\nendif\n\nifeq ($(BUILD_VARIANT),tcfull)\n  #enable iptables/xtables requirement only if tciptables variant is selected\n  TC_CONFIG_XT:=y\n  TC_CONFIG_XT_OLD:=y\n  TC_CONFIG_XT_OLD_H:=y\n  TC_CONFIG_IPSET:=y\n  HAVE_ELF:=y\n  LIBBPF_FORCE:=on\n  SHARED_LIBS:=y\nelse\n  #disable iptables requirement by default\n  TC_CONFIG_XT:=n\n  TC_CONFIG_XT_OLD:=n\n  TC_CONFIG_XT_OLD_H:=n\n  TC_CONFIG_IPSET:=n\nendif\n\nifdef CONFIG_PACKAGE_devlink\n  HAVE_MNL:=y\nendif\n\nifdef CONFIG_PACKAGE_rdma\n  HAVE_MNL:=y\nendif\n\ndefine Build/Configure\n\techo \"static const char SNAPSHOT[] = \\\"$(PKG_VERSION)-$(PKG_RELEASE)-openwrt\\\";\" \\\n\t\t> $(PKG_BUILD_DIR)/include/SNAPSHOT.h\nendef\n\nTARGET_CFLAGS += -ffunction-sections -fdata-sections -flto\nTARGET_LDFLAGS += -Wl,--gc-sections -Wl,--as-needed\nTARGET_CPPFLAGS += -I$(STAGING_DIR)/usr/include/libnl-tiny\n\nMAKE_FLAGS += \\\n\tKERNEL_INCLUDE=\"$(LINUX_DIR)/user_headers/include\" \\\n\tSHARED_LIBS=$(SHARED_LIBS) \\\n\tIP_CONFIG_TINY=$(IP_CONFIG_TINY) \\\n\tBUILD_VARIANT=$(BUILD_VARIANT) \\\n\tLIBBPF_FORCE=$(LIBBPF_FORCE) \\\n\tHAVE_ELF=$(HAVE_ELF) \\\n\tHAVE_MNL=$(HAVE_MNL) \\\n\tHAVE_CAP=$(HAVE_CAP) \\\n\tIPT_LIB_DIR=/usr/lib/iptables \\\n\tXT_LIB_DIR=/usr/lib/iptables \\\n\tTC_CONFIG_XT=$(TC_CONFIG_XT) \\\n\tTC_CONFIG_XT_OLD=$(TC_CONFIG_XT_OLD) \\\n\tTC_CONFIG_XT_OLD_H=$(TC_CONFIG_XT_OLD_H) \\\n\tTC_CONFIG_IPSET=$(TC_CONFIG_IPSET) \\\n\tFPIC=\"$(FPIC)\" \\\n\t$(if $(findstring c,$(OPENWRT_VERBOSE)),V=1,V='')\n\ndefine Build/Compile\n\t+$(MAKE_VARS) $(MAKE) $(PKG_JOBS) -C $(PKG_BUILD_DIR) $(MAKE_FLAGS)\nendef\n\ndefine Build/InstallDev\n\t$(INSTALL_DIR) $(1)/usr/include/iproute2\n\t$(CP) $(PKG_BUILD_DIR)/include/bpf_elf.h $(1)/usr/include/iproute2\n\t$(CP) $(PKG_BUILD_DIR)/include/{libgenl,libnetlink}.h $(1)/usr/include/\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(CP) $(PKG_BUILD_DIR)/lib/libnetlink.a $(1)/usr/lib/\nendef\n\ndefine Package/ip-tiny/install\n\t$(INSTALL_DIR) $(1)/usr/libexec\n\t$(INSTALL_BIN) $(PKG_BUILD_DIR)/ip/ip $(1)/usr/libexec/ip-tiny\nendef\n\ndefine Package/ip-full/install\n\t$(INSTALL_DIR) $(1)/usr/libexec\n\t$(INSTALL_BIN) $(PKG_BUILD_DIR)/ip/ip $(1)/usr/libexec/ip-full\nendef\n\ndefine Package/tc-tiny/install\n\t$(INSTALL_DIR) $(1)/usr/libexec\n\t$(INSTALL_BIN) $(PKG_BUILD_DIR)/tc/tc $(1)/usr/libexec/tc-tiny\nendef\n\ndefine Package/tc-bpf/install\n\t$(INSTALL_DIR) $(1)/usr/libexec\n\t$(INSTALL_BIN) $(PKG_BUILD_DIR)/tc/tc $(1)/usr/libexec/tc-bpf\nendef\n\ndefine Package/tc-full/install\n\t$(INSTALL_DIR) $(1)/usr/libexec\n\t$(INSTALL_BIN) $(PKG_BUILD_DIR)/tc/tc $(1)/usr/libexec/tc-full\nendef\n\ndefine Package/tc-mod-iptables/install\n\t$(INSTALL_DIR) $(1)/usr/lib/tc\n\t$(CP) $(PKG_BUILD_DIR)/tc/m_xt.so $(1)/usr/lib/tc\nendef\n\ndefine Package/genl/install\n\t$(INSTALL_DIR) $(1)/usr/sbin\n\t$(INSTALL_BIN) $(PKG_BUILD_DIR)/genl/genl $(1)/usr/sbin/\nendef\n\ndefine Package/ip-bridge/install\n\t$(INSTALL_DIR) $(1)/usr/sbin\n\t$(INSTALL_BIN) $(PKG_BUILD_DIR)/bridge/bridge $(1)/usr/sbin/\nendef\n\ndefine Package/ss/install\n\t$(INSTALL_DIR) $(1)/usr/sbin\n\t$(INSTALL_BIN) $(PKG_BUILD_DIR)/misc/ss $(1)/usr/sbin/\nendef\n\ndefine Package/nstat/install\n\t$(INSTALL_DIR) $(1)/usr/sbin\n\t$(INSTALL_BIN) $(PKG_BUILD_DIR)/misc/nstat $(1)/usr/sbin/\nendef\n\ndefine Package/devlink/install\n\t$(INSTALL_DIR) $(1)/usr/sbin\n\t$(INSTALL_BIN) $(PKG_BUILD_DIR)/devlink/devlink $(1)/usr/sbin/\nendef\n\ndefine Package/rdma/install\n\t$(INSTALL_DIR) $(1)/usr/sbin\n\t$(INSTALL_BIN) $(PKG_BUILD_DIR)/rdma/rdma $(1)/usr/sbin/\nendef\n\n$(eval $(call BuildPackage,ip-tiny))\n$(eval $(call BuildPackage,ip-full))\n# build tc-mod-iptables before its dependents, to avoid\n# spurious rebuilds when building multiple variants.\n$(eval $(call BuildPackage,tc-mod-iptables))\n$(eval $(call BuildPackage,tc-tiny))\n$(eval $(call BuildPackage,tc-bpf))\n$(eval $(call BuildPackage,tc-full))\n$(eval $(call BuildPackage,genl))\n$(eval $(call BuildPackage,ip-bridge))\n$(eval $(call BuildPackage,ss))\n$(eval $(call BuildPackage,nstat))\n$(eval $(call BuildPackage,devlink))\n$(eval $(call BuildPackage,rdma))\n"
  },
  {
    "path": "package/network/utils/iproute2/patches/100-configure.patch",
    "content": "--- a/configure\n+++ b/configure\n@@ -34,7 +34,8 @@ int main(int argc, char **argv) {\n }\n EOF\n \n-    if $CC -I$INCLUDE -o $TMPDIR/atmtest $TMPDIR/atmtest.c -latm >/dev/null 2>&1; then\n+# OpenWrt: disable ATM support even if present on host system\n+    if [ 1 -eq 0 ]; then\n \techo \"TC_CONFIG_ATM:=y\" >>$CONFIG\n \techo yes\n     else\n"
  },
  {
    "path": "package/network/utils/iproute2/patches/110-darwin_fixes.patch",
    "content": "--- a/netem/maketable.c\n+++ b/netem/maketable.c\n@@ -10,7 +10,9 @@\n #include <stdio.h>\n #include <stdlib.h>\n #include <math.h>\n+#if !defined(__APPLE__) && !defined(__FreeBSD__)\n #include <malloc.h>\n+#endif\n #include <string.h>\n #include <sys/types.h>\n #include <sys/stat.h>\n--- a/netem/normal.c\n+++ b/netem/normal.c\n@@ -8,8 +8,12 @@\n #include <string.h>\n #include <limits.h>\n \n+#if !defined(__APPLE__) && !defined(__FreeBSD__)\n #include <linux/types.h>\n #include <linux/pkt_sched.h>\n+#else\n+#define NETEM_DIST_SCALE        8192\n+#endif\n \n #define TABLESIZE 16384\n #define TABLEFACTOR NETEM_DIST_SCALE\n--- a/netem/pareto.c\n+++ b/netem/pareto.c\n@@ -7,8 +7,12 @@\n #include <math.h>\n #include <limits.h>\n \n+#if !defined(__APPLE__) && !defined(__FreeBSD__)\n #include <linux/types.h>\n #include <linux/pkt_sched.h>\n+#else\n+#define NETEM_DIST_SCALE        8192\n+#endif\n \n static const double a=3.0;\n #define TABLESIZE\t16384\n--- a/netem/paretonormal.c\n+++ b/netem/paretonormal.c\n@@ -14,10 +14,13 @@\n #include <string.h>\n #include <math.h>\n #include <limits.h>\n+#if !defined(__APPLE__) && !defined(__FreeBSD__)\n #include <malloc.h>\n-\n #include <linux/types.h>\n #include <linux/pkt_sched.h>\n+#else\n+#define NETEM_DIST_SCALE        8192\n+#endif\n \n #define TABLESIZE\t16384\n #define TABLEFACTOR\tNETEM_DIST_SCALE\n"
  },
  {
    "path": "package/network/utils/iproute2/patches/115-add-config-xtlibdir.patch",
    "content": "--- a/tc/Makefile\n+++ b/tc/Makefile\n@@ -128,6 +128,9 @@ CFLAGS += -DCONFIG_GACT -DCONFIG_GACT_PR\n ifneq ($(IPT_LIB_DIR),)\n \tCFLAGS += -DIPT_LIB_DIR=\\\"$(IPT_LIB_DIR)\\\"\n endif\n+ifneq ($(XT_LIB_DIR),)\n+\tCFLAGS += -DXT_LIB_DIR=\\\"$(XT_LIB_DIR)\\\"\n+endif\n \n LEX := flex\n CFLAGS += -DYY_NO_INPUT\n"
  },
  {
    "path": "package/network/utils/iproute2/patches/120-no_arpd_ifstat_rtacct_lnstat.patch",
    "content": "--- a/misc/Makefile\n+++ b/misc/Makefile\n@@ -2,13 +2,13 @@\n SSOBJ=ss.o ssfilter_check.o ssfilter.tab.o\n LNSTATOBJ=lnstat.o lnstat_util.o\n \n-TARGETS=ss nstat ifstat rtacct lnstat\n+TARGETS=ss nstat\n \n include ../config.mk\n \n-ifeq ($(HAVE_BERKELEY_DB),y)\n-\tTARGETS += arpd\n-endif\n+#ifeq ($(HAVE_BERKELEY_DB),y)\n+#\tTARGETS += arpd\n+#endif\n \n all: $(TARGETS)\n \n"
  },
  {
    "path": "package/network/utils/iproute2/patches/130-no_netem_tipc_dcb_man_vdpa.patch",
    "content": "--- a/Makefile\n+++ b/Makefile\n@@ -55,7 +55,7 @@ WFLAGS += -Wmissing-declarations -Wold-s\n CFLAGS := $(WFLAGS) $(CCOPTS) -I../include -I../include/uapi $(DEFINES) $(CFLAGS)\n YACCFLAGS = -d -t -v\n \n-SUBDIRS=lib ip tc bridge misc netem genl tipc devlink rdma dcb man vdpa\n+SUBDIRS=lib ip tc bridge misc genl devlink rdma\n \n LIBNETLINK=../lib/libutil.a ../lib/libnetlink.a\n LDLIBS += $(LIBNETLINK)\n"
  },
  {
    "path": "package/network/utils/iproute2/patches/140-allow_pfifo_fast.patch",
    "content": "--- a/tc/q_fifo.c\n+++ b/tc/q_fifo.c\n@@ -95,5 +95,6 @@ struct qdisc_util pfifo_head_drop_qdisc_\n \n struct qdisc_util pfifo_fast_qdisc_util = {\n \t.id = \"pfifo_fast\",\n+\t.parse_qopt = fifo_parse_opt,\n \t.print_qopt = prio_print_opt,\n };\n"
  },
  {
    "path": "package/network/utils/iproute2/patches/140-keep_libmnl_optional.patch",
    "content": "--- a/configure\n+++ b/configure\n@@ -387,7 +387,7 @@ check_selinux()\n \n check_mnl()\n {\n-\tif ${PKG_CONFIG} libmnl --exists; then\n+\tif [ \"${HAVE_MNL}\" = \"y\" ] && ${PKG_CONFIG} libmnl --exists; then\n \t\techo \"HAVE_MNL:=y\" >>$CONFIG\n \t\techo \"yes\"\n \n"
  },
  {
    "path": "package/network/utils/iproute2/patches/145-keep_libelf_optional.patch",
    "content": "--- a/configure\n+++ b/configure\n@@ -255,7 +255,7 @@ EOF\n \n check_elf()\n {\n-    if ${PKG_CONFIG} libelf --exists; then\n+    if [ \"${HAVE_ELF}\" = \"y\" ] && ${PKG_CONFIG} libelf --exists; then\n \techo \"HAVE_ELF:=y\" >>$CONFIG\n \techo \"yes\"\n \n"
  },
  {
    "path": "package/network/utils/iproute2/patches/150-keep_libcap_optional.patch",
    "content": "--- a/configure\n+++ b/configure\n@@ -445,7 +445,7 @@ EOF\n \n check_cap()\n {\n-\tif ${PKG_CONFIG} libcap --exists; then\n+\tif [ \"${HAVE_CAP}\" = \"y\" ] && ${PKG_CONFIG} libcap --exists; then\n \t\techo \"HAVE_CAP:=y\" >>$CONFIG\n \t\techo \"yes\"\n \n"
  },
  {
    "path": "package/network/utils/iproute2/patches/160-libnetlink-pic.patch",
    "content": "--- a/lib/Makefile\n+++ b/lib/Makefile\n@@ -1,7 +1,7 @@\n # SPDX-License-Identifier: GPL-2.0\n include ../config.mk\n \n-CFLAGS += -fPIC\n+CFLAGS += $(FPIC)\n \n UTILOBJ = utils.o utils_math.o rt_names.o ll_map.o ll_types.o ll_proto.o ll_addr.o \\\n \tinet_proto.o namespace.o json_writer.o json_print.o json_print_math.o \\\n"
  },
  {
    "path": "package/network/utils/iproute2/patches/170-ip_tiny.patch",
    "content": "--- a/ip/Makefile\n+++ b/ip/Makefile\n@@ -17,6 +17,13 @@ RTMONOBJ=rtmon.o\n \n include ../config.mk\n \n+STATIC_SYM_FILTER:=\n+ifeq ($(IP_CONFIG_TINY),y)\n+  STATIC_SYM_FILTER:=iplink_can.c iplink_ipoib.c iplink_vxlan.c\n+  CFLAGS += -DIPROUTE2_TINY\n+endif\n+STATIC_SYM_SOURCES:=$(filter-out $(STATIC_SYM_FILTER),$(wildcard *.c))\n+\n ALLOBJ=$(IPOBJ) $(RTMONOBJ)\n SCRIPTS=ifcfg rtpr routel routef\n TARGETS=ip rtmon\n@@ -46,7 +53,7 @@ else\n \n ip: static-syms.o\n static-syms.o: static-syms.h\n-static-syms.h: $(wildcard *.c)\n+static-syms.h: $(STATIC_SYM_SOURCES)\n \tfiles=\"$^\" ; \\\n \tfor s in `grep -B 3 '\\<dlsym' $$files | sed -n '/snprintf/{s:.*\"\\([^\"]*\\)\".*:\\1:;s:%s::;p}'` ; do \\\n \t\tsed -n '/'$$s'[^ ]* =/{s:.* \\([^ ]*'$$s'[^ ]*\\) .*:extern char \\1[] __attribute__((weak)); if (!strcmp(sym, \"\\1\")) return \\1;:;p}' $$files ; \\\n--- a/ip/ip.c\n+++ b/ip/ip.c\n@@ -64,11 +64,17 @@ static void usage(void)\n \tfprintf(stderr,\n \t\t\"Usage: ip [ OPTIONS ] OBJECT { COMMAND | help }\\n\"\n \t\t\"       ip [ -force ] -batch filename\\n\"\n+#ifndef IPROUTE2_TINY\n \t\t\"where  OBJECT := { address | addrlabel | fou | help | ila | ioam | l2tp | link |\\n\"\n \t\t\"                   macsec | maddress | monitor | mptcp | mroute | mrule |\\n\"\n \t\t\"                   neighbor | neighbour | netconf | netns | nexthop | ntable |\\n\"\n \t\t\"                   ntbl | route | rule | sr | tap | tcpmetrics |\\n\"\n \t\t\"                   token | tunnel | tuntap | vrf | xfrm }\\n\"\n+#else\n+\t\t\"where  OBJECT := { address | ila | link | macsec | maddress | monitor |\\n\"\n+\t\t\"                   mroute | mrule | neighbor | neighbour | netns | route |\\n\"\n+\t\t\"                   rule | sr | token | tunnel | vrf }\\n\"\n+#endif\n \t\t\"       OPTIONS := { -V[ersion] | -s[tatistics] | -d[etails] | -r[esolve] |\\n\"\n \t\t\"                    -h[uman-readable] | -iec | -j[son] | -p[retty] |\\n\"\n \t\t\"                    -f[amily] { inet | inet6 | mpls | bridge | link } |\\n\"\n@@ -91,37 +97,51 @@ static const struct cmd {\n \tint (*func)(int argc, char **argv);\n } cmds[] = {\n \t{ \"address\",\tdo_ipaddr },\n+#ifndef IPROUTE2_TINY\n \t{ \"addrlabel\",\tdo_ipaddrlabel },\n+#endif\n \t{ \"maddress\",\tdo_multiaddr },\n \t{ \"route\",\tdo_iproute },\n \t{ \"rule\",\tdo_iprule },\n \t{ \"neighbor\",\tdo_ipneigh },\n \t{ \"neighbour\",\tdo_ipneigh },\n+#ifndef IPROUTE2_TINY\n \t{ \"ntable\",\tdo_ipntable },\n \t{ \"ntbl\",\tdo_ipntable },\n+#endif\n \t{ \"link\",\tdo_iplink },\n+#ifndef IPROUTE2_TINY\n \t{ \"l2tp\",\tdo_ipl2tp },\n \t{ \"fou\",\tdo_ipfou },\n+#endif\n \t{ \"ila\",\tdo_ipila },\n \t{ \"macsec\",\tdo_ipmacsec },\n \t{ \"tunnel\",\tdo_iptunnel },\n \t{ \"tunl\",\tdo_iptunnel },\n+#ifndef IPROUTE2_TINY\n \t{ \"tuntap\",\tdo_iptuntap },\n \t{ \"tap\",\tdo_iptuntap },\n \t{ \"token\",\tdo_iptoken },\n \t{ \"tcpmetrics\",\tdo_tcp_metrics },\n \t{ \"tcp_metrics\", do_tcp_metrics },\n+#endif\n \t{ \"monitor\",\tdo_ipmonitor },\n+#ifndef IPROUTE2_TINY\n \t{ \"xfrm\",\tdo_xfrm },\n+#endif\n \t{ \"mroute\",\tdo_multiroute },\n \t{ \"mrule\",\tdo_multirule },\n \t{ \"netns\",\tdo_netns },\n+#ifndef IPROUTE2_TINY\n \t{ \"netconf\",\tdo_ipnetconf },\n+#endif\n \t{ \"vrf\",\tdo_ipvrf},\n \t{ \"sr\",\t\tdo_seg6 },\n+#ifndef IPROUTE2_TINY\n \t{ \"nexthop\",\tdo_ipnh },\n \t{ \"mptcp\",\tdo_mptcp },\n \t{ \"ioam\",\tdo_ioam6 },\n+#endif\n \t{ \"help\",\tdo_help },\n \t{ 0 }\n };\n--- a/lib/Makefile\n+++ b/lib/Makefile\n@@ -3,6 +3,10 @@ include ../config.mk\n \n CFLAGS += $(FPIC)\n \n+ifeq ($(IP_CONFIG_TINY),y)\n+  CFLAGS += -DIPROUTE2_TINY\n+endif\n+\n UTILOBJ = utils.o utils_math.o rt_names.o ll_map.o ll_types.o ll_proto.o ll_addr.o \\\n \tinet_proto.o namespace.o json_writer.o json_print.o json_print_math.o \\\n \tnames.o color.o bpf_legacy.o bpf_glue.o exec.o fs.o cg_map.o\n"
  },
  {
    "path": "package/network/utils/iproute2/patches/175-reduce-dynamic-syms.patch",
    "content": "--- a/tc/Makefile\n+++ b/tc/Makefile\n@@ -114,7 +114,7 @@ LDLIBS += -L. -lm\n \n ifeq ($(SHARED_LIBS),y)\n LDLIBS += -ldl\n-LDFLAGS += -Wl,-export-dynamic\n+LDFLAGS += -Wl,--dynamic-list=dynsyms.list\n endif\n \n TCLIB := tc_core.o\n@@ -144,7 +144,7 @@ MODDESTDIR := $(DESTDIR)$(LIBDIR)/tc\n all: tc $(TCSO)\n \n tc: $(TCOBJ) $(LIBNETLINK) libtc.a\n-\t$(QUIET_LINK)$(CC) $^ $(LDFLAGS) $(LDLIBS) -o $@\n+\t$(QUIET_LINK)$(CC) $(filter-out dynsyms.list, $^) $(LDFLAGS) $(LDLIBS) -o $@\n \n libtc.a: $(TCLIB)\n \t$(QUIET_AR)$(AR) rcs $@ $^\n@@ -166,6 +166,7 @@ install: all\n clean:\n \trm -f $(TCOBJ) $(TCLIB) libtc.a tc *.so emp_ematch.tab.h; \\\n \trm -f emp_ematch.tab.*\n+\trm -f dynsyms.list\n \n q_atm.so: q_atm.c\n \t$(QUIET_CC)$(CC) $(CFLAGS) $(CPPFLAGS) $(LDFLAGS) -shared -fpic -o q_atm.so q_atm.c -latm\n@@ -205,4 +206,16 @@ static-syms.h: $(wildcard *.c)\n \t\tsed -n '/'$$s'[^ ]* =/{s:.* \\([^ ]*'$$s'[^ ]*\\) .*:extern char \\1[] __attribute__((weak)); if (!strcmp(sym, \"\\1\")) return \\1;:;p}' $$files ; \\\n \tdone > $@\n \n+else\n+\n+tc: dynsyms.list\n+m_xt.so: dynsyms.list\n+dynsyms.list: $(wildcard *.c)\n+\tfiles=\"$(filter-out $(patsubst %.so,%.c,$(TCSO)), $^)\" ; \\\n+\techo \"{\" > $@ ; \\\n+\tfor s in `grep -B 3 '\\<dlsym' $$files | sed -n '/snprintf/{s:.*\"\\([^\"]*\\)\".*:\\1:;s:%s::;p}'` ; do \\\n+\t\tsed -n '/'$$s'[^ ]* =/{s:.* \\([^ ]*'$$s'[^ ]*\\) .*:\\1;:;p}' $$files ; \\\n+\tdone >> $@ ; \\\n+\techo \"show_stats; print_nl; print_tm; parse_rtattr; parse_rtattr_flags; get_u32; matches; addattr_l; addattr_nest; addattr_nest_end; };\" >> $@\n+\n endif\n"
  },
  {
    "path": "package/network/utils/iproute2/patches/180-drop_FAILED_POLICY.patch",
    "content": "From 4e7dbf76227e8c7be7897dc81def3011f637864d Mon Sep 17 00:00:00 2001\nFrom: Jonas Gorski <jogo@openwrt.org>\nDate: Thu, 30 May 2013 11:54:04 +0200\nSubject: [PATCH] add support for dropping with FAILED_POLICY\n\n---\n include/linux/fib_rules.h |    4 ++++\n include/linux/rtnetlink.h |    1 +\n ip/rtm_map.c              |    4 ++++\n 3 files changed, 9 insertions(+)\n\n--- a/ip/rtm_map.c\n+++ b/ip/rtm_map.c\n@@ -54,6 +54,8 @@ char *rtnl_rtntype_n2a(int id, char *buf\n \t\treturn \"nat\";\n \tcase RTN_XRESOLVE:\n \t\treturn \"xresolve\";\n+\tcase RTN_FAILED_POLICY:\n+\t\treturn \"failed_policy\";\n \tdefault:\n \t\tsnprintf(buf, len, \"%d\", id);\n \t\treturn buf;\n@@ -89,6 +91,8 @@ int rtnl_rtntype_a2n(int *id, char *arg)\n \t\tres = RTN_UNICAST;\n \telse if (strcmp(arg, \"throw\") == 0)\n \t\tres = RTN_THROW;\n+\telse if (strcmp(arg, \"failed_policy\") == 0)\n+\t\tres = RTN_FAILED_POLICY;\n \telse {\n \t\tres = strtoul(arg, &end, 0);\n \t\tif (!end || end == arg || *end || res > 255)\n--- a/include/uapi/linux/rtnetlink.h\n+++ b/include/uapi/linux/rtnetlink.h\n@@ -256,6 +256,7 @@ enum {\n \tRTN_THROW,\t\t/* Not in this table\t\t*/\n \tRTN_NAT,\t\t/* Translate this address\t*/\n \tRTN_XRESOLVE,\t\t/* Use external resolver\t*/\n+\tRTN_FAILED_POLICY,      /* Source address failed policy */\n \t__RTN_MAX\n };\n \n"
  },
  {
    "path": "package/network/utils/iproute2/patches/190-fix-nls-rpath-link.patch",
    "content": "--- a/configure\n+++ b/configure\n@@ -279,7 +279,7 @@ int main(int argc, char **argv) {\n }\n EOF\n \n-    $CC -o $TMPDIR/libbpf_test $TMPDIR/libbpf_test.c $LIBBPF_CFLAGS $LIBBPF_LDLIBS >/dev/null 2>&1\n+    $CC -o $TMPDIR/libbpf_test $TMPDIR/libbpf_test.c $LIBBPF_CFLAGS $LIBBPF_LDLIBS $LDFLAGS >/dev/null 2>&1\n     local ret=$?\n \n     rm -f $TMPDIR/libbpf_test.c $TMPDIR/libbpf_test\n@@ -297,7 +297,7 @@ int main(int argc, char **argv) {\n }\n EOF\n \n-    $CC -o $TMPDIR/libbpf_sec_test $TMPDIR/libbpf_sec_test.c $LIBBPF_CFLAGS $LIBBPF_LDLIBS >/dev/null 2>&1\n+    $CC -o $TMPDIR/libbpf_sec_test $TMPDIR/libbpf_sec_test.c $LIBBPF_CFLAGS $LIBBPF_LDLIBS $LDFLAGS >/dev/null 2>&1\n     local ret=$?\n \n     rm -f $TMPDIR/libbpf_sec_test.c $TMPDIR/libbpf_sec_test\n"
  },
  {
    "path": "package/network/utils/iproute2/patches/195-build_variant_ip_tc.patch",
    "content": "--- a/ip/Makefile\n+++ b/ip/Makefile\n@@ -26,7 +26,7 @@ STATIC_SYM_SOURCES:=$(filter-out $(STATI\n \n ALLOBJ=$(IPOBJ) $(RTMONOBJ)\n SCRIPTS=ifcfg rtpr routel routef\n-TARGETS=ip rtmon\n+TARGETS=$(findstring ip,$(BUILD_VARIANT)) rtmon\n \n all: $(TARGETS) $(SCRIPTS)\n \n--- a/tc/Makefile\n+++ b/tc/Makefile\n@@ -141,7 +141,7 @@ MODDESTDIR := $(DESTDIR)$(LIBDIR)/tc\n \t$(QUIET_CC)$(CC) $(CFLAGS) $(CPPFLAGS) $(LDFLAGS) -shared -fpic $< -o $@\n \n \n-all: tc $(TCSO)\n+all: $(findstring tc,$(BUILD_VARIANT)) $(TCSO)\n \n tc: $(TCOBJ) $(LIBNETLINK) libtc.a\n \t$(QUIET_LINK)$(CC) $(filter-out dynsyms.list, $^) $(LDFLAGS) $(LDLIBS) -o $@\n"
  },
  {
    "path": "package/network/utils/iproute2/patches/200-drop_libbsd_dependency.patch",
    "content": "--- a/configure\n+++ b/configure\n@@ -431,14 +431,8 @@ EOF\n     if $CC -I$INCLUDE -o $TMPDIR/strtest $TMPDIR/strtest.c >/dev/null 2>&1; then\n \techo \"no\"\n     else\n-\tif ${PKG_CONFIG} libbsd --exists; then\n-\t\techo 'CFLAGS += -DHAVE_LIBBSD' `${PKG_CONFIG} libbsd --cflags` >>$CONFIG\n-\t\techo 'LDLIBS +=' `${PKG_CONFIG} libbsd --libs` >> $CONFIG\n-\t\techo \"no\"\n-\telse\n-\t\techo 'CFLAGS += -DNEED_STRLCPY' >>$CONFIG\n-\t\techo \"yes\"\n-\tfi\n+\techo 'CFLAGS += -DNEED_STRLCPY' >>$CONFIG\n+\techo \"yes\"\n     fi\n     rm -f $TMPDIR/strtest.c $TMPDIR/strtest\n }\n"
  },
  {
    "path": "package/network/utils/iproute2/patches/300-selinux-configurable.patch",
    "content": "--- a/configure\n+++ b/configure\n@@ -374,7 +374,7 @@ check_libbpf()\n check_selinux()\n # SELinux is a compile time option in the ss utility\n {\n-\tif ${PKG_CONFIG} libselinux --exists; then\n+\tif [ \"${HAVE_SELINUX}\" = \"y\" ] && ${PKG_CONFIG} libselinux --exists; then\n \t\techo \"HAVE_SELINUX:=y\" >>$CONFIG\n \t\techo \"yes\"\n \n"
  },
  {
    "path": "package/network/utils/ipset/Makefile",
    "content": "\n# Copyright (C) 2009-2012 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n#\ninclude $(TOPDIR)/rules.mk\ninclude $(INCLUDE_DIR)/kernel.mk\n\nPKG_NAME:=ipset\nPKG_VERSION:=7.15\nPKG_RELEASE:=2\n\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.bz2\nPKG_SOURCE_URL:=http://ipset.netfilter.org\nPKG_HASH:=0a5545aaadb640142c1f888d366a78ddf8724799967fa20686a70053bd621751\n\nPKG_MAINTAINER:=Jo-Philipp Wich <jo@mein.io>\nPKG_LICENSE:=GPL-2.0\n\nPKG_FIXUP:=autoreconf\nPKG_INSTALL:=1\n\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine Package/ipset/Default\n  SECTION:=net\n  CATEGORY:=Network\n  DEPENDS+= +kmod-ipt-ipset +libmnl\n  TITLE:=IPset administration utility\n  URL:=http://ipset.netfilter.org/\nendef\n\ndefine Package/ipset\n$(call Package/ipset/Default)\n  DEPENDS+= +libipset\nendef\n\ndefine Package/libipset\n$(call Package/ipset/Default)\n  ABI_VERSION:=13\nendef\n\nCONFIGURE_ARGS += \\\n\t--disable-static \\\n\t--with-kbuild=\"$(LINUX_DIR)\"\n\nTARGET_LDFLAGS += -Wl,--gc-sections,--as-needed\n\nMAKE_FLAGS += \\\n\tARCH=\"$(LINUX_KARCH)\" \\\n\tSHELL=\"$(BASH)\"\n\ndefine Build/InstallDev\n\t$(INSTALL_DIR) $(1)/usr/include $(1)/usr/lib $(1)/usr/lib/pkgconfig\n\t$(CP) $(PKG_INSTALL_DIR)/usr/include/libipset $(1)/usr/include/\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/libipset.so* $(1)/usr/lib/\n\t$(CP) $(PKG_BUILD_DIR)/lib/libipset.pc $(1)/usr/lib/pkgconfig/\nendef\n\ndefine Package/ipset/install\n\t$(INSTALL_DIR) $(1)/usr/sbin\n\t$(CP) $(PKG_INSTALL_DIR)/usr/sbin/ipset $(1)/usr/sbin/\n\t$(CP) $(PKG_INSTALL_DIR)/usr/sbin/ipset-translate $(1)/usr/sbin/\nendef\n\ndefine Package/libipset/install\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/libipset*.so.* $(1)/usr/lib/\nendef\n\n$(eval $(call BuildPackage,libipset))\n$(eval $(call BuildPackage,ipset))\n"
  },
  {
    "path": "package/network/utils/ipset/patches/0001-lib-ipset-fix-printf-warning.patch",
    "content": "--- a/lib/ipset.c\n+++ b/lib/ipset.c\n@@ -1847,7 +1847,7 @@ static int ipset_xlate(struct ipset *ips\n \t\treturn -1;\n \tcase IPSET_CMD_LIST:\n \t\tif (!set) {\n-\t\t\tprintf(\"list sets %s\\n\",\n+\t\t\tprintf(\"list sets %s %s\\n\",\n \t\t\t       ipset_xlate_family(family), table);\n \t\t} else {\n \t\t\tprintf(\"list set %s %s %s\\n\",\n"
  },
  {
    "path": "package/network/utils/ipset/patches/0002-Fix-IPv6-sets-nftables-translation.patch",
    "content": "From 50ef784944c60cd291970c47e4b831ff7ef9c923 Mon Sep 17 00:00:00 2001\nFrom: Pablo Neira Ayuso <pablo@netfilter.org>\nDate: Mon, 28 Feb 2022 20:02:17 +0100\nSubject: [PATCH] Fix IPv6 sets nftables translation\n\nThe parser assumes the set is an IPv4 ipset because IPSET_OPT_FAMILY is\nnot set.\n\n # ipset-translate restore < ./ipset-mwan3_set_connected_ipv6.dump\n add table inet global\n add set inet global mwan3_connected_v6 { type ipv6_addr; flags interval; }\n flush set inet global mwan3_connected_v6\n ipset v7.15: Error in line 4: Syntax error: '64' is out of range 0-32\n\nRemove ipset_xlate_type_get(), call ipset_xlate_set_get() instead to\nobtain the set type and family.\n\nReported-by: Florian Eckert <fe@dev.tdt.de>\nFixes: 325af556cd3a (\"add ipset to nftables translation infrastructure\")\nSigned-off-by: Pablo Neira Ayuso <pablo@netfilter.org>\n---\n lib/ipset.c             | 24 ++++++++++--------------\n tests/xlate/xlate.t     |  2 ++\n tests/xlate/xlate.t.nft |  2 ++\n 3 files changed, 14 insertions(+), 14 deletions(-)\n\n--- a/lib/ipset.c\n+++ b/lib/ipset.c\n@@ -949,18 +949,6 @@ ipset_xlate_set_get(struct ipset *ipset,\n \treturn NULL;\n }\n \n-static const struct ipset_type *ipset_xlate_type_get(struct ipset *ipset,\n-\t\t\t\t\t\t     const char *name)\n-{\n-\tconst struct ipset_xlate_set *set;\n-\n-\tset = ipset_xlate_set_get(ipset, name);\n-\tif (!set)\n-\t\treturn NULL;\n-\n-\treturn set->type;\n-}\n-\n static int\n ipset_parser(struct ipset *ipset, int oargc, char *oargv[])\n {\n@@ -1282,8 +1270,16 @@ ipset_parser(struct ipset *ipset, int oa\n \t\tif (!ipset->xlate) {\n \t\t\ttype = ipset_type_get(session, cmd);\n \t\t} else {\n-\t\t\ttype = ipset_xlate_type_get(ipset, arg0);\n-\t\t\tipset_session_data_set(session, IPSET_OPT_TYPE, type);\n+\t\t\tconst struct ipset_xlate_set *xlate_set;\n+\n+\t\t\txlate_set = ipset_xlate_set_get(ipset, arg0);\n+\t\t\tif (xlate_set) {\n+\t\t\t\tipset_session_data_set(session, IPSET_OPT_TYPE,\n+\t\t\t\t\t\t       xlate_set->type);\n+\t\t\t\tipset_session_data_set(session, IPSET_OPT_FAMILY,\n+\t\t\t\t\t\t       &xlate_set->family);\n+\t\t\t\ttype = xlate_set->type;\n+\t\t\t}\n \t\t}\n \t\tif (type == NULL)\n \t\t\treturn ipset->standard_error(ipset, p);\n--- a/tests/xlate/xlate.t\n+++ b/tests/xlate/xlate.t\n@@ -53,3 +53,5 @@ create bp1 bitmap:port range 1-1024\n add bp1 22\n create bim1 bitmap:ip,mac range 1.1.1.0/24\n add bim1 1.1.1.1,aa:bb:cc:dd:ee:ff\n+create hn6 hash:net family inet6\n+add hn6 fe80::/64\n--- a/tests/xlate/xlate.t.nft\n+++ b/tests/xlate/xlate.t.nft\n@@ -54,3 +54,5 @@ add set inet global bp1 { type inet_serv\n add element inet global bp1 { 22 }\n add set inet global bim1 { type ipv4_addr . ether_addr; }\n add element inet global bim1 { 1.1.1.1 . aa:bb:cc:dd:ee:ff }\n+add set inet global hn6 { type ipv6_addr; flags interval; }\n+add element inet global hn6 { fe80::/64 }\n"
  },
  {
    "path": "package/network/utils/iptables/Makefile",
    "content": "#\n# Copyright (C) 2006-2016 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\ninclude $(INCLUDE_DIR)/kernel.mk\n\nPKG_NAME:=iptables\nPKG_VERSION:=1.8.7\nPKG_RELEASE:=6\n\nPKG_SOURCE_URL:=https://netfilter.org/projects/iptables/files\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.bz2\nPKG_HASH:=c109c96bb04998cd44156622d36f8e04b140701ec60531a10668cfdff5e8d8f0\n\nPKG_FIXUP:=autoreconf\nPKG_FLAGS:=nonshared\n\nPKG_INSTALL:=1\nPKG_BUILD_PARALLEL:=1\nPKG_LICENSE:=GPL-2.0\nPKG_CPE_ID:=cpe:/a:netfilter_core_team:iptables\n\ninclude $(INCLUDE_DIR)/package.mk\nifeq ($(DUMP),)\n  -include $(LINUX_DIR)/.config\n  include $(INCLUDE_DIR)/netfilter.mk\n  STAMP_CONFIGURED:=$(strip $(STAMP_CONFIGURED))_$(shell grep 'NETFILTER' $(LINUX_DIR)/.config | $(MKHASH) md5)\nendif\n\n\ndefine Package/iptables/Default\n  SECTION:=net\n  CATEGORY:=Network\n  SUBMENU:=Firewall\n  URL:=https://netfilter.org/\nendef\n\ndefine Package/iptables/Module\n$(call Package/iptables/Default)\n  DEPENDS:=+libxtables $(1)\nendef\n\ndefine Package/xtables-legacy\n$(call Package/iptables/Default)\n  TITLE:=IP firewall administration tool\n  DEPENDS+= +kmod-ipt-core +libip4tc +IPV6:libip6tc +libiptext +IPV6:libiptext6 +libxtables\nendef\n\ndefine Package/iptables-legacy\n$(call Package/iptables/Default)\n  TITLE:=IP firewall administration tool\n  DEPENDS+= +xtables-legacy\n  PROVIDES:=iptables\n  ALTERNATIVES:=\\\n    200:/usr/sbin/iptables:/usr/sbin/xtables-legacy-multi \\\n    200:/usr/sbin/iptables-restore:/usr/sbin/xtables-legacy-multi \\\n    200:/usr/sbin/iptables-save:/usr/sbin/xtables-legacy-multi\nendef\n\ndefine Package/iptables-legacy/description\nIP firewall administration tool.\n\n Matches:\n  - icmp\n  - tcp\n  - udp\n  - comment\n  - conntrack\n  - limit\n  - mac\n  - mark\n  - multiport\n  - set\n  - state\n  - time\n\n Targets:\n  - ACCEPT\n  - CT\n  - DNAT\n  - DROP\n  - REJECT\n  - FLOWOFFLOAD\n  - LOG\n  - MARK\n  - MASQUERADE\n  - REDIRECT\n  - SET\n  - SNAT\n  - TCPMSS\n\n Tables:\n  - filter\n  - mangle\n  - nat\n  - raw\n\nendef\n\ndefine Package/xtables-nft\n$(call Package/iptables/Default)\n  TITLE:=IP firewall administration tool nft\n  DEPENDS:=@IPTABLES_NFTABLES +libnftnl +libiptext +IPV6:libiptext6 +libiptext-nft +kmod-nft-compat\nendef\n\ndefine Package/arptables-nft\n$(call Package/iptables/Default)\n  DEPENDS:=+kmod-nft-arp +xtables-nft +kmod-arptables\n  TITLE:=ARP firewall administration tool nft\n  PROVIDES:=arptables\n  ALTERNATIVES:=\\\n    300:/usr/sbin/arptables:/usr/sbin/xtables-nft-multi \\\n    300:/usr/sbin/arptables-restore:/usr/sbin/xtables-nft-multi \\\n    300:/usr/sbin/arptables-save:/usr/sbin/xtables-nft-multi\nendef\n\ndefine Package/ebtables-nft\n$(call Package/iptables/Default)\n  DEPENDS:=+kmod-nft-bridge +xtables-nft +kmod-ebtables\n  TITLE:=Bridge firewall administration tool nft\n  PROVIDES:=ebtables\n  ALTERNATIVES:=\\\n    300:/usr/sbin/ebtables:/usr/sbin/xtables-nft-multi \\\n    300:/usr/sbin/ebtables-restore:/usr/sbin/xtables-nft-multi \\\n    300:/usr/sbin/ebtables-save:/usr/sbin/xtables-nft-multi\nendef\n\ndefine Package/iptables-nft\n$(call Package/iptables/Default)\n  TITLE:=IP firewall administration tool nft\n  DEPENDS:=+kmod-ipt-core +xtables-nft\n  PROVIDES:=iptables\n  ALTERNATIVES:=\\\n    300:/usr/sbin/iptables:/usr/sbin/xtables-nft-multi \\\n    300:/usr/sbin/iptables-restore:/usr/sbin/xtables-nft-multi \\\n    300:/usr/sbin/iptables-save:/usr/sbin/xtables-nft-multi\nendef\n\ndefine Package/iptables-nft/description\nExtra iptables nftables nft binaries.\n  iptables-nft\n  iptables-nft-restore\n  iptables-nft-save\n  iptables-translate\n  iptables-restore-translate\nendef\n\ndefine Package/iptables-mod-conntrack-extra\n$(call Package/iptables/Module, +kmod-ipt-conntrack-extra +kmod-ipt-raw)\n  TITLE:=Extra connection tracking extensions\nendef\n\ndefine Package/iptables-mod-conntrack-extra/description\nExtra iptables extensions for connection tracking.\n\n Matches:\n  - connbytes\n  - connlimit\n  - connmark\n  - recent\n  - helper\n\n Targets:\n  - CONNMARK\n\nendef\n\ndefine Package/iptables-mod-conntrack-label\n$(call Package/iptables/Module, +kmod-ipt-conntrack-label @IPTABLES_CONNLABEL)\n  TITLE:=Connection tracking labeling extension\n  DEFAULT:=y if IPTABLES_CONNLABEL\nendef\n\ndefine Package/iptables-mod-conntrack-label/description\nMatch and set label(s) on connection tracking entries\n\n Matches:\n  - connlabel\n\nendef\n\ndefine Package/iptables-mod-filter\n$(call Package/iptables/Module, +kmod-ipt-filter)\n  TITLE:=Content inspection extensions\nendef\n\ndefine Package/iptables-mod-filter/description\niptables extensions for packet content inspection.\nIncludes support for:\n\n Matches:\n  - string\n  - bpf\n\nendef\n\ndefine Package/iptables-mod-ipopt\n$(call Package/iptables/Module, +kmod-ipt-ipopt)\n  TITLE:=IP/Packet option extensions\nendef\n\ndefine Package/iptables-mod-ipopt/description\niptables extensions for matching/changing IP packet options.\n\n Matches:\n  - dscp\n  - ecn\n  - length\n  - statistic\n  - tcpmss\n  - unclean\n  - hl\n\n Targets:\n  - DSCP\n  - CLASSIFY\n  - ECN\n  - HL\n\nendef\n\ndefine Package/iptables-mod-ipsec\n$(call Package/iptables/Module, +kmod-ipt-ipsec)\n  TITLE:=IPsec extensions\nendef\n\ndefine Package/iptables-mod-ipsec/description\niptables extensions for matching ipsec traffic.\n\n Matches:\n  - ah\n  - esp\n  - policy\n\nendef\n\ndefine Package/iptables-mod-nat-extra\n$(call Package/iptables/Module, +kmod-ipt-nat-extra)\n  TITLE:=Extra NAT extensions\nendef\n\ndefine Package/iptables-mod-nat-extra/description\niptables extensions for extra NAT targets.\n\n Targets:\n  - MIRROR\n  - NETMAP\nendef\n\ndefine Package/iptables-mod-ulog\n$(call Package/iptables/Module, +kmod-ipt-ulog)\n  TITLE:=user-space packet logging\nendef\n\ndefine Package/iptables-mod-ulog/description\niptables extensions for user-space packet logging.\n\n Targets:\n  - ULOG\n\nendef\n\ndefine Package/iptables-mod-nflog\n$(call Package/iptables/Module, +kmod-nfnetlink-log +kmod-ipt-nflog)\n  TITLE:=Netfilter NFLOG target\nendef\n\ndefine Package/iptables-mod-nflog/description\n iptables extension for user-space logging via NFNETLINK.\n\n Includes:\n  - libxt_NFLOG\n\nendef\n\ndefine Package/iptables-mod-trace\n$(call Package/iptables/Module, +kmod-ipt-debug)\n  TITLE:=Netfilter TRACE target\nendef\n\ndefine Package/iptables-mod-trace/description\n iptables extension for TRACE target\n\n Includes:\n  - libxt_TRACE\n\nendef\n\n\ndefine Package/iptables-mod-nfqueue\n$(call Package/iptables/Module, +kmod-nfnetlink-queue +kmod-ipt-nfqueue)\n  TITLE:=Netfilter NFQUEUE target\nendef\n\ndefine Package/iptables-mod-nfqueue/description\n iptables extension for user-space queuing via NFNETLINK.\n\n Includes:\n  - libxt_NFQUEUE\n\nendef\n\ndefine Package/iptables-mod-hashlimit\n$(call Package/iptables/Module, +kmod-ipt-hashlimit)\n  TITLE:=hashlimit matching\nendef\n\ndefine Package/iptables-mod-hashlimit/description\niptables extensions for hashlimit matching\n\n Matches:\n  - hashlimit\n\nendef\n\ndefine Package/iptables-mod-rpfilter\n$(call Package/iptables/Module, +kmod-ipt-rpfilter)\n  TITLE:=rpfilter iptables extension\nendef\n\ndefine Package/iptables-mod-rpfilter/description\niptables extensions for reverse path filter test on a packet\n\n Matches:\n  - rpfilter\n\nendef\n\ndefine Package/iptables-mod-iprange\n$(call Package/iptables/Module, +kmod-ipt-iprange)\n  TITLE:=IP range extension\nendef\n\ndefine Package/iptables-mod-iprange/description\niptables extensions for matching ip ranges.\n\n Matches:\n  - iprange\n\nendef\n\ndefine Package/iptables-mod-cluster\n$(call Package/iptables/Module, +kmod-ipt-cluster)\n  TITLE:=Match cluster extension\nendef\n\ndefine Package/iptables-mod-cluster/description\niptables extensions for matching cluster.\n\n Netfilter (IPv4/IPv6) module for matching cluster\n This option allows you to build work-load-sharing clusters of\n network servers/stateful firewalls without having a dedicated\n load-balancing router/server/switch. Basically, this match returns\n true when the packet must be handled by this cluster node. Thus,\n all nodes see all packets and this match decides which node handles\n what packets. The work-load sharing algorithm is based on source\n address hashing.\n\n This module is usable for ipv4 and ipv6.\n\n If you select it, it enables kmod-ipt-cluster.\n\n see `iptables -m cluster --help` for more information.\nendef\n\ndefine Package/iptables-mod-clusterip\n$(call Package/iptables/Module, +kmod-ipt-clusterip)\n  TITLE:=Clusterip extension\nendef\n\ndefine Package/iptables-mod-clusterip/description\niptables extensions for CLUSTERIP.\n The CLUSTERIP target allows you to build load-balancing clusters of\n network servers without having a dedicated load-balancing\n router/server/switch.\n\n If you select it, it enables kmod-ipt-clusterip.\n\n see `iptables -j CLUSTERIP --help` for more information.\nendef\n\ndefine Package/iptables-mod-extra\n$(call Package/iptables/Module, +kmod-ipt-extra)\n  TITLE:=Other extra iptables extensions\nendef\n\ndefine Package/iptables-mod-extra/description\nOther extra iptables extensions.\n\n Matches:\n  - addrtype\n  - condition\n  - owner\n  - pkttype\n  - quota\n\nendef\n\ndefine Package/iptables-mod-physdev\n$(call Package/iptables/Module, +kmod-ipt-physdev)\n  TITLE:=physdev iptables extension\nendef\n\ndefine Package/iptables-mod-physdev/description\nThe iptables physdev match.\nendef\n\ndefine Package/iptables-mod-led\n$(call Package/iptables/Module, +kmod-ipt-led)\n  TITLE:=LED trigger iptables extension\nendef\n\ndefine Package/iptables-mod-led/description\niptables extension for triggering a LED.\n\n Targets:\n  - LED\n\nendef\n\ndefine Package/iptables-mod-socket\n$(call Package/iptables/Module, +kmod-ipt-socket)\n  TITLE:=Socket match iptables extensions\nendef\n\ndefine Package/iptables-mod-socket/description\nSocket match iptables extensions.\n\n Matches:\n  - socket\n\nendef\n\ndefine Package/iptables-mod-tproxy\n$(call Package/iptables/Module, +kmod-ipt-tproxy)\n  TITLE:=Transparent proxy iptables extensions\nendef\n\ndefine Package/iptables-mod-tproxy/description\nTransparent proxy iptables extensions.\n\n Targets:\n  - TPROXY\n\nendef\n\ndefine Package/iptables-mod-tee\n$(call Package/iptables/Module, +kmod-ipt-tee)\n  TITLE:=TEE iptables extensions\nendef\n\ndefine Package/iptables-mod-tee/description\nTEE iptables extensions.\n\n Targets:\n  - TEE\n\nendef\n\ndefine Package/iptables-mod-u32\n$(call Package/iptables/Module, +kmod-ipt-u32)\n  TITLE:=U32 iptables extensions\nendef\n\ndefine Package/iptables-mod-u32/description\nU32 iptables extensions.\n\n Matches:\n  - u32\n\nendef\n\ndefine Package/iptables-mod-checksum\n$(call Package/iptables/Module, +kmod-ipt-checksum)\n  TITLE:=IP CHECKSUM target extension\nendef\n\ndefine Package/iptables-mod-checksum/description\niptables extension for the CHECKSUM calculation target\nendef\n\ndefine Package/ip6tables-legacy\n$(call Package/iptables/Default)\n  DEPENDS:=@IPV6 +kmod-ip6tables +xtables-legacy\n  CATEGORY:=Network\n  TITLE:=IPv6 firewall administration tool\n  PROVIDES:=ip6tables\n  ALTERNATIVES:=\\\n    200:/usr/sbin/ip6tables:/usr/sbin/xtables-legacy-multi \\\n    200:/usr/sbin/ip6tables-restore:/usr/sbin/xtables-legacy-multi \\\n    200:/usr/sbin/ip6tables-save:/usr/sbin/xtables-legacy-multi\nendef\n\ndefine Package/ip6tables-nft\n$(call Package/iptables/Default)\n  DEPENDS:=@IPV6 +kmod-ip6tables +xtables-nft\n  TITLE:=IP firewall administration tool nft\n  PROVIDES:=ip6tables\n  ALTERNATIVES:=\\\n    300:/usr/sbin/ip6tables:/usr/sbin/xtables-nft-multi \\\n    300:/usr/sbin/ip6tables-restore:/usr/sbin/xtables-nft-multi \\\n    300:/usr/sbin/ip6tables-save:/usr/sbin/xtables-nft-multi\nendef\n\ndefine Package/ip6tables-nft/description\nExtra ip6tables nftables nft binaries.\n  ip6tables-nft\n  ip6tables-nft-restore\n  ip6tables-nft-save\n  ip6tables-translate\n  ip6tables-restore-translate\nendef\n\ndefine Package/ip6tables-extra\n$(call Package/iptables/Default)\n  DEPENDS:=+libxtables +kmod-ip6tables-extra\n  TITLE:=IPv6 header matching modules\nendef\n\ndefine Package/ip6tables-extra/description\niptables header matching modules for IPv6\nendef\n\ndefine Package/ip6tables-mod-nat\n$(call Package/iptables/Default)\n  DEPENDS:=+libxtables +kmod-ipt-nat6\n  TITLE:=IPv6 NAT extensions\nendef\n\ndefine Package/ip6tables-mod-nat/description\niptables extensions for IPv6-NAT targets.\nendef\n\ndefine Package/libip4tc\n$(call Package/iptables/Default)\n  SECTION:=libs\n  CATEGORY:=Libraries\n  TITLE:=IPv4 firewall - shared libiptc library\n  ABI_VERSION:=2\nendef\n\ndefine Package/libip6tc\n$(call Package/iptables/Default)\n  SECTION:=libs\n  CATEGORY:=Libraries\n  TITLE:=IPv6 firewall - shared libiptc library\n  ABI_VERSION:=2\nendef\n\ndefine Package/libiptext\n $(call Package/iptables/Default)\n SECTION:=libs\n CATEGORY:=Libraries\n TITLE:=IPv4 firewall - shared libiptext library\n ABI_VERSION:=0\n DEPENDS:=+libxtables\nendef\n\ndefine Package/libiptext6\n $(call Package/iptables/Default)\n SECTION:=libs\n CATEGORY:=Libraries\n TITLE:=IPv6 firewall - shared libiptext library\n ABI_VERSION:=0\n DEPENDS:=+libxtables\nendef\n\ndefine Package/libiptext-nft\n $(call Package/iptables/Default)\n SECTION:=libs\n CATEGORY:=Libraries\n TITLE:=IPv4/IPv6 firewall - shared libiptext nft library\n ABI_VERSION:=0\n DEPENDS:=@IPTABLES_NFTABLES +libxtables\nendef\n\ndefine Package/libxtables\n $(call Package/iptables/Default)\n SECTION:=libs\n CATEGORY:=Libraries\n TITLE:=IPv4/IPv6 firewall - shared xtables library\n MENU:=1\n ABI_VERSION:=12\n DEPENDS:=+IPTABLES_CONNLABEL:libnetfilter-conntrack\nendef\n\ndefine Package/libxtables/config\n  config IPTABLES_CONNLABEL\n\tbool \"Enable Connlabel support\"\n\tdefault n\n\thelp\n\t\tThis enable connlabel support in iptables.\n\n  config IPTABLES_NFTABLES\n\tbool \"Enable Nftables support\"\n\tdefault y\n\thelp\n\t\tThis enable nftables support in iptables.\nendef\n\nTARGET_CPPFLAGS := \\\n\t-I$(PKG_BUILD_DIR)/include \\\n\t-I$(LINUX_DIR)/user_headers/include \\\n\t$(TARGET_CPPFLAGS)\n\nTARGET_CFLAGS += \\\n\t-I$(PKG_BUILD_DIR)/include \\\n\t-I$(LINUX_DIR)/user_headers/include \\\n\t-ffunction-sections -fdata-sections \\\n\t-DNO_LEGACY\n\nTARGET_LDFLAGS += \\\n\t-Wl,--gc-sections\n\nCONFIGURE_ARGS += \\\n\t--enable-shared \\\n\t--enable-static \\\n\t--enable-devel \\\n\t--with-kernel=\"$(LINUX_DIR)/user_headers\" \\\n\t--with-xtlibdir=/usr/lib/iptables \\\n\t--with-xt-lock-name=/var/run/xtables.lock \\\n\t$(if $(CONFIG_IPTABLES_CONNLABEL),,--disable-connlabel) \\\n\t$(if $(CONFIG_IPTABLES_NFTABLES),,--disable-nftables) \\\n\t$(if $(CONFIG_IPV6),,--disable-ipv6)\n\nMAKE_FLAGS := \\\n\t$(TARGET_CONFIGURE_OPTS) \\\n\tCOPT_FLAGS=\"$(TARGET_CFLAGS)\" \\\n\tKERNEL_DIR=\"$(LINUX_DIR)/user_headers/\" PREFIX=/usr \\\n\tKBUILD_OUTPUT=\"$(LINUX_DIR)\" \\\n\tBUILTIN_MODULES=\"$(patsubst ip6t_%,%,$(patsubst ipt_%,%,$(patsubst xt_%,%,$(IPT_BUILTIN) $(IPT_CONNTRACK-m) $(IPT_NAT-m))))\"\n\nifneq ($(wildcard $(PKG_BUILD_DIR)/.config_*),$(subst .configured_,.config_,$(STAMP_CONFIGURED)))\n  define Build/Configure/rebuild\n\t$(FIND) $(PKG_BUILD_DIR) -name \\*.o -or -name \\*.\\?o -or -name \\*.a | $(XARGS) rm -f\n\trm -f $(PKG_BUILD_DIR)/.config_*\n\trm -f $(PKG_BUILD_DIR)/.configured_*\n\ttouch $(subst .configured_,.config_,$(STAMP_CONFIGURED))\n  endef\nendif\n\ndefine Build/Configure\n$(Build/Configure/rebuild)\n$(Build/Configure/Default)\nendef\n\ndefine Build/InstallDev\n\t$(INSTALL_DIR) $(1)/usr/include\n\t$(INSTALL_DIR) $(1)/usr/include/iptables\n\t$(INSTALL_DIR) $(1)/usr/include/net/netfilter\n\n\t# XXX: iptables header fixup, some headers are not installed by iptables anymore\n\t$(CP) $(PKG_BUILD_DIR)/include/iptables/*.h $(1)/usr/include/iptables/\n\t$(CP) $(PKG_BUILD_DIR)/include/iptables.h $(1)/usr/include/\n\t$(CP) $(PKG_BUILD_DIR)/include/ip6tables.h $(1)/usr/include/\n\t$(CP) $(PKG_BUILD_DIR)/include/libipulog $(1)/usr/include/\n\t$(CP) $(PKG_BUILD_DIR)/include/libiptc $(1)/usr/include/\n\n\t$(CP) $(PKG_INSTALL_DIR)/usr/include/* $(1)/usr/include/\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/libxtables.so* $(1)/usr/lib/\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/libip*tc.so* $(1)/usr/lib/\n\t$(INSTALL_DIR) $(1)/usr/lib/pkgconfig\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/pkgconfig/xtables.pc $(1)/usr/lib/pkgconfig/\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/pkgconfig/libip*tc.pc $(1)/usr/lib/pkgconfig/\n\n\t# XXX: needed by firewall3\n\t$(CP) $(PKG_BUILD_DIR)/extensions/libiptext*.so $(1)/usr/lib/\nendef\n\ndefine Package/xtables-legacy/install\n\t$(INSTALL_DIR) $(1)/usr/sbin\n\t$(CP) $(PKG_INSTALL_DIR)/usr/sbin/xtables-legacy-multi $(1)/usr/sbin/\nendef\n\ndefine Package/iptables-legacy/install\n\t$(INSTALL_DIR) $(1)/usr/sbin\n\t$(CP) $(PKG_INSTALL_DIR)/usr/sbin/iptables-legacy{,-restore,-save} $(1)/usr/sbin/\n\t$(INSTALL_DIR) $(1)/usr/lib/iptables\nendef\n\ndefine Package/xtables-nft/install\n\t$(INSTALL_DIR) $(1)/usr/sbin\n\t$(CP) $(PKG_INSTALL_DIR)/usr/sbin/xtables-nft-multi $(1)/usr/sbin/\nendef\n\ndefine Package/arptables-nft/install\n\t$(INSTALL_DIR) $(1)/usr/sbin\n\t$(CP) $(PKG_INSTALL_DIR)/usr/sbin/arptables-nft{,-restore,-save} $(1)/usr/sbin/\n\t$(INSTALL_DIR) $(1)/usr/lib/iptables\n\t$(CP) $(PKG_BUILD_DIR)/extensions/libarpt_*.so $(1)/usr/lib/iptables/\nendef\n\ndefine Package/ebtables-nft/install\n\t$(INSTALL_DIR) $(1)/usr/sbin\n\t$(CP) $(PKG_INSTALL_DIR)/usr/sbin/ebtables-nft{,-restore,-save} $(1)/usr/sbin/\n\t$(INSTALL_DIR) $(1)/usr/lib/iptables\n\t$(CP) $(PKG_BUILD_DIR)/extensions/libebt_*.so $(1)/usr/lib/iptables/\nendef\n\ndefine Package/iptables-nft/install\n\t$(INSTALL_DIR) $(1)/usr/sbin\n\t$(CP) $(PKG_INSTALL_DIR)/usr/sbin/iptables-nft{,-restore,-save} $(1)/usr/sbin/\n\t$(CP) $(PKG_INSTALL_DIR)/usr/sbin/iptables{,-restore}-translate $(1)/usr/sbin/\nendef\n\ndefine Package/ip6tables-legacy/install\n\t$(INSTALL_DIR) $(1)/usr/sbin\n\t$(CP) $(PKG_INSTALL_DIR)/usr/sbin/ip6tables-legacy{,-restore,-save} $(1)/usr/sbin/\nendef\n\ndefine Package/ip6tables-nft/install\n\t$(INSTALL_DIR) $(1)/usr/sbin\n\t$(CP) $(PKG_INSTALL_DIR)/usr/sbin/ip6tables-nft{,-restore,-save} $(1)/usr/sbin/\n\t$(CP) $(PKG_INSTALL_DIR)/usr/sbin/ip6tables{,-restore}-translate $(1)/usr/sbin/\nendef\n\ndefine Package/libip4tc/install\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/libip4tc.so.* $(1)/usr/lib/\nendef\n\ndefine Package/libip6tc/install\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/libip6tc.so.* $(1)/usr/lib/\nendef\n\ndefine Package/libiptext/install\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(CP) $(PKG_BUILD_DIR)/extensions/libiptext.so $(1)/usr/lib/\n\t$(CP) $(PKG_BUILD_DIR)/extensions/libiptext4.so $(1)/usr/lib/\nendef\n\ndefine Package/libiptext6/install\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(CP) $(PKG_BUILD_DIR)/extensions/libiptext6.so $(1)/usr/lib/\nendef\n\ndefine Package/libiptext-nft/install\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(CP) $(PKG_BUILD_DIR)/extensions/libiptext_*.so $(1)/usr/lib/\nendef\n\ndefine Package/libxtables/install\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/libxtables.so.* $(1)/usr/lib/\nendef\n\ndefine BuildPlugin\n  define Package/$(1)/install\n\t$(INSTALL_DIR) $$(1)/usr/lib/iptables\n\tfor m in $(patsubst xt_%,ipt_%,$(2)) $(patsubst ipt_%,xt_%,$(2)) $(patsubst xt_%,ip6t_%,$(2)) $(patsubst ip6t_%,xt_%,$(2)); do \\\n\t\tif [ -f $(PKG_INSTALL_DIR)/usr/lib/iptables/lib$$$$$$$${m}.so ]; then \\\n\t\t\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/iptables/lib$$$$$$$${m}.so $$(1)/usr/lib/iptables/ ; \\\n\t\tfi; \\\n\tdone\n\t$(3)\n  endef\n\n  $$(eval $$(call BuildPackage,$(1)))\nendef\n\n$(eval $(call BuildPackage,libxtables))\n$(eval $(call BuildPackage,libip4tc))\n$(eval $(call BuildPackage,libip6tc))\n$(eval $(call BuildPackage,libiptext))\n$(eval $(call BuildPackage,libiptext6))\n$(eval $(call BuildPackage,libiptext-nft))\n$(eval $(call BuildPackage,xtables-legacy))\n$(eval $(call BuildPackage,iptables-legacy))\n$(eval $(call BuildPackage,xtables-nft))\n$(eval $(call BuildPackage,arptables-nft))\n$(eval $(call BuildPackage,ebtables-nft))\n$(eval $(call BuildPackage,iptables-nft))\n$(eval $(call BuildPlugin,iptables-mod-conntrack-extra,$(IPT_CONNTRACK_EXTRA-m)))\n$(eval $(call BuildPlugin,iptables-mod-conntrack-label,$(IPT_CONNTRACK_LABEL-m)))\n$(eval $(call BuildPlugin,iptables-mod-extra,$(IPT_EXTRA-m)))\n$(eval $(call BuildPlugin,iptables-mod-physdev,$(IPT_PHYSDEV-m)))\n$(eval $(call BuildPlugin,iptables-mod-filter,$(IPT_FILTER-m)))\n$(eval $(call BuildPlugin,iptables-mod-ipopt,$(IPT_IPOPT-m)))\n$(eval $(call BuildPlugin,iptables-mod-ipsec,$(IPT_IPSEC-m)))\n$(eval $(call BuildPlugin,iptables-mod-nat-extra,$(IPT_NAT_EXTRA-m)))\n$(eval $(call BuildPlugin,iptables-mod-iprange,$(IPT_IPRANGE-m)))\n$(eval $(call BuildPlugin,iptables-mod-cluster,$(IPT_CLUSTER-m)))\n$(eval $(call BuildPlugin,iptables-mod-clusterip,$(IPT_CLUSTERIP-m)))\n$(eval $(call BuildPlugin,iptables-mod-ulog,$(IPT_ULOG-m)))\n$(eval $(call BuildPlugin,iptables-mod-hashlimit,$(IPT_HASHLIMIT-m)))\n$(eval $(call BuildPlugin,iptables-mod-rpfilter,$(IPT_RPFILTER-m)))\n$(eval $(call BuildPlugin,iptables-mod-led,$(IPT_LED-m)))\n$(eval $(call BuildPlugin,iptables-mod-socket,$(IPT_SOCKET-m)))\n$(eval $(call BuildPlugin,iptables-mod-tproxy,$(IPT_TPROXY-m)))\n$(eval $(call BuildPlugin,iptables-mod-tee,$(IPT_TEE-m)))\n$(eval $(call BuildPlugin,iptables-mod-u32,$(IPT_U32-m)))\n$(eval $(call BuildPlugin,iptables-mod-nflog,$(IPT_NFLOG-m)))\n$(eval $(call BuildPlugin,iptables-mod-trace,$(IPT_DEBUG-m)))\n$(eval $(call BuildPlugin,iptables-mod-nfqueue,$(IPT_NFQUEUE-m)))\n$(eval $(call BuildPlugin,iptables-mod-checksum,$(IPT_CHECKSUM-m)))\n$(eval $(call BuildPackage,ip6tables-legacy))\n$(eval $(call BuildPackage,ip6tables-nft))\n$(eval $(call BuildPlugin,ip6tables-extra,$(IPT_IPV6_EXTRA-m)))\n$(eval $(call BuildPlugin,ip6tables-mod-nat,$(IPT_NAT6-m)))\n\n"
  },
  {
    "path": "package/network/utils/iptables/patches/001-xtables-Call-init_extensions6-for-static-builds.patch",
    "content": "From e727ccad036e2cdba3339536c65c7ceef43c0740 Mon Sep 17 00:00:00 2001\nFrom: Erik Wilson <erik.e.wilson@gmail.com>\nDate: Tue, 13 Jul 2021 16:48:23 -0700\nSubject: [PATCH] xtables: Call init_extensions6() for static builds\n\nInitialize extensions from libext6 for cases where xtables is built statically.\n\nCloses: https://bugzilla.netfilter.org/show_bug.cgi?id=1550\nSigned-off-by: Erik Wilson <Erik.E.Wilson@gmail.com>\nSigned-off-by: Florian Westphal <fw@strlen.de>\n---\n iptables/xtables-monitor.c    | 1 +\n iptables/xtables-restore.c    | 1 +\n iptables/xtables-save.c       | 1 +\n iptables/xtables-standalone.c | 1 +\n iptables/xtables-translate.c  | 1 +\n 5 files changed, 5 insertions(+)\n\n--- a/iptables/xtables-monitor.c\n+++ b/iptables/xtables-monitor.c\n@@ -628,6 +628,7 @@ int xtables_monitor_main(int argc, char\n #if defined(ALL_INCLUSIVE) || defined(NO_SHARED_LIBS)\n \tinit_extensions();\n \tinit_extensions4();\n+\tinit_extensions6();\n #endif\n \n \tif (nft_init(&h, AF_INET, xtables_ipv4)) {\n--- a/iptables/xtables-restore.c\n+++ b/iptables/xtables-restore.c\n@@ -364,6 +364,7 @@ xtables_restore_main(int family, const c\n #if defined(ALL_INCLUSIVE) || defined(NO_SHARED_LIBS)\n \t\tinit_extensions();\n \t\tinit_extensions4();\n+\t\tinit_extensions6();\n #endif\n \t\tbreak;\n \tcase NFPROTO_ARP:\n--- a/iptables/xtables-save.c\n+++ b/iptables/xtables-save.c\n@@ -202,6 +202,7 @@ xtables_save_main(int family, int argc,\n #if defined(ALL_INCLUSIVE) || defined(NO_SHARED_LIBS)\n \t\tinit_extensions();\n \t\tinit_extensions4();\n+\t\tinit_extensions6();\n #endif\n \t\ttables = xtables_ipv4;\n \t\td.commit = true;\n--- a/iptables/xtables-standalone.c\n+++ b/iptables/xtables-standalone.c\n@@ -57,6 +57,7 @@ xtables_main(int family, const char *pro\n #if defined(ALL_INCLUSIVE) || defined(NO_SHARED_LIBS)\n \tinit_extensions();\n \tinit_extensions4();\n+\tinit_extensions6();\n #endif\n \n \tif (nft_init(&h, family, xtables_ipv4) < 0) {\n--- a/iptables/xtables-translate.c\n+++ b/iptables/xtables-translate.c\n@@ -469,6 +469,7 @@ static int xtables_xlate_main_common(str\n #if defined(ALL_INCLUSIVE) || defined(NO_SHARED_LIBS)\n \tinit_extensions();\n \tinit_extensions4();\n+\tinit_extensions6();\n #endif\n \t\ttables = xtables_ipv4;\n \t\tbreak;\n"
  },
  {
    "path": "package/network/utils/iptables/patches/002-xtables-Call-init_extensions_a_b.patch",
    "content": "A modified version of this patch was commited upstream\nas part of a fixup series\nhttps://bugzilla.netfilter.org/show_bug.cgi?id=1593\nhttps://git.netfilter.org/iptables/commit/?id=0836524f093c0fd9c39604a46a949e43d9b47ef2\n\n--- a/iptables/xtables-monitor.c\n+++ b/iptables/xtables-monitor.c\n@@ -629,6 +629,8 @@ int xtables_monitor_main(int argc, char\n \tinit_extensions();\n \tinit_extensions4();\n \tinit_extensions6();\n+\tinit_extensionsa();\n+\tinit_extensionsb();\n #endif\n \n \tif (nft_init(&h, AF_INET, xtables_ipv4)) {\n--- a/iptables/xtables-restore.c\n+++ b/iptables/xtables-restore.c\n@@ -368,9 +368,17 @@ xtables_restore_main(int family, const c\n #endif\n \t\tbreak;\n \tcase NFPROTO_ARP:\n+#if defined(ALL_INCLUSIVE) || defined(NO_SHARED_LIBS)\n+\t\tinit_extensions();\n+\t\tinit_extensionsa();\n+#endif\n \t\ttables = xtables_arp;\n \t\tbreak;\n \tcase NFPROTO_BRIDGE:\n+#if defined(ALL_INCLUSIVE) || defined(NO_SHARED_LIBS)\n+\t\tinit_extensions();\n+\t\tinit_extensionsb();\n+#endif\n \t\ttables = xtables_bridge;\n \t\tbreak;\n \tdefault:\n--- a/iptables/xtables-save.c\n+++ b/iptables/xtables-save.c\n@@ -208,9 +208,17 @@ xtables_save_main(int family, int argc,\n \t\td.commit = true;\n \t\tbreak;\n \tcase NFPROTO_ARP:\n+#if defined(ALL_INCLUSIVE) || defined(NO_SHARED_LIBS)\n+\t\tinit_extensions();\n+\t\tinit_extensionsa();\n+#endif\n \t\ttables = xtables_arp;\n \t\tbreak;\n \tcase NFPROTO_BRIDGE: {\n+#if defined(ALL_INCLUSIVE) || defined(NO_SHARED_LIBS)\n+\t\tinit_extensions();\n+\t\tinit_extensionsb();\n+#endif\n \t\tconst char *ctr = getenv(\"EBTABLES_SAVE_COUNTER\");\n \n \t\tif (!(d.format & FMT_NOCOUNTS)) {\n--- a/iptables/xtables-standalone.c\n+++ b/iptables/xtables-standalone.c\n@@ -58,6 +58,8 @@ xtables_main(int family, const char *pro\n \tinit_extensions();\n \tinit_extensions4();\n \tinit_extensions6();\n+\tinit_extensionsa();\n+\tinit_extensionsb();\n #endif\n \n \tif (nft_init(&h, family, xtables_ipv4) < 0) {\n--- a/iptables/xtables-translate.c\n+++ b/iptables/xtables-translate.c\n@@ -474,9 +474,17 @@ static int xtables_xlate_main_common(str\n \t\ttables = xtables_ipv4;\n \t\tbreak;\n \tcase NFPROTO_ARP:\n+#if defined(ALL_INCLUSIVE) || defined(NO_SHARED_LIBS)\n+\t\tinit_extensions();\n+\t\tinit_extensionsa();\n+#endif\n \t\ttables = xtables_arp;\n \t\tbreak;\n \tcase NFPROTO_BRIDGE:\n+#if defined(ALL_INCLUSIVE) || defined(NO_SHARED_LIBS)\n+\t\tinit_extensions();\n+\t\tinit_extensionsb();\n+#endif\n \t\ttables = xtables_bridge;\n \t\tbreak;\n \tdefault:\n--- a/iptables/xtables-arp.c\n+++ b/iptables/xtables-arp.c\n@@ -438,6 +438,7 @@ int nft_init_arp(struct nft_handle *h, c\n \t}\n \n #if defined(ALL_INCLUSIVE) || defined(NO_SHARED_LIBS)\n+\tinit_extensions();\n \tinit_extensionsa();\n #endif\n \n--- a/iptables/xtables-eb.c\n+++ b/iptables/xtables-eb.c\n@@ -685,6 +685,7 @@ int nft_init_eb(struct nft_handle *h, co\n \t}\n \n #if defined(ALL_INCLUSIVE) || defined(NO_SHARED_LIBS)\n+\tinit_extensions();\n \tinit_extensionsb();\n #endif\n \n"
  },
  {
    "path": "package/network/utils/iptables/patches/010-add-set-dscpmark-support.patch",
    "content": "From 74267bacce0c43e5038b0377cb7c08f1ad9d50a3 Mon Sep 17 00:00:00 2001\nFrom: Kevin Darbyshire-Bryant <ldir@darbyshire-bryant.me.uk>\nDate: Sat, 23 Mar 2019 10:21:03 +0000\nSubject: [PATCH] iptables: connmark - add set-dscpmark option for openwrt\n\nNaive user space front end to xt_connmark 'setdscp' option.\n\niptables -A QOS_MARK_eth0 -t mangle -j CONNMARK --set-dscpmark 0xfc000000/0x01000000\n\nThis version has a hack to support a backport to 4.14\n\nSigned-off-by: Kevin Darbyshire-Bryant <ldir@darbyshire-bryant.me.uk>\n---\n extensions/libxt_CONNMARK.c           | 315 +++++++++++++++++++++++++-\n include/linux/netfilter/xt_connmark.h |  10 +\n 2 files changed, 324 insertions(+), 1 deletion(-)\n\n--- a/extensions/libxt_CONNMARK.c\n+++ b/extensions/libxt_CONNMARK.c\n@@ -22,6 +22,7 @@\n #include <stdbool.h>\n #include <stdint.h>\n #include <stdio.h>\n+#include <strings.h>\n #include <xtables.h>\n #include <linux/netfilter/xt_CONNMARK.h>\n \n@@ -49,6 +50,7 @@ enum {\n \tO_CTMASK,\n \tO_NFMASK,\n \tO_MASK,\n+\tO_DSCP_MARK,\n \tF_SET_MARK         = 1 << O_SET_MARK,\n \tF_SAVE_MARK        = 1 << O_SAVE_MARK,\n \tF_RESTORE_MARK     = 1 << O_RESTORE_MARK,\n@@ -61,8 +63,10 @@ enum {\n \tF_CTMASK           = 1 << O_CTMASK,\n \tF_NFMASK           = 1 << O_NFMASK,\n \tF_MASK             = 1 << O_MASK,\n+\tF_DSCP_MARK\t   = 1 << O_DSCP_MARK,\n \tF_OP_ANY           = F_SET_MARK | F_SAVE_MARK | F_RESTORE_MARK |\n-\t                     F_AND_MARK | F_OR_MARK | F_XOR_MARK | F_SET_XMARK,\n+\t                     F_AND_MARK | F_OR_MARK | F_XOR_MARK | F_SET_XMARK |\n+\t\t\t     F_DSCP_MARK,\n };\n \n static const char *const xt_connmark_shift_ops[] = {\n@@ -114,6 +118,8 @@ static const struct xt_option_entry conn\n \t .excl = F_MASK, .flags = XTOPT_PUT, XTOPT_POINTER(s, nfmask)},\n \t{.name = \"mask\", .id = O_MASK, .type = XTTYPE_UINT32,\n \t .excl = F_CTMASK | F_NFMASK},\n+\t{.name = \"set-dscpmark\", .id = O_DSCP_MARK, .type = XTTYPE_MARKMASK32,\n+\t .excl = F_OP_ANY},\n \tXTOPT_TABLEEND,\n };\n #undef s\n@@ -148,6 +154,38 @@ static const struct xt_option_entry conn\n };\n #undef s\n \n+#define s struct xt_connmark_tginfo3\n+static const struct xt_option_entry connmark_tg_opts_v3[] = {\n+\t{.name = \"set-xmark\", .id = O_SET_XMARK, .type = XTTYPE_MARKMASK32,\n+\t .excl = F_OP_ANY},\n+\t{.name = \"set-mark\", .id = O_SET_MARK, .type = XTTYPE_MARKMASK32,\n+\t .excl = F_OP_ANY},\n+\t{.name = \"and-mark\", .id = O_AND_MARK, .type = XTTYPE_UINT32,\n+\t .excl = F_OP_ANY},\n+\t{.name = \"or-mark\", .id = O_OR_MARK, .type = XTTYPE_UINT32,\n+\t .excl = F_OP_ANY},\n+\t{.name = \"xor-mark\", .id = O_XOR_MARK, .type = XTTYPE_UINT32,\n+\t .excl = F_OP_ANY},\n+\t{.name = \"save-mark\", .id = O_SAVE_MARK, .type = XTTYPE_NONE,\n+\t .excl = F_OP_ANY},\n+\t{.name = \"restore-mark\", .id = O_RESTORE_MARK, .type = XTTYPE_NONE,\n+\t .excl = F_OP_ANY},\n+\t{.name = \"left-shift-mark\", .id = O_LEFT_SHIFT_MARK, .type = XTTYPE_UINT8,\n+\t .min = 0, .max = 32},\n+\t{.name = \"right-shift-mark\", .id = O_RIGHT_SHIFT_MARK, .type = XTTYPE_UINT8,\n+\t .min = 0, .max = 32},\n+\t{.name = \"ctmask\", .id = O_CTMASK, .type = XTTYPE_UINT32,\n+\t .excl = F_MASK, .flags = XTOPT_PUT, XTOPT_POINTER(s, ctmask)},\n+\t{.name = \"nfmask\", .id = O_NFMASK, .type = XTTYPE_UINT32,\n+\t .excl = F_MASK, .flags = XTOPT_PUT, XTOPT_POINTER(s, nfmask)},\n+\t{.name = \"mask\", .id = O_MASK, .type = XTTYPE_UINT32,\n+\t .excl = F_CTMASK | F_NFMASK},\n+\t{.name = \"set-dscpmark\", .id = O_DSCP_MARK, .type = XTTYPE_MARKMASK32,\n+\t .excl = F_OP_ANY},\n+\tXTOPT_TABLEEND,\n+};\n+#undef s\n+\n static void connmark_tg_help(void)\n {\n \tprintf(\n@@ -175,6 +213,15 @@ static void connmark_tg_help_v2(void)\n );\n }\n \n+static void connmark_tg_help_v3(void)\n+{\n+\tconnmark_tg_help_v2();\n+\tprintf(\n+\"  --set-dscpmark value/mask        Save DSCP to conntrack mark value\\n\"\n+);\n+}\n+\n+\n static void connmark_tg_init(struct xt_entry_target *target)\n {\n \tstruct xt_connmark_tginfo1 *info = (void *)target->data;\n@@ -199,6 +246,16 @@ static void connmark_tg_init_v2(struct x\n \tinfo->shift_bits = 0;\n }\n \n+static void connmark_tg_init_v3(struct xt_entry_target *target)\n+{\n+\tstruct xt_connmark_tginfo3 *info;\n+\n+\tconnmark_tg_init_v2(target);\n+\tinfo = (void *)target->data;\n+\n+\tinfo->func = 0;\n+}\n+\n static void CONNMARK_parse(struct xt_option_call *cb)\n {\n \tstruct xt_connmark_target_info *markinfo = cb->data;\n@@ -253,6 +310,23 @@ static void connmark_tg_parse(struct xt_\n \t\tinfo->ctmark = cb->val.u32;\n \t\tinfo->ctmask = 0;\n \t\tbreak;\n+\tcase O_DSCP_MARK:\n+/* we sneaky sneaky this.  nfmask isn't used by the set mark functionality\n+ * and by default is set to uint32max.  We can use the top bit as a flag\n+ * that we're in DSCP_MARK submode of SET_MARK, if set then it's normal\n+ * if unset then we're in DSCP_MARK\n+ */\n+\t\tinfo->mode   = XT_CONNMARK_SET;\n+\t\tinfo->ctmark = cb->val.mark;\n+\t\tinfo->ctmask = cb->val.mask;\n+\t\tinfo->nfmask = info->ctmark ? ffs(info->ctmark) - 1 : 0;\n+\t\t/* need 6 contiguous bits */\n+\t\tif ((~0 & (info->ctmark >> info->nfmask)) != 0x3f)\n+\t\t\txtables_error(PARAMETER_PROBLEM,\n+\t\t\t\t\"CONNMARK set-dscpmark: need 6 contiguous dscpmask bits\");\n+\t\tif (info->ctmark & info->ctmask)\n+\t\t\txtables_error(PARAMETER_PROBLEM,\n+\t\t\t\t\"CONNMARK set-dscpmark: dscpmask/statemask bits overlap\");\n \tcase O_SAVE_MARK:\n \t\tinfo->mode = XT_CONNMARK_SAVE;\n \t\tbreak;\n@@ -320,6 +394,78 @@ static void connmark_tg_parse_v2(struct\n \t}\n }\n \n+static void connmark_tg_parse_v3(struct xt_option_call *cb)\n+{\n+\tstruct xt_connmark_tginfo3 *info = cb->data;\n+\n+\txtables_option_parse(cb);\n+\tswitch (cb->entry->id) {\n+\tcase O_SET_XMARK:\n+\t\tinfo->mode   = XT_CONNMARK_SET;\n+\t\tinfo->func   = XT_CONNMARK_VALUE;\n+\t\tinfo->ctmark = cb->val.mark;\n+\t\tinfo->ctmask = cb->val.mask;\n+\t\tbreak;\n+\tcase O_SET_MARK:\n+\t\tinfo->mode   = XT_CONNMARK_SET;\n+\t\tinfo->func   = XT_CONNMARK_VALUE;\n+\t\tinfo->ctmark = cb->val.mark;\n+\t\tinfo->ctmask = cb->val.mark | cb->val.mask;\n+\t\tbreak;\n+\tcase O_AND_MARK:\n+\t\tinfo->mode   = XT_CONNMARK_SET;\n+\t\tinfo->func   = XT_CONNMARK_VALUE;\n+\t\tinfo->ctmark = 0;\n+\t\tinfo->ctmask = ~cb->val.u32;\n+\t\tbreak;\n+\tcase O_OR_MARK:\n+\t\tinfo->mode   = XT_CONNMARK_SET;\n+\t\tinfo->func   = XT_CONNMARK_VALUE;\n+\t\tinfo->ctmark = cb->val.u32;\n+\t\tinfo->ctmask = cb->val.u32;\n+\t\tbreak;\n+\tcase O_XOR_MARK:\n+\t\tinfo->mode   = XT_CONNMARK_SET;\n+\t\tinfo->func   = XT_CONNMARK_VALUE;\n+\t\tinfo->ctmark = cb->val.u32;\n+\t\tinfo->ctmask = 0;\n+\t\tbreak;\n+\tcase O_DSCP_MARK:\n+\t\tinfo->mode   = XT_CONNMARK_SET;\n+\t\tinfo->func   = XT_CONNMARK_DSCP;\n+\t\tinfo->ctmark = cb->val.mark;\n+\t\tinfo->ctmask = cb->val.mask;\n+\t\tinfo->shift_bits = info->ctmark ? ffs(info->ctmark) - 1 : 0;\n+\t\t/* need 6 contiguous bits */\n+\t\tif ((~0 & (info->ctmark >> info->shift_bits)) != 0x3f)\n+\t\t\txtables_error(PARAMETER_PROBLEM,\n+\t\t\t\t\"CONNMARK set-dscpmark: need 6 contiguous dscpmask bits\");\n+\t\tif (info->ctmark & info->ctmask)\n+\t\t\txtables_error(PARAMETER_PROBLEM,\n+\t\t\t\t\"CONNMARK set-dscpmark: dscpmask/statemask bits overlap\");\n+\t\tbreak;\n+\tcase O_SAVE_MARK:\n+\t\tinfo->mode = XT_CONNMARK_SAVE;\n+\t\tbreak;\n+\tcase O_RESTORE_MARK:\n+\t\tinfo->mode = XT_CONNMARK_RESTORE;\n+\t\tbreak;\n+\tcase O_MASK:\n+\t\tinfo->nfmask = info->ctmask = cb->val.u32;\n+\t\tbreak;\n+\tcase O_LEFT_SHIFT_MARK:\n+\t\tinfo->shift_dir = D_SHIFT_LEFT;\n+\t\tinfo->shift_bits = cb->val.u8;\n+\t\tbreak;\n+\tcase O_RIGHT_SHIFT_MARK:\n+\t\tinfo->shift_dir = D_SHIFT_RIGHT;\n+\t\tinfo->shift_bits = cb->val.u8;\n+\t\tbreak;\n+\tdefault:\n+\t\tbreak;\n+\t}\n+}\n+\n static void connmark_tg_check(struct xt_fcheck_call *cb)\n {\n \tif (!(cb->xflags & F_OP_ANY))\n@@ -463,6 +609,65 @@ connmark_tg_print_v2(const void *ip, con\n \t}\n }\n \n+static void\n+connmark_tg_print_v3(const void *ip, const struct xt_entry_target *target,\n+                  int numeric)\n+{\n+\tconst struct xt_connmark_tginfo3 *info = (const void *)target->data;\n+\tconst char *shift_op = xt_connmark_shift_ops[info->shift_dir];\n+\n+\tswitch (info->mode) {\n+\tcase XT_CONNMARK_SET:\n+\t\tif (info->func & XT_CONNMARK_DSCP) {\n+\t\t\tprintf(\" CONNMARK DSCP 0x%x/0x%x\",\n+\t\t\t       info->ctmark, info->ctmask);\n+\t\t}\n+\t\tif (info->func & XT_CONNMARK_VALUE) {\n+\t\t\tif (info->ctmark == 0)\n+\t\t\t\tprintf(\" CONNMARK and 0x%x\",\n+\t\t\t\t       (unsigned int)(uint32_t)~info->ctmask);\n+\t\t\telse if (info->ctmark == info->ctmask)\n+\t\t\t\tprintf(\" CONNMARK or 0x%x\", info->ctmark);\n+\t\t\telse if (info->ctmask == 0)\n+\t\t\t\tprintf(\" CONNMARK xor 0x%x\", info->ctmark);\n+\t\t\telse if (info->ctmask == 0xFFFFFFFFU)\n+\t\t\t\tprintf(\" CONNMARK set 0x%x\", info->ctmark);\n+\t\t\telse\n+\t\t\t\tprintf(\" CONNMARK xset 0x%x/0x%x\",\n+\t\t\t\t       info->ctmark, info->ctmask);\n+\t\t}\n+\t\tbreak;\n+\tcase XT_CONNMARK_SAVE:\n+\t\tif (info->nfmask == UINT32_MAX && info->ctmask == UINT32_MAX)\n+\t\t\tprintf(\" CONNMARK save\");\n+\t\telse if (info->nfmask == info->ctmask)\n+\t\t\tprintf(\" CONNMARK save mask 0x%x\", info->nfmask);\n+\t\telse\n+\t\t\tprintf(\" CONNMARK save nfmask 0x%x ctmask ~0x%x\",\n+\t\t\t       info->nfmask, info->ctmask);\n+\t\tbreak;\n+\tcase XT_CONNMARK_RESTORE:\n+\t\tif (info->ctmask == UINT32_MAX && info->nfmask == UINT32_MAX)\n+\t\t\tprintf(\" CONNMARK restore\");\n+\t\telse if (info->ctmask == info->nfmask)\n+\t\t\tprintf(\" CONNMARK restore mask 0x%x\", info->ctmask);\n+\t\telse\n+\t\t\tprintf(\" CONNMARK restore ctmask 0x%x nfmask ~0x%x\",\n+\t\t\t       info->ctmask, info->nfmask);\n+\t\tbreak;\n+\n+\tdefault:\n+\t\tprintf(\" ERROR: UNKNOWN CONNMARK MODE\");\n+\t\tbreak;\n+\t}\n+\n+\tif (info->mode <= XT_CONNMARK_RESTORE &&\n+\t    !(info->mode == XT_CONNMARK_SET && info->func == XT_CONNMARK_DSCP) &&\n+\t    info->shift_bits != 0) {\n+\t\tprintf(\" %s %u\", shift_op, info->shift_bits);\n+\t}\n+}\n+\n static void CONNMARK_save(const void *ip, const struct xt_entry_target *target)\n {\n \tconst struct xt_connmark_target_info *markinfo =\n@@ -548,6 +753,38 @@ connmark_tg_save_v2(const void *ip, cons\n \t}\n }\n \n+static void\n+connmark_tg_save_v3(const void *ip, const struct xt_entry_target *target)\n+{\n+\tconst struct xt_connmark_tginfo3 *info = (const void *)target->data;\n+\tconst char *shift_op = xt_connmark_shift_ops[info->shift_dir];\n+\n+\tswitch (info->mode) {\n+\tcase XT_CONNMARK_SET:\n+\t\tif (info->func & XT_CONNMARK_VALUE)\n+\t\t\tprintf(\" --set-xmark 0x%x/0x%x\", info->ctmark, info->ctmask);\n+\t\tif (info->func & XT_CONNMARK_DSCP)\n+\t\t\tprintf(\" --set-dscpmark 0x%x/0x%x\", info->ctmark, info->ctmask);\n+\t\tbreak;\n+\tcase XT_CONNMARK_SAVE:\n+\t\tprintf(\" --save-mark --nfmask 0x%x --ctmask 0x%x\",\n+\t\t       info->nfmask, info->ctmask);\n+\t\tbreak;\n+\tcase XT_CONNMARK_RESTORE:\n+\t\tprintf(\" --restore-mark --nfmask 0x%x --ctmask 0x%x\",\n+\t\t       info->nfmask, info->ctmask);\n+\t\tbreak;\n+\tdefault:\n+\t\tprintf(\" ERROR: UNKNOWN CONNMARK MODE\");\n+\t\tbreak;\n+\t}\n+\tif (info->mode <= XT_CONNMARK_RESTORE &&\n+\t    !(info->mode == XT_CONNMARK_SET && info->func == XT_CONNMARK_DSCP) &&\n+\t    info->shift_bits != 0) {\n+\t\tprintf(\" --%s %u\", shift_op, info->shift_bits);\n+\t}\n+}\n+\n static int connmark_tg_xlate(struct xt_xlate *xl,\n \t\t\t     const struct xt_xlate_tg_params *params)\n {\n@@ -639,6 +876,66 @@ static int connmark_tg_xlate_v2(struct x\n \n \treturn 1;\n }\n+\n+static int connmark_tg_xlate_v3(struct xt_xlate *xl,\n+\t\t\t     const struct xt_xlate_tg_params *params)\n+{\n+\tconst struct xt_connmark_tginfo3 *info =\n+\t\t(const void *)params->target->data;\n+\tconst char *shift_op = xt_connmark_shift_ops[info->shift_dir];\n+\n+\tswitch (info->mode) {\n+\tcase XT_CONNMARK_SET:\n+\t\txt_xlate_add(xl, \"ct mark set \");\n+\t\tif (info->func & XT_CONNMARK_VALUE) {\n+\t\t\tif (info->ctmask == 0xFFFFFFFFU)\n+\t\t\t\txt_xlate_add(xl, \"0x%x \", info->ctmark);\n+\t\t\telse if (info->ctmark == 0)\n+\t\t\t\txt_xlate_add(xl, \"ct mark and 0x%x\", ~info->ctmask);\n+\t\t\telse if (info->ctmark == info->ctmask)\n+\t\t\t\txt_xlate_add(xl, \"ct mark or 0x%x\",\n+\t\t\t\t\t     info->ctmark);\n+\t\t\telse if (info->ctmask == 0)\n+\t\t\t\txt_xlate_add(xl, \"ct mark xor 0x%x\",\n+\t\t\t\t\t     info->ctmark);\n+\t\t\telse\n+\t\t\t\txt_xlate_add(xl, \"ct mark xor 0x%x and 0x%x\",\n+\t\t\t\t\t     info->ctmark, ~info->ctmask);\n+\t\t}\n+\t\tif (info->func & XT_CONNMARK_DSCP) {\n+/* FIXME the nftables syntax would go here if only we knew what it was */\n+\t\t\txt_xlate_add(xl, \"ct mark set typeof(ct mark) ip dscp \"\n+\t\t\t\t\t \"<< %u or 0x%x\", info->shift_bits,\n+\t\t\t\t\t     info->ctmask);\n+\t\t}\n+\t\tbreak;\n+\tcase XT_CONNMARK_SAVE:\n+\t\txt_xlate_add(xl, \"ct mark set mark\");\n+\t\tif (!(info->nfmask == UINT32_MAX &&\n+\t\t    info->ctmask == UINT32_MAX)) {\n+\t\t\tif (info->nfmask == info->ctmask)\n+\t\t\t\txt_xlate_add(xl, \" and 0x%x\", info->nfmask);\n+\t\t}\n+\t\tbreak;\n+\tcase XT_CONNMARK_RESTORE:\n+\t\txt_xlate_add(xl, \"meta mark set ct mark\");\n+\t\tif (!(info->nfmask == UINT32_MAX &&\n+\t\t    info->ctmask == UINT32_MAX)) {\n+\t\t\tif (info->nfmask == info->ctmask)\n+\t\t\t\txt_xlate_add(xl, \" and 0x%x\", info->nfmask);\n+\t\t}\n+\t\tbreak;\n+\t}\n+\n+\tif (info->mode <= XT_CONNMARK_RESTORE &&\n+\t    !(info->mode == XT_CONNMARK_SET && info->func == XT_CONNMARK_DSCP) &&\n+\t    info->shift_bits != 0) {\n+\t\txt_xlate_add(xl, \" %s %u\", shift_op, info->shift_bits);\n+\t}\n+\n+\treturn 1;\n+}\n+\n static struct xtables_target connmark_tg_reg[] = {\n \t{\n \t\t.family        = NFPROTO_UNSPEC,\n@@ -687,6 +984,22 @@ static struct xtables_target connmark_tg\n \t\t.x6_options    = connmark_tg_opts_v2,\n \t\t.xlate         = connmark_tg_xlate_v2,\n \t},\n+\t{\n+\t\t.version       = XTABLES_VERSION,\n+\t\t.name          = \"CONNMARK\",\n+\t\t.revision      = 3,\n+\t\t.family        = NFPROTO_UNSPEC,\n+\t\t.size          = XT_ALIGN(sizeof(struct xt_connmark_tginfo3)),\n+\t\t.userspacesize = XT_ALIGN(sizeof(struct xt_connmark_tginfo3)),\n+\t\t.help          = connmark_tg_help_v3,\n+\t\t.init          = connmark_tg_init_v3,\n+\t\t.print         = connmark_tg_print_v3,\n+\t\t.save          = connmark_tg_save_v3,\n+\t\t.x6_parse      = connmark_tg_parse_v3,\n+\t\t.x6_fcheck     = connmark_tg_check,\n+\t\t.x6_options    = connmark_tg_opts_v3,\n+\t\t.xlate         = connmark_tg_xlate_v3,\n+\t},\n };\n \n void _init(void)\n--- a/include/linux/netfilter/xt_connmark.h\n+++ b/include/linux/netfilter/xt_connmark.h\n@@ -18,6 +18,11 @@ enum {\n \tXT_CONNMARK_RESTORE\n };\n \n+enum {\n+\tXT_CONNMARK_VALUE\t= (1 << 0),\n+\tXT_CONNMARK_DSCP\t= (1 << 1)\n+};\n+\n struct xt_connmark_tginfo1 {\n \t__u32 ctmark, ctmask, nfmask;\n \t__u8 mode;\n@@ -28,6 +33,11 @@ struct xt_connmark_tginfo2 {\n \t__u8 shift_dir, shift_bits, mode;\n };\n \n+struct xt_connmark_tginfo3 {\n+\t__u32 ctmark, ctmask, nfmask;\n+\t__u8 shift_dir, shift_bits, mode, func;\n+};\n+\n struct xt_connmark_mtinfo1 {\n \t__u32 mark, mask;\n \t__u8 invert;\n"
  },
  {
    "path": "package/network/utils/iptables/patches/101-remove-check-already.patch",
    "content": "--- a/libxtables/xtables.c\n+++ b/libxtables/xtables.c\n@@ -968,12 +968,6 @@ void xtables_register_match(struct xtabl\n \tstruct xtables_match **pos;\n \tbool seen_myself = false;\n \n-\tif (me->next) {\n-\t\tfprintf(stderr, \"%s: match \\\"%s\\\" already registered\\n\",\n-\t\t\txt_params->program_name, me->name);\n-\t\texit(1);\n-\t}\n-\n \tif (me->version == NULL) {\n \t\tfprintf(stderr, \"%s: match %s<%u> is missing a version\\n\",\n \t\t        xt_params->program_name, me->name, me->revision);\n@@ -1152,12 +1146,6 @@ void xtables_register_target(struct xtab\n \tstruct xtables_target **pos;\n \tbool seen_myself = false;\n \n-\tif (me->next) {\n-\t\tfprintf(stderr, \"%s: target \\\"%s\\\" already registered\\n\",\n-\t\t\txt_params->program_name, me->name);\n-\t\texit(1);\n-\t}\n-\n \tif (me->version == NULL) {\n \t\tfprintf(stderr, \"%s: target %s<%u> is missing a version\\n\",\n \t\t        xt_params->program_name, me->name, me->revision);\n"
  },
  {
    "path": "package/network/utils/iptables/patches/102-iptables-disable-modprobe.patch",
    "content": "--- a/libxtables/xtables.c\n+++ b/libxtables/xtables.c\n@@ -403,6 +403,7 @@ static char *get_modprobe(void)\n \n int xtables_insmod(const char *modname, const char *modprobe, bool quiet)\n {\n+#if 0\n \tchar *buf = NULL;\n \tchar *argv[4];\n \tint status;\n@@ -437,6 +438,7 @@ int xtables_insmod(const char *modname,\n \tfree(buf);\n \tif (WIFEXITED(status) && WEXITSTATUS(status) == 0)\n \t\treturn 0;\n+#endif\n \treturn -1;\n }\n \n"
  },
  {
    "path": "package/network/utils/iptables/patches/103-optional-xml.patch",
    "content": "--- a/iptables/xtables-legacy-multi.c\n+++ b/iptables/xtables-legacy-multi.c\n@@ -32,8 +32,10 @@ static const struct subcommand multi_sub\n \n \n #endif\n+#ifdef ENABLE_XML\n \t{\"iptables-xml\",        iptables_xml_main},\n \t{\"xml\",                 iptables_xml_main},\n+#endif\n #ifdef ENABLE_IPV6\n \t{\"ip6tables\",           ip6tables_main},\n \t{\"main6\",               ip6tables_main},\n"
  },
  {
    "path": "package/network/utils/iptables/patches/200-configurable_builtin.patch",
    "content": "--- a/extensions/GNUmakefile.in\n+++ b/extensions/GNUmakefile.in\n@@ -50,11 +50,31 @@ pfb_build_mod := $(filter-out @blacklist\n pfa_build_mod := $(filter-out @blacklist_modules@ @blacklist_a_modules@,${pfa_build_mod})\n pf4_build_mod := $(filter-out @blacklist_modules@ @blacklist_4_modules@,${pf4_build_mod})\n pf6_build_mod := $(filter-out @blacklist_modules@ @blacklist_6_modules@,${pf6_build_mod})\n-pfx_objs      := $(patsubst %,libxt_%.o,${pfx_build_mod})\n-pfb_objs      := $(patsubst %,libebt_%.o,${pfb_build_mod})\n-pfa_objs      := $(patsubst %,libarpt_%.o,${pfa_build_mod})\n-pf4_objs      := $(patsubst %,libipt_%.o,${pf4_build_mod})\n-pf6_objs      := $(patsubst %,libip6t_%.o,${pf6_build_mod})\n+ifdef BUILTIN_MODULES\n+pfx_build_static := $(filter $(BUILTIN_MODULES),${pfx_build_mod})\n+pfb_build_static := $(filter $(BUILTIN_MODULES),${pfb_build_mod})\n+pfa_build_static := $(filter $(BUILTIN_MODULES),${pfa_build_mod})\n+pf4_build_static := $(filter $(BUILTIN_MODULES),${pf4_build_mod})\n+pf6_build_static := $(filter $(BUILTIN_MODULES),${pf6_build_mod})\n+else\n+@ENABLE_STATIC_TRUE@ pfx_build_static := $(pfx_build_mod)\n+@ENABLE_STATIC_TRUE@ pfb_build_static := $(pfb_build_mod)\n+@ENABLE_STATIC_TRUE@ pfa_build_static := $(pfa_build_mod)\n+@ENABLE_STATIC_TRUE@ pf4_build_static := $(pf4_build_mod)\n+@ENABLE_STATIC_TRUE@ pf6_build_static := $(pf6_build_mod)\n+endif\n+\n+pfx_build_mod := $(filter-out $(pfx_build_static),$(pfx_build_mod))\n+pfb_build_mod := $(filter-out $(pfb_build_static),$(pfb_build_mod))\n+pfa_build_mod := $(filter-out $(pfa_build_static),$(pfa_build_mod))\n+pf4_build_mod := $(filter-out $(pf4_build_static),$(pf4_build_mod))\n+pf6_build_mod := $(filter-out $(pf6_build_static),$(pf6_build_mod))\n+\n+pfx_objs      := $(patsubst %,libxt_%.o,${pfx_build_static})\n+pfb_objs      := $(patsubst %,libebt_%.o,${pfb_build_static})\n+pfa_objs      := $(patsubst %,libarpt_%.o,${pfa_build_static})\n+pf4_objs      := $(patsubst %,libipt_%.o,${pf4_build_static})\n+pf6_objs      := $(patsubst %,libip6t_%.o,${pf6_build_static})\n pfx_solibs    := $(patsubst %,libxt_%.so,${pfx_build_mod})\n pfb_solibs    := $(patsubst %,libebt_%.so,${pfb_build_mod})\n pfa_solibs    := $(patsubst %,libarpt_%.so,${pfa_build_mod})\n@@ -68,14 +88,14 @@ pfx_symlink_files := $(patsubst %,libxt_\n #\n targets := libext.a libext4.a libext6.a libext_ebt.a libext_arpt.a matches.man targets.man\n targets_install :=\n-@ENABLE_STATIC_TRUE@ libext_objs := ${pfx_objs}\n-@ENABLE_STATIC_TRUE@ libext_ebt_objs := ${pfb_objs}\n-@ENABLE_STATIC_TRUE@ libext_arpt_objs := ${pfa_objs}\n-@ENABLE_STATIC_TRUE@ libext4_objs := ${pf4_objs}\n-@ENABLE_STATIC_TRUE@ libext6_objs := ${pf6_objs}\n-@ENABLE_STATIC_FALSE@ targets += ${pfx_solibs} ${pfb_solibs} ${pf4_solibs} ${pf6_solibs} ${pfa_solibs} ${pfx_symlink_files}\n-@ENABLE_STATIC_FALSE@ targets_install += ${pfx_solibs} ${pfb_solibs} ${pf4_solibs} ${pf6_solibs} ${pfa_solibs}\n-@ENABLE_STATIC_FALSE@ symlinks_install := ${pfx_symlink_files}\n+libext_objs := ${pfx_objs}\n+libext_ebt_objs := ${pfb_objs}\n+libext_arpt_objs := ${pfa_objs}\n+libext4_objs := ${pf4_objs}\n+libext6_objs := ${pf6_objs}\n+targets += ${pfx_solibs} ${pfb_solibs} ${pf4_solibs} ${pf6_solibs} ${pfa_solibs} ${pfx_symlink_files}\n+targets_install := $(strip ${pfx_solibs} ${pfb_solibs} ${pf4_solibs} ${pf6_solibs} ${pfa_solibs})\n+symlinks_install := ${pfx_symlink_files}\n \n .SECONDARY:\n \n@@ -161,11 +181,11 @@ libext4.a: initext4.o ${libext4_objs}\n libext6.a: initext6.o ${libext6_objs}\n \t${AM_VERBOSE_AR} ${AR} crs $@ $^;\n \n-initext_func  := $(addprefix xt_,${pfx_build_mod})\n-initextb_func := $(addprefix ebt_,${pfb_build_mod})\n-initexta_func := $(addprefix arpt_,${pfa_build_mod})\n-initext4_func := $(addprefix ipt_,${pf4_build_mod})\n-initext6_func := $(addprefix ip6t_,${pf6_build_mod})\n+initext_func  := $(addprefix xt_,${pfx_build_static})\n+initextb_func := $(addprefix ebt_,${pfb_build_static})\n+initexta_func := $(addprefix arpt_,${pfa_build_static})\n+initext4_func := $(addprefix ipt_,${pf4_build_static})\n+initext6_func := $(addprefix ip6t_,${pf6_build_static})\n \n .initext.dd: FORCE\n \t@echo \"${initext_func}\" >$@.tmp; \\\n"
  },
  {
    "path": "package/network/utils/iptables/patches/600-shared-libext.patch",
    "content": "--- a/extensions/GNUmakefile.in\n+++ b/extensions/GNUmakefile.in\n@@ -86,7 +86,7 @@ pfx_symlink_files := $(patsubst %,libxt_\n #\n # Building blocks\n #\n-targets := libext.a libext4.a libext6.a libext_ebt.a libext_arpt.a matches.man targets.man\n+targets := libiptext.so libiptext4.so libiptext6.so libiptext_ebt.so libiptext_arpt.so matches.man targets.man\n targets_install :=\n libext_objs := ${pfx_objs}\n libext_ebt_objs := ${pfb_objs}\n@@ -132,7 +132,7 @@ clean:\n distclean: clean\n \n init%.o: init%.c\n-\t${AM_VERBOSE_CC} ${CC} ${AM_CPPFLAGS} ${AM_DEPFLAGS} ${AM_CFLAGS} -D_INIT=$*_init ${CFLAGS} -o $@ -c $<;\n+\t${AM_VERBOSE_CC} ${CC} ${AM_CPPFLAGS} ${AM_DEPFLAGS} ${AM_CFLAGS} -D_INIT=$*_init  -DPIC -fPIC ${CFLAGS} -o $@ -c $<;\n \n -include .*.d\n \n@@ -164,22 +164,22 @@ xt_connlabel_LIBADD = @libnetfilter_conn\n #\thandling code in the Makefiles.\n #\n lib%.o: ${srcdir}/lib%.c\n-\t${AM_VERBOSE_CC} ${CC} ${AM_CPPFLAGS} ${AM_DEPFLAGS} ${AM_CFLAGS} -DNO_SHARED_LIBS=1 -D_INIT=lib$*_init ${CFLAGS} -o $@ -c $<;\n+\t${AM_VERBOSE_CC} ${CC} ${AM_CPPFLAGS} ${AM_DEPFLAGS} ${AM_CFLAGS} -DNO_SHARED_LIBS=1 -D_INIT=lib$*_init -DPIC -fPIC ${CFLAGS} -o $@ -c $<;\n \n-libext.a: initext.o ${libext_objs}\n-\t${AM_VERBOSE_AR} ${AR} crs $@ $^;\n+libiptext.so: initext.o ${libext_objs}\n+\t${AM_VERBOSE_CCLD} ${CCLD} ${AM_LDFLAGS} -shared ${LDFLAGS} -o $@ $^ -L../libxtables/.libs -lxtables $(foreach obj,$^,${$(patsubst lib%.o,%,$(obj))_LIBADD});\n \n-libext_ebt.a: initextb.o ${libext_ebt_objs}\n-\t${AM_VERBOSE_AR} ${AR} crs $@ $^;\n+libiptext_ebt.so: initextb.o ${libext_ebt_objs}\n+\t${AM_VERBOSE_CCLD} ${CCLD} ${AM_LDFLAGS} -shared ${LDFLAGS} -o $@ $^ -L../libxtables/.libs -lxtables $(foreach obj,$^,${$(patsubst lib%.o,%,$(obj))_LIBADD});\n \n-libext_arpt.a: initexta.o ${libext_arpt_objs}\n-\t${AM_VERBOSE_AR} ${AR} crs $@ $^;\n+libiptext_arpt.so: initexta.o ${libext_arpt_objs}\n+\t${AM_VERBOSE_CCLD} ${CCLD} ${AM_LDFLAGS} -shared ${LDFLAGS} -o $@ $^ -L../libxtables/.libs -lxtables $(foreach obj,$^,${$(patsubst lib%.o,%,$(obj))_LIBADD});\n \n-libext4.a: initext4.o ${libext4_objs}\n-\t${AM_VERBOSE_AR} ${AR} crs $@ $^;\n+libiptext4.so: initext4.o ${libext4_objs}\n+\t${AM_VERBOSE_CCLD} ${CCLD} ${AM_LDFLAGS} -shared ${LDFLAGS} -o $@ $^ -L../libxtables/.libs -lxtables $(foreach obj,$^,${$(patsubst lib%.o,%,$(obj))_LIBADD});\n \n-libext6.a: initext6.o ${libext6_objs}\n-\t${AM_VERBOSE_AR} ${AR} crs $@ $^;\n+libiptext6.so: initext6.o ${libext6_objs}\n+\t${AM_VERBOSE_CCLD} ${CCLD} ${AM_LDFLAGS} -shared ${LDFLAGS} -o $@ $^ -L../libxtables/.libs -lxtables $(foreach obj,$^,${$(patsubst lib%.o,%,$(obj))_LIBADD});\n \n initext_func  := $(addprefix xt_,${pfx_build_static})\n initextb_func := $(addprefix ebt_,${pfb_build_static})\n--- a/iptables/Makefile.am\n+++ b/iptables/Makefile.am\n@@ -7,19 +7,22 @@ BUILT_SOURCES =\n \n xtables_legacy_multi_SOURCES  = xtables-legacy-multi.c iptables-xml.c\n xtables_legacy_multi_CFLAGS   = ${AM_CFLAGS}\n-xtables_legacy_multi_LDADD    = ../extensions/libext.a\n+xtables_legacy_multi_LDADD    =\n+xtables_legacy_multi_LDFLAGS  = -L../extensions/ -liptext\n if ENABLE_STATIC\n xtables_legacy_multi_CFLAGS  += -DALL_INCLUSIVE\n endif\n if ENABLE_IPV4\n xtables_legacy_multi_SOURCES += iptables-standalone.c iptables.c\n xtables_legacy_multi_CFLAGS  += -DENABLE_IPV4\n-xtables_legacy_multi_LDADD   += ../libiptc/libip4tc.la ../extensions/libext4.a\n+xtables_legacy_multi_LDADD   += ../libiptc/libip4tc.la\n+xtables_legacy_multi_LDFLAGS += -liptext4\n endif\n if ENABLE_IPV6\n xtables_legacy_multi_SOURCES += ip6tables-standalone.c ip6tables.c\n xtables_legacy_multi_CFLAGS  += -DENABLE_IPV6\n-xtables_legacy_multi_LDADD   += ../libiptc/libip6tc.la ../extensions/libext6.a\n+xtables_legacy_multi_LDADD   += ../libiptc/libip6tc.la\n+xtables_legacy_multi_LDFLAGS += -liptext6\n endif\n xtables_legacy_multi_SOURCES += xshared.c iptables-restore.c iptables-save.c\n xtables_legacy_multi_LDADD   += ../libxtables/libxtables.la -lm\n@@ -28,7 +31,8 @@ xtables_legacy_multi_LDADD   += ../libxt\n if ENABLE_NFTABLES\n xtables_nft_multi_SOURCES  = xtables-nft-multi.c iptables-xml.c\n xtables_nft_multi_CFLAGS   = ${AM_CFLAGS}\n-xtables_nft_multi_LDADD    = ../extensions/libext.a ../extensions/libext_ebt.a\n+xtables_nft_multi_LDADD    =\n+xtables_nft_multi_LDFLAGS  = -L../extensions/ -liptext -liptext_ebt\n if ENABLE_STATIC\n xtables_nft_multi_CFLAGS  += -DALL_INCLUSIVE\n endif\n@@ -42,7 +46,8 @@ xtables_nft_multi_SOURCES += xtables-sav\n \t\t\t\txtables-eb-standalone.c xtables-eb.c \\\n \t\t\t\txtables-eb-translate.c \\\n \t\t\t\txtables-translate.c\n-xtables_nft_multi_LDADD   += ${libmnl_LIBS} ${libnftnl_LIBS} ${libnetfilter_conntrack_LIBS} ../extensions/libext4.a ../extensions/libext6.a ../extensions/libext_ebt.a ../extensions/libext_arpt.a\n+xtables_nft_multi_LDADD   += ${libmnl_LIBS} ${libnftnl_LIBS} ${libnetfilter_conntrack_LIBS}\n+xtables_nft_multi_LDFLAGS += -liptext4 -liptext6 -liptext_arpt\n xtables_nft_multi_SOURCES += xshared.c\n xtables_nft_multi_LDADD   += ../libxtables/libxtables.la -lm\n endif\n"
  },
  {
    "path": "package/network/utils/iptables/patches/700-disable-legacy-revisions.patch",
    "content": "--- a/extensions/libxt_conntrack.c\n+++ b/extensions/libxt_conntrack.c\n@@ -1395,6 +1395,7 @@ static int conntrack3_mt6_xlate(struct x\n }\n \n static struct xtables_match conntrack_mt_reg[] = {\n+#ifndef NO_LEGACY\n \t{\n \t\t.version       = XTABLES_VERSION,\n \t\t.name          = \"conntrack\",\n@@ -1470,6 +1471,7 @@ static struct xtables_match conntrack_mt\n \t\t.alias\t       = conntrack_print_name_alias,\n \t\t.x6_options    = conntrack2_mt_opts,\n \t},\n+#endif\n \t{\n \t\t.version       = XTABLES_VERSION,\n \t\t.name          = \"conntrack\",\n@@ -1502,6 +1504,7 @@ static struct xtables_match conntrack_mt\n \t\t.x6_options    = conntrack3_mt_opts,\n \t\t.xlate\t       = conntrack3_mt6_xlate,\n \t},\n+#ifndef NO_LEGACY\n \t{\n \t\t.family        = NFPROTO_UNSPEC,\n \t\t.name          = \"state\",\n@@ -1532,6 +1535,8 @@ static struct xtables_match conntrack_mt\n \t\t.x6_parse      = state_ct23_parse,\n \t\t.x6_options    = state_opts,\n \t},\n+#endif\n+#ifndef NO_LEGACY\n \t{\n \t\t.family        = NFPROTO_UNSPEC,\n \t\t.name          = \"state\",\n@@ -1561,6 +1566,7 @@ static struct xtables_match conntrack_mt\n \t\t.x6_parse      = state_parse,\n \t\t.x6_options    = state_opts,\n \t},\n+#endif\n };\n \n void _init(void)\n--- a/extensions/libxt_CT.c\n+++ b/extensions/libxt_CT.c\n@@ -363,6 +363,7 @@ static int xlate_ct1_tg(struct xt_xlate\n }\n \n static struct xtables_target ct_target_reg[] = {\n+#ifndef NO_LEGACY\n \t{\n \t\t.family\t\t= NFPROTO_UNSPEC,\n \t\t.name\t\t= \"CT\",\n@@ -388,6 +389,7 @@ static struct xtables_target ct_target_r\n \t\t.x6_parse\t= ct_parse_v1,\n \t\t.x6_options\t= ct_opts_v1,\n \t},\n+#endif\n \t{\n \t\t.family\t\t= NFPROTO_UNSPEC,\n \t\t.name\t\t= \"CT\",\n@@ -403,6 +405,7 @@ static struct xtables_target ct_target_r\n \t\t.x6_options\t= ct_opts_v1,\n \t\t.xlate\t\t= xlate_ct1_tg,\n \t},\n+#ifndef NO_LEGACY\n \t{\n \t\t.family        = NFPROTO_UNSPEC,\n \t\t.name          = \"NOTRACK\",\n@@ -441,6 +444,7 @@ static struct xtables_target ct_target_r\n \t\t.revision      = 0,\n \t\t.version       = XTABLES_VERSION,\n \t},\n+#endif\n };\n \n void _init(void)\n--- a/extensions/libxt_multiport.c\n+++ b/extensions/libxt_multiport.c\n@@ -571,6 +571,7 @@ static int multiport_xlate6_v1(struct xt\n }\n \n static struct xtables_match multiport_mt_reg[] = {\n+#ifndef NO_LEGACY\n \t{\n \t\t.family        = NFPROTO_IPV4,\n \t\t.name          = \"multiport\",\n@@ -601,6 +602,7 @@ static struct xtables_match multiport_mt\n \t\t.x6_options    = multiport_opts,\n \t\t.xlate         = multiport_xlate6,\n \t},\n+#endif\n \t{\n \t\t.family        = NFPROTO_IPV4,\n \t\t.name          = \"multiport\",\n"
  },
  {
    "path": "package/network/utils/iptables/patches/800-flowoffload_target.patch",
    "content": "--- /dev/null\n+++ b/extensions/libxt_FLOWOFFLOAD.c\n@@ -0,0 +1,72 @@\n+#include <stdio.h>\n+#include <xtables.h>\n+#include <linux/netfilter/xt_FLOWOFFLOAD.h>\n+\n+enum {\n+    O_HW,\n+};\n+\n+static void offload_help(void)\n+{\n+\tprintf(\n+\"FLOWOFFLOAD target options:\\n\"\n+\" --hw\t\t\t\tEnable hardware offload\\n\"\n+\t);\n+}\n+\n+static const struct xt_option_entry offload_opts[] = {\n+\t{.name = \"hw\", .id = O_HW, .type = XTTYPE_NONE},\n+\tXTOPT_TABLEEND,\n+};\n+\n+static void offload_parse(struct xt_option_call *cb)\n+{\n+\tstruct xt_flowoffload_target_info *info = cb->data;\n+\n+\txtables_option_parse(cb);\n+\tswitch (cb->entry->id) {\n+\tcase O_HW:\n+\t\tinfo->flags |= XT_FLOWOFFLOAD_HW;\n+\t\tbreak;\n+\t}\n+}\n+\n+static void offload_print(const void *ip, const struct xt_entry_target *target, int numeric)\n+{\n+\tconst struct xt_flowoffload_target_info *info =\n+\t\t(const struct xt_flowoffload_target_info *)target->data;\n+\n+\tprintf(\" FLOWOFFLOAD\");\n+\tif (info->flags & XT_FLOWOFFLOAD_HW)\n+\t\tprintf(\" hw\");\n+}\n+\n+static void offload_save(const void *ip, const struct xt_entry_target *target)\n+{\n+\tconst struct xt_flowoffload_target_info *info =\n+\t\t(const struct xt_flowoffload_target_info *)target->data;\n+\n+\tif (info->flags & XT_FLOWOFFLOAD_HW)\n+\t\tprintf(\" --hw\");\n+}\n+\n+static struct xtables_target offload_tg_reg[] = {\n+\t{\n+\t\t.family\t\t= NFPROTO_UNSPEC,\n+\t\t.name\t\t= \"FLOWOFFLOAD\",\n+\t\t.revision\t= 0,\n+\t\t.version\t= XTABLES_VERSION,\n+\t\t.size\t\t= XT_ALIGN(sizeof(struct xt_flowoffload_target_info)),\n+\t\t.userspacesize\t= sizeof(struct xt_flowoffload_target_info),\n+\t\t.help\t\t= offload_help,\n+\t\t.print\t\t= offload_print,\n+\t\t.save\t\t= offload_save,\n+\t\t.x6_parse\t= offload_parse,\n+\t\t.x6_options\t= offload_opts,\n+\t},\n+};\n+\n+void _init(void)\n+{\n+\txtables_register_targets(offload_tg_reg, ARRAY_SIZE(offload_tg_reg));\n+}\n--- /dev/null\n+++ b/include/linux/netfilter/xt_FLOWOFFLOAD.h\n@@ -0,0 +1,17 @@\n+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */\n+#ifndef _XT_FLOWOFFLOAD_H\n+#define _XT_FLOWOFFLOAD_H\n+\n+#include <linux/types.h>\n+\n+enum {\n+\tXT_FLOWOFFLOAD_HW\t= 1 << 0,\n+\n+\tXT_FLOWOFFLOAD_MASK\t= XT_FLOWOFFLOAD_HW\n+};\n+\n+struct xt_flowoffload_target_info {\n+\t__u32 flags;\n+};\n+\n+#endif /* _XT_FLOWOFFLOAD_H */\n"
  },
  {
    "path": "package/network/utils/iw/Makefile",
    "content": "#\n# Copyright (C) 2007-2011 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=iw\nPKG_VERSION:=5.16\nPKG_RELEASE:=1\n \nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz\nPKG_SOURCE_URL:=@KERNEL/software/network/iw\nPKG_HASH:=4c44e42762f903f9094ba5a598998c800a97a62afd6fd31ec1e0a799e308659c\n\nPKG_MAINTAINER:=Felix Fietkau <nbd@nbd.name>\nPKG_LICENSE:=GPL-2.0\n\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine Package/iw\n  SECTION:=net\n  CATEGORY:=Network\n  TITLE:=cfg80211 interface configuration utility\n  URL:=http://wireless.kernel.org/en/users/Documentation/iw\n  DEPENDS:= +libnl-tiny\n  VARIANT:=tiny\nendef\n\ndefine Package/iw-full\n  $(Package/iw)\n  TITLE += (full version)\n  VARIANT:=full\n  PROVIDES:=iw\nendef\n\ndefine Build/Configure\n\techo \"const char iw_version[] = \\\"$(PKG_VERSION)\\\";\" > $(PKG_BUILD_DIR)/version.c\n\techo \"#!/bin/sh\" > $(PKG_BUILD_DIR)/version.sh\n\tchmod +x $(PKG_BUILD_DIR)/version.sh\nendef\n\nTARGET_CPPFLAGS:= \\\n\t-I$(STAGING_DIR)/usr/include/libnl-tiny \\\n\t$(TARGET_CPPFLAGS) \\\n\t-DCONFIG_LIBNL20 \\\n\t-D_GNU_SOURCE \\\n\t-flto\n\nifeq ($(BUILD_VARIANT),full)\n  TARGET_CPPFLAGS += -DIW_FULL\n  MAKE_FLAGS += IW_FULL=1\nendif\n\nMAKE_FLAGS += \\\n\tCFLAGS=\"$(TARGET_CPPFLAGS) $(TARGET_CFLAGS) -ffunction-sections -fdata-sections\" \\\n\tLDFLAGS=\"$(TARGET_LDFLAGS) -Wl,--gc-sections -flto\" \\\n\tNL1FOUND=\"\" NL2FOUND=Y \\\n\tNLLIBNAME=\"libnl-tiny\" \\\n\tLIBS=\"-lm -lnl-tiny\" \\\n\tV=1\n\ndefine Package/iw/install\n\t$(INSTALL_DIR) $(1)/usr/sbin\n\t$(INSTALL_BIN) $(PKG_BUILD_DIR)/iw $(1)/usr/sbin/\nendef\n\nPackage/iw-full/install=$(Package/iw/install)\n\n$(eval $(call BuildPackage,iw))\n$(eval $(call BuildPackage,iw-full))\n"
  },
  {
    "path": "package/network/utils/iw/patches/001-nl80211_h_sync.patch",
    "content": "--- a/nl80211.h\n+++ b/nl80211.h\n@@ -301,29 +301,6 @@\n  */\n \n /**\n- * DOC: FILS shared key crypto offload\n- *\n- * This feature is applicable to drivers running in AP mode.\n- *\n- * FILS shared key crypto offload can be advertised by drivers by setting\n- * @NL80211_EXT_FEATURE_FILS_CRYPTO_OFFLOAD flag. The drivers that support\n- * FILS shared key crypto offload should be able to encrypt and decrypt\n- * association frames for FILS shared key authentication as per IEEE 802.11ai.\n- * With this capability, for FILS key derivation, drivers depend on userspace.\n- *\n- * After FILS key derivation, userspace shares the FILS AAD details with the\n- * driver and the driver stores the same to use in decryption of association\n- * request and in encryption of association response. The below parameters\n- * should be given to the driver in %NL80211_CMD_SET_FILS_AAD.\n- *\t%NL80211_ATTR_MAC - STA MAC address, used for storing FILS AAD per STA\n- *\t%NL80211_ATTR_FILS_KEK - Used for encryption or decryption\n- *\t%NL80211_ATTR_FILS_NONCES - Used for encryption or decryption\n- *\t\t\t(STA Nonce 16 bytes followed by AP Nonce 16 bytes)\n- *\n- * Once the association is done, the driver cleans the FILS AAD data.\n- */\n-\n-/**\n  * enum nl80211_commands - supported nl80211 commands\n  *\n  * @NL80211_CMD_UNSPEC: unspecified command to catch errors\n@@ -1226,12 +1203,6 @@\n  * @NL80211_CMD_COLOR_CHANGE_COMPLETED: Notify userland that the color change\n  *\thas completed\n  *\n- * @NL80211_CMD_SET_FILS_AAD: Set FILS AAD data to the driver using -\n- *\t&NL80211_ATTR_MAC - for STA MAC address\n- *\t&NL80211_ATTR_FILS_KEK - for KEK\n- *\t&NL80211_ATTR_FILS_NONCES - for FILS Nonces\n- *\t\t(STA Nonce 16 bytes followed by AP Nonce 16 bytes)\n- *\n  * @NL80211_CMD_MAX: highest used command number\n  * @__NL80211_CMD_AFTER_LAST: internal use\n  */\n@@ -1472,8 +1443,6 @@ enum nl80211_commands {\n \tNL80211_CMD_COLOR_CHANGE_ABORTED,\n \tNL80211_CMD_COLOR_CHANGE_COMPLETED,\n \n-\tNL80211_CMD_SET_FILS_AAD,\n-\n \t/* add new commands above here */\n \n \t/* used to define NL80211_CMD_MAX below */\n@@ -2639,6 +2608,9 @@ enum nl80211_commands {\n  *\tMandatory parameter for the transmitting interface to enable MBSSID.\n  *\tOptional for the non-transmitting interfaces.\n  *\n+ * @NL80211_ATTR_WIPHY_ANTENNA_GAIN: Configured antenna gain. Used to reduce\n+ *\ttransmit power to stay within regulatory limits. u32, dBi.\n+ *\n  * @NUM_NL80211_ATTR: total number of nl80211_attrs available\n  * @NL80211_ATTR_MAX: highest attribute number currently defined\n  * @__NL80211_ATTR_AFTER_LAST: internal use\n@@ -3145,6 +3117,8 @@ enum nl80211_attrs {\n \tNL80211_ATTR_MBSSID_CONFIG,\n \tNL80211_ATTR_MBSSID_ELEMS,\n \n+\tNL80211_ATTR_WIPHY_ANTENNA_GAIN,\n+\n \t/* add attributes here, update the policy in nl80211.c */\n \n \t__NL80211_ATTR_AFTER_LAST,\n@@ -4978,7 +4952,6 @@ enum nl80211_txrate_gi {\n  * @NL80211_BAND_60GHZ: around 60 GHz band (58.32 - 69.12 GHz)\n  * @NL80211_BAND_6GHZ: around 6 GHz band (5.9 - 7.2 GHz)\n  * @NL80211_BAND_S1GHZ: around 900MHz, supported by S1G PHYs\n- * @NL80211_BAND_LC: light communication band (placeholder)\n  * @NUM_NL80211_BANDS: number of bands, avoid using this in userspace\n  *\tsince newer kernel versions may support more bands\n  */\n@@ -4988,7 +4961,6 @@ enum nl80211_band {\n \tNL80211_BAND_60GHZ,\n \tNL80211_BAND_6GHZ,\n \tNL80211_BAND_S1GHZ,\n-\tNL80211_BAND_LC,\n \n \tNUM_NL80211_BANDS,\n };\n@@ -6046,11 +6018,6 @@ enum nl80211_feature_flags {\n  * @NL80211_EXT_FEATURE_BSS_COLOR: The driver supports BSS color collision\n  *\tdetection and change announcemnts.\n  *\n- * @NL80211_EXT_FEATURE_FILS_CRYPTO_OFFLOAD: Driver running in AP mode supports\n- *\tFILS encryption and decryption for (Re)Association Request and Response\n- *\tframes. Userspace has to share FILS AAD details to the driver by using\n- *\t@NL80211_CMD_SET_FILS_AAD.\n- *\n  * @NUM_NL80211_EXT_FEATURES: number of extended features.\n  * @MAX_NL80211_EXT_FEATURES: highest extended feature index.\n  */\n@@ -6116,7 +6083,6 @@ enum nl80211_ext_feature_index {\n \tNL80211_EXT_FEATURE_SECURE_RTT,\n \tNL80211_EXT_FEATURE_PROT_RANGE_NEGO_AND_MEASURE,\n \tNL80211_EXT_FEATURE_BSS_COLOR,\n-\tNL80211_EXT_FEATURE_FILS_CRYPTO_OFFLOAD,\n \n \t/* add new features before the definition below */\n \tNUM_NL80211_EXT_FEATURES,\n@@ -7424,7 +7390,7 @@ enum nl80211_sar_specs_attrs {\n  * @NL80211_MBSSID_CONFIG_ATTR_MAX_EMA_PROFILE_PERIODICITY: Used by the kernel\n  *\tto advertise the maximum profile periodicity supported by the driver\n  *\tif EMA is enabled. Driver should indicate EMA support to the userspace\n- *\tby setting wiphy->ema_max_profile_periodicity to\n+ *\tby setting wiphy->mbssid_max_ema_profile_periodicity to\n  *\ta non-zero value.\n  *\n  * @NL80211_MBSSID_CONFIG_ATTR_INDEX: Mandatory parameter to pass the index of\n@@ -7443,7 +7409,7 @@ enum nl80211_sar_specs_attrs {\n  *\n  * @NL80211_MBSSID_CONFIG_ATTR_EMA: Flag used to enable EMA AP feature.\n  *\tSetting this flag is permitted only if the driver advertises EMA support\n- *\tby setting wiphy->ema_max_profile_periodicity to non-zero.\n+ *\tby setting wiphy->mbssid_max_ema_profile_periodicity to non-zero.\n  *\n  * @__NL80211_MBSSID_CONFIG_ATTR_LAST: Internal\n  * @NL80211_MBSSID_CONFIG_ATTR_MAX: highest attribute\n--- a/info.c\n+++ b/info.c\n@@ -701,7 +701,6 @@ broken_combination:\n \t\text_feat_print(tb, OPERATING_CHANNEL_VALIDATION, \"Operating Channel Validation (OCV) support\");\n \t\text_feat_print(tb, 4WAY_HANDSHAKE_AP_PSK, \"AP mode PSK offload support\");\n \t\text_feat_print(tb, BSS_COLOR, \"BSS coloring support\");\n-\t\text_feat_print(tb, FILS_CRYPTO_OFFLOAD, \"FILS crypto offload\");\n \t}\n \n \tif (tb_msg[NL80211_ATTR_COALESCE_RULE]) {\n"
  },
  {
    "path": "package/network/utils/iw/patches/010-Revert-iw-allow-specifying-CFLAGS-LIBS-externally.patch",
    "content": "From 1f3706d10812d70adefe32fe0d7d3a3ec25374f0 Mon Sep 17 00:00:00 2001\nFrom: Hauke Mehrtens <hauke@hauke-m.de>\nDate: Sun, 21 Nov 2021 00:02:57 +0100\nSubject: Revert \"iw: allow specifying CFLAGS/LIBS externally\"\n\nThis reverts commit 1325244b77d56fd7a16d1e35fdae0efc151920b1.\n\nThe OpenWrt build system provides the CFLAGS and LIBS names from the \npackage Makefile to overwrite them for libnl-tiny. This is not possible \nafter this upstream change which we revert here any more\n\nSigned-off-by: Hauke Mehrtens <hauke@hauke-m.de>\n---\n Makefile | 20 ++++++++++----------\n 1 file changed, 10 insertions(+), 10 deletions(-)\n\n--- a/Makefile\n+++ b/Makefile\n@@ -45,30 +45,30 @@ NLLIBNAME = libnl-1\n endif\n \n ifeq ($(NL2FOUND),Y)\n-override CFLAGS += -DCONFIG_LIBNL20\n-override LIBS += -lnl-genl\n+CFLAGS += -DCONFIG_LIBNL20\n+LIBS += -lnl-genl\n NLLIBNAME = libnl-2.0\n endif\n \n ifeq ($(NL3xFOUND),Y)\n # libnl 3.2 might be found as 3.2 and 3.0\n NL3FOUND = N\n-override CFLAGS += -DCONFIG_LIBNL30\n-override LIBS += -lnl-genl-3\n+CFLAGS += -DCONFIG_LIBNL30\n+LIBS += -lnl-genl-3\n NLLIBNAME = libnl-3.0\n endif\n \n ifeq ($(NL3FOUND),Y)\n-override CFLAGS += -DCONFIG_LIBNL30\n-override LIBS += -lnl-genl\n+CFLAGS += -DCONFIG_LIBNL30\n+LIBS += -lnl-genl\n NLLIBNAME = libnl-3.0\n endif\n \n # nl-3.1 has a broken libnl-gnl-3.1.pc file\n # as show by pkg-config --debug --libs --cflags --exact-version=3.1 libnl-genl-3.1;echo $?\n ifeq ($(NL31FOUND),Y)\n-override CFLAGS += -DCONFIG_LIBNL30\n-override LIBS += -lnl-genl\n+CFLAGS += -DCONFIG_LIBNL30\n+LIBS += -lnl-genl\n NLLIBNAME = libnl-3.1\n endif\n \n@@ -76,8 +76,8 @@ ifeq ($(NLLIBNAME),)\n $(error Cannot find development files for any supported version of libnl)\n endif\n \n-override LIBS += $(shell $(PKG_CONFIG) --libs $(NLLIBNAME))\n-override CFLAGS += $(shell $(PKG_CONFIG) --cflags $(NLLIBNAME))\n+LIBS += $(shell $(PKG_CONFIG) --libs $(NLLIBNAME))\n+CFLAGS += $(shell $(PKG_CONFIG) --cflags $(NLLIBNAME))\n endif # NO_PKG_CONFIG\n \n ifeq ($(V),1)\n"
  },
  {
    "path": "package/network/utils/iw/patches/120-antenna_gain.patch",
    "content": "--- a/phy.c\n+++ b/phy.c\n@@ -855,3 +855,30 @@ static int handle_get_txq(struct nl80211\n COMMAND(get, txq, \"\",\n \tNL80211_CMD_GET_WIPHY, 0, CIB_PHY, handle_get_txq,\n \t\"Get TXQ parameters.\");\n+\n+static int handle_antenna_gain(struct nl80211_state *state,\n+\t\t\t       struct nl_msg *msg,\n+\t\t\t       int argc, char **argv,\n+\t\t\t       enum id_input id)\n+{\n+\tchar *endptr;\n+\tint dbm;\n+\n+\t/* get the required args */\n+\tif (argc != 1)\n+\t\treturn 1;\n+\n+\tdbm = strtol(argv[0], &endptr, 10);\n+\tif (*endptr)\n+\t\treturn 2;\n+\n+\tNLA_PUT_U32(msg, NL80211_ATTR_WIPHY_ANTENNA_GAIN, dbm);\n+\n+\treturn 0;\n+\n+ nla_put_failure:\n+\treturn -ENOBUFS;\n+}\n+COMMAND(set, antenna_gain, \"<antenna gain in dBm>\",\n+\tNL80211_CMD_SET_WIPHY, 0, CIB_PHY, handle_antenna_gain,\n+\t\"Specify antenna gain.\");\n"
  },
  {
    "path": "package/network/utils/iw/patches/130-survey-bss-rx-time.patch",
    "content": "--- a/survey.c\n+++ b/survey.c\n@@ -60,6 +60,9 @@ static int print_survey_handler(struct n\n \tif (sinfo[NL80211_SURVEY_INFO_CHANNEL_TIME_RX])\n \t\tprintf(\"\\tchannel receive time:\\t\\t%llu ms\\n\",\n \t\t\t(unsigned long long)nla_get_u64(sinfo[NL80211_SURVEY_INFO_CHANNEL_TIME_RX]));\n+\tif (sinfo[NL80211_SURVEY_INFO_TIME_BSS_RX])\n+\t\tprintf(\"\\tchannel BSS receive time:\\t%llu ms\\n\",\n+\t\t\t(unsigned long long)nla_get_u64(sinfo[NL80211_SURVEY_INFO_TIME_BSS_RX]));\n \tif (sinfo[NL80211_SURVEY_INFO_CHANNEL_TIME_TX])\n \t\tprintf(\"\\tchannel transmit time:\\t\\t%llu ms\\n\",\n \t\t\t(unsigned long long)nla_get_u64(sinfo[NL80211_SURVEY_INFO_CHANNEL_TIME_TX]));\n"
  },
  {
    "path": "package/network/utils/iw/patches/200-reduce_size.patch",
    "content": "--- a/event.c\n+++ b/event.c\n@@ -956,6 +956,7 @@ static int print_event(struct nl_msg *ms\n \t}\n \n \tswitch (gnlh->cmd) {\n+#ifdef IW_FULL\n \tcase NL80211_CMD_NEW_WIPHY:\n \t\tprintf(\"renamed to %s\\n\", nla_get_string(tb[NL80211_ATTR_WIPHY_NAME]));\n \t\tbreak;\n@@ -991,6 +992,7 @@ static int print_event(struct nl_msg *ms\n \tcase NL80211_CMD_SCHED_SCAN_RESULTS:\n \t\tprintf(\"got scheduled scan results\\n\");\n \t\tbreak;\n+#endif\n \tcase NL80211_CMD_WIPHY_REG_CHANGE:\n \tcase NL80211_CMD_REG_CHANGE:\n \t\tif (gnlh->cmd == NL80211_CMD_WIPHY_REG_CHANGE)\n@@ -1073,6 +1075,7 @@ static int print_event(struct nl_msg *ms\n \t\tmac_addr_n2a(macbuf, nla_data(tb[NL80211_ATTR_MAC]));\n \t\tprintf(\"del station %s\\n\", macbuf);\n \t\tbreak;\n+#ifdef IW_FULL\n \tcase NL80211_CMD_JOIN_IBSS:\n \t\tmac_addr_n2a(macbuf, nla_data(tb[NL80211_ATTR_MAC]));\n \t\tprintf(\"IBSS %s joined\\n\", macbuf);\n@@ -1271,9 +1274,9 @@ static int print_event(struct nl_msg *ms\n \tcase NL80211_CMD_CH_SWITCH_NOTIFY:\n \t\tparse_ch_switch_notify(tb, gnlh->cmd);\n \t\tbreak;\n+#endif\n \tdefault:\n-\t\tprintf(\"unknown event %d (%s)\\n\",\n-\t\t       gnlh->cmd, command_name(gnlh->cmd));\n+\t\tprintf(\"unknown event %d\\n\", gnlh->cmd);\n \t\tbreak;\n \t}\n \n--- a/info.c\n+++ b/info.c\n@@ -215,6 +215,7 @@ next:\n \t\t\t\t}\n \t\t\t}\n \n+#ifdef IW_FULL\n \t\t\tif (tb_band[NL80211_BAND_ATTR_RATES]) {\n \t\t\tprintf(\"\\t\\tBitrates (non-HT):\\n\");\n \t\t\tnla_for_each_nested(nl_rate, tb_band[NL80211_BAND_ATTR_RATES], rem_rate) {\n@@ -231,6 +232,7 @@ next:\n \t\t\t\tprintf(\"\\n\");\n \t\t\t}\n \t\t\t}\n+#endif\n \t\t}\n \t}\n \n@@ -296,6 +298,7 @@ next:\n \t\tprintf(\"\\tCoverage class: %d (up to %dm)\\n\", coverage, 450 * coverage);\n \t}\n \n+#ifdef IW_FULL\n \tif (tb_msg[NL80211_ATTR_CIPHER_SUITES]) {\n \t\tint num = nla_len(tb_msg[NL80211_ATTR_CIPHER_SUITES]) / sizeof(__u32);\n \t\tint i;\n@@ -307,6 +310,7 @@ next:\n \t\t\t\t\tcipher_name(ciphers[i]));\n \t\t}\n \t}\n+#endif\n \n \tif (tb_msg[NL80211_ATTR_WIPHY_ANTENNA_AVAIL_TX] &&\n \t    tb_msg[NL80211_ATTR_WIPHY_ANTENNA_AVAIL_RX])\n@@ -324,9 +328,11 @@ next:\n \t\tprint_iftype_list(\"\\tSupported interface modes\", \"\\t\\t\",\n \t\t\t\t  tb_msg[NL80211_ATTR_SUPPORTED_IFTYPES]);\n \n+#ifdef IW_FULL\n \tif (tb_msg[NL80211_ATTR_SOFTWARE_IFTYPES])\n \t\tprint_iftype_list(\"\\tsoftware interface modes (can always be added)\",\n \t\t\t\t  \"\\t\\t\", tb_msg[NL80211_ATTR_SOFTWARE_IFTYPES]);\n+#endif\n \n \tif (tb_msg[NL80211_ATTR_INTERFACE_COMBINATIONS]) {\n \t\tstruct nlattr *nl_combi;\n@@ -416,6 +422,7 @@ broken_combination:\n \t\t\tprintf(\"\\tinterface combinations are not supported\\n\");\n \t}\n \n+#ifdef IW_FULL\n \tif (tb_msg[NL80211_ATTR_SUPPORTED_COMMANDS]) {\n \t\tprintf(\"\\tSupported commands:\\n\");\n \t\tnla_for_each_nested(nl_cmd, tb_msg[NL80211_ATTR_SUPPORTED_COMMANDS], rem_cmd)\n@@ -513,6 +520,7 @@ broken_combination:\n \t\t\t\tprintf(\"\\t\\t * wake up on TCP connection\\n\");\n \t\t}\n \t}\n+#endif\n \n \tif (tb_msg[NL80211_ATTR_ROAM_SUPPORT])\n \t\tprintf(\"\\tDevice supports roaming.\\n\");\n@@ -551,6 +559,7 @@ broken_combination:\n \t\t}\n \t}\n \n+#ifdef IW_FULL\n \tif (tb_msg[NL80211_ATTR_FEATURE_FLAGS]) {\n \t\tunsigned int features = nla_get_u32(tb_msg[NL80211_ATTR_FEATURE_FLAGS]);\n \n@@ -615,6 +624,7 @@ broken_combination:\n \t\tif (features & NL80211_FEATURE_ND_RANDOM_MAC_ADDR)\n \t\t\tprintf(\"\\tDevice supports randomizing MAC-addr in net-detect scans.\\n\");\n \t}\n+#endif\n \n \tif (tb_msg[NL80211_ATTR_TDLS_SUPPORT])\n \t\tprintf(\"\\tDevice supports T-DLS.\\n\");\n@@ -751,6 +761,7 @@ TOPLEVEL(list, NULL, NL80211_CMD_GET_WIP\n \t \"List all wireless devices and their capabilities.\");\n TOPLEVEL(phy, NULL, NL80211_CMD_GET_WIPHY, NLM_F_DUMP, CIB_NONE, handle_info, NULL);\n \n+#ifdef IW_FULL\n static int handle_commands(struct nl80211_state *state, struct nl_msg *msg,\n \t\t\t   int argc, char **argv, enum id_input id)\n {\n@@ -762,6 +773,7 @@ static int handle_commands(struct nl8021\n }\n TOPLEVEL(commands, NULL, NL80211_CMD_GET_WIPHY, 0, CIB_NONE, handle_commands,\n \t \"list all known commands and their decimal & hex value\");\n+#endif\n \n static int print_feature_handler(struct nl_msg *msg, void *arg)\n {\n--- a/scan.c\n+++ b/scan.c\n@@ -1306,6 +1306,9 @@ static void print_ht_op(const uint8_t ty\n \tprintf(\"\\t\\t * secondary channel offset: %s\\n\",\n \t\tht_secondary_offset[data[1] & 0x3]);\n \tprintf(\"\\t\\t * STA channel width: %s\\n\", sta_chan_width[(data[1] & 0x4)>>2]);\n+#ifndef IW_FULL\n+\treturn;\n+#endif\n \tprintf(\"\\t\\t * RIFS: %d\\n\", (data[1] & 0x8)>>3);\n \tprintf(\"\\t\\t * HT protection: %s\\n\", protection[data[2] & 0x3]);\n \tprintf(\"\\t\\t * non-GF present: %d\\n\", (data[2] & 0x4) >> 2);\n@@ -1716,6 +1719,14 @@ static void print_ie(const struct ie_pri\n \n static const struct ie_print ieprinters[] = {\n \t[0] = { \"SSID\", print_ssid, 0, 32, BIT(PRINT_SCAN) | BIT(PRINT_LINK), },\n+\t[45] = { \"HT capabilities\", print_ht_capa, 26, 26, BIT(PRINT_SCAN), },\n+\t[48] = { \"RSN\", print_rsn, 2, 255, BIT(PRINT_SCAN), },\n+\t[61] = { \"HT operation\", print_ht_op, 22, 22, BIT(PRINT_SCAN), },\n+\t[62] = { \"Secondary Channel Offset\", print_secchan_offs, 1, 1, BIT(PRINT_SCAN), },\n+\t[114] = { \"MESH ID\", print_ssid, 0, 32, BIT(PRINT_SCAN) | BIT(PRINT_LINK), },\n+\t[191] = { \"VHT capabilities\", print_vht_capa, 12, 255, BIT(PRINT_SCAN), },\n+\t[192] = { \"VHT operation\", print_vht_oper, 5, 255, BIT(PRINT_SCAN), },\n+#ifdef IW_FULL\n \t[1] = { \"Supported rates\", print_supprates, 0, 255, BIT(PRINT_SCAN), },\n \t[3] = { \"DS Parameter set\", print_ds, 1, 1, BIT(PRINT_SCAN), },\n \t[5] = { \"TIM\", print_tim, 4, 255, BIT(PRINT_SCAN), },\n@@ -1725,26 +1736,20 @@ static const struct ie_print ieprinters[\n \t[32] = { \"Power constraint\", print_powerconstraint, 1, 1, BIT(PRINT_SCAN), },\n \t[35] = { \"TPC report\", print_tpcreport, 2, 2, BIT(PRINT_SCAN), },\n \t[42] = { \"ERP\", print_erp, 1, 255, BIT(PRINT_SCAN), },\n-\t[45] = { \"HT capabilities\", print_ht_capa, 26, 26, BIT(PRINT_SCAN), },\n \t[47] = { \"ERP D4.0\", print_erp, 1, 255, BIT(PRINT_SCAN), },\n \t[51] = { \"AP Channel Report\", print_ap_channel_report, 1, 255, BIT(PRINT_SCAN), },\n \t[59] = { \"Supported operating classes\", print_supp_op_classes, 1, 255, BIT(PRINT_SCAN), },\n \t[66] = { \"Measurement Pilot Transmission\", print_measurement_pilot_tx, 1, 255, BIT(PRINT_SCAN), },\n \t[74] = { \"Overlapping BSS scan params\", print_obss_scan_params, 14, 255, BIT(PRINT_SCAN), },\n-\t[61] = { \"HT operation\", print_ht_op, 22, 22, BIT(PRINT_SCAN), },\n-\t[62] = { \"Secondary Channel Offset\", print_secchan_offs, 1, 1, BIT(PRINT_SCAN), },\n-\t[191] = { \"VHT capabilities\", print_vht_capa, 12, 255, BIT(PRINT_SCAN), },\n-\t[192] = { \"VHT operation\", print_vht_oper, 5, 255, BIT(PRINT_SCAN), },\n-\t[48] = { \"RSN\", print_rsn, 2, 255, BIT(PRINT_SCAN), },\n \t[50] = { \"Extended supported rates\", print_supprates, 0, 255, BIT(PRINT_SCAN), },\n \t[70] = { \"RM enabled capabilities\", print_rm_enabled_capabilities, 5, 5, BIT(PRINT_SCAN), },\n \t[113] = { \"MESH Configuration\", print_mesh_conf, 7, 7, BIT(PRINT_SCAN), },\n-\t[114] = { \"MESH ID\", print_ssid, 0, 32, BIT(PRINT_SCAN) | BIT(PRINT_LINK), },\n \t[127] = { \"Extended capabilities\", print_capabilities, 0, 255, BIT(PRINT_SCAN), },\n \t[107] = { \"802.11u Interworking\", print_interworking, 0, 255, BIT(PRINT_SCAN), },\n \t[108] = { \"802.11u Advertisement\", print_11u_advert, 0, 255, BIT(PRINT_SCAN), },\n \t[111] = { \"802.11u Roaming Consortium\", print_11u_rcon, 2, 255, BIT(PRINT_SCAN), },\n \t[195] = { \"Transmit Power Envelope\", print_tx_power_envelope, 2, 5, BIT(PRINT_SCAN), },\n+#endif\n };\n \n static void print_wifi_wpa(const uint8_t type, uint8_t len, const uint8_t *data,\n@@ -2080,8 +2085,10 @@ static void print_wifi_wps(const uint8_t\n \n static const struct ie_print wifiprinters[] = {\n \t[1] = { \"WPA\", print_wifi_wpa, 2, 255, BIT(PRINT_SCAN), },\n+#ifdef IW_FULL\n \t[2] = { \"WMM\", print_wifi_wmm, 1, 255, BIT(PRINT_SCAN), },\n \t[4] = { \"WPS\", print_wifi_wps, 0, 255, BIT(PRINT_SCAN), },\n+#endif\n };\n \n static inline void print_p2p(const uint8_t type, uint8_t len,\n@@ -2244,6 +2251,10 @@ static void print_vendor(unsigned char l\n \t\treturn;\n \t}\n \n+#ifdef IW_FULL\n+\treturn;\n+#endif\n+\n \tif (len >= 4 && memcmp(data, wfa_oui, 3) == 0) {\n \t\tif (data[3] < ARRAY_SIZE(wfa_printers) &&\n \t\t    wfa_printers[data[3]].name &&\n@@ -2377,6 +2388,7 @@ static void print_capa_non_dmg(__u16 cap\n \t\tprintf(\" ESS\");\n \tif (capa & WLAN_CAPABILITY_IBSS)\n \t\tprintf(\" IBSS\");\n+#ifdef IW_FULL\n \tif (capa & WLAN_CAPABILITY_CF_POLLABLE)\n \t\tprintf(\" CfPollable\");\n \tif (capa & WLAN_CAPABILITY_CF_POLL_REQUEST)\n@@ -2405,6 +2417,7 @@ static void print_capa_non_dmg(__u16 cap\n \t\tprintf(\" DelayedBACK\");\n \tif (capa & WLAN_CAPABILITY_IMM_BACK)\n \t\tprintf(\" ImmediateBACK\");\n+#endif\n }\n \n static int print_bss_handler(struct nl_msg *msg, void *arg)\n@@ -2489,8 +2502,10 @@ static int print_bss_handler(struct nl_m\n \tif (bss[NL80211_BSS_FREQUENCY]) {\n \t\tint freq = nla_get_u32(bss[NL80211_BSS_FREQUENCY]);\n \t\tprintf(\"\\tfreq: %d\\n\", freq);\n+#ifdef IW_FULL\n \t\tif (freq > 45000)\n \t\t\tis_dmg = true;\n+#endif\n \t}\n \tif (bss[NL80211_BSS_BEACON_INTERVAL])\n \t\tprintf(\"\\tbeacon interval: %d TUs\\n\",\n@@ -2684,6 +2699,7 @@ static int handle_stop_sched_scan(struct\n \treturn 0;\n }\n \n+#ifdef IW_FULL\n COMMAND(scan, sched_start,\n \tSCHED_SCAN_OPTIONS,\n \tNL80211_CMD_START_SCHED_SCAN, 0, CIB_NETDEV, handle_start_sched_scan,\n@@ -2694,3 +2710,4 @@ COMMAND(scan, sched_start,\n COMMAND(scan, sched_stop, \"\",\n \tNL80211_CMD_STOP_SCHED_SCAN, 0, CIB_NETDEV, handle_stop_sched_scan,\n \t\"Stop an ongoing scheduled scan.\");\n+#endif\n--- a/util.c\n+++ b/util.c\n@@ -153,6 +153,7 @@ static const char *commands[NL80211_CMD_\n \n static char cmdbuf[100];\n \n+#ifdef IW_FULL\n const char *command_name(enum nl80211_commands cmd)\n {\n \tif (cmd <= NL80211_CMD_MAX && commands[cmd])\n@@ -160,6 +161,7 @@ const char *command_name(enum nl80211_co\n \tsprintf(cmdbuf, \"Unknown command (%d)\", cmd);\n \treturn cmdbuf;\n }\n+#endif\n \n int ieee80211_channel_to_frequency(int chan, enum nl80211_band band)\n {\n@@ -311,6 +313,9 @@ int parse_keys(struct nl_msg *msg, char\n \tchar keybuf[13];\n \tint pos = 0;\n \n+#ifndef IW_FULL\n+\treturn 1;\n+#endif\n \tif (!*argc)\n \t\treturn 1;\n \n--- a/Makefile\n+++ b/Makefile\n@@ -23,6 +23,12 @@ _OBJS := $(sort $(patsubst %.c,%.o,$(wil\n VERSION_OBJS := $(filter-out version.o, $(_OBJS))\n OBJS := $(VERSION_OBJS) version.o\n \n+OBJS_FULL = ocb offch cqm wowlan coalesce roc p2p vendor mgmt ap sha256 nan bloom measurements ftm\n+ifdef IW_FULL\n+  CFLAGS += -DIW_FULL\n+else\n+  OBJS:=$(filter-out $(patsubst %,%.o,$(OBJS_FULL)),$(OBJS))\n+endif\n ALL = iw\n \n ifeq ($(NO_PKG_CONFIG),)\n--- a/station.c\n+++ b/station.c\n@@ -777,10 +777,12 @@ static int handle_station_set_plink(stru\n  nla_put_failure:\n \treturn -ENOBUFS;\n }\n+#ifdef IW_FULL\n COMMAND_ALIAS(station, set, \"<MAC address> plink_action <open|block>\",\n \tNL80211_CMD_SET_STATION, 0, CIB_NETDEV, handle_station_set_plink,\n \t\"Set mesh peer link action for this station (peer).\",\n \tselect_station_cmd, station_set_plink);\n+#endif\n \n static int handle_station_set_vlan(struct nl80211_state *state,\n \t\t\t\t   struct nl_msg *msg,\n@@ -875,11 +877,13 @@ static int handle_station_set_mesh_power\n nla_put_failure:\n \treturn -ENOBUFS;\n }\n+#ifdef IW_FULL\n COMMAND_ALIAS(station, set, \"<MAC address> mesh_power_mode \"\n \t\"<active|light|deep>\", NL80211_CMD_SET_STATION, 0, CIB_NETDEV,\n \thandle_station_set_mesh_power_mode,\n \t\"Set link-specific mesh power mode for this station\",\n \tselect_station_cmd, station_set_mesh_power_mode);\n+#endif\n \n static int handle_station_set_airtime_weight(struct nl80211_state *state,\n \t\t\t\t\t     struct nl_msg *msg,\n--- a/interface.c\n+++ b/interface.c\n@@ -627,9 +627,11 @@ static int handle_interface_wds_peer(str\n  nla_put_failure:\n \treturn -ENOBUFS;\n }\n+#ifdef IW_FULL\n COMMAND(set, peer, \"<MAC address>\",\n \tNL80211_CMD_SET_WDS_PEER, 0, CIB_NETDEV, handle_interface_wds_peer,\n \t\"Set interface WDS peer.\");\n+#endif\n \n static int set_mcast_rate(struct nl80211_state *state,\n \t\t\t  struct nl_msg *msg,\n@@ -719,6 +721,7 @@ static int handle_chan(struct nl80211_st\n \treturn handle_chanfreq(state, msg, true, argc, argv, id);\n }\n \n+#ifdef IW_FULL\n SECTION(switch);\n COMMAND(switch, freq,\n \t\"<freq> [NOHT|HT20|HT40+|HT40-|5MHz|10MHz|80MHz] [beacons <count>] [block-tx]\\n\"\n@@ -990,3 +993,4 @@ COMMAND(set, tidconf, \"[peer <MAC addres\n \t\"  $ iw dev wlan0 set tidconf peer xx:xx:xx:xx:xx:xx tids 0x2 bitrates auto\\n\"\n \t\"  $ iw dev wlan0 set tidconf peer xx:xx:xx:xx:xx:xx tids 0x2 bitrates limit vht-mcs-5 4:9\\n\"\n \t);\n+#endif\n--- a/phy.c\n+++ b/phy.c\n@@ -369,6 +369,7 @@ err_out:\n \t\tfree(cac_trigger_argv);\n \treturn err;\n }\n+#ifdef IW_FULL\n TOPLEVEL(cac, \"channel <channel> [NOHT|HT20|HT40+|HT40-|5MHz|10MHz|80MHz]\\n\"\n \t      \"freq <freq> [NOHT|HT20|HT40+|HT40-|5MHz|10MHz|80MHz]\\n\"\n \t      \"freq <control freq> [5|10|20|40|80|80+80|160] [<center1_freq> [<center2_freq>]]\",\n@@ -380,6 +381,7 @@ COMMAND(cac, trigger,\n \tNL80211_CMD_RADAR_DETECT, 0, CIB_NETDEV, handle_cac_trigger,\n \t\"Start or trigger a channel availability check (CAC) looking to look for\\n\"\n \t\"radars on the given channel.\");\n+#endif\n \n static int handle_fragmentation(struct nl80211_state *state,\n \t\t\t\tstruct nl_msg *msg,\n"
  },
  {
    "path": "package/network/utils/iwcap/Makefile",
    "content": "#\n# Copyright (C) 2012 Jo-Philipp Wich <jo@mein.io>\n#\n# This is free software, licensed under the Apache 2 license.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=iwcap\nPKG_RELEASE:=1\nPKG_LICENSE:=Apache-2.0\n\ninclude $(INCLUDE_DIR)/package.mk\n\n\ndefine Package/iwcap\n  SECTION:=utils\n  CATEGORY:=Utilities\n  TITLE:=Simple radiotap capture utility\n  MAINTAINER:=Jo-Philipp Wich <jo@mein.io>\nendef\n\ndefine Package/iwcap/description\n  The iwcap utility receives radiotap packet data from wifi monitor interfaces\n  and outputs it to pcap format. It gathers recived packets in a fixed ring\n  buffer to dump them on demand which is useful for background monitoring.\n  Alternatively the utility can stream the data to stdout to act as remote\n  capture drone for Wireshark or similar programs.\nendef\n\n\ndefine Build/Configure\nendef\n\ndefine Build/Compile\n\t$(TARGET_CC) $(TARGET_CFLAGS) \\\n\t\t-o $(PKG_BUILD_DIR)/iwcap $(PKG_BUILD_DIR)/iwcap.c\nendef\n\n\ndefine Package/iwcap/install\n\t$(INSTALL_DIR) $(1)/usr/sbin\n\t$(INSTALL_BIN) $(PKG_BUILD_DIR)/iwcap $(1)/usr/sbin/iwcap\nendef\n\n$(eval $(call BuildPackage,iwcap))\n"
  },
  {
    "path": "package/network/utils/iwcap/src/iwcap.c",
    "content": "/*\n * iwcap.c - A simply radiotap capture utility outputting pcap dumps\n *\n *    Copyright 2012 Jo-Philipp Wich <jo@mein.io>\n *\n *    Licensed under the Apache License, Version 2.0 (the \"License\");\n *    you may not use this file except in compliance with the License.\n *    You may obtain a copy of the License at\n *\n *        http://www.apache.org/licenses/LICENSE-2.0\n *\n *    Unless required by applicable law or agreed to in writing, software\n *    distributed under the License is distributed on an \"AS IS\" BASIS,\n *    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n *    See the License for the specific language governing permissions and\n *    limitations under the License.\n *\n */\n\n#include <stdio.h>\n#include <stdint.h>\n#include <stdlib.h>\n#include <stdarg.h>\n#include <unistd.h>\n#include <string.h>\n#include <signal.h>\n#include <syslog.h>\n#include <errno.h>\n#include <byteswap.h>\n#include <sys/stat.h>\n#include <sys/time.h>\n#include <sys/ioctl.h>\n#include <sys/socket.h>\n#include <net/ethernet.h>\n#include <net/if.h>\n#include <netinet/in.h>\n#include <linux/if_packet.h>\n\n#define ARPHRD_IEEE80211_RADIOTAP\t803\n\n#define DLT_IEEE802_11_RADIO\t\t127\n#define LEN_IEEE802_11_HDR\t\t\t32\n\n#define FRAMETYPE_MASK\t\t\t\t0xFC\n#define FRAMETYPE_BEACON\t\t\t0x80\n#define FRAMETYPE_DATA\t\t\t\t0x08\n\n#if __BYTE_ORDER == __BIG_ENDIAN\n#define le16(x) __bswap_16(x)\n#else\n#define le16(x) (x)\n#endif\n\nuint8_t run_dump   = 0;\nuint8_t run_stop   = 0;\nuint8_t run_daemon = 0;\n\nuint32_t frames_captured = 0;\nuint32_t frames_filtered = 0;\n\nint capture_sock = -1;\nconst char *ifname = NULL;\n\n\nstruct ringbuf {\n\tuint32_t len;            /* number of slots */\n\tuint32_t fill;           /* last used slot */\n\tuint32_t slen;           /* slot size */\n\tvoid *buf;               /* ring memory */\n};\n\nstruct ringbuf_entry {\n\tuint32_t len;            /* used slot memory */\n\tuint32_t olen;           /* original data size */\n\tuint32_t sec;            /* epoch of slot creation */\n\tuint32_t usec;\t\t\t /* epoch microseconds */\n};\n\ntypedef struct pcap_hdr_s {\n\tuint32_t magic_number;   /* magic number */\n\tuint16_t version_major;  /* major version number */\n\tuint16_t version_minor;  /* minor version number */\n\tint32_t  thiszone;       /* GMT to local correction */\n\tuint32_t sigfigs;        /* accuracy of timestamps */\n\tuint32_t snaplen;        /* max length of captured packets, in octets */\n\tuint32_t network;        /* data link type */\n} pcap_hdr_t;\n\ntypedef struct pcaprec_hdr_s {\n\tuint32_t ts_sec;         /* timestamp seconds */\n\tuint32_t ts_usec;        /* timestamp microseconds */\n\tuint32_t incl_len;       /* number of octets of packet saved in file */\n\tuint32_t orig_len;       /* actual length of packet */\n} pcaprec_hdr_t;\n\ntypedef struct ieee80211_radiotap_header {\n\tu_int8_t  it_version;    /* set to 0 */\n\tu_int8_t  it_pad;\n\tu_int16_t it_len;        /* entire length */\n\tu_int32_t it_present;    /* fields present */\n} __attribute__((__packed__)) radiotap_hdr_t;\n\n\nint check_type(void)\n{\n\tstruct ifreq ifr;\n\n\tstrncpy(ifr.ifr_name, ifname, IFNAMSIZ);\n\n\tif (ioctl(capture_sock, SIOCGIFHWADDR, &ifr) < 0)\n\t\treturn -1;\n\n\treturn (ifr.ifr_hwaddr.sa_family == ARPHRD_IEEE80211_RADIOTAP);\n}\n\nint set_promisc(int on)\n{\n\tstruct ifreq ifr;\n\n\tstrncpy(ifr.ifr_name, ifname, IFNAMSIZ);\n\n\tif (ioctl(capture_sock, SIOCGIFFLAGS, &ifr) < 0)\n\t\treturn -1;\n\n\tif (on && !(ifr.ifr_flags & IFF_PROMISC))\n\t{\n\t\tifr.ifr_flags |= IFF_PROMISC;\n\n\t\tif (ioctl(capture_sock, SIOCSIFFLAGS, &ifr))\n\t\t\treturn -1;\n\n\t\treturn 1;\n\t}\n\telse if (!on && (ifr.ifr_flags & IFF_PROMISC))\n\t{\n\t\tifr.ifr_flags &= ~IFF_PROMISC;\n\n\t\tif (ioctl(capture_sock, SIOCSIFFLAGS, &ifr))\n\t\t\treturn -1;\n\n\t\treturn 1;\n\t}\n\n\treturn 0;\n}\n\n\nvoid sig_dump(int sig)\n{\n\trun_dump = 1;\n}\n\nvoid sig_teardown(int sig)\n{\n\trun_stop = 1;\n}\n\n\nvoid write_pcap_header(FILE *o)\n{\n\tpcap_hdr_t ghdr = {\n\t\t.magic_number  = 0xa1b2c3d4,\n\t\t.version_major = 2,\n\t\t.version_minor = 4,\n\t\t.thiszone      = 0,\n\t\t.sigfigs       = 0,\n\t\t.snaplen       = 0xFFFF,\n\t\t.network       = DLT_IEEE802_11_RADIO\n\t};\n\n\tfwrite(&ghdr, 1, sizeof(ghdr), o);\n}\n\nvoid write_pcap_frame(FILE *o, uint32_t *sec, uint32_t *usec,\n\t\t\t\t\t  uint16_t len, uint16_t olen)\n{\n\tstruct timeval tv;\n\tpcaprec_hdr_t fhdr;\n\n\tif (!sec || !usec)\n\t{\n\t\tgettimeofday(&tv, NULL);\n\t}\n\telse\n\t{\n\t\ttv.tv_sec  = *sec;\n\t\ttv.tv_usec = *usec;\n\t}\n\n\tfhdr.ts_sec   = tv.tv_sec;\n\tfhdr.ts_usec  = tv.tv_usec;\n\tfhdr.incl_len = len;\n\tfhdr.orig_len = olen;\n\n\tfwrite(&fhdr, 1, sizeof(fhdr), o);\n}\n\n\nstruct ringbuf * ringbuf_init(uint32_t num_item, uint16_t len_item)\n{\n\tstatic struct ringbuf r;\n\n\tif (len_item <= 0)\n\t\treturn NULL;\n\n\tr.buf = malloc(num_item * (len_item + sizeof(struct ringbuf_entry)));\n\n\tif (r.buf)\n\t{\n\t\tr.len = num_item;\n\t\tr.fill = 0;\n\t\tr.slen = (len_item + sizeof(struct ringbuf_entry));\n\n\t\tmemset(r.buf, 0, num_item * len_item);\n\n\t\treturn &r;\n\t}\n\n\treturn NULL;\n}\n\nstruct ringbuf_entry * ringbuf_add(struct ringbuf *r)\n{\n\tstruct timeval t;\n\tstruct ringbuf_entry *e;\n\n\tgettimeofday(&t, NULL);\n\n\te = r->buf + (r->fill++ * r->slen);\n\tr->fill %= r->len;\n\n\tmemset(e, 0, r->slen);\n\n\te->sec = t.tv_sec;\n\te->usec = t.tv_usec;\n\n\treturn e;\n}\n\nstruct ringbuf_entry * ringbuf_get(struct ringbuf *r, int i)\n{\n\tstruct ringbuf_entry *e = r->buf + (((r->fill + i) % r->len) * r->slen);\n\n\tif (e->len > 0)\n\t\treturn e;\n\n\treturn NULL;\n}\n\nvoid ringbuf_free(struct ringbuf *r)\n{\n\tfree(r->buf);\n\tmemset(r, 0, sizeof(*r));\n}\n\n\nvoid msg(const char *fmt, ...)\n{\n\tva_list ap;\n\tva_start(ap, fmt);\n\n\tif (run_daemon)\n\t\tvsyslog(LOG_INFO | LOG_USER, fmt, ap);\n\telse\n\t\tvfprintf(stderr, fmt, ap);\n\n\tva_end(ap);\n}\n\n\nint main(int argc, char **argv)\n{\n\tint i, n;\n\tstruct ringbuf *ring;\n\tstruct ringbuf_entry *e;\n\tstruct sockaddr_ll local = {\n\t\t.sll_family   = AF_PACKET,\n\t\t.sll_protocol = htons(ETH_P_ALL)\n\t};\n\n\tradiotap_hdr_t *rhdr;\n\n\tuint8_t frametype;\n\tuint8_t pktbuf[0xFFFF];\n\tssize_t pktlen;\n\n\tFILE *o;\n\n\tint opt;\n\n\tuint8_t promisc        = 0;\n\tuint8_t streaming      = 0;\n\tuint8_t foreground     = 0;\n\tuint8_t filter_data    = 0;\n\tuint8_t filter_beacon  = 0;\n\tuint8_t header_written = 0;\n\n\tuint32_t ringsz   = 1024 * 1024; /* 1 Mbyte ring buffer */\n\tuint16_t pktcap   = 256;\t\t /* truncate frames after 265KB */\n\n\tconst char *output = NULL;\n\n\n\twhile ((opt = getopt(argc, argv, \"i:r:c:o:sfhBD\")) != -1)\n\t{\n\t\tswitch (opt)\n\t\t{\n\t\tcase 'i':\n\t\t\tifname = optarg;\n\t\t\tif (!(local.sll_ifindex = if_nametoindex(ifname)))\n\t\t\t{\n\t\t\t\tmsg(\"Unknown interface '%s'\\n\", ifname);\n\t\t\t\treturn 2;\n\t\t\t}\n\t\t\tbreak;\n\n\t\tcase 'r':\n\t\t\tringsz = atoi(optarg);\n\t\t\tif (ringsz < (3 * pktcap))\n\t\t\t{\n\t\t\t\tmsg(\"Ring size of %d bytes is too short, \"\n\t\t\t\t\t\"must be at least %d bytes\\n\", ringsz, 3 * pktcap);\n\t\t\t\treturn 3;\n\t\t\t}\n\t\t\tbreak;\n\n\t\tcase 'c':\n\t\t\tpktcap = atoi(optarg);\n\t\t\tif (pktcap <= (sizeof(radiotap_hdr_t) + LEN_IEEE802_11_HDR))\n\t\t\t{\n\t\t\t\tmsg(\"Packet truncate after %d bytes is too short, \"\n\t\t\t\t\t\"must be at least %d bytes\\n\",\n\t\t\t\t\tpktcap, sizeof(radiotap_hdr_t) + LEN_IEEE802_11_HDR);\n\t\t\t\treturn 4;\n\t\t\t}\n\t\t\tbreak;\n\n\t\tcase 's':\n\t\t\tstreaming = 1;\n\t\t\tbreak;\n\n\t\tcase 'o':\n\t\t\toutput = optarg;\n\t\t\tbreak;\n\n\t\tcase 'B':\n\t\t\tfilter_beacon = 1;\n\t\t\tbreak;\n\n\t\tcase 'D':\n\t\t\tfilter_data = 1;\n\t\t\tbreak;\n\n\t\tcase 'f':\n\t\t\tforeground = 1;\n\t\t\tbreak;\n\n\t\tcase 'h':\n\t\t\tmsg(\n\t\t\t\t\"Usage:\\n\"\n\t\t\t\t\"  %s -i {iface} -s [-b] [-d]\\n\"\n\t\t\t\t\"  %s -i {iface} -o {file} [-r len] [-c len] [-B] [-D] [-f]\\n\"\n\t\t\t\t\"\\n\"\n\t\t\t\t\"  -i iface\\n\"\n\t\t\t\t\"    Specify interface to use, must be in monitor mode and\\n\"\n\t\t\t\t\"    produce IEEE 802.11 Radiotap headers.\\n\\n\"\n\t\t\t\t\"  -s\\n\"\n\t\t\t\t\"    Stream to stdout instead of Dumping to file on USR1.\\n\\n\"\n\t\t\t\t\"  -o file\\n\"\n\t\t\t\t\"    Write current ringbuffer contents to given output file\\n\"\n\t\t\t\t\"    on receipt of SIGUSR1.\\n\\n\"\n\t\t\t\t\"  -r len\\n\"\n\t\t\t\t\"    Specify the amount of bytes to use for the ringbuffer.\\n\"\n\t\t\t\t\"    The default length is %d bytes.\\n\\n\"\n\t\t\t\t\"  -c len\\n\"\n\t\t\t\t\"    Truncate captured packets after given amount of bytes.\\n\"\n\t\t\t\t\"    The default size limit is %d bytes.\\n\\n\"\n\t\t\t\t\"  -B\\n\"\n\t\t\t\t\"    Don't store beacon frames in ring, default is keep.\\n\\n\"\n\t\t\t\t\"  -D\\n\"\n\t\t\t\t\"    Don't store data frames in ring, default is keep.\\n\\n\"\n\t\t\t\t\"  -f\\n\"\n\t\t\t\t\"    Do not daemonize but keep running in foreground.\\n\\n\"\n\t\t\t\t\"  -h\\n\"\n\t\t\t\t\"    Display this help.\\n\\n\",\n\t\t\t\targv[0], argv[0], ringsz, pktcap);\n\n\t\t\treturn 1;\n\t\t}\n\t}\n\n\tif (!streaming && !output)\n\t{\n\t\tmsg(\"No output file specified\\n\");\n\t\treturn 1;\n\t}\n\n\tif (streaming && output)\n\t{\n\t\tmsg(\"The -s and -o options are exclusive\\n\");\n\t\treturn 1;\n\t}\n\n\tif (streaming && isatty(1))\n\t{\n\t\tmsg(\"Refusing to stream into a terminal\\n\");\n\t\treturn 1;\n\t}\n\n\tif (!local.sll_ifindex)\n\t{\n\t\tmsg(\"No interface specified\\n\");\n\t\treturn 2;\n\t}\n\n\tif (!check_type())\n\t{\n\t\tmsg(\"Bad interface: not ARPHRD_IEEE80211_RADIOTAP\\n\");\n\t\treturn 2;\n\t}\n\n\tif ((capture_sock = socket(PF_PACKET, SOCK_RAW, htons(ETH_P_ALL))) < 0)\n\t{\n\t\tmsg(\"Unable to create raw socket: %s\\n\",\n\t\t\t\tstrerror(errno));\n\t\treturn 6;\n\t}\n\n\tif (bind(capture_sock, (struct sockaddr *)&local, sizeof(local)) == -1)\n\t{\n\t\tmsg(\"Unable to bind to interface: %s\\n\",\n\t\t\tstrerror(errno));\n\t\treturn 7;\n\t}\n\n\tif (!streaming)\n\t{\n\t\tif (!foreground)\n\t\t{\n\t\t\tswitch (fork())\n\t\t\t{\n\t\t\t\tcase -1:\n\t\t\t\t\tmsg(\"Unable to fork: %s\\n\", strerror(errno));\n\t\t\t\t\treturn 8;\n\n\t\t\t\tcase 0:\n\t\t\t\t\tumask(0077);\n\t\t\t\t\tchdir(\"/\");\n\t\t\t\t\tfreopen(\"/dev/null\", \"r\", stdin);\n\t\t\t\t\tfreopen(\"/dev/null\", \"w\", stdout);\n\t\t\t\t\tfreopen(\"/dev/null\", \"w\", stderr);\n\t\t\t\t\trun_daemon = 1;\n\t\t\t\t\tbreak;\n\n\t\t\t\tdefault:\n\t\t\t\t\tmsg(\"Daemon launched ...\\n\");\n\t\t\t\t\treturn 0;\n\t\t\t}\n\t\t}\n\n\t\tmsg(\"Monitoring interface %s ...\\n\", ifname);\n\n\t\tif (!(ring = ringbuf_init(ringsz / pktcap, pktcap)))\n\t\t{\n\t\t\tmsg(\"Unable to allocate ring buffer: %s\\n\",\n\t\t\t\tstrerror(errno));\n\t\t\treturn 5;\n\t\t}\n\n\t\tmsg(\" * Using %d bytes ringbuffer with %d slots\\n\", ringsz, ring->len);\n\t\tmsg(\" * Truncating frames at %d bytes\\n\", pktcap);\n\t\tmsg(\" * Dumping data to file %s\\n\", output);\n\n\t\tsignal(SIGUSR1, sig_dump);\n\t}\n\telse\n\t{\n\t\tmsg(\"Monitoring interface %s ...\\n\", ifname);\n\t\tmsg(\" * Streaming data to stdout\\n\");\n\t}\n\n\tmsg(\" * Beacon frames are %sfiltered\\n\", filter_beacon ? \"\" : \"not \");\n\tmsg(\" * Data frames are %sfiltered\\n\", filter_data ? \"\" : \"not \");\n\n\tsignal(SIGINT, sig_teardown);\n\tsignal(SIGTERM, sig_teardown);\n\n\tpromisc = set_promisc(1);\n\n\t/* capture loop */\n\twhile (1)\n\t{\n\t\tif (run_dump)\n\t\t{\n\t\t\tmsg(\"Dumping ring to %s ...\\n\", output);\n\n\t\t\tif (!(o = fopen(output, \"w\")))\n\t\t\t{\n\t\t\t\tmsg(\"Unable to open %s: %s\\n\",\n\t\t\t\t\toutput, strerror(errno));\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\twrite_pcap_header(o);\n\n\t\t\t\t/* sig_dump packet buffer */\n\t\t\t\tfor (i = 0, n = 0; i < ring->len; i++)\n\t\t\t\t{\n\t\t\t\t\tif (!(e = ringbuf_get(ring, i)))\n\t\t\t\t\t\tcontinue;\n\n\t\t\t\t\twrite_pcap_frame(o, &(e->sec), &(e->usec), e->len, e->olen);\n\t\t\t\t\tfwrite((void *)e + sizeof(*e), 1, e->len, o);\n\t\t\t\t\tn++;\n\t\t\t\t}\n\n\t\t\t\tfclose(o);\n\n\t\t\t\tmsg(\" * %d frames captured\\n\", frames_captured);\n\t\t\t\tmsg(\" * %d frames filtered\\n\", frames_filtered);\n\t\t\t\tmsg(\" * %d frames dumped\\n\", n);\n\t\t\t}\n\n\t\t\trun_dump = 0;\n\t\t}\n\t\tif (run_stop)\n\t\t{\n\t\t\tmsg(\"Shutting down ...\\n\");\n\n\t\t\tif (promisc)\n\t\t\t\tset_promisc(0);\n\n\t\t\tif (ring)\n\t\t\t\tringbuf_free(ring);\n\n\t\t\treturn 0;\n\t\t}\n\n\t\tpktlen = recvfrom(capture_sock, pktbuf, sizeof(pktbuf), 0, NULL, 0);\n\t\tframes_captured++;\n\n\t\t/* check received frametype, if we should filter it, rewind the ring */\n\t\trhdr = (radiotap_hdr_t *)pktbuf;\n\n\t\tif (pktlen <= sizeof(radiotap_hdr_t) || le16(rhdr->it_len) >= pktlen)\n\t\t{\n\t\t\tframes_filtered++;\n\t\t\tcontinue;\n\t\t}\n\n\t\tframetype = *(uint8_t *)(pktbuf + le16(rhdr->it_len));\n\n\t\tif ((filter_data   && (frametype & FRAMETYPE_MASK) == FRAMETYPE_DATA) ||\n\t\t    (filter_beacon && (frametype & FRAMETYPE_MASK) == FRAMETYPE_BEACON))\n\t\t{\n\t\t\tframes_filtered++;\n\t\t\tcontinue;\n\t\t}\n\n\t\tif (streaming)\n\t\t{\n\t\t\tif (!header_written)\n\t\t\t{\n\t\t\t\twrite_pcap_header(stdout);\n\t\t\t\theader_written = 1;\n\t\t\t}\n\n\t\t\twrite_pcap_frame(stdout, NULL, NULL, pktlen, pktlen);\n\t\t\tfwrite(pktbuf, 1, pktlen, stdout);\n\t\t\tfflush(stdout);\n\t\t}\n\t\telse\n\t\t{\n\t\t\te = ringbuf_add(ring);\n\t\t\te->olen = pktlen;\n\t\t\te->len = (pktlen > pktcap) ? pktcap : pktlen;\n\n\t\t\tmemcpy((void *)e + sizeof(*e), pktbuf, e->len);\n\t\t}\n\t}\n\n\treturn 0;\n}\n"
  },
  {
    "path": "package/network/utils/iwinfo/Makefile",
    "content": "#\n# Copyright (C) 2010-2016 Jo-Philipp Wich <jo@mein.io>\n#\n# This is free software, licensed under the GPL 2 license.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=libiwinfo\nPKG_RELEASE:=1\n\nPKG_SOURCE_PROTO:=git\nPKG_SOURCE_URL=$(PROJECT_GIT)/project/iwinfo.git\nPKG_SOURCE_DATE:=2022-04-26\nPKG_SOURCE_VERSION:=dc6847eb5ec8747867bc20f1024723c6397c1df7\nPKG_MIRROR_HASH:=3f243cf75f4cec02e9e8ecc2087577146845346c0172808f64dea066f84f88d4\nPKG_MAINTAINER:=Jo-Philipp Wich <jo@mein.io>\nPKG_LICENSE:=GPL-2.0\n\nIWINFO_ABI_VERSION:=20210430\n\ninclude $(INCLUDE_DIR)/package.mk\n\n\ndefine Package/libiwinfo\n  SECTION:=libs\n  CATEGORY:=Libraries\n  TITLE:=Generalized Wireless Information Library (iwinfo)\n  DEPENDS:=+libnl-tiny +libuci +libubus +libiwinfo-data\n  ABI_VERSION:=$(IWINFO_ABI_VERSION)\nendef\n\ndefine Package/libiwinfo/description\n  Wireless information library with simplified API for nl80211\n  and wext driver interfaces.\nendef\n\n\ndefine Package/libiwinfo-lua\n  SUBMENU:=Lua\n  SECTION:=lang\n  CATEGORY:=Languages\n  TITLE:=libiwinfo Lua binding\n  DEPENDS:=+libiwinfo +liblua\nendef\n\ndefine Package/libiwinfo-lua/description\n  This is the Lua binding for the iwinfo library. It provides access to all enabled\n  backends.\nendef\n\n\ndefine Package/libiwinfo-data\n  TITLE:=libiwinfo Lua binding\n  HIDDEN:=1\nendef\n\n\ndefine Package/iwinfo\n  SECTION:=utils\n  CATEGORY:=Utilities\n  TITLE:=Generalized Wireless Information utility\n  DEPENDS:=+libiwinfo\nendef\n\ndefine Package/iwinfo/description\n  Command line frontend for the wireless information library.\nendef\n\n\ndefine Build/Configure\nendef\n\nTARGET_CFLAGS += \\\n\t-I$(STAGING_DIR)/usr/include/libnl-tiny \\\n\t-I$(STAGING_DIR)/usr/include \\\n\t-D_GNU_SOURCE\n\nMAKE_FLAGS += \\\n\tFPIC=\"$(FPIC)\" \\\n\tCFLAGS=\"$(TARGET_CFLAGS)\" \\\n\tLDFLAGS=\"$(TARGET_LDFLAGS)\" \\\n\tBACKENDS=\"nl80211\" \\\n\tSOVERSION=\"$(IWINFO_ABI_VERSION)\"\n\ndefine Build/InstallDev\n\t$(INSTALL_DIR) $(1)/usr/include/iwinfo\n\t$(CP) $(PKG_BUILD_DIR)/include/iwinfo.h $(1)/usr/include/\n\t$(CP) $(PKG_BUILD_DIR)/include/iwinfo/* $(1)/usr/include/iwinfo/\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(CP) $(PKG_BUILD_DIR)/libiwinfo.so* $(1)/usr/lib/\n\t$(INSTALL_DIR) $(1)/usr/lib/lua\n\t$(INSTALL_BIN) $(PKG_BUILD_DIR)/iwinfo.so $(1)/usr/lib/lua/iwinfo.so\nendef\n\ndefine Package/libiwinfo/install\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(INSTALL_BIN) $(PKG_BUILD_DIR)/libiwinfo.so.$(IWINFO_ABI_VERSION) $(1)/usr/lib/libiwinfo.so.$(IWINFO_ABI_VERSION)\nendef\n\ndefine Package/libiwinfo-lua/install\n\t$(INSTALL_DIR) $(1)/usr/lib/lua\n\t$(INSTALL_BIN) $(PKG_BUILD_DIR)/iwinfo.so $(1)/usr/lib/lua/iwinfo.so\nendef\n\ndefine Package/libiwinfo-data/install\n\t$(INSTALL_DIR) $(1)/usr/share/libiwinfo\n\t$(INSTALL_DATA) $(PKG_BUILD_DIR)/devices.txt $(1)/usr/share/libiwinfo/devices.txt\nendef\n\ndefine Package/iwinfo/install\n\t$(INSTALL_DIR) $(1)/usr/bin\n\t$(INSTALL_BIN) $(PKG_BUILD_DIR)/iwinfo $(1)/usr/bin/iwinfo\nendef\n\n$(eval $(call BuildPackage,libiwinfo))\n$(eval $(call BuildPackage,libiwinfo-lua))\n$(eval $(call BuildPackage,libiwinfo-data))\n$(eval $(call BuildPackage,iwinfo))\n"
  },
  {
    "path": "package/network/utils/layerscape/restool/Makefile",
    "content": "#\n# Copyright 2017 NXP\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=restool\nPKG_VERSION:=21.08\nPKG_RELEASE:=$(AUTORELEASE)\n\nPKG_SOURCE_PROTO:=git\nPKG_SOURCE_URL:=https://source.codeaurora.org/external/qoriq/qoriq-components/restool\nPKG_SOURCE_VERSION:=LSDK-21.08\nPKG_MIRROR_HASH:=d793defa2e4cf907bebe7761d88feb2ac94e0ecdaabdb3bbc9dda83a82046bc5\n\nPKG_FLAGS:=nonshared\n\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine Package/restool\n  SECTION:=net\n  CATEGORY:=Network\n  TITLE:=Layerscape DPAA2 dynamical management tool\n  DEPENDS:=@TARGET_layerscape_armv8_64b\nendef\n\nMAKE_FLAGS += \\\n\tDESTDIR=\"$(PKG_BUILD_DIR)\"/output/ \\\n\tinstall\n\ndefine Package/restool/install\n\t$(INSTALL_DIR) $(1)/usr/bin/\n\t$(CP) $(PKG_BUILD_DIR)/output/usr/local/bin/* $(1)/usr/bin/\nendef\n\n$(eval $(call BuildPackage,restool))\n"
  },
  {
    "path": "package/network/utils/layerscape/restool/patches/remove-manpage.patch",
    "content": "--- a/Makefile\n+++ b/Makefile\n@@ -53,14 +53,13 @@ restool: $(OBJ)\n %.1: %.md\n \tpandoc --standalone --to man $^ -o $@\n \n-install: restool scripts/ls-main scripts/ls-append-dpl scripts/ls-debug scripts/restool_completion.sh $(MANPAGE)\n+install: restool scripts/ls-main scripts/ls-append-dpl scripts/ls-debug scripts/restool_completion.sh\n \tinstall -D -m 755 restool $(DESTDIR)$(bindir)/restool\n \tinstall -D -m 755 scripts/ls-main $(DESTDIR)$(bindir)/ls-main\n \tinstall -D -m 755 scripts/ls-append-dpl $(DESTDIR)$(bindir)/ls-append-dpl\n \tinstall -D -m 755 scripts/ls-debug $(DESTDIR)$(bindir)/ls-debug\n \t$(foreach symlink, $(RESTOOL_SCRIPT_SYMLINKS), sh -c \"cd $(DESTDIR)$(bindir) && ln -sf ls-main $(symlink)\" ;)\n \tinstall -D -m 755 scripts/restool_completion.sh $(DESTDIR)$(bindir_completion)/restool\n-\tinstall -m 0644 -D $(MANPAGE) $(call get_manpage_destination,$(MANPAGE))\n \n clean:\n \trm -f $(OBJ) $(MANPAGE) \\\n"
  },
  {
    "path": "package/network/utils/linux-atm/Makefile",
    "content": "#\n# Copyright (C) 2006-2012 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\ninclude $(INCLUDE_DIR)/kernel.mk\n\nPKG_NAME:=linux-atm\nPKG_VERSION:=2.5.2\nPKG_RELEASE:=7\n\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz\nPKG_SOURCE_URL:=@SF/$(PKG_NAME)\nPKG_HASH:=9645481a2b16476b59220aa2d6bc5bc41043f291326c9b37581018fbd16dd53a\n\nPKG_INSTALL:=1\nPKG_BUILD_PARALLEL:=1\nPKG_LICENSE:=GPL-2.0+\nPKG_CPE_ID:=cpe:/a:linux-atm:linux-atm\nPKG_FIXUP:=autoreconf\n\ninclude $(INCLUDE_DIR)/package.mk\n\nATM_DEBUG_BINS:=aread awrite atmdiag atmdump atmswitch saaldump \\\n\t\tsonetdiag svc_recv svc_send ttcp_atm\nATM_DEBUG_SBINS:=atmaddr atmloop atmtcp esi atmsigd bus \\\n\t\t ilmid ilmidiag lecs les mpcd zeppelin\nATM_DEBUG_TOOLS:=$(ATM_DEBUG_BINS) $(ATM_DEBUG_SBINS)\n\ndefine Package/linux-atm\n  SECTION:=libs\n  CATEGORY:=Libraries\n  TITLE:=Linux ATM library\n  URL:=http://linux-atm.sourceforge.net/\nendef\n\ndefine Package/linux-atm/description\n  This package contains a library for accessing the Linux ATM subsystem.\nendef\n\ndefine Package/linux-atm/Default\n  SECTION:=net\n  CATEGORY:=Network\n  DEPENDS:=+linux-atm\n  URL:=http://linux-atm.sourceforge.net/\n  SUBMENU:=Linux ATM tools\nendef\n\ndefine Package/atm-tools\n  $(call Package/linux-atm/Default)\n  TITLE:=Linux ATM tools\nendef\n\ndefine Package/atm-tools/description\n  This package contains the Linux ATM tools.\nendef\n\ndefine Package/atm-diagnostics\n  $(call Package/linux-atm/Default)\n  TITLE:=Linux ATM Diagnostics\nendef\n\ndefine Package/atm-diagnostics/description\n  This package contains the Linux ATM diagnostics.\nendef\n\ndefine Package/atm-debug-tools\n  $(call Package/linux-atm/Default)\n  TITLE:=Linux ATM debugging tools\nendef\n\ndefine Package/atm-debug-tools/description\n  This package contains the Linux ATM debugging tools.\nendef\n\ndefine Package/br2684ctl\n  $(call Package/linux-atm/Default)\n  TITLE:=ATM Ethernet bridging configuration utility\nendef\n\ndefine Package/br2684ctl/description\n  Support for AAL5 encapsulation (RFC-1483/RFC-2684) over ATM.\nendef\n\ndefine GenAtmPlugin\n  define Package/$(1)\n     $(call Package/linux-atm/Default)\n     TITLE:=Linux ATM tool $(2)\n  endef\n\n  define Package/$(1)/description\n     Linux ATM tool $(2).\n  endef\nendef\n\n$(foreach t,$(ATM_DEBUG_TOOLS),$(eval $(call GenAtmPlugin,atm-$(t),$(t))))\n\ndefine Build/Configure\n\t$(call Build/Configure/Default)\n\t# prevent autoheader invocation\n\ttouch $(PKG_BUILD_DIR)/stamp-h.in\nendef\n\nunexport PREFIX\n\ndefine Build/Compile\n\t# src/qgen is built with HOSTCC, which does not really like our LDFLAGS\n\t+$(MAKE) $(PKG_JOBS) -C $(PKG_BUILD_DIR)/src/qgen \\\n\t\tLDFLAGS=\"\" \\\n\t\tall\n\t+$(MAKE) $(PKG_JOBS) -C $(PKG_BUILD_DIR) OBJCOPY=$(TARGET_CROSS)objcopy all\nendef\n\ndefine Build/InstallDev\n\t$(INSTALL_DIR) $(1)/usr\n\t$(CP) \\\n\t\t$(PKG_INSTALL_DIR)/usr/include \\\n\t\t$(PKG_INSTALL_DIR)/usr/lib \\\n\t\t$(1)/usr/\nendef\n\ndefine Package/linux-atm/install\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/libatm.so* $(1)/usr/lib/\nendef\n\ndefine Package/atm-tools/install\n\t$(INSTALL_DIR) $(1)/usr/sbin/\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/sbin/atmarp{,d} $(1)/usr/sbin/\nendef\n\n\ndefine BuildAtmPlugin\n  define Package/$(1)/install\n\t$(INSTALL_DIR) $$(1)/usr/$(3)\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/$(3)/$(2) $$(1)/usr/$(3)\n  endef\n\n  $$(eval $$(call BuildPackage,$(1)))\nendef\n\ndefine Package/atm-debug-tools/install\n\t$(INSTALL_DIR) $(1)/usr/bin/\n\t$(INSTALL_DIR) $(1)/usr/sbin/\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/sbin/atmaddr $(1)/usr/sbin/\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/sbin/atmloop $(1)/usr/sbin/\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/sbin/atmtcp     $(1)/usr/sbin/\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/sbin/esi $(1)/usr/sbin/\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/bin/aread $(1)/usr/bin/\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/bin/awrite $(1)/usr/bin/\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/bin/atmdiag $(1)/usr/bin/\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/bin/atmdump $(1)/usr/bin/\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/sbin/atmsigd $(1)/usr/sbin/\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/sbin/bus $(1)/usr/sbin/\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/sbin/ilmid $(1)/usr/sbin/\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/sbin/ilmidiag $(1)/usr/sbin/\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/sbin/lecs $(1)/usr/sbin/\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/sbin/les $(1)/usr/sbin/\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/sbin/mpcd $(1)/usr/sbin/\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/sbin/zeppelin $(1)/usr/sbin/\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/bin/atmswitch $(1)/usr/bin/\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/bin/saaldump $(1)/usr/bin/\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/bin/sonetdiag $(1)/usr/bin/\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/bin/svc_recv $(1)/usr/bin/\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/bin/svc_send $(1)/usr/bin/\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/bin/ttcp_atm $(1)/usr/bin/\nendef\n\ndefine Package/atm-diagnostics/install\n\t$(INSTALL_DIR) $(1)/usr/bin\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/bin/aread $(1)/usr/bin/\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/bin/awrite $(1)/usr/bin/\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/bin/atmdiag $(1)/usr/bin/\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/bin/atmdump $(1)/usr/bin/\nendef\n\ndefine Package/br2684ctl/install\n\t$(INSTALL_DIR) $(1)/etc/init.d $(1)/etc/hotplug.d/atm $(1)/usr/sbin $(1)/lib/netifd\n\t$(INSTALL_BIN) ./files/br2684-up $(1)/lib/netifd/br2684-up\n\t$(INSTALL_BIN) ./files/br2684ctl $(1)/etc/init.d/\n\t$(INSTALL_CONF) ./files/atm.hotplug $(1)/etc/hotplug.d/atm/00-trigger\n\t$(INSTALL_BIN) \\\n\t\t./files/br2684ctl_wrap \\\n\t\t$(PKG_INSTALL_DIR)/usr/sbin/br2684ctl \\\n\t\t$(1)/usr/sbin/\nendef\n\n$(eval $(call BuildPackage,linux-atm))\n$(eval $(call BuildPackage,atm-tools))\n$(eval $(call BuildPackage,atm-debug-tools))\n$(eval $(call BuildPackage,atm-diagnostics))\n$(eval $(call BuildPackage,br2684ctl))\n$(foreach t,$(ATM_DEBUG_BINS),$(eval $(call BuildAtmPlugin,atm-$(t),$(t),bin)))\n$(foreach t,$(ATM_DEBUG_SBINS),$(eval $(call BuildAtmPlugin,atm-$(t),$(t),sbin)))\n"
  },
  {
    "path": "package/network/utils/linux-atm/files/atm.hotplug",
    "content": "ubus call service event '{ \"type\": \"hotplug.atm\", \"data\": { \"name\": \"'\"$DEVICENAME\"'\" } }'\n"
  },
  {
    "path": "package/network/utils/linux-atm/files/br2684-up",
    "content": "#!/bin/sh\n. /lib/functions/network.sh\nnetwork_ready_device \"$1\"\n"
  },
  {
    "path": "package/network/utils/linux-atm/files/br2684ctl",
    "content": "#!/bin/sh /etc/rc.common\n\nSTART=50\nUSE_PROCD=1\n\nstart_daemon() {\n\tlocal cfg=\"$1\"\n\n\tlocal atmdev disabled\n\n\tconfig_get_bool disabled \"$cfg\" disabled 0\n\t[ \"$disabled\" -eq 1 ] && return\n\n\tconfig_get atmdev \"$cfg\" atmdev 0\n\n\tlocal nameprefix\n\tconfig_get nameprefix \"$cfg\" nameprefix \"nas\"\n\n\tlocal unit\n\tconfig_get unit \"$cfg\" unit 0\n\n\tlocal vpi\n\tconfig_get vpi \"$cfg\" vpi 8\n\n\tlocal vci\n\tconfig_get vci \"$cfg\" vci 35\n\n\tlocal encaps\n\tconfig_get encaps \"$cfg\" encaps\n\n\tcase \"$encaps\" in\n\t\t1|vc) encaps=1;;\n\t\t*) encaps=0;;\n\tesac\n\n\tlocal payload\n\tconfig_get payload \"$cfg\" payload\n\n\tcase \"$payload\" in\n\t\t0|routed) payload=0;;\n\t\t*) payload=1;;\n\tesac\n\n\tlocal qos\n\tconfig_get qos \"$cfg\" qos\n\n\tlocal sendsize\n\tconfig_get sendsize \"$cfg\" sendsize\n\n\tfound=\n\tfor device in /sys/class/atm/*; do\n\t\t[ -d \"$device\" ] || break\n\t\t[ \"$(cat $device/atmindex)\" = \"$atmdev\" ] || continue\n\t\tfound=1\n\t\tbreak\n\tdone\n\n\t[ -n \"$found\" ] || return\n\n\tlocal circuit=\"$atmdev.$vpi.$vci\"\n\n\tprocd_open_instance\n\tprocd_set_param command \\\n\t\t/usr/sbin/br2684ctl_wrap \"${nameprefix}${unit}\" \\\n\t\t-n \"$nameprefix\" -c \"$unit\" -e \"$encaps\" -p \"$payload\" \\\n\t\t-a \"$circuit\" ${qos:+-q \"$qos\"} ${sendsize:+-s \"$sendsize\"} \\\n\t\t-S /lib/netifd/br2684-up\n\tprocd_close_instance\n}\n\nservice_triggers() {\n\tlocal script=$(readlink \"$initscript\")\n\tlocal name=$(basename ${script:-$initscript})\n\n\tprocd_open_trigger\n\tprocd_add_raw_trigger hotplug.atm 2000 /etc/init.d/$name reload\n\tprocd_add_config_trigger \"config.change\" \"network\" /etc/init.d/$name reload\n\tprocd_close_trigger\n}\n\nstart_service() {\n\tconfig_load network\n\tconfig_foreach start_daemon atm-bridge\n}\n"
  },
  {
    "path": "package/network/utils/linux-atm/files/br2684ctl_wrap",
    "content": "#!/bin/sh\n. /lib/functions/network.sh\ndevice=\"$1\"; shift\nnetwork_defer_device \"$device\"\nexec /usr/sbin/br2684ctl \"$@\"\n"
  },
  {
    "path": "package/network/utils/linux-atm/patches/000-debian_16.patch",
    "content": "--- a/src/arpd/io.c\n+++ b/src/arpd/io.c\n@@ -277,7 +277,8 @@ static void accept_new(void)\n     struct atm_qos qos;\n     ENTRY *entry;\n     VCC *vcc;\n-    int fd,len,size,error;\n+    int fd,error;\n+    socklen_t len,size;\n \n     len = sizeof(addr);\n     if ((fd = accept(incoming,(struct sockaddr *) &addr,&len)) < 0) {\n@@ -614,7 +615,8 @@ int ip_itf_info(int number,uint32_t *ip,\n \n int get_local(int fd,struct sockaddr_atmsvc *addr)\n {\n-    int length,result;\n+    int result;\n+    size_t length;\n \n     length = sizeof(struct sockaddr_atmsvc);\n     result = getsockname(fd,(struct sockaddr *) addr,&length);\n--- a/src/arpd/table.c\n+++ b/src/arpd/table.c\n@@ -101,7 +101,8 @@ static void dump_vcc(VCC *vcc)\n     char addr_buf[MAX_ATM_ADDR_LEN+1];\n     char qos_buf[MAX_ATM_QOS_LEN+1];\n     struct atm_qos qos;\n-    int size,sndbuf;\n+    int sndbuf;\n+    socklen_t size;\n \n     size = sizeof(addr);\n     if (getpeername(vcc->fd,(struct sockaddr *) &addr,&size) < 0) {\n--- a/src/ilmid/asn1/asn_int.c\n+++ b/src/ilmid/asn1/asn_int.c\n@@ -185,7 +185,7 @@ FILE* f _AND_\n AsnInt* v _AND_\n unsigned short int indent)\n {\n-    fprintf(f,\"%d\", *v);\n+    fprintf(f,\"%ld\", *v);\n } \n \n \n@@ -370,5 +370,5 @@ FILE* f _AND_\n UAsnInt* v _AND_\n unsigned short int indent)\n {\n-    fprintf(f,\"%u\", *v);\n+    fprintf(f,\"%lu\", *v);\n } \n--- a/src/ilmid/asn1/asn_oid.c\n+++ b/src/ilmid/asn1/asn_oid.c\n@@ -127,7 +127,7 @@ unsigned short int indent)\n     if (firstArcNum > 2)\n         firstArcNum = 2;\n \n-    fprintf(f,\"%u %u\", firstArcNum, arcNum - (firstArcNum * 40));\n+    fprintf(f,\"%d %lu\", firstArcNum, arcNum - (firstArcNum * 40));\n \n     for (; i < v->octetLen ; )\n     {\n@@ -136,7 +136,7 @@ unsigned short int indent)\n \n         arcNum = (arcNum << 7) + (v->octs[i] & 0x7f);\n         i++;\n-        fprintf(f,\" %u\", arcNum);\n+        fprintf(f,\" %lu\", arcNum);\n     }\n     fprintf(f,\"}\");\n \n--- a/src/lane/connect.c\n+++ b/src/lane/connect.c\n@@ -258,7 +258,8 @@ static int\n data_handler(const Event_t *event, void *funcdata)\n {\n   Conn_t *tmp, *newconn;\n-  int fd, nbytes;\n+  int fd;\n+  socklen_t nbytes;\n   static char buffer[BUFSIZE];\n   LaneControl_t *ctmp;\n   struct sockaddr_atmsvc addr;\n--- a/src/lane/connect_bus.c\n+++ b/src/lane/connect_bus.c\n@@ -170,7 +170,8 @@ static int\n data_handler(const Event_t *event, void *funcdata)\n {\n   Conn_t *tmp, *newconn;\n-  int fd, nbytes;\n+  int fd;\n+  socklen_t nbytes;\n   static char buffer[BUFSIZE];\n   struct sockaddr_atmsvc addr;\n \n--- a/src/lane/lane_atm.c\n+++ b/src/lane/lane_atm.c\n@@ -138,7 +138,7 @@ atm_connect_back(const AtmAddr_t *our_ad\n   struct atm_blli blli;\n   struct atm_qos qos;\n   int fd, ret;\n-  int len = sizeof(address);\n+  socklen_t len = sizeof(address);\n   \n   fd = socket(PF_ATMSVC, SOCK_DGRAM, 0);\n   if (fd <0) {\n--- a/src/lane/lecs.c\n+++ b/src/lane/lecs.c\n@@ -119,7 +119,7 @@ int main(int argc, char **argv)\n   int just_dump=0;\n   fd_set fds;\n   struct sockaddr_atmsvc client;\n-  int len;\n+  socklen_t len;\n   unsigned char buffer[P_SIZE];\n \n   while(i!=-1) {\n--- a/src/lib/ans.c\n+++ b/src/lib/ans.c\n@@ -41,7 +41,7 @@\n static int ans(const char *text,int wanted,void *result,int res_len)\n {\n     unsigned char answer[MAX_ANSWER];\n-    unsigned char name[MAX_NAME];\n+    char name[MAX_NAME];\n     unsigned char *pos,*data,*found;\n     int answer_len,name_len,data_len,found_len;\n     int questions,answers;\n--- a/src/lib/sdu2cell.c\n+++ b/src/lib/sdu2cell.c\n@@ -15,7 +15,8 @@ int sdu2cell(int s,int sizes,const int *\n {\n     struct atm_qos qos;\n     int trailer,total,cells;\n-    int size,i;\n+    int i;\n+    socklen_t size;\n \n     size = sizeof(qos);\n     if (getsockopt(s,SOL_AAL,SO_ATMQOS,&qos,&size) < 0) return -1;\n--- a/src/lib/unix.c\n+++ b/src/lib/unix.c\n@@ -63,8 +63,8 @@ int un_attach(const char *path)\n int un_recv_connect(int s,void *buf,int size)\n {\n     struct sockaddr_un addr;\n-    int addr_size;\n     int len;\n+    socklen_t addr_size;\n \n     addr_size = sizeof(addr);\n     len = recvfrom(s,buf,size,0,(struct sockaddr *) &addr,&addr_size);\n--- a/src/maint/atmtcp.c\n+++ b/src/maint/atmtcp.c\n@@ -817,7 +817,8 @@ int main(int argc,char **argv)\n \t}\n \telse if (!strcmp(ARG,\"listen\") ||\n \t  (do_background = !strcmp(ARG,\"listen-bg\"))) {\n-\t    int fd,port,addr_len;\n+\t    int fd,port;\n+\t    socklen_t addr_len;\n \t    int *fd2 = alloc_t(int);\n \n \t    if ((fd = socket(PF_INET,SOCK_STREAM,0)) < 0) {\n--- a/src/maint/hediag.c\n+++ b/src/maint/hediag.c\n@@ -1,6 +1,7 @@\n #include <stdio.h>\n #include <stdlib.h>\n #include <unistd.h>\n+#include <string.h>\n #include <sys/ioctl.h>\n #include <sys/types.h>\n #include <sys/socket.h>\n--- a/src/mpoad/io.c\n+++ b/src/mpoad/io.c\n@@ -521,7 +521,8 @@ static int msg_from_mps(int slot)\n static int accept_conn(int slot)\n {\n         struct sockaddr_atmsvc sa;\n-        int i, new_fd, sa_len;\n+        int i, new_fd;\n+        socklen_t sa_len;\n \n         sa_len = sizeof(sa);\n         new_fd = accept(fds[slot].fd, (struct sockaddr *)&sa, &sa_len);\n--- a/src/sigd/io.c\n+++ b/src/sigd/io.c\n@@ -355,7 +355,7 @@ int get_pvc(int itf,int *vci)\n     error = 0;\n     if (bind(s,(struct sockaddr *) &addr,sizeof(addr)) < 0) error = errno;\n     else {\n-\tint size;\n+\tsocklen_t size;\n \n \tsize = sizeof(addr);\n \tif (getsockname(s,(struct sockaddr *) &addr,&size) < 0)\n--- a/src/test/ttcp.c\n+++ b/src/test/ttcp.c\n@@ -92,7 +92,8 @@ struct sockaddr_in frominet;\n struct sockaddr_atmsvc satm;\n struct atm_qos qos;\n \n-int domain, fromlen;\n+int domain;\n+socklen_t fromlen;\n int fd;\t\t\t\t/* fd of network socket */\n \n int buflen = 8 * 1024;\t\t/* length of buffer */\n@@ -466,7 +467,7 @@ int no_check = 0;\n \t    \n \t    {\n \t\tstruct sockaddr_atmsvc peer;\n-\t\tint peerlen = sizeof(peer);\n+\t\tsocklen_t peerlen = sizeof(peer);\n \t\tif (getpeername(fd, (struct sockaddr *) &peer, \n \t\t\t\t&peerlen) < 0) {\n \t\t    err(\"getpeername\");\n@@ -498,7 +499,7 @@ int no_check = 0;\n     /* set socket buffer size */\n #if defined(SO_SNDBUF) || defined(SO_RCVBUF)\n     if (sockbufsize) {\n-\tint len;\n+\tsocklen_t len;\n \n \tif (trans) {\n \t    /* set send socket buffer if we are transmitting */    \n--- a/src/mpoad/mpcd.8\n+++ b/src/mpoad/mpcd.8\n@@ -28,7 +28,7 @@ mpcd \\- ATM MPOA (Multi\\-Protocol Over A\n .B ]]\n .SH DESCRIPTION\n MPOA client\n-.SM(MPC) is responsible for creating and receiving\n+.SM (MPC) is responsible for creating and receiving\n internetwork layer shortcuts. Using these shortcuts MPCs forward\n unicast internetwork layer packets effectively over ATM without need\n for routing protocols.\n@@ -43,7 +43,7 @@ accepts shortcuts and packets arriving o\n shortcuts is done with the help of\n .SM MPOA\n server\n-.SM(MPS).\n+.SM (MPS).\n .PP\n Just as the Linux\n .SM LAN\n--- a/src/led/zeppelin.8\n+++ b/src/led/zeppelin.8\n@@ -99,7 +99,7 @@ Ring and ATM parts of the ELAN, so using\n recommended. Token Ring support has received less testing than its\n Ethernet counterpart.\n .SH FILES\n-.IP \\fI/var/run/lec[interface number].pid\\fP\n+.IP \\fI/var/run/lec[interface\\ number].pid\\fP\n The file containing the process id of zeppelin.\n .SH BUGS\n John Bonham died 1980 and Led Zeppelin broke.\n--- a/src/sigd/atmsigd.conf.4\n+++ b/src/sigd/atmsigd.conf.4\n@@ -125,7 +125,7 @@ a comment. The `#' character cannot be e\n .P\n If an option is specified in \\fBatmsigd.conf\\fP and on the command\n line, the command line has priority.\n-.COMPATIBILITY\n+.SH COMPATIBILITY\n Certain options used by past versions of \\fBatmsigd\\fP but no longer documented\n on the man page are still recognized and supported, but they also yield a\n warning message. Future versions of \\fBatmsigd\\fP will not recognize those\n"
  },
  {
    "path": "package/network/utils/linux-atm/patches/200-no_libfl.patch",
    "content": "--- a/src/qgen/Makefile.am\n+++ b/src/qgen/Makefile.am\n@@ -2,7 +2,7 @@ noinst_PROGRAMS = qgen\n \n qgen_SOURCES = common.c common.h file.c file.h first.c ql_y.y ql_l.l qgen.c \\\n \t\tqgen.h second.c third.c\n-qgen_LDADD = -lfl\n+qgen_LDADD = \n \n COMPILE = @CC_FOR_BUILD@ @CFLAGS_FOR_BUILD@\n LINK = @CC_FOR_BUILD@ @CFLAGS_FOR_BUILD@ -o $@\n--- a/src/qgen/Makefile.in\n+++ b/src/qgen/Makefile.in\n@@ -204,7 +204,7 @@ top_srcdir = @top_srcdir@\n qgen_SOURCES = common.c common.h file.c file.h first.c ql_y.y ql_l.l qgen.c \\\n \t\tqgen.h second.c third.c\n \n-qgen_LDADD = -lfl\n+qgen_LDADD =\n COMPILE = @CC_FOR_BUILD@ @CFLAGS_FOR_BUILD@\n LINK = @CC_FOR_BUILD@ @CFLAGS_FOR_BUILD@ -o $@\n \n--- a/src/sigd/Makefile.am\n+++ b/src/sigd/Makefile.am\n@@ -8,7 +8,7 @@ atmsigd_XTRAS = mess.o $(top_builddir)/s\n \t\t\t$(top_builddir)/src/q2931/qd.dump.o \\\n \t\t\t$(top_builddir)/src/lib/libatm.la \\\n \t\t\t$(top_builddir)/src/saal/libsaal.a\n-atmsigd_LDADD = $(atmsigd_XTRAS) -lfl\n+atmsigd_LDADD = $(atmsigd_XTRAS) \n atmsigd_DEPENDENCIES = mess.c $(atmsigd_XTRAS)\n \n CLEANFILES = mess.c\n--- a/src/sigd/Makefile.in\n+++ b/src/sigd/Makefile.in\n@@ -245,7 +245,7 @@ atmsigd_XTRAS = mess.o $(top_builddir)/s\n \t\t\t$(top_builddir)/src/lib/libatm.la \\\n \t\t\t$(top_builddir)/src/saal/libsaal.a\n \n-atmsigd_LDADD = $(atmsigd_XTRAS) -lfl\n+atmsigd_LDADD = $(atmsigd_XTRAS) \n atmsigd_DEPENDENCIES = mess.c $(atmsigd_XTRAS)\n CLEANFILES = mess.c\n sysconf_DATA = atmsigd.conf\n--- a/src/switch/debug/debug.c\n+++ b/src/switch/debug/debug.c\n@@ -20,6 +20,11 @@\n \n #define PRV(call) ((FAB *) (call)->fab)\n \n+int yywrap(void)\n+{\n+        return 1;\n+}\n+\n \n typedef struct _fab {\n     CALL *next; /* relay.c may not keep track of calls, but WE are */\n--- a/src/switch/debug/Makefile.am\n+++ b/src/switch/debug/Makefile.am\n@@ -5,7 +5,7 @@ INCLUDES = -I$(srcdir)/../../q2931\n sw_debug_SOURCES = debug.c\n sw_debug_XTRAS = $(top_builddir)/src/switch/libsw.a \\\n \t\t\t$(top_builddir)/src/lib/libatm.la\n-sw_debug_LDADD = $(sw_debug_XTRAS) -lfl\n+sw_debug_LDADD = $(sw_debug_XTRAS) \n \t\t\t\n sw_debug_DEPENDENCIES = $(sw_debug_XTRAS)\n \n--- a/src/switch/debug/Makefile.in\n+++ b/src/switch/debug/Makefile.in\n@@ -200,7 +200,8 @@ sw_debug_SOURCES = debug.c\n sw_debug_XTRAS = $(top_builddir)/src/switch/libsw.a \\\n \t\t\t$(top_builddir)/src/lib/libatm.la\n \n-sw_debug_LDADD = $(sw_debug_XTRAS) -lfl\n+sw_debug_LDADD = $(sw_debug_XTRAS)\n+\n sw_debug_DEPENDENCIES = $(sw_debug_XTRAS)\n EXTRA_DIST = demo README\n all: all-am\n--- a/src/switch/tcp/Makefile.am\n+++ b/src/switch/tcp/Makefile.am\n@@ -5,7 +5,7 @@ INCLUDES = -I$(srcdir)/../../q2931\n sw_tcp_SOURCES = tcpsw.c\n sw_tcp_XTRAS = $(top_builddir)/src/switch/libsw.a \\\n \t\t$(top_builddir)/src/lib/libatm.la\n-sw_tcp_LDADD = $(sw_tcp_XTRAS) -lfl\n+sw_tcp_LDADD = $(sw_tcp_XTRAS) \n sw_tcp_DEPENDENCIES = $(sw_tcp_XTRAS)\n \n EXTRA_DIST = mkfiles README\n--- a/src/switch/tcp/Makefile.in\n+++ b/src/switch/tcp/Makefile.in\n@@ -200,7 +200,7 @@ sw_tcp_SOURCES = tcpsw.c\n sw_tcp_XTRAS = $(top_builddir)/src/switch/libsw.a \\\n \t\t$(top_builddir)/src/lib/libatm.la\n \n-sw_tcp_LDADD = $(sw_tcp_XTRAS) -lfl\n+sw_tcp_LDADD = $(sw_tcp_XTRAS) \n sw_tcp_DEPENDENCIES = $(sw_tcp_XTRAS)\n EXTRA_DIST = mkfiles README\n all: all-am\n--- a/src/switch/tcp/tcpsw.c\n+++ b/src/switch/tcp/tcpsw.c\n@@ -35,6 +35,10 @@\n #define MAX_PACKET (ATM_MAX_AAL5_PDU+sizeof(struct atmtcp_hdr))\n #define BUFFER_SIZE (MAX_PACKET*2)\n \n+int yywrap(void)\n+{\n+        return 1;\n+}\n \n typedef struct _table {\n     struct _link *out;\t/* output port */\n--- a/src/test/Makefile.am\n+++ b/src/test/Makefile.am\n@@ -20,7 +20,7 @@ br_SOURCES = br.c\n bw_SOURCES = bw.c\n isp_SOURCES = isp.c isp.h ispl_y.y ispl_l.l\n isp_XTRAS = $(LDADD)\n-isp_LDADD = $(isp_XTRAS) -lfl\n+isp_LDADD = $(isp_XTRAS)\n isp_DEPENDENCIES = $(isp_XTRAS)\n window_SOURCES = window.c\n \n--- a/src/test/Makefile.in\n+++ b/src/test/Makefile.in\n@@ -283,7 +283,7 @@ br_SOURCES = br.c\n bw_SOURCES = bw.c\n isp_SOURCES = isp.c isp.h ispl_y.y ispl_l.l\n isp_XTRAS = $(LDADD)\n-isp_LDADD = $(isp_XTRAS) -lfl\n+isp_LDADD = $(isp_XTRAS)\n isp_DEPENDENCIES = $(isp_XTRAS)\n window_SOURCES = window.c\n CLEANFILES = errnos.inc\n--- a/src/test/ispl_l.l\n+++ b/src/test/ispl_l.l\n@@ -18,6 +18,11 @@\n #include \"ispl_y.h\"\n \n \n+int yywrap(void)\n+{\n+       return 1;\n+}\n+\n static int lineno = 1;\n \n %}\n--- a/src/qgen/ql_l.l\n+++ b/src/qgen/ql_l.l\n@@ -11,6 +11,11 @@\n #include \"ql_y.h\"\n \n \n+int yywrap(void)\n+{\n+        return 1;\n+}\n+\n typedef struct _tree {\n     struct _tree *left,*right;\n     const char str[0];\n--- a/src/sigd/cfg_l.l\n+++ b/src/sigd/cfg_l.l\n@@ -16,6 +16,10 @@\n \n #include \"cfg_y.h\"\n \n+int yywrap(void)\n+{\n+        return 1;\n+}\n \n static int lineno = 1;\n static int token; /* f@#%ing flex doesn't grok return after BEGIN */\n"
  },
  {
    "path": "package/network/utils/linux-atm/patches/300-objcopy_path.patch",
    "content": "--- a/src/extra/Makefile.am\n+++ b/src/extra/Makefile.am\n@@ -7,6 +7,8 @@ EXTRA_DIST = linux-atm.spec.in \\\n BUILT_SOURCES = pca200e.bin pca200e_ecd.bin2 sba200e_ecd.bin2\n CLEANFILES = pca200e.bin pca200e_ecd.bin2 sba200e_ecd.bin2\n \n+OBJCOPY = objcopy\n+\n install-exec-hook:\n \t$(MKDIR_P) $(DESTDIR)/lib/firmware\n \t$(INSTALL_DATA) $(srcdir)/pca200e.bin $(DESTDIR)/lib/firmware\n@@ -14,7 +16,7 @@ install-exec-hook:\n \t$(INSTALL_DATA) $(srcdir)/sba200e_ecd.bin2 $(DESTDIR)/lib/firmware\n \n %.bin %.bin2: %.data\n-\tobjcopy -Iihex $< -Obinary $@.gz\n+\t$(OBJCOPY) -Iihex $< -Obinary $@.gz\n \tgzip -n -df $@.gz\n \n \n--- a/src/extra/Makefile.in\n+++ b/src/extra/Makefile.in\n@@ -187,6 +187,8 @@ CLEANFILES = pca200e.bin pca200e_ecd.bin\n all: $(BUILT_SOURCES)\n \t$(MAKE) $(AM_MAKEFLAGS) all-am\n \n+OBJCOPY = objcopy\n+\n .SUFFIXES:\n $(srcdir)/Makefile.in:  $(srcdir)/Makefile.am  $(am__configure_deps)\n \t@for dep in $?; do \\\n@@ -385,7 +387,7 @@ install-exec-hook:\n \t$(INSTALL_DATA) $(srcdir)/sba200e_ecd.bin2 $(DESTDIR)/lib/firmware\n \n %.bin %.bin2: %.data\n-\tobjcopy -Iihex $< -Obinary $@.gz\n+\t$(OBJCOPY) -Iihex $< -Obinary $@.gz\n \tgzip -n -df $@.gz\n \n # Tell versions [3.59,3.63) of GNU make to not export all variables.\n"
  },
  {
    "path": "package/network/utils/linux-atm/patches/400-portability_fixes.patch",
    "content": "--- a/src/ilmid/io.c\n+++ b/src/ilmid/io.c\n@@ -48,6 +48,14 @@\n \t\t\t     be manually configured (after ilmid has\n \t\t\t     registered the \"official\" address) - HACK */\n \n+#ifndef SUN_LEN\n+# include <string.h>            /* For prototype of `strlen'.  */\n+\n+/* Evaluate to actual length of the `sockaddr_un' structure.  */\n+# define SUN_LEN(ptr) ((size_t) (((struct sockaddr_un *) 0)->sun_path)        \\\n+                      + strlen ((ptr)->sun_path))\n+#endif\n+\n extern SysGroup *remsys;\n extern State ilmi_state;\n static short atm_itf = -1; /* bad value */\n--- a/src/mpoad/io.c\n+++ b/src/mpoad/io.c\n@@ -10,14 +10,7 @@\n #include <errno.h>\n #include <sys/ioctl.h>\n #include <sys/param.h> /* for OPEN_MAX   */\n-#if __GLIBC__ >= 2\n #include <sys/poll.h>\n-#else /* ugly hack to make it compile on RH 4.2 - WA */\n-#include <syscall.h>\n-#include <linux/poll.h>\n-#define SYS_poll 168\n-_syscall3(int,poll,struct pollfd *,ufds,unsigned int,nfds,int,timeout);\n-#endif\n #include <atm.h>\n #include <linux/types.h>\n #include <linux/atmioc.h>\n--- a/src/sigd/atmsigd.c\n+++ b/src/sigd/atmsigd.c\n@@ -283,12 +283,11 @@ static void setup_signals(void)\n /* ------------------------------- main ...  ------------------------------- */\n \n \n-static void trace_on_exit(int status,void *dummy)\n+static void trace_on_exit(void)\n {\n     char path[PATH_MAX+1];\n     FILE *file;\n \n-    if (!status) return;\n     if (!dump_dir) file = stderr;\n     else {\n \tsprintf(path,\"atmsigd.%d.trace.exit\",getpid());\n@@ -517,7 +516,7 @@ int main(int argc,char **argv)\n \t    exit(0);\n \t}\n     }\n-    (void) on_exit(trace_on_exit,NULL);\n+    (void) atexit(trace_on_exit);\n     poll_loop();\n     close_all();\n     for (sig = entities; sig; sig = sig->next) stop_saal(&sig->saal);\n--- a/src/test/align.c\n+++ b/src/test/align.c\n@@ -24,7 +24,7 @@\n #include <signal.h>\n #include <sys/types.h>\n #include <sys/socket.h>\n-#include <sys/errno.h>\n+#include <errno.h>\n #include <atm.h>\n \n \n"
  },
  {
    "path": "package/network/utils/linux-atm/patches/500-br2684ctl_script.patch",
    "content": "--- a/src/br2684/br2684ctl.c\n+++ b/src/br2684/br2684ctl.c\n@@ -1,3 +1,4 @@\n+#define _GNU_SOURCE\n #include <stdio.h>\n #include <stdlib.h>\n #include <unistd.h>\n@@ -43,6 +44,7 @@ struct br2684_params {\n \n \n int lastsock, lastitf;\n+static char *up_script;\n \n \n void fatal(const char *str, int err)\n@@ -185,6 +187,8 @@ int assign_vcc(char *astr, int encap, in\n \n void start_interface(struct br2684_params* params)\n {\n+  char *cmd;\n+\n   if (params->astr==NULL) {\n     syslog(LOG_ERR, \"Required ATM parameters not specified.\");\n     exit(1);\n@@ -193,13 +197,18 @@ void start_interface(struct br2684_param\n   create_br(params->itfnum, params->payload);\n   assign_vcc(params->astr, params->encap, params->payload, params->sndbuf,\n \t     params->reqqos);\n+  if (up_script) {\n+    asprintf(&cmd, \"%s nas%d\", up_script, lastitf);\n+    system(cmd);\n+    free(cmd);\n+  }\n }\n \n \n void usage(char *s)\n {\n   printf(\"usage: %s [-b] [[-c number] [-e 0|1] [-s sndbuf] [-q qos] [-p 0|1] \"\n-\t \"[-a [itf.]vpi.vci]*]*\\n\", s);\n+\t \"[-a [itf.]vpi.vci]*]* [-S script]\\n\", s);\n   printf(\"  encapsulations: 0=llc, 1=vcmux\\n  payloads: 0=routed, 1=bridged\\n\");\n   exit(1);\n }\n@@ -225,7 +234,7 @@ int main (int argc, char **argv)\n \n   openlog (LOG_NAME,LOG_OPTION,LOG_FACILITY);\n   if (argc>1)\n-    while ((c = getopt(argc, argv,\"q:a:bc:e:s:p:?h\")) !=EOF)\n+    while ((c = getopt(argc, argv,\"q:a:bc:e:s:S:p:?h\")) !=EOF)\n       switch (c) {\n       case 'q':\n \tprintf (\"optarg : %s\",optarg);\n@@ -258,6 +267,9 @@ int main (int argc, char **argv)\n \t  params.sndbuf=8192;\n \t}\n \tbreak;\n+      case 'S':\n+\tup_script = optarg;\n+\tbreak;\n       case 'p':\t/* payload type: routed (0) or bridged (1) */\n #ifdef BR2684_FLAG_ROUTED\n \tparams.payload = atoi(optarg);\n"
  },
  {
    "path": "package/network/utils/linux-atm/patches/501-br2684ctl_itfname.patch",
    "content": "--- a/src/br2684/br2684ctl.c\n+++ b/src/br2684/br2684ctl.c\n@@ -45,6 +45,7 @@ struct br2684_params {\n \n int lastsock, lastitf;\n static char *up_script;\n+const char *itfname = \"nas\";\n \n \n void fatal(const char *str, int err)\n@@ -73,7 +74,7 @@ int create_pidfile(int num)\n \n   if (num < 0) return -1;\n \n-  snprintf(name, 32, \"/var/run/br2684ctl-nas%d.pid\", num);\n+  snprintf(name, 32, \"/var/run/br2684ctl-%s%d.pid\", itfname, num);\n   pidfile = fopen(name, \"w\");\n   if (pidfile == NULL) return -1;\n   fprintf(pidfile, \"%d\", getpid());\n@@ -102,7 +103,7 @@ int create_br(int itfnum, int payload)\n         ni.media |= BR2684_FLAG_ROUTED;\n #endif\n       ni.mtu = 1500;\n-      sprintf(ni.ifname, \"nas%d\", itfnum);\n+      sprintf(ni.ifname, \"%s%d\", itfname, itfnum);\n       err=ioctl (lastsock, ATM_NEWBACKENDIF, &ni);\n   \n       if (err == 0)\n@@ -167,7 +168,7 @@ int assign_vcc(char *astr, int encap, in\n     \n     be.backend_num = ATM_BACKEND_BR2684;\n     be.ifspec.method = BR2684_FIND_BYIFNAME;\n-    sprintf(be.ifspec.spec.ifname, \"nas%d\", lastitf);\n+    sprintf(be.ifspec.spec.ifname, \"%s%d\", itfname, lastitf);\n     be.fcs_in = BR2684_FCSIN_NO;\n     be.fcs_out = BR2684_FCSOUT_NO;\n     be.fcs_auto = 0;\n@@ -198,7 +199,7 @@ void start_interface(struct br2684_param\n   assign_vcc(params->astr, params->encap, params->payload, params->sndbuf,\n \t     params->reqqos);\n   if (up_script) {\n-    asprintf(&cmd, \"%s nas%d\", up_script, lastitf);\n+    asprintf(&cmd, \"%s %s%d\", up_script, itfname, lastitf);\n     system(cmd);\n     free(cmd);\n   }\n@@ -207,7 +208,7 @@ void start_interface(struct br2684_param\n \n void usage(char *s)\n {\n-  printf(\"usage: %s [-b] [[-c number] [-e 0|1] [-s sndbuf] [-q qos] [-p 0|1] \"\n+  printf(\"usage: %s [-b] [-n name] [[-c number] [-e 0|1] [-s sndbuf] [-q qos] [-p 0|1] \"\n \t \"[-a [itf.]vpi.vci]*]* [-S script]\\n\", s);\n   printf(\"  encapsulations: 0=llc, 1=vcmux\\n  payloads: 0=routed, 1=bridged\\n\");\n   exit(1);\n@@ -234,7 +235,7 @@ int main (int argc, char **argv)\n \n   openlog (LOG_NAME,LOG_OPTION,LOG_FACILITY);\n   if (argc>1)\n-    while ((c = getopt(argc, argv,\"q:a:bc:e:s:S:p:?h\")) !=EOF)\n+    while ((c = getopt(argc, argv,\"q:a:bn:c:e:s:S:p:?h\")) !=EOF)\n       switch (c) {\n       case 'q':\n \tprintf (\"optarg : %s\",optarg);\n@@ -247,6 +248,9 @@ int main (int argc, char **argv)\n       case 'b':\n \tbackground=1;\n \tbreak;\n+      case 'n':\n+\titfname = optarg;\n+\tbreak;\n       case 'c':\n \t/* temporary, to make it work with multiple interfaces: */\n \tif (params.itfnum>=0) start_interface(&params);\n"
  },
  {
    "path": "package/network/utils/linux-atm/patches/510-remove-LINUX_NETDEVICE-hack.patch",
    "content": "This fixes the following compile problem with kernel 4.20:\n\nIn file included from arp.c:20:0:\ninclude/linux/if_arp.h:121:16: error: 'IFNAMSIZ' undeclared here (not in a function)\n  char  arp_dev[IFNAMSIZ];\n                ^~~~~~~~\nmake[7]: *** [Makefile:459: arp.o] Error 1\n\nThis is caused by commit 6a12709da354 (\"net: if_arp: use define instead \nof hard-coded value\") in the upstream Linux kernel which is integrated \nin Linux 4.20.\n\n--- a/src/oamd/io.c\n+++ b/src/oamd/io.c\n@@ -20,7 +20,6 @@\n #include <net/if.h>\n #include <netinet/in.h>\n #include <atm.h>\n-#define _LINUX_NETDEVICE_H\t/* glibc2 */\n #include <linux/types.h>\n #include <linux/if_arp.h>\n \n--- a/src/arpd/itf.c\n+++ b/src/arpd/itf.c\n@@ -12,7 +12,6 @@\n #include <sys/types.h>\n #include <linux/atmclip.h>\n #include <sys/socket.h>\n-#define _LINUX_NETDEVICE_H /* glibc2 */\n #include <linux/types.h>\n #include <linux/if_arp.h>\n \n--- a/src/arpd/io.c\n+++ b/src/arpd/io.c\n@@ -21,7 +21,6 @@\n #include <atm.h>\n #include <linux/atmclip.h> /* for CLIP_DEFAULT_IDLETIMER */\n #include <linux/atmarp.h>\n-#define _LINUX_NETDEVICE_H /* glibc2 */\n #include <linux/types.h>\n #include <linux/if_arp.h>\n \n--- a/src/arpd/arp.c\n+++ b/src/arpd/arp.c\n@@ -15,7 +15,6 @@\n #include <sys/types.h>\n #include <sys/socket.h> /* for linux/if_arp.h */\n #include <netinet/in.h> /* for ntohs, etc. */\n-#define _LINUX_NETDEVICE_H /* very crude hack for glibc2 */\n #include <linux/types.h>\n #include <linux/if_arp.h>\n #include <linux/if_ether.h>\n"
  },
  {
    "path": "package/network/utils/linux-atm/patches/600-fix-format-errors.patch",
    "content": "--- a/src/test/ttcp.c\n+++ b/src/test/ttcp.c\n@@ -664,7 +664,7 @@ int no_check = 0;\n     exit(0);\n \n   usage:\n-    fprintf(stderr, Usage);\n+    fprintf(stderr, \"%s\", Usage);\n     exit(1);\n }\n \n"
  },
  {
    "path": "package/network/utils/linux-atm/patches/700-musl-include.patch",
    "content": "--- a/src/include/atmd.h\n+++ b/src/include/atmd.h\n@@ -10,6 +10,7 @@\n \n #include <stdint.h>\n #include <stdio.h>\n+#include <string.h>\n #include <sys/types.h>\n #include <sys/time.h>\n \n--- a/src/lib/unix.c\n+++ b/src/lib/unix.c\n@@ -8,6 +8,7 @@\n \n #include <stdlib.h>\n #include <stdio.h>\n+#include <string.h>\n #include <unistd.h>\n #include <errno.h>\n #include <sys/types.h>\n--- a/src/sigd/kernel.c\n+++ b/src/sigd/kernel.c\n@@ -8,6 +8,7 @@\n \n #include <stdlib.h>\n #include <stdio.h>\n+#include <string.h>\n #include <errno.h>\n #include <assert.h>\n \n"
  },
  {
    "path": "package/network/utils/linux-atm/patches/800-include_sockios.patch",
    "content": "--- a/src/maint/saaldump.c\t2020-03-29 22:58:01.089711789 +0200\n+++ b/src/maint/saaldump.c\t2020-03-29 22:59:17.564639387 +0200\n@@ -6,6 +6,7 @@\n #include <config.h>\n #endif\n\n+#include <linux/sockios.h>\n #include <stdlib.h>\n #include <stdarg.h>\n #include <stdio.h>\n--- a/src/maint/atmdump.c\t2020-03-29 22:58:18.573694469 +0200\n+++ b/src/maint/atmdump.c\t2020-03-29 22:58:49.956729365 +0200\n@@ -6,6 +6,7 @@\n #include <config.h>\n #endif\n\n+#include <linux/sockios.h>\n #include <stdlib.h>\n #include <stdio.h>\n #include <unistd.h>\n\n"
  },
  {
    "path": "package/network/utils/ltq-dsl-base/Makefile",
    "content": "#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=ltq-dsl-base\nPKG_RELEASE:=3\n\nPKG_FLAGS:=nonshared\n\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine Package/ltq-dsl-base\n  SECTION:=net\n  CATEGORY:=Network\n  TITLE:=DSL related files for Intel/Lantiq DSL Chipsets\n  URL:=http://openwrt.org/\n  DEPENDS:=@TARGET_lantiq +jshn\nendef\n\ndefine Package/ltq-dsl-base/description\n  This package contains DSL related files for Intel/Lantiq DSL Chipsets.\nendef\n\ndefine Build/Compile\nendef\n\ndefine Package/ltq-dsl-base/install\n\t$(CP) ./files/* $(1)/\nendef\n\n$(eval $(call BuildPackage,ltq-dsl-base))\n"
  },
  {
    "path": "package/network/utils/ltq-dsl-base/files/etc/hotplug.d/dsl/led_dsl.sh",
    "content": "#!/bin/sh\n\n[ \"$DSL_NOTIFICATION_TYPE\" = \"DSL_INTERFACE_STATUS\" ] || exit 0\n\n. /lib/functions.sh\n. /lib/functions/leds.sh\n\nled_dsl_up() {\n\tcase \"$(config_get led_dsl trigger)\" in\n\t\"netdev\")\n\t\tled_set_attr $1 \"trigger\" \"netdev\"\n\t\tled_set_attr $1 \"device_name\" \"$(config_get led_dsl dev)\"\n\t\tfor m in $(config_get led_dsl mode); do\n\t\t\tled_set_attr $1 \"$m\" \"1\"\n\t\tdone\n\t\t;;\n\t*)\n\t\tled_on $1\n\t\t;;\n\tesac\n}\n\nconfig_load system\nconfig_get led led_dsl sysfs\nif [ -n \"$led\" ]; then\n\tcase \"$DSL_INTERFACE_STATUS\" in\n\t  \"HANDSHAKE\")  led_timer $led 500 500;;\n\t  \"TRAINING\")   led_timer $led 200 200;;\n\t  \"UP\")\t\tled_dsl_up $led;;\n\t  *)\t\tled_off $led\n\tesac\nfi\n"
  },
  {
    "path": "package/network/utils/ltq-dsl-base/files/etc/hotplug.d/dsl/pppoa.sh",
    "content": "#!/bin/sh\n\n[ \"$DSL_NOTIFICATION_TYPE\" = \"DSL_INTERFACE_STATUS\" ] || exit 0\n\n. /usr/share/libubox/jshn.sh\n. /lib/functions.sh\n\ninclude /lib/network\nscan_interfaces\n\ninterfaces=$(ubus list network.interface.\\* | cut -d\".\" -f3)\nfor ifc in $interfaces; do\n\n\tjson_load \"$(ifstatus $ifc)\"\n\n\tjson_get_var proto proto\n\tif [ \"$proto\" != \"pppoa\" ]; then\n\t\tcontinue\n\tfi\n\n\tjson_get_var up up\n\tconfig_get_bool auto \"$ifc\" auto 1\n\tif [ \"$DSL_INTERFACE_STATUS\" = \"UP\" ]; then\n\t\tif [ \"$up\" != 1 ] && [ \"$auto\" = 1 ]; then\n\t\t\t( sleep 1; ifup \"$ifc\" ) &\n\t\tfi\n\telse\n\t\tif [ \"$up\" = 1 ] && [ \"$auto\" = 1 ]; then\n\t\t\t( sleep 1; ifdown \"$ifc\" ) &\n\t\telse\n\t\t\tjson_get_var autostart autostart\n\t\t\tif [ \"$up\" != 1 ] && [ \"$autostart\" = 1 ]; then\n\t\t\t\t( sleep 1; ifdown \"$ifc\" ) &\n\t\t\tfi\n\t\tfi\n\tfi\ndone\n"
  },
  {
    "path": "package/network/utils/ltq-dsl-base/files/sbin/dsl_notify.sh",
    "content": "#!/bin/sh\n#\n# This script is called by dsl_cpe_control whenever there is a DSL event\n# and calls any available hotplug script(s) in /etc/hotplug.d/dsl.\n\nexec /sbin/hotplug-call dsl\n"
  },
  {
    "path": "package/network/utils/nftables/Makefile",
    "content": "# Copyright (C) 2015 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=nftables\nPKG_VERSION:=1.0.2\nPKG_RELEASE:=2\n\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.bz2\nPKG_SOURCE_URL:=https://netfilter.org/projects/$(PKG_NAME)/files\nPKG_HASH:=0b28a36ffcf4567b841de7bd3f37918b1fed27859eb48bdec51e1f7a83954c02\nPKG_MAINTAINER:=\nPKG_LICENSE:=GPL-2.0\n\nPKG_FIXUP:=autoreconf\nPKG_INSTALL:=1\n\ninclude $(INCLUDE_DIR)/package.mk\n\nDISABLE_NLS:=\n\nCONFIGURE_ARGS += \\\n        --disable-debug \\\n        --disable-man-doc \\\n        --with-mini-gmp \\\n        --without-cli \\\n        --disable-python\n\ndefine Package/nftables/Default\n  SECTION:=net\n  CATEGORY:=Network\n  SUBMENU:=Firewall\n  TITLE:=nftables userspace utility\n  DEPENDS:=+kmod-nft-core +libnftnl\n  URL:=http://netfilter.org/projects/nftables/\n  PROVIDES:=nftables\nendef\n\ndefine Package/nftables-nojson\n  $(Package/nftables/Default)\n  TITLE+= no JSON support\n  VARIANT:=nojson\n  DEFAULT_VARIANT:=1\n  CONFLICTS:=nftables-json\nendef\n\ndefine Package/nftables-json\n  $(Package/nftables/Default)\n  TITLE+= with JSON support\n  VARIANT:=json\n  DEPENDS+=+jansson\nendef\n\nifeq ($(BUILD_VARIANT),json)\n  CONFIGURE_ARGS += --with-json\nendif\n\nTARGET_CFLAGS += -flto\nTARGET_LDFLAGS += -flto\n\ndefine Build/InstallDev\n\t$(INSTALL_DIR) $(1)/usr/lib $(1)/usr/include\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/*.so* $(1)/usr/lib/\n\t$(CP) $(PKG_INSTALL_DIR)/usr/include/nftables $(1)/usr/include/\n\t$(INSTALL_DIR) $(1)/usr/lib/pkgconfig\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/pkgconfig/libnftables.pc \\\n\t\t$(1)/usr/lib/pkgconfig/\nendef\n\ndefine Package/nftables/install/Default\n\t$(INSTALL_DIR) $(1)/usr/sbin\n\t$(CP) $(PKG_INSTALL_DIR)/usr/sbin/nft $(1)/usr/sbin/\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/*.so* $(1)/usr/lib/\nendef\n\nPackage/nftables-nojson/install = $(Package/nftables/install/Default)\nPackage/nftables-json/install = $(Package/nftables/install/Default)\n\n$(eval $(call BuildPackage,nftables-nojson))\n$(eval $(call BuildPackage,nftables-json))\n"
  },
  {
    "path": "package/network/utils/nftables/patches/001-examples-compile-with-make-check.patch",
    "content": "From 18a08fb7f0443f8bde83393bd6f69e23a04246b3 Mon Sep 17 00:00:00 2001\nFrom: Pablo Neira Ayuso <pablo@netfilter.org>\nDate: Tue, 22 Feb 2022 00:56:36 +0100\nSubject: examples: compile with `make check' and add AM_CPPFLAGS\n\nCompile examples via `make check' like libnftnl does. Use AM_CPPFLAGS to\nspecify local headers via -I.\n\nUnfortunately, `make distcheck' did not catch this compile time error in\nmy system, since it was using the nftables/libnftables.h file of the\nprevious nftables release.\n\nFixes: 5b364657a35f (\"build: missing SUBIRS update\")\nFixes: caf2a6ad2d22 (\"examples: add libnftables example program\")\nSigned-off-by: Pablo Neira Ayuso <pablo@netfilter.org>\n---\n examples/Makefile.am | 4 +++-\n 1 file changed, 3 insertions(+), 1 deletion(-)\n\n--- a/examples/Makefile.am\n+++ b/examples/Makefile.am\n@@ -1,4 +1,6 @@\n-noinst_PROGRAMS\t= nft-buffer\t\t\\\n+check_PROGRAMS\t= nft-buffer\t\t\\\n \t\t  nft-json-file\n \n+AM_CPPFLAGS = -I$(top_srcdir)/include\n+\n LDADD = $(top_builddir)/src/libnftables.la\n"
  },
  {
    "path": "package/network/utils/resolveip/Makefile",
    "content": "#\n# Copyright (C) 2011-2012 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=resolveip\nPKG_RELEASE:=2\nPKG_LICENSE:=GPL-2.0\n\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine Package/resolveip\n  SECTION:=utils\n  CATEGORY:=Base system\n  TITLE:=Simple DNS resolver with configurable timeout\n  MAINTAINER:=Jo-Philipp Wich <jo@mein.io>\nendef\n\ndefine Package/resolveip/description\n This package contains the small resolveip utility which\n can be used by scripts to turn host names into numeric\n IP addresses. It supports IPv4 and IPv6 resolving and\n has a configurable timeout to guarantee a certain maximum\n runtime in case of slow or defunct DNS servers.\nendef\n\ndefine Build/Compile\n\t$(TARGET_CC) $(TARGET_CFLAGS) -Wall \\\n\t\t-o $(PKG_BUILD_DIR)/resolveip $(PKG_BUILD_DIR)/resolveip.c\nendef\n\ndefine Package/resolveip/install\n\t$(INSTALL_DIR) $(1)/usr/bin\n\t$(INSTALL_BIN) $(PKG_BUILD_DIR)/resolveip $(1)/usr/bin/\nendef\n\n$(eval $(call BuildPackage,resolveip))\n"
  },
  {
    "path": "package/network/utils/resolveip/src/resolveip.c",
    "content": "/*\n * Based on code found at https://dev.openwrt.org/ticket/4876 .\n * Extended by Jo-Philipp Wich <jo@mein.io> for use in OpenWrt.\n *\n * You may use this program under the terms of the GPLv2 license.\n */\n\n#include <string.h>\n#include <stdio.h>\n#include <sys/types.h>\n#include <sys/socket.h>\n#include <netdb.h>\n#include <arpa/inet.h>\n#include <netinet/in.h>\n#include <stdlib.h>\n#include <unistd.h>\n#include <signal.h>\n\n\nstatic void abort_query(int sig)\n{\n\texit(1);\n}\n\nstatic void show_usage(void)\n{\n\tprintf(\"Usage:\\n\");\n\tprintf(\"\tresolveip -h\\n\");\n\tprintf(\"\tresolveip [-t timeout] hostname\\n\");\n\tprintf(\"\tresolveip -4 [-t timeout] hostname\\n\");\n\tprintf(\"\tresolveip -6 [-t timeout] hostname\\n\");\n\texit(255);\n}\n\nint main(int argc, char **argv)\n{\n\tint timeout = 3;\n\tint opt;\n\tchar ipaddr[INET6_ADDRSTRLEN];\n\tvoid *addr;\n\tstruct addrinfo *res, *rp;\n\tstruct sigaction sa = {\t.sa_handler = &abort_query };\n\tstruct addrinfo hints = {\n\t\t.ai_family   = AF_UNSPEC,\n\t\t.ai_socktype = SOCK_STREAM,\n\t\t.ai_protocol = IPPROTO_TCP,\n\t\t.ai_flags    = 0\n\t};\n\n\twhile ((opt = getopt(argc, argv, \"46t:h\")) > -1)\n\t{\n\t\tswitch ((char)opt)\n\t\t{\n\t\t\tcase '4':\n\t\t\t\thints.ai_family = AF_INET;\n\t\t\t\tbreak;\n\n\t\t\tcase '6':\n\t\t\t\thints.ai_family = AF_INET6;\n\t\t\t\tbreak;\n\n\t\t\tcase 't':\n\t\t\t\ttimeout = atoi(optarg);\n\t\t\t\tif (timeout <= 0)\n\t\t\t\t\tshow_usage();\n\t\t\t\tbreak;\n\n\t\t\tcase 'h':\n\t\t\t\tshow_usage();\n\t\t\t\tbreak;\n\t\t}\n\t}\n\n\tif (!argv[optind])\n\t\tshow_usage();\n\n\tsigaction(SIGALRM, &sa, NULL);\n\talarm(timeout);\n\n\tif (getaddrinfo(argv[optind], NULL, &hints, &res))\n\t\texit(2);\n\n\tfor (rp = res; rp != NULL; rp = rp->ai_next)\n\t{\n\t\taddr = (rp->ai_family == AF_INET)\n\t\t\t? (void *)&((struct sockaddr_in *)rp->ai_addr)->sin_addr\n\t\t\t: (void *)&((struct sockaddr_in6 *)rp->ai_addr)->sin6_addr\n\t\t;\n\n\t\tif (!inet_ntop(rp->ai_family, addr, ipaddr, INET6_ADDRSTRLEN - 1))\n\t\t\texit(3);\n\n\t\tprintf(\"%s\\n\", ipaddr);\n\t}\n\n\tfreeaddrinfo(res);\n\texit(0);\n}\n"
  },
  {
    "path": "package/network/utils/rssileds/Makefile",
    "content": "#\n# Copyright (C) 2011-2012 Daniel Golle <dgolle@allnet.de>\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=rssileds\nPKG_RELEASE:=3\nPKG_LICNESE:=GPL-2.0+\n\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine Package/rssileds\n  SECTION:=net\n  CATEGORY:=Network\n  TITLE:=RSSI real-time LED indicator\n  DEPENDS:=+libiwinfo +libnl-tiny +libubox +libuci\n  MAINTAINER:=Daniel Golle <daniel@makrotopia.org>\nendef\n\ndefine Package/rssileds/description\n  A small process written in C to update the signal-strength indicator LEDs\nendef\n\ndefine Build/Configure\nendef\n\nTARGET_LDFLAGS += -liwinfo -luci -lubox -lnl-tiny\n\ndefine Build/Compile\n\t$(TARGET_CC) $(TARGET_CFLAGS) $(TARGET_CPPFLAGS) -Wall \\\n\t\t-o $(PKG_BUILD_DIR)/rssileds $(PKG_BUILD_DIR)/rssileds.c $(TARGET_LDFLAGS)\nendef\n\ndefine Package/rssileds/install\n\t$(INSTALL_DIR) $(1)/etc/init.d\n\t$(INSTALL_BIN) ./files/rssileds.init $(1)/etc/init.d/rssileds\n\t$(INSTALL_DIR) $(1)/usr/sbin\n\t$(INSTALL_BIN) $(PKG_BUILD_DIR)/rssileds $(1)/usr/sbin/\n\t$(INSTALL_DIR) $(1)/usr/libexec/led-trigger\n\t$(INSTALL_BIN) ./files/rssi $(1)/usr/libexec/led-trigger/\nendef\n\n$(eval $(call BuildPackage,rssileds))\n"
  },
  {
    "path": "package/network/utils/rssileds/files/rssi",
    "content": "#!/bin/sh\n\nlogger -t led-trigger \"LED trigger rssi is handled by /etc/init.d/rssileds\"\n"
  },
  {
    "path": "package/network/utils/rssileds/files/rssileds.init",
    "content": "#!/bin/sh /etc/rc.common\n# (C) 2012 Daniel Golle, Allnet GmbH <dgolle@allnet.de>\n\nSTART=96\nSTOP=89\nRSSILEDS_BIN=\"/usr/sbin/rssileds\"\n\nSERVICE_DAEMONIZE=1\nSERVICE_WRITE_PID=1\n\nstart_rssid() {\n\tlocal name\n\tlocal dev\n\tlocal threshold\n\tlocal refresh\n\tlocal leds\n\tconfig_get name $1 name\n\tconfig_get dev $1 dev\n\tconfig_get threshold $1 threshold\n\tconfig_get refresh $1 refresh\n\tleds=\"$( cur_iface=$1 ; config_foreach get_led led )\"\n\tSERVICE_PID_FILE=/var/run/rssileds-$dev.pid\n\tservice_start $RSSILEDS_BIN $dev $refresh $threshold $leds\n}\n\nstop_rssid() {\n\tlocal dev\n\tconfig_get dev $1 dev\n\tSERVICE_PID_FILE=/var/run/rssileds-$dev.pid\n\tservice_stop $RSSILEDS_BIN\n}\n\nget_led() {\n\tlocal name\n\tlocal sysfs\n\tlocal trigger\n\tlocal iface\n\tconfig_get sysfs $1 sysfs\n\tconfig_get name $1 name \"$sysfs\"\n\tconfig_get trigger $1 trigger \"none\"\n\tconfig_get iface $1 iface\n\tconfig_get minq $1 minq\n\tconfig_get maxq $1 maxq\n\tconfig_get offset $1 offset\n\tconfig_get factor $1 factor\n\t[ \"$trigger\" = \"rssi\" ] || return\n\t[ \"$iface\" = \"$cur_iface\" ] || return\n\t[ ! \"$minq\" ] || [ ! \"$maxq\" ] || [ ! \"$offset\" ] || [ ! \"$factor\" ] && return\n\techo \"none\" > /sys/class/leds/$sysfs/trigger\n\techo \"$sysfs $minq $maxq $offset $factor\"\n}\n\noff_led() {\n\tlocal name\n\tlocal sysfs\n\tlocal trigger\n\tconfig_get sysfs $1 sysfs\n\tconfig_get name $1 name \"$sysfs\"\n\tconfig_get trigger $1 trigger \"none\"\n\t[ \"$trigger\" = \"rssi\" ] || return\n\techo \"0\" > /sys/class/leds/$sysfs/brightness\n}\n\nstart() {\n\t[ -e /sys/class/leds/ ] && [ -x \"$RSSILEDS_BIN\" ] && {\n\t\tconfig_load system\n\t\tconfig_foreach start_rssid rssid\n\t}\n}\n\nstop() {\n\tconfig_load system\n\tconfig_foreach stop_rssid rssid\n\tconfig_foreach off_led led\n}\n"
  },
  {
    "path": "package/network/utils/rssileds/src/rssileds.c",
    "content": "/*\n * configurable RSSI LED control daemon for OpenWrt\n *  (c) 2012 Allnet GmbH, Daniel Golle <dgolle@allnet.de>\n *\n * This program is free software; you can redistribute it and/or modify\n * it under the terms of the GNU General Public License as published by\n * the Free Software Foundation; either version 2 of the License, or\n * (at your option) any later version.\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU\n * General Public License for more details.\n *\n * You should have received a copy of the GNU General Public License\n * along with this program; if not, write to the Free Software\n * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\n *\n * The author may be reached as dgolle@allnet.de, or\n * ALLNET GmbH\n * Maistr. 2\n * D-82110 Germering\n * Germany\n *\n */\n\n#include <stdio.h>\n#include <stdlib.h>\n#include <sys/stat.h>\n#include <fcntl.h>\n#include <signal.h>\n#include <unistd.h>\n#include <syslog.h>\n\n#include \"iwinfo.h\"\n\n#define RUN_DIR\t\t\t\"/var/run\"\n#define LEDS_BASEPATH\t\t\"/sys/class/leds/\"\n#define BACKEND_RETRY_DELAY\t500000\n\nchar *ifname;\nint qual_max;\n\nstruct led {\n\tchar *sysfspath;\n\tFILE *controlfd;\n\tunsigned char state;\n};\n\ntypedef struct rule rule_t;\nstruct rule {\n\tstruct led *led;\n\tint minq;\n\tint maxq;\n\tint boffset;\n\tint bfactor;\n\trule_t *next;\n};\n\nvoid log_rules(rule_t *rules)\n{\n\trule_t *rule = rules;\n\twhile (rule)\n\t{\n\t\tsyslog(LOG_INFO, \" %s r: %d..%d, o: %d, f: %d\\n\",\n\t\t\trule->led->sysfspath,\n\t\t\trule->minq, rule->maxq,\n\t\t\trule->boffset, rule->bfactor);\n\t\trule = rule->next;\n\t}\n}\n\nint set_led(struct led *led, unsigned char value)\n{\n\tchar buf[8];\n\n\tif ( ! led )\n\t\treturn -1;\n\n\tif ( ! led->controlfd )\n\t\treturn -1;\n\n\tif ( led->state == value )\n\t\treturn 0;\n\n\tsnprintf(buf, 8, \"%d\", value);\n\n\trewind(led->controlfd);\n\n\tif ( ! fwrite(buf, sizeof(char), strlen(buf), led->controlfd) )\n\t\treturn -2;\n\n\tfflush(led->controlfd);\n\tled->state=value;\n\n\treturn 0;\n}\n\nint init_led(struct led **led, char *ledname)\n{\n\tstruct led *newled;\n\tstruct stat statbuffer;\n\tint status;\n\tchar *bp;\n\tFILE *bfp;\n\n\tbp = calloc(sizeof(char), strlen(ledname) + strlen(LEDS_BASEPATH) + 12);\n\tif ( ! bp )\n\t\tgoto return_error;\n\n\tsprintf(bp, \"%s%s/brightness\", LEDS_BASEPATH, ledname);\n\n\tstatus = stat(bp, &statbuffer);\n\tif ( status )\n\t\tgoto cleanup_fname;\n\n\tbfp = fopen( bp, \"w\" );\n\tif ( !bfp )\n\t\tgoto cleanup_fname;\n\n\tif ( ferror(bfp) )\n\t\tgoto cleanup_fp;\n\n\t/* sysfs path exists and, allocate LED struct */\n\tnewled = calloc(sizeof(struct led),1);\n\tif ( !newled )\n\t\tgoto cleanup_fp;\n\n\tnewled->sysfspath = bp;\n\tnewled->controlfd = bfp;\n\n\t*led = newled;\n\n\tif ( set_led(newled, 255) )\n\t\tgoto cleanup_fp;\n\n\tif ( set_led(newled, 0) )\n\t\tgoto cleanup_fp;\n\n\treturn 0;\n\ncleanup_fp:\n\tfclose(bfp);\ncleanup_fname:\n\tfree(bp);\nreturn_error:\n\tsyslog(LOG_CRIT, \"can't open LED %s\\n\", ledname);\n\t*led = NULL;\n\treturn -1;\n}\n\nvoid close_led(struct led **led)\n{\n\tfclose((*led)->controlfd);\n\tfree((*led)->sysfspath);\n\tfree((*led));\n\t(*led)=NULL;\n}\n\n\nint quality(const struct iwinfo_ops *iw, const char *ifname)\n{\n\tint qual;\n\n\tif ( ! iw ) return -1;\n\n\tif (qual_max < 1)\n\t\tif (iw->quality_max(ifname, &qual_max))\n\t\t\treturn -1;\n\n\tif (iw->quality(ifname, &qual))\n\t\treturn -1;\n\n\treturn ( qual * 100 ) / qual_max ;\n}\n\nint open_backend(const struct iwinfo_ops **iw, const char *ifname)\n{\n\t*iw = iwinfo_backend(ifname);\n\n\tif (!(*iw))\n\t\treturn 1;\n\n\treturn 0;\n}\n\nvoid update_leds(rule_t *rules, int q)\n{\n\trule_t *rule = rules;\n\twhile (rule)\n\t{\n\t\tint b;\n\t\t/* offset and factore correction according to rule */\n\t\tb = ( q + rule->boffset ) * rule->bfactor;\n\t\tif ( b < 0 )\n\t\t\tb=0;\n\t\tif ( b > 255 )\n\t\t\tb=255;\n\n\t\tif ( q >= rule->minq && q <= rule->maxq )\n\t\t\tset_led(rule->led, (unsigned char)b);\n\t\telse\n\t\t\tset_led(rule->led, 0);\n\n\t\trule = rule->next;\n\t}\n}\n\nint main(int argc, char **argv)\n{\n\tint i,q,q0,r,s;\n\tconst struct iwinfo_ops *iw = NULL;\n\trule_t *headrule = NULL, *currentrule = NULL;\n\n\tif (argc < 9 || ( (argc-4) % 5 != 0 ) )\n\t{\n\t\tprintf(\"syntax: %s (ifname) (refresh) (threshold) (rule) [rule] ...\\n\", argv[0]);\n\t\tprintf(\"  rule: (sysfs-name) (minq) (maxq) (offset) (factore)\\n\");\n\t\treturn 1;\n\t}\n\n\tifname = argv[1];\n\n\t/* refresh interval */\n\tif ( sscanf(argv[2], \"%d\", &r) != 1 )\n\t\treturn 1;\n\n\t/* sustain threshold */\n\tif ( sscanf(argv[3], \"%d\", &s) != 1 )\n\t\treturn 1;\n\n\topenlog(\"rssileds\", LOG_PID, LOG_DAEMON);\n\tsyslog(LOG_INFO, \"monitoring %s, refresh rate %d, threshold %d\\n\", ifname, r, s);\n\n\tcurrentrule = headrule;\n\tfor (i=4; i<argc; i=i+5) {\n\t\tif (! currentrule)\n\t\t{\n\t\t\t/* first element in the list */\n\t\t\tcurrentrule = calloc(sizeof(rule_t),1);\n\t\t\theadrule = currentrule;\n\t\t}\n\t\telse\n\t\t{\n\t\t\t/* follow-up element */\n\t\t\tcurrentrule->next = calloc(sizeof(rule_t),1);\n\t\t\tcurrentrule = currentrule->next;\n\t\t}\n\n\t\tif ( init_led(&(currentrule->led), argv[i]) )\n\t\t\treturn 1;\n\t\t\n\t\tif ( sscanf(argv[i+1], \"%d\", &(currentrule->minq)) != 1 )\n\t\t\treturn 1;\n\n\t\tif ( sscanf(argv[i+2], \"%d\", &(currentrule->maxq)) != 1 )\n\t\t\treturn 1;\n\t\t\n\t\tif ( sscanf(argv[i+3], \"%d\", &(currentrule->boffset)) != 1 )\n\t\t\treturn 1;\n\t\t\n\t\tif ( sscanf(argv[i+4], \"%d\", &(currentrule->bfactor)) != 1 )\n\t\t\treturn 1;\n\t}\n\tlog_rules(headrule);\n\n\tq0 = -1;\n\tdo {\n\t\tq = quality(iw, ifname);\n\t\tif ( q < q0 - s || q > q0 + s ) {\n\t\t\tupdate_leds(headrule, q);\n\t\t\tq0=q;\n\t\t};\n\t\t// re-open backend...\n\t\tif ( q == -1 && q0 == -1 ) {\n\t\t\tif (iw) {\n\t\t\t\tiwinfo_finish();\n\t\t\t\tiw=NULL;\n\t\t\t\tusleep(BACKEND_RETRY_DELAY);\n\t\t\t}\n\t\t\twhile (open_backend(&iw, ifname))\n\t\t\t\tusleep(BACKEND_RETRY_DELAY);\n\t\t}\n\t\tusleep(r);\n\t} while(1);\n\n\tiwinfo_finish();\n\n\treturn 0;\n}\n"
  },
  {
    "path": "package/network/utils/tcpdump/Makefile",
    "content": "#\n# Copyright (C) 2007-2011 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=tcpdump\nPKG_VERSION:=4.9.3\nPKG_RELEASE:=4\n\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz\nPKG_SOURCE_URL:=http://www.tcpdump.org/release/\nPKG_HASH:=2cd47cb3d460b6ff75f4a9940f594317ad456cfbf2bd2c8e5151e16559db6410\n\nPKG_MAINTAINER:=Felix Fietkau <nbd@nbd.name>\nPKG_LICENSE:=BSD-3-Clause\nPKG_CPE_ID:=cpe:/a:tcpdump:tcpdump\n\nPKG_INSTALL:=1\nPKG_BUILD_PARALLEL:=1\n\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine Package/tcpdump/default\n  SECTION:=net\n  CATEGORY:=Network\n  DEPENDS:=+libpcap\n  TITLE:=Network monitoring and data acquisition tool\n  URL:=http://www.tcpdump.org/\nendef\n\ndefine Package/tcpdump\n  $(Package/tcpdump/default)\n  VARIANT:=full\nendef\n\ndefine Package/tcpdump-mini\n  $(Package/tcpdump/default)\n  TITLE+= (minimal version)\n  VARIANT:=mini\nendef\n\nCONFIGURE_ARGS += \\\n\t--without-cap-ng \\\n\t--without-crypto \\\n\t$(call autoconf_bool,CONFIG_IPV6,ipv6)\n\nTARGET_CFLAGS += -ffunction-sections -fdata-sections\nTARGET_LDFLAGS += -Wl,--gc-sections\n\nifeq ($(BUILD_VARIANT),mini)\n  TARGET_CFLAGS += -DTCPDUMP_MINI\n  CONFIGURE_ARGS += --disable-smb\n  MAKE_FLAGS += TCPDUMP_MINI=1\nendif\n\ndefine Package/tcpdump/install\n\t$(INSTALL_DIR) $(1)/usr/sbin\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/sbin/tcpdump $(1)/usr/sbin/\nendef\n\nPackage/tcpdump-mini/install = $(Package/tcpdump/install)\n\n$(eval $(call BuildPackage,tcpdump))\n$(eval $(call BuildPackage,tcpdump-mini))\n"
  },
  {
    "path": "package/network/utils/tcpdump/patches/001-remove_pcap_debug.patch",
    "content": "--- a/configure\n+++ b/configure\n@@ -6183,97 +6183,6 @@ $as_echo \"no\" >&6; }\n     fi\n fi\n \n-#\n-# Check for special debugging functions\n-#\n-for ac_func in pcap_set_parser_debug\n-do :\n-  ac_fn_c_check_func \"$LINENO\" \"pcap_set_parser_debug\" \"ac_cv_func_pcap_set_parser_debug\"\n-if test \"x$ac_cv_func_pcap_set_parser_debug\" = xyes; then :\n-  cat >>confdefs.h <<_ACEOF\n-#define HAVE_PCAP_SET_PARSER_DEBUG 1\n-_ACEOF\n-\n-fi\n-done\n-\n-if test \"$ac_cv_func_pcap_set_parser_debug\" = \"no\" ; then\n-\t#\n-\t# OK, we don't have pcap_set_parser_debug() to set the libpcap\n-\t# filter expression parser debug flag; can we directly set the\n-\t# flag?\n-\t{ $as_echo \"$as_me:${as_lineno-$LINENO}: checking whether pcap_debug is defined by libpcap\" >&5\n-$as_echo_n \"checking whether pcap_debug is defined by libpcap... \" >&6; }\n-\tcat confdefs.h - <<_ACEOF >conftest.$ac_ext\n-/* end confdefs.h.  */\n-\n-int\n-main ()\n-{\n-\n-\t\textern int pcap_debug;\n-\n-\t\treturn pcap_debug;\n-\n-  ;\n-  return 0;\n-}\n-_ACEOF\n-if ac_fn_c_try_link \"$LINENO\"; then :\n-  ac_lbl_cv_pcap_debug_defined=yes\n-else\n-  ac_lbl_cv_pcap_debug_defined=no\n-fi\n-rm -f core conftest.err conftest.$ac_objext \\\n-    conftest$ac_exeext conftest.$ac_ext\n-\tif test \"$ac_lbl_cv_pcap_debug_defined\" = yes ; then\n-\t\t{ $as_echo \"$as_me:${as_lineno-$LINENO}: result: yes\" >&5\n-$as_echo \"yes\" >&6; }\n-\n-$as_echo \"#define HAVE_PCAP_DEBUG 1\" >>confdefs.h\n-\n-\telse\n-\t\t{ $as_echo \"$as_me:${as_lineno-$LINENO}: result: no\" >&5\n-$as_echo \"no\" >&6; }\n-\t\t#\n-\t\t# OK, what about \"yydebug\"?\n-\t\t#\n-\t\t{ $as_echo \"$as_me:${as_lineno-$LINENO}: checking whether yydebug is defined by libpcap\" >&5\n-$as_echo_n \"checking whether yydebug is defined by libpcap... \" >&6; }\n-\t\tcat confdefs.h - <<_ACEOF >conftest.$ac_ext\n-/* end confdefs.h.  */\n-\n-int\n-main ()\n-{\n-\n-\t\t\textern int yydebug;\n-\n-\t\t\treturn yydebug;\n-\n-  ;\n-  return 0;\n-}\n-_ACEOF\n-if ac_fn_c_try_link \"$LINENO\"; then :\n-  ac_lbl_cv_yydebug_defined=yes\n-else\n-  ac_lbl_cv_yydebug_defined=no\n-fi\n-rm -f core conftest.err conftest.$ac_objext \\\n-    conftest$ac_exeext conftest.$ac_ext\n-\t\tif test \"$ac_lbl_cv_yydebug_defined\" = yes ; then\n-\t\t\t{ $as_echo \"$as_me:${as_lineno-$LINENO}: result: yes\" >&5\n-$as_echo \"yes\" >&6; }\n-\n-$as_echo \"#define HAVE_YYDEBUG 1\" >>confdefs.h\n-\n-\t\telse\n-\t\t\t{ $as_echo \"$as_me:${as_lineno-$LINENO}: result: no\" >&5\n-$as_echo \"no\" >&6; }\n-\t\tfi\n-\tfi\n-fi\n for ac_func in pcap_set_optimizer_debug\n do :\n   ac_fn_c_check_func \"$LINENO\" \"pcap_set_optimizer_debug\" \"ac_cv_func_pcap_set_optimizer_debug\"\n"
  },
  {
    "path": "package/network/utils/tcpdump/patches/100-tcpdump_mini.patch",
    "content": "--- a/Makefile.in\n+++ b/Makefile.in\n@@ -72,6 +72,80 @@ DEPENDENCY_CFLAG = @DEPENDENCY_CFLAG@\n \n CSRC =\tsetsignal.c tcpdump.c\n \n+ifdef TCPDUMP_MINI\n+\n+LIBNETDISSECT_SRC=\\\n+\tnetdissect.c \\\n+\taddrtoname.c \\\n+\taddrtostr.c \\\n+\taf.c \\\n+\tascii_strcasecmp.c \\\n+\tchecksum.c \\\n+\tcpack.c \\\n+\tgmpls.c \\\n+\tgmt2local.c \\\n+\tin_cksum.c \\\n+\tipproto.c \\\n+\tl2vpn.c \\\n+\tmachdep.c \\\n+\tnlpid.c \\\n+\toui.c \\\n+\tparsenfsfh.c \\\n+\tprint.c \\\n+\tprint-802_11.c \\\n+\tprint-aodv.c \\\n+\tprint-arp.c \\\n+\tprint-ascii.c \\\n+\tprint-bootp.c \\\n+\tprint-dhcp6.c \\\n+\tprint-domain.c \\\n+\tprint-eap.c \\\n+\tprint-ether.c \\\n+\tprint-ftp.c \\\n+\tprint-gre.c \\\n+\tprint-http.c \\\n+\tprint-icmp.c \\\n+\tprint-icmp6.c \\\n+\tprint-igmp.c \\\n+\tprint-ip.c \\\n+\tprint-ip6.c \\\n+\tprint-ip6opts.c \\\n+\tprint-ipnet.c \\\n+\tprint-l2tp.c \\\n+\tprint-llc.c \\\n+\tprint-lldp.c \\\n+\tprint-loopback.c \\\n+\tprint-nfs.c \\\n+\tprint-ntp.c \\\n+\tprint-null.c \\\n+\tprint-olsr.c \\\n+\tprint-ospf.c \\\n+\tprint-ospf6.c \\\n+\tprint-ppp.c \\\n+\tprint-pppoe.c \\\n+\tprint-pptp.c \\\n+\tprint-radius.c \\\n+\tprint-raw.c \\\n+\tprint-rsvp.c \\\n+\tprint-rt6.c \\\n+\tprint-rtsp.c \\\n+\tprint-sip.c \\\n+\tprint-sll.c \\\n+\tprint-smtp.c \\\n+\tprint-snmp.c \\\n+\tprint-stp.c \\\n+\tprint-sunrpc.c \\\n+\tprint-syslog.c \\\n+\tprint-tcp.c \\\n+\tprint-telnet.c \\\n+\tprint-tftp.c \\\n+\tprint-udp.c \\\n+\tsignature.c \\\n+\tstrtoaddr.c \\\n+\tutil-print.c\n+\n+else\n+\n LIBNETDISSECT_SRC=\\\n \taddrtoname.c \\\n \taddrtostr.c \\\n@@ -237,6 +311,8 @@ LIBNETDISSECT_SRC=\\\n \tstrtoaddr.c \\\n \tutil-print.c\n \n+endif\n+\n LOCALSRC = @LOCALSRC@\n GENSRC = version.c\n LIBOBJS = @LIBOBJS@\n--- a/addrtoname.c\n+++ b/addrtoname.c\n@@ -578,8 +578,10 @@ linkaddr_string(netdissect_options *ndo,\n \tif (type == LINKADDR_ETHER && len == ETHER_ADDR_LEN)\n \t\treturn (etheraddr_string(ndo, ep));\n \n+#ifndef TCPDUMP_MINI\n \tif (type == LINKADDR_FRELAY)\n \t\treturn (q922_string(ndo, ep, len));\n+#endif\n \n \ttp = lookup_bytestring(ndo, ep, len);\n \tif (tp->bs_name)\n@@ -1214,6 +1216,7 @@ init_addrtoname(netdissect_options *ndo,\n \tinit_ipxsaparray(ndo);\n }\n \n+#ifndef TCPDUMP_MINI\n const char *\n dnaddr_string(netdissect_options *ndo, u_short dnaddr)\n {\n@@ -1230,6 +1233,7 @@ dnaddr_string(netdissect_options *ndo, u\n \n \treturn(tp->name);\n }\n+#endif\n \n /* Return a zero'ed hnamemem struct and cuts down on calloc() overhead */\n struct hnamemem *\n--- a/print.c\n+++ b/print.c\n@@ -48,6 +48,7 @@ static const struct printer printers[] =\n #ifdef DLT_IPNET\n \t{ ipnet_if_print,\tDLT_IPNET },\n #endif\n+#ifndef TCPDUMP_MINI\n #ifdef DLT_IEEE802_15_4\n \t{ ieee802_15_4_if_print, DLT_IEEE802_15_4 },\n #endif\n@@ -57,12 +58,14 @@ static const struct printer printers[] =\n #ifdef DLT_PPI\n \t{ ppi_if_print,\t\tDLT_PPI },\n #endif\n+#endif\n #ifdef DLT_NETANALYZER\n \t{ netanalyzer_if_print, DLT_NETANALYZER },\n #endif\n #ifdef DLT_NETANALYZER_TRANSPARENT\n \t{ netanalyzer_transparent_if_print, DLT_NETANALYZER_TRANSPARENT },\n #endif\n+#ifndef TCPDUMP_MINI\n #if defined(DLT_NFLOG) && defined(HAVE_PCAP_NFLOG_H)\n \t{ nflog_if_print,\tDLT_NFLOG},\n #endif\n@@ -75,10 +78,12 @@ static const struct printer printers[] =\n #ifdef DLT_IP_OVER_FC\n \t{ ipfc_if_print,\tDLT_IP_OVER_FC },\n #endif\n+#endif\n \t{ null_if_print,\tDLT_NULL },\n #ifdef DLT_LOOP\n \t{ null_if_print,\tDLT_LOOP },\n #endif\n+#ifndef TCPDUMP_MINI\n #ifdef DLT_APPLE_IP_OVER_IEEE1394\n \t{ ap1394_if_print,\tDLT_APPLE_IP_OVER_IEEE1394 },\n #endif\n@@ -92,7 +97,9 @@ static const struct printer printers[] =\n #ifdef DLT_ARCNET_LINUX\n \t{ arcnet_linux_if_print, DLT_ARCNET_LINUX },\n #endif\n+#endif\n \t{ raw_if_print,\t\tDLT_RAW },\n+#ifndef TCPDUMP_MINI\n #ifdef DLT_IPV4\n \t{ raw_if_print,\t\tDLT_IPV4 },\n #endif\n@@ -116,17 +123,21 @@ static const struct printer printers[] =\n #ifdef DLT_HDLC\n \t{ chdlc_if_print,\tDLT_HDLC },\n #endif\n+#endif\n #ifdef DLT_PPP_ETHER\n \t{ pppoe_if_print,\tDLT_PPP_ETHER },\n #endif\n+#ifndef TCPDUMP_MINI\n #if defined(DLT_PFLOG) && defined(HAVE_NET_IF_PFLOG_H)\n \t{ pflog_if_print,\tDLT_PFLOG },\n #endif\n \t{ token_if_print,\tDLT_IEEE802 },\n \t{ fddi_if_print,\tDLT_FDDI },\n+#endif\n #ifdef DLT_LINUX_SLL\n \t{ sll_if_print,\t\tDLT_LINUX_SLL },\n #endif\n+#ifndef TCPDUMP_MINI\n #ifdef DLT_FR\n \t{ fr_if_print,\t\tDLT_FR },\n #endif\n@@ -198,6 +209,7 @@ static const struct printer printers[] =\n #ifdef DLT_PKTAP\n \t{ pktap_if_print,\tDLT_PKTAP },\n #endif\n+#endif\n #ifdef DLT_IEEE802_11_RADIO\n \t{ ieee802_11_radio_if_print,\tDLT_IEEE802_11_RADIO },\n #endif\n@@ -214,12 +226,14 @@ static const struct printer printers[] =\n #ifdef DLT_PPP_WITHDIRECTION\n \t{ ppp_if_print,\t\tDLT_PPP_WITHDIRECTION },\n #endif\n+#ifndef TCPDUMP_MINI\n #ifdef DLT_PPP_BSDOS\n \t{ ppp_bsdos_if_print,\tDLT_PPP_BSDOS },\n #endif\n #ifdef DLT_PPP_SERIAL\n \t{ ppp_hdlc_if_print,\tDLT_PPP_SERIAL },\n #endif\n+#endif\n \t{ NULL,\t\t\t0 },\n };\n \n--- a/print-ether.c\n+++ b/print-ether.c\n@@ -342,6 +342,7 @@ ethertype_print(netdissect_options *ndo,\n \t        arp_print(ndo, p, length, caplen);\n \t\treturn (1);\n \n+#ifndef TCPDUMP_MINI\n \tcase ETHERTYPE_DN:\n \t\tdecnet_print(ndo, p, length, caplen);\n \t\treturn (1);\n@@ -368,6 +369,7 @@ ethertype_print(netdissect_options *ndo,\n \t\t}\n \t\tisoclns_print(ndo, p + 1, length - 1);\n \t\treturn(1);\n+#endif\n \n \tcase ETHERTYPE_PPPOED:\n \tcase ETHERTYPE_PPPOES:\n@@ -380,9 +382,11 @@ ethertype_print(netdissect_options *ndo,\n \t        eap_print(ndo, p, length);\n \t\treturn (1);\n \n+#ifndef TCPDUMP_MINI\n \tcase ETHERTYPE_RRCP:\n \t        rrcp_print(ndo, p, length, src, dst);\n \t\treturn (1);\n+#endif\n \n \tcase ETHERTYPE_PPP:\n \t\tif (length) {\n@@ -391,6 +395,7 @@ ethertype_print(netdissect_options *ndo,\n \t\t}\n \t\treturn (1);\n \n+#ifndef TCPDUMP_MINI\n \tcase ETHERTYPE_MPCP:\n \t        mpcp_print(ndo, p, length);\n \t\treturn (1);\n@@ -403,6 +408,7 @@ ethertype_print(netdissect_options *ndo,\n \tcase ETHERTYPE_CFM_OLD:\n \t\tcfm_print(ndo, p, length);\n \t\treturn (1);\n+#endif\n \n \tcase ETHERTYPE_LLDP:\n \t\tlldp_print(ndo, p, length);\n@@ -412,6 +418,7 @@ ethertype_print(netdissect_options *ndo,\n \t\tloopback_print(ndo, p, length);\n                 return (1);\n \n+#ifndef TCPDUMP_MINI\n \tcase ETHERTYPE_MPLS:\n \tcase ETHERTYPE_MPLS_MULTI:\n \t\tmpls_print(ndo, p, length);\n@@ -441,6 +448,7 @@ ethertype_print(netdissect_options *ndo,\n \tcase ETHERTYPE_MEDSA:\n \t\tmedsa_print(ndo, p, length, caplen, src, dst);\n \t\treturn (1);\n+#endif\n \n \tcase ETHERTYPE_LAT:\n \tcase ETHERTYPE_SCA:\n--- a/print-gre.c\n+++ b/print-gre.c\n@@ -216,6 +216,7 @@ gre_print_0(netdissect_options *ndo, con\n \tcase ETHERTYPE_IPV6:\n \t\tip6_print(ndo, bp, len);\n \t\tbreak;\n+#ifndef TCPDUMP_MINI\n \tcase ETHERTYPE_MPLS:\n \t\tmpls_print(ndo, bp, len);\n \t\tbreak;\n@@ -231,6 +232,7 @@ gre_print_0(netdissect_options *ndo, con\n \tcase ETHERTYPE_TEB:\n \t\tether_print(ndo, bp, len, ndo->ndo_snapend - bp, NULL, NULL);\n \t\tbreak;\n+#endif\n \tdefault:\n \t\tND_PRINT((ndo, \"gre-proto-0x%x\", prot));\n \t}\n--- a/print-igmp.c\n+++ b/print-igmp.c\n@@ -306,6 +306,7 @@ igmp_print(netdissect_options *ndo,\n         ND_TCHECK2(bp[4], 4);\n         ND_PRINT((ndo, \"igmp leave %s\", ipaddr_string(ndo, &bp[4])));\n         break;\n+#ifndef TCPDUMP_MINI\n     case 0x13:\n         ND_PRINT((ndo, \"igmp dvmrp\"));\n         if (len < 8)\n@@ -317,6 +318,7 @@ igmp_print(netdissect_options *ndo,\n         ND_PRINT((ndo, \"igmp pimv1\"));\n         pimv1_print(ndo, bp, len);\n         break;\n+#endif\n     case 0x1e:\n         print_mresp(ndo, bp, len);\n         break;\n--- a/print-ip6.c\n+++ b/print-ip6.c\n@@ -305,6 +305,7 @@ ip6_print(netdissect_options *ndo, const\n \t\t\t\treturn;\n \t\t\tnh = *cp;\n \t\t\tbreak;\n+#ifndef TCPDUMP_MINI\n \t\tcase IPPROTO_FRAGMENT:\n \t\t\tadvance = frag6_print(ndo, cp, (const u_char *)ip6);\n \t\t\tif (advance < 0 || ndo->ndo_snapend <= cp + advance)\n@@ -328,6 +329,7 @@ ip6_print(netdissect_options *ndo, const\n \t\t\t\treturn;\n \t\t\tnh = *cp;\n \t\t\treturn;\n+#endif\n \t\tcase IPPROTO_ROUTING:\n \t\t\tND_TCHECK(*cp);\n \t\t\tadvance = rt6_print(ndo, cp, (const u_char *)ip6);\n@@ -335,12 +337,14 @@ ip6_print(netdissect_options *ndo, const\n \t\t\t\treturn;\n \t\t\tnh = *cp;\n \t\t\tbreak;\n+#ifndef TCPDUMP_MINI\n \t\tcase IPPROTO_SCTP:\n \t\t\tsctp_print(ndo, cp, (const u_char *)ip6, len);\n \t\t\treturn;\n \t\tcase IPPROTO_DCCP:\n \t\t\tdccp_print(ndo, cp, (const u_char *)ip6, len);\n \t\t\treturn;\n+#endif\n \t\tcase IPPROTO_TCP:\n \t\t\ttcp_print(ndo, cp, len, (const u_char *)ip6, fragmented);\n \t\t\treturn;\n@@ -350,6 +354,7 @@ ip6_print(netdissect_options *ndo, const\n \t\tcase IPPROTO_ICMPV6:\n \t\t\ticmp6_print(ndo, cp, len, (const u_char *)ip6, fragmented);\n \t\t\treturn;\n+#ifndef TCPDUMP_MINI\n \t\tcase IPPROTO_AH:\n \t\t\tadvance = ah_print(ndo, cp);\n \t\t\tif (advance < 0)\n@@ -382,6 +387,7 @@ ip6_print(netdissect_options *ndo, const\n \t\tcase IPPROTO_PIM:\n \t\t\tpim_print(ndo, cp, len, (const u_char *)ip6);\n \t\t\treturn;\n+#endif\n \n \t\tcase IPPROTO_OSPF:\n \t\t\tospf6_print(ndo, cp, len);\n@@ -395,9 +401,11 @@ ip6_print(netdissect_options *ndo, const\n \t\t        ip_print(ndo, cp, len);\n \t\t\treturn;\n \n+#ifndef TCPDUMP_MINI\n                 case IPPROTO_PGM:\n                         pgm_print(ndo, cp, len, (const u_char *)ip6);\n                         return;\n+#endif\n \n \t\tcase IPPROTO_GRE:\n \t\t\tgre_print(ndo, cp, len);\n--- a/print-ip.c\n+++ b/print-ip.c\n@@ -344,6 +344,7 @@ ip_print_demux(netdissect_options *ndo,\n again:\n \tswitch (ipds->nh) {\n \n+#ifndef TCPDUMP_MINI\n \tcase IPPROTO_AH:\n \t\tif (!ND_TTEST(*ipds->cp)) {\n \t\t\tND_PRINT((ndo, \"[|AH]\"));\n@@ -382,7 +383,9 @@ again:\n \t\t */\n \t\tbreak;\n \t}\n+#endif\n \n+#ifndef TCPDUMP_MINI\n \tcase IPPROTO_SCTP:\n \t\tsctp_print(ndo, ipds->cp, (const u_char *)ipds->ip, ipds->len);\n \t\tbreak;\n@@ -390,6 +393,7 @@ again:\n \tcase IPPROTO_DCCP:\n \t\tdccp_print(ndo, ipds->cp, (const u_char *)ipds->ip, ipds->len);\n \t\tbreak;\n+#endif\n \n \tcase IPPROTO_TCP:\n \t\t/* pass on the MF bit plus the offset to detect fragments */\n@@ -409,6 +413,7 @@ again:\n \t\t\t   ipds->off & (IP_MF|IP_OFFMASK));\n \t\tbreak;\n \n+#ifndef TCPDUMP_MINI\n \tcase IPPROTO_PIGP:\n \t\t/*\n \t\t * XXX - the current IANA protocol number assignments\n@@ -429,14 +434,17 @@ again:\n \tcase IPPROTO_EIGRP:\n \t\teigrp_print(ndo, ipds->cp, ipds->len);\n \t\tbreak;\n+#endif\n \n \tcase IPPROTO_ND:\n \t\tND_PRINT((ndo, \" nd %d\", ipds->len));\n \t\tbreak;\n \n+#ifndef TCPDUMP_MINI\n \tcase IPPROTO_EGP:\n \t\tegp_print(ndo, ipds->cp, ipds->len);\n \t\tbreak;\n+#endif\n \n \tcase IPPROTO_OSPF:\n \t\tospf_print(ndo, ipds->cp, ipds->len, (const u_char *)ipds->ip);\n@@ -469,6 +477,7 @@ again:\n \t\tgre_print(ndo, ipds->cp, ipds->len);\n \t\tbreak;\n \n+#ifndef TCPDUMP_MINI\n \tcase IPPROTO_MOBILE:\n \t\tmobile_print(ndo, ipds->cp, ipds->len);\n \t\tbreak;\n@@ -497,6 +506,7 @@ again:\n \tcase IPPROTO_PGM:\n \t\tpgm_print(ndo, ipds->cp, ipds->len, (const u_char *)ipds->ip);\n \t\tbreak;\n+#endif\n \n \tdefault:\n \t\tif (ndo->ndo_nflag==0 && (p_name = netdb_protoname(ipds->nh)) != NULL)\n--- a/print-llc.c\n+++ b/print-llc.c\n@@ -206,6 +206,7 @@ llc_print(netdissect_options *ndo, const\n \t\thdrlen = 4;\t/* DSAP, SSAP, 2-byte control field */\n \t}\n \n+#ifndef TCPDUMP_MINI\n \tif (ssap_field == LLCSAP_GLOBAL && dsap_field == LLCSAP_GLOBAL) {\n \t\t/*\n \t\t * This is an Ethernet_802.3 IPX frame; it has an\n@@ -228,6 +229,7 @@ llc_print(netdissect_options *ndo, const\n             ipx_print(ndo, p, length);\n             return (0);\t\t/* no LLC header */\n \t}\n+#endif\n \n \tdsap = dsap_field & ~LLC_IG;\n \tssap = ssap_field & ~LLC_GSAP;\n@@ -291,6 +293,7 @@ llc_print(netdissect_options *ndo, const\n \t\treturn (hdrlen);\n \t}\n \n+#ifndef TCPDUMP_MINI\n \tif (ssap == LLCSAP_IPX && dsap == LLCSAP_IPX &&\n \t    control == LLC_UI) {\n \t\t/*\n@@ -304,6 +307,7 @@ llc_print(netdissect_options *ndo, const\n \t\tipx_print(ndo, p, length);\n \t\treturn (hdrlen);\n \t}\n+#endif\n \n #ifdef ENABLE_SMB\n \tif (ssap == LLCSAP_NETBEUI && dsap == LLCSAP_NETBEUI\n@@ -322,12 +326,13 @@ llc_print(netdissect_options *ndo, const\n \t\treturn (hdrlen);\n \t}\n #endif\n+#ifndef TCPDUMP_MINI\n \tif (ssap == LLCSAP_ISONS && dsap == LLCSAP_ISONS\n \t    && control == LLC_UI) {\n \t\tisoclns_print(ndo, p, length);\n \t\treturn (hdrlen);\n \t}\n-\n+#endif\n \tif (!ndo->ndo_eflag) {\n \t\tif (ssap == dsap) {\n \t\t\tif (src == NULL || dst == NULL)\n@@ -480,6 +485,7 @@ snap_print(netdissect_options *ndo, cons\n \n \tcase OUI_CISCO:\n                 switch (et) {\n+#ifndef TCPDUMP_MINI\n                 case PID_CISCO_CDP:\n                         cdp_print(ndo, p, length, caplen);\n                         return (1);\n@@ -492,6 +498,7 @@ snap_print(netdissect_options *ndo, cons\n                 case PID_CISCO_VTP:\n                         vtp_print(ndo, p, length);\n                         return (1);\n+#endif\n                 case PID_CISCO_PVST:\n                 case PID_CISCO_VLANBRIDGE:\n                         stp_print(ndo, p, length);\n@@ -504,6 +511,7 @@ snap_print(netdissect_options *ndo, cons\n \tcase OUI_RFC2684:\n \t\tswitch (et) {\n \n+#ifndef TCPDUMP_MINI\n \t\tcase PID_RFC2684_ETH_FCS:\n \t\tcase PID_RFC2684_ETH_NOFCS:\n \t\t\t/*\n@@ -565,6 +573,7 @@ snap_print(netdissect_options *ndo, cons\n \t\t\t */\n \t\t\tfddi_print(ndo, p, length, caplen);\n \t\t\treturn (1);\n+#endif\n \n \t\tcase PID_RFC2684_BPDU:\n \t\t\tstp_print(ndo, p, length);\n--- a/print-null.c\n+++ b/print-null.c\n@@ -116,6 +116,7 @@ null_if_print(netdissect_options *ndo, c\n \t\tip6_print(ndo, p, length);\n \t\tbreak;\n \n+#ifndef TCPDUMP_MINI\n \tcase BSD_AFNUM_ISO:\n \t\tisoclns_print(ndo, p, length);\n \t\tbreak;\n@@ -127,6 +128,7 @@ null_if_print(netdissect_options *ndo, c\n \tcase BSD_AFNUM_IPX:\n \t\tipx_print(ndo, p, length);\n \t\tbreak;\n+#endif\n \n \tdefault:\n \t\t/* unknown AF_ value */\n--- a/print-ppp.c\n+++ b/print-ppp.c\n@@ -1367,6 +1367,7 @@ trunc:\n \treturn 0;\n }\n \n+#ifndef TCPDUMP_MINI\n static void\n ppp_hdlc(netdissect_options *ndo,\n          const u_char *p, int length)\n@@ -1445,6 +1446,7 @@ trunc:\n \tfree(b);\n \tND_PRINT((ndo, \"[|ppp]\"));\n }\n+#endif\n \n \n /* PPP */\n@@ -1452,10 +1454,12 @@ static void\n handle_ppp(netdissect_options *ndo,\n            u_int proto, const u_char *p, int length)\n {\n+#ifndef TCPDUMP_MINI\n \tif ((proto & 0xff00) == 0x7e00) { /* is this an escape code ? */\n \t\tppp_hdlc(ndo, p - 1, length);\n \t\treturn;\n \t}\n+#endif\n \n \tswitch (proto) {\n \tcase PPP_LCP: /* fall through */\n@@ -1488,6 +1492,7 @@ handle_ppp(netdissect_options *ndo,\n \tcase PPP_IPV6:\n \t\tip6_print(ndo, p, length);\n \t\tbreak;\n+#ifndef TCPDUMP_MINI\n \tcase ETHERTYPE_IPX:\t/*XXX*/\n \tcase PPP_IPX:\n \t\tipx_print(ndo, p, length);\n@@ -1499,6 +1504,7 @@ handle_ppp(netdissect_options *ndo,\n \tcase PPP_MPLS_MCAST:\n \t\tmpls_print(ndo, p, length);\n \t\tbreak;\n+#endif\n \tcase PPP_COMP:\n \t\tND_PRINT((ndo, \"compressed PPP data\"));\n \t\tbreak;\n@@ -1639,6 +1645,7 @@ ppp_if_print(netdissect_options *ndo,\n \treturn (0);\n }\n \n+#ifndef TCPDUMP_MINI\n /*\n  * PPP I/F printer to use if we know that RFC 1662-style PPP in HDLC-like\n  * framing, or Cisco PPP with HDLC framing as per section 4.3.1 of RFC 1547,\n@@ -1866,6 +1873,7 @@ printx:\n #endif /* __bsdi__ */\n \treturn (hdrlength);\n }\n+#endif\n \n \n /*\n--- a/print-sll.c\n+++ b/print-sll.c\n@@ -249,12 +249,14 @@ recurse:\n \t\t */\n \t\tswitch (ether_type) {\n \n+#ifndef TCPDUMP_MINI\n \t\tcase LINUX_SLL_P_802_3:\n \t\t\t/*\n \t\t\t * Ethernet_802.3 IPX frame.\n \t\t\t */\n \t\t\tipx_print(ndo, p, length);\n \t\t\tbreak;\n+#endif\n \n \t\tcase LINUX_SLL_P_802_2:\n \t\t\t/*\n--- a/print-tcp.c\n+++ b/print-tcp.c\n@@ -589,12 +589,14 @@ tcp_print(netdissect_options *ndo,\n                                 ND_PRINT((ndo, \" %u\", utoval));\n                                 break;\n \n+#ifndef TCPDUMP_MINI\n                         case TCPOPT_MPTCP:\n                                 datalen = len - 2;\n                                 LENCHECK(datalen);\n                                 if (!mptcp_print(ndo, cp-2, len, flags))\n                                         goto bad;\n                                 break;\n+#endif\n \n                         case TCPOPT_FASTOPEN:\n                                 datalen = len - 2;\n@@ -670,6 +672,7 @@ tcp_print(netdissect_options *ndo,\n                 return;\n         }\n \n+#ifndef TCPDUMP_MINI\n         if (ndo->ndo_packettype) {\n                 switch (ndo->ndo_packettype) {\n                 case PT_ZMTP1:\n@@ -681,28 +684,36 @@ tcp_print(netdissect_options *ndo,\n                 }\n                 return;\n         }\n+#endif\n \n         if (IS_SRC_OR_DST_PORT(TELNET_PORT)) {\n                 telnet_print(ndo, bp, length);\n         } else if (IS_SRC_OR_DST_PORT(SMTP_PORT)) {\n                 ND_PRINT((ndo, \": \"));\n                 smtp_print(ndo, bp, length);\n-        } else if (IS_SRC_OR_DST_PORT(BGP_PORT))\n+        }\n+#ifndef TCPDUMP_MINI\n+        else if (IS_SRC_OR_DST_PORT(BGP_PORT))\n                 bgp_print(ndo, bp, length);\n+#endif\n         else if (IS_SRC_OR_DST_PORT(PPTP_PORT))\n                 pptp_print(ndo, bp);\n+#ifndef TCPDUMP_MINI\n         else if (IS_SRC_OR_DST_PORT(REDIS_PORT))\n                 resp_print(ndo, bp, length);\n+#endif\n #ifdef ENABLE_SMB\n         else if (IS_SRC_OR_DST_PORT(NETBIOS_SSN_PORT))\n                 nbt_tcp_print(ndo, bp, length);\n \telse if (IS_SRC_OR_DST_PORT(SMB_PORT))\n \t\tsmb_tcp_print(ndo, bp, length);\n #endif\n+#ifndef TCPDUMP_MINI\n         else if (IS_SRC_OR_DST_PORT(BEEP_PORT))\n                 beep_print(ndo, bp, length);\n         else if (IS_SRC_OR_DST_PORT(OPENFLOW_PORT_OLD) || IS_SRC_OR_DST_PORT(OPENFLOW_PORT_IANA))\n                 openflow_print(ndo, bp, length);\n+#endif\n         else if (IS_SRC_OR_DST_PORT(FTP_PORT)) {\n                 ND_PRINT((ndo, \": \"));\n                 ftp_print(ndo, bp, length);\n@@ -725,6 +736,7 @@ tcp_print(netdissect_options *ndo,\n                  * XXX packet could be unaligned, it can go strange\n                  */\n                 ns_print(ndo, bp + 2, length - 2, 0);\n+#ifndef TCPDUMP_MINI\n         } else if (IS_SRC_OR_DST_PORT(MSDP_PORT)) {\n                 msdp_print(ndo, bp, length);\n         } else if (IS_SRC_OR_DST_PORT(RPKI_RTR_PORT)) {\n@@ -732,6 +744,7 @@ tcp_print(netdissect_options *ndo,\n         }\n         else if (length > 0 && (IS_SRC_OR_DST_PORT(LDP_PORT))) {\n                 ldp_print(ndo, bp, length);\n+#endif\n         }\n         else if ((IS_SRC_OR_DST_PORT(NFS_PORT)) &&\n                  length >= 4 && ND_TTEST2(*bp, 4)) {\n--- a/print-udp.c\n+++ b/print-udp.c\n@@ -430,10 +430,12 @@ udp_print(netdissect_options *ndo, regis\n \t\t\tvat_print(ndo, (const void *)(up + 1), up);\n \t\t\tbreak;\n \n+#ifndef TCPDUMP_MINI\n \t\tcase PT_WB:\n \t\t\tudpipaddr_print(ndo, ip, sport, dport);\n \t\t\twb_print(ndo, (const void *)(up + 1), length);\n \t\t\tbreak;\n+#endif\n \n \t\tcase PT_RPC:\n \t\t\trp = (const struct sunrpc_msg *)(up + 1);\n@@ -462,10 +464,12 @@ udp_print(netdissect_options *ndo, regis\n \t\t\tsnmp_print(ndo, (const u_char *)(up + 1), length);\n \t\t\tbreak;\n \n+#ifndef TCPDUMP_MINI\n \t\tcase PT_CNFP:\n \t\t\tudpipaddr_print(ndo, ip, sport, dport);\n \t\t\tcnfp_print(ndo, cp);\n \t\t\tbreak;\n+#endif\n \n \t\tcase PT_TFTP:\n \t\t\tudpipaddr_print(ndo, ip, sport, dport);\n@@ -483,6 +487,7 @@ udp_print(netdissect_options *ndo, regis\n \t\t\tradius_print(ndo, cp, length);\n \t\t\tbreak;\n \n+#ifndef TCPDUMP_MINI\n \t\tcase PT_VXLAN:\n \t\t\tudpipaddr_print(ndo, ip, sport, dport);\n \t\t\tvxlan_print(ndo, (const u_char *)(up + 1), length);\n@@ -497,6 +502,7 @@ udp_print(netdissect_options *ndo, regis\n \t\t\tudpipaddr_print(ndo, ip, sport, dport);\n \t\t\tlmp_print(ndo, cp, length);\n \t\t\tbreak;\n+#endif\n \t\t}\n \t\treturn;\n \t}\n@@ -574,31 +580,40 @@ udp_print(netdissect_options *ndo, regis\n \t\t\tns_print(ndo, (const u_char *)(up + 1), length, 0);\n \t\telse if (IS_SRC_OR_DST_PORT(MULTICASTDNS_PORT))\n \t\t\tns_print(ndo, (const u_char *)(up + 1), length, 1);\n+#ifndef TCPDUMP_MINI\n \t\telse if (IS_SRC_OR_DST_PORT(TIMED_PORT))\n \t\t\ttimed_print(ndo, (const u_char *)(up + 1));\n+#endif\n \t\telse if (IS_SRC_OR_DST_PORT(TFTP_PORT))\n \t\t\ttftp_print(ndo, (const u_char *)(up + 1), length);\n \t\telse if (IS_SRC_OR_DST_PORT(BOOTPC_PORT) || IS_SRC_OR_DST_PORT(BOOTPS_PORT))\n \t\t\tbootp_print(ndo, (const u_char *)(up + 1), length);\n+#ifndef TCPDUMP_MINI\n \t\telse if (IS_SRC_OR_DST_PORT(RIP_PORT))\n \t\t\trip_print(ndo, (const u_char *)(up + 1), length);\n+#endif\n \t\telse if (IS_SRC_OR_DST_PORT(AODV_PORT))\n \t\t\taodv_print(ndo, (const u_char *)(up + 1), length,\n \t\t\t    ip6 != NULL);\n+#ifndef TCPDUMP_MINI\n \t        else if (IS_SRC_OR_DST_PORT(ISAKMP_PORT))\n \t\t\t isakmp_print(ndo, (const u_char *)(up + 1), length, bp2);\n+\n \t        else if (IS_SRC_OR_DST_PORT(ISAKMP_PORT_NATT))\n \t\t\t isakmp_rfc3948_print(ndo, (const u_char *)(up + 1), length, bp2);\n #if 1 /*???*/\n \t        else if (IS_SRC_OR_DST_PORT(ISAKMP_PORT_USER1) || IS_SRC_OR_DST_PORT(ISAKMP_PORT_USER2))\n \t\t\tisakmp_print(ndo, (const u_char *)(up + 1), length, bp2);\n #endif\n+#endif\n \t\telse if (IS_SRC_OR_DST_PORT(SNMP_PORT) || IS_SRC_OR_DST_PORT(SNMPTRAP_PORT))\n \t\t\tsnmp_print(ndo, (const u_char *)(up + 1), length);\n \t\telse if (IS_SRC_OR_DST_PORT(NTP_PORT))\n \t\t\tntp_print(ndo, (const u_char *)(up + 1), length);\n+#ifndef TCPDUMP_MINI\n \t\telse if (IS_SRC_OR_DST_PORT(KERBEROS_PORT) || IS_SRC_OR_DST_PORT(KERBEROS_SEC_PORT))\n \t\t\tkrb_print(ndo, (const void *)(up + 1));\n+#endif\n \t\telse if (IS_SRC_OR_DST_PORT(L2TP_PORT))\n \t\t\tl2tp_print(ndo, (const u_char *)(up + 1), length);\n #ifdef ENABLE_SMB\n@@ -609,6 +624,7 @@ udp_print(netdissect_options *ndo, regis\n #endif\n \t\telse if (dport == VAT_PORT)\n \t\t\tvat_print(ndo, (const void *)(up + 1), up);\n+#ifndef TCPDUMP_MINI\n \t\telse if (IS_SRC_OR_DST_PORT(ZEPHYR_SRV_PORT) || IS_SRC_OR_DST_PORT(ZEPHYR_CLT_PORT))\n \t\t\tzephyr_print(ndo, (const void *)(up + 1), length);\n \t\t/*\n@@ -621,8 +637,11 @@ udp_print(netdissect_options *ndo, regis\n \t\t\t\t (const u_char *) ip);\n \t\telse if (IS_SRC_OR_DST_PORT(RIPNG_PORT))\n \t\t\tripng_print(ndo, (const u_char *)(up + 1), length);\n+#endif\n+\n \t\telse if (IS_SRC_OR_DST_PORT(DHCP6_SERV_PORT) || IS_SRC_OR_DST_PORT(DHCP6_CLI_PORT))\n \t\t\tdhcp6_print(ndo, (const u_char *)(up + 1), length);\n+#ifndef TCPDUMP_MINI\n \t\telse if (IS_SRC_OR_DST_PORT(AHCP_PORT))\n \t\t\tahcp_print(ndo, (const u_char *)(up + 1), length);\n \t\telse if (IS_SRC_OR_DST_PORT(BABEL_PORT) || IS_SRC_OR_DST_PORT(BABEL_PORT_OLD))\n@@ -636,6 +655,7 @@ udp_print(netdissect_options *ndo, regis\n \t\t\twb_print(ndo, (const void *)(up + 1), length);\n \t\telse if (IS_SRC_OR_DST_PORT(CISCO_AUTORP_PORT))\n \t\t\tcisco_autorp_print(ndo, (const void *)(up + 1), length);\n+#endif\n \t\telse if (IS_SRC_OR_DST_PORT(RADIUS_PORT) ||\n \t\t\t IS_SRC_OR_DST_PORT(RADIUS_NEW_PORT) ||\n \t\t\t IS_SRC_OR_DST_PORT(RADIUS_ACCOUNTING_PORT) ||\n@@ -643,15 +663,18 @@ udp_print(netdissect_options *ndo, regis\n \t\t\t IS_SRC_OR_DST_PORT(RADIUS_CISCO_COA_PORT) ||\n \t\t\t IS_SRC_OR_DST_PORT(RADIUS_COA_PORT) )\n \t\t\tradius_print(ndo, (const u_char *)(up+1), length);\n+#ifndef TCPDUMP_MINI\n \t\telse if (dport == HSRP_PORT)\n \t\t\thsrp_print(ndo, (const u_char *)(up + 1), length);\n \t\telse if (IS_SRC_OR_DST_PORT(LWRES_PORT))\n \t\t\tlwres_print(ndo, (const u_char *)(up + 1), length);\n \t\telse if (IS_SRC_OR_DST_PORT(LDP_PORT))\n \t\t\tldp_print(ndo, (const u_char *)(up + 1), length);\n+#endif\n \t\telse if (IS_SRC_OR_DST_PORT(OLSR_PORT))\n \t\t\tolsr_print(ndo, (const u_char *)(up + 1), length,\n \t\t\t\t\t(IP_V(ip) == 6) ? 1 : 0);\n+#ifndef TCPDUMP_MINI\n \t\telse if (IS_SRC_OR_DST_PORT(MPLS_LSP_PING_PORT))\n \t\t\tlspping_print(ndo, (const u_char *)(up + 1), length);\n \t\telse if (dport == BFD_CONTROL_PORT ||\n@@ -669,10 +692,12 @@ udp_print(netdissect_options *ndo, regis\n                         lwapp_control_print(ndo, (const u_char *)(up + 1), length, 0);\n                 else if (IS_SRC_OR_DST_PORT(LWAPP_DATA_PORT))\n                         lwapp_data_print(ndo, (const u_char *)(up + 1), length);\n+#endif\n                 else if (IS_SRC_OR_DST_PORT(SIP_PORT))\n \t\t\tsip_print(ndo, (const u_char *)(up + 1), length);\n                 else if (IS_SRC_OR_DST_PORT(SYSLOG_PORT))\n \t\t\tsyslog_print(ndo, (const u_char *)(up + 1), length);\n+#ifndef TCPDUMP_MINI\n                 else if (IS_SRC_OR_DST_PORT(OTV_PORT))\n \t\t\totv_print(ndo, (const u_char *)(up + 1), length);\n                 else if (IS_SRC_OR_DST_PORT(VXLAN_PORT))\n@@ -689,7 +714,9 @@ udp_print(netdissect_options *ndo, regis\n \t\t\tif (ndo->ndo_vflag)\n \t\t\t\tND_PRINT((ndo, \"kip \"));\n \t\t\tllap_print(ndo, cp, length);\n-\t\t} else {\n+\t\t}\n+#endif\n+\t\telse {\n \t\t\tif (ulen > length)\n \t\t\t\tND_PRINT((ndo, \"UDP, bad length %u > %u\",\n \t\t\t\t    ulen, length));\n"
  },
  {
    "path": "package/network/utils/tcpdump/patches/101-CVE-2020-8037.patch",
    "content": "--- a/print-ppp.c\n+++ b/print-ppp.c\n@@ -1368,19 +1368,29 @@ trunc:\n }\n \n #ifndef TCPDUMP_MINI\n+/*\n+ * Un-escape RFC 1662 PPP in HDLC-like framing, with octet escapes.\n+ * The length argument is the on-the-wire length, not the captured\n+ * length; we can only un-escape the captured part.\n+ */\n static void\n ppp_hdlc(netdissect_options *ndo,\n          const u_char *p, int length)\n {\n+\tu_int caplen = ndo->ndo_snapend - p;\n \tu_char *b, *t, c;\n \tconst u_char *s;\n-\tint i, proto;\n+\tu_int i;\n+\tint proto;\n \tconst void *se;\n \n+\tif (caplen == 0)\n+\t\treturn;\n+\n         if (length <= 0)\n                 return;\n \n-\tb = (u_char *)malloc(length);\n+\tb = (u_char *)malloc(caplen);\n \tif (b == NULL)\n \t\treturn;\n \n@@ -1389,10 +1399,10 @@ ppp_hdlc(netdissect_options *ndo,\n \t * Do this so that we dont overwrite the original packet\n \t * contents.\n \t */\n-\tfor (s = p, t = b, i = length; i > 0 && ND_TTEST(*s); i--) {\n+\tfor (s = p, t = b, i = caplen; i != 0; i--) {\n \t\tc = *s++;\n \t\tif (c == 0x7d) {\n-\t\t\tif (i <= 1 || !ND_TTEST(*s))\n+\t\t\tif (i <= 1)\n \t\t\t\tbreak;\n \t\t\ti--;\n \t\t\tc = *s++ ^ 0x20;\n"
  },
  {
    "path": "package/network/utils/tcpdump/patches/102-CVE-2018-16301.patch",
    "content": "From 8ab211a7ec728bb0ad8c766c8eeb12deb0a13b86 Mon Sep 17 00:00:00 2001\nFrom: Guy Harris <gharris@sonic.net>\nDate: Wed, 30 Sep 2020 11:37:30 -0700\nSubject: [PATCH] Handle very large -f files by rejecting them.\n\n_read(), on Windows, has a 32-bit size argument and a 32-bit return\nvalue, so reject -f files that have more than 2^31-1 characters.\n\nAdd some #defines so that, on Windows, we use _fstati64 to get the size\nof that file, to handle large files.\n\nDon't assume that our definition for ssize_t is the same size as size_t;\nby the time we want to print the return value of the read, we know it'll\nfit into an int, so just cast it to int and print it with %d.\n\n(cherry picked from commit faf8fb70af3a013e5d662b8283dec742fd6b1a77)\n---\n netdissect-stdinc.h | 16 +++++++++++++++-\n tcpdump.c           | 15 ++++++++++++---\n 2 files changed, 27 insertions(+), 4 deletions(-)\n\n--- a/netdissect-stdinc.h\n+++ b/netdissect-stdinc.h\n@@ -149,10 +149,17 @@\n #ifdef _MSC_VER\n #define stat _stat\n #define open _open\n-#define fstat _fstat\n #define read _read\n #define close _close\n #define O_RDONLY _O_RDONLY\n+\n+/*\n+ * We define our_fstat64 as _fstati64, and define our_statb as\n+ * struct _stati64, so we get 64-bit file sizes.\n+ */\n+#define our_fstat _fstati64\n+#define our_statb struct _stati64\n+\n #endif  /* _MSC_VER */\n \n /*\n@@ -211,6 +218,13 @@ typedef char* caddr_t;\n \n #include <arpa/inet.h>\n \n+/*\n+ * We should have large file support enabled, if it's available,\n+ * so just use fstat as our_fstat and struct stat as our_statb.\n+ */\n+#define our_fstat fstat\n+#define our_statb struct stat\n+\n #endif /* _WIN32 */\n \n #ifndef HAVE___ATTRIBUTE__\n--- a/tcpdump.c\n+++ b/tcpdump.c\n@@ -108,6 +108,7 @@ The Regents of the University of Califor\n #endif /* HAVE_CAP_NG_H */\n #endif /* HAVE_LIBCAP_NG */\n \n+#include \"netdissect-stdinc.h\"\n #include \"netdissect.h\"\n #include \"interface.h\"\n #include \"addrtoname.h\"\n@@ -861,15 +862,22 @@ read_infile(char *fname)\n {\n \tregister int i, fd, cc;\n \tregister char *cp;\n-\tstruct stat buf;\n+\tour_statb buf;\n \n \tfd = open(fname, O_RDONLY|O_BINARY);\n \tif (fd < 0)\n \t\terror(\"can't open %s: %s\", fname, pcap_strerror(errno));\n \n-\tif (fstat(fd, &buf) < 0)\n+\tif (our_fstat(fd, &buf) < 0)\n \t\terror(\"can't stat %s: %s\", fname, pcap_strerror(errno));\n \n+\t/*\n+\t * Reject files whose size doesn't fit into an int; a filter\n+\t * *that* large will probably be too big.\n+\t */\n+\tif (buf.st_size > INT_MAX)\n+\t\terror(\"%s is too large\", fname);\n+\n \tcp = malloc((u_int)buf.st_size + 1);\n \tif (cp == NULL)\n \t\terror(\"malloc(%d) for %s: %s\", (u_int)buf.st_size + 1,\n@@ -878,7 +886,8 @@ read_infile(char *fname)\n \tif (cc < 0)\n \t\terror(\"read %s: %s\", fname, pcap_strerror(errno));\n \tif (cc != buf.st_size)\n-\t\terror(\"short read %s (%d != %d)\", fname, cc, (int)buf.st_size);\n+\t\terror(\"short read %s (%d != %d)\", fname, (int) cc,\n+\t\t    (int)buf.st_size);\n \n \tclose(fd);\n \t/* replace \"# comment\" with spaces */\n"
  },
  {
    "path": "package/network/utils/umbim/Makefile",
    "content": "include $(TOPDIR)/rules.mk\n\nPKG_NAME:=umbim\nPKG_RELEASE:=$(AUTORELEASE)\n\nPKG_SOURCE_PROTO:=git\nPKG_SOURCE_URL=$(PROJECT_GIT)/project/umbim.git\nPKG_SOURCE_DATE:=2021-08-18\nPKG_SOURCE_VERSION:=de5623104baee6e0c13c92f05c15bf4b4145c0b1\nPKG_MIRROR_HASH:=2d4a75d2b53c8413521a2fd138895e327bff3f4b4d29a540342b2d2e1e009852\nPKG_MAINTAINER:=John Crispin <john@phrozen.org>\n\nPKG_LICENSE:=GPL-2.0\nPKG_LICENSE_FILES:=\n\nPKG_FLAGS:=nonshared\n\ninclude $(INCLUDE_DIR)/package.mk\ninclude $(INCLUDE_DIR)/cmake.mk\n\ndefine Package/umbim\n  SECTION:=net\n  CATEGORY:=Network\n  SUBMENU:=WWAN\n  DEPENDS:=+libubox +kmod-usb-net +kmod-usb-net-cdc-mbim +wwan\n  TITLE:=Control utility for mobile broadband modems\nendef\n\ndefine Package/umbim/description\n  umbim is a command line tool for controlling mobile broadband modems using\n  the MBIM-protocol.\nendef\n\nTARGET_CFLAGS += \\\n\t-I$(STAGING_DIR)/usr/include -ffunction-sections -fdata-sections\n\nTARGET_LDFLAGS += -Wl,--gc-sections\n\ndefine Package/umbim/install\n\t$(INSTALL_DIR) $(1)/sbin\n\t$(INSTALL_BIN) $(PKG_BUILD_DIR)/umbim $(1)/sbin/\n\t$(CP) ./files/* $(1)/\nendef\n\n$(eval $(call BuildPackage,umbim))\n"
  },
  {
    "path": "package/network/utils/umbim/files/lib/netifd/proto/mbim.sh",
    "content": "#!/bin/sh\n\n[ -n \"$INCLUDE_ONLY\" ] || {\n\t. /lib/functions.sh\n\t. ../netifd-proto.sh\n\tinit_proto \"$@\"\n}\n#DBG=-v\n\nproto_mbim_init_config() {\n\tavailable=1\n\tno_device=1\n\tproto_config_add_string \"device:device\"\n\tproto_config_add_string apn\n\tproto_config_add_string pincode\n\tproto_config_add_string delay\n\tproto_config_add_string auth\n\tproto_config_add_string username\n\tproto_config_add_string password\n\tproto_config_add_defaults\n}\n\n_proto_mbim_setup() {\n\tlocal interface=\"$1\"\n\tlocal tid=2\n\tlocal ret\n\n\tlocal device apn pincode delay $PROTO_DEFAULT_OPTIONS\n\tjson_get_vars device apn pincode delay auth username password $PROTO_DEFAULT_OPTIONS\n\n\t[ -n \"$ctl_device\" ] && device=$ctl_device\n\n\t[ -n \"$device\" ] || {\n\t\techo \"mbim[$$]\" \"No control device specified\"\n\t\tproto_notify_error \"$interface\" NO_DEVICE\n\t\tproto_set_available \"$interface\" 0\n\t\treturn 1\n\t}\n\t[ -c \"$device\" ] || {\n\t\techo \"mbim[$$]\" \"The specified control device does not exist\"\n\t\tproto_notify_error \"$interface\" NO_DEVICE\n\t\tproto_set_available \"$interface\" 0\n\t\treturn 1\n\t}\n\n\tdevname=\"$(basename \"$device\")\"\n\tdevpath=\"$(readlink -f /sys/class/usbmisc/$devname/device/)\"\n\tifname=\"$( ls \"$devpath\"/net )\"\n\n\t[ -n \"$ifname\" ] || {\n\t\techo \"mbim[$$]\" \"Failed to find matching interface\"\n\t\tproto_notify_error \"$interface\" NO_IFNAME\n\t\tproto_set_available \"$interface\" 0\n\t\treturn 1\n\t}\n\n\t[ -n \"$apn\" ] || {\n\t\techo \"mbim[$$]\" \"No APN specified\"\n\t\tproto_notify_error \"$interface\" NO_APN\n\t\treturn 1\n\t}\n\n\t[ -n \"$delay\" ] && sleep \"$delay\"\n\n\techo \"mbim[$$]\" \"Reading capabilities\"\n\tumbim $DBG -n -d $device caps || {\n\t\techo \"mbim[$$]\" \"Failed to read modem caps\"\n\t\ttid=$((tid + 1))\n\t\tumbim $DBG -t $tid -d \"$device\" disconnect\n\t\tproto_notify_error \"$interface\" PIN_FAILED\n\t\treturn 1\n\t}\n\ttid=$((tid + 1))\n\n\t[ \"$pincode\" ] && {\n\t\techo \"mbim[$$]\" \"Sending pin\"\n\t\tumbim $DBG -n -t $tid -d $device unlock \"$pincode\" || {\n\t\t\techo \"mbim[$$]\" \"Unable to verify PIN\"\n\t\t\ttid=$((tid + 1))\n\t\t\tumbim $DBG -t $tid -d \"$device\" disconnect\n\t\t\tproto_notify_error \"$interface\" PIN_FAILED\n\t\t\tproto_block_restart \"$interface\"\n\t\t\treturn 1\n\t\t}\n\t}\n\ttid=$((tid + 1))\n\n\techo \"mbim[$$]\" \"Checking pin\"\n\tumbim $DBG -n -t $tid -d $device pinstate\n\t[ $? -eq 2 ] && {\n\t\techo \"mbim[$$]\" \"PIN required\"\n\t\ttid=$((tid + 1))\n\t\tumbim $DBG -t $tid -d \"$device\" disconnect\n\t\tproto_notify_error \"$interface\" PIN_FAILED\n\t\tproto_block_restart \"$interface\"\n\t\treturn 1\n\t}\n\ttid=$((tid + 1))\n\n\techo \"mbim[$$]\" \"Checking subscriber\"\n\tumbim $DBG -n -t $tid -d $device subscriber || {\n\t\techo \"mbim[$$]\" \"Subscriber init failed\"\n\t\ttid=$((tid + 1))\n\t\tumbim $DBG -t $tid -d \"$device\" disconnect\n\t\tproto_notify_error \"$interface\" NO_SUBSCRIBER\n\t\treturn 1\n\t}\n\ttid=$((tid + 1))\n\n\techo \"mbim[$$]\" \"Register with network\"\n\tumbim $DBG -n -t $tid -d $device registration || {\n\t\techo \"mbim[$$]\" \"Subscriber registration failed\"\n\t\ttid=$((tid + 1))\n\t\tumbim $DBG -t $tid -d \"$device\" disconnect\n\t\tproto_notify_error \"$interface\" NO_REGISTRATION\n\t\treturn 1\n\t}\n\ttid=$((tid + 1))\n\n\techo \"mbim[$$]\" \"Attach to network\"\n\tumbim $DBG -n -t $tid -d $device attach || {\n\t\techo \"mbim[$$]\" \"Failed to attach to network\"\n\t\ttid=$((tid + 1))\n\t\tumbim $DBG -t $tid -d \"$device\" disconnect\n\t\tproto_notify_error \"$interface\" ATTACH_FAILED\n\t\treturn 1\n\t}\n\ttid=$((tid + 1))\n\n\techo \"mbim[$$]\" \"Connect to network\"\n\twhile ! umbim $DBG -n -t $tid -d $device connect \"$apn\" \"$auth\" \"$username\" \"$password\"; do\n\t\ttid=$((tid + 1))\n\t\tsleep 1;\n\tdone\n\ttid=$((tid + 1))\n\n\tuci_set_state network $interface tid \"$tid\"\n\n\techo \"mbim[$$]\" \"Connected, starting DHCP\"\n\tproto_init_update \"$ifname\" 1\n\tproto_send_update \"$interface\"\n\n\tjson_init\n\tjson_add_string name \"${interface}_4\"\n\tjson_add_string ifname \"@$interface\"\n\tjson_add_string proto \"dhcp\"\n\tproto_add_dynamic_defaults\n\tjson_close_object\n\tubus call network add_dynamic \"$(json_dump)\"\n\n\tjson_init\n\tjson_add_string name \"${interface}_6\"\n\tjson_add_string ifname \"@$interface\"\n\tjson_add_string proto \"dhcpv6\"\n\tjson_add_string extendprefix 1\n\tproto_add_dynamic_defaults\n\tjson_close_object\n\tubus call network add_dynamic \"$(json_dump)\"\n}\n\nproto_mbim_setup() {\n\tlocal ret\n\n\t_proto_mbim_setup $@\n\tret=$?\n\n\t[ \"$ret\" = 0 ] || {\n\t\tlogger \"mbim bringup failed, retry in 15s\"\n\t\tsleep 15\n\t}\n\n\treturn $ret\n}\n\nproto_mbim_teardown() {\n\tlocal interface=\"$1\"\n\n\tlocal device\n\tjson_get_vars device\n\tlocal tid=$(uci_get_state network $interface tid)\n\n\t[ -n \"$ctl_device\" ] && device=$ctl_device\n\n\techo \"mbim[$$]\" \"Stopping network\"\n\t[ -n \"$tid\" ] && {\n\t\tumbim $DBG -t $tid -d \"$device\" disconnect\n\t\tuci_revert_state network $interface tid\n\t}\n\n\tproto_init_update \"*\" 0\n\tproto_send_update \"$interface\"\n}\n\n[ -n \"$INCLUDE_ONLY\" ] || add_protocol mbim\n"
  },
  {
    "path": "package/network/utils/uqmi/Makefile",
    "content": "include $(TOPDIR)/rules.mk\n\nPKG_NAME:=uqmi\nPKG_RELEASE:=$(AUTORELEASE)\n\nPKG_SOURCE_PROTO:=git\nPKG_SOURCE_URL=$(PROJECT_GIT)/project/uqmi.git\nPKG_SOURCE_DATE:=2022-05-04\nPKG_SOURCE_VERSION:=56cb2d4056fef132ccf78dfb6f3074ae5d109992\nPKG_MIRROR_HASH:=cc832b5318805df8c8387a3650f250dee72d5f1dbda4e4866b5503e186b2210c\nPKG_MAINTAINER:=Matti Laakso <malaakso@elisanet.fi>\n\nPKG_LICENSE:=GPL-2.0\nPKG_LICENSE_FILES:=\n\nPKG_FLAGS:=nonshared\n\ninclude $(INCLUDE_DIR)/package.mk\ninclude $(INCLUDE_DIR)/cmake.mk\n\ndefine Package/uqmi\n  SECTION:=net\n  CATEGORY:=Network\n  SUBMENU:=WWAN\n  DEPENDS:=+libubox +libblobmsg-json +kmod-usb-net +kmod-usb-net-qmi-wwan +wwan\n  TITLE:=Control utility for mobile broadband modems\nendef\n\ndefine Package/uqmi/description\n  uqmi is a command line tool for controlling mobile broadband modems using\n  the QMI-protocol.\nendef\n\nTARGET_CFLAGS += \\\n\t-I$(STAGING_DIR)/usr/include -ffunction-sections -fdata-sections\n\nTARGET_LDFLAGS += -Wl,--gc-sections\n\nCMAKE_OPTIONS += \\\n\t-DDEBUG=1\n\ndefine Package/uqmi/install\n\t$(INSTALL_DIR) $(1)/sbin\n\t$(INSTALL_BIN) $(PKG_BUILD_DIR)/uqmi $(1)/sbin/\n\t$(CP) ./files/* $(1)/\nendef\n\n$(eval $(call BuildPackage,uqmi))\n"
  },
  {
    "path": "package/network/utils/uqmi/files/lib/netifd/proto/qmi.sh",
    "content": "#!/bin/sh\n\n[ -n \"$INCLUDE_ONLY\" ] || {\n\t. /lib/functions.sh\n\t. ../netifd-proto.sh\n\tinit_proto \"$@\"\n}\n\nproto_qmi_init_config() {\n\tavailable=1\n\tno_device=1\n\tproto_config_add_string \"device:device\"\n\tproto_config_add_string apn\n\tproto_config_add_string auth\n\tproto_config_add_string username\n\tproto_config_add_string password\n\tproto_config_add_string pincode\n\tproto_config_add_int delay\n\tproto_config_add_string modes\n\tproto_config_add_string pdptype\n\tproto_config_add_int profile\n\tproto_config_add_boolean dhcp\n\tproto_config_add_boolean dhcpv6\n\tproto_config_add_boolean autoconnect\n\tproto_config_add_int plmn\n\tproto_config_add_int timeout\n\tproto_config_add_int mtu\n\tproto_config_add_defaults\n}\n\nproto_qmi_setup() {\n\tlocal interface=\"$1\"\n\tlocal dataformat connstat plmn_mode mcc mnc\n\tlocal device apn auth username password pincode delay modes pdptype\n\tlocal profile dhcp dhcpv6 autoconnect plmn timeout mtu $PROTO_DEFAULT_OPTIONS\n\tlocal ip4table ip6table\n\tlocal cid_4 pdh_4 cid_6 pdh_6\n\tlocal ip_6 ip_prefix_length gateway_6 dns1_6 dns2_6\n\n\tjson_get_vars device apn auth username password pincode delay modes\n\tjson_get_vars pdptype profile dhcp dhcpv6 autoconnect plmn ip4table\n\tjson_get_vars ip6table timeout mtu $PROTO_DEFAULT_OPTIONS\n\n\t[ \"$timeout\" = \"\" ] && timeout=\"10\"\n\n\t[ \"$metric\" = \"\" ] && metric=\"0\"\n\n\t[ -n \"$ctl_device\" ] && device=$ctl_device\n\n\t[ -n \"$device\" ] || {\n\t\techo \"No control device specified\"\n\t\tproto_notify_error \"$interface\" NO_DEVICE\n\t\tproto_set_available \"$interface\" 0\n\t\treturn 1\n\t}\n\n\t[ -n \"$delay\" ] && sleep \"$delay\"\n\n\tdevice=\"$(readlink -f $device)\"\n\t[ -c \"$device\" ] || {\n\t\techo \"The specified control device does not exist\"\n\t\tproto_notify_error \"$interface\" NO_DEVICE\n\t\tproto_set_available \"$interface\" 0\n\t\treturn 1\n\t}\n\n\tdevname=\"$(basename \"$device\")\"\n\tdevpath=\"$(readlink -f /sys/class/usbmisc/$devname/device/)\"\n\tifname=\"$( ls \"$devpath\"/net )\"\n\t[ -n \"$ifname\" ] || {\n\t\techo \"The interface could not be found.\"\n\t\tproto_notify_error \"$interface\" NO_IFACE\n\t\tproto_set_available \"$interface\" 0\n\t\treturn 1\n\t}\n\n\t[ -n \"$mtu\" ] && {\n\t\techo \"Setting MTU to $mtu\"\n\t\t/sbin/ip link set dev $ifname mtu $mtu\n\t}\n\n\techo \"Waiting for SIM initialization\"\n\tlocal uninitialized_timeout=0\n\twhile uqmi -s -d \"$device\" --get-pin-status | grep '\"UIM uninitialized\"' > /dev/null; do\n\t\t[ -e \"$device\" ] || return 1\n\t\tif [ \"$uninitialized_timeout\" -lt \"$timeout\" -o \"$timeout\" = \"0\" ]; then\n\t\t\tlet uninitialized_timeout++\n\t\t\tsleep 1;\n\t\telse\n\t\t\techo \"SIM not initialized\"\n\t\t\tproto_notify_error \"$interface\" SIM_NOT_INITIALIZED\n\t\t\tproto_block_restart \"$interface\"\n\t\t\treturn 1\n\t\tfi\n\tdone\n\n\tif uqmi -s -d \"$device\" --uim-get-sim-state | grep -q '\"Not supported\"\\|\"Invalid QMI command\"' &&\n\t   uqmi -s -d \"$device\" --get-pin-status | grep -q '\"Not supported\"\\|\"Invalid QMI command\"' ; then\n\t\t[ -n \"$pincode\" ] && {\n\t\t\tuqmi -s -d \"$device\" --verify-pin1 \"$pincode\" > /dev/null || uqmi -s -d \"$device\" --uim-verify-pin1 \"$pincode\" > /dev/null || {\n\t\t\t\techo \"Unable to verify PIN\"\n\t\t\t\tproto_notify_error \"$interface\" PIN_FAILED\n\t\t\t\tproto_block_restart \"$interface\"\n\t\t\t\treturn 1\n\t\t\t}\n\t\t}\n\telse\n\t\tjson_load \"$(uqmi -s -d \"$device\" --get-pin-status)\"\n\t\tjson_get_var pin1_status pin1_status\n\t\tif [ -z \"$pin1_status\" ]; then\n\t\t\tjson_load \"$(uqmi -s -d \"$device\" --uim-get-sim-state)\"\n\t\t\tjson_get_var pin1_status pin1_status\n\t\tfi\n\t\tjson_get_var pin1_verify_tries pin1_verify_tries\n\n\t\tcase \"$pin1_status\" in\n\t\t\tdisabled)\n\t\t\t\techo \"PIN verification is disabled\"\n\t\t\t\t;;\n\t\t\tblocked)\n\t\t\t\techo \"SIM locked PUK required\"\n\t\t\t\tproto_notify_error \"$interface\" PUK_NEEDED\n\t\t\t\tproto_block_restart \"$interface\"\n\t\t\t\treturn 1\n\t\t\t\t;;\n\t\t\tnot_verified)\n\t\t\t\t[ \"$pin1_verify_tries\" -lt \"3\" ] && {\n\t\t\t\t\techo \"PIN verify count value is $pin1_verify_tries this is below the limit of 3\"\n\t\t\t\t\tproto_notify_error \"$interface\" PIN_TRIES_BELOW_LIMIT\n\t\t\t\t\tproto_block_restart \"$interface\"\n\t\t\t\t\treturn 1\n\t\t\t\t}\n\t\t\t\tif [ -n \"$pincode\" ]; then\n\t\t\t\t\tuqmi -s -d \"$device\" --verify-pin1 \"$pincode\" > /dev/null 2>&1 || uqmi -s -d \"$device\" --uim-verify-pin1 \"$pincode\" > /dev/null 2>&1 || {\n\t\t\t\t\t\techo \"Unable to verify PIN\"\n\t\t\t\t\t\tproto_notify_error \"$interface\" PIN_FAILED\n\t\t\t\t\t\tproto_block_restart \"$interface\"\n\t\t\t\t\t\treturn 1\n\t\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t\techo \"PIN not specified but required\"\n\t\t\t\t\tproto_notify_error \"$interface\" PIN_NOT_SPECIFIED\n\t\t\t\t\tproto_block_restart \"$interface\"\n\t\t\t\t\treturn 1\n\t\t\t\tfi\n\t\t\t\t;;\n\t\t\tverified)\n\t\t\t\techo \"PIN already verified\"\n\t\t\t\t;;\n\t\t\t*)\n\t\t\t\techo \"PIN status failed (${pin1_status:-sim_not_present})\"\n\t\t\t\tproto_notify_error \"$interface\" PIN_STATUS_FAILED\n\t\t\t\tproto_block_restart \"$interface\"\n\t\t\t\treturn 1\n\t\t\t;;\n\t\tesac\n\t\tjson_cleanup\n\tfi\n\n\tif [ -n \"$plmn\" ]; then\n\t\tjson_load \"$(uqmi -s -d \"$device\" --get-plmn)\"\n\t\tjson_get_var plmn_mode mode\n\t\tjson_get_vars mcc mnc || {\n\t\t\tmcc=0\n\t\t\tmnc=0\n\t\t}\n\n\t\tif [ \"$plmn\" = \"0\" ]; then\n\t\t\tif [ \"$plmn_mode\" != \"automatic\" ]; then\n\t\t\t\tmcc=0\n\t\t\t\tmnc=0\n\t\t\t\techo \"Setting PLMN to auto\"\n\t\t\tfi\n\t\telif [ \"$mcc\" -ne \"${plmn:0:3}\" -o \"$mnc\" -ne \"${plmn:3}\" ]; then\n\t\t\tmcc=${plmn:0:3}\n\t\t\tmnc=${plmn:3}\n\t\t\techo \"Setting PLMN to $plmn\"\n\t\telse\n\t\t\tmcc=\"\"\n\t\t\tmnc=\"\"\n\t\tfi\n\tfi\n\n\tif [ -n \"$mcc\" -a -n \"$mnc\" ]; then\n\t\tuqmi -s -d \"$device\" --set-plmn --mcc \"$mcc\" --mnc \"$mnc\" > /dev/null 2>&1 || {\n\t\t\techo \"Unable to set PLMN\"\n\t\t\tproto_notify_error \"$interface\" PLMN_FAILED\n\t\t\tproto_block_restart \"$interface\"\n\t\t\treturn 1\n\t\t}\n\tfi\n\n\t# Cleanup current state if any\n\tuqmi -s -d \"$device\" --stop-network 0xffffffff --autoconnect > /dev/null 2>&1\n\n\t# Go online\n\tuqmi -s -d \"$device\" --set-device-operating-mode online > /dev/null 2>&1\n\n\t# Set IP format\n\tuqmi -s -d \"$device\" --set-data-format 802.3 > /dev/null 2>&1\n\tuqmi -s -d \"$device\" --wda-set-data-format 802.3 > /dev/null 2>&1\n\tdataformat=\"$(uqmi -s -d \"$device\" --wda-get-data-format)\"\n\n\tif [ \"$dataformat\" = '\"raw-ip\"' ]; then\n\n\t\t[ -f /sys/class/net/$ifname/qmi/raw_ip ] || {\n\t\t\techo \"Device only supports raw-ip mode but is missing this required driver attribute: /sys/class/net/$ifname/qmi/raw_ip\"\n\t\t\treturn 1\n\t\t}\n\n\t\techo \"Device does not support 802.3 mode. Informing driver of raw-ip only for $ifname ..\"\n\t\techo \"Y\" > /sys/class/net/$ifname/qmi/raw_ip\n\tfi\n\n\tuqmi -s -d \"$device\" --sync > /dev/null 2>&1\n\n\tuqmi -s -d \"$device\" --network-register > /dev/null 2>&1\n\n\techo \"Waiting for network registration\"\n\tsleep 1\n\tlocal registration_timeout=0\n\tlocal registration_state=\"\"\n\twhile true; do\n\t\tregistration_state=$(uqmi -s -d \"$device\" --get-serving-system 2>/dev/null | jsonfilter -e \"@.registration\" 2>/dev/null)\n\n\t\t[ \"$registration_state\" = \"registered\" ] && break\n\n\t\tif [ \"$registration_state\" = \"searching\" ] || [ \"$registration_state\" = \"not_registered\" ]; then\n\t\t\tif [ \"$registration_timeout\" -lt \"$timeout\" ] || [ \"$timeout\" = \"0\" ]; then\n\t\t\t\t[ \"$registration_state\" = \"searching\" ] || {\n\t\t\t\t\techo \"Device stopped network registration. Restart network registration\"\n\t\t\t\t\tuqmi -s -d \"$device\" --network-register > /dev/null 2>&1\n\t\t\t\t}\n\t\t\t\tlet registration_timeout++\n\t\t\t\tsleep 1\n\t\t\t\tcontinue\n\t\t\tfi\n\t\t\techo \"Network registration failed, registration timeout reached\"\n\t\telse\n\t\t\t# registration_state is 'registration_denied' or 'unknown' or ''\n\t\t\techo \"Network registration failed (reason: '$registration_state')\"\n\t\tfi\n\n\t\tproto_notify_error \"$interface\" NETWORK_REGISTRATION_FAILED\n\t\tproto_block_restart \"$interface\"\n\t\treturn 1\n\tdone\n\n\t[ -n \"$modes\" ] && uqmi -s -d \"$device\" --set-network-modes \"$modes\" > /dev/null 2>&1\n\n\techo \"Starting network $interface\"\n\n\tpdptype=\"$(echo \"$pdptype\" | awk '{print tolower($0)}')\"\n\n\t[ \"$pdptype\" = \"ip\" -o \"$pdptype\" = \"ipv6\" -o \"$pdptype\" = \"ipv4v6\" ] || pdptype=\"ip\"\n\n\tif [ \"$pdptype\" = \"ip\" ]; then\n\t\t[ -z \"$autoconnect\" ] && autoconnect=1\n\t\t[ \"$autoconnect\" = 0 ] && autoconnect=\"\"\n\telse\n\t\t[ \"$autoconnect\" = 1 ] || autoconnect=\"\"\n\tfi\n\n\t[ \"$pdptype\" = \"ip\" -o \"$pdptype\" = \"ipv4v6\" ] && {\n\t\tcid_4=$(uqmi -s -d \"$device\" --get-client-id wds)\n\t\tif ! [ \"$cid_4\" -eq \"$cid_4\" ] 2> /dev/null; then\n\t\t\techo \"Unable to obtain client ID\"\n\t\t\tproto_notify_error \"$interface\" NO_CID\n\t\t\treturn 1\n\t\tfi\n\n\t\tuqmi -s -d \"$device\" --set-client-id wds,\"$cid_4\" --set-ip-family ipv4 > /dev/null 2>&1\n\n\t\tpdh_4=$(uqmi -s -d \"$device\" --set-client-id wds,\"$cid_4\" \\\n\t\t\t--start-network \\\n\t\t\t${apn:+--apn $apn} \\\n\t\t\t${profile:+--profile $profile} \\\n\t\t\t${auth:+--auth-type $auth} \\\n\t\t\t${username:+--username $username} \\\n\t\t\t${password:+--password $password} \\\n\t\t\t${autoconnect:+--autoconnect})\n\n\t\t# pdh_4 is a numeric value on success\n\t\tif ! [ \"$pdh_4\" -eq \"$pdh_4\" ] 2> /dev/null; then\n\t\t\techo \"Unable to connect IPv4\"\n\t\t\tuqmi -s -d \"$device\" --set-client-id wds,\"$cid_4\" --release-client-id wds > /dev/null 2>&1\n\t\t\tproto_notify_error \"$interface\" CALL_FAILED\n\t\t\treturn 1\n\t\tfi\n\n\t\t# Check data connection state\n\t\tconnstat=$(uqmi -s -d \"$device\" --set-client-id wds,\"$cid_4\" --get-data-status)\n\t\t[ \"$connstat\" == '\"connected\"' ] || {\n\t\t\techo \"No data link!\"\n\t\t\tuqmi -s -d \"$device\" --set-client-id wds,\"$cid_4\" --release-client-id wds > /dev/null 2>&1\n\t\t\tproto_notify_error \"$interface\" CALL_FAILED\n\t\t\treturn 1\n\t\t}\n\t}\n\n\t[ \"$pdptype\" = \"ipv6\" -o \"$pdptype\" = \"ipv4v6\" ] && {\n\t\tcid_6=$(uqmi -s -d \"$device\" --get-client-id wds)\n\t\tif ! [ \"$cid_6\" -eq \"$cid_6\" ] 2> /dev/null; then\n\t\t\techo \"Unable to obtain client ID\"\n\t\t\tproto_notify_error \"$interface\" NO_CID\n\t\t\treturn 1\n\t\tfi\n\n\t\tuqmi -s -d \"$device\" --set-client-id wds,\"$cid_6\" --set-ip-family ipv6 > /dev/null 2>&1\n\n\t\tpdh_6=$(uqmi -s -d \"$device\" --set-client-id wds,\"$cid_6\" \\\n\t\t\t--start-network \\\n\t\t\t${apn:+--apn $apn} \\\n\t\t\t${profile:+--profile $profile} \\\n\t\t\t${auth:+--auth-type $auth} \\\n\t\t\t${username:+--username $username} \\\n\t\t\t${password:+--password $password} \\\n\t\t\t${autoconnect:+--autoconnect})\n\n\t\t# pdh_6 is a numeric value on success\n\t\tif ! [ \"$pdh_6\" -eq \"$pdh_6\" ] 2> /dev/null; then\n\t\t\techo \"Unable to connect IPv6\"\n\t\t\tuqmi -s -d \"$device\" --set-client-id wds,\"$cid_6\" --release-client-id wds > /dev/null 2>&1\n\t\t\tproto_notify_error \"$interface\" CALL_FAILED\n\t\t\treturn 1\n\t\tfi\n\n\t\t# Check data connection state\n\t\tconnstat=$(uqmi -s -d \"$device\" --set-client-id wds,\"$cid_6\" --get-data-status)\n\t\t[ \"$connstat\" == '\"connected\"' ] || {\n\t\t\techo \"No data link!\"\n\t\t\tuqmi -s -d \"$device\" --set-client-id wds,\"$cid_6\" --release-client-id wds > /dev/null 2>&1\n\t\t\tproto_notify_error \"$interface\" CALL_FAILED\n\t\t\treturn 1\n\t\t}\n\t}\n\n\techo \"Setting up $ifname\"\n\tproto_init_update \"$ifname\" 1\n\tproto_set_keep 1\n\tproto_add_data\n\t[ -n \"$pdh_4\" ] && {\n\t\tjson_add_string \"cid_4\" \"$cid_4\"\n\t\tjson_add_string \"pdh_4\" \"$pdh_4\"\n\t}\n\t[ -n \"$pdh_6\" ] && {\n\t\tjson_add_string \"cid_6\" \"$cid_6\"\n\t\tjson_add_string \"pdh_6\" \"$pdh_6\"\n\t}\n\tproto_close_data\n\tproto_send_update \"$interface\"\n\n\tlocal zone=\"$(fw3 -q network \"$interface\" 2>/dev/null)\"\n\n\t[ -n \"$pdh_6\" ] && {\n\t\tif [ -z \"$dhcpv6\" -o \"$dhcpv6\" = 0 ]; then\n\t\t\tjson_load \"$(uqmi -s -d $device --set-client-id wds,$cid_6 --get-current-settings)\"\n\t\t\tjson_select ipv6\n\t\t\tjson_get_var ip_6 ip\n\t\t\tjson_get_var gateway_6 gateway\n\t\t\tjson_get_var dns1_6 dns1\n\t\t\tjson_get_var dns2_6 dns2\n\t\t\tjson_get_var ip_prefix_length ip-prefix-length\n\n\t\t\tproto_init_update \"$ifname\" 1\n\t\t\tproto_set_keep 1\n\t\t\tproto_add_ipv6_address \"$ip_6\" \"128\"\n\t\t\tproto_add_ipv6_prefix \"${ip_6}/${ip_prefix_length}\"\n\t\t\tproto_add_ipv6_route \"$gateway_6\" \"128\"\n\t\t\t[ \"$defaultroute\" = 0 ] || proto_add_ipv6_route \"::0\" 0 \"$gateway_6\" \"\" \"\" \"${ip_6}/${ip_prefix_length}\"\n\t\t\t[ \"$peerdns\" = 0 ] || {\n\t\t\t\tproto_add_dns_server \"$dns1_6\"\n\t\t\t\tproto_add_dns_server \"$dns2_6\"\n\t\t\t}\n\t\t\t[ -n \"$zone\" ] && {\n\t\t\t\tproto_add_data\n\t\t\t\tjson_add_string zone \"$zone\"\n\t\t\t\tproto_close_data\n\t\t\t}\n\t\t\tproto_send_update \"$interface\"\n\t\telse\n\t\t\tjson_init\n\t\t\tjson_add_string name \"${interface}_6\"\n\t\t\tjson_add_string ifname \"@$interface\"\n\t\t\tjson_add_string proto \"dhcpv6\"\n\t\t\t[ -n \"$ip6table\" ] && json_add_string ip6table \"$ip6table\"\n\t\t\tproto_add_dynamic_defaults\n\t\t\t# RFC 7278: Extend an IPv6 /64 Prefix to LAN\n\t\t\tjson_add_string extendprefix 1\n\t\t\t[ -n \"$zone\" ] && json_add_string zone \"$zone\"\n\t\t\tjson_close_object\n\t\t\tubus call network add_dynamic \"$(json_dump)\"\n\t\tfi\n\t}\n\n\t[ -n \"$pdh_4\" ] && {\n\t\tif [ \"$dhcp\" = 0 ]; then\n\t\t\tjson_load \"$(uqmi -s -d $device --set-client-id wds,$cid_4 --get-current-settings)\"\n\t\t\tjson_select ipv4\n\t\t\tjson_get_var ip_4 ip\n\t\t\tjson_get_var gateway_4 gateway\n\t\t\tjson_get_var dns1_4 dns1\n\t\t\tjson_get_var dns2_4 dns2\n\t\t\tjson_get_var subnet_4 subnet\n\n\t\t\tproto_init_update \"$ifname\" 1\n\t\t\tproto_set_keep 1\n\t\t\tproto_add_ipv4_address \"$ip_4\" \"$subnet_4\"\n\t\t\tproto_add_ipv4_route \"$gateway_4\" \"128\"\n\t\t\t[ \"$defaultroute\" = 0 ] || proto_add_ipv4_route \"0.0.0.0\" 0 \"$gateway_4\"\n\t\t\t[ \"$peerdns\" = 0 ] || {\n\t\t\t\tproto_add_dns_server \"$dns1_4\"\n\t\t\t\tproto_add_dns_server \"$dns2_4\"\n\t\t\t}\n\t\t\t[ -n \"$zone\" ] && {\n\t\t\t\tproto_add_data\n\t\t\t\tjson_add_string zone \"$zone\"\n\t\t\t\tproto_close_data\n\t\t\t}\n\t\t\tproto_send_update \"$interface\"\n\t\telse\n\t\t\tjson_init\n\t\t\tjson_add_string name \"${interface}_4\"\n\t\t\tjson_add_string ifname \"@$interface\"\n\t\t\tjson_add_string proto \"dhcp\"\n\t\t\t[ -n \"$ip4table\" ] && json_add_string ip4table \"$ip4table\"\n\t\t\tproto_add_dynamic_defaults\n\t\t\t[ -n \"$zone\" ] && json_add_string zone \"$zone\"\n\t\t\tjson_close_object\n\t\t\tubus call network add_dynamic \"$(json_dump)\"\n\t\tfi\n\t}\n}\n\nqmi_wds_stop() {\n\tlocal cid=\"$1\"\n\tlocal pdh=\"$2\"\n\n\t[ -n \"$cid\" ] || return\n\n\tuqmi -s -d \"$device\" --set-client-id wds,\"$cid\" \\\n\t\t--stop-network 0xffffffff \\\n\t\t--autoconnect > /dev/null 2>&1\n\n\t[ -n \"$pdh\" ] && {\n\t\tuqmi -s -d \"$device\" --set-client-id wds,\"$cid\" \\\n\t\t\t--stop-network \"$pdh\" > /dev/null 2>&1\n\t}\n\n\tuqmi -s -d \"$device\" --set-client-id wds,\"$cid\" \\\n\t\t--release-client-id wds > /dev/null 2>&1\n}\n\nproto_qmi_teardown() {\n\tlocal interface=\"$1\"\n\n\tlocal device cid_4 pdh_4 cid_6 pdh_6\n\tjson_get_vars device\n\n\t[ -n \"$ctl_device\" ] && device=$ctl_device\n\n\techo \"Stopping network $interface\"\n\n\tjson_load \"$(ubus call network.interface.$interface status)\"\n\tjson_select data\n\tjson_get_vars cid_4 pdh_4 cid_6 pdh_6\n\n\tqmi_wds_stop \"$cid_4\" \"$pdh_4\"\n\tqmi_wds_stop \"$cid_6\" \"$pdh_6\"\n\n\tproto_init_update \"*\" 0\n\tproto_send_update \"$interface\"\n}\n\n[ -n \"$INCLUDE_ONLY\" ] || {\n\tadd_protocol qmi\n}\n"
  },
  {
    "path": "package/network/utils/wireguard-tools/Makefile",
    "content": "#\n# Copyright (C) 2016-2019 Jason A. Donenfeld <Jason@zx2c4.com>\n# Copyright (C) 2016 Baptiste Jonglez <openwrt@bitsofnetworks.org>\n# Copyright (C) 2016-2017 Dan Luedtke <mail@danrl.com>\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n\ninclude $(TOPDIR)/rules.mk\ninclude $(INCLUDE_DIR)/kernel.mk\n\nPKG_NAME:=wireguard-tools\n\nPKG_VERSION:=1.0.20210424\nPKG_RELEASE:=$(AUTORELEASE)\n\nPKG_SOURCE:=wireguard-tools-$(PKG_VERSION).tar.xz\nPKG_SOURCE_URL:=https://git.zx2c4.com/wireguard-tools/snapshot/\nPKG_HASH:=b288b0c43871d919629d7e77846ef0b47f8eeaa9ebc9cedeee8233fc6cc376ad\n\nPKG_LICENSE:=GPL-2.0\nPKG_LICENSE_FILES:=COPYING\n\nPKG_BUILD_PARALLEL:=1\n\ninclude $(INCLUDE_DIR)/package.mk\ninclude $(INCLUDE_DIR)/package-defaults.mk\n\nMAKE_PATH:=src\nMAKE_VARS += PLATFORM=linux\n\ndefine Package/wireguard-tools\n  SECTION:=net\n  CATEGORY:=Network\n  SUBMENU:=VPN\n  URL:=https://www.wireguard.com\n  MAINTAINER:=Jason A. Donenfeld <Jason@zx2c4.com>\n  TITLE:=WireGuard userspace control program (wg)\n  DEPENDS:= \\\n\t  +@BUSYBOX_CONFIG_IP \\\n\t  +@BUSYBOX_CONFIG_FEATURE_IP_LINK \\\n\t  +kmod-wireguard\nendef\n\ndefine Package/wireguard-tools/description\n  WireGuard is a novel VPN that runs inside the Linux Kernel and utilizes\n  state-of-the-art cryptography. It aims to be faster, simpler, leaner, and\n  more useful than IPSec, while avoiding the massive headache. It intends to\n  be considerably more performant than OpenVPN.  WireGuard is designed as a\n  general purpose VPN for running on embedded interfaces and super computers\n  alike, fit for many different circumstances. It uses UDP.\n\n  This package provides the userspace control program for WireGuard,\n  `wg(8)`, a netifd protocol helper, and a re-resolve watchdog script.\nendef\n\ndefine Package/wireguard-tools/install\n\t$(INSTALL_DIR) $(1)/usr/bin/\n\t$(INSTALL_BIN) $(PKG_BUILD_DIR)/src/wg $(1)/usr/bin/\n\t$(INSTALL_BIN) ./files/wireguard_watchdog $(1)/usr/bin/\n\t$(INSTALL_DIR) $(1)/lib/netifd/proto/\n\t$(INSTALL_BIN) ./files/wireguard.sh $(1)/lib/netifd/proto/\nendef\n\n$(eval $(call BuildPackage,wireguard-tools))\n"
  },
  {
    "path": "package/network/utils/wireguard-tools/files/wireguard.sh",
    "content": "#!/bin/sh\n# Copyright 2016-2017 Dan Luedtke <mail@danrl.com>\n# Licensed to the public under the Apache License 2.0.\n\nWG=/usr/bin/wg\nif [ ! -x $WG ]; then\n\tlogger -t \"wireguard\" \"error: missing wireguard-tools (${WG})\"\n\texit 0\nfi\n\n[ -n \"$INCLUDE_ONLY\" ] || {\n\t. /lib/functions.sh\n\t. ../netifd-proto.sh\n\tinit_proto \"$@\"\n}\n\nproto_wireguard_init_config() {\n\tproto_config_add_string \"private_key\"\n\tproto_config_add_int \"listen_port\"\n\tproto_config_add_int \"mtu\"\n\tproto_config_add_string \"fwmark\"\n\tavailable=1\n\tno_proto_task=1\n}\n\nproto_wireguard_setup_peer() {\n\tlocal peer_config=\"$1\"\n\n\tlocal disabled\n\tlocal public_key\n\tlocal preshared_key\n\tlocal allowed_ips\n\tlocal route_allowed_ips\n\tlocal endpoint_host\n\tlocal endpoint_port\n\tlocal persistent_keepalive\n\n\tconfig_get_bool disabled \"${peer_config}\" \"disabled\" 0\n\tconfig_get public_key \"${peer_config}\" \"public_key\"\n\tconfig_get preshared_key \"${peer_config}\" \"preshared_key\"\n\tconfig_get allowed_ips \"${peer_config}\" \"allowed_ips\"\n\tconfig_get_bool route_allowed_ips \"${peer_config}\" \"route_allowed_ips\" 0\n\tconfig_get endpoint_host \"${peer_config}\" \"endpoint_host\"\n\tconfig_get endpoint_port \"${peer_config}\" \"endpoint_port\"\n\tconfig_get persistent_keepalive \"${peer_config}\" \"persistent_keepalive\"\n\n\tif [ \"${disabled}\" -eq 1 ]; then\n\t\t# skip disabled peers\n\t\treturn 0\n\tfi\n\n\tif [ -z \"$public_key\" ]; then\n\t\techo \"Skipping peer config $peer_config because public key is not defined.\"\n\t\treturn 0\n\tfi\n\n\techo \"[Peer]\" >> \"${wg_cfg}\"\n\techo \"PublicKey=${public_key}\" >> \"${wg_cfg}\"\n\tif [ \"${preshared_key}\" ]; then\n\t\techo \"PresharedKey=${preshared_key}\" >> \"${wg_cfg}\"\n\tfi\n\tfor allowed_ip in $allowed_ips; do\n\t\techo \"AllowedIPs=${allowed_ip}\" >> \"${wg_cfg}\"\n\tdone\n\tif [ \"${endpoint_host}\" ]; then\n\t\tcase \"${endpoint_host}\" in\n\t\t\t*:*)\n\t\t\t\tendpoint=\"[${endpoint_host}]\"\n\t\t\t\t;;\n\t\t\t*)\n\t\t\t\tendpoint=\"${endpoint_host}\"\n\t\t\t\t;;\n\t\tesac\n\t\tif [ \"${endpoint_port}\" ]; then\n\t\t\tendpoint=\"${endpoint}:${endpoint_port}\"\n\t\telse\n\t\t\tendpoint=\"${endpoint}:51820\"\n\t\tfi\n\t\techo \"Endpoint=${endpoint}\" >> \"${wg_cfg}\"\n\tfi\n\tif [ \"${persistent_keepalive}\" ]; then\n\t\techo \"PersistentKeepalive=${persistent_keepalive}\" >> \"${wg_cfg}\"\n\tfi\n\n\tif [ ${route_allowed_ips} -ne 0 ]; then\n\t\tfor allowed_ip in ${allowed_ips}; do\n\t\t\tcase \"${allowed_ip}\" in\n\t\t\t\t*:*/*)\n\t\t\t\t\tproto_add_ipv6_route \"${allowed_ip%%/*}\" \"${allowed_ip##*/}\"\n\t\t\t\t\t;;\n\t\t\t\t*.*/*)\n\t\t\t\t\tproto_add_ipv4_route \"${allowed_ip%%/*}\" \"${allowed_ip##*/}\"\n\t\t\t\t\t;;\n\t\t\t\t*:*)\n\t\t\t\t\tproto_add_ipv6_route \"${allowed_ip%%/*}\" \"128\"\n\t\t\t\t\t;;\n\t\t\t\t*.*)\n\t\t\t\t\tproto_add_ipv4_route \"${allowed_ip%%/*}\" \"32\"\n\t\t\t\t\t;;\n\t\t\tesac\n\t\tdone\n\tfi\n}\n\nensure_key_is_generated() {\n\tlocal private_key\n\tprivate_key=\"$(uci get network.\"$1\".private_key)\"\n\n\tif [ \"$private_key\" == \"generate\" ]; then\n\t\tlocal ucitmp\n\t\toldmask=\"$(umask)\"\n\t\tumask 077\n\t\tucitmp=\"$(mktemp -d)\"\n\t\tprivate_key=\"$(\"${WG}\" genkey)\"\n\t\tuci -q -t \"$ucitmp\" set network.\"$1\".private_key=\"$private_key\" && \\\n\t\t\tuci -q -t \"$ucitmp\" commit network\n\t\trm -rf \"$ucitmp\"\n\t\tumask \"$oldmask\"\n\tfi\n}\n\nproto_wireguard_setup() {\n\tlocal config=\"$1\"\n\tlocal wg_dir=\"/tmp/wireguard\"\n\tlocal wg_cfg=\"${wg_dir}/${config}\"\n\n\tlocal private_key\n\tlocal listen_port\n\tlocal mtu\n\n\tensure_key_is_generated \"${config}\"\n\n\tconfig_load network\n\tconfig_get private_key \"${config}\" \"private_key\"\n\tconfig_get listen_port \"${config}\" \"listen_port\"\n\tconfig_get addresses \"${config}\" \"addresses\"\n\tconfig_get mtu \"${config}\" \"mtu\"\n\tconfig_get fwmark \"${config}\" \"fwmark\"\n\tconfig_get ip6prefix \"${config}\" \"ip6prefix\"\n\tconfig_get nohostroute \"${config}\" \"nohostroute\"\n\tconfig_get tunlink \"${config}\" \"tunlink\"\n\n\tip link del dev \"${config}\" 2>/dev/null\n\tip link add dev \"${config}\" type wireguard\n\n\tif [ \"${mtu}\" ]; then\n\t\tip link set mtu \"${mtu}\" dev \"${config}\"\n\tfi\n\n\tproto_init_update \"${config}\" 1\n\n\tumask 077\n\tmkdir -p \"${wg_dir}\"\n\techo \"[Interface]\" > \"${wg_cfg}\"\n\techo \"PrivateKey=${private_key}\" >> \"${wg_cfg}\"\n\tif [ \"${listen_port}\" ]; then\n\t\techo \"ListenPort=${listen_port}\" >> \"${wg_cfg}\"\n\tfi\n\tif [ \"${fwmark}\" ]; then\n\t\techo \"FwMark=${fwmark}\" >> \"${wg_cfg}\"\n\tfi\n\tconfig_foreach proto_wireguard_setup_peer \"wireguard_${config}\"\n\n\t# apply configuration file\n\t${WG} setconf ${config} \"${wg_cfg}\"\n\tWG_RETURN=$?\n\n\trm -f \"${wg_cfg}\"\n\n\tif [ ${WG_RETURN} -ne 0 ]; then\n\t\tsleep 5\n\t\tproto_setup_failed \"${config}\"\n\t\texit 1\n\tfi\n\n\tfor address in ${addresses}; do\n\t\tcase \"${address}\" in\n\t\t\t*:*/*)\n\t\t\t\tproto_add_ipv6_address \"${address%%/*}\" \"${address##*/}\"\n\t\t\t\t;;\n\t\t\t*.*/*)\n\t\t\t\tproto_add_ipv4_address \"${address%%/*}\" \"${address##*/}\"\n\t\t\t\t;;\n\t\t\t*:*)\n\t\t\t\tproto_add_ipv6_address \"${address%%/*}\" \"128\"\n\t\t\t\t;;\n\t\t\t*.*)\n\t\t\t\tproto_add_ipv4_address \"${address%%/*}\" \"32\"\n\t\t\t\t;;\n\t\tesac\n\tdone\n\n\tfor prefix in ${ip6prefix}; do\n\t\tproto_add_ipv6_prefix \"$prefix\"\n\tdone\n\n\t# endpoint dependency\n\tif [ \"${nohostroute}\" != \"1\" ]; then\n\t\twg show \"${config}\" endpoints | \\\n\t\tsed -E 's/\\[?([0-9.:a-f]+)\\]?:([0-9]+)/\\1 \\2/' | \\\n\t\twhile IFS=$'\\t ' read -r key address port; do\n\t\t\t[ -n \"${port}\" ] || continue\n\t\t\tproto_add_host_dependency \"${config}\" \"${address}\" \"${tunlink}\"\n\t\tdone\n\tfi\n\n\tproto_send_update \"${config}\"\n}\n\nproto_wireguard_teardown() {\n\tlocal config=\"$1\"\n\tip link del dev \"${config}\" >/dev/null 2>&1\n}\n\n[ -n \"$INCLUDE_ONLY\" ] || {\n\tadd_protocol wireguard\n}\n"
  },
  {
    "path": "package/network/utils/wireguard-tools/files/wireguard_watchdog",
    "content": "#!/bin/sh\n# SPDX-License-Identifier: GPL-2.0\n#\n# Copyright (C) 2018 Aleksandr V. Piskunov <aleksandr.v.piskunov@gmail.com>.\n# Copyright (C) 2015-2018 Jason A. Donenfeld <Jason@zx2c4.com>. All Rights Reserved.\n#\n# This watchdog script tries to re-resolve hostnames for inactive WireGuard peers.\n# Use it for peers with a frequently changing dynamic IP.\n# persistent_keepalive must be set, recommended value is 25 seconds.\n#\n# Run this script from cron every minute:\n# echo '* * * * * /usr/bin/wireguard_watchdog' >> /etc/crontabs/root\n\n\n. /lib/functions.sh\n\ncheck_peer_activity() {\n  local cfg=$1\n  local iface=$2\n  local disabled\n  local public_key\n  local endpoint_host\n  local endpoint_port\n  local persistent_keepalive\n  local last_handshake\n  local idle_seconds\n\n  config_get_bool disabled \"${cfg}\" \"disabled\" 0\n  config_get public_key \"${cfg}\" \"public_key\"\n  config_get endpoint_host \"${cfg}\" \"endpoint_host\"\n  config_get endpoint_port \"${cfg}\" \"endpoint_port\"\n\n  if [ \"${disabled}\" -eq 1 ]; then\n    # skip disabled peers\n    return 0\n  fi\n\n  persistent_keepalive=$(wg show ${iface} persistent-keepalive | grep ${public_key} | awk '{print $2}')\n\n  # only process peers with endpoints and keepalive set\n  [ -z ${endpoint_host} ] && return 0;\n  [ -z ${persistent_keepalive} -o ${persistent_keepalive} = \"off\" ] && return 0;\n\n  # skip IP addresses\n  # check taken from packages/net/ddns-scripts/files/dynamic_dns_functions.sh\n  local IPV4_REGEX=\"[0-9]\\{1,3\\}\\.[0-9]\\{1,3\\}\\.[0-9]\\{1,3\\}\\.[0-9]\\{1,3\\}\"\n  local IPV6_REGEX=\"\\(\\([0-9A-Fa-f]\\{1,4\\}:\\)\\{1,\\}\\)\\(\\([0-9A-Fa-f]\\{1,4\\}\\)\\{0,1\\}\\)\\(\\(:[0-9A-Fa-f]\\{1,4\\}\\)\\{1,\\}\\)\"\n  local IPV4=$(echo ${endpoint_host} | grep -m 1 -o \"$IPV4_REGEX$\")    # do not detect ip in 0.0.0.0.example.com\n  local IPV6=$(echo ${endpoint_host} | grep -m 1 -o \"$IPV6_REGEX\")\n  [ -n \"${IPV4}\" -o -n \"${IPV6}\" ] && return 0;\n\n  # re-resolve endpoint hostname if not responding for too long\n  last_handshake=$(wg show ${iface} latest-handshakes | grep ${public_key} | awk '{print $2}')\n  [ -z ${last_handshake} ] && return 0;\n  idle_seconds=$(($(date +%s)-${last_handshake}))\n  [ ${idle_seconds} -lt 150 ] && return 0;\n  logger -t \"wireguard_monitor\" \"${iface} endpoint ${endpoint_host}:${endpoint_port} is not responding for ${idle_seconds} seconds, trying to re-resolve hostname\"\n  wg set ${iface} peer ${public_key} endpoint \"${endpoint_host}:${endpoint_port}\"\n}\n\n# query ubus for all active wireguard interfaces\nwg_ifaces=$(ubus -S call network.interface dump | jsonfilter -e '@.interface[@.up=true]' | jsonfilter -a -e '@[@.proto=\"wireguard\"].interface' | tr \"\\n\" \" \")\n\n# check every peer in every active wireguard interface\nconfig_load network\nfor iface in $wg_ifaces; do\n  config_foreach check_peer_activity \"wireguard_${iface}\" \"${iface}\"\ndone\n"
  },
  {
    "path": "package/network/utils/wireless-tools/Makefile",
    "content": "#\n# Copyright (C) 2006-2014 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=wireless-tools\nPKG_VERSION:=29\nPKG_MINOR:=\nPKG_RELEASE:=6\n\nPKG_SOURCE:=wireless_tools.$(PKG_VERSION)$(PKG_MINOR).tar.gz\nPKG_SOURCE_URL:=https://hewlettpackard.github.io/wireless-tools\nPKG_HASH:=6fb80935fe208538131ce2c4178221bab1078a1656306bce8909c19887e2e5a1\nTAR_OPTIONS += || true\n\nPKG_MAINTAINER:=Felix Fietkau <nbd@nbd.name>\nPKG_LICENSE:=GPL-2.0\n\nPKG_BUILD_DIR:=$(BUILD_DIR)/wireless_tools.$(PKG_VERSION)\n\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine Package/wireless-tools/Default\n  URL:=http://hplabs.hp.com/personal/Jean_Tourrilhes/Linux/Tools.html\nendef\n\ndefine Package/wireless-tools\n$(call Package/wireless-tools/Default)\n  SECTION:=net\n  CATEGORY:=Base system\n  TITLE:=Tools for manipulating Linux Wireless Extensions\nendef\n\ndefine Package/wireless-tools/description\n This package contains a collection of tools for configuring wireless\n adapters implementing the \"Linux Wireless Extensions\".\nendef\n\ndefine Package/libiw\n$(call Package/wireless-tools/Default)\n  SECTION:=libs\n  CATEGORY:=Libraries\n  TITLE:=Library for manipulating Linux Wireless Extensions\n  ABI_VERSION:=29\nendef\n\ndefine Package/libiw/description\n This package contains a library for manipulating\n \"Linux Wireless Extensions\".\nendef\n\ndefine Build/Compile\n\trm -rf $(PKG_INSTALL_DIR)\n\tmkdir -p $(PKG_INSTALL_DIR)\n\t$(MAKE) -C $(PKG_BUILD_DIR) \\\n\t\t$(TARGET_CONFIGURE_OPTS) \\\n\t\tCFLAGS=\"$(TARGET_CFLAGS) -I.\" \\\n\t\tBUILD_WE_ESSENTIAL=y \\\n\t\tLIBS=\"-lm -Wl,--gc-sections\" \\\n\t\tlibiw.so.$(PKG_VERSION) iwmulticall\n\t$(MAKE) -C $(PKG_BUILD_DIR) \\\n\t\tPREFIX=\"$(PKG_INSTALL_DIR)\" \\\n\t\tINSTALL_DIR=\"$(PKG_INSTALL_DIR)/usr/sbin\" \\\n\t\tINSTALL_LIB=\"$(PKG_INSTALL_DIR)/usr/lib\" \\\n\t\tinstall-iwmulticall\nendef\n\ndefine Build/InstallDev\n\tmkdir -p $(1)/usr/include\n\t$(CP) $(PKG_BUILD_DIR)/{iwlib,wireless}.h $(1)/usr/include/\n\tmkdir -p $(1)/usr/lib\n\t$(CP) $(PKG_BUILD_DIR)/libiw.so* $(1)/usr/lib/\n\t$(LN) libiw.so.$(PKG_VERSION) $(1)/usr/lib/libiw.so\nendef\n\ndefine Package/wireless-tools/install\n\t$(INSTALL_DIR) $(1)/usr/sbin\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/sbin/iwconfig $(1)/usr/sbin/\n\t$(LN) iwconfig $(1)/usr/sbin/iwlist\n\t$(LN) iwconfig $(1)/usr/sbin/iwpriv\nendef\n\ndefine Package/libiw/install\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(CP) $(PKG_BUILD_DIR)/libiw.so.* $(1)/usr/lib/\nendef\n\n$(eval $(call BuildPackage,libiw))\n$(eval $(call BuildPackage,wireless-tools))\n"
  },
  {
    "path": "package/network/utils/wireless-tools/patches/001-debian.patch",
    "content": "--- a/iwlib.c\n+++ b/iwlib.c\n@@ -667,6 +667,7 @@ iw_get_basic_config(int\t\t\tskfd,\n {\n   struct iwreq\t\twrq;\n \n+  memset((char *) &wrq, 0, sizeof(struct iwreq));\n   memset((char *) info, 0, sizeof(struct wireless_config));\n \n   /* Get wireless name */\n--- a/Makefile\n+++ b/Makefile\n@@ -73,8 +73,8 @@ DYNAMIC_LINK= libiw.so\n # Install directories\n INSTALL_DIR= $(PREFIX)/sbin/\n INSTALL_LIB= $(PREFIX)/lib/\n-INSTALL_INC= $(PREFIX)/include/\n-INSTALL_MAN= $(PREFIX)/man/\n+INSTALL_INC= $(PREFIX)/usr/include/\n+INSTALL_MAN= $(PREFIX)/usr/share/man/\n \n # Various commands\n RM = rm -f\n@@ -102,9 +102,9 @@ ifdef BUILD_WE_ESSENTIAL\n endif\n \n # Other flags\n-CFLAGS=-Os -W -Wall -Wstrict-prototypes -Wmissing-prototypes -Wshadow \\\n+#CFLAGS=-Os -W -Wall -Wstrict-prototypes -Wmissing-prototypes -Wshadow \\\n \t-Wpointer-arith -Wcast-qual -Winline -I.\n-#CFLAGS=-O2 -W -Wall -Wstrict-prototypes -I.\n+CFLAGS=-O2 -W -Wall -Wstrict-prototypes -I.\n DEPFLAGS=-MMD\n XCFLAGS=$(CFLAGS) $(DEPFLAGS) $(WARN) $(HEADERS) $(WELIB_FLAG) $(WEDEF_FLAG)\n PICFLAG=-fPIC\n"
  },
  {
    "path": "package/network/utils/wireless-tools/patches/002-fix-iwconfig-power-argument-parsing.patch",
    "content": "--- a/iwconfig.c\n+++ b/iwconfig.c\n@@ -1034,8 +1034,8 @@ set_power_info(int\t\tskfd,\n \twrq.u.power.disabled = 0;\n \n \t/* Is there any value to grab ? */\n-\tvalue = strtod(args[0], &unit);\n-\tif(unit != args[0])\n+\tvalue = strtod(args[i], &unit);\n+\tif(unit != args[i])\n \t  {\n \t    struct iw_range\trange;\n \t    int\t\t\tflags;\n"
  },
  {
    "path": "package/network/utils/wireless-tools/patches/003-we_essential_def.patch",
    "content": "--- a/iwlist.c\n+++ b/iwlist.c\n@@ -58,7 +58,6 @@ typedef struct iw_auth_descr\n  * Maybe this should go in iwlib.c ?\n  */\n \n-#ifndef WE_ESSENTIAL\n #define IW_ARRAY_LEN(x) (sizeof(x)/sizeof((x)[0]))\n \n //static const struct iwmask_name iw_enc_mode_name[] = {\n@@ -161,11 +160,8 @@ static const char *\tiw_ie_key_mgmt_name[\n };\n #define\tIW_IE_KEY_MGMT_NUM\tIW_ARRAY_LEN(iw_ie_key_mgmt_name)\n \n-#endif\t/* WE_ESSENTIAL */\n-\n /************************* WPA SUBROUTINES *************************/\n \n-#ifndef WE_ESSENTIAL\n /*------------------------------------------------------------------*/\n /*\n  * Print all names corresponding to a mask.\n@@ -431,7 +427,6 @@ iw_print_gen_ie(unsigned char *\tbuffer,\n       offset += buffer[offset+1] + 2;\n     }\n }\n-#endif\t/* WE_ESSENTIAL */\n \n /***************************** SCANNING *****************************/\n /*\n@@ -585,12 +580,10 @@ print_scanning_token(struct stream_descr\n \t\t     &event->u.qual, iw_range, has_range);\n       printf(\"                    %s\\n\", buffer);\n       break;\n-#ifndef WE_ESSENTIAL\n     case IWEVGENIE:\n       /* Informations Elements are complex, let's do only some of them */\n       iw_print_gen_ie(event->u.data.pointer, event->u.data.length);\n       break;\n-#endif\t/* WE_ESSENTIAL */\n     case IWEVCUSTOM:\n       {\n \tchar custom[IW_CUSTOM_MAX+1];\n@@ -1302,7 +1295,6 @@ print_pm_info(int\t\tskfd,\n   return(0);\n }\n \n-#ifndef WE_ESSENTIAL\n /************************** TRANSMIT POWER **************************/\n \n /*------------------------------------------------------------------*/\n@@ -1405,6 +1397,7 @@ print_txpower_info(int\t\tskfd,\n   return(0);\n }\n \n+#ifndef WE_ESSENTIAL\n /*********************** RETRY LIMIT/LIFETIME ***********************/\n \n /*------------------------------------------------------------------*/\n@@ -2060,8 +2053,8 @@ static const struct iwlist_entry iwlist_\n   { \"encryption\",\tprint_keys_info,\t0, NULL },\n   { \"keys\",\t\tprint_keys_info,\t0, NULL },\n   { \"power\",\t\tprint_pm_info,\t\t0, NULL },\n-#ifndef WE_ESSENTIAL\n   { \"txpower\",\t\tprint_txpower_info,\t0, NULL },\n+#ifndef WE_ESSENTIAL\n   { \"retry\",\t\tprint_retry_info,\t0, NULL },\n   { \"ap\",\t\tprint_ap_info,\t\t0, NULL },\n   { \"accesspoints\",\tprint_ap_info,\t\t0, NULL },\n--- a/iwconfig.c\n+++ b/iwconfig.c\n@@ -106,16 +106,6 @@ get_info(int\t\t\tskfd,\n     if(wrq.u.data.length > 1)\n       info->has_nickname = 1;\n \n-  if((info->has_range) && (info->range.we_version_compiled > 9))\n-    {\n-      /* Get Transmit Power */\n-      if(iw_get_ext(skfd, ifname, SIOCGIWTXPOW, &wrq) >= 0)\n-\t{\n-\t  info->has_txpower = 1;\n-\t  memcpy(&(info->txpower), &(wrq.u.txpower), sizeof(iwparam));\n-\t}\n-    }\n-\n   /* Get sensitivity */\n   if(iw_get_ext(skfd, ifname, SIOCGIWSENS, &wrq) >= 0)\n     {\n@@ -132,6 +122,17 @@ get_info(int\t\t\tskfd,\n \t  memcpy(&(info->retry), &(wrq.u.retry), sizeof(iwparam));\n \t}\n     }\n+#endif\t/* WE_ESSENTIAL */\n+\n+  if((info->has_range) && (info->range.we_version_compiled > 9))\n+    {\n+      /* Get Transmit Power */\n+      if(iw_get_ext(skfd, ifname, SIOCGIWTXPOW, &wrq) >= 0)\n+\t{\n+\t  info->has_txpower = 1;\n+\t  memcpy(&(info->txpower), &(wrq.u.txpower), sizeof(iwparam));\n+\t}\n+    }\n \n   /* Get RTS threshold */\n   if(iw_get_ext(skfd, ifname, SIOCGIWRTS, &wrq) >= 0)\n@@ -146,7 +147,6 @@ get_info(int\t\t\tskfd,\n       info->has_frag = 1;\n       memcpy(&(info->frag), &(wrq.u.frag), sizeof(iwparam));\n     }\n-#endif\t/* WE_ESSENTIAL */\n \n   return(0);\n }\n@@ -269,7 +269,6 @@ display_info(struct wireless_info *\tinfo\n       printf(\"Bit Rate%c%s   \", (info->bitrate.fixed ? '=' : ':'), buffer);\n     }\n \n-#ifndef WE_ESSENTIAL\n   /* Display the Transmit Power */\n   if(info->has_txpower)\n     {\n@@ -286,6 +285,7 @@ display_info(struct wireless_info *\tinfo\n       printf(\"Tx-Power%c%s   \", (info->txpower.fixed ? '=' : ':'), buffer);\n     }\n \n+#ifndef WE_ESSENTIAL\n   /* Display sensitivity */\n   if(info->has_sens)\n     {\n@@ -340,6 +340,7 @@ display_info(struct wireless_info *\tinfo\n       printf(\"   \");\n       tokens += 5;\t/* Between 3 and 5, depend on flags */\n     }\n+#endif\t/* WE_ESSENTIAL */\n \n   /* Display the RTS threshold */\n   if(info->has_rts)\n@@ -383,7 +384,6 @@ display_info(struct wireless_info *\tinfo\n   /* Formating */\n   if(tokens > 0)\n     printf(\"\\n          \");\n-#endif\t/* WE_ESSENTIAL */\n \n   /* Display encryption information */\n   /* Note : we display only the \"current\" key, use iwlist to list all keys */\n@@ -1196,6 +1196,7 @@ set_nwid_info(int\t\tskfd,\n   /* 1 arg */\n   return(1);\n }\n+#endif\t/* WE_ESSENTIAL */\n \n /*------------------------------------------------------------------*/\n /*\n@@ -1362,6 +1363,7 @@ set_txpower_info(int\t\tskfd,\n   return(i);\n }\n \n+#ifndef WE_ESSENTIAL\n /*------------------------------------------------------------------*/\n /*\n  * Set Sensitivity\n@@ -1459,6 +1461,7 @@ set_retry_info(int\t\tskfd,\n   /* Var args */\n   return(i);\n }\n+#endif\t/* WE_ESSENTIAL */\n \n /*------------------------------------------------------------------*/\n /*\n@@ -1565,6 +1568,7 @@ set_frag_info(int\t\tskfd,\n   return(1);\n }\n \n+#ifndef WE_ESSENTIAL\n /*------------------------------------------------------------------*/\n /*\n  * Set Modulation\n@@ -1719,21 +1723,21 @@ static const struct iwconfig_entry iwcon\n \t\"Set Nickname\",\t\t\t\"NNN\" },\n   { \"nwid\",\t\tset_nwid_info,\t\t1,\tSIOCSIWNWID,\n \t\"Set NWID\",\t\t\t\"{NN|on|off}\" },\n-  { \"ap\",\t\tset_apaddr_info,\t1,\tSIOCSIWAP,\n-\t\"Set AP Address\",\t\t\"{N|off|auto}\" },\n-  { \"txpower\",\t\tset_txpower_info,\t1,\tSIOCSIWTXPOW,\n-\t\"Set Tx Power\",\t\t\t\"{NmW|NdBm|off|auto}\" },\n   { \"sens\",\t\tset_sens_info,\t\t1,\tSIOCSIWSENS,\n \t\"Set Sensitivity\",\t\t\"N\" },\n+  { \"modulation\",\tset_modulation_info,\t1,\tSIOCGIWMODUL,\n+\t\"Set Modulation\",\t\t\"{11g|11a|CCK|OFDMg|...}\" },\n   { \"retry\",\t\tset_retry_info,\t\t1,\tSIOCSIWRETRY,\n \t\"Set Retry Limit\",\t\t\"{limit N|lifetime N}\" },\n+#endif\t/* WE_ESSENTIAL */\n+  { \"ap\",\t\tset_apaddr_info,\t1,\tSIOCSIWAP,\n+\t\"Set AP Address\",\t\t\"{N|off|auto}\" },\n+  { \"txpower\",\t\tset_txpower_info,\t1,\tSIOCSIWTXPOW,\n+\t\"Set Tx Power\",\t\t\t\"{NmW|NdBm|off|auto}\" },\n   { \"rts\",\t\tset_rts_info,\t\t1,\tSIOCSIWRTS,\n \t\"Set RTS Threshold\",\t\t\"{N|auto|fixed|off}\" },\n   { \"frag\",\t\tset_frag_info,\t\t1,\tSIOCSIWFRAG,\n \t\"Set Fragmentation Threshold\",\t\"{N|auto|fixed|off}\" },\n-  { \"modulation\",\tset_modulation_info,\t1,\tSIOCGIWMODUL,\n-\t\"Set Modulation\",\t\t\"{11g|11a|CCK|OFDMg|...}\" },\n-#endif\t/* WE_ESSENTIAL */\n   { \"commit\",\t\tset_commit_info,\t0,\tSIOCSIWCOMMIT,\n \t\"Commit changes\",\t\t\"\" },\n   { NULL, NULL, 0, 0, NULL, NULL },\n--- a/iwmulticall.c\n+++ b/iwmulticall.c\n@@ -81,7 +81,7 @@ extern int\n #define main(args...) main_iwspy(args)\n #include \"iwspy.c\"\n #undef main\n-#endif\t/* WE_ESSENTIAL */\n+#endif\n \n /* Get iwpriv in there. Mandatory for HostAP and some other drivers. */\n #define main(args...) main_iwpriv(args)\n@@ -90,12 +90,14 @@ extern int\n #undef iw_usage\n #undef main\n \n+#ifndef WE_ESSENTIAL\n /* Do we really need iwgetid ? Well, it's not like it's a big one */\n #define main(args...) main_iwgetid(args)\n #define iw_usage(args...) iwgetid_usage(args)\n #include \"iwgetid.c\"\n #undef iw_usage\n #undef main\n+#endif\n \n /* iwevent is useless for most people, don't grab it ? */\n \n@@ -131,11 +133,13 @@ main(int\targc,\n #ifndef WE_ESSENTIAL\n   if(!strcmp(call_name, \"iwspy\"))\n     return(main_iwspy(argc, argv));\n-#endif\t/* WE_ESSENTIAL */\n+#endif\n   if(!strcmp(call_name, \"iwpriv\"))\n     return(main_iwpriv(argc, argv));\n+#ifndef WE_ESSENTIAL\n   if(!strcmp(call_name, \"iwgetid\"))\n     return(main_iwgetid(argc, argv));\n+#endif\n \n   /* Uh oh... Not supposed to come here. */\n   printf(\"iwmulticall : you are not supposed to call me this way...\\n\");\n--- a/iwlib.c\n+++ b/iwlib.c\n@@ -113,6 +113,7 @@ const struct iw_modul_descr\tiw_modul_lis\n   { IW_MODUL_11A, \"11a\", \"IEEE 802.11a (5 GHz, up to 54 Mb/s)\" },\n   { IW_MODUL_11B, \"11b\", \"IEEE 802.11b (2.4 GHz, up to 11 Mb/s)\" },\n \n+#ifndef WE_ESSENTIAL\n   /* Proprietary aggregates */\n   { IW_MODUL_TURBO | IW_MODUL_11A, \"turboa\",\n     \"Atheros turbo mode at 5 GHz (up to 108 Mb/s)\" },\n@@ -120,6 +121,7 @@ const struct iw_modul_descr\tiw_modul_lis\n     \"Atheros turbo mode at 2.4 GHz (up to 108 Mb/s)\" },\n   { IW_MODUL_PBCC | IW_MODUL_11B, \"11+\",\n     \"TI 802.11+ (2.4 GHz, up to 22 Mb/s)\" },\n+#endif\n \n   /* Individual modulations */\n   { IW_MODUL_OFDM_G, \"OFDMg\",\n@@ -129,6 +131,7 @@ const struct iw_modul_descr\tiw_modul_lis\n   { IW_MODUL_DS, \"DS\", \"802.11 Direct Sequence (2.4 GHz, up to 2 Mb/s)\" },\n   { IW_MODUL_FH, \"FH\", \"802.11 Frequency Hopping (2,4 GHz, up to 2 Mb/s)\" },\n \n+#ifndef WE_ESSENTIAL\n   /* Proprietary modulations */\n   { IW_MODUL_TURBO, \"turbo\",\n     \"Atheros turbo mode, channel bonding (up to 108 Mb/s)\" },\n@@ -136,6 +139,7 @@ const struct iw_modul_descr\tiw_modul_lis\n     \"TI 802.11+ higher rates (2.4 GHz, up to 22 Mb/s)\" },\n   { IW_MODUL_CUSTOM, \"custom\",\n     \"Driver specific modulation (check driver documentation)\" },\n+#endif\n };\n \n /* Disable runtime version warning in iw_get_range_info() */\n@@ -440,6 +444,7 @@ iw_print_version_info(const char *\ttooln\n       return -1;\n     }\n \n+#ifndef WE_ESSENTIAL\n   /* Information about the tools themselves */\n   if(toolname != NULL)\n     printf(\"%-8.16s  Wireless-Tools version %d\\n\", toolname, WT_VERSION);\n@@ -452,6 +457,7 @@ iw_print_version_info(const char *\ttooln\n   if(we_kernel_version > 15)\n     printf(\"Kernel    Currently compiled with Wireless Extension v%d.\\n\\n\",\n \t   we_kernel_version);\n+#endif\n \n   /* Version for each device */\n   iw_enum_devices(skfd, &print_iface_version_info, NULL, 0);\n@@ -501,6 +507,7 @@ iw_get_range_info(int\t\tskfd,\n       /* Copy stuff at the right place, ignore extra */\n       memcpy((char *) range, buffer, sizeof(iwrange));\n     }\n+#ifndef WE_ESSENTIAL\n   else\n     {\n       /* Zero unknown fields */\n@@ -574,6 +581,7 @@ iw_get_range_info(int\t\tskfd,\n        * If the driver source has not been updated to the latest, it doesn't\n        * matter because the new fields are set to zero */\n     }\n+#endif\n \n   /* Don't complain twice.\n    * In theory, the test apply to each individual driver, but usually\n@@ -1542,6 +1550,7 @@ iw_print_key(char *\t\t\tbuffer,\n     }\n }\n \n+#ifndef WE_ESSENTIAL\n /*------------------------------------------------------------------*/\n /*\n  * Convert a passphrase into a key\n@@ -1556,6 +1565,7 @@ iw_pass_key(const char *\tinput,\n   fprintf(stderr, \"Error: Passphrase not implemented\\n\");\n   return(-1);\n }\n+#endif\n \n /*------------------------------------------------------------------*/\n /*\n@@ -1578,12 +1588,14 @@ iw_in_key(const char *\t\tinput,\n \tkeylen = IW_ENCODING_TOKEN_MAX;\n       memcpy(key, input + 2, keylen);\n     }\n+#ifndef WE_ESSENTIAL\n   else\n     if(!strncmp(input, \"p:\", 2))\n       {\n \t/* Second case : as a passphrase (PrismII cards) */\n \treturn(iw_pass_key(input + 2, key));\t\t/* skip \"p:\" */\n       }\n+#endif\n     else\n       {\n \tconst char *\tp;\n--- a/Makefile\n+++ b/Makefile\n@@ -195,9 +195,9 @@ install-iwmulticall:: iwmulticall\n \tinstall -m 755 $< $(INSTALL_DIR)/iwconfig\n \t( cd $(INSTALL_DIR) ; \\\n \t  ln -f -s iwconfig iwlist ; \\\n-\t  ln -f -s iwconfig iwspy ; \\\n+\t  $(if $(BUILD_WE_ESSENTIAL),,ln -f -s iwconfig iwspy ;) \\\n \t  ln -f -s iwconfig iwpriv ; \\\n-\t  ln -f -s iwconfig iwgetid )\n+\t  $(if $(BUILD_WE_ESSENTIAL),,ln -f -s iwconfig iwgetid ) )\n \n clean::\n \t$(RM_CMD) \n"
  },
  {
    "path": "package/network/utils/wireless-tools/patches/004-increase_iwlist_buffer.patch",
    "content": "--- a/iwlist.c\n+++ b/iwlist.c\n@@ -792,7 +792,8 @@ print_scanning_info(int\t\tskfd,\n \t  if(iw_get_ext(skfd, ifname, SIOCGIWSCAN, &wrq) < 0)\n \t    {\n \t      /* Check if buffer was too small (WE-17 only) */\n-\t      if((errno == E2BIG) && (range.we_version_compiled > 16))\n+\t      if((errno == E2BIG) && (range.we_version_compiled > 16)\n+\t         && (buflen < 0xFFFF))\n \t\t{\n \t\t  /* Some driver may return very large scan results, either\n \t\t   * because there are many cells, or because they have many\n@@ -808,6 +809,10 @@ print_scanning_info(int\t\tskfd,\n \t\t  else\n \t\t    buflen *= 2;\n \n+                 /* wrq.u.data.length is 16 bits so max size is 65535 */\n+                 if(buflen > 0xFFFF)\n+                   buflen = 0xFFFF;\n+\n \t\t  /* Try again */\n \t\t  goto realloc;\n \t\t}\n@@ -2152,6 +2157,7 @@ main(int\targc,\n   char **args;\t\t\t/* Command arguments */\n   int count;\t\t\t/* Number of arguments */\n   const iwlist_cmd *iwcmd;\n+  int goterr = 0;\n \n   if(argc < 2)\n     iw_usage(1);\n@@ -2199,12 +2205,12 @@ main(int\targc,\n \n   /* do the actual work */\n   if (dev)\n-    (*iwcmd->fn)(skfd, dev, args, count);\n+    goterr = (*iwcmd->fn)(skfd, dev, args, count);\n   else\n     iw_enum_devices(skfd, iwcmd->fn, args, count);\n \n   /* Close the socket. */\n   iw_sockets_close(skfd);\n \n-  return 0;\n+  return goterr;\n }\n"
  },
  {
    "path": "package/network/utils/wpan-tools/Makefile",
    "content": "#\n# Copyright (C) 2015 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=wpan-tools\nPKG_VERSION:=0.7\n\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz\nPKG_SOURCE_URL:=http://wpan.cakelab.org/releases/\nPKG_HASH:=c16de9d7861c2d9b6a4436a0fac730f9f545ee290b92bc770c538ec6a3f22309\n\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine Package/wpan-tools\n  SECTION:=net\n  CATEGORY:=Network\n  TITLE:=cfg802154 interface configuration utility\n  URL:=http://wpan.cakelab.org/\n  DEPENDS:= +libnl\nendef\n\ndefine Package/wpan-tools/install\n\t$(INSTALL_DIR) $(1)/usr/sbin\n\t$(INSTALL_BIN) $(PKG_BUILD_DIR)/src/iwpan $(1)/usr/sbin/\n\t$(INSTALL_BIN) $(PKG_BUILD_DIR)/wpan-ping/wpan-ping $(1)/usr/sbin/\nendef\n\n$(eval $(call BuildPackage,wpan-tools))\n"
  },
  {
    "path": "package/network/utils/wpan-tools/patches/001-src-nl_extras.h-fix-compatibility-with-libnl-3.3.0.patch",
    "content": "From bb522bd584f05e6658d5dba97f48ca018f46394c Mon Sep 17 00:00:00 2001\nFrom: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>\nDate: Sat, 6 May 2017 14:36:08 +0200\nSubject: [PATCH] src/nl_extras.h: fix compatibility with libnl 3.3.0\n\nnl_extras.h defines a set of nla_set_s*() functions if not provided by\nlibnl. They are provided by libnl since version 3.2.26. The test\n(LIBNL_VER_MIC <= 26) was working fine while libnl was in the 3.2.x\nseries, but now that they have incremented the minor version, the\nmicro version was reset to 0, with the latest libnl version being\n3.3.0.\n\nDue to this, the condition (LIBNL_VER_MIC <= 26) is true, and we get\nredefinition errors because nl_extras.h redefines functions already\nprovided by libnl.\n\nThis commit improves the condition so that nl_extras.h provides the\nmissing functions only if the minor version is < 2, or if minor is 2\nand micro is < 26.\n\nSigned-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>\n---\n src/nl_extras.h | 4 ++--\n 1 file changed, 2 insertions(+), 2 deletions(-)\n\n--- a/src/nl_extras.h\n+++ b/src/nl_extras.h\n@@ -1,7 +1,7 @@\n #ifndef __NL_EXTRAS_H\n #define __NL_EXTRAS_H\n \n-#if LIBNL_VER_MIC <= 26\n+#if (LIBNL_VER_MIN < 2) || (LIBNL_VER_MIN == 2) && (LIBNL_VER_MIC <= 26)\n \n #ifndef NLA_S8\n \n@@ -45,6 +45,6 @@ static inline int32_t nla_get_s32(struct\n \n #endif /* NLA_S64 */\n \n-#endif /* LIBNL_VER_MIC */\n+#endif /* LIBNL_VER_* */\n \n #endif /* __NL_EXTRAS_H */\n"
  },
  {
    "path": "package/network/utils/wwan/Makefile",
    "content": "include $(TOPDIR)/rules.mk\n\nPKG_NAME:=wwan\nPKG_VERSION:=2019-04-29\nPKG_RELEASE=5\n\nPKG_LICENSE:=GPL-2.0\nPKG_LICENSE_FILES:=\n\nPKG_MAINTAINER:=John Crispin <john@phrozen.org>\n\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine Package/wwan\n  SECTION:=net\n  CATEGORY:=Network\n  TITLE:=Generic OpenWrt 3G/4G proto handler\nendef\n\ndefine Build/Compile\n\ttrue\nendef\n\ndefine Package/wwan/install\n\t$(INSTALL_DIR) $(1)/lib/netifd/proto/\n\t$(CP) ./files/wwan.sh $(1)/lib/netifd/proto/\n\t$(INSTALL_DIR) $(1)/etc/hotplug.d/usb\n\t$(INSTALL_BIN) ./files/wwan.usb $(1)/etc/hotplug.d/usb/00_wwan.sh\n\t$(INSTALL_DIR) $(1)/etc/hotplug.d/usbmisc\n\t$(INSTALL_BIN) ./files/wwan.usbmisc $(1)/etc/hotplug.d/usbmisc/00_wwan.sh\n\t$(INSTALL_DIR) $(1)/lib/network/wwan/\n\t$(INSTALL_DATA) ./files/data/* $(1)/lib/network/wwan/\n\t#in order to keep the Lede GIT repo free of filenames with colons,\n\t#we name the files xxxx-yyyy\n\t# and rename here after copying to the build directory\n\tshopt -s nullglob ; \\\n\tfor filevar in $(1)/lib/network/wwan/*-* ; \\\n\tdo \\\n\t\tFILENAME=$$$$(basename $$$$filevar) ; \\\n\t\tNEWNAME=$$$${FILENAME//-/:} ; \\\n\t\tmv \"$(1)/lib/network/wwan/$$$$FILENAME\" \"$(1)/lib/network/wwan/$$$$NEWNAME\" ; \\\n\tdone\nendef\n\n$(eval $(call BuildPackage,wwan))\n"
  },
  {
    "path": "package/network/utils/wwan/files/data/0421-03a7",
    "content": "{\n\t\"desc\": \"Nokia C5-00 Mobile phone\",\n\t\"control\": 0,\n\t\"data\": 0,\n\t\"acm\": 1\n}\n"
  },
  {
    "path": "package/network/utils/wwan/files/data/0421-060d",
    "content": "{\n\t\"desc\": \"Nokia CS-10\",\n\t\"control\": 0,\n\t\"data\": 0,\n\t\"acm\": 1\n}\n"
  },
  {
    "path": "package/network/utils/wwan/files/data/0421-060e",
    "content": "{\n\t\"desc\": \"Nokia CS-10\",\n\t\"control\": 0,\n\t\"data\": 0,\n\t\"acm\": 1\n}\n"
  },
  {
    "path": "package/network/utils/wwan/files/data/0421-0612",
    "content": "{\n\t\"desc\": \"Nokia CS-15/CS-18\",\n\t\"control\": 0,\n\t\"data\": 0,\n\t\"acm\": 1\n}\n"
  },
  {
    "path": "package/network/utils/wwan/files/data/0421-0619",
    "content": "{\n\t\"desc\": \"Nokia CS-12\",\n\t\"control\": 0,\n\t\"data\": 0,\n\t\"acm\": 1\n}\n"
  },
  {
    "path": "package/network/utils/wwan/files/data/0421-061e",
    "content": "{\n\t\"desc\": \"Nokia CS-11\",\n\t\"control\": 0,\n\t\"data\": 0,\n\t\"acm\": 1\n}\n"
  },
  {
    "path": "package/network/utils/wwan/files/data/0421-0623",
    "content": "{\n\t\"desc\": \"Nokia CS-17\",\n\t\"control\": 0,\n\t\"data\": 0,\n\t\"acm\": 1\n}\n"
  },
  {
    "path": "package/network/utils/wwan/files/data/0421-0629",
    "content": "{\n\t\"desc\": \"Nokia CS-18\",\n\t\"control\": 0,\n\t\"data\": 0,\n\t\"acm\": 1\n}\n"
  },
  {
    "path": "package/network/utils/wwan/files/data/0421-062d",
    "content": "{\n\t\"desc\": \"Nokia CS-19\",\n\t\"control\": 0,\n\t\"data\": 0,\n\t\"acm\": 1\n}\n"
  },
  {
    "path": "package/network/utils/wwan/files/data/0421-062f",
    "content": "{\n\t\"desc\": \"Nokia CS-19\",\n\t\"control\": 0,\n\t\"data\": 0,\n\t\"acm\": 1\n}\n"
  },
  {
    "path": "package/network/utils/wwan/files/data/0421-0638",
    "content": "{\n\t\"desc\": \"Nokia 21M-02\",\n\t\"control\": 0,\n\t\"data\": 0,\n\t\"acm\": 1\n}\n"
  },
  {
    "path": "package/network/utils/wwan/files/data/05c6-0016",
    "content": "{\n\t\"desc\": \"iBall 3.5G Connect\",\n\t\"control\": 2,\n\t\"data\": 2,\n\t\"generic\": 1\n}\n"
  },
  {
    "path": "package/network/utils/wwan/files/data/05c6-0023",
    "content": "{\n\t\"desc\": \"Leoxsys LN-72V\",\n\t\"control\": 2,\n\t\"data\": 0\n}\n"
  },
  {
    "path": "package/network/utils/wwan/files/data/05c6-00a0",
    "content": "{\n\t\"desc\": \"Axesstel MV241\",\n\t\"control\": 2,\n\t\"data\": 0,\n\t\"generic\": 1\n}\n"
  },
  {
    "path": "package/network/utils/wwan/files/data/05c6-6000",
    "content": "{\n\t\"desc\": \"Siemens SG75\",\n\t\"control\": 2,\n\t\"data\": 0\n}\n"
  },
  {
    "path": "package/network/utils/wwan/files/data/05c6-9000",
    "content": "{\n\t\"desc\": \"Generic Qualcomm\",\n\t\"control\": 1,\n\t\"data\": 2\n}\n"
  },
  {
    "path": "package/network/utils/wwan/files/data/07d1-3e01",
    "content": "{\n\t\"desc\": \"D-Link DWM-152\",\n\t\"control\": 1,\n\t\"data\": 0\n}\n"
  },
  {
    "path": "package/network/utils/wwan/files/data/07d1-3e02",
    "content": "{\n\t\"desc\": \"D-Link DWM-156\",\n\t\"control\": 1,\n\t\"data\": 0\n}\n"
  },
  {
    "path": "package/network/utils/wwan/files/data/07d1-7e11",
    "content": "{\n\t\"desc\": \"D-Link DWM-156\",\n\t\"control\": 1,\n\t\"data\": 2,\n\t\"generic\": 1\n}\n"
  },
  {
    "path": "package/network/utils/wwan/files/data/0af0-4005",
    "content": "{\n\t\"desc\": \"Option GIO711\",\n\t\"type\": \"qmi\"\n}\n"
  },
  {
    "path": "package/network/utils/wwan/files/data/0af0-6901",
    "content": "{\n\t\"desc\": \"Option GI0201\",\n\t\"control\": 1,\n\t\"data\": 0\n}\n"
  },
  {
    "path": "package/network/utils/wwan/files/data/0af0-7201",
    "content": "{\n\t\"desc\": \"Option GTM380\",\n\t\"control\": 1,\n\t\"data\": 0\n}\n"
  },
  {
    "path": "package/network/utils/wwan/files/data/0af0-8120",
    "content": "{\n\t\"desc\": \"Option GTM681W\",\n\t\"type\": \"qmi\"\n}\n"
  },
  {
    "path": "package/network/utils/wwan/files/data/0af0-9200",
    "content": "{\n\t\"desc\": \"Option GTM671WFS\",\n\t\"control\": 2,\n\t\"data\": 2\n}\n"
  },
  {
    "path": "package/network/utils/wwan/files/data/0b3c-c000",
    "content": "{\n\t\"desc\": \"Olivetti Olicard 100\",\n\t\"type\": \"qmi\"\n}\n"
  },
  {
    "path": "package/network/utils/wwan/files/data/0b3c-c001",
    "content": "{\n\t\"desc\": \"Olivetti Olicard 120\",\n\t\"type\": \"qmi\"\n}\n"
  },
  {
    "path": "package/network/utils/wwan/files/data/0b3c-c002",
    "content": "{\n\t\"desc\": \"Olivetti Olicard 140\",\n\t\"type\": \"qmi\"\n}\n"
  },
  {
    "path": "package/network/utils/wwan/files/data/0b3c-c003",
    "content": "{\n\t\"desc\": \"Olivetti Olicard 145\",\n\t\"control\": 0,\n\t\"data\": 4\n}\n"
  },
  {
    "path": "package/network/utils/wwan/files/data/0b3c-c004",
    "content": "{\n\t\"desc\": \"Olivetti Olicard 155\",\n\t\"type\": \"qmi\"\n}\n"
  },
  {
    "path": "package/network/utils/wwan/files/data/0b3c-c005",
    "content": "{\n\t\"desc\": \"Olivetti Olicard 200\",\n\t\"type\": \"qmi\"\n}\n"
  },
  {
    "path": "package/network/utils/wwan/files/data/0b3c-c00a",
    "content": "{\n\t\"desc\": \"Olivetti Olicard 160\",\n\t\"type\": \"qmi\"\n}\n"
  },
  {
    "path": "package/network/utils/wwan/files/data/0b3c-c00b",
    "content": "{\n\t\"desc\": \"Olivetti Olicard 500\",\n\t\"type\": \"qmi\"\n}\n"
  },
  {
    "path": "package/network/utils/wwan/files/data/0bdb-1900",
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  {
    "path": "package/network/utils/wwan/files/data/413c-8181",
    "content": "{\n\t\"desc\": \"Dell 5730\",\n\t\"control\": 1,\n\t\"data\": 0\n}\n"
  },
  {
    "path": "package/network/utils/wwan/files/data/413c-8182",
    "content": "{\n\t\"desc\": \"Dell 5730\",\n\t\"control\": 1,\n\t\"data\": 0\n}\n"
  },
  {
    "path": "package/network/utils/wwan/files/data/413c-8186",
    "content": "{\n\t\"desc\": \"Dell 5620\",\n\t\"type\": \"qmi\"\n}\n"
  },
  {
    "path": "package/network/utils/wwan/files/data/413c-8194",
    "content": "{\n\t\"desc\": \"Dell 5630\",\n\t\"type\": \"qmi\"\n}\n"
  },
  {
    "path": "package/network/utils/wwan/files/data/413c-8195",
    "content": "{\n\t\"desc\": \"Dell 5800\",\n\t\"type\": \"qmi\"\n}\n"
  },
  {
    "path": "package/network/utils/wwan/files/data/413c-8196",
    "content": "{\n\t\"desc\": \"Dell 5800v2\",\n\t\"type\": \"qmi\"\n}\n"
  },
  {
    "path": "package/network/utils/wwan/files/data/413c-819b",
    "content": "{\n\t\"desc\": \"Dell 5804\",\n\t\"control\": 1,\n\t\"data\": 0\n}\n"
  },
  {
    "path": "package/network/utils/wwan/files/wwan.sh",
    "content": "#!/bin/sh\n\n. /lib/functions.sh\n. ../netifd-proto.sh\ninit_proto \"$@\"\n\nINCLUDE_ONLY=1\n\nctl_device=\"\"\ndat_device=\"\"\n\nproto_mbim_setup() { echo \"wwan[$$] mbim proto is missing\"; }\nproto_qmi_setup() { echo \"wwan[$$] qmi proto is missing\"; }\nproto_ncm_setup() { echo \"wwan[$$] ncm proto is missing\"; }\nproto_3g_setup() { echo \"wwan[$$] 3g proto is missing\"; }\nproto_directip_setup() { echo \"wwan[$$] directip proto is missing\"; }\n\n[ -f ./mbim.sh ] && . ./mbim.sh\n[ -f ./ncm.sh ] && . ./ncm.sh\n[ -f ./qmi.sh ] && . ./qmi.sh\n[ -f ./3g.sh ] && { . ./ppp.sh; . ./3g.sh; }\n[ -f ./directip.sh ] && . ./directip.sh\n\nproto_wwan_init_config() {\n\tavailable=1\n\tno_device=1\n\n\tproto_config_add_string apn\n\tproto_config_add_string auth\n\tproto_config_add_string username\n\tproto_config_add_string password\n\tproto_config_add_string pincode\n\tproto_config_add_string delay\n\tproto_config_add_string modes\n\tproto_config_add_string bus\n}\n\nproto_wwan_setup() {\n\tlocal driver usb devicename desc bus\n\n\tjson_get_vars bus\n\n\tif [ -L \"/sys/bus/usb/devices/${bus}\" ]; then\n\t\tif [ -f \"/sys/bus/usb/devices/${bus}/idVendor\" ] \\\n\t\t\t&& [ -f \"/sys/bus/usb/devices/${bus}/idProduct\" ]; then\n\t\t\tlocal vendor product\n\t\t\tvendor=$(cat /sys/bus/usb/devices/${bus}/idVendor)\n\t\t\tproduct=$(cat /sys/bus/usb/devices/${bus}/idProduct)\n\t\t\t[ -f /lib/network/wwan/$vendor:$product ] && {\n\t\t\t\tusb=/lib/network/wwan/$vendor:$product\n\t\t\t\tdevicename=$bus\n\t\t\t}\n\t\telse\n\t\t\techo \"wwan[$$]\" \"Specified usb bus ${bus} was not found\"\n\t\t\tproto_notify_error \"$interface\" NO_USB\n\t\t\tproto_block_restart \"$interface\"\n\t\t\treturn 1\n\t\tfi\n\telse\n\t\techo \"wwan[$$]\" \"Searching for a valid wwan usb device...\"\n\t\tfor a in $(ls /sys/bus/usb/devices); do\n\t\t\tlocal vendor product\n\t\t\t[ -z \"$usb\" -a -f /sys/bus/usb/devices/$a/idVendor -a  -f /sys/bus/usb/devices/$a/idProduct ] || continue\n\t\t\tvendor=$(cat /sys/bus/usb/devices/$a/idVendor)\n\t\t\tproduct=$(cat /sys/bus/usb/devices/$a/idProduct)\n\t\t\t[ -f /lib/network/wwan/$vendor:$product ] && {\n\t\t\t\tusb=/lib/network/wwan/$vendor:$product\n\t\t\t\tdevicename=$a\n\t\t\t}\n\t\tdone\n\tfi\n\n\techo \"wwan[$$]\" \"Using wwan usb device on bus $devicename\"\n\n\t[ -n \"$usb\" ] && {\n\t\tlocal old_cb control data\n\n\t\tjson_set_namespace wwan old_cb\n\t\tjson_init\n\t\tjson_load \"$(cat \"$usb\")\"\n\t\tjson_select\n\t\tjson_get_vars desc control data\n\t\tjson_set_namespace \"$old_cb\"\n\n\t\t[ -n \"$control\" -a -n \"$data\" ] && {\n\t\t\tttys=$(ls -d /sys/bus/usb/devices/$devicename/${devicename}*/tty?* /sys/bus/usb/devices/$devicename/${devicename}*/tty/tty?* | sed \"s/.*\\///g\" | tr \"\\n\" \" \")\n\t\t\tctl_device=/dev/$(echo $ttys | cut -d\" \" -f $((control + 1)))\n\t\t\tdat_device=/dev/$(echo $ttys | cut -d\" \" -f $((data + 1)))\n\t\t\tdriver=comgt\n\t\t}\n\t}\n\n\t[ -z \"$ctl_device\" ] && for net in $(ls /sys/class/net/ | grep -e wwan -e usb); do\n\t\t[ -z \"$ctl_device\" ] || continue\n\t\t[ -n \"$bus\" ] && {\n\t\t\t[ $(readlink /sys/class/net/$net | grep $bus) ] || continue\n\t\t}\n\t\tdriver=$(grep DRIVER /sys/class/net/$net/device/uevent | cut -d= -f2)\n\t\tcase \"$driver\" in\n\t\tqmi_wwan|cdc_mbim)\n\t\t\tctl_device=/dev/$(ls /sys/class/net/$net/device/usbmisc)\n\t\t\t;;\n\t\tsierra_net|cdc_ether|*cdc_ncm)\n\t\t\tctl_device=/dev/$(cd /sys/class/net/$net/; find ../../../ -name ttyUSB* |xargs -n1 basename | head -n1)\n\t\t\t;;\n\t\t*) continue;;\n\t\tesac\n\t\techo \"wwan[$$]\" \"Using proto:$proto device:$ctl_device iface:$net desc:$desc\"\n\tdone\n\n\t[ -n \"$ctl_device\" ] || {\n\t\techo \"wwan[$$]\" \"No valid device was found\"\n\t\tproto_notify_error \"$interface\" NO_DEVICE\n\t\tproto_block_restart \"$interface\"\n\t\treturn 1\n\t}\n\n\tuci_set_state network \"$interface\" driver \"$driver\"\n\tuci_set_state network \"$interface\" ctl_device \"$ctl_device\"\n\tuci_set_state network \"$interface\" dat_device \"$dat_device\"\n\n\tcase $driver in\n\tqmi_wwan)\t\tproto_qmi_setup $@ ;;\n\tcdc_mbim)\t\tproto_mbim_setup $@ ;;\n\tsierra_net)\t\tproto_directip_setup $@ ;;\n\tcomgt)\t\t\tproto_3g_setup $@ ;;\n\tcdc_ether|*cdc_ncm)\tproto_ncm_setup $@ ;;\n\tesac\n}\n\nproto_wwan_teardown() {\n\tlocal interface=$1\n\tlocal driver=$(uci_get_state network \"$interface\" driver)\n\tctl_device=$(uci_get_state network \"$interface\" ctl_device)\n\tdat_device=$(uci_get_state network \"$interface\" dat_device)\n\n\tcase $driver in\n\tqmi_wwan)\t\tproto_qmi_teardown $@ ;;\n\tcdc_mbim)\t\tproto_mbim_teardown $@ ;;\n\tsierra_net)\t\tproto_directip_teardown $@ ;;\n\tcomgt)\t\t\tproto_3g_teardown $@ ;;\n\tcdc_ether|*cdc_ncm)\tproto_ncm_teardown $@ ;;\n\tesac\n}\n\nadd_protocol wwan\n"
  },
  {
    "path": "package/network/utils/wwan/files/wwan.usb",
    "content": "#!/bin/sh\n\n[ \"$ACTION\" = add -a \"$DEVTYPE\" = usb_device ] || exit 0\n\n. /lib/functions.sh\n. /lib/netifd/netifd-proto.sh\n\nvid=$(cat /sys$DEVPATH/idVendor)\npid=$(cat /sys$DEVPATH/idProduct)\n[ -f \"/lib/network/wwan/$vid:$pid\" ] || exit 0\n\nfind_wwan_iface() {\n\tlocal cfg=\"$1\"\n\tlocal proto\n\tconfig_get proto \"$cfg\" proto\n\t[ \"$proto\" = wwan ] || return 0\n\tproto_set_available \"$cfg\" 1\n\tifup $cfg\n\texit 0\n}\n\nconfig_load network\nconfig_foreach find_wwan_iface interface\n"
  },
  {
    "path": "package/network/utils/wwan/files/wwan.usbmisc",
    "content": "#!/bin/sh\n\n[ \"$ACTION\" = add ] || [ \"$ACTION\" = remove ] || exit 0\n[ \"${DEVNAME/[0-9]/}\" = cdc-wdm ] || exit 0\n\n. /lib/functions.sh\n. /lib/netifd/netifd-proto.sh\n\nfind_wwan_iface() {\n\tlocal cfg=\"$1\"\n\n\tlocal proto device\n\tconfig_get proto \"$cfg\" proto\n\tconfig_get device \"$cfg\" device\n\n\t[ \"$proto\" = wwan ] || [ \"$proto\" = mbim ] || [ \"$proto\" = qmi ] || [ \"$proto\" = ncm ] || return 0\n\t[ -z \"$device\" -a \"$proto\" = wwan ] || [ \"$device\" = \"/dev/$DEVNAME\" ] || return 0\n\tif [ \"$ACTION\" = add ]; then\n\t\tproto_set_available \"$cfg\" 1\n\tfi\n\tif [ \"$ACTION\" = remove ]; then\n\t\tproto_set_available \"$cfg\" 0\n\tfi\n\texit 0\n}\n\nconfig_load network\nconfig_foreach find_wwan_iface interface\n"
  },
  {
    "path": "package/system/ca-certificates/Makefile",
    "content": "#\n# Copyright (C) 2006-2017 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=ca-certificates\nPKG_VERSION:=20211016\nPKG_RELEASE:=1\nPKG_MAINTAINER:=\n\nPKG_SOURCE:=$(PKG_NAME)_$(PKG_VERSION).tar.xz\nPKG_SOURCE_URL:=@DEBIAN/pool/main/c/ca-certificates\nPKG_HASH:=2ae9b6dc5f40c25d6d7fe55e07b54f12a8967d1955d3b7b2f42ee46266eeef88\nPKG_INSTALL:=1\n\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine Package/ca-certificates\n  SECTION:=base\n  CATEGORY:=Base system\n  TITLE:=System CA certificates\n  PKGARCH:=all\n  PROVIDES:=ca-certs\nendef\n\ndefine Package/ca-bundle\n  SECTION:=base\n  CATEGORY:=Base system\n  TITLE:=System CA certificates as a bundle\n  PKGARCH:=all\n  PROVIDES:=ca-certs\nendef\n\ndefine Build/Prepare\n\t$(DECOMPRESS_CMD) $(HOST_TAR) -C $(PKG_BUILD_DIR) $(TAR_OPTIONS)\n\t$(Build/Patch)\nendef\n\nMAKE_PATH := work\n\ndefine Build/Install\n\tmkdir -p \\\n\t\t$(PKG_INSTALL_DIR)/usr/sbin \\\n\t\t$(PKG_INSTALL_DIR)/usr/share/ca-certificates\n\t$(call Build/Install/Default,)\nendef\n\ndefine Package/ca-certificates/install\n\t$(INSTALL_DIR) $(1)/etc/ssl/certs\n\t$(INSTALL_DATA) $(PKG_INSTALL_DIR)/usr/share/ca-certificates/*/*.crt $(1)/etc/ssl/certs/\n\n\tfor CERTFILE in `ls -1 $(1)/etc/ssl/certs`; do \\\n\t\tHASH=`openssl x509 -hash -noout -in $(1)/etc/ssl/certs/$$$$CERTFILE` ; \\\n\t\tSUFFIX=0 ; \\\n\t\twhile [ -h \"$(1)/etc/ssl/certs/$$$$HASH.$$$$SUFFIX\" ]; do \\\n\t\t\tlet \"SUFFIX += 1\" ; \\\n\t\tdone ; \\\n\t\t$(LN) \"$$$$CERTFILE\" \"$(1)/etc/ssl/certs/$$$$HASH.$$$$SUFFIX\" ; \\\n\tdone\nendef\n\ndefine Package/ca-bundle/install\n\t$(INSTALL_DIR) $(1)/etc/ssl/certs\n\tcat $(PKG_INSTALL_DIR)/usr/share/ca-certificates/*/*.crt >$(1)/etc/ssl/certs/ca-certificates.crt\n\t$(LN) /etc/ssl/certs/ca-certificates.crt $(1)/etc/ssl/cert.pem\nendef\n$(eval $(call BuildPackage,ca-bundle))\n$(eval $(call BuildPackage,ca-certificates))\n"
  },
  {
    "path": "package/system/ca-certificates/patches/0001-ca-certificates-fix-python3-cryptography-woes-in-cer.patch",
    "content": "From 3c51cb5ff1d0db41fb3288fb555c7e7055cf3e86 Mon Sep 17 00:00:00 2001\nFrom: Christian Lamparter <chunkeey@gmail.com>\nDate: Wed, 1 Dec 2021 14:41:31 +0100\nSubject: [PATCH] ca-certificates: fix python3-cryptography woes in\n certdata2pem.py\n\nreverts the code portion of the Debian's ca-certificate\ncommit 033d52259172 (\"mozilla/certdata2pem.py: print a warning for expired certificates.\")\n\nIt broke builds with the popular Ubuntu 20.04 (focal) releases.\nThis was due to them shipping with an older python3-cryptography\nversion which is not compatible.\n\nMore concerns were raised by jow- as well:\n\"We don't want the build to depend on the local system time anyway.\"\n\nReported-by: Chen Minqiang <ptpt52@gmail.com>\nReported-by: Shane Synan <digitalcircuit36939@gmail.com>\nSigned-off-by: Christian Lamparter <chunkeey@gmail.com>\n---\n--- a/work/mozilla/certdata2pem.py\n+++ b/work/mozilla/certdata2pem.py\n@@ -21,16 +21,12 @@\n # USA.\n \n import base64\n-import datetime\n import os.path\n import re\n import sys\n import textwrap\n import io\n \n-from cryptography import x509\n-\n-\n objects = []\n \n # Dirty file parser.\n@@ -121,13 +117,6 @@ for obj in objects:\n     if obj['CKA_CLASS'] == 'CKO_CERTIFICATE':\n         if not obj['CKA_LABEL'] in trust or not trust[obj['CKA_LABEL']]:\n             continue\n-\n-        cert = x509.load_der_x509_certificate(obj['CKA_VALUE'])\n-        if cert.not_valid_after < datetime.datetime.now():\n-            print('!'*74)\n-            print('Trusted but expired certificate found: %s' % obj['CKA_LABEL'])\n-            print('!'*74)\n-\n         bname = obj['CKA_LABEL'][1:-1].replace('/', '_')\\\n                                       .replace(' ', '_')\\\n                                       .replace('(', '=')\\\n"
  },
  {
    "path": "package/system/fstools/Makefile",
    "content": "#\n# Copyright (C) 2014-2015 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=fstools\nPKG_RELEASE:=$(AUTORELEASE)\n\nPKG_SOURCE_PROTO:=git\nPKG_SOURCE_URL=$(PROJECT_GIT)/project/fstools.git\nPKG_MIRROR_HASH:=c6239a75f6a3b5b010a48d195006550b0e2154f5b22611484c4979f552c0da7d\nPKG_SOURCE_DATE:=2022-05-03\nPKG_SOURCE_VERSION:=9e11b3723ce30b9b8c94ad7d15072a10cf13c0b4\nCMAKE_INSTALL:=1\n\nPKG_LICENSE:=GPL-2.0\nPKG_LICENSE_FILES:=\n\nPKG_USE_MIPS16:=0\nPKG_FLAGS:=nonshared\n\nPKG_BUILD_DEPENDS := util-linux\nPKG_CONFIG_DEPENDS := CONFIG_NAND_SUPPORT CONFIG_FSTOOLS_UBIFS_EXTROOT\n\nPKG_MAINTAINER:=John Crispin <john@phrozen.org>\n\ninclude $(INCLUDE_DIR)/package.mk\ninclude $(INCLUDE_DIR)/cmake.mk\n\nTARGET_LDFLAGS += $(if $(CONFIG_USE_GLIBC),-lrt)\nCMAKE_OPTIONS += $(if $(CONFIG_FSTOOLS_UBIFS_EXTROOT),-DCMAKE_UBIFS_EXTROOT=y)\nCMAKE_OPTIONS += $(if $(CONFIG_FSTOOLS_OVL_MOUNT_FULL_ACCESS_TIME),-DCMAKE_OVL_MOUNT_FULL_ACCESS_TIME=y)\nCMAKE_OPTIONS += $(if $(CONFIG_FSTOOLS_OVL_MOUNT_COMPRESS_ZLIB),-DCMAKE_OVL_MOUNT_COMPRESS_ZLIB=y)\n\ndefine Package/fstools\n  SECTION:=base\n  CATEGORY:=Base system\n  DEPENDS:=+ubox +USE_GLIBC:librt +NAND_SUPPORT:ubi-utils\n  TITLE:=OpenWrt filesystem tools\n  MENU:=1\nendef\n\ndefine Package/fstools/config\n\tconfig FSTOOLS_UBIFS_EXTROOT\n\t\tdepends on PACKAGE_fstools\n\t\tdepends on NAND_SUPPORT\n\t\tbool \"Support extroot functionality with UBIFS\"\n\t\tdefault y\n\t\thelp\n\t\t\tThis option makes it possible to use extroot functionality if the root filesystem resides on an UBIFS partition\n\n\tconfig FSTOOLS_OVL_MOUNT_FULL_ACCESS_TIME\n\t\tdepends on PACKAGE_fstools\n\t\tbool \"Full access time accounting\"\n\t\tdefault n\n\t\thelp\n\t\t\tThis option enables the full access time accounting (warning: it will increase the flash writes).\n\n\tconfig FSTOOLS_OVL_MOUNT_COMPRESS_ZLIB\n\t\tdepends on PACKAGE_fstools\n\t\tbool \"Compress using zlib\"\n\t\tdefault n\n\t\thelp\n\t\t\tThis option enables the compression using zlib on the storage device.\nendef\n\ndefine Package/snapshot-tool\n  SECTION:=base\n  CATEGORY:=Base system\n  TITLE:=rootfs snapshoting tool\n  DEPENDS:=+libubox +fstools\nendef\n\ndefine Package/block-mount\n  SECTION:=base\n  CATEGORY:=Base system\n  TITLE:=Block device mounting and checking\n  DEPENDS:=+ubox +libubox +libuci +libblobmsg-json +libjson-c\nendef\n\ndefine Package/blockd\n  SECTION:=base\n  CATEGORY:=Base system\n  TITLE:=Block device automounting\n  DEPENDS:=+block-mount +fstools +libubus +kmod-fs-autofs4 +libblobmsg-json +libjson-c\nendef\n\ndefine Package/fstools/install\n\t$(INSTALL_DIR) $(1)/sbin $(1)/lib\n\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/sbin/{mount_root,jffs2reset} $(1)/sbin/\n\t$(INSTALL_DATA) $(PKG_INSTALL_DIR)/usr/lib/libfstools.so $(1)/lib/\n\t$(LN) jffs2reset $(1)/sbin/jffs2mark\nendef\n\ndefine Package/snapshot-tool/install\n\t$(INSTALL_DIR) $(1)/sbin\n\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/sbin/snapshot_tool $(1)/sbin/\n\t$(INSTALL_BIN) ./files/snapshot $(1)/sbin/\nendef\n\ndefine Package/block-mount/install\n\t$(INSTALL_DIR) $(1)/sbin $(1)/lib $(1)/usr/sbin $(1)/etc/hotplug.d/block $(1)/etc/init.d/ $(1)/etc/uci-defaults/\n\n\t$(INSTALL_BIN) ./files/fstab.init $(1)/etc/init.d/fstab\n\t$(INSTALL_CONF) ./files/fstab.default $(1)/etc/uci-defaults/10-fstab\n\t$(INSTALL_CONF) ./files/mount.hotplug $(1)/etc/hotplug.d/block/10-mount\n\t$(INSTALL_CONF) ./files/media-change.hotplug  $(1)/etc/hotplug.d/block/00-media-change\n\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/sbin/block $(1)/sbin/\n\t$(INSTALL_DATA) $(PKG_INSTALL_DIR)/usr/lib/libblkid-tiny.so $(1)/lib/\n\t$(LN) ../../sbin/block $(1)/usr/sbin/swapon\n\t$(LN) ../../sbin/block $(1)/usr/sbin/swapoff\n\nendef\n\ndefine Package/blockd/install\n\t$(INSTALL_DIR) $(1)/sbin $(1)/etc/init.d/\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/sbin/blockd $(1)/sbin/\n\t$(INSTALL_BIN) ./files/blockd.init $(1)/etc/init.d/blockd\nendef\n\ndefine Build/InstallDev\n\t$(INSTALL_DIR) $(1)/usr/include\n\t$(CP) $(PKG_INSTALL_DIR)/usr/include/*.h $(1)/usr/include/\n\t$(INSTALL_DIR) $(1)/usr/lib/\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/libubi-utils.a $(1)/usr/lib/\nendef\n\n$(eval $(call BuildPackage,fstools))\n$(eval $(call BuildPackage,snapshot-tool))\n$(eval $(call BuildPackage,block-mount))\n$(eval $(call BuildPackage,blockd))\n"
  },
  {
    "path": "package/system/fstools/files/blockd.init",
    "content": "#!/bin/sh /etc/rc.common\n\nSTART=80\n\nUSE_PROCD=1\nPROG=/sbin/blockd\n\nservice_triggers() {\n\tprocd_add_reload_trigger \"fstab\"\n}\n\nreload_service() {\n\tblock autofs start\n}\n\nstart_service() {\n\tprocd_open_instance\n\tprocd_set_param command \"$PROG\"\n\tprocd_set_param watch block\n\tprocd_set_param respawn\n\tprocd_close_instance\n}\n"
  },
  {
    "path": "package/system/fstools/files/fstab.default",
    "content": "[ ! -f /etc/config/fstab ] && ( block detect > /etc/config/fstab )\nexit 0\n"
  },
  {
    "path": "package/system/fstools/files/fstab.init",
    "content": "#!/bin/sh /etc/rc.common\n# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2013-2020 OpenWrt.org\n\nSTART=11\n\nboot() {\n\t/sbin/block mount\n}\n\nstart() {\n\treturn 0\n}\n\nrestart() {\n\treturn 0\n}\n\nstop() {\n\t/sbin/block umount\n}\n"
  },
  {
    "path": "package/system/fstools/files/media-change.hotplug",
    "content": "[ -n \"$DISK_MEDIA_CHANGE\" ] && /sbin/block info\n\nif [ \"$ACTION\" = \"add\" -a \"$DEVTYPE\" = \"disk\" ]; then\n\tcase \"$DEVNAME\" in\n\t\tmtd*) : ;;\n\t\t*) echo 2000 > /sys/block/$DEVNAME/events_poll_msecs ;;\n\tesac\nfi\n"
  },
  {
    "path": "package/system/fstools/files/mount.hotplug",
    "content": "[ \"$ACTION\" = \"add\" -o \"$ACTION\" = \"remove\" ] && /sbin/block hotplug\n"
  },
  {
    "path": "package/system/fstools/files/snapshot",
    "content": "#!/bin/sh\n# Copyright (C) 2014 OpenWrt.org\n\n\ndo_snapshot_unpack() {\n\techo \"- snapshot -\"\n\tmkdir /tmp/snapshot\n\tcd /tmp/snapshot\n\tsnapshot_tool read\n\tblock=`ls block*.tar.gz 2> /dev/null`\n\t[ -z \"$block\" ] || for a in $block; do\n\t\ttar xzf $a -C /\n\t\trm -f $a\n\tdone\n}\n\ndo_config_unpack() {\n\techo \"- config -\"\n\tsnapshot_tool config_read\n\t[ -f /tmp/config.tar.gz ] && {\n\t\ttar xzf /tmp/config.tar.gz -C /\n\t\trm -f /tmp/config.tar.gz\n\t}\n}\n\ndo_snapshot_push() {\n\tcd /volatile/upper\n\ttar czf /tmp/snapshot.tar.gz *\n\tsnapshot_tool write\n\treboot\n}\n\ndo_config_push() {\n\tcd /volatile/upper\n\ttar czf /tmp/config.tar.gz *\n\tsnapshot_tool config_write\n}\n\ndo_snapshot_upgrade() {\n\topkg update\n\t[ $? -eq 0 ] || exit 1\n\n\topkg list-upgradable\n\t[ $? -eq 0 ] || exit 2\n\n\tUPDATES=`opkg list-upgradable | cut -d\" \" -f1`\n\t[ -z \"${UPDATES}\" ] && exit 0\n\n\topkg upgrade ${UPDATES}\n\t[ $? -eq 0 ] || exit 3\n\n\tdo_snapshot_push\n\tsleep 5\n\treboot\n\tsleep 10\n}\n\ndo_convert_jffs2() {\n\tsnapshot_tool write\n\tsleep 2\n\treboot -f\n}\n\ndo_convert() {\n\t. /lib/functions.sh\n\t. /lib/upgrade/common.sh\n\n\tcd /overlay/upper\n\ttar czf /tmp/snapshot.tar.gz *\n\n\tinstall_bin /sbin/upgraded\n\tubus call system sysupgrade \"{\n\t\t\\\"prefix\\\": \\\"$RAM_ROOT\\\",\n\t\t\\\"path\\\": \\\"\\\",\n\t\t\\\"command\\\": \\\". /sbin/snapshot; do_convert_jffs2\\\"\n\t}\"\n}\n\n[ -n \"$(cat /proc/mounts|grep /overlay|grep jffs2)\" ] && {\ncase $1 in\nconvert)\n\tdo_convert\n\t;;\nesac\n}\n\n[ -d /volatile/upper ] && {\ncase $1 in\npush)\n\tdo_snapshot_push\n\t;;\nconfig)\n\tdo_config_push\n\t;;\nupgrade)\n\tdo_snapshot_upgrade\n\t;;\ninfo)\n\tsnapshot_tool info\n\t;;\nesac\n}\n\n[ \"$SNAPSHOT\" = \"magic\" ] && {\ncase $1 in\nunpack)\n\tdo_snapshot_unpack\n\t;;\nconfig_unpack)\n\tdo_config_unpack\n\t;;\nesac\n}\n"
  },
  {
    "path": "package/system/fwtool/Makefile",
    "content": "#\n# Copyright (C) Felix Fietkau <nbd@nbd.name>\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=fwtool\nPKG_RELEASE:=1\n\nPKG_SOURCE_PROTO:=git\nPKG_SOURCE_URL=$(PROJECT_GIT)/project/fwtool.git\nPKG_SOURCE_DATE:=2019-11-12\nPKG_SOURCE_VERSION:=8f7fe925ca205c8e8e2d0d1b16218c1e148d5173\nPKG_MIRROR_HASH:=ff68e77397a7ba8f497aae9a6d1f89e196c89391a8d5ed0b81c4eafb889ba744\nCMAKE_INSTALL:=1\n\nPKG_FLAGS:=nonshared\n\nPKG_LICENSE:=GPL-2.0\nPKG_MAINTAINER := Felix Fietkau <nbd@nbd.name>\nPKG_BUILD_DEPENDS := fwtool/host\n\ninclude $(INCLUDE_DIR)/package.mk\ninclude $(INCLUDE_DIR)/host-build.mk\ninclude $(INCLUDE_DIR)/cmake.mk\n\nHOST_BUILD_PREFIX:=$(STAGING_DIR_HOST)\n\ndefine Package/fwtool\n  SECTION:=utils\n  CATEGORY:=Base system\n  TITLE:=Utility for appending and extracting firmware metadata and signatures\nendef\n\ndefine Host/Install\n\t$(INSTALL_BIN) $(HOST_BUILD_DIR)/fwtool $(1)/bin/\nendef\n\ndefine Package/fwtool/install\n\t$(INSTALL_DIR) $(1)/usr/bin\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/bin/fwtool $(1)/usr/bin/\nendef\n\n$(eval $(call HostBuild))\n$(eval $(call BuildPackage,fwtool))\n"
  },
  {
    "path": "package/system/gpio-cdev/nu801/Makefile",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=nu801\nPKG_RELEASE:=1\n\nPKG_SOURCE_PROTO:=git\nPKG_SOURCE_URL:=https://github.com/chunkeey/nu801.git\nPKG_SOURCE_VERSION:=d9942c0ceb949080b93366a9431028de3608e535\nPKG_MIRROR_HASH:=859be7dec96d2a0d6ee8b80c6f1a703384940d19caeeb74a4ac0a961b2a985db\nPKG_MAINTAINER:=Christian Lamparter <chunkeey@gmail.com>\nPKG_LICENSE:=GPL-3.0-or-later\nPKG_LICENSE_FILES:=LICENSE\n\ninclude $(INCLUDE_DIR)/package.mk\ninclude $(INCLUDE_DIR)/cmake.mk\n\ndefine Package/nu801\n  SECTION:=utils\n  CATEGORY:=Utilities\n  SUBMENU:=Userspace GPIO Drivers\n  DEPENDS:=@TARGET_x86\n  KCONFIG:=CONFIG_GPIO_CDEV=y\n  TITLE:=NU801 LED Driver\nendef\n\ndefine Package/nu801/description\nThis package contains a userspace driver to power the NUMEN Tech. NU801 LED Driver.\nendef\n\ndefine Package/nu801/install\n\t$(INSTALL_DIR) $(1)/usr/sbin\n\t$(INSTALL_BIN) $(PKG_BUILD_DIR)/nu801 $(1)/usr/sbin/\n\t$(INSTALL_DIR) $(1)/etc/init.d\n\t$(INSTALL_BIN) ./files/nu801.init $(1)/etc/init.d/nu801\nendef\n\n$(eval $(call BuildPackage,nu801))\n"
  },
  {
    "path": "package/system/gpio-cdev/nu801/files/nu801.init",
    "content": "#!/bin/sh /etc/rc.common\n# SPDX-License-Identifier: GPL-2.0-or-later\n\nSTART=11\n\nboot() {\n\t. /lib/functions.sh\n\t/usr/sbin/nu801 \"$(board_name)\"\n\n\t# Because this is a userspace driver, we need to trigger diag.sh after\n\t# we start the driver, but before boot is complete so we blink.\n\t. /etc/diag.sh\n\tset_state preinit_regular\n}\n"
  },
  {
    "path": "package/system/iucode-tool/Makefile",
    "content": "#\n# Copyright (C) 2018 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=iucode-tool\nPKG_VERSION:=2.3.1\nPKG_RELEASE:=2\n\nPKG_SOURCE:=iucode-tool_$(PKG_VERSION).tar.xz\nPKG_SOURCE_URL:=https://gitlab.com/iucode-tool/releases/raw/latest\nPKG_HASH:=12b88efa4d0d95af08db05a50b3dcb217c0eb2bfc67b483779e33d498ddb2f95\n\nPKG_BUILD_DEPENDS:=USE_UCLIBC:argp-standalone USE_MUSL:argp-standalone\nHOST_BUILD_DEPENDS:=HOST_OS_MACOS:argp-standalone/host\n\nPKG_MAINTAINER:=Zoltan HERPAI <wigyori@uid0.hu>\nPKG_LICENSE:=GPL-2.0\n\nPKG_FLAGS:=nonshared\n\nPKG_INSTALL:=1\n\ninclude $(INCLUDE_DIR)/package.mk\ninclude $(INCLUDE_DIR)/host-build.mk\n\ndefine Package/iucode-tool\n  SECTION:=utils\n  CATEGORY:=Base system\n  URL:=$(PKG_SOURCE_URL)\n  DEPENDS:=@TARGET_x86\n  TITLE:=Intel microcode loader\nendef\n\ndefine Package/iucode-tool/install\n\t$(INSTALL_DIR) $(1)/lib/firmware\n\t$(INSTALL_DIR) $(1)/usr/bin\n\t$(INSTALL_BIN) $(PKG_BUILD_DIR)/iucode_tool $(1)/usr/bin/\nendef\n\n# List of build hosts with working cpuid.h\nIUT_NATIVE_HOST_OS_ARCH := \\\n\tlinux/x86_64 linux/amd64 linux/i386 linux/i686\n\nIUT_HOST_OS_ARCH := $(call tolower,$(HOST_OS))/$(HOST_ARCH)\n\n# Use cpuid.h compat header if build host does not have working cpuid.h\nifeq ($(filter $(IUT_HOST_OS_ARCH),$(IUT_NATIVE_HOST_OS_ARCH)),)\nHOST_CFLAGS += \\\n\t-I$(HOST_BUILD_DIR)/cpuid-compat\nendif\n\ndefine Host/Install\n\t$(INSTALL_BIN) $(HOST_BUILD_DIR)/iucode_tool $(STAGING_DIR_HOST)/bin/iucode_tool\nendef\n\n$(eval $(call HostBuild))\n$(eval $(call BuildPackage,iucode-tool))\n"
  },
  {
    "path": "package/system/iucode-tool/patches/200_add-cpuid-compatibility-header-to-build-on-non-x86.patch",
    "content": "From a21e75da32c0016f1575ea29775565934a67660d Mon Sep 17 00:00:00 2001\nFrom: \"Sergey V. Lobanov\" <sergey@lobanov.in>\nDate: Sat, 5 Feb 2022 13:10:23 +0300\nSubject: [PATCH] Add cpuid compatibility header to build on non-x86 hosts\n\nSigned-off-by: Sergey V. Lobanov <sergey@lobanov.in>\n---\n cpuid-compat/cpuid.h | 17 +++++++++++++++++\n 1 file changed, 17 insertions(+)\n create mode 100644 cpuid-compat/cpuid.h\n\n--- /dev/null\n+++ b/cpuid-compat/cpuid.h\n@@ -0,0 +1,17 @@\n+// SPDX-License-Identifier: GPL-2.0-or-later\n+/*\n+ *  cpuid compatibility header to build iucode-tool on non-x86 hosts\n+ *\n+ *  Copyright (C) 2022       Sergey V. Lobanov <sergey@lobanov.in>\n+ */\n+\n+#ifdef __APPLE__\n+# include <limits.h>\n+#endif\n+\n+static __inline int __get_cpuid (unsigned int leaf,\n+              unsigned int *eax, unsigned int *ebx,\n+              unsigned int *ecx, unsigned int *edx)\n+{\n+    return 0;\n+}\n"
  },
  {
    "path": "package/system/mtd/Makefile",
    "content": "#\n# Copyright (C) 2006-2012 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\ninclude $(INCLUDE_DIR)/kernel.mk\n\nPKG_NAME:=mtd\nPKG_RELEASE:=26\n\nPKG_BUILD_DIR := $(KERNEL_BUILD_DIR)/$(PKG_NAME)\nSTAMP_PREPARED := $(STAMP_PREPARED)_$(call confvar,CONFIG_MTD_REDBOOT_PARTS)\n\nPKG_LICENSE:=GPL-2.0+\nPKG_LICENSE_FILES:=\n\nPKG_FLAGS:=nonshared\n\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine Package/mtd\n  SECTION:=utils\n  CATEGORY:=Base system\n  DEPENDS:=+libubox\n  TITLE:=Update utility for trx firmware images\nendef\n\ndefine Package/mtd/description\n This package contains an utility useful to upgrade from other firmware or \n older OpenWrt releases.\nendef\n\ntarget=$(firstword $(subst -, ,$(BOARD)))\n\nMAKE_FLAGS += TARGET=\"$(target)\"\nTARGET_CFLAGS += -Dtarget_$(target)=1 -Wall -flto\nTARGET_LDFLAGS += -flto=jobserver\n\nifdef CONFIG_MTD_REDBOOT_PARTS\n  MAKE_FLAGS += FIS_SUPPORT=1\n  TARGET_CFLAGS += -DFIS_SUPPORT=1\nendif\n\ndefine Package/mtd/install\n\t$(INSTALL_DIR) $(1)/sbin\n\t$(INSTALL_BIN) $(PKG_BUILD_DIR)/mtd $(1)/sbin/\nendef\n\n$(eval $(call BuildPackage,mtd))\n"
  },
  {
    "path": "package/system/mtd/src/Makefile",
    "content": "CC = gcc\nCFLAGS += -Wall\nLDFLAGS += -lubox\n\nobj = mtd.o jffs2.o crc32.o md5.o\nobj.seama = seama.o md5.o\nobj.wrg = wrg.o md5.o\nobj.wrgg = wrgg.o md5.o\nobj.tpl = tpl_ramips_recoveryflag.o\nobj.ath79 = $(obj.seama) $(obj.wrgg)\nobj.gemini = $(obj.wrgg)\nobj.brcm = trx.o\nobj.bcm47xx = $(obj.brcm)\nobj.bcm53xx = $(obj.brcm) $(obj.seama)\nobj.mediatek = $(obj.brcm)\nobj.bcm63xx = imagetag.o\nobj.bmips = imagetag.o\nobj.ramips = $(obj.seama) $(obj.tpl) $(obj.wrg) linksys_bootcount.o\nobj.mvebu = linksys_bootcount.o\nobj.kirkwood = linksys_bootcount.o\nobj.ipq806x = linksys_bootcount.o\nobj.ipq40xx = linksys_bootcount.o\n\nifdef FIS_SUPPORT\n  obj += fis.o\nendif\n\nmtd: $(obj) $(obj.$(TARGET))\nclean:\n\trm -f *.o jffs2\n"
  },
  {
    "path": "package/system/mtd/src/crc32.c",
    "content": "/*\n *  COPYRIGHT (C) 1986 Gary S. Brown.  You may use this program, or\n *  code or tables extracted from it, as desired without restriction.\n *\n *  First, the polynomial itself and its table of feedback terms.  The\n *  polynomial is\n *  X^32+X^26+X^23+X^22+X^16+X^12+X^11+X^10+X^8+X^7+X^5+X^4+X^2+X^1+X^0\n *\n *  Note that we take it \"backwards\" and put the highest-order term in\n *  the lowest-order bit.  The X^32 term is \"implied\"; the LSB is the\n *  X^31 term, etc.  The X^0 term (usually shown as \"+1\") results in\n *  the MSB being 1\n *\n *  Note that the usual hardware shift register implementation, which\n *  is what we're using (we're merely optimizing it by doing eight-bit\n *  chunks at a time) shifts bits into the lowest-order term.  In our\n *  implementation, that means shifting towards the right.  Why do we\n *  do it this way?  Because the calculated CRC must be transmitted in\n *  order from highest-order term to lowest-order term.  UARTs transmit\n *  characters in order from LSB to MSB.  By storing the CRC this way\n *  we hand it to the UART in the order low-byte to high-byte; the UART\n *  sends each low-bit to hight-bit; and the result is transmission bit\n *  by bit from highest- to lowest-order term without requiring any bit\n *  shuffling on our part.  Reception works similarly\n *\n *  The feedback terms table consists of 256, 32-bit entries.  Notes\n *\n *      The table can be generated at runtime if desired; code to do so\n *      is shown later.  It might not be obvious, but the feedback\n *      terms simply represent the results of eight shift/xor opera\n *      tions for all combinations of data and CRC register values\n *\n *      The values must be right-shifted by eight bits by the \"updcrc\n *      logic; the shift must be unsigned (bring in zeroes).  On some\n *      hardware you could probably optimize the shift in assembler by\n *      using byte-swap instructions\n *      polynomial $edb88320\n */\n\n#include <stdint.h>\n\nconst uint32_t crc32_table[256] = {\n\t0x00000000L, 0x77073096L, 0xee0e612cL, 0x990951baL, 0x076dc419L,\n\t0x706af48fL, 0xe963a535L, 0x9e6495a3L, 0x0edb8832L, 0x79dcb8a4L,\n\t0xe0d5e91eL, 0x97d2d988L, 0x09b64c2bL, 0x7eb17cbdL, 0xe7b82d07L,\n\t0x90bf1d91L, 0x1db71064L, 0x6ab020f2L, 0xf3b97148L, 0x84be41deL,\n\t0x1adad47dL, 0x6ddde4ebL, 0xf4d4b551L, 0x83d385c7L, 0x136c9856L,\n\t0x646ba8c0L, 0xfd62f97aL, 0x8a65c9ecL, 0x14015c4fL, 0x63066cd9L,\n\t0xfa0f3d63L, 0x8d080df5L, 0x3b6e20c8L, 0x4c69105eL, 0xd56041e4L,\n\t0xa2677172L, 0x3c03e4d1L, 0x4b04d447L, 0xd20d85fdL, 0xa50ab56bL,\n\t0x35b5a8faL, 0x42b2986cL, 0xdbbbc9d6L, 0xacbcf940L, 0x32d86ce3L,\n\t0x45df5c75L, 0xdcd60dcfL, 0xabd13d59L, 0x26d930acL, 0x51de003aL,\n\t0xc8d75180L, 0xbfd06116L, 0x21b4f4b5L, 0x56b3c423L, 0xcfba9599L,\n\t0xb8bda50fL, 0x2802b89eL, 0x5f058808L, 0xc60cd9b2L, 0xb10be924L,\n\t0x2f6f7c87L, 0x58684c11L, 0xc1611dabL, 0xb6662d3dL, 0x76dc4190L,\n\t0x01db7106L, 0x98d220bcL, 0xefd5102aL, 0x71b18589L, 0x06b6b51fL,\n\t0x9fbfe4a5L, 0xe8b8d433L, 0x7807c9a2L, 0x0f00f934L, 0x9609a88eL,\n\t0xe10e9818L, 0x7f6a0dbbL, 0x086d3d2dL, 0x91646c97L, 0xe6635c01L,\n\t0x6b6b51f4L, 0x1c6c6162L, 0x856530d8L, 0xf262004eL, 0x6c0695edL,\n\t0x1b01a57bL, 0x8208f4c1L, 0xf50fc457L, 0x65b0d9c6L, 0x12b7e950L,\n\t0x8bbeb8eaL, 0xfcb9887cL, 0x62dd1ddfL, 0x15da2d49L, 0x8cd37cf3L,\n\t0xfbd44c65L, 0x4db26158L, 0x3ab551ceL, 0xa3bc0074L, 0xd4bb30e2L,\n\t0x4adfa541L, 0x3dd895d7L, 0xa4d1c46dL, 0xd3d6f4fbL, 0x4369e96aL,\n\t0x346ed9fcL, 0xad678846L, 0xda60b8d0L, 0x44042d73L, 0x33031de5L,\n\t0xaa0a4c5fL, 0xdd0d7cc9L, 0x5005713cL, 0x270241aaL, 0xbe0b1010L,\n\t0xc90c2086L, 0x5768b525L, 0x206f85b3L, 0xb966d409L, 0xce61e49fL,\n\t0x5edef90eL, 0x29d9c998L, 0xb0d09822L, 0xc7d7a8b4L, 0x59b33d17L,\n\t0x2eb40d81L, 0xb7bd5c3bL, 0xc0ba6cadL, 0xedb88320L, 0x9abfb3b6L,\n\t0x03b6e20cL, 0x74b1d29aL, 0xead54739L, 0x9dd277afL, 0x04db2615L,\n\t0x73dc1683L, 0xe3630b12L, 0x94643b84L, 0x0d6d6a3eL, 0x7a6a5aa8L,\n\t0xe40ecf0bL, 0x9309ff9dL, 0x0a00ae27L, 0x7d079eb1L, 0xf00f9344L,\n\t0x8708a3d2L, 0x1e01f268L, 0x6906c2feL, 0xf762575dL, 0x806567cbL,\n\t0x196c3671L, 0x6e6b06e7L, 0xfed41b76L, 0x89d32be0L, 0x10da7a5aL,\n\t0x67dd4accL, 0xf9b9df6fL, 0x8ebeeff9L, 0x17b7be43L, 0x60b08ed5L,\n\t0xd6d6a3e8L, 0xa1d1937eL, 0x38d8c2c4L, 0x4fdff252L, 0xd1bb67f1L,\n\t0xa6bc5767L, 0x3fb506ddL, 0x48b2364bL, 0xd80d2bdaL, 0xaf0a1b4cL,\n\t0x36034af6L, 0x41047a60L, 0xdf60efc3L, 0xa867df55L, 0x316e8eefL,\n\t0x4669be79L, 0xcb61b38cL, 0xbc66831aL, 0x256fd2a0L, 0x5268e236L,\n\t0xcc0c7795L, 0xbb0b4703L, 0x220216b9L, 0x5505262fL, 0xc5ba3bbeL,\n\t0xb2bd0b28L, 0x2bb45a92L, 0x5cb36a04L, 0xc2d7ffa7L, 0xb5d0cf31L,\n\t0x2cd99e8bL, 0x5bdeae1dL, 0x9b64c2b0L, 0xec63f226L, 0x756aa39cL,\n\t0x026d930aL, 0x9c0906a9L, 0xeb0e363fL, 0x72076785L, 0x05005713L,\n\t0x95bf4a82L, 0xe2b87a14L, 0x7bb12baeL, 0x0cb61b38L, 0x92d28e9bL,\n\t0xe5d5be0dL, 0x7cdcefb7L, 0x0bdbdf21L, 0x86d3d2d4L, 0xf1d4e242L,\n\t0x68ddb3f8L, 0x1fda836eL, 0x81be16cdL, 0xf6b9265bL, 0x6fb077e1L,\n\t0x18b74777L, 0x88085ae6L, 0xff0f6a70L, 0x66063bcaL, 0x11010b5cL,\n\t0x8f659effL, 0xf862ae69L, 0x616bffd3L, 0x166ccf45L, 0xa00ae278L,\n\t0xd70dd2eeL, 0x4e048354L, 0x3903b3c2L, 0xa7672661L, 0xd06016f7L,\n\t0x4969474dL, 0x3e6e77dbL, 0xaed16a4aL, 0xd9d65adcL, 0x40df0b66L,\n\t0x37d83bf0L, 0xa9bcae53L, 0xdebb9ec5L, 0x47b2cf7fL, 0x30b5ffe9L,\n\t0xbdbdf21cL, 0xcabac28aL, 0x53b39330L, 0x24b4a3a6L, 0xbad03605L,\n\t0xcdd70693L, 0x54de5729L, 0x23d967bfL, 0xb3667a2eL, 0xc4614ab8L,\n\t0x5d681b02L, 0x2a6f2b94L, 0xb40bbe37L, 0xc30c8ea1L, 0x5a05df1bL,\n\t0x2d02ef8dL\n};\n"
  },
  {
    "path": "package/system/mtd/src/crc32.h",
    "content": "#ifndef CRC32_H\n#define CRC32_H\n\n#include <stdint.h>\n\nextern const uint32_t crc32_table[256];\n\n/* Return a 32-bit CRC of the contents of the buffer. */\n\nstatic inline uint32_t\ncrc32(uint32_t val, const void *ss, int len)\n{\n\tconst unsigned char *s = ss;\n\twhile (--len >= 0)\n\t\tval = crc32_table[(val ^ *s++) & 0xff] ^ (val >> 8);\n\treturn val;\n}\n\nstatic inline unsigned int crc32buf(char *buf, size_t len)\n{\n\treturn crc32(0xFFFFFFFF, buf, len);\n}\n\n\n\n#endif\n"
  },
  {
    "path": "package/system/mtd/src/fis.c",
    "content": "/*\n * FIS table updating code for mtd\n *\n * Copyright (C) 2009 Felix Fietkau <nbd@nbd.name>\n *\n * This program is free software; you can redistribute it and/or\n * modify it under the terms of the GNU General Public License v2\n * as published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n * GNU General Public License for more details.\n */\n#include <sys/mman.h>\n#include <stdint.h>\n#include <stdlib.h>\n#include <string.h>\n#include <unistd.h>\n#include <stdio.h>\n#include \"crc32.h\"\n#include \"mtd.h\"\n#include \"fis.h\"\n\nstruct fis_image_hdr {\n\tunsigned char name[16];\n\tuint32_t flash_base;\n\tuint32_t mem_base;\n\tuint32_t size;\n\tuint32_t entry_point;\n\tuint32_t data_length;\n} __attribute__((packed));\n\nstruct fis_image_crc {\n\tuint32_t desc;\n\tuint32_t file;\n} __attribute__((packed));\n\nstruct fis_image_desc {\n\tstruct fis_image_hdr hdr;\n\tchar _pad[256 - sizeof(struct fis_image_hdr) - sizeof(struct fis_image_crc)];\n\tstruct fis_image_crc crc;\n} __attribute__((packed));\n\nstatic int fis_fd = -1;\nstatic struct fis_image_desc *fis_desc;\nstatic int fis_erasesize = 0;\n\nstatic void\nfis_close(void)\n{\n\tif (fis_desc)\n\t\tmunmap(fis_desc, fis_erasesize);\n\n\tif (fis_fd >= 0)\n\t\tclose(fis_fd);\n\n\tfis_fd = -1;\n\tfis_desc = NULL;\n}\n\nstatic struct fis_image_desc *\nfis_open(void)\n{\n\tstruct fis_image_desc *desc;\n\n\tif (fis_fd >= 0)\n\t\tfis_close();\n\n\tfis_fd = mtd_check_open(\"FIS directory\");\n\tif (fis_fd < 0)\n\t\tgoto error;\n\n\tclose(fis_fd);\n\tfis_fd = mtd_open(\"FIS directory\", true);\n\tif (fis_fd < 0)\n\t\tgoto error;\n\n\tfis_erasesize = erasesize;\n\tdesc = mmap(NULL, erasesize, PROT_READ|PROT_WRITE, MAP_SHARED|MAP_LOCKED, fis_fd, 0);\n\tif (desc == MAP_FAILED)\n\t\tgoto error;\n\n\tfis_desc = desc;\n\treturn desc;\n\nerror:\n\tfis_close();\n\treturn NULL;\n}\n\nint\nfis_validate(struct fis_part *old, int n_old, struct fis_part *new, int n_new)\n{\n\tstruct fis_image_desc *desc;\n\tvoid *end;\n\tint found = 0;\n\tint i;\n\n\tdesc = fis_open();\n\tif (!desc)\n\t\treturn -1;\n\n\tfor (i = 0; i < n_new - 1; i++) {\n\t\tif (!new[i].size) {\n\t\t\tfprintf(stderr, \"FIS error: only the last partition can detect the size automatically\\n\");\n\t\t\ti = -1;\n\t\t\tgoto done;\n\t\t}\n\t}\n\n\tend = desc;\n\tend = (char *) end + fis_erasesize;\n\twhile ((void *) desc < end) {\n\t\tif (!desc->hdr.name[0] || (desc->hdr.name[0] == 0xff))\n\t\t\tbreak;\n\n\t\tfor (i = 0; i < n_old; i++) {\n\t\t\tif (!strncmp((char *) desc->hdr.name, (char *) old[i].name, sizeof(desc->hdr.name))) {\n\t\t\t\tfound++;\n\t\t\t\tgoto next;\n\t\t\t}\n\t\t}\nnext:\n\t\tdesc++;\n\t\tcontinue;\n\t}\n\n\tif (found == n_old)\n\t\ti = 1;\n\telse\n\t\ti = -1;\n\ndone:\n\tfis_close();\n\treturn i;\n}\n\nint\nfis_remap(struct fis_part *old, int n_old, struct fis_part *new, int n_new)\n{\n\tstruct fis_image_desc *first = NULL;\n\tstruct fis_image_desc *last = NULL;\n\tstruct fis_image_desc *first_fb = NULL;\n\tstruct fis_image_desc *last_fb = NULL;\n\tstruct fis_image_desc *desc;\n\tstruct fis_part *part;\n\tuint32_t offset = 0, size = 0;\n\tchar *start, *end, *tmp;\n\tint i;\n\n\tdesc = fis_open();\n\tif (!desc)\n\t\treturn -1;\n\n\tif (!quiet)\n\t\tfprintf(stderr, \"Updating FIS table... \\n\");\n\n\tstart = (char *) desc;\n\tend = (char *) desc + fis_erasesize;\n\twhile ((char *) desc < end) {\n\t\tif (!desc->hdr.name[0] || (desc->hdr.name[0] == 0xff))\n\t\t\tbreak;\n\n\t\t/* update max offset */\n\t\tif (offset < desc->hdr.flash_base)\n\t\t\toffset = desc->hdr.flash_base;\n\n\t\tfor (i = 0; i < n_old; i++) {\n\t\t\tif (!strncmp((char *) desc->hdr.name, (char *) old[i].name, sizeof(desc->hdr.name))) {\n\t\t\t\tlast = desc;\n\t\t\t\tif (!first)\n\t\t\t\t\tfirst = desc;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t\tdesc++;\n\t}\n\tdesc--;\n\n\tfirst_fb = first;\n\tlast_fb = last;\n\n\tif (first_fb->hdr.flash_base > last_fb->hdr.flash_base) {\n\t\tfirst_fb = last;\n\t\tlast_fb = first;\n\t}\n\n\t/* determine size of available space */\n\tdesc = (struct fis_image_desc *) start;\n\twhile ((char *) desc < end) {\n\t\tif (!desc->hdr.name[0] || (desc->hdr.name[0] == 0xff))\n\t\t\tbreak;\n\n\t\tif (desc->hdr.flash_base > last_fb->hdr.flash_base &&\n\t\t    desc->hdr.flash_base < offset)\n\t\t\toffset = desc->hdr.flash_base;\n\n\t\tdesc++;\n\t}\n\tdesc--;\n\n\tsize = offset - first_fb->hdr.flash_base;\n\n\tlast++;\n\tdesc = first + n_new;\n\toffset = first_fb->hdr.flash_base;\n\n\tif (desc != last) {\n\t\tif (desc > last)\n\t\t\ttmp = (char *) desc;\n\t\telse\n\t\t\ttmp = (char *) last;\n\n\t\tmemmove(desc, last, end - tmp);\n\t\tif (desc < last) {\n\t\t\ttmp = end - (last - desc) * sizeof(struct fis_image_desc);\n\t\t\tmemset(tmp, 0xff, tmp - end);\n\t\t}\n\t}\n\n\tfor (part = new, desc = first; desc < first + n_new; desc++, part++) {\n\t\tmemset(desc, 0, sizeof(struct fis_image_desc));\n\t\tmemcpy(desc->hdr.name, part->name, sizeof(desc->hdr.name));\n\t\tdesc->crc.desc = 0;\n\t\tdesc->crc.file = part->crc;\n\n\t\tdesc->hdr.flash_base = offset;\n\t\tdesc->hdr.mem_base = part->loadaddr;\n\t\tdesc->hdr.entry_point = part->loadaddr;\n\t\tdesc->hdr.size = (part->size > 0) ? part->size : size;\n\t\tdesc->hdr.data_length = (part->length > 0) ? part->length :\n\t\t\t\t\t\t\t\tdesc->hdr.size;\n\t\toffset += desc->hdr.size;\n\t\tsize -= desc->hdr.size;\n\t}\n\n\tmsync(fis_desc, fis_erasesize, MS_SYNC|MS_INVALIDATE);\n\tfis_close();\n\n\treturn 0;\n}\n"
  },
  {
    "path": "package/system/mtd/src/fis.h",
    "content": "#ifndef __FIS_H\n#define __FIS_H\n\nstruct fis_part {\n\tunsigned char name[16];\n\tuint32_t offset;\n\tuint32_t loadaddr;\n\tuint32_t size;\n\tuint32_t length;\n\tuint32_t crc;\n};\n\nint fis_validate(struct fis_part *old, int n_old, struct fis_part *new, int n_new);\nint fis_remap(struct fis_part *old, int n_old, struct fis_part *new, int n_new);\n\n#endif\n"
  },
  {
    "path": "package/system/mtd/src/imagetag.c",
    "content": "/*\n * imagetag.c\n *\n * Copyright (C) 2005 Mike Baker\n * Copyright (C) 2008 Felix Fietkau <nbd@nbd.name>\n * Copyrigth (C) 2010 Daniel Dickinson <openwrt@cshore.neomailbox.net>\n *\n * This program is free software; you can redistribute it and/or\n * modify it under the terms of the GNU General Public License\n * as published by the Free Software Foundation; either version 2\n * of the License, or (at your option) any later version.\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n * GNU General Public License for more details.\n *\n * You should have received a copy of the GNU General Public License\n * along with this program; if not, write to the Free Software\n * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.\n */\n\n#include <stdio.h>\n#include <stdlib.h>\n#include <stddef.h>\n#include <unistd.h>\n#include <fcntl.h>\n#include <sys/mman.h>\n#include <sys/stat.h>\n#include <string.h>\n#include <errno.h>\n\n#include <sys/ioctl.h>\n#include <mtd/mtd-user.h>\n\n#include \"mtd.h\"\n#include \"crc32.h\"\n\n#define TAGVER_LEN\t\t4\t/* Length of Tag Version */\n#define TAGLAYOUT_LEN\t\t4\t/* Length of FlashLayoutVer */\n#define SIG1_LEN\t\t20\t/* Company Signature 1 Length */\n#define SIG2_LEN\t\t14\t/* Company Signature 2 Length */\n#define BOARDID_LEN\t\t16\t/* Length of BoardId */\n#define ENDIANFLAG_LEN\t\t2\t/* Endian Flag Length */\n#define CHIPID_LEN\t\t6\t/* Chip Id Length */\n#define IMAGE_LEN\t\t10\t/* Length of Length Field */\n#define ADDRESS_LEN\t\t12\t/* Length of Address field */\n#define DUALFLAG_LEN\t\t2\t/* Dual Image flag Length */\n#define INACTIVEFLAG_LEN\t2\t/* Inactie Flag Length */\n#define RSASIG_LEN\t\t20\t/* Length of RSA Signature in tag */\n#define TAGINFO1_LEN\t\t30\t/* Length of vendor information field1 in tag */\n#define FLASHLAYOUTVER_LEN\t4\t/* Length of Flash Layout Version String tag */\n#define TAGINFO2_LEN\t\t16\t/* Length of vendor information field2 in tag */\n#define ALTTAGINFO_LEN\t\t54\t/* Alternate length for vendor information; Pirelli */\n\n#define NUM_PIRELLI\t\t2\n#define IMAGETAG_CRC_START\t0xFFFFFFFF\n\n#define PIRELLI_BOARDS { \\\n\t\"AGPF-S0\", \\\n\t\"DWV-S0\", \\\n}\n/*\n * The broadcom firmware assumes the rootfs starts the image,\n * therefore uses the rootfs start (flash_image_address)\n * to determine where to flash the image.  Since we have the kernel first\n * we have to give it the kernel address, but the crc uses the length\n * associated with this address (root_length), which is added to the kernel\n * length (kernel_length) to determine the length of image to flash and thus\n * needs to be rootfs + deadcode (jffs2 EOF marker)\n*/\n\nstruct bcm_tag {\n\t/* 0-3: Version of the image tag */\n\tchar tag_version[TAGVER_LEN];\n\t/* 4-23: Company Line 1 */\n\tchar sig_1[SIG1_LEN];\n\t/*  24-37: Company Line 2 */\n\tchar sig_2[SIG2_LEN];\n\t/* 38-43: Chip this image is for */\n\tchar chip_id[CHIPID_LEN];\n\t/* 44-59: Board name */\n\tchar board_id[BOARDID_LEN];\n\t/* 60-61: Map endianness -- 1 BE 0 LE */\n\tchar big_endian[ENDIANFLAG_LEN];\n\t/* 62-71: Total length of image */\n\tchar total_length[IMAGE_LEN];\n\t/* 72-83: Address in memory of CFE */\n\tchar cfe__address[ADDRESS_LEN];\n\t/* 84-93: Size of CFE */\n\tchar cfe_length[IMAGE_LEN];\n\t/* 94-105: Address in memory of image start\n\t * (kernel for OpenWRT, rootfs for stock firmware)\n\t */\n\tchar flash_image_start[ADDRESS_LEN];\n\t/* 106-115: Size of rootfs */\n\tchar root_length[IMAGE_LEN];\n\t/* 116-127: Address in memory of kernel */\n\tchar kernel_address[ADDRESS_LEN];\n\t/* 128-137: Size of kernel */\n\tchar kernel_length[IMAGE_LEN];\n\t/* 138-139: Unused at the moment */\n\tchar dual_image[DUALFLAG_LEN];\n\t/* 140-141: Unused at the moment */\n\tchar inactive_flag[INACTIVEFLAG_LEN];\n\t/* 142-161: RSA Signature (not used; some vendors may use this) */\n\tchar rsa_signature[RSASIG_LEN];\n\t/* 162-191: Compilation and related information (not used in OpenWrt) */\n\tchar information1[TAGINFO1_LEN];\n\t/* 192-195: Version flash layout */\n\tchar flash_layout_ver[FLASHLAYOUTVER_LEN];\n\t/* 196-199: kernel+rootfs CRC32 */\n\t__u32 fskernel_crc;\n\t/* 200-215: Unused except on Alice Gate where is is information */\n\tchar information2[TAGINFO2_LEN];\n\t/* 216-219: CRC32 of image less imagetag (kernel for Alice Gate) */\n\t__u32 image_crc;\n\t/* 220-223: CRC32 of rootfs partition */\n\t__u32 rootfs_crc;\n\t/* 224-227: CRC32 of kernel partition */\n\t__u32 kernel_crc;\n\t/* 228-231: Image sequence number */\n\tchar image_sequence[4];\n\t/* 222-235: Openwrt: real rootfs length */\n\t__u32 real_rootfs_length;\n\t/* 236-239: CRC32 of header excluding last 20 bytes */\n\t__u32 header_crc;\n\t/* 240-255: Unused at present */\n\tchar reserved2[16];\n};\nssize_t pread(int fd, void *buf, size_t count, off_t offset);\nssize_t pwrite(int fd, const void *buf, size_t count, off_t offset);\n\n#define CRC_START 0xFFFFFFFF\n\nstatic uint32_t strntoul(char *str, char **endptr, int base, size_t len) {\n  char *newstr;\n  uint32_t res = 0;\n\n  newstr = calloc(len + 1, sizeof(char));\n  if (newstr) {\n\tstrncpy(newstr, str, len); \n\tres = strtoul(newstr, endptr, base);\n\tfree(newstr);\n  }\n  return res;\n}\n\nuint32_t compute_crc32(uint32_t crc, off_t start, size_t compute_len, int fd)\n{\n\tuint8_t readbuf[1024];\n\tssize_t res;\n\toff_t offset = start;\n\n\t/* Read a buffer's worth of bytes  */\n\twhile (fd && (compute_len >= sizeof(readbuf))) {\n\t\tres = pread(fd, readbuf, sizeof(readbuf), offset);\n\t\tcrc = crc32(crc, readbuf, res);\n\t\tcompute_len = compute_len - res;\n\t\toffset += res;\n\t}\n\n\t/* Less than buffer-size bytes remains, read compute_len bytes */\n\tif (fd && (compute_len > 0)) {\n\t  res = pread(fd, readbuf, compute_len, offset);\n\t  crc = crc32(crc, readbuf, res);\n\t}\n\n\treturn crc;\n}\n\nint\ntrx_fixup(int fd, const char *name)\n{\n\tstruct mtd_info_user mtdInfo;\n\tunsigned long len;\n\tvoid *ptr, *scan;\n\tint bfd;\n\tstruct bcm_tag *tag;\n\tssize_t res;\n\tuint32_t cfelen, imagelen, imagestart, rootfslen;\n\tuint32_t imagecrc, rootfscrc, headercrc;\n\tuint32_t offset = 0;\n\tcfelen = imagelen = imagestart = imagecrc = rootfscrc = headercrc = rootfslen = 0;\n\n\n\tif (ioctl(fd, MEMGETINFO, &mtdInfo) < 0) {\n\t\tfprintf(stderr, \"Failed to get mtd info\\n\");\n\t\tgoto err;\n\t}\n\n\tlen = mtdInfo.size;\n\tif (mtdInfo.size <= 0) {\n\t\tfprintf(stderr, \"Invalid MTD device size\\n\");\n\t\tgoto err;\n\t}\n\n\tbfd = mtd_open(name, true);\n\tptr = mmap(NULL, len, PROT_READ|PROT_WRITE, MAP_SHARED, bfd, 0);\n\tif (!ptr || (ptr == (void *) -1)) {\n\t\tperror(\"mmap\");\n\t\tgoto err1;\n\t}\n\n\ttag = (struct bcm_tag *) (ptr);\n\n\tcfelen = strntoul(&tag->cfe_length[0], NULL, 10, IMAGE_LEN);\n\tif (cfelen) {\n\t  fprintf(stderr, \"Non-zero CFE length.  This is currently unsupported.\\n\");\n\t  exit(1);\n\t}\n\n\theadercrc = compute_crc32(CRC_START, offset, offsetof(struct bcm_tag, header_crc), fd);\n\tif (headercrc != *(uint32_t *)(&tag->header_crc)) {\n\t\tfprintf(stderr, \"Tag verify failed.  This may not be a valid image.\\n\");\n\t\texit(1);\n\t}\n\n\tsprintf(&tag->root_length[0], \"%u\", 0);\n\tstrncpy(&tag->total_length[0], &tag->kernel_length[0], IMAGE_LEN);\n\n\timagestart = sizeof(tag);\n\tmemcpy(&tag->image_crc, &tag->kernel_crc, sizeof(uint32_t));\n\tmemcpy(&tag->fskernel_crc, &tag->kernel_crc, sizeof(uint32_t));\n\trootfscrc = CRC_START;\n\tmemcpy(&tag->rootfs_crc, &rootfscrc, sizeof(uint32_t));\n\theadercrc = crc32(CRC_START, tag, offsetof(struct bcm_tag, header_crc));\n\tmemcpy(&tag->header_crc, &headercrc, sizeof(uint32_t));\n\n\tmsync(ptr, sizeof(struct bcm_tag), MS_SYNC|MS_INVALIDATE);\n\tmunmap(ptr, len);\n\tclose(bfd);\n\treturn 0;\n\nerr1:\n\tclose(bfd);\nerr:\n\tfprintf(stderr, \"Error fixing up imagetag header\\n\");\n\treturn -1;\n}\n\n\nint\ntrx_check(int imagefd, const char *mtd, char *buf, int *len)\n{\n    struct bcm_tag *tag = (const struct bcm_tag *) buf;\n\tint fd;\n\tuint32_t headerCRC;\n\tuint32_t imageLen;\n\n\tif (strcmp(mtd, \"linux\") != 0)\n\t\treturn 1;\n\n\t*len = read(imagefd, buf, sizeof(struct bcm_tag));\n\tif (*len < sizeof(struct bcm_tag)) {\n\t\tfprintf(stdout, \"Could not get image header, file too small (%d bytes)\\n\", *len);\n\t\treturn 0;\n\t}\n\theaderCRC = crc32buf(buf, offsetof(struct bcm_tag, header_crc));\n\tif (*(uint32_t *)(&tag->header_crc) != headerCRC) {\n  \n\t  if (quiet < 2) {\n\t\tfprintf(stderr, \"Bad header CRC got %08x, calculated %08x\\n\",\n\t\t\t\t*(uint32_t *)(&tag->header_crc), headerCRC);\n\t\tfprintf(stderr, \"This is not the correct file format; refusing to flash.\\n\"\n\t\t\t\t\"Please specify the correct file or use -f to force.\\n\");\n\t  }\n\t  return 0;\n\t}\n\n\t/* check if image fits to mtd device */\n\tfd = mtd_check_open(mtd);\n\tif(fd < 0) {\n\t\tfprintf(stderr, \"Could not open mtd device: %s\\n\", mtd);\n\t\texit(1);\n\t}\n\n\timageLen = strntoul(&tag->total_length[0], NULL, 10, IMAGE_LEN);\n\t\n\tif(mtdsize < imageLen) {\n\t\tfprintf(stderr, \"Image too big for partition: %s\\n\", mtd);\n\t\tclose(fd);\n\t\treturn 0;\n\t}\n\n\tclose(fd);\n\treturn 1;\n}\n\nint\nmtd_fixtrx(const char *mtd, size_t offset, size_t data_size)\n{\n\tint fd;\n\tstruct bcm_tag *tag;\n\tchar *buf;\n\tssize_t res;\n\tsize_t block_offset;\n\tuint32_t cfelen, imagelen, imagestart, rootfslen;\n\tuint32_t imagecrc, rootfscrc, headercrc;\n\tcfelen = imagelen = imagestart = imagecrc = rootfscrc = headercrc = rootfslen = 0;\n\n\tif (data_size)\n\t\tfprintf(stderr, \"Specifying data size in unsupported for imagetag\\n\");\n\n\tif (quiet < 2)\n\t\tfprintf(stderr, \"Trying to fix trx header in %s at 0x%x...\\n\", mtd, offset);\n\n\tblock_offset = offset & ~(erasesize - 1);\n\toffset -= block_offset;\n\n\tfd = mtd_check_open(mtd);\n\tif(fd < 0) {\n\t\tfprintf(stderr, \"Could not open mtd device: %s\\n\", mtd);\n\t\texit(1);\n\t}\n\n\tif (block_offset + erasesize > mtdsize) {\n\t\tfprintf(stderr, \"Offset too large, device size 0x%x\\n\", mtdsize);\n\t\texit(1);\n\t}\n\n\tbuf = malloc(erasesize);\n\tif (!buf) {\n\t\tperror(\"malloc\");\n\t\texit(1);\n\t}\n\n\tres = pread(fd, buf, erasesize, block_offset);\n\tif (res != erasesize) {\n\t\tperror(\"pread\");\n\t\texit(1);\n\t}\n\n\ttag = (struct bcm_tag *) (buf + offset);\n\n\tcfelen = strntoul(tag->cfe_length, NULL, 10, IMAGE_LEN);\n\tif (cfelen) {\n\t  fprintf(stderr, \"Non-zero CFE length.  This is currently unsupported.\\n\");\n\t  exit(1);\n\t}\n\n\tif (quiet < 2) {\n\t  fprintf(stderr, \"Verifying we actually have an imagetag.\\n\");\n\t}\n\n\theadercrc = compute_crc32(CRC_START, offset, offsetof(struct bcm_tag, header_crc), fd);\n\tif (headercrc != *(uint32_t *)(&tag->header_crc)) {\n\t\tfprintf(stderr, \"Tag verify failed.  This may not be a valid image.\\n\");\n\t\texit(1);\n\t}\n\n\tif (quiet < 2) {\n\t  fprintf(stderr, \"Checking current fixed status.\\n\");\n\t}\n\n\trootfslen = strntoul(&tag->root_length[0], NULL, 10, IMAGE_LEN);\n\tif (rootfslen == 0) {\n\t  if (quiet < 2) \n\t\tfprintf(stderr, \"Header already fixed, exiting\\n\");\n\t  close(fd);\n\t  return 0;\n\t}\n\n\tif (quiet < 2) {\n\t  fprintf(stderr, \"Setting root length to 0.\\n\");\n\t}\n\n\tsprintf(&tag->root_length[0], \"%u\", 0);\n\tstrncpy(&tag->total_length[0], &tag->kernel_length[0], IMAGE_LEN);\n\n\tif (quiet < 2) {\n\t  fprintf(stderr, \"Recalculating CRCs.\\n\");\n\t}\n\n\timagestart = sizeof(tag);\n\tmemcpy(&tag->image_crc, &tag->kernel_crc, sizeof(uint32_t));\n\tmemcpy(&tag->fskernel_crc, &tag->kernel_crc, sizeof(uint32_t));\n\trootfscrc = CRC_START;\n\tmemcpy(&tag->rootfs_crc, &rootfscrc, sizeof(uint32_t));\n\theadercrc = crc32(CRC_START, tag, offsetof(struct bcm_tag, header_crc));\n\tmemcpy(&tag->header_crc, &headercrc, sizeof(uint32_t));\n\n\tif (quiet < 2) {\n\t  fprintf(stderr, \"Erasing imagetag block\\n\");\n\t}\n\n\tif (mtd_erase_block(fd, block_offset)) {\n\t\tfprintf(stderr, \"Can't erase block at 0x%x (%s)\\n\", block_offset, strerror(errno));\n\t\texit(1);\n\t}\n\n\tif (quiet < 2) {\n\t  fprintf(stderr, \"New image crc32: 0x%x, rewriting block\\n\", \n\t\t\t  *(uint32_t *)(&tag->image_crc));\n\t  fprintf(stderr, \"New header crc32: 0x%x, rewriting block\\n\", headercrc);  \n\t}\n\n\tif (pwrite(fd, buf, erasesize, block_offset) != erasesize) {\n\t\tfprintf(stderr, \"Error writing block (%s)\\n\", strerror(errno));\n\t\texit(1);\n\t}\n\n\tif (quiet < 2)\n\t\tfprintf(stderr, \"Done.\\n\");\n\n\tclose (fd);\n\tsync();\n\treturn 0;\n\n}\n"
  },
  {
    "path": "package/system/mtd/src/jffs2.c",
    "content": "/*\n * jffs2 on-disk structure generator for mtd\n *\n * Copyright (C) 2008 Felix Fietkau <nbd@nbd.name>\n *\n * This program is free software; you can redistribute it and/or\n * modify it under the terms of the GNU General Public License v2\n * as published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n * GNU General Public License for more details.\n * Based on:\n *   JFFS2 -- Journalling Flash File System, Version 2.\n *   Copyright © 2001-2007 Red Hat, Inc.\n *   Created by David Woodhouse <dwmw2@infradead.org>\n */\n#include <sys/types.h>\n#include <sys/stat.h>\n#include <stdint.h>\n#include <stdio.h>\n#include <fcntl.h>\n#include <stdlib.h>\n#include <string.h>\n#include <dirent.h>\n#include <unistd.h>\n#include <endian.h>\n#include \"jffs2.h\"\n#include \"crc32.h\"\n#include \"mtd.h\"\n\n#define PAD(x) (((x)+3)&~3)\n\n#if BYTE_ORDER == BIG_ENDIAN\n# define CLEANMARKER \"\\x19\\x85\\x20\\x03\\x00\\x00\\x00\\x0c\\xf0\\x60\\xdc\\x98\"\n#else\n# define CLEANMARKER \"\\x85\\x19\\x03\\x20\\x0c\\x00\\x00\\x00\\xb1\\xb0\\x1e\\xe4\"\n#endif\n\nstatic int last_ino = 0;\nstatic int last_version = 0;\nstatic char *buf = NULL;\nstatic int ofs = 0;\nstatic int outfd = -1;\nstatic int mtdofs = 0;\nstatic int target_ino = 0;\n\nstatic void prep_eraseblock(void);\n\nstatic void pad(int size)\n{\n\tif ((ofs % size == 0) && (ofs < erasesize))\n\t\treturn;\n\n\tif (ofs < erasesize) {\n\t\tmemset(buf + ofs, 0xff, (size - (ofs % size)));\n\t\tofs += (size - (ofs % size));\n\t}\n\tofs = ofs % erasesize;\n\tif (ofs == 0) {\n\t\twhile (mtd_block_is_bad(outfd, mtdofs) && (mtdofs < mtdsize)) {\n\t\t\tif (!quiet)\n\t\t\t\tfprintf(stderr, \"\\nSkipping bad block at 0x%08x   \", mtdofs);\n\n\t\t\tmtdofs += erasesize;\n\n\t\t\t/* Move the file pointer along over the bad block. */\n\t\t\tlseek(outfd, erasesize, SEEK_CUR);\n\t\t}\n\t\tmtd_erase_block(outfd, mtdofs);\n\t\twrite(outfd, buf, erasesize);\n\t\tmtdofs += erasesize;\n\t}\n}\n\nstatic inline int rbytes(void)\n{\n\treturn erasesize - (ofs % erasesize);\n}\n\nstatic inline void add_data(char *ptr, int len)\n{\n\tif (ofs + len > erasesize) {\n\t\tpad(erasesize);\n\t\tprep_eraseblock();\n\t}\n\tmemcpy(buf + ofs, ptr, len);\n\tofs += len;\n}\n\nstatic void prep_eraseblock(void)\n{\n\tif (ofs > 0)\n\t\treturn;\n\n\tadd_data(CLEANMARKER, sizeof(CLEANMARKER) - 1);\n}\n\nstatic int add_dirent(const char *name, const char type, int parent)\n{\n\tstruct jffs2_raw_dirent *de;\n\n\tif (ofs - erasesize < sizeof(struct jffs2_raw_dirent) + strlen(name))\n\t\tpad(erasesize);\n\n\tprep_eraseblock();\n\tlast_ino++;\n\tmemset(buf + ofs, 0, sizeof(struct jffs2_raw_dirent));\n\tde = (struct jffs2_raw_dirent *) (buf + ofs);\n\n\tde->magic = JFFS2_MAGIC_BITMASK;\n\tde->nodetype = JFFS2_NODETYPE_DIRENT;\n\tde->type = type;\n\tde->name_crc = crc32(0, name, strlen(name));\n\tde->ino = last_ino++;\n\tde->pino = parent;\n\tde->totlen = sizeof(*de) + strlen(name);\n\tde->hdr_crc = crc32(0, (void *) de, sizeof(struct jffs2_unknown_node) - 4);\n\tde->version = last_version++;\n\tde->mctime = 0;\n\tde->nsize = strlen(name);\n\tde->node_crc = crc32(0, (void *) de, sizeof(*de) - 8);\n\tmemcpy(de->name, name, strlen(name));\n\n\tofs += sizeof(struct jffs2_raw_dirent) + de->nsize;\n\tpad(4);\n\n\treturn de->ino;\n}\n\nstatic int add_dir(const char *name, int parent)\n{\n\tstruct jffs2_raw_inode ri;\n\tint inode;\n\n\tinode = add_dirent(name, IFTODT(S_IFDIR), parent);\n\n\tif (rbytes() < sizeof(ri))\n\t\tpad(erasesize);\n\tprep_eraseblock();\n\n\tmemset(&ri, 0, sizeof(ri));\n\tri.magic = JFFS2_MAGIC_BITMASK;\n\tri.nodetype = JFFS2_NODETYPE_INODE;\n\tri.totlen = sizeof(ri);\n\tri.hdr_crc = crc32(0, &ri, sizeof(struct jffs2_unknown_node) - 4);\n\n\tri.ino = inode;\n\tri.mode = S_IFDIR | 0755;\n\tri.uid = ri.gid = 0;\n\tri.atime = ri.ctime = ri.mtime = 0;\n\tri.isize = ri.csize = ri.dsize = 0;\n\tri.version = 1;\n\tri.node_crc = crc32(0, &ri, sizeof(ri) - 8);\n\tri.data_crc = 0;\n\n\tadd_data((char *) &ri, sizeof(ri));\n\tpad(4);\n\treturn inode;\n}\n\nstatic void add_file(const char *name, int parent)\n{\n\tint inode, f_offset = 0, fd;\n\tstruct jffs2_raw_inode ri;\n\tstruct stat st;\n\tchar wbuf[4096];\n\tconst char *fname;\n\n\tif (stat(name, &st)) {\n\t\tfprintf(stderr, \"File %s does not exist\\n\", name);\n\t\treturn;\n\t}\n\n\tfname = strrchr(name, '/');\n\tif (fname)\n\t\tfname++;\n\telse\n\t\tfname = name;\n\n\tinode = add_dirent(fname, IFTODT(S_IFREG), parent);\n\tmemset(&ri, 0, sizeof(ri));\n\tri.magic = JFFS2_MAGIC_BITMASK;\n\tri.nodetype = JFFS2_NODETYPE_INODE;\n\n\tri.ino = inode;\n\tri.mode = st.st_mode;\n\tri.uid = ri.gid = 0;\n\tri.atime = st.st_atime;\n\tri.ctime = st.st_ctime;\n\tri.mtime = st.st_mtime;\n\tri.isize = st.st_size;\n\tri.compr = 0;\n\tri.usercompr = 0;\n\n\tfd = open(name, 0);\n\tif (fd < 0) {\n\t\tfprintf(stderr, \"File %s does not exist\\n\", name);\n\t\treturn;\n\t}\n\n\tfor (;;) {\n\t\tint len = 0;\n\n\t\tfor (;;) {\n\t\t\tlen = rbytes() - sizeof(ri);\n\t\t\tif (len > 128)\n\t\t\t\tbreak;\n\n\t\t\tpad(erasesize);\n\t\t\tprep_eraseblock();\n\t\t}\n\n\t\tif (len > sizeof(wbuf))\n\t\t\tlen = sizeof(wbuf);\n\n\t\tlen = read(fd, wbuf, len);\n\t\tif (len <= 0)\n\t\t\tbreak;\n\n\t\tri.totlen = sizeof(ri) + len;\n\t\tri.hdr_crc = crc32(0, &ri, sizeof(struct jffs2_unknown_node) - 4);\n\t\tri.version = ++last_version;\n\t\tri.offset = f_offset;\n\t\tri.csize = ri.dsize = len;\n\t\tri.node_crc = crc32(0, &ri, sizeof(ri) - 8);\n\t\tri.data_crc = crc32(0, wbuf, len);\n\t\tf_offset += len;\n\t\tadd_data((char *) &ri, sizeof(ri));\n\t\tadd_data(wbuf, len);\n\t\tpad(4);\n\t\tprep_eraseblock();\n\t}\n\n\tclose(fd);\n}\n\nint mtd_replace_jffs2(const char *mtd, int fd, int ofs, const char *filename)\n{\n\toutfd = fd;\n\tmtdofs = ofs;\n\n\tbuf = malloc(erasesize);\n\ttarget_ino = 1;\n\tif (!last_ino)\n\t\tlast_ino = 1;\n\tadd_file(filename, target_ino);\n\tpad(erasesize);\n\n\t/* add eof marker, pad to eraseblock size and write the data */\n\tadd_data(JFFS2_EOF, sizeof(JFFS2_EOF) - 1);\n\tpad(erasesize);\n\tfree(buf);\n\n\treturn (mtdofs - ofs);\n}\n\nvoid mtd_parse_jffs2data(const char *buf, const char *dir)\n{\n\tstruct jffs2_unknown_node *node = (struct jffs2_unknown_node *) buf;\n\tunsigned int ofs = 0;\n\n\twhile (ofs < erasesize) {\n\t\tnode = (struct jffs2_unknown_node *) (buf + ofs);\n\t\tif (node->magic != 0x1985)\n\t\t\tbreak;\n\n\t\tofs += PAD(node->totlen);\n\t\tif (node->nodetype == JFFS2_NODETYPE_DIRENT) {\n\t\t\tstruct jffs2_raw_dirent *de = (struct jffs2_raw_dirent *) node;\n\n\t\t\t/* is this the right directory name and is it a subdirectory of / */\n\t\t\tif (*dir && (de->pino == 1) && !strncmp((char *) de->name, dir, de->nsize))\n\t\t\t\ttarget_ino = de->ino;\n\n\t\t\t/* store the last inode and version numbers for adding extra files */\n\t\t\tif (last_ino < de->ino)\n\t\t\t\tlast_ino = de->ino;\n\t\t\tif (last_version < de->version)\n\t\t\t\tlast_version = de->version;\n\t\t}\n\t}\n}\n\nint mtd_write_jffs2(const char *mtd, const char *filename, const char *dir)\n{\n\tint err = -1, fdeof = 0;\n\n\toutfd = mtd_check_open(mtd);\n\tif (outfd < 0)\n\t\treturn -1;\n\n\tif (quiet < 2)\n\t\tfprintf(stderr, \"Appending %s to jffs2 partition %s\\n\", filename, mtd);\n\t\n\tbuf = malloc(erasesize);\n\tif (!buf) {\n\t\tfprintf(stderr, \"Out of memory!\\n\");\n\t\tgoto done;\n\t}\n\n\tif (!*dir)\n\t\ttarget_ino = 1;\n\n\t/* parse the structure of the jffs2 first\n\t * locate the directory that the file is going to be placed in */\n\tfor(;;) {\n\t\tstruct jffs2_unknown_node *node = (struct jffs2_unknown_node *) buf;\n\n\t\tif (read(outfd, buf, erasesize) != erasesize) {\n\t\t\tfdeof = 1;\n\t\t\tbreak;\n\t\t}\n\t\tmtdofs += erasesize;\n\n\t\tif (node->magic == 0x8519) {\n\t\t\tfprintf(stderr, \"Error: wrong endianness filesystem\\n\");\n\t\t\tgoto done;\n\t\t}\n\n\t\t/* assume  no magic == end of filesystem\n\t\t * the filesystem will probably end with be32(0xdeadc0de) */\n\t\tif (node->magic != 0x1985)\n\t\t\tbreak;\n\n\t\tmtd_parse_jffs2data(buf, dir);\n\t}\n\n\tif (fdeof) {\n\t\tfprintf(stderr, \"Error: No room for additional data\\n\");\n\t\tgoto done;\n\t}\n\n\t/* jump back one eraseblock */\n\tmtdofs -= erasesize;\n\tlseek(outfd, mtdofs, SEEK_SET);\n\n\tofs = 0;\n\n\tif (!last_ino)\n\t\tlast_ino = 1;\n\n\tif (!target_ino)\n\t\ttarget_ino = add_dir(dir, 1);\n\n\tadd_file(filename, target_ino);\n\tpad(erasesize);\n\n\t/* add eof marker, pad to eraseblock size and write the data */\n\tadd_data(JFFS2_EOF, sizeof(JFFS2_EOF) - 1);\n\tpad(erasesize);\n\n\terr = 0;\n\n\tif (trx_fixup) {\n\t  trx_fixup(outfd, mtd);\n\t}\n\ndone:\n\tclose(outfd);\n\tif (buf)\n\t\tfree(buf);\n\n\treturn err;\n}\n"
  },
  {
    "path": "package/system/mtd/src/jffs2.h",
    "content": "/*\n * JFFS2 -- Journalling Flash File System, Version 2.\n *\n * Copyright (C) 2001-2003 Red Hat, Inc.\n *\n * Created by David Woodhouse <dwmw2@infradead.org>\n *\n * For licensing information, see the file 'LICENCE' in the\n * jffs2 directory.\n *\n *\n */\n\n#ifndef __LINUX_JFFS2_H__\n#define __LINUX_JFFS2_H__\n\n#define JFFS2_SUPER_MAGIC   0x72b6\n\n/* You must include something which defines the C99 uintXX_t types. \n   We don't do it from here because this file is used in too many\n   different environments. */\n\n/* Values we may expect to find in the 'magic' field */\n#define JFFS2_OLD_MAGIC_BITMASK 0x1984\n#define JFFS2_MAGIC_BITMASK 0x1985\n#define KSAMTIB_CIGAM_2SFFJ 0x8519 /* For detecting wrong-endian fs */\n#define JFFS2_EMPTY_BITMASK 0xffff\n#define JFFS2_DIRTY_BITMASK 0x0000\n\n/* Summary node MAGIC marker */\n#define JFFS2_SUM_MAGIC\t0x02851885\n\n/* We only allow a single char for length, and 0xFF is empty flash so\n   we don't want it confused with a real length. Hence max 254.\n*/\n#define JFFS2_MAX_NAME_LEN 254\n\n/* How small can we sensibly write nodes? */\n#define JFFS2_MIN_DATA_LEN 128\n\n#define JFFS2_COMPR_NONE\t0x00\n#define JFFS2_COMPR_ZERO\t0x01\n#define JFFS2_COMPR_RTIME\t0x02\n#define JFFS2_COMPR_RUBINMIPS\t0x03\n#define JFFS2_COMPR_COPY\t0x04\n#define JFFS2_COMPR_DYNRUBIN\t0x05\n#define JFFS2_COMPR_ZLIB\t0x06\n/* Compatibility flags. */\n#define JFFS2_COMPAT_MASK 0xc000      /* What do to if an unknown nodetype is found */\n#define JFFS2_NODE_ACCURATE 0x2000\n/* INCOMPAT: Fail to mount the filesystem */\n#define JFFS2_FEATURE_INCOMPAT 0xc000\n/* ROCOMPAT: Mount read-only */\n#define JFFS2_FEATURE_ROCOMPAT 0x8000\n/* RWCOMPAT_COPY: Mount read/write, and copy the node when it's GC'd */\n#define JFFS2_FEATURE_RWCOMPAT_COPY 0x4000\n/* RWCOMPAT_DELETE: Mount read/write, and delete the node when it's GC'd */\n#define JFFS2_FEATURE_RWCOMPAT_DELETE 0x0000\n\n#define JFFS2_NODETYPE_DIRENT (JFFS2_FEATURE_INCOMPAT | JFFS2_NODE_ACCURATE | 1)\n#define JFFS2_NODETYPE_INODE (JFFS2_FEATURE_INCOMPAT | JFFS2_NODE_ACCURATE | 2)\n#define JFFS2_NODETYPE_CLEANMARKER (JFFS2_FEATURE_RWCOMPAT_DELETE | JFFS2_NODE_ACCURATE | 3)\n#define JFFS2_NODETYPE_PADDING (JFFS2_FEATURE_RWCOMPAT_DELETE | JFFS2_NODE_ACCURATE | 4)\n\n#define JFFS2_NODETYPE_SUMMARY (JFFS2_FEATURE_RWCOMPAT_DELETE | JFFS2_NODE_ACCURATE | 6)\n\n#define JFFS2_NODETYPE_XATTR (JFFS2_FEATURE_INCOMPAT | JFFS2_NODE_ACCURATE | 8)\n#define JFFS2_NODETYPE_XREF (JFFS2_FEATURE_INCOMPAT | JFFS2_NODE_ACCURATE | 9)\n\n/* XATTR Related */\n#define JFFS2_XPREFIX_USER\t\t1\t/* for \"user.\" */\n#define JFFS2_XPREFIX_SECURITY\t\t2\t/* for \"security.\" */\n#define JFFS2_XPREFIX_ACL_ACCESS\t3\t/* for \"system.posix_acl_access\" */\n#define JFFS2_XPREFIX_ACL_DEFAULT\t4\t/* for \"system.posix_acl_default\" */\n#define JFFS2_XPREFIX_TRUSTED\t\t5\t/* for \"trusted.*\" */\n\n#define JFFS2_ACL_VERSION\t\t0x0001\n\n// Maybe later...\n//#define JFFS2_NODETYPE_CHECKPOINT (JFFS2_FEATURE_RWCOMPAT_DELETE | JFFS2_NODE_ACCURATE | 3)\n//#define JFFS2_NODETYPE_OPTIONS (JFFS2_FEATURE_RWCOMPAT_COPY | JFFS2_NODE_ACCURATE | 4)\n\n\n#define JFFS2_INO_FLAG_PREREAD\t  1\t/* Do read_inode() for this one at\n\t\t\t\t\t   mount time, don't wait for it to\n\t\t\t\t\t   happen later */\n#define JFFS2_INO_FLAG_USERCOMPR  2\t/* User has requested a specific\n\t\t\t\t\t   compression type */\n\n\n/* These can go once we've made sure we've caught all uses without\n   byteswapping */\n\ntypedef\tuint32_t jint32_t;\n\ntypedef uint32_t jmode_t;\n\ntypedef uint16_t jint16_t;\n\nstruct jffs2_unknown_node\n{\n\t/* All start like this */\n\tjint16_t magic;\n\tjint16_t nodetype;\n\tjint32_t totlen; /* So we can skip over nodes we don't grok */\n\tjint32_t hdr_crc;\n};\n\nstruct jffs2_raw_dirent\n{\n\tjint16_t magic;\n\tjint16_t nodetype;\t/* == JFFS2_NODETYPE_DIRENT */\n\tjint32_t totlen;\n\tjint32_t hdr_crc;\n\tjint32_t pino;\n\tjint32_t version;\n\tjint32_t ino; /* == zero for unlink */\n\tjint32_t mctime;\n\tuint8_t nsize;\n\tuint8_t type;\n\tuint8_t unused[2];\n\tjint32_t node_crc;\n\tjint32_t name_crc;\n\tuint8_t name[0];\n};\n\n/* The JFFS2 raw inode structure: Used for storage on physical media.  */\n/* The uid, gid, atime, mtime and ctime members could be longer, but\n   are left like this for space efficiency. If and when people decide\n   they really need them extended, it's simple enough to add support for\n   a new type of raw node.\n*/\nstruct jffs2_raw_inode\n{\n\tjint16_t magic;      /* A constant magic number.  */\n\tjint16_t nodetype;   /* == JFFS2_NODETYPE_INODE */\n\tjint32_t totlen;     /* Total length of this node (inc data, etc.) */\n\tjint32_t hdr_crc;\n\tjint32_t ino;        /* Inode number.  */\n\tjint32_t version;    /* Version number.  */\n\tjmode_t mode;       /* The file's type or mode.  */\n\tjint16_t uid;        /* The file's owner.  */\n\tjint16_t gid;        /* The file's group.  */\n\tjint32_t isize;      /* Total resultant size of this inode (used for truncations)  */\n\tjint32_t atime;      /* Last access time.  */\n\tjint32_t mtime;      /* Last modification time.  */\n\tjint32_t ctime;      /* Change time.  */\n\tjint32_t offset;     /* Where to begin to write.  */\n\tjint32_t csize;      /* (Compressed) data size */\n\tjint32_t dsize;\t     /* Size of the node's data. (after decompression) */\n\tuint8_t compr;       /* Compression algorithm used */\n\tuint8_t usercompr;   /* Compression algorithm requested by the user */\n\tjint16_t flags;\t     /* See JFFS2_INO_FLAG_* */\n\tjint32_t data_crc;   /* CRC for the (compressed) data.  */\n\tjint32_t node_crc;   /* CRC for the raw inode (excluding data)  */\n\tuint8_t data[0];\n};\n\nstruct jffs2_raw_xattr {\n\tjint16_t magic;\n\tjint16_t nodetype;\t/* = JFFS2_NODETYPE_XATTR */\n\tjint32_t totlen;\n\tjint32_t hdr_crc;\n\tjint32_t xid;\t\t/* XATTR identifier number */\n\tjint32_t version;\n\tuint8_t xprefix;\n\tuint8_t name_len;\n\tjint16_t value_len;\n\tjint32_t data_crc;\n\tjint32_t node_crc;\n\tuint8_t data[0];\n} __attribute__((packed));\n\nstruct jffs2_raw_xref\n{\n\tjint16_t magic;\n\tjint16_t nodetype;\t/* = JFFS2_NODETYPE_XREF */\n\tjint32_t totlen;\n\tjint32_t hdr_crc;\n\tjint32_t ino;\t\t/* inode number */\n\tjint32_t xid;\t\t/* XATTR identifier number */\n\tjint32_t xseqno;\t/* xref sequencial number */\n\tjint32_t node_crc;\n} __attribute__((packed));\n\nstruct jffs2_raw_summary\n{\n\tjint16_t magic;\n\tjint16_t nodetype; \t/* = JFFS2_NODETYPE_SUMMARY */\n\tjint32_t totlen;\n\tjint32_t hdr_crc;\n\tjint32_t sum_num;\t/* number of sum entries*/\n\tjint32_t cln_mkr;\t/* clean marker size, 0 = no cleanmarker */\n\tjint32_t padded;\t/* sum of the size of padding nodes */\n\tjint32_t sum_crc;\t/* summary information crc */\n\tjint32_t node_crc; \t/* node crc */\n\tjint32_t sum[0]; \t/* inode summary info */\n};\n\nunion jffs2_node_union\n{\n\tstruct jffs2_raw_inode i;\n\tstruct jffs2_raw_dirent d;\n\tstruct jffs2_raw_xattr x;\n\tstruct jffs2_raw_xref r;\n\tstruct jffs2_raw_summary s;\n\tstruct jffs2_unknown_node u;\n};\n\n/* Data payload for device nodes. */\nunion jffs2_device_node {\n\tjint16_t old;\n\tjint32_t new;\n};\n\n#endif /* __LINUX_JFFS2_H__ */\n"
  },
  {
    "path": "package/system/mtd/src/linksys_bootcount.c",
    "content": "/*\n * Linksys boot counter reset code for mtd\n *\n * Copyright (C) 2013 Jonas Gorski <jogo@openwrt.org>\n * Portions Copyright (c) 2019, Jeff Kletsky\n *\n * This program is free software; you can redistribute it and/or\n * modify it under the terms of the GNU General Public License v2\n * as published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n * GNU General Public License for more details.\n *\n * You should have received a copy of the GNU General Public License\n * along with this program; if not, write to the Free Software\n * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.\n *\n */\n\n#include <stdio.h>\n#include <stdlib.h>\n#include <stddef.h>\n#include <unistd.h>\n#include <fcntl.h>\n#include <sys/mman.h>\n#include <sys/stat.h>\n#include <endian.h>\n#include <string.h>\n#include <errno.h>\n#include <stdint.h>\n#include <syslog.h>\n\n#include <sys/ioctl.h>\n#include <mtd/mtd-user.h>\n\n#include \"mtd.h\"\n\n#define BOOTCOUNT_MAGIC\t0x20110811\n\n/*\n * EA6350v3, and potentially other NOR-boot devices,\n * use an offset increment of 16 between records,\n * not mtd_info_user.writesize (often 1 on NOR devices).\n */\n\n#define BC_OFFSET_INCREMENT_MIN 16\n\n\n\n#define DLOG_OPEN()\n\n#define DLOG_ERR(...) do {\t\t\t\t\t\t       \\\n\t\tfprintf(stderr, \"ERROR: \" __VA_ARGS__); fprintf(stderr, \"\\n\"); \\\n\t} while (0)\n\n#define DLOG_NOTICE(...) do {\t\t\t\t\t\t\\\n\t\tfprintf(stderr, __VA_ARGS__); fprintf(stderr, \"\\n\");\t\\\n\t} while (0)\n\n#define DLOG_DEBUG(...)\n\n\n\nstruct bootcounter {\n\tuint32_t magic;\n\tuint32_t count;\n\tuint32_t checksum;\n};\n\nstatic char page[2048];\n\nint mtd_resetbc(const char *mtd)\n{\n\tstruct mtd_info_user mtd_info;\n\tstruct bootcounter *curr = (struct bootcounter *)page;\n\tunsigned int i;\n\tunsigned int bc_offset_increment;\n\tint last_count = 0;\n\tint num_bc;\n\tint fd;\n\tint ret;\n\tint retval = 0;\n\n\tDLOG_OPEN();\n\n\tfd = mtd_check_open(mtd);\n\n\tif (ioctl(fd, MEMGETINFO, &mtd_info) < 0) {\n\t\tDLOG_ERR(\"Unable to obtain mtd_info for given partition name.\");\n\n\t\tretval = -1;\n\t\tgoto out;\n\t}\n\n\n\t/* Detect need to override increment (for EA6350v3) */\n\n\tif (mtd_info.writesize < BC_OFFSET_INCREMENT_MIN) {\n\n\t\tbc_offset_increment = BC_OFFSET_INCREMENT_MIN;\n\t\tDLOG_DEBUG(\"Offset increment set to %i for writesize of %i\",\n\t\t\t   bc_offset_increment, mtd_info.writesize);\n\t} else {\n\n\t\tbc_offset_increment = mtd_info.writesize;\n\t}\n\n\tnum_bc = mtd_info.size / bc_offset_increment;\n\n\tfor (i = 0; i < num_bc; i++) {\n\t\tpread(fd, curr, sizeof(*curr), i * bc_offset_increment);\n\n\t\t/* Existing code assumes erase is to 0xff; left as-is (2019) */\n\n\t\tif (curr->magic != BOOTCOUNT_MAGIC &&\n\t\t    curr->magic != 0xffffffff) {\n\t\t\tDLOG_ERR(\"Unexpected magic %08x at offset %08x; aborting.\",\n\t\t\t\t curr->magic, i * bc_offset_increment);\n\n\t\t\tretval = -2;\n\t\t\tgoto out;\n\t\t}\n\n\t\tif (curr->magic == 0xffffffff)\n\t\t\tbreak;\n\n\t\tlast_count = curr->count;\n\t}\n\n\n\tif (last_count == 0) {\t/* bootcount is already 0 */\n\n\t\tretval = 0;\n\t\tgoto out;\n\t}\n\n\n\tif (i == num_bc) {\n\t\tDLOG_NOTICE(\"Boot-count log full with %i entries; erasing (expected occasionally).\",\n\t\t\t    i);\n\n\t\tstruct erase_info_user erase_info;\n\t\terase_info.start = 0;\n\t\terase_info.length = mtd_info.size;\n\n\t\tret = ioctl(fd, MEMERASE, &erase_info);\n\t\tif (ret < 0) {\n\t\t\tDLOG_ERR(\"Failed to erase boot-count log MTD; ioctl() MEMERASE returned %i\",\n\t\t\t\t ret);\n\n\t\t\tretval = -3;\n\t\t\tgoto out;\n\t\t}\n\n\t\ti = 0;\n\t}\n\n\tmemset(curr, 0xff, bc_offset_increment);\n\n\tcurr->magic = BOOTCOUNT_MAGIC;\n\tcurr->count = 0;\n\tcurr->checksum = BOOTCOUNT_MAGIC;\n\n\t/* Assumes bc_offset_increment is a multiple of mtd_info.writesize */\n\n\tret = pwrite(fd, curr, bc_offset_increment, i * bc_offset_increment);\n\tif (ret < 0) {\n\t\tDLOG_ERR(\"Failed to write boot-count log entry; pwrite() returned %i\",\n\t\t\t errno);\n\t\tretval = -4;\n\t\tgoto out;\n\n\t} else {\n\t\tsync();\n\n\t\tDLOG_NOTICE(\"Boot count sucessfully reset to zero.\");\n\n\t\tretval = 0;\n\t\tgoto out;\n\t}\n\nout:\n\tclose(fd);\n\treturn retval;\n}\n"
  },
  {
    "path": "package/system/mtd/src/md5.c",
    "content": "\n\n/*\n ***********************************************************************\n ** md5.c -- the source code for MD5 routines                         **\n ** RSA Data Security, Inc. MD5 Message-Digest Algorithm              **\n ** Created: 2/17/90 RLR                                              **\n ** Revised: 1/91 SRD,AJ,BSK,JT Reference C ver., 7/10 constant corr. **\n ***********************************************************************\n */\n\n/*\n ***********************************************************************\n ** Copyright (C) 1990, RSA Data Security, Inc. All rights reserved.  **\n **                                                                   **\n ** License to copy and use this software is granted provided that    **\n ** it is identified as the \"RSA Data Security, Inc. MD5 Message-     **\n ** Digest Algorithm\" in all material mentioning or referencing this  **\n ** software or this function.                                        **\n **                                                                   **\n ** License is also granted to make and use derivative works          **\n ** provided that such works are identified as \"derived from the RSA  **\n ** Data Security, Inc. MD5 Message-Digest Algorithm\" in all          **\n ** material mentioning or referencing the derived work.              **\n **                                                                   **\n ** RSA Data Security, Inc. makes no representations concerning       **\n ** either the merchantability of this software or the suitability    **\n ** of this software for any particular purpose.  It is provided \"as  **\n ** is\" without express or implied warranty of any kind.              **\n **                                                                   **\n ** These notices must be retained in any copies of any part of this  **\n ** documentation and/or software.                                    **\n ***********************************************************************\n */\n\n#include <string.h>\n#include \"md5.h\"\n\n/*\n ***********************************************************************\n **  Message-digest routines:                                         **\n **  To form the message digest for a message M                       **\n **    (1) Initialize a context buffer mdContext using MD5_Init       **\n **    (2) Call MD5_Update on mdContext and M                         **\n **    (3) Call MD5_Final on mdContext                                **\n **  The message digest is now in mdContext->digest[0...15]           **\n ***********************************************************************\n */\n\n/* forward declaration */\nstatic void Transform ();\n\nstatic unsigned char PADDING[64] = {\n  0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00\n};\n\n/* F, G, H and I are basic MD5 functions */\n#define F(x, y, z) (((x) & (y)) | ((~x) & (z)))\n#define G(x, y, z) (((x) & (z)) | ((y) & (~z)))\n#define H(x, y, z) ((x) ^ (y) ^ (z))\n#define I(x, y, z) ((y) ^ ((x) | (~z)))\n\n/* ROTATE_LEFT rotates x left n bits */\n#define ROTATE_LEFT(x, n) (((x) << (n)) | ((x) >> (32-(n))))\n\n/* FF, GG, HH, and II transformations for rounds 1, 2, 3, and 4 */\n/* Rotation is separate from addition to prevent recomputation */\n#define FF(a, b, c, d, x, s, ac) \\\n  {(a) += F ((b), (c), (d)) + (x) + (UINT4)(ac); \\\n   (a) = ROTATE_LEFT ((a), (s)); \\\n   (a) += (b); \\\n  }\n#define GG(a, b, c, d, x, s, ac) \\\n  {(a) += G ((b), (c), (d)) + (x) + (UINT4)(ac); \\\n   (a) = ROTATE_LEFT ((a), (s)); \\\n   (a) += (b); \\\n  }\n#define HH(a, b, c, d, x, s, ac) \\\n  {(a) += H ((b), (c), (d)) + (x) + (UINT4)(ac); \\\n   (a) = ROTATE_LEFT ((a), (s)); \\\n   (a) += (b); \\\n  }\n#define II(a, b, c, d, x, s, ac) \\\n  {(a) += I ((b), (c), (d)) + (x) + (UINT4)(ac); \\\n   (a) = ROTATE_LEFT ((a), (s)); \\\n   (a) += (b); \\\n  }\n\n#ifdef __STDC__\n#define UL(x)\tx##U\n#else\n#define UL(x)\tx\n#endif\n\n/* The routine MD5_Init initializes the message-digest context\n   mdContext. All fields are set to zero.\n */\nvoid MD5_Init (mdContext)\nMD5_CTX *mdContext;\n{\n  mdContext->i[0] = mdContext->i[1] = (UINT4)0;\n\n  /* Load magic initialization constants.\n   */\n  mdContext->buf[0] = (UINT4)0x67452301;\n  mdContext->buf[1] = (UINT4)0xefcdab89;\n  mdContext->buf[2] = (UINT4)0x98badcfe;\n  mdContext->buf[3] = (UINT4)0x10325476;\n}\n\n/* The routine MD5Update updates the message-digest context to\n   account for the presence of each of the characters inBuf[0..inLen-1]\n   in the message whose digest is being computed.\n */\nvoid MD5_Update (mdContext, inBuf, inLen)\nMD5_CTX *mdContext;\nunsigned char *inBuf;\nunsigned int inLen;\n{\n  UINT4 in[16];\n  int mdi;\n  unsigned int i, ii;\n\n  /* compute number of bytes mod 64 */\n  mdi = (int)((mdContext->i[0] >> 3) & 0x3F);\n\n  /* update number of bits */\n  if ((mdContext->i[0] + ((UINT4)inLen << 3)) < mdContext->i[0])\n    mdContext->i[1]++;\n  mdContext->i[0] += ((UINT4)inLen << 3);\n  mdContext->i[1] += ((UINT4)inLen >> 29);\n\n  while (inLen--) {\n    /* add new character to buffer, increment mdi */\n    mdContext->in[mdi++] = *inBuf++;\n\n    /* transform if necessary */\n    if (mdi == 0x40) {\n      for (i = 0, ii = 0; i < 16; i++, ii += 4)\n        in[i] = (((UINT4)mdContext->in[ii+3]) << 24) |\n                (((UINT4)mdContext->in[ii+2]) << 16) |\n                (((UINT4)mdContext->in[ii+1]) << 8) |\n                ((UINT4)mdContext->in[ii]);\n      Transform (mdContext->buf, in);\n      mdi = 0;\n    }\n  }\n}\n\n/* The routine MD5Final terminates the message-digest computation and\n   ends with the desired message digest in mdContext->digest[0...15].\n */\nvoid MD5_Final (hash, mdContext)\nunsigned char hash[];\nMD5_CTX *mdContext;\n{\n  UINT4 in[16];\n  int mdi;\n  unsigned int i, ii;\n  unsigned int padLen;\n\n  /* save number of bits */\n  in[14] = mdContext->i[0];\n  in[15] = mdContext->i[1];\n\n  /* compute number of bytes mod 64 */\n  mdi = (int)((mdContext->i[0] >> 3) & 0x3F);\n\n  /* pad out to 56 mod 64 */\n  padLen = (mdi < 56) ? (56 - mdi) : (120 - mdi);\n  MD5_Update (mdContext, PADDING, padLen);\n\n  /* append length in bits and transform */\n  for (i = 0, ii = 0; i < 14; i++, ii += 4)\n    in[i] = (((UINT4)mdContext->in[ii+3]) << 24) |\n            (((UINT4)mdContext->in[ii+2]) << 16) |\n            (((UINT4)mdContext->in[ii+1]) << 8) |\n            ((UINT4)mdContext->in[ii]);\n  Transform (mdContext->buf, in);\n\n  /* store buffer in digest */\n  for (i = 0, ii = 0; i < 4; i++, ii += 4) {\n    mdContext->digest[ii] = (unsigned char)(mdContext->buf[i] & 0xFF);\n    mdContext->digest[ii+1] =\n      (unsigned char)((mdContext->buf[i] >> 8) & 0xFF);\n    mdContext->digest[ii+2] =\n      (unsigned char)((mdContext->buf[i] >> 16) & 0xFF);\n    mdContext->digest[ii+3] =\n      (unsigned char)((mdContext->buf[i] >> 24) & 0xFF);\n  }\n  memcpy(hash, mdContext->digest, 16);\n}\n\n/* Basic MD5 step. Transforms buf based on in.\n */\nstatic void Transform (buf, in)\nUINT4 *buf;\nUINT4 *in;\n{\n  UINT4 a = buf[0], b = buf[1], c = buf[2], d = buf[3];\n\n  /* Round 1 */\n#define S11 7\n#define S12 12\n#define S13 17\n#define S14 22\n  FF ( a, b, c, d, in[ 0], S11, UL(3614090360)); /* 1 */\n  FF ( d, a, b, c, in[ 1], S12, UL(3905402710)); /* 2 */\n  FF ( c, d, a, b, in[ 2], S13, UL( 606105819)); /* 3 */\n  FF ( b, c, d, a, in[ 3], S14, UL(3250441966)); /* 4 */\n  FF ( a, b, c, d, in[ 4], S11, UL(4118548399)); /* 5 */\n  FF ( d, a, b, c, in[ 5], S12, UL(1200080426)); /* 6 */\n  FF ( c, d, a, b, in[ 6], S13, UL(2821735955)); /* 7 */\n  FF ( b, c, d, a, in[ 7], S14, UL(4249261313)); /* 8 */\n  FF ( a, b, c, d, in[ 8], S11, UL(1770035416)); /* 9 */\n  FF ( d, a, b, c, in[ 9], S12, UL(2336552879)); /* 10 */\n  FF ( c, d, a, b, in[10], S13, UL(4294925233)); /* 11 */\n  FF ( b, c, d, a, in[11], S14, UL(2304563134)); /* 12 */\n  FF ( a, b, c, d, in[12], S11, UL(1804603682)); /* 13 */\n  FF ( d, a, b, c, in[13], S12, UL(4254626195)); /* 14 */\n  FF ( c, d, a, b, in[14], S13, UL(2792965006)); /* 15 */\n  FF ( b, c, d, a, in[15], S14, UL(1236535329)); /* 16 */\n\n  /* Round 2 */\n#define S21 5\n#define S22 9\n#define S23 14\n#define S24 20\n  GG ( a, b, c, d, in[ 1], S21, UL(4129170786)); /* 17 */\n  GG ( d, a, b, c, in[ 6], S22, UL(3225465664)); /* 18 */\n  GG ( c, d, a, b, in[11], S23, UL( 643717713)); /* 19 */\n  GG ( b, c, d, a, in[ 0], S24, UL(3921069994)); /* 20 */\n  GG ( a, b, c, d, in[ 5], S21, UL(3593408605)); /* 21 */\n  GG ( d, a, b, c, in[10], S22, UL(  38016083)); /* 22 */\n  GG ( c, d, a, b, in[15], S23, UL(3634488961)); /* 23 */\n  GG ( b, c, d, a, in[ 4], S24, UL(3889429448)); /* 24 */\n  GG ( a, b, c, d, in[ 9], S21, UL( 568446438)); /* 25 */\n  GG ( d, a, b, c, in[14], S22, UL(3275163606)); /* 26 */\n  GG ( c, d, a, b, in[ 3], S23, UL(4107603335)); /* 27 */\n  GG ( b, c, d, a, in[ 8], S24, UL(1163531501)); /* 28 */\n  GG ( a, b, c, d, in[13], S21, UL(2850285829)); /* 29 */\n  GG ( d, a, b, c, in[ 2], S22, UL(4243563512)); /* 30 */\n  GG ( c, d, a, b, in[ 7], S23, UL(1735328473)); /* 31 */\n  GG ( b, c, d, a, in[12], S24, UL(2368359562)); /* 32 */\n\n  /* Round 3 */\n#define S31 4\n#define S32 11\n#define S33 16\n#define S34 23\n  HH ( a, b, c, d, in[ 5], S31, UL(4294588738)); /* 33 */\n  HH ( d, a, b, c, in[ 8], S32, UL(2272392833)); /* 34 */\n  HH ( c, d, a, b, in[11], S33, UL(1839030562)); /* 35 */\n  HH ( b, c, d, a, in[14], S34, UL(4259657740)); /* 36 */\n  HH ( a, b, c, d, in[ 1], S31, UL(2763975236)); /* 37 */\n  HH ( d, a, b, c, in[ 4], S32, UL(1272893353)); /* 38 */\n  HH ( c, d, a, b, in[ 7], S33, UL(4139469664)); /* 39 */\n  HH ( b, c, d, a, in[10], S34, UL(3200236656)); /* 40 */\n  HH ( a, b, c, d, in[13], S31, UL( 681279174)); /* 41 */\n  HH ( d, a, b, c, in[ 0], S32, UL(3936430074)); /* 42 */\n  HH ( c, d, a, b, in[ 3], S33, UL(3572445317)); /* 43 */\n  HH ( b, c, d, a, in[ 6], S34, UL(  76029189)); /* 44 */\n  HH ( a, b, c, d, in[ 9], S31, UL(3654602809)); /* 45 */\n  HH ( d, a, b, c, in[12], S32, UL(3873151461)); /* 46 */\n  HH ( c, d, a, b, in[15], S33, UL( 530742520)); /* 47 */\n  HH ( b, c, d, a, in[ 2], S34, UL(3299628645)); /* 48 */\n\n  /* Round 4 */\n#define S41 6\n#define S42 10\n#define S43 15\n#define S44 21\n  II ( a, b, c, d, in[ 0], S41, UL(4096336452)); /* 49 */\n  II ( d, a, b, c, in[ 7], S42, UL(1126891415)); /* 50 */\n  II ( c, d, a, b, in[14], S43, UL(2878612391)); /* 51 */\n  II ( b, c, d, a, in[ 5], S44, UL(4237533241)); /* 52 */\n  II ( a, b, c, d, in[12], S41, UL(1700485571)); /* 53 */\n  II ( d, a, b, c, in[ 3], S42, UL(2399980690)); /* 54 */\n  II ( c, d, a, b, in[10], S43, UL(4293915773)); /* 55 */\n  II ( b, c, d, a, in[ 1], S44, UL(2240044497)); /* 56 */\n  II ( a, b, c, d, in[ 8], S41, UL(1873313359)); /* 57 */\n  II ( d, a, b, c, in[15], S42, UL(4264355552)); /* 58 */\n  II ( c, d, a, b, in[ 6], S43, UL(2734768916)); /* 59 */\n  II ( b, c, d, a, in[13], S44, UL(1309151649)); /* 60 */\n  II ( a, b, c, d, in[ 4], S41, UL(4149444226)); /* 61 */\n  II ( d, a, b, c, in[11], S42, UL(3174756917)); /* 62 */\n  II ( c, d, a, b, in[ 2], S43, UL( 718787259)); /* 63 */\n  II ( b, c, d, a, in[ 9], S44, UL(3951481745)); /* 64 */\n\n  buf[0] += a;\n  buf[1] += b;\n  buf[2] += c;\n  buf[3] += d;\n}\n\n/*\n ***********************************************************************\n ** End of md5.c                                                      **\n ******************************** (cut) ********************************\n */\n"
  },
  {
    "path": "package/system/mtd/src/md5.h",
    "content": "/*\n ***********************************************************************\n ** md5.h -- header file for implementation of MD5                    **\n ** RSA Data Security, Inc. MD5 Message-Digest Algorithm              **\n ** Created: 2/17/90 RLR                                              **\n ** Revised: 12/27/90 SRD,AJ,BSK,JT Reference C version               **\n ** Revised (for MD5): RLR 4/27/91                                    **\n **   -- G modified to have y&~z instead of y&z                       **\n **   -- FF, GG, HH modified to add in last register done             **\n **   -- Access pattern: round 2 works mod 5, round 3 works mod 3     **\n **   -- distinct additive constant for each step                     **\n **   -- round 4 added, working mod 7                                 **\n ***********************************************************************\n */\n\n/*\n ***********************************************************************\n ** Copyright (C) 1990, RSA Data Security, Inc. All rights reserved.  **\n **                                                                   **\n ** License to copy and use this software is granted provided that    **\n ** it is identified as the \"RSA Data Security, Inc. MD5 Message-     **\n ** Digest Algorithm\" in all material mentioning or referencing this  **\n ** software or this function.                                        **\n **                                                                   **\n ** License is also granted to make and use derivative works          **\n ** provided that such works are identified as \"derived from the RSA  **\n ** Data Security, Inc. MD5 Message-Digest Algorithm\" in all          **\n ** material mentioning or referencing the derived work.              **\n **                                                                   **\n ** RSA Data Security, Inc. makes no representations concerning       **\n ** either the merchantability of this software or the suitability    **\n ** of this software for any particular purpose.  It is provided \"as  **\n ** is\" without express or implied warranty of any kind.              **\n **                                                                   **\n ** These notices must be retained in any copies of any part of this  **\n ** documentation and/or software.                                    **\n ***********************************************************************\n */\n\n#ifndef __MD5_INCLUDE__\n\n/* typedef a 32-bit type */\n#ifdef _LP64\ntypedef unsigned int UINT4;\ntypedef int          INT4;\n#else\ntypedef unsigned long UINT4;\ntypedef long          INT4;\n#endif\n#define _UINT4_T\n\n/* Data structure for MD5 (Message-Digest) computation */\ntypedef struct {\n  UINT4 i[2];                   /* number of _bits_ handled mod 2^64 */\n  UINT4 buf[4];                                    /* scratch buffer */\n  unsigned char in[64];                              /* input buffer */\n  unsigned char digest[16];     /* actual digest after MD5Final call */\n} MD5_CTX;\n\nvoid MD5_Init ();\nvoid MD5_Update ();\nvoid MD5_Final ();\n\n#define __MD5_INCLUDE__\n#endif /* __MD5_INCLUDE__ */\n"
  },
  {
    "path": "package/system/mtd/src/mtd.c",
    "content": "/*\n * mtd - simple memory technology device manipulation tool\n *\n * Copyright (C) 2005      Waldemar Brodkorb <wbx@dass-it.de>,\n * Copyright (C) 2005-2009 Felix Fietkau <nbd@nbd.name>\n *\n * This program is free software; you can redistribute it and/or\n * modify it under the terms of the GNU General Public License v2\n * as published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n * GNU General Public License for more details.\n *\n * You should have received a copy of the GNU General Public License\n * along with this program; if not, write to the Free Software\n * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.\n *\n *\n * The code is based on the linux-mtd examples.\n */\n\n#define _GNU_SOURCE\n#include <byteswap.h>\n#include <endian.h>\n#include <limits.h>\n#include <unistd.h>\n#include <stdlib.h>\n#include <stdio.h>\n#include <stdint.h>\n#include <signal.h>\n#include <sys/ioctl.h>\n#include <sys/syscall.h>\n#include <fcntl.h>\n#include <errno.h>\n#include <time.h>\n#include <string.h>\n#include <sys/ioctl.h>\n#include <sys/types.h>\n#include <sys/param.h>\n#include <sys/mount.h>\n#include <sys/stat.h>\n#include <sys/reboot.h>\n#include <linux/reboot.h>\n#include <mtd/mtd-user.h>\n#include \"crc32.h\"\n#include \"fis.h\"\n#include \"mtd.h\"\n\n#include <libubox/md5.h>\n\n#define MAX_ARGS 8\n#define JFFS2_DEFAULT_DIR\t\"\" /* directory name without /, empty means root dir */\n\n#define TRX_MAGIC\t\t0x48445230\t/* \"HDR0\" */\n#define SEAMA_MAGIC\t\t0x5ea3a417\n#define WRG_MAGIC\t\t0x20040220\n#define WRGG03_MAGIC\t\t0x20080321\n\n#if !defined(__BYTE_ORDER)\n#error \"Unknown byte order\"\n#endif\n\n#if __BYTE_ORDER == __BIG_ENDIAN\n#define cpu_to_be32(x)\t(x)\n#define be32_to_cpu(x)\t(x)\n#define le32_to_cpu(x)\tbswap_32(x)\n#elif __BYTE_ORDER == __LITTLE_ENDIAN\n#define cpu_to_be32(x)\tbswap_32(x)\n#define be32_to_cpu(x)\tbswap_32(x)\n#define le32_to_cpu(x)  (x)\n#else\n#error \"Unsupported endianness\"\n#endif\n\nenum mtd_image_format {\n\tMTD_IMAGE_FORMAT_UNKNOWN,\n\tMTD_IMAGE_FORMAT_TRX,\n\tMTD_IMAGE_FORMAT_SEAMA,\n\tMTD_IMAGE_FORMAT_WRG,\n\tMTD_IMAGE_FORMAT_WRGG03,\n};\n\nstatic char *buf = NULL;\nstatic char *imagefile = NULL;\nstatic enum mtd_image_format imageformat = MTD_IMAGE_FORMAT_UNKNOWN;\nstatic char *jffs2file = NULL, *jffs2dir = JFFS2_DEFAULT_DIR;\nstatic char *tpl_uboot_args_part;\nstatic int buflen = 0;\nint quiet;\nint no_erase;\nint mtdsize = 0;\nint erasesize = 0;\nint jffs2_skip_bytes=0;\nint mtdtype = 0;\nuint32_t opt_trxmagic = TRX_MAGIC;\n\nint mtd_open(const char *mtd, bool block)\n{\n\tFILE *fp;\n\tchar dev[PATH_MAX];\n\tint i;\n\tint ret;\n\tint flags = O_RDWR | O_SYNC;\n\tchar name[PATH_MAX];\n\n\tsnprintf(name, sizeof(name), \"\\\"%s\\\"\", mtd);\n\tif ((fp = fopen(\"/proc/mtd\", \"r\"))) {\n\t\twhile (fgets(dev, sizeof(dev), fp)) {\n\t\t\tif (sscanf(dev, \"mtd%d:\", &i) && strstr(dev, name)) {\n\t\t\t\tsnprintf(dev, sizeof(dev), \"/dev/mtd%s/%d\", (block ? \"block\" : \"\"), i);\n\t\t\t\tif ((ret=open(dev, flags))<0) {\n\t\t\t\t\tsnprintf(dev, sizeof(dev), \"/dev/mtd%s%d\", (block ? \"block\" : \"\"), i);\n\t\t\t\t\tret=open(dev, flags);\n\t\t\t\t}\n\t\t\t\tfclose(fp);\n\t\t\t\treturn ret;\n\t\t\t}\n\t\t}\n\t\tfclose(fp);\n\t}\n\n\treturn open(mtd, flags);\n}\n\nint mtd_check_open(const char *mtd)\n{\n\tstruct mtd_info_user mtdInfo;\n\tint fd;\n\n\tfd = mtd_open(mtd, false);\n\tif(fd < 0) {\n\t\tfprintf(stderr, \"Could not open mtd device: %s\\n\", mtd);\n\t\treturn -1;\n\t}\n\n\tif(ioctl(fd, MEMGETINFO, &mtdInfo)) {\n\t\tfprintf(stderr, \"Could not get MTD device info from %s\\n\", mtd);\n\t\tclose(fd);\n\t\treturn -1;\n\t}\n\tmtdsize = mtdInfo.size;\n\terasesize = mtdInfo.erasesize;\n\tmtdtype = mtdInfo.type;\n\n\treturn fd;\n}\n\nint mtd_block_is_bad(int fd, int offset)\n{\n\tint r = 0;\n\tloff_t o = offset;\n\n\tif (mtdtype == MTD_NANDFLASH)\n\t{\n\t\tr = ioctl(fd, MEMGETBADBLOCK, &o);\n\t\tif (r < 0)\n\t\t{\n\t\t\tfprintf(stderr, \"Failed to get erase block status\\n\");\n\t\t\texit(1);\n\t\t}\n\t}\n\treturn r;\n}\n\nint mtd_erase_block(int fd, int offset)\n{\n\tstruct erase_info_user mtdEraseInfo;\n\n\tmtdEraseInfo.start = offset;\n\tmtdEraseInfo.length = erasesize;\n\tioctl(fd, MEMUNLOCK, &mtdEraseInfo);\n\tif (ioctl (fd, MEMERASE, &mtdEraseInfo) < 0)\n\t\treturn -1;\n\n\treturn 0;\n}\n\nint mtd_write_buffer(int fd, const char *buf, int offset, int length)\n{\n\tlseek(fd, offset, SEEK_SET);\n\twrite(fd, buf, length);\n\treturn 0;\n}\n\nstatic int\nimage_check(int imagefd, const char *mtd)\n{\n\tuint32_t magic;\n\tint ret = 1;\n\tint bufread;\n\n\twhile (buflen < sizeof(magic)) {\n\t\tbufread = read(imagefd, buf + buflen, sizeof(magic) - buflen);\n\t\tif (bufread < 1)\n\t\t\tbreak;\n\n\t\tbuflen += bufread;\n\t}\n\n\tif (buflen < sizeof(magic)) {\n\t\tfprintf(stdout, \"Could not get image magic\\n\");\n\t\treturn 0;\n\t}\n\n\tmagic = ((uint32_t *)buf)[0];\n\n\tif (be32_to_cpu(magic) == opt_trxmagic)\n\t\timageformat = MTD_IMAGE_FORMAT_TRX;\n\telse if (be32_to_cpu(magic) == SEAMA_MAGIC)\n\t\timageformat = MTD_IMAGE_FORMAT_SEAMA;\n\telse if (le32_to_cpu(magic) == WRG_MAGIC)\n\t\timageformat = MTD_IMAGE_FORMAT_WRG;\n\telse if (le32_to_cpu(magic) == WRGG03_MAGIC)\n\t\timageformat = MTD_IMAGE_FORMAT_WRGG03;\n\n\tswitch (imageformat) {\n\tcase MTD_IMAGE_FORMAT_TRX:\n\t\tif (trx_check)\n\t\t\tret = trx_check(imagefd, mtd, buf, &buflen);\n\t\tbreak;\n\tcase MTD_IMAGE_FORMAT_SEAMA:\n\tcase MTD_IMAGE_FORMAT_WRG:\n\tcase MTD_IMAGE_FORMAT_WRGG03:\n\t\tbreak;\n\tdefault:\n#ifdef target_brcm\n\t\tif (!strcmp(mtd, \"firmware\"))\n\t\t\tret = 0;\n#endif\n\t\tbreak;\n\t}\n\n\treturn ret;\n}\n\nstatic int mtd_check(const char *mtd)\n{\n\tchar *next = NULL;\n\tchar *str = NULL;\n\tint fd;\n\n\tif (strchr(mtd, ':')) {\n\t\tstr = strdup(mtd);\n\t\tmtd = str;\n\t}\n\n\tdo {\n\t\tnext = strchr(mtd, ':');\n\t\tif (next) {\n\t\t\t*next = 0;\n\t\t\tnext++;\n\t\t}\n\n\t\tfd = mtd_check_open(mtd);\n\t\tif (fd < 0)\n\t\t\treturn 0;\n\n\t\tif (!buf)\n\t\t\tbuf = malloc(erasesize);\n\n\t\tclose(fd);\n\t\tmtd = next;\n\t} while (next);\n\n\tif (str)\n\t\tfree(str);\n\n\treturn 1;\n}\n\nstatic int\nmtd_unlock(const char *mtd)\n{\n\tstruct erase_info_user mtdLockInfo;\n\tchar *next = NULL;\n\tchar *str = NULL;\n\tint fd;\n\n\tif (strchr(mtd, ':')) {\n\t\tstr = strdup(mtd);\n\t\tmtd = str;\n\t}\n\n\tdo {\n\t\tnext = strchr(mtd, ':');\n\t\tif (next) {\n\t\t\t*next = 0;\n\t\t\tnext++;\n\t\t}\n\n\t\tfd = mtd_check_open(mtd);\n\t\tif(fd < 0) {\n\t\t\tfprintf(stderr, \"Could not open mtd device: %s\\n\", mtd);\n\t\t\texit(1);\n\t\t}\n\n\t\tif (quiet < 2)\n\t\t\tfprintf(stderr, \"Unlocking %s ...\\n\", mtd);\n\n\t\tmtdLockInfo.start = 0;\n\t\tmtdLockInfo.length = mtdsize;\n\t\tioctl(fd, MEMUNLOCK, &mtdLockInfo);\n\t\tclose(fd);\n\t\tmtd = next;\n\t} while (next);\n\n\tif (str)\n\t\tfree(str);\n\n\treturn 0;\n}\n\nstatic int\nmtd_erase(const char *mtd)\n{\n\tint fd;\n\tstruct erase_info_user mtdEraseInfo;\n\n\tif (quiet < 2)\n\t\tfprintf(stderr, \"Erasing %s ...\\n\", mtd);\n\n\tfd = mtd_check_open(mtd);\n\tif(fd < 0) {\n\t\tfprintf(stderr, \"Could not open mtd device: %s\\n\", mtd);\n\t\texit(1);\n\t}\n\n\tmtdEraseInfo.length = erasesize;\n\n\tfor (mtdEraseInfo.start = 0;\n\t\t mtdEraseInfo.start < mtdsize;\n\t\t mtdEraseInfo.start += erasesize) {\n\t\tif (mtd_block_is_bad(fd, mtdEraseInfo.start)) {\n\t\t\tif (!quiet)\n\t\t\t\tfprintf(stderr, \"\\nSkipping bad block at 0x%x   \", mtdEraseInfo.start);\n\t\t} else {\n\t\t\tioctl(fd, MEMUNLOCK, &mtdEraseInfo);\n\t\t\tif(ioctl(fd, MEMERASE, &mtdEraseInfo))\n\t\t\t\tfprintf(stderr, \"Failed to erase block on %s at 0x%x\\n\", mtd, mtdEraseInfo.start);\n\t\t}\n\t}\n\n\tclose(fd);\n\treturn 0;\n\n}\n\nstatic int\nmtd_dump(const char *mtd, int part_offset, int size)\n{\n\tint ret = 0, offset = 0;\n\tint fd;\n\tchar *buf;\n\n\tif (quiet < 2)\n\t\tfprintf(stderr, \"Dumping %s ...\\n\", mtd);\n\n\tfd = mtd_check_open(mtd);\n\tif(fd < 0) {\n\t\tfprintf(stderr, \"Could not open mtd device: %s\\n\", mtd);\n\t\treturn -1;\n\t}\n\n\tif (!size)\n\t\tsize = mtdsize;\n\n\tif (part_offset)\n\t\tlseek(fd, part_offset, SEEK_SET);\n\n\tbuf = malloc(erasesize);\n\tif (!buf)\n\t\treturn -1;\n\n\tdo {\n\t\tint len = (size > erasesize) ? (erasesize) : (size);\n\t\tint rlen = read(fd, buf, len);\n\n\t\tif (rlen < 0) {\n\t\t\tif (errno == EINTR)\n\t\t\t\tcontinue;\n\t\t\tret = -1;\n\t\t\tgoto out;\n\t\t}\n\t\tif (!rlen || rlen != len)\n\t\t\tbreak;\n\t\tif (mtd_block_is_bad(fd, offset)) {\n\t\t\tfprintf(stderr, \"skipping bad block at 0x%08x\\n\", offset);\n\t\t} else {\n\t\t\tsize -= rlen;\n\t\t\twrite(1, buf, rlen);\n\t\t}\n\t\toffset += rlen;\n\t} while (size > 0);\n\nout:\n\tclose(fd);\n\treturn ret;\n}\n\nstatic int\nmtd_verify(const char *mtd, char *file)\n{\n\tuint32_t f_md5[4], m_md5[4];\n\tstruct stat s;\n\tmd5_ctx_t ctx;\n\tint ret = 0;\n\tint fd;\n\n\tif (quiet < 2)\n\t\tfprintf(stderr, \"Verifying %s against %s ...\\n\", mtd, file);\n\n\tif (stat(file, &s) || md5sum(file, f_md5) < 0) {\n\t\tfprintf(stderr, \"Failed to hash %s\\n\", file);\n\t\treturn -1;\n\t}\n\n\tfd = mtd_check_open(mtd);\n\tif(fd < 0) {\n\t\tfprintf(stderr, \"Could not open mtd device: %s\\n\", mtd);\n\t\treturn -1;\n\t}\n\n\tmd5_begin(&ctx);\n\tdo {\n\t\tchar buf[256];\n\t\tint len = (s.st_size > sizeof(buf)) ? (sizeof(buf)) : (s.st_size);\n\t\tint rlen = read(fd, buf, len);\n\n\t\tif (rlen < 0) {\n\t\t\tif (errno == EINTR)\n\t\t\t\tcontinue;\n\t\t\tret = -1;\n\t\t\tgoto out;\n\t\t}\n\t\tif (!rlen)\n\t\t\tbreak;\n\t\tmd5_hash(buf, rlen, &ctx);\n\t\ts.st_size -= rlen;\n\t} while (s.st_size > 0);\n\n\tmd5_end(m_md5, &ctx);\n\n\tfprintf(stderr, \"%08x%08x%08x%08x - %s\\n\", m_md5[0], m_md5[1], m_md5[2], m_md5[3], mtd);\n\tfprintf(stderr, \"%08x%08x%08x%08x - %s\\n\", f_md5[0], f_md5[1], f_md5[2], f_md5[3], file);\n\n\tret = memcmp(f_md5, m_md5, sizeof(m_md5));\n\tif (!ret)\n\t\tfprintf(stderr, \"Success\\n\");\n\telse\n\t\tfprintf(stderr, \"Failed\\n\");\n\nout:\n\tclose(fd);\n\treturn ret;\n}\n\nstatic void\nindicate_writing(const char *mtd)\n{\n\tif (quiet < 2)\n\t\tfprintf(stderr, \"\\nWriting from %s to %s ... \", imagefile, mtd);\n\n\tif (!quiet)\n\t\tfprintf(stderr, \" [ ]\");\n}\n\nstatic int\nmtd_write(int imagefd, const char *mtd, char *fis_layout, size_t part_offset)\n{\n\tchar *next = NULL;\n\tchar *str = NULL;\n\tint fd, result;\n\tssize_t r, w, e;\n\tssize_t skip = 0;\n\tuint32_t offset = 0;\n\tint buflen_raw = 0;\n\tint jffs2_replaced = 0;\n\tint skip_bad_blocks = 0;\n\n#ifdef FIS_SUPPORT\n\tstatic struct fis_part new_parts[MAX_ARGS];\n\tstatic struct fis_part old_parts[MAX_ARGS];\n\tstruct fis_part *cur_part = NULL;\n\tint n_new = 0, n_old = 0;\n\n\tif (fis_layout) {\n\t\tconst char *tmp = mtd;\n\t\tchar *word, *brkt;\n\t\tint ret;\n\n\t\tmemset(&old_parts, 0, sizeof(old_parts));\n\t\tmemset(&new_parts, 0, sizeof(new_parts));\n\t\tif (!part_offset)\n\t\t\tcur_part = new_parts;\n\n\t\tdo {\n\t\t\tnext = strchr(tmp, ':');\n\t\t\tif (!next)\n\t\t\t\tnext = (char *) tmp + strlen(tmp);\n\n\t\t\tmemcpy(old_parts[n_old].name, tmp, next - tmp);\n\n\t\t\tn_old++;\n\t\t\ttmp = next + 1;\n\t\t} while(*next);\n\n\t\tfor (word = strtok_r(fis_layout, \",\", &brkt);\n\t\t     word;\n\t\t\t word = strtok_r(NULL, \",\", &brkt)) {\n\n\t\t\ttmp = strtok(word, \":\");\n\t\t\tstrncpy((char *) new_parts[n_new].name, tmp, sizeof(new_parts[n_new].name) - 1);\n\n\t\t\ttmp = strtok(NULL, \":\");\n\t\t\tif (!tmp)\n\t\t\t\tgoto next;\n\n\t\t\tnew_parts[n_new].size = strtoul(tmp, NULL, 0);\n\n\t\t\ttmp = strtok(NULL, \":\");\n\t\t\tif (!tmp)\n\t\t\t\tgoto next;\n\n\t\t\tnew_parts[n_new].loadaddr = strtoul(tmp, NULL, 16);\nnext:\n\t\t\tn_new++;\n\t\t}\n\t\tret = fis_validate(old_parts, n_old, new_parts, n_new);\n\t\tif (ret < 0) {\n\t\t\tfprintf(stderr, \"Failed to validate the new FIS partition table\\n\");\n\t\t\texit(1);\n\t\t}\n\t\tif (ret == 0)\n\t\t\tfis_layout = NULL;\n\t}\n#endif\n\n\tif (strchr(mtd, ':')) {\n\t\tstr = strdup(mtd);\n\t\tmtd = str;\n\t}\n\n\tr = 0;\n\nresume:\n\tnext = strchr(mtd, ':');\n\tif (next) {\n\t\t*next = 0;\n\t\tnext++;\n\t}\n\n\tfd = mtd_check_open(mtd);\n\tif(fd < 0) {\n\t\tfprintf(stderr, \"Could not open mtd device: %s\\n\", mtd);\n\t\texit(1);\n\t}\n\tif (part_offset > 0) {\n\t\tfprintf(stderr, \"Seeking on mtd device '%s' to: %zu\\n\", mtd, part_offset);\n\t\tlseek(fd, part_offset, SEEK_SET);\n\t}\n\n\t/* Write TP-Link recovery flag */\n\tif (tpl_uboot_args_part && mtd_tpl_recoverflag_write) {\n\t\tif (quiet < 2)\n\t\t\tfprintf(stderr, \"Writing recovery flag to %s\\n\", tpl_uboot_args_part);\n\t\tresult = mtd_tpl_recoverflag_write(tpl_uboot_args_part, true);\n\t\tif (result < 0) {\n\t\t\tfprintf(stderr, \"Could not write TP-Link recovery flag to %s: %i\", mtd, result);\n\t\t\texit(1);\n\t\t}\n\t}\n\n\tindicate_writing(mtd);\n\n\tw = e = 0;\n\tfor (;;) {\n\t\t/* buffer may contain data already (from trx check or last mtd partition write attempt) */\n\t\twhile (buflen < erasesize) {\n\t\t\tr = read(imagefd, buf + buflen, erasesize - buflen);\n\t\t\tif (r < 0) {\n\t\t\t\tif ((errno == EINTR) || (errno == EAGAIN))\n\t\t\t\t\tcontinue;\n\t\t\t\telse {\n\t\t\t\t\tperror(\"read\");\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t}\n\n\t\t\tif (r == 0)\n\t\t\t\tbreak;\n\n\t\t\tbuflen += r;\n\t\t}\n\n\t\tif (buflen_raw == 0)\n\t\t\tbuflen_raw = buflen;\n\n\t\tif (buflen == 0)\n\t\t\tbreak;\n\n\t\tif (buflen < erasesize) {\n\t\t\t/* Pad block to eraseblock size */\n\t\t\tmemset(&buf[buflen], 0xff, erasesize - buflen);\n\t\t\tbuflen = erasesize;\n\t\t}\n\n\t\tif (skip > 0) {\n\t\t\tskip -= buflen;\n\t\t\tbuflen_raw = 0;\n\t\t\tbuflen = 0;\n\t\t\tif (skip <= 0)\n\t\t\t\tindicate_writing(mtd);\n\n\t\t\tcontinue;\n\t\t}\n\n\t\tif (jffs2file && w >= jffs2_skip_bytes) {\n\t\t\tif (memcmp(buf, JFFS2_EOF, sizeof(JFFS2_EOF) - 1) == 0) {\n\t\t\t\tif (!quiet)\n\t\t\t\t\tfprintf(stderr, \"\\b\\b\\b   \");\n\t\t\t\tif (quiet < 2)\n\t\t\t\t\tfprintf(stderr, \"\\nAppending jffs2 data from %s to %s..\\n.\", jffs2file, mtd);\n\t\t\t\t/* got an EOF marker - this is the place to add some jffs2 data */\n\t\t\t\tskip = mtd_replace_jffs2(mtd, fd, e, jffs2file);\n\t\t\t\tjffs2_replaced = 1;\n\n\t\t\t\t/* don't add it again */\n\t\t\t\tjffs2file = NULL;\n\n\t\t\t\tw += skip;\n\t\t\t\te += skip;\n\t\t\t\tskip -= buflen;\n\t\t\t\tbuflen_raw = 0;\n\t\t\t\tbuflen = 0;\n\t\t\t\toffset = 0;\n\t\t\t\tcontinue;\n\t\t\t}\n\t\t\t/* no EOF marker, make sure we figure out the last inode number\n\t\t\t * before appending some data */\n\t\t\tmtd_parse_jffs2data(buf, jffs2dir);\n\t\t}\n\n\t\t/* need to erase the next block before writing data to it */\n\t\tif(!no_erase)\n\t\t{\n\t\t\twhile (w + buflen > e - skip_bad_blocks) {\n\t\t\t\tif (!quiet)\n\t\t\t\t\tfprintf(stderr, \"\\b\\b\\b[e]\");\n\n\t\t\t\tif (mtd_block_is_bad(fd, e)) {\n\t\t\t\t\tif (!quiet)\n\t\t\t\t\t\tfprintf(stderr, \"\\nSkipping bad block at 0x%08zx   \", e);\n\n\t\t\t\t\tskip_bad_blocks += erasesize;\n\t\t\t\t\te += erasesize;\n\n\t\t\t\t\t// Move the file pointer along over the bad block.\n\t\t\t\t\tlseek(fd, erasesize, SEEK_CUR);\n\t\t\t\t\tcontinue;\n\t\t\t\t}\n\n\t\t\t\tif (mtd_erase_block(fd, e + part_offset) < 0) {\n\t\t\t\t\tif (next) {\n\t\t\t\t\t\tif (w < e) {\n\t\t\t\t\t\t\twrite(fd, buf + offset, e - w);\n\t\t\t\t\t\t\toffset = e - w;\n\t\t\t\t\t\t}\n\t\t\t\t\t\tw = 0;\n\t\t\t\t\t\te = 0;\n\t\t\t\t\t\tclose(fd);\n\t\t\t\t\t\tmtd = next;\n\t\t\t\t\t\tfprintf(stderr, \"\\b\\b\\b   \\n\");\n\t\t\t\t\t\tgoto resume;\n\t\t\t\t\t} else {\n\t\t\t\t\t\tfprintf(stderr, \"Failed to erase block\\n\");\n\t\t\t\t\t\texit(1);\n\t\t\t\t\t}\n\t\t\t\t}\n\n\t\t\t\t/* erase the chunk */\n\t\t\t\te += erasesize;\n\t\t\t}\n\t\t}\n\n\t\tif (!quiet)\n\t\t\tfprintf(stderr, \"\\b\\b\\b[w]\");\n\n\t\tif ((result = write(fd, buf + offset, buflen)) < buflen) {\n\t\t\tif (result < 0) {\n\t\t\t\tfprintf(stderr, \"Error writing image.\\n\");\n\t\t\t\texit(1);\n\t\t\t} else {\n\t\t\t\tfprintf(stderr, \"Insufficient space.\\n\");\n\t\t\t\texit(1);\n\t\t\t}\n\t\t}\n\t\tw += buflen;\n\n#ifdef FIS_SUPPORT\n\t\tif (cur_part && cur_part->size\n\t\t&& cur_part < &new_parts[MAX_ARGS - 1]\n\t\t&& cur_part->length + buflen_raw > cur_part->size)\n\t\t\tcur_part++;\n\t\tif (cur_part) {\n\t\t\tcur_part->length += buflen_raw;\n\t\t\tcur_part->crc = crc32(cur_part->crc, buf, buflen_raw);\n\t\t}\n#endif\n\t\tbuflen_raw = 0;\n\t\tbuflen = 0;\n\t\toffset = 0;\n\t}\n\n\tif (jffs2_replaced) {\n\t\tswitch (imageformat) {\n\t\tcase MTD_IMAGE_FORMAT_TRX:\n\t\t\tif (trx_fixup)\n\t\t\t\ttrx_fixup(fd, mtd);\n\t\t\tbreak;\n\t\tcase MTD_IMAGE_FORMAT_SEAMA:\n\t\t\tif (mtd_fixseama)\n\t\t\t\tmtd_fixseama(mtd, 0, 0);\n\t\t\tbreak;\n\t\tcase MTD_IMAGE_FORMAT_WRG:\n\t\t\tif (mtd_fixwrg)\n\t\t\t\tmtd_fixwrg(mtd, 0, 0);\n\t\t\tbreak;\n\t\tcase MTD_IMAGE_FORMAT_WRGG03:\n\t\t\tif (mtd_fixwrgg)\n\t\t\t\tmtd_fixwrgg(mtd, 0, 0);\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tbreak;\n\t\t}\n\t}\n\n\tif (!quiet)\n\t\tfprintf(stderr, \"\\b\\b\\b\\b    \");\n\n\tif (quiet < 2)\n\t\tfprintf(stderr, \"\\n\");\n\n#ifdef FIS_SUPPORT\n\tif (fis_layout) {\n\t\tif (fis_remap(old_parts, n_old, new_parts, n_new) < 0)\n\t\t\tfprintf(stderr, \"Failed to update the FIS partition table\\n\");\n\t}\n#endif\n\n\tclose(fd);\n\n\t/* Clear TP-Link recovery flag */\n\tif (tpl_uboot_args_part && mtd_tpl_recoverflag_write) {\n\t\tif (quiet < 2)\n\t\t\tfprintf(stderr, \"Removing recovery flag from %s\\n\", tpl_uboot_args_part);\n\t\tresult = mtd_tpl_recoverflag_write(tpl_uboot_args_part, false);\n\t\tif (result < 0) {\n\t\t\tfprintf(stderr, \"Could not clear TP-Link recovery flag to %s: %i\", mtd, result);\n\t\t\texit(1);\n\t\t}\n\t}\n\n\treturn 0;\n}\n\nstatic void usage(void)\n{\n\tfprintf(stderr, \"Usage: mtd [<options> ...] <command> [<arguments> ...] <device>[:<device>...]\\n\\n\"\n\t\"The device is in the format of mtdX (eg: mtd4) or its label.\\n\"\n\t\"mtd recognizes these commands:\\n\"\n\t\"        unlock                  unlock the device\\n\"\n\t\"        refresh                 refresh mtd partition\\n\"\n\t\"        erase                   erase all data on device\\n\"\n\t\"        verify <imagefile>|-    verify <imagefile> (use - for stdin) to device\\n\"\n\t\"        write <imagefile>|-     write <imagefile> (use - for stdin) to device\\n\"\n\t\"        jffs2write <file>       append <file> to the jffs2 partition on the device\\n\");\n\tif (mtd_resetbc) {\n\t    fprintf(stderr,\n\t\"        resetbc <device>        reset the uboot boot counter\\n\");\n\t}\n\tif (mtd_fixtrx) {\n\t    fprintf(stderr,\n\t\"        fixtrx                  fix the checksum in a trx header on first boot\\n\");\n\t}\n\tif (mtd_fixseama) {\n\t    fprintf(stderr,\n\t\"        fixseama                fix the checksum in a seama header on first boot\\n\");\n\t}\n\tif (mtd_fixwrg) {\n\t    fprintf(stderr,\n\t\"        fixwrg                  fix the checksum in a wrg header on first boot\\n\");\n\t}\n\tif (mtd_fixwrgg) {\n\t    fprintf(stderr,\n\t\"        fixwrgg                 fix the checksum in a wrgg header on first boot\\n\");\n\t}\n\tfprintf(stderr,\n\t\"Following options are available:\\n\"\n\t\"        -q                      quiet mode (once: no [w] on writing,\\n\"\n\t\"                                           twice: no status messages)\\n\"\n\t\"        -n                      write without first erasing the blocks\\n\"\n\t\"        -r                      reboot after successful command\\n\"\n\t\"        -f                      force write without trx checks\\n\"\n\t\"        -e <device>             erase <device> before executing the command\\n\"\n\t\"        -d <name>               directory for jffs2write, defaults to \\\"tmp\\\"\\n\"\n\t\"        -j <name>               integrate <file> into jffs2 data when writing an image\\n\"\n\t\"        -s <number>             skip the first n bytes when appending data to the jffs2 partiton, defaults to \\\"0\\\"\\n\"\n\t\"        -p <number>             write beginning at partition offset\\n\"\n\t\"        -l <length>             the length of data that we want to dump\\n\");\n\tif (mtd_fixtrx) {\n\t    fprintf(stderr,\n\t\"        -M <magic>              magic number of the image header in the partition (for fixtrx)\\n\"\n\t\"        -o offset               offset of the image header in the partition(for fixtrx)\\n\");\n\t}\n\tif (mtd_fixtrx || mtd_fixseama || mtd_fixwrg || mtd_fixwrgg) {\n\t\tfprintf(stderr,\n\t\"        -c datasize             amount of data to be used for checksum calculation (for fixtrx / fixseama / fixwrg / fixwrgg)\\n\");\n\t}\n\tif (mtd_tpl_recoverflag_write) {\n\t\tfprintf(stderr,\n\t\"        -t <partition>          write TP-Link recovery-flag to <partition> (for write)\\n\");\n\t}\n\tfprintf(stderr,\n#ifdef FIS_SUPPORT\n\t\"        -F <part>[:<size>[:<entrypoint>]][,<part>...]\\n\"\n\t\"                                alter the fis partition table to create new partitions replacing\\n\"\n\t\"                                the partitions provided as argument to the write command\\n\"\n\t\"                                (only valid together with the write command)\\n\"\n#endif\n\t\"\\n\"\n\t\"Example: To write linux.trx to mtd4 labeled as linux and reboot afterwards\\n\"\n\t\"         mtd -r write linux.trx linux\\n\\n\");\n\texit(1);\n}\n\nstatic void do_reboot(void)\n{\n\tfprintf(stderr, \"Rebooting ...\\n\");\n\tfflush(stderr);\n\n\t/* try regular reboot method first */\n\tsystem(\"/sbin/reboot\");\n\tsleep(2);\n\n\t/* if we're still alive at this point, force the kernel to reboot */\n\tsyscall(SYS_reboot,LINUX_REBOOT_MAGIC1,LINUX_REBOOT_MAGIC2,LINUX_REBOOT_CMD_RESTART,NULL);\n}\n\nint main (int argc, char **argv)\n{\n\tint ch, i, boot, imagefd = 0, force, unlocked;\n\tchar *erase[MAX_ARGS], *device = NULL;\n\tchar *fis_layout = NULL;\n\tsize_t offset = 0, data_size = 0, part_offset = 0, dump_len = 0;\n\tenum {\n\t\tCMD_ERASE,\n\t\tCMD_WRITE,\n\t\tCMD_UNLOCK,\n\t\tCMD_JFFS2WRITE,\n\t\tCMD_FIXTRX,\n\t\tCMD_FIXSEAMA,\n\t\tCMD_FIXWRG,\n\t\tCMD_FIXWRGG,\n\t\tCMD_VERIFY,\n\t\tCMD_DUMP,\n\t\tCMD_RESETBC,\n\t} cmd = -1;\n\n\terase[0] = NULL;\n\tboot = 0;\n\tforce = 0;\n\tbuflen = 0;\n\tquiet = 0;\n\tno_erase = 0;\n\n\twhile ((ch = getopt(argc, argv,\n#ifdef FIS_SUPPORT\n\t\t\t\"F:\"\n#endif\n\t\t\t\"frnqe:d:s:j:p:o:c:t:l:M:\")) != -1)\n\t\tswitch (ch) {\n\t\t\tcase 'f':\n\t\t\t\tforce = 1;\n\t\t\t\tbreak;\n\t\t\tcase 'r':\n\t\t\t\tboot = 1;\n\t\t\t\tbreak;\n\t\t\tcase 'n':\n\t\t\t\tno_erase = 1;\n\t\t\t\tbreak;\n\t\t\tcase 'j':\n\t\t\t\tjffs2file = optarg;\n\t\t\t\tbreak;\n\t\t\tcase 's':\n\t\t\t\terrno = 0;\n\t\t\t\tjffs2_skip_bytes = strtoul(optarg, 0, 0);\n\t\t\t\tif (errno) {\n\t\t\t\t\t\tfprintf(stderr, \"-s: illegal numeric string\\n\");\n\t\t\t\t\t\tusage();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 'q':\n\t\t\t\tquiet++;\n\t\t\t\tbreak;\n\t\t\tcase 'e':\n\t\t\t\ti = 0;\n\t\t\t\twhile ((erase[i] != NULL) && ((i + 1) < MAX_ARGS))\n\t\t\t\t\ti++;\n\n\t\t\t\terase[i++] = optarg;\n\t\t\t\terase[i] = NULL;\n\t\t\t\tbreak;\n\t\t\tcase 'd':\n\t\t\t\tjffs2dir = optarg;\n\t\t\t\tbreak;\n\t\t\tcase 'p':\n\t\t\t\terrno = 0;\n\t\t\t\tpart_offset = strtoul(optarg, 0, 0);\n\t\t\t\tif (errno) {\n\t\t\t\t\tfprintf(stderr, \"-p: illegal numeric string\\n\");\n\t\t\t\t\tusage();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 'l':\n\t\t\t\terrno = 0;\n\t\t\t\tdump_len = strtoul(optarg, 0, 0);\n\t\t\t\tif (errno) {\n\t\t\t\t\tfprintf(stderr, \"-l: illegal numeric string\\n\");\n\t\t\t\t\tusage();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 'M':\n\t\t\t\terrno = 0;\n\t\t\t\topt_trxmagic = strtoul(optarg, 0, 0);\n\t\t\t\tif (errno) {\n\t\t\t\t\tfprintf(stderr, \"-M: illegal numeric string\\n\");\n\t\t\t\t\tusage();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 'o':\n\t\t\t\terrno = 0;\n\t\t\t\toffset = strtoul(optarg, 0, 0);\n\t\t\t\tif (errno) {\n\t\t\t\t\tfprintf(stderr, \"-o: illegal numeric string\\n\");\n\t\t\t\t\tusage();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 'c':\n\t\t\t\terrno = 0;\n\t\t\t\tdata_size = strtoul(optarg, 0, 0);\n\t\t\t\tif (errno) {\n\t\t\t\t\tfprintf(stderr, \"-c: illegal numeric string\\n\");\n\t\t\t\t\tusage();\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 't':\n\t\t\t\ttpl_uboot_args_part = optarg;\n\t\t\t\tbreak;\n#ifdef FIS_SUPPORT\n\t\t\tcase 'F':\n\t\t\t\tfis_layout = optarg;\n\t\t\t\tbreak;\n#endif\n\t\t\tcase '?':\n\t\t\tdefault:\n\t\t\t\tusage();\n\t\t}\n\targc -= optind;\n\targv += optind;\n\n\tif (argc < 2)\n\t\tusage();\n\n\tif ((strcmp(argv[0], \"unlock\") == 0) && (argc == 2)) {\n\t\tcmd = CMD_UNLOCK;\n\t\tdevice = argv[1];\n\t} else if ((strcmp(argv[0], \"erase\") == 0) && (argc == 2)) {\n\t\tcmd = CMD_ERASE;\n\t\tdevice = argv[1];\n\t} else if (((strcmp(argv[0], \"resetbc\") == 0) && (argc == 2)) && mtd_resetbc) {\n\t\tcmd = CMD_RESETBC;\n\t\tdevice = argv[1];\n\t} else if (((strcmp(argv[0], \"fixtrx\") == 0) && (argc == 2)) && mtd_fixtrx) {\n\t\tcmd = CMD_FIXTRX;\n\t\tdevice = argv[1];\n\t} else if (((strcmp(argv[0], \"fixseama\") == 0) && (argc == 2)) && mtd_fixseama) {\n\t\tcmd = CMD_FIXSEAMA;\n\t\tdevice = argv[1];\n\t} else if (((strcmp(argv[0], \"fixwrg\") == 0) && (argc == 2)) && mtd_fixwrg) {\n\t\tcmd = CMD_FIXWRG;\n\t\tdevice = argv[1];\n\t} else if (((strcmp(argv[0], \"fixwrgg\") == 0) && (argc == 2)) && mtd_fixwrgg) {\n\t\tcmd = CMD_FIXWRGG;\n\t\tdevice = argv[1];\n\t} else if ((strcmp(argv[0], \"verify\") == 0) && (argc == 3)) {\n\t\tcmd = CMD_VERIFY;\n\t\timagefile = argv[1];\n\t\tdevice = argv[2];\n\t} else if ((strcmp(argv[0], \"dump\") == 0) && (argc == 2)) {\n\t\tcmd = CMD_DUMP;\n\t\tdevice = argv[1];\n\t} else if ((strcmp(argv[0], \"write\") == 0) && (argc == 3)) {\n\t\tcmd = CMD_WRITE;\n\t\tdevice = argv[2];\n\n\t\tif (strcmp(argv[1], \"-\") == 0) {\n\t\t\timagefile = \"<stdin>\";\n\t\t\timagefd = 0;\n\t\t} else {\n\t\t\timagefile = argv[1];\n\t\t\tif ((imagefd = open(argv[1], O_RDONLY)) < 0) {\n\t\t\t\tfprintf(stderr, \"Couldn't open image file: %s!\\n\", imagefile);\n\t\t\t\texit(1);\n\t\t\t}\n\t\t}\n\n\t\tif (!mtd_check(device)) {\n\t\t\tfprintf(stderr, \"Can't open device for writing!\\n\");\n\t\t\texit(1);\n\t\t}\n\t\t/* check trx file before erasing or writing anything */\n\t\tif (!image_check(imagefd, device) && !force) {\n\t\t\tfprintf(stderr, \"Image check failed.\\n\");\n\t\t\texit(1);\n\t\t}\n\t} else if ((strcmp(argv[0], \"jffs2write\") == 0) && (argc == 3)) {\n\t\tcmd = CMD_JFFS2WRITE;\n\t\tdevice = argv[2];\n\n\t\timagefile = argv[1];\n\t\tif (!mtd_check(device)) {\n\t\t\tfprintf(stderr, \"Can't open device for writing!\\n\");\n\t\t\texit(1);\n\t\t}\n\t} else {\n\t\tusage();\n\t}\n\n\tsync();\n\n\ti = 0;\n\tunlocked = 0;\n\twhile (erase[i] != NULL) {\n\t\tmtd_unlock(erase[i]);\n\t\tmtd_erase(erase[i]);\n\t\tif (strcmp(erase[i], device) == 0)\n\t\t\tunlocked = 1;\n\t\ti++;\n\t}\n\n\tswitch (cmd) {\n\t\tcase CMD_UNLOCK:\n\t\t\tif (!unlocked)\n\t\t\t\tmtd_unlock(device);\n\t\t\tbreak;\n\t\tcase CMD_VERIFY:\n\t\t\tmtd_verify(device, imagefile);\n\t\t\tbreak;\n\t\tcase CMD_DUMP:\n\t\t\tmtd_dump(device, offset, dump_len);\n\t\t\tbreak;\n\t\tcase CMD_ERASE:\n\t\t\tif (!unlocked)\n\t\t\t\tmtd_unlock(device);\n\t\t\tmtd_erase(device);\n\t\t\tbreak;\n\t\tcase CMD_WRITE:\n\t\t\tif (!unlocked)\n\t\t\t\tmtd_unlock(device);\n\t\t\tmtd_write(imagefd, device, fis_layout, part_offset);\n\t\t\tbreak;\n\t\tcase CMD_JFFS2WRITE:\n\t\t\tif (!unlocked)\n\t\t\t\tmtd_unlock(device);\n\t\t\tmtd_write_jffs2(device, imagefile, jffs2dir);\n\t\t\tbreak;\n\t\tcase CMD_FIXTRX:\n\t\t\tif (mtd_fixtrx) {\n\t\t\t\tmtd_fixtrx(device, offset, data_size);\n\t\t\t}\n\t\t\tbreak;\n\t\tcase CMD_RESETBC:\n\t\t\tif (mtd_resetbc) {\n\t\t\t\tmtd_resetbc(device);\n\t\t\t}\n\t\t\tbreak;\n\t\tcase CMD_FIXSEAMA:\n\t\t\tif (mtd_fixseama)\n\t\t\t\tmtd_fixseama(device, 0, data_size);\n\t\t\tbreak;\n\t\tcase CMD_FIXWRG:\n\t\t\tif (mtd_fixwrg)\n\t\t\t\tmtd_fixwrg(device, 0, data_size);\n\t\t\tbreak;\n\t\tcase CMD_FIXWRGG:\n\t\t\tif (mtd_fixwrgg)\n\t\t\t\tmtd_fixwrgg(device, 0, data_size);\n\t\t\tbreak;\n\t}\n\n\tsync();\n\n\tif (boot)\n\t\tdo_reboot();\n\n\treturn 0;\n}\n"
  },
  {
    "path": "package/system/mtd/src/mtd.h",
    "content": "#ifndef __mtd_h\n#define __mtd_h\n\n#include <stdbool.h>\n#include <stdint.h>\n\n#if defined(target_bcm47xx) || defined(target_bcm53xx)\n#define target_brcm 1\n#endif\n\n#define JFFS2_EOF \"\\xde\\xad\\xc0\\xde\"\n\nextern int quiet;\nextern int mtdsize;\nextern int erasesize;\nextern uint32_t opt_trxmagic;\n\nextern int mtd_open(const char *mtd, bool block);\nextern int mtd_check_open(const char *mtd);\nextern int mtd_block_is_bad(int fd, int offset);\nextern int mtd_erase_block(int fd, int offset);\nextern int mtd_write_buffer(int fd, const char *buf, int offset, int length);\nextern int mtd_write_jffs2(const char *mtd, const char *filename, const char *dir);\nextern int mtd_replace_jffs2(const char *mtd, int fd, int ofs, const char *filename);\nextern void mtd_parse_jffs2data(const char *buf, const char *dir);\n\n/* target specific functions */\nextern int trx_fixup(int fd, const char *name)  __attribute__ ((weak));\nextern int trx_check(int imagefd, const char *mtd, char *buf, int *len) __attribute__ ((weak));\nextern int mtd_fixtrx(const char *mtd, size_t offset, size_t data_size) __attribute__ ((weak));\nextern int mtd_fixseama(const char *mtd, size_t offset, size_t data_size) __attribute__ ((weak));\nextern int mtd_fixwrg(const char *mtd, size_t offset, size_t data_size) __attribute__ ((weak));\nextern int mtd_fixwrgg(const char *mtd, size_t offset, size_t data_size) __attribute__ ((weak));\nextern int mtd_resetbc(const char *mtd) __attribute__ ((weak));\nextern int mtd_tpl_recoverflag_write(const char *mtd, const bool recovery_active) __attribute__ ((weak));\n#endif /* __mtd_h */\n"
  },
  {
    "path": "package/system/mtd/src/seama.c",
    "content": "/*\n * seama.c\n *\n * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>\n *\n * Based on the trx fixup code:\n *   Copyright (C) 2005 Mike Baker\n *   Copyright (C) 2008 Felix Fietkau <nbd@nbd.name>\n *\n * This program is free software; you can redistribute it and/or\n * modify it under the terms of the GNU General Public License\n * as published by the Free Software Foundation; either version 2\n * of the License, or (at your option) any later version.\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n * GNU General Public License for more details.\n *\n * You should have received a copy of the GNU General Public License\n * along with this program; if not, write to the Free Software\n * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.\n */\n\n#include <endian.h>\n#include <stdio.h>\n#include <stdlib.h>\n#include <stddef.h>\n#include <unistd.h>\n#include <fcntl.h>\n#include <sys/mman.h>\n#include <sys/stat.h>\n#include <string.h>\n#include <errno.h>\n#include <arpa/inet.h>\n\n#include <sys/ioctl.h>\n#include <mtd/mtd-user.h>\n#include \"mtd.h\"\n#include \"seama.h\"\n#include \"md5.h\"\n\n#if __BYTE_ORDER == __BIG_ENDIAN\n#define STORE32_LE(X)           ((((X) & 0x000000FF) << 24) | (((X) & 0x0000FF00) << 8) | (((X) & 0x00FF0000) >> 8) | (((X) & 0xFF000000) >> 24))\n#elif __BYTE_ORDER == __LITTLE_ENDIAN\n#define STORE32_LE(X)           (X)\n#else\n#error unknown endianness!\n#endif\n\nssize_t pread(int fd, void *buf, size_t count, off_t offset);\nssize_t pwrite(int fd, const void *buf, size_t count, off_t offset);\n\nint\nseama_fix_md5(struct seama_entity_header *shdr, int fd, size_t data_offset, size_t data_size)\n{\n\tchar *buf;\n\tssize_t res;\n\tMD5_CTX ctx;\n\tunsigned char digest[16];\n\tint i;\n\tint err = 0;\n\n\tbuf = malloc(data_size);\n\tif (!buf) {\n\t\terr = -ENOMEM;\n\t\tgoto err_out;\n\t}\n\n\tres = pread(fd, buf, data_size, data_offset);\n\tif (res != data_size) {\n\t\tperror(\"pread\");\n\t\terr = -EIO;\n\t\tgoto err_free;\n\t}\n\n\tMD5_Init(&ctx);\n\tMD5_Update(&ctx, buf, data_size);\n\tMD5_Final(digest, &ctx);\n\n\tif (!memcmp(digest, shdr->md5, sizeof(digest))) {\n\t\tif (quiet < 2)\n\t\t\tfprintf(stderr, \"the header is fixed already\\n\");\n\t\treturn -1;\n\t}\n\n\tif (quiet < 2) {\n\t\tfprintf(stderr, \"new size:%u, new MD5: \", data_size);\n\t\tfor (i = 0; i < sizeof(digest); i++)\n\t\t\tfprintf(stderr, \"%02x\", digest[i]);\n\n\t\tfprintf(stderr, \"\\n\");\n\t}\n\n\t/* update the size in the image */\n\tshdr->size = htonl(data_size);\n\n\t/* update the checksum in the image */\n\tmemcpy(shdr->md5, digest, sizeof(digest));\n\nerr_free:\n\tfree(buf);\nerr_out:\n\treturn err;\n}\n\nint\nmtd_fixseama(const char *mtd, size_t offset, size_t data_size)\n{\n\tint fd;\n\tchar *first_block;\n\tssize_t res;\n\tsize_t block_offset;\n\tsize_t data_offset;\n\tstruct seama_entity_header *shdr;\n\n\tif (quiet < 2)\n\t\tfprintf(stderr, \"Trying to fix SEAMA header in %s at 0x%x...\\n\",\n\t\t\tmtd, offset);\n\n\tblock_offset = offset & ~(erasesize - 1);\n\toffset -= block_offset;\n\n\tfd = mtd_check_open(mtd);\n\tif(fd < 0) {\n\t\tfprintf(stderr, \"Could not open mtd device: %s\\n\", mtd);\n\t\texit(1);\n\t}\n\n\tif (block_offset + erasesize > mtdsize) {\n\t\tfprintf(stderr, \"Offset too large, device size 0x%x\\n\",\n\t\t\tmtdsize);\n\t\texit(1);\n\t}\n\n\tfirst_block = malloc(erasesize);\n\tif (!first_block) {\n\t\tperror(\"malloc\");\n\t\texit(1);\n\t}\n\n\tres = pread(fd, first_block, erasesize, block_offset);\n\tif (res != erasesize) {\n\t\tperror(\"pread\");\n\t\texit(1);\n\t}\n\n\tshdr = (struct seama_entity_header *)(first_block + offset);\n\tif (shdr->magic != htonl(SEAMA_MAGIC)) {\n\t\tfprintf(stderr, \"No SEAMA header found\\n\");\n\t\texit(1);\n\t} else if (!ntohl(shdr->size)) {\n\t\tfprintf(stderr, \"Seama entity with empty image\\n\");\n\t\texit(1);\n\t}\n\n\tdata_offset = offset + sizeof(struct seama_entity_header) + ntohs(shdr->metasize);\n\tif (!data_size)\n\t\tdata_size = mtdsize - data_offset;\n\tif (data_size > ntohl(shdr->size))\n\t\tdata_size = ntohl(shdr->size);\n\tif (seama_fix_md5(shdr, fd, data_offset, data_size))\n\t\tgoto out;\n\n\tif (mtd_erase_block(fd, block_offset)) {\n\t\tfprintf(stderr, \"Can't erease block at 0x%x (%s)\\n\",\n\t\t\tblock_offset, strerror(errno));\n\t\texit(1);\n\t}\n\n\tif (quiet < 2)\n\t\tfprintf(stderr, \"Rewriting block at 0x%x\\n\", block_offset);\n\n\tif (pwrite(fd, first_block, erasesize, block_offset) != erasesize) {\n\t\tfprintf(stderr, \"Error writing block (%s)\\n\", strerror(errno));\n\t\texit(1);\n\t}\n\n\tif (quiet < 2)\n\t\tfprintf(stderr, \"Done.\\n\");\n\nout:\n\tclose (fd);\n\tsync();\n\n\treturn 0;\n}\n\n"
  },
  {
    "path": "package/system/mtd/src/seama.h",
    "content": "/* vi: set sw=4 ts=4: */\n/*\n *\t(SEA)ttle i(MA)ge is the image which used in project seattle.\n *\n *\tCreated by David Hsieh <david_hsieh@alphanetworks.com>\n *\tCopyright (C) 2008-2009 Alpha Networks, Inc.\n *\n *\tThis file is free software; you can redistribute it and/or\n *\tmodify it under the terms of the GNU Lesser General Public\n *\tLicense as published by the Free Software Foundation; either'\n *\tversion 2.1 of the License, or (at your option) any later version.\n *\n *\tThe GNU C Library is distributed in the hope that it will be useful,'\n *\tbut WITHOUT ANY WARRANTY; without even the implied warranty of\n *\tMERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\n *\tLesser General Public License for more details.\n *\n *\tYou should have received a copy of the GNU Lesser General Public\n *\tLicense along with the GNU C Library; if not, write to the Free\n *\tSoftware Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA\n *\t02111-1307 USA.\n */\n\n#ifndef __SEAMA_HEADER_FILE__\n#define __SEAMA_HEADER_FILE__\n\n#include <stdint.h>\n\n#define SEAMA_MAGIC\t\t0x5EA3A417\n\n/*\n *\tSEAMA looks like the following map.\n *\tAll the data of the header should be in network byte order.\n *\n *  +-------------+-------------+------------\n *\t| SEAMA magic               |     ^\n *  +-------------+-------------+     |\n *\t| reserved    | meta size   |     |\n *  +-------------+-------------+   header\n *\t| image size (0 bytes)      |     |\n *  +-------------+-------------+     |\n *\t~ Meta data                 ~     v\n *  +-------------+-------------+------------\n *\t| SEAMA magic               |   ^     ^\n *  +-------------+-------------+   |     |\n *\t| reserved    | meta size   |   |     |\n *  +-------------+-------------+   |     |\n *\t| image size                |   |     |\n *  +-------------+-------------+ header  |\n *\t|                           |   |     |\n *\t| 16 bytes of MD5 digest    |   |     |\n *\t|                           |   |     |\n *\t|                           |   |     |\n *  +-------------+-------------+   |     |\n *\t~ Meta data                 ~   v     |\n *  +-------------+-------------+-------  |\n *\t|                           |         |\n *\t| Image of the 1st entity   |         |\n *\t~                           ~ 1st entity\n *\t|                           |         |\n *\t|                           |         v\n *  +-------------+-------------+-------------\n *\t| SEAMA magic               |   ^     ^\n *  +-------------+-------------+   |     |\n *\t| reserved    | meta size   |   |     |\n *  +-------------+-------------+   |     |\n *\t| image size                |   |     |\n *  +-------------+-------------+ header  |\n *\t|                           |   |     |\n *\t| 16 bytes of MD5 digest    |   |     |\n *\t|                           |   |     |\n *\t|                           |   |     |\n *  +-------------+-------------+   |     |\n *\t~ Meta data                 ~   v     |\n *  +-------------+-------------+-------  |\n *\t|                           |         |\n *\t| Image of the 2nd entity   |         |\n *\t~                           ~ 2nd entity\n *\t|                           |         |\n *\t|                           |         v\n *  +-------------+-------------+-------------\n */\n\n\n/*\n *\tSEAMA header\n *\n *\t|<-------- 32 bits -------->|\n *  +-------------+-------------+\n *\t| SEAMA magic               |\n *  +-------------+-------------+\n *\t| reserved    | meta size   |\n *  +-------------+-------------+\n *\t| image size                |\n *  +-------------+-------------+\n */\n\n/* seama header */\nstruct seama_entity_header {\n\tuint32_t\tmagic;\t\t\t/* should always be SEAMA_MAGIC. */\n\tuint16_t\treserved;\t\t/* reserved for  */\n\tuint16_t\tmetasize;\t\t/* size of the META data */\n\tuint32_t\tsize;\t\t\t/* size of the image */\n\tuint8_t\t\tmd5[16];\n} __attribute__ ((packed));\n\n\n#endif\n"
  },
  {
    "path": "package/system/mtd/src/tpl_ramips_recoveryflag.c",
    "content": "/*\n * TP-Link recovery flag set and unset code for ramips target\n *\n * Copyright (C) 2018 David Bauer <mail@david-bauer.net>\n *\n * This program is free software; you can redistribute it and/or\n * modify it under the terms of the GNU General Public License v2\n * as published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n * GNU General Public License for more details.\n */\n\n#include <stdio.h>\n#include <stdlib.h>\n#include <stddef.h>\n#include <unistd.h>\n#include <sys/mman.h>\n#include <errno.h>\n#include <stdint.h>\n\n#include <mtd/mtd-user.h>\n#include <sys/ioctl.h>\n\n#include \"mtd.h\"\n\n\n#define TPL_RECOVER_MAGIC\t0x89abcdef\n#define TPL_NO_RECOVER_MAGIC\t0x00000000\n\n\nstruct uboot_args {\n\tuint32_t magic;\n};\n\nint mtd_tpl_recoverflag_write(const char *mtd, const bool recovery_active)\n{\n\tstruct erase_info_user erase_info;\n\tstruct uboot_args *args;\n\tuint32_t magic;\n\tint ret = 0;\n\tint fd;\n\n\targs = malloc(erasesize);\n\tif (!args) {\n\t\tfprintf(stderr, \"Could not allocate memory!\\n\");\n\t\treturn -1;\n\t}\n\n\tfd = mtd_check_open(mtd);\n\tif (fd < 0) {\n\t\tfprintf(stderr, \"Could not open mtd device: %s\\n\", mtd);\n\t\tret = -1;\n\t\tgoto out;\n\t}\n\n\t/* read first block (containing the magic) */\n\tpread(fd, args, erasesize, 0);\n\n\t/* set magic to desired value */\n\tmagic = TPL_RECOVER_MAGIC;\n\tif (!recovery_active)\n\t\tmagic = TPL_NO_RECOVER_MAGIC;\n\n\t/* no need to write when magic is already set correctly */\n\tif (magic == args->magic)\n\t\tgoto out;\n\n\t/* erase first block (containing the magic) */\n\terase_info.start = 0;\n\terase_info.length = erasesize;\n\n\tret = ioctl(fd, MEMERASE, &erase_info);\n\tif (ret < 0) {\n\t\tfprintf(stderr, \"failed to erase block: %i\\n\", ret);\n\t\tgoto out;\n\t}\n\n\t/* write magic to flash */\n\targs->magic = magic;\n\n\tret = pwrite(fd, args, erasesize, 0);\n\tif (ret < 0)\n\t\tfprintf(stderr, \"failed to write: %i\\n\", ret);\n\n\tsync();\nout:\n\tfree(args);\n\tclose(fd);\n\n\treturn ret;\n}\n"
  },
  {
    "path": "package/system/mtd/src/trx.c",
    "content": "/*\n * trx.c\n *\n * Copyright (C) 2005 Mike Baker\n * Copyright (C) 2008 Felix Fietkau <nbd@nbd.name>\n *\n * This program is free software; you can redistribute it and/or\n * modify it under the terms of the GNU General Public License\n * as published by the Free Software Foundation; either version 2\n * of the License, or (at your option) any later version.\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n * GNU General Public License for more details.\n *\n * You should have received a copy of the GNU General Public License\n * along with this program; if not, write to the Free Software\n * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.\n */\n\n#include <stdio.h>\n#include <stdlib.h>\n#include <stddef.h>\n#include <unistd.h>\n#include <fcntl.h>\n#include <sys/mman.h>\n#include <sys/stat.h>\n#include <endian.h>\n#include <string.h>\n#include <errno.h>\n\n#include <sys/ioctl.h>\n#include <mtd/mtd-user.h>\n#include \"mtd.h\"\n#include \"crc32.h\"\n\n#define TRX_CRC32_DATA_OFFSET\t12\t/* First 12 bytes are not covered by CRC32 */\n#define TRX_CRC32_DATA_SIZE\t16\nstruct trx_header {\n\tuint32_t magic;\t\t/* \"HDR0\" */\n\tuint32_t len;\t\t/* Length of file including header */\n\tuint32_t crc32;\t\t/* 32-bit CRC from flag_version to end of file */\n\tuint32_t flag_version;\t/* 0:15 flags, 16:31 version */\n\tuint32_t offsets[3];    /* Offsets of partitions from start of header */\n};\n\n#define min(x,y) ({\t\t\\\n\ttypeof(x) _x = (x);\t\\\n\ttypeof(y) _y = (y);\t\\\n\t(void) (&_x == &_y);\t\\\n\t_x < _y ? _x : _y; })\n\n#if __BYTE_ORDER == __BIG_ENDIAN\n#define STORE32_LE(X)           ((((X) & 0x000000FF) << 24) | (((X) & 0x0000FF00) << 8) | (((X) & 0x00FF0000) >> 8) | (((X) & 0xFF000000) >> 24))\n#elif __BYTE_ORDER == __LITTLE_ENDIAN\n#define STORE32_LE(X)           (X)\n#else\n#error unknown endianness!\n#endif\n\nssize_t pread(int fd, void *buf, size_t count, off_t offset);\nssize_t pwrite(int fd, const void *buf, size_t count, off_t offset);\n\nint\ntrx_fixup(int fd, const char *name)\n{\n\tstruct mtd_info_user mtdInfo;\n\tunsigned long len;\n\tstruct trx_header *trx;\n\tvoid *ptr, *scan;\n\tint bfd;\n\n\tif (ioctl(fd, MEMGETINFO, &mtdInfo) < 0) {\n\t\tfprintf(stderr, \"Failed to get mtd info\\n\");\n\t\tgoto err;\n\t}\n\n\tlen = mtdInfo.size;\n\tif (mtdInfo.size <= 0) {\n\t\tfprintf(stderr, \"Invalid MTD device size\\n\");\n\t\tgoto err;\n\t}\n\n\tbfd = mtd_open(name, true);\n\tptr = mmap(NULL, len, PROT_READ|PROT_WRITE, MAP_SHARED, bfd, 0);\n\tif (!ptr || (ptr == (void *) -1)) {\n\t\tperror(\"mmap\");\n\t\tfprintf(stderr, \"Mapping the TRX header failed\\n\");\n\t\tgoto err1;\n\t}\n\n\ttrx = ptr;\n\tif (ntohl(trx->magic) != opt_trxmagic) {\n\t\tfprintf(stderr, \"TRX header not found\\n\");\n\t\tgoto err;\n\t}\n\n\tscan = ptr + offsetof(struct trx_header, flag_version);\n\ttrx->crc32 = crc32buf(scan, trx->len - (scan - ptr));\n\tmsync(ptr, sizeof(struct trx_header), MS_SYNC|MS_INVALIDATE);\n\tmunmap(ptr, len);\n\tclose(bfd);\n\treturn 0;\n\nerr1:\n\tclose(bfd);\nerr:\n\treturn -1;\n}\n\nint\ntrx_check(int imagefd, const char *mtd, char *buf, int *len)\n{\n\tconst struct trx_header *trx = (const struct trx_header *) buf;\n\tint fd;\n\n\tif (strcmp(mtd, \"firmware\") != 0)\n\t\treturn 1;\n\n\tif (*len < 32) {\n\t\t*len += read(imagefd, buf + *len, 32 - *len);\n\t\tif (*len < 32) {\n\t\t\tfprintf(stdout, \"Could not get image header, file too small (%d bytes)\\n\", *len);\n\t\t\treturn 0;\n\t\t}\n\t}\n\n\tif (ntohl(trx->magic) != opt_trxmagic ||\n\t    trx->len < sizeof(struct trx_header)) {\n\t\tif (quiet < 2) {\n\t\t\tfprintf(stderr, \"Bad trx header\\n\");\n\t\t\tfprintf(stderr, \"This is not the correct file format; refusing to flash.\\n\"\n\t\t\t\t\t\"Please specify the correct file or use -f to force.\\n\");\n\t\t}\n\t\treturn 0;\n\t}\n\n\t/* check if image fits to mtd device */\n\tfd = mtd_check_open(mtd);\n\tif(fd < 0) {\n\t\tfprintf(stderr, \"Could not open mtd device: %s\\n\", mtd);\n\t\texit(1);\n\t}\n\n\tif(mtdsize < trx->len) {\n\t\tfprintf(stderr, \"Image too big for partition: %s\\n\", mtd);\n\t\tclose(fd);\n\t\treturn 0;\n\t}\n\n\tclose(fd);\n\treturn 1;\n}\n\nint\nmtd_fixtrx(const char *mtd, size_t offset, size_t data_size)\n{\n\tsize_t data_offset;\n\tint fd;\n\tstruct trx_header *trx;\n\tchar *first_block;\n\tchar *buf, *to;\n\tssize_t res;\n\tsize_t block_offset;\n\n\tif (quiet < 2)\n\t\tfprintf(stderr, \"Trying to fix trx header in %s at 0x%x...\\n\", mtd, offset);\n\n\tfd = mtd_check_open(mtd);\n\tif(fd < 0) {\n\t\tfprintf(stderr, \"Could not open mtd device: %s\\n\", mtd);\n\t\texit(1);\n\t}\n\n\tdata_offset = offset + TRX_CRC32_DATA_OFFSET;\n\tif (data_size)\n\t\tdata_size += TRX_CRC32_DATA_SIZE;\n\telse\n\t\tdata_size = erasesize - TRX_CRC32_DATA_OFFSET;\n\n\tblock_offset = offset & ~(erasesize - 1);\n\toffset -= block_offset;\n\n\tif (data_offset + data_size > mtdsize) {\n\t\tfprintf(stderr, \"Offset too large, device size 0x%x\\n\", mtdsize);\n\t\texit(1);\n\t}\n\n\tfirst_block = malloc(erasesize);\n\tif (!first_block) {\n\t\tperror(\"malloc\");\n\t\texit(1);\n\t}\n\n\tres = pread(fd, first_block, erasesize, block_offset);\n\tif (res != erasesize) {\n\t\tperror(\"pread\");\n\t\texit(1);\n\t}\n\n\ttrx = (struct trx_header *)(first_block + offset);\n\tif (ntohl(trx->magic) != opt_trxmagic) {\n\t\tfprintf(stderr, \"No trx magic found\\n\");\n\t\texit(1);\n\t}\n\n\tbuf = malloc(data_size);\n\tif (!buf) {\n\t\tperror(\"malloc\");\n\t\texit(1);\n\t}\n\n\tto = buf;\n\twhile (data_size) {\n\t\tsize_t read_block_offset = data_offset & ~(erasesize - 1);\n\t\tsize_t read_chunk;\n\n\t\tread_chunk = erasesize - (data_offset & (erasesize - 1));\n\t\tread_chunk = min(read_chunk, data_size);\n\n\t\t/* Read from good blocks only to match CFE behavior */\n\t\tif (!mtd_block_is_bad(fd, read_block_offset)) {\n\t\t\tres = pread(fd, to, read_chunk, data_offset);\n\t\t\tif (res != read_chunk) {\n\t\t\t\tperror(\"pread\");\n\t\t\t\texit(1);\n\t\t\t}\n\t\t\tto += read_chunk;\n\t\t}\n\n\t\tdata_offset += read_chunk;\n\t\tdata_size -= read_chunk;\n\t}\n\tdata_size = to - buf;\n\n\tif (trx->len == STORE32_LE(data_size + TRX_CRC32_DATA_OFFSET) &&\n\t    trx->crc32 == STORE32_LE(crc32buf(buf, data_size))) {\n\t\tif (quiet < 2)\n\t\t\tfprintf(stderr, \"Header already fixed, exiting\\n\");\n\t\tclose(fd);\n\t\treturn 0;\n\t}\n\n\ttrx->len = STORE32_LE(data_size + offsetof(struct trx_header, flag_version));\n\n\ttrx->crc32 = STORE32_LE(crc32buf(buf, data_size));\n\tif (mtd_erase_block(fd, block_offset)) {\n\t\tfprintf(stderr, \"Can't erease block at 0x%x (%s)\\n\", block_offset, strerror(errno));\n\t\texit(1);\n\t}\n\n\tif (quiet < 2)\n\t\tfprintf(stderr, \"New crc32: 0x%x, rewriting block\\n\", trx->crc32);\n\n\tif (pwrite(fd, first_block, erasesize, block_offset) != erasesize) {\n\t\tfprintf(stderr, \"Error writing block (%s)\\n\", strerror(errno));\n\t\texit(1);\n\t}\n\n\tif (quiet < 2)\n\t\tfprintf(stderr, \"Done.\\n\");\n\n\tclose (fd);\n\tsync();\n\treturn 0;\n\n}\n"
  },
  {
    "path": "package/system/mtd/src/wrg.c",
    "content": "/*\n * wrg.c\n *\n * Copyright (C) 2005 Mike Baker\n * Copyright (C) 2008 Felix Fietkau <nbd@nbd.name>\n * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>\n * Copyright (C) 2016 Stijn Tintel <stijn@linux-ipv6.be>\n * Copyright (C) 2017 George Hopkins <george-hopkins@null.net>\n *\n * This program is free software; you can redistribute it and/or\n * modify it under the terms of the GNU General Public License\n * as published by the Free Software Foundation; either version 2\n * of the License, or (at your option) any later version.\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n * GNU General Public License for more details.\n *\n * You should have received a copy of the GNU General Public License\n * along with this program; if not, write to the Free Software\n * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.\n */\n\n#include <byteswap.h>\n#include <endian.h>\n#include <stdio.h>\n#include <stdlib.h>\n#include <stddef.h>\n#include <unistd.h>\n#include <fcntl.h>\n#include <sys/mman.h>\n#include <sys/stat.h>\n#include <string.h>\n#include <errno.h>\n#include <arpa/inet.h>\n\n#include <sys/ioctl.h>\n#include <mtd/mtd-user.h>\n#include \"mtd.h\"\n#include \"md5.h\"\n\n#if !defined(__BYTE_ORDER)\n#error \"Unknown byte order\"\n#endif\n\n#if __BYTE_ORDER == __BIG_ENDIAN\n#define cpu_to_le32(x)\tbswap_32(x)\n#define le32_to_cpu(x)\tbswap_32(x)\n#elif __BYTE_ORDER == __LITTLE_ENDIAN\n#define cpu_to_le32(x)\t(x)\n#define le32_to_cpu(x)\t(x)\n#else\n#error \"Unsupported endianness\"\n#endif\n\n#define WRG_MAGIC\t0x20040220\n\nstruct wrg_header {\n\tchar\t\tsignature[32];\n\tuint32_t\tmagic1;\n\tuint32_t\tmagic2;\n\tuint32_t\tsize;\n\tuint32_t\toffset;\n\tchar\t\tdevname[32];\n\tchar\t\tdigest[16];\n} __attribute__ ((packed));\n\nssize_t pread(int fd, void *buf, size_t count, off_t offset);\nssize_t pwrite(int fd, const void *buf, size_t count, off_t offset);\n\nint\nwrg_fix_md5(struct wrg_header *shdr, int fd, size_t data_offset, size_t data_size)\n{\n\tchar *buf;\n\tssize_t res;\n\tMD5_CTX ctx;\n\tunsigned char digest[16];\n\tint i;\n\tint err = 0;\n\n\tbuf = malloc(data_size);\n\tif (!buf) {\n\t\terr = -ENOMEM;\n\t\tgoto err_out;\n\t}\n\n\tres = pread(fd, buf, data_size, data_offset);\n\tif (res != data_size) {\n\t\tperror(\"pread\");\n\t\terr = -EIO;\n\t\tgoto err_free;\n\t}\n\n\tMD5_Init(&ctx);\n\tMD5_Update(&ctx, (char *)&shdr->offset, sizeof(shdr->offset));\n\tMD5_Update(&ctx, (char *)&shdr->devname, sizeof(shdr->devname));\n\tMD5_Update(&ctx, buf, data_size);\n\tMD5_Final(digest, &ctx);\n\n\tif (!memcmp(digest, shdr->digest, sizeof(digest))) {\n\t\tif (quiet < 2)\n\t\t\tfprintf(stderr, \"the header is fixed already\\n\");\n\t\treturn -1;\n\t}\n\n\tif (quiet < 2) {\n\t\tfprintf(stderr, \"new size: %u, new MD5: \", data_size);\n\t\tfor (i = 0; i < sizeof(digest); i++)\n\t\t\tfprintf(stderr, \"%02x\", digest[i]);\n\n\t\tfprintf(stderr, \"\\n\");\n\t}\n\n\t/* update the size in the image */\n\tshdr->size = cpu_to_le32(data_size);\n\n\t/* update the checksum in the image */\n\tmemcpy(shdr->digest, digest, sizeof(digest));\n\nerr_free:\n\tfree(buf);\nerr_out:\n\treturn err;\n}\n\nint\nmtd_fixwrg(const char *mtd, size_t offset, size_t data_size)\n{\n\tint fd;\n\tchar *first_block;\n\tssize_t res;\n\tsize_t block_offset;\n\tsize_t data_offset;\n\tstruct wrg_header *shdr;\n\n\tif (quiet < 2)\n\t\tfprintf(stderr, \"Trying to fix WRG header in %s at 0x%x...\\n\",\n\t\t\tmtd, offset);\n\n\tblock_offset = offset & ~(erasesize - 1);\n\toffset -= block_offset;\n\n\tfd = mtd_check_open(mtd);\n\tif(fd < 0) {\n\t\tfprintf(stderr, \"Could not open mtd device: %s\\n\", mtd);\n\t\texit(1);\n\t}\n\n\tif (block_offset + erasesize > mtdsize) {\n\t\tfprintf(stderr, \"Offset too large, device size 0x%x\\n\",\n\t\t\tmtdsize);\n\t\texit(1);\n\t}\n\n\tfirst_block = malloc(erasesize);\n\tif (!first_block) {\n\t\tperror(\"malloc\");\n\t\texit(1);\n\t}\n\n\tres = pread(fd, first_block, erasesize, block_offset);\n\tif (res != erasesize) {\n\t\tperror(\"pread\");\n\t\texit(1);\n\t}\n\n\tshdr = (struct wrg_header *)(first_block + offset);\n\tif (le32_to_cpu(shdr->magic1) != WRG_MAGIC) {\n\t\tfprintf(stderr, \"No WRG header found (%08x != %08x)\\n\",\n\t\t        le32_to_cpu(shdr->magic1), WRG_MAGIC);\n\t\texit(1);\n\t} else if (!le32_to_cpu(shdr->size)) {\n\t\tfprintf(stderr, \"WRG entity with empty image\\n\");\n\t\texit(1);\n\t}\n\n\tdata_offset = offset + sizeof(struct wrg_header);\n\tif (!data_size)\n\t\tdata_size = mtdsize - data_offset;\n\tif (data_size > le32_to_cpu(shdr->size))\n\t\tdata_size = le32_to_cpu(shdr->size);\n\tif (wrg_fix_md5(shdr, fd, data_offset, data_size))\n\t\tgoto out;\n\n\tif (mtd_erase_block(fd, block_offset)) {\n\t\tfprintf(stderr, \"Can't erease block at 0x%x (%s)\\n\",\n\t\t\tblock_offset, strerror(errno));\n\t\texit(1);\n\t}\n\n\tif (quiet < 2)\n\t\tfprintf(stderr, \"Rewriting block at 0x%x\\n\", block_offset);\n\n\tif (pwrite(fd, first_block, erasesize, block_offset) != erasesize) {\n\t\tfprintf(stderr, \"Error writing block (%s)\\n\", strerror(errno));\n\t\texit(1);\n\t}\n\n\tif (quiet < 2)\n\t\tfprintf(stderr, \"Done.\\n\");\n\nout:\n\tclose (fd);\n\tsync();\n\n\treturn 0;\n}\n"
  },
  {
    "path": "package/system/mtd/src/wrgg.c",
    "content": "/*\n * wrgg.c\n *\n * Copyright (C) 2005 Mike Baker\n * Copyright (C) 2008 Felix Fietkau <nbd@nbd.name>\n * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>\n * Copyright (C) 2016 Stijn Tintel <stijn@linux-ipv6.be>\n *\n * This program is free software; you can redistribute it and/or\n * modify it under the terms of the GNU General Public License\n * as published by the Free Software Foundation; either version 2\n * of the License, or (at your option) any later version.\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n * GNU General Public License for more details.\n *\n * You should have received a copy of the GNU General Public License\n * along with this program; if not, write to the Free Software\n * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.\n */\n\n#include <endian.h>\n#include <stdio.h>\n#include <stdlib.h>\n#include <stddef.h>\n#include <unistd.h>\n#include <fcntl.h>\n#include <sys/mman.h>\n#include <sys/stat.h>\n#include <string.h>\n#include <errno.h>\n#include <arpa/inet.h>\n\n#include <sys/ioctl.h>\n#include <mtd/mtd-user.h>\n#include \"mtd.h\"\n#include \"wrgg.h\"\n#include \"md5.h\"\n\nstatic inline uint32_t le32_to_cpu(uint8_t *buf)\n{\n\treturn buf[0] | buf[1] << 8 | buf[2] << 16 | buf[3] << 24;\n}\n\nssize_t pread(int fd, void *buf, size_t count, off_t offset);\nssize_t pwrite(int fd, const void *buf, size_t count, off_t offset);\n\nint\nwrgg_fix_md5(struct wrgg03_header *shdr, int fd, size_t data_offset, size_t data_size)\n{\n\tchar *buf;\n\tssize_t res;\n\tMD5_CTX ctx;\n\tunsigned char digest[16];\n\tint i;\n\tint err = 0;\n\n\tbuf = malloc(data_size);\n\tif (!buf) {\n\t\terr = -ENOMEM;\n\t\tgoto err_out;\n\t}\n\n\tres = pread(fd, buf, data_size, data_offset);\n\tif (res != data_size) {\n\t\tperror(\"pread\");\n\t\terr = -EIO;\n\t\tgoto err_free;\n\t}\n\n\tMD5_Init(&ctx);\n\tMD5_Update(&ctx, (char *)&shdr->offset, sizeof(shdr->offset));\n\tMD5_Update(&ctx, (char *)&shdr->dev_name, sizeof(shdr->dev_name));\n\tMD5_Update(&ctx, buf, data_size);\n\tMD5_Final(digest, &ctx);\n\n\tif (!memcmp(digest, shdr->digest, sizeof(digest))) {\n\t\tif (quiet < 2)\n\t\t\tfprintf(stderr, \"the header is fixed already\\n\");\n\t\treturn -1;\n\t}\n\n\tif (quiet < 2) {\n\t\tfprintf(stderr, \"new size:%u, new MD5: \", data_size);\n\t\tfor (i = 0; i < sizeof(digest); i++)\n\t\t\tfprintf(stderr, \"%02x\", digest[i]);\n\n\t\tfprintf(stderr, \"\\n\");\n\t}\n\n\t/* update the size in the image */\n\tshdr->size = data_size;\n\n\t/* update the checksum in the image */\n\tmemcpy(shdr->digest, digest, sizeof(digest));\n\nerr_free:\n\tfree(buf);\nerr_out:\n\treturn err;\n}\n\nint\nmtd_fixwrgg(const char *mtd, size_t offset, size_t data_size)\n{\n\tint fd;\n\tchar *first_block;\n\tssize_t res;\n\tsize_t block_offset;\n\tsize_t data_offset;\n\tstruct wrgg03_header *shdr;\n\n\tif (quiet < 2)\n\t\tfprintf(stderr, \"Trying to fix WRGG header in %s at 0x%x...\\n\",\n\t\t\tmtd, offset);\n\n\tblock_offset = offset & ~(erasesize - 1);\n\toffset -= block_offset;\n\n\tfd = mtd_check_open(mtd);\n\tif(fd < 0) {\n\t\tfprintf(stderr, \"Could not open mtd device: %s\\n\", mtd);\n\t\texit(1);\n\t}\n\n\tif (block_offset + erasesize > mtdsize) {\n\t\tfprintf(stderr, \"Offset too large, device size 0x%x\\n\",\n\t\t\tmtdsize);\n\t\texit(1);\n\t}\n\n\tfirst_block = malloc(erasesize);\n\tif (!first_block) {\n\t\tperror(\"malloc\");\n\t\texit(1);\n\t}\n\n\tres = pread(fd, first_block, erasesize, block_offset);\n\tif (res != erasesize) {\n\t\tperror(\"pread\");\n\t\texit(1);\n\t}\n\n\tshdr = (struct wrgg03_header *)(first_block + offset);\n\n\t/* The magic is always stored in little-endian byte order */\n\tif (le32_to_cpu((uint8_t *)&shdr->magic1) != WRGG03_MAGIC) {\n\t\tfprintf(stderr, \"magic1 = %x\\n\", shdr->magic1);\n\t\tfprintf(stderr, \"WRGG03_MAGIC = %x\\n\", WRGG03_MAGIC);\n\t\tfprintf(stderr, \"No WRGG header found\\n\");\n\t\texit(1);\n\t} else if (!shdr->size) {\n\t\tfprintf(stderr, \"WRGG entity with empty image\\n\");\n\t\texit(1);\n\t}\n\n\tdata_offset = offset + sizeof(struct wrgg03_header);\n\tif (!data_size)\n\t\tdata_size = mtdsize - data_offset;\n\tif (data_size > shdr->size)\n\t\tdata_size = shdr->size;\n\tif (wrgg_fix_md5(shdr, fd, data_offset, data_size))\n\t\tgoto out;\n\n\tif (mtd_erase_block(fd, block_offset)) {\n\t\tfprintf(stderr, \"Can't erease block at 0x%x (%s)\\n\",\n\t\t\tblock_offset, strerror(errno));\n\t\texit(1);\n\t}\n\n\tif (quiet < 2)\n\t\tfprintf(stderr, \"Rewriting block at 0x%x\\n\", block_offset);\n\n\tif (pwrite(fd, first_block, erasesize, block_offset) != erasesize) {\n\t\tfprintf(stderr, \"Error writing block (%s)\\n\", strerror(errno));\n\t\texit(1);\n\t}\n\n\tif (quiet < 2)\n\t\tfprintf(stderr, \"Done.\\n\");\n\nout:\n\tclose (fd);\n\tsync();\n\n\treturn 0;\n}\n"
  },
  {
    "path": "package/system/mtd/src/wrgg.h",
    "content": "#ifndef __wrgg_h\n#define __wrgg_h\n\n#define WRGG03_MAGIC\t0x20080321\n\nstruct wrgg03_header {\n\tchar\t\tsignature[32];\n\tuint32_t\tmagic1;\n\tuint32_t\tmagic2;\n\tchar\t\tversion[16];\n\tchar\t\tmodel[16];\n\tuint32_t\tflag[2];\n\tuint32_t\treserve[2];\n\tchar\t\tbuildno[16];\n\tuint32_t\tsize;\n\tuint32_t\toffset;\n\tchar\t\tdev_name[32];\n\tchar\t\tdigest[16];\n} __attribute__ ((packed));\n#endif /* __wrgg_h */\n"
  },
  {
    "path": "package/system/openwrt-keyring/Makefile",
    "content": "# Copyright (C) 2016 LEDE project\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=openwrt-keyring\nPKG_RELEASE:=2\n\nPKG_SOURCE_PROTO:=git\nPKG_SOURCE_URL=$(PROJECT_GIT)/keyring.git\nPKG_SOURCE_DATE:=2022-03-25\nPKG_SOURCE_VERSION:=62471e693b4f9f19dd88afa6827fc3a2cf121d9a\nPKG_MIRROR_HASH:=9e1c85c83b61c91f467d8df9bdf94e8a94a85ffbddfcbf3b3dc38a56e98e2516\n\nPKG_MAINTAINER:=John Crispin <john@phrozen.org>\nPKG_LICENSE:=GPL-2.0\n\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine Package/openwrt-keyring\n  SECTION:=base\n  CATEGORY:=Base system\n  PROVIDES:=lede-keyring\n  TITLE:=OpenWrt Developer Keyring\n  URL:=https://openwrt.org/docs/guide-user/security/signatures\nendef\n\ndefine Package/openwrt-keyring/description\n  The keyring of with the developer using and gpg public keys.\nendef\n\nBuild/Compile=\n\ndefine Package/openwrt-keyring/install\n\t$(INSTALL_DIR) $(1)/etc/opkg/keys/\n\t# Public usign key for unattended snapshot builds\n\t$(INSTALL_DATA) $(PKG_BUILD_DIR)/usign/b5043e70f9a75cde $(1)/etc/opkg/keys/\nendef\n\n$(eval $(call BuildPackage,openwrt-keyring))\n"
  },
  {
    "path": "package/system/opkg/Makefile",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n#\n# Copyright (C) 2006-2021 OpenWrt.org\n#\n\ninclude $(TOPDIR)/rules.mk\ninclude $(INCLUDE_DIR)/kernel.mk\n\nPKG_NAME:=opkg\nPKG_RELEASE:=$(AUTORELEASE)\nPKG_FLAGS:=essential\n\nPKG_SOURCE_PROTO:=git\nPKG_SOURCE_URL=$(PROJECT_GIT)/project/opkg-lede.git\nPKG_SOURCE_DATE:=2022-01-09\nPKG_SOURCE_VERSION:=2edcfad1bb9a32f31199d5842aa087b4d30ec6f5\nPKG_MIRROR_HASH:=b21e51ffe5bae3ca01865415630cc1f4b471f69e0d7947264a579165c7d44294\n\nPKG_LICENSE:=GPL-2.0\nPKG_LICENSE_FILES:=COPYING\n\nPKG_MAINTAINER:=Jo-Philipp Wich <jo@mein.io>\n\n# Extend depends from version.mk\nPKG_CONFIG_DEPENDS += \\\n\tCONFIG_SIGNATURE_CHECK \\\n\tCONFIG_TARGET_INIT_PATH\n\nHOST_BUILD_DEPENDS:=libubox/host\n\ninclude $(INCLUDE_DIR)/package.mk\ninclude $(INCLUDE_DIR)/host-build.mk\ninclude $(INCLUDE_DIR)/cmake.mk\n\ndefine Package/opkg\n  SECTION:=base\n  CATEGORY:=Base system\n  TITLE:=opkg package manager\n  DEPENDS:=+uclient-fetch +libpthread +libubox\n  URL:=$(PKG_SOURCE_URL)\n  MENU:=1\nendef\n\ndefine Package/opkg/description\n  Lightweight package management system\n  opkg is the opkg Package Management System, for handling\n  installation and removal of packages on a system. It can\n  recursively follow dependencies and download all packages\n  necessary to install a particular package.\n\n  opkg knows how to install both .ipk and .deb packages.\nendef\n\ndefine Package/opkg/conffiles\n/etc/opkg.conf\n/etc/opkg/keys/\n/etc/opkg/customfeeds.conf\nendef\n\nTARGET_CFLAGS += -ffunction-sections -fdata-sections\nEXTRA_CFLAGS += $(TARGET_CPPFLAGS)\n\nCMAKE_OPTIONS += \\\n\t-DBUILD_TESTS=OFF \\\n\t-DHOST_CPU=$(PKGARCH) \\\n\t-DPATH_SPEC=\"$(TARGET_INIT_PATH)\" \\\n\t-DVERSION=\"$(PKG_SOURCE_VERSION) ($(PKG_SOURCE_DATE))\"\n\nCMAKE_HOST_OPTIONS += \\\n\t-DSTATIC_UBOX=ON \\\n\t-DBUILD_TESTS=OFF \\\n\t-DHOST_CPU=$(PKGARCH) \\\n\t-DLOCK_FILE=/tmp/opkg.lock \\\n\t-DVERSION=\"$(PKG_SOURCE_VERSION) ($(PKG_SOURCE_DATE))\"\n\ndefine Package/opkg/install\n\t$(INSTALL_DIR) $(1)/usr/lib/opkg\n\t$(INSTALL_DIR) $(1)/bin\n\t$(INSTALL_DIR) $(1)/etc/opkg\n\t$(INSTALL_DIR) $(1)/etc/uci-defaults\n\t$(INSTALL_DATA) ./files/customfeeds.conf $(1)/etc/opkg/customfeeds.conf\n\t$(INSTALL_DATA) ./files/opkg$(2).conf $(1)/etc/opkg.conf\n\t$(INSTALL_BIN) ./files/20_migrate-feeds $(1)/etc/uci-defaults/\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/bin/opkg-cl $(1)/bin/opkg\n  ifneq ($(CONFIG_SIGNATURE_CHECK),)\n\techo \"option check_signature\" >> $(1)/etc/opkg.conf\n  endif\n\t$(INSTALL_DIR) $(1)/usr/sbin\n\t$(INSTALL_BIN) ./files/opkg-key $(1)/usr/sbin/\nendef\n\ndefine Host/Install\n\t$(INSTALL_BIN) $(HOST_BUILD_DIR)/src/opkg-cl $(STAGING_DIR_HOST)/bin/opkg\nendef\n\n$(eval $(call BuildPackage,opkg))\n$(eval $(call HostBuild))\n"
  },
  {
    "path": "package/system/opkg/files/20_migrate-feeds",
    "content": "#!/bin/sh\n\n[ -f /etc/opkg.conf ] && grep -q \"src\\/\" /etc/opkg.conf || exit 0\n\necho -e \"# Old feeds from previous image\\n# Uncomment to reenable\\n\" >> /etc/opkg/customfeeds.conf\nsed -n \"s/.*\\(src\\/.*\\)/# \\1/p\" /etc/opkg.conf >> /etc/opkg/customfeeds.conf\nsed -i \"/.*src\\/.*/d\" /etc/opkg.conf\n\nexit 0\n"
  },
  {
    "path": "package/system/opkg/files/customfeeds.conf",
    "content": "# add your custom package feeds here\n#\n# src/gz example_feed_name http://www.example.com/path/to/files\n"
  },
  {
    "path": "package/system/opkg/files/opkg-key",
    "content": "#!/bin/sh\n\nOPKG_KEYS=\"${OPKG_KEYS:-/etc/opkg/keys}\"\n\nusage() {\n\tcat <<EOF\nUsage: $0 <command> <arguments...>\nCommands:\n  add <file>:\t\t\tAdd keyfile <file> to opkg trusted keys\n  remove <file>:\t\tRemove keyfile matching <file> from opkg trusted keys\n  verify <sigfile> <list>:\tCheck list file <list> against signature file <sigfile>\n\nEOF\n\texit 1\n}\n\nopkg_key_verify() {\n\tlocal sigfile=\"$1\"\n\tlocal msgfile=\"$2\"\n\n\t(\n\t\tzcat \"$msgfile\" 2>/dev/null ||\n\t\tcat \"$msgfile\" 2>/dev/null\n\t) | usign -V -P \"$OPKG_KEYS\" -q -x \"$sigfile\" -m -\n}\n\nopkg_key_add() {\n\tlocal key=\"$1\"\n\t[ -n \"$key\" ] || usage\n\t[ -f \"$key\" ] || echo \"Cannot open file $1\"\n\tlocal fingerprint=\"$(usign -F -p \"$key\")\"\n\tmkdir -p \"$OPKG_KEYS\"\n\tcp \"$key\" \"$OPKG_KEYS/$fingerprint\"\n}\n\nopkg_key_remove() {\n\tlocal key=\"$1\"\n\t[ -n \"$key\" ] || usage\n\t[ -f \"$key\" ] || echo \"Cannot open file $1\"\n\tlocal fingerprint=\"$(usign -F -p \"$key\")\"\n\trm -f \"$OPKG_KEYS/$fingerprint\"\n}\n\ncase \"$1\" in\n\tadd)\n\t\tshift\n\t\topkg_key_add \"$@\"\n\t\t;;\n\tremove)\n\t\tshift\n\t\topkg_key_remove \"$@\"\n\t\t;;\n\tverify)\n\t\tshift\n\t\topkg_key_verify \"$@\"\n\t\t;;\n\t*) usage ;;\nesac\n"
  },
  {
    "path": "package/system/opkg/files/opkg-smime.conf",
    "content": "dest root /\ndest ram /tmp\nlists_dir ext /var/opkg-lists\noption overlay_root /overlay\noption check_signature 1\noption signature_ca_file /etc/ssl/certs/opkg.pem\n"
  },
  {
    "path": "package/system/opkg/files/opkg.conf",
    "content": "dest root /\ndest ram /tmp\nlists_dir ext /var/opkg-lists\noption overlay_root /overlay\n"
  },
  {
    "path": "package/system/procd/Makefile",
    "content": "#\n# Copyright (C) 2014-2016 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=procd\nPKG_RELEASE:=$(AUTORELEASE)\n\nPKG_SOURCE_PROTO:=git\nPKG_SOURCE_URL=$(PROJECT_GIT)/project/procd.git\nPKG_MIRROR_HASH:=26c4dd6cfb27ef8f5ef55f7c8d4622ff91e3490917e4fb03f54b138737113251\nPKG_SOURCE_DATE:=2022-05-03\nPKG_SOURCE_VERSION:=652e6df06f8413f19a4786a275862cfe76628093\nCMAKE_INSTALL:=1\n\nPKG_LICENSE:=GPL-2.0\nPKG_LICENSE_FILES:=\n\nPKG_MAINTAINER:=John Crispin <john@phrozen.org>\n\nPKG_ASLR_PIE_REGULAR:=1\nPKG_CONFIG_DEPENDS:= \\\n\tCONFIG_TARGET_INIT_PATH CONFIG_KERNEL_SECCOMP CONFIG_PROCD_SHOW_BOOT \\\n\tCONFIG_KERNEL_NAMESPACES CONFIG_PACKAGE_procd-ujail CONFIG_PACKAGE_procd-seccomp\n\ninclude $(INCLUDE_DIR)/package.mk\ninclude $(INCLUDE_DIR)/cmake.mk\n\nifeq ($(DUMP),)\n  STAMP_CONFIGURED:=$(strip $(STAMP_CONFIGURED))_$(shell echo $(CONFIG_TARGET_INIT_PATH) | $(MKHASH) md5)\nendif\n\nCMAKE_OPTIONS += -DEARLY_PATH=\"$(TARGET_INIT_PATH)\"\nTARGET_LDFLAGS += $(if $(CONFIG_USE_GLIBC),-lrt)\n\nTARGET_CFLAGS += -flto\nTARGET_LDFLAGS += -flto\n\ndefine Package/procd/Default\n  SECTION:=base\n  CATEGORY:=Base system\n  DEPENDS:=+ubusd +ubus +libjson-script +ubox +USE_GLIBC:librt +libubox \\\n\t  +libubus +libblobmsg-json +libjson-c +jshn\n  TITLE:=OpenWrt system process manager\n  USERID:=:dialout=20 :audio=29\nendef\n\ndefine Package/procd\n  $(call Package/procd/Default)\n  VARIANT:=default\n  CONFLICTS:=procd-selinux\nendef\n\ndefine Package/procd-selinux\n  $(call Package/procd/Default)\n  DEPENDS += +libselinux\n  TITLE += with SELinux support\n  PROVIDES:=procd\n  VARIANT:=selinux\nendef\n\ndefine Package/procd-ujail\n  SECTION:=base\n  CATEGORY:=Base system\n  DEPENDS:=@KERNEL_NAMESPACES +@KERNEL_UTS_NS +@KERNEL_IPC_NS +@KERNEL_PID_NS \\\n\t  +libubox +libubus +libuci +libblobmsg-json\n  TITLE:=OpenWrt process jail helper\nendef\n\ndefine Package/procd-seccomp\n  SECTION:=base\n  CATEGORY:=Base system\n  DEPENDS:=@SECCOMP +libubox +libblobmsg-json\n  TITLE:=OpenWrt process seccomp helper + utrace\nendef\n\ndefine Package/uxc\n  SECTION:=base\n  CATEGORY:=Base system\n  DEPENDS:=+procd-ujail +libubus +libubox +libblobmsg-json +blockd +PACKAGE_uxc:rpcd\n  TITLE:=OpenWrt container management\n  MAINTAINER:=Daniel Golle <daniel@makrotopia.org>\nendef\n\ndefine Package/procd/config\nmenu \"Configuration\"\n\tdepends on PACKAGE_procd || PACKAGE_procd-selinux\n\nconfig PROCD_SHOW_BOOT\n\tbool\n\tdefault n\n\tprompt \"Print the shutdown to the console as well as logging it to syslog\"\n\nendmenu\nendef\n\nifeq ($(BUILD_VARIANT),selinux)\n  CMAKE_OPTIONS += -DSELINUX=1\nendif\n\nifeq ($(CONFIG_PROCD_SHOW_BOOT),y)\n  CMAKE_OPTIONS += -DSHOW_BOOT_ON_CONSOLE=1\nendif\n\nifdef CONFIG_PACKAGE_procd-ujail\n  CMAKE_OPTIONS += -DJAIL_SUPPORT=1\nendif\n\nSECCOMP=$(if $(CONFIG_PACKAGE_procd-seccomp),1,0)\nCMAKE_OPTIONS += -DSECCOMP_SUPPORT=$(SECCOMP) -DUTRACE_SUPPORT=$(SECCOMP)\n\ndefine Package/procd/install\n\t$(INSTALL_DIR) $(1)/sbin $(1)/etc $(1)/lib/functions\n\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/sbin/{init,procd,askfirst,udevtrigger,upgraded} $(1)/sbin/\n\t$(INSTALL_DATA) $(PKG_INSTALL_DIR)/usr/lib/libsetlbf.so $(1)/lib\n\t$(INSTALL_BIN) ./files/reload_config $(1)/sbin/\n\t$(INSTALL_CONF) ./files/hotplug*.json $(1)/etc/\n\t$(INSTALL_DATA) ./files/procd.sh $(1)/lib/functions/\n\t$(INSTALL_BIN) ./files/service $(1)/sbin/service\nendef\n\nPackage/procd-selinux/install = $(Package/procd/install)\n\ndefine Package/procd-ujail/install\n\t$(INSTALL_DIR) $(1)/sbin\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/sbin/ujail $(1)/sbin/\nendef\n\ndefine Package/procd-seccomp/install\n\t$(INSTALL_DIR) $(1)/sbin $(1)/lib\n\t$(INSTALL_DATA) $(PKG_INSTALL_DIR)/usr/lib/libpreload-seccomp.so $(1)/lib\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/sbin/utrace $(1)/sbin/\n\t$(LN) utrace $(1)/sbin/seccomp-trace\n\t$(INSTALL_DATA) $(PKG_INSTALL_DIR)/usr/lib/libpreload-trace.so $(1)/lib\nendef\n\ndefine Package/uxc/conffiles\n/etc/uxc\nendef\n\ndefine Package/uxc/install\n\t$(INSTALL_DIR) $(1)/sbin\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/sbin/uxc $(1)/sbin/\n\t$(INSTALL_DIR) $(1)/etc/init.d\n\t$(INSTALL_BIN) ./files/uxc.init $(1)/etc/init.d/uxc\nendef\n\n$(eval $(call BuildPackage,procd))\n$(eval $(call BuildPackage,procd-selinux))\n$(eval $(call BuildPackage,procd-ujail))\n$(eval $(call BuildPackage,procd-seccomp))\n$(eval $(call BuildPackage,uxc))\n"
  },
  {
    "path": "package/system/procd/files/hotplug-preinit.json",
    "content": "[\n\t[ \"case\", \"ACTION\", {\n\t\t\"add\": [\n\t\t\t[ \"if\",\n\t\t\t\t[ \"has\", \"FIRMWARE\" ],\n\t\t\t\t[\n\t\t\t\t\t[ \"exec\", \"/sbin/hotplug-call\", \"%SUBSYSTEM%\" ],\n\t\t\t\t\t[ \"load-firmware\", \"/lib/firmware\" ],\n\t\t\t\t\t[ \"return\" ]\n\t\t\t\t]\n\t\t\t]\n\t\t]\n\t} ],\n\t[ \"if\",\n\t\t[ \"eq\", \"SUBSYSTEM\", \"button\" ],\n\t\t[ \"exec\", \"/etc/rc.button/failsafe\" ]\n\t]\n]\n"
  },
  {
    "path": "package/system/procd/files/hotplug.json",
    "content": "[\n\t[ \"case\", \"ACTION\", {\n\t\t\"add\": [\n\t\t\t[ \"if\",\n\t\t\t\t[ \"and\",\n\t\t\t\t\t[ \"has\", \"MAJOR\" ],\n\t\t\t\t\t[ \"has\", \"MINOR\" ]\n\t\t\t\t],\n\t\t\t\t[\n\t\t\t\t\t[ \"if\",\n\t\t\t\t\t\t[ \"eq\", \"DEVNAME\", \"null\" ],\n\t\t\t\t\t\t[\n\t\t\t\t\t\t\t[ \"makedev\", \"/dev/%DEVNAME%\", \"0666\" ],\n\t\t\t\t\t\t\t[ \"exec\", \"/bin/ln\", \"-s\", \"/proc/self/fd/0\", \"/dev/stdin\" ],\n\t\t\t\t\t\t\t[ \"exec\", \"/bin/ln\", \"-s\", \"/proc/self/fd/1\", \"/dev/stdout\" ],\n\t\t\t\t\t\t\t[ \"exec\", \"/bin/ln\", \"-s\", \"/proc/self/fd/2\", \"/dev/stderr\" ],\n\t\t\t\t\t\t\t[ \"return\" ]\n\t\t\t\t\t\t]\n\t\t\t\t\t],\n\t\t\t\t\t[ \"if\",\n\t\t\t\t\t\t[ \"eq\", \"DEVNAME\",\n\t\t\t\t\t\t\t[ \"full\", \"ptmx\", \"zero\", \"tty\", \"net\", \"random\", \"urandom\" ]\n\t\t\t\t\t\t],\n\t\t\t\t\t\t[\n\t\t\t\t\t\t\t[ \"makedev\", \"/dev/%DEVNAME%\", \"0666\" ],\n\t\t\t\t\t\t\t[ \"return\" ]\n\t\t\t\t\t\t]\n\t\t\t\t\t],\n\t\t\t\t\t[ \"if\",\n\t\t\t\t\t\t[ \"regex\", \"DEVNAME\", \"^snd\" ],\n\t\t\t\t\t\t[ \"makedev\", \"/dev/%DEVNAME%\", \"0660\", \"audio\" ]\n\t\t\t\t\t],\n\t\t\t\t\t[ \"if\",\n\t\t\t\t\t\t[ \"regex\", \"DEVNAME\", \"^tty\" ],\n\t\t\t\t\t\t[ \"makedev\", \"/dev/%DEVNAME%\", \"0660\", \"dialout\" ]\n\t\t\t\t\t],\n\t\t\t\t\t[ \"if\",\n\t\t\t\t\t\t[ \"has\", \"DEVNAME\" ],\n\t\t\t\t\t\t[ \"makedev\", \"/dev/%DEVNAME%\", \"0600\" ]\n\t\t\t\t\t]\n\t\t\t\t]\n\t\t\t],\n\t\t\t[ \"if\",\n\t\t\t\t[ \"has\", \"FIRMWARE\" ],\n\t\t\t\t[\n\t\t\t\t\t[ \"exec\", \"/sbin/hotplug-call\", \"%SUBSYSTEM%\" ],\n\t\t\t\t\t[ \"load-firmware\", \"/lib/firmware\" ],\n\t\t\t\t\t[ \"return\" ]\n\t\t\t\t]\n\t\t\t],\n\t\t\t[ \"if\",\n\t\t\t\t[ \"regex\", \"DEVNAME\", \"^ttyGS\" ],\n\t\t\t\t[ \"start-console\", \"%DEVNAME%\" ]\n\t\t\t]\n\t\t],\n\t\t\"remove\" : [\n\t\t\t[ \"if\",\n\t\t\t\t[ \"and\",\n\t\t\t\t\t[ \"has\", \"DEVNAME\" ],\n\t\t\t\t\t[ \"has\", \"MAJOR\" ],\n\t\t\t\t\t[ \"has\", \"MINOR\" ]\n\t\t\t\t],\n\t\t\t\t[ \"rm\", \"/dev/%DEVNAME%\" ]\n\t\t\t]\n\t\t]\n\t} ],\n\t[ \"if\",\n\t\t[ \"and\",\n\t\t\t[ \"has\", \"BUTTON\" ],\n\t\t\t[ \"eq\", \"SUBSYSTEM\", \"button\" ]\n\t\t],\n\t\t[ \"button\", \"/etc/rc.button/%BUTTON%\" ]\n\t],\n\t[ \"if\",\n\t\t[ \"and\",\n\t\t\t[ \"eq\", \"SUBSYSTEM\", \"usb-serial\" ],\n\t\t\t[ \"regex\", \"DEVNAME\",\n\t\t\t\t[ \"^ttyUSB\", \"^ttyACM\" ]\n\t\t\t]\n\t\t],\n\t\t[ \"exec\", \"/sbin/hotplug-call\", \"tty\" ],\n\t\t[ \"if\",\n\t\t\t[ \"isdir\", \"/etc/hotplug.d/%SUBSYSTEM%\" ],\n\t\t\t[ \"exec\", \"/sbin/hotplug-call\", \"%SUBSYSTEM%\" ]\n\t\t]\n\t]\n]\n"
  },
  {
    "path": "package/system/procd/files/procd.sh",
    "content": "# procd API:\n#\n# procd_open_service(name, [script]):\n#   Initialize a new procd command message containing a service with one or more instances\n#\n# procd_close_service()\n#   Send the command message for the service\n#\n# procd_open_instance([name]):\n#   Add an instance to the service described by the previous procd_open_service call\n#\n# procd_set_param(type, [value...])\n#   Available types:\n#     command: command line (array).\n#     respawn info: array with 3 values $fail_threshold $restart_timeout $max_fail\n#     env: environment variable (passed to the process)\n#     data: arbitrary name/value pairs for detecting config changes (table)\n#     file: configuration files (array)\n#     netdev: bound network device (detects ifindex changes)\n#     limits: resource limits (passed to the process)\n#     user: $username to run service as\n#     group: $groupname to run service as\n#     pidfile: file name to write pid into\n#     stdout: boolean whether to redirect commands stdout to syslog (default: 0)\n#     stderr: boolean whether to redirect commands stderr to syslog (default: 0)\n#     facility: syslog facility used when logging to syslog (default: daemon)\n#\n#   No space separation is done for arrays/tables - use one function argument per command line argument\n#\n# procd_close_instance():\n#   Complete the instance being prepared\n#\n# procd_running(service, [instance]):\n#   Checks if service/instance is currently running\n#\n# procd_kill(service, [instance]):\n#   Kill a service instance (or all instances)\n#\n# procd_send_signal(service, [instance], [signal])\n#   Send a signal to a service instance (or all instances)\n#\n\n. \"$IPKG_INSTROOT/usr/share/libubox/jshn.sh\"\n\nPROCD_RELOAD_DELAY=1000\n_PROCD_SERVICE=\n\nprocd_lock() {\n\tlocal basescript=$(readlink \"$initscript\")\n\tlocal service_name=\"$(basename ${basescript:-$initscript})\"\n\n\tflock -n 1000 &> /dev/null\n\tif [ \"$?\" != \"0\" ]; then\n\t\texec 1000>\"$IPKG_INSTROOT/var/lock/procd_${service_name}.lock\"\n\t\tflock 1000\n\t\tif [ \"$?\" != \"0\" ]; then\n\t\t\tlogger \"warning: procd flock for $service_name failed\"\n\t\tfi\n\tfi\n}\n\n_procd_call() {\n\tlocal old_cb\n\n\tjson_set_namespace procd old_cb\n\t\"$@\"\n\tjson_set_namespace $old_cb\n}\n\n_procd_wrapper() {\n\tprocd_lock\n\twhile [ -n \"$1\" ]; do\n\t\teval \"$1() { _procd_call _$1 \\\"\\$@\\\"; }\"\n\t\tshift\n\tdone\n}\n\n_procd_ubus_call() {\n\tlocal cmd=\"$1\"\n\n\t[ -n \"$PROCD_DEBUG\" ] && json_dump >&2\n\tubus call service \"$cmd\" \"$(json_dump)\"\n\tjson_cleanup\n}\n\n_procd_open_service() {\n\tlocal name=\"$1\"\n\tlocal script=\"$2\"\n\n\t_PROCD_SERVICE=\"$name\"\n\t_PROCD_INSTANCE_SEQ=0\n\n\tjson_init\n\tjson_add_string name \"$name\"\n\t[ -n \"$script\" ] && json_add_string script \"$script\"\n\tjson_add_object instances\n}\n\n_procd_close_service() {\n\tjson_close_object\n\t_procd_open_trigger\n\tservice_triggers\n\t_procd_close_trigger\n\t_procd_open_data\n\tservice_data\n\t_procd_close_data\n\t_procd_ubus_call ${1:-set}\n}\n\n_procd_add_array_data() {\n\twhile [ \"$#\" -gt 0 ]; do\n\t\tjson_add_string \"\" \"$1\"\n\t\tshift\n\tdone\n}\n\n_procd_add_array() {\n\tjson_add_array \"$1\"\n\tshift\n\t_procd_add_array_data \"$@\"\n\tjson_close_array\n}\n\n_procd_add_table_data() {\n\twhile [ -n \"$1\" ]; do\n\t\tlocal var=\"${1%%=*}\"\n\t\tlocal val=\"${1#*=}\"\n\t\t[ \"$1\" = \"$val\" ] && val=\n\t\tjson_add_string \"$var\" \"$val\"\n\t\tshift\n\tdone\n}\n\n_procd_add_table() {\n\tjson_add_object \"$1\"\n\tshift\n\t_procd_add_table_data \"$@\"\n\tjson_close_object\n}\n\n_procd_open_instance() {\n\tlocal name=\"$1\"; shift\n\n\t_PROCD_INSTANCE_SEQ=\"$(($_PROCD_INSTANCE_SEQ + 1))\"\n\tname=\"${name:-instance$_PROCD_INSTANCE_SEQ}\"\n\tjson_add_object \"$name\"\n\t[ -n \"$TRACE_SYSCALLS\" ] && json_add_boolean trace \"1\"\n}\n\n_procd_open_trigger() {\n\tlet '_procd_trigger_open = _procd_trigger_open + 1'\n\t[ \"$_procd_trigger_open\" -gt 1 ] && return\n\tjson_add_array \"triggers\"\n}\n\n_procd_close_trigger() {\n\tlet '_procd_trigger_open = _procd_trigger_open - 1'\n\t[ \"$_procd_trigger_open\" -lt 1 ] || return\n\tjson_close_array\n}\n\n_procd_open_data() {\n\tlet '_procd_data_open = _procd_data_open + 1'\n\t[ \"$_procd_data_open\" -gt 1 ] && return\n\tjson_add_object \"data\"\n}\n\n_procd_close_data() {\n\tlet '_procd_data_open = _procd_data_open - 1'\n\t[ \"$_procd_data_open\" -lt 1 ] || return\n\tjson_close_object\n}\n\n_procd_open_validate() {\n\tjson_select ..\n\tjson_add_array \"validate\"\n}\n\n_procd_close_validate() {\n\tjson_close_array\n\tjson_select triggers\n}\n\n_procd_add_jail() {\n\tjson_add_object \"jail\"\n\tjson_add_string name \"$1\"\n\n\tshift\n\t\n\tfor a in $@; do\n\t\tcase $a in\n\t\tlog)\tjson_add_boolean \"log\" \"1\";;\n\t\tubus)\tjson_add_boolean \"ubus\" \"1\";;\n\t\tprocfs)\tjson_add_boolean \"procfs\" \"1\";;\n\t\tsysfs)\tjson_add_boolean \"sysfs\" \"1\";;\n\t\tronly)\tjson_add_boolean \"ronly\" \"1\";;\n\t\trequirejail)\tjson_add_boolean \"requirejail\" \"1\";;\n\t\tnetns)\tjson_add_boolean \"netns\" \"1\";;\n\t\tuserns)\tjson_add_boolean \"userns\" \"1\";;\n\t\tcgroupsns)\tjson_add_boolean \"cgroupsns\" \"1\";;\n\t\tesac\n\tdone\n\tjson_add_object \"mount\"\n\tjson_close_object\n\tjson_close_object\n}\n\n_procd_add_jail_mount() {\n\tlocal _json_no_warning=1\n\n\tjson_select \"jail\"\n\t[ $? = 0 ] || return\n\tjson_select \"mount\"\n\t[ $? = 0 ] || {\n\t\tjson_select ..\n\t\treturn\n\t}\n\tfor a in $@; do\n\t\tjson_add_string \"$a\" \"0\"\n\tdone\n\tjson_select ..\n\tjson_select ..\n}\n\n_procd_add_jail_mount_rw() {\n\tlocal _json_no_warning=1\n\n\tjson_select \"jail\"\n\t[ $? = 0 ] || return\n\tjson_select \"mount\"\n\t[ $? = 0 ] || {\n\t\tjson_select ..\n\t\treturn\n\t}\n\tfor a in $@; do\n\t\tjson_add_string \"$a\" \"1\"\n\tdone\n\tjson_select ..\n\tjson_select ..\n}\n\n_procd_set_param() {\n\tlocal type=\"$1\"; shift\n\n\tcase \"$type\" in\n\t\tenv|data|limits)\n\t\t\t_procd_add_table \"$type\" \"$@\"\n\t\t;;\n\t\tcommand|netdev|file|respawn|watch|watchdog)\n\t\t\t_procd_add_array \"$type\" \"$@\"\n\t\t;;\n\t\terror)\n\t\t\tjson_add_array \"$type\"\n\t\t\tjson_add_string \"\" \"$@\"\n\t\t\tjson_close_array\n\t\t;;\n\t\tnice|term_timeout)\n\t\t\tjson_add_int \"$type\" \"$1\"\n\t\t;;\n\t\treload_signal)\n\t\t\tjson_add_int \"$type\" $(kill -l \"$1\")\n\t\t;;\n\t\tpidfile|user|group|seccomp|capabilities|facility|\\\n\t\textroot|overlaydir|tmpoverlaysize)\n\t\t\tjson_add_string \"$type\" \"$1\"\n\t\t;;\n\t\tstdout|stderr|no_new_privs)\n\t\t\tjson_add_boolean \"$type\" \"$1\"\n\t\t;;\n\tesac\n}\n\n_procd_add_timeout() {\n\t[ \"$PROCD_RELOAD_DELAY\" -gt 0 ] && json_add_int \"\" \"$PROCD_RELOAD_DELAY\"\n\treturn 0\n}\n\n_procd_add_interface_trigger() {\n\tjson_add_array\n\t_procd_add_array_data \"$1\"\n\tshift\n\n\tjson_add_array\n\t_procd_add_array_data \"if\"\n\n\tjson_add_array\n\t_procd_add_array_data \"eq\" \"interface\" \"$1\"\n\tshift\n\tjson_close_array\n\n\tjson_add_array\n\t_procd_add_array_data \"run_script\" \"$@\"\n\tjson_close_array\n\n\tjson_close_array\n\t_procd_add_timeout\n\tjson_close_array\n}\n\n_procd_add_reload_interface_trigger() {\n\tlocal script=$(readlink \"$initscript\")\n\tlocal name=$(basename ${script:-$initscript})\n\n\t_procd_open_trigger\n\t_procd_add_interface_trigger \"interface.*\" $1 /etc/init.d/$name reload\n\t_procd_close_trigger\n}\n\n_procd_add_config_trigger() {\n\tjson_add_array\n\t_procd_add_array_data \"$1\"\n\tshift\n\n\tjson_add_array\n\t_procd_add_array_data \"if\"\n\n\tjson_add_array\n\t_procd_add_array_data \"eq\" \"package\" \"$1\"\n\tshift\n\tjson_close_array\n\n\tjson_add_array\n\t_procd_add_array_data \"run_script\" \"$@\"\n\tjson_close_array\n\n\tjson_close_array\n\t_procd_add_timeout\n\tjson_close_array\n}\n\n_procd_add_mount_trigger() {\n\tjson_add_array\n\t_procd_add_array_data \"$1\"\n\tlocal action=\"$2\"\n\tlocal multi=0\n\tshift ; shift\n\n\tjson_add_array\n\t_procd_add_array_data \"if\"\n\n\tif [ \"$2\" ]; then\n\t\tjson_add_array\n\t\t_procd_add_array_data \"or\"\n\t\tmulti=1\n\tfi\n\n\twhile [ \"$1\" ]; do\n\t\tjson_add_array\n\t\t_procd_add_array_data \"eq\" \"target\" \"$1\"\n\t\tshift\n\t\tjson_close_array\n\tdone\n\n\t[ $multi = 1 ] && json_close_array\n\n\tjson_add_array\n\t_procd_add_array_data \"run_script\" /etc/init.d/$name $action\n\tjson_close_array\n\n\tjson_close_array\n\t_procd_add_timeout\n\tjson_close_array\n}\n\n_procd_add_action_mount_trigger() {\n\tlocal action=\"$1\"\n\tshift\n\tlocal mountpoints=\"$(procd_get_mountpoints \"$@\")\"\n\t[ \"${mountpoints//[[:space:]]}\" ] || return 0\n\tlocal script=$(readlink \"$initscript\")\n\tlocal name=$(basename ${script:-$initscript})\n\n\t_procd_open_trigger\n\t_procd_add_mount_trigger mount.add $action \"$mountpoints\"\n\t_procd_close_trigger\n}\n\nprocd_get_mountpoints() {\n\t(\n\t\t__procd_check_mount() {\n\t\t\tlocal cfg=\"$1\"\n\t\t\tlocal path=\"${2%%/}/\"\n\t\t\tlocal target\n\t\t\tconfig_get target \"$cfg\" target\n\t\t\ttarget=\"${target%%/}/\"\n\t\t\t[ \"$path\" != \"${path##$target}\" ] && echo \"${target%%/}\"\n\t\t}\n\t\tlocal mpath\n\t\tconfig_load fstab\n\t\tfor mpath in \"$@\"; do\n\t\t\tconfig_foreach __procd_check_mount mount \"$mpath\"\n\t\tdone\n\t) | sort -u\n}\n\n_procd_add_restart_mount_trigger() {\n\t_procd_add_action_mount_trigger restart \"$@\"\n}\n\n_procd_add_reload_mount_trigger() {\n\t_procd_add_action_mount_trigger reload \"$@\"\n}\n\n_procd_add_raw_trigger() {\n\tjson_add_array\n\t_procd_add_array_data \"$1\"\n\tshift\n\tlocal timeout=$1\n\tshift\n\n\tjson_add_array\n\tjson_add_array\n\t_procd_add_array_data \"run_script\" \"$@\"\n\tjson_close_array\n\tjson_close_array\n\n\tjson_add_int \"\" \"$timeout\"\n\n\tjson_close_array\n}\n\n_procd_add_reload_trigger() {\n\tlocal script=$(readlink \"$initscript\")\n\tlocal name=$(basename ${script:-$initscript})\n\tlocal file\n\n\t_procd_open_trigger\n\tfor file in \"$@\"; do\n\t\t_procd_add_config_trigger \"config.change\" \"$file\" /etc/init.d/$name reload\n\tdone\n\t_procd_close_trigger\n}\n\n_procd_add_validation() {\n\t_procd_open_validate\n\t$@\n\t_procd_close_validate\n}\n\n_procd_append_param() {\n\tlocal type=\"$1\"; shift\n\tlocal _json_no_warning=1\n\n\tjson_select \"$type\"\n\t[ $? = 0 ] || {\n\t\t_procd_set_param \"$type\" \"$@\"\n\t\treturn\n\t}\n\tcase \"$type\" in\n\t\tenv|data|limits)\n\t\t\t_procd_add_table_data \"$@\"\n\t\t;;\n\t\tcommand|netdev|file|respawn|watch|watchdog)\n\t\t\t_procd_add_array_data \"$@\"\n\t\t;;\n\t\terror)\n\t\t\tjson_add_string \"\" \"$@\"\n\t\t;;\n\tesac\n\tjson_select ..\n}\n\n_procd_close_instance() {\n\tlocal respawn_vals\n\t_json_no_warning=1\n\tif json_select respawn ; then\n\t\tjson_get_values respawn_vals\n\t\tif [ -z \"$respawn_vals\" ]; then\n\t\t\tlocal respawn_threshold=$(uci_get system.@service[0].respawn_threshold)\n\t\t\tlocal respawn_timeout=$(uci_get system.@service[0].respawn_timeout)\n\t\t\tlocal respawn_retry=$(uci_get system.@service[0].respawn_retry)\n\t\t\t_procd_add_array_data ${respawn_threshold:-3600} ${respawn_timeout:-5} ${respawn_retry:-5}\n\t\tfi\n\t\tjson_select ..\n\tfi\n\n\tjson_close_object\n}\n\n_procd_add_instance() {\n\t_procd_open_instance\n\t_procd_set_param command \"$@\"\n\t_procd_close_instance\n}\n\nprocd_running() {\n\tlocal service=\"$1\"\n\tlocal instance=\"${2:-*}\"\n\t[ \"$instance\" = \"*\" ] || instance=\"'$instance'\"\n\n\tjson_init\n\tjson_add_string name \"$service\"\n\tlocal running=$(_procd_ubus_call list | jsonfilter -l 1 -e \"@['$service'].instances[$instance].running\")\n\n\t[ \"$running\" = \"true\" ]\n}\n\n_procd_kill() {\n\tlocal service=\"$1\"\n\tlocal instance=\"$2\"\n\n\tjson_init\n\t[ -n \"$service\" ] && json_add_string name \"$service\"\n\t[ -n \"$instance\" ] && json_add_string instance \"$instance\"\n\t_procd_ubus_call delete\n}\n\n_procd_send_signal() {\n\tlocal service=\"$1\"\n\tlocal instance=\"$2\"\n\tlocal signal=\"$3\"\n\n\tcase \"$signal\" in\n\t\t[A-Z]*)\tsignal=\"$(kill -l \"$signal\" 2>/dev/null)\" || return 1;;\n\tesac\n\n\tjson_init\n\tjson_add_string name \"$service\"\n\t[ -n \"$instance\" -a \"$instance\" != \"*\" ] && json_add_string instance \"$instance\"\n\t[ -n \"$signal\" ] && json_add_int signal \"$signal\"\n\t_procd_ubus_call signal\n}\n\n_procd_status() {\n\tlocal service=\"$1\"\n\tlocal instance=\"$2\"\n\tlocal data\n\n\tjson_init\n\t[ -n \"$service\" ] && json_add_string name \"$service\"\n\n\tdata=$(_procd_ubus_call list | jsonfilter -e '@[\"'\"$service\"'\"]')\n\t[ -z \"$data\" ] && { echo \"inactive\"; return 3; }\n\n\tdata=$(echo \"$data\" | jsonfilter -e '$.instances')\n\tif [ -z \"$data\" ]; then\n\t\t[ -z \"$instance\" ] && { echo \"active with no instances\"; return 0; }\n\t\tdata=\"[]\"\n\tfi\n\n\t[ -n \"$instance\" ] && instance=\"\\\"$instance\\\"\" || instance='*'\n\tif [ -z \"$(echo \"$data\" | jsonfilter -e '$['\"$instance\"']')\" ]; then\n\t\techo \"unknown instance $instance\"; return 4\n\telse\n\t\techo \"running\"; return 0\n\tfi\n}\n\nprocd_open_data() {\n\tlocal name=\"$1\"\n\tjson_set_namespace procd __procd_old_cb\n\tjson_add_object data\n}\n\nprocd_close_data() {\n\tjson_close_object\n\tjson_set_namespace $__procd_old_cb\n}\n\n_procd_set_config_changed() {\n\tlocal package=\"$1\"\n\n\tjson_init\n\tjson_add_string type config.change\n\tjson_add_object data\n\tjson_add_string package \"$package\"\n\tjson_close_object\n\n\tubus call service event \"$(json_dump)\"\n}\n\nprocd_add_mdns_service() {\n\tlocal service proto port\n\tservice=$1; shift\n\tproto=$1; shift\n\tport=$1; shift\n\tjson_add_object \"${service}_$port\"\n\tjson_add_string \"service\" \"_$service._$proto.local\"\n\tjson_add_int port \"$port\"\n\t[ -n \"$1\" ] && {\n\t\tjson_add_array txt\n\t\tfor txt in \"$@\"; do json_add_string \"\" \"$txt\"; done\n\t\tjson_select ..\n\t}\n\tjson_select ..\n}\n\nprocd_add_mdns() {\n\tprocd_open_data\n\tjson_add_object \"mdns\"\n\tprocd_add_mdns_service \"$@\"\n\tjson_close_object\n\tprocd_close_data\n}\n\nuci_validate_section()\n{\n\tlocal _package=\"$1\"\n\tlocal _type=\"$2\"\n\tlocal _name=\"$3\"\n\tlocal _result\n\tlocal _error\n\tshift; shift; shift\n\t_result=$(/sbin/validate_data \"$_package\" \"$_type\" \"$_name\" \"$@\" 2> /dev/null)\n\t_error=$?\n\teval \"$_result\"\n\t[ \"$_error\" = \"0\" ] || $(/sbin/validate_data \"$_package\" \"$_type\" \"$_name\" \"$@\" 1> /dev/null)\n\treturn $_error\n}\n\nuci_load_validate() {\n\tlocal _package=\"$1\"\n\tlocal _type=\"$2\"\n\tlocal _name=\"$3\"\n\tlocal _function=\"$4\"\n\tlocal _option\n\tlocal _result\n\tshift; shift; shift; shift\n\tfor _option in \"$@\"; do\n\t\teval \"local ${_option%%:*}\"\n\tdone\n\tuci_validate_section \"$_package\" \"$_type\" \"$_name\" \"$@\"\n\t_result=$?\n\t[ -n \"$_function\" ] || return $_result\n\teval \"$_function \\\"\\$_name\\\" \\\"\\$_result\\\"\"\n}\n\n_procd_wrapper \\\n\tprocd_open_service \\\n\tprocd_close_service \\\n\tprocd_add_instance \\\n\tprocd_add_raw_trigger \\\n\tprocd_add_config_trigger \\\n\tprocd_add_interface_trigger \\\n\tprocd_add_mount_trigger \\\n\tprocd_add_reload_trigger \\\n\tprocd_add_reload_interface_trigger \\\n\tprocd_add_action_mount_trigger \\\n\tprocd_add_reload_mount_trigger \\\n\tprocd_add_restart_mount_trigger \\\n\tprocd_open_trigger \\\n\tprocd_close_trigger \\\n\tprocd_open_instance \\\n\tprocd_close_instance \\\n\tprocd_open_validate \\\n\tprocd_close_validate \\\n\tprocd_add_jail \\\n\tprocd_add_jail_mount \\\n\tprocd_add_jail_mount_rw \\\n\tprocd_set_param \\\n\tprocd_append_param \\\n\tprocd_add_validation \\\n\tprocd_set_config_changed \\\n\tprocd_kill \\\n\tprocd_send_signal\n"
  },
  {
    "path": "package/system/procd/files/reload_config",
    "content": "#!/bin/sh\nrm -rf /var/run/config.check\nmkdir -p /var/run/config.check\nfor config in /etc/config/*; do\n\tfile=${config##*/}\n\tuci show \"${file##*/}\" > /var/run/config.check/$file\ndone\nMD5FILE=/var/run/config.md5\n[ -f $MD5FILE ] && {\n\tfor c in $(md5sum -c $MD5FILE 2>/dev/null| grep FAILED | cut -d: -f1); do\n\t\tubus call service event \"{ \\\"type\\\": \\\"config.change\\\", \\\"data\\\": { \\\"package\\\": \\\"$(basename $c)\\\" }}\"\n\tdone\n}\nmd5sum /var/run/config.check/* > $MD5FILE\nrm -rf /var/run/config.check\n"
  },
  {
    "path": "package/system/procd/files/service",
    "content": "#!/bin/sh\n\nmain() {\n\tlocal service=\"$1\"\n\tlocal cmd=\"$2\"\n\n\tlocal boot status\n\n\tif [ -f \"/etc/init.d/${service}\" ]; then\n\t\t/etc/init.d/\"${service}\" \"${cmd}\"\n\t\texit \"$?\"\n\tfi\n\n\tif [ -n \"$service\" ]; then\n\t\techo \"Service \\\"$1\\\" not found:\"\n\t\texit 1\n\tfi\n\n\techo \"Usage: $(basename \"$0\") <service> [command]\"\n\tfor service in /etc/init.d/* ; do\n\t\tboot=\"$($service enabled && echo \"enabled\" || echo \"disabled\" )\"\n\t\tstatus=\"$( [ \"$(ubus call service list \"{ 'verbose': true, 'name': '$(basename \"$service\")' }\" \\\n\t\t\t| jsonfilter -q -e \"@['$(basename \"$service\")'].instances[*].running\" | uniq)\" = \"true\" ] \\\n\t\t\t&& echo \"running\" || echo \"stopped\" )\"\n\n\t\tprintf \"%-30s\\\\t%10s\\\\t%10s\\\\n\"  \"$service\" \"$boot\" \"$status\"\n\tdone\n}\n\nmain \"$@\"\n"
  },
  {
    "path": "package/system/procd/files/uxc.init",
    "content": "#!/bin/sh /etc/rc.common\n\nSTART=99\nUSE_PROCD=1\nNAME=uxc\nPROG=/sbin/uxc\n\nstart_service() {\n\tprocd_open_instance \"uxc\"\n\tprocd_set_param command \"$PROG\" boot\n\tprocd_close_instance\n}\n\nservice_triggers() {\n\tprocd_add_raw_trigger \"mount.add\" 3000 /etc/init.d/uxc start\n}\n"
  },
  {
    "path": "package/system/refpolicy/Makefile",
    "content": "#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=refpolicy\nPKG_VERSION:=2.20200229\nPKG_RELEASE:=3\n\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.bz2\nPKG_SOURCE_URL:=https://github.com/SELinuxProject/refpolicy/releases/download/RELEASE_2_20200229\nPKG_HASH:=dec854512ed00cd057408f330c2cea4de7a4405f7a147458f59c994bf578e4b0\nPKG_INSTALL:=1\nPKG_BUILD_DEPENDS:=checkpolicy/host policycoreutils/host\n\nPKG_MAINTAINER:=Thomas Petazzoni <thomas.petazzoni@bootlin.com>\nPKG_CPE_ID:=cpe:/a:tresys:refpolicy\nPKG_LICENSE:=GPL-2.0-or-later\nPKG_LICENSE_FILES:=COPYING\n\nTAR_OPTIONS:=--transform='s%^refpolicy%$(PKG_NAME)-$(PKG_VERSION)%' -xf -\n\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine Package/refpolicy\n  SECTION:=system\n  CATEGORY:=Base system\n  TITLE:=SELinux reference policy\n  URL:=http://selinuxproject.org/page/Main_Page\n  PKGARCH:=all\nendef\n\ndefine Package/refpolicy/description\n\tThe SELinux Reference Policy project (refpolicy) is a\n\tcomplete SELinux policy that can be used as the system\n\tpolicy for a variety of systems and used as the basis for\n\tcreating other policies. Reference Policy was originally\n\tbased on the NSA example policy, but aims to accomplish many\n\tadditional goals.\n\n\tThe current refpolicy does not fully support OpenWRT and\n\tneeds modifications to work with the default system file\n\tlayout. These changes should be added as patches to the\n\trefpolicy that modify a single SELinux policy.\n\n\tThe refpolicy works for the most part in permissive\n\tmode. Only the basic set of utilities are enabled in the\n\texample policy config and some of the pathing in the\n\tpolicies is not correct.  Individual policies would need to\n\tbe tweaked to get everything functioning properly.\nendef\n\n# Yes, we want CC=$(HOSTCC) because the only code that checkpolicy\n# builds is a small host tool that gets run as part of the build\n# process.\nMAKE_FLAGS += \\\n\tSETFILES=\"$(STAGING_DIR_HOST)/bin/setfiles\" \\\n\tCHECKPOLICY=\"$(STAGING_DIR_HOSTPKG)/bin/checkpolicy\" \\\n\tCC=\"$(HOSTCC)\" \\\n\tCFLAGS=\"$(HOST_CFLAGS)\"\n\ndefine Build/Configure\n\t$(SED) \"/MONOLITHIC/c\\MONOLITHIC = y\" $(PKG_BUILD_DIR)/build.conf\n\t$(SED) \"/NAME/c\\NAME = targeted\" $(PKG_BUILD_DIR)/build.conf\n\t$(call Build/Compile/Default,conf)\nendef\n\ndefine Package/refpolicy/conffiles\n/etc/selinux/config\nendef\n\ndefine Package/refpolicy/install\n\t$(INSTALL_DIR) $(1)/etc/selinux\n\t$(CP) $(PKG_INSTALL_DIR)/etc/selinux/* $(1)/etc/selinux/\n\t$(CP) ./files/selinux-config $(1)/etc/selinux/config\nendef\n\n$(eval $(call BuildPackage,refpolicy))\n"
  },
  {
    "path": "package/system/refpolicy/files/selinux-config",
    "content": "# This file controls the state of SELinux on the system.\n# SELINUX= can take one of these three values:\n#     enforcing - SELinux security policy is enforced.\n#     permissive - SELinux prints warnings instead of enforcing.\n#     disabled - No SELinux policy is loaded.\nSELINUX=permissive\nSELINUXTYPE=targeted\n"
  },
  {
    "path": "package/system/refpolicy/patches/100-no-docs.patch",
    "content": "Index: refpolicy-2.20200229/Makefile\n===================================================================\n--- refpolicy-2.20200229.orig/Makefile\n+++ refpolicy-2.20200229/Makefile\n@@ -648,6 +648,6 @@ ifneq ($(generated_fc),)\n endif\n endif\n \n-.PHONY: install-src install-appconfig install-headers generate xml conf html bare tags\n+.PHONY: install-src install-appconfig install-headers generate conf bare tags\n .SUFFIXES:\n .SUFFIXES: .c\n"
  },
  {
    "path": "package/system/rpcd/Makefile",
    "content": "#\n# Copyright (C) 2013-2016 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=rpcd\nPKG_RELEASE:=1\n\nPKG_SOURCE_PROTO:=git\nPKG_SOURCE_URL=$(PROJECT_GIT)/project/rpcd.git\nPKG_MIRROR_HASH:=186a7246c610fecc282b0966213350ff4508b0db88739345e7c79792db0423ce\nPKG_SOURCE_DATE:=2022-02-07\nPKG_SOURCE_VERSION:=909f2a04763dbc745488384b24281eca180452d6\nPKG_MAINTAINER:=Jo-Philipp Wich <jo@mein.io>\n\nPKG_LICENSE:=ISC\nPKG_LICENSE_FILES:=\n\nPKG_ASLR_PIE_REGULAR:=1\n\ninclude $(INCLUDE_DIR)/package.mk\ninclude $(INCLUDE_DIR)/cmake.mk\n\ndefine Build/InstallDev\n\t$(INSTALL_DIR) $(1)/usr/include\n\t$(CP) $(PKG_BUILD_DIR)/include/rpcd $(1)/usr/include/\nendef\n\ndefine Package/rpcd/default\n  SECTION:=utils\n  CATEGORY:=Base system\n  TITLE:=OpenWrt ubus RPC backend server\n  DEPENDS:=+libubus +libubox\nendef\n\ndefine Package/rpcd\n  $(Package/rpcd/default)\n  DEPENDS+= +libuci +libblobmsg-json +libjson-c\nendef\n\ndefine Package/rpcd/description\n This package provides the UBUS RPC backend server to expose various\n functionality to frontend programs via JSON-RPC.\nendef\n\ndefine Package/rpcd/conffiles\n/etc/config/rpcd\nendef\n\nTARGET_LDFLAGS += -lcrypt\n\ndefine Package/rpcd/install\n\t$(INSTALL_DIR) $(1)/etc/init.d\n\t$(INSTALL_BIN) ./files/rpcd.init $(1)/etc/init.d/rpcd\n\t$(INSTALL_DIR) $(1)/sbin\n\t$(INSTALL_BIN) $(PKG_BUILD_DIR)/rpcd $(1)/sbin/rpcd\n\t$(INSTALL_DIR) $(1)/usr/share/rpcd/acl.d\n\t$(INSTALL_DATA) $(PKG_BUILD_DIR)/unauthenticated.json $(1)/usr/share/rpcd/acl.d/unauthenticated.json\n\t$(INSTALL_DIR) $(1)/etc/config\n\t$(INSTALL_CONF) ./files/rpcd.config $(1)/etc/config/rpcd\n\t$(INSTALL_DIR) $(1)/etc/uci-defaults\n\t$(INSTALL_BIN) ./files/50-migrate-rpcd-ubus-sock.sh $(1)/etc/uci-defaults\nendef\n\n\n# 1: plugin name\n# 2: extra dependencies\n# 3: plugin title/description\ndefine BuildPlugin\n\n  PKG_CONFIG_DEPENDS += CONFIG_PACKAGE_rpcd-mod-$(1)\n\n  define Package/rpcd-mod-$(1)\n    $(Package/rpcd/default)\n    TITLE+= ($(1) plugin)\n    DEPENDS+=rpcd $(2)\n  endef\n\n  define Package/rpcd-mod-$(1)/description\n    $(3)\n  endef\n\n  define Package/rpcd-mod-$(1)/postinst\n#!/bin/sh\n[ -n \"$$$${IPKG_INSTROOT}\" ] || /etc/init.d/rpcd reload\n  endef\n\n  define Package/rpcd-mod-$(1)/install\n\t$(INSTALL_DIR) $$(1)/usr/lib/rpcd\n\t$(INSTALL_BIN) $(PKG_BUILD_DIR)/$(1).so $$(1)/usr/lib/rpcd/\n  endef\n\n  $$(eval $$(call BuildPackage,rpcd-mod-$(1)))\n\nendef\n\n$(eval $(call BuildPackage,rpcd))\n$(eval $(call BuildPlugin,file,,Provides ubus calls for file and directory operations.))\n$(eval $(call BuildPlugin,rpcsys,,Provides ubus calls for sysupgrade and password changing.))\n$(eval $(call BuildPlugin,iwinfo,+libiwinfo,Provides ubus calls for accessing iwinfo data.))\n$(eval $(call BuildPlugin,ucode,+libucode,Allows implementing plugins using ucode scripts.))\n"
  },
  {
    "path": "package/system/rpcd/files/50-migrate-rpcd-ubus-sock.sh",
    "content": "#!/bin/sh\n\n[ \"$(uci get rpcd.@rpcd[0].socket)\" = \"/var/run/ubus.sock\" ] || exit 0\n\nuci set rpcd.@rpcd[0].socket='/var/run/ubus/ubus.sock'\nuci commit rpcd\n\nexit 0\n"
  },
  {
    "path": "package/system/rpcd/files/rpcd.config",
    "content": "config rpcd\n\toption socket /var/run/ubus/ubus.sock\n\toption timeout 30\n\nconfig login\n\toption username 'root'\n\toption password '$p$root'\n\tlist read '*'\n\tlist write '*'\n\n"
  },
  {
    "path": "package/system/rpcd/files/rpcd.init",
    "content": "#!/bin/sh /etc/rc.common\n\nSTART=12\n\nUSE_PROCD=1\nNAME=rpcd\nPROG=/sbin/rpcd\n\nstart_service() {\n\tlocal socket=$(uci -q get rpcd.@rpcd[0].socket)\n\tlocal timeout=$(uci -q get rpcd.@rpcd[0].timeout)\n\n\tprocd_open_instance\n\tprocd_set_param command \"$PROG\" ${socket:+-s \"$socket\"} ${timeout:+-t \"$timeout\"}\n\tprocd_set_param respawn\n\tprocd_close_instance\n}\n\nreload_service() {\n\tprocd_send_signal rpcd\n}\n"
  },
  {
    "path": "package/system/selinux-policy/Makefile",
    "content": "#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=selinux-policy\nPKG_SOURCE_PROTO:=git\nPKG_SOURCE_URL:=https://git.defensec.nl/selinux-policy.git\nPKG_VERSION:=1.1\nPKG_MIRROR_HASH:=657ec1ff51ab946753fb3559384511a536ac1e018691f3e49cbab21c55d23e08\nPKG_SOURCE_VERSION:=v$(PKG_VERSION)\nPKG_BUILD_DEPENDS:=secilc/host policycoreutils/host\n\nPKG_MAINTAINER:=Dominick Grift <dominick.grift@defensec.nl>\nPKG_CPE_ID:=cpe:/a:defensec:selinux-policy\nPKG_LICENSE:=Unlicense\nPKG_LICENSE_FILES:=LICENSE\n\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine Package/selinux-policy\n\tSECTION:=system\n\tCATEGORY:=Base system\n\tTITLE:=SELinux security policy for OpenWrt\n\tURL:=https://git.defensec.nl/?p=selinux-policy.git;a=summary\n\tPKGARCH:=all\nendef\n\ndefine Package/selinux-policy/description\n\tBasic SELinux Security Policy designed specifically for\n\tOpenWrt and written in Common Intermediate Language.\nendef\n\ndefine Build/Compile\n\t$(call Build/Compile/Default,policy)\nendef\n\ndefine Package/selinux-policy/conffiles\n/etc/selinux/config\nendef\n\ndefine Package/selinux-policy/install\n\t$(INSTALL_DIR) $(1)/etc/selinux/$(PKG_NAME)/contexts/files/\n\t$(INSTALL_DIR) $(1)/etc/selinux/$(PKG_NAME)/policy/\n\t$(INSTALL_DATA) $(PKG_BUILD_DIR)/customizable_types $(1)/etc/selinux/$(PKG_NAME)/contexts/\n\t$(INSTALL_DATA) $(PKG_BUILD_DIR)/file_contexts.subs_dist $(1)/etc/selinux/$(PKG_NAME)/contexts/files/\n\t$(INSTALL_DATA) $(PKG_BUILD_DIR)/file_contexts $(1)/etc/selinux/$(PKG_NAME)/contexts/files/\n\t$(INSTALL_CONF) $(PKG_BUILD_DIR)/policy.* $(1)/etc/selinux/$(PKG_NAME)/policy/\n\t$(INSTALL_DATA) ./files/selinux-config $(1)/etc/selinux/config\nendef\n\n$(eval $(call BuildPackage,selinux-policy))\n"
  },
  {
    "path": "package/system/selinux-policy/files/selinux-config",
    "content": "SELINUX=enforcing\nSELINUXTYPE=selinux-policy\n"
  },
  {
    "path": "package/system/ubox/Makefile",
    "content": "include $(TOPDIR)/rules.mk\n\nPKG_NAME:=ubox\nPKG_RELEASE:=2\n\nPKG_SOURCE_PROTO:=git\nPKG_SOURCE_URL=$(PROJECT_GIT)/project/ubox.git\nPKG_SOURCE_DATE:=2022-01-06\nPKG_SOURCE_VERSION:=b87a4fdca6346a01c19e94fe0461fb9ef7493815\nPKG_MIRROR_HASH:=4b41596fa00637134b23175a4952de66ff80b2edb956f685347f146d90d910c5\nCMAKE_INSTALL:=1\n\nPKG_LICENSE:=GPL-2.0\nPKG_LICENSE_FILES:=\n\nPKG_MAINTAINER:=John Crispin <john@phrozen.org>\n\ninclude $(INCLUDE_DIR)/package.mk\ninclude $(INCLUDE_DIR)/cmake.mk\n\nTARGET_LDFLAGS += $(if $(CONFIG_USE_GLIBC),-lrt)\n\ndefine Package/ubox\n  SECTION:=base\n  CATEGORY:=Base system\n  DEPENDS:=+libubox +ubusd +ubus +libubus +libuci +USE_GLIBC:librt\n  TITLE:=OpenWrt system helper toolbox\n  ALTERNATIVES:=\\\n    100:/sbin/rmmod:/sbin/kmodloader \\\n    100:/sbin/insmod:/sbin/kmodloader \\\n    100:/sbin/lsmod:/sbin/kmodloader \\\n    100:/sbin/modinfo:/sbin/kmodloader \\\n    100:/sbin/modprobe:/sbin/kmodloader\nendef\n\ndefine Package/ubox/conffiles\n/etc/modules.conf\nendef\n\ndefine Package/getrandom\n  SECTION:=base\n  CATEGORY:=Base system\n  TITLE:=OpenWrt getrandom system helper\nendef\n\ndefine Package/logd\n  SECTION:=base\n  CATEGORY:=Base system\n  DEPENDS:=+libubox +libubus +libblobmsg-json +USE_GLIBC:librt\n  TITLE:=OpenWrt system log implementation\n  USERID:=logd=514:logd=514\nendef\n\ndefine Package/getrandom/install\n\t$(INSTALL_DIR) $(1)/usr/bin\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/bin/getrandom $(1)/usr/bin/\nendef\n\ndefine Package/ubox/install\n\t$(INSTALL_DIR) $(1)/sbin $(1)/usr/sbin $(1)/lib $(1)/usr/bin $(1)/etc\n\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/sbin/{kmodloader,validate_data} $(1)/sbin/\n\t$(INSTALL_DATA) $(PKG_INSTALL_DIR)/usr/lib/libvalidate.so $(1)/lib\n\t$(INSTALL_DATA) ./files/modules.conf $(1)/etc/modules.conf\nendef\n\ndefine Package/logd/install\n\t$(INSTALL_DIR) $(1)/sbin $(1)/etc/init.d/\n\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/sbin/{logd,logread} $(1)/sbin/\n\t$(INSTALL_BIN) ./files/log.init $(1)/etc/init.d/log\nendef\n\n$(eval $(call BuildPackage,ubox))\n$(eval $(call BuildPackage,getrandom))\n$(eval $(call BuildPackage,logd))\n"
  },
  {
    "path": "package/system/ubox/files/log.init",
    "content": "#!/bin/sh /etc/rc.common\n# Copyright (C) 2013 OpenWrt.org\n\n# start after and stop before networking\nSTART=12\nSTOP=89\nPIDCOUNT=0\n\nUSE_PROCD=1\nPROG=/sbin/logread\n\nvalidate_log_section()\n{\n\tuci_load_validate system system \"$1\" \"$2\" \\\n\t\t'log_file:string' \\\n\t\t'log_size:uinteger' \\\n\t\t'log_hostname:string' \\\n\t\t'log_ip:host' \\\n\t\t'log_remote:bool:1' \\\n\t\t'log_port:port:514' \\\n\t\t'log_proto:or(\"tcp\", \"udp\"):udp' \\\n\t\t'log_trailer_null:bool:0' \\\n\t\t'log_prefix:string'\n}\n\nvalidate_log_daemon()\n{\n\tuci_load_validate system system \"$1\" \"$2\" \\\n\t\t'log_size:uinteger:0' \\\n\t\t'log_buffer_size:uinteger:0'\n}\n\nstart_service_daemon()\n{\n\t[ $log_buffer_size -eq 0 -a $log_size -gt 0 ] && log_buffer_size=$log_size\n\t[ $log_buffer_size -eq 0 ] && log_buffer_size=64\n\tprocd_open_instance logd\n\tprocd_set_param command \"/sbin/logd\"\n\tprocd_append_param command -S \"${log_buffer_size}\"\n\tprocd_set_param respawn 5 1 -1\n\tprocd_close_instance\n}\n\nstart_service_file()\n{\n\tPIDCOUNT=\"$(( ${PIDCOUNT} + 1))\"\n\tlocal pid_file=\"/var/run/logread.${PIDCOUNT}.pid\"\n\n\t[ \"$2\" = 0 ] || {\n\t\techo \"validation failed\"\n\t\treturn 1\n\t}\n\t[ -z \"${log_file}\" ] && return\n\n\t[ \"$_BOOT\" = \"1\" ] &&\n\t\t[ \"$(procd_get_mountpoints \"${log_file}\")\" ] && return 0\n\n\tmkdir -p \"$(dirname \"${log_file}\")\"\n\n\tprocd_open_instance logfile\n\tprocd_set_param command \"$PROG\" -f -F \"$log_file\" -p \"$pid_file\"\n\t[ -n \"${log_size}\" ] && procd_append_param command -S \"$log_size\"\n\tprocd_close_instance\n}\n\nstart_service_remote()\n{\n\tPIDCOUNT=\"$(( ${PIDCOUNT} + 1))\"\n\tlocal pid_file=\"/var/run/logread.${PIDCOUNT}.pid\"\n\n\t[ \"$2\" = 0 ] || {\n\t\techo \"validation failed\"\n\t\treturn 1\n\t}\n\t[ \"${log_remote}\" -ne 0 ] || return\n\t[ -z \"${log_ip}\" ] && return\n\t[ -z \"${log_hostname}\" ] && log_hostname=$(cat /proc/sys/kernel/hostname)\n\n\tprocd_open_instance logremote\n\tprocd_set_param command \"$PROG\" -f -h \"$log_hostname\" -r \"$log_ip\" \"${log_port}\" -p \"$pid_file\"\n\tcase \"${log_proto}\" in\n\t\t\"udp\") procd_append_param command -u;;\n\t\t\"tcp\") [ \"${log_trailer_null}\" -eq 1 ] && procd_append_param command -0;;\n\tesac\n\t[ -z \"${log_prefix}\" ] || procd_append_param command -P \"${log_prefix}\"\n\tprocd_close_instance\n}\n\nregister_mount_trigger()\n{\n\t[ -n \"${log_file}\" ] && procd_add_action_mount_trigger start \"${log_file}\"\n}\n\nservice_triggers()\n{\n\tconfig_load system\n\tprocd_add_reload_trigger \"system\"\n\tprocd_add_validation validate_log_section\n\tconfig_foreach validate_log_section system register_mount_trigger\n}\n\nstart_service()\n{\n\tconfig_load system\n\tconfig_foreach validate_log_daemon system start_service_daemon\n\tconfig_foreach validate_log_section system start_service_file\n\tconfig_foreach validate_log_section system start_service_remote\n}\n\nboot() {\n\t_BOOT=1 start\n}\n"
  },
  {
    "path": "package/system/ubox/files/modules.conf",
    "content": "# examples:\n# options mod1 option=val\n# blacklist mod2\n"
  },
  {
    "path": "package/system/ubus/Makefile",
    "content": "include $(TOPDIR)/rules.mk\n\nPKG_NAME:=ubus\nPKG_RELEASE:=2\n\nPKG_SOURCE_PROTO:=git\nPKG_SOURCE_URL=$(PROJECT_GIT)/project/ubus.git\nPKG_SOURCE_DATE:=2022-02-28\nPKG_SOURCE_VERSION:=584f56a2331471459604ad054b3a7bcc366e0f07\nPKG_MIRROR_HASH:=9bb7025fa5513530e6f407e0514014a8116babe9287d4217d0b8f9315b1f2181\nPKG_ABI_VERSION:=$(call abi_version_str,$(PKG_SOURCE_DATE))\nCMAKE_INSTALL:=1\n\nPKG_LICENSE:=LGPL-2.1\nPKG_LICENSE_FILES:=\nPKG_MAINTAINER:=Felix Fietkau <nbd@nbd.name>\n\nPKG_ASLR_PIE_REGULAR:=1\n\ninclude $(INCLUDE_DIR)/package.mk\ninclude $(INCLUDE_DIR)/cmake.mk\n\ndefine Package/ubus\n  SECTION:=base\n  CATEGORY:=Base system\n  DEPENDS:=+libubus +libblobmsg-json +ubusd\n  TITLE:=OpenWrt RPC client utility\nendef\n\ndefine Package/ubusd\n  SECTION:=base\n  CATEGORY:=Base system\n  TITLE:=OpenWrt RPC daemon\n  DEPENDS:=+libubox +libblobmsg-json\n  USERID:=ubus=81:ubus=81\nendef\n\ndefine Package/libubus\n  SECTION:=libs\n  CATEGORY:=Libraries\n  DEPENDS:=+libubox\n  ABI_VERSION:=$(PKG_ABI_VERSION)\n  TITLE:=OpenWrt RPC client library\nendef\n\ndefine Package/libubus-lua\n  SECTION:=libs\n  CATEGORY:=Libraries\n  DEPENDS:=+libubus +liblua\n  TITLE:=Lua binding for the OpenWrt RPC client\nendef\n\nTARGET_CFLAGS += -I$(STAGING_DIR)/usr/include -flto\nTARGET_LDFLAGS += -flto\n\nCMAKE_OPTIONS += \\\n\t-DLUAPATH=/usr/lib/lua \\\n\t-DABIVERSION=\"$(PKG_ABI_VERSION)\"\n\ndefine Package/ubus/install\n\t$(INSTALL_DIR) $(1)/bin\n\t$(CP) $(PKG_INSTALL_DIR)/usr/bin/ubus $(1)/bin/\nendef\n\ndefine Package/ubusd/install\n\t$(INSTALL_DIR) $(1)/sbin\n\t$(CP) $(PKG_INSTALL_DIR)/usr/sbin/ubusd $(1)/sbin/\nendef\n\ndefine Package/libubus/install\n\t$(INSTALL_DIR) $(1)/lib\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/libubus.so.* $(1)/lib/\nendef\n\ndefine Package/libubus-lua/install\n\t$(INSTALL_DIR) $(1)/usr/lib/lua\n\t$(CP) $(PKG_BUILD_DIR)/lua/ubus.so $(1)/usr/lib/lua/\nendef\n\n$(eval $(call BuildPackage,libubus))\n$(eval $(call BuildPackage,libubus-lua))\n$(eval $(call BuildPackage,ubus))\n$(eval $(call BuildPackage,ubusd))\n"
  },
  {
    "path": "package/system/ucert/Makefile",
    "content": "include $(TOPDIR)/rules.mk\n\nPKG_NAME:=ucert\nPKG_RELEASE:=1\n\nPKG_SOURCE_PROTO:=git\nPKG_SOURCE_URL=$(PROJECT_GIT)/project/ucert.git\nPKG_SOURCE_DATE:=2020-05-24\nPKG_SOURCE_VERSION:=00b921d80ac0dc47339305d803f865ff43c56d63\nPKG_MIRROR_HASH:=839fda1811a58a495ac7bbc41db75222dd5a15e4d72110ca6acc4cdad56908fe\n\nCMAKE_INSTALL:=1\nPKG_CHECK_FORMAT_SECURITY:=1\n\nPKG_LICENSE:=GPL-3.0+\nPKG_LICENSE_FILES:=COPYING\n\nPKG_MAINTAINER:=Daniel Golle <daniel@makrotopia.org>\n\ninclude $(INCLUDE_DIR)/package.mk\ninclude $(INCLUDE_DIR)/host-build.mk\ninclude $(INCLUDE_DIR)/cmake.mk\n\nCMAKE_HOST_OPTIONS += \\\n\t-DUCERT_FULL=1 \\\n\t-DUCERT_HOST_BUILD=1 \\\n\t-DCMAKE_SKIP_RPATH=FALSE \\\n\t-DUSE_RPATH=\"${STAGING_DIR_HOST}/lib\"\n\nHOST_BUILD_DEPENDS:=libubox/host libjson-c/host usign/host\nHOST_BUILD_PREFIX:=$(STAGING_DIR_HOST)\nPKG_BUILD_DEPENDS:=ucert/host\n\ndefine Package/ucert-full\n  SECTION:=base\n  CATEGORY:=Base system\n  DEPENDS:=+usign +libubox +libjson-c +libblobmsg-json\n  TITLE:=OpenWrt certificate generation and verification utility\n  PROVIDES:=ucert\n  VARIANT:=full\nendef\n\ndefine Package/ucert\n  SECTION:=base\n  CATEGORY:=Base system\n  DEPENDS:=+usign +libubox\n  TITLE:=OpenWrt certificate verification utility\n  PROVIDES:=ucert\n  CONFLICTS:=ucert-full\n  VARIANT:=tiny\nendef\n\nifeq ($(BUILD_VARIANT),full)\n  CMAKE_OPTIONS += -DUCERT_FULL=1\nendif\n\ndefine Build/Prepare\n\tmkdir -p $(PKG_BUILD_DIR)\n\t$(call Build/Prepare/Default)\nendef\n\ndefine Package/ucert/install\n\t$(INSTALL_DIR) $(1)/usr/bin\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/bin/ucert $(1)/usr/bin\nendef\n\nPackage/ucert-full/install = $(Package/ucert/install)\n\n$(eval $(call BuildPackage,ucert))\n$(eval $(call BuildPackage,ucert-full))\n$(eval $(call HostBuild))\n"
  },
  {
    "path": "package/system/uci/Makefile",
    "content": "#\n# Copyright (C) 2008-2014 OpenWrt.org\n# Copyright (C) 2016 LEDE project\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=uci\nPKG_RELEASE:=6\n\nPKG_SOURCE_URL=$(PROJECT_GIT)/project/uci.git\nPKG_SOURCE_PROTO:=git\nPKG_SOURCE_DATE=2021-10-22\nPKG_SOURCE_VERSION:=f84f49f00fb70364f58b4cce72f1796a7190d370\nPKG_MIRROR_HASH:=9f4747a029976b43fcea9919643ce71e587e515edc21b280163f7262360d847f\n\nPKG_LICENSE:=LGPL-2.1\nPKG_LICENSE_FILES:=\n\nPKG_MAINTAINER:=Felix Fietkau <nbd@nbd.name>\n\ninclude $(INCLUDE_DIR)/package.mk\ninclude $(INCLUDE_DIR)/cmake.mk\n\n# set to 1 to enable debugging\nDEBUG=\n\ndefine Package/libuci\n  SECTION:=libs\n  CATEGORY:=Libraries\n  TITLE:=C library for the Unified Configuration Interface (UCI)\n  DEPENDS:=+libubox\n  ABI_VERSION:=20130104\nendef\n\ndefine Package/uci\n  SECTION:=base\n  CATEGORY:=Base system\n  DEPENDS:=+libuci\n  TITLE:=Utility for the Unified Configuration Interface (UCI)\nendef\n\ndefine Package/libuci-lua\n  SECTION=libs\n  CATEGORY=Libraries\n  DEPENDS:=+libuci +liblua\n  TITLE:=Lua plugin for UCI\nendef\n\nTARGET_CFLAGS += -I$(STAGING_DIR)/usr/include\nTARGET_LDFLAGS += -L$(STAGING_DIR)/usr/lib\n\nCMAKE_OPTIONS += \\\n\t-DLUAPATH=/usr/lib/lua \\\n\t$(if $(DEBUG),-DUCI_DEBUG=ON)\n\ndefine Package/libuci/install\n\t$(INSTALL_DIR) $(1)/lib\n\t$(CP) $(PKG_BUILD_DIR)/libuci.so* $(1)/lib/\nendef\n\ndefine Package/libuci-lua/install\n\t$(INSTALL_DIR) $(1)/usr/lib/lua\n\t$(CP) $(PKG_BUILD_DIR)/lua/uci.so $(1)/usr/lib/lua/\nendef\n\ndefine Package/uci/install\n\t$(INSTALL_DIR) $(1)/etc/uci-defaults\n\t$(INSTALL_DIR) $(1)/sbin\n\t$(INSTALL_BIN) $(PKG_BUILD_DIR)/uci $(1)/sbin/\n\t$(CP) ./files/* $(1)/\nendef\n\ndefine Build/InstallDev\n\t$(INSTALL_DIR) $(1)/usr/include\n\t$(CP) $(PKG_BUILD_DIR)/uci{,_config,_blob,map}.h $(1)/usr/include\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(CP) $(PKG_BUILD_DIR)/libuci.so* $(1)/usr/lib\n\t$(CP) $(PKG_BUILD_DIR)/libucimap.a $(1)/usr/lib\nendef\n\n$(eval $(call BuildPackage,libuci))\n$(eval $(call BuildPackage,libuci-lua))\n$(eval $(call BuildPackage,uci))\n"
  },
  {
    "path": "package/system/uci/files/lib/config/uci.sh",
    "content": "# Shell script compatibility wrappers for /sbin/uci\n#\n# Copyright (C) 2008-2010  OpenWrt.org\n# Copyright (C) 2008  Felix Fietkau <nbd@nbd.name>\n#\n# This program is free software; you can redistribute it and/or modify\n# it under the terms of the GNU General Public License as published by\n# the Free Software Foundation; either version 2 of the License, or\n# (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU\n# General Public License for more details.\n#\n# You should have received a copy of the GNU General Public License\n# along with this program; if not, write to the Free Software\n# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\n\nCONFIG_APPEND=\nuci_load() {\n\tlocal PACKAGE=\"$1\"\n\tlocal DATA\n\tlocal RET\n\tlocal VAR\n\n\t_C=0\n\tif [ -z \"$CONFIG_APPEND\" ]; then\n\t\tfor VAR in $CONFIG_LIST_STATE; do\n\t\t\texport ${NO_EXPORT:+-n} CONFIG_${VAR}=\n\t\t\texport ${NO_EXPORT:+-n} CONFIG_${VAR}_LENGTH=\n\t\tdone\n\t\texport ${NO_EXPORT:+-n} CONFIG_LIST_STATE=\n\t\texport ${NO_EXPORT:+-n} CONFIG_SECTIONS=\n\t\texport ${NO_EXPORT:+-n} CONFIG_NUM_SECTIONS=0\n\t\texport ${NO_EXPORT:+-n} CONFIG_SECTION=\n\tfi\n\n\tDATA=\"$(/sbin/uci ${UCI_CONFIG_DIR:+-c $UCI_CONFIG_DIR} ${LOAD_STATE:+-P /var/state} -S -n export \"$PACKAGE\" 2>/dev/null)\"\n\tRET=\"$?\"\n\t[ \"$RET\" != 0 -o -z \"$DATA\" ] || eval \"$DATA\"\n\tunset DATA\n\n\t${CONFIG_SECTION:+config_cb}\n\treturn \"$RET\"\n}\n\nuci_set_default() {\n\tlocal PACKAGE=\"$1\"\n\t/sbin/uci ${UCI_CONFIG_DIR:+-c $UCI_CONFIG_DIR} -q show \"$PACKAGE\" > /dev/null && return 0\n\t/sbin/uci ${UCI_CONFIG_DIR:+-c $UCI_CONFIG_DIR} import \"$PACKAGE\"\n\t/sbin/uci ${UCI_CONFIG_DIR:+-c $UCI_CONFIG_DIR} commit \"$PACKAGE\"\n}\n\nuci_revert_state() {\n\tlocal PACKAGE=\"$1\"\n\tlocal CONFIG=\"$2\"\n\tlocal OPTION=\"$3\"\n\n\t/sbin/uci ${UCI_CONFIG_DIR:+-c $UCI_CONFIG_DIR} -P /var/state revert \"$PACKAGE${CONFIG:+.$CONFIG}${OPTION:+.$OPTION}\"\n}\n\nuci_set_state() {\n\tlocal PACKAGE=\"$1\"\n\tlocal CONFIG=\"$2\"\n\tlocal OPTION=\"$3\"\n\tlocal VALUE=\"$4\"\n\n\t[ \"$#\" = 4 ] || return 0\n\t/sbin/uci ${UCI_CONFIG_DIR:+-c $UCI_CONFIG_DIR} -P /var/state set \"$PACKAGE.$CONFIG${OPTION:+.$OPTION}=$VALUE\"\n}\n\nuci_toggle_state() {\n\tuci_revert_state \"$1\" \"$2\" \"$3\"\n\tuci_set_state \"$1\" \"$2\" \"$3\" \"$4\"\n}\n\nuci_set() {\n\tlocal PACKAGE=\"$1\"\n\tlocal CONFIG=\"$2\"\n\tlocal OPTION=\"$3\"\n\tlocal VALUE=\"$4\"\n\n\t/sbin/uci ${UCI_CONFIG_DIR:+-c $UCI_CONFIG_DIR} set \"$PACKAGE.$CONFIG.$OPTION=$VALUE\"\n}\n\nuci_add_list() {\n\tlocal PACKAGE=\"$1\"\n\tlocal CONFIG=\"$2\"\n\tlocal OPTION=\"$3\"\n\tlocal VALUE=\"$4\"\n\n\t/sbin/uci ${UCI_CONFIG_DIR:+-c $UCI_CONFIG_DIR} add_list \"$PACKAGE.$CONFIG.$OPTION=$VALUE\"\n}\n\nuci_get_state() {\n\tuci_get \"$1\" \"$2\" \"$3\" \"$4\" \"/var/state\"\n}\n\nuci_get() {\n\tlocal PACKAGE=\"$1\"\n\tlocal CONFIG=\"$2\"\n\tlocal OPTION=\"$3\"\n\tlocal DEFAULT=\"$4\"\n\tlocal STATE=\"$5\"\n\n\t/sbin/uci ${UCI_CONFIG_DIR:+-c $UCI_CONFIG_DIR} ${STATE:+-P $STATE} -q get \"$PACKAGE${CONFIG:+.$CONFIG}${OPTION:+.$OPTION}\"\n\tRET=\"$?\"\n\t[ \"$RET\" -ne 0 ] && [ -n \"$DEFAULT\" ] && echo \"$DEFAULT\"\n\treturn \"$RET\"\n}\n\nuci_add() {\n\tlocal PACKAGE=\"$1\"\n\tlocal TYPE=\"$2\"\n\tlocal CONFIG=\"$3\"\n\n\tif [ -z \"$CONFIG\" ]; then\n\t\texport ${NO_EXPORT:+-n} CONFIG_SECTION=\"$(/sbin/uci ${UCI_CONFIG_DIR:+-c $UCI_CONFIG_DIR} add \"$PACKAGE\" \"$TYPE\")\"\n\telse\n\t\t/sbin/uci ${UCI_CONFIG_DIR:+-c $UCI_CONFIG_DIR} set \"$PACKAGE.$CONFIG=$TYPE\"\n\t\texport ${NO_EXPORT:+-n} CONFIG_SECTION=\"$CONFIG\"\n\tfi\n}\n\nuci_rename() {\n\tlocal PACKAGE=\"$1\"\n\tlocal CONFIG=\"$2\"\n\tlocal OPTION=\"$3\"\n\tlocal VALUE=\"$4\"\n\n\t/sbin/uci ${UCI_CONFIG_DIR:+-c $UCI_CONFIG_DIR} rename \"$PACKAGE.$CONFIG${VALUE:+.$OPTION}=${VALUE:-$OPTION}\"\n}\n\nuci_remove() {\n\tlocal PACKAGE=\"$1\"\n\tlocal CONFIG=\"$2\"\n\tlocal OPTION=\"$3\"\n\n\t/sbin/uci ${UCI_CONFIG_DIR:+-c $UCI_CONFIG_DIR} del \"$PACKAGE.$CONFIG${OPTION:+.$OPTION}\"\n}\n\nuci_remove_list() {\n\tlocal PACKAGE=\"$1\"\n\tlocal CONFIG=\"$2\"\n\tlocal OPTION=\"$3\"\n\tlocal VALUE=\"$4\"\n\n\t/sbin/uci ${UCI_CONFIG_DIR:+-c $UCI_CONFIG_DIR} del_list \"$PACKAGE.$CONFIG.$OPTION=$VALUE\"\n}\n\nuci_revert() {\n\tlocal PACKAGE=\"$1\"\n\tlocal CONFIG=\"$2\"\n\tlocal OPTION=\"$3\"\n\n\t/sbin/uci ${UCI_CONFIG_DIR:+-c $UCI_CONFIG_DIR} revert \"$PACKAGE${CONFIG:+.$CONFIG}${OPTION:+.$OPTION}\"\n}\n\nuci_commit() {\n\tlocal PACKAGE=\"$1\"\n\t/sbin/uci ${UCI_CONFIG_DIR:+-c $UCI_CONFIG_DIR} commit $PACKAGE\n}\n"
  },
  {
    "path": "package/system/urandom-seed/Makefile",
    "content": "include $(TOPDIR)/rules.mk\n\nPKG_NAME:=urandom-seed\nPKG_RELEASE:=3\nPKG_LICENSE:=GPL-2.0-only\n\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine Package/urandom-seed\n  SECTION:=base\n  CATEGORY:=Base system\n  DEPENDS:=+getrandom\n  TITLE:=/etc/urandom.seed handling for OpenWrt\n  URL:=https://openwrt.org/\nendef\n\ndefine Build/Prepare\n\tmkdir -p $(PKG_BUILD_DIR)\nendef\n\ndefine Build/Compile/Default\nendef\nBuild/Compile = $(Build/Compile/Default)\n\ndefine Package/urandom-seed/install\n\t$(CP) ./files/* $(1)/\nendef\n\n$(eval $(call BuildPackage,urandom-seed))\n"
  },
  {
    "path": "package/system/urandom-seed/files/etc/init.d/urandom_seed",
    "content": "#!/bin/sh /etc/rc.common\n\nSTART=99\nUSE_PROCD=1\n\nstart_service() {\n    procd_open_instance \"urandom_seed\"\n    procd_set_param command \"/sbin/urandom_seed\"\n    procd_set_param stdout 1\n    procd_set_param stderr 1\n    procd_close_instance\n}\n"
  },
  {
    "path": "package/system/urandom-seed/files/lib/preinit/81_urandom_seed",
    "content": "log_urandom_seed() {\n    echo \"urandom-seed: $1\" > /dev/kmsg\n}\n\n_do_urandom_seed() {\n    [ -f \"$1\" ] || { log_urandom_seed \"Seed file not found ($1)\"; return; }\n    [ -O \"$1\" -a -G \"$1\" -a ! -x \"$1\" ] || { log_urandom_seed \"Wrong owner / permissions for $1\"; return; }\n\n    log_urandom_seed \"Seeding with $1\"\n    cat \"$1\" > /dev/urandom\n}\n\ndo_urandom_seed() {\n    [ -c /dev/urandom ] || { log_urandom_seed \"Something is wrong with /dev/urandom\"; return; }\n\n    _do_urandom_seed \"/etc/urandom.seed\"\n\n    SEED=\"$(uci -q get system.@system[0].urandom_seed)\"\n    [ \"${SEED:0:1}\" = \"/\" -a \"$SEED\" != \"/etc/urandom.seed\" ] && _do_urandom_seed \"$SEED\"\n}\n\nboot_hook_add preinit_main do_urandom_seed\n"
  },
  {
    "path": "package/system/urandom-seed/files/sbin/urandom_seed",
    "content": "#!/bin/sh\nset -e\n\ntrap '[ \"$?\" -eq 0 ] || echo \"An error occured\" >&2' EXIT\n\nsave() {\n    touch \"$1.tmp\"\n    chown root:root \"$1.tmp\"\n    chmod 600 \"$1.tmp\"\n    getrandom 512 > \"$1.tmp\"\n    mv \"$1.tmp\" \"$1\"\n    echo \"Seed saved ($1)\"\n}\n\nSEED=\"$(uci -q get system.@system[0].urandom_seed || true)\"\n[ \"${SEED:0:1}\" = \"/\" ] && save \"$SEED\"\n\nSEED=/etc/urandom.seed\n[ ! -f $SEED ] && save \"$SEED\"\ntrue\n"
  },
  {
    "path": "package/system/urngd/Makefile",
    "content": "include $(TOPDIR)/rules.mk\n\nPKG_NAME:=urngd\nPKG_RELEASE:=1\n\nPKG_SOURCE_PROTO:=git\nPKG_SOURCE_URL=$(PROJECT_GIT)/project/urngd.git\nPKG_SOURCE_DATE:=2020-01-21\nPKG_SOURCE_VERSION:=c7f7b6b65b82eda4675b42d8cd28d76ea7aebf1a\nPKG_MIRROR_HASH:=2d31025b79fe130c579d6c3f4bf4dc12abc43a7319b20a5cdca24ae363ec70f3\n\nPKG_LICENSE:=GPL-2.0 BSD-3-Clause\nPKG_LICENSE_FILES:=\n\ninclude $(INCLUDE_DIR)/package.mk\ninclude $(INCLUDE_DIR)/cmake.mk\n\ndefine Package/urngd\n  SECTION:=utils\n  CATEGORY:=Base system\n  TITLE:=OpenWrt non-physical true random number generator based on timing jitter\n  DEPENDS:=+libubox\nendef\n\ndefine Package/urngd/description\n  urngd is OpenWrt's micro non-physical true random number generator based on\n  timing jitter.\n\n  Using the Jitter RNG core, the rngd provides an entropy source that feeds into\n  the Linux /dev/random device if its entropy runs low. It updates the\n  /dev/random entropy estimator such that the newly provided entropy unblocks\n  /dev/random.\n\n  The seeding of /dev/random also ensures that /dev/urandom benefits from\n  entropy. Especially during boot time, when the entropy of Linux is low, the\n  Jitter RNGd provides a source of sufficient entropy.\nendef\n\ndefine Package/urngd/install\n\t$(INSTALL_DIR) $(1)/etc/init.d\n\t$(INSTALL_BIN) ./files/$(PKG_NAME).init $(1)/etc/init.d/$(PKG_NAME)\n\t$(INSTALL_DIR) $(1)/sbin\n\t$(INSTALL_BIN) $(PKG_BUILD_DIR)/$(PKG_NAME) $(1)/sbin/$(PKG_NAME)\nendef\n\n$(eval $(call BuildPackage,urngd))\n"
  },
  {
    "path": "package/system/urngd/files/urngd.init",
    "content": "#!/bin/sh /etc/rc.common\n\nSTART=00\n\nUSE_PROCD=1\nNAME=urngd\nPROG=/sbin/urngd\n\nstart_service() {\n\tprocd_open_instance\n\tprocd_set_param command \"$PROG\"\n\tprocd_close_instance\n}\n\nreload_service() {\n\tprocd_send_signal $PROG\n}\n"
  },
  {
    "path": "package/system/usign/Makefile",
    "content": "include $(TOPDIR)/rules.mk\n\nPKG_NAME:=usign\nPKG_RELEASE:=1\n\nPKG_SOURCE_PROTO:=git\nPKG_SOURCE_URL=$(PROJECT_GIT)/project/usign.git\nPKG_SOURCE_DATE:=2020-05-23\nPKG_SOURCE_VERSION:=f1f65026a94137c91b5466b149ef3ea3f20091e9\nPKG_MIRROR_HASH:=3f6569a5e63fdfd032976ac0f79d736d3935101ac1b97fb370514b013c5e6bb6\nCMAKE_INSTALL:=1\nPKG_CHECK_FORMAT_SECURITY:=1\nPKG_USE_MIPS16:=0\n\nPKG_LICENSE:=ISC\nPKG_LICENSE_FILES:=\n\nPKG_MAINTAINER:=Felix Fietkau <nbd@nbd.name>\n\ninclude $(INCLUDE_DIR)/package.mk\ninclude $(INCLUDE_DIR)/host-build.mk\ninclude $(INCLUDE_DIR)/cmake.mk\n\nHOST_BUILD_PREFIX:=$(STAGING_DIR_HOST)\n\ndefine Package/usign\n  SECTION:=base\n  CATEGORY:=Base system\n  DEPENDS:=+libubox\n  TITLE:=OpenWrt signature verification utility\nendef\n\nTARGET_CFLAGS += -flto\nTARGET_LDFLAGS += -flto=jobserver\n\nCMAKE_OPTIONS += \\\n\t-DUSE_LIBUBOX=on\n\ndefine Package/usign/install\n\t$(INSTALL_DIR) $(1)/usr/bin\n\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/bin/usign $(1)/usr/bin\n\tln -s usign $(1)/usr/bin/signify\nendef\n\n$(eval $(call BuildPackage,usign))\n$(eval $(call HostBuild))\n"
  },
  {
    "path": "package/system/zram-swap/Makefile",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2013-2021 OpenWrt.org\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=zram-swap\nPKG_RELEASE:=$(AUTORELEASE)\n\nPKG_BUILD_DIR := $(BUILD_DIR)/$(PKG_NAME)\n\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine Package/zram-swap\n  SECTION:=utils\n  CATEGORY:=Base system\n  DEPENDS:= \\\n\t+@BUSYBOX_CONFIG_FEATURE_SWAPON_DISCARD \\\n\t+@BUSYBOX_CONFIG_FEATURE_SWAPON_PRI \\\n\t+@BUSYBOX_CONFIG_MKSWAP \\\n\t+@BUSYBOX_CONFIG_SWAPOFF \\\n\t+@BUSYBOX_CONFIG_SWAPON \\\n\t+kmod-zram\n  TITLE:=ZRAM swap scripts\n  PKGARCH:=all\nendef\n\ndefine Package/zram-swap/description\n A script to activate swaping on a compressed zram partition. This\n could be used to increase the available memory, by using compressed\n memory.\nendef\n\ndefine Build/Prepare\nendef\n\ndefine Build/Configure\nendef\n\ndefine Build/Compile\nendef\n\ndefine Package/zram-swap/install\n\t$(INSTALL_DIR) $(1)/etc/init.d\n\t$(INSTALL_BIN) ./files/zram.init $(1)/etc/init.d/zram\nendef\n\n$(eval $(call BuildPackage,zram-swap))\n"
  },
  {
    "path": "package/system/zram-swap/files/zram.init",
    "content": "#!/bin/sh /etc/rc.common\n\nSTART=15\n\nextra_command \"compact\" \"Trigger compaction for all zram swap devices\"\nextra_command \"status\" \"Print out information & statistics about zram swap devices\"\n\nram_getsize()\n{\n\tlocal line\n\n\twhile read line; do case \"$line\" in MemTotal:*) set $line; echo \"$2\"; break ;; esac; done </proc/meminfo\n}\n\nzram_getsize()\t# in megabytes\n{\n\tlocal zram_size=\"$( uci -q get system.@system[0].zram_size_mb )\"\n\tlocal ram_size=\"$( ram_getsize )\"\n\n\tif [ -z \"$zram_size\" ]; then\n\t\t# e.g. 6mb for 16mb-routers or 61mb for 128mb-routers\n\t\techo $(( ram_size / 2048 ))\n\telse\n\t\techo \"$zram_size\"\n\tfi\n}\n\nzram_dev()\n{\n\tlocal idx=\"$1\"\n\techo \"/dev/zram${idx:-0}\"\n}\n\nzram_reset()\n{\n\tlocal dev=\"$1\"\n\tlocal message=\"$2\"\n\tlocal proc_entry=\"/sys/block/$( basename \"$dev\" )/reset\"\n\n\tlogger -s -t zram_reset -p daemon.debug \"$message via $proc_entry\"\n\techo \"1\" >\"$proc_entry\"\n}\n\nzram_getdev()\n{\n\t#get unallocated zram dev\n\tlocal zdev=$( zram_dev )\n\n\tif [ \"$(mount | grep $zdev)\" ]; then\n\t\tlocal idx=$(cat /sys/class/zram-control/hot_add)\n\t\tzdev=\"$( zram_dev $idx )\"\n\tfi\n\n\techo $zdev\n}\n\nzram_comp_algo()\n{\n\tlocal dev=\"$1\"\n\tlocal zram_comp_algo=\"$( uci -q get system.@system[0].zram_comp_algo )\"\n\n\tif [ -z \"$zram_comp_algo\" ]; then\n\t\t# default to lzo, which is always available\n\t\tzram_comp_algo=\"lzo\"\n\tfi\n\n\tif [ $(grep -c \"$zram_comp_algo\" /sys/block/$( basename $dev )/comp_algorithm) -ne 0 ]; then\n\t\tlogger -s -t zram_comp_algo -p daemon.debug \"set compression algorithm '$zram_comp_algo' for zram '$dev'\"\n\t\techo $zram_comp_algo > \"/sys/block/$( basename $dev )/comp_algorithm\"\n\telse\n\t\tlogger -s -t zram_comp_algo -p daemon.debug \"compression algorithm '$zram_comp_algo' is not supported for '$dev'\"\n\tfi\n}\n\n#print various stats info about zram swap device\nzram_stats()\n{\n\tlocal zdev=\"/sys/block/$( basename \"$1\" )\"\n\n\tprintf \"\\nGathering stats info for zram device \\\"$( basename \"$1\" )\\\"\\n\\n\"\n\n\tprintf \"ZRAM\\n----\\n\"\n\tprintf \"%-25s - %s\\n\" \"Block device\" $zdev\n\tawk '{ printf \"%-25s - %d MiB\\n\", \"Device size\", $1/1024/1024 }' <$zdev/disksize\n\tprintf \"%-25s - %s\\n\" \"Compression algo\" \"$(cat $zdev/comp_algorithm)\"\n\n\tawk 'BEGIN { fmt = \"%-25s - %.2f %s\\n\"\n\t\tfmt2 = \"%-25s - %d\\n\"\n\t\tprint \"\\nDATA\\n----\" }\n\t\t{ printf fmt, \"Original data size\", $1/1024/1024, \"MiB\"\n\t\tprintf fmt, \"Compressed data size\", $2/1024/1024, \"MiB\"\n\t\tprintf fmt, \"Compress ratio\", $1/$2, \"\"\n\t\tprint \"\\nMEMORY\\n------\"\n\t\tprintf fmt, \"Memory used, total\", $3/1024/1024, \"MiB\"\n\t\tprintf fmt, \"Allocator overhead\", ($3-$2)/1024/1024, \"MiB\"\n\t\tprintf fmt, \"Allocator efficiency\", $2/$3*100, \"%\"\n\t\tprintf fmt, \"Maximum memory ever used\", $5/1024/1024, \"MiB\"\n\t\tprintf fmt, \"Memory limit\", $4/1024/1024, \"MiB\"\n\t\tprint \"\\nPAGES\\n-----\"\n\t\tprintf fmt2, \"Same pages count\", $6\n\t\tprintf fmt2, \"Pages compacted\", $7 }' <$zdev/mm_stat\n\n\tawk '{ printf \"%-25s - %d\\n\", \"Free pages discarded\", $4 }' <$zdev/io_stat\n}\n\nzram_compact()\n{\n\t# compact zram device (reduce memory allocation overhead)\n\tlocal zdev=\"/sys/block/$( basename \"$1\" )\"\n\n\tlocal old_mem_used=$(awk '{print $3}' <$zdev/mm_stat)\n\tlocal old_overhead=$(awk '{print $3-$2}' <$zdev/mm_stat)\n\n\techo 1 > $zdev/compact\n\n\t# If not running interactively, than just return\n\t[ -z \"$PS1\" ] && return 0\n\n\techo \"\"\n\techo \"Compacting zram device $zdev\"\n\tawk -v old_mem=\"$old_mem_used\" -v ovr=\"$old_overhead\" 'BEGIN { fmt = \"%-25s - %.1f %s\\n\" }\n\t\t{ printf fmt, \"Memory usage reduced by \", (old_mem-$3)/1024/1024, \"MiB\"\n\t\tprintf fmt, \"Overhead reduced by\", (ovr-($3-$2))/ovr*100, \"%\" }' <$zdev/mm_stat\n}\n\nstart()\n{\n\t[ -e /proc/swaps ] || {\n\t\tlogger -s -t zram_start -p daemon.crit \"kernel doesn't support swap\"\n\t\treturn 1\n\t}\n\n\tif [ $( grep -cs zram /proc/swaps ) -ne 0 ]; then\n\t\tlogger -s -t zram_start -p daemon.notice \"zram swap is already mounted\"\n\t\treturn 1\n\tfi\n\n\tlocal zram_dev=\"$( zram_getdev )\"\n\n\t[ -e \"$zram_dev\" ] || {\n\t\tlogger -s -t zram_start -p daemon.crit \"[ERROR] device '$zram_dev' not found\"\n\t\treturn 1\n\t}\n\n\tlocal zram_size=\"$( zram_getsize )\"\n\tlocal zram_priority=\"$( uci -q get system.@system[0].zram_priority )\"\n\n\tif [ -z \"$zram_priority\" ]; then\n\t\tzram_priority=\"100\"\n\tfi\n\n\tlogger -s -t zram_start -p daemon.debug \"activating '$zram_dev' for swapping ($zram_size MiB)\"\n\n\tzram_reset \"$zram_dev\" \"enforcing defaults\"\n\tzram_comp_algo \"$zram_dev\"\n\techo $(( $zram_size * 1024 * 1024 )) >\"/sys/block/$( basename \"$zram_dev\" )/disksize\"\n\tbusybox mkswap \"$zram_dev\"\n\tbusybox swapon -d -p $zram_priority \"$zram_dev\"\n}\n\nstop()\n{\n\tlocal zram_dev\n\n\tfor zram_dev in $( grep zram /proc/swaps |awk '{print $1}' ); do {\n\t\tlogger -s -t zram_stop -p daemon.debug \"deactivate swap $zram_dev\"\n\t\tbusybox swapoff \"$zram_dev\" && zram_reset \"$zram_dev\" \"claiming memory back\"\n\t\tlocal dev_index=\"$( echo $zram_dev | grep -o \"[0-9]*$\" )\"\n\t\tif [ $dev_index -ne 0 ]; then\n\t\t\tlogger -s -t zram_stop -p daemon.debug \"removing zram $zram_dev\"\n\t\t\techo $dev_index > /sys/class/zram-control/hot_remove\n\t\tfi\n\t} done\n}\n\n# show memory stats for all zram swaps\nstatus()\n{\n\tfor zram_dev in $( grep zram /proc/swaps |awk '{print $1}' ); do {\n\t\tzram_stats \"$zram_dev\"\n\t} done\n}\n\n# trigger compaction for all zram swaps\ncompact()\n{\n\tfor zram_dev in $( grep zram /proc/swaps |awk '{print $1}' ); do {\n\t\tzram_compact \"$zram_dev\"\n\t} done\n}\n"
  },
  {
    "path": "package/utils/adb/Makefile",
    "content": "include $(TOPDIR)/rules.mk\n#Based on adb package from AUR https://aur.archlinux.org/packages/adb/ , reused Makefile\n\nPKG_NAME:=adb\nPKG_VERSION:=android.5.0.2_r1\nPKG_RELEASE:=3\n\nPKG_SOURCE_PROTO:=git\nPKG_SOURCE_URL:=https://android.googlesource.com/platform/system/core\nPKG_SOURCE_VERSION:=6fe92d1a3fb17545d82d020a3c995f32e6b71f9d\nPKG_MIRROR_HASH:=a9b4b86602dfc0d4fc9e1d0f78dc83e648a931fb04f5a4be9b1f0054a8cebf7e\nPKG_SOURCE_SUBDIR:=$(PKG_NAME)-$(PKG_SOURCE_VERSION)\nPKG_SOURCE:=$(PKG_SOURCE_SUBDIR).tar.xz\nPKG_BUILD_DIR:=$(BUILD_DIR)/$(PKG_SOURCE_SUBDIR)\nPKG_MAINTAINER:=Henryk Heisig <hyniu@o2.pl>\n\ninclude $(INCLUDE_DIR)/package.mk\n\nifeq ($(CONFIG_BIG_ENDIAN),y)\nTARGET_CFLAGS+= -DHAVE_BIG_ENDIAN=1\nendif\nTARGET_CFLAGS+= -D_GNU_SOURCE\n\ndefine Package/adb\n  SECTION:=utils\n  CATEGORY:=Utilities\n  TITLE:=Android Debug Bridge CLI tool\n  URL:=http://tools.android.com/\n  DEPENDS:=+zlib +libopenssl +libpthread\nendef\n\ndefine Package/adb/description\n Android Debug Bridge (adb) is a versatile command line tool that lets you communicate with an emulator instance or connected Android-powered device.\nendef\n\n# Nothing just to be sure\n#define Build/Configure\n#endef\n\ndefine Build/Compile\n\t$(MAKE) -C $(PKG_BUILD_DIR)/adb/ \\\n\t\t$(TARGET_CONFIGURE_OPTS) \\\n\t\tTARGET=Linux \\\n\t\tCFLAGS=\"$(TARGET_CFLAGS) $(TARGET_CPPFLAGS)\" \\\n\t\tLDFLAGS=\"$(TARGET_LDFLAGS)\"\nendef\n\ndefine Package/adb/install\n\t$(INSTALL_DIR) $(1)/usr/bin\n\t$(INSTALL_BIN) $(PKG_BUILD_DIR)/adb/adb $(1)/usr/bin/\nendef\n\n$(eval $(call BuildPackage,adb))\n"
  },
  {
    "path": "package/utils/adb/patches/001-create_Makefile.patch",
    "content": "--- /dev/null\n+++ b/adb/Makefile\n@@ -0,0 +1,42 @@\n+SRCS+= adb.c\n+SRCS+= adb_auth_host.c\n+SRCS+= adb_client.c\n+SRCS+= commandline.c\n+SRCS+= console.c\n+SRCS+= fdevent.c\n+SRCS+= file_sync_client.c\n+SRCS+= get_my_path_linux.c\n+SRCS+= services.c\n+SRCS+= sockets.c\n+SRCS+= transport.c\n+SRCS+= transport_local.c\n+SRCS+= transport_usb.c\n+SRCS+= usb_linux.c\n+\n+VPATH+= ../libcutils\n+SRCS+= load_file.c\n+SRCS+= socket_inaddr_any_server.c\n+SRCS+= socket_local_client.c\n+SRCS+= socket_local_server.c\n+SRCS+= socket_loopback_client.c\n+SRCS+= socket_loopback_server.c\n+SRCS+= socket_network_client.c\n+\n+VPATH+= ../libzipfile\n+SRCS+= centraldir.c\n+SRCS+= zipfile.c\n+\n+CPPFLAGS+= -DADB_HOST=1\n+CPPFLAGS+= -DHAVE_FORKEXEC=1\n+CPPFLAGS+= -I.\n+CPPFLAGS+= -I../include\n+CPPFLAGS+= -D_FILE_OFFSET_BITS=64\n+\n+LIBS+= -lcrypto -lpthread -lz\n+\n+OBJS= $(SRCS:.c=.o)\n+\n+all: adb\n+\n+adb: $(OBJS)\n+\t$(CC) -o $@ $(LDFLAGS) $(OBJS) $(LIBS)\n"
  },
  {
    "path": "package/utils/adb/patches/003-fix-musl-build.patch",
    "content": "--- a/adb/usb_linux.c\n+++ b/adb/usb_linux.c\n@@ -21,6 +21,7 @@\n \n #include <sys/ioctl.h>\n #include <sys/types.h>\n+#include <sys/sysmacros.h>\n #include <sys/time.h>\n #include <dirent.h>\n #include <fcntl.h>\n"
  },
  {
    "path": "package/utils/adb/patches/010-openssl-1.1.patch",
    "content": "--- a/adb/adb_auth_host.c\n+++ b/adb/adb_auth_host.c\n@@ -83,7 +83,13 @@ static int RSA_to_RSAPublicKey(RSA *rsa,\n     }\n \n     BN_set_bit(r32, 32);\n+#if OPENSSL_VERSION_NUMBER >= 0x10100000L\n+    const BIGNUM *rsa_n, *rsa_e;\n+    RSA_get0_key(rsa, &rsa_n, &rsa_e, NULL);\n+    BN_copy(n, rsa_n);\n+#else\n     BN_copy(n, rsa->n);\n+#endif\n     BN_set_bit(r, RSANUMWORDS * 32);\n     BN_mod_sqr(rr, r, n, ctx);\n     BN_div(NULL, rem, n, r32, ctx);\n@@ -97,7 +103,11 @@ static int RSA_to_RSAPublicKey(RSA *rsa,\n         BN_div(n, rem, n, r32, ctx);\n         pkey->n[i] = BN_get_word(rem);\n     }\n+#if OPENSSL_VERSION_NUMBER >= 0x10100000L\n+    pkey->exponent = BN_get_word(rsa_e);\n+#else\n     pkey->exponent = BN_get_word(rsa->e);\n+#endif\n \n out:\n     BN_free(n0inv);\n"
  },
  {
    "path": "package/utils/adb/patches/020-cherry-picked-superspeed-fix.patch",
    "content": "From 58b01e01875e2f6ae593ded197430bc23713dd0a Mon Sep 17 00:00:00 2001\nFrom: Ingo Rohloff <lundril@gmx.de>\nDate: Fri, 16 May 2014 21:51:41 +0200\nSubject: [PATCH] ADB on linux: Handle USB SuperSpeed extra Descriptors\n\nUnder Linux, ADB manually parses USB Descriptors to check for\npossible ADB USB Interfaces. USB Devices connected with SuperSpeed\nwill exhibit extra USB SuperSpeed Endpoint Companion Descriptors.\nThis patch handles these USB SuperSpeed specific USB Descriptors.\n\nChange-Id: Icd1e5fdde0b324c7df4f933583499f2c52a922f3\nSigned-off-by: Ingo Rohloff <lundril@gmx.de>\n---\n adb/usb_linux.c | 12 ++++++++++++\n 1 file changed, 12 insertions(+)\n\n--- a/adb/usb_linux.c\n+++ b/adb/usb_linux.c\n@@ -238,8 +238,20 @@ static void find_usb_device(const char *\n                             // looks like ADB...\n                         ep1 = (struct usb_endpoint_descriptor *)bufptr;\n                         bufptr += USB_DT_ENDPOINT_SIZE;\n+                            // For USB 3.0 SuperSpeed devices, skip potential\n+                            // USB 3.0 SuperSpeed Endpoint Companion descriptor\n+                        if (bufptr+2 <= devdesc + desclength &&\n+                            bufptr[0] == USB_DT_SS_EP_COMP_SIZE &&\n+                            bufptr[1] == USB_DT_SS_ENDPOINT_COMP) {\n+                            bufptr += USB_DT_SS_EP_COMP_SIZE;\n+                        }\n                         ep2 = (struct usb_endpoint_descriptor *)bufptr;\n                         bufptr += USB_DT_ENDPOINT_SIZE;\n+                        if (bufptr+2 <= devdesc + desclength &&\n+                            bufptr[0] == USB_DT_SS_EP_COMP_SIZE &&\n+                            bufptr[1] == USB_DT_SS_ENDPOINT_COMP) {\n+                            bufptr += USB_DT_SS_EP_COMP_SIZE;\n+                        }\n \n                         if (bufptr > devdesc + desclength ||\n                             ep1->bLength != USB_DT_ENDPOINT_SIZE ||\n"
  },
  {
    "path": "package/utils/bcm27xx-userland/Makefile",
    "content": "#\n# Copyright (C) 2019-2020 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=bcm27xx-userland\nPKG_VERSION:=97bc8180ad682b004ea224d1db7b8e108eda4397\nPKG_RELEASE:=1\n\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz\nPKG_SOURCE_URL:=https://codeload.github.com/raspberrypi/userland/tar.gz/$(PKG_VERSION)?\nPKG_HASH:=d67def03931215f41b741aed5a3a1bc2bd62fa33f5cc14692e9a4d65f2e0ea27\n\nPKG_FLAGS:=nonshared\n\nPKG_MAINTAINER:=Álvaro Fernández Rojas <noltari@gmail.com>\nPKG_LICENSE:=BSD-3-Clause\nPKG_LICENSE_FILES:=LICENCE\n\nCMAKE_INSTALL:=1\nCMAKE_OPTIONS+=-DVMCS_INSTALL_PREFIX=/usr\n\nifeq ($(ARCH),aarch64)\n  CMAKE_OPTIONS+=-DARM64=ON\nelse\n  CMAKE_OPTIONS+=-DARM64=OFF\nendif\n\ninclude $(INCLUDE_DIR)/package.mk\ninclude $(INCLUDE_DIR)/cmake.mk\n\nTAR_OPTIONS:=--strip-components 1 $(TAR_OPTIONS)\nTAR_CMD=$(HOST_TAR) -C $(1) $(TAR_OPTIONS)\n\ndefine Package/bcm27xx-userland\n  SECTION:=utils\n  CATEGORY:=Utilities\n  DEPENDS:=@TARGET_bcm27xx\n  TITLE:=BCM27xx userland tools\n  DEFAULT:=y if TARGET_bcm27xx\nendef\n\ndefine Package/bcm27xx-userland/description\n  BCM27xx userland tools including vcgencmd and tvservice.\nendef\n\ndefine Package/bcm27xx-userland-dev\n  SECTION:=devel\n  CATEGORY:=Development\n  SUBMENU:=Libraries\n  DEPENDS:=@TARGET_bcm27xx +bcm27xx-userland\n  TITLE:=Development files of BCM27xx userland tools\nendef\n\ndefine Package/bcm27xx-userland-dev/description\n  This package contains the header and static libraries of\n  the BCM27xx userland tools.\nendef\n\ndefine Package/bcm27xx-userland/install\n\t$(INSTALL_DIR) $(1)/usr/bin\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/bin/dtmerge $(1)/usr/bin\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/bin/dtparam $(1)/usr/bin\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/bin/dtoverlay $(1)/usr/bin\nifneq ($(ARCH),aarch64)\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/bin/raspistill $(1)/usr/bin\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/bin/raspivid $(1)/usr/bin\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/bin/raspividyuv $(1)/usr/bin\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/bin/raspiyuv $(1)/usr/bin\nendif\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/bin/tvservice $(1)/usr/bin\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/bin/vcgencmd $(1)/usr/bin\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/bin/vcmailbox $(1)/usr/bin\n\n\t$(INSTALL_DIR) $(1)/usr/lib/\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/*.so $(1)/usr/lib/\nifneq ($(ARCH),aarch64)\n\t$(INSTALL_DIR) $(1)/usr/lib/plugins\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/plugins/ $(1)/usr/lib/\nendif\nendef\n\ndefine Package/bcm27xx-userland-dev/install\n\t$(INSTALL_DIR) $(1)/usr/include\n\t$(CP) $(PKG_INSTALL_DIR)/usr/include/ $(1)/usr/\n\n\t$(INSTALL_DIR) $(1)/usr/lib/pkgconfig\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/pkgconfig $(1)/usr/lib/\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/*.a $(1)/usr/lib/\nendef\n\n$(eval $(call BuildPackage,bcm27xx-userland))\n$(eval $(call BuildPackage,bcm27xx-userland-dev))\n"
  },
  {
    "path": "package/utils/bcm4908img/Makefile",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=bcm4908img\nPKG_RELEASE:=3\n\nPKG_FLAGS:=nonshared\n\nPKG_BUILD_DEPENDS := bcm4908img/host\n\ninclude $(INCLUDE_DIR)/package.mk\ninclude $(INCLUDE_DIR)/host-build.mk\n\ndefine Package/bcm4908img\n  SECTION:=utils\n  CATEGORY:=Base system\n  TITLE:=Utility handling BCM4908 images\n  MAINTAINER:=Rafał Miłecki <rafal@milecki.pl>\n  DEPENDS:=@TARGET_bcm4908\nendef\n\ndefine Package/bcm4908img/description\n  CFE bootloader for BCM4908 uses custom image format. It consists of:\n  1. Optional cferom image\n  2. bootfs JFFS2 partition (cferam, kernel, DTB and optional helper files)\n  3. padding\n  4. rootfs simply appended to the bootfs + padding\n  5. tail with checksum and basic device info\n\n  This util allows creating, modifying and extracting from BCM4908 images.\nendef\n\ndefine Host/Prepare\n  $(CP) ./src/* $(HOST_BUILD_DIR)\nendef\n\ndefine Build/Compile\n\t$(MAKE) -C $(PKG_BUILD_DIR) \\\n\t\tCC=\"$(TARGET_CC)\" \\\n\t\tCFLAGS=\"$(TARGET_CFLAGS) -Wall\"\nendef\n\ndefine Package/bcm4908img/install\n\t$(INSTALL_DIR) $(1)/usr/bin\n\t$(INSTALL_BIN) $(PKG_BUILD_DIR)/bcm4908img $(1)/usr/bin/\nendef\n\ndefine Host/Install\n\t$(INSTALL_BIN) $(HOST_BUILD_DIR)/bcm4908img $(STAGING_DIR_HOST)/bin/\nendef\n\n$(eval $(call BuildPackage,bcm4908img))\n$(eval $(call HostBuild))\n"
  },
  {
    "path": "package/utils/bcm4908img/src/Makefile",
    "content": "all: bcm4908img\n\nbcm4908img:\n\t$(CC) $(CFLAGS) -o $@ bcm4908img.c -Wall\n\nclean:\n\trm -f bcm4908img\n"
  },
  {
    "path": "package/utils/bcm4908img/src/bcm4908img.c",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later\n/*\n * Copyright (C) 2021 Rafał Miłecki <rafal@milecki.pl>\n */\n\n#include <byteswap.h>\n#include <endian.h>\n#include <errno.h>\n#include <stdbool.h>\n#include <stddef.h>\n#include <stdint.h>\n#include <stdio.h>\n#include <stdlib.h>\n#include <string.h>\n#include <sys/stat.h>\n#include <unistd.h>\n\n#if !defined(__BYTE_ORDER)\n#error \"Unknown byte order\"\n#endif\n\n#if __BYTE_ORDER == __BIG_ENDIAN\n#define cpu_to_le32(x)\tbswap_32(x)\n#define le32_to_cpu(x)\tbswap_32(x)\n#define cpu_to_be32(x)\t(x)\n#define be32_to_cpu(x)\t(x)\n#define cpu_to_le16(x)\tbswap_16(x)\n#define le16_to_cpu(x)\tbswap_16(x)\n#define cpu_to_be16(x)\t(x)\n#define be16_to_cpu(x)\t(x)\n#elif __BYTE_ORDER == __LITTLE_ENDIAN\n#define cpu_to_le32(x)\t(x)\n#define le32_to_cpu(x)\t(x)\n#define cpu_to_be32(x)\tbswap_32(x)\n#define be32_to_cpu(x)\tbswap_32(x)\n#define cpu_to_le16(x)\t(x)\n#define le16_to_cpu(x)\t(x)\n#define cpu_to_be16(x)\tbswap_16(x)\n#define be16_to_cpu(x)\tbswap_16(x)\n#else\n#error \"Unsupported endianness\"\n#endif\n\n#define WFI_VERSION\t\t\t0x00005732\n#define WFI_VERSION_NAND_1MB_DATA\t0x00005731\n\n#define WFI_NOR_FLASH\t\t\t1\n#define WFI_NAND16_FLASH\t\t2\n#define WFI_NAND128_FLASH\t\t3\n#define WFI_NAND256_FLASH\t\t4\n#define WFI_NAND512_FLASH\t\t5\n#define WFI_NAND1024_FLASH\t\t6\n#define WFI_NAND2048_FLASH\t\t7\n\n#define WFI_FLAG_HAS_PMC\t\t0x1\n#define WFI_FLAG_SUPPORTS_BTRM\t\t0x2\n\n#define UBI_EC_HDR_MAGIC\t\t0x55424923\n\nstatic int debug;\n\nstruct bcm4908img_tail {\n\tuint32_t crc32;\n\tuint32_t version;\n\tuint32_t chip_id;\n\tuint32_t flash_type;\n\tuint32_t flags;\n};\n\n/**\n * struct bcm4908img_info - info about BCM4908 image\n *\n * Standard BCM4908 image consists of:\n * 1. (Optional) vedor header\n * 2. (Optional) cferom\n * 3. bootfs  ─┐\n * 4. padding  ├─ firmware\n * 5. rootfs  ─┘\n * 6. BCM4908 tail\n * 7. (Optional) vendor tail\n */\nstruct bcm4908img_info {\n\tsize_t cferom_offset;\n\tsize_t bootfs_offset;\n\tsize_t padding_offset;\n\tsize_t rootfs_offset;\n\tsize_t tail_offset;\n\tuint32_t crc32;\t\t\t/* Calculated checksum */\n\tstruct bcm4908img_tail tail;\n};\n\nchar *pathname;\n\nstatic inline size_t bcm4908img_min(size_t x, size_t y) {\n\treturn x < y ? x : y;\n}\n\n/**************************************************\n * CRC32\n **************************************************/\n\nstatic const uint32_t crc32_tbl[] = {\n\t0x00000000, 0x77073096, 0xee0e612c, 0x990951ba,\n\t0x076dc419, 0x706af48f, 0xe963a535, 0x9e6495a3,\n\t0x0edb8832, 0x79dcb8a4, 0xe0d5e91e, 0x97d2d988,\n\t0x09b64c2b, 0x7eb17cbd, 0xe7b82d07, 0x90bf1d91,\n\t0x1db71064, 0x6ab020f2, 0xf3b97148, 0x84be41de,\n\t0x1adad47d, 0x6ddde4eb, 0xf4d4b551, 0x83d385c7,\n\t0x136c9856, 0x646ba8c0, 0xfd62f97a, 0x8a65c9ec,\n\t0x14015c4f, 0x63066cd9, 0xfa0f3d63, 0x8d080df5,\n\t0x3b6e20c8, 0x4c69105e, 0xd56041e4, 0xa2677172,\n\t0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b,\n\t0x35b5a8fa, 0x42b2986c, 0xdbbbc9d6, 0xacbcf940,\n\t0x32d86ce3, 0x45df5c75, 0xdcd60dcf, 0xabd13d59,\n\t0x26d930ac, 0x51de003a, 0xc8d75180, 0xbfd06116,\n\t0x21b4f4b5, 0x56b3c423, 0xcfba9599, 0xb8bda50f,\n\t0x2802b89e, 0x5f058808, 0xc60cd9b2, 0xb10be924,\n\t0x2f6f7c87, 0x58684c11, 0xc1611dab, 0xb6662d3d,\n\t0x76dc4190, 0x01db7106, 0x98d220bc, 0xefd5102a,\n\t0x71b18589, 0x06b6b51f, 0x9fbfe4a5, 0xe8b8d433,\n\t0x7807c9a2, 0x0f00f934, 0x9609a88e, 0xe10e9818,\n\t0x7f6a0dbb, 0x086d3d2d, 0x91646c97, 0xe6635c01,\n\t0x6b6b51f4, 0x1c6c6162, 0x856530d8, 0xf262004e,\n\t0x6c0695ed, 0x1b01a57b, 0x8208f4c1, 0xf50fc457,\n\t0x65b0d9c6, 0x12b7e950, 0x8bbeb8ea, 0xfcb9887c,\n\t0x62dd1ddf, 0x15da2d49, 0x8cd37cf3, 0xfbd44c65,\n\t0x4db26158, 0x3ab551ce, 0xa3bc0074, 0xd4bb30e2,\n\t0x4adfa541, 0x3dd895d7, 0xa4d1c46d, 0xd3d6f4fb,\n\t0x4369e96a, 0x346ed9fc, 0xad678846, 0xda60b8d0,\n\t0x44042d73, 0x33031de5, 0xaa0a4c5f, 0xdd0d7cc9,\n\t0x5005713c, 0x270241aa, 0xbe0b1010, 0xc90c2086,\n\t0x5768b525, 0x206f85b3, 0xb966d409, 0xce61e49f,\n\t0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4,\n\t0x59b33d17, 0x2eb40d81, 0xb7bd5c3b, 0xc0ba6cad,\n\t0xedb88320, 0x9abfb3b6, 0x03b6e20c, 0x74b1d29a,\n\t0xead54739, 0x9dd277af, 0x04db2615, 0x73dc1683,\n\t0xe3630b12, 0x94643b84, 0x0d6d6a3e, 0x7a6a5aa8,\n\t0xe40ecf0b, 0x9309ff9d, 0x0a00ae27, 0x7d079eb1,\n\t0xf00f9344, 0x8708a3d2, 0x1e01f268, 0x6906c2fe,\n\t0xf762575d, 0x806567cb, 0x196c3671, 0x6e6b06e7,\n\t0xfed41b76, 0x89d32be0, 0x10da7a5a, 0x67dd4acc,\n\t0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5,\n\t0xd6d6a3e8, 0xa1d1937e, 0x38d8c2c4, 0x4fdff252,\n\t0xd1bb67f1, 0xa6bc5767, 0x3fb506dd, 0x48b2364b,\n\t0xd80d2bda, 0xaf0a1b4c, 0x36034af6, 0x41047a60,\n\t0xdf60efc3, 0xa867df55, 0x316e8eef, 0x4669be79,\n\t0xcb61b38c, 0xbc66831a, 0x256fd2a0, 0x5268e236,\n\t0xcc0c7795, 0xbb0b4703, 0x220216b9, 0x5505262f,\n\t0xc5ba3bbe, 0xb2bd0b28, 0x2bb45a92, 0x5cb36a04,\n\t0xc2d7ffa7, 0xb5d0cf31, 0x2cd99e8b, 0x5bdeae1d,\n\t0x9b64c2b0, 0xec63f226, 0x756aa39c, 0x026d930a,\n\t0x9c0906a9, 0xeb0e363f, 0x72076785, 0x05005713,\n\t0x95bf4a82, 0xe2b87a14, 0x7bb12bae, 0x0cb61b38,\n\t0x92d28e9b, 0xe5d5be0d, 0x7cdcefb7, 0x0bdbdf21,\n\t0x86d3d2d4, 0xf1d4e242, 0x68ddb3f8, 0x1fda836e,\n\t0x81be16cd, 0xf6b9265b, 0x6fb077e1, 0x18b74777,\n\t0x88085ae6, 0xff0f6a70, 0x66063bca, 0x11010b5c,\n\t0x8f659eff, 0xf862ae69, 0x616bffd3, 0x166ccf45,\n\t0xa00ae278, 0xd70dd2ee, 0x4e048354, 0x3903b3c2,\n\t0xa7672661, 0xd06016f7, 0x4969474d, 0x3e6e77db,\n\t0xaed16a4a, 0xd9d65adc, 0x40df0b66, 0x37d83bf0,\n\t0xa9bcae53, 0xdebb9ec5, 0x47b2cf7f, 0x30b5ffe9,\n\t0xbdbdf21c, 0xcabac28a, 0x53b39330, 0x24b4a3a6,\n\t0xbad03605, 0xcdd70693, 0x54de5729, 0x23d967bf,\n\t0xb3667a2e, 0xc4614ab8, 0x5d681b02, 0x2a6f2b94,\n\t0xb40bbe37, 0xc30c8ea1, 0x5a05df1b, 0x2d02ef8d,\n};\n\nuint32_t bcm4908img_crc32(uint32_t crc, const void *buf, size_t len) {\n\tconst uint8_t *in = buf;\n\n\twhile (len) {\n\t\tcrc = crc32_tbl[(crc ^ *in) & 0xff] ^ (crc >> 8);\n\t\tin++;\n\t\tlen--;\n\t}\n\n\treturn crc;\n}\n\n/**************************************************\n * Helpers\n **************************************************/\n\nstatic FILE *bcm4908img_open(const char *pathname, const char *mode) {\n\tstruct stat st;\n\n\tif (pathname)\n\t\treturn fopen(pathname, mode);\n\n\tif (isatty(fileno(stdin))) {\n\t\tfprintf(stderr, \"Reading from TTY stdin is unsupported\\n\");\n\t\treturn NULL;\n\t}\n\n\tif (fstat(fileno(stdin), &st)) {\n\t\tfprintf(stderr, \"Failed to fstat stdin: %d\\n\", -errno);\n\t\treturn NULL;\n\t}\n\n\tif (S_ISFIFO(st.st_mode)) {\n\t\tfprintf(stderr, \"Reading from pipe stdin is unsupported\\n\");\n\t\treturn NULL;\n\t}\n\n\treturn stdin;\n}\n\nstatic void bcm4908img_close(FILE *fp) {\n\tif (fp != stdin)\n\t\tfclose(fp);\n}\n\nstatic int bcm4908img_calc_crc32(FILE *fp, struct bcm4908img_info *info) {\n\tuint8_t buf[1024];\n\tsize_t length;\n\tsize_t bytes;\n\n\t/* Start with cferom (or bootfs) - skip vendor header */\n\tfseek(fp, info->cferom_offset, SEEK_SET);\n\n\tinfo->crc32 = 0xffffffff;\n\tlength = info->tail_offset - info->cferom_offset;\n\twhile (length && (bytes = fread(buf, 1, bcm4908img_min(sizeof(buf), length), fp)) > 0) {\n\t\tinfo->crc32 = bcm4908img_crc32(info->crc32, buf, bytes);\n\t\tlength -= bytes;\n\t}\n\tif (length) {\n\t\tfprintf(stderr, \"Failed to read last %zd B of data\\n\", length);\n\t\treturn -EIO;\n\t}\n\n\treturn 0;\n}\n\n/**************************************************\n * Existing firmware parser\n **************************************************/\n\nstruct chk_header {\n\tuint32_t magic;\n\tuint32_t header_len;\n\tuint8_t  reserved[8];\n\tuint32_t kernel_chksum;\n\tuint32_t rootfs_chksum;\n\tuint32_t kernel_len;\n\tuint32_t rootfs_len;\n\tuint32_t image_chksum;\n\tuint32_t header_chksum;\n\tchar board_id[0];\n};\n\nstruct linksys_tail {\n\tchar magic[9];\n\tuint8_t version[8];\n\tchar model[15];\n\tuint32_t crc32;\n\tuint8_t padding[9];\n\tuint8_t signature[16];\n\tuint8_t reserved[192];\n};\n\nstatic bool bcm4908img_is_all_ff(const void *buf, size_t length)\n{\n\tconst uint8_t *in = buf;\n\tint i;\n\n\tfor (i = 0; i < length; i++) {\n\t\tif (in[i] != 0xff)\n\t\t\treturn false;\n\t}\n\n\treturn true;\n}\n\nstatic int bcm4908img_parse(FILE *fp, struct bcm4908img_info *info) {\n\tstruct bcm4908img_tail *tail = &info->tail;\n\tstruct linksys_tail *linksys;\n\tstruct chk_header *chk;\n\tstruct stat st;\n\tuint8_t buf[1024];\n\tsize_t file_size;\n\tuint16_t tmp16;\n\tsize_t length;\n\tsize_t bytes;\n\tint err = 0;\n\n\tmemset(info, 0, sizeof(*info));\n\n\t/* File size */\n\n\tif (fstat(fileno(fp), &st)) {\n\t\terr = -errno;\n\t\tfprintf(stderr, \"Failed to fstat: %d\\n\", err);\n\t\treturn err;\n\t}\n\tfile_size = st.st_size;\n\n\tinfo->tail_offset = file_size - sizeof(*tail);\n\n\t/* Vendor formats */\n\n\trewind(fp);\n\tif (fread(buf, 1, sizeof(buf), fp) != sizeof(buf)) {\n\t\tfprintf(stderr, \"Failed to read file header\\n\");\n\t\treturn -EIO;\n\t}\n\tchk = (void *)buf;\n\tif (be32_to_cpu(chk->magic) == 0x2a23245e)\n\t\tinfo->cferom_offset = be32_to_cpu(chk->header_len);\n\n\tfseek(fp, -sizeof(buf), SEEK_END);\n\tif (fread(buf, 1, sizeof(buf), fp) != sizeof(buf)) {\n\t\tfprintf(stderr, \"Failed to read file header\\n\");\n\t\treturn -EIO;\n\t}\n\tlinksys = (void *)(buf + sizeof(buf) - sizeof(*linksys));\n\tif (!memcmp(linksys->magic, \".LINKSYS.\", sizeof(linksys->magic))) {\n\t\tinfo->tail_offset -= sizeof(*linksys);\n\t}\n\n\t/* Offsets */\n\n\tfor (info->bootfs_offset = info->cferom_offset;\n\t     info->bootfs_offset < info->tail_offset;\n\t     info->bootfs_offset += 0x20000) {\n\t\tif (fseek(fp, info->bootfs_offset, SEEK_SET)) {\n\t\t\terr = -errno;\n\t\t\tfprintf(stderr, \"Failed to fseek to the 0x%zx\\n\", info->bootfs_offset);\n\t\t\treturn err;\n\t\t}\n\t\tif (fread(&tmp16, 1, sizeof(tmp16), fp) != sizeof(tmp16)) {\n\t\t\tfprintf(stderr, \"Failed to read while looking for JFFS2\\n\");\n\t\t\treturn -EIO;\n\t\t}\n\t\tif (be16_to_cpu(tmp16) == 0x8519)\n\t\t\tbreak;\n\t}\n\tif (info->bootfs_offset >= info->tail_offset) {\n\t\tfprintf(stderr, \"Failed to find bootfs offset\\n\");\n\t\treturn -EPROTO;\n\t}\n\n\tfor (info->rootfs_offset = info->bootfs_offset;\n\t     info->rootfs_offset < info->tail_offset;\n\t     info->rootfs_offset += 0x20000) {\n\t\tuint32_t *magic = (uint32_t *)&buf[0];\n\n\t\tif (fseek(fp, info->rootfs_offset, SEEK_SET)) {\n\t\t\terr = -errno;\n\t\t\tfprintf(stderr, \"Failed to fseek: %d\\n\", err);\n\t\t\treturn err;\n\t\t}\n\n\t\tlength = info->padding_offset ? sizeof(*magic) : 256;\n\t\tbytes = fread(buf, 1, length, fp);\n\t\tif (bytes != length) {\n\t\t\tfprintf(stderr, \"Failed to read %zu bytes\\n\", length);\n\t\t\treturn -EIO;\n\t\t}\n\n\t\tif (!info->padding_offset && bcm4908img_is_all_ff(buf, length))\n\t\t\tinfo->padding_offset = info->rootfs_offset;\n\n\t\tif (be32_to_cpu(*magic) == UBI_EC_HDR_MAGIC)\n\t\t\tbreak;\n\t}\n\tif (info->rootfs_offset >= info->tail_offset) {\n\t\tfprintf(stderr, \"Failed to find rootfs offset\\n\");\n\t\treturn -EPROTO;\n\t}\n\n\t/* CRC32 */\n\n\t/* Start with cferom (or bootfs) - skip vendor header */\n\tfseek(fp, info->cferom_offset, SEEK_SET);\n\n\tinfo->crc32 = 0xffffffff;\n\tlength = info->tail_offset - info->cferom_offset;\n\twhile (length && (bytes = fread(buf, 1, bcm4908img_min(sizeof(buf), length), fp)) > 0) {\n\t\tinfo->crc32 = bcm4908img_crc32(info->crc32, buf, bytes);\n\t\tlength -= bytes;\n\t}\n\tif (length) {\n\t\tfprintf(stderr, \"Failed to read last %zd B of data\\n\", length);\n\t\treturn -EIO;\n\t}\n\n\t/* Tail */\n\n\tif (fread(tail, 1, sizeof(*tail), fp) != sizeof(*tail)) {\n\t\tfprintf(stderr, \"Failed to read BCM4908 image tail\\n\");\n\t\treturn -EIO;\n\t}\n\n\t/* Standard validation */\n\n\tif (info->crc32 != le32_to_cpu(tail->crc32)) {\n\t\tfprintf(stderr, \"Invalid data crc32: 0x%08x instead of 0x%08x\\n\", info->crc32, le32_to_cpu(tail->crc32));\n\t\treturn -EPROTO;\n\t}\n\n\treturn 0;\n}\n\n/**************************************************\n * Info\n **************************************************/\n\nstatic int bcm4908img_info(int argc, char **argv) {\n\tstruct bcm4908img_info info;\n\tconst char *pathname = NULL;\n\tFILE *fp;\n\tint c;\n\tint err = 0;\n\n\twhile ((c = getopt(argc, argv, \"i:\")) != -1) {\n\t\tswitch (c) {\n\t\tcase 'i':\n\t\t\tpathname = optarg;\n\t\t\tbreak;\n\t\t}\n\t}\n\n\tfp = bcm4908img_open(pathname, \"r\");\n\tif (!fp) {\n\t\tfprintf(stderr, \"Failed to open BCM4908 image\\n\");\n\t\terr = -EACCES;\n\t\tgoto out;\n\t}\n\n\terr = bcm4908img_parse(fp, &info);\n\tif (err) {\n\t\tfprintf(stderr, \"Failed to parse BCM4908 image\\n\");\n\t\tgoto err_close;\n\t}\n\n\tif (info.bootfs_offset != info.cferom_offset)\n\t\tprintf(\"cferom offset:\\t%zu\\n\", info.cferom_offset);\n\tprintf(\"bootfs offset:\\t0x%zx\\n\", info.bootfs_offset);\n\tif (info.padding_offset)\n\t\tprintf(\"padding offset:\\t0x%zx\\n\", info.padding_offset);\n\tprintf(\"rootfs offset:\\t0x%zx\\n\", info.rootfs_offset);\n\tprintf(\"Checksum:\\t0x%08x\\n\", info.crc32);\n\nerr_close:\n\tbcm4908img_close(fp);\nout:\n\treturn err;\n}\n\n/**************************************************\n * Create\n **************************************************/\n\nstatic ssize_t bcm4908img_create_append_file(FILE *trx, const char *in_path, uint32_t *crc32) {\n\tFILE *in;\n\tsize_t bytes;\n\tssize_t length = 0;\n\tuint8_t buf[1024];\n\n\tin = fopen(in_path, \"r\");\n\tif (!in) {\n\t\tfprintf(stderr, \"Failed to open %s\\n\", in_path);\n\t\treturn -EACCES;\n\t}\n\n\twhile ((bytes = fread(buf, 1, sizeof(buf), in)) > 0) {\n\t\tif (fwrite(buf, 1, bytes, trx) != bytes) {\n\t\t\tfprintf(stderr, \"Failed to write %zu B to %s\\n\", bytes, pathname);\n\t\t\tlength = -EIO;\n\t\t\tbreak;\n\t\t}\n\t\t*crc32 = bcm4908img_crc32(*crc32, buf, bytes);\n\t\tlength += bytes;\n\t}\n\n\tfclose(in);\n\n\treturn length;\n}\n\nstatic ssize_t bcm4908img_create_append_zeros(FILE *trx, size_t length) {\n\tuint8_t *buf;\n\n\tbuf = malloc(length);\n\tif (!buf)\n\t\treturn -ENOMEM;\n\tmemset(buf, 0, length);\n\n\tif (fwrite(buf, 1, length, trx) != length) {\n\t\tfprintf(stderr, \"Failed to write %zu B to %s\\n\", length, pathname);\n\t\tfree(buf);\n\t\treturn -EIO;\n\t}\n\n\tfree(buf);\n\n\treturn length;\n}\n\nstatic ssize_t bcm4908img_create_align(FILE *trx, size_t cur_offset, size_t alignment) {\n\tif (cur_offset & (alignment - 1)) {\n\t\tsize_t length = alignment - (cur_offset % alignment);\n\t\treturn bcm4908img_create_append_zeros(trx, length);\n\t}\n\n\treturn 0;\n}\n\nstatic int bcm4908img_create(int argc, char **argv) {\n\tstruct bcm4908img_tail tail = {\n\t\t.version = cpu_to_le32(WFI_VERSION),\n\t\t.chip_id = cpu_to_le32(0x4908),\n\t\t.flash_type = cpu_to_le32(WFI_NAND128_FLASH),\n\t\t.flags = cpu_to_le32(WFI_FLAG_SUPPORTS_BTRM),\n\t};\n\tuint32_t crc32 = 0xffffffff;\n\tsize_t cur_offset = 0;\n\tssize_t bytes;\n\tFILE *fp;\n\tint c;\n\tint err = 0;\n\n\tif (argc < 3) {\n\t\tfprintf(stderr, \"No BCM4908 image pathname passed\\n\");\n\t\terr = -EINVAL;\n\t\tgoto out;\n\t}\n\tpathname = argv[2];\n\n\tfp = fopen(pathname, \"w+\");\n\tif (!fp) {\n\t\tfprintf(stderr, \"Failed to open %s\\n\", pathname);\n\t\terr = -EACCES;\n\t\tgoto out;\n\t}\n\n\toptind = 3;\n\twhile ((c = getopt(argc, argv, \"f:a:A:\")) != -1) {\n\t\tswitch (c) {\n\t\tcase 'f':\n\t\t\tbytes = bcm4908img_create_append_file(fp, optarg, &crc32);\n\t\t\tif (bytes < 0) {\n\t\t\t\tfprintf(stderr, \"Failed to append file %s\\n\", optarg);\n\t\t\t} else {\n\t\t\t\tcur_offset += bytes;\n\t\t\t}\n\t\t\tbreak;\n\t\tcase 'a':\n\t\t\tbytes = bcm4908img_create_align(fp, cur_offset, strtol(optarg, NULL, 0));\n\t\t\tif (bytes < 0)\n\t\t\t\tfprintf(stderr, \"Failed to append zeros\\n\");\n\t\t\telse\n\t\t\t\tcur_offset += bytes;\n\t\t\tbreak;\n\t\tcase 'A':\n\t\t\tbytes = strtol(optarg, NULL, 0) - cur_offset;\n\t\t\tif (bytes < 0) {\n\t\t\t\tfprintf(stderr, \"Current BCM4908 image length is 0x%zx, can't pad it with zeros to 0x%lx\\n\", cur_offset, strtol(optarg, NULL, 0));\n\t\t\t} else {\n\t\t\t\tbytes = bcm4908img_create_append_zeros(fp, bytes);\n\t\t\t\tif (bytes < 0)\n\t\t\t\t\tfprintf(stderr, \"Failed to append zeros\\n\");\n\t\t\t\telse\n\t\t\t\t\tcur_offset += bytes;\n\t\t\t}\n\t\t\tbreak;\n\t\t}\n\t\tif (err)\n\t\t\tgoto err_close;\n\t}\n\n\ttail.crc32 = cpu_to_le32(crc32);\n\n\tbytes = fwrite(&tail, 1, sizeof(tail), fp);\n\tif (bytes != sizeof(tail)) {\n\t\tfprintf(stderr, \"Failed to write BCM4908 image tail to %s\\n\", pathname);\n\t\treturn -EIO;\n\t}\n\nerr_close:\n\tfclose(fp);\nout:\n\treturn err;\n}\n\n/**************************************************\n * Extract\n **************************************************/\n\nstatic int bcm4908img_extract(int argc, char **argv) {\n\tstruct bcm4908img_info info;\n\tconst char *pathname = NULL;\n\tconst char *type = NULL;\n\tuint8_t buf[1024];\n\tsize_t offset;\n\tsize_t length;\n\tsize_t bytes;\n\tFILE *fp;\n\tint c;\n\tint err = 0;\n\n\twhile ((c = getopt(argc, argv, \"i:t:\")) != -1) {\n\t\tswitch (c) {\n\t\tcase 'i':\n\t\t\tpathname = optarg;\n\t\t\tbreak;\n\t\tcase 't':\n\t\t\ttype = optarg;\n\t\t\tbreak;\n\t\t}\n\t}\n\n\tfp = bcm4908img_open(pathname, \"r\");\n\tif (!fp) {\n\t\tfprintf(stderr, \"Failed to open BCM4908 image\\n\");\n\t\terr = -EACCES;\n\t\tgoto err_out;\n\t}\n\n\terr = bcm4908img_parse(fp, &info);\n\tif (err) {\n\t\tfprintf(stderr, \"Failed to parse BCM4908 image\\n\");\n\t\tgoto err_close;\n\t}\n\n\tif (!type) {\n\t\terr = -EINVAL;\n\t\tfprintf(stderr, \"No data to extract specified\\n\");\n\t\tgoto err_close;\n\t} else if (!strcmp(type, \"cferom\")) {\n\t\toffset = info.cferom_offset;\n\t\tlength = info.bootfs_offset - offset;\n\t\tif (!length) {\n\t\t\terr = -ENOENT;\n\t\t\tfprintf(stderr, \"This BCM4908 image doesn't contain cferom\\n\");\n\t\t\tgoto err_close;\n\t\t}\n\t} else if (!strcmp(type, \"bootfs\")) {\n\t\toffset = info.bootfs_offset;\n\t\tlength = (info.padding_offset ? info.padding_offset : info.rootfs_offset) - offset;\n\t} else if (!strcmp(type, \"rootfs\")) {\n\t\toffset = info.rootfs_offset;\n\t\tlength = info.tail_offset - offset;\n\t} else if (!strcmp(type, \"firmware\")) {\n\t\toffset = info.bootfs_offset;\n\t\tlength = info.tail_offset - offset;\n\t} else {\n\t\terr = -EINVAL;\n\t\tfprintf(stderr, \"Unsupported extract type: %s\\n\", type);\n\t\tgoto err_close;\n\t}\n\n\tif (!length) {\n\t\terr = -EINVAL;\n\t\tfprintf(stderr, \"Failed to find requested data in input image\\n\");\n\t\tgoto err_close;\n\t}\n\n\tfseek(fp, offset, SEEK_SET);\n\twhile (length && (bytes = fread(buf, 1, bcm4908img_min(sizeof(buf), length), fp)) > 0) {\n\t\tfwrite(buf, bytes, 1, stdout);\n\t\tlength -= bytes;\n\t}\n\tif (length) {\n\t\terr = -EIO;\n\t\tfprintf(stderr, \"Failed to read last %zd B of data\\n\", length);\n\t\tgoto err_close;\n\t}\n\nerr_close:\n\tbcm4908img_close(fp);\nerr_out:\n\treturn err;\n}\n\n/**************************************************\n * bootfs\n **************************************************/\n\n#define JFFS2_MAGIC_BITMASK 0x1985\n\n#define JFFS2_COMPR_NONE\t0x00\n#define JFFS2_COMPR_ZERO\t0x01\n#define JFFS2_COMPR_RTIME\t0x02\n#define JFFS2_COMPR_RUBINMIPS\t0x03\n#define JFFS2_COMPR_COPY\t0x04\n#define JFFS2_COMPR_DYNRUBIN\t0x05\n#define JFFS2_COMPR_ZLIB\t0x06\n#define JFFS2_COMPR_LZO\t\t0x07\n/* Compatibility flags. */\n#define JFFS2_COMPAT_MASK 0xc000      /* What do to if an unknown nodetype is found */\n#define JFFS2_NODE_ACCURATE 0x2000\n/* INCOMPAT: Fail to mount the filesystem */\n#define JFFS2_FEATURE_INCOMPAT 0xc000\n/* ROCOMPAT: Mount read-only */\n#define JFFS2_FEATURE_ROCOMPAT 0x8000\n/* RWCOMPAT_COPY: Mount read/write, and copy the node when it's GC'd */\n#define JFFS2_FEATURE_RWCOMPAT_COPY 0x4000\n/* RWCOMPAT_DELETE: Mount read/write, and delete the node when it's GC'd */\n#define JFFS2_FEATURE_RWCOMPAT_DELETE 0x0000\n\n#define JFFS2_NODETYPE_DIRENT (JFFS2_FEATURE_INCOMPAT | JFFS2_NODE_ACCURATE | 1)\n\ntypedef struct {\n\tuint32_t v32;\n} __attribute__((packed)) jint32_t;\n\ntypedef struct {\n\tuint16_t v16;\n} __attribute__((packed)) jint16_t;\n\nstruct jffs2_unknown_node\n{\n\t/* All start like this */\n\tjint16_t magic;\n\tjint16_t nodetype;\n\tjint32_t totlen; /* So we can skip over nodes we don't grok */\n\tjint32_t hdr_crc;\n};\n\nstruct jffs2_raw_dirent\n{\n\tjint16_t magic;\n\tjint16_t nodetype;\t/* == JFFS2_NODETYPE_DIRENT */\n\tjint32_t totlen;\n\tjint32_t hdr_crc;\n\tjint32_t pino;\n\tjint32_t version;\n\tjint32_t ino; /* == zero for unlink */\n\tjint32_t mctime;\n\tuint8_t nsize;\n\tuint8_t type;\n\tuint8_t unused[2];\n\tjint32_t node_crc;\n\tjint32_t name_crc;\n\tuint8_t name[0];\n};\n\n#define je16_to_cpu(x) ((x).v16)\n#define je32_to_cpu(x) ((x).v32)\n\nstatic int bcm4908img_bootfs_ls(FILE *fp, struct bcm4908img_info *info) {\n\tstruct jffs2_unknown_node node;\n\tstruct jffs2_raw_dirent dirent;\n\tsize_t offset;\n\tsize_t bytes;\n\tint err = 0;\n\n\tfor (offset = info->bootfs_offset; ; offset += (je32_to_cpu(node.totlen) + 0x03) & ~0x03) {\n\t\tchar name[FILENAME_MAX + 1];\n\n\t\tif (fseek(fp, offset, SEEK_SET)) {\n\t\t\terr = -errno;\n\t\t\tfprintf(stderr, \"Failed to fseek: %d\\n\", err);\n\t\t\treturn err;\n\t\t}\n\n\t\tbytes = fread(&node, 1, sizeof(node), fp);\n\t\tif (bytes != sizeof(node)) {\n\t\t\tfprintf(stderr, \"Failed to read %zu bytes\\n\", sizeof(node));\n\t\t\treturn -EIO;\n\t\t}\n\n\t\tif (je16_to_cpu(node.magic) != JFFS2_MAGIC_BITMASK) {\n\t\t\tbreak;\n\t\t}\n\n\t\tif (je16_to_cpu(node.nodetype) != JFFS2_NODETYPE_DIRENT) {\n\t\t\tcontinue;\n\t\t}\n\n\t\tmemcpy(&dirent, &node, sizeof(node));\n\t\tbytes += fread((uint8_t *)&dirent + sizeof(node), 1, sizeof(dirent) - sizeof(node), fp);\n\t\tif (bytes != sizeof(dirent)) {\n\t\t\tfprintf(stderr, \"Failed to read %zu bytes\\n\", sizeof(node));\n\t\t\treturn -EIO;\n\t\t}\n\n\t\tif (dirent.nsize + 1 > sizeof(name)) {\n\t\t\t/* Keep reading & printing BUT exit with error code */\n\t\t\tfprintf(stderr, \"Too long filename\\n\");\n\t\t\terr = -ENOMEM;\n\t\t\tcontinue;\n\t\t}\n\n\t\tbytes = fread(name, 1, dirent.nsize, fp);\n\t\tif (bytes != dirent.nsize) {\n\t\t\tfprintf(stderr, \"Failed to read filename\\n\");\n\t\t\treturn -EIO;\n\t\t}\n\t\tname[bytes] = '\\0';\n\n\t\tprintf(\"%s\\n\", name);\n\t}\n\n\treturn err;\n}\n\nstatic int bcm4908img_bootfs_mv(FILE *fp, struct bcm4908img_info *info, int argc, char **argv) {\n\tstruct jffs2_unknown_node node;\n\tstruct jffs2_raw_dirent dirent;\n\tconst char *oldname;\n\tconst char *newname;\n\tsize_t offset;\n\tsize_t bytes;\n\tint err = -ENOENT;\n\n\tif (argc - optind < 2) {\n\t\tfprintf(stderr, \"No enough arguments passed\\n\");\n\t\treturn -EINVAL;\n\t}\n\toldname = argv[optind++];\n\tnewname = argv[optind++];\n\n\tif (strlen(newname) != strlen(oldname)) {\n\t\tfprintf(stderr, \"New filename must have the same length as the old one\\n\");\n\t\treturn -EINVAL;\n\t}\n\n\tfor (offset = info->bootfs_offset; ; offset += (je32_to_cpu(node.totlen) + 0x03) & ~0x03) {\n\t\tchar name[FILENAME_MAX];\n\t\tuint32_t crc32;\n\n\t\tif (fseek(fp, offset, SEEK_SET)) {\n\t\t\terr = -errno;\n\t\t\tfprintf(stderr, \"Failed to fseek: %d\\n\", err);\n\t\t\treturn err;\n\t\t}\n\n\t\tbytes = fread(&node, 1, sizeof(node), fp);\n\t\tif (bytes != sizeof(node)) {\n\t\t\tfprintf(stderr, \"Failed to read %zu bytes\\n\", sizeof(node));\n\t\t\treturn -EIO;\n\t\t}\n\n\t\tif (je16_to_cpu(node.magic) != JFFS2_MAGIC_BITMASK) {\n\t\t\tbreak;\n\t\t}\n\n\t\tif (je16_to_cpu(node.nodetype) != JFFS2_NODETYPE_DIRENT) {\n\t\t\tcontinue;\n\t\t}\n\n\t\tbytes += fread((uint8_t *)&dirent + sizeof(node), 1, sizeof(dirent) - sizeof(node), fp);\n\t\tif (bytes != sizeof(dirent)) {\n\t\t\tfprintf(stderr, \"Failed to read %zu bytes\\n\", sizeof(node));\n\t\t\treturn -EIO;\n\t\t}\n\n\t\tif (dirent.nsize + 1 > sizeof(name)) {\n\t\t\tfprintf(stderr, \"Too long filename\\n\");\n\t\t\terr = -ENOMEM;\n\t\t\tcontinue;\n\t\t}\n\n\t\tbytes = fread(name, 1, dirent.nsize, fp);\n\t\tif (bytes != dirent.nsize) {\n\t\t\tfprintf(stderr, \"Failed to read filename\\n\");\n\t\t\treturn -EIO;\n\t\t}\n\t\tname[bytes] = '\\0';\n\n\t\tif (debug)\n\t\t\tprintf(\"offset:%08zx name_crc:%04x filename:%s\\n\", offset, je32_to_cpu(dirent.name_crc), name);\n\n\t\tif (strcmp(name, oldname)) {\n\t\t\tcontinue;\n\t\t}\n\n\t\tif (fseek(fp, offset + offsetof(struct jffs2_raw_dirent, name_crc), SEEK_SET)) {\n\t\t\terr = -errno;\n\t\t\tfprintf(stderr, \"Failed to fseek: %d\\n\", err);\n\t\t\treturn err;\n\t\t}\n\t\tcrc32 = bcm4908img_crc32(0, newname, dirent.nsize);\n\t\tbytes = fwrite(&crc32, 1, sizeof(crc32), fp);\n\t\tif (bytes != sizeof(crc32)) {\n\t\t\tfprintf(stderr, \"Failed to write new CRC32\\n\");\n\t\t\treturn -EIO;\n\t\t}\n\n\t\tif (fseek(fp, offset + offsetof(struct jffs2_raw_dirent, name), SEEK_SET)) {\n\t\t\terr = -errno;\n\t\t\tfprintf(stderr, \"Failed to fseek: %d\\n\", err);\n\t\t\treturn err;\n\t\t}\n\t\tbytes = fwrite(newname, 1, dirent.nsize, fp);\n\t\tif (bytes != dirent.nsize) {\n\t\t\tfprintf(stderr, \"Failed to write new filename\\n\");\n\t\t\treturn -EIO;\n\t\t}\n\n\t\t/* Calculate new BCM4908 image checksum */\n\n\t\terr = bcm4908img_calc_crc32(fp, info);\n\t\tif (err) {\n\t\t\tfprintf(stderr, \"Failed to write new filename\\n\");\n\t\t\treturn err;\n\t\t}\n\n\t\tinfo->tail.crc32 = cpu_to_le32(info->crc32);\n\t\tif (fseek(fp, -sizeof(struct bcm4908img_tail), SEEK_END)) {\n\t\t\terr = -errno;\n\t\t\tfprintf(stderr, \"Failed to write new filename\\n\");\n\t\t\treturn err;\n\t\t}\n\n\t\tif (fwrite(&info->tail, 1, sizeof(struct bcm4908img_tail), fp) != sizeof(struct bcm4908img_tail)) {\n\t\t\tfprintf(stderr, \"Failed to write updated tail\\n\");\n\t\t\treturn -EIO;\n\t\t}\n\n\t\tprintf(\"Successfully renamed %s to the %s\\n\", oldname, newname);\n\n\t\treturn 0;\n\t}\n\n\tfprintf(stderr, \"Failed to find %s\\n\", oldname);\n\n\treturn -ENOENT;\n}\n\nstatic int bcm4908img_bootfs(int argc, char **argv) {\n\tstruct bcm4908img_info info;\n\tconst char *pathname = NULL;\n\tconst char *mode;\n\tconst char *cmd;\n\tFILE *fp;\n\tint c;\n\tint err = 0;\n\n\twhile ((c = getopt(argc, argv, \"i:\")) != -1) {\n\t\tswitch (c) {\n\t\tcase 'i':\n\t\t\tpathname = optarg;\n\t\t\tbreak;\n\t\t}\n\t}\n\n\tif (argc - optind < 1) {\n\t\tfprintf(stderr, \"No bootfs command specified\\n\");\n\t\terr = -EINVAL;\n\t\tgoto out;\n\t}\n\tcmd = argv[optind++];\n\n\tmode = strcmp(cmd, \"mv\") ? \"r\" : \"r+\";\n\tfp = bcm4908img_open(pathname, mode);\n\tif (!fp) {\n\t\tfprintf(stderr, \"Failed to open BCM4908 image\\n\");\n\t\terr = -EACCES;\n\t\tgoto out;\n\t}\n\n\terr = bcm4908img_parse(fp, &info);\n\tif (err) {\n\t\tfprintf(stderr, \"Failed to parse BCM4908 image\\n\");\n\t\tgoto err_close;\n\t}\n\n\tif (!strcmp(cmd, \"ls\")) {\n\t\terr = bcm4908img_bootfs_ls(fp, &info);\n\t} else if (!strcmp(cmd, \"mv\")) {\n\t\terr = bcm4908img_bootfs_mv(fp, &info, argc, argv);\n\t} else {\n\t\terr = -EINVAL;\n\t\tfprintf(stderr, \"Unsupported bootfs command: %s\\n\", cmd);\n\t}\n\nerr_close:\n\tbcm4908img_close(fp);\nout:\n\treturn err;\n}\n\n/**************************************************\n * Start\n **************************************************/\n\nstatic void usage() {\n\tprintf(\"Usage:\\n\");\n\tprintf(\"\\n\");\n\tprintf(\"Info about a BCM4908 image:\\n\");\n\tprintf(\"\\tbcm4908img info <options>\\n\");\n\tprintf(\"\\t-i <file>\\t\\t\\t\\tinput BCM490 image\\n\");\n\tprintf(\"\\n\");\n\tprintf(\"Creating a new BCM4908 image:\\n\");\n\tprintf(\"\\tbcm4908img create <file> [options]\\n\");\n\tprintf(\"\\t-f file\\t\\t\\t\\tadd data from specified file\\n\");\n\tprintf(\"\\t-a alignment\\t\\t\\tpad image with zeros to specified alignment\\n\");\n\tprintf(\"\\t-A offset\\t\\t\\t\\tappend zeros until reaching specified offset\\n\");\n\tprintf(\"\\n\");\n\tprintf(\"Extracting from a BCM4908 image:\\n\");\n\tprintf(\"\\tbcm4908img extract <options>\\n\");\n\tprintf(\"\\t-i <file>\\t\\t\\t\\tinput BCM490 image\\n\");\n\tprintf(\"\\t-t <type>\\t\\t\\t\\tone of: cferom, bootfs, rootfs, firmware\\n\");\n\tprintf(\"\\n\");\n\tprintf(\"Access bootfs in a BCM4908 image:\\n\");\n\tprintf(\"\\tbcm4908img bootfs <options> <command> <arguments>\\n\");\n\tprintf(\"\\t-i <file>\\t\\t\\t\\tinput BCM490 image\\n\");\n\tprintf(\"\\tls\\t\\t\\t\\t\\tlist bootfs files\\n\");\n\tprintf(\"\\tmv <source> <dest>\\t\\t\\trename bootfs file\\n\");\n}\n\nint main(int argc, char **argv) {\n\tif (argc > 1) {\n\t\toptind++;\n\t\tif (!strcmp(argv[1], \"info\"))\n\t\t\treturn bcm4908img_info(argc, argv);\n\t\telse if (!strcmp(argv[1], \"create\"))\n\t\t\treturn bcm4908img_create(argc, argv);\n\t\telse if (!strcmp(argv[1], \"extract\"))\n\t\t\treturn bcm4908img_extract(argc, argv);\n\t\telse if (!strcmp(argv[1], \"bootfs\"))\n\t\t\treturn bcm4908img_bootfs(argc, argv);\n\t}\n\n\tusage();\n\treturn 0;\n}\n"
  },
  {
    "path": "package/utils/bsdiff/Makefile",
    "content": "#\n# Copyright (C) 2016 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=bsdiff\nPKG_VERSION:=4.3\nPKG_RELEASE:=1\n\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz\nPKG_SOURCE_URL:=http://www.daemonology.net/bsdiff/\nPKG_HASH:=18821588b2dc5bf159aa37d3bcb7b885d85ffd1e19f23a0c57a58723fea85f48\nPKG_MAINTAINER:=Hauke Mehrtens <hauke@hauke-m.de>\nHOST_BUILD_DEPENDS:=bzip2/host\n\nPKG_LICENSE:=BSD-2-Clause\n\ninclude $(INCLUDE_DIR)/host-build.mk\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine Package/bsdiff\n  SECTION:=utils\n  CATEGORY:=Utilities\n  DEPENDS:=+libbz2\n  TITLE:=Binary diff tool\n  URL:=http://www.daemonology.net/bsdiff/\nendef\n\ndefine Package/bspatch\n  SECTION:=utils\n  CATEGORY:=Utilities\n  DEPENDS:=+libbz2\n  TITLE:=Binary patch tool\n  URL:=http://www.daemonology.net/bsdiff/\nendef\n\n\ndefine Build/Compile\n\t$(TARGET_CC) $(TARGET_CFLAGS) $(TARGET_CPPFLAGS) $(TARGET_LDFLAGS) \\\n\t\t-o $(PKG_BUILD_DIR)/bsdiff \\\n\t\t$(PKG_BUILD_DIR)/bsdiff.c -lbz2\n\t$(TARGET_CC) $(TARGET_CFLAGS) $(TARGET_CPPFLAGS) $(TARGET_LDFLAGS) \\\n\t\t-o $(PKG_BUILD_DIR)/bspatch \\\n\t\t$(PKG_BUILD_DIR)/bspatch.c -lbz2\nendef\n\ndefine Package/bsdiff/install\n\t$(INSTALL_DIR) $(1)/usr/bin/\n\t$(INSTALL_BIN) $(PKG_BUILD_DIR)/bsdiff $(1)/usr/bin/bsdiff\nendef\n\ndefine Package/bspatch/install\n\t$(INSTALL_DIR) $(1)/usr/bin/\n\t$(INSTALL_BIN) $(PKG_BUILD_DIR)/bspatch $(1)/usr/bin/bspatch\nendef\n\ndefine Host/Install\n\t$(INSTALL_DIR) $(STAGING_DIR_HOSTPKG)/bin/\n\t$(MAKE) -C $(HOST_BUILD_DIR) PREFIX=$(STAGING_DIR_HOSTPKG)/ install\nendef\n\ndefine Host/Compile\n\t$(HOSTCC) $(HOST_CFLAGS) $(HOST_LDFLAGS) \\\n\t\t-o $(HOST_BUILD_DIR)/bsdiff \\\n\t\t$(HOST_BUILD_DIR)/bsdiff.c -lbz2\nendef\n\ndefine Host/Install\n\t$(INSTALL_BIN) $(HOST_BUILD_DIR)/bsdiff $(STAGING_DIR_HOSTPKG)/bin/\nendef\n\n$(eval $(call HostBuild))\n\n$(eval $(call BuildPackage,bsdiff))\n$(eval $(call BuildPackage,bspatch))\n"
  },
  {
    "path": "package/utils/bsdiff/patches/001-musl.patch",
    "content": "--- a/bsdiff.c\t2005-08-17 00:13:52.000000000 +0200\n+++ b/bsdiff.c\t2016-02-21 01:39:31.157915765 +0100\n@@ -101,7 +101,7 @@\n \tif(start+len>kk) split(I,V,kk,start+len-kk,h);\n }\n \n-static void qsufsort(off_t *I,off_t *V,u_char *old,off_t oldsize)\n+static void qsufsort(off_t *I,off_t *V,unsigned char *old,off_t oldsize)\n {\n \toff_t buckets[256];\n \toff_t i,h,len;\n@@ -139,7 +139,7 @@\n \tfor(i=0;i<oldsize+1;i++) I[V[i]]=i;\n }\n \n-static off_t matchlen(u_char *old,off_t oldsize,u_char *new,off_t newsize)\n+static off_t matchlen(unsigned char *old,off_t oldsize,unsigned char *new,off_t newsize)\n {\n \toff_t i;\n \n@@ -149,8 +149,8 @@\n \treturn i;\n }\n \n-static off_t search(off_t *I,u_char *old,off_t oldsize,\n-\t\tu_char *new,off_t newsize,off_t st,off_t en,off_t *pos)\n+static off_t search(off_t *I,unsigned char *old,off_t oldsize,\n+\t\tunsigned char *new,off_t newsize,off_t st,off_t en,off_t *pos)\n {\n \toff_t x,y;\n \n@@ -175,7 +175,7 @@\n \t};\n }\n \n-static void offtout(off_t x,u_char *buf)\n+static void offtout(off_t x,unsigned char *buf)\n {\n \toff_t y;\n \n@@ -196,7 +196,7 @@\n int main(int argc,char *argv[])\n {\n \tint fd;\n-\tu_char *old,*new;\n+\tunsigned char *old,*new;\n \toff_t oldsize,newsize;\n \toff_t *I,*V;\n \toff_t scan,pos,len;\n@@ -206,9 +206,9 @@\n \toff_t overlap,Ss,lens;\n \toff_t i;\n \toff_t dblen,eblen;\n-\tu_char *db,*eb;\n-\tu_char buf[8];\n-\tu_char header[32];\n+\tunsigned char *db,*eb;\n+\tunsigned char buf[8];\n+\tunsigned char header[32];\n \tFILE * pf;\n \tBZFILE * pfbz2;\n \tint bz2err;\n--- a/bspatch.c\t2005-08-17 00:14:00.000000000 +0200\n+++ b/bspatch.c\t2016-02-21 01:39:29.753859970 +0100\n@@ -36,7 +36,7 @@\n #include <unistd.h>\n #include <fcntl.h>\n \n-static off_t offtin(u_char *buf)\n+static off_t offtin(unsigned char *buf)\n {\n \toff_t y;\n \n@@ -62,8 +62,8 @@\n \tint fd;\n \tssize_t oldsize,newsize;\n \tssize_t bzctrllen,bzdatalen;\n-\tu_char header[32],buf[8];\n-\tu_char *old, *new;\n+\tunsigned char header[32],buf[8];\n+\tunsigned char *old, *new;\n \toff_t oldpos,newpos;\n \toff_t ctrl[3];\n \toff_t lenread;\n"
  },
  {
    "path": "package/utils/busybox/Config-defaults.in",
    "content": "config BUSYBOX_DEFAULT_HAVE_DOT_CONFIG\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_DESKTOP\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_EXTRA_COMPAT\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEDORA_COMPAT\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_INCLUDE_SUSv2\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_LONG_OPTS\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_SHOW_USAGE\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_VERBOSE_USAGE\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_COMPRESS_USAGE\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_LFS\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_PAM\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_DEVPTS\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_UTMP\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_WTMP\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_PIDFILE\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_PID_FILE_PATH\n\tstring\n\tdefault \"/var/run\"\nconfig BUSYBOX_DEFAULT_BUSYBOX\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_SHOW_SCRIPT\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_INSTALLER\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_INSTALL_NO_USR\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_SUID\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_SUID_CONFIG\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_SUID_CONFIG_QUIET\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_PREFER_APPLETS\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_BUSYBOX_EXEC_PATH\n\tstring\n\tdefault \"/proc/self/exe\"\nconfig BUSYBOX_DEFAULT_SELINUX\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_CLEAN_UP\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_SYSLOG_INFO\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_SYSLOG\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_STATIC\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_PIE\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_NOMMU\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_BUILD_LIBBUSYBOX\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_LIBBUSYBOX_STATIC\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_INDIVIDUAL\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_SHARED_BUSYBOX\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_CROSS_COMPILER_PREFIX\n\tstring\n\tdefault \"\"\nconfig BUSYBOX_DEFAULT_SYSROOT\n\tstring\n\tdefault \"\"\nconfig BUSYBOX_DEFAULT_EXTRA_CFLAGS\n\tstring\n\tdefault \"\"\nconfig BUSYBOX_DEFAULT_EXTRA_LDFLAGS\n\tstring\n\tdefault \"\"\nconfig BUSYBOX_DEFAULT_EXTRA_LDLIBS\n\tstring\n\tdefault \"\"\nconfig BUSYBOX_DEFAULT_USE_PORTABLE_CODE\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_STACK_OPTIMIZATION_386\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_STATIC_LIBGCC\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_INSTALL_APPLET_SYMLINKS\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_INSTALL_APPLET_HARDLINKS\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_INSTALL_APPLET_SCRIPT_WRAPPERS\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_INSTALL_APPLET_DONT\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_INSTALL_SH_APPLET_SYMLINK\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_INSTALL_SH_APPLET_HARDLINK\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_INSTALL_SH_APPLET_SCRIPT_WRAPPER\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_PREFIX\n\tstring\n\tdefault \"./_install\"\nconfig BUSYBOX_DEFAULT_DEBUG\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_DEBUG_PESSIMIZE\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_DEBUG_SANITIZE\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_UNIT_TEST\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_WERROR\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_WARN_SIMPLE_MSG\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_NO_DEBUG_LIB\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_DMALLOC\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_EFENCE\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_USE_BSS_TAIL\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FLOAT_DURATION\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_RTMINMAX\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_RTMINMAX_USE_LIBC_DEFINITIONS\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_BUFFERS_USE_MALLOC\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_BUFFERS_GO_ON_STACK\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_BUFFERS_GO_IN_BSS\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_PASSWORD_MINLEN\n\tint\n\tdefault 6\nconfig BUSYBOX_DEFAULT_MD5_SMALL\n\tint\n\tdefault 1\nconfig BUSYBOX_DEFAULT_SHA3_SMALL\n\tint\n\tdefault 1\nconfig BUSYBOX_DEFAULT_FEATURE_NON_POSIX_CP\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_VERBOSE_CP_MESSAGE\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_USE_SENDFILE\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_COPYBUF_KB\n\tint\n\tdefault 4\nconfig BUSYBOX_DEFAULT_MONOTONIC_SYSCALL\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_IOCTL_HEX2STR_ERROR\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_EDITING\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_EDITING_MAX_LEN\n\tint\n\tdefault 512\nconfig BUSYBOX_DEFAULT_FEATURE_EDITING_VI\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_EDITING_HISTORY\n\tint\n\tdefault 256\nconfig BUSYBOX_DEFAULT_FEATURE_EDITING_SAVEHISTORY\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_EDITING_SAVE_ON_EXIT\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_REVERSE_SEARCH\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_TAB_COMPLETION\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_USERNAME_COMPLETION\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_EDITING_FANCY_PROMPT\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_EDITING_WINCH\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_EDITING_ASK_TERMINAL\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_LOCALE_SUPPORT\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_UNICODE_SUPPORT\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_UNICODE_USING_LOCALE\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_CHECK_UNICODE_IN_ENV\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_SUBST_WCHAR\n\tint\n\tdefault 0\nconfig BUSYBOX_DEFAULT_LAST_SUPPORTED_WCHAR\n\tint\n\tdefault 0\nconfig BUSYBOX_DEFAULT_UNICODE_COMBINING_WCHARS\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_UNICODE_WIDE_WCHARS\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_UNICODE_BIDI_SUPPORT\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_UNICODE_NEUTRAL_TABLE\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_UNICODE_PRESERVE_BROKEN\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_SEAMLESS_XZ\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_SEAMLESS_LZMA\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_SEAMLESS_BZ2\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_SEAMLESS_GZ\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_SEAMLESS_Z\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_AR\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_AR_LONG_FILENAMES\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_AR_CREATE\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_UNCOMPRESS\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_GUNZIP\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_ZCAT\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_GUNZIP_LONG_OPTIONS\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_BUNZIP2\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_BZCAT\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_UNLZMA\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_LZCAT\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_LZMA\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_UNXZ\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_XZCAT\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_XZ\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_BZIP2\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_BZIP2_SMALL\n\tint\n\tdefault 0\nconfig BUSYBOX_DEFAULT_FEATURE_BZIP2_DECOMPRESS\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_CPIO\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_CPIO_O\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_CPIO_P\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_CPIO_IGNORE_DEVNO\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_CPIO_RENUMBER_INODES\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_DPKG\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_DPKG_DEB\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_GZIP\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_GZIP_LONG_OPTIONS\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_GZIP_FAST\n\tint\n\tdefault 0\nconfig BUSYBOX_DEFAULT_FEATURE_GZIP_LEVELS\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_GZIP_DECOMPRESS\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_LZOP\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_UNLZOP\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_LZOPCAT\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_LZOP_COMPR_HIGH\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_RPM\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_RPM2CPIO\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_TAR\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_TAR_LONG_OPTIONS\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_TAR_CREATE\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_TAR_AUTODETECT\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_TAR_FROM\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_TAR_OLDGNU_COMPATIBILITY\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_TAR_OLDSUN_COMPATIBILITY\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_TAR_GNU_EXTENSIONS\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_TAR_TO_COMMAND\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_TAR_UNAME_GNAME\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_TAR_NOPRESERVE_TIME\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_TAR_SELINUX\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_UNZIP\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_UNZIP_CDF\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_UNZIP_BZIP2\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_UNZIP_LZMA\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_UNZIP_XZ\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_LZMA_FAST\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_VERBOSE\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_TIMEZONE\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_PRESERVE_HARDLINKS\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_HUMAN_READABLE\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_BASENAME\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_CAT\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_CATN\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_CATV\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_CHGRP\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_CHMOD\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_CHOWN\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_CHOWN_LONG_OPTIONS\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_CHROOT\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_CKSUM\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_CRC32\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_COMM\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_CP\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_CP_LONG_OPTIONS\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_CP_REFLINK\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_CUT\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_CUT_REGEX\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_DATE\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_DATE_ISOFMT\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_DATE_NANO\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_DATE_COMPAT\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_DD\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_DD_SIGNAL_HANDLING\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_DD_THIRD_STATUS_LINE\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_DD_IBS_OBS\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_DD_STATUS\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_DF\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_DF_FANCY\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_SKIP_ROOTFS\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_DIRNAME\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_DOS2UNIX\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_UNIX2DOS\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_DU\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_DU_DEFAULT_BLOCKSIZE_1K\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_ECHO\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_FANCY_ECHO\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_ENV\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_EXPAND\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_UNEXPAND\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_EXPR\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_EXPR_MATH_SUPPORT_64\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FACTOR\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FALSE\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FOLD\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_HEAD\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_FANCY_HEAD\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_HOSTID\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_ID\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_GROUPS\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_INSTALL\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_INSTALL_LONG_OPTIONS\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_LINK\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_LN\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_LOGNAME\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_LS\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_LS_FILETYPES\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_LS_FOLLOWLINKS\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_LS_RECURSIVE\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_LS_WIDTH\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_LS_SORTFILES\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_LS_TIMESTAMPS\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_LS_USERNAME\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_LS_COLOR\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_LS_COLOR_IS_DEFAULT\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_MD5SUM\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_SHA1SUM\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_SHA256SUM\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_SHA512SUM\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_SHA3SUM\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_MD5_SHA1_SUM_CHECK\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_MKDIR\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_MKFIFO\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_MKNOD\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_MKTEMP\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_MV\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_NICE\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_NL\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_NOHUP\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_NPROC\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_OD\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_PASTE\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_PRINTENV\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_PRINTF\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_PWD\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_READLINK\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_READLINK_FOLLOW\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_REALPATH\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_RM\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_RMDIR\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_SEQ\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_SHRED\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_SHUF\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_SLEEP\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_FANCY_SLEEP\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_SORT\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_SORT_BIG\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_SORT_OPTIMIZE_MEMORY\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_SPLIT\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_SPLIT_FANCY\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_STAT\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_STAT_FORMAT\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_STAT_FILESYSTEM\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_STTY\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_SUM\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_SYNC\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_SYNC_FANCY\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FSYNC\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_TAC\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_TAIL\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_FANCY_TAIL\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_TEE\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_TEE_USE_BLOCK_IO\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_TEST\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_TEST1\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_TEST2\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_TEST_64\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_TIMEOUT\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_TOUCH\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_TOUCH_SUSV3\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_TR\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_TR_CLASSES\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_TR_EQUIV\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_TRUE\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_TRUNCATE\n\tbool\n\tdefault y if TARGET_bcm53xx\n\tdefault n\nconfig BUSYBOX_DEFAULT_TTY\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_UNAME\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_UNAME_OSNAME\n\tstring\n\tdefault \"GNU/Linux\"\nconfig BUSYBOX_DEFAULT_BB_ARCH\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_UNIQ\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_UNLINK\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_USLEEP\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_UUDECODE\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_BASE32\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_BASE64\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_UUENCODE\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_WC\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_WC_LARGE\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_WHO\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_W\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_USERS\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_WHOAMI\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_YES\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_CHVT\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_CLEAR\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_DEALLOCVT\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_DUMPKMAP\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FGCONSOLE\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_KBD_MODE\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_LOADFONT\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_SETFONT\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_SETFONT_TEXTUAL_MAP\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_DEFAULT_SETFONT_DIR\n\tstring\n\tdefault \"\"\nconfig BUSYBOX_DEFAULT_FEATURE_LOADFONT_PSF2\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_LOADFONT_RAW\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_LOADKMAP\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_OPENVT\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_RESET\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_RESIZE\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_RESIZE_PRINT\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_SETCONSOLE\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_SETCONSOLE_LONG_OPTIONS\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_SETKEYCODES\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_SETLOGCONS\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_SHOWKEY\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_PIPE_PROGRESS\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_RUN_PARTS\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_RUN_PARTS_LONG_OPTIONS\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_RUN_PARTS_FANCY\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_START_STOP_DAEMON\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_START_STOP_DAEMON_LONG_OPTIONS\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_START_STOP_DAEMON_FANCY\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_WHICH\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_MINIPS\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_NUKE\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_RESUME\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_RUN_INIT\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_AWK\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_AWK_LIBM\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_AWK_GNU_EXTENSIONS\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_CMP\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_DIFF\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_DIFF_LONG_OPTIONS\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_DIFF_DIR\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_ED\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_PATCH\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_SED\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_VI\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_VI_MAX_LEN\n\tint\n\tdefault 1024\nconfig BUSYBOX_DEFAULT_FEATURE_VI_8BIT\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_VI_COLON\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_VI_COLON_EXPAND\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_VI_YANKMARK\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_VI_SEARCH\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_VI_REGEX_SEARCH\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_VI_USE_SIGNALS\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_VI_DOT_CMD\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_VI_READONLY\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_VI_SETOPTS\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_VI_SET\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_VI_WIN_RESIZE\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_VI_ASK_TERMINAL\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_VI_UNDO\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_VI_UNDO_QUEUE\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_VI_UNDO_QUEUE_MAX\n\tint\n\tdefault 0\nconfig BUSYBOX_DEFAULT_FEATURE_VI_VERBOSE_STATUS\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_ALLOW_EXEC\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FIND\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_FIND_PRINT0\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_FIND_MTIME\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_FIND_ATIME\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_FIND_CTIME\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_FIND_MMIN\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_FIND_AMIN\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_FIND_CMIN\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_FIND_PERM\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_FIND_TYPE\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_FIND_EXECUTABLE\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_FIND_XDEV\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_FIND_MAXDEPTH\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_FIND_NEWER\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_FIND_INUM\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_FIND_SAMEFILE\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_FIND_EXEC\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_FIND_EXEC_PLUS\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_FIND_USER\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_FIND_GROUP\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_FIND_NOT\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_FIND_DEPTH\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_FIND_PAREN\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_FIND_SIZE\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_FIND_PRUNE\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_FIND_QUIT\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_FIND_DELETE\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_FIND_EMPTY\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_FIND_PATH\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_FIND_REGEX\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_FIND_CONTEXT\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_FIND_LINKS\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_GREP\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_EGREP\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FGREP\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_GREP_CONTEXT\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_XARGS\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_XARGS_SUPPORT_CONFIRMATION\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_XARGS_SUPPORT_QUOTES\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_XARGS_SUPPORT_TERMOPT\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_XARGS_SUPPORT_ZERO_TERM\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_XARGS_SUPPORT_REPL_STR\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_XARGS_SUPPORT_PARALLEL\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_XARGS_SUPPORT_ARGS_FILE\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_BOOTCHARTD\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_BOOTCHARTD_BLOATED_HEADER\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_BOOTCHARTD_CONFIG_FILE\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_HALT\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_POWEROFF\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_REBOOT\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_WAIT_FOR_INIT\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_CALL_TELINIT\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_TELINIT_PATH\n\tstring\n\tdefault \"\"\nconfig BUSYBOX_DEFAULT_INIT\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_LINUXRC\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_USE_INITTAB\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_KILL_REMOVED\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_KILL_DELAY\n\tint\n\tdefault 0\nconfig BUSYBOX_DEFAULT_FEATURE_INIT_SCTTY\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_INIT_SYSLOG\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_INIT_QUIET\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_INIT_COREDUMPS\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_INIT_TERMINAL_TYPE\n\tstring\n\tdefault \"\"\nconfig BUSYBOX_DEFAULT_FEATURE_INIT_MODIFY_CMDLINE\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_SHADOWPASSWDS\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_USE_BB_PWD_GRP\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_USE_BB_SHADOW\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_USE_BB_CRYPT\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_USE_BB_CRYPT_SHA\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_ADD_SHELL\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_REMOVE_SHELL\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_ADDGROUP\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_ADDUSER_TO_GROUP\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_ADDUSER\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_CHECK_NAMES\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_LAST_ID\n\tint\n\tdefault 0\nconfig BUSYBOX_DEFAULT_FIRST_SYSTEM_ID\n\tint\n\tdefault 0\nconfig BUSYBOX_DEFAULT_LAST_SYSTEM_ID\n\tint\n\tdefault 0\nconfig BUSYBOX_DEFAULT_CHPASSWD\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_DEFAULT_PASSWD_ALGO\n\tstring\n\tdefault \"md5\"\nconfig BUSYBOX_DEFAULT_CRYPTPW\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_MKPASSWD\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_DELUSER\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_DELGROUP\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_DEL_USER_FROM_GROUP\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_GETTY\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_LOGIN\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_LOGIN_SESSION_AS_CHILD\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_LOGIN_SCRIPTS\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_NOLOGIN\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_SECURETTY\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_PASSWD\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_PASSWD_WEAK_CHECK\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_SU\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_SU_SYSLOG\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_SU_CHECKS_SHELLS\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_SU_BLANK_PW_NEEDS_SECURE_TTY\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_SULOGIN\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_VLOCK\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_CHATTR\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FSCK\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_LSATTR\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_TUNE2FS\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_MODPROBE_SMALL\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_DEPMOD\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_INSMOD\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_LSMOD\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_LSMOD_PRETTY_2_6_OUTPUT\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_MODINFO\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_MODPROBE\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_MODPROBE_BLACKLIST\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_RMMOD\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_CMDLINE_MODULE_OPTIONS\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_MODPROBE_SMALL_CHECK_ALREADY_LOADED\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_2_4_MODULES\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_INSMOD_VERSION_CHECKING\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_INSMOD_KSYMOOPS_SYMBOLS\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_INSMOD_LOADINKMEM\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_INSMOD_LOAD_MAP\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_INSMOD_LOAD_MAP_FULL\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_CHECK_TAINTED_MODULE\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_INSMOD_TRY_MMAP\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_MODUTILS_ALIAS\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_MODUTILS_SYMBOLS\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_DEFAULT_MODULES_DIR\n\tstring\n\tdefault \"\"\nconfig BUSYBOX_DEFAULT_DEFAULT_DEPMOD_FILE\n\tstring\n\tdefault \"\"\nconfig BUSYBOX_DEFAULT_ACPID\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_ACPID_COMPAT\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_BLKDISCARD\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_BLKID\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_BLKID_TYPE\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_BLOCKDEV\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_CAL\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_CHRT\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_DMESG\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_DMESG_PRETTY\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_EJECT\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_EJECT_SCSI\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FALLOCATE\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FATATTR\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FBSET\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_FBSET_FANCY\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_FBSET_READMODE\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FDFORMAT\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FDISK\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FDISK_SUPPORT_LARGE_DISKS\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_FDISK_WRITABLE\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_AIX_LABEL\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_SGI_LABEL\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_SUN_LABEL\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_OSF_LABEL\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_GPT_LABEL\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_FDISK_ADVANCED\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FINDFS\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FLOCK\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FDFLUSH\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FREERAMDISK\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FSCK_MINIX\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FSFREEZE\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FSTRIM\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_GETOPT\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_GETOPT_LONG\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_HEXDUMP\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_HD\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_XXD\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_HWCLOCK\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_HWCLOCK_ADJTIME_FHS\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_IONICE\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_IPCRM\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_IPCS\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_LAST\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_LAST_FANCY\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_LOSETUP\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_LSPCI\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_LSUSB\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_MDEV\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_MDEV_CONF\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_MDEV_RENAME\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_MDEV_RENAME_REGEXP\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_MDEV_EXEC\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_MDEV_LOAD_FIRMWARE\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_MDEV_DAEMON\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_MESG\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_MESG_ENABLE_ONLY_GROUP\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_MKE2FS\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_MKFS_EXT2\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_MKFS_MINIX\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_MINIX2\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_MKFS_REISER\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_MKDOSFS\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_MKFS_VFAT\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_MKSWAP\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_MKSWAP_UUID\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_MORE\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_MOUNT\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_MOUNT_FAKE\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_MOUNT_VERBOSE\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_MOUNT_HELPERS\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_MOUNT_LABEL\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_MOUNT_NFS\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_MOUNT_CIFS\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_MOUNT_FLAGS\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_MOUNT_FSTAB\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_MOUNT_OTHERTAB\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_MOUNTPOINT\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_NOLOGIN\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_NOLOGIN_DEPENDENCIES\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_NSENTER\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_PIVOT_ROOT\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_RDATE\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_RDEV\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_READPROFILE\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_RENICE\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_REV\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_RTCWAKE\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_SCRIPT\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_SCRIPTREPLAY\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_SETARCH\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_LINUX32\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_LINUX64\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_SETPRIV\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_SETPRIV_DUMP\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_SETPRIV_CAPABILITIES\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_SETPRIV_CAPABILITY_NAMES\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_SETSID\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_SWAPON\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_SWAPON_DISCARD\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_SWAPON_PRI\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_SWAPOFF\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_SWAPONOFF_LABEL\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_SWITCH_ROOT\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_TASKSET\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_TASKSET_FANCY\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_TASKSET_CPULIST\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_UEVENT\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_UMOUNT\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_UMOUNT_ALL\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_UNSHARE\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_WALL\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_MOUNT_LOOP\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_MOUNT_LOOP_CREATE\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_MTAB_SUPPORT\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_VOLUMEID\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_VOLUMEID_BCACHE\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_VOLUMEID_BTRFS\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_VOLUMEID_CRAMFS\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_VOLUMEID_EROFS\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_VOLUMEID_EXFAT\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_VOLUMEID_EXT\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_VOLUMEID_F2FS\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_VOLUMEID_FAT\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_VOLUMEID_HFS\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_VOLUMEID_ISO9660\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_VOLUMEID_JFS\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_VOLUMEID_LFS\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_VOLUMEID_LINUXRAID\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_VOLUMEID_LINUXSWAP\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_VOLUMEID_LUKS\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_VOLUMEID_MINIX\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_VOLUMEID_NILFS\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_VOLUMEID_NTFS\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_VOLUMEID_OCFS2\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_VOLUMEID_REISERFS\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_VOLUMEID_ROMFS\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_VOLUMEID_SQUASHFS\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_VOLUMEID_SYSV\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_VOLUMEID_UBIFS\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_VOLUMEID_UDF\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_VOLUMEID_XFS\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_ADJTIMEX\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_ASCII\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_BBCONFIG\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_COMPRESS_BBCONFIG\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_BC\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_DC\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_DC_BIG\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_DC_LIBM\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_BC_INTERACTIVE\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_BC_LONG_OPTIONS\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_BEEP\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_BEEP_FREQ\n\tint\n\tdefault 0\nconfig BUSYBOX_DEFAULT_FEATURE_BEEP_LENGTH_MS\n\tint\n\tdefault 0\nconfig BUSYBOX_DEFAULT_CHAT\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_CHAT_NOFAIL\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_CHAT_TTY_HIFI\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_CHAT_IMPLICIT_CR\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_CHAT_SWALLOW_OPTS\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_CHAT_SEND_ESCAPES\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_CHAT_VAR_ABORT_LEN\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_CHAT_CLR_ABORT\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_CONSPY\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_CROND\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_CROND_D\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_CROND_CALL_SENDMAIL\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_CROND_SPECIAL_TIMES\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_CROND_DIR\n\tstring\n\tdefault \"/etc\"\nconfig BUSYBOX_DEFAULT_CRONTAB\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_DEVFSD\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_DEVFSD_MODLOAD\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_DEVFSD_FG_NP\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_DEVFSD_VERBOSE\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_DEVFS\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_DEVMEM\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FBSPLASH\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FLASH_ERASEALL\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FLASH_LOCK\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FLASH_UNLOCK\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FLASHCP\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_HDPARM\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_HDPARM_GET_IDENTITY\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_HDPARM_HDIO_SCAN_HWIF\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_HDPARM_HDIO_UNREGISTER_HWIF\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_HDPARM_HDIO_DRIVE_RESET\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_HDPARM_HDIO_TRISTATE_HWIF\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_HDPARM_HDIO_GETSET_DMA\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_HEXEDIT\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_I2CGET\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_I2CSET\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_I2CDUMP\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_I2CDETECT\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_I2CTRANSFER\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_INOTIFYD\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_LESS\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_LESS_MAXLINES\n\tint\n\tdefault 9999999\nconfig BUSYBOX_DEFAULT_FEATURE_LESS_BRACKETS\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_LESS_FLAGS\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_LESS_TRUNCATE\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_LESS_MARKS\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_LESS_REGEXP\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_LESS_WINCH\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_LESS_ASK_TERMINAL\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_LESS_DASHCMD\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_LESS_LINENUMS\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_LESS_RAW\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_LESS_ENV\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_LOCK\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_LSSCSI\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_MAKEDEVS\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_MAKEDEVS_LEAF\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_MAKEDEVS_TABLE\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_MAN\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_MICROCOM\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_MIM\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_MT\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_NANDWRITE\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_NANDDUMP\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_PARTPROBE\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_RAIDAUTORUN\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_READAHEAD\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_RFKILL\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_RUNLEVEL\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_RX\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_SETFATTR\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_SETSERIAL\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_STRINGS\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_TIME\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_TS\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_TTYSIZE\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_UBIATTACH\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_UBIDETACH\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_UBIMKVOL\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_UBIRMVOL\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_UBIRSVOL\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_UBIUPDATEVOL\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_UBIRENAME\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_VOLNAME\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_WATCHDOG\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_WATCHDOG_OPEN_TWICE\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_IPV6\n\tbool\n\tdefault y if IPV6\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_UNIX_LOCAL\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_PREFER_IPV4_ADDRESS\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_VERBOSE_RESOLUTION_ERRORS\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_ETC_NETWORKS\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_ETC_SERVICES\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_HWIB\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_TLS_SHA1\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_ARP\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_ARPING\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_BRCTL\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_BRCTL_FANCY\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_BRCTL_SHOW\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_DNSD\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_ETHER_WAKE\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FTPD\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_FTPD_WRITE\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_FTPD_ACCEPT_BROKEN_LIST\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_FTPD_AUTHENTICATION\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FTPGET\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FTPPUT\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_FTPGETPUT_LONG_OPTIONS\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_HOSTNAME\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_DNSDOMAINNAME\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_HTTPD\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_HTTPD_PORT_DEFAULT\n\tint\n\tdefault 80\nconfig BUSYBOX_DEFAULT_FEATURE_HTTPD_RANGES\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_HTTPD_SETUID\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_HTTPD_BASIC_AUTH\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_HTTPD_AUTH_MD5\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_HTTPD_CGI\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_HTTPD_CONFIG_WITH_SCRIPT_INTERPR\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_HTTPD_SET_REMOTE_PORT_TO_ENV\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_HTTPD_ENCODE_URL_STR\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_HTTPD_ERROR_PAGES\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_HTTPD_PROXY\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_HTTPD_GZIP\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_HTTPD_ETAG\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_HTTPD_LAST_MODIFIED\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_HTTPD_DATE\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_HTTPD_ACL_IP\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_IFCONFIG\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_IFCONFIG_STATUS\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_IFCONFIG_SLIP\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_IFCONFIG_MEMSTART_IOADDR_IRQ\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_IFCONFIG_HW\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_IFCONFIG_BROADCAST_PLUS\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_IFENSLAVE\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_IFPLUGD\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_IFUP\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_IFDOWN\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_IFUPDOWN_IFSTATE_PATH\n\tstring\n\tdefault \"\"\nconfig BUSYBOX_DEFAULT_FEATURE_IFUPDOWN_IP\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_IFUPDOWN_IPV4\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_IFUPDOWN_IPV6\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_IFUPDOWN_MAPPING\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_IFUPDOWN_EXTERNAL_DHCP\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_INETD\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_INETD_SUPPORT_BUILTIN_ECHO\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_INETD_SUPPORT_BUILTIN_DISCARD\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_INETD_SUPPORT_BUILTIN_TIME\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_INETD_SUPPORT_BUILTIN_DAYTIME\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_INETD_SUPPORT_BUILTIN_CHARGEN\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_INETD_RPC\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_IP\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_IPADDR\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_IPLINK\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_IPROUTE\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_IPTUNNEL\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_IPRULE\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_IPNEIGH\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_IP_ADDRESS\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_IP_LINK\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_IP_ROUTE\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_IP_ROUTE_DIR\n\tstring\n\tdefault \"/etc/iproute2\"\nconfig BUSYBOX_DEFAULT_FEATURE_IP_TUNNEL\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_IP_RULE\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_IP_NEIGH\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_IP_RARE_PROTOCOLS\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_IPCALC\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_IPCALC_LONG_OPTIONS\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_IPCALC_FANCY\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FAKEIDENTD\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_NAMEIF\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_NAMEIF_EXTENDED\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_NBDCLIENT\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_NC\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_NETCAT\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_NC_SERVER\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_NC_EXTRA\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_NC_110_COMPAT\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_NETMSG\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_NETSTAT\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_NETSTAT_WIDE\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_NETSTAT_PRG\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_NSLOOKUP\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_NSLOOKUP_BIG\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_NSLOOKUP_LONG_OPTIONS\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_NTPD\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_NTPD_SERVER\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_NTPD_CONF\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_NTP_AUTH\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_PING\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_PING6\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_FANCY_PING\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_PSCAN\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_ROUTE\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_SLATTACH\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_SSL_CLIENT\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_TC\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_TC_INGRESS\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_TCPSVD\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_UDPSVD\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_TELNET\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_TELNET_TTYPE\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_TELNET_AUTOLOGIN\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_TELNET_WIDTH\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_TELNETD\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_TELNETD_STANDALONE\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_TELNETD_PORT_DEFAULT\n\tint\n\tdefault 23\nconfig BUSYBOX_DEFAULT_FEATURE_TELNETD_INETD_WAIT\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_TFTP\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_TFTP_PROGRESS_BAR\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_TFTP_HPA_COMPAT\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_TFTPD\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_TFTP_GET\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_TFTP_PUT\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_TFTP_BLOCKSIZE\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_TFTP_DEBUG\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_TLS\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_TRACEROUTE\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_TRACEROUTE6\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_TRACEROUTE_VERBOSE\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_TRACEROUTE_USE_ICMP\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_TUNCTL\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_TUNCTL_UG\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_VCONFIG\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_WGET\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_WGET_LONG_OPTIONS\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_WGET_STATUSBAR\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_WGET_FTP\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_WGET_AUTHENTICATION\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_WGET_TIMEOUT\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_WGET_HTTPS\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_WGET_OPENSSL\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_WHOIS\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_ZCIP\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_UDHCPD\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_UDHCPD_BASE_IP_ON_MAC\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_UDHCPD_WRITE_LEASES_EARLY\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_DHCPD_LEASES_FILE\n\tstring\n\tdefault \"\"\nconfig BUSYBOX_DEFAULT_DUMPLEASES\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_DHCPRELAY\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_UDHCPC\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_UDHCPC_ARPING\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_UDHCPC_SANITIZEOPT\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_UDHCPC_DEFAULT_SCRIPT\n\tstring\n\tdefault \"/usr/share/udhcpc/default.script\"\nconfig BUSYBOX_DEFAULT_UDHCPC6\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_UDHCPC6_RFC3646\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_UDHCPC6_RFC4704\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_UDHCPC6_RFC4833\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_UDHCPC6_RFC5970\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_UDHCPC_DEFAULT_INTERFACE\n\tstring\n\tdefault \"\"\nconfig BUSYBOX_DEFAULT_FEATURE_UDHCP_PORT\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_UDHCP_DEBUG\n\tint\n\tdefault 0\nconfig BUSYBOX_DEFAULT_UDHCPC_SLACK_FOR_BUGGY_SERVERS\n\tint\n\tdefault 80\nconfig BUSYBOX_DEFAULT_FEATURE_UDHCP_RFC3397\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_UDHCP_8021Q\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_IFUPDOWN_UDHCPC_CMD_OPTIONS\n\tstring\n\tdefault \"\"\nconfig BUSYBOX_DEFAULT_LPD\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_LPR\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_LPQ\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_MIME_CHARSET\n\tstring\n\tdefault \"\"\nconfig BUSYBOX_DEFAULT_MAKEMIME\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_POPMAILDIR\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_POPMAILDIR_DELIVERY\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_REFORMIME\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_REFORMIME_COMPAT\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_SENDMAIL\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_FAST_TOP\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_SHOW_THREADS\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FREE\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FUSER\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_IOSTAT\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_KILL\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_KILLALL\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_KILLALL5\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_LSOF\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_MPSTAT\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_NMETER\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_PGREP\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_PKILL\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_PIDOF\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_PIDOF_SINGLE\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_PIDOF_OMIT\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_PMAP\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_POWERTOP\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_POWERTOP_INTERACTIVE\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_PS\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_PS_WIDE\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_PS_LONG\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_PS_TIME\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_PS_UNUSUAL_SYSTEMS\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_PS_ADDITIONAL_COLUMNS\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_PSTREE\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_PWDX\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_SMEMCAP\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_BB_SYSCTL\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_TOP\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_TOP_INTERACTIVE\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_TOP_CPU_USAGE_PERCENTAGE\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_TOP_CPU_GLOBAL_PERCENTS\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_TOP_SMP_CPU\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_TOP_DECIMALS\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_TOP_SMP_PROCESS\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_TOPMEM\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_UPTIME\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_UPTIME_UTMP_SUPPORT\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_WATCH\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_CHPST\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_SETUIDGID\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_ENVUIDGID\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_ENVDIR\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_SOFTLIMIT\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_RUNSV\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_RUNSVDIR\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_RUNSVDIR_LOG\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_SV\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_SV_DEFAULT_SERVICE_DIR\n\tstring\n\tdefault \"\"\nconfig BUSYBOX_DEFAULT_SVC\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_SVOK\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_SVLOGD\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_CHCON\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_GETENFORCE\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_GETSEBOOL\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_LOAD_POLICY\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_MATCHPATHCON\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_RUNCON\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_SELINUXENABLED\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_SESTATUS\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_SETENFORCE\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_SETFILES\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_SETFILES_CHECK_OPTION\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_RESTORECON\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_SETSEBOOL\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_SH_IS_ASH\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_SH_IS_HUSH\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_SH_IS_NONE\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_BASH_IS_ASH\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_BASH_IS_HUSH\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_BASH_IS_NONE\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_SHELL_ASH\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_ASH\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_ASH_OPTIMIZE_FOR_SIZE\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_ASH_INTERNAL_GLOB\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_ASH_BASH_COMPAT\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_ASH_BASH_SOURCE_CURDIR\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_ASH_BASH_NOT_FOUND_HOOK\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_ASH_JOB_CONTROL\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_ASH_ALIAS\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_ASH_RANDOM_SUPPORT\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_ASH_EXPAND_PRMT\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_ASH_IDLE_TIMEOUT\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_ASH_MAIL\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_ASH_ECHO\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_ASH_PRINTF\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_ASH_TEST\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_ASH_HELP\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_ASH_GETOPTS\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_ASH_CMDCMD\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_CTTYHACK\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_HUSH\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_SHELL_HUSH\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_HUSH_BASH_COMPAT\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_HUSH_BRACE_EXPANSION\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_HUSH_BASH_SOURCE_CURDIR\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_HUSH_LINENO_VAR\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_HUSH_INTERACTIVE\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_HUSH_SAVEHISTORY\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_HUSH_JOB\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_HUSH_TICK\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_HUSH_IF\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_HUSH_LOOPS\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_HUSH_CASE\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_HUSH_FUNCTIONS\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_HUSH_LOCAL\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_HUSH_RANDOM_SUPPORT\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_HUSH_MODE_X\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_HUSH_ECHO\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_HUSH_PRINTF\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_HUSH_TEST\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_HUSH_HELP\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_HUSH_EXPORT\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_HUSH_EXPORT_N\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_HUSH_READONLY\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_HUSH_KILL\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_HUSH_WAIT\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_HUSH_COMMAND\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_HUSH_TRAP\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_HUSH_TYPE\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_HUSH_TIMES\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_HUSH_READ\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_HUSH_SET\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_HUSH_UNSET\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_HUSH_ULIMIT\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_HUSH_UMASK\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_HUSH_GETOPTS\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_HUSH_MEMLEAK\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_SH_MATH\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_SH_MATH_64\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_SH_MATH_BASE\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_SH_EXTRA_QUIET\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_SH_STANDALONE\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_SH_NOFORK\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_FEATURE_SH_READ_FRAC\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_SH_HISTFILESIZE\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_SH_EMBEDDED_SCRIPTS\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_KLOGD\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_KLOGD_KLOGCTL\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_LOGGER\n\tbool\n\tdefault y\nconfig BUSYBOX_DEFAULT_LOGREAD\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_LOGREAD_REDUCED_LOCKING\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_SYSLOGD\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_ROTATE_LOGFILE\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_REMOTE_LOG\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_SYSLOGD_DUP\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_SYSLOGD_CFG\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_SYSLOGD_PRECISE_TIMESTAMPS\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_SYSLOGD_READ_BUFFER_SIZE\n\tint\n\tdefault 0\nconfig BUSYBOX_DEFAULT_FEATURE_IPC_SYSLOG\n\tbool\n\tdefault n\nconfig BUSYBOX_DEFAULT_FEATURE_IPC_SYSLOG_BUFFER_SIZE\n\tint\n\tdefault 0\nconfig BUSYBOX_DEFAULT_FEATURE_KMSG_SYSLOG\n\tbool\n\tdefault n\n"
  },
  {
    "path": "package/utils/busybox/Config.in",
    "content": "if PACKAGE_busybox || PACKAGE_busybox-selinux\n\nconfig BUSYBOX_CUSTOM\n\tbool \"Customize busybox options\"\n\tdefault n\n        help\n          Enabling this allows full customization of busybox settings.\n          Note that there are many options here that can result in a build\n          that doesn't work properly.  Enabling customization will mark your\n          build as \"tainted\" for the purpose of bug reports.\n          See the variables written to /etc/openwrt_release\n\n          Unless you know what you are doing, you should leave this as 'n'\n\n\tsource \"Config-defaults.in\"\n\n\tif BUSYBOX_CUSTOM\n\tsource \"config/Config.in\"\n\tendif\n\nendif\n"
  },
  {
    "path": "package/utils/busybox/Makefile",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n#\n# Copyright (C) 2006-2021 OpenWrt.org\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=busybox\nPKG_VERSION:=1.35.0\nPKG_RELEASE:=$(AUTORELEASE)\nPKG_FLAGS:=essential\n\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.bz2\nPKG_SOURCE_URL:=https://www.busybox.net/downloads \\\n\t\thttp://sources.buildroot.net\nPKG_HASH:=faeeb244c35a348a334f4a59e44626ee870fb07b6884d68c10ae8bc19f83a694\n\nPKG_BUILD_DEPENDS:=BUSYBOX_CONFIG_PAM:libpam\nPKG_BUILD_PARALLEL:=1\nPKG_CHECK_FORMAT_SECURITY:=0\n\nPKG_LICENSE:=GPL-2.0\nPKG_LICENSE_FILES:=LICENSE archival/libarchive/bz/LICENSE\nPKG_CPE_ID:=cpe:/a:busybox:busybox\n\nBUSYBOX_SYM=$(if $(CONFIG_BUSYBOX_CUSTOM),CONFIG,DEFAULT)\nBUSYBOX_IF_ENABLED=$(if $(CONFIG_BUSYBOX_$(BUSYBOX_SYM)_$(1)),$(2))\n\nifneq ($(CONFIG_BUSYBOX_$(BUSYBOX_SYM)_FEATURE_SUID),)\n  PKG_FILE_MODES:=/bin/busybox:root:root:4755\nendif\n\ninclude $(INCLUDE_DIR)/package.mk\n\nifeq ($(DUMP),)\n  STAMP_CONFIGURED:=$(strip $(STAMP_CONFIGURED))_$(shell grep '^CONFIG_BUSYBOX_' $(TOPDIR)/.config | $(MKHASH) md5)\nendif\n\n# All files provided by busybox will serve as fallback alternatives by opkg.\n# There should be no need to enumerate ALTERNATIVES entries here\ndefine Package/busybox/Default\n  SECTION:=base\n  CATEGORY:=Base system\n  MAINTAINER:=Felix Fietkau <nbd@nbd.name>\n  TITLE:=Core utilities for embedded Linux\n  URL:=http://busybox.net/\n  DEPENDS:=+BUSYBOX_CONFIG_PAM:libpam +BUSYBOX_CONFIG_NTPD:jsonfilter\n  USERID:=ntp=123:ntp=123\nendef\n\ndefine Package/busybox\n  $(call Package/busybox/Default)\n  CONFLICTS:=busybox-selinux\n  VARIANT:=default\nendef\n\ndefine Package/busybox-selinux\n  $(call Package/busybox/Default)\n  TITLE += with SELinux support\n  DEPENDS += +libselinux\n  VARIANT:=selinux\n  PROVIDES:=busybox\nendef\n\ndefine Package/busybox/description\n The Swiss Army Knife of embedded Linux.\n It slices, it dices, it makes Julian Fries.\nendef\n\ndefine Package/busybox/config\n\tsource \"$(SOURCE)/Config.in\"\nendef\n\nifneq ($(CONFIG_BUSYBOX_$(BUSYBOX_SYM)_FEATURE_SYSLOG)$(CONFIG_BUSYBOX_$(BUSYBOX_SYM)_FEATURE_SYSLOGD_CFG),)\ndefine Package/busybox/conffiles/syslog\n/etc/syslog.conf\nendef\nendif\n\nifneq ($(CONFIG_BUSYBOX_$(BUSYBOX_SYM)_CROND),)\ndefine Package/busybox/conffiles/crond\n/etc/crontabs/\nendef\nendif\n\ndefine Package/busybox/conffiles\n$(Package/busybox/conffiles/syslog)\n$(Package/busybox/conffiles/crond)\nendef\n\nPackage/busybox-selinux/conffiles = $(Package/busybox/conffiles)\n\nifndef CONFIG_USE_MUSL\nLDLIBS:=m crypt\nendif\n\nLDLIBS += $(call BUSYBOX_IF_ENABLED,PAM,pam pam_misc pthread)\n\nifeq ($(CONFIG_USE_GLIBC),y)\n  LDLIBS += $(call BUSYBOX_IF_ENABLED,NSLOOKUP,resolv)\nendif\n\nifeq ($(BUILD_VARIANT),selinux)\n  LDLIBS += selinux sepol\nendif\n\nTARGET_CFLAGS += -flto\nTARGET_LDFLAGS += -flto=jobserver -fuse-linker-plugin\n\nMAKE_VARS :=\nMAKE_FLAGS += \\\n\tEXTRA_CFLAGS=\"$(TARGET_CFLAGS) $(TARGET_CPPFLAGS)\" \\\n\tEXTRA_LDFLAGS=\"$(TARGET_LDFLAGS)\" \\\n\tLDLIBS=\"$(LDLIBS)\" \\\n\tLD=\"$(TARGET_CC)\" \\\n\tSKIP_STRIP=y\nifneq ($(findstring c,$(OPENWRT_VERBOSE)),)\n  MAKE_FLAGS += V=1\nendif\n\ndefine Build/Configure\n\trm -f $(PKG_BUILD_DIR)/.config\n\ttouch $(PKG_BUILD_DIR)/.config\nifeq ($(DEVICE_TYPE),nas)\n\techo \"CONFIG_HDPARM=y\" >> $(PKG_BUILD_DIR)/.config\nendif\nifeq ($(BUILD_VARIANT),selinux)\n\tcat $(TOPDIR)/$(SOURCE)/selinux.config >> $(PKG_BUILD_DIR)/.config\nendif\n\tgrep 'CONFIG_BUSYBOX_$(BUSYBOX_SYM)' $(TOPDIR)/.config | sed -e \"s,\\\\(# \\)\\\\?CONFIG_BUSYBOX_$(BUSYBOX_SYM)_\\\\(.*\\\\),\\\\1CONFIG_\\\\2,g\" >> $(PKG_BUILD_DIR)/.config\n\tyes 'n' | $(MAKE) -C $(PKG_BUILD_DIR) $(MAKE_FLAGS) oldconfig\nendef\n\ndefine Build/Compile\n\t$(call Build/Compile/Default, \\\n\t\tCONFIG_PREFIX=\"$(PKG_INSTALL_DIR)\" \\\n\t\tall install \\\n\t)\nendef\n\ndefine Package/busybox/install\n\t$(INSTALL_DIR) $(1)/etc/init.d\n\t$(INSTALL_DIR) $(1)/usr/sbin\n\t$(CP) $(PKG_INSTALL_DIR)/* $(1)/\nifneq ($(CONFIG_BUSYBOX_$(BUSYBOX_SYM)_FEATURE_SYSLOG)$(CONFIG_BUSYBOX_$(BUSYBOX_SYM)_FEATURE_SYSLOGD_CFG),)\n\ttouch $(1)/etc/syslog.conf\nendif\nifneq ($(CONFIG_BUSYBOX_$(BUSYBOX_SYM)_CROND),)\n\t$(INSTALL_BIN) ./files/cron $(1)/etc/init.d/cron\n\t$(INSTALL_DIR) $(1)/etc/crontabs\nendif\nifneq ($(CONFIG_BUSYBOX_$(BUSYBOX_SYM)_NTPD),)\n\t$(INSTALL_BIN) ./files/sysntpd $(1)/etc/init.d/sysntpd\n\t$(INSTALL_BIN) ./files/ntpd-hotplug $(1)/usr/sbin/ntpd-hotplug\n\t$(INSTALL_DIR) $(1)/etc/capabilities $(1)/usr/share/acl.d\n\t$(INSTALL_DATA) ./files/ntpd.capabilities $(1)/etc/capabilities/ntpd.json\n\t$(INSTALL_DATA) ./files/ntpd_acl.json $(1)/usr/share/acl.d/ntpd.json\nendif\n\t-rm -rf $(1)/lib64\nendef\n\nPackage/busybox-selinux/install = $(Package/busybox/install)\n\n$(eval $(call BuildPackage,busybox))\n$(eval $(call BuildPackage,busybox-selinux))\n"
  },
  {
    "path": "package/utils/busybox/config/Config.in",
    "content": "#\n# For a description of the syntax of this configuration file,\n# see docs/Kconfig-language.txt.\n#\n\n\nconfig BUSYBOX_CONFIG_HAVE_DOT_CONFIG\n\tbool\n\tdefault BUSYBOX_DEFAULT_HAVE_DOT_CONFIG\n\nmenu \"Settings\"\n\nconfig BUSYBOX_CONFIG_DESKTOP\n\tbool \"Enable compatibility for full-blown desktop systems (8kb)\"\n\tdefault BUSYBOX_DEFAULT_DESKTOP\n\thelp\n\tEnable applet options and features which are not essential.\n\tMany applet options have dedicated config options to (de)select them\n\tunder that applet; this options enables those options which have no\n\tindividual config item for them.\n\n\tSelect this if you plan to use busybox on full-blown desktop machine\n\twith common Linux distro, which needs higher level of command-line\n\tcompatibility.\n\n\tIf you are preparing your build to be used on an embedded box\n\twhere you have tighter control over the entire set of userspace\n\ttools, you can unselect this option for smaller code size.\n\nconfig BUSYBOX_CONFIG_EXTRA_COMPAT\n\tbool \"Provide compatible behavior for rare corner cases (bigger code)\"\n\tdefault BUSYBOX_DEFAULT_EXTRA_COMPAT\n\thelp\n\tThis option makes grep, sed etc handle rare corner cases\n\t(embedded NUL bytes and such). This makes code bigger and uses\n\tsome GNU extensions in libc. You probably only need this option\n\tif you plan to run busybox on desktop.\n\nconfig BUSYBOX_CONFIG_FEDORA_COMPAT\n\tbool \"Building for Fedora distribution\"\n\tdefault BUSYBOX_DEFAULT_FEDORA_COMPAT\n\thelp\n\tThis option makes some tools behave like they do on Fedora.\n\n\tAt the time of this writing (2017-08) this only affects uname:\n\tnormally, uname -p (processor) and uname -i (platform)\n\tare shown as \"unknown\", but with this option uname -p\n\tshows the same string as uname -m (machine type),\n\tand so does uname -i unless machine type is i486/i586/i686 -\n\tthen uname -i shows \"i386\".\n\nconfig BUSYBOX_CONFIG_INCLUDE_SUSv2\n\tbool \"Enable obsolete features removed before SUSv3\"\n\tdefault BUSYBOX_DEFAULT_INCLUDE_SUSv2\n\thelp\n\tThis option will enable backwards compatibility with SuSv2,\n\tspecifically, old-style numeric options ('command -1 <file>')\n\twill be supported in head, tail, and fold. (Note: should\n\taffect renice too.)\n\nconfig BUSYBOX_CONFIG_LONG_OPTS\n\tbool \"Support --long-options\"\n\tdefault BUSYBOX_DEFAULT_LONG_OPTS\n\thelp\n\tEnable this if you want busybox applets to use the gnu --long-option\n\tstyle, in addition to single character -a -b -c style options.\n\nconfig BUSYBOX_CONFIG_SHOW_USAGE\n\tbool \"Show applet usage messages\"\n\tdefault BUSYBOX_DEFAULT_SHOW_USAGE\n\thelp\n\tEnabling this option, applets will show terse help messages\n\twhen invoked with wrong arguments.\n\tIf you do not want to show any (helpful) usage message when\n\tissuing wrong command syntax, you can say 'N' here,\n\tsaving approximately 7k.\n\nconfig BUSYBOX_CONFIG_FEATURE_VERBOSE_USAGE\n\tbool \"Show verbose applet usage messages\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_VERBOSE_USAGE\n\tdepends on BUSYBOX_CONFIG_SHOW_USAGE\n\thelp\n\tAll applets will show verbose help messages when invoked with --help.\n\tThis will add a lot of text to the binary.\n\nconfig BUSYBOX_CONFIG_FEATURE_COMPRESS_USAGE\n\tbool \"Store applet usage messages in compressed form\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_COMPRESS_USAGE\n\tdepends on BUSYBOX_CONFIG_SHOW_USAGE\n\thelp\n\tStore usage messages in .bz2 compressed form, uncompress them\n\ton-the-fly when \"APPLET --help\" is run.\n\n\tIf you have a really tiny busybox with few applets enabled (and\n\tbunzip2 isn't one of them), the overhead of the decompressor might\n\tbe noticeable. Also, if you run executables directly from ROM\n\tand have very little memory, this might not be a win. Otherwise,\n\tyou probably want this.\n\nconfig BUSYBOX_CONFIG_LFS\n\tbool\n\tdefault BUSYBOX_DEFAULT_LFS\n\thelp\n\tIf you need to work with large files, enable this option.\n\tThis will have no effect if your kernel or your C\n\tlibrary lacks large file support for large files. Some of the\n\tprograms that can benefit from large file support include dd, gzip,\n\tcp, mount, tar.\n\nconfig BUSYBOX_CONFIG_PAM\n\tbool \"Support PAM (Pluggable Authentication Modules)\"\n\tdefault BUSYBOX_DEFAULT_PAM\n\thelp\n\tUse PAM in some applets (currently login and httpd) instead\n\tof direct access to password database.\n\nconfig BUSYBOX_CONFIG_FEATURE_DEVPTS\n\tbool \"Use the devpts filesystem for Unix98 PTYs\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_DEVPTS\n\thelp\n\tEnable if you want to use Unix98 PTY support. If enabled,\n\tbusybox will use /dev/ptmx for the master side of the pseudoterminal\n\tand /dev/pts/<number> for the slave side. Otherwise, BSD style\n\t/dev/ttyp<number> will be used. To use this option, you should have\n\tdevpts mounted.\n\nconfig BUSYBOX_CONFIG_FEATURE_UTMP\n\tbool \"Support utmp file\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_UTMP\n\thelp\n\tThe file /var/run/utmp is used to track who is currently logged in.\n\tWith this option on, certain applets (getty, login, telnetd etc)\n\twill create and delete entries there.\n\t\"who\" applet requires this option.\n\nconfig BUSYBOX_CONFIG_FEATURE_WTMP\n\tbool \"Support wtmp file\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_WTMP\n\tdepends on BUSYBOX_CONFIG_FEATURE_UTMP\n\thelp\n\tThe file /var/run/wtmp is used to track when users have logged into\n\tand logged out of the system.\n\tWith this option on, certain applets (getty, login, telnetd etc)\n\twill append new entries there.\n\t\"last\" applet requires this option.\n\nconfig BUSYBOX_CONFIG_FEATURE_PIDFILE\n\tbool \"Support writing pidfiles\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_PIDFILE\n\thelp\n\tThis option makes some applets (e.g. crond, syslogd, inetd) write\n\ta pidfile at the configured PID_FILE_PATH.  It has no effect\n\ton applets which require pidfiles to run.\n\nconfig BUSYBOX_CONFIG_PID_FILE_PATH\n\tstring \"Directory for pidfiles\"\n\tdefault BUSYBOX_DEFAULT_PID_FILE_PATH\n\tdepends on BUSYBOX_CONFIG_FEATURE_PIDFILE || BUSYBOX_CONFIG_FEATURE_CROND_SPECIAL_TIMES\n\thelp\n\tThis is the default path where pidfiles are created.  Applets which\n\tallow you to set the pidfile path on the command line will override\n\tthis value.  The option has no effect on applets that require you to\n\tspecify a pidfile path.  When crond has the 'Support special times'\n\toption enabled, the 'crond.reboot' file is also stored here.\n\nconfig BUSYBOX_CONFIG_BUSYBOX\n\tbool \"Include busybox applet\"\n\tdefault BUSYBOX_DEFAULT_BUSYBOX\n\thelp\n\tThe busybox applet provides general help message and allows\n\tthe included applets to be listed.  It also provides\n\toptional --install command to create applet links. If you unselect\n\tthis option, running busybox without any arguments will give\n\tjust a cryptic error message:\n\n\t$ busybox\n\tbusybox: applet not found\n\n\tRunning \"busybox APPLET [ARGS...]\" will still work, of course.\n\nconfig BUSYBOX_CONFIG_FEATURE_SHOW_SCRIPT\n\tbool \"Support --show SCRIPT\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_SHOW_SCRIPT\n\tdepends on BUSYBOX_CONFIG_BUSYBOX\n\nconfig BUSYBOX_CONFIG_FEATURE_INSTALLER\n\tbool \"Support --install [-s] to install applet links at runtime\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_INSTALLER\n\tdepends on BUSYBOX_CONFIG_BUSYBOX\n\thelp\n\tEnable 'busybox --install [-s]' support. This will allow you to use\n\tbusybox at runtime to create hard links or symlinks for all the\n\tapplets that are compiled into busybox.\n\nconfig BUSYBOX_CONFIG_INSTALL_NO_USR\n\tbool \"Don't use /usr\"\n\tdefault BUSYBOX_DEFAULT_INSTALL_NO_USR\n\thelp\n\tDisable use of /usr. \"busybox --install\" and \"make install\"\n\twill install applets only to /bin and /sbin,\n\tnever to /usr/bin or /usr/sbin.\n\nconfig BUSYBOX_CONFIG_FEATURE_SUID\n\tbool \"Drop SUID state for most applets\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_SUID\n\thelp\n\tWith this option you can install the busybox binary belonging\n\tto root with the suid bit set, enabling some applets to perform\n\troot-level operations even when run by ordinary users\n\t(for example, mounting of user mounts in fstab needs this).\n\n\tWith this option enabled, busybox drops privileges for applets\n\tthat don't need root access, before entering their main() function.\n\n\tIf you are really paranoid and don't want even initial busybox code\n\tto run under root for every applet, build two busybox binaries with\n\tdifferent applets in them (and the appropriate symlinks pointing\n\tto each binary), and only set the suid bit on the one that needs it.\n\n\tSome applets which require root rights (need suid bit on the binary\n\tor to be run by root) and will refuse to execute otherwise:\n\tcrontab, login, passwd, su, vlock, wall.\n\n\tThe applets which will use root rights if they have them\n\t(via suid bit, or because run by root), but would try to work\n\twithout root right nevertheless:\n\tfindfs, ping[6], traceroute[6], mount.\n\n\tNote that if you DO NOT select this option, but DO make busybox\n\tsuid root, ALL applets will run under root, which is a huge\n\tsecurity hole (think \"cp /some/file /etc/passwd\").\n\nconfig BUSYBOX_CONFIG_FEATURE_SUID_CONFIG\n\tbool \"Enable SUID configuration via /etc/busybox.conf\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_SUID_CONFIG\n\tdepends on BUSYBOX_CONFIG_FEATURE_SUID\n\thelp\n\tAllow the SUID/SGID state of an applet to be determined at runtime\n\tby checking /etc/busybox.conf. (This is sort of a poor man's sudo.)\n\tThe format of this file is as follows:\n\n\tAPPLET = [Ssx-][Ssx-][x-] [USER.GROUP]\n\n\ts: USER or GROUP is allowed to execute APPLET.\n\t   APPLET will run under USER or GROUP\n\t   (regardless of who's running it).\n\tS: USER or GROUP is NOT allowed to execute APPLET.\n\t   APPLET will run under USER or GROUP.\n\t   This option is not very sensical.\n\tx: USER/GROUP/others are allowed to execute APPLET.\n\t   No UID/GID change will be done when it is run.\n\t-: USER/GROUP/others are not allowed to execute APPLET.\n\n\tAn example might help:\n\n\t|[SUID]\n\t|su = ssx root.0 # applet su can be run by anyone and runs with\n\t|                # euid=0,egid=0\n\t|su = ssx        # exactly the same\n\t|\n\t|mount = sx- root.disk # applet mount can be run by root and members\n\t|                      # of group disk (but not anyone else)\n\t|                      # and runs with euid=0 (egid is not changed)\n\t|\n\t|cp = --- # disable applet cp for everyone\n\n\tThe file has to be owned by user root, group root and has to be\n\twriteable only by root:\n\t\t(chown 0.0 /etc/busybox.conf; chmod 600 /etc/busybox.conf)\n\tThe busybox executable has to be owned by user root, group\n\troot and has to be setuid root for this to work:\n\t\t(chown 0.0 /bin/busybox; chmod 4755 /bin/busybox)\n\n\tRobert 'sandman' Griebl has more information here:\n\t<url: http://www.softforge.de/bb/suid.html >.\n\nconfig BUSYBOX_CONFIG_FEATURE_SUID_CONFIG_QUIET\n\tbool \"Suppress warning message if /etc/busybox.conf is not readable\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_SUID_CONFIG_QUIET\n\tdepends on BUSYBOX_CONFIG_FEATURE_SUID_CONFIG\n\thelp\n\t/etc/busybox.conf should be readable by the user needing the SUID,\n\tcheck this option to avoid users to be notified about missing\n\tpermissions.\n\nconfig BUSYBOX_CONFIG_FEATURE_PREFER_APPLETS\n\tbool \"exec prefers applets\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_PREFER_APPLETS\n\thelp\n\tThis is an experimental option which directs applets about to\n\tcall 'exec' to try and find an applicable busybox applet before\n\tsearching the PATH. This is typically done by exec'ing\n\t/proc/self/exe.\n\n\tThis may affect shell, find -exec, xargs and similar applets.\n\tThey will use applets even if /bin/APPLET -> busybox link\n\tis missing (or is not a link to busybox). However, this causes\n\tproblems in chroot jails without mounted /proc and with ps/top\n\t(command name can be shown as 'exe' for applets started this way).\n\nconfig BUSYBOX_CONFIG_BUSYBOX_EXEC_PATH\n\tstring \"Path to busybox executable\"\n\tdefault BUSYBOX_DEFAULT_BUSYBOX_EXEC_PATH\n\thelp\n\tWhen applets need to run other applets, busybox\n\tsometimes needs to exec() itself. When the /proc filesystem is\n\tmounted, /proc/self/exe always points to the currently running\n\texecutable. If you haven't got /proc, set this to wherever you\n\twant to run busybox from.\n\nconfig BUSYBOX_CONFIG_SELINUX\n\tbool \"Support NSA Security Enhanced Linux\"\n\tdefault BUSYBOX_DEFAULT_SELINUX\n\thelp\n\tEnable support for SELinux in applets ls, ps, and id. Also provide\n\tthe option of compiling in SELinux applets.\n\n\tIf you do not have a complete SELinux userland installed, this stuff\n\twill not compile.  Specifially, libselinux 1.28 or better is\n\tdirectly required by busybox. If the installation is located in a\n\tnon-standard directory, provide it by invoking make as follows:\n\n\t\tCFLAGS=-I<libselinux-include-path> \\\n\t\tLDFLAGS=-L<libselinux-lib-path> \\\n\t\tmake\n\n\tMost people will leave this set to 'N'.\n\nconfig BUSYBOX_CONFIG_FEATURE_CLEAN_UP\n\tbool \"Clean up all memory before exiting (usually not needed)\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_CLEAN_UP\n\thelp\n\tAs a size optimization, busybox normally exits without explicitly\n\tfreeing dynamically allocated memory or closing files. This saves\n\tspace since the OS will clean up for us, but it can confuse debuggers\n\tlike valgrind, which report tons of memory and resource leaks.\n\n\tDon't enable this unless you have a really good reason to clean\n\tthings up manually.\n\nconfig BUSYBOX_CONFIG_FEATURE_SYSLOG_INFO\n\tbool \"Support LOG_INFO level syslog messages\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_SYSLOG_INFO\n\tdepends on BUSYBOX_CONFIG_FEATURE_SYSLOG\n\thelp\n\tApplets which send their output to syslog use either LOG_INFO or\n\tLOG_ERR log levels, but by disabling this option all messages will\n\tbe logged at the LOG_ERR level, saving just under 200 bytes.\n\n# These are auto-selected by other options\n\nconfig BUSYBOX_CONFIG_FEATURE_SYSLOG\n\tbool #No description makes it a hidden option\n\tdefault BUSYBOX_DEFAULT_FEATURE_SYSLOG\n\t#help\n\t#This option is auto-selected when you select any applet which may\n\t#send its output to syslog. You do not need to select it manually.\n\ncomment 'Build Options'\n\nconfig BUSYBOX_CONFIG_STATIC\n\tbool \"Build static binary (no shared libs)\"\n\tdefault BUSYBOX_DEFAULT_STATIC\n\thelp\n\tIf you want to build a static binary, which does not use\n\tor require any shared libraries, enable this option.\n\tStatic binaries are larger, but do not require functioning\n\tdynamic libraries to be present, which is important if used\n\tas a system rescue tool.\n\nconfig BUSYBOX_CONFIG_PIE\n\tbool \"Build position independent executable\"\n\tdefault BUSYBOX_DEFAULT_PIE\n\tdepends on !BUSYBOX_CONFIG_STATIC\n\thelp\n\tHardened code option. PIE binaries are loaded at a different\n\taddress at each invocation. This has some overhead,\n\tparticularly on x86-32 which is short on registers.\n\n\tMost people will leave this set to 'N'.\n\nconfig BUSYBOX_CONFIG_NOMMU\n\tbool \"Force NOMMU build\"\n\tdefault BUSYBOX_DEFAULT_NOMMU\n\thelp\n\tBusybox tries to detect whether architecture it is being\n\tbuilt against supports MMU or not. If this detection fails,\n\tor if you want to build NOMMU version of busybox for testing,\n\tyou may force NOMMU build here.\n\n\tMost people will leave this set to 'N'.\n\n# PIE can be made to work with BUILD_LIBBUSYBOX, but currently\n# build system does not support that\nconfig BUSYBOX_CONFIG_BUILD_LIBBUSYBOX\n\tbool \"Build shared libbusybox\"\n\tdefault BUSYBOX_DEFAULT_BUILD_LIBBUSYBOX\n\tdepends on !BUSYBOX_CONFIG_FEATURE_PREFER_APPLETS && !BUSYBOX_CONFIG_PIE && !BUSYBOX_CONFIG_STATIC\n\thelp\n\tBuild a shared library libbusybox.so.N.N.N which contains all\n\tbusybox code.\n\n\tThis feature allows every applet to be built as a really tiny\n\tseparate executable linked against the library:\n\t|$ size 0_lib/l*\n\t|    text  data   bss     dec    hex filename\n\t|     939   212    28    1179    49b 0_lib/last\n\t|     939   212    28    1179    49b 0_lib/less\n\t|  919138  8328  1556  929022  e2cfe 0_lib/libbusybox.so.1.N.M\n\n\tThis is useful on NOMMU systems which are not capable\n\tof sharing executables, but are capable of sharing code\n\tin dynamic libraries.\n\nconfig BUSYBOX_CONFIG_FEATURE_LIBBUSYBOX_STATIC\n\tbool \"Pull in all external references into libbusybox\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_LIBBUSYBOX_STATIC\n\tdepends on BUSYBOX_CONFIG_BUILD_LIBBUSYBOX\n\thelp\n\tMake libbusybox library independent, not using or requiring\n\tany other shared libraries.\n\nconfig BUSYBOX_CONFIG_FEATURE_INDIVIDUAL\n\tbool \"Produce a binary for each applet, linked against libbusybox\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_INDIVIDUAL\n\tdepends on BUSYBOX_CONFIG_BUILD_LIBBUSYBOX\n\thelp\n\tIf your CPU architecture doesn't allow for sharing text/rodata\n\tsections of running binaries, but allows for runtime dynamic\n\tlibraries, this option will allow you to reduce memory footprint\n\twhen you have many different applets running at once.\n\n\tIf your CPU architecture allows for sharing text/rodata,\n\thaving single binary is more optimal.\n\n\tEach applet will be a tiny program, dynamically linked\n\tagainst libbusybox.so.N.N.N.\n\n\tYou need to have a working dynamic linker.\n\nconfig BUSYBOX_CONFIG_FEATURE_SHARED_BUSYBOX\n\tbool \"Produce additional busybox binary linked against libbusybox\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_SHARED_BUSYBOX\n\tdepends on BUSYBOX_CONFIG_BUILD_LIBBUSYBOX\n\thelp\n\tBuild busybox, dynamically linked against libbusybox.so.N.N.N.\n\n\tYou need to have a working dynamic linker.\n\n### config BUILD_AT_ONCE\n###\tbool \"Compile all sources at once\"\n###\tdefault n\n###\thelp\n###\tNormally each source-file is compiled with one invocation of\n###\tthe compiler.\n###\tIf you set this option, all sources are compiled at once.\n###\tThis gives the compiler more opportunities to optimize which can\n###\tresult in smaller and/or faster binaries.\n###\n###\tSetting this option will consume alot of memory, e.g. if you\n###\tenable all applets with all features, gcc uses more than 300MB\n###\tRAM during compilation of busybox.\n###\n###\tThis option is most likely only beneficial for newer compilers\n###\tsuch as gcc-4.1 and above.\n###\n###\tSay 'N' unless you know what you are doing.\n\nconfig BUSYBOX_CONFIG_CROSS_COMPILER_PREFIX\n\tstring \"Cross compiler prefix\"\n\tdefault BUSYBOX_DEFAULT_CROSS_COMPILER_PREFIX\n\thelp\n\tIf you want to build busybox with a cross compiler, then you\n\twill need to set this to the cross-compiler prefix, for example,\n\t\"i386-uclibc-\".\n\n\tNote that CROSS_COMPILE environment variable or\n\t\"make CROSS_COMPILE=xxx ...\" will override this selection.\n\n\tNative builds leave this empty.\n\nconfig BUSYBOX_CONFIG_SYSROOT\n\tstring \"Path to sysroot\"\n\tdefault BUSYBOX_DEFAULT_SYSROOT\n\thelp\n\tIf you want to build busybox with a cross compiler, then you\n\tmight also need to specify where /usr/include and /usr/lib\n\twill be found.\n\n\tFor example, busybox can be built against an installed\n\tAndroid NDK, platform version 9, for ARM ABI with\n\n\tCONFIG_SYSROOT=/opt/android-ndk/platforms/android-9/arch-arm\n\n\tNative builds leave this empty.\n\nconfig BUSYBOX_CONFIG_EXTRA_CFLAGS\n\tstring \"Additional CFLAGS\"\n\tdefault BUSYBOX_DEFAULT_EXTRA_CFLAGS\n\thelp\n\tAdditional CFLAGS to pass to the compiler verbatim.\n\nconfig BUSYBOX_CONFIG_EXTRA_LDFLAGS\n\tstring \"Additional LDFLAGS\"\n\tdefault BUSYBOX_DEFAULT_EXTRA_LDFLAGS\n\thelp\n\tAdditional LDFLAGS to pass to the linker verbatim.\n\nconfig BUSYBOX_CONFIG_EXTRA_LDLIBS\n\tstring \"Additional LDLIBS\"\n\tdefault BUSYBOX_DEFAULT_EXTRA_LDLIBS\n\thelp\n\tAdditional LDLIBS to pass to the linker with -l.\n\nconfig BUSYBOX_CONFIG_USE_PORTABLE_CODE\n\tbool \"Avoid using GCC-specific code constructs\"\n\tdefault BUSYBOX_DEFAULT_USE_PORTABLE_CODE\n\thelp\n\tUse this option if you are trying to compile busybox with\n\tcompiler other than gcc.\n\tIf you do use gcc, this option may needlessly increase code size.\n\nconfig BUSYBOX_CONFIG_STACK_OPTIMIZATION_386\n\tbool \"Use -mpreferred-stack-boundary=2 on i386 arch\"\n\tdefault BUSYBOX_DEFAULT_STACK_OPTIMIZATION_386\n\thelp\n\tThis option makes for smaller code, but some libc versions\n\tdo not work with it (they use SSE instructions without\n\tensuring stack alignment).\n\nconfig BUSYBOX_CONFIG_STATIC_LIBGCC\n\tbool \"Use -static-libgcc\"\n\tdefault BUSYBOX_DEFAULT_STATIC_LIBGCC\n\thelp\n\tThis option instructs gcc to link in a static version of its\n\tsupport library, libgcc. This means that the binary will require\n\tone fewer dynamic library at run time.\n\ncomment 'Installation Options (\"make install\" behavior)'\n\nchoice\n\tprompt \"What kind of applet links to install\"\n\tdefault BUSYBOX_CONFIG_INSTALL_APPLET_SYMLINKS\n\thelp\n\tChoose what kind of links to applets are created by \"make install\".\n\nconfig BUSYBOX_CONFIG_INSTALL_APPLET_SYMLINKS\n\tbool \"as soft-links\"\n\thelp\n\tInstall applets as soft-links to the busybox binary. This needs some\n\tfree inodes on the filesystem, but might help with filesystem\n\tgenerators that can't cope with hard-links.\n\nconfig BUSYBOX_CONFIG_INSTALL_APPLET_HARDLINKS\n\tbool \"as hard-links\"\n\thelp\n\tInstall applets as hard-links to the busybox binary. This might\n\tcount on a filesystem with few inodes.\n\nconfig BUSYBOX_CONFIG_INSTALL_APPLET_SCRIPT_WRAPPERS\n\tbool \"as script wrappers\"\n\thelp\n\tInstall applets as script wrappers that call the busybox binary.\n\nconfig BUSYBOX_CONFIG_INSTALL_APPLET_DONT\n\tbool \"not installed\"\n\thelp\n\tDo not install applet links. Useful when you plan to use\n\tbusybox --install for installing links, or plan to use\n\ta standalone shell and thus don't need applet links.\n\nendchoice\n\nchoice\n\tprompt \"/bin/sh applet link\"\n\tdefault BUSYBOX_CONFIG_INSTALL_SH_APPLET_SYMLINK\n\tdepends on BUSYBOX_CONFIG_INSTALL_APPLET_SCRIPT_WRAPPERS\n\thelp\n\tChoose how you install /bin/sh applet link.\n\nconfig BUSYBOX_CONFIG_INSTALL_SH_APPLET_SYMLINK\n\tbool \"as soft-link\"\n\thelp\n\tInstall /bin/sh applet as soft-link to the busybox binary.\n\nconfig BUSYBOX_CONFIG_INSTALL_SH_APPLET_HARDLINK\n\tbool \"as hard-link\"\n\thelp\n\tInstall /bin/sh applet as hard-link to the busybox binary.\n\nconfig BUSYBOX_CONFIG_INSTALL_SH_APPLET_SCRIPT_WRAPPER\n\tbool \"as script wrapper\"\n\thelp\n\tInstall /bin/sh applet as script wrapper that calls\n\tthe busybox binary.\n\nendchoice\n\nconfig BUSYBOX_CONFIG_PREFIX\n\tstring \"Destination path for 'make install'\"\n\tdefault BUSYBOX_DEFAULT_PREFIX\n\thelp\n\tWhere \"make install\" should install busybox binary and links.\n\ncomment 'Debugging Options'\n\nconfig BUSYBOX_CONFIG_DEBUG\n\tbool \"Build with debug information\"\n\tdefault BUSYBOX_DEFAULT_DEBUG\n\thelp\n\tSay Y here to compile with debug information.\n\tThis increases the size of the binary considerably, and\n\tshould only be used when doing development.\n\n\tThis adds -g option to gcc command line.\n\n\tMost people should answer N.\n\nconfig BUSYBOX_CONFIG_DEBUG_PESSIMIZE\n\tbool \"Disable compiler optimizations\"\n\tdefault BUSYBOX_DEFAULT_DEBUG_PESSIMIZE\n\tdepends on BUSYBOX_CONFIG_DEBUG\n\thelp\n\tThe compiler's optimization of source code can eliminate and reorder\n\tcode, resulting in an executable that's hard to understand when\n\tstepping through it with a debugger. This switches it off, resulting\n\tin a much bigger executable that more closely matches the source\n\tcode.\n\n\tThis replaces -Os/-O2 with -O0 in gcc command line.\n\nconfig BUSYBOX_CONFIG_DEBUG_SANITIZE\n\tbool \"Enable runtime sanitizers (ASAN/LSAN/USAN/etc...)\"\n\tdefault BUSYBOX_DEFAULT_DEBUG_SANITIZE\n\thelp\n\tSay Y here if you want to enable runtime sanitizers. These help\n\tcatch bad memory accesses (e.g. buffer overflows), but will make\n\tthe executable larger and slow down runtime a bit.\n\n\tThis adds -fsanitize=foo options to gcc command line.\n\n\tIf you aren't developing/testing busybox, say N here.\n\nconfig BUSYBOX_CONFIG_UNIT_TEST\n\tbool \"Build unit tests\"\n\tdefault BUSYBOX_DEFAULT_UNIT_TEST\n\thelp\n\tSay Y here if you want to build unit tests (both the framework and\n\ttest cases) as an applet. This results in bigger code, so you\n\tprobably don't want this option in production builds.\n\nconfig BUSYBOX_CONFIG_WERROR\n\tbool \"Abort compilation on any warning\"\n\tdefault BUSYBOX_DEFAULT_WERROR\n\thelp\n\tThis adds -Werror to gcc command line.\n\n\tMost people should answer N.\n\nconfig BUSYBOX_CONFIG_WARN_SIMPLE_MSG\n\tbool \"Warn about single parameter bb_xx_msg calls\"\n\tdefault BUSYBOX_DEFAULT_WARN_SIMPLE_MSG\n\thelp\n\tThis will cause warnings to be shown for any instances of\n\tbb_error_msg(), bb_error_msg_and_die(), bb_perror_msg(),\n\tbb_perror_msg_and_die(), bb_herror_msg() or bb_herror_msg_and_die()\n\tbeing called with a single parameter. In these cases the equivalent\n\tbb_simple_xx_msg function should be used instead.\n\tNote that use of STRERROR_FMT may give false positives.\n\n\tIf you aren't developing busybox, say N here.\n\nchoice\n\tprompt \"Additional debugging library\"\n\tdefault BUSYBOX_CONFIG_NO_DEBUG_LIB\n\thelp\n\tUsing an additional debugging library will make busybox become\n\tconsiderably larger and will cause it to run more slowly. You\n\tshould always leave this option disabled for production use.\n\n\tdmalloc support:\n\t----------------\n\tThis enables compiling with dmalloc ( http://dmalloc.com/ )\n\twhich is an excellent public domain mem leak and malloc problem\n\tdetector. To enable dmalloc, before running busybox you will\n\twant to properly set your environment, for example:\n\t\texport DMALLOC_OPTIONS=debug=0x34f47d83,inter=100,log=logfile\n\tThe 'debug=' value is generated using the following command\n\tdmalloc -p log-stats -p log-non-free -p log-bad-space \\\n\t\t-p log-elapsed-time -p check-fence -p check-heap \\\n\t\t-p check-lists -p check-blank -p check-funcs -p realloc-copy \\\n\t\t-p allow-free-null\n\n\tElectric-fence support:\n\t-----------------------\n\tThis enables compiling with Electric-fence support. Electric\n\tfence is another very useful malloc debugging library which uses\n\tyour computer's virtual memory hardware to detect illegal memory\n\taccesses. This support will make busybox be considerably larger\n\tand run slower, so you should leave this option disabled unless\n\tyou are hunting a hard to find memory problem.\n\n\nconfig BUSYBOX_CONFIG_NO_DEBUG_LIB\n\tbool \"None\"\n\nconfig BUSYBOX_CONFIG_DMALLOC\n\tbool \"Dmalloc\"\n\nconfig BUSYBOX_CONFIG_EFENCE\n\tbool \"Electric-fence\"\n\nendchoice\n\nsource \"libbb/Config.in\"\n\nendmenu\n\ncomment \"Applets\"\n\nsource \"archival/Config.in\"\nsource \"coreutils/Config.in\"\nsource \"console-tools/Config.in\"\nsource \"debianutils/Config.in\"\nsource \"klibc-utils/Config.in\"\nsource \"editors/Config.in\"\nsource \"findutils/Config.in\"\nsource \"init/Config.in\"\nsource \"loginutils/Config.in\"\nsource \"e2fsprogs/Config.in\"\nsource \"modutils/Config.in\"\nsource \"util-linux/Config.in\"\nsource \"miscutils/Config.in\"\nsource \"networking/Config.in\"\nsource \"printutils/Config.in\"\nsource \"mailutils/Config.in\"\nsource \"procps/Config.in\"\nsource \"runit/Config.in\"\nsource \"selinux/Config.in\"\nsource \"shell/Config.in\"\nsource \"sysklogd/Config.in\"\n"
  },
  {
    "path": "package/utils/busybox/config/archival/Config.in",
    "content": "# DO NOT EDIT. This file is generated from Config.src\n#\n# For a description of the syntax of this configuration file,\n# see docs/Kconfig-language.txt.\n#\n\nmenu \"Archival Utilities\"\n\nconfig BUSYBOX_CONFIG_FEATURE_SEAMLESS_XZ\n\tbool \"Make tar, rpm, modprobe etc understand .xz data\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_SEAMLESS_XZ\n\nconfig BUSYBOX_CONFIG_FEATURE_SEAMLESS_LZMA\n\tbool \"Make tar, rpm, modprobe etc understand .lzma data\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_SEAMLESS_LZMA\n\nconfig BUSYBOX_CONFIG_FEATURE_SEAMLESS_BZ2\n\tbool \"Make tar, rpm, modprobe etc understand .bz2 data\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_SEAMLESS_BZ2\n\nconfig BUSYBOX_CONFIG_FEATURE_SEAMLESS_GZ\n\tbool \"Make tar, rpm, modprobe etc understand .gz data\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_SEAMLESS_GZ\n\nconfig BUSYBOX_CONFIG_FEATURE_SEAMLESS_Z\n\tbool \"Make tar, rpm, modprobe etc understand .Z data\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_SEAMLESS_Z  # it is ancient\n\nconfig BUSYBOX_CONFIG_AR\n\tbool \"ar (9.5 kb)\"\n\tdefault BUSYBOX_DEFAULT_AR  # needs to be improved to be able to replace binutils ar\n\thelp\n\tar is an archival utility program used to create, modify, and\n\textract contents from archives. In practice, it is used exclusively\n\tfor object module archives used by compilers.\n\n\tUnless you have a specific application which requires ar, you should\n\tprobably say N here: most compilers come with their own ar utility.\n\nconfig BUSYBOX_CONFIG_FEATURE_AR_LONG_FILENAMES\n\tbool \"Support long filenames (not needed for debs)\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_AR_LONG_FILENAMES\n\tdepends on BUSYBOX_CONFIG_AR\n\thelp\n\tBy default the ar format can only store the first 15 characters\n\tof the filename, this option removes that limitation.\n\tIt supports the GNU ar long filename method which moves multiple long\n\tfilenames into a the data section of a new ar entry.\n\nconfig BUSYBOX_CONFIG_FEATURE_AR_CREATE\n\tbool \"Support archive creation\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_AR_CREATE\n\tdepends on BUSYBOX_CONFIG_AR\n\thelp\n\tThis enables archive creation (-c and -r) with busybox ar.\nconfig BUSYBOX_CONFIG_UNCOMPRESS\n\tbool \"uncompress (7.1 kb)\"\n\tdefault BUSYBOX_DEFAULT_UNCOMPRESS  # ancient\n\thelp\n\tuncompress is used to decompress archives created by compress.\n\tNot much used anymore, replaced by gzip/gunzip.\nconfig BUSYBOX_CONFIG_GUNZIP\n\tbool \"gunzip (11 kb)\"\n\tdefault BUSYBOX_DEFAULT_GUNZIP\n\tselect BUSYBOX_CONFIG_FEATURE_GZIP_DECOMPRESS\n\thelp\n\tgunzip is used to decompress archives created by gzip.\n\tYou can use the '-t' option to test the integrity of\n\tan archive, without decompressing it.\n\nconfig BUSYBOX_CONFIG_ZCAT\n\tbool \"zcat (24 kb)\"\n\tdefault BUSYBOX_DEFAULT_ZCAT\n\tselect BUSYBOX_CONFIG_FEATURE_GZIP_DECOMPRESS\n\thelp\n\tAlias to \"gunzip -c\".\n\nconfig BUSYBOX_CONFIG_FEATURE_GUNZIP_LONG_OPTIONS\n\tbool \"Enable long options\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_GUNZIP_LONG_OPTIONS\n\tdepends on (BUSYBOX_CONFIG_GUNZIP || BUSYBOX_CONFIG_ZCAT) && BUSYBOX_CONFIG_LONG_OPTS\nconfig BUSYBOX_CONFIG_BUNZIP2\n\tbool \"bunzip2 (8.7 kb)\"\n\tdefault BUSYBOX_DEFAULT_BUNZIP2\n\tselect BUSYBOX_CONFIG_FEATURE_BZIP2_DECOMPRESS\n\thelp\n\tbunzip2 is a compression utility using the Burrows-Wheeler block\n\tsorting text compression algorithm, and Huffman coding. Compression\n\tis generally considerably better than that achieved by more\n\tconventional LZ77/LZ78-based compressors, and approaches the\n\tperformance of the PPM family of statistical compressors.\n\n\tUnless you have a specific application which requires bunzip2, you\n\tshould probably say N here.\n\nconfig BUSYBOX_CONFIG_BZCAT\n\tbool \"bzcat (8.7 kb)\"\n\tdefault BUSYBOX_DEFAULT_BZCAT\n\tselect BUSYBOX_CONFIG_FEATURE_BZIP2_DECOMPRESS\n\thelp\n\tAlias to \"bunzip2 -c\".\nconfig BUSYBOX_CONFIG_UNLZMA\n\tbool \"unlzma (7.5 kb)\"\n\tdefault BUSYBOX_DEFAULT_UNLZMA\n\thelp\n\tunlzma is a compression utility using the Lempel-Ziv-Markov chain\n\tcompression algorithm, and range coding. Compression\n\tis generally considerably better than that achieved by the bzip2\n\tcompressors.\n\nconfig BUSYBOX_CONFIG_LZCAT\n\tbool \"lzcat (7.5 kb)\"\n\tdefault BUSYBOX_DEFAULT_LZCAT\n\thelp\n\tAlias to \"unlzma -c\".\n\nconfig BUSYBOX_CONFIG_LZMA\n\tbool \"lzma -d\"\n\tdefault BUSYBOX_DEFAULT_LZMA\n\thelp\n\tEnable this option if you want commands like \"lzma -d\" to work.\n\tIOW: you'll get lzma applet, but it will always require -d option.\nconfig BUSYBOX_CONFIG_UNXZ\n\tbool \"unxz (13 kb)\"\n\tdefault BUSYBOX_DEFAULT_UNXZ\n\thelp\n\tunxz is a unlzma successor.\n\nconfig BUSYBOX_CONFIG_XZCAT\n\tbool \"xzcat (13 kb)\"\n\tdefault BUSYBOX_DEFAULT_XZCAT\n\thelp\n\tAlias to \"unxz -c\".\n\nconfig BUSYBOX_CONFIG_XZ\n\tbool \"xz -d\"\n\tdefault BUSYBOX_DEFAULT_XZ\n\thelp\n\tEnable this option if you want commands like \"xz -d\" to work.\n\tIOW: you'll get xz applet, but it will always require -d option.\nconfig BUSYBOX_CONFIG_BZIP2\n\tbool \"bzip2 (16 kb)\"\n\tdefault BUSYBOX_DEFAULT_BZIP2\n\thelp\n\tbzip2 is a compression utility using the Burrows-Wheeler block\n\tsorting text compression algorithm, and Huffman coding. Compression\n\tis generally considerably better than that achieved by more\n\tconventional LZ77/LZ78-based compressors, and approaches the\n\tperformance of the PPM family of statistical compressors.\n\n\tUnless you have a specific application which requires bzip2, you\n\tshould probably say N here.\n\nconfig BUSYBOX_CONFIG_BZIP2_SMALL\n\tint \"Trade bytes for speed (0:fast, 9:small)\"\n\tdefault BUSYBOX_DEFAULT_BZIP2_SMALL  # all \"fast or small\" options default to small\n\trange 0 9\n\tdepends on BUSYBOX_CONFIG_BZIP2\n\thelp\n\tTrade code size versus speed.\n\tApproximate values with gcc-6.3.0 \"bzip -9\" compressing\n\tlinux-4.15.tar were:\n\tvalue         time (sec)  code size (386)\n\t9 (smallest)       70.11             7687\n\t8                  67.93             8091\n\t7                  67.88             8405\n\t6                  67.78             8624\n\t5                  67.05             9427\n\t4-0 (fastest)      64.14            12083\n\nconfig BUSYBOX_CONFIG_FEATURE_BZIP2_DECOMPRESS\n\tbool \"Enable decompression\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_BZIP2_DECOMPRESS\n\tdepends on BUSYBOX_CONFIG_BZIP2 || BUSYBOX_CONFIG_BUNZIP2 || BUSYBOX_CONFIG_BZCAT\n\thelp\n\tEnable -d (--decompress) and -t (--test) options for bzip2.\n\tThis will be automatically selected if bunzip2 or bzcat is\n\tenabled.\nconfig BUSYBOX_CONFIG_CPIO\n\tbool \"cpio (15 kb)\"\n\tdefault BUSYBOX_DEFAULT_CPIO\n\thelp\n\tcpio is an archival utility program used to create, modify, and\n\textract contents from archives.\n\tcpio has 110 bytes of overheads for every stored file.\n\n\tThis implementation of cpio can extract cpio archives created in the\n\t\"newc\" or \"crc\" format.\n\n\tUnless you have a specific application which requires cpio, you\n\tshould probably say N here.\n\nconfig BUSYBOX_CONFIG_FEATURE_CPIO_O\n\tbool \"Support archive creation\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_CPIO_O\n\tdepends on BUSYBOX_CONFIG_CPIO\n\thelp\n\tThis implementation of cpio can create cpio archives in the \"newc\"\n\tformat only.\n\nconfig BUSYBOX_CONFIG_FEATURE_CPIO_P\n\tbool \"Support passthrough mode\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_CPIO_P\n\tdepends on BUSYBOX_CONFIG_FEATURE_CPIO_O\n\thelp\n\tPassthrough mode. Rarely used.\n\nconfig BUSYBOX_CONFIG_FEATURE_CPIO_IGNORE_DEVNO\n\tbool \"Support --ignore-devno like GNU cpio\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_CPIO_IGNORE_DEVNO\n\tdepends on BUSYBOX_CONFIG_FEATURE_CPIO_O && BUSYBOX_CONFIG_LONG_OPTS\n\thelp\n\tOptionally ignore device numbers when creating archives.\n\nconfig BUSYBOX_CONFIG_FEATURE_CPIO_RENUMBER_INODES\n\tbool \"Support --renumber-inodes like GNU cpio\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_CPIO_RENUMBER_INODES\n\tdepends on BUSYBOX_CONFIG_FEATURE_CPIO_O && BUSYBOX_CONFIG_LONG_OPTS\n\thelp\n\tOptionally renumber inodes when creating archives.\nconfig BUSYBOX_CONFIG_DPKG\n\tbool \"dpkg (43 kb)\"\n\tdefault BUSYBOX_DEFAULT_DPKG\n\tselect BUSYBOX_CONFIG_FEATURE_SEAMLESS_GZ\n\thelp\n\tdpkg is a medium-level tool to install, build, remove and manage\n\tDebian packages.\n\n\tThis implementation of dpkg has a number of limitations,\n\tyou should use the official dpkg if possible.\nconfig BUSYBOX_CONFIG_DPKG_DEB\n\tbool \"dpkg-deb (30 kb)\"\n\tdefault BUSYBOX_DEFAULT_DPKG_DEB\n\tselect BUSYBOX_CONFIG_FEATURE_SEAMLESS_GZ\n\thelp\n\tdpkg-deb unpacks and provides information about Debian archives.\n\n\tThis implementation of dpkg-deb cannot pack archives.\n\n\tUnless you have a specific application which requires dpkg-deb,\n\tsay N here.\nconfig BUSYBOX_CONFIG_GZIP\n\tbool \"gzip (17 kb)\"\n\tdefault BUSYBOX_DEFAULT_GZIP\n\thelp\n\tgzip is used to compress files.\n\tIt's probably the most widely used UNIX compression program.\n\nconfig BUSYBOX_CONFIG_FEATURE_GZIP_LONG_OPTIONS\n\tbool \"Enable long options\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_GZIP_LONG_OPTIONS\n\tdepends on BUSYBOX_CONFIG_GZIP && BUSYBOX_CONFIG_LONG_OPTS\n\nconfig BUSYBOX_CONFIG_GZIP_FAST\n\tint \"Trade memory for speed (0:small,slow - 2:fast,big)\"\n\tdefault BUSYBOX_DEFAULT_GZIP_FAST\n\trange 0 2\n\tdepends on BUSYBOX_CONFIG_GZIP\n\thelp\n\tEnable big memory options for gzip.\n\t0: small buffers, small hash-tables\n\t1: larger buffers, larger hash-tables\n\t2: larger buffers, largest hash-tables\n\tLarger models may give slightly better compression\n\nconfig BUSYBOX_CONFIG_FEATURE_GZIP_LEVELS\n\tbool \"Enable compression levels\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_GZIP_LEVELS\n\tdepends on BUSYBOX_CONFIG_GZIP\n\thelp\n\tEnable support for compression levels 4-9. The default level\n\tis 6. If levels 1-3 are specified, 4 is used.\n\tIf this option is not selected, -N options are ignored and -6\n\tis used.\n\nconfig BUSYBOX_CONFIG_FEATURE_GZIP_DECOMPRESS\n\tbool \"Enable decompression\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_GZIP_DECOMPRESS\n\tdepends on BUSYBOX_CONFIG_GZIP || BUSYBOX_CONFIG_GUNZIP || BUSYBOX_CONFIG_ZCAT\n\thelp\n\tEnable -d (--decompress) and -t (--test) options for gzip.\n\tThis will be automatically selected if gunzip or zcat is\n\tenabled.\nconfig BUSYBOX_CONFIG_LZOP\n\tbool \"lzop (12 kb)\"\n\tdefault BUSYBOX_DEFAULT_LZOP\n\thelp\n\tLzop compression/decompresion.\n\nconfig BUSYBOX_CONFIG_UNLZOP\n\tbool \"unlzop (13 kb)\"\n\tdefault BUSYBOX_DEFAULT_UNLZOP  # INCOMPAT: upstream lzop does not provide such tool\n\thelp\n\tLzop decompresion.\n\nconfig BUSYBOX_CONFIG_LZOPCAT\n\tbool \"lzopcat (13 kb)\"\n\tdefault BUSYBOX_DEFAULT_LZOPCAT  # INCOMPAT: upstream lzop does not provide such tool\n\thelp\n\tAlias to \"lzop -dc\".\n\nconfig BUSYBOX_CONFIG_LZOP_COMPR_HIGH\n\tbool \"lzop compression levels 7,8,9 (not very useful)\"\n\tdefault BUSYBOX_DEFAULT_LZOP_COMPR_HIGH\n\tdepends on BUSYBOX_CONFIG_LZOP || BUSYBOX_CONFIG_UNLZOP || BUSYBOX_CONFIG_LZOPCAT\n\thelp\n\tHigh levels (7,8,9) of lzop compression. These levels\n\tare actually slower than gzip at equivalent compression ratios\n\tand take up 3.2K of code.\nconfig BUSYBOX_CONFIG_RPM\n\tbool \"rpm (32 kb)\"\n\tdefault BUSYBOX_DEFAULT_RPM\n\thelp\n\tMini RPM applet - queries and extracts RPM packages.\nconfig BUSYBOX_CONFIG_RPM2CPIO\n\tbool \"rpm2cpio (21 kb)\"\n\tdefault BUSYBOX_DEFAULT_RPM2CPIO\n\thelp\n\tConverts a RPM file into a CPIO archive.\nconfig BUSYBOX_CONFIG_TAR\n\tbool \"tar (39 kb)\"\n\tdefault BUSYBOX_DEFAULT_TAR\n\thelp\n\ttar is an archiving program. It's commonly used with gzip to\n\tcreate compressed archives. It's probably the most widely used\n\tUNIX archive program.\n\nconfig BUSYBOX_CONFIG_FEATURE_TAR_LONG_OPTIONS\n\tbool \"Enable long options\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_TAR_LONG_OPTIONS\n\tdepends on BUSYBOX_CONFIG_TAR && BUSYBOX_CONFIG_LONG_OPTS\n\nconfig BUSYBOX_CONFIG_FEATURE_TAR_CREATE\n\tbool \"Enable -c (archive creation)\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_TAR_CREATE\n\tdepends on BUSYBOX_CONFIG_TAR\n\nconfig BUSYBOX_CONFIG_FEATURE_TAR_AUTODETECT\n\tbool \"Autodetect compressed tarballs\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_TAR_AUTODETECT\n\tdepends on BUSYBOX_CONFIG_TAR && (BUSYBOX_CONFIG_FEATURE_SEAMLESS_Z || BUSYBOX_CONFIG_FEATURE_SEAMLESS_GZ || BUSYBOX_CONFIG_FEATURE_SEAMLESS_BZ2 || BUSYBOX_CONFIG_FEATURE_SEAMLESS_LZMA || BUSYBOX_CONFIG_FEATURE_SEAMLESS_XZ)\n\thelp\n\tWith this option tar can automatically detect compressed\n\ttarballs. Currently it works only on files (not pipes etc).\n\nconfig BUSYBOX_CONFIG_FEATURE_TAR_FROM\n\tbool \"Enable -X (exclude from) and -T (include from) options\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_TAR_FROM\n\tdepends on BUSYBOX_CONFIG_TAR\n\thelp\n\tIf you enable this option you'll be able to specify\n\ta list of files to include or exclude from an archive.\n\nconfig BUSYBOX_CONFIG_FEATURE_TAR_OLDGNU_COMPATIBILITY\n\tbool \"Support old tar header format\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_TAR_OLDGNU_COMPATIBILITY\n\tdepends on BUSYBOX_CONFIG_TAR || BUSYBOX_CONFIG_DPKG\n\thelp\n\tThis option is required to unpack archives created in\n\tthe old GNU format; help to kill this old format by\n\trepacking your ancient archives with the new format.\n\nconfig BUSYBOX_CONFIG_FEATURE_TAR_OLDSUN_COMPATIBILITY\n\tbool \"Enable untarring of tarballs with checksums produced by buggy Sun tar\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_TAR_OLDSUN_COMPATIBILITY\n\tdepends on BUSYBOX_CONFIG_TAR || BUSYBOX_CONFIG_DPKG\n\thelp\n\tThis option is required to unpack archives created by some old\n\tversion of Sun's tar (it was calculating checksum using signed\n\tarithmetic). It is said to be fixed in newer Sun tar, but \"old\"\n\ttarballs still exist.\n\nconfig BUSYBOX_CONFIG_FEATURE_TAR_GNU_EXTENSIONS\n\tbool \"Support GNU tar extensions (long filenames)\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_TAR_GNU_EXTENSIONS\n\tdepends on BUSYBOX_CONFIG_TAR || BUSYBOX_CONFIG_DPKG\n\nconfig BUSYBOX_CONFIG_FEATURE_TAR_TO_COMMAND\n\tbool \"Support writing to an external program (--to-command)\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_TAR_TO_COMMAND\n\tdepends on BUSYBOX_CONFIG_TAR && BUSYBOX_CONFIG_FEATURE_TAR_LONG_OPTIONS\n\thelp\n\tIf you enable this option you'll be able to instruct tar to send\n\tthe contents of each extracted file to the standard input of an\n\texternal program.\n\nconfig BUSYBOX_CONFIG_FEATURE_TAR_UNAME_GNAME\n\tbool \"Enable use of user and group names\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_TAR_UNAME_GNAME\n\tdepends on BUSYBOX_CONFIG_TAR\n\thelp\n\tEnable use of user and group names in tar. This affects contents\n\tlistings (-t) and preserving permissions when unpacking (-p).\n\t+200 bytes.\n\nconfig BUSYBOX_CONFIG_FEATURE_TAR_NOPRESERVE_TIME\n\tbool \"Enable -m (do not preserve time) GNU option\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_TAR_NOPRESERVE_TIME\n\tdepends on BUSYBOX_CONFIG_TAR\n\nconfig BUSYBOX_CONFIG_FEATURE_TAR_SELINUX\n\tbool \"Support extracting SELinux labels\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_TAR_SELINUX\n\tdepends on BUSYBOX_CONFIG_TAR && BUSYBOX_CONFIG_SELINUX\n\thelp\n\tWith this option busybox supports restoring SELinux labels\n\twhen extracting files from tar archives.\nconfig BUSYBOX_CONFIG_UNZIP\n\tbool \"unzip (26 kb)\"\n\tdefault BUSYBOX_DEFAULT_UNZIP\n\thelp\n\tunzip will list or extract files from a ZIP archive,\n\tcommonly found on DOS/WIN systems. The default behavior\n\t(with no options) is to extract the archive into the\n\tcurrent directory.\n\nconfig BUSYBOX_CONFIG_FEATURE_UNZIP_CDF\n\tbool \"Read and use Central Directory data\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_UNZIP_CDF\n\tdepends on BUSYBOX_CONFIG_UNZIP\n\thelp\n\tIf you know that you only need to deal with simple\n\tZIP files without deleted/updated files, SFX archives etc,\n\tyou can reduce code size by unselecting this option.\n\tTo support less trivial ZIPs, say Y.\n\nconfig BUSYBOX_CONFIG_FEATURE_UNZIP_BZIP2\n\tbool \"Support compression method 12 (bzip2)\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_UNZIP_BZIP2\n\tdepends on BUSYBOX_CONFIG_FEATURE_UNZIP_CDF && BUSYBOX_CONFIG_DESKTOP\n\nconfig BUSYBOX_CONFIG_FEATURE_UNZIP_LZMA\n\tbool \"Support compression method 14 (lzma)\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_UNZIP_LZMA\n\tdepends on BUSYBOX_CONFIG_FEATURE_UNZIP_CDF && BUSYBOX_CONFIG_DESKTOP\n\nconfig BUSYBOX_CONFIG_FEATURE_UNZIP_XZ\n\tbool \"Support compression method 95 (xz)\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_UNZIP_XZ\n\tdepends on BUSYBOX_CONFIG_FEATURE_UNZIP_CDF && BUSYBOX_CONFIG_DESKTOP\n\nconfig BUSYBOX_CONFIG_FEATURE_LZMA_FAST\n\tbool \"Optimize lzma for speed\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_LZMA_FAST\n\tdepends on BUSYBOX_CONFIG_UNLZMA || BUSYBOX_CONFIG_LZCAT || BUSYBOX_CONFIG_LZMA || BUSYBOX_CONFIG_FEATURE_SEAMLESS_LZMA\n\thelp\n\tThis option reduces decompression time by about 25% at the cost of\n\ta 1K bigger binary.\n\nendmenu\n"
  },
  {
    "path": "package/utils/busybox/config/console-tools/Config.in",
    "content": "# DO NOT EDIT. This file is generated from Config.src\n#\n# For a description of the syntax of this configuration file,\n# see docs/Kconfig-language.txt.\n#\n\nmenu \"Console Utilities\"\n\nconfig BUSYBOX_CONFIG_CHVT\n\tbool \"chvt (2 kb)\"\n\tdefault BUSYBOX_DEFAULT_CHVT\n\thelp\n\tThis program is used to change to another terminal.\n\tExample: chvt 4 (change to terminal /dev/tty4)\nconfig BUSYBOX_CONFIG_CLEAR\n\tbool \"clear (tiny)\"\n\tdefault BUSYBOX_DEFAULT_CLEAR\n\thelp\n\tThis program clears the terminal screen.\nconfig BUSYBOX_CONFIG_DEALLOCVT\n\tbool \"deallocvt (1.9 kb)\"\n\tdefault BUSYBOX_DEFAULT_DEALLOCVT\n\thelp\n\tThis program deallocates unused virtual consoles.\nconfig BUSYBOX_CONFIG_DUMPKMAP\n\tbool \"dumpkmap (1.6 kb)\"\n\tdefault BUSYBOX_DEFAULT_DUMPKMAP\n\thelp\n\tThis program dumps the kernel's keyboard translation table to\n\tstdout, in binary format. You can then use loadkmap to load it.\nconfig BUSYBOX_CONFIG_FGCONSOLE\n\tbool \"fgconsole (1.5 kb)\"\n\tdefault BUSYBOX_DEFAULT_FGCONSOLE\n\thelp\n\tThis program prints active (foreground) console number.\nconfig BUSYBOX_CONFIG_KBD_MODE\n\tbool \"kbd_mode (4.1 kb)\"\n\tdefault BUSYBOX_DEFAULT_KBD_MODE\n\thelp\n\tThis program reports and sets keyboard mode.\nconfig BUSYBOX_CONFIG_LOADFONT\n\tbool \"loadfont (5.2 kb)\"\n\tdefault BUSYBOX_DEFAULT_LOADFONT\n\thelp\n\tThis program loads a console font from standard input.\n\nconfig BUSYBOX_CONFIG_SETFONT\n\tbool \"setfont (24 kb)\"\n\tdefault BUSYBOX_DEFAULT_SETFONT\n\thelp\n\tAllows to load console screen map. Useful for i18n.\n\nconfig BUSYBOX_CONFIG_FEATURE_SETFONT_TEXTUAL_MAP\n\tbool \"Support reading textual screen maps\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_SETFONT_TEXTUAL_MAP\n\tdepends on BUSYBOX_CONFIG_SETFONT\n\thelp\n\tSupport reading textual screen maps.\n\nconfig BUSYBOX_CONFIG_DEFAULT_SETFONT_DIR\n\tstring \"Default directory for console-tools files\"\n\tdefault BUSYBOX_DEFAULT_DEFAULT_SETFONT_DIR\n\tdepends on BUSYBOX_CONFIG_SETFONT\n\thelp\n\tDirectory to use if setfont's params are simple filenames\n\t(not /path/to/file or ./file). Default is \"\" (no default directory).\n\ncomment \"Common options for loadfont and setfont\"\n\tdepends on BUSYBOX_CONFIG_LOADFONT || BUSYBOX_CONFIG_SETFONT\n\nconfig BUSYBOX_CONFIG_FEATURE_LOADFONT_PSF2\n\tbool \"Support PSF2 console fonts\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_LOADFONT_PSF2\n\tdepends on BUSYBOX_CONFIG_LOADFONT || BUSYBOX_CONFIG_SETFONT\n\nconfig BUSYBOX_CONFIG_FEATURE_LOADFONT_RAW\n\tbool \"Support old (raw) console fonts\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_LOADFONT_RAW\n\tdepends on BUSYBOX_CONFIG_LOADFONT || BUSYBOX_CONFIG_SETFONT\nconfig BUSYBOX_CONFIG_LOADKMAP\n\tbool \"loadkmap (1.8 kb)\"\n\tdefault BUSYBOX_DEFAULT_LOADKMAP\n\thelp\n\tThis program loads a keyboard translation table from\n\tstandard input.\nconfig BUSYBOX_CONFIG_OPENVT\n\tbool \"openvt (7.2 kb)\"\n\tdefault BUSYBOX_DEFAULT_OPENVT\n\thelp\n\tThis program is used to start a command on an unused\n\tvirtual terminal.\nconfig BUSYBOX_CONFIG_RESET\n\tbool \"reset (345 bytes)\"\n\tdefault BUSYBOX_DEFAULT_RESET\n\thelp\n\tThis program is used to reset the terminal screen, if it\n\tgets messed up.\nconfig BUSYBOX_CONFIG_RESIZE\n\tbool \"resize (903 bytes)\"\n\tdefault BUSYBOX_DEFAULT_RESIZE\n\thelp\n\tThis program is used to (re)set the width and height of your current\n\tterminal.\n\nconfig BUSYBOX_CONFIG_FEATURE_RESIZE_PRINT\n\tbool \"Print environment variables\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_RESIZE_PRINT\n\tdepends on BUSYBOX_CONFIG_RESIZE\n\thelp\n\tPrints the newly set size (number of columns and rows) of\n\tthe terminal.\n\tE.g.:\n\tCOLUMNS=80;LINES=44;export COLUMNS LINES;\nconfig BUSYBOX_CONFIG_SETCONSOLE\n\tbool \"setconsole (3.6 kb)\"\n\tdefault BUSYBOX_DEFAULT_SETCONSOLE\n\thelp\n\tRedirect writes to /dev/console to another device,\n\tlike the current tty while logged in via telnet.\n\tThis does not redirect kernel log, only writes\n\tfrom user space.\n\nconfig BUSYBOX_CONFIG_FEATURE_SETCONSOLE_LONG_OPTIONS\n\tbool \"Enable long options\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_SETCONSOLE_LONG_OPTIONS\n\tdepends on BUSYBOX_CONFIG_SETCONSOLE && BUSYBOX_CONFIG_LONG_OPTS\nconfig BUSYBOX_CONFIG_SETKEYCODES\n\tbool \"setkeycodes (2.1 kb)\"\n\tdefault BUSYBOX_DEFAULT_SETKEYCODES\n\thelp\n\tThis program loads entries into the kernel's scancode-to-keycode\n\tmap, allowing unusual keyboards to generate usable keycodes.\nconfig BUSYBOX_CONFIG_SETLOGCONS\n\tbool \"setlogcons (1.8 kb)\"\n\tdefault BUSYBOX_DEFAULT_SETLOGCONS\n\thelp\n\tThis program redirects the output console of kernel messages.\nconfig BUSYBOX_CONFIG_SHOWKEY\n\tbool \"showkey (4.7 kb)\"\n\tdefault BUSYBOX_DEFAULT_SHOWKEY\n\thelp\n\tShows keys pressed.\n\nendmenu\n"
  },
  {
    "path": "package/utils/busybox/config/coreutils/Config.in",
    "content": "# DO NOT EDIT. This file is generated from Config.src\n#\n# For a description of the syntax of this configuration file,\n# see docs/Kconfig-language.txt.\n#\n\nmenu \"Coreutils\"\n\nconfig BUSYBOX_CONFIG_FEATURE_VERBOSE\n\tbool \"Support verbose options (usually -v) for various applets\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_VERBOSE\n\thelp\n\tEnable cp -v, rm -v and similar messages.\n\tAlso enables long option (--verbose) if it exists.\n\tWithout this option, -v is accepted but ignored.\n\ncomment \"Common options for date and touch\"\n\nconfig BUSYBOX_CONFIG_FEATURE_TIMEZONE\n\tbool \"Allow timezone in dates\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_TIMEZONE\n\tdepends on BUSYBOX_CONFIG_DESKTOP\n\thelp\n\tPermit the use of timezones when parsing user-provided data\n\tstrings, e.g. '1996-04-09 12:45:00 -0500'.\n\n\tThis requires support for the '%z' extension to strptime() which\n\tmay not be available in all implementations.\n\ncomment \"Common options for cp and mv\"\n\tdepends on BUSYBOX_CONFIG_CP || BUSYBOX_CONFIG_MV\n\nconfig BUSYBOX_CONFIG_FEATURE_PRESERVE_HARDLINKS\n\tbool \"Preserve hard links\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_PRESERVE_HARDLINKS\n\tdepends on BUSYBOX_CONFIG_CP || BUSYBOX_CONFIG_MV\n\thelp\n\tAllow cp and mv to preserve hard links.\n\ncomment \"Common options for df, du, ls\"\n\tdepends on BUSYBOX_CONFIG_DF || BUSYBOX_CONFIG_DU || BUSYBOX_CONFIG_LS\n\nconfig BUSYBOX_CONFIG_FEATURE_HUMAN_READABLE\n\tbool \"Support human readable output (example 13k, 23M, 235G)\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_HUMAN_READABLE\n\tdepends on BUSYBOX_CONFIG_DF || BUSYBOX_CONFIG_DU || BUSYBOX_CONFIG_LS\n\thelp\n\tAllow df, du, and ls to have human readable output.\n\nconfig BUSYBOX_CONFIG_BASENAME\n\tbool \"basename (438 bytes)\"\n\tdefault BUSYBOX_DEFAULT_BASENAME\n\thelp\n\tbasename is used to strip the directory and suffix from filenames,\n\tleaving just the filename itself. Enable this option if you wish\n\tto enable the 'basename' utility.\nconfig BUSYBOX_CONFIG_CAT\n\tbool \"cat (5.6 kb)\"\n\tdefault BUSYBOX_DEFAULT_CAT\n\thelp\n\tcat is used to concatenate files and print them to the standard\n\toutput. Enable this option if you wish to enable the 'cat' utility.\n\nconfig BUSYBOX_CONFIG_FEATURE_CATN\n\tbool \"Enable -n and -b options\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_CATN\n\tdepends on BUSYBOX_CONFIG_CAT\n\thelp\n\t-n numbers all output lines while -b numbers nonempty output lines.\n\nconfig BUSYBOX_CONFIG_FEATURE_CATV\n\tbool \"cat -v[etA]\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_CATV\n\tdepends on BUSYBOX_CONFIG_CAT\n\thelp\n\tDisplay nonprinting characters as escape sequences\nconfig BUSYBOX_CONFIG_CHGRP\n\tbool \"chgrp (7.6 kb)\"\n\tdefault BUSYBOX_DEFAULT_CHGRP\n\thelp\n\tchgrp is used to change the group ownership of files.\nconfig BUSYBOX_CONFIG_CHMOD\n\tbool \"chmod (5.5 kb)\"\n\tdefault BUSYBOX_DEFAULT_CHMOD\n\thelp\n\tchmod is used to change the access permission of files.\nconfig BUSYBOX_CONFIG_CHOWN\n\tbool \"chown (7.6 kb)\"\n\tdefault BUSYBOX_DEFAULT_CHOWN\n\thelp\n\tchown is used to change the user and/or group ownership\n\tof files.\n\nconfig BUSYBOX_CONFIG_FEATURE_CHOWN_LONG_OPTIONS\n\tbool \"Enable long options\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_CHOWN_LONG_OPTIONS\n\tdepends on BUSYBOX_CONFIG_CHOWN && BUSYBOX_CONFIG_LONG_OPTS\nconfig BUSYBOX_CONFIG_CHROOT\n\tbool \"chroot (3.7 kb)\"\n\tdefault BUSYBOX_DEFAULT_CHROOT\n\thelp\n\tchroot is used to change the root directory and run a command.\n\tThe default command is '/bin/sh'.\nconfig BUSYBOX_CONFIG_CKSUM\n\tbool \"cksum (4.1 kb)\"\n\tdefault BUSYBOX_DEFAULT_CKSUM\n\nconfig BUSYBOX_CONFIG_CRC32\n\tbool \"crc32 (4.1 kb)\"\n\tdefault BUSYBOX_DEFAULT_CRC32\nconfig BUSYBOX_CONFIG_COMM\n\tbool \"comm (4.2 kb)\"\n\tdefault BUSYBOX_DEFAULT_COMM\n\thelp\n\tcomm is used to compare two files line by line and return\n\ta three-column output.\nconfig BUSYBOX_CONFIG_CP\n\tbool \"cp (10 kb)\"\n\tdefault BUSYBOX_DEFAULT_CP\n\thelp\n\tcp is used to copy files and directories.\n\nconfig BUSYBOX_CONFIG_FEATURE_CP_LONG_OPTIONS\n\tbool \"Enable long options\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_CP_LONG_OPTIONS\n\tdepends on BUSYBOX_CONFIG_CP && BUSYBOX_CONFIG_LONG_OPTS\n\thelp\n\tEnable long options.\n\tAlso add support for --parents option.\n\nconfig BUSYBOX_CONFIG_FEATURE_CP_REFLINK\n\tbool \"Enable --reflink[=auto]\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_CP_REFLINK\n\tdepends on BUSYBOX_CONFIG_FEATURE_CP_LONG_OPTIONS\nconfig BUSYBOX_CONFIG_CUT\n\tbool \"cut (5.8 kb)\"\n\tdefault BUSYBOX_DEFAULT_CUT\n\thelp\n\tcut is used to print selected parts of lines from\n\teach file to stdout.\n\nconfig BUSYBOX_CONFIG_FEATURE_CUT_REGEX\n\tbool \"cut -F\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_CUT_REGEX\n\tdepends on BUSYBOX_CONFIG_CUT\n\thelp\n\tAllow regex based delimiters.\nconfig BUSYBOX_CONFIG_DATE\n\tbool \"date (7 kb)\"\n\tdefault BUSYBOX_DEFAULT_DATE\n\thelp\n\tdate is used to set the system date or display the\n\tcurrent time in the given format.\n\nconfig BUSYBOX_CONFIG_FEATURE_DATE_ISOFMT\n\tbool \"Enable ISO date format output (-I)\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_DATE_ISOFMT\n\tdepends on BUSYBOX_CONFIG_DATE\n\thelp\n\tEnable option (-I) to output an ISO-8601 compliant\n\tdate/time string.\n\nconfig BUSYBOX_CONFIG_FEATURE_DATE_NANO\n\tbool \"Support %[num]N nanosecond format specifier\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_DATE_NANO # stat's nanosecond field is a bit non-portable\n\tdepends on BUSYBOX_CONFIG_DATE\n\thelp\n\tSupport %[num]N format specifier. Adds ~250 bytes of code.\n\nconfig BUSYBOX_CONFIG_FEATURE_DATE_COMPAT\n\tbool \"Support weird 'date MMDDhhmm[[YY]YY][.ss]' format\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_DATE_COMPAT\n\tdepends on BUSYBOX_CONFIG_DATE\n\thelp\n\tSystem time can be set by 'date -s DATE' and simply 'date DATE',\n\tbut formats of DATE string are different. 'date DATE' accepts\n\ta rather weird MMDDhhmm[[YY]YY][.ss] format with completely\n\tunnatural placement of year between minutes and seconds.\n\tdate -s (and other commands like touch -d) use more sensible\n\tformats (for one, ISO format YYYY-MM-DD hh:mm:ss.ssssss).\n\n\tWith this option off, 'date DATE' and 'date -s DATE' support\n\tthe same format. With it on, 'date DATE' additionally supports\n\tMMDDhhmm[[YY]YY][.ss] format.\nconfig BUSYBOX_CONFIG_DD\n\tbool \"dd (7.5 kb)\"\n\tdefault BUSYBOX_DEFAULT_DD\n\thelp\n\tdd copies a file (from standard input to standard output,\n\tby default) using specific input and output blocksizes,\n\twhile optionally performing conversions on it.\n\nconfig BUSYBOX_CONFIG_FEATURE_DD_SIGNAL_HANDLING\n\tbool \"Enable signal handling for status reporting\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_DD_SIGNAL_HANDLING\n\tdepends on BUSYBOX_CONFIG_DD\n\thelp\n\tSending a SIGUSR1 signal to a running 'dd' process makes it\n\tprint to standard error the number of records read and written\n\tso far, then to resume copying.\n\n\t$ dd if=/dev/zero of=/dev/null &\n\t$ pid=$!; kill -USR1 $pid; sleep 1; kill $pid\n\t10899206+0 records in\n\t10899206+0 records out\n\nconfig BUSYBOX_CONFIG_FEATURE_DD_THIRD_STATUS_LINE\n\tbool \"Enable the third status line upon signal\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_DD_THIRD_STATUS_LINE\n\tdepends on BUSYBOX_CONFIG_DD && BUSYBOX_CONFIG_FEATURE_DD_SIGNAL_HANDLING\n\thelp\n\tDisplays a coreutils-like third status line with transferred bytes,\n\telapsed time and speed.\n\nconfig BUSYBOX_CONFIG_FEATURE_DD_IBS_OBS\n\tbool \"Enable ibs, obs, iflag, oflag and conv options\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_DD_IBS_OBS\n\tdepends on BUSYBOX_CONFIG_DD\n\thelp\n\tEnable support for writing a certain number of bytes in and out,\n\tat a time, and performing conversions on the data stream.\n\nconfig BUSYBOX_CONFIG_FEATURE_DD_STATUS\n\tbool \"Enable status display options\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_DD_STATUS\n\tdepends on BUSYBOX_CONFIG_DD\n\thelp\n\tEnable support for status=noxfer/none option.\nconfig BUSYBOX_CONFIG_DF\n\tbool \"df (6.8 kb)\"\n\tdefault BUSYBOX_DEFAULT_DF\n\thelp\n\tdf reports the amount of disk space used and available\n\ton filesystems.\n\nconfig BUSYBOX_CONFIG_FEATURE_DF_FANCY\n\tbool \"Enable -a, -i, -B\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_DF_FANCY\n\tdepends on BUSYBOX_CONFIG_DF\n\thelp\n\t-a Show all filesystems\n\t-i Inodes\n\t-B <SIZE> Blocksize\n\nconfig BUSYBOX_CONFIG_FEATURE_SKIP_ROOTFS\n\tbool \"Skip rootfs in mount table\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_SKIP_ROOTFS\n\tdepends on BUSYBOX_CONFIG_DF\n\thelp\n\tIgnore rootfs entry in mount table.\n\n\tIn Linux, kernel has a special filesystem, rootfs, which is initially\n\tmounted on /. It contains initramfs data, if kernel is configured\n\tto have one. Usually, another file system is mounted over / early\n\tin boot process, and therefore most tools which manipulate\n\tmount table, such as df, will skip rootfs entry.\n\n\tHowever, some systems do not mount anything on /.\n\tIf you need to configure busybox for one of these systems,\n\tyou may find it useful to turn this option off to make df show\n\tinitramfs statistics.\n\n\tOtherwise, choose Y.\nconfig BUSYBOX_CONFIG_DIRNAME\n\tbool \"dirname (329 bytes)\"\n\tdefault BUSYBOX_DEFAULT_DIRNAME\n\thelp\n\tdirname is used to strip a non-directory suffix from\n\ta file name.\nconfig BUSYBOX_CONFIG_DOS2UNIX\n\tbool \"dos2unix (5.2 kb)\"\n\tdefault BUSYBOX_DEFAULT_DOS2UNIX\n\thelp\n\tdos2unix is used to convert a text file from DOS format to\n\tUNIX format, and vice versa.\n\nconfig BUSYBOX_CONFIG_UNIX2DOS\n\tbool \"unix2dos (5.2 kb)\"\n\tdefault BUSYBOX_DEFAULT_UNIX2DOS\n\thelp\n\tunix2dos is used to convert a text file from UNIX format to\n\tDOS format, and vice versa.\nconfig BUSYBOX_CONFIG_DU\n\tbool \"du (6.3 kb)\"\n\tdefault BUSYBOX_DEFAULT_DU\n\thelp\n\tdu is used to report the amount of disk space used\n\tfor specified files.\n\nconfig BUSYBOX_CONFIG_FEATURE_DU_DEFAULT_BLOCKSIZE_1K\n\tbool \"Use default blocksize of 1024 bytes (else it's 512 bytes)\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_DU_DEFAULT_BLOCKSIZE_1K\n\tdepends on BUSYBOX_CONFIG_DU\nconfig BUSYBOX_CONFIG_ECHO\n\tbool \"echo (1.8 kb)\"\n\tdefault BUSYBOX_DEFAULT_ECHO\n\thelp\n\techo prints a specified string to stdout.\n\n# this entry also appears in shell/Config.in, next to the echo builtin\nconfig BUSYBOX_CONFIG_FEATURE_FANCY_ECHO\n\tbool \"Enable -n and -e options\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_FANCY_ECHO\n\tdepends on BUSYBOX_CONFIG_ECHO || BUSYBOX_CONFIG_ASH_ECHO || BUSYBOX_CONFIG_HUSH_ECHO\nconfig BUSYBOX_CONFIG_ENV\n\tbool \"env (4 kb)\"\n\tdefault BUSYBOX_DEFAULT_ENV\n\thelp\n\tenv is used to set an environment variable and run\n\ta command; without options it displays the current\n\tenvironment.\nconfig BUSYBOX_CONFIG_EXPAND\n\tbool \"expand (5.1 kb)\"\n\tdefault BUSYBOX_DEFAULT_EXPAND\n\thelp\n\tBy default, convert all tabs to spaces.\n\nconfig BUSYBOX_CONFIG_UNEXPAND\n\tbool \"unexpand (5.3 kb)\"\n\tdefault BUSYBOX_DEFAULT_UNEXPAND\n\thelp\n\tBy default, convert only leading sequences of blanks to tabs.\nconfig BUSYBOX_CONFIG_EXPR\n\tbool \"expr (6.6 kb)\"\n\tdefault BUSYBOX_DEFAULT_EXPR\n\thelp\n\texpr is used to calculate numbers and print the result\n\tto standard output.\n\nconfig BUSYBOX_CONFIG_EXPR_MATH_SUPPORT_64\n\tbool \"Extend Posix numbers support to 64 bit\"\n\tdefault BUSYBOX_DEFAULT_EXPR_MATH_SUPPORT_64\n\tdepends on BUSYBOX_CONFIG_EXPR\n\thelp\n\tEnable 64-bit math support in the expr applet. This will make\n\tthe applet slightly larger, but will allow computation with very\n\tlarge numbers.\nconfig BUSYBOX_CONFIG_FACTOR\n\tbool \"factor (2.7 kb)\"\n\tdefault BUSYBOX_DEFAULT_FACTOR\n\thelp\n\tfactor factorizes integers\nconfig BUSYBOX_CONFIG_FALSE\n\tbool \"false (tiny)\"\n\tdefault BUSYBOX_DEFAULT_FALSE\n\thelp\n\tfalse returns an exit code of FALSE (1).\nconfig BUSYBOX_CONFIG_FOLD\n\tbool \"fold (4.6 kb)\"\n\tdefault BUSYBOX_DEFAULT_FOLD\n\thelp\n\tWrap text to fit a specific width.\nconfig BUSYBOX_CONFIG_HEAD\n\tbool \"head (3.8 kb)\"\n\tdefault BUSYBOX_DEFAULT_HEAD\n\thelp\n\thead is used to print the first specified number of lines\n\tfrom files.\n\nconfig BUSYBOX_CONFIG_FEATURE_FANCY_HEAD\n\tbool \"Enable -c, -q, and -v\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_FANCY_HEAD\n\tdepends on BUSYBOX_CONFIG_HEAD\nconfig BUSYBOX_CONFIG_HOSTID\n\tbool \"hostid (286 bytes)\"\n\tdefault BUSYBOX_DEFAULT_HOSTID\n\thelp\n\thostid prints the numeric identifier (in hexadecimal) for\n\tthe current host.\nconfig BUSYBOX_CONFIG_ID\n\tbool \"id (7 kb)\"\n\tdefault BUSYBOX_DEFAULT_ID\n\thelp\n\tid displays the current user and group ID names.\n\nconfig BUSYBOX_CONFIG_GROUPS\n\tbool \"groups (6.7 kb)\"\n\tdefault BUSYBOX_DEFAULT_GROUPS\n\thelp\n\tPrint the group names associated with current user id.\nconfig BUSYBOX_CONFIG_INSTALL\n\tbool \"install (12 kb)\"\n\tdefault BUSYBOX_DEFAULT_INSTALL\n\thelp\n\tCopy files and set attributes.\n\nconfig BUSYBOX_CONFIG_FEATURE_INSTALL_LONG_OPTIONS\n\tbool \"Enable long options\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_INSTALL_LONG_OPTIONS\n\tdepends on BUSYBOX_CONFIG_INSTALL && BUSYBOX_CONFIG_LONG_OPTS\nconfig BUSYBOX_CONFIG_LINK\n\tbool \"link (3.2 kb)\"\n\tdefault BUSYBOX_DEFAULT_LINK\n\thelp\n\tlink creates hard links between files.\nconfig BUSYBOX_CONFIG_LN\n\tbool \"ln (4.9 kb)\"\n\tdefault BUSYBOX_DEFAULT_LN\n\thelp\n\tln is used to create hard or soft links between files.\nconfig BUSYBOX_CONFIG_LOGNAME\n\tbool \"logname (1.1 kb)\"\n\tdefault BUSYBOX_DEFAULT_LOGNAME\n\thelp\n\tlogname is used to print the current user's login name.\nconfig BUSYBOX_CONFIG_LS\n\tbool \"ls (14 kb)\"\n\tdefault BUSYBOX_DEFAULT_LS\n\thelp\n\tls is used to list the contents of directories.\n\nconfig BUSYBOX_CONFIG_FEATURE_LS_FILETYPES\n\tbool \"Enable filetyping options (-p and -F)\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_LS_FILETYPES\n\tdepends on BUSYBOX_CONFIG_LS\n\nconfig BUSYBOX_CONFIG_FEATURE_LS_FOLLOWLINKS\n\tbool \"Enable symlinks dereferencing (-L)\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_LS_FOLLOWLINKS\n\tdepends on BUSYBOX_CONFIG_LS\n\nconfig BUSYBOX_CONFIG_FEATURE_LS_RECURSIVE\n\tbool \"Enable recursion (-R)\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_LS_RECURSIVE\n\tdepends on BUSYBOX_CONFIG_LS\n\nconfig BUSYBOX_CONFIG_FEATURE_LS_WIDTH\n\tbool \"Enable -w WIDTH and window size autodetection\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_LS_WIDTH\n\tdepends on BUSYBOX_CONFIG_LS\n\nconfig BUSYBOX_CONFIG_FEATURE_LS_SORTFILES\n\tbool \"Sort the file names\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_LS_SORTFILES\n\tdepends on BUSYBOX_CONFIG_LS\n\thelp\n\tAllow ls to sort file names alphabetically.\n\nconfig BUSYBOX_CONFIG_FEATURE_LS_TIMESTAMPS\n\tbool \"Show file timestamps\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_LS_TIMESTAMPS\n\tdepends on BUSYBOX_CONFIG_LS\n\thelp\n\tAllow ls to display timestamps for files.\n\nconfig BUSYBOX_CONFIG_FEATURE_LS_USERNAME\n\tbool \"Show username/groupnames\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_LS_USERNAME\n\tdepends on BUSYBOX_CONFIG_LS\n\thelp\n\tAllow ls to display username/groupname for files.\n\nconfig BUSYBOX_CONFIG_FEATURE_LS_COLOR\n\tbool \"Allow use of color to identify file types\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_LS_COLOR\n\tdepends on BUSYBOX_CONFIG_LS && BUSYBOX_CONFIG_LONG_OPTS\n\thelp\n\tThis enables the --color option to ls.\n\nconfig BUSYBOX_CONFIG_FEATURE_LS_COLOR_IS_DEFAULT\n\tbool \"Produce colored ls output by default\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_LS_COLOR_IS_DEFAULT\n\tdepends on BUSYBOX_CONFIG_FEATURE_LS_COLOR\n\thelp\n\tSaying yes here will turn coloring on by default,\n\teven if no \"--color\" option is given to the ls command.\n\tThis is not recommended, since the colors are not\n\tconfigurable, and the output may not be legible on\n\tmany output screens.\nconfig BUSYBOX_CONFIG_MD5SUM\n\tbool \"md5sum (6.5 kb)\"\n\tdefault BUSYBOX_DEFAULT_MD5SUM\n\thelp\n\tCompute and check MD5 message digest\n\nconfig BUSYBOX_CONFIG_SHA1SUM\n\tbool \"sha1sum (5.9 kb)\"\n\tdefault BUSYBOX_DEFAULT_SHA1SUM\n\thelp\n\tCompute and check SHA1 message digest\n\nconfig BUSYBOX_CONFIG_SHA256SUM\n\tbool \"sha256sum (7 kb)\"\n\tdefault BUSYBOX_DEFAULT_SHA256SUM\n\thelp\n\tCompute and check SHA256 message digest\n\nconfig BUSYBOX_CONFIG_SHA512SUM\n\tbool \"sha512sum (7.4 kb)\"\n\tdefault BUSYBOX_DEFAULT_SHA512SUM\n\thelp\n\tCompute and check SHA512 message digest\n\nconfig BUSYBOX_CONFIG_SHA3SUM\n\tbool \"sha3sum (6.1 kb)\"\n\tdefault BUSYBOX_DEFAULT_SHA3SUM\n\thelp\n\tCompute and check SHA3 message digest\n\ncomment \"Common options for md5sum, sha1sum, sha256sum, sha512sum, sha3sum\"\n\tdepends on BUSYBOX_CONFIG_MD5SUM || BUSYBOX_CONFIG_SHA1SUM || BUSYBOX_CONFIG_SHA256SUM || BUSYBOX_CONFIG_SHA512SUM || BUSYBOX_CONFIG_SHA3SUM\n\nconfig BUSYBOX_CONFIG_FEATURE_MD5_SHA1_SUM_CHECK\n\tbool \"Enable -c, -s and -w options\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_MD5_SHA1_SUM_CHECK\n\tdepends on BUSYBOX_CONFIG_MD5SUM || BUSYBOX_CONFIG_SHA1SUM || BUSYBOX_CONFIG_SHA256SUM || BUSYBOX_CONFIG_SHA512SUM || BUSYBOX_CONFIG_SHA3SUM\n\thelp\n\tEnabling the -c options allows files to be checked\n\tagainst pre-calculated hash values.\n\t-s and -w are useful options when verifying checksums.\nconfig BUSYBOX_CONFIG_MKDIR\n\tbool \"mkdir (4.5 kb)\"\n\tdefault BUSYBOX_DEFAULT_MKDIR\n\thelp\n\tmkdir is used to create directories with the specified names.\nconfig BUSYBOX_CONFIG_MKFIFO\n\tbool \"mkfifo (3.8 kb)\"\n\tdefault BUSYBOX_DEFAULT_MKFIFO\n\thelp\n\tmkfifo is used to create FIFOs (named pipes).\n\tThe 'mknod' program can also create FIFOs.\nconfig BUSYBOX_CONFIG_MKNOD\n\tbool \"mknod (4.5 kb)\"\n\tdefault BUSYBOX_DEFAULT_MKNOD\n\thelp\n\tmknod is used to create FIFOs or block/character special\n\tfiles with the specified names.\nconfig BUSYBOX_CONFIG_MKTEMP\n\tbool \"mktemp (4.2 kb)\"\n\tdefault BUSYBOX_DEFAULT_MKTEMP\n\thelp\n\tmktemp is used to create unique temporary files\nconfig BUSYBOX_CONFIG_MV\n\tbool \"mv (10 kb)\"\n\tdefault BUSYBOX_DEFAULT_MV\n\thelp\n\tmv is used to move or rename files or directories.\nconfig BUSYBOX_CONFIG_NICE\n\tbool \"nice (2.1 kb)\"\n\tdefault BUSYBOX_DEFAULT_NICE\n\thelp\n\tnice runs a program with modified scheduling priority.\nconfig BUSYBOX_CONFIG_NL\n\tbool \"nl (4.6 kb)\"\n\tdefault BUSYBOX_DEFAULT_NL\n\thelp\n\tnl is used to number lines of files.\nconfig BUSYBOX_CONFIG_NOHUP\n\tbool \"nohup (2 kb)\"\n\tdefault BUSYBOX_DEFAULT_NOHUP\n\thelp\n\trun a command immune to hangups, with output to a non-tty.\nconfig BUSYBOX_CONFIG_NPROC\n\tbool \"nproc (3.7 kb)\"\n\tdefault BUSYBOX_DEFAULT_NPROC\n\thelp\n\tPrint number of CPUs\nconfig BUSYBOX_CONFIG_OD\n\tbool \"od (11 kb)\"\n\tdefault BUSYBOX_DEFAULT_OD\n\thelp\n\tod is used to dump binary files in octal and other formats.\nconfig BUSYBOX_CONFIG_PASTE\n\tbool \"paste (4.9 kb)\"\n\tdefault BUSYBOX_DEFAULT_PASTE\n\thelp\n\tpaste is used to paste lines of different files together\n\tand write the result to stdout\nconfig BUSYBOX_CONFIG_PRINTENV\n\tbool \"printenv (1.3 kb)\"\n\tdefault BUSYBOX_DEFAULT_PRINTENV\n\thelp\n\tprintenv is used to print all or part of environment.\nconfig BUSYBOX_CONFIG_PRINTF\n\tbool \"printf (3.8 kb)\"\n\tdefault BUSYBOX_DEFAULT_PRINTF\n\thelp\n\tprintf is used to format and print specified strings.\n\tIt's similar to 'echo' except it has more options.\nconfig BUSYBOX_CONFIG_PWD\n\tbool \"pwd (3.7 kb)\"\n\tdefault BUSYBOX_DEFAULT_PWD\n\thelp\n\tpwd is used to print the current directory.\nconfig BUSYBOX_CONFIG_READLINK\n\tbool \"readlink (4 kb)\"\n\tdefault BUSYBOX_DEFAULT_READLINK\n\thelp\n\tThis program reads a symbolic link and returns the name\n\tof the file it points to\n\nconfig BUSYBOX_CONFIG_FEATURE_READLINK_FOLLOW\n\tbool \"Enable canonicalization by following all symlinks (-f)\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_READLINK_FOLLOW\n\tdepends on BUSYBOX_CONFIG_READLINK\n\thelp\n\tEnable the readlink option (-f).\nconfig BUSYBOX_CONFIG_REALPATH\n\tbool \"realpath (1.6 kb)\"\n\tdefault BUSYBOX_DEFAULT_REALPATH\n\thelp\n\tReturn the canonicalized absolute pathname.\n\tThis isn't provided by GNU shellutils, but where else does it belong.\nconfig BUSYBOX_CONFIG_RM\n\tbool \"rm (5.4 kb)\"\n\tdefault BUSYBOX_DEFAULT_RM\n\thelp\n\trm is used to remove files or directories.\nconfig BUSYBOX_CONFIG_RMDIR\n\tbool \"rmdir (3.5 kb)\"\n\tdefault BUSYBOX_DEFAULT_RMDIR\n\thelp\n\trmdir is used to remove empty directories.\nconfig BUSYBOX_CONFIG_SEQ\n\tbool \"seq (3.8 kb)\"\n\tdefault BUSYBOX_DEFAULT_SEQ\n\thelp\n\tprint a sequence of numbers\nconfig BUSYBOX_CONFIG_SHRED\n\tbool \"shred (4.9 kb)\"\n\tdefault BUSYBOX_DEFAULT_SHRED\n\thelp\n\tOverwrite a file to hide its contents, and optionally delete it\nconfig BUSYBOX_CONFIG_SHUF\n\tbool \"shuf (5.4 kb)\"\n\tdefault BUSYBOX_DEFAULT_SHUF\n\thelp\n\tGenerate random permutations\nconfig BUSYBOX_CONFIG_SLEEP\n\tbool \"sleep (2 kb)\"\n\tdefault BUSYBOX_DEFAULT_SLEEP\n\thelp\n\tsleep is used to pause for a specified number of seconds.\n\tIt comes in 3 versions:\n\t- small: takes one integer parameter\n\t- fancy: takes multiple integer arguments with suffixes:\n\t\tsleep 1d 2h 3m 15s\n\t- fancy with fractional numbers:\n\t\tsleep 2.3s 4.5h sleeps for 16202.3 seconds\n\tLast one is \"the most compatible\" with coreutils sleep,\n\tbut it adds around 1k of code.\n\nconfig BUSYBOX_CONFIG_FEATURE_FANCY_SLEEP\n\tbool \"Enable multiple arguments and s/m/h/d suffixes\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_FANCY_SLEEP\n\tdepends on BUSYBOX_CONFIG_SLEEP\n\thelp\n\tAllow sleep to pause for specified minutes, hours, and days.\nconfig BUSYBOX_CONFIG_SORT\n\tbool \"sort (7.7 kb)\"\n\tdefault BUSYBOX_DEFAULT_SORT\n\thelp\n\tsort is used to sort lines of text in specified files.\n\nconfig BUSYBOX_CONFIG_FEATURE_SORT_BIG\n\tbool \"Full SuSv3 compliant sort (support -ktcbdfiogM)\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_SORT_BIG\n\tdepends on BUSYBOX_CONFIG_SORT\n\thelp\n\tWithout this, sort only supports -rusz, and an integer version\n\tof -n. Selecting this adds sort keys, floating point support, and\n\tmore. This adds a little over 3k to a nonstatic build on x86.\n\n\tThe SuSv3 sort standard is available at:\n\thttp://www.opengroup.org/onlinepubs/007904975/utilities/sort.html\n\nconfig BUSYBOX_CONFIG_FEATURE_SORT_OPTIMIZE_MEMORY\n\tbool \"Use less memory (but might be slower)\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_SORT_OPTIMIZE_MEMORY   # defaults to N since we are size-paranoid tribe\n\tdepends on BUSYBOX_CONFIG_SORT\n\thelp\n\tAttempt to use less memory (by storing only one copy\n\tof duplicated lines, and such). Useful if you work on huge files.\nconfig BUSYBOX_CONFIG_SPLIT\n\tbool \"split (5 kb)\"\n\tdefault BUSYBOX_DEFAULT_SPLIT\n\thelp\n\tSplit a file into pieces.\n\nconfig BUSYBOX_CONFIG_FEATURE_SPLIT_FANCY\n\tbool \"Fancy extensions\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_SPLIT_FANCY\n\tdepends on BUSYBOX_CONFIG_SPLIT\n\thelp\n\tAdd support for features not required by SUSv3.\n\tSupports additional suffixes 'b' for 512 bytes,\n\t'g' for 1GiB for the -b option.\nconfig BUSYBOX_CONFIG_STAT\n\tbool \"stat (11 kb)\"\n\tdefault BUSYBOX_DEFAULT_STAT\n\thelp\n\tdisplay file or filesystem status.\n\nconfig BUSYBOX_CONFIG_FEATURE_STAT_FORMAT\n\tbool \"Enable custom formats (-c)\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_STAT_FORMAT\n\tdepends on BUSYBOX_CONFIG_STAT\n\thelp\n\tWithout this, stat will not support the '-c format' option where\n\tusers can pass a custom format string for output. This adds about\n\t7k to a nonstatic build on amd64.\n\nconfig BUSYBOX_CONFIG_FEATURE_STAT_FILESYSTEM\n\tbool \"Enable display of filesystem status (-f)\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_STAT_FILESYSTEM\n\tdepends on BUSYBOX_CONFIG_STAT\n\thelp\n\tWithout this, stat will not support the '-f' option to display\n\tinformation about filesystem status.\nconfig BUSYBOX_CONFIG_STTY\n\tbool \"stty (8.9 kb)\"\n\tdefault BUSYBOX_DEFAULT_STTY\n\thelp\n\tstty is used to change and print terminal line settings.\nconfig BUSYBOX_CONFIG_SUM\n\tbool \"sum (4 kb)\"\n\tdefault BUSYBOX_DEFAULT_SUM\n\thelp\n\tchecksum and count the blocks in a file\nconfig BUSYBOX_CONFIG_SYNC\n\tbool \"sync (3.8 kb)\"\n\tdefault BUSYBOX_DEFAULT_SYNC\n\thelp\n\tsync is used to flush filesystem buffers.\nconfig BUSYBOX_CONFIG_FEATURE_SYNC_FANCY\n\tbool \"Enable -d and -f flags (requires syncfs(2) in libc)\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_SYNC_FANCY\n\tdepends on BUSYBOX_CONFIG_SYNC\n\thelp\n\tsync -d FILE... executes fdatasync() on each FILE.\n\tsync -f FILE... executes syncfs() on each FILE.\nconfig BUSYBOX_CONFIG_FSYNC\n\tbool \"fsync (3.6 kb)\"\n\tdefault BUSYBOX_DEFAULT_FSYNC\n\thelp\n\tfsync is used to flush file-related cached blocks to disk.\nconfig BUSYBOX_CONFIG_TAC\n\tbool \"tac (3.9 kb)\"\n\tdefault BUSYBOX_DEFAULT_TAC\n\thelp\n\ttac is used to concatenate and print files in reverse.\nconfig BUSYBOX_CONFIG_TAIL\n\tbool \"tail (6.8 kb)\"\n\tdefault BUSYBOX_DEFAULT_TAIL\n\thelp\n\ttail is used to print the last specified number of lines\n\tfrom files.\n\nconfig BUSYBOX_CONFIG_FEATURE_FANCY_TAIL\n\tbool \"Enable -q, -s, -v, and -F options\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_FANCY_TAIL\n\tdepends on BUSYBOX_CONFIG_TAIL\n\thelp\n\tThese options are provided by GNU tail, but\n\tare not specified in the SUSv3 standard:\n\t\t-q      Never output headers giving file names\n\t\t-s SEC  Wait SEC seconds between reads with -f\n\t\t-v      Always output headers giving file names\n\t\t-F      Same as -f, but keep retrying\nconfig BUSYBOX_CONFIG_TEE\n\tbool \"tee (4.2 kb)\"\n\tdefault BUSYBOX_DEFAULT_TEE\n\thelp\n\ttee is used to read from standard input and write\n\tto standard output and files.\n\nconfig BUSYBOX_CONFIG_FEATURE_TEE_USE_BLOCK_IO\n\tbool \"Enable block I/O (larger/faster) instead of byte I/O\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_TEE_USE_BLOCK_IO\n\tdepends on BUSYBOX_CONFIG_TEE\n\thelp\n\tEnable this option for a faster tee, at expense of size.\nconfig BUSYBOX_CONFIG_TEST\n\tbool \"test (4.1 kb)\"\n\tdefault BUSYBOX_DEFAULT_TEST\n\thelp\n\ttest is used to check file types and compare values,\n\treturning an appropriate exit code. The bash shell\n\thas test built in, ash can build it in optionally.\n\nconfig BUSYBOX_CONFIG_TEST1\n\tbool \"test as [\"\n\tdefault BUSYBOX_DEFAULT_TEST1\n\thelp\n\tProvide test command in the \"[ EXPR ]\" form\n\nconfig BUSYBOX_CONFIG_TEST2\n\tbool \"test as [[\"\n\tdefault BUSYBOX_DEFAULT_TEST2\n\thelp\n\tProvide test command in the \"[[ EXPR ]]\" form\n\nconfig BUSYBOX_CONFIG_FEATURE_TEST_64\n\tbool \"Extend test to 64 bit\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_TEST_64\n\tdepends on BUSYBOX_CONFIG_TEST || BUSYBOX_CONFIG_TEST1 || BUSYBOX_CONFIG_TEST2 || BUSYBOX_CONFIG_ASH_TEST || BUSYBOX_CONFIG_HUSH_TEST\n\thelp\n\tEnable 64-bit support in test.\nconfig BUSYBOX_CONFIG_TIMEOUT\n\tbool \"timeout (6 kb)\"\n\tdefault BUSYBOX_DEFAULT_TIMEOUT\n\thelp\n\tRuns a program and watches it. If it does not terminate in\n\tspecified number of seconds, it is sent a signal.\nconfig BUSYBOX_CONFIG_TOUCH\n\tbool \"touch (5.9 kb)\"\n\tdefault BUSYBOX_DEFAULT_TOUCH\n\thelp\n\ttouch is used to create or change the access and/or\n\tmodification timestamp of specified files.\n\nconfig BUSYBOX_CONFIG_FEATURE_TOUCH_SUSV3\n\tbool \"Add support for SUSV3 features (-a -d -m -t -r)\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_TOUCH_SUSV3\n\tdepends on BUSYBOX_CONFIG_TOUCH\n\thelp\n\tEnable touch to use a reference file or a given date/time argument.\nconfig BUSYBOX_CONFIG_TR\n\tbool \"tr (5.1 kb)\"\n\tdefault BUSYBOX_DEFAULT_TR\n\thelp\n\ttr is used to squeeze, and/or delete characters from standard\n\tinput, writing to standard output.\n\nconfig BUSYBOX_CONFIG_FEATURE_TR_CLASSES\n\tbool \"Enable character classes (such as [:upper:])\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_TR_CLASSES\n\tdepends on BUSYBOX_CONFIG_TR\n\thelp\n\tEnable character classes, enabling commands such as:\n\ttr [:upper:] [:lower:] to convert input into lowercase.\n\nconfig BUSYBOX_CONFIG_FEATURE_TR_EQUIV\n\tbool \"Enable equivalence classes\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_TR_EQUIV\n\tdepends on BUSYBOX_CONFIG_TR\n\thelp\n\tEnable equivalence classes, which essentially add the enclosed\n\tcharacter to the current set. For instance, tr [=a=] xyz would\n\treplace all instances of 'a' with 'xyz'. This option is mainly\n\tuseful for cases when no other way of expressing a character\n\tis possible.\nconfig BUSYBOX_CONFIG_TRUE\n\tbool \"true (tiny)\"\n\tdefault BUSYBOX_DEFAULT_TRUE\n\thelp\n\ttrue returns an exit code of TRUE (0).\nconfig BUSYBOX_CONFIG_TRUNCATE\n\tbool \"truncate (4.2 kb)\"\n\tdefault BUSYBOX_DEFAULT_TRUNCATE\n\thelp\n\ttruncate truncates files to a given size. If a file does\n\tnot exist, it is created unless told otherwise.\nconfig BUSYBOX_CONFIG_TTY\n\tbool \"tty (3.6 kb)\"\n\tdefault BUSYBOX_DEFAULT_TTY\n\thelp\n\ttty is used to print the name of the current terminal to\n\tstandard output.\nconfig BUSYBOX_CONFIG_UNAME\n\tbool \"uname (3.9 kb)\"\n\tdefault BUSYBOX_DEFAULT_UNAME\n\thelp\n\tuname is used to print system information.\n\nconfig BUSYBOX_CONFIG_UNAME_OSNAME\n\tstring \"Operating system name\"\n\tdefault BUSYBOX_DEFAULT_UNAME_OSNAME\n\tdepends on BUSYBOX_CONFIG_UNAME\n\thelp\n\tSets the operating system name reported by uname -o.  The\n\tdefault BUSYBOX_DEFAULT_UNAME_OSNAME \"GNU/Linux\".\n\nconfig BUSYBOX_CONFIG_BB_ARCH\n\tbool \"arch (1.1 kb)\"\n\tdefault BUSYBOX_DEFAULT_BB_ARCH\n\thelp\n\tSame as uname -m.\nconfig BUSYBOX_CONFIG_UNIQ\n\tbool \"uniq (4.9 kb)\"\n\tdefault BUSYBOX_DEFAULT_UNIQ\n\thelp\n\tuniq is used to remove duplicate lines from a sorted file.\nconfig BUSYBOX_CONFIG_UNLINK\n\tbool \"unlink (3.2 kb)\"\n\tdefault BUSYBOX_DEFAULT_UNLINK\n\thelp\n\tunlink deletes a file by calling unlink()\nconfig BUSYBOX_CONFIG_USLEEP\n\tbool \"usleep (1.3 kb)\"\n\tdefault BUSYBOX_DEFAULT_USLEEP\n\thelp\n\tusleep is used to pause for a specified number of microseconds.\nconfig BUSYBOX_CONFIG_UUDECODE\n\tbool \"uudecode (5.8 kb)\"\n\tdefault BUSYBOX_DEFAULT_UUDECODE\n\thelp\n\tuudecode is used to decode a uuencoded file.\nconfig BUSYBOX_CONFIG_BASE32\n\tbool \"base32 (4.9 kb)\"\n\tdefault BUSYBOX_DEFAULT_BASE32\n\thelp\n\tBase32 encode and decode\nconfig BUSYBOX_CONFIG_BASE64\n\tbool \"base64 (4.9 kb)\"\n\tdefault BUSYBOX_DEFAULT_BASE64\n\thelp\n\tBase64 encode and decode\nconfig BUSYBOX_CONFIG_UUENCODE\n\tbool \"uuencode (4.4 kb)\"\n\tdefault BUSYBOX_DEFAULT_UUENCODE\n\thelp\n\tuuencode is used to uuencode a file.\nconfig BUSYBOX_CONFIG_WC\n\tbool \"wc (4.5 kb)\"\n\tdefault BUSYBOX_DEFAULT_WC\n\thelp\n\twc is used to print the number of bytes, words, and lines,\n\tin specified files.\n\nconfig BUSYBOX_CONFIG_FEATURE_WC_LARGE\n\tbool \"Support very large counts\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_WC_LARGE\n\tdepends on BUSYBOX_CONFIG_WC\n\thelp\n\tUse \"unsigned long long\" for counter variables.\nconfig BUSYBOX_CONFIG_WHO\n\tbool \"who (3.9 kb)\"\n\tdefault BUSYBOX_DEFAULT_WHO\n\tdepends on BUSYBOX_CONFIG_FEATURE_UTMP\n\thelp\n\tPrint users currently logged on.\n\nconfig BUSYBOX_CONFIG_W\n\tbool \"w (3.8 kb)\"\n\tdefault BUSYBOX_DEFAULT_W\n\tdepends on BUSYBOX_CONFIG_FEATURE_UTMP\n\thelp\n\tPrint users currently logged on.\n\nconfig BUSYBOX_CONFIG_USERS\n\tbool \"users (3.4 kb)\"\n\tdefault BUSYBOX_DEFAULT_USERS\n\tdepends on BUSYBOX_CONFIG_FEATURE_UTMP\n\thelp\n\tPrint users currently logged on.\nconfig BUSYBOX_CONFIG_WHOAMI\n\tbool \"whoami (3.2 kb)\"\n\tdefault BUSYBOX_DEFAULT_WHOAMI\n\thelp\n\twhoami is used to print the username of the current\n\tuser id (same as id -un).\nconfig BUSYBOX_CONFIG_YES\n\tbool \"yes (1.2 kb)\"\n\tdefault BUSYBOX_DEFAULT_YES\n\thelp\n\tyes is used to repeatedly output a specific string, or\n\tthe default string 'y'.\n\nendmenu\n"
  },
  {
    "path": "package/utils/busybox/config/debianutils/Config.in",
    "content": "# DO NOT EDIT. This file is generated from Config.src\n#\n# For a description of the syntax of this configuration file,\n# see docs/Kconfig-language.txt.\n#\n\nmenu \"Debian Utilities\"\n\nconfig BUSYBOX_CONFIG_PIPE_PROGRESS\n\tbool \"pipe_progress (275 bytes)\"\n\tdefault BUSYBOX_DEFAULT_PIPE_PROGRESS\n\thelp\n\tDisplay a dot to indicate pipe activity.\nconfig BUSYBOX_CONFIG_RUN_PARTS\n\tbool \"run-parts (6.1 kb)\"\n\tdefault BUSYBOX_DEFAULT_RUN_PARTS\n\thelp\n\trun-parts is a utility designed to run all the scripts in a directory.\n\n\tIt is useful to set up a directory like cron.daily, where you need to\n\texecute all the scripts in that directory.\n\n\tIn this implementation of run-parts some features (such as report\n\tmode) are not implemented.\n\n\tUnless you know that run-parts is used in some of your scripts\n\tyou can safely say N here.\n\nconfig BUSYBOX_CONFIG_FEATURE_RUN_PARTS_LONG_OPTIONS\n\tbool \"Enable long options\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_RUN_PARTS_LONG_OPTIONS\n\tdepends on BUSYBOX_CONFIG_RUN_PARTS && BUSYBOX_CONFIG_LONG_OPTS\n\nconfig BUSYBOX_CONFIG_FEATURE_RUN_PARTS_FANCY\n\tbool \"Support additional arguments\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_RUN_PARTS_FANCY\n\tdepends on BUSYBOX_CONFIG_RUN_PARTS\n\thelp\n\tSupport additional options:\n\t-l --list print the names of the all matching files (not\n\tlimited to executables), but don't actually run them.\nconfig BUSYBOX_CONFIG_START_STOP_DAEMON\n\tbool \"start-stop-daemon (12 kb)\"\n\tdefault BUSYBOX_DEFAULT_START_STOP_DAEMON\n\thelp\n\tstart-stop-daemon is used to control the creation and\n\ttermination of system-level processes, usually the ones\n\tstarted during the startup of the system.\n\nconfig BUSYBOX_CONFIG_FEATURE_START_STOP_DAEMON_LONG_OPTIONS\n\tbool \"Enable long options\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_START_STOP_DAEMON_LONG_OPTIONS\n\tdepends on BUSYBOX_CONFIG_START_STOP_DAEMON && BUSYBOX_CONFIG_LONG_OPTS\n\nconfig BUSYBOX_CONFIG_FEATURE_START_STOP_DAEMON_FANCY\n\tbool \"Support additional arguments\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_START_STOP_DAEMON_FANCY\n\tdepends on BUSYBOX_CONFIG_START_STOP_DAEMON\n\thelp\n\t-o|--oknodo ignored since we exit with 0 anyway\n\t-v|--verbose\n\t-N|--nicelevel N\nconfig BUSYBOX_CONFIG_WHICH\n\tbool \"which (3.8 kb)\"\n\tdefault BUSYBOX_DEFAULT_WHICH\n\thelp\n\twhich is used to find programs in your PATH and\n\tprint out their pathnames.\n\nendmenu\n"
  },
  {
    "path": "package/utils/busybox/config/e2fsprogs/Config.in",
    "content": "# DO NOT EDIT. This file is generated from Config.src\n#\n# For a description of the syntax of this configuration file,\n# see docs/Kconfig-language.txt.\n#\n\nmenu \"Linux Ext2 FS Progs\"\n\nconfig BUSYBOX_CONFIG_CHATTR\n\tbool \"chattr (3.8 kb)\"\n\tdefault BUSYBOX_DEFAULT_CHATTR\n\thelp\n\tchattr changes the file attributes on a second extended file system.\nconfig BUSYBOX_CONFIG_FSCK\n\tbool \"fsck (7.4 kb)\"\n\tdefault BUSYBOX_DEFAULT_FSCK\n\thelp\n\tfsck is used to check and optionally repair one or more filesystems.\n\tIn actuality, fsck is simply a front-end for the various file system\n\tcheckers (fsck.fstype) available under Linux.\nconfig BUSYBOX_CONFIG_LSATTR\n\tbool \"lsattr (5.5 kb)\"\n\tdefault BUSYBOX_DEFAULT_LSATTR\n\thelp\n\tlsattr lists the file attributes on a second extended file system.\nconfig BUSYBOX_CONFIG_TUNE2FS\n\tbool \"tune2fs (4.4 kb)\"\n\tdefault BUSYBOX_DEFAULT_TUNE2FS  # off: it is too limited compared to upstream version\n\thelp\n\ttune2fs allows the system administrator to adjust various tunable\n\tfilesystem parameters on Linux ext2/ext3 filesystems.\n\n### config E2FSCK\n###\tbool \"e2fsck\"\n###\tdefault y\n###\thelp\n###\t  e2fsck is used to check Linux second extended file systems (ext2fs).\n###\t  e2fsck also supports ext2 filesystems countaining a journal (ext3).\n###\t  The normal compat symlinks 'fsck.ext2' and 'fsck.ext3' are also\n###\t  provided.\n\n### config MKE2FS\n###\tbool \"mke2fs\"\n###\tdefault y\n###\thelp\n###\t  mke2fs is used to create an ext2/ext3 filesystem. The normal compat\n###\t  symlinks 'mkfs.ext2' and 'mkfs.ext3' are also provided.\n\n### config E2LABEL\n###\tbool \"e2label\"\n###\tdefault y\n###\tdepends on TUNE2FS\n###\thelp\n###\t  e2label will display or change the filesystem label on the ext2\n###\t  filesystem located on device.\n\n### NB: this one is now provided by util-linux/volume_id/*\n### config FINDFS\n###\tbool \"findfs\"\n###\tdefault y\n###\tdepends on TUNE2FS\n###\thelp\n###\t  findfs will search the disks in the system looking for a filesystem\n###\t  which has a label matching label or a UUID equal to uuid.\n\nendmenu\n"
  },
  {
    "path": "package/utils/busybox/config/e2fsprogs/old_e2fsprogs/Config.in",
    "content": "# DO NOT EDIT. This file is generated from Config.src\n#\n# For a description of the syntax of this configuration file,\n# see scripts/kbuild/config-language.txt.\n#\n\nmenu \"Linux Ext2 FS Progs\"\n\n\nconfig BUSYBOX_CONFIG_CHATTR\n\tbool \"chattr\"\n\tdefault BUSYBOX_DEFAULT_CHATTR\n\thelp\n\tchattr changes the file attributes on a second extended file system.\n\nconfig BUSYBOX_CONFIG_E2FSCK\n\tbool \"e2fsck\"\n\tdefault BUSYBOX_DEFAULT_E2FSCK\n\thelp\n\te2fsck is used to check Linux second extended file systems (ext2fs).\n\te2fsck also supports ext2 filesystems countaining a journal (ext3).\n\tThe normal compat symlinks 'fsck.ext2' and 'fsck.ext3' are also\n\tprovided.\n\nconfig BUSYBOX_CONFIG_FSCK\n\tbool \"fsck\"\n\tdefault BUSYBOX_DEFAULT_FSCK\n\thelp\n\tfsck is used to check and optionally repair one or more filesystems.\n\tIn actuality, fsck is simply a front-end for the various file system\n\tcheckers (fsck.fstype) available under Linux.\n\nconfig BUSYBOX_CONFIG_LSATTR\n\tbool \"lsattr\"\n\tdefault BUSYBOX_DEFAULT_LSATTR\n\thelp\n\tlsattr lists the file attributes on a second extended file system.\n\nconfig BUSYBOX_CONFIG_MKE2FS\n\tbool \"mke2fs\"\n\tdefault BUSYBOX_DEFAULT_MKE2FS\n\thelp\n\tmke2fs is used to create an ext2/ext3 filesystem. The normal compat\n\tsymlinks 'mkfs.ext2' and 'mkfs.ext3' are also provided.\n\nconfig BUSYBOX_CONFIG_TUNE2FS\n\tbool \"tune2fs\"\n\tdefault BUSYBOX_DEFAULT_TUNE2FS\n\thelp\n\ttune2fs allows the system administrator to adjust various tunable\n\tfilesystem parameters on Linux ext2/ext3 filesystems.\n\nconfig BUSYBOX_CONFIG_E2LABEL\n\tbool \"e2label\"\n\tdefault BUSYBOX_DEFAULT_E2LABEL\n\tdepends on BUSYBOX_CONFIG_TUNE2FS\n\thelp\n\te2label will display or change the filesystem label on the ext2\n\tfilesystem located on device.\n\nconfig BUSYBOX_CONFIG_FINDFS\n\tbool \"findfs\"\n\tdefault BUSYBOX_DEFAULT_FINDFS\n\tdepends on BUSYBOX_CONFIG_TUNE2FS\n\thelp\n\tfindfs will search the disks in the system looking for a filesystem\n\twhich has a label matching label or a UUID equal to uuid.\n\nendmenu\n"
  },
  {
    "path": "package/utils/busybox/config/editors/Config.in",
    "content": "# DO NOT EDIT. This file is generated from Config.src\n#\n# For a description of the syntax of this configuration file,\n# see docs/Kconfig-language.txt.\n#\n\nmenu \"Editors\"\n\nconfig BUSYBOX_CONFIG_AWK\n\tbool \"awk (23 kb)\"\n\tdefault BUSYBOX_DEFAULT_AWK\n\thelp\n\tAwk is used as a pattern scanning and processing language.\n\nconfig BUSYBOX_CONFIG_FEATURE_AWK_LIBM\n\tbool \"Enable math functions (requires libm)\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_AWK_LIBM\n\tdepends on BUSYBOX_CONFIG_AWK\n\thelp\n\tEnable math functions of the Awk programming language.\n\tNOTE: This requires libm to be present for linking.\n\nconfig BUSYBOX_CONFIG_FEATURE_AWK_GNU_EXTENSIONS\n\tbool \"Enable a few GNU extensions\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_AWK_GNU_EXTENSIONS\n\tdepends on BUSYBOX_CONFIG_AWK\n\thelp\n\tEnable a few features from gawk:\n\t* command line option -e AWK_PROGRAM\n\t* simultaneous use of -f and -e on the command line.\n\tThis enables the use of awk library files.\n\tExample: awk -f mylib.awk -e '{print myfunction($1);}' ...\nconfig BUSYBOX_CONFIG_CMP\n\tbool \"cmp (4.9 kb)\"\n\tdefault BUSYBOX_DEFAULT_CMP\n\thelp\n\tcmp is used to compare two files and returns the result\n\tto standard output.\nconfig BUSYBOX_CONFIG_DIFF\n\tbool \"diff (13 kb)\"\n\tdefault BUSYBOX_DEFAULT_DIFF\n\thelp\n\tdiff compares two files or directories and outputs the\n\tdifferences between them in a form that can be given to\n\tthe patch command.\n\nconfig BUSYBOX_CONFIG_FEATURE_DIFF_LONG_OPTIONS\n\tbool \"Enable long options\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_DIFF_LONG_OPTIONS\n\tdepends on BUSYBOX_CONFIG_DIFF && BUSYBOX_CONFIG_LONG_OPTS\n\nconfig BUSYBOX_CONFIG_FEATURE_DIFF_DIR\n\tbool \"Enable directory support\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_DIFF_DIR\n\tdepends on BUSYBOX_CONFIG_DIFF\n\thelp\n\tThis option enables support for directory and subdirectory\n\tcomparison.\nconfig BUSYBOX_CONFIG_ED\n\tbool \"ed (21 kb)\"\n\tdefault BUSYBOX_DEFAULT_ED\n\thelp\n\tThe original 1970's Unix text editor, from the days of teletypes.\n\tSmall, simple, evil. Part of SUSv3. If you're not already using\n\tthis, you don't need it.\nconfig BUSYBOX_CONFIG_PATCH\n\tbool \"patch (9.4 kb)\"\n\tdefault BUSYBOX_DEFAULT_PATCH\n\thelp\n\tApply a unified diff formatted patch.\nconfig BUSYBOX_CONFIG_SED\n\tbool \"sed (12 kb)\"\n\tdefault BUSYBOX_DEFAULT_SED\n\thelp\n\tsed is used to perform text transformations on a file\n\tor input from a pipeline.\nconfig BUSYBOX_CONFIG_VI\n\tbool \"vi (23 kb)\"\n\tdefault BUSYBOX_DEFAULT_VI\n\thelp\n\t'vi' is a text editor. More specifically, it is the One True\n\ttext editor <grin>. It does, however, have a rather steep\n\tlearning curve. If you are not already comfortable with 'vi'\n\tyou may wish to use something else.\n\nconfig BUSYBOX_CONFIG_FEATURE_VI_MAX_LEN\n\tint \"Maximum screen width\"\n\trange 256 16384\n\tdefault BUSYBOX_DEFAULT_FEATURE_VI_MAX_LEN\n\tdepends on BUSYBOX_CONFIG_VI\n\thelp\n\tContrary to what you may think, this is not eating much.\n\tMake it smaller than 4k only if you are very limited on memory.\n\nconfig BUSYBOX_CONFIG_FEATURE_VI_8BIT\n\tbool \"Allow to display 8-bit chars (otherwise shows dots)\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_VI_8BIT\n\tdepends on BUSYBOX_CONFIG_VI\n\thelp\n\tIf your terminal can display characters with high bit set,\n\tyou may want to enable this. Note: vi is not Unicode-capable.\n\tIf your terminal combines several 8-bit bytes into one character\n\t(as in Unicode mode), this will not work properly.\n\nconfig BUSYBOX_CONFIG_FEATURE_VI_COLON\n\tbool \"Enable \\\":\\\" colon commands (no \\\"ex\\\" mode)\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_VI_COLON\n\tdepends on BUSYBOX_CONFIG_VI\n\thelp\n\tEnable a limited set of colon commands. This does not\n\tprovide an \"ex\" mode.\n\nconfig BUSYBOX_CONFIG_FEATURE_VI_COLON_EXPAND\n\tbool \"Expand \\\"%\\\" and \\\"#\\\" in colon commands\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_VI_COLON_EXPAND\n\tdepends on BUSYBOX_CONFIG_FEATURE_VI_COLON\n\thelp\n\tExpand the special characters \\\"%\\\" (current filename)\n\tand \\\"#\\\" (alternate filename) in colon commands.\n\nconfig BUSYBOX_CONFIG_FEATURE_VI_YANKMARK\n\tbool \"Enable yank/put commands and mark cmds\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_VI_YANKMARK\n\tdepends on BUSYBOX_CONFIG_VI\n\thelp\n\tThis enables you to use yank and put, as well as mark.\n\nconfig BUSYBOX_CONFIG_FEATURE_VI_SEARCH\n\tbool \"Enable search and replace cmds\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_VI_SEARCH\n\tdepends on BUSYBOX_CONFIG_VI\n\thelp\n\tSelect this if you wish to be able to do search and replace.\n\nconfig BUSYBOX_CONFIG_FEATURE_VI_REGEX_SEARCH\n\tbool \"Enable regex in search and replace\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_VI_REGEX_SEARCH   # Uses GNU regex, which may be unavailable. FIXME\n\tdepends on BUSYBOX_CONFIG_FEATURE_VI_SEARCH\n\tdepends on USE_GLIBC\n\thelp\n\tUse extended regex search.\n\nconfig BUSYBOX_CONFIG_FEATURE_VI_USE_SIGNALS\n\tbool \"Catch signals\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_VI_USE_SIGNALS\n\tdepends on BUSYBOX_CONFIG_VI\n\thelp\n\tSelecting this option will make vi signal aware. This will support\n\tSIGWINCH to deal with Window Changes, catch ^Z and ^C and alarms.\n\nconfig BUSYBOX_CONFIG_FEATURE_VI_DOT_CMD\n\tbool \"Remember previous cmd and \\\".\\\" cmd\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_VI_DOT_CMD\n\tdepends on BUSYBOX_CONFIG_VI\n\thelp\n\tMake vi remember the last command and be able to repeat it.\n\nconfig BUSYBOX_CONFIG_FEATURE_VI_READONLY\n\tbool \"Enable -R option and \\\"view\\\" mode\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_VI_READONLY\n\tdepends on BUSYBOX_CONFIG_VI\n\thelp\n\tEnable the read-only command line option, which allows the user to\n\topen a file in read-only mode.\n\nconfig BUSYBOX_CONFIG_FEATURE_VI_SETOPTS\n\tbool \"Enable settable options, ai ic showmatch\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_VI_SETOPTS\n\tdepends on BUSYBOX_CONFIG_VI\n\thelp\n\tEnable the editor to set some (ai, ic, showmatch) options.\n\nconfig BUSYBOX_CONFIG_FEATURE_VI_SET\n\tbool \"Support :set\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_VI_SET\n\tdepends on BUSYBOX_CONFIG_VI\n\nconfig BUSYBOX_CONFIG_FEATURE_VI_WIN_RESIZE\n\tbool \"Handle window resize\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_VI_WIN_RESIZE\n\tdepends on BUSYBOX_CONFIG_VI\n\thelp\n\tBehave nicely with terminals that get resized.\n\nconfig BUSYBOX_CONFIG_FEATURE_VI_ASK_TERMINAL\n\tbool \"Use 'tell me cursor position' ESC sequence to measure window\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_VI_ASK_TERMINAL\n\tdepends on BUSYBOX_CONFIG_VI\n\thelp\n\tIf terminal size can't be retrieved and $LINES/$COLUMNS are not set,\n\tthis option makes vi perform a last-ditch effort to find it:\n\tposition cursor to 999,999 and ask terminal to report real\n\tcursor position using \"ESC [ 6 n\" escape sequence, then read stdin.\n\tThis is not clean but helps a lot on serial lines and such.\n\nconfig BUSYBOX_CONFIG_FEATURE_VI_UNDO\n\tbool \"Support undo command \\\"u\\\"\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_VI_UNDO\n\tdepends on BUSYBOX_CONFIG_VI\n\thelp\n\tSupport the 'u' command to undo insertion, deletion, and replacement\n\tof text.\n\nconfig BUSYBOX_CONFIG_FEATURE_VI_UNDO_QUEUE\n\tbool \"Enable undo operation queuing\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_VI_UNDO_QUEUE\n\tdepends on BUSYBOX_CONFIG_FEATURE_VI_UNDO\n\thelp\n\tThe vi undo functions can use an intermediate queue to greatly lower\n\tmalloc() calls and overhead. When the maximum size of this queue is\n\treached, the contents of the queue are committed to the undo stack.\n\tThis increases the size of the undo code and allows some undo\n\toperations (especially un-typing/backspacing) to be far more useful.\n\nconfig BUSYBOX_CONFIG_FEATURE_VI_UNDO_QUEUE_MAX\n\tint \"Maximum undo character queue size\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_VI_UNDO_QUEUE_MAX\n\trange 32 65536\n\tdepends on BUSYBOX_CONFIG_FEATURE_VI_UNDO_QUEUE\n\thelp\n\tThis option sets the number of bytes used at runtime for the queue.\n\tSmaller values will create more undo objects and reduce the amount\n\tof typed or backspaced characters that are grouped into one undo\n\toperation; larger values increase the potential size of each undo\n\tand will generally malloc() larger objects and less frequently.\n\tUnless you want more (or less) frequent \"undo points\" while typing,\n\tyou should probably leave this unchanged.\n\nconfig BUSYBOX_CONFIG_FEATURE_VI_VERBOSE_STATUS\n\tbool \"Enable verbose status reporting\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_VI_VERBOSE_STATUS\n\tdepends on BUSYBOX_CONFIG_VI\n\thelp\n\tEnable more verbose reporting of the results of yank, change,\n\tdelete, undo and substitution commands.\n\nconfig BUSYBOX_CONFIG_FEATURE_ALLOW_EXEC\n\tbool \"Allow vi and awk to execute shell commands\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_ALLOW_EXEC\n\tdepends on BUSYBOX_CONFIG_VI || BUSYBOX_CONFIG_AWK\n\thelp\n\tEnables vi and awk features which allow user to execute\n\tshell commands (using system() C call).\n\nendmenu\n"
  },
  {
    "path": "package/utils/busybox/config/findutils/Config.in",
    "content": "# DO NOT EDIT. This file is generated from Config.src\n#\n# For a description of the syntax of this configuration file,\n# see docs/Kconfig-language.txt.\n#\n\nmenu \"Finding Utilities\"\n\nconfig BUSYBOX_CONFIG_FIND\n\tbool \"find (14 kb)\"\n\tdefault BUSYBOX_DEFAULT_FIND\n\thelp\n\tfind is used to search your system to find specified files.\n\nconfig BUSYBOX_CONFIG_FEATURE_FIND_PRINT0\n\tbool \"Enable -print0: NUL-terminated output\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_FIND_PRINT0\n\tdepends on BUSYBOX_CONFIG_FIND\n\thelp\n\tCauses output names to be separated by a NUL character\n\trather than a newline. This allows names that contain\n\tnewlines and other whitespace to be more easily\n\tinterpreted by other programs.\n\nconfig BUSYBOX_CONFIG_FEATURE_FIND_MTIME\n\tbool \"Enable -mtime: modification time matching\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_FIND_MTIME\n\tdepends on BUSYBOX_CONFIG_FIND\n\thelp\n\tAllow searching based on the modification time of\n\tfiles, in days.\n\nconfig BUSYBOX_CONFIG_FEATURE_FIND_ATIME\n\tbool \"Enable -atime: access time matching\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_FIND_ATIME\n\tdepends on BUSYBOX_CONFIG_FEATURE_FIND_MTIME\n\thelp\n\tAllow searching based on the access time of\n\tfiles, in days.\n\nconfig BUSYBOX_CONFIG_FEATURE_FIND_CTIME\n\tbool \"Enable -ctime: status change timestamp matching\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_FIND_CTIME\n\tdepends on BUSYBOX_CONFIG_FEATURE_FIND_MTIME\n\thelp\n\tAllow searching based on the status change timestamp of\n\tfiles, in days.\n\nconfig BUSYBOX_CONFIG_FEATURE_FIND_MMIN\n\tbool \"Enable -mmin: modification time matching by minutes\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_FIND_MMIN\n\tdepends on BUSYBOX_CONFIG_FIND\n\thelp\n\tAllow searching based on the modification time of\n\tfiles, in minutes.\n\nconfig BUSYBOX_CONFIG_FEATURE_FIND_AMIN\n\tbool \"Enable -amin: access time matching by minutes\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_FIND_AMIN\n\tdepends on BUSYBOX_CONFIG_FEATURE_FIND_MMIN\n\thelp\n\tAllow searching based on the access time of\n\tfiles, in minutes.\n\nconfig BUSYBOX_CONFIG_FEATURE_FIND_CMIN\n\tbool \"Enable -cmin: status change timestamp matching by minutes\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_FIND_CMIN\n\tdepends on BUSYBOX_CONFIG_FEATURE_FIND_MMIN\n\thelp\n\tAllow searching based on the status change timestamp of\n\tfiles, in minutes.\n\nconfig BUSYBOX_CONFIG_FEATURE_FIND_PERM\n\tbool \"Enable -perm: permissions matching\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_FIND_PERM\n\tdepends on BUSYBOX_CONFIG_FIND\n\nconfig BUSYBOX_CONFIG_FEATURE_FIND_TYPE\n\tbool \"Enable -type: file type matching (file/dir/link/...)\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_FIND_TYPE\n\tdepends on BUSYBOX_CONFIG_FIND\n\thelp\n\tEnable searching based on file type (file,\n\tdirectory, socket, device, etc.).\n\nconfig BUSYBOX_CONFIG_FEATURE_FIND_EXECUTABLE\n\tbool \"Enable -executable: file is executable\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_FIND_EXECUTABLE\n\tdepends on BUSYBOX_CONFIG_FIND\n\nconfig BUSYBOX_CONFIG_FEATURE_FIND_XDEV\n\tbool \"Enable -xdev: 'stay in filesystem'\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_FIND_XDEV\n\tdepends on BUSYBOX_CONFIG_FIND\n\nconfig BUSYBOX_CONFIG_FEATURE_FIND_MAXDEPTH\n\tbool \"Enable -mindepth N and -maxdepth N\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_FIND_MAXDEPTH\n\tdepends on BUSYBOX_CONFIG_FIND\n\nconfig BUSYBOX_CONFIG_FEATURE_FIND_NEWER\n\tbool \"Enable -newer: compare file modification times\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_FIND_NEWER\n\tdepends on BUSYBOX_CONFIG_FIND\n\thelp\n\tSupport the 'find -newer' option for finding any files which have\n\tmodification time that is more recent than the specified FILE.\n\nconfig BUSYBOX_CONFIG_FEATURE_FIND_INUM\n\tbool \"Enable -inum: inode number matching\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_FIND_INUM\n\tdepends on BUSYBOX_CONFIG_FIND\n\nconfig BUSYBOX_CONFIG_FEATURE_FIND_SAMEFILE\n\tbool \"Enable -samefile: reference file matching\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_FIND_SAMEFILE\n\tdepends on BUSYBOX_CONFIG_FIND\n\thelp\n\tSupport the 'find -samefile' option for searching by a reference file.\n\nconfig BUSYBOX_CONFIG_FEATURE_FIND_EXEC\n\tbool \"Enable -exec: execute commands\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_FIND_EXEC\n\tdepends on BUSYBOX_CONFIG_FIND\n\thelp\n\tSupport the 'find -exec' option for executing commands based upon\n\tthe files matched.\n\nconfig BUSYBOX_CONFIG_FEATURE_FIND_EXEC_PLUS\n\tbool \"Enable -exec ... {} +\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_FIND_EXEC_PLUS\n\tdepends on BUSYBOX_CONFIG_FEATURE_FIND_EXEC\n\thelp\n\tSupport the 'find -exec ... {} +' option for executing commands\n\tfor all matched files at once.\n\tWithout this option, -exec + is a synonym for -exec ;\n\t(IOW: it works correctly, but without expected speedup)\n\nconfig BUSYBOX_CONFIG_FEATURE_FIND_USER\n\tbool \"Enable -user: username/uid matching\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_FIND_USER\n\tdepends on BUSYBOX_CONFIG_FIND\n\nconfig BUSYBOX_CONFIG_FEATURE_FIND_GROUP\n\tbool \"Enable -group: group/gid matching\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_FIND_GROUP\n\tdepends on BUSYBOX_CONFIG_FIND\n\nconfig BUSYBOX_CONFIG_FEATURE_FIND_NOT\n\tbool \"Enable the 'not' (!) operator\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_FIND_NOT\n\tdepends on BUSYBOX_CONFIG_FIND\n\thelp\n\tSupport the '!' operator to invert the test results.\n\tIf 'Enable full-blown desktop' is enabled, then will also support\n\tthe non-POSIX notation '-not'.\n\nconfig BUSYBOX_CONFIG_FEATURE_FIND_DEPTH\n\tbool \"Enable -depth\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_FIND_DEPTH\n\tdepends on BUSYBOX_CONFIG_FIND\n\thelp\n\tProcess each directory's contents before the directory itself.\n\nconfig BUSYBOX_CONFIG_FEATURE_FIND_PAREN\n\tbool \"Enable parens in options\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_FIND_PAREN\n\tdepends on BUSYBOX_CONFIG_FIND\n\thelp\n\tEnable usage of parens '(' to specify logical order of arguments.\n\nconfig BUSYBOX_CONFIG_FEATURE_FIND_SIZE\n\tbool \"Enable -size: file size matching\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_FIND_SIZE\n\tdepends on BUSYBOX_CONFIG_FIND\n\nconfig BUSYBOX_CONFIG_FEATURE_FIND_PRUNE\n\tbool \"Enable -prune: exclude subdirectories\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_FIND_PRUNE\n\tdepends on BUSYBOX_CONFIG_FIND\n\thelp\n\tIf the file is a directory, don't descend into it. Useful for\n\texclusion .svn and CVS directories.\n\nconfig BUSYBOX_CONFIG_FEATURE_FIND_QUIT\n\tbool \"Enable -quit: exit\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_FIND_QUIT\n\tdepends on BUSYBOX_CONFIG_FIND\n\thelp\n\tIf this action is reached, 'find' exits.\n\nconfig BUSYBOX_CONFIG_FEATURE_FIND_DELETE\n\tbool \"Enable -delete: delete files/dirs\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_FIND_DELETE\n\tdepends on BUSYBOX_CONFIG_FIND && BUSYBOX_CONFIG_FEATURE_FIND_DEPTH\n\thelp\n\tSupport the 'find -delete' option for deleting files and directories.\n\tWARNING: This option can do much harm if used wrong. Busybox will not\n\ttry to protect the user from doing stupid things. Use with care.\n\nconfig BUSYBOX_CONFIG_FEATURE_FIND_EMPTY\n\tbool \"Enable -empty: match empty files or directories\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_FIND_EMPTY\n\tdepends on BUSYBOX_CONFIG_FIND\n\thelp\n\tSupport the 'find -empty' option to find empty regular files\n\tor directories.\n\nconfig BUSYBOX_CONFIG_FEATURE_FIND_PATH\n\tbool \"Enable -path: match pathname with shell pattern\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_FIND_PATH\n\tdepends on BUSYBOX_CONFIG_FIND\n\thelp\n\tThe -path option matches whole pathname instead of just filename.\n\nconfig BUSYBOX_CONFIG_FEATURE_FIND_REGEX\n\tbool \"Enable -regex: match pathname with regex\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_FIND_REGEX\n\tdepends on BUSYBOX_CONFIG_FIND\n\thelp\n\tThe -regex option matches whole pathname against regular expression.\n\nconfig BUSYBOX_CONFIG_FEATURE_FIND_CONTEXT\n\tbool \"Enable -context: security context matching\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_FIND_CONTEXT\n\tdepends on BUSYBOX_CONFIG_FIND && BUSYBOX_CONFIG_SELINUX\n\thelp\n\tSupport the 'find -context' option for matching security context.\n\nconfig BUSYBOX_CONFIG_FEATURE_FIND_LINKS\n\tbool \"Enable -links: link count matching\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_FIND_LINKS\n\tdepends on BUSYBOX_CONFIG_FIND\n\thelp\n\tSupport the 'find -links' option for matching number of links.\nconfig BUSYBOX_CONFIG_GREP\n\tbool \"grep (8.6 kb)\"\n\tdefault BUSYBOX_DEFAULT_GREP\n\thelp\n\tgrep is used to search files for a specified pattern.\n\nconfig BUSYBOX_CONFIG_EGREP\n\tbool \"egrep (7.8 kb)\"\n\tdefault BUSYBOX_DEFAULT_EGREP\n\thelp\n\tAlias to \"grep -E\".\n\nconfig BUSYBOX_CONFIG_FGREP\n\tbool \"fgrep (7.8 kb)\"\n\tdefault BUSYBOX_DEFAULT_FGREP\n\thelp\n\tAlias to \"grep -F\".\n\nconfig BUSYBOX_CONFIG_FEATURE_GREP_CONTEXT\n\tbool \"Enable before and after context flags (-A, -B and -C)\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_GREP_CONTEXT\n\tdepends on BUSYBOX_CONFIG_GREP || BUSYBOX_CONFIG_EGREP || BUSYBOX_CONFIG_FGREP\n\thelp\n\tPrint the specified number of leading (-B) and/or trailing (-A)\n\tcontext surrounding our matching lines.\n\tPrint the specified number of context lines (-C).\nconfig BUSYBOX_CONFIG_XARGS\n\tbool \"xargs (7.2 kb)\"\n\tdefault BUSYBOX_DEFAULT_XARGS\n\thelp\n\txargs is used to execute a specified command for\n\tevery item from standard input.\n\nconfig BUSYBOX_CONFIG_FEATURE_XARGS_SUPPORT_CONFIRMATION\n\tbool \"Enable -p: prompt and confirmation\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_XARGS_SUPPORT_CONFIRMATION\n\tdepends on BUSYBOX_CONFIG_XARGS\n\thelp\n\tSupport -p: prompt the user whether to run each command\n\tline and read a line from the terminal.\n\nconfig BUSYBOX_CONFIG_FEATURE_XARGS_SUPPORT_QUOTES\n\tbool \"Enable single and double quotes and backslash\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_XARGS_SUPPORT_QUOTES\n\tdepends on BUSYBOX_CONFIG_XARGS\n\thelp\n\tSupport quoting in the input.\n\nconfig BUSYBOX_CONFIG_FEATURE_XARGS_SUPPORT_TERMOPT\n\tbool \"Enable -x: exit if -s or -n is exceeded\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_XARGS_SUPPORT_TERMOPT\n\tdepends on BUSYBOX_CONFIG_XARGS\n\thelp\n\tSupport -x: exit if the command size (see the -s or -n option)\n\tis exceeded.\n\nconfig BUSYBOX_CONFIG_FEATURE_XARGS_SUPPORT_ZERO_TERM\n\tbool \"Enable -0: NUL-terminated input\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_XARGS_SUPPORT_ZERO_TERM\n\tdepends on BUSYBOX_CONFIG_XARGS\n\thelp\n\tSupport -0: input items are terminated by a NUL character\n\tinstead of whitespace, and the quotes and backslash\n\tare not special.\n\nconfig BUSYBOX_CONFIG_FEATURE_XARGS_SUPPORT_REPL_STR\n\tbool \"Enable -I STR: string to replace\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_XARGS_SUPPORT_REPL_STR\n\tdepends on BUSYBOX_CONFIG_XARGS\n\thelp\n\tSupport -I STR and -i[STR] options.\n\nconfig BUSYBOX_CONFIG_FEATURE_XARGS_SUPPORT_PARALLEL\n\tbool \"Enable -P N: processes to run in parallel\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_XARGS_SUPPORT_PARALLEL\n\tdepends on BUSYBOX_CONFIG_XARGS\n\nconfig BUSYBOX_CONFIG_FEATURE_XARGS_SUPPORT_ARGS_FILE\n\tbool \"Enable -a FILE: use FILE instead of stdin\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_XARGS_SUPPORT_ARGS_FILE\n\tdepends on BUSYBOX_CONFIG_XARGS\n\nendmenu\n"
  },
  {
    "path": "package/utils/busybox/config/init/Config.in",
    "content": "# DO NOT EDIT. This file is generated from Config.src\n#\n# For a description of the syntax of this configuration file,\n# see docs/Kconfig-language.txt.\n#\n\nmenu \"Init Utilities\"\n\nconfig BUSYBOX_CONFIG_BOOTCHARTD\n\tbool \"bootchartd (10 kb)\"\n\tdefault BUSYBOX_DEFAULT_BOOTCHARTD\n\thelp\n\tbootchartd is commonly used to profile the boot process\n\tfor the purpose of speeding it up. In this case, it is started\n\tby the kernel as the init process. This is configured by adding\n\tthe init=/sbin/bootchartd option to the kernel command line.\n\n\tIt can also be used to monitor the resource usage of a specific\n\tapplication or the running system in general. In this case,\n\tbootchartd is started interactively by running bootchartd start\n\tand stopped using bootchartd stop.\n\nconfig BUSYBOX_CONFIG_FEATURE_BOOTCHARTD_BLOATED_HEADER\n\tbool \"Compatible, bloated header\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_BOOTCHARTD_BLOATED_HEADER\n\tdepends on BUSYBOX_CONFIG_BOOTCHARTD\n\thelp\n\tCreate extended header file compatible with \"big\" bootchartd.\n\t\"Big\" bootchartd is a shell script and it dumps some\n\t\"convenient\" info into the header, such as:\n\t\ttitle = Boot chart for `hostname` (`date`)\n\t\tsystem.uname = `uname -srvm`\n\t\tsystem.release = `cat /etc/DISTRO-release`\n\t\tsystem.cpu = `grep '^model name' /proc/cpuinfo | head -1` ($cpucount)\n\t\tsystem.kernel.options = `cat /proc/cmdline`\n\tThis data is not mandatory for bootchart graph generation,\n\tand is considered bloat. Nevertheless, this option\n\tmakes bootchartd applet to dump a subset of it.\n\nconfig BUSYBOX_CONFIG_FEATURE_BOOTCHARTD_CONFIG_FILE\n\tbool \"Support bootchartd.conf\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_BOOTCHARTD_CONFIG_FILE\n\tdepends on BUSYBOX_CONFIG_BOOTCHARTD\n\thelp\n\tEnable reading and parsing of $PWD/bootchartd.conf\n\tand /etc/bootchartd.conf files.\nconfig BUSYBOX_CONFIG_HALT\n\tbool \"halt (4 kb)\"\n\tdefault BUSYBOX_DEFAULT_HALT\n\thelp\n\tStop all processes and halt the system.\n\nconfig BUSYBOX_CONFIG_POWEROFF\n\tbool \"poweroff (4 kb)\"\n\tdefault BUSYBOX_DEFAULT_POWEROFF\n\thelp\n\tStop all processes and power off the system.\n\nconfig BUSYBOX_CONFIG_REBOOT\n\tbool \"reboot (4 kb)\"\n\tdefault BUSYBOX_DEFAULT_REBOOT\n\thelp\n\tStop all processes and reboot the system.\n\nconfig BUSYBOX_CONFIG_FEATURE_WAIT_FOR_INIT\n\tbool \"Before signaling init, make sure it is ready for it\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_WAIT_FOR_INIT\n\tdepends on BUSYBOX_CONFIG_HALT || BUSYBOX_CONFIG_POWEROFF || BUSYBOX_CONFIG_REBOOT\n\thelp\n\tIn rare cases, poweroff may be commanded by firmware to OS\n\teven before init process exists. On Linux, this spawns\n\t\"/sbin/poweroff\" very early. This option adds code\n\twhich checks that init is ready to receive poweroff\n\tcommands. Code size increase of ~80 bytes.\n\nconfig BUSYBOX_CONFIG_FEATURE_CALL_TELINIT\n\tbool \"Call telinit on shutdown and reboot\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_CALL_TELINIT\n\tdepends on (BUSYBOX_CONFIG_HALT || BUSYBOX_CONFIG_POWEROFF || BUSYBOX_CONFIG_REBOOT) && !BUSYBOX_CONFIG_INIT\n\thelp\n\tCall an external program (normally telinit) to facilitate\n\ta switch to a proper runlevel.\n\n\tThis option is only available if you selected halt and friends,\n\tbut did not select init.\n\nconfig BUSYBOX_CONFIG_TELINIT_PATH\n\tstring \"Path to telinit executable\"\n\tdefault BUSYBOX_DEFAULT_TELINIT_PATH\n\tdepends on BUSYBOX_CONFIG_FEATURE_CALL_TELINIT\n\thelp\n\tWhen busybox halt and friends have to call external telinit\n\tto facilitate proper shutdown, this path is to be used when\n\tlocating telinit executable.\nconfig BUSYBOX_CONFIG_INIT\n\tbool \"init (10 kb)\"\n\tdefault BUSYBOX_DEFAULT_INIT\n\tselect BUSYBOX_CONFIG_FEATURE_SYSLOG\n\thelp\n\tinit is the first program run when the system boots.\n\nconfig BUSYBOX_CONFIG_LINUXRC\n\tbool \"linuxrc: support running init from initrd (not initramfs)\"\n\tdefault BUSYBOX_DEFAULT_LINUXRC\n\tselect BUSYBOX_CONFIG_FEATURE_SYSLOG\n\thelp\n\tLegacy support for running init under the old-style initrd. Allows\n\tthe name linuxrc to act as init, and it doesn't assume init is PID 1.\n\n\tThis does not apply to initramfs, which runs /init as PID 1 and\n\trequires no special support.\n\nconfig BUSYBOX_CONFIG_FEATURE_USE_INITTAB\n\tbool \"Support reading an inittab file\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_USE_INITTAB\n\tdepends on BUSYBOX_CONFIG_INIT || BUSYBOX_CONFIG_LINUXRC\n\thelp\n\tAllow init to read an inittab file when the system boot.\n\nconfig BUSYBOX_CONFIG_FEATURE_KILL_REMOVED\n\tbool \"Support killing processes that have been removed from inittab\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_KILL_REMOVED\n\tdepends on BUSYBOX_CONFIG_FEATURE_USE_INITTAB\n\thelp\n\tWhen respawn entries are removed from inittab and a SIGHUP is\n\tsent to init, this option will make init kill the processes\n\tthat have been removed.\n\nconfig BUSYBOX_CONFIG_FEATURE_KILL_DELAY\n\tint \"How long to wait between TERM and KILL (0 - send TERM only)\" if FEATURE_KILL_REMOVED\n\trange 0 1024\n\tdefault BUSYBOX_DEFAULT_FEATURE_KILL_DELAY\n\tdepends on BUSYBOX_CONFIG_FEATURE_KILL_REMOVED\n\thelp\n\tWith nonzero setting, init sends TERM, forks, child waits N\n\tseconds, sends KILL and exits. Setting it too high is unwise\n\t(child will hang around for too long and could actually kill\n\tthe wrong process!)\n\nconfig BUSYBOX_CONFIG_FEATURE_INIT_SCTTY\n\tbool \"Run commands with leading dash with controlling tty\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_INIT_SCTTY\n\tdepends on BUSYBOX_CONFIG_INIT || BUSYBOX_CONFIG_LINUXRC\n\thelp\n\tIf this option is enabled, init will try to give a controlling\n\ttty to any command which has leading hyphen (often it's \"-/bin/sh\").\n\tMore precisely, init will do \"ioctl(STDIN_FILENO, TIOCSCTTY, 0)\".\n\tIf device attached to STDIN_FILENO can be a ctty but is not yet\n\ta ctty for other session, it will become this process' ctty.\n\tThis is not the traditional init behavour, but is often what you want\n\tin an embedded system where the console is only accessed during\n\tdevelopment or for maintenance.\n\tNB: using cttyhack applet may work better.\n\nconfig BUSYBOX_CONFIG_FEATURE_INIT_SYSLOG\n\tbool \"Enable init to write to syslog\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_INIT_SYSLOG\n\tdepends on BUSYBOX_CONFIG_INIT || BUSYBOX_CONFIG_LINUXRC\n\thelp\n\tIf selected, some init messages are sent to syslog.\n\tOtherwise, they are sent to VT #5 if linux virtual tty is detected\n\t(if not, no separate logging is done).\n\nconfig BUSYBOX_CONFIG_FEATURE_INIT_QUIET\n\tbool \"Be quiet on boot (no 'init started:' message)\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_INIT_QUIET\n\tdepends on BUSYBOX_CONFIG_INIT || BUSYBOX_CONFIG_LINUXRC\n\nconfig BUSYBOX_CONFIG_FEATURE_INIT_COREDUMPS\n\tbool \"Support dumping core for child processes (debugging only)\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_INIT_COREDUMPS\t# not Y because this is a debug option\n\tdepends on BUSYBOX_CONFIG_INIT || BUSYBOX_CONFIG_LINUXRC\n\thelp\n\tIf this option is enabled and the file /.init_enable_core\n\texists, then init will call setrlimit() to allow unlimited\n\tcore file sizes. If this option is disabled, processes\n\twill not generate any core files.\n\nconfig BUSYBOX_CONFIG_INIT_TERMINAL_TYPE\n\tstring \"Initial terminal type\"\n\tdefault BUSYBOX_DEFAULT_INIT_TERMINAL_TYPE\n\tdepends on BUSYBOX_CONFIG_INIT || BUSYBOX_CONFIG_LINUXRC\n\thelp\n\tThis is the initial value set by init for the TERM environment\n\tvariable. This variable is used by programs which make use of\n\textended terminal capabilities.\n\n\tNote that on Linux, init attempts to detect serial terminal and\n\tsets TERM to \"vt102\" if one is found.\n\nconfig BUSYBOX_CONFIG_FEATURE_INIT_MODIFY_CMDLINE\n\tbool \"Clear init's command line\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_INIT_MODIFY_CMDLINE\n\tdepends on BUSYBOX_CONFIG_INIT || BUSYBOX_CONFIG_LINUXRC\n\thelp\n\tWhen launched as PID 1 and after parsing its arguments, init\n\twipes all the arguments but argv[0] and rewrites argv[0] to\n\tcontain only \"init\", so that its command line appears solely as\n\t\"init\" in tools such as ps.\n\tIf this option is set to Y, init will keep its original behavior,\n\totherwise, all the arguments including argv[0] will be preserved,\n\tbe they parsed or ignored by init.\n\tThe original command-line used to launch init can then be\n\tretrieved in /proc/1/cmdline on Linux, for example.\n\nendmenu\n"
  },
  {
    "path": "package/utils/busybox/config/klibc-utils/Config.in",
    "content": "# DO NOT EDIT. This file is generated from Config.src\n#\n# For a description of the syntax of this configuration file,\n# see docs/Kconfig-language.txt.\n#\n\nmenu \"klibc-utils\"\n\nconfig BUSYBOX_CONFIG_MINIPS\n\tbool \"minips (11 kb)\"\n\tdefault BUSYBOX_DEFAULT_MINIPS  # for god's sake, just use \"ps\" name in your scripts\n\thelp\n\tAlias to \"ps\".\nconfig BUSYBOX_CONFIG_NUKE\n\tbool \"nuke (2.9 kb)\"\n\tdefault BUSYBOX_DEFAULT_NUKE  # off by default: too \"accidentally destructive\"\n\thelp\n\tAlias to \"rm -rf\".\nconfig BUSYBOX_CONFIG_RESUME\n\tbool \"resume (3.2 kb)\"\n\tdefault BUSYBOX_DEFAULT_RESUME\n\thelp\n\tResume from saved \"suspend-to-disk\" image\nconfig BUSYBOX_CONFIG_RUN_INIT\n\tbool \"run-init (7.7 kb)\"\n\tdefault BUSYBOX_DEFAULT_RUN_INIT\n\thelp\n\tThe run-init utility is used from initramfs to select a new\n\troot device. Under initramfs, you have to use this instead of\n\tpivot_root.\n\n\tBooting with initramfs extracts a gzipped cpio archive into rootfs\n\t(which is a variant of ramfs/tmpfs). Because rootfs can't be moved\n\tor unmounted, pivot_root will not work from initramfs. Instead,\n\trun-init deletes everything out of rootfs (including itself),\n\tdoes a mount --move that overmounts rootfs with the new root, and\n\tthen execs the specified init program.\n\n\tutil-linux has a similar tool, switch-root.\n\trun-init differs by also having a \"-d CAPS_TO_DROP\" option.\n\nendmenu\n"
  },
  {
    "path": "package/utils/busybox/config/libbb/Config.in",
    "content": "# DO NOT EDIT. This file is generated from Config.src\n#\n# For a description of the syntax of this configuration file,\n# see docs/Kconfig-language.txt.\n#\n\ncomment \"Library Tuning\"\n\nconfig BUSYBOX_CONFIG_FEATURE_USE_BSS_TAIL\n\tbool \"Use the end of BSS page\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_USE_BSS_TAIL\n\thelp\n\tAttempt to reclaim a small unused part of BSS.\n\n\tExecutables have the following parts:\n\t= read-only executable code and constants, also known as \"text\"\n\t= read-write data\n\t= non-initialized (zeroed on demand) data, also known as \"bss\"\n\n\tAt link time, \"text\" is padded to a full page. At runtime, all \"text\"\n\tpages are mapped RO and executable.\n\n\t\"Data\" starts on the next page boundary, but is not padded\n\tto a full page at the end. \"Bss\" starts wherever \"data\" ends.\n\tAt runtime, \"data\" pages are mapped RW and they are file-backed\n\t(this includes a small portion of \"bss\" which may live in the last\n\tpartial page of \"data\").\n\tPages which are fully in \"bss\" are mapped to anonymous memory.\n\n\t\"Bss\" end is usually not page-aligned. There is an unused space\n\tin the last page. Linker marks its start with the \"_end\" symbol.\n\n\tThis option will attempt to use that space for bb_common_bufsiz1[]\n\tarray. If it fits after _end, it will be used, and COMMON_BUFSIZE\n\twill be enlarged from its guaranteed minimum size of 1 kbyte.\n\tThis may require recompilation a second time, since value of _end\n\tis known only after final link.\n\n\tIf you are getting a build error like this:\n\t\tappletlib.c:(.text.main+0xd): undefined reference to '_end'\n\tdisable this option.\nconfig BUSYBOX_CONFIG_FLOAT_DURATION\n\tbool \"Enable fractional duration arguments\"\n\tdefault BUSYBOX_DEFAULT_FLOAT_DURATION\n\thelp\n\tAllow sleep N.NNN, top -d N.NNN etc.\nconfig BUSYBOX_CONFIG_FEATURE_RTMINMAX\n\tbool \"Support RTMIN[+n] and RTMAX[-n] signal names\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_RTMINMAX\n\thelp\n\tSupport RTMIN[+n] and RTMAX[-n] signal names\n\tin kill, killall etc. This costs ~250 bytes.\n\nconfig BUSYBOX_CONFIG_FEATURE_RTMINMAX_USE_LIBC_DEFINITIONS\n\tbool \"Use the definitions of SIGRTMIN/SIGRTMAX provided by libc\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_RTMINMAX_USE_LIBC_DEFINITIONS\n\tdepends on BUSYBOX_CONFIG_FEATURE_RTMINMAX\n\thelp\n\tSome C libraries reserve a few real-time signals for internal\n\tuse, and adjust the values of SIGRTMIN/SIGRTMAX seen by\n\tapplications accordingly. Saying yes here means that a signal\n\tname RTMIN+n will be interpreted according to the libc definition\n\tof SIGRTMIN, and not the raw definition provided by the kernel.\n\tThis behavior matches \"kill -l RTMIN+n\" from bash.\n\nchoice\n\tprompt \"Buffer allocation policy\"\n\tdefault BUSYBOX_CONFIG_FEATURE_BUFFERS_GO_ON_STACK\n\thelp\n\tThere are 3 ways busybox can handle buffer allocations:\n\t- Use malloc. This costs code size for the call to xmalloc.\n\t- Put them on stack. For some very small machines with limited stack\n\tspace, this can be deadly. For most folks, this works just fine.\n\t- Put them in BSS. This works beautifully for computers with a real\n\tMMU (and OS support), but wastes runtime RAM for uCLinux. This\n\tbehavior was the only one available for versions 0.48 and earlier.\n\nconfig BUSYBOX_CONFIG_FEATURE_BUFFERS_USE_MALLOC\n\tbool \"Allocate with Malloc\"\n\nconfig BUSYBOX_CONFIG_FEATURE_BUFFERS_GO_ON_STACK\n\tbool \"Allocate on the Stack\"\n\nconfig BUSYBOX_CONFIG_FEATURE_BUFFERS_GO_IN_BSS\n\tbool \"Allocate in the .bss section\"\n\nendchoice\n\nconfig BUSYBOX_CONFIG_PASSWORD_MINLEN\n\tint \"Minimum password length\"\n\tdefault BUSYBOX_DEFAULT_PASSWORD_MINLEN\n\trange 5 32\n\thelp\n\tMinimum allowable password length.\n\nconfig BUSYBOX_CONFIG_MD5_SMALL\n\tint \"MD5: Trade bytes for speed (0:fast, 3:slow)\"\n\tdefault BUSYBOX_DEFAULT_MD5_SMALL  # all \"fast or small\" options default to small\n\trange 0 3\n\thelp\n\tTrade binary size versus speed for the md5sum algorithm.\n\tApproximate values running uClibc and hashing\n\tlinux-2.4.4.tar.bz2 were:\n\tvalue               user times (sec)  text size (386)\n\t0 (fastest)         1.1                6144\n\t1                   1.4                5392\n\t2                   3.0                5088\n\t3 (smallest)        5.1                4912\n\nconfig BUSYBOX_CONFIG_SHA3_SMALL\n\tint \"SHA3: Trade bytes for speed (0:fast, 1:slow)\"\n\tdefault BUSYBOX_DEFAULT_SHA3_SMALL  # all \"fast or small\" options default to small\n\trange 0 1\n\thelp\n\tTrade binary size versus speed for the sha3sum algorithm.\n\tSHA3_SMALL=0 compared to SHA3_SMALL=1 (approximate):\n\t64-bit x86: +270 bytes of code, 45% faster\n\t32-bit x86: +450 bytes of code, 75% faster\n\nconfig BUSYBOX_CONFIG_FEATURE_NON_POSIX_CP\n\tbool \"Non-POSIX, but safer, copying to special nodes\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_NON_POSIX_CP\n\thelp\n\tWith this option, \"cp file symlink\" will delete symlink\n\tand create a regular file. This does not conform to POSIX,\n\tbut prevents a symlink attack.\n\tSimilarly, \"cp file device\" will not send file's data\n\tto the device. (To do that, use \"cat file >device\")\n\nconfig BUSYBOX_CONFIG_FEATURE_VERBOSE_CP_MESSAGE\n\tbool \"Give more precise messages when copy fails (cp, mv etc)\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_VERBOSE_CP_MESSAGE\n\thelp\n\tError messages with this feature enabled:\n\n\t$ cp file /does_not_exist/file\n\tcp: cannot create '/does_not_exist/file': Path does not exist\n\t$ cp file /vmlinuz/file\n\tcp: cannot stat '/vmlinuz/file': Path has non-directory component\n\n\tIf this feature is not enabled, they will be, respectively:\n\n\tcp: cannot create '/does_not_exist/file': No such file or directory\n\tcp: cannot stat '/vmlinuz/file': Not a directory\n\n\tThis will cost you ~60 bytes.\n\nconfig BUSYBOX_CONFIG_FEATURE_USE_SENDFILE\n\tbool \"Use sendfile system call\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_USE_SENDFILE\n\thelp\n\tWhen enabled, busybox will use the kernel sendfile() function\n\tinstead of read/write loops to copy data between file descriptors\n\t(for example, cp command does this a lot).\n\tIf sendfile() doesn't work, copying code falls back to read/write\n\tloop. sendfile() was originally implemented for faster I/O\n\tfrom files to sockets, but since Linux 2.6.33 it was extended\n\tto work for many more file types.\n\nconfig BUSYBOX_CONFIG_FEATURE_COPYBUF_KB\n\tint \"Copy buffer size, in kilobytes\"\n\trange 1 1024\n\tdefault BUSYBOX_DEFAULT_FEATURE_COPYBUF_KB\n\thelp\n\tSize of buffer used by cp, mv, install, wget etc.\n\tBuffers which are 4 kb or less will be allocated on stack.\n\tBigger buffers will be allocated with mmap, with fallback to 4 kb\n\tstack buffer if mmap fails.\n\nconfig BUSYBOX_CONFIG_MONOTONIC_SYSCALL\n\tbool \"Use clock_gettime(CLOCK_MONOTONIC) syscall\"\n\tdefault BUSYBOX_DEFAULT_MONOTONIC_SYSCALL\n\thelp\n\tUse clock_gettime(CLOCK_MONOTONIC) syscall for measuring\n\ttime intervals (time, ping, traceroute etc need this).\n\tProbably requires Linux 2.6+. If not selected, gettimeofday\n\twill be used instead (which gives wrong results if date/time\n\tis reset).\n\nconfig BUSYBOX_CONFIG_IOCTL_HEX2STR_ERROR\n\tbool \"Use ioctl names rather than hex values in error messages\"\n\tdefault BUSYBOX_DEFAULT_IOCTL_HEX2STR_ERROR\n\thelp\n\tUse ioctl names rather than hex values in error messages\n\t(e.g. VT_DISALLOCATE rather than 0x5608). If disabled this\n\tsaves about 1400 bytes.\n\nconfig BUSYBOX_CONFIG_FEATURE_EDITING\n\tbool \"Command line editing\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_EDITING\n\thelp\n\tEnable line editing (mainly for shell command line).\n\nconfig BUSYBOX_CONFIG_FEATURE_EDITING_MAX_LEN\n\tint \"Maximum length of input\"\n\trange 128 8192\n\tdefault BUSYBOX_DEFAULT_FEATURE_EDITING_MAX_LEN\n\tdepends on BUSYBOX_CONFIG_FEATURE_EDITING\n\thelp\n\tLine editing code uses on-stack buffers for storage.\n\tYou may want to decrease this parameter if your target machine\n\tbenefits from smaller stack usage.\n\nconfig BUSYBOX_CONFIG_FEATURE_EDITING_VI\n\tbool \"vi-style line editing commands\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_EDITING_VI\n\tdepends on BUSYBOX_CONFIG_FEATURE_EDITING\n\thelp\n\tEnable vi-style line editing. In shells, this mode can be\n\tturned on and off with \"set -o vi\" and \"set +o vi\".\n\nconfig BUSYBOX_CONFIG_FEATURE_EDITING_HISTORY\n\tint \"History size\"\n\t# Don't allow way too big values here, code uses fixed \"char *history[N]\" struct member\n\trange 0 9999\n\tdefault BUSYBOX_DEFAULT_FEATURE_EDITING_HISTORY\n\tdepends on BUSYBOX_CONFIG_FEATURE_EDITING\n\thelp\n\tSpecify command history size (0 - disable).\n\nconfig BUSYBOX_CONFIG_FEATURE_EDITING_SAVEHISTORY\n\tbool \"History saving\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_EDITING_SAVEHISTORY\n\tdepends on BUSYBOX_CONFIG_FEATURE_EDITING\n\thelp\n\tEnable history saving in shells.\n\nconfig BUSYBOX_CONFIG_FEATURE_EDITING_SAVE_ON_EXIT\n\tbool \"Save history on shell exit, not after every command\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_EDITING_SAVE_ON_EXIT\n\tdepends on BUSYBOX_CONFIG_FEATURE_EDITING_SAVEHISTORY\n\thelp\n\tSave history on shell exit, not after every command.\n\nconfig BUSYBOX_CONFIG_FEATURE_REVERSE_SEARCH\n\tbool \"Reverse history search\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_REVERSE_SEARCH\n\tdepends on BUSYBOX_CONFIG_FEATURE_EDITING\n\thelp\n\tEnable readline-like Ctrl-R combination for reverse history search.\n\tIncreases code by about 0.5k.\n\nconfig BUSYBOX_CONFIG_FEATURE_TAB_COMPLETION\n\tbool \"Tab completion\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_TAB_COMPLETION\n\tdepends on BUSYBOX_CONFIG_FEATURE_EDITING\n\nconfig BUSYBOX_CONFIG_FEATURE_USERNAME_COMPLETION\n\tbool \"Username completion\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_USERNAME_COMPLETION\n\tdepends on BUSYBOX_CONFIG_FEATURE_TAB_COMPLETION\n\nconfig BUSYBOX_CONFIG_FEATURE_EDITING_FANCY_PROMPT\n\tbool \"Fancy shell prompts\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_EDITING_FANCY_PROMPT\n\tdepends on BUSYBOX_CONFIG_FEATURE_EDITING\n\thelp\n\tSetting this option allows for prompts to use things like \\w and\n\t\\$ and escape codes.\n\nconfig BUSYBOX_CONFIG_FEATURE_EDITING_WINCH\n\tbool \"Enable automatic tracking of window size changes\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_EDITING_WINCH\n\tdepends on BUSYBOX_CONFIG_FEATURE_EDITING\n\nconfig BUSYBOX_CONFIG_FEATURE_EDITING_ASK_TERMINAL\n\tbool \"Query cursor position from terminal\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_EDITING_ASK_TERMINAL\n\tdepends on BUSYBOX_CONFIG_FEATURE_EDITING\n\thelp\n\tAllow usage of \"ESC [ 6 n\" sequence. Terminal answers back with\n\tcurrent cursor position. This information is used to make line\n\tediting more robust in some cases.\n\tIf you are not sure whether your terminals respond to this code\n\tcorrectly, or want to save on code size (about 400 bytes),\n\tthen do not turn this option on.\n\nconfig BUSYBOX_CONFIG_LOCALE_SUPPORT\n\tbool \"Enable locale support (system needs locale for this to work)\"\n\tdefault BUSYBOX_DEFAULT_LOCALE_SUPPORT\n\thelp\n\tEnable this if your system has locale support and you would like\n\tbusybox to support locale settings.\n\nconfig BUSYBOX_CONFIG_UNICODE_SUPPORT\n\tbool \"Support Unicode\"\n\tdefault BUSYBOX_DEFAULT_UNICODE_SUPPORT\n\thelp\n\tThis makes various applets aware that one byte is not\n\tone character on screen.\n\n\tBusybox aims to eventually work correctly with Unicode displays.\n\tAny older encodings are not guaranteed to work.\n\tProbably by the time when busybox will be fully Unicode-clean,\n\tother encodings will be mainly of historic interest.\n\nconfig BUSYBOX_CONFIG_UNICODE_USING_LOCALE\n\tbool \"Use libc routines for Unicode (else uses internal ones)\"\n\tdefault BUSYBOX_DEFAULT_UNICODE_USING_LOCALE\n\tdepends on BUSYBOX_CONFIG_UNICODE_SUPPORT && BUSYBOX_CONFIG_LOCALE_SUPPORT\n\thelp\n\tWith this option on, Unicode support is implemented using libc\n\troutines. Otherwise, internal implementation is used.\n\tInternal implementation is smaller.\n\nconfig BUSYBOX_CONFIG_FEATURE_CHECK_UNICODE_IN_ENV\n\tbool \"Check $LC_ALL, $LC_CTYPE and $LANG environment variables\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_CHECK_UNICODE_IN_ENV\n\tdepends on BUSYBOX_CONFIG_UNICODE_SUPPORT && !BUSYBOX_CONFIG_UNICODE_USING_LOCALE\n\thelp\n\tWith this option on, Unicode support is activated\n\tonly if locale-related variables have the value of the form\n\t\"xxxx.utf8\"\n\n\tOtherwise, Unicode support will be always enabled and active.\n\nconfig BUSYBOX_CONFIG_SUBST_WCHAR\n\tint \"Character code to substitute unprintable characters with\"\n\tdepends on BUSYBOX_CONFIG_UNICODE_SUPPORT\n\tdefault BUSYBOX_DEFAULT_SUBST_WCHAR\n\thelp\n\tTypical values are 63 for '?' (works with any output device),\n\t30 for ASCII substitute control code,\n\t65533 (0xfffd) for Unicode replacement character.\n\nconfig BUSYBOX_CONFIG_LAST_SUPPORTED_WCHAR\n\tint \"Range of supported Unicode characters\"\n\tdepends on BUSYBOX_CONFIG_UNICODE_SUPPORT\n\tdefault BUSYBOX_DEFAULT_LAST_SUPPORTED_WCHAR\n\thelp\n\tAny character with Unicode value bigger than this is assumed\n\tto be non-printable on output device. Many applets replace\n\tsuch characters with substitution character.\n\n\tThe idea is that many valid printable Unicode chars\n\tnevertheless are not displayed correctly. Think about\n\tcombining charachers, double-wide hieroglyphs, obscure\n\tcharacters in dozens of ancient scripts...\n\tMany terminals, terminal emulators, xterms etc will fail\n\tto handle them correctly. Choose the smallest value\n\twhich suits your needs.\n\n\tTypical values are:\n\t126 - ASCII only\n\t767 (0x2ff) - there are no combining chars in [0..767] range\n\t\t\t(the range includes Latin 1, Latin Ext. A and B),\n\t\t\tcode is ~700 bytes smaller for this case.\n\t4351 (0x10ff) - there are no double-wide chars in [0..4351] range,\n\t\t\tcode is ~300 bytes smaller for this case.\n\t12799 (0x31ff) - nearly all non-ideographic characters are\n\t\t\tavailable in [0..12799] range, including\n\t\t\tEast Asian scripts like katakana, hiragana, hangul,\n\t\t\tbopomofo...\n\t0 - off, any valid printable Unicode character will be printed.\n\nconfig BUSYBOX_CONFIG_UNICODE_COMBINING_WCHARS\n\tbool \"Allow zero-width Unicode characters on output\"\n\tdefault BUSYBOX_DEFAULT_UNICODE_COMBINING_WCHARS\n\tdepends on BUSYBOX_CONFIG_UNICODE_SUPPORT\n\thelp\n\tWith this option off, any Unicode char with width of 0\n\tis substituted on output.\n\nconfig BUSYBOX_CONFIG_UNICODE_WIDE_WCHARS\n\tbool \"Allow wide Unicode characters on output\"\n\tdefault BUSYBOX_DEFAULT_UNICODE_WIDE_WCHARS\n\tdepends on BUSYBOX_CONFIG_UNICODE_SUPPORT\n\thelp\n\tWith this option off, any Unicode char with width > 1\n\tis substituted on output.\n\nconfig BUSYBOX_CONFIG_UNICODE_BIDI_SUPPORT\n\tbool \"Bidirectional character-aware line input\"\n\tdefault BUSYBOX_DEFAULT_UNICODE_BIDI_SUPPORT\n\tdepends on BUSYBOX_CONFIG_UNICODE_SUPPORT && !BUSYBOX_CONFIG_UNICODE_USING_LOCALE\n\thelp\n\tWith this option on, right-to-left Unicode characters\n\tare treated differently on input (e.g. cursor movement).\n\nconfig BUSYBOX_CONFIG_UNICODE_NEUTRAL_TABLE\n\tbool \"In bidi input, support non-ASCII neutral chars too\"\n\tdefault BUSYBOX_DEFAULT_UNICODE_NEUTRAL_TABLE\n\tdepends on BUSYBOX_CONFIG_UNICODE_BIDI_SUPPORT\n\thelp\n\tIn most cases it's enough to treat only ASCII non-letters\n\t(i.e. punctuation, numbers and space) as characters\n\twith neutral directionality.\n\tWith this option on, more extensive (and bigger) table\n\tof neutral chars will be used.\n\nconfig BUSYBOX_CONFIG_UNICODE_PRESERVE_BROKEN\n\tbool \"Make it possible to enter sequences of chars which are not Unicode\"\n\tdefault BUSYBOX_DEFAULT_UNICODE_PRESERVE_BROKEN\n\tdepends on BUSYBOX_CONFIG_UNICODE_SUPPORT\n\thelp\n\tWith this option on, on line-editing input (such as used by shells)\n\tinvalid UTF-8 bytes are not substituted with the selected\n\tsubstitution character.\n\tFor example, this means that entering 'l', 's', ' ', 0xff, [Enter]\n\tat shell prompt will list file named 0xff (single char name\n\twith char value 255), not file named '?'.\n"
  },
  {
    "path": "package/utils/busybox/config/loginutils/Config.in",
    "content": "# DO NOT EDIT. This file is generated from Config.src\n#\n# For a description of the syntax of this configuration file,\n# see docs/Kconfig-language.txt.\n#\n\nmenu \"Login/Password Management Utilities\"\n\nconfig BUSYBOX_CONFIG_FEATURE_SHADOWPASSWDS\n\tbool \"Support shadow passwords\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_SHADOWPASSWDS\n\thelp\n\tBuild support for shadow password in /etc/shadow. This file is only\n\treadable by root and thus the encrypted passwords are no longer\n\tpublicly readable.\n\nconfig BUSYBOX_CONFIG_USE_BB_PWD_GRP\n\tbool \"Use internal password and group functions rather than system functions\"\n\tdefault BUSYBOX_DEFAULT_USE_BB_PWD_GRP\n\thelp\n\tIf you leave this disabled, busybox will use the system's password\n\tand group functions. And if you are using the GNU C library\n\t(glibc), you will then need to install the /etc/nsswitch.conf\n\tconfiguration file and the required /lib/libnss_* libraries in\n\torder for the password and group functions to work. This generally\n\tmakes your embedded system quite a bit larger.\n\n\tEnabling this option will cause busybox to directly access the\n\tsystem's /etc/password, /etc/group files (and your system will be\n\tsmaller, and I will get fewer emails asking about how glibc NSS\n\tworks). When this option is enabled, you will not be able to use\n\tPAM to access remote LDAP password servers and whatnot. And if you\n\twant hostname resolution to work with glibc, you still need the\n\t/lib/libnss_* libraries.\n\n\tIf you need to use glibc's nsswitch.conf mechanism\n\t(e.g. if user/group database is NOT stored in /etc/passwd etc),\n\tyou must NOT use this option.\n\n\tIf you enable this option, it will add about 1.5k.\n\nconfig BUSYBOX_CONFIG_USE_BB_SHADOW\n\tbool \"Use internal shadow password functions\"\n\tdefault BUSYBOX_DEFAULT_USE_BB_SHADOW\n\tdepends on BUSYBOX_CONFIG_USE_BB_PWD_GRP && BUSYBOX_CONFIG_FEATURE_SHADOWPASSWDS\n\thelp\n\tIf you leave this disabled, busybox will use the system's shadow\n\tpassword handling functions. And if you are using the GNU C library\n\t(glibc), you will then need to install the /etc/nsswitch.conf\n\tconfiguration file and the required /lib/libnss_* libraries in\n\torder for the shadow password functions to work. This generally\n\tmakes your embedded system quite a bit larger.\n\n\tEnabling this option will cause busybox to directly access the\n\tsystem's /etc/shadow file when handling shadow passwords. This\n\tmakes your system smaller (and I will get fewer emails asking about\n\thow glibc NSS works). When this option is enabled, you will not be\n\table to use PAM to access shadow passwords from remote LDAP\n\tpassword servers and whatnot.\n\nconfig BUSYBOX_CONFIG_USE_BB_CRYPT\n\tbool \"Use internal crypt functions\"\n\tdefault BUSYBOX_DEFAULT_USE_BB_CRYPT\n\thelp\n\tBusybox has internal DES and MD5 crypt functions.\n\tThey produce results which are identical to corresponding\n\tstandard C library functions.\n\n\tIf you leave this disabled, busybox will use the system's\n\tcrypt functions. Most C libraries use large (~70k)\n\tstatic buffers there, and also combine them with more general\n\tDES encryption/decryption.\n\n\tFor busybox, having large static buffers is undesirable,\n\tespecially on NOMMU machines. Busybox also doesn't need\n\tDES encryption/decryption and can do with smaller code.\n\n\tIf you enable this option, it will add about 4.8k of code\n\tif you are building dynamically linked executable.\n\tIn static build, it makes code _smaller_ by about 1.2k,\n\tand likely many kilobytes less of bss.\n\nconfig BUSYBOX_CONFIG_USE_BB_CRYPT_SHA\n\tbool \"Enable SHA256/512 crypt functions\"\n\tdefault BUSYBOX_DEFAULT_USE_BB_CRYPT_SHA\n\tdepends on BUSYBOX_CONFIG_USE_BB_CRYPT\n\thelp\n\tEnable this if you have passwords starting with \"$5$\" or \"$6$\"\n\tin your /etc/passwd or /etc/shadow files. These passwords\n\tare hashed using SHA256 and SHA512 algorithms. Support for them\n\twas added to glibc in 2008.\n\tWith this option off, login will fail password check for any\n\tuser which has password encrypted with these algorithms.\n\nconfig BUSYBOX_CONFIG_ADD_SHELL\n\tbool \"add-shell (3.1 kb)\"\n\tdefault BUSYBOX_DEFAULT_ADD_SHELL if BUSYBOX_CONFIG_DESKTOP\n\thelp\n\tAdd shells to /etc/shells.\n\nconfig BUSYBOX_CONFIG_REMOVE_SHELL\n\tbool \"remove-shell (3 kb)\"\n\tdefault BUSYBOX_DEFAULT_REMOVE_SHELL if BUSYBOX_CONFIG_DESKTOP\n\thelp\n\tRemove shells from /etc/shells.\nconfig BUSYBOX_CONFIG_ADDGROUP\n\tbool \"addgroup (8.6 kb)\"\n\tdefault BUSYBOX_DEFAULT_ADDGROUP\n\tselect BUSYBOX_CONFIG_LONG_OPTS\n\thelp\n\tUtility for creating a new group account.\n\nconfig BUSYBOX_CONFIG_FEATURE_ADDUSER_TO_GROUP\n\tbool \"Support adding users to groups\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_ADDUSER_TO_GROUP\n\tdepends on BUSYBOX_CONFIG_ADDGROUP\n\thelp\n\tIf called with two non-option arguments,\n\taddgroup will add an existing user to an\n\texisting group.\nconfig BUSYBOX_CONFIG_ADDUSER\n\tbool \"adduser (15 kb)\"\n\tdefault BUSYBOX_DEFAULT_ADDUSER\n\tselect BUSYBOX_CONFIG_LONG_OPTS\n\thelp\n\tUtility for creating a new user account.\n\nconfig BUSYBOX_CONFIG_FEATURE_CHECK_NAMES\n\tbool \"Enable sanity check on user/group names in adduser and addgroup\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_CHECK_NAMES\n\tdepends on BUSYBOX_CONFIG_ADDUSER || BUSYBOX_CONFIG_ADDGROUP\n\thelp\n\tEnable sanity check on user and group names in adduser and addgroup.\n\tTo avoid problems, the user or group name should consist only of\n\tletters, digits, underscores, periods, at signs and dashes,\n\tand not start with a dash (as defined by IEEE Std 1003.1-2001).\n\tFor compatibility with Samba machine accounts \"$\" is also supported\n\tat the end of the user or group name.\n\nconfig BUSYBOX_CONFIG_LAST_ID\n\tint \"Last valid uid or gid for adduser and addgroup\"\n\tdepends on BUSYBOX_CONFIG_ADDUSER || BUSYBOX_CONFIG_ADDGROUP\n\tdefault BUSYBOX_DEFAULT_LAST_ID\n\thelp\n\tLast valid uid or gid for adduser and addgroup\n\nconfig BUSYBOX_CONFIG_FIRST_SYSTEM_ID\n\tint \"First valid system uid or gid for adduser and addgroup\"\n\tdepends on BUSYBOX_CONFIG_ADDUSER || BUSYBOX_CONFIG_ADDGROUP\n\trange 0 BUSYBOX_CONFIG_LAST_ID\n\tdefault BUSYBOX_DEFAULT_FIRST_SYSTEM_ID\n\thelp\n\tFirst valid system uid or gid for adduser and addgroup\n\nconfig BUSYBOX_CONFIG_LAST_SYSTEM_ID\n\tint \"Last valid system uid or gid for adduser and addgroup\"\n\tdepends on BUSYBOX_CONFIG_ADDUSER || BUSYBOX_CONFIG_ADDGROUP\n\trange BUSYBOX_CONFIG_FIRST_SYSTEM_ID BUSYBOX_CONFIG_LAST_ID\n\tdefault BUSYBOX_DEFAULT_LAST_SYSTEM_ID\n\thelp\n\tLast valid system uid or gid for adduser and addgroup\nconfig BUSYBOX_CONFIG_CHPASSWD\n\tbool \"chpasswd (18 kb)\"\n\tdefault BUSYBOX_DEFAULT_CHPASSWD\n\thelp\n\tReads a file of user name and password pairs from standard input\n\tand uses this information to update a group of existing users.\n\nconfig BUSYBOX_CONFIG_FEATURE_DEFAULT_PASSWD_ALGO\n\tstring \"Default encryption method (passwd -a, cryptpw -m, chpasswd -c ALG)\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_DEFAULT_PASSWD_ALGO\n\tdepends on BUSYBOX_CONFIG_PASSWD || BUSYBOX_CONFIG_CRYPTPW || BUSYBOX_CONFIG_CHPASSWD\n\thelp\n\tPossible choices are \"d[es]\", \"m[d5]\", \"s[ha256]\" or \"sha512\".\nconfig BUSYBOX_CONFIG_CRYPTPW\n\tbool \"cryptpw (14 kb)\"\n\tdefault BUSYBOX_DEFAULT_CRYPTPW\n\thelp\n\tEncrypts the given password with the crypt(3) libc function\n\tusing the given salt.\n\nconfig BUSYBOX_CONFIG_MKPASSWD\n\tbool \"mkpasswd (15 kb)\"\n\tdefault BUSYBOX_DEFAULT_MKPASSWD\n\thelp\n\tEncrypts the given password with the crypt(3) libc function\n\tusing the given salt. Debian has this utility under mkpasswd\n\tname. Busybox provides mkpasswd as an alias for cryptpw.\nconfig BUSYBOX_CONFIG_DELUSER\n\tbool \"deluser (9.1 kb)\"\n\tdefault BUSYBOX_DEFAULT_DELUSER\n\thelp\n\tUtility for deleting a user account.\n\nconfig BUSYBOX_CONFIG_DELGROUP\n\tbool \"delgroup (6.4 kb)\"\n\tdefault BUSYBOX_DEFAULT_DELGROUP\n\thelp\n\tUtility for deleting a group account.\n\nconfig BUSYBOX_CONFIG_FEATURE_DEL_USER_FROM_GROUP\n\tbool \"Support removing users from groups\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_DEL_USER_FROM_GROUP\n\tdepends on BUSYBOX_CONFIG_DELGROUP\n\thelp\n\tIf called with two non-option arguments, deluser\n\tor delgroup will remove an user from a specified group.\nconfig BUSYBOX_CONFIG_GETTY\n\tbool \"getty (10 kb)\"\n\tdefault BUSYBOX_DEFAULT_GETTY\n\tselect BUSYBOX_CONFIG_FEATURE_SYSLOG\n\thelp\n\tgetty lets you log in on a tty. It is normally invoked by init.\n\n\tNote that you can save a few bytes by disabling it and\n\tusing login applet directly.\n\tIf you need to reset tty attributes before calling login,\n\tthis script approximates getty:\n\n\texec </dev/$1 >/dev/$1 2>&1 || exit 1\n\treset\n\tstty sane; stty ispeed 38400; stty ospeed 38400\n\tprintf \"%s login: \" \"`hostname`\"\n\tread -r login\n\texec /bin/login \"$login\"\nconfig BUSYBOX_CONFIG_LOGIN\n\tbool \"login (24 kb)\"\n\tdefault BUSYBOX_DEFAULT_LOGIN\n\tselect BUSYBOX_CONFIG_FEATURE_SYSLOG\n\thelp\n\tlogin is used when signing onto a system.\n\n\tNote that busybox binary must be setuid root for this applet to\n\twork properly.\n\nconfig BUSYBOX_CONFIG_LOGIN_SESSION_AS_CHILD\n\tbool \"Run logged in session in a child process\"\n\tdefault BUSYBOX_DEFAULT_LOGIN_SESSION_AS_CHILD if BUSYBOX_CONFIG_PAM\n\tdepends on BUSYBOX_CONFIG_LOGIN\n\thelp\n\tRun the logged in session in a child process.  This allows\n\tlogin to clean up things such as utmp entries or PAM sessions\n\twhen the login session is complete.  If you use PAM, you\n\talmost always would want this to be set to Y, else PAM session\n\twill not be cleaned up.\n\nconfig BUSYBOX_CONFIG_LOGIN_SCRIPTS\n\tbool \"Support login scripts\"\n\tdepends on BUSYBOX_CONFIG_LOGIN\n\tdefault BUSYBOX_DEFAULT_LOGIN_SCRIPTS\n\thelp\n\tEnable this if you want login to execute $LOGIN_PRE_SUID_SCRIPT\n\tjust prior to switching from root to logged-in user.\n\nconfig BUSYBOX_CONFIG_FEATURE_NOLOGIN\n\tbool \"Support /etc/nologin\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_NOLOGIN\n\tdepends on BUSYBOX_CONFIG_LOGIN\n\thelp\n\tThe file /etc/nologin is used by (some versions of) login(1).\n\tIf it exists, non-root logins are prohibited.\n\nconfig BUSYBOX_CONFIG_FEATURE_SECURETTY\n\tbool \"Support /etc/securetty\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_SECURETTY\n\tdepends on BUSYBOX_CONFIG_LOGIN\n\thelp\n\tThe file /etc/securetty is used by (some versions of) login(1).\n\tThe file contains the device names of tty lines (one per line,\n\twithout leading /dev/) on which root is allowed to login.\nconfig BUSYBOX_CONFIG_PASSWD\n\tbool \"passwd (21 kb)\"\n\tdefault BUSYBOX_DEFAULT_PASSWD\n\tselect BUSYBOX_CONFIG_FEATURE_SYSLOG\n\thelp\n\tpasswd changes passwords for user and group accounts. A normal user\n\tmay only change the password for his/her own account, the super user\n\tmay change the password for any account. The administrator of a group\n\tmay change the password for the group.\n\n\tNote that busybox binary must be setuid root for this applet to\n\twork properly.\n\nconfig BUSYBOX_CONFIG_FEATURE_PASSWD_WEAK_CHECK\n\tbool \"Check new passwords for weakness\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_PASSWD_WEAK_CHECK\n\tdepends on BUSYBOX_CONFIG_PASSWD\n\thelp\n\tWith this option passwd will refuse new passwords which are \"weak\".\nconfig BUSYBOX_CONFIG_SU\n\tbool \"su (19 kb)\"\n\tdefault BUSYBOX_DEFAULT_SU\n\tselect BUSYBOX_CONFIG_FEATURE_SYSLOG\n\thelp\n\tsu is used to become another user during a login session.\n\tInvoked without a username, su defaults to becoming the super user.\n\tNote that busybox binary must be setuid root for this applet to\n\twork properly.\n\nconfig BUSYBOX_CONFIG_FEATURE_SU_SYSLOG\n\tbool \"Log to syslog all attempts to use su\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_SU_SYSLOG\n\tdepends on BUSYBOX_CONFIG_SU\n\nconfig BUSYBOX_CONFIG_FEATURE_SU_CHECKS_SHELLS\n\tbool \"If user's shell is not in /etc/shells, disallow -s PROG\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_SU_CHECKS_SHELLS\n\tdepends on BUSYBOX_CONFIG_SU\n\nconfig BUSYBOX_CONFIG_FEATURE_SU_BLANK_PW_NEEDS_SECURE_TTY\n\tbool \"Allow blank passwords only on TTYs in /etc/securetty\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_SU_BLANK_PW_NEEDS_SECURE_TTY\n\tdepends on BUSYBOX_CONFIG_SU\nconfig BUSYBOX_CONFIG_SULOGIN\n\tbool \"sulogin (17 kb)\"\n\tdefault BUSYBOX_DEFAULT_SULOGIN\n\tselect BUSYBOX_CONFIG_FEATURE_SYSLOG\n\thelp\n\tsulogin is invoked when the system goes into single user\n\tmode (this is done through an entry in inittab).\nconfig BUSYBOX_CONFIG_VLOCK\n\tbool \"vlock (17 kb)\"\n\tdefault BUSYBOX_DEFAULT_VLOCK\n\thelp\n\tBuild the \"vlock\" applet which allows you to lock (virtual) terminals.\n\n\tNote that busybox binary must be setuid root for this applet to\n\twork properly.\n\nendmenu\n"
  },
  {
    "path": "package/utils/busybox/config/mailutils/Config.in",
    "content": "# DO NOT EDIT. This file is generated from Config.src\nmenu \"Mail Utilities\"\n\nconfig BUSYBOX_CONFIG_FEATURE_MIME_CHARSET\n\tstring \"Default charset\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_MIME_CHARSET\n\tdepends on BUSYBOX_CONFIG_MAKEMIME || BUSYBOX_CONFIG_REFORMIME || BUSYBOX_CONFIG_SENDMAIL\n\thelp\n\tDefault charset of the message.\n\nconfig BUSYBOX_CONFIG_MAKEMIME\n\tbool \"makemime (5.4 kb)\"\n\tdefault BUSYBOX_DEFAULT_MAKEMIME\n\thelp\n\tCreate MIME-formatted messages.\nconfig BUSYBOX_CONFIG_POPMAILDIR\n\tbool \"popmaildir (10 kb)\"\n\tdefault BUSYBOX_DEFAULT_POPMAILDIR\n\thelp\n\tSimple yet powerful POP3 mail popper. Delivers content\n\tof remote mailboxes to local Maildir.\n\nconfig BUSYBOX_CONFIG_FEATURE_POPMAILDIR_DELIVERY\n\tbool \"Allow message filters and custom delivery program\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_POPMAILDIR_DELIVERY\n\tdepends on BUSYBOX_CONFIG_POPMAILDIR\n\thelp\n\tAllow to use a custom program to filter the content\n\tof the message before actual delivery (-F \"prog [args...]\").\n\tAllow to use a custom program for message actual delivery\n\t(-M \"prog [args...]\").\nconfig BUSYBOX_CONFIG_REFORMIME\n\tbool \"reformime (7.5 kb)\"\n\tdefault BUSYBOX_DEFAULT_REFORMIME\n\thelp\n\tParse MIME-formatted messages.\n\nconfig BUSYBOX_CONFIG_FEATURE_REFORMIME_COMPAT\n\tbool \"Accept and ignore options other than -x and -X\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_REFORMIME_COMPAT\n\tdepends on BUSYBOX_CONFIG_REFORMIME\n\thelp\n\tAccept (for compatibility only) and ignore options\n\tother than -x and -X.\nconfig BUSYBOX_CONFIG_SENDMAIL\n\tbool \"sendmail (14 kb)\"\n\tdefault BUSYBOX_DEFAULT_SENDMAIL\n\thelp\n\tBarebones sendmail.\n\nendmenu\n"
  },
  {
    "path": "package/utils/busybox/config/miscutils/Config.in",
    "content": "# DO NOT EDIT. This file is generated from Config.src\n#\n# For a description of the syntax of this configuration file,\n# see docs/Kconfig-language.txt.\n#\n\nmenu \"Miscellaneous Utilities\"\n\nconfig BUSYBOX_CONFIG_ADJTIMEX\n\tbool \"adjtimex (4.7 kb)\"\n\tdefault BUSYBOX_DEFAULT_ADJTIMEX\n\thelp\n\tAdjtimex reads and optionally sets adjustment parameters for\n\tthe Linux clock adjustment algorithm.\nconfig BUSYBOX_CONFIG_ASCII\n\tbool \"ascii\"\n\tdefault BUSYBOX_DEFAULT_ASCII\n\thelp\n\tPrint ascii table.\n\nconfig BUSYBOX_CONFIG_BBCONFIG\n\tbool \"bbconfig (9.7 kb)\"\n\tdefault BUSYBOX_DEFAULT_BBCONFIG\n\thelp\n\tThe bbconfig applet will print the config file with which\n\tbusybox was built.\n\nconfig BUSYBOX_CONFIG_FEATURE_COMPRESS_BBCONFIG\n\tbool \"Compress bbconfig data\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_COMPRESS_BBCONFIG\n\tdepends on BUSYBOX_CONFIG_BBCONFIG\n\thelp\n\tStore bbconfig data in compressed form, uncompress them on-the-fly\n\tbefore output.\n\n\tIf you have a really tiny busybox with few applets enabled (and\n\tbunzip2 isn't one of them), the overhead of the decompressor might\n\tbe noticeable. Also, if you run executables directly from ROM\n\tand have very little memory, this might not be a win. Otherwise,\n\tyou probably want this.\nconfig BUSYBOX_CONFIG_BC\n\tbool \"bc (45 kb)\"\n\tdefault BUSYBOX_DEFAULT_BC\n\tselect BUSYBOX_CONFIG_FEATURE_DC_BIG\n\thelp\n\tbc is a command-line, arbitrary-precision calculator with a\n\tTuring-complete language. See the GNU bc manual\n\t(https://www.gnu.org/software/bc/manual/bc.html) and bc spec\n\t(http://pubs.opengroup.org/onlinepubs/9699919799/utilities/bc.html).\n\n\tThis bc has five differences to the GNU bc:\n\t  1) The period (.) is a shortcut for \"last\", as in the BSD bc.\n\t  2) Arrays are copied before being passed as arguments to\n\t     functions. This behavior is required by the bc spec.\n\t  3) Arrays can be passed to the builtin \"length\" function to get\n\t     the number of elements in the array. This prints \"1\":\n\t\ta[0] = 0; length(a[])\n\t  4) The precedence of the boolean \"not\" operator (!) is equal to\n\t     that of the unary minus (-) negation operator. This still\n\t     allows POSIX-compliant scripts to work while somewhat\n\t     preserving expected behavior (versus C) and making parsing\n\t     easier.\n\t  5) \"read()\" accepts expressions, not only numeric literals.\n\nconfig BUSYBOX_CONFIG_DC\n\tbool \"dc (36 kb)\"\n\tdefault BUSYBOX_DEFAULT_DC\n\thelp\n\tdc is a reverse-polish notation command-line calculator which\n\tsupports unlimited precision arithmetic. See the FreeBSD man page\n\t(https://www.unix.com/man-page/FreeBSD/1/dc/) and GNU dc manual\n\t(https://www.gnu.org/software/bc/manual/dc-1.05/html_mono/dc.html).\n\n\tThis dc has a few differences from the two above:\n\t  1) When printing a byte stream (command \"P\"), this dc follows what\n\t     the FreeBSD dc does.\n\t  2) Implements the GNU extensions for divmod (\"~\") and\n\t     modular exponentiation (\"|\").\n\t  3) Implements all FreeBSD extensions, except for \"J\" and \"M\".\n\t  4) Like the FreeBSD dc, this dc supports extended registers.\n\t     However, they are implemented differently. When it encounters\n\t     whitespace where a register should be, it skips the whitespace.\n\t     If the character following is not a lowercase letter, an error\n\t     is issued. Otherwise, the register name is parsed by the\n\t     following regex: [a-z][a-z0-9_]*\n\t     This generally means that register names will be surrounded by\n\t     whitespace. Examples:\n\t\tl idx s temp L index S temp2 < do_thing\n\t     Also note that, like the FreeBSD dc, extended registers are not\n\t     allowed unless the \"-x\" option is given.\n\nif BC || BUSYBOX_CONFIG_DC  # for menuconfig indenting\n\nconfig BUSYBOX_CONFIG_FEATURE_DC_BIG\n\tbool \"Use bc code base for dc (larger, more features)\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_DC_BIG\n\nconfig BUSYBOX_CONFIG_FEATURE_DC_LIBM\n\tbool \"Enable power and exp functions (requires libm)\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_DC_LIBM\n\tdepends on BUSYBOX_CONFIG_DC && !BUSYBOX_CONFIG_BC && !BUSYBOX_CONFIG_FEATURE_DC_BIG\n\thelp\n\tEnable power and exp functions.\n\tNOTE: This will require libm to be present for linking.\n\nconfig BUSYBOX_CONFIG_FEATURE_BC_INTERACTIVE\n\tbool \"Interactive mode (+4kb)\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_BC_INTERACTIVE\n\tdepends on BUSYBOX_CONFIG_BC || (BUSYBOX_CONFIG_DC && BUSYBOX_CONFIG_FEATURE_DC_BIG)\n\thelp\n\tEnable interactive mode: when started on a tty,\n\t^C interrupts execution and returns to command line,\n\terrors also return to command line instead of exiting,\n\tline editing with history is available.\n\n\tWith this option off, input can still be taken from tty,\n\tbut all errors are fatal, ^C is fatal,\n\ttty is treated exactly the same as any other\n\tstandard input (IOW: no line editing).\n\nconfig BUSYBOX_CONFIG_FEATURE_BC_LONG_OPTIONS\n\tbool \"Enable bc/dc long options\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_BC_LONG_OPTIONS\n\tdepends on BUSYBOX_CONFIG_BC || (BUSYBOX_CONFIG_DC && BUSYBOX_CONFIG_FEATURE_DC_BIG)\n\nendif\nconfig BUSYBOX_CONFIG_BEEP\n\tbool \"beep (2.4 kb)\"\n\tdefault BUSYBOX_DEFAULT_BEEP\n\thelp\n\tThe beep applets beeps in a given freq/Hz.\n\nconfig BUSYBOX_CONFIG_FEATURE_BEEP_FREQ\n\tint \"default frequency\"\n\trange 20 50000\t# allowing 0 here breaks the build\n\tdefault BUSYBOX_DEFAULT_FEATURE_BEEP_FREQ\n\tdepends on BUSYBOX_CONFIG_BEEP\n\thelp\n\tFrequency for default beep.\n\nconfig BUSYBOX_CONFIG_FEATURE_BEEP_LENGTH_MS\n\tint \"default length\"\n\trange 0 2147483647\n\tdefault BUSYBOX_DEFAULT_FEATURE_BEEP_LENGTH_MS\n\tdepends on BUSYBOX_CONFIG_BEEP\n\thelp\n\tLength in ms for default beep.\nconfig BUSYBOX_CONFIG_CHAT\n\tbool \"chat (6.3 kb)\"\n\tdefault BUSYBOX_DEFAULT_CHAT\n\thelp\n\tSimple chat utility.\n\nconfig BUSYBOX_CONFIG_FEATURE_CHAT_NOFAIL\n\tbool \"Enable NOFAIL expect strings\"\n\tdepends on BUSYBOX_CONFIG_CHAT\n\tdefault BUSYBOX_DEFAULT_FEATURE_CHAT_NOFAIL\n\thelp\n\tWhen enabled expect strings which are started with a dash trigger\n\tno-fail mode. That is when expectation is not met within timeout\n\tthe script is not terminated but sends next SEND string and waits\n\tfor next EXPECT string. This allows to compose far more flexible\n\tscripts.\n\nconfig BUSYBOX_CONFIG_FEATURE_CHAT_TTY_HIFI\n\tbool \"Force STDIN to be a TTY\"\n\tdepends on BUSYBOX_CONFIG_CHAT\n\tdefault BUSYBOX_DEFAULT_FEATURE_CHAT_TTY_HIFI\n\thelp\n\tOriginal chat always treats STDIN as a TTY device and sets for it\n\tso-called raw mode. This option turns on such behaviour.\n\nconfig BUSYBOX_CONFIG_FEATURE_CHAT_IMPLICIT_CR\n\tbool \"Enable implicit Carriage Return\"\n\tdepends on BUSYBOX_CONFIG_CHAT\n\tdefault BUSYBOX_DEFAULT_FEATURE_CHAT_IMPLICIT_CR\n\thelp\n\tWhen enabled make chat to terminate all SEND strings with a \"\\r\"\n\tunless \"\\c\" is met anywhere in the string.\n\nconfig BUSYBOX_CONFIG_FEATURE_CHAT_SWALLOW_OPTS\n\tbool \"Swallow options\"\n\tdepends on BUSYBOX_CONFIG_CHAT\n\tdefault BUSYBOX_DEFAULT_FEATURE_CHAT_SWALLOW_OPTS\n\thelp\n\tBusybox chat require no options. To make it not fail when used\n\tin place of original chat (which has a bunch of options) turn\n\tthis on.\n\nconfig BUSYBOX_CONFIG_FEATURE_CHAT_SEND_ESCAPES\n\tbool \"Support weird SEND escapes\"\n\tdepends on BUSYBOX_CONFIG_CHAT\n\tdefault BUSYBOX_DEFAULT_FEATURE_CHAT_SEND_ESCAPES\n\thelp\n\tOriginal chat uses some escape sequences in SEND arguments which\n\tare not sent to device but rather performs special actions.\n\tE.g. \"\\K\" means to send a break sequence to device.\n\t\"\\d\" delays execution for a second, \"\\p\" -- for a 1/100 of second.\n\tBefore turning this option on think twice: do you really need them?\n\nconfig BUSYBOX_CONFIG_FEATURE_CHAT_VAR_ABORT_LEN\n\tbool \"Support variable-length ABORT conditions\"\n\tdepends on BUSYBOX_CONFIG_CHAT\n\tdefault BUSYBOX_DEFAULT_FEATURE_CHAT_VAR_ABORT_LEN\n\thelp\n\tOriginal chat uses fixed 50-bytes length ABORT conditions. Say N here.\n\nconfig BUSYBOX_CONFIG_FEATURE_CHAT_CLR_ABORT\n\tbool \"Support revoking of ABORT conditions\"\n\tdepends on BUSYBOX_CONFIG_CHAT\n\tdefault BUSYBOX_DEFAULT_FEATURE_CHAT_CLR_ABORT\n\thelp\n\tSupport CLR_ABORT directive.\nconfig BUSYBOX_CONFIG_CONSPY\n\tbool \"conspy (10 kb)\"\n\tdefault BUSYBOX_DEFAULT_CONSPY\n\thelp\n\tA text-mode VNC like program for Linux virtual terminals.\n\texample:  conspy NUM      shared access to console num\n\tor        conspy -nd NUM  screenshot of console num\n\tor        conspy -cs NUM  poor man's GNU screen like\nconfig BUSYBOX_CONFIG_CROND\n\tbool \"crond (14 kb)\"\n\tdefault BUSYBOX_DEFAULT_CROND\n\tselect BUSYBOX_CONFIG_FEATURE_SYSLOG\n\thelp\n\tCrond is a background daemon that parses individual crontab\n\tfiles and executes commands on behalf of the users in question.\n\tThis is a port of dcron from slackware. It uses files of the\n\tformat /var/spool/cron/crontabs/<username> files, for example:\n\t\t$ cat /var/spool/cron/crontabs/root\n\t\t# Run daily cron jobs at 4:40 every day:\n\t\t40 4 * * * /etc/cron/daily > /dev/null 2>&1\n\nconfig BUSYBOX_CONFIG_FEATURE_CROND_D\n\tbool \"Support -d (redirect output to stderr)\"\n\tdepends on BUSYBOX_CONFIG_CROND\n\tdefault BUSYBOX_DEFAULT_FEATURE_CROND_D\n\thelp\n\t-d N sets loglevel (0:most verbose) and directs all output to stderr.\n\nconfig BUSYBOX_CONFIG_FEATURE_CROND_CALL_SENDMAIL\n\tbool \"Report command output via email (using sendmail)\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_CROND_CALL_SENDMAIL\n\tdepends on BUSYBOX_CONFIG_CROND\n\thelp\n\tCommand output will be sent to corresponding user via email.\n\nconfig BUSYBOX_CONFIG_FEATURE_CROND_SPECIAL_TIMES\n\tbool \"Support special times (@reboot, @daily, etc) in crontabs\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_CROND_SPECIAL_TIMES\n\tdepends on BUSYBOX_CONFIG_CROND\n\thelp\n\tstring        meaning\n\t------        -------\n\t@reboot       Run once, at startup\n\t@yearly       Run once a year:  \"0 0 1 1 *\"\n\t@annually     Same as @yearly:  \"0 0 1 1 *\"\n\t@monthly      Run once a month: \"0 0 1 * *\"\n\t@weekly       Run once a week:  \"0 0 * * 0\"\n\t@daily        Run once a day:   \"0 0 * * *\"\n\t@midnight     Same as @daily:   \"0 0 * * *\"\n\t@hourly       Run once an hour: \"0 * * * *\"\n\nconfig BUSYBOX_CONFIG_FEATURE_CROND_DIR\n\tstring \"crond spool directory\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_CROND_DIR\n\tdepends on BUSYBOX_CONFIG_CROND || BUSYBOX_CONFIG_CRONTAB\n\thelp\n\tLocation of crond spool.\nconfig BUSYBOX_CONFIG_CRONTAB\n\tbool \"crontab (10 kb)\"\n\tdefault BUSYBOX_DEFAULT_CRONTAB\n\thelp\n\tCrontab manipulates the crontab for a particular user. Only\n\tthe superuser may specify a different user and/or crontab directory.\n\tNote that busybox binary must be setuid root for this applet to\n\twork properly.\nconfig BUSYBOX_CONFIG_DEVFSD\n\tbool \"devfsd (obsolete)\"\n\tdefault BUSYBOX_DEFAULT_DEVFSD\n\tselect BUSYBOX_CONFIG_FEATURE_SYSLOG\n\thelp\n\tThis is deprecated and should NOT be used anymore.\n\tUse linux >= 2.6 (optionally with hotplug) and mdev instead!\n\tSee docs/mdev.txt for detailed instructions on how to use mdev\n\tinstead.\n\n\tProvides compatibility with old device names on a devfs systems.\n\tYou should set it to true if you have devfs enabled.\n\tThe following keywords in devsfd.conf are supported:\n\t\"CLEAR_CONFIG\", \"INCLUDE\", \"OPTIONAL_INCLUDE\", \"RESTORE\",\n\t\"PERMISSIONS\", \"EXECUTE\", \"COPY\", \"IGNORE\",\n\t\"MKOLDCOMPAT\", \"MKNEWCOMPAT\",\"RMOLDCOMPAT\", \"RMNEWCOMPAT\".\n\n\tBut only if they are written UPPERCASE!!!!!!!!\n\nconfig BUSYBOX_CONFIG_DEVFSD_MODLOAD\n\tbool \"Adds support for MODLOAD keyword in devsfd.conf\"\n\tdefault BUSYBOX_DEFAULT_DEVFSD_MODLOAD\n\tdepends on BUSYBOX_CONFIG_DEVFSD\n\thelp\n\tThis actually doesn't work with busybox modutils but needs\n\tthe external modutils.\n\nconfig BUSYBOX_CONFIG_DEVFSD_FG_NP\n\tbool \"Enable the -fg and -np options\"\n\tdefault BUSYBOX_DEFAULT_DEVFSD_FG_NP\n\tdepends on BUSYBOX_CONFIG_DEVFSD\n\thelp\n\t-fg  Run the daemon in the foreground.\n\t-np  Exit after parsing config. Do not poll for events.\n\nconfig BUSYBOX_CONFIG_DEVFSD_VERBOSE\n\tbool \"Increases logging (and size)\"\n\tdefault BUSYBOX_DEFAULT_DEVFSD_VERBOSE\n\tdepends on BUSYBOX_CONFIG_DEVFSD\n\thelp\n\tIncreases logging to stderr or syslog.\n\nconfig BUSYBOX_CONFIG_FEATURE_DEVFS\n\tbool \"Use devfs names for all devices (obsolete)\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_DEVFS\n\thelp\n\tThis is obsolete and should NOT be used anymore.\n\tUse linux >= 2.6 (optionally with hotplug) and mdev instead!\n\n\tFor legacy systems -- if there is no way around devfsd -- this\n\ttells busybox to look for names like /dev/loop/0 instead of\n\t/dev/loop0. If your /dev directory has normal names instead of\n\tdevfs names, you don't want this.\nconfig BUSYBOX_CONFIG_DEVMEM\n\tbool \"devmem (2.5 kb)\"\n\tdefault BUSYBOX_DEFAULT_DEVMEM\n\thelp\n\tdevmem is a small program that reads and writes from physical\n\tmemory using /dev/mem.\nconfig BUSYBOX_CONFIG_FBSPLASH\n\tbool \"fbsplash (26 kb)\"\n\tdefault BUSYBOX_DEFAULT_FBSPLASH\n\thelp\n\tShows splash image and progress bar on framebuffer device.\n\tCan be used during boot phase of an embedded device.\n\tUsage:\n\t- use kernel option 'vga=xxx' or otherwise enable fb device.\n\t- put somewhere fbsplash.cfg file and an image in .ppm format.\n\t- $ setsid fbsplash [params] &\n\t    -c: hide cursor\n\t    -d /dev/fbN: framebuffer device (if not /dev/fb0)\n\t    -s path_to_image_file (can be \"-\" for stdin)\n\t    -i path_to_cfg_file (can be \"-\" for stdin)\n\t    -f path_to_fifo (can be \"-\" for stdin)\n\t- if you want to run it only in presence of kernel parameter:\n\t    grep -q \"fbsplash=on\" </proc/cmdline && setsid fbsplash [params] &\n\t- commands for fifo:\n\t    \"NN\" (ASCII decimal number) - percentage to show on progress bar\n\t    \"exit\" - well you guessed it\nconfig BUSYBOX_CONFIG_FLASH_ERASEALL\n\tbool \"flash_eraseall (5.9 kb)\"\n\tdefault BUSYBOX_DEFAULT_FLASH_ERASEALL  # doesn't build on Ubuntu 8.04\n\thelp\n\tThe flash_eraseall binary from mtd-utils as of git head c4c6a59eb.\n\tThis utility is used to erase the whole MTD device.\nconfig BUSYBOX_CONFIG_FLASH_LOCK\n\tbool \"flash_lock (2.1 kb)\"\n\tdefault BUSYBOX_DEFAULT_FLASH_LOCK  # doesn't build on Ubuntu 8.04\n\thelp\n\tThe flash_lock binary from mtd-utils as of git head 5ec0c10d0. This\n\tutility locks part or all of the flash device.\n\nconfig BUSYBOX_CONFIG_FLASH_UNLOCK\n\tbool \"flash_unlock (1.3 kb)\"\n\tdefault BUSYBOX_DEFAULT_FLASH_UNLOCK  # doesn't build on Ubuntu 8.04\n\thelp\n\tThe flash_unlock binary from mtd-utils as of git head 5ec0c10d0. This\n\tutility unlocks part or all of the flash device.\nconfig BUSYBOX_CONFIG_FLASHCP\n\tbool \"flashcp (5.3 kb)\"\n\tdefault BUSYBOX_DEFAULT_FLASHCP  # doesn't build on Ubuntu 8.04\n\thelp\n\tThe flashcp binary, inspired by mtd-utils as of git head 5eceb74f7.\n\tThis utility is used to copy images into a MTD device.\nconfig BUSYBOX_CONFIG_HDPARM\n\tbool \"hdparm (25 kb)\"\n\tdefault BUSYBOX_DEFAULT_HDPARM\n\thelp\n\tGet/Set hard drive parameters. Primarily intended for ATA\n\tdrives.\n\nconfig BUSYBOX_CONFIG_FEATURE_HDPARM_GET_IDENTITY\n\tbool \"Support obtaining detailed information directly from drives\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_HDPARM_GET_IDENTITY\n\tdepends on BUSYBOX_CONFIG_HDPARM\n\thelp\n\tEnable the -I and -i options to obtain detailed information\n\tdirectly from drives about their capabilities and supported ATA\n\tfeature set. If no device name is specified, hdparm will read\n\tidentify data from stdin. Enabling this option will add about 16k...\n\nconfig BUSYBOX_CONFIG_FEATURE_HDPARM_HDIO_SCAN_HWIF\n\tbool \"Register an IDE interface (DANGEROUS)\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_HDPARM_HDIO_SCAN_HWIF\n\tdepends on BUSYBOX_CONFIG_HDPARM\n\thelp\n\tEnable the 'hdparm -R' option to register an IDE interface.\n\tThis is dangerous stuff, so you should probably say N.\n\nconfig BUSYBOX_CONFIG_FEATURE_HDPARM_HDIO_UNREGISTER_HWIF\n\tbool \"Un-register an IDE interface (DANGEROUS)\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_HDPARM_HDIO_UNREGISTER_HWIF\n\tdepends on BUSYBOX_CONFIG_HDPARM\n\thelp\n\tEnable the 'hdparm -U' option to un-register an IDE interface.\n\tThis is dangerous stuff, so you should probably say N.\n\nconfig BUSYBOX_CONFIG_FEATURE_HDPARM_HDIO_DRIVE_RESET\n\tbool \"Perform device reset (DANGEROUS)\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_HDPARM_HDIO_DRIVE_RESET\n\tdepends on BUSYBOX_CONFIG_HDPARM\n\thelp\n\tEnable the 'hdparm -w' option to perform a device reset.\n\tThis is dangerous stuff, so you should probably say N.\n\nconfig BUSYBOX_CONFIG_FEATURE_HDPARM_HDIO_TRISTATE_HWIF\n\tbool \"Tristate device for hotswap (DANGEROUS)\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_HDPARM_HDIO_TRISTATE_HWIF\n\tdepends on BUSYBOX_CONFIG_HDPARM\n\thelp\n\tEnable the 'hdparm -x' option to tristate device for hotswap,\n\tand the '-b' option to get/set bus state. This is dangerous\n\tstuff, so you should probably say N.\n\nconfig BUSYBOX_CONFIG_FEATURE_HDPARM_HDIO_GETSET_DMA\n\tbool \"Get/set using_dma flag\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_HDPARM_HDIO_GETSET_DMA\n\tdepends on BUSYBOX_CONFIG_HDPARM\n\thelp\n\tEnable the 'hdparm -d' option to get/set using_dma flag.\nconfig BUSYBOX_CONFIG_HEXEDIT\n\tbool \"hexedit (21 kb)\"\n\tdefault BUSYBOX_DEFAULT_HEXEDIT\n\thelp\n\tEdit file in hexadecimal.\nconfig BUSYBOX_CONFIG_I2CGET\n\tbool \"i2cget (5.5 kb)\"\n\tdefault BUSYBOX_DEFAULT_I2CGET\n\thelp\n\tRead from I2C/SMBus chip registers.\n\nconfig BUSYBOX_CONFIG_I2CSET\n\tbool \"i2cset (6.7 kb)\"\n\tdefault BUSYBOX_DEFAULT_I2CSET\n\thelp\n\tSet I2C registers.\n\nconfig BUSYBOX_CONFIG_I2CDUMP\n\tbool \"i2cdump (7.1 kb)\"\n\tdefault BUSYBOX_DEFAULT_I2CDUMP\n\thelp\n\tExamine I2C registers.\n\nconfig BUSYBOX_CONFIG_I2CDETECT\n\tbool \"i2cdetect (7.1 kb)\"\n\tdefault BUSYBOX_DEFAULT_I2CDETECT\n\thelp\n\tDetect I2C chips.\n\nconfig BUSYBOX_CONFIG_I2CTRANSFER\n\tbool \"i2ctransfer (4.0 kb)\"\n\tdefault BUSYBOX_DEFAULT_I2CTRANSFER\n\thelp\n\tSend user-defined I2C messages in one transfer.\n\nconfig BUSYBOX_CONFIG_INOTIFYD\n\tbool \"inotifyd (3.6 kb)\"\n\tdefault BUSYBOX_DEFAULT_INOTIFYD  # doesn't build on Knoppix 5\n\thelp\n\tSimple inotify daemon. Reports filesystem changes. Requires\n\tkernel >= 2.6.13\nconfig BUSYBOX_CONFIG_LESS\n\tbool \"less (16 kb)\"\n\tdefault BUSYBOX_DEFAULT_LESS\n\thelp\n\t'less' is a pager, meaning that it displays text files. It possesses\n\ta wide array of features, and is an improvement over 'more'.\n\nconfig BUSYBOX_CONFIG_FEATURE_LESS_MAXLINES\n\tint \"Max number of input lines less will try to eat\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_LESS_MAXLINES\n\tdepends on BUSYBOX_CONFIG_LESS\n\nconfig BUSYBOX_CONFIG_FEATURE_LESS_BRACKETS\n\tbool \"Enable bracket searching\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_LESS_BRACKETS\n\tdepends on BUSYBOX_CONFIG_LESS\n\thelp\n\tThis option adds the capability to search for matching left and right\n\tbrackets, facilitating programming.\n\nconfig BUSYBOX_CONFIG_FEATURE_LESS_FLAGS\n\tbool \"Enable -m/-M\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_LESS_FLAGS\n\tdepends on BUSYBOX_CONFIG_LESS\n\thelp\n\tThe -M/-m flag enables a more sophisticated status line.\n\nconfig BUSYBOX_CONFIG_FEATURE_LESS_TRUNCATE\n\tbool \"Enable -S\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_LESS_TRUNCATE\n\tdepends on BUSYBOX_CONFIG_LESS\n\thelp\n\tThe -S flag causes long lines to be truncated rather than\n\twrapped.\n\nconfig BUSYBOX_CONFIG_FEATURE_LESS_MARKS\n\tbool \"Enable marks\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_LESS_MARKS\n\tdepends on BUSYBOX_CONFIG_LESS\n\thelp\n\tMarks enable positions in a file to be stored for easy reference.\n\nconfig BUSYBOX_CONFIG_FEATURE_LESS_REGEXP\n\tbool \"Enable regular expressions\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_LESS_REGEXP\n\tdepends on BUSYBOX_CONFIG_LESS\n\thelp\n\tEnable regular expressions, allowing complex file searches.\n\nconfig BUSYBOX_CONFIG_FEATURE_LESS_WINCH\n\tbool \"Enable automatic resizing on window size changes\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_LESS_WINCH\n\tdepends on BUSYBOX_CONFIG_LESS\n\thelp\n\tMakes less track window size changes.\n\nconfig BUSYBOX_CONFIG_FEATURE_LESS_ASK_TERMINAL\n\tbool \"Use 'tell me cursor position' ESC sequence to measure window\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_LESS_ASK_TERMINAL\n\tdepends on BUSYBOX_CONFIG_FEATURE_LESS_WINCH\n\thelp\n\tMakes less track window size changes.\n\tIf terminal size can't be retrieved and $LINES/$COLUMNS are not set,\n\tthis option makes less perform a last-ditch effort to find it:\n\tposition cursor to 999,999 and ask terminal to report real\n\tcursor position using \"ESC [ 6 n\" escape sequence, then read stdin.\n\tThis is not clean but helps a lot on serial lines and such.\n\nconfig BUSYBOX_CONFIG_FEATURE_LESS_DASHCMD\n\tbool \"Enable flag changes ('-' command)\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_LESS_DASHCMD\n\tdepends on BUSYBOX_CONFIG_LESS\n\thelp\n\tThis enables the ability to change command-line flags within\n\tless itself ('-' keyboard command).\n\nconfig BUSYBOX_CONFIG_FEATURE_LESS_LINENUMS\n\tbool \"Enable -N (dynamic switching of line numbers)\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_LESS_LINENUMS\n\tdepends on BUSYBOX_CONFIG_FEATURE_LESS_DASHCMD\n\nconfig BUSYBOX_CONFIG_FEATURE_LESS_RAW\n\tbool \"Enable -R ('raw control characters')\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_LESS_RAW\n\tdepends on BUSYBOX_CONFIG_FEATURE_LESS_DASHCMD\n\thelp\n\tThis is essential for less applet to work with tools that use colors\n\tand paging, such as git, systemd tools or nmcli.\n\nconfig BUSYBOX_CONFIG_FEATURE_LESS_ENV\n\tbool \"Take options from $LESS environment variable\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_LESS_ENV\n\tdepends on BUSYBOX_CONFIG_FEATURE_LESS_DASHCMD\n\thelp\n\tThis is essential for less applet to work with tools that use colors\n\tand paging, such as git, systemd tools or nmcli.\nconfig BUSYBOX_CONFIG_LOCK\n\tbool \"lock\"\n\tdefault BUSYBOX_DEFAULT_LOCK\n\thelp\n\t  Small utility for using locks in scripts\nconfig BUSYBOX_CONFIG_LSSCSI\n\tbool \"lsscsi (2.5 kb)\"\n\tdefault BUSYBOX_DEFAULT_LSSCSI\n\thelp\n\tlsscsi is a utility for displaying information about SCSI buses in the\n\tsystem and devices connected to them.\n\n\tThis version uses sysfs (/sys/bus/scsi/devices) only.\nconfig BUSYBOX_CONFIG_MAKEDEVS\n\tbool \"makedevs (9.2 kb)\"\n\tdefault BUSYBOX_DEFAULT_MAKEDEVS\n\thelp\n\t'makedevs' is a utility used to create a batch of devices with\n\tone command.\n\n\tThere are two choices for command line behaviour, the interface\n\tas used by LEAF/Linux Router Project, or a device table file.\n\n\t'leaf' is traditionally what busybox follows, it allows multiple\n\tdevices of a particluar type to be created per command.\n\te.g. /dev/hda[0-9]\n\tDevice properties are passed as command line arguments.\n\n\t'table' reads device properties from a file or stdin, allowing\n\ta batch of unrelated devices to be made with one command.\n\tUser/group names are allowed as an alternative to uid/gid.\n\nchoice\n\tprompt \"Choose makedevs behaviour\"\n\tdepends on BUSYBOX_CONFIG_MAKEDEVS\n\tdefault BUSYBOX_CONFIG_FEATURE_MAKEDEVS_TABLE\n\nconfig BUSYBOX_CONFIG_FEATURE_MAKEDEVS_LEAF\n\tbool \"leaf\"\n\nconfig BUSYBOX_CONFIG_FEATURE_MAKEDEVS_TABLE\n\tbool \"table\"\n\nendchoice\nconfig BUSYBOX_CONFIG_MAN\n\tbool \"man (26 kb)\"\n\tdefault BUSYBOX_DEFAULT_MAN\n\thelp\n\tFormat and display manual pages.\nconfig BUSYBOX_CONFIG_MICROCOM\n\tbool \"microcom (5.7 kb)\"\n\tdefault BUSYBOX_DEFAULT_MICROCOM\n\thelp\n\tThe poor man's minicom utility for chatting with serial port devices.\nconfig BUSYBOX_CONFIG_MIM\n\tbool \"mim (0.5 kb)\"\n\tdefault BUSYBOX_DEFAULT_MIM\n\tdepends on BUSYBOX_CONFIG_FEATURE_SH_EMBEDDED_SCRIPTS\n\thelp\n\tRun a script from a Makefile-like specification file.\n\tUnlike 'make' dependencies aren't supported.\nconfig BUSYBOX_CONFIG_MT\n\tbool \"mt (2.5 kb)\"\n\tdefault BUSYBOX_DEFAULT_MT\n\thelp\n\tmt is used to control tape devices. You can use the mt utility\n\tto advance or rewind a tape past a specified number of archive\n\tfiles on the tape.\nconfig BUSYBOX_CONFIG_NANDWRITE\n\tbool \"nandwrite (4.8 kb)\"\n\tdefault BUSYBOX_DEFAULT_NANDWRITE\n\thelp\n\tWrite to the specified MTD device, with bad blocks awareness\n\nconfig BUSYBOX_CONFIG_NANDDUMP\n\tbool \"nanddump (5.2 kb)\"\n\tdefault BUSYBOX_DEFAULT_NANDDUMP\n\thelp\n\tDump the content of raw NAND chip\nconfig BUSYBOX_CONFIG_PARTPROBE\n\tbool \"partprobe (3.5 kb)\"\n\tdefault BUSYBOX_DEFAULT_PARTPROBE\n\thelp\n\tAsk kernel to rescan partition table.\nconfig BUSYBOX_CONFIG_RAIDAUTORUN\n\tbool \"raidautorun (1.3 kb)\"\n\tdefault BUSYBOX_DEFAULT_RAIDAUTORUN\n\thelp\n\traidautorun tells the kernel md driver to\n\tsearch and start RAID arrays.\nconfig BUSYBOX_CONFIG_READAHEAD\n\tbool \"readahead (1.5 kb)\"\n\tdefault BUSYBOX_DEFAULT_READAHEAD\n\tdepends on BUSYBOX_CONFIG_LFS\n\thelp\n\tPreload the files listed on the command line into RAM cache so that\n\tsubsequent reads on these files will not block on disk I/O.\n\n\tThis applet just calls the readahead(2) system call on each file.\n\tIt is mainly useful in system startup scripts to preload files\n\tor executables before they are used. When used at the right time\n\t(in particular when a CPU bound process is running) it can\n\tsignificantly speed up system startup.\n\n\tAs readahead(2) blocks until each file has been read, it is best to\n\trun this applet as a background job.\nconfig BUSYBOX_CONFIG_RFKILL\n\tbool \"rfkill (4.4 kb)\"\n\tdefault BUSYBOX_DEFAULT_RFKILL # doesn't build on Ubuntu 9.04\n\thelp\n\tEnable/disable wireless devices.\n\n\trfkill list : list all wireless devices\n\trfkill list bluetooth : list all bluetooth devices\n\trfkill list 1 : list device corresponding to the given index\n\trfkill block|unblock wlan : block/unblock all wlan(wifi) devices\n\nconfig BUSYBOX_CONFIG_RUNLEVEL\n\tbool \"runlevel (559 bytes)\"\n\tdefault BUSYBOX_DEFAULT_RUNLEVEL\n\tdepends on BUSYBOX_CONFIG_FEATURE_UTMP\n\thelp\n\tFind the current and previous system runlevel.\n\n\tThis applet uses utmp but does not rely on busybox supporing\n\tutmp on purpose. It is used by e.g. emdebian via /etc/init.d/rc.\nconfig BUSYBOX_CONFIG_RX\n\tbool \"rx (2.9 kb)\"\n\tdefault BUSYBOX_DEFAULT_RX\n\thelp\n\tReceive files using the Xmodem protocol.\nconfig BUSYBOX_CONFIG_SETFATTR\n\tbool \"setfattr (3.7 kb)\"\n\tdefault BUSYBOX_DEFAULT_SETFATTR\n\thelp\n\tSet/delete extended attributes on files\nconfig BUSYBOX_CONFIG_SETSERIAL\n\tbool \"setserial (6.9 kb)\"\n\tdefault BUSYBOX_DEFAULT_SETSERIAL\n\thelp\n\tRetrieve or set Linux serial port.\nconfig BUSYBOX_CONFIG_STRINGS\n\tbool \"strings (4.6 kb)\"\n\tdefault BUSYBOX_DEFAULT_STRINGS\n\thelp\n\tstrings prints the printable character sequences for each file\n\tspecified.\nconfig BUSYBOX_CONFIG_TIME\n\tbool \"time (6.8 kb)\"\n\tdefault BUSYBOX_DEFAULT_TIME\n\thelp\n\tThe time command runs the specified program with the given arguments.\n\tWhen the command finishes, time writes a message to standard output\n\tgiving timing statistics about this program run.\nconfig BUSYBOX_CONFIG_TS\n\tbool \"ts (450 bytes)\"\n\tdefault BUSYBOX_DEFAULT_TS\nconfig BUSYBOX_CONFIG_TTYSIZE\n\tbool \"ttysize (432 bytes)\"\n\tdefault BUSYBOX_DEFAULT_TTYSIZE\n\thelp\n\tA replacement for \"stty size\". Unlike stty, can report only width,\n\tonly height, or both, in any order. It also does not complain on\n\terror, but returns default 80x24.\n\tUsage in shell scripts: width=`ttysize w`.\nconfig BUSYBOX_CONFIG_UBIATTACH\n\tbool \"ubiattach (4.2 kb)\"\n\tdefault BUSYBOX_DEFAULT_UBIATTACH\n\thelp\n\tAttach MTD device to an UBI device.\n\nconfig BUSYBOX_CONFIG_UBIDETACH\n\tbool \"ubidetach (4.1 kb)\"\n\tdefault BUSYBOX_DEFAULT_UBIDETACH\n\thelp\n\tDetach MTD device from an UBI device.\n\nconfig BUSYBOX_CONFIG_UBIMKVOL\n\tbool \"ubimkvol (5.3 kb)\"\n\tdefault BUSYBOX_DEFAULT_UBIMKVOL\n\thelp\n\tCreate a UBI volume.\n\nconfig BUSYBOX_CONFIG_UBIRMVOL\n\tbool \"ubirmvol (4.9 kb)\"\n\tdefault BUSYBOX_DEFAULT_UBIRMVOL\n\thelp\n\tDelete a UBI volume.\n\nconfig BUSYBOX_CONFIG_UBIRSVOL\n\tbool \"ubirsvol (4.2 kb)\"\n\tdefault BUSYBOX_DEFAULT_UBIRSVOL\n\thelp\n\tResize a UBI volume.\n\nconfig BUSYBOX_CONFIG_UBIUPDATEVOL\n\tbool \"ubiupdatevol (5.2 kb)\"\n\tdefault BUSYBOX_DEFAULT_UBIUPDATEVOL\n\thelp\n\tUpdate a UBI volume.\nconfig BUSYBOX_CONFIG_UBIRENAME\n\tbool \"ubirename (2.4 kb)\"\n\tdefault BUSYBOX_DEFAULT_UBIRENAME\n\thelp\n\tUtility to rename UBI volumes\nconfig BUSYBOX_CONFIG_VOLNAME\n\tbool \"volname (1.6 kb)\"\n\tdefault BUSYBOX_DEFAULT_VOLNAME\n\thelp\n\tPrints a CD-ROM volume name.\nconfig BUSYBOX_CONFIG_WATCHDOG\n\tbool \"watchdog (5.3 kb)\"\n\tdefault BUSYBOX_DEFAULT_WATCHDOG\n\thelp\n\tThe watchdog utility is used with hardware or software watchdog\n\tdevice drivers. It opens the specified watchdog device special file\n\tand periodically writes a magic character to the device. If the\n\twatchdog applet ever fails to write the magic character within a\n\tcertain amount of time, the watchdog device assumes the system has\n\thung, and will cause the hardware to reboot.\n\nconfig BUSYBOX_CONFIG_FEATURE_WATCHDOG_OPEN_TWICE\n\tbool \"Open watchdog device twice, closing it gracefully in between\"\n\tdepends on BUSYBOX_CONFIG_WATCHDOG\n\tdefault BUSYBOX_DEFAULT_FEATURE_WATCHDOG_OPEN_TWICE   # this behavior was essentially a hack for a broken driver\n\thelp\n\tWhen enabled, the watchdog device is opened and then immediately\n\tmagic-closed, before being opened a second time. This may be necessary\n\tfor some watchdog devices, but can cause spurious warnings in the\n\tkernel log if the nowayout feature is enabled. If this workaround\n\tis really needed for you machine to work properly, consider whether\n\tit should be fixed in the kernel driver instead. Even when disabled,\n\tthe behaviour is easily emulated with a \"printf 'V' > /dev/watchdog\"\n\timmediately before starting the busybox watchdog daemon. Say n unless\n\tyou know that you absolutely need this.\n\nendmenu\n"
  },
  {
    "path": "package/utils/busybox/config/modutils/Config.in",
    "content": "# DO NOT EDIT. This file is generated from Config.src\n#\n# For a description of the syntax of this configuration file,\n# see docs/Kconfig-language.txt.\n#\n\nmenu \"Linux Module Utilities\"\n\nconfig BUSYBOX_CONFIG_MODPROBE_SMALL\n\tbool \"Simplified modutils\"\n\tdefault BUSYBOX_DEFAULT_MODPROBE_SMALL\n\thelp\n\tBuild smaller (~1.5 kbytes), simplified module tools.\n\n\tThis option by itself does not enable any applets -\n\tyou need to select applets individually below.\n\n\tWith this option modprobe does not require modules.dep file\n\tand does not use /etc/modules.conf file.\n\tIt scans module files in /lib/modules/`uname -r` and\n\tdetermines dependencies and module alias names on the fly.\n\tThis may make module loading slower, most notably\n\twhen one needs to load module by alias (this requires\n\tscanning through module _bodies_).\n\n\tAt the first attempt to load a module by alias modprobe\n\twill try to generate modules.dep.bb file in order to speed up\n\tfuture loads by alias. Failure to do so (read-only /lib/modules,\n\tetc) is not reported, and future modprobes will be slow too.\n\n\tNB: modules.dep.bb file format is not compatible\n\twith modules.dep file as created/used by standard module tools.\n\n\tAdditional module parameters can be stored in\n\t/etc/modules/$module_name files.\n\nconfig BUSYBOX_CONFIG_DEPMOD\n\tbool \"depmod (27 kb)\"\n\tdefault BUSYBOX_DEFAULT_DEPMOD\n\thelp\n\tdepmod generates modules.dep (and potentially modules.alias\n\tand modules.symbols) that contain dependency information\n\tfor modprobe.\nconfig BUSYBOX_CONFIG_INSMOD\n\tbool \"insmod (22 kb)\"\n\tdefault BUSYBOX_DEFAULT_INSMOD\n\thelp\n\tinsmod is used to load specified modules in the running kernel.\nconfig BUSYBOX_CONFIG_LSMOD\n\tbool \"lsmod (1.9 kb)\"\n\tdefault BUSYBOX_DEFAULT_LSMOD\n\thelp\n\tlsmod is used to display a list of loaded modules.\n\nconfig BUSYBOX_CONFIG_FEATURE_LSMOD_PRETTY_2_6_OUTPUT\n\tbool \"Pretty output\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_LSMOD_PRETTY_2_6_OUTPUT\n\tdepends on BUSYBOX_CONFIG_LSMOD && !BUSYBOX_CONFIG_MODPROBE_SMALL\n\thelp\n\tThis option makes output format of lsmod adjusted to\n\tthe format of module-init-tools for Linux kernel 2.6.\n\tIncreases size somewhat.\nconfig BUSYBOX_CONFIG_MODINFO\n\tbool \"modinfo (24 kb)\"\n\tdefault BUSYBOX_DEFAULT_MODINFO\n\thelp\n\tShow information about a Linux Kernel module\nconfig BUSYBOX_CONFIG_MODPROBE\n\tbool \"modprobe (28 kb)\"\n\tdefault BUSYBOX_DEFAULT_MODPROBE\n\thelp\n\tHandle the loading of modules, and their dependencies on a high\n\tlevel.\n\nconfig BUSYBOX_CONFIG_FEATURE_MODPROBE_BLACKLIST\n\tbool \"Blacklist support\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_MODPROBE_BLACKLIST\n\tdepends on BUSYBOX_CONFIG_MODPROBE && !BUSYBOX_CONFIG_MODPROBE_SMALL\n\thelp\n\tSay 'y' here to enable support for the 'blacklist' command in\n\tmodprobe.conf. This prevents the alias resolver to resolve\n\tblacklisted modules. This is useful if you want to prevent your\n\thardware autodetection scripts to load modules like evdev, frame\n\tbuffer drivers etc.\nconfig BUSYBOX_CONFIG_RMMOD\n\tbool \"rmmod (3.3 kb)\"\n\tdefault BUSYBOX_DEFAULT_RMMOD\n\thelp\n\trmmod is used to unload specified modules from the kernel.\n\ncomment \"Options common to multiple modutils\"\n\nconfig BUSYBOX_CONFIG_FEATURE_CMDLINE_MODULE_OPTIONS\n\tbool \"Accept module options on modprobe command line\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_CMDLINE_MODULE_OPTIONS\n\tdepends on BUSYBOX_CONFIG_INSMOD || BUSYBOX_CONFIG_MODPROBE\n\thelp\n\tAllow insmod and modprobe take module options from the applets'\n\tcommand line.\n\nconfig BUSYBOX_CONFIG_FEATURE_MODPROBE_SMALL_CHECK_ALREADY_LOADED\n\tbool \"Skip loading of already loaded modules\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_MODPROBE_SMALL_CHECK_ALREADY_LOADED\n\tdepends on BUSYBOX_CONFIG_MODPROBE_SMALL && (BUSYBOX_CONFIG_DEPMOD || BUSYBOX_CONFIG_INSMOD || BUSYBOX_CONFIG_MODPROBE)\n\thelp\n\tCheck if the module is already loaded.\n\nconfig BUSYBOX_CONFIG_FEATURE_2_4_MODULES\n\tbool \"Support version 2.2/2.4 Linux kernels\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_2_4_MODULES\n\tdepends on (BUSYBOX_CONFIG_INSMOD || BUSYBOX_CONFIG_LSMOD || BUSYBOX_CONFIG_MODPROBE || BUSYBOX_CONFIG_RMMOD) && !BUSYBOX_CONFIG_MODPROBE_SMALL\n\thelp\n\tSupport module loading for 2.2.x and 2.4.x Linux kernels.\n\tThis increases size considerably. Say N unless you plan\n\tto run ancient kernels.\n\nconfig BUSYBOX_CONFIG_FEATURE_INSMOD_VERSION_CHECKING\n\tbool \"Enable module version checking\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_INSMOD_VERSION_CHECKING\n\tdepends on BUSYBOX_CONFIG_FEATURE_2_4_MODULES && (BUSYBOX_CONFIG_INSMOD || BUSYBOX_CONFIG_MODPROBE)\n\thelp\n\tSupport checking of versions for modules. This is used to\n\tensure that the kernel and module are made for each other.\n\nconfig BUSYBOX_CONFIG_FEATURE_INSMOD_KSYMOOPS_SYMBOLS\n\tbool \"Add module symbols to kernel symbol table\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_INSMOD_KSYMOOPS_SYMBOLS\n\tdepends on BUSYBOX_CONFIG_FEATURE_2_4_MODULES && (BUSYBOX_CONFIG_INSMOD || BUSYBOX_CONFIG_MODPROBE)\n\thelp\n\tBy adding module symbols to the kernel symbol table, Oops messages\n\toccurring within kernel modules can be properly debugged. By enabling\n\tthis feature, module symbols will always be added to the kernel symbol\n\ttable for proper debugging support. If you are not interested in\n\tOops messages from kernel modules, say N.\n\nconfig BUSYBOX_CONFIG_FEATURE_INSMOD_LOADINKMEM\n\tbool \"In kernel memory optimization (uClinux only)\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_INSMOD_LOADINKMEM\n\tdepends on BUSYBOX_CONFIG_FEATURE_2_4_MODULES && (BUSYBOX_CONFIG_INSMOD || BUSYBOX_CONFIG_MODPROBE)\n\thelp\n\tThis is a special uClinux only memory optimization that lets insmod\n\tload the specified kernel module directly into kernel space, reducing\n\tmemory usage by preventing the need for two copies of the module\n\tbeing loaded into memory.\n\nconfig BUSYBOX_CONFIG_FEATURE_INSMOD_LOAD_MAP\n\tbool \"Enable insmod load map (-m) option\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_INSMOD_LOAD_MAP\n\tdepends on BUSYBOX_CONFIG_FEATURE_2_4_MODULES && BUSYBOX_CONFIG_INSMOD\n\thelp\n\tEnabling this, one would be able to get a load map\n\toutput on stdout. This makes kernel module debugging\n\teasier.\n\tIf you don't plan to debug kernel modules, you\n\tdon't need this option.\n\nconfig BUSYBOX_CONFIG_FEATURE_INSMOD_LOAD_MAP_FULL\n\tbool \"Symbols in load map\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_INSMOD_LOAD_MAP_FULL\n\tdepends on BUSYBOX_CONFIG_FEATURE_INSMOD_LOAD_MAP\n\thelp\n\tWithout this option, -m will only output section\n\tload map. With this option, -m will also output\n\tsymbols load map.\n\nconfig BUSYBOX_CONFIG_FEATURE_CHECK_TAINTED_MODULE\n\tbool \"Support tainted module checking with new kernels\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_CHECK_TAINTED_MODULE\n\tdepends on (BUSYBOX_CONFIG_LSMOD || BUSYBOX_CONFIG_FEATURE_2_4_MODULES) && !BUSYBOX_CONFIG_MODPROBE_SMALL\n\thelp\n\tSupport checking for tainted modules. These are usually binary\n\tonly modules that will make the linux-kernel list ignore your\n\tsupport request.\n\tThis option is required to support GPLONLY modules.\n\nconfig BUSYBOX_CONFIG_FEATURE_INSMOD_TRY_MMAP\n\tbool \"Try to load module from a mmap'ed area\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_INSMOD_TRY_MMAP\n\tdepends on (BUSYBOX_CONFIG_INSMOD || BUSYBOX_CONFIG_MODPROBE) && !BUSYBOX_CONFIG_MODPROBE_SMALL\n\thelp\n\tThis option causes module loading code to try to mmap\n\tmodule first. If it does not work (for example,\n\tit does not work for compressed modules), module will be read\n\t(and unpacked if needed) into a memory block allocated by malloc.\n\n\tThe only case when mmap works but malloc does not is when\n\tyou are trying to load a big module on a very memory-constrained\n\tmachine. Malloc will momentarily need 2x as much memory as mmap.\n\n\tChoosing N saves about 250 bytes of code (on 32-bit x86).\n\nconfig BUSYBOX_CONFIG_FEATURE_MODUTILS_ALIAS\n\tbool \"Support module.aliases file\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_MODUTILS_ALIAS\n\tdepends on (BUSYBOX_CONFIG_DEPMOD || BUSYBOX_CONFIG_MODPROBE) && !BUSYBOX_CONFIG_MODPROBE_SMALL\n\thelp\n\tGenerate and parse modules.alias containing aliases for bus\n\tidentifiers:\n\t\talias pcmcia:m*c*f03fn*pfn*pa*pb*pc*pd* parport_cs\n\n\tand aliases for logical modules names e.g.:\n\t\talias padlock_aes aes\n\t\talias aes_i586 aes\n\t\talias aes_generic aes\n\n\tSay Y if unsure.\n\nconfig BUSYBOX_CONFIG_FEATURE_MODUTILS_SYMBOLS\n\tbool \"Support module.symbols file\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_MODUTILS_SYMBOLS\n\tdepends on (BUSYBOX_CONFIG_DEPMOD || BUSYBOX_CONFIG_MODPROBE) && !BUSYBOX_CONFIG_MODPROBE_SMALL\n\thelp\n\tGenerate and parse modules.symbols containing aliases for\n\tsymbol_request() kernel calls, such as:\n\t\talias symbol:usb_sg_init usbcore\n\n\tSay Y if unsure.\n\nconfig BUSYBOX_CONFIG_DEFAULT_MODULES_DIR\n\tstring \"Default directory containing modules\"\n\tdefault BUSYBOX_DEFAULT_DEFAULT_MODULES_DIR\n\tdepends on BUSYBOX_CONFIG_DEPMOD || BUSYBOX_CONFIG_MODPROBE || BUSYBOX_CONFIG_MODINFO\n\thelp\n\tDirectory that contains kernel modules.\n\tDefaults to \"/lib/modules\"\n\nconfig BUSYBOX_CONFIG_DEFAULT_DEPMOD_FILE\n\tstring \"Default name of modules.dep\"\n\tdefault BUSYBOX_DEFAULT_DEFAULT_DEPMOD_FILE\n\tdepends on BUSYBOX_CONFIG_DEPMOD || BUSYBOX_CONFIG_MODPROBE || BUSYBOX_CONFIG_MODINFO\n\thelp\n\tFilename that contains kernel modules dependencies.\n\tDefaults to \"modules.dep\".\n\tIf you configured the \"simplified modutils\" (MODPROBE_SMALL), a\n\t\".bb\" suffix will be added after this name. Do not specify \".bb\"\n\there unless you intend your depmod or modprobe to work on\n\t\"modules.dep.bb.bb\" or such.\n\nendmenu\n"
  },
  {
    "path": "package/utils/busybox/config/networking/Config.in",
    "content": "# DO NOT EDIT. This file is generated from Config.src\n#\n# For a description of the syntax of this configuration file,\n# see docs/Kconfig-language.txt.\n#\n\nmenu \"Networking Utilities\"\n\nconfig BUSYBOX_CONFIG_FEATURE_IPV6\n\tbool \"Enable IPv6 support\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_IPV6\n\thelp\n\tEnable IPv6 support in busybox.\n\tThis adds IPv6 support in the networking applets.\n\nconfig BUSYBOX_CONFIG_FEATURE_UNIX_LOCAL\n\tbool \"Enable Unix domain socket support (usually not needed)\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_UNIX_LOCAL\n\thelp\n\tEnable Unix domain socket support in all busybox networking\n\tapplets.  Address of the form local:/path/to/unix/socket\n\twill be recognized.\n\n\tThis extension is almost never used in real world usage.\n\tYou most likely want to say N.\n\nconfig BUSYBOX_CONFIG_FEATURE_PREFER_IPV4_ADDRESS\n\tbool \"Prefer IPv4 addresses from DNS queries\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_PREFER_IPV4_ADDRESS\n\tdepends on BUSYBOX_CONFIG_FEATURE_IPV6\n\thelp\n\tUse IPv4 address of network host if it has one.\n\n\tIf this option is off, the first returned address will be used.\n\tThis may cause problems when your DNS server is IPv6-capable and\n\tis returning IPv6 host addresses too. If IPv6 address\n\tprecedes IPv4 one in DNS reply, busybox network applets\n\t(e.g. wget) will use IPv6 address. On an IPv6-incapable host\n\tor network applets will fail to connect to the host\n\tusing IPv6 address.\n\nconfig BUSYBOX_CONFIG_VERBOSE_RESOLUTION_ERRORS\n\tbool \"Verbose resolution errors\"\n\tdefault BUSYBOX_DEFAULT_VERBOSE_RESOLUTION_ERRORS\n\thelp\n\tEnable if you are not satisfied with simplistic\n\t\"can't resolve 'hostname.com'\" and want to know more.\n\tThis may increase size of your executable a bit.\n\nconfig BUSYBOX_CONFIG_FEATURE_ETC_NETWORKS\n\tbool \"Support /etc/networks\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_ETC_NETWORKS\n\thelp\n\tEnable support for network names in /etc/networks. This is\n\ta rarely used feature which allows you to use names\n\tinstead of IP/mask pairs in route command.\n\nconfig BUSYBOX_CONFIG_FEATURE_ETC_SERVICES\n\tbool \"Consult /etc/services even for well-known ports\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_ETC_SERVICES\n\thelp\n\tLook up e.g. \"telnet\" and \"http\" in /etc/services file\n\tinstead of assuming ports 23 and 80.\n\tThis is almost never necessary (everybody uses standard ports),\n\tand it makes sense to avoid reading this file.\n\tIf you disable this option, in the cases where port is explicitly\n\tspecified as a service name (e.g. \"telnet HOST PORTNAME\"),\n\tit will still be looked up in /etc/services.\n\nconfig BUSYBOX_CONFIG_FEATURE_HWIB\n\tbool \"Support infiniband HW\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_HWIB\n\thelp\n\tSupport for printing infiniband addresses in network applets.\n\nconfig BUSYBOX_CONFIG_FEATURE_TLS_SHA1\n\tbool \"In TLS code, support ciphers which use deprecated SHA1\"\n\tdepends on BUSYBOX_CONFIG_TLS\n\tdefault BUSYBOX_DEFAULT_FEATURE_TLS_SHA1\n\thelp\n\tSelecting this option increases interoperability with very old\n\tservers, but slightly increases code size.\n\n\tMost TLS servers support SHA256 today (2018), since SHA1 is\n\tconsidered possibly insecure (although not yet definitely broken).\n\nconfig BUSYBOX_CONFIG_ARP\n\tbool \"arp (10 kb)\"\n\tdefault BUSYBOX_DEFAULT_ARP\n\thelp\n\tManipulate the system ARP cache.\nconfig BUSYBOX_CONFIG_ARPING\n\tbool \"arping (9 kb)\"\n\tdefault BUSYBOX_DEFAULT_ARPING\n\thelp\n\tPing hosts by ARP packets.\nconfig BUSYBOX_CONFIG_BRCTL\n\tbool \"brctl (4.7 kb)\"\n\tdefault BUSYBOX_DEFAULT_BRCTL\n\thelp\n\tManage ethernet bridges.\n\tSupports addbr/delbr and addif/delif.\n\nconfig BUSYBOX_CONFIG_FEATURE_BRCTL_FANCY\n\tbool \"Fancy options\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_BRCTL_FANCY\n\tdepends on BUSYBOX_CONFIG_BRCTL\n\thelp\n\tAdd support for extended option like:\n\t\tsetageing, setfd, sethello, setmaxage,\n\t\tsetpathcost, setportprio, setbridgeprio,\n\t\tstp\n\tThis adds about 600 bytes.\n\nconfig BUSYBOX_CONFIG_FEATURE_BRCTL_SHOW\n\tbool \"Support show\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_BRCTL_SHOW\n\tdepends on BUSYBOX_CONFIG_BRCTL && BUSYBOX_CONFIG_FEATURE_BRCTL_FANCY\n\thelp\n\tAdd support for option which prints the current config:\n\t\tshow\nconfig BUSYBOX_CONFIG_DNSD\n\tbool \"dnsd (9.8 kb)\"\n\tdefault BUSYBOX_DEFAULT_DNSD\n\thelp\n\tSmall and static DNS server daemon.\nconfig BUSYBOX_CONFIG_ETHER_WAKE\n\tbool \"ether-wake (4.9 kb)\"\n\tdefault BUSYBOX_DEFAULT_ETHER_WAKE\n\thelp\n\tSend a magic packet to wake up sleeping machines.\nconfig BUSYBOX_CONFIG_FTPD\n\tbool \"ftpd (30 kb)\"\n\tdefault BUSYBOX_DEFAULT_FTPD\n\thelp\n\tSimple FTP daemon. You have to run it via inetd.\n\nconfig BUSYBOX_CONFIG_FEATURE_FTPD_WRITE\n\tbool \"Enable -w (upload commands)\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_FTPD_WRITE\n\tdepends on BUSYBOX_CONFIG_FTPD\n\thelp\n\tEnable -w option. \"ftpd -w\" will accept upload commands\n\tsuch as STOR, STOU, APPE, DELE, MKD, RMD, rename commands.\n\nconfig BUSYBOX_CONFIG_FEATURE_FTPD_ACCEPT_BROKEN_LIST\n\tbool \"Enable workaround for RFC-violating clients\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_FTPD_ACCEPT_BROKEN_LIST\n\tdepends on BUSYBOX_CONFIG_FTPD\n\thelp\n\tSome ftp clients (among them KDE's Konqueror) issue illegal\n\t\"LIST -l\" requests. This option works around such problems.\n\tIt might prevent you from listing files starting with \"-\" and\n\tit increases the code size by ~40 bytes.\n\tMost other ftp servers seem to behave similar to this.\n\nconfig BUSYBOX_CONFIG_FEATURE_FTPD_AUTHENTICATION\n\tbool \"Enable authentication\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_FTPD_AUTHENTICATION\n\tdepends on BUSYBOX_CONFIG_FTPD\n\thelp\n\tRequire login, and change to logged in user's UID:GID before\n\taccessing any files. Option \"-a USER\" allows \"anonymous\"\n\tlogins (treats them as if USER logged in).\n\n\tIf this option is not selected, ftpd runs with the rights\n\tof the user it was started under, and does not require login.\n\tTake care to not launch it under root.\nconfig BUSYBOX_CONFIG_FTPGET\n\tbool \"ftpget (7.8 kb)\"\n\tdefault BUSYBOX_DEFAULT_FTPGET\n\thelp\n\tRetrieve a remote file via FTP.\n\nconfig BUSYBOX_CONFIG_FTPPUT\n\tbool \"ftpput (7.5 kb)\"\n\tdefault BUSYBOX_DEFAULT_FTPPUT\n\thelp\n\tStore a remote file via FTP.\n\nconfig BUSYBOX_CONFIG_FEATURE_FTPGETPUT_LONG_OPTIONS\n\tbool \"Enable long options in ftpget/ftpput\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_FTPGETPUT_LONG_OPTIONS\n\tdepends on BUSYBOX_CONFIG_LONG_OPTS && (BUSYBOX_CONFIG_FTPGET || BUSYBOX_CONFIG_FTPPUT)\nconfig BUSYBOX_CONFIG_HOSTNAME\n\tbool \"hostname (5.5 kb)\"\n\tdefault BUSYBOX_DEFAULT_HOSTNAME\n\thelp\n\tShow or set the system's host name.\n\nconfig BUSYBOX_CONFIG_DNSDOMAINNAME\n\tbool \"dnsdomainname (3.6 kb)\"\n\tdefault BUSYBOX_DEFAULT_DNSDOMAINNAME\n\thelp\n\tAlias to \"hostname -d\".\nconfig BUSYBOX_CONFIG_HTTPD\n\tbool \"httpd (32 kb)\"\n\tdefault BUSYBOX_DEFAULT_HTTPD\n\thelp\n\tHTTP server.\n\nconfig BUSYBOX_CONFIG_FEATURE_HTTPD_PORT_DEFAULT\n\tint \"Default port\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_HTTPD_PORT_DEFAULT\n\trange 1 65535\n\tdepends on BUSYBOX_CONFIG_HTTPD\n\nconfig BUSYBOX_CONFIG_FEATURE_HTTPD_RANGES\n\tbool \"Support 'Ranges:' header\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_HTTPD_RANGES\n\tdepends on BUSYBOX_CONFIG_HTTPD\n\thelp\n\tMakes httpd emit \"Accept-Ranges: bytes\" header and understand\n\t\"Range: bytes=NNN-[MMM]\" header. Allows for resuming interrupted\n\tdownloads, seeking in multimedia players etc.\n\nconfig BUSYBOX_CONFIG_FEATURE_HTTPD_SETUID\n\tbool \"Enable -u <user> option\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_HTTPD_SETUID\n\tdepends on BUSYBOX_CONFIG_HTTPD\n\thelp\n\tThis option allows the server to run as a specific user\n\trather than defaulting to the user that starts the server.\n\tUse of this option requires special privileges to change to a\n\tdifferent user.\n\nconfig BUSYBOX_CONFIG_FEATURE_HTTPD_BASIC_AUTH\n\tbool \"Enable HTTP authentication\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_HTTPD_BASIC_AUTH\n\tdepends on BUSYBOX_CONFIG_HTTPD\n\thelp\n\tUtilizes password settings from /etc/httpd.conf for basic\n\tauthentication on a per url basis.\n\tExample for httpd.conf file:\n\t/adm:toor:PaSsWd\n\nconfig BUSYBOX_CONFIG_FEATURE_HTTPD_AUTH_MD5\n\tbool \"Support MD5-encrypted passwords in HTTP authentication\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_HTTPD_AUTH_MD5\n\tdepends on BUSYBOX_CONFIG_FEATURE_HTTPD_BASIC_AUTH\n\thelp\n\tEnables encrypted passwords, and wildcard user/passwords\n\tin httpd.conf file.\n\tUser '*' means 'any system user name is ok',\n\tpassword of '*' means 'use system password for this user'\n\tExamples:\n\t/adm:toor:$1$P/eKnWXS$aI1aPGxT.dJD5SzqAKWrF0\n\t/adm:root:*\n\t/wiki:*:*\n\nconfig BUSYBOX_CONFIG_FEATURE_HTTPD_CGI\n\tbool \"Support Common Gateway Interface (CGI)\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_HTTPD_CGI\n\tdepends on BUSYBOX_CONFIG_HTTPD\n\thelp\n\tThis option allows scripts and executables to be invoked\n\twhen specific URLs are requested.\n\nconfig BUSYBOX_CONFIG_FEATURE_HTTPD_CONFIG_WITH_SCRIPT_INTERPR\n\tbool \"Support running scripts through an interpreter\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_HTTPD_CONFIG_WITH_SCRIPT_INTERPR\n\tdepends on BUSYBOX_CONFIG_FEATURE_HTTPD_CGI\n\thelp\n\tThis option enables support for running scripts through an\n\tinterpreter. Turn this on if you want PHP scripts to work\n\tproperly. You need to supply an additional line in your\n\thttpd.conf file:\n\t*.php:/path/to/your/php\n\nconfig BUSYBOX_CONFIG_FEATURE_HTTPD_SET_REMOTE_PORT_TO_ENV\n\tbool \"Set REMOTE_PORT environment variable for CGI\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_HTTPD_SET_REMOTE_PORT_TO_ENV\n\tdepends on BUSYBOX_CONFIG_FEATURE_HTTPD_CGI\n\thelp\n\tUse of this option can assist scripts in generating\n\treferences that contain a unique port number.\n\nconfig BUSYBOX_CONFIG_FEATURE_HTTPD_ENCODE_URL_STR\n\tbool \"Enable -e option (useful for CGIs written as shell scripts)\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_HTTPD_ENCODE_URL_STR\n\tdepends on BUSYBOX_CONFIG_HTTPD\n\thelp\n\tThis option allows html encoding of arbitrary strings for display\n\tby the browser. Output goes to stdout.\n\tFor example, httpd -e \"<Hello World>\" produces\n\t\"&#60Hello&#32World&#62\".\n\nconfig BUSYBOX_CONFIG_FEATURE_HTTPD_ERROR_PAGES\n\tbool \"Support custom error pages\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_HTTPD_ERROR_PAGES\n\tdepends on BUSYBOX_CONFIG_HTTPD\n\thelp\n\tThis option allows you to define custom error pages in\n\tthe configuration file instead of the default HTTP status\n\terror pages. For instance, if you add the line:\n\t\tE404:/path/e404.html\n\tin the config file, the server will respond the specified\n\t'/path/e404.html' file instead of the terse '404 NOT FOUND'\n\tmessage.\n\nconfig BUSYBOX_CONFIG_FEATURE_HTTPD_PROXY\n\tbool \"Support reverse proxy\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_HTTPD_PROXY\n\tdepends on BUSYBOX_CONFIG_HTTPD\n\thelp\n\tThis option allows you to define URLs that will be forwarded\n\tto another HTTP server. To setup add the following line to the\n\tconfiguration file\n\t\tP:/url/:http://hostname[:port]/new/path/\n\tThen a request to /url/myfile will be forwarded to\n\thttp://hostname[:port]/new/path/myfile.\n\nconfig BUSYBOX_CONFIG_FEATURE_HTTPD_GZIP\n\tbool \"Support GZIP content encoding\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_HTTPD_GZIP\n\tdepends on BUSYBOX_CONFIG_HTTPD\n\thelp\n\tMakes httpd send files using GZIP content encoding if the\n\tclient supports it and a pre-compressed <file>.gz exists.\n\nconfig BUSYBOX_CONFIG_FEATURE_HTTPD_ETAG\n\tbool \"Support caching via ETag header\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_HTTPD_ETAG\n\tdepends on BUSYBOX_CONFIG_HTTPD\n\thelp\n\tIf server responds with ETag then next time client (browser)\n\tresend it via If-None-Match header.\n\tThen httpd will check if file wasn't modified and if not,\n\treturn 304 Not Modified status code.\n\tThe ETag value is constructed from last modification date\n\tin unix epoch, and size: \"hex(last_mod)-hex(file_size)\".\n\tIt's not completely reliable as hash functions but fair enough.\n\nconfig BUSYBOX_CONFIG_FEATURE_HTTPD_LAST_MODIFIED\n\tbool \"Add Last-Modified header to response\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_HTTPD_LAST_MODIFIED\n\tdepends on BUSYBOX_CONFIG_HTTPD\n\thelp\n\tThe Last-Modified header is used for cache validation.\n\tThe client sends last seen mtime to server in If-Modified-Since.\n\tBoth headers MUST be an RFC 1123 formatted, which is hard to parse.\n\tUse ETag header instead.\n\nconfig BUSYBOX_CONFIG_FEATURE_HTTPD_DATE\n\tbool \"Add Date header to response\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_HTTPD_DATE\n\tdepends on BUSYBOX_CONFIG_HTTPD\n\thelp\n\tRFC2616 says that server MUST add Date header to response.\n\tBut it is almost useless and can be omitted.\n\nconfig BUSYBOX_CONFIG_FEATURE_HTTPD_ACL_IP\n\tbool \"ACL IP\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_HTTPD_ACL_IP\n\tdepends on BUSYBOX_CONFIG_HTTPD\n\thelp\n\tSupport IP deny/allow rules\nconfig BUSYBOX_CONFIG_IFCONFIG\n\tbool \"ifconfig (12 kb)\"\n\tdefault BUSYBOX_DEFAULT_IFCONFIG\n\thelp\n\tIfconfig is used to configure the kernel-resident network interfaces.\n\nconfig BUSYBOX_CONFIG_FEATURE_IFCONFIG_STATUS\n\tbool \"Enable status reporting output (+7k)\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_IFCONFIG_STATUS\n\tdepends on BUSYBOX_CONFIG_IFCONFIG\n\thelp\n\tIf ifconfig is called with no arguments it will display the status\n\tof the currently active interfaces.\n\nconfig BUSYBOX_CONFIG_FEATURE_IFCONFIG_SLIP\n\tbool \"Enable slip-specific options \\\"keepalive\\\" and \\\"outfill\\\"\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_IFCONFIG_SLIP\n\tdepends on BUSYBOX_CONFIG_IFCONFIG\n\thelp\n\tAllow \"keepalive\" and \"outfill\" support for SLIP. If you're not\n\tplanning on using serial lines, leave this unchecked.\n\nconfig BUSYBOX_CONFIG_FEATURE_IFCONFIG_MEMSTART_IOADDR_IRQ\n\tbool \"Enable options \\\"mem_start\\\", \\\"io_addr\\\", and \\\"irq\\\"\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_IFCONFIG_MEMSTART_IOADDR_IRQ\n\tdepends on BUSYBOX_CONFIG_IFCONFIG\n\thelp\n\tAllow the start address for shared memory, start address for I/O,\n\tand/or the interrupt line used by the specified device.\n\nconfig BUSYBOX_CONFIG_FEATURE_IFCONFIG_HW\n\tbool \"Enable option \\\"hw\\\" (ether only)\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_IFCONFIG_HW\n\tdepends on BUSYBOX_CONFIG_IFCONFIG\n\thelp\n\tSet the hardware address of this interface, if the device driver\n\tsupports  this  operation. Currently, we only support the 'ether'\n\tclass.\n\nconfig BUSYBOX_CONFIG_FEATURE_IFCONFIG_BROADCAST_PLUS\n\tbool \"Set the broadcast automatically\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_IFCONFIG_BROADCAST_PLUS\n\tdepends on BUSYBOX_CONFIG_IFCONFIG\n\thelp\n\tSetting this will make ifconfig attempt to find the broadcast\n\tautomatically if the value '+' is used.\nconfig BUSYBOX_CONFIG_IFENSLAVE\n\tbool \"ifenslave (13 kb)\"\n\tdefault BUSYBOX_DEFAULT_IFENSLAVE\n\thelp\n\tUserspace application to bind several interfaces\n\tto a logical interface (use with kernel bonding driver).\nconfig BUSYBOX_CONFIG_IFPLUGD\n\tbool \"ifplugd (10 kb)\"\n\tdefault BUSYBOX_DEFAULT_IFPLUGD\n\thelp\n\tNetwork interface plug detection daemon.\nconfig BUSYBOX_CONFIG_IFUP\n\tbool \"ifup (14 kb)\"\n\tdefault BUSYBOX_DEFAULT_IFUP\n\thelp\n\tActivate the specified interfaces. This applet makes use\n\tof either \"ifconfig\" and \"route\" or the \"ip\" command to actually\n\tconfigure network interfaces. Therefore, you will probably also want\n\tto enable either IFCONFIG and ROUTE, or enable\n\tFEATURE_IFUPDOWN_IP and the various IP options. Of\n\tcourse you could use non-busybox versions of these programs, so\n\tagainst my better judgement (since this will surely result in plenty\n\tof support questions on the mailing list), I do not force you to\n\tenable these additional options. It is up to you to supply either\n\t\"ifconfig\", \"route\" and \"run-parts\" or the \"ip\" command, either\n\tvia busybox or via standalone utilities.\n\nconfig BUSYBOX_CONFIG_IFDOWN\n\tbool \"ifdown (13 kb)\"\n\tdefault BUSYBOX_DEFAULT_IFDOWN\n\thelp\n\tDeactivate the specified interfaces.\n\nconfig BUSYBOX_CONFIG_IFUPDOWN_IFSTATE_PATH\n\tstring \"Absolute path to ifstate file\"\n\tdefault BUSYBOX_DEFAULT_IFUPDOWN_IFSTATE_PATH\n\tdepends on BUSYBOX_CONFIG_IFUP || BUSYBOX_CONFIG_IFDOWN\n\thelp\n\tifupdown keeps state information in a file called ifstate.\n\tTypically it is located in /var/run/ifstate, however\n\tsome distributions tend to put it in other places\n\t(debian, for example, uses /etc/network/run/ifstate).\n\tThis config option defines location of ifstate.\n\nconfig BUSYBOX_CONFIG_FEATURE_IFUPDOWN_IP\n\tbool \"Use ip tool (else ifconfig/route is used)\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_IFUPDOWN_IP\n\tdepends on BUSYBOX_CONFIG_IFUP || BUSYBOX_CONFIG_IFDOWN\n\thelp\n\tUse the iproute \"ip\" command to implement \"ifup\" and \"ifdown\", rather\n\tthan the default of using the older \"ifconfig\" and \"route\" utilities.\n\n\tIf Y: you must install either the full-blown iproute2 package\n\tor enable \"ip\" applet in busybox, or the \"ifup\" and \"ifdown\" applets\n\twill not work.\n\n\tIf N: you must install either the full-blown ifconfig and route\n\tutilities, or enable these applets in busybox.\n\nconfig BUSYBOX_CONFIG_FEATURE_IFUPDOWN_IPV4\n\tbool \"Support IPv4\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_IFUPDOWN_IPV4\n\tdepends on BUSYBOX_CONFIG_IFUP || BUSYBOX_CONFIG_IFDOWN\n\thelp\n\tIf you want ifup/ifdown to talk IPv4, leave this on.\n\nconfig BUSYBOX_CONFIG_FEATURE_IFUPDOWN_IPV6\n\tbool \"Support IPv6\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_IFUPDOWN_IPV6\n\tdepends on (BUSYBOX_CONFIG_IFUP || BUSYBOX_CONFIG_IFDOWN) && BUSYBOX_CONFIG_FEATURE_IPV6\n\thelp\n\tIf you need support for IPv6, turn this option on.\n\n\nconfig BUSYBOX_CONFIG_FEATURE_IFUPDOWN_MAPPING\n\tbool \"Enable mapping support\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_IFUPDOWN_MAPPING\n\tdepends on BUSYBOX_CONFIG_IFUP || BUSYBOX_CONFIG_IFDOWN\n\thelp\n\tThis enables support for the \"mapping\" stanza, unless you have\n\ta weird network setup you don't need it.\n\nconfig BUSYBOX_CONFIG_FEATURE_IFUPDOWN_EXTERNAL_DHCP\n\tbool \"Support external DHCP clients\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_IFUPDOWN_EXTERNAL_DHCP\n\tdepends on BUSYBOX_CONFIG_IFUP || BUSYBOX_CONFIG_IFDOWN\n\thelp\n\tThis enables support for the external dhcp clients. Clients are\n\ttried in the following order: dhcpcd, dhclient, pump and udhcpc.\n\tOtherwise, if udhcpc applet is enabled, it is used.\n\tOtherwise, ifup/ifdown will have no support for DHCP.\nconfig BUSYBOX_CONFIG_INETD\n\tbool \"inetd (18 kb)\"\n\tdefault BUSYBOX_DEFAULT_INETD\n\tselect BUSYBOX_CONFIG_FEATURE_SYSLOG\n\thelp\n\tInternet superserver daemon\n\nconfig BUSYBOX_CONFIG_FEATURE_INETD_SUPPORT_BUILTIN_ECHO\n\tbool \"Support echo service on port 7\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_INETD_SUPPORT_BUILTIN_ECHO\n\tdepends on BUSYBOX_CONFIG_INETD\n\thelp\n\tInternal service which echoes data back.\n\tActivated by configuration lines like these:\n\t\techo stream tcp nowait root internal\n\t\techo dgram  udp wait   root internal\n\nconfig BUSYBOX_CONFIG_FEATURE_INETD_SUPPORT_BUILTIN_DISCARD\n\tbool \"Support discard service on port 8\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_INETD_SUPPORT_BUILTIN_DISCARD\n\tdepends on BUSYBOX_CONFIG_INETD\n\thelp\n\tInternal service which discards all input.\n\tActivated by configuration lines like these:\n\t\tdiscard stream tcp nowait root internal\n\t\tdiscard dgram  udp wait   root internal\n\nconfig BUSYBOX_CONFIG_FEATURE_INETD_SUPPORT_BUILTIN_TIME\n\tbool \"Support time service on port 37\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_INETD_SUPPORT_BUILTIN_TIME\n\tdepends on BUSYBOX_CONFIG_INETD\n\thelp\n\tInternal service which returns big-endian 32-bit number\n\tof seconds passed since 1900-01-01. The number wraps around\n\ton overflow.\n\tActivated by configuration lines like these:\n\t\ttime stream tcp nowait root internal\n\t\ttime dgram  udp wait   root internal\n\nconfig BUSYBOX_CONFIG_FEATURE_INETD_SUPPORT_BUILTIN_DAYTIME\n\tbool \"Support daytime service on port 13\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_INETD_SUPPORT_BUILTIN_DAYTIME\n\tdepends on BUSYBOX_CONFIG_INETD\n\thelp\n\tInternal service which returns human-readable time.\n\tActivated by configuration lines like these:\n\t\tdaytime stream tcp nowait root internal\n\t\tdaytime dgram  udp wait   root internal\n\nconfig BUSYBOX_CONFIG_FEATURE_INETD_SUPPORT_BUILTIN_CHARGEN\n\tbool \"Support chargen service on port 19\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_INETD_SUPPORT_BUILTIN_CHARGEN\n\tdepends on BUSYBOX_CONFIG_INETD\n\thelp\n\tInternal service which generates endless stream\n\tof all ASCII chars beetween space and char 126.\n\tActivated by configuration lines like these:\n\t\tchargen stream tcp nowait root internal\n\t\tchargen dgram  udp wait   root internal\n\nconfig BUSYBOX_CONFIG_FEATURE_INETD_RPC\n\tbool \"Support RPC services\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_INETD_RPC  # very rarely used, and needs Sun RPC support in libc\n\tdepends on BUSYBOX_CONFIG_INETD\n\thelp\n\tSupport Sun-RPC based services\nconfig BUSYBOX_CONFIG_IP\n\tbool \"ip (35 kb)\"\n\tdefault BUSYBOX_DEFAULT_IP\n\thelp\n\tThe \"ip\" applet is a TCP/IP interface configuration and routing\n\tutility.\n\tShort forms (enabled below) are busybox-specific extensions.\n\tThe standard \"ip\" utility does not provide them. If you are\n\ttrying to be portable, it's better to use \"ip CMD\" forms.\n\nconfig BUSYBOX_CONFIG_IPADDR\n\tbool \"ipaddr (14 kb)\"\n\tdefault BUSYBOX_DEFAULT_IPADDR\n\tselect BUSYBOX_CONFIG_FEATURE_IP_ADDRESS\n\thelp\n\tShort form of \"ip addr\"\n\nconfig BUSYBOX_CONFIG_IPLINK\n\tbool \"iplink (17 kb)\"\n\tdefault BUSYBOX_DEFAULT_IPLINK\n\tselect BUSYBOX_CONFIG_FEATURE_IP_LINK\n\thelp\n\tShort form of \"ip link\"\n\nconfig BUSYBOX_CONFIG_IPROUTE\n\tbool \"iproute (15 kb)\"\n\tdefault BUSYBOX_DEFAULT_IPROUTE\n\tselect BUSYBOX_CONFIG_FEATURE_IP_ROUTE\n\thelp\n\tShort form of \"ip route\"\n\nconfig BUSYBOX_CONFIG_IPTUNNEL\n\tbool \"iptunnel (9.6 kb)\"\n\tdefault BUSYBOX_DEFAULT_IPTUNNEL\n\tselect BUSYBOX_CONFIG_FEATURE_IP_TUNNEL\n\thelp\n\tShort form of \"ip tunnel\"\n\nconfig BUSYBOX_CONFIG_IPRULE\n\tbool \"iprule (10 kb)\"\n\tdefault BUSYBOX_DEFAULT_IPRULE\n\tselect BUSYBOX_CONFIG_FEATURE_IP_RULE\n\thelp\n\tShort form of \"ip rule\"\n\nconfig BUSYBOX_CONFIG_IPNEIGH\n\tbool \"ipneigh (8.3 kb)\"\n\tdefault BUSYBOX_DEFAULT_IPNEIGH\n\tselect BUSYBOX_CONFIG_FEATURE_IP_NEIGH\n\thelp\n\tShort form of \"ip neigh\"\n\nconfig BUSYBOX_CONFIG_FEATURE_IP_ADDRESS\n\tbool \"ip address\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_IP_ADDRESS\n\tdepends on BUSYBOX_CONFIG_IP || BUSYBOX_CONFIG_IPADDR\n\thelp\n\tAddress manipulation support for the \"ip\" applet.\n\nconfig BUSYBOX_CONFIG_FEATURE_IP_LINK\n\tbool \"ip link\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_IP_LINK\n\tdepends on BUSYBOX_CONFIG_IP || BUSYBOX_CONFIG_IPLINK\n\thelp\n\tConfigure network devices with \"ip\".\n\nconfig BUSYBOX_CONFIG_FEATURE_IP_ROUTE\n\tbool \"ip route\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_IP_ROUTE\n\tdepends on BUSYBOX_CONFIG_IP || BUSYBOX_CONFIG_IPROUTE\n\thelp\n\tAdd support for routing table management to \"ip\".\n\nconfig BUSYBOX_CONFIG_FEATURE_IP_ROUTE_DIR\n\tstring \"ip route configuration directory\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_IP_ROUTE_DIR\n\tdepends on BUSYBOX_CONFIG_FEATURE_IP_ROUTE\n\thelp\n\tLocation of the \"ip\" applet routing configuration.\n\nconfig BUSYBOX_CONFIG_FEATURE_IP_TUNNEL\n\tbool \"ip tunnel\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_IP_TUNNEL\n\tdepends on BUSYBOX_CONFIG_IP || BUSYBOX_CONFIG_IPTUNNEL\n\thelp\n\tAdd support for tunneling commands to \"ip\".\n\nconfig BUSYBOX_CONFIG_FEATURE_IP_RULE\n\tbool \"ip rule\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_IP_RULE\n\tdepends on BUSYBOX_CONFIG_IP || BUSYBOX_CONFIG_IPRULE\n\thelp\n\tAdd support for rule commands to \"ip\".\n\nconfig BUSYBOX_CONFIG_FEATURE_IP_NEIGH\n\tbool \"ip neighbor\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_IP_NEIGH\n\tdepends on BUSYBOX_CONFIG_IP || BUSYBOX_CONFIG_IPNEIGH\n\thelp\n\tAdd support for neighbor commands to \"ip\".\n\nconfig BUSYBOX_CONFIG_FEATURE_IP_RARE_PROTOCOLS\n\tbool \"Support displaying rarely used link types\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_IP_RARE_PROTOCOLS\n\tdepends on BUSYBOX_CONFIG_IP || BUSYBOX_CONFIG_IPADDR || BUSYBOX_CONFIG_IPLINK || BUSYBOX_CONFIG_IPROUTE || BUSYBOX_CONFIG_IPTUNNEL || BUSYBOX_CONFIG_IPRULE || BUSYBOX_CONFIG_IPNEIGH\n\thelp\n\tIf you are not going to use links of type \"frad\", \"econet\",\n\t\"bif\" etc, you probably don't need to enable this.\n\tEthernet, wireless, infrared, ppp/slip, ip tunnelling\n\tlink types are supported without this option selected.\nconfig BUSYBOX_CONFIG_IPCALC\n\tbool \"ipcalc (4.4 kb)\"\n\tdefault BUSYBOX_DEFAULT_IPCALC\n\thelp\n\tipcalc takes an IP address and netmask and calculates the\n\tresulting broadcast, network, and host range.\n\nconfig BUSYBOX_CONFIG_FEATURE_IPCALC_LONG_OPTIONS\n\tbool \"Enable long options\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_IPCALC_LONG_OPTIONS\n\tdepends on BUSYBOX_CONFIG_IPCALC && BUSYBOX_CONFIG_LONG_OPTS\n\nconfig BUSYBOX_CONFIG_FEATURE_IPCALC_FANCY\n\tbool \"Fancy IPCALC, more options, adds 1 kbyte\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_IPCALC_FANCY\n\tdepends on BUSYBOX_CONFIG_IPCALC\n\thelp\n\tAdds the options hostname, prefix and silent to the output of\n\t\"ipcalc\".\nconfig BUSYBOX_CONFIG_FAKEIDENTD\n\tbool \"fakeidentd (8.7 kb)\"\n\tdefault BUSYBOX_DEFAULT_FAKEIDENTD\n\tselect BUSYBOX_CONFIG_FEATURE_SYSLOG\n\thelp\n\tfakeidentd listens on the ident port and returns a predefined\n\tfake value on any query.\nconfig BUSYBOX_CONFIG_NAMEIF\n\tbool \"nameif (6.6 kb)\"\n\tdefault BUSYBOX_DEFAULT_NAMEIF\n\tselect BUSYBOX_CONFIG_FEATURE_SYSLOG\n\thelp\n\tnameif is used to rename network interface by its MAC address.\n\tRenamed interfaces MUST be in the down state.\n\tIt is possible to use a file (default: /etc/mactab)\n\twith list of new interface names and MACs.\n\tMaximum interface name length: IFNAMSIZ = 16\n\tFile fields are separated by space or tab.\n\tFile format:\n\t\t# Comment\n\t\tnew_interface_name  XX:XX:XX:XX:XX:XX\n\nconfig BUSYBOX_CONFIG_FEATURE_NAMEIF_EXTENDED\n\tbool \"Extended nameif\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_NAMEIF_EXTENDED\n\tdepends on BUSYBOX_CONFIG_NAMEIF\n\thelp\n\tThis extends the nameif syntax to support the bus_info, driver,\n\tphyaddr selectors. The syntax is compatible to the normal nameif.\n\tFile format:\n\t\tnew_interface_name  driver=asix bus=usb-0000:00:08.2-3\n\t\tnew_interface_name  bus=usb-0000:00:08.2-3 00:80:C8:38:91:B5\n\t\tnew_interface_name  phy_address=2 00:80:C8:38:91:B5\n\t\tnew_interface_name  mac=00:80:C8:38:91:B5\n\t\tnew_interface_name  00:80:C8:38:91:B5\nconfig BUSYBOX_CONFIG_NBDCLIENT\n\tbool \"nbd-client (6 kb)\"\n\tdefault BUSYBOX_DEFAULT_NBDCLIENT\n\thelp\n\tNetwork block device client\nconfig BUSYBOX_CONFIG_NC\n\tbool \"nc (11 kb)\"\n\tdefault BUSYBOX_DEFAULT_NC\n\thelp\n\tA simple Unix utility which reads and writes data across network\n\tconnections.\n\nconfig BUSYBOX_CONFIG_NETCAT\n\tbool \"netcat (11 kb)\"\n\tdefault BUSYBOX_DEFAULT_NETCAT\n\thelp\n\tAlias to nc.\n\nconfig BUSYBOX_CONFIG_NC_SERVER\n\tbool \"Netcat server options (-l)\"\n\tdefault BUSYBOX_DEFAULT_NC_SERVER\n\tdepends on BUSYBOX_CONFIG_NC || BUSYBOX_CONFIG_NETCAT\n\thelp\n\tAllow netcat to act as a server.\n\nconfig BUSYBOX_CONFIG_NC_EXTRA\n\tbool \"Netcat extensions (-eiw and -f FILE)\"\n\tdefault BUSYBOX_DEFAULT_NC_EXTRA\n\tdepends on BUSYBOX_CONFIG_NC || BUSYBOX_CONFIG_NETCAT\n\thelp\n\tAdd -e (support for executing the rest of the command line after\n\tmaking or receiving a successful connection), -i (delay interval for\n\tlines sent), -w (timeout for initial connection).\n\nconfig BUSYBOX_CONFIG_NC_110_COMPAT\n\tbool \"Netcat 1.10 compatibility (+2.5k)\"\n\tdefault BUSYBOX_DEFAULT_NC_110_COMPAT\n\tdepends on BUSYBOX_CONFIG_NC || BUSYBOX_CONFIG_NETCAT\n\thelp\n\tThis option makes nc closely follow original nc-1.10.\n\tThe code is about 2.5k bigger. It enables\n\t-s ADDR, -n, -u, -v, -o FILE, -z options, but loses\n\tbusybox-specific extensions: -f FILE.\nconfig BUSYBOX_CONFIG_NETMSG\n\tbool \"netmsg\"\n\tdefault BUSYBOX_DEFAULT_NETMSG\n\thelp\n\t  simple program for sending udp broadcast messages\nconfig BUSYBOX_CONFIG_NETSTAT\n\tbool \"netstat (10 kb)\"\n\tdefault BUSYBOX_DEFAULT_NETSTAT\n\thelp\n\tnetstat prints information about the Linux networking subsystem.\n\nconfig BUSYBOX_CONFIG_FEATURE_NETSTAT_WIDE\n\tbool \"Enable wide output\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_NETSTAT_WIDE\n\tdepends on BUSYBOX_CONFIG_NETSTAT\n\thelp\n\tAdd support for wide columns. Useful when displaying IPv6 addresses\n\t(-W option).\n\nconfig BUSYBOX_CONFIG_FEATURE_NETSTAT_PRG\n\tbool \"Enable PID/Program name output\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_NETSTAT_PRG\n\tdepends on BUSYBOX_CONFIG_NETSTAT\n\thelp\n\tAdd support for -p flag to print out PID and program name.\n\t+700 bytes of code.\nconfig BUSYBOX_CONFIG_NSLOOKUP\n\tbool \"nslookup (9.7 kb)\"\n\tdefault BUSYBOX_DEFAULT_NSLOOKUP\n\thelp\n\tnslookup is a tool to query Internet name servers.\n\nconfig BUSYBOX_CONFIG_FEATURE_NSLOOKUP_BIG\n\tbool \"Use internal resolver code instead of libc\"\n\tdepends on BUSYBOX_CONFIG_NSLOOKUP\n\tdefault BUSYBOX_DEFAULT_FEATURE_NSLOOKUP_BIG\n\nconfig BUSYBOX_CONFIG_FEATURE_NSLOOKUP_LONG_OPTIONS\n\tbool \"Enable long options\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_NSLOOKUP_LONG_OPTIONS\n\tdepends on BUSYBOX_CONFIG_FEATURE_NSLOOKUP_BIG && BUSYBOX_CONFIG_LONG_OPTS\nconfig BUSYBOX_CONFIG_NTPD\n\tbool \"ntpd (22 kb)\"\n\tdefault BUSYBOX_DEFAULT_NTPD\n\thelp\n\tThe NTP client/server daemon.\n\nconfig BUSYBOX_CONFIG_FEATURE_NTPD_SERVER\n\tbool \"Make ntpd usable as a NTP server\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_NTPD_SERVER\n\tdepends on BUSYBOX_CONFIG_NTPD\n\thelp\n\tMake ntpd usable as a NTP server. If you disable this option\n\tntpd will be usable only as a NTP client.\n\nconfig BUSYBOX_CONFIG_FEATURE_NTPD_CONF\n\tbool \"Make ntpd understand /etc/ntp.conf\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_NTPD_CONF\n\tdepends on BUSYBOX_CONFIG_NTPD\n\thelp\n\tMake ntpd look in /etc/ntp.conf for peers. Only \"server address\"\n\tis supported.\n\nconfig BUSYBOX_CONFIG_FEATURE_NTP_AUTH\n\tbool \"Support md5/sha1 message authentication codes\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_NTP_AUTH\n\tdepends on BUSYBOX_CONFIG_NTPD\nconfig BUSYBOX_CONFIG_PING\n\tbool \"ping (10 kb)\"\n\tdefault BUSYBOX_DEFAULT_PING\n\thelp\n\tping uses the ICMP protocol's mandatory ECHO_REQUEST datagram to\n\telicit an ICMP ECHO_RESPONSE from a host or gateway.\n\nconfig BUSYBOX_CONFIG_PING6\n\tbool \"ping6 (11 kb)\"\n\tdefault BUSYBOX_DEFAULT_PING6\n\tdepends on BUSYBOX_CONFIG_FEATURE_IPV6\n\thelp\n\tAlias to \"ping -6\".\n\nconfig BUSYBOX_CONFIG_FEATURE_FANCY_PING\n\tbool \"Enable fancy ping output\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_FANCY_PING\n\tdepends on BUSYBOX_CONFIG_PING || BUSYBOX_CONFIG_PING6\n\thelp\n\tWith this option off, ping will say \"HOST is alive!\"\n\tor terminate with SIGALRM in 5 seconds otherwise.\n\tNo command-line options will be recognized.\nconfig BUSYBOX_CONFIG_PSCAN\n\tbool \"pscan (6 kb)\"\n\tdefault BUSYBOX_DEFAULT_PSCAN\n\thelp\n\tSimple network port scanner.\nconfig BUSYBOX_CONFIG_ROUTE\n\tbool \"route (8.7 kb)\"\n\tdefault BUSYBOX_DEFAULT_ROUTE\n\thelp\n\tRoute displays or manipulates the kernel's IP routing tables.\nconfig BUSYBOX_CONFIG_SLATTACH\n\tbool \"slattach (6.2 kb)\"\n\tdefault BUSYBOX_DEFAULT_SLATTACH\n\thelp\n\tslattach configures serial line as SLIP network interface.\nconfig BUSYBOX_CONFIG_SSL_CLIENT\n\tbool \"ssl_client (25 kb)\"\n\tdefault BUSYBOX_DEFAULT_SSL_CLIENT\n\tselect BUSYBOX_CONFIG_TLS\n\thelp\n\tThis tool pipes data to/from a socket, TLS-encrypting it.\nconfig BUSYBOX_CONFIG_TC\n\tbool \"tc (8.3 kb)\"\n\tdefault BUSYBOX_DEFAULT_TC\n\thelp\n\tShow / manipulate traffic control settings\n\nconfig BUSYBOX_CONFIG_FEATURE_TC_INGRESS\n\tbool \"Enable ingress\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_TC_INGRESS\n\tdepends on BUSYBOX_CONFIG_TC\nconfig BUSYBOX_CONFIG_TCPSVD\n\tbool \"tcpsvd (14 kb)\"\n\tdefault BUSYBOX_DEFAULT_TCPSVD\n\thelp\n\ttcpsvd listens on a TCP port and runs a program for each new\n\tconnection.\n\nconfig BUSYBOX_CONFIG_UDPSVD\n\tbool \"udpsvd (13 kb)\"\n\tdefault BUSYBOX_DEFAULT_UDPSVD\n\thelp\n\tudpsvd listens on an UDP port and runs a program for each new\n\tconnection.\nconfig BUSYBOX_CONFIG_TELNET\n\tbool \"telnet (8.8 kb)\"\n\tdefault BUSYBOX_DEFAULT_TELNET\n\thelp\n\tTelnet is an interface to the TELNET protocol, but is also commonly\n\tused to test other simple protocols.\n\nconfig BUSYBOX_CONFIG_FEATURE_TELNET_TTYPE\n\tbool \"Pass TERM type to remote host\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_TELNET_TTYPE\n\tdepends on BUSYBOX_CONFIG_TELNET\n\thelp\n\tSetting this option will forward the TERM environment variable to the\n\tremote host you are connecting to. This is useful to make sure that\n\tthings like ANSI colors and other control sequences behave.\n\nconfig BUSYBOX_CONFIG_FEATURE_TELNET_AUTOLOGIN\n\tbool \"Pass USER type to remote host\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_TELNET_AUTOLOGIN\n\tdepends on BUSYBOX_CONFIG_TELNET\n\thelp\n\tSetting this option will forward the USER environment variable to the\n\tremote host you are connecting to. This is useful when you need to\n\tlog into a machine without telling the username (autologin). This\n\toption enables '-a' and '-l USER' options.\n\nconfig BUSYBOX_CONFIG_FEATURE_TELNET_WIDTH\n\tbool \"Enable window size autodetection\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_TELNET_WIDTH\n\tdepends on BUSYBOX_CONFIG_TELNET\nconfig BUSYBOX_CONFIG_TELNETD\n\tbool \"telnetd (12 kb)\"\n\tdefault BUSYBOX_DEFAULT_TELNETD\n\tselect BUSYBOX_CONFIG_FEATURE_SYSLOG\n\thelp\n\tA daemon for the TELNET protocol, allowing you to log onto the host\n\trunning the daemon. Please keep in mind that the TELNET protocol\n\tsends passwords in plain text. If you can't afford the space for an\n\tSSH daemon and you trust your network, you may say 'y' here. As a\n\tmore secure alternative, you should seriously consider installing the\n\tvery small Dropbear SSH daemon instead:\n\t\thttp://matt.ucc.asn.au/dropbear/dropbear.html\n\n\tNote that for busybox telnetd to work you need several things:\n\tFirst of all, your kernel needs:\n\t\t  CONFIG_UNIX98_PTYS=y\n\n\tNext, you need a /dev/pts directory on your root filesystem:\n\n\t\t  $ ls -ld /dev/pts\n\t\t  drwxr-xr-x  2 root root 0 Sep 23 13:21 /dev/pts/\n\n\tNext you need the pseudo terminal master multiplexer /dev/ptmx:\n\n\t\t  $ ls -la /dev/ptmx\n\t\t  crw-rw-rw-  1 root tty 5, 2 Sep 23 13:55 /dev/ptmx\n\n\tAny /dev/ttyp[0-9]* files you may have can be removed.\n\tNext, you need to mount the devpts filesystem on /dev/pts using:\n\n\t\t  mount -t devpts devpts /dev/pts\n\n\tYou need to be sure that busybox has LOGIN and\n\tFEATURE_SUID enabled. And finally, you should make\n\tcertain that busybox has been installed setuid root:\n\n\t\tchown root.root /bin/busybox\n\t\tchmod 4755 /bin/busybox\n\n\twith all that done, telnetd _should_ work....\n\nconfig BUSYBOX_CONFIG_FEATURE_TELNETD_STANDALONE\n\tbool \"Support standalone telnetd (not inetd only)\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_TELNETD_STANDALONE\n\tdepends on BUSYBOX_CONFIG_TELNETD\n\thelp\n\tSelecting this will make telnetd able to run standalone.\n\nconfig BUSYBOX_CONFIG_FEATURE_TELNETD_PORT_DEFAULT\n\tint \"Default port\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_TELNETD_PORT_DEFAULT\n\trange 1 65535\n\tdepends on BUSYBOX_CONFIG_FEATURE_TELNETD_STANDALONE\n\nconfig BUSYBOX_CONFIG_FEATURE_TELNETD_INETD_WAIT\n\tbool \"Support -w SEC option (inetd wait mode)\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_TELNETD_INETD_WAIT\n\tdepends on BUSYBOX_CONFIG_FEATURE_TELNETD_STANDALONE\n\thelp\n\tThis option allows you to run telnetd in \"inet wait\" mode.\n\tExample inetd.conf line (note \"wait\", not usual \"nowait\"):\n\n\ttelnet stream tcp wait root /bin/telnetd telnetd -w10\n\n\tIn this example, inetd passes _listening_ socket_ as fd 0\n\tto telnetd when connection appears.\n\ttelnetd will wait for connections until all existing\n\tconnections are closed, and no new connections\n\tappear during 10 seconds. Then it exits, and inetd continues\n\tto listen for new connections.\n\n\tThis option is rarely used. \"tcp nowait\" is much more usual\n\tway of running tcp services, including telnetd.\n\tYou most probably want to say N here.\nconfig BUSYBOX_CONFIG_TFTP\n\tbool \"tftp (11 kb)\"\n\tdefault BUSYBOX_DEFAULT_TFTP\n\thelp\n\tTrivial File Transfer Protocol client. TFTP is usually used\n\tfor simple, small transfers such as a root image\n\tfor a network-enabled bootloader.\n\nconfig BUSYBOX_CONFIG_FEATURE_TFTP_PROGRESS_BAR\n\tbool \"Enable progress bar\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_TFTP_PROGRESS_BAR\n\tdepends on BUSYBOX_CONFIG_TFTP\n\nconfig BUSYBOX_CONFIG_FEATURE_TFTP_HPA_COMPAT\n\tbool \"tftp-hpa compat (support -c get/put FILE)\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_TFTP_HPA_COMPAT\n\tdepends on BUSYBOX_CONFIG_TFTP\n\nconfig BUSYBOX_CONFIG_TFTPD\n\tbool \"tftpd (10 kb)\"\n\tdefault BUSYBOX_DEFAULT_TFTPD\n\thelp\n\tTrivial File Transfer Protocol server.\n\tIt expects that stdin is a datagram socket and a packet\n\tis already pending on it. It will exit after one transfer.\n\tIn other words: it should be run from inetd in nowait mode,\n\tor from udpsvd. Example: \"udpsvd -E 0 69 tftpd DIR\"\n\nconfig BUSYBOX_CONFIG_FEATURE_TFTP_GET\n\tbool \"Enable 'tftp get' and/or tftpd upload code\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_TFTP_GET\n\tdepends on BUSYBOX_CONFIG_TFTP || BUSYBOX_CONFIG_TFTPD\n\thelp\n\tAdd support for the GET command within the TFTP client. This allows\n\ta client to retrieve a file from a TFTP server.\n\tAlso enable upload support in tftpd, if tftpd is selected.\n\n\tNote: this option does _not_ make tftpd capable of download\n\t(the usual operation people need from it)!\n\nconfig BUSYBOX_CONFIG_FEATURE_TFTP_PUT\n\tbool \"Enable 'tftp put' and/or tftpd download code\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_TFTP_PUT\n\tdepends on BUSYBOX_CONFIG_TFTP || BUSYBOX_CONFIG_TFTPD\n\thelp\n\tAdd support for the PUT command within the TFTP client. This allows\n\ta client to transfer a file to a TFTP server.\n\tAlso enable download support in tftpd, if tftpd is selected.\n\nconfig BUSYBOX_CONFIG_FEATURE_TFTP_BLOCKSIZE\n\tbool \"Enable 'blksize' and 'tsize' protocol options\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_TFTP_BLOCKSIZE\n\tdepends on BUSYBOX_CONFIG_TFTP || BUSYBOX_CONFIG_TFTPD\n\thelp\n\tAllow tftp to specify block size, and tftpd to understand\n\t\"blksize\" and \"tsize\" options.\n\nconfig BUSYBOX_CONFIG_TFTP_DEBUG\n\tbool \"Enable debug\"\n\tdefault BUSYBOX_DEFAULT_TFTP_DEBUG\n\tdepends on BUSYBOX_CONFIG_TFTP || BUSYBOX_CONFIG_TFTPD\n\thelp\n\tMake tftp[d] print debugging messages on stderr.\n\tThis is useful if you are diagnosing a bug in tftp[d].\nconfig BUSYBOX_CONFIG_TLS\n\tbool #No description makes it a hidden option\n\tdefault BUSYBOX_DEFAULT_TLS\nconfig BUSYBOX_CONFIG_TRACEROUTE\n\tbool \"traceroute (11 kb)\"\n\tdefault BUSYBOX_DEFAULT_TRACEROUTE\n\thelp\n\tUtility to trace the route of IP packets.\n\nconfig BUSYBOX_CONFIG_TRACEROUTE6\n\tbool \"traceroute6 (13 kb)\"\n\tdefault BUSYBOX_DEFAULT_TRACEROUTE6\n\tdepends on BUSYBOX_CONFIG_FEATURE_IPV6\n\thelp\n\tUtility to trace the route of IPv6 packets.\n\nconfig BUSYBOX_CONFIG_FEATURE_TRACEROUTE_VERBOSE\n\tbool \"Enable verbose output\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_TRACEROUTE_VERBOSE\n\tdepends on BUSYBOX_CONFIG_TRACEROUTE || BUSYBOX_CONFIG_TRACEROUTE6\n\thelp\n\tAdd some verbosity to traceroute. This includes among other things\n\thostnames and ICMP response types.\n\nconfig BUSYBOX_CONFIG_FEATURE_TRACEROUTE_USE_ICMP\n\tbool \"Enable -I option (use ICMP instead of UDP)\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_TRACEROUTE_USE_ICMP\n\tdepends on BUSYBOX_CONFIG_TRACEROUTE || BUSYBOX_CONFIG_TRACEROUTE6\nconfig BUSYBOX_CONFIG_TUNCTL\n\tbool \"tunctl (6.2 kb)\"\n\tdefault BUSYBOX_DEFAULT_TUNCTL\n\thelp\n\ttunctl creates or deletes tun devices.\n\nconfig BUSYBOX_CONFIG_FEATURE_TUNCTL_UG\n\tbool \"Support owner:group assignment\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_TUNCTL_UG\n\tdepends on BUSYBOX_CONFIG_TUNCTL\n\thelp\n\tAllow to specify owner and group of newly created interface.\n\t340 bytes of pure bloat. Say no here.\nconfig BUSYBOX_CONFIG_VCONFIG\n\tbool \"vconfig (2.3 kb)\"\n\tdefault BUSYBOX_DEFAULT_VCONFIG\n\thelp\n\tCreates, removes, and configures VLAN interfaces\nconfig BUSYBOX_CONFIG_WGET\n\tbool \"wget (38 kb)\"\n\tdefault BUSYBOX_DEFAULT_WGET\n\thelp\n\twget is a utility for non-interactive download of files from HTTP\n\tand FTP servers.\n\nconfig BUSYBOX_CONFIG_FEATURE_WGET_LONG_OPTIONS\n\tbool \"Enable long options\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_WGET_LONG_OPTIONS\n\tdepends on BUSYBOX_CONFIG_WGET && BUSYBOX_CONFIG_LONG_OPTS\n\nconfig BUSYBOX_CONFIG_FEATURE_WGET_STATUSBAR\n\tbool \"Enable progress bar (+2k)\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_WGET_STATUSBAR\n\tdepends on BUSYBOX_CONFIG_WGET\n\nconfig BUSYBOX_CONFIG_FEATURE_WGET_FTP\n\tbool \"Enable FTP protocol (+1k)\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_WGET_FTP\n\tdepends on BUSYBOX_CONFIG_WGET\n\thelp\n\tTo support FTPS, enable FEATURE_WGET_HTTPS as well.\n\nconfig BUSYBOX_CONFIG_FEATURE_WGET_AUTHENTICATION\n\tbool \"Enable HTTP authentication\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_WGET_AUTHENTICATION\n\tdepends on BUSYBOX_CONFIG_WGET\n\thelp\n\tSupport authenticated HTTP transfers.\n\nconfig BUSYBOX_CONFIG_FEATURE_WGET_TIMEOUT\n\tbool \"Enable timeout option -T SEC\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_WGET_TIMEOUT\n\tdepends on BUSYBOX_CONFIG_WGET\n\thelp\n\tSupports network read and connect timeouts for wget,\n\tso that wget will give up and timeout, through the -T\n\tcommand line option.\n\n\tCurrently only connect and network data read timeout are\n\tsupported (i.e., timeout is not applied to the DNS query). When\n\tFEATURE_WGET_LONG_OPTIONS is also enabled, the --timeout option\n\twill work in addition to -T.\n\nconfig BUSYBOX_CONFIG_FEATURE_WGET_HTTPS\n\tbool \"Support HTTPS using internal TLS code\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_WGET_HTTPS\n\tdepends on BUSYBOX_CONFIG_WGET\n\tselect BUSYBOX_CONFIG_TLS\n\thelp\n\twget will use internal TLS code to connect to https:// URLs.\n\tIt also enables FTPS support, but it's not well tested yet.\n\tNote:\n\tOn NOMMU machines, ssl_helper applet should be available\n\tin the $PATH for this to work. Make sure to select that applet.\n\n\tNote: currently, TLS code only makes TLS I/O work, it\n\tdoes *not* check that the peer is who it claims to be, etc.\n\tIOW: it uses peer-supplied public keys to establish encryption\n\tand signing keys, then encrypts and signs outgoing data and\n\tdecrypts incoming data.\n\tIt does not check signature hashes on the incoming data:\n\tthis means that attackers manipulating TCP packets can\n\tsend altered data and we unknowingly receive garbage.\n\t(This check might be relatively easy to add).\n\tIt does not check public key's certificate:\n\tthis means that the peer may be an attacker impersonating\n\tthe server we think we are talking to.\n\n\tIf you think this is unacceptable, consider this. As more and more\n\tservers switch to HTTPS-only operation, without such \"crippled\"\n\tTLS code it is *impossible* to simply download a kernel source\n\tfrom kernel.org. Which can in real world translate into\n\t\"my small automatic tooling to build cross-compilers from sources\n\tno longer works, I need to additionally keep a local copy\n\tof ~4 megabyte source tarball of a SSL library and ~2 megabyte\n\tsource of wget, need to compile and built both before I can\n\tdownload anything. All this despite the fact that the build\n\tis done in a QEMU sandbox on a machine with absolutely nothing\n\tworth stealing, so I don't care if someone would go to a lot\n\tof trouble to intercept my HTTPS download to send me an altered\n\tkernel tarball\".\n\n\tIf you still think this is unacceptable, send patches.\n\n\tIf you still think this is unacceptable, do not want to send\n\tpatches, but do want to waste bandwidth expaining how wrong\n\tit is, you will be ignored.\n\n\tFEATURE_WGET_OPENSSL does implement TLS verification\n\tusing the certificates available to OpenSSL.\n\nconfig BUSYBOX_CONFIG_FEATURE_WGET_OPENSSL\n\tbool \"Try to connect to HTTPS using openssl\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_WGET_OPENSSL\n\tdepends on BUSYBOX_CONFIG_WGET\n\thelp\n\tTry to use openssl to handle HTTPS.\n\n\tOpenSSL has a simple SSL client for debug purposes.\n\tIf you select this option, wget will effectively run:\n\t\"openssl s_client -quiet -connect hostname:443\n\t-servername hostname 2>/dev/null\" and pipe its data\n\tthrough it. -servername is not used if hostname is numeric.\n\tNote inconvenient API: host resolution is done twice,\n\tand there is no guarantee openssl's idea of IPv6 address\n\tformat is the same as ours.\n\tAnother problem is that s_client prints debug information\n\tto stderr, and it needs to be suppressed. This means\n\tall error messages get suppressed too.\n\topenssl is also a big binary, often dynamically linked\n\tagainst ~15 libraries.\n\n\tIf openssl can't be executed, internal TLS code will be used\n\t(if you enabled it); if openssl can be executed but fails later,\n\twget can't detect this, and download will fail.\n\n\tBy default TLS verification is performed, unless\n\t--no-check-certificate option is passed.\nconfig BUSYBOX_CONFIG_WHOIS\n\tbool \"whois (6.3 kb)\"\n\tdefault BUSYBOX_DEFAULT_WHOIS\n\thelp\n\twhois is a client for the whois directory service\nconfig BUSYBOX_CONFIG_ZCIP\n\tbool \"zcip (8.4 kb)\"\n\tdefault BUSYBOX_DEFAULT_ZCIP\n\tselect BUSYBOX_CONFIG_FEATURE_SYSLOG\n\thelp\n\tZCIP provides ZeroConf IPv4 address selection, according to RFC 3927.\n\tIt's a daemon that allocates and defends a dynamically assigned\n\taddress on the 169.254/16 network, requiring no system administrator.\n\n\tSee http://www.zeroconf.org for further details, and \"zcip.script\"\n\tin the busybox examples.\n\nsource \"udhcp/Config.in\"\n\nconfig BUSYBOX_CONFIG_IFUPDOWN_UDHCPC_CMD_OPTIONS\n\tstring \"ifup udhcpc command line options\"\n\tdefault BUSYBOX_DEFAULT_IFUPDOWN_UDHCPC_CMD_OPTIONS\n\tdepends on BUSYBOX_CONFIG_IFUP || BUSYBOX_CONFIG_IFDOWN\n\thelp\n\tCommand line options to pass to udhcpc from ifup.\n\tIntended to alter options not available in /etc/network/interfaces.\n\t(IE: --syslog --background etc...)\n\nendmenu\n"
  },
  {
    "path": "package/utils/busybox/config/networking/udhcp/Config.in",
    "content": "# DO NOT EDIT. This file is generated from Config.src\n#\n# For a description of the syntax of this configuration file,\n# see docs/Kconfig-language.txt.\n#\n\nconfig BUSYBOX_CONFIG_UDHCPD\n\tbool \"udhcpd (21 kb)\"\n\tdefault BUSYBOX_DEFAULT_UDHCPD\n\thelp\n\tudhcpd is a DHCP server geared primarily toward embedded systems,\n\twhile striving to be fully functional and RFC compliant.\n\nconfig BUSYBOX_CONFIG_FEATURE_UDHCPD_BASE_IP_ON_MAC\n\tbool \"Select IP address based on client MAC\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_UDHCPD_BASE_IP_ON_MAC\n\tdepends on BUSYBOX_CONFIG_UDHCPD\n\thelp\n\tIf selected, udhcpd will base its selection of IP address to offer\n\ton the client's hardware address. Otherwise udhcpd uses the next\n\tconsecutive free address.\n\n\tThis reduces the frequency of IP address changes for clients\n\twhich let their lease expire, and makes consecutive DHCPOFFERS\n\tfor the same client to (almost always) contain the same\n\tIP address.\n\nconfig BUSYBOX_CONFIG_FEATURE_UDHCPD_WRITE_LEASES_EARLY\n\tbool \"Rewrite lease file at every new acknowledge\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_UDHCPD_WRITE_LEASES_EARLY\n\tdepends on BUSYBOX_CONFIG_UDHCPD\n\thelp\n\tIf selected, udhcpd will write a new file with leases every\n\ttime a new lease has been accepted, thus eliminating the need\n\tto send SIGUSR1 for the initial writing or updating. Any timed\n\trewriting remains undisturbed.\n\nconfig BUSYBOX_CONFIG_DHCPD_LEASES_FILE\n\tstring \"Absolute path to lease file\"\n\tdefault BUSYBOX_DEFAULT_DHCPD_LEASES_FILE\n\tdepends on BUSYBOX_CONFIG_UDHCPD\n\thelp\n\tudhcpd stores addresses in a lease file. This is the absolute path\n\tof the file. Normally it is safe to leave it untouched.\n\nconfig BUSYBOX_CONFIG_DUMPLEASES\n\tbool \"dumpleases (5.1 kb)\"\n\tdefault BUSYBOX_DEFAULT_DUMPLEASES\n\thelp\n\tdumpleases displays the leases written out by the udhcpd.\n\tLease times are stored in the file by time remaining in lease, or\n\tby the absolute time that it expires in seconds from epoch.\n\nconfig BUSYBOX_CONFIG_DHCPRELAY\n\tbool \"dhcprelay (5.2 kb)\"\n\tdefault BUSYBOX_DEFAULT_DHCPRELAY\n\thelp\n\tdhcprelay listens for DHCP requests on one or more interfaces\n\tand forwards these requests to a different interface or DHCP\n\tserver.\n\nconfig BUSYBOX_CONFIG_UDHCPC\n\tbool \"udhcpc (24 kb)\"\n\tdefault BUSYBOX_DEFAULT_UDHCPC\n\thelp\n\tudhcpc is a DHCP client geared primarily toward embedded systems,\n\twhile striving to be fully functional and RFC compliant.\n\n\tThe udhcp client negotiates a lease with the DHCP server and\n\truns a script when a lease is obtained or lost.\n\nconfig BUSYBOX_CONFIG_FEATURE_UDHCPC_ARPING\n\tbool \"Verify that the offered address is free, using ARP ping\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_UDHCPC_ARPING\n\tdepends on BUSYBOX_CONFIG_UDHCPC\n\thelp\n\tIf selected, udhcpc will send ARP probes and make sure\n\tthe offered address is really not in use by anyone. The client\n\twill DHCPDECLINE the offer if the address is in use,\n\tand restart the discover process.\n\nconfig BUSYBOX_CONFIG_FEATURE_UDHCPC_SANITIZEOPT\n\tbool \"Do not pass malformed host and domain names\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_UDHCPC_SANITIZEOPT\n\tdepends on BUSYBOX_CONFIG_UDHCPC\n\thelp\n\tIf selected, udhcpc will check some options (such as option 12 -\n\thostname) and if they don't look like valid hostnames\n\t(for example, if they start with dash or contain spaces),\n\tthey will be replaced with string \"bad\" when exporting\n\tto the environment.\n\nconfig BUSYBOX_CONFIG_UDHCPC_DEFAULT_SCRIPT\n\tstring \"Absolute path to config script\"\n\tdefault BUSYBOX_DEFAULT_UDHCPC_DEFAULT_SCRIPT\n\tdepends on BUSYBOX_CONFIG_UDHCPC || BUSYBOX_CONFIG_UDHCPC6\n\thelp\n\tThis script is called after udhcpc receives an answer. See\n\texamples/udhcp for a working example. Normally it is safe\n\tto leave this untouched.\n\n# udhcpc6 config is inserted here:\nconfig BUSYBOX_CONFIG_UDHCPC6\n\tbool \"udhcpc6 (21 kb)\"\n\tdefault BUSYBOX_DEFAULT_UDHCPC6\n\tdepends on BUSYBOX_CONFIG_FEATURE_IPV6\n\thelp\n\tudhcpc6 is a DHCPv6 client\n\nconfig BUSYBOX_CONFIG_FEATURE_UDHCPC6_RFC3646\n\tbool \"Support RFC 3646 (DNS server and search list)\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_UDHCPC6_RFC3646\n\tdepends on BUSYBOX_CONFIG_UDHCPC6\n\thelp\n\tList of DNS servers and domain search list can be requested with\n\t\"-O dns\" and \"-O search\". If server gives these values,\n\tthey will be set in environment variables \"dns\" and \"search\".\n\nconfig BUSYBOX_CONFIG_FEATURE_UDHCPC6_RFC4704\n\tbool \"Support RFC 4704 (Client FQDN)\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_UDHCPC6_RFC4704\n\tdepends on BUSYBOX_CONFIG_UDHCPC6\n\thelp\n\tYou can request FQDN to be given by server using \"-O fqdn\".\n\nconfig BUSYBOX_CONFIG_FEATURE_UDHCPC6_RFC4833\n\tbool \"Support RFC 4833 (Timezones)\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_UDHCPC6_RFC4833\n\tdepends on BUSYBOX_CONFIG_UDHCPC6\n\thelp\n\tYou can request POSIX timezone with \"-O tz\" and timezone name\n\twith \"-O timezone\".\n\nconfig BUSYBOX_CONFIG_FEATURE_UDHCPC6_RFC5970\n\tbool \"Support RFC 5970 (Network Boot)\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_UDHCPC6_RFC5970\n\tdepends on BUSYBOX_CONFIG_UDHCPC6\n\thelp\n\tYou can request bootfile-url with \"-O bootfile_url\" and\n\tbootfile-params with \"-O bootfile_params\".\n\ncomment \"Common options for DHCP applets\"\n        depends on BUSYBOX_CONFIG_UDHCPD || BUSYBOX_CONFIG_UDHCPC || BUSYBOX_CONFIG_UDHCPC6 || BUSYBOX_CONFIG_DHCPRELAY\n\nconfig BUSYBOX_CONFIG_UDHCPC_DEFAULT_INTERFACE\n\tstring \"Default interface name\"\n\tdefault BUSYBOX_DEFAULT_UDHCPC_DEFAULT_INTERFACE\n\tdepends on BUSYBOX_CONFIG_UDHCPC || BUSYBOX_CONFIG_UDHCPC6\n\thelp\n\tThe interface that will be used if no other interface is\n\tspecified on the commandline.\n\nconfig BUSYBOX_CONFIG_FEATURE_UDHCP_PORT\n\tbool \"Enable '-P port' option for udhcpd and udhcpc\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_UDHCP_PORT\n\tdepends on BUSYBOX_CONFIG_UDHCPD || BUSYBOX_CONFIG_UDHCPC || BUSYBOX_CONFIG_UDHCPC6\n\thelp\n\tAt the cost of ~300 bytes, enables -P port option.\n\tThis feature is typically not needed.\n\nconfig BUSYBOX_CONFIG_UDHCP_DEBUG\n\tint \"Maximum verbosity level (0..9)\"\n\tdefault BUSYBOX_DEFAULT_UDHCP_DEBUG\n\trange 0 9\n\tdepends on BUSYBOX_CONFIG_UDHCPD || BUSYBOX_CONFIG_UDHCPC || BUSYBOX_CONFIG_UDHCPC6 || BUSYBOX_CONFIG_DHCPRELAY\n\thelp\n\tVerbosity can be increased with multiple -v options.\n\tThis option controls how high it can be cranked up.\n\n\tBigger values result in bigger code. Levels above 1\n\tare very verbose and useful for debugging only.\n\nconfig BUSYBOX_CONFIG_UDHCPC_SLACK_FOR_BUGGY_SERVERS\n\tint \"DHCP options slack buffer size\"\n\tdefault BUSYBOX_DEFAULT_UDHCPC_SLACK_FOR_BUGGY_SERVERS\n\trange 0 924\n\tdepends on BUSYBOX_CONFIG_UDHCPD || BUSYBOX_CONFIG_UDHCPC\n\thelp\n\tSome buggy DHCP servers send DHCP offer packets with option\n\tfield larger than we expect (which might also be considered a\n\tbuffer overflow attempt). These packets are normally discarded.\n\tIf circumstances beyond your control force you to support such\n\tservers, this may help. The upper limit (924) makes udhcpc accept\n\teven 1500 byte packets (maximum-sized ethernet packets).\n\n\tThis option does not make udhcp[cd] emit non-standard\n\tsized packets.\n\n\tKnown buggy DHCP servers:\n\t3Com OfficeConnect Remote 812 ADSL Router:\n\t\tseems to confuse maximum allowed UDP packet size with\n\t\tmaximum size of entire IP packet, and sends packets\n\t\twhich are 28 bytes too large.\n\tSeednet (ISP) VDSL: sends packets 2 bytes too large.\n\nconfig BUSYBOX_CONFIG_FEATURE_UDHCP_RFC3397\n\tbool \"Support RFC 3397 domain search options\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_UDHCP_RFC3397\n\tdepends on BUSYBOX_CONFIG_UDHCPD || BUSYBOX_CONFIG_UDHCPC\n\thelp\n\tIf selected, both client and server will support passing of domain\n\tsearch lists via option 119, specified in RFC 3397,\n\tand SIP servers option 120, specified in RFC 3361.\n\nconfig BUSYBOX_CONFIG_FEATURE_UDHCP_8021Q\n\tbool \"Support 802.1Q VLAN parameters options\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_UDHCP_8021Q\n\tdepends on BUSYBOX_CONFIG_UDHCPD || BUSYBOX_CONFIG_UDHCPC\n\thelp\n\tIf selected, both client and server will support passing of VLAN\n\tID and priority via options 132 and 133 as per 802.1Q.\n"
  },
  {
    "path": "package/utils/busybox/config/printutils/Config.in",
    "content": "# DO NOT EDIT. This file is generated from Config.src\n#\n# For a description of the syntax of this configuration file,\n# see docs/Kconfig-language.txt.\n#\n\nmenu \"Print Utilities\"\n\nconfig BUSYBOX_CONFIG_LPD\n\tbool \"lpd (5.5 kb)\"\n\tdefault BUSYBOX_DEFAULT_LPD\n\thelp\n\tlpd is a print spooling daemon.\nconfig BUSYBOX_CONFIG_LPR\n\tbool \"lpr (9.9 kb)\"\n\tdefault BUSYBOX_DEFAULT_LPR\n\thelp\n\tlpr sends files (or standard input) to a print spooling daemon.\n\nconfig BUSYBOX_CONFIG_LPQ\n\tbool \"lpq (9.9 kb)\"\n\tdefault BUSYBOX_DEFAULT_LPQ\n\thelp\n\tlpq is a print spool queue examination and manipulation program.\n\nendmenu\n"
  },
  {
    "path": "package/utils/busybox/config/procps/Config.in",
    "content": "# DO NOT EDIT. This file is generated from Config.src\n#\n# For a description of the syntax of this configuration file,\n# see docs/Kconfig-language.txt.\n#\n\nmenu \"Process Utilities\"\n\nconfig BUSYBOX_CONFIG_FEATURE_FAST_TOP\n\tbool \"Faster /proc scanning code (+100 bytes)\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_FAST_TOP  # all \"fast or small\" options default to small\n\thelp\n\tThis option makes top and ps ~20% faster (or 20% less CPU hungry),\n\tbut code size is slightly bigger.\n\nconfig BUSYBOX_CONFIG_FEATURE_SHOW_THREADS\n\tbool \"Support thread display in ps/pstree/top\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_SHOW_THREADS\n\tdepends on BUSYBOX_CONFIG_PS || BUSYBOX_CONFIG_TOP || BUSYBOX_CONFIG_PSTREE\n\thelp\n\tEnables the ps -T option, showing of threads in pstree,\n\tand 'h' command in top.\n\nconfig BUSYBOX_CONFIG_FREE\n\tbool \"free (3.1 kb)\"\n\tdefault BUSYBOX_DEFAULT_FREE\n\thelp\n\tfree displays the total amount of free and used physical and swap\n\tmemory in the system, as well as the buffers used by the kernel.\n\tThe shared memory column should be ignored; it is obsolete.\nconfig BUSYBOX_CONFIG_FUSER\n\tbool \"fuser (7 kb)\"\n\tdefault BUSYBOX_DEFAULT_FUSER\n\thelp\n\tfuser lists all PIDs (Process IDs) that currently have a given\n\tfile open. fuser can also list all PIDs that have a given network\n\t(TCP or UDP) port open.\nconfig BUSYBOX_CONFIG_IOSTAT\n\tbool \"iostat (7.6 kb)\"\n\tdefault BUSYBOX_DEFAULT_IOSTAT\n\thelp\n\tReport CPU and I/O statistics\nconfig BUSYBOX_CONFIG_KILL\n\tbool \"kill (3.1 kb)\"\n\tdefault BUSYBOX_DEFAULT_KILL\n\thelp\n\tThe command kill sends the specified signal to the specified\n\tprocess or process group. If no signal is specified, the TERM\n\tsignal is sent.\n\nconfig BUSYBOX_CONFIG_KILLALL\n\tbool \"killall (5.6 kb)\"\n\tdefault BUSYBOX_DEFAULT_KILLALL\n\thelp\n\tkillall sends a signal to all processes running any of the\n\tspecified commands. If no signal name is specified, SIGTERM is\n\tsent.\n\nconfig BUSYBOX_CONFIG_KILLALL5\n\tbool \"killall5 (5.3 kb)\"\n\tdefault BUSYBOX_DEFAULT_KILLALL5\n\thelp\n\tThe SystemV killall command. killall5 sends a signal\n\tto all processes except kernel threads and the processes\n\tin its own session, so it won't kill the shell that is running\n\tthe script it was called from.\nconfig BUSYBOX_CONFIG_LSOF\n\tbool \"lsof (3.4 kb)\"\n\tdefault BUSYBOX_DEFAULT_LSOF\n\thelp\n\tShow open files in the format of:\n\tPID <TAB> /path/to/executable <TAB> /path/to/opened/file\nconfig BUSYBOX_CONFIG_MPSTAT\n\tbool \"mpstat (9.8 kb)\"\n\tdefault BUSYBOX_DEFAULT_MPSTAT\n\thelp\n\tPer-processor statistics\nconfig BUSYBOX_CONFIG_NMETER\n\tbool \"nmeter (11 kb)\"\n\tdefault BUSYBOX_DEFAULT_NMETER\n\thelp\n\tPrints selected system stats continuously, one line per update.\nconfig BUSYBOX_CONFIG_PGREP\n\tbool \"pgrep (6.5 kb)\"\n\tdefault BUSYBOX_DEFAULT_PGREP\n\thelp\n\tLook for processes by name.\n\nconfig BUSYBOX_CONFIG_PKILL\n\tbool \"pkill (7.5 kb)\"\n\tdefault BUSYBOX_DEFAULT_PKILL\n\thelp\n\tSend signals to processes by name.\nconfig BUSYBOX_CONFIG_PIDOF\n\tbool \"pidof (6.3 kb)\"\n\tdefault BUSYBOX_DEFAULT_PIDOF\n\thelp\n\tPidof finds the process id's (pids) of the named programs. It prints\n\tthose id's on the standard output.\n\nconfig BUSYBOX_CONFIG_FEATURE_PIDOF_SINGLE\n\tbool \"Enable single shot (-s)\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_PIDOF_SINGLE\n\tdepends on BUSYBOX_CONFIG_PIDOF\n\thelp\n\tSupport '-s' for returning only the first pid found.\n\nconfig BUSYBOX_CONFIG_FEATURE_PIDOF_OMIT\n\tbool \"Enable omitting pids (-o PID)\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_PIDOF_OMIT\n\tdepends on BUSYBOX_CONFIG_PIDOF\n\thelp\n\tSupport '-o PID' for omitting the given pid(s) in output.\n\tThe special pid %PPID can be used to name the parent process\n\tof the pidof, in other words the calling shell or shell script.\nconfig BUSYBOX_CONFIG_PMAP\n\tbool \"pmap (6 kb)\"\n\tdefault BUSYBOX_DEFAULT_PMAP\n\thelp\n\tDisplay processes' memory mappings.\nconfig BUSYBOX_CONFIG_POWERTOP\n\tbool \"powertop (9.6 kb)\"\n\tdefault BUSYBOX_DEFAULT_POWERTOP\n\thelp\n\tAnalyze power consumption on Intel-based laptops\n\nconfig BUSYBOX_CONFIG_FEATURE_POWERTOP_INTERACTIVE\n\tbool \"Accept keyboard commands\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_POWERTOP_INTERACTIVE\n\tdepends on BUSYBOX_CONFIG_POWERTOP\n\thelp\n\tWithout this, powertop will only refresh display every 10 seconds.\n\tNo keyboard commands will work, only ^C to terminate.\nconfig BUSYBOX_CONFIG_PS\n\tbool \"ps (11 kb)\"\n\tdefault BUSYBOX_DEFAULT_PS\n\thelp\n\tps gives a snapshot of the current processes.\n\nconfig BUSYBOX_CONFIG_FEATURE_PS_WIDE\n\tbool \"Enable wide output (-w)\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_PS_WIDE\n\tdepends on (BUSYBOX_CONFIG_PS || BUSYBOX_CONFIG_MINIPS) && !BUSYBOX_CONFIG_DESKTOP\n\thelp\n\tSupport argument 'w' for wide output.\n\tIf given once, 132 chars are printed, and if given more\n\tthan once, the length is unlimited.\n\nconfig BUSYBOX_CONFIG_FEATURE_PS_LONG\n\tbool \"Enable long output (-l)\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_PS_LONG\n\tdepends on (BUSYBOX_CONFIG_PS || BUSYBOX_CONFIG_MINIPS) && !BUSYBOX_CONFIG_DESKTOP\n\thelp\n\tSupport argument 'l' for long output.\n\tAdds fields PPID, RSS, START, TIME & TTY\n\nconfig BUSYBOX_CONFIG_FEATURE_PS_TIME\n\tbool \"Enable -o time and -o etime specifiers\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_PS_TIME\n\tdepends on (BUSYBOX_CONFIG_PS || BUSYBOX_CONFIG_MINIPS) && BUSYBOX_CONFIG_DESKTOP\n\nconfig BUSYBOX_CONFIG_FEATURE_PS_UNUSUAL_SYSTEMS\n\tbool \"Support Linux prior to 2.4.0 and non-ELF systems\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_PS_UNUSUAL_SYSTEMS\n\tdepends on BUSYBOX_CONFIG_FEATURE_PS_TIME\n\thelp\n\tInclude support for measuring HZ on old kernels and non-ELF systems\n\t(if you are on Linux 2.4.0+ and use ELF, you don't need this)\n\nconfig BUSYBOX_CONFIG_FEATURE_PS_ADDITIONAL_COLUMNS\n\tbool \"Enable -o rgroup, -o ruser, -o nice specifiers\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_PS_ADDITIONAL_COLUMNS\n\tdepends on (BUSYBOX_CONFIG_PS || BUSYBOX_CONFIG_MINIPS) && BUSYBOX_CONFIG_DESKTOP\nconfig BUSYBOX_CONFIG_PSTREE\n\tbool \"pstree (9.3 kb)\"\n\tdefault BUSYBOX_DEFAULT_PSTREE\n\thelp\n\tDisplay a tree of processes.\nconfig BUSYBOX_CONFIG_PWDX\n\tbool \"pwdx (3.7 kb)\"\n\tdefault BUSYBOX_DEFAULT_PWDX\n\thelp\n\tReport current working directory of a process\nconfig BUSYBOX_CONFIG_SMEMCAP\n\tbool \"smemcap (2.5 kb)\"\n\tdefault BUSYBOX_DEFAULT_SMEMCAP\n\thelp\n\tsmemcap is a tool for capturing process data for smem,\n\ta memory usage statistic tool.\nconfig BUSYBOX_CONFIG_BB_SYSCTL\n\tbool \"sysctl (7.4 kb)\"\n\tdefault BUSYBOX_DEFAULT_BB_SYSCTL\n\thelp\n\tConfigure kernel parameters at runtime.\nconfig BUSYBOX_CONFIG_TOP\n\tbool \"top (18 kb)\"\n\tdefault BUSYBOX_DEFAULT_TOP\n\thelp\n\tThe top program provides a dynamic real-time view of a running\n\tsystem.\n\nconfig BUSYBOX_CONFIG_FEATURE_TOP_INTERACTIVE\n\tbool \"Accept keyboard commands\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_TOP_INTERACTIVE\n\tdepends on BUSYBOX_CONFIG_TOP\n\thelp\n\tWithout this, top will only refresh display every 5 seconds.\n\tNo keyboard commands will work, only ^C to terminate.\n\nconfig BUSYBOX_CONFIG_FEATURE_TOP_CPU_USAGE_PERCENTAGE\n\tbool \"Show CPU per-process usage percentage\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_TOP_CPU_USAGE_PERCENTAGE\n\tdepends on BUSYBOX_CONFIG_TOP\n\thelp\n\tMake top display CPU usage for each process.\n\tThis adds about 2k.\n\nconfig BUSYBOX_CONFIG_FEATURE_TOP_CPU_GLOBAL_PERCENTS\n\tbool \"Show CPU global usage percentage\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_TOP_CPU_GLOBAL_PERCENTS\n\tdepends on BUSYBOX_CONFIG_FEATURE_TOP_CPU_USAGE_PERCENTAGE\n\thelp\n\tMakes top display \"CPU: NN% usr NN% sys...\" line.\n\tThis adds about 0.5k.\n\nconfig BUSYBOX_CONFIG_FEATURE_TOP_SMP_CPU\n\tbool \"SMP CPU usage display ('c' key)\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_TOP_SMP_CPU\n\tdepends on BUSYBOX_CONFIG_FEATURE_TOP_CPU_GLOBAL_PERCENTS\n\thelp\n\tAllow 'c' key to switch between individual/cumulative CPU stats\n\tThis adds about 0.5k.\n\nconfig BUSYBOX_CONFIG_FEATURE_TOP_DECIMALS\n\tbool \"Show 1/10th of a percent in CPU/mem statistics\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_TOP_DECIMALS\n\tdepends on BUSYBOX_CONFIG_FEATURE_TOP_CPU_USAGE_PERCENTAGE\n\thelp\n\tShow 1/10th of a percent in CPU/mem statistics.\n\tThis adds about 0.3k.\n\nconfig BUSYBOX_CONFIG_FEATURE_TOP_SMP_PROCESS\n\tbool \"Show CPU process runs on ('j' field)\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_TOP_SMP_PROCESS\n\tdepends on BUSYBOX_CONFIG_TOP\n\thelp\n\tShow CPU where process was last found running on.\n\tThis is the 'j' field.\n\nconfig BUSYBOX_CONFIG_FEATURE_TOPMEM\n\tbool \"Topmem command ('s' key)\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_TOPMEM\n\tdepends on BUSYBOX_CONFIG_TOP\n\thelp\n\tEnable 's' in top (gives lots of memory info).\nconfig BUSYBOX_CONFIG_UPTIME\n\tbool \"uptime (3.7 kb)\"\n\tdefault BUSYBOX_DEFAULT_UPTIME\n\thelp\n\tuptime gives a one line display of the current time, how long\n\tthe system has been running, how many users are currently logged\n\ton, and the system load averages for the past 1, 5, and 15 minutes.\n\nconfig BUSYBOX_CONFIG_FEATURE_UPTIME_UTMP_SUPPORT\n\tbool \"Show the number of users\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_UPTIME_UTMP_SUPPORT\n\tdepends on BUSYBOX_CONFIG_UPTIME && BUSYBOX_CONFIG_FEATURE_UTMP\n\thelp\n\tDisplay the number of users currently logged on.\nconfig BUSYBOX_CONFIG_WATCH\n\tbool \"watch (4.4 kb)\"\n\tdefault BUSYBOX_DEFAULT_WATCH\n\thelp\n\twatch is used to execute a program periodically, showing\n\toutput to the screen.\n\nendmenu\n"
  },
  {
    "path": "package/utils/busybox/config/runit/Config.in",
    "content": "# DO NOT EDIT. This file is generated from Config.src\n#\n# For a description of the syntax of this configuration file,\n# see docs/Kconfig-language.txt.\n#\n\nmenu \"Runit Utilities\"\n\nconfig BUSYBOX_CONFIG_CHPST\n\tbool \"chpst (9 kb)\"\n\tdefault BUSYBOX_DEFAULT_CHPST\n\thelp\n\tchpst changes the process state according to the given options, and\n\texecs specified program.\n\nconfig BUSYBOX_CONFIG_SETUIDGID\n\tbool \"setuidgid (4 kb)\"\n\tdefault BUSYBOX_DEFAULT_SETUIDGID\n\thelp\n\tSets soft resource limits as specified by options\n\nconfig BUSYBOX_CONFIG_ENVUIDGID\n\tbool \"envuidgid (3.9 kb)\"\n\tdefault BUSYBOX_DEFAULT_ENVUIDGID\n\thelp\n\tSets $UID to account's uid and $GID to account's gid\n\nconfig BUSYBOX_CONFIG_ENVDIR\n\tbool \"envdir (2.5 kb)\"\n\tdefault BUSYBOX_DEFAULT_ENVDIR\n\thelp\n\tSets various environment variables as specified by files\n\tin the given directory\n\nconfig BUSYBOX_CONFIG_SOFTLIMIT\n\tbool \"softlimit (4.5 kb)\"\n\tdefault BUSYBOX_DEFAULT_SOFTLIMIT\n\thelp\n\tSets soft resource limits as specified by options\nconfig BUSYBOX_CONFIG_RUNSV\n\tbool \"runsv (7.8 kb)\"\n\tdefault BUSYBOX_DEFAULT_RUNSV\n\thelp\n\trunsv starts and monitors a service and optionally an appendant log\n\tservice.\nconfig BUSYBOX_CONFIG_RUNSVDIR\n\tbool \"runsvdir (6.3 kb)\"\n\tdefault BUSYBOX_DEFAULT_RUNSVDIR\n\thelp\n\trunsvdir starts a runsv process for each subdirectory, or symlink to\n\ta directory, in the services directory dir, up to a limit of 1000\n\tsubdirectories, and restarts a runsv process if it terminates.\n\nconfig BUSYBOX_CONFIG_FEATURE_RUNSVDIR_LOG\n\tbool \"Enable scrolling argument log\"\n\tdepends on BUSYBOX_CONFIG_RUNSVDIR\n\tdefault BUSYBOX_DEFAULT_FEATURE_RUNSVDIR_LOG\n\thelp\n\tEnable feature where second parameter of runsvdir holds last error\n\tmessage (viewable via top/ps). Otherwise (feature is off\n\tor no parameter), error messages go to stderr only.\nconfig BUSYBOX_CONFIG_SV\n\tbool \"sv (8.5 kb)\"\n\tdefault BUSYBOX_DEFAULT_SV\n\thelp\n\tsv reports the current status and controls the state of services\n\tmonitored by the runsv supervisor.\n\nconfig BUSYBOX_CONFIG_SV_DEFAULT_SERVICE_DIR\n\tstring \"Default directory for services\"\n\tdefault BUSYBOX_DEFAULT_SV_DEFAULT_SERVICE_DIR\n\tdepends on BUSYBOX_CONFIG_SV || BUSYBOX_CONFIG_SVC || BUSYBOX_CONFIG_SVOK\n\thelp\n\tDefault directory for services.\n\tDefaults to \"/var/service\"\n\nconfig BUSYBOX_CONFIG_SVC\n\tbool \"svc (8.4 kb)\"\n\tdefault BUSYBOX_DEFAULT_SVC\n\thelp\n\tsvc controls the state of services monitored by the runsv supervisor.\n\tIt is compatible with daemontools command with the same name.\n\nconfig BUSYBOX_CONFIG_SVOK\n\tbool \"svok (1.5 kb)\"\n\tdefault BUSYBOX_DEFAULT_SVOK\n\thelp\n\tsvok checks whether runsv supervisor is running.\n\tIt is compatible with daemontools command with the same name.\nconfig BUSYBOX_CONFIG_SVLOGD\n\tbool \"svlogd (16 kb)\"\n\tdefault BUSYBOX_DEFAULT_SVLOGD\n\thelp\n\tsvlogd continuously reads log data from its standard input, optionally\n\tfilters log messages, and writes the data to one or more automatically\n\trotated logs.\n\nendmenu\n"
  },
  {
    "path": "package/utils/busybox/config/selinux/Config.in",
    "content": "# DO NOT EDIT. This file is generated from Config.src\n#\n# For a description of the syntax of this configuration file,\n# see docs/Kconfig-language.txt.\n#\n\nmenu \"SELinux Utilities\"\n\tdepends on BUSYBOX_CONFIG_SELINUX\n\nconfig BUSYBOX_CONFIG_CHCON\n\tbool \"chcon (8.9 kb)\"\n\tdefault BUSYBOX_DEFAULT_CHCON\n\tdepends on BUSYBOX_CONFIG_SELINUX\n\thelp\n\tEnable support to change the security context of file.\nconfig BUSYBOX_CONFIG_GETENFORCE\n\tbool \"getenforce (1.7 kb)\"\n\tdefault BUSYBOX_DEFAULT_GETENFORCE\n\tdepends on BUSYBOX_CONFIG_SELINUX\n\thelp\n\tEnable support to get the current mode of SELinux.\nconfig BUSYBOX_CONFIG_GETSEBOOL\n\tbool \"getsebool (5.5 kb)\"\n\tdefault BUSYBOX_DEFAULT_GETSEBOOL\n\tdepends on BUSYBOX_CONFIG_SELINUX\n\thelp\n\tEnable support to get SELinux boolean values.\nconfig BUSYBOX_CONFIG_LOAD_POLICY\n\tbool \"load_policy (1.6 kb)\"\n\tdefault BUSYBOX_DEFAULT_LOAD_POLICY\n\tdepends on BUSYBOX_CONFIG_SELINUX\n\thelp\n\tEnable support to load SELinux policy.\nconfig BUSYBOX_CONFIG_MATCHPATHCON\n\tbool \"matchpathcon (6.1 kb)\"\n\tdefault BUSYBOX_DEFAULT_MATCHPATHCON\n\tdepends on BUSYBOX_CONFIG_SELINUX\n\thelp\n\tEnable support to get default security context of the\n\tspecified path from the file contexts configuration.\nconfig BUSYBOX_CONFIG_RUNCON\n\tbool \"runcon (6.6 kb)\"\n\tdefault BUSYBOX_DEFAULT_RUNCON\n\tdepends on BUSYBOX_CONFIG_SELINUX\n\thelp\n\tEnable support to run command in specified security context.\nconfig BUSYBOX_CONFIG_SELINUXENABLED\n\tbool \"selinuxenabled (321 bytes)\"\n\tdefault BUSYBOX_DEFAULT_SELINUXENABLED\n\tdepends on BUSYBOX_CONFIG_SELINUX\n\thelp\n\tEnable support for this command to be used within shell scripts\n\tto determine if selinux is enabled.\nconfig BUSYBOX_CONFIG_SESTATUS\n\tbool \"sestatus (12 kb)\"\n\tdefault BUSYBOX_DEFAULT_SESTATUS\n\tdepends on BUSYBOX_CONFIG_SELINUX\n\thelp\n\tDisplays the status of SELinux.\nconfig BUSYBOX_CONFIG_SETENFORCE\n\tbool \"setenforce (2.1 kb)\"\n\tdefault BUSYBOX_DEFAULT_SETENFORCE\n\tdepends on BUSYBOX_CONFIG_SELINUX\n\thelp\n\tEnable support to modify the mode SELinux is running in.\nconfig BUSYBOX_CONFIG_SETFILES\n\tbool \"setfiles (13 kb)\"\n\tdefault BUSYBOX_DEFAULT_SETFILES\n\tdepends on BUSYBOX_CONFIG_SELINUX\n\thelp\n\tEnable support to modify to relabel files.\n\tNotice: If you built libselinux with -D_FILE_OFFSET_BITS=64,\n\t(It is default in libselinux's Makefile), you _must_ enable\n\tCONFIG_LFS.\n\nconfig BUSYBOX_CONFIG_FEATURE_SETFILES_CHECK_OPTION\n\tbool \"Enable check option\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_SETFILES_CHECK_OPTION\n\tdepends on BUSYBOX_CONFIG_SETFILES\n\thelp\n\tSupport \"-c\" option (check the validity of the contexts against\n\tthe specified binary policy) for setfiles. Requires libsepol.\n\nconfig BUSYBOX_CONFIG_RESTORECON\n\tbool \"restorecon (12 kb)\"\n\tdefault BUSYBOX_DEFAULT_RESTORECON\n\tdepends on BUSYBOX_CONFIG_SELINUX\n\thelp\n\tEnable support to relabel files. The feature is almost\n\tthe same as setfiles, but usage is a little different.\nconfig BUSYBOX_CONFIG_SETSEBOOL\n\tbool \"setsebool (1.7 kb)\"\n\tdefault BUSYBOX_DEFAULT_SETSEBOOL\n\tdepends on BUSYBOX_CONFIG_SELINUX\n\thelp\n\tEnable support for change boolean.\n\tsemanage and -P option is not supported yet.\n\nendmenu\n"
  },
  {
    "path": "package/utils/busybox/config/shell/Config.in",
    "content": "# DO NOT EDIT. This file is generated from Config.src\n#\n# For a description of the syntax of this configuration file,\n# see docs/Kconfig-language.txt.\n#\n\nmenu \"Shells\"\n\n\nchoice\n\tprompt \"Choose which shell is aliased to 'sh' name\"\n\tdefault BUSYBOX_CONFIG_SH_IS_ASH\n\thelp\n\tChoose which shell you want to be executed by 'sh' alias.\n\tThe ash shell is the most bash compatible and full featured one.\n\n# note: cannot use \"select ASH\" here, it breaks \"make allnoconfig\"\nconfig BUSYBOX_CONFIG_SH_IS_ASH\n\tdepends on !BUSYBOX_CONFIG_NOMMU\n\tbool \"ash\"\n\tselect BUSYBOX_CONFIG_SHELL_ASH\n\thelp\n\tChoose ash to be the shell executed by 'sh' name.\n\tThe ash code will be built into busybox. If you don't select\n\t\"ash\" choice (CONFIG_ASH), this shell may only be invoked by\n\tthe name 'sh' (and not 'ash').\n\nconfig BUSYBOX_CONFIG_SH_IS_HUSH\n\tbool \"hush\"\n\tselect BUSYBOX_CONFIG_SHELL_HUSH\n\thelp\n\tChoose hush to be the shell executed by 'sh' name.\n\tThe hush code will be built into busybox. If you don't select\n\t\"hush\" choice (CONFIG_HUSH), this shell may only be invoked by\n\tthe name 'sh' (and not 'hush').\n\nconfig BUSYBOX_CONFIG_SH_IS_NONE\n\tbool \"none\"\n\nendchoice\n\nchoice\n\tprompt \"Choose which shell is aliased to 'bash' name\"\n\tdefault BUSYBOX_CONFIG_BASH_IS_NONE\n\thelp\n\tChoose which shell you want to be executed by 'bash' alias.\n\tThe ash shell is the most bash compatible and full featured one,\n\talthough compatibility is far from being complete.\n\n\tNote that selecting this option does not switch on any bash\n\tcompatibility code. It merely makes it possible to install\n\t/bin/bash (sym)link and run scripts which start with\n\t#!/bin/bash line.\n\n\tMany systems use it in scripts which use bash-specific features,\n\teven simple ones like $RANDOM. Without this option, busybox\n\tcan't be used for running them because it won't recongnize\n\t\"bash\" as a supported applet name.\n\nconfig BUSYBOX_CONFIG_BASH_IS_ASH\n\tdepends on !BUSYBOX_CONFIG_NOMMU\n\tbool \"ash\"\n\tselect BUSYBOX_CONFIG_SHELL_ASH\n\thelp\n\tChoose ash to be the shell executed by 'bash' name.\n\tThe ash code will be built into busybox. If you don't select\n\t\"ash\" choice (CONFIG_ASH), this shell may only be invoked by\n\tthe name 'bash' (and not 'ash').\n\nconfig BUSYBOX_CONFIG_BASH_IS_HUSH\n\tbool \"hush\"\n\tselect BUSYBOX_CONFIG_SHELL_HUSH\n\thelp\n\tChoose hush to be the shell executed by 'bash' name.\n\tThe hush code will be built into busybox. If you don't select\n\t\"hush\" choice (CONFIG_HUSH), this shell may only be invoked by\n\tthe name 'bash' (and not 'hush').\n\nconfig BUSYBOX_CONFIG_BASH_IS_NONE\n\tbool \"none\"\n\nendchoice\n\n\nconfig BUSYBOX_CONFIG_SHELL_ASH\n\tbool #hidden option\n\tdepends on !BUSYBOX_CONFIG_NOMMU\n\nconfig BUSYBOX_CONFIG_ASH\n\tbool \"ash (78 kb)\"\n\tdefault BUSYBOX_DEFAULT_ASH\n\tdepends on !BUSYBOX_CONFIG_NOMMU\n\tselect BUSYBOX_CONFIG_SHELL_ASH\n\thelp\n\tThe most complete and most pedantically correct shell included with\n\tbusybox. This shell is actually a derivative of the Debian 'dash'\n\tshell (by Herbert Xu), which was created by porting the 'ash' shell\n\t(written by Kenneth Almquist) from NetBSD.\n\n# ash options\n# note: Don't remove !NOMMU part in the next line; it would break\n# menuconfig's indenting.\nif !NOMMU && (BUSYBOX_CONFIG_SHELL_ASH || BUSYBOX_CONFIG_ASH || BUSYBOX_CONFIG_SH_IS_ASH || BUSYBOX_CONFIG_BASH_IS_ASH)\n\nconfig BUSYBOX_CONFIG_ASH_OPTIMIZE_FOR_SIZE\n\tbool \"Optimize for size instead of speed\"\n\tdefault BUSYBOX_DEFAULT_ASH_OPTIMIZE_FOR_SIZE\n\tdepends on BUSYBOX_CONFIG_SHELL_ASH\n\nconfig BUSYBOX_CONFIG_ASH_INTERNAL_GLOB\n\tbool \"Use internal glob() implementation\"\n\tdefault BUSYBOX_DEFAULT_ASH_INTERNAL_GLOB\t# Y is bigger, but because of uclibc glob() bug, let Y be default for now\n\tdepends on BUSYBOX_CONFIG_SHELL_ASH\n\thelp\n\tDo not use glob() function from libc, use internal implementation.\n\tUse this if you are getting \"glob.h: No such file or directory\"\n\tor similar build errors.\n\tNote that as of now (2017-01), uclibc and musl glob() both have bugs\n\twhich would break ash if you select N here.\n\nconfig BUSYBOX_CONFIG_ASH_BASH_COMPAT\n\tbool \"bash-compatible extensions\"\n\tdefault BUSYBOX_DEFAULT_ASH_BASH_COMPAT\n\tdepends on BUSYBOX_CONFIG_SHELL_ASH\n\nconfig BUSYBOX_CONFIG_ASH_BASH_SOURCE_CURDIR\n\tbool \"'source' and '.' builtins search current directory after $PATH\"\n\tdefault BUSYBOX_DEFAULT_ASH_BASH_SOURCE_CURDIR   # do not encourage non-standard behavior\n\tdepends on BUSYBOX_CONFIG_ASH_BASH_COMPAT\n\thelp\n\tThis is not compliant with standards. Avoid if possible.\n\nconfig BUSYBOX_CONFIG_ASH_BASH_NOT_FOUND_HOOK\n\tbool \"command_not_found_handle hook support\"\n\tdefault BUSYBOX_DEFAULT_ASH_BASH_NOT_FOUND_HOOK\n\tdepends on BUSYBOX_CONFIG_ASH_BASH_COMPAT\n\thelp\n\tEnable support for the 'command_not_found_handle' hook function,\n\tfrom GNU bash, which allows for alternative command not found\n\thandling.\n\nconfig BUSYBOX_CONFIG_ASH_JOB_CONTROL\n\tbool \"Job control\"\n\tdefault BUSYBOX_DEFAULT_ASH_JOB_CONTROL\n\tdepends on BUSYBOX_CONFIG_SHELL_ASH\n\nconfig BUSYBOX_CONFIG_ASH_ALIAS\n\tbool \"Alias support\"\n\tdefault BUSYBOX_DEFAULT_ASH_ALIAS\n\tdepends on BUSYBOX_CONFIG_SHELL_ASH\n\nconfig BUSYBOX_CONFIG_ASH_RANDOM_SUPPORT\n\tbool \"Pseudorandom generator and $RANDOM variable\"\n\tdefault BUSYBOX_DEFAULT_ASH_RANDOM_SUPPORT\n\tdepends on BUSYBOX_CONFIG_SHELL_ASH\n\thelp\n\tEnable pseudorandom generator and dynamic variable \"$RANDOM\".\n\tEach read of \"$RANDOM\" will generate a new pseudorandom value.\n\tYou can reset the generator by using a specified start value.\n\tAfter \"unset RANDOM\" the generator will switch off and this\n\tvariable will no longer have special treatment.\n\nconfig BUSYBOX_CONFIG_ASH_EXPAND_PRMT\n\tbool \"Expand prompt string\"\n\tdefault BUSYBOX_DEFAULT_ASH_EXPAND_PRMT\n\tdepends on BUSYBOX_CONFIG_SHELL_ASH\n\thelp\n\t$PS# may contain volatile content, such as backquote commands.\n\tThis option recreates the prompt string from the environment\n\tvariable each time it is displayed.\n\nconfig BUSYBOX_CONFIG_ASH_IDLE_TIMEOUT\n\tbool \"Idle timeout variable $TMOUT\"\n\tdefault BUSYBOX_DEFAULT_ASH_IDLE_TIMEOUT\n\tdepends on BUSYBOX_CONFIG_SHELL_ASH\n\thelp\n\tEnable bash-like auto-logout after $TMOUT seconds of idle time.\n\nconfig BUSYBOX_CONFIG_ASH_MAIL\n\tbool \"Check for new mail in interactive shell\"\n\tdefault BUSYBOX_DEFAULT_ASH_MAIL\n\tdepends on BUSYBOX_CONFIG_SHELL_ASH\n\thelp\n\tEnable \"check for new mail\" function:\n\tif set, $MAIL file and $MAILPATH list of files\n\tare checked for mtime changes, and \"you have mail\"\n\tmessage is printed if change is detected.\n\nconfig BUSYBOX_CONFIG_ASH_ECHO\n\tbool \"echo builtin\"\n\tdefault BUSYBOX_DEFAULT_ASH_ECHO\n\tdepends on BUSYBOX_CONFIG_SHELL_ASH\n\nconfig BUSYBOX_CONFIG_ASH_PRINTF\n\tbool \"printf builtin\"\n\tdefault BUSYBOX_DEFAULT_ASH_PRINTF\n\tdepends on BUSYBOX_CONFIG_SHELL_ASH\n\nconfig BUSYBOX_CONFIG_ASH_TEST\n\tbool \"test builtin\"\n\tdefault BUSYBOX_DEFAULT_ASH_TEST\n\tdepends on BUSYBOX_CONFIG_SHELL_ASH\n\nconfig BUSYBOX_CONFIG_ASH_HELP\n\tbool \"help builtin\"\n\tdefault BUSYBOX_DEFAULT_ASH_HELP\n\tdepends on BUSYBOX_CONFIG_SHELL_ASH\n\nconfig BUSYBOX_CONFIG_ASH_GETOPTS\n\tbool \"getopts builtin\"\n\tdefault BUSYBOX_DEFAULT_ASH_GETOPTS\n\tdepends on BUSYBOX_CONFIG_SHELL_ASH\n\nconfig BUSYBOX_CONFIG_ASH_CMDCMD\n\tbool \"command builtin\"\n\tdefault BUSYBOX_DEFAULT_ASH_CMDCMD\n\tdepends on BUSYBOX_CONFIG_SHELL_ASH\n\thelp\n\tEnable support for the 'command' builtin, which allows\n\tyou to run the specified command or builtin,\n\teven when there is a function with the same name.\n\nendif # ash options\nconfig BUSYBOX_CONFIG_CTTYHACK\n\tbool \"cttyhack (2.4 kb)\"\n\tdefault BUSYBOX_DEFAULT_CTTYHACK\n\thelp\n\tOne common problem reported on the mailing list is the \"can't\n\taccess tty; job control turned off\" error message, which typically\n\tappears when one tries to use a shell with stdin/stdout on\n\t/dev/console.\n\tThis device is special - it cannot be a controlling tty.\n\n\tThe proper solution is to use the correct device instead of\n\t/dev/console.\n\n\tcttyhack provides a \"quick and dirty\" solution to this problem.\n\tIt analyzes stdin with various ioctls, trying to determine whether\n\tit is a /dev/ttyN or /dev/ttySN (virtual terminal or serial line).\n\tOn Linux it also checks sysfs for a pointer to the active console.\n\tIf cttyhack is able to find the real console device, it closes\n\tstdin/out/err and reopens that device.\n\tThen it executes the given program. Opening the device will make\n\tthat device a controlling tty. This may require cttyhack\n\tto be a session leader.\n\n\tExample for /etc/inittab (for busybox init):\n\n\t::respawn:/bin/cttyhack /bin/sh\n\n\tStarting an interactive shell from boot shell script:\n\n\tsetsid cttyhack sh\n\n\tGiving controlling tty to shell running with PID 1:\n\n\t# exec cttyhack sh\n\n\tWithout cttyhack, you need to know exact tty name,\n\tand do something like this:\n\n\t# exec setsid sh -c 'exec sh </dev/tty1 >/dev/tty1 2>&1'\n\n\tStarting getty on a controlling tty from a shell script:\n\n\t# getty 115200 $(cttyhack)\nconfig BUSYBOX_CONFIG_HUSH\n\tbool \"hush (68 kb)\"\n\tdefault BUSYBOX_DEFAULT_HUSH\n\tselect BUSYBOX_CONFIG_SHELL_HUSH\n\thelp\n\thush is a small shell. It handles the normal flow control\n\tconstructs such as if/then/elif/else/fi, for/in/do/done, while loops,\n\tcase/esac. Redirections, here documents, $((arithmetic))\n\tand functions are supported.\n\n\tIt will compile and work on no-mmu systems.\n\n\tIt does not handle select, aliases, tilde expansion,\n\t&>file and >&file redirection of stdout+stderr.\n\nconfig BUSYBOX_CONFIG_SHELL_HUSH\n\tbool \"Internal shell for embedded script support\"\n\tdefault BUSYBOX_DEFAULT_SHELL_HUSH\n\n# hush options\n# It's only needed to get \"nice\" menuconfig indenting.\nif SHELL_HUSH || BUSYBOX_CONFIG_HUSH || BUSYBOX_CONFIG_SH_IS_HUSH || BUSYBOX_CONFIG_BASH_IS_HUSH\n\nconfig BUSYBOX_CONFIG_HUSH_BASH_COMPAT\n\tbool \"bash-compatible extensions\"\n\tdefault BUSYBOX_DEFAULT_HUSH_BASH_COMPAT\n\tdepends on BUSYBOX_CONFIG_SHELL_HUSH\n\nconfig BUSYBOX_CONFIG_HUSH_BRACE_EXPANSION\n\tbool \"Brace expansion\"\n\tdefault BUSYBOX_DEFAULT_HUSH_BRACE_EXPANSION\n\tdepends on BUSYBOX_CONFIG_HUSH_BASH_COMPAT\n\thelp\n\tEnable {abc,def} extension.\n\nconfig BUSYBOX_CONFIG_HUSH_BASH_SOURCE_CURDIR\n\tbool \"'source' and '.' builtins search current directory after $PATH\"\n\tdefault BUSYBOX_DEFAULT_HUSH_BASH_SOURCE_CURDIR   # do not encourage non-standard behavior\n\tdepends on BUSYBOX_CONFIG_HUSH_BASH_COMPAT\n\thelp\n\tThis is not compliant with standards. Avoid if possible.\n\nconfig BUSYBOX_CONFIG_HUSH_LINENO_VAR\n\tbool \"$LINENO variable (bashism)\"\n\tdefault BUSYBOX_DEFAULT_HUSH_LINENO_VAR\n\tdepends on BUSYBOX_CONFIG_SHELL_HUSH\n\nconfig BUSYBOX_CONFIG_HUSH_INTERACTIVE\n\tbool \"Interactive mode\"\n\tdefault BUSYBOX_DEFAULT_HUSH_INTERACTIVE\n\tdepends on BUSYBOX_CONFIG_SHELL_HUSH\n\thelp\n\tEnable interactive mode (prompt and command editing).\n\tWithout this, hush simply reads and executes commands\n\tfrom stdin just like a shell script from a file.\n\tNo prompt, no PS1/PS2 magic shell variables.\n\nconfig BUSYBOX_CONFIG_HUSH_SAVEHISTORY\n\tbool \"Save command history to .hush_history\"\n\tdefault BUSYBOX_DEFAULT_HUSH_SAVEHISTORY\n\tdepends on BUSYBOX_CONFIG_HUSH_INTERACTIVE && BUSYBOX_CONFIG_FEATURE_EDITING_SAVEHISTORY\n\nconfig BUSYBOX_CONFIG_HUSH_JOB\n\tbool \"Job control\"\n\tdefault BUSYBOX_DEFAULT_HUSH_JOB\n\tdepends on BUSYBOX_CONFIG_HUSH_INTERACTIVE\n\thelp\n\tEnable job control: Ctrl-Z backgrounds, Ctrl-C interrupts current\n\tcommand (not entire shell), fg/bg builtins work. Without this option,\n\t\"cmd &\" still works by simply spawning a process and immediately\n\tprompting for next command (or executing next command in a script),\n\tbut no separate process group is formed.\n\nconfig BUSYBOX_CONFIG_HUSH_TICK\n\tbool \"Support command substitution\"\n\tdefault BUSYBOX_DEFAULT_HUSH_TICK\n\tdepends on BUSYBOX_CONFIG_SHELL_HUSH\n\thelp\n\tEnable `command` and $(command).\n\nconfig BUSYBOX_CONFIG_HUSH_IF\n\tbool \"Support if/then/elif/else/fi\"\n\tdefault BUSYBOX_DEFAULT_HUSH_IF\n\tdepends on BUSYBOX_CONFIG_SHELL_HUSH\n\nconfig BUSYBOX_CONFIG_HUSH_LOOPS\n\tbool \"Support for, while and until loops\"\n\tdefault BUSYBOX_DEFAULT_HUSH_LOOPS\n\tdepends on BUSYBOX_CONFIG_SHELL_HUSH\n\nconfig BUSYBOX_CONFIG_HUSH_CASE\n\tbool \"Support case ... esac statement\"\n\tdefault BUSYBOX_DEFAULT_HUSH_CASE\n\tdepends on BUSYBOX_CONFIG_SHELL_HUSH\n\thelp\n\tEnable case ... esac statement. +400 bytes.\n\nconfig BUSYBOX_CONFIG_HUSH_FUNCTIONS\n\tbool \"Support funcname() { commands; } syntax\"\n\tdefault BUSYBOX_DEFAULT_HUSH_FUNCTIONS\n\tdepends on BUSYBOX_CONFIG_SHELL_HUSH\n\thelp\n\tEnable support for shell functions. +800 bytes.\n\nconfig BUSYBOX_CONFIG_HUSH_LOCAL\n\tbool \"local builtin\"\n\tdefault BUSYBOX_DEFAULT_HUSH_LOCAL\n\tdepends on BUSYBOX_CONFIG_HUSH_FUNCTIONS\n\thelp\n\tEnable support for local variables in functions.\n\nconfig BUSYBOX_CONFIG_HUSH_RANDOM_SUPPORT\n\tbool \"Pseudorandom generator and $RANDOM variable\"\n\tdefault BUSYBOX_DEFAULT_HUSH_RANDOM_SUPPORT\n\tdepends on BUSYBOX_CONFIG_SHELL_HUSH\n\thelp\n\tEnable pseudorandom generator and dynamic variable \"$RANDOM\".\n\tEach read of \"$RANDOM\" will generate a new pseudorandom value.\n\nconfig BUSYBOX_CONFIG_HUSH_MODE_X\n\tbool \"Support 'hush -x' option and 'set -x' command\"\n\tdefault BUSYBOX_DEFAULT_HUSH_MODE_X\n\tdepends on BUSYBOX_CONFIG_SHELL_HUSH\n\thelp\n\tThis instructs hush to print commands before execution.\n\tAdds ~300 bytes.\n\nconfig BUSYBOX_CONFIG_HUSH_ECHO\n\tbool \"echo builtin\"\n\tdefault BUSYBOX_DEFAULT_HUSH_ECHO\n\tdepends on BUSYBOX_CONFIG_SHELL_HUSH\n\nconfig BUSYBOX_CONFIG_HUSH_PRINTF\n\tbool \"printf builtin\"\n\tdefault BUSYBOX_DEFAULT_HUSH_PRINTF\n\tdepends on BUSYBOX_CONFIG_SHELL_HUSH\n\nconfig BUSYBOX_CONFIG_HUSH_TEST\n\tbool \"test builtin\"\n\tdefault BUSYBOX_DEFAULT_HUSH_TEST\n\tdepends on BUSYBOX_CONFIG_SHELL_HUSH\n\nconfig BUSYBOX_CONFIG_HUSH_HELP\n\tbool \"help builtin\"\n\tdefault BUSYBOX_DEFAULT_HUSH_HELP\n\tdepends on BUSYBOX_CONFIG_SHELL_HUSH\n\nconfig BUSYBOX_CONFIG_HUSH_EXPORT\n\tbool \"export builtin\"\n\tdefault BUSYBOX_DEFAULT_HUSH_EXPORT\n\tdepends on BUSYBOX_CONFIG_SHELL_HUSH\n\nconfig BUSYBOX_CONFIG_HUSH_EXPORT_N\n\tbool \"Support 'export -n' option\"\n\tdefault BUSYBOX_DEFAULT_HUSH_EXPORT_N\n\tdepends on BUSYBOX_CONFIG_HUSH_EXPORT\n\thelp\n\texport -n unexports variables. It is a bash extension.\n\nconfig BUSYBOX_CONFIG_HUSH_READONLY\n\tbool \"readonly builtin\"\n\tdefault BUSYBOX_DEFAULT_HUSH_READONLY\n\tdepends on BUSYBOX_CONFIG_SHELL_HUSH\n\thelp\n\tEnable support for read-only variables.\n\nconfig BUSYBOX_CONFIG_HUSH_KILL\n\tbool \"kill builtin (supports kill %jobspec)\"\n\tdefault BUSYBOX_DEFAULT_HUSH_KILL\n\tdepends on BUSYBOX_CONFIG_SHELL_HUSH\n\nconfig BUSYBOX_CONFIG_HUSH_WAIT\n\tbool \"wait builtin\"\n\tdefault BUSYBOX_DEFAULT_HUSH_WAIT\n\tdepends on BUSYBOX_CONFIG_SHELL_HUSH\n\nconfig BUSYBOX_CONFIG_HUSH_COMMAND\n\tbool \"command builtin\"\n\tdefault BUSYBOX_DEFAULT_HUSH_COMMAND\n\tdepends on BUSYBOX_CONFIG_SHELL_HUSH\n\nconfig BUSYBOX_CONFIG_HUSH_TRAP\n\tbool \"trap builtin\"\n\tdefault BUSYBOX_DEFAULT_HUSH_TRAP\n\tdepends on BUSYBOX_CONFIG_SHELL_HUSH\n\nconfig BUSYBOX_CONFIG_HUSH_TYPE\n\tbool \"type builtin\"\n\tdefault BUSYBOX_DEFAULT_HUSH_TYPE\n\tdepends on BUSYBOX_CONFIG_SHELL_HUSH\n\nconfig BUSYBOX_CONFIG_HUSH_TIMES\n\tbool \"times builtin\"\n\tdefault BUSYBOX_DEFAULT_HUSH_TIMES\n\tdepends on BUSYBOX_CONFIG_SHELL_HUSH\n\nconfig BUSYBOX_CONFIG_HUSH_READ\n\tbool \"read builtin\"\n\tdefault BUSYBOX_DEFAULT_HUSH_READ\n\tdepends on BUSYBOX_CONFIG_SHELL_HUSH\n\nconfig BUSYBOX_CONFIG_HUSH_SET\n\tbool \"set builtin\"\n\tdefault BUSYBOX_DEFAULT_HUSH_SET\n\tdepends on BUSYBOX_CONFIG_SHELL_HUSH\n\nconfig BUSYBOX_CONFIG_HUSH_UNSET\n\tbool \"unset builtin\"\n\tdefault BUSYBOX_DEFAULT_HUSH_UNSET\n\tdepends on BUSYBOX_CONFIG_SHELL_HUSH\n\nconfig BUSYBOX_CONFIG_HUSH_ULIMIT\n\tbool \"ulimit builtin\"\n\tdefault BUSYBOX_DEFAULT_HUSH_ULIMIT\n\tdepends on BUSYBOX_CONFIG_SHELL_HUSH\n\nconfig BUSYBOX_CONFIG_HUSH_UMASK\n\tbool \"umask builtin\"\n\tdefault BUSYBOX_DEFAULT_HUSH_UMASK\n\tdepends on BUSYBOX_CONFIG_SHELL_HUSH\n\nconfig BUSYBOX_CONFIG_HUSH_GETOPTS\n\tbool \"getopts builtin\"\n\tdefault BUSYBOX_DEFAULT_HUSH_GETOPTS\n\tdepends on BUSYBOX_CONFIG_SHELL_HUSH\n\nconfig BUSYBOX_CONFIG_HUSH_MEMLEAK\n\tbool \"memleak builtin (debugging)\"\n\tdefault BUSYBOX_DEFAULT_HUSH_MEMLEAK\n\tdepends on BUSYBOX_CONFIG_SHELL_HUSH\n\nendif # hush options\n\n\ncomment \"Options common to all shells\"\nif BUSYBOX_CONFIG_SHELL_ASH || BUSYBOX_CONFIG_SHELL_HUSH\n\nconfig BUSYBOX_CONFIG_FEATURE_SH_MATH\n\tbool \"POSIX math support\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_SH_MATH\n\tdepends on BUSYBOX_CONFIG_SHELL_ASH || BUSYBOX_CONFIG_SHELL_HUSH\n\thelp\n\tEnable math support in the shell via $((...)) syntax.\n\nconfig BUSYBOX_CONFIG_FEATURE_SH_MATH_64\n\tbool \"Extend POSIX math support to 64 bit\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_SH_MATH_64\n\tdepends on BUSYBOX_CONFIG_FEATURE_SH_MATH\n\thelp\n\tEnable 64-bit math support in the shell. This will make the shell\n\tslightly larger, but will allow computation with very large numbers.\n\tThis is not in POSIX, so do not rely on this in portable code.\n\nconfig BUSYBOX_CONFIG_FEATURE_SH_MATH_BASE\n\tbool \"Support BASE#nnnn literals\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_SH_MATH_BASE\n\tdepends on BUSYBOX_CONFIG_FEATURE_SH_MATH\n\nconfig BUSYBOX_CONFIG_FEATURE_SH_EXTRA_QUIET\n\tbool \"Hide message on interactive shell startup\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_SH_EXTRA_QUIET\n\tdepends on BUSYBOX_CONFIG_SHELL_ASH || BUSYBOX_CONFIG_SHELL_HUSH\n\thelp\n\tRemove the busybox introduction when starting a shell.\n\nconfig BUSYBOX_CONFIG_FEATURE_SH_STANDALONE\n\tbool \"Standalone shell\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_SH_STANDALONE\n\tdepends on BUSYBOX_CONFIG_SHELL_ASH || BUSYBOX_CONFIG_SHELL_HUSH\n\thelp\n\tThis option causes busybox shells to use busybox applets\n\tin preference to executables in the PATH whenever possible. For\n\texample, entering the command 'ifconfig' into the shell would cause\n\tbusybox to use the ifconfig busybox applet. Specifying the fully\n\tqualified executable name, such as '/sbin/ifconfig' will still\n\texecute the /sbin/ifconfig executable on the filesystem. This option\n\tis generally used when creating a statically linked version of busybox\n\tfor use as a rescue shell, in the event that you screw up your system.\n\n\tThis is implemented by re-execing /proc/self/exe (typically)\n\twith right parameters.\n\n\tHowever, there are drawbacks: it is problematic in chroot jails\n\twithout mounted /proc, and ps/top may show command name as 'exe'\n\tfor applets started this way.\n\nconfig BUSYBOX_CONFIG_FEATURE_SH_NOFORK\n\tbool \"Run 'nofork' applets directly\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_SH_NOFORK\n\tdepends on BUSYBOX_CONFIG_SHELL_ASH || BUSYBOX_CONFIG_SHELL_HUSH\n\thelp\n\tThis option causes busybox shells to not execute typical\n\tfork/exec/wait sequence, but call <applet>_main directly,\n\tif possible. (Sometimes it is not possible: for example,\n\tthis is not possible in pipes).\n\n\tThis will be done only for some applets (those which are marked\n\tNOFORK in include/applets.h).\n\n\tThis may significantly speed up some shell scripts.\n\n\tThis feature is relatively new. Use with care. Report bugs\n\tto project mailing list.\n\nconfig BUSYBOX_CONFIG_FEATURE_SH_READ_FRAC\n\tbool \"read -t N.NNN support (+110 bytes)\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_SH_READ_FRAC\n\tdepends on BUSYBOX_CONFIG_SHELL_ASH || BUSYBOX_CONFIG_SHELL_HUSH\n\thelp\n\tEnable support for fractional second timeout in read builtin.\n\nconfig BUSYBOX_CONFIG_FEATURE_SH_HISTFILESIZE\n\tbool \"Use $HISTFILESIZE\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_SH_HISTFILESIZE\n\tdepends on BUSYBOX_CONFIG_SHELL_ASH || BUSYBOX_CONFIG_SHELL_HUSH\n\thelp\n\tThis option makes busybox shells to use $HISTFILESIZE variable\n\tto set shell history size. Note that its max value is capped\n\tby \"History size\" setting in library tuning section.\n\nconfig BUSYBOX_CONFIG_FEATURE_SH_EMBEDDED_SCRIPTS\n\tbool \"Embed scripts in the binary\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_SH_EMBEDDED_SCRIPTS\n\tdepends on BUSYBOX_CONFIG_SHELL_ASH || BUSYBOX_CONFIG_SHELL_HUSH\n\thelp\n\tAllow scripts to be compressed and embedded in the busybox\n\tbinary. The scripts should be placed in the 'embed' directory\n\tat build time. Like applets, scripts can be run as\n\t'busybox SCRIPT ...' or by linking their name to the binary.\n\n\tThis also allows applets to be implemented as scripts: place\n\tthe script in 'applets_sh' and a stub C file containing\n\tconfiguration in the appropriate subsystem directory.\n\nendif # Options common to all shells\n\nendmenu\n"
  },
  {
    "path": "package/utils/busybox/config/sysklogd/Config.in",
    "content": "# DO NOT EDIT. This file is generated from Config.src\n#\n# For a description of the syntax of this configuration file,\n# see docs/Kconfig-language.txt.\n#\n\nmenu \"System Logging Utilities\"\n\nconfig BUSYBOX_CONFIG_KLOGD\n\tbool \"klogd (5.7 kb)\"\n\tdefault BUSYBOX_DEFAULT_KLOGD\n\thelp\n\tklogd is a utility which intercepts and logs all\n\tmessages from the Linux kernel and sends the messages\n\tout to the 'syslogd' utility so they can be logged. If\n\tyou wish to record the messages produced by the kernel,\n\tyou should enable this option.\n\ncomment \"klogd should not be used together with syslog to kernel printk buffer\"\n\tdepends on BUSYBOX_CONFIG_KLOGD && BUSYBOX_CONFIG_FEATURE_KMSG_SYSLOG\n\nconfig BUSYBOX_CONFIG_FEATURE_KLOGD_KLOGCTL\n\tbool \"Use the klogctl() interface\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_KLOGD_KLOGCTL\n\tdepends on BUSYBOX_CONFIG_KLOGD\n\thelp\n\tThe klogd applet supports two interfaces for reading\n\tkernel messages. Linux provides the klogctl() interface\n\twhich allows reading messages from the kernel ring buffer\n\tindependently from the file system.\n\n\tIf you answer 'N' here, klogd will use the more portable\n\tapproach of reading them from /proc or a device node.\n\tHowever, this method requires the file to be available.\n\n\tIf in doubt, say 'Y'.\nconfig BUSYBOX_CONFIG_LOGGER\n\tbool \"logger (6.3 kb)\"\n\tdefault BUSYBOX_DEFAULT_LOGGER\n\tselect BUSYBOX_CONFIG_FEATURE_SYSLOG\n\thelp\n\tThe logger utility allows you to send arbitrary text\n\tmessages to the system log (i.e. the 'syslogd' utility) so\n\tthey can be logged. This is generally used to help locate\n\tproblems that occur within programs and scripts.\nconfig BUSYBOX_CONFIG_LOGREAD\n\tbool \"logread (4.8 kb)\"\n\tdefault BUSYBOX_DEFAULT_LOGREAD\n\thelp\n\tIf you enabled Circular Buffer support, you almost\n\tcertainly want to enable this feature as well. This\n\tutility will allow you to read the messages that are\n\tstored in the syslogd circular buffer.\n\nconfig BUSYBOX_CONFIG_FEATURE_LOGREAD_REDUCED_LOCKING\n\tbool \"Double buffering\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_LOGREAD_REDUCED_LOCKING\n\tdepends on BUSYBOX_CONFIG_LOGREAD\n\thelp\n\t'logread' output to slow serial terminals can have\n\tside effects on syslog because of the semaphore.\n\tThis option make logread to double buffer copy\n\tfrom circular buffer, minimizing semaphore\n\tcontention at some minor memory expense.\n\nconfig BUSYBOX_CONFIG_SYSLOGD\n\tbool \"syslogd (13 kb)\"\n\tdefault BUSYBOX_DEFAULT_SYSLOGD\n\thelp\n\tThe syslogd utility is used to record logs of all the\n\tsignificant events that occur on a system. Every\n\tmessage that is logged records the date and time of the\n\tevent, and will generally also record the name of the\n\tapplication that generated the message. When used in\n\tconjunction with klogd, messages from the Linux kernel\n\tcan also be recorded. This is terribly useful,\n\tespecially for finding what happened when something goes\n\twrong. And something almost always will go wrong if\n\tyou wait long enough....\n\nconfig BUSYBOX_CONFIG_FEATURE_ROTATE_LOGFILE\n\tbool \"Rotate message files\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_ROTATE_LOGFILE\n\tdepends on BUSYBOX_CONFIG_SYSLOGD\n\thelp\n\tThis enables syslogd to rotate the message files\n\ton his own. No need to use an external rotate script.\n\nconfig BUSYBOX_CONFIG_FEATURE_REMOTE_LOG\n\tbool \"Remote Log support\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_REMOTE_LOG\n\tdepends on BUSYBOX_CONFIG_SYSLOGD\n\thelp\n\tWhen you enable this feature, the syslogd utility can\n\tbe used to send system log messages to another system\n\tconnected via a network. This allows the remote\n\tmachine to log all the system messages, which can be\n\tterribly useful for reducing the number of serial\n\tcables you use. It can also be a very good security\n\tmeasure to prevent system logs from being tampered with\n\tby an intruder.\n\nconfig BUSYBOX_CONFIG_FEATURE_SYSLOGD_DUP\n\tbool \"Support -D (drop dups) option\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_SYSLOGD_DUP\n\tdepends on BUSYBOX_CONFIG_SYSLOGD\n\thelp\n\tOption -D instructs syslogd to drop consecutive messages\n\twhich are totally the same.\n\nconfig BUSYBOX_CONFIG_FEATURE_SYSLOGD_CFG\n\tbool \"Support syslog.conf\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_SYSLOGD_CFG\n\tdepends on BUSYBOX_CONFIG_SYSLOGD\n\thelp\n\tSupports restricted syslogd config. See docs/syslog.conf.txt\n\nconfig BUSYBOX_CONFIG_FEATURE_SYSLOGD_PRECISE_TIMESTAMPS\n\tbool \"Include milliseconds in timestamps\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_SYSLOGD_PRECISE_TIMESTAMPS\n\tdepends on BUSYBOX_CONFIG_SYSLOGD\n\thelp\n\tIncludes milliseconds (HH:MM:SS.mmm) in timestamp when\n\ttimestamps are added.\n\nconfig BUSYBOX_CONFIG_FEATURE_SYSLOGD_READ_BUFFER_SIZE\n\tint \"Read buffer size in bytes\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_SYSLOGD_READ_BUFFER_SIZE\n\trange 256 20000\n\tdepends on BUSYBOX_CONFIG_SYSLOGD\n\thelp\n\tThis option sets the size of the syslog read buffer.\n\tActual memory usage increases around five times the\n\tchange done here.\n\nconfig BUSYBOX_CONFIG_FEATURE_IPC_SYSLOG\n\tbool \"Circular Buffer support\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_IPC_SYSLOG\n\tdepends on BUSYBOX_CONFIG_SYSLOGD\n\thelp\n\tWhen you enable this feature, the syslogd utility will\n\tuse a circular buffer to record system log messages.\n\tWhen the buffer is filled it will continue to overwrite\n\tthe oldest messages. This can be very useful for\n\tsystems with little or no permanent storage, since\n\totherwise system logs can eventually fill up your\n\tentire filesystem, which may cause your system to\n\tbreak badly.\n\nconfig BUSYBOX_CONFIG_FEATURE_IPC_SYSLOG_BUFFER_SIZE\n\tint \"Circular buffer size in Kbytes (minimum 4KB)\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_IPC_SYSLOG_BUFFER_SIZE\n\trange 4 2147483647\n\tdepends on BUSYBOX_CONFIG_FEATURE_IPC_SYSLOG\n\thelp\n\tThis option sets the size of the circular buffer\n\tused to record system log messages.\n\nconfig BUSYBOX_CONFIG_FEATURE_KMSG_SYSLOG\n\tbool \"Linux kernel printk buffer support\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_KMSG_SYSLOG\n\tdepends on BUSYBOX_CONFIG_SYSLOGD\n\thelp\n\tWhen you enable this feature, the syslogd utility will\n\twrite system log message to the Linux kernel's printk buffer.\n\tThis can be used as a smaller alternative to the syslogd IPC\n\tsupport, as klogd and logread aren't needed.\n\n\tNOTICE: Syslog facilities in log entries needs kernel 3.5+.\n\nendmenu\n"
  },
  {
    "path": "package/utils/busybox/config/util-linux/Config.in",
    "content": "# DO NOT EDIT. This file is generated from Config.src\n#\n# For a description of the syntax of this configuration file,\n# see docs/Kconfig-language.txt.\n#\n\nmenu \"Linux System Utilities\"\n\nconfig BUSYBOX_CONFIG_ACPID\n\tbool \"acpid (9 kb)\"\n\tdefault BUSYBOX_DEFAULT_ACPID\n\thelp\n\tacpid listens to ACPI events coming either in textual form from\n\t/proc/acpi/event (though it is marked deprecated it is still widely\n\tused and _is_ a standard) or in binary form from specified evdevs\n\t(just use /dev/input/event*).\n\n\tIt parses the event to retrieve ACTION and a possible PARAMETER.\n\tIt then spawns /etc/acpi/<ACTION>[/<PARAMETER>] either via run-parts\n\t(if the resulting path is a directory) or directly as an executable.\n\n\tN.B. acpid relies on run-parts so have the latter installed.\n\nconfig BUSYBOX_CONFIG_FEATURE_ACPID_COMPAT\n\tbool \"Accept and ignore redundant options\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_ACPID_COMPAT\n\tdepends on BUSYBOX_CONFIG_ACPID\n\thelp\n\tAccept and ignore compatibility options -g -m -s -S -v.\nconfig BUSYBOX_CONFIG_BLKDISCARD\n\tbool \"blkdiscard (4.3 kb)\"\n\tdefault BUSYBOX_DEFAULT_BLKDISCARD\n\thelp\n\tblkdiscard discards sectors on a given device.\nconfig BUSYBOX_CONFIG_BLKID\n\tbool \"blkid (12 kb)\"\n\tdefault BUSYBOX_DEFAULT_BLKID\n\tselect BUSYBOX_CONFIG_VOLUMEID\n\thelp\n\tLists labels and UUIDs of all filesystems.\n\nconfig BUSYBOX_CONFIG_FEATURE_BLKID_TYPE\n\tbool \"Print filesystem type\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_BLKID_TYPE\n\tdepends on BUSYBOX_CONFIG_BLKID\n\thelp\n\tShow TYPE=\"filesystem type\"\nconfig BUSYBOX_CONFIG_BLOCKDEV\n\tbool \"blockdev (2.3 kb)\"\n\tdefault BUSYBOX_DEFAULT_BLOCKDEV\n\thelp\n\tPerforms some ioctls with block devices.\nconfig BUSYBOX_CONFIG_CAL\n\tbool \"cal (5.8 kb)\"\n\tdefault BUSYBOX_DEFAULT_CAL\n\thelp\n\tcal is used to display a monthly calendar.\nconfig BUSYBOX_CONFIG_CHRT\n\tbool \"chrt (4.7 kb)\"\n\tdefault BUSYBOX_DEFAULT_CHRT\n\thelp\n\tManipulate real-time attributes of a process.\n\tThis requires sched_{g,s}etparam support in your libc.\nconfig BUSYBOX_CONFIG_DMESG\n\tbool \"dmesg (3.7 kb)\"\n\tdefault BUSYBOX_DEFAULT_DMESG\n\thelp\n\tdmesg is used to examine or control the kernel ring buffer. When the\n\tLinux kernel prints messages to the system log, they are stored in\n\tthe kernel ring buffer. You can use dmesg to print the kernel's ring\n\tbuffer, clear the kernel ring buffer, change the size of the kernel\n\tring buffer, and change the priority level at which kernel messages\n\tare also logged to the system console. Enable this option if you\n\twish to enable the 'dmesg' utility.\n\nconfig BUSYBOX_CONFIG_FEATURE_DMESG_PRETTY\n\tbool \"Pretty output\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_DMESG_PRETTY\n\tdepends on BUSYBOX_CONFIG_DMESG\n\thelp\n\tIf you wish to scrub the syslog level from the output, say 'Y' here.\n\tThe syslog level is a string prefixed to every line with the form\n\t\"<#>\".\n\n\tWith this option you will see:\n\t\t# dmesg\n\t\tLinux version 2.6.17.4 .....\n\t\tBIOS-provided physical RAM map:\n\t\t BIOS-e820: 0000000000000000 - 000000000009f000 (usable)\n\n\tWithout this option you will see:\n\t\t# dmesg\n\t\t<5>Linux version 2.6.17.4 .....\n\t\t<6>BIOS-provided physical RAM map:\n\t\t<6> BIOS-e820: 0000000000000000 - 000000000009f000 (usable)\nconfig BUSYBOX_CONFIG_EJECT\n\tbool \"eject (4 kb)\"\n\tdefault BUSYBOX_DEFAULT_EJECT\n\thelp\n\tUsed to eject cdroms. (defaults to /dev/cdrom)\n\nconfig BUSYBOX_CONFIG_FEATURE_EJECT_SCSI\n\tbool \"SCSI support\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_EJECT_SCSI\n\tdepends on BUSYBOX_CONFIG_EJECT\n\thelp\n\tAdd the -s option to eject, this allows to eject SCSI-Devices and\n\tusb-storage devices.\nconfig BUSYBOX_CONFIG_FALLOCATE\n\tbool \"fallocate (4.1 kb)\"\n\tdefault BUSYBOX_DEFAULT_FALLOCATE\n\thelp\n\tPreallocate space for files.\nconfig BUSYBOX_CONFIG_FATATTR\n\tbool \"fatattr (1.9 kb)\"\n\tdefault BUSYBOX_DEFAULT_FATATTR\n\thelp\n\tfatattr lists or changes the file attributes on a fat file system.\nconfig BUSYBOX_CONFIG_FBSET\n\tbool \"fbset (5.9 kb)\"\n\tdefault BUSYBOX_DEFAULT_FBSET\n\thelp\n\tfbset is used to show or change the settings of a Linux frame buffer\n\tdevice. The frame buffer device provides a simple and unique\n\tinterface to access a graphics display. Enable this option\n\tif you wish to enable the 'fbset' utility.\n\nconfig BUSYBOX_CONFIG_FEATURE_FBSET_FANCY\n\tbool \"Enable extra options\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_FBSET_FANCY\n\tdepends on BUSYBOX_CONFIG_FBSET\n\thelp\n\tThis option enables extended fbset options, allowing one to set the\n\tframebuffer size, color depth, etc. interface to access a graphics\n\tdisplay. Enable this option if you wish to enable extended fbset\n\toptions.\n\nconfig BUSYBOX_CONFIG_FEATURE_FBSET_READMODE\n\tbool \"Enable readmode support\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_FBSET_READMODE\n\tdepends on BUSYBOX_CONFIG_FBSET\n\thelp\n\tThis option allows fbset to read the video mode database stored by\n\tdefault BUSYBOX_DEFAULT_FEATURE_FBSET_READMODE /etc/fb.modes, which can be used to set frame buffer\n\tdevice to pre-defined video modes.\nconfig BUSYBOX_CONFIG_FDFORMAT\n\tbool \"fdformat (4.4 kb)\"\n\tdefault BUSYBOX_DEFAULT_FDFORMAT\n\thelp\n\tfdformat is used to low-level format a floppy disk.\nconfig BUSYBOX_CONFIG_FDISK\n\tbool \"fdisk (37 kb)\"\n\tdefault BUSYBOX_DEFAULT_FDISK\n\thelp\n\tThe fdisk utility is used to divide hard disks into one or more\n\tlogical disks, which are generally called partitions. This utility\n\tcan be used to list and edit the set of partitions or BSD style\n\t'disk slices' that are defined on a hard drive.\n\nconfig BUSYBOX_CONFIG_FDISK_SUPPORT_LARGE_DISKS\n\tbool \"Support over 4GB disks\"\n\tdefault BUSYBOX_DEFAULT_FDISK_SUPPORT_LARGE_DISKS\n\tdepends on BUSYBOX_CONFIG_FDISK\n\tdepends on !BUSYBOX_CONFIG_LFS   # with LFS no special code is needed\n\nconfig BUSYBOX_CONFIG_FEATURE_FDISK_WRITABLE\n\tbool \"Write support\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_FDISK_WRITABLE\n\tdepends on BUSYBOX_CONFIG_FDISK\n\thelp\n\tEnabling this option allows you to create or change a partition table\n\tand write those changes out to disk. If you leave this option\n\tdisabled, you will only be able to view the partition table.\n\nconfig BUSYBOX_CONFIG_FEATURE_AIX_LABEL\n\tbool \"Support AIX disklabels\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_AIX_LABEL\n\tdepends on BUSYBOX_CONFIG_FDISK && BUSYBOX_CONFIG_FEATURE_FDISK_WRITABLE\n\thelp\n\tEnabling this option allows you to create or change AIX disklabels.\n\tMost people can safely leave this option disabled.\n\nconfig BUSYBOX_CONFIG_FEATURE_SGI_LABEL\n\tbool \"Support SGI disklabels\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_SGI_LABEL\n\tdepends on BUSYBOX_CONFIG_FDISK && BUSYBOX_CONFIG_FEATURE_FDISK_WRITABLE\n\thelp\n\tEnabling this option allows you to create or change SGI disklabels.\n\tMost people can safely leave this option disabled.\n\nconfig BUSYBOX_CONFIG_FEATURE_SUN_LABEL\n\tbool \"Support SUN disklabels\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_SUN_LABEL\n\tdepends on BUSYBOX_CONFIG_FDISK && BUSYBOX_CONFIG_FEATURE_FDISK_WRITABLE\n\thelp\n\tEnabling this option allows you to create or change SUN disklabels.\n\tMost people can safely leave this option disabled.\n\nconfig BUSYBOX_CONFIG_FEATURE_OSF_LABEL\n\tbool \"Support BSD disklabels\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_OSF_LABEL\n\tdepends on BUSYBOX_CONFIG_FDISK && BUSYBOX_CONFIG_FEATURE_FDISK_WRITABLE\n\thelp\n\tEnabling this option allows you to create or change BSD disklabels\n\tand define and edit BSD disk slices.\n\nconfig BUSYBOX_CONFIG_FEATURE_GPT_LABEL\n\tbool \"Support GPT disklabels\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_GPT_LABEL\n\tdepends on BUSYBOX_CONFIG_FDISK && BUSYBOX_CONFIG_FEATURE_FDISK_WRITABLE\n\thelp\n\tEnabling this option allows you to view GUID Partition Table\n\tdisklabels.\n\nconfig BUSYBOX_CONFIG_FEATURE_FDISK_ADVANCED\n\tbool \"Support expert mode\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_FDISK_ADVANCED\n\tdepends on BUSYBOX_CONFIG_FDISK && BUSYBOX_CONFIG_FEATURE_FDISK_WRITABLE\n\thelp\n\tEnabling this option allows you to do terribly unsafe things like\n\tdefine arbitrary drive geometry, move the beginning of data in a\n\tpartition, and similarly evil things. Unless you have a very good\n\treason you would be wise to leave this disabled.\nconfig BUSYBOX_CONFIG_FINDFS\n\tbool \"findfs (12 kb)\"\n\tdefault BUSYBOX_DEFAULT_FINDFS\n\tselect BUSYBOX_CONFIG_VOLUMEID\n\thelp\n\tPrints the name of a filesystem with given label or UUID.\nconfig BUSYBOX_CONFIG_FLOCK\n\tbool \"flock (6.3 kb)\"\n\tdefault BUSYBOX_DEFAULT_FLOCK\n\thelp\n\tManage locks from shell scripts\nconfig BUSYBOX_CONFIG_FDFLUSH\n\tbool \"fdflush (1.3 kb)\"\n\tdefault BUSYBOX_DEFAULT_FDFLUSH\n\thelp\n\tfdflush is only needed when changing media on slightly-broken\n\tremovable media drives. It is used to make Linux believe that a\n\thardware disk-change switch has been actuated, which causes Linux to\n\tforget anything it has cached from the previous media. If you have\n\tsuch a slightly-broken drive, you will need to run fdflush every time\n\tyou change a disk. Most people have working hardware and can safely\n\tleave this disabled.\n\nconfig BUSYBOX_CONFIG_FREERAMDISK\n\tbool \"freeramdisk (1.3 kb)\"\n\tdefault BUSYBOX_DEFAULT_FREERAMDISK\n\thelp\n\tLinux allows you to create ramdisks. This utility allows you to\n\tdelete them and completely free all memory that was used for the\n\tramdisk. For example, if you boot Linux into a ramdisk and later\n\tpivot_root, you may want to free the memory that is allocated to the\n\tramdisk. If you have no use for freeing memory from a ramdisk, leave\n\tthis disabled.\nconfig BUSYBOX_CONFIG_FSCK_MINIX\n\tbool \"fsck.minix (13 kb)\"\n\tdefault BUSYBOX_DEFAULT_FSCK_MINIX\n\thelp\n\tThe minix filesystem is a nice, small, compact, read-write filesystem\n\twith little overhead. It is not a journaling filesystem however and\n\tcan experience corruption if it is not properly unmounted or if the\n\tpower goes off in the middle of a write. This utility allows you to\n\tcheck for and attempt to repair any corruption that occurs to a minix\n\tfilesystem.\nconfig BUSYBOX_CONFIG_FSFREEZE\n\tbool \"fsfreeze (3.5 kb)\"\n\tdefault BUSYBOX_DEFAULT_FSFREEZE\n\tselect BUSYBOX_CONFIG_LONG_OPTS\n\thelp\n\tHalt new accesses and flush writes on a mounted filesystem.\nconfig BUSYBOX_CONFIG_FSTRIM\n\tbool \"fstrim (4.4 kb)\"\n\tdefault BUSYBOX_DEFAULT_FSTRIM\n\thelp\n\tDiscard unused blocks on a mounted filesystem.\nconfig BUSYBOX_CONFIG_GETOPT\n\tbool \"getopt (5.8 kb)\"\n\tdefault BUSYBOX_DEFAULT_GETOPT\n\thelp\n\tThe getopt utility is used to break up (parse) options in command\n\tlines to make it easy to write complex shell scripts that also check\n\tfor legal (and illegal) options. If you want to write horribly\n\tcomplex shell scripts, or use some horribly complex shell script\n\twritten by others, this utility may be for you. Most people will\n\twisely leave this disabled.\n\nconfig BUSYBOX_CONFIG_FEATURE_GETOPT_LONG\n\tbool \"Support -l LONGOPTs\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_GETOPT_LONG\n\tdepends on BUSYBOX_CONFIG_GETOPT && BUSYBOX_CONFIG_LONG_OPTS\n\thelp\n\tEnable support for long options (option -l).\nconfig BUSYBOX_CONFIG_HEXDUMP\n\tbool \"hexdump (8.6 kb)\"\n\tdefault BUSYBOX_DEFAULT_HEXDUMP\n\thelp\n\tThe hexdump utility is used to display binary data in a readable\n\tway that is comparable to the output from most hex editors.\n\nconfig BUSYBOX_CONFIG_HD\n\tbool \"hd (7.8 kb)\"\n\tdefault BUSYBOX_DEFAULT_HD\n\thelp\n\thd is an alias to hexdump -C.\nconfig BUSYBOX_CONFIG_XXD\n\tbool \"xxd (8.9 kb)\"\n\tdefault BUSYBOX_DEFAULT_XXD\n\thelp\n\tThe xxd utility is used to display binary data in a readable\n\tway that is comparable to the output from most hex editors.\nconfig BUSYBOX_CONFIG_HWCLOCK\n\tbool \"hwclock (5.8 kb)\"\n\tdefault BUSYBOX_DEFAULT_HWCLOCK\n\thelp\n\tThe hwclock utility is used to read and set the hardware clock\n\ton a system. This is primarily used to set the current time on\n\tshutdown in the hardware clock, so the hardware will keep the\n\tcorrect time when Linux is _not_ running.\n\nconfig BUSYBOX_CONFIG_FEATURE_HWCLOCK_ADJTIME_FHS\n\tbool \"Use FHS /var/lib/hwclock/adjtime\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_HWCLOCK_ADJTIME_FHS  # util-linux-ng in Fedora 13 still uses /etc/adjtime\n\tdepends on BUSYBOX_CONFIG_HWCLOCK\n\thelp\n\tStarting with FHS 2.3, the adjtime state file is supposed to exist\n\tat /var/lib/hwclock/adjtime instead of /etc/adjtime. If you wish\n\tto use the FHS behavior, answer Y here, otherwise answer N for the\n\tclassic /etc/adjtime path.\n\n\tpathname.com/fhs/pub/fhs-2.3.html#VARLIBHWCLOCKSTATEDIRECTORYFORHWCLO\nconfig BUSYBOX_CONFIG_IONICE\n\tbool \"ionice (3.8 kb)\"\n\tdefault BUSYBOX_DEFAULT_IONICE\n\thelp\n\tSet/set program io scheduling class and priority\n\tRequires kernel >= 2.6.13\nconfig BUSYBOX_CONFIG_IPCRM\n\tbool \"ipcrm (3.2 kb)\"\n\tdefault BUSYBOX_DEFAULT_IPCRM\n\thelp\n\tThe ipcrm utility allows the removal of System V interprocess\n\tcommunication (IPC) objects and the associated data structures\n\tfrom the system.\nconfig BUSYBOX_CONFIG_IPCS\n\tbool \"ipcs (11 kb)\"\n\tdefault BUSYBOX_DEFAULT_IPCS\n\thelp\n\tThe ipcs utility is used to provide information on the currently\n\tallocated System V interprocess (IPC) objects in the system.\nconfig BUSYBOX_CONFIG_LAST\n\tbool \"last (6.1 kb)\"\n\tdefault BUSYBOX_DEFAULT_LAST\n\tdepends on BUSYBOX_CONFIG_FEATURE_WTMP\n\thelp\n\t'last' displays a list of the last users that logged into the system.\n\nconfig BUSYBOX_CONFIG_FEATURE_LAST_FANCY\n\tbool \"Output extra information\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_LAST_FANCY\n\tdepends on BUSYBOX_CONFIG_LAST\n\thelp\n\t'last' displays detailed information about the last users that\n\tlogged into the system (mimics sysvinit last). +900 bytes.\nconfig BUSYBOX_CONFIG_LOSETUP\n\tbool \"losetup (5.5 kb)\"\n\tdefault BUSYBOX_DEFAULT_LOSETUP\n\thelp\n\tlosetup is used to associate or detach a loop device with a regular\n\tfile or block device, and to query the status of a loop device. This\n\tversion does not currently support enabling data encryption.\nconfig BUSYBOX_CONFIG_LSPCI\n\tbool \"lspci (6.3 kb)\"\n\tdefault BUSYBOX_DEFAULT_LSPCI\n\thelp\n\tlspci is a utility for displaying information about PCI buses in the\n\tsystem and devices connected to them.\n\n\tThis version uses sysfs (/sys/bus/pci/devices) only.\nconfig BUSYBOX_CONFIG_LSUSB\n\tbool \"lsusb (4.2 kb)\"\n\tdefault BUSYBOX_DEFAULT_LSUSB\n\thelp\n\tlsusb is a utility for displaying information about USB buses in the\n\tsystem and devices connected to them.\n\n\tThis version uses sysfs (/sys/bus/usb/devices) only.\nconfig BUSYBOX_CONFIG_MDEV\n\tbool \"mdev (17 kb)\"\n\tdefault BUSYBOX_DEFAULT_MDEV\n\thelp\n\tmdev is a mini-udev implementation for dynamically creating device\n\tnodes in the /dev directory.\n\n\tFor more information, please see docs/mdev.txt\n\nconfig BUSYBOX_CONFIG_FEATURE_MDEV_CONF\n\tbool \"Support /etc/mdev.conf\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_MDEV_CONF\n\tdepends on BUSYBOX_CONFIG_MDEV\n\thelp\n\tAdd support for the mdev config file to control ownership and\n\tpermissions of the device nodes.\n\n\tFor more information, please see docs/mdev.txt\n\nconfig BUSYBOX_CONFIG_FEATURE_MDEV_RENAME\n\tbool \"Support subdirs/symlinks\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_MDEV_RENAME\n\tdepends on BUSYBOX_CONFIG_FEATURE_MDEV_CONF\n\thelp\n\tAdd support for renaming devices and creating symlinks.\n\n\tFor more information, please see docs/mdev.txt\n\nconfig BUSYBOX_CONFIG_FEATURE_MDEV_RENAME_REGEXP\n\tbool \"Support regular expressions substitutions when renaming device\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_MDEV_RENAME_REGEXP\n\tdepends on BUSYBOX_CONFIG_FEATURE_MDEV_RENAME\n\thelp\n\tAdd support for regular expressions substitutions when renaming\n\tdevice.\n\nconfig BUSYBOX_CONFIG_FEATURE_MDEV_EXEC\n\tbool \"Support command execution at device addition/removal\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_MDEV_EXEC\n\tdepends on BUSYBOX_CONFIG_FEATURE_MDEV_CONF\n\thelp\n\tThis adds support for an optional field to /etc/mdev.conf for\n\texecuting commands when devices are created/removed.\n\n\tFor more information, please see docs/mdev.txt\n\nconfig BUSYBOX_CONFIG_FEATURE_MDEV_LOAD_FIRMWARE\n\tbool \"Support loading of firmware\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_MDEV_LOAD_FIRMWARE\n\tdepends on BUSYBOX_CONFIG_MDEV\n\thelp\n\tSome devices need to load firmware before they can be usable.\n\n\tThese devices will request userspace look up the files in\n\t/lib/firmware/ and if it exists, send it to the kernel for\n\tloading into the hardware.\n\nconfig BUSYBOX_CONFIG_FEATURE_MDEV_DAEMON\n\tbool \"Support daemon mode\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_MDEV_DAEMON\n\tdepends on BUSYBOX_CONFIG_MDEV\n\thelp\n\tAdds the -d option to run mdev in daemon mode handling hotplug\n\tevents from the kernel like udev. If the system generates many\n\thotplug events this mode of operation will consume less\n\tresources than registering mdev as hotplug helper or using the\n\tuevent applet.\nconfig BUSYBOX_CONFIG_MESG\n\tbool \"mesg (1.4 kb)\"\n\tdefault BUSYBOX_DEFAULT_MESG\n\thelp\n\tMesg controls access to your terminal by others. It is typically\n\tused to allow or disallow other users to write to your terminal\n\nconfig BUSYBOX_CONFIG_FEATURE_MESG_ENABLE_ONLY_GROUP\n\tbool \"Enable writing to tty only by group, not by everybody\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_MESG_ENABLE_ONLY_GROUP\n\tdepends on BUSYBOX_CONFIG_MESG\n\thelp\n\tUsually, ttys are owned by group \"tty\", and \"write\" tool is\n\tsetgid to this group. This way, \"mesg y\" only needs to enable\n\t\"write by owning group\" bit in tty mode.\n\n\tIf you set this option to N, \"mesg y\" will enable writing\n\tby anybody at all. This is not recommended.\nconfig BUSYBOX_CONFIG_MKE2FS\n\tbool \"mke2fs (10 kb)\"\n\tdefault BUSYBOX_DEFAULT_MKE2FS\n\thelp\n\tUtility to create EXT2 filesystems.\n\nconfig BUSYBOX_CONFIG_MKFS_EXT2\n\tbool \"mkfs.ext2 (10 kb)\"\n\tdefault BUSYBOX_DEFAULT_MKFS_EXT2\n\thelp\n\tAlias to \"mke2fs\".\nconfig BUSYBOX_CONFIG_MKFS_MINIX\n\tbool \"mkfs.minix (10 kb)\"\n\tdefault BUSYBOX_DEFAULT_MKFS_MINIX\n\thelp\n\tThe minix filesystem is a nice, small, compact, read-write filesystem\n\twith little overhead. If you wish to be able to create minix\n\tfilesystems this utility will do the job for you.\n\nconfig BUSYBOX_CONFIG_FEATURE_MINIX2\n\tbool \"Support Minix fs v2 (fsck_minix/mkfs_minix)\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_MINIX2\n\tdepends on BUSYBOX_CONFIG_FSCK_MINIX || BUSYBOX_CONFIG_MKFS_MINIX\n\thelp\n\tIf you wish to be able to create version 2 minix filesystems, enable\n\tthis. If you enabled 'mkfs_minix' then you almost certainly want to\n\tbe using the version 2 filesystem support.\nconfig BUSYBOX_CONFIG_MKFS_REISER\n\tbool \"mkfs_reiser\"\n\tdefault BUSYBOX_DEFAULT_MKFS_REISER\n\thelp\n\tUtility to create ReiserFS filesystems.\n\tNote: this applet needs a lot of testing and polishing.\nconfig BUSYBOX_CONFIG_MKDOSFS\n\tbool \"mkdosfs (7.2 kb)\"\n\tdefault BUSYBOX_DEFAULT_MKDOSFS\n\thelp\n\tUtility to create FAT32 filesystems.\n\nconfig BUSYBOX_CONFIG_MKFS_VFAT\n\tbool \"mkfs.vfat (7.2 kb)\"\n\tdefault BUSYBOX_DEFAULT_MKFS_VFAT\n\thelp\n\tAlias to \"mkdosfs\".\nconfig BUSYBOX_CONFIG_MKSWAP\n\tbool \"mkswap (6.3 kb)\"\n\tdefault BUSYBOX_DEFAULT_MKSWAP\n\thelp\n\tThe mkswap utility is used to configure a file or disk partition as\n\tLinux swap space. This allows Linux to use the entire file or\n\tpartition as if it were additional RAM, which can greatly increase\n\tthe capability of low-memory machines. This additional memory is\n\tmuch slower than real RAM, but can be very helpful at preventing your\n\tapplications being killed by the Linux out of memory (OOM) killer.\n\tOnce you have created swap space using 'mkswap' you need to enable\n\tthe swap space using the 'swapon' utility.\n\nconfig BUSYBOX_CONFIG_FEATURE_MKSWAP_UUID\n\tbool \"UUID support\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_MKSWAP_UUID\n\tdepends on BUSYBOX_CONFIG_MKSWAP\n\thelp\n\tGenerate swap spaces with universally unique identifiers.\nconfig BUSYBOX_CONFIG_MORE\n\tbool \"more (7 kb)\"\n\tdefault BUSYBOX_DEFAULT_MORE\n\thelp\n\tmore is a simple utility which allows you to read text one screen\n\tsized page at a time. If you want to read text that is larger than\n\tthe screen, and you are using anything faster than a 300 baud modem,\n\tyou will probably find this utility very helpful. If you don't have\n\tany need to reading text files, you can leave this disabled.\nconfig BUSYBOX_CONFIG_MOUNT\n\tbool \"mount (23 kb)\"\n\tdefault BUSYBOX_DEFAULT_MOUNT\n\thelp\n\tAll files and filesystems in Unix are arranged into one big directory\n\ttree. The 'mount' utility is used to graft a filesystem onto a\n\tparticular part of the tree. A filesystem can either live on a block\n\tdevice, or it can be accessible over the network, as is the case with\n\tNFS filesystems.\n\nconfig BUSYBOX_CONFIG_FEATURE_MOUNT_FAKE\n\tbool \"Support -f (fake mount)\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_MOUNT_FAKE\n\tdepends on BUSYBOX_CONFIG_MOUNT\n\thelp\n\tEnable support for faking a file system mount.\n\nconfig BUSYBOX_CONFIG_FEATURE_MOUNT_VERBOSE\n\tbool \"Support -v (verbose)\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_MOUNT_VERBOSE\n\tdepends on BUSYBOX_CONFIG_MOUNT\n\thelp\n\tEnable multi-level -v[vv...] verbose messages. Useful if you\n\tdebug mount problems and want to see what is exactly passed\n\tto the kernel.\n\nconfig BUSYBOX_CONFIG_FEATURE_MOUNT_HELPERS\n\tbool \"Support mount helpers\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_MOUNT_HELPERS\n\tdepends on BUSYBOX_CONFIG_MOUNT\n\thelp\n\tEnable mounting of virtual file systems via external helpers.\n\tE.g. \"mount obexfs#-b00.11.22.33.44.55 /mnt\" will in effect call\n\t\"obexfs -b00.11.22.33.44.55 /mnt\"\n\tAlso \"mount -t sometype [-o opts] fs /mnt\" will try\n\t\"sometype [-o opts] fs /mnt\" if simple mount syscall fails.\n\tThe idea is to use such virtual filesystems in /etc/fstab.\n\nconfig BUSYBOX_CONFIG_FEATURE_MOUNT_LABEL\n\tbool \"Support specifying devices by label or UUID\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_MOUNT_LABEL\n\tdepends on BUSYBOX_CONFIG_MOUNT\n\tselect BUSYBOX_CONFIG_VOLUMEID\n\thelp\n\tThis allows for specifying a device by label or uuid, rather than by\n\tname. This feature utilizes the same functionality as blkid/findfs.\n\nconfig BUSYBOX_CONFIG_FEATURE_MOUNT_NFS\n\tbool \"Support mounting NFS file systems on Linux < 2.6.23\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_MOUNT_NFS\n\tdepends on BUSYBOX_CONFIG_MOUNT\n\tselect BUSYBOX_CONFIG_FEATURE_SYSLOG\n\thelp\n\tEnable mounting of NFS file systems on Linux kernels prior\n\tto version 2.6.23. Note that in this case mounting of NFS\n\tover IPv6 will not be possible.\n\n\tNote that this option links in RPC support from libc,\n\twhich is rather large (~10 kbytes on uclibc).\n\nconfig BUSYBOX_CONFIG_FEATURE_MOUNT_CIFS\n\tbool \"Support mounting CIFS/SMB file systems\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_MOUNT_CIFS\n\tdepends on BUSYBOX_CONFIG_MOUNT\n\thelp\n\tEnable support for samba mounts.\n\nconfig BUSYBOX_CONFIG_FEATURE_MOUNT_FLAGS\n\tdepends on BUSYBOX_CONFIG_MOUNT\n\tbool \"Support lots of -o flags\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_MOUNT_FLAGS\n\thelp\n\tWithout this, mount only supports ro/rw/remount. With this, it\n\tsupports nosuid, suid, dev, nodev, exec, noexec, sync, async, atime,\n\tnoatime, diratime, nodiratime, loud, bind, move, shared, slave,\n\tprivate, unbindable, rshared, rslave, rprivate, and runbindable.\n\nconfig BUSYBOX_CONFIG_FEATURE_MOUNT_FSTAB\n\tdepends on BUSYBOX_CONFIG_MOUNT\n\tbool \"Support /etc/fstab and -a (mount all)\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_MOUNT_FSTAB\n\thelp\n\tSupport mount all and looking for files in /etc/fstab.\n\nconfig BUSYBOX_CONFIG_FEATURE_MOUNT_OTHERTAB\n\tdepends on BUSYBOX_CONFIG_FEATURE_MOUNT_FSTAB\n\tbool \"Support -T <alt_fstab>\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_MOUNT_OTHERTAB\n\thelp\n\tSupport mount -T (specifying an alternate fstab)\nconfig BUSYBOX_CONFIG_MOUNTPOINT\n\tbool \"mountpoint (4.9 kb)\"\n\tdefault BUSYBOX_DEFAULT_MOUNTPOINT\n\thelp\n\tmountpoint checks if the directory is a mountpoint.\nconfig BUSYBOX_CONFIG_NOLOGIN\n\tbool \"nologin\"\n\tdefault BUSYBOX_DEFAULT_NOLOGIN\n\tdepends on BUSYBOX_CONFIG_FEATURE_SH_EMBEDDED_SCRIPTS\n\thelp\n\tPolitely refuse a login\n\nconfig BUSYBOX_CONFIG_NOLOGIN_DEPENDENCIES\n\tbool \"Enable dependencies for nologin\"\n\tdefault BUSYBOX_DEFAULT_NOLOGIN_DEPENDENCIES  # Y default makes it harder to select single-applet test\n\tdepends on BUSYBOX_CONFIG_NOLOGIN\n\tselect BUSYBOX_CONFIG_CAT\n\tselect BUSYBOX_CONFIG_ECHO\n\tselect BUSYBOX_CONFIG_SLEEP\n\thelp\n\tnologin is implemented as a shell script. It requires the\n\tfollowing in the runtime environment:\n\t\tcat echo sleep\n\tIf you know these will be available externally you can\n\tdisable this option.\nconfig BUSYBOX_CONFIG_NSENTER\n\tbool \"nsenter (6.5 kb)\"\n\tdefault BUSYBOX_DEFAULT_NSENTER\n\thelp\n\tRun program with namespaces of other processes.\nconfig BUSYBOX_CONFIG_PIVOT_ROOT\n\tbool \"pivot_root (1.1 kb)\"\n\tdefault BUSYBOX_DEFAULT_PIVOT_ROOT\n\thelp\n\tThe pivot_root utility swaps the mount points for the root filesystem\n\twith some other mounted filesystem. This allows you to do all sorts\n\tof wild and crazy things with your Linux system and is far more\n\tpowerful than 'chroot'.\n\n\tNote: This is for initrd in linux 2.4. Under initramfs (introduced\n\tin linux 2.6) use switch_root instead.\nconfig BUSYBOX_CONFIG_RDATE\n\tbool \"rdate (5.6 kb)\"\n\tdefault BUSYBOX_DEFAULT_RDATE\n\thelp\n\tThe rdate utility allows you to synchronize the date and time of your\n\tsystem clock with the date and time of a remote networked system using\n\tthe RFC868 protocol, which is built into the inetd daemon on most\n\tsystems.\nconfig BUSYBOX_CONFIG_RDEV\n\tbool \"rdev (1.8 kb)\"\n\tdefault BUSYBOX_DEFAULT_RDEV\n\thelp\n\tPrint the device node associated with the filesystem mounted at '/'.\nconfig BUSYBOX_CONFIG_READPROFILE\n\tbool \"readprofile (7.1 kb)\"\n\tdefault BUSYBOX_DEFAULT_READPROFILE\n\thelp\n\tThis allows you to parse /proc/profile for basic profiling.\nconfig BUSYBOX_CONFIG_RENICE\n\tbool \"renice (4.2 kb)\"\n\tdefault BUSYBOX_DEFAULT_RENICE\n\thelp\n\tRenice alters the scheduling priority of one or more running\n\tprocesses.\nconfig BUSYBOX_CONFIG_REV\n\tbool \"rev (4.4 kb)\"\n\tdefault BUSYBOX_DEFAULT_REV\n\thelp\n\tReverse lines of a file or files.\nconfig BUSYBOX_CONFIG_RTCWAKE\n\tbool \"rtcwake (6.8 kb)\"\n\tdefault BUSYBOX_DEFAULT_RTCWAKE\n\thelp\n\tEnter a system sleep state until specified wakeup time.\nconfig BUSYBOX_CONFIG_SCRIPT\n\tbool \"script (8.6 kb)\"\n\tdefault BUSYBOX_DEFAULT_SCRIPT\n\thelp\n\tThe script makes typescript of terminal session.\nconfig BUSYBOX_CONFIG_SCRIPTREPLAY\n\tbool \"scriptreplay (2.4 kb)\"\n\tdefault BUSYBOX_DEFAULT_SCRIPTREPLAY\n\thelp\n\tThis program replays a typescript, using timing information\n\tgiven by script -t.\nconfig BUSYBOX_CONFIG_SETARCH\n\tbool \"setarch (3.6 kb)\"\n\tdefault BUSYBOX_DEFAULT_SETARCH\n\thelp\n\tThe linux32 utility is used to create a 32bit environment for the\n\tspecified program (usually a shell). It only makes sense to have\n\tthis util on a system that supports both 64bit and 32bit userland\n\t(like amd64/x86, ppc64/ppc, sparc64/sparc, etc...).\n\nconfig BUSYBOX_CONFIG_LINUX32\n\tbool \"linux32 (3.3 kb)\"\n\tdefault BUSYBOX_DEFAULT_LINUX32\n\thelp\n\tAlias to \"setarch linux32\".\n\nconfig BUSYBOX_CONFIG_LINUX64\n\tbool \"linux64 (3.3 kb)\"\n\tdefault BUSYBOX_DEFAULT_LINUX64\n\thelp\n\tAlias to \"setarch linux64\".\nconfig BUSYBOX_CONFIG_SETPRIV\n\tbool \"setpriv (6.6 kb)\"\n\tdefault BUSYBOX_DEFAULT_SETPRIV\n\tselect BUSYBOX_CONFIG_LONG_OPTS\n\thelp\n\tRun a program with different Linux privilege settings.\n\tRequires kernel >= 3.5\n\nconfig BUSYBOX_CONFIG_FEATURE_SETPRIV_DUMP\n\tbool \"Support dumping current privilege state\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_SETPRIV_DUMP\n\tdepends on BUSYBOX_CONFIG_SETPRIV\n\thelp\n\tEnables the \"--dump\" switch to print out the current privilege\n\tstate. This is helpful for diagnosing problems.\n\nconfig BUSYBOX_CONFIG_FEATURE_SETPRIV_CAPABILITIES\n\tbool \"Support capabilities\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_SETPRIV_CAPABILITIES\n\tdepends on BUSYBOX_CONFIG_SETPRIV\n\thelp\n\tCapabilities can be used to grant processes additional rights\n\twithout the necessity to always execute as the root user.\n\tEnabling this option enables \"--dump\" to show information on\n\tcapabilities.\n\nconfig BUSYBOX_CONFIG_FEATURE_SETPRIV_CAPABILITY_NAMES\n\tbool \"Support capability names\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_SETPRIV_CAPABILITY_NAMES\n\tdepends on BUSYBOX_CONFIG_SETPRIV && BUSYBOX_CONFIG_FEATURE_SETPRIV_CAPABILITIES\n\thelp\n\tCapabilities can be either referenced via a human-readble name,\n\te.g. \"net_admin\", or using their index, e.g. \"cap_12\". Enabling\n\tthis option allows using the human-readable names in addition to\n\tthe index-based names.\nconfig BUSYBOX_CONFIG_SETSID\n\tbool \"setsid (3.6 kb)\"\n\tdefault BUSYBOX_DEFAULT_SETSID\n\thelp\n\tsetsid runs a program in a new session\nconfig BUSYBOX_CONFIG_SWAPON\n\tbool \"swapon (15 kb)\"\n\tdefault BUSYBOX_DEFAULT_SWAPON\n\thelp\n\tOnce you have created some swap space using 'mkswap', you also need\n\tto enable your swap space with the 'swapon' utility. The 'swapoff'\n\tutility is used, typically at system shutdown, to disable any swap\n\tspace. If you are not using any swap space, you can leave this\n\toption disabled.\n\nconfig BUSYBOX_CONFIG_FEATURE_SWAPON_DISCARD\n\tbool \"Support discard option -d\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_SWAPON_DISCARD\n\tdepends on BUSYBOX_CONFIG_SWAPON\n\thelp\n\tEnable support for discarding swap area blocks at swapon and/or as\n\tthe kernel frees them. This option enables both the -d option on\n\t'swapon' and the 'discard' option for swap entries in /etc/fstab.\n\nconfig BUSYBOX_CONFIG_FEATURE_SWAPON_PRI\n\tbool \"Support priority option -p\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_SWAPON_PRI\n\tdepends on BUSYBOX_CONFIG_SWAPON\n\thelp\n\tEnable support for setting swap device priority in swapon.\n\nconfig BUSYBOX_CONFIG_SWAPOFF\n\tbool \"swapoff (14 kb)\"\n\tdefault BUSYBOX_DEFAULT_SWAPOFF\n\nconfig BUSYBOX_CONFIG_FEATURE_SWAPONOFF_LABEL\n\tbool \"Support specifying devices by label or UUID\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_SWAPONOFF_LABEL\n\tdepends on BUSYBOX_CONFIG_SWAPON || BUSYBOX_CONFIG_SWAPOFF\n\tselect BUSYBOX_CONFIG_VOLUMEID\n\thelp\n\tThis allows for specifying a device by label or uuid, rather than by\n\tname. This feature utilizes the same functionality as blkid/findfs.\nconfig BUSYBOX_CONFIG_SWITCH_ROOT\n\tbool \"switch_root (5.5 kb)\"\n\tdefault BUSYBOX_DEFAULT_SWITCH_ROOT\n\thelp\n\tThe switch_root utility is used from initramfs to select a new\n\troot device. Under initramfs, you have to use this instead of\n\tpivot_root. (Stop reading here if you don't care why.)\n\n\tBooting with initramfs extracts a gzipped cpio archive into rootfs\n\t(which is a variant of ramfs/tmpfs). Because rootfs can't be moved\n\tor unmounted*, pivot_root will not work from initramfs. Instead,\n\tswitch_root deletes everything out of rootfs (including itself),\n\tdoes a mount --move that overmounts rootfs with the new root, and\n\tthen execs the specified init program.\n\n\t* Because the Linux kernel uses rootfs internally as the starting\n\tand ending point for searching through the kernel's doubly linked\n\tlist of active mount points. That's why.\n\nconfig BUSYBOX_CONFIG_TASKSET\n\tbool \"taskset (4.2 kb)\"\n\tdefault BUSYBOX_DEFAULT_TASKSET\n\thelp\n\tRetrieve or set a processes's CPU affinity.\n\tThis requires sched_{g,s}etaffinity support in your libc.\n\nconfig BUSYBOX_CONFIG_FEATURE_TASKSET_FANCY\n\tbool \"Fancy output\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_TASKSET_FANCY\n\tdepends on BUSYBOX_CONFIG_TASKSET\n\thelp\n\tNeeded for machines with more than 32-64 CPUs:\n\taffinity parameter 0xHHHHHHHHHHHHHHHHHHHH can be arbitrarily long\n\tin this case. Otherwise, it is limited to sizeof(long).\n\nconfig BUSYBOX_CONFIG_FEATURE_TASKSET_CPULIST\n\tbool \"CPU list support (-c option)\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_TASKSET_CPULIST\n\tdepends on BUSYBOX_CONFIG_FEATURE_TASKSET_FANCY\n\thelp\n\tAdd support for taking/printing affinity as CPU list when '-c'\n\toption is used. For example, it prints '0-3,7' instead of mask '8f'.\nconfig BUSYBOX_CONFIG_UEVENT\n\tbool \"uevent (3.1 kb)\"\n\tdefault BUSYBOX_DEFAULT_UEVENT\n\thelp\n\tuevent is a netlink listener for kernel uevent notifications\n\tsent via netlink. It is usually used for dynamic device creation.\nconfig BUSYBOX_CONFIG_UMOUNT\n\tbool \"umount (5.1 kb)\"\n\tdefault BUSYBOX_DEFAULT_UMOUNT\n\thelp\n\tWhen you want to remove a mounted filesystem from its current mount\n\tpoint, for example when you are shutting down the system, the\n\t'umount' utility is the tool to use. If you enabled the 'mount'\n\tutility, you almost certainly also want to enable 'umount'.\n\nconfig BUSYBOX_CONFIG_FEATURE_UMOUNT_ALL\n\tbool \"Support -a (unmount all)\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_UMOUNT_ALL\n\tdepends on BUSYBOX_CONFIG_UMOUNT\n\thelp\n\tSupport -a option to unmount all currently mounted filesystems.\nconfig BUSYBOX_CONFIG_UNSHARE\n\tbool \"unshare (7.2 kb)\"\n\tdefault BUSYBOX_DEFAULT_UNSHARE\n\tdepends on !BUSYBOX_CONFIG_NOMMU\n\tselect BUSYBOX_CONFIG_LONG_OPTS\n\thelp\n\tRun program with some namespaces unshared from parent.\nconfig BUSYBOX_CONFIG_WALL\n\tbool \"wall (2.6 kb)\"\n\tdefault BUSYBOX_DEFAULT_WALL\n\tdepends on BUSYBOX_CONFIG_FEATURE_UTMP\n\thelp\n\tWrite a message to all users that are logged in.\n\ncomment \"Common options for mount/umount\"\n\tdepends on BUSYBOX_CONFIG_MOUNT || BUSYBOX_CONFIG_UMOUNT\n\nconfig BUSYBOX_CONFIG_FEATURE_MOUNT_LOOP\n\tbool \"Support loopback mounts\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_MOUNT_LOOP\n\tdepends on BUSYBOX_CONFIG_MOUNT || BUSYBOX_CONFIG_UMOUNT\n\thelp\n\tEnabling this feature allows automatic mounting of files (containing\n\tfilesystem images) via the linux kernel's loopback devices.\n\tThe mount command will detect you are trying to mount a file instead\n\tof a block device, and transparently associate the file with a\n\tloopback device. The umount command will also free that loopback\n\tdevice.\n\n\tYou can still use the 'losetup' utility (to manually associate files\n\twith loop devices) if you need to do something advanced, such as\n\tspecify an offset or cryptographic options to the loopback device.\n\t(If you don't want umount to free the loop device, use \"umount -D\".)\n\nconfig BUSYBOX_CONFIG_FEATURE_MOUNT_LOOP_CREATE\n\tbool \"Create new loopback devices if needed\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_MOUNT_LOOP_CREATE\n\tdepends on BUSYBOX_CONFIG_FEATURE_MOUNT_LOOP\n\thelp\n\tLinux kernels >= 2.6.24 support unlimited loopback devices. They are\n\tallocated for use when trying to use a loop device. The loop device\n\tmust however exist.\n\n\tThis feature lets mount to try to create next /dev/loopN device\n\tif it does not find a free one.\n\nconfig BUSYBOX_CONFIG_FEATURE_MTAB_SUPPORT\n\tbool \"Support old /etc/mtab file\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_MTAB_SUPPORT\n\tdepends on BUSYBOX_CONFIG_MOUNT || BUSYBOX_CONFIG_UMOUNT\n\tselect BUSYBOX_CONFIG_FEATURE_MOUNT_FAKE\n\thelp\n\tHistorically, Unix systems kept track of the currently mounted\n\tpartitions in the file \"/etc/mtab\". These days, the kernel exports\n\tthe list of currently mounted partitions in \"/proc/mounts\", rendering\n\tthe old mtab file obsolete. (In modern systems, /etc/mtab should be\n\ta symlink to /proc/mounts.)\n\n\tThe only reason to have mount maintain an /etc/mtab file itself is if\n\tyour stripped-down embedded system does not have a /proc directory.\n\tIf you must use this, keep in mind it's inherently brittle (for\n\texample a mount under chroot won't update it), can't handle modern\n\tfeatures like separate per-process filesystem namespaces, requires\n\tthat your /etc directory be writable, tends to get easily confused\n\tby --bind or --move mounts, won't update if you rename a directory\n\tthat contains a mount point, and so on. (In brief: avoid.)\n\n\tAbout the only reason to use this is if you've removed /proc from\n\tyour kernel.\n\nsource \"volume_id/Config.in\"\n\nendmenu\n"
  },
  {
    "path": "package/utils/busybox/config/util-linux/volume_id/Config.in",
    "content": "# DO NOT EDIT. This file is generated from Config.src\n#\n# For a description of the syntax of this configuration file,\n# see docs/Kconfig-language.txt.\n#\n\nconfig BUSYBOX_CONFIG_VOLUMEID\n\tbool #No description makes it a hidden option\n\tdefault BUSYBOX_DEFAULT_VOLUMEID\n\nmenu \"Filesystem/Volume identification\"\n\tdepends on BUSYBOX_CONFIG_VOLUMEID\n\nconfig BUSYBOX_CONFIG_FEATURE_VOLUMEID_BCACHE\n\tbool \"bcache filesystem\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_VOLUMEID_BCACHE\n\tdepends on BUSYBOX_CONFIG_VOLUMEID\nconfig BUSYBOX_CONFIG_FEATURE_VOLUMEID_BTRFS\n\tbool \"btrfs filesystem\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_VOLUMEID_BTRFS\n\tdepends on BUSYBOX_CONFIG_VOLUMEID\nconfig BUSYBOX_CONFIG_FEATURE_VOLUMEID_CRAMFS\n\tbool \"cramfs filesystem\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_VOLUMEID_CRAMFS\n\tdepends on BUSYBOX_CONFIG_VOLUMEID\nconfig BUSYBOX_CONFIG_FEATURE_VOLUMEID_EROFS\n\tbool \"erofs filesystem\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_VOLUMEID_EROFS\n\tdepends on BUSYBOX_CONFIG_VOLUMEID\n\thelp\n\tErofs is a compressed readonly filesystem for Linux.\nconfig BUSYBOX_CONFIG_FEATURE_VOLUMEID_EXFAT\n\tbool \"exFAT filesystem\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_VOLUMEID_EXFAT\n\tdepends on BUSYBOX_CONFIG_VOLUMEID\n\thelp\n\texFAT (extended FAT) is a proprietary file system designed especially\n\tfor flash drives. It has many features from NTFS, but with less\n\toverhead. exFAT is used on most SDXC cards for consumer electronics.\nconfig BUSYBOX_CONFIG_FEATURE_VOLUMEID_EXT\n\tbool \"Ext filesystem\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_VOLUMEID_EXT\n\tdepends on BUSYBOX_CONFIG_VOLUMEID\nconfig BUSYBOX_CONFIG_FEATURE_VOLUMEID_F2FS\n\tbool \"f2fs filesystem\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_VOLUMEID_F2FS\n\tdepends on BUSYBOX_CONFIG_VOLUMEID\n\thelp\n\tF2FS (aka Flash-Friendly File System) is a log-structured file system,\n\twhich is adapted to newer forms of storage. F2FS also remedies some\n\tknown issues of the older log structured file systems, such as high\n\tcleaning overhead.\nconfig BUSYBOX_CONFIG_FEATURE_VOLUMEID_FAT\n\tbool \"fat filesystem\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_VOLUMEID_FAT\n\tdepends on BUSYBOX_CONFIG_VOLUMEID\nconfig BUSYBOX_CONFIG_FEATURE_VOLUMEID_HFS\n\tbool \"hfs filesystem\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_VOLUMEID_HFS\n\tdepends on BUSYBOX_CONFIG_VOLUMEID\nconfig BUSYBOX_CONFIG_FEATURE_VOLUMEID_ISO9660\n\tbool \"iso9660 filesystem\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_VOLUMEID_ISO9660\n\tdepends on BUSYBOX_CONFIG_VOLUMEID\nconfig BUSYBOX_CONFIG_FEATURE_VOLUMEID_JFS\n\tbool \"jfs filesystem\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_VOLUMEID_JFS\n\tdepends on BUSYBOX_CONFIG_VOLUMEID\nconfig BUSYBOX_CONFIG_FEATURE_VOLUMEID_LFS\n\tbool \"LittleFS filesystem\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_VOLUMEID_LFS\n\tdepends on BUSYBOX_CONFIG_VOLUMEID && BUSYBOX_CONFIG_FEATURE_BLKID_TYPE\n\thelp\n\tLittleFS is a small fail-safe filesystem designed for embedded\n\tsystems. It has strong copy-on-write guarantees and storage on disk\n\tis always kept in a valid state. It also provides a form of dynamic\n\twear levelling for systems that can not fit a full flash translation\n\tlayer.\nconfig BUSYBOX_CONFIG_FEATURE_VOLUMEID_LINUXRAID\n\tbool \"linuxraid\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_VOLUMEID_LINUXRAID\n\tdepends on BUSYBOX_CONFIG_VOLUMEID\nconfig BUSYBOX_CONFIG_FEATURE_VOLUMEID_LINUXSWAP\n\tbool \"linux swap filesystem\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_VOLUMEID_LINUXSWAP\n\tdepends on BUSYBOX_CONFIG_VOLUMEID\nconfig BUSYBOX_CONFIG_FEATURE_VOLUMEID_LUKS\n\tbool \"luks filesystem\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_VOLUMEID_LUKS\n\tdepends on BUSYBOX_CONFIG_VOLUMEID\nconfig BUSYBOX_CONFIG_FEATURE_VOLUMEID_MINIX\n\tbool \"minix filesystem\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_VOLUMEID_MINIX\n\tdepends on BUSYBOX_CONFIG_VOLUMEID\nconfig BUSYBOX_CONFIG_FEATURE_VOLUMEID_NILFS\n\tbool \"nilfs filesystem\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_VOLUMEID_NILFS\n\tdepends on BUSYBOX_CONFIG_VOLUMEID\n\thelp\n\tNILFS is a New Implementation of a Log-Structured File System (LFS)\n\tthat supports continuous snapshots. This provides features like\n\tversioning of the entire filesystem, restoration of files that\n\twere deleted a few minutes ago. NILFS keeps consistency like\n\tconventional LFS, so it provides quick recovery after system crashes.\n\n\tThe possible use of NILFS includes versioning, tamper detection,\n\tSOX compliance logging, and so forth. It can serve as an alternative\n\tfilesystem for Linux desktop environment, or as a basis of advanced\n\tstorage appliances.\nconfig BUSYBOX_CONFIG_FEATURE_VOLUMEID_NTFS\n\tbool \"ntfs filesystem\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_VOLUMEID_NTFS\n\tdepends on BUSYBOX_CONFIG_VOLUMEID\nconfig BUSYBOX_CONFIG_FEATURE_VOLUMEID_OCFS2\n\tbool \"ocfs2 filesystem\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_VOLUMEID_OCFS2\n\tdepends on BUSYBOX_CONFIG_VOLUMEID\nconfig BUSYBOX_CONFIG_FEATURE_VOLUMEID_REISERFS\n\tbool \"Reiser filesystem\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_VOLUMEID_REISERFS\n\tdepends on BUSYBOX_CONFIG_VOLUMEID\nconfig BUSYBOX_CONFIG_FEATURE_VOLUMEID_ROMFS\n\tbool \"romfs filesystem\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_VOLUMEID_ROMFS\n\tdepends on BUSYBOX_CONFIG_VOLUMEID\nconfig BUSYBOX_CONFIG_FEATURE_VOLUMEID_SQUASHFS\n\tbool \"SquashFS filesystem\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_VOLUMEID_SQUASHFS\n\tdepends on BUSYBOX_CONFIG_VOLUMEID && BUSYBOX_CONFIG_FEATURE_BLKID_TYPE\n\thelp\n\tSquashfs is a compressed read-only filesystem for Linux. Squashfs is\n\tintended for general read-only filesystem use and in constrained block\n\tdevice/memory systems (e.g. embedded systems) where low overhead is\n\tneeded.\nconfig BUSYBOX_CONFIG_FEATURE_VOLUMEID_SYSV\n\tbool \"sysv filesystem\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_VOLUMEID_SYSV\n\tdepends on BUSYBOX_CONFIG_VOLUMEID\nconfig BUSYBOX_CONFIG_FEATURE_VOLUMEID_UBIFS\n\tbool \"UBIFS filesystem\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_VOLUMEID_UBIFS\n\tdepends on BUSYBOX_CONFIG_VOLUMEID\n\thelp\n\tUBIFS (Unsorted Block Image File System) is a file\n\tsystem for use with raw flash memory media.\nconfig BUSYBOX_CONFIG_FEATURE_VOLUMEID_UDF\n\tbool \"udf filesystem\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_VOLUMEID_UDF\n\tdepends on BUSYBOX_CONFIG_VOLUMEID\n### config FEATURE_VOLUMEID_HIGHPOINTRAID\n###\tbool \"highpoint raid\"\n###\tdefault y\n###\tdepends on VOLUMEID\n### config FEATURE_VOLUMEID_HPFS\n###\tbool \"hpfs filesystem\"\n###\tdefault y\n###\tdepends on VOLUMEID\n### config FEATURE_VOLUMEID_ISWRAID\n###\tbool \"intel raid\"\n###\tdefault y\n###\tdepends on VOLUMEID\n### config FEATURE_VOLUMEID_LSIRAID\n###\tbool \"lsi raid\"\n###\tdefault y\n###\tdepends on VOLUMEID\n### config FEATURE_VOLUMEID_LVM\n###\tbool \"lvm\"\n###\tdefault y\n###\tdepends on VOLUMEID\n### config FEATURE_VOLUMEID_MAC\n###\tbool \"mac filesystem\"\n###\tdefault y\n###\tdepends on VOLUMEID\n### config FEATURE_VOLUMEID_MSDOS\n###\tbool \"msdos filesystem\"\n###\tdefault y\n###\tdepends on VOLUMEID\n### config FEATURE_VOLUMEID_NVIDIARAID\n###\tbool \"nvidia raid\"\n###\tdefault y\n###\tdepends on VOLUMEID\n### config FEATURE_VOLUMEID_PROMISERAID\n###\tbool \"promise raid\"\n###\tdefault y\n###\tdepends on VOLUMEID\n### config FEATURE_VOLUMEID_SILICONRAID\n###\tbool \"silicon raid\"\n###\tdefault y\n###\tdepends on VOLUMEID\n### config FEATURE_VOLUMEID_UFS\n###\tbool \"ufs filesystem\"\n###\tdefault y\n###\tdepends on VOLUMEID\n### config FEATURE_VOLUMEID_VIARAID\n###\tbool \"via raid\"\n###\tdefault y\n###\tdepends on VOLUMEID\nconfig BUSYBOX_CONFIG_FEATURE_VOLUMEID_XFS\n\tbool \"xfs filesystem\"\n\tdefault BUSYBOX_DEFAULT_FEATURE_VOLUMEID_XFS\n\tdepends on BUSYBOX_CONFIG_VOLUMEID\n\nendmenu\n"
  },
  {
    "path": "package/utils/busybox/convert_defaults.pl",
    "content": "#!/usr/bin/env perl\n\nwhile (<>) {\n\t/^(# )?CONFIG_([^=]+)(=(.+)| is not set)/ and do {\n\t\tmy $default = $4;\n\t\t$1 and $default = \"n\";\n\t\tmy $name = $2;\n\t\tmy $type = \"bool\";\n\t\t$default =~ /^\\\"/ and $type = \"string\";\n\t\t$default =~ /^\\d/ and $type = \"int\";\n\t\tprint \"config BUSYBOX_DEFAULT_$name\\n\\t$type\\n\\tdefault $default\\n\";\n\t};\n}\n"
  },
  {
    "path": "package/utils/busybox/convert_menuconfig.pl",
    "content": "#!/usr/bin/perl\n# \n# Copyright (C) 2006 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\nuse strict;\nmy $PATH = $ARGV[0];\n($PATH and -d $PATH) or die 'invalid path';\n\nmy %config;\n\nopen FIND, \"find \\\"$PATH\\\" -name Config.in |\";\nwhile (<FIND>) {\n\tchomp;\n\tmy $input = $_;\n\tmy $output = $input;\n\tmy $replace = quotemeta($PATH);\n\t$output =~ s/^$replace\\///g;\n\t$output =~ s/sysdeps\\/linux\\///g;\n\tprint STDERR \"$input => $output\\n\";\n\t$output =~ /^(.+)\\/[^\\/]+$/ and system(\"mkdir -p $1\");\n\n\topen INPUT, $input;\n\topen OUTPUT, \">$output\";\n\tmy ($cur, $default_set, $line);\n\twhile ($line = <INPUT>) {\n\t\tnext if $line =~ /^\\s*mainmenu/;\n\n\t\t# FIXME: make this dynamic\n\t\t$line =~ s/default FEATURE_BUFFERS_USE_MALLOC/default FEATURE_BUFFERS_GO_ON_STACK/;\n\t\t$line =~ s/default FEATURE_SH_IS_NONE/default FEATURE_SH_IS_ASH/;\n\n\t\tif ($line =~ /^\\s*config\\s*([\\w_]+)/) {\n\t\t\t$cur = $1;\n\t\t\tundef $default_set;\n\t\t}\n\t\tif ($line =~ /^\\s*(menu|choice|end|source)/) {\n\t\t\tundef $cur;\n\t\t\tundef $default_set;\n\t\t}\n\t\t$line =~ s/^(\\s*source\\s+)([^\\/]+\\/)*([^\\/]+\\/[^\\/]+)$/$1$3/;\n\t\tif ($line =~ /^(\\s*range\\s*)(\\w+)(\\s+)(\\w+)\\s*$/) {\n\t\t\tmy $prefix = $1;\n\t\t\tmy $r1 = $2;\n\t\t\tmy $r2 = $4;\n\t\t\t$r1 =~ s/^([a-zA-Z]+)/BUSYBOX_CONFIG_$1/;\n\t\t\t$r2 =~ s/^([a-zA-Z]+)/BUSYBOX_CONFIG_$1/;\n\t\t\t$line = \"$prefix$r1 $r2\\n\";\n\t\t}\n\n\t\t$line =~ s/^(\\s*(prompt \"[^\"]+\" if|config|depends|depends on|select|default|default \\w if)\\s+\\!?)([A-Z_])/$1BUSYBOX_CONFIG_$3/g;\n\t\t$line =~ s/(( \\|\\| | \\&\\& | \\( )!?)([A-Z_])/$1BUSYBOX_CONFIG_$3/g;\n\t\t$line =~ s/(\\( ?!?)([A-Z_]+ (\\|\\||&&))/$1BUSYBOX_CONFIG_$2/g;\n\n\t\tif ($cur) {\n\t\t\t($cur eq 'LFS') and do {\n\t\t\t\t$line =~ s/^(\\s*(bool|tristate|string))\\s*\".+\"$/$1/;\n\t\t\t};\n\t\t\tif ($line =~ /^\\s*default/) {\n\t\t\t\tmy $c;\n\t\t\t\t$default_set = 1;\n\t\t\t\t$c = \"BUSYBOX_DEFAULT_$cur\";\n\n\t\t\t\t$line =~ s/^(\\s*default\\s*)(\\w+|\"[^\"]*\")(.*)/$1$c$3/;\n\t\t\t}\n\t\t}\n\n\t\tprint OUTPUT $line;\n\t}\n\tclose OUTPUT;\n\tclose INPUT;\n}\nclose FIND;\n"
  },
  {
    "path": "package/utils/busybox/files/cron",
    "content": "#!/bin/sh /etc/rc.common\n# Copyright (C) 2006-2011 OpenWrt.org\n\nSTART=50\n\nUSE_PROCD=1\nPROG=/usr/sbin/crond\n\nvalidate_cron_section() {\n\tuci_validate_section system system \"${1}\" \\\n\t\t'cronloglevel:uinteger'\n}\n\nstart_service() {\n\t[ -z \"$(ls /etc/crontabs/)\" ] && return 1\n\n\tloglevel=\"$(uci_get \"system.@system[0].cronloglevel\")\"\n\n\t[ -z \"${loglevel}\" ] || {\n\t\t/sbin/validate_data uinteger \"${loglevel}\" 2>/dev/null\n\t\t[ \"$?\" -eq 0 ] || {\n\t\t\techo \"validation failed\"\n\t\t\treturn 1\n\t\t}\n\t}\n\n\tmkdir -p /var/spool/cron\n\tln -s /etc/crontabs /var/spool/cron/ 2>/dev/null\n\n\tprocd_open_instance\n\tprocd_set_param command \"$PROG\" -f -c /etc/crontabs -l \"${loglevel:-5}\"\n\tfor crontab in /etc/crontabs/*; do\n\t\t procd_set_param file \"$crontab\"\n\tdone\n\tprocd_set_param respawn\n\tprocd_close_instance\n}\n\nservice_triggers() {\n\tprocd_add_validation validate_cron_section\n}\n"
  },
  {
    "path": "package/utils/busybox/files/ntpd-hotplug",
    "content": "#!/bin/sh\n\n. /usr/share/libubox/jshn.sh\n\naddenv=\"$( env | while read line; do echo \"json_add_string \\\"\\\" \\\"$line\\\";\"; done )\"\njson_init\njson_add_array env\njson_add_string \"\" \"ACTION=$1\"\neval \"$addenv\"\njson_close_array env\n\nubus call hotplug.ntp call \"$(json_dump)\"\n"
  },
  {
    "path": "package/utils/busybox/files/ntpd.capabilities",
    "content": "{\n\t\"bounding\": [\n\t\t\"CAP_NET_BIND_SERVICE\",\n\t\t\"CAP_SYS_TIME\"\n\t],\n\t\"effective\": [\n\t\t\"CAP_NET_BIND_SERVICE\",\n\t\t\"CAP_SYS_TIME\"\n\t],\n\t\"ambient\": [\n\t\t\"CAP_NET_BIND_SERVICE\",\n\t\t\"CAP_SYS_TIME\"\n\t],\n\t\"permitted\": [\n\t\t\"CAP_NET_BIND_SERVICE\",\n\t\t\"CAP_SYS_TIME\"\n\t],\n\t\"inheritable\": [\n\t\t\"CAP_NET_BIND_SERVICE\",\n\t\t\"CAP_SYS_TIME\"\n\t]\n}\n"
  },
  {
    "path": "package/utils/busybox/files/ntpd_acl.json",
    "content": "{\n\t\"user\": \"ntp\",\n\t\"access\": {\n\t\t\"hotplug.ntp\": {\n\t\t\t\"methods\": [ \"call\" ]\n\t\t}\n\t}\n}\n"
  },
  {
    "path": "package/utils/busybox/files/sysntpd",
    "content": "#!/bin/sh /etc/rc.common\n# Copyright (C) 2011 OpenWrt.org\n\nSTART=98\n\nUSE_PROCD=1\nPROG=/usr/sbin/ntpd\nHOTPLUG_SCRIPT=/usr/sbin/ntpd-hotplug\n\nget_dhcp_ntp_servers() {\n\tlocal interfaces=\"$1\"\n\tlocal filter=\"*\"\n\tlocal interface ntpservers ntpserver\n\n\tfor interface in $interfaces; do\n\t\t[ \"$filter\" = \"*\" ] && filter=\"@.interface='$interface'\" || filter=\"$filter,@.interface='$interface'\"\n\tdone\n\n\tntpservers=$(ubus call network.interface dump | jsonfilter -e \"@.interface[$filter]['data']['ntpserver']\")\n\n\tfor ntpserver in $ntpservers; do\n\t\tlocal duplicate=0\n\t\tlocal entry\n\t\tfor entry in $server; do\n\t\t\t[ \"$ntpserver\" = \"$entry\" ] && duplicate=1\n\t\tdone\n\t\t[ \"$duplicate\" = 0 ] && server=\"$server $ntpserver\"\n\tdone\n}\n\nvalidate_ntp_section() {\n\tuci_load_validate system timeserver \"$1\" \"$2\" \\\n\t\t'dhcp_interface:list(string)' \\\n\t\t'enable_server:bool:0' \\\n\t\t'enabled:bool:1' \\\n\t\t'interface:string' \\\n\t\t'server:list(host)' \\\n\t\t'use_dhcp:bool:1'\n}\n\nstart_ntpd_instance() {\n\tlocal peer\n\n\t[ \"$2\" = 0 ] || {\n\t\techo \"validation failed\"\n\t\treturn 1\n\t}\n\n\t[ $enabled = 0 ] && return\n\n\t[ $use_dhcp = 1 ] && get_dhcp_ntp_servers \"$dhcp_interface\"\n\n\t[ -z \"$server\" -a \"$enable_server\" = \"0\" ] && return\n\n\tprocd_open_instance\n\tprocd_set_param command \"$PROG\" -n -N\n\tif [ \"$enable_server\" = \"1\" ]; then\n\t\tprocd_append_param command -l\n\t\t[ -n \"$interface\" ] && {\n\t\t\tlocal ifname\n\n\t\t\tnetwork_get_device ifname \"$interface\" || \\\n\t\t\t\tifname=\"$interface\"\n\t\t\tprocd_append_param command -I \"$ifname\"\n\t\t\tprocd_append_param netdev \"$ifname\"\n\t\t}\n\tfi\n\t[ -x \"$HOTPLUG_SCRIPT\" ] && procd_append_param command -S \"$HOTPLUG_SCRIPT\"\n\tfor peer in $server; do\n\t\tprocd_append_param command -p $peer\n\tdone\n\tprocd_set_param respawn\n\t[ -x /sbin/ujail -a -e /etc/capabilities/ntpd.json ] && {\n\t\tprocd_add_jail ntpd ubus\n\t\tprocd_add_jail_mount \"$HOTPLUG_SCRIPT\"\n\t\tprocd_add_jail_mount \"/usr/share/libubox/jshn.sh\"\n\t\tprocd_add_jail_mount \"/usr/bin/env\"\n\t\tprocd_add_jail_mount \"/usr/bin/jshn\"\n\t\tprocd_add_jail_mount \"/bin/ubus\"\n\t\tprocd_set_param capabilities /etc/capabilities/ntpd.json\n\t\tprocd_set_param user ntp\n\t\tprocd_set_param group ntp\n\t\tprocd_set_param no_new_privs 1\n\t}\n\tprocd_close_instance\n}\n\nstart_service() {\n\t. /lib/functions/network.sh\n\tvalidate_ntp_section ntp start_ntpd_instance\n}\n\nservice_triggers() {\n\tlocal script name use_dhcp enable_server interface\n\n\tscript=$(readlink -f \"$initscript\")\n\tname=$(basename ${script:-$initscript})\n\n\tprocd_add_config_trigger \"config.change\" \"system\" /etc/init.d/$name reload\n\n\tconfig_load system\n\tconfig_get use_dhcp ntp use_dhcp 1\n\n\t[ $use_dhcp = 1 ] && {\n\t\tlocal dhcp_interface\n\t\tconfig_get dhcp_interface ntp dhcp_interface\n\n\t\tif [ -n \"$dhcp_interface\" ]; then\n\t\t\tfor n in $dhcp_interface; do\n\t\t\t\tprocd_add_interface_trigger \"interface.*\" $n /etc/init.d/$name reload\n\t\t\tdone\n\t\telse\n\t\t\tprocd_add_raw_trigger \"interface.*\" 1000 /etc/init.d/$name reload\n\t\tfi\n\t}\n\n\tconfig_get_bool enable_server ntp enable_server 0\n\tconfig_get interface ntp interface\n\n\t[ $enable_server -eq 1 ] && [ -n \"$interface\" ] && {\n\t\tlocal ifname\n\n\t\tnetwork_get_device ifname \"$interface\" || \\\n\t\t\tifname=\"$interface\"\n\t\tprocd_add_interface_trigger \"interface.*\" \"$ifname\" \\\n\t\t\t/etc/init.d/\"$name\" reload\n\t}\n\n\tprocd_add_validation validate_ntp_section\n}\n"
  },
  {
    "path": "package/utils/busybox/patches/120-lto-jobserver.patch",
    "content": "--- a/scripts/Kbuild.include\n+++ b/scripts/Kbuild.include\n@@ -131,7 +131,7 @@ make-cmd = $(subst \\#,\\\\\\#,$(subst $$,$$\n #\n if_changed = $(if $(strip $(filter-out $(PHONY),$?)          \\\n \t\t$(call arg-check, $(cmd_$(1)), $(cmd_$@)) ), \\\n-\t@set -e; \\\n+\t+@set -e; \\\n \t$(echo-cmd) $(cmd_$(1)); \\\n \techo 'cmd_$@ := $(make-cmd)' > $(@D)/.$(@F).cmd)\n \n@@ -140,7 +140,7 @@ if_changed = $(if $(strip $(filter-out $\n if_changed_dep = $(if $(strip $(filter-out $(PHONY),$?)  \\\n \t\t$(filter-out FORCE $(wildcard $^),$^)    \\\n \t$(call arg-check, $(cmd_$(1)), $(cmd_$@)) ),     \\\n-\t@set -e; \\\n+\t+@set -e; \\\n \t$(echo-cmd) $(cmd_$(1)); \\\n \tscripts/basic/fixdep $(depfile) $@ '$(make-cmd)' > $(@D)/.$(@F).tmp; \\\n \trm -f $(depfile); \\\n@@ -151,5 +151,5 @@ if_changed_dep = $(if $(strip $(filter-o\n # and if so will execute $(rule_foo)\n if_changed_rule = $(if $(strip $(filter-out $(PHONY),$?)            \\\n \t\t\t$(call arg-check, $(cmd_$(1)), $(cmd_$@)) ),\\\n-\t\t\t@set -e; \\\n+\t\t\t+@set -e; \\\n \t\t\t$(rule_$(1)))\n"
  },
  {
    "path": "package/utils/busybox/patches/200-udhcpc_reduce_msgs.patch",
    "content": "--- a/networking/udhcp/dhcpc.c\n+++ b/networking/udhcp/dhcpc.c\n@@ -722,6 +722,7 @@ static int bcast_or_ucast(struct dhcp_pa\n static NOINLINE int send_discover(uint32_t requested)\n {\n \tstruct dhcp_packet packet;\n+\tstatic int msgs = 0;\n \n \t/* Fill in: op, htype, hlen, cookie, chaddr fields,\n \t * xid field, message type option:\n@@ -736,6 +737,7 @@ static NOINLINE int send_discover(uint32\n \t */\n \tadd_client_options(&packet);\n \n+\tif (msgs++ < 3)\n \tbb_simple_info_msg(\"broadcasting discover\");\n \treturn raw_bcast_from_client_data_ifindex(&packet, INADDR_ANY);\n }\n"
  },
  {
    "path": "package/utils/busybox/patches/201-udhcpc_changed_ifindex.patch",
    "content": "--- a/networking/udhcp/dhcpc.c\n+++ b/networking/udhcp/dhcpc.c\n@@ -1384,6 +1384,12 @@ int udhcpc_main(int argc UNUSED_PARAM, c\n \t\tstruct pollfd pfds[2];\n \t\tstruct dhcp_packet packet;\n \n+\t\t/* When running on a bridge, the ifindex may have changed (e.g. if\n+\t\t * member interfaces were added/removed or if the status of the\n+\t\t * bridge changed).\n+\t\t * Workaround: refresh it here before processing the next packet */\n+\t\tudhcp_read_interface(client_data.interface, &client_data.ifindex, NULL, client_data.client_mac);\n+\n \t\t//bb_error_msg(\"sockfd:%d, listen_mode:%d\", client_data.sockfd, client_data.listen_mode);\n \n \t\t/* Was opening raw or udp socket here\n"
  },
  {
    "path": "package/utils/busybox/patches/210-add_netmsg_util.patch",
    "content": "--- /dev/null\n+++ b/networking/netmsg.c\n@@ -0,0 +1,76 @@\n+/*\n+ * Copyright (C) 2006 Felix Fietkau <nbd@nbd.name>\n+ *\n+ * This is free software, licensed under the GNU General Public License v2.\n+ */\n+\n+//config:config NETMSG\n+//config:\tbool \"netmsg\"\n+//config:\tdefault n\n+//config:\thelp\n+//config:\t  simple program for sending udp broadcast messages\n+\n+//applet:IF_NETMSG(APPLET(netmsg, BB_DIR_BIN, BB_SUID_REQUIRE))\n+\n+//kbuild:lib-$(CONFIG_NETMSG) += netmsg.o\n+\n+//usage:#define netmsg_trivial_usage NOUSAGE_STR\n+//usage:#define netmsg_full_usage \"\"\n+\n+#include <sys/types.h>\n+#include <sys/socket.h>\n+#include <netinet/in.h>\n+#include <netdb.h>\n+#include <stdio.h>\n+#include <stdlib.h>\n+#include <string.h>\n+#include \"busybox.h\"\n+\n+#ifndef CONFIG_NETMSG\n+int main(int argc, char **argv)\n+#else\n+int netmsg_main(int argc, char **argv)\n+#endif\n+{\n+\tint s;\n+\tstruct sockaddr_in addr;\n+\tint optval = 1;\n+\tunsigned char buf[1001];\n+\n+\tif (argc != 3) {\n+\t\tfprintf(stderr, \"usage: %s <ip> \\\"<message>\\\"\\n\", argv[0]);\n+\t\texit(1);\n+\t}\n+\n+\tif ((s = socket(AF_INET, SOCK_DGRAM, 0)) < 0) {\n+\t\tperror(\"Opening socket\");\n+\t\texit(1);\n+\t}\n+\n+\tmemset(&addr, 0, sizeof(addr));\n+\taddr.sin_family = AF_INET;\n+\taddr.sin_addr.s_addr = inet_addr(argv[1]);\n+\taddr.sin_port = htons(0x1337);\n+\n+\tmemset(buf, 0, 1001);\n+\tbuf[0] = 0xde;\n+\tbuf[1] = 0xad;\n+\n+\tstrncpy(buf + 2, argv[2], 998);\n+\n+\tif (setsockopt (s, SOL_SOCKET, SO_BROADCAST, (caddr_t) &optval, sizeof (optval)) < 0) {\n+\t\tperror(\"setsockopt()\");\n+\t\tgoto fail;\n+\t}\n+\n+\tif (sendto(s, buf, 1001, 0, (struct sockaddr *) &addr, sizeof(addr)) < 0) {\n+\t\tperror(\"sendto()\");\n+\t\tgoto fail;\n+\t}\n+\n+\treturn 0;\n+\n+fail:\n+\tclose(s);\n+\texit(1);\n+}\n"
  },
  {
    "path": "package/utils/busybox/patches/220-add_lock_util.patch",
    "content": "--- /dev/null\n+++ b/miscutils/lock.c\n@@ -0,0 +1,155 @@\n+/*\n+ * Copyright (C) 2006 Felix Fietkau <nbd@nbd.name>\n+ *\n+ * This is free software, licensed under the GNU General Public License v2.\n+ */\n+\n+//config:config LOCK\n+//config:\tbool \"lock\"\n+//config:\tdefault n\n+//config:\thelp\n+//config:\t  Small utility for using locks in scripts\n+\n+//applet:IF_LOCK(APPLET(lock, BB_DIR_BIN, BB_SUID_DROP))\n+\n+//kbuild:lib-$(CONFIG_LOCK) += lock.o\n+\n+//usage:#define lock_trivial_usage NOUSAGE_STR\n+//usage:#define lock_full_usage \"\"\n+\n+#include <sys/types.h>\n+#include <sys/file.h>\n+#include <sys/stat.h>\n+#include <signal.h>\n+#include <fcntl.h>\n+#include <unistd.h>\n+#include <stdio.h>\n+#include \"busybox.h\"\n+\n+static int unlock = 0;\n+static int shared = 0;\n+static int waitonly = 0;\n+static int try_lock = 0;\n+static int fd;\n+static char *file;\n+\n+static void usage(char *name)\n+{\n+\tfprintf(stderr, \"Usage: %s [-suw] <filename>\\n\"\n+\t                \"\t-s\tUse shared locking\\n\"\n+\t                \"\t-u\tUnlock\\n\"\n+\t                \"\t-w\tWait for the lock to become free, don't acquire lock\\n\"\n+\t\t\t\"\t-n\tDon't wait for the lock to become free. Fail with exit code\\n\"\n+\t\t\t\t\t\"\\n\", name);\n+\texit(1);\n+}\n+\n+static void exit_unlock(int sig)\n+{\n+\tflock(fd, LOCK_UN);\n+\texit(0);\n+}\n+\n+static int do_unlock(void)\n+{\n+\tFILE *f;\n+\tint i;\n+\n+\tif ((f = fopen(file, \"r\")) == NULL)\n+\t\treturn 0;\n+\n+\tfscanf(f, \"%d\", &i);\n+\tif (i > 0)\n+\t\tkill(i, SIGTERM);\n+\n+\tfclose(f);\n+\n+\treturn 0;\n+}\n+\n+static int do_lock(void)\n+{\n+\tpid_t pid;\n+\tint flags;\n+\tchar pidstr[12];\n+\n+\tif ((fd = open(file, O_RDWR | O_CREAT | O_EXCL, 0700)) < 0) {\n+\t\tif ((fd = open(file, O_RDWR)) < 0) {\n+\t\t\tfprintf(stderr, \"Can't open %s\\n\", file);\n+\t\t\treturn 1;\n+\t\t}\n+\t}\n+\n+\tflags = shared ? LOCK_SH : LOCK_EX;\n+\tflags |= try_lock ? LOCK_NB : 0;\n+\n+\tif (flock(fd, flags) < 0) {\n+\t\tfprintf(stderr, \"Can't lock %s\\n\", file);\n+\t\treturn 1;\n+\t}\n+\n+\tpid = fork();\n+\n+\tif (pid < 0)\n+\t\treturn -1;\n+\n+\tif (pid == 0) {\n+\t\tsignal(SIGKILL, exit_unlock);\n+\t\tsignal(SIGTERM, exit_unlock);\n+\t\tsignal(SIGINT, exit_unlock);\n+\t\tif (waitonly)\n+\t\t\texit_unlock(0);\n+\t\telse\n+\t\t\twhile (1)\n+\t\t\t\tsleep(1);\n+\t} else {\n+\t\tif (!waitonly) {\n+\t\t\tlseek(fd, 0, SEEK_SET);\n+\t\t\tftruncate(fd, 0);\n+\t\t\tsnprintf(pidstr, sizeof(pidstr), \"%d\\n\", pid);\n+\t\t\twrite(fd, pidstr, strlen(pidstr));\n+\t\t\tclose(fd);\n+\t\t}\n+\n+\t\treturn 0;\n+\t}\n+\treturn 0;\n+}\n+\n+int lock_main(int argc, char **argv) MAIN_EXTERNALLY_VISIBLE;\n+int lock_main(int argc, char **argv)\n+{\n+\tchar **args = &argv[1];\n+\tint c = argc - 1;\n+\n+\twhile ((*args != NULL) && (*args)[0] == '-') {\n+\t\tchar *ch = *args;\n+\t\twhile (*(++ch) > 0) {\n+\t\t\tswitch(*ch) {\n+\t\t\t\tcase 'w':\n+\t\t\t\t\twaitonly = 1;\n+\t\t\t\t\tbreak;\n+\t\t\t\tcase 's':\n+\t\t\t\t\tshared = 1;\n+\t\t\t\t\tbreak;\n+\t\t\t\tcase 'u':\n+\t\t\t\t\tunlock = 1;\n+\t\t\t\t\tbreak;\n+\t\t\t\tcase 'n':\n+\t\t\t\t\ttry_lock = 1;\n+\t\t\t\t\tbreak;\n+\t\t\t}\n+\t\t}\n+\t\tc--;\n+\t\targs++;\n+\t}\n+\n+\tif (c != 1)\n+\t\tusage(argv[0]);\n+\n+\tfile = *args;\n+\tif (unlock)\n+\t\treturn do_unlock();\n+\telse\n+\t\treturn do_lock();\n+}\n"
  },
  {
    "path": "package/utils/busybox/patches/270-libbb_make_unicode_printable.patch",
    "content": "--- a/libbb/printable_string.c\n+++ b/libbb/printable_string.c\n@@ -28,8 +28,6 @@ const char* FAST_FUNC printable_string2(\n \t\t}\n \t\tif (c < ' ')\n \t\t\tbreak;\n-\t\tif (c >= 0x7f)\n-\t\t\tbreak;\n \t\ts++;\n \t}\n \n@@ -42,7 +40,7 @@ const char* FAST_FUNC printable_string2(\n \t\t\tunsigned char c = *d;\n \t\t\tif (c == '\\0')\n \t\t\t\tbreak;\n-\t\t\tif (c < ' ' || c >= 0x7f)\n+\t\t\tif (c < ' ')\n \t\t\t\t*d = '?';\n \t\t\td++;\n \t\t}\n"
  },
  {
    "path": "package/utils/busybox/patches/301-ip-link-fix-netlink-msg-size.patch",
    "content": "--- a/networking/libiproute/iplink.c\n+++ b/networking/libiproute/iplink.c\n@@ -683,7 +683,7 @@ static int do_add_or_delete(char **argv,\n \t}\n \txrtnl_open(&rth);\n \tll_init_map(&rth);\n-\tif (type_str) {\n+\tif (type_str && rtm == RTM_NEWLINK) {\n \t\tstruct rtattr *linkinfo = NLMSG_TAIL(&req.n);\n \n \t\taddattr_l(&req.n, sizeof(req), IFLA_LINKINFO, NULL, 0);\n"
  },
  {
    "path": "package/utils/busybox/patches/500-move-traceroute-applets-to-bin.patch",
    "content": "--- a/networking/traceroute.c\n+++ b/networking/traceroute.c\n@@ -236,8 +236,8 @@\n //config:\tdepends on TRACEROUTE || TRACEROUTE6\n \n /* Needs socket(AF_INET, SOCK_RAW, IPPROTO_ICMP), therefore BB_SUID_MAYBE: */\n-//applet:IF_TRACEROUTE(APPLET(traceroute, BB_DIR_USR_BIN, BB_SUID_MAYBE))\n-//applet:IF_TRACEROUTE6(APPLET(traceroute6, BB_DIR_USR_BIN, BB_SUID_MAYBE))\n+//applet:IF_TRACEROUTE(APPLET(traceroute, BB_DIR_BIN, BB_SUID_MAYBE))\n+//applet:IF_TRACEROUTE6(APPLET(traceroute6, BB_DIR_BIN, BB_SUID_MAYBE))\n \n //kbuild:lib-$(CONFIG_TRACEROUTE) += traceroute.o\n //kbuild:lib-$(CONFIG_TRACEROUTE6) += traceroute.o\n"
  },
  {
    "path": "package/utils/busybox/patches/510-move-passwd-applet-to-bin.patch",
    "content": "--- a/loginutils/passwd.c\n+++ b/loginutils/passwd.c\n@@ -23,7 +23,7 @@\n //config:\tWith this option passwd will refuse new passwords which are \"weak\".\n \n //applet:/* Needs to be run by root or be suid root - needs to change /etc/{passwd,shadow}: */\n-//applet:IF_PASSWD(APPLET(passwd, BB_DIR_USR_BIN, BB_SUID_REQUIRE))\n+//applet:IF_PASSWD(APPLET(passwd, BB_DIR_BIN, BB_SUID_REQUIRE))\n \n //kbuild:lib-$(CONFIG_PASSWD) += passwd.o\n \n"
  },
  {
    "path": "package/utils/busybox/patches/520-loginutils-handle-crypt-failures.patch",
    "content": "--- a/loginutils/chpasswd.c\n+++ b/loginutils/chpasswd.c\n@@ -89,6 +89,11 @@ int chpasswd_main(int argc UNUSED_PARAM,\n \n \t\t\tcrypt_make_pw_salt(salt, algo);\n \t\t\tfree_me = pass = pw_encrypt(pass, salt, 0);\n+\n+\t\t\tif (pass[0] == 0) {\n+\t\t\t\tfree(free_me);\n+\t\t\t\tbb_perror_msg_and_die(\"password encryption failed\");\n+\t\t\t}\n \t\t}\n \n \t\t/* This is rather complex: if user is not found in /etc/shadow,\n--- a/loginutils/cryptpw.c\n+++ b/loginutils/cryptpw.c\n@@ -87,7 +87,7 @@ int cryptpw_main(int argc UNUSED_PARAM,\n \t/* Supports: cryptpw -m sha256 PASS 'rounds=999999999$SALT' */\n \tchar salt[MAX_PW_SALT_LEN + sizeof(\"rounds=999999999$\")];\n \tchar *salt_ptr;\n-\tchar *password;\n+\tchar *password, *hash;\n \tconst char *opt_m, *opt_S;\n \tint fd;\n \n@@ -132,8 +132,12 @@ int cryptpw_main(int argc UNUSED_PARAM,\n \t\t/* may still be NULL on EOF/error */\n \t}\n \n-\tif (password)\n-\t\tputs(pw_encrypt(password, salt, 1));\n+\tif (password) {\n+\t\thash = pw_encrypt(password, salt, 1);\n+\t\tif (hash[0] == 0)\n+\t\t\tbb_perror_msg_and_die(\"password encryption failed\");\n+\t\tputs(hash);\n+\t}\n \n \treturn EXIT_SUCCESS;\n }\n--- a/loginutils/passwd.c\n+++ b/loginutils/passwd.c\n@@ -187,6 +187,10 @@ int passwd_main(int argc UNUSED_PARAM, c\n \t\tif (!newp) {\n \t\t\tlogmode = LOGMODE_STDIO;\n \t\t\tbb_error_msg_and_die(\"password for %s is unchanged\", name);\n+\t\t} else if (newp[0] == 0) {\n+\t\t\tlogmode = LOGMODE_STDIO;\n+\t\t\tfree(newp);\n+\t\t\tbb_perror_msg_and_die(\"password encryption failed\");\n \t\t}\n \t} else if (opt & OPT_lock) {\n \t\tif (!c)\n"
  },
  {
    "path": "package/utils/busybox/selinux.config",
    "content": "CONFIG_SELINUX=y\nCONFIG_FEATURE_TAR_SELINUX=y\nCONFIG_CHCON=y\nCONFIG_GETENFORCE=y\nCONFIG_GETSEBOOL=y\nCONFIG_LOAD_POLICY=y\nCONFIG_MATCHPATHCON=y\nCONFIG_RUNCON=y\nCONFIG_SELINUXENABLED=y\nCONFIG_SESTATUS=y\nCONFIG_SETFILES=y\nCONFIG_FEATURE_SETFILES_CHECK_OPTION=y\nCONFIG_RESTORECON=y\nCONFIG_SETSEBOOL=y\nCONFIG_SETENFORCE=y\n"
  },
  {
    "path": "package/utils/bzip2/Makefile",
    "content": "#\n# Copyright (C) 2007-2008 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=bzip2\nPKG_VERSION:=1.0.8\nPKG_RELEASE:=1\n\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz\nPKG_SOURCE_URL:=https://sourceware.org/pub/bzip2\nPKG_HASH:=ab5a03176ee106d3f0fa90e381da478ddae405918153cca248e682cd0c4a2269\n\nPKG_MAINTAINER:=Steven Barth <cyrus@openwrt.org>\nPKG_LICENSE:=bzip2-1.0.8\nPKG_LICENSE_FILES:=LICENSE\nPKG_CPE_ID:=cpe:/a:bzip:bzip2\n\ninclude $(INCLUDE_DIR)/host-build.mk\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine Package/bzip2/Default\n  SUBMENU:=Compression\n  URL:=https://sourceware.org/bzip2/\nendef\n\ndefine Package/libbz2\n$(call Package/bzip2/Default)\n  SECTION:=libs\n  CATEGORY:=Libraries\n  DEPENDS:=\n  TITLE:=bzip2 library.\n  ABI_VERSION:=1.0\nendef\n\ndefine Package/libbz2/description\n\tbzip2 is a freely available, patent free, high-quality\n\tdata compressor. This packages provides libbz2 library.\nendef\n\ndefine Package/bzip2\n$(call Package/bzip2/Default)\n  SECTION:=utils\n  CATEGORY:=Utilities\n  DEPENDS:=+libbz2\n  TITLE:=bzip2 is a compression utility.\nendef\n\ndefine Package/bzip2/description\n\tbzip2 is a freely available, patent free, high-quality\n\tdata compressor. This package provides the binary.\nendef\n\nTARGET_CFLAGS += \\\n\t$(FPIC)\n\nCONFIGURE_ARGS += --prefix=/usr\n\nMAKE_FLAGS += \\\n\t-f Makefile-libbz2_so \\\n\tCFLAGS=\"$(TARGET_CFLAGS)\" \\\n\tLDFLAGS=\"$(TARGET_LDFLAGS)\" \\\n\tall\n\ndefine Build/InstallDev\n\t$(INSTALL_DIR) $(1)/usr/include\n\t$(CP) $(PKG_BUILD_DIR)/bzlib.h $(1)/usr/include/\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(CP) $(PKG_BUILD_DIR)/libbz2.so.$(PKG_VERSION) $(1)/usr/lib/\n\t$(LN) libbz2.so.$(PKG_VERSION) $(1)/usr/lib/libbz2.so.1.0\n\t$(LN) libbz2.so.$(PKG_VERSION) $(1)/usr/lib/libbz2.so\nendef\n\ndefine Package/libbz2/install\n\t$(INSTALL_DIR) $(1)/usr/lib/\n\t$(CP) $(PKG_BUILD_DIR)/libbz2.so.$(PKG_VERSION) $(1)/usr/lib/\n\t$(LN) libbz2.so.$(PKG_VERSION) $(1)/usr/lib/libbz2.so.1.0\nendef\n\ndefine Package/bzip2/install\n\t$(INSTALL_DIR) $(1)/usr/bin/\n\t$(INSTALL_BIN) $(PKG_BUILD_DIR)/bzip2-shared $(1)/usr/bin/bzip2\n\t$(INSTALL_DIR) $(1)/bin/\n\t$(LN) ../usr/bin/bzip2 $(1)/bin/bzip2\nendef\n\nHOST_CFLAGS += \\\n\t$(FPIC)\n\nHOST_MAKE_FLAGS+= \\\n\tCFLAGS=\"$(HOST_CFLAGS)\" \\\n\tLDFLAGS=\"$(HOST_LDFLAGS)\" \\\n\tall\n\nHOST_CONFIGURE_ARGS+= \\\n\t--prefix=$(STAGING_DIR_HOSTPKG)\n\ndefine Host/Install\n\t$(INSTALL_DIR) $(STAGING_DIR_HOSTPKG)/bin/\n\t$(MAKE) -C $(HOST_BUILD_DIR) PREFIX=$(STAGING_DIR_HOSTPKG)/ install\nendef\n\n$(eval $(call HostBuild))\n\n$(eval $(call BuildPackage,libbz2))\n$(eval $(call BuildPackage,bzip2))\n"
  },
  {
    "path": "package/utils/bzip2/patches/020-no-utime.patch",
    "content": "--- a/bzip2.c\n+++ b/bzip2.c\n@@ -69,7 +69,6 @@\n #if BZ_UNIX\n #   include <fcntl.h>\n #   include <sys/types.h>\n-#   include <utime.h>\n #   include <unistd.h>\n #   include <sys/stat.h>\n #   include <sys/times.h>\n@@ -1051,12 +1050,12 @@ void applySavedTimeInfoToOutputFile ( Ch\n {\n #  if BZ_UNIX\n    IntNative      retVal;\n-   struct utimbuf uTimBuf;\n+   struct timespec uTimBuf[2] = {};\n \n-   uTimBuf.actime = fileMetaInfo.st_atime;\n-   uTimBuf.modtime = fileMetaInfo.st_mtime;\n+   uTimBuf[0].tv_sec = fileMetaInfo.st_atime;\n+   uTimBuf[1].tv_sec = fileMetaInfo.st_mtime;\n \n-   retVal = utime ( dstName, &uTimBuf );\n+   retVal = utimensat ( AT_FDCWD, dstName, uTimBuf , 0 );\n    ERROR_IF_NOT_ZERO ( retVal );\n #  endif\n }\n"
  },
  {
    "path": "package/utils/bzip2/patches/021-fix-LDFLAGS.patch",
    "content": "--- a/Makefile-libbz2_so\n+++ b/Makefile-libbz2_so\n@@ -35,7 +35,7 @@ OBJS= blocksort.o  \\\n       bzlib.o\n \n all: $(OBJS)\n-\t$(CC) -shared -Wl,-soname -Wl,libbz2.so.1.0 -o libbz2.so.1.0.8 $(OBJS)\n+\t$(CC) -shared -Wl,-soname -Wl,libbz2.so.1.0 $(LDFLAGS) -o libbz2.so.1.0.8 $(OBJS)\n \t$(CC) $(CFLAGS) -o bzip2-shared bzip2.c libbz2.so.1.0.8\n \trm -f libbz2.so.1.0\n \tln -s libbz2.so.1.0.8 libbz2.so.1.0\n"
  },
  {
    "path": "package/utils/checkpolicy/Makefile",
    "content": "#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=checkpolicy\nPKG_VERSION:=3.3\nPKG_RELEASE:=1\n\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz\nPKG_SOURCE_URL:=https://github.com/SELinuxProject/selinux/releases/download/$(PKG_VERSION)\nPKG_HASH:=25c84edfa3a10ab8cb073b97bc55cb66377532d54a2723da9accdabd05431485\nPKG_INSTALL:=1\nPKG_BUILD_DEPENDS:=libselinux\nHOST_BUILD_DEPENDS:=libselinux/host\n\nPKG_MAINTAINER:=Thomas Petazzoni <thomas.petazzoni@bootlin.com>\nPKG_CPE_ID:=cpe:/a:selinuxproject:checkpolicy\nPKG_LICENSE:=GPL-2.0-or-later\nPKG_LICENSE_FILES:=COPYING\n\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine Package/checkpolicy\n  SECTION:=utils\n  CATEGORY:=Utilities\n  TITLE:=SELinux policy compiler\n  URL:=http://selinuxproject.org/page/Main_Page\nendef\n\ndefine Package/checkpolicy/description\n\tcheckpolicy is the SELinux policy compiler. It uses libsepol\n\tto generate the binary policy. checkpolicy uses the static\n\tlibsepol since it deals with low level details of the policy\n\tthat have not been encapsulated/abstracted by a proper\n\tshared library interface.\nendef\n\ninclude $(INCLUDE_DIR)/host-build.mk\n\nHOST_MAKE_FLAGS += \\\n\tPREFIX=$(STAGING_DIR_HOSTPKG)\n\ndefine Package/checkpolicy/install\n\t$(INSTALL_DIR) $(1)/usr/bin\n\t$(CP) $(PKG_INSTALL_DIR)/usr/bin/* $(1)/usr/bin/\nendef\n\n$(eval $(call HostBuild))\n$(eval $(call BuildPackage,checkpolicy))\n"
  },
  {
    "path": "package/utils/ct-bugcheck/Makefile",
    "content": "#\n# Copyright (C) 2016 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\ninclude $(INCLUDE_DIR)/kernel.mk\n\nPKG_NAME:=ct-bugcheck\nPKG_RELEASE:=2016-07-21\n\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine Package/ct-bugcheck\n  SECTION:=utils\n  CATEGORY:=Utilities\n  TITLE:=Bug checking and reporting utility\n  VERSION:=$(PKG_RELEASE)\n  MAINTAINER:=Ben Greear <greearb@candelatech.com>\nendef\n\ndefine Package/ct-bugcheck/description\n  Scripts to check for bugs (like firmware crashes) and package them for reporting.\n  Currently this script only checks for ath10k firmware crashes.\n  Once installed, you can enable this tool by creating a file called\n  /etc/config/bugcheck with the following contents:\n DO_BUGCHECK=1\n export DO_BUGCHECK\n\nendef\n\ndefine Build/Prepare\n\t$(CP) src/bugcheck.sh $(PKG_BUILD_DIR)/\n\t$(CP) src/bugchecker.sh $(PKG_BUILD_DIR)/\n\t$(CP) src/bugcheck.initd $(PKG_BUILD_DIR)/\nendef\n\ndefine Build/Compile\n\ttrue\nendef\n\ndefine Package/ct-bugcheck/install\n\t$(INSTALL_DIR) $(1)/usr/bin\n\t$(INSTALL_DIR) $(1)/etc/init.d\n\t$(INSTALL_BIN) $(PKG_BUILD_DIR)/bugcheck.sh $(1)/usr/bin/\n\t$(INSTALL_BIN) $(PKG_BUILD_DIR)/bugchecker.sh $(1)/usr/bin/\n\t$(INSTALL_BIN) $(PKG_BUILD_DIR)/bugcheck.initd $(1)/etc/init.d/bugcheck\nendef\n\n$(eval $(call BuildPackage,ct-bugcheck))\n"
  },
  {
    "path": "package/utils/ct-bugcheck/src/bugcheck.initd",
    "content": "#!/bin/sh /etc/rc.common\n# Copyright (C) 2016 OpenWrt.org\n\nSTART=99\n\nUSE_PROCD=1\nPROG=/usr/bin/bugchecker.sh\n\n# To actually make bugchecker.sh run, see comments\n# at top of its file.\n\nstart_service () {\n        procd_open_instance\n        procd_set_param command \"$PROG\"\n        procd_close_instance\n}\n"
  },
  {
    "path": "package/utils/ct-bugcheck/src/bugcheck.sh",
    "content": "#!/bin/sh\n\n# Check for ath10k (and maybe other) bugs, package them up,\n# and let user know what to do with them.\n\nTMPLOC=/tmp\nCRASHDIR=$TMPLOC/bugcheck\nFOUND_BUG=0\n\n# set -x\n\nbugcheck_generic()\n{\n    echo \"OpenWrt crashlog report\" > $CRASHDIR/info.txt\n    date >> $CRASHDIR/info.txt\n    echo >> $CRASHDIR/info.txt\n    echo \"uname\" >> $CRASHDIR/info.txt\n    uname -a >> $CRASHDIR/info.txt\n    echo >> $CRASHDIR/info.txt\n    echo \"os-release\" >> $CRASHDIR/info.txt\n    cat /etc/os-release >> $CRASHDIR/info.txt\n    echo >> $CRASHDIR/info.txt\n    echo \"os-release\" >> $CRASHDIR/info.txt\n    cat /etc/os-release >> $CRASHDIR/info.txt\n    echo >> $CRASHDIR/info.txt\n    echo \"dmesg output\" >> $CRASHDIR/info.txt\n    dmesg >> $CRASHDIR/info.txt\n    if [ -x /usr/bin/lspci ]\n\tthen\n\techo >> $CRASHDIR/info.txt\n\techo \"lspci\" >> $CRASHDIR/info.txt\n\tlspci >> $CRASHDIR/info.txt\n    fi\n    echo >> $CRASHDIR/info.txt\n    echo \"cpuinfo\" >> $CRASHDIR/info.txt\n    cat /proc/cpuinfo >> $CRASHDIR/info.txt\n    echo >> $CRASHDIR/info.txt\n    echo \"meminfo\" >> $CRASHDIR/info.txt\n    cat /proc/cpuinfo >> $CRASHDIR/info.txt\n    echo >> $CRASHDIR/info.txt\n    echo \"cmdline\" >> $CRASHDIR/info.txt\n    cat /proc/cmdline >> $CRASHDIR/info.txt\n    echo >> $CRASHDIR/info.txt\n    echo \"lsmod\" >> $CRASHDIR/info.txt\n    lsmod >> $CRASHDIR/info.txt\n}\n\nroll_crashes()\n{\n    # Roll any existing crashes\n    if [ -d $CRASHDIR ]\n\tthen\n\tif [ -d $CRASHDIR.1 ]\n\t    then\n\t    rm -fr $CRASHDIR.1\n\tfi\n\tmv $CRASHDIR $CRASHDIR.1\n    fi\n\n    # Prepare location\n    mkdir -p $CRASHDIR\n}\n\n# ath10k, check debugfs entries.\nfor i in /sys/kernel/debug/ieee80211/*/ath10k/fw_crash_dump\ndo\n  #echo \"Checking $i\"\n  if cat $i > $TMPLOC/ath10k_crash.bin 2>&1\n      then\n      FOUND_BUG=1\n\n      #echo \"Found ath10k crash data in $i\"\n      roll_crashes\n\n      ADIR=${i/fw_crash_dump/}\n\n      CTFW=0\n      if grep -- -ct- $TMPLOC/ath10k_crash.bin > /dev/null 2>&1\n\t  then\n\t  CTFW=1\n      fi\n\n      echo \"Send bug reports to:\" > $CRASHDIR/report_to.txt\n      if [ -f $ADIR/ct_special -o $CTFW == \"1\" ]\n\t  then\n\t  # Looks like this is CT firmware or driver...\n\t  echo \"greearb@candelatech.com\" >> $CRASHDIR/report_to.txt\n\t  echo \"and/or report or check for duplicates here:\" >> $CRASHDIR/report_to.txt\n\t  echo \"https://github.com/greearb/ath10k-ct/issues\" >> $CRASHDIR/report_to.txt\n      else\n\t  # Not sure who would want these bug reports for upstream...\n\t  echo \"https://openwrt.org/\" >> $CRASHDIR/report_to.txt\n      fi\n      echo >> $CRASHDIR/report_to.txt\n      echo \"Please attach all files in this directory to bug reports.\" >> $CRASHDIR/report_to.txt\n\n      mv $TMPLOC/ath10k_crash.bin $CRASHDIR\n\n      # Add any more ath10k specific stuff here.\n\n      # And call generic bug reporting logic\n      bugcheck_generic\n  fi\ndone\n\nif [ $FOUND_BUG == \"1\" ]\n    then\n    # Notify LUCI somehow?\n    echo \"bugcheck.sh found an issue to be reported\" > /dev/kmsg\n    echo \"See $CRASHDIR for details on how to report this\" > /dev/kmsg\n    # Let calling code know something was wrong.\n    exit 1\nfi\n\nexit 0\n"
  },
  {
    "path": "package/utils/ct-bugcheck/src/bugchecker.sh",
    "content": "#!/bin/sh\n\n# Periodically call bugcheck.sh script\n\nCHECKER=bugcheck.sh\nSLEEPFOR=60\n\nDO_BUGCHECK=0\n\n# So, to enable this, you create an /etc/config/bugcheck file\n# with contents like:\n#  DO_BUGCHECK=1\n#  export DO_BUGCHECK\n\nif [ -f /etc/config/bugcheck ]\n    then\n    . /etc/config/bugcheck\nfi\n\nif [ $DO_BUGCHECK == 0 ]\nthen\n    exit 0\nfi\n\nwhile true\n  do\n  $CHECKER\n  sleep $SLEEPFOR\ndone\n"
  },
  {
    "path": "package/utils/dtc/Makefile",
    "content": "# SPDX-License-Identifier: GPL-2.0\n#\n# Copyright (C) 2016-2019 Yousong Zhou <yszhou4tech@gmail.com>\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=dtc\nPKG_VERSION:=1.6.1\nPKG_RELEASE:=$(AUTORELEASE)\n\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz\nPKG_HASH:=65cec529893659a49a89740bb362f507a3b94fc8cd791e76a8d6a2b6f3203473\nPKG_SOURCE_URL:=@KERNEL/software/utils/dtc\n\nPKG_MAINTAINER:=Yousong Zhou <yszhou4tech@gmail.com>\nPKG_LICENSE:=GPL-2.0-only\nPKG_LICENSE_FILES:=GPL\n\nPKG_INSTALL:=1\n\ninclude $(INCLUDE_DIR)/package.mk\ninclude $(INCLUDE_DIR)/meson.mk\n\ndefine Package/dtc\n  SECTION:=utils\n  CATEGORY:=Utilities\n  TITLE:=Device Tree Compiler\n  URL:=https://git.kernel.org/pub/scm/utils/dtc/dtc.git\nendef\n\ndefine Package/dtc/description\n  Device Tree Compiler for Flat Device Trees Device Tree Compiler, dtc, takes\n  as input a device-tree in a given format and outputs a device-tree in another\n  format for booting kernels on embedded systems.\nendef\n\ndefine Package/dtc/install\n\t$(INSTALL_DIR) $(1)/usr/bin\n\t$(CP) $(PKG_INSTALL_DIR)/usr/bin/dtc $(1)/usr/bin\nendef\n\n\n# See Documentation/manual.txt for details about each utility\ndefine Package/fdt-utils\n  SECTION:=utils\n  CATEGORY:=Utilities\n  TITLE:=Flat Device Tree Utilities\n  URL:=https://git.kernel.org/pub/scm/utils/dtc/dtc.git\n  DEPENDS:=+libfdt\nendef\n\ndefine Package/fdt-utils/install\n\t$(INSTALL_DIR) $(1)/usr/bin\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/bin/convert-dtsv0 $(1)/usr/bin\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/bin/fdtdump $(1)/usr/bin\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/bin/fdtget $(1)/usr/bin\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/bin/fdtput $(1)/usr/bin\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/bin/fdtoverlay $(1)/usr/bin\nendef\n\n\ndefine Package/libfdt\n  SECTION:=libs\n  CATEGORY:=Libraries\n  TITLE:=a utility library for reading and manipulating dtb files\n  URL:=https://git.kernel.org/pub/scm/utils/dtc/dtc.git\nendef\n\ndefine Package/libfdt/description\n  This is a library containing functions for manipulating Flat Device Trees.\nendef\n\ndefine Package/libfdt/install\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/libfdt*.so* $(1)/usr/lib\nendef\n\nMESON_ARGS += \\\n\t-Dtools=true \\\n\t-Dyaml=disabled \\\n\t-Dvalgrind=disabled \\\n\t-Dpython=disabled\n\ndefine Build/InstallDev\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(INSTALL_DIR) $(1)/usr/include\n\t$(CP) $(PKG_INSTALL_DIR)/usr/include/* $(1)/usr/include\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/* $(1)/usr/lib\nendef\n\n$(eval $(call BuildPackage,dtc))\n$(eval $(call BuildPackage,fdt-utils))\n$(eval $(call BuildPackage,libfdt))\n"
  },
  {
    "path": "package/utils/dtc/patches/0001-Support-r-format-for-printing-raw-bytes-with-fdtget.patch",
    "content": "From 17739b7ef510917471409d71fb45d8eaf6a1e1fb Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Thu, 9 Dec 2021 07:14:20 +0100\nSubject: [PATCH] Support 'r' format for printing raw bytes with fdtget\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nFT is sometimes used for storing raw data. That is quite common for\nU-Boot FIT images.\n\nExtracting such data is not trivial currently. Using type 's' (string)\nwill replace every 0x00 (NUL) with 0x20 (space). Using type 'x' will\nprint bytes but in xxd incompatible format.\n\nThis commit adds support for 'r' (raw) format. Example usage:\nfdtget -t r firmware.itb /images/foo data > image.raw\n\nSupport for encoding isn't added as there isn't any clean way of passing\nbinary data as command line argument.\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nMessage-Id: <20211209061420.29466-1-zajec5@gmail.com>\nSigned-off-by: David Gibson <david@gibson.dropbear.id.au>\n---\n Documentation/manual.txt | 2 +-\n fdtget.c                 | 5 +++++\n fdtput.c                 | 2 ++\n tests/run_tests.sh       | 2 ++\n tests/utilfdt_test.c     | 5 ++++-\n util.c                   | 4 ++--\n util.h                   | 3 ++-\n 7 files changed, 18 insertions(+), 5 deletions(-)\n\n--- a/Documentation/manual.txt\n+++ b/Documentation/manual.txt\n@@ -712,7 +712,7 @@ The syntax of the fdtget command is:\n \n where options are:\n \n-    <type>    s=string, i=int, u=unsigned, x=hex\n+    <type>    s=string, i=int, u=unsigned, x=hex, r=raw\n         Optional modifier prefix:\n             hh or b=byte, h=2 byte, l=4 byte (default)\n \n--- a/fdtget.c\n+++ b/fdtget.c\n@@ -91,6 +91,11 @@ static int show_data(struct display_info\n \tif (len == 0)\n \t\treturn 0;\n \n+\tif (disp->type == 'r') {\n+\t\tfwrite(data, 1, len, stdout);\n+\t\treturn 0;\n+\t}\n+\n \tis_string = (disp->type) == 's' ||\n \t\t(!disp->type && util_is_printable_string(data, len));\n \tif (is_string) {\n--- a/fdtput.c\n+++ b/fdtput.c\n@@ -433,6 +433,8 @@ int main(int argc, char *argv[])\n \t\t\tif (utilfdt_decode_type(optarg, &disp.type,\n \t\t\t\t\t&disp.size))\n \t\t\t\tusage(\"Invalid type string\");\n+\t\t\tif (disp.type == 'r')\n+\t\t\t\tusage(\"Unsupported raw data type\");\n \t\t\tbreak;\n \n \t\tcase 'v':\n--- a/tests/run_tests.sh\n+++ b/tests/run_tests.sh\n@@ -852,6 +852,8 @@ fdtget_tests () {\n     run_fdtget_test 8000 -tx $dtb /cpus/PowerPC,970@1 d-cache-size\n     run_fdtget_test \"61 62 63 0\" -tbx $dtb /randomnode tricky1\n     run_fdtget_test \"a b c d de ea ad be ef\" -tbx $dtb /randomnode blob\n+    run_fdtget_test \"MyBoardName\\0MyBoardFamilyName\\0\" -tr $dtb / compatible\n+    run_fdtget_test \"\\x0a\\x0b\\x0c\\x0d\\xde\\xea\\xad\\xbe\\xef\" -tr $dtb /randomnode blob\n \n     # Here the property size is not a multiple of 4 bytes, so it should fail\n     run_wrap_error_test $DTGET -tlx $dtb /randomnode mixed\n--- a/tests/utilfdt_test.c\n+++ b/tests/utilfdt_test.c\n@@ -73,6 +73,9 @@ static void check_sizes(char *modifier,\n \n \t*ptr = 's';\n \tcheck(fmt, 's', -1);\n+\n+\t*ptr = 'r';\n+\tcheck(fmt, 'r', -1);\n }\n \n static void test_utilfdt_decode_type(void)\n@@ -90,7 +93,7 @@ static void test_utilfdt_decode_type(voi\n \t/* try every other character */\n \tcheckfail(\"\");\n \tfor (ch = ' '; ch < 127; ch++) {\n-\t\tif (!strchr(\"iuxs\", ch)) {\n+\t\tif (!strchr(\"iuxsr\", ch)) {\n \t\t\t*fmt = ch;\n \t\t\tfmt[1] = '\\0';\n \t\t\tcheckfail(fmt);\n--- a/util.c\n+++ b/util.c\n@@ -353,11 +353,11 @@ int utilfdt_decode_type(const char *fmt,\n \t}\n \n \t/* we should now have a type */\n-\tif ((*fmt == '\\0') || !strchr(\"iuxs\", *fmt))\n+\tif ((*fmt == '\\0') || !strchr(\"iuxsr\", *fmt))\n \t\treturn -1;\n \n \t/* convert qualifier (bhL) to byte size */\n-\tif (*fmt != 's')\n+\tif (*fmt != 's' && *fmt != 'r')\n \t\t*size = qualifier == 'b' ? 1 :\n \t\t\t\tqualifier == 'h' ? 2 :\n \t\t\t\tqualifier == 'l' ? 4 : -1;\n--- a/util.h\n+++ b/util.h\n@@ -143,6 +143,7 @@ int utilfdt_write_err(const char *filena\n  *\t\ti\tsigned integer\n  *\t\tu\tunsigned integer\n  *\t\tx\thex\n+ *\t\tr\traw\n  *\n  * TODO: Implement ll modifier (8 bytes)\n  * TODO: Implement o type (octal)\n@@ -160,7 +161,7 @@ int utilfdt_decode_type(const char *fmt,\n  */\n \n #define USAGE_TYPE_MSG \\\n-\t\"<type>\\ts=string, i=int, u=unsigned, x=hex\\n\" \\\n+\t\"<type>\\ts=string, i=int, u=unsigned, x=hex, r=raw\\n\" \\\n \t\"\\tOptional modifier prefix:\\n\" \\\n \t\"\\t\\thh or b=byte, h=2 byte, l=4 byte (default)\";\n \n"
  },
  {
    "path": "package/utils/e2fsprogs/Makefile",
    "content": "#\n# Copyright (C) 2006-2014 OpenWrt.org\n# Copyright 2010 Vertical Communications\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=e2fsprogs\nPKG_VERSION:=1.46.5\nPKG_RELEASE:=1\n\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz\nPKG_SOURCE_URL:=@KERNEL/linux/kernel/people/tytso/e2fsprogs/v$(PKG_VERSION)/\nPKG_HASH:=2f16c9176704cf645dc69d5b15ff704ae722d665df38b2ed3cfc249757d8d81e\n\nPKG_LICENSE:=GPL-2.0\nPKG_LICENSE_FILES:=NOTICE\nPKG_CPE_ID:=cpe:/a:e2fsprogs_project:e2fsprogs\n\nPKG_BUILD_DEPENDS:=util-linux e2fsprogs/host\nPKG_INSTALL:=1\n\nPKG_BUILD_PARALLEL:=1\n\ninclude $(INCLUDE_DIR)/package.mk\ninclude $(INCLUDE_DIR)/host-build.mk\n\ndefine Package/e2fsprogs\n  SECTION:=utils\n  CATEGORY:=Utilities\n  SUBMENU:=Filesystem\n  TITLE:=Ext2/3/4 filesystem utilities\n  URL:=http://e2fsprogs.sourceforge.net/\n  DEPENDS:=+libuuid +libext2fs\nendef\n\ndefine Package/e2fsprogs/description\n This package contains essential ext2 filesystem utilities which consists of\n e2fsck, mke2fs and most of the other core ext2 filesystem utilities.\nendef\n\ndefine Package/libext2fs\n  SECTION:=libs\n  CATEGORY:=Libraries\n  TITLE:=ext2/3/4 filesystem library\n  URL:=http://e2fsprogs.sourceforge.net/\n  DEPENDS:=+libuuid +libblkid +libss +libcomerr\n  ABI_VERSION:=2\nendef\n\ndefine Package/libext2fs/description\n libext2fs is a library which can access ext2, ext3 and ext4 filesystems.\nendef\n\ndefine Package/libss\n  SECTION:=libs\n  CATEGORY:=Libraries\n  TITLE:=command-line interface parsing library\n  URL:=http://e2fsprogs.sourceforge.net/\n  DEPENDS:=+libcomerr\n  ABI_VERSION:=2\nendef\n\ndefine Package/libss/description\n  This pacakge contains libss, a command-line interface parsing library\n  bundled with e2fsprogs.\nendef\n\ndefine Package/libcomerr\n  SECTION:=libs\n  CATEGORY:=Libraries\n  TITLE:=common error description library\n  URL:=http://e2fsprogs.sourceforge.net/\n  DEPENDS:=+libuuid\n  ABI_VERSION:=0\nendef\n\ndefine Package/libcomerr/description\n  This package contains libcom_err, the common error description library\n  bundled with e2fsprogs.\nendef\n\ndefine Package/tune2fs\n$(call Package/e2fsprogs)\n  TITLE:=Ext2 Filesystem tune utility\n  DEPENDS:= +e2fsprogs\nendef\n\ndefine Package/resize2fs\n$(call Package/e2fsprogs)\n  TITLE:=Ext2 Filesystem resize utility\n  DEPENDS:= +e2fsprogs\nendef\n\ndefine Package/badblocks\n$(call Package/e2fsprogs)\n  TITLE:=Ext2 Filesystem badblocks utility\n  DEPENDS:= +e2fsprogs\nendef\n\ndefine Package/dumpe2fs\n$(call Package/e2fsprogs)\n  TITLE:=Ext2 Filesystem information dumping utility\n  DEPENDS:= +e2fsprogs\nendef\n\ndefine Package/e2freefrag\n$(call Package/e2fsprogs)\n  TITLE:=Ext2 Filesystem free space fragmentation information utility\n  DEPENDS:= +e2fsprogs\nendef\n\ndefine Package/e4crypt\n$(call Package/e2fsprogs)\n  TITLE:=Ext4 Filesystem encryption utility\n  DEPENDS:= +e2fsprogs\nendef\n\ndefine Package/filefrag\n$(call Package/e2fsprogs)\n  TITLE:=Ext2 Filesystem file fragmentation report utility\n  DEPENDS:= +e2fsprogs\nendef\n\ndefine Package/debugfs\n$(call Package/e2fsprogs)\n  TITLE:=Ext2 Filesystem debugger\n  DEPENDS:= +e2fsprogs\nendef\n\ndefine Package/chattr\n$(call Package/e2fsprogs)\n  TITLE:=Ext2 Filesystem chattr utility\n  DEPENDS:= +e2fsprogs\nendef\n\ndefine Package/lsattr\n$(call Package/e2fsprogs)\n  TITLE:=Ext2 Filesystem lsattr utility\n  DEPENDS:= +e2fsprogs\nendef\n\nTARGET_CFLAGS += $(FPIC) -ffunction-sections -fdata-sections -flto\n\nTARGET_LDFLAGS += $(if $(CONFIG_USE_GLIBC),-lrt)\nTARGET_LDFLAGS += -flto\n\nCONFIGURE_ARGS += \\\n\t--disable-testio-debug \\\n\t--enable-elf-shlibs\t\\\n\t--disable-libuuid\t\\\n\t--disable-libblkid\t\\\n\t--disable-uuidd\t\t\\\n\t--disable-tls\t\t\\\n\t--disable-nls\t\t\\\n\t--disable-rpath\t\t\\\n\t--disable-fuse2fs\n\ndefine Build/Prepare\n\t$(call Build/Prepare/Default)\n\t$(CP) $(SCRIPT_DIR)/config.{guess,sub} $(PKG_BUILD_DIR)/config/\nendef\n\ndefine Build/Compile\n\t+$(MAKE) $(PKG_JOBS) -C $(PKG_BUILD_DIR)/util \\\n\t\tBUILDCC=\"$(HOSTCC)\" \\\n\t\tCFLAGS=\"\" \\\n\t\tCPPFLAGS=\"\" \\\n\t\tLDFLAGS=\"\" \\\n\t\tV=$(if $(findstring c,$(OPENWRT_VERBOSE)),1,) \\\n\t\tsubst\n\t+$(MAKE) $(PKG_JOBS) -C $(PKG_BUILD_DIR) \\\n\t\tLDFLAGS=-Wl,--gc-sections \\\n\t\tBUILDCC=\"$(HOSTCC)\" \\\n\t\tDESTDIR=\"$(PKG_INSTALL_DIR)\" \\\n\t\tELF_OTHER_LIBS=\"$(TARGET_LDFLAGS) -luuid\" \\\n\t\tSYSLIBS=\"$(TARGET_LDFLAGS) -ldl -L$(PKG_BUILD_DIR)/lib/ -l:libcom_err.so.0.0\" \\\n\t\tV=$(if $(findstring c,$(OPENWRT_VERBOSE)),1,) \\\n\t\tall\nendef\n\ndefine Build/InstallDev\n\t$(INSTALL_DIR) $(1)/usr/lib/pkgconfig\n\t$(CP) $(PKG_BUILD_DIR)/lib/ext2fs/ext2fs.pc $(1)/usr/lib/pkgconfig\n\t$(CP) $(PKG_BUILD_DIR)/lib/et/com_err.pc $(1)/usr/lib/pkgconfig\n\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(CP) $(PKG_BUILD_DIR)/lib/libext2fs.{so,a}* $(1)/usr/lib\n\t$(CP) $(PKG_BUILD_DIR)/lib/libcom_err.{so,a}* $(1)/usr/lib\n\t$(CP) $(PKG_BUILD_DIR)/lib/libss.{so,a}* $(1)/usr/lib\n\n\t$(INSTALL_DIR) $(1)/usr/include/ext2fs\n\t$(CP) $(PKG_BUILD_DIR)/lib/ext2fs/*.h $(1)/usr/include/ext2fs\n\t$(INSTALL_DIR) $(1)/usr/include/et\n\t$(INSTALL_BIN) $(PKG_BUILD_DIR)/lib/et/*.h $(1)/usr/include/et\n\t# Apparently there is some confusion\n\techo \"#include <et/com_err.h>\" > $(1)/usr/include/com_err.h\n\t$(INSTALL_DIR) $(1)/usr/include/ss\n\t$(CP) \\\n\t\t$(PKG_BUILD_DIR)/lib/ss/ss.h \\\n\t\t$(PKG_BUILD_DIR)/lib/ss/ss_err.h \\\n\t\t$(1)/usr/include/ss/\nendef\n\ndefine Host/Compile\n\t$(MAKE) $(PKG_JOBS) -C $(HOST_BUILD_DIR)/lib/ss mk_cmds\n\t$(MAKE) $(PKG_JOBS) -C $(HOST_BUILD_DIR)/lib/et compile_et\nendef\n\ndefine Host/Install\n\t$(INSTALL_DIR) $(1)/share/et\n\t$(CP) $(HOST_BUILD_DIR)/lib/et/et_[ch].awk $(1)/share/et/\n\t$(INSTALL_DIR) $(1)/share/ss\n\t$(CP) $(HOST_BUILD_DIR)/lib/ss/ct_c.{sed,awk} $(1)/share/ss/\n\t$(INSTALL_DIR) $(1)/bin\n\t$(CP) \\\n\t\t$(HOST_BUILD_DIR)/lib/et/compile_et \\\n\t\t$(HOST_BUILD_DIR)/lib/ss/mk_cmds \\\n\t\t$(1)/bin/\nendef\n\ndefine Package/e2fsprogs/conffiles\n/etc/e2fsck.conf\nendef\n\ndefine Package/e2fsprogs/install\n\t$(INSTALL_DIR) $(1)/usr/sbin\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/sbin/e2fsck $(1)/usr/sbin/\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/sbin/mke2fs $(1)/usr/sbin/\n\t$(LN) mke2fs $(1)/usr/sbin/mkfs.ext2\n\t$(LN) mke2fs $(1)/usr/sbin/mkfs.ext3\n\t$(LN) mke2fs $(1)/usr/sbin/mkfs.ext4\n\t$(LN) e2fsck $(1)/usr/sbin/fsck.ext2\n\t$(LN) e2fsck $(1)/usr/sbin/fsck.ext3\n\t$(LN) e2fsck $(1)/usr/sbin/fsck.ext4\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/libe2p.so.* $(1)/usr/lib/\n\t$(INSTALL_DIR) $(1)/etc/init.d\n\t$(INSTALL_DIR) $(1)/lib/functions/fsck\n\t$(INSTALL_DATA) ./files/e2fsck.sh $(1)/lib/functions/fsck/\n\t$(INSTALL_DATA) ./files/e2fsck.conf $(1)/etc/e2fsck.conf\nendef\n\ndefine Package/libcomerr/install\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/libcom_err.so.* $(1)/usr/lib/\nendef\n\ndefine Package/libss/install\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/libss.so.* $(1)/usr/lib/\nendef\n\ndefine Package/libext2fs/install\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/libext2fs.so.* $(1)/usr/lib/\nendef\n\ndefine Package/libext2fs/install_lib\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(CP) $(PKG_BUILD_DIR)/lib/ext2fs/libext2fs.a $(1)/usr/lib/libext2fs_pic.a\nendef\n\ndefine Package/tune2fs/install\n\t$(INSTALL_DIR) $(1)/usr/sbin\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/sbin/tune2fs $(1)/usr/sbin/\n\t$(LN) tune2fs $(1)/usr/sbin/findfs\nendef\n\ndefine Package/resize2fs/install\n\t$(INSTALL_DIR) $(1)/usr/sbin\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/sbin/resize2fs $(1)/usr/sbin/\nendef\n\ndefine Package/badblocks/install\n\t$(INSTALL_DIR) $(1)/usr/sbin\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/sbin/badblocks $(1)/usr/sbin/\nendef\n\ndefine Package/dumpe2fs/install\n\t$(INSTALL_DIR) $(1)/usr/sbin\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/sbin/dumpe2fs $(1)/usr/sbin/\nendef\n\ndefine Package/e2freefrag/install\n\t$(INSTALL_DIR) $(1)/usr/sbin\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/sbin/e2freefrag $(1)/usr/sbin/\nendef\n\ndefine Package/e4crypt/install\n\t$(INSTALL_DIR) $(1)/usr/sbin\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/sbin/e4crypt $(1)/usr/sbin/\nendef\n\ndefine Package/filefrag/install\n\t$(INSTALL_DIR) $(1)/usr/sbin\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/sbin/filefrag $(1)/usr/sbin/\nendef\n\ndefine Package/debugfs/install\n\t$(INSTALL_DIR) $(1)/usr/sbin\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/sbin/debugfs $(1)/usr/sbin/\nendef\n\ndefine Package/chattr/install\n\t$(INSTALL_DIR) $(1)/usr/bin\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/bin/chattr $(1)/usr/bin/\nendef\n\ndefine Package/lsattr/install\n\t$(INSTALL_DIR) $(1)/usr/bin\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/bin/lsattr $(1)/usr/bin/\nendef\n\n$(eval $(call BuildPackage,libcomerr))\n$(eval $(call BuildPackage,libss))\n$(eval $(call BuildPackage,libext2fs))\n$(eval $(call BuildPackage,e2fsprogs))\n$(eval $(call BuildPackage,tune2fs))\n$(eval $(call BuildPackage,resize2fs))\n$(eval $(call BuildPackage,badblocks))\n$(eval $(call BuildPackage,dumpe2fs))\n$(eval $(call BuildPackage,e2freefrag))\n$(eval $(call BuildPackage,e4crypt))\n$(eval $(call BuildPackage,filefrag))\n$(eval $(call BuildPackage,debugfs))\n$(eval $(call BuildPackage,chattr))\n$(eval $(call BuildPackage,lsattr))\n$(eval $(call HostBuild))\n"
  },
  {
    "path": "package/utils/e2fsprogs/files/e2fsck.conf",
    "content": "[options]\nbroken_system_clock = true\n\n"
  },
  {
    "path": "package/utils/e2fsprogs/files/e2fsck.sh",
    "content": "#!/bin/sh\n# Copyright 2010 Vertical Communications\n# Copyright 2012 OpenWrt.org\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\nfsck_e2fsck() {\n\tset -o pipefail\n\te2fsck -p \"$device\" 2>&1 | logger -t \"fstab: e2fsck ($device)\"\n\tlocal status=\"$?\"\n\tset +o pipefail\n\tcase \"$status\" in\n\t\t0|1) ;; #success\n\t\t2) reboot;;\n\t\t4) echo \"e2fsck ($device): Warning! Uncorrected errors.\"| logger -t fstab\n\t\t\treturn 1\n\t\t\t;;\n\t\t*) echo \"e2fsck ($device): Error $status. Check not complete.\"| logger -t fstab;;\n\tesac\n\treturn 0\n}\n\nfsck_ext2() {\n\tfsck_e2fsck \"$@\"\n}\n\nfsck_ext3() {\n\tfsck_e2fsck \"$@\"\n}\n\nfsck_ext4() {\n\tfsck_e2fsck \"$@\"\n}\n\nappend libmount_known_fsck \"ext2\"\nappend libmount_known_fsck \"ext3\"\nappend libmount_known_fsck \"ext4\"\n"
  },
  {
    "path": "package/utils/e2fsprogs/patches/000-relocatable.patch",
    "content": "--- a/lib/et/compile_et.sh.in\n+++ b/lib/et/compile_et.sh.in\n@@ -2,8 +2,14 @@\n #\n #\n \n-AWK=@AWK@\n-DIR=@datadir@/et\n+if test \"x$STAGING_DIR\" = x ; then\n+\tAWK=@AWK@\n+\tDIR=@datadir@/et\n+else\n+\tAWK=awk\n+\tDIR=\"$STAGING_DIR/../hostpkg/share/et\"\n+fi\n+\n \n if test \"$1\" = \"--build-tree\" ; then\n     shift;\n--- a/lib/ss/mk_cmds.sh.in\n+++ b/lib/ss/mk_cmds.sh.in\n@@ -2,10 +2,16 @@\n #\n #\n \n-DIR=@datadir@/ss\n-AWK=@AWK@\n SED=sed\n \n+if test \"x$STAGING_DIR\" = x ; then\n+\tDIR=@datadir@/ss\n+\tAWK=@AWK@\n+else\n+\tDIR=\"$STAGING_DIR/../hostpkg/share/ss\"\n+\tAWK=awk\n+fi\n+\n for as_var in \\\n   LANG LANGUAGE LC_ADDRESS LC_ALL LC_COLLATE LC_CTYPE LC_IDENTIFICATION \\\n   LC_MEASUREMENT LC_MESSAGES LC_MONETARY LC_NAME LC_NUMERIC LC_PAPER \\\n"
  },
  {
    "path": "package/utils/e2fsprogs/patches/001-com_err_version.patch",
    "content": "--- a/lib/et/Makefile.in\n+++ b/lib/et/Makefile.in\n@@ -26,8 +26,8 @@ SHARE_FILES= et_c.awk et_h.awk\n LIBRARY= libcom_err\n LIBDIR= et\n \n-ELF_VERSION = 2.1\n-ELF_SO_VERSION = 2\n+ELF_VERSION = 0.0\n+ELF_SO_VERSION = 0\n ELF_IMAGE = libcom_err\n ELF_MYDIR = et\n ELF_INSTALL_DIR = $(root_libdir)\n"
  },
  {
    "path": "package/utils/e2fsprogs/patches/002-fix-subst-host-build.patch",
    "content": "--- a/util/subst.c\n+++ b/util/subst.c\n@@ -10,6 +10,7 @@\n #else\n #define HAVE_SYS_STAT_H\n #define HAVE_SYS_TIME_H\n+#define HAVE_SYS_STAT_H\n #endif\n #include <stdio.h>\n #include <errno.h>\n"
  },
  {
    "path": "package/utils/f2fs-tools/Makefile",
    "content": "#\n# Copyright (C) 2014 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=f2fs-tools\nPKG_VERSION:=1.14.0\nPKG_RELEASE:=3\n\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz\nPKG_SOURCE_URL:=https://git.kernel.org/pub/scm/linux/kernel/git/jaegeuk/f2fs-tools.git/snapshot/\nPKG_HASH:=619263d4e2022152a1472c1d912eaae104f20bd227ce0bb9d41d1d6608094bd1\n\nPKG_MAINTAINER:=Felix Fietkau <nbd@nbd.name>\nPKG_LICENSE:=GPL-2.0-only\nPKG_LICENSE_FILES:=COPYING\n\nPKG_FIXUP:=autoreconf\nPKG_BUILD_PARALLEL:=1\nPKG_INSTALL:=1\n\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine Package/f2fs-tools/Default\n  SECTION:=utils\n  CATEGORY:=Utilities\n  SUBMENU:=Filesystem\n  DEPENDS:=+libf2fs\n  URL:=http://git.kernel.org/cgit/linux/kernel/git/jaegeuk/f2fs-tools.git\n  VARIANT:=default\nendef\n\ndefine Package/f2fs-tools/SELinux\n  SECTION:=utils\n  CATEGORY:=Utilities\n  SUBMENU:=Filesystem\n  DEPENDS:=+libf2fs-selinux +libselinux\n  URL:=http://git.kernel.org/cgit/linux/kernel/git/jaegeuk/f2fs-tools.git\n  VARIANT:=selinux\nendef\n\ndefine Package/mkf2fs\n  $(Package/f2fs-tools/Default)\n  TITLE:=Utility for creating a Flash-Friendly File System (F2FS)\n  CONFLICTS:=mkf2fs-selinux\nendef\n\ndefine Package/mkf2fs-selinux\n  $(Package/f2fs-tools/SELinux)\n  TITLE:=Utility for creating a Flash-Friendly File System (F2FS) with SELinux support\nendef\n\ndefine Package/f2fsck\n  $(Package/f2fs-tools/Default)\n  TITLE:=Utility for checking/repairing a Flash-Friendly File System (F2FS)\n  CONFLICTS:=f2fsck-selinux\nendef\n\ndefine Package/f2fsck-selinux\n  $(Package/f2fs-tools/SELinux)\n  TITLE:=Utility for checking/repairing a Flash-Friendly File System (F2FS) with SELinux support\nendef\n\ndefine Package/f2fs-tools\n  $(Package/f2fs-tools/Default)\n  TITLE:=Tools for Flash-Friendly File System (F2FS)\n  DEPENDS += +mkf2fs +f2fsck\n  CONFLICTS:=f2fs-tools-selinux\nendef\n\ndefine Package/f2fs-tools-selinux\n  $(Package/f2fs-tools/SELinux)\n  TITLE:=Tools for Flash-Friendly File System (F2FS) with SELinux support\n  DEPENDS += +mkf2fs-selinux +f2fsck-selinux\nendef\n\ndefine Package/libf2fs\n  SECTION:=libs\n  CATEGORY:=Libraries\n  TITLE:=Library for Flash-Friendly File System (F2FS) tools\n  DEPENDS:=+libuuid\n  ABI_VERSION:=6\n  CONFLICTS:=libf2fs-selinux\n  VARIANT:=default\nendef\n\ndefine Package/libf2fs-selinux\n  SECTION:=libs\n  CATEGORY:=Libraries\n  TITLE:=Library for Flash-Friendly File System (F2FS) tools with SELinux support\n  DEPENDS:=+libuuid +libselinux\n  ABI_VERSION:=6\n  VARIANT:=selinux\nendef\n\nCONFIGURE_ARGS += \\\n\t--disable-static \\\n\t--without-blkid\n\nifneq ($(BUILD_VARIANT),selinux)\n  CONFIGURE_ARGS += --without-selinux\nendif\n\nCONFIGURE_VARS += \\\n\tac_cv_file__git=no\n\ndefine Package/libf2fs/install\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(CP) \\\n\t\t$(PKG_INSTALL_DIR)/usr/lib/libf2fs.so.* $(1)/usr/lib/\nendef\n\nPackage/libf2fs-selinux/install = $(Package/libf2fs/install)\n\ndefine Package/mkf2fs/install\n\t$(INSTALL_DIR) $(1)/usr/sbin\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/sbin/mkfs.f2fs $(1)/usr/sbin\nendef\n\nPackage/mkf2fs-selinux/install = $(Package/mkf2fs/install)\n\ndefine Package/f2fsck/install\n\t$(INSTALL_DIR) $(1)/usr/sbin\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/sbin/fsck.f2fs $(1)/usr/sbin\n\tln -s /usr/sbin/fsck.f2fs $(1)/usr/sbin/defrag.f2fs\n\tln -s /usr/sbin/fsck.f2fs $(1)/usr/sbin/dump.f2fs\n\tln -s /usr/sbin/fsck.f2fs $(1)/usr/sbin/sload.f2fs\n\tln -s /usr/sbin/fsck.f2fs $(1)/usr/sbin/resize.f2fs\nendef\n\nPackage/f2fsck-selinux/install = $(Package/f2fsck/install)\n\ndefine Package/f2fs-tools/install\n\t$(INSTALL_DIR) $(1)/usr/sbin\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/sbin/f2fstat $(1)/usr/sbin\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/sbin/fibmap.f2fs $(1)/usr/sbin\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/sbin/parse.f2fs $(1)/usr/sbin\nendef\n\nPackage/f2fs-tools-selinux/install = $(Package/f2fs-tools/install)\n\n$(eval $(call BuildPackage,libf2fs))\n$(eval $(call BuildPackage,libf2fs-selinux))\n$(eval $(call BuildPackage,mkf2fs))\n$(eval $(call BuildPackage,mkf2fs-selinux))\n$(eval $(call BuildPackage,f2fsck))\n$(eval $(call BuildPackage,f2fsck-selinux))\n$(eval $(call BuildPackage,f2fs-tools))\n$(eval $(call BuildPackage,f2fs-tools-selinux))\n"
  },
  {
    "path": "package/utils/f2fs-tools/patches/200-resize_f2fs-fix_wrong_ovp_calculation.patch",
    "content": "From f056fbeff08d30a6d9acdb9e06704461ceee3500 Mon Sep 17 00:00:00 2001\nFrom: Jaegeuk Kim <jaegeuk@kernel.org>\nDate: Thu, 1 Apr 2021 20:13:55 -0700\nSubject: resize.f2fs: fix wrong ovp calculation\n\nberoal reported a mount failure due to broken valid_user_blocks.\n[ 6890.647749] F2FS-fs (loop0): Wrong valid_user_blocks: 16040048,\nuser_block_count: 10016768\n\nFrom fsck,\n\nsegment_count_main                      [0x    9a95 : 39573]\n-> 39573 * 2MB = 78GB as user space\n\noverprov_segment_count                  [0x    4e29 : 20009]\n-> 20009 * 2MB = 40GB as overprovisioned space which user can't see.\n\nBut,\n[FSCK] valid_block_count matching with CP             [Ok..] [0xf4c070]\n-> 0xf4c070 = 16040048\n\nvalid_block_count                       [0x  f4c070 : 16040048]\n-> So, this is correct.\n\nIt turns out resize.f2fs gave very large and wrong overprovisioning space\nresult in shortage of user blocks. The root cause was f2fs_get_usable_segments()\ndidn't consider resize case which needs segment_count_main from new superblock.\n\nFixes: f8410857b7a8 (\"f2fs-tools: zns zone-capacity support\")\nSigned-off-by: Jaegeuk Kim <jaegeuk@kernel.org>\n---\n lib/libf2fs_zoned.c | 3 +++\n 1 file changed, 3 insertions(+)\n\n--- a/lib/libf2fs_zoned.c\n+++ b/lib/libf2fs_zoned.c\n@@ -495,6 +495,9 @@ uint32_t f2fs_get_usable_segments(struct\n \tint i, j;\n \tuint32_t usable_segs = 0, zone_segs;\n \n+\tif (c.func == RESIZE)\n+\t\treturn get_sb(segment_count_main);\n+\n \tfor (i = 0; i < c.ndevs; i++) {\n \t\tif (c.devices[i].zoned_model != F2FS_ZONED_HM) {\n \t\t\tusable_segs += c.devices[i].total_segments;\n"
  },
  {
    "path": "package/utils/fbtest/Makefile",
    "content": "#\n# Copyright (C) 2012 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=fbtest\nPKG_RELEASE:=1\n\nPKG_BUILD_DIR := $(BUILD_DIR)/$(PKG_NAME)\n\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine Package/fbtest\n  SECTION:=utils\n  CATEGORY:=Utilities\n  TITLE:=Frame buffer device testing tool\n  DEPENDS:=@DISPLAY_SUPPORT\nendef\n\ndefine Build/Configure\nendef\n\ndefine Build/Compile\n\t$(MAKE) -C $(PKG_BUILD_DIR) \\\n\t\tCC=\"$(TARGET_CC)\" \\\n\t\tCFLAGS=\"$(TARGET_CFLAGS) -Wall\" \\\n\t\tLDFLAGS=\"$(TARGET_LDFLAGS)\"\nendef\n\ndefine Package/fbtest/install\n\t$(INSTALL_DIR) $(1)/usr/sbin\n\t$(INSTALL_BIN) $(PKG_BUILD_DIR)/fbtest $(1)/usr/sbin/\nendef\n\n$(eval $(call BuildPackage,fbtest))\n"
  },
  {
    "path": "package/utils/fbtest/src/Makefile",
    "content": "CC = gcc\nCFLAGS = -Wall\nOBJS = fbtest.o\n\nall: fbtest\n\n%.o: %.c\n\t$(CC) $(CFLAGS) -c -o $@ $<\n\nfbtest: $(OBJS)\n\t$(CC) -o $@ $(OBJS)\n\nclean:\n\trm -f fbtest *.o\n"
  },
  {
    "path": "package/utils/fbtest/src/fbtest.c",
    "content": "/******************************************************************************\n *\tfbtest - fbtest.c\n *\ttest program for the tuxbox-framebuffer device\n *\ttests all GTX/eNX supported modes\n *                                                                            \n *\t(c) 2003 Carsten Juttner (carjay@gmx.net)\n *\n * \tThis program is free software; you can redistribute it and/or modify\n * \tit under the terms of the GNU General Public License as published by\n * \tThe Free Software Foundation; either version 2 of the License, or\n * \t(at your option) any later version.\n *\n * \tThis program is distributed in the hope that it will be useful,\n * \tbut WITHOUT ANY WARRANTY; without even the implied warranty of\n * \tMERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n * \tGNU General Public License for more details.\n *\n * \tYou should have received a copy of the GNU General Public License\n * \talong with this program; if not, write to the Free Software\n * \tFoundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.\n *  \t\t\t\t\t\t\t\t\t      \n ******************************************************************************\n * $Id: fbtest.c,v 1.5 2005/01/14 23:14:41 carjay Exp $\n ******************************************************************************/\n\n// TODO: - should restore the colour map and mode to what it was before\n//\t - is colour map handled correctly?\n\n#include <stdio.h>\n#include <stdlib.h>\n#include <unistd.h>\n#include <string.h>\n\n#include <sys/types.h>\n#include <sys/stat.h>\n#include <sys/ioctl.h>\n#include <sys/mman.h>\n#include <fcntl.h>\n\n#include <linux/fb.h>\n\n#define FBDEV \"/dev/fb0\"\n\nstruct vidsize{\n\tint width;\n\tint height;\n};\nstatic\nconst struct vidsize vidsizetable[]={\t// all supported sizes\n\t{720,576},{720,480},{720,288},{720,240},\n\t{640,576},{640,480},{640,288},{640,240},\n\t{360,576},{360,480},{360,288},{360,240},\n\t{320,576},{320,480},{320,288},{320,240}\n};\n#define VIDSIZENUM (sizeof(vidsizetable)/sizeof(struct vidsize))\n\nenum pixenum{\t// keep in sync with pixname !\n\tCLUT4=0,\n\tCLUT8,\n\tRGB565,\n\tARGB1555,\n\tARGB\n};\nconst char *pixname[] = {\n\t\"CLUT4\",\n\t\"CLUT8\",\n\t\"RGB565\",\n\t\"ARGB1555\",\n\t\"ARGB\"\n};\n\nstruct pixelformat{\n\tchar *name;\n\tstruct fb_bitfield red;\n\tstruct fb_bitfield green;\n\tstruct fb_bitfield blue;\n\tstruct fb_bitfield transp;\n\tchar bpp;\n\tchar pixenum;\n};\n\nstatic\t\t// so far these are all modes supported by the eNX (only partially by GTX)\nconst struct pixelformat pixelformattable[] = {\n\t{ .name = \"CLUT4 ARGB8888\", \t// CLUT4 (ARGB8888)\n\t\t.bpp = 4, .pixenum = CLUT4,\n\t\t.red = \t { .offset = 0, .length=8, .msb_right =0 },\n\t\t.green = { .offset = 0, .length=8, .msb_right =0 },\n\t\t.blue =  { .offset = 0, .length=8, .msb_right =0 },\n\t\t.transp=  { .offset = 0, .length=8, .msb_right =0 }\n\t},\n\t{ .name = \"CLUT4 ARGB1555\", \t// CLUT4 (ARGB1555)\n\t\t.bpp = 4, .pixenum = CLUT4,\n\t\t.red = \t { .offset = 0, .length=5, .msb_right =0 },\n\t\t.green = { .offset = 0, .length=5, .msb_right =0 },\n\t\t.blue =  { .offset = 0, .length=5, .msb_right =0 },\n\t\t.transp=  { .offset = 0, .length=1, .msb_right =0 }\n\t},\n\t{ .name = \"CLUT8 ARGB8888\",\t// CLUT8 (ARGB8888)\n\t\t.bpp = 8, .pixenum = CLUT8,\n\t\t.red = \t { .offset = 0, .length=8, .msb_right =0 },\n\t\t.green = { .offset = 0, .length=8, .msb_right =0 },\n\t\t.blue =  { .offset = 0, .length=8, .msb_right =0 },\n\t\t.transp=  { .offset = 0, .length=8, .msb_right =0 }\n\t},\n\t{ .name = \"CLUT8 ARGB1555\",\t// CLUT8 (ARGB1555)\n\t\t.bpp = 8, .pixenum = CLUT8,\n\t\t.red = \t { .offset = 0, .length=5, .msb_right =0 },\n\t\t.green = { .offset = 0, .length=5, .msb_right =0 },\n\t\t.blue =  { .offset = 0, .length=5, .msb_right =0 },\n\t\t.transp=  { .offset = 0, .length=1, .msb_right =0 }\n\t},\n\t{ .name = \"ARGB1555\", \t// ARGB1555\n\t\t.bpp = 16, .pixenum = ARGB1555,\n\t\t.red = \t { .offset = 10, .length=5, .msb_right =0 },\n\t\t.green = { .offset = 5,  .length=5, .msb_right =0 },\n\t\t.blue =  { .offset = 0,  .length=5, .msb_right =0 },\n\t\t.transp=  { .offset = 15, .length=1, .msb_right =0 }\n\t},\n\t{ .name = \"RGB565\", \t\t// RGB565\n\t\t.bpp = 16, .pixenum = RGB565,\n\t\t.red = \t { .offset = 11, .length=5, .msb_right =0 },\n\t\t.green = { .offset = 5,  .length=6, .msb_right =0 },\n\t\t.blue =  { .offset = 0,  .length=5, .msb_right =0 },\n\t\t.transp=  { .offset = 0,  .length=0, .msb_right =0 }\n\t},\n\t{ .name = \"ARGB\",\t// 32 f*cking bits, the real McCoy :)\n\t\t.bpp = 32, .pixenum = ARGB,\n\t\t.red = \t { .offset = 16, .length=8, .msb_right =0 },\n\t\t.green = { .offset = 8,  .length=8, .msb_right =0 },\n\t\t.blue =  { .offset = 0,  .length=8, .msb_right =0 },\n\t\t.transp=  { .offset = 24, .length=8, .msb_right =0 }\n\t}\n};\n#define PIXELFORMATNUM (sizeof(pixelformattable)/sizeof(struct pixelformat))\n\nstruct colour {\n\t__u16 r;\n\t__u16 g;\n\t__u16 b;\n\t__u16 a;\n};\nstatic\nstruct colour colourtable[] = {\n\t{.r =0xffff, .g = 0xffff, .b=0xffff, .a=0xffff},\t// fully transparent white\n\t{.r =0xffff, .g = 0x0000, .b=0x0000, .a=0x0000},\t// red\n\t{.r =0x0000, .g = 0xffff, .b=0x0000, .a=0x0000},\t// green\n\t{.r =0x0000, .g = 0x0000, .b=0xffff, .a=0x0000},\t// blue\n\t{.r =0x0000, .g = 0x0000, .b=0x0000, .a=0x0000}\t\t// black\n};\n#define COLOURNUM (sizeof(colourtable)/sizeof(struct colour))\n\nstruct rect{\n\tint x;\n\tint y;\n\tint width;\n\tint height;\n\tconst struct colour *col;\n};\nstruct pixel{\t\t// up to 32 bits of pixel information\n\tchar byte[4];\n};\n\nvoid col2pixel (struct pixel *pix, const struct pixelformat *pixf, const struct colour *col){\n\tswitch (pixf->pixenum){\n\t\tcase RGB565:\n\t\t\tpix->byte[0]=(col->r&0xf8)|(col->g&0xfc)>>5;\n\t\t\tpix->byte[1]=(col->g&0xfc)<<3|(col->b&0xf8)>>3;\n\t\t\tbreak;\n\t\tcase ARGB1555:\n\t\t\tpix->byte[0]=(col->a&0x80)|(col->r&0xf8)>>1|(col->g&0xf8)>>6;\n\t\t\tpix->byte[1]=(col->g&0xf8)<<2|(col->b&0xf8)>>3;\n\t\t\tbreak;\n\t\tcase ARGB:\n\t\t\tpix->byte[0]=col->a;\n\t\t\tpix->byte[1]=col->r;\n\t\t\tpix->byte[2]=col->g;\n\t\t\tpix->byte[3]=col->b;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tprintf (\"unknown pixelformat\\n\");\n\t\t\texit(1);\n\t}\n}\n\nint setmode(int fbd, const struct pixelformat *pixf,const struct vidsize *vids){\n\tstruct fb_var_screeninfo var;\n\tint stat;\n\tstat = ioctl (fbd, FBIOGET_VSCREENINFO,&var);\n\tif (stat<0) return -2;\n\t\n\tvar.xres= vids->width;\n\tvar.xres_virtual = vids->width;\n\tvar.yres= vids->height;\n\tvar.yres_virtual = vids->height;\n\t\n\tvar.bits_per_pixel = pixf->bpp;\n\tvar.red = pixf->red;\n\tvar.green = pixf->green;\n\tvar.blue = pixf->blue;\n\tvar.transp = pixf->transp;\n\n\tstat = ioctl (fbd, FBIOPUT_VSCREENINFO,&var);\n\tif (stat<0) return -1;\n\treturn 0;\n}\n\n// unefficient implementation, do NOT use it for your next ego shooter, please :)\n// for 4-Bit only rectangles with even width are supported\n// CLUT-modes use value of red component as index\nvoid drawrect(void *videoram, struct rect *r, const struct pixelformat *pixf, const struct vidsize *vids){\n\tint x,y,corwidth, bpp = 0, tocopy = 1;\n\tstruct pixel pix;\n\tunsigned char *pmem = videoram;\n\tcorwidth = r->width;\t// actually only \"corrected\" for 4 Bit\n\n\tif (pixf->pixenum!=CLUT4&&pixf->pixenum!=CLUT8){\n\t\tswitch (pixf->pixenum){\n\t\t\tcase ARGB1555:\n\t\t\tcase RGB565:\n\t\t\t\tbpp = 16;\n\t\t\t\ttocopy = 2;\n\t\t\t\tbreak;\n\t\t\tcase ARGB:\n\t\t\t\tbpp = 32;\n\t\t\t\ttocopy = 4;\n\t\t\t\tbreak;\n\t\t\tdefault:\n\t\t\t\tprintf (\"drawrect: unknown pixelformat(%d) bpp:%d\\n\",pixf->pixenum,pixf->bpp);\n\t\t\t\texit(1);\n\t\t}\n\t\tcol2pixel(&pix,pixf,r->col);\n\t} else {\n\t\tswitch (pixf->pixenum){\t// CLUT = Colour LookUp Table (palette)\n\t\t\tcase CLUT4:\t// take red value as index in this case\n\t\t\t\tpix.byte[0]=(r->col->r)<<4|(r->col->r&0xf);\t// slightly cryptic... \"rect->colour->red\"\n\t\t\t\tcorwidth>>=1;\t// we copy bytes\n\t\t\t\tbpp=4;\n\t\t\t\ttocopy=1;\n\t\t\t\tbreak;\n\t\t\tcase CLUT8:\n\t\t\t\tpix.byte[0]=(r->col->r&0xff);\n\t\t\t\tbpp=8;\n\t\t\t\ttocopy=1;\n\t\t\t\tbreak;\n\t\t}\n\t}\n\tpmem=videoram+((((r->y*vids->width)+r->x)*bpp)>>3);\n\tfor (y=0;y<r->height;y++){\n\t\tint offset = 0;\n\t\tfor (x=0;x<corwidth;x++){\n\t\t\tmemcpy (pmem+offset,pix.byte,tocopy);\n\t\t\toffset+=tocopy;\n\t\t}\n\t\tpmem +=((vids->width*bpp)>>3);\t// skip one whole line, actually should be taken from \"fix-info\"\n\t}\n}\n\t\t\t\n// create quick little test image, 4 colours from table\nvoid draw4field(void *videoram, const struct pixelformat *pixf, const struct vidsize *vids){\n\tstruct rect r;\n\tstruct colour c;\n\tint height, width;\n\tc.r = 1;\t// only used for the indexed modes, r is taken as index\n\theight = vids->height;\n\twidth = vids->width;\n\n\tr.height = height>>1;\n\tr.width = width>>1;\n\tr.x = 0;\tr.y = 0;\n\tif (pixf->pixenum==CLUT4||pixf->pixenum==CLUT8) r.col = &c;\n\telse r.col = &colourtable[1];\n\tdrawrect (videoram, &r, pixf, vids);\n\n\tr.x = width/2;\tr.y = 0;\n\tif (pixf->pixenum==CLUT4||pixf->pixenum==CLUT8) c.r = 2;\n\telse r.col = &colourtable[2];\n\tdrawrect (videoram, &r, pixf, vids);\n\n\tr.x = 0;\tr.y = height/2;\n\tif (pixf->pixenum==CLUT4||pixf->pixenum==CLUT8) c.r = 3;\n\telse r.col = &colourtable[3];\n\tdrawrect (videoram, &r, pixf, vids);\n\n\tr.x = width/2;\tr.y = height/2;\n\tif (pixf->pixenum==CLUT4||pixf->pixenum==CLUT8) c.r = 0;\n\telse r.col = &colourtable[0];\n\tdrawrect (videoram, &r, pixf, vids);\n}\n\nvoid usage(char *name){\n \tprintf (\"Usage: %s [options]\\n\"\n\t\t\"Options: -f<pixelformat>\\n\"\n\t\t\"            where format is one of:\\n\"\n\t\t\"              CLUT4,CLUT8,ARGB1555,RGB565,ARGB\\n\"\n\t\t\"         -s<width>x<heigth>\\n\"\n\t\t\"            where width is either 720,640,360,320\\n\"\n\t\t\"                  and height is either 288,240,480,576\\n\"\n\t\t\"         -n\\n\"\n\t\t\"            disables clearing the framebuffer after drawing\\n\"\n\t\t\"            the testimage. This can be useful to keep the last\\n\"\n\t\t\"            drawn image onscreen.\\n\"\n\t\t\"\\nExample: %s -fRGB322\\n\",name,name);\n\texit(0);\n}\n\nint main (int argc,char **argv){\n\tstruct fb_fix_screeninfo fix;\n\tstruct fb_var_screeninfo var;\n\tstruct fb_cmap cmap;\n\tstruct rect r;\n\tint fbd;\n\tunsigned char *pfb;\n\tint stat;\n\tint optchar,fmode=-1,smode=-1,clear=1;\n\tint i_cmap,i_size,i_pix;\n\textern char *optarg;\n\t\n\tif (argc!=0&&argc>4) usage(argv[0]);\n\twhile ( (optchar = getopt (argc,argv,\"f:s:n\"))!= -1){\n\t\tint i,height,width;\n\t\tswitch (optchar){\n\t\t\tcase 'f':\n\t\t\t\tfor (i=0;i<(sizeof(pixname)/sizeof(char*));i++){\n\t\t\t\t\tif (!strncmp (optarg,pixname[i],strlen(pixname[i]))){\n\t\t\t\t\t\tfmode=i;\n\t\t\t\t\t\tprintf (\"displaying only %s-modes\\n\",pixname[i]);\n\t\t\t\t\t\tbreak;\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\tif (fmode==-1){\n\t\t\t\t\tprintf (\"unknown pixelformat\\n\");\n\t\t\t\t\texit(0);\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 's':\n\t\t\t\tif (sscanf (optarg,\"%dx%d\",&width,&height)!=2){\n\t\t\t\t\tprintf (\"parsing size failed\\n\");\n\t\t\t\t\texit(0);\n\t\t\t\t} else {\n\t\t\t\t\tprintf (\"requested size %dx%d\\n\",width,height);\n\t\t\t\t\tfor (i=0;i<VIDSIZENUM;i++){\n\t\t\t\t\t\tif (vidsizetable[i].width == width &&\n\t\t\t\t\t\t\tvidsizetable[i].height == height){\n\t\t\t\t\t\t\tsmode = i;\n\t\t\t\t\t\t\tbreak;\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t\tif (smode==-1){\n\t\t\t\t\t\tprintf (\"this size is not supported\\n\");\n\t\t\t\t\t\texit(0);\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 'n':\n\t\t\t\tclear = 0;\n\t\t\t\tprintf (\"clearing framebuffer after drawing is disabled\\n\");\n\t\t\t\tbreak;\n\t\t\tcase '?':\n\t\t\t\tusage (argv[0]);\n\t\t}\n\t}\n\t\n\tfbd = open (FBDEV, O_RDWR);\n\tif (fbd<0){\n\t\tperror (\"Error opening framebuffer device\");\n\t\treturn 1;\n\t}\n\tstat = ioctl (fbd, FBIOGET_FSCREENINFO,&fix);\n\tif (stat<0){\n\t\tperror (\"Error getting fix screeninfo\");\n\t\treturn 1;\n\t}\n\tstat = ioctl (fbd, FBIOGET_VSCREENINFO,&var);\n\tif (stat<0){\n\t\tperror (\"Error getting var screeninfo\");\n\t\treturn 1;\n\t}\n\tstat = ioctl (fbd, FBIOPUT_VSCREENINFO,&var);\n\tif (stat<0){\n\t\tperror (\"Error setting mode\");\n\t\treturn 1;\n\t}\n\tpfb = mmap (0, fix.smem_len, PROT_READ|PROT_WRITE, MAP_SHARED, fbd, 0);\n\tif (pfb == MAP_FAILED){\n\t\tperror (\"Error mmap'ing framebuffer device\");\n\t\treturn 1;\n\t}\n\n\t// iterate over all modes\n\tfor (i_pix=0;i_pix<PIXELFORMATNUM;i_pix++){\n\t\tif (fmode!=-1 && pixelformattable[i_pix].pixenum != fmode) continue;\n\t\tprintf (\"testing: %s\",pixelformattable[i_pix].name);\n\t\tprintf (\" for sizes: \\n\");\n\t\tfor (i_size=0;i_size<VIDSIZENUM;i_size++){\n\t\t\tif (smode!=-1 && i_size!=smode) continue;\n\t\t\tprintf (\"%dx%d \",vidsizetable[i_size].width,vidsizetable[i_size].height);\n\t\t\tfflush(stdout);\n\t\t\tif ((i_size%4)==3) printf (\"\\n\");\n\t\t\t\n\t\t\t// try to set mode\n\t\t\tstat = setmode(fbd,&pixelformattable[i_pix],&vidsizetable[i_size]);\n\t\t\tif (stat==-2) perror (\"fbtest: could not get fb_var-screeninfo from fb-device\");\n\t\t\telse if (stat==-1){\n\t\t\t\tprintf (\"\\nCould not set mode %s (%dx%d), possible reasons:\\n\"\n\t\t\t\t\t\"- you have a GTX (soz m8)\\n\"\n\t\t\t\t\t\"- your configuration does not have enough graphics RAM\\n\"\n\t\t\t\t\t\"- you found a bug\\n\"\n\t\t\t\t\t\"choose your poison accordingly...\\n\",\n\t\t\t\t\tpixelformattable[i_pix].name,vidsizetable[i_size].width,vidsizetable[i_size].height);\n\t\t\t\t\tcontinue;\n\t\t\t}\n\t\t\t// fill cmap;\n\t\t\tcmap.len = 1;\n\t\t\tif ((pixelformattable[i_pix].bpp==4)||\n\t\t\t\t((pixelformattable[i_pix].bpp==8)&&(pixelformattable[i_pix].red.length!=3))){\n\t\t\t\tfor (i_cmap=0;i_cmap<COLOURNUM;i_cmap++){\n\t\t\t\t\tcmap.start=i_cmap;\n\t\t\t\t\tcmap.red=&colourtable[i_cmap].r;\n\t\t\t\t\tcmap.green=&colourtable[i_cmap].g;\n\t\t\t\t\tcmap.blue=&colourtable[i_cmap].b;\n\t\t\t\t\tcmap.transp=&colourtable[i_cmap].a;\n\t\t\t\t\tstat = ioctl (fbd, FBIOPUTCMAP, &cmap);\n\t\t\t\t\tif (stat<0) printf (\"setting colourmap failed\\n\");\n\t\t\t\t}\n\t\t\t}\n\t\t\t// create the test image\n\t\t\tdraw4field(pfb,&pixelformattable[i_pix],&vidsizetable[i_size]);\n\t\t\tusleep (500000);\n\t\t\t// clear screen\n\t\t\tif (clear){\n\t\t\t\tr.x=r.y=0;r.width = vidsizetable[i_size].width; r.height = vidsizetable[i_size].height;\n\t\t\t\tr.col = &colourtable[4];\n\t\t\t\tdrawrect(pfb,&r,&pixelformattable[i_pix],&vidsizetable[i_size]);\n\t\t\t}\n\t\t}\n\t\tprintf (\"\\n\");\n\t}\n\n\tstat = munmap (pfb,fix.smem_len);\n\tif (stat<0){\n\t\tperror (\"Error munmap'ing framebuffer device\");\n\t\treturn 1;\n\t}\n\tclose (fbd);\n\treturn 0;\n}\n"
  },
  {
    "path": "package/utils/fritz-tools/Makefile",
    "content": "include $(TOPDIR)/rules.mk\n\nPKG_NAME:=fritz-tools\nPKG_RELEASE:=1\nCMAKE_INSTALL:=1\n\ninclude $(INCLUDE_DIR)/package.mk\ninclude $(INCLUDE_DIR)/cmake.mk\n\ndefine Package/fritz-tools/Default\n  SECTION:=utils\n  CATEGORY:=Utilities\nendef\n\ndefine Package/fritz-tffs\n  $(call Package/fritz-tools/Default)\n  TITLE:=Utility to partially read the TFFS filesystems\nendef\n\ndefine Package/fritz-tffs/description\n Utility to partially read the TFFS filesystems.\nendef\n\ndefine Package/fritz-tffs-nand\n  $(call Package/fritz-tools/Default)\n  TITLE:=Utility to partially read the TFFS filesystems on NAND flash\nendef\n\ndefine Package/fritz-tffs-nand/description\n Utility to partially read the TFFS filesystems on NAND flash.\nendef\n\ndefine Package/fritz-caldata\n  $(call Package/fritz-tools/Default)\n  DEPENDS:=+zlib\n  TITLE:=Utility to extract WLAN calibration data\nendef\n\ndefine Package/fritz-caldata/description\n Utility to extract the zlib compress calibration data from flash.\nendef\n\ndefine Package/fritz-tffs/install\n\t$(INSTALL_DIR) $(1)/usr/bin\n\t$(INSTALL_BIN) $(PKG_BUILD_DIR)/fritz_tffs_read $(1)/usr/bin/fritz_tffs\nendef\n\ndefine Package/fritz-tffs-nand/install\n\t$(INSTALL_DIR) $(1)/usr/bin\n\t$(INSTALL_BIN) $(PKG_BUILD_DIR)/fritz_tffs_nand_read $(1)/usr/bin/fritz_tffs_nand\nendef\n\ndefine Package/fritz-caldata/install\n\t$(INSTALL_DIR) $(1)/usr/bin\n\t$(INSTALL_BIN) $(PKG_BUILD_DIR)/fritz_cal_extract $(1)/usr/bin/\nendef\n\n$(eval $(call BuildPackage,fritz-tffs))\n$(eval $(call BuildPackage,fritz-tffs-nand))\n$(eval $(call BuildPackage,fritz-caldata))\n"
  },
  {
    "path": "package/utils/fritz-tools/README.md",
    "content": "Userspace utilties for accessing TFFS (a name-value storage usually found in AVM Fritz!Box based devices)\n\n## Building\n\n```\nmkdir build\ncd build\ncmake /path/to/fritz_tffs_tools\nmake\n```\n\n## Usage\n\nAll command line parameters are documented:\n```\nfritz_tffs_read -h\n```\n\nShow all entries from a TFFS partition dump  (in the format: name=value):\n```\nfritz_tffs_read -i /path/to/tffs.dump -a\n```\n\nRead a TFFS partition and show all entries (in the format: name=value):\n```\nfritz_tffs_read -i /dev/mtdX -a\n```\n\nOutput only the value of a specific key (this will only show the value):\n```\nfritz_tffs_read -i /dev/mtdX -n my_ipaddress\n```\n\n## LICENSE\n\nSee `LICENSE`:\n\n    This program is free software; you can redistribute it and/or modify\n    it under the terms of the GNU General Public License as published by\n    the Free Software Foundation; either version 2 of the License, or\n    (at your option) any later version.\n\n    This program is distributed in the hope that it will be useful,\n    but WITHOUT ANY WARRANTY; without even the implied warranty of\n    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n    GNU General Public License for more details.\n\n    You should have received a copy of the GNU General Public License along\n    with this program; if not, write to the Free Software Foundation, Inc.,\n    51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.\n"
  },
  {
    "path": "package/utils/fritz-tools/src/CMakeLists.txt",
    "content": "cmake_minimum_required(VERSION 2.6)\n\nPROJECT(fritz-tools C)\nADD_DEFINITIONS(-Wall -Werror --std=gnu99 -Wmissing-declarations)\n\nSET(CMAKE_SHARED_LIBRARY_LINK_C_FLAGS \"\")\n\nFIND_PATH(zlib_include_dir zlib.h)\nINCLUDE_DIRECTORIES(${zlib_include_dir})\n\nADD_EXECUTABLE(fritz_tffs_read fritz_tffs_read.c)\nADD_EXECUTABLE(fritz_tffs_nand_read fritz_tffs_nand_read.c)\nADD_EXECUTABLE(fritz_cal_extract fritz_cal_extract.c)\nTARGET_LINK_LIBRARIES(fritz_cal_extract z)\n\nINSTALL(TARGETS fritz_tffs_read fritz_tffs_nand_read fritz_cal_extract RUNTIME DESTINATION bin)\n"
  },
  {
    "path": "package/utils/fritz-tools/src/fritz_cal_extract.c",
    "content": "/*\n * A tool for reading the zlib compressed calibration data\n * found in AVM Fritz!Box based devices).\n *\n * Copyright (c) 2017 Christian Lamparter <chunkeey@googlemail.com>\n *\n * Based on zpipe, which is an example of proper use of zlib's inflate().\n * that is Not copyrighted -- provided to the public domain\n * Version 1.4  11 December 2005  Mark Adler\n *\n * This program is free software; you can redistribute it and/or modify\n * it under the terms of the GNU General Public License as published by\n * the Free Software Foundation; either version 2 of the License, or\n * (at your option) any later version.\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n * GNU General Public License for more details.\n *\n * You should have received a copy of the GNU General Public License along\n * with this program; if not, write to the Free Software Foundation, Inc.,\n * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.\n */\n\n#include <stdio.h>\n#include <string.h>\n#include <assert.h>\n#include <unistd.h>\n#include <stdint.h>\n#include <stdlib.h>\n#include <endian.h>\n#include <errno.h>\n#include \"zlib.h\"\n\n#define CHUNK 1024\n\nstatic inline size_t special_min(size_t a, size_t b)\n{\n\treturn a == 0 ? b : (a < b ? a : b);\n}\n\n/* Decompress from file source to file dest until stream ends or EOF.\n   inf() returns Z_OK on success, Z_MEM_ERROR if memory could not be\n   allocated for processing, Z_DATA_ERROR if the deflate data is\n   invalid or incomplete, Z_VERSION_ERROR if the version of zlib.h and\n   the version of the library linked do not match, or Z_ERRNO if there\n   is an error reading or writing the files. */\nstatic int inf(FILE *source, FILE *dest, size_t limit, size_t skip)\n{\n    int ret;\n    size_t have;\n    z_stream strm;\n    unsigned char in[CHUNK];\n    unsigned char out[CHUNK];\n\n    /* allocate inflate state */\n    strm.zalloc = Z_NULL;\n    strm.zfree = Z_NULL;\n    strm.opaque = Z_NULL;\n    strm.avail_in = 0;\n    strm.next_in = Z_NULL;\n    ret = inflateInit(&strm);\n    if (ret != Z_OK)\n        return ret;\n\n    /* decompress until deflate stream ends or end of file */\n    do {\n        strm.avail_in = fread(in, 1, CHUNK, source);\n        if (ferror(source)) {\n            (void)inflateEnd(&strm);\n            return Z_ERRNO;\n        }\n        if (strm.avail_in == 0)\n            break;\n        strm.next_in = in;\n\n        /* run inflate() on input until output buffer not full */\n        do {\n            strm.avail_out = CHUNK;\n            strm.next_out = out;\n            ret = inflate(&strm, Z_NO_FLUSH);\n            assert(ret != Z_STREAM_ERROR);  /* state not clobbered */\n            switch (ret) {\n            case Z_NEED_DICT:\n                ret = Z_DATA_ERROR;     /* and fall through */\n            case Z_DATA_ERROR:\n            case Z_MEM_ERROR:\n                (void)inflateEnd(&strm);\n                return ret;\n            }\n            have = special_min(limit, CHUNK - strm.avail_out) - skip;\n            if (fwrite(&out[skip], have, 1, dest) != 1 || ferror(dest)) {\n                (void)inflateEnd(&strm);\n                return Z_ERRNO;\n            }\n\t    skip = 0;\n\t    limit -= have;\n        } while (strm.avail_out == 0 && limit > 0);\n\n        /* done when inflate() says it's done */\n    } while (ret != Z_STREAM_END && limit > 0);\n\n    /* clean up and return */\n    (void)inflateEnd(&strm);\n    return (limit == 0 ? Z_OK : (ret == Z_STREAM_END ? Z_OK : Z_DATA_ERROR));\n}\n\n/* report a zlib or i/o error */\nstatic void zerr(int ret)\n{\n    switch (ret) {\n    case Z_ERRNO:\n        if (ferror(stdin))\n            fputs(\"error reading stdin\\n\", stderr);\n        if (ferror(stdout))\n            fputs(\"error writing stdout\\n\", stderr);\n        break;\n    case Z_STREAM_ERROR:\n        fputs(\"invalid compression level\\n\", stderr);\n        break;\n    case Z_DATA_ERROR:\n        fputs(\"invalid or incomplete deflate data\\n\", stderr);\n        break;\n    case Z_MEM_ERROR:\n        fputs(\"out of memory\\n\", stderr);\n        break;\n    case Z_VERSION_ERROR:\n        fputs(\"zlib version mismatch!\\n\", stderr);\n    }\n}\n\nstatic unsigned int get_num(char *str)\n{\n\tif (!strncmp(\"0x\", str, 2))\n\t\treturn strtoul(str+2, NULL, 16);\n\telse\n\t\treturn strtoul(str, NULL, 10);\n}\n\nstatic void usage(void)\n{\n\tfprintf(stderr, \"Usage: fritz_cal_extract [-s seek offset] [-i skip] [-o output file] [-l limit] [infile] -e entry_id\\n\"\n\t\t\t\"Finds and extracts zlib compressed calibration data in the EVA loader\\n\");\n\texit(EXIT_FAILURE);\n}\n\nstruct cal_entry {\n\tuint16_t id;\n\tuint16_t len;\n} __attribute__((packed));\n\n/* compress or decompress from stdin to stdout */\nint main(int argc, char **argv)\n{\n\tstruct cal_entry cal = { .len = 0 };\n\tFILE *in = stdin;\n\tFILE *out = stdout;\n\tsize_t limit = 0, skip = 0;\n\tint initial_offset = 0;\n\tint entry = -1;\n\tint ret;\n\tint opt;\n\n\twhile ((opt = getopt(argc, argv, \"s:e:o:l:i:\")) != -1) {\n\t\tswitch (opt) {\n\t\tcase 's':\n\t\t\tinitial_offset = (int)get_num(optarg);\n\t\t\tif (errno) {\n\t\t\t\tperror(\"Failed to parse seek offset\");\n\t\t\t\tgoto out_bad;\n\t\t\t}\n\t\t\tbreak;\n\t\tcase 'e':\n\t\t\tentry = (int) htobe16(get_num(optarg));\n\t\t\tif (errno) {\n\t\t\t\tperror(\"Failed to entry id\");\n\t\t\t\tgoto out_bad;\n\t\t\t}\n\t\t\tbreak;\n\t\tcase 'o':\n\t\t\tout = fopen(optarg, \"w\");\n\t\t\tif (!out) {\n\t\t\t\tperror(\"Failed to create output file\");\n\t\t\t\tgoto out_bad;\n\t\t\t}\n\t\t\tbreak;\n\t\tcase 'l':\n\t\t\tlimit = (size_t)get_num(optarg);\n\t\t\tif (errno) {\n\t\t\t\tperror(\"Failed to parse limit\");\n\t\t\t\tgoto out_bad;\n\t\t\t}\n\t\t\tbreak;\n\t\tcase 'i':\n\t\t\tskip = (size_t)get_num(optarg);\n\t\t\tif (errno) {\n\t\t\t\tperror(\"Failed to parse skip\");\n\t\t\t\tgoto out_bad;\n\t\t\t}\n\t\t\tbreak;\n\t\tdefault: /* '?' */\n\t\t\tusage();\n\t\t}\n\t}\n\n\tif (entry == -1)\n\t\tusage();\n\n\tif (argc > 1 && optind <= argc) {\n\t\tin = fopen(argv[optind], \"r\");\n\t\tif (!in) {\n\t\t\tperror(\"Failed to create output file\");\n\t\t\tgoto out_bad;\n\t\t}\n\t}\n\n\tif (initial_offset) {\n\t\tret = fseek(in, initial_offset, SEEK_CUR);\n\t\tif (ret) {\n\t\t\tperror(\"Failed to seek to calibration table\");\n\t\t\tgoto out_bad;\n\t\t}\n\t}\n\n\tdo {\n\t\tret = fseek(in, be16toh(cal.len), SEEK_CUR);\n\t\tif (feof(in)) {\n\t\t\tfprintf(stderr, \"Reached end of file, but didn't find the matching entry\\n\");\n\t\t\tgoto out_bad;\n\t\t} else if (ferror(in)) {\n\t\t\tperror(\"Failure during seek\");\n\t\t\tgoto out_bad;\n\t\t}\n\n\t\tret = fread(&cal, 1, sizeof cal, in);\n\t\tif (ret != sizeof cal)\n\t\t\tgoto out_bad;\n\t} while (entry != cal.id || cal.id == 0xffff);\n\n\tif (cal.id == 0xffff) {\n\t\tfprintf(stderr, \"Reached end of filesystem, but didn't find the matching entry\\n\");\n\t\tgoto out_bad;\n\t}\n\n\tret = inf(in, out, limit, skip);\n\tif (ret == Z_OK)\n\t\tgoto out;\n\n\tzerr(ret);\n\nout_bad:\n\tret = EXIT_FAILURE;\n\nout:\n\tfclose(in);\n\tfclose(out);\n\treturn ret;\n}\n"
  },
  {
    "path": "package/utils/fritz-tools/src/fritz_tffs_nand_read.c",
    "content": "/*\n * A tool for reading the TFFS partitions (a name-value storage usually\n * found in AVM Fritz!Box based devices) on nand flash.\n *\n * Copyright (c) 2018 Valentin Spreckels <Valentin.Spreckels@Informatik.Uni-Oldenburg.DE>\n *\n * Based on the fritz_tffs_read tool:\n *     Copyright (c) 2015-2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>\n * and on the TFFS 2.0 kernel driver from AVM:\n *     Copyright (c) 2004-2007 AVM GmbH <fritzbox_info@avm.de>\n * and the TFFS 3.0 kernel driver from AVM:\n *     Copyright (C) 2004-2014 AVM GmbH <fritzbox_info@avm.de>\n * and the OpenWrt TFFS kernel driver:\n *     Copyright (c) 2013 John Crispin <john@phrozen.org>\n *\n * This program is free software; you can redistribute it and/or modify\n * it under the terms of the GNU General Public License as published by\n * the Free Software Foundation; either version 2 of the License, or\n * (at your option) any later version.\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n * GNU General Public License for more details.\n *\n * You should have received a copy of the GNU General Public License along\n * with this program; if not, write to the Free Software Foundation, Inc.,\n * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.\n */\n\n#include <stdbool.h>\n#include <stddef.h>\n#include <stdio.h>\n#include <stdlib.h>\n#include <stdint.h>\n#include <string.h>\n#include <libgen.h>\n#include <getopt.h>\n#include <unistd.h>\n#include <fcntl.h>\n#include <endian.h>\n#include <sys/ioctl.h>\n#include <sys/types.h>\n#include <sys/stat.h>\n#include <arpa/inet.h>\n#include <mtd/mtd-user.h>\n#include <assert.h>\n\n#define DEFAULT_TFFS_SIZE\t(256 * 1024)\n\n#define TFFS_ID_END\t\t0xffffffff\n#define TFFS_ID_TABLE_NAME\t0x000001ff\n\n#define TFFS_BLOCK_HEADER_MAGIC\t0x41564d5f54464653ULL\n#define TFFS_VERSION\t\t0x0003\n#define TFFS_ENTRY_HEADER_SIZE\t0x18\n#define TFFS_MAXIMUM_SEGMENT_SIZE\t(0x800 - TFFS_ENTRY_HEADER_SIZE)\n\n#define TFFS_SECTOR_SIZE 0x0800\n#define TFFS_SECTOR_OOB_SIZE 0x0040\n#define TFFS_SECTORS_PER_PAGE 2\n\n#define TFFS_SEGMENT_CLEARED 0xffffffff\n\nstatic char *progname;\nstatic char *mtddev;\nstatic char *name_filter = NULL;\nstatic bool show_all = false;\nstatic bool print_all_key_names = false;\nstatic bool read_oob_sector_health = false;\nstatic bool swap_bytes = false;\nstatic uint8_t readbuf[TFFS_SECTOR_SIZE];\nstatic uint8_t oobbuf[TFFS_SECTOR_OOB_SIZE];\nstatic uint32_t blocksize;\nstatic int mtdfd;\nstruct tffs_sectors *sectors;\n\nstruct tffs_sectors {\n\tuint32_t num_sectors;\n\tuint8_t sectors[0];\n};\n\nstatic inline void sector_mark_bad(int num)\n{\n\tsectors->sectors[num / 8] &= ~(0x80 >> (num % 8));\n};\n\nstatic inline uint8_t sector_get_good(int num)\n{\n\treturn sectors->sectors[num / 8] & 0x80 >> (num % 8);\n};\n\nstruct tffs_entry_segment {\n\tuint32_t len;\n\tvoid *val;\n};\n\nstruct tffs_entry {\n\tuint32_t len;\n\tvoid *val;\n};\n\nstruct tffs_name_table_entry {\n\tuint32_t id;\n\tchar *val;\n};\n\nstruct tffs_key_name_table {\n\tuint32_t size;\n\tstruct tffs_name_table_entry *entries;\n};\n\nstatic inline uint8_t read_uint8(void *buf, ptrdiff_t off)\n{\n\treturn *(uint8_t *)(buf + off);\n}\n\nstatic inline uint32_t read_uint32(void *buf, ptrdiff_t off)\n{\n\tuint32_t tmp = *(uint32_t *)(buf + off);\n\tif (swap_bytes) {\n\t\ttmp = be32toh(tmp);\n\t}\n\treturn tmp;\n}\n\nstatic inline uint64_t read_uint64(void *buf, ptrdiff_t off)\n{\n\tuint64_t tmp = *(uint64_t *)(buf + off);\n\tif (swap_bytes) {\n\t\ttmp = be64toh(tmp);\n\t}\n\treturn tmp;\n}\n\nstatic int read_sector(off_t pos)\n{\n\tif (pread(mtdfd, readbuf, TFFS_SECTOR_SIZE, pos) != TFFS_SECTOR_SIZE) {\n\t\treturn -1;\n\t}\n\n\treturn 0;\n}\n\nstatic int read_sectoroob(off_t pos)\n{\n\tstruct mtd_oob_buf oob = {\n\t\t.start = pos,\n\t\t.length = TFFS_SECTOR_OOB_SIZE,\n\t\t.ptr = oobbuf\n\t};\n\n\tif (ioctl(mtdfd, MEMREADOOB, &oob) < 0)\t{\n\t\treturn -1;\n\t}\n\n\treturn 0;\n}\n\nstatic inline uint32_t get_walk_size(uint32_t entry_len)\n{\n\treturn (entry_len + 3) & ~0x03;\n}\n\nstatic void print_entry_value(const struct tffs_entry *entry)\n{\n\t/* These are NOT NULL terminated. */\n\tfwrite(entry->val, 1, entry->len, stdout);\n}\n\nstatic int find_entry(uint32_t id, struct tffs_entry *entry)\n{\n\tuint32_t rev = 0;\n\tuint32_t num_segments = 0;\n\tstruct tffs_entry_segment *segments = NULL;\n\n\toff_t pos = 0;\n\tuint8_t block_end = 0;\n\tfor (uint32_t sector = 0; sector < sectors->num_sectors; sector++, pos += TFFS_SECTOR_SIZE) {\n\t\tif (block_end) {\n\t\t\tif (pos % blocksize == 0) {\n\t\t\t\tblock_end = 0;\n\t\t\t}\n\t\t} else if (sector_get_good(sector)) {\n\t\t\tif (read_sectoroob(pos) || read_sector(pos)) {\n\t\t\t\tfprintf(stderr, \"ERROR: sector isn't readable, but has been previously!\\n\");\n\t\t\t\texit(EXIT_FAILURE);\n\t\t\t}\n\t\t\tuint32_t oob_id = read_uint32(oobbuf, 0x02);\n\t\t\tuint32_t oob_len = read_uint32(oobbuf, 0x06);\n\t\t\tuint32_t oob_rev = read_uint32(oobbuf, 0x0a);\n\t\t\tuint32_t read_id = read_uint32(readbuf, 0x00);\n\t\t\tuint32_t read_len = read_uint32(readbuf, 0x04);\n\t\t\tuint32_t read_rev = read_uint32(readbuf, 0x0c);\n\t\t\tif (read_oob_sector_health && (oob_id != read_id || oob_len != read_len || oob_rev != read_rev)) {\n\t\t\t\tfprintf(stderr, \"Warning: sector has inconsistent metadata\\n\");\n\t\t\t\tcontinue;\n\t\t\t}\n\t\t\tif (read_id == TFFS_ID_END) {\n\t\t\t\t/* no more entries in this block */\n\t\t\t\tblock_end = 1;\n\t\t\t\tcontinue;\n\t\t\t}\n\t\t\tif (read_len > TFFS_MAXIMUM_SEGMENT_SIZE) {\n\t\t\t\tfprintf(stderr, \"Warning: segment is longer than possible\\n\");\n\t\t\t\tcontinue;\n\t\t\t}\n\t\t\tif (read_id == id) {\n\t\t\t\tif (read_rev < rev) {\n\t\t\t\t\t/* obsolete revision => ignore this */\n\t\t\t\t\tcontinue;\n\t\t\t\t}\n\t\t\t\tif (read_rev > rev) {\n\t\t\t\t\t/* newer revision => clear old data */\n\t\t\t\t\tfor (uint32_t i = 0; i < num_segments; i++) {\n\t\t\t\t\t\tfree(segments[i].val);\n\t\t\t\t\t}\n\t\t\t\t\tfree (segments);\n\t\t\t\t\trev = read_rev;\n\t\t\t\t\tnum_segments = 0;\n\t\t\t\t\tsegments = NULL;\n\t\t\t\t}\n\n\t\t\t\tuint32_t seg = read_uint32(readbuf, 0x10);\n\n\t\t\t\tif (seg == TFFS_SEGMENT_CLEARED) {\n\t\t\t\t\tcontinue;\n\t\t\t\t}\n\n\t\t\t\tuint32_t next_seg = read_uint32(readbuf, 0x14);\n\n\t\t\t\tuint32_t new_num_segs = next_seg == 0 ? seg + 1 : next_seg + 1;\n\t\t\t\tif (new_num_segs > num_segments) {\n\t\t\t\t\tsegments = realloc(segments, new_num_segs * sizeof(struct tffs_entry_segment));\n\t\t\t\t\tmemset(segments + (num_segments * sizeof(struct tffs_entry_segment)), 0x0,\n\t\t\t\t\t\t\t(new_num_segs - num_segments) * sizeof(struct tffs_entry_segment));\n\t\t\t\t\tnum_segments = new_num_segs;\n\t\t\t\t}\n\t\t\t\tsegments[seg].len = read_len;\n\t\t\t\tsegments[seg].val = malloc(read_len);\n\t\t\t\tmemcpy(segments[seg].val, readbuf + TFFS_ENTRY_HEADER_SIZE, read_len);\n\t\t\t}\n\t\t}\n\t}\n\n\tif (num_segments == 0) {\n\t\treturn 0;\n\t}\n\n\tassert (segments != NULL);\n\n\tuint32_t len = 0;\n\tfor (uint32_t i = 0; i < num_segments; i++) {\n\t\tif (segments[i].val == NULL) {\n\t\t\t/* missing segment */\n\t\t\treturn 0;\n\t\t}\n\n\t\tlen += segments[i].len;\n\t}\n\n\tvoid *p = malloc(len);\n\tentry->val = p;\n\tentry->len = len;\n\tfor (uint32_t i = 0; i < num_segments; i++) {\n\t\tmemcpy(p, segments[i].val, segments[i].len);\n\t\tp += segments[i].len;\n\t}\n\n\treturn 1;\n}\n\nstatic void parse_key_names(struct tffs_entry *names_entry,\n\t\t\t     struct tffs_key_name_table *key_names)\n{\n\tuint32_t pos = 0, i = 0;\n\tstruct tffs_name_table_entry *name_item;\n\n\tkey_names->entries = NULL;\n\n\tdo {\n\t\tkey_names->entries = realloc(key_names->entries,\n\t\t\t sizeof(struct tffs_name_table_entry) * (i + 1));\n\t\tif (key_names->entries == NULL) {\n\t\t\tfprintf(stderr, \"ERROR: memory allocation failed!\\n\");\n\t\t\texit(EXIT_FAILURE);\n\t\t}\n\t\tname_item = &key_names->entries[i];\n\n\t\tname_item->id = read_uint32(names_entry->val, pos);\n\t\tpos += sizeof(uint32_t);\n\t\tname_item->val = strdup((const char *)(names_entry->val + pos));\n\n\t\t/*\n\t\t * There is no \"length\" field because the string values are\n\t\t * simply NULL-terminated -> strlen() gives us the size.\n\t\t */\n\t\tpos += get_walk_size(strlen(name_item->val) + 1);\n\n\t\t++i;\n\t} while (pos < names_entry->len);\n\n\tkey_names->size = i;\n}\n\nstatic void show_all_key_names(struct tffs_key_name_table *key_names)\n{\n\tfor (uint32_t i = 0; i < key_names->size; i++)\n\t\tprintf(\"%s\\n\", key_names->entries[i].val);\n}\n\nstatic int show_all_key_value_pairs(struct tffs_key_name_table *key_names)\n{\n\tuint8_t has_value = 0;\n\tstruct tffs_entry tmp;\n\n\tfor (uint32_t i = 0; i < key_names->size; i++) {\n\t\tif (find_entry(key_names->entries[i].id, &tmp)) {\n\t\t\tprintf(\"%s=\", (const char *)key_names->entries[i].val);\n\t\t\tprint_entry_value(&tmp);\n\t\t\tprintf(\"\\n\");\n\t\t\thas_value++;\n\t\t\tfree(tmp.val);\n\t\t}\n\t}\n\n\tif (!has_value) {\n\t\tfprintf(stderr, \"ERROR: no values found!\\n\");\n\t\treturn EXIT_FAILURE;\n\t}\n\n\treturn EXIT_SUCCESS;\n}\n\nstatic int show_matching_key_value(struct tffs_key_name_table *key_names)\n{\n\tstruct tffs_entry tmp;\n\tconst char *name;\n\n\tfor (uint32_t i = 0; i < key_names->size; i++) {\n\t\tname = key_names->entries[i].val;\n\n\t\tif (strcmp(name, name_filter) == 0) {\n\t\t\tif (find_entry(key_names->entries[i].id, &tmp)) {\n\t\t\t\tprint_entry_value(&tmp);\n\t\t\t\tprintf(\"\\n\");\n\t\t\t\tfree(tmp.val);\n\t\t\t\treturn EXIT_SUCCESS;\n\t\t\t} else {\n\t\t\t\tfprintf(stderr,\n\t\t\t\t\t\"ERROR: no value found for name %s!\\n\",\n\t\t\t\t\tname);\n\t\t\t\treturn EXIT_FAILURE;\n\t\t\t}\n\t\t}\n\t}\n\n\tfprintf(stderr, \"ERROR: Unknown key name %s!\\n\", name_filter);\n\treturn EXIT_FAILURE;\n}\n\nstatic int check_sector(off_t pos)\n{\n\tif (!read_oob_sector_health) {\n\t\treturn 1;\n\t}\n\tif (read_sectoroob(pos)) {\n\t\treturn 0;\n\t}\n\tif (read_uint8(oobbuf, 0x00) != 0xff) {\n\t\t/* block is bad */\n\t\treturn 0;\n\t}\n\tif (read_uint8(oobbuf, 0x01) != 0xff) {\n\t\t/* sector is bad */\n\t\treturn 0;\n\t}\n\treturn 1;\n}\n\nstatic int check_block(off_t pos, uint32_t sector)\n{\n\tif (!check_sector(pos)) {\n\t\treturn 0;\n\t}\n\tif (read_sector(pos)) {\n\t\treturn 0;\n\t}\n\tif (read_uint64(readbuf, 0x00) != TFFS_BLOCK_HEADER_MAGIC) {\n\t\tfprintf(stderr, \"Warning: block without magic header. Skipping block\\n\");\n\t\treturn 0;\n\t}\n\tif (read_uint32(readbuf, 0x0c) != TFFS_SECTORS_PER_PAGE) {\n\t\tfprintf(stderr, \"Warning: block with wrong number of sectors per page. Skipping block\\n\");\n\t\treturn 0;\n\t}\n\n\tuint32_t num_hdr_bad = read_uint32(readbuf, 0x0c);\n\tfor (uint32_t i = 0; i < num_hdr_bad; i++) {\n\t\tuint32_t bad = sector + read_uint64(readbuf, 0x1c + sizeof(uint64_t)*i);\n\t\tsector_mark_bad(bad);\n\t}\n\n\treturn 1;\n}\n\nstatic int scan_mtd(void)\n{\n\tstruct mtd_info_user info;\n\n\tif (ioctl(mtdfd, MEMGETINFO, &info)) {\n\t\treturn 0;\n\t}\n\n\tblocksize = info.erasesize;\n\n\tsectors = malloc(sizeof(*sectors) + (info.size / TFFS_SECTOR_SIZE + 7) / 8);\n\tif (sectors == NULL) {\n\t\tfprintf(stderr, \"ERROR: memory allocation failed!\\n\");\n\t\texit(EXIT_FAILURE);\n\t}\n\tsectors->num_sectors = info.size / TFFS_SECTOR_SIZE;\n\tmemset(sectors->sectors, 0xff, (info.size / TFFS_SECTOR_SIZE + 7) / 8);\n\n\tuint32_t sector = 0, valid_blocks = 0;\n\tuint8_t block_ok = 0;\n\tfor (off_t pos = 0; pos < info.size; sector++, pos += TFFS_SECTOR_SIZE) {\n\t\tif (pos % info.erasesize == 0) {\n\t\t\tblock_ok = check_block(pos, sector);\n\t\t\t/* first sector of the block contains metadata\n\t\t\t   => handle it like a bad sector */\n\t\t\tsector_mark_bad(sector);\n\t\t\tif (block_ok) {\n\t\t\t\tvalid_blocks++;\n\t\t\t}\n\t\t} else if (!block_ok || !sector_get_good(sector) || !check_sector(pos)) {\n\t\t\tsector_mark_bad(sector);\n\t\t}\n\t}\n\n\treturn valid_blocks;\n}\n\nstatic void usage(int status)\n{\n\tFILE *stream = (status != EXIT_SUCCESS) ? stderr : stdout;\n\n\tfprintf(stream, \"Usage: %s [OPTIONS...]\\n\", progname);\n\tfprintf(stream,\n\t\"\\n\"\n\t\"Options:\\n\"\n\t\"  -a              list all key value pairs found in the TFFS file/device\\n\"\n\t\"  -d <mtd>        inspect the TFFS on mtd device <mtd>\\n\"\n\t\"  -h              show this screen\\n\"\n\t\"  -l              list all supported keys\\n\"\n\t\"  -n <key name>   display the value of the given key\\n\"\n\t\"  -o              read OOB information about sector health\\n\"\n\t);\n\n\texit(status);\n}\n\nstatic void parse_options(int argc, char *argv[])\n{\n\twhile (1) {\n\t\tint c;\n\n\t\tc = getopt(argc, argv, \"abd:hln:o\");\n\t\tif (c == -1)\n\t\t\tbreak;\n\n\t\tswitch (c) {\n\t\tcase 'a':\n\t\t\tshow_all = true;\n\t\t\tname_filter = NULL;\n\t\t\tprint_all_key_names = false;\n\t\t\tbreak;\n\t\tcase 'b':\n\t\t\tswap_bytes = 1;\n\t\t\tbreak;\n\t\tcase 'd':\n\t\t\tmtddev = optarg;\n\t\t\tbreak;\n\t\tcase 'h':\n\t\t\tusage(EXIT_SUCCESS);\n\t\t\tbreak;\n\t\tcase 'l':\n\t\t\tprint_all_key_names = true;\n\t\t\tshow_all = false;\n\t\t\tname_filter = NULL;\n\t\t\tbreak;\n\t\tcase 'n':\n\t\t\tname_filter = optarg;\n\t\t\tshow_all = false;\n\t\t\tprint_all_key_names = false;\n\t\t\tbreak;\n\t\tcase 'o':\n\t\t\tread_oob_sector_health = true;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tusage(EXIT_FAILURE);\n\t\t\tbreak;\n\t\t}\n\t}\n\n\tif (!mtddev) {\n\t\tfprintf(stderr, \"ERROR: No input file (-d <file>) given!\\n\");\n\t\tusage(EXIT_FAILURE);\n\t}\n\n\tif (!show_all && !name_filter && !print_all_key_names) {\n\t\tfprintf(stderr,\n\t\t\t\"ERROR: either -l, -a or -n <key name> is required!\\n\");\n\t\tusage(EXIT_FAILURE);\n\t}\n}\n\nint main(int argc, char *argv[])\n{\n\tint ret = EXIT_FAILURE;\n\tstruct tffs_entry name_table;\n\tstruct tffs_key_name_table key_names;\n\n\tprogname = basename(argv[0]);\n\n\tparse_options(argc, argv);\n\n\tmtdfd = open(mtddev, O_RDONLY);\n\tif (mtdfd < 0) {\n\t\tfprintf(stderr, \"ERROR: Failed to open tffs device %s\\n\",\n\t\t\tmtddev);\n\t\tgoto out;\n\t}\n\n\tif (!scan_mtd()) {\n\t\tfprintf(stderr, \"ERROR: Parsing blocks from tffs device %s failed\\n\", mtddev);\n\t\tfprintf(stderr, \"       Is byte-swapping (-b) required?\\n\");\n\t\tgoto out_close;\n\t}\n\n\tif (!find_entry(TFFS_ID_TABLE_NAME, &name_table)) {\n\t\tfprintf(stderr, \"ERROR: No name table found on tffs device %s\\n\",\n\t\t\tmtddev);\n\t\tgoto out_free_sectors;\n\t}\n\n\tparse_key_names(&name_table, &key_names);\n\tif (key_names.size < 1) {\n\t\tfprintf(stderr, \"ERROR: No name table found on tffs device %s\\n\",\n\t\t\tmtddev);\n\t\tgoto out_free_entry;\n\t}\n\n\tif (print_all_key_names) {\n\t\tshow_all_key_names(&key_names);\n\t\tret = EXIT_SUCCESS;\n\t} else if (show_all) {\n\t\tret = show_all_key_value_pairs(&key_names);\n\t} else {\n\t\tret = show_matching_key_value(&key_names);\n\t}\n\n\tfree(key_names.entries);\nout_free_entry:\n\tfree(name_table.val);\nout_free_sectors:\n\tfree(sectors);\nout_close:\n\tclose(mtdfd);\nout:\n\treturn ret;\n}\n"
  },
  {
    "path": "package/utils/fritz-tools/src/fritz_tffs_read.c",
    "content": "/*\n * A tool for reading the TFFS partitions (a name-value storage usually\n * found in AVM Fritz!Box based devices).\n *\n * Copyright (c) 2015-2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>\n *\n * Based on the TFFS 2.0 kernel driver from AVM:\n *     Copyright (c) 2004-2007 AVM GmbH <fritzbox_info@avm.de>\n * and the OpenWrt TFFS kernel driver:\n *     Copyright (c) 2013 John Crispin <blogic@openwrt.org>\n *\n * This program is free software; you can redistribute it and/or modify\n * it under the terms of the GNU General Public License as published by\n * the Free Software Foundation; either version 2 of the License, or\n * (at your option) any later version.\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n * GNU General Public License for more details.\n *\n * You should have received a copy of the GNU General Public License along\n * with this program; if not, write to the Free Software Foundation, Inc.,\n * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.\n */\n\n#include <stdbool.h>\n#include <stdio.h>\n#include <stdlib.h>\n#include <stdint.h>\n#include <string.h>\n#include <libgen.h>\n#include <getopt.h>\n#include <unistd.h>\n#include <sys/types.h>\n#include <sys/stat.h>\n#include <arpa/inet.h>\n\n#define TFFS_ID_END\t\t0xffff\n#define TFFS_ID_TABLE_NAME\t0x01ff\n\nstatic char *progname;\nstatic char *input_file;\nstatic unsigned long tffs_size;\nstatic char *name_filter = NULL;\nstatic bool show_all = false;\nstatic bool print_all_key_names = false;\nstatic bool swap_bytes = false;\n\nstruct tffs_entry_header {\n\tuint16_t id;\n\tuint16_t len;\n};\n\nstruct tffs_entry {\n\tconst struct tffs_entry_header *header;\n\tchar *name;\n\tuint8_t *val;\n};\n\nstruct tffs_name_table_entry {\n\tconst uint32_t *id;\n\tconst char *val;\n};\n\nstruct tffs_key_name_table {\n\tuint32_t size;\n\tstruct tffs_name_table_entry *entries;\n};\n\nstatic inline uint16_t get_header_len(const struct tffs_entry_header *header)\n{\n\tif (swap_bytes)\n\t\treturn ntohs(header->len);\n\n\treturn header->len;\n}\n\nstatic inline uint16_t get_header_id(const struct tffs_entry_header *header)\n{\n\tif (swap_bytes)\n\t\treturn ntohs(header->id);\n\n\treturn header->id;\n}\n\nstatic inline uint16_t to_entry_header_id(uint32_t name_id)\n{\n\tif (swap_bytes)\n\t\treturn ntohl(name_id) & 0xffff;\n\n\treturn name_id & 0xffff;\n}\n\nstatic inline uint32_t get_walk_size(uint32_t entry_len)\n{\n\treturn (entry_len + 3) & ~0x03;\n}\n\nstatic void print_entry_value(const struct tffs_entry *entry)\n{\n\tint i;\n\n\t/* These are NOT NULL terminated. */\n\tfor (i = 0; i < get_header_len(entry->header); i++)\n\t\tfprintf(stdout, \"%c\", entry->val[i]);\n}\n\nstatic void parse_entry(uint8_t *buffer, uint32_t pos,\n\t\t\tstruct tffs_entry *entry)\n{\n\tentry->header = (struct tffs_entry_header *) &buffer[pos];\n\tentry->val = &buffer[pos + sizeof(struct tffs_entry_header)];\n}\n\nstatic int find_entry(uint8_t *buffer, uint16_t id, struct tffs_entry *entry)\n{\n\tuint32_t pos = 0;\n\n\tdo {\n\t\tparse_entry(buffer, pos, entry);\n\n\t\tif (get_header_id(entry->header) == id)\n\t\t\treturn 1;\n\n\t\tpos += sizeof(struct tffs_entry_header);\n\t\tpos += get_walk_size(get_header_len(entry->header));\n\t} while (pos < tffs_size && entry->header->id != TFFS_ID_END);\n\n\treturn 0;\n}\n\nstatic void parse_key_names(struct tffs_entry *names_entry,\n\t\t\t    struct tffs_key_name_table *key_names)\n{\n\tuint32_t pos = 0, i = 0;\n\tstruct tffs_name_table_entry *name_item;\n\n\tkey_names->entries = calloc(sizeof(*name_item), 1);\n\n\tdo {\n\t\tname_item = &key_names->entries[i];\n\n\t\tname_item->id = (uint32_t *) &names_entry->val[pos];\n\t\tpos += sizeof(*name_item->id);\n\t\tname_item->val = (const char *) &names_entry->val[pos];\n\n\t\t/*\n\t\t * There is no \"length\" field because the string values are\n\t\t * simply NULL-terminated -> strlen() gives us the size.\n\t\t */\n\t\tpos += get_walk_size(strlen(name_item->val) + 1);\n\n\t\t++i;\n\t\tkey_names->entries = realloc(key_names->entries,\n\t\t\t\t\t\tsizeof(*name_item) * (i + 1));\n\t} while (pos < get_header_len(names_entry->header));\n\n\tkey_names->size = i;\n}\n\nstatic void show_all_key_names(struct tffs_key_name_table *key_names)\n{\n\tint i;\n\n\tfor (i = 0; i < key_names->size; i++)\n\t\tprintf(\"%s\\n\", key_names->entries[i].val);\n}\n\nstatic int show_all_key_value_pairs(uint8_t *buffer,\n\t\t\t\t    struct tffs_key_name_table *key_names)\n{\n\tint i, has_value = 0;\n\tuint16_t id;\n\tstruct tffs_entry tmp;\n\n\tfor (i = 0; i < key_names->size; i++) {\n\t\tid = to_entry_header_id(*key_names->entries[i].id);\n\n\t\tif (find_entry(buffer, id, &tmp)) {\n\t\t\tprintf(\"%s=\", key_names->entries[i].val);\n\t\t\tprint_entry_value(&tmp);\n\t\t\tprintf(\"\\n\");\n\t\t\thas_value++;\n\t\t}\n\t}\n\n\tif (!has_value) {\n\t\tfprintf(stderr, \"ERROR: no values found!\\n\");\n\t\treturn EXIT_FAILURE;\n\t}\n\n\treturn EXIT_SUCCESS;\n}\n\nstatic int show_matching_key_value(uint8_t *buffer,\n\t\t\t\t   struct tffs_key_name_table *key_names)\n{\n\tint i;\n\tuint16_t id;\n\tstruct tffs_entry tmp;\n\tconst char *name;\n\n\tfor (i = 0; i < key_names->size; i++) {\n\t\tname = key_names->entries[i].val;\n\n\t\tif (strcmp(name, name_filter) == 0) {\n\t\t\tid = to_entry_header_id(*key_names->entries[i].id);\n\n\t\t\tif (find_entry(buffer, id, &tmp)) {\n\t\t\t\tprint_entry_value(&tmp);\n\t\t\t\tprintf(\"\\n\");\n\t\t\t\treturn EXIT_SUCCESS;\n\t\t\t} else {\n\t\t\t\tfprintf(stderr,\n\t\t\t\t\t\"ERROR: no value found for name %s!\\n\",\n\t\t\t\t\tname);\n\t\t\t\treturn EXIT_FAILURE;\n\t\t\t}\n\t\t}\n\t}\n\n\tfprintf(stderr, \"ERROR: Unknown key name %s!\\n\", name_filter);\n\treturn EXIT_FAILURE;\n}\n\nstatic void usage(int status)\n{\n\tFILE *stream = (status != EXIT_SUCCESS) ? stderr : stdout;\n\n\tfprintf(stream, \"Usage: %s [OPTIONS...]\\n\", progname);\n\tfprintf(stream,\n\t\"\\n\"\n\t\"Options:\\n\"\n\t\"  -a              list all key value pairs found in the TFFS file/device\\n\"\n\t\"  -b              swap bytes while parsing the TFFS file/device\\n\"\n\t\"  -h              show this screen\\n\"\n\t\"  -i <file>       inspect the given TFFS file/device <file>\\n\"\n\t\"  -l              list all supported keys\\n\"\n\t\"  -n <key name>   display the value of the given key\\n\"\n\t\"  -s <size>       the (max) size of the TFFS file/device <size>\\n\"\n\t);\n\n\texit(status);\n}\n\nstatic int file_exist(char *filename)\n{\n\tstruct stat buffer;\n\n\treturn stat(filename, &buffer) == 0;\n}\n\nstatic void parse_options(int argc, char *argv[])\n{\n\twhile (1)\n\t{\n\t\tint c;\n\n\t\tc = getopt(argc, argv, \"abhi:ln:s:\");\n\t\tif (c == -1)\n\t\t\tbreak;\n\n\t\tswitch (c) {\n\t\t\tcase 'a':\n\t\t\t\tshow_all = true;\n\t\t\t\tname_filter = NULL;\n\t\t\t\tprint_all_key_names = false;\n\t\t\t\tbreak;\n\t\t\tcase 'b':\n\t\t\t\tswap_bytes = 1;\n\t\t\t\tbreak;\n\t\t\tcase 'h':\n\t\t\t\tusage(EXIT_SUCCESS);\n\t\t\t\tbreak;\n\t\t\tcase 'i':\n\t\t\t\tinput_file = optarg;\n\t\t\t\tbreak;\n\t\t\tcase 'l':\n\t\t\t\tprint_all_key_names = true;\n\t\t\t\tshow_all = false;\n\t\t\t\tname_filter = NULL;\n\t\t\t\tbreak;\n\t\t\tcase 'n':\n\t\t\t\tname_filter = optarg;\n\t\t\t\tshow_all = false;\n\t\t\t\tprint_all_key_names = false;\n\t\t\t\tbreak;\n\t\t\tcase 's':\n\t\t\t\ttffs_size = strtoul(optarg, NULL, 0);\n\t\t\t\tbreak;\n\t\t\tdefault:\n\t\t\t\tusage(EXIT_FAILURE);\n\t\t\t\tbreak;\n\t\t}\n\t}\n\n\tif (!input_file) {\n\t\tfprintf(stderr, \"ERROR: No input file (-i <file>) given!\\n\");\n\t\texit(EXIT_FAILURE);\n\t}\n\n\tif (!file_exist(input_file)) {\n\t\tfprintf(stderr, \"ERROR: %s does not exist\\n\", input_file);\n\t\texit(EXIT_FAILURE);\n\t}\n\n\tif (!show_all && !name_filter && !print_all_key_names) {\n\t\tfprintf(stderr,\n\t\t\t\"ERROR: either -l, -a or -n <key name> is required!\\n\");\n\t\texit(EXIT_FAILURE);\n\t}\n}\n\nint main(int argc, char *argv[])\n{\n\tint ret = EXIT_FAILURE;\n\tuint8_t *buffer;\n\tFILE *fp;\n\tstruct tffs_entry name_table;\n\tstruct tffs_key_name_table key_names;\n\n\tprogname = basename(argv[0]);\n\n\tparse_options(argc, argv);\n\n\tfp = fopen(input_file, \"r\");\n\n\tif (!fp) {\n\t\tfprintf(stderr, \"ERROR: Failed to open tffs input file %s\\n\",\n\t\t\tinput_file);\n\t\tgoto out;\n\t}\n\n\tif (tffs_size == 0) {\n\t\tfseek(fp, 0L, SEEK_END);\n\t\ttffs_size = ftell(fp);\n\t\tfseek(fp, 0L, SEEK_SET);\n\t}\n\n\tbuffer = malloc(tffs_size);\n\n\tif (fread(buffer, 1, tffs_size, fp) != tffs_size) {\n\t\tfprintf(stderr, \"ERROR: Failed read tffs file %s\\n\",\n\t\t\tinput_file);\n\t\tgoto out_free;\n\t}\n\n\tif (!find_entry(buffer, TFFS_ID_TABLE_NAME, &name_table)) {\n\t\tfprintf(stderr,\"ERROR: No name table found in tffs file %s\\n\",\n\t\t\tinput_file);\n\t\tfprintf(stderr,\"       Is byte-swapping (-b) required?\\n\");\n\t\tgoto out_free;\n\t}\n\n\tparse_key_names(&name_table, &key_names);\n\tif (key_names.size < 1) {\n\t\tfprintf(stderr, \"ERROR: No name table found in tffs file %s\\n\",\n\t\t\tinput_file);\n\t\tgoto out_free_names;\n\t}\n\n\tif (print_all_key_names) {\n\t\tshow_all_key_names(&key_names);\n\t\tret = EXIT_SUCCESS;\n\t} else if (show_all) {\n\t\tret = show_all_key_value_pairs(buffer, &key_names);\n\t} else {\n\t\tret = show_matching_key_value(buffer, &key_names);\n\t}\n\nout_free_names:\n\tfree(key_names.entries);\nout_free:\n\tfclose(fp);\n\tfree(buffer);\nout:\n\treturn ret;\n}\n"
  },
  {
    "path": "package/utils/jboot-tools/Makefile",
    "content": "include $(TOPDIR)/rules.mk\n\nPKG_NAME:=jboot-tools\nPKG_RELEASE:=1\nCMAKE_INSTALL:=1\nPKG_FLAGS:=nonshared\n\ninclude $(INCLUDE_DIR)/package.mk\ninclude $(INCLUDE_DIR)/cmake.mk\n\ndefine Package/jboot-tools\n  SECTION:=firmware\n  CATEGORY:=Firmware\n  DEPENDS:=@TARGET_ramips\n  TITLE:=Utilites for accessing JBOOT based D-Link devices Calibration data\nendef\n\ndefine Package/jboot-tools/description\n This package contains:\n jboot_config_read.c: partially read the config partition of JBOOT based D-Link devices.\nendef\n\ndefine Package/jboot-tools/install\n\t$(INSTALL_DIR) $(1)/usr/bin\n\t$(INSTALL_BIN) $(PKG_BUILD_DIR)/jboot_config_read $(1)/usr/bin/\nendef\n\n$(eval $(call BuildPackage,jboot-tools))\n"
  },
  {
    "path": "package/utils/jboot-tools/README.md",
    "content": "Userspace utilties for jboot based devices config partition read\n\n## Building\n\n```\nmkdir build\ncd build\ncmake /path/to/jboot-tools\nmake\n```\n\n## Usage\n\nAll command line parameters are documented:\n```\njboot_config_read -h\n```\n\nShow all stored MACs:\n```\njboot_config_read -m -i PATH_TO_CONFIG_PARTITIO\n```\n\nExtract wifi eeprom data:\n```\njboot_config_read  -i PATH_TO_CONFIG_PARTITION -e OUTPUT_PATH\n```\n\n\n## LICENSE\n\nSee `LICENSE`:\n\n    This program is free software; you can redistribute it and/or modify\n    it under the terms of the GNU General Public License as published by\n    the Free Software Foundation; either version 2 of the License, or\n    (at your option) any later version.\n\n    This program is distributed in the hope that it will be useful,\n    but WITHOUT ANY WARRANTY; without even the implied warranty of\n    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n    GNU General Public License for more details.\n\n    You should have received a copy of the GNU General Public License along\n    with this program; if not, write to the Free Software Foundation, Inc.,\n    51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.\n"
  },
  {
    "path": "package/utils/jboot-tools/src/CMakeLists.txt",
    "content": "cmake_minimum_required(VERSION 2.6)\n\nPROJECT(jboot-tools C)\nADD_DEFINITIONS(-Wall -Werror --std=gnu99 -Wmissing-declarations)\n\nSET(CMAKE_SHARED_LIBRARY_LINK_C_FLAGS \"\")\n\nADD_EXECUTABLE(jboot_config_read jboot_config_read.c)\nTARGET_LINK_LIBRARIES(jboot_config_read)\n\nINSTALL(TARGETS jboot_config_read RUNTIME DESTINATION bin)\n"
  },
  {
    "path": "package/utils/jboot-tools/src/jboot_config_read.c",
    "content": "/*\n * jboot_config_read\n *\n * Copyright (C) 2018 Paweł Dembicki <paweldembicki@gmail.com>\n *\n * This tool is based on mkdlinkfw.\n * Copyright (C) 2018 Paweł Dembicki <paweldembicki@gmail.com>\n * Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>\n * Copyright (C) 2008,2009 Wang Jian <lark@linux.net.cn>\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of the GNU General Public License as published by the Free\n * Software Foundation; either version 2 of the License, or (at your option)\n * any later version.\n */\n\n#include <stdio.h>\n#include <stdlib.h>\n#include <stdint.h>\n#include <string.h>\n#include <unistd.h>\t\t/* for unlink() */\n#include <libgen.h>\n#include <getopt.h>\t\t/* for getopt() */\n#include <stdarg.h>\n#include <stdbool.h>\n#include <endian.h>\n#include <errno.h>\n#include <sys/stat.h>\n\n\n\n#define ERR(fmt, ...) do { \\\n\tfflush(0); \\\n\tfprintf(stderr, \"[%s] *** error: \" fmt \"\\n\", \\\n\t\t\tprogname, ## __VA_ARGS__); \\\n} while (0)\n\n#define ERRS(fmt, ...) do { \\\n\tint save = errno; \\\n\tfflush(0); \\\n\tfprintf(stderr, \"[%s] *** error: \" fmt \": %s\\n\", \\\n\t\t\tprogname, ## __VA_ARGS__, strerror(save)); \\\n} while (0)\n\n#define VERBOSE(fmt, ...) do { \\\n\tif (verbose) { \\\n\t\tfprintf(stdout, \"[%s] \" fmt \"\\n\", progname, ## __VA_ARGS__); \\\n\t} \\\n} while (0)\n\n#define STAG_SIZE 16\n#define STAG_MAGIC\t0x2B24\n#define STAG_ID\t\t0x02\n\n#define CSXF_SIZE 16\n#define CSXF_MAGIC\t0x5343\n\n#define MAX_DATA_HEADER 128\n#define DATA_HEADER_UNKNOWN 0x8000\n#define DATA_HEADER_EEPROM 0xF5\n#define DATA_HEADER_CONFIG 0x42\n#define DATA_HEADER_SIZE 6\n\n#define DATA_HEADER_ID_MAC 0x30\n#define DATA_HEADER_ID_CAL 0x0\n\n/* ARM update header 2.0\n * used only in factory images to erase and flash selected area\n */\nstruct stag_header {\t\t/* used only of sch2 wrapped kernel data */\n\tuint8_t cmark;\t\t/* in factory 0xFF ,in sysuograde must be the same as id */\n\tuint8_t id;\t\t/* 0x04 */\n\tuint16_t magic;\t\t/* magic 0x2B24 */\n\tuint32_t time_stamp;\t/* timestamp calculated in jboot way */\n\tuint32_t image_length;\t/* lentgh of kernel + sch2 header */\n\tuint16_t image_checksum;\t/* negated jboot_checksum of sch2 + kernel */\n\tuint16_t tag_checksum;\t/* negated jboot_checksum of stag header data */\n};\n\nstruct csxf_header {\n\tuint16_t magic;\t\t/* 0x5343, 'CS' in little endian */\n\tuint16_t checksum;\t/* checksum, include header & body */\n\tuint32_t body_length;\t/* length of body */\n\tuint8_t body_encoding;\t/* encoding method of body */\n\tuint8_t reserved[3];\n\tuint32_t raw_length;\t/* length of body before encoded */\n};\n\nstruct data_header {\n\tuint8_t id;\n\tuint8_t type;\t\t/* 0x42xx for config 0xF5xx for eeprom */\n\tuint16_t unknown;\n\tuint16_t length;\t/* length of body */\n\tuint8_t data[];\t\t/* encoding method of body */\n};\n\n/* globals */\n\nchar *ofname;\nchar *ifname;\nchar *progname;\n\nuint8_t *buffer;\nuint32_t config_size;\n\nuint32_t start_offset;\nuint8_t mac_duplicate;\nuint8_t mac_print;\nuint8_t print_data;\nuint8_t verbose;\n\nstatic void usage(int status)\n{\n\tfprintf(stderr, \"Usage: %s [OPTIONS...]\\n\", progname);\n\tfprintf(stderr,\n\t\t\"\\n\"\n\t\t\"Options:\\n\"\n\t\t\"  -i <file>       config partition file <file>\\n\"\n\t\t\"  -m              print mac address\\n\"\n\t\t\"  -e <file>       save eeprom calibration data image to the file <file>\\n\"\n\t\t\"  -o <offset>     set start offset to <ofset>\\n\"\n\t\t\"  -p              print config data\\n\"\n\t\t\"  -v              verbose\\n\"\n\t\t\"  -h              show this screen\\n\");\n\n\texit(status);\n}\n\nstatic void print_data_header(struct data_header *printed_header)\n{\n\tprintf(\"id: 0x%02X \"\n\t       \"type: 0x%02X \"\n\t       \"unknown: 0x%04X \"\n\t       \"length: 0x%04X\\n\"\n\t       \"data: \",\n\t       printed_header->id,\n\t       printed_header->type,\n\t       printed_header->unknown, printed_header->length);\n\n\tfor (uint16_t i = 0; i < printed_header->length; i++)\n\t\tprintf(\"%02X \", printed_header->data[i]);\n\n\tprintf(\"\\n\");\n\n}\n\nstatic uint16_t jboot_checksum(uint16_t start_val, uint16_t *data, int size)\n{\n\tuint32_t counter = start_val;\n\tuint16_t *ptr = data;\n\n\twhile (size > 1) {\n\t\tcounter += *ptr;\n\t\t++ptr;\n\t\twhile (counter >> 16)\n\t\t\tcounter = (uint16_t) counter + (counter >> 16);\n\t\tsize -= 2;\n\t}\n\tif (size > 0) {\n\t\tcounter += *(uint8_t *) ptr;\n\t\tcounter -= 0xFF;\n\t}\n\twhile (counter >> 16)\n\t\tcounter = (uint16_t) counter + (counter >> 16);\n\treturn counter;\n}\n\nstatic int find_header(uint8_t *buf, uint32_t buf_size,\n\t\t       struct data_header **data_table)\n{\n\tuint8_t *tmp_buf = buf + start_offset;\n\tuint8_t tmp_hdr[4] = { STAG_ID, STAG_ID, (STAG_MAGIC & 0xFF), (STAG_MAGIC >> 8) };\n\tstruct csxf_header *tmp_csxf_header;\n\tuint16_t tmp_checksum = 0;\n\tuint16_t data_header_counter = 0;\n\tint ret = EXIT_FAILURE;\n\n\tVERBOSE(\"Looking for STAG header!\");\n\n\twhile ((uint32_t) tmp_buf - (uint32_t) buf <= buf_size) {\n\t\tif (!memcmp(tmp_buf, tmp_hdr, 4)) {\n\t\t\tif (((struct stag_header *)tmp_buf)->tag_checksum ==\n\t\t\t    (uint16_t) ~jboot_checksum(0, (uint16_t *) tmp_buf,\n\t\t\t\t\t\t\tSTAG_SIZE - 2)) {\n\t\t\t\tVERBOSE(\"Found proper STAG header at: 0x%X.\",\n\t\t\t\t\ttmp_buf - buf);\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t\ttmp_buf++;\n\t}\n\n\ttmp_csxf_header = (struct csxf_header *)(tmp_buf + STAG_SIZE);\n\tif (tmp_csxf_header->magic != CSXF_MAGIC) {\n\t\tERR(\"CSXF magic incorrect! 0x%X != 0x%X\",\n\t\t    tmp_csxf_header->magic, CSXF_MAGIC);\n\t\tgoto out;\n\t}\n\tVERBOSE(\"CSXF magic ok.\");\n\ttmp_checksum = tmp_csxf_header->checksum;\n\ttmp_csxf_header->checksum = 0;\n\n\ttmp_csxf_header->checksum =\n\t    (uint16_t) ~jboot_checksum(0, (uint16_t *) (tmp_buf + STAG_SIZE),\n\t\t\t\t\ttmp_csxf_header->raw_length +\n\t\t\t\t\tCSXF_SIZE);\n\n\tif (tmp_checksum != tmp_csxf_header->checksum) {\n\t\tERR(\"CSXF checksum incorrect! Stored: 0x%X Calculated: 0x%X\",\n\t\t    tmp_checksum, tmp_csxf_header->checksum);\n\t\tgoto out;\n\t}\n\tVERBOSE(\"CSXF image checksum ok.\");\n\n\ttmp_buf = tmp_buf + STAG_SIZE + CSXF_SIZE;\n\n\twhile ((uint32_t) tmp_buf - (uint32_t) buf <= buf_size) {\n\n\t\tstruct data_header *tmp_data_header =\n\t\t    (struct data_header *)tmp_buf;\n\n\t\tif (tmp_data_header->unknown != DATA_HEADER_UNKNOWN) {\n\t\t\ttmp_buf++;\n\t\t\tcontinue;\n\t\t}\n\t\tif (tmp_data_header->type != DATA_HEADER_EEPROM\n\t\t    && tmp_data_header->type != DATA_HEADER_CONFIG) {\n\t\t\ttmp_buf++;\n\t\t\tcontinue;\n\t\t}\n\n\t\tdata_table[data_header_counter] = tmp_data_header;\n\t\ttmp_buf +=\n\t\t    DATA_HEADER_SIZE + data_table[data_header_counter]->length;\n\t\tdata_header_counter++;\n\n\t}\n\n\tret = data_header_counter;\n\n out:\n\treturn ret;\n}\n\nstatic int read_file(char *file_name)\n{\n\tint ret = EXIT_FAILURE;\n\tuint32_t file_size = 0;\n\tFILE *fp;\n\n\tfp = fopen(file_name, \"r\");\n\n\tif (!fp) {\n\t\tERR(\"Failed to open config input file %s\", file_name);\n\t\tgoto out;\n\t}\n\n\tfseek(fp, 0L, SEEK_END);\n\tfile_size = ftell(fp);\n\tfseek(fp, 0L, SEEK_SET);\n\n\tbuffer = malloc(file_size);\n\tVERBOSE(\"Allocated %d bytes.\", file_size);\n\n\tif (fread(buffer, 1, file_size, fp) != file_size) {\n\t\tERR(\"Failed to read config input file %s\", file_name);\n\t\tgoto out_free_buf;\n\t}\n\n\tVERBOSE(\"Read %d bytes of config input file %s\", file_size, file_name);\n\tconfig_size = file_size;\n\tret = EXIT_SUCCESS;\n\tgoto out;\n\n out_free_buf:\n\tfree(buffer);\n\tfclose(fp);\n out:\n\treturn ret;\n}\n\nstatic int write_file(const char *ofname, const uint8_t *data, int len)\n{\n\tFILE *f;\n\tint ret = EXIT_FAILURE;\n\n\tf = fopen(ofname, \"w\");\n\tif (f == NULL) {\n\t\tERRS(\"could not open \\\"%s\\\" for writing\", ofname);\n\t\tgoto out;\n\t}\n\n\terrno = 0;\n\tfwrite(data, len, 1, f);\n\tif (errno) {\n\t\tERRS(\"unable to write output file\");\n\t\tgoto out_flush;\n\t}\n\n\tVERBOSE(\"firmware file \\\"%s\\\" completed\", ofname);\n\n\tret = EXIT_SUCCESS;\n\n out_flush:\n\tfflush(f);\n\tfclose(f);\n\tif (ret != EXIT_SUCCESS)\n\t\tunlink(ofname);\n out:\n\treturn ret;\n}\n\nstatic void print_mac(struct data_header **data_table, int cnt)\n{\n\n\tfor (int i = 0; i < cnt; i++) {\n\t\tif (data_table[i]->type == DATA_HEADER_CONFIG\n\t\t    && data_table[i]->id == DATA_HEADER_ID_MAC) {\n\t\t\tint j;\n\t\t\tfor (j = 0; j < 5; j++)\n\t\t\t\tprintf(\"%02x:\", data_table[i]->data[j]);\n\t\t\tprintf(\"%02x\\n\", data_table[i]->data[j]);\n\t\t}\n\n\t}\n\n}\n\nstatic int write_eeprom(struct data_header **data_table, int cnt)\n{\n\tint ret = EXIT_FAILURE;\n\n\tfor (int i = 0; i < cnt; i++) {\n\t\tif (data_table[i]->type == DATA_HEADER_EEPROM\n\t\t    && data_table[i]->id == DATA_HEADER_ID_CAL) {\n\t\t\tret =\n\t\t\t    write_file(ofname, data_table[i]->data,\n\t\t\t\t       data_table[i]->length);\n\t\t\tbreak;\n\t\t}\n\n\t}\n\n\treturn ret;\n}\n\nint main(int argc, char *argv[])\n{\n\tint ret = EXIT_FAILURE;\n\tint configs_counter = 0;\n\tstruct data_header *configs_table[MAX_DATA_HEADER];\n\tbuffer = NULL;\n\tconfig_size = 0;\n\n\tprogname = basename(argv[0]);\n\tstart_offset = 0;\n\tmac_print = 0;\n\tprint_data = 0;\n\tverbose = 0;\n\tofname = NULL;\n\tifname = NULL;\n\n\twhile (1) {\n\t\tint c;\n\n\t\tc = getopt(argc, argv, \"de:hi:mo:pv\");\n\t\tif (c == -1)\n\t\t\tbreak;\n\n\t\tswitch (c) {\n\t\tcase 'm':\n\t\t\tmac_print = 1;\n\t\t\tbreak;\n\t\tcase 'i':\n\t\t\tifname = optarg;\n\t\t\tbreak;\n\t\tcase 'e':\n\t\t\tofname = optarg;\n\t\t\tbreak;\n\t\tcase 'o':\n\t\t\tsscanf(optarg, \"0x%x\", &start_offset);\n\t\t\tbreak;\n\t\tcase 'p':\n\t\t\tprint_data = 1;\n\t\t\tbreak;\n\t\tcase 'v':\n\t\t\tverbose = 1;\n\t\t\tVERBOSE(\"Enable verbose!\");\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tusage(EXIT_FAILURE);\n\t\t\tbreak;\n\t\t}\n\t}\n\n\tif (!ifname)\n\t\tusage(EXIT_FAILURE);\n\n\tret = read_file(ifname);\n\n\tif (ret || config_size <= 0)\n\t\tgoto out;\n\n\tconfigs_counter = find_header(buffer, config_size, configs_table);\n\n\tif (configs_counter <= 0)\n\t\tgoto out_free_buf;\n\n\tif (print_data || verbose) {\n\t\tfor (int i = 0; i < configs_counter; i++)\n\t\t\tprint_data_header(configs_table[i]);\n\t}\n\n\tif (mac_print)\n\t\tprint_mac(configs_table, configs_counter);\n\n\tret = EXIT_SUCCESS;\n\n\tif (ofname)\n\t\tret = write_eeprom(configs_table, configs_counter);\n\n out_free_buf:\n\tfree(buffer);\n out:\n\treturn ret;\n\n}\n"
  },
  {
    "path": "package/utils/jsonfilter/Makefile",
    "content": "include $(TOPDIR)/rules.mk\n\nPKG_NAME:=jsonfilter\nPKG_RELEASE:=1\n\nPKG_SOURCE_PROTO:=git\nPKG_SOURCE_URL=$(PROJECT_GIT)/project/jsonpath.git\nPKG_SOURCE_DATE:=2018-02-04\nPKG_SOURCE_VERSION:=c7e938d6582a436dddc938539e72dd1320625c54\nPKG_MIRROR_HASH:=0601b4d7aa5ee096e99388a57cb0701673ab58fccd6ed2984a2abbd4f846e045\nCMAKE_INSTALL:=1\n\nPKG_MAINTAINER:=Jo-Philipp Wich <jo@mein.io>\nPKG_LICENSE:=ISC\n\ninclude $(INCLUDE_DIR)/package.mk\ninclude $(INCLUDE_DIR)/cmake.mk\n\ndefine Package/jsonfilter\n  SECTION:=base\n  CATEGORY:=Base system\n  DEPENDS:=+libubox +libjson-c\n  TITLE:=OpenWrt JSON filter utility\n  URL:=$(PKG_SOURCE_URL)\nendef\n\ndefine Package/jsonfilter/install\n\t$(INSTALL_DIR) $(1)/usr/bin\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/bin/jsonpath $(1)/usr/bin/jsonfilter\nendef\n\n$(eval $(call BuildPackage,jsonfilter))\n"
  },
  {
    "path": "package/utils/lua/Makefile",
    "content": "#\n# Copyright (C) 2006-2014 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=lua\nPKG_VERSION:=5.1.5\nPKG_RELEASE:=10\n\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz\nPKG_SOURCE_URL:=http://www.lua.org/ftp/ \\\n\thttp://www.tecgraf.puc-rio.br/lua/ftp/\nPKG_HASH:=2640fc56a795f29d28ef15e13c34a47e223960b0240e8cb0a82d9b0738695333\nPKG_BUILD_PARALLEL:=1\n\nPKG_LICENSE:=MIT\nPKG_LICENSE_FILES:=COPYRIGHT\n\nHOST_PATCH_DIR := ./patches-host\n\ninclude $(INCLUDE_DIR)/package.mk\ninclude $(INCLUDE_DIR)/host-build.mk\n\ndefine Package/lua/Default\n  SUBMENU:=Lua\n  SECTION:=lang\n  CATEGORY:=Languages\n  TITLE:=Lua programming language\n  URL:=http://www.lua.org/\n  MAINTAINER:=Jo-Philipp Wich <jo@mein.io>\nendef\n\ndefine Package/lua/Default/description\n Lua is a powerful light-weight programming language designed for extending \n applications. Lua is also frequently used as a general-purpose, stand-alone \n language. Lua is free software.\nendef\n\ndefine Package/liblua\n$(call Package/lua/Default)\n  SUBMENU:=\n  SECTION:=libs\n  CATEGORY:=Libraries\n  TITLE+= (libraries)\n  ABI_VERSION:=5.1.5\nendef\n\ndefine Package/liblua/description\n$(call Package/lua/Default/description)\n This package contains the Lua shared libraries, needed by other programs.\nendef\n\ndefine Package/lua\n$(call Package/lua/Default)\n  DEPENDS:=+liblua\n  TITLE+= (interpreter)\nendef\n\ndefine Package/lua/description\n$(call Package/lua/Default/description)\n This package contains the Lua language interpreter.\nendef\n\ndefine Package/luac\n$(call Package/lua/Default)\n  DEPENDS:=+liblua\n  TITLE+= (compiler)\nendef\n\ndefine Package/luac/description\n$(call Package/lua/Default/description)\n This package contains the Lua language compiler.\nendef\n\ndefine Package/lua-examples\n$(call Package/lua/Default)\n  DEPENDS:=lua\n  TITLE+= (examples)\nendef\n\ndefine Package/lua-examples/description\n$(call Package/lua/Default/description)\n This package contains Lua language examples.\nendef\n\ndefine Build/Configure\nendef\n\nTARGET_CFLAGS += -DLUA_USE_LINUX $(FPIC) -std=gnu99\n\ndefine Build/Compile\n\t$(MAKE) $(PKG_JOBS) -C $(PKG_BUILD_DIR) \\\n\t\tCC=\"$(TARGET_CROSS)gcc\" \\\n\t\tAR=\"$(TARGET_CROSS)ar rcu\" \\\n\t\tRANLIB=\"$(TARGET_CROSS)ranlib\" \\\n\t\tINSTALL_ROOT=/usr \\\n\t\tCFLAGS=\"$(TARGET_CPPFLAGS) $(TARGET_CFLAGS)\" \\\n\t\tMYLDFLAGS=\"$(TARGET_LDFLAGS) $(if $(CONFIG_USE_GLIBC),-lm -ldl)\" \\\n\t\tPKG_VERSION=$(PKG_VERSION) \\\n\t\tlinux\n\trm -rf $(PKG_INSTALL_DIR)\n\tmkdir -p $(PKG_INSTALL_DIR)\n\t$(MAKE) -C $(PKG_BUILD_DIR) \\\n\t\tINSTALL_TOP=\"$(PKG_INSTALL_DIR)/usr\" \\\n\t\tinstall\nendef\n\ndefine Host/Configure\n\t$(SED) 's,\"/usr/local/\",\"$(STAGING_DIR_HOSTPKG)/\",' $(HOST_BUILD_DIR)/src/luaconf.h\nendef\n\nifeq ($(HOST_OS),Darwin)\n\tLUA_OS:=macosx\nelse\n\tifeq ($(HOST_OS),FreeBSD)\n\t\tLUA_OS:=freebsd\n\telse\n\t\tLUA_OS:=linux\n\tendif\nendif\n\ndefine Host/Compile\n\t$(MAKE) -C $(HOST_BUILD_DIR) \\\n\t\tCC=\"$(HOSTCC) $(HOST_FPIC) -std=gnu99\" \\\n\t\t$(LUA_OS)\nendef\n\ndefine Host/Install\n\t$(MAKE) -C $(HOST_BUILD_DIR) \\\n\t\tINSTALL_TOP=\"$(STAGING_DIR_HOSTPKG)\" \\\n\t\tinstall\n\n\t$(INSTALL_DIR) $(STAGING_DIR_HOSTPKG)/lib/pkgconfig\n\t$(CP) $(HOST_BUILD_DIR)/etc/lua.pc $(STAGING_DIR_HOSTPKG)/lib/pkgconfig/lua5.1.pc\n\n\t$(LN) lua5.1 $(STAGING_DIR_HOSTPKG)/bin/lua\n\t$(LN) luac5.1 $(STAGING_DIR_HOSTPKG)/bin/luac\n\t$(LN) lua5.1.pc $(STAGING_DIR_HOSTPKG)/lib/pkgconfig/lua.pc\nendef\n\ndefine Build/InstallDev\n\t$(INSTALL_DIR) $(1)/usr/include\n\t$(CP) $(PKG_INSTALL_DIR)/usr/include/lua{,lib,conf}.h $(1)/usr/include/\n\t$(CP) $(PKG_INSTALL_DIR)/usr/include/lua.hpp $(1)/usr/include/\n\t$(CP) $(PKG_INSTALL_DIR)/usr/include/lauxlib.h $(1)/usr/include/\n\t$(CP) $(PKG_INSTALL_DIR)/usr/include/lnum_config.h $(1)/usr/include/\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/liblua.{a,so*} $(1)/usr/lib/\n\t$(LN) liblua.so.$(PKG_VERSION) $(1)/usr/lib/liblualib.so\n\t$(INSTALL_DIR) $(1)/usr/lib/pkgconfig\n\t$(CP) $(PKG_BUILD_DIR)/etc/lua.pc $(1)/usr/lib/pkgconfig/\nendef\n\ndefine Package/liblua/install\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/liblua.so.* $(1)/usr/lib/\nendef\n\ndefine Package/lua/install\n\t$(INSTALL_DIR) $(1)/usr/bin\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/bin/lua5.1 $(1)/usr/bin/\n\t$(LN) lua5.1 $(1)/usr/bin/lua\nendef\n\ndefine Package/luac/install\n\t$(INSTALL_DIR) $(1)/usr/bin\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/bin/luac5.1 $(1)/usr/bin/\n\t$(LN) luac5.1 $(1)/usr/bin/luac\nendef\n\ndefine Package/lua-examples/install\n\t$(INSTALL_DIR) $(1)/usr/share/lua/examples\n\t$(INSTALL_DATA) $(PKG_BUILD_DIR)/test/*.lua \\\n\t\t$(1)/usr/share/lua/examples/\nendef\n\n$(eval $(call BuildPackage,liblua))\n$(eval $(call BuildPackage,lua))\n$(eval $(call BuildPackage,luac))\n$(eval $(call BuildPackage,lua-examples))\n$(eval $(call HostBuild))\n\n"
  },
  {
    "path": "package/utils/lua/patches/001-include-version-number.patch",
    "content": "From 96576b44a1b368bd6590eb0778ae45cc9ccede3f Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Fri, 21 Jun 2019 14:08:38 +0200\nSubject: [PATCH] include version number\n\nIncluding it allows multiple lua versions to coexist.\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\n---\n\ndiff --git a/Makefile b/Makefile\n--- a/Makefile\n+++ b/Makefile\n@@ -41,10 +41,10 @@ RANLIB= ranlib\n PLATS= aix ansi bsd freebsd generic linux macosx mingw posix solaris\n \n # What to install.\n-TO_BIN= lua luac\n+TO_BIN= lua$V luac$V\n TO_INC= lua.h luaconf.h lualib.h lauxlib.h ../etc/lua.hpp\n TO_LIB= liblua.a\n-TO_MAN= lua.1 luac.1\n+TO_MAN= lua$V.1 luac$V.1\n \n # Lua version and release.\n V= 5.1\n@@ -53,7 +53,7 @@ R= 5.1.5\n all:\t$(PLAT)\n \n $(PLATS) clean:\n-\tcd src && $(MAKE) $@\n+\tcd src && $(MAKE) $@ V=$V\n \n test:\tdummy\n \tsrc/lua test/hello.lua\ndiff --git a/doc/lua.1 b/doc/lua5.1.1\nrename from doc/lua.1\nrename to doc/lua5.1.1\ndiff --git a/doc/luac.1 b/doc/luac5.1.1\nrename from doc/luac.1\nrename to doc/luac5.1.1\ndiff --git a/src/Makefile b/src/Makefile\n--- a/src/Makefile\n+++ b/src/Makefile\n@@ -29,10 +29,10 @@ CORE_O=\tlapi.o lcode.o ldebug.o ldo.o ldump.o lfunc.o lgc.o llex.o lmem.o \\\n LIB_O=\tlauxlib.o lbaselib.o ldblib.o liolib.o lmathlib.o loslib.o ltablib.o \\\n \tlstrlib.o loadlib.o linit.o\n \n-LUA_T=\tlua\n+LUA_T=\tlua$V\n LUA_O=\tlua.o\n \n-LUAC_T=\tluac\n+LUAC_T=\tluac$V\n LUAC_O=\tluac.o print.o\n \n ALL_O= $(CORE_O) $(LIB_O) $(LUA_O) $(LUAC_O)\n"
  },
  {
    "path": "package/utils/lua/patches/010-lua-5.1.3-lnum-full-260308.patch",
    "content": "--- a/src/Makefile\n+++ b/src/Makefile\n@@ -25,7 +25,7 @@ PLATS= aix ansi bsd freebsd generic linu\n LUA_A=\tliblua.a\n CORE_O=\tlapi.o lcode.o ldebug.o ldo.o ldump.o lfunc.o lgc.o llex.o lmem.o \\\n \tlobject.o lopcodes.o lparser.o lstate.o lstring.o ltable.o ltm.o  \\\n-\tlundump.o lvm.o lzio.o\n+\tlundump.o lvm.o lzio.o lnum.o\n LIB_O=\tlauxlib.o lbaselib.o ldblib.o liolib.o lmathlib.o loslib.o ltablib.o \\\n \tlstrlib.o loadlib.o linit.o\n \n@@ -148,6 +148,7 @@ llex.o: llex.c lua.h luaconf.h ldo.h lob\n lmathlib.o: lmathlib.c lua.h luaconf.h lauxlib.h lualib.h\n lmem.o: lmem.c lua.h luaconf.h ldebug.h lstate.h lobject.h llimits.h \\\n   ltm.h lzio.h lmem.h ldo.h\n+lnum.o: lnum.c lua.h llex.h lnum.h\n loadlib.o: loadlib.c lua.h luaconf.h lauxlib.h lualib.h\n lobject.o: lobject.c lua.h luaconf.h ldo.h lobject.h llimits.h lstate.h \\\n   ltm.h lzio.h lmem.h lstring.h lgc.h lvm.h\n@@ -179,4 +180,18 @@ lzio.o: lzio.c lua.h luaconf.h llimits.h\n print.o: print.c ldebug.h lstate.h lua.h luaconf.h lobject.h llimits.h \\\n   ltm.h lzio.h lmem.h lopcodes.h lundump.h\n \n+luaconf.h: lnum_config.h\n+lapi.c: lnum.h\n+lauxlib.c: llimits.h\n+lbaselib.c: llimits.h lobject.h lapi.h\n+lcode.c: lnum.h\n+liolib.c: lnum.h llex.h\n+llex.c: lnum.h\n+lnum.h: lobject.h\n+lobject.c: llex.h lnum.h\n+ltable.c: lnum.h\n+lua.c: llimits.h\n+lvm.c: llex.h lnum.h\n+print.c: lnum.h\n+\n # (end of Makefile)\n--- a/src/lapi.c\n+++ b/src/lapi.c\n@@ -28,7 +28,7 @@\n #include \"ltm.h\"\n #include \"lundump.h\"\n #include \"lvm.h\"\n-\n+#include \"lnum.h\"\n \n \n const char lua_ident[] =\n@@ -241,12 +241,13 @@ LUA_API void lua_pushvalue (lua_State *L\n \n LUA_API int lua_type (lua_State *L, int idx) {\n   StkId o = index2adr(L, idx);\n-  return (o == luaO_nilobject) ? LUA_TNONE : ttype(o);\n+  return (o == luaO_nilobject) ? LUA_TNONE : ttype_ext(o);\n }\n \n \n LUA_API const char *lua_typename (lua_State *L, int t) {\n   UNUSED(L);\n+  lua_assert( t!= LUA_TINT );\n   return (t == LUA_TNONE) ? \"no value\" : luaT_typenames[t];\n }\n \n@@ -264,6 +265,14 @@ LUA_API int lua_isnumber (lua_State *L,\n }\n \n \n+LUA_API int lua_isinteger (lua_State *L, int idx) {\n+  TValue tmp;\n+  lua_Integer dum;\n+  const TValue *o = index2adr(L, idx);\n+  return tonumber(o,&tmp) && (ttisint(o) || tt_integer_valued(o,&dum));\n+}\n+\n+\n LUA_API int lua_isstring (lua_State *L, int idx) {\n   int t = lua_type(L, idx);\n   return (t == LUA_TSTRING || t == LUA_TNUMBER);\n@@ -309,31 +318,66 @@ LUA_API int lua_lessthan (lua_State *L,\n }\n \n \n-\n LUA_API lua_Number lua_tonumber (lua_State *L, int idx) {\n   TValue n;\n   const TValue *o = index2adr(L, idx);\n-  if (tonumber(o, &n))\n+  if (tonumber(o, &n)) {\n+#ifdef LNUM_COMPLEX\n+    if (nvalue_img(o) != 0)\n+      luaG_runerror(L, \"expecting a real number\");\n+#endif\n     return nvalue(o);\n-  else\n-    return 0;\n+  }\n+  return 0;\n }\n \n \n LUA_API lua_Integer lua_tointeger (lua_State *L, int idx) {\n   TValue n;\n+    /* Lua 5.1 documented behaviour is to return nonzero for non-integer:\n+     * \"If the number is not an integer, it is truncated in some non-specified way.\" \n+     * I would suggest to change this, to return 0 for anything that would\n+     * not fit in 'lua_Integer'.\n+     */\n+#ifdef LUA_COMPAT_TOINTEGER\n+  /* Lua 5.1 compatible */\n   const TValue *o = index2adr(L, idx);\n   if (tonumber(o, &n)) {\n-    lua_Integer res;\n-    lua_Number num = nvalue(o);\n-    lua_number2integer(res, num);\n-    return res;\n+    lua_Integer i;\n+    lua_Number d;\n+    if (ttisint(o)) return ivalue(o);\n+    d= nvalue_fast(o);\n+# ifdef LNUM_COMPLEX\n+    if (nvalue_img_fast(o) != 0)\n+      luaG_runerror(L, \"expecting a real number\");\n+# endif\n+    lua_number2integer(i, d);\n+    return i;\n   }\n-  else\n-    return 0;\n+#else\n+  /* New suggestion */\n+  const TValue *o = index2adr(L, idx);\n+  if (tonumber(o, &n)) {\n+    lua_Integer i;\n+    if (ttisint(o)) return ivalue(o);\n+    if (tt_integer_valued(o,&i)) return i;\n+  }\n+#endif\n+  return 0;\n }\n \n \n+#ifdef LNUM_COMPLEX\n+LUA_API lua_Complex lua_tocomplex (lua_State *L, int idx) {\n+  TValue tmp;\n+  const TValue *o = index2adr(L, idx);\n+  if (tonumber(o, &tmp))\n+    return nvalue_complex(o);\n+  return 0;\n+}\n+#endif\n+\n+\n LUA_API int lua_toboolean (lua_State *L, int idx) {\n   const TValue *o = index2adr(L, idx);\n   return !l_isfalse(o);\n@@ -364,6 +408,7 @@ LUA_API size_t lua_objlen (lua_State *L,\n     case LUA_TSTRING: return tsvalue(o)->len;\n     case LUA_TUSERDATA: return uvalue(o)->len;\n     case LUA_TTABLE: return luaH_getn(hvalue(o));\n+    case LUA_TINT:\n     case LUA_TNUMBER: {\n       size_t l;\n       lua_lock(L);  /* `luaV_tostring' may create a new string */\n@@ -426,6 +471,8 @@ LUA_API void lua_pushnil (lua_State *L)\n }\n \n \n+/* 'lua_pushnumber()' may lose accuracy on integers, 'lua_pushinteger' will not.\n+ */\n LUA_API void lua_pushnumber (lua_State *L, lua_Number n) {\n   lua_lock(L);\n   setnvalue(L->top, n);\n@@ -434,12 +481,22 @@ LUA_API void lua_pushnumber (lua_State *\n }\n \n \n-LUA_API void lua_pushinteger (lua_State *L, lua_Integer n) {\n+LUA_API void lua_pushinteger (lua_State *L, lua_Integer i) {\n+  lua_lock(L);\n+  setivalue(L->top, i);\n+  api_incr_top(L);\n+  lua_unlock(L);\n+}\n+\n+\n+#ifdef LNUM_COMPLEX\n+LUA_API void lua_pushcomplex (lua_State *L, lua_Complex v) {\n   lua_lock(L);\n-  setnvalue(L->top, cast_num(n));\n+  setnvalue_complex( L->top, v );\n   api_incr_top(L);\n   lua_unlock(L);\n }\n+#endif\n \n \n LUA_API void lua_pushlstring (lua_State *L, const char *s, size_t len) {\n@@ -569,7 +626,7 @@ LUA_API void lua_rawgeti (lua_State *L,\n   lua_lock(L);\n   o = index2adr(L, idx);\n   api_check(L, ttistable(o));\n-  setobj2s(L, L->top, luaH_getnum(hvalue(o), n));\n+  setobj2s(L, L->top, luaH_getint(hvalue(o), n));\n   api_incr_top(L);\n   lua_unlock(L);\n }\n@@ -597,6 +654,9 @@ LUA_API int lua_getmetatable (lua_State\n     case LUA_TUSERDATA:\n       mt = uvalue(obj)->metatable;\n       break;\n+    case LUA_TINT:\n+      mt = G(L)->mt[LUA_TNUMBER];\n+      break;\n     default:\n       mt = G(L)->mt[ttype(obj)];\n       break;\n@@ -687,7 +747,7 @@ LUA_API void lua_rawseti (lua_State *L,\n   api_checknelems(L, 1);\n   o = index2adr(L, idx);\n   api_check(L, ttistable(o));\n-  setobj2t(L, luaH_setnum(L, hvalue(o), n), L->top-1);\n+  setobj2t(L, luaH_setint(L, hvalue(o), n), L->top-1);\n   luaC_barriert(L, hvalue(o), L->top-1);\n   L->top--;\n   lua_unlock(L);\n@@ -721,7 +781,7 @@ LUA_API int lua_setmetatable (lua_State\n       break;\n     }\n     default: {\n-      G(L)->mt[ttype(obj)] = mt;\n+      G(L)->mt[ttype_ext(obj)] = mt;\n       break;\n     }\n   }\n@@ -1085,3 +1145,32 @@ LUA_API const char *lua_setupvalue (lua_\n   return name;\n }\n \n+\n+/* Help function for 'luaB_tonumber()', avoids multiple str->number\n+ * conversions for Lua \"tonumber()\".\n+ *\n+ * Also pushes floating point numbers with integer value as integer, which\n+ * can be used by 'tonumber()' in scripts to bring values back to integer\n+ * realm.\n+ *\n+ * Note: The 'back to integer realm' is _not_ to affect string conversions:\n+ * 'tonumber(\"4294967295.1\")' should give a floating point value, although\n+ * the value would be 4294967296 (and storable in int64 realm).\n+ */\n+int lua_pushvalue_as_number (lua_State *L, int idx)\n+{\n+  const TValue *o = index2adr(L, idx);\n+  TValue tmp;\n+  lua_Integer i;\n+  if (ttisnumber(o)) {\n+    if ( (!ttisint(o)) && tt_integer_valued(o,&i)) {\n+      lua_pushinteger( L, i );\n+      return 1;\n+    }\n+  } else if (!tonumber(o, &tmp)) {\n+    return 0;\n+  }\n+  if (ttisint(o)) lua_pushinteger( L, ivalue(o) );\n+  else lua_pushnumber( L, nvalue_fast(o) );\n+  return 1;\n+}\n--- a/src/lapi.h\n+++ b/src/lapi.h\n@@ -13,4 +13,6 @@\n \n LUAI_FUNC void luaA_pushobject (lua_State *L, const TValue *o);\n \n+int lua_pushvalue_as_number (lua_State *L, int idx);\n+\n #endif\n--- a/src/lauxlib.c\n+++ b/src/lauxlib.c\n@@ -23,7 +23,7 @@\n #include \"lua.h\"\n \n #include \"lauxlib.h\"\n-\n+#include \"llimits.h\"\n \n #define FREELIST_REF\t0\t/* free list of references */\n \n@@ -66,7 +66,7 @@ LUALIB_API int luaL_typerror (lua_State\n \n \n static void tag_error (lua_State *L, int narg, int tag) {\n-  luaL_typerror(L, narg, lua_typename(L, tag));\n+  luaL_typerror(L, narg, tag==LUA_TINT ? \"integer\" : lua_typename(L, tag));\n }\n \n \n@@ -188,8 +188,8 @@ LUALIB_API lua_Number luaL_optnumber (lu\n \n LUALIB_API lua_Integer luaL_checkinteger (lua_State *L, int narg) {\n   lua_Integer d = lua_tointeger(L, narg);\n-  if (d == 0 && !lua_isnumber(L, narg))  /* avoid extra test when d is not 0 */\n-    tag_error(L, narg, LUA_TNUMBER);\n+  if (d == 0 && !lua_isinteger(L, narg))  /* avoid extra test when d is not 0 */\n+    tag_error(L, narg, LUA_TINT);\n   return d;\n }\n \n@@ -200,6 +200,16 @@ LUALIB_API lua_Integer luaL_optinteger (\n }\n \n \n+#ifdef LNUM_COMPLEX\n+LUALIB_API lua_Complex luaL_checkcomplex (lua_State *L, int narg) {\n+  lua_Complex c = lua_tocomplex(L, narg);\n+  if (c == 0 && !lua_isnumber(L, narg))  /* avoid extra test when c is not 0 */\n+    tag_error(L, narg, LUA_TNUMBER);\n+  return c;\n+}\n+#endif\n+\n+\n LUALIB_API int luaL_getmetafield (lua_State *L, int obj, const char *event) {\n   if (!lua_getmetatable(L, obj))  /* no metatable? */\n     return 0;\n--- a/src/lauxlib.h\n+++ b/src/lauxlib.h\n@@ -57,6 +57,12 @@ LUALIB_API lua_Number (luaL_optnumber) (\n LUALIB_API lua_Integer (luaL_checkinteger) (lua_State *L, int numArg);\n LUALIB_API lua_Integer (luaL_optinteger) (lua_State *L, int nArg,\n                                           lua_Integer def);\n+#define luaL_checkint32(L,narg) ((int)luaL_checkinteger(L,narg))\n+#define luaL_optint32(L,narg,def) ((int)luaL_optinteger(L,narg,def))\n+\n+#ifdef LNUM_COMPLEX\n+  LUALIB_API lua_Complex (luaL_checkcomplex) (lua_State *L, int narg);\n+#endif\n \n LUALIB_API void (luaL_checkstack) (lua_State *L, int sz, const char *msg);\n LUALIB_API void (luaL_checktype) (lua_State *L, int narg, int t);\n--- a/src/lbaselib.c\n+++ b/src/lbaselib.c\n@@ -18,7 +18,9 @@\n \n #include \"lauxlib.h\"\n #include \"lualib.h\"\n-\n+#include \"llimits.h\"\n+#include \"lobject.h\"\n+#include \"lapi.h\"\n \n \n \n@@ -54,20 +56,25 @@ static int luaB_tonumber (lua_State *L)\n   int base = luaL_optint(L, 2, 10);\n   if (base == 10) {  /* standard conversion */\n     luaL_checkany(L, 1);\n-    if (lua_isnumber(L, 1)) {\n-      lua_pushnumber(L, lua_tonumber(L, 1));\n+    if (lua_isnumber(L, 1)) {       /* numeric string, or a number */\n+      lua_pushvalue_as_number(L,1);     /* API extension (not to lose accuracy here) */\n       return 1;\n-    }\n+\t}\n   }\n   else {\n     const char *s1 = luaL_checkstring(L, 1);\n     char *s2;\n-    unsigned long n;\n+    unsigned LUA_INTEGER n;\n     luaL_argcheck(L, 2 <= base && base <= 36, 2, \"base out of range\");\n-    n = strtoul(s1, &s2, base);\n+    n = lua_str2ul(s1, &s2, base);\n     if (s1 != s2) {  /* at least one valid digit? */\n       while (isspace((unsigned char)(*s2))) s2++;  /* skip trailing spaces */\n       if (*s2 == '\\0') {  /* no invalid trailing characters? */\n+\t  \n+\t\t/* Push as number, there needs to be separate 'luaB_tointeger' for\n+\t\t * when the caller wants to preserve the bits (matters if unsigned\n+\t\t * values are used).\n+\t\t */\n         lua_pushnumber(L, (lua_Number)n);\n         return 1;\n       }\n@@ -144,7 +151,7 @@ static int luaB_setfenv (lua_State *L) {\n   luaL_checktype(L, 2, LUA_TTABLE);\n   getfunc(L, 0);\n   lua_pushvalue(L, 2);\n-  if (lua_isnumber(L, 1) && lua_tonumber(L, 1) == 0) {\n+  if (lua_isnumber(L, 1) && lua_tointeger(L, 1) == 0) {\n     /* change environment of current thread */\n     lua_pushthread(L);\n     lua_insert(L, -2);\n@@ -209,7 +216,7 @@ static int luaB_collectgarbage (lua_Stat\n       return 1;\n     }\n     default: {\n-      lua_pushnumber(L, res);\n+      lua_pushinteger(L, res);\n       return 1;\n     }\n   }\n@@ -631,6 +638,8 @@ static void base_open (lua_State *L) {\n   luaL_register(L, \"_G\", base_funcs);\n   lua_pushliteral(L, LUA_VERSION);\n   lua_setglobal(L, \"_VERSION\");  /* set global _VERSION */\n+  lua_pushliteral(L, LUA_LNUM);\n+  lua_setglobal(L, \"_LNUM\");  /* \"[complex] double|float|ldouble int32|int64\" */\n   /* `ipairs' and `pairs' need auxiliary functions as upvalues */\n   auxopen(L, \"ipairs\", luaB_ipairs, ipairsaux);\n   auxopen(L, \"pairs\", luaB_pairs, luaB_next);\n--- a/src/lcode.c\n+++ b/src/lcode.c\n@@ -22,13 +22,18 @@\n #include \"lopcodes.h\"\n #include \"lparser.h\"\n #include \"ltable.h\"\n+#include \"lnum.h\"\n \n \n #define hasjumps(e)\t((e)->t != (e)->f)\n \n-\n static int isnumeral(expdesc *e) {\n-  return (e->k == VKNUM && e->t == NO_JUMP && e->f == NO_JUMP);\n+  int ek=\n+#ifdef LNUM_COMPLEX\n+    (e->k == VKNUM2) ||\n+#endif\n+    (e->k == VKINT) || (e->k == VKNUM);\n+  return (ek && e->t == NO_JUMP && e->f == NO_JUMP);\n }\n \n \n@@ -231,12 +236,16 @@ static int addk (FuncState *fs, TValue *\n   TValue *idx = luaH_set(L, fs->h, k);\n   Proto *f = fs->f;\n   int oldsize = f->sizek;\n-  if (ttisnumber(idx)) {\n-    lua_assert(luaO_rawequalObj(&fs->f->k[cast_int(nvalue(idx))], v));\n-    return cast_int(nvalue(idx));\n+  if (ttype(idx)==LUA_TNUMBER) {\n+    luai_normalize(idx);\n+    lua_assert( ttype(idx)==LUA_TINT );     /* had no fraction */\n+  }\n+  if (ttisint(idx)) {\n+    lua_assert(luaO_rawequalObj(&fs->f->k[ivalue(idx)], v));\n+    return cast_int(ivalue(idx));\n   }\n   else {  /* constant not found; create a new entry */\n-    setnvalue(idx, cast_num(fs->nk));\n+    setivalue(idx, fs->nk);\n     luaM_growvector(L, f->k, fs->nk, f->sizek, TValue,\n                     MAXARG_Bx, \"constant table overflow\");\n     while (oldsize < f->sizek) setnilvalue(&f->k[oldsize++]);\n@@ -261,6 +270,21 @@ int luaK_numberK (FuncState *fs, lua_Num\n }\n \n \n+int luaK_integerK (FuncState *fs, lua_Integer r) {\n+  TValue o;\n+  setivalue(&o, r);\n+  return addk(fs, &o, &o);\n+}\n+\n+\n+#ifdef LNUM_COMPLEX\n+static int luaK_imagK (FuncState *fs, lua_Number r) {\n+  TValue o;\n+  setnvalue_complex(&o, r*I);\n+  return addk(fs, &o, &o);\n+}\n+#endif\n+\n static int boolK (FuncState *fs, int b) {\n   TValue o;\n   setbvalue(&o, b);\n@@ -359,6 +383,16 @@ static void discharge2reg (FuncState *fs\n       luaK_codeABx(fs, OP_LOADK, reg, luaK_numberK(fs, e->u.nval));\n       break;\n     }\n+    case VKINT: {\n+      luaK_codeABx(fs, OP_LOADK, reg, luaK_integerK(fs, e->u.ival));\n+      break;\n+    }\n+#ifdef LNUM_COMPLEX\n+    case VKNUM2: {\n+      luaK_codeABx(fs, OP_LOADK, reg, luaK_imagK(fs, e->u.nval));\n+      break;\n+    }\n+#endif\n     case VRELOCABLE: {\n       Instruction *pc = &getcode(fs, e);\n       SETARG_A(*pc, reg);\n@@ -444,6 +478,10 @@ void luaK_exp2val (FuncState *fs, expdes\n int luaK_exp2RK (FuncState *fs, expdesc *e) {\n   luaK_exp2val(fs, e);\n   switch (e->k) {\n+#ifdef LNUM_COMPLEX\n+    case VKNUM2:\n+#endif\n+    case VKINT:\n     case VKNUM:\n     case VTRUE:\n     case VFALSE:\n@@ -451,6 +489,10 @@ int luaK_exp2RK (FuncState *fs, expdesc\n       if (fs->nk <= MAXINDEXRK) {  /* constant fit in RK operand? */\n         e->u.s.info = (e->k == VNIL)  ? nilK(fs) :\n                       (e->k == VKNUM) ? luaK_numberK(fs, e->u.nval) :\n+                      (e->k == VKINT) ? luaK_integerK(fs, e->u.ival) :\n+#ifdef LNUM_COMPLEX\n+                      (e->k == VKNUM2) ? luaK_imagK(fs, e->u.nval) :\n+#endif\n                                         boolK(fs, (e->k == VTRUE));\n         e->k = VK;\n         return RKASK(e->u.s.info);\n@@ -540,7 +582,10 @@ void luaK_goiftrue (FuncState *fs, expde\n   int pc;  /* pc of last jump */\n   luaK_dischargevars(fs, e);\n   switch (e->k) {\n-    case VK: case VKNUM: case VTRUE: {\n+#ifdef LNUM_COMPLEX\n+    case VKNUM2:\n+#endif\n+    case VKINT: case VK: case VKNUM: case VTRUE: {\n       pc = NO_JUMP;  /* always true; do nothing */\n       break;\n     }\n@@ -590,7 +635,10 @@ static void codenot (FuncState *fs, expd\n       e->k = VTRUE;\n       break;\n     }\n-    case VK: case VKNUM: case VTRUE: {\n+#ifdef LNUM_COMPLEX\n+    case VKNUM2:\n+#endif\n+    case VKINT: case VK: case VKNUM: case VTRUE: {\n       e->k = VFALSE;\n       break;\n     }\n@@ -626,25 +674,70 @@ void luaK_indexed (FuncState *fs, expdes\n \n static int constfolding (OpCode op, expdesc *e1, expdesc *e2) {\n   lua_Number v1, v2, r;\n+  int vkres= VKNUM;\n   if (!isnumeral(e1) || !isnumeral(e2)) return 0;\n-  v1 = e1->u.nval;\n-  v2 = e2->u.nval;\n+\n+  /* real and imaginary parts don't mix. */\n+#ifdef LNUM_COMPLEX\n+  if (e1->k == VKNUM2) {\n+    if ((op != OP_UNM) && (e2->k != VKNUM2)) return 0; \n+    vkres= VKNUM2; }\n+  else if (e2->k == VKNUM2) { return 0; }\n+#endif\n+  if ((e1->k == VKINT) && (e2->k == VKINT)) {\n+    lua_Integer i1= e1->u.ival, i2= e2->u.ival;\n+    lua_Integer rr;\n+    int done= 0;\n+    /* Integer/integer calculations (may end up producing floating point) */\n+    switch (op) {\n+      case OP_ADD: done= try_addint( &rr, i1, i2 ); break;\n+      case OP_SUB: done= try_subint( &rr, i1, i2 ); break;\n+      case OP_MUL: done= try_mulint( &rr, i1, i2 ); break;\n+      case OP_DIV: done= try_divint( &rr, i1, i2 ); break;\n+      case OP_MOD: done= try_modint( &rr, i1, i2 ); break;\n+      case OP_POW: done= try_powint( &rr, i1, i2 ); break;\n+      case OP_UNM: done= try_unmint( &rr, i1 ); break;\n+      default:     done= 0; break;\n+    }\n+    if (done) {\n+      e1->u.ival = rr;  /* remained within integer range */\n+      return 1;\n+    }\n+  }\n+  v1 = (e1->k == VKINT) ? ((lua_Number)e1->u.ival) : e1->u.nval;\n+  v2 = (e2->k == VKINT) ? ((lua_Number)e2->u.ival) : e2->u.nval;\n+\n   switch (op) {\n     case OP_ADD: r = luai_numadd(v1, v2); break;\n     case OP_SUB: r = luai_numsub(v1, v2); break;\n-    case OP_MUL: r = luai_nummul(v1, v2); break;\n+    case OP_MUL: \n+#ifdef LNUM_COMPLEX\n+        if (vkres==VKNUM2) return 0;    /* leave to runtime (could do here, but not worth it?) */\n+#endif\n+        r = luai_nummul(v1, v2); break;\n     case OP_DIV:\n       if (v2 == 0) return 0;  /* do not attempt to divide by 0 */\n-      r = luai_numdiv(v1, v2); break;\n+#ifdef LNUM_COMPLEX\n+        if (vkres==VKNUM2) return 0;    /* leave to runtime */\n+#endif\n+        r = luai_numdiv(v1, v2); break;\n     case OP_MOD:\n       if (v2 == 0) return 0;  /* do not attempt to divide by 0 */\n+#ifdef LNUM_COMPLEX\n+      if (vkres==VKNUM2) return 0;    /* leave to runtime */\n+#endif\n       r = luai_nummod(v1, v2); break;\n-    case OP_POW: r = luai_numpow(v1, v2); break;\n+    case OP_POW: \n+#ifdef LNUM_COMPLEX\n+      if (vkres==VKNUM2) return 0;    /* leave to runtime */\n+#endif\n+      r = luai_numpow(v1, v2); break;\n     case OP_UNM: r = luai_numunm(v1); break;\n     case OP_LEN: return 0;  /* no constant folding for 'len' */\n     default: lua_assert(0); r = 0; break;\n   }\n   if (luai_numisnan(r)) return 0;  /* do not attempt to produce NaN */\n+  e1->k = cast(expkind,vkres);\n   e1->u.nval = r;\n   return 1;\n }\n@@ -688,7 +781,8 @@ static void codecomp (FuncState *fs, OpC\n \n void luaK_prefix (FuncState *fs, UnOpr op, expdesc *e) {\n   expdesc e2;\n-  e2.t = e2.f = NO_JUMP; e2.k = VKNUM; e2.u.nval = 0;\n+  e2.t = e2.f = NO_JUMP; e2.k = VKINT; e2.u.ival = 0;\n+\n   switch (op) {\n     case OPR_MINUS: {\n       if (!isnumeral(e))\n--- a/src/lcode.h\n+++ b/src/lcode.h\n@@ -71,6 +71,6 @@ LUAI_FUNC void luaK_prefix (FuncState *f\n LUAI_FUNC void luaK_infix (FuncState *fs, BinOpr op, expdesc *v);\n LUAI_FUNC void luaK_posfix (FuncState *fs, BinOpr op, expdesc *v1, expdesc *v2);\n LUAI_FUNC void luaK_setlist (FuncState *fs, int base, int nelems, int tostore);\n-\n+LUAI_FUNC int luaK_integerK (FuncState *fs, lua_Integer r);\n \n #endif\n--- a/src/ldebug.c\n+++ b/src/ldebug.c\n@@ -183,7 +183,7 @@ static void collectvalidlines (lua_State\n     int *lineinfo = f->l.p->lineinfo;\n     int i;\n     for (i=0; i<f->l.p->sizelineinfo; i++)\n-      setbvalue(luaH_setnum(L, t, lineinfo[i]), 1);\n+      setbvalue(luaH_setint(L, t, lineinfo[i]), 1);\n     sethvalue(L, L->top, t); \n   }\n   incr_top(L);\n@@ -566,7 +566,7 @@ static int isinstack (CallInfo *ci, cons\n \n void luaG_typeerror (lua_State *L, const TValue *o, const char *op) {\n   const char *name = NULL;\n-  const char *t = luaT_typenames[ttype(o)];\n+  const char *t = luaT_typenames[ttype_ext(o)];\n   const char *kind = (isinstack(L->ci, o)) ?\n                          getobjname(L, L->ci, cast_int(o - L->base), &name) :\n                          NULL;\n@@ -594,8 +594,8 @@ void luaG_aritherror (lua_State *L, cons\n \n \n int luaG_ordererror (lua_State *L, const TValue *p1, const TValue *p2) {\n-  const char *t1 = luaT_typenames[ttype(p1)];\n-  const char *t2 = luaT_typenames[ttype(p2)];\n+  const char *t1 = luaT_typenames[ttype_ext(p1)];\n+  const char *t2 = luaT_typenames[ttype_ext(p2)];\n   if (t1[2] == t2[2])\n     luaG_runerror(L, \"attempt to compare two %s values\", t1);\n   else\n--- a/src/ldo.c\n+++ b/src/ldo.c\n@@ -220,9 +220,9 @@ static StkId adjust_varargs (lua_State *\n     luaD_checkstack(L, p->maxstacksize);\n     htab = luaH_new(L, nvar, 1);  /* create `arg' table */\n     for (i=0; i<nvar; i++)  /* put extra arguments into `arg' table */\n-      setobj2n(L, luaH_setnum(L, htab, i+1), L->top - nvar + i);\n+      setobj2n(L, luaH_setint(L, htab, i+1), L->top - nvar + i);\n     /* store counter in field `n' */\n-    setnvalue(luaH_setstr(L, htab, luaS_newliteral(L, \"n\")), cast_num(nvar));\n+    setivalue(luaH_setstr(L, htab, luaS_newliteral(L, \"n\")), nvar);\n   }\n #endif\n   /* move fixed parameters to final position */\n--- a/src/ldump.c\n+++ b/src/ldump.c\n@@ -52,6 +52,11 @@ static void DumpNumber(lua_Number x, Dum\n  DumpVar(x,D);\n }\n \n+static void DumpInteger(lua_Integer x, DumpState* D)\n+{\n+ DumpVar(x,D);\n+}\n+\n static void DumpVector(const void* b, int n, size_t size, DumpState* D)\n {\n  DumpInt(n,D);\n@@ -93,8 +98,11 @@ static void DumpConstants(const Proto* f\n \tDumpChar(bvalue(o),D);\n \tbreak;\n    case LUA_TNUMBER:\n-\tDumpNumber(nvalue(o),D);\n+\tDumpNumber(nvalue_fast(o),D);\n \tbreak;\n+   case LUA_TINT:\n+\tDumpInteger(ivalue(o),D);\n+    break;\n    case LUA_TSTRING:\n \tDumpString(rawtsvalue(o),D);\n \tbreak;\n--- a/src/liolib.c\n+++ b/src/liolib.c\n@@ -9,6 +9,7 @@\n #include <stdio.h>\n #include <stdlib.h>\n #include <string.h>\n+#include <ctype.h>\n \n #define liolib_c\n #define LUA_LIB\n@@ -18,7 +19,8 @@\n #include \"lauxlib.h\"\n #include \"lualib.h\"\n \n-\n+#include \"lnum.h\"\n+#include \"llex.h\"\n \n #define IO_INPUT\t1\n #define IO_OUTPUT\t2\n@@ -269,6 +271,13 @@ static int io_lines (lua_State *L) {\n ** =======================================================\n */\n \n+/*\n+* Many problems if we intend the same 'n' format specifier (see 'file:read()')\n+* to work for both FP and integer numbers, without losing their accuracy. So\n+* we don't. 'n' reads numbers as floating points, 'i' as integers. Old code\n+* remains valid, but won't provide full integer accuracy (this only matters\n+* with float FP and/or 64-bit integers).\n+*/\n \n static int read_number (lua_State *L, FILE *f) {\n   lua_Number d;\n@@ -282,6 +291,43 @@ static int read_number (lua_State *L, FI\n   }\n }\n \n+static int read_integer (lua_State *L, FILE *f) {\n+  lua_Integer i;\n+  if (fscanf(f, LUA_INTEGER_SCAN, &i) == 1) {\n+    lua_pushinteger(L, i);\n+    return 1;\n+  }\n+  else return 0;  /* read fails */\n+}\n+\n+#ifdef LNUM_COMPLEX\n+static int read_complex (lua_State *L, FILE *f) {\n+  /* NNN / NNNi / NNN+MMMi / NNN-MMMi */\n+  lua_Number a,b;\n+  if (fscanf(f, LUA_NUMBER_SCAN, &a) == 1) {\n+    int c=fgetc(f);\n+    switch(c) {\n+        case 'i':\n+            lua_pushcomplex(L, a*I);\n+            return 1;\n+        case '+':\n+        case '-':\n+            /* \"i\" is consumed if at the end; just 'NNN+MMM' will most likely\n+             * behave as if \"i\" was there? (TBD: test)\n+             */\n+            if (fscanf(f, LUA_NUMBER_SCAN \"i\", &b) == 1) {\n+                lua_pushcomplex(L, a+ (c=='+' ? b:-b)*I);\n+                return 1;\n+            }\n+    }\n+    ungetc( c,f );\n+    lua_pushnumber(L,a);  /*real part only*/\n+    return 1;\n+  }\n+  return 0;  /* read fails */\n+}\n+#endif\n+\n \n static int test_eof (lua_State *L, FILE *f) {\n   int c = getc(f);\n@@ -355,6 +401,14 @@ static int g_read (lua_State *L, FILE *f\n           case 'n':  /* number */\n             success = read_number(L, f);\n             break;\n+          case 'i':  /* integer (full accuracy) */\n+            success = read_integer(L, f);\n+            break;\n+#ifdef LNUM_COMPLEX\n+          case 'c':  /* complex */\n+            success = read_complex(L, f);\n+            break;\n+#endif\n           case 'l':  /* line */\n             success = read_line(L, f);\n             break;\n@@ -415,9 +469,10 @@ static int g_write (lua_State *L, FILE *\n   int status = 1;\n   for (; nargs--; arg++) {\n     if (lua_type(L, arg) == LUA_TNUMBER) {\n-      /* optimization: could be done exactly as for strings */\n-      status = status &&\n-          fprintf(f, LUA_NUMBER_FMT, lua_tonumber(L, arg)) > 0;\n+      if (lua_isinteger(L,arg))\n+          status = status && fprintf(f, LUA_INTEGER_FMT, lua_tointeger(L, arg)) > 0;\n+      else\n+          status = status && fprintf(f, LUA_NUMBER_FMT, lua_tonumber(L, arg)) > 0;\n     }\n     else {\n       size_t l;\n@@ -460,7 +515,7 @@ static int f_setvbuf (lua_State *L) {\n   static const char *const modenames[] = {\"no\", \"full\", \"line\", NULL};\n   FILE *f = tofile(L);\n   int op = luaL_checkoption(L, 2, NULL, modenames);\n-  lua_Integer sz = luaL_optinteger(L, 3, LUAL_BUFFERSIZE);\n+  size_t sz = luaL_optint32(L, 3, LUAL_BUFFERSIZE);\n   int res = setvbuf(f, NULL, mode[op], sz);\n   return pushresult(L, res == 0, NULL);\n }\n--- a/src/llex.c\n+++ b/src/llex.c\n@@ -22,6 +22,7 @@\n #include \"lstring.h\"\n #include \"ltable.h\"\n #include \"lzio.h\"\n+#include \"lnum.h\"\n \n \n \n@@ -34,13 +35,17 @@\n \n \n /* ORDER RESERVED */\n-const char *const luaX_tokens [] = {\n+static const char *const luaX_tokens [] = {\n     \"and\", \"break\", \"do\", \"else\", \"elseif\",\n     \"end\", \"false\", \"for\", \"function\", \"if\",\n     \"in\", \"local\", \"nil\", \"not\", \"or\", \"repeat\",\n     \"return\", \"then\", \"true\", \"until\", \"while\",\n     \"..\", \"...\", \"==\", \">=\", \"<=\", \"~=\",\n     \"<number>\", \"<name>\", \"<string>\", \"<eof>\",\n+    \"<integer>\",\n+#ifdef LNUM_COMPLEX\n+    \"<number2>\",\n+#endif\n     NULL\n };\n \n@@ -90,7 +95,11 @@ static const char *txtToken (LexState *l\n   switch (token) {\n     case TK_NAME:\n     case TK_STRING:\n+    case TK_INT:\n     case TK_NUMBER:\n+#ifdef LNUM_COMPLEX\n+    case TK_NUMBER2:\n+#endif\n       save(ls, '\\0');\n       return luaZ_buffer(ls->buff);\n     default:\n@@ -175,23 +184,27 @@ static void buffreplace (LexState *ls, c\n     if (p[n] == from) p[n] = to;\n }\n \n-\n-static void trydecpoint (LexState *ls, SemInfo *seminfo) {\n+/* TK_NUMBER (/ TK_NUMBER2) */\n+static int trydecpoint (LexState *ls, SemInfo *seminfo) {\n   /* format error: try to update decimal point separator */\n   struct lconv *cv = localeconv();\n   char old = ls->decpoint;\n+  int ret;\n   ls->decpoint = (cv ? cv->decimal_point[0] : '.');\n   buffreplace(ls, old, ls->decpoint);  /* try updated decimal separator */\n-  if (!luaO_str2d(luaZ_buffer(ls->buff), &seminfo->r)) {\n+  ret= luaO_str2d(luaZ_buffer(ls->buff), &seminfo->r, NULL);\n+  if (!ret) {\n     /* format error with correct decimal point: no more options */\n     buffreplace(ls, ls->decpoint, '.');  /* undo change (for error message) */\n     luaX_lexerror(ls, \"malformed number\", TK_NUMBER);\n   }\n+  return ret;\n }\n \n \n-/* LUA_NUMBER */\n-static void read_numeral (LexState *ls, SemInfo *seminfo) {\n+/* TK_NUMBER / TK_INT (/TK_NUMBER2) */\n+static int read_numeral (LexState *ls, SemInfo *seminfo) {\n+  int ret;\n   lua_assert(isdigit(ls->current));\n   do {\n     save_and_next(ls);\n@@ -202,8 +215,9 @@ static void read_numeral (LexState *ls,\n     save_and_next(ls);\n   save(ls, '\\0');\n   buffreplace(ls, '.', ls->decpoint);  /* follow locale for decimal point */\n-  if (!luaO_str2d(luaZ_buffer(ls->buff), &seminfo->r))  /* format error? */\n-    trydecpoint(ls, seminfo); /* try to update decimal point separator */\n+  ret= luaO_str2d(luaZ_buffer(ls->buff), &seminfo->r, &seminfo->i );\n+  if (!ret) return trydecpoint(ls, seminfo); /* try to update decimal point separator */\n+  return ret;\n }\n \n \n@@ -331,6 +345,7 @@ static void read_string (LexState *ls, i\n }\n \n \n+/* char / TK_* */\n static int llex (LexState *ls, SemInfo *seminfo) {\n   luaZ_resetbuffer(ls->buff);\n   for (;;) {\n@@ -402,8 +417,7 @@ static int llex (LexState *ls, SemInfo *\n         }\n         else if (!isdigit(ls->current)) return '.';\n         else {\n-          read_numeral(ls, seminfo);\n-          return TK_NUMBER;\n+          return read_numeral(ls, seminfo);\n         }\n       }\n       case EOZ: {\n@@ -416,8 +430,7 @@ static int llex (LexState *ls, SemInfo *\n           continue;\n         }\n         else if (isdigit(ls->current)) {\n-          read_numeral(ls, seminfo);\n-          return TK_NUMBER;\n+          return read_numeral(ls, seminfo);\n         }\n         else if (isalpha(ls->current) || ls->current == '_') {\n           /* identifier or reserved word */\n--- a/src/llex.h\n+++ b/src/llex.h\n@@ -29,19 +29,22 @@ enum RESERVED {\n   TK_RETURN, TK_THEN, TK_TRUE, TK_UNTIL, TK_WHILE,\n   /* other terminal symbols */\n   TK_CONCAT, TK_DOTS, TK_EQ, TK_GE, TK_LE, TK_NE, TK_NUMBER,\n-  TK_NAME, TK_STRING, TK_EOS\n+  TK_NAME, TK_STRING, TK_EOS, TK_INT\n+#ifdef LNUM_COMPLEX\n+  , TK_NUMBER2   /* imaginary constants: Ni */ \n+#endif\n };\n \n /* number of reserved words */\n #define NUM_RESERVED\t(cast(int, TK_WHILE-FIRST_RESERVED+1))\n \n \n-/* array with token `names' */\n-LUAI_DATA const char *const luaX_tokens [];\n-\n-\n+/* SemInfo is a local data structure of 'llex.c', used for carrying a string\n+ * or a number. A separate token (TK_*) will tell, how to interpret the data.\n+ */      \n typedef union {\n   lua_Number r;\n+  lua_Integer i;\n   TString *ts;\n } SemInfo;  /* semantics information */\n \n--- a/src/llimits.h\n+++ b/src/llimits.h\n@@ -49,6 +49,7 @@ typedef LUAI_USER_ALIGNMENT_T L_Umaxalig\n \n /* result of a `usual argument conversion' over lua_Number */\n typedef LUAI_UACNUMBER l_uacNumber;\n+typedef LUAI_UACINTEGER l_uacInteger;\n \n \n /* internal assertions for in-house debugging */\n@@ -80,7 +81,6 @@ typedef LUAI_UACNUMBER l_uacNumber;\n #define cast_int(i)\tcast(int, (i))\n \n \n-\n /*\n ** type for virtual-machine instructions\n ** must be an unsigned with (at least) 4 bytes (see details in lopcodes.h)\n--- a/src/lmathlib.c\n+++ b/src/lmathlib.c\n@@ -4,7 +4,6 @@\n ** See Copyright Notice in lua.h\n */\n \n-\n #include <stdlib.h>\n #include <math.h>\n \n@@ -16,113 +15,210 @@\n #include \"lauxlib.h\"\n #include \"lualib.h\"\n \n+/* 'luai_vectpow()' as a replacement for 'cpow()'. Defined in the header; we\n+ * don't intrude the code libs internal functions.\n+ */\n+#ifdef LNUM_COMPLEX\n+# include \"lnum.h\"    \n+#endif\n \n #undef PI\n-#define PI (3.14159265358979323846)\n-#define RADIANS_PER_DEGREE (PI/180.0)\n-\n-\n+#ifdef LNUM_FLOAT\n+# define PI (3.14159265358979323846F)\n+#elif defined(M_PI)\n+# define PI M_PI\n+#else\n+# define PI (3.14159265358979323846264338327950288)\n+#endif\n+#define RADIANS_PER_DEGREE (PI/180)\n+\n+#undef HUGE\n+#ifdef LNUM_FLOAT\n+# define HUGE HUGE_VALF\n+#elif defined(LNUM_LDOUBLE)\n+# define HUGE HUGE_VALL\n+#else\n+# define HUGE HUGE_VAL\n+#endif\n \n static int math_abs (lua_State *L) {\n-  lua_pushnumber(L, fabs(luaL_checknumber(L, 1)));\n+#ifdef LNUM_COMPLEX\n+  lua_pushnumber(L, _LF(cabs) (luaL_checkcomplex(L,1)));\n+#else\n+  lua_pushnumber(L, _LF(fabs) (luaL_checknumber(L, 1)));\n+#endif\n   return 1;\n }\n \n static int math_sin (lua_State *L) {\n-  lua_pushnumber(L, sin(luaL_checknumber(L, 1)));\n+#ifdef LNUM_COMPLEX\n+  lua_pushcomplex(L, _LF(csin) (luaL_checkcomplex(L,1)));\n+#else\n+  lua_pushnumber(L, _LF(sin) (luaL_checknumber(L, 1)));\n+#endif\n   return 1;\n }\n \n static int math_sinh (lua_State *L) {\n-  lua_pushnumber(L, sinh(luaL_checknumber(L, 1)));\n+#ifdef LNUM_COMPLEX\n+  lua_pushcomplex(L, _LF(csinh) (luaL_checkcomplex(L,1)));\n+#else\n+  lua_pushnumber(L, _LF(sinh) (luaL_checknumber(L, 1)));\n+#endif\n   return 1;\n }\n \n static int math_cos (lua_State *L) {\n-  lua_pushnumber(L, cos(luaL_checknumber(L, 1)));\n+#ifdef LNUM_COMPLEX\n+  lua_pushcomplex(L, _LF(ccos) (luaL_checkcomplex(L,1)));\n+#else\n+  lua_pushnumber(L, _LF(cos) (luaL_checknumber(L, 1)));\n+#endif\n   return 1;\n }\n \n static int math_cosh (lua_State *L) {\n-  lua_pushnumber(L, cosh(luaL_checknumber(L, 1)));\n+#ifdef LNUM_COMPLEX\n+  lua_pushcomplex(L, _LF(ccosh) (luaL_checkcomplex(L,1)));\n+#else\n+  lua_pushnumber(L, _LF(cosh) (luaL_checknumber(L, 1)));\n+#endif\n   return 1;\n }\n \n static int math_tan (lua_State *L) {\n-  lua_pushnumber(L, tan(luaL_checknumber(L, 1)));\n+#ifdef LNUM_COMPLEX\n+  lua_pushcomplex(L, _LF(ctan) (luaL_checkcomplex(L,1)));\n+#else\n+  lua_pushnumber(L, _LF(tan) (luaL_checknumber(L, 1)));\n+#endif\n   return 1;\n }\n \n static int math_tanh (lua_State *L) {\n-  lua_pushnumber(L, tanh(luaL_checknumber(L, 1)));\n+#ifdef LNUM_COMPLEX\n+  lua_pushcomplex(L, _LF(ctanh) (luaL_checkcomplex(L,1)));\n+#else\n+  lua_pushnumber(L, _LF(tanh) (luaL_checknumber(L, 1)));\n+#endif\n   return 1;\n }\n \n static int math_asin (lua_State *L) {\n-  lua_pushnumber(L, asin(luaL_checknumber(L, 1)));\n+#ifdef LNUM_COMPLEX\n+  lua_pushcomplex(L, _LF(casin) (luaL_checkcomplex(L,1)));\n+#else\n+  lua_pushnumber(L, _LF(asin) (luaL_checknumber(L, 1)));\n+#endif\n   return 1;\n }\n \n static int math_acos (lua_State *L) {\n-  lua_pushnumber(L, acos(luaL_checknumber(L, 1)));\n+#ifdef LNUM_COMPLEX\n+  lua_pushcomplex(L, _LF(cacos) (luaL_checkcomplex(L,1)));\n+#else\n+  lua_pushnumber(L, _LF(acos) (luaL_checknumber(L, 1)));\n+#endif\n   return 1;\n }\n \n static int math_atan (lua_State *L) {\n-  lua_pushnumber(L, atan(luaL_checknumber(L, 1)));\n+#ifdef LNUM_COMPLEX\n+  lua_pushcomplex(L, _LF(catan) (luaL_checkcomplex(L,1)));\n+#else\n+  lua_pushnumber(L, _LF(atan) (luaL_checknumber(L, 1)));\n+#endif\n   return 1;\n }\n \n static int math_atan2 (lua_State *L) {\n-  lua_pushnumber(L, atan2(luaL_checknumber(L, 1), luaL_checknumber(L, 2)));\n+  /* scalars only */\n+  lua_pushnumber(L, _LF(atan2) (luaL_checknumber(L, 1), luaL_checknumber(L, 2)));\n   return 1;\n }\n \n static int math_ceil (lua_State *L) {\n-  lua_pushnumber(L, ceil(luaL_checknumber(L, 1)));\n+#ifdef LNUM_COMPLEX\n+  lua_Complex v= luaL_checkcomplex(L, 1);\n+  lua_pushcomplex(L, _LF(ceil) (_LF(creal)(v)) + _LF(ceil) (_LF(cimag)(v))*I);\n+#else\n+  lua_pushnumber(L, _LF(ceil) (luaL_checknumber(L, 1)));\n+#endif\n   return 1;\n }\n \n static int math_floor (lua_State *L) {\n-  lua_pushnumber(L, floor(luaL_checknumber(L, 1)));\n+#ifdef LNUM_COMPLEX\n+  lua_Complex v= luaL_checkcomplex(L, 1);\n+  lua_pushcomplex(L, _LF(floor) (_LF(creal)(v)) + _LF(floor) (_LF(cimag)(v))*I);\n+#else\n+  lua_pushnumber(L, _LF(floor) (luaL_checknumber(L, 1)));\n+#endif\n   return 1;\n }\n \n-static int math_fmod (lua_State *L) {\n-  lua_pushnumber(L, fmod(luaL_checknumber(L, 1), luaL_checknumber(L, 2)));\n+static int math_fmod (lua_State *L) {  \n+  /* scalars only */\n+  lua_pushnumber(L, _LF(fmod) (luaL_checknumber(L, 1), luaL_checknumber(L, 2)));\n   return 1;\n }\n \n static int math_modf (lua_State *L) {\n-  double ip;\n-  double fp = modf(luaL_checknumber(L, 1), &ip);\n+  /* scalars only */\n+  lua_Number ip;\n+  lua_Number fp = _LF(modf) (luaL_checknumber(L, 1), &ip);\n   lua_pushnumber(L, ip);\n   lua_pushnumber(L, fp);\n   return 2;\n }\n \n static int math_sqrt (lua_State *L) {\n-  lua_pushnumber(L, sqrt(luaL_checknumber(L, 1)));\n+#ifdef LNUM_COMPLEX\n+  lua_pushcomplex(L, _LF(csqrt) (luaL_checkcomplex(L,1)));\n+#else\n+  lua_pushnumber(L, _LF(sqrt) (luaL_checknumber(L, 1)));\n+#endif\n   return 1;\n }\n \n static int math_pow (lua_State *L) {\n-  lua_pushnumber(L, pow(luaL_checknumber(L, 1), luaL_checknumber(L, 2)));\n+#ifdef LNUM_COMPLEX\n+  /* C99 'cpow' gives somewhat inaccurate results (i.e. (-1)^2 = -1+1.2246467991474e-16i). \n+  * 'luai_vectpow' smoothens such, reusing it is the reason we need to #include \"lnum.h\".\n+  */\n+  lua_pushcomplex(L, luai_vectpow(luaL_checkcomplex(L,1), luaL_checkcomplex(L,2)));\n+#else\n+  lua_pushnumber(L, _LF(pow) (luaL_checknumber(L, 1), luaL_checknumber(L, 2)));\n+#endif\n   return 1;\n }\n \n static int math_log (lua_State *L) {\n-  lua_pushnumber(L, log(luaL_checknumber(L, 1)));\n+#ifdef LNUM_COMPLEX\n+  lua_pushcomplex(L, _LF(clog) (luaL_checkcomplex(L,1)));\n+#else\n+  lua_pushnumber(L, _LF(log) (luaL_checknumber(L, 1)));\n+#endif\n   return 1;\n }\n \n static int math_log10 (lua_State *L) {\n-  lua_pushnumber(L, log10(luaL_checknumber(L, 1)));\n+#ifdef LNUM_COMPLEX\n+  /* Not in standard <complex.h> , but easy to calculate: log_a(x) = log_b(x) / log_b(a) \n+  */\n+  lua_pushcomplex(L, _LF(clog) (luaL_checkcomplex(L,1)) / _LF(log) (10));\n+#else\n+  lua_pushnumber(L, _LF(log10) (luaL_checknumber(L, 1)));\n+#endif\n   return 1;\n }\n \n static int math_exp (lua_State *L) {\n-  lua_pushnumber(L, exp(luaL_checknumber(L, 1)));\n+#ifdef LNUM_COMPLEX\n+  lua_pushcomplex(L, _LF(cexp) (luaL_checkcomplex(L,1)));\n+#else\n+  lua_pushnumber(L, _LF(exp) (luaL_checknumber(L, 1)));\n+#endif\n   return 1;\n }\n \n@@ -138,19 +234,20 @@ static int math_rad (lua_State *L) {\n \n static int math_frexp (lua_State *L) {\n   int e;\n-  lua_pushnumber(L, frexp(luaL_checknumber(L, 1), &e));\n+  lua_pushnumber(L, _LF(frexp) (luaL_checknumber(L, 1), &e));\n   lua_pushinteger(L, e);\n   return 2;\n }\n \n static int math_ldexp (lua_State *L) {\n-  lua_pushnumber(L, ldexp(luaL_checknumber(L, 1), luaL_checkint(L, 2)));\n+  lua_pushnumber(L, _LF(ldexp) (luaL_checknumber(L, 1), luaL_checkint(L, 2)));\n   return 1;\n }\n \n \n \n static int math_min (lua_State *L) {\n+  /* scalars only */\n   int n = lua_gettop(L);  /* number of arguments */\n   lua_Number dmin = luaL_checknumber(L, 1);\n   int i;\n@@ -165,6 +262,7 @@ static int math_min (lua_State *L) {\n \n \n static int math_max (lua_State *L) {\n+  /* scalars only */\n   int n = lua_gettop(L);  /* number of arguments */\n   lua_Number dmax = luaL_checknumber(L, 1);\n   int i;\n@@ -182,25 +280,20 @@ static int math_random (lua_State *L) {\n   /* the `%' avoids the (rare) case of r==1, and is needed also because on\n      some systems (SunOS!) `rand()' may return a value larger than RAND_MAX */\n   lua_Number r = (lua_Number)(rand()%RAND_MAX) / (lua_Number)RAND_MAX;\n-  switch (lua_gettop(L)) {  /* check number of arguments */\n-    case 0: {  /* no arguments */\n-      lua_pushnumber(L, r);  /* Number between 0 and 1 */\n-      break;\n-    }\n-    case 1: {  /* only upper limit */\n-      int u = luaL_checkint(L, 1);\n-      luaL_argcheck(L, 1<=u, 1, \"interval is empty\");\n-      lua_pushnumber(L, floor(r*u)+1);  /* int between 1 and `u' */\n-      break;\n-    }\n-    case 2: {  /* lower and upper limits */\n-      int l = luaL_checkint(L, 1);\n-      int u = luaL_checkint(L, 2);\n-      luaL_argcheck(L, l<=u, 2, \"interval is empty\");\n-      lua_pushnumber(L, floor(r*(u-l+1))+l);  /* int between `l' and `u' */\n-      break;\n-    }\n-    default: return luaL_error(L, \"wrong number of arguments\");\n+  int n= lua_gettop(L);  /* number of arguments */\n+  if (n==0) {\t/* no arguments: range [0,1) */\n+    lua_pushnumber(L, r);\n+  } else if (n<=2) {\t/* int range [1,u] or [l,u] */\n+    int l= n==1 ? 1 : luaL_checkint(L, 1);\n+    int u = luaL_checkint(L, n);\n+    int tmp;\n+    lua_Number d;\n+    luaL_argcheck(L, l<=u, n, \"interval is empty\");\n+    d= _LF(floor)(r*(u-l+1));\n+    lua_number2int(tmp,d);\n+    lua_pushinteger(L, l+tmp);\n+  } else {\n+    return luaL_error(L, \"wrong number of arguments\");\n   }\n   return 1;\n }\n@@ -211,6 +304,66 @@ static int math_randomseed (lua_State *L\n   return 0;\n }\n \n+/* \n+* Lua 5.1 does not have acosh, asinh, atanh for scalars (not ANSI C)\n+*/\n+#if __STDC_VERSION__ >= 199901L\n+static int math_acosh (lua_State *L) {\n+# ifdef LNUM_COMPLEX\n+  lua_pushcomplex(L, _LF(cacosh) (luaL_checkcomplex(L,1)));\n+# else\n+  lua_pushnumber(L, _LF(acosh) (luaL_checknumber(L,1)));\n+# endif\n+  return 1;\n+}\n+static int math_asinh (lua_State *L) {\n+# ifdef LNUM_COMPLEX\n+  lua_pushcomplex(L, _LF(casinh) (luaL_checkcomplex(L,1)));\n+# else\n+  lua_pushnumber(L, _LF(asinh) (luaL_checknumber(L,1)));\n+# endif\n+  return 1;\n+}\n+static int math_atanh (lua_State *L) {\n+# ifdef LNUM_COMPLEX\n+  lua_pushcomplex(L, _LF(catanh) (luaL_checkcomplex(L,1)));\n+# else\n+  lua_pushnumber(L, _LF(atanh) (luaL_checknumber(L,1)));\n+# endif\n+  return 1;\n+}\n+#endif\n+\n+/* \n+ * C99 complex functions, not covered above.\n+*/\n+#ifdef LNUM_COMPLEX\n+static int math_arg (lua_State *L) {\n+  lua_pushnumber(L, _LF(carg) (luaL_checkcomplex(L,1)));\n+  return 1;\n+}\n+\n+static int math_imag (lua_State *L) {\n+  lua_pushnumber(L, _LF(cimag) (luaL_checkcomplex(L,1)));\n+  return 1;\n+}\n+\n+static int math_real (lua_State *L) {\n+  lua_pushnumber(L, _LF(creal) (luaL_checkcomplex(L,1)));\n+  return 1;\n+}\n+\n+static int math_conj (lua_State *L) {\n+  lua_pushcomplex(L, _LF(conj) (luaL_checkcomplex(L,1)));\n+  return 1;\n+}\n+\n+static int math_proj (lua_State *L) {\n+  lua_pushcomplex(L, _LF(cproj) (luaL_checkcomplex(L,1)));\n+  return 1;\n+}\n+#endif\n+\n \n static const luaL_Reg mathlib[] = {\n   {\"abs\",   math_abs},\n@@ -241,6 +394,18 @@ static const luaL_Reg mathlib[] = {\n   {\"sqrt\",  math_sqrt},\n   {\"tanh\",   math_tanh},\n   {\"tan\",   math_tan},\n+#if __STDC_VERSION__ >= 199901L\n+  {\"acosh\",  math_acosh},\n+  {\"asinh\",  math_asinh},\n+  {\"atanh\",  math_atanh},\n+#endif\n+#ifdef LNUM_COMPLEX\n+  {\"arg\",   math_arg},\n+  {\"imag\",  math_imag},\n+  {\"real\",  math_real},\n+  {\"conj\",  math_conj},\n+  {\"proj\",  math_proj},\n+#endif\n   {NULL, NULL}\n };\n \n@@ -252,8 +417,10 @@ LUALIB_API int luaopen_math (lua_State *\n   luaL_register(L, LUA_MATHLIBNAME, mathlib);\n   lua_pushnumber(L, PI);\n   lua_setfield(L, -2, \"pi\");\n-  lua_pushnumber(L, HUGE_VAL);\n+  lua_pushnumber(L, HUGE);\n   lua_setfield(L, -2, \"huge\");\n+  lua_pushinteger(L, LUA_INTEGER_MAX );\n+  lua_setfield(L, -2, \"hugeint\");\n #if defined(LUA_COMPAT_MOD)\n   lua_getfield(L, -1, \"fmod\");\n   lua_setfield(L, -2, \"mod\");\n--- /dev/null\n+++ b/src/lnum.c\n@@ -0,0 +1,312 @@\n+/*\n+** $Id: lnum.c,v ... $\n+** Internal number model\n+** See Copyright Notice in lua.h\n+*/\n+\n+#include <stdlib.h>\n+#include <math.h>\n+#include <ctype.h>\n+#include <string.h>\n+#include <stdio.h>\n+#include <errno.h>\n+\n+#define lnum_c\n+#define LUA_CORE\n+\n+#include \"lua.h\"\n+#include \"llex.h\"\n+#include \"lnum.h\"\n+\n+/*\n+** lua_real2str converts a (non-complex) number to a string.\n+** lua_str2real converts a string to a (non-complex) number.\n+*/\n+#define lua_real2str(s,n)  sprintf((s), LUA_NUMBER_FMT, (n))\n+\n+/*\n+* Note: Only 'strtod()' is part of ANSI C; others are C99 and\n+* may need '--std=c99' compiler setting (at least on Ubuntu 7.10).\n+* \n+* Visual C++ 2008 Express does not have 'strtof()', nor 'strtold()'.\n+* References to '_strtold()' exist but don't compile. It seems best\n+* to leave Windows users with DOUBLE only (or compile with MinGW).\n+*\n+* In practise, using '(long double)strtod' is a risky thing, since\n+* it will cause accuracy loss in reading in numbers, and such losses\n+* will pile up in later processing. Get a real 'strtold()' or don't\n+* use that mode at all.\n+*/\n+#ifdef LNUM_DOUBLE\n+# define lua_str2real\tstrtod\n+#elif defined(LNUM_FLOAT)\n+# define lua_str2real\tstrtof\n+#elif defined(LNUM_LDOUBLE)\n+# define lua_str2real\tstrtold\n+#endif\n+\n+#define lua_integer2str(s,v) sprintf((s), LUA_INTEGER_FMT, (v))\n+\n+/* 's' is expected to be LUAI_MAXNUMBER2STR long (enough for any number)\n+*/\n+void luaO_num2buf( char *s, const TValue *o )\n+{\n+  lua_Number n;\n+  lua_assert( ttisnumber(o) );\n+\n+  /* Reason to handle integers differently is not only speed, but accuracy as\n+   * well. We want to make any integer tostring() without roundings, at all.\n+   */\n+  if (ttisint(o)) {\n+    lua_integer2str( s, ivalue(o) );\n+    return;\n+  }\n+  n= nvalue_fast(o);\n+  lua_real2str(s, n);\n+\n+#ifdef LNUM_COMPLEX\n+  lua_Number n2= nvalue_img_fast(o);\n+  if (n2!=0) {   /* Postfix with +-Ni */\n+      int re0= (n == 0);\n+      char *s2= re0 ? s : strchr(s,'\\0'); \n+      if ((!re0) && (n2>0)) *s2++= '+';\n+      lua_real2str( s2, n2 );\n+      strcat(s2,\"i\");\n+  }\n+#endif\n+}\n+\n+/*\n+* If a LUA_TNUMBER has integer value, give it.\n+*/\n+int /*bool*/ tt_integer_valued( const TValue *o, lua_Integer *ref ) {\n+  lua_Number d;\n+  lua_Integer i;\n+\n+  lua_assert( ttype(o)==LUA_TNUMBER );\n+  lua_assert( ref );\n+#ifdef LNUM_COMPLEX\n+  if (nvalue_img_fast(o)!=0) return 0;\n+#endif\n+  d= nvalue_fast(o);\n+  lua_number2integer(i, d);\n+  if (cast_num(i) == d) {\n+    *ref= i; return 1;\n+  }\n+  return 0;\n+}\n+\n+/* \n+ * Lua 5.1.3 (using 'strtod()') allows 0x+hex but not 0+octal. This is good,\n+ * and we should NOT use 'autobase' 0 with 'strtoul[l]()' for this reason.\n+ *\n+ * Lua 5.1.3 allows '0x...' numbers to overflow and lose precision; this is not\n+ * good. On Visual C++ 2008, 'strtod()' does not even take them in. Better to\n+ * require hex values to fit 'lua_Integer' or give an error that they don't?\n+ *\n+ * Full hex range (0 .. 0xff..ff) is stored as integers, not to lose any bits.\n+ * Numerical value of 0xff..ff will be -1, if used in calculations.\n+ * \n+ * Returns: TK_INT for a valid integer, '*endptr_ref' updated\n+ *          TK_NUMBER for seemingly numeric, to be parsed as floating point\n+ *          0 for bad characters, not a number (or '0x' out of range)\n+ */\n+static int luaO_str2i (const char *s, lua_Integer *res, char **endptr_ref) {\n+  char *endptr;\n+  /* 'v' gets ULONG_MAX on possible overflow (which is > LUA_INTEGER_MAX);\n+   * we don't have to check 'errno' here.\n+   */\n+  unsigned LUA_INTEGER v= lua_str2ul(s, &endptr, 10);\n+  if (endptr == s) return 0;  /* nothing numeric */\n+  if (v==0 && *endptr=='x') {\n+    errno= 0;   /* needs to be set, 'strtoul[l]' does not clear it */\n+    v= lua_str2ul(endptr+1, &endptr, 16);  /* retry as hex, unsigned range */\n+    if (errno==ERANGE) {   /* clamped to 0xff..ff */\n+#if (defined(LNUM_INT32) && !defined(LNUM_FLOAT)) || defined(LNUM_LDOUBLE)\n+      return TK_NUMBER; /* Allow to be read as floating point (has more integer range) */\n+#else\n+      return 0;  /* Reject the number */\n+#endif\n+    }\n+  } else if ((v > LUA_INTEGER_MAX) || (*endptr && (!isspace(*endptr)))) {\n+    return TK_NUMBER;\t/* not in signed range, or has '.', 'e' etc. trailing */\n+  }\n+  *res= (lua_Integer)v;\n+  *endptr_ref= endptr;\n+  return TK_INT;\n+}\n+\n+/* 0 / TK_NUMBER / TK_INT (/ TK_NUMBER2) */\n+int luaO_str2d (const char *s, lua_Number *res_n, lua_Integer *res_i) {\n+  char *endptr;\n+  int ret= TK_NUMBER;\n+  /* Check integers first, if caller is allowing. \n+   * If 'res2'==NULL, they're only looking for floating point. \n+   */\n+  if (res_i) {\n+    ret= luaO_str2i(s,res_i,&endptr);\n+    if (ret==0) return 0;\n+  }\n+  if (ret==TK_NUMBER) {\n+    lua_assert(res_n);\n+    /* Note: Visual C++ 2008 Express 'strtod()' does not read in \"0x...\"\n+     *       numbers; it will read '0' and spit 'x' as endptr.\n+     *       This means hex constants not fitting in 'lua_Integer' won't \n+     *       be read in at all. What to do?\n+     */\n+    *res_n = lua_str2real(s, &endptr);\n+    if (endptr == s) return 0;  /* conversion failed */\n+    /* Visual C++ 2008 'strtod()' does not allow \"0x...\" input. */\n+#if defined(_MSC_VER) && !defined(LNUM_FLOAT) && !defined(LNUM_INT64)\n+    if (*res_n==0 && *endptr=='x') {\n+      /* Hex constant too big for 'lua_Integer' but that could fit in 'lua_Number'\n+       * integer bits \n+       */\n+      unsigned __int64 v= _strtoui64( s, &endptr, 16 );\n+      /* We just let > 64 bit values be clamped to _UI64_MAX (MSDN does not say 'errno'==ERANGE would be set) */\n+      *res_n= cast_num(v);\n+      if (*res_n != v) return 0;    /* Would have lost accuracy */\n+    }\n+#endif\n+#ifdef LNUM_COMPLEX\n+    if (*endptr == 'i') { endptr++; ret= TK_NUMBER2; }\n+#endif\n+  }\n+  if (*endptr) {\n+    while (isspace(cast(unsigned char, *endptr))) endptr++;\n+    if (*endptr) return 0;  /* invalid trail */\n+  }\n+  return ret;\n+}\n+\n+\n+/* Functions for finding out, when integer operations remain in range\n+ * (and doing them).\n+ */\n+int try_addint( lua_Integer *r, lua_Integer ib, lua_Integer ic ) {\n+  lua_Integer v= ib+ic; /* may overflow */\n+  if (ib>0 && ic>0)      { if (v < 0) return 0; /*overflow, use floats*/ }\n+  else if (ib<0 && ic<0) { if (v >= 0) return 0; }\n+  *r= v;\n+  return 1;\n+}\n+\n+int try_subint( lua_Integer *r, lua_Integer ib, lua_Integer ic ) {\n+  lua_Integer v= ib-ic; /* may overflow */\n+  if (ib>=0 && ic<0)     { if (v < 0) return 0; /*overflow, use floats*/ }\n+  else if (ib<0 && ic>0) { if (v >= 0) return 0; }\n+  *r= v;\n+  return 1;\n+}\n+\n+int try_mulint( lua_Integer *r, lua_Integer ib, lua_Integer ic ) {\n+  if (ib!=LUA_INTEGER_MIN && ic!=LUA_INTEGER_MIN) {\n+    lua_Integer b= luai_abs(ib), c= luai_abs(ic);\n+    if ( (ib==0) || (LUA_INTEGER_MAX/b >= c) ) {\n+      *r= ib*ic;  /* no overflow */\n+      return 1;\n+    }\n+  } else if (ib==0 || ic==0) {\n+    *r= 0; return 1;\n+  }\n+\n+  /* Result can be LUA_INTEGER_MIN; if it is, calculating it using floating \n+   * point will not cause accuracy loss.\n+   */\n+  if ( luai_nummul( cast_num(ib), cast_num(ic) ) == LUA_INTEGER_MIN ) {\n+    *r= LUA_INTEGER_MIN;\n+    return 1;\n+  }\n+  return 0;\n+}\n+\n+int try_divint( lua_Integer *r, lua_Integer ib, lua_Integer ic ) {\n+  /* N/0: leave to float side, to give an error\n+  */\n+  if (ic==0) return 0;\n+\n+  /* N/LUA_INTEGER_MIN: always non-integer results, or 0 or +1\n+  */\n+  if (ic==LUA_INTEGER_MIN) {\n+    if (ib==LUA_INTEGER_MIN) { *r=1; return 1; }\n+    if (ib==0) { *r=0; return 1; }\n+\n+  /* LUA_INTEGER_MIN (-2^31|63)/N: calculate using float side (either the division \n+   *    causes non-integer results, or there is no accuracy loss in int->fp->int\n+   *    conversions (N=2,4,8,..,256 and N=2^30,2^29,..2^23).\n+   */\n+  } else if (ib==LUA_INTEGER_MIN) {\n+    lua_Number d= luai_numdiv( cast_num(LUA_INTEGER_MIN), cast_num(ic) );\n+    lua_Integer i; lua_number2integer(i,d);\n+    if (cast_num(i)==d) { *r= i; return 1; }\n+  \n+  } else {\n+    /* Note: We _can_ use ANSI C mod here, even on negative values, since\n+     *       we only test for == 0 (the sign would be implementation dependent).\n+     */\n+     if (ib%ic == 0) { *r= ib/ic; return 1; }\n+  }\n+\n+  return 0;\n+}\n+\n+int try_modint( lua_Integer *r, lua_Integer ib, lua_Integer ic ) {\n+  if (ic!=0) {\n+    /* ANSI C can be trusted when b%c==0, or when values are non-negative. \n+     * b - (floor(b/c) * c)\n+     *   -->\n+     * + +: b - (b/c) * c (b % c can be used)\n+     * - -: b - (b/c) * c (b % c could work, but not defined by ANSI C)\n+     * 0 -: b - (b/c) * c (=0, b % c could work, but not defined by ANSI C)\n+     * - +: b - (b/c-1) * c (when b!=-c)\n+     * + -: b - (b/c-1) * c (when b!=-c)\n+     *\n+     * o MIN%MIN ends up 0, via overflow in calcs but that does not matter.\n+     * o MIN%MAX ends up MAX-1 (and other such numbers), also after overflow,\n+     *   but that does not matter, results do.\n+     */\n+    lua_Integer v= ib % ic;\n+    if ( v!=0 && (ib<0 || ic<0) ) {\n+      v= ib - ((ib/ic) - ((ib<=0 && ic<0) ? 0:1)) * ic;\n+    }      \n+    /* Result should always have same sign as 2nd argument. (PIL2) */\n+    lua_assert( (v<0) ? (ic<0) : (v>0) ? (ic>0) : 1 );\n+    *r= v;\n+    return 1;\n+  }\n+  return 0;  /* let float side return NaN */\n+}\n+\n+int try_powint( lua_Integer *r, lua_Integer ib, lua_Integer ic ) {\n+\n+    /* In FLOAT/INT32 or FLOAT|DOUBLE/INT64 modes, calculating integer powers \n+     * via FP realm may lose accuracy (i.e. 7^11 = 1977326743, which fits int32\n+     * but not 23-bit float mantissa). \n+     *\n+     * The current solution is dumb, but it works and uses little code. Use of\n+     * integer powers is not anticipated to be very frequent (apart from 2^x,\n+     * which is separately optimized).\n+     */\n+  if (ib==0) *r=0;\n+  else if (ic<0) return 0;  /* FP realm */\n+  else if (ib==2 && ic < (int)sizeof(lua_Integer)*8-1) *r= ((lua_Integer)1)<<ic;   /* 1,2,4,...2^30 | 2^62 optimization */\n+  else if (ic==0) *r=1;\n+  else if (luai_abs(ib)==1) *r= (ic%2) ? ib:1;\n+  else {\n+    lua_Integer x= ib;\n+    while( --ic ) {\n+      if (!try_mulint( &x, x, ib ))\n+        return 0; /* FP realm */\n+    }\n+    *r= x;\n+  }\n+  return 1;\n+}\n+\n+int try_unmint( lua_Integer *r, lua_Integer ib ) {\n+  /* Negating LUA_INTEGER_MIN leaves the range. */\n+  if ( ib != LUA_INTEGER_MIN )  \n+    { *r= -ib; return 1; }\n+  return 0;\n+}\n+\n--- /dev/null\n+++ b/src/lnum.h\n@@ -0,0 +1,116 @@\n+/*\n+** $Id: lnum.h,v ... $\n+** Internal Number model\n+** See Copyright Notice in lua.h\n+*/\n+\n+#ifndef lnum_h\n+#define lnum_h\n+\n+#include <math.h>\n+\n+#include \"lobject.h\"\n+\n+/*\n+** The luai_num* macros define the primitive operations over 'lua_Number's\n+** (not 'lua_Integer's, not 'lua_Complex').\n+*/\n+#define luai_numadd(a,b)\t((a)+(b))\n+#define luai_numsub(a,b)\t((a)-(b))\n+#define luai_nummul(a,b)\t((a)*(b))\n+#define luai_numdiv(a,b)\t((a)/(b))\n+#define luai_nummod(a,b)\t((a) - _LF(floor)((a)/(b))*(b))\n+#define luai_numpow(a,b)\t(_LF(pow)(a,b))\n+#define luai_numunm(a)\t\t(-(a))\n+#define luai_numeq(a,b)\t    ((a)==(b))\n+#define luai_numlt(a,b)\t    ((a)<(b))\n+#define luai_numle(a,b)\t    ((a)<=(b))\n+#define luai_numisnan(a)\t(!luai_numeq((a), (a)))\n+\n+int try_addint( lua_Integer *r, lua_Integer ib, lua_Integer ic );\n+int try_subint( lua_Integer *r, lua_Integer ib, lua_Integer ic );\n+int try_mulint( lua_Integer *r, lua_Integer ib, lua_Integer ic );\n+int try_divint( lua_Integer *r, lua_Integer ib, lua_Integer ic );\n+int try_modint( lua_Integer *r, lua_Integer ib, lua_Integer ic );\n+int try_powint( lua_Integer *r, lua_Integer ib, lua_Integer ic );\n+int try_unmint( lua_Integer *r, lua_Integer ib );\n+\n+#ifdef LNUM_COMPLEX\n+  static inline lua_Complex luai_vectunm( lua_Complex a ) { return -a; }\n+  static inline lua_Complex luai_vectadd( lua_Complex a, lua_Complex b ) { return a+b; }\n+  static inline lua_Complex luai_vectsub( lua_Complex a, lua_Complex b ) { return a-b; }\n+  static inline lua_Complex luai_vectmul( lua_Complex a, lua_Complex b ) { return a*b; }\n+  static inline lua_Complex luai_vectdiv( lua_Complex a, lua_Complex b ) { return a/b; }\n+\n+/* \n+ * C99 does not provide modulus for complex numbers. It most likely is not\n+ * meaningful at all.\n+ */\n+\n+/* \n+ * Complex power\n+ *\n+ * C99 'cpow' gives inaccurate results for many common cases s.a. (1i)^2 -> \n+ * -1+1.2246467991474e-16i (OS X 10.4, gcc 4.0.1 build 5367)\n+ * \n+ * [(a+bi)^(c+di)] = (r^c) * exp(-d*t) * cos(c*t + d*ln(r)) +\n+ *                 = (r^c) * exp(-d*t) * sin(c*t + d*ln(r)) *i\n+ * r = sqrt(a^2+b^2), t = arctan( b/a )\n+ * \n+ * Reference: <http://home.att.net/~srschmitt/complexnumbers.html>\n+ * Could also be calculated using: x^y = exp(ln(x)*y)\n+ *\n+ * Note: Defined here (and not in .c) so 'lmathlib.c' can share the \n+ *       implementation.\n+ */\n+  static inline\n+  lua_Complex luai_vectpow( lua_Complex a, lua_Complex b )\n+  {\n+# if 1\n+    lua_Number ar= _LF(creal)(a), ai= _LF(cimag)(a);\n+    lua_Number br= _LF(creal)(b), bi= _LF(cimag)(b);\n+    \n+    if (ai==0 && bi==0) {     /* a^c (real) */\n+        return luai_numpow( ar, br );\n+    } \n+\n+    int br_int= (int)br;\n+    \n+    if ( ai!=0 && bi==0 && br_int==br && br_int!=0 && br_int!=INT_MIN ) { \n+        /* (a+bi)^N, N = { +-1,+-2, ... +-INT_MAX } \n+        */\n+        lua_Number k= luai_numpow( _LF(sqrt) (ar*ar + ai*ai), br );\n+        lua_Number cos_z, sin_z;\n+\n+        /* Situation depends upon c (N) in the following manner:\n+         * \n+         * N%4==0                                => cos(c*t)=1, sin(c*t)=0\n+         * (N*sign(b))%4==1 or (N*sign(b))%4==-3 => cos(c*t)=0, sin(c*t)=1\n+         * N%4==2 or N%4==-2                     => cos(c*t)=-1, sin(c*t)=0\n+         * (N*sign(b))%4==-1 or (N*sign(b))%4==3 => cos(c*t)=0, sin(c*t)=-1\n+         */\n+      int br_int_abs = br_int<0 ? -br_int:br_int;\n+      \n+      switch( (br_int_abs%4) * (br_int<0 ? -1:1) * (ai<0 ? -1:1) ) {\n+        case 0:             cos_z=1, sin_z=0; break;\n+        case 2: case -2:    cos_z=-1, sin_z=0; break;\n+        case 1: case -3:    cos_z=0, sin_z=1; break;\n+        case 3: case -1:    cos_z=0, sin_z=-1; break;\n+        default:            lua_assert(0); return 0;\n+      }\n+      return k*cos_z + (k*sin_z)*I;\n+    }\n+# endif\n+    return _LF(cpow) ( a, b );\n+  }\n+#endif\n+\n+LUAI_FUNC int luaO_str2d (const char *s, lua_Number *res1, lua_Integer *res2);\n+LUAI_FUNC void luaO_num2buf( char *s, const TValue *o );\n+\n+LUAI_FUNC int /*bool*/ tt_integer_valued( const TValue *o, lua_Integer *ref );\n+\n+#define luai_normalize(o) \\\n+{ lua_Integer _i; if (tt_integer_valued(o,&_i)) setivalue(o,_i); }\n+\n+#endif\n--- /dev/null\n+++ b/src/lnum_config.h\n@@ -0,0 +1,221 @@\n+/*\n+** $Id: lnum_config.h,v ... $\n+** Internal Number model\n+** See Copyright Notice in lua.h\n+*/\n+\n+#ifndef lnum_config_h\n+#define lnum_config_h\n+\n+/*\n+** Default number modes\n+*/\n+#if (!defined LNUM_DOUBLE) && (!defined LNUM_FLOAT) && (!defined LNUM_LDOUBLE)\n+# define LNUM_FLOAT\n+#endif\n+#if (!defined LNUM_INT16) && (!defined LNUM_INT32) && (!defined LNUM_INT64)\n+# define LNUM_INT32\n+#endif\n+\n+/*\n+** Require C99 mode for COMPLEX, FLOAT and LDOUBLE (only DOUBLE is ANSI C).\n+*/\n+#if defined(LNUM_COMPLEX) && (__STDC_VERSION__ < 199901L)\n+# error \"Need C99 for complex (use '--std=c99' or similar)\"\n+#elif defined(LNUM_LDOUBLE) && (__STDC_VERSION__ < 199901L) && !defined(_MSC_VER)\n+# error \"Need C99 for 'long double' (use '--std=c99' or similar)\"\n+#elif defined(LNUM_FLOAT) && (__STDC_VERSION__ < 199901L)\n+/* LNUM_FLOAT not supported on Windows */\n+# error \"Need C99 for 'float' (use '--std=c99' or similar)\"\n+#endif\n+ \n+/*\n+** Number mode identifier to accompany the version string.\n+*/\n+#ifdef LNUM_COMPLEX\n+# define _LNUM1 \"complex \"\n+#else\n+# define _LNUM1 \"\"\n+#endif\n+#ifdef LNUM_DOUBLE\n+# define _LNUM2 \"double\"\n+#elif defined(LNUM_FLOAT)\n+# define _LNUM2 \"float\"\n+#elif defined(LNUM_LDOUBLE)\n+# define _LNUM2 \"ldouble\"\n+#endif\n+#ifdef LNUM_INT32\n+# define _LNUM3 \"int32\"\n+#elif defined(LNUM_INT64)\n+# define _LNUM3 \"int64\"\n+#elif defined(LNUM_INT16)\n+# define _LNUM3 \"int16\"\n+#endif\n+#define LUA_LNUM _LNUM1 _LNUM2 \" \" _LNUM3\n+\n+/*\n+** LUA_NUMBER is the type of floating point number in Lua\n+** LUA_NUMBER_SCAN is the format for reading numbers.\n+** LUA_NUMBER_FMT is the format for writing numbers.\n+*/\n+#ifdef LNUM_FLOAT\n+# define LUA_NUMBER         float\n+# define LUA_NUMBER_SCAN    \"%f\"\n+# define LUA_NUMBER_FMT     \"%g\"  \n+#elif (defined LNUM_DOUBLE)\n+# define LUA_NUMBER\t        double\n+# define LUA_NUMBER_SCAN    \"%lf\"\n+# define LUA_NUMBER_FMT     \"%.14g\"\n+#elif (defined LNUM_LDOUBLE)\n+# define LUA_NUMBER         long double\n+# define LUA_NUMBER_SCAN    \"%Lg\"\n+# define LUA_NUMBER_FMT     \"%.20Lg\"\n+#endif\n+\n+\n+/* \n+** LUAI_MAXNUMBER2STR: size of a buffer fitting any number->string result.\n+**\n+**  double:  24 (sign, x.xxxxxxxxxxxxxxe+nnnn, and \\0)\n+**  int64:   21 (19 digits, sign, and \\0)\n+**  long double: 43 for 128-bit (sign, x.xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxe+nnnn, and \\0)\n+**           30 for 80-bit (sign, x.xxxxxxxxxxxxxxxxxxxxe+nnnn, and \\0)\n+*/\n+#ifdef LNUM_LDOUBLE\n+# define _LUAI_MN2S 44\n+#else\n+# define _LUAI_MN2S 24\n+#endif\n+\n+#ifdef LNUM_COMPLEX\n+# define LUAI_MAXNUMBER2STR (2*_LUAI_MN2S)\n+#else\n+# define LUAI_MAXNUMBER2STR _LUAI_MN2S\n+#endif\n+\n+/*\n+** LUA_INTEGER is the integer type used by lua_pushinteger/lua_tointeger/lua_isinteger.\n+** LUA_INTEGER_SCAN is the format for reading integers\n+** LUA_INTEGER_FMT is the format for writing integers\n+**\n+** Note: Visual C++ 2005 does not have 'strtoull()', use '_strtoui64()' instead.\n+*/\n+#ifdef LNUM_INT32\n+# if LUAI_BITSINT > 16\n+#  define LUA_INTEGER   int\n+#  define LUA_INTEGER_SCAN \"%d\"\n+#  define LUA_INTEGER_FMT \"%d\"\n+# else\n+/* Note: 'LUA_INTEGER' being 'ptrdiff_t' (as in Lua 5.1) causes problems with\n+ *       'printf()' operations. Also 'unsigned ptrdiff_t' is invalid.\n+ */\n+#  define LUA_INTEGER   long\n+#  define LUA_INTEGER_SCAN \"%ld\"\n+#  define LUA_INTEGER_FMT \"%ld\"\n+# endif\n+# define LUA_INTEGER_MAX 0x7FFFFFFF             /* 2^31-1 */\n+/* */\n+#elif defined(LNUM_INT64)\n+# define LUA_INTEGER\tlong long\n+# ifdef _MSC_VER\n+#  define lua_str2ul    _strtoui64\n+# else\n+#  define lua_str2ul    strtoull\n+# endif\n+# define LUA_INTEGER_SCAN \"%lld\"\n+# define LUA_INTEGER_FMT \"%lld\"\n+# define LUA_INTEGER_MAX 0x7fffffffffffffffLL       /* 2^63-1 */ \n+# define LUA_INTEGER_MIN (-LUA_INTEGER_MAX - 1LL)   /* -2^63 */\n+/* */\n+#elif defined(LNUM_INT16)\n+# if LUAI_BITSINT > 16\n+#  define LUA_INTEGER    short\n+#  define LUA_INTEGER_SCAN \"%hd\"\n+#  define LUA_INTEGER_FMT \"%hd\"\n+# else\n+#  define LUA_INTEGER    int\n+#  define LUA_INTEGER_SCAN \"%d\"\n+#  define LUA_INTEGER_FMT \"%d\"\n+# endif\n+# define LUA_INTEGER_MAX 0x7FFF             /* 2^16-1 */\n+#endif\n+\n+#ifndef lua_str2ul\n+# define lua_str2ul (unsigned LUA_INTEGER)strtoul\n+#endif\n+#ifndef LUA_INTEGER_MIN\n+# define LUA_INTEGER_MIN (-LUA_INTEGER_MAX -1)  /* -2^16|32 */\n+#endif\n+\n+/*\n+@@ lua_number2int is a macro to convert lua_Number to int.\n+@@ lua_number2integer is a macro to convert lua_Number to lua_Integer.\n+** CHANGE them if you know a faster way to convert a lua_Number to\n+** int (with any rounding method and without throwing errors) in your\n+** system. In Pentium machines, a naive typecast from double to int\n+** in C is extremely slow, so any alternative is worth trying.\n+*/\n+\n+/* On a Pentium, resort to a trick */\n+#if defined(LNUM_DOUBLE) && !defined(LUA_ANSI) && !defined(__SSE2__) && \\\n+    (defined(__i386) || defined (_M_IX86) || defined(__i386__))\n+\n+/* On a Microsoft compiler, use assembler */\n+# if defined(_MSC_VER)\n+#  define lua_number2int(i,d)   __asm fld d   __asm fistp i\n+# else\n+\n+/* the next trick should work on any Pentium, but sometimes clashes\n+   with a DirectX idiosyncrasy */\n+union luai_Cast { double l_d; long l_l; };\n+#  define lua_number2int(i,d) \\\n+  { volatile union luai_Cast u; u.l_d = (d) + 6755399441055744.0; (i) = u.l_l; }\n+# endif\n+\n+# ifndef LNUM_INT64\n+#  define lua_number2integer    lua_number2int\n+# endif\n+\n+/* this option always works, but may be slow */\n+#else\n+# define lua_number2int(i,d)        ((i)=(int)(d))\n+#endif\n+\n+/* Note: Some compilers (OS X gcc 4.0?) may choke on double->long long conversion \n+ *       since it can lose precision. Others do require 'long long' there.  \n+ */\n+#ifndef lua_number2integer\n+# define lua_number2integer(i,d)    ((i)=(lua_Integer)(d))\n+#endif\n+\n+/*\n+** 'luai_abs()' to give absolute value of 'lua_Integer'\n+*/\n+#ifdef LNUM_INT32\n+# define luai_abs abs\n+#elif defined(LNUM_INT64) && (__STDC_VERSION__ >= 199901L)\n+# define luai_abs llabs\n+#else\n+# define luai_abs(v) ((v) >= 0 ? (v) : -(v))\n+#endif\n+\n+/*\n+** LUAI_UACNUMBER is the result of an 'usual argument conversion' over a number.\n+** LUAI_UACINTEGER the same, over an integer.\n+*/\n+#define LUAI_UACNUMBER\tdouble\n+#define LUAI_UACINTEGER long\n+\n+/* ANSI C only has math funcs for 'double. C99 required for float and long double\n+ * variants.\n+ */\n+#ifdef LNUM_DOUBLE\n+# define _LF(name) name\n+#elif defined(LNUM_FLOAT)\n+# define _LF(name) name ## f\n+#elif defined(LNUM_LDOUBLE)\n+# define _LF(name) name ## l\n+#endif\n+\n+#endif\n+\n--- a/src/lobject.c\n+++ b/src/lobject.c\n@@ -21,7 +21,8 @@\n #include \"lstate.h\"\n #include \"lstring.h\"\n #include \"lvm.h\"\n-\n+#include \"llex.h\"\n+#include \"lnum.h\"\n \n \n const TValue luaO_nilobject_ = {{NULL}, LUA_TNIL};\n@@ -70,12 +71,31 @@ int luaO_log2 (unsigned int x) {\n \n \n int luaO_rawequalObj (const TValue *t1, const TValue *t2) {\n-  if (ttype(t1) != ttype(t2)) return 0;\n+  if (!ttype_ext_same(t1,t2)) return 0;\n   else switch (ttype(t1)) {\n     case LUA_TNIL:\n       return 1;\n+    case LUA_TINT:\n+      if (ttype(t2)==LUA_TINT)\n+        return ivalue(t1) == ivalue(t2);\n+      else {  /* t1:int, t2:num */\n+#ifdef LNUM_COMPLEX\n+        if (nvalue_img_fast(t2) != 0) return 0;\n+#endif\n+        /* Avoid doing accuracy losing cast, if possible. */\n+        lua_Integer tmp;\n+        if (tt_integer_valued(t2,&tmp)) \n+          return ivalue(t1) == tmp;\n+        else\n+          return luai_numeq( cast_num(ivalue(t1)), nvalue_fast(t2) );\n+        }\n     case LUA_TNUMBER:\n-      return luai_numeq(nvalue(t1), nvalue(t2));\n+        if (ttype(t2)==LUA_TINT)\n+          return luaO_rawequalObj(t2, t1);  /* swap LUA_TINT to left */\n+#ifdef LNUM_COMPLEX\n+        if (!luai_numeq(nvalue_img_fast(t1), nvalue_img_fast(t2))) return 0;\n+#endif\n+        return luai_numeq(nvalue_fast(t1), nvalue_fast(t2));\n     case LUA_TBOOLEAN:\n       return bvalue(t1) == bvalue(t2);  /* boolean true must be 1 !! */\n     case LUA_TLIGHTUSERDATA:\n@@ -86,21 +106,6 @@ int luaO_rawequalObj (const TValue *t1,\n   }\n }\n \n-\n-int luaO_str2d (const char *s, lua_Number *result) {\n-  char *endptr;\n-  *result = lua_str2number(s, &endptr);\n-  if (endptr == s) return 0;  /* conversion failed */\n-  if (*endptr == 'x' || *endptr == 'X')  /* maybe an hexadecimal constant? */\n-    *result = cast_num(strtoul(s, &endptr, 16));\n-  if (*endptr == '\\0') return 1;  /* most common case */\n-  while (isspace(cast(unsigned char, *endptr))) endptr++;\n-  if (*endptr != '\\0') return 0;  /* invalid trailing characters? */\n-  return 1;\n-}\n-\n-\n-\n static void pushstr (lua_State *L, const char *str) {\n   setsvalue2s(L, L->top, luaS_new(L, str));\n   incr_top(L);\n@@ -131,7 +136,11 @@ const char *luaO_pushvfstring (lua_State\n         break;\n       }\n       case 'd': {\n-        setnvalue(L->top, cast_num(va_arg(argp, int)));\n+        /* This is tricky for 64-bit integers; maybe they even cannot be\n+         * supported on all compilers; depends on the conversions applied to\n+         * variable argument lists. TBD: test!\n+         */\n+        setivalue(L->top, (lua_Integer) va_arg(argp, l_uacInteger));\n         incr_top(L);\n         break;\n       }\n@@ -212,3 +221,4 @@ void luaO_chunkid (char *out, const char\n     }\n   }\n }\n+\n--- a/src/lobject.h\n+++ b/src/lobject.h\n@@ -17,7 +17,11 @@\n \n \n /* tags for values visible from Lua */\n-#define LAST_TAG\tLUA_TTHREAD\n+#if LUA_TINT > LUA_TTHREAD\n+# define LAST_TAG   LUA_TINT\n+#else\n+# define LAST_TAG\tLUA_TTHREAD\n+#endif\n \n #define NUM_TAGS\t(LAST_TAG+1)\n \n@@ -59,7 +63,12 @@ typedef struct GCheader {\n typedef union {\n   GCObject *gc;\n   void *p;\n+#ifdef LNUM_COMPLEX\n+  lua_Complex n;\n+#else\n   lua_Number n;\n+#endif\n+  lua_Integer i;\n   int b;\n } Value;\n \n@@ -77,7 +86,11 @@ typedef struct lua_TValue {\n \n /* Macros to test type */\n #define ttisnil(o)\t(ttype(o) == LUA_TNIL)\n-#define ttisnumber(o)\t(ttype(o) == LUA_TNUMBER)\n+#define ttisint(o) (ttype(o) == LUA_TINT)\n+#define ttisnumber(o) ((ttype(o) == LUA_TINT) || (ttype(o) == LUA_TNUMBER))\n+#ifdef LNUM_COMPLEX\n+# define ttiscomplex(o) ((ttype(o) == LUA_TNUMBER) && (nvalue_img_fast(o)!=0))\n+#endif\n #define ttisstring(o)\t(ttype(o) == LUA_TSTRING)\n #define ttistable(o)\t(ttype(o) == LUA_TTABLE)\n #define ttisfunction(o)\t(ttype(o) == LUA_TFUNCTION)\n@@ -90,7 +103,25 @@ typedef struct lua_TValue {\n #define ttype(o)\t((o)->tt)\n #define gcvalue(o)\tcheck_exp(iscollectable(o), (o)->value.gc)\n #define pvalue(o)\tcheck_exp(ttislightuserdata(o), (o)->value.p)\n-#define nvalue(o)\tcheck_exp(ttisnumber(o), (o)->value.n)\n+\n+#define ttype_ext(o) ( ttype(o) == LUA_TINT ? LUA_TNUMBER : ttype(o) )\n+#define ttype_ext_same(o1,o2) ( (ttype(o1)==ttype(o2)) || (ttisnumber(o1) && ttisnumber(o2)) )\n+\n+/* '_fast' variants are for cases where 'ttype(o)' is known to be LUA_TNUMBER.\n+ */\n+#ifdef LNUM_COMPLEX\n+#  define nvalue_complex_fast(o) check_exp( ttype(o)==LUA_TNUMBER, (o)->value.n )   \n+#  define nvalue_fast(o)     ( _LF(creal) ( nvalue_complex_fast(o) ) )\n+#  define nvalue_img_fast(o) ( _LF(cimag) ( nvalue_complex_fast(o) ) )\n+#  define nvalue_complex(o) check_exp( ttisnumber(o), (ttype(o)==LUA_TINT) ? (o)->value.i : (o)->value.n )\n+#  define nvalue_img(o) check_exp( ttisnumber(o), (ttype(o)==LUA_TINT) ? 0 : _LF(cimag)( (o)->value.n ) ) \n+#  define nvalue(o) check_exp( ttisnumber(o), (ttype(o)==LUA_TINT) ? cast_num((o)->value.i) : _LF(creal)((o)->value.n) ) \n+#else\n+# define nvalue(o)\tcheck_exp( ttisnumber(o), (ttype(o)==LUA_TINT) ? cast_num((o)->value.i) : (o)->value.n )\n+# define nvalue_fast(o) check_exp( ttype(o)==LUA_TNUMBER, (o)->value.n )   \n+#endif\n+#define ivalue(o)\tcheck_exp( ttype(o)==LUA_TINT, (o)->value.i )\n+\n #define rawtsvalue(o)\tcheck_exp(ttisstring(o), &(o)->value.gc->ts)\n #define tsvalue(o)\t(&rawtsvalue(o)->tsv)\n #define rawuvalue(o)\tcheck_exp(ttisuserdata(o), &(o)->value.gc->u)\n@@ -116,8 +147,27 @@ typedef struct lua_TValue {\n /* Macros to set values */\n #define setnilvalue(obj) ((obj)->tt=LUA_TNIL)\n \n-#define setnvalue(obj,x) \\\n-  { TValue *i_o=(obj); i_o->value.n=(x); i_o->tt=LUA_TNUMBER; }\n+/* Must not have side effects, 'x' may be expression.\n+*/\n+#define setivalue(obj,x) \\\n+    { TValue *i_o=(obj); i_o->value.i=(x); i_o->tt=LUA_TINT; }\n+\n+# define setnvalue(obj,x) \\\n+    { TValue *i_o=(obj); i_o->value.n= (x); i_o->tt=LUA_TNUMBER; }\n+\n+/* Note: Complex always has \"inline\", both are C99.\n+*/\n+#ifdef LNUM_COMPLEX\n+  static inline void setnvalue_complex_fast( TValue *obj, lua_Complex x ) {\n+    lua_assert( _LF(cimag)(x) != 0 );\n+    obj->value.n= x; obj->tt= LUA_TNUMBER;\n+  }\n+  static inline void setnvalue_complex( TValue *obj, lua_Complex x ) {\n+    if (_LF(cimag)(x) == 0) { setnvalue(obj, _LF(creal)(x)); }\n+    else { obj->value.n= x; obj->tt= LUA_TNUMBER; }\n+  }\n+#endif\n+\n \n #define setpvalue(obj,x) \\\n   { TValue *i_o=(obj); i_o->value.p=(x); i_o->tt=LUA_TLIGHTUSERDATA; }\n@@ -155,9 +205,6 @@ typedef struct lua_TValue {\n     i_o->value.gc=cast(GCObject *, (x)); i_o->tt=LUA_TPROTO; \\\n     checkliveness(G(L),i_o); }\n \n-\n-\n-\n #define setobj(L,obj1,obj2) \\\n   { const TValue *o2=(obj2); TValue *o1=(obj1); \\\n     o1->value = o2->value; o1->tt=o2->tt; \\\n@@ -185,8 +232,11 @@ typedef struct lua_TValue {\n \n #define setttype(obj, tt) (ttype(obj) = (tt))\n \n-\n-#define iscollectable(o)\t(ttype(o) >= LUA_TSTRING)\n+#if LUA_TINT >= LUA_TSTRING\n+# define iscollectable(o)\t((ttype(o) >= LUA_TSTRING) && (ttype(o) != LUA_TINT))\n+#else\n+# define iscollectable(o)\t(ttype(o) >= LUA_TSTRING)\n+#endif\n \n \n \n@@ -370,12 +420,10 @@ LUAI_FUNC int luaO_log2 (unsigned int x)\n LUAI_FUNC int luaO_int2fb (unsigned int x);\n LUAI_FUNC int luaO_fb2int (int x);\n LUAI_FUNC int luaO_rawequalObj (const TValue *t1, const TValue *t2);\n-LUAI_FUNC int luaO_str2d (const char *s, lua_Number *result);\n LUAI_FUNC const char *luaO_pushvfstring (lua_State *L, const char *fmt,\n                                                        va_list argp);\n LUAI_FUNC const char *luaO_pushfstring (lua_State *L, const char *fmt, ...);\n LUAI_FUNC void luaO_chunkid (char *out, const char *source, size_t len);\n \n-\n #endif\n \n--- a/src/loslib.c\n+++ b/src/loslib.c\n@@ -186,15 +186,30 @@ static int os_time (lua_State *L) {\n   }\n   if (t == (time_t)(-1))\n     lua_pushnil(L);\n-  else\n-    lua_pushnumber(L, (lua_Number)t);\n+  else {\n+     /* On float systems the pushed value must be an integer, NOT a number.\n+      * Otherwise, accuracy is lost in the time_t->float conversion.\n+      */\n+#ifdef LNUM_FLOAT\n+     lua_pushinteger(L, (lua_Integer) t);\n+#else\n+     lua_pushnumber(L, (lua_Number) t);\n+#endif\n+     }\n   return 1;\n }\n \n \n static int os_difftime (lua_State *L) {\n+#ifdef LNUM_FLOAT\n+  lua_Integer i= (lua_Integer)\n+    difftime( (time_t)(luaL_checkinteger(L, 1)),\n+              (time_t)(luaL_optinteger(L, 2, 0)));\n+  lua_pushinteger(L, i);\n+#else\n   lua_pushnumber(L, difftime((time_t)(luaL_checknumber(L, 1)),\n                              (time_t)(luaL_optnumber(L, 2, 0))));\n+#endif\n   return 1;\n }\n \n--- a/src/lparser.c\n+++ b/src/lparser.c\n@@ -33,7 +33,6 @@\n \n #define luaY_checklimit(fs,v,l,m)\tif ((v)>(l)) errorlimit(fs,l,m)\n \n-\n /*\n ** nodes for block list (list of active blocks)\n */\n@@ -72,7 +71,7 @@ static void errorlimit (FuncState *fs, i\n   const char *msg = (fs->f->linedefined == 0) ?\n     luaO_pushfstring(fs->L, \"main function has more than %d %s\", limit, what) :\n     luaO_pushfstring(fs->L, \"function at line %d has more than %d %s\",\n-                            fs->f->linedefined, limit, what);\n+                            (fs->f->linedefined), limit, what);\n   luaX_lexerror(fs->ls, msg, 0);\n }\n \n@@ -733,6 +732,18 @@ static void simpleexp (LexState *ls, exp\n       v->u.nval = ls->t.seminfo.r;\n       break;\n     }\n+    case TK_INT: {\n+      init_exp(v, VKINT, 0);\n+      v->u.ival = ls->t.seminfo.i;\n+      break;\n+    }\n+#ifdef LNUM_COMPLEX\n+    case TK_NUMBER2: {\n+      init_exp(v, VKNUM2, 0);\n+      v->u.nval = ls->t.seminfo.r;\n+      break;\n+    }\n+#endif\n     case TK_STRING: {\n       codestring(ls, v, ls->t.seminfo.ts);\n       break;\n@@ -1079,7 +1090,7 @@ static void fornum (LexState *ls, TStrin\n   if (testnext(ls, ','))\n     exp1(ls);  /* optional step */\n   else {  /* default step = 1 */\n-    luaK_codeABx(fs, OP_LOADK, fs->freereg, luaK_numberK(fs, 1));\n+    luaK_codeABx(fs, OP_LOADK, fs->freereg, luaK_integerK(fs, 1));\n     luaK_reserveregs(fs, 1);\n   }\n   forbody(ls, base, line, 1, 1);\n--- a/src/lparser.h\n+++ b/src/lparser.h\n@@ -31,7 +31,11 @@ typedef enum {\n   VRELOCABLE,\t/* info = instruction pc */\n   VNONRELOC,\t/* info = result register */\n   VCALL,\t/* info = instruction pc */\n-  VVARARG\t/* info = instruction pc */\n+  VVARARG,\t/* info = instruction pc */\n+  VKINT     /* ival = integer value */\n+#ifdef LNUM_COMPLEX\n+  ,VKNUM2   /* nval = imaginary value */\n+#endif\n } expkind;\n \n typedef struct expdesc {\n@@ -39,6 +43,7 @@ typedef struct expdesc {\n   union {\n     struct { int info, aux; } s;\n     lua_Number nval;\n+    lua_Integer ival;\n   } u;\n   int t;  /* patch list of `exit when true' */\n   int f;  /* patch list of `exit when false' */\n--- a/src/lstrlib.c\n+++ b/src/lstrlib.c\n@@ -43,8 +43,8 @@ static ptrdiff_t posrelat (ptrdiff_t pos\n static int str_sub (lua_State *L) {\n   size_t l;\n   const char *s = luaL_checklstring(L, 1, &l);\n-  ptrdiff_t start = posrelat(luaL_checkinteger(L, 2), l);\n-  ptrdiff_t end = posrelat(luaL_optinteger(L, 3, -1), l);\n+  ptrdiff_t start = posrelat(luaL_checkint32(L, 2), l);\n+  ptrdiff_t end = posrelat(luaL_optint32(L, 3, -1), l);\n   if (start < 1) start = 1;\n   if (end > (ptrdiff_t)l) end = (ptrdiff_t)l;\n   if (start <= end)\n@@ -106,8 +106,8 @@ static int str_rep (lua_State *L) {\n static int str_byte (lua_State *L) {\n   size_t l;\n   const char *s = luaL_checklstring(L, 1, &l);\n-  ptrdiff_t posi = posrelat(luaL_optinteger(L, 2, 1), l);\n-  ptrdiff_t pose = posrelat(luaL_optinteger(L, 3, posi), l);\n+  ptrdiff_t posi = posrelat(luaL_optint32(L, 2, 1), l);\n+  ptrdiff_t pose = posrelat(luaL_optint32(L, 3, posi), l);\n   int n, i;\n   if (posi <= 0) posi = 1;\n   if ((size_t)pose > l) pose = l;\n@@ -496,7 +496,7 @@ static int str_find_aux (lua_State *L, i\n   size_t l1, l2;\n   const char *s = luaL_checklstring(L, 1, &l1);\n   const char *p = luaL_checklstring(L, 2, &l2);\n-  ptrdiff_t init = posrelat(luaL_optinteger(L, 3, 1), l1) - 1;\n+  ptrdiff_t init = posrelat(luaL_optint32(L, 3, 1), l1) - 1;\n   if (init < 0) init = 0;\n   else if ((size_t)(init) > l1) init = (ptrdiff_t)l1;\n   if (find && (lua_toboolean(L, 4) ||  /* explicit request? */\n@@ -690,7 +690,7 @@ static int str_gsub (lua_State *L) {\n ** maximum size of each format specification (such as '%-099.99d')\n ** (+10 accounts for %99.99x plus margin of error)\n */\n-#define MAX_FORMAT\t(sizeof(FLAGS) + sizeof(LUA_INTFRMLEN) + 10)\n+#define MAX_FORMAT\t(sizeof(FLAGS) + sizeof(LUA_INTEGER_FMT)-2 + 10)\n \n \n static void addquoted (lua_State *L, luaL_Buffer *b, int arg) {\n@@ -747,9 +747,9 @@ static const char *scanformat (lua_State\n static void addintlen (char *form) {\n   size_t l = strlen(form);\n   char spec = form[l - 1];\n-  strcpy(form + l - 1, LUA_INTFRMLEN);\n-  form[l + sizeof(LUA_INTFRMLEN) - 2] = spec;\n-  form[l + sizeof(LUA_INTFRMLEN) - 1] = '\\0';\n+  const char *tmp= LUA_INTEGER_FMT;   /* \"%lld\" or \"%ld\" */\n+  strcpy(form + l - 1, tmp+1);\n+  form[l + sizeof(LUA_INTEGER_FMT)-4] = spec;\n }\n \n \n@@ -779,12 +779,12 @@ static int str_format (lua_State *L) {\n         }\n         case 'd':  case 'i': {\n           addintlen(form);\n-          sprintf(buff, form, (LUA_INTFRM_T)luaL_checknumber(L, arg));\n+          sprintf(buff, form, luaL_checkinteger(L, arg));\n           break;\n         }\n         case 'o':  case 'u':  case 'x':  case 'X': {\n           addintlen(form);\n-          sprintf(buff, form, (unsigned LUA_INTFRM_T)luaL_checknumber(L, arg));\n+          sprintf(buff, form, (unsigned LUA_INTEGER)luaL_checkinteger(L, arg));\n           break;\n         }\n         case 'e':  case 'E': case 'f':\n--- a/src/ltable.c\n+++ b/src/ltable.c\n@@ -33,6 +33,7 @@\n #include \"lobject.h\"\n #include \"lstate.h\"\n #include \"ltable.h\"\n+#include \"lnum.h\"\n \n \n /*\n@@ -51,25 +52,15 @@\n   \n #define hashstr(t,str)  hashpow2(t, (str)->tsv.hash)\n #define hashboolean(t,p)        hashpow2(t, p)\n-\n+#define hashint(t,i)    hashpow2(t,i)\n \n /*\n ** for some types, it is better to avoid modulus by power of 2, as\n ** they tend to have many 2 factors.\n */\n #define hashmod(t,n)\t(gnode(t, ((n) % ((sizenode(t)-1)|1))))\n-\n-\n #define hashpointer(t,p)\thashmod(t, IntPoint(p))\n \n-\n-/*\n-** number of ints inside a lua_Number\n-*/\n-#define numints\t\tcast_int(sizeof(lua_Number)/sizeof(int))\n-\n-\n-\n #define dummynode\t\t(&dummynode_)\n \n static const Node dummynode_ = {\n@@ -80,27 +71,46 @@ static const Node dummynode_ = {\n \n /*\n ** hash for lua_Numbers\n+**\n+** for non-complex modes, never called with 'lua_Integer' value range (s.a. 0)\n */\n static Node *hashnum (const Table *t, lua_Number n) {\n-  unsigned int a[numints];\n-  int i;\n-  if (luai_numeq(n, 0))  /* avoid problems with -0 */\n-    return gnode(t, 0);\n-  memcpy(a, &n, sizeof(a));\n-  for (i = 1; i < numints; i++) a[0] += a[i];\n-  return hashmod(t, a[0]);\n+  const unsigned int *p= cast(const unsigned int *,&n);\n+  unsigned int sum= *p;\n+  unsigned int m= sizeof(lua_Number)/sizeof(int);\n+  unsigned int i;\n+  /* OS X Intel has 'm'==4 and gives \"Bus error\" if the last integer of \n+   * 'n' is read; the actual size of long double is only 80 bits = 10 bytes.\n+   * Linux x86 has 'm'==3, and does not require reduction.\n+   */\n+#if defined(LNUM_LDOUBLE) && defined(__i386__)\n+  if (m>3) m--;\n+#endif\n+  for (i = 1; i < m; i++) sum += p[i];\n+  return hashmod(t, sum);\n }\n \n \n-\n /*\n ** returns the `main' position of an element in a table (that is, the index\n ** of its hash value)\n+**\n+** Floating point numbers with integer value give the hash position of the\n+** integer (so they use the same table position).\n */\n static Node *mainposition (const Table *t, const TValue *key) {\n+  lua_Integer i;\n   switch (ttype(key)) {\n     case LUA_TNUMBER:\n-      return hashnum(t, nvalue(key));\n+      if (tt_integer_valued(key,&i)) \n+        return hashint(t, i);\n+#ifdef LNUM_COMPLEX\n+      if (nvalue_img_fast(key)!=0 && luai_numeq(nvalue_fast(key),0))\n+        return gnode(t, 0);  /* 0 and -0 to give same hash */\n+#endif\n+      return hashnum(t, nvalue_fast(key));\n+    case LUA_TINT:\n+      return hashint(t, ivalue(key));\n     case LUA_TSTRING:\n       return hashstr(t, rawtsvalue(key));\n     case LUA_TBOOLEAN:\n@@ -116,16 +126,20 @@ static Node *mainposition (const Table *\n /*\n ** returns the index for `key' if `key' is an appropriate key to live in\n ** the array part of the table, -1 otherwise.\n+**\n+** Anything <=0 is taken as not being in the array part.\n */\n-static int arrayindex (const TValue *key) {\n-  if (ttisnumber(key)) {\n-    lua_Number n = nvalue(key);\n-    int k;\n-    lua_number2int(k, n);\n-    if (luai_numeq(cast_num(k), n))\n-      return k;\n+static int arrayindex (const TValue *key, int max) {\n+  lua_Integer k;\n+  switch( ttype(key) ) {\n+    case LUA_TINT:\n+      k= ivalue(key); break;\n+    case LUA_TNUMBER:\n+      if (tt_integer_valued(key,&k)) break;\n+    default:\n+      return -1;  /* not to be used as array index */\n   }\n-  return -1;  /* `key' did not match some condition */\n+  return ((k>0) && (k <= max)) ? cast_int(k) : -1;\n }\n \n \n@@ -137,8 +151,8 @@ static int arrayindex (const TValue *key\n static int findindex (lua_State *L, Table *t, StkId key) {\n   int i;\n   if (ttisnil(key)) return -1;  /* first iteration */\n-  i = arrayindex(key);\n-  if (0 < i && i <= t->sizearray)  /* is `key' inside array part? */\n+  i = arrayindex(key, t->sizearray);\n+  if (i>0)  /* inside array part? */\n     return i-1;  /* yes; that's the index (corrected to C) */\n   else {\n     Node *n = mainposition(t, key);\n@@ -163,7 +177,7 @@ int luaH_next (lua_State *L, Table *t, S\n   int i = findindex(L, t, key);  /* find original element */\n   for (i++; i < t->sizearray; i++) {  /* try first array part */\n     if (!ttisnil(&t->array[i])) {  /* a non-nil value? */\n-      setnvalue(key, cast_num(i+1));\n+      setivalue(key, i+1);\n       setobj2s(L, key+1, &t->array[i]);\n       return 1;\n     }\n@@ -209,8 +223,8 @@ static int computesizes (int nums[], int\n \n \n static int countint (const TValue *key, int *nums) {\n-  int k = arrayindex(key);\n-  if (0 < k && k <= MAXASIZE) {  /* is `key' an appropriate array index? */\n+  int k = arrayindex(key,MAXASIZE);\n+  if (k>0) {  /* appropriate array index? */\n     nums[ceillog2(k)]++;  /* count as such */\n     return 1;\n   }\n@@ -308,7 +322,7 @@ static void resize (lua_State *L, Table\n     /* re-insert elements from vanishing slice */\n     for (i=nasize; i<oldasize; i++) {\n       if (!ttisnil(&t->array[i]))\n-        setobjt2t(L, luaH_setnum(L, t, i+1), &t->array[i]);\n+        setobjt2t(L, luaH_setint(L, t, i+1), &t->array[i]);\n     }\n     /* shrink array */\n     luaM_reallocvector(L, t->array, oldasize, nasize, TValue);\n@@ -409,7 +423,9 @@ static TValue *newkey (lua_State *L, Tab\n     othern = mainposition(t, key2tval(mp));\n     if (othern != mp) {  /* is colliding node out of its main position? */\n       /* yes; move colliding node into free position */\n-      while (gnext(othern) != mp) othern = gnext(othern);  /* find previous */\n+      while (gnext(othern) != mp) {\n+        othern = gnext(othern);  /* find previous */\n+      }\n       gnext(othern) = n;  /* redo the chain with `n' in place of `mp' */\n       *n = *mp;  /* copy colliding node into free pos. (mp->next also goes) */\n       gnext(mp) = NULL;  /* now `mp' is free */\n@@ -432,17 +448,18 @@ static TValue *newkey (lua_State *L, Tab\n /*\n ** search function for integers\n */\n-const TValue *luaH_getnum (Table *t, int key) {\n+const TValue *luaH_getint (Table *t, lua_Integer key) {\n   /* (1 <= key && key <= t->sizearray) */\n   if (cast(unsigned int, key-1) < cast(unsigned int, t->sizearray))\n     return &t->array[key-1];\n   else {\n-    lua_Number nk = cast_num(key);\n-    Node *n = hashnum(t, nk);\n+    Node *n = hashint(t, key);\n     do {  /* check whether `key' is somewhere in the chain */\n-      if (ttisnumber(gkey(n)) && luai_numeq(nvalue(gkey(n)), nk))\n+      if (ttisint(gkey(n)) && (ivalue(gkey(n)) == key)) {\n         return gval(n);  /* that's it */\n-      else n = gnext(n);\n+      } else { \n+      n = gnext(n);\n+    }\n     } while (n);\n     return luaO_nilobject;\n   }\n@@ -470,14 +487,12 @@ const TValue *luaH_get (Table *t, const\n   switch (ttype(key)) {\n     case LUA_TNIL: return luaO_nilobject;\n     case LUA_TSTRING: return luaH_getstr(t, rawtsvalue(key));\n+    case LUA_TINT: return luaH_getint(t, ivalue(key));\n     case LUA_TNUMBER: {\n-      int k;\n-      lua_Number n = nvalue(key);\n-      lua_number2int(k, n);\n-      if (luai_numeq(cast_num(k), nvalue(key))) /* index is int? */\n-        return luaH_getnum(t, k);  /* use specialized version */\n-      /* else go through */\n-    }\n+      lua_Integer i;\n+      if (tt_integer_valued(key,&i))\n+        return luaH_getint(t,i);\n+    } /* pass through */\n     default: {\n       Node *n = mainposition(t, key);\n       do {  /* check whether `key' is somewhere in the chain */\n@@ -498,20 +513,25 @@ TValue *luaH_set (lua_State *L, Table *t\n     return cast(TValue *, p);\n   else {\n     if (ttisnil(key)) luaG_runerror(L, \"table index is nil\");\n-    else if (ttisnumber(key) && luai_numisnan(nvalue(key)))\n-      luaG_runerror(L, \"table index is NaN\");\n+    else if (ttype(key)==LUA_TNUMBER) {\n+      lua_Integer k;\n+      if (luai_numisnan(nvalue_fast(key)))\n+        luaG_runerror(L, \"table index is NaN\");\n+      if (tt_integer_valued(key,&k))\n+        return luaH_setint(L, t, k);\n+    }\n     return newkey(L, t, key);\n   }\n }\n \n \n-TValue *luaH_setnum (lua_State *L, Table *t, int key) {\n-  const TValue *p = luaH_getnum(t, key);\n+TValue *luaH_setint (lua_State *L, Table *t, lua_Integer key) {\n+  const TValue *p = luaH_getint(t, key);\n   if (p != luaO_nilobject)\n     return cast(TValue *, p);\n   else {\n     TValue k;\n-    setnvalue(&k, cast_num(key));\n+    setivalue(&k, key);\n     return newkey(L, t, &k);\n   }\n }\n@@ -533,20 +553,21 @@ static int unbound_search (Table *t, uns\n   unsigned int i = j;  /* i is zero or a present index */\n   j++;\n   /* find `i' and `j' such that i is present and j is not */\n-  while (!ttisnil(luaH_getnum(t, j))) {\n+  while (!ttisnil(luaH_getint(t, j))) {\n     i = j;\n     j *= 2;\n     if (j > cast(unsigned int, MAX_INT)) {  /* overflow? */\n       /* table was built with bad purposes: resort to linear search */\n-      i = 1;\n-      while (!ttisnil(luaH_getnum(t, i))) i++;\n-      return i - 1;\n+      for( i = 1; i<MAX_INT+1; i++ ) {\n+        if (ttisnil(luaH_getint(t, i))) break;\n+      }\n+      return i - 1;  /* up to MAX_INT */\n     }\n   }\n   /* now do a binary search between them */\n   while (j - i > 1) {\n     unsigned int m = (i+j)/2;\n-    if (ttisnil(luaH_getnum(t, m))) j = m;\n+    if (ttisnil(luaH_getint(t, m))) j = m;\n     else i = m;\n   }\n   return i;\n--- a/src/ltable.h\n+++ b/src/ltable.h\n@@ -18,8 +18,8 @@\n #define key2tval(n)\t(&(n)->i_key.tvk)\n \n \n-LUAI_FUNC const TValue *luaH_getnum (Table *t, int key);\n-LUAI_FUNC TValue *luaH_setnum (lua_State *L, Table *t, int key);\n+LUAI_FUNC const TValue *luaH_getint (Table *t, lua_Integer key);\n+LUAI_FUNC TValue *luaH_setint (lua_State *L, Table *t, lua_Integer key);\n LUAI_FUNC const TValue *luaH_getstr (Table *t, TString *key);\n LUAI_FUNC TValue *luaH_setstr (lua_State *L, Table *t, TString *key);\n LUAI_FUNC const TValue *luaH_get (Table *t, const TValue *key);\n--- a/src/ltm.c\n+++ b/src/ltm.c\n@@ -19,7 +19,6 @@\n #include \"ltm.h\"\n \n \n-\n const char *const luaT_typenames[] = {\n   \"nil\", \"boolean\", \"userdata\", \"number\",\n   \"string\", \"table\", \"function\", \"userdata\", \"thread\",\n@@ -67,6 +66,9 @@ const TValue *luaT_gettmbyobj (lua_State\n     case LUA_TUSERDATA:\n       mt = uvalue(o)->metatable;\n       break;\n+    case LUA_TINT:\n+      mt = G(L)->mt[LUA_TNUMBER];\n+      break;\n     default:\n       mt = G(L)->mt[ttype(o)];\n   }\n--- a/src/lua.c\n+++ b/src/lua.c\n@@ -16,7 +16,7 @@\n \n #include \"lauxlib.h\"\n #include \"lualib.h\"\n-\n+#include \"llimits.h\"\n \n \n static lua_State *globalL = NULL;\n@@ -382,6 +382,15 @@ int main (int argc, char **argv) {\n     l_message(argv[0], \"cannot create state: not enough memory\");\n     return EXIT_FAILURE;\n   }\n+  /* Checking 'sizeof(lua_Integer)' cannot be made in preprocessor on all compilers.\n+  */\n+#ifdef LNUM_INT16\n+  lua_assert( sizeof(lua_Integer) == 2 );\n+#elif defined(LNUM_INT32)\n+  lua_assert( sizeof(lua_Integer) == 4 );\n+#elif defined(LNUM_INT64)\n+  lua_assert( sizeof(lua_Integer) == 8 );\n+#endif\n   s.argc = argc;\n   s.argv = argv;\n   status = lua_cpcall(L, &pmain, &s);\n--- a/src/lua.h\n+++ b/src/lua.h\n@@ -19,7 +19,7 @@\n #define LUA_VERSION\t\"Lua 5.1\"\n #define LUA_RELEASE\t\"Lua 5.1.5\"\n #define LUA_VERSION_NUM\t501\n-#define LUA_COPYRIGHT\t\"Copyright (C) 1994-2012 Lua.org, PUC-Rio\"\n+#define LUA_COPYRIGHT\t\"Copyright (C) 1994-2012 Lua.org, PUC-Rio\" \" (\" LUA_LNUM \")\"\n #define LUA_AUTHORS \t\"R. Ierusalimschy, L. H. de Figueiredo & W. Celes\"\n \n \n@@ -71,6 +71,16 @@ typedef void * (*lua_Alloc) (void *ud, v\n */\n #define LUA_TNONE\t\t(-1)\n \n+/* LUA_TINT is an internal type, not visible to applications. There are three\n+ * potential values where it can be tweaked to (code autoadjusts to these):\n+ *\n+ * -2: not 'usual' type value; good since 'LUA_TINT' is not part of the API\n+ * LUA_TNUMBER+1: shifts other type values upwards, breaking binary compatibility\n+ *     not acceptable for 5.1, maybe 5.2 onwards?\n+ *  9: greater than existing (5.1) type values.\n+*/\n+#define LUA_TINT (-2)\n+\n #define LUA_TNIL\t\t0\n #define LUA_TBOOLEAN\t\t1\n #define LUA_TLIGHTUSERDATA\t2\n@@ -139,6 +149,8 @@ LUA_API int             (lua_isuserdata)\n LUA_API int             (lua_type) (lua_State *L, int idx);\n LUA_API const char     *(lua_typename) (lua_State *L, int tp);\n \n+LUA_API int             (lua_isinteger) (lua_State *L, int idx);\n+\n LUA_API int            (lua_equal) (lua_State *L, int idx1, int idx2);\n LUA_API int            (lua_rawequal) (lua_State *L, int idx1, int idx2);\n LUA_API int            (lua_lessthan) (lua_State *L, int idx1, int idx2);\n@@ -244,6 +256,19 @@ LUA_API lua_Alloc (lua_getallocf) (lua_S\n LUA_API void lua_setallocf (lua_State *L, lua_Alloc f, void *ud);\n \n \n+/*\n+* It is unnecessary to break Lua C API 'lua_tonumber()' compatibility, just\n+* because the Lua number type is complex. Most C modules would use scalars\n+* only. We'll introduce new 'lua_tocomplex' and 'lua_pushcomplex' for when\n+* the module really wants to use them.\n+*/\n+#ifdef LNUM_COMPLEX\n+  #include <complex.h>\n+  typedef LUA_NUMBER complex lua_Complex;\n+  LUA_API lua_Complex (lua_tocomplex) (lua_State *L, int idx);\n+  LUA_API void (lua_pushcomplex) (lua_State *L, lua_Complex v);\n+#endif\n+\n \n /* \n ** ===============================================================\n@@ -268,7 +293,12 @@ LUA_API void lua_setallocf (lua_State *L\n #define lua_isboolean(L,n)\t(lua_type(L, (n)) == LUA_TBOOLEAN)\n #define lua_isthread(L,n)\t(lua_type(L, (n)) == LUA_TTHREAD)\n #define lua_isnone(L,n)\t\t(lua_type(L, (n)) == LUA_TNONE)\n-#define lua_isnoneornil(L, n)\t(lua_type(L, (n)) <= 0)\n+\n+#if LUA_TINT < 0\n+# define lua_isnoneornil(L, n)\t( (lua_type(L,(n)) <= 0) && (lua_type(L,(n)) != LUA_TINT) )\n+#else\n+# define lua_isnoneornil(L, n)\t(lua_type(L, (n)) <= 0)\n+#endif\n \n #define lua_pushliteral(L, s)\t\\\n \tlua_pushlstring(L, \"\" s, (sizeof(s)/sizeof(char))-1)\n@@ -386,3 +416,4 @@ struct lua_Debug {\n \n \n #endif\n+\n--- a/src/luaconf.h\n+++ b/src/luaconf.h\n@@ -10,7 +10,9 @@\n \n #include <limits.h>\n #include <stddef.h>\n-\n+#ifdef lua_assert\n+# include <assert.h>\n+#endif\n \n /*\n ** ==================================================================\n@@ -136,14 +138,38 @@\n \n \n /*\n-@@ LUA_INTEGER is the integral type used by lua_pushinteger/lua_tointeger.\n-** CHANGE that if ptrdiff_t is not adequate on your machine. (On most\n-** machines, ptrdiff_t gives a good choice between int or long.)\n+@@ LUAI_BITSINT defines the number of bits in an int.\n+** CHANGE here if Lua cannot automatically detect the number of bits of\n+** your machine. Probably you do not need to change this.\n */\n-#define LUA_INTEGER\tptrdiff_t\n+/* avoid overflows in comparison */\n+#if INT_MAX-20 < 32760\n+#define LUAI_BITSINT\t16\n+#elif INT_MAX > 2147483640L\n+/* int has at least 32 bits */\n+#define LUAI_BITSINT\t32\n+#else\n+#error \"you must define LUA_BITSINT with number of bits in an integer\"\n+#endif\n \n \n /*\n+@@ LNUM_DOUBLE | LNUM_FLOAT | LNUM_LDOUBLE: Generic Lua number mode\n+@@ LNUM_INT32 | LNUM_INT64: Integer type\n+@@ LNUM_COMPLEX: Define for using 'a+bi' numbers\n+@@\n+@@ You can combine LNUM_xxx but only one of each group. I.e. '-DLNUM_FLOAT\n+@@ -DLNUM_INT32 -DLNUM_COMPLEX' gives float range complex numbers, with \n+@@ 32-bit scalar integer range optimized.\n+**\n+** These are kept in a separate configuration file mainly for ease of patching\n+** (can be changed if integerated to Lua proper).\n+*/\n+/*#define LNUM_DOUBLE*/\n+/*#define LNUM_INT32*/\n+#include \"lnum_config.h\"\n+\n+/*\n @@ LUA_API is a mark for all core API functions.\n @@ LUALIB_API is a mark for all standard library functions.\n ** CHANGE them if you need to define those functions in some special way.\n@@ -383,22 +409,6 @@\n \n \n /*\n-@@ LUAI_BITSINT defines the number of bits in an int.\n-** CHANGE here if Lua cannot automatically detect the number of bits of\n-** your machine. Probably you do not need to change this.\n-*/\n-/* avoid overflows in comparison */\n-#if INT_MAX-20 < 32760\n-#define LUAI_BITSINT\t16\n-#elif INT_MAX > 2147483640L\n-/* int has at least 32 bits */\n-#define LUAI_BITSINT\t32\n-#else\n-#error \"you must define LUA_BITSINT with number of bits in an integer\"\n-#endif\n-\n-\n-/*\n @@ LUAI_UINT32 is an unsigned integer with at least 32 bits.\n @@ LUAI_INT32 is an signed integer with at least 32 bits.\n @@ LUAI_UMEM is an unsigned integer big enough to count the total\n@@ -425,6 +435,15 @@\n #define LUAI_MEM\tlong\n #endif\n \n+/*\n+@@ LUAI_BOOL carries 0 and nonzero (normally 1). It may be defined as 'char'\n+** (to save memory), 'int' (for speed), 'bool' (for C++) or '_Bool' (C99)\n+*/\n+#ifdef __cplusplus\n+# define LUAI_BOOL bool\n+#else\n+# define LUAI_BOOL int\n+#endif\n \n /*\n @@ LUAI_MAXCALLS limits the number of nested calls.\n@@ -490,101 +509,6 @@\n /* }================================================================== */\n \n \n-\n-\n-/*\n-** {==================================================================\n-@@ LUA_NUMBER is the type of numbers in Lua.\n-** CHANGE the following definitions only if you want to build Lua\n-** with a number type different from double. You may also need to\n-** change lua_number2int & lua_number2integer.\n-** ===================================================================\n-*/\n-\n-#define LUA_NUMBER_DOUBLE\n-#define LUA_NUMBER\tdouble\n-\n-/*\n-@@ LUAI_UACNUMBER is the result of an 'usual argument conversion'\n-@* over a number.\n-*/\n-#define LUAI_UACNUMBER\tdouble\n-\n-\n-/*\n-@@ LUA_NUMBER_SCAN is the format for reading numbers.\n-@@ LUA_NUMBER_FMT is the format for writing numbers.\n-@@ lua_number2str converts a number to a string.\n-@@ LUAI_MAXNUMBER2STR is maximum size of previous conversion.\n-@@ lua_str2number converts a string to a number.\n-*/\n-#define LUA_NUMBER_SCAN\t\t\"%lf\"\n-#define LUA_NUMBER_FMT\t\t\"%.14g\"\n-#define lua_number2str(s,n)\tsprintf((s), LUA_NUMBER_FMT, (n))\n-#define LUAI_MAXNUMBER2STR\t32 /* 16 digits, sign, point, and \\0 */\n-#define lua_str2number(s,p)\tstrtod((s), (p))\n-\n-\n-/*\n-@@ The luai_num* macros define the primitive operations over numbers.\n-*/\n-#if defined(LUA_CORE)\n-#include <math.h>\n-#define luai_numadd(a,b)\t((a)+(b))\n-#define luai_numsub(a,b)\t((a)-(b))\n-#define luai_nummul(a,b)\t((a)*(b))\n-#define luai_numdiv(a,b)\t((a)/(b))\n-#define luai_nummod(a,b)\t((a) - floor((a)/(b))*(b))\n-#define luai_numpow(a,b)\t(pow(a,b))\n-#define luai_numunm(a)\t\t(-(a))\n-#define luai_numeq(a,b)\t\t((a)==(b))\n-#define luai_numlt(a,b)\t\t((a)<(b))\n-#define luai_numle(a,b)\t\t((a)<=(b))\n-#define luai_numisnan(a)\t(!luai_numeq((a), (a)))\n-#endif\n-\n-\n-/*\n-@@ lua_number2int is a macro to convert lua_Number to int.\n-@@ lua_number2integer is a macro to convert lua_Number to lua_Integer.\n-** CHANGE them if you know a faster way to convert a lua_Number to\n-** int (with any rounding method and without throwing errors) in your\n-** system. In Pentium machines, a naive typecast from double to int\n-** in C is extremely slow, so any alternative is worth trying.\n-*/\n-\n-/* On a Pentium, resort to a trick */\n-#if defined(LUA_NUMBER_DOUBLE) && !defined(LUA_ANSI) && !defined(__SSE2__) && \\\n-    (defined(__i386) || defined (_M_IX86) || defined(__i386__))\n-\n-/* On a Microsoft compiler, use assembler */\n-#if defined(_MSC_VER)\n-\n-#define lua_number2int(i,d)   __asm fld d   __asm fistp i\n-#define lua_number2integer(i,n)\t\tlua_number2int(i, n)\n-\n-/* the next trick should work on any Pentium, but sometimes clashes\n-   with a DirectX idiosyncrasy */\n-#else\n-\n-union luai_Cast { double l_d; long l_l; };\n-#define lua_number2int(i,d) \\\n-  { volatile union luai_Cast u; u.l_d = (d) + 6755399441055744.0; (i) = u.l_l; }\n-#define lua_number2integer(i,n)\t\tlua_number2int(i, n)\n-\n-#endif\n-\n-\n-/* this option always works, but may be slow */\n-#else\n-#define lua_number2int(i,d)\t((i)=(int)(d))\n-#define lua_number2integer(i,d)\t((i)=(lua_Integer)(d))\n-\n-#endif\n-\n-/* }================================================================== */\n-\n-\n /*\n @@ LUAI_USER_ALIGNMENT_T is a type that requires maximum alignment.\n ** CHANGE it if your system requires alignments larger than double. (For\n@@ -728,28 +652,6 @@ union luai_Cast { double l_d; long l_l;\n #define luai_userstateyield(L,n)\t((void)L)\n \n \n-/*\n-@@ LUA_INTFRMLEN is the length modifier for integer conversions\n-@* in 'string.format'.\n-@@ LUA_INTFRM_T is the integer type correspoding to the previous length\n-@* modifier.\n-** CHANGE them if your system supports long long or does not support long.\n-*/\n-\n-#if defined(LUA_USELONGLONG)\n-\n-#define LUA_INTFRMLEN\t\t\"ll\"\n-#define LUA_INTFRM_T\t\tlong long\n-\n-#else\n-\n-#define LUA_INTFRMLEN\t\t\"l\"\n-#define LUA_INTFRM_T\t\tlong\n-\n-#endif\n-\n-\n-\n /* =================================================================== */\n \n /*\n--- a/src/lundump.c\n+++ b/src/lundump.c\n@@ -73,6 +73,13 @@ static lua_Number LoadNumber(LoadState*\n  return x;\n }\n \n+static lua_Integer LoadInteger(LoadState* S)\n+{\n+ lua_Integer x;\n+ LoadVar(S,x);\n+ return x;\n+}\n+\n static TString* LoadString(LoadState* S)\n {\n  size_t size;\n@@ -119,6 +126,9 @@ static void LoadConstants(LoadState* S,\n    case LUA_TNUMBER:\n \tsetnvalue(o,LoadNumber(S));\n \tbreak;\n+   case LUA_TINT:   /* Integer type saved in bytecode (see lcode.c) */\n+\tsetivalue(o,LoadInteger(S));\n+\tbreak;\n    case LUA_TSTRING:\n \tsetsvalue2n(S->L,o,LoadString(S));\n \tbreak;\n@@ -223,5 +233,22 @@ void luaU_header (char* h)\n  *h++=(char)sizeof(size_t);\n  *h++=(char)sizeof(Instruction);\n  *h++=(char)sizeof(lua_Number);\n- *h++=(char)(((lua_Number)0.5)==0);\t\t/* is lua_Number integral? */\n+\n+ /* \n+  * Last byte of header (0/1 in unpatched Lua 5.1.3):\n+  *\n+  * 0: lua_Number is float or double, lua_Integer not used. (nonpatched only)\n+  * 1: lua_Number is integer (nonpatched only)\n+  *\n+  * +2: LNUM_INT16: sizeof(lua_Integer)\n+  * +4: LNUM_INT32: sizeof(lua_Integer)\n+  * +8: LNUM_INT64: sizeof(lua_Integer)\n+  *\n+  * +0x80: LNUM_COMPLEX\n+  */\n+ *h++ = (char)(sizeof(lua_Integer)\n+#ifdef LNUM_COMPLEX\n+    | 0x80\n+#endif\n+    );\n }\n--- a/src/lvm.c\n+++ b/src/lvm.c\n@@ -25,22 +25,35 @@\n #include \"ltable.h\"\n #include \"ltm.h\"\n #include \"lvm.h\"\n-\n-\n+#include \"llex.h\"\n+#include \"lnum.h\"\n \n /* limit for table tag-method chains (to avoid loops) */\n #define MAXTAGLOOP\t100\n \n \n-const TValue *luaV_tonumber (const TValue *obj, TValue *n) {\n-  lua_Number num;\n+/*\n+ * If 'obj' is a string, it is tried to be interpreted as a number.\n+ */\n+const TValue *luaV_tonumber ( const TValue *obj, TValue *n) {\n+  lua_Number d;\n+  lua_Integer i;\n+  \n   if (ttisnumber(obj)) return obj;\n-  if (ttisstring(obj) && luaO_str2d(svalue(obj), &num)) {\n-    setnvalue(n, num);\n-    return n;\n-  }\n-  else\n-    return NULL;\n+\n+  if (ttisstring(obj)) {\n+    switch( luaO_str2d( svalue(obj), &d, &i ) ) {\n+        case TK_INT:\n+            setivalue(n,i); return n;\n+        case TK_NUMBER: \n+            setnvalue(n,d); return n;\n+#ifdef LNUM_COMPLEX\n+        case TK_NUMBER2:    /* \"N.NNNi\", != 0 */\n+            setnvalue_complex_fast(n, d*I); return n;\n+#endif\n+        }\n+    }\n+  return NULL;\n }\n \n \n@@ -49,8 +62,7 @@ int luaV_tostring (lua_State *L, StkId o\n     return 0;\n   else {\n     char s[LUAI_MAXNUMBER2STR];\n-    lua_Number n = nvalue(obj);\n-    lua_number2str(s, n);\n+    luaO_num2buf(s,obj);\n     setsvalue2s(L, obj, luaS_new(L, s));\n     return 1;\n   }\n@@ -222,59 +234,127 @@ static int l_strcmp (const TString *ls,\n }\n \n \n+#ifdef LNUM_COMPLEX\n+void error_complex( lua_State *L, const TValue *l, const TValue *r )\n+{\n+  char buf1[ LUAI_MAXNUMBER2STR ];\n+  char buf2[ LUAI_MAXNUMBER2STR ];\n+  luaO_num2buf( buf1, l );\n+  luaO_num2buf( buf2, r );\n+  luaG_runerror( L, \"unable to compare: %s with %s\", buf1, buf2 );\n+  /* no return */\n+}\n+#endif\n+\n+\n int luaV_lessthan (lua_State *L, const TValue *l, const TValue *r) {\n   int res;\n-  if (ttype(l) != ttype(r))\n+  int tl,tr;\n+  lua_Integer tmp;\n+\n+  if (!ttype_ext_same(l,r))\n     return luaG_ordererror(L, l, r);\n-  else if (ttisnumber(l))\n-    return luai_numlt(nvalue(l), nvalue(r));\n-  else if (ttisstring(l))\n-    return l_strcmp(rawtsvalue(l), rawtsvalue(r)) < 0;\n-  else if ((res = call_orderTM(L, l, r, TM_LT)) != -1)\n+#ifdef LNUM_COMPLEX\n+  if ( (nvalue_img(l)!=0) || (nvalue_img(r)!=0) )\n+    error_complex( L, l, r );\n+#endif\n+  tl= ttype(l); tr= ttype(r);\n+  if (tl==tr) {  /* clear arithmetics */\n+    switch(tl) {\n+      case LUA_TINT:      return ivalue(l) < ivalue(r);\n+      case LUA_TNUMBER:   return luai_numlt(nvalue_fast(l), nvalue_fast(r));\n+      case LUA_TSTRING:   return l_strcmp(rawtsvalue(l), rawtsvalue(r)) < 0;\n+    }\n+  } else if (tl==LUA_TINT) {  /* l:int, r:num */\n+    /* Avoid accuracy losing casts: if 'r' is integer by value, do comparisons\n+     * in integer realm. Only otherwise cast 'l' to FP (which might change its\n+     * value).\n+     */\n+    if (tt_integer_valued(r,&tmp)) \n+        return ivalue(l) < tmp;\n+    else \n+        return luai_numlt( cast_num(ivalue(l)), nvalue_fast(r) );\n+\n+  } else if (tl==LUA_TNUMBER) {  /* l:num, r:int */\n+    if (tt_integer_valued(l,&tmp)) \n+        return tmp < ivalue(r);\n+    else\n+        return luai_numlt( nvalue_fast(l), cast_num(ivalue(r)) );\n+\n+  } else if ((res = call_orderTM(L, l, r, TM_LT)) != -1)\n     return res;\n+\n   return luaG_ordererror(L, l, r);\n }\n \n \n static int lessequal (lua_State *L, const TValue *l, const TValue *r) {\n   int res;\n-  if (ttype(l) != ttype(r))\n+  int tl, tr;\n+  lua_Integer tmp;\n+\n+  if (!ttype_ext_same(l,r))\n     return luaG_ordererror(L, l, r);\n-  else if (ttisnumber(l))\n-    return luai_numle(nvalue(l), nvalue(r));\n-  else if (ttisstring(l))\n-    return l_strcmp(rawtsvalue(l), rawtsvalue(r)) <= 0;\n-  else if ((res = call_orderTM(L, l, r, TM_LE)) != -1)  /* first try `le' */\n+#ifdef LNUM_COMPLEX\n+  if ( (nvalue_img(l)!=0) || (nvalue_img(r)!=0) )\n+    error_complex( L, l, r );\n+#endif\n+  tl= ttype(l); tr= ttype(r);\n+  if (tl==tr) {  /* clear arithmetics */\n+    switch(tl) {\n+      case LUA_TINT:      return ivalue(l) <= ivalue(r);\n+      case LUA_TNUMBER:   return luai_numle(nvalue_fast(l), nvalue_fast(r));\n+      case LUA_TSTRING:   return l_strcmp(rawtsvalue(l), rawtsvalue(r)) <= 0;\n+    }\n+  }\n+  if (tl==LUA_TINT) {  /* l:int, r:num */\n+    if (tt_integer_valued(r,&tmp)) \n+        return ivalue(l) <= tmp;\n+    else\n+        return luai_numle( cast_num(ivalue(l)), nvalue_fast(r) );\n+\n+  } else if (tl==LUA_TNUMBER) {  /* l:num, r:int */\n+    if (tt_integer_valued(l,&tmp)) \n+        return tmp <= ivalue(r);\n+    else\n+        return luai_numle( nvalue_fast(l), cast_num(ivalue(r)) );\n+\n+  } else if ((res = call_orderTM(L, l, r, TM_LE)) != -1)  /* first try `le' */\n     return res;\n   else if ((res = call_orderTM(L, r, l, TM_LT)) != -1)  /* else try `lt' */\n     return !res;\n+\n   return luaG_ordererror(L, l, r);\n }\n \n \n-int luaV_equalval (lua_State *L, const TValue *t1, const TValue *t2) {\n+/* Note: 'luaV_equalval()' and 'luaO_rawequalObj()' have largely overlapping\n+ *       implementation. LUA_TNIL..LUA_TLIGHTUSERDATA cases could be handled\n+ *       simply by the 'default' case here.\n+ */\n+int luaV_equalval (lua_State *L, const TValue *l, const TValue *r) {\n   const TValue *tm;\n-  lua_assert(ttype(t1) == ttype(t2));\n-  switch (ttype(t1)) {\n+  lua_assert(ttype_ext_same(l,r));\n+  switch (ttype(l)) {\n     case LUA_TNIL: return 1;\n-    case LUA_TNUMBER: return luai_numeq(nvalue(t1), nvalue(t2));\n-    case LUA_TBOOLEAN: return bvalue(t1) == bvalue(t2);  /* true must be 1 !! */\n-    case LUA_TLIGHTUSERDATA: return pvalue(t1) == pvalue(t2);\n+    case LUA_TINT:\n+    case LUA_TNUMBER: return luaO_rawequalObj(l,r);\n+    case LUA_TBOOLEAN: return bvalue(l) == bvalue(r);  /* true must be 1 !! */\n+    case LUA_TLIGHTUSERDATA: return pvalue(l) == pvalue(r);\n     case LUA_TUSERDATA: {\n-      if (uvalue(t1) == uvalue(t2)) return 1;\n-      tm = get_compTM(L, uvalue(t1)->metatable, uvalue(t2)->metatable,\n-                         TM_EQ);\n+      if (uvalue(l) == uvalue(r)) return 1;\n+      tm = get_compTM(L, uvalue(l)->metatable, uvalue(r)->metatable, TM_EQ);\n       break;  /* will try TM */\n     }\n     case LUA_TTABLE: {\n-      if (hvalue(t1) == hvalue(t2)) return 1;\n-      tm = get_compTM(L, hvalue(t1)->metatable, hvalue(t2)->metatable, TM_EQ);\n+      if (hvalue(l) == hvalue(r)) return 1;\n+      tm = get_compTM(L, hvalue(l)->metatable, hvalue(r)->metatable, TM_EQ);\n       break;  /* will try TM */\n     }\n-    default: return gcvalue(t1) == gcvalue(t2);\n+    default: return gcvalue(l) == gcvalue(r);\n   }\n   if (tm == NULL) return 0;  /* no TM? */\n-  callTMres(L, L->top, tm, t1, t2);  /* call TM */\n+  callTMres(L, L->top, tm, l, r);  /* call TM */\n   return !l_isfalse(L->top);\n }\n \n@@ -314,30 +394,6 @@ void luaV_concat (lua_State *L, int tota\n }\n \n \n-static void Arith (lua_State *L, StkId ra, const TValue *rb,\n-                   const TValue *rc, TMS op) {\n-  TValue tempb, tempc;\n-  const TValue *b, *c;\n-  if ((b = luaV_tonumber(rb, &tempb)) != NULL &&\n-      (c = luaV_tonumber(rc, &tempc)) != NULL) {\n-    lua_Number nb = nvalue(b), nc = nvalue(c);\n-    switch (op) {\n-      case TM_ADD: setnvalue(ra, luai_numadd(nb, nc)); break;\n-      case TM_SUB: setnvalue(ra, luai_numsub(nb, nc)); break;\n-      case TM_MUL: setnvalue(ra, luai_nummul(nb, nc)); break;\n-      case TM_DIV: setnvalue(ra, luai_numdiv(nb, nc)); break;\n-      case TM_MOD: setnvalue(ra, luai_nummod(nb, nc)); break;\n-      case TM_POW: setnvalue(ra, luai_numpow(nb, nc)); break;\n-      case TM_UNM: setnvalue(ra, luai_numunm(nb)); break;\n-      default: lua_assert(0); break;\n-    }\n-  }\n-  else if (!call_binTM(L, rb, rc, ra, op))\n-    luaG_aritherror(L, rb, rc);\n-}\n-\n-\n-\n /*\n ** some macros for common tasks in `luaV_execute'\n */\n@@ -361,17 +417,154 @@ static void Arith (lua_State *L, StkId r\n #define Protect(x)\t{ L->savedpc = pc; {x;}; base = L->base; }\n \n \n-#define arith_op(op,tm) { \\\n-        TValue *rb = RKB(i); \\\n-        TValue *rc = RKC(i); \\\n-        if (ttisnumber(rb) && ttisnumber(rc)) { \\\n-          lua_Number nb = nvalue(rb), nc = nvalue(rc); \\\n-          setnvalue(ra, op(nb, nc)); \\\n-        } \\\n-        else \\\n-          Protect(Arith(L, ra, rb, rc, tm)); \\\n+/* Note: if called for unary operations, 'rc'=='rb'.\n+ */\n+static void Arith (lua_State *L, StkId ra, const TValue *rb,\n+                   const TValue *rc, TMS op) {\n+  TValue tempb, tempc;\n+  const TValue *b, *c;\n+  lua_Number nb,nc;\n+\n+  if ((b = luaV_tonumber(rb, &tempb)) != NULL &&\n+      (c = luaV_tonumber(rc, &tempc)) != NULL) {\n+\n+    /* Keep integer arithmetics in the integer realm, if possible.\n+     */\n+    if (ttisint(b) && ttisint(c)) {\n+      lua_Integer ib = ivalue(b), ic = ivalue(c);\n+      lua_Integer *ri = &ra->value.i;\n+      ra->tt= LUA_TINT;  /* part of 'setivalue(ra)' */\n+      switch (op) {\n+        case TM_ADD: if (try_addint( ri, ib, ic)) return; break;\n+        case TM_SUB: if (try_subint( ri, ib, ic)) return; break;\n+        case TM_MUL: if (try_mulint( ri, ib, ic)) return; break;\n+        case TM_DIV: if (try_divint( ri, ib, ic)) return; break;\n+        case TM_MOD: if (try_modint( ri, ib, ic)) return; break;\n+        case TM_POW: if (try_powint( ri, ib, ic)) return; break;\n+        case TM_UNM: if (try_unmint( ri, ib)) return; break;\n+        default: lua_assert(0);\n       }\n+    }\n+    /* Fallback to floating point, when leaving range. */\n \n+#ifdef LNUM_COMPLEX\n+    if ((nvalue_img(b)!=0) || (nvalue_img(c)!=0)) {\n+      lua_Complex r;\n+      if (op==TM_UNM) {\n+        r= -nvalue_complex_fast(b);     /* never an integer (or scalar) */\n+        setnvalue_complex_fast( ra, r );\n+      } else {\n+        lua_Complex bb= nvalue_complex(b), cc= nvalue_complex(c);\n+        switch (op) {\n+          case TM_ADD: r= bb + cc; break;\n+          case TM_SUB: r= bb - cc; break;\n+          case TM_MUL: r= bb * cc; break;\n+          case TM_DIV: r= bb / cc; break;\n+          case TM_MOD: \n+            luaG_runerror(L, \"attempt to use %% on complex numbers\");  /* no return */\n+          case TM_POW: r= luai_vectpow( bb, cc ); break;\n+          default: lua_assert(0); r=0;\n+        }\n+        setnvalue_complex( ra, r );\n+      }\n+      return;\n+    }\n+#endif\n+    nb = nvalue(b); nc = nvalue(c);\n+    switch (op) {\n+      case TM_ADD: setnvalue(ra, luai_numadd(nb, nc)); return;\n+      case TM_SUB: setnvalue(ra, luai_numsub(nb, nc)); return;\n+      case TM_MUL: setnvalue(ra, luai_nummul(nb, nc)); return;\n+      case TM_DIV: setnvalue(ra, luai_numdiv(nb, nc)); return;\n+      case TM_MOD: setnvalue(ra, luai_nummod(nb, nc)); return;\n+      case TM_POW: setnvalue(ra, luai_numpow(nb, nc)); return;\n+      case TM_UNM: setnvalue(ra, luai_numunm(nb)); return;\n+      default: lua_assert(0);\n+    }\n+  }\n+  \n+  /* Either operand not a number */\n+  if (!call_binTM(L, rb, rc, ra, op))\n+    luaG_aritherror(L, rb, rc);\n+}\n+\n+/* Helper macro to sort arithmetic operations into four categories:\n+ *  TK_INT: integer - integer operands\n+ *  TK_NUMBER: number - number (non complex, either may be integer)\n+ *  TK_NUMBER2: complex numbers (at least the other)\n+ *  0: non-numeric (at least the other)\n+*/\n+#ifdef LNUM_COMPLEX\n+static inline int arith_mode( const TValue *rb, const TValue *rc ) {\n+  if (ttisint(rb) && ttisint(rc)) return TK_INT;\n+  if (ttiscomplex(rb) || ttiscomplex(rc)) return TK_NUMBER2;\n+  if (ttisnumber(rb) && ttisnumber(rc)) return TK_NUMBER;\n+  return 0;\n+}\n+#else\n+# define arith_mode(rb,rc) \\\n+    ( (ttisint(rb) && ttisint(rc)) ? TK_INT : \\\n+      (ttisnumber(rb) && ttisnumber(rc)) ? TK_NUMBER : 0 )\n+#endif\n+\n+/* arith_op macro for two operators:\n+ * automatically chooses, which function (number, integer, complex) to use\n+ */\n+#define ARITH_OP2_START( op_num, op_int ) \\\n+  int failed= 0; \\\n+  switch( arith_mode(rb,rc) ) { \\\n+    case TK_INT: \\\n+      if (op_int ( &(ra)->value.i, ivalue(rb), ivalue(rc) )) \\\n+        { ra->tt= LUA_TINT; break; } /* else flow through */ \\\n+    case TK_NUMBER: \\\n+      setnvalue(ra, op_num ( nvalue(rb), nvalue(rc) )); break;\n+\n+#define ARITH_OP2_END \\\n+    default: \\\n+      failed= 1; break; \\\n+  } if (!failed) continue;\n+\n+#define arith_op_continue_scalar( op_num, op_int ) \\\n+    ARITH_OP2_START( op_num, op_int ) \\\n+    ARITH_OP2_END\n+\n+#ifdef LNUM_COMPLEX\n+# define arith_op_continue( op_num, op_int, op_complex ) \\\n+    ARITH_OP2_START( op_num, op_int ) \\\n+      case TK_NUMBER2: \\\n+        setnvalue_complex( ra, op_complex ( nvalue_complex(rb), nvalue_complex(rc) ) ); break; \\\n+    ARITH_OP2_END\n+#else\n+# define arith_op_continue(op_num,op_int,_) arith_op_continue_scalar(op_num,op_int)\n+#endif\n+\n+/* arith_op macro for one operator:\n+ */\n+#define ARITH_OP1_START( op_num, op_int ) \\\n+  int failed= 0; \\\n+  switch( arith_mode(rb,rb) ) { \\\n+    case TK_INT: \\\n+      if (op_int ( &(ra)->value.i, ivalue(rb) )) \\\n+        { ra->tt= LUA_TINT; break; } /* else flow through */ \\\n+      case TK_NUMBER: \\\n+        setnvalue(ra, op_num (nvalue(rb))); break; \\\n+\n+#define ARITH_OP1_END \\\n+      default: \\\n+        failed= 1; break; \\\n+  } if (!failed) continue;\n+\n+#ifdef LNUM_COMPLEX\n+# define arith_op1_continue( op_num, op_int, op_complex ) \\\n+    ARITH_OP1_START( op_num, op_int ) \\\n+      case TK_NUMBER2: \\\n+        setnvalue_complex( ra, op_complex ( nvalue_complex_fast(rb) )); break; \\\n+    ARITH_OP1_END\n+#else\n+# define arith_op1_continue( op_num, op_int, _ ) \\\n+    ARITH_OP1_START( op_num, op_int ) \\\n+    ARITH_OP1_END\n+#endif\n \n \n void luaV_execute (lua_State *L, int nexeccalls) {\n@@ -472,38 +665,45 @@ void luaV_execute (lua_State *L, int nex\n         continue;\n       }\n       case OP_ADD: {\n-        arith_op(luai_numadd, TM_ADD);\n+        TValue *rb = RKB(i), *rc= RKC(i);\n+        arith_op_continue( luai_numadd, try_addint, luai_vectadd );\n+        Protect(Arith(L, ra, rb, rc, TM_ADD)); \\\n         continue;\n       }\n       case OP_SUB: {\n-        arith_op(luai_numsub, TM_SUB);\n+        TValue *rb = RKB(i), *rc= RKC(i);\n+        arith_op_continue( luai_numsub, try_subint, luai_vectsub );\n+        Protect(Arith(L, ra, rb, rc, TM_SUB));\n         continue;\n       }\n       case OP_MUL: {\n-        arith_op(luai_nummul, TM_MUL);\n+        TValue *rb = RKB(i), *rc= RKC(i);\n+        arith_op_continue(luai_nummul, try_mulint, luai_vectmul);\n+        Protect(Arith(L, ra, rb, rc, TM_MUL));\n         continue;\n       }\n       case OP_DIV: {\n-        arith_op(luai_numdiv, TM_DIV);\n+        TValue *rb = RKB(i), *rc= RKC(i);\n+        arith_op_continue(luai_numdiv, try_divint, luai_vectdiv);\n+        Protect(Arith(L, ra, rb, rc, TM_DIV));\n         continue;\n       }\n       case OP_MOD: {\n-        arith_op(luai_nummod, TM_MOD);\n+        TValue *rb = RKB(i), *rc= RKC(i);\n+        arith_op_continue_scalar(luai_nummod, try_modint);  /* scalars only */\n+        Protect(Arith(L, ra, rb, rc, TM_MOD));\n         continue;\n       }\n       case OP_POW: {\n-        arith_op(luai_numpow, TM_POW);\n+        TValue *rb = RKB(i), *rc= RKC(i);\n+        arith_op_continue(luai_numpow, try_powint, luai_vectpow);\n+        Protect(Arith(L, ra, rb, rc, TM_POW));\n         continue;\n       }\n       case OP_UNM: {\n         TValue *rb = RB(i);\n-        if (ttisnumber(rb)) {\n-          lua_Number nb = nvalue(rb);\n-          setnvalue(ra, luai_numunm(nb));\n-        }\n-        else {\n-          Protect(Arith(L, ra, rb, rb, TM_UNM));\n-        }\n+        arith_op1_continue(luai_numunm, try_unmint, luai_vectunm);\n+        Protect(Arith(L, ra, rb, rb, TM_UNM));\n         continue;\n       }\n       case OP_NOT: {\n@@ -515,11 +715,11 @@ void luaV_execute (lua_State *L, int nex\n         const TValue *rb = RB(i);\n         switch (ttype(rb)) {\n           case LUA_TTABLE: {\n-            setnvalue(ra, cast_num(luaH_getn(hvalue(rb))));\n+            setivalue(ra, luaH_getn(hvalue(rb)));\n             break;\n           }\n           case LUA_TSTRING: {\n-            setnvalue(ra, cast_num(tsvalue(rb)->len));\n+            setivalue(ra, tsvalue(rb)->len);\n             break;\n           }\n           default: {  /* try metamethod */\n@@ -652,14 +852,30 @@ void luaV_execute (lua_State *L, int nex\n         }\n       }\n       case OP_FORLOOP: {\n-        lua_Number step = nvalue(ra+2);\n-        lua_Number idx = luai_numadd(nvalue(ra), step); /* increment index */\n-        lua_Number limit = nvalue(ra+1);\n-        if (luai_numlt(0, step) ? luai_numle(idx, limit)\n-                                : luai_numle(limit, idx)) {\n-          dojump(L, pc, GETARG_sBx(i));  /* jump back */\n-          setnvalue(ra, idx);  /* update internal index... */\n-          setnvalue(ra+3, idx);  /* ...and external index */\n+        /* If start,step and limit are all integers, we don't need to check\n+         * against overflow in the looping.\n+         */\n+        if (ttisint(ra) && ttisint(ra+1) && ttisint(ra+2)) {\n+          lua_Integer step = ivalue(ra+2);\n+          lua_Integer idx = ivalue(ra) + step; /* increment index */\n+          lua_Integer limit = ivalue(ra+1);\n+          if (step > 0 ? (idx <= limit) : (limit <= idx)) {\n+            dojump(L, pc, GETARG_sBx(i));  /* jump back */\n+            setivalue(ra, idx);  /* update internal index... */\n+            setivalue(ra+3, idx);  /* ...and external index */\n+          }\n+        } else {\n+          /* non-integer looping (don't use 'nvalue_fast', some may be integer!) \n+          */\n+          lua_Number step = nvalue(ra+2);\n+          lua_Number idx = luai_numadd(nvalue(ra), step); /* increment index */\n+          lua_Number limit = nvalue(ra+1);\n+          if (luai_numlt(0, step) ? luai_numle(idx, limit)\n+                                  : luai_numle(limit, idx)) {\n+            dojump(L, pc, GETARG_sBx(i));  /* jump back */\n+            setnvalue(ra, idx);  /* update internal index... */\n+            setnvalue(ra+3, idx);  /* ...and external index */\n+          }\n         }\n         continue;\n       }\n@@ -668,13 +884,21 @@ void luaV_execute (lua_State *L, int nex\n         const TValue *plimit = ra+1;\n         const TValue *pstep = ra+2;\n         L->savedpc = pc;  /* next steps may throw errors */\n+        /* Using same location for tonumber's both arguments, effectively does\n+         * in-place modification (string->number). */\n         if (!tonumber(init, ra))\n           luaG_runerror(L, LUA_QL(\"for\") \" initial value must be a number\");\n         else if (!tonumber(plimit, ra+1))\n           luaG_runerror(L, LUA_QL(\"for\") \" limit must be a number\");\n         else if (!tonumber(pstep, ra+2))\n           luaG_runerror(L, LUA_QL(\"for\") \" step must be a number\");\n-        setnvalue(ra, luai_numsub(nvalue(ra), nvalue(pstep)));\n+        /* Step back one value (keep within integers if we can)\n+         */\n+        if (!( ttisint(ra) && ttisint(pstep) &&\n+               try_subint( &ra->value.i, ivalue(ra), ivalue(pstep) ) )) {\n+            /* don't use 'nvalue_fast()', values may be integer */\n+            setnvalue(ra, luai_numsub(nvalue(ra), nvalue(pstep)));\n+        }\n         dojump(L, pc, GETARG_sBx(i));\n         continue;\n       }\n@@ -711,7 +935,7 @@ void luaV_execute (lua_State *L, int nex\n           luaH_resizearray(L, h, last);  /* pre-alloc it at once */\n         for (; n > 0; n--) {\n           TValue *val = ra+n;\n-          setobj2t(L, luaH_setnum(L, h, last--), val);\n+          setobj2t(L, luaH_setint(L, h, last--), val);\n           luaC_barriert(L, h, val);\n         }\n         continue;\n--- a/src/lvm.h\n+++ b/src/lvm.h\n@@ -15,11 +15,9 @@\n \n #define tostring(L,o) ((ttype(o) == LUA_TSTRING) || (luaV_tostring(L, o)))\n \n-#define tonumber(o,n)\t(ttype(o) == LUA_TNUMBER || \\\n-                         (((o) = luaV_tonumber(o,n)) != NULL))\n+#define tonumber(o,n) (ttisnumber(o) || (((o) = luaV_tonumber(o,n)) != NULL))\n \n-#define equalobj(L,o1,o2) \\\n-\t(ttype(o1) == ttype(o2) && luaV_equalval(L, o1, o2))\n+#define equalobj(L,o1,o2) (ttype_ext_same(o1,o2) && luaV_equalval(L, o1, o2))\n \n \n LUAI_FUNC int luaV_lessthan (lua_State *L, const TValue *l, const TValue *r);\n--- a/src/print.c\n+++ b/src/print.c\n@@ -14,6 +14,7 @@\n #include \"lobject.h\"\n #include \"lopcodes.h\"\n #include \"lundump.h\"\n+#include \"lnum.h\"\n \n #define PrintFunction\tluaU_print\n \n@@ -59,8 +60,16 @@ static void PrintConstant(const Proto* f\n   case LUA_TBOOLEAN:\n \tprintf(bvalue(o) ? \"true\" : \"false\");\n \tbreak;\n+  case LUA_TINT:\n+\tprintf(LUA_INTEGER_FMT,ivalue(o));\n+\tbreak;\n   case LUA_TNUMBER:\n-\tprintf(LUA_NUMBER_FMT,nvalue(o));\n+#ifdef LNUM_COMPLEX\n+    // TBD: Do we get complex values here?\n+    { lua_Number b= nvalue_img_fast(o);\n+\t  printf( LUA_NUMBER_FMT \"%s\" LUA_NUMBER_FMT \"i\", nvalue_fast(o), b>=0 ? \"+\":\"\", b ); }\n+#endif\n+\tprintf(LUA_NUMBER_FMT,nvalue_fast(o));\n \tbreak;\n   case LUA_TSTRING:\n \tPrintString(rawtsvalue(o));\n"
  },
  {
    "path": "package/utils/lua/patches/011-lnum-use-double.patch",
    "content": "--- a/src/lnum_config.h\n+++ b/src/lnum_config.h\n@@ -11,7 +11,7 @@\n ** Default number modes\n */\n #if (!defined LNUM_DOUBLE) && (!defined LNUM_FLOAT) && (!defined LNUM_LDOUBLE)\n-# define LNUM_FLOAT\n+# define LNUM_DOUBLE\n #endif\n #if (!defined LNUM_INT16) && (!defined LNUM_INT32) && (!defined LNUM_INT64)\n # define LNUM_INT32\n"
  },
  {
    "path": "package/utils/lua/patches/012-lnum-fix-ltle-relational-operators.patch",
    "content": "--- a/src/lvm.c\n+++ b/src/lvm.c\n@@ -281,7 +281,8 @@ int luaV_lessthan (lua_State *L, const T\n     else\n         return luai_numlt( nvalue_fast(l), cast_num(ivalue(r)) );\n \n-  } else if ((res = call_orderTM(L, l, r, TM_LT)) != -1)\n+  } \n+  if ((res = call_orderTM(L, l, r, TM_LT)) != -1)\n     return res;\n \n   return luaG_ordererror(L, l, r);\n@@ -319,7 +320,8 @@ static int lessequal (lua_State *L, cons\n     else\n         return luai_numle( nvalue_fast(l), cast_num(ivalue(r)) );\n \n-  } else if ((res = call_orderTM(L, l, r, TM_LE)) != -1)  /* first try `le' */\n+  } \n+  if ((res = call_orderTM(L, l, r, TM_LE)) != -1)  /* first try `le' */\n     return res;\n   else if ((res = call_orderTM(L, r, l, TM_LT)) != -1)  /* else try `lt' */\n     return !res;\n"
  },
  {
    "path": "package/utils/lua/patches/013-lnum-strtoul-parsing-fixes.patch",
    "content": "diff --git a/src/lnum.c b/src/lnum.c\nindex 1456b6a2ed23..b0632b04c2b7 100644\n--- a/src/lnum.c\n+++ b/src/lnum.c\n@@ -127,6 +127,8 @@ static int luaO_str2i (const char *s, lua_Integer *res, char **endptr_ref) {\n #else\n       return 0;  /* Reject the number */\n #endif\n+    } else if (v > LUA_INTEGER_MAX) {\n+      return TK_NUMBER;\n     }\n   } else if ((v > LUA_INTEGER_MAX) || (*endptr && (!isspace(*endptr)))) {\n     return TK_NUMBER;\t/* not in signed range, or has '.', 'e' etc. trailing */\n@@ -310,3 +312,13 @@ int try_unmint( lua_Integer *r, lua_Integer ib ) {\n   return 0;\n }\n \n+#ifdef LONG_OVERFLOW_LUA_INTEGER\n+unsigned LUA_INTEGER lua_str2ul( const char *str, char **endptr, int base ) {\n+  unsigned long v= strtoul(str, endptr, base);\n+  if ( v > LUA_INTEGER_MAX ) {\n+    errno= ERANGE;\n+    v= ULONG_MAX;\n+  }\n+  return (unsigned LUA_INTEGER)v;\n+}\n+#endif\ndiff --git a/src/lnum_config.h b/src/lnum_config.h\nindex 19d7a4231a49..1092eead6629 100644\n--- a/src/lnum_config.h\n+++ b/src/lnum_config.h\n@@ -141,7 +141,12 @@\n #endif\n \n #ifndef lua_str2ul\n-# define lua_str2ul (unsigned LUA_INTEGER)strtoul\n+# if LONG_MAX > LUA_INTEGER_MAX\n+#   define LONG_OVERFLOW_LUA_INTEGER\n+    unsigned LUA_INTEGER lua_str2ul( const char *str, char **endptr, int base );\n+# else\n+#  define lua_str2ul (unsigned LUA_INTEGER)strtoul\n+# endif\n #endif\n #ifndef LUA_INTEGER_MIN\n # define LUA_INTEGER_MIN (-LUA_INTEGER_MAX -1)  /* -2^16|32 */\n-- \n1.9.1\n\n"
  },
  {
    "path": "package/utils/lua/patches/015-lnum-ppc-compat.patch",
    "content": "--- a/src/lua.h\n+++ b/src/lua.h\n@@ -79,7 +79,7 @@ typedef void * (*lua_Alloc) (void *ud, v\n  *     not acceptable for 5.1, maybe 5.2 onwards?\n  *  9: greater than existing (5.1) type values.\n */\n-#define LUA_TINT (-2)\n+#define LUA_TINT 9\n \n #define LUA_TNIL\t\t0\n #define LUA_TBOOLEAN\t\t1\n"
  },
  {
    "path": "package/utils/lua/patches/020-shared_liblua.patch",
    "content": "--- a/Makefile\n+++ b/Makefile\n@@ -42,8 +42,8 @@ PLATS= aix ansi bsd freebsd generic linu\n \n # What to install.\n TO_BIN= lua$V luac$V\n-TO_INC= lua.h luaconf.h lualib.h lauxlib.h ../etc/lua.hpp\n-TO_LIB= liblua.a\n+TO_INC= lua.h luaconf.h lualib.h lauxlib.h ../etc/lua.hpp lnum_config.h\n+TO_LIB= liblua.a liblua.so.$R\n TO_MAN= lua$V.1 luac$V.1\n \n # Lua version and release.\n@@ -63,6 +63,7 @@ install: dummy\n \tcd src && $(INSTALL_EXEC) $(TO_BIN) $(INSTALL_BIN)\n \tcd src && $(INSTALL_DATA) $(TO_INC) $(INSTALL_INC)\n \tcd src && $(INSTALL_DATA) $(TO_LIB) $(INSTALL_LIB)\n+\tln -s liblua.so.$R $(INSTALL_LIB)/liblua.so\n \tcd doc && $(INSTALL_DATA) $(TO_MAN) $(INSTALL_MAN)\n \n ranlib:\n--- a/src/ldo.h\n+++ b/src/ldo.h\n@@ -46,7 +46,7 @@ LUAI_FUNC int luaD_pcall (lua_State *L,\n LUAI_FUNC int luaD_poscall (lua_State *L, StkId firstResult);\n LUAI_FUNC void luaD_reallocCI (lua_State *L, int newsize);\n LUAI_FUNC void luaD_reallocstack (lua_State *L, int newsize);\n-LUAI_FUNC void luaD_growstack (lua_State *L, int n);\n+LUA_API void luaD_growstack (lua_State *L, int n);\n \n LUAI_FUNC void luaD_throw (lua_State *L, int errcode);\n LUAI_FUNC int luaD_rawrunprotected (lua_State *L, Pfunc f, void *ud);\n--- a/src/lfunc.h\n+++ b/src/lfunc.h\n@@ -18,7 +18,7 @@\n                          cast(int, sizeof(TValue *)*((n)-1)))\n \n \n-LUAI_FUNC Proto *luaF_newproto (lua_State *L);\n+LUA_API Proto *luaF_newproto (lua_State *L);\n LUAI_FUNC Closure *luaF_newCclosure (lua_State *L, int nelems, Table *e);\n LUAI_FUNC Closure *luaF_newLclosure (lua_State *L, int nelems, Table *e);\n LUAI_FUNC UpVal *luaF_newupval (lua_State *L);\n--- a/src/lmem.h\n+++ b/src/lmem.h\n@@ -38,9 +38,9 @@\n    ((v)=cast(t *, luaM_reallocv(L, v, oldn, n, sizeof(t))))\n \n \n-LUAI_FUNC void *luaM_realloc_ (lua_State *L, void *block, size_t oldsize,\n+LUA_API void *luaM_realloc_ (lua_State *L, void *block, size_t oldsize,\n                                                           size_t size);\n-LUAI_FUNC void *luaM_toobig (lua_State *L);\n+LUA_API void *luaM_toobig (lua_State *L);\n LUAI_FUNC void *luaM_growaux_ (lua_State *L, void *block, int *size,\n                                size_t size_elem, int limit,\n                                const char *errormsg);\n--- a/src/lstring.h\n+++ b/src/lstring.h\n@@ -25,7 +25,7 @@\n \n LUAI_FUNC void luaS_resize (lua_State *L, int newsize);\n LUAI_FUNC Udata *luaS_newudata (lua_State *L, size_t s, Table *e);\n-LUAI_FUNC TString *luaS_newlstr (lua_State *L, const char *str, size_t l);\n+LUA_API TString *luaS_newlstr (lua_State *L, const char *str, size_t l);\n \n \n #endif\n--- a/src/lundump.h\n+++ b/src/lundump.h\n@@ -17,7 +17,7 @@ LUAI_FUNC Proto* luaU_undump (lua_State*\n LUAI_FUNC void luaU_header (char* h);\n \n /* dump one chunk; from ldump.c */\n-LUAI_FUNC int luaU_dump (lua_State* L, const Proto* f, lua_Writer w, void* data, int strip);\n+LUA_API int luaU_dump (lua_State* L, const Proto* f, lua_Writer w, void* data, int strip);\n \n #ifdef luac_c\n /* print one chunk; from print.c */\n--- a/src/Makefile\n+++ b/src/Makefile\n@@ -23,6 +23,7 @@ MYLIBS=\n PLATS= aix ansi bsd freebsd generic linux macosx mingw posix solaris\n \n LUA_A=\tliblua.a\n+LUA_SO= liblua.so\n CORE_O=\tlapi.o lcode.o ldebug.o ldo.o ldump.o lfunc.o lgc.o llex.o lmem.o \\\n \tlobject.o lopcodes.o lparser.o lstate.o lstring.o ltable.o ltm.o  \\\n \tlundump.o lvm.o lzio.o lnum.o\n@@ -33,11 +34,12 @@ LUA_T=\tlua$V\n LUA_O=\tlua.o\n \n LUAC_T=\tluac$V\n-LUAC_O=\tluac.o print.o\n+LUAC_O=\tluac.o print.o lopcodes.o\n \n ALL_O= $(CORE_O) $(LIB_O) $(LUA_O) $(LUAC_O)\n-ALL_T= $(LUA_A) $(LUA_T) $(LUAC_T)\n+ALL_T= $(LUA_A) $(LUA_SO) $(LUA_T) $(LUAC_T)\n ALL_A= $(LUA_A)\n+ALL_SO= $(LUA_SO)\n \n default: $(PLAT)\n \n@@ -47,14 +49,23 @@ o:\t$(ALL_O)\n \n a:\t$(ALL_A)\n \n+so:\t$(ALL_SO)\n+\n $(LUA_A): $(CORE_O) $(LIB_O)\n \t$(AR) $@ $(CORE_O) $(LIB_O)\t# DLL needs all object files\n \t$(RANLIB) $@\n \n-$(LUA_T): $(LUA_O) $(LUA_A)\n-\t$(CC) -o $@ $(MYLDFLAGS) $(LUA_O) $(LUA_A) $(LIBS)\n+$(LUA_SO): $(CORE_O) $(LIB_O)\n+\t$(CC) -o $@.$(PKG_VERSION) -shared -Wl,-soname=\"$@.$(PKG_VERSION)\" $?\n+\tln -fs $@.$(PKG_VERSION) $@\n+\n+$(LUA_T): $(LUA_O) $(LUA_SO)\n+\t$(CC) -o $@ -L. -llua $(MYLDFLAGS) $(LUA_O) $(LIBS)\n+\n+$(LUAC_T): $(LUAC_O) $(LUA_SO)\n+\t$(CC) -o $@ -L. -llua $(MYLDFLAGS) $(LUAC_O) $(LIBS)\n \n-$(LUAC_T): $(LUAC_O) $(LUA_A)\n+$(LUAC_T)-host: $(LUAC_O) $(LUA_A)\n \t$(CC) -o $@ $(MYLDFLAGS) $(LUAC_O) $(LUA_A) $(LIBS)\n \n clean:\n@@ -96,7 +107,7 @@ generic:\n \t$(MAKE) all MYCFLAGS=\n \n linux:\n-\t$(MAKE) all MYCFLAGS=-DLUA_USE_LINUX MYLIBS=\"-Wl,-E -ldl -lreadline -lhistory -lncurses\"\n+\t$(MAKE) all MYCFLAGS+=-DLUA_USE_LINUX MYLIBS=\"-Wl,-E -ldl -lreadline -lhistory -lncurses\"\n \n macosx:\n \t$(MAKE) all MYCFLAGS=-DLUA_USE_LINUX MYLIBS=\"-lreadline\"\n"
  },
  {
    "path": "package/utils/lua/patches/030-archindependent-bytecode.patch",
    "content": "--- a/src/ldump.c\n+++ b/src/ldump.c\n@@ -67,12 +67,12 @@ static void DumpString(const TString* s,\n {\n  if (s==NULL || getstr(s)==NULL)\n  {\n-  size_t size=0;\n+  unsigned int size=0;\n   DumpVar(size,D);\n  }\n  else\n  {\n-  size_t size=s->tsv.len+1;\t\t/* include trailing '\\0' */\n+  unsigned int size=s->tsv.len+1;\t\t/* include trailing '\\0' */\n   DumpVar(size,D);\n   DumpBlock(getstr(s),size,D);\n  }\n--- a/src/lundump.c\n+++ b/src/lundump.c\n@@ -25,6 +25,7 @@ typedef struct {\n  ZIO* Z;\n  Mbuffer* b;\n  const char* name;\n+ int swap;\n } LoadState;\n \n #ifdef LUAC_TRUST_BINARIES\n@@ -40,7 +41,6 @@ static void error(LoadState* S, const ch\n }\n #endif\n \n-#define LoadMem(S,b,n,size)\tLoadBlock(S,b,(n)*(size))\n #define\tLoadByte(S)\t\t(lu_byte)LoadChar(S)\n #define LoadVar(S,x)\t\tLoadMem(S,&x,1,sizeof(x))\n #define LoadVector(S,b,n,size)\tLoadMem(S,b,n,size)\n@@ -51,6 +51,49 @@ static void LoadBlock(LoadState* S, void\n  IF (r!=0, \"unexpected end\");\n }\n \n+static void LoadMem (LoadState* S, void* b, int n, size_t size)\n+{\n+ LoadBlock(S,b,n*size);\n+ if (S->swap)\n+ {\n+  char* p=(char*) b;\n+  char c;\n+  switch (size)\n+  {\n+   case 1:\n+  \tbreak;\n+   case 2:\n+\twhile (n--)\n+\t{\n+\t c=p[0]; p[0]=p[1]; p[1]=c;\n+\t p+=2;\n+\t}\n+  \tbreak;\n+   case 4:\n+\twhile (n--)\n+\t{\n+\t c=p[0]; p[0]=p[3]; p[3]=c;\n+\t c=p[1]; p[1]=p[2]; p[2]=c;\n+\t p+=4;\n+\t}\n+  \tbreak;\n+   case 8:\n+\twhile (n--)\n+\t{\n+\t c=p[0]; p[0]=p[7]; p[7]=c;\n+\t c=p[1]; p[1]=p[6]; p[6]=c;\n+\t c=p[2]; p[2]=p[5]; p[5]=c;\n+\t c=p[3]; p[3]=p[4]; p[4]=c;\n+\t p+=8;\n+\t}\n+  \tbreak;\n+   default:\n+   \tIF(1, \"bad size\");\n+  \tbreak;\n+  }\n+ }\n+}\n+\n static int LoadChar(LoadState* S)\n {\n  char x;\n@@ -82,7 +125,7 @@ static lua_Integer LoadInteger(LoadState\n \n static TString* LoadString(LoadState* S)\n {\n- size_t size;\n+ unsigned int size;\n  LoadVar(S,size);\n  if (size==0)\n   return NULL;\n@@ -196,6 +239,7 @@ static void LoadHeader(LoadState* S)\n  char s[LUAC_HEADERSIZE];\n  luaU_header(h);\n  LoadBlock(S,s,LUAC_HEADERSIZE);\n+ S->swap=(s[6]!=h[6]); s[6]=h[6];\n  IF (memcmp(h,s,LUAC_HEADERSIZE)!=0, \"bad header\");\n }\n \n@@ -230,7 +274,7 @@ void luaU_header (char* h)\n  *h++=(char)LUAC_FORMAT;\n  *h++=(char)*(char*)&x;\t\t\t\t/* endianness */\n  *h++=(char)sizeof(int);\n- *h++=(char)sizeof(size_t);\n+ *h++=(char)sizeof(unsigned int);\n  *h++=(char)sizeof(Instruction);\n  *h++=(char)sizeof(lua_Number);\n \n"
  },
  {
    "path": "package/utils/lua/patches/040-use-symbolic-functions.patch",
    "content": "--- a/src/Makefile\n+++ b/src/Makefile\n@@ -56,7 +56,7 @@ $(LUA_A): $(CORE_O) $(LIB_O)\n \t$(RANLIB) $@\n \n $(LUA_SO): $(CORE_O) $(LIB_O)\n-\t$(CC) -o $@.$(PKG_VERSION) -shared -Wl,-soname=\"$@.$(PKG_VERSION)\" $?\n+\t$(CC) -o $@.$(PKG_VERSION) -Wl,-Bsymbolic-functions -shared -Wl,-soname=\"$@.$(PKG_VERSION)\" $?\n \tln -fs $@.$(PKG_VERSION) $@\n \n $(LUA_T): $(LUA_O) $(LUA_SO)\n"
  },
  {
    "path": "package/utils/lua/patches/050-honor-cflags.patch",
    "content": "--- a/src/Makefile\n+++ b/src/Makefile\n@@ -56,7 +56,7 @@ $(LUA_A): $(CORE_O) $(LIB_O)\n \t$(RANLIB) $@\n \n $(LUA_SO): $(CORE_O) $(LIB_O)\n-\t$(CC) -o $@.$(PKG_VERSION) -Wl,-Bsymbolic-functions -shared -Wl,-soname=\"$@.$(PKG_VERSION)\" $?\n+\t$(CC) -o $@.$(PKG_VERSION) -Wl,-Bsymbolic-functions $(MYLDFLAGS) -shared -Wl,-soname=\"$@.$(PKG_VERSION)\" $?\n \tln -fs $@.$(PKG_VERSION) $@\n \n $(LUA_T): $(LUA_O) $(LUA_SO)\n"
  },
  {
    "path": "package/utils/lua/patches/100-no_readline.patch",
    "content": "--- a/src/luaconf.h\n+++ b/src/luaconf.h\n@@ -38,7 +38,6 @@\n #if defined(LUA_USE_LINUX)\n #define LUA_USE_POSIX\n #define LUA_USE_DLOPEN\t\t/* needs an extra library: -ldl */\n-#define LUA_USE_READLINE\t/* needs some extra libraries */\n #endif\n \n #if defined(LUA_USE_MACOSX)\n--- a/src/Makefile\n+++ b/src/Makefile\n@@ -17,6 +17,7 @@ LIBS= -lm $(MYLIBS)\n MYCFLAGS=\n MYLDFLAGS=\n MYLIBS=\n+# USE_READLINE=1\n \n # == END OF USER SETTINGS. NO NEED TO CHANGE ANYTHING BELOW THIS LINE =========\n \n@@ -86,7 +87,7 @@ echo:\n \t@echo \"MYLIBS = $(MYLIBS)\"\n \n # convenience targets for popular platforms\n-\n+RFLAG=$(if $(USE_READLINE),-DLUA_USE_READLINE)\n none:\n \t@echo \"Please choose a platform:\"\n \t@echo \"   $(PLATS)\"\n@@ -101,16 +102,16 @@ bsd:\n \t$(MAKE) all MYCFLAGS=\"-DLUA_USE_POSIX -DLUA_USE_DLOPEN\" MYLIBS=\"-Wl,-E\"\n \n freebsd:\n-\t$(MAKE) all MYCFLAGS=\"-DLUA_USE_LINUX\" MYLIBS=\"-Wl,-E -lreadline\"\n+\t$(MAKE) all MYCFLAGS=\"-DLUA_USE_LINUX $(RFLAG)\" MYLIBS=\"-Wl,-E$(if $(USE_READLINE), -lreadline)\"\n \n generic:\n \t$(MAKE) all MYCFLAGS=\n \n linux:\n-\t$(MAKE) all MYCFLAGS+=-DLUA_USE_LINUX MYLIBS=\"-Wl,-E -ldl -lreadline -lhistory -lncurses\"\n+\t$(MAKE) all MYCFLAGS+=\"-DLUA_USE_LINUX $(RFLAG)\" MYLIBS=\"-Wl,-E -ldl $(if $(USE_READLINE), -lreadline -lhistory -lncurses)\"\n \n macosx:\n-\t$(MAKE) all MYCFLAGS=-DLUA_USE_LINUX MYLIBS=\"-lreadline\"\n+\t$(MAKE) all MYCFLAGS=-DLUA_USE_LINUX $(if $(USE_READLINE), MYLIBS=\"-lreadline\")\n # use this on Mac OS X 10.3-\n #\t$(MAKE) all MYCFLAGS=-DLUA_USE_MACOSX\n \n"
  },
  {
    "path": "package/utils/lua/patches/200-lua-path.patch",
    "content": "--- a/src/luaconf.h\n+++ b/src/luaconf.h\n@@ -95,9 +95,9 @@\n \t\".\\\\?.dll;\"  LUA_CDIR\"?.dll;\" LUA_CDIR\"loadall.dll\"\n \n #else\n-#define LUA_ROOT\t\"/usr/local/\"\n-#define LUA_LDIR\tLUA_ROOT \"share/lua/5.1/\"\n-#define LUA_CDIR\tLUA_ROOT \"lib/lua/5.1/\"\n+#define LUA_ROOT\t\"/usr/\"\n+#define LUA_LDIR\tLUA_ROOT \"share/lua/\"\n+#define LUA_CDIR\tLUA_ROOT \"lib/lua/\"\n #define LUA_PATH_DEFAULT  \\\n \t\t\"./?.lua;\"  LUA_LDIR\"?.lua;\"  LUA_LDIR\"?/init.lua;\" \\\n \t\t            LUA_CDIR\"?.lua;\"  LUA_CDIR\"?/init.lua\"\n"
  },
  {
    "path": "package/utils/lua/patches/300-opcode_performance.patch",
    "content": "--- a/src/lvm.c\n+++ b/src/lvm.c\n@@ -31,6 +31,9 @@\n /* limit for table tag-method chains (to avoid loops) */\n #define MAXTAGLOOP\t100\n \n+#ifdef __GNUC__\n+#define COMPUTED_GOTO 1\n+#endif\n \n /*\n  * If 'obj' is a string, it is tried to be interpreted as a number.\n@@ -568,12 +571,63 @@ static inline int arith_mode( const TVal\n     ARITH_OP1_END\n #endif\n \n+#ifdef COMPUTED_GOTO\n+#define OPCODE_TARGET(op) DO_OP_##op:\n+#define CALL_OPCODE(op) goto *opcodes[op];\n+#define OPCODE_PTR(op) [OP_##op] = &&DO_OP_##op\n+#else\n+#define OPCODE_TARGET(op) case OP_##op:\n+#define CALL_OPCODE(op) switch (op)\n+#endif\n+\n \n void luaV_execute (lua_State *L, int nexeccalls) {\n   LClosure *cl;\n   StkId base;\n   TValue *k;\n   const Instruction *pc;\n+#ifdef COMPUTED_GOTO\n+  static const void *opcodes[] = {\n+   OPCODE_PTR(MOVE),\n+   OPCODE_PTR(LOADK),\n+   OPCODE_PTR(LOADBOOL),\n+   OPCODE_PTR(LOADNIL),\n+   OPCODE_PTR(GETUPVAL),\n+   OPCODE_PTR(GETGLOBAL),\n+   OPCODE_PTR(GETTABLE),\n+   OPCODE_PTR(SETGLOBAL),\n+   OPCODE_PTR(SETUPVAL),\n+   OPCODE_PTR(SETTABLE),\n+   OPCODE_PTR(NEWTABLE),\n+   OPCODE_PTR(SELF),\n+   OPCODE_PTR(ADD),\n+   OPCODE_PTR(SUB),\n+   OPCODE_PTR(MUL),\n+   OPCODE_PTR(DIV),\n+   OPCODE_PTR(MOD),\n+   OPCODE_PTR(POW),\n+   OPCODE_PTR(UNM),\n+   OPCODE_PTR(NOT),\n+   OPCODE_PTR(LEN),\n+   OPCODE_PTR(CONCAT),\n+   OPCODE_PTR(JMP),\n+   OPCODE_PTR(EQ),\n+   OPCODE_PTR(LT),\n+   OPCODE_PTR(LE),\n+   OPCODE_PTR(TEST),\n+   OPCODE_PTR(TESTSET),\n+   OPCODE_PTR(CALL),\n+   OPCODE_PTR(TAILCALL),\n+   OPCODE_PTR(RETURN),\n+   OPCODE_PTR(FORLOOP),\n+   OPCODE_PTR(FORPREP),\n+   OPCODE_PTR(TFORLOOP),\n+   OPCODE_PTR(SETLIST),\n+   OPCODE_PTR(CLOSE),\n+   OPCODE_PTR(CLOSURE),\n+   OPCODE_PTR(VARARG)\n+  };\n+#endif\n  reentry:  /* entry point */\n   lua_assert(isLua(L->ci));\n   pc = L->savedpc;\n@@ -598,33 +652,33 @@ void luaV_execute (lua_State *L, int nex\n     lua_assert(base == L->base && L->base == L->ci->base);\n     lua_assert(base <= L->top && L->top <= L->stack + L->stacksize);\n     lua_assert(L->top == L->ci->top || luaG_checkopenop(i));\n-    switch (GET_OPCODE(i)) {\n-      case OP_MOVE: {\n+    CALL_OPCODE(GET_OPCODE(i)) {\n+      OPCODE_TARGET(MOVE) {\n         setobjs2s(L, ra, RB(i));\n         continue;\n       }\n-      case OP_LOADK: {\n+      OPCODE_TARGET(LOADK) {\n         setobj2s(L, ra, KBx(i));\n         continue;\n       }\n-      case OP_LOADBOOL: {\n+      OPCODE_TARGET(LOADBOOL) {\n         setbvalue(ra, GETARG_B(i));\n         if (GETARG_C(i)) pc++;  /* skip next instruction (if C) */\n         continue;\n       }\n-      case OP_LOADNIL: {\n+      OPCODE_TARGET(LOADNIL) {\n         TValue *rb = RB(i);\n         do {\n           setnilvalue(rb--);\n         } while (rb >= ra);\n         continue;\n       }\n-      case OP_GETUPVAL: {\n+      OPCODE_TARGET(GETUPVAL) {\n         int b = GETARG_B(i);\n         setobj2s(L, ra, cl->upvals[b]->v);\n         continue;\n       }\n-      case OP_GETGLOBAL: {\n+      OPCODE_TARGET(GETGLOBAL) {\n         TValue g;\n         TValue *rb = KBx(i);\n         sethvalue(L, &g, cl->env);\n@@ -632,88 +686,88 @@ void luaV_execute (lua_State *L, int nex\n         Protect(luaV_gettable(L, &g, rb, ra));\n         continue;\n       }\n-      case OP_GETTABLE: {\n+      OPCODE_TARGET(GETTABLE) {\n         Protect(luaV_gettable(L, RB(i), RKC(i), ra));\n         continue;\n       }\n-      case OP_SETGLOBAL: {\n+      OPCODE_TARGET(SETGLOBAL) {\n         TValue g;\n         sethvalue(L, &g, cl->env);\n         lua_assert(ttisstring(KBx(i)));\n         Protect(luaV_settable(L, &g, KBx(i), ra));\n         continue;\n       }\n-      case OP_SETUPVAL: {\n+      OPCODE_TARGET(SETUPVAL) {\n         UpVal *uv = cl->upvals[GETARG_B(i)];\n         setobj(L, uv->v, ra);\n         luaC_barrier(L, uv, ra);\n         continue;\n       }\n-      case OP_SETTABLE: {\n+      OPCODE_TARGET(SETTABLE) {\n         Protect(luaV_settable(L, ra, RKB(i), RKC(i)));\n         continue;\n       }\n-      case OP_NEWTABLE: {\n+      OPCODE_TARGET(NEWTABLE) {\n         int b = GETARG_B(i);\n         int c = GETARG_C(i);\n         sethvalue(L, ra, luaH_new(L, luaO_fb2int(b), luaO_fb2int(c)));\n         Protect(luaC_checkGC(L));\n         continue;\n       }\n-      case OP_SELF: {\n+      OPCODE_TARGET(SELF) {\n         StkId rb = RB(i);\n         setobjs2s(L, ra+1, rb);\n         Protect(luaV_gettable(L, rb, RKC(i), ra));\n         continue;\n       }\n-      case OP_ADD: {\n+      OPCODE_TARGET(ADD) {\n         TValue *rb = RKB(i), *rc= RKC(i);\n         arith_op_continue( luai_numadd, try_addint, luai_vectadd );\n         Protect(Arith(L, ra, rb, rc, TM_ADD)); \\\n         continue;\n       }\n-      case OP_SUB: {\n+      OPCODE_TARGET(SUB) {\n         TValue *rb = RKB(i), *rc= RKC(i);\n         arith_op_continue( luai_numsub, try_subint, luai_vectsub );\n         Protect(Arith(L, ra, rb, rc, TM_SUB));\n         continue;\n       }\n-      case OP_MUL: {\n+      OPCODE_TARGET(MUL) {\n         TValue *rb = RKB(i), *rc= RKC(i);\n         arith_op_continue(luai_nummul, try_mulint, luai_vectmul);\n         Protect(Arith(L, ra, rb, rc, TM_MUL));\n         continue;\n       }\n-      case OP_DIV: {\n+      OPCODE_TARGET(DIV) {\n         TValue *rb = RKB(i), *rc= RKC(i);\n         arith_op_continue(luai_numdiv, try_divint, luai_vectdiv);\n         Protect(Arith(L, ra, rb, rc, TM_DIV));\n         continue;\n       }\n-      case OP_MOD: {\n+      OPCODE_TARGET(MOD) {\n         TValue *rb = RKB(i), *rc= RKC(i);\n         arith_op_continue_scalar(luai_nummod, try_modint);  /* scalars only */\n         Protect(Arith(L, ra, rb, rc, TM_MOD));\n         continue;\n       }\n-      case OP_POW: {\n+      OPCODE_TARGET(POW) {\n         TValue *rb = RKB(i), *rc= RKC(i);\n         arith_op_continue(luai_numpow, try_powint, luai_vectpow);\n         Protect(Arith(L, ra, rb, rc, TM_POW));\n         continue;\n       }\n-      case OP_UNM: {\n+      OPCODE_TARGET(UNM) {\n         TValue *rb = RB(i);\n         arith_op1_continue(luai_numunm, try_unmint, luai_vectunm);\n         Protect(Arith(L, ra, rb, rb, TM_UNM));\n         continue;\n       }\n-      case OP_NOT: {\n+      OPCODE_TARGET(NOT) {\n         int res = l_isfalse(RB(i));  /* next assignment may change this value */\n         setbvalue(ra, res);\n         continue;\n       }\n-      case OP_LEN: {\n+      OPCODE_TARGET(LEN) {\n         const TValue *rb = RB(i);\n         switch (ttype(rb)) {\n           case LUA_TTABLE: {\n@@ -733,18 +787,18 @@ void luaV_execute (lua_State *L, int nex\n         }\n         continue;\n       }\n-      case OP_CONCAT: {\n+      OPCODE_TARGET(CONCAT) {\n         int b = GETARG_B(i);\n         int c = GETARG_C(i);\n         Protect(luaV_concat(L, c-b+1, c); luaC_checkGC(L));\n         setobjs2s(L, RA(i), base+b);\n         continue;\n       }\n-      case OP_JMP: {\n+      OPCODE_TARGET(JMP) {\n         dojump(L, pc, GETARG_sBx(i));\n         continue;\n       }\n-      case OP_EQ: {\n+      OPCODE_TARGET(EQ) {\n         TValue *rb = RKB(i);\n         TValue *rc = RKC(i);\n         Protect(\n@@ -754,7 +808,7 @@ void luaV_execute (lua_State *L, int nex\n         pc++;\n         continue;\n       }\n-      case OP_LT: {\n+      OPCODE_TARGET(LT) {\n         Protect(\n           if (luaV_lessthan(L, RKB(i), RKC(i)) == GETARG_A(i))\n             dojump(L, pc, GETARG_sBx(*pc));\n@@ -762,7 +816,7 @@ void luaV_execute (lua_State *L, int nex\n         pc++;\n         continue;\n       }\n-      case OP_LE: {\n+      OPCODE_TARGET(LE) {\n         Protect(\n           if (lessequal(L, RKB(i), RKC(i)) == GETARG_A(i))\n             dojump(L, pc, GETARG_sBx(*pc));\n@@ -770,13 +824,13 @@ void luaV_execute (lua_State *L, int nex\n         pc++;\n         continue;\n       }\n-      case OP_TEST: {\n+      OPCODE_TARGET(TEST) {\n         if (l_isfalse(ra) != GETARG_C(i))\n           dojump(L, pc, GETARG_sBx(*pc));\n         pc++;\n         continue;\n       }\n-      case OP_TESTSET: {\n+      OPCODE_TARGET(TESTSET) {\n         TValue *rb = RB(i);\n         if (l_isfalse(rb) != GETARG_C(i)) {\n           setobjs2s(L, ra, rb);\n@@ -785,7 +839,7 @@ void luaV_execute (lua_State *L, int nex\n         pc++;\n         continue;\n       }\n-      case OP_CALL: {\n+      OPCODE_TARGET(CALL) {\n         int b = GETARG_B(i);\n         int nresults = GETARG_C(i) - 1;\n         if (b != 0) L->top = ra+b;  /* else previous instruction set top */\n@@ -806,7 +860,7 @@ void luaV_execute (lua_State *L, int nex\n           }\n         }\n       }\n-      case OP_TAILCALL: {\n+      OPCODE_TARGET(TAILCALL) {\n         int b = GETARG_B(i);\n         if (b != 0) L->top = ra+b;  /* else previous instruction set top */\n         L->savedpc = pc;\n@@ -838,7 +892,7 @@ void luaV_execute (lua_State *L, int nex\n           }\n         }\n       }\n-      case OP_RETURN: {\n+      OPCODE_TARGET(RETURN) {\n         int b = GETARG_B(i);\n         if (b != 0) L->top = ra+b-1;\n         if (L->openupval) luaF_close(L, base);\n@@ -853,7 +907,7 @@ void luaV_execute (lua_State *L, int nex\n           goto reentry;\n         }\n       }\n-      case OP_FORLOOP: {\n+      OPCODE_TARGET(FORLOOP) {\n         /* If start,step and limit are all integers, we don't need to check\n          * against overflow in the looping.\n          */\n@@ -881,7 +935,7 @@ void luaV_execute (lua_State *L, int nex\n         }\n         continue;\n       }\n-      case OP_FORPREP: {\n+      OPCODE_TARGET(FORPREP) {\n         const TValue *init = ra;\n         const TValue *plimit = ra+1;\n         const TValue *pstep = ra+2;\n@@ -904,7 +958,7 @@ void luaV_execute (lua_State *L, int nex\n         dojump(L, pc, GETARG_sBx(i));\n         continue;\n       }\n-      case OP_TFORLOOP: {\n+      OPCODE_TARGET(TFORLOOP) {\n         StkId cb = ra + 3;  /* call base */\n         setobjs2s(L, cb+2, ra+2);\n         setobjs2s(L, cb+1, ra+1);\n@@ -920,7 +974,7 @@ void luaV_execute (lua_State *L, int nex\n         pc++;\n         continue;\n       }\n-      case OP_SETLIST: {\n+      OPCODE_TARGET(SETLIST) {\n         int n = GETARG_B(i);\n         int c = GETARG_C(i);\n         int last;\n@@ -942,11 +996,11 @@ void luaV_execute (lua_State *L, int nex\n         }\n         continue;\n       }\n-      case OP_CLOSE: {\n+      OPCODE_TARGET(CLOSE) {\n         luaF_close(L, ra);\n         continue;\n       }\n-      case OP_CLOSURE: {\n+      OPCODE_TARGET(CLOSURE) {\n         Proto *p;\n         Closure *ncl;\n         int nup, j;\n@@ -966,7 +1020,7 @@ void luaV_execute (lua_State *L, int nex\n         Protect(luaC_checkGC(L));\n         continue;\n       }\n-      case OP_VARARG: {\n+      OPCODE_TARGET(VARARG) {\n         int b = GETARG_B(i) - 1;\n         int j;\n         CallInfo *ci = L->ci;\n"
  },
  {
    "path": "package/utils/lua/patches-host/001-include-version-number.patch",
    "content": "From 96576b44a1b368bd6590eb0778ae45cc9ccede3f Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Fri, 21 Jun 2019 14:08:38 +0200\nSubject: [PATCH] include version number\n\nIncluding it allows multiple lua versions to coexist.\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\n---\n\ndiff --git a/Makefile b/Makefile\n--- a/Makefile\n+++ b/Makefile\n@@ -41,10 +41,10 @@ RANLIB= ranlib\n PLATS= aix ansi bsd freebsd generic linux macosx mingw posix solaris\n \n # What to install.\n-TO_BIN= lua luac\n+TO_BIN= lua$V luac$V\n TO_INC= lua.h luaconf.h lualib.h lauxlib.h ../etc/lua.hpp\n TO_LIB= liblua.a\n-TO_MAN= lua.1 luac.1\n+TO_MAN= lua$V.1 luac$V.1\n \n # Lua version and release.\n V= 5.1\n@@ -53,7 +53,7 @@ R= 5.1.5\n all:\t$(PLAT)\n \n $(PLATS) clean:\n-\tcd src && $(MAKE) $@\n+\tcd src && $(MAKE) $@ V=$V\n \n test:\tdummy\n \tsrc/lua test/hello.lua\ndiff --git a/doc/lua.1 b/doc/lua5.1.1\nrename from doc/lua.1\nrename to doc/lua5.1.1\ndiff --git a/doc/luac.1 b/doc/luac5.1.1\nrename from doc/luac.1\nrename to doc/luac5.1.1\ndiff --git a/src/Makefile b/src/Makefile\n--- a/src/Makefile\n+++ b/src/Makefile\n@@ -29,10 +29,10 @@ CORE_O=\tlapi.o lcode.o ldebug.o ldo.o ldump.o lfunc.o lgc.o llex.o lmem.o \\\n LIB_O=\tlauxlib.o lbaselib.o ldblib.o liolib.o lmathlib.o loslib.o ltablib.o \\\n \tlstrlib.o loadlib.o linit.o\n \n-LUA_T=\tlua\n+LUA_T=\tlua$V\n LUA_O=\tlua.o\n \n-LUAC_T=\tluac\n+LUAC_T=\tluac$V\n LUAC_O=\tluac.o print.o\n \n ALL_O= $(CORE_O) $(LIB_O) $(LUA_O) $(LUAC_O)\n"
  },
  {
    "path": "package/utils/lua/patches-host/010-lua-5.1.3-lnum-full-260308.patch",
    "content": "--- a/Makefile\n+++ b/Makefile\n@@ -42,7 +42,7 @@ PLATS= aix ansi bsd freebsd generic linu\n \n # What to install.\n TO_BIN= lua$V luac$V\n-TO_INC= lua.h luaconf.h lualib.h lauxlib.h ../etc/lua.hpp\n+TO_INC= lua.h luaconf.h lualib.h lauxlib.h lnum_config.h ../etc/lua.hpp\n TO_LIB= liblua.a\n TO_MAN= lua$V.1 luac$V.1\n \n--- a/src/Makefile\n+++ b/src/Makefile\n@@ -25,7 +25,7 @@ PLATS= aix ansi bsd freebsd generic linu\n LUA_A=\tliblua.a\n CORE_O=\tlapi.o lcode.o ldebug.o ldo.o ldump.o lfunc.o lgc.o llex.o lmem.o \\\n \tlobject.o lopcodes.o lparser.o lstate.o lstring.o ltable.o ltm.o  \\\n-\tlundump.o lvm.o lzio.o\n+\tlundump.o lvm.o lzio.o lnum.o\n LIB_O=\tlauxlib.o lbaselib.o ldblib.o liolib.o lmathlib.o loslib.o ltablib.o \\\n \tlstrlib.o loadlib.o linit.o\n \n@@ -148,6 +148,7 @@ llex.o: llex.c lua.h luaconf.h ldo.h lob\n lmathlib.o: lmathlib.c lua.h luaconf.h lauxlib.h lualib.h\n lmem.o: lmem.c lua.h luaconf.h ldebug.h lstate.h lobject.h llimits.h \\\n   ltm.h lzio.h lmem.h ldo.h\n+lnum.o: lnum.c lua.h llex.h lnum.h\n loadlib.o: loadlib.c lua.h luaconf.h lauxlib.h lualib.h\n lobject.o: lobject.c lua.h luaconf.h ldo.h lobject.h llimits.h lstate.h \\\n   ltm.h lzio.h lmem.h lstring.h lgc.h lvm.h\n@@ -179,4 +180,18 @@ lzio.o: lzio.c lua.h luaconf.h llimits.h\n print.o: print.c ldebug.h lstate.h lua.h luaconf.h lobject.h llimits.h \\\n   ltm.h lzio.h lmem.h lopcodes.h lundump.h\n \n+luaconf.h: lnum_config.h\n+lapi.c: lnum.h\n+lauxlib.c: llimits.h\n+lbaselib.c: llimits.h lobject.h lapi.h\n+lcode.c: lnum.h\n+liolib.c: lnum.h llex.h\n+llex.c: lnum.h\n+lnum.h: lobject.h\n+lobject.c: llex.h lnum.h\n+ltable.c: lnum.h\n+lua.c: llimits.h\n+lvm.c: llex.h lnum.h\n+print.c: lnum.h\n+\n # (end of Makefile)\n--- a/src/lapi.c\n+++ b/src/lapi.c\n@@ -28,7 +28,7 @@\n #include \"ltm.h\"\n #include \"lundump.h\"\n #include \"lvm.h\"\n-\n+#include \"lnum.h\"\n \n \n const char lua_ident[] =\n@@ -241,12 +241,13 @@ LUA_API void lua_pushvalue (lua_State *L\n \n LUA_API int lua_type (lua_State *L, int idx) {\n   StkId o = index2adr(L, idx);\n-  return (o == luaO_nilobject) ? LUA_TNONE : ttype(o);\n+  return (o == luaO_nilobject) ? LUA_TNONE : ttype_ext(o);\n }\n \n \n LUA_API const char *lua_typename (lua_State *L, int t) {\n   UNUSED(L);\n+  lua_assert( t!= LUA_TINT );\n   return (t == LUA_TNONE) ? \"no value\" : luaT_typenames[t];\n }\n \n@@ -264,6 +265,14 @@ LUA_API int lua_isnumber (lua_State *L,\n }\n \n \n+LUA_API int lua_isinteger (lua_State *L, int idx) {\n+  TValue tmp;\n+  lua_Integer dum;\n+  const TValue *o = index2adr(L, idx);\n+  return tonumber(o,&tmp) && (ttisint(o) || tt_integer_valued(o,&dum));\n+}\n+\n+\n LUA_API int lua_isstring (lua_State *L, int idx) {\n   int t = lua_type(L, idx);\n   return (t == LUA_TSTRING || t == LUA_TNUMBER);\n@@ -309,31 +318,66 @@ LUA_API int lua_lessthan (lua_State *L,\n }\n \n \n-\n LUA_API lua_Number lua_tonumber (lua_State *L, int idx) {\n   TValue n;\n   const TValue *o = index2adr(L, idx);\n-  if (tonumber(o, &n))\n+  if (tonumber(o, &n)) {\n+#ifdef LNUM_COMPLEX\n+    if (nvalue_img(o) != 0)\n+      luaG_runerror(L, \"expecting a real number\");\n+#endif\n     return nvalue(o);\n-  else\n-    return 0;\n+  }\n+  return 0;\n }\n \n \n LUA_API lua_Integer lua_tointeger (lua_State *L, int idx) {\n   TValue n;\n+    /* Lua 5.1 documented behaviour is to return nonzero for non-integer:\n+     * \"If the number is not an integer, it is truncated in some non-specified way.\" \n+     * I would suggest to change this, to return 0 for anything that would\n+     * not fit in 'lua_Integer'.\n+     */\n+#ifdef LUA_COMPAT_TOINTEGER\n+  /* Lua 5.1 compatible */\n   const TValue *o = index2adr(L, idx);\n   if (tonumber(o, &n)) {\n-    lua_Integer res;\n-    lua_Number num = nvalue(o);\n-    lua_number2integer(res, num);\n-    return res;\n+    lua_Integer i;\n+    lua_Number d;\n+    if (ttisint(o)) return ivalue(o);\n+    d= nvalue_fast(o);\n+# ifdef LNUM_COMPLEX\n+    if (nvalue_img_fast(o) != 0)\n+      luaG_runerror(L, \"expecting a real number\");\n+# endif\n+    lua_number2integer(i, d);\n+    return i;\n   }\n-  else\n-    return 0;\n+#else\n+  /* New suggestion */\n+  const TValue *o = index2adr(L, idx);\n+  if (tonumber(o, &n)) {\n+    lua_Integer i;\n+    if (ttisint(o)) return ivalue(o);\n+    if (tt_integer_valued(o,&i)) return i;\n+  }\n+#endif\n+  return 0;\n }\n \n \n+#ifdef LNUM_COMPLEX\n+LUA_API lua_Complex lua_tocomplex (lua_State *L, int idx) {\n+  TValue tmp;\n+  const TValue *o = index2adr(L, idx);\n+  if (tonumber(o, &tmp))\n+    return nvalue_complex(o);\n+  return 0;\n+}\n+#endif\n+\n+\n LUA_API int lua_toboolean (lua_State *L, int idx) {\n   const TValue *o = index2adr(L, idx);\n   return !l_isfalse(o);\n@@ -364,6 +408,7 @@ LUA_API size_t lua_objlen (lua_State *L,\n     case LUA_TSTRING: return tsvalue(o)->len;\n     case LUA_TUSERDATA: return uvalue(o)->len;\n     case LUA_TTABLE: return luaH_getn(hvalue(o));\n+    case LUA_TINT:\n     case LUA_TNUMBER: {\n       size_t l;\n       lua_lock(L);  /* `luaV_tostring' may create a new string */\n@@ -426,6 +471,8 @@ LUA_API void lua_pushnil (lua_State *L)\n }\n \n \n+/* 'lua_pushnumber()' may lose accuracy on integers, 'lua_pushinteger' will not.\n+ */\n LUA_API void lua_pushnumber (lua_State *L, lua_Number n) {\n   lua_lock(L);\n   setnvalue(L->top, n);\n@@ -434,12 +481,22 @@ LUA_API void lua_pushnumber (lua_State *\n }\n \n \n-LUA_API void lua_pushinteger (lua_State *L, lua_Integer n) {\n+LUA_API void lua_pushinteger (lua_State *L, lua_Integer i) {\n+  lua_lock(L);\n+  setivalue(L->top, i);\n+  api_incr_top(L);\n+  lua_unlock(L);\n+}\n+\n+\n+#ifdef LNUM_COMPLEX\n+LUA_API void lua_pushcomplex (lua_State *L, lua_Complex v) {\n   lua_lock(L);\n-  setnvalue(L->top, cast_num(n));\n+  setnvalue_complex( L->top, v );\n   api_incr_top(L);\n   lua_unlock(L);\n }\n+#endif\n \n \n LUA_API void lua_pushlstring (lua_State *L, const char *s, size_t len) {\n@@ -569,7 +626,7 @@ LUA_API void lua_rawgeti (lua_State *L,\n   lua_lock(L);\n   o = index2adr(L, idx);\n   api_check(L, ttistable(o));\n-  setobj2s(L, L->top, luaH_getnum(hvalue(o), n));\n+  setobj2s(L, L->top, luaH_getint(hvalue(o), n));\n   api_incr_top(L);\n   lua_unlock(L);\n }\n@@ -597,6 +654,9 @@ LUA_API int lua_getmetatable (lua_State\n     case LUA_TUSERDATA:\n       mt = uvalue(obj)->metatable;\n       break;\n+    case LUA_TINT:\n+      mt = G(L)->mt[LUA_TNUMBER];\n+      break;\n     default:\n       mt = G(L)->mt[ttype(obj)];\n       break;\n@@ -687,7 +747,7 @@ LUA_API void lua_rawseti (lua_State *L,\n   api_checknelems(L, 1);\n   o = index2adr(L, idx);\n   api_check(L, ttistable(o));\n-  setobj2t(L, luaH_setnum(L, hvalue(o), n), L->top-1);\n+  setobj2t(L, luaH_setint(L, hvalue(o), n), L->top-1);\n   luaC_barriert(L, hvalue(o), L->top-1);\n   L->top--;\n   lua_unlock(L);\n@@ -721,7 +781,7 @@ LUA_API int lua_setmetatable (lua_State\n       break;\n     }\n     default: {\n-      G(L)->mt[ttype(obj)] = mt;\n+      G(L)->mt[ttype_ext(obj)] = mt;\n       break;\n     }\n   }\n@@ -1085,3 +1145,32 @@ LUA_API const char *lua_setupvalue (lua_\n   return name;\n }\n \n+\n+/* Help function for 'luaB_tonumber()', avoids multiple str->number\n+ * conversions for Lua \"tonumber()\".\n+ *\n+ * Also pushes floating point numbers with integer value as integer, which\n+ * can be used by 'tonumber()' in scripts to bring values back to integer\n+ * realm.\n+ *\n+ * Note: The 'back to integer realm' is _not_ to affect string conversions:\n+ * 'tonumber(\"4294967295.1\")' should give a floating point value, although\n+ * the value would be 4294967296 (and storable in int64 realm).\n+ */\n+int lua_pushvalue_as_number (lua_State *L, int idx)\n+{\n+  const TValue *o = index2adr(L, idx);\n+  TValue tmp;\n+  lua_Integer i;\n+  if (ttisnumber(o)) {\n+    if ( (!ttisint(o)) && tt_integer_valued(o,&i)) {\n+      lua_pushinteger( L, i );\n+      return 1;\n+    }\n+  } else if (!tonumber(o, &tmp)) {\n+    return 0;\n+  }\n+  if (ttisint(o)) lua_pushinteger( L, ivalue(o) );\n+  else lua_pushnumber( L, nvalue_fast(o) );\n+  return 1;\n+}\n--- a/src/lapi.h\n+++ b/src/lapi.h\n@@ -13,4 +13,6 @@\n \n LUAI_FUNC void luaA_pushobject (lua_State *L, const TValue *o);\n \n+int lua_pushvalue_as_number (lua_State *L, int idx);\n+\n #endif\n--- a/src/lauxlib.c\n+++ b/src/lauxlib.c\n@@ -23,7 +23,7 @@\n #include \"lua.h\"\n \n #include \"lauxlib.h\"\n-\n+#include \"llimits.h\"\n \n #define FREELIST_REF\t0\t/* free list of references */\n \n@@ -66,7 +66,7 @@ LUALIB_API int luaL_typerror (lua_State\n \n \n static void tag_error (lua_State *L, int narg, int tag) {\n-  luaL_typerror(L, narg, lua_typename(L, tag));\n+  luaL_typerror(L, narg, tag==LUA_TINT ? \"integer\" : lua_typename(L, tag));\n }\n \n \n@@ -188,8 +188,8 @@ LUALIB_API lua_Number luaL_optnumber (lu\n \n LUALIB_API lua_Integer luaL_checkinteger (lua_State *L, int narg) {\n   lua_Integer d = lua_tointeger(L, narg);\n-  if (d == 0 && !lua_isnumber(L, narg))  /* avoid extra test when d is not 0 */\n-    tag_error(L, narg, LUA_TNUMBER);\n+  if (d == 0 && !lua_isinteger(L, narg))  /* avoid extra test when d is not 0 */\n+    tag_error(L, narg, LUA_TINT);\n   return d;\n }\n \n@@ -200,6 +200,16 @@ LUALIB_API lua_Integer luaL_optinteger (\n }\n \n \n+#ifdef LNUM_COMPLEX\n+LUALIB_API lua_Complex luaL_checkcomplex (lua_State *L, int narg) {\n+  lua_Complex c = lua_tocomplex(L, narg);\n+  if (c == 0 && !lua_isnumber(L, narg))  /* avoid extra test when c is not 0 */\n+    tag_error(L, narg, LUA_TNUMBER);\n+  return c;\n+}\n+#endif\n+\n+\n LUALIB_API int luaL_getmetafield (lua_State *L, int obj, const char *event) {\n   if (!lua_getmetatable(L, obj))  /* no metatable? */\n     return 0;\n--- a/src/lauxlib.h\n+++ b/src/lauxlib.h\n@@ -57,6 +57,12 @@ LUALIB_API lua_Number (luaL_optnumber) (\n LUALIB_API lua_Integer (luaL_checkinteger) (lua_State *L, int numArg);\n LUALIB_API lua_Integer (luaL_optinteger) (lua_State *L, int nArg,\n                                           lua_Integer def);\n+#define luaL_checkint32(L,narg) ((int)luaL_checkinteger(L,narg))\n+#define luaL_optint32(L,narg,def) ((int)luaL_optinteger(L,narg,def))\n+\n+#ifdef LNUM_COMPLEX\n+  LUALIB_API lua_Complex (luaL_checkcomplex) (lua_State *L, int narg);\n+#endif\n \n LUALIB_API void (luaL_checkstack) (lua_State *L, int sz, const char *msg);\n LUALIB_API void (luaL_checktype) (lua_State *L, int narg, int t);\n--- a/src/lbaselib.c\n+++ b/src/lbaselib.c\n@@ -18,7 +18,9 @@\n \n #include \"lauxlib.h\"\n #include \"lualib.h\"\n-\n+#include \"llimits.h\"\n+#include \"lobject.h\"\n+#include \"lapi.h\"\n \n \n \n@@ -54,20 +56,25 @@ static int luaB_tonumber (lua_State *L)\n   int base = luaL_optint(L, 2, 10);\n   if (base == 10) {  /* standard conversion */\n     luaL_checkany(L, 1);\n-    if (lua_isnumber(L, 1)) {\n-      lua_pushnumber(L, lua_tonumber(L, 1));\n+    if (lua_isnumber(L, 1)) {       /* numeric string, or a number */\n+      lua_pushvalue_as_number(L,1);     /* API extension (not to lose accuracy here) */\n       return 1;\n-    }\n+\t}\n   }\n   else {\n     const char *s1 = luaL_checkstring(L, 1);\n     char *s2;\n-    unsigned long n;\n+    unsigned LUA_INTEGER n;\n     luaL_argcheck(L, 2 <= base && base <= 36, 2, \"base out of range\");\n-    n = strtoul(s1, &s2, base);\n+    n = lua_str2ul(s1, &s2, base);\n     if (s1 != s2) {  /* at least one valid digit? */\n       while (isspace((unsigned char)(*s2))) s2++;  /* skip trailing spaces */\n       if (*s2 == '\\0') {  /* no invalid trailing characters? */\n+\t  \n+\t\t/* Push as number, there needs to be separate 'luaB_tointeger' for\n+\t\t * when the caller wants to preserve the bits (matters if unsigned\n+\t\t * values are used).\n+\t\t */\n         lua_pushnumber(L, (lua_Number)n);\n         return 1;\n       }\n@@ -144,7 +151,7 @@ static int luaB_setfenv (lua_State *L) {\n   luaL_checktype(L, 2, LUA_TTABLE);\n   getfunc(L, 0);\n   lua_pushvalue(L, 2);\n-  if (lua_isnumber(L, 1) && lua_tonumber(L, 1) == 0) {\n+  if (lua_isnumber(L, 1) && lua_tointeger(L, 1) == 0) {\n     /* change environment of current thread */\n     lua_pushthread(L);\n     lua_insert(L, -2);\n@@ -209,7 +216,7 @@ static int luaB_collectgarbage (lua_Stat\n       return 1;\n     }\n     default: {\n-      lua_pushnumber(L, res);\n+      lua_pushinteger(L, res);\n       return 1;\n     }\n   }\n@@ -631,6 +638,8 @@ static void base_open (lua_State *L) {\n   luaL_register(L, \"_G\", base_funcs);\n   lua_pushliteral(L, LUA_VERSION);\n   lua_setglobal(L, \"_VERSION\");  /* set global _VERSION */\n+  lua_pushliteral(L, LUA_LNUM);\n+  lua_setglobal(L, \"_LNUM\");  /* \"[complex] double|float|ldouble int32|int64\" */\n   /* `ipairs' and `pairs' need auxiliary functions as upvalues */\n   auxopen(L, \"ipairs\", luaB_ipairs, ipairsaux);\n   auxopen(L, \"pairs\", luaB_pairs, luaB_next);\n--- a/src/lcode.c\n+++ b/src/lcode.c\n@@ -22,13 +22,18 @@\n #include \"lopcodes.h\"\n #include \"lparser.h\"\n #include \"ltable.h\"\n+#include \"lnum.h\"\n \n \n #define hasjumps(e)\t((e)->t != (e)->f)\n \n-\n static int isnumeral(expdesc *e) {\n-  return (e->k == VKNUM && e->t == NO_JUMP && e->f == NO_JUMP);\n+  int ek=\n+#ifdef LNUM_COMPLEX\n+    (e->k == VKNUM2) ||\n+#endif\n+    (e->k == VKINT) || (e->k == VKNUM);\n+  return (ek && e->t == NO_JUMP && e->f == NO_JUMP);\n }\n \n \n@@ -231,12 +236,16 @@ static int addk (FuncState *fs, TValue *\n   TValue *idx = luaH_set(L, fs->h, k);\n   Proto *f = fs->f;\n   int oldsize = f->sizek;\n-  if (ttisnumber(idx)) {\n-    lua_assert(luaO_rawequalObj(&fs->f->k[cast_int(nvalue(idx))], v));\n-    return cast_int(nvalue(idx));\n+  if (ttype(idx)==LUA_TNUMBER) {\n+    luai_normalize(idx);\n+    lua_assert( ttype(idx)==LUA_TINT );     /* had no fraction */\n+  }\n+  if (ttisint(idx)) {\n+    lua_assert(luaO_rawequalObj(&fs->f->k[ivalue(idx)], v));\n+    return cast_int(ivalue(idx));\n   }\n   else {  /* constant not found; create a new entry */\n-    setnvalue(idx, cast_num(fs->nk));\n+    setivalue(idx, fs->nk);\n     luaM_growvector(L, f->k, fs->nk, f->sizek, TValue,\n                     MAXARG_Bx, \"constant table overflow\");\n     while (oldsize < f->sizek) setnilvalue(&f->k[oldsize++]);\n@@ -261,6 +270,21 @@ int luaK_numberK (FuncState *fs, lua_Num\n }\n \n \n+int luaK_integerK (FuncState *fs, lua_Integer r) {\n+  TValue o;\n+  setivalue(&o, r);\n+  return addk(fs, &o, &o);\n+}\n+\n+\n+#ifdef LNUM_COMPLEX\n+static int luaK_imagK (FuncState *fs, lua_Number r) {\n+  TValue o;\n+  setnvalue_complex(&o, r*I);\n+  return addk(fs, &o, &o);\n+}\n+#endif\n+\n static int boolK (FuncState *fs, int b) {\n   TValue o;\n   setbvalue(&o, b);\n@@ -359,6 +383,16 @@ static void discharge2reg (FuncState *fs\n       luaK_codeABx(fs, OP_LOADK, reg, luaK_numberK(fs, e->u.nval));\n       break;\n     }\n+    case VKINT: {\n+      luaK_codeABx(fs, OP_LOADK, reg, luaK_integerK(fs, e->u.ival));\n+      break;\n+    }\n+#ifdef LNUM_COMPLEX\n+    case VKNUM2: {\n+      luaK_codeABx(fs, OP_LOADK, reg, luaK_imagK(fs, e->u.nval));\n+      break;\n+    }\n+#endif\n     case VRELOCABLE: {\n       Instruction *pc = &getcode(fs, e);\n       SETARG_A(*pc, reg);\n@@ -444,6 +478,10 @@ void luaK_exp2val (FuncState *fs, expdes\n int luaK_exp2RK (FuncState *fs, expdesc *e) {\n   luaK_exp2val(fs, e);\n   switch (e->k) {\n+#ifdef LNUM_COMPLEX\n+    case VKNUM2:\n+#endif\n+    case VKINT:\n     case VKNUM:\n     case VTRUE:\n     case VFALSE:\n@@ -451,6 +489,10 @@ int luaK_exp2RK (FuncState *fs, expdesc\n       if (fs->nk <= MAXINDEXRK) {  /* constant fit in RK operand? */\n         e->u.s.info = (e->k == VNIL)  ? nilK(fs) :\n                       (e->k == VKNUM) ? luaK_numberK(fs, e->u.nval) :\n+                      (e->k == VKINT) ? luaK_integerK(fs, e->u.ival) :\n+#ifdef LNUM_COMPLEX\n+                      (e->k == VKNUM2) ? luaK_imagK(fs, e->u.nval) :\n+#endif\n                                         boolK(fs, (e->k == VTRUE));\n         e->k = VK;\n         return RKASK(e->u.s.info);\n@@ -540,7 +582,10 @@ void luaK_goiftrue (FuncState *fs, expde\n   int pc;  /* pc of last jump */\n   luaK_dischargevars(fs, e);\n   switch (e->k) {\n-    case VK: case VKNUM: case VTRUE: {\n+#ifdef LNUM_COMPLEX\n+    case VKNUM2:\n+#endif\n+    case VKINT: case VK: case VKNUM: case VTRUE: {\n       pc = NO_JUMP;  /* always true; do nothing */\n       break;\n     }\n@@ -590,7 +635,10 @@ static void codenot (FuncState *fs, expd\n       e->k = VTRUE;\n       break;\n     }\n-    case VK: case VKNUM: case VTRUE: {\n+#ifdef LNUM_COMPLEX\n+    case VKNUM2:\n+#endif\n+    case VKINT: case VK: case VKNUM: case VTRUE: {\n       e->k = VFALSE;\n       break;\n     }\n@@ -626,25 +674,70 @@ void luaK_indexed (FuncState *fs, expdes\n \n static int constfolding (OpCode op, expdesc *e1, expdesc *e2) {\n   lua_Number v1, v2, r;\n+  int vkres= VKNUM;\n   if (!isnumeral(e1) || !isnumeral(e2)) return 0;\n-  v1 = e1->u.nval;\n-  v2 = e2->u.nval;\n+\n+  /* real and imaginary parts don't mix. */\n+#ifdef LNUM_COMPLEX\n+  if (e1->k == VKNUM2) {\n+    if ((op != OP_UNM) && (e2->k != VKNUM2)) return 0; \n+    vkres= VKNUM2; }\n+  else if (e2->k == VKNUM2) { return 0; }\n+#endif\n+  if ((e1->k == VKINT) && (e2->k == VKINT)) {\n+    lua_Integer i1= e1->u.ival, i2= e2->u.ival;\n+    lua_Integer rr;\n+    int done= 0;\n+    /* Integer/integer calculations (may end up producing floating point) */\n+    switch (op) {\n+      case OP_ADD: done= try_addint( &rr, i1, i2 ); break;\n+      case OP_SUB: done= try_subint( &rr, i1, i2 ); break;\n+      case OP_MUL: done= try_mulint( &rr, i1, i2 ); break;\n+      case OP_DIV: done= try_divint( &rr, i1, i2 ); break;\n+      case OP_MOD: done= try_modint( &rr, i1, i2 ); break;\n+      case OP_POW: done= try_powint( &rr, i1, i2 ); break;\n+      case OP_UNM: done= try_unmint( &rr, i1 ); break;\n+      default:     done= 0; break;\n+    }\n+    if (done) {\n+      e1->u.ival = rr;  /* remained within integer range */\n+      return 1;\n+    }\n+  }\n+  v1 = (e1->k == VKINT) ? ((lua_Number)e1->u.ival) : e1->u.nval;\n+  v2 = (e2->k == VKINT) ? ((lua_Number)e2->u.ival) : e2->u.nval;\n+\n   switch (op) {\n     case OP_ADD: r = luai_numadd(v1, v2); break;\n     case OP_SUB: r = luai_numsub(v1, v2); break;\n-    case OP_MUL: r = luai_nummul(v1, v2); break;\n+    case OP_MUL: \n+#ifdef LNUM_COMPLEX\n+        if (vkres==VKNUM2) return 0;    /* leave to runtime (could do here, but not worth it?) */\n+#endif\n+        r = luai_nummul(v1, v2); break;\n     case OP_DIV:\n       if (v2 == 0) return 0;  /* do not attempt to divide by 0 */\n-      r = luai_numdiv(v1, v2); break;\n+#ifdef LNUM_COMPLEX\n+        if (vkres==VKNUM2) return 0;    /* leave to runtime */\n+#endif\n+        r = luai_numdiv(v1, v2); break;\n     case OP_MOD:\n       if (v2 == 0) return 0;  /* do not attempt to divide by 0 */\n+#ifdef LNUM_COMPLEX\n+      if (vkres==VKNUM2) return 0;    /* leave to runtime */\n+#endif\n       r = luai_nummod(v1, v2); break;\n-    case OP_POW: r = luai_numpow(v1, v2); break;\n+    case OP_POW: \n+#ifdef LNUM_COMPLEX\n+      if (vkres==VKNUM2) return 0;    /* leave to runtime */\n+#endif\n+      r = luai_numpow(v1, v2); break;\n     case OP_UNM: r = luai_numunm(v1); break;\n     case OP_LEN: return 0;  /* no constant folding for 'len' */\n     default: lua_assert(0); r = 0; break;\n   }\n   if (luai_numisnan(r)) return 0;  /* do not attempt to produce NaN */\n+  e1->k = cast(expkind,vkres);\n   e1->u.nval = r;\n   return 1;\n }\n@@ -688,7 +781,8 @@ static void codecomp (FuncState *fs, OpC\n \n void luaK_prefix (FuncState *fs, UnOpr op, expdesc *e) {\n   expdesc e2;\n-  e2.t = e2.f = NO_JUMP; e2.k = VKNUM; e2.u.nval = 0;\n+  e2.t = e2.f = NO_JUMP; e2.k = VKINT; e2.u.ival = 0;\n+\n   switch (op) {\n     case OPR_MINUS: {\n       if (!isnumeral(e))\n--- a/src/lcode.h\n+++ b/src/lcode.h\n@@ -71,6 +71,6 @@ LUAI_FUNC void luaK_prefix (FuncState *f\n LUAI_FUNC void luaK_infix (FuncState *fs, BinOpr op, expdesc *v);\n LUAI_FUNC void luaK_posfix (FuncState *fs, BinOpr op, expdesc *v1, expdesc *v2);\n LUAI_FUNC void luaK_setlist (FuncState *fs, int base, int nelems, int tostore);\n-\n+LUAI_FUNC int luaK_integerK (FuncState *fs, lua_Integer r);\n \n #endif\n--- a/src/ldebug.c\n+++ b/src/ldebug.c\n@@ -183,7 +183,7 @@ static void collectvalidlines (lua_State\n     int *lineinfo = f->l.p->lineinfo;\n     int i;\n     for (i=0; i<f->l.p->sizelineinfo; i++)\n-      setbvalue(luaH_setnum(L, t, lineinfo[i]), 1);\n+      setbvalue(luaH_setint(L, t, lineinfo[i]), 1);\n     sethvalue(L, L->top, t); \n   }\n   incr_top(L);\n@@ -566,7 +566,7 @@ static int isinstack (CallInfo *ci, cons\n \n void luaG_typeerror (lua_State *L, const TValue *o, const char *op) {\n   const char *name = NULL;\n-  const char *t = luaT_typenames[ttype(o)];\n+  const char *t = luaT_typenames[ttype_ext(o)];\n   const char *kind = (isinstack(L->ci, o)) ?\n                          getobjname(L, L->ci, cast_int(o - L->base), &name) :\n                          NULL;\n@@ -594,8 +594,8 @@ void luaG_aritherror (lua_State *L, cons\n \n \n int luaG_ordererror (lua_State *L, const TValue *p1, const TValue *p2) {\n-  const char *t1 = luaT_typenames[ttype(p1)];\n-  const char *t2 = luaT_typenames[ttype(p2)];\n+  const char *t1 = luaT_typenames[ttype_ext(p1)];\n+  const char *t2 = luaT_typenames[ttype_ext(p2)];\n   if (t1[2] == t2[2])\n     luaG_runerror(L, \"attempt to compare two %s values\", t1);\n   else\n--- a/src/ldo.c\n+++ b/src/ldo.c\n@@ -220,9 +220,9 @@ static StkId adjust_varargs (lua_State *\n     luaD_checkstack(L, p->maxstacksize);\n     htab = luaH_new(L, nvar, 1);  /* create `arg' table */\n     for (i=0; i<nvar; i++)  /* put extra arguments into `arg' table */\n-      setobj2n(L, luaH_setnum(L, htab, i+1), L->top - nvar + i);\n+      setobj2n(L, luaH_setint(L, htab, i+1), L->top - nvar + i);\n     /* store counter in field `n' */\n-    setnvalue(luaH_setstr(L, htab, luaS_newliteral(L, \"n\")), cast_num(nvar));\n+    setivalue(luaH_setstr(L, htab, luaS_newliteral(L, \"n\")), nvar);\n   }\n #endif\n   /* move fixed parameters to final position */\n--- a/src/ldump.c\n+++ b/src/ldump.c\n@@ -52,6 +52,11 @@ static void DumpNumber(lua_Number x, Dum\n  DumpVar(x,D);\n }\n \n+static void DumpInteger(lua_Integer x, DumpState* D)\n+{\n+ DumpVar(x,D);\n+}\n+\n static void DumpVector(const void* b, int n, size_t size, DumpState* D)\n {\n  DumpInt(n,D);\n@@ -93,8 +98,11 @@ static void DumpConstants(const Proto* f\n \tDumpChar(bvalue(o),D);\n \tbreak;\n    case LUA_TNUMBER:\n-\tDumpNumber(nvalue(o),D);\n+\tDumpNumber(nvalue_fast(o),D);\n \tbreak;\n+   case LUA_TINT:\n+\tDumpInteger(ivalue(o),D);\n+    break;\n    case LUA_TSTRING:\n \tDumpString(rawtsvalue(o),D);\n \tbreak;\n--- a/src/liolib.c\n+++ b/src/liolib.c\n@@ -9,6 +9,7 @@\n #include <stdio.h>\n #include <stdlib.h>\n #include <string.h>\n+#include <ctype.h>\n \n #define liolib_c\n #define LUA_LIB\n@@ -18,7 +19,8 @@\n #include \"lauxlib.h\"\n #include \"lualib.h\"\n \n-\n+#include \"lnum.h\"\n+#include \"llex.h\"\n \n #define IO_INPUT\t1\n #define IO_OUTPUT\t2\n@@ -269,6 +271,13 @@ static int io_lines (lua_State *L) {\n ** =======================================================\n */\n \n+/*\n+* Many problems if we intend the same 'n' format specifier (see 'file:read()')\n+* to work for both FP and integer numbers, without losing their accuracy. So\n+* we don't. 'n' reads numbers as floating points, 'i' as integers. Old code\n+* remains valid, but won't provide full integer accuracy (this only matters\n+* with float FP and/or 64-bit integers).\n+*/\n \n static int read_number (lua_State *L, FILE *f) {\n   lua_Number d;\n@@ -282,6 +291,43 @@ static int read_number (lua_State *L, FI\n   }\n }\n \n+static int read_integer (lua_State *L, FILE *f) {\n+  lua_Integer i;\n+  if (fscanf(f, LUA_INTEGER_SCAN, &i) == 1) {\n+    lua_pushinteger(L, i);\n+    return 1;\n+  }\n+  else return 0;  /* read fails */\n+}\n+\n+#ifdef LNUM_COMPLEX\n+static int read_complex (lua_State *L, FILE *f) {\n+  /* NNN / NNNi / NNN+MMMi / NNN-MMMi */\n+  lua_Number a,b;\n+  if (fscanf(f, LUA_NUMBER_SCAN, &a) == 1) {\n+    int c=fgetc(f);\n+    switch(c) {\n+        case 'i':\n+            lua_pushcomplex(L, a*I);\n+            return 1;\n+        case '+':\n+        case '-':\n+            /* \"i\" is consumed if at the end; just 'NNN+MMM' will most likely\n+             * behave as if \"i\" was there? (TBD: test)\n+             */\n+            if (fscanf(f, LUA_NUMBER_SCAN \"i\", &b) == 1) {\n+                lua_pushcomplex(L, a+ (c=='+' ? b:-b)*I);\n+                return 1;\n+            }\n+    }\n+    ungetc( c,f );\n+    lua_pushnumber(L,a);  /*real part only*/\n+    return 1;\n+  }\n+  return 0;  /* read fails */\n+}\n+#endif\n+\n \n static int test_eof (lua_State *L, FILE *f) {\n   int c = getc(f);\n@@ -355,6 +401,14 @@ static int g_read (lua_State *L, FILE *f\n           case 'n':  /* number */\n             success = read_number(L, f);\n             break;\n+          case 'i':  /* integer (full accuracy) */\n+            success = read_integer(L, f);\n+            break;\n+#ifdef LNUM_COMPLEX\n+          case 'c':  /* complex */\n+            success = read_complex(L, f);\n+            break;\n+#endif\n           case 'l':  /* line */\n             success = read_line(L, f);\n             break;\n@@ -415,9 +469,10 @@ static int g_write (lua_State *L, FILE *\n   int status = 1;\n   for (; nargs--; arg++) {\n     if (lua_type(L, arg) == LUA_TNUMBER) {\n-      /* optimization: could be done exactly as for strings */\n-      status = status &&\n-          fprintf(f, LUA_NUMBER_FMT, lua_tonumber(L, arg)) > 0;\n+      if (lua_isinteger(L,arg))\n+          status = status && fprintf(f, LUA_INTEGER_FMT, lua_tointeger(L, arg)) > 0;\n+      else\n+          status = status && fprintf(f, LUA_NUMBER_FMT, lua_tonumber(L, arg)) > 0;\n     }\n     else {\n       size_t l;\n@@ -460,7 +515,7 @@ static int f_setvbuf (lua_State *L) {\n   static const char *const modenames[] = {\"no\", \"full\", \"line\", NULL};\n   FILE *f = tofile(L);\n   int op = luaL_checkoption(L, 2, NULL, modenames);\n-  lua_Integer sz = luaL_optinteger(L, 3, LUAL_BUFFERSIZE);\n+  size_t sz = luaL_optint32(L, 3, LUAL_BUFFERSIZE);\n   int res = setvbuf(f, NULL, mode[op], sz);\n   return pushresult(L, res == 0, NULL);\n }\n--- a/src/llex.c\n+++ b/src/llex.c\n@@ -22,6 +22,7 @@\n #include \"lstring.h\"\n #include \"ltable.h\"\n #include \"lzio.h\"\n+#include \"lnum.h\"\n \n \n \n@@ -34,13 +35,17 @@\n \n \n /* ORDER RESERVED */\n-const char *const luaX_tokens [] = {\n+static const char *const luaX_tokens [] = {\n     \"and\", \"break\", \"do\", \"else\", \"elseif\",\n     \"end\", \"false\", \"for\", \"function\", \"if\",\n     \"in\", \"local\", \"nil\", \"not\", \"or\", \"repeat\",\n     \"return\", \"then\", \"true\", \"until\", \"while\",\n     \"..\", \"...\", \"==\", \">=\", \"<=\", \"~=\",\n     \"<number>\", \"<name>\", \"<string>\", \"<eof>\",\n+    \"<integer>\",\n+#ifdef LNUM_COMPLEX\n+    \"<number2>\",\n+#endif\n     NULL\n };\n \n@@ -90,7 +95,11 @@ static const char *txtToken (LexState *l\n   switch (token) {\n     case TK_NAME:\n     case TK_STRING:\n+    case TK_INT:\n     case TK_NUMBER:\n+#ifdef LNUM_COMPLEX\n+    case TK_NUMBER2:\n+#endif\n       save(ls, '\\0');\n       return luaZ_buffer(ls->buff);\n     default:\n@@ -175,23 +184,27 @@ static void buffreplace (LexState *ls, c\n     if (p[n] == from) p[n] = to;\n }\n \n-\n-static void trydecpoint (LexState *ls, SemInfo *seminfo) {\n+/* TK_NUMBER (/ TK_NUMBER2) */\n+static int trydecpoint (LexState *ls, SemInfo *seminfo) {\n   /* format error: try to update decimal point separator */\n   struct lconv *cv = localeconv();\n   char old = ls->decpoint;\n+  int ret;\n   ls->decpoint = (cv ? cv->decimal_point[0] : '.');\n   buffreplace(ls, old, ls->decpoint);  /* try updated decimal separator */\n-  if (!luaO_str2d(luaZ_buffer(ls->buff), &seminfo->r)) {\n+  ret= luaO_str2d(luaZ_buffer(ls->buff), &seminfo->r, NULL);\n+  if (!ret) {\n     /* format error with correct decimal point: no more options */\n     buffreplace(ls, ls->decpoint, '.');  /* undo change (for error message) */\n     luaX_lexerror(ls, \"malformed number\", TK_NUMBER);\n   }\n+  return ret;\n }\n \n \n-/* LUA_NUMBER */\n-static void read_numeral (LexState *ls, SemInfo *seminfo) {\n+/* TK_NUMBER / TK_INT (/TK_NUMBER2) */\n+static int read_numeral (LexState *ls, SemInfo *seminfo) {\n+  int ret;\n   lua_assert(isdigit(ls->current));\n   do {\n     save_and_next(ls);\n@@ -202,8 +215,9 @@ static void read_numeral (LexState *ls,\n     save_and_next(ls);\n   save(ls, '\\0');\n   buffreplace(ls, '.', ls->decpoint);  /* follow locale for decimal point */\n-  if (!luaO_str2d(luaZ_buffer(ls->buff), &seminfo->r))  /* format error? */\n-    trydecpoint(ls, seminfo); /* try to update decimal point separator */\n+  ret= luaO_str2d(luaZ_buffer(ls->buff), &seminfo->r, &seminfo->i );\n+  if (!ret) return trydecpoint(ls, seminfo); /* try to update decimal point separator */\n+  return ret;\n }\n \n \n@@ -331,6 +345,7 @@ static void read_string (LexState *ls, i\n }\n \n \n+/* char / TK_* */\n static int llex (LexState *ls, SemInfo *seminfo) {\n   luaZ_resetbuffer(ls->buff);\n   for (;;) {\n@@ -402,8 +417,7 @@ static int llex (LexState *ls, SemInfo *\n         }\n         else if (!isdigit(ls->current)) return '.';\n         else {\n-          read_numeral(ls, seminfo);\n-          return TK_NUMBER;\n+          return read_numeral(ls, seminfo);\n         }\n       }\n       case EOZ: {\n@@ -416,8 +430,7 @@ static int llex (LexState *ls, SemInfo *\n           continue;\n         }\n         else if (isdigit(ls->current)) {\n-          read_numeral(ls, seminfo);\n-          return TK_NUMBER;\n+          return read_numeral(ls, seminfo);\n         }\n         else if (isalpha(ls->current) || ls->current == '_') {\n           /* identifier or reserved word */\n--- a/src/llex.h\n+++ b/src/llex.h\n@@ -29,19 +29,22 @@ enum RESERVED {\n   TK_RETURN, TK_THEN, TK_TRUE, TK_UNTIL, TK_WHILE,\n   /* other terminal symbols */\n   TK_CONCAT, TK_DOTS, TK_EQ, TK_GE, TK_LE, TK_NE, TK_NUMBER,\n-  TK_NAME, TK_STRING, TK_EOS\n+  TK_NAME, TK_STRING, TK_EOS, TK_INT\n+#ifdef LNUM_COMPLEX\n+  , TK_NUMBER2   /* imaginary constants: Ni */ \n+#endif\n };\n \n /* number of reserved words */\n #define NUM_RESERVED\t(cast(int, TK_WHILE-FIRST_RESERVED+1))\n \n \n-/* array with token `names' */\n-LUAI_DATA const char *const luaX_tokens [];\n-\n-\n+/* SemInfo is a local data structure of 'llex.c', used for carrying a string\n+ * or a number. A separate token (TK_*) will tell, how to interpret the data.\n+ */      \n typedef union {\n   lua_Number r;\n+  lua_Integer i;\n   TString *ts;\n } SemInfo;  /* semantics information */\n \n--- a/src/llimits.h\n+++ b/src/llimits.h\n@@ -49,6 +49,7 @@ typedef LUAI_USER_ALIGNMENT_T L_Umaxalig\n \n /* result of a `usual argument conversion' over lua_Number */\n typedef LUAI_UACNUMBER l_uacNumber;\n+typedef LUAI_UACINTEGER l_uacInteger;\n \n \n /* internal assertions for in-house debugging */\n@@ -80,7 +81,6 @@ typedef LUAI_UACNUMBER l_uacNumber;\n #define cast_int(i)\tcast(int, (i))\n \n \n-\n /*\n ** type for virtual-machine instructions\n ** must be an unsigned with (at least) 4 bytes (see details in lopcodes.h)\n--- a/src/lmathlib.c\n+++ b/src/lmathlib.c\n@@ -4,7 +4,6 @@\n ** See Copyright Notice in lua.h\n */\n \n-\n #include <stdlib.h>\n #include <math.h>\n \n@@ -16,113 +15,210 @@\n #include \"lauxlib.h\"\n #include \"lualib.h\"\n \n+/* 'luai_vectpow()' as a replacement for 'cpow()'. Defined in the header; we\n+ * don't intrude the code libs internal functions.\n+ */\n+#ifdef LNUM_COMPLEX\n+# include \"lnum.h\"    \n+#endif\n \n #undef PI\n-#define PI (3.14159265358979323846)\n-#define RADIANS_PER_DEGREE (PI/180.0)\n-\n-\n+#ifdef LNUM_FLOAT\n+# define PI (3.14159265358979323846F)\n+#elif defined(M_PI)\n+# define PI M_PI\n+#else\n+# define PI (3.14159265358979323846264338327950288)\n+#endif\n+#define RADIANS_PER_DEGREE (PI/180)\n+\n+#undef HUGE\n+#ifdef LNUM_FLOAT\n+# define HUGE HUGE_VALF\n+#elif defined(LNUM_LDOUBLE)\n+# define HUGE HUGE_VALL\n+#else\n+# define HUGE HUGE_VAL\n+#endif\n \n static int math_abs (lua_State *L) {\n-  lua_pushnumber(L, fabs(luaL_checknumber(L, 1)));\n+#ifdef LNUM_COMPLEX\n+  lua_pushnumber(L, _LF(cabs) (luaL_checkcomplex(L,1)));\n+#else\n+  lua_pushnumber(L, _LF(fabs) (luaL_checknumber(L, 1)));\n+#endif\n   return 1;\n }\n \n static int math_sin (lua_State *L) {\n-  lua_pushnumber(L, sin(luaL_checknumber(L, 1)));\n+#ifdef LNUM_COMPLEX\n+  lua_pushcomplex(L, _LF(csin) (luaL_checkcomplex(L,1)));\n+#else\n+  lua_pushnumber(L, _LF(sin) (luaL_checknumber(L, 1)));\n+#endif\n   return 1;\n }\n \n static int math_sinh (lua_State *L) {\n-  lua_pushnumber(L, sinh(luaL_checknumber(L, 1)));\n+#ifdef LNUM_COMPLEX\n+  lua_pushcomplex(L, _LF(csinh) (luaL_checkcomplex(L,1)));\n+#else\n+  lua_pushnumber(L, _LF(sinh) (luaL_checknumber(L, 1)));\n+#endif\n   return 1;\n }\n \n static int math_cos (lua_State *L) {\n-  lua_pushnumber(L, cos(luaL_checknumber(L, 1)));\n+#ifdef LNUM_COMPLEX\n+  lua_pushcomplex(L, _LF(ccos) (luaL_checkcomplex(L,1)));\n+#else\n+  lua_pushnumber(L, _LF(cos) (luaL_checknumber(L, 1)));\n+#endif\n   return 1;\n }\n \n static int math_cosh (lua_State *L) {\n-  lua_pushnumber(L, cosh(luaL_checknumber(L, 1)));\n+#ifdef LNUM_COMPLEX\n+  lua_pushcomplex(L, _LF(ccosh) (luaL_checkcomplex(L,1)));\n+#else\n+  lua_pushnumber(L, _LF(cosh) (luaL_checknumber(L, 1)));\n+#endif\n   return 1;\n }\n \n static int math_tan (lua_State *L) {\n-  lua_pushnumber(L, tan(luaL_checknumber(L, 1)));\n+#ifdef LNUM_COMPLEX\n+  lua_pushcomplex(L, _LF(ctan) (luaL_checkcomplex(L,1)));\n+#else\n+  lua_pushnumber(L, _LF(tan) (luaL_checknumber(L, 1)));\n+#endif\n   return 1;\n }\n \n static int math_tanh (lua_State *L) {\n-  lua_pushnumber(L, tanh(luaL_checknumber(L, 1)));\n+#ifdef LNUM_COMPLEX\n+  lua_pushcomplex(L, _LF(ctanh) (luaL_checkcomplex(L,1)));\n+#else\n+  lua_pushnumber(L, _LF(tanh) (luaL_checknumber(L, 1)));\n+#endif\n   return 1;\n }\n \n static int math_asin (lua_State *L) {\n-  lua_pushnumber(L, asin(luaL_checknumber(L, 1)));\n+#ifdef LNUM_COMPLEX\n+  lua_pushcomplex(L, _LF(casin) (luaL_checkcomplex(L,1)));\n+#else\n+  lua_pushnumber(L, _LF(asin) (luaL_checknumber(L, 1)));\n+#endif\n   return 1;\n }\n \n static int math_acos (lua_State *L) {\n-  lua_pushnumber(L, acos(luaL_checknumber(L, 1)));\n+#ifdef LNUM_COMPLEX\n+  lua_pushcomplex(L, _LF(cacos) (luaL_checkcomplex(L,1)));\n+#else\n+  lua_pushnumber(L, _LF(acos) (luaL_checknumber(L, 1)));\n+#endif\n   return 1;\n }\n \n static int math_atan (lua_State *L) {\n-  lua_pushnumber(L, atan(luaL_checknumber(L, 1)));\n+#ifdef LNUM_COMPLEX\n+  lua_pushcomplex(L, _LF(catan) (luaL_checkcomplex(L,1)));\n+#else\n+  lua_pushnumber(L, _LF(atan) (luaL_checknumber(L, 1)));\n+#endif\n   return 1;\n }\n \n static int math_atan2 (lua_State *L) {\n-  lua_pushnumber(L, atan2(luaL_checknumber(L, 1), luaL_checknumber(L, 2)));\n+  /* scalars only */\n+  lua_pushnumber(L, _LF(atan2) (luaL_checknumber(L, 1), luaL_checknumber(L, 2)));\n   return 1;\n }\n \n static int math_ceil (lua_State *L) {\n-  lua_pushnumber(L, ceil(luaL_checknumber(L, 1)));\n+#ifdef LNUM_COMPLEX\n+  lua_Complex v= luaL_checkcomplex(L, 1);\n+  lua_pushcomplex(L, _LF(ceil) (_LF(creal)(v)) + _LF(ceil) (_LF(cimag)(v))*I);\n+#else\n+  lua_pushnumber(L, _LF(ceil) (luaL_checknumber(L, 1)));\n+#endif\n   return 1;\n }\n \n static int math_floor (lua_State *L) {\n-  lua_pushnumber(L, floor(luaL_checknumber(L, 1)));\n+#ifdef LNUM_COMPLEX\n+  lua_Complex v= luaL_checkcomplex(L, 1);\n+  lua_pushcomplex(L, _LF(floor) (_LF(creal)(v)) + _LF(floor) (_LF(cimag)(v))*I);\n+#else\n+  lua_pushnumber(L, _LF(floor) (luaL_checknumber(L, 1)));\n+#endif\n   return 1;\n }\n \n-static int math_fmod (lua_State *L) {\n-  lua_pushnumber(L, fmod(luaL_checknumber(L, 1), luaL_checknumber(L, 2)));\n+static int math_fmod (lua_State *L) {  \n+  /* scalars only */\n+  lua_pushnumber(L, _LF(fmod) (luaL_checknumber(L, 1), luaL_checknumber(L, 2)));\n   return 1;\n }\n \n static int math_modf (lua_State *L) {\n-  double ip;\n-  double fp = modf(luaL_checknumber(L, 1), &ip);\n+  /* scalars only */\n+  lua_Number ip;\n+  lua_Number fp = _LF(modf) (luaL_checknumber(L, 1), &ip);\n   lua_pushnumber(L, ip);\n   lua_pushnumber(L, fp);\n   return 2;\n }\n \n static int math_sqrt (lua_State *L) {\n-  lua_pushnumber(L, sqrt(luaL_checknumber(L, 1)));\n+#ifdef LNUM_COMPLEX\n+  lua_pushcomplex(L, _LF(csqrt) (luaL_checkcomplex(L,1)));\n+#else\n+  lua_pushnumber(L, _LF(sqrt) (luaL_checknumber(L, 1)));\n+#endif\n   return 1;\n }\n \n static int math_pow (lua_State *L) {\n-  lua_pushnumber(L, pow(luaL_checknumber(L, 1), luaL_checknumber(L, 2)));\n+#ifdef LNUM_COMPLEX\n+  /* C99 'cpow' gives somewhat inaccurate results (i.e. (-1)^2 = -1+1.2246467991474e-16i). \n+  * 'luai_vectpow' smoothens such, reusing it is the reason we need to #include \"lnum.h\".\n+  */\n+  lua_pushcomplex(L, luai_vectpow(luaL_checkcomplex(L,1), luaL_checkcomplex(L,2)));\n+#else\n+  lua_pushnumber(L, _LF(pow) (luaL_checknumber(L, 1), luaL_checknumber(L, 2)));\n+#endif\n   return 1;\n }\n \n static int math_log (lua_State *L) {\n-  lua_pushnumber(L, log(luaL_checknumber(L, 1)));\n+#ifdef LNUM_COMPLEX\n+  lua_pushcomplex(L, _LF(clog) (luaL_checkcomplex(L,1)));\n+#else\n+  lua_pushnumber(L, _LF(log) (luaL_checknumber(L, 1)));\n+#endif\n   return 1;\n }\n \n static int math_log10 (lua_State *L) {\n-  lua_pushnumber(L, log10(luaL_checknumber(L, 1)));\n+#ifdef LNUM_COMPLEX\n+  /* Not in standard <complex.h> , but easy to calculate: log_a(x) = log_b(x) / log_b(a) \n+  */\n+  lua_pushcomplex(L, _LF(clog) (luaL_checkcomplex(L,1)) / _LF(log) (10));\n+#else\n+  lua_pushnumber(L, _LF(log10) (luaL_checknumber(L, 1)));\n+#endif\n   return 1;\n }\n \n static int math_exp (lua_State *L) {\n-  lua_pushnumber(L, exp(luaL_checknumber(L, 1)));\n+#ifdef LNUM_COMPLEX\n+  lua_pushcomplex(L, _LF(cexp) (luaL_checkcomplex(L,1)));\n+#else\n+  lua_pushnumber(L, _LF(exp) (luaL_checknumber(L, 1)));\n+#endif\n   return 1;\n }\n \n@@ -138,19 +234,20 @@ static int math_rad (lua_State *L) {\n \n static int math_frexp (lua_State *L) {\n   int e;\n-  lua_pushnumber(L, frexp(luaL_checknumber(L, 1), &e));\n+  lua_pushnumber(L, _LF(frexp) (luaL_checknumber(L, 1), &e));\n   lua_pushinteger(L, e);\n   return 2;\n }\n \n static int math_ldexp (lua_State *L) {\n-  lua_pushnumber(L, ldexp(luaL_checknumber(L, 1), luaL_checkint(L, 2)));\n+  lua_pushnumber(L, _LF(ldexp) (luaL_checknumber(L, 1), luaL_checkint(L, 2)));\n   return 1;\n }\n \n \n \n static int math_min (lua_State *L) {\n+  /* scalars only */\n   int n = lua_gettop(L);  /* number of arguments */\n   lua_Number dmin = luaL_checknumber(L, 1);\n   int i;\n@@ -165,6 +262,7 @@ static int math_min (lua_State *L) {\n \n \n static int math_max (lua_State *L) {\n+  /* scalars only */\n   int n = lua_gettop(L);  /* number of arguments */\n   lua_Number dmax = luaL_checknumber(L, 1);\n   int i;\n@@ -182,25 +280,20 @@ static int math_random (lua_State *L) {\n   /* the `%' avoids the (rare) case of r==1, and is needed also because on\n      some systems (SunOS!) `rand()' may return a value larger than RAND_MAX */\n   lua_Number r = (lua_Number)(rand()%RAND_MAX) / (lua_Number)RAND_MAX;\n-  switch (lua_gettop(L)) {  /* check number of arguments */\n-    case 0: {  /* no arguments */\n-      lua_pushnumber(L, r);  /* Number between 0 and 1 */\n-      break;\n-    }\n-    case 1: {  /* only upper limit */\n-      int u = luaL_checkint(L, 1);\n-      luaL_argcheck(L, 1<=u, 1, \"interval is empty\");\n-      lua_pushnumber(L, floor(r*u)+1);  /* int between 1 and `u' */\n-      break;\n-    }\n-    case 2: {  /* lower and upper limits */\n-      int l = luaL_checkint(L, 1);\n-      int u = luaL_checkint(L, 2);\n-      luaL_argcheck(L, l<=u, 2, \"interval is empty\");\n-      lua_pushnumber(L, floor(r*(u-l+1))+l);  /* int between `l' and `u' */\n-      break;\n-    }\n-    default: return luaL_error(L, \"wrong number of arguments\");\n+  int n= lua_gettop(L);  /* number of arguments */\n+  if (n==0) {\t/* no arguments: range [0,1) */\n+    lua_pushnumber(L, r);\n+  } else if (n<=2) {\t/* int range [1,u] or [l,u] */\n+    int l= n==1 ? 1 : luaL_checkint(L, 1);\n+    int u = luaL_checkint(L, n);\n+    int tmp;\n+    lua_Number d;\n+    luaL_argcheck(L, l<=u, n, \"interval is empty\");\n+    d= _LF(floor)(r*(u-l+1));\n+    lua_number2int(tmp,d);\n+    lua_pushinteger(L, l+tmp);\n+  } else {\n+    return luaL_error(L, \"wrong number of arguments\");\n   }\n   return 1;\n }\n@@ -211,6 +304,66 @@ static int math_randomseed (lua_State *L\n   return 0;\n }\n \n+/* \n+* Lua 5.1 does not have acosh, asinh, atanh for scalars (not ANSI C)\n+*/\n+#if __STDC_VERSION__ >= 199901L\n+static int math_acosh (lua_State *L) {\n+# ifdef LNUM_COMPLEX\n+  lua_pushcomplex(L, _LF(cacosh) (luaL_checkcomplex(L,1)));\n+# else\n+  lua_pushnumber(L, _LF(acosh) (luaL_checknumber(L,1)));\n+# endif\n+  return 1;\n+}\n+static int math_asinh (lua_State *L) {\n+# ifdef LNUM_COMPLEX\n+  lua_pushcomplex(L, _LF(casinh) (luaL_checkcomplex(L,1)));\n+# else\n+  lua_pushnumber(L, _LF(asinh) (luaL_checknumber(L,1)));\n+# endif\n+  return 1;\n+}\n+static int math_atanh (lua_State *L) {\n+# ifdef LNUM_COMPLEX\n+  lua_pushcomplex(L, _LF(catanh) (luaL_checkcomplex(L,1)));\n+# else\n+  lua_pushnumber(L, _LF(atanh) (luaL_checknumber(L,1)));\n+# endif\n+  return 1;\n+}\n+#endif\n+\n+/* \n+ * C99 complex functions, not covered above.\n+*/\n+#ifdef LNUM_COMPLEX\n+static int math_arg (lua_State *L) {\n+  lua_pushnumber(L, _LF(carg) (luaL_checkcomplex(L,1)));\n+  return 1;\n+}\n+\n+static int math_imag (lua_State *L) {\n+  lua_pushnumber(L, _LF(cimag) (luaL_checkcomplex(L,1)));\n+  return 1;\n+}\n+\n+static int math_real (lua_State *L) {\n+  lua_pushnumber(L, _LF(creal) (luaL_checkcomplex(L,1)));\n+  return 1;\n+}\n+\n+static int math_conj (lua_State *L) {\n+  lua_pushcomplex(L, _LF(conj) (luaL_checkcomplex(L,1)));\n+  return 1;\n+}\n+\n+static int math_proj (lua_State *L) {\n+  lua_pushcomplex(L, _LF(cproj) (luaL_checkcomplex(L,1)));\n+  return 1;\n+}\n+#endif\n+\n \n static const luaL_Reg mathlib[] = {\n   {\"abs\",   math_abs},\n@@ -241,6 +394,18 @@ static const luaL_Reg mathlib[] = {\n   {\"sqrt\",  math_sqrt},\n   {\"tanh\",   math_tanh},\n   {\"tan\",   math_tan},\n+#if __STDC_VERSION__ >= 199901L\n+  {\"acosh\",  math_acosh},\n+  {\"asinh\",  math_asinh},\n+  {\"atanh\",  math_atanh},\n+#endif\n+#ifdef LNUM_COMPLEX\n+  {\"arg\",   math_arg},\n+  {\"imag\",  math_imag},\n+  {\"real\",  math_real},\n+  {\"conj\",  math_conj},\n+  {\"proj\",  math_proj},\n+#endif\n   {NULL, NULL}\n };\n \n@@ -252,8 +417,10 @@ LUALIB_API int luaopen_math (lua_State *\n   luaL_register(L, LUA_MATHLIBNAME, mathlib);\n   lua_pushnumber(L, PI);\n   lua_setfield(L, -2, \"pi\");\n-  lua_pushnumber(L, HUGE_VAL);\n+  lua_pushnumber(L, HUGE);\n   lua_setfield(L, -2, \"huge\");\n+  lua_pushinteger(L, LUA_INTEGER_MAX );\n+  lua_setfield(L, -2, \"hugeint\");\n #if defined(LUA_COMPAT_MOD)\n   lua_getfield(L, -1, \"fmod\");\n   lua_setfield(L, -2, \"mod\");\n--- /dev/null\n+++ b/src/lnum.c\n@@ -0,0 +1,312 @@\n+/*\n+** $Id: lnum.c,v ... $\n+** Internal number model\n+** See Copyright Notice in lua.h\n+*/\n+\n+#include <stdlib.h>\n+#include <math.h>\n+#include <ctype.h>\n+#include <string.h>\n+#include <stdio.h>\n+#include <errno.h>\n+\n+#define lnum_c\n+#define LUA_CORE\n+\n+#include \"lua.h\"\n+#include \"llex.h\"\n+#include \"lnum.h\"\n+\n+/*\n+** lua_real2str converts a (non-complex) number to a string.\n+** lua_str2real converts a string to a (non-complex) number.\n+*/\n+#define lua_real2str(s,n)  sprintf((s), LUA_NUMBER_FMT, (n))\n+\n+/*\n+* Note: Only 'strtod()' is part of ANSI C; others are C99 and\n+* may need '--std=c99' compiler setting (at least on Ubuntu 7.10).\n+* \n+* Visual C++ 2008 Express does not have 'strtof()', nor 'strtold()'.\n+* References to '_strtold()' exist but don't compile. It seems best\n+* to leave Windows users with DOUBLE only (or compile with MinGW).\n+*\n+* In practise, using '(long double)strtod' is a risky thing, since\n+* it will cause accuracy loss in reading in numbers, and such losses\n+* will pile up in later processing. Get a real 'strtold()' or don't\n+* use that mode at all.\n+*/\n+#ifdef LNUM_DOUBLE\n+# define lua_str2real\tstrtod\n+#elif defined(LNUM_FLOAT)\n+# define lua_str2real\tstrtof\n+#elif defined(LNUM_LDOUBLE)\n+# define lua_str2real\tstrtold\n+#endif\n+\n+#define lua_integer2str(s,v) sprintf((s), LUA_INTEGER_FMT, (v))\n+\n+/* 's' is expected to be LUAI_MAXNUMBER2STR long (enough for any number)\n+*/\n+void luaO_num2buf( char *s, const TValue *o )\n+{\n+  lua_Number n;\n+  lua_assert( ttisnumber(o) );\n+\n+  /* Reason to handle integers differently is not only speed, but accuracy as\n+   * well. We want to make any integer tostring() without roundings, at all.\n+   */\n+  if (ttisint(o)) {\n+    lua_integer2str( s, ivalue(o) );\n+    return;\n+  }\n+  n= nvalue_fast(o);\n+  lua_real2str(s, n);\n+\n+#ifdef LNUM_COMPLEX\n+  lua_Number n2= nvalue_img_fast(o);\n+  if (n2!=0) {   /* Postfix with +-Ni */\n+      int re0= (n == 0);\n+      char *s2= re0 ? s : strchr(s,'\\0'); \n+      if ((!re0) && (n2>0)) *s2++= '+';\n+      lua_real2str( s2, n2 );\n+      strcat(s2,\"i\");\n+  }\n+#endif\n+}\n+\n+/*\n+* If a LUA_TNUMBER has integer value, give it.\n+*/\n+int /*bool*/ tt_integer_valued( const TValue *o, lua_Integer *ref ) {\n+  lua_Number d;\n+  lua_Integer i;\n+\n+  lua_assert( ttype(o)==LUA_TNUMBER );\n+  lua_assert( ref );\n+#ifdef LNUM_COMPLEX\n+  if (nvalue_img_fast(o)!=0) return 0;\n+#endif\n+  d= nvalue_fast(o);\n+  lua_number2integer(i, d);\n+  if (cast_num(i) == d) {\n+    *ref= i; return 1;\n+  }\n+  return 0;\n+}\n+\n+/* \n+ * Lua 5.1.3 (using 'strtod()') allows 0x+hex but not 0+octal. This is good,\n+ * and we should NOT use 'autobase' 0 with 'strtoul[l]()' for this reason.\n+ *\n+ * Lua 5.1.3 allows '0x...' numbers to overflow and lose precision; this is not\n+ * good. On Visual C++ 2008, 'strtod()' does not even take them in. Better to\n+ * require hex values to fit 'lua_Integer' or give an error that they don't?\n+ *\n+ * Full hex range (0 .. 0xff..ff) is stored as integers, not to lose any bits.\n+ * Numerical value of 0xff..ff will be -1, if used in calculations.\n+ * \n+ * Returns: TK_INT for a valid integer, '*endptr_ref' updated\n+ *          TK_NUMBER for seemingly numeric, to be parsed as floating point\n+ *          0 for bad characters, not a number (or '0x' out of range)\n+ */\n+static int luaO_str2i (const char *s, lua_Integer *res, char **endptr_ref) {\n+  char *endptr;\n+  /* 'v' gets ULONG_MAX on possible overflow (which is > LUA_INTEGER_MAX);\n+   * we don't have to check 'errno' here.\n+   */\n+  unsigned LUA_INTEGER v= lua_str2ul(s, &endptr, 10);\n+  if (endptr == s) return 0;  /* nothing numeric */\n+  if (v==0 && *endptr=='x') {\n+    errno= 0;   /* needs to be set, 'strtoul[l]' does not clear it */\n+    v= lua_str2ul(endptr+1, &endptr, 16);  /* retry as hex, unsigned range */\n+    if (errno==ERANGE) {   /* clamped to 0xff..ff */\n+#if (defined(LNUM_INT32) && !defined(LNUM_FLOAT)) || defined(LNUM_LDOUBLE)\n+      return TK_NUMBER; /* Allow to be read as floating point (has more integer range) */\n+#else\n+      return 0;  /* Reject the number */\n+#endif\n+    }\n+  } else if ((v > LUA_INTEGER_MAX) || (*endptr && (!isspace(*endptr)))) {\n+    return TK_NUMBER;\t/* not in signed range, or has '.', 'e' etc. trailing */\n+  }\n+  *res= (lua_Integer)v;\n+  *endptr_ref= endptr;\n+  return TK_INT;\n+}\n+\n+/* 0 / TK_NUMBER / TK_INT (/ TK_NUMBER2) */\n+int luaO_str2d (const char *s, lua_Number *res_n, lua_Integer *res_i) {\n+  char *endptr;\n+  int ret= TK_NUMBER;\n+  /* Check integers first, if caller is allowing. \n+   * If 'res2'==NULL, they're only looking for floating point. \n+   */\n+  if (res_i) {\n+    ret= luaO_str2i(s,res_i,&endptr);\n+    if (ret==0) return 0;\n+  }\n+  if (ret==TK_NUMBER) {\n+    lua_assert(res_n);\n+    /* Note: Visual C++ 2008 Express 'strtod()' does not read in \"0x...\"\n+     *       numbers; it will read '0' and spit 'x' as endptr.\n+     *       This means hex constants not fitting in 'lua_Integer' won't \n+     *       be read in at all. What to do?\n+     */\n+    *res_n = lua_str2real(s, &endptr);\n+    if (endptr == s) return 0;  /* conversion failed */\n+    /* Visual C++ 2008 'strtod()' does not allow \"0x...\" input. */\n+#if defined(_MSC_VER) && !defined(LNUM_FLOAT) && !defined(LNUM_INT64)\n+    if (*res_n==0 && *endptr=='x') {\n+      /* Hex constant too big for 'lua_Integer' but that could fit in 'lua_Number'\n+       * integer bits \n+       */\n+      unsigned __int64 v= _strtoui64( s, &endptr, 16 );\n+      /* We just let > 64 bit values be clamped to _UI64_MAX (MSDN does not say 'errno'==ERANGE would be set) */\n+      *res_n= cast_num(v);\n+      if (*res_n != v) return 0;    /* Would have lost accuracy */\n+    }\n+#endif\n+#ifdef LNUM_COMPLEX\n+    if (*endptr == 'i') { endptr++; ret= TK_NUMBER2; }\n+#endif\n+  }\n+  if (*endptr) {\n+    while (isspace(cast(unsigned char, *endptr))) endptr++;\n+    if (*endptr) return 0;  /* invalid trail */\n+  }\n+  return ret;\n+}\n+\n+\n+/* Functions for finding out, when integer operations remain in range\n+ * (and doing them).\n+ */\n+int try_addint( lua_Integer *r, lua_Integer ib, lua_Integer ic ) {\n+  lua_Integer v= ib+ic; /* may overflow */\n+  if (ib>0 && ic>0)      { if (v < 0) return 0; /*overflow, use floats*/ }\n+  else if (ib<0 && ic<0) { if (v >= 0) return 0; }\n+  *r= v;\n+  return 1;\n+}\n+\n+int try_subint( lua_Integer *r, lua_Integer ib, lua_Integer ic ) {\n+  lua_Integer v= ib-ic; /* may overflow */\n+  if (ib>=0 && ic<0)     { if (v < 0) return 0; /*overflow, use floats*/ }\n+  else if (ib<0 && ic>0) { if (v >= 0) return 0; }\n+  *r= v;\n+  return 1;\n+}\n+\n+int try_mulint( lua_Integer *r, lua_Integer ib, lua_Integer ic ) {\n+  if (ib!=LUA_INTEGER_MIN && ic!=LUA_INTEGER_MIN) {\n+    lua_Integer b= luai_abs(ib), c= luai_abs(ic);\n+    if ( (ib==0) || (LUA_INTEGER_MAX/b >= c) ) {\n+      *r= ib*ic;  /* no overflow */\n+      return 1;\n+    }\n+  } else if (ib==0 || ic==0) {\n+    *r= 0; return 1;\n+  }\n+\n+  /* Result can be LUA_INTEGER_MIN; if it is, calculating it using floating \n+   * point will not cause accuracy loss.\n+   */\n+  if ( luai_nummul( cast_num(ib), cast_num(ic) ) == LUA_INTEGER_MIN ) {\n+    *r= LUA_INTEGER_MIN;\n+    return 1;\n+  }\n+  return 0;\n+}\n+\n+int try_divint( lua_Integer *r, lua_Integer ib, lua_Integer ic ) {\n+  /* N/0: leave to float side, to give an error\n+  */\n+  if (ic==0) return 0;\n+\n+  /* N/LUA_INTEGER_MIN: always non-integer results, or 0 or +1\n+  */\n+  if (ic==LUA_INTEGER_MIN) {\n+    if (ib==LUA_INTEGER_MIN) { *r=1; return 1; }\n+    if (ib==0) { *r=0; return 1; }\n+\n+  /* LUA_INTEGER_MIN (-2^31|63)/N: calculate using float side (either the division \n+   *    causes non-integer results, or there is no accuracy loss in int->fp->int\n+   *    conversions (N=2,4,8,..,256 and N=2^30,2^29,..2^23).\n+   */\n+  } else if (ib==LUA_INTEGER_MIN) {\n+    lua_Number d= luai_numdiv( cast_num(LUA_INTEGER_MIN), cast_num(ic) );\n+    lua_Integer i; lua_number2integer(i,d);\n+    if (cast_num(i)==d) { *r= i; return 1; }\n+  \n+  } else {\n+    /* Note: We _can_ use ANSI C mod here, even on negative values, since\n+     *       we only test for == 0 (the sign would be implementation dependent).\n+     */\n+     if (ib%ic == 0) { *r= ib/ic; return 1; }\n+  }\n+\n+  return 0;\n+}\n+\n+int try_modint( lua_Integer *r, lua_Integer ib, lua_Integer ic ) {\n+  if (ic!=0) {\n+    /* ANSI C can be trusted when b%c==0, or when values are non-negative. \n+     * b - (floor(b/c) * c)\n+     *   -->\n+     * + +: b - (b/c) * c (b % c can be used)\n+     * - -: b - (b/c) * c (b % c could work, but not defined by ANSI C)\n+     * 0 -: b - (b/c) * c (=0, b % c could work, but not defined by ANSI C)\n+     * - +: b - (b/c-1) * c (when b!=-c)\n+     * + -: b - (b/c-1) * c (when b!=-c)\n+     *\n+     * o MIN%MIN ends up 0, via overflow in calcs but that does not matter.\n+     * o MIN%MAX ends up MAX-1 (and other such numbers), also after overflow,\n+     *   but that does not matter, results do.\n+     */\n+    lua_Integer v= ib % ic;\n+    if ( v!=0 && (ib<0 || ic<0) ) {\n+      v= ib - ((ib/ic) - ((ib<=0 && ic<0) ? 0:1)) * ic;\n+    }      \n+    /* Result should always have same sign as 2nd argument. (PIL2) */\n+    lua_assert( (v<0) ? (ic<0) : (v>0) ? (ic>0) : 1 );\n+    *r= v;\n+    return 1;\n+  }\n+  return 0;  /* let float side return NaN */\n+}\n+\n+int try_powint( lua_Integer *r, lua_Integer ib, lua_Integer ic ) {\n+\n+    /* In FLOAT/INT32 or FLOAT|DOUBLE/INT64 modes, calculating integer powers \n+     * via FP realm may lose accuracy (i.e. 7^11 = 1977326743, which fits int32\n+     * but not 23-bit float mantissa). \n+     *\n+     * The current solution is dumb, but it works and uses little code. Use of\n+     * integer powers is not anticipated to be very frequent (apart from 2^x,\n+     * which is separately optimized).\n+     */\n+  if (ib==0) *r=0;\n+  else if (ic<0) return 0;  /* FP realm */\n+  else if (ib==2 && ic < (int)sizeof(lua_Integer)*8-1) *r= ((lua_Integer)1)<<ic;   /* 1,2,4,...2^30 | 2^62 optimization */\n+  else if (ic==0) *r=1;\n+  else if (luai_abs(ib)==1) *r= (ic%2) ? ib:1;\n+  else {\n+    lua_Integer x= ib;\n+    while( --ic ) {\n+      if (!try_mulint( &x, x, ib ))\n+        return 0; /* FP realm */\n+    }\n+    *r= x;\n+  }\n+  return 1;\n+}\n+\n+int try_unmint( lua_Integer *r, lua_Integer ib ) {\n+  /* Negating LUA_INTEGER_MIN leaves the range. */\n+  if ( ib != LUA_INTEGER_MIN )  \n+    { *r= -ib; return 1; }\n+  return 0;\n+}\n+\n--- /dev/null\n+++ b/src/lnum.h\n@@ -0,0 +1,116 @@\n+/*\n+** $Id: lnum.h,v ... $\n+** Internal Number model\n+** See Copyright Notice in lua.h\n+*/\n+\n+#ifndef lnum_h\n+#define lnum_h\n+\n+#include <math.h>\n+\n+#include \"lobject.h\"\n+\n+/*\n+** The luai_num* macros define the primitive operations over 'lua_Number's\n+** (not 'lua_Integer's, not 'lua_Complex').\n+*/\n+#define luai_numadd(a,b)\t((a)+(b))\n+#define luai_numsub(a,b)\t((a)-(b))\n+#define luai_nummul(a,b)\t((a)*(b))\n+#define luai_numdiv(a,b)\t((a)/(b))\n+#define luai_nummod(a,b)\t((a) - _LF(floor)((a)/(b))*(b))\n+#define luai_numpow(a,b)\t(_LF(pow)(a,b))\n+#define luai_numunm(a)\t\t(-(a))\n+#define luai_numeq(a,b)\t    ((a)==(b))\n+#define luai_numlt(a,b)\t    ((a)<(b))\n+#define luai_numle(a,b)\t    ((a)<=(b))\n+#define luai_numisnan(a)\t(!luai_numeq((a), (a)))\n+\n+int try_addint( lua_Integer *r, lua_Integer ib, lua_Integer ic );\n+int try_subint( lua_Integer *r, lua_Integer ib, lua_Integer ic );\n+int try_mulint( lua_Integer *r, lua_Integer ib, lua_Integer ic );\n+int try_divint( lua_Integer *r, lua_Integer ib, lua_Integer ic );\n+int try_modint( lua_Integer *r, lua_Integer ib, lua_Integer ic );\n+int try_powint( lua_Integer *r, lua_Integer ib, lua_Integer ic );\n+int try_unmint( lua_Integer *r, lua_Integer ib );\n+\n+#ifdef LNUM_COMPLEX\n+  static inline lua_Complex luai_vectunm( lua_Complex a ) { return -a; }\n+  static inline lua_Complex luai_vectadd( lua_Complex a, lua_Complex b ) { return a+b; }\n+  static inline lua_Complex luai_vectsub( lua_Complex a, lua_Complex b ) { return a-b; }\n+  static inline lua_Complex luai_vectmul( lua_Complex a, lua_Complex b ) { return a*b; }\n+  static inline lua_Complex luai_vectdiv( lua_Complex a, lua_Complex b ) { return a/b; }\n+\n+/* \n+ * C99 does not provide modulus for complex numbers. It most likely is not\n+ * meaningful at all.\n+ */\n+\n+/* \n+ * Complex power\n+ *\n+ * C99 'cpow' gives inaccurate results for many common cases s.a. (1i)^2 -> \n+ * -1+1.2246467991474e-16i (OS X 10.4, gcc 4.0.1 build 5367)\n+ * \n+ * [(a+bi)^(c+di)] = (r^c) * exp(-d*t) * cos(c*t + d*ln(r)) +\n+ *                 = (r^c) * exp(-d*t) * sin(c*t + d*ln(r)) *i\n+ * r = sqrt(a^2+b^2), t = arctan( b/a )\n+ * \n+ * Reference: <http://home.att.net/~srschmitt/complexnumbers.html>\n+ * Could also be calculated using: x^y = exp(ln(x)*y)\n+ *\n+ * Note: Defined here (and not in .c) so 'lmathlib.c' can share the \n+ *       implementation.\n+ */\n+  static inline\n+  lua_Complex luai_vectpow( lua_Complex a, lua_Complex b )\n+  {\n+# if 1\n+    lua_Number ar= _LF(creal)(a), ai= _LF(cimag)(a);\n+    lua_Number br= _LF(creal)(b), bi= _LF(cimag)(b);\n+    \n+    if (ai==0 && bi==0) {     /* a^c (real) */\n+        return luai_numpow( ar, br );\n+    } \n+\n+    int br_int= (int)br;\n+    \n+    if ( ai!=0 && bi==0 && br_int==br && br_int!=0 && br_int!=INT_MIN ) { \n+        /* (a+bi)^N, N = { +-1,+-2, ... +-INT_MAX } \n+        */\n+        lua_Number k= luai_numpow( _LF(sqrt) (ar*ar + ai*ai), br );\n+        lua_Number cos_z, sin_z;\n+\n+        /* Situation depends upon c (N) in the following manner:\n+         * \n+         * N%4==0                                => cos(c*t)=1, sin(c*t)=0\n+         * (N*sign(b))%4==1 or (N*sign(b))%4==-3 => cos(c*t)=0, sin(c*t)=1\n+         * N%4==2 or N%4==-2                     => cos(c*t)=-1, sin(c*t)=0\n+         * (N*sign(b))%4==-1 or (N*sign(b))%4==3 => cos(c*t)=0, sin(c*t)=-1\n+         */\n+      int br_int_abs = br_int<0 ? -br_int:br_int;\n+      \n+      switch( (br_int_abs%4) * (br_int<0 ? -1:1) * (ai<0 ? -1:1) ) {\n+        case 0:             cos_z=1, sin_z=0; break;\n+        case 2: case -2:    cos_z=-1, sin_z=0; break;\n+        case 1: case -3:    cos_z=0, sin_z=1; break;\n+        case 3: case -1:    cos_z=0, sin_z=-1; break;\n+        default:            lua_assert(0); return 0;\n+      }\n+      return k*cos_z + (k*sin_z)*I;\n+    }\n+# endif\n+    return _LF(cpow) ( a, b );\n+  }\n+#endif\n+\n+LUAI_FUNC int luaO_str2d (const char *s, lua_Number *res1, lua_Integer *res2);\n+LUAI_FUNC void luaO_num2buf( char *s, const TValue *o );\n+\n+LUAI_FUNC int /*bool*/ tt_integer_valued( const TValue *o, lua_Integer *ref );\n+\n+#define luai_normalize(o) \\\n+{ lua_Integer _i; if (tt_integer_valued(o,&_i)) setivalue(o,_i); }\n+\n+#endif\n--- /dev/null\n+++ b/src/lnum_config.h\n@@ -0,0 +1,221 @@\n+/*\n+** $Id: lnum_config.h,v ... $\n+** Internal Number model\n+** See Copyright Notice in lua.h\n+*/\n+\n+#ifndef lnum_config_h\n+#define lnum_config_h\n+\n+/*\n+** Default number modes\n+*/\n+#if (!defined LNUM_DOUBLE) && (!defined LNUM_FLOAT) && (!defined LNUM_LDOUBLE)\n+# define LNUM_FLOAT\n+#endif\n+#if (!defined LNUM_INT16) && (!defined LNUM_INT32) && (!defined LNUM_INT64)\n+# define LNUM_INT32\n+#endif\n+\n+/*\n+** Require C99 mode for COMPLEX, FLOAT and LDOUBLE (only DOUBLE is ANSI C).\n+*/\n+#if defined(LNUM_COMPLEX) && (__STDC_VERSION__ < 199901L)\n+# error \"Need C99 for complex (use '--std=c99' or similar)\"\n+#elif defined(LNUM_LDOUBLE) && (__STDC_VERSION__ < 199901L) && !defined(_MSC_VER)\n+# error \"Need C99 for 'long double' (use '--std=c99' or similar)\"\n+#elif defined(LNUM_FLOAT) && (__STDC_VERSION__ < 199901L)\n+/* LNUM_FLOAT not supported on Windows */\n+# error \"Need C99 for 'float' (use '--std=c99' or similar)\"\n+#endif\n+ \n+/*\n+** Number mode identifier to accompany the version string.\n+*/\n+#ifdef LNUM_COMPLEX\n+# define _LNUM1 \"complex \"\n+#else\n+# define _LNUM1 \"\"\n+#endif\n+#ifdef LNUM_DOUBLE\n+# define _LNUM2 \"double\"\n+#elif defined(LNUM_FLOAT)\n+# define _LNUM2 \"float\"\n+#elif defined(LNUM_LDOUBLE)\n+# define _LNUM2 \"ldouble\"\n+#endif\n+#ifdef LNUM_INT32\n+# define _LNUM3 \"int32\"\n+#elif defined(LNUM_INT64)\n+# define _LNUM3 \"int64\"\n+#elif defined(LNUM_INT16)\n+# define _LNUM3 \"int16\"\n+#endif\n+#define LUA_LNUM _LNUM1 _LNUM2 \" \" _LNUM3\n+\n+/*\n+** LUA_NUMBER is the type of floating point number in Lua\n+** LUA_NUMBER_SCAN is the format for reading numbers.\n+** LUA_NUMBER_FMT is the format for writing numbers.\n+*/\n+#ifdef LNUM_FLOAT\n+# define LUA_NUMBER         float\n+# define LUA_NUMBER_SCAN    \"%f\"\n+# define LUA_NUMBER_FMT     \"%g\"  \n+#elif (defined LNUM_DOUBLE)\n+# define LUA_NUMBER\t        double\n+# define LUA_NUMBER_SCAN    \"%lf\"\n+# define LUA_NUMBER_FMT     \"%.14g\"\n+#elif (defined LNUM_LDOUBLE)\n+# define LUA_NUMBER         long double\n+# define LUA_NUMBER_SCAN    \"%Lg\"\n+# define LUA_NUMBER_FMT     \"%.20Lg\"\n+#endif\n+\n+\n+/* \n+** LUAI_MAXNUMBER2STR: size of a buffer fitting any number->string result.\n+**\n+**  double:  24 (sign, x.xxxxxxxxxxxxxxe+nnnn, and \\0)\n+**  int64:   21 (19 digits, sign, and \\0)\n+**  long double: 43 for 128-bit (sign, x.xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxe+nnnn, and \\0)\n+**           30 for 80-bit (sign, x.xxxxxxxxxxxxxxxxxxxxe+nnnn, and \\0)\n+*/\n+#ifdef LNUM_LDOUBLE\n+# define _LUAI_MN2S 44\n+#else\n+# define _LUAI_MN2S 24\n+#endif\n+\n+#ifdef LNUM_COMPLEX\n+# define LUAI_MAXNUMBER2STR (2*_LUAI_MN2S)\n+#else\n+# define LUAI_MAXNUMBER2STR _LUAI_MN2S\n+#endif\n+\n+/*\n+** LUA_INTEGER is the integer type used by lua_pushinteger/lua_tointeger/lua_isinteger.\n+** LUA_INTEGER_SCAN is the format for reading integers\n+** LUA_INTEGER_FMT is the format for writing integers\n+**\n+** Note: Visual C++ 2005 does not have 'strtoull()', use '_strtoui64()' instead.\n+*/\n+#ifdef LNUM_INT32\n+# if LUAI_BITSINT > 16\n+#  define LUA_INTEGER   int\n+#  define LUA_INTEGER_SCAN \"%d\"\n+#  define LUA_INTEGER_FMT \"%d\"\n+# else\n+/* Note: 'LUA_INTEGER' being 'ptrdiff_t' (as in Lua 5.1) causes problems with\n+ *       'printf()' operations. Also 'unsigned ptrdiff_t' is invalid.\n+ */\n+#  define LUA_INTEGER   long\n+#  define LUA_INTEGER_SCAN \"%ld\"\n+#  define LUA_INTEGER_FMT \"%ld\"\n+# endif\n+# define LUA_INTEGER_MAX 0x7FFFFFFF             /* 2^31-1 */\n+/* */\n+#elif defined(LNUM_INT64)\n+# define LUA_INTEGER\tlong long\n+# ifdef _MSC_VER\n+#  define lua_str2ul    _strtoui64\n+# else\n+#  define lua_str2ul    strtoull\n+# endif\n+# define LUA_INTEGER_SCAN \"%lld\"\n+# define LUA_INTEGER_FMT \"%lld\"\n+# define LUA_INTEGER_MAX 0x7fffffffffffffffLL       /* 2^63-1 */ \n+# define LUA_INTEGER_MIN (-LUA_INTEGER_MAX - 1LL)   /* -2^63 */\n+/* */\n+#elif defined(LNUM_INT16)\n+# if LUAI_BITSINT > 16\n+#  define LUA_INTEGER    short\n+#  define LUA_INTEGER_SCAN \"%hd\"\n+#  define LUA_INTEGER_FMT \"%hd\"\n+# else\n+#  define LUA_INTEGER    int\n+#  define LUA_INTEGER_SCAN \"%d\"\n+#  define LUA_INTEGER_FMT \"%d\"\n+# endif\n+# define LUA_INTEGER_MAX 0x7FFF             /* 2^16-1 */\n+#endif\n+\n+#ifndef lua_str2ul\n+# define lua_str2ul (unsigned LUA_INTEGER)strtoul\n+#endif\n+#ifndef LUA_INTEGER_MIN\n+# define LUA_INTEGER_MIN (-LUA_INTEGER_MAX -1)  /* -2^16|32 */\n+#endif\n+\n+/*\n+@@ lua_number2int is a macro to convert lua_Number to int.\n+@@ lua_number2integer is a macro to convert lua_Number to lua_Integer.\n+** CHANGE them if you know a faster way to convert a lua_Number to\n+** int (with any rounding method and without throwing errors) in your\n+** system. In Pentium machines, a naive typecast from double to int\n+** in C is extremely slow, so any alternative is worth trying.\n+*/\n+\n+/* On a Pentium, resort to a trick */\n+#if defined(LNUM_DOUBLE) && !defined(LUA_ANSI) && !defined(__SSE2__) && \\\n+    (defined(__i386) || defined (_M_IX86) || defined(__i386__))\n+\n+/* On a Microsoft compiler, use assembler */\n+# if defined(_MSC_VER)\n+#  define lua_number2int(i,d)   __asm fld d   __asm fistp i\n+# else\n+\n+/* the next trick should work on any Pentium, but sometimes clashes\n+   with a DirectX idiosyncrasy */\n+union luai_Cast { double l_d; long l_l; };\n+#  define lua_number2int(i,d) \\\n+  { volatile union luai_Cast u; u.l_d = (d) + 6755399441055744.0; (i) = u.l_l; }\n+# endif\n+\n+# ifndef LNUM_INT64\n+#  define lua_number2integer    lua_number2int\n+# endif\n+\n+/* this option always works, but may be slow */\n+#else\n+# define lua_number2int(i,d)        ((i)=(int)(d))\n+#endif\n+\n+/* Note: Some compilers (OS X gcc 4.0?) may choke on double->long long conversion \n+ *       since it can lose precision. Others do require 'long long' there.  \n+ */\n+#ifndef lua_number2integer\n+# define lua_number2integer(i,d)    ((i)=(lua_Integer)(d))\n+#endif\n+\n+/*\n+** 'luai_abs()' to give absolute value of 'lua_Integer'\n+*/\n+#ifdef LNUM_INT32\n+# define luai_abs abs\n+#elif defined(LNUM_INT64) && (__STDC_VERSION__ >= 199901L)\n+# define luai_abs llabs\n+#else\n+# define luai_abs(v) ((v) >= 0 ? (v) : -(v))\n+#endif\n+\n+/*\n+** LUAI_UACNUMBER is the result of an 'usual argument conversion' over a number.\n+** LUAI_UACINTEGER the same, over an integer.\n+*/\n+#define LUAI_UACNUMBER\tdouble\n+#define LUAI_UACINTEGER long\n+\n+/* ANSI C only has math funcs for 'double. C99 required for float and long double\n+ * variants.\n+ */\n+#ifdef LNUM_DOUBLE\n+# define _LF(name) name\n+#elif defined(LNUM_FLOAT)\n+# define _LF(name) name ## f\n+#elif defined(LNUM_LDOUBLE)\n+# define _LF(name) name ## l\n+#endif\n+\n+#endif\n+\n--- a/src/lobject.c\n+++ b/src/lobject.c\n@@ -21,7 +21,8 @@\n #include \"lstate.h\"\n #include \"lstring.h\"\n #include \"lvm.h\"\n-\n+#include \"llex.h\"\n+#include \"lnum.h\"\n \n \n const TValue luaO_nilobject_ = {{NULL}, LUA_TNIL};\n@@ -70,12 +71,31 @@ int luaO_log2 (unsigned int x) {\n \n \n int luaO_rawequalObj (const TValue *t1, const TValue *t2) {\n-  if (ttype(t1) != ttype(t2)) return 0;\n+  if (!ttype_ext_same(t1,t2)) return 0;\n   else switch (ttype(t1)) {\n     case LUA_TNIL:\n       return 1;\n+    case LUA_TINT:\n+      if (ttype(t2)==LUA_TINT)\n+        return ivalue(t1) == ivalue(t2);\n+      else {  /* t1:int, t2:num */\n+#ifdef LNUM_COMPLEX\n+        if (nvalue_img_fast(t2) != 0) return 0;\n+#endif\n+        /* Avoid doing accuracy losing cast, if possible. */\n+        lua_Integer tmp;\n+        if (tt_integer_valued(t2,&tmp)) \n+          return ivalue(t1) == tmp;\n+        else\n+          return luai_numeq( cast_num(ivalue(t1)), nvalue_fast(t2) );\n+        }\n     case LUA_TNUMBER:\n-      return luai_numeq(nvalue(t1), nvalue(t2));\n+        if (ttype(t2)==LUA_TINT)\n+          return luaO_rawequalObj(t2, t1);  /* swap LUA_TINT to left */\n+#ifdef LNUM_COMPLEX\n+        if (!luai_numeq(nvalue_img_fast(t1), nvalue_img_fast(t2))) return 0;\n+#endif\n+        return luai_numeq(nvalue_fast(t1), nvalue_fast(t2));\n     case LUA_TBOOLEAN:\n       return bvalue(t1) == bvalue(t2);  /* boolean true must be 1 !! */\n     case LUA_TLIGHTUSERDATA:\n@@ -86,21 +106,6 @@ int luaO_rawequalObj (const TValue *t1,\n   }\n }\n \n-\n-int luaO_str2d (const char *s, lua_Number *result) {\n-  char *endptr;\n-  *result = lua_str2number(s, &endptr);\n-  if (endptr == s) return 0;  /* conversion failed */\n-  if (*endptr == 'x' || *endptr == 'X')  /* maybe an hexadecimal constant? */\n-    *result = cast_num(strtoul(s, &endptr, 16));\n-  if (*endptr == '\\0') return 1;  /* most common case */\n-  while (isspace(cast(unsigned char, *endptr))) endptr++;\n-  if (*endptr != '\\0') return 0;  /* invalid trailing characters? */\n-  return 1;\n-}\n-\n-\n-\n static void pushstr (lua_State *L, const char *str) {\n   setsvalue2s(L, L->top, luaS_new(L, str));\n   incr_top(L);\n@@ -131,7 +136,11 @@ const char *luaO_pushvfstring (lua_State\n         break;\n       }\n       case 'd': {\n-        setnvalue(L->top, cast_num(va_arg(argp, int)));\n+        /* This is tricky for 64-bit integers; maybe they even cannot be\n+         * supported on all compilers; depends on the conversions applied to\n+         * variable argument lists. TBD: test!\n+         */\n+        setivalue(L->top, (lua_Integer) va_arg(argp, l_uacInteger));\n         incr_top(L);\n         break;\n       }\n@@ -212,3 +221,4 @@ void luaO_chunkid (char *out, const char\n     }\n   }\n }\n+\n--- a/src/lobject.h\n+++ b/src/lobject.h\n@@ -17,7 +17,11 @@\n \n \n /* tags for values visible from Lua */\n-#define LAST_TAG\tLUA_TTHREAD\n+#if LUA_TINT > LUA_TTHREAD\n+# define LAST_TAG   LUA_TINT\n+#else\n+# define LAST_TAG\tLUA_TTHREAD\n+#endif\n \n #define NUM_TAGS\t(LAST_TAG+1)\n \n@@ -59,7 +63,12 @@ typedef struct GCheader {\n typedef union {\n   GCObject *gc;\n   void *p;\n+#ifdef LNUM_COMPLEX\n+  lua_Complex n;\n+#else\n   lua_Number n;\n+#endif\n+  lua_Integer i;\n   int b;\n } Value;\n \n@@ -77,7 +86,11 @@ typedef struct lua_TValue {\n \n /* Macros to test type */\n #define ttisnil(o)\t(ttype(o) == LUA_TNIL)\n-#define ttisnumber(o)\t(ttype(o) == LUA_TNUMBER)\n+#define ttisint(o) (ttype(o) == LUA_TINT)\n+#define ttisnumber(o) ((ttype(o) == LUA_TINT) || (ttype(o) == LUA_TNUMBER))\n+#ifdef LNUM_COMPLEX\n+# define ttiscomplex(o) ((ttype(o) == LUA_TNUMBER) && (nvalue_img_fast(o)!=0))\n+#endif\n #define ttisstring(o)\t(ttype(o) == LUA_TSTRING)\n #define ttistable(o)\t(ttype(o) == LUA_TTABLE)\n #define ttisfunction(o)\t(ttype(o) == LUA_TFUNCTION)\n@@ -90,7 +103,25 @@ typedef struct lua_TValue {\n #define ttype(o)\t((o)->tt)\n #define gcvalue(o)\tcheck_exp(iscollectable(o), (o)->value.gc)\n #define pvalue(o)\tcheck_exp(ttislightuserdata(o), (o)->value.p)\n-#define nvalue(o)\tcheck_exp(ttisnumber(o), (o)->value.n)\n+\n+#define ttype_ext(o) ( ttype(o) == LUA_TINT ? LUA_TNUMBER : ttype(o) )\n+#define ttype_ext_same(o1,o2) ( (ttype(o1)==ttype(o2)) || (ttisnumber(o1) && ttisnumber(o2)) )\n+\n+/* '_fast' variants are for cases where 'ttype(o)' is known to be LUA_TNUMBER.\n+ */\n+#ifdef LNUM_COMPLEX\n+#  define nvalue_complex_fast(o) check_exp( ttype(o)==LUA_TNUMBER, (o)->value.n )   \n+#  define nvalue_fast(o)     ( _LF(creal) ( nvalue_complex_fast(o) ) )\n+#  define nvalue_img_fast(o) ( _LF(cimag) ( nvalue_complex_fast(o) ) )\n+#  define nvalue_complex(o) check_exp( ttisnumber(o), (ttype(o)==LUA_TINT) ? (o)->value.i : (o)->value.n )\n+#  define nvalue_img(o) check_exp( ttisnumber(o), (ttype(o)==LUA_TINT) ? 0 : _LF(cimag)( (o)->value.n ) ) \n+#  define nvalue(o) check_exp( ttisnumber(o), (ttype(o)==LUA_TINT) ? cast_num((o)->value.i) : _LF(creal)((o)->value.n) ) \n+#else\n+# define nvalue(o)\tcheck_exp( ttisnumber(o), (ttype(o)==LUA_TINT) ? cast_num((o)->value.i) : (o)->value.n )\n+# define nvalue_fast(o) check_exp( ttype(o)==LUA_TNUMBER, (o)->value.n )   \n+#endif\n+#define ivalue(o)\tcheck_exp( ttype(o)==LUA_TINT, (o)->value.i )\n+\n #define rawtsvalue(o)\tcheck_exp(ttisstring(o), &(o)->value.gc->ts)\n #define tsvalue(o)\t(&rawtsvalue(o)->tsv)\n #define rawuvalue(o)\tcheck_exp(ttisuserdata(o), &(o)->value.gc->u)\n@@ -116,8 +147,27 @@ typedef struct lua_TValue {\n /* Macros to set values */\n #define setnilvalue(obj) ((obj)->tt=LUA_TNIL)\n \n-#define setnvalue(obj,x) \\\n-  { TValue *i_o=(obj); i_o->value.n=(x); i_o->tt=LUA_TNUMBER; }\n+/* Must not have side effects, 'x' may be expression.\n+*/\n+#define setivalue(obj,x) \\\n+    { TValue *i_o=(obj); i_o->value.i=(x); i_o->tt=LUA_TINT; }\n+\n+# define setnvalue(obj,x) \\\n+    { TValue *i_o=(obj); i_o->value.n= (x); i_o->tt=LUA_TNUMBER; }\n+\n+/* Note: Complex always has \"inline\", both are C99.\n+*/\n+#ifdef LNUM_COMPLEX\n+  static inline void setnvalue_complex_fast( TValue *obj, lua_Complex x ) {\n+    lua_assert( _LF(cimag)(x) != 0 );\n+    obj->value.n= x; obj->tt= LUA_TNUMBER;\n+  }\n+  static inline void setnvalue_complex( TValue *obj, lua_Complex x ) {\n+    if (_LF(cimag)(x) == 0) { setnvalue(obj, _LF(creal)(x)); }\n+    else { obj->value.n= x; obj->tt= LUA_TNUMBER; }\n+  }\n+#endif\n+\n \n #define setpvalue(obj,x) \\\n   { TValue *i_o=(obj); i_o->value.p=(x); i_o->tt=LUA_TLIGHTUSERDATA; }\n@@ -155,9 +205,6 @@ typedef struct lua_TValue {\n     i_o->value.gc=cast(GCObject *, (x)); i_o->tt=LUA_TPROTO; \\\n     checkliveness(G(L),i_o); }\n \n-\n-\n-\n #define setobj(L,obj1,obj2) \\\n   { const TValue *o2=(obj2); TValue *o1=(obj1); \\\n     o1->value = o2->value; o1->tt=o2->tt; \\\n@@ -185,8 +232,11 @@ typedef struct lua_TValue {\n \n #define setttype(obj, tt) (ttype(obj) = (tt))\n \n-\n-#define iscollectable(o)\t(ttype(o) >= LUA_TSTRING)\n+#if LUA_TINT >= LUA_TSTRING\n+# define iscollectable(o)\t((ttype(o) >= LUA_TSTRING) && (ttype(o) != LUA_TINT))\n+#else\n+# define iscollectable(o)\t(ttype(o) >= LUA_TSTRING)\n+#endif\n \n \n \n@@ -370,12 +420,10 @@ LUAI_FUNC int luaO_log2 (unsigned int x)\n LUAI_FUNC int luaO_int2fb (unsigned int x);\n LUAI_FUNC int luaO_fb2int (int x);\n LUAI_FUNC int luaO_rawequalObj (const TValue *t1, const TValue *t2);\n-LUAI_FUNC int luaO_str2d (const char *s, lua_Number *result);\n LUAI_FUNC const char *luaO_pushvfstring (lua_State *L, const char *fmt,\n                                                        va_list argp);\n LUAI_FUNC const char *luaO_pushfstring (lua_State *L, const char *fmt, ...);\n LUAI_FUNC void luaO_chunkid (char *out, const char *source, size_t len);\n \n-\n #endif\n \n--- a/src/loslib.c\n+++ b/src/loslib.c\n@@ -186,15 +186,30 @@ static int os_time (lua_State *L) {\n   }\n   if (t == (time_t)(-1))\n     lua_pushnil(L);\n-  else\n-    lua_pushnumber(L, (lua_Number)t);\n+  else {\n+     /* On float systems the pushed value must be an integer, NOT a number.\n+      * Otherwise, accuracy is lost in the time_t->float conversion.\n+      */\n+#ifdef LNUM_FLOAT\n+     lua_pushinteger(L, (lua_Integer) t);\n+#else\n+     lua_pushnumber(L, (lua_Number) t);\n+#endif\n+     }\n   return 1;\n }\n \n \n static int os_difftime (lua_State *L) {\n+#ifdef LNUM_FLOAT\n+  lua_Integer i= (lua_Integer)\n+    difftime( (time_t)(luaL_checkinteger(L, 1)),\n+              (time_t)(luaL_optinteger(L, 2, 0)));\n+  lua_pushinteger(L, i);\n+#else\n   lua_pushnumber(L, difftime((time_t)(luaL_checknumber(L, 1)),\n                              (time_t)(luaL_optnumber(L, 2, 0))));\n+#endif\n   return 1;\n }\n \n--- a/src/lparser.c\n+++ b/src/lparser.c\n@@ -33,7 +33,6 @@\n \n #define luaY_checklimit(fs,v,l,m)\tif ((v)>(l)) errorlimit(fs,l,m)\n \n-\n /*\n ** nodes for block list (list of active blocks)\n */\n@@ -72,7 +71,7 @@ static void errorlimit (FuncState *fs, i\n   const char *msg = (fs->f->linedefined == 0) ?\n     luaO_pushfstring(fs->L, \"main function has more than %d %s\", limit, what) :\n     luaO_pushfstring(fs->L, \"function at line %d has more than %d %s\",\n-                            fs->f->linedefined, limit, what);\n+                            (fs->f->linedefined), limit, what);\n   luaX_lexerror(fs->ls, msg, 0);\n }\n \n@@ -733,6 +732,18 @@ static void simpleexp (LexState *ls, exp\n       v->u.nval = ls->t.seminfo.r;\n       break;\n     }\n+    case TK_INT: {\n+      init_exp(v, VKINT, 0);\n+      v->u.ival = ls->t.seminfo.i;\n+      break;\n+    }\n+#ifdef LNUM_COMPLEX\n+    case TK_NUMBER2: {\n+      init_exp(v, VKNUM2, 0);\n+      v->u.nval = ls->t.seminfo.r;\n+      break;\n+    }\n+#endif\n     case TK_STRING: {\n       codestring(ls, v, ls->t.seminfo.ts);\n       break;\n@@ -1079,7 +1090,7 @@ static void fornum (LexState *ls, TStrin\n   if (testnext(ls, ','))\n     exp1(ls);  /* optional step */\n   else {  /* default step = 1 */\n-    luaK_codeABx(fs, OP_LOADK, fs->freereg, luaK_numberK(fs, 1));\n+    luaK_codeABx(fs, OP_LOADK, fs->freereg, luaK_integerK(fs, 1));\n     luaK_reserveregs(fs, 1);\n   }\n   forbody(ls, base, line, 1, 1);\n--- a/src/lparser.h\n+++ b/src/lparser.h\n@@ -31,7 +31,11 @@ typedef enum {\n   VRELOCABLE,\t/* info = instruction pc */\n   VNONRELOC,\t/* info = result register */\n   VCALL,\t/* info = instruction pc */\n-  VVARARG\t/* info = instruction pc */\n+  VVARARG,\t/* info = instruction pc */\n+  VKINT     /* ival = integer value */\n+#ifdef LNUM_COMPLEX\n+  ,VKNUM2   /* nval = imaginary value */\n+#endif\n } expkind;\n \n typedef struct expdesc {\n@@ -39,6 +43,7 @@ typedef struct expdesc {\n   union {\n     struct { int info, aux; } s;\n     lua_Number nval;\n+    lua_Integer ival;\n   } u;\n   int t;  /* patch list of `exit when true' */\n   int f;  /* patch list of `exit when false' */\n--- a/src/lstrlib.c\n+++ b/src/lstrlib.c\n@@ -43,8 +43,8 @@ static ptrdiff_t posrelat (ptrdiff_t pos\n static int str_sub (lua_State *L) {\n   size_t l;\n   const char *s = luaL_checklstring(L, 1, &l);\n-  ptrdiff_t start = posrelat(luaL_checkinteger(L, 2), l);\n-  ptrdiff_t end = posrelat(luaL_optinteger(L, 3, -1), l);\n+  ptrdiff_t start = posrelat(luaL_checkint32(L, 2), l);\n+  ptrdiff_t end = posrelat(luaL_optint32(L, 3, -1), l);\n   if (start < 1) start = 1;\n   if (end > (ptrdiff_t)l) end = (ptrdiff_t)l;\n   if (start <= end)\n@@ -106,8 +106,8 @@ static int str_rep (lua_State *L) {\n static int str_byte (lua_State *L) {\n   size_t l;\n   const char *s = luaL_checklstring(L, 1, &l);\n-  ptrdiff_t posi = posrelat(luaL_optinteger(L, 2, 1), l);\n-  ptrdiff_t pose = posrelat(luaL_optinteger(L, 3, posi), l);\n+  ptrdiff_t posi = posrelat(luaL_optint32(L, 2, 1), l);\n+  ptrdiff_t pose = posrelat(luaL_optint32(L, 3, posi), l);\n   int n, i;\n   if (posi <= 0) posi = 1;\n   if ((size_t)pose > l) pose = l;\n@@ -496,7 +496,7 @@ static int str_find_aux (lua_State *L, i\n   size_t l1, l2;\n   const char *s = luaL_checklstring(L, 1, &l1);\n   const char *p = luaL_checklstring(L, 2, &l2);\n-  ptrdiff_t init = posrelat(luaL_optinteger(L, 3, 1), l1) - 1;\n+  ptrdiff_t init = posrelat(luaL_optint32(L, 3, 1), l1) - 1;\n   if (init < 0) init = 0;\n   else if ((size_t)(init) > l1) init = (ptrdiff_t)l1;\n   if (find && (lua_toboolean(L, 4) ||  /* explicit request? */\n@@ -690,7 +690,7 @@ static int str_gsub (lua_State *L) {\n ** maximum size of each format specification (such as '%-099.99d')\n ** (+10 accounts for %99.99x plus margin of error)\n */\n-#define MAX_FORMAT\t(sizeof(FLAGS) + sizeof(LUA_INTFRMLEN) + 10)\n+#define MAX_FORMAT\t(sizeof(FLAGS) + sizeof(LUA_INTEGER_FMT)-2 + 10)\n \n \n static void addquoted (lua_State *L, luaL_Buffer *b, int arg) {\n@@ -747,9 +747,9 @@ static const char *scanformat (lua_State\n static void addintlen (char *form) {\n   size_t l = strlen(form);\n   char spec = form[l - 1];\n-  strcpy(form + l - 1, LUA_INTFRMLEN);\n-  form[l + sizeof(LUA_INTFRMLEN) - 2] = spec;\n-  form[l + sizeof(LUA_INTFRMLEN) - 1] = '\\0';\n+  const char *tmp= LUA_INTEGER_FMT;   /* \"%lld\" or \"%ld\" */\n+  strcpy(form + l - 1, tmp+1);\n+  form[l + sizeof(LUA_INTEGER_FMT)-4] = spec;\n }\n \n \n@@ -779,12 +779,12 @@ static int str_format (lua_State *L) {\n         }\n         case 'd':  case 'i': {\n           addintlen(form);\n-          sprintf(buff, form, (LUA_INTFRM_T)luaL_checknumber(L, arg));\n+          sprintf(buff, form, luaL_checkinteger(L, arg));\n           break;\n         }\n         case 'o':  case 'u':  case 'x':  case 'X': {\n           addintlen(form);\n-          sprintf(buff, form, (unsigned LUA_INTFRM_T)luaL_checknumber(L, arg));\n+          sprintf(buff, form, (unsigned LUA_INTEGER)luaL_checkinteger(L, arg));\n           break;\n         }\n         case 'e':  case 'E': case 'f':\n--- a/src/ltable.c\n+++ b/src/ltable.c\n@@ -33,6 +33,7 @@\n #include \"lobject.h\"\n #include \"lstate.h\"\n #include \"ltable.h\"\n+#include \"lnum.h\"\n \n \n /*\n@@ -51,25 +52,15 @@\n   \n #define hashstr(t,str)  hashpow2(t, (str)->tsv.hash)\n #define hashboolean(t,p)        hashpow2(t, p)\n-\n+#define hashint(t,i)    hashpow2(t,i)\n \n /*\n ** for some types, it is better to avoid modulus by power of 2, as\n ** they tend to have many 2 factors.\n */\n #define hashmod(t,n)\t(gnode(t, ((n) % ((sizenode(t)-1)|1))))\n-\n-\n #define hashpointer(t,p)\thashmod(t, IntPoint(p))\n \n-\n-/*\n-** number of ints inside a lua_Number\n-*/\n-#define numints\t\tcast_int(sizeof(lua_Number)/sizeof(int))\n-\n-\n-\n #define dummynode\t\t(&dummynode_)\n \n static const Node dummynode_ = {\n@@ -80,27 +71,46 @@ static const Node dummynode_ = {\n \n /*\n ** hash for lua_Numbers\n+**\n+** for non-complex modes, never called with 'lua_Integer' value range (s.a. 0)\n */\n static Node *hashnum (const Table *t, lua_Number n) {\n-  unsigned int a[numints];\n-  int i;\n-  if (luai_numeq(n, 0))  /* avoid problems with -0 */\n-    return gnode(t, 0);\n-  memcpy(a, &n, sizeof(a));\n-  for (i = 1; i < numints; i++) a[0] += a[i];\n-  return hashmod(t, a[0]);\n+  const unsigned int *p= cast(const unsigned int *,&n);\n+  unsigned int sum= *p;\n+  unsigned int m= sizeof(lua_Number)/sizeof(int);\n+  unsigned int i;\n+  /* OS X Intel has 'm'==4 and gives \"Bus error\" if the last integer of \n+   * 'n' is read; the actual size of long double is only 80 bits = 10 bytes.\n+   * Linux x86 has 'm'==3, and does not require reduction.\n+   */\n+#if defined(LNUM_LDOUBLE) && defined(__i386__)\n+  if (m>3) m--;\n+#endif\n+  for (i = 1; i < m; i++) sum += p[i];\n+  return hashmod(t, sum);\n }\n \n \n-\n /*\n ** returns the `main' position of an element in a table (that is, the index\n ** of its hash value)\n+**\n+** Floating point numbers with integer value give the hash position of the\n+** integer (so they use the same table position).\n */\n static Node *mainposition (const Table *t, const TValue *key) {\n+  lua_Integer i;\n   switch (ttype(key)) {\n     case LUA_TNUMBER:\n-      return hashnum(t, nvalue(key));\n+      if (tt_integer_valued(key,&i)) \n+        return hashint(t, i);\n+#ifdef LNUM_COMPLEX\n+      if (nvalue_img_fast(key)!=0 && luai_numeq(nvalue_fast(key),0))\n+        return gnode(t, 0);  /* 0 and -0 to give same hash */\n+#endif\n+      return hashnum(t, nvalue_fast(key));\n+    case LUA_TINT:\n+      return hashint(t, ivalue(key));\n     case LUA_TSTRING:\n       return hashstr(t, rawtsvalue(key));\n     case LUA_TBOOLEAN:\n@@ -116,16 +126,20 @@ static Node *mainposition (const Table *\n /*\n ** returns the index for `key' if `key' is an appropriate key to live in\n ** the array part of the table, -1 otherwise.\n+**\n+** Anything <=0 is taken as not being in the array part.\n */\n-static int arrayindex (const TValue *key) {\n-  if (ttisnumber(key)) {\n-    lua_Number n = nvalue(key);\n-    int k;\n-    lua_number2int(k, n);\n-    if (luai_numeq(cast_num(k), n))\n-      return k;\n+static int arrayindex (const TValue *key, int max) {\n+  lua_Integer k;\n+  switch( ttype(key) ) {\n+    case LUA_TINT:\n+      k= ivalue(key); break;\n+    case LUA_TNUMBER:\n+      if (tt_integer_valued(key,&k)) break;\n+    default:\n+      return -1;  /* not to be used as array index */\n   }\n-  return -1;  /* `key' did not match some condition */\n+  return ((k>0) && (k <= max)) ? cast_int(k) : -1;\n }\n \n \n@@ -137,8 +151,8 @@ static int arrayindex (const TValue *key\n static int findindex (lua_State *L, Table *t, StkId key) {\n   int i;\n   if (ttisnil(key)) return -1;  /* first iteration */\n-  i = arrayindex(key);\n-  if (0 < i && i <= t->sizearray)  /* is `key' inside array part? */\n+  i = arrayindex(key, t->sizearray);\n+  if (i>0)  /* inside array part? */\n     return i-1;  /* yes; that's the index (corrected to C) */\n   else {\n     Node *n = mainposition(t, key);\n@@ -163,7 +177,7 @@ int luaH_next (lua_State *L, Table *t, S\n   int i = findindex(L, t, key);  /* find original element */\n   for (i++; i < t->sizearray; i++) {  /* try first array part */\n     if (!ttisnil(&t->array[i])) {  /* a non-nil value? */\n-      setnvalue(key, cast_num(i+1));\n+      setivalue(key, i+1);\n       setobj2s(L, key+1, &t->array[i]);\n       return 1;\n     }\n@@ -209,8 +223,8 @@ static int computesizes (int nums[], int\n \n \n static int countint (const TValue *key, int *nums) {\n-  int k = arrayindex(key);\n-  if (0 < k && k <= MAXASIZE) {  /* is `key' an appropriate array index? */\n+  int k = arrayindex(key,MAXASIZE);\n+  if (k>0) {  /* appropriate array index? */\n     nums[ceillog2(k)]++;  /* count as such */\n     return 1;\n   }\n@@ -308,7 +322,7 @@ static void resize (lua_State *L, Table\n     /* re-insert elements from vanishing slice */\n     for (i=nasize; i<oldasize; i++) {\n       if (!ttisnil(&t->array[i]))\n-        setobjt2t(L, luaH_setnum(L, t, i+1), &t->array[i]);\n+        setobjt2t(L, luaH_setint(L, t, i+1), &t->array[i]);\n     }\n     /* shrink array */\n     luaM_reallocvector(L, t->array, oldasize, nasize, TValue);\n@@ -409,7 +423,9 @@ static TValue *newkey (lua_State *L, Tab\n     othern = mainposition(t, key2tval(mp));\n     if (othern != mp) {  /* is colliding node out of its main position? */\n       /* yes; move colliding node into free position */\n-      while (gnext(othern) != mp) othern = gnext(othern);  /* find previous */\n+      while (gnext(othern) != mp) {\n+        othern = gnext(othern);  /* find previous */\n+      }\n       gnext(othern) = n;  /* redo the chain with `n' in place of `mp' */\n       *n = *mp;  /* copy colliding node into free pos. (mp->next also goes) */\n       gnext(mp) = NULL;  /* now `mp' is free */\n@@ -432,17 +448,18 @@ static TValue *newkey (lua_State *L, Tab\n /*\n ** search function for integers\n */\n-const TValue *luaH_getnum (Table *t, int key) {\n+const TValue *luaH_getint (Table *t, lua_Integer key) {\n   /* (1 <= key && key <= t->sizearray) */\n   if (cast(unsigned int, key-1) < cast(unsigned int, t->sizearray))\n     return &t->array[key-1];\n   else {\n-    lua_Number nk = cast_num(key);\n-    Node *n = hashnum(t, nk);\n+    Node *n = hashint(t, key);\n     do {  /* check whether `key' is somewhere in the chain */\n-      if (ttisnumber(gkey(n)) && luai_numeq(nvalue(gkey(n)), nk))\n+      if (ttisint(gkey(n)) && (ivalue(gkey(n)) == key)) {\n         return gval(n);  /* that's it */\n-      else n = gnext(n);\n+      } else { \n+      n = gnext(n);\n+    }\n     } while (n);\n     return luaO_nilobject;\n   }\n@@ -470,14 +487,12 @@ const TValue *luaH_get (Table *t, const\n   switch (ttype(key)) {\n     case LUA_TNIL: return luaO_nilobject;\n     case LUA_TSTRING: return luaH_getstr(t, rawtsvalue(key));\n+    case LUA_TINT: return luaH_getint(t, ivalue(key));\n     case LUA_TNUMBER: {\n-      int k;\n-      lua_Number n = nvalue(key);\n-      lua_number2int(k, n);\n-      if (luai_numeq(cast_num(k), nvalue(key))) /* index is int? */\n-        return luaH_getnum(t, k);  /* use specialized version */\n-      /* else go through */\n-    }\n+      lua_Integer i;\n+      if (tt_integer_valued(key,&i))\n+        return luaH_getint(t,i);\n+    } /* pass through */\n     default: {\n       Node *n = mainposition(t, key);\n       do {  /* check whether `key' is somewhere in the chain */\n@@ -498,20 +513,25 @@ TValue *luaH_set (lua_State *L, Table *t\n     return cast(TValue *, p);\n   else {\n     if (ttisnil(key)) luaG_runerror(L, \"table index is nil\");\n-    else if (ttisnumber(key) && luai_numisnan(nvalue(key)))\n-      luaG_runerror(L, \"table index is NaN\");\n+    else if (ttype(key)==LUA_TNUMBER) {\n+      lua_Integer k;\n+      if (luai_numisnan(nvalue_fast(key)))\n+        luaG_runerror(L, \"table index is NaN\");\n+      if (tt_integer_valued(key,&k))\n+        return luaH_setint(L, t, k);\n+    }\n     return newkey(L, t, key);\n   }\n }\n \n \n-TValue *luaH_setnum (lua_State *L, Table *t, int key) {\n-  const TValue *p = luaH_getnum(t, key);\n+TValue *luaH_setint (lua_State *L, Table *t, lua_Integer key) {\n+  const TValue *p = luaH_getint(t, key);\n   if (p != luaO_nilobject)\n     return cast(TValue *, p);\n   else {\n     TValue k;\n-    setnvalue(&k, cast_num(key));\n+    setivalue(&k, key);\n     return newkey(L, t, &k);\n   }\n }\n@@ -533,20 +553,21 @@ static int unbound_search (Table *t, uns\n   unsigned int i = j;  /* i is zero or a present index */\n   j++;\n   /* find `i' and `j' such that i is present and j is not */\n-  while (!ttisnil(luaH_getnum(t, j))) {\n+  while (!ttisnil(luaH_getint(t, j))) {\n     i = j;\n     j *= 2;\n     if (j > cast(unsigned int, MAX_INT)) {  /* overflow? */\n       /* table was built with bad purposes: resort to linear search */\n-      i = 1;\n-      while (!ttisnil(luaH_getnum(t, i))) i++;\n-      return i - 1;\n+      for( i = 1; i<MAX_INT+1; i++ ) {\n+        if (ttisnil(luaH_getint(t, i))) break;\n+      }\n+      return i - 1;  /* up to MAX_INT */\n     }\n   }\n   /* now do a binary search between them */\n   while (j - i > 1) {\n     unsigned int m = (i+j)/2;\n-    if (ttisnil(luaH_getnum(t, m))) j = m;\n+    if (ttisnil(luaH_getint(t, m))) j = m;\n     else i = m;\n   }\n   return i;\n--- a/src/ltable.h\n+++ b/src/ltable.h\n@@ -18,8 +18,8 @@\n #define key2tval(n)\t(&(n)->i_key.tvk)\n \n \n-LUAI_FUNC const TValue *luaH_getnum (Table *t, int key);\n-LUAI_FUNC TValue *luaH_setnum (lua_State *L, Table *t, int key);\n+LUAI_FUNC const TValue *luaH_getint (Table *t, lua_Integer key);\n+LUAI_FUNC TValue *luaH_setint (lua_State *L, Table *t, lua_Integer key);\n LUAI_FUNC const TValue *luaH_getstr (Table *t, TString *key);\n LUAI_FUNC TValue *luaH_setstr (lua_State *L, Table *t, TString *key);\n LUAI_FUNC const TValue *luaH_get (Table *t, const TValue *key);\n--- a/src/ltm.c\n+++ b/src/ltm.c\n@@ -19,7 +19,6 @@\n #include \"ltm.h\"\n \n \n-\n const char *const luaT_typenames[] = {\n   \"nil\", \"boolean\", \"userdata\", \"number\",\n   \"string\", \"table\", \"function\", \"userdata\", \"thread\",\n@@ -67,6 +66,9 @@ const TValue *luaT_gettmbyobj (lua_State\n     case LUA_TUSERDATA:\n       mt = uvalue(o)->metatable;\n       break;\n+    case LUA_TINT:\n+      mt = G(L)->mt[LUA_TNUMBER];\n+      break;\n     default:\n       mt = G(L)->mt[ttype(o)];\n   }\n--- a/src/lua.c\n+++ b/src/lua.c\n@@ -16,7 +16,7 @@\n \n #include \"lauxlib.h\"\n #include \"lualib.h\"\n-\n+#include \"llimits.h\"\n \n \n static lua_State *globalL = NULL;\n@@ -382,6 +382,15 @@ int main (int argc, char **argv) {\n     l_message(argv[0], \"cannot create state: not enough memory\");\n     return EXIT_FAILURE;\n   }\n+  /* Checking 'sizeof(lua_Integer)' cannot be made in preprocessor on all compilers.\n+  */\n+#ifdef LNUM_INT16\n+  lua_assert( sizeof(lua_Integer) == 2 );\n+#elif defined(LNUM_INT32)\n+  lua_assert( sizeof(lua_Integer) == 4 );\n+#elif defined(LNUM_INT64)\n+  lua_assert( sizeof(lua_Integer) == 8 );\n+#endif\n   s.argc = argc;\n   s.argv = argv;\n   status = lua_cpcall(L, &pmain, &s);\n--- a/src/lua.h\n+++ b/src/lua.h\n@@ -19,7 +19,7 @@\n #define LUA_VERSION\t\"Lua 5.1\"\n #define LUA_RELEASE\t\"Lua 5.1.5\"\n #define LUA_VERSION_NUM\t501\n-#define LUA_COPYRIGHT\t\"Copyright (C) 1994-2012 Lua.org, PUC-Rio\"\n+#define LUA_COPYRIGHT\t\"Copyright (C) 1994-2012 Lua.org, PUC-Rio\" \" (\" LUA_LNUM \")\"\n #define LUA_AUTHORS \t\"R. Ierusalimschy, L. H. de Figueiredo & W. Celes\"\n \n \n@@ -71,6 +71,16 @@ typedef void * (*lua_Alloc) (void *ud, v\n */\n #define LUA_TNONE\t\t(-1)\n \n+/* LUA_TINT is an internal type, not visible to applications. There are three\n+ * potential values where it can be tweaked to (code autoadjusts to these):\n+ *\n+ * -2: not 'usual' type value; good since 'LUA_TINT' is not part of the API\n+ * LUA_TNUMBER+1: shifts other type values upwards, breaking binary compatibility\n+ *     not acceptable for 5.1, maybe 5.2 onwards?\n+ *  9: greater than existing (5.1) type values.\n+*/\n+#define LUA_TINT (-2)\n+\n #define LUA_TNIL\t\t0\n #define LUA_TBOOLEAN\t\t1\n #define LUA_TLIGHTUSERDATA\t2\n@@ -139,6 +149,8 @@ LUA_API int             (lua_isuserdata)\n LUA_API int             (lua_type) (lua_State *L, int idx);\n LUA_API const char     *(lua_typename) (lua_State *L, int tp);\n \n+LUA_API int             (lua_isinteger) (lua_State *L, int idx);\n+\n LUA_API int            (lua_equal) (lua_State *L, int idx1, int idx2);\n LUA_API int            (lua_rawequal) (lua_State *L, int idx1, int idx2);\n LUA_API int            (lua_lessthan) (lua_State *L, int idx1, int idx2);\n@@ -244,6 +256,19 @@ LUA_API lua_Alloc (lua_getallocf) (lua_S\n LUA_API void lua_setallocf (lua_State *L, lua_Alloc f, void *ud);\n \n \n+/*\n+* It is unnecessary to break Lua C API 'lua_tonumber()' compatibility, just\n+* because the Lua number type is complex. Most C modules would use scalars\n+* only. We'll introduce new 'lua_tocomplex' and 'lua_pushcomplex' for when\n+* the module really wants to use them.\n+*/\n+#ifdef LNUM_COMPLEX\n+  #include <complex.h>\n+  typedef LUA_NUMBER complex lua_Complex;\n+  LUA_API lua_Complex (lua_tocomplex) (lua_State *L, int idx);\n+  LUA_API void (lua_pushcomplex) (lua_State *L, lua_Complex v);\n+#endif\n+\n \n /* \n ** ===============================================================\n@@ -268,7 +293,12 @@ LUA_API void lua_setallocf (lua_State *L\n #define lua_isboolean(L,n)\t(lua_type(L, (n)) == LUA_TBOOLEAN)\n #define lua_isthread(L,n)\t(lua_type(L, (n)) == LUA_TTHREAD)\n #define lua_isnone(L,n)\t\t(lua_type(L, (n)) == LUA_TNONE)\n-#define lua_isnoneornil(L, n)\t(lua_type(L, (n)) <= 0)\n+\n+#if LUA_TINT < 0\n+# define lua_isnoneornil(L, n)\t( (lua_type(L,(n)) <= 0) && (lua_type(L,(n)) != LUA_TINT) )\n+#else\n+# define lua_isnoneornil(L, n)\t(lua_type(L, (n)) <= 0)\n+#endif\n \n #define lua_pushliteral(L, s)\t\\\n \tlua_pushlstring(L, \"\" s, (sizeof(s)/sizeof(char))-1)\n@@ -386,3 +416,4 @@ struct lua_Debug {\n \n \n #endif\n+\n--- a/src/luaconf.h\n+++ b/src/luaconf.h\n@@ -10,7 +10,9 @@\n \n #include <limits.h>\n #include <stddef.h>\n-\n+#ifdef lua_assert\n+# include <assert.h>\n+#endif\n \n /*\n ** ==================================================================\n@@ -136,14 +138,38 @@\n \n \n /*\n-@@ LUA_INTEGER is the integral type used by lua_pushinteger/lua_tointeger.\n-** CHANGE that if ptrdiff_t is not adequate on your machine. (On most\n-** machines, ptrdiff_t gives a good choice between int or long.)\n+@@ LUAI_BITSINT defines the number of bits in an int.\n+** CHANGE here if Lua cannot automatically detect the number of bits of\n+** your machine. Probably you do not need to change this.\n */\n-#define LUA_INTEGER\tptrdiff_t\n+/* avoid overflows in comparison */\n+#if INT_MAX-20 < 32760\n+#define LUAI_BITSINT\t16\n+#elif INT_MAX > 2147483640L\n+/* int has at least 32 bits */\n+#define LUAI_BITSINT\t32\n+#else\n+#error \"you must define LUA_BITSINT with number of bits in an integer\"\n+#endif\n \n \n /*\n+@@ LNUM_DOUBLE | LNUM_FLOAT | LNUM_LDOUBLE: Generic Lua number mode\n+@@ LNUM_INT32 | LNUM_INT64: Integer type\n+@@ LNUM_COMPLEX: Define for using 'a+bi' numbers\n+@@\n+@@ You can combine LNUM_xxx but only one of each group. I.e. '-DLNUM_FLOAT\n+@@ -DLNUM_INT32 -DLNUM_COMPLEX' gives float range complex numbers, with \n+@@ 32-bit scalar integer range optimized.\n+**\n+** These are kept in a separate configuration file mainly for ease of patching\n+** (can be changed if integerated to Lua proper).\n+*/\n+/*#define LNUM_DOUBLE*/\n+/*#define LNUM_INT32*/\n+#include \"lnum_config.h\"\n+\n+/*\n @@ LUA_API is a mark for all core API functions.\n @@ LUALIB_API is a mark for all standard library functions.\n ** CHANGE them if you need to define those functions in some special way.\n@@ -383,22 +409,6 @@\n \n \n /*\n-@@ LUAI_BITSINT defines the number of bits in an int.\n-** CHANGE here if Lua cannot automatically detect the number of bits of\n-** your machine. Probably you do not need to change this.\n-*/\n-/* avoid overflows in comparison */\n-#if INT_MAX-20 < 32760\n-#define LUAI_BITSINT\t16\n-#elif INT_MAX > 2147483640L\n-/* int has at least 32 bits */\n-#define LUAI_BITSINT\t32\n-#else\n-#error \"you must define LUA_BITSINT with number of bits in an integer\"\n-#endif\n-\n-\n-/*\n @@ LUAI_UINT32 is an unsigned integer with at least 32 bits.\n @@ LUAI_INT32 is an signed integer with at least 32 bits.\n @@ LUAI_UMEM is an unsigned integer big enough to count the total\n@@ -425,6 +435,15 @@\n #define LUAI_MEM\tlong\n #endif\n \n+/*\n+@@ LUAI_BOOL carries 0 and nonzero (normally 1). It may be defined as 'char'\n+** (to save memory), 'int' (for speed), 'bool' (for C++) or '_Bool' (C99)\n+*/\n+#ifdef __cplusplus\n+# define LUAI_BOOL bool\n+#else\n+# define LUAI_BOOL int\n+#endif\n \n /*\n @@ LUAI_MAXCALLS limits the number of nested calls.\n@@ -490,101 +509,6 @@\n /* }================================================================== */\n \n \n-\n-\n-/*\n-** {==================================================================\n-@@ LUA_NUMBER is the type of numbers in Lua.\n-** CHANGE the following definitions only if you want to build Lua\n-** with a number type different from double. You may also need to\n-** change lua_number2int & lua_number2integer.\n-** ===================================================================\n-*/\n-\n-#define LUA_NUMBER_DOUBLE\n-#define LUA_NUMBER\tdouble\n-\n-/*\n-@@ LUAI_UACNUMBER is the result of an 'usual argument conversion'\n-@* over a number.\n-*/\n-#define LUAI_UACNUMBER\tdouble\n-\n-\n-/*\n-@@ LUA_NUMBER_SCAN is the format for reading numbers.\n-@@ LUA_NUMBER_FMT is the format for writing numbers.\n-@@ lua_number2str converts a number to a string.\n-@@ LUAI_MAXNUMBER2STR is maximum size of previous conversion.\n-@@ lua_str2number converts a string to a number.\n-*/\n-#define LUA_NUMBER_SCAN\t\t\"%lf\"\n-#define LUA_NUMBER_FMT\t\t\"%.14g\"\n-#define lua_number2str(s,n)\tsprintf((s), LUA_NUMBER_FMT, (n))\n-#define LUAI_MAXNUMBER2STR\t32 /* 16 digits, sign, point, and \\0 */\n-#define lua_str2number(s,p)\tstrtod((s), (p))\n-\n-\n-/*\n-@@ The luai_num* macros define the primitive operations over numbers.\n-*/\n-#if defined(LUA_CORE)\n-#include <math.h>\n-#define luai_numadd(a,b)\t((a)+(b))\n-#define luai_numsub(a,b)\t((a)-(b))\n-#define luai_nummul(a,b)\t((a)*(b))\n-#define luai_numdiv(a,b)\t((a)/(b))\n-#define luai_nummod(a,b)\t((a) - floor((a)/(b))*(b))\n-#define luai_numpow(a,b)\t(pow(a,b))\n-#define luai_numunm(a)\t\t(-(a))\n-#define luai_numeq(a,b)\t\t((a)==(b))\n-#define luai_numlt(a,b)\t\t((a)<(b))\n-#define luai_numle(a,b)\t\t((a)<=(b))\n-#define luai_numisnan(a)\t(!luai_numeq((a), (a)))\n-#endif\n-\n-\n-/*\n-@@ lua_number2int is a macro to convert lua_Number to int.\n-@@ lua_number2integer is a macro to convert lua_Number to lua_Integer.\n-** CHANGE them if you know a faster way to convert a lua_Number to\n-** int (with any rounding method and without throwing errors) in your\n-** system. In Pentium machines, a naive typecast from double to int\n-** in C is extremely slow, so any alternative is worth trying.\n-*/\n-\n-/* On a Pentium, resort to a trick */\n-#if defined(LUA_NUMBER_DOUBLE) && !defined(LUA_ANSI) && !defined(__SSE2__) && \\\n-    (defined(__i386) || defined (_M_IX86) || defined(__i386__))\n-\n-/* On a Microsoft compiler, use assembler */\n-#if defined(_MSC_VER)\n-\n-#define lua_number2int(i,d)   __asm fld d   __asm fistp i\n-#define lua_number2integer(i,n)\t\tlua_number2int(i, n)\n-\n-/* the next trick should work on any Pentium, but sometimes clashes\n-   with a DirectX idiosyncrasy */\n-#else\n-\n-union luai_Cast { double l_d; long l_l; };\n-#define lua_number2int(i,d) \\\n-  { volatile union luai_Cast u; u.l_d = (d) + 6755399441055744.0; (i) = u.l_l; }\n-#define lua_number2integer(i,n)\t\tlua_number2int(i, n)\n-\n-#endif\n-\n-\n-/* this option always works, but may be slow */\n-#else\n-#define lua_number2int(i,d)\t((i)=(int)(d))\n-#define lua_number2integer(i,d)\t((i)=(lua_Integer)(d))\n-\n-#endif\n-\n-/* }================================================================== */\n-\n-\n /*\n @@ LUAI_USER_ALIGNMENT_T is a type that requires maximum alignment.\n ** CHANGE it if your system requires alignments larger than double. (For\n@@ -728,28 +652,6 @@ union luai_Cast { double l_d; long l_l;\n #define luai_userstateyield(L,n)\t((void)L)\n \n \n-/*\n-@@ LUA_INTFRMLEN is the length modifier for integer conversions\n-@* in 'string.format'.\n-@@ LUA_INTFRM_T is the integer type correspoding to the previous length\n-@* modifier.\n-** CHANGE them if your system supports long long or does not support long.\n-*/\n-\n-#if defined(LUA_USELONGLONG)\n-\n-#define LUA_INTFRMLEN\t\t\"ll\"\n-#define LUA_INTFRM_T\t\tlong long\n-\n-#else\n-\n-#define LUA_INTFRMLEN\t\t\"l\"\n-#define LUA_INTFRM_T\t\tlong\n-\n-#endif\n-\n-\n-\n /* =================================================================== */\n \n /*\n--- a/src/lundump.c\n+++ b/src/lundump.c\n@@ -73,6 +73,13 @@ static lua_Number LoadNumber(LoadState*\n  return x;\n }\n \n+static lua_Integer LoadInteger(LoadState* S)\n+{\n+ lua_Integer x;\n+ LoadVar(S,x);\n+ return x;\n+}\n+\n static TString* LoadString(LoadState* S)\n {\n  size_t size;\n@@ -119,6 +126,9 @@ static void LoadConstants(LoadState* S,\n    case LUA_TNUMBER:\n \tsetnvalue(o,LoadNumber(S));\n \tbreak;\n+   case LUA_TINT:   /* Integer type saved in bytecode (see lcode.c) */\n+\tsetivalue(o,LoadInteger(S));\n+\tbreak;\n    case LUA_TSTRING:\n \tsetsvalue2n(S->L,o,LoadString(S));\n \tbreak;\n@@ -223,5 +233,22 @@ void luaU_header (char* h)\n  *h++=(char)sizeof(size_t);\n  *h++=(char)sizeof(Instruction);\n  *h++=(char)sizeof(lua_Number);\n- *h++=(char)(((lua_Number)0.5)==0);\t\t/* is lua_Number integral? */\n+\n+ /* \n+  * Last byte of header (0/1 in unpatched Lua 5.1.3):\n+  *\n+  * 0: lua_Number is float or double, lua_Integer not used. (nonpatched only)\n+  * 1: lua_Number is integer (nonpatched only)\n+  *\n+  * +2: LNUM_INT16: sizeof(lua_Integer)\n+  * +4: LNUM_INT32: sizeof(lua_Integer)\n+  * +8: LNUM_INT64: sizeof(lua_Integer)\n+  *\n+  * +0x80: LNUM_COMPLEX\n+  */\n+ *h++ = (char)(sizeof(lua_Integer)\n+#ifdef LNUM_COMPLEX\n+    | 0x80\n+#endif\n+    );\n }\n--- a/src/lvm.c\n+++ b/src/lvm.c\n@@ -25,22 +25,35 @@\n #include \"ltable.h\"\n #include \"ltm.h\"\n #include \"lvm.h\"\n-\n-\n+#include \"llex.h\"\n+#include \"lnum.h\"\n \n /* limit for table tag-method chains (to avoid loops) */\n #define MAXTAGLOOP\t100\n \n \n-const TValue *luaV_tonumber (const TValue *obj, TValue *n) {\n-  lua_Number num;\n+/*\n+ * If 'obj' is a string, it is tried to be interpreted as a number.\n+ */\n+const TValue *luaV_tonumber ( const TValue *obj, TValue *n) {\n+  lua_Number d;\n+  lua_Integer i;\n+  \n   if (ttisnumber(obj)) return obj;\n-  if (ttisstring(obj) && luaO_str2d(svalue(obj), &num)) {\n-    setnvalue(n, num);\n-    return n;\n-  }\n-  else\n-    return NULL;\n+\n+  if (ttisstring(obj)) {\n+    switch( luaO_str2d( svalue(obj), &d, &i ) ) {\n+        case TK_INT:\n+            setivalue(n,i); return n;\n+        case TK_NUMBER: \n+            setnvalue(n,d); return n;\n+#ifdef LNUM_COMPLEX\n+        case TK_NUMBER2:    /* \"N.NNNi\", != 0 */\n+            setnvalue_complex_fast(n, d*I); return n;\n+#endif\n+        }\n+    }\n+  return NULL;\n }\n \n \n@@ -49,8 +62,7 @@ int luaV_tostring (lua_State *L, StkId o\n     return 0;\n   else {\n     char s[LUAI_MAXNUMBER2STR];\n-    lua_Number n = nvalue(obj);\n-    lua_number2str(s, n);\n+    luaO_num2buf(s,obj);\n     setsvalue2s(L, obj, luaS_new(L, s));\n     return 1;\n   }\n@@ -222,59 +234,127 @@ static int l_strcmp (const TString *ls,\n }\n \n \n+#ifdef LNUM_COMPLEX\n+void error_complex( lua_State *L, const TValue *l, const TValue *r )\n+{\n+  char buf1[ LUAI_MAXNUMBER2STR ];\n+  char buf2[ LUAI_MAXNUMBER2STR ];\n+  luaO_num2buf( buf1, l );\n+  luaO_num2buf( buf2, r );\n+  luaG_runerror( L, \"unable to compare: %s with %s\", buf1, buf2 );\n+  /* no return */\n+}\n+#endif\n+\n+\n int luaV_lessthan (lua_State *L, const TValue *l, const TValue *r) {\n   int res;\n-  if (ttype(l) != ttype(r))\n+  int tl,tr;\n+  lua_Integer tmp;\n+\n+  if (!ttype_ext_same(l,r))\n     return luaG_ordererror(L, l, r);\n-  else if (ttisnumber(l))\n-    return luai_numlt(nvalue(l), nvalue(r));\n-  else if (ttisstring(l))\n-    return l_strcmp(rawtsvalue(l), rawtsvalue(r)) < 0;\n-  else if ((res = call_orderTM(L, l, r, TM_LT)) != -1)\n+#ifdef LNUM_COMPLEX\n+  if ( (nvalue_img(l)!=0) || (nvalue_img(r)!=0) )\n+    error_complex( L, l, r );\n+#endif\n+  tl= ttype(l); tr= ttype(r);\n+  if (tl==tr) {  /* clear arithmetics */\n+    switch(tl) {\n+      case LUA_TINT:      return ivalue(l) < ivalue(r);\n+      case LUA_TNUMBER:   return luai_numlt(nvalue_fast(l), nvalue_fast(r));\n+      case LUA_TSTRING:   return l_strcmp(rawtsvalue(l), rawtsvalue(r)) < 0;\n+    }\n+  } else if (tl==LUA_TINT) {  /* l:int, r:num */\n+    /* Avoid accuracy losing casts: if 'r' is integer by value, do comparisons\n+     * in integer realm. Only otherwise cast 'l' to FP (which might change its\n+     * value).\n+     */\n+    if (tt_integer_valued(r,&tmp)) \n+        return ivalue(l) < tmp;\n+    else \n+        return luai_numlt( cast_num(ivalue(l)), nvalue_fast(r) );\n+\n+  } else if (tl==LUA_TNUMBER) {  /* l:num, r:int */\n+    if (tt_integer_valued(l,&tmp)) \n+        return tmp < ivalue(r);\n+    else\n+        return luai_numlt( nvalue_fast(l), cast_num(ivalue(r)) );\n+\n+  } else if ((res = call_orderTM(L, l, r, TM_LT)) != -1)\n     return res;\n+\n   return luaG_ordererror(L, l, r);\n }\n \n \n static int lessequal (lua_State *L, const TValue *l, const TValue *r) {\n   int res;\n-  if (ttype(l) != ttype(r))\n+  int tl, tr;\n+  lua_Integer tmp;\n+\n+  if (!ttype_ext_same(l,r))\n     return luaG_ordererror(L, l, r);\n-  else if (ttisnumber(l))\n-    return luai_numle(nvalue(l), nvalue(r));\n-  else if (ttisstring(l))\n-    return l_strcmp(rawtsvalue(l), rawtsvalue(r)) <= 0;\n-  else if ((res = call_orderTM(L, l, r, TM_LE)) != -1)  /* first try `le' */\n+#ifdef LNUM_COMPLEX\n+  if ( (nvalue_img(l)!=0) || (nvalue_img(r)!=0) )\n+    error_complex( L, l, r );\n+#endif\n+  tl= ttype(l); tr= ttype(r);\n+  if (tl==tr) {  /* clear arithmetics */\n+    switch(tl) {\n+      case LUA_TINT:      return ivalue(l) <= ivalue(r);\n+      case LUA_TNUMBER:   return luai_numle(nvalue_fast(l), nvalue_fast(r));\n+      case LUA_TSTRING:   return l_strcmp(rawtsvalue(l), rawtsvalue(r)) <= 0;\n+    }\n+  }\n+  if (tl==LUA_TINT) {  /* l:int, r:num */\n+    if (tt_integer_valued(r,&tmp)) \n+        return ivalue(l) <= tmp;\n+    else\n+        return luai_numle( cast_num(ivalue(l)), nvalue_fast(r) );\n+\n+  } else if (tl==LUA_TNUMBER) {  /* l:num, r:int */\n+    if (tt_integer_valued(l,&tmp)) \n+        return tmp <= ivalue(r);\n+    else\n+        return luai_numle( nvalue_fast(l), cast_num(ivalue(r)) );\n+\n+  } else if ((res = call_orderTM(L, l, r, TM_LE)) != -1)  /* first try `le' */\n     return res;\n   else if ((res = call_orderTM(L, r, l, TM_LT)) != -1)  /* else try `lt' */\n     return !res;\n+\n   return luaG_ordererror(L, l, r);\n }\n \n \n-int luaV_equalval (lua_State *L, const TValue *t1, const TValue *t2) {\n+/* Note: 'luaV_equalval()' and 'luaO_rawequalObj()' have largely overlapping\n+ *       implementation. LUA_TNIL..LUA_TLIGHTUSERDATA cases could be handled\n+ *       simply by the 'default' case here.\n+ */\n+int luaV_equalval (lua_State *L, const TValue *l, const TValue *r) {\n   const TValue *tm;\n-  lua_assert(ttype(t1) == ttype(t2));\n-  switch (ttype(t1)) {\n+  lua_assert(ttype_ext_same(l,r));\n+  switch (ttype(l)) {\n     case LUA_TNIL: return 1;\n-    case LUA_TNUMBER: return luai_numeq(nvalue(t1), nvalue(t2));\n-    case LUA_TBOOLEAN: return bvalue(t1) == bvalue(t2);  /* true must be 1 !! */\n-    case LUA_TLIGHTUSERDATA: return pvalue(t1) == pvalue(t2);\n+    case LUA_TINT:\n+    case LUA_TNUMBER: return luaO_rawequalObj(l,r);\n+    case LUA_TBOOLEAN: return bvalue(l) == bvalue(r);  /* true must be 1 !! */\n+    case LUA_TLIGHTUSERDATA: return pvalue(l) == pvalue(r);\n     case LUA_TUSERDATA: {\n-      if (uvalue(t1) == uvalue(t2)) return 1;\n-      tm = get_compTM(L, uvalue(t1)->metatable, uvalue(t2)->metatable,\n-                         TM_EQ);\n+      if (uvalue(l) == uvalue(r)) return 1;\n+      tm = get_compTM(L, uvalue(l)->metatable, uvalue(r)->metatable, TM_EQ);\n       break;  /* will try TM */\n     }\n     case LUA_TTABLE: {\n-      if (hvalue(t1) == hvalue(t2)) return 1;\n-      tm = get_compTM(L, hvalue(t1)->metatable, hvalue(t2)->metatable, TM_EQ);\n+      if (hvalue(l) == hvalue(r)) return 1;\n+      tm = get_compTM(L, hvalue(l)->metatable, hvalue(r)->metatable, TM_EQ);\n       break;  /* will try TM */\n     }\n-    default: return gcvalue(t1) == gcvalue(t2);\n+    default: return gcvalue(l) == gcvalue(r);\n   }\n   if (tm == NULL) return 0;  /* no TM? */\n-  callTMres(L, L->top, tm, t1, t2);  /* call TM */\n+  callTMres(L, L->top, tm, l, r);  /* call TM */\n   return !l_isfalse(L->top);\n }\n \n@@ -314,30 +394,6 @@ void luaV_concat (lua_State *L, int tota\n }\n \n \n-static void Arith (lua_State *L, StkId ra, const TValue *rb,\n-                   const TValue *rc, TMS op) {\n-  TValue tempb, tempc;\n-  const TValue *b, *c;\n-  if ((b = luaV_tonumber(rb, &tempb)) != NULL &&\n-      (c = luaV_tonumber(rc, &tempc)) != NULL) {\n-    lua_Number nb = nvalue(b), nc = nvalue(c);\n-    switch (op) {\n-      case TM_ADD: setnvalue(ra, luai_numadd(nb, nc)); break;\n-      case TM_SUB: setnvalue(ra, luai_numsub(nb, nc)); break;\n-      case TM_MUL: setnvalue(ra, luai_nummul(nb, nc)); break;\n-      case TM_DIV: setnvalue(ra, luai_numdiv(nb, nc)); break;\n-      case TM_MOD: setnvalue(ra, luai_nummod(nb, nc)); break;\n-      case TM_POW: setnvalue(ra, luai_numpow(nb, nc)); break;\n-      case TM_UNM: setnvalue(ra, luai_numunm(nb)); break;\n-      default: lua_assert(0); break;\n-    }\n-  }\n-  else if (!call_binTM(L, rb, rc, ra, op))\n-    luaG_aritherror(L, rb, rc);\n-}\n-\n-\n-\n /*\n ** some macros for common tasks in `luaV_execute'\n */\n@@ -361,17 +417,154 @@ static void Arith (lua_State *L, StkId r\n #define Protect(x)\t{ L->savedpc = pc; {x;}; base = L->base; }\n \n \n-#define arith_op(op,tm) { \\\n-        TValue *rb = RKB(i); \\\n-        TValue *rc = RKC(i); \\\n-        if (ttisnumber(rb) && ttisnumber(rc)) { \\\n-          lua_Number nb = nvalue(rb), nc = nvalue(rc); \\\n-          setnvalue(ra, op(nb, nc)); \\\n-        } \\\n-        else \\\n-          Protect(Arith(L, ra, rb, rc, tm)); \\\n+/* Note: if called for unary operations, 'rc'=='rb'.\n+ */\n+static void Arith (lua_State *L, StkId ra, const TValue *rb,\n+                   const TValue *rc, TMS op) {\n+  TValue tempb, tempc;\n+  const TValue *b, *c;\n+  lua_Number nb,nc;\n+\n+  if ((b = luaV_tonumber(rb, &tempb)) != NULL &&\n+      (c = luaV_tonumber(rc, &tempc)) != NULL) {\n+\n+    /* Keep integer arithmetics in the integer realm, if possible.\n+     */\n+    if (ttisint(b) && ttisint(c)) {\n+      lua_Integer ib = ivalue(b), ic = ivalue(c);\n+      lua_Integer *ri = &ra->value.i;\n+      ra->tt= LUA_TINT;  /* part of 'setivalue(ra)' */\n+      switch (op) {\n+        case TM_ADD: if (try_addint( ri, ib, ic)) return; break;\n+        case TM_SUB: if (try_subint( ri, ib, ic)) return; break;\n+        case TM_MUL: if (try_mulint( ri, ib, ic)) return; break;\n+        case TM_DIV: if (try_divint( ri, ib, ic)) return; break;\n+        case TM_MOD: if (try_modint( ri, ib, ic)) return; break;\n+        case TM_POW: if (try_powint( ri, ib, ic)) return; break;\n+        case TM_UNM: if (try_unmint( ri, ib)) return; break;\n+        default: lua_assert(0);\n       }\n+    }\n+    /* Fallback to floating point, when leaving range. */\n \n+#ifdef LNUM_COMPLEX\n+    if ((nvalue_img(b)!=0) || (nvalue_img(c)!=0)) {\n+      lua_Complex r;\n+      if (op==TM_UNM) {\n+        r= -nvalue_complex_fast(b);     /* never an integer (or scalar) */\n+        setnvalue_complex_fast( ra, r );\n+      } else {\n+        lua_Complex bb= nvalue_complex(b), cc= nvalue_complex(c);\n+        switch (op) {\n+          case TM_ADD: r= bb + cc; break;\n+          case TM_SUB: r= bb - cc; break;\n+          case TM_MUL: r= bb * cc; break;\n+          case TM_DIV: r= bb / cc; break;\n+          case TM_MOD: \n+            luaG_runerror(L, \"attempt to use %% on complex numbers\");  /* no return */\n+          case TM_POW: r= luai_vectpow( bb, cc ); break;\n+          default: lua_assert(0); r=0;\n+        }\n+        setnvalue_complex( ra, r );\n+      }\n+      return;\n+    }\n+#endif\n+    nb = nvalue(b); nc = nvalue(c);\n+    switch (op) {\n+      case TM_ADD: setnvalue(ra, luai_numadd(nb, nc)); return;\n+      case TM_SUB: setnvalue(ra, luai_numsub(nb, nc)); return;\n+      case TM_MUL: setnvalue(ra, luai_nummul(nb, nc)); return;\n+      case TM_DIV: setnvalue(ra, luai_numdiv(nb, nc)); return;\n+      case TM_MOD: setnvalue(ra, luai_nummod(nb, nc)); return;\n+      case TM_POW: setnvalue(ra, luai_numpow(nb, nc)); return;\n+      case TM_UNM: setnvalue(ra, luai_numunm(nb)); return;\n+      default: lua_assert(0);\n+    }\n+  }\n+  \n+  /* Either operand not a number */\n+  if (!call_binTM(L, rb, rc, ra, op))\n+    luaG_aritherror(L, rb, rc);\n+}\n+\n+/* Helper macro to sort arithmetic operations into four categories:\n+ *  TK_INT: integer - integer operands\n+ *  TK_NUMBER: number - number (non complex, either may be integer)\n+ *  TK_NUMBER2: complex numbers (at least the other)\n+ *  0: non-numeric (at least the other)\n+*/\n+#ifdef LNUM_COMPLEX\n+static inline int arith_mode( const TValue *rb, const TValue *rc ) {\n+  if (ttisint(rb) && ttisint(rc)) return TK_INT;\n+  if (ttiscomplex(rb) || ttiscomplex(rc)) return TK_NUMBER2;\n+  if (ttisnumber(rb) && ttisnumber(rc)) return TK_NUMBER;\n+  return 0;\n+}\n+#else\n+# define arith_mode(rb,rc) \\\n+    ( (ttisint(rb) && ttisint(rc)) ? TK_INT : \\\n+      (ttisnumber(rb) && ttisnumber(rc)) ? TK_NUMBER : 0 )\n+#endif\n+\n+/* arith_op macro for two operators:\n+ * automatically chooses, which function (number, integer, complex) to use\n+ */\n+#define ARITH_OP2_START( op_num, op_int ) \\\n+  int failed= 0; \\\n+  switch( arith_mode(rb,rc) ) { \\\n+    case TK_INT: \\\n+      if (op_int ( &(ra)->value.i, ivalue(rb), ivalue(rc) )) \\\n+        { ra->tt= LUA_TINT; break; } /* else flow through */ \\\n+    case TK_NUMBER: \\\n+      setnvalue(ra, op_num ( nvalue(rb), nvalue(rc) )); break;\n+\n+#define ARITH_OP2_END \\\n+    default: \\\n+      failed= 1; break; \\\n+  } if (!failed) continue;\n+\n+#define arith_op_continue_scalar( op_num, op_int ) \\\n+    ARITH_OP2_START( op_num, op_int ) \\\n+    ARITH_OP2_END\n+\n+#ifdef LNUM_COMPLEX\n+# define arith_op_continue( op_num, op_int, op_complex ) \\\n+    ARITH_OP2_START( op_num, op_int ) \\\n+      case TK_NUMBER2: \\\n+        setnvalue_complex( ra, op_complex ( nvalue_complex(rb), nvalue_complex(rc) ) ); break; \\\n+    ARITH_OP2_END\n+#else\n+# define arith_op_continue(op_num,op_int,_) arith_op_continue_scalar(op_num,op_int)\n+#endif\n+\n+/* arith_op macro for one operator:\n+ */\n+#define ARITH_OP1_START( op_num, op_int ) \\\n+  int failed= 0; \\\n+  switch( arith_mode(rb,rb) ) { \\\n+    case TK_INT: \\\n+      if (op_int ( &(ra)->value.i, ivalue(rb) )) \\\n+        { ra->tt= LUA_TINT; break; } /* else flow through */ \\\n+      case TK_NUMBER: \\\n+        setnvalue(ra, op_num (nvalue(rb))); break; \\\n+\n+#define ARITH_OP1_END \\\n+      default: \\\n+        failed= 1; break; \\\n+  } if (!failed) continue;\n+\n+#ifdef LNUM_COMPLEX\n+# define arith_op1_continue( op_num, op_int, op_complex ) \\\n+    ARITH_OP1_START( op_num, op_int ) \\\n+      case TK_NUMBER2: \\\n+        setnvalue_complex( ra, op_complex ( nvalue_complex_fast(rb) )); break; \\\n+    ARITH_OP1_END\n+#else\n+# define arith_op1_continue( op_num, op_int, _ ) \\\n+    ARITH_OP1_START( op_num, op_int ) \\\n+    ARITH_OP1_END\n+#endif\n \n \n void luaV_execute (lua_State *L, int nexeccalls) {\n@@ -472,38 +665,45 @@ void luaV_execute (lua_State *L, int nex\n         continue;\n       }\n       case OP_ADD: {\n-        arith_op(luai_numadd, TM_ADD);\n+        TValue *rb = RKB(i), *rc= RKC(i);\n+        arith_op_continue( luai_numadd, try_addint, luai_vectadd );\n+        Protect(Arith(L, ra, rb, rc, TM_ADD)); \\\n         continue;\n       }\n       case OP_SUB: {\n-        arith_op(luai_numsub, TM_SUB);\n+        TValue *rb = RKB(i), *rc= RKC(i);\n+        arith_op_continue( luai_numsub, try_subint, luai_vectsub );\n+        Protect(Arith(L, ra, rb, rc, TM_SUB));\n         continue;\n       }\n       case OP_MUL: {\n-        arith_op(luai_nummul, TM_MUL);\n+        TValue *rb = RKB(i), *rc= RKC(i);\n+        arith_op_continue(luai_nummul, try_mulint, luai_vectmul);\n+        Protect(Arith(L, ra, rb, rc, TM_MUL));\n         continue;\n       }\n       case OP_DIV: {\n-        arith_op(luai_numdiv, TM_DIV);\n+        TValue *rb = RKB(i), *rc= RKC(i);\n+        arith_op_continue(luai_numdiv, try_divint, luai_vectdiv);\n+        Protect(Arith(L, ra, rb, rc, TM_DIV));\n         continue;\n       }\n       case OP_MOD: {\n-        arith_op(luai_nummod, TM_MOD);\n+        TValue *rb = RKB(i), *rc= RKC(i);\n+        arith_op_continue_scalar(luai_nummod, try_modint);  /* scalars only */\n+        Protect(Arith(L, ra, rb, rc, TM_MOD));\n         continue;\n       }\n       case OP_POW: {\n-        arith_op(luai_numpow, TM_POW);\n+        TValue *rb = RKB(i), *rc= RKC(i);\n+        arith_op_continue(luai_numpow, try_powint, luai_vectpow);\n+        Protect(Arith(L, ra, rb, rc, TM_POW));\n         continue;\n       }\n       case OP_UNM: {\n         TValue *rb = RB(i);\n-        if (ttisnumber(rb)) {\n-          lua_Number nb = nvalue(rb);\n-          setnvalue(ra, luai_numunm(nb));\n-        }\n-        else {\n-          Protect(Arith(L, ra, rb, rb, TM_UNM));\n-        }\n+        arith_op1_continue(luai_numunm, try_unmint, luai_vectunm);\n+        Protect(Arith(L, ra, rb, rb, TM_UNM));\n         continue;\n       }\n       case OP_NOT: {\n@@ -515,11 +715,11 @@ void luaV_execute (lua_State *L, int nex\n         const TValue *rb = RB(i);\n         switch (ttype(rb)) {\n           case LUA_TTABLE: {\n-            setnvalue(ra, cast_num(luaH_getn(hvalue(rb))));\n+            setivalue(ra, luaH_getn(hvalue(rb)));\n             break;\n           }\n           case LUA_TSTRING: {\n-            setnvalue(ra, cast_num(tsvalue(rb)->len));\n+            setivalue(ra, tsvalue(rb)->len);\n             break;\n           }\n           default: {  /* try metamethod */\n@@ -652,14 +852,30 @@ void luaV_execute (lua_State *L, int nex\n         }\n       }\n       case OP_FORLOOP: {\n-        lua_Number step = nvalue(ra+2);\n-        lua_Number idx = luai_numadd(nvalue(ra), step); /* increment index */\n-        lua_Number limit = nvalue(ra+1);\n-        if (luai_numlt(0, step) ? luai_numle(idx, limit)\n-                                : luai_numle(limit, idx)) {\n-          dojump(L, pc, GETARG_sBx(i));  /* jump back */\n-          setnvalue(ra, idx);  /* update internal index... */\n-          setnvalue(ra+3, idx);  /* ...and external index */\n+        /* If start,step and limit are all integers, we don't need to check\n+         * against overflow in the looping.\n+         */\n+        if (ttisint(ra) && ttisint(ra+1) && ttisint(ra+2)) {\n+          lua_Integer step = ivalue(ra+2);\n+          lua_Integer idx = ivalue(ra) + step; /* increment index */\n+          lua_Integer limit = ivalue(ra+1);\n+          if (step > 0 ? (idx <= limit) : (limit <= idx)) {\n+            dojump(L, pc, GETARG_sBx(i));  /* jump back */\n+            setivalue(ra, idx);  /* update internal index... */\n+            setivalue(ra+3, idx);  /* ...and external index */\n+          }\n+        } else {\n+          /* non-integer looping (don't use 'nvalue_fast', some may be integer!) \n+          */\n+          lua_Number step = nvalue(ra+2);\n+          lua_Number idx = luai_numadd(nvalue(ra), step); /* increment index */\n+          lua_Number limit = nvalue(ra+1);\n+          if (luai_numlt(0, step) ? luai_numle(idx, limit)\n+                                  : luai_numle(limit, idx)) {\n+            dojump(L, pc, GETARG_sBx(i));  /* jump back */\n+            setnvalue(ra, idx);  /* update internal index... */\n+            setnvalue(ra+3, idx);  /* ...and external index */\n+          }\n         }\n         continue;\n       }\n@@ -668,13 +884,21 @@ void luaV_execute (lua_State *L, int nex\n         const TValue *plimit = ra+1;\n         const TValue *pstep = ra+2;\n         L->savedpc = pc;  /* next steps may throw errors */\n+        /* Using same location for tonumber's both arguments, effectively does\n+         * in-place modification (string->number). */\n         if (!tonumber(init, ra))\n           luaG_runerror(L, LUA_QL(\"for\") \" initial value must be a number\");\n         else if (!tonumber(plimit, ra+1))\n           luaG_runerror(L, LUA_QL(\"for\") \" limit must be a number\");\n         else if (!tonumber(pstep, ra+2))\n           luaG_runerror(L, LUA_QL(\"for\") \" step must be a number\");\n-        setnvalue(ra, luai_numsub(nvalue(ra), nvalue(pstep)));\n+        /* Step back one value (keep within integers if we can)\n+         */\n+        if (!( ttisint(ra) && ttisint(pstep) &&\n+               try_subint( &ra->value.i, ivalue(ra), ivalue(pstep) ) )) {\n+            /* don't use 'nvalue_fast()', values may be integer */\n+            setnvalue(ra, luai_numsub(nvalue(ra), nvalue(pstep)));\n+        }\n         dojump(L, pc, GETARG_sBx(i));\n         continue;\n       }\n@@ -711,7 +935,7 @@ void luaV_execute (lua_State *L, int nex\n           luaH_resizearray(L, h, last);  /* pre-alloc it at once */\n         for (; n > 0; n--) {\n           TValue *val = ra+n;\n-          setobj2t(L, luaH_setnum(L, h, last--), val);\n+          setobj2t(L, luaH_setint(L, h, last--), val);\n           luaC_barriert(L, h, val);\n         }\n         continue;\n--- a/src/lvm.h\n+++ b/src/lvm.h\n@@ -15,11 +15,9 @@\n \n #define tostring(L,o) ((ttype(o) == LUA_TSTRING) || (luaV_tostring(L, o)))\n \n-#define tonumber(o,n)\t(ttype(o) == LUA_TNUMBER || \\\n-                         (((o) = luaV_tonumber(o,n)) != NULL))\n+#define tonumber(o,n) (ttisnumber(o) || (((o) = luaV_tonumber(o,n)) != NULL))\n \n-#define equalobj(L,o1,o2) \\\n-\t(ttype(o1) == ttype(o2) && luaV_equalval(L, o1, o2))\n+#define equalobj(L,o1,o2) (ttype_ext_same(o1,o2) && luaV_equalval(L, o1, o2))\n \n \n LUAI_FUNC int luaV_lessthan (lua_State *L, const TValue *l, const TValue *r);\n--- a/src/print.c\n+++ b/src/print.c\n@@ -14,6 +14,7 @@\n #include \"lobject.h\"\n #include \"lopcodes.h\"\n #include \"lundump.h\"\n+#include \"lnum.h\"\n \n #define PrintFunction\tluaU_print\n \n@@ -59,8 +60,16 @@ static void PrintConstant(const Proto* f\n   case LUA_TBOOLEAN:\n \tprintf(bvalue(o) ? \"true\" : \"false\");\n \tbreak;\n+  case LUA_TINT:\n+\tprintf(LUA_INTEGER_FMT,ivalue(o));\n+\tbreak;\n   case LUA_TNUMBER:\n-\tprintf(LUA_NUMBER_FMT,nvalue(o));\n+#ifdef LNUM_COMPLEX\n+    // TBD: Do we get complex values here?\n+    { lua_Number b= nvalue_img_fast(o);\n+\t  printf( LUA_NUMBER_FMT \"%s\" LUA_NUMBER_FMT \"i\", nvalue_fast(o), b>=0 ? \"+\":\"\", b ); }\n+#endif\n+\tprintf(LUA_NUMBER_FMT,nvalue_fast(o));\n \tbreak;\n   case LUA_TSTRING:\n \tPrintString(rawtsvalue(o));\n"
  },
  {
    "path": "package/utils/lua/patches-host/011-lnum-use-double.patch",
    "content": "--- a/src/lnum_config.h\n+++ b/src/lnum_config.h\n@@ -11,7 +11,7 @@\n ** Default number modes\n */\n #if (!defined LNUM_DOUBLE) && (!defined LNUM_FLOAT) && (!defined LNUM_LDOUBLE)\n-# define LNUM_FLOAT\n+# define LNUM_DOUBLE\n #endif\n #if (!defined LNUM_INT16) && (!defined LNUM_INT32) && (!defined LNUM_INT64)\n # define LNUM_INT32\n"
  },
  {
    "path": "package/utils/lua/patches-host/012-lnum-fix-ltle-relational-operators.patch",
    "content": "--- a/src/lvm.c\n+++ b/src/lvm.c\n@@ -281,7 +281,8 @@ int luaV_lessthan (lua_State *L, const T\n     else\n         return luai_numlt( nvalue_fast(l), cast_num(ivalue(r)) );\n \n-  } else if ((res = call_orderTM(L, l, r, TM_LT)) != -1)\n+  } \n+  if ((res = call_orderTM(L, l, r, TM_LT)) != -1)\n     return res;\n \n   return luaG_ordererror(L, l, r);\n@@ -319,7 +320,8 @@ static int lessequal (lua_State *L, cons\n     else\n         return luai_numle( nvalue_fast(l), cast_num(ivalue(r)) );\n \n-  } else if ((res = call_orderTM(L, l, r, TM_LE)) != -1)  /* first try `le' */\n+  } \n+  if ((res = call_orderTM(L, l, r, TM_LE)) != -1)  /* first try `le' */\n     return res;\n   else if ((res = call_orderTM(L, r, l, TM_LT)) != -1)  /* else try `lt' */\n     return !res;\n"
  },
  {
    "path": "package/utils/lua/patches-host/013-lnum-strtoul-parsing-fixes.patch",
    "content": "diff --git a/src/lnum.c b/src/lnum.c\nindex 1456b6a2ed23..b0632b04c2b7 100644\n--- a/src/lnum.c\n+++ b/src/lnum.c\n@@ -127,6 +127,8 @@ static int luaO_str2i (const char *s, lua_Integer *res, char **endptr_ref) {\n #else\n       return 0;  /* Reject the number */\n #endif\n+    } else if (v > LUA_INTEGER_MAX) {\n+      return TK_NUMBER;\n     }\n   } else if ((v > LUA_INTEGER_MAX) || (*endptr && (!isspace(*endptr)))) {\n     return TK_NUMBER;\t/* not in signed range, or has '.', 'e' etc. trailing */\n@@ -310,3 +312,13 @@ int try_unmint( lua_Integer *r, lua_Integer ib ) {\n   return 0;\n }\n \n+#ifdef LONG_OVERFLOW_LUA_INTEGER\n+unsigned LUA_INTEGER lua_str2ul( const char *str, char **endptr, int base ) {\n+  unsigned long v= strtoul(str, endptr, base);\n+  if ( v > LUA_INTEGER_MAX ) {\n+    errno= ERANGE;\n+    v= ULONG_MAX;\n+  }\n+  return (unsigned LUA_INTEGER)v;\n+}\n+#endif\ndiff --git a/src/lnum_config.h b/src/lnum_config.h\nindex 19d7a4231a49..1092eead6629 100644\n--- a/src/lnum_config.h\n+++ b/src/lnum_config.h\n@@ -141,7 +141,12 @@\n #endif\n \n #ifndef lua_str2ul\n-# define lua_str2ul (unsigned LUA_INTEGER)strtoul\n+# if LONG_MAX > LUA_INTEGER_MAX\n+#   define LONG_OVERFLOW_LUA_INTEGER\n+    unsigned LUA_INTEGER lua_str2ul( const char *str, char **endptr, int base );\n+# else\n+#  define lua_str2ul (unsigned LUA_INTEGER)strtoul\n+# endif\n #endif\n #ifndef LUA_INTEGER_MIN\n # define LUA_INTEGER_MIN (-LUA_INTEGER_MAX -1)  /* -2^16|32 */\n-- \n1.9.1\n\n"
  },
  {
    "path": "package/utils/lua/patches-host/015-lnum-ppc-compat.patch",
    "content": "--- a/src/lua.h\n+++ b/src/lua.h\n@@ -79,7 +79,7 @@ typedef void * (*lua_Alloc) (void *ud, v\n  *     not acceptable for 5.1, maybe 5.2 onwards?\n  *  9: greater than existing (5.1) type values.\n */\n-#define LUA_TINT (-2)\n+#define LUA_TINT 9\n \n #define LUA_TNIL\t\t0\n #define LUA_TBOOLEAN\t\t1\n"
  },
  {
    "path": "package/utils/lua/patches-host/030-archindependent-bytecode.patch",
    "content": "--- a/src/ldump.c\n+++ b/src/ldump.c\n@@ -67,12 +67,12 @@ static void DumpString(const TString* s,\n {\n  if (s==NULL || getstr(s)==NULL)\n  {\n-  size_t size=0;\n+  unsigned int size=0;\n   DumpVar(size,D);\n  }\n  else\n  {\n-  size_t size=s->tsv.len+1;\t\t/* include trailing '\\0' */\n+  unsigned int size=s->tsv.len+1;\t\t/* include trailing '\\0' */\n   DumpVar(size,D);\n   DumpBlock(getstr(s),size,D);\n  }\n--- a/src/lundump.c\n+++ b/src/lundump.c\n@@ -25,6 +25,7 @@ typedef struct {\n  ZIO* Z;\n  Mbuffer* b;\n  const char* name;\n+ int swap;\n } LoadState;\n \n #ifdef LUAC_TRUST_BINARIES\n@@ -40,7 +41,6 @@ static void error(LoadState* S, const ch\n }\n #endif\n \n-#define LoadMem(S,b,n,size)\tLoadBlock(S,b,(n)*(size))\n #define\tLoadByte(S)\t\t(lu_byte)LoadChar(S)\n #define LoadVar(S,x)\t\tLoadMem(S,&x,1,sizeof(x))\n #define LoadVector(S,b,n,size)\tLoadMem(S,b,n,size)\n@@ -51,6 +51,49 @@ static void LoadBlock(LoadState* S, void\n  IF (r!=0, \"unexpected end\");\n }\n \n+static void LoadMem (LoadState* S, void* b, int n, size_t size)\n+{\n+ LoadBlock(S,b,n*size);\n+ if (S->swap)\n+ {\n+  char* p=(char*) b;\n+  char c;\n+  switch (size)\n+  {\n+   case 1:\n+  \tbreak;\n+   case 2:\n+\twhile (n--)\n+\t{\n+\t c=p[0]; p[0]=p[1]; p[1]=c;\n+\t p+=2;\n+\t}\n+  \tbreak;\n+   case 4:\n+\twhile (n--)\n+\t{\n+\t c=p[0]; p[0]=p[3]; p[3]=c;\n+\t c=p[1]; p[1]=p[2]; p[2]=c;\n+\t p+=4;\n+\t}\n+  \tbreak;\n+   case 8:\n+\twhile (n--)\n+\t{\n+\t c=p[0]; p[0]=p[7]; p[7]=c;\n+\t c=p[1]; p[1]=p[6]; p[6]=c;\n+\t c=p[2]; p[2]=p[5]; p[5]=c;\n+\t c=p[3]; p[3]=p[4]; p[4]=c;\n+\t p+=8;\n+\t}\n+  \tbreak;\n+   default:\n+   \tIF(1, \"bad size\");\n+  \tbreak;\n+  }\n+ }\n+}\n+\n static int LoadChar(LoadState* S)\n {\n  char x;\n@@ -82,7 +125,7 @@ static lua_Integer LoadInteger(LoadState\n \n static TString* LoadString(LoadState* S)\n {\n- size_t size;\n+ unsigned int size;\n  LoadVar(S,size);\n  if (size==0)\n   return NULL;\n@@ -196,6 +239,7 @@ static void LoadHeader(LoadState* S)\n  char s[LUAC_HEADERSIZE];\n  luaU_header(h);\n  LoadBlock(S,s,LUAC_HEADERSIZE);\n+ S->swap=(s[6]!=h[6]); s[6]=h[6];\n  IF (memcmp(h,s,LUAC_HEADERSIZE)!=0, \"bad header\");\n }\n \n@@ -230,7 +274,7 @@ void luaU_header (char* h)\n  *h++=(char)LUAC_FORMAT;\n  *h++=(char)*(char*)&x;\t\t\t\t/* endianness */\n  *h++=(char)sizeof(int);\n- *h++=(char)sizeof(size_t);\n+ *h++=(char)sizeof(unsigned int);\n  *h++=(char)sizeof(Instruction);\n  *h++=(char)sizeof(lua_Number);\n \n"
  },
  {
    "path": "package/utils/lua/patches-host/100-no_readline.patch",
    "content": "--- a/src/luaconf.h\n+++ b/src/luaconf.h\n@@ -38,7 +38,6 @@\n #if defined(LUA_USE_LINUX)\n #define LUA_USE_POSIX\n #define LUA_USE_DLOPEN\t\t/* needs an extra library: -ldl */\n-#define LUA_USE_READLINE\t/* needs some extra libraries */\n #endif\n \n #if defined(LUA_USE_MACOSX)\n--- a/src/Makefile\n+++ b/src/Makefile\n@@ -17,6 +17,7 @@\n MYCFLAGS=\n MYLDFLAGS=\n MYLIBS=\n+# USE_READLINE=1\n \n # == END OF USER SETTINGS. NO NEED TO CHANGE ANYTHING BELOW THIS LINE =========\n \n@@ -75,7 +76,7 @@\n \t@echo \"MYLIBS = $(MYLIBS)\"\n \n # convenience targets for popular platforms\n-\n+RFLAG=$(if $(USE_READLINE),-DLUA_USE_READLINE)\n none:\n \t@echo \"Please choose a platform:\"\n \t@echo \"   $(PLATS)\"\n@@ -90,16 +91,16 @@\n \t$(MAKE) all MYCFLAGS=\"-DLUA_USE_POSIX -DLUA_USE_DLOPEN\" MYLIBS=\"-Wl,-E\"\n \n freebsd:\n-\t$(MAKE) all MYCFLAGS=\"-DLUA_USE_LINUX\" MYLIBS=\"-Wl,-E -lreadline\"\n+\t$(MAKE) all MYCFLAGS=\"-DLUA_USE_LINUX\" $(RFLAG)\" MYLIBS=\"-Wl,-E$(if $(USE_READLINE), -lreadline)\"\n \n generic:\n \t$(MAKE) all MYCFLAGS=\n \n linux:\n-\t$(MAKE) all MYCFLAGS=-DLUA_USE_LINUX MYLIBS=\"-Wl,-E -ldl -lreadline -lhistory -lncurses\"\n+\t$(MAKE) all MYCFLAGS=\"-DLUA_USE_LINUX $(RFLAG)\" MYLIBS=\"-Wl,-E -ldl $(if $(USE_READLINE), -lreadline -lhistory -lncurses)\"\n \n macosx:\n-\t$(MAKE) all MYCFLAGS=-DLUA_USE_LINUX MYLIBS=\"-lreadline\"\n+\t$(MAKE) all MYCFLAGS=-DLUA_USE_LINUX $(if $(USE_READLINE), MYLIBS=\"-lreadline\")\n # use this on Mac OS X 10.3-\n #\t$(MAKE) all MYCFLAGS=-DLUA_USE_MACOSX\n \n"
  },
  {
    "path": "package/utils/lua5.3/Makefile",
    "content": "#\n# Copyright (C) 2006-2014 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=lua\nPKG_VERSION:=5.3.5\nPKG_RELEASE:=5\n\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz\nPKG_SOURCE_URL:=http://www.lua.org/ftp/ \\\n\thttp://www.tecgraf.puc-rio.br/lua/ftp/\nPKG_HASH:=0c2eed3f960446e1a3e4b9a1ca2f3ff893b6ce41942cf54d5dd59ab4b3b058ac\nPKG_BUILD_PARALLEL:=1\n\nPKG_LICENSE:=MIT\nPKG_LICENSE_FILES:=COPYRIGHT\n\nHOST_PATCH_DIR := ./patches-host\n\ninclude $(INCLUDE_DIR)/package.mk\ninclude $(INCLUDE_DIR)/host-build.mk\n\ndefine Package/lua5.3/Default\n  SUBMENU:=Lua\n  SECTION:=lang\n  CATEGORY:=Languages\n  TITLE:=Lua programming language\n  URL:=http://www.lua.org/\n  MAINTAINER:=Jo-Philipp Wich <jo@mein.io>\nendef\n\ndefine Package/lua5.3/Default/description\n  Lua is a powerful, efficient, lightweight, embeddable scripting language. It\n  supports procedural programming, object-oriented programming, functional\n  programming, data-driven programming, and data description.\nendef\n\ndefine Package/liblua5.3\n$(call Package/lua53/Default)\n  SUBMENU:=\n  SECTION:=libs\n  CATEGORY:=Libraries\n  TITLE+= (libraries)\n  ABI_VERSION:=5.3\nendef\n\ndefine Package/liblua5.3/description\n$(call Package/lua53/Default/description)\n This package contains the Lua shared libraries, needed by other programs.\nendef\n\ndefine Package/lua5.3\n$(call Package/lua5.3/Default)\n  DEPENDS:=+liblua5.3\n  TITLE+= (interpreter)\nendef\n\ndefine Package/lua5.3/description\n$(call Package/lua5.3/Default/description)\n  This package contains the Lua language interpreter.\nendef\n\ndefine Package/luac5.3\n$(call Package/lua5.3/Default)\n  DEPENDS:=+liblua5.3\n  TITLE+= (compiler)\nendef\n\ndefine Package/luac5.3/description\n$(call Package/lua5.3/Default/description)\n  This package contains the Lua language compiler.\nendef\n\nTARGET_CFLAGS += -DLUA_USE_LINUX $(FPIC) -std=gnu99\n\ndefine Build/Compile\n\t$(MAKE) $(PKG_JOBS) -C $(PKG_BUILD_DIR) \\\n\t\tCC=\"$(TARGET_CROSS)gcc\" \\\n\t\tAR=\"$(TARGET_CROSS)ar rcu\" \\\n\t\tRANLIB=\"$(TARGET_CROSS)ranlib\" \\\n\t\tINSTALL_ROOT=/usr \\\n\t\tCFLAGS=\"$(TARGET_CPPFLAGS) $(TARGET_CFLAGS)\" \\\n\t\tPKG_VERSION=$(PKG_VERSION) \\\n\t\tlinux\n\trm -rf $(PKG_INSTALL_DIR)\n\tmkdir -p $(PKG_INSTALL_DIR)\n\t$(MAKE) -C $(PKG_BUILD_DIR) \\\n\t\tINSTALL_TOP=\"$(PKG_INSTALL_DIR)/usr\" \\\n\t\tinstall\nendef\n\ndefine Host/Configure\n\t$(SED) 's,\"/usr/local/\",\"$(STAGING_DIR_HOSTPKG)/\",' $(HOST_BUILD_DIR)/src/luaconf.h\nendef\n\nifeq ($(HOST_OS),Darwin)\n\tLUA_OS:=macosx\nelse\n\tifeq ($(HOST_OS),FreeBSD)\n\t\tLUA_OS:=freebsd\n\telse\n\t\tLUA_OS:=linux\n\tendif\nendif\n\ndefine Host/Compile\n\t$(MAKE) -C $(HOST_BUILD_DIR) \\\n\t\tCC=\"$(HOSTCC) $(HOST_FPIC) -std=gnu99\" \\\n\t\t$(LUA_OS)\nendef\n\ndefine Host/Install\n\t$(MAKE) -C $(HOST_BUILD_DIR) \\\n\t\tINSTALL_TOP=\"$(STAGING_DIR_HOSTPKG)\" \\\n\t\tinstall\nendef\n\ndefine Build/InstallDev\n\t$(INSTALL_DIR) $(1)/usr/include/lua5.3 $(1)/usr/lib\n\t$(CP) $(PKG_INSTALL_DIR)/usr/include/lua5.3/lua{,lib,conf}.h $(1)/usr/include/lua5.3/\n\t$(CP) $(PKG_INSTALL_DIR)/usr/include/lua5.3/lua.hpp $(1)/usr/include/lua5.3/\n\t$(CP) $(PKG_INSTALL_DIR)/usr/include/lua5.3/lauxlib.h $(1)/usr/include/lua5.3/\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/liblua5.3.{a,so*} $(1)/usr/lib/\n\t$(LN) liblua5.3.so.0.0.0 $(1)/usr/lib/liblualib5.3.so\nendef\n\ndefine Package/liblua5.3/install\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/liblua5.3.so* $(1)/usr/lib/\nendef\n\ndefine Package/lua5.3/install\n\t$(INSTALL_DIR) $(1)/usr/bin\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/bin/lua5.3 $(1)/usr/bin/\nendef\n\ndefine Package/luac5.3/install\n\t$(INSTALL_DIR) $(1)/usr/bin\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/bin/luac5.3 $(1)/usr/bin/\nendef\n\n$(eval $(call BuildPackage,liblua5.3))\n$(eval $(call BuildPackage,lua5.3))\n$(eval $(call BuildPackage,luac5.3))\n$(eval $(call HostBuild))\n"
  },
  {
    "path": "package/utils/lua5.3/patches/001-include-version-number.patch",
    "content": "From 96576b44a1b368bd6590eb0778ae45cc9ccede3f Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Fri, 21 Jun 2019 14:08:38 +0200\nSubject: [PATCH] include version number\n\nIncluding it allows multiple lua versions to coexist.\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\n---\n\ndiff --git a/Makefile b/Makefile\n--- a/Makefile\n+++ b/Makefile\n@@ -12,7 +12,7 @@ PLAT= none\n # LUA_ROOT, LUA_LDIR, and LUA_CDIR in luaconf.h.\n INSTALL_TOP= /usr/local\n INSTALL_BIN= $(INSTALL_TOP)/bin\n-INSTALL_INC= $(INSTALL_TOP)/include\n+INSTALL_INC= $(INSTALL_TOP)/include/lua$V\n INSTALL_LIB= $(INSTALL_TOP)/lib\n INSTALL_MAN= $(INSTALL_TOP)/man/man1\n INSTALL_LMOD= $(INSTALL_TOP)/share/lua/$V\n@@ -39,10 +39,10 @@ RM= rm -f\n PLATS= aix bsd c89 freebsd generic linux macosx mingw posix solaris\n \n # What to install.\n-TO_BIN= lua luac\n+TO_BIN= lua$V luac$V\n TO_INC= lua.h luaconf.h lualib.h lauxlib.h lua.hpp\n-TO_LIB= liblua.a\n-TO_MAN= lua.1 luac.1\n+TO_LIB= liblua$V.a\n+TO_MAN= lua$V.1 luac$V.1\n \n # Lua version and release.\n V= 5.3\n@@ -52,7 +52,7 @@ R= $V.4\n all:\t$(PLAT)\n \n $(PLATS) clean:\n-\tcd src && $(MAKE) $@\n+\tcd src && $(MAKE) $@ V=$V\n \n test:\tdummy\n \tsrc/lua -v\ndiff --git a/doc/lua.1 b/doc/lua5.3.1\nrename from doc/lua.1\nrename to doc/lua5.3.1\ndiff --git a/doc/luac.1 b/doc/luac5.3.1\nrename from doc/luac.1\nrename to doc/luac5.3.1\ndiff --git a/src/Makefile b/src/Makefile\n--- a/src/Makefile\n+++ b/src/Makefile\n@@ -28,7 +28,7 @@ MYOBJS=\n \n PLATS= aix bsd c89 freebsd generic linux macosx mingw posix solaris\n \n-LUA_A=\tliblua.a\n+LUA_A=\tliblua$V.a\n CORE_O=\tlapi.o lcode.o lctype.o ldebug.o ldo.o ldump.o lfunc.o lgc.o llex.o \\\n \tlmem.o lobject.o lopcodes.o lparser.o lstate.o lstring.o ltable.o \\\n \tltm.o lundump.o lvm.o lzio.o\n@@ -36,10 +36,10 @@ LIB_O=\tlauxlib.o lbaselib.o lbitlib.o lc\n \tlmathlib.o loslib.o lstrlib.o ltablib.o lutf8lib.o loadlib.o linit.o\n BASE_O= $(CORE_O) $(LIB_O) $(MYOBJS)\n \n-LUA_T=\tlua\n+LUA_T=\tlua$V\n LUA_O=\tlua.o\n \n-LUAC_T=\tluac\n+LUAC_T=\tluac$V\n LUAC_O=\tluac.o\n \n ALL_O= $(BASE_O) $(LUA_O) $(LUAC_O)\n"
  },
  {
    "path": "package/utils/lua5.3/patches/020-shared_liblua.patch",
    "content": "--- a/Makefile\t2019-07-02 09:24:57.554332875 -0600\n+++ b/Makefile\t2019-07-02 09:25:42.626694604 -0600\n@@ -41,7 +41,7 @@ PLATS= aix bsd c89 freebsd generic linux\n # What to install.\n TO_BIN= lua$V luac$V\n TO_INC= lua.h luaconf.h lualib.h lauxlib.h lua.hpp\n-TO_LIB= liblua$V.a\n+TO_LIB= liblua$V.a liblua$V.so.0.0.0\n TO_MAN= lua$V.1 luac$V.1\n \n # Lua version and release.\n@@ -62,6 +62,9 @@ install: dummy\n \tcd src && $(INSTALL_EXEC) $(TO_BIN) $(INSTALL_BIN)\n \tcd src && $(INSTALL_DATA) $(TO_INC) $(INSTALL_INC)\n \tcd src && $(INSTALL_DATA) $(TO_LIB) $(INSTALL_LIB)\n+\tln -s liblua$V.so.0.0.0 $(INSTALL_LIB)/liblua$V.so.0.0\n+\tln -s liblua$V.so.0.0.0 $(INSTALL_LIB)/liblua$V.so.0\n+\tln -s liblua$V.so.0.0.0 $(INSTALL_LIB)/liblua$V.so\n \tcd doc && $(INSTALL_DATA) $(TO_MAN) $(INSTALL_MAN)\n \n uninstall:\n--- a/src/ldo.h\t2017-04-19 11:20:42.000000000 -0600\n+++ b/src/ldo.h\t2019-07-02 09:25:42.626694604 -0600\n@@ -47,8 +47,8 @@ LUAI_FUNC int luaD_pcall (lua_State *L,\n LUAI_FUNC int luaD_poscall (lua_State *L, CallInfo *ci, StkId firstResult,\n                                           int nres);\n LUAI_FUNC void luaD_reallocstack (lua_State *L, int newsize);\n-LUAI_FUNC void luaD_growstack (lua_State *L, int n);\n-LUAI_FUNC void luaD_shrinkstack (lua_State *L);\n+LUA_API void luaD_growstack (lua_State *L, int n);\n+LUA_API void luaD_shrinkstack (lua_State *L);\n LUAI_FUNC void luaD_inctop (lua_State *L);\n \n LUAI_FUNC l_noret luaD_throw (lua_State *L, int errcode);\n--- a/src/lfunc.h\t2017-04-19 11:39:34.000000000 -0600\n+++ b/src/lfunc.h\t2019-07-02 09:25:42.630694635 -0600\n@@ -47,14 +47,14 @@ struct UpVal {\n #define upisopen(up)\t((up)->v != &(up)->u.value)\n \n \n-LUAI_FUNC Proto *luaF_newproto (lua_State *L);\n+LUA_API Proto *luaF_newproto (lua_State *L);\n LUAI_FUNC CClosure *luaF_newCclosure (lua_State *L, int nelems);\n-LUAI_FUNC LClosure *luaF_newLclosure (lua_State *L, int nelems);\n-LUAI_FUNC void luaF_initupvals (lua_State *L, LClosure *cl);\n-LUAI_FUNC UpVal *luaF_findupval (lua_State *L, StkId level);\n-LUAI_FUNC void luaF_close (lua_State *L, StkId level);\n+LUA_API LClosure *luaF_newLclosure (lua_State *L, int nelems);\n+LUA_API void luaF_initupvals (lua_State *L, LClosure *cl);\n+LUA_API UpVal *luaF_findupval (lua_State *L, StkId level);\n+LUA_API void luaF_close (lua_State *L, StkId level);\n LUAI_FUNC void luaF_freeproto (lua_State *L, Proto *f);\n-LUAI_FUNC const char *luaF_getlocalname (const Proto *func, int local_number,\n+LUA_API const char *luaF_getlocalname (const Proto *func, int local_number,\n                                          int pc);\n \n \n--- a/src/lgc.h\t2017-04-19 11:39:34.000000000 -0600\n+++ b/src/lgc.h\t2019-07-02 09:25:42.634694666 -0600\n@@ -133,11 +133,11 @@\n \n LUAI_FUNC void luaC_fix (lua_State *L, GCObject *o);\n LUAI_FUNC void luaC_freeallobjects (lua_State *L);\n-LUAI_FUNC void luaC_step (lua_State *L);\n+LUA_API void luaC_step (lua_State *L);\n LUAI_FUNC void luaC_runtilstate (lua_State *L, int statesmask);\n LUAI_FUNC void luaC_fullgc (lua_State *L, int isemergency);\n LUAI_FUNC GCObject *luaC_newobj (lua_State *L, int tt, size_t sz);\n-LUAI_FUNC void luaC_barrier_ (lua_State *L, GCObject *o, GCObject *v);\n+LUA_API void luaC_barrier_ (lua_State *L, GCObject *o, GCObject *v);\n LUAI_FUNC void luaC_barrierback_ (lua_State *L, Table *o);\n LUAI_FUNC void luaC_upvalbarrier_ (lua_State *L, UpVal *uv);\n LUAI_FUNC void luaC_checkfinalizer (lua_State *L, GCObject *o, Table *mt);\n--- a/src/llex.h\t2017-04-19 11:20:42.000000000 -0600\n+++ b/src/llex.h\t2019-07-02 09:25:42.630694635 -0600\n@@ -73,13 +73,13 @@ typedef struct LexState {\n \n \n LUAI_FUNC void luaX_init (lua_State *L);\n-LUAI_FUNC void luaX_setinput (lua_State *L, LexState *ls, ZIO *z,\n+LUA_API void luaX_setinput (lua_State *L, LexState *ls, ZIO *z,\n                               TString *source, int firstchar);\n LUAI_FUNC TString *luaX_newstring (LexState *ls, const char *str, size_t l);\n-LUAI_FUNC void luaX_next (LexState *ls);\n-LUAI_FUNC int luaX_lookahead (LexState *ls);\n-LUAI_FUNC l_noret luaX_syntaxerror (LexState *ls, const char *s);\n-LUAI_FUNC const char *luaX_token2str (LexState *ls, int token);\n+LUA_API void luaX_next (LexState *ls);\n+LUA_API int luaX_lookahead (LexState *ls);\n+LUA_API l_noret luaX_syntaxerror (LexState *ls, const char *s);\n+LUA_API const char *luaX_token2str (LexState *ls, int token);\n \n \n #endif\n--- a/src/lmem.h\t2017-04-19 11:20:42.000000000 -0600\n+++ b/src/lmem.h\t2019-07-02 09:25:42.630694635 -0600\n@@ -56,12 +56,12 @@\n #define luaM_reallocvector(L, v,oldn,n,t) \\\n    ((v)=cast(t *, luaM_reallocv(L, v, oldn, n, sizeof(t))))\n \n-LUAI_FUNC l_noret luaM_toobig (lua_State *L);\n+LUA_API l_noret luaM_toobig (lua_State *L);\n \n /* not to be called directly */\n-LUAI_FUNC void *luaM_realloc_ (lua_State *L, void *block, size_t oldsize,\n+LUA_API void *luaM_realloc_ (lua_State *L, void *block, size_t oldsize,\n                                                           size_t size);\n-LUAI_FUNC void *luaM_growaux_ (lua_State *L, void *block, int *size,\n+LUA_API void *luaM_growaux_ (lua_State *L, void *block, int *size,\n                                size_t size_elem, int limit,\n                                const char *what);\n \n--- a/src/lobject.h\t2017-04-19 11:39:34.000000000 -0600\n+++ b/src/lobject.h\t2019-07-02 09:25:42.630694635 -0600\n@@ -525,7 +525,7 @@ typedef struct Table {\n #define luaO_nilobject\t\t(&luaO_nilobject_)\n \n \n-LUAI_DDEC const TValue luaO_nilobject_;\n+LUA_API const TValue luaO_nilobject_;\n \n /* size of buffer for 'luaO_utf8esc' function */\n #define UTF8BUFFSZ\t8\n@@ -534,15 +534,15 @@ LUAI_FUNC int luaO_int2fb (unsigned int\n LUAI_FUNC int luaO_fb2int (int x);\n LUAI_FUNC int luaO_utf8esc (char *buff, unsigned long x);\n LUAI_FUNC int luaO_ceillog2 (unsigned int x);\n-LUAI_FUNC void luaO_arith (lua_State *L, int op, const TValue *p1,\n+LUA_API void luaO_arith (lua_State *L, int op, const TValue *p1,\n                            const TValue *p2, TValue *res);\n LUAI_FUNC size_t luaO_str2num (const char *s, TValue *o);\n LUAI_FUNC int luaO_hexavalue (int c);\n LUAI_FUNC void luaO_tostring (lua_State *L, StkId obj);\n-LUAI_FUNC const char *luaO_pushvfstring (lua_State *L, const char *fmt,\n+LUA_API const char *luaO_pushvfstring (lua_State *L, const char *fmt,\n                                                        va_list argp);\n-LUAI_FUNC const char *luaO_pushfstring (lua_State *L, const char *fmt, ...);\n-LUAI_FUNC void luaO_chunkid (char *out, const char *source, size_t len);\n+LUA_API const char *luaO_pushfstring (lua_State *L, const char *fmt, ...);\n+LUA_API void luaO_chunkid (char *out, const char *source, size_t len);\n \n \n #endif\n--- a/src/lopcodes.h\t2017-04-19 11:20:42.000000000 -0600\n+++ b/src/lopcodes.h\t2019-07-02 09:25:42.630694635 -0600\n@@ -278,7 +278,7 @@ enum OpArgMask {\n   OpArgK   /* argument is a constant or register/constant */\n };\n \n-LUAI_DDEC const lu_byte luaP_opmodes[NUM_OPCODES];\n+LUA_API const lu_byte luaP_opmodes[NUM_OPCODES];\n \n #define getOpMode(m)\t(cast(enum OpMode, luaP_opmodes[m] & 3))\n #define getBMode(m)\t(cast(enum OpArgMask, (luaP_opmodes[m] >> 4) & 3))\n@@ -287,7 +287,7 @@ LUAI_DDEC const lu_byte luaP_opmodes[NUM\n #define testTMode(m)\t(luaP_opmodes[m] & (1 << 7))\n \n \n-LUAI_DDEC const char *const luaP_opnames[NUM_OPCODES+1];  /* opcode names */\n+LUA_API const char *const luaP_opnames[NUM_OPCODES+1];  /* opcode names */\n \n \n /* number of list items to accumulate before a SETLIST instruction */\n--- a/src/lstate.h\t2017-04-19 11:39:34.000000000 -0600\n+++ b/src/lstate.h\t2019-07-02 09:25:42.630694635 -0600\n@@ -244,9 +244,9 @@ union GCUnion {\n \n LUAI_FUNC void luaE_setdebt (global_State *g, l_mem debt);\n LUAI_FUNC void luaE_freethread (lua_State *L, lua_State *L1);\n-LUAI_FUNC CallInfo *luaE_extendCI (lua_State *L);\n-LUAI_FUNC void luaE_freeCI (lua_State *L);\n-LUAI_FUNC void luaE_shrinkCI (lua_State *L);\n+LUA_API CallInfo *luaE_extendCI (lua_State *L);\n+LUA_API void luaE_freeCI (lua_State *L);\n+LUA_API void luaE_shrinkCI (lua_State *L);\n \n \n #endif\n--- a/src/lstring.h\t2017-04-19 11:20:42.000000000 -0600\n+++ b/src/lstring.h\t2019-07-02 09:25:42.630694635 -0600\n@@ -35,15 +35,15 @@\n \n LUAI_FUNC unsigned int luaS_hash (const char *str, size_t l, unsigned int seed);\n LUAI_FUNC unsigned int luaS_hashlongstr (TString *ts);\n-LUAI_FUNC int luaS_eqlngstr (TString *a, TString *b);\n+LUA_API int luaS_eqlngstr (TString *a, TString *b);\n LUAI_FUNC void luaS_resize (lua_State *L, int newsize);\n LUAI_FUNC void luaS_clearcache (global_State *g);\n LUAI_FUNC void luaS_init (lua_State *L);\n LUAI_FUNC void luaS_remove (lua_State *L, TString *ts);\n LUAI_FUNC Udata *luaS_newudata (lua_State *L, size_t s);\n-LUAI_FUNC TString *luaS_newlstr (lua_State *L, const char *str, size_t l);\n-LUAI_FUNC TString *luaS_new (lua_State *L, const char *str);\n-LUAI_FUNC TString *luaS_createlngstrobj (lua_State *L, size_t l);\n+LUA_API TString *luaS_newlstr (lua_State *L, const char *str, size_t l);\n+LUA_API TString *luaS_new (lua_State *L, const char *str);\n+LUA_API TString *luaS_createlngstrobj (lua_State *L, size_t l);\n \n \n #endif\n--- a/src/ltable.h\t2018-05-24 13:39:05.000000000 -0600\n+++ b/src/ltable.h\t2019-07-02 09:25:42.630694635 -0600\n@@ -41,14 +41,14 @@\n \n \n LUAI_FUNC const TValue *luaH_getint (Table *t, lua_Integer key);\n-LUAI_FUNC void luaH_setint (lua_State *L, Table *t, lua_Integer key,\n+LUA_API void luaH_setint (lua_State *L, Table *t, lua_Integer key,\n                                                     TValue *value);\n LUAI_FUNC const TValue *luaH_getshortstr (Table *t, TString *key);\n LUAI_FUNC const TValue *luaH_getstr (Table *t, TString *key);\n LUAI_FUNC const TValue *luaH_get (Table *t, const TValue *key);\n LUAI_FUNC TValue *luaH_newkey (lua_State *L, Table *t, const TValue *key);\n-LUAI_FUNC TValue *luaH_set (lua_State *L, Table *t, const TValue *key);\n-LUAI_FUNC Table *luaH_new (lua_State *L);\n+LUA_API TValue *luaH_set (lua_State *L, Table *t, const TValue *key);\n+LUA_API Table *luaH_new (lua_State *L);\n LUAI_FUNC void luaH_resize (lua_State *L, Table *t, unsigned int nasize,\n                                                     unsigned int nhsize);\n LUAI_FUNC void luaH_resizearray (lua_State *L, Table *t, unsigned int nasize);\n--- a/src/ltm.h\t2017-04-19 11:20:42.000000000 -0600\n+++ b/src/ltm.h\t2019-07-02 09:25:42.634694666 -0600\n@@ -55,10 +55,10 @@ typedef enum {\n LUAI_DDEC const char *const luaT_typenames_[LUA_TOTALTAGS];\n \n \n-LUAI_FUNC const char *luaT_objtypename (lua_State *L, const TValue *o);\n+LUA_API const char *luaT_objtypename (lua_State *L, const TValue *o);\n \n LUAI_FUNC const TValue *luaT_gettm (Table *events, TMS event, TString *ename);\n-LUAI_FUNC const TValue *luaT_gettmbyobj (lua_State *L, const TValue *o,\n+LUA_API const TValue *luaT_gettmbyobj (lua_State *L, const TValue *o,\n                                                        TMS event);\n LUAI_FUNC void luaT_init (lua_State *L);\n \n@@ -66,9 +66,9 @@ LUAI_FUNC void luaT_callTM (lua_State *L\n                             const TValue *p2, TValue *p3, int hasres);\n LUAI_FUNC int luaT_callbinTM (lua_State *L, const TValue *p1, const TValue *p2,\n                               StkId res, TMS event);\n-LUAI_FUNC void luaT_trybinTM (lua_State *L, const TValue *p1, const TValue *p2,\n+LUA_API void luaT_trybinTM (lua_State *L, const TValue *p1, const TValue *p2,\n                               StkId res, TMS event);\n-LUAI_FUNC int luaT_callorderTM (lua_State *L, const TValue *p1,\n+LUA_API int luaT_callorderTM (lua_State *L, const TValue *p1,\n                                 const TValue *p2, TMS event);\n \n \n--- a/src/lundump.h\t2017-04-19 11:20:42.000000000 -0600\n+++ b/src/lundump.h\t2019-07-02 09:25:42.634694666 -0600\n@@ -23,10 +23,10 @@\n #define LUAC_FORMAT\t0\t/* this is the official format */\n \n /* load one chunk; from lundump.c */\n-LUAI_FUNC LClosure* luaU_undump (lua_State* L, ZIO* Z, const char* name);\n+LUA_API LClosure* luaU_undump (lua_State* L, ZIO* Z, const char* name);\n \n /* dump one chunk; from ldump.c */\n-LUAI_FUNC int luaU_dump (lua_State* L, const Proto* f, lua_Writer w,\n+LUA_API int luaU_dump (lua_State* L, const Proto* f, lua_Writer w,\n                          void* data, int strip);\n \n #endif\n--- a/src/lzio.h\t2017-04-19 11:20:42.000000000 -0600\n+++ b/src/lzio.h\t2019-07-02 09:25:42.634694666 -0600\n@@ -61,6 +61,6 @@ struct Zio {\n };\n \n \n-LUAI_FUNC int luaZ_fill (ZIO *z);\n+LUA_API int luaZ_fill (ZIO *z);\n \n #endif\n--- a/src/Makefile\t2019-07-02 09:24:57.554332875 -0600\n+++ b/src/Makefile\t2019-07-02 09:25:42.630694635 -0600\n@@ -29,6 +29,7 @@ MYOBJS=\n PLATS= aix bsd c89 freebsd generic linux macosx mingw posix solaris\n \n LUA_A=\tliblua$V.a\n+LUA_SO=\tliblua$V.so.0.0.0\n CORE_O=\tlapi.o lcode.o lctype.o ldebug.o ldo.o ldump.o lfunc.o lgc.o llex.o \\\n \tlmem.o lobject.o lopcodes.o lparser.o lstate.o lstring.o ltable.o \\\n \tltm.o lundump.o lvm.o lzio.o\n@@ -43,8 +44,9 @@ LUAC_T=\tluac$V\n LUAC_O=\tluac.o\n \n ALL_O= $(BASE_O) $(LUA_O) $(LUAC_O)\n-ALL_T= $(LUA_A) $(LUA_T) $(LUAC_T)\n+ALL_T= $(LUA_A) $(LUA_SO) $(LUA_T) $(LUAC_T)\n ALL_A= $(LUA_A)\n+ALL_SO= $(LUA_SO)\n \n # Targets start here.\n default: $(PLAT)\n@@ -55,14 +57,25 @@ o:\t$(ALL_O)\n \n a:\t$(ALL_A)\n \n+so:\t$(ALL_SO)\n+\n $(LUA_A): $(BASE_O)\n \t$(AR) $@ $(BASE_O)\n \t$(RANLIB) $@\n \n-$(LUA_T): $(LUA_O) $(LUA_A)\n-\t$(CC) -o $@ $(LDFLAGS) $(LUA_O) $(LUA_A) $(LIBS)\n+$(LUA_SO): $(CORE_O) $(LIB_O)\n+\t$(CC) -o $@ -Wl,-Bsymbolic-functions -shared -Wl,-soname=\"$@\" $?\n+\tln -fs $@ liblua$V.so.0.0\n+\tln -fs $@ liblua$V.so.0\n+\tln -fs $@ liblua$V.so\n+\n+$(LUA_T): $(LUA_O) $(LUA_SO)\n+\t$(CC) -o $@ -L. -llua$V $(MYLDFLAGS) $(LUA_O) $(LIBS)\n+\n+$(LUAC_T): $(LUAC_O) $(LUA_SO)\n+\t$(CC) -o $@ -L. -llua$V $(MYLDFLAGS) $(LUAC_O) $(LIBS)\n \n-$(LUAC_T): $(LUAC_O) $(LUA_A)\n+$(LUAC_T)-host: $(LUAC_O) $(LUA_A)\n \t$(CC) -o $@ $(LDFLAGS) $(LUAC_O) $(LUA_A) $(LIBS)\n \n clean:\n"
  },
  {
    "path": "package/utils/lua5.3/patches/100-no_readline.patch",
    "content": "--- a/src/luaconf.h\n+++ b/src/luaconf.h\n@@ -61,14 +61,12 @@\n #if defined(LUA_USE_LINUX)\n #define LUA_USE_POSIX\n #define LUA_USE_DLOPEN\t\t/* needs an extra library: -ldl */\n-#define LUA_USE_READLINE\t/* needs some extra libraries */\n #endif\n \n \n #if defined(LUA_USE_MACOSX)\n #define LUA_USE_POSIX\n #define LUA_USE_DLOPEN\t\t/* MacOS does not need -ldl */\n-#define LUA_USE_READLINE\t/* needs an extra library: -lreadline */\n #endif\n \n \n--- a/src/Makefile\n+++ b/src/Makefile\n@@ -23,6 +23,7 @@ MYCFLAGS=\n MYLDFLAGS=\n MYLIBS=\n MYOBJS=\n+# USE_READLINE=1\n \n # == END OF USER SETTINGS -- NO NEED TO CHANGE ANYTHING BELOW THIS LINE =======\n \n@@ -96,6 +97,7 @@ echo:\n \n # Convenience targets for popular platforms\n ALL= all\n+RFLAG=$(if $(USE_READLINE),-DLUA_USE_READLINE)\n \n none:\n \t@echo \"Please do 'make PLATFORM' where PLATFORM is one of these:\"\n@@ -115,15 +117,15 @@ c89:\n \n \n freebsd:\n-\t$(MAKE) $(ALL) SYSCFLAGS=\"-DLUA_USE_LINUX -DLUA_USE_READLINE -I/usr/include/edit\" SYSLIBS=\"-Wl,-E -ledit\" CC=\"cc\"\n+\t$(MAKE) $(ALL) SYSCFLAGS=\"-DLUA_USE_LINUX $(RFLAG) -I/usr/include/edit\" SYSLIBS=\"-Wl,-E -ledit\" CC=\"cc\"\n \n generic: $(ALL)\n \n linux:\n-\t$(MAKE) $(ALL) SYSCFLAGS=\"-DLUA_USE_LINUX\" SYSLIBS=\"-Wl,-E -ldl -lreadline\"\n+\t$(MAKE) $(ALL) SYSCFLAGS=\"-DLUA_USE_LINUX\" $(RFLAG) SYSLIBS=\"-Wl,-E -ldl $(if $(USE_READLINE), -lreadline)\"\n \n macosx:\n-\t$(MAKE) $(ALL) SYSCFLAGS=\"-DLUA_USE_MACOSX\" SYSLIBS=\"-lreadline\"\n+\t$(MAKE) $(ALL) SYSCFLAGS=\"-DLUA_USE_MACOSX\" $(RFLAG) SYSLIBS=\"$(if $(USE_READLINE), -lreadline)\"\n \n mingw:\n \t$(MAKE) \"LUA_A=lua53.dll\" \"LUA_T=lua.exe\" \\\n"
  },
  {
    "path": "package/utils/lua5.3/patches-host/001-include-version-number.patch",
    "content": "From 96576b44a1b368bd6590eb0778ae45cc9ccede3f Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Fri, 21 Jun 2019 14:08:38 +0200\nSubject: [PATCH] include version number\n\nIncluding it allows multiple lua versions to coexist.\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\n---\n\ndiff --git a/Makefile b/Makefile\n--- a/Makefile\n+++ b/Makefile\n@@ -12,7 +12,7 @@ PLAT= none\n # LUA_ROOT, LUA_LDIR, and LUA_CDIR in luaconf.h.\n INSTALL_TOP= /usr/local\n INSTALL_BIN= $(INSTALL_TOP)/bin\n-INSTALL_INC= $(INSTALL_TOP)/include\n+INSTALL_INC= $(INSTALL_TOP)/include/lua$V\n INSTALL_LIB= $(INSTALL_TOP)/lib\n INSTALL_MAN= $(INSTALL_TOP)/man/man1\n INSTALL_LMOD= $(INSTALL_TOP)/share/lua/$V\n@@ -39,10 +39,10 @@ RM= rm -f\n PLATS= aix bsd c89 freebsd generic linux macosx mingw posix solaris\n \n # What to install.\n-TO_BIN= lua luac\n+TO_BIN= lua$V luac$V\n TO_INC= lua.h luaconf.h lualib.h lauxlib.h lua.hpp\n-TO_LIB= liblua.a\n-TO_MAN= lua.1 luac.1\n+TO_LIB= liblua$V.a\n+TO_MAN= lua$V.1 luac$V.1\n \n # Lua version and release.\n V= 5.3\n@@ -52,7 +52,7 @@ R= $V.4\n all:\t$(PLAT)\n \n $(PLATS) clean:\n-\tcd src && $(MAKE) $@\n+\tcd src && $(MAKE) $@ V=$V\n \n test:\tdummy\n \tsrc/lua -v\ndiff --git a/doc/lua.1 b/doc/lua5.3.1\nrename from doc/lua.1\nrename to doc/lua5.3.1\ndiff --git a/doc/luac.1 b/doc/luac5.3.1\nrename from doc/luac.1\nrename to doc/luac5.3.1\ndiff --git a/src/Makefile b/src/Makefile\n--- a/src/Makefile\n+++ b/src/Makefile\n@@ -28,7 +28,7 @@ MYOBJS=\n \n PLATS= aix bsd c89 freebsd generic linux macosx mingw posix solaris\n \n-LUA_A=\tliblua.a\n+LUA_A=\tliblua$V.a\n CORE_O=\tlapi.o lcode.o lctype.o ldebug.o ldo.o ldump.o lfunc.o lgc.o llex.o \\\n \tlmem.o lobject.o lopcodes.o lparser.o lstate.o lstring.o ltable.o \\\n \tltm.o lundump.o lvm.o lzio.o\n@@ -36,10 +36,10 @@ LIB_O=\tlauxlib.o lbaselib.o lbitlib.o lc\n \tlmathlib.o loslib.o lstrlib.o ltablib.o lutf8lib.o loadlib.o linit.o\n BASE_O= $(CORE_O) $(LIB_O) $(MYOBJS)\n \n-LUA_T=\tlua\n+LUA_T=\tlua$V\n LUA_O=\tlua.o\n \n-LUAC_T=\tluac\n+LUAC_T=\tluac$V\n LUAC_O=\tluac.o\n \n ALL_O= $(BASE_O) $(LUA_O) $(LUAC_O)\n"
  },
  {
    "path": "package/utils/lua5.3/patches-host/100-no_readline.patch",
    "content": "--- a/src/luaconf.h\n+++ b/src/luaconf.h\n@@ -61,14 +61,12 @@\n #if defined(LUA_USE_LINUX)\n #define LUA_USE_POSIX\n #define LUA_USE_DLOPEN\t\t/* needs an extra library: -ldl */\n-#define LUA_USE_READLINE\t/* needs some extra libraries */\n #endif\n \n \n #if defined(LUA_USE_MACOSX)\n #define LUA_USE_POSIX\n #define LUA_USE_DLOPEN\t\t/* MacOS does not need -ldl */\n-#define LUA_USE_READLINE\t/* needs an extra library: -lreadline */\n #endif\n \n \n--- a/src/Makefile\n+++ b/src/Makefile\n@@ -23,6 +23,7 @@ MYCFLAGS=\n MYLDFLAGS=\n MYLIBS=\n MYOBJS=\n+# USE_READLINE=1\n \n # == END OF USER SETTINGS -- NO NEED TO CHANGE ANYTHING BELOW THIS LINE =======\n \n@@ -83,6 +84,7 @@ echo:\n \n # Convenience targets for popular platforms\n ALL= all\n+RFLAG=$(if $(USE_READLINE),-DLUA_USE_READLINE)\n \n none:\n \t@echo \"Please do 'make PLATFORM' where PLATFORM is one of these:\"\n@@ -102,15 +104,15 @@ c89:\n \n \n freebsd:\n-\t$(MAKE) $(ALL) SYSCFLAGS=\"-DLUA_USE_LINUX -DLUA_USE_READLINE -I/usr/include/edit\" SYSLIBS=\"-Wl,-E -ledit\" CC=\"cc\"\n+\t$(MAKE) $(ALL) SYSCFLAGS=\"-DLUA_USE_LINUX $(RFLAG) -I/usr/include/edit\" SYSLIBS=\"-Wl,-E -ledit\" CC=\"cc\"\n \n generic: $(ALL)\n \n linux:\n-\t$(MAKE) $(ALL) SYSCFLAGS=\"-DLUA_USE_LINUX\" SYSLIBS=\"-Wl,-E -ldl -lreadline\"\n+\t$(MAKE) $(ALL) SYSCFLAGS=\"-DLUA_USE_LINUX\" $(RFLAG) SYSLIBS=\"-Wl,-E -ldl $(if $(USE_READLINE), -lreadline)\"\n \n macosx:\n-\t$(MAKE) $(ALL) SYSCFLAGS=\"-DLUA_USE_MACOSX\" SYSLIBS=\"-lreadline\"\n+\t$(MAKE) $(ALL) SYSCFLAGS=\"-DLUA_USE_MACOSX\" $(RFLAG) SYSLIBS=\"$(if $(USE_READLINE), -lreadline)\"\n \n mingw:\n \t$(MAKE) \"LUA_A=lua53.dll\" \"LUA_T=lua.exe\" \\\n"
  },
  {
    "path": "package/utils/mdadm/Makefile",
    "content": "#\n# Copyright (C) 2008-2012 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=mdadm\nPKG_VERSION:=4.2\nPKG_RELEASE:=1\n\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz\nPKG_SOURCE_URL:=@KERNEL/linux/utils/raid/mdadm\nPKG_HASH:=461c215670864bb74a4d1a3620684aa2b2f8296dffa06743f26dda5557acf01d\n\nPKG_MAINTAINER:=Felix Fietkau <nbd@nbd.name>\nPKG_CPE_ID:=cpe:/a:mdadm_project:mdadm\n\nPKG_BUILD_PARALLEL:=1\n\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine Package/mdadm\n  SECTION:=utils\n  CATEGORY:=Utilities\n  SUBMENU:=Disc\n  TITLE:=A tool for managing Soft RAID under Linux\n  URL:=https://www.kernel.org/pub/linux/utils/raid/mdadm/\n  DEPENDS:=+libpthread +kmod-md-mod +kmod-md-raid0 +kmod-md-raid10 +kmod-md-raid1\nendef\n\ndefine Package/mdadm/description\n A tool for managing Linux Software RAID arrays.\n RAID 0, 1 and 10 support included.\n If you need RAID 4,5 or 6 functionality please\n install kmod-md-raid456 .\nendef\n\ndefine Package/mdadm/conffiles\n/etc/config/mdadm\nendef\n\nTARGET_CFLAGS += \\\n\t-ffunction-sections -fdata-sections \\\n\t-DHAVE_STDINT_H -DNO_COROSYNC -DNO_DLM -DUSE_PTHREADS \\\n\t-DCONFFILE='\\\"/var/etc/mdadm.conf\\\"' \\\n\t-DMAP_DIR='\\\"/var/run/mdadm\\\"' \\\n\t-DMDMON_DIR='\\\"/var/run/mdadm\\\"' \\\n\t-DFAILED_SLOTS_DIR='\\\"/var/run/mdadm/failed-slots\\\"' \\\n\t-DNO_LIBUDEV\n\nTARGET_CXFLAGS = -DNO_LIBUDEV\n\nTARGET_LDFLAGS += -Wl,--gc-sections\n\nMAKE_FLAGS += \\\n\t\tCHECK_RUN_DIR=0 \\\n\t\tCXFLAGS=\"$(TARGET_CXFLAGS)\"\n\ndefine Build/Compile\n\t$(call Build/Compile/Default,mdadm)\nendef\n\ndefine Package/mdadm/install\n\t$(INSTALL_DIR) $(1)/sbin\n\t$(INSTALL_BIN) $(PKG_BUILD_DIR)/mdadm $(1)/sbin\n\t$(INSTALL_DIR) $(1)/etc/init.d\n\t$(INSTALL_BIN) ./files/mdadm.init $(1)/etc/init.d/mdadm\n\t$(INSTALL_DIR) $(1)/etc/config\n\t$(INSTALL_CONF) ./files/mdadm.config $(1)/etc/config/mdadm\nendef\n\n$(eval $(call BuildPackage,mdadm))\n"
  },
  {
    "path": "package/utils/mdadm/files/mdadm.config",
    "content": "config mdadm\n\toption email root\n\t# list devices /dev/hd*\n\t# list devices /dev/sd*\n\t# list devices partitions\n\nconfig array\n\toption uuid 52c5c44a:d2162820:f75d3464:799750f8\n\toption device /dev/md0\n\t# option name raid:0\n\t# option super_minor 0\n\t# list devices /dev/sda1\n\t# list devices /dev/sdb1\n\t# option spares 0\n\t# option spare_group spares\n\t# option bitmap /bitmap.md\n\t# option container 00000000:00000000:00000000:00000000\n\t# option member 1\n"
  },
  {
    "path": "package/utils/mdadm/files/mdadm.init",
    "content": "#!/bin/sh /etc/rc.common\n\nSTART=13\nSTOP=98\n\nUSE_PROCD=1\nPROG=/sbin/mdadm\nNAME=mdadm\n\nCONF=\"/var/etc/mdadm.conf\"\n\nappend_list_item() {\n\tappend \"$2\" \"$1\" \"$3\"\n}\n\nappend_option() {\n\tlocal var=\"$1\"\n\tlocal cfg=\"$2\"\n\tlocal opt=\"$3\"\n\tlocal name=\"$4\"\n\tlocal sep=\"$5\"\n\tlocal str\n\n\tif [ -n \"$sep\" ]; then\n\t\tconfig_list_foreach \"$cfg\" \"$opt\" append_list_item str \"$sep\"\n\telse\n\t\tconfig_get str \"$cfg\" \"$opt\"\n\tfi\n\n\t[ -n \"$str\" ] && append \"$var\" $(printf \"%s=%s\" \"${name:-${opt//_/-}}\" \"$str\")\n}\n\nmdadm_common() {\n\tlocal cfg=\"$1\"\n\tlocal email devices\n\n\tif [ -x /usr/sbin/sendmail ]; then\n\t\tconfig_get email \"$cfg\" email\n\t\t[ -n \"$email\" ] && printf \"MAILADDR %s\\n\" \"$email\" >> $CONF\n\tfi\n\n\tconfig_list_foreach \"$cfg\" devices append_list_item devices \" \"\n\t[ -n \"$devices\" ] && printf \"DEVICE %s\\n\" \"$devices\" >> $CONF\n}\n\nmdadm_array() {\n\tlocal cfg=\"$1\"\n\tlocal uuid device devices name array\n\n\tconfig_get uuid \"$cfg\" uuid\n\tconfig_get name \"$cfg\" name\n\tconfig_get device \"$cfg\" device\n\n\tif [ -z \"$device\" ] || [ -z \"$uuid$name\" ]; then\n\t\techo \"Skipping array without device, uuid or name\" >&2\n\t\treturn\n\tfi\n\n\t[ -n \"$uuid\" ] && append array \"uuid=$uuid\"\n\t[ -n \"$name\" ] && append array \"name=$name\"\n\n\tappend_option array \"$cfg\" super_minor\n\tappend_option array \"$cfg\" spares\n\tappend_option array \"$cfg\" spare_group\n\tappend_option array \"$cfg\" bitmap\n\tappend_option array \"$cfg\" container\n\tappend_option array \"$cfg\" member\n\tappend_option array \"$cfg\" devices devices \",\"\n\n\tprintf \"ARRAY %s %s\\n\" \"$device\" \"$array\" >> $CONF\n}\n\nstart_service() {\n\tlocal email\n\n\tmkdir -p \"${CONF%/*}\"\n\tprintf \"# Autogenerated from /etc/config/mdadm, do not edit!\\n\" > $CONF\n\n\tconfig_load mdadm\n\tconfig_foreach mdadm_common mdadm\n\tconfig_foreach mdadm_array array\n\n\t$PROG --assemble --scan --config=\"$CONF\"\n\n\tprocd_open_instance\n\tprocd_set_param command \"$PROG\" --monitor --syslog --scan --config=\"$CONF\"\n\tprocd_close_instance\n}\n\nstop_service() {\n\t$PROG --stop --scan\n}\n\n"
  },
  {
    "path": "package/utils/mdadm/patches/100-cross_compile.patch",
    "content": "--- a/Makefile\n+++ b/Makefile\n@@ -99,7 +99,7 @@ DLM:=$(shell [ -f /usr/include/libdlm.h\n DIRFLAGS = -DMAP_DIR=\\\"$(MAP_DIR)\\\" -DMAP_FILE=\\\"$(MAP_FILE)\\\"\n DIRFLAGS += -DMDMON_DIR=\\\"$(MDMON_DIR)\\\"\n DIRFLAGS += -DFAILED_SLOTS_DIR=\\\"$(FAILED_SLOTS_DIR)\\\"\n-CFLAGS = $(CWFLAGS) $(CXFLAGS) -DSendmail=\\\"\"$(MAILCMD)\"\\\" $(CONFFILEFLAGS) $(DIRFLAGS) $(COROSYNC) $(DLM)\n+#CFLAGS = $(CWFLAGS) $(CXFLAGS) -DSendmail=\\\"\"$(MAILCMD)\"\\\" $(CONFFILEFLAGS) $(DIRFLAGS) $(COROSYNC) $(DLM)\n \n VERSION = $(shell [ -d .git ] && git describe HEAD | sed 's/mdadm-//')\n VERS_DATE = $(shell [ -d .git ] && date --iso-8601 --date=\"`git log -n1 --format=format:%cd --date=iso --date=short`\")\n"
  },
  {
    "path": "package/utils/mdadm/patches/200-reduce_size.patch",
    "content": "--- a/Incremental.c\n+++ b/Incremental.c\n@@ -983,6 +983,10 @@ static int array_try_spare(char *devname\n \t\t\t\tgoto next;\n \t\t}\n \n+\t\t#ifndef MDADM_FULL\n+\t\t\treturn 0;\n+\t\t#endif\n+\n \t\tdl = domain_from_array(sra, st2->ss->name);\n \t\tif (domain_test(dl, pol, st2->ss->name) != 1) {\n \t\t\t/* domain test fails */\n--- a/util.c\n+++ b/util.c\n@@ -1147,7 +1147,9 @@ void wait_for(char *dev, int fd)\n struct superswitch *superlist[] =\n {\n \t&super0, &super1,\n+#ifdef MDADM_FULL\n \t&super_ddf, &super_imsm,\n+#endif\n \t&mbr, &gpt,\n \tNULL\n };\n"
  },
  {
    "path": "package/utils/mtd-utils/Makefile",
    "content": "#\n# Copyright (C) 2009-2014 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=mtd-utils\nPKG_VERSION:=2.1.4\nPKG_RELEASE:=1\n\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.bz2\nPKG_SOURCE_URL:=https://infraroot.at/pub/mtd/\nPKG_HASH:=2c6711d15d282c47cb3867b6857340597e26d332c238465134c602e5eef71b99\n\nPKG_INSTALL:=1\nPKG_FIXUP:=autoreconf\n\nPKG_FLAGS:=nonshared\n\nPKG_BUILD_DEPENDS:=util-linux\n\nPKG_LICENSE:=GPLv2\nPKG_LICENSE_FILES:=\n\nPKG_MAINTAINER:=John Crispin <john@phrozen.org>\n\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine Package/mtd-utils/Default\n  SECTION:=utils\n  CATEGORY:=Utilities\n  URL:=http://www.linux-mtd.infradead.org/\n  DEPENDS:=@NAND_SUPPORT\nendef\n\ndefine Package/ubi-utils\n $(call Package/mtd-utils/Default)\n  TITLE:=Utilities for ubi info/debug\nendef\n\ndefine Package/ubi-utils/description\n  Utilities for manipulating memory technology devices.\nendef\n\ndefine Package/nand-utils\n $(call Package/mtd-utils/Default)\n  TITLE:=Utilities for nand flash erase/read/write/test\nendef\n\ndefine Package/nand-utils/description\n  Utilities for NAND devices.\nendef\n\nMAKE_FLAGS += LDLIBS+=\"$(LIBGCC_S)\"\n\nCONFIGURE_ARGS += \\\n\t--disable-tests \\\n\t--without-crypto \\\n\t--without-xattr \\\n\t--without-zstd \\\n\t--without-lzo\n\nTARGET_CFLAGS += -ffunction-sections -fdata-sections\nTARGET_LDFLAGS += -Wl,--gc-sections\n\ndefine Package/ubi-utils/install\n\t$(INSTALL_DIR) $(1)/usr/sbin\n\t$(INSTALL_BIN) \\\n\t\t$(PKG_INSTALL_DIR)/usr/sbin/{ubiattach,ubicrc32,ubiblock,ubidetach,ubiformat,ubimkvol} $(1)/usr/sbin/\n\t$(INSTALL_BIN) \\\n\t\t$(PKG_INSTALL_DIR)/usr/sbin/{ubinfo,ubinize,ubirename,ubirmvol,ubirsvol,ubiupdatevol} $(1)/usr/sbin/\nendef\n\ndefine Package/nand-utils/install\n\t$(INSTALL_DIR) $(1)/usr/sbin\n\t$(INSTALL_BIN) \\\n\t$(PKG_INSTALL_DIR)/usr/sbin/{flash_erase,nanddump,nandwrite,nandtest,mtdinfo} $(1)/usr/sbin/\nendef\n\n$(eval $(call BuildPackage,ubi-utils))\n$(eval $(call BuildPackage,nand-utils))\n"
  },
  {
    "path": "package/utils/mtd-utils/patches/100-fix_includes.patch",
    "content": "--- a/lib/libfec.c\n+++ b/lib/libfec.c\n@@ -45,6 +45,7 @@\n #include <stdio.h>\n #include <stdlib.h>\n #include <string.h>\n+#include <sys/types.h>\n #include \"libfec.h\"\n \n /*\n"
  },
  {
    "path": "package/utils/mtd-utils/patches/130-lzma_jffs2.patch",
    "content": "--- a/jffsX-utils/Makemodule.am\n+++ b/jffsX-utils/Makemodule.am\n@@ -4,7 +4,10 @@ mkfs_jffs2_SOURCES = \\\n \tjffsX-utils/compr_zlib.c \\\n \tjffsX-utils/compr.h \\\n \tjffsX-utils/rbtree.c \\\n-\tjffsX-utils/compr_lzo.c \\\n+\tjffsX-utils/compr_lzma.c \\\n+\tjffsX-utils/lzma/LzFind.c \\\n+\tjffsX-utils/lzma/LzmaEnc.c \\\n+\tjffsX-utils/lzma/LzmaDec.c \\\n \tjffsX-utils/compr.c \\\n \tjffsX-utils/compr_rtime.c \\\n \tjffsX-utils/compr.h \\\n@@ -12,8 +15,13 @@ mkfs_jffs2_SOURCES = \\\n \tjffsX-utils/summary.h \\\n \tinclude/linux/jffs2.h \\\n \tinclude/mtd/jffs2-user.h\n+\n+if !WITHOUT_LZO\n+mkfs_jffs2_SOURCES += jffsX-utils/compr_lzo.c\n+endif\n+\n mkfs_jffs2_LDADD = libmtd.a $(ZLIB_LIBS) $(LZO_LIBS)\n-mkfs_jffs2_CPPFLAGS = $(AM_CPPFLAGS) $(ZLIB_CFLAGS) $(LZO_CFLAGS)\n+mkfs_jffs2_CPPFLAGS = $(AM_CPPFLAGS) $(ZLIB_CFLAGS) $(LZO_CFLAGS) -I./include/linux/lzma\n \n jffs2reader_SOURCES = jffsX-utils/jffs2reader.c\tinclude/mtd/jffs2-user.h\n jffs2reader_LDADD = libmtd.a $(ZLIB_LIBS) $(LZO_LIBS)\n--- a/jffsX-utils/compr.c\n+++ b/jffsX-utils/compr.c\n@@ -520,6 +520,9 @@ int jffs2_compressors_init(void)\n #ifdef CONFIG_JFFS2_LZO\n \tjffs2_lzo_init();\n #endif\n+#ifdef CONFIG_JFFS2_LZMA\n+\tjffs2_lzma_init();\n+#endif\n \treturn 0;\n }\n \n@@ -534,5 +537,8 @@ int jffs2_compressors_exit(void)\n #ifdef CONFIG_JFFS2_LZO\n \tjffs2_lzo_exit();\n #endif\n+#ifdef CONFIG_JFFS2_LZMA\n+\tjffs2_lzma_exit();\n+#endif\n \treturn 0;\n }\n--- a/jffsX-utils/compr.h\n+++ b/jffsX-utils/compr.h\n@@ -18,13 +18,14 @@\n \n #define CONFIG_JFFS2_ZLIB\n #define CONFIG_JFFS2_RTIME\n-#define CONFIG_JFFS2_LZO\n+#define CONFIG_JFFS2_LZMA\n \n #define JFFS2_RUBINMIPS_PRIORITY 10\n #define JFFS2_DYNRUBIN_PRIORITY  20\n #define JFFS2_RTIME_PRIORITY     50\n-#define JFFS2_ZLIB_PRIORITY      60\n-#define JFFS2_LZO_PRIORITY       80\n+#define JFFS2_LZMA_PRIORITY      70\n+#define JFFS2_ZLIB_PRIORITY      80\n+#define JFFS2_LZO_PRIORITY       90\n \n #define JFFS2_COMPR_MODE_NONE       0\n #define JFFS2_COMPR_MODE_PRIORITY   1\n@@ -115,5 +116,10 @@ void jffs2_rtime_exit(void);\n int jffs2_lzo_init(void);\n void jffs2_lzo_exit(void);\n #endif\n+#ifdef CONFIG_JFFS2_LZMA\n+int jffs2_lzma_init(void);\n+void jffs2_lzma_exit(void);\n+#endif\n+\n \n #endif /* __JFFS2_COMPR_H__ */\n--- /dev/null\n+++ b/jffsX-utils/compr_lzma.c\n@@ -0,0 +1,128 @@\n+/*\n+ * JFFS2 -- Journalling Flash File System, Version 2.\n+ *\n+ * For licensing information, see the file 'LICENCE' in this directory.\n+ *\n+ * JFFS2 wrapper to the LZMA C SDK\n+ *\n+ */\n+\n+#include <linux/lzma.h>\n+#include \"compr.h\"\n+\n+#ifdef __KERNEL__\n+\tstatic DEFINE_MUTEX(deflate_mutex);\n+#endif\n+\n+CLzmaEncHandle *p;\n+Byte propsEncoded[LZMA_PROPS_SIZE];\n+SizeT propsSize = sizeof(propsEncoded);\n+\n+STATIC void lzma_free_workspace(void)\n+{\n+\tLzmaEnc_Destroy(p, &lzma_alloc, &lzma_alloc);\n+}\n+\n+STATIC int INIT lzma_alloc_workspace(CLzmaEncProps *props)\n+{\n+\tif ((p = (CLzmaEncHandle *)LzmaEnc_Create(&lzma_alloc)) == NULL)\n+\t{\n+\t\tPRINT_ERROR(\"Failed to allocate lzma deflate workspace\\n\");\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\tif (LzmaEnc_SetProps(p, props) != SZ_OK)\n+\t{\n+\t\tlzma_free_workspace();\n+\t\treturn -1;\n+\t}\n+\t\n+\tif (LzmaEnc_WriteProperties(p, propsEncoded, &propsSize) != SZ_OK)\n+\t{\n+\t\tlzma_free_workspace();\n+\t\treturn -1;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+STATIC int jffs2_lzma_compress(unsigned char *data_in, unsigned char *cpage_out,\n+\t\t\t      uint32_t *sourcelen, uint32_t *dstlen)\n+{\n+\tSizeT compress_size = (SizeT)(*dstlen);\n+\tint ret;\n+\n+\t#ifdef __KERNEL__\n+\t\tmutex_lock(&deflate_mutex);\n+\t#endif\n+\n+\tret = LzmaEnc_MemEncode(p, cpage_out, &compress_size, data_in, *sourcelen,\n+\t\t0, NULL, &lzma_alloc, &lzma_alloc);\n+\n+\t#ifdef __KERNEL__\n+\t\tmutex_unlock(&deflate_mutex);\n+\t#endif\n+\n+\tif (ret != SZ_OK)\n+\t\treturn -1;\n+\n+\t*dstlen = (uint32_t)compress_size;\n+\n+\treturn 0;\n+}\n+\n+STATIC int jffs2_lzma_decompress(unsigned char *data_in, unsigned char *cpage_out,\n+\t\t\t\t uint32_t srclen, uint32_t destlen)\n+{\n+\tint ret;\n+\tSizeT dl = (SizeT)destlen;\n+\tSizeT sl = (SizeT)srclen;\n+\tELzmaStatus status;\n+\t\n+\tret = LzmaDecode(cpage_out, &dl, data_in, &sl, propsEncoded,\n+\t\tpropsSize, LZMA_FINISH_ANY, &status, &lzma_alloc);\n+\n+\tif (ret != SZ_OK || status == LZMA_STATUS_NOT_FINISHED || dl != (SizeT)destlen)\n+\t\treturn -1;\n+\n+\treturn 0;\n+}\n+\n+static struct jffs2_compressor jffs2_lzma_comp = {\n+\t.priority = JFFS2_LZMA_PRIORITY,\n+\t.name = \"lzma\",\n+\t.compr = JFFS2_COMPR_LZMA,\n+\t.compress = &jffs2_lzma_compress,\n+\t.decompress = &jffs2_lzma_decompress,\n+\t.disabled = 0,\n+};\n+\n+int INIT jffs2_lzma_init(void)\n+{\n+\tint ret;\n+\tCLzmaEncProps props;\n+\tLzmaEncProps_Init(&props);\n+\n+\tprops.dictSize = LZMA_BEST_DICT(0x2000);\n+\tprops.level = LZMA_BEST_LEVEL;\n+\tprops.lc = LZMA_BEST_LC;\n+\tprops.lp = LZMA_BEST_LP;\n+\tprops.pb = LZMA_BEST_PB;\n+\tprops.fb = LZMA_BEST_FB;\n+\n+\tret = lzma_alloc_workspace(&props);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\tret = jffs2_register_compressor(&jffs2_lzma_comp);\n+\tif (ret)\n+\t\tlzma_free_workspace();\n+\t\n+\treturn ret;\n+}\n+\n+void jffs2_lzma_exit(void)\n+{\n+\tjffs2_unregister_compressor(&jffs2_lzma_comp);\n+\tlzma_free_workspace();\n+}\n--- a/include/linux/jffs2.h\n+++ b/include/linux/jffs2.h\n@@ -47,6 +47,7 @@\n #define JFFS2_COMPR_DYNRUBIN\t0x05\n #define JFFS2_COMPR_ZLIB\t0x06\n #define JFFS2_COMPR_LZO\t\t0x07\n+#define JFFS2_COMPR_LZMA\t0x08\n /* Compatibility flags. */\n #define JFFS2_COMPAT_MASK 0xc000      /* What do to if an unknown nodetype is found */\n #define JFFS2_NODE_ACCURATE 0x2000\n--- /dev/null\n+++ b/include/linux/lzma.h\n@@ -0,0 +1,61 @@\n+#ifndef __LZMA_H__\n+#define __LZMA_H__\n+\n+#ifdef __KERNEL__\n+\t#include <linux/kernel.h>\n+\t#include <linux/sched.h>\n+\t#include <linux/slab.h>\n+\t#include <linux/vmalloc.h>\n+\t#include <linux/init.h>\n+\t#define LZMA_MALLOC vmalloc\n+\t#define LZMA_FREE vfree\n+\t#define PRINT_ERROR(msg) printk(KERN_WARNING #msg)\n+\t#define INIT __init\n+\t#define STATIC static\n+#else\n+\t#include <stdint.h>\n+\t#include <stdlib.h>\n+\t#include <stdio.h>\n+\t#include <unistd.h>\n+\t#include <string.h>\n+\t#include <errno.h>\n+\t#include <linux/jffs2.h>\n+\t#ifndef PAGE_SIZE\n+\t\textern int page_size;\n+\t\t#define PAGE_SIZE page_size\n+\t#endif\n+\t#define LZMA_MALLOC malloc\n+\t#define LZMA_FREE free\n+\t#define PRINT_ERROR(msg) fprintf(stderr, msg)\n+\t#define INIT\n+\t#define STATIC static\n+#endif\n+\n+#include \"lzma/LzmaDec.h\"\n+#include \"lzma/LzmaEnc.h\"\n+\n+#define LZMA_BEST_LEVEL (9)\n+#define LZMA_BEST_LC    (0)\n+#define LZMA_BEST_LP    (0)\n+#define LZMA_BEST_PB    (0)\n+#define LZMA_BEST_FB  (273)\n+\n+#define LZMA_BEST_DICT(n) (((int)((n) / 2)) * 2)\n+\n+static void *p_lzma_malloc(void *p, size_t size)\n+{\n+\tif (size == 0)\n+\t\treturn NULL;\n+\n+\treturn LZMA_MALLOC(size);\n+}\n+\n+static void p_lzma_free(void *p, void *address)\n+{\n+\tif (address != NULL)\n+\t\tLZMA_FREE(address);\n+}\n+\n+static ISzAlloc lzma_alloc = {p_lzma_malloc, p_lzma_free};\n+\n+#endif\n--- /dev/null\n+++ b/include/linux/lzma/LzFind.h\n@@ -0,0 +1,116 @@\n+/* LzFind.h  -- Match finder for LZ algorithms\n+2008-04-04\n+Copyright (c) 1999-2008 Igor Pavlov\n+You can use any of the following license options:\n+  1) GNU Lesser General Public License (GNU LGPL)\n+  2) Common Public License (CPL)\n+  3) Common Development and Distribution License (CDDL) Version 1.0 \n+  4) Igor Pavlov, as the author of this code, expressly permits you to \n+     statically or dynamically link your code (or bind by name) to this file, \n+     while you keep this file unmodified.\n+*/\n+\n+#ifndef __LZFIND_H\n+#define __LZFIND_H\n+\n+#include \"Types.h\"\n+\n+typedef UInt32 CLzRef;\n+\n+typedef struct _CMatchFinder\n+{\n+  Byte *buffer;\n+  UInt32 pos;\n+  UInt32 posLimit;\n+  UInt32 streamPos;\n+  UInt32 lenLimit;\n+\n+  UInt32 cyclicBufferPos;\n+  UInt32 cyclicBufferSize; /* it must be = (historySize + 1) */\n+\n+  UInt32 matchMaxLen;\n+  CLzRef *hash;\n+  CLzRef *son;\n+  UInt32 hashMask;\n+  UInt32 cutValue;\n+\n+  Byte *bufferBase;\n+  ISeqInStream *stream;\n+  int streamEndWasReached;\n+\n+  UInt32 blockSize;\n+  UInt32 keepSizeBefore;\n+  UInt32 keepSizeAfter;\n+\n+  UInt32 numHashBytes;\n+  int directInput;\n+  int btMode;\n+  /* int skipModeBits; */\n+  int bigHash;\n+  UInt32 historySize;\n+  UInt32 fixedHashSize;\n+  UInt32 hashSizeSum;\n+  UInt32 numSons;\n+  SRes result;\n+  UInt32 crc[256];\n+} CMatchFinder;\n+\n+#define Inline_MatchFinder_GetPointerToCurrentPos(p) ((p)->buffer)\n+#define Inline_MatchFinder_GetIndexByte(p, index) ((p)->buffer[(Int32)(index)])\n+\n+#define Inline_MatchFinder_GetNumAvailableBytes(p) ((p)->streamPos - (p)->pos)\n+\n+int MatchFinder_NeedMove(CMatchFinder *p);\n+Byte *MatchFinder_GetPointerToCurrentPos(CMatchFinder *p);\n+void MatchFinder_MoveBlock(CMatchFinder *p);\n+void MatchFinder_ReadIfRequired(CMatchFinder *p);\n+\n+void MatchFinder_Construct(CMatchFinder *p);\n+\n+/* Conditions:\n+     historySize <= 3 GB\n+     keepAddBufferBefore + matchMaxLen + keepAddBufferAfter < 511MB\n+*/\n+int MatchFinder_Create(CMatchFinder *p, UInt32 historySize, \n+    UInt32 keepAddBufferBefore, UInt32 matchMaxLen, UInt32 keepAddBufferAfter,\n+    ISzAlloc *alloc);\n+void MatchFinder_Free(CMatchFinder *p, ISzAlloc *alloc);\n+void MatchFinder_Normalize3(UInt32 subValue, CLzRef *items, UInt32 numItems);\n+void MatchFinder_ReduceOffsets(CMatchFinder *p, UInt32 subValue);\n+\n+UInt32 * GetMatchesSpec1(UInt32 lenLimit, UInt32 curMatch, UInt32 pos, const Byte *buffer, CLzRef *son, \n+    UInt32 _cyclicBufferPos, UInt32 _cyclicBufferSize, UInt32 _cutValue, \n+    UInt32 *distances, UInt32 maxLen);\n+\n+/* \n+Conditions:\n+  Mf_GetNumAvailableBytes_Func must be called before each Mf_GetMatchLen_Func.\n+  Mf_GetPointerToCurrentPos_Func's result must be used only before any other function\n+*/\n+\n+typedef void (*Mf_Init_Func)(void *object);\n+typedef Byte (*Mf_GetIndexByte_Func)(void *object, Int32 index);\n+typedef UInt32 (*Mf_GetNumAvailableBytes_Func)(void *object);\n+typedef const Byte * (*Mf_GetPointerToCurrentPos_Func)(void *object);\n+typedef UInt32 (*Mf_GetMatches_Func)(void *object, UInt32 *distances);\n+typedef void (*Mf_Skip_Func)(void *object, UInt32);\n+\n+typedef struct _IMatchFinder\n+{\n+  Mf_Init_Func Init;\n+  Mf_GetIndexByte_Func GetIndexByte;\n+  Mf_GetNumAvailableBytes_Func GetNumAvailableBytes;\n+  Mf_GetPointerToCurrentPos_Func GetPointerToCurrentPos;\n+  Mf_GetMatches_Func GetMatches;\n+  Mf_Skip_Func Skip;\n+} IMatchFinder;\n+\n+void MatchFinder_CreateVTable(CMatchFinder *p, IMatchFinder *vTable);\n+\n+void MatchFinder_Init(CMatchFinder *p);\n+UInt32 Bt3Zip_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances);\n+UInt32 Hc3Zip_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances);\n+void Bt3Zip_MatchFinder_Skip(CMatchFinder *p, UInt32 num);\n+void Hc3Zip_MatchFinder_Skip(CMatchFinder *p, UInt32 num);\n+\n+#endif\n--- /dev/null\n+++ b/include/linux/lzma/LzHash.h\n@@ -0,0 +1,56 @@\n+/* LzHash.h  -- HASH functions for LZ algorithms\n+2008-03-26\n+Copyright (c) 1999-2008 Igor Pavlov\n+Read LzFind.h for license options */\n+\n+#ifndef __LZHASH_H\n+#define __LZHASH_H\n+\n+#define kHash2Size (1 << 10)\n+#define kHash3Size (1 << 16)\n+#define kHash4Size (1 << 20)\n+\n+#define kFix3HashSize (kHash2Size)\n+#define kFix4HashSize (kHash2Size + kHash3Size)\n+#define kFix5HashSize (kHash2Size + kHash3Size + kHash4Size)\n+\n+#define HASH2_CALC hashValue = cur[0] | ((UInt32)cur[1] << 8);\n+\n+#define HASH3_CALC { \\\n+  UInt32 temp = p->crc[cur[0]] ^ cur[1]; \\\n+  hash2Value = temp & (kHash2Size - 1); \\\n+  hashValue = (temp ^ ((UInt32)cur[2] << 8)) & p->hashMask; }\n+\n+#define HASH4_CALC { \\\n+  UInt32 temp = p->crc[cur[0]] ^ cur[1]; \\\n+  hash2Value = temp & (kHash2Size - 1); \\\n+  hash3Value = (temp ^ ((UInt32)cur[2] << 8)) & (kHash3Size - 1); \\\n+  hashValue = (temp ^ ((UInt32)cur[2] << 8) ^ (p->crc[cur[3]] << 5)) & p->hashMask; }\n+\n+#define HASH5_CALC { \\\n+  UInt32 temp = p->crc[cur[0]] ^ cur[1]; \\\n+  hash2Value = temp & (kHash2Size - 1); \\\n+  hash3Value = (temp ^ ((UInt32)cur[2] << 8)) & (kHash3Size - 1); \\\n+  hash4Value = (temp ^ ((UInt32)cur[2] << 8) ^ (p->crc[cur[3]] << 5)); \\\n+  hashValue = (hash4Value ^ (p->crc[cur[4]] << 3)) & p->hashMask; \\\n+  hash4Value &= (kHash4Size - 1); }\n+\n+/* #define HASH_ZIP_CALC hashValue = ((cur[0] | ((UInt32)cur[1] << 8)) ^ p->crc[cur[2]]) & 0xFFFF; */\n+#define HASH_ZIP_CALC hashValue = ((cur[2] | ((UInt32)cur[0] << 8)) ^ p->crc[cur[1]]) & 0xFFFF;\n+\n+\n+#define MT_HASH2_CALC \\\n+  hash2Value = (p->crc[cur[0]] ^ cur[1]) & (kHash2Size - 1);\n+\n+#define MT_HASH3_CALC { \\\n+  UInt32 temp = p->crc[cur[0]] ^ cur[1]; \\\n+  hash2Value = temp & (kHash2Size - 1); \\\n+  hash3Value = (temp ^ ((UInt32)cur[2] << 8)) & (kHash3Size - 1); }\n+\n+#define MT_HASH4_CALC { \\\n+  UInt32 temp = p->crc[cur[0]] ^ cur[1]; \\\n+  hash2Value = temp & (kHash2Size - 1); \\\n+  hash3Value = (temp ^ ((UInt32)cur[2] << 8)) & (kHash3Size - 1); \\\n+  hash4Value = (temp ^ ((UInt32)cur[2] << 8) ^ (p->crc[cur[3]] << 5)) & (kHash4Size - 1); }\n+\n+#endif\n--- /dev/null\n+++ b/include/linux/lzma/LzmaDec.h\n@@ -0,0 +1,232 @@\n+/* LzmaDec.h -- LZMA Decoder\n+2008-04-29\n+Copyright (c) 1999-2008 Igor Pavlov\n+You can use any of the following license options:\n+  1) GNU Lesser General Public License (GNU LGPL)\n+  2) Common Public License (CPL)\n+  3) Common Development and Distribution License (CDDL) Version 1.0 \n+  4) Igor Pavlov, as the author of this code, expressly permits you to \n+     statically or dynamically link your code (or bind by name) to this file, \n+     while you keep this file unmodified.\n+*/\n+\n+#ifndef __LZMADEC_H\n+#define __LZMADEC_H\n+\n+#include \"Types.h\"\n+\n+/* #define _LZMA_PROB32 */\n+/* _LZMA_PROB32 can increase the speed on some CPUs, \n+   but memory usage for CLzmaDec::probs will be doubled in that case */\n+\n+#ifdef _LZMA_PROB32\n+#define CLzmaProb UInt32\n+#else\n+#define CLzmaProb UInt16\n+#endif\n+\n+\n+/* ---------- LZMA Properties ---------- */  \n+\n+#define LZMA_PROPS_SIZE 5\n+\n+typedef struct _CLzmaProps\n+{\n+  unsigned lc, lp, pb;\n+  UInt32 dicSize;\n+} CLzmaProps;\n+\n+/* LzmaProps_Decode - decodes properties\n+Returns:\n+  SZ_OK\n+  SZ_ERROR_UNSUPPORTED - Unsupported properties\n+*/\n+\n+SRes LzmaProps_Decode(CLzmaProps *p, const Byte *data, unsigned size);\n+\n+\n+/* ---------- LZMA Decoder state ---------- */  \n+\n+/* LZMA_REQUIRED_INPUT_MAX = number of required input bytes for worst case.\n+   Num bits = log2((2^11 / 31) ^ 22) + 26 < 134 + 26 = 160; */\n+\n+#define LZMA_REQUIRED_INPUT_MAX 20\n+\n+typedef struct\n+{\n+  CLzmaProps prop;\n+  CLzmaProb *probs;\n+  Byte *dic;\n+  const Byte *buf;\n+  UInt32 range, code;\n+  SizeT dicPos;\n+  SizeT dicBufSize;\n+  UInt32 processedPos;\n+  UInt32 checkDicSize;\n+  unsigned state;\n+  UInt32 reps[4];\n+  unsigned remainLen;\n+  int needFlush;\n+  int needInitState;\n+  UInt32 numProbs;\n+  unsigned tempBufSize;\n+  Byte tempBuf[LZMA_REQUIRED_INPUT_MAX];\n+} CLzmaDec;\n+\n+#define LzmaDec_Construct(p) { (p)->dic = 0; (p)->probs = 0; }\n+\n+void LzmaDec_Init(CLzmaDec *p);\n+\n+/* There are two types of LZMA streams:\n+     0) Stream with end mark. That end mark adds about 6 bytes to compressed size.\n+     1) Stream without end mark. You must know exact uncompressed size to decompress such stream. */\n+\n+typedef enum \n+{\n+  LZMA_FINISH_ANY,   /* finish at any point */      \n+  LZMA_FINISH_END    /* block must be finished at the end */\n+} ELzmaFinishMode;\n+\n+/* ELzmaFinishMode has meaning only if the decoding reaches output limit !!!\n+\n+   You must use LZMA_FINISH_END, when you know that current output buffer \n+   covers last bytes of block. In other cases you must use LZMA_FINISH_ANY.\n+\n+   If LZMA decoder sees end marker before reaching output limit, it returns SZ_OK,\n+   and output value of destLen will be less than output buffer size limit.\n+   You can check status result also.\n+\n+   You can use multiple checks to test data integrity after full decompression:\n+     1) Check Result and \"status\" variable.\n+     2) Check that output(destLen) = uncompressedSize, if you know real uncompressedSize.\n+     3) Check that output(srcLen) = compressedSize, if you know real compressedSize. \n+        You must use correct finish mode in that case. */ \n+\n+typedef enum \n+{\n+  LZMA_STATUS_NOT_SPECIFIED,               /* use main error code instead */\n+  LZMA_STATUS_FINISHED_WITH_MARK,          /* stream was finished with end mark. */\n+  LZMA_STATUS_NOT_FINISHED,                /* stream was not finished */\n+  LZMA_STATUS_NEEDS_MORE_INPUT,            /* you must provide more input bytes */   \n+  LZMA_STATUS_MAYBE_FINISHED_WITHOUT_MARK  /* there is probability that stream was finished without end mark */\n+} ELzmaStatus;\n+\n+/* ELzmaStatus is used only as output value for function call */\n+\n+\n+/* ---------- Interfaces ---------- */  \n+\n+/* There are 3 levels of interfaces:\n+     1) Dictionary Interface\n+     2) Buffer Interface\n+     3) One Call Interface\n+   You can select any of these interfaces, but don't mix functions from different \n+   groups for same object. */\n+\n+\n+/* There are two variants to allocate state for Dictionary Interface:\n+     1) LzmaDec_Allocate / LzmaDec_Free\n+     2) LzmaDec_AllocateProbs / LzmaDec_FreeProbs\n+   You can use variant 2, if you set dictionary buffer manually. \n+   For Buffer Interface you must always use variant 1. \n+\n+LzmaDec_Allocate* can return:\n+  SZ_OK\n+  SZ_ERROR_MEM         - Memory allocation error\n+  SZ_ERROR_UNSUPPORTED - Unsupported properties\n+*/\n+   \n+SRes LzmaDec_AllocateProbs(CLzmaDec *p, const Byte *props, unsigned propsSize, ISzAlloc *alloc);\n+void LzmaDec_FreeProbs(CLzmaDec *p, ISzAlloc *alloc);\n+\n+SRes LzmaDec_Allocate(CLzmaDec *state, const Byte *prop, unsigned propsSize, ISzAlloc *alloc);\n+void LzmaDec_Free(CLzmaDec *state, ISzAlloc *alloc);\n+\n+/* ---------- Dictionary Interface ---------- */  \n+\n+/* You can use it, if you want to eliminate the overhead for data copying from \n+   dictionary to some other external buffer.\n+   You must work with CLzmaDec variables directly in this interface.\n+\n+   STEPS:\n+     LzmaDec_Constr()\n+     LzmaDec_Allocate()\n+     for (each new stream)\n+     {\n+       LzmaDec_Init()\n+       while (it needs more decompression)\n+       {\n+         LzmaDec_DecodeToDic()\n+         use data from CLzmaDec::dic and update CLzmaDec::dicPos\n+       }\n+     }\n+     LzmaDec_Free()\n+*/\n+\n+/* LzmaDec_DecodeToDic\n+   \n+   The decoding to internal dictionary buffer (CLzmaDec::dic).\n+   You must manually update CLzmaDec::dicPos, if it reaches CLzmaDec::dicBufSize !!! \n+\n+finishMode:\n+  It has meaning only if the decoding reaches output limit (dicLimit).\n+  LZMA_FINISH_ANY - Decode just dicLimit bytes.\n+  LZMA_FINISH_END - Stream must be finished after dicLimit.\n+\n+Returns:\n+  SZ_OK\n+    status:\n+      LZMA_STATUS_FINISHED_WITH_MARK\n+      LZMA_STATUS_NOT_FINISHED \n+      LZMA_STATUS_NEEDS_MORE_INPUT\n+      LZMA_STATUS_MAYBE_FINISHED_WITHOUT_MARK\n+  SZ_ERROR_DATA - Data error\n+*/\n+\n+SRes LzmaDec_DecodeToDic(CLzmaDec *p, SizeT dicLimit, \n+    const Byte *src, SizeT *srcLen, ELzmaFinishMode finishMode, ELzmaStatus *status);\n+\n+\n+/* ---------- Buffer Interface ---------- */  \n+\n+/* It's zlib-like interface.\n+   See LzmaDec_DecodeToDic description for information about STEPS and return results,\n+   but you must use LzmaDec_DecodeToBuf instead of LzmaDec_DecodeToDic and you don't need\n+   to work with CLzmaDec variables manually.\n+\n+finishMode: \n+  It has meaning only if the decoding reaches output limit (*destLen).\n+  LZMA_FINISH_ANY - Decode just destLen bytes.\n+  LZMA_FINISH_END - Stream must be finished after (*destLen).\n+*/\n+\n+SRes LzmaDec_DecodeToBuf(CLzmaDec *p, Byte *dest, SizeT *destLen, \n+    const Byte *src, SizeT *srcLen, ELzmaFinishMode finishMode, ELzmaStatus *status);\n+\n+\n+/* ---------- One Call Interface ---------- */  \n+\n+/* LzmaDecode\n+\n+finishMode:\n+  It has meaning only if the decoding reaches output limit (*destLen).\n+  LZMA_FINISH_ANY - Decode just destLen bytes.\n+  LZMA_FINISH_END - Stream must be finished after (*destLen).\n+\n+Returns:\n+  SZ_OK\n+    status:\n+      LZMA_STATUS_FINISHED_WITH_MARK\n+      LZMA_STATUS_NOT_FINISHED \n+      LZMA_STATUS_MAYBE_FINISHED_WITHOUT_MARK\n+  SZ_ERROR_DATA - Data error\n+  SZ_ERROR_MEM  - Memory allocation error\n+  SZ_ERROR_UNSUPPORTED - Unsupported properties\n+  SZ_ERROR_INPUT_EOF - It needs more bytes in input buffer (src).\n+*/\n+\n+SRes LzmaDecode(Byte *dest, SizeT *destLen, const Byte *src, SizeT *srcLen,\n+    const Byte *propData, unsigned propSize, ELzmaFinishMode finishMode, \n+    ELzmaStatus *status, ISzAlloc *alloc);\n+\n+#endif\n--- /dev/null\n+++ b/include/linux/lzma/LzmaEnc.h\n@@ -0,0 +1,74 @@\n+/*  LzmaEnc.h -- LZMA Encoder\n+2008-04-27\n+Copyright (c) 1999-2008 Igor Pavlov\n+Read LzFind.h for license options */\n+\n+#ifndef __LZMAENC_H\n+#define __LZMAENC_H\n+\n+#include \"Types.h\"\n+\n+#define LZMA_PROPS_SIZE 5\n+\n+typedef struct _CLzmaEncProps\n+{\n+  int level;       /*  0 <= level <= 9 */ \n+  UInt32 dictSize; /* (1 << 12) <= dictSize <= (1 << 27) for 32-bit version\n+                      (1 << 12) <= dictSize <= (1 << 30) for 64-bit version \n+                       default = (1 << 24) */\n+  int lc;          /* 0 <= lc <= 8, default = 3 */ \n+  int lp;          /* 0 <= lp <= 4, default = 0 */ \n+  int pb;          /* 0 <= pb <= 4, default = 2 */ \n+  int algo;        /* 0 - fast, 1 - normal, default = 1 */\n+  int fb;          /* 5 <= fb <= 273, default = 32 */\n+  int btMode;      /* 0 - hashChain Mode, 1 - binTree mode - normal, default = 1 */\n+  int numHashBytes; /* 2, 3 or 4, default = 4 */\n+  UInt32 mc;        /* 1 <= mc <= (1 << 30), default = 32 */\n+  unsigned writeEndMark;  /* 0 - do not write EOPM, 1 - write EOPM, default = 0 */\n+  int numThreads;  /* 1 or 2, default = 2 */\n+} CLzmaEncProps;\n+\n+void LzmaEncProps_Init(CLzmaEncProps *p);\n+void LzmaEncProps_Normalize(CLzmaEncProps *p);\n+UInt32 LzmaEncProps_GetDictSize(const CLzmaEncProps *props2);\n+\n+\n+/* ---------- CLzmaEncHandle Interface ---------- */\n+\n+/* LzmaEnc_* functions can return the following exit codes:\n+Returns:\n+  SZ_OK           - OK\n+  SZ_ERROR_MEM    - Memory allocation error \n+  SZ_ERROR_PARAM  - Incorrect paramater in props\n+  SZ_ERROR_WRITE  - Write callback error.\n+  SZ_ERROR_PROGRESS - some break from progress callback\n+  SZ_ERROR_THREAD - errors in multithreading functions (only for Mt version)\n+*/\n+\n+typedef void * CLzmaEncHandle;\n+\n+CLzmaEncHandle LzmaEnc_Create(ISzAlloc *alloc);\n+void LzmaEnc_Destroy(CLzmaEncHandle p, ISzAlloc *alloc, ISzAlloc *allocBig);\n+SRes LzmaEnc_SetProps(CLzmaEncHandle p, const CLzmaEncProps *props);\n+SRes LzmaEnc_WriteProperties(CLzmaEncHandle p, Byte *properties, SizeT *size);\n+SRes LzmaEnc_Encode(CLzmaEncHandle p, ISeqOutStream *outStream, ISeqInStream *inStream, \n+    ICompressProgress *progress, ISzAlloc *alloc, ISzAlloc *allocBig);\n+SRes LzmaEnc_MemEncode(CLzmaEncHandle p, Byte *dest, SizeT *destLen, const Byte *src, SizeT srcLen,\n+    int writeEndMark, ICompressProgress *progress, ISzAlloc *alloc, ISzAlloc *allocBig);\n+\n+/* ---------- One Call Interface ---------- */\n+\n+/* LzmaEncode\n+Return code:\n+  SZ_OK               - OK\n+  SZ_ERROR_MEM        - Memory allocation error \n+  SZ_ERROR_PARAM      - Incorrect paramater\n+  SZ_ERROR_OUTPUT_EOF - output buffer overflow\n+  SZ_ERROR_THREAD     - errors in multithreading functions (only for Mt version)\n+*/\n+\n+SRes LzmaEncode(Byte *dest, SizeT *destLen, const Byte *src, SizeT srcLen,\n+    const CLzmaEncProps *props, Byte *propsEncoded, SizeT *propsSize, int writeEndMark, \n+    ICompressProgress *progress, ISzAlloc *alloc, ISzAlloc *allocBig);\n+\n+#endif\n--- /dev/null\n+++ b/include/linux/lzma/Types.h\n@@ -0,0 +1,130 @@\n+/* Types.h -- Basic types\n+2008-04-11\n+Igor Pavlov\n+Public domain */\n+\n+#ifndef __7Z_TYPES_H\n+#define __7Z_TYPES_H\n+\n+#define SZ_OK 0\n+\n+#define SZ_ERROR_DATA 1\n+#define SZ_ERROR_MEM 2\n+#define SZ_ERROR_CRC 3\n+#define SZ_ERROR_UNSUPPORTED 4\n+#define SZ_ERROR_PARAM 5\n+#define SZ_ERROR_INPUT_EOF 6\n+#define SZ_ERROR_OUTPUT_EOF 7\n+#define SZ_ERROR_READ 8\n+#define SZ_ERROR_WRITE 9\n+#define SZ_ERROR_PROGRESS 10\n+#define SZ_ERROR_FAIL 11\n+#define SZ_ERROR_THREAD 12\n+\n+#define SZ_ERROR_ARCHIVE 16\n+#define SZ_ERROR_NO_ARCHIVE 17\n+\n+typedef int SRes;\n+\n+#ifndef RINOK\n+#define RINOK(x) { int __result__ = (x); if (__result__ != 0) return __result__; }\n+#endif\n+\n+typedef unsigned char Byte;\n+typedef short Int16;\n+typedef unsigned short UInt16;\n+\n+#ifdef _LZMA_UINT32_IS_ULONG\n+typedef long Int32;\n+typedef unsigned long UInt32;\n+#else\n+typedef int Int32;\n+typedef unsigned int UInt32;\n+#endif\n+\n+/* #define _SZ_NO_INT_64 */\n+/* define it if your compiler doesn't support 64-bit integers */\n+\n+#ifdef _SZ_NO_INT_64\n+\n+typedef long Int64;\n+typedef unsigned long UInt64;\n+\n+#else\n+\n+#if defined(_MSC_VER) || defined(__BORLANDC__)\n+typedef __int64 Int64;\n+typedef unsigned __int64 UInt64;\n+#else\n+typedef long long int Int64;\n+typedef unsigned long long int UInt64;\n+#endif\n+\n+#endif\n+\n+#ifdef _LZMA_NO_SYSTEM_SIZE_T\n+typedef UInt32 SizeT;\n+#else\n+#include <stddef.h>\n+typedef size_t SizeT;\n+#endif\n+\n+typedef int Bool;\n+#define True 1\n+#define False 0\n+\n+\n+#ifdef _MSC_VER\n+\n+#if _MSC_VER >= 1300\n+#define MY_NO_INLINE __declspec(noinline)\n+#else\n+#define MY_NO_INLINE\n+#endif\n+\n+#define MY_CDECL __cdecl\n+#define MY_STD_CALL __stdcall \n+#define MY_FAST_CALL MY_NO_INLINE __fastcall \n+\n+#else\n+\n+#define MY_CDECL\n+#define MY_STD_CALL\n+#define MY_FAST_CALL\n+\n+#endif\n+\n+\n+/* The following interfaces use first parameter as pointer to structure */\n+\n+typedef struct\n+{\n+  SRes (*Read)(void *p, void *buf, size_t *size);\n+    /* if (input(*size) != 0 && output(*size) == 0) means end_of_stream.\n+       (output(*size) < input(*size)) is allowed */\n+} ISeqInStream;\n+\n+typedef struct\n+{\n+  size_t (*Write)(void *p, const void *buf, size_t size);\n+    /* Returns: result - the number of actually written bytes.\n+      (result < size) means error */\n+} ISeqOutStream;\n+\n+typedef struct\n+{\n+  SRes (*Progress)(void *p, UInt64 inSize, UInt64 outSize);\n+    /* Returns: result. (result != SZ_OK) means break.\n+       Value (UInt64)(Int64)-1 for size means unknown value. */\n+} ICompressProgress;\n+\n+typedef struct\n+{\n+  void *(*Alloc)(void *p, size_t size);\n+  void (*Free)(void *p, void *address); /* address can be 0 */\n+} ISzAlloc;\n+\n+#define IAlloc_Alloc(p, size) (p)->Alloc((p), size)\n+#define IAlloc_Free(p, a) (p)->Free((p), a)\n+\n+#endif\n--- /dev/null\n+++ b/jffsX-utils/lzma/LzFind.c\n@@ -0,0 +1,753 @@\n+/* LzFind.c  -- Match finder for LZ algorithms\n+2008-04-04\n+Copyright (c) 1999-2008 Igor Pavlov\n+Read LzFind.h for license options */\n+\n+#include <string.h>\n+\n+#include \"LzFind.h\"\n+#include \"LzHash.h\"\n+\n+#define kEmptyHashValue 0\n+#define kMaxValForNormalize ((UInt32)0xFFFFFFFF)\n+#define kNormalizeStepMin (1 << 10) /* it must be power of 2 */\n+#define kNormalizeMask (~(kNormalizeStepMin - 1))\n+#define kMaxHistorySize ((UInt32)3 << 30)\n+\n+#define kStartMaxLen 3\n+\n+static void LzInWindow_Free(CMatchFinder *p, ISzAlloc *alloc)\n+{\n+  if (!p->directInput)\n+  {\n+    alloc->Free(alloc, p->bufferBase);\n+    p->bufferBase = 0;\n+  }\n+}\n+\n+/* keepSizeBefore + keepSizeAfter + keepSizeReserv must be < 4G) */\n+\n+static int LzInWindow_Create(CMatchFinder *p, UInt32 keepSizeReserv, ISzAlloc *alloc)\n+{\n+  UInt32 blockSize = p->keepSizeBefore + p->keepSizeAfter + keepSizeReserv;\n+  if (p->directInput)\n+  {\n+    p->blockSize = blockSize;\n+    return 1;\n+  }\n+  if (p->bufferBase == 0 || p->blockSize != blockSize)\n+  {\n+    LzInWindow_Free(p, alloc);\n+    p->blockSize = blockSize;\n+    p->bufferBase = (Byte *)alloc->Alloc(alloc, (size_t)blockSize);\n+  }\n+  return (p->bufferBase != 0);\n+}\n+\n+Byte *MatchFinder_GetPointerToCurrentPos(CMatchFinder *p) { return p->buffer; }\n+static Byte MatchFinder_GetIndexByte(CMatchFinder *p, Int32 index) { return p->buffer[index]; }\n+\n+static UInt32 MatchFinder_GetNumAvailableBytes(CMatchFinder *p) { return p->streamPos - p->pos; }\n+\n+void MatchFinder_ReduceOffsets(CMatchFinder *p, UInt32 subValue)\n+{\n+  p->posLimit -= subValue;\n+  p->pos -= subValue;\n+  p->streamPos -= subValue;\n+}\n+\n+static void MatchFinder_ReadBlock(CMatchFinder *p)\n+{\n+  if (p->streamEndWasReached || p->result != SZ_OK)\n+    return;\n+  for (;;)\n+  {\n+    Byte *dest = p->buffer + (p->streamPos - p->pos);\n+    size_t size = (p->bufferBase + p->blockSize - dest);\n+    if (size == 0)\n+      return;\n+    p->result = p->stream->Read(p->stream, dest, &size);\n+    if (p->result != SZ_OK)\n+      return;\n+    if (size == 0)\n+    {\n+      p->streamEndWasReached = 1;\n+      return;\n+    }\n+    p->streamPos += (UInt32)size;\n+    if (p->streamPos - p->pos > p->keepSizeAfter)\n+      return;\n+  }\n+}\n+\n+void MatchFinder_MoveBlock(CMatchFinder *p)\n+{\n+  memmove(p->bufferBase, \n+    p->buffer - p->keepSizeBefore, \n+    (size_t)(p->streamPos - p->pos + p->keepSizeBefore));\n+  p->buffer = p->bufferBase + p->keepSizeBefore;\n+}\n+\n+int MatchFinder_NeedMove(CMatchFinder *p)\n+{\n+  /* if (p->streamEndWasReached) return 0; */\n+  return ((size_t)(p->bufferBase + p->blockSize - p->buffer) <= p->keepSizeAfter);\n+}\n+\n+void MatchFinder_ReadIfRequired(CMatchFinder *p)\n+{\n+  if (p->streamEndWasReached) \n+    return;\n+  if (p->keepSizeAfter >= p->streamPos - p->pos)\n+    MatchFinder_ReadBlock(p);\n+}\n+\n+static void MatchFinder_CheckAndMoveAndRead(CMatchFinder *p)\n+{\n+  if (MatchFinder_NeedMove(p))\n+    MatchFinder_MoveBlock(p);\n+  MatchFinder_ReadBlock(p);\n+}\n+\n+static void MatchFinder_SetDefaultSettings(CMatchFinder *p)\n+{\n+  p->cutValue = 32;\n+  p->btMode = 1;\n+  p->numHashBytes = 4;\n+  /* p->skipModeBits = 0; */\n+  p->directInput = 0;\n+  p->bigHash = 0;\n+}\n+\n+#define kCrcPoly 0xEDB88320\n+\n+void MatchFinder_Construct(CMatchFinder *p)\n+{\n+  UInt32 i;\n+  p->bufferBase = 0;\n+  p->directInput = 0;\n+  p->hash = 0;\n+  MatchFinder_SetDefaultSettings(p);\n+\n+  for (i = 0; i < 256; i++)\n+  {\n+    UInt32 r = i;\n+    int j;\n+    for (j = 0; j < 8; j++)\n+      r = (r >> 1) ^ (kCrcPoly & ~((r & 1) - 1));\n+    p->crc[i] = r;\n+  }\n+}\n+\n+static void MatchFinder_FreeThisClassMemory(CMatchFinder *p, ISzAlloc *alloc)\n+{\n+  alloc->Free(alloc, p->hash);\n+  p->hash = 0;\n+}\n+\n+void MatchFinder_Free(CMatchFinder *p, ISzAlloc *alloc)\n+{\n+  MatchFinder_FreeThisClassMemory(p, alloc);\n+  LzInWindow_Free(p, alloc);\n+}\n+\n+static CLzRef* AllocRefs(UInt32 num, ISzAlloc *alloc)\n+{\n+  size_t sizeInBytes = (size_t)num * sizeof(CLzRef);\n+  if (sizeInBytes / sizeof(CLzRef) != num)\n+    return 0;\n+  return (CLzRef *)alloc->Alloc(alloc, sizeInBytes);\n+}\n+\n+int MatchFinder_Create(CMatchFinder *p, UInt32 historySize, \n+    UInt32 keepAddBufferBefore, UInt32 matchMaxLen, UInt32 keepAddBufferAfter,\n+    ISzAlloc *alloc)\n+{\n+  UInt32 sizeReserv;\n+  if (historySize > kMaxHistorySize)\n+  {\n+    MatchFinder_Free(p, alloc);\n+    return 0;\n+  }\n+  sizeReserv = historySize >> 1;\n+  if (historySize > ((UInt32)2 << 30))\n+    sizeReserv = historySize >> 2;\n+  sizeReserv += (keepAddBufferBefore + matchMaxLen + keepAddBufferAfter) / 2 + (1 << 19);\n+\n+  p->keepSizeBefore = historySize + keepAddBufferBefore + 1; \n+  p->keepSizeAfter = matchMaxLen + keepAddBufferAfter;\n+  /* we need one additional byte, since we use MoveBlock after pos++ and before dictionary using */\n+  if (LzInWindow_Create(p, sizeReserv, alloc))\n+  {\n+    UInt32 newCyclicBufferSize = (historySize /* >> p->skipModeBits */) + 1;\n+    UInt32 hs;\n+    p->matchMaxLen = matchMaxLen;\n+    {\n+      p->fixedHashSize = 0;\n+      if (p->numHashBytes == 2)\n+        hs = (1 << 16) - 1;\n+      else\n+      {\n+        hs = historySize - 1;\n+        hs |= (hs >> 1);\n+        hs |= (hs >> 2);\n+        hs |= (hs >> 4);\n+        hs |= (hs >> 8);\n+        hs >>= 1;\n+        /* hs >>= p->skipModeBits; */\n+        hs |= 0xFFFF; /* don't change it! It's required for Deflate */\n+        if (hs > (1 << 24))\n+        {\n+          if (p->numHashBytes == 3)\n+            hs = (1 << 24) - 1;\n+          else\n+            hs >>= 1;\n+        }\n+      }\n+      p->hashMask = hs;\n+      hs++;\n+      if (p->numHashBytes > 2) p->fixedHashSize += kHash2Size;\n+      if (p->numHashBytes > 3) p->fixedHashSize += kHash3Size;\n+      if (p->numHashBytes > 4) p->fixedHashSize += kHash4Size;\n+      hs += p->fixedHashSize;\n+    }\n+\n+    {\n+      UInt32 prevSize = p->hashSizeSum + p->numSons;\n+      UInt32 newSize;\n+      p->historySize = historySize;\n+      p->hashSizeSum = hs;\n+      p->cyclicBufferSize = newCyclicBufferSize;\n+      p->numSons = (p->btMode ? newCyclicBufferSize * 2 : newCyclicBufferSize);\n+      newSize = p->hashSizeSum + p->numSons;\n+      if (p->hash != 0 && prevSize == newSize)\n+        return 1;\n+      MatchFinder_FreeThisClassMemory(p, alloc);\n+      p->hash = AllocRefs(newSize, alloc);\n+      if (p->hash != 0)\n+      {\n+        p->son = p->hash + p->hashSizeSum;\n+        return 1;\n+      }\n+    }\n+  }\n+  MatchFinder_Free(p, alloc);\n+  return 0;\n+}\n+\n+static void MatchFinder_SetLimits(CMatchFinder *p)\n+{\n+  UInt32 limit = kMaxValForNormalize - p->pos;\n+  UInt32 limit2 = p->cyclicBufferSize - p->cyclicBufferPos;\n+  if (limit2 < limit) \n+    limit = limit2;\n+  limit2 = p->streamPos - p->pos;\n+  if (limit2 <= p->keepSizeAfter)\n+  {\n+    if (limit2 > 0)\n+      limit2 = 1;\n+  }\n+  else\n+    limit2 -= p->keepSizeAfter;\n+  if (limit2 < limit) \n+    limit = limit2;\n+  {\n+    UInt32 lenLimit = p->streamPos - p->pos;\n+    if (lenLimit > p->matchMaxLen)\n+      lenLimit = p->matchMaxLen;\n+    p->lenLimit = lenLimit;\n+  }\n+  p->posLimit = p->pos + limit;\n+}\n+\n+void MatchFinder_Init(CMatchFinder *p)\n+{\n+  UInt32 i;\n+  for(i = 0; i < p->hashSizeSum; i++)\n+    p->hash[i] = kEmptyHashValue;\n+  p->cyclicBufferPos = 0;\n+  p->buffer = p->bufferBase;\n+  p->pos = p->streamPos = p->cyclicBufferSize;\n+  p->result = SZ_OK;\n+  p->streamEndWasReached = 0;\n+  MatchFinder_ReadBlock(p);\n+  MatchFinder_SetLimits(p);\n+}\n+\n+static UInt32 MatchFinder_GetSubValue(CMatchFinder *p) \n+{ \n+  return (p->pos - p->historySize - 1) & kNormalizeMask; \n+}\n+\n+void MatchFinder_Normalize3(UInt32 subValue, CLzRef *items, UInt32 numItems)\n+{\n+  UInt32 i;\n+  for (i = 0; i < numItems; i++)\n+  {\n+    UInt32 value = items[i];\n+    if (value <= subValue)\n+      value = kEmptyHashValue;\n+    else\n+      value -= subValue;\n+    items[i] = value;\n+  }\n+}\n+\n+static void MatchFinder_Normalize(CMatchFinder *p)\n+{\n+  UInt32 subValue = MatchFinder_GetSubValue(p);\n+  MatchFinder_Normalize3(subValue, p->hash, p->hashSizeSum + p->numSons);\n+  MatchFinder_ReduceOffsets(p, subValue);\n+}\n+\n+static void MatchFinder_CheckLimits(CMatchFinder *p)\n+{\n+  if (p->pos == kMaxValForNormalize)\n+    MatchFinder_Normalize(p);\n+  if (!p->streamEndWasReached && p->keepSizeAfter == p->streamPos - p->pos)\n+    MatchFinder_CheckAndMoveAndRead(p);\n+  if (p->cyclicBufferPos == p->cyclicBufferSize)\n+    p->cyclicBufferPos = 0;\n+  MatchFinder_SetLimits(p);\n+}\n+\n+static UInt32 * Hc_GetMatchesSpec(UInt32 lenLimit, UInt32 curMatch, UInt32 pos, const Byte *cur, CLzRef *son, \n+    UInt32 _cyclicBufferPos, UInt32 _cyclicBufferSize, UInt32 cutValue, \n+    UInt32 *distances, UInt32 maxLen)\n+{\n+  son[_cyclicBufferPos] = curMatch;\n+  for (;;)\n+  {\n+    UInt32 delta = pos - curMatch;\n+    if (cutValue-- == 0 || delta >= _cyclicBufferSize)\n+      return distances;\n+    {\n+      const Byte *pb = cur - delta;\n+      curMatch = son[_cyclicBufferPos - delta + ((delta > _cyclicBufferPos) ? _cyclicBufferSize : 0)];\n+      if (pb[maxLen] == cur[maxLen] && *pb == *cur)\n+      {\n+        UInt32 len = 0;\n+        while(++len != lenLimit)\n+          if (pb[len] != cur[len])\n+            break;\n+        if (maxLen < len)\n+        {\n+          *distances++ = maxLen = len;\n+          *distances++ = delta - 1;\n+          if (len == lenLimit)\n+            return distances;\n+        }\n+      }\n+    }\n+  }\n+}\n+\n+UInt32 * GetMatchesSpec1(UInt32 lenLimit, UInt32 curMatch, UInt32 pos, const Byte *cur, CLzRef *son, \n+    UInt32 _cyclicBufferPos, UInt32 _cyclicBufferSize, UInt32 cutValue, \n+    UInt32 *distances, UInt32 maxLen)\n+{\n+  CLzRef *ptr0 = son + (_cyclicBufferPos << 1) + 1;\n+  CLzRef *ptr1 = son + (_cyclicBufferPos << 1);\n+  UInt32 len0 = 0, len1 = 0;\n+  for (;;)\n+  {\n+    UInt32 delta = pos - curMatch;\n+    if (cutValue-- == 0 || delta >= _cyclicBufferSize)\n+    {\n+      *ptr0 = *ptr1 = kEmptyHashValue;\n+      return distances;\n+    }\n+    {\n+      CLzRef *pair = son + ((_cyclicBufferPos - delta + ((delta > _cyclicBufferPos) ? _cyclicBufferSize : 0)) << 1);\n+      const Byte *pb = cur - delta;\n+      UInt32 len = (len0 < len1 ? len0 : len1);\n+      if (pb[len] == cur[len])\n+      {\n+        if (++len != lenLimit && pb[len] == cur[len])\n+          while(++len != lenLimit)\n+            if (pb[len] != cur[len])\n+              break;\n+        if (maxLen < len)\n+        {\n+          *distances++ = maxLen = len;\n+          *distances++ = delta - 1;\n+          if (len == lenLimit)\n+          {\n+            *ptr1 = pair[0];\n+            *ptr0 = pair[1];\n+            return distances;\n+          }\n+        }\n+      }\n+      if (pb[len] < cur[len])\n+      {\n+        *ptr1 = curMatch;\n+        ptr1 = pair + 1;\n+        curMatch = *ptr1;\n+        len1 = len;\n+      }\n+      else\n+      {\n+        *ptr0 = curMatch;\n+        ptr0 = pair;\n+        curMatch = *ptr0;\n+        len0 = len;\n+      }\n+    }\n+  }\n+}\n+\n+static void SkipMatchesSpec(UInt32 lenLimit, UInt32 curMatch, UInt32 pos, const Byte *cur, CLzRef *son, \n+    UInt32 _cyclicBufferPos, UInt32 _cyclicBufferSize, UInt32 cutValue)\n+{\n+  CLzRef *ptr0 = son + (_cyclicBufferPos << 1) + 1;\n+  CLzRef *ptr1 = son + (_cyclicBufferPos << 1);\n+  UInt32 len0 = 0, len1 = 0;\n+  for (;;)\n+  {\n+    UInt32 delta = pos - curMatch;\n+    if (cutValue-- == 0 || delta >= _cyclicBufferSize)\n+    {\n+      *ptr0 = *ptr1 = kEmptyHashValue;\n+      return;\n+    }\n+    {\n+      CLzRef *pair = son + ((_cyclicBufferPos - delta + ((delta > _cyclicBufferPos) ? _cyclicBufferSize : 0)) << 1);\n+      const Byte *pb = cur - delta;\n+      UInt32 len = (len0 < len1 ? len0 : len1);\n+      if (pb[len] == cur[len])\n+      {\n+        while(++len != lenLimit)\n+          if (pb[len] != cur[len])\n+            break;\n+        {\n+          if (len == lenLimit)\n+          {\n+            *ptr1 = pair[0];\n+            *ptr0 = pair[1];\n+            return;\n+          }\n+        }\n+      }\n+      if (pb[len] < cur[len])\n+      {\n+        *ptr1 = curMatch;\n+        ptr1 = pair + 1;\n+        curMatch = *ptr1;\n+        len1 = len;\n+      }\n+      else\n+      {\n+        *ptr0 = curMatch;\n+        ptr0 = pair;\n+        curMatch = *ptr0;\n+        len0 = len;\n+      }\n+    }\n+  }\n+}\n+\n+#define MOVE_POS \\\n+  ++p->cyclicBufferPos; \\\n+  p->buffer++; \\\n+  if (++p->pos == p->posLimit) MatchFinder_CheckLimits(p);\n+\n+#define MOVE_POS_RET MOVE_POS return offset;\n+\n+static void MatchFinder_MovePos(CMatchFinder *p) { MOVE_POS; }\n+\n+#define GET_MATCHES_HEADER2(minLen, ret_op) \\\n+  UInt32 lenLimit; UInt32 hashValue; const Byte *cur; UInt32 curMatch; \\\n+  lenLimit = p->lenLimit; { if (lenLimit < minLen) { MatchFinder_MovePos(p); ret_op; }} \\\n+  cur = p->buffer;\n+\n+#define GET_MATCHES_HEADER(minLen) GET_MATCHES_HEADER2(minLen, return 0)\n+#define SKIP_HEADER(minLen)        GET_MATCHES_HEADER2(minLen, continue)\n+\n+#define MF_PARAMS(p) p->pos, p->buffer, p->son, p->cyclicBufferPos, p->cyclicBufferSize, p->cutValue\n+\n+#define GET_MATCHES_FOOTER(offset, maxLen) \\\n+  offset = (UInt32)(GetMatchesSpec1(lenLimit, curMatch, MF_PARAMS(p), \\\n+  distances + offset, maxLen) - distances); MOVE_POS_RET;\n+\n+#define SKIP_FOOTER \\\n+  SkipMatchesSpec(lenLimit, curMatch, MF_PARAMS(p)); MOVE_POS;\n+\n+static UInt32 Bt2_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances)\n+{\n+  UInt32 offset;\n+  GET_MATCHES_HEADER(2)\n+  HASH2_CALC;\n+  curMatch = p->hash[hashValue];\n+  p->hash[hashValue] = p->pos;\n+  offset = 0;\n+  GET_MATCHES_FOOTER(offset, 1)\n+}\n+\n+UInt32 Bt3Zip_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances)\n+{\n+  UInt32 offset;\n+  GET_MATCHES_HEADER(3)\n+  HASH_ZIP_CALC;\n+  curMatch = p->hash[hashValue];\n+  p->hash[hashValue] = p->pos;\n+  offset = 0;\n+  GET_MATCHES_FOOTER(offset, 2)\n+}\n+\n+static UInt32 Bt3_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances)\n+{\n+  UInt32 hash2Value, delta2, maxLen, offset;\n+  GET_MATCHES_HEADER(3)\n+\n+  HASH3_CALC;\n+\n+  delta2 = p->pos - p->hash[hash2Value];\n+  curMatch = p->hash[kFix3HashSize + hashValue];\n+  \n+  p->hash[hash2Value] = \n+  p->hash[kFix3HashSize + hashValue] = p->pos;\n+\n+\n+  maxLen = 2;\n+  offset = 0;\n+  if (delta2 < p->cyclicBufferSize && *(cur - delta2) == *cur)\n+  {\n+    for (; maxLen != lenLimit; maxLen++)\n+      if (cur[(ptrdiff_t)maxLen - delta2] != cur[maxLen])\n+        break;\n+    distances[0] = maxLen;\n+    distances[1] = delta2 - 1;\n+    offset = 2;\n+    if (maxLen == lenLimit)\n+    {\n+      SkipMatchesSpec(lenLimit, curMatch, MF_PARAMS(p));\n+      MOVE_POS_RET; \n+    }\n+  }\n+  GET_MATCHES_FOOTER(offset, maxLen)\n+}\n+\n+static UInt32 Bt4_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances)\n+{\n+  UInt32 hash2Value, hash3Value, delta2, delta3, maxLen, offset;\n+  GET_MATCHES_HEADER(4)\n+\n+  HASH4_CALC;\n+\n+  delta2 = p->pos - p->hash[                hash2Value];\n+  delta3 = p->pos - p->hash[kFix3HashSize + hash3Value];\n+  curMatch = p->hash[kFix4HashSize + hashValue];\n+  \n+  p->hash[                hash2Value] =\n+  p->hash[kFix3HashSize + hash3Value] =\n+  p->hash[kFix4HashSize + hashValue] = p->pos;\n+\n+  maxLen = 1;\n+  offset = 0;\n+  if (delta2 < p->cyclicBufferSize && *(cur - delta2) == *cur)\n+  {\n+    distances[0] = maxLen = 2;\n+    distances[1] = delta2 - 1;\n+    offset = 2;\n+  }\n+  if (delta2 != delta3 && delta3 < p->cyclicBufferSize && *(cur - delta3) == *cur)\n+  {\n+    maxLen = 3;\n+    distances[offset + 1] = delta3 - 1;\n+    offset += 2;\n+    delta2 = delta3;\n+  }\n+  if (offset != 0)\n+  {\n+    for (; maxLen != lenLimit; maxLen++)\n+      if (cur[(ptrdiff_t)maxLen - delta2] != cur[maxLen])\n+        break;\n+    distances[offset - 2] = maxLen;\n+    if (maxLen == lenLimit)\n+    {\n+      SkipMatchesSpec(lenLimit, curMatch, MF_PARAMS(p));\n+      MOVE_POS_RET; \n+    }\n+  }\n+  if (maxLen < 3)\n+    maxLen = 3;\n+  GET_MATCHES_FOOTER(offset, maxLen)\n+}\n+\n+static UInt32 Hc4_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances)\n+{\n+  UInt32 hash2Value, hash3Value, delta2, delta3, maxLen, offset;\n+  GET_MATCHES_HEADER(4)\n+\n+  HASH4_CALC;\n+\n+  delta2 = p->pos - p->hash[                hash2Value];\n+  delta3 = p->pos - p->hash[kFix3HashSize + hash3Value];\n+  curMatch = p->hash[kFix4HashSize + hashValue];\n+\n+  p->hash[                hash2Value] =\n+  p->hash[kFix3HashSize + hash3Value] =\n+  p->hash[kFix4HashSize + hashValue] = p->pos;\n+\n+  maxLen = 1;\n+  offset = 0;\n+  if (delta2 < p->cyclicBufferSize && *(cur - delta2) == *cur)\n+  {\n+    distances[0] = maxLen = 2;\n+    distances[1] = delta2 - 1;\n+    offset = 2;\n+  }\n+  if (delta2 != delta3 && delta3 < p->cyclicBufferSize && *(cur - delta3) == *cur)\n+  {\n+    maxLen = 3;\n+    distances[offset + 1] = delta3 - 1;\n+    offset += 2;\n+    delta2 = delta3;\n+  }\n+  if (offset != 0)\n+  {\n+    for (; maxLen != lenLimit; maxLen++)\n+      if (cur[(ptrdiff_t)maxLen - delta2] != cur[maxLen])\n+        break;\n+    distances[offset - 2] = maxLen;\n+    if (maxLen == lenLimit)\n+    {\n+      p->son[p->cyclicBufferPos] = curMatch;\n+      MOVE_POS_RET; \n+    }\n+  }\n+  if (maxLen < 3)\n+    maxLen = 3;\n+  offset = (UInt32)(Hc_GetMatchesSpec(lenLimit, curMatch, MF_PARAMS(p),\n+    distances + offset, maxLen) - (distances));\n+  MOVE_POS_RET\n+}\n+\n+UInt32 Hc3Zip_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances)\n+{\n+  UInt32 offset;\n+  GET_MATCHES_HEADER(3)\n+  HASH_ZIP_CALC;\n+  curMatch = p->hash[hashValue];\n+  p->hash[hashValue] = p->pos;\n+  offset = (UInt32)(Hc_GetMatchesSpec(lenLimit, curMatch, MF_PARAMS(p),\n+    distances, 2) - (distances));\n+  MOVE_POS_RET\n+}\n+\n+static void Bt2_MatchFinder_Skip(CMatchFinder *p, UInt32 num)\n+{\n+  do\n+  {\n+    SKIP_HEADER(2) \n+    HASH2_CALC;\n+    curMatch = p->hash[hashValue];\n+    p->hash[hashValue] = p->pos;\n+    SKIP_FOOTER\n+  }\n+  while (--num != 0);\n+}\n+\n+void Bt3Zip_MatchFinder_Skip(CMatchFinder *p, UInt32 num)\n+{\n+  do\n+  {\n+    SKIP_HEADER(3)\n+    HASH_ZIP_CALC;\n+    curMatch = p->hash[hashValue];\n+    p->hash[hashValue] = p->pos;\n+    SKIP_FOOTER\n+  }\n+  while (--num != 0);\n+}\n+\n+static void Bt3_MatchFinder_Skip(CMatchFinder *p, UInt32 num)\n+{\n+  do\n+  {\n+    UInt32 hash2Value;\n+    SKIP_HEADER(3)\n+    HASH3_CALC;\n+    curMatch = p->hash[kFix3HashSize + hashValue];\n+    p->hash[hash2Value] =\n+    p->hash[kFix3HashSize + hashValue] = p->pos;\n+    SKIP_FOOTER\n+  }\n+  while (--num != 0);\n+}\n+\n+static void Bt4_MatchFinder_Skip(CMatchFinder *p, UInt32 num)\n+{\n+  do\n+  {\n+    UInt32 hash2Value, hash3Value;\n+    SKIP_HEADER(4) \n+    HASH4_CALC;\n+    curMatch = p->hash[kFix4HashSize + hashValue];\n+    p->hash[                hash2Value] =\n+    p->hash[kFix3HashSize + hash3Value] = p->pos;\n+    p->hash[kFix4HashSize + hashValue] = p->pos;\n+    SKIP_FOOTER\n+  }\n+  while (--num != 0);\n+}\n+\n+static void Hc4_MatchFinder_Skip(CMatchFinder *p, UInt32 num)\n+{\n+  do\n+  {\n+    UInt32 hash2Value, hash3Value;\n+    SKIP_HEADER(4)\n+    HASH4_CALC;\n+    curMatch = p->hash[kFix4HashSize + hashValue];\n+    p->hash[                hash2Value] =\n+    p->hash[kFix3HashSize + hash3Value] =\n+    p->hash[kFix4HashSize + hashValue] = p->pos;\n+    p->son[p->cyclicBufferPos] = curMatch;\n+    MOVE_POS\n+  }\n+  while (--num != 0);\n+}\n+\n+void Hc3Zip_MatchFinder_Skip(CMatchFinder *p, UInt32 num)\n+{\n+  do\n+  {\n+    SKIP_HEADER(3)\n+    HASH_ZIP_CALC;\n+    curMatch = p->hash[hashValue];\n+    p->hash[hashValue] = p->pos;\n+    p->son[p->cyclicBufferPos] = curMatch;\n+    MOVE_POS\n+  }\n+  while (--num != 0);\n+}\n+\n+void MatchFinder_CreateVTable(CMatchFinder *p, IMatchFinder *vTable)\n+{\n+  vTable->Init = (Mf_Init_Func)MatchFinder_Init;\n+  vTable->GetIndexByte = (Mf_GetIndexByte_Func)MatchFinder_GetIndexByte;\n+  vTable->GetNumAvailableBytes = (Mf_GetNumAvailableBytes_Func)MatchFinder_GetNumAvailableBytes;\n+  vTable->GetPointerToCurrentPos = (Mf_GetPointerToCurrentPos_Func)MatchFinder_GetPointerToCurrentPos;\n+  if (!p->btMode)\n+  {\n+    vTable->GetMatches = (Mf_GetMatches_Func)Hc4_MatchFinder_GetMatches;\n+    vTable->Skip = (Mf_Skip_Func)Hc4_MatchFinder_Skip;\n+  }\n+  else if (p->numHashBytes == 2)\n+  {\n+    vTable->GetMatches = (Mf_GetMatches_Func)Bt2_MatchFinder_GetMatches;\n+    vTable->Skip = (Mf_Skip_Func)Bt2_MatchFinder_Skip;\n+  }\n+  else if (p->numHashBytes == 3)\n+  {\n+    vTable->GetMatches = (Mf_GetMatches_Func)Bt3_MatchFinder_GetMatches;\n+    vTable->Skip = (Mf_Skip_Func)Bt3_MatchFinder_Skip;\n+  }\n+  else\n+  {\n+    vTable->GetMatches = (Mf_GetMatches_Func)Bt4_MatchFinder_GetMatches;\n+    vTable->Skip = (Mf_Skip_Func)Bt4_MatchFinder_Skip;\n+  }\n+}\n--- /dev/null\n+++ b/jffsX-utils/lzma/LzmaDec.c\n@@ -0,0 +1,1014 @@\n+/* LzmaDec.c -- LZMA Decoder\n+2008-04-29\n+Copyright (c) 1999-2008 Igor Pavlov\n+Read LzmaDec.h for license options */\n+\n+#include \"LzmaDec.h\"\n+\n+#include <string.h>\n+\n+#define kNumTopBits 24\n+#define kTopValue ((UInt32)1 << kNumTopBits)\n+\n+#define kNumBitModelTotalBits 11\n+#define kBitModelTotal (1 << kNumBitModelTotalBits)\n+#define kNumMoveBits 5\n+\n+#define RC_INIT_SIZE 5\n+\n+#define NORMALIZE if (range < kTopValue) { range <<= 8; code = (code << 8) | (*buf++); }\n+\n+#define IF_BIT_0(p) ttt = *(p); NORMALIZE; bound = (range >> kNumBitModelTotalBits) * ttt; if (code < bound)\n+#define UPDATE_0(p) range = bound; *(p) = (CLzmaProb)(ttt + ((kBitModelTotal - ttt) >> kNumMoveBits));\n+#define UPDATE_1(p) range -= bound; code -= bound; *(p) = (CLzmaProb)(ttt - (ttt >> kNumMoveBits));\n+#define GET_BIT2(p, i, A0, A1) IF_BIT_0(p) \\\n+  { UPDATE_0(p); i = (i + i); A0; } else \\\n+  { UPDATE_1(p); i = (i + i) + 1; A1; } \n+#define GET_BIT(p, i) GET_BIT2(p, i, ; , ;)               \n+\n+#define TREE_GET_BIT(probs, i) { GET_BIT((probs + i), i); }\n+#define TREE_DECODE(probs, limit, i) \\\n+  { i = 1; do { TREE_GET_BIT(probs, i); } while (i < limit); i -= limit; }\n+\n+/* #define _LZMA_SIZE_OPT */\n+\n+#ifdef _LZMA_SIZE_OPT\n+#define TREE_6_DECODE(probs, i) TREE_DECODE(probs, (1 << 6), i)\n+#else\n+#define TREE_6_DECODE(probs, i) \\\n+  { i = 1; \\\n+  TREE_GET_BIT(probs, i); \\\n+  TREE_GET_BIT(probs, i); \\\n+  TREE_GET_BIT(probs, i); \\\n+  TREE_GET_BIT(probs, i); \\\n+  TREE_GET_BIT(probs, i); \\\n+  TREE_GET_BIT(probs, i); \\\n+  i -= 0x40; }\n+#endif\n+\n+#define NORMALIZE_CHECK if (range < kTopValue) { if (buf >= bufLimit) return DUMMY_ERROR; range <<= 8; code = (code << 8) | (*buf++); }\n+\n+#define IF_BIT_0_CHECK(p) ttt = *(p); NORMALIZE_CHECK; bound = (range >> kNumBitModelTotalBits) * ttt; if (code < bound)\n+#define UPDATE_0_CHECK range = bound;\n+#define UPDATE_1_CHECK range -= bound; code -= bound;\n+#define GET_BIT2_CHECK(p, i, A0, A1) IF_BIT_0_CHECK(p) \\\n+  { UPDATE_0_CHECK; i = (i + i); A0; } else \\\n+  { UPDATE_1_CHECK; i = (i + i) + 1; A1; } \n+#define GET_BIT_CHECK(p, i) GET_BIT2_CHECK(p, i, ; , ;)               \n+#define TREE_DECODE_CHECK(probs, limit, i) \\\n+  { i = 1; do { GET_BIT_CHECK(probs + i, i) } while(i < limit); i -= limit; }\n+\n+\n+#define kNumPosBitsMax 4\n+#define kNumPosStatesMax (1 << kNumPosBitsMax)\n+\n+#define kLenNumLowBits 3\n+#define kLenNumLowSymbols (1 << kLenNumLowBits)\n+#define kLenNumMidBits 3\n+#define kLenNumMidSymbols (1 << kLenNumMidBits)\n+#define kLenNumHighBits 8\n+#define kLenNumHighSymbols (1 << kLenNumHighBits)\n+\n+#define LenChoice 0\n+#define LenChoice2 (LenChoice + 1)\n+#define LenLow (LenChoice2 + 1)\n+#define LenMid (LenLow + (kNumPosStatesMax << kLenNumLowBits))\n+#define LenHigh (LenMid + (kNumPosStatesMax << kLenNumMidBits))\n+#define kNumLenProbs (LenHigh + kLenNumHighSymbols) \n+\n+\n+#define kNumStates 12\n+#define kNumLitStates 7\n+\n+#define kStartPosModelIndex 4\n+#define kEndPosModelIndex 14\n+#define kNumFullDistances (1 << (kEndPosModelIndex >> 1))\n+\n+#define kNumPosSlotBits 6\n+#define kNumLenToPosStates 4\n+\n+#define kNumAlignBits 4\n+#define kAlignTableSize (1 << kNumAlignBits)\n+\n+#define kMatchMinLen 2\n+#define kMatchSpecLenStart (kMatchMinLen + kLenNumLowSymbols + kLenNumMidSymbols + kLenNumHighSymbols)\n+\n+#define IsMatch 0\n+#define IsRep (IsMatch + (kNumStates << kNumPosBitsMax))\n+#define IsRepG0 (IsRep + kNumStates)\n+#define IsRepG1 (IsRepG0 + kNumStates)\n+#define IsRepG2 (IsRepG1 + kNumStates)\n+#define IsRep0Long (IsRepG2 + kNumStates)\n+#define PosSlot (IsRep0Long + (kNumStates << kNumPosBitsMax))\n+#define SpecPos (PosSlot + (kNumLenToPosStates << kNumPosSlotBits))\n+#define Align (SpecPos + kNumFullDistances - kEndPosModelIndex)\n+#define LenCoder (Align + kAlignTableSize)\n+#define RepLenCoder (LenCoder + kNumLenProbs)\n+#define Literal (RepLenCoder + kNumLenProbs)\n+\n+#define LZMA_BASE_SIZE 1846\n+#define LZMA_LIT_SIZE 768\n+\n+#define LzmaProps_GetNumProbs(p) ((UInt32)LZMA_BASE_SIZE + (LZMA_LIT_SIZE << ((p)->lc + (p)->lp)))\n+\n+#if Literal != LZMA_BASE_SIZE\n+StopCompilingDueBUG\n+#endif\n+\n+/*\n+#define LZMA_STREAM_WAS_FINISHED_ID (-1)\n+#define LZMA_SPEC_LEN_OFFSET (-3)\n+*/\n+\n+Byte kLiteralNextStates[kNumStates * 2] = \n+{\n+  0, 0, 0, 0, 1, 2, 3,  4,  5,  6,  4,  5, \n+  7, 7, 7, 7, 7, 7, 7, 10, 10, 10, 10, 10\n+};\n+\n+#define LZMA_DIC_MIN (1 << 12)\n+\n+/* First LZMA-symbol is always decoded. \n+And it decodes new LZMA-symbols while (buf < bufLimit), but \"buf\" is without last normalization \n+Out:\n+  Result:\n+    0 - OK\n+    1 - Error\n+  p->remainLen:\n+    < kMatchSpecLenStart : normal remain\n+    = kMatchSpecLenStart : finished\n+    = kMatchSpecLenStart + 1 : Flush marker\n+    = kMatchSpecLenStart + 2 : State Init Marker\n+*/\n+\n+static int MY_FAST_CALL LzmaDec_DecodeReal(CLzmaDec *p, SizeT limit, const Byte *bufLimit)\n+{\n+  CLzmaProb *probs = p->probs;\n+\n+  unsigned state = p->state;\n+  UInt32 rep0 = p->reps[0], rep1 = p->reps[1], rep2 = p->reps[2], rep3 = p->reps[3];\n+  unsigned pbMask = ((unsigned)1 << (p->prop.pb)) - 1;\n+  unsigned lpMask = ((unsigned)1 << (p->prop.lp)) - 1;\n+  unsigned lc = p->prop.lc;\n+\n+  Byte *dic = p->dic;\n+  SizeT dicBufSize = p->dicBufSize;\n+  SizeT dicPos = p->dicPos;\n+  \n+  UInt32 processedPos = p->processedPos;\n+  UInt32 checkDicSize = p->checkDicSize;\n+  unsigned len = 0;\n+\n+  const Byte *buf = p->buf;\n+  UInt32 range = p->range;\n+  UInt32 code = p->code;\n+\n+  do\n+  {\n+    CLzmaProb *prob;\n+    UInt32 bound;\n+    unsigned ttt;\n+    unsigned posState = processedPos & pbMask;\n+\n+    prob = probs + IsMatch + (state << kNumPosBitsMax) + posState;\n+    IF_BIT_0(prob)\n+    {\n+      unsigned symbol;\n+      UPDATE_0(prob);\n+      prob = probs + Literal;\n+      if (checkDicSize != 0 || processedPos != 0)\n+        prob += (LZMA_LIT_SIZE * (((processedPos & lpMask) << lc) + \n+        (dic[(dicPos == 0 ? dicBufSize : dicPos) - 1] >> (8 - lc))));\n+\n+      if (state < kNumLitStates)\n+      {\n+        symbol = 1;\n+        do { GET_BIT(prob + symbol, symbol) } while (symbol < 0x100);\n+      }\n+      else\n+      {\n+        unsigned matchByte = p->dic[(dicPos - rep0) + ((dicPos < rep0) ? dicBufSize : 0)];\n+        unsigned offs = 0x100;\n+        symbol = 1;\n+        do\n+        {\n+          unsigned bit;\n+          CLzmaProb *probLit;\n+          matchByte <<= 1;\n+          bit = (matchByte & offs);\n+          probLit = prob + offs + bit + symbol;\n+          GET_BIT2(probLit, symbol, offs &= ~bit, offs &= bit)\n+        }\n+        while (symbol < 0x100);\n+      }\n+      dic[dicPos++] = (Byte)symbol;\n+      processedPos++;\n+\n+      state = kLiteralNextStates[state];\n+      /* if (state < 4) state = 0; else if (state < 10) state -= 3; else state -= 6; */\n+      continue;\n+    }\n+    else             \n+    {\n+      UPDATE_1(prob);\n+      prob = probs + IsRep + state;\n+      IF_BIT_0(prob)\n+      {\n+        UPDATE_0(prob);\n+        state += kNumStates;\n+        prob = probs + LenCoder;\n+      }\n+      else\n+      {\n+        UPDATE_1(prob);\n+        if (checkDicSize == 0 && processedPos == 0)\n+          return SZ_ERROR_DATA;\n+        prob = probs + IsRepG0 + state;\n+        IF_BIT_0(prob)\n+        {\n+          UPDATE_0(prob);\n+          prob = probs + IsRep0Long + (state << kNumPosBitsMax) + posState;\n+          IF_BIT_0(prob)\n+          {\n+            UPDATE_0(prob);\n+            dic[dicPos] = dic[(dicPos - rep0) + ((dicPos < rep0) ? dicBufSize : 0)];\n+            dicPos++;\n+            processedPos++;\n+            state = state < kNumLitStates ? 9 : 11;\n+            continue;\n+          }\n+          UPDATE_1(prob);\n+        }\n+        else\n+        {\n+          UInt32 distance;\n+          UPDATE_1(prob);\n+          prob = probs + IsRepG1 + state;\n+          IF_BIT_0(prob)\n+          {\n+            UPDATE_0(prob);\n+            distance = rep1;\n+          }\n+          else \n+          {\n+            UPDATE_1(prob);\n+            prob = probs + IsRepG2 + state;\n+            IF_BIT_0(prob)\n+            {\n+              UPDATE_0(prob);\n+              distance = rep2;\n+            }\n+            else\n+            {\n+              UPDATE_1(prob);\n+              distance = rep3;\n+              rep3 = rep2;\n+            }\n+            rep2 = rep1;\n+          }\n+          rep1 = rep0;\n+          rep0 = distance;\n+        }\n+        state = state < kNumLitStates ? 8 : 11;\n+        prob = probs + RepLenCoder;\n+      }\n+      {\n+        unsigned limit, offset;\n+        CLzmaProb *probLen = prob + LenChoice;\n+        IF_BIT_0(probLen)\n+        {\n+          UPDATE_0(probLen);\n+          probLen = prob + LenLow + (posState << kLenNumLowBits);\n+          offset = 0;\n+          limit = (1 << kLenNumLowBits);\n+        }\n+        else\n+        {\n+          UPDATE_1(probLen);\n+          probLen = prob + LenChoice2;\n+          IF_BIT_0(probLen)\n+          {\n+            UPDATE_0(probLen);\n+            probLen = prob + LenMid + (posState << kLenNumMidBits);\n+            offset = kLenNumLowSymbols;\n+            limit = (1 << kLenNumMidBits);\n+          }\n+          else\n+          {\n+            UPDATE_1(probLen);\n+            probLen = prob + LenHigh;\n+            offset = kLenNumLowSymbols + kLenNumMidSymbols;\n+            limit = (1 << kLenNumHighBits);\n+          }\n+        }\n+        TREE_DECODE(probLen, limit, len);\n+        len += offset;\n+      }\n+\n+      if (state >= kNumStates)\n+      {\n+        UInt32 distance;\n+        prob = probs + PosSlot +\n+            ((len < kNumLenToPosStates ? len : kNumLenToPosStates - 1) << kNumPosSlotBits);\n+        TREE_6_DECODE(prob, distance);\n+        if (distance >= kStartPosModelIndex)\n+        {\n+          unsigned posSlot = (unsigned)distance; \n+          int numDirectBits = (int)(((distance >> 1) - 1));\n+          distance = (2 | (distance & 1));\n+          if (posSlot < kEndPosModelIndex)\n+          {\n+            distance <<= numDirectBits;\n+            prob = probs + SpecPos + distance - posSlot - 1;\n+            {\n+              UInt32 mask = 1;\n+              unsigned i = 1;\n+              do\n+              {\n+                GET_BIT2(prob + i, i, ; , distance |= mask);\n+                mask <<= 1;\n+              }\n+              while(--numDirectBits != 0);\n+            }\n+          }\n+          else\n+          {\n+            numDirectBits -= kNumAlignBits;\n+            do\n+            {\n+              NORMALIZE\n+              range >>= 1;\n+              \n+              {\n+                UInt32 t;\n+                code -= range;\n+                t = (0 - ((UInt32)code >> 31)); /* (UInt32)((Int32)code >> 31) */\n+                distance = (distance << 1) + (t + 1);\n+                code += range & t;\n+              }\n+              /*\n+              distance <<= 1;\n+              if (code >= range)\n+              {\n+                code -= range;\n+                distance |= 1;\n+              }\n+              */\n+            }\n+            while (--numDirectBits != 0);\n+            prob = probs + Align;\n+            distance <<= kNumAlignBits;\n+            {\n+              unsigned i = 1;\n+              GET_BIT2(prob + i, i, ; , distance |= 1);\n+              GET_BIT2(prob + i, i, ; , distance |= 2);\n+              GET_BIT2(prob + i, i, ; , distance |= 4);\n+              GET_BIT2(prob + i, i, ; , distance |= 8);\n+            }\n+            if (distance == (UInt32)0xFFFFFFFF)\n+            {\n+              len += kMatchSpecLenStart;\n+              state -= kNumStates;\n+              break;\n+            }\n+          }\n+        }\n+        rep3 = rep2;\n+        rep2 = rep1;\n+        rep1 = rep0;\n+        rep0 = distance + 1; \n+        if (checkDicSize == 0)\n+        {\n+          if (distance >= processedPos)\n+            return SZ_ERROR_DATA;\n+        }\n+        else if (distance >= checkDicSize)\n+          return SZ_ERROR_DATA;\n+        state = (state < kNumStates + kNumLitStates) ? kNumLitStates : kNumLitStates + 3;\n+        /* state = kLiteralNextStates[state]; */\n+      }\n+\n+      len += kMatchMinLen;\n+\n+      {\n+        SizeT rem = limit - dicPos;\n+        unsigned curLen = ((rem < len) ? (unsigned)rem : len);\n+        SizeT pos = (dicPos - rep0) + ((dicPos < rep0) ? dicBufSize : 0);\n+\n+        processedPos += curLen;\n+\n+        len -= curLen;\n+        if (pos + curLen <= dicBufSize)\n+        {\n+          Byte *dest = dic + dicPos;\n+          ptrdiff_t src = (ptrdiff_t)pos - (ptrdiff_t)dicPos;\n+          const Byte *lim = dest + curLen;\n+          dicPos += curLen;\n+          do \n+            *(dest) = (Byte)*(dest + src); \n+          while (++dest != lim);\n+        }\n+        else\n+        {\n+          do\n+          {\n+            dic[dicPos++] = dic[pos];\n+            if (++pos == dicBufSize)\n+              pos = 0;\n+          }\n+          while (--curLen != 0);\n+        }\n+      }\n+    }\n+  }\n+  while (dicPos < limit && buf < bufLimit);\n+  NORMALIZE;\n+  p->buf = buf;\n+  p->range = range;\n+  p->code = code;\n+  p->remainLen = len;\n+  p->dicPos = dicPos;\n+  p->processedPos = processedPos;\n+  p->reps[0] = rep0;\n+  p->reps[1] = rep1;\n+  p->reps[2] = rep2;\n+  p->reps[3] = rep3;\n+  p->state = state;\n+\n+  return SZ_OK;\n+}\n+\n+static void MY_FAST_CALL LzmaDec_WriteRem(CLzmaDec *p, SizeT limit)\n+{\n+  if (p->remainLen != 0 && p->remainLen < kMatchSpecLenStart)\n+  {\n+    Byte *dic = p->dic;\n+    SizeT dicPos = p->dicPos;\n+    SizeT dicBufSize = p->dicBufSize;\n+    unsigned len = p->remainLen;\n+    UInt32 rep0 = p->reps[0];\n+    if (limit - dicPos < len)\n+      len = (unsigned)(limit - dicPos);\n+\n+    if (p->checkDicSize == 0 && p->prop.dicSize - p->processedPos <= len)\n+      p->checkDicSize = p->prop.dicSize;\n+\n+    p->processedPos += len;\n+    p->remainLen -= len;\n+    while (len-- != 0)\n+    {\n+      dic[dicPos] = dic[(dicPos - rep0) + ((dicPos < rep0) ? dicBufSize : 0)];\n+      dicPos++;\n+    }\n+    p->dicPos = dicPos;\n+  }\n+}\n+\n+/* LzmaDec_DecodeReal2 decodes LZMA-symbols and sets p->needFlush and p->needInit, if required. */\n+\n+static int MY_FAST_CALL LzmaDec_DecodeReal2(CLzmaDec *p, SizeT limit, const Byte *bufLimit)\n+{\n+  do\n+  {\n+    SizeT limit2 = limit;\n+    if (p->checkDicSize == 0)\n+    {\n+      UInt32 rem = p->prop.dicSize - p->processedPos;\n+      if (limit - p->dicPos > rem)\n+        limit2 = p->dicPos + rem;\n+    }\n+    RINOK(LzmaDec_DecodeReal(p, limit2, bufLimit));\n+    if (p->processedPos >= p->prop.dicSize)\n+      p->checkDicSize = p->prop.dicSize;\n+    LzmaDec_WriteRem(p, limit);\n+  }\n+  while (p->dicPos < limit && p->buf < bufLimit && p->remainLen < kMatchSpecLenStart);\n+\n+  if (p->remainLen > kMatchSpecLenStart)\n+  {\n+    p->remainLen = kMatchSpecLenStart;\n+  }\n+  return 0;\n+}\n+\n+typedef enum \n+{\n+  DUMMY_ERROR, /* unexpected end of input stream */\n+  DUMMY_LIT,\n+  DUMMY_MATCH,\n+  DUMMY_REP\n+} ELzmaDummy;\n+\n+static ELzmaDummy LzmaDec_TryDummy(const CLzmaDec *p, const Byte *buf, SizeT inSize)\n+{\n+  UInt32 range = p->range;\n+  UInt32 code = p->code;\n+  const Byte *bufLimit = buf + inSize;\n+  CLzmaProb *probs = p->probs;\n+  unsigned state = p->state;\n+  ELzmaDummy res;\n+\n+  {\n+    CLzmaProb *prob;\n+    UInt32 bound;\n+    unsigned ttt;\n+    unsigned posState = (p->processedPos) & ((1 << p->prop.pb) - 1);\n+\n+    prob = probs + IsMatch + (state << kNumPosBitsMax) + posState;\n+    IF_BIT_0_CHECK(prob)\n+    {\n+      UPDATE_0_CHECK\n+\n+      /* if (bufLimit - buf >= 7) return DUMMY_LIT; */\n+\n+      prob = probs + Literal;\n+      if (p->checkDicSize != 0 || p->processedPos != 0)\n+        prob += (LZMA_LIT_SIZE * \n+          ((((p->processedPos) & ((1 << (p->prop.lp)) - 1)) << p->prop.lc) + \n+          (p->dic[(p->dicPos == 0 ? p->dicBufSize : p->dicPos) - 1] >> (8 - p->prop.lc))));\n+\n+      if (state < kNumLitStates)\n+      {\n+        unsigned symbol = 1;\n+        do { GET_BIT_CHECK(prob + symbol, symbol) } while (symbol < 0x100);\n+      }\n+      else\n+      {\n+        unsigned matchByte = p->dic[p->dicPos - p->reps[0] + \n+            ((p->dicPos < p->reps[0]) ? p->dicBufSize : 0)];\n+        unsigned offs = 0x100;\n+        unsigned symbol = 1;\n+        do\n+        {\n+          unsigned bit;\n+          CLzmaProb *probLit;\n+          matchByte <<= 1;\n+          bit = (matchByte & offs);\n+          probLit = prob + offs + bit + symbol;\n+          GET_BIT2_CHECK(probLit, symbol, offs &= ~bit, offs &= bit)\n+        }\n+        while (symbol < 0x100);\n+      }\n+      res = DUMMY_LIT;\n+    }\n+    else             \n+    {\n+      unsigned len;\n+      UPDATE_1_CHECK;\n+\n+      prob = probs + IsRep + state;\n+      IF_BIT_0_CHECK(prob)\n+      {\n+        UPDATE_0_CHECK;\n+        state = 0;\n+        prob = probs + LenCoder;\n+        res = DUMMY_MATCH;\n+      }\n+      else\n+      {\n+        UPDATE_1_CHECK;\n+        res = DUMMY_REP;\n+        prob = probs + IsRepG0 + state;\n+        IF_BIT_0_CHECK(prob)\n+        {\n+          UPDATE_0_CHECK;\n+          prob = probs + IsRep0Long + (state << kNumPosBitsMax) + posState;\n+          IF_BIT_0_CHECK(prob)\n+          {\n+            UPDATE_0_CHECK;\n+            NORMALIZE_CHECK;\n+            return DUMMY_REP;\n+          }\n+          else\n+          {\n+            UPDATE_1_CHECK;\n+          }\n+        }\n+        else\n+        {\n+          UPDATE_1_CHECK;\n+          prob = probs + IsRepG1 + state;\n+          IF_BIT_0_CHECK(prob)\n+          {\n+            UPDATE_0_CHECK;\n+          }\n+          else \n+          {\n+            UPDATE_1_CHECK;\n+            prob = probs + IsRepG2 + state;\n+            IF_BIT_0_CHECK(prob)\n+            {\n+              UPDATE_0_CHECK;\n+            }\n+            else\n+            {\n+              UPDATE_1_CHECK;\n+            }\n+          }\n+        }\n+        state = kNumStates;\n+        prob = probs + RepLenCoder;\n+      }\n+      {\n+        unsigned limit, offset;\n+        CLzmaProb *probLen = prob + LenChoice;\n+        IF_BIT_0_CHECK(probLen)\n+        {\n+          UPDATE_0_CHECK;\n+          probLen = prob + LenLow + (posState << kLenNumLowBits);\n+          offset = 0;\n+          limit = 1 << kLenNumLowBits;\n+        }\n+        else\n+        {\n+          UPDATE_1_CHECK;\n+          probLen = prob + LenChoice2;\n+          IF_BIT_0_CHECK(probLen)\n+          {\n+            UPDATE_0_CHECK;\n+            probLen = prob + LenMid + (posState << kLenNumMidBits);\n+            offset = kLenNumLowSymbols;\n+            limit = 1 << kLenNumMidBits;\n+          }\n+          else\n+          {\n+            UPDATE_1_CHECK;\n+            probLen = prob + LenHigh;\n+            offset = kLenNumLowSymbols + kLenNumMidSymbols;\n+            limit = 1 << kLenNumHighBits;\n+          }\n+        }\n+        TREE_DECODE_CHECK(probLen, limit, len);\n+        len += offset;\n+      }\n+\n+      if (state < 4)\n+      {\n+        unsigned posSlot;\n+        prob = probs + PosSlot +\n+            ((len < kNumLenToPosStates ? len : kNumLenToPosStates - 1) << \n+            kNumPosSlotBits);\n+        TREE_DECODE_CHECK(prob, 1 << kNumPosSlotBits, posSlot);\n+        if (posSlot >= kStartPosModelIndex)\n+        {\n+          int numDirectBits = ((posSlot >> 1) - 1);\n+\n+          /* if (bufLimit - buf >= 8) return DUMMY_MATCH; */\n+\n+          if (posSlot < kEndPosModelIndex)\n+          {\n+            prob = probs + SpecPos + ((2 | (posSlot & 1)) << numDirectBits) - posSlot - 1;\n+          }\n+          else\n+          {\n+            numDirectBits -= kNumAlignBits;\n+            do\n+            {\n+              NORMALIZE_CHECK\n+              range >>= 1;\n+              code -= range & (((code - range) >> 31) - 1);\n+              /* if (code >= range) code -= range; */\n+            }\n+            while (--numDirectBits != 0);\n+            prob = probs + Align;\n+            numDirectBits = kNumAlignBits;\n+          }\n+          {\n+            unsigned i = 1;\n+            do\n+            {\n+              GET_BIT_CHECK(prob + i, i);\n+            }\n+            while(--numDirectBits != 0);\n+          }\n+        }\n+      }\n+    }\n+  }\n+  NORMALIZE_CHECK;\n+  return res;\n+}\n+\n+\n+static void LzmaDec_InitRc(CLzmaDec *p, const Byte *data)\n+{\n+  p->code = ((UInt32)data[1] << 24) | ((UInt32)data[2] << 16) | ((UInt32)data[3] << 8) | ((UInt32)data[4]);\n+  p->range = 0xFFFFFFFF;\n+  p->needFlush = 0;\n+}\n+\n+static void LzmaDec_InitDicAndState(CLzmaDec *p, Bool initDic, Bool initState) \n+{ \n+  p->needFlush = 1; \n+  p->remainLen = 0; \n+  p->tempBufSize = 0; \n+\n+  if (initDic)\n+  {\n+    p->processedPos = 0;\n+    p->checkDicSize = 0;\n+    p->needInitState = 1;\n+  }\n+  if (initState)\n+    p->needInitState = 1;\n+}\n+\n+void LzmaDec_Init(CLzmaDec *p) \n+{ \n+  p->dicPos = 0; \n+  LzmaDec_InitDicAndState(p, True, True);\n+}\n+\n+static void LzmaDec_InitStateReal(CLzmaDec *p)\n+{\n+  UInt32 numProbs = Literal + ((UInt32)LZMA_LIT_SIZE << (p->prop.lc + p->prop.lp));\n+  UInt32 i;\n+  CLzmaProb *probs = p->probs;\n+  for (i = 0; i < numProbs; i++)\n+    probs[i] = kBitModelTotal >> 1; \n+  p->reps[0] = p->reps[1] = p->reps[2] = p->reps[3] = 1;\n+  p->state = 0;\n+  p->needInitState = 0;\n+}\n+\n+SRes LzmaDec_DecodeToDic(CLzmaDec *p, SizeT dicLimit, const Byte *src, SizeT *srcLen, \n+    ELzmaFinishMode finishMode, ELzmaStatus *status)\n+{\n+  SizeT inSize = *srcLen;\n+  (*srcLen) = 0;\n+  LzmaDec_WriteRem(p, dicLimit);\n+  \n+  *status = LZMA_STATUS_NOT_SPECIFIED;\n+\n+  while (p->remainLen != kMatchSpecLenStart)\n+  {\n+      int checkEndMarkNow;\n+\n+      if (p->needFlush != 0)\n+      {\n+        for (; inSize > 0 && p->tempBufSize < RC_INIT_SIZE; (*srcLen)++, inSize--)\n+          p->tempBuf[p->tempBufSize++] = *src++;\n+        if (p->tempBufSize < RC_INIT_SIZE)\n+        {\n+          *status = LZMA_STATUS_NEEDS_MORE_INPUT;\n+          return SZ_OK;\n+        }\n+        if (p->tempBuf[0] != 0)\n+          return SZ_ERROR_DATA;\n+\n+        LzmaDec_InitRc(p, p->tempBuf);\n+        p->tempBufSize = 0;\n+      }\n+\n+      checkEndMarkNow = 0;\n+      if (p->dicPos >= dicLimit)\n+      {\n+        if (p->remainLen == 0 && p->code == 0)\n+        {\n+          *status = LZMA_STATUS_MAYBE_FINISHED_WITHOUT_MARK;\n+          return SZ_OK;\n+        }\n+        if (finishMode == LZMA_FINISH_ANY)\n+        {\n+          *status = LZMA_STATUS_NOT_FINISHED;\n+          return SZ_OK;\n+        }\n+        if (p->remainLen != 0)\n+        {\n+          *status = LZMA_STATUS_NOT_FINISHED;\n+          return SZ_ERROR_DATA;\n+        }\n+        checkEndMarkNow = 1;\n+      }\n+\n+      if (p->needInitState)\n+        LzmaDec_InitStateReal(p);\n+  \n+      if (p->tempBufSize == 0)\n+      {\n+        SizeT processed;\n+        const Byte *bufLimit;\n+        if (inSize < LZMA_REQUIRED_INPUT_MAX || checkEndMarkNow)\n+        {\n+          int dummyRes = LzmaDec_TryDummy(p, src, inSize);\n+          if (dummyRes == DUMMY_ERROR)\n+          {\n+            memcpy(p->tempBuf, src, inSize);\n+            p->tempBufSize = (unsigned)inSize;\n+            (*srcLen) += inSize;\n+            *status = LZMA_STATUS_NEEDS_MORE_INPUT;\n+            return SZ_OK;\n+          }\n+          if (checkEndMarkNow && dummyRes != DUMMY_MATCH)\n+          {\n+            *status = LZMA_STATUS_NOT_FINISHED;\n+            return SZ_ERROR_DATA;\n+          }\n+          bufLimit = src;\n+        }\n+        else\n+          bufLimit = src + inSize - LZMA_REQUIRED_INPUT_MAX;\n+        p->buf = src;\n+        if (LzmaDec_DecodeReal2(p, dicLimit, bufLimit) != 0)\n+          return SZ_ERROR_DATA;\n+        processed = p->buf - src;\n+        (*srcLen) += processed;\n+        src += processed;\n+        inSize -= processed;\n+      }\n+      else\n+      {\n+        unsigned rem = p->tempBufSize, lookAhead = 0;\n+        while (rem < LZMA_REQUIRED_INPUT_MAX && lookAhead < inSize)\n+          p->tempBuf[rem++] = src[lookAhead++];\n+        p->tempBufSize = rem;\n+        if (rem < LZMA_REQUIRED_INPUT_MAX || checkEndMarkNow)\n+        {\n+          int dummyRes = LzmaDec_TryDummy(p, p->tempBuf, rem);\n+          if (dummyRes == DUMMY_ERROR)\n+          {\n+            (*srcLen) += lookAhead;\n+            *status = LZMA_STATUS_NEEDS_MORE_INPUT;\n+            return SZ_OK;\n+          }\n+          if (checkEndMarkNow && dummyRes != DUMMY_MATCH)\n+          {\n+            *status = LZMA_STATUS_NOT_FINISHED;\n+            return SZ_ERROR_DATA;\n+          }\n+        }\n+        p->buf = p->tempBuf;\n+        if (LzmaDec_DecodeReal2(p, dicLimit, p->buf) != 0)\n+          return SZ_ERROR_DATA;\n+        lookAhead -= (rem - (unsigned)(p->buf - p->tempBuf));\n+        (*srcLen) += lookAhead;\n+        src += lookAhead;\n+        inSize -= lookAhead;\n+        p->tempBufSize = 0;\n+      }\n+  }\n+  if (p->code == 0) \n+    *status = LZMA_STATUS_FINISHED_WITH_MARK;\n+  return (p->code == 0) ? SZ_OK : SZ_ERROR_DATA;\n+}\n+\n+SRes LzmaDec_DecodeToBuf(CLzmaDec *p, Byte *dest, SizeT *destLen, const Byte *src, SizeT *srcLen, ELzmaFinishMode finishMode, ELzmaStatus *status)\n+{\n+  SizeT outSize = *destLen;\n+  SizeT inSize = *srcLen;\n+  *srcLen = *destLen = 0;\n+  for (;;)\n+  {\n+    SizeT inSizeCur = inSize, outSizeCur, dicPos;\n+    ELzmaFinishMode curFinishMode;\n+    SRes res;\n+    if (p->dicPos == p->dicBufSize)\n+      p->dicPos = 0;\n+    dicPos = p->dicPos;\n+    if (outSize > p->dicBufSize - dicPos)\n+    {\n+      outSizeCur = p->dicBufSize;\n+      curFinishMode = LZMA_FINISH_ANY;\n+    }\n+    else\n+    {\n+      outSizeCur = dicPos + outSize;\n+      curFinishMode = finishMode;\n+    }\n+\n+    res = LzmaDec_DecodeToDic(p, outSizeCur, src, &inSizeCur, curFinishMode, status);\n+    src += inSizeCur;\n+    inSize -= inSizeCur;\n+    *srcLen += inSizeCur;\n+    outSizeCur = p->dicPos - dicPos;\n+    memcpy(dest, p->dic + dicPos, outSizeCur);\n+    dest += outSizeCur;\n+    outSize -= outSizeCur;\n+    *destLen += outSizeCur;\n+    if (res != 0)\n+      return res;\n+    if (outSizeCur == 0 || outSize == 0)\n+      return SZ_OK;\n+  }\n+}\n+\n+void LzmaDec_FreeProbs(CLzmaDec *p, ISzAlloc *alloc) \n+{ \n+  alloc->Free(alloc, p->probs);  \n+  p->probs = 0; \n+}\n+\n+static void LzmaDec_FreeDict(CLzmaDec *p, ISzAlloc *alloc) \n+{ \n+  alloc->Free(alloc, p->dic); \n+  p->dic = 0; \n+}\n+\n+void LzmaDec_Free(CLzmaDec *p, ISzAlloc *alloc)\n+{\n+  LzmaDec_FreeProbs(p, alloc);\n+  LzmaDec_FreeDict(p, alloc);\n+}\n+\n+SRes LzmaProps_Decode(CLzmaProps *p, const Byte *data, unsigned size)\n+{\n+  UInt32 dicSize; \n+  Byte d;\n+  \n+  if (size < LZMA_PROPS_SIZE)\n+    return SZ_ERROR_UNSUPPORTED;\n+  else\n+    dicSize = data[1] | ((UInt32)data[2] << 8) | ((UInt32)data[3] << 16) | ((UInt32)data[4] << 24);\n+ \n+  if (dicSize < LZMA_DIC_MIN)\n+    dicSize = LZMA_DIC_MIN;\n+  p->dicSize = dicSize;\n+\n+  d = data[0];\n+  if (d >= (9 * 5 * 5))\n+    return SZ_ERROR_UNSUPPORTED;\n+\n+  p->lc = d % 9;\n+  d /= 9;\n+  p->pb = d / 5;\n+  p->lp = d % 5;\n+\n+  return SZ_OK;\n+}\n+\n+static SRes LzmaDec_AllocateProbs2(CLzmaDec *p, const CLzmaProps *propNew, ISzAlloc *alloc)\n+{\n+  UInt32 numProbs = LzmaProps_GetNumProbs(propNew);\n+  if (p->probs == 0 || numProbs != p->numProbs)\n+  {\n+    LzmaDec_FreeProbs(p, alloc);\n+    p->probs = (CLzmaProb *)alloc->Alloc(alloc, numProbs * sizeof(CLzmaProb));\n+    p->numProbs = numProbs;\n+    if (p->probs == 0)\n+      return SZ_ERROR_MEM;\n+  }\n+  return SZ_OK;\n+}\n+\n+SRes LzmaDec_AllocateProbs(CLzmaDec *p, const Byte *props, unsigned propsSize, ISzAlloc *alloc)\n+{\n+  CLzmaProps propNew;\n+  RINOK(LzmaProps_Decode(&propNew, props, propsSize));\n+  RINOK(LzmaDec_AllocateProbs2(p, &propNew, alloc));\n+  p->prop = propNew;\n+  return SZ_OK;\n+}\n+\n+SRes LzmaDec_Allocate(CLzmaDec *p, const Byte *props, unsigned propsSize, ISzAlloc *alloc)\n+{\n+  CLzmaProps propNew;\n+  SizeT dicBufSize;\n+  RINOK(LzmaProps_Decode(&propNew, props, propsSize));\n+  RINOK(LzmaDec_AllocateProbs2(p, &propNew, alloc));\n+  dicBufSize = propNew.dicSize;\n+  if (p->dic == 0 || dicBufSize != p->dicBufSize)\n+  {\n+    LzmaDec_FreeDict(p, alloc);\n+    p->dic = (Byte *)alloc->Alloc(alloc, dicBufSize);\n+    if (p->dic == 0)\n+    {\n+      LzmaDec_FreeProbs(p, alloc);\n+      return SZ_ERROR_MEM;\n+    }\n+  }\n+  p->dicBufSize = dicBufSize;\n+  p->prop = propNew;\n+  return SZ_OK;\n+}\n+\n+SRes LzmaDecode(Byte *dest, SizeT *destLen, const Byte *src, SizeT *srcLen,\n+    const Byte *propData, unsigned propSize, ELzmaFinishMode finishMode, \n+    ELzmaStatus *status, ISzAlloc *alloc)\n+{\n+  CLzmaDec p;\n+  SRes res;\n+  SizeT inSize = *srcLen;\n+  SizeT outSize = *destLen;\n+  *srcLen = *destLen = 0;\n+  if (inSize < RC_INIT_SIZE)\n+    return SZ_ERROR_INPUT_EOF;\n+\n+  LzmaDec_Construct(&p);\n+  res = LzmaDec_AllocateProbs(&p, propData, propSize, alloc);\n+  if (res != 0)\n+    return res;\n+  p.dic = dest;\n+  p.dicBufSize = outSize;\n+\n+  LzmaDec_Init(&p);\n+  \n+  *srcLen = inSize;\n+  res = LzmaDec_DecodeToDic(&p, outSize, src, srcLen, finishMode, status);\n+\n+  if (res == SZ_OK && *status == LZMA_STATUS_NEEDS_MORE_INPUT)\n+    res = SZ_ERROR_INPUT_EOF;\n+\n+  (*destLen) = p.dicPos;\n+  LzmaDec_FreeProbs(&p, alloc);\n+  return res;\n+}\n--- /dev/null\n+++ b/jffsX-utils/lzma/LzmaEnc.c\n@@ -0,0 +1,2335 @@\n+/* LzmaEnc.c -- LZMA Encoder\n+2008-04-28\n+Copyright (c) 1999-2008 Igor Pavlov\n+Read LzmaEnc.h for license options */\n+\n+#if defined(SHOW_STAT) || defined(SHOW_STAT2)\n+#include <stdio.h>\n+#endif\n+\n+#include <string.h>\n+\n+#include \"LzmaEnc.h\"\n+\n+#include \"LzFind.h\"\n+#ifdef COMPRESS_MF_MT\n+#include \"LzFindMt.h\"\n+#endif\n+\n+/* #define SHOW_STAT */\n+/* #define SHOW_STAT2 */\n+\n+#ifdef SHOW_STAT\n+static int ttt = 0;\n+#endif\n+\n+#define kBlockSizeMax ((1 << LZMA_NUM_BLOCK_SIZE_BITS) - 1)\n+\n+#define kBlockSize (9 << 10)\n+#define kUnpackBlockSize (1 << 18)\n+#define kMatchArraySize (1 << 21)\n+#define kMatchRecordMaxSize ((LZMA_MATCH_LEN_MAX * 2 + 3) * LZMA_MATCH_LEN_MAX)\n+\n+#define kNumMaxDirectBits (31)\n+\n+#define kNumTopBits 24\n+#define kTopValue ((UInt32)1 << kNumTopBits)\n+\n+#define kNumBitModelTotalBits 11\n+#define kBitModelTotal (1 << kNumBitModelTotalBits)\n+#define kNumMoveBits 5\n+#define kProbInitValue (kBitModelTotal >> 1)\n+\n+#define kNumMoveReducingBits 4\n+#define kNumBitPriceShiftBits 4\n+#define kBitPrice (1 << kNumBitPriceShiftBits)\n+\n+void LzmaEncProps_Init(CLzmaEncProps *p)\n+{\n+  p->level = 5;\n+  p->dictSize = p->mc = 0;\n+  p->lc = p->lp = p->pb = p->algo = p->fb = p->btMode = p->numHashBytes = p->numThreads = -1;\n+  p->writeEndMark = 0;\n+}\n+\n+void LzmaEncProps_Normalize(CLzmaEncProps *p)\n+{\n+  int level = p->level;\n+  if (level < 0) level = 5;\n+  p->level = level;\n+  if (p->dictSize == 0) p->dictSize = (level <= 5 ? (1 << (level * 2 + 14)) : (level == 6 ? (1 << 25) : (1 << 26)));\n+  if (p->lc < 0) p->lc = 3; \n+  if (p->lp < 0) p->lp = 0; \n+  if (p->pb < 0) p->pb = 2; \n+  if (p->algo < 0) p->algo = (level < 5 ? 0 : 1); \n+  if (p->fb < 0) p->fb = (level < 7 ? 32 : 64); \n+  if (p->btMode < 0) p->btMode = (p->algo == 0 ? 0 : 1); \n+  if (p->numHashBytes < 0) p->numHashBytes = 4; \n+  if (p->mc == 0)  p->mc = (16 + (p->fb >> 1)) >> (p->btMode ? 0 : 1);\n+  if (p->numThreads < 0) p->numThreads = ((p->btMode && p->algo) ? 2 : 1);\n+}\n+\n+UInt32 LzmaEncProps_GetDictSize(const CLzmaEncProps *props2)\n+{\n+  CLzmaEncProps props = *props2;\n+  LzmaEncProps_Normalize(&props);\n+  return props.dictSize;\n+}\n+\n+/* #define LZMA_LOG_BSR */\n+/* Define it for Intel's CPU */\n+\n+\n+#ifdef LZMA_LOG_BSR\n+\n+#define kDicLogSizeMaxCompress 30\n+\n+#define BSR2_RET(pos, res) { unsigned long i; _BitScanReverse(&i, (pos)); res = (i + i) + ((pos >> (i - 1)) & 1); }\n+\n+UInt32 GetPosSlot1(UInt32 pos) \n+{ \n+  UInt32 res; \n+  BSR2_RET(pos, res); \n+  return res; \n+}\n+#define GetPosSlot2(pos, res) { BSR2_RET(pos, res); }\n+#define GetPosSlot(pos, res) { if (pos < 2) res = pos; else BSR2_RET(pos, res); }\n+\n+#else\n+\n+#define kNumLogBits (9 + (int)sizeof(size_t) / 2)\n+#define kDicLogSizeMaxCompress ((kNumLogBits - 1) * 2 + 7)\n+\n+static void LzmaEnc_FastPosInit(Byte *g_FastPos)\n+{\n+  int c = 2, slotFast;\n+  g_FastPos[0] = 0;\n+  g_FastPos[1] = 1;\n+  \n+  for (slotFast = 2; slotFast < kNumLogBits * 2; slotFast++)\n+  {\n+    UInt32 k = (1 << ((slotFast >> 1) - 1));\n+    UInt32 j;\n+    for (j = 0; j < k; j++, c++)\n+      g_FastPos[c] = (Byte)slotFast;\n+  }\n+}\n+\n+#define BSR2_RET(pos, res) { UInt32 i = 6 + ((kNumLogBits - 1) & \\\n+  (0 - (((((UInt32)1 << (kNumLogBits + 6)) - 1) - pos) >> 31))); \\\n+  res = p->g_FastPos[pos >> i] + (i * 2); }\n+/*\n+#define BSR2_RET(pos, res) { res = (pos < (1 << (kNumLogBits + 6))) ? \\\n+  p->g_FastPos[pos >> 6] + 12 : \\\n+  p->g_FastPos[pos >> (6 + kNumLogBits - 1)] + (6 + (kNumLogBits - 1)) * 2; }\n+*/\n+\n+#define GetPosSlot1(pos) p->g_FastPos[pos]\n+#define GetPosSlot2(pos, res) { BSR2_RET(pos, res); }\n+#define GetPosSlot(pos, res) { if (pos < kNumFullDistances) res = p->g_FastPos[pos]; else BSR2_RET(pos, res); }\n+\n+#endif\n+\n+\n+#define LZMA_NUM_REPS 4\n+\n+typedef unsigned CState;\n+\n+typedef struct _COptimal\n+{\n+  UInt32 price;    \n+\n+  CState state;\n+  int prev1IsChar;\n+  int prev2;\n+\n+  UInt32 posPrev2;\n+  UInt32 backPrev2;     \n+\n+  UInt32 posPrev;\n+  UInt32 backPrev;     \n+  UInt32 backs[LZMA_NUM_REPS];\n+} COptimal;\n+\n+#define kNumOpts (1 << 12)\n+\n+#define kNumLenToPosStates 4\n+#define kNumPosSlotBits 6 \n+#define kDicLogSizeMin 0 \n+#define kDicLogSizeMax 32 \n+#define kDistTableSizeMax (kDicLogSizeMax * 2)\n+\n+\n+#define kNumAlignBits 4\n+#define kAlignTableSize (1 << kNumAlignBits)\n+#define kAlignMask (kAlignTableSize - 1)\n+\n+#define kStartPosModelIndex 4\n+#define kEndPosModelIndex 14\n+#define kNumPosModels (kEndPosModelIndex - kStartPosModelIndex)\n+\n+#define kNumFullDistances (1 << (kEndPosModelIndex / 2))\n+\n+#ifdef _LZMA_PROB32\n+#define CLzmaProb UInt32\n+#else\n+#define CLzmaProb UInt16\n+#endif\n+\n+#define LZMA_PB_MAX 4\n+#define LZMA_LC_MAX 8\n+#define LZMA_LP_MAX 4\n+\n+#define LZMA_NUM_PB_STATES_MAX (1 << LZMA_PB_MAX)\n+\n+\n+#define kLenNumLowBits 3\n+#define kLenNumLowSymbols (1 << kLenNumLowBits)\n+#define kLenNumMidBits 3\n+#define kLenNumMidSymbols (1 << kLenNumMidBits)\n+#define kLenNumHighBits 8\n+#define kLenNumHighSymbols (1 << kLenNumHighBits)\n+\n+#define kLenNumSymbolsTotal (kLenNumLowSymbols + kLenNumMidSymbols + kLenNumHighSymbols)\n+\n+#define LZMA_MATCH_LEN_MIN 2\n+#define LZMA_MATCH_LEN_MAX (LZMA_MATCH_LEN_MIN + kLenNumSymbolsTotal - 1)\n+\n+#define kNumStates 12\n+\n+typedef struct\n+{\n+  CLzmaProb choice;\n+  CLzmaProb choice2;\n+  CLzmaProb low[LZMA_NUM_PB_STATES_MAX << kLenNumLowBits];\n+  CLzmaProb mid[LZMA_NUM_PB_STATES_MAX << kLenNumMidBits];\n+  CLzmaProb high[kLenNumHighSymbols];\n+} CLenEnc;\n+\n+typedef struct\n+{\n+  CLenEnc p;\n+  UInt32 prices[LZMA_NUM_PB_STATES_MAX][kLenNumSymbolsTotal];\n+  UInt32 tableSize;\n+  UInt32 counters[LZMA_NUM_PB_STATES_MAX];\n+} CLenPriceEnc;\n+\n+typedef struct _CRangeEnc\n+{\n+  UInt32 range;\n+  Byte cache;\n+  UInt64 low;\n+  UInt64 cacheSize;\n+  Byte *buf;\n+  Byte *bufLim;\n+  Byte *bufBase;\n+  ISeqOutStream *outStream;\n+  UInt64 processed;\n+  SRes res;\n+} CRangeEnc;\n+\n+typedef struct _CSeqInStreamBuf\n+{\n+  ISeqInStream funcTable;\n+  const Byte *data;\n+  SizeT rem;\n+} CSeqInStreamBuf;\n+\n+static SRes MyRead(void *pp, void *data, size_t *size)\n+{\n+  size_t curSize = *size;\n+  CSeqInStreamBuf *p = (CSeqInStreamBuf *)pp;\n+  if (p->rem < curSize)\n+    curSize = p->rem;\n+  memcpy(data, p->data, curSize);\n+  p->rem -= curSize;\n+  p->data += curSize;\n+  *size = curSize;\n+  return SZ_OK;\n+}\n+\n+typedef struct \n+{\n+  CLzmaProb *litProbs;\n+\n+  CLzmaProb isMatch[kNumStates][LZMA_NUM_PB_STATES_MAX];\n+  CLzmaProb isRep[kNumStates];\n+  CLzmaProb isRepG0[kNumStates];\n+  CLzmaProb isRepG1[kNumStates];\n+  CLzmaProb isRepG2[kNumStates];\n+  CLzmaProb isRep0Long[kNumStates][LZMA_NUM_PB_STATES_MAX];\n+\n+  CLzmaProb posSlotEncoder[kNumLenToPosStates][1 << kNumPosSlotBits];\n+  CLzmaProb posEncoders[kNumFullDistances - kEndPosModelIndex];\n+  CLzmaProb posAlignEncoder[1 << kNumAlignBits];\n+  \n+  CLenPriceEnc lenEnc;\n+  CLenPriceEnc repLenEnc;\n+\n+  UInt32 reps[LZMA_NUM_REPS];\n+  UInt32 state;\n+} CSaveState;\n+\n+typedef struct _CLzmaEnc\n+{\n+  IMatchFinder matchFinder;\n+  void *matchFinderObj;\n+\n+  #ifdef COMPRESS_MF_MT\n+  Bool mtMode;\n+  CMatchFinderMt matchFinderMt;\n+  #endif\n+\n+  CMatchFinder matchFinderBase;\n+\n+  #ifdef COMPRESS_MF_MT\n+  Byte pad[128];\n+  #endif\n+  \n+  UInt32 optimumEndIndex;\n+  UInt32 optimumCurrentIndex;\n+\n+  Bool longestMatchWasFound;\n+  UInt32 longestMatchLength;    \n+  UInt32 numDistancePairs;\n+\n+  COptimal opt[kNumOpts];\n+  \n+  #ifndef LZMA_LOG_BSR\n+  Byte g_FastPos[1 << kNumLogBits];\n+  #endif\n+\n+  UInt32 ProbPrices[kBitModelTotal >> kNumMoveReducingBits];\n+  UInt32 matchDistances[LZMA_MATCH_LEN_MAX * 2 + 2 + 1];\n+  UInt32 numFastBytes;\n+  UInt32 additionalOffset;\n+  UInt32 reps[LZMA_NUM_REPS];\n+  UInt32 state;\n+\n+  UInt32 posSlotPrices[kNumLenToPosStates][kDistTableSizeMax];\n+  UInt32 distancesPrices[kNumLenToPosStates][kNumFullDistances];\n+  UInt32 alignPrices[kAlignTableSize];\n+  UInt32 alignPriceCount;\n+\n+  UInt32 distTableSize;\n+\n+  unsigned lc, lp, pb;\n+  unsigned lpMask, pbMask;\n+\n+  CLzmaProb *litProbs;\n+\n+  CLzmaProb isMatch[kNumStates][LZMA_NUM_PB_STATES_MAX];\n+  CLzmaProb isRep[kNumStates];\n+  CLzmaProb isRepG0[kNumStates];\n+  CLzmaProb isRepG1[kNumStates];\n+  CLzmaProb isRepG2[kNumStates];\n+  CLzmaProb isRep0Long[kNumStates][LZMA_NUM_PB_STATES_MAX];\n+\n+  CLzmaProb posSlotEncoder[kNumLenToPosStates][1 << kNumPosSlotBits];\n+  CLzmaProb posEncoders[kNumFullDistances - kEndPosModelIndex];\n+  CLzmaProb posAlignEncoder[1 << kNumAlignBits];\n+  \n+  CLenPriceEnc lenEnc;\n+  CLenPriceEnc repLenEnc;\n+\n+  unsigned lclp;\n+\n+  Bool fastMode;\n+  \n+  CRangeEnc rc;\n+\n+  Bool writeEndMark;\n+  UInt64 nowPos64;\n+  UInt32 matchPriceCount;\n+  Bool finished;\n+  Bool multiThread;\n+\n+  SRes result;\n+  UInt32 dictSize;\n+  UInt32 matchFinderCycles;\n+\n+  ISeqInStream *inStream;\n+  CSeqInStreamBuf seqBufInStream;\n+\n+  CSaveState saveState;\n+} CLzmaEnc;\n+\n+static void LzmaEnc_SaveState(CLzmaEncHandle pp)\n+{\n+  CLzmaEnc *p = (CLzmaEnc *)pp;\n+  CSaveState *dest = &p->saveState;\n+  int i;\n+  dest->lenEnc = p->lenEnc;\n+  dest->repLenEnc = p->repLenEnc;\n+  dest->state = p->state;\n+\n+  for (i = 0; i < kNumStates; i++)\n+  {\n+    memcpy(dest->isMatch[i], p->isMatch[i], sizeof(p->isMatch[i]));\n+    memcpy(dest->isRep0Long[i], p->isRep0Long[i], sizeof(p->isRep0Long[i]));\n+  }\n+  for (i = 0; i < kNumLenToPosStates; i++)\n+    memcpy(dest->posSlotEncoder[i], p->posSlotEncoder[i], sizeof(p->posSlotEncoder[i]));\n+  memcpy(dest->isRep, p->isRep, sizeof(p->isRep));\n+  memcpy(dest->isRepG0, p->isRepG0, sizeof(p->isRepG0));\n+  memcpy(dest->isRepG1, p->isRepG1, sizeof(p->isRepG1));\n+  memcpy(dest->isRepG2, p->isRepG2, sizeof(p->isRepG2));\n+  memcpy(dest->posEncoders, p->posEncoders, sizeof(p->posEncoders));\n+  memcpy(dest->posAlignEncoder, p->posAlignEncoder, sizeof(p->posAlignEncoder));\n+  memcpy(dest->reps, p->reps, sizeof(p->reps));\n+  memcpy(dest->litProbs, p->litProbs, (0x300 << p->lclp) * sizeof(CLzmaProb));\n+}\n+\n+static void LzmaEnc_RestoreState(CLzmaEncHandle pp)\n+{\n+  CLzmaEnc *dest = (CLzmaEnc *)pp;\n+  const CSaveState *p = &dest->saveState;\n+  int i;\n+  dest->lenEnc = p->lenEnc;\n+  dest->repLenEnc = p->repLenEnc;\n+  dest->state = p->state;\n+\n+  for (i = 0; i < kNumStates; i++)\n+  {\n+    memcpy(dest->isMatch[i], p->isMatch[i], sizeof(p->isMatch[i]));\n+    memcpy(dest->isRep0Long[i], p->isRep0Long[i], sizeof(p->isRep0Long[i]));\n+  }\n+  for (i = 0; i < kNumLenToPosStates; i++)\n+    memcpy(dest->posSlotEncoder[i], p->posSlotEncoder[i], sizeof(p->posSlotEncoder[i]));\n+  memcpy(dest->isRep, p->isRep, sizeof(p->isRep));\n+  memcpy(dest->isRepG0, p->isRepG0, sizeof(p->isRepG0));\n+  memcpy(dest->isRepG1, p->isRepG1, sizeof(p->isRepG1));\n+  memcpy(dest->isRepG2, p->isRepG2, sizeof(p->isRepG2));\n+  memcpy(dest->posEncoders, p->posEncoders, sizeof(p->posEncoders));\n+  memcpy(dest->posAlignEncoder, p->posAlignEncoder, sizeof(p->posAlignEncoder));\n+  memcpy(dest->reps, p->reps, sizeof(p->reps));\n+  memcpy(dest->litProbs, p->litProbs, (0x300 << dest->lclp) * sizeof(CLzmaProb));\n+}\n+\n+SRes LzmaEnc_SetProps(CLzmaEncHandle pp, const CLzmaEncProps *props2)\n+{\n+  CLzmaEnc *p = (CLzmaEnc *)pp;\n+  CLzmaEncProps props = *props2;\n+  LzmaEncProps_Normalize(&props);\n+\n+  if (props.lc > LZMA_LC_MAX || props.lp > LZMA_LP_MAX || props.pb > LZMA_PB_MAX ||\n+      props.dictSize > (1 << kDicLogSizeMaxCompress) || props.dictSize > (1 << 30))\n+    return SZ_ERROR_PARAM;\n+  p->dictSize = props.dictSize;\n+  p->matchFinderCycles = props.mc;\n+  {\n+    unsigned fb = props.fb;\n+    if (fb < 5)\n+      fb = 5;\n+    if (fb > LZMA_MATCH_LEN_MAX)\n+      fb = LZMA_MATCH_LEN_MAX;\n+    p->numFastBytes = fb;\n+  }\n+  p->lc = props.lc;\n+  p->lp = props.lp;\n+  p->pb = props.pb;\n+  p->fastMode = (props.algo == 0);\n+  p->matchFinderBase.btMode = props.btMode;\n+  {\n+    UInt32 numHashBytes = 4;\n+    if (props.btMode)\n+    {\n+      if (props.numHashBytes < 2)\n+        numHashBytes = 2;\n+      else if (props.numHashBytes < 4)\n+        numHashBytes = props.numHashBytes;\n+    }\n+    p->matchFinderBase.numHashBytes = numHashBytes;\n+  }\n+\n+  p->matchFinderBase.cutValue = props.mc;\n+\n+  p->writeEndMark = props.writeEndMark;\n+\n+  #ifdef COMPRESS_MF_MT\n+  /*\n+  if (newMultiThread != _multiThread)\n+  {\n+    ReleaseMatchFinder();\n+    _multiThread = newMultiThread;\n+  }\n+  */\n+  p->multiThread = (props.numThreads > 1);\n+  #endif\n+\n+  return SZ_OK;\n+}\n+\n+static const int kLiteralNextStates[kNumStates] = {0, 0, 0, 0, 1, 2, 3, 4,  5,  6,   4, 5};\n+static const int kMatchNextStates[kNumStates]   = {7, 7, 7, 7, 7, 7, 7, 10, 10, 10, 10, 10};\n+static const int kRepNextStates[kNumStates]     = {8, 8, 8, 8, 8, 8, 8, 11, 11, 11, 11, 11};\n+static const int kShortRepNextStates[kNumStates]= {9, 9, 9, 9, 9, 9, 9, 11, 11, 11, 11, 11};\n+\n+/*\n+  void UpdateChar() { Index = kLiteralNextStates[Index]; }\n+  void UpdateMatch() { Index = kMatchNextStates[Index]; }\n+  void UpdateRep() { Index = kRepNextStates[Index]; }\n+  void UpdateShortRep() { Index = kShortRepNextStates[Index]; }\n+*/\n+\n+#define IsCharState(s) ((s) < 7)\n+\n+\n+#define GetLenToPosState(len) (((len) < kNumLenToPosStates + 1) ? (len) - 2 : kNumLenToPosStates - 1)\n+\n+#define kInfinityPrice (1 << 30)\n+\n+static void RangeEnc_Construct(CRangeEnc *p)\n+{\n+  p->outStream = 0;\n+  p->bufBase = 0;\n+}\n+\n+#define RangeEnc_GetProcessed(p) ((p)->processed + ((p)->buf - (p)->bufBase) + (p)->cacheSize)\n+\n+#define RC_BUF_SIZE (1 << 16)\n+static int RangeEnc_Alloc(CRangeEnc *p, ISzAlloc *alloc)\n+{\n+  if (p->bufBase == 0)\n+  {\n+    p->bufBase = (Byte *)alloc->Alloc(alloc, RC_BUF_SIZE);\n+    if (p->bufBase == 0)\n+      return 0;\n+    p->bufLim = p->bufBase + RC_BUF_SIZE;\n+  }\n+  return 1;\n+}\n+\n+static void RangeEnc_Free(CRangeEnc *p, ISzAlloc *alloc)\n+{\n+  alloc->Free(alloc, p->bufBase);\n+  p->bufBase = 0;\n+}\n+\n+static void RangeEnc_Init(CRangeEnc *p)\n+{\n+  /* Stream.Init(); */\n+  p->low = 0;\n+  p->range = 0xFFFFFFFF;\n+  p->cacheSize = 1;\n+  p->cache = 0;\n+\n+  p->buf = p->bufBase;\n+\n+  p->processed = 0;\n+  p->res = SZ_OK;\n+}\n+\n+static void RangeEnc_FlushStream(CRangeEnc *p)\n+{\n+  size_t num;\n+  if (p->res != SZ_OK)\n+    return;\n+  num = p->buf - p->bufBase;\n+  if (num != p->outStream->Write(p->outStream, p->bufBase, num))\n+    p->res = SZ_ERROR_WRITE;\n+  p->processed += num;\n+  p->buf = p->bufBase;\n+}\n+\n+static void MY_FAST_CALL RangeEnc_ShiftLow(CRangeEnc *p)\n+{\n+  if ((UInt32)p->low < (UInt32)0xFF000000 || (int)(p->low >> 32) != 0) \n+  {\n+    Byte temp = p->cache;\n+    do\n+    {\n+      Byte *buf = p->buf;\n+      *buf++ = (Byte)(temp + (Byte)(p->low >> 32));\n+      p->buf = buf;\n+      if (buf == p->bufLim)\n+        RangeEnc_FlushStream(p);\n+      temp = 0xFF;\n+    }\n+    while (--p->cacheSize != 0);\n+    p->cache = (Byte)((UInt32)p->low >> 24);                      \n+  } \n+  p->cacheSize++;                               \n+  p->low = (UInt32)p->low << 8;                           \n+}\n+\n+static void RangeEnc_FlushData(CRangeEnc *p)\n+{\n+  int i;\n+  for (i = 0; i < 5; i++)\n+    RangeEnc_ShiftLow(p);\n+}\n+\n+static void RangeEnc_EncodeDirectBits(CRangeEnc *p, UInt32 value, int numBits)\n+{\n+  do\n+  {\n+    p->range >>= 1;\n+    p->low += p->range & (0 - ((value >> --numBits) & 1));\n+    if (p->range < kTopValue)\n+    {\n+      p->range <<= 8;\n+      RangeEnc_ShiftLow(p);\n+    }\n+  }\n+  while (numBits != 0);\n+}\n+\n+static void RangeEnc_EncodeBit(CRangeEnc *p, CLzmaProb *prob, UInt32 symbol)\n+{\n+  UInt32 ttt = *prob;\n+  UInt32 newBound = (p->range >> kNumBitModelTotalBits) * ttt;\n+  if (symbol == 0)\n+  {\n+    p->range = newBound;\n+    ttt += (kBitModelTotal - ttt) >> kNumMoveBits;\n+  }\n+  else\n+  {\n+    p->low += newBound;\n+    p->range -= newBound;\n+    ttt -= ttt >> kNumMoveBits;\n+  }\n+  *prob = (CLzmaProb)ttt;\n+  if (p->range < kTopValue)\n+  {\n+    p->range <<= 8;\n+    RangeEnc_ShiftLow(p);\n+  }\n+}\n+\n+static void LitEnc_Encode(CRangeEnc *p, CLzmaProb *probs, UInt32 symbol)\n+{\n+  symbol |= 0x100;\n+  do \n+  {\n+    RangeEnc_EncodeBit(p, probs + (symbol >> 8), (symbol >> 7) & 1);\n+    symbol <<= 1;\n+  }\n+  while (symbol < 0x10000);\n+}\n+\n+static void LitEnc_EncodeMatched(CRangeEnc *p, CLzmaProb *probs, UInt32 symbol, UInt32 matchByte)\n+{\n+  UInt32 offs = 0x100;\n+  symbol |= 0x100;\n+  do \n+  {\n+    matchByte <<= 1;\n+    RangeEnc_EncodeBit(p, probs + (offs + (matchByte & offs) + (symbol >> 8)), (symbol >> 7) & 1);\n+    symbol <<= 1;\n+    offs &= ~(matchByte ^ symbol);\n+  }\n+  while (symbol < 0x10000);\n+}\n+\n+static void LzmaEnc_InitPriceTables(UInt32 *ProbPrices)\n+{\n+  UInt32 i;\n+  for (i = (1 << kNumMoveReducingBits) / 2; i < kBitModelTotal; i += (1 << kNumMoveReducingBits))\n+  {\n+    const int kCyclesBits = kNumBitPriceShiftBits;\n+    UInt32 w = i;\n+    UInt32 bitCount = 0;\n+    int j;\n+    for (j = 0; j < kCyclesBits; j++)\n+    {\n+      w = w * w;\n+      bitCount <<= 1;\n+      while (w >= ((UInt32)1 << 16))\n+      {\n+        w >>= 1;\n+        bitCount++;\n+      }\n+    }\n+    ProbPrices[i >> kNumMoveReducingBits] = ((kNumBitModelTotalBits << kCyclesBits) - 15 - bitCount);\n+  }\n+}\n+\n+\n+#define GET_PRICE(prob, symbol) \\\n+  p->ProbPrices[((prob) ^ (((-(int)(symbol))) & (kBitModelTotal - 1))) >> kNumMoveReducingBits];\n+\n+#define GET_PRICEa(prob, symbol) \\\n+  ProbPrices[((prob) ^ ((-((int)(symbol))) & (kBitModelTotal - 1))) >> kNumMoveReducingBits];\n+\n+#define GET_PRICE_0(prob) p->ProbPrices[(prob) >> kNumMoveReducingBits]\n+#define GET_PRICE_1(prob) p->ProbPrices[((prob) ^ (kBitModelTotal - 1)) >> kNumMoveReducingBits]\n+\n+#define GET_PRICE_0a(prob) ProbPrices[(prob) >> kNumMoveReducingBits]\n+#define GET_PRICE_1a(prob) ProbPrices[((prob) ^ (kBitModelTotal - 1)) >> kNumMoveReducingBits]\n+\n+static UInt32 LitEnc_GetPrice(const CLzmaProb *probs, UInt32 symbol, UInt32 *ProbPrices)\n+{\n+  UInt32 price = 0;\n+  symbol |= 0x100;\n+  do\n+  {\n+    price += GET_PRICEa(probs[symbol >> 8], (symbol >> 7) & 1);\n+    symbol <<= 1;\n+  }\n+  while (symbol < 0x10000);\n+  return price;\n+};\n+\n+static UInt32 LitEnc_GetPriceMatched(const CLzmaProb *probs, UInt32 symbol, UInt32 matchByte, UInt32 *ProbPrices)\n+{\n+  UInt32 price = 0;\n+  UInt32 offs = 0x100;\n+  symbol |= 0x100;\n+  do \n+  {\n+    matchByte <<= 1;\n+    price += GET_PRICEa(probs[offs + (matchByte & offs) + (symbol >> 8)], (symbol >> 7) & 1);\n+    symbol <<= 1;\n+    offs &= ~(matchByte ^ symbol);\n+  }\n+  while (symbol < 0x10000);\n+  return price;\n+};\n+\n+\n+static void RcTree_Encode(CRangeEnc *rc, CLzmaProb *probs, int numBitLevels, UInt32 symbol)\n+{\n+  UInt32 m = 1;\n+  int i;\n+  for (i = numBitLevels; i != 0 ;)\n+  {\n+    UInt32 bit;\n+    i--;\n+    bit = (symbol >> i) & 1;\n+    RangeEnc_EncodeBit(rc, probs + m, bit);\n+    m = (m << 1) | bit;\n+  }\n+};\n+\n+static void RcTree_ReverseEncode(CRangeEnc *rc, CLzmaProb *probs, int numBitLevels, UInt32 symbol)\n+{\n+  UInt32 m = 1;\n+  int i;\n+  for (i = 0; i < numBitLevels; i++)\n+  {\n+    UInt32 bit = symbol & 1;\n+    RangeEnc_EncodeBit(rc, probs + m, bit);\n+    m = (m << 1) | bit;\n+    symbol >>= 1;\n+  }\n+}\n+\n+static UInt32 RcTree_GetPrice(const CLzmaProb *probs, int numBitLevels, UInt32 symbol, UInt32 *ProbPrices)\n+{\n+  UInt32 price = 0;\n+  symbol |= (1 << numBitLevels);\n+  while (symbol != 1)\n+  {\n+    price += GET_PRICEa(probs[symbol >> 1], symbol & 1);\n+    symbol >>= 1;\n+  }\n+  return price;\n+}\n+\n+static UInt32 RcTree_ReverseGetPrice(const CLzmaProb *probs, int numBitLevels, UInt32 symbol, UInt32 *ProbPrices)\n+{\n+  UInt32 price = 0;\n+  UInt32 m = 1;\n+  int i;\n+  for (i = numBitLevels; i != 0; i--)\n+  {\n+    UInt32 bit = symbol & 1;\n+    symbol >>= 1;\n+    price += GET_PRICEa(probs[m], bit);\n+    m = (m << 1) | bit;\n+  }\n+  return price;\n+}\n+\n+\n+static void LenEnc_Init(CLenEnc *p)\n+{\n+  unsigned i;\n+  p->choice = p->choice2 = kProbInitValue;\n+  for (i = 0; i < (LZMA_NUM_PB_STATES_MAX << kLenNumLowBits); i++)\n+    p->low[i] = kProbInitValue;\n+  for (i = 0; i < (LZMA_NUM_PB_STATES_MAX << kLenNumMidBits); i++)\n+    p->mid[i] = kProbInitValue;\n+  for (i = 0; i < kLenNumHighSymbols; i++)\n+    p->high[i] = kProbInitValue;\n+}\n+\n+static void LenEnc_Encode(CLenEnc *p, CRangeEnc *rc, UInt32 symbol, UInt32 posState)\n+{\n+  if (symbol < kLenNumLowSymbols)\n+  {\n+    RangeEnc_EncodeBit(rc, &p->choice, 0);\n+    RcTree_Encode(rc, p->low + (posState << kLenNumLowBits), kLenNumLowBits, symbol);\n+  }\n+  else\n+  {\n+    RangeEnc_EncodeBit(rc, &p->choice, 1);\n+    if (symbol < kLenNumLowSymbols + kLenNumMidSymbols)\n+    {\n+      RangeEnc_EncodeBit(rc, &p->choice2, 0);\n+      RcTree_Encode(rc, p->mid + (posState << kLenNumMidBits), kLenNumMidBits, symbol - kLenNumLowSymbols);\n+    }\n+    else\n+    {\n+      RangeEnc_EncodeBit(rc, &p->choice2, 1);\n+      RcTree_Encode(rc, p->high, kLenNumHighBits, symbol - kLenNumLowSymbols - kLenNumMidSymbols);\n+    }\n+  }\n+}\n+\n+static void LenEnc_SetPrices(CLenEnc *p, UInt32 posState, UInt32 numSymbols, UInt32 *prices, UInt32 *ProbPrices)\n+{\n+  UInt32 a0 = GET_PRICE_0a(p->choice);\n+  UInt32 a1 = GET_PRICE_1a(p->choice);\n+  UInt32 b0 = a1 + GET_PRICE_0a(p->choice2);\n+  UInt32 b1 = a1 + GET_PRICE_1a(p->choice2);\n+  UInt32 i = 0;\n+  for (i = 0; i < kLenNumLowSymbols; i++)\n+  {\n+    if (i >= numSymbols)\n+      return;\n+    prices[i] = a0 + RcTree_GetPrice(p->low + (posState << kLenNumLowBits), kLenNumLowBits, i, ProbPrices);\n+  }\n+  for (; i < kLenNumLowSymbols + kLenNumMidSymbols; i++)\n+  {\n+    if (i >= numSymbols)\n+      return;\n+    prices[i] = b0 + RcTree_GetPrice(p->mid + (posState << kLenNumMidBits), kLenNumMidBits, i - kLenNumLowSymbols, ProbPrices);\n+  }\n+  for (; i < numSymbols; i++)\n+    prices[i] = b1 + RcTree_GetPrice(p->high, kLenNumHighBits, i - kLenNumLowSymbols - kLenNumMidSymbols, ProbPrices);\n+}\n+\n+static void MY_FAST_CALL LenPriceEnc_UpdateTable(CLenPriceEnc *p, UInt32 posState, UInt32 *ProbPrices)\n+{\n+  LenEnc_SetPrices(&p->p, posState, p->tableSize, p->prices[posState], ProbPrices);\n+  p->counters[posState] = p->tableSize;\n+}\n+\n+static void LenPriceEnc_UpdateTables(CLenPriceEnc *p, UInt32 numPosStates, UInt32 *ProbPrices)\n+{\n+  UInt32 posState;\n+  for (posState = 0; posState < numPosStates; posState++)\n+    LenPriceEnc_UpdateTable(p, posState, ProbPrices);\n+}\n+\n+static void LenEnc_Encode2(CLenPriceEnc *p, CRangeEnc *rc, UInt32 symbol, UInt32 posState, Bool updatePrice, UInt32 *ProbPrices)\n+{\n+  LenEnc_Encode(&p->p, rc, symbol, posState);\n+  if (updatePrice)\n+    if (--p->counters[posState] == 0)\n+      LenPriceEnc_UpdateTable(p, posState, ProbPrices);\n+}\n+\n+\n+\n+\n+static void MovePos(CLzmaEnc *p, UInt32 num)\n+{\n+  #ifdef SHOW_STAT\n+  ttt += num;\n+  printf(\"\\n MovePos %d\", num);\n+  #endif\n+  if (num != 0)\n+  {\n+    p->additionalOffset += num;\n+    p->matchFinder.Skip(p->matchFinderObj, num);\n+  }\n+}\n+\n+static UInt32 ReadMatchDistances(CLzmaEnc *p, UInt32 *numDistancePairsRes)\n+{\n+  UInt32 lenRes = 0, numDistancePairs;\n+  numDistancePairs = p->matchFinder.GetMatches(p->matchFinderObj, p->matchDistances);\n+  #ifdef SHOW_STAT\n+  printf(\"\\n i = %d numPairs = %d    \", ttt, numDistancePairs / 2);\n+  if (ttt >= 61994)\n+    ttt = ttt;\n+\n+  ttt++;\n+  {\n+    UInt32 i;\n+  for (i = 0; i < numDistancePairs; i += 2)\n+    printf(\"%2d %6d   | \", p->matchDistances[i], p->matchDistances[i + 1]);\n+  }\n+  #endif\n+  if (numDistancePairs > 0)\n+  {\n+    lenRes = p->matchDistances[numDistancePairs - 2];\n+    if (lenRes == p->numFastBytes)\n+    {\n+      UInt32 numAvail = p->matchFinder.GetNumAvailableBytes(p->matchFinderObj) + 1;\n+      const Byte *pby = p->matchFinder.GetPointerToCurrentPos(p->matchFinderObj) - 1;\n+      UInt32 distance = p->matchDistances[numDistancePairs - 1] + 1;\n+      if (numAvail > LZMA_MATCH_LEN_MAX)\n+        numAvail = LZMA_MATCH_LEN_MAX;\n+\n+      {\n+        const Byte *pby2 = pby - distance;\n+        for (; lenRes < numAvail && pby[lenRes] == pby2[lenRes]; lenRes++);\n+      }\n+    }\n+  }\n+  p->additionalOffset++;\n+  *numDistancePairsRes = numDistancePairs;\n+  return lenRes;\n+}\n+\n+\n+#define MakeAsChar(p) (p)->backPrev = (UInt32)(-1); (p)->prev1IsChar = False;\n+#define MakeAsShortRep(p) (p)->backPrev = 0; (p)->prev1IsChar = False;\n+#define IsShortRep(p) ((p)->backPrev == 0)\n+\n+static UInt32 GetRepLen1Price(CLzmaEnc *p, UInt32 state, UInt32 posState)\n+{\n+  return \n+    GET_PRICE_0(p->isRepG0[state]) +\n+    GET_PRICE_0(p->isRep0Long[state][posState]);\n+}\n+\n+static UInt32 GetPureRepPrice(CLzmaEnc *p, UInt32 repIndex, UInt32 state, UInt32 posState)\n+{\n+  UInt32 price;\n+  if (repIndex == 0)\n+  {\n+    price = GET_PRICE_0(p->isRepG0[state]);\n+    price += GET_PRICE_1(p->isRep0Long[state][posState]);\n+  }\n+  else\n+  {\n+    price = GET_PRICE_1(p->isRepG0[state]);\n+    if (repIndex == 1)\n+      price += GET_PRICE_0(p->isRepG1[state]);\n+    else\n+    {\n+      price += GET_PRICE_1(p->isRepG1[state]);\n+      price += GET_PRICE(p->isRepG2[state], repIndex - 2);\n+    }\n+  }\n+  return price;\n+}\n+\n+static UInt32 GetRepPrice(CLzmaEnc *p, UInt32 repIndex, UInt32 len, UInt32 state, UInt32 posState)\n+{\n+  return p->repLenEnc.prices[posState][len - LZMA_MATCH_LEN_MIN] +\n+    GetPureRepPrice(p, repIndex, state, posState);\n+}\n+\n+static UInt32 Backward(CLzmaEnc *p, UInt32 *backRes, UInt32 cur)\n+{\n+  UInt32 posMem = p->opt[cur].posPrev;\n+  UInt32 backMem = p->opt[cur].backPrev;\n+  p->optimumEndIndex = cur;\n+  do\n+  {\n+    if (p->opt[cur].prev1IsChar)\n+    {\n+      MakeAsChar(&p->opt[posMem])\n+      p->opt[posMem].posPrev = posMem - 1;\n+      if (p->opt[cur].prev2)\n+      {\n+        p->opt[posMem - 1].prev1IsChar = False;\n+        p->opt[posMem - 1].posPrev = p->opt[cur].posPrev2;\n+        p->opt[posMem - 1].backPrev = p->opt[cur].backPrev2;\n+      }\n+    }\n+    {\n+      UInt32 posPrev = posMem;\n+      UInt32 backCur = backMem;\n+      \n+      backMem = p->opt[posPrev].backPrev;\n+      posMem = p->opt[posPrev].posPrev;\n+      \n+      p->opt[posPrev].backPrev = backCur;\n+      p->opt[posPrev].posPrev = cur;\n+      cur = posPrev;\n+    }\n+  }\n+  while (cur != 0);\n+  *backRes = p->opt[0].backPrev;\n+  p->optimumCurrentIndex  = p->opt[0].posPrev;\n+  return p->optimumCurrentIndex; \n+}\n+\n+#define LIT_PROBS(pos, prevByte) (p->litProbs + ((((pos) & p->lpMask) << p->lc) + ((prevByte) >> (8 - p->lc))) * 0x300)\n+\n+static UInt32 GetOptimum(CLzmaEnc *p, UInt32 position, UInt32 *backRes)\n+{\n+  UInt32 numAvailableBytes, lenMain, numDistancePairs;\n+  const Byte *data;\n+  UInt32 reps[LZMA_NUM_REPS];\n+  UInt32 repLens[LZMA_NUM_REPS];\n+  UInt32 repMaxIndex, i;\n+  UInt32 *matchDistances;\n+  Byte currentByte, matchByte; \n+  UInt32 posState;\n+  UInt32 matchPrice, repMatchPrice;\n+  UInt32 lenEnd;\n+  UInt32 len;\n+  UInt32 normalMatchPrice;\n+  UInt32 cur;\n+  if (p->optimumEndIndex != p->optimumCurrentIndex)\n+  {\n+    const COptimal *opt = &p->opt[p->optimumCurrentIndex];\n+    UInt32 lenRes = opt->posPrev - p->optimumCurrentIndex;\n+    *backRes = opt->backPrev;\n+    p->optimumCurrentIndex = opt->posPrev;\n+    return lenRes;\n+  }\n+  p->optimumCurrentIndex = p->optimumEndIndex = 0;\n+  \n+  numAvailableBytes = p->matchFinder.GetNumAvailableBytes(p->matchFinderObj);\n+\n+  if (!p->longestMatchWasFound)\n+  {\n+    lenMain = ReadMatchDistances(p, &numDistancePairs);\n+  }\n+  else\n+  {\n+    lenMain = p->longestMatchLength;\n+    numDistancePairs = p->numDistancePairs;\n+    p->longestMatchWasFound = False;\n+  }\n+\n+  data = p->matchFinder.GetPointerToCurrentPos(p->matchFinderObj) - 1;\n+  if (numAvailableBytes < 2)\n+  {\n+    *backRes = (UInt32)(-1);\n+    return 1;\n+  }\n+  if (numAvailableBytes > LZMA_MATCH_LEN_MAX)\n+    numAvailableBytes = LZMA_MATCH_LEN_MAX;\n+\n+  repMaxIndex = 0;\n+  for (i = 0; i < LZMA_NUM_REPS; i++)\n+  {\n+    UInt32 lenTest;\n+    const Byte *data2;\n+    reps[i] = p->reps[i];\n+    data2 = data - (reps[i] + 1);\n+    if (data[0] != data2[0] || data[1] != data2[1])\n+    {\n+      repLens[i] = 0;\n+      continue;\n+    }\n+    for (lenTest = 2; lenTest < numAvailableBytes && data[lenTest] == data2[lenTest]; lenTest++);\n+    repLens[i] = lenTest;\n+    if (lenTest > repLens[repMaxIndex])\n+      repMaxIndex = i;\n+  }\n+  if (repLens[repMaxIndex] >= p->numFastBytes)\n+  {\n+    UInt32 lenRes;\n+    *backRes = repMaxIndex;\n+    lenRes = repLens[repMaxIndex];\n+    MovePos(p, lenRes - 1);\n+    return lenRes;\n+  }\n+\n+  matchDistances = p->matchDistances;\n+  if (lenMain >= p->numFastBytes)\n+  {\n+    *backRes = matchDistances[numDistancePairs - 1] + LZMA_NUM_REPS; \n+    MovePos(p, lenMain - 1);\n+    return lenMain;\n+  }\n+  currentByte = *data;\n+  matchByte = *(data - (reps[0] + 1));\n+\n+  if (lenMain < 2 && currentByte != matchByte && repLens[repMaxIndex] < 2)\n+  {\n+    *backRes = (UInt32)-1;\n+    return 1;\n+  }\n+\n+  p->opt[0].state = (CState)p->state;\n+\n+  posState = (position & p->pbMask);\n+\n+  {\n+    const CLzmaProb *probs = LIT_PROBS(position, *(data - 1));\n+    p->opt[1].price = GET_PRICE_0(p->isMatch[p->state][posState]) + \n+        (!IsCharState(p->state) ? \n+          LitEnc_GetPriceMatched(probs, currentByte, matchByte, p->ProbPrices) :\n+          LitEnc_GetPrice(probs, currentByte, p->ProbPrices));\n+  }\n+\n+  MakeAsChar(&p->opt[1]);\n+\n+  matchPrice = GET_PRICE_1(p->isMatch[p->state][posState]);\n+  repMatchPrice = matchPrice + GET_PRICE_1(p->isRep[p->state]);\n+\n+  if (matchByte == currentByte)\n+  {\n+    UInt32 shortRepPrice = repMatchPrice + GetRepLen1Price(p, p->state, posState);\n+    if (shortRepPrice < p->opt[1].price)\n+    {\n+      p->opt[1].price = shortRepPrice;\n+      MakeAsShortRep(&p->opt[1]);\n+    }\n+  }\n+  lenEnd = ((lenMain >= repLens[repMaxIndex]) ? lenMain : repLens[repMaxIndex]);\n+\n+  if (lenEnd < 2)\n+  {\n+    *backRes = p->opt[1].backPrev;\n+    return 1;\n+  }\n+\n+  p->opt[1].posPrev = 0;\n+  for (i = 0; i < LZMA_NUM_REPS; i++)\n+    p->opt[0].backs[i] = reps[i];\n+\n+  len = lenEnd;\n+  do\n+    p->opt[len--].price = kInfinityPrice;\n+  while (len >= 2);\n+\n+  for (i = 0; i < LZMA_NUM_REPS; i++)\n+  {\n+    UInt32 repLen = repLens[i];\n+    UInt32 price;\n+    if (repLen < 2)\n+      continue;\n+    price = repMatchPrice + GetPureRepPrice(p, i, p->state, posState);\n+    do\n+    {\n+      UInt32 curAndLenPrice = price + p->repLenEnc.prices[posState][repLen - 2];\n+      COptimal *opt = &p->opt[repLen];\n+      if (curAndLenPrice < opt->price) \n+      {\n+        opt->price = curAndLenPrice;\n+        opt->posPrev = 0;\n+        opt->backPrev = i;\n+        opt->prev1IsChar = False;\n+      }\n+    }\n+    while (--repLen >= 2);\n+  }\n+\n+  normalMatchPrice = matchPrice + GET_PRICE_0(p->isRep[p->state]);\n+\n+  len = ((repLens[0] >= 2) ? repLens[0] + 1 : 2);\n+  if (len <= lenMain)\n+  {\n+    UInt32 offs = 0;\n+    while (len > matchDistances[offs])\n+      offs += 2;\n+    for (; ; len++)\n+    {\n+      COptimal *opt;\n+      UInt32 distance = matchDistances[offs + 1];\n+\n+      UInt32 curAndLenPrice = normalMatchPrice + p->lenEnc.prices[posState][len - LZMA_MATCH_LEN_MIN];\n+      UInt32 lenToPosState = GetLenToPosState(len);\n+      if (distance < kNumFullDistances)\n+        curAndLenPrice += p->distancesPrices[lenToPosState][distance];\n+      else\n+      {\n+        UInt32 slot;\n+        GetPosSlot2(distance, slot);\n+        curAndLenPrice += p->alignPrices[distance & kAlignMask] + p->posSlotPrices[lenToPosState][slot];\n+      }\n+      opt = &p->opt[len];\n+      if (curAndLenPrice < opt->price) \n+      {\n+        opt->price = curAndLenPrice;\n+        opt->posPrev = 0;\n+        opt->backPrev = distance + LZMA_NUM_REPS;\n+        opt->prev1IsChar = False;\n+      }\n+      if (len == matchDistances[offs])\n+      {\n+        offs += 2;\n+        if (offs == numDistancePairs)\n+          break;\n+      }\n+    }\n+  }\n+\n+  cur = 0;\n+\n+    #ifdef SHOW_STAT2\n+    if (position >= 0)\n+    {\n+      unsigned i;\n+      printf(\"\\n pos = %4X\", position);\n+      for (i = cur; i <= lenEnd; i++)\n+      printf(\"\\nprice[%4X] = %d\", position - cur + i, p->opt[i].price);\n+    }\n+    #endif\n+\n+  for (;;)\n+  {\n+    UInt32 numAvailableBytesFull, newLen, numDistancePairs;\n+    COptimal *curOpt;\n+    UInt32 posPrev;\n+    UInt32 state;\n+    UInt32 curPrice;\n+    Bool nextIsChar;\n+    const Byte *data;\n+    Byte currentByte, matchByte;\n+    UInt32 posState;\n+    UInt32 curAnd1Price;\n+    COptimal *nextOpt;\n+    UInt32 matchPrice, repMatchPrice;  \n+    UInt32 numAvailableBytes;\n+    UInt32 startLen;\n+\n+    cur++;\n+    if (cur == lenEnd)\n+      return Backward(p, backRes, cur);\n+\n+    numAvailableBytesFull = p->matchFinder.GetNumAvailableBytes(p->matchFinderObj);\n+    newLen = ReadMatchDistances(p, &numDistancePairs);\n+    if (newLen >= p->numFastBytes)\n+    {\n+      p->numDistancePairs = numDistancePairs;\n+      p->longestMatchLength = newLen;\n+      p->longestMatchWasFound = True;\n+      return Backward(p, backRes, cur);\n+    }\n+    position++;\n+    curOpt = &p->opt[cur];\n+    posPrev = curOpt->posPrev;\n+    if (curOpt->prev1IsChar)\n+    {\n+      posPrev--;\n+      if (curOpt->prev2)\n+      {\n+        state = p->opt[curOpt->posPrev2].state;\n+        if (curOpt->backPrev2 < LZMA_NUM_REPS)\n+          state = kRepNextStates[state];\n+        else\n+          state = kMatchNextStates[state];\n+      }\n+      else\n+        state = p->opt[posPrev].state;\n+      state = kLiteralNextStates[state];\n+    }\n+    else\n+      state = p->opt[posPrev].state;\n+    if (posPrev == cur - 1)\n+    {\n+      if (IsShortRep(curOpt))\n+        state = kShortRepNextStates[state];\n+      else\n+        state = kLiteralNextStates[state];\n+    }\n+    else\n+    {\n+      UInt32 pos;\n+      const COptimal *prevOpt;\n+      if (curOpt->prev1IsChar && curOpt->prev2)\n+      {\n+        posPrev = curOpt->posPrev2;\n+        pos = curOpt->backPrev2;\n+        state = kRepNextStates[state];\n+      }\n+      else\n+      {\n+        pos = curOpt->backPrev;\n+        if (pos < LZMA_NUM_REPS)\n+          state = kRepNextStates[state];\n+        else\n+          state = kMatchNextStates[state];\n+      }\n+      prevOpt = &p->opt[posPrev];\n+      if (pos < LZMA_NUM_REPS)\n+      {\n+        UInt32 i;\n+        reps[0] = prevOpt->backs[pos];\n+        for (i = 1; i <= pos; i++)\n+          reps[i] = prevOpt->backs[i - 1];\n+        for (; i < LZMA_NUM_REPS; i++)\n+          reps[i] = prevOpt->backs[i];\n+      }\n+      else\n+      {\n+        UInt32 i;\n+        reps[0] = (pos - LZMA_NUM_REPS);\n+        for (i = 1; i < LZMA_NUM_REPS; i++)\n+          reps[i] = prevOpt->backs[i - 1];\n+      }\n+    }\n+    curOpt->state = (CState)state;\n+\n+    curOpt->backs[0] = reps[0];\n+    curOpt->backs[1] = reps[1];\n+    curOpt->backs[2] = reps[2];\n+    curOpt->backs[3] = reps[3];\n+\n+    curPrice = curOpt->price; \n+    nextIsChar = False;\n+    data = p->matchFinder.GetPointerToCurrentPos(p->matchFinderObj) - 1;\n+    currentByte = *data;\n+    matchByte = *(data - (reps[0] + 1));\n+\n+    posState = (position & p->pbMask);\n+\n+    curAnd1Price = curPrice + GET_PRICE_0(p->isMatch[state][posState]);\n+    {\n+      const CLzmaProb *probs = LIT_PROBS(position, *(data - 1));\n+      curAnd1Price += \n+        (!IsCharState(state) ? \n+          LitEnc_GetPriceMatched(probs, currentByte, matchByte, p->ProbPrices) :\n+          LitEnc_GetPrice(probs, currentByte, p->ProbPrices));\n+    }   \n+\n+    nextOpt = &p->opt[cur + 1];\n+\n+    if (curAnd1Price < nextOpt->price) \n+    {\n+      nextOpt->price = curAnd1Price;\n+      nextOpt->posPrev = cur;\n+      MakeAsChar(nextOpt);\n+      nextIsChar = True;\n+    }\n+\n+    matchPrice = curPrice + GET_PRICE_1(p->isMatch[state][posState]);\n+    repMatchPrice = matchPrice + GET_PRICE_1(p->isRep[state]);\n+    \n+    if (matchByte == currentByte && !(nextOpt->posPrev < cur && nextOpt->backPrev == 0))\n+    {\n+      UInt32 shortRepPrice = repMatchPrice + GetRepLen1Price(p, state, posState);\n+      if (shortRepPrice <= nextOpt->price)\n+      {\n+        nextOpt->price = shortRepPrice;\n+        nextOpt->posPrev = cur;\n+        MakeAsShortRep(nextOpt);\n+        nextIsChar = True;\n+      }\n+    }\n+\n+    {\n+      UInt32 temp = kNumOpts - 1 - cur;\n+      if (temp <  numAvailableBytesFull)\n+        numAvailableBytesFull = temp;\n+    }\n+    numAvailableBytes = numAvailableBytesFull;\n+\n+    if (numAvailableBytes < 2)\n+      continue;\n+    if (numAvailableBytes > p->numFastBytes)\n+      numAvailableBytes = p->numFastBytes;\n+    if (!nextIsChar && matchByte != currentByte) /* speed optimization */\n+    {\n+      /* try Literal + rep0 */\n+      UInt32 temp;\n+      UInt32 lenTest2;\n+      const Byte *data2 = data - (reps[0] + 1);\n+      UInt32 limit = p->numFastBytes + 1;\n+      if (limit > numAvailableBytesFull)\n+        limit = numAvailableBytesFull;\n+\n+      for (temp = 1; temp < limit && data[temp] == data2[temp]; temp++);\n+      lenTest2 = temp - 1;\n+      if (lenTest2 >= 2)\n+      {\n+        UInt32 state2 = kLiteralNextStates[state];\n+        UInt32 posStateNext = (position + 1) & p->pbMask;\n+        UInt32 nextRepMatchPrice = curAnd1Price + \n+            GET_PRICE_1(p->isMatch[state2][posStateNext]) +\n+            GET_PRICE_1(p->isRep[state2]);\n+        /* for (; lenTest2 >= 2; lenTest2--) */\n+        {\n+          UInt32 curAndLenPrice;\n+          COptimal *opt;\n+          UInt32 offset = cur + 1 + lenTest2;\n+          while (lenEnd < offset)\n+            p->opt[++lenEnd].price = kInfinityPrice;\n+          curAndLenPrice = nextRepMatchPrice + GetRepPrice(p, 0, lenTest2, state2, posStateNext);\n+          opt = &p->opt[offset];\n+          if (curAndLenPrice < opt->price) \n+          {\n+            opt->price = curAndLenPrice;\n+            opt->posPrev = cur + 1;\n+            opt->backPrev = 0;\n+            opt->prev1IsChar = True;\n+            opt->prev2 = False;\n+          }\n+        }\n+      }\n+    }\n+    \n+    startLen = 2; /* speed optimization */\n+    {\n+    UInt32 repIndex;\n+    for (repIndex = 0; repIndex < LZMA_NUM_REPS; repIndex++)\n+    {\n+      UInt32 lenTest;\n+      UInt32 lenTestTemp;\n+      UInt32 price;\n+      const Byte *data2 = data - (reps[repIndex] + 1);\n+      if (data[0] != data2[0] || data[1] != data2[1])\n+        continue;\n+      for (lenTest = 2; lenTest < numAvailableBytes && data[lenTest] == data2[lenTest]; lenTest++);\n+      while (lenEnd < cur + lenTest)\n+        p->opt[++lenEnd].price = kInfinityPrice;\n+      lenTestTemp = lenTest;\n+      price = repMatchPrice + GetPureRepPrice(p, repIndex, state, posState);\n+      do\n+      {\n+        UInt32 curAndLenPrice = price + p->repLenEnc.prices[posState][lenTest - 2];\n+        COptimal *opt = &p->opt[cur + lenTest];\n+        if (curAndLenPrice < opt->price) \n+        {\n+          opt->price = curAndLenPrice;\n+          opt->posPrev = cur;\n+          opt->backPrev = repIndex;\n+          opt->prev1IsChar = False;\n+        }\n+      }\n+      while (--lenTest >= 2);\n+      lenTest = lenTestTemp;\n+      \n+      if (repIndex == 0)\n+        startLen = lenTest + 1;\n+        \n+      /* if (_maxMode) */\n+        {\n+          UInt32 lenTest2 = lenTest + 1;\n+          UInt32 limit = lenTest2 + p->numFastBytes;\n+          UInt32 nextRepMatchPrice;\n+          if (limit > numAvailableBytesFull)\n+            limit = numAvailableBytesFull;\n+          for (; lenTest2 < limit && data[lenTest2] == data2[lenTest2]; lenTest2++);\n+          lenTest2 -= lenTest + 1;\n+          if (lenTest2 >= 2)\n+          {\n+            UInt32 state2 = kRepNextStates[state];\n+            UInt32 posStateNext = (position + lenTest) & p->pbMask;\n+            UInt32 curAndLenCharPrice = \n+                price + p->repLenEnc.prices[posState][lenTest - 2] + \n+                GET_PRICE_0(p->isMatch[state2][posStateNext]) +\n+                LitEnc_GetPriceMatched(LIT_PROBS(position + lenTest, data[lenTest - 1]),\n+                    data[lenTest], data2[lenTest], p->ProbPrices);\n+            state2 = kLiteralNextStates[state2];\n+            posStateNext = (position + lenTest + 1) & p->pbMask;\n+            nextRepMatchPrice = curAndLenCharPrice + \n+                GET_PRICE_1(p->isMatch[state2][posStateNext]) +\n+                GET_PRICE_1(p->isRep[state2]);\n+            \n+            /* for (; lenTest2 >= 2; lenTest2--) */\n+            {\n+              UInt32 curAndLenPrice;\n+              COptimal *opt;\n+              UInt32 offset = cur + lenTest + 1 + lenTest2;\n+              while (lenEnd < offset)\n+                p->opt[++lenEnd].price = kInfinityPrice;\n+              curAndLenPrice = nextRepMatchPrice + GetRepPrice(p, 0, lenTest2, state2, posStateNext);\n+              opt = &p->opt[offset];\n+              if (curAndLenPrice < opt->price) \n+              {\n+                opt->price = curAndLenPrice;\n+                opt->posPrev = cur + lenTest + 1;\n+                opt->backPrev = 0;\n+                opt->prev1IsChar = True;\n+                opt->prev2 = True;\n+                opt->posPrev2 = cur;\n+                opt->backPrev2 = repIndex;\n+              }\n+            }\n+          }\n+        }\n+    }\n+    }\n+    /* for (UInt32 lenTest = 2; lenTest <= newLen; lenTest++) */\n+    if (newLen > numAvailableBytes)\n+    {\n+      newLen = numAvailableBytes;\n+      for (numDistancePairs = 0; newLen > matchDistances[numDistancePairs]; numDistancePairs += 2);\n+      matchDistances[numDistancePairs] = newLen;\n+      numDistancePairs += 2;\n+    }\n+    if (newLen >= startLen)\n+    {\n+      UInt32 normalMatchPrice = matchPrice + GET_PRICE_0(p->isRep[state]);\n+      UInt32 offs, curBack, posSlot;\n+      UInt32 lenTest;\n+      while (lenEnd < cur + newLen)\n+        p->opt[++lenEnd].price = kInfinityPrice;\n+\n+      offs = 0;\n+      while (startLen > matchDistances[offs])\n+        offs += 2;\n+      curBack = matchDistances[offs + 1];\n+      GetPosSlot2(curBack, posSlot);\n+      for (lenTest = /*2*/ startLen; ; lenTest++)\n+      {\n+        UInt32 curAndLenPrice = normalMatchPrice + p->lenEnc.prices[posState][lenTest - LZMA_MATCH_LEN_MIN];\n+        UInt32 lenToPosState = GetLenToPosState(lenTest);\n+        COptimal *opt;\n+        if (curBack < kNumFullDistances)\n+          curAndLenPrice += p->distancesPrices[lenToPosState][curBack];\n+        else\n+          curAndLenPrice += p->posSlotPrices[lenToPosState][posSlot] + p->alignPrices[curBack & kAlignMask];\n+        \n+        opt = &p->opt[cur + lenTest];\n+        if (curAndLenPrice < opt->price) \n+        {\n+          opt->price = curAndLenPrice;\n+          opt->posPrev = cur;\n+          opt->backPrev = curBack + LZMA_NUM_REPS;\n+          opt->prev1IsChar = False;\n+        }\n+\n+        if (/*_maxMode && */lenTest == matchDistances[offs])\n+        {\n+          /* Try Match + Literal + Rep0 */\n+          const Byte *data2 = data - (curBack + 1);\n+          UInt32 lenTest2 = lenTest + 1;\n+          UInt32 limit = lenTest2 + p->numFastBytes;\n+          UInt32 nextRepMatchPrice;\n+          if (limit > numAvailableBytesFull)\n+            limit = numAvailableBytesFull;\n+          for (; lenTest2 < limit && data[lenTest2] == data2[lenTest2]; lenTest2++);\n+          lenTest2 -= lenTest + 1;\n+          if (lenTest2 >= 2)\n+          {\n+            UInt32 state2 = kMatchNextStates[state];\n+            UInt32 posStateNext = (position + lenTest) & p->pbMask;\n+            UInt32 curAndLenCharPrice = curAndLenPrice + \n+                GET_PRICE_0(p->isMatch[state2][posStateNext]) +\n+                LitEnc_GetPriceMatched(LIT_PROBS(position + lenTest, data[lenTest - 1]),\n+                    data[lenTest], data2[lenTest], p->ProbPrices);\n+            state2 = kLiteralNextStates[state2];\n+            posStateNext = (posStateNext + 1) & p->pbMask;\n+            nextRepMatchPrice = curAndLenCharPrice + \n+                GET_PRICE_1(p->isMatch[state2][posStateNext]) +\n+                GET_PRICE_1(p->isRep[state2]);\n+            \n+            /* for (; lenTest2 >= 2; lenTest2--) */\n+            {\n+              UInt32 offset = cur + lenTest + 1 + lenTest2;\n+              UInt32 curAndLenPrice;\n+              COptimal *opt;\n+              while (lenEnd < offset)\n+                p->opt[++lenEnd].price = kInfinityPrice;\n+              curAndLenPrice = nextRepMatchPrice + GetRepPrice(p, 0, lenTest2, state2, posStateNext);\n+              opt = &p->opt[offset];\n+              if (curAndLenPrice < opt->price) \n+              {\n+                opt->price = curAndLenPrice;\n+                opt->posPrev = cur + lenTest + 1;\n+                opt->backPrev = 0;\n+                opt->prev1IsChar = True;\n+                opt->prev2 = True;\n+                opt->posPrev2 = cur;\n+                opt->backPrev2 = curBack + LZMA_NUM_REPS;\n+              }\n+            }\n+          }\n+          offs += 2;\n+          if (offs == numDistancePairs)\n+            break;\n+          curBack = matchDistances[offs + 1];\n+          if (curBack >= kNumFullDistances)\n+            GetPosSlot2(curBack, posSlot);\n+        }\n+      }\n+    }\n+  }\n+}\n+\n+#define ChangePair(smallDist, bigDist) (((bigDist) >> 7) > (smallDist))\n+\n+static UInt32 GetOptimumFast(CLzmaEnc *p, UInt32 *backRes)\n+{\n+  UInt32 numAvailableBytes = p->matchFinder.GetNumAvailableBytes(p->matchFinderObj);\n+  UInt32 lenMain, numDistancePairs;\n+  const Byte *data;\n+  UInt32 repLens[LZMA_NUM_REPS];\n+  UInt32 repMaxIndex, i;\n+  UInt32 *matchDistances;\n+  UInt32 backMain;\n+\n+  if (!p->longestMatchWasFound)\n+  {\n+    lenMain = ReadMatchDistances(p, &numDistancePairs);\n+  }\n+  else\n+  {\n+    lenMain = p->longestMatchLength;\n+    numDistancePairs = p->numDistancePairs;\n+    p->longestMatchWasFound = False;\n+  }\n+\n+  data = p->matchFinder.GetPointerToCurrentPos(p->matchFinderObj) - 1;\n+  if (numAvailableBytes > LZMA_MATCH_LEN_MAX)\n+    numAvailableBytes = LZMA_MATCH_LEN_MAX;\n+  if (numAvailableBytes < 2)\n+  {\n+    *backRes = (UInt32)(-1);\n+    return 1;\n+  }\n+\n+  repMaxIndex = 0;\n+\n+  for (i = 0; i < LZMA_NUM_REPS; i++)\n+  {\n+    const Byte *data2 = data - (p->reps[i] + 1);\n+    UInt32 len;\n+    if (data[0] != data2[0] || data[1] != data2[1])\n+    {\n+      repLens[i] = 0;\n+      continue;\n+    }\n+    for (len = 2; len < numAvailableBytes && data[len] == data2[len]; len++);\n+    if (len >= p->numFastBytes)\n+    {\n+      *backRes = i;\n+      MovePos(p, len - 1);\n+      return len;\n+    }\n+    repLens[i] = len;\n+    if (len > repLens[repMaxIndex])\n+      repMaxIndex = i;\n+  }\n+  matchDistances = p->matchDistances;\n+  if (lenMain >= p->numFastBytes)\n+  {\n+    *backRes = matchDistances[numDistancePairs - 1] + LZMA_NUM_REPS; \n+    MovePos(p, lenMain - 1);\n+    return lenMain;\n+  }\n+\n+  backMain = 0; /* for GCC */\n+  if (lenMain >= 2)\n+  {\n+    backMain = matchDistances[numDistancePairs - 1];\n+    while (numDistancePairs > 2 && lenMain == matchDistances[numDistancePairs - 4] + 1)\n+    {\n+      if (!ChangePair(matchDistances[numDistancePairs - 3], backMain))\n+        break;\n+      numDistancePairs -= 2;\n+      lenMain = matchDistances[numDistancePairs - 2];\n+      backMain = matchDistances[numDistancePairs - 1];\n+    }\n+    if (lenMain == 2 && backMain >= 0x80)\n+      lenMain = 1;\n+  }\n+\n+  if (repLens[repMaxIndex] >= 2)\n+  {\n+    if (repLens[repMaxIndex] + 1 >= lenMain || \n+        (repLens[repMaxIndex] + 2 >= lenMain && (backMain > (1 << 9))) ||\n+        (repLens[repMaxIndex] + 3 >= lenMain && (backMain > (1 << 15))))\n+    {\n+      UInt32 lenRes;\n+      *backRes = repMaxIndex;\n+      lenRes = repLens[repMaxIndex];\n+      MovePos(p, lenRes - 1);\n+      return lenRes;\n+    }\n+  }\n+  \n+  if (lenMain >= 2 && numAvailableBytes > 2)\n+  {\n+    UInt32 i;\n+    numAvailableBytes = p->matchFinder.GetNumAvailableBytes(p->matchFinderObj);\n+    p->longestMatchLength = ReadMatchDistances(p, &p->numDistancePairs);\n+    if (p->longestMatchLength >= 2)\n+    {\n+      UInt32 newDistance = matchDistances[p->numDistancePairs - 1];\n+      if ((p->longestMatchLength >= lenMain && newDistance < backMain) || \n+          (p->longestMatchLength == lenMain + 1 && !ChangePair(backMain, newDistance)) ||\n+          (p->longestMatchLength > lenMain + 1) ||\n+          (p->longestMatchLength + 1 >= lenMain && lenMain >= 3 && ChangePair(newDistance, backMain)))\n+      {\n+        p->longestMatchWasFound = True;\n+        *backRes = (UInt32)(-1);\n+        return 1;\n+      }\n+    }\n+    data = p->matchFinder.GetPointerToCurrentPos(p->matchFinderObj) - 1;\n+    for (i = 0; i < LZMA_NUM_REPS; i++)\n+    {\n+      UInt32 len;\n+      const Byte *data2 = data - (p->reps[i] + 1);\n+      if (data[1] != data2[1] || data[2] != data2[2])\n+      {\n+        repLens[i] = 0;\n+        continue;\n+      }\n+      for (len = 2; len < numAvailableBytes && data[len] == data2[len]; len++);\n+      if (len + 1 >= lenMain)\n+      {\n+        p->longestMatchWasFound = True;\n+        *backRes = (UInt32)(-1);\n+        return 1;\n+      }\n+    }\n+    *backRes = backMain + LZMA_NUM_REPS; \n+    MovePos(p, lenMain - 2);\n+    return lenMain;\n+  }\n+  *backRes = (UInt32)(-1);\n+  return 1;\n+}\n+\n+static void WriteEndMarker(CLzmaEnc *p, UInt32 posState)\n+{\n+  UInt32 len;\n+  RangeEnc_EncodeBit(&p->rc, &p->isMatch[p->state][posState], 1);\n+  RangeEnc_EncodeBit(&p->rc, &p->isRep[p->state], 0);\n+  p->state = kMatchNextStates[p->state];\n+  len = LZMA_MATCH_LEN_MIN;\n+  LenEnc_Encode2(&p->lenEnc, &p->rc, len - LZMA_MATCH_LEN_MIN, posState, !p->fastMode, p->ProbPrices);\n+  RcTree_Encode(&p->rc, p->posSlotEncoder[GetLenToPosState(len)], kNumPosSlotBits, (1 << kNumPosSlotBits) - 1);\n+  RangeEnc_EncodeDirectBits(&p->rc, (((UInt32)1 << 30) - 1) >> kNumAlignBits, 30 - kNumAlignBits);\n+  RcTree_ReverseEncode(&p->rc, p->posAlignEncoder, kNumAlignBits, kAlignMask);\n+}\n+\n+static SRes CheckErrors(CLzmaEnc *p)\n+{\n+  if (p->result != SZ_OK)\n+    return p->result;\n+  if (p->rc.res != SZ_OK)\n+    p->result = SZ_ERROR_WRITE;\n+  if (p->matchFinderBase.result != SZ_OK)\n+    p->result = SZ_ERROR_READ;\n+  if (p->result != SZ_OK)\n+    p->finished = True;\n+  return p->result;\n+}\n+\n+static SRes Flush(CLzmaEnc *p, UInt32 nowPos)\n+{\n+  /* ReleaseMFStream(); */\n+  p->finished = True;\n+  if (p->writeEndMark)\n+    WriteEndMarker(p, nowPos & p->pbMask);\n+  RangeEnc_FlushData(&p->rc);\n+  RangeEnc_FlushStream(&p->rc);\n+  return CheckErrors(p);\n+}\n+\n+static void FillAlignPrices(CLzmaEnc *p)\n+{\n+  UInt32 i;\n+  for (i = 0; i < kAlignTableSize; i++)\n+    p->alignPrices[i] = RcTree_ReverseGetPrice(p->posAlignEncoder, kNumAlignBits, i, p->ProbPrices);\n+  p->alignPriceCount = 0;\n+}\n+\n+static void FillDistancesPrices(CLzmaEnc *p)\n+{\n+  UInt32 tempPrices[kNumFullDistances];\n+  UInt32 i, lenToPosState;\n+  for (i = kStartPosModelIndex; i < kNumFullDistances; i++)\n+  { \n+    UInt32 posSlot = GetPosSlot1(i);\n+    UInt32 footerBits = ((posSlot >> 1) - 1);\n+    UInt32 base = ((2 | (posSlot & 1)) << footerBits);\n+    tempPrices[i] = RcTree_ReverseGetPrice(p->posEncoders + base - posSlot - 1, footerBits, i - base, p->ProbPrices);\n+  }\n+\n+  for (lenToPosState = 0; lenToPosState < kNumLenToPosStates; lenToPosState++)\n+  {\n+    UInt32 posSlot;\n+    const CLzmaProb *encoder = p->posSlotEncoder[lenToPosState];\n+    UInt32 *posSlotPrices = p->posSlotPrices[lenToPosState];\n+    for (posSlot = 0; posSlot < p->distTableSize; posSlot++)\n+      posSlotPrices[posSlot] = RcTree_GetPrice(encoder, kNumPosSlotBits, posSlot, p->ProbPrices);\n+    for (posSlot = kEndPosModelIndex; posSlot < p->distTableSize; posSlot++)\n+      posSlotPrices[posSlot] += ((((posSlot >> 1) - 1) - kNumAlignBits) << kNumBitPriceShiftBits);\n+\n+    {\n+      UInt32 *distancesPrices = p->distancesPrices[lenToPosState];\n+      UInt32 i;\n+      for (i = 0; i < kStartPosModelIndex; i++)\n+        distancesPrices[i] = posSlotPrices[i];\n+      for (; i < kNumFullDistances; i++)\n+        distancesPrices[i] = posSlotPrices[GetPosSlot1(i)] + tempPrices[i];\n+    }\n+  }\n+  p->matchPriceCount = 0;\n+}\n+\n+static void LzmaEnc_Construct(CLzmaEnc *p)\n+{\n+  RangeEnc_Construct(&p->rc);\n+  MatchFinder_Construct(&p->matchFinderBase);\n+  #ifdef COMPRESS_MF_MT\n+  MatchFinderMt_Construct(&p->matchFinderMt);\n+  p->matchFinderMt.MatchFinder = &p->matchFinderBase;\n+  #endif\n+\n+  {\n+    CLzmaEncProps props;\n+    LzmaEncProps_Init(&props);\n+    LzmaEnc_SetProps(p, &props);\n+  }\n+\n+  #ifndef LZMA_LOG_BSR\n+  LzmaEnc_FastPosInit(p->g_FastPos);\n+  #endif\n+\n+  LzmaEnc_InitPriceTables(p->ProbPrices);\n+  p->litProbs = 0;\n+  p->saveState.litProbs = 0;\n+}\n+\n+CLzmaEncHandle LzmaEnc_Create(ISzAlloc *alloc)\n+{\n+  void *p;\n+  p = alloc->Alloc(alloc, sizeof(CLzmaEnc));\n+  if (p != 0)\n+    LzmaEnc_Construct((CLzmaEnc *)p);\n+  return p;\n+}\n+\n+static void LzmaEnc_FreeLits(CLzmaEnc *p, ISzAlloc *alloc)\n+{\n+  alloc->Free(alloc, p->litProbs);\n+  alloc->Free(alloc, p->saveState.litProbs);\n+  p->litProbs = 0;\n+  p->saveState.litProbs = 0;\n+}\n+\n+static void LzmaEnc_Destruct(CLzmaEnc *p, ISzAlloc *alloc, ISzAlloc *allocBig)\n+{\n+  #ifdef COMPRESS_MF_MT\n+  MatchFinderMt_Destruct(&p->matchFinderMt, allocBig);\n+  #endif\n+  MatchFinder_Free(&p->matchFinderBase, allocBig);\n+  LzmaEnc_FreeLits(p, alloc);\n+  RangeEnc_Free(&p->rc, alloc);\n+}\n+\n+void LzmaEnc_Destroy(CLzmaEncHandle p, ISzAlloc *alloc, ISzAlloc *allocBig)\n+{\n+  LzmaEnc_Destruct((CLzmaEnc *)p, alloc, allocBig);\n+  alloc->Free(alloc, p);\n+}\n+\n+static SRes LzmaEnc_CodeOneBlock(CLzmaEnc *p, Bool useLimits, UInt32 maxPackSize, UInt32 maxUnpackSize)\n+{\n+  UInt32 nowPos32, startPos32;\n+  if (p->inStream != 0)\n+  {\n+    p->matchFinderBase.stream = p->inStream;\n+    p->matchFinder.Init(p->matchFinderObj);\n+    p->inStream = 0;\n+  }\n+\n+  if (p->finished)\n+    return p->result;\n+  RINOK(CheckErrors(p));\n+\n+  nowPos32 = (UInt32)p->nowPos64;\n+  startPos32 = nowPos32;\n+\n+  if (p->nowPos64 == 0)\n+  {\n+    UInt32 numDistancePairs;\n+    Byte curByte;\n+    if (p->matchFinder.GetNumAvailableBytes(p->matchFinderObj) == 0)\n+      return Flush(p, nowPos32);\n+    ReadMatchDistances(p, &numDistancePairs);\n+    RangeEnc_EncodeBit(&p->rc, &p->isMatch[p->state][0], 0);\n+    p->state = kLiteralNextStates[p->state];\n+    curByte = p->matchFinder.GetIndexByte(p->matchFinderObj, 0 - p->additionalOffset);\n+    LitEnc_Encode(&p->rc, p->litProbs, curByte);\n+    p->additionalOffset--;\n+    nowPos32++;\n+  }\n+\n+  if (p->matchFinder.GetNumAvailableBytes(p->matchFinderObj) != 0)\n+  for (;;)\n+  {\n+    UInt32 pos, len, posState;\n+\n+    if (p->fastMode)\n+      len = GetOptimumFast(p, &pos);\n+    else\n+      len = GetOptimum(p, nowPos32, &pos);\n+\n+    #ifdef SHOW_STAT2\n+    printf(\"\\n pos = %4X,   len = %d   pos = %d\", nowPos32, len, pos);\n+    #endif\n+\n+    posState = nowPos32 & p->pbMask;\n+    if (len == 1 && pos == 0xFFFFFFFF)\n+    {\n+      Byte curByte;\n+      CLzmaProb *probs;\n+      const Byte *data;\n+\n+      RangeEnc_EncodeBit(&p->rc, &p->isMatch[p->state][posState], 0);\n+      data = p->matchFinder.GetPointerToCurrentPos(p->matchFinderObj) - p->additionalOffset;\n+      curByte = *data;\n+      probs = LIT_PROBS(nowPos32, *(data - 1));\n+      if (IsCharState(p->state))\n+        LitEnc_Encode(&p->rc, probs, curByte);\n+      else\n+        LitEnc_EncodeMatched(&p->rc, probs, curByte, *(data - p->reps[0] - 1));\n+      p->state = kLiteralNextStates[p->state];\n+    }\n+    else\n+    {\n+      RangeEnc_EncodeBit(&p->rc, &p->isMatch[p->state][posState], 1);\n+      if (pos < LZMA_NUM_REPS)\n+      {\n+        RangeEnc_EncodeBit(&p->rc, &p->isRep[p->state], 1);\n+        if (pos == 0)\n+        {\n+          RangeEnc_EncodeBit(&p->rc, &p->isRepG0[p->state], 0);\n+          RangeEnc_EncodeBit(&p->rc, &p->isRep0Long[p->state][posState], ((len == 1) ? 0 : 1));\n+        }\n+        else\n+        {\n+          UInt32 distance = p->reps[pos];\n+          RangeEnc_EncodeBit(&p->rc, &p->isRepG0[p->state], 1);\n+          if (pos == 1)\n+            RangeEnc_EncodeBit(&p->rc, &p->isRepG1[p->state], 0);\n+          else\n+          {\n+            RangeEnc_EncodeBit(&p->rc, &p->isRepG1[p->state], 1);\n+            RangeEnc_EncodeBit(&p->rc, &p->isRepG2[p->state], pos - 2);\n+            if (pos == 3)\n+              p->reps[3] = p->reps[2];\n+            p->reps[2] = p->reps[1];\n+          }\n+          p->reps[1] = p->reps[0];\n+          p->reps[0] = distance;\n+        }\n+        if (len == 1)\n+          p->state = kShortRepNextStates[p->state];\n+        else\n+        {\n+          LenEnc_Encode2(&p->repLenEnc, &p->rc, len - LZMA_MATCH_LEN_MIN, posState, !p->fastMode, p->ProbPrices);\n+          p->state = kRepNextStates[p->state];\n+        }\n+      }\n+      else\n+      {\n+        UInt32 posSlot;\n+        RangeEnc_EncodeBit(&p->rc, &p->isRep[p->state], 0);\n+        p->state = kMatchNextStates[p->state];\n+        LenEnc_Encode2(&p->lenEnc, &p->rc, len - LZMA_MATCH_LEN_MIN, posState, !p->fastMode, p->ProbPrices);\n+        pos -= LZMA_NUM_REPS;\n+        GetPosSlot(pos, posSlot);\n+        RcTree_Encode(&p->rc, p->posSlotEncoder[GetLenToPosState(len)], kNumPosSlotBits, posSlot);\n+        \n+        if (posSlot >= kStartPosModelIndex)\n+        {\n+          UInt32 footerBits = ((posSlot >> 1) - 1);\n+          UInt32 base = ((2 | (posSlot & 1)) << footerBits);\n+          UInt32 posReduced = pos - base;\n+\n+          if (posSlot < kEndPosModelIndex)\n+            RcTree_ReverseEncode(&p->rc, p->posEncoders + base - posSlot - 1, footerBits, posReduced);\n+          else\n+          {\n+            RangeEnc_EncodeDirectBits(&p->rc, posReduced >> kNumAlignBits, footerBits - kNumAlignBits);\n+            RcTree_ReverseEncode(&p->rc, p->posAlignEncoder, kNumAlignBits, posReduced & kAlignMask);\n+            p->alignPriceCount++;\n+          }\n+        }\n+        p->reps[3] = p->reps[2];\n+        p->reps[2] = p->reps[1];\n+        p->reps[1] = p->reps[0];\n+        p->reps[0] = pos;\n+        p->matchPriceCount++;\n+      }\n+    }\n+    p->additionalOffset -= len;\n+    nowPos32 += len;\n+    if (p->additionalOffset == 0)\n+    {\n+      UInt32 processed;\n+      if (!p->fastMode)\n+      {\n+        if (p->matchPriceCount >= (1 << 7))\n+          FillDistancesPrices(p);\n+        if (p->alignPriceCount >= kAlignTableSize)\n+          FillAlignPrices(p);\n+      }\n+      if (p->matchFinder.GetNumAvailableBytes(p->matchFinderObj) == 0)\n+        break;\n+      processed = nowPos32 - startPos32;\n+      if (useLimits)\n+      {\n+        if (processed + kNumOpts + 300 >= maxUnpackSize ||\n+            RangeEnc_GetProcessed(&p->rc) + kNumOpts * 2 >= maxPackSize)\n+          break;\n+      }\n+      else if (processed >= (1 << 15))\n+      {\n+        p->nowPos64 += nowPos32 - startPos32;\n+        return CheckErrors(p);\n+      }\n+    }\n+  }\n+  p->nowPos64 += nowPos32 - startPos32;\n+  return Flush(p, nowPos32);\n+}\n+\n+#define kBigHashDicLimit ((UInt32)1 << 24)\n+\n+static SRes LzmaEnc_Alloc(CLzmaEnc *p, UInt32 keepWindowSize, ISzAlloc *alloc, ISzAlloc *allocBig)\n+{\n+  UInt32 beforeSize = kNumOpts;\n+  Bool btMode;\n+  if (!RangeEnc_Alloc(&p->rc, alloc))\n+    return SZ_ERROR_MEM;\n+  btMode = (p->matchFinderBase.btMode != 0);\n+  #ifdef COMPRESS_MF_MT\n+  p->mtMode = (p->multiThread && !p->fastMode && btMode);\n+  #endif\n+\n+  {\n+    unsigned lclp = p->lc + p->lp;\n+    if (p->litProbs == 0 || p->saveState.litProbs == 0 || p->lclp != lclp)\n+    {\n+      LzmaEnc_FreeLits(p, alloc);\n+      p->litProbs = (CLzmaProb *)alloc->Alloc(alloc, (0x300 << lclp) * sizeof(CLzmaProb));\n+      p->saveState.litProbs = (CLzmaProb *)alloc->Alloc(alloc, (0x300 << lclp) * sizeof(CLzmaProb));\n+      if (p->litProbs == 0 || p->saveState.litProbs == 0)\n+      {\n+        LzmaEnc_FreeLits(p, alloc);\n+        return SZ_ERROR_MEM;\n+      }\n+      p->lclp = lclp;\n+    }\n+  }\n+\n+  p->matchFinderBase.bigHash = (p->dictSize > kBigHashDicLimit);\n+\n+  if (beforeSize + p->dictSize < keepWindowSize)\n+    beforeSize = keepWindowSize - p->dictSize;\n+\n+  #ifdef COMPRESS_MF_MT\n+  if (p->mtMode)\n+  {\n+    RINOK(MatchFinderMt_Create(&p->matchFinderMt, p->dictSize, beforeSize, p->numFastBytes, LZMA_MATCH_LEN_MAX, allocBig));\n+    p->matchFinderObj = &p->matchFinderMt;\n+    MatchFinderMt_CreateVTable(&p->matchFinderMt, &p->matchFinder);\n+  }\n+  else\n+  #endif\n+  {\n+    if (!MatchFinder_Create(&p->matchFinderBase, p->dictSize, beforeSize, p->numFastBytes, LZMA_MATCH_LEN_MAX, allocBig))\n+      return SZ_ERROR_MEM;\n+    p->matchFinderObj = &p->matchFinderBase;\n+    MatchFinder_CreateVTable(&p->matchFinderBase, &p->matchFinder);\n+  }\n+  return SZ_OK;\n+}\n+\n+static void LzmaEnc_Init(CLzmaEnc *p)\n+{\n+  UInt32 i;\n+  p->state = 0;\n+  for(i = 0 ; i < LZMA_NUM_REPS; i++)\n+    p->reps[i] = 0;\n+\n+  RangeEnc_Init(&p->rc);\n+\n+\n+  for (i = 0; i < kNumStates; i++)\n+  {\n+    UInt32 j;\n+    for (j = 0; j < LZMA_NUM_PB_STATES_MAX; j++)\n+    {\n+      p->isMatch[i][j] = kProbInitValue;\n+      p->isRep0Long[i][j] = kProbInitValue;\n+    }\n+    p->isRep[i] = kProbInitValue;\n+    p->isRepG0[i] = kProbInitValue;\n+    p->isRepG1[i] = kProbInitValue;\n+    p->isRepG2[i] = kProbInitValue;\n+  }\n+\n+  {\n+    UInt32 num = 0x300 << (p->lp + p->lc);\n+    for (i = 0; i < num; i++)\n+      p->litProbs[i] = kProbInitValue;\n+  }\n+\n+  {\n+    for (i = 0; i < kNumLenToPosStates; i++)\n+    {\n+      CLzmaProb *probs = p->posSlotEncoder[i];\n+      UInt32 j;\n+      for (j = 0; j < (1 << kNumPosSlotBits); j++)\n+        probs[j] = kProbInitValue;\n+    }\n+  }\n+  {\n+    for(i = 0; i < kNumFullDistances - kEndPosModelIndex; i++)\n+      p->posEncoders[i] = kProbInitValue;\n+  }\n+\n+  LenEnc_Init(&p->lenEnc.p);\n+  LenEnc_Init(&p->repLenEnc.p);\n+\n+  for (i = 0; i < (1 << kNumAlignBits); i++)\n+    p->posAlignEncoder[i] = kProbInitValue;\n+\n+  p->longestMatchWasFound = False;\n+  p->optimumEndIndex = 0;\n+  p->optimumCurrentIndex = 0;\n+  p->additionalOffset = 0;\n+\n+  p->pbMask = (1 << p->pb) - 1;\n+  p->lpMask = (1 << p->lp) - 1;\n+}\n+\n+static void LzmaEnc_InitPrices(CLzmaEnc *p)\n+{\n+  if (!p->fastMode)\n+  {\n+    FillDistancesPrices(p);\n+    FillAlignPrices(p);\n+  }\n+\n+  p->lenEnc.tableSize = \n+  p->repLenEnc.tableSize = \n+      p->numFastBytes + 1 - LZMA_MATCH_LEN_MIN;\n+  LenPriceEnc_UpdateTables(&p->lenEnc, 1 << p->pb, p->ProbPrices);\n+  LenPriceEnc_UpdateTables(&p->repLenEnc, 1 << p->pb, p->ProbPrices);\n+}\n+\n+static SRes LzmaEnc_AllocAndInit(CLzmaEnc *p, UInt32 keepWindowSize, ISzAlloc *alloc, ISzAlloc *allocBig)\n+{\n+  UInt32 i;\n+  for (i = 0; i < (UInt32)kDicLogSizeMaxCompress; i++)\n+    if (p->dictSize <= ((UInt32)1 << i))\n+      break;\n+  p->distTableSize = i * 2;\n+\n+  p->finished = False;\n+  p->result = SZ_OK;\n+  RINOK(LzmaEnc_Alloc(p, keepWindowSize, alloc, allocBig));\n+  LzmaEnc_Init(p);\n+  LzmaEnc_InitPrices(p);\n+  p->nowPos64 = 0;\n+  return SZ_OK;\n+}\n+\n+static SRes LzmaEnc_Prepare(CLzmaEncHandle pp, ISeqInStream *inStream, ISeqOutStream *outStream,\n+    ISzAlloc *alloc, ISzAlloc *allocBig)\n+{\n+  CLzmaEnc *p = (CLzmaEnc *)pp;\n+  p->inStream = inStream;\n+  p->rc.outStream = outStream;\n+  return LzmaEnc_AllocAndInit(p, 0, alloc, allocBig);\n+}\n+\n+static SRes LzmaEnc_PrepareForLzma2(CLzmaEncHandle pp, \n+    ISeqInStream *inStream, UInt32 keepWindowSize,\n+    ISzAlloc *alloc, ISzAlloc *allocBig)\n+{\n+  CLzmaEnc *p = (CLzmaEnc *)pp;\n+  p->inStream = inStream;\n+  return LzmaEnc_AllocAndInit(p, keepWindowSize, alloc, allocBig);\n+}\n+\n+static void LzmaEnc_SetInputBuf(CLzmaEnc *p, const Byte *src, SizeT srcLen)\n+{\n+  p->seqBufInStream.funcTable.Read = MyRead;\n+  p->seqBufInStream.data = src;\n+  p->seqBufInStream.rem = srcLen;\n+}\n+\n+static SRes LzmaEnc_MemPrepare(CLzmaEncHandle pp, const Byte *src, SizeT srcLen,\n+    UInt32 keepWindowSize, ISzAlloc *alloc, ISzAlloc *allocBig)\n+{\n+  CLzmaEnc *p = (CLzmaEnc *)pp;\n+  LzmaEnc_SetInputBuf(p, src, srcLen);\n+  p->inStream = &p->seqBufInStream.funcTable;\n+  return LzmaEnc_AllocAndInit(p, keepWindowSize, alloc, allocBig);\n+}\n+\n+static void LzmaEnc_Finish(CLzmaEncHandle pp)\n+{\n+  #ifdef COMPRESS_MF_MT\n+  CLzmaEnc *p = (CLzmaEnc *)pp;\n+  if (p->mtMode)\n+    MatchFinderMt_ReleaseStream(&p->matchFinderMt);\n+  #endif\n+}\n+\n+typedef struct _CSeqOutStreamBuf\n+{\n+  ISeqOutStream funcTable;\n+  Byte *data;\n+  SizeT rem;\n+  Bool overflow;\n+} CSeqOutStreamBuf;\n+\n+static size_t MyWrite(void *pp, const void *data, size_t size)\n+{\n+  CSeqOutStreamBuf *p = (CSeqOutStreamBuf *)pp;\n+  if (p->rem < size)\n+  {\n+    size = p->rem;\n+    p->overflow = True;\n+  }\n+  memcpy(p->data, data, size);\n+  p->rem -= size;\n+  p->data += size;\n+  return size;\n+}\n+\n+\n+static UInt32 LzmaEnc_GetNumAvailableBytes(CLzmaEncHandle pp)\n+{\n+  const CLzmaEnc *p = (CLzmaEnc *)pp;\n+  return p->matchFinder.GetNumAvailableBytes(p->matchFinderObj);\n+}\n+\n+static const Byte *LzmaEnc_GetCurBuf(CLzmaEncHandle pp)\n+{\n+  const CLzmaEnc *p = (CLzmaEnc *)pp;\n+  return p->matchFinder.GetPointerToCurrentPos(p->matchFinderObj) - p->additionalOffset;\n+}\n+\n+static SRes LzmaEnc_CodeOneMemBlock(CLzmaEncHandle pp, Bool reInit, \n+    Byte *dest, size_t *destLen, UInt32 desiredPackSize, UInt32 *unpackSize)\n+{\n+  CLzmaEnc *p = (CLzmaEnc *)pp;\n+  UInt64 nowPos64;\n+  SRes res;\n+  CSeqOutStreamBuf outStream;\n+\n+  outStream.funcTable.Write = MyWrite;\n+  outStream.data = dest;\n+  outStream.rem = *destLen;\n+  outStream.overflow = False;\n+\n+  p->writeEndMark = False;\n+  p->finished = False;\n+  p->result = SZ_OK;\n+\n+  if (reInit)\n+    LzmaEnc_Init(p);\n+  LzmaEnc_InitPrices(p);\n+  nowPos64 = p->nowPos64;\n+  RangeEnc_Init(&p->rc);\n+  p->rc.outStream = &outStream.funcTable;\n+\n+  res = LzmaEnc_CodeOneBlock(pp, True, desiredPackSize, *unpackSize);\n+  \n+  *unpackSize = (UInt32)(p->nowPos64 - nowPos64);\n+  *destLen -= outStream.rem;\n+  if (outStream.overflow)\n+    return SZ_ERROR_OUTPUT_EOF;\n+\n+  return res;\n+}\n+\n+SRes LzmaEnc_Encode(CLzmaEncHandle pp, ISeqOutStream *outStream, ISeqInStream *inStream, ICompressProgress *progress,\n+    ISzAlloc *alloc, ISzAlloc *allocBig)\n+{\n+  CLzmaEnc *p = (CLzmaEnc *)pp;\n+  SRes res = SZ_OK;\n+\n+  #ifdef COMPRESS_MF_MT\n+  Byte allocaDummy[0x300];\n+  int i = 0;\n+  for (i = 0; i < 16; i++)\n+    allocaDummy[i] = (Byte)i;\n+  #endif\n+\n+  RINOK(LzmaEnc_Prepare(pp, inStream, outStream, alloc, allocBig));\n+\n+  for (;;)\n+  {\n+    res = LzmaEnc_CodeOneBlock(pp, False, 0, 0);\n+    if (res != SZ_OK || p->finished != 0)\n+      break;\n+    if (progress != 0)\n+    {\n+      res = progress->Progress(progress, p->nowPos64, RangeEnc_GetProcessed(&p->rc));\n+      if (res != SZ_OK)\n+      {\n+        res = SZ_ERROR_PROGRESS;\n+        break;\n+      }\n+    }\n+  }\n+  LzmaEnc_Finish(pp);\n+  return res;\n+}\n+\n+SRes LzmaEnc_WriteProperties(CLzmaEncHandle pp, Byte *props, SizeT *size)\n+{\n+  CLzmaEnc *p = (CLzmaEnc *)pp;\n+  int i;\n+  UInt32 dictSize = p->dictSize;\n+  if (*size < LZMA_PROPS_SIZE)\n+    return SZ_ERROR_PARAM;\n+  *size = LZMA_PROPS_SIZE;\n+  props[0] = (Byte)((p->pb * 5 + p->lp) * 9 + p->lc);\n+\n+  for (i = 11; i <= 30; i++)\n+  {\n+    if (dictSize <= ((UInt32)2 << i))\n+    {\n+      dictSize = (2 << i);\n+      break;\n+    }\n+    if (dictSize <= ((UInt32)3 << i))\n+    {\n+      dictSize = (3 << i);\n+      break;\n+    }\n+  }\n+\n+  for (i = 0; i < 4; i++)\n+    props[1 + i] = (Byte)(dictSize >> (8 * i));\n+  return SZ_OK;\n+}\n+\n+SRes LzmaEnc_MemEncode(CLzmaEncHandle pp, Byte *dest, SizeT *destLen, const Byte *src, SizeT srcLen,\n+    int writeEndMark, ICompressProgress *progress, ISzAlloc *alloc, ISzAlloc *allocBig)\n+{\n+  SRes res;\n+  CLzmaEnc *p = (CLzmaEnc *)pp;\n+\n+  CSeqOutStreamBuf outStream;\n+\n+  LzmaEnc_SetInputBuf(p, src, srcLen);\n+\n+  outStream.funcTable.Write = MyWrite;\n+  outStream.data = dest;\n+  outStream.rem = *destLen;\n+  outStream.overflow = False;\n+\n+  p->writeEndMark = writeEndMark;\n+  res = LzmaEnc_Encode(pp, &outStream.funcTable, &p->seqBufInStream.funcTable, \n+      progress, alloc, allocBig);\n+\n+  *destLen -= outStream.rem;\n+  if (outStream.overflow)\n+    return SZ_ERROR_OUTPUT_EOF;\n+  return res;\n+}\n+\n+SRes LzmaEncode(Byte *dest, SizeT *destLen, const Byte *src, SizeT srcLen,\n+    const CLzmaEncProps *props, Byte *propsEncoded, SizeT *propsSize, int writeEndMark, \n+    ICompressProgress *progress, ISzAlloc *alloc, ISzAlloc *allocBig)\n+{\n+  CLzmaEnc *p = (CLzmaEnc *)LzmaEnc_Create(alloc);\n+  SRes res;\n+  if (p == 0)\n+    return SZ_ERROR_MEM;\n+\n+  res = LzmaEnc_SetProps(p, props);\n+  if (res == SZ_OK)\n+  {\n+    res = LzmaEnc_WriteProperties(p, propsEncoded, propsSize);\n+    if (res == SZ_OK)\n+      res = LzmaEnc_MemEncode(p, dest, destLen, src, srcLen,\n+          writeEndMark, progress, alloc, allocBig);\n+  }\n+\n+  LzmaEnc_Destroy(p, alloc, allocBig);\n+  return res;\n+}\n--- a/jffsX-utils/mkfs.jffs2.c\n+++ b/jffsX-utils/mkfs.jffs2.c\n@@ -1667,11 +1667,11 @@ int main(int argc, char **argv)\n \t\t\t\t\t\t  }\n \t\t\t\t\t\t  erase_block_size *= units;\n \n-\t\t\t\t\t\t  /* If it's less than 8KiB, they're not allowed */\n-\t\t\t\t\t\t  if (erase_block_size < 0x2000) {\n-\t\t\t\t\t\t\t  fprintf(stderr, \"Erase size 0x%x too small. Increasing to 8KiB minimum\\n\",\n+\t\t\t\t\t\t  /* If it's less than 4KiB, they're not allowed */\n+\t\t\t\t\t\t  if (erase_block_size < 0x1000) {\n+\t\t\t\t\t\t\t  fprintf(stderr, \"Erase size 0x%x too small. Increasing to 4KiB minimum\\n\",\n \t\t\t\t\t\t\t\t\t  erase_block_size);\n-\t\t\t\t\t\t\t  erase_block_size = 0x2000;\n+\t\t\t\t\t\t\t  erase_block_size = 0x1000;\n \t\t\t\t\t\t  }\n \t\t\t\t\t\t  break;\n \t\t\t\t\t  }\n"
  },
  {
    "path": "package/utils/nvram/Makefile",
    "content": "#\n# Copyright (C) 2009-2010 Jo-Philipp Wich <xm@subsignal.org>\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=nvram\nPKG_RELEASE:=11\n\nPKG_BUILD_DIR := $(BUILD_DIR)/$(PKG_NAME)\n\nPKG_FLAGS:=nonshared\n\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine Package/nvram\n  SECTION:=utils\n  CATEGORY:=Base system\n  TITLE:=Userspace port of the Broadcom NVRAM manipulation tool\n  MAINTAINER:=Jo-Philipp Wich <xm@subsignal.org>\n  DEPENDS:=@(TARGET_bcm47xx||TARGET_bcm53xx||TARGET_ath79)\nendef\n\ndefine Package/nvram/description\n This package contains an utility to manipulate NVRAM on Broadcom based devices.\n It works on bcm47xx (Linux 2.6) without using the kernel api.\nendef\n\ndefine Build/Configure\nendef\n\ndefine Build/Compile\n\t$(MAKE) -C $(PKG_BUILD_DIR) \\\n\t\tCC=\"$(TARGET_CC)\" \\\n\t\tCFLAGS=\"$(TARGET_CFLAGS) -Wall\" \\\n\t\tLDFLAGS=\"$(TARGET_LDFLAGS)\"\nendef\n\ndefine Package/nvram/install\n\t$(INSTALL_DIR) $(1)/usr/sbin\n\t$(INSTALL_BIN) $(PKG_BUILD_DIR)/nvram $(1)/usr/sbin/\nifneq ($(CONFIG_TARGET_bcm47xx),)\n\t$(INSTALL_DIR) $(1)/etc/init.d\n\t$(INSTALL_BIN) ./files/nvram-bcm47xx.init $(1)/etc/init.d/nvram\nendif\nifneq ($(CONFIG_TARGET_bcm53xx),)\n\t$(INSTALL_DIR) $(1)/etc/init.d\n\t$(INSTALL_BIN) ./files/nvram-bcm53xx.init $(1)/etc/init.d/nvram\nendif\nendef\n\n$(eval $(call BuildPackage,nvram))\n"
  },
  {
    "path": "package/utils/nvram/files/nvram-bcm47xx.init",
    "content": "#!/bin/sh /etc/rc.common\n# NVRAM setup\n#\n# This file handles the NVRAM quirks of various hardware of the bcm47xx target.\n\nSTART=02\nalias debug=${DEBUG:-:}\n\nnvram_default() {\n\t[ -z \"$(nvram get $1)\" ] && nvram set \"$1=$2\"\n}\n\nnvram_set() { # for the linksys fixup part\n\t[ \"$(nvram get \"$1\")\" = \"$2\" -a \"$2\" != \"\" ] || {\n\t\tCOMMIT=1\n\t\t/usr/sbin/nvram set \"$1=$2\"\n\t}\n}\n\nfixup_linksys() {\n\t# work around braindead CFE defaults in linksys routers\n\tboardtype=$(nvram get boardtype)\n\tboardnum=$(nvram get boardnum)\n\tboardflags=$(($(nvram get boardflags)))\n\tadm_switch=\"$(( ($boardflags & 0x80) >> 7 ))\"\n\n\t[ -n \"$(nvram get vxkilled)\" ] && boardtype=0 # don't mess with the ram settings on the hacked cfe\n\tcase \"$(( $boardtype ))\" in\n\t\t\"1800\") #0x708\n\t\t\tif [ \"$adm_switch\" = 0 ]; then\n\t\t\t\tnvram_set sdram_init \"$(printf 0x%04x $(( $(/usr/sbin/nvram get sdram_init) | 0x0100 )))\"\n\t\t\t\t[ \"$COMMIT\" = 1 ] && {\n\t\t\t\t\tnvram_set clkfreq 216\n\t\t\t\t\tnvram_set sdram_ncdl 0x0\n\t\t\t\t\tnvram_set pa0itssit 62\n\t\t\t\t\tnvram_set pa0b0 0x15eb\n\t\t\t\t\tnvram_set pa0b1 0xfa82\n\t\t\t\t\tnvram_set pa0b2 0xfe66\n\t\t\t\t\tnvram_set pa0maxpwr 0x4e\n\t\t\t\t}\n\t\t\tfi\n\t\t;;\n\t\t\"1127\") #0x467\n\t\t\tnvram_set sdram_init \"$(printf 0x%04x $(( $(/usr/sbin/nvram get sdram_init) | 0x0100 )))\"\n\t\t\t[ \"$COMMIT\" = 1 ] && {\n\t\t\t\tnvram_set sdram_ncdl 0x0\n\t\t\t\tnvram_set pa0itssit 62\n\t\t\t\tnvram_set pa0b0 0x168b\n\t\t\t\tnvram_set pa0b1 0xfabf\n\t\t\t\tnvram_set pa0b2 0xfeaf\n\t\t\t\tnvram_set pa0maxpwr 0x4e\n\t\t\t}\n\t\t;;\n\t\t\"1071\") #0x042f\n\t\t\t# do sanity check first! max 0x0011 = 128mb\n\t\t\tSDRAM_INIT=$(printf %d $(/usr/sbin/nvram get sdram_init))\n\t\t\t[ \"$SDRAM_INIT\" -lt \"9\" -o \"$SDRAM_INIT\" -gt \"17\" ] && {\n\t\t\t\t# set this to default: 0x09 only if value is invaild like 16MB on Asus WL-500GP\n\t\t\t\techo \"sdram_init is invaild: $(printf 0x%04x $SDRAM_INIT), force to default!\"\n\t\t\t\tnvram_set sdram_init 0x0009\n\t\t\t}\n\t\t\t# on WRT54G3GV2 set flag, so checksum errors of firmware image 2 don't stop the boot process\n\t\t\tnoset_try_flag=$(nvram get noset_try_flag)\n\t\t\t[ \"$noset_try_flag\" = 0 ] && {\n\t\t\t\techo \"setting noset_try_flag to 1.\"\n\t\t\t\tnvram_set noset_try_flag 1\n\t\t\t}\n\t\t\t[ \"$COMMIT\" = 1 ] && {\n\t\t\t\tnvram_set sdram_ncdl 0x0\n\t\t\t}\n\tesac\n}\n\nboot() {\n\t# Don't do any fixups on the WGT634U\n\t[ \"$(cat /proc/diag/model)\" = \"Netgear WGT634U\" ] && return\n\n\tfixup_linksys\n\n\t# OFDM Power Offset is set incorrectly on many boards.\n\t# Setting it to 0 will increase the tx power to normal levels.\n\tnvram_set opo 0x0\n\n\t[ \"$(nvram get il0macaddr)\" = \"00:90:4c:5f:00:2a\" ] && {\n\t\t# if default wifi mac, set two higher than the lan mac\n\t\tnvram set il0macaddr=$(nvram get et0macaddr|\n\t\tawk '{OFS=FS=\":\";for(x=7,y=2;--x;){$x=sprintf(\"%02x\",(y+=\"0x\"$x)%256);y/=256}print}')\n\t}\n\n\t[ \"$(nvram get et0macaddr)\" = \"00:90:4c:c0:00:08\" ] && {\n\t\t# OvisLink WL-1600GL mac workaround\n\t\tnvram set et0macaddr=$(hexdump -n 6 -s 130976 -e '5/1 \"%02x:\" \"%02x\" ' /dev/mtd/0)\n\t\tnvram set il0macaddr=$(nvram get et0macaddr|\n\t\tawk '{OFS=FS=\":\";for(x=7,y=2;--x;){$x=sprintf(\"%02x\",(y+=\"0x\"$x)%256);y/=256}print}')\n\t}\n\n\t[ \"$COMMIT\" = \"1\" ] && nvram commit\n}\n"
  },
  {
    "path": "package/utils/nvram/files/nvram-bcm53xx.init",
    "content": "#!/bin/sh /etc/rc.common\n# NVRAM setup\n#\n# This file handles the NVRAM quirks of various hardware of the bcm53xx target.\n\nSTART=02\n\nclear_partialboots() {\n\t# clear partialboots\n\n\tcase $(board_name) in\n\t\tlinksys,panamera)\n\t\t\tCOMMIT=1\n\t\t\tnvram set partialboots=0\n\t\t\t;;\n\tesac\n}\n\nset_wireless_led_behaviour() {\n\t# set Broadcom wireless LED behaviour for both radios\n\t# 0:ledbh9 -> Behaviour of 2.4GHz LED\n\t# 1:ledbh9 -> Behaviour of 5GHz LED\n\t# 0x7 makes the wireless LEDs on, when radios are enabled, and blink when there's activity\n\n\tcase $(board_name) in\n\t\tasus,rt-ac88u)\n\t\t\tCOMMIT=1\n\t\t\tnvram set 0:ledbh9=0x7 set 1:ledbh9=0x7\n\t\t\t;;\n\tesac\n}\n\nboot() {\n\t. /lib/functions.sh\n\n\tclear_partialboots\n\tset_wireless_led_behaviour\n\n\t[ \"$COMMIT\" = \"1\" ] && nvram commit\n}\n"
  },
  {
    "path": "package/utils/nvram/src/Makefile",
    "content": "all: nvram\n\nnvram:\n\t$(CC) $(CFLAGS) -o $@ cli.c crc.c nvram.c $(LDFLAGS)\n\nclean:\n\trm -f nvram\n"
  },
  {
    "path": "package/utils/nvram/src/cli.c",
    "content": "/*\n * Command line interface for libnvram\n *\n * Copyright 2009, Jo-Philipp Wich <xm@subsignal.org>\n *\n * This program is free software; you can redistribute it and/or\n * modify it under the terms of the GNU General Public License\n * as published by the Free Software Foundation; either version 2\n * of the License, or (at your option) any later version.\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n * GNU General Public License for more details.\n *\n * You should have received a copy of the GNU General Public License\n * along with this program; if not, write to the Free Software\n * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.\n *\n *\n * The libnvram code is based on Broadcom code for Linux 2.4.x .\n *\n */\n\n#include \"nvram.h\"\n\n\nstatic nvram_handle_t * nvram_open_rdonly(void)\n{\n\tchar *file = nvram_find_staging();\n\n\tif( file == NULL )\n\t\tfile = nvram_find_mtd();\n\n\tif( file != NULL ) {\n\t\tnvram_handle_t *h = nvram_open(file, NVRAM_RO);\n\t\tif( strcmp(file, NVRAM_STAGING) )\n\t\t\tfree(file);\n\t\treturn h;\n\t}\n\n\treturn NULL;\n}\n\nstatic nvram_handle_t * nvram_open_staging(void)\n{\n\tif( nvram_find_staging() != NULL || nvram_to_staging() == 0 )\n\t\treturn nvram_open(NVRAM_STAGING, NVRAM_RW);\n\n\treturn NULL;\n}\n\nstatic int do_show(nvram_handle_t *nvram)\n{\n\tnvram_tuple_t *t;\n\tint stat = 1;\n\n\tif( (t = nvram_getall(nvram)) != NULL )\n\t{\n\t\twhile( t )\n\t\t{\n\t\t\tprintf(\"%s=%s\\n\", t->name, t->value);\n\t\t\tt = t->next;\n\t\t}\n\n\t\tstat = 0;\n\t}\n\n\treturn stat;\n}\n\nstatic int do_get(nvram_handle_t *nvram, const char *var)\n{\n\tconst char *val;\n\tint stat = 1;\n\n\tif( (val = nvram_get(nvram, var)) != NULL )\n\t{\n\t\tprintf(\"%s\\n\", val);\n\t\tstat = 0;\n\t}\n\n\treturn stat;\n}\n\nstatic int do_unset(nvram_handle_t *nvram, const char *var)\n{\n\treturn nvram_unset(nvram, var);\n}\n\nstatic int do_set(nvram_handle_t *nvram, const char *pair)\n{\n\tchar *val = strstr(pair, \"=\");\n\tchar var[strlen(pair)];\n\tint stat = 1;\n\n\tif( val != NULL )\n\t{\n\t\tmemset(var, 0, sizeof(var));\n\t\tstrncpy(var, pair, (int)(val-pair));\n\t\tstat = nvram_set(nvram, var, (char *)(val + 1));\n\t}\n\n\treturn stat;\n}\n\nstatic int do_info(nvram_handle_t *nvram)\n{\n\tnvram_header_t *hdr = nvram_header(nvram);\n\n\t/* CRC8 over the last 11 bytes of the header and data bytes */\n\tuint8_t crc = hndcrc8((unsigned char *) &hdr[0] + NVRAM_CRC_START_POSITION,\n\t\thdr->len - NVRAM_CRC_START_POSITION, 0xff);\n\n\t/* Show info */\n\tprintf(\"Magic:         0x%08X\\n\",   hdr->magic);\n\tprintf(\"Length:        0x%08X\\n\",   hdr->len);\n\tprintf(\"Offset:        0x%08X\\n\",   nvram->offset);\n\n\tprintf(\"CRC8:          0x%02X (calculated: 0x%02X)\\n\",\n\t\thdr->crc_ver_init & 0xFF, crc);\n\n\tprintf(\"Version:       0x%02X\\n\",   (hdr->crc_ver_init >> 8) & 0xFF);\n\tprintf(\"SDRAM init:    0x%04X\\n\",   (hdr->crc_ver_init >> 16) & 0xFFFF);\n\tprintf(\"SDRAM config:  0x%04X\\n\",   hdr->config_refresh & 0xFFFF);\n\tprintf(\"SDRAM refresh: 0x%04X\\n\",   (hdr->config_refresh >> 16) & 0xFFFF);\n\tprintf(\"NCDL values:   0x%08X\\n\\n\", hdr->config_ncdl);\n\n\tprintf(\"%i bytes used / %i bytes available (%.2f%%)\\n\",\n\t\thdr->len, nvram->length - nvram->offset - hdr->len,\n\t\t(100.00 / (double)(nvram->length - nvram->offset)) * (double)hdr->len);\n\n\treturn 0;\n}\n\nstatic void usage(void)\n{\n\tfprintf(stderr,\n\t\t\"Usage:\\n\"\n\t\t\"\tnvram show\\n\"\n\t\t\"\tnvram info\\n\"\n\t\t\"\tnvram get variable\\n\"\n\t\t\"\tnvram set variable=value [set ...]\\n\"\n\t\t\"\tnvram unset variable [unset ...]\\n\"\n\t\t\"\tnvram commit\\n\"\n\t);\n}\n\nint main( int argc, const char *argv[] )\n{\n\tnvram_handle_t *nvram;\n\tint commit = 0;\n\tint write = 0;\n\tint stat = 1;\n\tint done = 0;\n\tint i;\n\n\tif( argc < 2 ) {\n\t\tusage();\n\t\treturn 1;\n\t}\n\n\t/* Ugly... iterate over arguments to see whether we can expect a write */\n\tif( ( !strcmp(argv[1], \"set\")  && 2 < argc ) ||\n\t\t( !strcmp(argv[1], \"unset\") && 2 < argc ) ||\n\t\t!strcmp(argv[1], \"commit\") )\n\t\twrite = 1;\n\n\n\tnvram = write ? nvram_open_staging() : nvram_open_rdonly();\n\n\tif( nvram != NULL && argc > 1 )\n\t{\n\t\tfor( i = 1; i < argc; i++ )\n\t\t{\n\t\t\tif( !strcmp(argv[i], \"show\") )\n\t\t\t{\n\t\t\t\tstat = do_show(nvram);\n\t\t\t\tdone++;\n\t\t\t}\n\t\t\telse if( !strcmp(argv[i], \"info\") )\n\t\t\t{\n\t\t\t\tstat = do_info(nvram);\n\t\t\t\tdone++;\n\t\t\t}\n\t\t\telse if( !strcmp(argv[i], \"get\") || !strcmp(argv[i], \"unset\") || !strcmp(argv[i], \"set\") )\n\t\t\t{\n\t\t\t\tif( (i+1) < argc )\n\t\t\t\t{\n\t\t\t\t\tswitch(argv[i++][0])\n\t\t\t\t\t{\n\t\t\t\t\t\tcase 'g':\n\t\t\t\t\t\t\tstat = do_get(nvram, argv[i]);\n\t\t\t\t\t\t\tbreak;\n\n\t\t\t\t\t\tcase 'u':\n\t\t\t\t\t\t\tstat = do_unset(nvram, argv[i]);\n\t\t\t\t\t\t\tbreak;\n\n\t\t\t\t\t\tcase 's':\n\t\t\t\t\t\t\tstat = do_set(nvram, argv[i]);\n\t\t\t\t\t\t\tbreak;\n\t\t\t\t\t}\n\t\t\t\t\tdone++;\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\tfprintf(stderr, \"Command '%s' requires an argument!\\n\", argv[i]);\n\t\t\t\t\tdone = 0;\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t}\n\t\t\telse if( !strcmp(argv[i], \"commit\") )\n\t\t\t{\n\t\t\t\tcommit = 1;\n\t\t\t\tdone++;\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tfprintf(stderr, \"Unknown option '%s' !\\n\", argv[i]);\n\t\t\t\tdone = 0;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\n\t\tif( write )\n\t\t\tstat = nvram_commit(nvram);\n\n\t\tnvram_close(nvram);\n\n\t\tif( commit )\n\t\t\tstat = staging_to_nvram();\n\t}\n\n\tif( !nvram )\n\t{\n\t\tfprintf(stderr,\n\t\t\t\"Could not open nvram! Possible reasons are:\\n\"\n\t\t\t\"\t- No device found (/proc not mounted or no nvram present)\\n\"\n\t\t\t\"\t- Insufficient permissions to open mtd device\\n\"\n\t\t\t\"\t- Insufficient memory to complete operation\\n\"\n\t\t\t\"\t- Memory mapping failed or not supported\\n\"\n\t\t\t\"\t- Nvram magic not found in specific nvram partition\\n\"\n\t\t);\n\n\t\tstat = 1;\n\t}\n\telse if( !done )\n\t{\n\t\tusage();\n\t\tstat = 1;\n\t}\n\n\treturn stat;\n}\n"
  },
  {
    "path": "package/utils/nvram/src/crc.c",
    "content": "#include \"nvram.h\"\n\n/*******************************************************************************\n * crc8\n *\n * Computes a crc8 over the input data using the polynomial:\n *\n *       x^8 + x^7 +x^6 + x^4 + x^2 + 1\n *\n * The caller provides the initial value (either CRC8_INIT_VALUE\n * or the previous returned value) to allow for processing of\n * discontiguous blocks of data.  When generating the CRC the\n * caller is responsible for complementing the final return value\n * and inserting it into the byte stream.  When checking, a final\n * return value of CRC8_GOOD_VALUE indicates a valid CRC.\n *\n * Reference: Dallas Semiconductor Application Note 27\n *   Williams, Ross N., \"A Painless Guide to CRC Error Detection Algorithms\",\n *     ver 3, Aug 1993, ross@guest.adelaide.edu.au, Rocksoft Pty Ltd.,\n *     ftp://ftp.rocksoft.com/clients/rocksoft/papers/crc_v3.txt\n *\n * ****************************************************************************\n */\n\nstatic const uint8_t crc8_table[256] = {\n\t0x00, 0xF7, 0xB9, 0x4E, 0x25, 0xD2, 0x9C, 0x6B,\n\t0x4A, 0xBD, 0xF3, 0x04, 0x6F, 0x98, 0xD6, 0x21,\n\t0x94, 0x63, 0x2D, 0xDA, 0xB1, 0x46, 0x08, 0xFF,\n\t0xDE, 0x29, 0x67, 0x90, 0xFB, 0x0C, 0x42, 0xB5,\n\t0x7F, 0x88, 0xC6, 0x31, 0x5A, 0xAD, 0xE3, 0x14,\n\t0x35, 0xC2, 0x8C, 0x7B, 0x10, 0xE7, 0xA9, 0x5E,\n\t0xEB, 0x1C, 0x52, 0xA5, 0xCE, 0x39, 0x77, 0x80,\n\t0xA1, 0x56, 0x18, 0xEF, 0x84, 0x73, 0x3D, 0xCA,\n\t0xFE, 0x09, 0x47, 0xB0, 0xDB, 0x2C, 0x62, 0x95,\n\t0xB4, 0x43, 0x0D, 0xFA, 0x91, 0x66, 0x28, 0xDF,\n\t0x6A, 0x9D, 0xD3, 0x24, 0x4F, 0xB8, 0xF6, 0x01,\n\t0x20, 0xD7, 0x99, 0x6E, 0x05, 0xF2, 0xBC, 0x4B,\n\t0x81, 0x76, 0x38, 0xCF, 0xA4, 0x53, 0x1D, 0xEA,\n\t0xCB, 0x3C, 0x72, 0x85, 0xEE, 0x19, 0x57, 0xA0,\n\t0x15, 0xE2, 0xAC, 0x5B, 0x30, 0xC7, 0x89, 0x7E,\n\t0x5F, 0xA8, 0xE6, 0x11, 0x7A, 0x8D, 0xC3, 0x34,\n\t0xAB, 0x5C, 0x12, 0xE5, 0x8E, 0x79, 0x37, 0xC0,\n\t0xE1, 0x16, 0x58, 0xAF, 0xC4, 0x33, 0x7D, 0x8A,\n\t0x3F, 0xC8, 0x86, 0x71, 0x1A, 0xED, 0xA3, 0x54,\n\t0x75, 0x82, 0xCC, 0x3B, 0x50, 0xA7, 0xE9, 0x1E,\n\t0xD4, 0x23, 0x6D, 0x9A, 0xF1, 0x06, 0x48, 0xBF,\n\t0x9E, 0x69, 0x27, 0xD0, 0xBB, 0x4C, 0x02, 0xF5,\n\t0x40, 0xB7, 0xF9, 0x0E, 0x65, 0x92, 0xDC, 0x2B,\n\t0x0A, 0xFD, 0xB3, 0x44, 0x2F, 0xD8, 0x96, 0x61,\n\t0x55, 0xA2, 0xEC, 0x1B, 0x70, 0x87, 0xC9, 0x3E,\n\t0x1F, 0xE8, 0xA6, 0x51, 0x3A, 0xCD, 0x83, 0x74,\n\t0xC1, 0x36, 0x78, 0x8F, 0xE4, 0x13, 0x5D, 0xAA,\n\t0x8B, 0x7C, 0x32, 0xC5, 0xAE, 0x59, 0x17, 0xE0,\n\t0x2A, 0xDD, 0x93, 0x64, 0x0F, 0xF8, 0xB6, 0x41,\n\t0x60, 0x97, 0xD9, 0x2E, 0x45, 0xB2, 0xFC, 0x0B,\n\t0xBE, 0x49, 0x07, 0xF0, 0x9B, 0x6C, 0x22, 0xD5,\n\t0xF4, 0x03, 0x4D, 0xBA, 0xD1, 0x26, 0x68, 0x9F\n};\n\nuint8_t hndcrc8 (\n\tuint8_t * pdata,  /* pointer to array of data to process */\n\tuint32_t nbytes,  /* number of input data bytes to process */\n\tuint8_t crc       /* either CRC8_INIT_VALUE or previous return value */\n) {\n\twhile (nbytes-- > 0)\n\t\tcrc = crc8_table[(crc ^ *pdata++) & 0xff];\n\n\treturn crc;\n}\n"
  },
  {
    "path": "package/utils/nvram/src/nvram.c",
    "content": "/*\n * NVRAM variable manipulation (common)\n *\n * Copyright 2004, Broadcom Corporation\n * Copyright 2009-2010, OpenWrt.org\n * All Rights Reserved.\n *\n * THIS SOFTWARE IS OFFERED \"AS IS\", AND BROADCOM GRANTS NO WARRANTIES OF ANY\n * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM\n * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.\n *\n */\n\n#include \"nvram.h\"\n\n#define TRACE(msg) \\\n\tprintf(\"%s(%i) in %s(): %s\\n\", \\\n\t\t__FILE__, __LINE__, __FUNCTION__, msg ? msg : \"?\")\n\n/* Size of \"nvram\" MTD partition */\nsize_t nvram_part_size = 0;\n\n\n/*\n * -- Helper functions --\n */\n\n/* String hash */\nstatic uint32_t hash(const char *s)\n{\n\tuint32_t hash = 0;\n\n\twhile (*s)\n\t\thash = 31 * hash + *s++;\n\n\treturn hash;\n}\n\n/* Free all tuples. */\nstatic void _nvram_free(nvram_handle_t *h)\n{\n\tuint32_t i;\n\tnvram_tuple_t *t, *next;\n\n\t/* Free hash table */\n\tfor (i = 0; i < NVRAM_ARRAYSIZE(h->nvram_hash); i++) {\n\t\tfor (t = h->nvram_hash[i]; t; t = next) {\n\t\t\tnext = t->next;\n\t\t\tif (t->value)\n\t\t\t\tfree(t->value);\n\t\t\tfree(t);\n\t\t}\n\t\th->nvram_hash[i] = NULL;\n\t}\n\n\t/* Free dead table */\n\tfor (t = h->nvram_dead; t; t = next) {\n\t\tnext = t->next;\n\t\tif (t->value)\n\t\t\tfree(t->value);\n\t\tfree(t);\n\t}\n\n\th->nvram_dead = NULL;\n}\n\n/* (Re)allocate NVRAM tuples. */\nstatic nvram_tuple_t * _nvram_realloc( nvram_handle_t *h, nvram_tuple_t *t,\n\tconst char *name, const char *value )\n{\n\tif ((strlen(value) + 1) > h->length - h->offset)\n\t\treturn NULL;\n\n\tif (!t) {\n\t\tif (!(t = malloc(sizeof(nvram_tuple_t) + strlen(name) + 1)))\n\t\t\treturn NULL;\n\n\t\t/* Copy name */\n\t\tt->name = (char *) &t[1];\n\t\tstrcpy(t->name, name);\n\n\t\tt->value = NULL;\n\t}\n\n\t/* Copy value */\n\tif (!t->value || strcmp(t->value, value))\n\t{\n\t\tif(!(t->value = (char *) realloc(t->value, strlen(value)+1)))\n\t\t\treturn NULL;\n\n\t\tstrcpy(t->value, value);\n\t\tt->value[strlen(value)] = '\\0';\n\t}\n\n\treturn t;\n}\n\n/* (Re)initialize the hash table. */\nstatic int _nvram_rehash(nvram_handle_t *h)\n{\n\tnvram_header_t *header = nvram_header(h);\n\tchar buf[] = \"0xXXXXXXXX\", *name, *value, *eq;\n\n\t/* (Re)initialize hash table */\n\t_nvram_free(h);\n\n\t/* Parse and set \"name=value\\0 ... \\0\\0\" */\n\tname = (char *) &header[1];\n\n\tfor (; *name; name = value + strlen(value) + 1) {\n\t\tif (!(eq = strchr(name, '=')))\n\t\t\tbreak;\n\t\t*eq = '\\0';\n\t\tvalue = eq + 1;\n\t\tnvram_set(h, name, value);\n\t\t*eq = '=';\n\t}\n\n\t/* Set special SDRAM parameters */\n\tif (!nvram_get(h, \"sdram_init\")) {\n\t\tsprintf(buf, \"0x%04X\", (uint16_t)(header->crc_ver_init >> 16));\n\t\tnvram_set(h, \"sdram_init\", buf);\n\t}\n\tif (!nvram_get(h, \"sdram_config\")) {\n\t\tsprintf(buf, \"0x%04X\", (uint16_t)(header->config_refresh & 0xffff));\n\t\tnvram_set(h, \"sdram_config\", buf);\n\t}\n\tif (!nvram_get(h, \"sdram_refresh\")) {\n\t\tsprintf(buf, \"0x%04X\",\n\t\t\t(uint16_t)((header->config_refresh >> 16) & 0xffff));\n\t\tnvram_set(h, \"sdram_refresh\", buf);\n\t}\n\tif (!nvram_get(h, \"sdram_ncdl\")) {\n\t\tsprintf(buf, \"0x%08X\", header->config_ncdl);\n\t\tnvram_set(h, \"sdram_ncdl\", buf);\n\t}\n\n\treturn 0;\n}\n\n\n/*\n * -- Public functions --\n */\n\n/* Get nvram header. */\nnvram_header_t * nvram_header(nvram_handle_t *h)\n{\n\treturn (nvram_header_t *) &h->mmap[h->offset];\n}\n\n/* Get the value of an NVRAM variable. */\nchar * nvram_get(nvram_handle_t *h, const char *name)\n{\n\tuint32_t i;\n\tnvram_tuple_t *t;\n\tchar *value;\n\n\tif (!name)\n\t\treturn NULL;\n\n\t/* Hash the name */\n\ti = hash(name) % NVRAM_ARRAYSIZE(h->nvram_hash);\n\n\t/* Find the associated tuple in the hash table */\n\tfor (t = h->nvram_hash[i]; t && strcmp(t->name, name); t = t->next);\n\n\tvalue = t ? t->value : NULL;\n\n\treturn value;\n}\n\n/* Set the value of an NVRAM variable. */\nint nvram_set(nvram_handle_t *h, const char *name, const char *value)\n{\n\tuint32_t i;\n\tnvram_tuple_t *t, *u, **prev;\n\n\t/* Hash the name */\n\ti = hash(name) % NVRAM_ARRAYSIZE(h->nvram_hash);\n\n\t/* Find the associated tuple in the hash table */\n\tfor (prev = &h->nvram_hash[i], t = *prev;\n\t\t t && strcmp(t->name, name); prev = &t->next, t = *prev);\n\n\t/* (Re)allocate tuple */\n\tif (!(u = _nvram_realloc(h, t, name, value)))\n\t\treturn -12; /* -ENOMEM */\n\n\t/* Value reallocated */\n\tif (t && t == u)\n\t\treturn 0;\n\n\t/* Move old tuple to the dead table */\n\tif (t) {\n\t\t*prev = t->next;\n\t\tt->next = h->nvram_dead;\n\t\th->nvram_dead = t;\n\t}\n\n\t/* Add new tuple to the hash table */\n\tu->next = h->nvram_hash[i];\n\th->nvram_hash[i] = u;\n\n\treturn 0;\n}\n\n/* Unset the value of an NVRAM variable. */\nint nvram_unset(nvram_handle_t *h, const char *name)\n{\n\tuint32_t i;\n\tnvram_tuple_t *t, **prev;\n\n\tif (!name)\n\t\treturn 0;\n\n\t/* Hash the name */\n\ti = hash(name) % NVRAM_ARRAYSIZE(h->nvram_hash);\n\n\t/* Find the associated tuple in the hash table */\n\tfor (prev = &h->nvram_hash[i], t = *prev;\n\t\t t && strcmp(t->name, name); prev = &t->next, t = *prev);\n\n\t/* Move it to the dead table */\n\tif (t) {\n\t\t*prev = t->next;\n\t\tt->next = h->nvram_dead;\n\t\th->nvram_dead = t;\n\t}\n\n\treturn 0;\n}\n\n/* Get all NVRAM variables. */\nnvram_tuple_t * nvram_getall(nvram_handle_t *h)\n{\n\tint i;\n\tnvram_tuple_t *t, *l, *x;\n\n\tl = NULL;\n\n\tfor (i = 0; i < NVRAM_ARRAYSIZE(h->nvram_hash); i++) {\n\t\tfor (t = h->nvram_hash[i]; t; t = t->next) {\n\t\t\tif( (x = (nvram_tuple_t *) malloc(sizeof(nvram_tuple_t))) != NULL )\n\t\t\t{\n\t\t\t\tx->name  = t->name;\n\t\t\t\tx->value = t->value;\n\t\t\t\tx->next  = l;\n\t\t\t\tl = x;\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t}\n\n\treturn l;\n}\n\n/* Regenerate NVRAM. */\nint nvram_commit(nvram_handle_t *h)\n{\n\tnvram_header_t *header = nvram_header(h);\n\tchar *init, *config, *refresh, *ncdl;\n\tchar *ptr, *end;\n\tint i;\n\tnvram_tuple_t *t;\n\tnvram_header_t tmp;\n\tuint8_t crc;\n\n\t/* Regenerate header */\n\theader->magic = NVRAM_MAGIC;\n\theader->crc_ver_init = (NVRAM_VERSION << 8);\n\tif (!(init = nvram_get(h, \"sdram_init\")) ||\n\t\t!(config = nvram_get(h, \"sdram_config\")) ||\n\t\t!(refresh = nvram_get(h, \"sdram_refresh\")) ||\n\t\t!(ncdl = nvram_get(h, \"sdram_ncdl\"))) {\n\t\theader->crc_ver_init |= SDRAM_INIT << 16;\n\t\theader->config_refresh = SDRAM_CONFIG;\n\t\theader->config_refresh |= SDRAM_REFRESH << 16;\n\t\theader->config_ncdl = 0;\n\t} else {\n\t\theader->crc_ver_init |= (strtoul(init, NULL, 0) & 0xffff) << 16;\n\t\theader->config_refresh = strtoul(config, NULL, 0) & 0xffff;\n\t\theader->config_refresh |= (strtoul(refresh, NULL, 0) & 0xffff) << 16;\n\t\theader->config_ncdl = strtoul(ncdl, NULL, 0);\n\t}\n\n\t/* Clear data area */\n\tptr = (char *) header + sizeof(nvram_header_t);\n\tmemset(ptr, 0xFF, nvram_part_size - h->offset - sizeof(nvram_header_t));\n\tmemset(&tmp, 0, sizeof(nvram_header_t));\n\n\t/* Leave space for a double NUL at the end */\n\tend = (char *) header + nvram_part_size - h->offset - 2;\n\n\t/* Write out all tuples */\n\tfor (i = 0; i < NVRAM_ARRAYSIZE(h->nvram_hash); i++) {\n\t\tfor (t = h->nvram_hash[i]; t; t = t->next) {\n\t\t\tif ((ptr + strlen(t->name) + 1 + strlen(t->value) + 1) > end)\n\t\t\t\tbreak;\n\t\t\tptr += sprintf(ptr, \"%s=%s\", t->name, t->value) + 1;\n\t\t}\n\t}\n\n\t/* End with a double NULL and pad to 4 bytes */\n\t*ptr = '\\0';\n\tptr++;\n\n\tif( (int)ptr % 4 )\n\t\tmemset(ptr, 0, 4 - ((int)ptr % 4));\n\n\tptr++;\n\n\t/* Set new length */\n\theader->len = NVRAM_ROUNDUP(ptr - (char *) header, 4);\n\n\t/* Little-endian CRC8 over the last 11 bytes of the header */\n\ttmp.crc_ver_init   = header->crc_ver_init;\n\ttmp.config_refresh = header->config_refresh;\n\ttmp.config_ncdl    = header->config_ncdl;\n\tcrc = hndcrc8((unsigned char *) &tmp + NVRAM_CRC_START_POSITION,\n\t\tsizeof(nvram_header_t) - NVRAM_CRC_START_POSITION, 0xff);\n\n\t/* Continue CRC8 over data bytes */\n\tcrc = hndcrc8((unsigned char *) &header[0] + sizeof(nvram_header_t),\n\t\theader->len - sizeof(nvram_header_t), crc);\n\n\t/* Set new CRC8 */\n\theader->crc_ver_init |= crc;\n\n\t/* Write out */\n\tmsync(h->mmap, h->length, MS_SYNC);\n\tfsync(h->fd);\n\n\t/* Reinitialize hash table */\n\treturn _nvram_rehash(h);\n}\n\n/* Open NVRAM and obtain a handle. */\nnvram_handle_t * nvram_open(const char *file, int rdonly)\n{\n\tint i;\n\tint fd;\n\tchar *mtd = NULL;\n\tnvram_handle_t *h;\n\tnvram_header_t *header;\n\tint offset = -1;\n\n\t/* If erase size or file are undefined then try to define them */\n\tif( (nvram_part_size == 0) || (file == NULL) )\n\t{\n\t\t/* Finding the mtd will set the appropriate erase size */\n\t\tif( (mtd = nvram_find_mtd()) == NULL || nvram_part_size == 0 )\n\t\t{\n\t\t\tfree(mtd);\n\t\t\treturn NULL;\n\t\t}\n\t}\n\n\tif( (fd = open(file ? file : mtd, O_RDWR)) > -1 )\n\t{\n\t\tchar *mmap_area = (char *) mmap(\n\t\t\tNULL, nvram_part_size, PROT_READ | PROT_WRITE,\n\t\t\t(( rdonly == NVRAM_RO ) ? MAP_PRIVATE : MAP_SHARED) | MAP_LOCKED, fd, 0);\n\n\t\tif( mmap_area != MAP_FAILED )\n\t\t{\n\t\t\t/*\n\t\t\t * Start looking for NVRAM_MAGIC at beginning of MTD\n\t\t\t * partition. Stop if there is less than NVRAM_MIN_SPACE\n\t\t\t * to check, that was the lowest used size.\n\t\t\t */\n\t\t\tfor( i = 0; i <= ((nvram_part_size - NVRAM_MIN_SPACE) / sizeof(uint32_t)); i++ )\n\t\t\t{\n\t\t\t\tif( ((uint32_t *)mmap_area)[i] == NVRAM_MAGIC )\n\t\t\t\t{\n\t\t\t\t\toffset = i * sizeof(uint32_t);\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t}\n\n\t\t\tif( offset < 0 )\n\t\t\t{\n\t\t\t\tmunmap(mmap_area, nvram_part_size);\n\t\t\t\tfree(mtd);\n\t\t\t\tclose(fd);\n\t\t\t\treturn NULL;\n\t\t\t}\n\t\t\telse if( (h = malloc(sizeof(nvram_handle_t))) != NULL )\n\t\t\t{\n\t\t\t\tmemset(h, 0, sizeof(nvram_handle_t));\n\n\t\t\t\th->fd     = fd;\n\t\t\t\th->mmap   = mmap_area;\n\t\t\t\th->length = nvram_part_size;\n\t\t\t\th->offset = offset;\n\n\t\t\t\theader = nvram_header(h);\n\n\t\t\t\tif (header->magic == NVRAM_MAGIC &&\n\t\t\t\t    (rdonly || header->len < h->length - h->offset)) {\n\t\t\t\t\t_nvram_rehash(h);\n\t\t\t\t\tfree(mtd);\n\t\t\t\t\treturn h;\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\tmunmap(h->mmap, h->length);\n\t\t\t\t\tfree(h);\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n\n\tfree(mtd);\n\tclose(fd);\n\treturn NULL;\n}\n\n/* Close NVRAM and free memory. */\nint nvram_close(nvram_handle_t *h)\n{\n\t_nvram_free(h);\n\tmunmap(h->mmap, h->length);\n\tclose(h->fd);\n\tfree(h);\n\n\treturn 0;\n}\n\n/* Determine NVRAM device node. */\nchar * nvram_find_mtd(void)\n{\n\tFILE *fp;\n\tint i, part_size;\n\tchar dev[PATH_MAX];\n\tchar *path = NULL;\n\tstruct stat s;\n\n\tif ((fp = fopen(\"/proc/mtd\", \"r\")))\n\t{\n\t\twhile( fgets(dev, sizeof(dev), fp) )\n\t\t{\n\t\t\tif( strstr(dev, \"nvram\") && sscanf(dev, \"mtd%d: %08x\", &i, &part_size) )\n\t\t\t{\n\t\t\t\tnvram_part_size = part_size;\n\n\t\t\t\tsprintf(dev, \"/dev/mtdblock%d\", i);\n\t\t\t\tif( stat(dev, &s) > -1 && (s.st_mode & S_IFBLK) )\n\t\t\t\t{\n\t\t\t\t\tif( (path = (char *) malloc(strlen(dev)+1)) != NULL )\n\t\t\t\t\t{\n\t\t\t\t\t\tstrncpy(path, dev, strlen(dev)+1);\n\t\t\t\t\t\tbreak;\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t\tfclose(fp);\n\t}\n\n\treturn path;\n}\n\n/* Check NVRAM staging file. */\nchar * nvram_find_staging(void)\n{\n\tstruct stat s;\n\n\tif( (stat(NVRAM_STAGING, &s) > -1) && (s.st_mode & S_IFREG) )\n\t{\n\t\treturn NVRAM_STAGING;\n\t}\n\n\treturn NULL;\n}\n\n/* Copy NVRAM contents to staging file. */\nint nvram_to_staging(void)\n{\n\tint fdmtd, fdstg, stat;\n\tchar *mtd = nvram_find_mtd();\n\tchar buf[nvram_part_size];\n\n\tstat = -1;\n\n\tif( (mtd != NULL) && (nvram_part_size > 0) )\n\t{\n\t\tif( (fdmtd = open(mtd, O_RDONLY)) > -1 )\n\t\t{\n\t\t\tif( read(fdmtd, buf, sizeof(buf)) == sizeof(buf) )\n\t\t\t{\n\t\t\t\tif((fdstg = open(NVRAM_STAGING, O_WRONLY | O_CREAT, 0600)) > -1)\n\t\t\t\t{\n\t\t\t\t\twrite(fdstg, buf, sizeof(buf));\n\t\t\t\t\tfsync(fdstg);\n\t\t\t\t\tclose(fdstg);\n\n\t\t\t\t\tstat = 0;\n\t\t\t\t}\n\t\t\t}\n\n\t\t\tclose(fdmtd);\n\t\t}\n\t}\n\n\tfree(mtd);\n\treturn stat;\n}\n\n/* Copy staging file to NVRAM device. */\nint staging_to_nvram(void)\n{\n\tint fdmtd, fdstg, stat;\n\tchar *mtd = nvram_find_mtd();\n\tchar buf[nvram_part_size];\n\n\tstat = -1;\n\n\tif( (mtd != NULL) && (nvram_part_size > 0) )\n\t{\n\t\tif( (fdstg = open(NVRAM_STAGING, O_RDONLY)) > -1 )\n\t\t{\n\t\t\tif( read(fdstg, buf, sizeof(buf)) == sizeof(buf) )\n\t\t\t{\n\t\t\t\tif( (fdmtd = open(mtd, O_WRONLY | O_SYNC)) > -1 )\n\t\t\t\t{\n\t\t\t\t\twrite(fdmtd, buf, sizeof(buf));\n\t\t\t\t\tfsync(fdmtd);\n\t\t\t\t\tclose(fdmtd);\n\t\t\t\t\tstat = 0;\n\t\t\t\t}\n\t\t\t}\n\n\t\t\tclose(fdstg);\n\n\t\t\tif( !stat )\n\t\t\t\tstat = unlink(NVRAM_STAGING) ? 1 : 0;\n\t\t}\n\t}\n\n\tfree(mtd);\n\treturn stat;\n}\n"
  },
  {
    "path": "package/utils/nvram/src/nvram.h",
    "content": "/*\n * NVRAM variable manipulation\n *\n * Copyright 2007, Broadcom Corporation\n * Copyright 2009, OpenWrt.org\n * All Rights Reserved.\n *\n * THIS SOFTWARE IS OFFERED \"AS IS\", AND BROADCOM GRANTS NO WARRANTIES OF ANY\n * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM\n * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.\n *\n */\n\n#ifndef _nvram_h_\n#define _nvram_h_\n\n#include <stdint.h>\n#include <string.h>\n#include <stdio.h>\n#include <stdlib.h>\n#include <fcntl.h>\n#include <unistd.h>\n#include <errno.h>\n#include <sys/mman.h>\n#include <sys/stat.h>\n#include <linux/limits.h>\n\n#include \"sdinitvals.h\"\n\n\nstruct nvram_header {\n\tuint32_t magic;\n\tuint32_t len;\n\tuint32_t crc_ver_init;\t/* 0:7 crc, 8:15 ver, 16:31 sdram_init */\n\tuint32_t config_refresh;\t/* 0:15 sdram_config, 16:31 sdram_refresh */\n\tuint32_t config_ncdl;\t/* ncdl values for memc */\n} __attribute__((__packed__));\n\nstruct nvram_tuple {\n\tchar *name;\n\tchar *value;\n\tstruct nvram_tuple *next;\n};\n\nstruct nvram_handle {\n\tint fd;\n\tchar *mmap;\n\tunsigned int length;\n\tunsigned int offset;\n\tstruct nvram_tuple *nvram_hash[257];\n\tstruct nvram_tuple *nvram_dead;\n};\n\ntypedef struct nvram_handle nvram_handle_t;\ntypedef struct nvram_header nvram_header_t;\ntypedef struct nvram_tuple  nvram_tuple_t;\n\n\n/* Get nvram header. */\nnvram_header_t * nvram_header(nvram_handle_t *h);\n\n/* Set the value of an NVRAM variable */\nint nvram_set(nvram_handle_t *h, const char *name, const char *value);\n\n/* Get the value of an NVRAM variable. */\nchar * nvram_get(nvram_handle_t *h, const char *name);\n\n/* Unset the value of an NVRAM variable. */\nint nvram_unset(nvram_handle_t *h, const char *name);\n\n/* Get all NVRAM variables. */\nnvram_tuple_t * nvram_getall(nvram_handle_t *h);\n\n/* Regenerate NVRAM. */\nint nvram_commit(nvram_handle_t *h);\n\n/* Open NVRAM and obtain a handle. */\nnvram_handle_t * nvram_open(const char *file, int rdonly);\n\n/* Close NVRAM and free memory. */\nint nvram_close(nvram_handle_t *h);\n\n/* Get the value of an NVRAM variable in a safe way, use \"\" instead of NULL. */\n#define nvram_safe_get(h, name) (nvram_get(h, name) ? : \"\")\n\n/* Computes a crc8 over the input data. */\nuint8_t hndcrc8 (uint8_t * pdata, uint32_t nbytes, uint8_t crc);\n\n/* Returns the crc value of the nvram. */\nuint8_t nvram_calc_crc(nvram_header_t * nvh);\n\n/* Determine NVRAM device node. */\nchar * nvram_find_mtd(void);\n\n/* Copy NVRAM contents to staging file. */\nint nvram_to_staging(void);\n\n/* Copy staging file to NVRAM device. */\nint staging_to_nvram(void);\n\n/* Check NVRAM staging file. */\nchar * nvram_find_staging(void);\n\n\n/* Staging file for NVRAM */\n#define NVRAM_STAGING\t\t\"/tmp/.nvram\"\n#define NVRAM_RO\t\t\t1\n#define NVRAM_RW\t\t\t0\n\n/* Helper macros */\n#define NVRAM_ARRAYSIZE(a)\tsizeof(a)/sizeof(a[0])\n#define\tNVRAM_ROUNDUP(x, y)\t((((x)+((y)-1))/(y))*(y))\n\n/* NVRAM constants */\n#define NVRAM_MIN_SPACE\t\t\t0x8000\n#define NVRAM_MAGIC\t\t\t0x48534C46\t/* 'FLSH' */\n#define NVRAM_VERSION\t\t1\n\n#define NVRAM_CRC_START_POSITION\t9 /* magic, len, crc8 to be skipped */\n\n\n#endif /* _nvram_h_ */\n"
  },
  {
    "path": "package/utils/nvram/src/sdinitvals.h",
    "content": "/*\n * SDRAM init values\n *\n * Copyright 2007, Broadcom Corporation\n * Copyright 2009, OpenWrt.org\n * All Rights Reserved.\n *\n * THIS SOFTWARE IS OFFERED \"AS IS\", AND BROADCOM GRANTS NO WARRANTIES OF ANY\n * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM\n * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.\n *\n */\n\n#ifndef _sdinitvals_h_\n#define _sdinitvals_h_\n\n/* SDRAM refresh control (refresh) register bits */\n#define SDRAM_REF(p)    (((p)&0xff) | SDRAM_REF_EN)     /* Refresh period */\n#define SDRAM_REF_EN    0x8000          /* Writing 1 enables periodic refresh */\n\n/* SDRAM Core default Init values (OCP ID 0x803) */\n#define MEM4MX16X2      0x419   /* 16 MB */\n\n#define SDRAM_INIT\tMEM4MX16X2\n#define SDRAM_BURSTFULL 0x0000  /* Use full page bursts */\n#define SDRAM_CONFIG    SDRAM_BURSTFULL\n#define SDRAM_REFRESH   SDRAM_REF(0x40)\n\n#endif /* _sdinitvals_h_ */\n"
  },
  {
    "path": "package/utils/osafeloader/Makefile",
    "content": "#\n# Copyright (C) 2016 Rafał Miłecki <rafal@milecki.pl>\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=osafeloader\nPKG_RELEASE:=1\n\nPKG_FLAGS:=nonshared\n\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine Package/osafeloader\n  SECTION:=utils\n  CATEGORY:=Base system\n  TITLE:=Utility for handling TP-LINK SafeLoader images\n  MAINTAINER:=Rafał Miłecki <rafal@milecki.pl>\n  DEPENDS:=@TARGET_bcm53xx\nendef\n\ndefine Package/osafeloader/description\n This package contains an utility that allows handling SafeLoader images.\nendef\n\ndefine Build/Compile\n\t$(MAKE) -C $(PKG_BUILD_DIR) \\\n\t\tCC=\"$(TARGET_CC)\" \\\n\t\tCFLAGS=\"$(TARGET_CFLAGS) -Wall\"\nendef\n\ndefine Package/osafeloader/install\n\t$(INSTALL_DIR) $(1)/usr/bin\n\t$(INSTALL_BIN) $(PKG_BUILD_DIR)/osafeloader $(1)/usr/bin/\nendef\n\n$(eval $(call BuildPackage,osafeloader))\n"
  },
  {
    "path": "package/utils/osafeloader/src/Makefile",
    "content": "all: osafeloader\n\nosafeloader:\n\t$(CC) $(CFLAGS) -Wall osafeloader.c md5.c -o $@ $^\n\nclean:\n\trm -f osafeloader\n"
  },
  {
    "path": "package/utils/osafeloader/src/md5.c",
    "content": "/*\n * This is an OpenSSL-compatible implementation of the RSA Data Security, Inc.\n * MD5 Message-Digest Algorithm (RFC 1321).\n *\n * Homepage:\n * http://openwall.info/wiki/people/solar/software/public-domain-source-code/md5\n *\n * Author:\n * Alexander Peslyak, better known as Solar Designer <solar at openwall.com>\n *\n * This software was written by Alexander Peslyak in 2001.  No copyright is\n * claimed, and the software is hereby placed in the public domain.\n * In case this attempt to disclaim copyright and place the software in the\n * public domain is deemed null and void, then the software is\n * Copyright (c) 2001 Alexander Peslyak and it is hereby released to the\n * general public under the following terms:\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted.\n *\n * There's ABSOLUTELY NO WARRANTY, express or implied.\n *\n * (This is a heavily cut-down \"BSD license\".)\n *\n * This differs from Colin Plumb's older public domain implementation in that\n * no exactly 32-bit integer data type is required (any 32-bit or wider\n * unsigned integer data type will do), there's no compile-time endianness\n * configuration, and the function prototypes match OpenSSL's.  No code from\n * Colin Plumb's implementation has been reused; this comment merely compares\n * the properties of the two independent implementations.\n *\n * The primary goals of this implementation are portability and ease of use.\n * It is meant to be fast, but not as fast as possible.  Some known\n * optimizations are not included to reduce source code size and avoid\n * compile-time configuration.\n */\n\n#ifndef HAVE_OPENSSL\n\n#include <string.h>\n\n#include \"md5.h\"\n\n/*\n * The basic MD5 functions.\n *\n * F and G are optimized compared to their RFC 1321 definitions for\n * architectures that lack an AND-NOT instruction, just like in Colin Plumb's\n * implementation.\n */\n#define F(x, y, z)\t\t\t((z) ^ ((x) & ((y) ^ (z))))\n#define G(x, y, z)\t\t\t((y) ^ ((z) & ((x) ^ (y))))\n#define H(x, y, z)\t\t\t(((x) ^ (y)) ^ (z))\n#define H2(x, y, z)\t\t\t((x) ^ ((y) ^ (z)))\n#define I(x, y, z)\t\t\t((y) ^ ((x) | ~(z)))\n\n/*\n * The MD5 transformation for all four rounds.\n */\n#define STEP(f, a, b, c, d, x, t, s) \\\n\t(a) += f((b), (c), (d)) + (x) + (t); \\\n\t(a) = (((a) << (s)) | (((a) & 0xffffffff) >> (32 - (s)))); \\\n\t(a) += (b);\n\n/*\n * SET reads 4 input bytes in little-endian byte order and stores them\n * in a properly aligned word in host byte order.\n *\n * The check for little-endian architectures that tolerate unaligned\n * memory accesses is just an optimization.  Nothing will break if it\n * doesn't work.\n */\n#if defined(__i386__) || defined(__x86_64__) || defined(__vax__)\n#define SET(n) \\\n\t(*(MD5_u32plus *)&ptr[(n) * 4])\n#define GET(n) \\\n\tSET(n)\n#else\n#define SET(n) \\\n\t(ctx->block[(n)] = \\\n\t(MD5_u32plus)ptr[(n) * 4] | \\\n\t((MD5_u32plus)ptr[(n) * 4 + 1] << 8) | \\\n\t((MD5_u32plus)ptr[(n) * 4 + 2] << 16) | \\\n\t((MD5_u32plus)ptr[(n) * 4 + 3] << 24))\n#define GET(n) \\\n\t(ctx->block[(n)])\n#endif\n\n/*\n * This processes one or more 64-byte data blocks, but does NOT update\n * the bit counters.  There are no alignment requirements.\n */\nstatic const void *body(MD5_CTX *ctx, const void *data, unsigned long size)\n{\n\tconst unsigned char *ptr;\n\tMD5_u32plus a, b, c, d;\n\tMD5_u32plus saved_a, saved_b, saved_c, saved_d;\n\n\tptr = (const unsigned char *)data;\n\n\ta = ctx->a;\n\tb = ctx->b;\n\tc = ctx->c;\n\td = ctx->d;\n\n\tdo {\n\t\tsaved_a = a;\n\t\tsaved_b = b;\n\t\tsaved_c = c;\n\t\tsaved_d = d;\n\n/* Round 1 */\n\t\tSTEP(F, a, b, c, d, SET(0), 0xd76aa478, 7)\n\t\tSTEP(F, d, a, b, c, SET(1), 0xe8c7b756, 12)\n\t\tSTEP(F, c, d, a, b, SET(2), 0x242070db, 17)\n\t\tSTEP(F, b, c, d, a, SET(3), 0xc1bdceee, 22)\n\t\tSTEP(F, a, b, c, d, SET(4), 0xf57c0faf, 7)\n\t\tSTEP(F, d, a, b, c, SET(5), 0x4787c62a, 12)\n\t\tSTEP(F, c, d, a, b, SET(6), 0xa8304613, 17)\n\t\tSTEP(F, b, c, d, a, SET(7), 0xfd469501, 22)\n\t\tSTEP(F, a, b, c, d, SET(8), 0x698098d8, 7)\n\t\tSTEP(F, d, a, b, c, SET(9), 0x8b44f7af, 12)\n\t\tSTEP(F, c, d, a, b, SET(10), 0xffff5bb1, 17)\n\t\tSTEP(F, b, c, d, a, SET(11), 0x895cd7be, 22)\n\t\tSTEP(F, a, b, c, d, SET(12), 0x6b901122, 7)\n\t\tSTEP(F, d, a, b, c, SET(13), 0xfd987193, 12)\n\t\tSTEP(F, c, d, a, b, SET(14), 0xa679438e, 17)\n\t\tSTEP(F, b, c, d, a, SET(15), 0x49b40821, 22)\n\n/* Round 2 */\n\t\tSTEP(G, a, b, c, d, GET(1), 0xf61e2562, 5)\n\t\tSTEP(G, d, a, b, c, GET(6), 0xc040b340, 9)\n\t\tSTEP(G, c, d, a, b, GET(11), 0x265e5a51, 14)\n\t\tSTEP(G, b, c, d, a, GET(0), 0xe9b6c7aa, 20)\n\t\tSTEP(G, a, b, c, d, GET(5), 0xd62f105d, 5)\n\t\tSTEP(G, d, a, b, c, GET(10), 0x02441453, 9)\n\t\tSTEP(G, c, d, a, b, GET(15), 0xd8a1e681, 14)\n\t\tSTEP(G, b, c, d, a, GET(4), 0xe7d3fbc8, 20)\n\t\tSTEP(G, a, b, c, d, GET(9), 0x21e1cde6, 5)\n\t\tSTEP(G, d, a, b, c, GET(14), 0xc33707d6, 9)\n\t\tSTEP(G, c, d, a, b, GET(3), 0xf4d50d87, 14)\n\t\tSTEP(G, b, c, d, a, GET(8), 0x455a14ed, 20)\n\t\tSTEP(G, a, b, c, d, GET(13), 0xa9e3e905, 5)\n\t\tSTEP(G, d, a, b, c, GET(2), 0xfcefa3f8, 9)\n\t\tSTEP(G, c, d, a, b, GET(7), 0x676f02d9, 14)\n\t\tSTEP(G, b, c, d, a, GET(12), 0x8d2a4c8a, 20)\n\n/* Round 3 */\n\t\tSTEP(H, a, b, c, d, GET(5), 0xfffa3942, 4)\n\t\tSTEP(H2, d, a, b, c, GET(8), 0x8771f681, 11)\n\t\tSTEP(H, c, d, a, b, GET(11), 0x6d9d6122, 16)\n\t\tSTEP(H2, b, c, d, a, GET(14), 0xfde5380c, 23)\n\t\tSTEP(H, a, b, c, d, GET(1), 0xa4beea44, 4)\n\t\tSTEP(H2, d, a, b, c, GET(4), 0x4bdecfa9, 11)\n\t\tSTEP(H, c, d, a, b, GET(7), 0xf6bb4b60, 16)\n\t\tSTEP(H2, b, c, d, a, GET(10), 0xbebfbc70, 23)\n\t\tSTEP(H, a, b, c, d, GET(13), 0x289b7ec6, 4)\n\t\tSTEP(H2, d, a, b, c, GET(0), 0xeaa127fa, 11)\n\t\tSTEP(H, c, d, a, b, GET(3), 0xd4ef3085, 16)\n\t\tSTEP(H2, b, c, d, a, GET(6), 0x04881d05, 23)\n\t\tSTEP(H, a, b, c, d, GET(9), 0xd9d4d039, 4)\n\t\tSTEP(H2, d, a, b, c, GET(12), 0xe6db99e5, 11)\n\t\tSTEP(H, c, d, a, b, GET(15), 0x1fa27cf8, 16)\n\t\tSTEP(H2, b, c, d, a, GET(2), 0xc4ac5665, 23)\n\n/* Round 4 */\n\t\tSTEP(I, a, b, c, d, GET(0), 0xf4292244, 6)\n\t\tSTEP(I, d, a, b, c, GET(7), 0x432aff97, 10)\n\t\tSTEP(I, c, d, a, b, GET(14), 0xab9423a7, 15)\n\t\tSTEP(I, b, c, d, a, GET(5), 0xfc93a039, 21)\n\t\tSTEP(I, a, b, c, d, GET(12), 0x655b59c3, 6)\n\t\tSTEP(I, d, a, b, c, GET(3), 0x8f0ccc92, 10)\n\t\tSTEP(I, c, d, a, b, GET(10), 0xffeff47d, 15)\n\t\tSTEP(I, b, c, d, a, GET(1), 0x85845dd1, 21)\n\t\tSTEP(I, a, b, c, d, GET(8), 0x6fa87e4f, 6)\n\t\tSTEP(I, d, a, b, c, GET(15), 0xfe2ce6e0, 10)\n\t\tSTEP(I, c, d, a, b, GET(6), 0xa3014314, 15)\n\t\tSTEP(I, b, c, d, a, GET(13), 0x4e0811a1, 21)\n\t\tSTEP(I, a, b, c, d, GET(4), 0xf7537e82, 6)\n\t\tSTEP(I, d, a, b, c, GET(11), 0xbd3af235, 10)\n\t\tSTEP(I, c, d, a, b, GET(2), 0x2ad7d2bb, 15)\n\t\tSTEP(I, b, c, d, a, GET(9), 0xeb86d391, 21)\n\n\t\ta += saved_a;\n\t\tb += saved_b;\n\t\tc += saved_c;\n\t\td += saved_d;\n\n\t\tptr += 64;\n\t} while (size -= 64);\n\n\tctx->a = a;\n\tctx->b = b;\n\tctx->c = c;\n\tctx->d = d;\n\n\treturn ptr;\n}\n\nvoid MD5_Init(MD5_CTX *ctx)\n{\n\tctx->a = 0x67452301;\n\tctx->b = 0xefcdab89;\n\tctx->c = 0x98badcfe;\n\tctx->d = 0x10325476;\n\n\tctx->lo = 0;\n\tctx->hi = 0;\n}\n\nvoid MD5_Update(MD5_CTX *ctx, const void *data, unsigned long size)\n{\n\tMD5_u32plus saved_lo;\n\tunsigned long used, available;\n\n\tsaved_lo = ctx->lo;\n\tif ((ctx->lo = (saved_lo + size) & 0x1fffffff) < saved_lo)\n\t\tctx->hi++;\n\tctx->hi += size >> 29;\n\n\tused = saved_lo & 0x3f;\n\n\tif (used) {\n\t\tavailable = 64 - used;\n\n\t\tif (size < available) {\n\t\t\tmemcpy(&ctx->buffer[used], data, size);\n\t\t\treturn;\n\t\t}\n\n\t\tmemcpy(&ctx->buffer[used], data, available);\n\t\tdata = (const unsigned char *)data + available;\n\t\tsize -= available;\n\t\tbody(ctx, ctx->buffer, 64);\n\t}\n\n\tif (size >= 64) {\n\t\tdata = body(ctx, data, size & ~(unsigned long)0x3f);\n\t\tsize &= 0x3f;\n\t}\n\n\tmemcpy(ctx->buffer, data, size);\n}\n\nvoid MD5_Final(unsigned char *result, MD5_CTX *ctx)\n{\n\tunsigned long used, available;\n\n\tused = ctx->lo & 0x3f;\n\n\tctx->buffer[used++] = 0x80;\n\n\tavailable = 64 - used;\n\n\tif (available < 8) {\n\t\tmemset(&ctx->buffer[used], 0, available);\n\t\tbody(ctx, ctx->buffer, 64);\n\t\tused = 0;\n\t\tavailable = 64;\n\t}\n\n\tmemset(&ctx->buffer[used], 0, available - 8);\n\n\tctx->lo <<= 3;\n\tctx->buffer[56] = ctx->lo;\n\tctx->buffer[57] = ctx->lo >> 8;\n\tctx->buffer[58] = ctx->lo >> 16;\n\tctx->buffer[59] = ctx->lo >> 24;\n\tctx->buffer[60] = ctx->hi;\n\tctx->buffer[61] = ctx->hi >> 8;\n\tctx->buffer[62] = ctx->hi >> 16;\n\tctx->buffer[63] = ctx->hi >> 24;\n\n\tbody(ctx, ctx->buffer, 64);\n\n\tresult[0] = ctx->a;\n\tresult[1] = ctx->a >> 8;\n\tresult[2] = ctx->a >> 16;\n\tresult[3] = ctx->a >> 24;\n\tresult[4] = ctx->b;\n\tresult[5] = ctx->b >> 8;\n\tresult[6] = ctx->b >> 16;\n\tresult[7] = ctx->b >> 24;\n\tresult[8] = ctx->c;\n\tresult[9] = ctx->c >> 8;\n\tresult[10] = ctx->c >> 16;\n\tresult[11] = ctx->c >> 24;\n\tresult[12] = ctx->d;\n\tresult[13] = ctx->d >> 8;\n\tresult[14] = ctx->d >> 16;\n\tresult[15] = ctx->d >> 24;\n\n\tmemset(ctx, 0, sizeof(*ctx));\n}\n\n#endif\n"
  },
  {
    "path": "package/utils/osafeloader/src/md5.h",
    "content": "/*\n * This is an OpenSSL-compatible implementation of the RSA Data Security, Inc.\n * MD5 Message-Digest Algorithm (RFC 1321).\n *\n * Homepage:\n * http://openwall.info/wiki/people/solar/software/public-domain-source-code/md5\n *\n * Author:\n * Alexander Peslyak, better known as Solar Designer <solar at openwall.com>\n *\n * This software was written by Alexander Peslyak in 2001.  No copyright is\n * claimed, and the software is hereby placed in the public domain.\n * In case this attempt to disclaim copyright and place the software in the\n * public domain is deemed null and void, then the software is\n * Copyright (c) 2001 Alexander Peslyak and it is hereby released to the\n * general public under the following terms:\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted.\n *\n * There's ABSOLUTELY NO WARRANTY, express or implied.\n *\n * See md5.c for more information.\n */\n\n#ifdef HAVE_OPENSSL\n#include <openssl/md5.h>\n#elif !defined(_MD5_H)\n#define _MD5_H\n\n/* Any 32-bit or wider unsigned integer data type will do */\ntypedef unsigned int MD5_u32plus;\n\ntypedef struct {\n\tMD5_u32plus lo, hi;\n\tMD5_u32plus a, b, c, d;\n\tunsigned char buffer[64];\n\tMD5_u32plus block[16];\n} MD5_CTX;\n\nextern void MD5_Init(MD5_CTX *ctx);\nextern void MD5_Update(MD5_CTX *ctx, const void *data, unsigned long size);\nextern void MD5_Final(unsigned char *result, MD5_CTX *ctx);\n\n#endif\n"
  },
  {
    "path": "package/utils/osafeloader/src/osafeloader.c",
    "content": "/*\n * osafeloader\n *\n * Copyright (C) 2016 Rafał Miłecki <zajec5@gmail.com>\n *\n * This program is free software; you can redistribute it and/or modify\n * it under the terms of the GNU General Public License version 2 as\n * published by the Free Software Foundation.\n */\n\n#include <byteswap.h>\n#include <endian.h>\n#include <errno.h>\n#include <stdint.h>\n#include <stdio.h>\n#include <stdlib.h>\n#include <string.h>\n#include <unistd.h>\n\n#include \"md5.h\"\n\n#if !defined(__BYTE_ORDER)\n#error \"Unknown byte order\"\n#endif\n\n#if __BYTE_ORDER == __BIG_ENDIAN\n#define cpu_to_be32(x)\t(x)\n#define be32_to_cpu(x)\t(x)\n#define cpu_to_be16(x)\t(x)\n#define be16_to_cpu(x)\t(x)\n#elif __BYTE_ORDER == __LITTLE_ENDIAN\n#define cpu_to_be32(x)\tbswap_32(x)\n#define be32_to_cpu(x)\tbswap_32(x)\n#define cpu_to_be16(x)\tbswap_16(x)\n#define be16_to_cpu(x)\tbswap_16(x)\n#else\n#error \"Unsupported endianness\"\n#endif\n\nstruct safeloader_header {\n\tuint32_t imagesize;\n\tuint8_t md5[16];\n} __attribute__ ((packed));\n\nchar *safeloader_path;\nchar *partition_name;\nchar *out_path;\n\nstatic inline size_t osafeloader_min(size_t x, size_t y) {\n\treturn x < y ? x : y;\n}\n\nstatic const uint8_t md5_salt[16] = {\n\t0x7a, 0x2b, 0x15, 0xed,\n\t0x9b, 0x98, 0x59, 0x6d,\n\t0xe5, 0x04, 0xab, 0x44,\n\t0xac, 0x2a, 0x9f, 0x4e,\n};\n\n/**************************************************\n * Info\n **************************************************/\n\nstatic int osafeloader_info(int argc, char **argv) {\n\tFILE *safeloader;\n\tstruct safeloader_header hdr;\n\tMD5_CTX ctx;\n\tsize_t bytes, imagesize;\n\tuint8_t buf[1024];\n\tuint8_t md5[16];\n\tchar name[32];\n\tint base, size, i;\n\tint err = 0;\n\n\tif (argc < 3) {\n\t\tfprintf(stderr, \"No SafeLoader file passed\\n\");\n\t\terr = -EINVAL;\n\t\tgoto out;\n\t}\n\tsafeloader_path = argv[2];\n\n\tsafeloader = fopen(safeloader_path, \"r\");\n\tif (!safeloader) {\n\t\tfprintf(stderr, \"Couldn't open %s\\n\", safeloader_path);\n\t\terr = -EACCES;\n\t\tgoto out;\n\t}\n\n\tbytes = fread(&hdr, 1, sizeof(hdr), safeloader);\n\tif (bytes != sizeof(hdr)) {\n\t\tfprintf(stderr, \"Couldn't read %s header\\n\", safeloader_path);\n\t\terr =  -EIO;\n\t\tgoto err_close;\n\t}\n\timagesize = be32_to_cpu(hdr.imagesize);\n\n\tMD5_Init(&ctx);\n\tMD5_Update(&ctx, md5_salt, sizeof(md5_salt));\n\twhile ((bytes = fread(buf, 1, osafeloader_min(sizeof(buf), imagesize), safeloader)) > 0) {\n\t\tMD5_Update(&ctx, buf, bytes);\n\t\timagesize -= bytes;\n\t}\n\tMD5_Final(md5, &ctx);\n\n\tif (memcmp(md5, hdr.md5, 16)) {\n\t\tfprintf(stderr, \"Broken SafeLoader file with invalid MD5\\n\");\n\t\terr =  -EIO;\n\t\tgoto err_close;\n\t}\n\n\tprintf(\"%10s: %d\\n\", \"Image size\", be32_to_cpu(hdr.imagesize));\n\tprintf(\"%10s: \", \"MD5\");\n\tfor (i = 0; i < 16; i++)\n\t\tprintf(\"%02x\", md5[i]);\n\tprintf(\"\\n\");\n\n\t/* Skip header & vendor info */\n\tfseek(safeloader, 0x1014, SEEK_SET);\n\n\twhile (fscanf(safeloader, \"fwup-ptn %s base 0x%x size 0x%x\\t\\r\\n\", name, &base, &size) == 3) {\n\t\tprintf(\"%10s: %s (0x%x - 0x%x)\\n\", \"Partition\", name, base, base + size);\n\t}\n\nerr_close:\n\tfclose(safeloader);\nout:\n\treturn err;\n}\n\n/**************************************************\n * Extract\n **************************************************/\n\nstatic void osafeloader_extract_parse_options(int argc, char **argv) {\n\tint c;\n\n\twhile ((c = getopt(argc, argv, \"p:o:\")) != -1) {\n\t\tswitch (c) {\n\t\tcase 'p':\n\t\t\tpartition_name = optarg;\n\t\t\tbreak;\n\t\tcase 'o':\n\t\t\tout_path = optarg;\n\t\t\tbreak;\n\t\t}\n\t}\n}\n\nstatic int osafeloader_extract(int argc, char **argv) {\n\tFILE *safeloader;\n\tFILE *out;\n\tstruct safeloader_header hdr;\n\tsize_t bytes;\n\tchar name[32];\n\tint base, size;\n\tint err = 0;\n\n\tif (argc < 3) {\n\t\tfprintf(stderr, \"No SafeLoader file passed\\n\");\n\t\terr = -EINVAL;\n\t\tgoto out;\n\t}\n\tsafeloader_path = argv[2];\n\n\toptind = 3;\n\tosafeloader_extract_parse_options(argc, argv);\n\tif (!partition_name) {\n\t\tfprintf(stderr, \"No partition name specified\\n\");\n\t\terr = -EINVAL;\n\t\tgoto out;\n\t} else if (!out_path) {\n\t\tfprintf(stderr, \"No output file specified\\n\");\n\t\terr = -EINVAL;\n\t\tgoto out;\n\t}\n\n\tsafeloader = fopen(safeloader_path, \"r\");\n\tif (!safeloader) {\n\t\tfprintf(stderr, \"Couldn't open %s\\n\", safeloader_path);\n\t\terr = -EACCES;\n\t\tgoto out;\n\t}\n\n\tout = fopen(out_path, \"w\");\n\tif (!out) {\n\t\tfprintf(stderr, \"Couldn't open %s\\n\", out_path);\n\t\terr = -EACCES;\n\t\tgoto err_close_safeloader;\n\t}\n\n\tbytes = fread(&hdr, 1, sizeof(hdr), safeloader);\n\tif (bytes != sizeof(hdr)) {\n\t\tfprintf(stderr, \"Couldn't read %s header\\n\", safeloader_path);\n\t\terr =  -EIO;\n\t\tgoto err_close_out;\n\t}\n\n\t/* Skip vendor info */\n\tfseek(safeloader, 0x1000, SEEK_CUR);\n\n\terr = -ENOENT;\n\twhile (fscanf(safeloader, \"fwup-ptn %s base 0x%x size 0x%x\\t\\r\\n\", name, &base, &size) == 3) {\n\t\tuint8_t buf[1024];\n\n\t\tif (strcmp(name, partition_name))\n\t\t\tcontinue;\n\n\t\terr = 0;\n\n\t\tfseek(safeloader, sizeof(hdr) + 0x1000 + base, SEEK_SET);\n\n\t\twhile ((bytes = fread(buf, 1, osafeloader_min(sizeof(buf), size), safeloader)) > 0) {\n\t\t\tif (fwrite(buf, 1, bytes, out) != bytes) {\n\t\t\t\tfprintf(stderr, \"Couldn't write %zu B to %s\\n\", bytes, out_path);\n\t\t\t\terr = -EIO;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\tsize -= bytes;\n\t\t}\n\n\t\tif (size) {\n\t\t\tfprintf(stderr, \"Couldn't extract whole partition %s from %s (%d B left)\\n\", partition_name, safeloader_path, size);\n\t\t\terr = -EIO;\n\t\t}\n\n\t\tbreak;\n\t}\n\nerr_close_out:\n\tfclose(out);\nerr_close_safeloader:\n\tfclose(safeloader);\nout:\n\treturn err;\n}\n\n/**************************************************\n * Start\n **************************************************/\n\nstatic void usage() {\n\tprintf(\"Usage:\\n\");\n\tprintf(\"\\n\");\n\tprintf(\"Info about SafeLoader:\\n\");\n\tprintf(\"\\tosafeloader info <file>\\n\");\n\tprintf(\"\\n\");\n\tprintf(\"Extract from SafeLoader:\\n\");\n\tprintf(\"\\tosafeloader extract <file> [options]\\n\");\n\tprintf(\"\\t-p name\\t\\t\\t\\tname of partition to extract\\n\");\n\tprintf(\"\\t-o file\\t\\t\\t\\toutput file\\n\");\n}\n\nint main(int argc, char **argv) {\n\tif (argc > 1) {\n\t\tif (!strcmp(argv[1], \"info\"))\n\t\t\treturn osafeloader_info(argc, argv);\n\t\telse if (!strcmp(argv[1], \"extract\"))\n\t\t\treturn osafeloader_extract(argc, argv);\n\t}\n\n\tusage();\n\treturn 0;\n}\n"
  },
  {
    "path": "package/utils/oseama/Makefile",
    "content": "#\n# Copyright (C) 2016 Rafał Miłecki <zajec5@gmail.com>\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=oseama\nPKG_RELEASE:=1\n\nPKG_FLAGS:=nonshared\n\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine Package/oseama\n  SECTION:=utils\n  CATEGORY:=Base system\n  TITLE:=Utility for handling Seama firmware images\n  MAINTAINER:=Rafał Miłecki <zajec5@gmail.com>\n  DEPENDS:=@TARGET_bcm53xx\nendef\n\ndefine Package/oseama/description\n This package contains an utility that allows handling Seama images.\nendef\n\ndefine Build/Compile\n\t$(MAKE) -C $(PKG_BUILD_DIR) \\\n\t\tCC=\"$(TARGET_CC)\" \\\n\t\tCFLAGS=\"$(TARGET_CFLAGS) -Wall\"\nendef\n\ndefine Package/oseama/install\n\t$(INSTALL_DIR) $(1)/usr/bin\n\t$(INSTALL_BIN) $(PKG_BUILD_DIR)/oseama $(1)/usr/bin/\nendef\n\n$(eval $(call BuildPackage,oseama))\n"
  },
  {
    "path": "package/utils/oseama/src/Makefile",
    "content": "all: oseama\n\noseama:\n\t$(CC) $(CFLAGS) -Wall oseama.c md5.c -o $@ $^\n\nclean:\n\trm -f oseama\n"
  },
  {
    "path": "package/utils/oseama/src/md5.c",
    "content": "/*\n * This is an OpenSSL-compatible implementation of the RSA Data Security, Inc.\n * MD5 Message-Digest Algorithm (RFC 1321).\n *\n * Homepage:\n * http://openwall.info/wiki/people/solar/software/public-domain-source-code/md5\n *\n * Author:\n * Alexander Peslyak, better known as Solar Designer <solar at openwall.com>\n *\n * This software was written by Alexander Peslyak in 2001.  No copyright is\n * claimed, and the software is hereby placed in the public domain.\n * In case this attempt to disclaim copyright and place the software in the\n * public domain is deemed null and void, then the software is\n * Copyright (c) 2001 Alexander Peslyak and it is hereby released to the\n * general public under the following terms:\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted.\n *\n * There's ABSOLUTELY NO WARRANTY, express or implied.\n *\n * (This is a heavily cut-down \"BSD license\".)\n *\n * This differs from Colin Plumb's older public domain implementation in that\n * no exactly 32-bit integer data type is required (any 32-bit or wider\n * unsigned integer data type will do), there's no compile-time endianness\n * configuration, and the function prototypes match OpenSSL's.  No code from\n * Colin Plumb's implementation has been reused; this comment merely compares\n * the properties of the two independent implementations.\n *\n * The primary goals of this implementation are portability and ease of use.\n * It is meant to be fast, but not as fast as possible.  Some known\n * optimizations are not included to reduce source code size and avoid\n * compile-time configuration.\n */\n\n#ifndef HAVE_OPENSSL\n\n#include <string.h>\n\n#include \"md5.h\"\n\n/*\n * The basic MD5 functions.\n *\n * F and G are optimized compared to their RFC 1321 definitions for\n * architectures that lack an AND-NOT instruction, just like in Colin Plumb's\n * implementation.\n */\n#define F(x, y, z)\t\t\t((z) ^ ((x) & ((y) ^ (z))))\n#define G(x, y, z)\t\t\t((y) ^ ((z) & ((x) ^ (y))))\n#define H(x, y, z)\t\t\t(((x) ^ (y)) ^ (z))\n#define H2(x, y, z)\t\t\t((x) ^ ((y) ^ (z)))\n#define I(x, y, z)\t\t\t((y) ^ ((x) | ~(z)))\n\n/*\n * The MD5 transformation for all four rounds.\n */\n#define STEP(f, a, b, c, d, x, t, s) \\\n\t(a) += f((b), (c), (d)) + (x) + (t); \\\n\t(a) = (((a) << (s)) | (((a) & 0xffffffff) >> (32 - (s)))); \\\n\t(a) += (b);\n\n/*\n * SET reads 4 input bytes in little-endian byte order and stores them\n * in a properly aligned word in host byte order.\n *\n * The check for little-endian architectures that tolerate unaligned\n * memory accesses is just an optimization.  Nothing will break if it\n * doesn't work.\n */\n#if defined(__i386__) || defined(__x86_64__) || defined(__vax__)\n#define SET(n) \\\n\t(*(MD5_u32plus *)&ptr[(n) * 4])\n#define GET(n) \\\n\tSET(n)\n#else\n#define SET(n) \\\n\t(ctx->block[(n)] = \\\n\t(MD5_u32plus)ptr[(n) * 4] | \\\n\t((MD5_u32plus)ptr[(n) * 4 + 1] << 8) | \\\n\t((MD5_u32plus)ptr[(n) * 4 + 2] << 16) | \\\n\t((MD5_u32plus)ptr[(n) * 4 + 3] << 24))\n#define GET(n) \\\n\t(ctx->block[(n)])\n#endif\n\n/*\n * This processes one or more 64-byte data blocks, but does NOT update\n * the bit counters.  There are no alignment requirements.\n */\nstatic const void *body(MD5_CTX *ctx, const void *data, unsigned long size)\n{\n\tconst unsigned char *ptr;\n\tMD5_u32plus a, b, c, d;\n\tMD5_u32plus saved_a, saved_b, saved_c, saved_d;\n\n\tptr = (const unsigned char *)data;\n\n\ta = ctx->a;\n\tb = ctx->b;\n\tc = ctx->c;\n\td = ctx->d;\n\n\tdo {\n\t\tsaved_a = a;\n\t\tsaved_b = b;\n\t\tsaved_c = c;\n\t\tsaved_d = d;\n\n/* Round 1 */\n\t\tSTEP(F, a, b, c, d, SET(0), 0xd76aa478, 7)\n\t\tSTEP(F, d, a, b, c, SET(1), 0xe8c7b756, 12)\n\t\tSTEP(F, c, d, a, b, SET(2), 0x242070db, 17)\n\t\tSTEP(F, b, c, d, a, SET(3), 0xc1bdceee, 22)\n\t\tSTEP(F, a, b, c, d, SET(4), 0xf57c0faf, 7)\n\t\tSTEP(F, d, a, b, c, SET(5), 0x4787c62a, 12)\n\t\tSTEP(F, c, d, a, b, SET(6), 0xa8304613, 17)\n\t\tSTEP(F, b, c, d, a, SET(7), 0xfd469501, 22)\n\t\tSTEP(F, a, b, c, d, SET(8), 0x698098d8, 7)\n\t\tSTEP(F, d, a, b, c, SET(9), 0x8b44f7af, 12)\n\t\tSTEP(F, c, d, a, b, SET(10), 0xffff5bb1, 17)\n\t\tSTEP(F, b, c, d, a, SET(11), 0x895cd7be, 22)\n\t\tSTEP(F, a, b, c, d, SET(12), 0x6b901122, 7)\n\t\tSTEP(F, d, a, b, c, SET(13), 0xfd987193, 12)\n\t\tSTEP(F, c, d, a, b, SET(14), 0xa679438e, 17)\n\t\tSTEP(F, b, c, d, a, SET(15), 0x49b40821, 22)\n\n/* Round 2 */\n\t\tSTEP(G, a, b, c, d, GET(1), 0xf61e2562, 5)\n\t\tSTEP(G, d, a, b, c, GET(6), 0xc040b340, 9)\n\t\tSTEP(G, c, d, a, b, GET(11), 0x265e5a51, 14)\n\t\tSTEP(G, b, c, d, a, GET(0), 0xe9b6c7aa, 20)\n\t\tSTEP(G, a, b, c, d, GET(5), 0xd62f105d, 5)\n\t\tSTEP(G, d, a, b, c, GET(10), 0x02441453, 9)\n\t\tSTEP(G, c, d, a, b, GET(15), 0xd8a1e681, 14)\n\t\tSTEP(G, b, c, d, a, GET(4), 0xe7d3fbc8, 20)\n\t\tSTEP(G, a, b, c, d, GET(9), 0x21e1cde6, 5)\n\t\tSTEP(G, d, a, b, c, GET(14), 0xc33707d6, 9)\n\t\tSTEP(G, c, d, a, b, GET(3), 0xf4d50d87, 14)\n\t\tSTEP(G, b, c, d, a, GET(8), 0x455a14ed, 20)\n\t\tSTEP(G, a, b, c, d, GET(13), 0xa9e3e905, 5)\n\t\tSTEP(G, d, a, b, c, GET(2), 0xfcefa3f8, 9)\n\t\tSTEP(G, c, d, a, b, GET(7), 0x676f02d9, 14)\n\t\tSTEP(G, b, c, d, a, GET(12), 0x8d2a4c8a, 20)\n\n/* Round 3 */\n\t\tSTEP(H, a, b, c, d, GET(5), 0xfffa3942, 4)\n\t\tSTEP(H2, d, a, b, c, GET(8), 0x8771f681, 11)\n\t\tSTEP(H, c, d, a, b, GET(11), 0x6d9d6122, 16)\n\t\tSTEP(H2, b, c, d, a, GET(14), 0xfde5380c, 23)\n\t\tSTEP(H, a, b, c, d, GET(1), 0xa4beea44, 4)\n\t\tSTEP(H2, d, a, b, c, GET(4), 0x4bdecfa9, 11)\n\t\tSTEP(H, c, d, a, b, GET(7), 0xf6bb4b60, 16)\n\t\tSTEP(H2, b, c, d, a, GET(10), 0xbebfbc70, 23)\n\t\tSTEP(H, a, b, c, d, GET(13), 0x289b7ec6, 4)\n\t\tSTEP(H2, d, a, b, c, GET(0), 0xeaa127fa, 11)\n\t\tSTEP(H, c, d, a, b, GET(3), 0xd4ef3085, 16)\n\t\tSTEP(H2, b, c, d, a, GET(6), 0x04881d05, 23)\n\t\tSTEP(H, a, b, c, d, GET(9), 0xd9d4d039, 4)\n\t\tSTEP(H2, d, a, b, c, GET(12), 0xe6db99e5, 11)\n\t\tSTEP(H, c, d, a, b, GET(15), 0x1fa27cf8, 16)\n\t\tSTEP(H2, b, c, d, a, GET(2), 0xc4ac5665, 23)\n\n/* Round 4 */\n\t\tSTEP(I, a, b, c, d, GET(0), 0xf4292244, 6)\n\t\tSTEP(I, d, a, b, c, GET(7), 0x432aff97, 10)\n\t\tSTEP(I, c, d, a, b, GET(14), 0xab9423a7, 15)\n\t\tSTEP(I, b, c, d, a, GET(5), 0xfc93a039, 21)\n\t\tSTEP(I, a, b, c, d, GET(12), 0x655b59c3, 6)\n\t\tSTEP(I, d, a, b, c, GET(3), 0x8f0ccc92, 10)\n\t\tSTEP(I, c, d, a, b, GET(10), 0xffeff47d, 15)\n\t\tSTEP(I, b, c, d, a, GET(1), 0x85845dd1, 21)\n\t\tSTEP(I, a, b, c, d, GET(8), 0x6fa87e4f, 6)\n\t\tSTEP(I, d, a, b, c, GET(15), 0xfe2ce6e0, 10)\n\t\tSTEP(I, c, d, a, b, GET(6), 0xa3014314, 15)\n\t\tSTEP(I, b, c, d, a, GET(13), 0x4e0811a1, 21)\n\t\tSTEP(I, a, b, c, d, GET(4), 0xf7537e82, 6)\n\t\tSTEP(I, d, a, b, c, GET(11), 0xbd3af235, 10)\n\t\tSTEP(I, c, d, a, b, GET(2), 0x2ad7d2bb, 15)\n\t\tSTEP(I, b, c, d, a, GET(9), 0xeb86d391, 21)\n\n\t\ta += saved_a;\n\t\tb += saved_b;\n\t\tc += saved_c;\n\t\td += saved_d;\n\n\t\tptr += 64;\n\t} while (size -= 64);\n\n\tctx->a = a;\n\tctx->b = b;\n\tctx->c = c;\n\tctx->d = d;\n\n\treturn ptr;\n}\n\nvoid MD5_Init(MD5_CTX *ctx)\n{\n\tctx->a = 0x67452301;\n\tctx->b = 0xefcdab89;\n\tctx->c = 0x98badcfe;\n\tctx->d = 0x10325476;\n\n\tctx->lo = 0;\n\tctx->hi = 0;\n}\n\nvoid MD5_Update(MD5_CTX *ctx, const void *data, unsigned long size)\n{\n\tMD5_u32plus saved_lo;\n\tunsigned long used, available;\n\n\tsaved_lo = ctx->lo;\n\tif ((ctx->lo = (saved_lo + size) & 0x1fffffff) < saved_lo)\n\t\tctx->hi++;\n\tctx->hi += size >> 29;\n\n\tused = saved_lo & 0x3f;\n\n\tif (used) {\n\t\tavailable = 64 - used;\n\n\t\tif (size < available) {\n\t\t\tmemcpy(&ctx->buffer[used], data, size);\n\t\t\treturn;\n\t\t}\n\n\t\tmemcpy(&ctx->buffer[used], data, available);\n\t\tdata = (const unsigned char *)data + available;\n\t\tsize -= available;\n\t\tbody(ctx, ctx->buffer, 64);\n\t}\n\n\tif (size >= 64) {\n\t\tdata = body(ctx, data, size & ~(unsigned long)0x3f);\n\t\tsize &= 0x3f;\n\t}\n\n\tmemcpy(ctx->buffer, data, size);\n}\n\nvoid MD5_Final(unsigned char *result, MD5_CTX *ctx)\n{\n\tunsigned long used, available;\n\n\tused = ctx->lo & 0x3f;\n\n\tctx->buffer[used++] = 0x80;\n\n\tavailable = 64 - used;\n\n\tif (available < 8) {\n\t\tmemset(&ctx->buffer[used], 0, available);\n\t\tbody(ctx, ctx->buffer, 64);\n\t\tused = 0;\n\t\tavailable = 64;\n\t}\n\n\tmemset(&ctx->buffer[used], 0, available - 8);\n\n\tctx->lo <<= 3;\n\tctx->buffer[56] = ctx->lo;\n\tctx->buffer[57] = ctx->lo >> 8;\n\tctx->buffer[58] = ctx->lo >> 16;\n\tctx->buffer[59] = ctx->lo >> 24;\n\tctx->buffer[60] = ctx->hi;\n\tctx->buffer[61] = ctx->hi >> 8;\n\tctx->buffer[62] = ctx->hi >> 16;\n\tctx->buffer[63] = ctx->hi >> 24;\n\n\tbody(ctx, ctx->buffer, 64);\n\n\tresult[0] = ctx->a;\n\tresult[1] = ctx->a >> 8;\n\tresult[2] = ctx->a >> 16;\n\tresult[3] = ctx->a >> 24;\n\tresult[4] = ctx->b;\n\tresult[5] = ctx->b >> 8;\n\tresult[6] = ctx->b >> 16;\n\tresult[7] = ctx->b >> 24;\n\tresult[8] = ctx->c;\n\tresult[9] = ctx->c >> 8;\n\tresult[10] = ctx->c >> 16;\n\tresult[11] = ctx->c >> 24;\n\tresult[12] = ctx->d;\n\tresult[13] = ctx->d >> 8;\n\tresult[14] = ctx->d >> 16;\n\tresult[15] = ctx->d >> 24;\n\n\tmemset(ctx, 0, sizeof(*ctx));\n}\n\n#endif\n"
  },
  {
    "path": "package/utils/oseama/src/md5.h",
    "content": "/*\n * This is an OpenSSL-compatible implementation of the RSA Data Security, Inc.\n * MD5 Message-Digest Algorithm (RFC 1321).\n *\n * Homepage:\n * http://openwall.info/wiki/people/solar/software/public-domain-source-code/md5\n *\n * Author:\n * Alexander Peslyak, better known as Solar Designer <solar at openwall.com>\n *\n * This software was written by Alexander Peslyak in 2001.  No copyright is\n * claimed, and the software is hereby placed in the public domain.\n * In case this attempt to disclaim copyright and place the software in the\n * public domain is deemed null and void, then the software is\n * Copyright (c) 2001 Alexander Peslyak and it is hereby released to the\n * general public under the following terms:\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted.\n *\n * There's ABSOLUTELY NO WARRANTY, express or implied.\n *\n * See md5.c for more information.\n */\n\n#ifdef HAVE_OPENSSL\n#include <openssl/md5.h>\n#elif !defined(_MD5_H)\n#define _MD5_H\n\n/* Any 32-bit or wider unsigned integer data type will do */\ntypedef unsigned int MD5_u32plus;\n\ntypedef struct {\n\tMD5_u32plus lo, hi;\n\tMD5_u32plus a, b, c, d;\n\tunsigned char buffer[64];\n\tMD5_u32plus block[16];\n} MD5_CTX;\n\nextern void MD5_Init(MD5_CTX *ctx);\nextern void MD5_Update(MD5_CTX *ctx, const void *data, unsigned long size);\nextern void MD5_Final(unsigned char *result, MD5_CTX *ctx);\n\n#endif\n"
  },
  {
    "path": "package/utils/oseama/src/oseama.c",
    "content": "/*\n * oseama\n *\n * Copyright (C) 2016 Rafał Miłecki <zajec5@gmail.com>\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of the GNU General Public License as published by the Free\n * Software Foundation; either version 2 of the License, or (at your option)\n * any later version.\n */\n\n#include <byteswap.h>\n#include <endian.h>\n#include <errno.h>\n#include <stdint.h>\n#include <stdio.h>\n#include <stdlib.h>\n#include <string.h>\n#include <unistd.h>\n\n#include \"md5.h\"\n\n#if !defined(__BYTE_ORDER)\n#error \"Unknown byte order\"\n#endif\n\n#if __BYTE_ORDER == __BIG_ENDIAN\n#define cpu_to_be32(x)\t(x)\n#define be32_to_cpu(x)\t(x)\n#define cpu_to_be16(x)\t(x)\n#define be16_to_cpu(x)\t(x)\n#elif __BYTE_ORDER == __LITTLE_ENDIAN\n#define cpu_to_be32(x)\tbswap_32(x)\n#define be32_to_cpu(x)\tbswap_32(x)\n#define cpu_to_be16(x)\tbswap_16(x)\n#define be16_to_cpu(x)\tbswap_16(x)\n#else\n#error \"Unsupported endianness\"\n#endif\n\n#define SEAMA_MAGIC\t\t\t0x5ea3a417\n\nstruct seama_seal_header {\n\tuint32_t magic;\n\tuint16_t reserved;\n\tuint16_t metasize;\n\tuint32_t imagesize;\n} __attribute__ ((packed));\n\nstruct seama_entity_header {\n\tuint32_t magic;\n\tuint16_t reserved;\n\tuint16_t metasize;\n\tuint32_t imagesize;\n\tuint8_t md5[16];\n} __attribute__ ((packed));\n\nchar *seama_path;\nint entity_idx = -1;\nchar *out_path;\n\nstatic inline size_t oseama_min(size_t x, size_t y) {\n\treturn x < y ? x : y;\n}\n\n/**************************************************\n * Info\n **************************************************/\n\nstatic void oseama_info_parse_options(int argc, char **argv) {\n\tint c;\n\n\twhile ((c = getopt(argc, argv, \"e:\")) != -1) {\n\t\tswitch (c) {\n\t\tcase 'e':\n\t\t\tentity_idx = atoi(optarg);\n\t\t\tbreak;\n\t\t}\n\t}\n}\n\nstatic int oseama_info_entities(FILE *seama) {\n\tstruct seama_entity_header hdr;\n\tsize_t bytes, metasize, imagesize;\n\tuint8_t buf[1024];\n\tchar *end, *tmp;\n\tint i = 0;\n\tint err = 0;\n\n\twhile ((bytes = fread(&hdr, 1, sizeof(hdr), seama)) == sizeof(hdr)) {\n\t\tif (be32_to_cpu(hdr.magic) != SEAMA_MAGIC) {\n\t\t\tfprintf(stderr, \"Invalid Seama magic: 0x%08x\\n\", be32_to_cpu(hdr.magic));\n\t\t\terr =  -EINVAL;\n\t\t\tgoto err_out;\n\t\t}\n\t\tmetasize = be16_to_cpu(hdr.metasize);\n\t\timagesize = be32_to_cpu(hdr.imagesize);\n\n\t\tif (entity_idx >= 0 && i != entity_idx) {\n\t\t\tfseek(seama, metasize + imagesize, SEEK_CUR);\n\t\t\ti++;\n\t\t\tcontinue;\n\t\t}\n\n\t\tif (metasize >= sizeof(buf)) {\n\t\t\tfprintf(stderr, \"Too small buffer (%zu B) to read all meta info (%zd B)\\n\", sizeof(buf), metasize);\n\t\t\terr =  -EINVAL;\n\t\t\tgoto err_out;\n\t\t}\n\n\t\tif (entity_idx < 0)\n\t\t\tprintf(\"\\n\");\n\t\tprintf(\"Entity offset:\\t%ld\\n\", ftell(seama) - sizeof(hdr));\n\t\tprintf(\"Entity size:\\t%zd\\n\", sizeof(hdr) + metasize + imagesize);\n\t\tprintf(\"Meta size:\\t%zd\\n\", metasize);\n\t\tprintf(\"Image size:\\t%zd\\n\", imagesize);\n\n\t\tbytes = fread(buf, 1, metasize, seama);\n\t\tif (bytes != metasize) {\n\t\t\tfprintf(stderr, \"Couldn't read %zd B of meta\\n\", metasize);\n\t\t\terr =  -EIO;\n\t\t\tgoto err_out;\n\t\t}\n\n\t\tend = (char *)&buf[metasize - 1];\n\t\t*end = '\\0';\n\t\tfor (tmp = (char *)buf; tmp < end && strlen(tmp); tmp += strlen(tmp) + 1) {\n\t\t\tprintf(\"Meta entry:\\t%s\\n\", tmp);\n\t\t}\n\n\t\tfseek(seama, imagesize, SEEK_CUR);\n\t\ti++;\n\t}\n\nerr_out:\n\treturn err;\n}\n\nstatic int oseama_info(int argc, char **argv) {\n\tFILE *seama;\n\tstruct seama_seal_header hdr;\n\tsize_t bytes;\n\tuint16_t metasize;\n\tuint32_t imagesize;\n\tuint8_t buf[1024];\n\tint err = 0;\n\n\tif (argc < 3) {\n\t\tfprintf(stderr, \"No Seama file passed\\n\");\n\t\terr = -EINVAL;\n\t\tgoto out;\n\t}\n\tseama_path = argv[2];\n\n\toptind = 3;\n\toseama_info_parse_options(argc, argv);\n\n\tseama = fopen(seama_path, \"r\");\n\tif (!seama) {\n\t\tfprintf(stderr, \"Couldn't open %s\\n\", seama_path);\n\t\terr = -EACCES;\n\t\tgoto out;\n\t}\n\n\tbytes = fread(&hdr, 1, sizeof(hdr), seama);\n\tif (bytes != sizeof(hdr)) {\n\t\tfprintf(stderr, \"Couldn't read %s header\\n\", seama_path);\n\t\terr =  -EIO;\n\t\tgoto err_close;\n\t}\n\tmetasize = be16_to_cpu(hdr.metasize);\n\timagesize = be32_to_cpu(hdr.imagesize);\n\n\tif (be32_to_cpu(hdr.magic) != SEAMA_MAGIC) {\n\t\tfprintf(stderr, \"Invalid Seama magic: 0x%08x\\n\", be32_to_cpu(hdr.magic));\n\t\terr =  -EINVAL;\n\t\tgoto err_close;\n\t}\n\n\tif (metasize >= sizeof(buf)) {\n\t\tfprintf(stderr, \"Too small buffer (%zu B) to read all meta info (%d B)\\n\", sizeof(buf), metasize);\n\t\terr =  -EINVAL;\n\t\tgoto err_close;\n\t}\n\n\tif (imagesize) {\n\t\tfprintf(stderr, \"Invalid Seama image size: 0x%08x (should be 0)\\n\", imagesize);\n\t\terr =  -EINVAL;\n\t\tgoto err_close;\n\t}\n\n\tbytes = fread(buf, 1, metasize, seama);\n\tif (bytes != metasize) {\n\t\tfprintf(stderr, \"Couldn't read %d B of meta\\n\", metasize);\n\t\terr =  -EIO;\n\t\tgoto err_close;\n\t}\n\n\tif (entity_idx < 0) {\n\t\tchar *end, *tmp;\n\n\t\tprintf(\"Meta size:\\t%d\\n\", metasize);\n\t\tprintf(\"Image size:\\t%d\\n\", imagesize);\n\n\t\tend = (char *)&buf[metasize - 1];\n\t\t*end = '\\0';\n\t\tfor (tmp = (char *)buf; tmp < end && strlen(tmp); tmp += strlen(tmp) + 1) {\n\t\t\tprintf(\"Meta entry:\\t%s\\n\", tmp);\n\t\t}\n\t}\n\n\toseama_info_entities(seama);\n\nerr_close:\n\tfclose(seama);\nout:\n\treturn err;\n}\n\n/**************************************************\n * Create\n **************************************************/\n\nstatic ssize_t oseama_entity_append_file(FILE *seama, const char *in_path) {\n\tFILE *in;\n\tsize_t bytes;\n\tssize_t length = 0;\n\tuint8_t buf[128];\n\n\tin = fopen(in_path, \"r\");\n\tif (!in) {\n\t\tfprintf(stderr, \"Couldn't open %s\\n\", in_path);\n\t\treturn -EACCES;\n\t}\n\n\twhile ((bytes = fread(buf, 1, sizeof(buf), in)) > 0) {\n\t\tif (fwrite(buf, 1, bytes, seama) != bytes) {\n\t\t\tfprintf(stderr, \"Couldn't write %zu B to %s\\n\", bytes, seama_path);\n\t\t\tlength = -EIO;\n\t\t\tbreak;\n\t\t}\n\t\tlength += bytes;\n\t}\n\n\tfclose(in);\n\n\treturn length;\n}\n\nstatic ssize_t oseama_entity_append_zeros(FILE *seama, size_t length) {\n\tuint8_t *buf;\n\n\tbuf = malloc(length);\n\tif (!buf)\n\t\treturn -ENOMEM;\n\tmemset(buf, 0, length);\n\n\tif (fwrite(buf, 1, length, seama) != length) {\n\t\tfprintf(stderr, \"Couldn't write %zu B to %s\\n\", length, seama_path);\n\t\treturn -EIO;\n\t}\n\n\treturn length;\n}\n\nstatic ssize_t oseama_entity_align(FILE *seama, size_t curr_offset, size_t alignment) {\n\tif (curr_offset & (alignment - 1)) {\n\t\tsize_t length = alignment - (curr_offset % alignment);\n\n\t\treturn oseama_entity_append_zeros(seama, length);\n\t}\n\n\treturn 0;\n}\n\nstatic int oseama_entity_write_hdr(FILE *seama, size_t metasize, size_t imagesize) {\n\tstruct seama_entity_header hdr = {};\n\tuint8_t buf[128];\n\tsize_t length = imagesize;\n\tsize_t bytes;\n\tMD5_CTX ctx;\n\n\tfseek(seama, sizeof(hdr) + metasize, SEEK_SET);\n\tMD5_Init(&ctx);\n\twhile ((bytes = fread(buf, 1, oseama_min(sizeof(buf), length), seama)) > 0) {\n\t\tMD5_Update(&ctx, buf, bytes);\n\t\tlength -= bytes;\n\t}\n\tMD5_Final(hdr.md5, &ctx);\n\n\thdr.magic = cpu_to_be32(SEAMA_MAGIC);\n\thdr.metasize = cpu_to_be16(metasize);\n\thdr.imagesize = cpu_to_be32(imagesize);\n\n\tfseek(seama, 0, SEEK_SET);\n\tbytes = fwrite(&hdr, 1, sizeof(hdr), seama);\n\tif (bytes != sizeof(hdr)) {\n\t\tfprintf(stderr, \"Couldn't write Seama entity header to %s\\n\", seama_path);\n\t\treturn -EIO;\n\t}\n\n\treturn 0;\n}\n\nstatic int oseama_entity(int argc, char **argv) {\n\tFILE *seama;\n\tssize_t sbytes;\n\tsize_t curr_offset = sizeof(struct seama_entity_header);\n\tsize_t metasize = 0, imagesize = 0;\n\tint c;\n\tint err = 0;\n\n\tif (argc < 3) {\n\t\tfprintf(stderr, \"No Seama file passed\\n\");\n\t\terr = -EINVAL;\n\t\tgoto out;\n\t}\n\tseama_path = argv[2];\n\n\tseama = fopen(seama_path, \"w+\");\n\tif (!seama) {\n\t\tfprintf(stderr, \"Couldn't open %s\\n\", seama_path);\n\t\terr = -EACCES;\n\t\tgoto out;\n\t}\n\tfseek(seama, curr_offset, SEEK_SET);\n\n\toptind = 3;\n\twhile ((c = getopt(argc, argv, \"m:f:b:\")) != -1) {\n\t\tswitch (c) {\n\t\tcase 'm':\n\t\t\tsbytes = fwrite(optarg, 1, strlen(optarg) + 1, seama);\n\t\t\tif (sbytes < 0) {\n\t\t\t\tfprintf(stderr, \"Failed to write meta %s\\n\", optarg);\n\t\t\t} else {\n\t\t\t\tcurr_offset += sbytes;\n\t\t\t\tmetasize += sbytes;\n\t\t\t}\n\n\t\t\tsbytes = oseama_entity_align(seama, curr_offset, 4);\n\t\t\tif (sbytes < 0) {\n\t\t\t\tfprintf(stderr, \"Failed to append zeros\\n\");\n\t\t\t} else {\n\t\t\t\tcurr_offset += sbytes;\n\t\t\t\tmetasize += sbytes;\n\t\t\t}\n\n\t\t\tbreak;\n\t\tcase 'f':\n\t\tcase 'b':\n\t\t\tbreak;\n\t\t}\n\t}\n\n\toptind = 3;\n\twhile ((c = getopt(argc, argv, \"m:f:b:\")) != -1) {\n\t\tswitch (c) {\n\t\tcase 'm':\n\t\t\tbreak;\n\t\tcase 'f':\n\t\t\tsbytes = oseama_entity_append_file(seama, optarg);\n\t\t\tif (sbytes < 0) {\n\t\t\t\tfprintf(stderr, \"Failed to append file %s\\n\", optarg);\n\t\t\t} else {\n\t\t\t\tcurr_offset += sbytes;\n\t\t\t\timagesize += sbytes;\n\t\t\t}\n\t\t\tbreak;\n\t\tcase 'b':\n\t\t\tsbytes = strtol(optarg, NULL, 0) - curr_offset;\n\t\t\tif (sbytes < 0) {\n\t\t\t\tfprintf(stderr, \"Current Seama entity length is 0x%zx, can't pad it with zeros to 0x%lx\\n\", curr_offset, strtol(optarg, NULL, 0));\n\t\t\t} else {\n\t\t\t\tsbytes = oseama_entity_append_zeros(seama, sbytes);\n\t\t\t\tif (sbytes < 0) {\n\t\t\t\t\tfprintf(stderr, \"Failed to append zeros\\n\");\n\t\t\t\t} else {\n\t\t\t\t\tcurr_offset += sbytes;\n\t\t\t\t\timagesize += sbytes;\n\t\t\t\t}\n\t\t\t}\n\t\t\tbreak;\n\t\t}\n\t\tif (err)\n\t\t\tbreak;\n\t}\n\n\toseama_entity_write_hdr(seama, metasize, imagesize);\n\n\tfclose(seama);\nout:\n\treturn err;\n}\n\n/**************************************************\n * Extract\n **************************************************/\n\nstatic void oseama_extract_parse_options(int argc, char **argv) {\n\tint c;\n\n\twhile ((c = getopt(argc, argv, \"e:o:\")) != -1) {\n\t\tswitch (c) {\n\t\tcase 'e':\n\t\t\tentity_idx = atoi(optarg);\n\t\t\tbreak;\n\t\tcase 'o':\n\t\t\tout_path = optarg;\n\t\t\tbreak;\n\t\t}\n\t}\n}\n\nstatic int oseama_extract_entity(FILE *seama, FILE *out) {\n\tstruct seama_entity_header hdr;\n\tsize_t bytes, metasize, imagesize, length;\n\tuint8_t buf[1024];\n\tint i = 0;\n\tint err = 0;\n\n\twhile ((bytes = fread(&hdr, 1, sizeof(hdr), seama)) == sizeof(hdr)) {\n\t\tif (be32_to_cpu(hdr.magic) != SEAMA_MAGIC) {\n\t\t\tfprintf(stderr, \"Invalid Seama magic: 0x%08x\\n\", be32_to_cpu(hdr.magic));\n\t\t\terr =  -EINVAL;\n\t\t\tbreak;\n\t\t}\n\t\tmetasize = be16_to_cpu(hdr.metasize);\n\t\timagesize = be32_to_cpu(hdr.imagesize);\n\n\t\tif (i != entity_idx) {\n\t\t\tfseek(seama, metasize + imagesize, SEEK_CUR);\n\t\t\ti++;\n\t\t\tcontinue;\n\t\t}\n\n\t\tfseek(seama, -sizeof(hdr), SEEK_CUR);\n\n\t\tlength = sizeof(hdr) + metasize + imagesize;\n\t\twhile ((bytes = fread(buf, 1, oseama_min(sizeof(buf), length), seama)) > 0) {\n\t\t\tif (fwrite(buf, 1, bytes, out) != bytes) {\n\t\t\t\tfprintf(stderr, \"Couldn't write %zu B to %s\\n\", bytes, out_path);\n\t\t\t\terr = -EIO;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\tlength -= bytes;\n\t\t}\n\n\t\tif (length) {\n\t\t\tfprintf(stderr, \"Couldn't extract whole entity %d from %s (%zu B left)\\n\", entity_idx, seama_path, length);\n\t\t\terr = -EIO;\n\t\t\tbreak;\n\t\t}\n\n\t\tbreak;\n\t}\n\n\treturn err;\n}\n\nstatic int oseama_extract(int argc, char **argv) {\n\tFILE *seama;\n\tFILE *out;\n\tstruct seama_seal_header hdr;\n\tsize_t bytes;\n\tuint16_t metasize;\n\tint err = 0;\n\n\tif (argc < 3) {\n\t\tfprintf(stderr, \"No Seama file passed\\n\");\n\t\terr = -EINVAL;\n\t\tgoto out;\n\t}\n\tseama_path = argv[2];\n\n\toptind = 3;\n\toseama_extract_parse_options(argc, argv);\n\tif (entity_idx < 0) {\n\t\tfprintf(stderr, \"No entity specified\\n\");\n\t\terr = -EINVAL;\n\t\tgoto out;\n\t} else if (!out_path) {\n\t\tfprintf(stderr, \"No output file specified\\n\");\n\t\terr = -EINVAL;\n\t\tgoto out;\n\t}\n\n\tseama = fopen(seama_path, \"r\");\n\tif (!seama) {\n\t\tfprintf(stderr, \"Couldn't open %s\\n\", seama_path);\n\t\terr = -EACCES;\n\t\tgoto out;\n\t}\n\n\tout = fopen(out_path, \"w\");\n\tif (!out) {\n\t\tfprintf(stderr, \"Couldn't open %s\\n\", out_path);\n\t\terr = -EACCES;\n\t\tgoto err_close_seama;\n\t}\n\n\tbytes = fread(&hdr, 1, sizeof(hdr), seama);\n\tif (bytes != sizeof(hdr)) {\n\t\tfprintf(stderr, \"Couldn't read %s header\\n\", seama_path);\n\t\terr =  -EIO;\n\t\tgoto err_close_out;\n\t}\n\tmetasize = be16_to_cpu(hdr.metasize);\n\n\tfseek(seama, metasize, SEEK_CUR);\n\n\toseama_extract_entity(seama, out);\n\nerr_close_out:\n\tfclose(out);\nerr_close_seama:\n\tfclose(seama);\nout:\n\treturn err;\n}\n\n/**************************************************\n * Start\n **************************************************/\n\nstatic void usage() {\n\tprintf(\"Usage:\\n\");\n\tprintf(\"\\n\");\n\tprintf(\"Info about Seama seal (container):\\n\");\n\tprintf(\"\\toseama info <file> [options]\\n\");\n\tprintf(\"\\t-e\\t\\t\\t\\tprint info about specified entity only\\n\");\n\tprintf(\"\\n\");\n\tprintf(\"Create Seama entity:\\n\");\n\tprintf(\"\\toseama entity <file> [options]\\n\");\n\tprintf(\"\\t-m meta\\t\\t\\t\\tmeta into to put in header\\n\");\n\tprintf(\"\\t-f file\\t\\t\\t\\tappend content from file\\n\");\n\tprintf(\"\\t-b offset\\t\\t\\tappend zeros till reaching absolute offset\\n\");\n\tprintf(\"\\n\");\n\tprintf(\"Extract from Seama seal (container):\\n\");\n\tprintf(\"\\toseama extract <file> [options]\\n\");\n\tprintf(\"\\t-e\\t\\t\\t\\tindex of entity to extract\\n\");\n\tprintf(\"\\t-o file\\t\\t\\t\\toutput file\\n\");\n}\n\nint main(int argc, char **argv) {\n\tif (argc > 1) {\n\t\tif (!strcmp(argv[1], \"info\"))\n\t\t\treturn oseama_info(argc, argv);\n\t\telse if (!strcmp(argv[1], \"entity\"))\n\t\t\treturn oseama_entity(argc, argv);\n\t\telse if (!strcmp(argv[1], \"extract\"))\n\t\t\treturn oseama_extract(argc, argv);\n\t}\n\n\tusage();\n\treturn 0;\n}\n"
  },
  {
    "path": "package/utils/otrx/Makefile",
    "content": "#\n# Copyright (C) 2015 Rafał Miłecki <zajec5@gmail.com>\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=otrx\nPKG_RELEASE:=1\n\nPKG_SOURCE_PROTO:=git\nPKG_SOURCE_URL=$(PROJECT_GIT)/project/firmware-utils.git\nPKG_SOURCE_DATE:=2021-12-02\nPKG_SOURCE_VERSION:=56e8e19151743c923f48604c457850cf8eb52076\nPKG_MIRROR_HASH:=2a40ac73e8eab0a7a4474cb331b8e2fc972635314b0b5e02a9f2b9a32c5d5f3b\n\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine Package/otrx\n  SECTION:=utils\n  CATEGORY:=Base system\n  TITLE:=Utility for opening (analyzing) TRX firmware images\n  MAINTAINER:=Rafał Miłecki <zajec5@gmail.com>\n  DEPENDS:=@(TARGET_bcm47xx||TARGET_bcm53xx)\nendef\n\ndefine Package/otrx/description\n This package contains an utility that allows validating TRX images.\nendef\n\nTARGET_CFLAGS += -Wall\n\ndefine Build/Compile\n\t$(TARGET_CC) $(TARGET_CFLAGS) $(TARGET_LDFLAGS) \\\n\t\t-o $(PKG_BUILD_DIR)/otrx \\\n\t\t$(PKG_BUILD_DIR)/src/otrx.c\nendef\n\ndefine Package/otrx/install\n\t$(INSTALL_DIR) $(1)/usr/bin\n\t$(INSTALL_BIN) $(PKG_BUILD_DIR)/otrx $(1)/usr/bin/\nendef\n\n$(eval $(call BuildPackage,otrx))\n"
  },
  {
    "path": "package/utils/policycoreutils/Makefile",
    "content": "#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=policycoreutils\nPKG_VERSION:=3.3\nPKG_RELEASE:=1\n\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz\nPKG_SOURCE_URL:=https://github.com/SELinuxProject/selinux/releases/download/$(PKG_VERSION)\nPKG_HASH:=4199040ced8a81f2ddd0522b4faf2aba62fc821473f4051dc8474fb1c4a01078\nPKG_INSTALL:=1\nHOST_BUILD_DEPENDS:=libsemanage/host gettext-full/host\nPKG_BUILD_DEPENDS:=BUSYBOX_CONFIG_PAM:libpam gettext-full/host\n\nPKG_MAINTAINER:=Thomas Petazzoni <thomas.petazzoni@bootlin.com>\nPKG_CPE_ID:=cpe:/a:selinuxproject:policycoreutils\nPKG_LICENSE:=GPL-2.0-or-later\nPKG_LICENSE_FILES:=COPYING\n\ninclude $(INCLUDE_DIR)/package.mk\ninclude $(INCLUDE_DIR)/nls.mk\ninclude $(INCLUDE_DIR)/host-build.mk\n\nDIR_USR_BIN:= \\\n\tnewrole \\\n\tsecon \\\n\tsestatus\n\nDIR_USR_SBIN:= \\\n\tload_policy \\\n\tsetsebool\n\nLIBEXEC_UTILS := \\\n\tpp\n\nSBIN_UTILS:= \\\n\trestorecon_xattr \\\n\tsetfiles\n\nUSR_BIN_UTILS:= \\\n\tnewrole \\\n\tsecon \\\n\tsestatus\n\nUSR_SBIN_UTILS:= \\\n\tfixfiles \\\n\tgenhomedircon \\\n\topen_init_pty \\\n\trun_init \\\n\tsemodule \\\n\tload_policy \\\n\tsetsebool\n\nTARGET_LDFLAGS += $(INTL_LDFLAGS) $(if $(INTL_FULL),-lintl)\n\nMAKE_FLAGS += \\\n\tPAMH=$(CONFIG_BUSYBOX_CONFIG_PAM)\n\nHOST_MAKE_FLAGS += \\\n\tPAMH=$(CONFIG_BUSYBOX_CONFIG_PAM) \\\n\tDESTDIR=$(STAGING_DIR_HOST) \\\n\tPREFIX= \\\n\tSBINDIR=/bin\n\nHOST_LDFLAGS += -Wl,-rpath=$(STAGING_DIR_HOSTPKG)/lib\n\n$(eval $(foreach a,$(DIR_SBIN),ALTS_$(a):=300:/sbin/$(a):/sbin/policycoreutils-$(a)$(newline)))\n$(eval $(foreach a,$(DIR_USR_BIN),ALTS_$(a):=300:/usr/bin/$(a):/usr/bin/policycoreutils-$(a)$(newline)))\n$(eval $(foreach a,$(DIR_USR_SBIN),ALTS_$(a):=300:/usr/sbin/$(a):/usr/sbin/policycoreutils-$(a)$(newline)))\nALTS_setfiles:=300:/sbin/restorecon:/sbin/policycoreutils-setfiles 300:/sbin/setfiles:/sbin/policycoreutils-setfiles\n\nDEPENDS_genhomedircon:=+libsemanage $(INTL_DEPENDS)\nDEPENDS_load_policy:=+libselinux $(INTL_DEPENDS)\nDEPENDS_newrole:=+libselinux +libaudit +BUSYBOX_CONFIG_PAM:libpam $(INTL_DEPENDS)\nDEPENDS_open_init_pty:=$(INTL_DEPENDS)\nDEPENDS_pp:=+libsepol $(INTL_DEPENDS)\nDEPENDS_restorecon_xattr:=+libselinux +libsepol +libaudit $(INTL_DEPENDS)\nDEPENDS_run_init:=+libselinux +libaudit +BUSYBOX_CONFIG_PAM:libpam $(INTL_DEPENDS)\nDEPENDS_secon:=+libselinux $(INTL_DEPENDS)\nDEPENDS_semanage:=+libsemanage\nDEPENDS_semodule:=+libsemanage $(INTL_DEPENDS)\nDEPENDS_sestatus:=+libselinux $(INTL_DEPENDS)\nDEPENDS_setfiles:=+libselinux +libsepol +libaudit $(INTL_DEPENDS)\nDEPENDS_setsebool:=+libsemanage $(INTL_DEPENDS)\n\ndefine Package/policycoreutils/Default\n  SECTION:=utils\n  CATEGORY:=Utilities\n  TITLE:=SELinux policy utility\n  URL:=http://selinuxproject.org/page/Main_Page\nendef\n\ndefine Package/policycoreutils\n  $(call Package/policycoreutils/Default)\n  MENU:=1\n  TITLE+= common files\nendef\n\ndefine GenUtilPkg\n  define Package/$(1)\n    $(call Package/policycoreutils/Default)\n    DEPENDS+= policycoreutils $(DEPENDS_$(2))\n    TITLE+= $(2)\n    ALTERNATIVES:=$(ALTS_$(2))\n  endef\n\n  define Package/$(1)/description\nPolicycoreutils is a collection of policy utilities\n(originally the \"core\" set of utilities needed to use\nSELinux, although it has grown a bit over time).\n\nThis package provides the $(2) utility.\n  endef\nendef\n\n$(foreach a,$(LIBEXEC_UTILS) $(SBIN_UTILS) $(USR_BIN_UTILS) $(USR_SBIN_UTILS),$(eval $(call GenUtilPkg,policycoreutils-$(a),$(a))))\n\ndefine Package/policycoreutils/install\n\t$(INSTALL_DIR) $(1)/etc\n\t$(INSTALL_CONF) $(PKG_INSTALL_DIR)/etc/sestatus.conf $(1)/etc\nifdef CONFIG_BUSYBOX_CONFIG_PAM\n\t$(INSTALL_DIR) $(1)/etc/pam.d\n\t$(INSTALL_CONF) $(PKG_INSTALL_DIR)/etc/pam.d/run_init $(1)/etc/pam.d\n\t$(INSTALL_CONF) $(PKG_INSTALL_DIR)/etc/pam.d/newrole $(1)/etc/pam.d\nendif\nendef\n\ndefine BuildUtil\n  define Package/$(1)/install\n\t$(INSTALL_DIR) $$(1)$(2)\n\t$(INSTALL_BIN) $$(PKG_INSTALL_DIR)$(2)/$(3) $$(1)$(2)/$(if $(ALTS_$(3)),policycoreutils-$(3),$(3))\n  endef\n\n  $$(eval $$(call BuildPackage,$(1)))\nendef\n\n$(eval $(call BuildPackage,policycoreutils))\n$(foreach a,$(SBIN_UTILS),$(eval $(call BuildUtil,policycoreutils-$(a),/sbin,$(a))))\n$(foreach a,$(USR_BIN_UTILS),$(eval $(call BuildUtil,policycoreutils-$(a),/usr/bin,$(a))))\n$(foreach a,$(USR_SBIN_UTILS),$(eval $(call BuildUtil,policycoreutils-$(a),/usr/sbin,$(a))))\n$(foreach a,$(LIBEXEC_UTILS),$(eval $(call BuildUtil,policycoreutils-$(a),/usr/libexec/selinux/hll,$(a))))\n$(eval $(call HostBuild))\n"
  },
  {
    "path": "package/utils/px5g-mbedtls/Makefile",
    "content": "#\n# Copyright (C) 2010-2015 Jo-Philipp Wich <jo@mein.io>\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=px5g-mbedtls\nPKG_RELEASE:=9\nPKG_LICENSE:=LGPL-2.1\n\nPKG_USE_MIPS16:=0\n\nPKG_MAINTAINER:=Jo-Philipp Wich <jo@mein.io>\n\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine Package/px5g-mbedtls\n  SECTION:=utils\n  CATEGORY:=Utilities\n  SUBMENU:=Encryption\n  TITLE:=X.509 certificate generator (using mbedtls)\n  DEPENDS:=+libmbedtls\n  PROVIDES:=px5g\n  VARIANT:=mbedtls\nendef\n\ndefine Package/px5g-mbedtls/description\n Px5g is a tiny standalone X.509 certificate generator.\n It suitable to create key files and certificates in DER\n and PEM format for use with stunnel, uhttpd and others.\nendef\n\ndefine Package/px5g-standalone\n  SECTION:=utils\n  CATEGORY:=Utilities\n  SUBMENU:=Encryption\n  TITLE:=X.509 certificate generator (standalone)\n  VARIANT:=standalone\nendef\nPackage/px5g-standalone/description = $(Package/px5g-mbedtls/description)\n\ndefine Build/Prepare\n\tmkdir -p $(PKG_BUILD_DIR)\nendef\n\nTARGET_LDFLAGS += -lmbedtls -lmbedx509 -lmbedcrypto\n\nifeq ($(BUILD_VARIANT),standalone)\n  TARGET_LDFLAGS := -Wl,-Bstatic $(TARGET_LDFLAGS) -Wl,-Bdynamic\nendif\n\nTARGET_CFLAGS += -Wl,--gc-sections -Wall -Werror\n\ndefine Build/Compile\n\t$(TARGET_CC) $(TARGET_CPPFLAGS) $(TARGET_CFLAGS) -o $(PKG_BUILD_DIR)/px5g px5g-mbedtls.c $(TARGET_LDFLAGS)\nendef\n\ndefine Package/px5g-mbedtls/install\n\t$(INSTALL_DIR) $(1)/usr/sbin\n\t$(INSTALL_BIN) $(PKG_BUILD_DIR)/px5g $(1)/usr/sbin/px5g\nendef\n\nPackage/px5g-standalone/install = $(Package/px5g-mbedtls/install)\n\n$(eval $(call BuildPackage,px5g-mbedtls))\n$(eval $(call BuildPackage,px5g-standalone))\n"
  },
  {
    "path": "package/utils/px5g-mbedtls/px5g-mbedtls.c",
    "content": "/*\n * px5g - Embedded x509 key and certificate generator based on PolarSSL\n *\n *   Copyright (C) 2009 Steven Barth <steven@midlink.org>\n *   Copyright (C) 2014 Felix Fietkau <nbd@nbd.name>\n *\n *  This library is free software; you can redistribute it and/or\n *  modify it under the terms of the GNU Lesser General Public\n *  License, version 2.1 as published by the Free Software Foundation.\n *\n *  This library is distributed in the hope that it will be useful,\n *  but WITHOUT ANY WARRANTY; without even the implied warranty of\n *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\n *  Lesser General Public License for more details.\n *\n *  You should have received a copy of the GNU Lesser General Public\n *  License along with this library; if not, write to the Free Software\n *  Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,\n *  MA  02110-1301  USA\n */\n\n#include <sys/types.h>\n\n#include <stdio.h>\n#include <stdlib.h>\n#include <string.h>\n#include <time.h>\n#include <limits.h>\n#include <unistd.h>\n#include <fcntl.h>\n#include <stdbool.h>\n\n#include <mbedtls/bignum.h>\n#include <mbedtls/x509_crt.h>\n#include <mbedtls/ecp.h>\n#include <mbedtls/rsa.h>\n#include <mbedtls/pk.h>\n\n#define PX5G_VERSION \"0.2\"\n#define PX5G_COPY \"Copyright (c) 2009 Steven Barth <steven@midlink.org>\"\n#define PX5G_LICENSE \"Licensed under the GNU Lesser General Public License v2.1\"\n\nstatic int urandom_fd;\nstatic char buf[16384];\n\nstatic int _urandom(void *ctx, unsigned char *out, size_t len)\n{\n\tread(urandom_fd, out, len);\n\treturn 0;\n}\n\nstatic void write_file(const char *path, int len, bool pem)\n{\n\tFILE *f = stdout;\n\tconst char *buf_start = buf;\n\n\tif (!pem)\n\t\tbuf_start += sizeof(buf) - len;\n\n\tif (!len) {\n\t\tfprintf(stderr, \"No data to write\\n\");\n\t\texit(1);\n\t}\n\n\tif (!f) {\n\t\tfprintf(stderr, \"error: I/O error\\n\");\n\t\texit(1);\n\t}\n\n\tif (path)\n\t\tf = fopen(path, \"w\");\n\n\tfwrite(buf_start, 1, len, f);\n\tfclose(f);\n}\n\nstatic mbedtls_ecp_group_id ecp_curve(const char *name)\n{\n\tconst mbedtls_ecp_curve_info *curve_info;\n\n\tif (!strcmp(name, \"P-256\"))\n\t\treturn MBEDTLS_ECP_DP_SECP256R1;\n\telse if (!strcmp(name, \"P-384\"))\n\t\treturn MBEDTLS_ECP_DP_SECP384R1;\n\telse if (!strcmp(name, \"P-521\"))\n\t\treturn MBEDTLS_ECP_DP_SECP521R1;\n\tcurve_info = mbedtls_ecp_curve_info_from_name(name);\n\tif (curve_info == NULL)\n\t\treturn MBEDTLS_ECP_DP_NONE;\n\telse\n\t\treturn curve_info->grp_id;\n}\n\nstatic void write_key(mbedtls_pk_context *key, const char *path, bool pem)\n{\n\tint len = 0;\n\n\tif (pem) {\n\t\tif (mbedtls_pk_write_key_pem(key, (void *) buf, sizeof(buf)) == 0)\n\t\t\tlen = strlen(buf);\n\t} else {\n\t\tlen = mbedtls_pk_write_key_der(key, (void *) buf, sizeof(buf));\n\t\tif (len < 0)\n\t\t\tlen = 0;\n\t}\n\n\twrite_file(path, len, pem);\n}\n\nstatic void gen_key(mbedtls_pk_context *key, bool rsa, int ksize, int exp,\n\t\t    mbedtls_ecp_group_id curve, bool pem)\n{\n\tmbedtls_pk_init(key);\n\tif (rsa) {\n\t\tfprintf(stderr, \"Generating RSA private key, %i bit long modulus\\n\", ksize);\n\t\tmbedtls_pk_setup(key, mbedtls_pk_info_from_type(MBEDTLS_PK_RSA));\n\t\tif (!mbedtls_rsa_gen_key(mbedtls_pk_rsa(*key), _urandom, NULL, ksize, exp))\n\t\t\treturn;\n\t} else {\n\t\tfprintf(stderr, \"Generating EC private key\\n\");\n\t\tmbedtls_pk_setup(key, mbedtls_pk_info_from_type(MBEDTLS_PK_ECKEY));\n\t\tif (!mbedtls_ecp_gen_key(curve, mbedtls_pk_ec(*key), _urandom, NULL))\n\t\t\treturn;\n\t}\n\tfprintf(stderr, \"error: key generation failed\\n\");\n\texit(1);\n}\n\nint dokey(bool rsa, char **arg)\n{\n\tmbedtls_pk_context key;\n\tunsigned int ksize = 512;\n\tint exp = 65537;\n\tchar *path = NULL;\n\tbool pem = true;\n\tmbedtls_ecp_group_id curve = MBEDTLS_ECP_DP_SECP256R1;\n\n\twhile (*arg && **arg == '-') {\n\t\tif (!strcmp(*arg, \"-out\") && arg[1]) {\n\t\t\tpath = arg[1];\n\t\t\targ++;\n\t\t} else if (!strcmp(*arg, \"-3\")) {\n\t\t\texp = 3;\n\t\t} else if (!strcmp(*arg, \"-der\")) {\n\t\t\tpem = false;\n\t\t}\n\t\targ++;\n\t}\n\n\tif (*arg && rsa) {\n\t\tksize = (unsigned int)atoi(*arg);\n\t} else if (*arg) {\n\t\tcurve = ecp_curve((const char *)*arg);\n\t\tif (curve == MBEDTLS_ECP_DP_NONE) {\n\t\t\tfprintf(stderr, \"error: invalid curve name: %s\\n\", *arg);\n\t\t\treturn 1;\n\t\t}\n\t}\n\n\tgen_key(&key, rsa, ksize, exp, curve, pem);\n\twrite_key(&key, path, pem);\n\n\tmbedtls_pk_free(&key);\n\n\treturn 0;\n}\n\nint selfsigned(char **arg)\n{\n\tmbedtls_pk_context key;\n\tmbedtls_x509write_cert cert;\n\tmbedtls_mpi serial;\n\n\tchar *subject = \"\";\n\tunsigned int ksize = 512;\n\tint exp = 65537;\n\tunsigned int days = 30;\n\tchar *keypath = NULL, *certpath = NULL;\n\tbool pem = true;\n\ttime_t from = time(NULL), to;\n\tchar fstr[20], tstr[20], sstr[17];\n\tint len;\n\tbool rsa = true;\n\tmbedtls_ecp_group_id curve = MBEDTLS_ECP_DP_SECP256R1;\n\n\twhile (*arg && **arg == '-') {\n\t\tif (!strcmp(*arg, \"-der\")) {\n\t\t\tpem = false;\n\t\t} else if (!strcmp(*arg, \"-newkey\") && arg[1]) {\n\t\t\tif (!strncmp(arg[1], \"rsa:\", 4)) {\n\t\t\t\trsa = true;\n\t\t\t\tksize = (unsigned int)atoi(arg[1] + 4);\n\t\t\t} else if (!strcmp(arg[1], \"ec\")) {\n\t\t\t\trsa = false;\n\t\t\t} else {\n\t\t\t\tfprintf(stderr, \"error: invalid algorithm\\n\");\n\t\t\t\treturn 1;\n\t\t\t}\n\t\t\targ++;\n\t\t} else if (!strcmp(*arg, \"-days\") && arg[1]) {\n\t\t\tdays = (unsigned int)atoi(arg[1]);\n\t\t\targ++;\n\t\t} else if (!strcmp(*arg, \"-pkeyopt\") && arg[1]) {\n\t\t\tif (strncmp(arg[1], \"ec_paramgen_curve:\", 18)) {\n\t\t\t\tfprintf(stderr, \"error: invalid pkey option: %s\\n\", arg[1]);\n\t\t\t\treturn 1;\n\t\t\t}\n\t\t\tcurve = ecp_curve((const char *)(arg[1] + 18));\n\t\t\tif (curve == MBEDTLS_ECP_DP_NONE) {\n\t\t\t\tfprintf(stderr, \"error: invalid curve name: %s\\n\", arg[1] + 18);\n\t\t\t\treturn 1;\n\t\t\t}\n\t\t\targ++;\n\t\t} else if (!strcmp(*arg, \"-keyout\") && arg[1]) {\n\t\t\tkeypath = arg[1];\n\t\t\targ++;\n\t\t} else if (!strcmp(*arg, \"-out\") && arg[1]) {\n\t\t\tcertpath = arg[1];\n\t\t\targ++;\n\t\t} else if (!strcmp(*arg, \"-subj\") && arg[1]) {\n\t\t\tif (arg[1][0] != '/' || strchr(arg[1], ';')) {\n\t\t\t\tfprintf(stderr, \"error: invalid subject\");\n\t\t\t\treturn 1;\n\t\t\t}\n\t\t\tsubject = calloc(strlen(arg[1]) + 1, 1);\n\t\t\tchar *oldc = arg[1] + 1, *newc = subject, *delim;\n\t\t\tdo {\n\t\t\t\tdelim = strchr(oldc, '=');\n\t\t\t\tif (!delim) {\n\t\t\t\t\tfprintf(stderr, \"error: invalid subject\");\n\t\t\t\t\treturn 1;\n\t\t\t\t}\n\t\t\t\tmemcpy(newc, oldc, delim - oldc + 1);\n\t\t\t\tnewc += delim - oldc + 1;\n\t\t\t\toldc = delim + 1;\n\n\t\t\t\tdelim = strchr(oldc, '/');\n\t\t\t\tif (!delim) {\n\t\t\t\t\tdelim = arg[1] + strlen(arg[1]);\n\t\t\t\t}\n\t\t\t\tmemcpy(newc, oldc, delim - oldc);\n\t\t\t\tnewc += delim - oldc;\n\t\t\t\t*newc++ = ',';\n\t\t\t\toldc = delim + 1;\n\t\t\t} while(*delim);\n\t\t\targ++;\n\t\t}\n\t\targ++;\n\t}\n\tgen_key(&key, rsa, ksize, exp, curve, pem);\n\n\tif (keypath)\n\t\twrite_key(&key, keypath, pem);\n\n\tfrom = (from < 1000000000) ? 1000000000 : from;\n\tstrftime(fstr, sizeof(fstr), \"%Y%m%d%H%M%S\", gmtime(&from));\n\tto = from + 60 * 60 * 24 * days;\n\tif (to < from)\n\t\tto = INT_MAX;\n\tstrftime(tstr, sizeof(tstr), \"%Y%m%d%H%M%S\", gmtime(&to));\n\n\tfprintf(stderr, \"Generating selfsigned certificate with subject '%s'\"\n\t\t\t\" and validity %s-%s\\n\", subject, fstr, tstr);\n\n\tmbedtls_x509write_crt_init(&cert);\n\tmbedtls_x509write_crt_set_md_alg(&cert, MBEDTLS_MD_SHA256);\n\tmbedtls_x509write_crt_set_issuer_key(&cert, &key);\n\tmbedtls_x509write_crt_set_subject_key(&cert, &key);\n\tmbedtls_x509write_crt_set_subject_name(&cert, subject);\n\tmbedtls_x509write_crt_set_issuer_name(&cert, subject);\n\tmbedtls_x509write_crt_set_validity(&cert, fstr, tstr);\n\tmbedtls_x509write_crt_set_basic_constraints(&cert, 0, -1);\n\tmbedtls_x509write_crt_set_subject_key_identifier(&cert);\n\tmbedtls_x509write_crt_set_authority_key_identifier(&cert);\n\n\t_urandom(NULL, (void *) buf, 8);\n\tfor (len = 0; len < 8; len++)\n\t\tsprintf(sstr + len*2, \"%02x\", (unsigned char) buf[len]);\n\n\tmbedtls_mpi_init(&serial);\n\tmbedtls_mpi_read_string(&serial, 16, sstr);\n\tmbedtls_x509write_crt_set_serial(&cert, &serial);\n\n\tif (pem) {\n\t\tif (mbedtls_x509write_crt_pem(&cert, (void *) buf, sizeof(buf), _urandom, NULL) < 0) {\n\t\t\tfprintf(stderr, \"Failed to generate certificate\\n\");\n\t\t\treturn 1;\n\t\t}\n\n\t\tlen = strlen(buf);\n\t} else {\n\t\tlen = mbedtls_x509write_crt_der(&cert, (void *) buf, sizeof(buf), _urandom, NULL);\n\t\tif (len < 0) {\n\t\t\tfprintf(stderr, \"Failed to generate certificate: %d\\n\", len);\n\t\t\treturn 1;\n\t\t}\n\t}\n\twrite_file(certpath, len, pem);\n\n\tmbedtls_x509write_crt_free(&cert);\n\tmbedtls_mpi_free(&serial);\n\tmbedtls_pk_free(&key);\n\n\treturn 0;\n}\n\nint main(int argc, char *argv[])\n{\n\turandom_fd = open(\"/dev/urandom\", O_RDONLY);\n\n\tif (!argv[1]) {\n\t\t//Usage\n\t} else if (!strcmp(argv[1], \"eckey\")) {\n\t\treturn dokey(false, argv+2);\n\t} else if (!strcmp(argv[1], \"rsakey\")) {\n\t\treturn dokey(true, argv+2);\n\t} else if (!strcmp(argv[1], \"selfsigned\")) {\n\t\treturn selfsigned(argv+2);\n\t}\n\n\tfprintf(stderr,\n\t\t\"PX5G X.509 Certificate Generator Utility v\" PX5G_VERSION \"\\n\" PX5G_COPY\n\t\t\"\\nbased on PolarSSL by Christophe Devine and Paul Bakker\\n\\n\");\n\tfprintf(stderr, \"Usage: %s [eckey|rsakey|selfsigned]\\n\", *argv);\n\treturn 1;\n}\n"
  },
  {
    "path": "package/utils/px5g-wolfssl/Makefile",
    "content": "# Copyright (C) 2020 Paul Spooren <mail@aparcar.org>\n#\n# SPDX-License-Identifier: GPL-2.0-or-later\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=px5g-wolfssl\nPKG_RELEASE:=$(COMMITCOUNT)\nPKG_LICENSE:=GPL-2.0-or-later\n\nPKG_USE_MIPS16:=0\n\nPKG_MAINTAINER:=Paul Spooren <mail@aparcar.org>\n\nPKG_CONFIG_DEPENDS:=CONFIG_WOLFSSL_ALT_NAMES\n\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine Package/px5g-wolfssl\n  SECTION:=utils\n  CATEGORY:=Utilities\n  SUBMENU:=Encryption\n  TITLE:=X.509 certificate generator (using WolfSSL)\n  DEPENDS:=+libwolfssl\n  PROVIDES:=px5g\n  VARIANT:=wolfssl\nendef\n\ndefine Package/px5g-wolfssl/description\n Px5g is a tiny X.509 certificate generator.\n It suitable to create key files and certificates in DER\n and PEM format for use with stunnel, uhttpd and others.\nendef\n\nTARGET_LDFLAGS += -lwolfssl\n\n\nTARGET_CFLAGS += -Wl,--gc-sections\n\ndefine Build/Compile\n\t$(TARGET_CC) $(TARGET_CPPFLAGS) $(TARGET_CFLAGS) \\\n\t\t-o $(PKG_BUILD_DIR)/px5g px5g-wolfssl.c $(TARGET_LDFLAGS)\nendef\n\ndefine Package/px5g-wolfssl/install\n\t$(INSTALL_DIR) $(1)/usr/sbin\n\t$(INSTALL_BIN) $(PKG_BUILD_DIR)/px5g $(1)/usr/sbin/px5g\nendef\n\n$(eval $(call BuildPackage,px5g-wolfssl))\n"
  },
  {
    "path": "package/utils/px5g-wolfssl/px5g-wolfssl.c",
    "content": "// Copyright 2020 Paul Spooren <mail@aparcar.org>\n//\n// SPDX-License-Identifier: GPL-2.0-or-later\n\n#define _GNU_SOURCE\n#include <stdbool.h>\n#include <stdint.h>\n#include <stdio.h>\n#include <string.h>\n#include <wolfssl/options.h>\n#include <wolfssl/wolfcrypt/asn.h>\n#include <wolfssl/wolfcrypt/asn_public.h>\n#include <wolfssl/wolfcrypt/ecc.h>\n#include <wolfssl/wolfcrypt/error-crypt.h>\n#include <wolfssl/wolfcrypt/rsa.h>\n#include <wolfssl/wolfcrypt/settings.h>\n\n#define HEAP_HINT NULL\n#define FOURK_SZ 4096\n#define WOLFSSL_MIN_RSA_BITS 2048\n\nenum {\n  EC_KEY_TYPE = 0,\n  RSA_KEY_TYPE = 1,\n};\n\nint write_file(byte *buf, int bufSz, char *path) {\n  int ret;\n  FILE *file;\n  if (path) {\n    file = fopen(path, \"wb\");\n    if (file == NULL) {\n      perror(\"Error opening file\");\n      exit(1);\n    }\n  } else {\n    file = stdout;\n  }\n  ret = (int)fwrite(buf, 1, bufSz, file);\n  if (path) {\n    fclose(file);\n  }\n  if (ret > 0) {\n    /* ret > 0 indicates a successful file write, set to zero for return */\n    ret = 0;\n  }\n  return ret;\n}\n\nint write_key(ecc_key *ecKey, RsaKey *rsaKey, int type, int keySz, char *fName,\n              bool write_pem) {\n  int ret;\n  byte der[FOURK_SZ] = {};\n  byte pem[FOURK_SZ] = {};\n  int derSz, pemSz;\n  if (type == EC_KEY_TYPE) {\n    ret = wc_EccKeyToDer(ecKey, der, sizeof(der));\n  } else {\n    ret = wc_RsaKeyToDer(rsaKey, der, sizeof(der));\n  }\n  if (ret <= 0) {\n    fprintf(stderr, \"Key To DER failed: %d\\n\", ret);\n  }\n  derSz = ret;\n\n  if (write_pem) {\n    if (type == EC_KEY_TYPE) {\n      ret = wc_DerToPem(der, derSz, pem, sizeof(pem), ECC_PRIVATEKEY_TYPE);\n    } else {\n      ret = wc_DerToPem(der, derSz, pem, sizeof(pem), PRIVATEKEY_TYPE);\n    }\n    if (ret <= 0) {\n      fprintf(stderr, \"DER to PEM failed: %d\\n\", ret);\n    }\n    pemSz = ret;\n    ret = write_file(pem, pemSz, fName);\n  } else {\n    ret = write_file(der, derSz, fName);\n  }\n  return ret;\n}\n\nint gen_key(WC_RNG *rng, ecc_key *ecKey, RsaKey *rsaKey, int type, int keySz,\n            long exp, int curve) {\n  int ret;\n\n  if (type == EC_KEY_TYPE) {\n    ret = wc_ecc_init(ecKey);\n    (void)rsaKey;\n  } else {\n    ret = wc_InitRsaKey(rsaKey, NULL);\n    (void)ecKey;\n  }\n  if (ret != 0) {\n    fprintf(stderr, \"Key initialization failed: %d\\n\", ret);\n    return ret;\n  }\n\n  if (type == EC_KEY_TYPE) {\n    fprintf(stderr, \"Generating EC private key\\n\");\n    ret = wc_ecc_make_key_ex(rng, 32, ecKey, curve);\n  } else {\n    fprintf(stderr, \"Generating RSA private key, %i bit long modulus\\n\", keySz);\n    ret = wc_MakeRsaKey(rsaKey, keySz, WC_RSA_EXPONENT, rng);\n  }\n  if (ret != 0) {\n    fprintf(stderr, \"Key generation failed: %d\\n\", ret);\n  }\n  return ret;\n}\n\nint selfsigned(WC_RNG *rng, char **arg) {\n  ecc_key ecKey;\n  RsaKey rsaKey;\n  int ret;\n  char *subject = \"\";\n  int keySz = WOLFSSL_MIN_RSA_BITS;\n  int type = EC_KEY_TYPE;\n  int exp = WC_RSA_EXPONENT;\n  int curve = ECC_SECP256R1;\n  unsigned int days = 3653; // 10 years\n  char *keypath = NULL, *certpath = NULL;\n  char fstr[20], tstr[20];\n  bool pem = true;\n  Cert newCert;\n#ifdef __USE_TIME_BITS64\n  time_t to, from = time(NULL);\n#else\n  unsigned long to, from = time(NULL);\n#endif\n  byte derBuf[FOURK_SZ] = {};\n  byte pemBuf[FOURK_SZ] = {};\n  int pemSz = -1;\n  int derSz = -1;\n  char *key, *val, *tmp;\n\n  ret = wc_InitCert(&newCert);\n  if (ret != 0) {\n    fprintf(stderr, \"Init Cert failed: %d\\n\", ret);\n    return ret;\n  }\n  newCert.isCA = 0;\n\n  while (*arg && **arg == '-') {\n    if (!strncmp(*arg, \"-der\", 4)) {\n      pem = false;\n    } else if (!strncmp(*arg, \"-newkey\", 6) && arg[1]) {\n      if (!strncmp(arg[1], \"rsa:\", 4)) {\n        type = RSA_KEY_TYPE;\n        keySz = (unsigned int)atoi(arg[1] + 4);\n      } else if (!strncmp(arg[1], \"ec\", 2)) {\n        type = EC_KEY_TYPE;\n      } else {\n        fprintf(stderr, \"error: invalid algorithm\\n\");\n        return 1;\n      }\n      arg++;\n    } else if (!strncmp(*arg, \"-days\", 5) && arg[1]) {\n      days = (unsigned int)atoi(arg[1]);\n      arg++;\n    } else if (!strncmp(*arg, \"-pkeyopt\", 8) && arg[1]) {\n      if (strncmp(arg[1], \"ec_paramgen_curve:\", 18)) {\n        fprintf(stderr, \"error: invalid pkey option: %s\\n\", arg[1]);\n        return 1;\n      }\n      if (!strncmp(arg[1] + 18, \"P-256:\", 5)) {\n        curve = ECC_SECP256R1;\n      } else if (!strncmp(arg[1] + 18, \"P-384:\", 5)) {\n        curve = ECC_SECP384R1;\n      } else if (!strncmp(arg[1] + 18, \"P-521:\", 5)) {\n        curve = ECC_SECP521R1;\n      } else {\n        fprintf(stderr, \"error: invalid curve name: %s\\n\", arg[1] + 18);\n        return 1;\n      }\n      arg++;\n    } else if (!strncmp(*arg, \"-keyout\", 7) && arg[1]) {\n      keypath = arg[1];\n      arg++;\n    } else if (!strncmp(*arg, \"-out\", 4) && arg[1]) {\n      certpath = arg[1];\n      arg++;\n    } else if (!strcmp(*arg, \"-subj\") && arg[1]) {\n      subject = strdupa(arg[1]);\n      key = arg[1];\n      do {\n        tmp = strchr(key, '/');\n        if (tmp)\n          *tmp = '\\0';\n\n        val = strchr(key, '=');\n        if (val) {\n          *val = '\\0';\n          ++val;\n\n          if (!strcmp(key, \"C\"))\n            strncpy(newCert.subject.country, val, CTC_NAME_SIZE);\n          else if (!strcmp(key, \"ST\"))\n            strncpy(newCert.subject.state, val, CTC_NAME_SIZE);\n          else if (!strcmp(key, \"L\"))\n            strncpy(newCert.subject.locality, val, CTC_NAME_SIZE);\n          else if (!strcmp(key, \"O\"))\n            strncpy(newCert.subject.org, val, CTC_NAME_SIZE);\n          else if (!strcmp(key, \"OU\"))\n            strncpy(newCert.subject.unit, val, CTC_NAME_SIZE);\n          else if (!strcmp(key, \"CN\")) {\n            strncpy(newCert.subject.commonName, val, CTC_NAME_SIZE);\n\n#ifdef WOLFSSL_ALT_NAMES\n            if(strlen(val) + 2 > 256) {\n              fprintf(stderr, \"error: CN is too long: %s\\n\", val);\n              return 1;\n            }\n\n            newCert.altNames[0] = 0x30; //Sequence with one element\n            newCert.altNames[1] = strlen(val) + 2; // Length of entire sequence\n            newCert.altNames[2] = 0x82; //8 - String, 2 - DNS Name\n            newCert.altNames[3] = strlen(val); //DNS Name length\n            memcpy(newCert.altNames + 4, val, strlen(val)); //DNS Name\n            newCert.altNamesSz = strlen(val) + 4;\n#endif\n          }\n          else if (!strcmp(key, \"EMAIL\"))\n            strncpy(newCert.subject.email, val, CTC_NAME_SIZE);\n          else\n            printf(\"warning: unknown attribute %s=%s\\n\", key, val);\n        }\n      } while (tmp && (key = ++tmp));\n    }\n    arg++;\n  }\n  newCert.daysValid = days;\n\n  newCert.keyUsage = KEYUSE_DIGITAL_SIG | KEYUSE_CONTENT_COMMIT | KEYUSE_KEY_ENCIPHER;\n  newCert.extKeyUsage = EXTKEYUSE_SERVER_AUTH;\n\n  gen_key(rng, &ecKey, &rsaKey, type, keySz, exp, curve);\n  write_key(&ecKey, &rsaKey, type, keySz, keypath, pem);\n\n  from = (from < 1000000000) ? 1000000000 : from;\n  strftime(fstr, sizeof(fstr), \"%Y%m%d%H%M%S\", gmtime(&from));\n  to = from + 60 * 60 * 24 * days;\n  if (to < from)\n    to = INT_MAX;\n  strftime(tstr, sizeof(tstr), \"%Y%m%d%H%M%S\", gmtime(&to));\n\n  fprintf(stderr,\n          \"Generating selfsigned certificate with subject '%s'\"\n          \" and validity %s-%s\\n\",\n          subject, fstr, tstr);\n\n  if (type == EC_KEY_TYPE) {\n    newCert.sigType = CTC_SHA256wECDSA;\n    ret = wc_MakeCert(&newCert, derBuf, sizeof(derBuf), NULL, &ecKey, rng);\n  } else {\n    newCert.sigType = CTC_SHA256wRSA;\n    ret = wc_MakeCert(&newCert, derBuf, sizeof(derBuf), &rsaKey, NULL, rng);\n  }\n  if (ret <= 0) {\n    fprintf(stderr, \"Make Cert failed: %d\\n\", ret);\n    return ret;\n  }\n\n  if (type == EC_KEY_TYPE) {\n    ret = wc_SignCert(newCert.bodySz, newCert.sigType, derBuf, sizeof(derBuf),\n                      NULL, &ecKey, rng);\n  } else {\n    ret = wc_SignCert(newCert.bodySz, newCert.sigType, derBuf, sizeof(derBuf),\n                      &rsaKey, NULL, rng);\n  }\n  if (ret <= 0) {\n    fprintf(stderr, \"Sign Cert failed: %d\\n\", ret);\n    return ret;\n  }\n  derSz = ret;\n\n  ret = wc_DerToPem(derBuf, derSz, pemBuf, sizeof(pemBuf), CERT_TYPE);\n  if (ret <= 0) {\n    fprintf(stderr, \"DER to PEM failed: %d\\n\", ret);\n    return ret;\n  }\n  pemSz = ret;\n\n  ret = write_file(pemBuf, pemSz, certpath);\n  if (ret != 0) {\n    fprintf(stderr, \"Write Cert failed: %d\\n\", ret);\n    return ret;\n  }\n\n  if (type == EC_KEY_TYPE) {\n    wc_ecc_free(&ecKey);\n  } else {\n    wc_FreeRsaKey(&rsaKey);\n  }\n  return 0;\n}\n\nint dokey(WC_RNG *rng, int type, char **arg) {\n  ecc_key ecKey;\n  RsaKey rsaKey;\n  int ret;\n  int curve = ECC_SECP256R1;\n  int keySz = WOLFSSL_MIN_RSA_BITS;\n  int exp = WC_RSA_EXPONENT;\n  char *path = NULL;\n  bool pem = true;\n\n  while (*arg && **arg == '-') {\n    if (!strncmp(*arg, \"-out\", 4) && arg[1]) {\n      path = arg[1];\n      arg++;\n    } else if (!strncmp(*arg, \"-3\", 2)) {\n      exp = 3;\n    } else if (!strncmp(*arg, \"-der\", 4)) {\n      pem = false;\n    }\n    arg++;\n  }\n\n  if (*arg && type == RSA_KEY_TYPE) {\n    keySz = (unsigned int)atoi(*arg);\n  } else if (*arg) {\n    if (!strncmp(*arg, \"P-256\", 5)) {\n      curve = ECC_SECP256R1;\n    } else if (!strncmp(*arg, \"P-384\", 5)) {\n      curve = ECC_SECP384R1;\n    } else if (!strncmp(*arg, \"P-521\", 5)) {\n      curve = ECC_SECP521R1;\n    } else {\n      fprintf(stderr, \"Invalid Curve Name: %s\\n\", *arg);\n      return 1;\n    }\n  }\n\n  ret = gen_key(rng, &ecKey, &rsaKey, type, keySz, exp, curve);\n  if (ret != 0)\n    return ret;\n\n  ret = write_key(&ecKey, &rsaKey, type, keySz, path, pem);\n\n  if (type == EC_KEY_TYPE) {\n    wc_ecc_free(&ecKey);\n  } else {\n    wc_FreeRsaKey(&rsaKey);\n  }\n  return ret;\n}\n\nint main(int argc, char *argv[]) {\n  int ret;\n  WC_RNG rng;\n  ret = wc_InitRng(&rng);\n  if (ret != 0) {\n    fprintf(stderr, \"Init Rng failed: %d\\n\", ret);\n    return ret;\n  }\n\n  if (argv[1]) {\n    if (!strncmp(argv[1], \"eckey\", 5))\n      return dokey(&rng, EC_KEY_TYPE, argv + 2);\n\n    if (!strncmp(argv[1], \"rsakey\", 5))\n      return dokey(&rng, RSA_KEY_TYPE, argv + 2);\n\n    if (!strncmp(argv[1], \"selfsigned\", 10))\n      return selfsigned(&rng, argv + 2);\n  }\n\n  fprintf(stderr, \"PX5G X.509 Certificate Generator Utilit using WolfSSL\\n\\n\");\n  fprintf(stderr, \"Usage: [eckey|rsakey|selfsigned]\\n\");\n  return 1;\n}\n"
  },
  {
    "path": "package/utils/ravpower-mcu/Makefile",
    "content": "include $(TOPDIR)/rules.mk\n\nPKG_NAME:=ravpower-mcu\nPKG_RELEASE:=2\n\nPKG_SOURCE_PROTO:=git\nPKG_SOURCE_URL=https://github.com/blocktrron/ravpower-mcu.git\nPKG_MIRROR_HASH:=edde0fda3fc708eac65baff46b5b6f1290ab733d3f4bd7fc027ef45c3d1b5814\nPKG_SOURCE_DATE:=2020-06-19\nPKG_SOURCE_VERSION:=1665d9e9212dcd118629a74fbe658841f81036f7\nPKG_MAINTAINER:=David Bauer <mail@david-bauer.net>\nPKG_LICENSE:=GPL-2.0-or-later\n\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine Package/ravpower-mcu\n  SECTION:=utils\n  CATEGORY:=Utilities\n  TITLE:=Utility to control the RAVPower RP-WD009 PMIC\n  URL:=https://github.com/blocktrron/ravpower-mcu/\nendef\n\ndefine Build/Compile\n\t$(MAKE) -C $(PKG_BUILD_DIR) \\\n\t\tCC=\"$(TARGET_CC)\" \\\n\t\tCFLAGS=\"$(TARGET_CFLAGS) -Wall\"\nendef\n\ndefine Package/ravpower-mcu/install\n\t$(INSTALL_DIR) $(1)/usr/bin\n\t$(INSTALL_BIN) $(PKG_BUILD_DIR)/out/ravpower-mcu $(1)/usr/bin/\nendef\n\n$(eval $(call BuildPackage,ravpower-mcu))\n"
  },
  {
    "path": "package/utils/secilc/Makefile",
    "content": "#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=secilc\nPKG_VERSION:=3.3\nPKG_RELEASE:=1\n\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz\nPKG_SOURCE_URL:=https://github.com/SELinuxProject/selinux/releases/download/$(PKG_VERSION)\nPKG_HASH:=2c5e1a5d417baf1d2aa3eac294e12c3aac7184a5ef6a779dcbe469ed756e8651\nHOST_BUILD_DEPENDS:=libsepol/host\n\nPKG_MAINTAINER:=Dominick Grift <dominick.grift@defensec.nl>\nPKG_CPE_ID:=cpe:/a:selinuxproject:secilc\nPKG_LICENSE:=BSD-2-Clause\nPKG_LICENSE_FILES:=COPYING\n\ninclude $(INCLUDE_DIR)/host-build.mk\ninclude $(INCLUDE_DIR)/nls.mk\ninclude $(INCLUDE_DIR)/package.mk\n\nHOST_LDFLAGS+=-Wl,-rpath=$(STAGING_DIR_HOSTPKG)/lib\nHOST_MAKE_FLAGS += \\\n\tDESTDIR=$(STAGING_DIR_HOSTPKG) \\\n\tPREFIX=\n\ndefine Package/secilc\n\tSECTION:=utils\n\tCATEGORY:=Utilities\n\tTITLE:=SELinux Common Intermediate Language (CIL) Compiler\n\tURL:=http://selinuxproject.org/page/Main_Page\n\tDEPENDS:=+libsepol\nendef\n\ndefine Package/secilc/description\n\tThe SELinux CIL Compiler is a compiler that converts the CIL language as\n\tdescribed on the CIL design wiki into a kernel binary policy file.\n\tPlease see the CIL Design Wiki at:\n\thttp://github.com/SELinuxProject/cil/wiki/\n\tfor more information about the goals and features on the CIL language.\nendef\n\ndefine Build/Compile\n\t$(call Build/Compile/Default,secilc)\nendef\n\ndefine Host/Compile\n\t$(call Host/Compile/Default,secilc)\nendef\n\ndefine Host/Install\n\t$(INSTALL_DIR) $(STAGING_DIR_HOSTPKG)/bin\n\t$(INSTALL_BIN) $(HOST_BUILD_DIR)/secilc $(STAGING_DIR_HOSTPKG)/bin\nendef\n\ndefine Package/secilc/install\n\t$(INSTALL_DIR) $(1)/usr/bin\n\t$(INSTALL_BIN) $(PKG_BUILD_DIR)/secilc $(1)/usr/bin\nendef\n\n$(eval $(call BuildPackage,secilc))\n$(eval $(call HostBuild))\n"
  },
  {
    "path": "package/utils/spidev_test/Makefile",
    "content": "#\n# Copyright (C) 2009 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\ninclude $(INCLUDE_DIR)/kernel.mk\n\nPKG_NAME:=spidev-test\nPKG_RELEASE:=$(LINUX_VERSION)\nPKG_FLAGS:=nonshared\nPKG_BUILD_DIR:=$(LINUX_DIR)/tools/spi-$(TARGET_DIR_NAME)\nPKG_BUILD_PARALLEL:=1\n\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine Package/spidev-test\n  SECTION:=utils\n  CATEGORY:=Utilities\n  DEPENDS:=+kmod-spi-dev @!IN_SDK\n  TITLE:=SPI testing utility\n  VERSION:=$(LINUX_VERSION)-$(PKG_RELEASE)\n  URL:=http://www.kernel.org\nendef\n\ndefine Package/spidev-test/description\n  SPI testing utility.\nendef\n\ndefine Build/Prepare\n\t$(CP) $(LINUX_DIR)/tools/spi/* $(PKG_BUILD_DIR)/\nendef\n\nMAKE_FLAGS = \\\n\tARCH=\"$(LINUX_KARCH)\" \\\n\tCROSS_COMPILE=\"$(TARGET_CROSS)\" \\\n\tCC=\"$(TARGET_CC)\" \\\n\tLD=\"$(TARGET_CROSS)ld\" \\\n\tCFLAGS=\"$(TARGET_CFLAGS) $(TARGET_CPPFLAGS)\" \\\n\tLDFLAGS=\"$(TARGET_LDFLAGS)\" \\\n\t$(if $(findstring c,$(OPENWRT_VERBOSE)),V=1,V='') \\\n\tWERROR=0 \\\n\tprefix=/usr\n\ndefine Build/Compile\n\t+$(MAKE_FLAGS) $(MAKE) $(PKG_JOBS) \\\n\t\t-C $(PKG_BUILD_DIR) \\\n\t\t-f Makefile \\\n\t\t--no-print-directory\nendef\n\ndefine Package/spidev-test/install\n\t$(INSTALL_DIR) $(1)/sbin\n\t$(INSTALL_BIN) $(PKG_BUILD_DIR)/spidev_test $(1)/sbin/\nendef\n\n$(eval $(call BuildPackage,spidev-test))\n"
  },
  {
    "path": "package/utils/ucode/Makefile",
    "content": "#\n# Copyright (C) 2020-2021 Jo-Philipp Wich <jo@mein.io>\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=ucode\nPKG_RELEASE:=1\n\nPKG_SOURCE_PROTO:=git\nPKG_SOURCE_URL=https://github.com/jow-/ucode.git\nPKG_SOURCE_DATE:=2022-04-13\nPKG_SOURCE_VERSION:=e14b0993b101839d2d40b5c4f184e6b0c2083b65\nPKG_MIRROR_HASH:=50771ea70be071626cfb682627713f818d740bc91ccadad0ba0aad5bef08a865\nPKG_MAINTAINER:=Jo-Philipp Wich <jo@mein.io>\nPKG_LICENSE:=ISC\n\nPKG_ABI_VERSION:=20220322\n\ninclude $(INCLUDE_DIR)/package.mk\ninclude $(INCLUDE_DIR)/cmake.mk\n\nCMAKE_OPTIONS += -DSOVERSION=$(PKG_ABI_VERSION)\n\ndefine Package/ucode/default\n  SECTION:=utils\n  CATEGORY:=Utilities\n  TITLE:=ucode - Tiny scripting and templating language\nendef\n\ndefine Package/ucode\n  $(Package/ucode/default)\n  DEPENDS:=+libucode\nendef\n\ndefine Package/ucode/description\n ucode is a tiny script interpreter featuring an ECMAScript oriented\n script language and Jinja-inspired templating.\nendef\n\n\ndefine Package/libucode\n  $(Package/ucode/default)\n  TITLE+= - runtime library\n  ABI_VERSION:=$(PKG_ABI_VERSION)\n  DEPENDS:=+libjson-c\nendef\n\ndefine Package/libucode/description\n The libucode package provides the shared runtime library for the ucode interpreter.\nendef\n\n\ndefine Package/ucode-mod-fs\n  $(Package/ucode/default)\n  TITLE+= (filesystem module)\n  DEPENDS:=ucode\nendef\n\ndefine Package/ucode-mod-fs/description\n The filesystem plugin module allows interaction with the local file system.\nendef\n\n\ndefine Package/ucode-mod-math\n  $(Package/ucode/default)\n  TITLE+= (math module)\n  DEPENDS:=ucode\nendef\n\ndefine Package/ucode-mod-math/description\n The math plugin provides access to various <math.h> procedures.\nendef\n\n\ndefine Package/ucode-mod-nl80211\n  $(Package/ucode/default)\n  TITLE+= (nl80211 module)\n  DEPENDS:=ucode +libnl-tiny\nendef\n\ndefine Package/ucode-mod-nl80211/description\n The nl80211 plugin provides access to the Linux wireless 802.11 netlink API.\nendef\n\n\ndefine Package/ucode-mod-resolv\n  $(Package/ucode/default)\n  TITLE+= (resolv module)\n  DEPENDS:=ucode\nendef\n\ndefine Package/ucode-mod-resolv/description\n The resolv plugin implements simple DNS resolving.\nendef\n\n\ndefine Package/ucode-mod-rtnl\n  $(Package/ucode/default)\n  TITLE+= (rtnl module)\n  DEPENDS:=ucode +libnl-tiny\nendef\n\ndefine Package/ucode-mod-rtnl/description\n The rtnl plugin provides access to the Linux routing netlink API.\nendef\n\n\ndefine Package/ucode-mod-struct\n  $(Package/ucode/default)\n  TITLE+= (struct module)\n  DEPENDS:=ucode\nendef\n\ndefine Package/ucode-mod-struct/description\n The struct plugin implemnts Python 3 compatible struct.pack/unpack functionality.\nendef\n\n\ndefine Package/ucode-mod-ubus\n  $(Package/ucode/default)\n  TITLE+= (ubus module)\n  DEPENDS:=ucode +libubus +libblobmsg-json\nendef\n\ndefine Package/ucode-mod-ubus/description\n The ubus module allows ucode template scripts to enumerate and invoke ubus\n procedures.\nendef\n\n\ndefine Package/ucode-mod-uci\n  $(Package/ucode/default)\n  TITLE+= (uci module)\n  DEPENDS:=ucode +libuci\nendef\n\ndefine Package/ucode-mod-uci/description\n The uci module allows templates to read and modify uci configuration.\nendef\n\n\ndefine Build/InstallDev\n\t$(INSTALL_DIR) $(1)/usr/lib $(1)/usr/include/ucode\n\t$(CP) $(PKG_INSTALL_DIR)/usr/include/ucode/*.h $(1)/usr/include/ucode/\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/libucode.so* $(1)/usr/lib/\nendef\n\n\ndefine Package/ucode/install\n\t$(INSTALL_DIR) $(1)/usr/bin\n\t$(CP) $(PKG_INSTALL_DIR)/usr/bin/u* $(1)/usr/bin/\nendef\n\ndefine Package/libucode/install\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/libucode.so.* $(1)/usr/lib/\nendef\n\ndefine Package/ucode-mod-fs/install\n\t$(INSTALL_DIR) $(1)/usr/lib/ucode\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/lib/ucode/fs.so $(1)/usr/lib/ucode/\nendef\n\ndefine Package/ucode-mod-math/install\n\t$(INSTALL_DIR) $(1)/usr/lib/ucode\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/lib/ucode/math.so $(1)/usr/lib/ucode/\nendef\n\ndefine Package/ucode-mod-nl80211/install\n\t$(INSTALL_DIR) $(1)/usr/lib/ucode\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/lib/ucode/nl80211.so $(1)/usr/lib/ucode/\nendef\n\ndefine Package/ucode-mod-resolv/install\n\t$(INSTALL_DIR) $(1)/usr/lib/ucode\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/lib/ucode/resolv.so $(1)/usr/lib/ucode/\nendef\n\ndefine Package/ucode-mod-rtnl/install\n\t$(INSTALL_DIR) $(1)/usr/lib/ucode\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/lib/ucode/rtnl.so $(1)/usr/lib/ucode/\nendef\n\ndefine Package/ucode-mod-struct/install\n\t$(INSTALL_DIR) $(1)/usr/lib/ucode\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/lib/ucode/struct.so $(1)/usr/lib/ucode/\nendef\n\ndefine Package/ucode-mod-ubus/install\n\t$(INSTALL_DIR) $(1)/usr/lib/ucode\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/lib/ucode/ubus.so $(1)/usr/lib/ucode/\nendef\n\ndefine Package/ucode-mod-uci/install\n\t$(INSTALL_DIR) $(1)/usr/lib/ucode\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/lib/ucode/uci.so $(1)/usr/lib/ucode/\nendef\n\n\n$(eval $(call BuildPackage,libucode))\n$(eval $(call BuildPackage,ucode))\n$(eval $(call BuildPackage,ucode-mod-fs))\n$(eval $(call BuildPackage,ucode-mod-math))\n$(eval $(call BuildPackage,ucode-mod-nl80211))\n$(eval $(call BuildPackage,ucode-mod-resolv))\n$(eval $(call BuildPackage,ucode-mod-rtnl))\n$(eval $(call BuildPackage,ucode-mod-struct))\n$(eval $(call BuildPackage,ucode-mod-ubus))\n$(eval $(call BuildPackage,ucode-mod-uci))\n"
  },
  {
    "path": "package/utils/ugps/Makefile",
    "content": "#\n# Copyright (C) 2014 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=ugps\nPKG_RELEASE:=$(AUTORELEASE)\n\nPKG_SOURCE_URL=$(PROJECT_GIT)/project/ugps.git\nPKG_SOURCE_PROTO:=git\nPKG_SOURCE_DATE:=2021-06-08\nPKG_SOURCE_VERSION:=5e88403fc0d39ae8a270d2c6c6e9c8a4d5232cf3\nPKG_MIRROR_HASH:=a3dfc2cc6def3b634d8b7cda9139926be3d876cf2faa5251c4821987954442a5\n\nPKG_MAINTAINER:=John Crispin <john@phrozen.org>\nPKG_LICENSE:=GPL-2.0+\n\ninclude $(INCLUDE_DIR)/package.mk\ninclude $(INCLUDE_DIR)/cmake.mk\n\ndefine Package/ugps\n  SECTION:=utils\n  CATEGORY:=Utilities\n  TITLE:=OpenWrt GPS Daemon\n  DEPENDS:=+libubox +libubus\nendef\n\nTARGET_CFLAGS += -I$(STAGING_DIR)/usr/include\n\ndefine Package/ugps/conffiles\n/etc/config/gps\nendef\n\ndefine Package/ugps/install\n\t$(INSTALL_DIR) $(1)/usr/sbin $(1)/etc/init.d $(1)/etc/config\n\t$(INSTALL_BIN) $(PKG_BUILD_DIR)/ugps $(1)/usr/sbin/\n\t$(INSTALL_BIN) ./files/ugps.init $(1)/etc/init.d/ugps\n\t$(INSTALL_CONF) ./files/gps.config $(1)/etc/config/gps\nendef\n\n$(eval $(call BuildPackage,ugps))\n"
  },
  {
    "path": "package/utils/ugps/files/gps.config",
    "content": "config gps\n\toption\t'tty'\t'ttyACM0'\n\toption\t'adjust_time'\t'1'\n\toption\t'disabled'\t'1'\n"
  },
  {
    "path": "package/utils/ugps/files/ugps.init",
    "content": "#!/bin/sh /etc/rc.common\n# Copyright (c) 2014 OpenWrt.org\n\nSTART=80\n\nUSE_PROCD=1\nPROG=/usr/sbin/ugps\n\nservice_triggers() {\n\tprocd_add_reload_trigger gps\n}\n\nstart_service() {\n\tlocal tty=\"$(uci get gps.@gps[-1].tty)\"\n\tlocal atime=\"$(uci get gps.@gps[-1].adjust_time)\"\n\tlocal disabled=\"$(uci get gps.@gps[-1].disabled || echo 0)\"\n\n\t[ \"$disabled\" == \"0\" ] || return\n\t[ \"$tty\" ] || return\n\n\tcase \"$tty\" in\n\t\t\"/\"*)\n\t\t\ttrue\n\t\t\t;;\n\t\t*)\n\t\t\ttty=\"/dev/$tty\"\n\t\t\t;;\n\tesac\n\n\tprocd_open_instance\n\tprocd_set_param command \"$PROG\"\n\t[ \"$atime\" -eq 0 ] || procd_append_param command \"-a\"\n\tprocd_append_param command \"$tty\"\n\tprocd_set_param respawn\n\tprocd_close_instance\n}\n"
  },
  {
    "path": "package/utils/usbmode/Makefile",
    "content": "include $(TOPDIR)/rules.mk\n\nPKG_NAME:=usbmode\nPKG_RELEASE:=1\n\nPKG_SOURCE_PROTO:=git\nPKG_SOURCE_URL=$(PROJECT_GIT)/project/usbmode.git\nPKG_SOURCE_DATE:=2022-02-24\nPKG_SOURCE_VERSION:=3c8595a4e75510f58fa231b145d5506768dcafc9\nPKG_MIRROR_HASH:=5f0234945f61639080f039522172151452180dd4aec33bafc8a61b60131c3bed\nCMAKE_INSTALL:=1\n\nPKG_LICENSE:=GPL-2.0\nPKG_LICENSE_FILES:=\n\nPKG_MAINTAINER:=Felix Fietkau <nbd@nbd.name>\n\nPKG_DATA_VERSION:=20191128\nPKG_DATA_URL:=http://www.draisberghof.de/usb_modeswitch\nPKG_DATA_PATH:=usb-modeswitch-data-$(PKG_DATA_VERSION)\nPKG_DATA_FILENAME:=$(PKG_DATA_PATH).tar.bz2\n\ninclude $(INCLUDE_DIR)/package.mk\ninclude $(INCLUDE_DIR)/cmake.mk\n\ndefine Download/data\n  FILE:=$(PKG_DATA_FILENAME)\n  URL:=$(PKG_DATA_URL)\n  HASH:=3f039b60791c21c7cb15c7986cac89650f076dc274798fa242231b910785eaf9\nendef\n$(eval $(call Download,data))\n\ndefine Package/usb-modeswitch\n  SECTION:=utils\n  CATEGORY:=Utilities\n  DEPENDS:=+libubox +libblobmsg-json +libusb-1.0\n  TITLE:=USB mode switching utility\nendef\n\ndefine Build/Prepare\n\t$(Build/Prepare/Default)\n\ttar xvfj $(DL_DIR)/$(PKG_DATA_FILENAME) -C $(PKG_BUILD_DIR)\n\t#remove devices with unsupported modes\n\tfor filevar in $(PKG_BUILD_DIR)/$(PKG_DATA_PATH)/usb_modeswitch.d/* ; \\\n\tdo \\\n\t\tif grep -q -E '(Quanta|Option|Blackberry|Pantech)Mode' \"$$$$filevar\" ; then \\\n\t\t\trm \"$$$$filevar\" ; \\\n\t\tfi \\\n\tdone\n\tcp ./data/* $(PKG_BUILD_DIR)/$(PKG_DATA_PATH)/usb_modeswitch.d/\n\t#in order to keep the Lede GIT repo free of filenames with colons,\n\t#we name the files xxxx-yyyy\n\t# and rename here after copying to the build directory\n\tfor filevar in $(PKG_BUILD_DIR)/$(PKG_DATA_PATH)/usb_modeswitch.d/*-* ; \\\n\tdo \\\n\t\t[ -f \"$$$$filevar\" ] || continue ; \\\n\t\tFILENAME=$$$$(basename $$$$filevar) ; \\\n\t\tNEWNAME=$$$${FILENAME//-/:} ; \\\n\t\trm \"$(PKG_BUILD_DIR)/$(PKG_DATA_PATH)/usb_modeswitch.d/$$$$NEWNAME\" ; \\\n\t\tmv \"$(PKG_BUILD_DIR)/$(PKG_DATA_PATH)/usb_modeswitch.d/$$$$FILENAME\" \"$(PKG_BUILD_DIR)/$(PKG_DATA_PATH)/usb_modeswitch.d/$$$$NEWNAME\" ; \\\n\tdone\nendef\n\ndefine Package/usb-modeswitch/install\n\t$(INSTALL_DIR) $(1)/etc/hotplug.d/usb $(1)/etc/init.d $(1)/sbin\n\tperl $(PKG_BUILD_DIR)/convert-modeswitch.pl \\\n\t\t$(PKG_BUILD_DIR)/$(PKG_DATA_PATH)/usb_modeswitch.d/* \\\n\t\t> $(1)/etc/usb-mode.json\n\t$(INSTALL_CONF) ./files/usbmode.hotplug $(1)/etc/hotplug.d/usb/20-usb_mode\n\t$(INSTALL_BIN) ./files/usbmode.init $(1)/etc/init.d/usbmode\n\t$(CP) $(PKG_INSTALL_DIR)/usr/sbin/usbmode $(1)/sbin/\nendef\n\n$(eval $(call BuildPackage,usb-modeswitch))\n"
  },
  {
    "path": "package/utils/usbmode/data/12d1-1f16",
    "content": "# Vodafone K5150\nMBIM=1\n"
  },
  {
    "path": "package/utils/usbmode/files/usbmode.hotplug",
    "content": "/etc/init.d/usbmode start\n"
  },
  {
    "path": "package/utils/usbmode/files/usbmode.init",
    "content": "#!/bin/sh /etc/rc.common\n# Copyright (C) 2013 OpenWrt.org\n\nSTART=20\nUSE_PROCD=1\n\nstart_service()\n{\n\tprocd_open_instance\n\tprocd_set_param command \"/sbin/usbmode\" -s\n\tprocd_close_instance\n}\n"
  },
  {
    "path": "package/utils/util-linux/Makefile",
    "content": "#\n# Copyright (C) 2007-2018 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=util-linux\nPKG_VERSION:=2.38\nPKG_RELEASE:=$(AUTORELEASE)\n\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz\nPKG_SOURCE_URL:=@KERNEL/linux/utils/$(PKG_NAME)/v2.38\nPKG_HASH:=6d111cbe4d55b336db2f1fbeffbc65b89908704c01136371d32aa9bec373eb64\nPKG_CPE_ID:=cpe:/a:kernel:util-linux\n\nPKG_LICENSE:=GPL-2.0-only\nPKG_LICENSE_FILES:=\tCOPYING\t\t\t\t\t\\\n\t\t\tlibblkid/COPYING\t\t\t\\\n\t\t\tlibmount/COPYING\t\t\t\\\n\t\t\tDocumentation/licenses/COPYING.GPLv2\t\\\n\t\t\tDocumentation/licenses/COPYING.LGPLv2.1\t\\\n\t\t\tlibuuid/COPYING\t\t\t\t\\\n\t\t\tDocumentation/licenses/COPYING.BSD-3\n\nPKG_INSTALL:=1\n\ninclude $(INCLUDE_DIR)/package.mk\ninclude $(INCLUDE_DIR)/meson.mk\n\ndefine Package/util-linux/Default\n  SECTION:=utils\n  CATEGORY:=Utilities\n  DEPENDS:= +librt\n  URL:=http://www.kernel.org/pub/linux/utils/util-linux/\nendef\n\ndefine Package/libblkid\n$(call Package/util-linux/Default)\n  DEPENDS:=+libuuid\n  TITLE:=block device id library\n  SECTION:=libs\n  CATEGORY:=Libraries\n  ABI_VERSION:=1\nendef\n\ndefine Package/libblkid/description\n The libblkid library is used to identify block devices (disks) as to their\n content (e.g. filesystem type, partitions) as well as extracting additional\n information such as filesystem labels/volume names, partitions, unique\n identifiers/serial numbers...\nendef\n\ndefine Package/libfdisk\n$(call Package/util-linux/Default)\n  DEPENDS:=+libuuid +libblkid\n  TITLE:=partition manipulating library\n  SECTION:=libs\n  CATEGORY:=Libraries\n  ABI_VERSION:=1\nendef\n\ndefine Package/libfdisk/description\n  The libfdisk library is used for manipulating with partition tables.\nendef\n\ndefine Package/libmount\n$(call Package/util-linux/Default)\n  DEPENDS:=+libblkid\n  TITLE:=mount library\n  SECTION:=libs\n  CATEGORY:=Libraries\n  ABI_VERSION:=1\nendef\n\ndefine Package/libmount/description\n The libmount library is used to parse /etc/fstab, /etc/mtab and\n /proc/self/mountinfo files, manage the mtab file, evaluate mount options...\nendef\n\ndefine Package/libuuid\n$(call Package/util-linux/Default)\n  TITLE:=DCE compatible Universally Unique Identifier library\n  SECTION:=libs\n  CATEGORY:=Libraries\n  ABI_VERSION:=1\nendef\n\ndefine Package/libuuid/description\n The UUID library is used to generate unique identifiers for objects\n that may be accessible beyond the local system. This library\n generates UUIDs compatible with those created by the Open Software\n Foundation (OSF) Distributed Computing Environment (DCE) utility.\nendef\n\ndefine Package/libsmartcols\n$(call Package/util-linux/Default)\n  TITLE:=table or tree library\n  SECTION:=libs\n  CATEGORY:=Libraries\n  ABI_VERSION:=1\nendef\n\ndefine Package/libsmartcols/description\n The smartcols library is used to print tables and trees in a pretty way.\nendef\n\ndefine Package/agetty\n$(call Package/util-linux/Default)\n  TITLE:=alternative Linux getty\n  SUBMENU=Terminal\nendef\n\ndefine Package/agetty/description\n agetty opens a tty port, prompts for a login name and invokes the\n /bin/login command\nendef\n\ndefine Package/blkdiscard\n$(call Package/util-linux/Default)\n  TITLE:=discard sectors on a device\n  SUBMENU=Disc\n  DEPENDS:=libblkid\nendef\n\ndefine Package/blkdiscard/description\n The blkdiscard is used to discard device sectors. This is useful for\n solid-state drivers (SSDs) and thinly-provisioned storage. Unlike fstrim,\n this command is used directly on the block device.\nendef\n\ndefine Package/blkid\n$(call Package/util-linux/Default)\n  TITLE:=locate and print block device attributes\n  DEPENDS:= +libblkid +libuuid\n  SUBMENU=Disc\nendef\n\ndefine Package/blkid/description\n The blkid program is the command-line interface to working with the libblkid\n library.\nendef\n\ndefine Package/blockdev\n$(call Package/util-linux/Default)\n  TITLE:=call block device ioctls from the command line\n  SUBMENU=Disc\nendef\n\ndefine Package/blockdev/description\n The blockdev program is the command-line interface to call block device ioctls.\nendef\n\ndefine Package/cal\n$(call Package/util-linux/Default)\n  TITLE:=display a calendar\n  DEPENDS:= +libncurses\nendef\n\ndefine Package/cal/description\n cal displays a simple calendar\nendef\n\ndefine Package/cfdisk\n$(call Package/util-linux/Default)\n  TITLE:=display or manipulate disk partition table\n  DEPENDS:= +libblkid +libncurses +libsmartcols +libfdisk +libmount\n  SUBMENU:=Disc\nendef\n\ndefine Package/cfdisk/description\n cfdisk is a curses-based program for partitioning any hard disk drive\nendef\n\ndefine Package/dmesg\n$(call Package/util-linux/Default)\n  TITLE:=print or control the kernel ring buffer\n  DEPENDS:= +libncursesw\nendef\n\ndefine Package/dmesg/description\n dmesg  is used to examine or control the kernel ring buffer\nendef\n\ndefine Package/eject\n$(call Package/util-linux/Default)\n  TITLE:=eject removable media\n  DEPENDS:= +libblkid +libmount +libuuid\n  SUBMENU=Disc\nendef\n\ndefine Package/eject/description\n  eject allows removable media (typically a CD-ROM, floppy disk, tape, or JAZ\n  or ZIP disk) to be ejected under software control.\nendef\n\ndefine Package/fdisk\n$(call Package/util-linux/Default)\n  TITLE:=manipulate disk partition table\n  DEPENDS:= +libblkid +libsmartcols +libfdisk +libncursesw\n  SUBMENU=Disc\nendef\n\ndefine Package/fdisk/description\n a menu-driven program for creation and manipulation of partition tables\nendef\n\ndefine Package/findfs\n$(call Package/util-linux/Default)\n  TITLE:=find a filesystem by label or UUID\n  DEPENDS:= +libblkid\n  SUBMENU=Disc\nendef\n\ndefine Package/findfs/description\n findfs will search the disks in the system looking for a filesystem which has\n a label matching label or a UUID equal to uuid\nendef\n\ndefine Package/flock\n$(call Package/util-linux/Default)\n  TITLE:=manage locks from shell scripts\n  ALTERNATIVES:=200:/usr/bin/flock:/usr/bin/util-linux-flock\nendef\n\ndefine Package/flock/description\n  manages flock locks from within shell scripts or the command line\nendef\n\ndefine Package/fstrim\n$(call Package/util-linux/Default)\n  TITLE:=discard unused blocks on a mounted filesystem\n  DEPENDS:= +libblkid +libuuid +libsmartcols +libmount\n  SUBMENU=Filesystem\nendef\n\ndefine Package/fstrim/description\n  fstrim is used on a mounted filesystem to discard (or \"trim\") blocks\n  which are not in use by the filesystem.  This is useful for solid-\n  state drives (SSDs) and thinly-provisioned storage.\nendef\n\ndefine Package/getopt\n$(call Package/util-linux/Default)\n  TITLE:=parse command options (enhanced)\nendef\n\ndefine Package/getopt/description\n getopt is used to break up (parse) options in command lines for easy parsing\n by shell procedures, and to check for legal options\nendef\n\ndefine Package/hwclock\n$(call Package/util-linux/Default)\n  TITLE:=query or set the hardware clock\nendef\n\ndefine Package/hwclock/description\n hwclock is a tool for accessing the Hardware Clock\nendef\n\ndefine Package/ipcs\n$(call Package/util-linux/Default)\n  TITLE:=show information on IPC facilities\nendef\n\ndefine Package/ipcs/description\n  ipcs shows information on the inter-process communication facilities for\n  which the calling process has read access. By default it shows information\n  about all three resources: shared memory segments, message queues, and\n  semaphore arrays.\nendef\n\ndefine Package/logger\n$(call Package/util-linux/Default)\n  TITLE:=a shell command interface to the syslog system log module\n  ALTERNATIVES:=200:/usr/bin/logger:/usr/bin/util-linux-logger\nendef\n\ndefine Package/logger/description\n logger makes entries in the system log, it provides a shell command interface\n to the syslog system log module\nendef\n\ndefine Package/look\n$(call Package/util-linux/Default)\n  TITLE:=display lines beginning with a given string\nendef\n\ndefine Package/look/description\n look utility displays any lines in file which contain string\nendef\n\ndefine Package/losetup\n$(call Package/util-linux/Default)\n  TITLE:=set up and control loop devices\n  DEPENDS:= +libsmartcols\nendef\n\ndefine Package/losetup/description\n losetup is used to associate loop devices with regular files or block devices,\n to detach loop devices and to query the status of a loop device\nendef\n\ndefine Package/lsblk\n$(call Package/util-linux/Default)\n  TITLE:=list block devices\n  DEPENDS:= +libblkid +libmount +libsmartcols\n  SUBMENU=Disc\nendef\n\ndefine Package/lsblk/description\n lsblk lists information about all or the specified block devices\nendef\n\ndefine Package/lscpu\n$(call Package/util-linux/Default)\n  TITLE:=display information about the CPU architecture\n  DEPENDS:= +libsmartcols\nendef\n\ndefine Package/lscpu/description\n lscpu displays information about the CPU architecture\nendef\n\ndefine Package/lslocks\n$(call Package/util-linux/Default)\n  TITLE:=list local system locks\n  DEPENDS:= +libmount +libsmartcols\nendef\n\ndefine Package/lslocks/description\n lslocks lists information about all the currently held file locks in a Linux system\nendef\n\ndefine Package/lsns\n$(call Package/util-linux/Default)\n  TITLE:=list system namespaces\n  DEPENDS:= +libblkid +libmount +libsmartcols\nendef\n\ndefine Package/lsns/description\n lsns lists information about all namespaces and their processes\nendef\n\ndefine Package/more\n$(call Package/util-linux/Default)\n  TITLE:=filter for paging through text one screenful at a time\n  DEPENDS:= +libncurses\nendef\n\ndefine Package/more/description\n more is a filter for paging through text one screenful at a time\nendef\n\ndefine Package/mcookie\n$(call Package/util-linux/Default)\n  TITLE:=generate magic cookies for xauth\nendef\n\ndefine Package/mcookie/description\n mcookie generates a 128-bit random hexadecimal number for use with the X\n authority system\nendef\n\ndefine Package/mount-utils\n$(call Package/util-linux/Default)\n  TITLE:=related (u)mount utilities\n  DEPENDS+= +libmount +libsmartcols\nendef\n\ndefine Package/mount-utils/description\n contains: mount, umount, findmnt\nendef\n\ndefine Package/namei\n$(call Package/util-linux/Default)\n  TITLE:=follow a pathname until a terminal point is found\nendef\n\ndefine Package/namei/description\n namei uses its arguments as pathnames to any type of Unix file (symlinks,\n files, directories, and so forth)\nendef\n\ndefine Package/nsenter\n$(call Package/util-linux/Default)\n  TITLE:=enter a namespace\nendef\n\ndefine Package/nsenter/description\n  run program with namespaces of other processes\nendef\n\ndefine Package/prlimit\n$(call Package/util-linux/Default)\n  TITLE:=get and set process resource limits\n  DEPENDS:= +libsmartcols\nendef\n\ndefine Package/prlimit/description\n  Given a process id and one or more resources, prlimit tries to retrieve\n  and/or modify the limits.\nendef\n\ndefine Package/rename\n$(call Package/util-linux/Default)\n  TITLE:=rename files\nendef\n\ndefine Package/rename/description\n rename will rename the specified files by replacing the first occurrence of\n expression in their name by replacement\nendef\n\ndefine Package/partx-utils\n$(call Package/util-linux/Default)\n  TITLE:=inform kernel about the presence and numbering of on-disk partitions\n  DEPENDS:= +libblkid +libsmartcols\n  SUBMENU=Disc\nendef\n\ndefine Package/partx-utils/description\n contains partx, addpart, delpart\nendef\n\ndefine Package/script-utils\n$(call Package/util-linux/Default)\n  TITLE:=make and replay typescript of terminal session\n  SUBMENU=Terminal\nendef\n\ndefine Package/script-utils/description\n contains: script, scriptreplay\nendef\n\ndefine Package/setterm\n$(call Package/util-linux/Default)\n  TITLE:=set terminal attributes\n  DEPENDS:= +libncurses\n  SUBMENU:=Terminal\nendef\n\ndefine Package/setterm/description\n setterm writes to standard output a character string that will invoke the\n specified terminal capabilities\nendef\n\ndefine Package/sfdisk\n$(call Package/util-linux/Default)\n  TITLE:=partition table manipulator for Linux\n  SUBMENU=Disc\n  DEPENDS:= +libblkid +libfdisk +libsmartcols +libncursesw\nendef\n\ndefine Package/sfdisk/description\n list the size of a partition, list the partitions on a device, check the\n partitions on a device and repartition a device\nendef\n\ndefine Package/swap-utils\n$(call Package/util-linux/Default)\n  TITLE:=swap space management utilities\n  DEPENDS+= +libblkid\n  SUBMENU:=Filesystem\nendef\n\ndefine Package/swap-utils/description\n contains: mkswap, swaplabel\nendef\n\ndefine Package/taskset\n$(call Package/util-linux/Default)\n  TITLE:=set or retrieve a process's CPU affinity\nendef\n\ndefine Package/taskset/description\n contains: taskset\nendef\n\ndefine Package/unshare\n$(call Package/util-linux/Default)\n  TITLE:=unshare userspace tool\nendef\n\ndefine Package/unshare/description\n  run programs with some namespaces unshared from parent\nendef\n\ndefine Package/uuidd\n$(call Package/util-linux/Default)\n  TITLE:=UUID generation daemon\n  DEPENDS:= +libuuid\nendef\n\ndefine Package/uuidd/description\n The uuidd daemon is used by the UUID library to generate universally unique\n identifiers (UUIDs), especially time-based UUIDs, in a secure and\n guaranteed-unique fashion, even in the face of large numbers of threads\n running on different CPUs trying to grab UUIDs.\nendef\n\ndefine Package/uuidgen\n$(call Package/util-linux/Default)\n  TITLE:=create a new UUID value\n  DEPENDS:= +libuuid\nendef\n\ndefine Package/uuidgen/description\n The uuidgen program creates (and prints) a new universally unique identifier\n (UUID) using the libuuid library. The new UUID can reasonably be considered\n unique among all UUIDs created on the local system, and among UUIDs created on\n other systems in the past and in the future.\nendef\n\ndefine Package/wall\n$(call Package/util-linux/Default)\n  TITLE:=send a message to everybody's terminal\n  SUBMENU=Terminal\nendef\n\ndefine Package/wall/description\n wall sends a message to everybody logged in with their mesg permission\n set to yes\nendef\n\ndefine Package/whereis\n$(call Package/util-linux/Default)\n  TITLE:=locate the binary, source, and manual page files for a command\nendef\n\ndefine Package/whereis/description\n whereis locates source/binary and manuals sections for specified files\nendef\n\ndefine Package/wipefs\n$(call Package/util-linux/Default)\n  TITLE:=wipe a signature from a device\n  DEPENDS:= +libblkid +libsmartcols\n  SUBMENU:=Disc\nendef\n\ndefine Package/wipefs/description\n wipefs can erase filesystem, raid or partition table signatures (magic\n strings) from the specified device to make the signature invisible for\n libblkid.\nendef\n\nMESON_ARGS += \\\n\t-Dsystemd=disabled \\\n\t-Dtinfo=disabled \\\n\t-Dcryptsetup=disabled \\\n\t-Dlibutil=disabled \\\n\t-Dlibutempter=disabled \\\n\t-Dlibpcre2-posix=disabled \\\n\t-Dlibuser=disabled \\\n\t-Duse-tty-group=false \\\n\t-Duse-tls=false \\\n\t-Dbuild-python=disabled \\\n\t-Dbuild-zramctl=disabled \\\n\t-Dbuild-fsck=disabled \\\n\t-Dbuild-wipefs=disabled \\\n\t-Dbuild-fallocate=disabled \\\n\t-Dbuild-setpriv=disabled \\\n\t-Dbuild-hardlink=disabled \\\n\t-Dbuild-cramfs=disabled \\\n\t-Dbuild-bfs=disabled \\\n\t-Dbuild-minix=disabled \\\n\t-Dbuild-fdformat=disabled \\\n\t-Dbuild-lslogins=disabled \\\n\t-Dbuild-wdctl=disabled \\\n\t-Dbuild-cal=disabled \\\n\t-Dbuild-switch_root=disabled \\\n\t-Dbuild-pivot_root=disabled \\\n\t-Dbuild-lsmem=disabled \\\n\t-Dbuild-lsirq=disabled \\\n\t-Dbuild-irqtop=disabled \\\n\t-Dbuild-chmem=disabled \\\n\t-Dbuild-ipcrm=disabled \\\n\t-Dbuild-rfkill=disabled \\\n\t-Dbuild-tunelp=disabled \\\n\t-Dbuild-kill=disabled \\\n\t-Dbuild-last=disabled \\\n\t-Dbuild-utmpdump=disabled \\\n\t-Dbuild-line=disabled \\\n\t-Dbuild-mesg=disabled \\\n\t-Dbuild-raw=disabled \\\n\t-Dbuild-vipw=disabled \\\n\t-Dbuild-newgrp=disabled \\\n\t-Dbuild-chfn-chsh=disabled \\\n\t-Dbuild-login=disabled \\\n\t-Dbuild-nologin=disabled \\\n\t-Dbuild-sulogin=disabled \\\n\t-Dbuild-su=disabled \\\n\t-Dbuild-runuser=disabled \\\n\t-Dbuild-ul=disabled \\\n\t-Dbuild-pg=disabled \\\n\t-Dbuild-write=disabled \\\n\t-Dbuild-bash-completion=disabled \\\n\t-Dbuild-pylibmount=disabled \\\n\t-Dreadline=disabled \\\n\t-Dmagic=disabled \\\n\t-Dncursesw=enabled\n\ndefine Build/InstallDev\n\t$(INSTALL_DIR) $(1)/usr/lib/pkgconfig\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/pkgconfig/blkid.pc $(1)/usr/lib/pkgconfig\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/pkgconfig/fdisk.pc $(1)/usr/lib/pkgconfig\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/pkgconfig/mount.pc $(1)/usr/lib/pkgconfig\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/pkgconfig/smartcols.pc $(1)/usr/lib/pkgconfig\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/pkgconfig/uuid.pc $(1)/usr/lib/pkgconfig\n\n\t$(INSTALL_DIR) $(1)/usr/include/blkid\n\t$(CP) $(PKG_INSTALL_DIR)/usr/include/blkid/blkid.h $(1)/usr/include/blkid\n\t$(INSTALL_DIR) $(1)/usr/include/libfdisk\n\t$(CP) $(PKG_INSTALL_DIR)/usr/include/libfdisk/libfdisk.h $(1)/usr/include/libfdisk\n\t$(INSTALL_DIR) $(1)/usr/include/libmount\n\t$(CP) $(PKG_INSTALL_DIR)/usr/include/libmount/libmount.h $(1)/usr/include/libmount\n\t$(INSTALL_DIR) $(1)/usr/include/uuid\n\t$(CP) $(PKG_INSTALL_DIR)/usr/include/uuid/uuid.h $(1)/usr/include/uuid\n\t$(INSTALL_DIR) $(1)/usr/include/libsmartcols\n\t$(CP) $(PKG_INSTALL_DIR)/usr/include/libsmartcols/libsmartcols.h $(1)/usr/include/libsmartcols\n\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/libblkid.so* $(1)/usr/lib\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/libfdisk.so* $(1)/usr/lib\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/libmount.so* $(1)/usr/lib\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/libuuid.so* $(1)/usr/lib\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/libsmartcols.so* $(1)/usr/lib\nendef\n\n\ndefine Package/libfdisk/install\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/libfdisk.so.* $(1)/usr/lib/\nendef\n\ndefine Package/libblkid/install\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/libblkid.so.* $(1)/usr/lib/\nendef\n\ndefine Package/libmount/install\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/libmount.so.* $(1)/usr/lib/\nendef\n\ndefine Package/libsmartcols/install\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/libsmartcols.so.* $(1)/usr/lib/\nendef\n\ndefine Package/libuuid/install\n\t$(INSTALL_DIR) $(1)/usr/lib\n\t$(CP) $(PKG_INSTALL_DIR)/usr/lib/libuuid.so.* $(1)/usr/lib/\nendef\n\ndefine Package/agetty/install\n\t$(INSTALL_DIR) $(1)/usr/sbin\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/sbin/agetty $(1)/usr/sbin/\nendef\n\ndefine Package/blkdiscard/install\n\t$(INSTALL_DIR) $(1)/usr/sbin\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/sbin/blkdiscard $(1)/usr/sbin/\nendef\n\ndefine Package/blkid/install\n\t$(INSTALL_DIR) $(1)/usr/sbin\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/sbin/blkid $(1)/usr/sbin/\nendef\n\ndefine Package/blockdev/install\n\t$(INSTALL_DIR) $(1)/usr/sbin\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/sbin/blockdev $(1)/usr/sbin/\nendef\n\ndefine Package/cal/install\n\t$(INSTALL_DIR) $(1)/usr/bin\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/bin/cal $(1)/usr/bin/\nendef\n\ndefine Package/cfdisk/install\n\t$(INSTALL_DIR) $(1)/usr/sbin\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/sbin/cfdisk $(1)/usr/sbin/\nendef\n\ndefine Package/dmesg/install\n\t$(INSTALL_DIR) $(1)/usr/bin\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/bin/dmesg $(1)/usr/bin/\nendef\n\ndefine Package/eject/install\n\t$(INSTALL_DIR) $(1)/usr/bin\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/bin/eject $(1)/usr/bin/\nendef\n\ndefine Package/fdisk/install\n\t$(INSTALL_DIR) $(1)/usr/sbin\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/sbin/fdisk $(1)/usr/sbin/\nendef\n\ndefine Package/findfs/install\n\t$(INSTALL_DIR) $(1)/usr/sbin\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/sbin/findfs $(1)/usr/sbin/\nendef\n\ndefine Package/flock/install\n\t$(INSTALL_DIR) $(1)/usr/bin\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/bin/flock $(1)/usr/bin/util-linux-flock\nendef\n\ndefine Package/fstrim/install\n\t$(INSTALL_DIR) $(1)/usr/sbin\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/sbin/fstrim $(1)/usr/sbin/\nendef\n\ndefine Package/getopt/install\n\t$(INSTALL_DIR) $(1)/usr/bin\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/bin/getopt $(1)/usr/bin/\nendef\n\ndefine Package/hwclock/install\n\t$(INSTALL_DIR) $(1)/usr/sbin\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/sbin/hwclock $(1)/usr/sbin/\nendef\n\ndefine Package/ipcs/install\n\t$(INSTALL_DIR) $(1)/usr/bin\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/bin/ipcs $(1)/usr/bin/\nendef\n\ndefine Package/logger/install\n\t$(INSTALL_DIR) $(1)/usr/bin\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/bin/logger $(1)/usr/bin/util-linux-logger\nendef\n\ndefine Package/look/install\n\t$(INSTALL_DIR) $(1)/usr/bin\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/bin/look $(1)/usr/bin/\nendef\n\ndefine Package/losetup/install\n\t$(INSTALL_DIR) $(1)/usr/sbin\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/sbin/losetup $(1)/usr/sbin/\nendef\n\ndefine Package/lsblk/install\n\t$(INSTALL_DIR) $(1)/usr/bin\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/bin/lsblk $(1)/usr/bin/\nendef\n\ndefine Package/lscpu/install\n\t$(INSTALL_DIR) $(1)/usr/bin\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/bin/lscpu $(1)/usr/bin/\nendef\n\ndefine Package/lslocks/install\n\t$(INSTALL_DIR) $(1)/usr/bin\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/bin/lslocks $(1)/usr/bin/\nendef\n\ndefine Package/lsns/install\n\t$(INSTALL_DIR) $(1)/usr/bin\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/bin/lsns $(1)/usr/bin/\nendef\n\ndefine Package/more/install\n\t$(INSTALL_DIR) $(1)/usr/bin\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/bin/more $(1)/usr/bin/\nendef\n\ndefine Package/mcookie/install\n\t$(INSTALL_DIR) $(1)/usr/bin\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/bin/mcookie $(1)/usr/bin/\nendef\n\ndefine Package/mount-utils/install\n\t$(INSTALL_DIR) $(1)/usr/bin\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/bin/{u,}mount $(1)/usr/bin/\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/bin/mountpoint $(1)/usr/bin/\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/bin/findmnt $(1)/usr/bin/\nendef\n\ndefine Package/namei/install\n\t$(INSTALL_DIR) $(1)/usr/bin\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/bin/namei $(1)/usr/bin/\nendef\n\ndefine Package/nsenter/install\n\t$(INSTALL_DIR) $(1)/usr/bin\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/bin/nsenter $(1)/usr/bin/\nendef\n\ndefine Package/prlimit/install\n\t$(INSTALL_DIR) $(1)/usr/bin\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/bin/prlimit $(1)/usr/bin/\nendef\n\ndefine Package/rename/install\n\t$(INSTALL_DIR) $(1)/usr/bin\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/bin/rename $(1)/usr/bin/\nendef\n\ndefine Package/partx-utils/install\n\t$(INSTALL_DIR) $(1)/usr/sbin\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/sbin/partx $(1)/usr/sbin/\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/sbin/addpart $(1)/usr/sbin/\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/sbin/delpart $(1)/usr/sbin/\nendef\n\ndefine Package/script-utils/install\n\t$(INSTALL_DIR) $(1)/usr/bin\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/bin/script $(1)/usr/bin/\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/bin/scriptreplay $(1)/usr/bin/\nendef\n\ndefine Package/setterm/install\n\t$(INSTALL_DIR) $(1)/usr/bin\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/bin/setterm $(1)/usr/bin/\nendef\n\ndefine Package/sfdisk/install\n\t$(INSTALL_DIR) $(1)/usr/sbin\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/sbin/sfdisk $(1)/usr/sbin/\nendef\n\ndefine Package/swap-utils/install\n\t$(INSTALL_DIR) $(1)/usr/sbin\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/sbin/mkswap $(1)/usr/sbin/\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/sbin/swaplabel $(1)/usr/sbin/\nendef\n\ndefine Package/taskset/install\n\t$(INSTALL_DIR) $(1)/usr/bin\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/bin/taskset $(1)/usr/bin/\nendef\n\ndefine Package/unshare/install\n\t$(INSTALL_DIR) $(1)/usr/bin\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/bin/unshare $(1)/usr/bin/\nendef\n\ndefine Package/uuidd/install\n\t$(INSTALL_DIR) $(1)/usr/sbin\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/sbin//uuidd $(1)/usr/sbin/\nendef\n\ndefine Package/uuidgen/install\n\t$(INSTALL_DIR) $(1)/usr/bin\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/bin//uuidgen $(1)/usr/bin/\nendef\n\ndefine Package/wall/install\n\t$(INSTALL_DIR) $(1)/usr/bin\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/bin/wall $(1)/usr/bin/\nendef\n\ndefine Package/whereis/install\n\t$(INSTALL_DIR) $(1)/usr/bin\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/bin/whereis $(1)/usr/bin/\nendef\n\ndefine Package/wipefs/install\n\t$(INSTALL_DIR) $(1)/usr/sbin\n\t$(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/sbin/wipefs $(1)/usr/sbin/\nendef\n\n# these lines need to be ordered by dependency because of ABI versioning\n$(eval $(call BuildPackage,libuuid))\n$(eval $(call BuildPackage,libblkid))\n$(eval $(call BuildPackage,libfdisk))\n\n$(eval $(call BuildPackage,libmount))\n$(eval $(call BuildPackage,libsmartcols))\n$(eval $(call BuildPackage,agetty))\n$(eval $(call BuildPackage,blkdiscard))\n$(eval $(call BuildPackage,blkid))\n$(eval $(call BuildPackage,blockdev))\n$(eval $(call BuildPackage,cal))\n$(eval $(call BuildPackage,cfdisk))\n$(eval $(call BuildPackage,dmesg))\n$(eval $(call BuildPackage,eject))\n$(eval $(call BuildPackage,fdisk))\n$(eval $(call BuildPackage,findfs))\n$(eval $(call BuildPackage,flock))\n$(eval $(call BuildPackage,fstrim))\n$(eval $(call BuildPackage,getopt))\n$(eval $(call BuildPackage,hwclock))\n$(eval $(call BuildPackage,ipcs))\n$(eval $(call BuildPackage,logger))\n$(eval $(call BuildPackage,look))\n$(eval $(call BuildPackage,losetup))\n$(eval $(call BuildPackage,lsblk))\n$(eval $(call BuildPackage,lscpu))\n$(eval $(call BuildPackage,lslocks))\n$(eval $(call BuildPackage,lsns))\n$(eval $(call BuildPackage,more))\n$(eval $(call BuildPackage,mcookie))\n$(eval $(call BuildPackage,mount-utils))\n$(eval $(call BuildPackage,namei))\n$(eval $(call BuildPackage,nsenter))\n$(eval $(call BuildPackage,prlimit))\n$(eval $(call BuildPackage,rename))\n$(eval $(call BuildPackage,partx-utils))\n$(eval $(call BuildPackage,script-utils))\n$(eval $(call BuildPackage,setterm))\n$(eval $(call BuildPackage,sfdisk))\n$(eval $(call BuildPackage,swap-utils))\n$(eval $(call BuildPackage,taskset))\n$(eval $(call BuildPackage,unshare))\n$(eval $(call BuildPackage,uuidd))\n$(eval $(call BuildPackage,uuidgen))\n$(eval $(call BuildPackage,wall))\n$(eval $(call BuildPackage,whereis))\n$(eval $(call BuildPackage,wipefs))\n"
  },
  {
    "path": "package/utils/util-linux/patches/010-meson-typo.patch",
    "content": "From c387d4fe7a1435a762a5b7d8b75feb13ad613315 Mon Sep 17 00:00:00 2001\nFrom: Anatoly Pugachev <matorola@gmail.com>\nDate: Fri, 8 Apr 2022 15:34:16 +0300\nSubject: [PATCH] libfdisk: meson.build fix typo\n\n---\n libfdisk/meson.build | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/libfdisk/meson.build\n+++ b/libfdisk/meson.build\n@@ -11,7 +11,7 @@ libfdisk_h = configure_file(\n   output : 'libfdisk.h',\n   configuration : defs,\n   install : build_libfdisk,\n-  install_dir : join_paths(get_option('includedir'), 'libfisk'),\n+  install_dir : join_paths(get_option('includedir'), 'libfdisk'),\n )\n \n lib_fdisk_sources = '''\n"
  },
  {
    "path": "package/utils/util-linux/patches/020-meson-fix-compilation-without-systemd.patch",
    "content": "From 38b15ca2dc4ca32bbe4a2449e1c7b645e4577840 Mon Sep 17 00:00:00 2001\nFrom: Rosen Penev <rosenp@gmail.com>\nDate: Fri, 29 Apr 2022 16:53:43 -0700\nSubject: [PATCH 1/7] meson: fix compilation without systemd\n\nsystemdsystemunitdir is used elsewhere.\n\nSigned-off-by: Rosen Penev <rosenp@gmail.com>\n---\n meson.build | 1 +\n 1 file changed, 1 insertion(+)\n\n--- a/meson.build\n+++ b/meson.build\n@@ -720,6 +720,7 @@ if fs_search_path_extra != ''\n endif\n conf.set_quoted('FS_SEARCH_PATH', fs_search_path)\n \n+systemdsystemunitdir = ''\n if systemd.found()\n   systemdsystemunitdir = systemd.get_pkgconfig_variable('systemdsystemunitdir')\n endif\n"
  },
  {
    "path": "package/utils/util-linux/patches/030-meson-don-t-use-run.patch",
    "content": "From e25db9169450d3d5fb43656a2eae5c08999310f4 Mon Sep 17 00:00:00 2001\nFrom: Rosen Penev <rosenp@gmail.com>\nDate: Fri, 29 Apr 2022 16:56:54 -0700\nSubject: [PATCH 2/7] meson: don't use run\n\nFixes cross compilation. run is not needed anyway.\n\nSigned-off-by: Rosen Penev <rosenp@gmail.com>\n---\n meson.build | 6 ++----\n 1 file changed, 2 insertions(+), 4 deletions(-)\n\n--- a/meson.build\n+++ b/meson.build\n@@ -577,8 +577,7 @@ int main(void) {\n   return tzname ? 0 : 1;\n }\n '''.format(have ? 1 : 0)\n-result = cc.run(code, name : 'using tzname[]')\n-have = result.compiled() and result.returncode() == 0\n+have = cc.compiles(code, name : 'using tzname[]')\n conf.set('HAVE_TZNAME', have ? 1 : false)\n \n socket_libs = []\n@@ -641,8 +640,7 @@ int main(void) {\n     return (*__progname != 0);\n }\n '''\n-result = cc.run(code, name : 'using __progname')\n-have = result.compiled() and result.returncode() == 0\n+have = cc.compiles(code, name : 'using __progname')\n conf.set('HAVE___PROGNAME', have ? 1 : false)\n \n build_plymouth_support = get_option('build-plymouth-support')\n"
  },
  {
    "path": "package/utils/util-linux/patches/040-meson-fix-cpu_set_t-test.patch",
    "content": "From 4194bb5b35e9b5f3296bf17b7cabcc5cb1632ba3 Mon Sep 17 00:00:00 2001\nFrom: Rosen Penev <rosenp@gmail.com>\nDate: Fri, 29 Apr 2022 16:55:15 -0700\nSubject: [PATCH 3/7] meson: fix cpu_set_t test\n\n_GNU_SOURCE is needed here.\n\nSigned-off-by: Rosen Penev <rosenp@gmail.com>\n---\n meson.build | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/meson.build\n+++ b/meson.build\n@@ -379,7 +379,7 @@ endforeach\n have = cc.has_header('sched.h')\n conf.set10('HAVE_DECL_CPU_ALLOC', have)\n # We get -1 if the size cannot be determined\n-have_cpu_set_t = cc.sizeof('cpu_set_t', prefix : '#include <sched.h>') > 0\n+have_cpu_set_t = cc.sizeof('cpu_set_t', prefix : '#define _GNU_SOURCE\\n#include <sched.h>') > 0\n conf.set('HAVE_CPU_SET_T', have_cpu_set_t ? 1 : false)\n \n have = cc.has_header_symbol('stdlib.h', 'environ')\n"
  },
  {
    "path": "package/utils/util-linux/patches/050-meson-fix-environ-search.patch",
    "content": "From 1e9e2b9fe365cc4a0025d44dc0a9c54bfffe9058 Mon Sep 17 00:00:00 2001\nFrom: Rosen Penev <rosenp@gmail.com>\nDate: Fri, 29 Apr 2022 18:16:17 -0700\nSubject: [PATCH 4/7] meson: fix environ search\n\nmusl has it defined in unistd.h and hidden behind _GNU_SOURCE.\n\nSigned-off-by: Rosen Penev <rosenp@gmail.com>\n---\n meson.build | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/meson.build\n+++ b/meson.build\n@@ -382,7 +382,7 @@ conf.set10('HAVE_DECL_CPU_ALLOC', have)\n have_cpu_set_t = cc.sizeof('cpu_set_t', prefix : '#define _GNU_SOURCE\\n#include <sched.h>') > 0\n conf.set('HAVE_CPU_SET_T', have_cpu_set_t ? 1 : false)\n \n-have = cc.has_header_symbol('stdlib.h', 'environ')\n+have = cc.has_header_symbol('unistd.h', 'environ', prefix : '#define _GNU_SOURCE')\n conf.set10('HAVE_ENVIRON_DECL', have)\n \n have = cc.has_header_symbol('signal.h', 'sighandler_t')\n"
  },
  {
    "path": "package/utils/util-linux/patches/060-meson-add-_GNU_SOURCE-for-sighandler_t.patch",
    "content": "From 5d7557eb3827664b2b78145373907f2a6994bdf9 Mon Sep 17 00:00:00 2001\nFrom: Rosen Penev <rosenp@gmail.com>\nDate: Fri, 29 Apr 2022 18:17:52 -0700\nSubject: [PATCH 5/7] meson: add _GNU_SOURCE for sighandler_t\n\nmusl requires it.\n\nSigned-off-by: Rosen Penev <rosenp@gmail.com>\n---\n meson.build | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/meson.build\n+++ b/meson.build\n@@ -385,7 +385,7 @@ conf.set('HAVE_CPU_SET_T', have_cpu_set_\n have = cc.has_header_symbol('unistd.h', 'environ', prefix : '#define _GNU_SOURCE')\n conf.set10('HAVE_ENVIRON_DECL', have)\n \n-have = cc.has_header_symbol('signal.h', 'sighandler_t')\n+have = cc.has_header_symbol('signal.h', 'sighandler_t', prefix : '#define _GNU_SOURCE')\n conf.set('HAVE_SIGHANDLER_T', have ? 1 : false)\n \n have = cc.has_header_symbol('string.h', 'strsignal')\n"
  },
  {
    "path": "package/utils/util-linux/patches/070-meson-fix-isnan-check.patch",
    "content": "From 777652585924034deeba98ae3192f26bc32bb661 Mon Sep 17 00:00:00 2001\nFrom: Rosen Penev <rosenp@gmail.com>\nDate: Fri, 29 Apr 2022 18:19:53 -0700\nSubject: [PATCH 6/7] meson: fix isnan check\n\nmusl only has isnan as a macro, not as a function. Handle the former\ncase.\n\nSigned-off-by: Rosen Penev <rosenp@gmail.com>\n---\n meson.build | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/meson.build\n+++ b/meson.build\n@@ -622,7 +622,7 @@ rtas_libs = cc.find_library('rtas', requ\n conf.set('HAVE_LIBRTAS', rtas_libs.found() ? 1 : false)\n \n math_libs = []\n-if not cc.has_function('isnan')\n+if not cc.has_header_symbol('math.h', 'isnan')\n   lib = cc.find_library('m', required : true)\n   if (cc.has_function('isnan', dependencies : lib) and\n       cc.has_function('__isnan', dependencies : lib))\n"
  },
  {
    "path": "package/utils/util-linux/patches/080-meson-fix-tzname-check.patch",
    "content": "From 9a6b2618b46a859388139d1eb18f876886786659 Mon Sep 17 00:00:00 2001\nFrom: Rosen Penev <rosenp@gmail.com>\nDate: Fri, 29 Apr 2022 19:00:53 -0700\nSubject: [PATCH] meson: fix tzname check\n\ntzname is not a type but a variable. sizeof only works on types.\n\nSigned-off-by: Rosen Penev <rosenp@gmail.com>\n---\n meson.build | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/meson.build\n+++ b/meson.build\n@@ -565,7 +565,7 @@ have = cc.has_member('struct tm', 'tm_zo\n                      prefix : '#include <time.h>')\n conf.set('HAVE_STRUCT_TM_TM_ZONE', have ? 1 : false)\n \n-have = cc.sizeof('tzname', prefix : '#include <time.h>') > 0\n+have = cc.has_header_symbol('time.h', 'tzname')\n conf.set('HAVE_DECL_TZNAME', have ? 1 : false)\n \n code = '''\n"
  },
  {
    "path": "package/utils/util-linux/patches/090-meson-libpam.patch",
    "content": "--- a/meson.build\n+++ b/meson.build\n@@ -299,10 +299,14 @@ conf.set('HAVE_LIBUDEV', lib_udev.found(\n \n lib_crypt = cc.find_library('crypt')\n \n-lib_pam = cc.find_library('pam')\n+req_libpam = not (get_option('build-login').disabled() or get_option('build-chfn-chsh').disabled()\n+  or get_option('build-su').disabled() or get_option('build-runuser').disabled())\n+lib_pam = cc.find_library('pam', required : req_libpam)\n if lib_pam.found()\n   lib_pam_misc = cc.find_library('pam_misc')\n   lib_pam = [lib_pam, lib_pam_misc]\n+else\n+  lib_pam_misc = declare_dependency()\n endif\n \n lib_cryptsetup = dependency(\n"
  },
  {
    "path": "package/utils/util-linux/patches/100-meson-make-libcap-ng-dependent-on-setpriv.patch",
    "content": "From cd23a4336f49ba6a12ade557a09589f2a7c966f4 Mon Sep 17 00:00:00 2001\nFrom: Rosen Penev <rosenp@gmail.com>\nDate: Mon, 2 May 2022 16:18:33 -0700\nSubject: [PATCH] meson: make libcap-ng dependent on setpriv\n\nSigned-off-by: Rosen Penev <rosenp@gmail.com>\n---\n meson.build | 5 +++--\n 1 file changed, 3 insertions(+), 2 deletions(-)\n\n--- a/meson.build\n+++ b/meson.build\n@@ -334,7 +334,8 @@ have = cc.has_function(\n conf.set('HAVE_CRYPT_ACTIVATE_BY_SIGNED_KEY', have ? 1 : false)\n \n lib_cap_ng = dependency(\n-  'libcap-ng')\n+  'libcap-ng',\n+  required : get_option('build-setpriv'))\n \n lib_selinux = dependency(\n   'libselinux',\n@@ -1754,7 +1755,7 @@ if opt and not is_disabler(exe)\n   exes += exe\n endif\n \n-opt = not get_option('build-setpriv').disabled()\n+opt = not get_option('build-setpriv').disabled() and lib_cap_ng.found()\n exe = executable(\n   'setpriv',\n   setpriv_sources,\n"
  },
  {
    "path": "package/utils/util-linux/patches/110-meson-fix-when-HAVE_CLOCK_GETTIME-is-set.patch",
    "content": "From e51565b653cf09985df57cb7254b16d5af5df223 Mon Sep 17 00:00:00 2001\nFrom: Nicolas Caramelli <caramelli.devel@gmail.com>\nDate: Fri, 29 Apr 2022 18:16:36 +0200\nSubject: [PATCH] meson: fix when HAVE_CLOCK_GETTIME is set\n\nSigned-off-by: Nicolas Caramelli <caramelli.devel@gmail.com>\n---\n meson.build | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/meson.build\n+++ b/meson.build\n@@ -602,7 +602,7 @@ if not have\n   have = cc.has_function('clock_gettime',\n                          dependencies : realtime_libs)\n endif\n-conf.set('HAVE_CLOCK_GETTIME', have_dirfd ? 1 : false)\n+conf.set('HAVE_CLOCK_GETTIME', have ? 1 : false)\n \n thread_libs = dependency('threads')\n \n"
  },
  {
    "path": "package/utils/util-linux/patches/120-meson-get-the-project-version-from-the-version-gen-s.patch",
    "content": "From e0c1a86bf88b568a7afe8ebaea1b9f84afb892c2 Mon Sep 17 00:00:00 2001\nFrom: Eli Schwartz <eschwartz@archlinux.org>\nDate: Wed, 4 May 2022 23:52:31 -0400\nSubject: [PATCH] meson: get the project version from the version-gen script\n\nThis matches autotools and ensures that the version number is actually\nreliable.\n---\n meson.build | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/meson.build\n+++ b/meson.build\n@@ -1,5 +1,5 @@\n project('util-linux', 'c',\n-        version : '2.37',\n+        version : run_command('tools/git-version-gen', check: true).stdout(),\n         license : 'GPLv2+')\n \n pkgconfig = import('pkgconfig')\n"
  },
  {
    "path": "package/utils/util-linux/patches/130-meson-fix-error-in-processing-version-for-pc-files.patch",
    "content": "From dc307e1cbf73f6dbf72bb049c19d332774cdb4e7 Mon Sep 17 00:00:00 2001\nFrom: Eli Schwartz <eschwartz@archlinux.org>\nDate: Thu, 5 May 2022 00:16:15 -0400\nSubject: [PATCH] meson: fix error in processing version for pc files\n\nThis awk command was copied verbatim from configure.ac, which included\nnon-awk syntax because configure.ac cannot contain [ literals.\n\nRewrite these autoconf quadrigraphs as their actual values, for meson.\n\nFixes always setting the micro version to \"0\".\n---\n meson.build | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/meson.build\n+++ b/meson.build\n@@ -41,7 +41,7 @@ conf.set_quoted('PACKAGE_VERSION', meson\n \n codes = [''' {print $1}  ''',\n          ''' {sub(\"-.*\",\"\",$2); print $2} ''',\n-         ''' {sub(\"-.*\",\"\",$3); print $3 ~ /^@<:@0-9@:>@+$/ ? $3 : 0} ''']\n+         ''' {sub(\"-.*\",\"\",$3); print $3 ~ /^[0-9]+$/ ? $3 : 0} ''']\n pc_version = []\n foreach code : codes\n   res = run_command('bash', '-c',\n"
  },
  {
    "path": "package/utils/util-linux/patches/200-meson-no-po.patch",
    "content": "--- a/meson.build\n+++ b/meson.build\n@@ -774,7 +774,6 @@ subdir('disk-utils')\n subdir('misc-utils')\n subdir('text-utils')\n subdir('term-utils')\n-subdir('po')\n \n includes = [dir_include,\n             dir_libblkid,\n"
  },
  {
    "path": "package/utils/util-linux/patches/210-use-urandom.patch",
    "content": "--- a/lib/randutils.c\n+++ b/lib/randutils.c\n@@ -26,6 +26,11 @@\n #define THREAD_LOCAL static\n #endif\n \n+/* force /dev/urandom to avoid hanging on early boot */\n+#undef HAVE_GETRANDOM\n+#undef SYS_getrandom\n+#undef __NR_getrandom\n+\n #ifdef HAVE_GETRANDOM\n # include <sys/random.h>\n #elif defined (__linux__)\n"
  },
  {
    "path": "rules.mk",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2006-2010 OpenWrt.org\n# Copyright (C) 2016 LEDE Project\n\nifneq ($(__rules_inc),1)\n__rules_inc=1\n\nifeq ($(DUMP),)\n  -include $(TOPDIR)/.config\nendif\ninclude $(TOPDIR)/include/debug.mk\ninclude $(TOPDIR)/include/verbose.mk\n\nifneq ($(filter check,$(MAKECMDGOALS)),)\nCHECK:=1\nDUMP:=1\nendif\n\nexport TMP_DIR:=$(TOPDIR)/tmp\nexport TMPDIR:=$(TMP_DIR)\n\nqstrip=$(strip $(subst \",,$(1)))\n#\"))\n\nempty:=\nspace:= $(empty) $(empty)\ncomma:=,\nmerge=$(subst $(space),,$(1))\nconfvar=$(shell echo '$(foreach v,$(1),$(v)=$(subst ','\\'',$($(v))))' | $(MKHASH) md5)\nstrip_last=$(patsubst %.$(lastword $(subst .,$(space),$(1))),%,$(1))\n\nparen_left = (\nparen_right = )\nchars_lower = a b c d e f g h i j k l m n o p q r s t u v w x y z\nchars_upper = A B C D E F G H I J K L M N O P Q R S T U V W X Y Z\n\ndefine sep\n\nendef\n\ndefine newline\n\n\nendef\n\n__tr_list = $(join $(join $(1),$(foreach char,$(1),$(comma))),$(2))\n__tr_head_stripped = $(subst $(space),,$(foreach cv,$(call __tr_list,$(1),$(2)),$$$(paren_left)subst$(cv)$(comma)))\n__tr_head = $(subst $(paren_left)subst,$(paren_left)subst$(space),$(__tr_head_stripped))\n__tr_tail = $(subst $(space),,$(foreach cv,$(1),$(paren_right)))\n__tr_template = $(__tr_head)$$(1)$(__tr_tail)\n\n$(eval toupper = $(call __tr_template,$(chars_lower),$(chars_upper)))\n$(eval tolower = $(call __tr_template,$(chars_upper),$(chars_lower)))\n\nversion_abbrev = $(if $(if $(CHECK),,$(DUMP)),$(1),$(shell printf '%.8s' $(1)))\n\n_SINGLE=export MAKEFLAGS=$(space);\nCFLAGS:=\nARCH:=$(subst i486,i386,$(subst i586,i386,$(subst i686,i386,$(call qstrip,$(CONFIG_ARCH)))))\nARCH_PACKAGES:=$(call qstrip,$(CONFIG_TARGET_ARCH_PACKAGES))\nBOARD:=$(call qstrip,$(CONFIG_TARGET_BOARD))\nSUBTARGET:=$(call qstrip,$(CONFIG_TARGET_SUBTARGET))\nTARGET_OPTIMIZATION:=$(call qstrip,$(CONFIG_TARGET_OPTIMIZATION))\nexport EXTRA_OPTIMIZATION:=$(filter-out -fno-plt,$(call qstrip,$(CONFIG_EXTRA_OPTIMIZATION)))\nTARGET_SUFFIX=$(call qstrip,$(CONFIG_TARGET_SUFFIX))\nBUILD_SUFFIX:=$(call qstrip,$(CONFIG_BUILD_SUFFIX))\nSUBDIR:=$(patsubst $(TOPDIR)/%,%,${CURDIR})\nBUILD_SUBDIR:=$(patsubst $(TOPDIR)/%,%,${CURDIR})\nNPROC:=$(shell sysctl -n hw.ncpu 2>/dev/null || nproc)\nexport SHELL:=/usr/bin/env bash\n\nIS_PACKAGE_BUILD := $(if $(filter package/%,$(BUILD_SUBDIR)),1)\n\nOPTIMIZE_FOR_CPU=$(subst i386,i486,$(ARCH))\n\nifneq (,$(findstring $(ARCH) , aarch64 aarch64_be powerpc ))\n  FPIC:=-DPIC -fPIC\nelse\n  FPIC:=-DPIC -fpic\nendif\n\nHOST_FPIC:=-DPIC -fPIC\n\nARCH_SUFFIX:=$(call qstrip,$(CONFIG_CPU_TYPE))\nGCC_ARCH:=\n\nifneq ($(ARCH_SUFFIX),)\n  ARCH_SUFFIX:=_$(ARCH_SUFFIX)\nendif\nifneq ($(filter -march=armv%,$(TARGET_OPTIMIZATION)),)\n  GCC_ARCH:=$(patsubst -march=%,%,$(filter -march=armv%,$(TARGET_OPTIMIZATION)))\nendif\nifdef CONFIG_HAS_SPE_FPU\n  TARGET_SUFFIX:=$(TARGET_SUFFIX)spe\nendif\nifdef CONFIG_MIPS64_ABI\n  ifneq ($(CONFIG_MIPS64_ABI_O32),y)\n     ARCH_SUFFIX:=$(ARCH_SUFFIX)_$(call qstrip,$(CONFIG_MIPS64_ABI))\n  endif\nendif\n\nDEFAULT_SUBDIR_TARGETS:=clean download prepare compile update refresh prereq dist distcheck configure check check-depends\n\ndefine DefaultTargets\n$(foreach t,$(DEFAULT_SUBDIR_TARGETS) $(1),\n  .$(t):\n  $(t): .$(t)\n  .PHONY: $(t) .$(t)\n)\nendef\n\nDL_DIR:=$(if $(call qstrip,$(CONFIG_DOWNLOAD_FOLDER)),$(call qstrip,$(CONFIG_DOWNLOAD_FOLDER)),$(TOPDIR)/dl)\nOUTPUT_DIR:=$(if $(call qstrip,$(CONFIG_BINARY_FOLDER)),$(call qstrip,$(CONFIG_BINARY_FOLDER)),$(TOPDIR)/bin)\nBIN_DIR:=$(OUTPUT_DIR)/targets/$(BOARD)/$(SUBTARGET)\nINCLUDE_DIR:=$(TOPDIR)/include\nSCRIPT_DIR:=$(TOPDIR)/scripts\nBUILD_DIR_BASE:=$(TOPDIR)/build_dir\nifeq ($(CONFIG_EXTERNAL_TOOLCHAIN),)\n  GCCV:=$(call qstrip,$(CONFIG_GCC_VERSION))\n  LIBC:=$(call qstrip,$(CONFIG_LIBC))\n  REAL_GNU_TARGET_NAME=$(OPTIMIZE_FOR_CPU)-openwrt-linux$(if $(TARGET_SUFFIX),-$(TARGET_SUFFIX))\n  GNU_TARGET_NAME=$(OPTIMIZE_FOR_CPU)-openwrt-linux\n  DIR_SUFFIX:=_$(LIBC)$(if $(CONFIG_arm),_eabi)\n  BIN_DIR:=$(BIN_DIR)$(if $(CONFIG_USE_MUSL),,-$(LIBC))\n  TARGET_DIR_NAME = target-$(ARCH)$(ARCH_SUFFIX)$(DIR_SUFFIX)$(if $(BUILD_SUFFIX),_$(BUILD_SUFFIX))\n  TOOLCHAIN_DIR_NAME = toolchain-$(ARCH)$(ARCH_SUFFIX)_gcc-$(GCCV)$(DIR_SUFFIX)\nelse\n  ifeq ($(CONFIG_NATIVE_TOOLCHAIN),)\n    GNU_TARGET_NAME=$(call qstrip,$(CONFIG_TARGET_NAME))\n  else\n    GNU_TARGET_NAME=$(shell gcc -dumpmachine)\n  endif\n  REAL_GNU_TARGET_NAME=$(GNU_TARGET_NAME)\n  LIBC:=$(call qstrip,$(CONFIG_LIBC))\n  TARGET_DIR_NAME:=target-$(GNU_TARGET_NAME)_$(LIBC)$(if $(BUILD_SUFFIX),_$(BUILD_SUFFIX))\n  TOOLCHAIN_DIR_NAME:=toolchain-$(GNU_TARGET_NAME)\nendif\n\nifeq ($(or $(CONFIG_EXTERNAL_TOOLCHAIN),$(CONFIG_TARGET_uml)),)\n  iremap = -f$(if $(CONFIG_REPRODUCIBLE_DEBUG_INFO),file,macro)-prefix-map=$(1)=$(2)\nendif\n\nPACKAGE_DIR:=$(BIN_DIR)/packages\nPACKAGE_DIR_ALL:=$(TOPDIR)/staging_dir/packages/$(BOARD)\nBUILD_DIR:=$(BUILD_DIR_BASE)/$(TARGET_DIR_NAME)\nSTAGING_DIR:=$(TOPDIR)/staging_dir/$(TARGET_DIR_NAME)\nBUILD_DIR_TOOLCHAIN:=$(BUILD_DIR_BASE)/$(TOOLCHAIN_DIR_NAME)\nTOOLCHAIN_DIR:=$(TOPDIR)/staging_dir/$(TOOLCHAIN_DIR_NAME)\nSTAMP_DIR:=$(BUILD_DIR)/stamp\nSTAMP_DIR_HOST=$(BUILD_DIR_HOST)/stamp\nTARGET_ROOTFS_DIR?=$(if $(call qstrip,$(CONFIG_TARGET_ROOTFS_DIR)),$(call qstrip,$(CONFIG_TARGET_ROOTFS_DIR)),$(BUILD_DIR))\nTARGET_DIR:=$(TARGET_ROOTFS_DIR)/root-$(BOARD)\nSTAGING_DIR_ROOT:=$(STAGING_DIR)/root-$(BOARD)\nSTAGING_DIR_IMAGE:=$(STAGING_DIR)/image\nBUILD_LOG_DIR:=$(if $(call qstrip,$(CONFIG_BUILD_LOG_DIR)),$(call qstrip,$(CONFIG_BUILD_LOG_DIR)),$(TOPDIR)/logs)\nPKG_INFO_DIR := $(STAGING_DIR)/pkginfo\n\nBUILD_DIR_HOST:=$(if $(IS_PACKAGE_BUILD),$(BUILD_DIR_BASE)/hostpkg,$(BUILD_DIR_BASE)/host)\nSTAGING_DIR_HOST:=$(TOPDIR)/staging_dir/host\nSTAGING_DIR_HOSTPKG:=$(TOPDIR)/staging_dir/hostpkg\n\nTARGET_PATH:=$(subst $(space),:,$(filter-out .,$(filter-out ./,$(subst :,$(space),$(PATH)))))\nTARGET_INIT_PATH:=$(call qstrip,$(CONFIG_TARGET_INIT_PATH))\nTARGET_INIT_PATH:=$(if $(TARGET_INIT_PATH),$(TARGET_INIT_PATH),/usr/sbin:/sbin:/usr/bin:/bin)\nTARGET_CFLAGS:=$(TARGET_OPTIMIZATION)$(if $(CONFIG_DEBUG), -g3) $(call qstrip,$(CONFIG_EXTRA_OPTIMIZATION))\nTARGET_CXXFLAGS = $(TARGET_CFLAGS)\nTARGET_ASFLAGS_DEFAULT = $(TARGET_CFLAGS)\nTARGET_ASFLAGS = $(TARGET_ASFLAGS_DEFAULT)\nifneq ($(CONFIG_EXTERNAL_TOOLCHAIN),)\nLIBGCC_S_PATH=$(realpath $(wildcard $(call qstrip,$(CONFIG_LIBGCC_ROOT_DIR))/$(call qstrip,$(CONFIG_LIBGCC_FILE_SPEC))))\nLIBGCC_S=$(if $(LIBGCC_S_PATH),-L$(dir $(LIBGCC_S_PATH)) -lgcc_s)\nLIBGCC_A=$(realpath $(lastword $(wildcard $(dir $(LIBGCC_S_PATH))/gcc/*/*/libgcc.a)))\nelse\nLIBGCC_A=$(lastword $(wildcard $(TOOLCHAIN_DIR)/lib/gcc/*/*/libgcc.a))\nLIBGCC_S=$(if $(wildcard $(TOOLCHAIN_DIR)/lib/libgcc_s.so),-L$(TOOLCHAIN_DIR)/lib -lgcc_s,$(LIBGCC_A))\nendif\n\nifeq ($(CONFIG_ARCH_64BIT),y)\n  LIB_SUFFIX:=64\nendif\n\nifndef DUMP\n  ifeq ($(CONFIG_EXTERNAL_TOOLCHAIN),)\n    -include $(TOOLCHAIN_DIR)/info.mk\n    export GCC_HONOUR_COPTS:=0\n    TARGET_CROSS:=$(if $(TARGET_CROSS),$(TARGET_CROSS),$(OPTIMIZE_FOR_CPU)-openwrt-linux$(if $(TARGET_SUFFIX),-$(TARGET_SUFFIX))-)\n    TARGET_CFLAGS+= -fhonour-copts -Wno-error=unused-but-set-variable -Wno-error=unused-result\n    TARGET_CPPFLAGS+= -I$(TOOLCHAIN_DIR)/usr/include\n    ifeq ($(CONFIG_USE_MUSL),y)\n      TARGET_CPPFLAGS+= -I$(TOOLCHAIN_DIR)/include/fortify\n    endif\n    TARGET_CPPFLAGS+= -I$(TOOLCHAIN_DIR)/include\n    TARGET_LDFLAGS+= -L$(TOOLCHAIN_DIR)/usr/lib -L$(TOOLCHAIN_DIR)/lib\n    TARGET_PATH:=$(TOOLCHAIN_DIR)/bin:$(TARGET_PATH)\n  else\n    ifeq ($(CONFIG_NATIVE_TOOLCHAIN),)\n      TARGET_CROSS:=$(call qstrip,$(CONFIG_TOOLCHAIN_PREFIX))\n      TOOLCHAIN_ROOT_DIR:=$(call qstrip,$(CONFIG_TOOLCHAIN_ROOT))\n      TOOLCHAIN_BIN_DIRS:=$(patsubst ./%,$(TOOLCHAIN_ROOT_DIR)/%,$(call qstrip,$(CONFIG_TOOLCHAIN_BIN_PATH)))\n      TOOLCHAIN_INC_DIRS:=$(patsubst ./%,$(TOOLCHAIN_ROOT_DIR)/%,$(call qstrip,$(CONFIG_TOOLCHAIN_INC_PATH)))\n      TOOLCHAIN_LIB_DIRS:=$(patsubst ./%,$(TOOLCHAIN_ROOT_DIR)/%,$(call qstrip,$(CONFIG_TOOLCHAIN_LIB_PATH)))\n      ifneq ($(TOOLCHAIN_BIN_DIRS),)\n        TARGET_PATH:=$(subst $(space),:,$(TOOLCHAIN_BIN_DIRS)):$(TARGET_PATH)\n      endif\n      ifneq ($(TOOLCHAIN_INC_DIRS),)\n        TARGET_CPPFLAGS+= $(patsubst %,-I%,$(TOOLCHAIN_INC_DIRS))\n      endif\n      ifneq ($(TOOLCHAIN_LIB_DIRS),)\n        TARGET_LDFLAGS+= $(patsubst %,-L%,$(TOOLCHAIN_LIB_DIRS))\n      endif\n      TARGET_PATH:=$(TOOLCHAIN_DIR)/bin:$(TARGET_PATH)\n    endif\n  endif\nendif\nTARGET_PATH_PKG:=$(STAGING_DIR)/host/bin:$(STAGING_DIR_HOSTPKG)/bin:$(TARGET_PATH)\n\nifeq ($(CONFIG_SOFT_FLOAT),y)\n  SOFT_FLOAT_CONFIG_OPTION:=--with-float=soft\n  ifeq ($(CONFIG_arm),y)\n    TARGET_CFLAGS+= -mfloat-abi=soft\n  else\n    TARGET_CFLAGS+= -msoft-float\n  endif\nelse\n  SOFT_FLOAT_CONFIG_OPTION:=\n  ifeq ($(CONFIG_arm),y)\n    TARGET_CFLAGS+= -mfloat-abi=hard\n  endif\nendif\n\nexport PATH:=$(TARGET_PATH)\nexport STAGING_DIR STAGING_DIR_HOST STAGING_DIR_HOSTPKG\nexport SH_FUNC:=. $(INCLUDE_DIR)/shell.sh;\n\nPKG_CONFIG:=$(STAGING_DIR_HOST)/bin/pkg-config\n\nexport PKG_CONFIG\n\nHOSTCC:=gcc\nHOSTCXX:=g++\nHOST_CPPFLAGS:=-I$(STAGING_DIR_HOST)/include $(if $(IS_PACKAGE_BUILD),-I$(STAGING_DIR_HOSTPKG)/include -I$(STAGING_DIR)/host/include)\nHOST_CXXFLAGS:=\nHOST_CFLAGS:=-O2 $(HOST_CPPFLAGS)\nHOST_LDFLAGS:=-L$(STAGING_DIR_HOST)/lib $(if $(IS_PACKAGE_BUILD),-L$(STAGING_DIR_HOSTPKG)/lib -L$(STAGING_DIR)/host/lib)\n\nifeq ($(CONFIG_EXTERNAL_TOOLCHAIN),)\n  TARGET_AR:=$(TARGET_CROSS)gcc-ar\n  TARGET_RANLIB:=$(TARGET_CROSS)gcc-ranlib\n  TARGET_NM:=$(TARGET_CROSS)gcc-nm\nelse\n  TARGET_AR:=$(TARGET_CROSS)ar\n  TARGET_RANLIB:=$(TARGET_CROSS)ranlib\n  TARGET_NM:=$(TARGET_CROSS)nm\nendif\n\nBUILD_KEY=$(TOPDIR)/key-build\n\nFAKEROOT:=$(STAGING_DIR_HOST)/bin/fakeroot\n\nTARGET_CC:=$(TARGET_CROSS)gcc\nTARGET_CXX:=$(TARGET_CROSS)g++\nKPATCH:=$(SCRIPT_DIR)/patch-kernel.sh\nSED:=$(STAGING_DIR_HOST)/bin/sed -i -e\nESED:=$(STAGING_DIR_HOST)/bin/sed -E -i -e\nMKHASH:=$(STAGING_DIR_HOST)/bin/mkhash\n# MKHASH is used in /scripts, so we export it here.\nexport MKHASH\nCP:=cp -fpR\nLN:=ln -sf\nXARGS:=xargs -r\n\nBASH:=bash\nTAR:=tar\nFIND:=find\nPATCH:=patch\nPYTHON:=python3\n\nINSTALL_BIN:=install -m0755\nINSTALL_SUID:=install -m4755\nINSTALL_DIR:=install -d -m0755\nINSTALL_DATA:=install -m0644\nINSTALL_CONF:=install -m0600\n\nTARGET_CC_NOCACHE:=$(TARGET_CC)\nTARGET_CXX_NOCACHE:=$(TARGET_CXX)\nHOSTCC_NOCACHE:=$(HOSTCC)\nHOSTCXX_NOCACHE:=$(HOSTCXX)\nexport TARGET_CC_NOCACHE\nexport TARGET_CXX_NOCACHE\nexport HOSTCC_NOCACHE\nexport HOSTCXX_NOCACHE\n\nifneq ($(CONFIG_CCACHE),)\n  TARGET_CC:= ccache_cc\n  TARGET_CXX:= ccache_cxx\n  HOSTCC:= ccache $(HOSTCC)\n  HOSTCXX:= ccache $(HOSTCXX)\n  export CCACHE_BASEDIR:=$(TOPDIR)\n  export CCACHE_DIR:=$(if $(call qstrip,$(CONFIG_CCACHE_DIR)),$(call qstrip,$(CONFIG_CCACHE_DIR)),$(TOPDIR)/.ccache)\n  export CCACHE_COMPILERCHECK:=%compiler% -dumpmachine; %compiler% -dumpversion\nendif\n\nTARGET_CONFIGURE_OPTS = \\\n  AR=\"$(TARGET_AR)\" \\\n  AS=\"$(TARGET_CC) -c $(TARGET_ASFLAGS)\" \\\n  LD=$(TARGET_CROSS)ld \\\n  NM=\"$(TARGET_NM)\" \\\n  CC=\"$(TARGET_CC)\" \\\n  GCC=\"$(TARGET_CC)\" \\\n  CXX=\"$(TARGET_CXX)\" \\\n  RANLIB=\"$(TARGET_RANLIB)\" \\\n  STRIP=$(TARGET_CROSS)strip \\\n  OBJCOPY=$(TARGET_CROSS)objcopy \\\n  OBJDUMP=$(TARGET_CROSS)objdump \\\n  SIZE=$(TARGET_CROSS)size\n\n# strip an entire directory\nifneq ($(CONFIG_NO_STRIP),)\n  RSTRIP:=:\n  STRIP:=:\nelse\n  ifneq ($(CONFIG_USE_STRIP),)\n    STRIP:=$(TARGET_CROSS)strip $(call qstrip,$(CONFIG_STRIP_ARGS))\n  else\n    ifneq ($(CONFIG_USE_SSTRIP),)\n      STRIP:=$(STAGING_DIR_HOST)/bin/sstrip $(call qstrip,$(CONFIG_SSTRIP_ARGS))\n    endif\n  endif\n  RSTRIP= \\\n    export CROSS=\"$(TARGET_CROSS)\" \\\n\t\t$(if $(PKG_BUILD_ID),KEEP_BUILD_ID=1) \\\n\t\t$(if $(CONFIG_KERNEL_KALLSYMS),NO_RENAME=1) \\\n\t\t$(if $(CONFIG_KERNEL_PROFILING),KEEP_SYMBOLS=1); \\\n    NM=\"$(TARGET_CROSS)nm\" \\\n    STRIP=\"$(STRIP)\" \\\n    STRIP_KMOD=\"$(SCRIPT_DIR)/strip-kmod.sh\" \\\n    PATCHELF=\"$(STAGING_DIR_HOST)/bin/patchelf\" \\\n    $(SCRIPT_DIR)/rstrip.sh\nendif\n\nNINJA = \\\n\tMAKEFLAGS=\"$(MAKE_JOBSERVER)\" \\\n\t$(STAGING_DIR_HOST)/bin/ninja \\\n\t\t$(if $(findstring c,$(OPENWRT_VERBOSE)),-v) \\\n\t\t$(if $(MAKE_JOBSERVER),,-j1)\n\nifeq ($(CONFIG_IPV6),y)\n  DISABLE_IPV6:=\nelse\n  DISABLE_IPV6:=--disable-ipv6\nendif\n\nTAR_OPTIONS:=-xf -\n\nifeq ($(CONFIG_BUILD_LOG),y)\n  BUILD_LOG:=1\nendif\n\nexport BISON_PKGDATADIR:=$(STAGING_DIR_HOST)/share/bison\nexport M4:=$(STAGING_DIR_HOST)/bin/m4\n\ndefine shvar\nV_$(subst .,_,$(subst -,_,$(subst /,_,$(1))))\nendef\n\ndefine shexport\nexport $(call shvar,$(1))=$$(call $(1))\nendef\n\n# Execute commands under flock\n# $(1) => The shell expression.\n# $(2) => The lock name. If not given, the global lock will be used.\nifneq ($(wildcard $(STAGING_DIR_HOST)/bin/flock),)\n  define locked\n\tSHELL= \\\n\tflock \\\n\t\t$(TMP_DIR)/.$(if $(2),$(strip $(2)),global).flock \\\n\t\t-c '$(subst ','\\'',$(1))'\n  endef\nelse\n  locked=$(1)\nendif\n\n# Recursively copy paths into another directory, purge dangling\n# symlinks before.\n# $(1) => File glob expression\n# $(2) => Destination directory\ndefine file_copy\n\tfor src_dir in $(sort $(foreach d,$(wildcard $(1)),$(dir $(d)))); do \\\n\t\t( cd $$src_dir; find -type f -or -type d ) | \\\n\t\t\t( cd $(2); while :; do \\\n\t\t\t\tread FILE; \\\n\t\t\t\t[ -z \"$$FILE\" ] && break; \\\n\t\t\t\t[ -L \"$$FILE\" ] || continue; \\\n\t\t\t\techo \"Removing symlink $(2)/$$FILE\"; \\\n\t\t\t\trm -f \"$$FILE\"; \\\n\t\t\tdone; ); \\\n\tdone; \\\n\t$(CP) $(1) $(2)\nendef\n\n# Calculate sha256sum of any plain file within a given directory\n# $(1) => Input directory\n# $(2) => If set, recurse into subdirectories\ndefine sha256sums\n\t(cd $(1); find . $(if $(2),,-maxdepth 1) -type f -not -name 'sha256sums' -printf \"%P\\n\" | sort | \\\n\t\txargs -r $(MKHASH) -n sha256 | sed -ne 's!^\\(.*\\) \\(.*\\)$$!\\1 *\\2!p' > sha256sums)\nendef\n\n# file extension\next=$(word $(words $(subst ., ,$(1))),$(subst ., ,$(1)))\n\n# Count Git commits of a package\n# $(1) => if non-empty: count commits since last \": [uU]pdate to \" or \": [bB]ump to \" in commit message\ndefine commitcount\n$(shell \\\n  if git log -1 >/dev/null 2>/dev/null; then \\\n    if [ -n \"$(1)\" ]; then \\\n      last_bump=\"$$(git log --pretty=format:'%h %s' . | \\\n        grep --max-count=1 -e ': [uU]pdate to ' -e ': [bB]ump to ' | \\\n        cut -f 1 -d ' ')\"; \\\n    fi; \\\n    if [ -n \"$$last_bump\" ]; then \\\n      echo -n $$(($$(git rev-list --count \"$$last_bump..HEAD\" .) + 1)); \\\n    else \\\n      git rev-list --count HEAD .; \\\n    fi; \\\n  else \\\n    secs=\"$$(($(SOURCE_DATE_EPOCH) % 86400))\"; \\\n    date=\"$$(date --utc --date=\"@$(SOURCE_DATE_EPOCH)\" \"+%y%m%d\")\"; \\\n    printf '%s.%05d' \"$$date\" \"$$secs\"; \\\n  fi; \\\n)\nendef\n\nabi_version_str = $(subst -,,$(subst _,,$(subst .,,$(1))))\n\nCOMMITCOUNT = $(if $(DUMP),0,$(call commitcount))\nAUTORELEASE = $(if $(DUMP),0,$(call commitcount,1))\n\nall:\nFORCE: ;\n.PHONY: FORCE\n\ncheck: FORCE\n\t@true\n\nval.%:\n\t@$(if $(filter undefined,$(origin $*)),\\\n\t\techo \"$* undefined\" >&2, \\\n\t\techo '$(subst ','\"'\"',$($*))' \\\n\t)\n\nvar.%:\n\t@$(if $(filter undefined,$(origin $*)),\\\n\t\techo \"$* undefined\" >&2, \\\n\t\techo \"$*='\"'$(subst ','\"'\\\"'\\\"'\"',$($*))'\"'\" \\\n\t)\n\nendif #__rules_inc\n"
  },
  {
    "path": "scripts/arm-magic.sh",
    "content": "#!/bin/sh\n#\n#   Empty/wrong machtype-workaround generator\n#\n#   Copyright (C) 2006-2012 Imre Kaloz <kaloz@openwrt.org>\n#   based on linux/arch/arm/boot/compressed/head-xscale.S\n#\n#   This program is free software; you can redistribute it and/or modify\n#   it under the terms of the GNU General Public License as published by\n#   the Free Software Foundation; either version 2 of the License, or\n#   (at your option) any later version.\n#\n#   This program is distributed in the hope that it will be useful,\n#   but WITHOUT ANY WARRANTY; without even the implied warranty of\n#   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n#   GNU General Public License for more details.\n#\n#   You should have received a copy of the GNU General Public License\n#   along with this program; if not, write to the Free Software\n#   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA\n\n# NOTE: for now it's for only IXP4xx in big endian mode\n\n# list of supported boards, in \"boardname machtypeid\" format\nfor board in \"avila 526\" \"gateway7001 731\" \"nslu2 597\" \"nas100d 865\" \"wg302v1 889\" \"wg302v2 890\" \"pronghorn 928\" \"pronghornmetro 1040\" \"compex 1273\" \"wrt300nv2 1077\" \"loft 849\" \"dsmg600 964\" \"fsg3 1091\" \"ap1000 1543\" \"tw2662 1658\" \"tw5334 1664\" \"ixdpg425 604\" \"cambria 1468\" \"sidewinder 1041\" \"ap42x 4418\"\ndo\n  set -- $board\n  hexid=$(printf %x\\\\n $2)\n  if [ \"$2\" -lt \"256\" ]; then\n    # we have a low machtypeid, we just need a \"mov\" (e3a)\n    printf \"\\xe3\\xa0\\x10\\x$hexid\" > $BIN_DIR/$IMG_PREFIX-$1-zImage\n  else\n    # we have a high machtypeid, we need a \"mov\" (e3a) and an \"orr\" (e38)\n    if [ \"$2\" -lt \"4096\" ]; then\n      printf \"\\xe3\\xa0\\x10\\x$(echo $hexid|cut -b \"2 3\")\\xe3\\x81\\x1c\\x$(echo $hexid|cut -b 1)\" > $BIN_DIR/$IMG_PREFIX-$1-zImage\n    else\n      printf \"\\xe3\\xa0\\x10\\x$(echo $hexid|cut -b \"3 4\")\\xe3\\x81\\x1c\\x$(echo $hexid|cut -b \"1 2\")\" > $BIN_DIR/$IMG_PREFIX-$1-zImage\n    fi\n  fi\n    # generate the image\n    cat $BIN_DIR/$IMG_PREFIX-zImage >> $BIN_DIR/$IMG_PREFIX-$1-zImage\ndone\n"
  },
  {
    "path": "scripts/brcmImage.pl",
    "content": "#!/usr/bin/env perl\n#\n#    Copyright (C) 2009\tHenk Vergonet <Henk.Vergonet@gmail.com>\n#\n#    This program is free software; you can redistribute it and/or modify\n#    it under the terms of the GNU General Public License as published by\n#    the Free Software Foundation; either version 2 of the License, or\n#    (at your option) any later version.\n#\n#    This program is distributed in the hope that it will be useful,\n#    but WITHOUT ANY WARRANTY; without even the implied warranty of\n#    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n#    GNU General Public License for more details.\n#\n#    You should have received a copy of the GNU General Public License\n#    along with this program; if not, write to the Free Software\n#    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.\n#\n\n# Description:\n#   Replacement for brcmImagebuilder\n#\n# Disclaimer:\n#   Use this software at your own risk.\n#\n# Changelog:\n#   2009-01-01\tHenk.Vergonet at gmail.com\n#\nuse strict;\nuse Getopt::Std;\nuse Compress::Zlib;\n\nmy $version = \"0.1\";\nmy %arg = (\n\to => 'bcm963xx_fs_kernel',\n\tb => 'OpenWrt',\n\tc => '6348',\n\ts => 64,\n\tf => 0xbfc00000,\n\tx => 0x00010000,\n\ta => 0x80010000,\n\te => 0x80010000,\n\ti => 2,\n);\nmy $prog = $0;\n$prog =~ s/^.*\\///;\ngetopts(\"r:k:o:lc:b:s:f:i:a:e:tpvh\", \\%arg);\n\ndie \"usage: $prog ~opts~\n\n  -r <file>\t: input rootfs file\n  -k <file>\t: input kernel file\n  -o <file>\t: output image file, default $arg{o}\n  -l\t\t: littleendian system, default \".($arg{l} ? 'yes' : 'no').\"\n  -c <chipid>\t: default $arg{c} \n  -b <boardid>\t: default $arg{b} \n  -s <size_kb>\t: erase sise flash, default $arg{s} \n  -f <baseaddr>\t: flash base, default \".sprintf('0x%x', $arg{f}).\"\n  -x <cfelen>\t: length of cfe, default \".sprintf('0x%x', $arg{x}).\"\n  -i\t\t: 2=dual image, default $arg{i}\n\n  -a <loadaddr>\t: Kernel load address, default \".sprintf('0x%x', $arg{a}).\"\n  -e <entryaddr>: Kernel entry address, default \".sprintf('0x%x', $arg{e}).\"\n  -t\t\t: Prefix kernel with load,entry,size\n\n  -p\t\t: Add a 'gOtO' partition \n\n  -v\t\t: be more verbose\n  -h\t\t: help, version $version\n\nEXAMPLES:\n    $prog -k kern -r rootfs\n\" if $arg{h} || !$arg{k} || !$arg{r};\n\nsub Read_Image\n{\n\topen my $fh, $_[0] or die \"open $_[0]: $!\";\n\tlocal $/;\t# Set input to \"slurp\" mode.\n\tmy $buf = <$fh>;\n\tclose $fh;\n\treturn $buf;\n}\n\nsub Padlen\n{\n\tmy $p = $_[0] % $_[1];\n\treturn ($p ? $_[1] - $p : 0);\n}\n\nsub Pad\n{\n\tmy ($buf, $off, $bs) = @_[0..2];\n\t$buf .= chr(255) x Padlen(length($buf) + $off, $bs);\n\treturn $buf;\n}\n\nsub bcmImage\n{\n\tmy ($k, $f) = @_[0..1];\n\tmy $tmp = $arg{x} + 0x100 + $arg{f};\n\t\n\t# regular: rootfs+kernel\n\tmy ($img, $fa, $ka) = ( $f.$k, $tmp, $tmp + length($f) );\n\n\t# test: kernel+rootfs\n#\tmy ($img, $fa, $ka) = ( $k.$f, $tmp + length($k), $tmp );\n\n\t$fa = 0 unless length($f);\n\n\tmy $hdr = pack(\"a4a20a14a6a16a2a10a12a10a12a10a12a10a2a2a74Na16\",\n\t\t'6',\n\t\t'LinuxInside', \n\t\t'ver. 2.0', \n\t\t$arg{c},\n\t\t$arg{b},\n\t\t($arg{l} ? '0' : '1'),\n\t\tlength($img),\n\t\t'0',\n\t\t'0',\n\t\t$fa,\n\t\tlength($f),\n\t\t$ka,\n\t\tlength($k),\n\t\t($arg{i}==2 ? '1' : '0'),\n\t\t'',\t\t# if 1, the image is INACTIVE; if 0, active\n\t\t'',\n\t\t~crc32($k, crc32($f)),\n\t\t'');\n\t$hdr .= pack('Na16', ~crc32($hdr), '');\n\n\tprintf \"kernel at 0x%x length 0x%x(%u)\\n\", $ka, length($k), length($k)\n\t\tif $arg{v};\n\tprintf \"rootfs at 0x%x length 0x%x(%u)\\n\", $fa, length($f), length($f)\n\t\tif $arg{v};\n\n\topen(FO, \">$arg{o}\");\n\tprint FO $hdr;\n\tprint FO $img;\n\tclose FO;\n}\n\n# MAIN\n\nmy $kern = Read_Image $arg{k};\nmy $root = Read_Image $arg{r};\n\n$kern = pack('NNN', $arg{a}, $arg{e}, length($kern)).$kern if $arg{t};\n\n# specific fixup for the CFE that expects rootfs-kernel order\nif ($arg{p}) {\n\t$kern = Pad($kern, 0x10c, $arg{s} * 1024);\n\tmy $dummy_root = pack('a4NN',\n\t\t\t'gOtO',\n\t\t\tlength($kern)+12,\n\t\t\tlength($root)+Padlen(length($root), $arg{s} * 1024)\n\t);\n\t$kern .= $root;\n\t$root = $dummy_root;\n}\n\nbcmImage($kern, $root);\n\n"
  },
  {
    "path": "scripts/bundle-libraries.sh",
    "content": "#!/usr/bin/env bash\n#\n#   Script to install host system binaries along with required libraries.\n#\n#   Copyright (C) 2012-2017 Jo-Philipp Wich <jo@mein.io>\n#\n#   This program is free software; you can redistribute it and/or modify\n#   it under the terms of the GNU General Public License as published by\n#   the Free Software Foundation; either version 2 of the License, or\n#   (at your option) any later version.\n#\n#   This program is distributed in the hope that it will be useful,\n#   but WITHOUT ANY WARRANTY; without even the implied warranty of\n#   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n#   GNU General Public License for more details.\n#\n#   You should have received a copy of the GNU General Public License\n#   along with this program; if not, write to the Free Software\n#   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA\n\nDIR=\"$1\"; shift\n\n_cp() {\n\tcp ${VERBOSE:+-v} -L \"$1\" \"$2\" || {\n\t\techo \"cp($1 $2) failed\" >&2\n\t\texit 1\n\t}\n}\n\n_mv() {\n\tmv ${VERBOSE:+-v} \"$1\" \"$2\" || {\n\t\techo \"mv($1 $2) failed\" >&2\n\t\texit 1\n\t}\n}\n\n_md() {\n\tmkdir ${VERBOSE:+-v} -p \"$1\" || {\n\t\techo \"mkdir($1) failed\" >&2\n\t\texit 2\n\t}\n}\n\n_ln() {\n\tln ${VERBOSE:+-v} -sf \"$1\" \"$2\" || {\n\t\techo \"ln($1 $2) failed\" >&2\n\t\texit 3\n\t}\n}\n\n_relpath() {\n\tlocal base=\"$(readlink -f \"$1\")\"\n\tlocal dest=\"$(readlink -f \"$2\")\"\n\tlocal up\n\n\t[ -d \"$base\" ] || base=\"${base%/*}\"\n\t[ -d \"$dest\" ] || dest=\"${dest%/*}\"\n\n\twhile true; do\n\t\tcase \"$base\"\n\t\t\tin \"$dest\"/*)\n\t\t\t\techo \"$up/${base#$dest/}\"\n\t\t\t\tbreak\n\t\t\t;;\n\t\t\t*)\n\t\t\t\tdest=\"${dest%/*}\"\n\t\t\t\tup=\"${up:+$up/}..\"\n\t\t\t;;\n\t\tesac\n\tdone\n}\n\n_runas_so() {\n\tcat <<-EOT | ${CC:-gcc} -x c -fPIC -shared -o \"$1\" -\n\t\t#include <unistd.h>\n\t\t#include <stdio.h>\n\t\t#include <stdlib.h>\n\n\t\tint mangle_arg0(int argc, char **argv, char **env) {\n\t\t\tchar *arg0 = getenv(\"RUNAS_ARG0\");\n\n\t\t\tif (arg0) {\n\t\t\t\targv[0] = arg0;\n\t\t\t\tunsetenv(\"RUNAS_ARG0\");\n\t\t\t}\n\n\t\t\treturn 0;\n\t\t}\n\n\t\t#ifdef __APPLE__\n\t\t__attribute__((section(\"__DATA,__mod_init_func\")))\n\t\t#else\n\t\t__attribute__((section(\".init_array\")))\n\t\t#endif\n\t\tstatic void *mangle_arg0_constructor = &mangle_arg0;\n\tEOT\n\n\t[ -x \"$1\" ] || {\n\t\techo \"compiling preload library failed\" >&2\n\t\texit 5\n\t}\n}\n\n_patch_ldso() {\n\t_cp \"$1\" \"$1.patched\"\n\tsed -i -e 's,/\\(usr\\|lib\\|etc\\)/,/###/,g' \"$1.patched\"\n\n\tif \"$1.patched\" 2>&1 | grep -q -- --library-path; then\n\t\t_mv \"$1.patched\" \"$1\"\n\telse\n\t\techo \"binary patched ${1##*/} not executable, using original\" >&2\n\t\trm -f \"$1.patched\"\n\tfi\n}\n\n_patch_glibc() {\n\t_cp \"$1\" \"$1.patched\"\n\tsed -i -e 's,/usr/\\(\\(lib\\|share\\)/locale\\),/###/\\1,g' \"$1.patched\"\n\n\tif \"$1.patched\" 2>&1 | grep -q -- GNU; then\n\t\t_mv \"$1.patched\" \"$1\"\n\telse\n\t\techo \"binary patched ${1##*/} not executable, using original\" >&2\n\t\trm -f \"$1.patched\"\n\tfi\n}\n\nshould_be_patched() {\n\tlocal bin=\"$1\"\n\n\t[ -x \"$bin\" ] || return 1\n\n\tcase \"$bin\" in\n\t\t*.so|*.so.[0-9]*)\n\t\t\treturn 1\n\t\t;;\n\t\t*)\n\t\t\tfile \"$bin\" | grep -sqE \"ELF.*(executable|interpreter)\" && return 0\n\t\t;;\n\tesac\n\n\treturn 1\n}\n\nfor LDD in ${PATH//://ldd }/ldd; do\n\t\"$LDD\" --version >/dev/null 2>/dev/null && break\n\tLDD=\"\"\ndone\n\n[ -n \"$LDD\" -a -x \"$LDD\" ] || LDD=\n\nfor BIN in \"$@\"; do\n\t[ -n \"$BIN\" -a -n \"$DIR\" ] || {\n\t\techo \"Usage: $0 <destdir> <executable> ...\" >&2\n\t\texit 1\n\t}\n\n\t[ ! -d \"$DIR/lib\" ] && {\n\t\t_md \"$DIR/lib\"\n\t\t_md \"$DIR/usr\"\n\t\t_ln \"../lib\" \"$DIR/usr/lib\"\n\t}\n\n\t[ ! -x \"$DIR/lib/runas.so\" ] && {\n\t\t_runas_so \"$DIR/lib/runas.so\"\n\t}\n\n\tLDSO=\"\"\n\n\t[ -n \"$LDD\" ] && should_be_patched \"$BIN\" && {\n\t\tfor token in $(\"$LDD\" \"$BIN\" 2>/dev/null); do\n\t\t\tcase \"$token\" in */*.so*)\n\t\t\t\tdest=\"$DIR/lib/${token##*/}\"\n\t\t\t\tddir=\"${dest%/*}\"\n\n\t\t\t\tcase \"$token\" in\n\t\t\t\t\t*/ld-*.so*) LDSO=\"${token##*/}\" ;;\n\t\t\t\tesac\n\n\t\t\t\t[ -f \"$token\" -a ! -f \"$dest\" ] && {\n\t\t\t\t\t_md \"$ddir\"\n\t\t\t\t\t_cp \"$token\" \"$dest\"\n\t\t\t\t\tcase \"$token\" in\n\t\t\t\t\t\t*/ld-*.so*) _patch_ldso \"$dest\" ;;\n\t\t\t\t\t\t*/libc.so.6) _patch_glibc \"$dest\" ;;\n\t\t\t\t\tesac\n\t\t\t\t}\n\t\t\t;; esac\n\t\tdone\n\t}\n\n\t# is a dynamically linked executable\n\tif [ -n \"$LDSO\" ]; then\n\t\techo \"Bundling ${BIN##*/}\"\n\n\t\tRUNDIR=\"$(readlink -f \"$BIN\")\"; RUNDIR=\"${RUNDIR%/*}\"\n\t\tRUN=\"${LDSO#ld-}\"; RUN=\"run-${RUN%%.so*}.sh\"\n\t\tREL=\"$(_relpath \"$DIR/lib\" \"$BIN\")\"\n\n\t\t_mv \"$BIN\" \"$RUNDIR/.${BIN##*/}.bin\"\n\n\t\tcat <<-EOF > \"$BIN\"\n\t\t\t#!/usr/bin/env bash\n\t\t\tdir=\"\\$(dirname \"\\$0\")\"\n\t\t\texport RUNAS_ARG0=\"\\$0\"\n\t\t\texport LD_PRELOAD=\"\\${LD_PRELOAD:+\\$LD_PRELOAD:}\\$dir/${REL:+$REL/}runas.so\"\n\t\t\texec \"\\$dir/${REL:+$REL/}$LDSO\" --library-path \"\\$dir/${REL:+$REL/}\" \"\\$dir/.${BIN##*/}.bin\" \"\\$@\"\n\t\tEOF\n\n\t\tchmod ${VERBOSE:+-v} 0755 \"$BIN\"\n\tfi\ndone\n"
  },
  {
    "path": "scripts/cfe-bin-header.py",
    "content": "#!/usr/bin/env python3\n\nimport argparse\nimport os\nimport struct\n\ndef auto_int(x):\n\treturn int(x, 0)\n\ndef create_header(args, size):\n\theader = struct.pack('>III', args.entry_addr, args.load_addr, size)\n\treturn header\n\ndef create_output(args):\n\tin_st = os.stat(args.input_file)\n\tin_size = in_st.st_size\n\n\theader = create_header(args, in_size)\n\tprint(header)\n\n\tin_f = open(args.input_file, 'r+b')\n\tin_bytes = in_f.read(in_size)\n\tin_f.close()\n\n\tout_f = open(args.output_file, 'w+b')\n\tout_f.write(header)\n\tout_f.write(in_bytes)\n\tout_f.close()\n\ndef main():\n\tglobal args\n\n\tparser = argparse.ArgumentParser(description='')\n\n\tparser.add_argument('--entry-addr',\n\t\tdest='entry_addr',\n\t\taction='store',\n\t\ttype=auto_int,\n\t\thelp='Entry Address')\n\n\tparser.add_argument('--input-file',\n\t\tdest='input_file',\n\t\taction='store',\n\t\ttype=str,\n\t\thelp='Input file')\n\n\tparser.add_argument('--load-addr',\n\t\tdest='load_addr',\n\t\taction='store',\n\t\ttype=auto_int,\n\t\thelp='Load Address')\n\n\tparser.add_argument('--output-file',\n\t\tdest='output_file',\n\t\taction='store',\n\t\ttype=str,\n\t\thelp='Output file')\n\n\targs = parser.parse_args()\n\n\tif (not args.input_file) or (not args.output_file):\n\t\tparser.print_help()\n\n\tif not args.entry_addr:\n\t\targs.entry_addr = 0x80010000\n\n\tif not args.load_addr:\n\t\targs.load_addr = 0x80010000\n\n\tcreate_output(args)\n\nmain()\n"
  },
  {
    "path": "scripts/cfe-partition-tag.py",
    "content": "#!/usr/bin/env python3\n\n\"\"\"\nCFE Partition Tag\n\n{\n\tu32 part_id;\n\tu32 part_size;\n\tu16 flags;\n\tchar part_name[33];\n\tchar part_version[21];\n\tu32 part_crc32;\n}\n\n\"\"\"\n\nimport argparse\nimport os\nimport struct\nimport binascii\n\n\nPART_NAME_SIZE = 33\nPART_VERSION_SIZE = 21\n\n\ndef auto_int(x):\n    return int(x, 0)\n\n\ndef str_to_bytes_pad(string, size):\n    str_bytes = string.encode()\n    num_bytes = len(str_bytes)\n    if num_bytes >= size:\n        str_bytes = str_bytes[: size - 1] + \"\\0\".encode()\n    else:\n        str_bytes += \"\\0\".encode() * (size - num_bytes)\n    return str_bytes\n\n\ndef create_tag(args, in_bytes, size):\n    # JAM CRC32 is bitwise not and unsigned\n    crc = ~binascii.crc32(in_bytes) & 0xFFFFFFFF\n\n    tag = bytearray()\n    tag += struct.pack(\">I\", args.part_id)\n    tag += struct.pack(\">I\", size)\n    tag += struct.pack(\">H\", args.part_flags)\n    tag += str_to_bytes_pad(args.part_name, PART_NAME_SIZE)\n    tag += str_to_bytes_pad(args.part_version, PART_VERSION_SIZE)\n    tag += struct.pack(\">I\", crc)\n\n    return tag\n\n\ndef create_output(args):\n    in_st = os.stat(args.input_file)\n    in_size = in_st.st_size\n\n    in_f = open(args.input_file, \"r+b\")\n    in_bytes = in_f.read(in_size)\n    in_f.close()\n\n    tag = create_tag(args, in_bytes, in_size)\n\n    out_f = open(args.output_file, \"w+b\")\n    out_f.write(tag)\n    out_f.close()\n\n\ndef main():\n    global args\n\n    parser = argparse.ArgumentParser(description=\"\")\n\n    parser.add_argument(\n        \"--flags\",\n        dest=\"part_flags\",\n        action=\"store\",\n        type=auto_int,\n        help=\"Partition Flags\",\n    )\n\n    parser.add_argument(\n        \"--id\",\n        dest=\"part_id\",\n        action=\"store\",\n        type=auto_int,\n        help=\"Partition ID\",\n    )\n\n    parser.add_argument(\n        \"--input-file\",\n        dest=\"input_file\",\n        action=\"store\",\n        type=str,\n        help=\"Input file\",\n    )\n\n    parser.add_argument(\n        \"--output-file\",\n        dest=\"output_file\",\n        action=\"store\",\n        type=str,\n        help=\"Output file\",\n    )\n\n    parser.add_argument(\n        \"--name\",\n        dest=\"part_name\",\n        action=\"store\",\n        type=str,\n        help=\"Partition Name\",\n    )\n\n    parser.add_argument(\n        \"--version\",\n        dest=\"part_version\",\n        action=\"store\",\n        type=str,\n        help=\"Partition Version\",\n    )\n\n    args = parser.parse_args()\n\n    if (\n        (not args.part_flags)\n        or (not args.part_id)\n        or (not args.input_file)\n        or (not args.output_file)\n        or (not args.part_name)\n        or (not args.part_version)\n    ):\n        parser.print_help()\n    else:\n        create_output(args)\n\n\nmain()\n"
  },
  {
    "path": "scripts/cfe-wfi-tag.py",
    "content": "#!/usr/bin/env python3\n\n\"\"\"\nWhole Flash Image Tag\n\n{\n\tu32 crc32;\n\tu32 version;\n\tu32 chipID;\n\tu32 flashType;\n\tu32 flags;\n}\n\nCRC32: Ethernet (Poly 0x04C11DB7)\n\nVersion:\n\t0x00005700: Any version\n\t0x00005731: NAND 1MB data partition\n\t0x00005732: Normal version\n\nChip ID:\n\tBroadcom Chip ID\n\t0x00006328: BCM6328\n\t0x00006362: BCM6362\n\t0x00006368: BCM6368\n\t0x00063268: BCM63268\n\nFlash Type:\n\t1: NOR\n\t2: NAND 16k blocks\n\t3: NAND 128k blocks\n\t4: NAND 256k blocks\n\t5: NAND 512k blocks\n\t6: NAND 1MB blocks\n\t7: NAND 2MB blocks\n\nFlags:\n\t0x00000001: PMC\n\t0x00000002: Secure BootROM\n\n\"\"\"\n\nimport argparse\nimport os\nimport struct\nimport binascii\n\n\ndef auto_int(x):\n    return int(x, 0)\n\n\ndef create_tag(args, in_bytes):\n    # JAM CRC32 is bitwise not and unsigned\n    crc = ~binascii.crc32(in_bytes) & 0xFFFFFFFF\n    tag = struct.pack(\n        \">IIIII\",\n        crc,\n        args.tag_version,\n        args.chip_id,\n        args.flash_type,\n        args.flags,\n    )\n    return tag\n\n\ndef create_output(args):\n    in_st = os.stat(args.input_file)\n    in_size = in_st.st_size\n\n    in_f = open(args.input_file, \"r+b\")\n    in_bytes = in_f.read(in_size)\n    in_f.close()\n\n    tag = create_tag(args, in_bytes)\n\n    out_f = open(args.output_file, \"w+b\")\n    out_f.write(in_bytes)\n    out_f.write(tag)\n    out_f.close()\n\n\ndef main():\n    global args\n\n    parser = argparse.ArgumentParser(description=\"\")\n\n    parser.add_argument(\n        \"--input-file\",\n        dest=\"input_file\",\n        action=\"store\",\n        type=str,\n        help=\"Input file\",\n    )\n\n    parser.add_argument(\n        \"--output-file\",\n        dest=\"output_file\",\n        action=\"store\",\n        type=str,\n        help=\"Output file\",\n    )\n\n    parser.add_argument(\n        \"--version\",\n        dest=\"tag_version\",\n        action=\"store\",\n        type=auto_int,\n        help=\"WFI Tag Version\",\n    )\n\n    parser.add_argument(\n        \"--chip-id\",\n        dest=\"chip_id\",\n        action=\"store\",\n        type=auto_int,\n        help=\"WFI Chip ID\",\n    )\n\n    parser.add_argument(\n        \"--flash-type\",\n        dest=\"flash_type\",\n        action=\"store\",\n        type=auto_int,\n        help=\"WFI Flash Type\",\n    )\n\n    parser.add_argument(\n        \"--flags\", dest=\"flags\", action=\"store\", type=auto_int, help=\"WFI Flags\"\n    )\n\n    args = parser.parse_args()\n\n    if not args.flags:\n        args.flags = 0\n\n    if (\n        (not args.input_file)\n        or (not args.output_file)\n        or (not args.tag_version)\n        or (not args.chip_id)\n        or (not args.flash_type)\n    ):\n        parser.print_help()\n    else:\n        create_output(args)\n\n\nmain()\n"
  },
  {
    "path": "scripts/check-toolchain-clean.sh",
    "content": "#!/bin/sh\neval \"$(grep CONFIG_GCC_VERSION .config)\"\nCONFIG_TOOLCHAIN_BUILD_VER=\"$CONFIG_GCC_VERSION-$(cat toolchain/build_version)\"\ntouch .toolchain_build_ver\nCURRENT_TOOLCHAIN_BUILD_VER=\"$(cat .toolchain_build_ver)\"\n[ -z \"$CURRENT_TOOLCHAIN_BUILD_VER\" ] && {\n\techo \"$CONFIG_TOOLCHAIN_BUILD_VER\" > .toolchain_build_ver\n\texit 0\n}\n[ \"$CONFIG_TOOLCHAIN_BUILD_VER\" = \"$CURRENT_TOOLCHAIN_BUILD_VER\" ] && exit 0\necho \"Toolchain build version changed ($CONFIG_TOOLCHAIN_BUILD_VER != $CURRENT_TOOLCHAIN_BUILD_VER), running make targetclean\"\nmake targetclean\necho \"$CONFIG_TOOLCHAIN_BUILD_VER\" > .toolchain_build_ver\nexit 0\n"
  },
  {
    "path": "scripts/checkpatch.pl",
    "content": "#!/usr/bin/env perl\n# SPDX-License-Identifier: GPL-2.0\n#\n# (c) 2001, Dave Jones. (the file handling bit)\n# (c) 2005, Joel Schopp <jschopp@austin.ibm.com> (the ugly bit)\n# (c) 2007,2008, Andy Whitcroft <apw@uk.ibm.com> (new conditions, test suite)\n# (c) 2008-2010 Andy Whitcroft <apw@canonical.com>\n# (c) 2013 Vasilis Tsiligiannis <acinonyx@openwrt.gr> (adapt for OpenWrt tree)\n# (c) 2010-2018 Joe Perches <joe@perches.com>\n\nuse strict;\nuse warnings;\nuse POSIX;\nuse File::Basename;\nuse Cwd 'abs_path';\nuse Term::ANSIColor qw(:constants);\nuse Encode qw(decode encode);\n\nmy $P = $0;\nmy $D = dirname(abs_path($P));\n\nmy $V = '0.32-openwrt';\n\nuse Getopt::Long qw(:config no_auto_abbrev);\n\nmy $quiet = 0;\nmy $tree = 1;\nmy $chk_signoff = 1;\nmy $chk_patch = 1;\nmy $tst_only;\nmy $emacs = 0;\nmy $terse = 0;\nmy $showfile = 0;\nmy $file = 0;\nmy $git = 0;\nmy %git_commits = ();\nmy $check = 0;\nmy $check_orig = 0;\nmy $summary = 1;\nmy $mailback = 0;\nmy $summary_file = 0;\nmy $show_types = 0;\nmy $list_types = 0;\nmy $fix = 0;\nmy $fix_inplace = 0;\nmy $root;\nmy %debug;\nmy %camelcase = ();\nmy %use_type = ();\nmy @use = ();\nmy %ignore_type = ();\nmy @ignore = ();\nmy $help = 0;\nmy $configuration_file = \".checkpatch.conf\";\nmy $max_line_length = 100;\nmy $ignore_perl_version = 0;\nmy $minimum_perl_version = 5.10.0;\nmy $min_conf_desc_length = 4;\nmy $spelling_file = \"$D/spelling.txt\";\nmy $codespell = 0;\nmy $codespellfile = \"/usr/share/codespell/dictionary.txt\";\nmy $conststructsfile = \"$D/const_structs.checkpatch\";\nmy $typedefsfile = \"\";\nmy $color = \"auto\";\nmy $allow_c99_comments = 1; # Can be overridden by --ignore C99_COMMENT_TOLERANCE\n# git output parsing needs US English output, so first set backtick child process LANGUAGE\nmy $git_command ='export LANGUAGE=en_US.UTF-8; git';\nmy $tabsize = 8;\n\nsub help {\n\tmy ($exitcode) = @_;\n\n\tprint << \"EOM\";\nUsage: $P [OPTION]... [FILE]...\nVersion: $V\n\nOptions:\n  -q, --quiet                quiet\n  --no-tree                  run without a OpenWrt tree\n  --no-signoff               do not check for 'Signed-off-by' line\n  --patch                    treat FILE as patchfile (default)\n  --emacs                    emacs compile window format\n  --terse                    one line per report\n  --showfile                 emit diffed file position, not input file position\n  -g, --git                  treat FILE as a single commit or git revision range\n                             single git commit with:\n                               <rev>\n                               <rev>^\n                               <rev>~n\n                             multiple git commits with:\n                               <rev1>..<rev2>\n                               <rev1>...<rev2>\n                               <rev>-<count>\n                             git merges are ignored\n  -f, --file                 treat FILE as regular source file\n  --subjective, --strict     enable more subjective tests\n  --list-types               list the possible message types\n  --types TYPE(,TYPE2...)    show only these comma separated message types\n  --ignore TYPE(,TYPE2...)   ignore various comma separated message types\n  --show-types               show the specific message type in the output\n  --max-line-length=n        set the maximum line length, (default $max_line_length)\n                             if exceeded, warn on patches\n                             requires --strict for use with --file\n  --min-conf-desc-length=n   set the min description length, if shorter, warn\n  --tab-size=n               set the number of spaces for tab (default $tabsize)\n  --root=PATH                PATH to the OpenWrt tree root\n  --no-summary               suppress the per-file summary\n  --mailback                 only produce a report in case of warnings/errors\n  --summary-file             include the filename in summary\n  --debug KEY=[0|1]          turn on/off debugging of KEY, where KEY is one of\n                             'values', 'possible', 'type', and 'attr' (default\n                             is all off)\n  --test-only=WORD           report only warnings/errors containing WORD\n                             literally\n  --fix                      EXPERIMENTAL - may create horrible results\n                             If correctable single-line errors exist, create\n                             \"<inputfile>.EXPERIMENTAL-checkpatch-fixes\"\n                             with potential errors corrected to the preferred\n                             checkpatch style\n  --fix-inplace              EXPERIMENTAL - may create horrible results\n                             Is the same as --fix, but overwrites the input\n                             file.  It's your fault if there's no backup or git\n  --ignore-perl-version      override checking of perl version.  expect\n                             runtime errors.\n  --codespell                Use the codespell dictionary for spelling/typos\n                             (default:/usr/share/codespell/dictionary.txt)\n  --codespellfile            Use this codespell dictionary\n  --typedefsfile             Read additional types from this file\n  --color[=WHEN]             Use colors 'always', 'never', or only when output\n                             is a terminal ('auto'). Default is 'auto'.\n  -h, --help, --version      display this help and exit\n\nWhen FILE is - read standard input.\nEOM\n\n\texit($exitcode);\n}\n\nsub uniq {\n\tmy %seen;\n\treturn grep { !$seen{$_}++ } @_;\n}\n\nsub list_types {\n\tmy ($exitcode) = @_;\n\n\tmy $count = 0;\n\n\tlocal $/ = undef;\n\n\topen(my $script, '<', abs_path($P)) or\n\t    die \"$P: Can't read '$P' $!\\n\";\n\n\tmy $text = <$script>;\n\tclose($script);\n\n\tmy @types = ();\n\t# Also catch when type or level is passed through a variable\n\tfor ($text =~ /(?:(?:\\bCHK|\\bWARN|\\bERROR|&\\{\\$msg_level})\\s*\\(|\\$msg_type\\s*=)\\s*\"([^\"]+)\"/g) {\n\t\tpush (@types, $_);\n\t}\n\t@types = sort(uniq(@types));\n\tprint(\"#\\tMessage type\\n\\n\");\n\tforeach my $type (@types) {\n\t\tprint(++$count . \"\\t\" . $type . \"\\n\");\n\t}\n\n\texit($exitcode);\n}\n\nmy $conf = which_conf($configuration_file);\nif (-f $conf) {\n\tmy @conf_args;\n\topen(my $conffile, '<', \"$conf\")\n\t    or warn \"$P: Can't find a readable $configuration_file file $!\\n\";\n\n\twhile (<$conffile>) {\n\t\tmy $line = $_;\n\n\t\t$line =~ s/\\s*\\n?$//g;\n\t\t$line =~ s/^\\s*//g;\n\t\t$line =~ s/\\s+/ /g;\n\n\t\tnext if ($line =~ m/^\\s*#/);\n\t\tnext if ($line =~ m/^\\s*$/);\n\n\t\tmy @words = split(\" \", $line);\n\t\tforeach my $word (@words) {\n\t\t\tlast if ($word =~ m/^#/);\n\t\t\tpush (@conf_args, $word);\n\t\t}\n\t}\n\tclose($conffile);\n\tunshift(@ARGV, @conf_args) if @conf_args;\n}\n\n# Perl's Getopt::Long allows options to take optional arguments after a space.\n# Prevent --color by itself from consuming other arguments\nforeach (@ARGV) {\n\tif ($_ eq \"--color\" || $_ eq \"-color\") {\n\t\t$_ = \"--color=$color\";\n\t}\n}\n\nGetOptions(\n\t'q|quiet+'\t=> \\$quiet,\n\t'tree!'\t\t=> \\$tree,\n\t'signoff!'\t=> \\$chk_signoff,\n\t'patch!'\t=> \\$chk_patch,\n\t'emacs!'\t=> \\$emacs,\n\t'terse!'\t=> \\$terse,\n\t'showfile!'\t=> \\$showfile,\n\t'f|file!'\t=> \\$file,\n\t'g|git!'\t=> \\$git,\n\t'subjective!'\t=> \\$check,\n\t'strict!'\t=> \\$check,\n\t'ignore=s'\t=> \\@ignore,\n\t'types=s'\t=> \\@use,\n\t'show-types!'\t=> \\$show_types,\n\t'list-types!'\t=> \\$list_types,\n\t'max-line-length=i' => \\$max_line_length,\n\t'min-conf-desc-length=i' => \\$min_conf_desc_length,\n\t'tab-size=i'\t=> \\$tabsize,\n\t'root=s'\t=> \\$root,\n\t'summary!'\t=> \\$summary,\n\t'mailback!'\t=> \\$mailback,\n\t'summary-file!'\t=> \\$summary_file,\n\t'fix!'\t\t=> \\$fix,\n\t'fix-inplace!'\t=> \\$fix_inplace,\n\t'ignore-perl-version!' => \\$ignore_perl_version,\n\t'debug=s'\t=> \\%debug,\n\t'test-only=s'\t=> \\$tst_only,\n\t'codespell!'\t=> \\$codespell,\n\t'codespellfile=s'\t=> \\$codespellfile,\n\t'typedefsfile=s'\t=> \\$typedefsfile,\n\t'color=s'\t=> \\$color,\n\t'no-color'\t=> \\$color,\t#keep old behaviors of -nocolor\n\t'nocolor'\t=> \\$color,\t#keep old behaviors of -nocolor\n\t'h|help'\t=> \\$help,\n\t'version'\t=> \\$help\n) or help(1);\n\nhelp(0) if ($help);\n\nlist_types(0) if ($list_types);\n\n$fix = 1 if ($fix_inplace);\n$check_orig = $check;\n\ndie \"$P: --git cannot be used with --file or --fix\\n\" if ($git && ($file || $fix));\n\nmy $exit = 0;\n\nmy $perl_version_ok = 1;\nif ($^V && $^V lt $minimum_perl_version) {\n\t$perl_version_ok = 0;\n\tprintf \"$P: requires at least perl version %vd\\n\", $minimum_perl_version;\n\texit(1) if (!$ignore_perl_version);\n}\n\n#if no filenames are given, push '-' to read patch from stdin\nif ($#ARGV < 0) {\n\tpush(@ARGV, '-');\n}\n\nif ($color =~ /^[01]$/) {\n\t$color = !$color;\n} elsif ($color =~ /^always$/i) {\n\t$color = 1;\n} elsif ($color =~ /^never$/i) {\n\t$color = 0;\n} elsif ($color =~ /^auto$/i) {\n\t$color = (-t STDOUT);\n} else {\n\tdie \"$P: Invalid color mode: $color\\n\";\n}\n\n# skip TAB size 1 to avoid additional checks on $tabsize - 1\ndie \"$P: Invalid TAB size: $tabsize\\n\" if ($tabsize < 2);\n\nsub hash_save_array_words {\n\tmy ($hashRef, $arrayRef) = @_;\n\n\tmy @array = split(/,/, join(',', @$arrayRef));\n\tforeach my $word (@array) {\n\t\t$word =~ s/\\s*\\n?$//g;\n\t\t$word =~ s/^\\s*//g;\n\t\t$word =~ s/\\s+/ /g;\n\t\t$word =~ tr/[a-z]/[A-Z]/;\n\n\t\tnext if ($word =~ m/^\\s*#/);\n\t\tnext if ($word =~ m/^\\s*$/);\n\n\t\t$hashRef->{$word}++;\n\t}\n}\n\nsub hash_show_words {\n\tmy ($hashRef, $prefix) = @_;\n\n\tif (keys %$hashRef) {\n\t\tprint \"\\nNOTE: $prefix message types:\";\n\t\tforeach my $word (sort keys %$hashRef) {\n\t\t\tprint \" $word\";\n\t\t}\n\t\tprint \"\\n\";\n\t}\n}\n\nhash_save_array_words(\\%ignore_type, \\@ignore);\nhash_save_array_words(\\%use_type, \\@use);\n\nmy $dbg_values = 0;\nmy $dbg_possible = 0;\nmy $dbg_type = 0;\nmy $dbg_attr = 0;\nfor my $key (keys %debug) {\n\t## no critic\n\teval \"\\${dbg_$key} = '$debug{$key}';\";\n\tdie \"$@\" if ($@);\n}\n\nmy $rpt_cleaners = 0;\n\nif ($terse) {\n\t$emacs = 1;\n\t$quiet++;\n}\n\nif ($tree) {\n\tif (defined $root) {\n\t\tif (!top_of_openwrt_tree($root)) {\n\t\t\tdie \"$P: $root: --root does not point at a valid tree\\n\";\n\t\t}\n\t} else {\n\t\tif (top_of_openwrt_tree('.')) {\n\t\t\t$root = '.';\n\t\t} elsif ($0 =~ m@(.*)/scripts/[^/]*$@ &&\n\t\t\t\t\t\ttop_of_openwrt_tree($1)) {\n\t\t\t$root = $1;\n\t\t}\n\t}\n\n\tif (!defined $root) {\n\t\tprint \"Must be run from the top-level dir. of a OpenWrt tree\\n\";\n\t\texit(2);\n\t}\n}\n\nmy $emitted_corrupt = 0;\n\nour $Ident\t= qr{\n\t\t\t[A-Za-z_][A-Za-z\\d_]*\n\t\t\t(?:\\s*\\#\\#\\s*[A-Za-z_][A-Za-z\\d_]*)*\n\t\t}x;\nour $Storage\t= qr{extern|static|asmlinkage};\nour $Sparse\t= qr{\n\t\t\t__user|\n\t\t\t__kernel|\n\t\t\t__force|\n\t\t\t__iomem|\n\t\t\t__must_check|\n\t\t\t__kprobes|\n\t\t\t__ref|\n\t\t\t__refconst|\n\t\t\t__refdata|\n\t\t\t__rcu|\n\t\t\t__private\n\t\t}x;\nour $InitAttributePrefix = qr{__(?:mem|cpu|dev|net_|)};\nour $InitAttributeData = qr{$InitAttributePrefix(?:initdata\\b)};\nour $InitAttributeConst = qr{$InitAttributePrefix(?:initconst\\b)};\nour $InitAttributeInit = qr{$InitAttributePrefix(?:init\\b)};\nour $InitAttribute = qr{$InitAttributeData|$InitAttributeConst|$InitAttributeInit};\n\n# Notes to $Attribute:\n# We need \\b after 'init' otherwise 'initconst' will cause a false positive in a check\nour $Attribute\t= qr{\n\t\t\tconst|\n\t\t\t__percpu|\n\t\t\t__nocast|\n\t\t\t__safe|\n\t\t\t__bitwise|\n\t\t\t__packed__|\n\t\t\t__packed2__|\n\t\t\t__naked|\n\t\t\t__maybe_unused|\n\t\t\t__always_unused|\n\t\t\t__noreturn|\n\t\t\t__used|\n\t\t\t__cold|\n\t\t\t__pure|\n\t\t\t__noclone|\n\t\t\t__deprecated|\n\t\t\t__read_mostly|\n\t\t\t__ro_after_init|\n\t\t\t__kprobes|\n\t\t\t$InitAttribute|\n\t\t\t____cacheline_aligned|\n\t\t\t____cacheline_aligned_in_smp|\n\t\t\t____cacheline_internodealigned_in_smp|\n\t\t\t__weak\n\t\t  }x;\nour $Modifier;\nour $Inline\t= qr{inline|__always_inline|noinline|__inline|__inline__};\nour $Member\t= qr{->$Ident|\\.$Ident|\\[[^]]*\\]};\nour $Lval\t= qr{$Ident(?:$Member)*};\n\nour $Int_type\t= qr{(?i)llu|ull|ll|lu|ul|l|u};\nour $Binary\t= qr{(?i)0b[01]+$Int_type?};\nour $Hex\t= qr{(?i)0x[0-9a-f]+$Int_type?};\nour $Int\t= qr{[0-9]+$Int_type?};\nour $Octal\t= qr{0[0-7]+$Int_type?};\nour $String\t= qr{\"[X\\t]*\"};\nour $Float_hex\t= qr{(?i)0x[0-9a-f]+p-?[0-9]+[fl]?};\nour $Float_dec\t= qr{(?i)(?:[0-9]+\\.[0-9]*|[0-9]*\\.[0-9]+)(?:e-?[0-9]+)?[fl]?};\nour $Float_int\t= qr{(?i)[0-9]+e-?[0-9]+[fl]?};\nour $Float\t= qr{$Float_hex|$Float_dec|$Float_int};\nour $Constant\t= qr{$Float|$Binary|$Octal|$Hex|$Int};\nour $Assignment\t= qr{\\*\\=|/=|%=|\\+=|-=|<<=|>>=|&=|\\^=|\\|=|=};\nour $Compare    = qr{<=|>=|==|!=|<|(?<!-)>};\nour $Arithmetic = qr{\\+|-|\\*|\\/|%};\nour $Operators\t= qr{\n\t\t\t<=|>=|==|!=|\n\t\t\t=>|->|<<|>>|<|>|!|~|\n\t\t\t&&|\\|\\||,|\\^|\\+\\+|--|&|\\||$Arithmetic\n\t\t  }x;\n\nour $c90_Keywords = qr{do|for|while|if|else|return|goto|continue|switch|default|case|break}x;\n\nour $BasicType;\nour $NonptrType;\nour $NonptrTypeMisordered;\nour $NonptrTypeWithAttr;\nour $Type;\nour $TypeMisordered;\nour $Declare;\nour $DeclareMisordered;\n\nour $NON_ASCII_UTF8\t= qr{\n\t[\\xC2-\\xDF][\\x80-\\xBF]               # non-overlong 2-byte\n\t|  \\xE0[\\xA0-\\xBF][\\x80-\\xBF]        # excluding overlongs\n\t| [\\xE1-\\xEC\\xEE\\xEF][\\x80-\\xBF]{2}  # straight 3-byte\n\t|  \\xED[\\x80-\\x9F][\\x80-\\xBF]        # excluding surrogates\n\t|  \\xF0[\\x90-\\xBF][\\x80-\\xBF]{2}     # planes 1-3\n\t| [\\xF1-\\xF3][\\x80-\\xBF]{3}          # planes 4-15\n\t|  \\xF4[\\x80-\\x8F][\\x80-\\xBF]{2}     # plane 16\n}x;\n\nour $UTF8\t= qr{\n\t[\\x09\\x0A\\x0D\\x20-\\x7E]              # ASCII\n\t| $NON_ASCII_UTF8\n}x;\n\nour $typeC99Typedefs = qr{(?:__)?(?:[us]_?)?int_?(?:8|16|32|64)_t};\nour $typeOtherOSTypedefs = qr{(?x:\n\tu_(?:char|short|int|long) |          # bsd\n\tu(?:nchar|short|int|long)            # sysv\n)};\nour $typeKernelTypedefs = qr{(?x:\n\t(?:__)?(?:u|s|be|le)(?:8|16|32|64)|\n\tatomic_t\n)};\nour $typeTypedefs = qr{(?x:\n\t$typeC99Typedefs\\b|\n\t$typeOtherOSTypedefs\\b|\n\t$typeKernelTypedefs\\b\n)};\n\nour $zero_initializer = qr{(?:(?:0[xX])?0+$Int_type?|NULL|false)\\b};\n\nour $logFunctions = qr{(?x:\n\tprintk(?:_ratelimited|_once|_deferred_once|_deferred|)|\n\t(?:[a-z0-9]+_){1,2}(?:printk|emerg|alert|crit|err|warning|warn|notice|info|debug|dbg|vdbg|devel|cont|WARN)(?:_ratelimited|_once|)|\n\tTP_printk|\n\tWARN(?:_RATELIMIT|_ONCE|)|\n\tpanic|\n\tMODULE_[A-Z_]+|\n\tseq_vprintf|seq_printf|seq_puts\n)};\n\nour $allocFunctions = qr{(?x:\n\t(?:(?:devm_)?\n\t\t(?:kv|k|v)[czm]alloc(?:_node|_array)? |\n\t\tkstrdup(?:_const)? |\n\t\tkmemdup(?:_nul)?) |\n\t(?:\\w+)?alloc_skb(?:_ip_align)? |\n\t\t\t\t# dev_alloc_skb/netdev_alloc_skb, et al\n\tdma_alloc_coherent\n)};\n\nour $signature_tags = qr{(?xi:\n\tSigned-off-by:|\n\tCo-developed-by:|\n\tAcked-by:|\n\tTested-by:|\n\tReviewed-by:|\n\tReported-by:|\n\tSuggested-by:|\n\tTo:|\n\tCc:\n)};\n\nour @typeListMisordered = (\n\tqr{char\\s+(?:un)?signed},\n\tqr{int\\s+(?:(?:un)?signed\\s+)?short\\s},\n\tqr{int\\s+short(?:\\s+(?:un)?signed)},\n\tqr{short\\s+int(?:\\s+(?:un)?signed)},\n\tqr{(?:un)?signed\\s+int\\s+short},\n\tqr{short\\s+(?:un)?signed},\n\tqr{long\\s+int\\s+(?:un)?signed},\n\tqr{int\\s+long\\s+(?:un)?signed},\n\tqr{long\\s+(?:un)?signed\\s+int},\n\tqr{int\\s+(?:un)?signed\\s+long},\n\tqr{int\\s+(?:un)?signed},\n\tqr{int\\s+long\\s+long\\s+(?:un)?signed},\n\tqr{long\\s+long\\s+int\\s+(?:un)?signed},\n\tqr{long\\s+long\\s+(?:un)?signed\\s+int},\n\tqr{long\\s+long\\s+(?:un)?signed},\n\tqr{long\\s+(?:un)?signed},\n);\n\nour @typeList = (\n\tqr{void},\n\tqr{(?:(?:un)?signed\\s+)?char},\n\tqr{(?:(?:un)?signed\\s+)?short\\s+int},\n\tqr{(?:(?:un)?signed\\s+)?short},\n\tqr{(?:(?:un)?signed\\s+)?int},\n\tqr{(?:(?:un)?signed\\s+)?long\\s+int},\n\tqr{(?:(?:un)?signed\\s+)?long\\s+long\\s+int},\n\tqr{(?:(?:un)?signed\\s+)?long\\s+long},\n\tqr{(?:(?:un)?signed\\s+)?long},\n\tqr{(?:un)?signed},\n\tqr{float},\n\tqr{double},\n\tqr{bool},\n\tqr{struct\\s+$Ident},\n\tqr{union\\s+$Ident},\n\tqr{enum\\s+$Ident},\n\tqr{${Ident}_t},\n\tqr{${Ident}_handler},\n\tqr{${Ident}_handler_fn},\n\t@typeListMisordered,\n);\n\nour $C90_int_types = qr{(?x:\n\tlong\\s+long\\s+int\\s+(?:un)?signed|\n\tlong\\s+long\\s+(?:un)?signed\\s+int|\n\tlong\\s+long\\s+(?:un)?signed|\n\t(?:(?:un)?signed\\s+)?long\\s+long\\s+int|\n\t(?:(?:un)?signed\\s+)?long\\s+long|\n\tint\\s+long\\s+long\\s+(?:un)?signed|\n\tint\\s+(?:(?:un)?signed\\s+)?long\\s+long|\n\n\tlong\\s+int\\s+(?:un)?signed|\n\tlong\\s+(?:un)?signed\\s+int|\n\tlong\\s+(?:un)?signed|\n\t(?:(?:un)?signed\\s+)?long\\s+int|\n\t(?:(?:un)?signed\\s+)?long|\n\tint\\s+long\\s+(?:un)?signed|\n\tint\\s+(?:(?:un)?signed\\s+)?long|\n\n\tint\\s+(?:un)?signed|\n\t(?:(?:un)?signed\\s+)?int\n)};\n\nour @typeListFile = ();\nour @typeListWithAttr = (\n\t@typeList,\n\tqr{struct\\s+$InitAttribute\\s+$Ident},\n\tqr{union\\s+$InitAttribute\\s+$Ident},\n);\n\nour @modifierList = (\n\tqr{fastcall},\n);\nour @modifierListFile = ();\n\nour @mode_permission_funcs = (\n\t[\"module_param\", 3],\n\t[\"module_param_(?:array|named|string)\", 4],\n\t[\"module_param_array_named\", 5],\n\t[\"debugfs_create_(?:file|u8|u16|u32|u64|x8|x16|x32|x64|size_t|atomic_t|bool|blob|regset32|u32_array)\", 2],\n\t[\"proc_create(?:_data|)\", 2],\n\t[\"(?:CLASS|DEVICE|SENSOR|SENSOR_DEVICE|IIO_DEVICE)_ATTR\", 2],\n\t[\"IIO_DEV_ATTR_[A-Z_]+\", 1],\n\t[\"SENSOR_(?:DEVICE_|)ATTR_2\", 2],\n\t[\"SENSOR_TEMPLATE(?:_2|)\", 3],\n\t[\"__ATTR\", 2],\n);\n\n#Create a search pattern for all these functions to speed up a loop below\nour $mode_perms_search = \"\";\nforeach my $entry (@mode_permission_funcs) {\n\t$mode_perms_search .= '|' if ($mode_perms_search ne \"\");\n\t$mode_perms_search .= $entry->[0];\n}\n$mode_perms_search = \"(?:${mode_perms_search})\";\n\nour %deprecated_apis = (\n\t\"synchronize_rcu_bh\"\t\t\t=> \"synchronize_rcu\",\n\t\"synchronize_rcu_bh_expedited\"\t\t=> \"synchronize_rcu_expedited\",\n\t\"call_rcu_bh\"\t\t\t\t=> \"call_rcu\",\n\t\"rcu_barrier_bh\"\t\t\t=> \"rcu_barrier\",\n\t\"synchronize_sched\"\t\t\t=> \"synchronize_rcu\",\n\t\"synchronize_sched_expedited\"\t\t=> \"synchronize_rcu_expedited\",\n\t\"call_rcu_sched\"\t\t\t=> \"call_rcu\",\n\t\"rcu_barrier_sched\"\t\t\t=> \"rcu_barrier\",\n\t\"get_state_synchronize_sched\"\t\t=> \"get_state_synchronize_rcu\",\n\t\"cond_synchronize_sched\"\t\t=> \"cond_synchronize_rcu\",\n);\n\n#Create a search pattern for all these strings to speed up a loop below\nour $deprecated_apis_search = \"\";\nforeach my $entry (keys %deprecated_apis) {\n\t$deprecated_apis_search .= '|' if ($deprecated_apis_search ne \"\");\n\t$deprecated_apis_search .= $entry;\n}\n$deprecated_apis_search = \"(?:${deprecated_apis_search})\";\n\nour $mode_perms_world_writable = qr{\n\tS_IWUGO\t\t|\n\tS_IWOTH\t\t|\n\tS_IRWXUGO\t|\n\tS_IALLUGO\t|\n\t0[0-7][0-7][2367]\n}x;\n\nour %mode_permission_string_types = (\n\t\"S_IRWXU\" => 0700,\n\t\"S_IRUSR\" => 0400,\n\t\"S_IWUSR\" => 0200,\n\t\"S_IXUSR\" => 0100,\n\t\"S_IRWXG\" => 0070,\n\t\"S_IRGRP\" => 0040,\n\t\"S_IWGRP\" => 0020,\n\t\"S_IXGRP\" => 0010,\n\t\"S_IRWXO\" => 0007,\n\t\"S_IROTH\" => 0004,\n\t\"S_IWOTH\" => 0002,\n\t\"S_IXOTH\" => 0001,\n\t\"S_IRWXUGO\" => 0777,\n\t\"S_IRUGO\" => 0444,\n\t\"S_IWUGO\" => 0222,\n\t\"S_IXUGO\" => 0111,\n);\n\n#Create a search pattern for all these strings to speed up a loop below\nour $mode_perms_string_search = \"\";\nforeach my $entry (keys %mode_permission_string_types) {\n\t$mode_perms_string_search .= '|' if ($mode_perms_string_search ne \"\");\n\t$mode_perms_string_search .= $entry;\n}\nour $single_mode_perms_string_search = \"(?:${mode_perms_string_search})\";\nour $multi_mode_perms_string_search = qr{\n\t${single_mode_perms_string_search}\n\t(?:\\s*\\|\\s*${single_mode_perms_string_search})*\n}x;\n\nsub perms_to_octal {\n\tmy ($string) = @_;\n\n\treturn trim($string) if ($string =~ /^\\s*0[0-7]{3,3}\\s*$/);\n\n\tmy $val = \"\";\n\tmy $oval = \"\";\n\tmy $to = 0;\n\tmy $curpos = 0;\n\tmy $lastpos = 0;\n\twhile ($string =~ /\\b(($single_mode_perms_string_search)\\b(?:\\s*\\|\\s*)?\\s*)/g) {\n\t\t$curpos = pos($string);\n\t\tmy $match = $2;\n\t\tmy $omatch = $1;\n\t\tlast if ($lastpos > 0 && ($curpos - length($omatch) != $lastpos));\n\t\t$lastpos = $curpos;\n\t\t$to |= $mode_permission_string_types{$match};\n\t\t$val .= '\\s*\\|\\s*' if ($val ne \"\");\n\t\t$val .= $match;\n\t\t$oval .= $omatch;\n\t}\n\t$oval =~ s/^\\s*\\|\\s*//;\n\t$oval =~ s/\\s*\\|\\s*$//;\n\treturn sprintf(\"%04o\", $to);\n}\n\nour $allowed_asm_includes = qr{(?x:\n\tirq|\n\tmemory|\n\ttime|\n\treboot\n)};\n# memory.h: ARM has a custom one\n\n# Load common spelling mistakes and build regular expression list.\nmy $misspellings;\nmy %spelling_fix;\n\nif (open(my $spelling, '<', $spelling_file)) {\n\twhile (<$spelling>) {\n\t\tmy $line = $_;\n\n\t\t$line =~ s/\\s*\\n?$//g;\n\t\t$line =~ s/^\\s*//g;\n\n\t\tnext if ($line =~ m/^\\s*#/);\n\t\tnext if ($line =~ m/^\\s*$/);\n\n\t\tmy ($suspect, $fix) = split(/\\|\\|/, $line);\n\n\t\t$spelling_fix{$suspect} = $fix;\n\t}\n\tclose($spelling);\n} else {\n\twarn \"No typos will be found - file '$spelling_file': $!\\n\";\n}\n\nif ($codespell) {\n\tif (open(my $spelling, '<', $codespellfile)) {\n\t\twhile (<$spelling>) {\n\t\t\tmy $line = $_;\n\n\t\t\t$line =~ s/\\s*\\n?$//g;\n\t\t\t$line =~ s/^\\s*//g;\n\n\t\t\tnext if ($line =~ m/^\\s*#/);\n\t\t\tnext if ($line =~ m/^\\s*$/);\n\t\t\tnext if ($line =~ m/, disabled/i);\n\n\t\t\t$line =~ s/,.*$//;\n\n\t\t\tmy ($suspect, $fix) = split(/->/, $line);\n\n\t\t\t$spelling_fix{$suspect} = $fix;\n\t\t}\n\t\tclose($spelling);\n\t} else {\n\t\twarn \"No codespell typos will be found - file '$codespellfile': $!\\n\";\n\t}\n}\n\n$misspellings = join(\"|\", sort keys %spelling_fix) if keys %spelling_fix;\n\nsub read_words {\n\tmy ($wordsRef, $file) = @_;\n\n\tif (open(my $words, '<', $file)) {\n\t\twhile (<$words>) {\n\t\t\tmy $line = $_;\n\n\t\t\t$line =~ s/\\s*\\n?$//g;\n\t\t\t$line =~ s/^\\s*//g;\n\n\t\t\tnext if ($line =~ m/^\\s*#/);\n\t\t\tnext if ($line =~ m/^\\s*$/);\n\t\t\tif ($line =~ /\\s/) {\n\t\t\t\tprint(\"$file: '$line' invalid - ignored\\n\");\n\t\t\t\tnext;\n\t\t\t}\n\n\t\t\t$$wordsRef .= '|' if ($$wordsRef ne \"\");\n\t\t\t$$wordsRef .= $line;\n\t\t}\n\t\tclose($file);\n\t\treturn 1;\n\t}\n\n\treturn 0;\n}\n\nmy $const_structs = \"\";\nread_words(\\$const_structs, $conststructsfile)\n    or warn \"No structs that should be const will be found - file '$conststructsfile': $!\\n\";\n\nmy $typeOtherTypedefs = \"\";\nif (length($typedefsfile)) {\n\tread_words(\\$typeOtherTypedefs, $typedefsfile)\n\t    or warn \"No additional types will be considered - file '$typedefsfile': $!\\n\";\n}\n$typeTypedefs .= '|' . $typeOtherTypedefs if ($typeOtherTypedefs ne \"\");\n\nsub build_types {\n\tmy $mods = \"(?x:  \\n\" . join(\"|\\n  \", (@modifierList, @modifierListFile)) . \"\\n)\";\n\tmy $all = \"(?x:  \\n\" . join(\"|\\n  \", (@typeList, @typeListFile)) . \"\\n)\";\n\tmy $Misordered = \"(?x:  \\n\" . join(\"|\\n  \", @typeListMisordered) . \"\\n)\";\n\tmy $allWithAttr = \"(?x:  \\n\" . join(\"|\\n  \", @typeListWithAttr) . \"\\n)\";\n\t$Modifier\t= qr{(?:$Attribute|$Sparse|$mods)};\n\t$BasicType\t= qr{\n\t\t\t\t(?:$typeTypedefs\\b)|\n\t\t\t\t(?:${all}\\b)\n\t\t}x;\n\t$NonptrType\t= qr{\n\t\t\t(?:$Modifier\\s+|const\\s+)*\n\t\t\t(?:\n\t\t\t\t(?:typeof|__typeof__)\\s*\\([^\\)]*\\)|\n\t\t\t\t(?:$typeTypedefs\\b)|\n\t\t\t\t(?:${all}\\b)\n\t\t\t)\n\t\t\t(?:\\s+$Modifier|\\s+const)*\n\t\t  }x;\n\t$NonptrTypeMisordered\t= qr{\n\t\t\t(?:$Modifier\\s+|const\\s+)*\n\t\t\t(?:\n\t\t\t\t(?:${Misordered}\\b)\n\t\t\t)\n\t\t\t(?:\\s+$Modifier|\\s+const)*\n\t\t  }x;\n\t$NonptrTypeWithAttr\t= qr{\n\t\t\t(?:$Modifier\\s+|const\\s+)*\n\t\t\t(?:\n\t\t\t\t(?:typeof|__typeof__)\\s*\\([^\\)]*\\)|\n\t\t\t\t(?:$typeTypedefs\\b)|\n\t\t\t\t(?:${allWithAttr}\\b)\n\t\t\t)\n\t\t\t(?:\\s+$Modifier|\\s+const)*\n\t\t  }x;\n\t$Type\t= qr{\n\t\t\t$NonptrType\n\t\t\t(?:(?:\\s|\\*|\\[\\])+\\s*const|(?:\\s|\\*\\s*(?:const\\s*)?|\\[\\])+|(?:\\s*\\[\\s*\\])+){0,4}\n\t\t\t(?:\\s+$Inline|\\s+$Modifier)*\n\t\t  }x;\n\t$TypeMisordered\t= qr{\n\t\t\t$NonptrTypeMisordered\n\t\t\t(?:(?:\\s|\\*|\\[\\])+\\s*const|(?:\\s|\\*\\s*(?:const\\s*)?|\\[\\])+|(?:\\s*\\[\\s*\\])+){0,4}\n\t\t\t(?:\\s+$Inline|\\s+$Modifier)*\n\t\t  }x;\n\t$Declare\t= qr{(?:$Storage\\s+(?:$Inline\\s+)?)?$Type};\n\t$DeclareMisordered\t= qr{(?:$Storage\\s+(?:$Inline\\s+)?)?$TypeMisordered};\n}\nbuild_types();\n\nour $Typecast\t= qr{\\s*(\\(\\s*$NonptrType\\s*\\)){0,1}\\s*};\n\n# Using $balanced_parens, $LvalOrFunc, or $FuncArg\n# requires at least perl version v5.10.0\n# Any use must be runtime checked with $^V\n\nour $balanced_parens = qr/(\\((?:[^\\(\\)]++|(?-1))*\\))/;\nour $LvalOrFunc\t= qr{((?:[\\&\\*]\\s*)?$Lval)\\s*($balanced_parens{0,1})\\s*};\nour $FuncArg = qr{$Typecast{0,1}($LvalOrFunc|$Constant|$String)};\n\nour $declaration_macros = qr{(?x:\n\t(?:$Storage\\s+)?(?:[A-Z_][A-Z0-9]*_){0,2}(?:DEFINE|DECLARE)(?:_[A-Z0-9]+){1,6}\\s*\\(|\n\t(?:$Storage\\s+)?[HLP]?LIST_HEAD\\s*\\(|\n\t(?:$Storage\\s+)?${Type}\\s+uninitialized_var\\s*\\(|\n\t(?:SKCIPHER_REQUEST|SHASH_DESC|AHASH_REQUEST)_ON_STACK\\s*\\(\n)};\n\nsub deparenthesize {\n\tmy ($string) = @_;\n\treturn \"\" if (!defined($string));\n\n\twhile ($string =~ /^\\s*\\(.*\\)\\s*$/) {\n\t\t$string =~ s@^\\s*\\(\\s*@@;\n\t\t$string =~ s@\\s*\\)\\s*$@@;\n\t}\n\n\t$string =~ s@\\s+@ @g;\n\n\treturn $string;\n}\n\nsub seed_camelcase_file {\n\tmy ($file) = @_;\n\n\treturn if (!(-f $file));\n\n\tlocal $/;\n\n\topen(my $include_file, '<', \"$file\")\n\t    or warn \"$P: Can't read '$file' $!\\n\";\n\tmy $text = <$include_file>;\n\tclose($include_file);\n\n\tmy @lines = split('\\n', $text);\n\n\tforeach my $line (@lines) {\n\t\tnext if ($line !~ /(?:[A-Z][a-z]|[a-z][A-Z])/);\n\t\tif ($line =~ /^[ \\t]*(?:#[ \\t]*define|typedef\\s+$Type)\\s+(\\w*(?:[A-Z][a-z]|[a-z][A-Z])\\w*)/) {\n\t\t\t$camelcase{$1} = 1;\n\t\t} elsif ($line =~ /^\\s*$Declare\\s+(\\w*(?:[A-Z][a-z]|[a-z][A-Z])\\w*)\\s*[\\(\\[,;]/) {\n\t\t\t$camelcase{$1} = 1;\n\t\t} elsif ($line =~ /^\\s*(?:union|struct|enum)\\s+(\\w*(?:[A-Z][a-z]|[a-z][A-Z])\\w*)\\s*[;\\{]/) {\n\t\t\t$camelcase{$1} = 1;\n\t\t}\n\t}\n}\n\nour %maintained_status = ();\n\nsub is_maintained_obsolete {\n\tmy ($filename) = @_;\n\n\treturn 0 if (!$tree || !(-e \"$root/scripts/get_maintainer.pl\"));\n\n\tif (!exists($maintained_status{$filename})) {\n\t\t$maintained_status{$filename} = `perl $root/scripts/get_maintainer.pl --status --nom --nol --nogit --nogit-fallback -f $filename 2>&1`;\n\t}\n\n\treturn $maintained_status{$filename} =~ /obsolete/i;\n}\n\nsub is_SPDX_License_valid {\n\tmy ($license) = @_;\n\n\treturn 1 if (!$tree || which(\"python\") eq \"\" || !(-e \"$root/scripts/spdxcheck.py\") || !(-e \"$root/.git\"));\n\n\tmy $root_path = abs_path($root);\n\tmy $status = `cd \"$root_path\"; echo \"$license\" | python scripts/spdxcheck.py -`;\n\treturn 0 if ($status ne \"\");\n\treturn 1;\n}\n\nmy $camelcase_seeded = 0;\nsub seed_camelcase_includes {\n\treturn if ($camelcase_seeded);\n\n\tmy $files;\n\tmy $camelcase_cache = \"\";\n\tmy @include_files = ();\n\n\t$camelcase_seeded = 1;\n\n\tif (-e \".git\") {\n\t\tmy $git_last_include_commit = `${git_command} log --no-merges --pretty=format:\"%h%n\" -1 -- include`;\n\t\tchomp $git_last_include_commit;\n\t\t$camelcase_cache = \".checkpatch-camelcase.git.$git_last_include_commit\";\n\t} else {\n\t\tmy $last_mod_date = 0;\n\t\t$files = `find $root/include -name \"*.h\"`;\n\t\t@include_files = split('\\n', $files);\n\t\tforeach my $file (@include_files) {\n\t\t\tmy $date = POSIX::strftime(\"%Y%m%d%H%M\",\n\t\t\t\t\t\t   localtime((stat $file)[9]));\n\t\t\t$last_mod_date = $date if ($last_mod_date < $date);\n\t\t}\n\t\t$camelcase_cache = \".checkpatch-camelcase.date.$last_mod_date\";\n\t}\n\n\tif ($camelcase_cache ne \"\" && -f $camelcase_cache) {\n\t\topen(my $camelcase_file, '<', \"$camelcase_cache\")\n\t\t    or warn \"$P: Can't read '$camelcase_cache' $!\\n\";\n\t\twhile (<$camelcase_file>) {\n\t\t\tchomp;\n\t\t\t$camelcase{$_} = 1;\n\t\t}\n\t\tclose($camelcase_file);\n\n\t\treturn;\n\t}\n\n\tif (-e \".git\") {\n\t\t$files = `${git_command} ls-files \"include/*.h\"`;\n\t\t@include_files = split('\\n', $files);\n\t}\n\n\tforeach my $file (@include_files) {\n\t\tseed_camelcase_file($file);\n\t}\n\n\tif ($camelcase_cache ne \"\") {\n\t\tunlink glob \".checkpatch-camelcase.*\";\n\t\topen(my $camelcase_file, '>', \"$camelcase_cache\")\n\t\t    or warn \"$P: Can't write '$camelcase_cache' $!\\n\";\n\t\tforeach (sort { lc($a) cmp lc($b) } keys(%camelcase)) {\n\t\t\tprint $camelcase_file (\"$_\\n\");\n\t\t}\n\t\tclose($camelcase_file);\n\t}\n}\n\nsub git_commit_info {\n\tmy ($commit, $id, $desc) = @_;\n\n\treturn ($id, $desc) if ((which(\"git\") eq \"\") || !(-e \".git\"));\n\n\tmy $output = `${git_command} log --no-color --format='%H %s' -1 $commit 2>&1`;\n\t$output =~ s/^\\s*//gm;\n\tmy @lines = split(\"\\n\", $output);\n\n\treturn ($id, $desc) if ($#lines < 0);\n\n\tif ($lines[0] =~ /^error: short SHA1 $commit is ambiguous/) {\n# Maybe one day convert this block of bash into something that returns\n# all matching commit ids, but it's very slow...\n#\n#\t\techo \"checking commits $1...\"\n#\t\tgit rev-list --remotes | grep -i \"^$1\" |\n#\t\twhile read line ; do\n#\t\t    git log --format='%H %s' -1 $line |\n#\t\t    echo \"commit $(cut -c 1-12,41-)\"\n#\t\tdone\n\t} elsif ($lines[0] =~ /^fatal: ambiguous argument '$commit': unknown revision or path not in the working tree\\./) {\n\t\t$id = undef;\n\t} else {\n\t\t$id = substr($lines[0], 0, 12);\n\t\t$desc = substr($lines[0], 41);\n\t}\n\n\treturn ($id, $desc);\n}\n\n$chk_signoff = 0 if ($file);\n\nmy @rawlines = ();\nmy @lines = ();\nmy @fixed = ();\nmy @fixed_inserted = ();\nmy @fixed_deleted = ();\nmy $fixlinenr = -1;\n\n# If input is git commits, extract all commits from the commit expressions.\n# For example, HEAD-3 means we need check 'HEAD, HEAD~1, HEAD~2'.\ndie \"$P: No git repository found\\n\" if ($git && !-e \".git\");\n\nif ($git) {\n\tmy @commits = ();\n\tforeach my $commit_expr (@ARGV) {\n\t\tmy $git_range;\n\t\tif ($commit_expr =~ m/^(.*)-(\\d+)$/) {\n\t\t\t$git_range = \"-$2 $1\";\n\t\t} elsif ($commit_expr =~ m/\\.\\./) {\n\t\t\t$git_range = \"$commit_expr\";\n\t\t} else {\n\t\t\t$git_range = \"-1 $commit_expr\";\n\t\t}\n\t\tmy $lines = `${git_command} log --no-color --no-merges --pretty=format:'%H %s' $git_range`;\n\t\tforeach my $line (split(/\\n/, $lines)) {\n\t\t\t$line =~ /^([0-9a-fA-F]{40,40}) (.*)$/;\n\t\t\tnext if (!defined($1) || !defined($2));\n\t\t\tmy $sha1 = $1;\n\t\t\tmy $subject = $2;\n\t\t\tunshift(@commits, $sha1);\n\t\t\t$git_commits{$sha1} = $subject;\n\t\t}\n\t}\n\tdie \"$P: no git commits after extraction!\\n\" if (@commits == 0);\n\t@ARGV = @commits;\n}\n\nmy $vname;\n$allow_c99_comments = !defined $ignore_type{\"C99_COMMENT_TOLERANCE\"};\nfor my $filename (@ARGV) {\n\tmy $FILE;\n\tif ($git) {\n\t\topen($FILE, '-|', \"git format-patch -M --stdout -1 $filename\") ||\n\t\t\tdie \"$P: $filename: git format-patch failed - $!\\n\";\n\t} elsif ($file) {\n\t\topen($FILE, '-|', \"diff -u /dev/null $filename\") ||\n\t\t\tdie \"$P: $filename: diff failed - $!\\n\";\n\t} elsif ($filename eq '-') {\n\t\topen($FILE, '<&STDIN');\n\t} else {\n\t\topen($FILE, '<', \"$filename\") ||\n\t\t\tdie \"$P: $filename: open failed - $!\\n\";\n\t}\n\tif ($filename eq '-') {\n\t\t$vname = 'Your patch';\n\t} elsif ($git) {\n\t\t$vname = \"Commit \" . substr($filename, 0, 12) . ' (\"' . $git_commits{$filename} . '\")';\n\t} else {\n\t\t$vname = $filename;\n\t}\n\twhile (<$FILE>) {\n\t\tchomp;\n\t\tpush(@rawlines, $_);\n\t\t$vname = qq(\"$1\") if ($filename eq '-' && $_ =~ m/^Subject:\\s+(.+)/i);\n\t}\n\tclose($FILE);\n\n\tif ($#ARGV > 0 && $quiet == 0) {\n\t\tprint '-' x length($vname) . \"\\n\";\n\t\tprint \"$vname\\n\";\n\t\tprint '-' x length($vname) . \"\\n\";\n\t}\n\n\tif (!process($filename)) {\n\t\t$exit = 1;\n\t}\n\t@rawlines = ();\n\t@lines = ();\n\t@fixed = ();\n\t@fixed_inserted = ();\n\t@fixed_deleted = ();\n\t$fixlinenr = -1;\n\t@modifierListFile = ();\n\t@typeListFile = ();\n\tbuild_types();\n}\n\nif (!$quiet) {\n\thash_show_words(\\%use_type, \"Used\");\n\thash_show_words(\\%ignore_type, \"Ignored\");\n\n\tif (!$perl_version_ok) {\n\t\tprint << \"EOM\"\n\nNOTE: perl $^V is not modern enough to detect all possible issues.\n      An upgrade to at least perl $minimum_perl_version is suggested.\nEOM\n\t}\n\tif ($exit) {\n\t\tprint << \"EOM\"\n\nNOTE: If any of the errors are false positives, please report\n      them to the maintainer, see CHECKPATCH in MAINTAINERS.\nEOM\n\t}\n}\n\nexit($exit);\n\nsub top_of_openwrt_tree {\n\tmy ($root) = @_;\n\n\tmy @tree_check = (\n\t\t\"BSDmakefile\", \"Config.in\", \"LICENSES\", \"Makefile\", \"README.md\",\n\t\t\"feeds.conf.default\", \"include\", \"package\", \"rules.mk\",\n\t\t\"scripts\", \"target\", \"toolchain\", \"tools\"\n\t);\n\n\tforeach my $check (@tree_check) {\n\t\tif (! -e $root . '/' . $check) {\n\t\t\treturn 0;\n\t\t}\n\t}\n\treturn 1;\n}\n\nsub parse_email {\n\tmy ($formatted_email) = @_;\n\n\tmy $name = \"\";\n\tmy $name_comment = \"\";\n\tmy $address = \"\";\n\tmy $comment = \"\";\n\n\tif ($formatted_email =~ /^(.*)<(\\S+\\@\\S+)>(.*)$/) {\n\t\t$name = $1;\n\t\t$address = $2;\n\t\t$comment = $3 if defined $3;\n\t} elsif ($formatted_email =~ /^\\s*<(\\S+\\@\\S+)>(.*)$/) {\n\t\t$address = $1;\n\t\t$comment = $2 if defined $2;\n\t} elsif ($formatted_email =~ /(\\S+\\@\\S+)(.*)$/) {\n\t\t$address = $1;\n\t\t$comment = $2 if defined $2;\n\t\t$formatted_email =~ s/\\Q$address\\E.*$//;\n\t\t$name = $formatted_email;\n\t\t$name = trim($name);\n\t\t$name =~ s/^\\\"|\\\"$//g;\n\t\t# If there's a name left after stripping spaces and\n\t\t# leading quotes, and the address doesn't have both\n\t\t# leading and trailing angle brackets, the address\n\t\t# is invalid. ie:\n\t\t#   \"joe smith joe@smith.com\" bad\n\t\t#   \"joe smith <joe@smith.com\" bad\n\t\tif ($name ne \"\" && $address !~ /^<[^>]+>$/) {\n\t\t\t$name = \"\";\n\t\t\t$address = \"\";\n\t\t\t$comment = \"\";\n\t\t}\n\t}\n\n\t$name = trim($name);\n\t$name =~ s/^\\\"|\\\"$//g;\n\t$name =~ s/(\\s*\\([^\\)]+\\))\\s*//;\n\tif (defined($1)) {\n\t\t$name_comment = trim($1);\n\t}\n\t$address = trim($address);\n\t$address =~ s/^\\<|\\>$//g;\n\n\tif ($name =~ /[^\\w \\-]/i) { ##has \"must quote\" chars\n\t\t$name =~ s/(?<!\\\\)\"/\\\\\"/g; ##escape quotes\n\t\t$name = \"\\\"$name\\\"\";\n\t}\n\n\treturn ($name, $name_comment, $address, $comment);\n}\n\nsub format_email {\n\tmy ($name, $address) = @_;\n\n\tmy $formatted_email;\n\n\t$name = trim($name);\n\t$name =~ s/^\\\"|\\\"$//g;\n\t$address = trim($address);\n\n\tif ($name =~ /[^\\w \\-]/i) { ##has \"must quote\" chars\n\t\t$name =~ s/(?<!\\\\)\"/\\\\\"/g; ##escape quotes\n\t\t$name = \"\\\"$name\\\"\";\n\t}\n\n\tif (\"$name\" eq \"\") {\n\t\t$formatted_email = \"$address\";\n\t} else {\n\t\t$formatted_email = \"$name <$address>\";\n\t}\n\n\treturn $formatted_email;\n}\n\nsub reformat_email {\n\tmy ($email) = @_;\n\n\tmy ($email_name, $name_comment, $email_address, $comment) = parse_email($email);\n\treturn format_email($email_name, $email_address);\n}\n\nsub same_email_addresses {\n\tmy ($email1, $email2) = @_;\n\n\tmy ($email1_name, $name1_comment, $email1_address, $comment1) = parse_email($email1);\n\tmy ($email2_name, $name2_comment, $email2_address, $comment2) = parse_email($email2);\n\n\treturn $email1_name eq $email2_name &&\n\t       $email1_address eq $email2_address;\n}\n\nsub which {\n\tmy ($bin) = @_;\n\n\tforeach my $path (split(/:/, $ENV{PATH})) {\n\t\tif (-e \"$path/$bin\") {\n\t\t\treturn \"$path/$bin\";\n\t\t}\n\t}\n\n\treturn \"\";\n}\n\nsub which_conf {\n\tmy ($conf) = @_;\n\n\tforeach my $path (split(/:/, \".:$ENV{HOME}:.scripts\")) {\n\t\tif (-e \"$path/$conf\") {\n\t\t\treturn \"$path/$conf\";\n\t\t}\n\t}\n\n\treturn \"\";\n}\n\nsub expand_tabs {\n\tmy ($str) = @_;\n\n\tmy $res = '';\n\tmy $n = 0;\n\tfor my $c (split(//, $str)) {\n\t\tif ($c eq \"\\t\") {\n\t\t\t$res .= ' ';\n\t\t\t$n++;\n\t\t\tfor (; ($n % $tabsize) != 0; $n++) {\n\t\t\t\t$res .= ' ';\n\t\t\t}\n\t\t\tnext;\n\t\t}\n\t\t$res .= $c;\n\t\t$n++;\n\t}\n\n\treturn $res;\n}\nsub copy_spacing {\n\t(my $res = shift) =~ tr/\\t/ /c;\n\treturn $res;\n}\n\nsub line_stats {\n\tmy ($line) = @_;\n\n\t# Drop the diff line leader and expand tabs\n\t$line =~ s/^.//;\n\t$line = expand_tabs($line);\n\n\t# Pick the indent from the front of the line.\n\tmy ($white) = ($line =~ /^(\\s*)/);\n\n\treturn (length($line), length($white));\n}\n\nmy $sanitise_quote = '';\n\nsub sanitise_line_reset {\n\tmy ($in_comment) = @_;\n\n\tif ($in_comment) {\n\t\t$sanitise_quote = '*/';\n\t} else {\n\t\t$sanitise_quote = '';\n\t}\n}\nsub sanitise_line {\n\tmy ($line) = @_;\n\n\tmy $res = '';\n\tmy $l = '';\n\n\tmy $qlen = 0;\n\tmy $off = 0;\n\tmy $c;\n\n\t# Always copy over the diff marker.\n\t$res = substr($line, 0, 1);\n\n\tfor ($off = 1; $off < length($line); $off++) {\n\t\t$c = substr($line, $off, 1);\n\n\t\t# Comments we are whacking completely including the begin\n\t\t# and end, all to $;.\n\t\tif ($sanitise_quote eq '' && substr($line, $off, 2) eq '/*') {\n\t\t\t$sanitise_quote = '*/';\n\n\t\t\tsubstr($res, $off, 2, \"$;$;\");\n\t\t\t$off++;\n\t\t\tnext;\n\t\t}\n\t\tif ($sanitise_quote eq '*/' && substr($line, $off, 2) eq '*/') {\n\t\t\t$sanitise_quote = '';\n\t\t\tsubstr($res, $off, 2, \"$;$;\");\n\t\t\t$off++;\n\t\t\tnext;\n\t\t}\n\t\tif ($sanitise_quote eq '' && substr($line, $off, 2) eq '//') {\n\t\t\t$sanitise_quote = '//';\n\n\t\t\tsubstr($res, $off, 2, $sanitise_quote);\n\t\t\t$off++;\n\t\t\tnext;\n\t\t}\n\n\t\t# A \\ in a string means ignore the next character.\n\t\tif (($sanitise_quote eq \"'\" || $sanitise_quote eq '\"') &&\n\t\t    $c eq \"\\\\\") {\n\t\t\tsubstr($res, $off, 2, 'XX');\n\t\t\t$off++;\n\t\t\tnext;\n\t\t}\n\t\t# Regular quotes.\n\t\tif ($c eq \"'\" || $c eq '\"') {\n\t\t\tif ($sanitise_quote eq '') {\n\t\t\t\t$sanitise_quote = $c;\n\n\t\t\t\tsubstr($res, $off, 1, $c);\n\t\t\t\tnext;\n\t\t\t} elsif ($sanitise_quote eq $c) {\n\t\t\t\t$sanitise_quote = '';\n\t\t\t}\n\t\t}\n\n\t\t#print \"c<$c> SQ<$sanitise_quote>\\n\";\n\t\tif ($off != 0 && $sanitise_quote eq '*/' && $c ne \"\\t\") {\n\t\t\tsubstr($res, $off, 1, $;);\n\t\t} elsif ($off != 0 && $sanitise_quote eq '//' && $c ne \"\\t\") {\n\t\t\tsubstr($res, $off, 1, $;);\n\t\t} elsif ($off != 0 && $sanitise_quote && $c ne \"\\t\") {\n\t\t\tsubstr($res, $off, 1, 'X');\n\t\t} else {\n\t\t\tsubstr($res, $off, 1, $c);\n\t\t}\n\t}\n\n\tif ($sanitise_quote eq '//') {\n\t\t$sanitise_quote = '';\n\t}\n\n\t# The pathname on a #include may be surrounded by '<' and '>'.\n\tif ($res =~ /^.\\s*\\#\\s*include\\s+\\<(.*)\\>/) {\n\t\tmy $clean = 'X' x length($1);\n\t\t$res =~ s@\\<.*\\>@<$clean>@;\n\n\t# The whole of a #error is a string.\n\t} elsif ($res =~ /^.\\s*\\#\\s*(?:error|warning)\\s+(.*)\\b/) {\n\t\tmy $clean = 'X' x length($1);\n\t\t$res =~ s@(\\#\\s*(?:error|warning)\\s+).*@$1$clean@;\n\t}\n\n\tif ($allow_c99_comments && $res =~ m@(//.*$)@) {\n\t\tmy $match = $1;\n\t\t$res =~ s/\\Q$match\\E/\"$;\" x length($match)/e;\n\t}\n\n\treturn $res;\n}\n\nsub get_quoted_string {\n\tmy ($line, $rawline) = @_;\n\n\treturn \"\" if (!defined($line) || !defined($rawline));\n\treturn \"\" if ($line !~ m/($String)/g);\n\treturn substr($rawline, $-[0], $+[0] - $-[0]);\n}\n\nsub ctx_statement_block {\n\tmy ($linenr, $remain, $off) = @_;\n\tmy $line = $linenr - 1;\n\tmy $blk = '';\n\tmy $soff = $off;\n\tmy $coff = $off - 1;\n\tmy $coff_set = 0;\n\n\tmy $loff = 0;\n\n\tmy $type = '';\n\tmy $level = 0;\n\tmy @stack = ();\n\tmy $p;\n\tmy $c;\n\tmy $len = 0;\n\n\tmy $remainder;\n\twhile (1) {\n\t\t@stack = (['', 0]) if ($#stack == -1);\n\n\t\t#warn \"CSB: blk<$blk> remain<$remain>\\n\";\n\t\t# If we are about to drop off the end, pull in more\n\t\t# context.\n\t\tif ($off >= $len) {\n\t\t\tfor (; $remain > 0; $line++) {\n\t\t\t\tlast if (!defined $lines[$line]);\n\t\t\t\tnext if ($lines[$line] =~ /^-/);\n\t\t\t\t$remain--;\n\t\t\t\t$loff = $len;\n\t\t\t\t$blk .= $lines[$line] . \"\\n\";\n\t\t\t\t$len = length($blk);\n\t\t\t\t$line++;\n\t\t\t\tlast;\n\t\t\t}\n\t\t\t# Bail if there is no further context.\n\t\t\t#warn \"CSB: blk<$blk> off<$off> len<$len>\\n\";\n\t\t\tif ($off >= $len) {\n\t\t\t\tlast;\n\t\t\t}\n\t\t\tif ($level == 0 && substr($blk, $off) =~ /^.\\s*#\\s*define/) {\n\t\t\t\t$level++;\n\t\t\t\t$type = '#';\n\t\t\t}\n\t\t}\n\t\t$p = $c;\n\t\t$c = substr($blk, $off, 1);\n\t\t$remainder = substr($blk, $off);\n\n\t\t#warn \"CSB: c<$c> type<$type> level<$level> remainder<$remainder> coff_set<$coff_set>\\n\";\n\n\t\t# Handle nested #if/#else.\n\t\tif ($remainder =~ /^#\\s*(?:ifndef|ifdef|if)\\s/) {\n\t\t\tpush(@stack, [ $type, $level ]);\n\t\t} elsif ($remainder =~ /^#\\s*(?:else|elif)\\b/) {\n\t\t\t($type, $level) = @{$stack[$#stack - 1]};\n\t\t} elsif ($remainder =~ /^#\\s*endif\\b/) {\n\t\t\t($type, $level) = @{pop(@stack)};\n\t\t}\n\n\t\t# Statement ends at the ';' or a close '}' at the\n\t\t# outermost level.\n\t\tif ($level == 0 && $c eq ';') {\n\t\t\tlast;\n\t\t}\n\n\t\t# An else is really a conditional as long as its not else if\n\t\tif ($level == 0 && $coff_set == 0 &&\n\t\t\t\t(!defined($p) || $p =~ /(?:\\s|\\}|\\+)/) &&\n\t\t\t\t$remainder =~ /^(else)(?:\\s|{)/ &&\n\t\t\t\t$remainder !~ /^else\\s+if\\b/) {\n\t\t\t$coff = $off + length($1) - 1;\n\t\t\t$coff_set = 1;\n\t\t\t#warn \"CSB: mark coff<$coff> soff<$soff> 1<$1>\\n\";\n\t\t\t#warn \"[\" . substr($blk, $soff, $coff - $soff + 1) . \"]\\n\";\n\t\t}\n\n\t\tif (($type eq '' || $type eq '(') && $c eq '(') {\n\t\t\t$level++;\n\t\t\t$type = '(';\n\t\t}\n\t\tif ($type eq '(' && $c eq ')') {\n\t\t\t$level--;\n\t\t\t$type = ($level != 0)? '(' : '';\n\n\t\t\tif ($level == 0 && $coff < $soff) {\n\t\t\t\t$coff = $off;\n\t\t\t\t$coff_set = 1;\n\t\t\t\t#warn \"CSB: mark coff<$coff>\\n\";\n\t\t\t}\n\t\t}\n\t\tif (($type eq '' || $type eq '{') && $c eq '{') {\n\t\t\t$level++;\n\t\t\t$type = '{';\n\t\t}\n\t\tif ($type eq '{' && $c eq '}') {\n\t\t\t$level--;\n\t\t\t$type = ($level != 0)? '{' : '';\n\n\t\t\tif ($level == 0) {\n\t\t\t\tif (substr($blk, $off + 1, 1) eq ';') {\n\t\t\t\t\t$off++;\n\t\t\t\t}\n\t\t\t\tlast;\n\t\t\t}\n\t\t}\n\t\t# Preprocessor commands end at the newline unless escaped.\n\t\tif ($type eq '#' && $c eq \"\\n\" && $p ne \"\\\\\") {\n\t\t\t$level--;\n\t\t\t$type = '';\n\t\t\t$off++;\n\t\t\tlast;\n\t\t}\n\t\t$off++;\n\t}\n\t# We are truly at the end, so shuffle to the next line.\n\tif ($off == $len) {\n\t\t$loff = $len + 1;\n\t\t$line++;\n\t\t$remain--;\n\t}\n\n\tmy $statement = substr($blk, $soff, $off - $soff + 1);\n\tmy $condition = substr($blk, $soff, $coff - $soff + 1);\n\n\t#warn \"STATEMENT<$statement>\\n\";\n\t#warn \"CONDITION<$condition>\\n\";\n\n\t#print \"coff<$coff> soff<$off> loff<$loff>\\n\";\n\n\treturn ($statement, $condition,\n\t\t\t$line, $remain + 1, $off - $loff + 1, $level);\n}\n\nsub statement_lines {\n\tmy ($stmt) = @_;\n\n\t# Strip the diff line prefixes and rip blank lines at start and end.\n\t$stmt =~ s/(^|\\n)./$1/g;\n\t$stmt =~ s/^\\s*//;\n\t$stmt =~ s/\\s*$//;\n\n\tmy @stmt_lines = ($stmt =~ /\\n/g);\n\n\treturn $#stmt_lines + 2;\n}\n\nsub statement_rawlines {\n\tmy ($stmt) = @_;\n\n\tmy @stmt_lines = ($stmt =~ /\\n/g);\n\n\treturn $#stmt_lines + 2;\n}\n\nsub statement_block_size {\n\tmy ($stmt) = @_;\n\n\t$stmt =~ s/(^|\\n)./$1/g;\n\t$stmt =~ s/^\\s*{//;\n\t$stmt =~ s/}\\s*$//;\n\t$stmt =~ s/^\\s*//;\n\t$stmt =~ s/\\s*$//;\n\n\tmy @stmt_lines = ($stmt =~ /\\n/g);\n\tmy @stmt_statements = ($stmt =~ /;/g);\n\n\tmy $stmt_lines = $#stmt_lines + 2;\n\tmy $stmt_statements = $#stmt_statements + 1;\n\n\tif ($stmt_lines > $stmt_statements) {\n\t\treturn $stmt_lines;\n\t} else {\n\t\treturn $stmt_statements;\n\t}\n}\n\nsub ctx_statement_full {\n\tmy ($linenr, $remain, $off) = @_;\n\tmy ($statement, $condition, $level);\n\n\tmy (@chunks);\n\n\t# Grab the first conditional/block pair.\n\t($statement, $condition, $linenr, $remain, $off, $level) =\n\t\t\t\tctx_statement_block($linenr, $remain, $off);\n\t#print \"F: c<$condition> s<$statement> remain<$remain>\\n\";\n\tpush(@chunks, [ $condition, $statement ]);\n\tif (!($remain > 0 && $condition =~ /^\\s*(?:\\n[+-])?\\s*(?:if|else|do)\\b/s)) {\n\t\treturn ($level, $linenr, @chunks);\n\t}\n\n\t# Pull in the following conditional/block pairs and see if they\n\t# could continue the statement.\n\tfor (;;) {\n\t\t($statement, $condition, $linenr, $remain, $off, $level) =\n\t\t\t\tctx_statement_block($linenr, $remain, $off);\n\t\t#print \"C: c<$condition> s<$statement> remain<$remain>\\n\";\n\t\tlast if (!($remain > 0 && $condition =~ /^(?:\\s*\\n[+-])*\\s*(?:else|do)\\b/s));\n\t\t#print \"C: push\\n\";\n\t\tpush(@chunks, [ $condition, $statement ]);\n\t}\n\n\treturn ($level, $linenr, @chunks);\n}\n\nsub ctx_block_get {\n\tmy ($linenr, $remain, $outer, $open, $close, $off) = @_;\n\tmy $line;\n\tmy $start = $linenr - 1;\n\tmy $blk = '';\n\tmy @o;\n\tmy @c;\n\tmy @res = ();\n\n\tmy $level = 0;\n\tmy @stack = ($level);\n\tfor ($line = $start; $remain > 0; $line++) {\n\t\tnext if ($rawlines[$line] =~ /^-/);\n\t\t$remain--;\n\n\t\t$blk .= $rawlines[$line];\n\n\t\t# Handle nested #if/#else.\n\t\tif ($lines[$line] =~ /^.\\s*#\\s*(?:ifndef|ifdef|if)\\s/) {\n\t\t\tpush(@stack, $level);\n\t\t} elsif ($lines[$line] =~ /^.\\s*#\\s*(?:else|elif)\\b/) {\n\t\t\t$level = $stack[$#stack - 1];\n\t\t} elsif ($lines[$line] =~ /^.\\s*#\\s*endif\\b/) {\n\t\t\t$level = pop(@stack);\n\t\t}\n\n\t\tforeach my $c (split(//, $lines[$line])) {\n\t\t\t##print \"C<$c>L<$level><$open$close>O<$off>\\n\";\n\t\t\tif ($off > 0) {\n\t\t\t\t$off--;\n\t\t\t\tnext;\n\t\t\t}\n\n\t\t\tif ($c eq $close && $level > 0) {\n\t\t\t\t$level--;\n\t\t\t\tlast if ($level == 0);\n\t\t\t} elsif ($c eq $open) {\n\t\t\t\t$level++;\n\t\t\t}\n\t\t}\n\n\t\tif (!$outer || $level <= 1) {\n\t\t\tpush(@res, $rawlines[$line]);\n\t\t}\n\n\t\tlast if ($level == 0);\n\t}\n\n\treturn ($level, @res);\n}\nsub ctx_block_outer {\n\tmy ($linenr, $remain) = @_;\n\n\tmy ($level, @r) = ctx_block_get($linenr, $remain, 1, '{', '}', 0);\n\treturn @r;\n}\nsub ctx_block {\n\tmy ($linenr, $remain) = @_;\n\n\tmy ($level, @r) = ctx_block_get($linenr, $remain, 0, '{', '}', 0);\n\treturn @r;\n}\nsub ctx_statement {\n\tmy ($linenr, $remain, $off) = @_;\n\n\tmy ($level, @r) = ctx_block_get($linenr, $remain, 0, '(', ')', $off);\n\treturn @r;\n}\nsub ctx_block_level {\n\tmy ($linenr, $remain) = @_;\n\n\treturn ctx_block_get($linenr, $remain, 0, '{', '}', 0);\n}\nsub ctx_statement_level {\n\tmy ($linenr, $remain, $off) = @_;\n\n\treturn ctx_block_get($linenr, $remain, 0, '(', ')', $off);\n}\n\nsub ctx_locate_comment {\n\tmy ($first_line, $end_line) = @_;\n\n\t# If c99 comment on the current line, or the line before or after\n\tmy ($current_comment) = ($rawlines[$end_line - 1] =~ m@^\\+.*(//.*$)@);\n\treturn $current_comment if (defined $current_comment);\n\t($current_comment) = ($rawlines[$end_line - 2] =~ m@^[\\+ ].*(//.*$)@);\n\treturn $current_comment if (defined $current_comment);\n\t($current_comment) = ($rawlines[$end_line] =~ m@^[\\+ ].*(//.*$)@);\n\treturn $current_comment if (defined $current_comment);\n\n\t# Catch a comment on the end of the line itself.\n\t($current_comment) = ($rawlines[$end_line - 1] =~ m@.*(/\\*.*\\*/)\\s*(?:\\\\\\s*)?$@);\n\treturn $current_comment if (defined $current_comment);\n\n\t# Look through the context and try and figure out if there is a\n\t# comment.\n\tmy $in_comment = 0;\n\t$current_comment = '';\n\tfor (my $linenr = $first_line; $linenr < $end_line; $linenr++) {\n\t\tmy $line = $rawlines[$linenr - 1];\n\t\t#warn \"           $line\\n\";\n\t\tif ($linenr == $first_line and $line =~ m@^.\\s*\\*@) {\n\t\t\t$in_comment = 1;\n\t\t}\n\t\tif ($line =~ m@/\\*@) {\n\t\t\t$in_comment = 1;\n\t\t}\n\t\tif (!$in_comment && $current_comment ne '') {\n\t\t\t$current_comment = '';\n\t\t}\n\t\t$current_comment .= $line . \"\\n\" if ($in_comment);\n\t\tif ($line =~ m@\\*/@) {\n\t\t\t$in_comment = 0;\n\t\t}\n\t}\n\n\tchomp($current_comment);\n\treturn($current_comment);\n}\nsub ctx_has_comment {\n\tmy ($first_line, $end_line) = @_;\n\tmy $cmt = ctx_locate_comment($first_line, $end_line);\n\n\t##print \"LINE: $rawlines[$end_line - 1 ]\\n\";\n\t##print \"CMMT: $cmt\\n\";\n\n\treturn ($cmt ne '');\n}\n\nsub raw_line {\n\tmy ($linenr, $cnt) = @_;\n\n\tmy $offset = $linenr - 1;\n\t$cnt++;\n\n\tmy $line;\n\twhile ($cnt) {\n\t\t$line = $rawlines[$offset++];\n\t\tnext if (defined($line) && $line =~ /^-/);\n\t\t$cnt--;\n\t}\n\n\treturn $line;\n}\n\nsub get_stat_real {\n\tmy ($linenr, $lc) = @_;\n\n\tmy $stat_real = raw_line($linenr, 0);\n\tfor (my $count = $linenr + 1; $count <= $lc; $count++) {\n\t\t$stat_real = $stat_real . \"\\n\" . raw_line($count, 0);\n\t}\n\n\treturn $stat_real;\n}\n\nsub get_stat_here {\n\tmy ($linenr, $cnt, $here) = @_;\n\n\tmy $herectx = $here . \"\\n\";\n\tfor (my $n = 0; $n < $cnt; $n++) {\n\t\t$herectx .= raw_line($linenr, $n) . \"\\n\";\n\t}\n\n\treturn $herectx;\n}\n\nsub cat_vet {\n\tmy ($vet) = @_;\n\tmy ($res, $coded);\n\n\t$res = '';\n\twhile ($vet =~ /([^[:cntrl:]]*)([[:cntrl:]]|$)/g) {\n\t\t$res .= $1;\n\t\tif ($2 ne '') {\n\t\t\t$coded = sprintf(\"^%c\", unpack('C', $2) + 64);\n\t\t\t$res .= $coded;\n\t\t}\n\t}\n\t$res =~ s/$/\\$/;\n\n\treturn $res;\n}\n\nmy $av_preprocessor = 0;\nmy $av_pending;\nmy @av_paren_type;\nmy $av_pend_colon;\n\nsub annotate_reset {\n\t$av_preprocessor = 0;\n\t$av_pending = '_';\n\t@av_paren_type = ('E');\n\t$av_pend_colon = 'O';\n}\n\nsub annotate_values {\n\tmy ($stream, $type) = @_;\n\n\tmy $res;\n\tmy $var = '_' x length($stream);\n\tmy $cur = $stream;\n\n\tprint \"$stream\\n\" if ($dbg_values > 1);\n\n\twhile (length($cur)) {\n\t\t@av_paren_type = ('E') if ($#av_paren_type < 0);\n\t\tprint \" <\" . join('', @av_paren_type) .\n\t\t\t\t\"> <$type> <$av_pending>\" if ($dbg_values > 1);\n\t\tif ($cur =~ /^(\\s+)/o) {\n\t\t\tprint \"WS($1)\\n\" if ($dbg_values > 1);\n\t\t\tif ($1 =~ /\\n/ && $av_preprocessor) {\n\t\t\t\t$type = pop(@av_paren_type);\n\t\t\t\t$av_preprocessor = 0;\n\t\t\t}\n\n\t\t} elsif ($cur =~ /^(\\(\\s*$Type\\s*)\\)/ && $av_pending eq '_') {\n\t\t\tprint \"CAST($1)\\n\" if ($dbg_values > 1);\n\t\t\tpush(@av_paren_type, $type);\n\t\t\t$type = 'c';\n\n\t\t} elsif ($cur =~ /^($Type)\\s*(?:$Ident|,|\\)|\\(|\\s*$)/) {\n\t\t\tprint \"DECLARE($1)\\n\" if ($dbg_values > 1);\n\t\t\t$type = 'T';\n\n\t\t} elsif ($cur =~ /^($Modifier)\\s*/) {\n\t\t\tprint \"MODIFIER($1)\\n\" if ($dbg_values > 1);\n\t\t\t$type = 'T';\n\n\t\t} elsif ($cur =~ /^(\\#\\s*define\\s*$Ident)(\\(?)/o) {\n\t\t\tprint \"DEFINE($1,$2)\\n\" if ($dbg_values > 1);\n\t\t\t$av_preprocessor = 1;\n\t\t\tpush(@av_paren_type, $type);\n\t\t\tif ($2 ne '') {\n\t\t\t\t$av_pending = 'N';\n\t\t\t}\n\t\t\t$type = 'E';\n\n\t\t} elsif ($cur =~ /^(\\#\\s*(?:undef\\s*$Ident|include\\b))/o) {\n\t\t\tprint \"UNDEF($1)\\n\" if ($dbg_values > 1);\n\t\t\t$av_preprocessor = 1;\n\t\t\tpush(@av_paren_type, $type);\n\n\t\t} elsif ($cur =~ /^(\\#\\s*(?:ifdef|ifndef|if))/o) {\n\t\t\tprint \"PRE_START($1)\\n\" if ($dbg_values > 1);\n\t\t\t$av_preprocessor = 1;\n\n\t\t\tpush(@av_paren_type, $type);\n\t\t\tpush(@av_paren_type, $type);\n\t\t\t$type = 'E';\n\n\t\t} elsif ($cur =~ /^(\\#\\s*(?:else|elif))/o) {\n\t\t\tprint \"PRE_RESTART($1)\\n\" if ($dbg_values > 1);\n\t\t\t$av_preprocessor = 1;\n\n\t\t\tpush(@av_paren_type, $av_paren_type[$#av_paren_type]);\n\n\t\t\t$type = 'E';\n\n\t\t} elsif ($cur =~ /^(\\#\\s*(?:endif))/o) {\n\t\t\tprint \"PRE_END($1)\\n\" if ($dbg_values > 1);\n\n\t\t\t$av_preprocessor = 1;\n\n\t\t\t# Assume all arms of the conditional end as this\n\t\t\t# one does, and continue as if the #endif was not here.\n\t\t\tpop(@av_paren_type);\n\t\t\tpush(@av_paren_type, $type);\n\t\t\t$type = 'E';\n\n\t\t} elsif ($cur =~ /^(\\\\\\n)/o) {\n\t\t\tprint \"PRECONT($1)\\n\" if ($dbg_values > 1);\n\n\t\t} elsif ($cur =~ /^(__attribute__)\\s*\\(?/o) {\n\t\t\tprint \"ATTR($1)\\n\" if ($dbg_values > 1);\n\t\t\t$av_pending = $type;\n\t\t\t$type = 'N';\n\n\t\t} elsif ($cur =~ /^(sizeof)\\s*(\\()?/o) {\n\t\t\tprint \"SIZEOF($1)\\n\" if ($dbg_values > 1);\n\t\t\tif (defined $2) {\n\t\t\t\t$av_pending = 'V';\n\t\t\t}\n\t\t\t$type = 'N';\n\n\t\t} elsif ($cur =~ /^(if|while|for)\\b/o) {\n\t\t\tprint \"COND($1)\\n\" if ($dbg_values > 1);\n\t\t\t$av_pending = 'E';\n\t\t\t$type = 'N';\n\n\t\t} elsif ($cur =~/^(case)/o) {\n\t\t\tprint \"CASE($1)\\n\" if ($dbg_values > 1);\n\t\t\t$av_pend_colon = 'C';\n\t\t\t$type = 'N';\n\n\t\t} elsif ($cur =~/^(return|else|goto|typeof|__typeof__)\\b/o) {\n\t\t\tprint \"KEYWORD($1)\\n\" if ($dbg_values > 1);\n\t\t\t$type = 'N';\n\n\t\t} elsif ($cur =~ /^(\\()/o) {\n\t\t\tprint \"PAREN('$1')\\n\" if ($dbg_values > 1);\n\t\t\tpush(@av_paren_type, $av_pending);\n\t\t\t$av_pending = '_';\n\t\t\t$type = 'N';\n\n\t\t} elsif ($cur =~ /^(\\))/o) {\n\t\t\tmy $new_type = pop(@av_paren_type);\n\t\t\tif ($new_type ne '_') {\n\t\t\t\t$type = $new_type;\n\t\t\t\tprint \"PAREN('$1') -> $type\\n\"\n\t\t\t\t\t\t\tif ($dbg_values > 1);\n\t\t\t} else {\n\t\t\t\tprint \"PAREN('$1')\\n\" if ($dbg_values > 1);\n\t\t\t}\n\n\t\t} elsif ($cur =~ /^($Ident)\\s*\\(/o) {\n\t\t\tprint \"FUNC($1)\\n\" if ($dbg_values > 1);\n\t\t\t$type = 'V';\n\t\t\t$av_pending = 'V';\n\n\t\t} elsif ($cur =~ /^($Ident\\s*):(?:\\s*\\d+\\s*(,|=|;))?/) {\n\t\t\tif (defined $2 && $type eq 'C' || $type eq 'T') {\n\t\t\t\t$av_pend_colon = 'B';\n\t\t\t} elsif ($type eq 'E') {\n\t\t\t\t$av_pend_colon = 'L';\n\t\t\t}\n\t\t\tprint \"IDENT_COLON($1,$type>$av_pend_colon)\\n\" if ($dbg_values > 1);\n\t\t\t$type = 'V';\n\n\t\t} elsif ($cur =~ /^($Ident|$Constant)/o) {\n\t\t\tprint \"IDENT($1)\\n\" if ($dbg_values > 1);\n\t\t\t$type = 'V';\n\n\t\t} elsif ($cur =~ /^($Assignment)/o) {\n\t\t\tprint \"ASSIGN($1)\\n\" if ($dbg_values > 1);\n\t\t\t$type = 'N';\n\n\t\t} elsif ($cur =~/^(;|{|})/) {\n\t\t\tprint \"END($1)\\n\" if ($dbg_values > 1);\n\t\t\t$type = 'E';\n\t\t\t$av_pend_colon = 'O';\n\n\t\t} elsif ($cur =~/^(,)/) {\n\t\t\tprint \"COMMA($1)\\n\" if ($dbg_values > 1);\n\t\t\t$type = 'C';\n\n\t\t} elsif ($cur =~ /^(\\?)/o) {\n\t\t\tprint \"QUESTION($1)\\n\" if ($dbg_values > 1);\n\t\t\t$type = 'N';\n\n\t\t} elsif ($cur =~ /^(:)/o) {\n\t\t\tprint \"COLON($1,$av_pend_colon)\\n\" if ($dbg_values > 1);\n\n\t\t\tsubstr($var, length($res), 1, $av_pend_colon);\n\t\t\tif ($av_pend_colon eq 'C' || $av_pend_colon eq 'L') {\n\t\t\t\t$type = 'E';\n\t\t\t} else {\n\t\t\t\t$type = 'N';\n\t\t\t}\n\t\t\t$av_pend_colon = 'O';\n\n\t\t} elsif ($cur =~ /^(\\[)/o) {\n\t\t\tprint \"CLOSE($1)\\n\" if ($dbg_values > 1);\n\t\t\t$type = 'N';\n\n\t\t} elsif ($cur =~ /^(-(?![->])|\\+(?!\\+)|\\*|\\&\\&|\\&)/o) {\n\t\t\tmy $variant;\n\n\t\t\tprint \"OPV($1)\\n\" if ($dbg_values > 1);\n\t\t\tif ($type eq 'V') {\n\t\t\t\t$variant = 'B';\n\t\t\t} else {\n\t\t\t\t$variant = 'U';\n\t\t\t}\n\n\t\t\tsubstr($var, length($res), 1, $variant);\n\t\t\t$type = 'N';\n\n\t\t} elsif ($cur =~ /^($Operators)/o) {\n\t\t\tprint \"OP($1)\\n\" if ($dbg_values > 1);\n\t\t\tif ($1 ne '++' && $1 ne '--') {\n\t\t\t\t$type = 'N';\n\t\t\t}\n\n\t\t} elsif ($cur =~ /(^.)/o) {\n\t\t\tprint \"C($1)\\n\" if ($dbg_values > 1);\n\t\t}\n\t\tif (defined $1) {\n\t\t\t$cur = substr($cur, length($1));\n\t\t\t$res .= $type x length($1);\n\t\t}\n\t}\n\n\treturn ($res, $var);\n}\n\nsub possible {\n\tmy ($possible, $line) = @_;\n\tmy $notPermitted = qr{(?:\n\t\t^(?:\n\t\t\t$Modifier|\n\t\t\t$Storage|\n\t\t\t$Type|\n\t\t\tDEFINE_\\S+\n\t\t)$|\n\t\t^(?:\n\t\t\tgoto|\n\t\t\treturn|\n\t\t\tcase|\n\t\t\telse|\n\t\t\tasm|__asm__|\n\t\t\tdo|\n\t\t\t\\#|\n\t\t\t\\#\\#|\n\t\t)(?:\\s|$)|\n\t\t^(?:typedef|struct|enum)\\b\n\t    )}x;\n\twarn \"CHECK<$possible> ($line)\\n\" if ($dbg_possible > 2);\n\tif ($possible !~ $notPermitted) {\n\t\t# Check for modifiers.\n\t\t$possible =~ s/\\s*$Storage\\s*//g;\n\t\t$possible =~ s/\\s*$Sparse\\s*//g;\n\t\tif ($possible =~ /^\\s*$/) {\n\n\t\t} elsif ($possible =~ /\\s/) {\n\t\t\t$possible =~ s/\\s*$Type\\s*//g;\n\t\t\tfor my $modifier (split(' ', $possible)) {\n\t\t\t\tif ($modifier !~ $notPermitted) {\n\t\t\t\t\twarn \"MODIFIER: $modifier ($possible) ($line)\\n\" if ($dbg_possible);\n\t\t\t\t\tpush(@modifierListFile, $modifier);\n\t\t\t\t}\n\t\t\t}\n\n\t\t} else {\n\t\t\twarn \"POSSIBLE: $possible ($line)\\n\" if ($dbg_possible);\n\t\t\tpush(@typeListFile, $possible);\n\t\t}\n\t\tbuild_types();\n\t} else {\n\t\twarn \"NOTPOSS: $possible ($line)\\n\" if ($dbg_possible > 1);\n\t}\n}\n\nmy $prefix = '';\n\nsub show_type {\n\tmy ($type) = @_;\n\n\t$type =~ tr/[a-z]/[A-Z]/;\n\n\treturn defined $use_type{$type} if (scalar keys %use_type > 0);\n\n\treturn !defined $ignore_type{$type};\n}\n\nsub report {\n\tmy ($level, $type, $msg) = @_;\n\n\tif (!show_type($type) ||\n\t    (defined $tst_only && $msg !~ /\\Q$tst_only\\E/)) {\n\t\treturn 0;\n\t}\n\tmy $output = '';\n\tif ($color) {\n\t\tif ($level eq 'ERROR') {\n\t\t\t$output .= RED;\n\t\t} elsif ($level eq 'WARNING') {\n\t\t\t$output .= YELLOW;\n\t\t} else {\n\t\t\t$output .= GREEN;\n\t\t}\n\t}\n\t$output .= $prefix . $level . ':';\n\tif ($show_types) {\n\t\t$output .= BLUE if ($color);\n\t\t$output .= \"$type:\";\n\t}\n\t$output .= RESET if ($color);\n\t$output .= ' ' . $msg . \"\\n\";\n\n\tif ($showfile) {\n\t\tmy @lines = split(\"\\n\", $output, -1);\n\t\tsplice(@lines, 1, 1);\n\t\t$output = join(\"\\n\", @lines);\n\t}\n\t$output = (split('\\n', $output))[0] . \"\\n\" if ($terse);\n\n\tpush(our @report, $output);\n\n\treturn 1;\n}\n\nsub report_dump {\n\tour @report;\n}\n\nsub fixup_current_range {\n\tmy ($lineRef, $offset, $length) = @_;\n\n\tif ($$lineRef =~ /^\\@\\@ -\\d+,\\d+ \\+(\\d+),(\\d+) \\@\\@/) {\n\t\tmy $o = $1;\n\t\tmy $l = $2;\n\t\tmy $no = $o + $offset;\n\t\tmy $nl = $l + $length;\n\t\t$$lineRef =~ s/\\+$o,$l \\@\\@/\\+$no,$nl \\@\\@/;\n\t}\n}\n\nsub fix_inserted_deleted_lines {\n\tmy ($linesRef, $insertedRef, $deletedRef) = @_;\n\n\tmy $range_last_linenr = 0;\n\tmy $delta_offset = 0;\n\n\tmy $old_linenr = 0;\n\tmy $new_linenr = 0;\n\n\tmy $next_insert = 0;\n\tmy $next_delete = 0;\n\n\tmy @lines = ();\n\n\tmy $inserted = @{$insertedRef}[$next_insert++];\n\tmy $deleted = @{$deletedRef}[$next_delete++];\n\n\tforeach my $old_line (@{$linesRef}) {\n\t\tmy $save_line = 1;\n\t\tmy $line = $old_line;\t#don't modify the array\n\t\tif ($line =~ /^(?:\\+\\+\\+|\\-\\-\\-)\\s+\\S+/) {\t#new filename\n\t\t\t$delta_offset = 0;\n\t\t} elsif ($line =~ /^\\@\\@ -\\d+,\\d+ \\+\\d+,\\d+ \\@\\@/) {\t#new hunk\n\t\t\t$range_last_linenr = $new_linenr;\n\t\t\tfixup_current_range(\\$line, $delta_offset, 0);\n\t\t}\n\n\t\twhile (defined($deleted) && ${$deleted}{'LINENR'} == $old_linenr) {\n\t\t\t$deleted = @{$deletedRef}[$next_delete++];\n\t\t\t$save_line = 0;\n\t\t\tfixup_current_range(\\$lines[$range_last_linenr], $delta_offset--, -1);\n\t\t}\n\n\t\twhile (defined($inserted) && ${$inserted}{'LINENR'} == $old_linenr) {\n\t\t\tpush(@lines, ${$inserted}{'LINE'});\n\t\t\t$inserted = @{$insertedRef}[$next_insert++];\n\t\t\t$new_linenr++;\n\t\t\tfixup_current_range(\\$lines[$range_last_linenr], $delta_offset++, 1);\n\t\t}\n\n\t\tif ($save_line) {\n\t\t\tpush(@lines, $line);\n\t\t\t$new_linenr++;\n\t\t}\n\n\t\t$old_linenr++;\n\t}\n\n\treturn @lines;\n}\n\nsub fix_insert_line {\n\tmy ($linenr, $line) = @_;\n\n\tmy $inserted = {\n\t\tLINENR => $linenr,\n\t\tLINE => $line,\n\t};\n\tpush(@fixed_inserted, $inserted);\n}\n\nsub fix_delete_line {\n\tmy ($linenr, $line) = @_;\n\n\tmy $deleted = {\n\t\tLINENR => $linenr,\n\t\tLINE => $line,\n\t};\n\n\tpush(@fixed_deleted, $deleted);\n}\n\nsub ERROR {\n\tmy ($type, $msg) = @_;\n\n\tif (report(\"ERROR\", $type, $msg)) {\n\t\tour $clean = 0;\n\t\tour $cnt_error++;\n\t\treturn 1;\n\t}\n\treturn 0;\n}\nsub WARN {\n\tmy ($type, $msg) = @_;\n\n\tif (report(\"WARNING\", $type, $msg)) {\n\t\tour $clean = 0;\n\t\tour $cnt_warn++;\n\t\treturn 1;\n\t}\n\treturn 0;\n}\nsub CHK {\n\tmy ($type, $msg) = @_;\n\n\tif ($check && report(\"CHECK\", $type, $msg)) {\n\t\tour $clean = 0;\n\t\tour $cnt_chk++;\n\t\treturn 1;\n\t}\n\treturn 0;\n}\n\nsub check_absolute_file {\n\tmy ($absolute, $herecurr) = @_;\n\tmy $file = $absolute;\n\n\t##print \"absolute<$absolute>\\n\";\n\n\t# See if any suffix of this path is a path within the tree.\n\twhile ($file =~ s@^[^/]*/@@) {\n\t\tif (-f \"$root/$file\") {\n\t\t\t##print \"file<$file>\\n\";\n\t\t\tlast;\n\t\t}\n\t}\n\tif (! -f _)  {\n\t\treturn 0;\n\t}\n\n\t# It is, so see if the prefix is acceptable.\n\tmy $prefix = $absolute;\n\tsubstr($prefix, -length($file)) = '';\n\n\t##print \"prefix<$prefix>\\n\";\n\tif ($prefix ne \".../\") {\n\t\tWARN(\"USE_RELATIVE_PATH\",\n\t\t     \"use relative pathname instead of absolute in changelog text\\n\" . $herecurr);\n\t}\n}\n\nsub trim {\n\tmy ($string) = @_;\n\n\t$string =~ s/^\\s+|\\s+$//g;\n\n\treturn $string;\n}\n\nsub ltrim {\n\tmy ($string) = @_;\n\n\t$string =~ s/^\\s+//;\n\n\treturn $string;\n}\n\nsub rtrim {\n\tmy ($string) = @_;\n\n\t$string =~ s/\\s+$//;\n\n\treturn $string;\n}\n\nsub string_find_replace {\n\tmy ($string, $find, $replace) = @_;\n\n\t$string =~ s/$find/$replace/g;\n\n\treturn $string;\n}\n\nsub tabify {\n\tmy ($leading) = @_;\n\n\tmy $source_indent = $tabsize;\n\tmy $max_spaces_before_tab = $source_indent - 1;\n\tmy $spaces_to_tab = \" \" x $source_indent;\n\n\t#convert leading spaces to tabs\n\t1 while $leading =~ s@^([\\t]*)$spaces_to_tab@$1\\t@g;\n\t#Remove spaces before a tab\n\t1 while $leading =~ s@^([\\t]*)( {1,$max_spaces_before_tab})\\t@$1\\t@g;\n\n\treturn \"$leading\";\n}\n\nsub pos_last_openparen {\n\tmy ($line) = @_;\n\n\tmy $pos = 0;\n\n\tmy $opens = $line =~ tr/\\(/\\(/;\n\tmy $closes = $line =~ tr/\\)/\\)/;\n\n\tmy $last_openparen = 0;\n\n\tif (($opens == 0) || ($closes >= $opens)) {\n\t\treturn -1;\n\t}\n\n\tmy $len = length($line);\n\n\tfor ($pos = 0; $pos < $len; $pos++) {\n\t\tmy $string = substr($line, $pos);\n\t\tif ($string =~ /^($FuncArg|$balanced_parens)/) {\n\t\t\t$pos += length($1) - 1;\n\t\t} elsif (substr($line, $pos, 1) eq '(') {\n\t\t\t$last_openparen = $pos;\n\t\t} elsif (index($string, '(') == -1) {\n\t\t\tlast;\n\t\t}\n\t}\n\n\treturn length(expand_tabs(substr($line, 0, $last_openparen))) + 1;\n}\n\nsub get_raw_comment {\n\tmy ($line, $rawline) = @_;\n\tmy $comment = '';\n\n\tfor my $i (0 .. (length($line) - 1)) {\n\t\tif (substr($line, $i, 1) eq \"$;\") {\n\t\t\t$comment .= substr($rawline, $i, 1);\n\t\t}\n\t}\n\n\treturn $comment;\n}\n\nsub process {\n\tmy $filename = shift;\n\n\tmy $linenr=0;\n\tmy $prevline=\"\";\n\tmy $prevrawline=\"\";\n\tmy $stashline=\"\";\n\tmy $stashrawline=\"\";\n\n\tmy $length;\n\tmy $indent;\n\tmy $previndent=0;\n\tmy $stashindent=0;\n\n\tour $clean = 1;\n\tmy $signoff = 0;\n\tmy $author = '';\n\tmy $authorsignoff = 0;\n\tmy $is_patch = 0;\n\tmy $is_binding_patch = -1;\n\tmy $in_header_lines = $file ? 0 : 1;\n\tmy $in_commit_log = 0;\t\t#Scanning lines before patch\n\tmy $has_patch_separator = 0;\t#Found a --- line\n\tmy $has_commit_log = 0;\t\t#Encountered lines before patch\n\tmy $commit_log_lines = 0;\t#Number of commit log lines\n\tmy $commit_log_possible_stack_dump = 0;\n\tmy $commit_log_long_line = 0;\n\tmy $commit_log_has_diff = 0;\n\tmy $reported_maintainer_file = 1;\n\tmy $non_utf8_charset = 0;\n\n\tmy $last_blank_line = 0;\n\tmy $last_coalesced_string_linenr = -1;\n\n\tour @report = ();\n\tour $cnt_lines = 0;\n\tour $cnt_error = 0;\n\tour $cnt_warn = 0;\n\tour $cnt_chk = 0;\n\n\t# Trace the real file/line as we go.\n\tmy $realfile = '';\n\tmy $realline = 0;\n\tmy $realcnt = 0;\n\tmy $here = '';\n\tmy $context_function;\t\t#undef'd unless there's a known function\n\tmy $in_comment = 0;\n\tmy $comment_edge = 0;\n\tmy $first_line = 0;\n\tmy $p1_prefix = '';\n\n\tmy $prev_values = 'E';\n\n\t# suppression flags\n\tmy %suppress_ifbraces;\n\tmy %suppress_whiletrailers;\n\tmy %suppress_export;\n\tmy $suppress_statement = 0;\n\n\tmy %signatures = ();\n\n\tmy $camelcase_file_seeded = 0;\n\n\tmy $checklicenseline = 1;\n\n\tsanitise_line_reset();\n\tmy $line;\n\tforeach my $rawline (@rawlines) {\n\t\t$linenr++;\n\t\t$line = $rawline;\n\n\t\tpush(@fixed, $rawline) if ($fix);\n\n\t\tif ($rawline =~ /^\\@\\@ -\\d+(?:,\\d+)? \\+(\\d+)(,(\\d+))? \\@\\@/) {\n\t\t\t$realline=$1-1;\n\t\t\tif (defined $2) {\n\t\t\t\t$realcnt=$3+1;\n\t\t\t} else {\n\t\t\t\t$realcnt=1+1;\n\t\t\t}\n\t\t\t$in_comment = 0;\n\n\t\t\t# Guestimate if this is a continuing comment.  Run\n\t\t\t# the context looking for a comment \"edge\".  If this\n\t\t\t# edge is a close comment then we must be in a comment\n\t\t\t# at context start.\n\t\t\tmy $edge;\n\t\t\tmy $cnt = $realcnt;\n\t\t\tfor (my $ln = $linenr + 1; $cnt > 0; $ln++) {\n\t\t\t\tnext if (defined $rawlines[$ln - 1] &&\n\t\t\t\t\t $rawlines[$ln - 1] =~ /^-/);\n\t\t\t\t$cnt--;\n\t\t\t\t#print \"RAW<$rawlines[$ln - 1]>\\n\";\n\t\t\t\tlast if (!defined $rawlines[$ln - 1]);\n\t\t\t\tif ($rawlines[$ln - 1] =~ m@(/\\*|\\*/)@ &&\n\t\t\t\t    $rawlines[$ln - 1] !~ m@\"[^\"]*(?:/\\*|\\*/)[^\"]*\"@) {\n\t\t\t\t\t($edge) = $1;\n\t\t\t\t\tlast;\n\t\t\t\t}\n\t\t\t}\n\t\t\tif (defined $edge && $edge eq '*/') {\n\t\t\t\t$in_comment = 1;\n\t\t\t}\n\n\t\t\t# Guestimate if this is a continuing comment.  If this\n\t\t\t# is the start of a diff block and this line starts\n\t\t\t# ' *' then it is very likely a comment.\n\t\t\tif (!defined $edge &&\n\t\t\t    $rawlines[$linenr] =~ m@^.\\s*(?:\\*\\*+| \\*)(?:\\s|$)@)\n\t\t\t{\n\t\t\t\t$in_comment = 1;\n\t\t\t}\n\n\t\t\t##print \"COMMENT:$in_comment edge<$edge> $rawline\\n\";\n\t\t\tsanitise_line_reset($in_comment);\n\n\t\t} elsif ($realcnt && $rawline =~ /^(?:\\+| |$)/) {\n\t\t\t# Standardise the strings and chars within the input to\n\t\t\t# simplify matching -- only bother with positive lines.\n\t\t\t$line = sanitise_line($rawline);\n\t\t}\n\t\tpush(@lines, $line);\n\n\t\tif ($realcnt > 1) {\n\t\t\t$realcnt-- if ($line =~ /^(?:\\+| |$)/);\n\t\t} else {\n\t\t\t$realcnt = 0;\n\t\t}\n\n\t\t#print \"==>$rawline\\n\";\n\t\t#print \"-->$line\\n\";\n\t}\n\n\t$prefix = '';\n\n\t$realcnt = 0;\n\t$linenr = 0;\n\t$fixlinenr = -1;\n\tforeach my $line (@lines) {\n\t\t$linenr++;\n\t\t$fixlinenr++;\n\t\tmy $sline = $line;\t#copy of $line\n\t\t$sline =~ s/$;/ /g;\t#with comments as spaces\n\n\t\tmy $rawline = $rawlines[$linenr - 1];\n\t\tmy $raw_comment = get_raw_comment($line, $rawline);\n\n# check if it's a mode change, rename or start of a patch\n\t\tif (!$in_commit_log &&\n\t\t    ($line =~ /^ mode change [0-7]+ => [0-7]+ \\S+\\s*$/ ||\n\t\t    ($line =~ /^rename (?:from|to) \\S+\\s*$/ ||\n\t\t     $line =~ /^diff --git a\\/[\\w\\/\\.\\_\\-]+ b\\/\\S+\\s*$/))) {\n\t\t\t$is_patch = 1;\n\t\t}\n\n#extract the line range in the file after the patch is applied\n\t\tif (!$in_commit_log &&\n\t\t    $line =~ /^\\@\\@ -\\d+(?:,\\d+)? \\+(\\d+)(,(\\d+))? \\@\\@(.*)/) {\n\t\t\tmy $context = $4;\n\t\t\t$is_patch = 1;\n\t\t\t$first_line = $linenr + 1;\n\t\t\t$realline=$1-1;\n\t\t\tif (defined $2) {\n\t\t\t\t$realcnt=$3+1;\n\t\t\t} else {\n\t\t\t\t$realcnt=1+1;\n\t\t\t}\n\t\t\tannotate_reset();\n\t\t\t$prev_values = 'E';\n\n\t\t\t%suppress_ifbraces = ();\n\t\t\t%suppress_whiletrailers = ();\n\t\t\t%suppress_export = ();\n\t\t\t$suppress_statement = 0;\n\t\t\tif ($context =~ /\\b(\\w+)\\s*\\(/) {\n\t\t\t\t$context_function = $1;\n\t\t\t} else {\n\t\t\t\tundef $context_function;\n\t\t\t}\n\t\t\tnext;\n\n# track the line number as we move through the hunk, note that\n# new versions of GNU diff omit the leading space on completely\n# blank context lines so we need to count that too.\n\t\t} elsif ($line =~ /^( |\\+|$)/) {\n\t\t\t$realline++;\n\t\t\t$realcnt-- if ($realcnt != 0);\n\n\t\t\t# Measure the line length and indent.\n\t\t\t($length, $indent) = line_stats($rawline);\n\n\t\t\t# Track the previous line.\n\t\t\t($prevline, $stashline) = ($stashline, $line);\n\t\t\t($previndent, $stashindent) = ($stashindent, $indent);\n\t\t\t($prevrawline, $stashrawline) = ($stashrawline, $rawline);\n\n\t\t\t#warn \"line<$line>\\n\";\n\n\t\t} elsif ($realcnt == 1) {\n\t\t\t$realcnt--;\n\t\t}\n\n\t\tmy $hunk_line = ($realcnt != 0);\n\n\t\t$here = \"#$linenr: \" if (!$file);\n\t\t$here = \"#$realline: \" if ($file);\n\n\t\tmy $found_file = 0;\n\t\t# extract the filename as it passes\n\t\tif ($line =~ /^diff --git.*?(\\S+)$/) {\n\t\t\t$realfile = $1;\n\t\t\t$realfile =~ s@^([^/]*)/@@ if (!$file);\n\t\t\t$in_commit_log = 0;\n\t\t\t$found_file = 1;\n\t\t} elsif ($line =~ /^\\+\\+\\+\\s+(\\S+)/) {\n\t\t\t$realfile = $1;\n\t\t\t$realfile =~ s@^([^/]*)/@@ if (!$file);\n\t\t\t$in_commit_log = 0;\n\n\t\t\t$p1_prefix = $1;\n\t\t\tif (!$file && $tree && $p1_prefix ne '' &&\n\t\t\t    -e \"$root/$p1_prefix\") {\n\t\t\t\tWARN(\"PATCH_PREFIX\",\n\t\t\t\t     \"patch prefix '$p1_prefix' exists, appears to be a -p0 patch\\n\");\n\t\t\t}\n\n\t\t\tif ($realfile =~ m@^include/asm/@) {\n\t\t\t\tERROR(\"MODIFIED_INCLUDE_ASM\",\n\t\t\t\t      \"do not modify files in include/asm, change architecture specific files in include/asm-<architecture>\\n\" . \"$here$rawline\\n\");\n\t\t\t}\n\t\t\t$found_file = 1;\n\t\t}\n\n#make up the handle for any error we report on this line\n\t\tif ($showfile) {\n\t\t\t$prefix = \"$realfile:$realline: \"\n\t\t} elsif ($emacs) {\n\t\t\tif ($file) {\n\t\t\t\t$prefix = \"$filename:$realline: \";\n\t\t\t} else {\n\t\t\t\t$prefix = \"$filename:$linenr: \";\n\t\t\t}\n\t\t}\n\n\t\tif ($found_file) {\n\t\t\tif (is_maintained_obsolete($realfile)) {\n\t\t\t\tWARN(\"OBSOLETE\",\n\t\t\t\t     \"$realfile is marked as 'obsolete' in the MAINTAINERS hierarchy.  No unnecessary modifications please.\\n\");\n\t\t\t}\n\t\t\tif ($realfile =~ m@^(?:drivers/net/|net/|drivers/staging/)@) {\n\t\t\t\t$check = 1;\n\t\t\t} else {\n\t\t\t\t$check = $check_orig;\n\t\t\t}\n\t\t\t$checklicenseline = 1;\n\n\t\t\tif ($realfile !~ /^MAINTAINERS/) {\n\t\t\t\tmy $last_binding_patch = $is_binding_patch;\n\t\t\t}\n\n\t\t\tnext;\n\t\t}\n\n\t\t$here .= \"FILE: $realfile:$realline:\" if ($realcnt != 0);\n\n\t\tmy $hereline = \"$here\\n$rawline\\n\";\n\t\tmy $herecurr = \"$here\\n$rawline\\n\";\n\t\tmy $hereprev = \"$here\\n$prevrawline\\n$rawline\\n\";\n\n\t\t$cnt_lines++ if ($realcnt != 0);\n\n# Verify the existence of a commit log if appropriate\n# 2 is used because a $signature is counted in $commit_log_lines\n\t\tif ($in_commit_log) {\n\t\t\tif ($line !~ /^\\s*$/) {\n\t\t\t\t$commit_log_lines++;\t#could be a $signature\n\t\t\t}\n\t\t} elsif ($has_commit_log && $commit_log_lines < 2) {\n\t\t\tWARN(\"COMMIT_MESSAGE\",\n\t\t\t     \"Missing commit description - Add an appropriate one\\n\");\n\t\t\t$commit_log_lines = 2;\t#warn only once\n\t\t}\n\n# Check if the commit log has what seems like a diff which can confuse patch\n\t\tif ($in_commit_log && !$commit_log_has_diff &&\n\t\t    (($line =~ m@^\\s+diff\\b.*a/[\\w/]+@ &&\n\t\t      $line =~ m@^\\s+diff\\b.*a/([\\w/]+)\\s+b/$1\\b@) ||\n\t\t     $line =~ m@^\\s*(?:\\-\\-\\-\\s+a/|\\+\\+\\+\\s+b/)@ ||\n\t\t     $line =~ m/^\\s*\\@\\@ \\-\\d+,\\d+ \\+\\d+,\\d+ \\@\\@/)) {\n\t\t\tERROR(\"DIFF_IN_COMMIT_MSG\",\n\t\t\t      \"Avoid using diff content in the commit message - patch(1) might not work\\n\" . $herecurr);\n\t\t\t$commit_log_has_diff = 1;\n\t\t}\n\n# Check for incorrect file permissions\n\t\tif ($line =~ /^new (file )?mode.*[7531]\\d{0,2}$/) {\n\t\t\tmy $permhere = $here . \"FILE: $realfile\\n\";\n\t\t\tif ($realfile !~ m@scripts/@ &&\n\t\t\t    $realfile !~ /\\.(py|pl|awk|sh)$/) {\n\t\t\t\tERROR(\"EXECUTE_PERMISSIONS\",\n\t\t\t\t      \"do not set execute permissions for source files\\n\" . $permhere);\n\t\t\t}\n\t\t}\n\n# Check the patch for a From:\n\t\tif (decode(\"MIME-Header\", $line) =~ /^From:\\s*(.*)/) {\n\t\t\t$author = $1;\n\t\t\t$author = encode(\"utf8\", $author) if ($line =~ /=\\?utf-8\\?/i);\n\t\t\t$author =~ s/\"//g;\n\t\t\t$author = reformat_email($author);\n\t\t}\n\n# Check the patch for a signoff:\n\t\tif ($line =~ /^\\s*signed-off-by:\\s*(.*)/i) {\n\t\t\t$signoff++;\n\t\t\t$in_commit_log = 0;\n\t\t\tif ($author ne '') {\n\t\t\t\tif (same_email_addresses($1, $author)) {\n\t\t\t\t\t$authorsignoff = 1;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n# Check for patch separator\n\t\tif ($line =~ /^---$/) {\n\t\t\t$has_patch_separator = 1;\n\t\t\t$in_commit_log = 0;\n\t\t}\n\n# Check if MAINTAINERS is being updated.  If so, there's probably no need to\n# emit the \"does MAINTAINERS need updating?\" message on file add/move/delete\n\t\tif ($line =~ /^\\s*MAINTAINERS\\s*\\|/) {\n\t\t\t$reported_maintainer_file = 1;\n\t\t}\n\n# Check signature styles\n\t\tif (!$in_header_lines &&\n\t\t    $line =~ /^(\\s*)([a-z0-9_-]+by:|$signature_tags)(\\s*)(.*)/i) {\n\t\t\tmy $space_before = $1;\n\t\t\tmy $sign_off = $2;\n\t\t\tmy $space_after = $3;\n\t\t\tmy $email = $4;\n\t\t\tmy $ucfirst_sign_off = ucfirst(lc($sign_off));\n\n\t\t\tif ($sign_off !~ /$signature_tags/) {\n\t\t\t\tWARN(\"BAD_SIGN_OFF\",\n\t\t\t\t     \"Non-standard signature: $sign_off\\n\" . $herecurr);\n\t\t\t}\n\t\t\tif (defined $space_before && $space_before ne \"\") {\n\t\t\t\tif (WARN(\"BAD_SIGN_OFF\",\n\t\t\t\t\t \"Do not use whitespace before $ucfirst_sign_off\\n\" . $herecurr) &&\n\t\t\t\t    $fix) {\n\t\t\t\t\t$fixed[$fixlinenr] =\n\t\t\t\t\t    \"$ucfirst_sign_off $email\";\n\t\t\t\t}\n\t\t\t}\n\t\t\tif ($sign_off =~ /-by:$/i && $sign_off ne $ucfirst_sign_off) {\n\t\t\t\tif (WARN(\"BAD_SIGN_OFF\",\n\t\t\t\t\t \"'$ucfirst_sign_off' is the preferred signature form\\n\" . $herecurr) &&\n\t\t\t\t    $fix) {\n\t\t\t\t\t$fixed[$fixlinenr] =\n\t\t\t\t\t    \"$ucfirst_sign_off $email\";\n\t\t\t\t}\n\n\t\t\t}\n\t\t\tif (!defined $space_after || $space_after ne \" \") {\n\t\t\t\tif (WARN(\"BAD_SIGN_OFF\",\n\t\t\t\t\t \"Use a single space after $ucfirst_sign_off\\n\" . $herecurr) &&\n\t\t\t\t    $fix) {\n\t\t\t\t\t$fixed[$fixlinenr] =\n\t\t\t\t\t    \"$ucfirst_sign_off $email\";\n\t\t\t\t}\n\t\t\t}\n\n\t\t\tmy ($email_name, $name_comment, $email_address, $comment) = parse_email($email);\n\t\t\tmy $suggested_email = format_email(($email_name, $email_address));\n\t\t\tif ($suggested_email eq \"\") {\n\t\t\t\tERROR(\"BAD_SIGN_OFF\",\n\t\t\t\t      \"Unrecognized email address: '$email'\\n\" . $herecurr);\n\t\t\t} else {\n\t\t\t\tmy $dequoted = $suggested_email;\n\t\t\t\t$dequoted =~ s/^\"//;\n\t\t\t\t$dequoted =~ s/\" </ </;\n\t\t\t\t# Don't force email to have quotes\n\t\t\t\t# Allow just an angle bracketed address\n\t\t\t\tif (!same_email_addresses($email, $suggested_email)) {\n\t\t\t\t\tWARN(\"BAD_SIGN_OFF\",\n\t\t\t\t\t     \"email address '$email' might be better as '$suggested_email$comment'\\n\" . $herecurr);\n\t\t\t\t}\n\t\t\t}\n\n# Check for duplicate signatures\n\t\t\tmy $sig_nospace = $line;\n\t\t\t$sig_nospace =~ s/\\s//g;\n\t\t\t$sig_nospace = lc($sig_nospace);\n\t\t\tif (defined $signatures{$sig_nospace}) {\n\t\t\t\tWARN(\"BAD_SIGN_OFF\",\n\t\t\t\t     \"Duplicate signature\\n\" . $herecurr);\n\t\t\t} else {\n\t\t\t\t$signatures{$sig_nospace} = 1;\n\t\t\t}\n\n# Check Co-developed-by: immediately followed by Signed-off-by: with same name and email\n\t\t\tif ($sign_off =~ /^co-developed-by:$/i) {\n\t\t\t\tif ($email eq $author) {\n\t\t\t\t\tWARN(\"BAD_SIGN_OFF\",\n\t\t\t\t\t      \"Co-developed-by: should not be used to attribute nominal patch author '$author'\\n\" . \"$here\\n\" . $rawline);\n\t\t\t\t}\n\t\t\t\tif (!defined $lines[$linenr]) {\n\t\t\t\t\tWARN(\"BAD_SIGN_OFF\",\n                                             \"Co-developed-by: must be immediately followed by Signed-off-by:\\n\" . \"$here\\n\" . $rawline);\n\t\t\t\t} elsif ($rawlines[$linenr] !~ /^\\s*signed-off-by:\\s*(.*)/i) {\n\t\t\t\t\tWARN(\"BAD_SIGN_OFF\",\n\t\t\t\t\t     \"Co-developed-by: must be immediately followed by Signed-off-by:\\n\" . \"$here\\n\" . $rawline . \"\\n\" .$rawlines[$linenr]);\n\t\t\t\t} elsif ($1 ne $email) {\n\t\t\t\t\tWARN(\"BAD_SIGN_OFF\",\n\t\t\t\t\t     \"Co-developed-by and Signed-off-by: name/email do not match \\n\" . \"$here\\n\" . $rawline . \"\\n\" .$rawlines[$linenr]);\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n# Check email subject for common tools that don't need to be mentioned\n\t\tif ($in_header_lines &&\n\t\t    $line =~ /^Subject:.*\\b(?:checkpatch|sparse|smatch)\\b[^:]/i) {\n\t\t\tWARN(\"EMAIL_SUBJECT\",\n\t\t\t     \"A patch subject line should describe the change not the tool that found it\\n\" . $herecurr);\n\t\t}\n\n# Check for Gerrit Change-Ids not in any patch context\n\t\tif ($realfile eq '' && !$has_patch_separator && $line =~ /^\\s*change-id:/i) {\n\t\t\tERROR(\"GERRIT_CHANGE_ID\",\n\t\t\t      \"Remove Gerrit Change-Id's before submitting upstream\\n\" . $herecurr);\n\t\t}\n\n# Check if the commit log is in a possible stack dump\n\t\tif ($in_commit_log && !$commit_log_possible_stack_dump &&\n\t\t    ($line =~ /^\\s*(?:WARNING:|BUG:)/ ||\n\t\t     $line =~ /^\\s*\\[\\s*\\d+\\.\\d{6,6}\\s*\\]/ ||\n\t\t\t\t\t# timestamp\n\t\t     $line =~ /^\\s*\\[\\<[0-9a-fA-F]{8,}\\>\\]/) ||\n\t\t     $line =~ /^(?:\\s+\\w+:\\s+[0-9a-fA-F]+){3,3}/ ||\n\t\t     $line =~ /^\\s*\\#\\d+\\s*\\[[0-9a-fA-F]+\\]\\s*\\w+ at [0-9a-fA-F]+/) {\n\t\t\t\t\t# stack dump address styles\n\t\t\t$commit_log_possible_stack_dump = 1;\n\t\t}\n\n# Check for line lengths > 75 in commit log, warn once\n\t\tif ($in_commit_log && !$commit_log_long_line &&\n\t\t    length($line) > 75 &&\n\t\t    !($line =~ /^\\s*[a-zA-Z0-9_\\/\\.]+\\s+\\|\\s+\\d+/ ||\n\t\t\t\t\t# file delta changes\n\t\t      $line =~ /^\\s*(?:[\\w\\.\\-]+\\/)++[\\w\\.\\-]+:/ ||\n\t\t\t\t\t# filename then :\n\t\t      $line =~ /^\\s*(?:Fixes:|Link:)/i ||\n\t\t\t\t\t# A Fixes: or Link: line\n\t\t      $commit_log_possible_stack_dump)) {\n\t\t\tWARN(\"COMMIT_LOG_LONG_LINE\",\n\t\t\t     \"Possible unwrapped commit description (prefer a maximum 75 chars per line)\\n\" . $herecurr);\n\t\t\t$commit_log_long_line = 1;\n\t\t}\n\n# Reset possible stack dump if a blank line is found\n\t\tif ($in_commit_log && $commit_log_possible_stack_dump &&\n\t\t    $line =~ /^\\s*$/) {\n\t\t\t$commit_log_possible_stack_dump = 0;\n\t\t}\n\n# Check for git id commit length and improperly formed commit descriptions\n\t\tif ($in_commit_log && !$commit_log_possible_stack_dump &&\n\t\t    $line !~ /^\\s*(?:Link|Patchwork|http|https|BugLink|base-commit):/i &&\n\t\t    $line !~ /^This reverts commit [0-9a-f]{7,40}/ &&\n\t\t    ($line =~ /\\bcommit\\s+[0-9a-f]{5,}\\b/i ||\n\t\t     ($line =~ /(?:\\s|^)[0-9a-f]{12,40}(?:[\\s\"'\\(\\[]|$)/i &&\n\t\t      $line !~ /[\\<\\[][0-9a-f]{12,40}[\\>\\]]/i &&\n\t\t      $line !~ /\\bfixes:\\s*[0-9a-f]{12,40}/i))) {\n\t\t\tmy $init_char = \"c\";\n\t\t\tmy $orig_commit = \"\";\n\t\t\tmy $short = 1;\n\t\t\tmy $long = 0;\n\t\t\tmy $case = 1;\n\t\t\tmy $space = 1;\n\t\t\tmy $hasdesc = 0;\n\t\t\tmy $hasparens = 0;\n\t\t\tmy $id = '0123456789ab';\n\t\t\tmy $orig_desc = \"commit description\";\n\t\t\tmy $description = \"\";\n\n\t\t\tif ($line =~ /\\b(c)ommit\\s+([0-9a-f]{5,})\\b/i) {\n\t\t\t\t$init_char = $1;\n\t\t\t\t$orig_commit = lc($2);\n\t\t\t} elsif ($line =~ /\\b([0-9a-f]{12,40})\\b/i) {\n\t\t\t\t$orig_commit = lc($1);\n\t\t\t}\n\n\t\t\t$short = 0 if ($line =~ /\\bcommit\\s+[0-9a-f]{12,40}/i);\n\t\t\t$long = 1 if ($line =~ /\\bcommit\\s+[0-9a-f]{41,}/i);\n\t\t\t$space = 0 if ($line =~ /\\bcommit [0-9a-f]/i);\n\t\t\t$case = 0 if ($line =~ /\\b[Cc]ommit\\s+[0-9a-f]{5,40}[^A-F]/);\n\t\t\tif ($line =~ /\\bcommit\\s+[0-9a-f]{5,}\\s+\\(\"([^\"]+)\"\\)/i) {\n\t\t\t\t$orig_desc = $1;\n\t\t\t\t$hasparens = 1;\n\t\t\t} elsif ($line =~ /\\bcommit\\s+[0-9a-f]{5,}\\s*$/i &&\n\t\t\t\t defined $rawlines[$linenr] &&\n\t\t\t\t $rawlines[$linenr] =~ /^\\s*\\(\"([^\"]+)\"\\)/) {\n\t\t\t\t$orig_desc = $1;\n\t\t\t\t$hasparens = 1;\n\t\t\t} elsif ($line =~ /\\bcommit\\s+[0-9a-f]{5,}\\s+\\(\"[^\"]+$/i &&\n\t\t\t\t defined $rawlines[$linenr] &&\n\t\t\t\t $rawlines[$linenr] =~ /^\\s*[^\"]+\"\\)/) {\n\t\t\t\t$line =~ /\\bcommit\\s+[0-9a-f]{5,}\\s+\\(\"([^\"]+)$/i;\n\t\t\t\t$orig_desc = $1;\n\t\t\t\t$rawlines[$linenr] =~ /^\\s*([^\"]+)\"\\)/;\n\t\t\t\t$orig_desc .= \" \" . $1;\n\t\t\t\t$hasparens = 1;\n\t\t\t}\n\n\t\t\t($id, $description) = git_commit_info($orig_commit,\n\t\t\t\t\t\t\t      $id, $orig_desc);\n\n\t\t\tif (defined($id) &&\n\t\t\t   ($short || $long || $space || $case || ($orig_desc ne $description) || !$hasparens)) {\n\t\t\t\tERROR(\"GIT_COMMIT_ID\",\n\t\t\t\t      \"Please use git commit description style 'commit <12+ chars of sha1> (\\\"<title line>\\\")' - ie: '${init_char}ommit $id (\\\"$description\\\")'\\n\" . $herecurr);\n\t\t\t}\n\t\t}\n\n# Check for added, moved or deleted files\n\t\tif (!$reported_maintainer_file && !$in_commit_log &&\n\t\t    ($line =~ /^(?:new|deleted) file mode\\s*\\d+\\s*$/ ||\n\t\t     $line =~ /^rename (?:from|to) [\\w\\/\\.\\-]+\\s*$/ ||\n\t\t     ($line =~ /\\{\\s*([\\w\\/\\.\\-]*)\\s*\\=\\>\\s*([\\w\\/\\.\\-]*)\\s*\\}/ &&\n\t\t      (defined($1) || defined($2))))) {\n\t\t\t$is_patch = 1;\n\t\t\t$reported_maintainer_file = 1;\n\t\t\tWARN(\"FILE_PATH_CHANGES\",\n\t\t\t     \"added, moved or deleted file(s), does MAINTAINERS need updating?\\n\" . $herecurr);\n\t\t}\n\n# Check for wrappage within a valid hunk of the file\n\t\tif ($realcnt != 0 && $line !~ m{^(?:\\+|-| |\\\\ No newline|$)}) {\n\t\t\tERROR(\"CORRUPTED_PATCH\",\n\t\t\t      \"patch seems to be corrupt (line wrapped?)\\n\" .\n\t\t\t\t$herecurr) if (!$emitted_corrupt++);\n\t\t}\n\n# UTF-8 regex found at http://www.w3.org/International/questions/qa-forms-utf-8.en.php\n\t\tif (($realfile =~ /^$/ || $line =~ /^\\+/) &&\n\t\t    $rawline !~ m/^$UTF8*$/) {\n\t\t\tmy ($utf8_prefix) = ($rawline =~ /^($UTF8*)/);\n\n\t\t\tmy $blank = copy_spacing($rawline);\n\t\t\tmy $ptr = substr($blank, 0, length($utf8_prefix)) . \"^\";\n\t\t\tmy $hereptr = \"$hereline$ptr\\n\";\n\n\t\t\tCHK(\"INVALID_UTF8\",\n\t\t\t    \"Invalid UTF-8, patch and commit message should be encoded in UTF-8\\n\" . $hereptr);\n\t\t}\n\n# Check if it's the start of a commit log\n# (not a header line and we haven't seen the patch filename)\n\t\tif ($in_header_lines && $realfile =~ /^$/ &&\n\t\t    !($rawline =~ /^\\s+(?:\\S|$)/ ||\n\t\t      $rawline =~ /^(?:commit\\b|from\\b|[\\w-]+:)/i)) {\n\t\t\t$in_header_lines = 0;\n\t\t\t$in_commit_log = 1;\n\t\t\t$has_commit_log = 1;\n\t\t}\n\n# Check if there is UTF-8 in a commit log when a mail header has explicitly\n# declined it, i.e defined some charset where it is missing.\n\t\tif ($in_header_lines &&\n\t\t    $rawline =~ /^Content-Type:.+charset=\"(.+)\".*$/ &&\n\t\t    $1 !~ /utf-8/i) {\n\t\t\t$non_utf8_charset = 1;\n\t\t}\n\n\t\tif ($in_commit_log && $non_utf8_charset && $realfile =~ /^$/ &&\n\t\t    $rawline =~ /$NON_ASCII_UTF8/) {\n\t\t\tWARN(\"UTF8_BEFORE_PATCH\",\n\t\t\t    \"8-bit UTF-8 used in possible commit log\\n\" . $herecurr);\n\t\t}\n\n# Check for absolute kernel paths in commit message\n\t\tif ($tree && $in_commit_log) {\n\t\t\twhile ($line =~ m{(?:^|\\s)(/\\S*)}g) {\n\t\t\t\tmy $file = $1;\n\n\t\t\t\tif ($file =~ m{^(.*?)(?::\\d+)+:?$} &&\n\t\t\t\t    check_absolute_file($1, $herecurr)) {\n\t\t\t\t\t#\n\t\t\t\t} else {\n\t\t\t\t\tcheck_absolute_file($file, $herecurr);\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n# Check for various typo / spelling mistakes\n\t\tif (defined($misspellings) &&\n\t\t    ($in_commit_log || $line =~ /^(?:\\+|Subject:)/i)) {\n\t\t\twhile ($rawline =~ /(?:^|[^a-z@])($misspellings)(?:\\b|$|[^a-z@])/gi) {\n\t\t\t\tmy $typo = $1;\n\t\t\t\tmy $typo_fix = $spelling_fix{lc($typo)};\n\t\t\t\t$typo_fix = ucfirst($typo_fix) if ($typo =~ /^[A-Z]/);\n\t\t\t\t$typo_fix = uc($typo_fix) if ($typo =~ /^[A-Z]+$/);\n\t\t\t\tmy $msg_level = \\&WARN;\n\t\t\t\t$msg_level = \\&CHK if ($file);\n\t\t\t\tif (&{$msg_level}(\"TYPO_SPELLING\",\n\t\t\t\t\t\t  \"'$typo' may be misspelled - perhaps '$typo_fix'?\\n\" . $herecurr) &&\n\t\t\t\t    $fix) {\n\t\t\t\t\t$fixed[$fixlinenr] =~ s/(^|[^A-Za-z@])($typo)($|[^A-Za-z@])/$1$typo_fix$3/;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n# check for invalid commit id\n\t\tif ($in_commit_log && $line =~ /(^fixes:|\\bcommit)\\s+([0-9a-f]{6,40})\\b/i) {\n\t\t\tmy $id;\n\t\t\tmy $description;\n\t\t\t($id, $description) = git_commit_info($2, undef, undef);\n\t\t\tif (!defined($id)) {\n\t\t\t\tWARN(\"UNKNOWN_COMMIT_ID\",\n\t\t\t\t     \"Unknown commit id '$2', maybe rebased or not pulled?\\n\" . $herecurr);\n\t\t\t}\n\t\t}\n\n# ignore non-hunk lines and lines being removed\n\t\tnext if (!$hunk_line || $line =~ /^-/);\n\n#trailing whitespace\n\t\tif ($line =~ /^\\+.*\\015/) {\n\t\t\tmy $herevet = \"$here\\n\" . cat_vet($rawline) . \"\\n\";\n\t\t\tif (ERROR(\"DOS_LINE_ENDINGS\",\n\t\t\t\t  \"DOS line endings\\n\" . $herevet) &&\n\t\t\t    $fix) {\n\t\t\t\t$fixed[$fixlinenr] =~ s/[\\s\\015]+$//;\n\t\t\t}\n\t\t} elsif ($rawline =~ /^\\+.*\\S\\s+$/ || $rawline =~ /^\\+\\s+$/) {\n\t\t\tmy $herevet = \"$here\\n\" . cat_vet($rawline) . \"\\n\";\n\t\t\tif (ERROR(\"TRAILING_WHITESPACE\",\n\t\t\t\t  \"trailing whitespace\\n\" . $herevet) &&\n\t\t\t    $fix) {\n\t\t\t\t$fixed[$fixlinenr] =~ s/\\s+$//;\n\t\t\t}\n\n\t\t\t$rpt_cleaners = 1;\n\t\t}\n\n# Check for FSF mailing addresses.\n\t\tif ($rawline =~ /\\bwrite to the Free/i ||\n\t\t    $rawline =~ /\\b675\\s+Mass\\s+Ave/i ||\n\t\t    $rawline =~ /\\b59\\s+Temple\\s+Pl/i ||\n\t\t    $rawline =~ /\\b51\\s+Franklin\\s+St/i) {\n\t\t\tmy $herevet = \"$here\\n\" . cat_vet($rawline) . \"\\n\";\n\t\t\tmy $msg_level = \\&ERROR;\n\t\t\t$msg_level = \\&CHK if ($file);\n\t\t\t&{$msg_level}(\"FSF_MAILING_ADDRESS\",\n\t\t\t\t      \"Do not include the paragraph about writing to the Free Software Foundation's mailing address from the sample GPL notice. The FSF has changed addresses in the past, and may do so again. Linux already includes a copy of the GPL.\\n\" . $herevet)\n\t\t}\n\n# check for Kconfig help text having a real description\n# Only applies when adding the entry originally, after that we do not have\n# sufficient context to determine whether it is indeed long enough.\n\t\tif ($realfile =~ /Kconfig/ &&\n\t\t    # 'choice' is usually the last thing on the line (though\n\t\t    # Kconfig supports named choices), so use a word boundary\n\t\t    # (\\b) rather than a whitespace character (\\s)\n\t\t    $line =~ /^\\+\\s*(?:config|menuconfig|choice)\\b/) {\n\t\t\tmy $length = 0;\n\t\t\tmy $cnt = $realcnt;\n\t\t\tmy $ln = $linenr + 1;\n\t\t\tmy $f;\n\t\t\tmy $is_start = 0;\n\t\t\tmy $is_end = 0;\n\t\t\tfor (; $cnt > 0 && defined $lines[$ln - 1]; $ln++) {\n\t\t\t\t$f = $lines[$ln - 1];\n\t\t\t\t$cnt-- if ($lines[$ln - 1] !~ /^-/);\n\t\t\t\t$is_end = $lines[$ln - 1] =~ /^\\+/;\n\n\t\t\t\tnext if ($f =~ /^-/);\n\t\t\t\tlast if (!$file && $f =~ /^\\@\\@/);\n\n\t\t\t\tif ($lines[$ln - 1] =~ /^\\+\\s*(?:bool|tristate|prompt)\\s*[\"']/) {\n\t\t\t\t\t$is_start = 1;\n\t\t\t\t} elsif ($lines[$ln - 1] =~ /^\\+\\s*(?:help|---help---)\\s*$/) {\n\t\t\t\t\tif ($lines[$ln - 1] =~ \"---help---\") {\n\t\t\t\t\t\tWARN(\"CONFIG_DESCRIPTION\",\n\t\t\t\t\t\t     \"prefer 'help' over '---help---' for new help texts\\n\" . $herecurr);\n\t\t\t\t\t}\n\t\t\t\t\t$length = -1;\n\t\t\t\t}\n\n\t\t\t\t$f =~ s/^.//;\n\t\t\t\t$f =~ s/#.*//;\n\t\t\t\t$f =~ s/^\\s+//;\n\t\t\t\tnext if ($f =~ /^$/);\n\n\t\t\t\t# This only checks context lines in the patch\n\t\t\t\t# and so hopefully shouldn't trigger false\n\t\t\t\t# positives, even though some of these are\n\t\t\t\t# common words in help texts\n\t\t\t\tif ($f =~ /^\\s*(?:config|menuconfig|choice|endchoice|\n\t\t\t\t\t\t  if|endif|menu|endmenu|source)\\b/x) {\n\t\t\t\t\t$is_end = 1;\n\t\t\t\t\tlast;\n\t\t\t\t}\n\t\t\t\t$length++;\n\t\t\t}\n\t\t\tif ($is_start && $is_end && $length < $min_conf_desc_length) {\n\t\t\t\tWARN(\"CONFIG_DESCRIPTION\",\n\t\t\t\t     \"please write a paragraph that describes the config symbol fully\\n\" . $herecurr);\n\t\t\t}\n\t\t\t#print \"is_start<$is_start> is_end<$is_end> length<$length>\\n\";\n\t\t}\n\n# check MAINTAINERS entries\n\t\tif ($realfile =~ /^MAINTAINERS$/) {\n# check MAINTAINERS entries for the right form\n\t\t\tif ($rawline =~ /^\\+[A-Z]:/ &&\n\t\t\t    $rawline !~ /^\\+[A-Z]:\\t\\S/) {\n\t\t\t\tif (WARN(\"MAINTAINERS_STYLE\",\n\t\t\t\t\t \"MAINTAINERS entries use one tab after TYPE:\\n\" . $herecurr) &&\n\t\t\t\t    $fix) {\n\t\t\t\t\t$fixed[$fixlinenr] =~ s/^(\\+[A-Z]):\\s*/$1:\\t/;\n\t\t\t\t}\n\t\t\t}\n# check MAINTAINERS entries for the right ordering too\n\t\t\tmy $preferred_order = 'MRLSWQBCPTFXNK';\n\t\t\tif ($rawline =~ /^\\+[A-Z]:/ &&\n\t\t\t    $prevrawline =~ /^[\\+ ][A-Z]:/) {\n\t\t\t\t$rawline =~ /^\\+([A-Z]):\\s*(.*)/;\n\t\t\t\tmy $cur = $1;\n\t\t\t\tmy $curval = $2;\n\t\t\t\t$prevrawline =~ /^[\\+ ]([A-Z]):\\s*(.*)/;\n\t\t\t\tmy $prev = $1;\n\t\t\t\tmy $prevval = $2;\n\t\t\t\tmy $curindex = index($preferred_order, $cur);\n\t\t\t\tmy $previndex = index($preferred_order, $prev);\n\t\t\t\tif ($curindex < 0) {\n\t\t\t\t\tWARN(\"MAINTAINERS_STYLE\",\n\t\t\t\t\t     \"Unknown MAINTAINERS entry type: '$cur'\\n\" . $herecurr);\n\t\t\t\t} else {\n\t\t\t\t\tif ($previndex >= 0 && $curindex < $previndex) {\n\t\t\t\t\t\tWARN(\"MAINTAINERS_STYLE\",\n\t\t\t\t\t\t     \"Misordered MAINTAINERS entry - list '$cur:' before '$prev:'\\n\" . $hereprev);\n\t\t\t\t\t} elsif ((($prev eq 'F' && $cur eq 'F') ||\n\t\t\t\t\t\t  ($prev eq 'X' && $cur eq 'X')) &&\n\t\t\t\t\t\t ($prevval cmp $curval) > 0) {\n\t\t\t\t\t\tWARN(\"MAINTAINERS_STYLE\",\n\t\t\t\t\t\t     \"Misordered MAINTAINERS entry - list file patterns in alphabetic order\\n\" . $hereprev);\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n# discourage the use of boolean for type definition attributes of Kconfig options\n\t\tif ($realfile =~ /Kconfig/ &&\n\t\t    $line =~ /^\\+\\s*\\bboolean\\b/) {\n\t\t\tWARN(\"CONFIG_TYPE_BOOLEAN\",\n\t\t\t     \"Use of boolean is deprecated, please use bool instead.\\n\" . $herecurr);\n\t\t}\n\n\t\tif (($realfile =~ /Makefile.*/ || $realfile =~ /Kbuild.*/) &&\n\t\t    ($line =~ /\\+(EXTRA_[A-Z]+FLAGS).*/)) {\n\t\t\tmy $flag = $1;\n\t\t\tmy $replacement = {\n\t\t\t\t'EXTRA_AFLAGS' =>   'asflags-y',\n\t\t\t\t'EXTRA_CFLAGS' =>   'ccflags-y',\n\t\t\t\t'EXTRA_CPPFLAGS' => 'cppflags-y',\n\t\t\t\t'EXTRA_LDFLAGS' =>  'ldflags-y',\n\t\t\t};\n\n\t\t\tWARN(\"DEPRECATED_VARIABLE\",\n\t\t\t     \"Use of $flag is deprecated, please use \\`$replacement->{$flag} instead.\\n\" . $herecurr) if ($replacement->{$flag});\n\t\t}\n\n# check for using SPDX license tag at beginning of files\n\t\tif ($realline == $checklicenseline) {\n\t\t\tif ($rawline =~ /^[ \\+]\\s*\\#\\!\\s*\\//) {\n\t\t\t\t$checklicenseline = 2;\n\t\t\t} elsif ($rawline =~ /^\\+/) {\n\t\t\t\tmy $comment = \"\";\n\t\t\t\tif ($realfile =~ /\\.(h|s|S)$/) {\n\t\t\t\t\t$comment = '/*';\n\t\t\t\t} elsif ($realfile =~ /\\.(c|dts|dtsi)$/) {\n\t\t\t\t\t$comment = '//';\n\t\t\t\t} elsif (($checklicenseline == 2) || $realfile =~ /\\.(sh|pl|py|awk|tc|yaml)$/) {\n\t\t\t\t\t$comment = '#';\n\t\t\t\t} elsif ($realfile =~ /\\.rst$/) {\n\t\t\t\t\t$comment = '..';\n\t\t\t\t}\n\n# check SPDX comment style for .[chsS] files\n\t\t\t\tif ($realfile =~ /\\.[chsS]$/ &&\n\t\t\t\t    $rawline =~ /SPDX-License-Identifier:/ &&\n\t\t\t\t    $rawline !~ m@^\\+\\s*\\Q$comment\\E\\s*@) {\n\t\t\t\t\tWARN(\"SPDX_LICENSE_TAG\",\n\t\t\t\t\t     \"Improper SPDX comment style for '$realfile', please use '$comment' instead\\n\" . $herecurr);\n\t\t\t\t}\n\n\t\t\t\tif ($comment !~ /^$/ &&\n\t\t\t\t    $rawline !~ m@^\\+\\Q$comment\\E SPDX-License-Identifier: @) {\n\t\t\t\t\tWARN(\"SPDX_LICENSE_TAG\",\n\t\t\t\t\t     \"Missing or malformed SPDX-License-Identifier tag in line $checklicenseline\\n\" . $herecurr);\n\t\t\t\t} elsif ($rawline =~ /(SPDX-License-Identifier: .*)/) {\n\t\t\t\t\tmy $spdx_license = $1;\n\t\t\t\t\tif (!is_SPDX_License_valid($spdx_license)) {\n\t\t\t\t\t\tWARN(\"SPDX_LICENSE_TAG\",\n\t\t\t\t\t\t     \"'$spdx_license' is not supported in LICENSES/...\\n\" . $herecurr);\n\t\t\t\t\t}\n\t\t\t\t\tif ($realfile =~ m@^Documentation/devicetree/bindings/@ &&\n\t\t\t\t\t    not $spdx_license =~ /GPL-2\\.0.*BSD-2-Clause/) {\n\t\t\t\t\t\tmy $msg_level = \\&WARN;\n\t\t\t\t\t\t$msg_level = \\&CHK if ($file);\n\t\t\t\t\t\tif (&{$msg_level}(\"SPDX_LICENSE_TAG\",\n\n\t\t\t\t\t\t\t\t  \"DT binding documents should be licensed (GPL-2.0-only OR BSD-2-Clause)\\n\" . $herecurr) &&\n\t\t\t\t\t\t    $fix) {\n\t\t\t\t\t\t\t$fixed[$fixlinenr] =~ s/SPDX-License-Identifier: .*/SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)/;\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n# check we are in a valid source file if not then ignore this hunk\n\t\tnext if ($realfile !~ /\\.(h|c|s|S|sh|dtsi|dts)$/);\n\n# check for using SPDX-License-Identifier on the wrong line number\n\t\tif ($realline != $checklicenseline &&\n\t\t    $rawline =~ /\\bSPDX-License-Identifier:/ &&\n\t\t    substr($line, @-, @+ - @-) eq \"$;\" x (@+ - @-)) {\n\t\t\tWARN(\"SPDX_LICENSE_TAG\",\n\t\t\t     \"Misplaced SPDX-License-Identifier tag - use line $checklicenseline instead\\n\" . $herecurr);\n\t\t}\n\n# line length limit (with some exclusions)\n#\n# There are a few types of lines that may extend beyond $max_line_length:\n#\tlogging functions like pr_info that end in a string\n#\tlines with a single string\n#\t#defines that are a single string\n#\tlines with an RFC3986 like URL\n#\n# There are 3 different line length message types:\n# LONG_LINE_COMMENT\ta comment starts before but extends beyond $max_line_length\n# LONG_LINE_STRING\ta string starts before but extends beyond $max_line_length\n# LONG_LINE\t\tall other lines longer than $max_line_length\n#\n# if LONG_LINE is ignored, the other 2 types are also ignored\n#\n\n\t\tif ($line =~ /^\\+/ && $length > $max_line_length) {\n\t\t\tmy $msg_type = \"LONG_LINE\";\n\n\t\t\t# Check the allowed long line types first\n\n\t\t\t# logging functions that end in a string that starts\n\t\t\t# before $max_line_length\n\t\t\tif ($line =~ /^\\+\\s*$logFunctions\\s*\\(\\s*(?:(?:KERN_\\S+\\s*|[^\"]*))?($String\\s*(?:|,|\\)\\s*;)\\s*)$/ &&\n\t\t\t    length(expand_tabs(substr($line, 1, length($line) - length($1) - 1))) <= $max_line_length) {\n\t\t\t\t$msg_type = \"\";\n\n\t\t\t# lines with only strings (w/ possible termination)\n\t\t\t# #defines with only strings\n\t\t\t} elsif ($line =~ /^\\+\\s*$String\\s*(?:\\s*|,|\\)\\s*;)\\s*$/ ||\n\t\t\t\t $line =~ /^\\+\\s*#\\s*define\\s+\\w+\\s+$String$/) {\n\t\t\t\t$msg_type = \"\";\n\n\t\t\t# More special cases\n\t\t\t} elsif ($line =~ /^\\+.*\\bEFI_GUID\\s*\\(/ ||\n\t\t\t\t $line =~ /^\\+\\s*(?:\\w+)?\\s*DEFINE_PER_CPU/) {\n\t\t\t\t$msg_type = \"\";\n\n\t\t\t# URL ($rawline is used in case the URL is in a comment)\n\t\t\t} elsif ($rawline =~ /^\\+.*\\b[a-z][\\w\\.\\+\\-]*:\\/\\/\\S+/i) {\n\t\t\t\t$msg_type = \"\";\n\n\t\t\t# Otherwise set the alternate message types\n\n\t\t\t# a comment starts before $max_line_length\n\t\t\t} elsif ($line =~ /($;[\\s$;]*)$/ &&\n\t\t\t\t length(expand_tabs(substr($line, 1, length($line) - length($1) - 1))) <= $max_line_length) {\n\t\t\t\t$msg_type = \"LONG_LINE_COMMENT\"\n\n\t\t\t# a quoted string starts before $max_line_length\n\t\t\t} elsif ($sline =~ /\\s*($String(?:\\s*(?:\\\\|,\\s*|\\)\\s*;\\s*))?)$/ &&\n\t\t\t\t length(expand_tabs(substr($line, 1, length($line) - length($1) - 1))) <= $max_line_length) {\n\t\t\t\t$msg_type = \"LONG_LINE_STRING\"\n\t\t\t}\n\n\t\t\tif ($msg_type ne \"\" &&\n\t\t\t    (show_type(\"LONG_LINE\") || show_type($msg_type))) {\n\t\t\t\tmy $msg_level = \\&WARN;\n\t\t\t\t$msg_level = \\&CHK if ($file);\n\t\t\t\t&{$msg_level}($msg_type,\n\t\t\t\t\t      \"line length of $length exceeds $max_line_length columns\\n\" . $herecurr);\n\t\t\t}\n\t\t}\n\n# check for adding lines without a newline.\n\t\tif ($line =~ /^\\+/ && defined $lines[$linenr] && $lines[$linenr] =~ /^\\\\ No newline at end of file/) {\n\t\t\tWARN(\"MISSING_EOF_NEWLINE\",\n\t\t\t     \"adding a line without newline at end of file\\n\" . $herecurr);\n\t\t}\n\n# check we are in a valid source file C or perl if not then ignore this hunk\n\t\tnext if ($realfile !~ /\\.(h|c|pl|dtsi|dts)$/);\n\n# at the beginning of a line any tabs must come first and anything\n# more than $tabsize must use tabs.\n\t\tif ($rawline =~ /^\\+\\s* \\t\\s*\\S/ ||\n\t\t    $rawline =~ /^\\+\\s*        \\s*/) {\n\t\t\tmy $herevet = \"$here\\n\" . cat_vet($rawline) . \"\\n\";\n\t\t\t$rpt_cleaners = 1;\n\t\t\tif (ERROR(\"CODE_INDENT\",\n\t\t\t\t  \"code indent should use tabs where possible\\n\" . $herevet) &&\n\t\t\t    $fix) {\n\t\t\t\t$fixed[$fixlinenr] =~ s/^\\+([ \\t]+)/\"\\+\" . tabify($1)/e;\n\t\t\t}\n\t\t}\n\n# check for space before tabs.\n\t\tif ($rawline =~ /^\\+/ && $rawline =~ / \\t/) {\n\t\t\tmy $herevet = \"$here\\n\" . cat_vet($rawline) . \"\\n\";\n\t\t\tif (WARN(\"SPACE_BEFORE_TAB\",\n\t\t\t\t\"please, no space before tabs\\n\" . $herevet) &&\n\t\t\t    $fix) {\n\t\t\t\twhile ($fixed[$fixlinenr] =~\n\t\t\t\t\t   s/(^\\+.*) {$tabsize,$tabsize}\\t/$1\\t\\t/) {}\n\t\t\t\twhile ($fixed[$fixlinenr] =~\n\t\t\t\t\t   s/(^\\+.*) +\\t/$1\\t/) {}\n\t\t\t}\n\t\t}\n\n# check for assignments on the start of a line\n\t\tif ($sline =~ /^\\+\\s+($Assignment)[^=]/) {\n\t\t\tCHK(\"ASSIGNMENT_CONTINUATIONS\",\n\t\t\t    \"Assignment operator '$1' should be on the previous line\\n\" . $hereprev);\n\t\t}\n\n# check for && or || at the start of a line\n\t\tif ($rawline =~ /^\\+\\s*(&&|\\|\\|)/) {\n\t\t\tCHK(\"LOGICAL_CONTINUATIONS\",\n\t\t\t    \"Logical continuations should be on the previous line\\n\" . $hereprev);\n\t\t}\n\n# check indentation starts on a tab stop\n\t\tif ($perl_version_ok &&\n\t\t    $sline =~ /^\\+\\t+( +)(?:$c90_Keywords\\b|\\{\\s*$|\\}\\s*(?:else\\b|while\\b|\\s*$)|$Declare\\s*$Ident\\s*[;=])/) {\n\t\t\tmy $indent = length($1);\n\t\t\tif ($indent % $tabsize) {\n\t\t\t\tif (WARN(\"TABSTOP\",\n\t\t\t\t\t \"Statements should start on a tabstop\\n\" . $herecurr) &&\n\t\t\t\t    $fix) {\n\t\t\t\t\t$fixed[$fixlinenr] =~ s@(^\\+\\t+) +@$1 . \"\\t\" x ($indent/$tabsize)@e;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n# check multi-line statement indentation matches previous line\n\t\tif ($perl_version_ok &&\n\t\t    $prevline =~ /^\\+([ \\t]*)((?:$c90_Keywords(?:\\s+if)\\s*)|(?:$Declare\\s*)?(?:$Ident|\\(\\s*\\*\\s*$Ident\\s*\\))\\s*|(?:\\*\\s*)*$Lval\\s*=\\s*$Ident\\s*)\\(.*(\\&\\&|\\|\\||,)\\s*$/) {\n\t\t\t$prevline =~ /^\\+(\\t*)(.*)$/;\n\t\t\tmy $oldindent = $1;\n\t\t\tmy $rest = $2;\n\n\t\t\tmy $pos = pos_last_openparen($rest);\n\t\t\tif ($pos >= 0) {\n\t\t\t\t$line =~ /^(\\+| )([ \\t]*)/;\n\t\t\t\tmy $newindent = $2;\n\n\t\t\t\tmy $goodtabindent = $oldindent .\n\t\t\t\t\t\"\\t\" x ($pos / $tabsize) .\n\t\t\t\t\t\" \"  x ($pos % $tabsize);\n\t\t\t\tmy $goodspaceindent = $oldindent . \" \"  x $pos;\n\n\t\t\t\tif ($newindent ne $goodtabindent &&\n\t\t\t\t    $newindent ne $goodspaceindent) {\n\n\t\t\t\t\tif (CHK(\"PARENTHESIS_ALIGNMENT\",\n\t\t\t\t\t\t\"Alignment should match open parenthesis\\n\" . $hereprev) &&\n\t\t\t\t\t    $fix && $line =~ /^\\+/) {\n\t\t\t\t\t\t$fixed[$fixlinenr] =~\n\t\t\t\t\t\t    s/^\\+[ \\t]*/\\+$goodtabindent/;\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n# check for space after cast like \"(int) foo\" or \"(struct foo) bar\"\n# avoid checking a few false positives:\n#   \"sizeof(<type>)\" or \"__alignof__(<type>)\"\n#   function pointer declarations like \"(*foo)(int) = bar;\"\n#   structure definitions like \"(struct foo) { 0 };\"\n#   multiline macros that define functions\n#   known attributes or the __attribute__ keyword\n\t\tif ($line =~ /^\\+(.*)\\(\\s*$Type\\s*\\)([ \\t]++)((?![={]|\\\\$|$Attribute|__attribute__))/ &&\n\t\t    (!defined($1) || $1 !~ /\\b(?:sizeof|__alignof__)\\s*$/)) {\n\t\t\tif (CHK(\"SPACING\",\n\t\t\t\t\"No space is necessary after a cast\\n\" . $herecurr) &&\n\t\t\t    $fix) {\n\t\t\t\t$fixed[$fixlinenr] =~\n\t\t\t\t    s/(\\(\\s*$Type\\s*\\))[ \\t]+/$1/;\n\t\t\t}\n\t\t}\n\n# Block comment styles\n# Networking with an initial /*\n\t\tif ($realfile =~ m@^(drivers/net/|net/)@ &&\n\t\t    $prevrawline =~ /^\\+[ \\t]*\\/\\*[ \\t]*$/ &&\n\t\t    $rawline =~ /^\\+[ \\t]*\\*/ &&\n\t\t    $realline > 2) {\n\t\t\tWARN(\"NETWORKING_BLOCK_COMMENT_STYLE\",\n\t\t\t     \"networking block comments don't use an empty /* line, use /* Comment...\\n\" . $hereprev);\n\t\t}\n\n# Block comments use * on subsequent lines\n\t\tif ($prevline =~ /$;[ \\t]*$/ &&\t\t\t#ends in comment\n\t\t    $prevrawline =~ /^\\+.*?\\/\\*/ &&\t\t#starting /*\n\t\t    $prevrawline !~ /\\*\\/[ \\t]*$/ &&\t\t#no trailing */\n\t\t    $rawline =~ /^\\+/ &&\t\t\t#line is new\n\t\t    $rawline !~ /^\\+[ \\t]*\\*/) {\t\t#no leading *\n\t\t\tWARN(\"BLOCK_COMMENT_STYLE\",\n\t\t\t     \"Block comments use * on subsequent lines\\n\" . $hereprev);\n\t\t}\n\n# Block comments use */ on trailing lines\n\t\tif ($rawline !~ m@^\\+[ \\t]*\\*/[ \\t]*$@ &&\t#trailing */\n\t\t    $rawline !~ m@^\\+.*/\\*.*\\*/[ \\t]*$@ &&\t#inline /*...*/\n\t\t    $rawline !~ m@^\\+.*\\*{2,}/[ \\t]*$@ &&\t#trailing **/\n\t\t    $rawline =~ m@^\\+[ \\t]*.+\\*\\/[ \\t]*$@) {\t#non blank */\n\t\t\tWARN(\"BLOCK_COMMENT_STYLE\",\n\t\t\t     \"Block comments use a trailing */ on a separate line\\n\" . $herecurr);\n\t\t}\n\n# Block comment * alignment\n\t\tif ($prevline =~ /$;[ \\t]*$/ &&\t\t\t#ends in comment\n\t\t    $line =~ /^\\+[ \\t]*$;/ &&\t\t\t#leading comment\n\t\t    $rawline =~ /^\\+[ \\t]*\\*/ &&\t\t#leading *\n\t\t    (($prevrawline =~ /^\\+.*?\\/\\*/ &&\t\t#leading /*\n\t\t      $prevrawline !~ /\\*\\/[ \\t]*$/) ||\t\t#no trailing */\n\t\t     $prevrawline =~ /^\\+[ \\t]*\\*/)) {\t\t#leading *\n\t\t\tmy $oldindent;\n\t\t\t$prevrawline =~ m@^\\+([ \\t]*/?)\\*@;\n\t\t\tif (defined($1)) {\n\t\t\t\t$oldindent = expand_tabs($1);\n\t\t\t} else {\n\t\t\t\t$prevrawline =~ m@^\\+(.*/?)\\*@;\n\t\t\t\t$oldindent = expand_tabs($1);\n\t\t\t}\n\t\t\t$rawline =~ m@^\\+([ \\t]*)\\*@;\n\t\t\tmy $newindent = $1;\n\t\t\t$newindent = expand_tabs($newindent);\n\t\t\tif (length($oldindent) ne length($newindent)) {\n\t\t\t\tWARN(\"BLOCK_COMMENT_STYLE\",\n\t\t\t\t     \"Block comments should align the * on each line\\n\" . $hereprev);\n\t\t\t}\n\t\t}\n\n# check for missing blank lines after struct/union declarations\n# with exceptions for various attributes and macros\n\t\tif ($prevline =~ /^[\\+ ]};?\\s*$/ &&\n\t\t    $line =~ /^\\+/ &&\n\t\t    !($line =~ /^\\+\\s*$/ ||\n\t\t      $line =~ /^\\+\\s*EXPORT_SYMBOL/ ||\n\t\t      $line =~ /^\\+\\s*MODULE_/i ||\n\t\t      $line =~ /^\\+\\s*\\#\\s*(?:end|elif|else)/ ||\n\t\t      $line =~ /^\\+[a-z_]*init/ ||\n\t\t      $line =~ /^\\+\\s*(?:static\\s+)?[A-Z_]*ATTR/ ||\n\t\t      $line =~ /^\\+\\s*DECLARE/ ||\n\t\t      $line =~ /^\\+\\s*builtin_[\\w_]*driver/ ||\n\t\t      $line =~ /^\\+\\s*__setup/)) {\n\t\t\tif (CHK(\"LINE_SPACING\",\n\t\t\t\t\"Please use a blank line after function/struct/union/enum declarations\\n\" . $hereprev) &&\n\t\t\t    $fix) {\n\t\t\t\tfix_insert_line($fixlinenr, \"\\+\");\n\t\t\t}\n\t\t}\n\n# check for multiple consecutive blank lines\n\t\tif ($prevline =~ /^[\\+ ]\\s*$/ &&\n\t\t    $line =~ /^\\+\\s*$/ &&\n\t\t    $last_blank_line != ($linenr - 1)) {\n\t\t\tif (CHK(\"LINE_SPACING\",\n\t\t\t\t\"Please don't use multiple blank lines\\n\" . $hereprev) &&\n\t\t\t    $fix) {\n\t\t\t\tfix_delete_line($fixlinenr, $rawline);\n\t\t\t}\n\n\t\t\t$last_blank_line = $linenr;\n\t\t}\n\n# check for missing blank lines after declarations\n\t\tif ($sline =~ /^\\+\\s+\\S/ &&\t\t\t#Not at char 1\n\t\t\t# actual declarations\n\t\t    ($prevline =~ /^\\+\\s+$Declare\\s*$Ident\\s*[=,;:\\[]/ ||\n\t\t\t# function pointer declarations\n\t\t     $prevline =~ /^\\+\\s+$Declare\\s*\\(\\s*\\*\\s*$Ident\\s*\\)\\s*[=,;:\\[\\(]/ ||\n\t\t\t# foo bar; where foo is some local typedef or #define\n\t\t     $prevline =~ /^\\+\\s+$Ident(?:\\s+|\\s*\\*\\s*)$Ident\\s*[=,;\\[]/ ||\n\t\t\t# known declaration macros\n\t\t     $prevline =~ /^\\+\\s+$declaration_macros/) &&\n\t\t\t# for \"else if\" which can look like \"$Ident $Ident\"\n\t\t    !($prevline =~ /^\\+\\s+$c90_Keywords\\b/ ||\n\t\t\t# other possible extensions of declaration lines\n\t\t      $prevline =~ /(?:$Compare|$Assignment|$Operators)\\s*$/ ||\n\t\t\t# not starting a section or a macro \"\\\" extended line\n\t\t      $prevline =~ /(?:\\{\\s*|\\\\)$/) &&\n\t\t\t# looks like a declaration\n\t\t    !($sline =~ /^\\+\\s+$Declare\\s*$Ident\\s*[=,;:\\[]/ ||\n\t\t\t# function pointer declarations\n\t\t      $sline =~ /^\\+\\s+$Declare\\s*\\(\\s*\\*\\s*$Ident\\s*\\)\\s*[=,;:\\[\\(]/ ||\n\t\t\t# foo bar; where foo is some local typedef or #define\n\t\t      $sline =~ /^\\+\\s+$Ident(?:\\s+|\\s*\\*\\s*)$Ident\\s*[=,;\\[]/ ||\n\t\t\t# known declaration macros\n\t\t      $sline =~ /^\\+\\s+$declaration_macros/ ||\n\t\t\t# start of struct or union or enum\n\t\t      $sline =~ /^\\+\\s+(?:static\\s+)?(?:const\\s+)?(?:union|struct|enum|typedef)\\b/ ||\n\t\t\t# start or end of block or continuation of declaration\n\t\t      $sline =~ /^\\+\\s+(?:$|[\\{\\}\\.\\#\\\"\\?\\:\\(\\[])/ ||\n\t\t\t# bitfield continuation\n\t\t      $sline =~ /^\\+\\s+$Ident\\s*:\\s*\\d+\\s*[,;]/ ||\n\t\t\t# other possible extensions of declaration lines\n\t\t      $sline =~ /^\\+\\s+\\(?\\s*(?:$Compare|$Assignment|$Operators)/) &&\n\t\t\t# indentation of previous and current line are the same\n\t\t    (($prevline =~ /\\+(\\s+)\\S/) && $sline =~ /^\\+$1\\S/)) {\n\t\t\tif (WARN(\"LINE_SPACING\",\n\t\t\t\t \"Missing a blank line after declarations\\n\" . $hereprev) &&\n\t\t\t    $fix) {\n\t\t\t\tfix_insert_line($fixlinenr, \"\\+\");\n\t\t\t}\n\t\t}\n\n# check for spaces at the beginning of a line.\n# Exceptions:\n#  1) within comments\n#  2) indented preprocessor commands\n#  3) hanging labels\n\t\tif ($rawline =~ /^\\+ / && $line !~ /^\\+ *(?:$;|#|$Ident:)/)  {\n\t\t\tmy $herevet = \"$here\\n\" . cat_vet($rawline) . \"\\n\";\n\t\t\tif (WARN(\"LEADING_SPACE\",\n\t\t\t\t \"please, no spaces at the start of a line\\n\" . $herevet) &&\n\t\t\t    $fix) {\n\t\t\t\t$fixed[$fixlinenr] =~ s/^\\+([ \\t]+)/\"\\+\" . tabify($1)/e;\n\t\t\t}\n\t\t}\n\n# check we are in a valid C source file if not then ignore this hunk\n\t\tnext if ($realfile !~ /\\.(h|c)$/);\n\n# check for unusual line ending [ or (\n\t\tif ($line =~ /^\\+.*([\\[\\(])\\s*$/) {\n\t\t\tCHK(\"OPEN_ENDED_LINE\",\n\t\t\t    \"Lines should not end with a '$1'\\n\" . $herecurr);\n\t\t}\n\n# check if this appears to be the start function declaration, save the name\n\t\tif ($sline =~ /^\\+\\{\\s*$/ &&\n\t\t    $prevline =~ /^\\+(?:(?:(?:$Storage|$Inline)\\s*)*\\s*$Type\\s*)?($Ident)\\(/) {\n\t\t\t$context_function = $1;\n\t\t}\n\n# check if this appears to be the end of function declaration\n\t\tif ($sline =~ /^\\+\\}\\s*$/) {\n\t\t\tundef $context_function;\n\t\t}\n\n# check indentation of any line with a bare else\n# (but not if it is a multiple line \"if (foo) return bar; else return baz;\")\n# if the previous line is a break or return and is indented 1 tab more...\n\t\tif ($sline =~ /^\\+([\\t]+)(?:}[ \\t]*)?else(?:[ \\t]*{)?\\s*$/) {\n\t\t\tmy $tabs = length($1) + 1;\n\t\t\tif ($prevline =~ /^\\+\\t{$tabs,$tabs}break\\b/ ||\n\t\t\t    ($prevline =~ /^\\+\\t{$tabs,$tabs}return\\b/ &&\n\t\t\t     defined $lines[$linenr] &&\n\t\t\t     $lines[$linenr] !~ /^[ \\+]\\t{$tabs,$tabs}return/)) {\n\t\t\t\tWARN(\"UNNECESSARY_ELSE\",\n\t\t\t\t     \"else is not generally useful after a break or return\\n\" . $hereprev);\n\t\t\t}\n\t\t}\n\n# check indentation of a line with a break;\n# if the previous line is a goto or return and is indented the same # of tabs\n\t\tif ($sline =~ /^\\+([\\t]+)break\\s*;\\s*$/) {\n\t\t\tmy $tabs = $1;\n\t\t\tif ($prevline =~ /^\\+$tabs(?:goto|return)\\b/) {\n\t\t\t\tWARN(\"UNNECESSARY_BREAK\",\n\t\t\t\t     \"break is not useful after a goto or return\\n\" . $hereprev);\n\t\t\t}\n\t\t}\n\n# check for RCS/CVS revision markers\n\t\tif ($rawline =~ /^\\+.*\\$(Revision|Log|Id)(?:\\$|)/) {\n\t\t\tWARN(\"CVS_KEYWORD\",\n\t\t\t     \"CVS style keyword markers, these will _not_ be updated\\n\". $herecurr);\n\t\t}\n\n# check for old HOTPLUG __dev<foo> section markings\n\t\tif ($line =~ /\\b(__dev(init|exit)(data|const|))\\b/) {\n\t\t\tWARN(\"HOTPLUG_SECTION\",\n\t\t\t     \"Using $1 is unnecessary\\n\" . $herecurr);\n\t\t}\n\n# Check for potential 'bare' types\n\t\tmy ($stat, $cond, $line_nr_next, $remain_next, $off_next,\n\t\t    $realline_next);\n#print \"LINE<$line>\\n\";\n\t\tif ($linenr > $suppress_statement &&\n\t\t    $realcnt && $sline =~ /.\\s*\\S/) {\n\t\t\t($stat, $cond, $line_nr_next, $remain_next, $off_next) =\n\t\t\t\tctx_statement_block($linenr, $realcnt, 0);\n\t\t\t$stat =~ s/\\n./\\n /g;\n\t\t\t$cond =~ s/\\n./\\n /g;\n\n#print \"linenr<$linenr> <$stat>\\n\";\n\t\t\t# If this statement has no statement boundaries within\n\t\t\t# it there is no point in retrying a statement scan\n\t\t\t# until we hit end of it.\n\t\t\tmy $frag = $stat; $frag =~ s/;+\\s*$//;\n\t\t\tif ($frag !~ /(?:{|;)/) {\n#print \"skip<$line_nr_next>\\n\";\n\t\t\t\t$suppress_statement = $line_nr_next;\n\t\t\t}\n\n\t\t\t# Find the real next line.\n\t\t\t$realline_next = $line_nr_next;\n\t\t\tif (defined $realline_next &&\n\t\t\t    (!defined $lines[$realline_next - 1] ||\n\t\t\t     substr($lines[$realline_next - 1], $off_next) =~ /^\\s*$/)) {\n\t\t\t\t$realline_next++;\n\t\t\t}\n\n\t\t\tmy $s = $stat;\n\t\t\t$s =~ s/{.*$//s;\n\n\t\t\t# Ignore goto labels.\n\t\t\tif ($s =~ /$Ident:\\*$/s) {\n\n\t\t\t# Ignore functions being called\n\t\t\t} elsif ($s =~ /^.\\s*$Ident\\s*\\(/s) {\n\n\t\t\t} elsif ($s =~ /^.\\s*else\\b/s) {\n\n\t\t\t# declarations always start with types\n\t\t\t} elsif ($prev_values eq 'E' && $s =~ /^.\\s*(?:$Storage\\s+)?(?:$Inline\\s+)?(?:const\\s+)?((?:\\s*$Ident)+?)\\b(?:\\s+$Sparse)?\\s*\\**\\s*(?:$Ident|\\(\\*[^\\)]*\\))(?:\\s*$Modifier)?\\s*(?:;|=|,|\\()/s) {\n\t\t\t\tmy $type = $1;\n\t\t\t\t$type =~ s/\\s+/ /g;\n\t\t\t\tpossible($type, \"A:\" . $s);\n\n\t\t\t# definitions in global scope can only start with types\n\t\t\t} elsif ($s =~ /^.(?:$Storage\\s+)?(?:$Inline\\s+)?(?:const\\s+)?($Ident)\\b\\s*(?!:)/s) {\n\t\t\t\tpossible($1, \"B:\" . $s);\n\t\t\t}\n\n\t\t\t# any (foo ... *) is a pointer cast, and foo is a type\n\t\t\twhile ($s =~ /\\(($Ident)(?:\\s+$Sparse)*[\\s\\*]+\\s*\\)/sg) {\n\t\t\t\tpossible($1, \"C:\" . $s);\n\t\t\t}\n\n\t\t\t# Check for any sort of function declaration.\n\t\t\t# int foo(something bar, other baz);\n\t\t\t# void (*store_gdt)(x86_descr_ptr *);\n\t\t\tif ($prev_values eq 'E' && $s =~ /^(.(?:typedef\\s*)?(?:(?:$Storage|$Inline)\\s*)*\\s*$Type\\s*(?:\\b$Ident|\\(\\*\\s*$Ident\\))\\s*)\\(/s) {\n\t\t\t\tmy ($name_len) = length($1);\n\n\t\t\t\tmy $ctx = $s;\n\t\t\t\tsubstr($ctx, 0, $name_len + 1, '');\n\t\t\t\t$ctx =~ s/\\)[^\\)]*$//;\n\n\t\t\t\tfor my $arg (split(/\\s*,\\s*/, $ctx)) {\n\t\t\t\t\tif ($arg =~ /^(?:const\\s+)?($Ident)(?:\\s+$Sparse)*\\s*\\**\\s*(:?\\b$Ident)?$/s || $arg =~ /^($Ident)$/s) {\n\n\t\t\t\t\t\tpossible($1, \"D:\" . $s);\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\n\t\t}\n\n#\n# Checks which may be anchored in the context.\n#\n\n# Check for switch () and associated case and default\n# statements should be at the same indent.\n\t\tif ($line=~/\\bswitch\\s*\\(.*\\)/) {\n\t\t\tmy $err = '';\n\t\t\tmy $sep = '';\n\t\t\tmy @ctx = ctx_block_outer($linenr, $realcnt);\n\t\t\tshift(@ctx);\n\t\t\tfor my $ctx (@ctx) {\n\t\t\t\tmy ($clen, $cindent) = line_stats($ctx);\n\t\t\t\tif ($ctx =~ /^\\+\\s*(case\\s+|default:)/ &&\n\t\t\t\t\t\t\t$indent != $cindent) {\n\t\t\t\t\t$err .= \"$sep$ctx\\n\";\n\t\t\t\t\t$sep = '';\n\t\t\t\t} else {\n\t\t\t\t\t$sep = \"[...]\\n\";\n\t\t\t\t}\n\t\t\t}\n\t\t\tif ($err ne '') {\n\t\t\t\tERROR(\"SWITCH_CASE_INDENT_LEVEL\",\n\t\t\t\t      \"switch and case should be at the same indent\\n$hereline$err\");\n\t\t\t}\n\t\t}\n\n# if/while/etc brace do not go on next line, unless defining a do while loop,\n# or if that brace on the next line is for something else\n\t\tif ($line =~ /(.*)\\b((?:if|while|for|switch|(?:[a-z_]+|)for_each[a-z_]+)\\s*\\(|do\\b|else\\b)/ && $line !~ /^.\\s*\\#/) {\n\t\t\tmy $pre_ctx = \"$1$2\";\n\n\t\t\tmy ($level, @ctx) = ctx_statement_level($linenr, $realcnt, 0);\n\n\t\t\tif ($line =~ /^\\+\\t{6,}/) {\n\t\t\t\tWARN(\"DEEP_INDENTATION\",\n\t\t\t\t     \"Too many leading tabs - consider code refactoring\\n\" . $herecurr);\n\t\t\t}\n\n\t\t\tmy $ctx_cnt = $realcnt - $#ctx - 1;\n\t\t\tmy $ctx = join(\"\\n\", @ctx);\n\n\t\t\tmy $ctx_ln = $linenr;\n\t\t\tmy $ctx_skip = $realcnt;\n\n\t\t\twhile ($ctx_skip > $ctx_cnt || ($ctx_skip == $ctx_cnt &&\n\t\t\t\t\tdefined $lines[$ctx_ln - 1] &&\n\t\t\t\t\t$lines[$ctx_ln - 1] =~ /^-/)) {\n\t\t\t\t##print \"SKIP<$ctx_skip> CNT<$ctx_cnt>\\n\";\n\t\t\t\t$ctx_skip-- if (!defined $lines[$ctx_ln - 1] || $lines[$ctx_ln - 1] !~ /^-/);\n\t\t\t\t$ctx_ln++;\n\t\t\t}\n\n\t\t\t#print \"realcnt<$realcnt> ctx_cnt<$ctx_cnt>\\n\";\n\t\t\t#print \"pre<$pre_ctx>\\nline<$line>\\nctx<$ctx>\\nnext<$lines[$ctx_ln - 1]>\\n\";\n\n\t\t\tif ($ctx !~ /{\\s*/ && defined($lines[$ctx_ln - 1]) && $lines[$ctx_ln - 1] =~ /^\\+\\s*{/) {\n\t\t\t\tERROR(\"OPEN_BRACE\",\n\t\t\t\t      \"that open brace { should be on the previous line\\n\" .\n\t\t\t\t\t\"$here\\n$ctx\\n$rawlines[$ctx_ln - 1]\\n\");\n\t\t\t}\n\t\t\tif ($level == 0 && $pre_ctx !~ /}\\s*while\\s*\\($/ &&\n\t\t\t    $ctx =~ /\\)\\s*\\;\\s*$/ &&\n\t\t\t    defined $lines[$ctx_ln - 1])\n\t\t\t{\n\t\t\t\tmy ($nlength, $nindent) = line_stats($lines[$ctx_ln - 1]);\n\t\t\t\tif ($nindent > $indent) {\n\t\t\t\t\tWARN(\"TRAILING_SEMICOLON\",\n\t\t\t\t\t     \"trailing semicolon indicates no statements, indent implies otherwise\\n\" .\n\t\t\t\t\t\t\"$here\\n$ctx\\n$rawlines[$ctx_ln - 1]\\n\");\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n# Check relative indent for conditionals and blocks.\n\t\tif ($line =~ /\\b(?:(?:if|while|for|(?:[a-z_]+|)for_each[a-z_]+)\\s*\\(|(?:do|else)\\b)/ && $line !~ /^.\\s*#/ && $line !~ /\\}\\s*while\\s*/) {\n\t\t\t($stat, $cond, $line_nr_next, $remain_next, $off_next) =\n\t\t\t\tctx_statement_block($linenr, $realcnt, 0)\n\t\t\t\t\tif (!defined $stat);\n\t\t\tmy ($s, $c) = ($stat, $cond);\n\n\t\t\tsubstr($s, 0, length($c), '');\n\n\t\t\t# remove inline comments\n\t\t\t$s =~ s/$;/ /g;\n\t\t\t$c =~ s/$;/ /g;\n\n\t\t\t# Find out how long the conditional actually is.\n\t\t\tmy @newlines = ($c =~ /\\n/gs);\n\t\t\tmy $cond_lines = 1 + $#newlines;\n\n\t\t\t# Make sure we remove the line prefixes as we have\n\t\t\t# none on the first line, and are going to readd them\n\t\t\t# where necessary.\n\t\t\t$s =~ s/\\n./\\n/gs;\n\t\t\twhile ($s =~ /\\n\\s+\\\\\\n/) {\n\t\t\t\t$cond_lines += $s =~ s/\\n\\s+\\\\\\n/\\n/g;\n\t\t\t}\n\n\t\t\t# We want to check the first line inside the block\n\t\t\t# starting at the end of the conditional, so remove:\n\t\t\t#  1) any blank line termination\n\t\t\t#  2) any opening brace { on end of the line\n\t\t\t#  3) any do (...) {\n\t\t\tmy $continuation = 0;\n\t\t\tmy $check = 0;\n\t\t\t$s =~ s/^.*\\bdo\\b//;\n\t\t\t$s =~ s/^\\s*{//;\n\t\t\tif ($s =~ s/^\\s*\\\\//) {\n\t\t\t\t$continuation = 1;\n\t\t\t}\n\t\t\tif ($s =~ s/^\\s*?\\n//) {\n\t\t\t\t$check = 1;\n\t\t\t\t$cond_lines++;\n\t\t\t}\n\n\t\t\t# Also ignore a loop construct at the end of a\n\t\t\t# preprocessor statement.\n\t\t\tif (($prevline =~ /^.\\s*#\\s*define\\s/ ||\n\t\t\t    $prevline =~ /\\\\\\s*$/) && $continuation == 0) {\n\t\t\t\t$check = 0;\n\t\t\t}\n\n\t\t\tmy $cond_ptr = -1;\n\t\t\t$continuation = 0;\n\t\t\twhile ($cond_ptr != $cond_lines) {\n\t\t\t\t$cond_ptr = $cond_lines;\n\n\t\t\t\t# If we see an #else/#elif then the code\n\t\t\t\t# is not linear.\n\t\t\t\tif ($s =~ /^\\s*\\#\\s*(?:else|elif)/) {\n\t\t\t\t\t$check = 0;\n\t\t\t\t}\n\n\t\t\t\t# Ignore:\n\t\t\t\t#  1) blank lines, they should be at 0,\n\t\t\t\t#  2) preprocessor lines, and\n\t\t\t\t#  3) labels.\n\t\t\t\tif ($continuation ||\n\t\t\t\t    $s =~ /^\\s*?\\n/ ||\n\t\t\t\t    $s =~ /^\\s*#\\s*?/ ||\n\t\t\t\t    $s =~ /^\\s*$Ident\\s*:/) {\n\t\t\t\t\t$continuation = ($s =~ /^.*?\\\\\\n/) ? 1 : 0;\n\t\t\t\t\tif ($s =~ s/^.*?\\n//) {\n\t\t\t\t\t\t$cond_lines++;\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\n\t\t\tmy (undef, $sindent) = line_stats(\"+\" . $s);\n\t\t\tmy $stat_real = raw_line($linenr, $cond_lines);\n\n\t\t\t# Check if either of these lines are modified, else\n\t\t\t# this is not this patch's fault.\n\t\t\tif (!defined($stat_real) ||\n\t\t\t    $stat !~ /^\\+/ && $stat_real !~ /^\\+/) {\n\t\t\t\t$check = 0;\n\t\t\t}\n\t\t\tif (defined($stat_real) && $cond_lines > 1) {\n\t\t\t\t$stat_real = \"[...]\\n$stat_real\";\n\t\t\t}\n\n\t\t\t#print \"line<$line> prevline<$prevline> indent<$indent> sindent<$sindent> check<$check> continuation<$continuation> s<$s> cond_lines<$cond_lines> stat_real<$stat_real> stat<$stat>\\n\";\n\n\t\t\tif ($check && $s ne '' &&\n\t\t\t    (($sindent % $tabsize) != 0 ||\n\t\t\t     ($sindent < $indent) ||\n\t\t\t     ($sindent == $indent &&\n\t\t\t      ($s !~ /^\\s*(?:\\}|\\{|else\\b)/)) ||\n\t\t\t     ($sindent > $indent + $tabsize))) {\n\t\t\t\tWARN(\"SUSPECT_CODE_INDENT\",\n\t\t\t\t     \"suspect code indent for conditional statements ($indent, $sindent)\\n\" . $herecurr . \"$stat_real\\n\");\n\t\t\t}\n\t\t}\n\n\t\t# Track the 'values' across context and added lines.\n\t\tmy $opline = $line; $opline =~ s/^./ /;\n\t\tmy ($curr_values, $curr_vars) =\n\t\t\t\tannotate_values($opline . \"\\n\", $prev_values);\n\t\t$curr_values = $prev_values . $curr_values;\n\t\tif ($dbg_values) {\n\t\t\tmy $outline = $opline; $outline =~ s/\\t/ /g;\n\t\t\tprint \"$linenr > .$outline\\n\";\n\t\t\tprint \"$linenr > $curr_values\\n\";\n\t\t\tprint \"$linenr >  $curr_vars\\n\";\n\t\t}\n\t\t$prev_values = substr($curr_values, -1);\n\n#ignore lines not being added\n\t\tnext if ($line =~ /^[^\\+]/);\n\n# check for dereferences that span multiple lines\n\t\tif ($prevline =~ /^\\+.*$Lval\\s*(?:\\.|->)\\s*$/ &&\n\t\t    $line =~ /^\\+\\s*(?!\\#\\s*(?!define\\s+|if))\\s*$Lval/) {\n\t\t\t$prevline =~ /($Lval\\s*(?:\\.|->))\\s*$/;\n\t\t\tmy $ref = $1;\n\t\t\t$line =~ /^.\\s*($Lval)/;\n\t\t\t$ref .= $1;\n\t\t\t$ref =~ s/\\s//g;\n\t\t\tWARN(\"MULTILINE_DEREFERENCE\",\n\t\t\t     \"Avoid multiple line dereference - prefer '$ref'\\n\" . $hereprev);\n\t\t}\n\n# check for declarations of signed or unsigned without int\n\t\twhile ($line =~ m{\\b($Declare)\\s*(?!char\\b|short\\b|int\\b|long\\b)\\s*($Ident)?\\s*[=,;\\[\\)\\(]}g) {\n\t\t\tmy $type = $1;\n\t\t\tmy $var = $2;\n\t\t\t$var = \"\" if (!defined $var);\n\t\t\tif ($type =~ /^(?:(?:$Storage|$Inline|$Attribute)\\s+)*((?:un)?signed)((?:\\s*\\*)*)\\s*$/) {\n\t\t\t\tmy $sign = $1;\n\t\t\t\tmy $pointer = $2;\n\n\t\t\t\t$pointer = \"\" if (!defined $pointer);\n\n\t\t\t\tif (WARN(\"UNSPECIFIED_INT\",\n\t\t\t\t\t \"Prefer '\" . trim($sign) . \" int\" . rtrim($pointer) . \"' to bare use of '$sign\" . rtrim($pointer) . \"'\\n\" . $herecurr) &&\n\t\t\t\t    $fix) {\n\t\t\t\t\tmy $decl = trim($sign) . \" int \";\n\t\t\t\t\tmy $comp_pointer = $pointer;\n\t\t\t\t\t$comp_pointer =~ s/\\s//g;\n\t\t\t\t\t$decl .= $comp_pointer;\n\t\t\t\t\t$decl = rtrim($decl) if ($var eq \"\");\n\t\t\t\t\t$fixed[$fixlinenr] =~ s@\\b$sign\\s*\\Q$pointer\\E\\s*$var\\b@$decl$var@;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n# TEST: allow direct testing of the type matcher.\n\t\tif ($dbg_type) {\n\t\t\tif ($line =~ /^.\\s*$Declare\\s*$/) {\n\t\t\t\tERROR(\"TEST_TYPE\",\n\t\t\t\t      \"TEST: is type\\n\" . $herecurr);\n\t\t\t} elsif ($dbg_type > 1 && $line =~ /^.+($Declare)/) {\n\t\t\t\tERROR(\"TEST_NOT_TYPE\",\n\t\t\t\t      \"TEST: is not type ($1 is)\\n\". $herecurr);\n\t\t\t}\n\t\t\tnext;\n\t\t}\n# TEST: allow direct testing of the attribute matcher.\n\t\tif ($dbg_attr) {\n\t\t\tif ($line =~ /^.\\s*$Modifier\\s*$/) {\n\t\t\t\tERROR(\"TEST_ATTR\",\n\t\t\t\t      \"TEST: is attr\\n\" . $herecurr);\n\t\t\t} elsif ($dbg_attr > 1 && $line =~ /^.+($Modifier)/) {\n\t\t\t\tERROR(\"TEST_NOT_ATTR\",\n\t\t\t\t      \"TEST: is not attr ($1 is)\\n\". $herecurr);\n\t\t\t}\n\t\t\tnext;\n\t\t}\n\n# check for initialisation to aggregates open brace on the next line\n\t\tif ($line =~ /^.\\s*{/ &&\n\t\t    $prevline =~ /(?:^|[^=])=\\s*$/) {\n\t\t\tif (ERROR(\"OPEN_BRACE\",\n\t\t\t\t  \"that open brace { should be on the previous line\\n\" . $hereprev) &&\n\t\t\t    $fix && $prevline =~ /^\\+/ && $line =~ /^\\+/) {\n\t\t\t\tfix_delete_line($fixlinenr - 1, $prevrawline);\n\t\t\t\tfix_delete_line($fixlinenr, $rawline);\n\t\t\t\tmy $fixedline = $prevrawline;\n\t\t\t\t$fixedline =~ s/\\s*=\\s*$/ = {/;\n\t\t\t\tfix_insert_line($fixlinenr, $fixedline);\n\t\t\t\t$fixedline = $line;\n\t\t\t\t$fixedline =~ s/^(.\\s*)\\{\\s*/$1/;\n\t\t\t\tfix_insert_line($fixlinenr, $fixedline);\n\t\t\t}\n\t\t}\n\n#\n# Checks which are anchored on the added line.\n#\n\n# check for malformed paths in #include statements (uses RAW line)\n\t\tif ($rawline =~ m{^.\\s*\\#\\s*include\\s+[<\"](.*)[\">]}) {\n\t\t\tmy $path = $1;\n\t\t\tif ($path =~ m{//}) {\n\t\t\t\tERROR(\"MALFORMED_INCLUDE\",\n\t\t\t\t      \"malformed #include filename\\n\" . $herecurr);\n\t\t\t}\n\t\t\tif ($path =~ \"^uapi/\" && $realfile =~ m@\\binclude/uapi/@) {\n\t\t\t\tERROR(\"UAPI_INCLUDE\",\n\t\t\t\t      \"No #include in ...include/uapi/... should use a uapi/ path prefix\\n\" . $herecurr);\n\t\t\t}\n\t\t}\n\n# no C99 // comments\n\t\tif ($line =~ m{//}) {\n\t\t\tif (ERROR(\"C99_COMMENTS\",\n\t\t\t\t  \"do not use C99 // comments\\n\" . $herecurr) &&\n\t\t\t    $fix) {\n\t\t\t\tmy $line = $fixed[$fixlinenr];\n\t\t\t\tif ($line =~ /\\/\\/(.*)$/) {\n\t\t\t\t\tmy $comment = trim($1);\n\t\t\t\t\t$fixed[$fixlinenr] =~ s@\\/\\/(.*)$@/\\* $comment \\*/@;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t\t# Remove C99 comments.\n\t\t$line =~ s@//.*@@;\n\t\t$opline =~ s@//.*@@;\n\n# EXPORT_SYMBOL should immediately follow the thing it is exporting, consider\n# the whole statement.\n#print \"APW <$lines[$realline_next - 1]>\\n\";\n\t\tif (defined $realline_next &&\n\t\t    exists $lines[$realline_next - 1] &&\n\t\t    !defined $suppress_export{$realline_next} &&\n\t\t    ($lines[$realline_next - 1] =~ /EXPORT_SYMBOL.*\\((.*)\\)/ ||\n\t\t     $lines[$realline_next - 1] =~ /EXPORT_UNUSED_SYMBOL.*\\((.*)\\)/)) {\n\t\t\t# Handle definitions which produce identifiers with\n\t\t\t# a prefix:\n\t\t\t#   XXX(foo);\n\t\t\t#   EXPORT_SYMBOL(something_foo);\n\t\t\tmy $name = $1;\n\t\t\tif ($stat =~ /^(?:.\\s*}\\s*\\n)?.([A-Z_]+)\\s*\\(\\s*($Ident)/ &&\n\t\t\t    $name =~ /^${Ident}_$2/) {\n#print \"FOO C name<$name>\\n\";\n\t\t\t\t$suppress_export{$realline_next} = 1;\n\n\t\t\t} elsif ($stat !~ /(?:\n\t\t\t\t\\n.}\\s*$|\n\t\t\t\t^.DEFINE_$Ident\\(\\Q$name\\E\\)|\n\t\t\t\t^.DECLARE_$Ident\\(\\Q$name\\E\\)|\n\t\t\t\t^.LIST_HEAD\\(\\Q$name\\E\\)|\n\t\t\t\t^.(?:$Storage\\s+)?$Type\\s*\\(\\s*\\*\\s*\\Q$name\\E\\s*\\)\\s*\\(|\n\t\t\t\t\\b\\Q$name\\E(?:\\s+$Attribute)*\\s*(?:;|=|\\[|\\()\n\t\t\t    )/x) {\n#print \"FOO A<$lines[$realline_next - 1]> stat<$stat> name<$name>\\n\";\n\t\t\t\t$suppress_export{$realline_next} = 2;\n\t\t\t} else {\n\t\t\t\t$suppress_export{$realline_next} = 1;\n\t\t\t}\n\t\t}\n\t\tif (!defined $suppress_export{$linenr} &&\n\t\t    $prevline =~ /^.\\s*$/ &&\n\t\t    ($line =~ /EXPORT_SYMBOL.*\\((.*)\\)/ ||\n\t\t     $line =~ /EXPORT_UNUSED_SYMBOL.*\\((.*)\\)/)) {\n#print \"FOO B <$lines[$linenr - 1]>\\n\";\n\t\t\t$suppress_export{$linenr} = 2;\n\t\t}\n\t\tif (defined $suppress_export{$linenr} &&\n\t\t    $suppress_export{$linenr} == 2) {\n\t\t\tWARN(\"EXPORT_SYMBOL\",\n\t\t\t     \"EXPORT_SYMBOL(foo); should immediately follow its function/variable\\n\" . $herecurr);\n\t\t}\n\n# check for global initialisers.\n\t\tif ($line =~ /^\\+$Type\\s*$Ident(?:\\s+$Modifier)*\\s*=\\s*($zero_initializer)\\s*;/) {\n\t\t\tif (ERROR(\"GLOBAL_INITIALISERS\",\n\t\t\t\t  \"do not initialise globals to $1\\n\" . $herecurr) &&\n\t\t\t    $fix) {\n\t\t\t\t$fixed[$fixlinenr] =~ s/(^.$Type\\s*$Ident(?:\\s+$Modifier)*)\\s*=\\s*$zero_initializer\\s*;/$1;/;\n\t\t\t}\n\t\t}\n# check for static initialisers.\n\t\tif ($line =~ /^\\+.*\\bstatic\\s.*=\\s*($zero_initializer)\\s*;/) {\n\t\t\tif (ERROR(\"INITIALISED_STATIC\",\n\t\t\t\t  \"do not initialise statics to $1\\n\" .\n\t\t\t\t      $herecurr) &&\n\t\t\t    $fix) {\n\t\t\t\t$fixed[$fixlinenr] =~ s/(\\bstatic\\s.*?)\\s*=\\s*$zero_initializer\\s*;/$1;/;\n\t\t\t}\n\t\t}\n\n# check for misordered declarations of char/short/int/long with signed/unsigned\n\t\twhile ($sline =~ m{(\\b$TypeMisordered\\b)}g) {\n\t\t\tmy $tmp = trim($1);\n\t\t\tWARN(\"MISORDERED_TYPE\",\n\t\t\t     \"type '$tmp' should be specified in [[un]signed] [short|int|long|long long] order\\n\" . $herecurr);\n\t\t}\n\n# check for unnecessary <signed> int declarations of short/long/long long\n\t\twhile ($sline =~ m{\\b($TypeMisordered(\\s*\\*)*|$C90_int_types)\\b}g) {\n\t\t\tmy $type = trim($1);\n\t\t\tnext if ($type !~ /\\bint\\b/);\n\t\t\tnext if ($type !~ /\\b(?:short|long\\s+long|long)\\b/);\n\t\t\tmy $new_type = $type;\n\t\t\t$new_type =~ s/\\b\\s*int\\s*\\b/ /;\n\t\t\t$new_type =~ s/\\b\\s*(?:un)?signed\\b\\s*/ /;\n\t\t\t$new_type =~ s/^const\\s+//;\n\t\t\t$new_type = \"unsigned $new_type\" if ($type =~ /\\bunsigned\\b/);\n\t\t\t$new_type = \"const $new_type\" if ($type =~ /^const\\b/);\n\t\t\t$new_type =~ s/\\s+/ /g;\n\t\t\t$new_type = trim($new_type);\n\t\t\tif (WARN(\"UNNECESSARY_INT\",\n\t\t\t\t \"Prefer '$new_type' over '$type' as the int is unnecessary\\n\" . $herecurr) &&\n\t\t\t    $fix) {\n\t\t\t\t$fixed[$fixlinenr] =~ s/\\b\\Q$type\\E\\b/$new_type/;\n\t\t\t}\n\t\t}\n\n# check for static const char * arrays.\n\t\tif ($line =~ /\\bstatic\\s+const\\s+char\\s*\\*\\s*(\\w+)\\s*\\[\\s*\\]\\s*=\\s*/) {\n\t\t\tWARN(\"STATIC_CONST_CHAR_ARRAY\",\n\t\t\t     \"static const char * array should probably be static const char * const\\n\" .\n\t\t\t\t$herecurr);\n\t\t}\n\n# check for initialized const char arrays that should be static const\n\t\tif ($line =~ /^\\+\\s*const\\s+(char|unsigned\\s+char|_*u8|(?:[us]_)?int8_t)\\s+\\w+\\s*\\[\\s*(?:\\w+\\s*)?\\]\\s*=\\s*\"/) {\n\t\t\tif (WARN(\"STATIC_CONST_CHAR_ARRAY\",\n\t\t\t\t \"const array should probably be static const\\n\" . $herecurr) &&\n\t\t\t    $fix) {\n\t\t\t\t$fixed[$fixlinenr] =~ s/(^.\\s*)const\\b/${1}static const/;\n\t\t\t}\n\t\t}\n\n# check for static char foo[] = \"bar\" declarations.\n\t\tif ($line =~ /\\bstatic\\s+char\\s+(\\w+)\\s*\\[\\s*\\]\\s*=\\s*\"/) {\n\t\t\tWARN(\"STATIC_CONST_CHAR_ARRAY\",\n\t\t\t     \"static char array declaration should probably be static const char\\n\" .\n\t\t\t\t$herecurr);\n\t\t}\n\n# check for const <foo> const where <foo> is not a pointer or array type\n\t\tif ($sline =~ /\\bconst\\s+($BasicType)\\s+const\\b/) {\n\t\t\tmy $found = $1;\n\t\t\tif ($sline =~ /\\bconst\\s+\\Q$found\\E\\s+const\\b\\s*\\*/) {\n\t\t\t\tWARN(\"CONST_CONST\",\n\t\t\t\t     \"'const $found const *' should probably be 'const $found * const'\\n\" . $herecurr);\n\t\t\t} elsif ($sline !~ /\\bconst\\s+\\Q$found\\E\\s+const\\s+\\w+\\s*\\[/) {\n\t\t\t\tWARN(\"CONST_CONST\",\n\t\t\t\t     \"'const $found const' should probably be 'const $found'\\n\" . $herecurr);\n\t\t\t}\n\t\t}\n\n# check for non-global char *foo[] = {\"bar\", ...} declarations.\n\t\tif ($line =~ /^.\\s+(?:static\\s+|const\\s+)?char\\s+\\*\\s*\\w+\\s*\\[\\s*\\]\\s*=\\s*\\{/) {\n\t\t\tWARN(\"STATIC_CONST_CHAR_ARRAY\",\n\t\t\t     \"char * array declaration might be better as static const\\n\" .\n\t\t\t\t$herecurr);\n               }\n\n# check for sizeof(foo)/sizeof(foo[0]) that could be ARRAY_SIZE(foo)\n\t\tif ($line =~ m@\\bsizeof\\s*\\(\\s*($Lval)\\s*\\)@) {\n\t\t\tmy $array = $1;\n\t\t\tif ($line =~ m@\\b(sizeof\\s*\\(\\s*\\Q$array\\E\\s*\\)\\s*/\\s*sizeof\\s*\\(\\s*\\Q$array\\E\\s*\\[\\s*0\\s*\\]\\s*\\))@) {\n\t\t\t\tmy $array_div = $1;\n\t\t\t\tif (WARN(\"ARRAY_SIZE\",\n\t\t\t\t\t \"Prefer ARRAY_SIZE($array)\\n\" . $herecurr) &&\n\t\t\t\t    $fix) {\n\t\t\t\t\t$fixed[$fixlinenr] =~ s/\\Q$array_div\\E/ARRAY_SIZE($array)/;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n# check for function declarations without arguments like \"int foo()\"\n\t\tif ($line =~ /(\\b$Type\\s*$Ident)\\s*\\(\\s*\\)/) {\n\t\t\tif (ERROR(\"FUNCTION_WITHOUT_ARGS\",\n\t\t\t\t  \"Bad function definition - $1() should probably be $1(void)\\n\" . $herecurr) &&\n\t\t\t    $fix) {\n\t\t\t\t$fixed[$fixlinenr] =~ s/(\\b($Type)\\s+($Ident))\\s*\\(\\s*\\)/$2 $3(void)/;\n\t\t\t}\n\t\t}\n\n# check for new typedefs, only function parameters and sparse annotations\n# make sense.\n\t\tif ($line =~ /\\btypedef\\s/ &&\n\t\t    $line !~ /\\btypedef\\s+$Type\\s*\\(\\s*\\*?$Ident\\s*\\)\\s*\\(/ &&\n\t\t    $line !~ /\\btypedef\\s+$Type\\s+$Ident\\s*\\(/ &&\n\t\t    $line !~ /\\b$typeTypedefs\\b/ &&\n\t\t    $line !~ /\\b__bitwise\\b/) {\n\t\t\tWARN(\"NEW_TYPEDEFS\",\n\t\t\t     \"do not add new typedefs\\n\" . $herecurr);\n\t\t}\n\n# * goes on variable not on type\n\t\t# (char*[ const])\n\t\twhile ($line =~ m{(\\($NonptrType(\\s*(?:$Modifier\\b\\s*|\\*\\s*)+)\\))}g) {\n\t\t\t#print \"AA<$1>\\n\";\n\t\t\tmy ($ident, $from, $to) = ($1, $2, $2);\n\n\t\t\t# Should start with a space.\n\t\t\t$to =~ s/^(\\S)/ $1/;\n\t\t\t# Should not end with a space.\n\t\t\t$to =~ s/\\s+$//;\n\t\t\t# '*'s should not have spaces between.\n\t\t\twhile ($to =~ s/\\*\\s+\\*/\\*\\*/) {\n\t\t\t}\n\n##\t\t\tprint \"1: from<$from> to<$to> ident<$ident>\\n\";\n\t\t\tif ($from ne $to) {\n\t\t\t\tif (ERROR(\"POINTER_LOCATION\",\n\t\t\t\t\t  \"\\\"(foo$from)\\\" should be \\\"(foo$to)\\\"\\n\" .  $herecurr) &&\n\t\t\t\t    $fix) {\n\t\t\t\t\tmy $sub_from = $ident;\n\t\t\t\t\tmy $sub_to = $ident;\n\t\t\t\t\t$sub_to =~ s/\\Q$from\\E/$to/;\n\t\t\t\t\t$fixed[$fixlinenr] =~\n\t\t\t\t\t    s@\\Q$sub_from\\E@$sub_to@;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t\twhile ($line =~ m{(\\b$NonptrType(\\s*(?:$Modifier\\b\\s*|\\*\\s*)+)($Ident))}g) {\n\t\t\t#print \"BB<$1>\\n\";\n\t\t\tmy ($match, $from, $to, $ident) = ($1, $2, $2, $3);\n\n\t\t\t# Should start with a space.\n\t\t\t$to =~ s/^(\\S)/ $1/;\n\t\t\t# Should not end with a space.\n\t\t\t$to =~ s/\\s+$//;\n\t\t\t# '*'s should not have spaces between.\n\t\t\twhile ($to =~ s/\\*\\s+\\*/\\*\\*/) {\n\t\t\t}\n\t\t\t# Modifiers should have spaces.\n\t\t\t$to =~ s/(\\b$Modifier$)/$1 /;\n\n##\t\t\tprint \"2: from<$from> to<$to> ident<$ident>\\n\";\n\t\t\tif ($from ne $to && $ident !~ /^$Modifier$/) {\n\t\t\t\tif (ERROR(\"POINTER_LOCATION\",\n\t\t\t\t\t  \"\\\"foo${from}bar\\\" should be \\\"foo${to}bar\\\"\\n\" .  $herecurr) &&\n\t\t\t\t    $fix) {\n\n\t\t\t\t\tmy $sub_from = $match;\n\t\t\t\t\tmy $sub_to = $match;\n\t\t\t\t\t$sub_to =~ s/\\Q$from\\E/$to/;\n\t\t\t\t\t$fixed[$fixlinenr] =~\n\t\t\t\t\t    s@\\Q$sub_from\\E@$sub_to@;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n# avoid BUG() or BUG_ON()\n\t\tif ($line =~ /\\b(?:BUG|BUG_ON)\\b/) {\n\t\t\tmy $msg_level = \\&WARN;\n\t\t\t$msg_level = \\&CHK if ($file);\n\t\t\t&{$msg_level}(\"AVOID_BUG\",\n\t\t\t\t      \"Avoid crashing the kernel - try using WARN_ON & recovery code rather than BUG() or BUG_ON()\\n\" . $herecurr);\n\t\t}\n\n# avoid LINUX_VERSION_CODE\n\t\tif ($line =~ /\\bLINUX_VERSION_CODE\\b/) {\n\t\t\tWARN(\"LINUX_VERSION_CODE\",\n\t\t\t     \"LINUX_VERSION_CODE should be avoided, code should be for the version to which it is merged\\n\" . $herecurr);\n\t\t}\n\n# check for uses of printk_ratelimit\n\t\tif ($line =~ /\\bprintk_ratelimit\\s*\\(/) {\n\t\t\tWARN(\"PRINTK_RATELIMITED\",\n\t\t\t     \"Prefer printk_ratelimited or pr_<level>_ratelimited to printk_ratelimit\\n\" . $herecurr);\n\t\t}\n\n# printk should use KERN_* levels\n\t\tif ($line =~ /\\bprintk\\s*\\(\\s*(?!KERN_[A-Z]+\\b)/) {\n\t\t\tWARN(\"PRINTK_WITHOUT_KERN_LEVEL\",\n\t\t\t     \"printk() should include KERN_<LEVEL> facility level\\n\" . $herecurr);\n\t\t}\n\n\t\tif ($line =~ /\\bprintk\\s*\\(\\s*KERN_([A-Z]+)/) {\n\t\t\tmy $orig = $1;\n\t\t\tmy $level = lc($orig);\n\t\t\t$level = \"warn\" if ($level eq \"warning\");\n\t\t\tmy $level2 = $level;\n\t\t\t$level2 = \"dbg\" if ($level eq \"debug\");\n\t\t\tWARN(\"PREFER_PR_LEVEL\",\n\t\t\t     \"Prefer [subsystem eg: netdev]_$level2([subsystem]dev, ... then dev_$level2(dev, ... then pr_$level(...  to printk(KERN_$orig ...\\n\" . $herecurr);\n\t\t}\n\n\t\tif ($line =~ /\\bdev_printk\\s*\\(\\s*KERN_([A-Z]+)/) {\n\t\t\tmy $orig = $1;\n\t\t\tmy $level = lc($orig);\n\t\t\t$level = \"warn\" if ($level eq \"warning\");\n\t\t\t$level = \"dbg\" if ($level eq \"debug\");\n\t\t\tWARN(\"PREFER_DEV_LEVEL\",\n\t\t\t     \"Prefer dev_$level(... to dev_printk(KERN_$orig, ...\\n\" . $herecurr);\n\t\t}\n\n# ENOSYS means \"bad syscall nr\" and nothing else.  This will have a small\n# number of false positives, but assembly files are not checked, so at\n# least the arch entry code will not trigger this warning.\n\t\tif ($line =~ /\\bENOSYS\\b/) {\n\t\t\tWARN(\"ENOSYS\",\n\t\t\t     \"ENOSYS means 'invalid syscall nr' and nothing else\\n\" . $herecurr);\n\t\t}\n\n# ENOTSUPP is not a standard error code and should be avoided in new patches.\n# Folks usually mean EOPNOTSUPP (also called ENOTSUP), when they type ENOTSUPP.\n# Similarly to ENOSYS warning a small number of false positives is expected.\n\t\tif (!$file && $line =~ /\\bENOTSUPP\\b/) {\n\t\t\tif (WARN(\"ENOTSUPP\",\n\t\t\t\t \"ENOTSUPP is not a SUSV4 error code, prefer EOPNOTSUPP\\n\" . $herecurr) &&\n\t\t\t    $fix) {\n\t\t\t\t$fixed[$fixlinenr] =~ s/\\bENOTSUPP\\b/EOPNOTSUPP/;\n\t\t\t}\n\t\t}\n\n# function brace can't be on same line, except for #defines of do while,\n# or if closed on same line\n\t\tif ($perl_version_ok &&\n\t\t    $sline =~ /$Type\\s*$Ident\\s*$balanced_parens\\s*\\{/ &&\n\t\t    $sline !~ /\\#\\s*define\\b.*do\\s*\\{/ &&\n\t\t    $sline !~ /}/) {\n\t\t\tif (ERROR(\"OPEN_BRACE\",\n\t\t\t\t  \"open brace '{' following function definitions go on the next line\\n\" . $herecurr) &&\n\t\t\t    $fix) {\n\t\t\t\tfix_delete_line($fixlinenr, $rawline);\n\t\t\t\tmy $fixed_line = $rawline;\n\t\t\t\t$fixed_line =~ /(^..*$Type\\s*$Ident\\(.*\\)\\s*){(.*)$/;\n\t\t\t\tmy $line1 = $1;\n\t\t\t\tmy $line2 = $2;\n\t\t\t\tfix_insert_line($fixlinenr, ltrim($line1));\n\t\t\t\tfix_insert_line($fixlinenr, \"\\+{\");\n\t\t\t\tif ($line2 !~ /^\\s*$/) {\n\t\t\t\t\tfix_insert_line($fixlinenr, \"\\+\\t\" . trim($line2));\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n# open braces for enum, union and struct go on the same line.\n\t\tif ($line =~ /^.\\s*{/ &&\n\t\t    $prevline =~ /^.\\s*(?:typedef\\s+)?(enum|union|struct)(?:\\s+$Ident)?\\s*$/) {\n\t\t\tif (ERROR(\"OPEN_BRACE\",\n\t\t\t\t  \"open brace '{' following $1 go on the same line\\n\" . $hereprev) &&\n\t\t\t    $fix && $prevline =~ /^\\+/ && $line =~ /^\\+/) {\n\t\t\t\tfix_delete_line($fixlinenr - 1, $prevrawline);\n\t\t\t\tfix_delete_line($fixlinenr, $rawline);\n\t\t\t\tmy $fixedline = rtrim($prevrawline) . \" {\";\n\t\t\t\tfix_insert_line($fixlinenr, $fixedline);\n\t\t\t\t$fixedline = $rawline;\n\t\t\t\t$fixedline =~ s/^(.\\s*)\\{\\s*/$1\\t/;\n\t\t\t\tif ($fixedline !~ /^\\+\\s*$/) {\n\t\t\t\t\tfix_insert_line($fixlinenr, $fixedline);\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n# missing space after union, struct or enum definition\n\t\tif ($line =~ /^.\\s*(?:typedef\\s+)?(enum|union|struct)(?:\\s+$Ident){1,2}[=\\{]/) {\n\t\t\tif (WARN(\"SPACING\",\n\t\t\t\t \"missing space after $1 definition\\n\" . $herecurr) &&\n\t\t\t    $fix) {\n\t\t\t\t$fixed[$fixlinenr] =~\n\t\t\t\t    s/^(.\\s*(?:typedef\\s+)?(?:enum|union|struct)(?:\\s+$Ident){1,2})([=\\{])/$1 $2/;\n\t\t\t}\n\t\t}\n\n# Function pointer declarations\n# check spacing between type, funcptr, and args\n# canonical declaration is \"type (*funcptr)(args...)\"\n\t\tif ($line =~ /^.\\s*($Declare)\\((\\s*)\\*(\\s*)($Ident)(\\s*)\\)(\\s*)\\(/) {\n\t\t\tmy $declare = $1;\n\t\t\tmy $pre_pointer_space = $2;\n\t\t\tmy $post_pointer_space = $3;\n\t\t\tmy $funcname = $4;\n\t\t\tmy $post_funcname_space = $5;\n\t\t\tmy $pre_args_space = $6;\n\n# the $Declare variable will capture all spaces after the type\n# so check it for a missing trailing missing space but pointer return types\n# don't need a space so don't warn for those.\n\t\t\tmy $post_declare_space = \"\";\n\t\t\tif ($declare =~ /(\\s+)$/) {\n\t\t\t\t$post_declare_space = $1;\n\t\t\t\t$declare = rtrim($declare);\n\t\t\t}\n\t\t\tif ($declare !~ /\\*$/ && $post_declare_space =~ /^$/) {\n\t\t\t\tWARN(\"SPACING\",\n\t\t\t\t     \"missing space after return type\\n\" . $herecurr);\n\t\t\t\t$post_declare_space = \" \";\n\t\t\t}\n\n# unnecessary space \"type  (*funcptr)(args...)\"\n# This test is not currently implemented because these declarations are\n# equivalent to\n#\tint  foo(int bar, ...)\n# and this is form shouldn't/doesn't generate a checkpatch warning.\n#\n#\t\t\telsif ($declare =~ /\\s{2,}$/) {\n#\t\t\t\tWARN(\"SPACING\",\n#\t\t\t\t     \"Multiple spaces after return type\\n\" . $herecurr);\n#\t\t\t}\n\n# unnecessary space \"type ( *funcptr)(args...)\"\n\t\t\tif (defined $pre_pointer_space &&\n\t\t\t    $pre_pointer_space =~ /^\\s/) {\n\t\t\t\tWARN(\"SPACING\",\n\t\t\t\t     \"Unnecessary space after function pointer open parenthesis\\n\" . $herecurr);\n\t\t\t}\n\n# unnecessary space \"type (* funcptr)(args...)\"\n\t\t\tif (defined $post_pointer_space &&\n\t\t\t    $post_pointer_space =~ /^\\s/) {\n\t\t\t\tWARN(\"SPACING\",\n\t\t\t\t     \"Unnecessary space before function pointer name\\n\" . $herecurr);\n\t\t\t}\n\n# unnecessary space \"type (*funcptr )(args...)\"\n\t\t\tif (defined $post_funcname_space &&\n\t\t\t    $post_funcname_space =~ /^\\s/) {\n\t\t\t\tWARN(\"SPACING\",\n\t\t\t\t     \"Unnecessary space after function pointer name\\n\" . $herecurr);\n\t\t\t}\n\n# unnecessary space \"type (*funcptr) (args...)\"\n\t\t\tif (defined $pre_args_space &&\n\t\t\t    $pre_args_space =~ /^\\s/) {\n\t\t\t\tWARN(\"SPACING\",\n\t\t\t\t     \"Unnecessary space before function pointer arguments\\n\" . $herecurr);\n\t\t\t}\n\n\t\t\tif (show_type(\"SPACING\") && $fix) {\n\t\t\t\t$fixed[$fixlinenr] =~\n\t\t\t\t    s/^(.\\s*)$Declare\\s*\\(\\s*\\*\\s*$Ident\\s*\\)\\s*\\(/$1 . $declare . $post_declare_space . '(*' . $funcname . ')('/ex;\n\t\t\t}\n\t\t}\n\n# check for spacing round square brackets; allowed:\n#  1. with a type on the left -- int [] a;\n#  2. at the beginning of a line for slice initialisers -- [0...10] = 5,\n#  3. inside a curly brace -- = { [0...10] = 5 }\n\t\twhile ($line =~ /(.*?\\s)\\[/g) {\n\t\t\tmy ($where, $prefix) = ($-[1], $1);\n\t\t\tif ($prefix !~ /$Type\\s+$/ &&\n\t\t\t    ($where != 0 || $prefix !~ /^.\\s+$/) &&\n\t\t\t    $prefix !~ /[{,:]\\s+$/) {\n\t\t\t\tif (ERROR(\"BRACKET_SPACE\",\n\t\t\t\t\t  \"space prohibited before open square bracket '['\\n\" . $herecurr) &&\n\t\t\t\t    $fix) {\n\t\t\t\t    $fixed[$fixlinenr] =~\n\t\t\t\t\ts/^(\\+.*?)\\s+\\[/$1\\[/;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n# check for spaces between functions and their parentheses.\n\t\twhile ($line =~ /($Ident)\\s+\\(/g) {\n\t\t\tmy $name = $1;\n\t\t\tmy $ctx_before = substr($line, 0, $-[1]);\n\t\t\tmy $ctx = \"$ctx_before$name\";\n\n\t\t\t# Ignore those directives where spaces _are_ permitted.\n\t\t\tif ($name =~ /^(?:\n\t\t\t\tif|for|while|switch|return|case|\n\t\t\t\tvolatile|__volatile__|\n\t\t\t\t__attribute__|format|__extension__|\n\t\t\t\tasm|__asm__)$/x)\n\t\t\t{\n\t\t\t# cpp #define statements have non-optional spaces, ie\n\t\t\t# if there is a space between the name and the open\n\t\t\t# parenthesis it is simply not a parameter group.\n\t\t\t} elsif ($ctx_before =~ /^.\\s*\\#\\s*define\\s*$/) {\n\n\t\t\t# cpp #elif statement condition may start with a (\n\t\t\t} elsif ($ctx =~ /^.\\s*\\#\\s*elif\\s*$/) {\n\n\t\t\t# If this whole things ends with a type its most\n\t\t\t# likely a typedef for a function.\n\t\t\t} elsif ($ctx =~ /$Type$/) {\n\n\t\t\t} else {\n\t\t\t\tif (WARN(\"SPACING\",\n\t\t\t\t\t \"space prohibited between function name and open parenthesis '('\\n\" . $herecurr) &&\n\t\t\t\t\t     $fix) {\n\t\t\t\t\t$fixed[$fixlinenr] =~\n\t\t\t\t\t    s/\\b$name\\s+\\(/$name\\(/;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n# Check operator spacing.\n\t\tif (!($line=~/\\#\\s*include/)) {\n\t\t\tmy $fixed_line = \"\";\n\t\t\tmy $line_fixed = 0;\n\n\t\t\tmy $ops = qr{\n\t\t\t\t<<=|>>=|<=|>=|==|!=|\n\t\t\t\t\\+=|-=|\\*=|\\/=|%=|\\^=|\\|=|&=|\n\t\t\t\t=>|->|<<|>>|<|>|=|!|~|\n\t\t\t\t&&|\\|\\||,|\\^|\\+\\+|--|&|\\||\\+|-|\\*|\\/|%|\n\t\t\t\t\\?:|\\?|:\n\t\t\t}x;\n\t\t\tmy @elements = split(/($ops|;)/, $opline);\n\n##\t\t\tprint(\"element count: <\" . $#elements . \">\\n\");\n##\t\t\tforeach my $el (@elements) {\n##\t\t\t\tprint(\"el: <$el>\\n\");\n##\t\t\t}\n\n\t\t\tmy @fix_elements = ();\n\t\t\tmy $off = 0;\n\n\t\t\tforeach my $el (@elements) {\n\t\t\t\tpush(@fix_elements, substr($rawline, $off, length($el)));\n\t\t\t\t$off += length($el);\n\t\t\t}\n\n\t\t\t$off = 0;\n\n\t\t\tmy $blank = copy_spacing($opline);\n\t\t\tmy $last_after = -1;\n\n\t\t\tfor (my $n = 0; $n < $#elements; $n += 2) {\n\n\t\t\t\tmy $good = $fix_elements[$n] . $fix_elements[$n + 1];\n\n##\t\t\t\tprint(\"n: <$n> good: <$good>\\n\");\n\n\t\t\t\t$off += length($elements[$n]);\n\n\t\t\t\t# Pick up the preceding and succeeding characters.\n\t\t\t\tmy $ca = substr($opline, 0, $off);\n\t\t\t\tmy $cc = '';\n\t\t\t\tif (length($opline) >= ($off + length($elements[$n + 1]))) {\n\t\t\t\t\t$cc = substr($opline, $off + length($elements[$n + 1]));\n\t\t\t\t}\n\t\t\t\tmy $cb = \"$ca$;$cc\";\n\n\t\t\t\tmy $a = '';\n\t\t\t\t$a = 'V' if ($elements[$n] ne '');\n\t\t\t\t$a = 'W' if ($elements[$n] =~ /\\s$/);\n\t\t\t\t$a = 'C' if ($elements[$n] =~ /$;$/);\n\t\t\t\t$a = 'B' if ($elements[$n] =~ /(\\[|\\()$/);\n\t\t\t\t$a = 'O' if ($elements[$n] eq '');\n\t\t\t\t$a = 'E' if ($ca =~ /^\\s*$/);\n\n\t\t\t\tmy $op = $elements[$n + 1];\n\n\t\t\t\tmy $c = '';\n\t\t\t\tif (defined $elements[$n + 2]) {\n\t\t\t\t\t$c = 'V' if ($elements[$n + 2] ne '');\n\t\t\t\t\t$c = 'W' if ($elements[$n + 2] =~ /^\\s/);\n\t\t\t\t\t$c = 'C' if ($elements[$n + 2] =~ /^$;/);\n\t\t\t\t\t$c = 'B' if ($elements[$n + 2] =~ /^(\\)|\\]|;)/);\n\t\t\t\t\t$c = 'O' if ($elements[$n + 2] eq '');\n\t\t\t\t\t$c = 'E' if ($elements[$n + 2] =~ /^\\s*\\\\$/);\n\t\t\t\t} else {\n\t\t\t\t\t$c = 'E';\n\t\t\t\t}\n\n\t\t\t\tmy $ctx = \"${a}x${c}\";\n\n\t\t\t\tmy $at = \"(ctx:$ctx)\";\n\n\t\t\t\tmy $ptr = substr($blank, 0, $off) . \"^\";\n\t\t\t\tmy $hereptr = \"$hereline$ptr\\n\";\n\n\t\t\t\t# Pull out the value of this operator.\n\t\t\t\tmy $op_type = substr($curr_values, $off + 1, 1);\n\n\t\t\t\t# Get the full operator variant.\n\t\t\t\tmy $opv = $op . substr($curr_vars, $off, 1);\n\n\t\t\t\t# Ignore operators passed as parameters.\n\t\t\t\tif ($op_type ne 'V' &&\n\t\t\t\t    $ca =~ /\\s$/ && $cc =~ /^\\s*[,\\)]/) {\n\n#\t\t\t\t# Ignore comments\n#\t\t\t\t} elsif ($op =~ /^$;+$/) {\n\n\t\t\t\t# ; should have either the end of line or a space or \\ after it\n\t\t\t\t} elsif ($op eq ';') {\n\t\t\t\t\tif ($ctx !~ /.x[WEBC]/ &&\n\t\t\t\t\t    $cc !~ /^\\\\/ && $cc !~ /^;/) {\n\t\t\t\t\t\tif (ERROR(\"SPACING\",\n\t\t\t\t\t\t\t  \"space required after that '$op' $at\\n\" . $hereptr)) {\n\t\t\t\t\t\t\t$good = $fix_elements[$n] . trim($fix_elements[$n + 1]) . \" \";\n\t\t\t\t\t\t\t$line_fixed = 1;\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\n\t\t\t\t# // is a comment\n\t\t\t\t} elsif ($op eq '//') {\n\n\t\t\t\t#   :   when part of a bitfield\n\t\t\t\t} elsif ($opv eq ':B') {\n\t\t\t\t\t# skip the bitfield test for now\n\n\t\t\t\t# No spaces for:\n\t\t\t\t#   ->\n\t\t\t\t} elsif ($op eq '->') {\n\t\t\t\t\tif ($ctx =~ /Wx.|.xW/) {\n\t\t\t\t\t\tif (ERROR(\"SPACING\",\n\t\t\t\t\t\t\t  \"spaces prohibited around that '$op' $at\\n\" . $hereptr)) {\n\t\t\t\t\t\t\t$good = rtrim($fix_elements[$n]) . trim($fix_elements[$n + 1]);\n\t\t\t\t\t\t\tif (defined $fix_elements[$n + 2]) {\n\t\t\t\t\t\t\t\t$fix_elements[$n + 2] =~ s/^\\s+//;\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t$line_fixed = 1;\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\n\t\t\t\t# , must not have a space before and must have a space on the right.\n\t\t\t\t} elsif ($op eq ',') {\n\t\t\t\t\tmy $rtrim_before = 0;\n\t\t\t\t\tmy $space_after = 0;\n\t\t\t\t\tif ($ctx =~ /Wx./) {\n\t\t\t\t\t\tif (ERROR(\"SPACING\",\n\t\t\t\t\t\t\t  \"space prohibited before that '$op' $at\\n\" . $hereptr)) {\n\t\t\t\t\t\t\t$line_fixed = 1;\n\t\t\t\t\t\t\t$rtrim_before = 1;\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t\tif ($ctx !~ /.x[WEC]/ && $cc !~ /^}/) {\n\t\t\t\t\t\tif (ERROR(\"SPACING\",\n\t\t\t\t\t\t\t  \"space required after that '$op' $at\\n\" . $hereptr)) {\n\t\t\t\t\t\t\t$line_fixed = 1;\n\t\t\t\t\t\t\t$last_after = $n;\n\t\t\t\t\t\t\t$space_after = 1;\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t\tif ($rtrim_before || $space_after) {\n\t\t\t\t\t\tif ($rtrim_before) {\n\t\t\t\t\t\t\t$good = rtrim($fix_elements[$n]) . trim($fix_elements[$n + 1]);\n\t\t\t\t\t\t} else {\n\t\t\t\t\t\t\t$good = $fix_elements[$n] . trim($fix_elements[$n + 1]);\n\t\t\t\t\t\t}\n\t\t\t\t\t\tif ($space_after) {\n\t\t\t\t\t\t\t$good .= \" \";\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\n\t\t\t\t# '*' as part of a type definition -- reported already.\n\t\t\t\t} elsif ($opv eq '*_') {\n\t\t\t\t\t#warn \"'*' is part of type\\n\";\n\n\t\t\t\t# unary operators should have a space before and\n\t\t\t\t# none after.  May be left adjacent to another\n\t\t\t\t# unary operator, or a cast\n\t\t\t\t} elsif ($op eq '!' || $op eq '~' ||\n\t\t\t\t\t $opv eq '*U' || $opv eq '-U' ||\n\t\t\t\t\t $opv eq '&U' || $opv eq '&&U') {\n\t\t\t\t\tif ($ctx !~ /[WEBC]x./ && $ca !~ /(?:\\)|!|~|\\*|-|\\&|\\||\\+\\+|\\-\\-|\\{)$/) {\n\t\t\t\t\t\tif (ERROR(\"SPACING\",\n\t\t\t\t\t\t\t  \"space required before that '$op' $at\\n\" . $hereptr)) {\n\t\t\t\t\t\t\tif ($n != $last_after + 2) {\n\t\t\t\t\t\t\t\t$good = $fix_elements[$n] . \" \" . ltrim($fix_elements[$n + 1]);\n\t\t\t\t\t\t\t\t$line_fixed = 1;\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t\tif ($op eq '*' && $cc =~/\\s*$Modifier\\b/) {\n\t\t\t\t\t\t# A unary '*' may be const\n\n\t\t\t\t\t} elsif ($ctx =~ /.xW/) {\n\t\t\t\t\t\tif (ERROR(\"SPACING\",\n\t\t\t\t\t\t\t  \"space prohibited after that '$op' $at\\n\" . $hereptr)) {\n\t\t\t\t\t\t\t$good = $fix_elements[$n] . rtrim($fix_elements[$n + 1]);\n\t\t\t\t\t\t\tif (defined $fix_elements[$n + 2]) {\n\t\t\t\t\t\t\t\t$fix_elements[$n + 2] =~ s/^\\s+//;\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t$line_fixed = 1;\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\n\t\t\t\t# unary ++ and unary -- are allowed no space on one side.\n\t\t\t\t} elsif ($op eq '++' or $op eq '--') {\n\t\t\t\t\tif ($ctx !~ /[WEOBC]x[^W]/ && $ctx !~ /[^W]x[WOBEC]/) {\n\t\t\t\t\t\tif (ERROR(\"SPACING\",\n\t\t\t\t\t\t\t  \"space required one side of that '$op' $at\\n\" . $hereptr)) {\n\t\t\t\t\t\t\t$good = $fix_elements[$n] . trim($fix_elements[$n + 1]) . \" \";\n\t\t\t\t\t\t\t$line_fixed = 1;\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t\tif ($ctx =~ /Wx[BE]/ ||\n\t\t\t\t\t    ($ctx =~ /Wx./ && $cc =~ /^;/)) {\n\t\t\t\t\t\tif (ERROR(\"SPACING\",\n\t\t\t\t\t\t\t  \"space prohibited before that '$op' $at\\n\" . $hereptr)) {\n\t\t\t\t\t\t\t$good = rtrim($fix_elements[$n]) . trim($fix_elements[$n + 1]);\n\t\t\t\t\t\t\t$line_fixed = 1;\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t\tif ($ctx =~ /ExW/) {\n\t\t\t\t\t\tif (ERROR(\"SPACING\",\n\t\t\t\t\t\t\t  \"space prohibited after that '$op' $at\\n\" . $hereptr)) {\n\t\t\t\t\t\t\t$good = $fix_elements[$n] . trim($fix_elements[$n + 1]);\n\t\t\t\t\t\t\tif (defined $fix_elements[$n + 2]) {\n\t\t\t\t\t\t\t\t$fix_elements[$n + 2] =~ s/^\\s+//;\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t$line_fixed = 1;\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\n\t\t\t\t# << and >> may either have or not have spaces both sides\n\t\t\t\t} elsif ($op eq '<<' or $op eq '>>' or\n\t\t\t\t\t $op eq '&' or $op eq '^' or $op eq '|' or\n\t\t\t\t\t $op eq '+' or $op eq '-' or\n\t\t\t\t\t $op eq '*' or $op eq '/' or\n\t\t\t\t\t $op eq '%')\n\t\t\t\t{\n\t\t\t\t\tif ($check) {\n\t\t\t\t\t\tif (defined $fix_elements[$n + 2] && $ctx !~ /[EW]x[EW]/) {\n\t\t\t\t\t\t\tif (CHK(\"SPACING\",\n\t\t\t\t\t\t\t\t\"spaces preferred around that '$op' $at\\n\" . $hereptr)) {\n\t\t\t\t\t\t\t\t$good = rtrim($fix_elements[$n]) . \" \" . trim($fix_elements[$n + 1]) . \" \";\n\t\t\t\t\t\t\t\t$fix_elements[$n + 2] =~ s/^\\s+//;\n\t\t\t\t\t\t\t\t$line_fixed = 1;\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t} elsif (!defined $fix_elements[$n + 2] && $ctx !~ /Wx[OE]/) {\n\t\t\t\t\t\t\tif (CHK(\"SPACING\",\n\t\t\t\t\t\t\t\t\"space preferred before that '$op' $at\\n\" . $hereptr)) {\n\t\t\t\t\t\t\t\t$good = rtrim($fix_elements[$n]) . \" \" . trim($fix_elements[$n + 1]);\n\t\t\t\t\t\t\t\t$line_fixed = 1;\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t}\n\t\t\t\t\t} elsif ($ctx =~ /Wx[^WCE]|[^WCE]xW/) {\n\t\t\t\t\t\tif (ERROR(\"SPACING\",\n\t\t\t\t\t\t\t  \"need consistent spacing around '$op' $at\\n\" . $hereptr)) {\n\t\t\t\t\t\t\t$good = rtrim($fix_elements[$n]) . \" \" . trim($fix_elements[$n + 1]) . \" \";\n\t\t\t\t\t\t\tif (defined $fix_elements[$n + 2]) {\n\t\t\t\t\t\t\t\t$fix_elements[$n + 2] =~ s/^\\s+//;\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t$line_fixed = 1;\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\n\t\t\t\t# A colon needs no spaces before when it is\n\t\t\t\t# terminating a case value or a label.\n\t\t\t\t} elsif ($opv eq ':C' || $opv eq ':L') {\n\t\t\t\t\tif ($ctx =~ /Wx./) {\n\t\t\t\t\t\tif (ERROR(\"SPACING\",\n\t\t\t\t\t\t\t  \"space prohibited before that '$op' $at\\n\" . $hereptr)) {\n\t\t\t\t\t\t\t$good = rtrim($fix_elements[$n]) . trim($fix_elements[$n + 1]);\n\t\t\t\t\t\t\t$line_fixed = 1;\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\n\t\t\t\t# All the others need spaces both sides.\n\t\t\t\t} elsif ($ctx !~ /[EWC]x[CWE]/) {\n\t\t\t\t\tmy $ok = 0;\n\n\t\t\t\t\t# Ignore email addresses <foo@bar>\n\t\t\t\t\tif (($op eq '<' &&\n\t\t\t\t\t     $cc =~ /^\\S+\\@\\S+>/) ||\n\t\t\t\t\t    ($op eq '>' &&\n\t\t\t\t\t     $ca =~ /<\\S+\\@\\S+$/))\n\t\t\t\t\t{\n\t\t\t\t\t\t$ok = 1;\n\t\t\t\t\t}\n\n\t\t\t\t\t# for asm volatile statements\n\t\t\t\t\t# ignore a colon with another\n\t\t\t\t\t# colon immediately before or after\n\t\t\t\t\tif (($op eq ':') &&\n\t\t\t\t\t    ($ca =~ /:$/ || $cc =~ /^:/)) {\n\t\t\t\t\t\t$ok = 1;\n\t\t\t\t\t}\n\n\t\t\t\t\t# messages are ERROR, but ?: are CHK\n\t\t\t\t\tif ($ok == 0) {\n\t\t\t\t\t\tmy $msg_level = \\&ERROR;\n\t\t\t\t\t\t$msg_level = \\&CHK if (($op eq '?:' || $op eq '?' || $op eq ':') && $ctx =~ /VxV/);\n\n\t\t\t\t\t\tif (&{$msg_level}(\"SPACING\",\n\t\t\t\t\t\t\t\t  \"spaces required around that '$op' $at\\n\" . $hereptr)) {\n\t\t\t\t\t\t\t$good = rtrim($fix_elements[$n]) . \" \" . trim($fix_elements[$n + 1]) . \" \";\n\t\t\t\t\t\t\tif (defined $fix_elements[$n + 2]) {\n\t\t\t\t\t\t\t\t$fix_elements[$n + 2] =~ s/^\\s+//;\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t$line_fixed = 1;\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\t$off += length($elements[$n + 1]);\n\n##\t\t\t\tprint(\"n: <$n> GOOD: <$good>\\n\");\n\n\t\t\t\t$fixed_line = $fixed_line . $good;\n\t\t\t}\n\n\t\t\tif (($#elements % 2) == 0) {\n\t\t\t\t$fixed_line = $fixed_line . $fix_elements[$#elements];\n\t\t\t}\n\n\t\t\tif ($fix && $line_fixed && $fixed_line ne $fixed[$fixlinenr]) {\n\t\t\t\t$fixed[$fixlinenr] = $fixed_line;\n\t\t\t}\n\n\n\t\t}\n\n# check for whitespace before a non-naked semicolon\n\t\tif ($line =~ /^\\+.*\\S\\s+;\\s*$/) {\n\t\t\tif (WARN(\"SPACING\",\n\t\t\t\t \"space prohibited before semicolon\\n\" . $herecurr) &&\n\t\t\t    $fix) {\n\t\t\t\t1 while $fixed[$fixlinenr] =~\n\t\t\t\t    s/^(\\+.*\\S)\\s+;/$1;/;\n\t\t\t}\n\t\t}\n\n# check for multiple assignments\n\t\tif ($line =~ /^.\\s*$Lval\\s*=\\s*$Lval\\s*=(?!=)/) {\n\t\t\tCHK(\"MULTIPLE_ASSIGNMENTS\",\n\t\t\t    \"multiple assignments should be avoided\\n\" . $herecurr);\n\t\t}\n\n## # check for multiple declarations, allowing for a function declaration\n## # continuation.\n## \t\tif ($line =~ /^.\\s*$Type\\s+$Ident(?:\\s*=[^,{]*)?\\s*,\\s*$Ident.*/ &&\n## \t\t    $line !~ /^.\\s*$Type\\s+$Ident(?:\\s*=[^,{]*)?\\s*,\\s*$Type\\s*$Ident.*/) {\n##\n## \t\t\t# Remove any bracketed sections to ensure we do not\n## \t\t\t# falsely report the parameters of functions.\n## \t\t\tmy $ln = $line;\n## \t\t\twhile ($ln =~ s/\\([^\\(\\)]*\\)//g) {\n## \t\t\t}\n## \t\t\tif ($ln =~ /,/) {\n## \t\t\t\tWARN(\"MULTIPLE_DECLARATION\",\n##\t\t\t\t     \"declaring multiple variables together should be avoided\\n\" . $herecurr);\n## \t\t\t}\n## \t\t}\n\n#need space before brace following if, while, etc\n\t\tif (($line =~ /\\(.*\\)\\{/ && $line !~ /\\($Type\\)\\{/) ||\n\t\t    $line =~ /\\b(?:else|do)\\{/) {\n\t\t\tif (ERROR(\"SPACING\",\n\t\t\t\t  \"space required before the open brace '{'\\n\" . $herecurr) &&\n\t\t\t    $fix) {\n\t\t\t\t$fixed[$fixlinenr] =~ s/^(\\+.*(?:do|else|\\)))\\{/$1 {/;\n\t\t\t}\n\t\t}\n\n## # check for blank lines before declarations\n##\t\tif ($line =~ /^.\\t+$Type\\s+$Ident(?:\\s*=.*)?;/ &&\n##\t\t    $prevrawline =~ /^.\\s*$/) {\n##\t\t\tWARN(\"SPACING\",\n##\t\t\t     \"No blank lines before declarations\\n\" . $hereprev);\n##\t\t}\n##\n\n# closing brace should have a space following it when it has anything\n# on the line\n\t\tif ($line =~ /}(?!(?:,|;|\\)|\\}))\\S/) {\n\t\t\tif (ERROR(\"SPACING\",\n\t\t\t\t  \"space required after that close brace '}'\\n\" . $herecurr) &&\n\t\t\t    $fix) {\n\t\t\t\t$fixed[$fixlinenr] =~\n\t\t\t\t    s/}((?!(?:,|;|\\)))\\S)/} $1/;\n\t\t\t}\n\t\t}\n\n# check spacing on square brackets\n\t\tif ($line =~ /\\[\\s/ && $line !~ /\\[\\s*$/) {\n\t\t\tif (ERROR(\"SPACING\",\n\t\t\t\t  \"space prohibited after that open square bracket '['\\n\" . $herecurr) &&\n\t\t\t    $fix) {\n\t\t\t\t$fixed[$fixlinenr] =~\n\t\t\t\t    s/\\[\\s+/\\[/;\n\t\t\t}\n\t\t}\n\t\tif ($line =~ /\\s\\]/) {\n\t\t\tif (ERROR(\"SPACING\",\n\t\t\t\t  \"space prohibited before that close square bracket ']'\\n\" . $herecurr) &&\n\t\t\t    $fix) {\n\t\t\t\t$fixed[$fixlinenr] =~\n\t\t\t\t    s/\\s+\\]/\\]/;\n\t\t\t}\n\t\t}\n\n# check spacing on parentheses\n\t\tif ($line =~ /\\(\\s/ && $line !~ /\\(\\s*(?:\\\\)?$/ &&\n\t\t    $line !~ /for\\s*\\(\\s+;/) {\n\t\t\tif (ERROR(\"SPACING\",\n\t\t\t\t  \"space prohibited after that open parenthesis '('\\n\" . $herecurr) &&\n\t\t\t    $fix) {\n\t\t\t\t$fixed[$fixlinenr] =~\n\t\t\t\t    s/\\(\\s+/\\(/;\n\t\t\t}\n\t\t}\n\t\tif ($line =~ /(\\s+)\\)/ && $line !~ /^.\\s*\\)/ &&\n\t\t    $line !~ /for\\s*\\(.*;\\s+\\)/ &&\n\t\t    $line !~ /:\\s+\\)/) {\n\t\t\tif (ERROR(\"SPACING\",\n\t\t\t\t  \"space prohibited before that close parenthesis ')'\\n\" . $herecurr) &&\n\t\t\t    $fix) {\n\t\t\t\t$fixed[$fixlinenr] =~\n\t\t\t\t    s/\\s+\\)/\\)/;\n\t\t\t}\n\t\t}\n\n# check unnecessary parentheses around addressof/dereference single $Lvals\n# ie: &(foo->bar) should be &foo->bar and *(foo->bar) should be *foo->bar\n\n\t\twhile ($line =~ /(?:[^&]&\\s*|\\*)\\(\\s*($Ident\\s*(?:$Member\\s*)+)\\s*\\)/g) {\n\t\t\tmy $var = $1;\n\t\t\tif (CHK(\"UNNECESSARY_PARENTHESES\",\n\t\t\t\t\"Unnecessary parentheses around $var\\n\" . $herecurr) &&\n\t\t\t    $fix) {\n\t\t\t\t$fixed[$fixlinenr] =~ s/\\(\\s*\\Q$var\\E\\s*\\)/$var/;\n\t\t\t}\n\t\t}\n\n# check for unnecessary parentheses around function pointer uses\n# ie: (foo->bar)(); should be foo->bar();\n# but not \"if (foo->bar) (\" to avoid some false positives\n\t\tif ($line =~ /(\\bif\\s*|)(\\(\\s*$Ident\\s*(?:$Member\\s*)+\\))[ \\t]*\\(/ && $1 !~ /^if/) {\n\t\t\tmy $var = $2;\n\t\t\tif (CHK(\"UNNECESSARY_PARENTHESES\",\n\t\t\t\t\"Unnecessary parentheses around function pointer $var\\n\" . $herecurr) &&\n\t\t\t    $fix) {\n\t\t\t\tmy $var2 = deparenthesize($var);\n\t\t\t\t$var2 =~ s/\\s//g;\n\t\t\t\t$fixed[$fixlinenr] =~ s/\\Q$var\\E/$var2/;\n\t\t\t}\n\t\t}\n\n# check for unnecessary parentheses around comparisons in if uses\n# when !drivers/staging or command-line uses --strict\n\t\tif (($realfile !~ m@^(?:drivers/staging/)@ || $check_orig) &&\n\t\t    $perl_version_ok && defined($stat) &&\n\t\t    $stat =~ /(^.\\s*if\\s*($balanced_parens))/) {\n\t\t\tmy $if_stat = $1;\n\t\t\tmy $test = substr($2, 1, -1);\n\t\t\tmy $herectx;\n\t\t\twhile ($test =~ /(?:^|[^\\w\\&\\!\\~])+\\s*\\(\\s*([\\&\\!\\~]?\\s*$Lval\\s*(?:$Compare\\s*$FuncArg)?)\\s*\\)/g) {\n\t\t\t\tmy $match = $1;\n\t\t\t\t# avoid parentheses around potential macro args\n\t\t\t\tnext if ($match =~ /^\\s*\\w+\\s*$/);\n\t\t\t\tif (!defined($herectx)) {\n\t\t\t\t\t$herectx = $here . \"\\n\";\n\t\t\t\t\tmy $cnt = statement_rawlines($if_stat);\n\t\t\t\t\tfor (my $n = 0; $n < $cnt; $n++) {\n\t\t\t\t\t\tmy $rl = raw_line($linenr, $n);\n\t\t\t\t\t\t$herectx .=  $rl . \"\\n\";\n\t\t\t\t\t\tlast if $rl =~ /^[ \\+].*\\{/;\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\tCHK(\"UNNECESSARY_PARENTHESES\",\n\t\t\t\t    \"Unnecessary parentheses around '$match'\\n\" . $herectx);\n\t\t\t}\n\t\t}\n\n#goto labels aren't indented, allow a single space however\n\t\tif ($line=~/^.\\s+[A-Za-z\\d_]+:(?![0-9]+)/ and\n\t\t   !($line=~/^. [A-Za-z\\d_]+:/) and !($line=~/^.\\s+default:/)) {\n\t\t\tif (WARN(\"INDENTED_LABEL\",\n\t\t\t\t \"labels should not be indented\\n\" . $herecurr) &&\n\t\t\t    $fix) {\n\t\t\t\t$fixed[$fixlinenr] =~\n\t\t\t\t    s/^(.)\\s+/$1/;\n\t\t\t}\n\t\t}\n\n# return is not a function\n\t\tif (defined($stat) && $stat =~ /^.\\s*return(\\s*)\\(/s) {\n\t\t\tmy $spacing = $1;\n\t\t\tif ($perl_version_ok &&\n\t\t\t    $stat =~ /^.\\s*return\\s*($balanced_parens)\\s*;\\s*$/) {\n\t\t\t\tmy $value = $1;\n\t\t\t\t$value = deparenthesize($value);\n\t\t\t\tif ($value =~ m/^\\s*$FuncArg\\s*(?:\\?|$)/) {\n\t\t\t\t\tERROR(\"RETURN_PARENTHESES\",\n\t\t\t\t\t      \"return is not a function, parentheses are not required\\n\" . $herecurr);\n\t\t\t\t}\n\t\t\t} elsif ($spacing !~ /\\s+/) {\n\t\t\t\tERROR(\"SPACING\",\n\t\t\t\t      \"space required before the open parenthesis '('\\n\" . $herecurr);\n\t\t\t}\n\t\t}\n\n# unnecessary return in a void function\n# at end-of-function, with the previous line a single leading tab, then return;\n# and the line before that not a goto label target like \"out:\"\n\t\tif ($sline =~ /^[ \\+]}\\s*$/ &&\n\t\t    $prevline =~ /^\\+\\treturn\\s*;\\s*$/ &&\n\t\t    $linenr >= 3 &&\n\t\t    $lines[$linenr - 3] =~ /^[ +]/ &&\n\t\t    $lines[$linenr - 3] !~ /^[ +]\\s*$Ident\\s*:/) {\n\t\t\tWARN(\"RETURN_VOID\",\n\t\t\t     \"void function return statements are not generally useful\\n\" . $hereprev);\n               }\n\n# if statements using unnecessary parentheses - ie: if ((foo == bar))\n\t\tif ($perl_version_ok &&\n\t\t    $line =~ /\\bif\\s*((?:\\(\\s*){2,})/) {\n\t\t\tmy $openparens = $1;\n\t\t\tmy $count = $openparens =~ tr@\\(@\\(@;\n\t\t\tmy $msg = \"\";\n\t\t\tif ($line =~ /\\bif\\s*(?:\\(\\s*){$count,$count}$LvalOrFunc\\s*($Compare)\\s*$LvalOrFunc(?:\\s*\\)){$count,$count}/) {\n\t\t\t\tmy $comp = $4;\t#Not $1 because of $LvalOrFunc\n\t\t\t\t$msg = \" - maybe == should be = ?\" if ($comp eq \"==\");\n\t\t\t\tWARN(\"UNNECESSARY_PARENTHESES\",\n\t\t\t\t     \"Unnecessary parentheses$msg\\n\" . $herecurr);\n\t\t\t}\n\t\t}\n\n# comparisons with a constant or upper case identifier on the left\n#\tavoid cases like \"foo + BAR < baz\"\n#\tonly fix matches surrounded by parentheses to avoid incorrect\n#\tconversions like \"FOO < baz() + 5\" being \"misfixed\" to \"baz() > FOO + 5\"\n\t\tif ($perl_version_ok &&\n\t\t    $line =~ /^\\+(.*)\\b($Constant|[A-Z_][A-Z0-9_]*)\\s*($Compare)\\s*($LvalOrFunc)/) {\n\t\t\tmy $lead = $1;\n\t\t\tmy $const = $2;\n\t\t\tmy $comp = $3;\n\t\t\tmy $to = $4;\n\t\t\tmy $newcomp = $comp;\n\t\t\tif ($lead !~ /(?:$Operators|\\.)\\s*$/ &&\n\t\t\t    $to !~ /^(?:Constant|[A-Z_][A-Z0-9_]*)$/ &&\n\t\t\t    WARN(\"CONSTANT_COMPARISON\",\n\t\t\t\t \"Comparisons should place the constant on the right side of the test\\n\" . $herecurr) &&\n\t\t\t    $fix) {\n\t\t\t\tif ($comp eq \"<\") {\n\t\t\t\t\t$newcomp = \">\";\n\t\t\t\t} elsif ($comp eq \"<=\") {\n\t\t\t\t\t$newcomp = \">=\";\n\t\t\t\t} elsif ($comp eq \">\") {\n\t\t\t\t\t$newcomp = \"<\";\n\t\t\t\t} elsif ($comp eq \">=\") {\n\t\t\t\t\t$newcomp = \"<=\";\n\t\t\t\t}\n\t\t\t\t$fixed[$fixlinenr] =~ s/\\(\\s*\\Q$const\\E\\s*$Compare\\s*\\Q$to\\E\\s*\\)/($to $newcomp $const)/;\n\t\t\t}\n\t\t}\n\n# Return of what appears to be an errno should normally be negative\n\t\tif ($sline =~ /\\breturn(?:\\s*\\(+\\s*|\\s+)(E[A-Z]+)(?:\\s*\\)+\\s*|\\s*)[;:,]/) {\n\t\t\tmy $name = $1;\n\t\t\tif ($name ne 'EOF' && $name ne 'ERROR') {\n\t\t\t\tWARN(\"USE_NEGATIVE_ERRNO\",\n\t\t\t\t     \"return of an errno should typically be negative (ie: return -$1)\\n\" . $herecurr);\n\t\t\t}\n\t\t}\n\n# Need a space before open parenthesis after if, while etc\n\t\tif ($line =~ /\\b(if|while|for|switch)\\(/) {\n\t\t\tif (ERROR(\"SPACING\",\n\t\t\t\t  \"space required before the open parenthesis '('\\n\" . $herecurr) &&\n\t\t\t    $fix) {\n\t\t\t\t$fixed[$fixlinenr] =~\n\t\t\t\t    s/\\b(if|while|for|switch)\\(/$1 \\(/;\n\t\t\t}\n\t\t}\n\n# Check for illegal assignment in if conditional -- and check for trailing\n# statements after the conditional.\n\t\tif ($line =~ /do\\s*(?!{)/) {\n\t\t\t($stat, $cond, $line_nr_next, $remain_next, $off_next) =\n\t\t\t\tctx_statement_block($linenr, $realcnt, 0)\n\t\t\t\t\tif (!defined $stat);\n\t\t\tmy ($stat_next) = ctx_statement_block($line_nr_next,\n\t\t\t\t\t\t$remain_next, $off_next);\n\t\t\t$stat_next =~ s/\\n./\\n /g;\n\t\t\t##print \"stat<$stat> stat_next<$stat_next>\\n\";\n\n\t\t\tif ($stat_next =~ /^\\s*while\\b/) {\n\t\t\t\t# If the statement carries leading newlines,\n\t\t\t\t# then count those as offsets.\n\t\t\t\tmy ($whitespace) =\n\t\t\t\t\t($stat_next =~ /^((?:\\s*\\n[+-])*\\s*)/s);\n\t\t\t\tmy $offset =\n\t\t\t\t\tstatement_rawlines($whitespace) - 1;\n\n\t\t\t\t$suppress_whiletrailers{$line_nr_next +\n\t\t\t\t\t\t\t\t$offset} = 1;\n\t\t\t}\n\t\t}\n\t\tif (!defined $suppress_whiletrailers{$linenr} &&\n\t\t    defined($stat) && defined($cond) &&\n\t\t    $line =~ /\\b(?:if|while|for)\\s*\\(/ && $line !~ /^.\\s*#/) {\n\t\t\tmy ($s, $c) = ($stat, $cond);\n\n\t\t\tif ($c =~ /\\bif\\s*\\(.*[^<>!=]=[^=].*/s) {\n\t\t\t\tERROR(\"ASSIGN_IN_IF\",\n\t\t\t\t      \"do not use assignment in if condition\\n\" . $herecurr);\n\t\t\t}\n\n\t\t\t# Find out what is on the end of the line after the\n\t\t\t# conditional.\n\t\t\tsubstr($s, 0, length($c), '');\n\t\t\t$s =~ s/\\n.*//g;\n\t\t\t$s =~ s/$;//g;\t# Remove any comments\n\t\t\tif (length($c) && $s !~ /^\\s*{?\\s*\\\\*\\s*$/ &&\n\t\t\t    $c !~ /}\\s*while\\s*/)\n\t\t\t{\n\t\t\t\t# Find out how long the conditional actually is.\n\t\t\t\tmy @newlines = ($c =~ /\\n/gs);\n\t\t\t\tmy $cond_lines = 1 + $#newlines;\n\t\t\t\tmy $stat_real = '';\n\n\t\t\t\t$stat_real = raw_line($linenr, $cond_lines)\n\t\t\t\t\t\t\t. \"\\n\" if ($cond_lines);\n\t\t\t\tif (defined($stat_real) && $cond_lines > 1) {\n\t\t\t\t\t$stat_real = \"[...]\\n$stat_real\";\n\t\t\t\t}\n\n\t\t\t\tERROR(\"TRAILING_STATEMENTS\",\n\t\t\t\t      \"trailing statements should be on next line\\n\" . $herecurr . $stat_real);\n\t\t\t}\n\t\t}\n\n# Check for bitwise tests written as boolean\n\t\tif ($line =~ /\n\t\t\t(?:\n\t\t\t\t(?:\\[|\\(|\\&\\&|\\|\\|)\n\t\t\t\t\\s*0[xX][0-9]+\\s*\n\t\t\t\t(?:\\&\\&|\\|\\|)\n\t\t\t|\n\t\t\t\t(?:\\&\\&|\\|\\|)\n\t\t\t\t\\s*0[xX][0-9]+\\s*\n\t\t\t\t(?:\\&\\&|\\|\\||\\)|\\])\n\t\t\t)/x)\n\t\t{\n\t\t\tWARN(\"HEXADECIMAL_BOOLEAN_TEST\",\n\t\t\t     \"boolean test with hexadecimal, perhaps just 1 \\& or \\|?\\n\" . $herecurr);\n\t\t}\n\n# if and else should not have general statements after it\n\t\tif ($line =~ /^.\\s*(?:}\\s*)?else\\b(.*)/) {\n\t\t\tmy $s = $1;\n\t\t\t$s =~ s/$;//g;\t# Remove any comments\n\t\t\tif ($s !~ /^\\s*(?:\\sif|(?:{|)\\s*\\\\?\\s*$)/) {\n\t\t\t\tERROR(\"TRAILING_STATEMENTS\",\n\t\t\t\t      \"trailing statements should be on next line\\n\" . $herecurr);\n\t\t\t}\n\t\t}\n# if should not continue a brace\n\t\tif ($line =~ /}\\s*if\\b/) {\n\t\t\tERROR(\"TRAILING_STATEMENTS\",\n\t\t\t      \"trailing statements should be on next line (or did you mean 'else if'?)\\n\" .\n\t\t\t\t$herecurr);\n\t\t}\n# case and default should not have general statements after them\n\t\tif ($line =~ /^.\\s*(?:case\\s*.*|default\\s*):/g &&\n\t\t    $line !~ /\\G(?:\n\t\t\t(?:\\s*$;*)(?:\\s*{)?(?:\\s*$;*)(?:\\s*\\\\)?\\s*$|\n\t\t\t\\s*return\\s+\n\t\t    )/xg)\n\t\t{\n\t\t\tERROR(\"TRAILING_STATEMENTS\",\n\t\t\t      \"trailing statements should be on next line\\n\" . $herecurr);\n\t\t}\n\n\t\t# Check for }<nl>else {, these must be at the same\n\t\t# indent level to be relevant to each other.\n\t\tif ($prevline=~/}\\s*$/ and $line=~/^.\\s*else\\s*/ &&\n\t\t    $previndent == $indent) {\n\t\t\tif (ERROR(\"ELSE_AFTER_BRACE\",\n\t\t\t\t  \"else should follow close brace '}'\\n\" . $hereprev) &&\n\t\t\t    $fix && $prevline =~ /^\\+/ && $line =~ /^\\+/) {\n\t\t\t\tfix_delete_line($fixlinenr - 1, $prevrawline);\n\t\t\t\tfix_delete_line($fixlinenr, $rawline);\n\t\t\t\tmy $fixedline = $prevrawline;\n\t\t\t\t$fixedline =~ s/}\\s*$//;\n\t\t\t\tif ($fixedline !~ /^\\+\\s*$/) {\n\t\t\t\t\tfix_insert_line($fixlinenr, $fixedline);\n\t\t\t\t}\n\t\t\t\t$fixedline = $rawline;\n\t\t\t\t$fixedline =~ s/^(.\\s*)else/$1} else/;\n\t\t\t\tfix_insert_line($fixlinenr, $fixedline);\n\t\t\t}\n\t\t}\n\n\t\tif ($prevline=~/}\\s*$/ and $line=~/^.\\s*while\\s*/ &&\n\t\t    $previndent == $indent) {\n\t\t\tmy ($s, $c) = ctx_statement_block($linenr, $realcnt, 0);\n\n\t\t\t# Find out what is on the end of the line after the\n\t\t\t# conditional.\n\t\t\tsubstr($s, 0, length($c), '');\n\t\t\t$s =~ s/\\n.*//g;\n\n\t\t\tif ($s =~ /^\\s*;/) {\n\t\t\t\tif (ERROR(\"WHILE_AFTER_BRACE\",\n\t\t\t\t\t  \"while should follow close brace '}'\\n\" . $hereprev) &&\n\t\t\t\t    $fix && $prevline =~ /^\\+/ && $line =~ /^\\+/) {\n\t\t\t\t\tfix_delete_line($fixlinenr - 1, $prevrawline);\n\t\t\t\t\tfix_delete_line($fixlinenr, $rawline);\n\t\t\t\t\tmy $fixedline = $prevrawline;\n\t\t\t\t\tmy $trailing = $rawline;\n\t\t\t\t\t$trailing =~ s/^\\+//;\n\t\t\t\t\t$trailing = trim($trailing);\n\t\t\t\t\t$fixedline =~ s/}\\s*$/} $trailing/;\n\t\t\t\t\tfix_insert_line($fixlinenr, $fixedline);\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n#Specific variable tests\n\t\twhile ($line =~ m{($Constant|$Lval)}g) {\n\t\t\tmy $var = $1;\n\n#CamelCase\n\t\t\tif ($var !~ /^$Constant$/ &&\n\t\t\t    $var =~ /[A-Z][a-z]|[a-z][A-Z]/ &&\n#Ignore Page<foo> variants\n\t\t\t    $var !~ /^(?:Clear|Set|TestClear|TestSet|)Page[A-Z]/ &&\n#Ignore SI style variants like nS, mV and dB\n#(ie: max_uV, regulator_min_uA_show, RANGE_mA_VALUE)\n\t\t\t    $var !~ /^(?:[a-z0-9_]*|[A-Z0-9_]*)?_?[a-z][A-Z](?:_[a-z0-9_]+|_[A-Z0-9_]+)?$/ &&\n#Ignore some three character SI units explicitly, like MiB and KHz\n\t\t\t    $var !~ /^(?:[a-z_]*?)_?(?:[KMGT]iB|[KMGT]?Hz)(?:_[a-z_]+)?$/) {\n\t\t\t\twhile ($var =~ m{($Ident)}g) {\n\t\t\t\t\tmy $word = $1;\n\t\t\t\t\tnext if ($word !~ /[A-Z][a-z]|[a-z][A-Z]/);\n\t\t\t\t\tif ($check) {\n\t\t\t\t\t\tseed_camelcase_includes();\n\t\t\t\t\t\tif (!$file && !$camelcase_file_seeded) {\n\t\t\t\t\t\t\tseed_camelcase_file($realfile);\n\t\t\t\t\t\t\t$camelcase_file_seeded = 1;\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t\tif (!defined $camelcase{$word}) {\n\t\t\t\t\t\t$camelcase{$word} = 1;\n\t\t\t\t\t\tCHK(\"CAMELCASE\",\n\t\t\t\t\t\t    \"Avoid CamelCase: <$word>\\n\" . $herecurr);\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n#no spaces allowed after \\ in define\n\t\tif ($line =~ /\\#\\s*define.*\\\\\\s+$/) {\n\t\t\tif (WARN(\"WHITESPACE_AFTER_LINE_CONTINUATION\",\n\t\t\t\t \"Whitespace after \\\\ makes next lines useless\\n\" . $herecurr) &&\n\t\t\t    $fix) {\n\t\t\t\t$fixed[$fixlinenr] =~ s/\\s+$//;\n\t\t\t}\n\t\t}\n\n# warn if <asm/foo.h> is #included and <linux/foo.h> is available and includes\n# itself <asm/foo.h> (uses RAW line)\n\t\tif ($tree && $rawline =~ m{^.\\s*\\#\\s*include\\s*\\<asm\\/(.*)\\.h\\>}) {\n\t\t\tmy $file = \"$1.h\";\n\t\t\tmy $checkfile = \"include/linux/$file\";\n\t\t\tif (-f \"$root/$checkfile\" &&\n\t\t\t    $realfile ne $checkfile &&\n\t\t\t    $1 !~ /$allowed_asm_includes/)\n\t\t\t{\n\t\t\t\tmy $asminclude = `grep -Ec \"#include\\\\s+<asm/$file>\" $root/$checkfile`;\n\t\t\t\tif ($asminclude > 0) {\n\t\t\t\t\tif ($realfile =~ m{^arch/}) {\n\t\t\t\t\t\tCHK(\"ARCH_INCLUDE_LINUX\",\n\t\t\t\t\t\t    \"Consider using #include <linux/$file> instead of <asm/$file>\\n\" . $herecurr);\n\t\t\t\t\t} else {\n\t\t\t\t\t\tWARN(\"INCLUDE_LINUX\",\n\t\t\t\t\t\t     \"Use #include <linux/$file> instead of <asm/$file>\\n\" . $herecurr);\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n# multi-statement macros should be enclosed in a do while loop, grab the\n# first statement and ensure its the whole macro if its not enclosed\n# in a known good container\n\t\tif ($realfile !~ m@/vmlinux.lds.h$@ &&\n\t\t    $line =~ /^.\\s*\\#\\s*define\\s*$Ident(\\()?/) {\n\t\t\tmy $ln = $linenr;\n\t\t\tmy $cnt = $realcnt;\n\t\t\tmy ($off, $dstat, $dcond, $rest);\n\t\t\tmy $ctx = '';\n\t\t\tmy $has_flow_statement = 0;\n\t\t\tmy $has_arg_concat = 0;\n\t\t\t($dstat, $dcond, $ln, $cnt, $off) =\n\t\t\t\tctx_statement_block($linenr, $realcnt, 0);\n\t\t\t$ctx = $dstat;\n\t\t\t#print \"dstat<$dstat> dcond<$dcond> cnt<$cnt> off<$off>\\n\";\n\t\t\t#print \"LINE<$lines[$ln-1]> len<\" . length($lines[$ln-1]) . \"\\n\";\n\n\t\t\t$has_flow_statement = 1 if ($ctx =~ /\\b(goto|return)\\b/);\n\t\t\t$has_arg_concat = 1 if ($ctx =~ /\\#\\#/ && $ctx !~ /\\#\\#\\s*(?:__VA_ARGS__|args)\\b/);\n\n\t\t\t$dstat =~ s/^.\\s*\\#\\s*define\\s+$Ident(\\([^\\)]*\\))?\\s*//;\n\t\t\tmy $define_args = $1;\n\t\t\tmy $define_stmt = $dstat;\n\t\t\tmy @def_args = ();\n\n\t\t\tif (defined $define_args && $define_args ne \"\") {\n\t\t\t\t$define_args = substr($define_args, 1, length($define_args) - 2);\n\t\t\t\t$define_args =~ s/\\s*//g;\n\t\t\t\t$define_args =~ s/\\\\\\+?//g;\n\t\t\t\t@def_args = split(\",\", $define_args);\n\t\t\t}\n\n\t\t\t$dstat =~ s/$;//g;\n\t\t\t$dstat =~ s/\\\\\\n.//g;\n\t\t\t$dstat =~ s/^\\s*//s;\n\t\t\t$dstat =~ s/\\s*$//s;\n\n\t\t\t# Flatten any parentheses and braces\n\t\t\twhile ($dstat =~ s/\\([^\\(\\)]*\\)/1/ ||\n\t\t\t       $dstat =~ s/\\{[^\\{\\}]*\\}/1/ ||\n\t\t\t       $dstat =~ s/.\\[[^\\[\\]]*\\]/1/)\n\t\t\t{\n\t\t\t}\n\n\t\t\t# Flatten any obvious string concatenation.\n\t\t\twhile ($dstat =~ s/($String)\\s*$Ident/$1/ ||\n\t\t\t       $dstat =~ s/$Ident\\s*($String)/$1/)\n\t\t\t{\n\t\t\t}\n\n\t\t\t# Make asm volatile uses seem like a generic function\n\t\t\t$dstat =~ s/\\b_*asm_*\\s+_*volatile_*\\b/asm_volatile/g;\n\n\t\t\tmy $exceptions = qr{\n\t\t\t\t$Declare|\n\t\t\t\tmodule_param_named|\n\t\t\t\tMODULE_PARM_DESC|\n\t\t\t\tDECLARE_PER_CPU|\n\t\t\t\tDEFINE_PER_CPU|\n\t\t\t\t__typeof__\\(|\n\t\t\t\tunion|\n\t\t\t\tstruct|\n\t\t\t\t\\.$Ident\\s*=\\s*|\n\t\t\t\t^\\\"|\\\"$|\n\t\t\t\t^\\[\n\t\t\t}x;\n\t\t\t#print \"REST<$rest> dstat<$dstat> ctx<$ctx>\\n\";\n\n\t\t\t$ctx =~ s/\\n*$//;\n\t\t\tmy $stmt_cnt = statement_rawlines($ctx);\n\t\t\tmy $herectx = get_stat_here($linenr, $stmt_cnt, $here);\n\n\t\t\tif ($dstat ne '' &&\n\t\t\t    $dstat !~ /^(?:$Ident|-?$Constant),$/ &&\t\t\t# 10, // foo(),\n\t\t\t    $dstat !~ /^(?:$Ident|-?$Constant);$/ &&\t\t\t# foo();\n\t\t\t    $dstat !~ /^[!~-]?(?:$Lval|$Constant)$/ &&\t\t# 10 // foo() // !foo // ~foo // -foo // foo->bar // foo.bar->baz\n\t\t\t    $dstat !~ /^'X'$/ && $dstat !~ /^'XX'$/ &&\t\t\t# character constants\n\t\t\t    $dstat !~ /$exceptions/ &&\n\t\t\t    $dstat !~ /^\\.$Ident\\s*=/ &&\t\t\t\t# .foo =\n\t\t\t    $dstat !~ /^(?:\\#\\s*$Ident|\\#\\s*$Constant)\\s*$/ &&\t\t# stringification #foo\n\t\t\t    $dstat !~ /^do\\s*$Constant\\s*while\\s*$Constant;?$/ &&\t# do {...} while (...); // do {...} while (...)\n\t\t\t    $dstat !~ /^for\\s*$Constant$/ &&\t\t\t\t# for (...)\n\t\t\t    $dstat !~ /^for\\s*$Constant\\s+(?:$Ident|-?$Constant)$/ &&\t# for (...) bar()\n\t\t\t    $dstat !~ /^do\\s*{/ &&\t\t\t\t\t# do {...\n\t\t\t    $dstat !~ /^\\(\\{/ &&\t\t\t\t\t\t# ({...\n\t\t\t    $ctx !~ /^.\\s*#\\s*define\\s+TRACE_(?:SYSTEM|INCLUDE_FILE|INCLUDE_PATH)\\b/)\n\t\t\t{\n\t\t\t\tif ($dstat =~ /^\\s*if\\b/) {\n\t\t\t\t\tERROR(\"MULTISTATEMENT_MACRO_USE_DO_WHILE\",\n\t\t\t\t\t      \"Macros starting with if should be enclosed by a do - while loop to avoid possible if/else logic defects\\n\" . \"$herectx\");\n\t\t\t\t} elsif ($dstat =~ /;/) {\n\t\t\t\t\tERROR(\"MULTISTATEMENT_MACRO_USE_DO_WHILE\",\n\t\t\t\t\t      \"Macros with multiple statements should be enclosed in a do - while loop\\n\" . \"$herectx\");\n\t\t\t\t} else {\n\t\t\t\t\tERROR(\"COMPLEX_MACRO\",\n\t\t\t\t\t      \"Macros with complex values should be enclosed in parentheses\\n\" . \"$herectx\");\n\t\t\t\t}\n\n\t\t\t}\n\n\t\t\t# Make $define_stmt single line, comment-free, etc\n\t\t\tmy @stmt_array = split('\\n', $define_stmt);\n\t\t\tmy $first = 1;\n\t\t\t$define_stmt = \"\";\n\t\t\tforeach my $l (@stmt_array) {\n\t\t\t\t$l =~ s/\\\\$//;\n\t\t\t\tif ($first) {\n\t\t\t\t\t$define_stmt = $l;\n\t\t\t\t\t$first = 0;\n\t\t\t\t} elsif ($l =~ /^[\\+ ]/) {\n\t\t\t\t\t$define_stmt .= substr($l, 1);\n\t\t\t\t}\n\t\t\t}\n\t\t\t$define_stmt =~ s/$;//g;\n\t\t\t$define_stmt =~ s/\\s+/ /g;\n\t\t\t$define_stmt = trim($define_stmt);\n\n# check if any macro arguments are reused (ignore '...' and 'type')\n\t\t\tforeach my $arg (@def_args) {\n\t\t\t        next if ($arg =~ /\\.\\.\\./);\n\t\t\t        next if ($arg =~ /^type$/i);\n\t\t\t\tmy $tmp_stmt = $define_stmt;\n\t\t\t\t$tmp_stmt =~ s/\\b(sizeof|typeof|__typeof__|__builtin\\w+|typecheck\\s*\\(\\s*$Type\\s*,|\\#+)\\s*\\(*\\s*$arg\\s*\\)*\\b//g;\n\t\t\t\t$tmp_stmt =~ s/\\#+\\s*$arg\\b//g;\n\t\t\t\t$tmp_stmt =~ s/\\b$arg\\s*\\#\\#//g;\n\t\t\t\tmy $use_cnt = () = $tmp_stmt =~ /\\b$arg\\b/g;\n\t\t\t\tif ($use_cnt > 1) {\n\t\t\t\t\tCHK(\"MACRO_ARG_REUSE\",\n\t\t\t\t\t    \"Macro argument reuse '$arg' - possible side-effects?\\n\" . \"$herectx\");\n\t\t\t\t    }\n# check if any macro arguments may have other precedence issues\n\t\t\t\tif ($tmp_stmt =~ m/($Operators)?\\s*\\b$arg\\b\\s*($Operators)?/m &&\n\t\t\t\t    ((defined($1) && $1 ne ',') ||\n\t\t\t\t     (defined($2) && $2 ne ','))) {\n\t\t\t\t\tCHK(\"MACRO_ARG_PRECEDENCE\",\n\t\t\t\t\t    \"Macro argument '$arg' may be better as '($arg)' to avoid precedence issues\\n\" . \"$herectx\");\n\t\t\t\t}\n\t\t\t}\n\n# check for macros with flow control, but without ## concatenation\n# ## concatenation is commonly a macro that defines a function so ignore those\n\t\t\tif ($has_flow_statement && !$has_arg_concat) {\n\t\t\t\tmy $cnt = statement_rawlines($ctx);\n\t\t\t\tmy $herectx = get_stat_here($linenr, $cnt, $here);\n\n\t\t\t\tWARN(\"MACRO_WITH_FLOW_CONTROL\",\n\t\t\t\t     \"Macros with flow control statements should be avoided\\n\" . \"$herectx\");\n\t\t\t}\n\n# check for line continuations outside of #defines, preprocessor #, and asm\n\n\t\t} else {\n\t\t\tif ($prevline !~ /^..*\\\\$/ &&\n\t\t\t    $line !~ /^\\+\\s*\\#.*\\\\$/ &&\t\t# preprocessor\n\t\t\t    $line !~ /^\\+.*\\b(__asm__|asm)\\b.*\\\\$/ &&\t# asm\n\t\t\t    $line =~ /^\\+.*\\\\$/) {\n\t\t\t\tWARN(\"LINE_CONTINUATIONS\",\n\t\t\t\t     \"Avoid unnecessary line continuations\\n\" . $herecurr);\n\t\t\t}\n\t\t}\n\n# do {} while (0) macro tests:\n# single-statement macros do not need to be enclosed in do while (0) loop,\n# macro should not end with a semicolon\n\t\tif ($perl_version_ok &&\n\t\t    $realfile !~ m@/vmlinux.lds.h$@ &&\n\t\t    $line =~ /^.\\s*\\#\\s*define\\s+$Ident(\\()?/) {\n\t\t\tmy $ln = $linenr;\n\t\t\tmy $cnt = $realcnt;\n\t\t\tmy ($off, $dstat, $dcond, $rest);\n\t\t\tmy $ctx = '';\n\t\t\t($dstat, $dcond, $ln, $cnt, $off) =\n\t\t\t\tctx_statement_block($linenr, $realcnt, 0);\n\t\t\t$ctx = $dstat;\n\n\t\t\t$dstat =~ s/\\\\\\n.//g;\n\t\t\t$dstat =~ s/$;/ /g;\n\n\t\t\tif ($dstat =~ /^\\+\\s*#\\s*define\\s+$Ident\\s*${balanced_parens}\\s*do\\s*{(.*)\\s*}\\s*while\\s*\\(\\s*0\\s*\\)\\s*([;\\s]*)\\s*$/) {\n\t\t\t\tmy $stmts = $2;\n\t\t\t\tmy $semis = $3;\n\n\t\t\t\t$ctx =~ s/\\n*$//;\n\t\t\t\tmy $cnt = statement_rawlines($ctx);\n\t\t\t\tmy $herectx = get_stat_here($linenr, $cnt, $here);\n\n\t\t\t\tif (($stmts =~ tr/;/;/) == 1 &&\n\t\t\t\t    $stmts !~ /^\\s*(if|while|for|switch)\\b/) {\n\t\t\t\t\tWARN(\"SINGLE_STATEMENT_DO_WHILE_MACRO\",\n\t\t\t\t\t     \"Single statement macros should not use a do {} while (0) loop\\n\" . \"$herectx\");\n\t\t\t\t}\n\t\t\t\tif (defined $semis && $semis ne \"\") {\n\t\t\t\t\tWARN(\"DO_WHILE_MACRO_WITH_TRAILING_SEMICOLON\",\n\t\t\t\t\t     \"do {} while (0) macros should not be semicolon terminated\\n\" . \"$herectx\");\n\t\t\t\t}\n\t\t\t} elsif ($dstat =~ /^\\+\\s*#\\s*define\\s+$Ident.*;\\s*$/) {\n\t\t\t\t$ctx =~ s/\\n*$//;\n\t\t\t\tmy $cnt = statement_rawlines($ctx);\n\t\t\t\tmy $herectx = get_stat_here($linenr, $cnt, $here);\n\n\t\t\t\tWARN(\"TRAILING_SEMICOLON\",\n\t\t\t\t     \"macros should not use a trailing semicolon\\n\" . \"$herectx\");\n\t\t\t}\n\t\t}\n\n# check for redundant bracing round if etc\n\t\tif ($line =~ /(^.*)\\bif\\b/ && $1 !~ /else\\s*$/) {\n\t\t\tmy ($level, $endln, @chunks) =\n\t\t\t\tctx_statement_full($linenr, $realcnt, 1);\n\t\t\t#print \"chunks<$#chunks> linenr<$linenr> endln<$endln> level<$level>\\n\";\n\t\t\t#print \"APW: <<$chunks[1][0]>><<$chunks[1][1]>>\\n\";\n\t\t\tif ($#chunks > 0 && $level == 0) {\n\t\t\t\tmy @allowed = ();\n\t\t\t\tmy $allow = 0;\n\t\t\t\tmy $seen = 0;\n\t\t\t\tmy $herectx = $here . \"\\n\";\n\t\t\t\tmy $ln = $linenr - 1;\n\t\t\t\tfor my $chunk (@chunks) {\n\t\t\t\t\tmy ($cond, $block) = @{$chunk};\n\n\t\t\t\t\t# If the condition carries leading newlines, then count those as offsets.\n\t\t\t\t\tmy ($whitespace) = ($cond =~ /^((?:\\s*\\n[+-])*\\s*)/s);\n\t\t\t\t\tmy $offset = statement_rawlines($whitespace) - 1;\n\n\t\t\t\t\t$allowed[$allow] = 0;\n\t\t\t\t\t#print \"COND<$cond> whitespace<$whitespace> offset<$offset>\\n\";\n\n\t\t\t\t\t# We have looked at and allowed this specific line.\n\t\t\t\t\t$suppress_ifbraces{$ln + $offset} = 1;\n\n\t\t\t\t\t$herectx .= \"$rawlines[$ln + $offset]\\n[...]\\n\";\n\t\t\t\t\t$ln += statement_rawlines($block) - 1;\n\n\t\t\t\t\tsubstr($block, 0, length($cond), '');\n\n\t\t\t\t\t$seen++ if ($block =~ /^\\s*{/);\n\n\t\t\t\t\t#print \"cond<$cond> block<$block> allowed<$allowed[$allow]>\\n\";\n\t\t\t\t\tif (statement_lines($cond) > 1) {\n\t\t\t\t\t\t#print \"APW: ALLOWED: cond<$cond>\\n\";\n\t\t\t\t\t\t$allowed[$allow] = 1;\n\t\t\t\t\t}\n\t\t\t\t\tif ($block =~/\\b(?:if|for|while)\\b/) {\n\t\t\t\t\t\t#print \"APW: ALLOWED: block<$block>\\n\";\n\t\t\t\t\t\t$allowed[$allow] = 1;\n\t\t\t\t\t}\n\t\t\t\t\tif (statement_block_size($block) > 1) {\n\t\t\t\t\t\t#print \"APW: ALLOWED: lines block<$block>\\n\";\n\t\t\t\t\t\t$allowed[$allow] = 1;\n\t\t\t\t\t}\n\t\t\t\t\t$allow++;\n\t\t\t\t}\n\t\t\t\tif ($seen) {\n\t\t\t\t\tmy $sum_allowed = 0;\n\t\t\t\t\tforeach (@allowed) {\n\t\t\t\t\t\t$sum_allowed += $_;\n\t\t\t\t\t}\n\t\t\t\t\tif ($sum_allowed == 0) {\n\t\t\t\t\t\tWARN(\"BRACES\",\n\t\t\t\t\t\t     \"braces {} are not necessary for any arm of this statement\\n\" . $herectx);\n\t\t\t\t\t} elsif ($sum_allowed != $allow &&\n\t\t\t\t\t\t $seen != $allow) {\n\t\t\t\t\t\tCHK(\"BRACES\",\n\t\t\t\t\t\t    \"braces {} should be used on all arms of this statement\\n\" . $herectx);\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t\tif (!defined $suppress_ifbraces{$linenr - 1} &&\n\t\t\t\t\t$line =~ /\\b(if|while|for|else)\\b/) {\n\t\t\tmy $allowed = 0;\n\n\t\t\t# Check the pre-context.\n\t\t\tif (substr($line, 0, $-[0]) =~ /(\\}\\s*)$/) {\n\t\t\t\t#print \"APW: ALLOWED: pre<$1>\\n\";\n\t\t\t\t$allowed = 1;\n\t\t\t}\n\n\t\t\tmy ($level, $endln, @chunks) =\n\t\t\t\tctx_statement_full($linenr, $realcnt, $-[0]);\n\n\t\t\t# Check the condition.\n\t\t\tmy ($cond, $block) = @{$chunks[0]};\n\t\t\t#print \"CHECKING<$linenr> cond<$cond> block<$block>\\n\";\n\t\t\tif (defined $cond) {\n\t\t\t\tsubstr($block, 0, length($cond), '');\n\t\t\t}\n\t\t\tif (statement_lines($cond) > 1) {\n\t\t\t\t#print \"APW: ALLOWED: cond<$cond>\\n\";\n\t\t\t\t$allowed = 1;\n\t\t\t}\n\t\t\tif ($block =~/\\b(?:if|for|while)\\b/) {\n\t\t\t\t#print \"APW: ALLOWED: block<$block>\\n\";\n\t\t\t\t$allowed = 1;\n\t\t\t}\n\t\t\tif (statement_block_size($block) > 1) {\n\t\t\t\t#print \"APW: ALLOWED: lines block<$block>\\n\";\n\t\t\t\t$allowed = 1;\n\t\t\t}\n\t\t\t# Check the post-context.\n\t\t\tif (defined $chunks[1]) {\n\t\t\t\tmy ($cond, $block) = @{$chunks[1]};\n\t\t\t\tif (defined $cond) {\n\t\t\t\t\tsubstr($block, 0, length($cond), '');\n\t\t\t\t}\n\t\t\t\tif ($block =~ /^\\s*\\{/) {\n\t\t\t\t\t#print \"APW: ALLOWED: chunk-1 block<$block>\\n\";\n\t\t\t\t\t$allowed = 1;\n\t\t\t\t}\n\t\t\t}\n\t\t\tif ($level == 0 && $block =~ /^\\s*\\{/ && !$allowed) {\n\t\t\t\tmy $cnt = statement_rawlines($block);\n\t\t\t\tmy $herectx = get_stat_here($linenr, $cnt, $here);\n\n\t\t\t\tWARN(\"BRACES\",\n\t\t\t\t     \"braces {} are not necessary for single statement blocks\\n\" . $herectx);\n\t\t\t}\n\t\t}\n\n# check for single line unbalanced braces\n\t\tif ($sline =~ /^.\\s*\\}\\s*else\\s*$/ ||\n\t\t    $sline =~ /^.\\s*else\\s*\\{\\s*$/) {\n\t\t\tCHK(\"BRACES\", \"Unbalanced braces around else statement\\n\" . $herecurr);\n\t\t}\n\n# check for unnecessary blank lines around braces\n\t\tif (($line =~ /^.\\s*}\\s*$/ && $prevrawline =~ /^.\\s*$/)) {\n\t\t\tif (CHK(\"BRACES\",\n\t\t\t\t\"Blank lines aren't necessary before a close brace '}'\\n\" . $hereprev) &&\n\t\t\t    $fix && $prevrawline =~ /^\\+/) {\n\t\t\t\tfix_delete_line($fixlinenr - 1, $prevrawline);\n\t\t\t}\n\t\t}\n\t\tif (($rawline =~ /^.\\s*$/ && $prevline =~ /^..*{\\s*$/)) {\n\t\t\tif (CHK(\"BRACES\",\n\t\t\t\t\"Blank lines aren't necessary after an open brace '{'\\n\" . $hereprev) &&\n\t\t\t    $fix) {\n\t\t\t\tfix_delete_line($fixlinenr, $rawline);\n\t\t\t}\n\t\t}\n\n# no volatiles please\n\t\tmy $asm_volatile = qr{\\b(__asm__|asm)\\s+(__volatile__|volatile)\\b};\n\t\tif ($line =~ /\\bvolatile\\b/ && $line !~ /$asm_volatile/) {\n\t\t\tWARN(\"VOLATILE\",\n\t\t\t     \"Use of volatile is usually wrong: see Documentation/process/volatile-considered-harmful.rst\\n\" . $herecurr);\n\t\t}\n\n# Check for user-visible strings broken across lines, which breaks the ability\n# to grep for the string.  Make exceptions when the previous string ends in a\n# newline (multiple lines in one string constant) or '\\t', '\\r', ';', or '{'\n# (common in inline assembly) or is a octal \\123 or hexadecimal \\xaf value\n\t\tif ($line =~ /^\\+\\s*$String/ &&\n\t\t    $prevline =~ /\"\\s*$/ &&\n\t\t    $prevrawline !~ /(?:\\\\(?:[ntr]|[0-7]{1,3}|x[0-9a-fA-F]{1,2})|;\\s*|\\{\\s*)\"\\s*$/) {\n\t\t\tif (WARN(\"SPLIT_STRING\",\n\t\t\t\t \"quoted string split across lines\\n\" . $hereprev) &&\n\t\t\t\t     $fix &&\n\t\t\t\t     $prevrawline =~ /^\\+.*\"\\s*$/ &&\n\t\t\t\t     $last_coalesced_string_linenr != $linenr - 1) {\n\t\t\t\tmy $extracted_string = get_quoted_string($line, $rawline);\n\t\t\t\tmy $comma_close = \"\";\n\t\t\t\tif ($rawline =~ /\\Q$extracted_string\\E(\\s*\\)\\s*;\\s*$|\\s*,\\s*)/) {\n\t\t\t\t\t$comma_close = $1;\n\t\t\t\t}\n\n\t\t\t\tfix_delete_line($fixlinenr - 1, $prevrawline);\n\t\t\t\tfix_delete_line($fixlinenr, $rawline);\n\t\t\t\tmy $fixedline = $prevrawline;\n\t\t\t\t$fixedline =~ s/\"\\s*$//;\n\t\t\t\t$fixedline .= substr($extracted_string, 1) . trim($comma_close);\n\t\t\t\tfix_insert_line($fixlinenr - 1, $fixedline);\n\t\t\t\t$fixedline = $rawline;\n\t\t\t\t$fixedline =~ s/\\Q$extracted_string\\E\\Q$comma_close\\E//;\n\t\t\t\tif ($fixedline !~ /\\+\\s*$/) {\n\t\t\t\t\tfix_insert_line($fixlinenr, $fixedline);\n\t\t\t\t}\n\t\t\t\t$last_coalesced_string_linenr = $linenr;\n\t\t\t}\n\t\t}\n\n# check for missing a space in a string concatenation\n\t\tif ($prevrawline =~ /[^\\\\]\\w\"$/ && $rawline =~ /^\\+[\\t ]+\"\\w/) {\n\t\t\tWARN('MISSING_SPACE',\n\t\t\t     \"break quoted strings at a space character\\n\" . $hereprev);\n\t\t}\n\n# check for an embedded function name in a string when the function is known\n# This does not work very well for -f --file checking as it depends on patch\n# context providing the function name or a single line form for in-file\n# function declarations\n\t\tif ($line =~ /^\\+.*$String/ &&\n\t\t    defined($context_function) &&\n\t\t    get_quoted_string($line, $rawline) =~ /\\b$context_function\\b/ &&\n\t\t    length(get_quoted_string($line, $rawline)) != (length($context_function) + 2)) {\n\t\t\tWARN(\"EMBEDDED_FUNCTION_NAME\",\n\t\t\t     \"Prefer using '\\\"%s...\\\", __func__' to using '$context_function', this function's name, in a string\\n\" . $herecurr);\n\t\t}\n\n# check for spaces before a quoted newline\n\t\tif ($rawline =~ /^.*\\\".*\\s\\\\n/) {\n\t\t\tif (WARN(\"QUOTED_WHITESPACE_BEFORE_NEWLINE\",\n\t\t\t\t \"unnecessary whitespace before a quoted newline\\n\" . $herecurr) &&\n\t\t\t    $fix) {\n\t\t\t\t$fixed[$fixlinenr] =~ s/^(\\+.*\\\".*)\\s+\\\\n/$1\\\\n/;\n\t\t\t}\n\n\t\t}\n\n# concatenated string without spaces between elements\n\t\tif ($line =~ /$String[A-Za-z0-9_]/ || $line =~ /[A-Za-z0-9_]$String/) {\n\t\t\tif (CHK(\"CONCATENATED_STRING\",\n\t\t\t\t\"Concatenated strings should use spaces between elements\\n\" . $herecurr) &&\n\t\t\t    $fix) {\n\t\t\t\twhile ($line =~ /($String)/g) {\n\t\t\t\t\tmy $extracted_string = substr($rawline, $-[0], $+[0] - $-[0]);\n\t\t\t\t\t$fixed[$fixlinenr] =~ s/\\Q$extracted_string\\E([A-Za-z0-9_])/$extracted_string $1/;\n\t\t\t\t\t$fixed[$fixlinenr] =~ s/([A-Za-z0-9_])\\Q$extracted_string\\E/$1 $extracted_string/;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n# uncoalesced string fragments\n\t\tif ($line =~ /$String\\s*\"/) {\n\t\t\tif (WARN(\"STRING_FRAGMENTS\",\n\t\t\t\t \"Consecutive strings are generally better as a single string\\n\" . $herecurr) &&\n\t\t\t    $fix) {\n\t\t\t\twhile ($line =~ /($String)(?=\\s*\")/g) {\n\t\t\t\t\tmy $extracted_string = substr($rawline, $-[0], $+[0] - $-[0]);\n\t\t\t\t\t$fixed[$fixlinenr] =~ s/\\Q$extracted_string\\E\\s*\"/substr($extracted_string, 0, -1)/e;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n# check for non-standard and hex prefixed decimal printf formats\n\t\tmy $show_L = 1;\t#don't show the same defect twice\n\t\tmy $show_Z = 1;\n\t\twhile ($line =~ /(?:^|\")([X\\t]*)(?:\"|$)/g) {\n\t\t\tmy $string = substr($rawline, $-[1], $+[1] - $-[1]);\n\t\t\t$string =~ s/%%/__/g;\n\t\t\t# check for %L\n\t\t\tif ($show_L && $string =~ /%[\\*\\d\\.\\$]*L([diouxX])/) {\n\t\t\t\tWARN(\"PRINTF_L\",\n\t\t\t\t     \"\\%L$1 is non-standard C, use %ll$1\\n\" . $herecurr);\n\t\t\t\t$show_L = 0;\n\t\t\t}\n\t\t\t# check for %Z\n\t\t\tif ($show_Z && $string =~ /%[\\*\\d\\.\\$]*Z([diouxX])/) {\n\t\t\t\tWARN(\"PRINTF_Z\",\n\t\t\t\t     \"%Z$1 is non-standard C, use %z$1\\n\" . $herecurr);\n\t\t\t\t$show_Z = 0;\n\t\t\t}\n\t\t\t# check for 0x<decimal>\n\t\t\tif ($string =~ /0x%[\\*\\d\\.\\$\\Llzth]*[diou]/) {\n\t\t\t\tERROR(\"PRINTF_0XDECIMAL\",\n\t\t\t\t      \"Prefixing 0x with decimal output is defective\\n\" . $herecurr);\n\t\t\t}\n\t\t}\n\n# check for line continuations in quoted strings with odd counts of \"\n\t\tif ($rawline =~ /\\\\$/ && $sline =~ tr/\"/\"/ % 2) {\n\t\t\tWARN(\"LINE_CONTINUATIONS\",\n\t\t\t     \"Avoid line continuations in quoted strings\\n\" . $herecurr);\n\t\t}\n\n# warn about #if 0\n\t\tif ($line =~ /^.\\s*\\#\\s*if\\s+0\\b/) {\n\t\t\tWARN(\"IF_0\",\n\t\t\t     \"Consider removing the code enclosed by this #if 0 and its #endif\\n\" . $herecurr);\n\t\t}\n\n# warn about #if 1\n\t\tif ($line =~ /^.\\s*\\#\\s*if\\s+1\\b/) {\n\t\t\tWARN(\"IF_1\",\n\t\t\t     \"Consider removing the #if 1 and its #endif\\n\" . $herecurr);\n\t\t}\n\n# check for needless \"if (<foo>) fn(<foo>)\" uses\n\t\tif ($prevline =~ /\\bif\\s*\\(\\s*($Lval)\\s*\\)/) {\n\t\t\tmy $tested = quotemeta($1);\n\t\t\tmy $expr = '\\s*\\(\\s*' . $tested . '\\s*\\)\\s*;';\n\t\t\tif ($line =~ /\\b(kfree|usb_free_urb|debugfs_remove(?:_recursive)?|(?:kmem_cache|mempool|dma_pool)_destroy)$expr/) {\n\t\t\t\tmy $func = $1;\n\t\t\t\tif (WARN('NEEDLESS_IF',\n\t\t\t\t\t \"$func(NULL) is safe and this check is probably not required\\n\" . $hereprev) &&\n\t\t\t\t    $fix) {\n\t\t\t\t\tmy $do_fix = 1;\n\t\t\t\t\tmy $leading_tabs = \"\";\n\t\t\t\t\tmy $new_leading_tabs = \"\";\n\t\t\t\t\tif ($lines[$linenr - 2] =~ /^\\+(\\t*)if\\s*\\(\\s*$tested\\s*\\)\\s*$/) {\n\t\t\t\t\t\t$leading_tabs = $1;\n\t\t\t\t\t} else {\n\t\t\t\t\t\t$do_fix = 0;\n\t\t\t\t\t}\n\t\t\t\t\tif ($lines[$linenr - 1] =~ /^\\+(\\t+)$func\\s*\\(\\s*$tested\\s*\\)\\s*;\\s*$/) {\n\t\t\t\t\t\t$new_leading_tabs = $1;\n\t\t\t\t\t\tif (length($leading_tabs) + 1 ne length($new_leading_tabs)) {\n\t\t\t\t\t\t\t$do_fix = 0;\n\t\t\t\t\t\t}\n\t\t\t\t\t} else {\n\t\t\t\t\t\t$do_fix = 0;\n\t\t\t\t\t}\n\t\t\t\t\tif ($do_fix) {\n\t\t\t\t\t\tfix_delete_line($fixlinenr - 1, $prevrawline);\n\t\t\t\t\t\t$fixed[$fixlinenr] =~ s/^\\+$new_leading_tabs/\\+$leading_tabs/;\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n# check for unnecessary \"Out of Memory\" messages\n\t\tif ($line =~ /^\\+.*\\b$logFunctions\\s*\\(/ &&\n\t\t    $prevline =~ /^[ \\+]\\s*if\\s*\\(\\s*(\\!\\s*|NULL\\s*==\\s*)?($Lval)(\\s*==\\s*NULL\\s*)?\\s*\\)/ &&\n\t\t    (defined $1 || defined $3) &&\n\t\t    $linenr > 3) {\n\t\t\tmy $testval = $2;\n\t\t\tmy $testline = $lines[$linenr - 3];\n\n\t\t\tmy ($s, $c) = ctx_statement_block($linenr - 3, $realcnt, 0);\n#\t\t\tprint(\"line: <$line>\\nprevline: <$prevline>\\ns: <$s>\\nc: <$c>\\n\\n\\n\");\n\n\t\t\tif ($s =~ /(?:^|\\n)[ \\+]\\s*(?:$Type\\s*)?\\Q$testval\\E\\s*=\\s*(?:\\([^\\)]*\\)\\s*)?\\s*$allocFunctions\\s*\\(/ &&\n\t\t\t    $s !~ /\\b__GFP_NOWARN\\b/ ) {\n\t\t\t\tWARN(\"OOM_MESSAGE\",\n\t\t\t\t     \"Possible unnecessary 'out of memory' message\\n\" . $hereprev);\n\t\t\t}\n\t\t}\n\n# check for logging functions with KERN_<LEVEL>\n\t\tif ($line !~ /printk(?:_ratelimited|_once)?\\s*\\(/ &&\n\t\t    $line =~ /\\b$logFunctions\\s*\\(.*\\b(KERN_[A-Z]+)\\b/) {\n\t\t\tmy $level = $1;\n\t\t\tif (WARN(\"UNNECESSARY_KERN_LEVEL\",\n\t\t\t\t \"Possible unnecessary $level\\n\" . $herecurr) &&\n\t\t\t    $fix) {\n\t\t\t\t$fixed[$fixlinenr] =~ s/\\s*$level\\s*//;\n\t\t\t}\n\t\t}\n\n# check for logging continuations\n\t\tif ($line =~ /\\bprintk\\s*\\(\\s*KERN_CONT\\b|\\bpr_cont\\s*\\(/) {\n\t\t\tWARN(\"LOGGING_CONTINUATION\",\n\t\t\t     \"Avoid logging continuation uses where feasible\\n\" . $herecurr);\n\t\t}\n\n# check for mask then right shift without a parentheses\n\t\tif ($perl_version_ok &&\n\t\t    $line =~ /$LvalOrFunc\\s*\\&\\s*($LvalOrFunc)\\s*>>/ &&\n\t\t    $4 !~ /^\\&/) { # $LvalOrFunc may be &foo, ignore if so\n\t\t\tWARN(\"MASK_THEN_SHIFT\",\n\t\t\t     \"Possible precedence defect with mask then right shift - may need parentheses\\n\" . $herecurr);\n\t\t}\n\n# check for pointer comparisons to NULL\n\t\tif ($perl_version_ok) {\n\t\t\twhile ($line =~ /\\b$LvalOrFunc\\s*(==|\\!=)\\s*NULL\\b/g) {\n\t\t\t\tmy $val = $1;\n\t\t\t\tmy $equal = \"!\";\n\t\t\t\t$equal = \"\" if ($4 eq \"!=\");\n\t\t\t\tif (CHK(\"COMPARISON_TO_NULL\",\n\t\t\t\t\t\"Comparison to NULL could be written \\\"${equal}${val}\\\"\\n\" . $herecurr) &&\n\t\t\t\t\t    $fix) {\n\t\t\t\t\t$fixed[$fixlinenr] =~ s/\\b\\Q$val\\E\\s*(?:==|\\!=)\\s*NULL\\b/$equal$val/;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n# check for bad placement of section $InitAttribute (e.g.: __initdata)\n\t\tif ($line =~ /(\\b$InitAttribute\\b)/) {\n\t\t\tmy $attr = $1;\n\t\t\tif ($line =~ /^\\+\\s*static\\s+(?:const\\s+)?(?:$attr\\s+)?($NonptrTypeWithAttr)\\s+(?:$attr\\s+)?($Ident(?:\\[[^]]*\\])?)\\s*[=;]/) {\n\t\t\t\tmy $ptr = $1;\n\t\t\t\tmy $var = $2;\n\t\t\t\tif ((($ptr =~ /\\b(union|struct)\\s+$attr\\b/ &&\n\t\t\t\t      ERROR(\"MISPLACED_INIT\",\n\t\t\t\t\t    \"$attr should be placed after $var\\n\" . $herecurr)) ||\n\t\t\t\t     ($ptr !~ /\\b(union|struct)\\s+$attr\\b/ &&\n\t\t\t\t      WARN(\"MISPLACED_INIT\",\n\t\t\t\t\t   \"$attr should be placed after $var\\n\" . $herecurr))) &&\n\t\t\t\t    $fix) {\n\t\t\t\t\t$fixed[$fixlinenr] =~ s/(\\bstatic\\s+(?:const\\s+)?)(?:$attr\\s+)?($NonptrTypeWithAttr)\\s+(?:$attr\\s+)?($Ident(?:\\[[^]]*\\])?)\\s*([=;])\\s*/\"$1\" . trim(string_find_replace($2, \"\\\\s*$attr\\\\s*\", \" \")) . \" \" . trim(string_find_replace($3, \"\\\\s*$attr\\\\s*\", \"\")) . \" $attr\" . (\"$4\" eq \";\" ? \";\" : \" = \")/e;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n# check for $InitAttributeData (ie: __initdata) with const\n\t\tif ($line =~ /\\bconst\\b/ && $line =~ /($InitAttributeData)/) {\n\t\t\tmy $attr = $1;\n\t\t\t$attr =~ /($InitAttributePrefix)(.*)/;\n\t\t\tmy $attr_prefix = $1;\n\t\t\tmy $attr_type = $2;\n\t\t\tif (ERROR(\"INIT_ATTRIBUTE\",\n\t\t\t\t  \"Use of const init definition must use ${attr_prefix}initconst\\n\" . $herecurr) &&\n\t\t\t    $fix) {\n\t\t\t\t$fixed[$fixlinenr] =~\n\t\t\t\t    s/$InitAttributeData/${attr_prefix}initconst/;\n\t\t\t}\n\t\t}\n\n# check for $InitAttributeConst (ie: __initconst) without const\n\t\tif ($line !~ /\\bconst\\b/ && $line =~ /($InitAttributeConst)/) {\n\t\t\tmy $attr = $1;\n\t\t\tif (ERROR(\"INIT_ATTRIBUTE\",\n\t\t\t\t  \"Use of $attr requires a separate use of const\\n\" . $herecurr) &&\n\t\t\t    $fix) {\n\t\t\t\tmy $lead = $fixed[$fixlinenr] =~\n\t\t\t\t    /(^\\+\\s*(?:static\\s+))/;\n\t\t\t\t$lead = rtrim($1);\n\t\t\t\t$lead = \"$lead \" if ($lead !~ /^\\+$/);\n\t\t\t\t$lead = \"${lead}const \";\n\t\t\t\t$fixed[$fixlinenr] =~ s/(^\\+\\s*(?:static\\s+))/$lead/;\n\t\t\t}\n\t\t}\n\n# check for __read_mostly with const non-pointer (should just be const)\n\t\tif ($line =~ /\\b__read_mostly\\b/ &&\n\t\t    $line =~ /($Type)\\s*$Ident/ && $1 !~ /\\*\\s*$/ && $1 =~ /\\bconst\\b/) {\n\t\t\tif (ERROR(\"CONST_READ_MOSTLY\",\n\t\t\t\t  \"Invalid use of __read_mostly with const type\\n\" . $herecurr) &&\n\t\t\t    $fix) {\n\t\t\t\t$fixed[$fixlinenr] =~ s/\\s+__read_mostly\\b//;\n\t\t\t}\n\t\t}\n\n# don't use __constant_<foo> functions outside of include/uapi/\n\t\tif ($realfile !~ m@^include/uapi/@ &&\n\t\t    $line =~ /(__constant_(?:htons|ntohs|[bl]e(?:16|32|64)_to_cpu|cpu_to_[bl]e(?:16|32|64)))\\s*\\(/) {\n\t\t\tmy $constant_func = $1;\n\t\t\tmy $func = $constant_func;\n\t\t\t$func =~ s/^__constant_//;\n\t\t\tif (WARN(\"CONSTANT_CONVERSION\",\n\t\t\t\t \"$constant_func should be $func\\n\" . $herecurr) &&\n\t\t\t    $fix) {\n\t\t\t\t$fixed[$fixlinenr] =~ s/\\b$constant_func\\b/$func/g;\n\t\t\t}\n\t\t}\n\n# prefer usleep_range over udelay\n\t\tif ($line =~ /\\budelay\\s*\\(\\s*(\\d+)\\s*\\)/) {\n\t\t\tmy $delay = $1;\n\t\t\t# ignore udelay's < 10, however\n\t\t\tif (! ($delay < 10) ) {\n\t\t\t\tCHK(\"USLEEP_RANGE\",\n\t\t\t\t    \"usleep_range is preferred over udelay; see Documentation/timers/timers-howto.rst\\n\" . $herecurr);\n\t\t\t}\n\t\t\tif ($delay > 2000) {\n\t\t\t\tWARN(\"LONG_UDELAY\",\n\t\t\t\t     \"long udelay - prefer mdelay; see arch/arm/include/asm/delay.h\\n\" . $herecurr);\n\t\t\t}\n\t\t}\n\n# warn about unexpectedly long msleep's\n\t\tif ($line =~ /\\bmsleep\\s*\\((\\d+)\\);/) {\n\t\t\tif ($1 < 20) {\n\t\t\t\tWARN(\"MSLEEP\",\n\t\t\t\t     \"msleep < 20ms can sleep for up to 20ms; see Documentation/timers/timers-howto.rst\\n\" . $herecurr);\n\t\t\t}\n\t\t}\n\n# check for comparisons of jiffies\n\t\tif ($line =~ /\\bjiffies\\s*$Compare|$Compare\\s*jiffies\\b/) {\n\t\t\tWARN(\"JIFFIES_COMPARISON\",\n\t\t\t     \"Comparing jiffies is almost always wrong; prefer time_after, time_before and friends\\n\" . $herecurr);\n\t\t}\n\n# check for comparisons of get_jiffies_64()\n\t\tif ($line =~ /\\bget_jiffies_64\\s*\\(\\s*\\)\\s*$Compare|$Compare\\s*get_jiffies_64\\s*\\(\\s*\\)/) {\n\t\t\tWARN(\"JIFFIES_COMPARISON\",\n\t\t\t     \"Comparing get_jiffies_64() is almost always wrong; prefer time_after64, time_before64 and friends\\n\" . $herecurr);\n\t\t}\n\n# warn about #ifdefs in C files\n#\t\tif ($line =~ /^.\\s*\\#\\s*if(|n)def/ && ($realfile =~ /\\.c$/)) {\n#\t\t\tprint \"#ifdef in C files should be avoided\\n\";\n#\t\t\tprint \"$herecurr\";\n#\t\t\t$clean = 0;\n#\t\t}\n\n# warn about spacing in #ifdefs\n\t\tif ($line =~ /^.\\s*\\#\\s*(ifdef|ifndef|elif)\\s\\s+/) {\n\t\t\tif (ERROR(\"SPACING\",\n\t\t\t\t  \"exactly one space required after that #$1\\n\" . $herecurr) &&\n\t\t\t    $fix) {\n\t\t\t\t$fixed[$fixlinenr] =~\n\t\t\t\t    s/^(.\\s*\\#\\s*(ifdef|ifndef|elif))\\s{2,}/$1 /;\n\t\t\t}\n\n\t\t}\n\n# check for spinlock_t definitions without a comment.\n\t\tif ($line =~ /^.\\s*(struct\\s+mutex|spinlock_t)\\s+\\S+;/ ||\n\t\t    $line =~ /^.\\s*(DEFINE_MUTEX)\\s*\\(/) {\n\t\t\tmy $which = $1;\n\t\t\tif (!ctx_has_comment($first_line, $linenr)) {\n\t\t\t\tCHK(\"UNCOMMENTED_DEFINITION\",\n\t\t\t\t    \"$1 definition without comment\\n\" . $herecurr);\n\t\t\t}\n\t\t}\n# check for memory barriers without a comment.\n\n\t\tmy $barriers = qr{\n\t\t\tmb|\n\t\t\trmb|\n\t\t\twmb|\n\t\t\tread_barrier_depends\n\t\t}x;\n\t\tmy $barrier_stems = qr{\n\t\t\tmb__before_atomic|\n\t\t\tmb__after_atomic|\n\t\t\tstore_release|\n\t\t\tload_acquire|\n\t\t\tstore_mb|\n\t\t\t(?:$barriers)\n\t\t}x;\n\t\tmy $all_barriers = qr{\n\t\t\t(?:$barriers)|\n\t\t\tsmp_(?:$barrier_stems)|\n\t\t\tvirt_(?:$barrier_stems)\n\t\t}x;\n\n\t\tif ($line =~ /\\b(?:$all_barriers)\\s*\\(/) {\n\t\t\tif (!ctx_has_comment($first_line, $linenr)) {\n\t\t\t\tWARN(\"MEMORY_BARRIER\",\n\t\t\t\t     \"memory barrier without comment\\n\" . $herecurr);\n\t\t\t}\n\t\t}\n\n\t\tmy $underscore_smp_barriers = qr{__smp_(?:$barrier_stems)}x;\n\n\t\tif ($realfile !~ m@^include/asm-generic/@ &&\n\t\t    $realfile !~ m@/barrier\\.h$@ &&\n\t\t    $line =~ m/\\b(?:$underscore_smp_barriers)\\s*\\(/ &&\n\t\t    $line !~ m/^.\\s*\\#\\s*define\\s+(?:$underscore_smp_barriers)\\s*\\(/) {\n\t\t\tWARN(\"MEMORY_BARRIER\",\n\t\t\t     \"__smp memory barriers shouldn't be used outside barrier.h and asm-generic\\n\" . $herecurr);\n\t\t}\n\n# check for waitqueue_active without a comment.\n\t\tif ($line =~ /\\bwaitqueue_active\\s*\\(/) {\n\t\t\tif (!ctx_has_comment($first_line, $linenr)) {\n\t\t\t\tWARN(\"WAITQUEUE_ACTIVE\",\n\t\t\t\t     \"waitqueue_active without comment\\n\" . $herecurr);\n\t\t\t}\n\t\t}\n\n# check for data_race without a comment.\n\t\tif ($line =~ /\\bdata_race\\s*\\(/) {\n\t\t\tif (!ctx_has_comment($first_line, $linenr)) {\n\t\t\t\tWARN(\"DATA_RACE\",\n\t\t\t\t     \"data_race without comment\\n\" . $herecurr);\n\t\t\t}\n\t\t}\n\n# check for smp_read_barrier_depends and read_barrier_depends\n\t\tif (!$file && $line =~ /\\b(smp_|)read_barrier_depends\\s*\\(/) {\n\t\t\tWARN(\"READ_BARRIER_DEPENDS\",\n\t\t\t     \"$1read_barrier_depends should only be used in READ_ONCE or DEC Alpha code\\n\" . $herecurr);\n\t\t}\n\n# check of hardware specific defines\n\t\tif ($line =~ m@^.\\s*\\#\\s*if.*\\b(__i386__|__powerpc64__|__sun__|__s390x__)\\b@ && $realfile !~ m@include/asm-@) {\n\t\t\tCHK(\"ARCH_DEFINES\",\n\t\t\t    \"architecture specific defines should be avoided\\n\" .  $herecurr);\n\t\t}\n\n# check that the storage class is not after a type\n\t\tif ($line =~ /\\b($Type)\\s+($Storage)\\b/) {\n\t\t\tWARN(\"STORAGE_CLASS\",\n\t\t\t     \"storage class '$2' should be located before type '$1'\\n\" . $herecurr);\n\t\t}\n# Check that the storage class is at the beginning of a declaration\n\t\tif ($line =~ /\\b$Storage\\b/ &&\n\t\t    $line !~ /^.\\s*$Storage/ &&\n\t\t    $line =~ /^.\\s*(.+?)\\$Storage\\s/ &&\n\t\t    $1 !~ /[\\,\\)]\\s*$/) {\n\t\t\tWARN(\"STORAGE_CLASS\",\n\t\t\t     \"storage class should be at the beginning of the declaration\\n\" . $herecurr);\n\t\t}\n\n# check the location of the inline attribute, that it is between\n# storage class and type.\n\t\tif ($line =~ /\\b$Type\\s+$Inline\\b/ ||\n\t\t    $line =~ /\\b$Inline\\s+$Storage\\b/) {\n\t\t\tERROR(\"INLINE_LOCATION\",\n\t\t\t      \"inline keyword should sit between storage class and type\\n\" . $herecurr);\n\t\t}\n\n# Check for __inline__ and __inline, prefer inline\n\t\tif ($realfile !~ m@\\binclude/uapi/@ &&\n\t\t    $line =~ /\\b(__inline__|__inline)\\b/) {\n\t\t\tif (WARN(\"INLINE\",\n\t\t\t\t \"plain inline is preferred over $1\\n\" . $herecurr) &&\n\t\t\t    $fix) {\n\t\t\t\t$fixed[$fixlinenr] =~ s/\\b(__inline__|__inline)\\b/inline/;\n\n\t\t\t}\n\t\t}\n\n# Check for __attribute__ packed, prefer __packed\n\t\tif ($realfile !~ m@\\binclude/uapi/@ &&\n\t\t    $line =~ /\\b__attribute__\\s*\\(\\s*\\(.*\\bpacked\\b/) {\n\t\t\tWARN(\"PREFER_PACKED\",\n\t\t\t     \"__packed is preferred over __attribute__((packed))\\n\" . $herecurr);\n\t\t}\n\n# Check for __attribute__ aligned, prefer __aligned\n\t\tif ($realfile !~ m@\\binclude/uapi/@ &&\n\t\t    $line =~ /\\b__attribute__\\s*\\(\\s*\\(.*aligned/) {\n\t\t\tWARN(\"PREFER_ALIGNED\",\n\t\t\t     \"__aligned(size) is preferred over __attribute__((aligned(size)))\\n\" . $herecurr);\n\t\t}\n\n# Check for __attribute__ section, prefer __section\n\t\tif ($realfile !~ m@\\binclude/uapi/@ &&\n\t\t    $line =~ /\\b__attribute__\\s*\\(\\s*\\(.*_*section_*\\s*\\(\\s*(\"[^\"]*\")/) {\n\t\t\tmy $old = substr($rawline, $-[1], $+[1] - $-[1]);\n\t\t\tmy $new = substr($old, 1, -1);\n\t\t\tif (WARN(\"PREFER_SECTION\",\n\t\t\t\t \"__section($new) is preferred over __attribute__((section($old)))\\n\" . $herecurr) &&\n\t\t\t    $fix) {\n\t\t\t\t$fixed[$fixlinenr] =~ s/\\b__attribute__\\s*\\(\\s*\\(\\s*_*section_*\\s*\\(\\s*\\Q$old\\E\\s*\\)\\s*\\)\\s*\\)/__section($new)/;\n\t\t\t}\n\t\t}\n\n# Check for __attribute__ format(printf, prefer __printf\n\t\tif ($realfile !~ m@\\binclude/uapi/@ &&\n\t\t    $line =~ /\\b__attribute__\\s*\\(\\s*\\(\\s*format\\s*\\(\\s*printf/) {\n\t\t\tif (WARN(\"PREFER_PRINTF\",\n\t\t\t\t \"__printf(string-index, first-to-check) is preferred over __attribute__((format(printf, string-index, first-to-check)))\\n\" . $herecurr) &&\n\t\t\t    $fix) {\n\t\t\t\t$fixed[$fixlinenr] =~ s/\\b__attribute__\\s*\\(\\s*\\(\\s*format\\s*\\(\\s*printf\\s*,\\s*(.*)\\)\\s*\\)\\s*\\)/\"__printf(\" . trim($1) . \")\"/ex;\n\n\t\t\t}\n\t\t}\n\n# Check for __attribute__ format(scanf, prefer __scanf\n\t\tif ($realfile !~ m@\\binclude/uapi/@ &&\n\t\t    $line =~ /\\b__attribute__\\s*\\(\\s*\\(\\s*format\\s*\\(\\s*scanf\\b/) {\n\t\t\tif (WARN(\"PREFER_SCANF\",\n\t\t\t\t \"__scanf(string-index, first-to-check) is preferred over __attribute__((format(scanf, string-index, first-to-check)))\\n\" . $herecurr) &&\n\t\t\t    $fix) {\n\t\t\t\t$fixed[$fixlinenr] =~ s/\\b__attribute__\\s*\\(\\s*\\(\\s*format\\s*\\(\\s*scanf\\s*,\\s*(.*)\\)\\s*\\)\\s*\\)/\"__scanf(\" . trim($1) . \")\"/ex;\n\t\t\t}\n\t\t}\n\n# Check for __attribute__ weak, or __weak declarations (may have link issues)\n\t\tif ($perl_version_ok &&\n\t\t    $line =~ /(?:$Declare|$DeclareMisordered)\\s*$Ident\\s*$balanced_parens\\s*(?:$Attribute)?\\s*;/ &&\n\t\t    ($line =~ /\\b__attribute__\\s*\\(\\s*\\(.*\\bweak\\b/ ||\n\t\t     $line =~ /\\b__weak\\b/)) {\n\t\t\tERROR(\"WEAK_DECLARATION\",\n\t\t\t      \"Using weak declarations can have unintended link defects\\n\" . $herecurr);\n\t\t}\n\n# check for c99 types like uint8_t used outside of uapi/ and tools/\n\t\tif ($realfile !~ m@\\binclude/uapi/@ &&\n\t\t    $realfile !~ m@\\btools/@ &&\n\t\t    $line =~ /\\b($Declare)\\s*$Ident\\s*[=;,\\[]/) {\n\t\t\tmy $type = $1;\n\t\t\tif ($type =~ /\\b($typeC99Typedefs)\\b/) {\n\t\t\t\t$type = $1;\n\t\t\t\tmy $kernel_type = 'u';\n\t\t\t\t$kernel_type = 's' if ($type =~ /^_*[si]/);\n\t\t\t\t$type =~ /(\\d+)/;\n\t\t\t\t$kernel_type .= $1;\n\t\t\t\tif (CHK(\"PREFER_KERNEL_TYPES\",\n\t\t\t\t\t\"Prefer kernel type '$kernel_type' over '$type'\\n\" . $herecurr) &&\n\t\t\t\t    $fix) {\n\t\t\t\t\t$fixed[$fixlinenr] =~ s/\\b$type\\b/$kernel_type/;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n# check for cast of C90 native int or longer types constants\n\t\tif ($line =~ /(\\(\\s*$C90_int_types\\s*\\)\\s*)($Constant)\\b/) {\n\t\t\tmy $cast = $1;\n\t\t\tmy $const = $2;\n\t\t\tif (WARN(\"TYPECAST_INT_CONSTANT\",\n\t\t\t\t \"Unnecessary typecast of c90 int constant\\n\" . $herecurr) &&\n\t\t\t    $fix) {\n\t\t\t\tmy $suffix = \"\";\n\t\t\t\tmy $newconst = $const;\n\t\t\t\t$newconst =~ s/${Int_type}$//;\n\t\t\t\t$suffix .= 'U' if ($cast =~ /\\bunsigned\\b/);\n\t\t\t\tif ($cast =~ /\\blong\\s+long\\b/) {\n\t\t\t\t\t$suffix .= 'LL';\n\t\t\t\t} elsif ($cast =~ /\\blong\\b/) {\n\t\t\t\t\t$suffix .= 'L';\n\t\t\t\t}\n\t\t\t\t$fixed[$fixlinenr] =~ s/\\Q$cast\\E$const\\b/$newconst$suffix/;\n\t\t\t}\n\t\t}\n\n# check for sizeof(&)\n\t\tif ($line =~ /\\bsizeof\\s*\\(\\s*\\&/) {\n\t\t\tWARN(\"SIZEOF_ADDRESS\",\n\t\t\t     \"sizeof(& should be avoided\\n\" . $herecurr);\n\t\t}\n\n# check for sizeof without parenthesis\n\t\tif ($line =~ /\\bsizeof\\s+((?:\\*\\s*|)$Lval|$Type(?:\\s+$Lval|))/) {\n\t\t\tif (WARN(\"SIZEOF_PARENTHESIS\",\n\t\t\t\t \"sizeof $1 should be sizeof($1)\\n\" . $herecurr) &&\n\t\t\t    $fix) {\n\t\t\t\t$fixed[$fixlinenr] =~ s/\\bsizeof\\s+((?:\\*\\s*|)$Lval|$Type(?:\\s+$Lval|))/\"sizeof(\" . trim($1) . \")\"/ex;\n\t\t\t}\n\t\t}\n\n# check for struct spinlock declarations\n\t\tif ($line =~ /^.\\s*\\bstruct\\s+spinlock\\s+\\w+\\s*;/) {\n\t\t\tWARN(\"USE_SPINLOCK_T\",\n\t\t\t     \"struct spinlock should be spinlock_t\\n\" . $herecurr);\n\t\t}\n\n# check for seq_printf uses that could be seq_puts\n\t\tif ($sline =~ /\\bseq_printf\\s*\\(.*\"\\s*\\)\\s*;\\s*$/) {\n\t\t\tmy $fmt = get_quoted_string($line, $rawline);\n\t\t\t$fmt =~ s/%%//g;\n\t\t\tif ($fmt !~ /%/) {\n\t\t\t\tif (WARN(\"PREFER_SEQ_PUTS\",\n\t\t\t\t\t \"Prefer seq_puts to seq_printf\\n\" . $herecurr) &&\n\t\t\t\t    $fix) {\n\t\t\t\t\t$fixed[$fixlinenr] =~ s/\\bseq_printf\\b/seq_puts/;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n# check for vsprintf extension %p<foo> misuses\n\t\tif ($perl_version_ok &&\n\t\t    defined $stat &&\n\t\t    $stat =~ /^\\+(?![^\\{]*\\{\\s*).*\\b(\\w+)\\s*\\(.*$String\\s*,/s &&\n\t\t    $1 !~ /^_*volatile_*$/) {\n\t\t\tmy $stat_real;\n\n\t\t\tmy $lc = $stat =~ tr@\\n@@;\n\t\t\t$lc = $lc + $linenr;\n\t\t        for (my $count = $linenr; $count <= $lc; $count++) {\n\t\t\t\tmy $specifier;\n\t\t\t\tmy $extension;\n\t\t\t\tmy $qualifier;\n\t\t\t\tmy $bad_specifier = \"\";\n\t\t\t\tmy $fmt = get_quoted_string($lines[$count - 1], raw_line($count, 0));\n\t\t\t\t$fmt =~ s/%%//g;\n\n\t\t\t\twhile ($fmt =~ /(\\%[\\*\\d\\.]*p(\\w)(\\w*))/g) {\n\t\t\t\t\t$specifier = $1;\n\t\t\t\t\t$extension = $2;\n\t\t\t\t\t$qualifier = $3;\n\t\t\t\t\tif ($extension !~ /[SsBKRraEehMmIiUDdgVCbGNOxtf]/ ||\n\t\t\t\t\t    ($extension eq \"f\" &&\n\t\t\t\t\t     defined $qualifier && $qualifier !~ /^w/)) {\n\t\t\t\t\t\t$bad_specifier = $specifier;\n\t\t\t\t\t\tlast;\n\t\t\t\t\t}\n\t\t\t\t\tif ($extension eq \"x\" && !defined($stat_real)) {\n\t\t\t\t\t\tif (!defined($stat_real)) {\n\t\t\t\t\t\t\t$stat_real = get_stat_real($linenr, $lc);\n\t\t\t\t\t\t}\n\t\t\t\t\t\tWARN(\"VSPRINTF_SPECIFIER_PX\",\n\t\t\t\t\t\t     \"Using vsprintf specifier '\\%px' potentially exposes the kernel memory layout, if you don't really need the address please consider using '\\%p'.\\n\" . \"$here\\n$stat_real\\n\");\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\tif ($bad_specifier ne \"\") {\n\t\t\t\t\tmy $stat_real = get_stat_real($linenr, $lc);\n\t\t\t\t\tmy $ext_type = \"Invalid\";\n\t\t\t\t\tmy $use = \"\";\n\t\t\t\t\tif ($bad_specifier =~ /p[Ff]/) {\n\t\t\t\t\t\t$use = \" - use %pS instead\";\n\t\t\t\t\t\t$use =~ s/pS/ps/ if ($bad_specifier =~ /pf/);\n\t\t\t\t\t}\n\n\t\t\t\t\tWARN(\"VSPRINTF_POINTER_EXTENSION\",\n\t\t\t\t\t     \"$ext_type vsprintf pointer extension '$bad_specifier'$use\\n\" . \"$here\\n$stat_real\\n\");\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n# Check for misused memsets\n\t\tif ($perl_version_ok &&\n\t\t    defined $stat &&\n\t\t    $stat =~ /^\\+(?:.*?)\\bmemset\\s*\\(\\s*$FuncArg\\s*,\\s*$FuncArg\\s*\\,\\s*$FuncArg\\s*\\)/) {\n\n\t\t\tmy $ms_addr = $2;\n\t\t\tmy $ms_val = $7;\n\t\t\tmy $ms_size = $12;\n\n\t\t\tif ($ms_size =~ /^(0x|)0$/i) {\n\t\t\t\tERROR(\"MEMSET\",\n\t\t\t\t      \"memset to 0's uses 0 as the 2nd argument, not the 3rd\\n\" . \"$here\\n$stat\\n\");\n\t\t\t} elsif ($ms_size =~ /^(0x|)1$/i) {\n\t\t\t\tWARN(\"MEMSET\",\n\t\t\t\t     \"single byte memset is suspicious. Swapped 2nd/3rd argument?\\n\" . \"$here\\n$stat\\n\");\n\t\t\t}\n\t\t}\n\n# Check for memcpy(foo, bar, ETH_ALEN) that could be ether_addr_copy(foo, bar)\n#\t\tif ($perl_version_ok &&\n#\t\t    defined $stat &&\n#\t\t    $stat =~ /^\\+(?:.*?)\\bmemcpy\\s*\\(\\s*$FuncArg\\s*,\\s*$FuncArg\\s*\\,\\s*ETH_ALEN\\s*\\)/) {\n#\t\t\tif (WARN(\"PREFER_ETHER_ADDR_COPY\",\n#\t\t\t\t \"Prefer ether_addr_copy() over memcpy() if the Ethernet addresses are __aligned(2)\\n\" . \"$here\\n$stat\\n\") &&\n#\t\t\t    $fix) {\n#\t\t\t\t$fixed[$fixlinenr] =~ s/\\bmemcpy\\s*\\(\\s*$FuncArg\\s*,\\s*$FuncArg\\s*\\,\\s*ETH_ALEN\\s*\\)/ether_addr_copy($2, $7)/;\n#\t\t\t}\n#\t\t}\n\n# Check for memcmp(foo, bar, ETH_ALEN) that could be ether_addr_equal*(foo, bar)\n#\t\tif ($perl_version_ok &&\n#\t\t    defined $stat &&\n#\t\t    $stat =~ /^\\+(?:.*?)\\bmemcmp\\s*\\(\\s*$FuncArg\\s*,\\s*$FuncArg\\s*\\,\\s*ETH_ALEN\\s*\\)/) {\n#\t\t\tWARN(\"PREFER_ETHER_ADDR_EQUAL\",\n#\t\t\t     \"Prefer ether_addr_equal() or ether_addr_equal_unaligned() over memcmp()\\n\" . \"$here\\n$stat\\n\")\n#\t\t}\n\n# check for memset(foo, 0x0, ETH_ALEN) that could be eth_zero_addr\n# check for memset(foo, 0xFF, ETH_ALEN) that could be eth_broadcast_addr\n#\t\tif ($perl_version_ok &&\n#\t\t    defined $stat &&\n#\t\t    $stat =~ /^\\+(?:.*?)\\bmemset\\s*\\(\\s*$FuncArg\\s*,\\s*$FuncArg\\s*\\,\\s*ETH_ALEN\\s*\\)/) {\n#\n#\t\t\tmy $ms_val = $7;\n#\n#\t\t\tif ($ms_val =~ /^(?:0x|)0+$/i) {\n#\t\t\t\tif (WARN(\"PREFER_ETH_ZERO_ADDR\",\n#\t\t\t\t\t \"Prefer eth_zero_addr over memset()\\n\" . \"$here\\n$stat\\n\") &&\n#\t\t\t\t    $fix) {\n#\t\t\t\t\t$fixed[$fixlinenr] =~ s/\\bmemset\\s*\\(\\s*$FuncArg\\s*,\\s*$FuncArg\\s*,\\s*ETH_ALEN\\s*\\)/eth_zero_addr($2)/;\n#\t\t\t\t}\n#\t\t\t} elsif ($ms_val =~ /^(?:0xff|255)$/i) {\n#\t\t\t\tif (WARN(\"PREFER_ETH_BROADCAST_ADDR\",\n#\t\t\t\t\t \"Prefer eth_broadcast_addr() over memset()\\n\" . \"$here\\n$stat\\n\") &&\n#\t\t\t\t    $fix) {\n#\t\t\t\t\t$fixed[$fixlinenr] =~ s/\\bmemset\\s*\\(\\s*$FuncArg\\s*,\\s*$FuncArg\\s*,\\s*ETH_ALEN\\s*\\)/eth_broadcast_addr($2)/;\n#\t\t\t\t}\n#\t\t\t}\n#\t\t}\n\n# typecasts on min/max could be min_t/max_t\n\t\tif ($perl_version_ok &&\n\t\t    defined $stat &&\n\t\t    $stat =~ /^\\+(?:.*?)\\b(min|max)\\s*\\(\\s*$FuncArg\\s*,\\s*$FuncArg\\s*\\)/) {\n\t\t\tif (defined $2 || defined $7) {\n\t\t\t\tmy $call = $1;\n\t\t\t\tmy $cast1 = deparenthesize($2);\n\t\t\t\tmy $arg1 = $3;\n\t\t\t\tmy $cast2 = deparenthesize($7);\n\t\t\t\tmy $arg2 = $8;\n\t\t\t\tmy $cast;\n\n\t\t\t\tif ($cast1 ne \"\" && $cast2 ne \"\" && $cast1 ne $cast2) {\n\t\t\t\t\t$cast = \"$cast1 or $cast2\";\n\t\t\t\t} elsif ($cast1 ne \"\") {\n\t\t\t\t\t$cast = $cast1;\n\t\t\t\t} else {\n\t\t\t\t\t$cast = $cast2;\n\t\t\t\t}\n\t\t\t\tWARN(\"MINMAX\",\n\t\t\t\t     \"$call() should probably be ${call}_t($cast, $arg1, $arg2)\\n\" . \"$here\\n$stat\\n\");\n\t\t\t}\n\t\t}\n\n# check usleep_range arguments\n\t\tif ($perl_version_ok &&\n\t\t    defined $stat &&\n\t\t    $stat =~ /^\\+(?:.*?)\\busleep_range\\s*\\(\\s*($FuncArg)\\s*,\\s*($FuncArg)\\s*\\)/) {\n\t\t\tmy $min = $1;\n\t\t\tmy $max = $7;\n\t\t\tif ($min eq $max) {\n\t\t\t\tWARN(\"USLEEP_RANGE\",\n\t\t\t\t     \"usleep_range should not use min == max args; see Documentation/timers/timers-howto.rst\\n\" . \"$here\\n$stat\\n\");\n\t\t\t} elsif ($min =~ /^\\d+$/ && $max =~ /^\\d+$/ &&\n\t\t\t\t $min > $max) {\n\t\t\t\tWARN(\"USLEEP_RANGE\",\n\t\t\t\t     \"usleep_range args reversed, use min then max; see Documentation/timers/timers-howto.rst\\n\" . \"$here\\n$stat\\n\");\n\t\t\t}\n\t\t}\n\n# check for naked sscanf\n\t\tif ($perl_version_ok &&\n\t\t    defined $stat &&\n\t\t    $line =~ /\\bsscanf\\b/ &&\n\t\t    ($stat !~ /$Ident\\s*=\\s*sscanf\\s*$balanced_parens/ &&\n\t\t     $stat !~ /\\bsscanf\\s*$balanced_parens\\s*(?:$Compare)/ &&\n\t\t     $stat !~ /(?:$Compare)\\s*\\bsscanf\\s*$balanced_parens/)) {\n\t\t\tmy $lc = $stat =~ tr@\\n@@;\n\t\t\t$lc = $lc + $linenr;\n\t\t\tmy $stat_real = get_stat_real($linenr, $lc);\n\t\t\tWARN(\"NAKED_SSCANF\",\n\t\t\t     \"unchecked sscanf return value\\n\" . \"$here\\n$stat_real\\n\");\n\t\t}\n\n# check for simple sscanf that should be kstrto<foo>\n\t\tif ($perl_version_ok &&\n\t\t    defined $stat &&\n\t\t    $line =~ /\\bsscanf\\b/) {\n\t\t\tmy $lc = $stat =~ tr@\\n@@;\n\t\t\t$lc = $lc + $linenr;\n\t\t\tmy $stat_real = get_stat_real($linenr, $lc);\n\t\t\tif ($stat_real =~ /\\bsscanf\\b\\s*\\(\\s*$FuncArg\\s*,\\s*(\"[^\"]+\")/) {\n\t\t\t\tmy $format = $6;\n\t\t\t\tmy $count = $format =~ tr@%@%@;\n\t\t\t\tif ($count == 1 &&\n\t\t\t\t    $format =~ /^\"\\%(?i:ll[udxi]|[udxi]ll|ll|[hl]h?[udxi]|[udxi][hl]h?|[hl]h?|[udxi])\"$/) {\n\t\t\t\t\tWARN(\"SSCANF_TO_KSTRTO\",\n\t\t\t\t\t     \"Prefer kstrto<type> to single variable sscanf\\n\" . \"$here\\n$stat_real\\n\");\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n# check for new externs in .h files.\n\t\tif ($realfile =~ /\\.h$/ &&\n\t\t    $line =~ /^\\+\\s*(extern\\s+)$Type\\s*$Ident\\s*\\(/s) {\n\t\t\tif (CHK(\"AVOID_EXTERNS\",\n\t\t\t\t\"extern prototypes should be avoided in .h files\\n\" . $herecurr) &&\n\t\t\t    $fix) {\n\t\t\t\t$fixed[$fixlinenr] =~ s/(.*)\\bextern\\b\\s*(.*)/$1$2/;\n\t\t\t}\n\t\t}\n\n# check for new externs in .c files.\n\t\tif ($realfile =~ /\\.c$/ && defined $stat &&\n\t\t    $stat =~ /^.\\s*(?:extern\\s+)?$Type\\s+($Ident)(\\s*)\\(/s)\n\t\t{\n\t\t\tmy $function_name = $1;\n\t\t\tmy $paren_space = $2;\n\n\t\t\tmy $s = $stat;\n\t\t\tif (defined $cond) {\n\t\t\t\tsubstr($s, 0, length($cond), '');\n\t\t\t}\n\t\t\tif ($s =~ /^\\s*;/ &&\n\t\t\t    $function_name ne 'uninitialized_var')\n\t\t\t{\n\t\t\t\tWARN(\"AVOID_EXTERNS\",\n\t\t\t\t     \"externs should be avoided in .c files\\n\" .  $herecurr);\n\t\t\t}\n\n\t\t\tif ($paren_space =~ /\\n/) {\n\t\t\t\tWARN(\"FUNCTION_ARGUMENTS\",\n\t\t\t\t     \"arguments for function declarations should follow identifier\\n\" . $herecurr);\n\t\t\t}\n\n\t\t} elsif ($realfile =~ /\\.c$/ && defined $stat &&\n\t\t    $stat =~ /^.\\s*extern\\s+/)\n\t\t{\n\t\t\tWARN(\"AVOID_EXTERNS\",\n\t\t\t     \"externs should be avoided in .c files\\n\" .  $herecurr);\n\t\t}\n\n# check for function declarations that have arguments without identifier names\n# while avoiding uninitialized_var(x)\n\t\tif (defined $stat &&\n\t\t    $stat =~ /^.\\s*(?:extern\\s+)?$Type\\s*(?:($Ident)|\\(\\s*\\*\\s*$Ident\\s*\\))\\s*\\(\\s*([^{]+)\\s*\\)\\s*;/s &&\n\t\t    (!defined($1) ||\n\t\t     (defined($1) && $1 ne \"uninitialized_var\")) &&\n\t\t     $2 ne \"void\") {\n\t\t\tmy $args = trim($2);\n\t\t\twhile ($args =~ m/\\s*($Type\\s*(?:$Ident|\\(\\s*\\*\\s*$Ident?\\s*\\)\\s*$balanced_parens)?)/g) {\n\t\t\t\tmy $arg = trim($1);\n\t\t\t\tif ($arg =~ /^$Type$/ &&\n\t\t\t\t\t$arg !~ /enum\\s+$Ident$/) {\n\t\t\t\t\tWARN(\"FUNCTION_ARGUMENTS\",\n\t\t\t\t\t     \"function definition argument '$arg' should also have an identifier name\\n\" . $herecurr);\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n# check for function definitions\n\t\tif ($perl_version_ok &&\n\t\t    defined $stat &&\n\t\t    $stat =~ /^.\\s*(?:$Storage\\s+)?$Type\\s*($Ident)\\s*$balanced_parens\\s*{/s) {\n\t\t\t$context_function = $1;\n\n# check for multiline function definition with misplaced open brace\n\t\t\tmy $ok = 0;\n\t\t\tmy $cnt = statement_rawlines($stat);\n\t\t\tmy $herectx = $here . \"\\n\";\n\t\t\tfor (my $n = 0; $n < $cnt; $n++) {\n\t\t\t\tmy $rl = raw_line($linenr, $n);\n\t\t\t\t$herectx .=  $rl . \"\\n\";\n\t\t\t\t$ok = 1 if ($rl =~ /^[ \\+]\\{/);\n\t\t\t\t$ok = 1 if ($rl =~ /\\{/ && $n == 0);\n\t\t\t\tlast if $rl =~ /^[ \\+].*\\{/;\n\t\t\t}\n\t\t\tif (!$ok) {\n\t\t\t\tERROR(\"OPEN_BRACE\",\n\t\t\t\t      \"open brace '{' following function definitions go on the next line\\n\" . $herectx);\n\t\t\t}\n\t\t}\n\n# check for pointless casting of alloc functions\n\t\tif ($line =~ /\\*\\s*\\)\\s*$allocFunctions\\b/) {\n\t\t\tWARN(\"UNNECESSARY_CASTS\",\n\t\t\t     \"unnecessary cast may hide bugs, see http://c-faq.com/malloc/mallocnocast.html\\n\" . $herecurr);\n\t\t}\n\n# alloc style\n# p = alloc(sizeof(struct foo), ...) should be p = alloc(sizeof(*p), ...)\n\t\tif ($perl_version_ok &&\n\t\t    $line =~ /\\b($Lval)\\s*\\=\\s*(?:$balanced_parens)?\\s*((?:kv|k|v)[mz]alloc(?:_node)?)\\s*\\(\\s*(sizeof\\s*\\(\\s*struct\\s+$Lval\\s*\\))/) {\n\t\t\tCHK(\"ALLOC_SIZEOF_STRUCT\",\n\t\t\t    \"Prefer $3(sizeof(*$1)...) over $3($4...)\\n\" . $herecurr);\n\t\t}\n\n# check for k[mz]alloc with multiplies that could be kmalloc_array/kcalloc\n\t\tif ($perl_version_ok &&\n\t\t    defined $stat &&\n\t\t    $stat =~ /^\\+\\s*($Lval)\\s*\\=\\s*(?:$balanced_parens)?\\s*(k[mz]alloc)\\s*\\(\\s*($FuncArg)\\s*\\*\\s*($FuncArg)\\s*,/) {\n\t\t\tmy $oldfunc = $3;\n\t\t\tmy $a1 = $4;\n\t\t\tmy $a2 = $10;\n\t\t\tmy $newfunc = \"kmalloc_array\";\n\t\t\t$newfunc = \"kcalloc\" if ($oldfunc eq \"kzalloc\");\n\t\t\tmy $r1 = $a1;\n\t\t\tmy $r2 = $a2;\n\t\t\tif ($a1 =~ /^sizeof\\s*\\S/) {\n\t\t\t\t$r1 = $a2;\n\t\t\t\t$r2 = $a1;\n\t\t\t}\n\t\t\tif ($r1 !~ /^sizeof\\b/ && $r2 =~ /^sizeof\\s*\\S/ &&\n\t\t\t    !($r1 =~ /^$Constant$/ || $r1 =~ /^[A-Z_][A-Z0-9_]*$/)) {\n\t\t\t\tmy $cnt = statement_rawlines($stat);\n\t\t\t\tmy $herectx = get_stat_here($linenr, $cnt, $here);\n\n\t\t\t\tif (WARN(\"ALLOC_WITH_MULTIPLY\",\n\t\t\t\t\t \"Prefer $newfunc over $oldfunc with multiply\\n\" . $herectx) &&\n\t\t\t\t    $cnt == 1 &&\n\t\t\t\t    $fix) {\n\t\t\t\t\t$fixed[$fixlinenr] =~ s/\\b($Lval)\\s*\\=\\s*(?:$balanced_parens)?\\s*(k[mz]alloc)\\s*\\(\\s*($FuncArg)\\s*\\*\\s*($FuncArg)/$1 . ' = ' . \"$newfunc(\" . trim($r1) . ', ' . trim($r2)/e;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n# check for krealloc arg reuse\n\t\tif ($perl_version_ok &&\n\t\t    $line =~ /\\b($Lval)\\s*\\=\\s*(?:$balanced_parens)?\\s*krealloc\\s*\\(\\s*($Lval)\\s*,/ &&\n\t\t    $1 eq $3) {\n\t\t\tWARN(\"KREALLOC_ARG_REUSE\",\n\t\t\t     \"Reusing the krealloc arg is almost always a bug\\n\" . $herecurr);\n\t\t}\n\n# check for alloc argument mismatch\n\t\tif ($line =~ /\\b(kcalloc|kmalloc_array)\\s*\\(\\s*sizeof\\b/) {\n\t\t\tWARN(\"ALLOC_ARRAY_ARGS\",\n\t\t\t     \"$1 uses number as first arg, sizeof is generally wrong\\n\" . $herecurr);\n\t\t}\n\n# check for multiple semicolons\n\t\tif ($line =~ /;\\s*;\\s*$/) {\n\t\t\tif (WARN(\"ONE_SEMICOLON\",\n\t\t\t\t \"Statements terminations use 1 semicolon\\n\" . $herecurr) &&\n\t\t\t    $fix) {\n\t\t\t\t$fixed[$fixlinenr] =~ s/(\\s*;\\s*){2,}$/;/g;\n\t\t\t}\n\t\t}\n\n# check for #defines like: 1 << <digit> that could be BIT(digit), it is not exported to uapi\n\t\tif ($realfile !~ m@^include/uapi/@ &&\n\t\t    $line =~ /#\\s*define\\s+\\w+\\s+\\(?\\s*1\\s*([ulUL]*)\\s*\\<\\<\\s*(?:\\d+|$Ident)\\s*\\)?/) {\n\t\t\tmy $ull = \"\";\n\t\t\t$ull = \"_ULL\" if (defined($1) && $1 =~ /ll/i);\n\t\t\tif (CHK(\"BIT_MACRO\",\n\t\t\t\t\"Prefer using the BIT$ull macro\\n\" . $herecurr) &&\n\t\t\t    $fix) {\n\t\t\t\t$fixed[$fixlinenr] =~ s/\\(?\\s*1\\s*[ulUL]*\\s*<<\\s*(\\d+|$Ident)\\s*\\)?/BIT${ull}($1)/;\n\t\t\t}\n\t\t}\n\n# check for #if defined CONFIG_<FOO> || defined CONFIG_<FOO>_MODULE\n\t\tif ($line =~ /^\\+\\s*#\\s*if\\s+defined(?:\\s*\\(?\\s*|\\s+)(CONFIG_[A-Z_]+)\\s*\\)?\\s*\\|\\|\\s*defined(?:\\s*\\(?\\s*|\\s+)\\1_MODULE\\s*\\)?\\s*$/) {\n\t\t\tmy $config = $1;\n\t\t\tif (WARN(\"PREFER_IS_ENABLED\",\n\t\t\t\t \"Prefer IS_ENABLED(<FOO>) to CONFIG_<FOO> || CONFIG_<FOO>_MODULE\\n\" . $herecurr) &&\n\t\t\t    $fix) {\n\t\t\t\t$fixed[$fixlinenr] = \"\\+#if IS_ENABLED($config)\";\n\t\t\t}\n\t\t}\n\n# check for case / default statements not preceded by break/fallthrough/switch\n\t\tif ($line =~ /^.\\s*(?:case\\s+(?:$Ident|$Constant)\\s*|default):/) {\n\t\t\tmy $has_break = 0;\n\t\t\tmy $has_statement = 0;\n\t\t\tmy $count = 0;\n\t\t\tmy $prevline = $linenr;\n\t\t\twhile ($prevline > 1 && ($file || $count < 3) && !$has_break) {\n\t\t\t\t$prevline--;\n\t\t\t\tmy $rline = $rawlines[$prevline - 1];\n\t\t\t\tmy $fline = $lines[$prevline - 1];\n\t\t\t\tlast if ($fline =~ /^\\@\\@/);\n\t\t\t\tnext if ($fline =~ /^\\-/);\n\t\t\t\tnext if ($fline =~ /^.(?:\\s*(?:case\\s+(?:$Ident|$Constant)[\\s$;]*|default):[\\s$;]*)*$/);\n\t\t\t\t$has_break = 1 if ($rline =~ /fall[\\s_-]*(through|thru)/i);\n\t\t\t\tnext if ($fline =~ /^.[\\s$;]*$/);\n\t\t\t\t$has_statement = 1;\n\t\t\t\t$count++;\n\t\t\t\t$has_break = 1 if ($fline =~ /\\bswitch\\b|\\b(?:break\\s*;[\\s$;]*$|exit\\s*\\(\\b|return\\b|goto\\b|continue\\b)/);\n\t\t\t}\n\t\t\tif (!$has_break && $has_statement) {\n\t\t\t\tWARN(\"MISSING_BREAK\",\n\t\t\t\t     \"Possible switch case/default not preceded by break or fallthrough comment\\n\" . $herecurr);\n\t\t\t}\n\t\t}\n\n# check for /* fallthrough */ like comment, prefer fallthrough;\n\t\tmy @fallthroughs = (\n\t\t\t'fallthrough',\n\t\t\t'@fallthrough@',\n\t\t\t'lint -fallthrough[ \\t]*',\n\t\t\t'intentional(?:ly)?[ \\t]*fall(?:(?:s | |-)[Tt]|t)hr(?:ough|u|ew)',\n\t\t\t'(?:else,?\\s*)?FALL(?:S | |-)?THR(?:OUGH|U|EW)[ \\t.!]*(?:-[^\\n\\r]*)?',\n\t\t\t'Fall(?:(?:s | |-)[Tt]|t)hr(?:ough|u|ew)[ \\t.!]*(?:-[^\\n\\r]*)?',\n\t\t\t'fall(?:s | |-)?thr(?:ough|u|ew)[ \\t.!]*(?:-[^\\n\\r]*)?',\n\t\t    );\n\t\tif ($raw_comment ne '') {\n\t\t\tforeach my $ft (@fallthroughs) {\n\t\t\t\tif ($raw_comment =~ /$ft/) {\n\t\t\t\t\tmy $msg_level = \\&WARN;\n\t\t\t\t\t$msg_level = \\&CHK if ($file);\n\t\t\t\t\t&{$msg_level}(\"PREFER_FALLTHROUGH\",\n\t\t\t\t\t\t      \"Prefer 'fallthrough;' over fallthrough comment\\n\" . $herecurr);\n\t\t\t\t\tlast;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n# check for switch/default statements without a break;\n\t\tif ($perl_version_ok &&\n\t\t    defined $stat &&\n\t\t    $stat =~ /^\\+[$;\\s]*(?:case[$;\\s]+\\w+[$;\\s]*:[$;\\s]*|)*[$;\\s]*\\bdefault[$;\\s]*:[$;\\s]*;/g) {\n\t\t\tmy $cnt = statement_rawlines($stat);\n\t\t\tmy $herectx = get_stat_here($linenr, $cnt, $here);\n\n\t\t\tWARN(\"DEFAULT_NO_BREAK\",\n\t\t\t     \"switch default: should use break\\n\" . $herectx);\n\t\t}\n\n# check for gcc specific __FUNCTION__\n\t\tif ($line =~ /\\b__FUNCTION__\\b/) {\n\t\t\tif (WARN(\"USE_FUNC\",\n\t\t\t\t \"__func__ should be used instead of gcc specific __FUNCTION__\\n\"  . $herecurr) &&\n\t\t\t    $fix) {\n\t\t\t\t$fixed[$fixlinenr] =~ s/\\b__FUNCTION__\\b/__func__/g;\n\t\t\t}\n\t\t}\n\n# check for uses of __DATE__, __TIME__, __TIMESTAMP__\n\t\twhile ($line =~ /\\b(__(?:DATE|TIME|TIMESTAMP)__)\\b/g) {\n\t\t\tERROR(\"DATE_TIME\",\n\t\t\t      \"Use of the '$1' macro makes the build non-deterministic\\n\" . $herecurr);\n\t\t}\n\n# check for use of yield()\n\t\tif ($line =~ /\\byield\\s*\\(\\s*\\)/) {\n\t\t\tWARN(\"YIELD\",\n\t\t\t     \"Using yield() is generally wrong. See yield() kernel-doc (sched/core.c)\\n\"  . $herecurr);\n\t\t}\n\n# check for comparisons against true and false\n\t\tif ($line =~ /\\+\\s*(.*?)\\b(true|false|$Lval)\\s*(==|\\!=)\\s*(true|false|$Lval)\\b(.*)$/i) {\n\t\t\tmy $lead = $1;\n\t\t\tmy $arg = $2;\n\t\t\tmy $test = $3;\n\t\t\tmy $otype = $4;\n\t\t\tmy $trail = $5;\n\t\t\tmy $op = \"!\";\n\n\t\t\t($arg, $otype) = ($otype, $arg) if ($arg =~ /^(?:true|false)$/i);\n\n\t\t\tmy $type = lc($otype);\n\t\t\tif ($type =~ /^(?:true|false)$/) {\n\t\t\t\tif ((\"$test\" eq \"==\" && \"$type\" eq \"true\") ||\n\t\t\t\t    (\"$test\" eq \"!=\" && \"$type\" eq \"false\")) {\n\t\t\t\t\t$op = \"\";\n\t\t\t\t}\n\n\t\t\t\tCHK(\"BOOL_COMPARISON\",\n\t\t\t\t    \"Using comparison to $otype is error prone\\n\" . $herecurr);\n\n## maybe suggesting a correct construct would better\n##\t\t\t\t    \"Using comparison to $otype is error prone.  Perhaps use '${lead}${op}${arg}${trail}'\\n\" . $herecurr);\n\n\t\t\t}\n\t\t}\n\n# check for semaphores initialized locked\n\t\tif ($line =~ /^.\\s*sema_init.+,\\W?0\\W?\\)/) {\n\t\t\tWARN(\"CONSIDER_COMPLETION\",\n\t\t\t     \"consider using a completion\\n\" . $herecurr);\n\t\t}\n\n# recommend kstrto* over simple_strto* and strict_strto*\n\t\tif ($line =~ /\\b((simple|strict)_(strto(l|ll|ul|ull)))\\s*\\(/) {\n\t\t\tWARN(\"CONSIDER_KSTRTO\",\n\t\t\t     \"$1 is obsolete, use k$3 instead\\n\" . $herecurr);\n\t\t}\n\n# check for __initcall(), use device_initcall() explicitly or more appropriate function please\n\t\tif ($line =~ /^.\\s*__initcall\\s*\\(/) {\n\t\t\tWARN(\"USE_DEVICE_INITCALL\",\n\t\t\t     \"please use device_initcall() or more appropriate function instead of __initcall() (see include/linux/init.h)\\n\" . $herecurr);\n\t\t}\n\n# check for spin_is_locked(), suggest lockdep instead\n\t\tif ($line =~ /\\bspin_is_locked\\(/) {\n\t\t\tWARN(\"USE_LOCKDEP\",\n\t\t\t     \"Where possible, use lockdep_assert_held instead of assertions based on spin_is_locked\\n\" . $herecurr);\n\t\t}\n\n# check for deprecated apis\n\t\tif ($line =~ /\\b($deprecated_apis_search)\\b\\s*\\(/) {\n\t\t\tmy $deprecated_api = $1;\n\t\t\tmy $new_api = $deprecated_apis{$deprecated_api};\n\t\t\tWARN(\"DEPRECATED_API\",\n\t\t\t     \"Deprecated use of '$deprecated_api', prefer '$new_api' instead\\n\" . $herecurr);\n\t\t}\n\n# check for various structs that are normally const (ops, kgdb, device_tree)\n# and avoid what seem like struct definitions 'struct foo {'\n\t\tif ($line !~ /\\bconst\\b/ &&\n\t\t    $line =~ /\\bstruct\\s+($const_structs)\\b(?!\\s*\\{)/) {\n\t\t\tWARN(\"CONST_STRUCT\",\n\t\t\t     \"struct $1 should normally be const\\n\" . $herecurr);\n\t\t}\n\n# use of NR_CPUS is usually wrong\n# ignore definitions of NR_CPUS and usage to define arrays as likely right\n\t\tif ($line =~ /\\bNR_CPUS\\b/ &&\n\t\t    $line !~ /^.\\s*\\s*#\\s*if\\b.*\\bNR_CPUS\\b/ &&\n\t\t    $line !~ /^.\\s*\\s*#\\s*define\\b.*\\bNR_CPUS\\b/ &&\n\t\t    $line !~ /^.\\s*$Declare\\s.*\\[[^\\]]*NR_CPUS[^\\]]*\\]/ &&\n\t\t    $line !~ /\\[[^\\]]*\\.\\.\\.[^\\]]*NR_CPUS[^\\]]*\\]/ &&\n\t\t    $line !~ /\\[[^\\]]*NR_CPUS[^\\]]*\\.\\.\\.[^\\]]*\\]/)\n\t\t{\n\t\t\tWARN(\"NR_CPUS\",\n\t\t\t     \"usage of NR_CPUS is often wrong - consider using cpu_possible(), num_possible_cpus(), for_each_possible_cpu(), etc\\n\" . $herecurr);\n\t\t}\n\n# Use of __ARCH_HAS_<FOO> or ARCH_HAVE_<BAR> is wrong.\n\t\tif ($line =~ /\\+\\s*#\\s*define\\s+((?:__)?ARCH_(?:HAS|HAVE)\\w*)\\b/) {\n\t\t\tERROR(\"DEFINE_ARCH_HAS\",\n\t\t\t      \"#define of '$1' is wrong - use Kconfig variables or standard guards instead\\n\" . $herecurr);\n\t\t}\n\n# likely/unlikely comparisons similar to \"(likely(foo) > 0)\"\n\t\tif ($perl_version_ok &&\n\t\t    $line =~ /\\b((?:un)?likely)\\s*\\(\\s*$FuncArg\\s*\\)\\s*$Compare/) {\n\t\t\tWARN(\"LIKELY_MISUSE\",\n\t\t\t     \"Using $1 should generally have parentheses around the comparison\\n\" . $herecurr);\n\t\t}\n\n# nested likely/unlikely calls\n\t\tif ($line =~ /\\b(?:(?:un)?likely)\\s*\\(\\s*!?\\s*(IS_ERR(?:_OR_NULL|_VALUE)?|WARN)/) {\n\t\t\tWARN(\"LIKELY_MISUSE\",\n\t\t\t     \"nested (un)?likely() calls, $1 already uses unlikely() internally\\n\" . $herecurr);\n\t\t}\n\n# whine mightly about in_atomic\n\t\tif ($line =~ /\\bin_atomic\\s*\\(/) {\n\t\t\tif ($realfile =~ m@^drivers/@) {\n\t\t\t\tERROR(\"IN_ATOMIC\",\n\t\t\t\t      \"do not use in_atomic in drivers\\n\" . $herecurr);\n\t\t\t} elsif ($realfile !~ m@^kernel/@) {\n\t\t\t\tWARN(\"IN_ATOMIC\",\n\t\t\t\t     \"use of in_atomic() is incorrect outside core kernel code\\n\" . $herecurr);\n\t\t\t}\n\t\t}\n\n# check for mutex_trylock_recursive usage\n\t\tif ($line =~ /mutex_trylock_recursive/) {\n\t\t\tERROR(\"LOCKING\",\n\t\t\t      \"recursive locking is bad, do not use this ever.\\n\" . $herecurr);\n\t\t}\n\n# check for lockdep_set_novalidate_class\n\t\tif ($line =~ /^.\\s*lockdep_set_novalidate_class\\s*\\(/ ||\n\t\t    $line =~ /__lockdep_no_validate__\\s*\\)/ ) {\n\t\t\tif ($realfile !~ m@^kernel/lockdep@ &&\n\t\t\t    $realfile !~ m@^include/linux/lockdep@ &&\n\t\t\t    $realfile !~ m@^drivers/base/core@) {\n\t\t\t\tERROR(\"LOCKDEP\",\n\t\t\t\t      \"lockdep_no_validate class is reserved for device->mutex.\\n\" . $herecurr);\n\t\t\t}\n\t\t}\n\n\t\tif ($line =~ /debugfs_create_\\w+.*\\b$mode_perms_world_writable\\b/ ||\n\t\t    $line =~ /DEVICE_ATTR.*\\b$mode_perms_world_writable\\b/) {\n\t\t\tWARN(\"EXPORTED_WORLD_WRITABLE\",\n\t\t\t     \"Exporting world writable files is usually an error. Consider more restrictive permissions.\\n\" . $herecurr);\n\t\t}\n\n# check for DEVICE_ATTR uses that could be DEVICE_ATTR_<FOO>\n# and whether or not function naming is typical and if\n# DEVICE_ATTR permissions uses are unusual too\n\t\tif ($perl_version_ok &&\n\t\t    defined $stat &&\n\t\t    $stat =~ /\\bDEVICE_ATTR\\s*\\(\\s*(\\w+)\\s*,\\s*\\(?\\s*(\\s*(?:${multi_mode_perms_string_search}|0[0-7]{3,3})\\s*)\\s*\\)?\\s*,\\s*(\\w+)\\s*,\\s*(\\w+)\\s*\\)/) {\n\t\t\tmy $var = $1;\n\t\t\tmy $perms = $2;\n\t\t\tmy $show = $3;\n\t\t\tmy $store = $4;\n\t\t\tmy $octal_perms = perms_to_octal($perms);\n\t\t\tif ($show =~ /^${var}_show$/ &&\n\t\t\t    $store =~ /^${var}_store$/ &&\n\t\t\t    $octal_perms eq \"0644\") {\n\t\t\t\tif (WARN(\"DEVICE_ATTR_RW\",\n\t\t\t\t\t \"Use DEVICE_ATTR_RW\\n\" . $herecurr) &&\n\t\t\t\t    $fix) {\n\t\t\t\t\t$fixed[$fixlinenr] =~ s/\\bDEVICE_ATTR\\s*\\(\\s*$var\\s*,\\s*\\Q$perms\\E\\s*,\\s*$show\\s*,\\s*$store\\s*\\)/DEVICE_ATTR_RW(${var})/;\n\t\t\t\t}\n\t\t\t} elsif ($show =~ /^${var}_show$/ &&\n\t\t\t\t $store =~ /^NULL$/ &&\n\t\t\t\t $octal_perms eq \"0444\") {\n\t\t\t\tif (WARN(\"DEVICE_ATTR_RO\",\n\t\t\t\t\t \"Use DEVICE_ATTR_RO\\n\" . $herecurr) &&\n\t\t\t\t    $fix) {\n\t\t\t\t\t$fixed[$fixlinenr] =~ s/\\bDEVICE_ATTR\\s*\\(\\s*$var\\s*,\\s*\\Q$perms\\E\\s*,\\s*$show\\s*,\\s*NULL\\s*\\)/DEVICE_ATTR_RO(${var})/;\n\t\t\t\t}\n\t\t\t} elsif ($show =~ /^NULL$/ &&\n\t\t\t\t $store =~ /^${var}_store$/ &&\n\t\t\t\t $octal_perms eq \"0200\") {\n\t\t\t\tif (WARN(\"DEVICE_ATTR_WO\",\n\t\t\t\t\t \"Use DEVICE_ATTR_WO\\n\" . $herecurr) &&\n\t\t\t\t    $fix) {\n\t\t\t\t\t$fixed[$fixlinenr] =~ s/\\bDEVICE_ATTR\\s*\\(\\s*$var\\s*,\\s*\\Q$perms\\E\\s*,\\s*NULL\\s*,\\s*$store\\s*\\)/DEVICE_ATTR_WO(${var})/;\n\t\t\t\t}\n\t\t\t} elsif ($octal_perms eq \"0644\" ||\n\t\t\t\t $octal_perms eq \"0444\" ||\n\t\t\t\t $octal_perms eq \"0200\") {\n\t\t\t\tmy $newshow = \"$show\";\n\t\t\t\t$newshow = \"${var}_show\" if ($show ne \"NULL\" && $show ne \"${var}_show\");\n\t\t\t\tmy $newstore = $store;\n\t\t\t\t$newstore = \"${var}_store\" if ($store ne \"NULL\" && $store ne \"${var}_store\");\n\t\t\t\tmy $rename = \"\";\n\t\t\t\tif ($show ne $newshow) {\n\t\t\t\t\t$rename .= \" '$show' to '$newshow'\";\n\t\t\t\t}\n\t\t\t\tif ($store ne $newstore) {\n\t\t\t\t\t$rename .= \" '$store' to '$newstore'\";\n\t\t\t\t}\n\t\t\t\tWARN(\"DEVICE_ATTR_FUNCTIONS\",\n\t\t\t\t     \"Consider renaming function(s)$rename\\n\" . $herecurr);\n\t\t\t} else {\n\t\t\t\tWARN(\"DEVICE_ATTR_PERMS\",\n\t\t\t\t     \"DEVICE_ATTR unusual permissions '$perms' used\\n\" . $herecurr);\n\t\t\t}\n\t\t}\n\n# Mode permission misuses where it seems decimal should be octal\n# This uses a shortcut match to avoid unnecessary uses of a slow foreach loop\n# o Ignore module_param*(...) uses with a decimal 0 permission as that has a\n#   specific definition of not visible in sysfs.\n# o Ignore proc_create*(...) uses with a decimal 0 permission as that means\n#   use the default permissions\n\t\tif ($perl_version_ok &&\n\t\t    defined $stat &&\n\t\t    $line =~ /$mode_perms_search/) {\n\t\t\tforeach my $entry (@mode_permission_funcs) {\n\t\t\t\tmy $func = $entry->[0];\n\t\t\t\tmy $arg_pos = $entry->[1];\n\n\t\t\t\tmy $lc = $stat =~ tr@\\n@@;\n\t\t\t\t$lc = $lc + $linenr;\n\t\t\t\tmy $stat_real = get_stat_real($linenr, $lc);\n\n\t\t\t\tmy $skip_args = \"\";\n\t\t\t\tif ($arg_pos > 1) {\n\t\t\t\t\t$arg_pos--;\n\t\t\t\t\t$skip_args = \"(?:\\\\s*$FuncArg\\\\s*,\\\\s*){$arg_pos,$arg_pos}\";\n\t\t\t\t}\n\t\t\t\tmy $test = \"\\\\b$func\\\\s*\\\\(${skip_args}($FuncArg(?:\\\\|\\\\s*$FuncArg)*)\\\\s*[,\\\\)]\";\n\t\t\t\tif ($stat =~ /$test/) {\n\t\t\t\t\tmy $val = $1;\n\t\t\t\t\t$val = $6 if ($skip_args ne \"\");\n\t\t\t\t\tif (!($func =~ /^(?:module_param|proc_create)/ && $val eq \"0\") &&\n\t\t\t\t\t    (($val =~ /^$Int$/ && $val !~ /^$Octal$/) ||\n\t\t\t\t\t     ($val =~ /^$Octal$/ && length($val) ne 4))) {\n\t\t\t\t\t\tERROR(\"NON_OCTAL_PERMISSIONS\",\n\t\t\t\t\t\t      \"Use 4 digit octal (0777) not decimal permissions\\n\" . \"$here\\n\" . $stat_real);\n\t\t\t\t\t}\n\t\t\t\t\tif ($val =~ /^$Octal$/ && (oct($val) & 02)) {\n\t\t\t\t\t\tERROR(\"EXPORTED_WORLD_WRITABLE\",\n\t\t\t\t\t\t      \"Exporting writable files is usually an error. Consider more restrictive permissions.\\n\" . \"$here\\n\" . $stat_real);\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n# check for uses of S_<PERMS> that could be octal for readability\n\t\twhile ($line =~ m{\\b($multi_mode_perms_string_search)\\b}g) {\n\t\t\tmy $oval = $1;\n\t\t\tmy $octal = perms_to_octal($oval);\n\t\t\tif (WARN(\"SYMBOLIC_PERMS\",\n\t\t\t\t \"Symbolic permissions '$oval' are not preferred. Consider using octal permissions '$octal'.\\n\" . $herecurr) &&\n\t\t\t    $fix) {\n\t\t\t\t$fixed[$fixlinenr] =~ s/\\Q$oval\\E/$octal/;\n\t\t\t}\n\t\t}\n\n# validate content of MODULE_LICENSE against list from include/linux/module.h\n\t\tif ($line =~ /\\bMODULE_LICENSE\\s*\\(\\s*($String)\\s*\\)/) {\n\t\t\tmy $extracted_string = get_quoted_string($line, $rawline);\n\t\t\tmy $valid_licenses = qr{\n\t\t\t\t\t\tGPL|\n\t\t\t\t\t\tGPL\\ v2|\n\t\t\t\t\t\tGPL\\ and\\ additional\\ rights|\n\t\t\t\t\t\tDual\\ BSD/GPL|\n\t\t\t\t\t\tDual\\ MIT/GPL|\n\t\t\t\t\t\tDual\\ MPL/GPL|\n\t\t\t\t\t\tProprietary\n\t\t\t\t\t}x;\n\t\t\tif ($extracted_string !~ /^\"(?:$valid_licenses)\"$/x) {\n\t\t\t\tWARN(\"MODULE_LICENSE\",\n\t\t\t\t     \"unknown module license \" . $extracted_string . \"\\n\" . $herecurr);\n\t\t\t}\n\t\t}\n\n# check for sysctl duplicate constants\n\t\tif ($line =~ /\\.extra[12]\\s*=\\s*&(zero|one|int_max)\\b/) {\n\t\t\tWARN(\"DUPLICATED_SYSCTL_CONST\",\n\t\t\t\t\"duplicated sysctl range checking value '$1', consider using the shared one in include/linux/sysctl.h\\n\" . $herecurr);\n\t\t}\n\t}\n\n\t# If we have no input at all, then there is nothing to report on\n\t# so just keep quiet.\n\tif ($#rawlines == -1) {\n\t\texit(0);\n\t}\n\n\t# In mailback mode only produce a report in the negative, for\n\t# things that appear to be patches.\n\tif ($mailback && ($clean == 1 || !$is_patch)) {\n\t\texit(0);\n\t}\n\n\t# This is not a patch, and we are are in 'no-patch' mode so\n\t# just keep quiet.\n\tif (!$chk_patch && !$is_patch) {\n\t\texit(0);\n\t}\n\n\tif (!$is_patch && $filename !~ /cover-letter\\.patch$/) {\n\t\tERROR(\"NOT_UNIFIED_DIFF\",\n\t\t      \"Does not appear to be a unified-diff format patch\\n\");\n\t}\n\tif ($is_patch && $has_commit_log && $chk_signoff) {\n\t\tif ($signoff == 0) {\n\t\t\tERROR(\"MISSING_SIGN_OFF\",\n\t\t\t      \"Missing Signed-off-by: line(s)\\n\");\n\t\t} elsif (!$authorsignoff) {\n\t\t\tWARN(\"NO_AUTHOR_SIGN_OFF\",\n\t\t\t     \"Missing Signed-off-by: line by nominal patch author '$author'\\n\");\n\t\t}\n\t}\n\n\tprint report_dump();\n\tif ($summary && !($clean == 1 && $quiet == 1)) {\n\t\tprint \"$filename \" if ($summary_file);\n\t\tprint \"total: $cnt_error errors, $cnt_warn warnings, \" .\n\t\t\t(($check)? \"$cnt_chk checks, \" : \"\") .\n\t\t\t\"$cnt_lines lines checked\\n\";\n\t}\n\n\tif ($quiet == 0) {\n\t\t# If there were any defects found and not already fixing them\n\t\tif (!$clean and !$fix) {\n\t\t\tprint << \"EOM\"\n\nNOTE: For some of the reported defects, checkpatch may be able to\n      mechanically convert to the typical style using --fix or --fix-inplace.\nEOM\n\t\t}\n\t\t# If there were whitespace errors which cleanpatch can fix\n\t\t# then suggest that.\n\t\tif ($rpt_cleaners) {\n\t\t\t$rpt_cleaners = 0;\n\t\t\tprint << \"EOM\"\n\nNOTE: Whitespace errors detected.\n      You may wish to use scripts/cleanpatch or scripts/cleanfile\nEOM\n\t\t}\n\t}\n\n\tif ($clean == 0 && $fix &&\n\t    (\"@rawlines\" ne \"@fixed\" ||\n\t     $#fixed_inserted >= 0 || $#fixed_deleted >= 0)) {\n\t\tmy $newfile = $filename;\n\t\t$newfile .= \".EXPERIMENTAL-checkpatch-fixes\" if (!$fix_inplace);\n\t\tmy $linecount = 0;\n\t\tmy $f;\n\n\t\t@fixed = fix_inserted_deleted_lines(\\@fixed, \\@fixed_inserted, \\@fixed_deleted);\n\n\t\topen($f, '>', $newfile)\n\t\t    or die \"$P: Can't open $newfile for write\\n\";\n\t\tforeach my $fixed_line (@fixed) {\n\t\t\t$linecount++;\n\t\t\tif ($file) {\n\t\t\t\tif ($linecount > 3) {\n\t\t\t\t\t$fixed_line =~ s/^\\+//;\n\t\t\t\t\tprint $f $fixed_line . \"\\n\";\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\tprint $f $fixed_line . \"\\n\";\n\t\t\t}\n\t\t}\n\t\tclose($f);\n\n\t\tif (!$quiet) {\n\t\t\tprint << \"EOM\";\n\nWrote EXPERIMENTAL --fix correction(s) to '$newfile'\n\nDo _NOT_ trust the results written to this file.\nDo _NOT_ submit these changes without inspecting them for correctness.\n\nThis EXPERIMENTAL file is simply a convenience to help rewrite patches.\nNo warranties, expressed or implied...\nEOM\n\t\t}\n\t}\n\n\tif ($quiet == 0) {\n\t\tprint \"\\n\";\n\t\tif ($clean == 1) {\n\t\t\tprint \"$vname has no obvious style problems and is ready for submission.\\n\";\n\t\t} else {\n\t\t\tprint \"$vname has style problems, please review.\\n\";\n\t\t}\n\t}\n\treturn $clean;\n}\n"
  },
  {
    "path": "scripts/clean-package.sh",
    "content": "#!/usr/bin/env bash\nIFS=$'\\n'\n[ -n \"$1\" -a -n \"$2\" ] || {\n\techo \"Usage: $0 <file> <directory>\"\n\texit 1\n}\n[ -f \"$1\" -a -d \"$2\" ] || {\n\techo \"File/directory not found\"\n\texit 1\n}\ncat \"$1\" | (\n\tcd \"$2\"\n\twhile read entry; do\n\t\t[ -n \"$entry\" ] || break\n\t\t[ ! -d \"$entry\" ] || [ -L \"$entry\" ] && rm -f \"$entry\"\n\tdone\n)\nsort -r \"$1\" | (\n\tcd \"$2\"\n\twhile read entry; do\n\t\t[ -n \"$entry\" ] || break\n\t\t[ -d \"$entry\" ] && rmdir \"$entry\" > /dev/null 2>&1\n\tdone\n)\ntrue\n"
  },
  {
    "path": "scripts/cleanfile",
    "content": "#!/usr/bin/env perl\n#\n# Clean a text file -- or directory of text files -- of stealth whitespace.\n# WARNING: this can be a highly destructive operation.  Use with caution.\n#\n\nuse bytes;\nuse File::Basename;\nuse warnings;\n\n# Default options\n$max_width = 79;\n\n# Clean up space-tab sequences, either by removing spaces or\n# replacing them with tabs.\nsub clean_space_tabs($)\n{\n    no bytes;\t\t\t# Tab alignment depends on characters\n\n    my($li) = @_;\n    my($lo) = '';\n    my $pos = 0;\n    my $nsp = 0;\n    my($i, $c);\n\n    for ($i = 0; $i < length($li); $i++) {\n\t$c = substr($li, $i, 1);\n\tif ($c eq \"\\t\") {\n\t    my $npos = ($pos+$nsp+8) & ~7;\n\t    my $ntab = ($npos >> 3) - ($pos >> 3);\n\t    $lo .= \"\\t\" x $ntab;\n\t    $pos = $npos;\n\t    $nsp = 0;\n\t} elsif ($c eq \"\\n\" || $c eq \"\\r\") {\n\t    $lo .= \" \" x $nsp;\n\t    $pos += $nsp;\n\t    $nsp = 0;\n\t    $lo .= $c;\n\t    $pos = 0;\n\t} elsif ($c eq \" \") {\n\t    $nsp++;\n\t} else {\n\t    $lo .= \" \" x $nsp;\n\t    $pos += $nsp;\n\t    $nsp = 0;\n\t    $lo .= $c;\n\t    $pos++;\n\t}\n    }\n    $lo .= \" \" x $nsp;\n    return $lo;\n}\n\n# Compute the visual width of a string\nsub strwidth($) {\n    no bytes;\t\t\t# Tab alignment depends on characters\n\n    my($li) = @_;\n    my($c, $i);\n    my $pos = 0;\n    my $mlen = 0;\n\n    for ($i = 0; $i < length($li); $i++) {\n\t$c = substr($li,$i,1);\n\tif ($c eq \"\\t\") {\n\t    $pos = ($pos+8) & ~7;\n\t} elsif ($c eq \"\\n\") {\n\t    $mlen = $pos if ($pos > $mlen);\n\t    $pos = 0;\n\t} else {\n\t    $pos++;\n\t}\n    }\n\n    $mlen = $pos if ($pos > $mlen);\n    return $mlen;\n}\n\n$name = basename($0);\n\n@files = ();\n\nwhile (defined($a = shift(@ARGV))) {\n    if ($a =~ /^-/) {\n\tif ($a eq '-width' || $a eq '-w') {\n\t    $max_width = shift(@ARGV)+0;\n\t} else {\n\t    print STDERR \"Usage: $name [-width #] files...\\n\";\n\t    exit 1;\n\t}\n    } else {\n\tpush(@files, $a);\n    }\n}\n\nforeach $f ( @files ) {\n    print STDERR \"$name: $f\\n\";\n\n    if (! -f $f) {\n\tprint STDERR \"$f: not a file\\n\";\n\tnext;\n    }\n\n    if (!open(FILE, '+<', $f)) {\n\tprint STDERR \"$name: Cannot open file: $f: $!\\n\";\n\tnext;\n    }\n\n    binmode FILE;\n\n    # First, verify that it is not a binary file; consider any file\n    # with a zero byte to be a binary file.  Is there any better, or\n    # additional, heuristic that should be applied?\n    $is_binary = 0;\n\n    while (read(FILE, $data, 65536) > 0) {\n\tif ($data =~ /\\0/) {\n\t    $is_binary = 1;\n\t    last;\n\t}\n    }\n\n    if ($is_binary) {\n\tprint STDERR \"$name: $f: binary file\\n\";\n\tnext;\n    }\n\n    seek(FILE, 0, 0);\n\n    $in_bytes = 0;\n    $out_bytes = 0;\n    $blank_bytes = 0;\n\n    @blanks = ();\n    @lines  = ();\n    $lineno = 0;\n\n    while ( defined($line = <FILE>) ) {\n\t$lineno++;\n\t$in_bytes += length($line);\n\t$line =~ s/[ \\t\\r]*$//;\t\t# Remove trailing spaces\n\t$line = clean_space_tabs($line);\n\n\tif ( $line eq \"\\n\" ) {\n\t    push(@blanks, $line);\n\t    $blank_bytes += length($line);\n\t} else {\n\t    push(@lines, @blanks);\n\t    $out_bytes += $blank_bytes;\n\t    push(@lines, $line);\n\t    $out_bytes += length($line);\n\t    @blanks = ();\n\t    $blank_bytes = 0;\n\t}\n\n\t$l_width = strwidth($line);\n\tif ($max_width && $l_width > $max_width) {\n\t    print STDERR\n\t\t\"$f:$lineno: line exceeds $max_width characters ($l_width)\\n\";\n\t}\n    }\n\n    # Any blanks at the end of the file are discarded\n\n    if ($in_bytes != $out_bytes) {\n\t# Only write to the file if changed\n\tseek(FILE, 0, 0);\n\tprint FILE @lines;\n\n\tif ( !defined($where = tell(FILE)) ||\n\t     !truncate(FILE, $where) ) {\n\t    die \"$name: Failed to truncate modified file: $f: $!\\n\";\n\t}\n    }\n\n    close(FILE);\n}\n"
  },
  {
    "path": "scripts/cleanpatch",
    "content": "#!/usr/bin/env perl \n#\n# Clean a patch file -- or directory of patch files -- of stealth whitespace.\n# WARNING: this can be a highly destructive operation.  Use with caution.\n#\n\nuse bytes;\nuse File::Basename;\nuse warnings;\n\n# Default options\n$max_width = 79;\n\n# Clean up space-tab sequences, either by removing spaces or\n# replacing them with tabs.\nsub clean_space_tabs($)\n{\n    no bytes;\t\t\t# Tab alignment depends on characters\n\n    my($li) = @_;\n    my($lo) = '';\n    my $pos = 0;\n    my $nsp = 0;\n    my($i, $c);\n\n    for ($i = 0; $i < length($li); $i++) {\n\t$c = substr($li, $i, 1);\n\tif ($c eq \"\\t\") {\n\t    my $npos = ($pos+$nsp+8) & ~7;\n\t    my $ntab = ($npos >> 3) - ($pos >> 3);\n\t    $lo .= \"\\t\" x $ntab;\n\t    $pos = $npos;\n\t    $nsp = 0;\n\t} elsif ($c eq \"\\n\" || $c eq \"\\r\") {\n\t    $lo .= \" \" x $nsp;\n\t    $pos += $nsp;\n\t    $nsp = 0;\n\t    $lo .= $c;\n\t    $pos = 0;\n\t} elsif ($c eq \" \") {\n\t    $nsp++;\n\t} else {\n\t    $lo .= \" \" x $nsp;\n\t    $pos += $nsp;\n\t    $nsp = 0;\n\t    $lo .= $c;\n\t    $pos++;\n\t}\n    }\n    $lo .= \" \" x $nsp;\n    return $lo;\n}\n\n# Compute the visual width of a string\nsub strwidth($) {\n    no bytes;\t\t\t# Tab alignment depends on characters\n\n    my($li) = @_;\n    my($c, $i);\n    my $pos = 0;\n    my $mlen = 0;\n\n    for ($i = 0; $i < length($li); $i++) {\n\t$c = substr($li,$i,1);\n\tif ($c eq \"\\t\") {\n\t    $pos = ($pos+8) & ~7;\n\t} elsif ($c eq \"\\n\") {\n\t    $mlen = $pos if ($pos > $mlen);\n\t    $pos = 0;\n\t} else {\n\t    $pos++;\n\t}\n    }\n\n    $mlen = $pos if ($pos > $mlen);\n    return $mlen;\n}\n\n$name = basename($0);\n\n@files = ();\n\nwhile (defined($a = shift(@ARGV))) {\n    if ($a =~ /^-/) {\n\tif ($a eq '-width' || $a eq '-w') {\n\t    $max_width = shift(@ARGV)+0;\n\t} else {\n\t    print STDERR \"Usage: $name [-width #] files...\\n\";\n\t    exit 1;\n\t}\n    } else {\n\tpush(@files, $a);\n    }\n}\n\nforeach $f ( @files ) {\n    print STDERR \"$name: $f\\n\";\n\n    if (! -f $f) {\n\tprint STDERR \"$f: not a file\\n\";\n\tnext;\n    }\n\n    if (!open(FILE, '+<', $f)) {\n\tprint STDERR \"$name: Cannot open file: $f: $!\\n\";\n\tnext;\n    }\n\n    binmode FILE;\n\n    # First, verify that it is not a binary file; consider any file\n    # with a zero byte to be a binary file.  Is there any better, or\n    # additional, heuristic that should be applied?\n    $is_binary = 0;\n\n    while (read(FILE, $data, 65536) > 0) {\n\tif ($data =~ /\\0/) {\n\t    $is_binary = 1;\n\t    last;\n\t}\n    }\n\n    if ($is_binary) {\n\tprint STDERR \"$name: $f: binary file\\n\";\n\tnext;\n    }\n\n    seek(FILE, 0, 0);\n\n    $in_bytes = 0;\n    $out_bytes = 0;\n    $lineno = 0;\n\n    @lines  = ();\n\n    $in_hunk = 0;\n    $err = 0;\n\n    while ( defined($line = <FILE>) ) {\n\t$lineno++;\n\t$in_bytes += length($line);\n\n\tif (!$in_hunk) {\n\t    if ($line =~\n\t\t/^\\@\\@\\s+\\-([0-9]+),([0-9]+)\\s+\\+([0-9]+),([0-9]+)\\s\\@\\@/) {\n\t\t$minus_lines = $2;\n\t\t$plus_lines = $4;\n\t\tif ($minus_lines || $plus_lines) {\n\t\t    $in_hunk = 1;\n\t\t    @hunk_lines = ($line);\n\t\t}\n\t    } else {\n\t\tpush(@lines, $line);\n\t\t$out_bytes += length($line);\n\t    }\n\t} else {\n\t    # We're in a hunk\n\n\t    if ($line =~ /^\\+/) {\n\t\t$plus_lines--;\n\n\t\t$text = substr($line, 1);\n\t\t$text =~ s/[ \\t\\r]*$//;\t\t# Remove trailing spaces\n\t\t$text = clean_space_tabs($text);\n\n\t\t$l_width = strwidth($text);\n\t\tif ($max_width && $l_width > $max_width) {\n\t\t    print STDERR\n\t\t\t\"$f:$lineno: adds line exceeds $max_width \",\n\t\t\t\"characters ($l_width)\\n\";\n\t\t}\n\n\t\tpush(@hunk_lines, '+'.$text);\n\t    } elsif ($line =~ /^\\-/) {\n\t\t$minus_lines--;\n\t\tpush(@hunk_lines, $line);\n\t    } elsif ($line =~ /^ /) {\n\t\t$plus_lines--;\n\t\t$minus_lines--;\n\t\tpush(@hunk_lines, $line);\n\t    } else {\n\t\tprint STDERR \"$name: $f: malformed patch\\n\";\n\t\t$err = 1;\n\t\tlast;\n\t    }\n\n\t    if ($plus_lines < 0 || $minus_lines < 0) {\n\t\tprint STDERR \"$name: $f: malformed patch\\n\";\n\t\t$err = 1;\n\t\tlast;\n\t    } elsif ($plus_lines == 0 && $minus_lines == 0) {\n\t\t# End of a hunk.  Process this hunk.\n\t\tmy $i;\n\t\tmy $l;\n\t\tmy @h = ();\n\t\tmy $adj = 0;\n\t\tmy $done = 0;\n\n\t\tfor ($i = scalar(@hunk_lines)-1; $i > 0; $i--) {\n\t\t    $l = $hunk_lines[$i];\n\t\t    if (!$done && $l eq \"+\\n\") {\n\t\t\t$adj++; # Skip this line\n\t\t    } elsif ($l =~ /^[ +]/) {\n\t\t\t$done = 1;\n\t\t\tunshift(@h, $l);\n\t\t    } else {\n\t\t\tunshift(@h, $l);\n\t\t    }\n\t\t}\n\n\t\t$l = $hunk_lines[0];  # Hunk header\n\t\tundef @hunk_lines;    # Free memory\n\n\t\tif ($adj) {\n\t\t    die unless\n\t\t\t($l =~ /^\\@\\@\\s+\\-([0-9]+),([0-9]+)\\s+\\+([0-9]+),([0-9]+)\\s\\@\\@(.*)$/);\n\t\t    my $mstart = $1;\n\t\t    my $mlin = $2;\n\t\t    my $pstart = $3;\n\t\t    my $plin = $4;\n\t\t    my $tail = $5; # doesn't include the final newline\n\n\t\t    $l = sprintf(\"@@ -%d,%d +%d,%d @@%s\\n\",\n\t\t\t\t $mstart, $mlin, $pstart, $plin-$adj,\n\t\t\t\t $tail);\n\t\t}\n\t\tunshift(@h, $l);\n\n\t\t# Transfer to the output array\n\t\tforeach $l (@h) {\n\t\t    $out_bytes += length($l);\n\t\t    push(@lines, $l);\n\t\t}\n\n\t\t$in_hunk = 0;\n\t    }\n\t}\n    }\n\n    if ($in_hunk) {\n\tprint STDERR \"$name: $f: malformed patch\\n\";\n\t$err = 1;\n    }\n\n    if (!$err) {\n\tif ($in_bytes != $out_bytes) {\n\t    # Only write to the file if changed\n\t    seek(FILE, 0, 0);\n\t    print FILE @lines;\n\n\t    if ( !defined($where = tell(FILE)) ||\n\t\t !truncate(FILE, $where) ) {\n\t\tdie \"$name: Failed to truncate modified file: $f: $!\\n\";\n\t    }\n\t}\n    }\n\n    close(FILE);\n}\n"
  },
  {
    "path": "scripts/combined-ext-image.sh",
    "content": "#!/bin/sh\n#\n# Copyright (C) 2011 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\n# Write image header followed by all specified files\n# The header is padded to 64k, format is:\n#  CE               magic word (\"Combined Extended Image\") (2 bytes)\n#  <CE_VERSION>     file format version field (2 bytes) \n#  <TYPE>           short description of the target device (32 bytes)\n#  <NUM FILES>      number of files following the header (2 byte)\n#  <file1_name>     name of the first file (32 bytes)\n#  <file1_length>   length of the first file encoded as zero padded 8 digit hex (8 bytes)\n#  <file1_md5>      md5 checksum of the first file (32 bytes)\n#  <fileN_name>     name of the Nth file (32 bytes)\n#  <fileN_length>   length of the Nth file encoded as zero padded 8 digit hex (8 bytes)\n#  <fileN_md5>      md5 checksum of the Nth file (32 bytes)\n\n## version history\n# * version 1: initial file format with num files / name / length / md5 checksum \n\nset -e\n\nME=\"${0##*/}\"\n\nusage() {\n\techo \"Usage: $ME <type> <ext filename> <file1> <filename1> [<file2> <filename2> <fileN> <filenameN>]\"\n\t[ \"$IMG_OUT\" ] && rm -f \"$IMG_OUT\"\n\texit 1\n}\n\n[ \"$#\" -lt 4 ] && usage\n\nCE_VERSION=1\nIMG_TYPE=$1; shift\nIMG_OUT=$1; shift\nFILE_NUM=$(($# / 2))\nFILES=\"\"\n\ntmpdir=\"$( mktemp -d 2> /dev/null )\"\nif [ -z \"$tmpdir\" ]; then\n\t# try OSX signature\n\ttmpdir=\"$( mktemp -t 'ubitmp' -d )\"\nfi\n\nif [ -z \"$tmpdir\" ]; then\n\texit 1\nfi\n\ntrap \"rm -rf $tmpdir\" EXIT\n\nIMG_TMP_OUT=\"${tmpdir}/out\"\n\nprintf \"CE%02x%-32s%02x\" $CE_VERSION \"$IMG_TYPE\" $FILE_NUM > \"${IMG_TMP_OUT}\"\n\nwhile [ \"$#\" -gt 1 ]\n   do\n      file=$1\n      filename=$2\n\n      [ ! -f \"$file\" ] && echo \"$ME: Not a valid file: $file\" && usage\n      FILES=\"$FILES $file\"\n      md5=$($MKHASH md5 \"$file\")\n      printf \"%-32s%08x%32s\" \"$filename\" $(stat -c \"%s\" \"$file\") \"${md5%% *}\" >> \"${IMG_TMP_OUT}\"\n      shift 2\n   done\n\n[ \"$#\" -eq 1 ] && echo \"$ME: Filename not specified: $1\" && usage\n\nmv \"${IMG_TMP_OUT}\" \"${IMG_TMP_OUT}\".tmp\ndd if=\"${IMG_TMP_OUT}.tmp\" of=\"${IMG_TMP_OUT}\" bs=65536 conv=sync 2>/dev/null\nrm \"${IMG_TMP_OUT}\".tmp\n\ncat $FILES >> \"${IMG_TMP_OUT}\"\ncp \"${IMG_TMP_OUT}\" \"${IMG_OUT}\"\n"
  },
  {
    "path": "scripts/combined-image.sh",
    "content": "#!/bin/sh\n\nBLKSZ=65536\n\n[ -f \"$1\" -a -f \"$2\" ] || {\n\techo \"Usage: $0 <kernel image> <rootfs image> [output file]\"\n\texit 1\n}\n\nIMAGE=${3:-openwrt-combined.img}\n\n# Make sure provided images are 64k aligned.\nkern=\"${IMAGE}.kernel\"\nroot=\"${IMAGE}.rootfs\"\ndd if=\"$1\" of=\"$kern\" bs=$BLKSZ conv=sync 2>/dev/null\ndd if=\"$2\" of=\"$root\" bs=$BLKSZ conv=sync 2>/dev/null\n\n# Calculate md5sum over combined kernel and rootfs image.\nmd5=$(cat \"$kern\" \"$root\" | $MKHASH md5)\n\n# Write image header followed by kernel and rootfs image.\n# The header is padded to 64k, format is:\n#  CI               magic word (\"Combined Image\")\n#  <kernel length>  length of kernel encoded as zero padded 8 digit hex\n#  <rootfs length>  length of rootfs encoded as zero padded 8 digit hex\n#  <md5sum>         checksum of the combined kernel and rootfs image\n( printf \"CI%08x%08x%32s\" \\\n\t$(stat -c \"%s\" \"$kern\") $(stat -c \"%s\" \"$root\") \"${md5%% *}\" | \\\n\tdd bs=$BLKSZ conv=sync;\n  cat \"$kern\" \"$root\"\n) > ${IMAGE} 2>/dev/null\n\n# Clean up.\nrm -f \"$kern\" \"$root\"\n"
  },
  {
    "path": "scripts/command_all.sh",
    "content": "#! /bin/sh\n# SPDX-License-Identifier: GPL-2.0-or-later\n# Reduced version of which -a using command utility\n\ncase $PATH in\n\t(*[!:]:) PATH=\"$PATH:\" ;;\nesac\n\nfor ELEMENT in $(echo $PATH | tr \":\" \"\\n\"); do\n        PATH=$ELEMENT command -v \"$@\"\ndone\n"
  },
  {
    "path": "scripts/config/Makefile",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n# ===========================================================================\n# OpenWrt configuration targets\n\n.PHONY: clean all\nall: conf mconf\nclean:\n\trm -f *.o lxdialog/*.o *.moc .*.cmd $(clean-files)\n\n# This clean-files definition is here to ensure that temporary files from the\n# previous version are removed by make config-clean.\n# It should be emptied after the end of support for OpenWrt 19.07.\nclean-files\t:= zconf.tab.c zconf.lex.c zconf.hash.c .tmp_qtcheck\n\n# ===========================================================================\n# Variables needed by the upstream Makefile\n\n# Avoids displaying 'UPD mconf-cfg' in an otherwise quiet make menuconfig\nkecho:=true\n\nCONFIG_SHELL:=$(SHELL)\nsrctree:=.\nsrc:=.\nobj:=.\nQ:=$(if $V,,@)\ncmd = $(cmd_$(1))\n\n# some definitions taken from ../Kbuild.include\ndot-target = $(dir $@).$(notdir $@)\nsquote  := '\nescsq = $(subst $(squote),'\\$(squote)',$1)\ndefine filechk\n\t$(Q)set -e;\t\t\t\t\t\t\\\n\tmkdir -p $(dir $@);\t\t\t\t\t\\\n\ttrap \"rm -f $(dot-target).tmp\" EXIT;\t\t\t\\\n\t{ $(filechk_$(1)); } > $(dot-target).tmp;\t\t\\\n\tif [ ! -r $@ ] || ! cmp -s $@ $(dot-target).tmp; then\t\\\n\t\t$(kecho) '  UPD     $@';\t\t\t\\\n\t\tmv -f $(dot-target).tmp $@;\t\t\t\\\n\tfi\nendef\ncmd-check = $(if $(strip $(cmd_$@)),,1)\nmake-cmd = $(call escsq,$(subst $(pound),$$(pound),$(subst $$,$$$$,$(cmd_$(1)))))\nnewer-prereqs = $(filter-out $(PHONY),$?)\nif_changed = $(if $(newer-prereqs)$(cmd-check),\t\t\t\\\n\t$(cmd);\t\t\t\t\t\t\t\\\n\tprintf '%s\\n' 'cmd_$@ := $(make-cmd)' > $(dot-target).cmd, @:)\n\n### Stripped down upstream Makefile follows:\n# ===========================================================================\n# object files used by all kconfig flavours\ncommon-objs\t:= confdata.o expr.o lexer.lex.o menu.o parser.tab.o \\\n\t\t   preprocess.o symbol.o util.o\n\n$(obj)/lexer.lex.o: $(obj)/parser.tab.h\nHOSTCFLAGS_lexer.lex.o\t:= -I $(srctree)/$(src)\nHOSTCFLAGS_parser.tab.o\t:= -I $(srctree)/$(src)\n\n# conf: Used for defconfig, oldconfig and related targets\nhostprogs\t+= conf\nconf-objs\t:= conf.o $(common-objs)\n\n# nconf: Used for the nconfig target based on ncurses\nhostprogs\t+= nconf\nnconf-objs\t:= nconf.o nconf.gui.o $(common-objs)\n\nHOSTLDLIBS_nconf\t= $(shell . $(obj)/nconf-cfg && echo $$libs)\nHOSTCFLAGS_nconf.o\t= $(shell . $(obj)/nconf-cfg && echo $$cflags)\nHOSTCFLAGS_nconf.gui.o\t= $(shell . $(obj)/nconf-cfg && echo $$cflags)\n\n$(obj)/nconf.o $(obj)/nconf.gui.o: $(obj)/nconf-cfg\n\n# mconf: Used for the menuconfig target based on lxdialog\nhostprogs\t+= mconf\nlxdialog\t:= $(addprefix lxdialog/, \\\n\t\t     checklist.o inputbox.o menubox.o textbox.o util.o yesno.o)\nmconf-objs\t:= mconf.o $(lxdialog) $(common-objs)\n\nHOSTLDLIBS_mconf = $(shell . $(obj)/mconf-cfg && echo $$libs)\n$(foreach f, mconf.o $(lxdialog), \\\n  $(eval HOSTCFLAGS_$f = $$(shell . $(obj)/mconf-cfg && echo $$$$cflags)))\n\n$(addprefix $(obj)/, mconf.o $(lxdialog)): $(obj)/mconf-cfg\n\n# qconf: Used for the xconfig target based on Qt\nhostprogs\t+= qconf\nqconf-cxxobjs\t:= qconf.o qconf-moc.o\nqconf-objs\t:= images.o $(common-objs)\n\nHOSTLDLIBS_qconf\t= $(shell . $(obj)/qconf-cfg && echo $$libs)\nHOSTCXXFLAGS_qconf.o\t= $(shell . $(obj)/qconf-cfg && echo $$cflags)\nHOSTCXXFLAGS_qconf-moc.o = $(shell . $(obj)/qconf-cfg && echo $$cflags)\n\n$(obj)/qconf.o: $(obj)/qconf-cfg\n\nquiet_cmd_moc = MOC     $@\n      cmd_moc = $(shell . $(obj)/qconf-cfg && echo $$moc) $< -o $@\n\n$(obj)/qconf-moc.cc: $(src)/qconf.h $(obj)/qconf-cfg FORCE\n\t$(call if_changed,moc)\n\ntargets += qconf-moc.cc\n\n# check if necessary packages are available, and configure build flags\nfilechk_conf_cfg = $(CONFIG_SHELL) $<\n\n$(obj)/%conf-cfg: $(src)/%conf-cfg.sh FORCE\n\t$(call filechk,conf_cfg)\n\nclean-files += *conf-cfg\n\n# ===========================================================================\n# OpenWrt rules and final adjustments that need to be made after reading the\n# full upstream Makefile\n\nclean-files += $(targets) $(hostprogs)\n\nFORCE:\n\nifdef BUILD_SHIPPED_FILES\nshipped-files := lexer.lex.c parser.tab.c parser.tab.h\nclean-files += $(shipped-files)\n\n.SECONDARY: $(shipped-files)\n\n%.tab.c %.tab.h: %.y\n\tbison -l -d -b $* $<\n\n%.lex.c: %.l\n\tflex -L -o$@ $<\nendif\n\n$(foreach f,$(conf-objs) $(filter-out $(common-objs),$(mconf-objs) \\\n\t\t\t\t\t\t     $(qconf-objs) \\\n\t\t\t\t\t\t     $(nconf-objs)), \\\n  $(eval $(obj)/$f: CFLAGS+=$$(HOSTCFLAGS_$f)))\n\n$(foreach f,$(qconf-cxxobjs), \\\n  $(eval $(obj)/$f: CXXFLAGS+=$$(HOSTCXXFLAGS_$f)))\n\n$(obj)/conf: $(addprefix $(obj)/,$(conf-objs))\n\n# The *conf-cfg file is used (then filtered out) as the first prerequisite to\n# avoid sourcing it before the script is built, when trying to compute CFLAGS\n# for the actual first prerequisite.  This avoids errors like:\n# '/bin/sh: ./mconf-cfg: No such file or directory'\n$(obj)/mconf: mconf-cfg $(addprefix $(obj)/,$(mconf-objs))\n\t$(CC) -o $@ $(filter-out mconf-cfg,$^) $(HOSTLDLIBS_mconf)\n\n$(obj)/nconf: nconf-cfg $(addprefix $(obj)/,$(nconf-objs))\n\t$(CC) -o $@ $(filter-out nconf-cfg,$^) $(HOSTLDLIBS_nconf)\n\n$(obj)/qconf: qconf-cfg $(addprefix $(obj)/,$(qconf-cxxobjs) $(qconf-objs))\n\t$(CXX) -o $@ $(filter-out qconf-cfg,$^) $(HOSTLDLIBS_qconf)\n"
  },
  {
    "path": "scripts/config/README",
    "content": "These files were taken from the Linux 5.14 Kernel Configuration System and\nmodified for the OpenWrt Buildroot:\n - Removed nconf, gconf, tests and kernel configuration targets.\n - Adjusted the Makefile to compile outside the kernel.\n - Always use default file when running make all{no,mod,yes}config.\n - Added a 'reset' command to reset config when the target changes.\n - Allow config reading from & writing to a different file.\n - Allow 'source' command to use globs to include multiple files.\n - Don't warn when selecting a symbol with unmet direct dependencies.\n - Don't write auto.conf and other files under include/ directory.\n - Reverted a commit to allow use of '/' & '.' in unquoted config symbols.\n   There are too many of those in OpenWrt right now.\n - Reverted a commit that was issuing a warning when there were more than\n   one help text.  This is used in a few packages to use different texts\n   for the menuconfig help, and the ipkg package description.\n - Reverted an upstream change that avoids writing symbols that are not\n   visible to .config, which breaks OpenWrt busybox's '.config' generation\n   logic.\n - Treat recursive dependency as a warning only; add a --fatalrecursive\n   option to conf to treat recursive deps as a fatal error.\n - Use pre-built *.lex.c *.tab.[ch] files by default, to avoid depending on\n   flex & bison.  Rebuild/remove these files only if running make with\n   BUILD_SHIPPED_FILES defined\n\nFor a full list of changes, see the repository at:\nhttps://github.com/cotequeiroz/linux/commits/openwrt-5.14/scripts/kconfig\n"
  },
  {
    "path": "scripts/config/conf.c",
    "content": "// SPDX-License-Identifier: GPL-2.0-only\n/*\n * Copyright (C) 2002 Roman Zippel <zippel@linux-m68k.org>\n */\n\n#include <ctype.h>\n#include <limits.h>\n#include <stdio.h>\n#include <stdlib.h>\n#include <string.h>\n#include <time.h>\n#include <unistd.h>\n#include <getopt.h>\n#include <sys/time.h>\n#include <errno.h>\n\n#include \"lkc.h\"\n\nstatic void conf(struct menu *menu);\nstatic void check_conf(struct menu *menu);\n\nenum input_mode {\n\toldaskconfig,\n\tsyncconfig,\n\toldconfig,\n\tallnoconfig,\n\tallyesconfig,\n\tallmodconfig,\n\talldefconfig,\n\trandconfig,\n\tdefconfig,\n\tsavedefconfig,\n\tlistnewconfig,\n\thelpnewconfig,\n\tolddefconfig,\n\tyes2modconfig,\n\tmod2yesconfig,\n\tfatalrecursive,\n};\nstatic enum input_mode input_mode = oldaskconfig;\nstatic int input_mode_opt;\nstatic int indent = 1;\nstatic int tty_stdio;\nstatic int sync_kconfig;\nstatic int conf_cnt;\nstatic char line[PATH_MAX];\nstatic struct menu *rootEntry;\n\nstatic void print_help(struct menu *menu)\n{\n\tstruct gstr help = str_new();\n\n\tmenu_get_ext_help(menu, &help);\n\n\tprintf(\"\\n%s\\n\", str_get(&help));\n\tstr_free(&help);\n}\n\nstatic void strip(char *str)\n{\n\tchar *p = str;\n\tint l;\n\n\twhile ((isspace(*p)))\n\t\tp++;\n\tl = strlen(p);\n\tif (p != str)\n\t\tmemmove(str, p, l + 1);\n\tif (!l)\n\t\treturn;\n\tp = str + l - 1;\n\twhile ((isspace(*p)))\n\t\t*p-- = 0;\n}\n\n/* Helper function to facilitate fgets() by Jean Sacren. */\nstatic void xfgets(char *str, int size, FILE *in)\n{\n\tif (!fgets(str, size, in))\n\t\tfprintf(stderr, \"\\nError in reading or end of file.\\n\");\n\n\tif (!tty_stdio)\n\t\tprintf(\"%s\", str);\n}\n\nstatic void set_randconfig_seed(void)\n{\n\tunsigned int seed;\n\tchar *env;\n\tbool seed_set = false;\n\n\tenv = getenv(\"KCONFIG_SEED\");\n\tif (env && *env) {\n\t\tchar *endp;\n\n\t\tseed = strtol(env, &endp, 0);\n\t\tif (*endp == '\\0')\n\t\t\tseed_set = true;\n\t}\n\n\tif (!seed_set) {\n\t\tstruct timeval now;\n\n\t\t/*\n\t\t * Use microseconds derived seed, compensate for systems where it may\n\t\t * be zero.\n\t\t */\n\t\tgettimeofday(&now, NULL);\n\t\tseed = (now.tv_sec + 1) * (now.tv_usec + 1);\n\t}\n\n\tprintf(\"KCONFIG_SEED=0x%X\\n\", seed);\n\tsrand(seed);\n}\n\nstatic bool randomize_choice_values(struct symbol *csym)\n{\n\tstruct property *prop;\n\tstruct symbol *sym;\n\tstruct expr *e;\n\tint cnt, def;\n\n\t/*\n\t * If choice is mod then we may have more items selected\n\t * and if no then no-one.\n\t * In both cases stop.\n\t */\n\tif (csym->curr.tri != yes)\n\t\treturn false;\n\n\tprop = sym_get_choice_prop(csym);\n\n\t/* count entries in choice block */\n\tcnt = 0;\n\texpr_list_for_each_sym(prop->expr, e, sym)\n\t\tcnt++;\n\n\t/*\n\t * find a random value and set it to yes,\n\t * set the rest to no so we have only one set\n\t */\n\tdef = rand() % cnt;\n\n\tcnt = 0;\n\texpr_list_for_each_sym(prop->expr, e, sym) {\n\t\tif (def == cnt++) {\n\t\t\tsym->def[S_DEF_USER].tri = yes;\n\t\t\tcsym->def[S_DEF_USER].val = sym;\n\t\t} else {\n\t\t\tsym->def[S_DEF_USER].tri = no;\n\t\t}\n\t\tsym->flags |= SYMBOL_DEF_USER;\n\t\t/* clear VALID to get value calculated */\n\t\tsym->flags &= ~SYMBOL_VALID;\n\t}\n\tcsym->flags |= SYMBOL_DEF_USER;\n\t/* clear VALID to get value calculated */\n\tcsym->flags &= ~SYMBOL_VALID;\n\n\treturn true;\n}\n\nenum conf_def_mode {\n\tdef_default,\n\tdef_yes,\n\tdef_mod,\n\tdef_y2m,\n\tdef_m2y,\n\tdef_no,\n\tdef_random\n};\n\nstatic bool conf_set_all_new_symbols(enum conf_def_mode mode)\n{\n\tstruct symbol *sym, *csym;\n\tint i, cnt;\n\t/*\n\t * can't go as the default in switch-case below, otherwise gcc whines\n\t * about -Wmaybe-uninitialized\n\t */\n\tint pby = 50; /* probability of bool     = y */\n\tint pty = 33; /* probability of tristate = y */\n\tint ptm = 33; /* probability of tristate = m */\n\tbool has_changed = false;\n\n\tif (mode == def_random) {\n\t\tint n, p[3];\n\t\tchar *env = getenv(\"KCONFIG_PROBABILITY\");\n\n\t\tn = 0;\n\t\twhile (env && *env) {\n\t\t\tchar *endp;\n\t\t\tint tmp = strtol(env, &endp, 10);\n\n\t\t\tif (tmp >= 0 && tmp <= 100) {\n\t\t\t\tp[n++] = tmp;\n\t\t\t} else {\n\t\t\t\terrno = ERANGE;\n\t\t\t\tperror(\"KCONFIG_PROBABILITY\");\n\t\t\t\texit(1);\n\t\t\t}\n\t\t\tenv = (*endp == ':') ? endp + 1 : endp;\n\t\t\tif (n >= 3)\n\t\t\t\tbreak;\n\t\t}\n\t\tswitch (n) {\n\t\tcase 1:\n\t\t\tpby = p[0];\n\t\t\tptm = pby / 2;\n\t\t\tpty = pby - ptm;\n\t\t\tbreak;\n\t\tcase 2:\n\t\t\tpty = p[0];\n\t\t\tptm = p[1];\n\t\t\tpby = pty + ptm;\n\t\t\tbreak;\n\t\tcase 3:\n\t\t\tpby = p[0];\n\t\t\tpty = p[1];\n\t\t\tptm = p[2];\n\t\t\tbreak;\n\t\t}\n\n\t\tif (pty + ptm > 100) {\n\t\t\terrno = ERANGE;\n\t\t\tperror(\"KCONFIG_PROBABILITY\");\n\t\t\texit(1);\n\t\t}\n\t}\n\n\tsym_clear_all_valid();\n\n\tfor_all_symbols(i, sym) {\n\t\tif (sym_has_value(sym) || sym->flags & SYMBOL_VALID)\n\t\t\tcontinue;\n\t\tswitch (sym_get_type(sym)) {\n\t\tcase S_BOOLEAN:\n\t\tcase S_TRISTATE:\n\t\t\thas_changed = true;\n\t\t\tswitch (mode) {\n\t\t\tcase def_yes:\n\t\t\t\tsym->def[S_DEF_USER].tri = yes;\n\t\t\t\tbreak;\n\t\t\tcase def_mod:\n\t\t\t\tsym->def[S_DEF_USER].tri = mod;\n\t\t\t\tbreak;\n\t\t\tcase def_no:\n\t\t\t\tsym->def[S_DEF_USER].tri = no;\n\t\t\t\tbreak;\n\t\t\tcase def_random:\n\t\t\t\tsym->def[S_DEF_USER].tri = no;\n\t\t\t\tcnt = rand() % 100;\n\t\t\t\tif (sym->type == S_TRISTATE) {\n\t\t\t\t\tif (cnt < pty)\n\t\t\t\t\t\tsym->def[S_DEF_USER].tri = yes;\n\t\t\t\t\telse if (cnt < pty + ptm)\n\t\t\t\t\t\tsym->def[S_DEF_USER].tri = mod;\n\t\t\t\t} else if (cnt < pby)\n\t\t\t\t\tsym->def[S_DEF_USER].tri = yes;\n\t\t\t\tbreak;\n\t\t\tdefault:\n\t\t\t\tcontinue;\n\t\t\t}\n\t\t\tif (!(sym_is_choice(sym) && mode == def_random))\n\t\t\t\tsym->flags |= SYMBOL_DEF_USER;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tbreak;\n\t\t}\n\n\t}\n\n\t/*\n\t * We have different type of choice blocks.\n\t * If curr.tri equals to mod then we can select several\n\t * choice symbols in one block.\n\t * In this case we do nothing.\n\t * If curr.tri equals yes then only one symbol can be\n\t * selected in a choice block and we set it to yes,\n\t * and the rest to no.\n\t */\n\tif (mode != def_random) {\n\t\tfor_all_symbols(i, csym) {\n\t\t\tif ((sym_is_choice(csym) && !sym_has_value(csym)) ||\n\t\t\t    sym_is_choice_value(csym))\n\t\t\t\tcsym->flags |= SYMBOL_NEED_SET_CHOICE_VALUES;\n\t\t}\n\t}\n\n\tfor_all_symbols(i, csym) {\n\t\tif (sym_has_value(csym) || !sym_is_choice(csym))\n\t\t\tcontinue;\n\n\t\tsym_calc_value(csym);\n\t\tif (mode == def_random)\n\t\t\thas_changed |= randomize_choice_values(csym);\n\t\telse {\n\t\t\tset_all_choice_values(csym);\n\t\t\thas_changed = true;\n\t\t}\n\t}\n\n\treturn has_changed;\n}\n\nstatic void conf_rewrite_mod_or_yes(enum conf_def_mode mode)\n{\n\tstruct symbol *sym;\n\tint i;\n\ttristate old_val = (mode == def_y2m) ? yes : mod;\n\ttristate new_val = (mode == def_y2m) ? mod : yes;\n\n\tfor_all_symbols(i, sym) {\n\t\tif (sym_get_type(sym) == S_TRISTATE &&\n\t\t    sym->def[S_DEF_USER].tri == old_val)\n\t\t\tsym->def[S_DEF_USER].tri = new_val;\n\t}\n\tsym_clear_all_valid();\n}\n\nstatic int conf_askvalue(struct symbol *sym, const char *def)\n{\n\tif (!sym_has_value(sym))\n\t\tprintf(\"(NEW) \");\n\n\tline[0] = '\\n';\n\tline[1] = 0;\n\n\tif (!sym_is_changeable(sym)) {\n\t\tprintf(\"%s\\n\", def);\n\t\tline[0] = '\\n';\n\t\tline[1] = 0;\n\t\treturn 0;\n\t}\n\n\tswitch (input_mode) {\n\tcase oldconfig:\n\tcase syncconfig:\n\t\tif (sym_has_value(sym)) {\n\t\t\tprintf(\"%s\\n\", def);\n\t\t\treturn 0;\n\t\t}\n\t\t/* fall through */\n\tdefault:\n\t\tfflush(stdout);\n\t\txfgets(line, sizeof(line), stdin);\n\t\tbreak;\n\t}\n\n\treturn 1;\n}\n\nstatic int conf_string(struct menu *menu)\n{\n\tstruct symbol *sym = menu->sym;\n\tconst char *def;\n\n\twhile (1) {\n\t\tprintf(\"%*s%s \", indent - 1, \"\", menu->prompt->text);\n\t\tprintf(\"(%s) \", sym->name);\n\t\tdef = sym_get_string_value(sym);\n\t\tif (def)\n\t\t\tprintf(\"[%s] \", def);\n\t\tif (!conf_askvalue(sym, def))\n\t\t\treturn 0;\n\t\tswitch (line[0]) {\n\t\tcase '\\n':\n\t\t\tbreak;\n\t\tcase '?':\n\t\t\t/* print help */\n\t\t\tif (line[1] == '\\n') {\n\t\t\t\tprint_help(menu);\n\t\t\t\tdef = NULL;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\t/* fall through */\n\t\tdefault:\n\t\t\tline[strlen(line)-1] = 0;\n\t\t\tdef = line;\n\t\t}\n\t\tif (def && sym_set_string_value(sym, def))\n\t\t\treturn 0;\n\t}\n}\n\nstatic int conf_sym(struct menu *menu)\n{\n\tstruct symbol *sym = menu->sym;\n\ttristate oldval, newval;\n\n\twhile (1) {\n\t\tprintf(\"%*s%s \", indent - 1, \"\", menu->prompt->text);\n\t\tif (sym->name)\n\t\t\tprintf(\"(%s) \", sym->name);\n\t\tputchar('[');\n\t\toldval = sym_get_tristate_value(sym);\n\t\tswitch (oldval) {\n\t\tcase no:\n\t\t\tputchar('N');\n\t\t\tbreak;\n\t\tcase mod:\n\t\t\tputchar('M');\n\t\t\tbreak;\n\t\tcase yes:\n\t\t\tputchar('Y');\n\t\t\tbreak;\n\t\t}\n\t\tif (oldval != no && sym_tristate_within_range(sym, no))\n\t\t\tprintf(\"/n\");\n\t\tif (oldval != mod && sym_tristate_within_range(sym, mod))\n\t\t\tprintf(\"/m\");\n\t\tif (oldval != yes && sym_tristate_within_range(sym, yes))\n\t\t\tprintf(\"/y\");\n\t\tprintf(\"/?] \");\n\t\tif (!conf_askvalue(sym, sym_get_string_value(sym)))\n\t\t\treturn 0;\n\t\tstrip(line);\n\n\t\tswitch (line[0]) {\n\t\tcase 'n':\n\t\tcase 'N':\n\t\t\tnewval = no;\n\t\t\tif (!line[1] || !strcmp(&line[1], \"o\"))\n\t\t\t\tbreak;\n\t\t\tcontinue;\n\t\tcase 'm':\n\t\tcase 'M':\n\t\t\tnewval = mod;\n\t\t\tif (!line[1])\n\t\t\t\tbreak;\n\t\t\tcontinue;\n\t\tcase 'y':\n\t\tcase 'Y':\n\t\t\tnewval = yes;\n\t\t\tif (!line[1] || !strcmp(&line[1], \"es\"))\n\t\t\t\tbreak;\n\t\t\tcontinue;\n\t\tcase 0:\n\t\t\tnewval = oldval;\n\t\t\tbreak;\n\t\tcase '?':\n\t\t\tgoto help;\n\t\tdefault:\n\t\t\tcontinue;\n\t\t}\n\t\tif (sym_set_tristate_value(sym, newval))\n\t\t\treturn 0;\nhelp:\n\t\tprint_help(menu);\n\t}\n}\n\nstatic int conf_choice(struct menu *menu)\n{\n\tstruct symbol *sym, *def_sym;\n\tstruct menu *child;\n\tbool is_new;\n\n\tsym = menu->sym;\n\tis_new = !sym_has_value(sym);\n\tif (sym_is_changeable(sym)) {\n\t\tconf_sym(menu);\n\t\tsym_calc_value(sym);\n\t\tswitch (sym_get_tristate_value(sym)) {\n\t\tcase no:\n\t\t\treturn 1;\n\t\tcase mod:\n\t\t\treturn 0;\n\t\tcase yes:\n\t\t\tbreak;\n\t\t}\n\t} else {\n\t\tswitch (sym_get_tristate_value(sym)) {\n\t\tcase no:\n\t\t\treturn 1;\n\t\tcase mod:\n\t\t\tprintf(\"%*s%s\\n\", indent - 1, \"\", menu_get_prompt(menu));\n\t\t\treturn 0;\n\t\tcase yes:\n\t\t\tbreak;\n\t\t}\n\t}\n\n\twhile (1) {\n\t\tint cnt, def;\n\n\t\tprintf(\"%*s%s\\n\", indent - 1, \"\", menu_get_prompt(menu));\n\t\tdef_sym = sym_get_choice_value(sym);\n\t\tcnt = def = 0;\n\t\tline[0] = 0;\n\t\tfor (child = menu->list; child; child = child->next) {\n\t\t\tif (!menu_is_visible(child))\n\t\t\t\tcontinue;\n\t\t\tif (!child->sym) {\n\t\t\t\tprintf(\"%*c %s\\n\", indent, '*', menu_get_prompt(child));\n\t\t\t\tcontinue;\n\t\t\t}\n\t\t\tcnt++;\n\t\t\tif (child->sym == def_sym) {\n\t\t\t\tdef = cnt;\n\t\t\t\tprintf(\"%*c\", indent, '>');\n\t\t\t} else\n\t\t\t\tprintf(\"%*c\", indent, ' ');\n\t\t\tprintf(\" %d. %s\", cnt, menu_get_prompt(child));\n\t\t\tif (child->sym->name)\n\t\t\t\tprintf(\" (%s)\", child->sym->name);\n\t\t\tif (!sym_has_value(child->sym))\n\t\t\t\tprintf(\" (NEW)\");\n\t\t\tprintf(\"\\n\");\n\t\t}\n\t\tprintf(\"%*schoice\", indent - 1, \"\");\n\t\tif (cnt == 1) {\n\t\t\tprintf(\"[1]: 1\\n\");\n\t\t\tgoto conf_childs;\n\t\t}\n\t\tprintf(\"[1-%d?]: \", cnt);\n\t\tswitch (input_mode) {\n\t\tcase oldconfig:\n\t\tcase syncconfig:\n\t\t\tif (!is_new) {\n\t\t\t\tcnt = def;\n\t\t\t\tprintf(\"%d\\n\", cnt);\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\t/* fall through */\n\t\tcase oldaskconfig:\n\t\t\tfflush(stdout);\n\t\t\txfgets(line, sizeof(line), stdin);\n\t\t\tstrip(line);\n\t\t\tif (line[0] == '?') {\n\t\t\t\tprint_help(menu);\n\t\t\t\tcontinue;\n\t\t\t}\n\t\t\tif (!line[0])\n\t\t\t\tcnt = def;\n\t\t\telse if (isdigit(line[0]))\n\t\t\t\tcnt = atoi(line);\n\t\t\telse\n\t\t\t\tcontinue;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tbreak;\n\t\t}\n\n\tconf_childs:\n\t\tfor (child = menu->list; child; child = child->next) {\n\t\t\tif (!child->sym || !menu_is_visible(child))\n\t\t\t\tcontinue;\n\t\t\tif (!--cnt)\n\t\t\t\tbreak;\n\t\t}\n\t\tif (!child)\n\t\t\tcontinue;\n\t\tif (line[0] && line[strlen(line) - 1] == '?') {\n\t\t\tprint_help(child);\n\t\t\tcontinue;\n\t\t}\n\t\tsym_set_choice_value(sym, child->sym);\n\t\tfor (child = child->list; child; child = child->next) {\n\t\t\tindent += 2;\n\t\t\tconf(child);\n\t\t\tindent -= 2;\n\t\t}\n\t\treturn 1;\n\t}\n}\n\nstatic void conf(struct menu *menu)\n{\n\tstruct symbol *sym;\n\tstruct property *prop;\n\tstruct menu *child;\n\n\tif (!menu_is_visible(menu))\n\t\treturn;\n\n\tsym = menu->sym;\n\tprop = menu->prompt;\n\tif (prop) {\n\t\tconst char *prompt;\n\n\t\tswitch (prop->type) {\n\t\tcase P_MENU:\n\t\t\t/*\n\t\t\t * Except in oldaskconfig mode, we show only menus that\n\t\t\t * contain new symbols.\n\t\t\t */\n\t\t\tif (input_mode != oldaskconfig && rootEntry != menu) {\n\t\t\t\tcheck_conf(menu);\n\t\t\t\treturn;\n\t\t\t}\n\t\t\t/* fall through */\n\t\tcase P_COMMENT:\n\t\t\tprompt = menu_get_prompt(menu);\n\t\t\tif (prompt)\n\t\t\t\tprintf(\"%*c\\n%*c %s\\n%*c\\n\",\n\t\t\t\t\tindent, '*',\n\t\t\t\t\tindent, '*', prompt,\n\t\t\t\t\tindent, '*');\n\t\tdefault:\n\t\t\t;\n\t\t}\n\t}\n\n\tif (!sym)\n\t\tgoto conf_childs;\n\n\tif (sym_is_choice(sym)) {\n\t\tconf_choice(menu);\n\t\tif (sym->curr.tri != mod)\n\t\t\treturn;\n\t\tgoto conf_childs;\n\t}\n\n\tswitch (sym->type) {\n\tcase S_INT:\n\tcase S_HEX:\n\tcase S_STRING:\n\t\tconf_string(menu);\n\t\tbreak;\n\tdefault:\n\t\tconf_sym(menu);\n\t\tbreak;\n\t}\n\nconf_childs:\n\tif (sym)\n\t\tindent += 2;\n\tfor (child = menu->list; child; child = child->next)\n\t\tconf(child);\n\tif (sym)\n\t\tindent -= 2;\n}\n\nstatic void check_conf(struct menu *menu)\n{\n\tstruct symbol *sym;\n\tstruct menu *child;\n\n\tif (!menu_is_visible(menu))\n\t\treturn;\n\n\tsym = menu->sym;\n\tif (sym && !sym_has_value(sym) &&\n\t    (sym_is_changeable(sym) ||\n\t     (sym_is_choice(sym) && sym_get_tristate_value(sym) == yes))) {\n\n\t\tswitch (input_mode) {\n\t\tcase listnewconfig:\n\t\t\tif (sym->name) {\n\t\t\t\tconst char *str;\n\n\t\t\t\tif (sym->type == S_STRING) {\n\t\t\t\t\tstr = sym_get_string_value(sym);\n\t\t\t\t\tstr = sym_escape_string_value(str);\n\t\t\t\t\tprintf(\"%s%s=%s\\n\", CONFIG_, sym->name, str);\n\t\t\t\t\tfree((void *)str);\n\t\t\t\t} else {\n\t\t\t\t\tstr = sym_get_string_value(sym);\n\t\t\t\t\tprintf(\"%s%s=%s\\n\", CONFIG_, sym->name, str);\n\t\t\t\t}\n\t\t\t}\n\t\t\tbreak;\n\t\tcase helpnewconfig:\n\t\t\tprintf(\"-----\\n\");\n\t\t\tprint_help(menu);\n\t\t\tprintf(\"-----\\n\");\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tif (!conf_cnt++)\n\t\t\t\tprintf(\"*\\n* Restart config...\\n*\\n\");\n\t\t\trootEntry = menu_get_parent_menu(menu);\n\t\t\tconf(rootEntry);\n\t\t\tbreak;\n\t\t}\n\t}\n\n\tfor (child = menu->list; child; child = child->next)\n\t\tcheck_conf(child);\n}\n\nstatic const struct option long_opts[] = {\n\t{\"help\",          no_argument,       NULL,            'h'},\n\t{\"silent\",        no_argument,       NULL,            's'},\n\t{\"oldaskconfig\",  no_argument,       &input_mode_opt, oldaskconfig},\n\t{\"oldconfig\",     no_argument,       &input_mode_opt, oldconfig},\n\t{\"syncconfig\",    no_argument,       &input_mode_opt, syncconfig},\n\t{\"defconfig\",     required_argument, &input_mode_opt, defconfig},\n\t{\"savedefconfig\", required_argument, &input_mode_opt, savedefconfig},\n\t{\"allnoconfig\",   no_argument,       &input_mode_opt, allnoconfig},\n\t{\"allyesconfig\",  no_argument,       &input_mode_opt, allyesconfig},\n\t{\"allmodconfig\",  no_argument,       &input_mode_opt, allmodconfig},\n\t{\"alldefconfig\",  no_argument,       &input_mode_opt, alldefconfig},\n\t{\"randconfig\",    no_argument,       &input_mode_opt, randconfig},\n\t{\"listnewconfig\", no_argument,       &input_mode_opt, listnewconfig},\n\t{\"helpnewconfig\", no_argument,       &input_mode_opt, helpnewconfig},\n\t{\"olddefconfig\",  no_argument,       &input_mode_opt, olddefconfig},\n\t{\"yes2modconfig\", no_argument,       &input_mode_opt, yes2modconfig},\n\t{\"mod2yesconfig\", no_argument,       &input_mode_opt, mod2yesconfig},\n\t{\"fatalrecursive\",no_argument,       NULL, fatalrecursive},\n\t{NULL, 0, NULL, 0}\n};\n\nstatic void conf_usage(const char *progname)\n{\n\tprintf(\"Usage: %s [options] <kconfig-file>\\n\", progname);\n\tprintf(\"\\n\");\n\tprintf(\"Generic options:\\n\");\n\tprintf(\"  -h, --help              Print this message and exit.\\n\");\n\tprintf(\"  -s, --silent            Do not print log.\\n\");\n\tprintf(\"      --fatalrecursive    Treat recursive depenendencies as a fatal error\\n\");\n\tprintf(\"\\n\");\n\tprintf(\"Mode options:\\n\");\n\tprintf(\"  --listnewconfig         List new options\\n\");\n\tprintf(\"  --helpnewconfig         List new options and help text\\n\");\n\tprintf(\"  --oldaskconfig          Start a new configuration using a line-oriented program\\n\");\n\tprintf(\"  --oldconfig             Update a configuration using a provided .config as base\\n\");\n\tprintf(\"  --syncconfig            Similar to oldconfig but generates configuration in\\n\"\n\t       \"                          include/{generated/,config/}\\n\");\n\tprintf(\"  --olddefconfig          Same as oldconfig but sets new symbols to their default value\\n\");\n\tprintf(\"  --defconfig <file>      New config with default defined in <file>\\n\");\n\tprintf(\"  --savedefconfig <file>  Save the minimal current configuration to <file>\\n\");\n\tprintf(\"  --allnoconfig           New config where all options are answered with no\\n\");\n\tprintf(\"  --allyesconfig          New config where all options are answered with yes\\n\");\n\tprintf(\"  --allmodconfig          New config where all options are answered with mod\\n\");\n\tprintf(\"  --alldefconfig          New config with all symbols set to default\\n\");\n\tprintf(\"  --randconfig            New config with random answer to all options\\n\");\n\tprintf(\"  --yes2modconfig         Change answers from yes to mod if possible\\n\");\n\tprintf(\"  --mod2yesconfig         Change answers from mod to yes if possible\\n\");\n\tprintf(\"  (If none of the above is given, --oldaskconfig is the default)\\n\");\n}\n\nint main(int ac, char **av)\n{\n\tconst char *progname = av[0];\n\tint opt;\n\tconst char *name, *defconfig_file = NULL /* gcc uninit */;\n\tconst char *input_file = NULL, *output_file = NULL;\n\tint no_conf_write = 0;\n\n\ttty_stdio = isatty(0) && isatty(1);\n\n\twhile ((opt = getopt_long(ac, av, \"hr:sw:\", long_opts, NULL)) != -1) {\n\t\tswitch (opt) {\n\t\tcase 'h':\n\t\t\tconf_usage(progname);\n\t\t\texit(1);\n\t\t\tbreak;\n\t\tcase 's':\n\t\t\tconf_set_message_callback(NULL);\n\t\t\tbreak;\n\t\tcase fatalrecursive:\n\t\t\trecursive_is_error = 1;\n\t\t\tcontinue;\n\t\tcase 'r':\n\t\t\tinput_file = optarg;\n\t\t\tbreak;\n\t\tcase 'w':\n\t\t\toutput_file = optarg;\n\t\t\tbreak;\n\t\tcase 0:\n\t\t\tinput_mode = input_mode_opt;\n\t\t\tswitch (input_mode) {\n\t\t\tcase syncconfig:\n\t\t\t\t/*\n\t\t\t\t * syncconfig is invoked during the build stage.\n\t\t\t\t * Suppress distracting\n\t\t\t\t *   \"configuration written to ...\"\n\t\t\t\t */\n\t\t\t\tconf_set_message_callback(NULL);\n\t\t\t\tsync_kconfig = 1;\n\t\t\t\tbreak;\n\t\t\tcase defconfig:\n\t\t\tcase savedefconfig:\n\t\t\t\tdefconfig_file = optarg;\n\t\t\t\tbreak;\n\t\t\tcase randconfig:\n\t\t\t\tset_randconfig_seed();\n\t\t\t\tbreak;\n\t\t\tdefault:\n\t\t\t\tbreak;\n\t\t\t}\n\t\tdefault:\n\t\t\tbreak;\n\t\t}\n\t}\n\tif (ac == optind) {\n\t\tfprintf(stderr, \"%s: Kconfig file missing\\n\", av[0]);\n\t\tconf_usage(progname);\n\t\texit(1);\n\t}\n\tconf_parse(av[optind]);\n\t//zconfdump(stdout);\n\n\tswitch (input_mode) {\n\tcase defconfig:\n\t\tif (conf_read(defconfig_file)) {\n\t\t\tfprintf(stderr,\n\t\t\t\t\"***\\n\"\n\t\t\t\t  \"*** Can't find default configuration \\\"%s\\\"!\\n\"\n\t\t\t\t  \"***\\n\",\n\t\t\t\tdefconfig_file);\n\t\t\texit(1);\n\t\t}\n\t\tbreak;\n\tcase savedefconfig:\n\tcase syncconfig:\n\tcase oldaskconfig:\n\tcase oldconfig:\n\tcase listnewconfig:\n\tcase helpnewconfig:\n\tcase olddefconfig:\n\tcase yes2modconfig:\n\tcase mod2yesconfig:\n\tcase allnoconfig:\n\tcase allyesconfig:\n\tcase allmodconfig:\n\tcase alldefconfig:\n\tcase randconfig:\n\t\tconf_read(input_file);\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\n\tif (sync_kconfig) {\n\t\tname = getenv(\"KCONFIG_NOSILENTUPDATE\");\n\t\tif (name && *name) {\n\t\t\tif (conf_get_changed()) {\n\t\t\t\tfprintf(stderr,\n\t\t\t\t\t\"\\n*** The configuration requires explicit update.\\n\\n\");\n\t\t\t\treturn 1;\n\t\t\t}\n\t\t\tno_conf_write = 1;\n\t\t}\n\t}\n\n\tswitch (input_mode) {\n\tcase allnoconfig:\n\t\tconf_set_all_new_symbols(def_no);\n\t\tbreak;\n\tcase allyesconfig:\n\t\tconf_set_all_new_symbols(def_yes);\n\t\tbreak;\n\tcase allmodconfig:\n\t\tconf_set_all_new_symbols(def_mod);\n\t\tbreak;\n\tcase alldefconfig:\n\t\tconf_set_all_new_symbols(def_default);\n\t\tbreak;\n\tcase randconfig:\n\t\t/* Really nothing to do in this loop */\n\t\twhile (conf_set_all_new_symbols(def_random)) ;\n\t\tbreak;\n\tcase defconfig:\n\t\tconf_set_all_new_symbols(def_default);\n\t\tbreak;\n\tcase savedefconfig:\n\t\tbreak;\n\tcase yes2modconfig:\n\t\tconf_rewrite_mod_or_yes(def_y2m);\n\t\tbreak;\n\tcase mod2yesconfig:\n\t\tconf_rewrite_mod_or_yes(def_m2y);\n\t\tbreak;\n\tcase oldaskconfig:\n\t\trootEntry = &rootmenu;\n\t\tconf(&rootmenu);\n\t\tinput_mode = oldconfig;\n\t\t/* fall through */\n\tcase oldconfig:\n\tcase listnewconfig:\n\tcase helpnewconfig:\n\tcase syncconfig:\n\t\t/* Update until a loop caused no more changes */\n\t\tdo {\n\t\t\tconf_cnt = 0;\n\t\t\tcheck_conf(&rootmenu);\n\t\t} while (conf_cnt);\n\t\tbreak;\n\tcase olddefconfig:\n\tdefault:\n\t\tbreak;\n\t}\n\n\tif (input_mode == savedefconfig) {\n\t\tif (conf_write_defconfig(defconfig_file)) {\n\t\t\tfprintf(stderr, \"n*** Error while saving defconfig to: %s\\n\\n\",\n\t\t\t\tdefconfig_file);\n\t\t\treturn 1;\n\t\t}\n\t} else if (input_mode != listnewconfig && input_mode != helpnewconfig) {\n\t\tif ((output_file || !no_conf_write) &&\n\t\t    conf_write(output_file)) {\n\t\t\tfprintf(stderr, \"\\n*** Error during writing of the configuration.\\n\\n\");\n\t\t\texit(1);\n\t\t}\n\n\t\t/*\n\t\t * Create auto.conf if it does not exist.\n\t\t * This prevents GNU Make 4.1 or older from emitting\n\t\t * \"include/config/auto.conf: No such file or directory\"\n\t\t * in the top-level Makefile\n\t\t *\n\t\t * syncconfig always creates or updates auto.conf because it is\n\t\t * used during the build.\n\t\t */\n\t\tif (conf_write_autoconf(sync_kconfig) && sync_kconfig) {\n\t\t\tfprintf(stderr,\n\t\t\t\t\"\\n*** Error during sync of the configuration.\\n\\n\");\n\t\t\treturn 1;\n\t\t}\n\t}\n\treturn 0;\n}\n"
  },
  {
    "path": "scripts/config/confdata.c",
    "content": "// SPDX-License-Identifier: GPL-2.0-only\n/*\n * Copyright (C) 2002 Roman Zippel <zippel@linux-m68k.org>\n */\n\n#include <sys/mman.h>\n#include <sys/stat.h>\n#include <sys/types.h>\n#include <ctype.h>\n#include <errno.h>\n#include <fcntl.h>\n#include <limits.h>\n#include <stdarg.h>\n#include <stdio.h>\n#include <stdlib.h>\n#include <string.h>\n#include <time.h>\n#include <unistd.h>\n\n#include \"lkc.h\"\n\n/* return true if 'path' exists, false otherwise */\nstatic bool is_present(const char *path)\n{\n\tstruct stat st;\n\n\treturn !stat(path, &st);\n}\n\n/* return true if 'path' exists and it is a directory, false otherwise */\nstatic bool is_dir(const char *path)\n{\n\tstruct stat st;\n\n\tif (stat(path, &st))\n\t\treturn false;\n\n\treturn S_ISDIR(st.st_mode);\n}\n\n/* return true if the given two files are the same, false otherwise */\nstatic bool is_same(const char *file1, const char *file2)\n{\n\tint fd1, fd2;\n\tstruct stat st1, st2;\n\tvoid *map1, *map2;\n\tbool ret = false;\n\n\tfd1 = open(file1, O_RDONLY);\n\tif (fd1 < 0)\n\t\treturn ret;\n\n\tfd2 = open(file2, O_RDONLY);\n\tif (fd2 < 0)\n\t\tgoto close1;\n\n\tret = fstat(fd1, &st1);\n\tif (ret)\n\t\tgoto close2;\n\tret = fstat(fd2, &st2);\n\tif (ret)\n\t\tgoto close2;\n\n\tif (st1.st_size != st2.st_size)\n\t\tgoto close2;\n\n\tmap1 = mmap(NULL, st1.st_size, PROT_READ, MAP_PRIVATE, fd1, 0);\n\tif (map1 == MAP_FAILED)\n\t\tgoto close2;\n\n\tmap2 = mmap(NULL, st2.st_size, PROT_READ, MAP_PRIVATE, fd2, 0);\n\tif (map2 == MAP_FAILED)\n\t\tgoto close2;\n\n\tif (bcmp(map1, map2, st1.st_size))\n\t\tgoto close2;\n\n\tret = true;\nclose2:\n\tclose(fd2);\nclose1:\n\tclose(fd1);\n\n\treturn ret;\n}\n\n/*\n * Create the parent directory of the given path.\n *\n * For example, if 'include/config/auto.conf' is given, create 'include/config'.\n */\nstatic int make_parent_dir(const char *path)\n{\n\tchar tmp[PATH_MAX + 1];\n\tchar *p;\n\n\tstrncpy(tmp, path, sizeof(tmp));\n\ttmp[sizeof(tmp) - 1] = 0;\n\n\t/* Remove the base name. Just return if nothing is left */\n\tp = strrchr(tmp, '/');\n\tif (!p)\n\t\treturn 0;\n\t*(p + 1) = 0;\n\n\t/* Just in case it is an absolute path */\n\tp = tmp;\n\twhile (*p == '/')\n\t\tp++;\n\n\twhile ((p = strchr(p, '/'))) {\n\t\t*p = 0;\n\n\t\t/* skip if the directory exists */\n\t\tif (!is_dir(tmp) && mkdir(tmp, 0755))\n\t\t\treturn -1;\n\n\t\t*p = '/';\n\t\twhile (*p == '/')\n\t\t\tp++;\n\t}\n\n\treturn 0;\n}\n\nstatic char depfile_path[PATH_MAX];\nstatic size_t depfile_prefix_len;\n\n/* touch depfile for symbol 'name' */\nstatic int conf_touch_dep(const char *name)\n{\n\tint fd, ret;\n\tchar *d;\n\n\t/* check overflow: prefix + name + '\\0' must fit in buffer. */\n\tif (depfile_prefix_len + strlen(name) + 1 > sizeof(depfile_path))\n\t\treturn -1;\n\n\td = depfile_path + depfile_prefix_len;\n\tstrcpy(d, name);\n\n\t/* Assume directory path already exists. */\n\tfd = open(depfile_path, O_WRONLY | O_CREAT | O_TRUNC, 0644);\n\tif (fd == -1) {\n\t\tif (errno != ENOENT)\n\t\t\treturn -1;\n\n\t\tret = make_parent_dir(depfile_path);\n\t\tif (ret)\n\t\t\treturn ret;\n\n\t\t/* Try it again. */\n\t\tfd = open(depfile_path, O_WRONLY | O_CREAT | O_TRUNC, 0644);\n\t\tif (fd == -1)\n\t\t\treturn -1;\n\t}\n\tclose(fd);\n\n\treturn 0;\n}\n\nstruct conf_printer {\n\tvoid (*print_symbol)(FILE *, struct symbol *, const char *, void *);\n\tvoid (*print_comment)(FILE *, const char *, void *);\n};\n\nstatic void conf_warning(const char *fmt, ...)\n\t__attribute__ ((format (printf, 1, 2)));\n\nstatic void conf_message(const char *fmt, ...)\n\t__attribute__ ((format (printf, 1, 2)));\n\nstatic const char *conf_filename;\nstatic int conf_lineno, conf_warnings;\n\nstatic void conf_warning(const char *fmt, ...)\n{\n\tva_list ap;\n\tva_start(ap, fmt);\n\tfprintf(stderr, \"%s:%d:warning: \", conf_filename, conf_lineno);\n\tvfprintf(stderr, fmt, ap);\n\tfprintf(stderr, \"\\n\");\n\tva_end(ap);\n\tconf_warnings++;\n}\n\nstatic void conf_default_message_callback(const char *s)\n{\n\tprintf(\"#\\n# \");\n\tprintf(\"%s\", s);\n\tprintf(\"\\n#\\n\");\n}\n\nstatic void (*conf_message_callback)(const char *s) =\n\tconf_default_message_callback;\nvoid conf_set_message_callback(void (*fn)(const char *s))\n{\n\tconf_message_callback = fn;\n}\n\nstatic void conf_message(const char *fmt, ...)\n{\n\tva_list ap;\n\tchar buf[4096];\n\n\tif (!conf_message_callback)\n\t\treturn;\n\n\tva_start(ap, fmt);\n\n\tvsnprintf(buf, sizeof(buf), fmt, ap);\n\tconf_message_callback(buf);\n\tva_end(ap);\n}\n\nconst char *conf_get_configname(void)\n{\n\tchar *name = getenv(\"KCONFIG_CONFIG\");\n\n\treturn name ? name : \".config\";\n}\n\nstatic const char *conf_get_autoconfig_name(void)\n{\n\tchar *name = getenv(\"KCONFIG_AUTOCONFIG\");\n\n\treturn name ? name : \"include/config/auto.conf\";\n}\n\nstatic int conf_set_sym_val(struct symbol *sym, int def, int def_flags, char *p)\n{\n\tchar *p2;\n\n\tswitch (sym->type) {\n\tcase S_TRISTATE:\n\t\tif (p[0] == 'm') {\n\t\t\tsym->def[def].tri = mod;\n\t\t\tsym->flags |= def_flags;\n\t\t\tbreak;\n\t\t}\n\t\t/* fall through */\n\tcase S_BOOLEAN:\n\t\tif (p[0] == 'y') {\n\t\t\tsym->def[def].tri = yes;\n\t\t\tsym->flags |= def_flags;\n\t\t\tbreak;\n\t\t}\n\t\tif (p[0] == 'n') {\n\t\t\tsym->def[def].tri = no;\n\t\t\tsym->flags |= def_flags;\n\t\t\tbreak;\n\t\t}\n\t\tif (def != S_DEF_AUTO)\n\t\t\tconf_warning(\"symbol value '%s' invalid for %s\",\n\t\t\t\t     p, sym->name);\n\t\treturn 1;\n\tcase S_STRING:\n\t\tif (*p++ != '\"')\n\t\t\tbreak;\n\t\tfor (p2 = p; (p2 = strpbrk(p2, \"\\\"\\\\\")); p2++) {\n\t\t\tif (*p2 == '\"') {\n\t\t\t\t*p2 = 0;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\tmemmove(p2, p2 + 1, strlen(p2));\n\t\t}\n\t\tif (!p2) {\n\t\t\tif (def != S_DEF_AUTO)\n\t\t\t\tconf_warning(\"invalid string found\");\n\t\t\treturn 1;\n\t\t}\n\t\t/* fall through */\n\tcase S_INT:\n\tcase S_HEX:\n\t\tif (sym_string_valid(sym, p)) {\n\t\t\tsym->def[def].val = xstrdup(p);\n\t\t\tsym->flags |= def_flags;\n\t\t} else {\n\t\t\tif (def != S_DEF_AUTO)\n\t\t\t\tconf_warning(\"symbol value '%s' invalid for %s\",\n\t\t\t\t\t     p, sym->name);\n\t\t\treturn 1;\n\t\t}\n\t\tbreak;\n\tdefault:\n\t\t;\n\t}\n\treturn 0;\n}\n\n#define LINE_GROWTH 16\nstatic int add_byte(int c, char **lineptr, size_t slen, size_t *n)\n{\n\tchar *nline;\n\tsize_t new_size = slen + 1;\n\tif (new_size > *n) {\n\t\tnew_size += LINE_GROWTH - 1;\n\t\tnew_size *= 2;\n\t\tnline = xrealloc(*lineptr, new_size);\n\t\tif (!nline)\n\t\t\treturn -1;\n\n\t\t*lineptr = nline;\n\t\t*n = new_size;\n\t}\n\n\t(*lineptr)[slen] = c;\n\n\treturn 0;\n}\n\nstatic ssize_t compat_getline(char **lineptr, size_t *n, FILE *stream)\n{\n\tchar *line = *lineptr;\n\tsize_t slen = 0;\n\n\tfor (;;) {\n\t\tint c = getc(stream);\n\n\t\tswitch (c) {\n\t\tcase '\\n':\n\t\t\tif (add_byte(c, &line, slen, n) < 0)\n\t\t\t\tgoto e_out;\n\t\t\tslen++;\n\t\t\t/* fall through */\n\t\tcase EOF:\n\t\t\tif (add_byte('\\0', &line, slen, n) < 0)\n\t\t\t\tgoto e_out;\n\t\t\t*lineptr = line;\n\t\t\tif (slen == 0)\n\t\t\t\treturn -1;\n\t\t\treturn slen;\n\t\tdefault:\n\t\t\tif (add_byte(c, &line, slen, n) < 0)\n\t\t\t\tgoto e_out;\n\t\t\tslen++;\n\t\t}\n\t}\n\ne_out:\n\tline[slen-1] = '\\0';\n\t*lineptr = line;\n\treturn -1;\n}\n\nvoid conf_reset(int def)\n{\n\tstruct symbol *sym;\n\tint i, def_flags;\n\n\tdef_flags = SYMBOL_DEF << def;\n\tfor_all_symbols(i, sym) {\n\t\tsym->flags |= SYMBOL_CHANGED;\n\t\tsym->flags &= ~(def_flags|SYMBOL_VALID);\n\t\tif (sym_is_choice(sym))\n\t\t\tsym->flags |= def_flags;\n\t\tswitch (sym->type) {\n\t\tcase S_INT:\n\t\tcase S_HEX:\n\t\tcase S_STRING:\n\t\t\tif (sym->def[def].val)\n\t\t\t\tfree(sym->def[def].val);\n\t\t\t/* fall through */\n\t\tdefault:\n\t\t\tsym->def[def].val = NULL;\n\t\t\tsym->def[def].tri = no;\n\t\t}\n\t}\n}\n\nint conf_read_simple(const char *name, int def)\n{\n\tFILE *in = NULL;\n\tchar   *line = NULL;\n\tsize_t  line_asize = 0;\n\tchar *p, *p2;\n\tstruct symbol *sym;\n\tint def_flags;\n\n\tif (name) {\n\t\tin = zconf_fopen(name);\n\t} else {\n\t\tchar *env;\n\n\t\tname = conf_get_configname();\n\t\tin = zconf_fopen(name);\n\t\tif (in)\n\t\t\tgoto load;\n\t\tconf_set_changed(true);\n\n\t\tenv = getenv(\"KCONFIG_DEFCONFIG_LIST\");\n\t\tif (!env)\n\t\t\treturn 1;\n\n\t\twhile (1) {\n\t\t\tbool is_last;\n\n\t\t\twhile (isspace(*env))\n\t\t\t\tenv++;\n\n\t\t\tif (!*env)\n\t\t\t\tbreak;\n\n\t\t\tp = env;\n\t\t\twhile (*p && !isspace(*p))\n\t\t\t\tp++;\n\n\t\t\tis_last = (*p == '\\0');\n\n\t\t\t*p = '\\0';\n\n\t\t\tin = zconf_fopen(env);\n\t\t\tif (in) {\n\t\t\t\tconf_message(\"using defaults found in %s\",\n\t\t\t\t\t     env);\n\t\t\t\tgoto load;\n\t\t\t}\n\n\t\t\tif (is_last)\n\t\t\t\tbreak;\n\n\t\t\tenv = p + 1;\n\t\t}\n\t}\n\tif (!in)\n\t\treturn 1;\n\nload:\n\tconf_filename = name;\n\tconf_lineno = 0;\n\tconf_warnings = 0;\n\n\tdef_flags = SYMBOL_DEF << def;\n\tconf_reset(def);\n\n\twhile (compat_getline(&line, &line_asize, in) != -1) {\n\t\tconf_lineno++;\n\t\tsym = NULL;\n\t\tif (line[0] == '#') {\n\t\t\tif (memcmp(line + 2, CONFIG_, strlen(CONFIG_)))\n\t\t\t\tcontinue;\n\t\t\tp = strchr(line + 2 + strlen(CONFIG_), ' ');\n\t\t\tif (!p)\n\t\t\t\tcontinue;\n\t\t\t*p++ = 0;\n\t\t\tif (strncmp(p, \"is not set\", 10))\n\t\t\t\tcontinue;\n\t\t\tif (def == S_DEF_USER) {\n\t\t\t\tsym = sym_find(line + 2 + strlen(CONFIG_));\n\t\t\t\tif (!sym) {\n\t\t\t\t\tconf_set_changed(true);\n\t\t\t\t\tcontinue;\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\tsym = sym_lookup(line + 2 + strlen(CONFIG_), 0);\n\t\t\t\tif (sym->type == S_UNKNOWN)\n\t\t\t\t\tsym->type = S_BOOLEAN;\n\t\t\t}\n\t\t\tswitch (sym->type) {\n\t\t\tcase S_BOOLEAN:\n\t\t\tcase S_TRISTATE:\n\t\t\t\tsym->def[def].tri = no;\n\t\t\t\tsym->flags |= def_flags;\n\t\t\t\tbreak;\n\t\t\tdefault:\n\t\t\t\t;\n\t\t\t}\n\t\t} else if (memcmp(line, CONFIG_, strlen(CONFIG_)) == 0) {\n\t\t\tp = strchr(line + strlen(CONFIG_), '=');\n\t\t\tif (!p)\n\t\t\t\tcontinue;\n\t\t\t*p++ = 0;\n\t\t\tp2 = strchr(p, '\\n');\n\t\t\tif (p2) {\n\t\t\t\t*p2-- = 0;\n\t\t\t\tif (*p2 == '\\r')\n\t\t\t\t\t*p2 = 0;\n\t\t\t}\n\n\t\t\tsym = sym_find(line + strlen(CONFIG_));\n\t\t\tif (!sym) {\n\t\t\t\tif (def == S_DEF_AUTO)\n\t\t\t\t\t/*\n\t\t\t\t\t * Reading from include/config/auto.conf\n\t\t\t\t\t * If CONFIG_FOO previously existed in\n\t\t\t\t\t * auto.conf but it is missing now,\n\t\t\t\t\t * include/config/FOO must be touched.\n\t\t\t\t\t */\n\t\t\t\t\tconf_touch_dep(line + strlen(CONFIG_));\n\t\t\t\telse\n\t\t\t\t\tconf_set_changed(true);\n\t\t\t\tcontinue;\n\t\t\t}\n\n\t\t\tif (conf_set_sym_val(sym, def, def_flags, p))\n\t\t\t\tcontinue;\n\t\t} else {\n\t\t\tif (line[0] != '\\r' && line[0] != '\\n')\n\t\t\t\tconf_warning(\"unexpected data: %.*s\",\n\t\t\t\t\t     (int)strcspn(line, \"\\r\\n\"), line);\n\n\t\t\tcontinue;\n\t\t}\n\n\t\tif (sym && sym_is_choice_value(sym)) {\n\t\t\tstruct symbol *cs = prop_get_symbol(sym_get_choice_prop(sym));\n\t\t\tswitch (sym->def[def].tri) {\n\t\t\tcase no:\n\t\t\t\tbreak;\n\t\t\tcase mod:\n\t\t\t\tif (cs->def[def].tri == yes) {\n\t\t\t\t\tconf_warning(\"%s creates inconsistent choice state\", sym->name);\n\t\t\t\t\tcs->flags &= ~def_flags;\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase yes:\n\t\t\t\tif (cs->def[def].tri != no)\n\t\t\t\t\tconf_warning(\"override: %s changes choice state\", sym->name);\n\t\t\t\tcs->def[def].val = sym;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\tcs->def[def].tri = EXPR_OR(cs->def[def].tri, sym->def[def].tri);\n\t\t}\n\t}\n\tfree(line);\n\tfclose(in);\n\treturn 0;\n}\n\nint conf_read(const char *name)\n{\n\tstruct symbol *sym;\n\tint conf_unsaved = 0;\n\tint i;\n\n\tconf_set_changed(false);\n\n\tif (conf_read_simple(name, S_DEF_USER)) {\n\t\tsym_calc_value(modules_sym);\n\t\treturn 1;\n\t}\n\n\tsym_calc_value(modules_sym);\n\n\tfor_all_symbols(i, sym) {\n\t\tsym_calc_value(sym);\n\t\tif (sym_is_choice(sym) || (sym->flags & SYMBOL_NO_WRITE))\n\t\t\tcontinue;\n\t\tif (sym_has_value(sym) && (sym->flags & SYMBOL_WRITE)) {\n\t\t\t/* check that calculated value agrees with saved value */\n\t\t\tswitch (sym->type) {\n\t\t\tcase S_BOOLEAN:\n\t\t\tcase S_TRISTATE:\n\t\t\t\tif (sym->def[S_DEF_USER].tri == sym_get_tristate_value(sym))\n\t\t\t\t\tcontinue;\n\t\t\t\tbreak;\n\t\t\tdefault:\n\t\t\t\tif (!strcmp(sym->curr.val, sym->def[S_DEF_USER].val))\n\t\t\t\t\tcontinue;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t} else if (!sym_has_value(sym) && !(sym->flags & SYMBOL_WRITE))\n\t\t\t/* no previous value and not saved */\n\t\t\tcontinue;\n\t\tconf_unsaved++;\n\t\t/* maybe print value in verbose mode... */\n\t}\n\n\tfor_all_symbols(i, sym) {\n\t\tif (sym_has_value(sym) && !sym_is_choice_value(sym)) {\n\t\t\t/* Reset values of generates values, so they'll appear\n\t\t\t * as new, if they should become visible, but that\n\t\t\t * doesn't quite work if the Kconfig and the saved\n\t\t\t * configuration disagree.\n\t\t\t */\n\t\t\tif (sym->visible == no && !conf_unsaved)\n\t\t\t\tsym->flags &= ~SYMBOL_DEF_USER;\n\t\t\tswitch (sym->type) {\n\t\t\tcase S_STRING:\n\t\t\tcase S_INT:\n\t\t\tcase S_HEX:\n\t\t\t\t/* Reset a string value if it's out of range */\n\t\t\t\tif (sym_string_within_range(sym, sym->def[S_DEF_USER].val))\n\t\t\t\t\tbreak;\n\t\t\t\tsym->flags &= ~(SYMBOL_VALID|SYMBOL_DEF_USER);\n\t\t\t\tconf_unsaved++;\n\t\t\t\tbreak;\n\t\t\tdefault:\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t}\n\n\tif (conf_warnings || conf_unsaved)\n\t\tconf_set_changed(true);\n\n\treturn 0;\n}\n\n/*\n * Kconfig configuration printer\n *\n * This printer is used when generating the resulting configuration after\n * kconfig invocation and `defconfig' files. Unset symbol might be omitted by\n * passing a non-NULL argument to the printer.\n *\n */\nstatic void\nkconfig_print_symbol(FILE *fp, struct symbol *sym, const char *value, void *arg)\n{\n\n\tswitch (sym->type) {\n\tcase S_BOOLEAN:\n\tcase S_TRISTATE:\n\t\tif (*value == 'n') {\n\t\t\tbool skip_unset = (arg != NULL);\n\n\t\t\tif (!skip_unset)\n\t\t\t\tfprintf(fp, \"# %s%s is not set\\n\",\n\t\t\t\t    CONFIG_, sym->name);\n\t\t\treturn;\n\t\t}\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\n\tfprintf(fp, \"%s%s=%s\\n\", CONFIG_, sym->name, value);\n}\n\nstatic void\nkconfig_print_comment(FILE *fp, const char *value, void *arg)\n{\n\tconst char *p = value;\n\tsize_t l;\n\n\tfor (;;) {\n\t\tl = strcspn(p, \"\\n\");\n\t\tfprintf(fp, \"#\");\n\t\tif (l) {\n\t\t\tfprintf(fp, \" \");\n\t\t\txfwrite(p, l, 1, fp);\n\t\t\tp += l;\n\t\t}\n\t\tfprintf(fp, \"\\n\");\n\t\tif (*p++ == '\\0')\n\t\t\tbreak;\n\t}\n}\n\nstatic struct conf_printer kconfig_printer_cb =\n{\n\t.print_symbol = kconfig_print_symbol,\n\t.print_comment = kconfig_print_comment,\n};\n\n/*\n * Header printer\n *\n * This printer is used when generating the `include/generated/autoconf.h' file.\n */\nstatic void\nheader_print_symbol(FILE *fp, struct symbol *sym, const char *value, void *arg)\n{\n\n\tswitch (sym->type) {\n\tcase S_BOOLEAN:\n\tcase S_TRISTATE: {\n\t\tconst char *suffix = \"\";\n\n\t\tswitch (*value) {\n\t\tcase 'n':\n\t\t\tbreak;\n\t\tcase 'm':\n\t\t\tsuffix = \"_MODULE\";\n\t\t\t/* fall through */\n\t\tdefault:\n\t\t\tfprintf(fp, \"#define %s%s%s 1\\n\",\n\t\t\t    CONFIG_, sym->name, suffix);\n\t\t}\n\t\tbreak;\n\t}\n\tcase S_HEX: {\n\t\tconst char *prefix = \"\";\n\n\t\tif (value[0] != '0' || (value[1] != 'x' && value[1] != 'X'))\n\t\t\tprefix = \"0x\";\n\t\tfprintf(fp, \"#define %s%s %s%s\\n\",\n\t\t    CONFIG_, sym->name, prefix, value);\n\t\tbreak;\n\t}\n\tcase S_STRING:\n\tcase S_INT:\n\t\tfprintf(fp, \"#define %s%s %s\\n\",\n\t\t    CONFIG_, sym->name, value);\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\n}\n\nstatic void\nheader_print_comment(FILE *fp, const char *value, void *arg)\n{\n\tconst char *p = value;\n\tsize_t l;\n\n\tfprintf(fp, \"/*\\n\");\n\tfor (;;) {\n\t\tl = strcspn(p, \"\\n\");\n\t\tfprintf(fp, \" *\");\n\t\tif (l) {\n\t\t\tfprintf(fp, \" \");\n\t\t\txfwrite(p, l, 1, fp);\n\t\t\tp += l;\n\t\t}\n\t\tfprintf(fp, \"\\n\");\n\t\tif (*p++ == '\\0')\n\t\t\tbreak;\n\t}\n\tfprintf(fp, \" */\\n\");\n}\n\nstatic struct conf_printer header_printer_cb =\n{\n\t.print_symbol = header_print_symbol,\n\t.print_comment = header_print_comment,\n};\n\nstatic void conf_write_symbol(FILE *fp, struct symbol *sym,\n\t\t\t      struct conf_printer *printer, void *printer_arg)\n{\n\tconst char *str;\n\n\tswitch (sym->type) {\n\tcase S_UNKNOWN:\n\t\tbreak;\n\tcase S_STRING:\n\t\tstr = sym_get_string_value(sym);\n\t\tstr = sym_escape_string_value(str);\n\t\tprinter->print_symbol(fp, sym, str, printer_arg);\n\t\tfree((void *)str);\n\t\tbreak;\n\tdefault:\n\t\tstr = sym_get_string_value(sym);\n\t\tprinter->print_symbol(fp, sym, str, printer_arg);\n\t}\n}\n\nstatic void\nconf_write_heading(FILE *fp, struct conf_printer *printer, void *printer_arg)\n{\n\tchar buf[256];\n\n\tsnprintf(buf, sizeof(buf),\n\t    \"\\n\"\n\t    \"Automatically generated file; DO NOT EDIT.\\n\"\n\t    \"%s\\n\",\n\t    rootmenu.prompt->text);\n\n\tprinter->print_comment(fp, buf, printer_arg);\n}\n\n/*\n * Write out a minimal config.\n * All values that has default values are skipped as this is redundant.\n */\nint conf_write_defconfig(const char *filename)\n{\n\tstruct symbol *sym;\n\tstruct menu *menu;\n\tFILE *out;\n\n\tout = fopen(filename, \"w\");\n\tif (!out)\n\t\treturn 1;\n\n\tsym_clear_all_valid();\n\n\t/* Traverse all menus to find all relevant symbols */\n\tmenu = rootmenu.list;\n\n\twhile (menu != NULL)\n\t{\n\t\tsym = menu->sym;\n\t\tif (sym == NULL) {\n\t\t\tif (!menu_is_visible(menu))\n\t\t\t\tgoto next_menu;\n\t\t} else if (!sym_is_choice(sym)) {\n\t\t\tsym_calc_value(sym);\n\t\t\tif (!(sym->flags & SYMBOL_WRITE))\n\t\t\t\tgoto next_menu;\n\t\t\tsym->flags &= ~SYMBOL_WRITE;\n\t\t\t/* If we cannot change the symbol - skip */\n\t\t\tif (!sym_is_changeable(sym))\n\t\t\t\tgoto next_menu;\n\t\t\t/* If symbol equals to default value - skip */\n\t\t\tif (strcmp(sym_get_string_value(sym), sym_get_string_default(sym)) == 0)\n\t\t\t\tgoto next_menu;\n\n\t\t\t/*\n\t\t\t * If symbol is a choice value and equals to the\n\t\t\t * default for a choice - skip.\n\t\t\t * But only if value is bool and equal to \"y\" and\n\t\t\t * choice is not \"optional\".\n\t\t\t * (If choice is \"optional\" then all values can be \"n\")\n\t\t\t */\n\t\t\tif (sym_is_choice_value(sym)) {\n\t\t\t\tstruct symbol *cs;\n\t\t\t\tstruct symbol *ds;\n\n\t\t\t\tcs = prop_get_symbol(sym_get_choice_prop(sym));\n\t\t\t\tds = sym_choice_default(cs);\n\t\t\t\tif (!sym_is_optional(cs) && sym == ds) {\n\t\t\t\t\tif ((sym->type == S_BOOLEAN) &&\n\t\t\t\t\t    sym_get_tristate_value(sym) == yes)\n\t\t\t\t\t\tgoto next_menu;\n\t\t\t\t}\n\t\t\t}\n\t\t\tconf_write_symbol(out, sym, &kconfig_printer_cb, NULL);\n\t\t}\nnext_menu:\n\t\tif (menu->list != NULL) {\n\t\t\tmenu = menu->list;\n\t\t}\n\t\telse if (menu->next != NULL) {\n\t\t\tmenu = menu->next;\n\t\t} else {\n\t\t\twhile ((menu = menu->parent)) {\n\t\t\t\tif (menu->next != NULL) {\n\t\t\t\t\tmenu = menu->next;\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n\tfclose(out);\n\treturn 0;\n}\n\nint conf_write(const char *name)\n{\n\tFILE *out;\n\tstruct symbol *sym;\n\tstruct menu *menu;\n\tconst char *str;\n\tchar tmpname[PATH_MAX + 1], oldname[PATH_MAX + 1];\n\tchar *env;\n\tint i;\n\tbool need_newline = false;\n\n\tif (!name)\n\t\tname = conf_get_configname();\n\n\tif (!*name) {\n\t\tfprintf(stderr, \"config name is empty\\n\");\n\t\treturn -1;\n\t}\n\n\tif (is_dir(name)) {\n\t\tfprintf(stderr, \"%s: Is a directory\\n\", name);\n\t\treturn -1;\n\t}\n\n\tif (make_parent_dir(name))\n\t\treturn -1;\n\n\tenv = getenv(\"KCONFIG_OVERWRITECONFIG\");\n\tif (env && *env) {\n\t\t*tmpname = 0;\n\t\tout = fopen(name, \"w\");\n\t} else {\n\t\tsnprintf(tmpname, sizeof(tmpname), \"%s.%d.tmp\",\n\t\t\t name, (int)getpid());\n\t\tout = fopen(tmpname, \"w\");\n\t}\n\tif (!out)\n\t\treturn 1;\n\n\tconf_write_heading(out, &kconfig_printer_cb, NULL);\n\n\tif (!conf_get_changed())\n\t\tsym_clear_all_valid();\n\n\tmenu = rootmenu.list;\n\twhile (menu) {\n\t\tsym = menu->sym;\n\t\tif (!sym) {\n\t\t\tif (!menu_is_visible(menu))\n\t\t\t\tgoto next;\n\t\t\tstr = menu_get_prompt(menu);\n\t\t\tfprintf(out, \"\\n\"\n\t\t\t\t     \"#\\n\"\n\t\t\t\t     \"# %s\\n\"\n\t\t\t\t     \"#\\n\", str);\n\t\t\tneed_newline = false;\n\t\t} else if (!(sym->flags & SYMBOL_CHOICE) &&\n\t\t\t   !(sym->flags & SYMBOL_WRITTEN)) {\n\t\t\tsym_calc_value(sym);\n\t\t\tif (!(sym->flags & SYMBOL_WRITE))\n\t\t\t\tgoto next;\n\t\t\tif (need_newline) {\n\t\t\t\tfprintf(out, \"\\n\");\n\t\t\t\tneed_newline = false;\n\t\t\t}\n\t\t\tsym->flags |= SYMBOL_WRITTEN;\n\t\t\tconf_write_symbol(out, sym, &kconfig_printer_cb, NULL);\n\t\t}\n\nnext:\n\t\tif (menu->list) {\n\t\t\tmenu = menu->list;\n\t\t\tcontinue;\n\t\t}\n\t\tif (menu->next)\n\t\t\tmenu = menu->next;\n\t\telse while ((menu = menu->parent)) {\n\t\t\tif (!menu->sym && menu_is_visible(menu) &&\n\t\t\t    menu != &rootmenu) {\n\t\t\t\tstr = menu_get_prompt(menu);\n\t\t\t\tfprintf(out, \"# end of %s\\n\", str);\n\t\t\t\tneed_newline = true;\n\t\t\t}\n\t\t\tif (menu->next) {\n\t\t\t\tmenu = menu->next;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t}\n\tfclose(out);\n\n\tfor_all_symbols(i, sym)\n\t\tsym->flags &= ~SYMBOL_WRITTEN;\n\n\tif (*tmpname) {\n\t\tif (is_same(name, tmpname)) {\n\t\t\tconf_message(\"No change to %s\", name);\n\t\t\tunlink(tmpname);\n\t\t\tconf_set_changed(false);\n\t\t\treturn 0;\n\t\t}\n\n\t\tsnprintf(oldname, sizeof(oldname), \"%s.old\", name);\n\t\trename(name, oldname);\n\t\tif (rename(tmpname, name))\n\t\t\treturn 1;\n\t}\n\n\tconf_message(\"configuration written to %s\", name);\n\n\tconf_set_changed(false);\n\n\treturn 0;\n}\n\n/* write a dependency file as used by kbuild to track dependencies */\nstatic int conf_write_dep(const char *name)\n{\n\tstruct file *file;\n\tFILE *out;\n\n\tout = fopen(\"..config.tmp\", \"w\");\n\tif (!out)\n\t\treturn 1;\n\tfprintf(out, \"deps_config := \\\\\\n\");\n\tfor (file = file_list; file; file = file->next) {\n\t\tif (file->next)\n\t\t\tfprintf(out, \"\\t%s \\\\\\n\", file->name);\n\t\telse\n\t\t\tfprintf(out, \"\\t%s\\n\", file->name);\n\t}\n\tfprintf(out, \"\\n%s: \\\\\\n\"\n\t\t     \"\\t$(deps_config)\\n\\n\", conf_get_autoconfig_name());\n\n\tenv_write_dep(out, conf_get_autoconfig_name());\n\n\tfprintf(out, \"\\n$(deps_config): ;\\n\");\n\tfclose(out);\n\n\tif (make_parent_dir(name))\n\t\treturn 1;\n\trename(\"..config.tmp\", name);\n\treturn 0;\n}\n\nstatic int conf_touch_deps(void)\n{\n\tconst char *name;\n\tstruct symbol *sym;\n\tint res, i;\n\n\tstrcpy(depfile_path, \"include/config/\");\n\tdepfile_prefix_len = strlen(depfile_path);\n\n\tname = conf_get_autoconfig_name();\n\tconf_read_simple(name, S_DEF_AUTO);\n\tsym_calc_value(modules_sym);\n\n\tfor_all_symbols(i, sym) {\n\t\tsym_calc_value(sym);\n\t\tif ((sym->flags & SYMBOL_NO_WRITE) || !sym->name)\n\t\t\tcontinue;\n\t\tif (sym->flags & SYMBOL_WRITE) {\n\t\t\tif (sym->flags & SYMBOL_DEF_AUTO) {\n\t\t\t\t/*\n\t\t\t\t * symbol has old and new value,\n\t\t\t\t * so compare them...\n\t\t\t\t */\n\t\t\t\tswitch (sym->type) {\n\t\t\t\tcase S_BOOLEAN:\n\t\t\t\tcase S_TRISTATE:\n\t\t\t\t\tif (sym_get_tristate_value(sym) ==\n\t\t\t\t\t    sym->def[S_DEF_AUTO].tri)\n\t\t\t\t\t\tcontinue;\n\t\t\t\t\tbreak;\n\t\t\t\tcase S_STRING:\n\t\t\t\tcase S_HEX:\n\t\t\t\tcase S_INT:\n\t\t\t\t\tif (!strcmp(sym_get_string_value(sym),\n\t\t\t\t\t\t    sym->def[S_DEF_AUTO].val))\n\t\t\t\t\t\tcontinue;\n\t\t\t\t\tbreak;\n\t\t\t\tdefault:\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\t/*\n\t\t\t\t * If there is no old value, only 'no' (unset)\n\t\t\t\t * is allowed as new value.\n\t\t\t\t */\n\t\t\t\tswitch (sym->type) {\n\t\t\t\tcase S_BOOLEAN:\n\t\t\t\tcase S_TRISTATE:\n\t\t\t\t\tif (sym_get_tristate_value(sym) == no)\n\t\t\t\t\t\tcontinue;\n\t\t\t\t\tbreak;\n\t\t\t\tdefault:\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t}\n\t\t} else if (!(sym->flags & SYMBOL_DEF_AUTO))\n\t\t\t/* There is neither an old nor a new value. */\n\t\t\tcontinue;\n\t\t/* else\n\t\t *\tThere is an old value, but no new value ('no' (unset)\n\t\t *\tisn't saved in auto.conf, so the old value is always\n\t\t *\tdifferent from 'no').\n\t\t */\n\n\t\tres = conf_touch_dep(sym->name);\n\t\tif (res)\n\t\t\treturn res;\n\t}\n\n\treturn 0;\n}\n\nint conf_write_autoconf(int overwrite)\n{\n\tstruct symbol *sym;\n\tconst char *name;\n\tconst char *autoconf_name = conf_get_autoconfig_name();\n\tFILE *out, *out_h;\n\tint i;\n\n#ifndef OPENWRT_DOES_NOT_WANT_THIS\n\treturn 0;\n#endif\n\tif (!overwrite && is_present(autoconf_name))\n\t\treturn 0;\n\n\tconf_write_dep(\"include/config/auto.conf.cmd\");\n\n\tif (conf_touch_deps())\n\t\treturn 1;\n\n\tout = fopen(\".tmpconfig\", \"w\");\n\tif (!out)\n\t\treturn 1;\n\n\tout_h = fopen(\".tmpconfig.h\", \"w\");\n\tif (!out_h) {\n\t\tfclose(out);\n\t\treturn 1;\n\t}\n\n\tconf_write_heading(out, &kconfig_printer_cb, NULL);\n\tconf_write_heading(out_h, &header_printer_cb, NULL);\n\n\tfor_all_symbols(i, sym) {\n\t\tsym_calc_value(sym);\n\t\tif (!(sym->flags & SYMBOL_WRITE) || !sym->name)\n\t\t\tcontinue;\n\n\t\t/* write symbols to auto.conf and autoconf.h */\n\t\tconf_write_symbol(out, sym, &kconfig_printer_cb, (void *)1);\n\t\tconf_write_symbol(out_h, sym, &header_printer_cb, NULL);\n\t}\n\tfclose(out);\n\tfclose(out_h);\n\n\tname = getenv(\"KCONFIG_AUTOHEADER\");\n\tif (!name)\n\t\tname = \"include/generated/autoconf.h\";\n\tif (make_parent_dir(name))\n\t\treturn 1;\n\tif (rename(\".tmpconfig.h\", name))\n\t\treturn 1;\n\n\tif (make_parent_dir(autoconf_name))\n\t\treturn 1;\n\t/*\n\t * This must be the last step, kbuild has a dependency on auto.conf\n\t * and this marks the successful completion of the previous steps.\n\t */\n\tif (rename(\".tmpconfig\", autoconf_name))\n\t\treturn 1;\n\n\treturn 0;\n}\n\nstatic bool conf_changed;\nstatic void (*conf_changed_callback)(void);\n\nvoid conf_set_changed(bool val)\n{\n\tif (conf_changed_callback && conf_changed != val)\n\t\tconf_changed_callback();\n\n\tconf_changed = val;\n}\n\nbool conf_get_changed(void)\n{\n\treturn conf_changed;\n}\n\nvoid conf_set_changed_callback(void (*fn)(void))\n{\n\tconf_changed_callback = fn;\n}\n\nvoid set_all_choice_values(struct symbol *csym)\n{\n\tstruct property *prop;\n\tstruct symbol *sym;\n\tstruct expr *e;\n\n\tprop = sym_get_choice_prop(csym);\n\n\t/*\n\t * Set all non-assinged choice values to no\n\t */\n\texpr_list_for_each_sym(prop->expr, e, sym) {\n\t\tif (!sym_has_value(sym))\n\t\t\tsym->def[S_DEF_USER].tri = no;\n\t}\n\tcsym->flags |= SYMBOL_DEF_USER;\n\t/* clear VALID to get value calculated */\n\tcsym->flags &= ~(SYMBOL_VALID | SYMBOL_NEED_SET_CHOICE_VALUES);\n}\n"
  },
  {
    "path": "scripts/config/expr.c",
    "content": "// SPDX-License-Identifier: GPL-2.0-only\n/*\n * Copyright (C) 2002 Roman Zippel <zippel@linux-m68k.org>\n */\n\n#include <ctype.h>\n#include <errno.h>\n#include <stdio.h>\n#include <stdlib.h>\n#include <string.h>\n\n#include \"lkc.h\"\n\n#define DEBUG_EXPR\t0\n\nstatic struct expr *expr_eliminate_yn(struct expr *e);\n\nstruct expr *expr_alloc_symbol(struct symbol *sym)\n{\n\tstruct expr *e = xcalloc(1, sizeof(*e));\n\te->type = E_SYMBOL;\n\te->left.sym = sym;\n\treturn e;\n}\n\nstruct expr *expr_alloc_one(enum expr_type type, struct expr *ce)\n{\n\tstruct expr *e = xcalloc(1, sizeof(*e));\n\te->type = type;\n\te->left.expr = ce;\n\treturn e;\n}\n\nstruct expr *expr_alloc_two(enum expr_type type, struct expr *e1, struct expr *e2)\n{\n\tstruct expr *e = xcalloc(1, sizeof(*e));\n\te->type = type;\n\te->left.expr = e1;\n\te->right.expr = e2;\n\treturn e;\n}\n\nstruct expr *expr_alloc_comp(enum expr_type type, struct symbol *s1, struct symbol *s2)\n{\n\tstruct expr *e = xcalloc(1, sizeof(*e));\n\te->type = type;\n\te->left.sym = s1;\n\te->right.sym = s2;\n\treturn e;\n}\n\nstruct expr *expr_alloc_and(struct expr *e1, struct expr *e2)\n{\n\tif (!e1)\n\t\treturn e2;\n\treturn e2 ? expr_alloc_two(E_AND, e1, e2) : e1;\n}\n\nstruct expr *expr_alloc_or(struct expr *e1, struct expr *e2)\n{\n\tif (!e1)\n\t\treturn e2;\n\treturn e2 ? expr_alloc_two(E_OR, e1, e2) : e1;\n}\n\nstruct expr *expr_copy(const struct expr *org)\n{\n\tstruct expr *e;\n\n\tif (!org)\n\t\treturn NULL;\n\n\te = xmalloc(sizeof(*org));\n\tmemcpy(e, org, sizeof(*org));\n\tswitch (org->type) {\n\tcase E_SYMBOL:\n\t\te->left = org->left;\n\t\tbreak;\n\tcase E_NOT:\n\t\te->left.expr = expr_copy(org->left.expr);\n\t\tbreak;\n\tcase E_EQUAL:\n\tcase E_GEQ:\n\tcase E_GTH:\n\tcase E_LEQ:\n\tcase E_LTH:\n\tcase E_UNEQUAL:\n\t\te->left.sym = org->left.sym;\n\t\te->right.sym = org->right.sym;\n\t\tbreak;\n\tcase E_AND:\n\tcase E_OR:\n\tcase E_LIST:\n\t\te->left.expr = expr_copy(org->left.expr);\n\t\te->right.expr = expr_copy(org->right.expr);\n\t\tbreak;\n\tdefault:\n\t\tfprintf(stderr, \"can't copy type %d\\n\", e->type);\n\t\tfree(e);\n\t\te = NULL;\n\t\tbreak;\n\t}\n\n\treturn e;\n}\n\nvoid expr_free(struct expr *e)\n{\n\tif (!e)\n\t\treturn;\n\n\tswitch (e->type) {\n\tcase E_SYMBOL:\n\t\tbreak;\n\tcase E_NOT:\n\t\texpr_free(e->left.expr);\n\t\tbreak;\n\tcase E_EQUAL:\n\tcase E_GEQ:\n\tcase E_GTH:\n\tcase E_LEQ:\n\tcase E_LTH:\n\tcase E_UNEQUAL:\n\t\tbreak;\n\tcase E_OR:\n\tcase E_AND:\n\t\texpr_free(e->left.expr);\n\t\texpr_free(e->right.expr);\n\t\tbreak;\n\tdefault:\n\t\tfprintf(stderr, \"how to free type %d?\\n\", e->type);\n\t\tbreak;\n\t}\n\tfree(e);\n}\n\nstatic int trans_count;\n\n#define e1 (*ep1)\n#define e2 (*ep2)\n\n/*\n * expr_eliminate_eq() helper.\n *\n * Walks the two expression trees given in 'ep1' and 'ep2'. Any node that does\n * not have type 'type' (E_OR/E_AND) is considered a leaf, and is compared\n * against all other leaves. Two equal leaves are both replaced with either 'y'\n * or 'n' as appropriate for 'type', to be eliminated later.\n */\nstatic void __expr_eliminate_eq(enum expr_type type, struct expr **ep1, struct expr **ep2)\n{\n\t/* Recurse down to leaves */\n\n\tif (e1->type == type) {\n\t\t__expr_eliminate_eq(type, &e1->left.expr, &e2);\n\t\t__expr_eliminate_eq(type, &e1->right.expr, &e2);\n\t\treturn;\n\t}\n\tif (e2->type == type) {\n\t\t__expr_eliminate_eq(type, &e1, &e2->left.expr);\n\t\t__expr_eliminate_eq(type, &e1, &e2->right.expr);\n\t\treturn;\n\t}\n\n\t/* e1 and e2 are leaves. Compare them. */\n\n\tif (e1->type == E_SYMBOL && e2->type == E_SYMBOL &&\n\t    e1->left.sym == e2->left.sym &&\n\t    (e1->left.sym == &symbol_yes || e1->left.sym == &symbol_no))\n\t\treturn;\n\tif (!expr_eq(e1, e2))\n\t\treturn;\n\n\t/* e1 and e2 are equal leaves. Prepare them for elimination. */\n\n\ttrans_count++;\n\texpr_free(e1); expr_free(e2);\n\tswitch (type) {\n\tcase E_OR:\n\t\te1 = expr_alloc_symbol(&symbol_no);\n\t\te2 = expr_alloc_symbol(&symbol_no);\n\t\tbreak;\n\tcase E_AND:\n\t\te1 = expr_alloc_symbol(&symbol_yes);\n\t\te2 = expr_alloc_symbol(&symbol_yes);\n\t\tbreak;\n\tdefault:\n\t\t;\n\t}\n}\n\n/*\n * Rewrites the expressions 'ep1' and 'ep2' to remove operands common to both.\n * Example reductions:\n *\n *\tep1: A && B           ->  ep1: y\n *\tep2: A && B && C      ->  ep2: C\n *\n *\tep1: A || B           ->  ep1: n\n *\tep2: A || B || C      ->  ep2: C\n *\n *\tep1: A && (B && FOO)  ->  ep1: FOO\n *\tep2: (BAR && B) && A  ->  ep2: BAR\n *\n *\tep1: A && (B || C)    ->  ep1: y\n *\tep2: (C || B) && A    ->  ep2: y\n *\n * Comparisons are done between all operands at the same \"level\" of && or ||.\n * For example, in the expression 'e1 && (e2 || e3) && (e4 || e5)', the\n * following operands will be compared:\n *\n *\t- 'e1', 'e2 || e3', and 'e4 || e5', against each other\n *\t- e2 against e3\n *\t- e4 against e5\n *\n * Parentheses are irrelevant within a single level. 'e1 && (e2 && e3)' and\n * '(e1 && e2) && e3' are both a single level.\n *\n * See __expr_eliminate_eq() as well.\n */\nvoid expr_eliminate_eq(struct expr **ep1, struct expr **ep2)\n{\n\tif (!e1 || !e2)\n\t\treturn;\n\tswitch (e1->type) {\n\tcase E_OR:\n\tcase E_AND:\n\t\t__expr_eliminate_eq(e1->type, ep1, ep2);\n\tdefault:\n\t\t;\n\t}\n\tif (e1->type != e2->type) switch (e2->type) {\n\tcase E_OR:\n\tcase E_AND:\n\t\t__expr_eliminate_eq(e2->type, ep1, ep2);\n\tdefault:\n\t\t;\n\t}\n\te1 = expr_eliminate_yn(e1);\n\te2 = expr_eliminate_yn(e2);\n}\n\n#undef e1\n#undef e2\n\n/*\n * Returns true if 'e1' and 'e2' are equal, after minor simplification. Two\n * &&/|| expressions are considered equal if every operand in one expression\n * equals some operand in the other (operands do not need to appear in the same\n * order), recursively.\n */\nint expr_eq(struct expr *e1, struct expr *e2)\n{\n\tint res, old_count;\n\n\t/*\n\t * A NULL expr is taken to be yes, but there's also a different way to\n\t * represent yes. expr_is_yes() checks for either representation.\n\t */\n\tif (!e1 || !e2)\n\t\treturn expr_is_yes(e1) && expr_is_yes(e2);\n\n\tif (e1->type != e2->type)\n\t\treturn 0;\n\tswitch (e1->type) {\n\tcase E_EQUAL:\n\tcase E_GEQ:\n\tcase E_GTH:\n\tcase E_LEQ:\n\tcase E_LTH:\n\tcase E_UNEQUAL:\n\t\treturn e1->left.sym == e2->left.sym && e1->right.sym == e2->right.sym;\n\tcase E_SYMBOL:\n\t\treturn e1->left.sym == e2->left.sym;\n\tcase E_NOT:\n\t\treturn expr_eq(e1->left.expr, e2->left.expr);\n\tcase E_AND:\n\tcase E_OR:\n\t\te1 = expr_copy(e1);\n\t\te2 = expr_copy(e2);\n\t\told_count = trans_count;\n\t\texpr_eliminate_eq(&e1, &e2);\n\t\tres = (e1->type == E_SYMBOL && e2->type == E_SYMBOL &&\n\t\t       e1->left.sym == e2->left.sym);\n\t\texpr_free(e1);\n\t\texpr_free(e2);\n\t\ttrans_count = old_count;\n\t\treturn res;\n\tcase E_LIST:\n\tcase E_RANGE:\n\tcase E_NONE:\n\t\t/* panic */;\n\t}\n\n\tif (DEBUG_EXPR) {\n\t\texpr_fprint(e1, stdout);\n\t\tprintf(\" = \");\n\t\texpr_fprint(e2, stdout);\n\t\tprintf(\" ?\\n\");\n\t}\n\n\treturn 0;\n}\n\n/*\n * Recursively performs the following simplifications in-place (as well as the\n * corresponding simplifications with swapped operands):\n *\n *\texpr && n  ->  n\n *\texpr && y  ->  expr\n *\texpr || n  ->  expr\n *\texpr || y  ->  y\n *\n * Returns the optimized expression.\n */\nstatic struct expr *expr_eliminate_yn(struct expr *e)\n{\n\tstruct expr *tmp;\n\n\tif (e) switch (e->type) {\n\tcase E_AND:\n\t\te->left.expr = expr_eliminate_yn(e->left.expr);\n\t\te->right.expr = expr_eliminate_yn(e->right.expr);\n\t\tif (e->left.expr->type == E_SYMBOL) {\n\t\t\tif (e->left.expr->left.sym == &symbol_no) {\n\t\t\t\texpr_free(e->left.expr);\n\t\t\t\texpr_free(e->right.expr);\n\t\t\t\te->type = E_SYMBOL;\n\t\t\t\te->left.sym = &symbol_no;\n\t\t\t\te->right.expr = NULL;\n\t\t\t\treturn e;\n\t\t\t} else if (e->left.expr->left.sym == &symbol_yes) {\n\t\t\t\tfree(e->left.expr);\n\t\t\t\ttmp = e->right.expr;\n\t\t\t\t*e = *(e->right.expr);\n\t\t\t\tfree(tmp);\n\t\t\t\treturn e;\n\t\t\t}\n\t\t}\n\t\tif (e->right.expr->type == E_SYMBOL) {\n\t\t\tif (e->right.expr->left.sym == &symbol_no) {\n\t\t\t\texpr_free(e->left.expr);\n\t\t\t\texpr_free(e->right.expr);\n\t\t\t\te->type = E_SYMBOL;\n\t\t\t\te->left.sym = &symbol_no;\n\t\t\t\te->right.expr = NULL;\n\t\t\t\treturn e;\n\t\t\t} else if (e->right.expr->left.sym == &symbol_yes) {\n\t\t\t\tfree(e->right.expr);\n\t\t\t\ttmp = e->left.expr;\n\t\t\t\t*e = *(e->left.expr);\n\t\t\t\tfree(tmp);\n\t\t\t\treturn e;\n\t\t\t}\n\t\t}\n\t\tbreak;\n\tcase E_OR:\n\t\te->left.expr = expr_eliminate_yn(e->left.expr);\n\t\te->right.expr = expr_eliminate_yn(e->right.expr);\n\t\tif (e->left.expr->type == E_SYMBOL) {\n\t\t\tif (e->left.expr->left.sym == &symbol_no) {\n\t\t\t\tfree(e->left.expr);\n\t\t\t\ttmp = e->right.expr;\n\t\t\t\t*e = *(e->right.expr);\n\t\t\t\tfree(tmp);\n\t\t\t\treturn e;\n\t\t\t} else if (e->left.expr->left.sym == &symbol_yes) {\n\t\t\t\texpr_free(e->left.expr);\n\t\t\t\texpr_free(e->right.expr);\n\t\t\t\te->type = E_SYMBOL;\n\t\t\t\te->left.sym = &symbol_yes;\n\t\t\t\te->right.expr = NULL;\n\t\t\t\treturn e;\n\t\t\t}\n\t\t}\n\t\tif (e->right.expr->type == E_SYMBOL) {\n\t\t\tif (e->right.expr->left.sym == &symbol_no) {\n\t\t\t\tfree(e->right.expr);\n\t\t\t\ttmp = e->left.expr;\n\t\t\t\t*e = *(e->left.expr);\n\t\t\t\tfree(tmp);\n\t\t\t\treturn e;\n\t\t\t} else if (e->right.expr->left.sym == &symbol_yes) {\n\t\t\t\texpr_free(e->left.expr);\n\t\t\t\texpr_free(e->right.expr);\n\t\t\t\te->type = E_SYMBOL;\n\t\t\t\te->left.sym = &symbol_yes;\n\t\t\t\te->right.expr = NULL;\n\t\t\t\treturn e;\n\t\t\t}\n\t\t}\n\t\tbreak;\n\tdefault:\n\t\t;\n\t}\n\treturn e;\n}\n\n/*\n * bool FOO!=n => FOO\n */\nstruct expr *expr_trans_bool(struct expr *e)\n{\n\tif (!e)\n\t\treturn NULL;\n\tswitch (e->type) {\n\tcase E_AND:\n\tcase E_OR:\n\tcase E_NOT:\n\t\te->left.expr = expr_trans_bool(e->left.expr);\n\t\te->right.expr = expr_trans_bool(e->right.expr);\n\t\tbreak;\n\tcase E_UNEQUAL:\n\t\t// FOO!=n -> FOO\n\t\tif (e->left.sym->type == S_TRISTATE) {\n\t\t\tif (e->right.sym == &symbol_no) {\n\t\t\t\te->type = E_SYMBOL;\n\t\t\t\te->right.sym = NULL;\n\t\t\t}\n\t\t}\n\t\tbreak;\n\tdefault:\n\t\t;\n\t}\n\treturn e;\n}\n\n/*\n * e1 || e2 -> ?\n */\nstatic struct expr *expr_join_or(struct expr *e1, struct expr *e2)\n{\n\tstruct expr *tmp;\n\tstruct symbol *sym1, *sym2;\n\n\tif (expr_eq(e1, e2))\n\t\treturn expr_copy(e1);\n\tif (e1->type != E_EQUAL && e1->type != E_UNEQUAL && e1->type != E_SYMBOL && e1->type != E_NOT)\n\t\treturn NULL;\n\tif (e2->type != E_EQUAL && e2->type != E_UNEQUAL && e2->type != E_SYMBOL && e2->type != E_NOT)\n\t\treturn NULL;\n\tif (e1->type == E_NOT) {\n\t\ttmp = e1->left.expr;\n\t\tif (tmp->type != E_EQUAL && tmp->type != E_UNEQUAL && tmp->type != E_SYMBOL)\n\t\t\treturn NULL;\n\t\tsym1 = tmp->left.sym;\n\t} else\n\t\tsym1 = e1->left.sym;\n\tif (e2->type == E_NOT) {\n\t\tif (e2->left.expr->type != E_SYMBOL)\n\t\t\treturn NULL;\n\t\tsym2 = e2->left.expr->left.sym;\n\t} else\n\t\tsym2 = e2->left.sym;\n\tif (sym1 != sym2)\n\t\treturn NULL;\n\tif (sym1->type != S_BOOLEAN && sym1->type != S_TRISTATE)\n\t\treturn NULL;\n\tif (sym1->type == S_TRISTATE) {\n\t\tif (e1->type == E_EQUAL && e2->type == E_EQUAL &&\n\t\t    ((e1->right.sym == &symbol_yes && e2->right.sym == &symbol_mod) ||\n\t\t     (e1->right.sym == &symbol_mod && e2->right.sym == &symbol_yes))) {\n\t\t\t// (a='y') || (a='m') -> (a!='n')\n\t\t\treturn expr_alloc_comp(E_UNEQUAL, sym1, &symbol_no);\n\t\t}\n\t\tif (e1->type == E_EQUAL && e2->type == E_EQUAL &&\n\t\t    ((e1->right.sym == &symbol_yes && e2->right.sym == &symbol_no) ||\n\t\t     (e1->right.sym == &symbol_no && e2->right.sym == &symbol_yes))) {\n\t\t\t// (a='y') || (a='n') -> (a!='m')\n\t\t\treturn expr_alloc_comp(E_UNEQUAL, sym1, &symbol_mod);\n\t\t}\n\t\tif (e1->type == E_EQUAL && e2->type == E_EQUAL &&\n\t\t    ((e1->right.sym == &symbol_mod && e2->right.sym == &symbol_no) ||\n\t\t     (e1->right.sym == &symbol_no && e2->right.sym == &symbol_mod))) {\n\t\t\t// (a='m') || (a='n') -> (a!='y')\n\t\t\treturn expr_alloc_comp(E_UNEQUAL, sym1, &symbol_yes);\n\t\t}\n\t}\n\tif (sym1->type == S_BOOLEAN && sym1 == sym2) {\n\t\tif ((e1->type == E_NOT && e1->left.expr->type == E_SYMBOL && e2->type == E_SYMBOL) ||\n\t\t    (e2->type == E_NOT && e2->left.expr->type == E_SYMBOL && e1->type == E_SYMBOL))\n\t\t\treturn expr_alloc_symbol(&symbol_yes);\n\t}\n\n\tif (DEBUG_EXPR) {\n\t\tprintf(\"optimize (\");\n\t\texpr_fprint(e1, stdout);\n\t\tprintf(\") || (\");\n\t\texpr_fprint(e2, stdout);\n\t\tprintf(\")?\\n\");\n\t}\n\treturn NULL;\n}\n\nstatic struct expr *expr_join_and(struct expr *e1, struct expr *e2)\n{\n\tstruct expr *tmp;\n\tstruct symbol *sym1, *sym2;\n\n\tif (expr_eq(e1, e2))\n\t\treturn expr_copy(e1);\n\tif (e1->type != E_EQUAL && e1->type != E_UNEQUAL && e1->type != E_SYMBOL && e1->type != E_NOT)\n\t\treturn NULL;\n\tif (e2->type != E_EQUAL && e2->type != E_UNEQUAL && e2->type != E_SYMBOL && e2->type != E_NOT)\n\t\treturn NULL;\n\tif (e1->type == E_NOT) {\n\t\ttmp = e1->left.expr;\n\t\tif (tmp->type != E_EQUAL && tmp->type != E_UNEQUAL && tmp->type != E_SYMBOL)\n\t\t\treturn NULL;\n\t\tsym1 = tmp->left.sym;\n\t} else\n\t\tsym1 = e1->left.sym;\n\tif (e2->type == E_NOT) {\n\t\tif (e2->left.expr->type != E_SYMBOL)\n\t\t\treturn NULL;\n\t\tsym2 = e2->left.expr->left.sym;\n\t} else\n\t\tsym2 = e2->left.sym;\n\tif (sym1 != sym2)\n\t\treturn NULL;\n\tif (sym1->type != S_BOOLEAN && sym1->type != S_TRISTATE)\n\t\treturn NULL;\n\n\tif ((e1->type == E_SYMBOL && e2->type == E_EQUAL && e2->right.sym == &symbol_yes) ||\n\t    (e2->type == E_SYMBOL && e1->type == E_EQUAL && e1->right.sym == &symbol_yes))\n\t\t// (a) && (a='y') -> (a='y')\n\t\treturn expr_alloc_comp(E_EQUAL, sym1, &symbol_yes);\n\n\tif ((e1->type == E_SYMBOL && e2->type == E_UNEQUAL && e2->right.sym == &symbol_no) ||\n\t    (e2->type == E_SYMBOL && e1->type == E_UNEQUAL && e1->right.sym == &symbol_no))\n\t\t// (a) && (a!='n') -> (a)\n\t\treturn expr_alloc_symbol(sym1);\n\n\tif ((e1->type == E_SYMBOL && e2->type == E_UNEQUAL && e2->right.sym == &symbol_mod) ||\n\t    (e2->type == E_SYMBOL && e1->type == E_UNEQUAL && e1->right.sym == &symbol_mod))\n\t\t// (a) && (a!='m') -> (a='y')\n\t\treturn expr_alloc_comp(E_EQUAL, sym1, &symbol_yes);\n\n\tif (sym1->type == S_TRISTATE) {\n\t\tif (e1->type == E_EQUAL && e2->type == E_UNEQUAL) {\n\t\t\t// (a='b') && (a!='c') -> 'b'='c' ? 'n' : a='b'\n\t\t\tsym2 = e1->right.sym;\n\t\t\tif ((e2->right.sym->flags & SYMBOL_CONST) && (sym2->flags & SYMBOL_CONST))\n\t\t\t\treturn sym2 != e2->right.sym ? expr_alloc_comp(E_EQUAL, sym1, sym2)\n\t\t\t\t\t\t\t     : expr_alloc_symbol(&symbol_no);\n\t\t}\n\t\tif (e1->type == E_UNEQUAL && e2->type == E_EQUAL) {\n\t\t\t// (a='b') && (a!='c') -> 'b'='c' ? 'n' : a='b'\n\t\t\tsym2 = e2->right.sym;\n\t\t\tif ((e1->right.sym->flags & SYMBOL_CONST) && (sym2->flags & SYMBOL_CONST))\n\t\t\t\treturn sym2 != e1->right.sym ? expr_alloc_comp(E_EQUAL, sym1, sym2)\n\t\t\t\t\t\t\t     : expr_alloc_symbol(&symbol_no);\n\t\t}\n\t\tif (e1->type == E_UNEQUAL && e2->type == E_UNEQUAL &&\n\t\t\t   ((e1->right.sym == &symbol_yes && e2->right.sym == &symbol_no) ||\n\t\t\t    (e1->right.sym == &symbol_no && e2->right.sym == &symbol_yes)))\n\t\t\t// (a!='y') && (a!='n') -> (a='m')\n\t\t\treturn expr_alloc_comp(E_EQUAL, sym1, &symbol_mod);\n\n\t\tif (e1->type == E_UNEQUAL && e2->type == E_UNEQUAL &&\n\t\t\t   ((e1->right.sym == &symbol_yes && e2->right.sym == &symbol_mod) ||\n\t\t\t    (e1->right.sym == &symbol_mod && e2->right.sym == &symbol_yes)))\n\t\t\t// (a!='y') && (a!='m') -> (a='n')\n\t\t\treturn expr_alloc_comp(E_EQUAL, sym1, &symbol_no);\n\n\t\tif (e1->type == E_UNEQUAL && e2->type == E_UNEQUAL &&\n\t\t\t   ((e1->right.sym == &symbol_mod && e2->right.sym == &symbol_no) ||\n\t\t\t    (e1->right.sym == &symbol_no && e2->right.sym == &symbol_mod)))\n\t\t\t// (a!='m') && (a!='n') -> (a='m')\n\t\t\treturn expr_alloc_comp(E_EQUAL, sym1, &symbol_yes);\n\n\t\tif ((e1->type == E_SYMBOL && e2->type == E_EQUAL && e2->right.sym == &symbol_mod) ||\n\t\t    (e2->type == E_SYMBOL && e1->type == E_EQUAL && e1->right.sym == &symbol_mod) ||\n\t\t    (e1->type == E_SYMBOL && e2->type == E_UNEQUAL && e2->right.sym == &symbol_yes) ||\n\t\t    (e2->type == E_SYMBOL && e1->type == E_UNEQUAL && e1->right.sym == &symbol_yes))\n\t\t\treturn NULL;\n\t}\n\n\tif (DEBUG_EXPR) {\n\t\tprintf(\"optimize (\");\n\t\texpr_fprint(e1, stdout);\n\t\tprintf(\") && (\");\n\t\texpr_fprint(e2, stdout);\n\t\tprintf(\")?\\n\");\n\t}\n\treturn NULL;\n}\n\n/*\n * expr_eliminate_dups() helper.\n *\n * Walks the two expression trees given in 'ep1' and 'ep2'. Any node that does\n * not have type 'type' (E_OR/E_AND) is considered a leaf, and is compared\n * against all other leaves to look for simplifications.\n */\nstatic void expr_eliminate_dups1(enum expr_type type, struct expr **ep1, struct expr **ep2)\n{\n#define e1 (*ep1)\n#define e2 (*ep2)\n\tstruct expr *tmp;\n\n\t/* Recurse down to leaves */\n\n\tif (e1->type == type) {\n\t\texpr_eliminate_dups1(type, &e1->left.expr, &e2);\n\t\texpr_eliminate_dups1(type, &e1->right.expr, &e2);\n\t\treturn;\n\t}\n\tif (e2->type == type) {\n\t\texpr_eliminate_dups1(type, &e1, &e2->left.expr);\n\t\texpr_eliminate_dups1(type, &e1, &e2->right.expr);\n\t\treturn;\n\t}\n\n\t/* e1 and e2 are leaves. Compare and process them. */\n\n\tif (e1 == e2)\n\t\treturn;\n\n\tswitch (e1->type) {\n\tcase E_OR: case E_AND:\n\t\texpr_eliminate_dups1(e1->type, &e1, &e1);\n\tdefault:\n\t\t;\n\t}\n\n\tswitch (type) {\n\tcase E_OR:\n\t\ttmp = expr_join_or(e1, e2);\n\t\tif (tmp) {\n\t\t\texpr_free(e1); expr_free(e2);\n\t\t\te1 = expr_alloc_symbol(&symbol_no);\n\t\t\te2 = tmp;\n\t\t\ttrans_count++;\n\t\t}\n\t\tbreak;\n\tcase E_AND:\n\t\ttmp = expr_join_and(e1, e2);\n\t\tif (tmp) {\n\t\t\texpr_free(e1); expr_free(e2);\n\t\t\te1 = expr_alloc_symbol(&symbol_yes);\n\t\t\te2 = tmp;\n\t\t\ttrans_count++;\n\t\t}\n\t\tbreak;\n\tdefault:\n\t\t;\n\t}\n#undef e1\n#undef e2\n}\n\n/*\n * Rewrites 'e' in-place to remove (\"join\") duplicate and other redundant\n * operands.\n *\n * Example simplifications:\n *\n *\tA || B || A    ->  A || B\n *\tA && B && A=y  ->  A=y && B\n *\n * Returns the deduplicated expression.\n */\nstruct expr *expr_eliminate_dups(struct expr *e)\n{\n\tint oldcount;\n\tif (!e)\n\t\treturn e;\n\n\toldcount = trans_count;\n\twhile (1) {\n\t\ttrans_count = 0;\n\t\tswitch (e->type) {\n\t\tcase E_OR: case E_AND:\n\t\t\texpr_eliminate_dups1(e->type, &e, &e);\n\t\tdefault:\n\t\t\t;\n\t\t}\n\t\tif (!trans_count)\n\t\t\t/* No simplifications done in this pass. We're done */\n\t\t\tbreak;\n\t\te = expr_eliminate_yn(e);\n\t}\n\ttrans_count = oldcount;\n\treturn e;\n}\n\n/*\n * Performs various simplifications involving logical operators and\n * comparisons.\n *\n * Allocates and returns a new expression.\n */\nstruct expr *expr_transform(struct expr *e)\n{\n\tstruct expr *tmp;\n\n\tif (!e)\n\t\treturn NULL;\n\tswitch (e->type) {\n\tcase E_EQUAL:\n\tcase E_GEQ:\n\tcase E_GTH:\n\tcase E_LEQ:\n\tcase E_LTH:\n\tcase E_UNEQUAL:\n\tcase E_SYMBOL:\n\tcase E_LIST:\n\t\tbreak;\n\tdefault:\n\t\te->left.expr = expr_transform(e->left.expr);\n\t\te->right.expr = expr_transform(e->right.expr);\n\t}\n\n\tswitch (e->type) {\n\tcase E_EQUAL:\n\t\tif (e->left.sym->type != S_BOOLEAN)\n\t\t\tbreak;\n\t\tif (e->right.sym == &symbol_no) {\n\t\t\te->type = E_NOT;\n\t\t\te->left.expr = expr_alloc_symbol(e->left.sym);\n\t\t\te->right.sym = NULL;\n\t\t\tbreak;\n\t\t}\n\t\tif (e->right.sym == &symbol_mod) {\n\t\t\tprintf(\"boolean symbol %s tested for 'm'? test forced to 'n'\\n\", e->left.sym->name);\n\t\t\te->type = E_SYMBOL;\n\t\t\te->left.sym = &symbol_no;\n\t\t\te->right.sym = NULL;\n\t\t\tbreak;\n\t\t}\n\t\tif (e->right.sym == &symbol_yes) {\n\t\t\te->type = E_SYMBOL;\n\t\t\te->right.sym = NULL;\n\t\t\tbreak;\n\t\t}\n\t\tbreak;\n\tcase E_UNEQUAL:\n\t\tif (e->left.sym->type != S_BOOLEAN)\n\t\t\tbreak;\n\t\tif (e->right.sym == &symbol_no) {\n\t\t\te->type = E_SYMBOL;\n\t\t\te->right.sym = NULL;\n\t\t\tbreak;\n\t\t}\n\t\tif (e->right.sym == &symbol_mod) {\n\t\t\tprintf(\"boolean symbol %s tested for 'm'? test forced to 'y'\\n\", e->left.sym->name);\n\t\t\te->type = E_SYMBOL;\n\t\t\te->left.sym = &symbol_yes;\n\t\t\te->right.sym = NULL;\n\t\t\tbreak;\n\t\t}\n\t\tif (e->right.sym == &symbol_yes) {\n\t\t\te->type = E_NOT;\n\t\t\te->left.expr = expr_alloc_symbol(e->left.sym);\n\t\t\te->right.sym = NULL;\n\t\t\tbreak;\n\t\t}\n\t\tbreak;\n\tcase E_NOT:\n\t\tswitch (e->left.expr->type) {\n\t\tcase E_NOT:\n\t\t\t// !!a -> a\n\t\t\ttmp = e->left.expr->left.expr;\n\t\t\tfree(e->left.expr);\n\t\t\tfree(e);\n\t\t\te = tmp;\n\t\t\te = expr_transform(e);\n\t\t\tbreak;\n\t\tcase E_EQUAL:\n\t\tcase E_UNEQUAL:\n\t\t\t// !a='x' -> a!='x'\n\t\t\ttmp = e->left.expr;\n\t\t\tfree(e);\n\t\t\te = tmp;\n\t\t\te->type = e->type == E_EQUAL ? E_UNEQUAL : E_EQUAL;\n\t\t\tbreak;\n\t\tcase E_LEQ:\n\t\tcase E_GEQ:\n\t\t\t// !a<='x' -> a>'x'\n\t\t\ttmp = e->left.expr;\n\t\t\tfree(e);\n\t\t\te = tmp;\n\t\t\te->type = e->type == E_LEQ ? E_GTH : E_LTH;\n\t\t\tbreak;\n\t\tcase E_LTH:\n\t\tcase E_GTH:\n\t\t\t// !a<'x' -> a>='x'\n\t\t\ttmp = e->left.expr;\n\t\t\tfree(e);\n\t\t\te = tmp;\n\t\t\te->type = e->type == E_LTH ? E_GEQ : E_LEQ;\n\t\t\tbreak;\n\t\tcase E_OR:\n\t\t\t// !(a || b) -> !a && !b\n\t\t\ttmp = e->left.expr;\n\t\t\te->type = E_AND;\n\t\t\te->right.expr = expr_alloc_one(E_NOT, tmp->right.expr);\n\t\t\ttmp->type = E_NOT;\n\t\t\ttmp->right.expr = NULL;\n\t\t\te = expr_transform(e);\n\t\t\tbreak;\n\t\tcase E_AND:\n\t\t\t// !(a && b) -> !a || !b\n\t\t\ttmp = e->left.expr;\n\t\t\te->type = E_OR;\n\t\t\te->right.expr = expr_alloc_one(E_NOT, tmp->right.expr);\n\t\t\ttmp->type = E_NOT;\n\t\t\ttmp->right.expr = NULL;\n\t\t\te = expr_transform(e);\n\t\t\tbreak;\n\t\tcase E_SYMBOL:\n\t\t\tif (e->left.expr->left.sym == &symbol_yes) {\n\t\t\t\t// !'y' -> 'n'\n\t\t\t\ttmp = e->left.expr;\n\t\t\t\tfree(e);\n\t\t\t\te = tmp;\n\t\t\t\te->type = E_SYMBOL;\n\t\t\t\te->left.sym = &symbol_no;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\tif (e->left.expr->left.sym == &symbol_mod) {\n\t\t\t\t// !'m' -> 'm'\n\t\t\t\ttmp = e->left.expr;\n\t\t\t\tfree(e);\n\t\t\t\te = tmp;\n\t\t\t\te->type = E_SYMBOL;\n\t\t\t\te->left.sym = &symbol_mod;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\tif (e->left.expr->left.sym == &symbol_no) {\n\t\t\t\t// !'n' -> 'y'\n\t\t\t\ttmp = e->left.expr;\n\t\t\t\tfree(e);\n\t\t\t\te = tmp;\n\t\t\t\te->type = E_SYMBOL;\n\t\t\t\te->left.sym = &symbol_yes;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\tbreak;\n\t\tdefault:\n\t\t\t;\n\t\t}\n\t\tbreak;\n\tdefault:\n\t\t;\n\t}\n\treturn e;\n}\n\nint expr_contains_symbol(struct expr *dep, struct symbol *sym)\n{\n\tif (!dep)\n\t\treturn 0;\n\n\tswitch (dep->type) {\n\tcase E_AND:\n\tcase E_OR:\n\t\treturn expr_contains_symbol(dep->left.expr, sym) ||\n\t\t       expr_contains_symbol(dep->right.expr, sym);\n\tcase E_SYMBOL:\n\t\treturn dep->left.sym == sym;\n\tcase E_EQUAL:\n\tcase E_GEQ:\n\tcase E_GTH:\n\tcase E_LEQ:\n\tcase E_LTH:\n\tcase E_UNEQUAL:\n\t\treturn dep->left.sym == sym ||\n\t\t       dep->right.sym == sym;\n\tcase E_NOT:\n\t\treturn expr_contains_symbol(dep->left.expr, sym);\n\tdefault:\n\t\t;\n\t}\n\treturn 0;\n}\n\nbool expr_depends_symbol(struct expr *dep, struct symbol *sym)\n{\n\tif (!dep)\n\t\treturn false;\n\n\tswitch (dep->type) {\n\tcase E_AND:\n\t\treturn expr_depends_symbol(dep->left.expr, sym) ||\n\t\t       expr_depends_symbol(dep->right.expr, sym);\n\tcase E_SYMBOL:\n\t\treturn dep->left.sym == sym;\n\tcase E_EQUAL:\n\t\tif (dep->left.sym == sym) {\n\t\t\tif (dep->right.sym == &symbol_yes || dep->right.sym == &symbol_mod)\n\t\t\t\treturn true;\n\t\t}\n\t\tbreak;\n\tcase E_UNEQUAL:\n\t\tif (dep->left.sym == sym) {\n\t\t\tif (dep->right.sym == &symbol_no)\n\t\t\t\treturn true;\n\t\t}\n\t\tbreak;\n\tdefault:\n\t\t;\n\t}\n \treturn false;\n}\n\n/*\n * Inserts explicit comparisons of type 'type' to symbol 'sym' into the\n * expression 'e'.\n *\n * Examples transformations for type == E_UNEQUAL, sym == &symbol_no:\n *\n *\tA              ->  A!=n\n *\t!A             ->  A=n\n *\tA && B         ->  !(A=n || B=n)\n *\tA || B         ->  !(A=n && B=n)\n *\tA && (B || C)  ->  !(A=n || (B=n && C=n))\n *\n * Allocates and returns a new expression.\n */\nstruct expr *expr_trans_compare(struct expr *e, enum expr_type type, struct symbol *sym)\n{\n\tstruct expr *e1, *e2;\n\n\tif (!e) {\n\t\te = expr_alloc_symbol(sym);\n\t\tif (type == E_UNEQUAL)\n\t\t\te = expr_alloc_one(E_NOT, e);\n\t\treturn e;\n\t}\n\tswitch (e->type) {\n\tcase E_AND:\n\t\te1 = expr_trans_compare(e->left.expr, E_EQUAL, sym);\n\t\te2 = expr_trans_compare(e->right.expr, E_EQUAL, sym);\n\t\tif (sym == &symbol_yes)\n\t\t\te = expr_alloc_two(E_AND, e1, e2);\n\t\tif (sym == &symbol_no)\n\t\t\te = expr_alloc_two(E_OR, e1, e2);\n\t\tif (type == E_UNEQUAL)\n\t\t\te = expr_alloc_one(E_NOT, e);\n\t\treturn e;\n\tcase E_OR:\n\t\te1 = expr_trans_compare(e->left.expr, E_EQUAL, sym);\n\t\te2 = expr_trans_compare(e->right.expr, E_EQUAL, sym);\n\t\tif (sym == &symbol_yes)\n\t\t\te = expr_alloc_two(E_OR, e1, e2);\n\t\tif (sym == &symbol_no)\n\t\t\te = expr_alloc_two(E_AND, e1, e2);\n\t\tif (type == E_UNEQUAL)\n\t\t\te = expr_alloc_one(E_NOT, e);\n\t\treturn e;\n\tcase E_NOT:\n\t\treturn expr_trans_compare(e->left.expr, type == E_EQUAL ? E_UNEQUAL : E_EQUAL, sym);\n\tcase E_UNEQUAL:\n\tcase E_LTH:\n\tcase E_LEQ:\n\tcase E_GTH:\n\tcase E_GEQ:\n\tcase E_EQUAL:\n\t\tif (type == E_EQUAL) {\n\t\t\tif (sym == &symbol_yes)\n\t\t\t\treturn expr_copy(e);\n\t\t\tif (sym == &symbol_mod)\n\t\t\t\treturn expr_alloc_symbol(&symbol_no);\n\t\t\tif (sym == &symbol_no)\n\t\t\t\treturn expr_alloc_one(E_NOT, expr_copy(e));\n\t\t} else {\n\t\t\tif (sym == &symbol_yes)\n\t\t\t\treturn expr_alloc_one(E_NOT, expr_copy(e));\n\t\t\tif (sym == &symbol_mod)\n\t\t\t\treturn expr_alloc_symbol(&symbol_yes);\n\t\t\tif (sym == &symbol_no)\n\t\t\t\treturn expr_copy(e);\n\t\t}\n\t\tbreak;\n\tcase E_SYMBOL:\n\t\treturn expr_alloc_comp(type, e->left.sym, sym);\n\tcase E_LIST:\n\tcase E_RANGE:\n\tcase E_NONE:\n\t\t/* panic */;\n\t}\n\treturn NULL;\n}\n\nenum string_value_kind {\n\tk_string,\n\tk_signed,\n\tk_unsigned,\n};\n\nunion string_value {\n\tunsigned long long u;\n\tsigned long long s;\n};\n\nstatic enum string_value_kind expr_parse_string(const char *str,\n\t\t\t\t\t\tenum symbol_type type,\n\t\t\t\t\t\tunion string_value *val)\n{\n\tchar *tail;\n\tenum string_value_kind kind;\n\n\terrno = 0;\n\tswitch (type) {\n\tcase S_BOOLEAN:\n\tcase S_TRISTATE:\n\t\tval->s = !strcmp(str, \"n\") ? 0 :\n\t\t\t !strcmp(str, \"m\") ? 1 :\n\t\t\t !strcmp(str, \"y\") ? 2 : -1;\n\t\treturn k_signed;\n\tcase S_INT:\n\t\tval->s = strtoll(str, &tail, 10);\n\t\tkind = k_signed;\n\t\tbreak;\n\tcase S_HEX:\n\t\tval->u = strtoull(str, &tail, 16);\n\t\tkind = k_unsigned;\n\t\tbreak;\n\tdefault:\n\t\tval->s = strtoll(str, &tail, 0);\n\t\tkind = k_signed;\n\t\tbreak;\n\t}\n\treturn !errno && !*tail && tail > str && isxdigit(tail[-1])\n\t       ? kind : k_string;\n}\n\ntristate expr_calc_value(struct expr *e)\n{\n\ttristate val1, val2;\n\tconst char *str1, *str2;\n\tenum string_value_kind k1 = k_string, k2 = k_string;\n\tunion string_value lval = {}, rval = {};\n\tint res;\n\n\tif (!e)\n\t\treturn yes;\n\n\tswitch (e->type) {\n\tcase E_SYMBOL:\n\t\tsym_calc_value(e->left.sym);\n\t\treturn e->left.sym->curr.tri;\n\tcase E_AND:\n\t\tval1 = expr_calc_value(e->left.expr);\n\t\tval2 = expr_calc_value(e->right.expr);\n\t\treturn EXPR_AND(val1, val2);\n\tcase E_OR:\n\t\tval1 = expr_calc_value(e->left.expr);\n\t\tval2 = expr_calc_value(e->right.expr);\n\t\treturn EXPR_OR(val1, val2);\n\tcase E_NOT:\n\t\tval1 = expr_calc_value(e->left.expr);\n\t\treturn EXPR_NOT(val1);\n\tcase E_EQUAL:\n\tcase E_GEQ:\n\tcase E_GTH:\n\tcase E_LEQ:\n\tcase E_LTH:\n\tcase E_UNEQUAL:\n\t\tbreak;\n\tdefault:\n\t\tprintf(\"expr_calc_value: %d?\\n\", e->type);\n\t\treturn no;\n\t}\n\n\tsym_calc_value(e->left.sym);\n\tsym_calc_value(e->right.sym);\n\tstr1 = sym_get_string_value(e->left.sym);\n\tstr2 = sym_get_string_value(e->right.sym);\n\n\tif (e->left.sym->type != S_STRING || e->right.sym->type != S_STRING) {\n\t\tk1 = expr_parse_string(str1, e->left.sym->type, &lval);\n\t\tk2 = expr_parse_string(str2, e->right.sym->type, &rval);\n\t}\n\n\tif (k1 == k_string || k2 == k_string)\n\t\tres = strcmp(str1, str2);\n\telse if (k1 == k_unsigned || k2 == k_unsigned)\n\t\tres = (lval.u > rval.u) - (lval.u < rval.u);\n\telse /* if (k1 == k_signed && k2 == k_signed) */\n\t\tres = (lval.s > rval.s) - (lval.s < rval.s);\n\n\tswitch(e->type) {\n\tcase E_EQUAL:\n\t\treturn res ? no : yes;\n\tcase E_GEQ:\n\t\treturn res >= 0 ? yes : no;\n\tcase E_GTH:\n\t\treturn res > 0 ? yes : no;\n\tcase E_LEQ:\n\t\treturn res <= 0 ? yes : no;\n\tcase E_LTH:\n\t\treturn res < 0 ? yes : no;\n\tcase E_UNEQUAL:\n\t\treturn res ? yes : no;\n\tdefault:\n\t\tprintf(\"expr_calc_value: relation %d?\\n\", e->type);\n\t\treturn no;\n\t}\n}\n\nstatic int expr_compare_type(enum expr_type t1, enum expr_type t2)\n{\n\tif (t1 == t2)\n\t\treturn 0;\n\tswitch (t1) {\n\tcase E_LEQ:\n\tcase E_LTH:\n\tcase E_GEQ:\n\tcase E_GTH:\n\t\tif (t2 == E_EQUAL || t2 == E_UNEQUAL)\n\t\t\treturn 1;\n\tcase E_EQUAL:\n\tcase E_UNEQUAL:\n\t\tif (t2 == E_NOT)\n\t\t\treturn 1;\n\tcase E_NOT:\n\t\tif (t2 == E_AND)\n\t\t\treturn 1;\n\tcase E_AND:\n\t\tif (t2 == E_OR)\n\t\t\treturn 1;\n\tcase E_OR:\n\t\tif (t2 == E_LIST)\n\t\t\treturn 1;\n\tcase E_LIST:\n\t\tif (t2 == 0)\n\t\t\treturn 1;\n\tdefault:\n\t\treturn -1;\n\t}\n\tprintf(\"[%dgt%d?]\", t1, t2);\n\treturn 0;\n}\n\nvoid expr_print(struct expr *e,\n\t\tvoid (*fn)(void *, struct symbol *, const char *),\n\t\tvoid *data, int prevtoken)\n{\n\tif (!e) {\n\t\tfn(data, NULL, \"y\");\n\t\treturn;\n\t}\n\n\tif (expr_compare_type(prevtoken, e->type) > 0)\n\t\tfn(data, NULL, \"(\");\n\tswitch (e->type) {\n\tcase E_SYMBOL:\n\t\tif (e->left.sym->name)\n\t\t\tfn(data, e->left.sym, e->left.sym->name);\n\t\telse\n\t\t\tfn(data, NULL, \"<choice>\");\n\t\tbreak;\n\tcase E_NOT:\n\t\tfn(data, NULL, \"!\");\n\t\texpr_print(e->left.expr, fn, data, E_NOT);\n\t\tbreak;\n\tcase E_EQUAL:\n\t\tif (e->left.sym->name)\n\t\t\tfn(data, e->left.sym, e->left.sym->name);\n\t\telse\n\t\t\tfn(data, NULL, \"<choice>\");\n\t\tfn(data, NULL, \"=\");\n\t\tfn(data, e->right.sym, e->right.sym->name);\n\t\tbreak;\n\tcase E_LEQ:\n\tcase E_LTH:\n\t\tif (e->left.sym->name)\n\t\t\tfn(data, e->left.sym, e->left.sym->name);\n\t\telse\n\t\t\tfn(data, NULL, \"<choice>\");\n\t\tfn(data, NULL, e->type == E_LEQ ? \"<=\" : \"<\");\n\t\tfn(data, e->right.sym, e->right.sym->name);\n\t\tbreak;\n\tcase E_GEQ:\n\tcase E_GTH:\n\t\tif (e->left.sym->name)\n\t\t\tfn(data, e->left.sym, e->left.sym->name);\n\t\telse\n\t\t\tfn(data, NULL, \"<choice>\");\n\t\tfn(data, NULL, e->type == E_GEQ ? \">=\" : \">\");\n\t\tfn(data, e->right.sym, e->right.sym->name);\n\t\tbreak;\n\tcase E_UNEQUAL:\n\t\tif (e->left.sym->name)\n\t\t\tfn(data, e->left.sym, e->left.sym->name);\n\t\telse\n\t\t\tfn(data, NULL, \"<choice>\");\n\t\tfn(data, NULL, \"!=\");\n\t\tfn(data, e->right.sym, e->right.sym->name);\n\t\tbreak;\n\tcase E_OR:\n\t\texpr_print(e->left.expr, fn, data, E_OR);\n\t\tfn(data, NULL, \" || \");\n\t\texpr_print(e->right.expr, fn, data, E_OR);\n\t\tbreak;\n\tcase E_AND:\n\t\texpr_print(e->left.expr, fn, data, E_AND);\n\t\tfn(data, NULL, \" && \");\n\t\texpr_print(e->right.expr, fn, data, E_AND);\n\t\tbreak;\n\tcase E_LIST:\n\t\tfn(data, e->right.sym, e->right.sym->name);\n\t\tif (e->left.expr) {\n\t\t\tfn(data, NULL, \" ^ \");\n\t\t\texpr_print(e->left.expr, fn, data, E_LIST);\n\t\t}\n\t\tbreak;\n\tcase E_RANGE:\n\t\tfn(data, NULL, \"[\");\n\t\tfn(data, e->left.sym, e->left.sym->name);\n\t\tfn(data, NULL, \" \");\n\t\tfn(data, e->right.sym, e->right.sym->name);\n\t\tfn(data, NULL, \"]\");\n\t\tbreak;\n\tdefault:\n\t  {\n\t\tchar buf[32];\n\t\tsprintf(buf, \"<unknown type %d>\", e->type);\n\t\tfn(data, NULL, buf);\n\t\tbreak;\n\t  }\n\t}\n\tif (expr_compare_type(prevtoken, e->type) > 0)\n\t\tfn(data, NULL, \")\");\n}\n\nstatic void expr_print_file_helper(void *data, struct symbol *sym, const char *str)\n{\n\txfwrite(str, strlen(str), 1, data);\n}\n\nvoid expr_fprint(struct expr *e, FILE *out)\n{\n\texpr_print(e, expr_print_file_helper, out, E_NONE);\n}\n\nstatic void expr_print_gstr_helper(void *data, struct symbol *sym, const char *str)\n{\n\tstruct gstr *gs = (struct gstr*)data;\n\tconst char *sym_str = NULL;\n\n\tif (sym)\n\t\tsym_str = sym_get_string_value(sym);\n\n\tif (gs->max_width) {\n\t\tunsigned extra_length = strlen(str);\n\t\tconst char *last_cr = strrchr(gs->s, '\\n');\n\t\tunsigned last_line_length;\n\n\t\tif (sym_str)\n\t\t\textra_length += 4 + strlen(sym_str);\n\n\t\tif (!last_cr)\n\t\t\tlast_cr = gs->s;\n\n\t\tlast_line_length = strlen(gs->s) - (last_cr - gs->s);\n\n\t\tif ((last_line_length + extra_length) > gs->max_width)\n\t\t\tstr_append(gs, \"\\\\\\n\");\n\t}\n\n\tstr_append(gs, str);\n\tif (sym && sym->type != S_UNKNOWN)\n\t\tstr_printf(gs, \" [=%s]\", sym_str);\n}\n\nvoid expr_gstr_print(struct expr *e, struct gstr *gs)\n{\n\texpr_print(e, expr_print_gstr_helper, gs, E_NONE);\n}\n\n/*\n * Transform the top level \"||\" tokens into newlines and prepend each\n * line with a minus. This makes expressions much easier to read.\n * Suitable for reverse dependency expressions.\n */\nstatic void expr_print_revdep(struct expr *e,\n\t\t\t      void (*fn)(void *, struct symbol *, const char *),\n\t\t\t      void *data, tristate pr_type, const char **title)\n{\n\tif (e->type == E_OR) {\n\t\texpr_print_revdep(e->left.expr, fn, data, pr_type, title);\n\t\texpr_print_revdep(e->right.expr, fn, data, pr_type, title);\n\t} else if (expr_calc_value(e) == pr_type) {\n\t\tif (*title) {\n\t\t\tfn(data, NULL, *title);\n\t\t\t*title = NULL;\n\t\t}\n\n\t\tfn(data, NULL, \"  - \");\n\t\texpr_print(e, fn, data, E_NONE);\n\t\tfn(data, NULL, \"\\n\");\n\t}\n}\n\nvoid expr_gstr_print_revdep(struct expr *e, struct gstr *gs,\n\t\t\t    tristate pr_type, const char *title)\n{\n\texpr_print_revdep(e, expr_print_gstr_helper, gs, pr_type, &title);\n}\n"
  },
  {
    "path": "scripts/config/expr.h",
    "content": "/* SPDX-License-Identifier: GPL-2.0-only */\n/*\n * Copyright (C) 2002 Roman Zippel <zippel@linux-m68k.org>\n */\n\n#ifndef EXPR_H\n#define EXPR_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#include <assert.h>\n#include <stdio.h>\n#include \"list.h\"\n#ifndef __cplusplus\n#include <stdbool.h>\n#endif\n\nstruct file {\n\tstruct file *next;\n\tstruct file *parent;\n\tconst char *name;\n\tint lineno;\n};\n\ntypedef enum tristate {\n\tno, mod, yes\n} tristate;\n\nenum expr_type {\n\tE_NONE, E_OR, E_AND, E_NOT,\n\tE_EQUAL, E_UNEQUAL, E_LTH, E_LEQ, E_GTH, E_GEQ,\n\tE_LIST, E_SYMBOL, E_RANGE\n};\n\nunion expr_data {\n\tstruct expr *expr;\n\tstruct symbol *sym;\n};\n\nstruct expr {\n\tenum expr_type type;\n\tunion expr_data left, right;\n};\n\n#define EXPR_OR(dep1, dep2)\t(((dep1)>(dep2))?(dep1):(dep2))\n#define EXPR_AND(dep1, dep2)\t(((dep1)<(dep2))?(dep1):(dep2))\n#define EXPR_NOT(dep)\t\t(2-(dep))\n\n#define expr_list_for_each_sym(l, e, s) \\\n\tfor (e = (l); e && (s = e->right.sym); e = e->left.expr)\n\nstruct expr_value {\n\tstruct expr *expr;\n\ttristate tri;\n};\n\nstruct symbol_value {\n\tvoid *val;\n\ttristate tri;\n};\n\nenum symbol_type {\n\tS_UNKNOWN, S_BOOLEAN, S_TRISTATE, S_INT, S_HEX, S_STRING\n};\n\n/* enum values are used as index to symbol.def[] */\nenum {\n\tS_DEF_USER,\t\t/* main user value */\n\tS_DEF_AUTO,\t\t/* values read from auto.conf */\n\tS_DEF_DEF3,\t\t/* Reserved for UI usage */\n\tS_DEF_DEF4,\t\t/* Reserved for UI usage */\n\tS_DEF_COUNT\n};\n\n/*\n * Represents a configuration symbol.\n *\n * Choices are represented as a special kind of symbol and have the\n * SYMBOL_CHOICE bit set in 'flags'.\n */\nstruct symbol {\n\t/* The next symbol in the same bucket in the symbol hash table */\n\tstruct symbol *next;\n\n\t/* The name of the symbol, e.g. \"FOO\" for 'config FOO' */\n\tchar *name;\n\n\t/* S_BOOLEAN, S_TRISTATE, ... */\n\tenum symbol_type type;\n\n\t/*\n\t * The calculated value of the symbol. The SYMBOL_VALID bit is set in\n\t * 'flags' when this is up to date. Note that this value might differ\n\t * from the user value set in e.g. a .config file, due to visibility.\n\t */\n\tstruct symbol_value curr;\n\n\t/*\n\t * Values for the symbol provided from outside. def[S_DEF_USER] holds\n\t * the .config value.\n\t */\n\tstruct symbol_value def[S_DEF_COUNT];\n\n\t/*\n\t * An upper bound on the tristate value the user can set for the symbol\n\t * if it is a boolean or tristate. Calculated from prompt dependencies,\n\t * which also inherit dependencies from enclosing menus, choices, and\n\t * ifs. If 'n', the user value will be ignored.\n\t *\n\t * Symbols lacking prompts always have visibility 'n'.\n\t */\n\ttristate visible;\n\n\t/* SYMBOL_* flags */\n\tint flags;\n\n\t/* List of properties. See prop_type. */\n\tstruct property *prop;\n\n\t/* Dependencies from enclosing menus, choices, and ifs */\n\tstruct expr_value dir_dep;\n\n\t/* Reverse dependencies through being selected by other symbols */\n\tstruct expr_value rev_dep;\n\n\t/*\n\t * \"Weak\" reverse dependencies through being implied by other symbols\n\t */\n\tstruct expr_value implied;\n};\n\n#define for_all_symbols(i, sym) for (i = 0; i < SYMBOL_HASHSIZE; i++) for (sym = symbol_hash[i]; sym; sym = sym->next)\n\n#define SYMBOL_CONST      0x0001  /* symbol is const */\n#define SYMBOL_CHECK      0x0008  /* used during dependency checking */\n#define SYMBOL_CHOICE     0x0010  /* start of a choice block (null name) */\n#define SYMBOL_CHOICEVAL  0x0020  /* used as a value in a choice block */\n#define SYMBOL_VALID      0x0080  /* set when symbol.curr is calculated */\n#define SYMBOL_OPTIONAL   0x0100  /* choice is optional - values can be 'n' */\n#define SYMBOL_WRITE      0x0200  /* write symbol to file (KCONFIG_CONFIG) */\n#define SYMBOL_CHANGED    0x0400  /* ? */\n#define SYMBOL_WRITTEN    0x0800  /* track info to avoid double-write to .config */\n#define SYMBOL_NO_WRITE   0x1000  /* Symbol for internal use only; it will not be written */\n#define SYMBOL_CHECKED    0x2000  /* used during dependency checking */\n#define SYMBOL_WARNED     0x8000  /* warning has been issued */\n\n/* Set when symbol.def[] is used */\n#define SYMBOL_DEF        0x10000  /* First bit of SYMBOL_DEF */\n#define SYMBOL_DEF_USER   0x10000  /* symbol.def[S_DEF_USER] is valid */\n#define SYMBOL_DEF_AUTO   0x20000  /* symbol.def[S_DEF_AUTO] is valid */\n#define SYMBOL_DEF3       0x40000  /* symbol.def[S_DEF_3] is valid */\n#define SYMBOL_DEF4       0x80000  /* symbol.def[S_DEF_4] is valid */\n\n/* choice values need to be set before calculating this symbol value */\n#define SYMBOL_NEED_SET_CHOICE_VALUES  0x100000\n\n#define SYMBOL_MAXLENGTH\t256\n#define SYMBOL_HASHSIZE\t\t9973\n\n/* A property represent the config options that can be associated\n * with a config \"symbol\".\n * Sample:\n * config FOO\n *         default y\n *         prompt \"foo prompt\"\n *         select BAR\n * config BAZ\n *         int \"BAZ Value\"\n *         range 1..255\n *\n * Please, also check parser.y:print_symbol() when modifying the\n * list of property types!\n */\nenum prop_type {\n\tP_UNKNOWN,\n\tP_PROMPT,   /* prompt \"foo prompt\" or \"BAZ Value\" */\n\tP_COMMENT,  /* text associated with a comment */\n\tP_MENU,     /* prompt associated with a menu or menuconfig symbol */\n\tP_DEFAULT,  /* default y */\n\tP_CHOICE,   /* choice value */\n\tP_SELECT,   /* select BAR */\n\tP_IMPLY,    /* imply BAR */\n\tP_RANGE,    /* range 7..100 (for a symbol) */\n\tP_SYMBOL,   /* where a symbol is defined */\n\tP_RESET,\t/* reset to defaults condition */\n};\n\nstruct property {\n\tstruct property *next;     /* next property - null if last */\n\tenum prop_type type;       /* type of property */\n\tconst char *text;          /* the prompt value - P_PROMPT, P_MENU, P_COMMENT */\n\tstruct expr_value visible;\n\tstruct expr *expr;         /* the optional conditional part of the property */\n\tstruct menu *menu;         /* the menu the property are associated with\n\t                            * valid for: P_SELECT, P_RANGE, P_CHOICE,\n\t                            * P_PROMPT, P_DEFAULT, P_MENU, P_COMMENT */\n\tstruct file *file;         /* what file was this property defined */\n\tint lineno;                /* what lineno was this property defined */\n};\n\n#define for_all_properties(sym, st, tok) \\\n\tfor (st = sym->prop; st; st = st->next) \\\n\t\tif (st->type == (tok))\n#define for_all_defaults(sym, st) for_all_properties(sym, st, P_DEFAULT)\n#define for_all_choices(sym, st) for_all_properties(sym, st, P_CHOICE)\n#define for_all_prompts(sym, st) \\\n\tfor (st = sym->prop; st; st = st->next) \\\n\t\tif (st->text)\n\n/*\n * Represents a node in the menu tree, as seen in e.g. menuconfig (though used\n * for all front ends). Each symbol, menu, etc. defined in the Kconfig files\n * gets a node. A symbol defined in multiple locations gets one node at each\n * location.\n */\nstruct menu {\n\t/* The next menu node at the same level */\n\tstruct menu *next;\n\n\t/* The parent menu node, corresponding to e.g. a menu or choice */\n\tstruct menu *parent;\n\n\t/* The first child menu node, for e.g. menus and choices */\n\tstruct menu *list;\n\n\t/*\n\t * The symbol associated with the menu node. Choices are implemented as\n\t * a special kind of symbol. NULL for menus, comments, and ifs.\n\t */\n\tstruct symbol *sym;\n\n\t/*\n\t * The prompt associated with the node. This holds the prompt for a\n\t * symbol as well as the text for a menu or comment, along with the\n\t * type (P_PROMPT, P_MENU, etc.)\n\t */\n\tstruct property *prompt;\n\n\t/*\n\t * 'visible if' dependencies. If more than one is given, they will be\n\t * ANDed together.\n\t */\n\tstruct expr *visibility;\n\n\t/*\n\t * Ordinary dependencies from e.g. 'depends on' and 'if', ANDed\n\t * together\n\t */\n\tstruct expr *dep;\n\n\t/* MENU_* flags */\n\tunsigned int flags;\n\n\t/* Any help text associated with the node */\n\tchar *help;\n\n\t/* The location where the menu node appears in the Kconfig files */\n\tstruct file *file;\n\tint lineno;\n\n\t/* For use by front ends that need to store auxiliary data */\n\tvoid *data;\n};\n\n/*\n * Set on a menu node when the corresponding symbol changes state in some way.\n * Can be checked by front ends.\n */\n#define MENU_CHANGED\t\t0x0001\n\n#define MENU_ROOT\t\t0x0002\n\nstruct jump_key {\n\tstruct list_head entries;\n\tsize_t offset;\n\tstruct menu *target;\n\tint index;\n};\n\nextern struct file *file_list;\nextern struct file *current_file;\nstruct file *lookup_file(const char *name);\n\nextern struct symbol symbol_yes, symbol_no, symbol_mod;\nextern struct symbol *modules_sym;\nextern int cdebug;\nstruct expr *expr_alloc_symbol(struct symbol *sym);\nstruct expr *expr_alloc_one(enum expr_type type, struct expr *ce);\nstruct expr *expr_alloc_two(enum expr_type type, struct expr *e1, struct expr *e2);\nstruct expr *expr_alloc_comp(enum expr_type type, struct symbol *s1, struct symbol *s2);\nstruct expr *expr_alloc_and(struct expr *e1, struct expr *e2);\nstruct expr *expr_alloc_or(struct expr *e1, struct expr *e2);\nstruct expr *expr_copy(const struct expr *org);\nvoid expr_free(struct expr *e);\nvoid expr_eliminate_eq(struct expr **ep1, struct expr **ep2);\nint expr_eq(struct expr *e1, struct expr *e2);\ntristate expr_calc_value(struct expr *e);\nstruct expr *expr_trans_bool(struct expr *e);\nstruct expr *expr_eliminate_dups(struct expr *e);\nstruct expr *expr_transform(struct expr *e);\nint expr_contains_symbol(struct expr *dep, struct symbol *sym);\nbool expr_depends_symbol(struct expr *dep, struct symbol *sym);\nstruct expr *expr_trans_compare(struct expr *e, enum expr_type type, struct symbol *sym);\n\nvoid expr_fprint(struct expr *e, FILE *out);\nstruct gstr; /* forward */\nvoid expr_gstr_print(struct expr *e, struct gstr *gs);\nvoid expr_gstr_print_revdep(struct expr *e, struct gstr *gs,\n\t\t\t    tristate pr_type, const char *title);\n\nstatic inline int expr_is_yes(struct expr *e)\n{\n\treturn !e || (e->type == E_SYMBOL && e->left.sym == &symbol_yes);\n}\n\nstatic inline int expr_is_no(struct expr *e)\n{\n\treturn e && (e->type == E_SYMBOL && e->left.sym == &symbol_no);\n}\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* EXPR_H */\n"
  },
  {
    "path": "scripts/config/images.c",
    "content": "// SPDX-License-Identifier: GPL-2.0-only\n/*\n * Copyright (C) 2002 Roman Zippel <zippel@linux-m68k.org>\n */\n\n#include \"images.h\"\n\nconst char * const xpm_load[] = {\n\"22 22 5 1\",\n\". c None\",\n\"# c #000000\",\n\"c c #838100\",\n\"a c #ffff00\",\n\"b c #ffffff\",\n\"......................\",\n\"......................\",\n\"......................\",\n\"............####....#.\",\n\"...........#....##.##.\",\n\"..................###.\",\n\".................####.\",\n\".####...........#####.\",\n\"#abab##########.......\",\n\"#babababababab#.......\",\n\"#ababababababa#.......\",\n\"#babababababab#.......\",\n\"#ababab###############\",\n\"#babab##cccccccccccc##\",\n\"#abab##cccccccccccc##.\",\n\"#bab##cccccccccccc##..\",\n\"#ab##cccccccccccc##...\",\n\"#b##cccccccccccc##....\",\n\"###cccccccccccc##.....\",\n\"##cccccccccccc##......\",\n\"###############.......\",\n\"......................\"};\n\nconst char * const xpm_save[] = {\n\"22 22 5 1\",\n\". c None\",\n\"# c #000000\",\n\"a c #838100\",\n\"b c #c5c2c5\",\n\"c c #cdb6d5\",\n\"......................\",\n\".####################.\",\n\".#aa#bbbbbbbbbbbb#bb#.\",\n\".#aa#bbbbbbbbbbbb#bb#.\",\n\".#aa#bbbbbbbbbcbb####.\",\n\".#aa#bbbccbbbbbbb#aa#.\",\n\".#aa#bbbccbbbbbbb#aa#.\",\n\".#aa#bbbbbbbbbbbb#aa#.\",\n\".#aa#bbbbbbbbbbbb#aa#.\",\n\".#aa#bbbbbbbbbbbb#aa#.\",\n\".#aa#bbbbbbbbbbbb#aa#.\",\n\".#aaa############aaa#.\",\n\".#aaaaaaaaaaaaaaaaaa#.\",\n\".#aaaaaaaaaaaaaaaaaa#.\",\n\".#aaa#############aa#.\",\n\".#aaa#########bbb#aa#.\",\n\".#aaa#########bbb#aa#.\",\n\".#aaa#########bbb#aa#.\",\n\".#aaa#########bbb#aa#.\",\n\".#aaa#########bbb#aa#.\",\n\"..##################..\",\n\"......................\"};\n\nconst char * const xpm_back[] = {\n\"22 22 3 1\",\n\". c None\",\n\"# c #000083\",\n\"a c #838183\",\n\"......................\",\n\"......................\",\n\"......................\",\n\"......................\",\n\"......................\",\n\"...........######a....\",\n\"..#......##########...\",\n\"..##...####......##a..\",\n\"..###.###.........##..\",\n\"..######..........##..\",\n\"..#####...........##..\",\n\"..######..........##..\",\n\"..#######.........##..\",\n\"..########.......##a..\",\n\"...............a###...\",\n\"...............###....\",\n\"......................\",\n\"......................\",\n\"......................\",\n\"......................\",\n\"......................\",\n\"......................\"};\n\nconst char * const xpm_tree_view[] = {\n\"22 22 2 1\",\n\". c None\",\n\"# c #000000\",\n\"......................\",\n\"......................\",\n\"......#...............\",\n\"......#...............\",\n\"......#...............\",\n\"......#...............\",\n\"......#...............\",\n\"......########........\",\n\"......#...............\",\n\"......#...............\",\n\"......#...............\",\n\"......#...............\",\n\"......#...............\",\n\"......########........\",\n\"......#...............\",\n\"......#...............\",\n\"......#...............\",\n\"......#...............\",\n\"......#...............\",\n\"......########........\",\n\"......................\",\n\"......................\"};\n\nconst char * const xpm_single_view[] = {\n\"22 22 2 1\",\n\". c None\",\n\"# c #000000\",\n\"......................\",\n\"......................\",\n\"..........#...........\",\n\"..........#...........\",\n\"..........#...........\",\n\"..........#...........\",\n\"..........#...........\",\n\"..........#...........\",\n\"..........#...........\",\n\"..........#...........\",\n\"..........#...........\",\n\"..........#...........\",\n\"..........#...........\",\n\"..........#...........\",\n\"..........#...........\",\n\"..........#...........\",\n\"..........#...........\",\n\"..........#...........\",\n\"..........#...........\",\n\"..........#...........\",\n\"......................\",\n\"......................\"};\n\nconst char * const xpm_split_view[] = {\n\"22 22 2 1\",\n\". c None\",\n\"# c #000000\",\n\"......................\",\n\"......................\",\n\"......#......#........\",\n\"......#......#........\",\n\"......#......#........\",\n\"......#......#........\",\n\"......#......#........\",\n\"......#......#........\",\n\"......#......#........\",\n\"......#......#........\",\n\"......#......#........\",\n\"......#......#........\",\n\"......#......#........\",\n\"......#......#........\",\n\"......#......#........\",\n\"......#......#........\",\n\"......#......#........\",\n\"......#......#........\",\n\"......#......#........\",\n\"......#......#........\",\n\"......................\",\n\"......................\"};\n\nconst char * const xpm_symbol_no[] = {\n\"12 12 2 1\",\n\"  c white\",\n\". c black\",\n\"            \",\n\" .......... \",\n\" .        . \",\n\" .        . \",\n\" .        . \",\n\" .        . \",\n\" .        . \",\n\" .        . \",\n\" .        . \",\n\" .        . \",\n\" .......... \",\n\"            \"};\n\nconst char * const xpm_symbol_mod[] = {\n\"12 12 2 1\",\n\"  c white\",\n\". c black\",\n\"            \",\n\" .......... \",\n\" .        . \",\n\" .        . \",\n\" .   ..   . \",\n\" .  ....  . \",\n\" .  ....  . \",\n\" .   ..   . \",\n\" .        . \",\n\" .        . \",\n\" .......... \",\n\"            \"};\n\nconst char * const xpm_symbol_yes[] = {\n\"12 12 2 1\",\n\"  c white\",\n\". c black\",\n\"            \",\n\" .......... \",\n\" .        . \",\n\" .        . \",\n\" .      . . \",\n\" .     .. . \",\n\" . .  ..  . \",\n\" . ....   . \",\n\" .  ..    . \",\n\" .        . \",\n\" .......... \",\n\"            \"};\n\nconst char * const xpm_choice_no[] = {\n\"12 12 2 1\",\n\"  c white\",\n\". c black\",\n\"            \",\n\"    ....    \",\n\"  ..    ..  \",\n\"  .      .  \",\n\" .        . \",\n\" .        . \",\n\" .        . \",\n\" .        . \",\n\"  .      .  \",\n\"  ..    ..  \",\n\"    ....    \",\n\"            \"};\n\nconst char * const xpm_choice_yes[] = {\n\"12 12 2 1\",\n\"  c white\",\n\". c black\",\n\"            \",\n\"    ....    \",\n\"  ..    ..  \",\n\"  .      .  \",\n\" .   ..   . \",\n\" .  ....  . \",\n\" .  ....  . \",\n\" .   ..   . \",\n\"  .      .  \",\n\"  ..    ..  \",\n\"    ....    \",\n\"            \"};\n\nconst char * const xpm_menu[] = {\n\"12 12 2 1\",\n\"  c white\",\n\". c black\",\n\"            \",\n\" .......... \",\n\" .        . \",\n\" . ..     . \",\n\" . ....   . \",\n\" . ...... . \",\n\" . ...... . \",\n\" . ....   . \",\n\" . ..     . \",\n\" .        . \",\n\" .......... \",\n\"            \"};\n\nconst char * const xpm_menu_inv[] = {\n\"12 12 2 1\",\n\"  c white\",\n\". c black\",\n\"            \",\n\" .......... \",\n\" .......... \",\n\" ..  ...... \",\n\" ..    .... \",\n\" ..      .. \",\n\" ..      .. \",\n\" ..    .... \",\n\" ..  ...... \",\n\" .......... \",\n\" .......... \",\n\"            \"};\n\nconst char * const xpm_menuback[] = {\n\"12 12 2 1\",\n\"  c white\",\n\". c black\",\n\"            \",\n\" .......... \",\n\" .        . \",\n\" .     .. . \",\n\" .   .... . \",\n\" . ...... . \",\n\" . ...... . \",\n\" .   .... . \",\n\" .     .. . \",\n\" .        . \",\n\" .......... \",\n\"            \"};\n\nconst char * const xpm_void[] = {\n\"12 12 2 1\",\n\"  c white\",\n\". c black\",\n\"            \",\n\"            \",\n\"            \",\n\"            \",\n\"            \",\n\"            \",\n\"            \",\n\"            \",\n\"            \",\n\"            \",\n\"            \",\n\"            \"};\n"
  },
  {
    "path": "scripts/config/images.h",
    "content": "/* SPDX-License-Identifier: GPL-2.0-only */\n/*\n * Copyright (C) 2002 Roman Zippel <zippel@linux-m68k.org>\n */\n\n#ifndef IMAGES_H\n#define IMAGES_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\nextern const char * const xpm_load[];\nextern const char * const xpm_save[];\nextern const char * const xpm_back[];\nextern const char * const xpm_tree_view[];\nextern const char * const xpm_single_view[];\nextern const char * const xpm_split_view[];\nextern const char * const xpm_symbol_no[];\nextern const char * const xpm_symbol_mod[];\nextern const char * const xpm_symbol_yes[];\nextern const char * const xpm_choice_no[];\nextern const char * const xpm_choice_yes[];\nextern const char * const xpm_menu[];\nextern const char * const xpm_menu_inv[];\nextern const char * const xpm_menuback[];\nextern const char * const xpm_void[];\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* IMAGES_H */\n"
  },
  {
    "path": "scripts/config/internal.h",
    "content": "/* SPDX-License-Identifier: GPL-2.0-only */\n#ifndef INTERNAL_H\n#define INTERNAL_H\n\nstruct menu;\n\nextern struct menu *current_menu, *current_entry;\n\n#endif /* INTERNAL_H */\n"
  },
  {
    "path": "scripts/config/lexer.l",
    "content": "/* SPDX-License-Identifier: GPL-2.0-only */\n/*\n * Copyright (C) 2002 Roman Zippel <zippel@linux-m68k.org>\n */\n%option nostdinit noyywrap never-interactive full ecs\n%option 8bit nodefault yylineno\n%x ASSIGN_VAL HELP STRING\n%{\n\n#include <assert.h>\n#include <limits.h>\n#include <stdio.h>\n#include <stdlib.h>\n#include <string.h>\n#include <glob.h>\n#include <libgen.h>\n\n#include \"lkc.h\"\n#include \"parser.tab.h\"\n\n#define YY_DECL\t\tstatic int yylex1(void)\n\n#define START_STRSIZE\t16\n\nstatic struct {\n\tstruct file *file;\n\tint lineno;\n} current_pos;\n\nstatic int prev_prev_token = T_EOL;\nstatic int prev_token = T_EOL;\nstatic char *text;\nstatic int text_size, text_asize;\n\nstruct buffer {\n\tstruct buffer *parent;\n\tYY_BUFFER_STATE state;\n};\n\nstatic struct buffer *current_buf;\n\nstatic int last_ts, first_ts;\n\nstatic char *expand_token(const char *in, size_t n);\nstatic void append_expanded_string(const char *in);\nstatic void zconf_endhelp(void);\nstatic void zconf_endfile(void);\n\nstatic void new_string(void)\n{\n\ttext = xmalloc(START_STRSIZE);\n\ttext_asize = START_STRSIZE;\n\ttext_size = 0;\n\t*text = 0;\n}\n\nstatic void append_string(const char *str, int size)\n{\n\tint new_size = text_size + size + 1;\n\tif (new_size > text_asize) {\n\t\tnew_size += START_STRSIZE - 1;\n\t\tnew_size &= -START_STRSIZE;\n\t\ttext = xrealloc(text, new_size);\n\t\ttext_asize = new_size;\n\t}\n\tmemcpy(text + text_size, str, size);\n\ttext_size += size;\n\ttext[text_size] = 0;\n}\n\nstatic void alloc_string(const char *str, int size)\n{\n\ttext = xmalloc(size + 1);\n\tmemcpy(text, str, size);\n\ttext[size] = 0;\n}\n\nstatic void warn_ignored_character(char chr)\n{\n\tfprintf(stderr,\n\t        \"%s:%d:warning: ignoring unsupported character '%c'\\n\",\n\t        current_file->name, yylineno, chr);\n}\n%}\n\nn\t[A-Za-z0-9_-]\n\n%%\n\tint str = 0;\n\tint ts, i;\n\n#.*\t\t\t/* ignore comment */\n[ \\t]*\t\t\t/* whitespaces */\n\\\\\\n\t\t\t/* escaped new line */\n\\n\t\t\treturn T_EOL;\n\"bool\"\t\t\treturn T_BOOL;\n\"choice\"\t\treturn T_CHOICE;\n\"comment\"\t\treturn T_COMMENT;\n\"config\"\t\treturn T_CONFIG;\n\"def_bool\"\t\treturn T_DEF_BOOL;\n\"def_tristate\"\t\treturn T_DEF_TRISTATE;\n\"default\"\t\treturn T_DEFAULT;\n\"depends\"\t\treturn T_DEPENDS;\n\"endchoice\"\t\treturn T_ENDCHOICE;\n\"endif\"\t\t\treturn T_ENDIF;\n\"endmenu\"\t\treturn T_ENDMENU;\n\"help\"\t\t\treturn T_HELP;\n\"hex\"\t\t\treturn T_HEX;\n\"if\"\t\t\treturn T_IF;\n\"imply\"\t\t\treturn T_IMPLY;\n\"int\"\t\t\treturn T_INT;\n\"mainmenu\"\t\treturn T_MAINMENU;\n\"menu\"\t\t\treturn T_MENU;\n\"menuconfig\"\t\treturn T_MENUCONFIG;\n\"modules\"\t\treturn T_MODULES;\n\"on\"\t\t\treturn T_ON;\n\"optional\"\t\treturn T_OPTIONAL;\n\"prompt\"\t\treturn T_PROMPT;\n\"range\"\t\t\treturn T_RANGE;\n\"reset\"\t\t\treturn T_RESET;\n\"select\"\t\treturn T_SELECT;\n\"source\"\t\treturn T_SOURCE;\n\"string\"\t\treturn T_STRING;\n\"tristate\"\t\treturn T_TRISTATE;\n\"visible\"\t\treturn T_VISIBLE;\n\"||\"\t\t\treturn T_OR;\n\"&&\"\t\t\treturn T_AND;\n\"=\"\t\t\treturn T_EQUAL;\n\"!=\"\t\t\treturn T_UNEQUAL;\n\"<\"\t\t\treturn T_LESS;\n\"<=\"\t\t\treturn T_LESS_EQUAL;\n\">\"\t\t\treturn T_GREATER;\n\">=\"\t\t\treturn T_GREATER_EQUAL;\n\"!\"\t\t\treturn T_NOT;\n\"(\"\t\t\treturn T_OPEN_PAREN;\n\")\"\t\t\treturn T_CLOSE_PAREN;\n\":=\"\t\t\treturn T_COLON_EQUAL;\n\"+=\"\t\t\treturn T_PLUS_EQUAL;\n\\\"|\\'\t\t\t{\n\t\t\t\tstr = yytext[0];\n\t\t\t\tnew_string();\n\t\t\t\tBEGIN(STRING);\n\t\t\t}\n({n}|[/.])+\t\t{\n\t\t\t\talloc_string(yytext, yyleng);\n\t\t\t\tyylval.string = text;\n\t\t\t\treturn T_WORD;\n\t\t\t}\n({n}|[/.$])+\t\t{\n\t\t\t\t/* this token includes at least one '$' */\n\t\t\t\tyylval.string = expand_token(yytext, yyleng);\n\t\t\t\tif (strlen(yylval.string))\n\t\t\t\t\treturn T_WORD;\n\t\t\t\tfree(yylval.string);\n\t\t\t}\n.\t\t\twarn_ignored_character(*yytext);\n\n<ASSIGN_VAL>{\n\t[^[:blank:]\\n]+.*\t{\n\t\talloc_string(yytext, yyleng);\n\t\tyylval.string = text;\n\t\treturn T_ASSIGN_VAL;\n\t}\n\t\\n\t{ BEGIN(INITIAL); return T_EOL; }\n\t.\n}\n\n<STRING>{\n\t\"$\".*\tappend_expanded_string(yytext);\n\t[^$'\"\\\\\\n]+\t{\n\t\tappend_string(yytext, yyleng);\n\t}\n\t\\\\.?\t{\n\t\tappend_string(yytext + 1, yyleng - 1);\n\t}\n\t\\'|\\\"\t{\n\t\tif (str == yytext[0]) {\n\t\t\tBEGIN(INITIAL);\n\t\t\tyylval.string = text;\n\t\t\treturn T_WORD_QUOTE;\n\t\t} else\n\t\t\tappend_string(yytext, 1);\n\t}\n\t\\n\t{\n\t\tfprintf(stderr,\n\t\t\t\"%s:%d:warning: multi-line strings not supported\\n\",\n\t\t\tzconf_curname(), zconf_lineno());\n\t\tunput('\\n');\n\t\tBEGIN(INITIAL);\n\t\tyylval.string = text;\n\t\treturn T_WORD_QUOTE;\n\t}\n\t<<EOF>>\t{\n\t\tBEGIN(INITIAL);\n\t\tyylval.string = text;\n\t\treturn T_WORD_QUOTE;\n\t}\n}\n\n<HELP>{\n\t[ \\t]+\t{\n\t\tts = 0;\n\t\tfor (i = 0; i < yyleng; i++) {\n\t\t\tif (yytext[i] == '\\t')\n\t\t\t\tts = (ts & ~7) + 8;\n\t\t\telse\n\t\t\t\tts++;\n\t\t}\n\t\tlast_ts = ts;\n\t\tif (first_ts) {\n\t\t\tif (ts < first_ts) {\n\t\t\t\tzconf_endhelp();\n\t\t\t\treturn T_HELPTEXT;\n\t\t\t}\n\t\t\tts -= first_ts;\n\t\t\twhile (ts > 8) {\n\t\t\t\tappend_string(\"        \", 8);\n\t\t\t\tts -= 8;\n\t\t\t}\n\t\t\tappend_string(\"        \", ts);\n\t\t}\n\t}\n\t[ \\t]*\\n/[^ \\t\\n] {\n\t\tzconf_endhelp();\n\t\treturn T_HELPTEXT;\n\t}\n\t[ \\t]*\\n\t{\n\t\tappend_string(\"\\n\", 1);\n\t}\n\t[^ \\t\\n].* {\n\t\twhile (yyleng) {\n\t\t\tif ((yytext[yyleng-1] != ' ') && (yytext[yyleng-1] != '\\t'))\n\t\t\t\tbreak;\n\t\t\tyyleng--;\n\t\t}\n\t\tappend_string(yytext, yyleng);\n\t\tif (!first_ts)\n\t\t\tfirst_ts = last_ts;\n\t}\n\t<<EOF>>\t{\n\t\tzconf_endhelp();\n\t\treturn T_HELPTEXT;\n\t}\n}\n\n<<EOF>>\t{\n\tBEGIN(INITIAL);\n\n\tif (prev_token != T_EOL && prev_token != T_HELPTEXT)\n\t\tfprintf(stderr, \"%s:%d:warning: no new line at end of file\\n\",\n\t\t\tcurrent_file->name, yylineno);\n\n\tif (current_file) {\n\t\tzconf_endfile();\n\t\treturn T_EOL;\n\t}\n\tfclose(yyin);\n\tyyterminate();\n}\n\n%%\n\n/* second stage lexer */\nint yylex(void)\n{\n\tint token;\n\nrepeat:\n\ttoken = yylex1();\n\n\tif (prev_token == T_EOL || prev_token == T_HELPTEXT) {\n\t\tif (token == T_EOL) {\n\t\t\t/* Do not pass unneeded T_EOL to the parser. */\n\t\t\tgoto repeat;\n\t\t} else {\n\t\t\t/*\n\t\t\t * For the parser, update file/lineno at the first token\n\t\t\t * of each statement. Generally, \\n is a statement\n\t\t\t * terminator in Kconfig, but it is not always true\n\t\t\t * because \\n could be escaped by a backslash.\n\t\t\t */\n\t\t\tcurrent_pos.file = current_file;\n\t\t\tcurrent_pos.lineno = yylineno;\n\t\t}\n\t}\n\n\tif (prev_prev_token == T_EOL && prev_token == T_WORD &&\n\t    (token == T_EQUAL || token == T_COLON_EQUAL || token == T_PLUS_EQUAL))\n\t\tBEGIN(ASSIGN_VAL);\n\n\tprev_prev_token = prev_token;\n\tprev_token = token;\n\n\treturn token;\n}\n\nstatic char *expand_token(const char *in, size_t n)\n{\n\tchar *out;\n\tint c;\n\tchar c2;\n\tconst char *rest, *end;\n\n\tnew_string();\n\tappend_string(in, n);\n\n\t/* get the whole line because we do not know the end of token. */\n\twhile ((c = input()) != EOF) {\n\t\tif (c == '\\n') {\n\t\t\tunput(c);\n\t\t\tbreak;\n\t\t}\n\t\tc2 = c;\n\t\tappend_string(&c2, 1);\n\t}\n\n\trest = text;\n\tout = expand_one_token(&rest);\n\n\t/* push back unused characters to the input stream */\n\tend = rest + strlen(rest);\n\twhile (end > rest)\n\t\tunput(*--end);\n\n\tfree(text);\n\n\treturn out;\n}\n\nstatic void append_expanded_string(const char *str)\n{\n\tconst char *end;\n\tchar *res;\n\n\tstr++;\n\n\tres = expand_dollar(&str);\n\n\t/* push back unused characters to the input stream */\n\tend = str + strlen(str);\n\twhile (end > str)\n\t\tunput(*--end);\n\n\tappend_string(res, strlen(res));\n\n\tfree(res);\n}\n\nvoid zconf_starthelp(void)\n{\n\tnew_string();\n\tlast_ts = first_ts = 0;\n\tBEGIN(HELP);\n}\n\nstatic void zconf_endhelp(void)\n{\n\tyylval.string = text;\n\tBEGIN(INITIAL);\n}\n\n\n/*\n * Try to open specified file with following names:\n * ./name\n * $(srctree)/name\n * The latter is used when srctree is separate from objtree\n * when compiling the kernel.\n * Return NULL if file is not found.\n */\nFILE *zconf_fopen(const char *name)\n{\n\tchar *env, fullname[PATH_MAX+1];\n\tFILE *f;\n\n\tf = fopen(name, \"r\");\n\tif (!f && name != NULL && name[0] != '/') {\n\t\tenv = getenv(SRCTREE);\n\t\tif (env) {\n\t\t\tsnprintf(fullname, sizeof(fullname),\n\t\t\t\t \"%s/%s\", env, name);\n\t\t\tf = fopen(fullname, \"r\");\n\t\t}\n\t}\n\treturn f;\n}\n\nvoid zconf_initscan(const char *name)\n{\n\tyyin = zconf_fopen(name);\n\tif (!yyin) {\n\t\tfprintf(stderr, \"can't find file %s\\n\", name);\n\t\texit(1);\n\t}\n\n\tcurrent_buf = xmalloc(sizeof(*current_buf));\n\tmemset(current_buf, 0, sizeof(*current_buf));\n\n\tcurrent_file = file_lookup(name);\n\tyylineno = 1;\n}\n\nstatic void __zconf_nextfile(const char *name)\n{\n\tstruct file *iter;\n\tstruct file *file = file_lookup(name);\n\tstruct buffer *buf = xmalloc(sizeof(*buf));\n\tmemset(buf, 0, sizeof(*buf));\n\n\tcurrent_buf->state = YY_CURRENT_BUFFER;\n\tyyin = zconf_fopen(file->name);\n\tif (!yyin) {\n\t\tfprintf(stderr, \"%s:%d: can't open file \\\"%s\\\"\\n\",\n\t\t\tzconf_curname(), zconf_lineno(), file->name);\n\t\texit(1);\n\t}\n\tyy_switch_to_buffer(yy_create_buffer(yyin, YY_BUF_SIZE));\n\tbuf->parent = current_buf;\n\tcurrent_buf = buf;\n\n\tcurrent_file->lineno = yylineno;\n\tfile->parent = current_file;\n\n\tfor (iter = current_file; iter; iter = iter->parent) {\n\t\tif (!strcmp(iter->name, file->name)) {\n\t\t\tfprintf(stderr,\n\t\t\t\t\"Recursive inclusion detected.\\n\"\n\t\t\t\t\"Inclusion path:\\n\"\n\t\t\t\t\"  current file : %s\\n\", file->name);\n\t\t\titer = file;\n\t\t\tdo {\n\t\t\t\titer = iter->parent;\n\t\t\t\tfprintf(stderr, \"  included from: %s:%d\\n\",\n\t\t\t\t\titer->name, iter->lineno - 1);\n\t\t\t} while (strcmp(iter->name, file->name));\n\t\t\texit(1);\n\t\t}\n\t}\n\n\tyylineno = 1;\n\tcurrent_file = file;\n}\n\nvoid zconf_nextfile(const char *name)\n{\n\tglob_t gl;\n\tint err;\n\tint i;\n\tchar path[PATH_MAX], *p;\n\n\terr = glob(name, GLOB_ERR | GLOB_MARK, NULL, &gl);\n\n\t/* ignore wildcard patterns that return no result */\n\tif (err == GLOB_NOMATCH && strchr(name, '*')) {\n\t\terr = 0;\n\t\tgl.gl_pathc = 0;\n\t}\n\n\tif (err == GLOB_NOMATCH) {\n\t\tp = strdup(current_file->name);\n\t\tif (p) {\n\t\t\tsnprintf(path, sizeof(path), \"%s/%s\", dirname(p), name);\n\t\t\terr = glob(path, GLOB_ERR | GLOB_MARK, NULL, &gl);\n\t\t\tfree(p);\n\t\t}\n\t}\n\n\tif (err) {\n\t\tconst char *reason = \"unknown error\";\n\n\t\tswitch (err) {\n\t\tcase GLOB_NOSPACE:\n\t\t\treason = \"out of memory\";\n\t\t\tbreak;\n\t\tcase GLOB_ABORTED:\n\t\t\treason = \"read error\";\n\t\t\tbreak;\n\t\tcase GLOB_NOMATCH:\n\t\t\treason = \"No files found\";\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tbreak;\n\t\t}\n\n\t\tprintf(\"%s:%d: glob failed: %s \\\"%s\\\"\\n\", zconf_curname(), zconf_lineno(),\n\t\t\treason, name);\n\n\t\texit(1);\n\t}\n\n\tfor (i = 0; i < gl.gl_pathc; i++)\n\t\t__zconf_nextfile(gl.gl_pathv[i]);\n}\n\nstatic void zconf_endfile(void)\n{\n\tstruct buffer *parent;\n\n\tcurrent_file = current_file->parent;\n\tif (current_file)\n\t\tyylineno = current_file->lineno;\n\n\tparent = current_buf->parent;\n\tif (parent) {\n\t\tfclose(yyin);\n\t\tyy_delete_buffer(YY_CURRENT_BUFFER);\n\t\tyy_switch_to_buffer(parent->state);\n\t}\n\tfree(current_buf);\n\tcurrent_buf = parent;\n}\n\nint zconf_lineno(void)\n{\n\treturn current_pos.lineno;\n}\n\nconst char *zconf_curname(void)\n{\n\treturn current_pos.file ? current_pos.file->name : \"<none>\";\n}\n"
  },
  {
    "path": "scripts/config/lexer.lex.c",
    "content": "\n#define  YY_INT_ALIGNED short int\n\n/* A lexical scanner generated by flex */\n\n#define FLEX_SCANNER\n#define YY_FLEX_MAJOR_VERSION 2\n#define YY_FLEX_MINOR_VERSION 6\n#define YY_FLEX_SUBMINOR_VERSION 4\n#if YY_FLEX_SUBMINOR_VERSION > 0\n#define FLEX_BETA\n#endif\n\n/* First, we deal with  platform-specific or compiler-specific issues. */\n\n/* begin standard C headers. */\n#include <stdio.h>\n#include <string.h>\n#include <errno.h>\n#include <stdlib.h>\n\n/* end standard C headers. */\n\n/* flex integer type definitions */\n\n#ifndef FLEXINT_H\n#define FLEXINT_H\n\n/* C99 systems have <inttypes.h>. Non-C99 systems may or may not. */\n\n#if defined (__STDC_VERSION__) && __STDC_VERSION__ >= 199901L\n\n/* C99 says to define __STDC_LIMIT_MACROS before including stdint.h,\n * if you want the limit (max/min) macros for int types. \n */\n#ifndef __STDC_LIMIT_MACROS\n#define __STDC_LIMIT_MACROS 1\n#endif\n\n#include <inttypes.h>\ntypedef int8_t flex_int8_t;\ntypedef uint8_t flex_uint8_t;\ntypedef int16_t flex_int16_t;\ntypedef uint16_t flex_uint16_t;\ntypedef int32_t flex_int32_t;\ntypedef uint32_t flex_uint32_t;\n#else\ntypedef signed char flex_int8_t;\ntypedef short int flex_int16_t;\ntypedef int flex_int32_t;\ntypedef unsigned char flex_uint8_t; \ntypedef unsigned short int flex_uint16_t;\ntypedef unsigned int flex_uint32_t;\n\n/* Limits of integral types. */\n#ifndef INT8_MIN\n#define INT8_MIN               (-128)\n#endif\n#ifndef INT16_MIN\n#define INT16_MIN              (-32767-1)\n#endif\n#ifndef INT32_MIN\n#define INT32_MIN              (-2147483647-1)\n#endif\n#ifndef INT8_MAX\n#define INT8_MAX               (127)\n#endif\n#ifndef INT16_MAX\n#define INT16_MAX              (32767)\n#endif\n#ifndef INT32_MAX\n#define INT32_MAX              (2147483647)\n#endif\n#ifndef UINT8_MAX\n#define UINT8_MAX              (255U)\n#endif\n#ifndef UINT16_MAX\n#define UINT16_MAX             (65535U)\n#endif\n#ifndef UINT32_MAX\n#define UINT32_MAX             (4294967295U)\n#endif\n\n#ifndef SIZE_MAX\n#define SIZE_MAX               (~(size_t)0)\n#endif\n\n#endif /* ! C99 */\n\n#endif /* ! FLEXINT_H */\n\n/* begin standard C++ headers. */\n\n/* TODO: this is always defined, so inline it */\n#define yyconst const\n\n#if defined(__GNUC__) && __GNUC__ >= 3\n#define yynoreturn __attribute__((__noreturn__))\n#else\n#define yynoreturn\n#endif\n\n/* Returned upon end-of-file. */\n#define YY_NULL 0\n\n/* Promotes a possibly negative, possibly signed char to an\n *   integer in range [0..255] for use as an array index.\n */\n#define YY_SC_TO_UI(c) ((YY_CHAR) (c))\n\n/* Enter a start condition.  This macro really ought to take a parameter,\n * but we do it the disgusting crufty way forced on us by the ()-less\n * definition of BEGIN.\n */\n#define BEGIN (yy_start) = 1 + 2 *\n/* Translate the current start state into a value that can be later handed\n * to BEGIN to return to the state.  The YYSTATE alias is for lex\n * compatibility.\n */\n#define YY_START (((yy_start) - 1) / 2)\n#define YYSTATE YY_START\n/* Action number for EOF rule of a given start state. */\n#define YY_STATE_EOF(state) (YY_END_OF_BUFFER + state + 1)\n/* Special action meaning \"start processing a new file\". */\n#define YY_NEW_FILE yyrestart( yyin  )\n#define YY_END_OF_BUFFER_CHAR 0\n\n/* Size of default input buffer. */\n#ifndef YY_BUF_SIZE\n#ifdef __ia64__\n/* On IA-64, the buffer size is 16k, not 8k.\n * Moreover, YY_BUF_SIZE is 2*YY_READ_BUF_SIZE in the general case.\n * Ditto for the __ia64__ case accordingly.\n */\n#define YY_BUF_SIZE 32768\n#else\n#define YY_BUF_SIZE 16384\n#endif /* __ia64__ */\n#endif\n\n/* The state buf must be large enough to hold one state per character in the main buffer.\n */\n#define YY_STATE_BUF_SIZE   ((YY_BUF_SIZE + 2) * sizeof(yy_state_type))\n\n#ifndef YY_TYPEDEF_YY_BUFFER_STATE\n#define YY_TYPEDEF_YY_BUFFER_STATE\ntypedef struct yy_buffer_state *YY_BUFFER_STATE;\n#endif\n\n#ifndef YY_TYPEDEF_YY_SIZE_T\n#define YY_TYPEDEF_YY_SIZE_T\ntypedef size_t yy_size_t;\n#endif\n\nextern int yyleng;\n\nextern FILE *yyin, *yyout;\n\n#define EOB_ACT_CONTINUE_SCAN 0\n#define EOB_ACT_END_OF_FILE 1\n#define EOB_ACT_LAST_MATCH 2\n    \n    /* Note: We specifically omit the test for yy_rule_can_match_eol because it requires\n     *       access to the local variable yy_act. Since yyless() is a macro, it would break\n     *       existing scanners that call yyless() from OUTSIDE yylex.\n     *       One obvious solution it to make yy_act a global. I tried that, and saw\n     *       a 5% performance hit in a non-yylineno scanner, because yy_act is\n     *       normally declared as a register variable-- so it is not worth it.\n     */\n    #define  YY_LESS_LINENO(n) \\\n            do { \\\n                int yyl;\\\n                for ( yyl = n; yyl < yyleng; ++yyl )\\\n                    if ( yytext[yyl] == '\\n' )\\\n                        --yylineno;\\\n            }while(0)\n    #define YY_LINENO_REWIND_TO(dst) \\\n            do {\\\n                const char *p;\\\n                for ( p = yy_cp-1; p >= (dst); --p)\\\n                    if ( *p == '\\n' )\\\n                        --yylineno;\\\n            }while(0)\n    \n/* Return all but the first \"n\" matched characters back to the input stream. */\n#define yyless(n) \\\n\tdo \\\n\t\t{ \\\n\t\t/* Undo effects of setting up yytext. */ \\\n        int yyless_macro_arg = (n); \\\n        YY_LESS_LINENO(yyless_macro_arg);\\\n\t\t*yy_cp = (yy_hold_char); \\\n\t\tYY_RESTORE_YY_MORE_OFFSET \\\n\t\t(yy_c_buf_p) = yy_cp = yy_bp + yyless_macro_arg - YY_MORE_ADJ; \\\n\t\tYY_DO_BEFORE_ACTION; /* set up yytext again */ \\\n\t\t} \\\n\twhile ( 0 )\n#define unput(c) yyunput( c, (yytext_ptr)  )\n\n#ifndef YY_STRUCT_YY_BUFFER_STATE\n#define YY_STRUCT_YY_BUFFER_STATE\nstruct yy_buffer_state\n\t{\n\tFILE *yy_input_file;\n\n\tchar *yy_ch_buf;\t\t/* input buffer */\n\tchar *yy_buf_pos;\t\t/* current position in input buffer */\n\n\t/* Size of input buffer in bytes, not including room for EOB\n\t * characters.\n\t */\n\tint yy_buf_size;\n\n\t/* Number of characters read into yy_ch_buf, not including EOB\n\t * characters.\n\t */\n\tint yy_n_chars;\n\n\t/* Whether we \"own\" the buffer - i.e., we know we created it,\n\t * and can realloc() it to grow it, and should free() it to\n\t * delete it.\n\t */\n\tint yy_is_our_buffer;\n\n\t/* Whether this is an \"interactive\" input source; if so, and\n\t * if we're using stdio for input, then we want to use getc()\n\t * instead of fread(), to make sure we stop fetching input after\n\t * each newline.\n\t */\n\tint yy_is_interactive;\n\n\t/* Whether we're considered to be at the beginning of a line.\n\t * If so, '^' rules will be active on the next match, otherwise\n\t * not.\n\t */\n\tint yy_at_bol;\n\n    int yy_bs_lineno; /**< The line count. */\n    int yy_bs_column; /**< The column count. */\n\n\t/* Whether to try to fill the input buffer when we reach the\n\t * end of it.\n\t */\n\tint yy_fill_buffer;\n\n\tint yy_buffer_status;\n\n#define YY_BUFFER_NEW 0\n#define YY_BUFFER_NORMAL 1\n\t/* When an EOF's been seen but there's still some text to process\n\t * then we mark the buffer as YY_EOF_PENDING, to indicate that we\n\t * shouldn't try reading from the input source any more.  We might\n\t * still have a bunch of tokens to match, though, because of\n\t * possible backing-up.\n\t *\n\t * When we actually see the EOF, we change the status to \"new\"\n\t * (via yyrestart()), so that the user can continue scanning by\n\t * just pointing yyin at a new input file.\n\t */\n#define YY_BUFFER_EOF_PENDING 2\n\n\t};\n#endif /* !YY_STRUCT_YY_BUFFER_STATE */\n\n/* Stack of input buffers. */\nstatic size_t yy_buffer_stack_top = 0; /**< index of top of stack. */\nstatic size_t yy_buffer_stack_max = 0; /**< capacity of stack. */\nstatic YY_BUFFER_STATE * yy_buffer_stack = NULL; /**< Stack as an array. */\n\n/* We provide macros for accessing buffer states in case in the\n * future we want to put the buffer states in a more general\n * \"scanner state\".\n *\n * Returns the top of the stack, or NULL.\n */\n#define YY_CURRENT_BUFFER ( (yy_buffer_stack) \\\n                          ? (yy_buffer_stack)[(yy_buffer_stack_top)] \\\n                          : NULL)\n/* Same as previous macro, but useful when we know that the buffer stack is not\n * NULL or when we need an lvalue. For internal use only.\n */\n#define YY_CURRENT_BUFFER_LVALUE (yy_buffer_stack)[(yy_buffer_stack_top)]\n\n/* yy_hold_char holds the character lost when yytext is formed. */\nstatic char yy_hold_char;\nstatic int yy_n_chars;\t\t/* number of characters read into yy_ch_buf */\nint yyleng;\n\n/* Points to current character in buffer. */\nstatic char *yy_c_buf_p = NULL;\nstatic int yy_init = 0;\t\t/* whether we need to initialize */\nstatic int yy_start = 0;\t/* start state number */\n\n/* Flag which is used to allow yywrap()'s to do buffer switches\n * instead of setting up a fresh yyin.  A bit of a hack ...\n */\nstatic int yy_did_buffer_switch_on_eof;\n\nvoid yyrestart ( FILE *input_file  );\nvoid yy_switch_to_buffer ( YY_BUFFER_STATE new_buffer  );\nYY_BUFFER_STATE yy_create_buffer ( FILE *file, int size  );\nvoid yy_delete_buffer ( YY_BUFFER_STATE b  );\nvoid yy_flush_buffer ( YY_BUFFER_STATE b  );\nvoid yypush_buffer_state ( YY_BUFFER_STATE new_buffer  );\nvoid yypop_buffer_state ( void );\n\nstatic void yyensure_buffer_stack ( void );\nstatic void yy_load_buffer_state ( void );\nstatic void yy_init_buffer ( YY_BUFFER_STATE b, FILE *file  );\n#define YY_FLUSH_BUFFER yy_flush_buffer( YY_CURRENT_BUFFER )\n\nYY_BUFFER_STATE yy_scan_buffer ( char *base, yy_size_t size  );\nYY_BUFFER_STATE yy_scan_string ( const char *yy_str  );\nYY_BUFFER_STATE yy_scan_bytes ( const char *bytes, int len  );\n\nvoid *yyalloc ( yy_size_t  );\nvoid *yyrealloc ( void *, yy_size_t  );\nvoid yyfree ( void *  );\n\n#define yy_new_buffer yy_create_buffer\n#define yy_set_interactive(is_interactive) \\\n\t{ \\\n\tif ( ! YY_CURRENT_BUFFER ){ \\\n        yyensure_buffer_stack (); \\\n\t\tYY_CURRENT_BUFFER_LVALUE =    \\\n            yy_create_buffer( yyin, YY_BUF_SIZE ); \\\n\t} \\\n\tYY_CURRENT_BUFFER_LVALUE->yy_is_interactive = is_interactive; \\\n\t}\n#define yy_set_bol(at_bol) \\\n\t{ \\\n\tif ( ! YY_CURRENT_BUFFER ){\\\n        yyensure_buffer_stack (); \\\n\t\tYY_CURRENT_BUFFER_LVALUE =    \\\n            yy_create_buffer( yyin, YY_BUF_SIZE ); \\\n\t} \\\n\tYY_CURRENT_BUFFER_LVALUE->yy_at_bol = at_bol; \\\n\t}\n#define YY_AT_BOL() (YY_CURRENT_BUFFER_LVALUE->yy_at_bol)\n\n/* Begin user sect3 */\n\n#define yywrap() (/*CONSTCOND*/1)\n#define YY_SKIP_YYWRAP\ntypedef flex_uint8_t YY_CHAR;\n\nFILE *yyin = NULL, *yyout = NULL;\n\ntypedef int yy_state_type;\n\nextern int yylineno;\nint yylineno = 1;\n\nextern char *yytext;\n#ifdef yytext_ptr\n#undef yytext_ptr\n#endif\n#define yytext_ptr yytext\n\nstatic const flex_int16_t yy_nxt[][43] =\n    {\n    {\n        0,    0,    0,    0,    0,    0,    0,    0,    0,    0,\n        0,    0,    0,    0,    0,    0,    0,    0,    0,    0,\n        0,    0,    0,    0,    0,    0,    0,    0,    0,    0,\n        0,    0,    0,    0,    0,    0,    0,    0,    0,    0,\n        0,    0,    0\n    },\n\n    {\n        9,   10,   11,   12,   13,   14,   15,   16,   17,   14,\n       18,   19,   20,   21,   21,   22,   23,   24,   25,   26,\n       21,   21,   27,   28,   29,   30,   21,   21,   31,   32,\n       21,   33,   21,   34,   35,   36,   37,   38,   21,   39,\n       21,   21,   40\n\n    },\n\n    {\n        9,   10,   11,   12,   13,   14,   15,   16,   17,   14,\n       18,   19,   20,   21,   21,   22,   23,   24,   25,   26,\n       21,   21,   27,   28,   29,   30,   21,   21,   31,   32,\n       21,   33,   21,   34,   35,   36,   37,   38,   21,   39,\n       21,   21,   40\n    },\n\n    {\n        9,   41,   42,   43,   41,   41,   41,   41,   41,   41,\n       41,   41,   41,   41,   41,   41,   41,   41,   41,   41,\n       41,   41,   41,   41,   41,   41,   41,   41,   41,   41,\n       41,   41,   41,   41,   41,   41,   41,   41,   41,   41,\n       41,   41,   41\n\n    },\n\n    {\n        9,   41,   42,   43,   41,   41,   41,   41,   41,   41,\n       41,   41,   41,   41,   41,   41,   41,   41,   41,   41,\n       41,   41,   41,   41,   41,   41,   41,   41,   41,   41,\n       41,   41,   41,   41,   41,   41,   41,   41,   41,   41,\n       41,   41,   41\n    },\n\n    {\n        9,   44,   45,   46,   44,   44,   44,   44,   44,   44,\n       44,   44,   44,   44,   44,   44,   44,   44,   44,   44,\n       44,   44,   44,   44,   44,   44,   44,   44,   44,   44,\n       44,   44,   44,   44,   44,   44,   44,   44,   44,   44,\n       44,   44,   44\n\n    },\n\n    {\n        9,   44,   45,   46,   44,   44,   44,   44,   44,   44,\n       44,   44,   44,   44,   44,   44,   44,   44,   44,   44,\n       44,   44,   44,   44,   44,   44,   44,   44,   44,   44,\n       44,   44,   44,   44,   44,   44,   44,   44,   44,   44,\n       44,   44,   44\n    },\n\n    {\n        9,   47,   47,   48,   47,   49,   47,   50,   47,   49,\n       47,   47,   47,   47,   47,   47,   47,   47,   47,   51,\n       47,   47,   47,   47,   47,   47,   47,   47,   47,   47,\n       47,   47,   47,   47,   47,   47,   47,   47,   47,   47,\n       47,   47,   47\n\n    },\n\n    {\n        9,   47,   47,   48,   47,   49,   47,   50,   47,   49,\n       47,   47,   47,   47,   47,   47,   47,   47,   47,   51,\n       47,   47,   47,   47,   47,   47,   47,   47,   47,   47,\n       47,   47,   47,   47,   47,   47,   47,   47,   47,   47,\n       47,   47,   47\n    },\n\n    {\n       -9,   -9,   -9,   -9,   -9,   -9,   -9,   -9,   -9,   -9,\n       -9,   -9,   -9,   -9,   -9,   -9,   -9,   -9,   -9,   -9,\n       -9,   -9,   -9,   -9,   -9,   -9,   -9,   -9,   -9,   -9,\n       -9,   -9,   -9,   -9,   -9,   -9,   -9,   -9,   -9,   -9,\n       -9,   -9,   -9\n\n    },\n\n    {\n        9,  -10,  -10,  -10,  -10,  -10,  -10,  -10,  -10,  -10,\n      -10,  -10,  -10,  -10,  -10,  -10,  -10,  -10,  -10,  -10,\n      -10,  -10,  -10,  -10,  -10,  -10,  -10,  -10,  -10,  -10,\n      -10,  -10,  -10,  -10,  -10,  -10,  -10,  -10,  -10,  -10,\n      -10,  -10,  -10\n    },\n\n    {\n        9,  -11,   52,  -11,  -11,  -11,  -11,  -11,  -11,  -11,\n      -11,  -11,  -11,  -11,  -11,  -11,  -11,  -11,  -11,  -11,\n      -11,  -11,  -11,  -11,  -11,  -11,  -11,  -11,  -11,  -11,\n      -11,  -11,  -11,  -11,  -11,  -11,  -11,  -11,  -11,  -11,\n      -11,  -11,  -11\n\n    },\n\n    {\n        9,  -12,  -12,  -12,  -12,  -12,  -12,  -12,  -12,  -12,\n      -12,  -12,  -12,  -12,  -12,  -12,  -12,  -12,  -12,  -12,\n      -12,  -12,  -12,  -12,  -12,  -12,  -12,  -12,  -12,  -12,\n      -12,  -12,  -12,  -12,  -12,  -12,  -12,  -12,  -12,  -12,\n      -12,  -12,  -12\n    },\n\n    {\n        9,  -13,  -13,  -13,  -13,  -13,  -13,  -13,  -13,  -13,\n      -13,  -13,  -13,  -13,  -13,  -13,  -13,   53,  -13,  -13,\n      -13,  -13,  -13,  -13,  -13,  -13,  -13,  -13,  -13,  -13,\n      -13,  -13,  -13,  -13,  -13,  -13,  -13,  -13,  -13,  -13,\n      -13,  -13,  -13\n\n    },\n\n    {\n        9,  -14,  -14,  -14,  -14,  -14,  -14,  -14,  -14,  -14,\n      -14,  -14,  -14,  -14,  -14,  -14,  -14,  -14,  -14,  -14,\n      -14,  -14,  -14,  -14,  -14,  -14,  -14,  -14,  -14,  -14,\n      -14,  -14,  -14,  -14,  -14,  -14,  -14,  -14,  -14,  -14,\n      -14,  -14,  -14\n    },\n\n    {\n        9,   54,   54,  -15,   54,   54,   54,   54,   54,   54,\n       54,   54,   54,   54,   54,   54,   54,   54,   54,   54,\n       54,   54,   54,   54,   54,   54,   54,   54,   54,   54,\n       54,   54,   54,   54,   54,   54,   54,   54,   54,   54,\n       54,   54,   54\n\n    },\n\n    {\n        9,  -16,  -16,  -16,  -16,  -16,  -16,   55,  -16,  -16,\n      -16,  -16,  -16,   55,   55,  -16,  -16,  -16,  -16,  -16,\n       55,   55,   55,   55,   55,   55,   55,   55,   55,   55,\n       55,   55,   55,   55,   55,   55,   55,   55,   55,   55,\n       55,   55,  -16\n    },\n\n    {\n        9,  -17,  -17,  -17,  -17,  -17,  -17,  -17,   56,  -17,\n      -17,  -17,  -17,  -17,  -17,  -17,  -17,  -17,  -17,  -17,\n      -17,  -17,  -17,  -17,  -17,  -17,  -17,  -17,  -17,  -17,\n      -17,  -17,  -17,  -17,  -17,  -17,  -17,  -17,  -17,  -17,\n      -17,  -17,  -17\n\n    },\n\n    {\n        9,  -18,  -18,  -18,  -18,  -18,  -18,  -18,  -18,  -18,\n      -18,  -18,  -18,  -18,  -18,  -18,  -18,  -18,  -18,  -18,\n      -18,  -18,  -18,  -18,  -18,  -18,  -18,  -18,  -18,  -18,\n      -18,  -18,  -18,  -18,  -18,  -18,  -18,  -18,  -18,  -18,\n      -18,  -18,  -18\n    },\n\n    {\n        9,  -19,  -19,  -19,  -19,  -19,  -19,  -19,  -19,  -19,\n      -19,  -19,  -19,  -19,  -19,  -19,  -19,  -19,  -19,  -19,\n      -19,  -19,  -19,  -19,  -19,  -19,  -19,  -19,  -19,  -19,\n      -19,  -19,  -19,  -19,  -19,  -19,  -19,  -19,  -19,  -19,\n      -19,  -19,  -19\n\n    },\n\n    {\n        9,  -20,  -20,  -20,  -20,  -20,  -20,  -20,  -20,  -20,\n      -20,  -20,  -20,  -20,  -20,  -20,  -20,   57,  -20,  -20,\n      -20,  -20,  -20,  -20,  -20,  -20,  -20,  -20,  -20,  -20,\n      -20,  -20,  -20,  -20,  -20,  -20,  -20,  -20,  -20,  -20,\n      -20,  -20,  -20\n    },\n\n    {\n        9,  -21,  -21,  -21,  -21,  -21,  -21,   55,  -21,  -21,\n      -21,  -21,  -21,   58,   58,  -21,  -21,  -21,  -21,  -21,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58,  -21\n\n    },\n\n    {\n        9,  -22,  -22,  -22,  -22,  -22,  -22,  -22,  -22,  -22,\n      -22,  -22,  -22,  -22,  -22,  -22,  -22,   59,  -22,  -22,\n      -22,  -22,  -22,  -22,  -22,  -22,  -22,  -22,  -22,  -22,\n      -22,  -22,  -22,  -22,  -22,  -22,  -22,  -22,  -22,  -22,\n      -22,  -22,  -22\n    },\n\n    {\n        9,  -23,  -23,  -23,  -23,  -23,  -23,  -23,  -23,  -23,\n      -23,  -23,  -23,  -23,  -23,  -23,  -23,   60,  -23,  -23,\n      -23,  -23,  -23,  -23,  -23,  -23,  -23,  -23,  -23,  -23,\n      -23,  -23,  -23,  -23,  -23,  -23,  -23,  -23,  -23,  -23,\n      -23,  -23,  -23\n\n    },\n\n    {\n        9,  -24,  -24,  -24,  -24,  -24,  -24,  -24,  -24,  -24,\n      -24,  -24,  -24,  -24,  -24,  -24,  -24,  -24,  -24,  -24,\n      -24,  -24,  -24,  -24,  -24,  -24,  -24,  -24,  -24,  -24,\n      -24,  -24,  -24,  -24,  -24,  -24,  -24,  -24,  -24,  -24,\n      -24,  -24,  -24\n    },\n\n    {\n        9,  -25,  -25,  -25,  -25,  -25,  -25,  -25,  -25,  -25,\n      -25,  -25,  -25,  -25,  -25,  -25,  -25,   61,  -25,  -25,\n      -25,  -25,  -25,  -25,  -25,  -25,  -25,  -25,  -25,  -25,\n      -25,  -25,  -25,  -25,  -25,  -25,  -25,  -25,  -25,  -25,\n      -25,  -25,  -25\n\n    },\n\n    {\n        9,  -26,  -26,   62,  -26,  -26,  -26,  -26,  -26,  -26,\n      -26,  -26,  -26,  -26,  -26,  -26,  -26,  -26,  -26,  -26,\n      -26,  -26,  -26,  -26,  -26,  -26,  -26,  -26,  -26,  -26,\n      -26,  -26,  -26,  -26,  -26,  -26,  -26,  -26,  -26,  -26,\n      -26,  -26,  -26\n    },\n\n    {\n        9,  -27,  -27,  -27,  -27,  -27,  -27,   55,  -27,  -27,\n      -27,  -27,  -27,   58,   58,  -27,  -27,  -27,  -27,  -27,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58,   58,   63,   58,   58,   58,   58,   58,   58,\n       58,   58,  -27\n\n    },\n\n    {\n        9,  -28,  -28,  -28,  -28,  -28,  -28,   55,  -28,  -28,\n      -28,  -28,  -28,   58,   58,  -28,  -28,  -28,  -28,  -28,\n       58,   58,   58,   58,   58,   58,   58,   58,   64,   58,\n       58,   58,   58,   65,   58,   58,   58,   58,   58,   58,\n       58,   58,  -28\n    },\n\n    {\n        9,  -29,  -29,  -29,  -29,  -29,  -29,   55,  -29,  -29,\n      -29,  -29,  -29,   58,   58,  -29,  -29,  -29,  -29,  -29,\n       58,   58,   58,   58,   58,   66,   58,   58,   58,   58,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58,  -29\n\n    },\n\n    {\n        9,  -30,  -30,  -30,  -30,  -30,  -30,   55,  -30,  -30,\n      -30,  -30,  -30,   58,   58,  -30,  -30,  -30,  -30,  -30,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58,   67,   58,   58,   58,   58,   58,   58,   58,\n       58,   58,  -30\n    },\n\n    {\n        9,  -31,  -31,  -31,  -31,  -31,  -31,   55,  -31,  -31,\n      -31,  -31,  -31,   58,   58,  -31,  -31,  -31,  -31,  -31,\n       58,   58,   58,   58,   58,   68,   58,   58,   58,   58,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58,  -31\n\n    },\n\n    {\n        9,  -32,  -32,  -32,  -32,  -32,  -32,   55,  -32,  -32,\n      -32,  -32,  -32,   58,   58,  -32,  -32,  -32,  -32,  -32,\n       58,   58,   58,   58,   58,   58,   69,   58,   58,   58,\n       58,   70,   71,   58,   58,   58,   58,   58,   58,   58,\n       58,   58,  -32\n    },\n\n    {\n        9,  -33,  -33,  -33,  -33,  -33,  -33,   55,  -33,  -33,\n      -33,  -33,  -33,   58,   58,  -33,  -33,  -33,  -33,  -33,\n       58,   72,   58,   58,   58,   73,   58,   58,   58,   58,\n       58,   58,   58,   74,   58,   58,   58,   58,   58,   58,\n       58,   58,  -33\n\n    },\n\n    {\n        9,  -34,  -34,  -34,  -34,  -34,  -34,   55,  -34,  -34,\n      -34,  -34,  -34,   58,   58,  -34,  -34,  -34,  -34,  -34,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58,   75,   58,   76,   58,   58,   58,   58,   58,\n       58,   58,  -34\n    },\n\n    {\n        9,  -35,  -35,  -35,  -35,  -35,  -35,   55,  -35,  -35,\n      -35,  -35,  -35,   58,   58,  -35,  -35,  -35,  -35,  -35,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58,   58,   58,   58,   77,   58,   58,   58,   58,\n       58,   58,  -35\n\n    },\n\n    {\n        9,  -36,  -36,  -36,  -36,  -36,  -36,   55,  -36,  -36,\n      -36,  -36,  -36,   58,   58,  -36,  -36,  -36,  -36,  -36,\n       58,   78,   58,   58,   58,   79,   58,   58,   58,   58,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58,  -36\n    },\n\n    {\n        9,  -37,  -37,  -37,  -37,  -37,  -37,   55,  -37,  -37,\n      -37,  -37,  -37,   58,   58,  -37,  -37,  -37,  -37,  -37,\n       58,   58,   58,   58,   58,   80,   58,   58,   58,   58,\n       58,   58,   58,   81,   58,   58,   58,   82,   58,   58,\n       58,   58,  -37\n\n    },\n\n    {\n        9,  -38,  -38,  -38,  -38,  -38,  -38,   55,  -38,  -38,\n      -38,  -38,  -38,   58,   58,  -38,  -38,  -38,  -38,  -38,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58,   58,   58,   58,   83,   58,   58,   58,   58,\n       58,   58,  -38\n    },\n\n    {\n        9,  -39,  -39,  -39,  -39,  -39,  -39,   55,  -39,  -39,\n      -39,  -39,  -39,   58,   58,  -39,  -39,  -39,  -39,  -39,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   84,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58,  -39\n\n    },\n\n    {\n        9,  -40,  -40,  -40,  -40,  -40,  -40,  -40,  -40,  -40,\n      -40,  -40,  -40,  -40,  -40,  -40,  -40,  -40,  -40,  -40,\n      -40,  -40,  -40,  -40,  -40,  -40,  -40,  -40,  -40,  -40,\n      -40,  -40,  -40,  -40,  -40,  -40,  -40,  -40,  -40,  -40,\n      -40,  -40,   85\n    },\n\n    {\n        9,   86,   87,  -41,   86,   86,   86,   86,   86,   86,\n       86,   86,   86,   86,   86,   86,   86,   86,   86,   86,\n       86,   86,   86,   86,   86,   86,   86,   86,   86,   86,\n       86,   86,   86,   86,   86,   86,   86,   86,   86,   86,\n       86,   86,   86\n\n    },\n\n    {\n        9,  -42,  -42,  -42,  -42,  -42,  -42,  -42,  -42,  -42,\n      -42,  -42,  -42,  -42,  -42,  -42,  -42,  -42,  -42,  -42,\n      -42,  -42,  -42,  -42,  -42,  -42,  -42,  -42,  -42,  -42,\n      -42,  -42,  -42,  -42,  -42,  -42,  -42,  -42,  -42,  -42,\n      -42,  -42,  -42\n    },\n\n    {\n        9,  -43,  -43,  -43,  -43,  -43,  -43,  -43,  -43,  -43,\n      -43,  -43,  -43,  -43,  -43,  -43,  -43,  -43,  -43,  -43,\n      -43,  -43,  -43,  -43,  -43,  -43,  -43,  -43,  -43,  -43,\n      -43,  -43,  -43,  -43,  -43,  -43,  -43,  -43,  -43,  -43,\n      -43,  -43,  -43\n\n    },\n\n    {\n        9,   88,   88,  -44,   88,   88,   88,   88,   88,   88,\n       88,   88,   88,   88,   88,   88,   88,   88,   88,   88,\n       88,   88,   88,   88,   88,   88,   88,   88,   88,   88,\n       88,   88,   88,   88,   88,   88,   88,   88,   88,   88,\n       88,   88,   88\n    },\n\n    {\n        9,  -45,   89,   90,  -45,  -45,  -45,  -45,  -45,  -45,\n      -45,  -45,  -45,  -45,  -45,  -45,  -45,  -45,  -45,  -45,\n      -45,  -45,  -45,  -45,  -45,  -45,  -45,  -45,  -45,  -45,\n      -45,  -45,  -45,  -45,  -45,  -45,  -45,  -45,  -45,  -45,\n      -45,  -45,  -45\n\n    },\n\n    {\n        9,   91,  -46,  -46,   91,   91,   91,   91,   91,   91,\n       91,   91,   91,   91,   91,   91,   91,   91,   91,   91,\n       91,   91,   91,   91,   91,   91,   91,   91,   91,   91,\n       91,   91,   91,   91,   91,   91,   91,   91,   91,   91,\n       91,   91,   91\n    },\n\n    {\n        9,   92,   92,  -47,   92,  -47,   92,  -47,   92,  -47,\n       92,   92,   92,   92,   92,   92,   92,   92,   92,  -47,\n       92,   92,   92,   92,   92,   92,   92,   92,   92,   92,\n       92,   92,   92,   92,   92,   92,   92,   92,   92,   92,\n       92,   92,   92\n\n    },\n\n    {\n        9,  -48,  -48,  -48,  -48,  -48,  -48,  -48,  -48,  -48,\n      -48,  -48,  -48,  -48,  -48,  -48,  -48,  -48,  -48,  -48,\n      -48,  -48,  -48,  -48,  -48,  -48,  -48,  -48,  -48,  -48,\n      -48,  -48,  -48,  -48,  -48,  -48,  -48,  -48,  -48,  -48,\n      -48,  -48,  -48\n    },\n\n    {\n        9,  -49,  -49,  -49,  -49,  -49,  -49,  -49,  -49,  -49,\n      -49,  -49,  -49,  -49,  -49,  -49,  -49,  -49,  -49,  -49,\n      -49,  -49,  -49,  -49,  -49,  -49,  -49,  -49,  -49,  -49,\n      -49,  -49,  -49,  -49,  -49,  -49,  -49,  -49,  -49,  -49,\n      -49,  -49,  -49\n\n    },\n\n    {\n        9,   93,   93,  -50,   93,   93,   93,   93,   93,   93,\n       93,   93,   93,   93,   93,   93,   93,   93,   93,   93,\n       93,   93,   93,   93,   93,   93,   93,   93,   93,   93,\n       93,   93,   93,   93,   93,   93,   93,   93,   93,   93,\n       93,   93,   93\n    },\n\n    {\n        9,   94,   94,  -51,   94,   94,   94,   94,   94,   94,\n       94,   94,   94,   94,   94,   94,   94,   94,   94,   94,\n       94,   94,   94,   94,   94,   94,   94,   94,   94,   94,\n       94,   94,   94,   94,   94,   94,   94,   94,   94,   94,\n       94,   94,   94\n\n    },\n\n    {\n        9,  -52,   52,  -52,  -52,  -52,  -52,  -52,  -52,  -52,\n      -52,  -52,  -52,  -52,  -52,  -52,  -52,  -52,  -52,  -52,\n      -52,  -52,  -52,  -52,  -52,  -52,  -52,  -52,  -52,  -52,\n      -52,  -52,  -52,  -52,  -52,  -52,  -52,  -52,  -52,  -52,\n      -52,  -52,  -52\n    },\n\n    {\n        9,  -53,  -53,  -53,  -53,  -53,  -53,  -53,  -53,  -53,\n      -53,  -53,  -53,  -53,  -53,  -53,  -53,  -53,  -53,  -53,\n      -53,  -53,  -53,  -53,  -53,  -53,  -53,  -53,  -53,  -53,\n      -53,  -53,  -53,  -53,  -53,  -53,  -53,  -53,  -53,  -53,\n      -53,  -53,  -53\n\n    },\n\n    {\n        9,   54,   54,  -54,   54,   54,   54,   54,   54,   54,\n       54,   54,   54,   54,   54,   54,   54,   54,   54,   54,\n       54,   54,   54,   54,   54,   54,   54,   54,   54,   54,\n       54,   54,   54,   54,   54,   54,   54,   54,   54,   54,\n       54,   54,   54\n    },\n\n    {\n        9,  -55,  -55,  -55,  -55,  -55,  -55,   55,  -55,  -55,\n      -55,  -55,  -55,   55,   55,  -55,  -55,  -55,  -55,  -55,\n       55,   55,   55,   55,   55,   55,   55,   55,   55,   55,\n       55,   55,   55,   55,   55,   55,   55,   55,   55,   55,\n       55,   55,  -55\n\n    },\n\n    {\n        9,  -56,  -56,  -56,  -56,  -56,  -56,  -56,  -56,  -56,\n      -56,  -56,  -56,  -56,  -56,  -56,  -56,  -56,  -56,  -56,\n      -56,  -56,  -56,  -56,  -56,  -56,  -56,  -56,  -56,  -56,\n      -56,  -56,  -56,  -56,  -56,  -56,  -56,  -56,  -56,  -56,\n      -56,  -56,  -56\n    },\n\n    {\n        9,  -57,  -57,  -57,  -57,  -57,  -57,  -57,  -57,  -57,\n      -57,  -57,  -57,  -57,  -57,  -57,  -57,  -57,  -57,  -57,\n      -57,  -57,  -57,  -57,  -57,  -57,  -57,  -57,  -57,  -57,\n      -57,  -57,  -57,  -57,  -57,  -57,  -57,  -57,  -57,  -57,\n      -57,  -57,  -57\n\n    },\n\n    {\n        9,  -58,  -58,  -58,  -58,  -58,  -58,   55,  -58,  -58,\n      -58,  -58,  -58,   58,   58,  -58,  -58,  -58,  -58,  -58,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58,  -58\n    },\n\n    {\n        9,  -59,  -59,  -59,  -59,  -59,  -59,  -59,  -59,  -59,\n      -59,  -59,  -59,  -59,  -59,  -59,  -59,  -59,  -59,  -59,\n      -59,  -59,  -59,  -59,  -59,  -59,  -59,  -59,  -59,  -59,\n      -59,  -59,  -59,  -59,  -59,  -59,  -59,  -59,  -59,  -59,\n      -59,  -59,  -59\n\n    },\n\n    {\n        9,  -60,  -60,  -60,  -60,  -60,  -60,  -60,  -60,  -60,\n      -60,  -60,  -60,  -60,  -60,  -60,  -60,  -60,  -60,  -60,\n      -60,  -60,  -60,  -60,  -60,  -60,  -60,  -60,  -60,  -60,\n      -60,  -60,  -60,  -60,  -60,  -60,  -60,  -60,  -60,  -60,\n      -60,  -60,  -60\n    },\n\n    {\n        9,  -61,  -61,  -61,  -61,  -61,  -61,  -61,  -61,  -61,\n      -61,  -61,  -61,  -61,  -61,  -61,  -61,  -61,  -61,  -61,\n      -61,  -61,  -61,  -61,  -61,  -61,  -61,  -61,  -61,  -61,\n      -61,  -61,  -61,  -61,  -61,  -61,  -61,  -61,  -61,  -61,\n      -61,  -61,  -61\n\n    },\n\n    {\n        9,  -62,  -62,  -62,  -62,  -62,  -62,  -62,  -62,  -62,\n      -62,  -62,  -62,  -62,  -62,  -62,  -62,  -62,  -62,  -62,\n      -62,  -62,  -62,  -62,  -62,  -62,  -62,  -62,  -62,  -62,\n      -62,  -62,  -62,  -62,  -62,  -62,  -62,  -62,  -62,  -62,\n      -62,  -62,  -62\n    },\n\n    {\n        9,  -63,  -63,  -63,  -63,  -63,  -63,   55,  -63,  -63,\n      -63,  -63,  -63,   58,   58,  -63,  -63,  -63,  -63,  -63,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58,   58,   95,   58,   58,   58,   58,   58,   58,\n       58,   58,  -63\n\n    },\n\n    {\n        9,  -64,  -64,  -64,  -64,  -64,  -64,   55,  -64,  -64,\n      -64,  -64,  -64,   58,   58,  -64,  -64,  -64,  -64,  -64,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58,   58,   96,   58,   58,   58,   58,   58,   58,\n       58,   58,  -64\n    },\n\n    {\n        9,  -65,  -65,  -65,  -65,  -65,  -65,   55,  -65,  -65,\n      -65,  -65,  -65,   58,   58,  -65,  -65,  -65,  -65,  -65,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   97,   98,   58,   58,   58,   58,   58,   58,   58,\n       58,   58,  -65\n\n    },\n\n    {\n        9,  -66,  -66,  -66,  -66,  -66,  -66,   55,  -66,  -66,\n      -66,  -66,  -66,   58,   58,  -66,  -66,  -66,  -66,  -66,\n       58,   58,   58,   58,   58,   58,   99,   58,   58,   58,\n       58,   58,   58,   58,  100,   58,   58,   58,   58,   58,\n       58,   58,  -66\n    },\n\n    {\n        9,  -67,  -67,  -67,  -67,  -67,  -67,   55,  -67,  -67,\n      -67,  -67,  -67,   58,   58,  -67,  -67,  -67,  -67,  -67,\n       58,   58,   58,   58,  101,   58,   58,   58,   58,   58,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58,  -67\n\n    },\n\n    {\n        9,  -68,  -68,  -68,  -68,  -68,  -68,   55,  -68,  -68,\n      -68,  -68,  -68,   58,   58,  -68,  -68,  -68,  -68,  -68,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n      102,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n      103,   58,  -68\n    },\n\n    {\n        9,  -69,  -69,  -69,  -69,  -69,  -69,   55,  -69,  -69,\n      -69,  -69,  -69,   58,   58,  -69,  -69,  -69,  -69,  -69,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58,  -69\n\n    },\n\n    {\n        9,  -70,  -70,  -70,  -70,  -70,  -70,   55,  -70,  -70,\n      -70,  -70,  -70,   58,   58,  -70,  -70,  -70,  -70,  -70,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58,   58,   58,  104,   58,   58,   58,   58,   58,\n       58,   58,  -70\n    },\n\n    {\n        9,  -71,  -71,  -71,  -71,  -71,  -71,   55,  -71,  -71,\n      -71,  -71,  -71,   58,   58,  -71,  -71,  -71,  -71,  -71,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58,   58,   58,   58,   58,   58,  105,   58,   58,\n       58,   58,  -71\n\n    },\n\n    {\n        9,  -72,  -72,  -72,  -72,  -72,  -72,   55,  -72,  -72,\n      -72,  -72,  -72,   58,   58,  -72,  -72,  -72,  -72,  -72,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,  106,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58,  -72\n    },\n\n    {\n        9,  -73,  -73,  -73,  -73,  -73,  -73,   55,  -73,  -73,\n      -73,  -73,  -73,   58,   58,  -73,  -73,  -73,  -73,  -73,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58,  107,   58,   58,   58,   58,   58,   58,   58,\n       58,   58,  -73\n\n    },\n\n    {\n        9,  -74,  -74,  -74,  -74,  -74,  -74,   55,  -74,  -74,\n      -74,  -74,  -74,   58,   58,  -74,  -74,  -74,  -74,  -74,\n       58,   58,   58,   58,  108,   58,   58,   58,   58,   58,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58,  -74\n    },\n\n    {\n        9,  -75,  -75,  -75,  -75,  -75,  -75,   55,  -75,  -75,\n      -75,  -75,  -75,   58,   58,  -75,  -75,  -75,  -75,  -75,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58,  -75\n\n    },\n\n    {\n        9,  -76,  -76,  -76,  -76,  -76,  -76,   55,  -76,  -76,\n      -76,  -76,  -76,   58,   58,  -76,  -76,  -76,  -76,  -76,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58,   58,   58,   58,   58,   58,  109,   58,   58,\n       58,   58,  -76\n    },\n\n    {\n        9,  -77,  -77,  -77,  -77,  -77,  -77,   55,  -77,  -77,\n      -77,  -77,  -77,   58,   58,  -77,  -77,  -77,  -77,  -77,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58,   58,  110,   58,   58,   58,   58,   58,   58,\n       58,   58,  -77\n\n    },\n\n    {\n        9,  -78,  -78,  -78,  -78,  -78,  -78,   55,  -78,  -78,\n      -78,  -78,  -78,   58,   58,  -78,  -78,  -78,  -78,  -78,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58,  111,   58,   58,   58,   58,   58,   58,   58,\n       58,   58,  -78\n    },\n\n    {\n        9,  -79,  -79,  -79,  -79,  -79,  -79,   55,  -79,  -79,\n      -79,  -79,  -79,   58,   58,  -79,  -79,  -79,  -79,  -79,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58,   58,   58,   58,   58,  112,   58,   58,   58,\n       58,   58,  -79\n\n    },\n\n    {\n        9,  -80,  -80,  -80,  -80,  -80,  -80,   55,  -80,  -80,\n      -80,  -80,  -80,   58,   58,  -80,  -80,  -80,  -80,  -80,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n      113,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58,  -80\n    },\n\n    {\n        9,  -81,  -81,  -81,  -81,  -81,  -81,   55,  -81,  -81,\n      -81,  -81,  -81,   58,   58,  -81,  -81,  -81,  -81,  -81,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58,   58,   58,   58,   58,   58,   58,  114,   58,\n       58,   58,  -81\n\n    },\n\n    {\n        9,  -82,  -82,  -82,  -82,  -82,  -82,   55,  -82,  -82,\n      -82,  -82,  -82,   58,   58,  -82,  -82,  -82,  -82,  -82,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58,   58,   58,   58,  115,   58,   58,   58,   58,\n       58,   58,  -82\n    },\n\n    {\n        9,  -83,  -83,  -83,  -83,  -83,  -83,   55,  -83,  -83,\n      -83,  -83,  -83,   58,   58,  -83,  -83,  -83,  -83,  -83,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,  116,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58,  -83\n\n    },\n\n    {\n        9,  -84,  -84,  -84,  -84,  -84,  -84,   55,  -84,  -84,\n      -84,  -84,  -84,   58,   58,  -84,  -84,  -84,  -84,  -84,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58,   58,   58,   58,   58,  117,   58,   58,   58,\n       58,   58,  -84\n    },\n\n    {\n        9,  -85,  -85,  -85,  -85,  -85,  -85,  -85,  -85,  -85,\n      -85,  -85,  -85,  -85,  -85,  -85,  -85,  -85,  -85,  -85,\n      -85,  -85,  -85,  -85,  -85,  -85,  -85,  -85,  -85,  -85,\n      -85,  -85,  -85,  -85,  -85,  -85,  -85,  -85,  -85,  -85,\n      -85,  -85,  -85\n\n    },\n\n    {\n        9,   86,   87,  -86,   86,   86,   86,   86,   86,   86,\n       86,   86,   86,   86,   86,   86,   86,   86,   86,   86,\n       86,   86,   86,   86,   86,   86,   86,   86,   86,   86,\n       86,   86,   86,   86,   86,   86,   86,   86,   86,   86,\n       86,   86,   86\n    },\n\n    {\n        9,   87,   87,  -87,   87,   87,   87,   87,   87,   87,\n       87,   87,   87,   87,   87,   87,   87,   87,   87,   87,\n       87,   87,   87,   87,   87,   87,   87,   87,   87,   87,\n       87,   87,   87,   87,   87,   87,   87,   87,   87,   87,\n       87,   87,   87\n\n    },\n\n    {\n        9,   88,   88,  -88,   88,   88,   88,   88,   88,   88,\n       88,   88,   88,   88,   88,   88,   88,   88,   88,   88,\n       88,   88,   88,   88,   88,   88,   88,   88,   88,   88,\n       88,   88,   88,   88,   88,   88,   88,   88,   88,   88,\n       88,   88,   88\n    },\n\n    {\n        9,  -89,   89,   90,  -89,  -89,  -89,  -89,  -89,  -89,\n      -89,  -89,  -89,  -89,  -89,  -89,  -89,  -89,  -89,  -89,\n      -89,  -89,  -89,  -89,  -89,  -89,  -89,  -89,  -89,  -89,\n      -89,  -89,  -89,  -89,  -89,  -89,  -89,  -89,  -89,  -89,\n      -89,  -89,  -89\n\n    },\n\n    {\n        9,   91,  -90,  -90,   91,   91,   91,   91,   91,   91,\n       91,   91,   91,   91,   91,   91,   91,   91,   91,   91,\n       91,   91,   91,   91,   91,   91,   91,   91,   91,   91,\n       91,   91,   91,   91,   91,   91,   91,   91,   91,   91,\n       91,   91,   91\n    },\n\n    {\n        9,  -91,  -91,  -91,  -91,  -91,  -91,  -91,  -91,  -91,\n      -91,  -91,  -91,  -91,  -91,  -91,  -91,  -91,  -91,  -91,\n      -91,  -91,  -91,  -91,  -91,  -91,  -91,  -91,  -91,  -91,\n      -91,  -91,  -91,  -91,  -91,  -91,  -91,  -91,  -91,  -91,\n      -91,  -91,  -91\n\n    },\n\n    {\n        9,   92,   92,  -92,   92,  -92,   92,  -92,   92,  -92,\n       92,   92,   92,   92,   92,   92,   92,   92,   92,  -92,\n       92,   92,   92,   92,   92,   92,   92,   92,   92,   92,\n       92,   92,   92,   92,   92,   92,   92,   92,   92,   92,\n       92,   92,   92\n    },\n\n    {\n        9,   93,   93,  -93,   93,   93,   93,   93,   93,   93,\n       93,   93,   93,   93,   93,   93,   93,   93,   93,   93,\n       93,   93,   93,   93,   93,   93,   93,   93,   93,   93,\n       93,   93,   93,   93,   93,   93,   93,   93,   93,   93,\n       93,   93,   93\n\n    },\n\n    {\n        9,  -94,  -94,  -94,  -94,  -94,  -94,  -94,  -94,  -94,\n      -94,  -94,  -94,  -94,  -94,  -94,  -94,  -94,  -94,  -94,\n      -94,  -94,  -94,  -94,  -94,  -94,  -94,  -94,  -94,  -94,\n      -94,  -94,  -94,  -94,  -94,  -94,  -94,  -94,  -94,  -94,\n      -94,  -94,  -94\n    },\n\n    {\n        9,  -95,  -95,  -95,  -95,  -95,  -95,   55,  -95,  -95,\n      -95,  -95,  -95,   58,   58,  -95,  -95,  -95,  -95,  -95,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n      118,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58,  -95\n\n    },\n\n    {\n        9,  -96,  -96,  -96,  -96,  -96,  -96,   55,  -96,  -96,\n      -96,  -96,  -96,   58,   58,  -96,  -96,  -96,  -96,  -96,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,  119,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58,  -96\n    },\n\n    {\n        9,  -97,  -97,  -97,  -97,  -97,  -97,   55,  -97,  -97,\n      -97,  -97,  -97,   58,   58,  -97,  -97,  -97,  -97,  -97,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,  120,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58,  -97\n\n    },\n\n    {\n        9,  -98,  -98,  -98,  -98,  -98,  -98,   55,  -98,  -98,\n      -98,  -98,  -98,   58,   58,  -98,  -98,  -98,  -98,  -98,\n       58,   58,   58,   58,   58,   58,  121,   58,   58,   58,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58,  -98\n    },\n\n    {\n        9,  -99,  -99,  -99,  -99,  -99,  -99,   55,  -99,  -99,\n      -99,  -99,  -99,   58,   58,  -99,  -99,  -99,  -99,  -99,\n      122,  123,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58,  -99\n\n    },\n\n    {\n        9, -100, -100, -100, -100, -100, -100,   55, -100, -100,\n     -100, -100, -100,   58,   58, -100, -100, -100, -100, -100,\n       58,   58,   58,   58,   58,  124,   58,   58,   58,   58,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58, -100\n    },\n\n    {\n        9, -101, -101, -101, -101, -101, -101,   55, -101, -101,\n     -101, -101, -101,   58,   58, -101, -101, -101, -101, -101,\n       58,   58,   58,  125,   58,   58,   58,   58,   58,  126,\n       58,  127,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58, -101\n\n    },\n\n    {\n        9, -102, -102, -102, -102, -102, -102,   55, -102, -102,\n     -102, -102, -102,   58,   58, -102, -102, -102, -102, -102,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58,   58,   58,  128,   58,   58,   58,   58,   58,\n       58,   58, -102\n    },\n\n    {\n        9, -103, -103, -103, -103, -103, -103,   55, -103, -103,\n     -103, -103, -103,   58,   58, -103, -103, -103, -103, -103,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58, -103\n\n    },\n\n    {\n        9, -104, -104, -104, -104, -104, -104,   55, -104, -104,\n     -104, -104, -104,   58,   58, -104, -104, -104, -104, -104,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n      129,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58, -104\n    },\n\n    {\n        9, -105, -105, -105, -105, -105, -105,   55, -105, -105,\n     -105, -105, -105,   58,   58, -105, -105, -105, -105, -105,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58, -105\n\n    },\n\n    {\n        9, -106, -106, -106, -106, -106, -106,   55, -106, -106,\n     -106, -106, -106,   58,   58, -106, -106, -106, -106, -106,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58,  130,   58,   58,   58,   58,   58,   58,   58,\n       58,   58, -106\n    },\n\n    {\n        9, -107, -107, -107, -107, -107, -107,   55, -107, -107,\n     -107, -107, -107,   58,   58, -107, -107, -107, -107, -107,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58,   58,   58,   58,   58,   58,   58,  131,   58,\n       58,   58, -107\n\n    },\n\n    {\n        9, -108, -108, -108, -108, -108, -108,   55, -108, -108,\n     -108, -108, -108,   58,   58, -108, -108, -108, -108, -108,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58,   58,   58,   58,   58,   58,   58,  132,   58,\n       58,   58, -108\n    },\n\n    {\n        9, -109, -109, -109, -109, -109, -109,   55, -109, -109,\n     -109, -109, -109,   58,   58, -109, -109, -109, -109, -109,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,  133,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58, -109\n\n    },\n\n    {\n        9, -110, -110, -110, -110, -110, -110,   55, -110, -110,\n     -110, -110, -110,   58,   58, -110, -110, -110, -110, -110,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,  134,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58, -110\n    },\n\n    {\n        9, -111, -111, -111, -111, -111, -111,   55, -111, -111,\n     -111, -111, -111,   58,   58, -111, -111, -111, -111, -111,\n       58,   58,   58,   58,   58,   58,   58,  135,   58,   58,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58, -111\n\n    },\n\n    {\n        9, -112, -112, -112, -112, -112, -112,   55, -112, -112,\n     -112, -112, -112,   58,   58, -112, -112, -112, -112, -112,\n       58,   58,   58,   58,   58,  136,   58,   58,   58,   58,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58, -112\n    },\n\n    {\n        9, -113, -113, -113, -113, -113, -113,   55, -113, -113,\n     -113, -113, -113,   58,   58, -113, -113, -113, -113, -113,\n       58,   58,   58,   58,   58,  137,   58,   58,   58,   58,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58, -113\n\n    },\n\n    {\n        9, -114, -114, -114, -114, -114, -114,   55, -114, -114,\n     -114, -114, -114,   58,   58, -114, -114, -114, -114, -114,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58,   58,   58,   58,  138,   58,   58,   58,   58,\n       58,   58, -114\n    },\n\n    {\n        9, -115, -115, -115, -115, -115, -115,   55, -115, -115,\n     -115, -115, -115,   58,   58, -115, -115, -115, -115, -115,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,  139,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58, -115\n\n    },\n\n    {\n        9, -116, -116, -116, -116, -116, -116,   55, -116, -116,\n     -116, -116, -116,   58,   58, -116, -116, -116, -116, -116,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58,   58,   58,   58,   58,  140,   58,   58,   58,\n       58,   58, -116\n    },\n\n    {\n        9, -117, -117, -117, -117, -117, -117,   55, -117, -117,\n     -117, -117, -117,   58,   58, -117, -117, -117, -117, -117,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,  141,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58, -117\n\n    },\n\n    {\n        9, -118, -118, -118, -118, -118, -118,   55, -118, -118,\n     -118, -118, -118,   58,   58, -118, -118, -118, -118, -118,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58, -118\n    },\n\n    {\n        9, -119, -119, -119, -119, -119, -119,   55, -119, -119,\n     -119, -119, -119,   58,   58, -119, -119, -119, -119, -119,\n       58,   58,   58,  142,   58,   58,   58,   58,   58,   58,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58, -119\n\n    },\n\n    {\n        9, -120, -120, -120, -120, -120, -120,   55, -120, -120,\n     -120, -120, -120,   58,   58, -120, -120, -120, -120, -120,\n       58,   58,   58,   58,   58,  143,   58,   58,   58,   58,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58, -120\n    },\n\n    {\n        9, -121, -121, -121, -121, -121, -121,   55, -121, -121,\n     -121, -121, -121,   58,   58, -121, -121, -121, -121, -121,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,  144,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58, -121\n\n    },\n\n    {\n        9, -122, -122, -122, -122, -122, -122,   55, -122, -122,\n     -122, -122, -122,   58,   58, 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58,   58, -128\n    },\n\n    {\n        9, -129, -129, -129, -129, -129, -129,   55, -129, -129,\n     -129, -129, -129,   58,   58, -129, -129, -129, -129, -129,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,  152, -129\n\n    },\n\n    {\n        9, -130, -130, -130, -130, -130, -130,   55, -130, -130,\n     -130, -130, -130,   58,   58, -130, -130, -130, -130, -130,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,  153,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58, -130\n    },\n\n    {\n        9, -131, -131, -131, -131, -131, -131,   55, -131, -131,\n     -131, -131, -131,   58,   58, -131, -131, -131, -131, -131,\n       58,   58,   58,  154,   58,   58,   58,   58,   58,   58,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58, -131\n\n    },\n\n    {\n        9, -132, -132, -132, -132, -132, -132,   55, -132, -132,\n     -132, -132, -132,   58,   58, -132, -132, -132, -132, -132,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n      155,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58, -132\n    },\n\n    {\n        9, -133, -133, -133, -133, -133, -133,   55, -133, -133,\n     -133, -133, -133,   58,   58, -133, -133, -133, -133, -133,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58,   58,  156,   58,   58,   58,   58,   58,   58,\n       58,   58, -133\n\n    },\n\n    {\n        9, -134, -134, -134, -134, -134, -134,   55, -134, -134,\n     -134, -134, -134,   58,   58, -134, -134, -134, -134, -134,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58,   58,   58,  157,   58,   58,   58,   58,   58,\n       58,   58, -134\n    },\n\n    {\n        9, -135, -135, -135, -135, -135, -135,   55, -135, -135,\n     -135, -135, -135,   58,   58, -135, -135, -135, -135, -135,\n    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  58,   58,   58,   58,   58,   58,   58,\n       58,   58, -138\n    },\n\n    {\n        9, -139, -139, -139, -139, -139, -139,   55, -139, -139,\n     -139, -139, -139,   58,   58, -139, -139, -139, -139, -139,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58,  162,   58,   58,   58,   58,   58,   58,   58,\n       58,   58, -139\n\n    },\n\n    {\n        9, -140, -140, -140, -140, -140, -140,   55, -140, -140,\n     -140, -140, -140,   58,   58, -140, -140, -140, -140, -140,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58,   58,   58,   58,   58,   58,  163,   58,   58,\n       58,   58, -140\n    },\n\n    {\n        9, -141, -141, -141, -141, -141, -141,   55, -141, -141,\n     -141, -141, -141,   58,   58, -141, -141, -141, -141, -141,\n       58,   58,  164,   58,   58,   58,   58,   58,   58,   58,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58, -141\n\n    },\n\n    {\n        9, -142, -142, -142, -142, -142, -142,   55, -142, -142,\n     -142, -142, -142,   58,   58, -142, -142, -142, -142, -142,\n       58,   58,   58,   58,   58,  165,   58,   58,   58,   58,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58, -142\n    },\n\n    {\n        9, -143, -143, -143, -143, -143, -143,   55, -143, -143,\n     -143, -143, -143,   58,   58, -143, -143, -143, -143, -143,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58,  166,   58,   58,   58,   58,   58,   58,   58,\n       58,   58, -143\n\n    },\n\n    {\n        9, -144, -144, -144, -144, -144, -144,   55, -144, -144,\n     -144, -144, -144,   58,   58, -144, -144, -144, -144, -144,\n       58,   58,   58,   58,   58,   58,   58,  167,   58,   58,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58, -144\n    },\n\n    {\n        9, -145, -145, -145, -145, -145, -145,   55, -145, -145,\n     -145, -145, -145,   58,   58, -145, -145, -145, -145, -145,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58,   58,  168,   58,   58,   58,   58,   58,   58,\n       58,   58, -145\n\n    },\n\n    {\n        9, -146, -146, -146, -146, -146, -146,   55, -146, -146,\n     -146, -146, -146,   58,   58, -146, -146, -146, -146, -146,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58,   58,   58,   58,  169,   58,   58,   58,   58,\n       58,   58, -146\n    },\n\n    {\n        9, -147, -147, -147, -147, -147, -147,   55, -147, -147,\n     -147, -147, -147,   58,   58, -147, -147, -147, -147, -147,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n      170,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58, -147\n\n    },\n\n    {\n        9, -148, -148, -148, -148, -148, -148,   55, -148, -148,\n     -148, -148, -148,   58,   58, -148, -148, -148, -148, -148,\n       58,   58,   58,   58,  171,   58,   58,   58,   58,   58,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58, -148\n    },\n\n    {\n        9, -149, -149, -149, -149, -149, -149,   55, -149, -149,\n     -149, -149, -149,   58,   58, -149, -149, -149, -149, -149,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58,   58,  172,   58,   58,   58,   58,   58,   58,\n       58,   58, -149\n\n    },\n\n    {\n        9, -150, -150, -150, -150, -150, -150,   55, -150, -150,\n     -150, -150, -150,   58,   58, -150, -150, -150, -150, -150,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58, -150\n    },\n\n    {\n        9, -151, -151, -151, -151, -151, -151,   55, -151, -151,\n     -151, -151, -151,   58,   58, -151, -151, -151, -151, -151,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58,  173,   58,   58,   58,   58,   58,   58,   58,\n       58,   58, -151\n\n    },\n\n    {\n        9, -152, -152, -152, -152, -152, -152,   55, -152, -152,\n     -152, -152, -152,   58,   58, -152, -152, -152, -152, -152,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58, -152\n    },\n\n    {\n        9, -153, -153, -153, -153, -153, -153,   55, -153, -153,\n     -153, -153, -153,   58,   58, -153, -153, -153, -153, -153,\n       58,   58,   58,   58,   58,  174,   58,   58,   58,   58,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58, -153\n\n    },\n\n    {\n        9, -154, -154, -154, -154, -154, -154,   55, -154, -154,\n     -154, -154, -154,   58,   58, -154, -154, -154, -154, -154,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58,   58,  175,   58,   58,   58,   58,   58,   58,\n       58,   58, -154\n    },\n\n    {\n        9, -155, -155, -155, -155, -155, -155,   55, -155, -155,\n     -155, -155, -155,   58,   58, -155, -155, -155, -155, -155,\n       58,   58,   58,   58,   58,  176,   58,   58,   58,   58,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58, -155\n\n    },\n\n    {\n        9, -156, -156, -156, -156, -156, -156,   55, -156, -156,\n     -156, -156, -156,   58,   58, -156, -156, -156, -156, -156,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58,  177,   58,   58,   58,   58,   58,   58,   58,\n       58,   58, -156\n    },\n\n    {\n        9, -157, -157, -157, -157, -157, -157,   55, -157, -157,\n     -157, -157, -157,   58,   58, -157, -157, -157, -157, -157,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58,   58,   58,   58,   58,   58,  178,   58,   58,\n       58,   58, -157\n\n    },\n\n    {\n        9, -158, -158, -158, -158, -158, -158,   55, -158, -158,\n     -158, -158, -158,   58,   58, -158, -158, -158, -158, -158,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58, -158\n    },\n\n    {\n        9, -159, -159, -159, -159, -159, -159,   55, -159, -159,\n     -159, -159, -159,   58,   58, -159, -159, -159, -159, -159,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58, -159\n\n    },\n\n    {\n        9, -160, -160, -160, -160, -160, -160,   55, -160, -160,\n     -160, -160, -160,   58,   58, -160, -160, -160, -160, -160,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58,   58,   58,   58,   58,   58,  179,   58,   58,\n       58,   58, -160\n    },\n\n    {\n        9, -161, -161, -161, -161, -161, -161,   55, -161, -161,\n     -161, -161, -161,   58,   58, -161, -161, -161, -161, -161,\n       58,   58,   58,   58,   58,  180,   58,   58,   58,   58,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58, -161\n\n    },\n\n    {\n        9, -162, -162, -162, -162, -162, -162,   55, -162, -162,\n     -162, -162, -162,   58,   58, -162, -162, -162, -162, -162,\n       58,   58,   58,   58,   58,   58,   58,  181,   58,   58,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58, -162\n    },\n\n    {\n        9, -163, -163, -163, -163, -163, -163,   55, -163, -163,\n     -163, -163, -163,   58,   58, -163, -163, -163, -163, -163,\n       58,  182,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58, -163\n\n    },\n\n    {\n        9, -164, -164, -164, -164, -164, -164,   55, -164, -164,\n     -164, -164, -164,   58,   58, -164, -164, -164, -164, -164,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n      183,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58, -164\n    },\n\n    {\n        9, -165, -165, -165, -165, -165, -165,   55, -165, -165,\n     -165, -165, -165,   58,   58, -165, -165, -165, -165, -165,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58, -165\n\n    },\n\n    {\n        9, -166, -166, -166, -166, -166, -166,   55, -166, -166,\n     -166, -166, -166,   58,   58, -166, -166, -166, -166, -166,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58,   58,   58,   58,   58,   58,  184,   58,   58,\n       58,   58, -166\n    },\n\n    {\n        9, -167, -167, -167, -167, -167, -167,   55, -167, -167,\n     -167, -167, -167,   58,   58, -167, -167, -167, -167, -167,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58, -167\n\n    },\n\n    {\n        9, -168, -168, -168, -168, -168, -168,   55, -168, -168,\n     -168, -168, -168,   58,   58, -168, -168, -168, -168, -168,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58,   58,  185,   58,   58,   58,   58,   58,   58,\n       58,   58, -168\n    },\n\n    {\n        9, -169, -169, -169, -169, -169, -169,   55, -169, -169,\n     -169, -169, -169,   58,   58, -169, -169, -169, -169, -169,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,  186,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58, -169\n\n    },\n\n    {\n        9, -170, -170, -170, -170, -170, -170,   55, -170, -170,\n     -170, -170, -170,   58,   58, -170, -170, -170, -170, -170,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58,   58,   58,   58,   58,   58,  187,   58,   58,\n       58,   58, -170\n    },\n\n    {\n        9, -171, -171, -171, -171, -171, -171,   55, -171, -171,\n     -171, -171, -171,   58,   58, -171, -171, -171, -171, -171,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58,   58,   58,   58,   58,  188,   58,   58,   58,\n       58,   58, -171\n\n    },\n\n    {\n        9, -172, -172, -172, -172, -172, -172,   55, -172, -172,\n     -172, -172, -172,   58,   58, -172, -172, -172, -172, -172,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,  189,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58, -172\n    },\n\n    {\n        9, -173, -173, -173, -173, -173, -173,   55, -173, -173,\n     -173, -173, -173,   58,   58, -173, -173, -173, -173, -173,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58,   58,   58,   58,   58,   58,   58,  190,   58,\n       58,   58, -173\n\n    },\n\n    {\n        9, -174, -174, -174, -174, -174, -174,   55, -174, -174,\n     -174, -174, -174,   58,   58, -174, -174, -174, -174, -174,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58,  191,   58,   58,   58,   58,   58,   58,   58,\n       58,   58, -174\n    },\n\n    {\n        9, -175, -175, -175, -175, -175, -175,   55, -175, -175,\n     -175, -175, -175,   58,   58, -175, -175, -175, -175, -175,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58,  192,   58,   58,   58,   58,   58,   58,   58,\n       58,   58, -175\n\n    },\n\n    {\n        9, -176, -176, -176, -176, -176, -176,   55, -176, -176,\n     -176, -176, -176,   58,   58, -176, -176, -176, -176, -176,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58,   58,   58,   58,   58,  193,   58,   58,   58,\n       58,   58, -176\n    },\n\n    {\n        9, -177, -177, -177, -177, -177, -177,   55, -177, -177,\n     -177, -177, -177,   58,   58, -177, -177, -177, -177, -177,\n       58,  194,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58, -177\n\n    },\n\n    {\n        9, -178, -178, -178, -178, -178, -178,   55, -178, -178,\n     -178, -178, -178,   58,   58, -178, -178, -178, -178, -178,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58, -178\n    },\n\n    {\n        9, -179, -179, -179, -179, -179, -179,   55, -179, -179,\n     -179, -179, -179,   58,   58, -179, -179, -179, -179, -179,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58, -179\n\n    },\n\n    {\n        9, -180, -180, -180, -180, -180, -180,   55, -180, -180,\n     -180, -180, -180,   58,   58, -180, -180, -180, -180, -180,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58, -180\n    },\n\n    {\n        9, -181, -181, -181, -181, -181, -181,   55, -181, -181,\n     -181, -181, -181,   58,   58, -181, -181, -181, -181, -181,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58, -181\n\n    },\n\n    {\n        9, -182, -182, -182, -182, -182, -182,   55, -182, -182,\n     -182, -182, -182,   58,   58, -182, -182, -182, -182, -182,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58,   58,   58,   58,   58,   58,  195,   58,   58,\n       58,   58, -182\n    },\n\n    {\n        9, -183, -183, -183, -183, -183, -183,   55, -183, -183,\n     -183, -183, -183,   58,   58, -183, -183, -183, -183, -183,\n       58,   58,   58,   58,   58,  196,   58,   58,   58,   58,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58, -183\n\n    },\n\n    {\n        9, -184, -184, -184, -184, -184, -184,   55, -184, -184,\n     -184, -184, -184,   58,   58, -184, -184, -184, -184, -184,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58, -184\n    },\n\n    {\n        9, -185, -185, -185, -185, -185, -185,   55, -185, -185,\n     -185, -185, -185,   58,   58, -185, -185, -185, -185, -185,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n      197,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58, -185\n\n    },\n\n    {\n        9, -186, -186, -186, -186, -186, -186,   55, -186, -186,\n     -186, -186, -186,   58,   58, -186, -186, -186, -186, -186,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58,   58,   58,   58,   58,  198,   58,   58,   58,\n       58,   58, -186\n    },\n\n    {\n        9, -187, -187, -187, -187, -187, -187,   55, -187, -187,\n     -187, -187, -187,   58,   58, -187, -187, -187, -187, -187,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58, -187\n\n    },\n\n    {\n        9, -188, -188, -188, -188, -188, -188,   55, -188, -188,\n     -188, -188, -188,   58,   58, -188, -188, -188, -188, -188,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58, -188\n    },\n\n    {\n        9, -189, -189, -189, -189, -189, -189,   55, -189, -189,\n     -189, -189, -189,   58,   58, -189, -189, -189, -189, -189,\n       58,   58,   58,  199,   58,   58,   58,   58,   58,   58,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58, -189\n\n    },\n\n    {\n        9, -190, -190, -190, -190, -190, -190,   55, -190, -190,\n     -190, -190, -190,   58,   58, -190, -190, -190, -190, -190,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58, -190\n    },\n\n    {\n        9, -191, -191, -191, -191, -191, -191,   55, -191, -191,\n     -191, -191, -191,   58,   58, -191, -191, -191, -191, -191,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58,   58,   58,   58,   58,   58,   58,  200,   58,\n       58,   58, -191\n\n    },\n\n    {\n        9, -192, -192, -192, -192, -192, -192,   55, -192, -192,\n     -192, -192, -192,   58,   58, -192, -192, -192, -192, -192,\n       58,   58,   58,   58,   58,   58,  201,   58,   58,   58,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58, -192\n    },\n\n    {\n        9, -193, -193, -193, -193, -193, -193,   55, -193, -193,\n     -193, -193, -193,   58,   58, -193, -193, -193, -193, -193,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58, -193\n\n    },\n\n    {\n        9, -194, -194, -194, -194, -194, -194,   55, -194, -194,\n     -194, -194, -194,   58,   58, -194, -194, -194, -194, -194,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n      202,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58, -194\n    },\n\n    {\n        9, -195, -195, -195, -195, -195, -195,   55, -195, -195,\n     -195, -195, -195,   58,   58, -195, -195, -195, -195, -195,\n       58,   58,   58,   58,   58,  203,   58,   58,   58,   58,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58, -195\n\n    },\n\n    {\n        9, -196, -196, -196, -196, -196, -196,   55, -196, -196,\n     -196, -196, -196,   58,   58, -196, -196, -196, -196, -196,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58, -196\n    },\n\n    {\n        9, -197, -197, -197, -197, -197, -197,   55, -197, -197,\n     -197, -197, -197,   58,   58, -197, -197, -197, -197, -197,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58, -197\n\n    },\n\n    {\n        9, -198, -198, -198, -198, -198, -198,   55, -198, -198,\n     -198, -198, -198,   58,   58, -198, -198, -198, -198, -198,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58,   58,   58,   58,   58,   58,  204,   58,   58,\n       58,   58, -198\n    },\n\n    {\n        9, -199, -199, -199, -199, -199, -199,   55, -199, -199,\n     -199, -199, -199,   58,   58, -199, -199, -199, -199, -199,\n       58,   58,   58,   58,   58,  205,   58,   58,   58,   58,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58, -199\n\n    },\n\n    {\n        9, -200, -200, -200, -200, -200, -200,   55, -200, -200,\n     -200, -200, -200,   58,   58, -200, -200, -200, -200, -200,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58, -200\n    },\n\n    {\n        9, -201, -201, -201, -201, -201, -201,   55, -201, -201,\n     -201, -201, -201,   58,   58, -201, -201, -201, -201, -201,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,  206,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58, -201\n\n    },\n\n    {\n        9, -202, -202, -202, -202, -202, -202,   55, -202, -202,\n     -202, -202, -202,   58,   58, -202, -202, -202, -202, -202,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58, -202\n    },\n\n    {\n        9, -203, -203, -203, -203, -203, -203,   55, -203, -203,\n     -203, -203, -203,   58,   58, -203, -203, -203, -203, -203,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58, -203\n\n    },\n\n    {\n        9, -204, -204, -204, -204, -204, -204,   55, -204, -204,\n     -204, -204, -204,   58,   58, -204, -204, -204, -204, -204,\n       58,  207,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58, -204\n    },\n\n    {\n        9, -205, -205, -205, -205, -205, -205,   55, -205, -205,\n     -205, -205, -205,   58,   58, -205, -205, -205, -205, -205,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58, -205\n\n    },\n\n    {\n        9, -206, -206, -206, -206, -206, -206,   55, -206, -206,\n     -206, -206, -206,   58,   58, -206, -206, -206, -206, -206,\n       58,   58,   58,   58,   58,   58,   58,  208,   58,   58,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58, -206\n    },\n\n    {\n        9, -207, -207, -207, -207, -207, -207,   55, -207, -207,\n     -207, -207, -207,   58,   58, -207, -207, -207, -207, -207,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58,   58,   58,   58,   58,   58,  209,   58,   58,\n       58,   58, -207\n\n    },\n\n    {\n        9, -208, -208, -208, -208, -208, -208,   55, -208, -208,\n     -208, -208, -208,   58,   58, -208, -208, -208, -208, -208,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58, -208\n    },\n\n    {\n        9, -209, -209, -209, -209, -209, -209,   55, -209, -209,\n     -209, -209, -209,   58,   58, -209, -209, -209, -209, -209,\n       58,   58,   58,   58,   58,  210,   58,   58,   58,   58,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58, -209\n\n    },\n\n    {\n        9, -210, -210, -210, -210, -210, -210,   55, -210, -210,\n     -210, -210, -210,   58,   58, -210, -210, -210, -210, -210,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58,   58,   58,   58,   58,   58,   58,   58,   58,\n       58,   58, -210\n    },\n\n    } ;\n\nstatic yy_state_type yy_get_previous_state ( void );\nstatic yy_state_type yy_try_NUL_trans ( yy_state_type current_state  );\nstatic int yy_get_next_buffer ( void );\nstatic void yynoreturn yy_fatal_error ( const char* msg  );\n\n/* Done after the current pattern has been matched and before the\n * corresponding action - sets up yytext.\n */\n#define YY_DO_BEFORE_ACTION \\\n\t(yytext_ptr) = yy_bp; \\\n\tyyleng = (int) (yy_cp - yy_bp); \\\n\t(yy_hold_char) = *yy_cp; \\\n\t*yy_cp = '\\0'; \\\n\t(yy_c_buf_p) = yy_cp;\n#define YY_NUM_RULES 64\n#define YY_END_OF_BUFFER 65\n/* This struct is not used in this scanner,\n   but its presence is necessary. */\nstruct yy_trans_info\n\t{\n\tflex_int32_t yy_verify;\n\tflex_int32_t yy_nxt;\n\t};\nstatic const flex_int16_t yy_accept[211] =\n    {   0,\n        2,    2,    0,    0,    0,    0,    0,    0,   65,   51,\n        2,    4,   43,   48,    1,   50,   51,   44,   45,   51,\n       49,   51,   39,   37,   41,   51,   49,   49,   49,   49,\n       49,   49,   49,   49,   49,   49,   49,   49,   49,   51,\n       52,   54,   53,   63,   60,   62,   56,   59,   58,   55,\n       57,    2,   38,    1,   50,   36,   47,   49,   46,   40,\n       42,    3,   49,   49,   49,   49,   49,   49,   18,   49,\n       49,   49,   49,   49,   25,   49,   49,   49,   49,   49,\n       49,   49,   49,   49,   35,   52,   52,   63,   60,   62,\n       61,   56,   55,   57,   49,   49,   49,   49,   49,   49,\n\n       49,   49,   17,   49,   20,   49,   49,   49,   49,   49,\n       49,   49,   49,   49,   49,   49,   49,    5,   49,   49,\n       49,   49,   49,   49,   49,   49,   49,   16,   49,   49,\n       22,   49,   49,   49,   49,   49,   49,   49,   49,   49,\n       49,   49,   49,   49,   49,   49,   49,   49,   49,   14,\n       49,   19,   49,   49,   49,   49,   49,   28,   29,   49,\n       49,   49,   49,   49,    6,   49,    8,   49,   49,   49,\n       49,   49,   49,   49,   49,   49,   49,   27,   30,   31,\n       32,   49,   49,    7,   49,   49,   11,   12,   49,   15,\n       49,   49,   24,   49,   49,   34,    9,   49,   49,   21,\n\n       49,   26,   33,   49,   13,   49,   49,   23,   49,   10\n    } ;\n\nstatic const YY_CHAR yy_ec[256] =\n    {   0,\n        1,    1,    1,    1,    1,    1,    1,    1,    2,    3,\n        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,\n        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,\n        1,    2,    4,    5,    6,    7,    1,    8,    9,   10,\n       11,    1,   12,    1,   13,   14,   14,   13,   13,   13,\n       13,   13,   13,   13,   13,   13,   13,   15,    1,   16,\n       17,   18,    1,    1,   13,   13,   13,   13,   13,   13,\n       13,   13,   13,   13,   13,   13,   13,   13,   13,   13,\n       13,   13,   13,   13,   13,   13,   13,   13,   13,   13,\n        1,   19,    1,    1,   20,    1,   21,   22,   23,   24,\n\n       25,   26,   27,   28,   29,   13,   13,   30,   31,   32,\n       33,   34,   13,   35,   36,   37,   38,   39,   13,   40,\n       41,   13,    1,   42,    1,    1,    1,    1,    1,    1,\n        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,\n        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,\n        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,\n        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,\n        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,\n        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,\n        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,\n\n        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,\n        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,\n        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,\n        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,\n        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,\n        1,    1,    1,    1,    1\n    } ;\n\n/* Table of booleans, true if rule could match eol. */\nstatic const flex_int32_t yy_rule_can_match_eol[65] =\n    {   0,\n0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \n    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \n    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, \n    0, 1, 1, 0, 0,     };\n\nextern int yy_flex_debug;\nint yy_flex_debug = 0;\n\n/* The intent behind this definition is that it'll catch\n * any uses of REJECT which flex missed.\n */\n#define REJECT reject_used_but_not_detected\n#define yymore() yymore_used_but_not_detected\n#define YY_MORE_ADJ 0\n#define YY_RESTORE_YY_MORE_OFFSET\nchar *yytext;\n/* SPDX-License-Identifier: GPL-2.0-only */\n/*\n * Copyright (C) 2002 Roman Zippel <zippel@linux-m68k.org>\n */\n\n#include <assert.h>\n#include <limits.h>\n#include <stdio.h>\n#include <stdlib.h>\n#include <string.h>\n#include <glob.h>\n#include <libgen.h>\n\n#include \"lkc.h\"\n#include \"parser.tab.h\"\n\n#define YY_DECL\t\tstatic int yylex1(void)\n\n#define START_STRSIZE\t16\n\nstatic struct {\n\tstruct file *file;\n\tint lineno;\n} current_pos;\n\nstatic int prev_prev_token = T_EOL;\nstatic int prev_token = T_EOL;\nstatic char *text;\nstatic int text_size, text_asize;\n\nstruct buffer {\n\tstruct buffer *parent;\n\tYY_BUFFER_STATE state;\n};\n\nstatic struct buffer *current_buf;\n\nstatic int last_ts, first_ts;\n\nstatic char *expand_token(const char *in, size_t n);\nstatic void append_expanded_string(const char *in);\nstatic void zconf_endhelp(void);\nstatic void zconf_endfile(void);\n\nstatic void new_string(void)\n{\n\ttext = xmalloc(START_STRSIZE);\n\ttext_asize = START_STRSIZE;\n\ttext_size = 0;\n\t*text = 0;\n}\n\nstatic void append_string(const char *str, int size)\n{\n\tint new_size = text_size + size + 1;\n\tif (new_size > text_asize) {\n\t\tnew_size += START_STRSIZE - 1;\n\t\tnew_size &= -START_STRSIZE;\n\t\ttext = xrealloc(text, new_size);\n\t\ttext_asize = new_size;\n\t}\n\tmemcpy(text + text_size, str, size);\n\ttext_size += size;\n\ttext[text_size] = 0;\n}\n\nstatic void alloc_string(const char *str, int size)\n{\n\ttext = xmalloc(size + 1);\n\tmemcpy(text, str, size);\n\ttext[size] = 0;\n}\n\nstatic void warn_ignored_character(char chr)\n{\n\tfprintf(stderr,\n\t        \"%s:%d:warning: ignoring unsupported character '%c'\\n\",\n\t        current_file->name, yylineno, chr);\n}\n\n#define INITIAL 0\n#define ASSIGN_VAL 1\n#define HELP 2\n#define STRING 3\n\n#ifndef YY_NO_UNISTD_H\n/* Special case for \"unistd.h\", since it is non-ANSI. We include it way\n * down here because we want the user's section 1 to have been scanned first.\n * The user has a chance to override it with an option.\n */\n#include <unistd.h>\n#endif\n\n#ifndef YY_EXTRA_TYPE\n#define YY_EXTRA_TYPE void *\n#endif\n\nstatic int yy_init_globals ( void );\n\n/* Accessor methods to globals.\n   These are made visible to non-reentrant scanners for convenience. */\n\nint yylex_destroy ( void );\n\nint yyget_debug ( void );\n\nvoid yyset_debug ( int debug_flag  );\n\nYY_EXTRA_TYPE yyget_extra ( void );\n\nvoid yyset_extra ( YY_EXTRA_TYPE user_defined  );\n\nFILE *yyget_in ( void );\n\nvoid yyset_in  ( FILE * _in_str  );\n\nFILE *yyget_out ( void );\n\nvoid yyset_out  ( FILE * _out_str  );\n\n\t\t\tint yyget_leng ( void );\n\nchar *yyget_text ( void );\n\nint yyget_lineno ( void );\n\nvoid yyset_lineno ( int _line_number  );\n\n/* Macros after this point can all be overridden by user definitions in\n * section 1.\n */\n\n#ifndef YY_SKIP_YYWRAP\n#ifdef __cplusplus\nextern \"C\" int yywrap ( void );\n#else\nextern int yywrap ( void );\n#endif\n#endif\n\n#ifndef YY_NO_UNPUT\n    \n    static void yyunput ( int c, char *buf_ptr  );\n    \n#endif\n\n#ifndef yytext_ptr\nstatic void yy_flex_strncpy ( char *, const char *, int );\n#endif\n\n#ifdef YY_NEED_STRLEN\nstatic int yy_flex_strlen ( const char * );\n#endif\n\n#ifndef YY_NO_INPUT\n#ifdef __cplusplus\nstatic int yyinput ( void );\n#else\nstatic int input ( void );\n#endif\n\n#endif\n\n/* Amount of stuff to slurp up with each read. */\n#ifndef YY_READ_BUF_SIZE\n#ifdef __ia64__\n/* On IA-64, the buffer size is 16k, not 8k */\n#define YY_READ_BUF_SIZE 16384\n#else\n#define YY_READ_BUF_SIZE 8192\n#endif /* __ia64__ */\n#endif\n\n/* Copy whatever the last rule matched to the standard output. */\n#ifndef ECHO\n/* This used to be an fputs(), but since the string might contain NUL's,\n * we now use fwrite().\n */\n#define ECHO do { if (fwrite( yytext, (size_t) yyleng, 1, yyout )) {} } while (0)\n#endif\n\n/* Gets input and stuffs it into \"buf\".  number of characters read, or YY_NULL,\n * is returned in \"result\".\n */\n#ifndef YY_INPUT\n#define YY_INPUT(buf,result,max_size) \\\n\terrno=0; \\\n\twhile ( (result = (int) read( fileno(yyin), buf, (yy_size_t) max_size )) < 0 ) \\\n\t{ \\\n\t\tif( errno != EINTR) \\\n\t\t{ \\\n\t\t\tYY_FATAL_ERROR( \"input in flex scanner failed\" ); \\\n\t\t\tbreak; \\\n\t\t} \\\n\t\terrno=0; \\\n\t\tclearerr(yyin); \\\n\t}\\\n\\\n\n#endif\n\n/* No semi-colon after return; correct usage is to write \"yyterminate();\" -\n * we don't want an extra ';' after the \"return\" because that will cause\n * some compilers to complain about unreachable statements.\n */\n#ifndef yyterminate\n#define yyterminate() return YY_NULL\n#endif\n\n/* Number of entries by which start-condition stack grows. */\n#ifndef YY_START_STACK_INCR\n#define YY_START_STACK_INCR 25\n#endif\n\n/* Report a fatal error. */\n#ifndef YY_FATAL_ERROR\n#define YY_FATAL_ERROR(msg) yy_fatal_error( msg )\n#endif\n\n/* end tables serialization structures and prototypes */\n\n/* Default declaration of generated scanner - a define so the user can\n * easily add parameters.\n */\n#ifndef YY_DECL\n#define YY_DECL_IS_OURS 1\n\nextern int yylex (void);\n\n#define YY_DECL int yylex (void)\n#endif /* !YY_DECL */\n\n/* Code executed at the beginning of each rule, after yytext and yyleng\n * have been set up.\n */\n#ifndef YY_USER_ACTION\n#define YY_USER_ACTION\n#endif\n\n/* Code executed at the end of each rule. */\n#ifndef YY_BREAK\n#define YY_BREAK /*LINTED*/break;\n#endif\n\n#define YY_RULE_SETUP \\\n\tYY_USER_ACTION\n\n/** The main scanner function which does all the work.\n */\nYY_DECL\n{\n\tyy_state_type yy_current_state;\n\tchar *yy_cp, *yy_bp;\n\tint yy_act;\n    \n\tif ( !(yy_init) )\n\t\t{\n\t\t(yy_init) = 1;\n\n#ifdef YY_USER_INIT\n\t\tYY_USER_INIT;\n#endif\n\n\t\tif ( ! (yy_start) )\n\t\t\t(yy_start) = 1;\t/* first start state */\n\n\t\tif ( ! yyin )\n\t\t\tyyin = stdin;\n\n\t\tif ( ! yyout )\n\t\t\tyyout = stdout;\n\n\t\tif ( ! YY_CURRENT_BUFFER ) {\n\t\t\tyyensure_buffer_stack ();\n\t\t\tYY_CURRENT_BUFFER_LVALUE =\n\t\t\t\tyy_create_buffer( yyin, YY_BUF_SIZE );\n\t\t}\n\n\t\tyy_load_buffer_state(  );\n\t\t}\n\n\t{\n\n\tint str = 0;\n\tint ts, i;\n\n\twhile ( /*CONSTCOND*/1 )\t\t/* loops until end-of-file is reached */\n\t\t{\n\t\tyy_cp = (yy_c_buf_p);\n\n\t\t/* Support of yytext. */\n\t\t*yy_cp = (yy_hold_char);\n\n\t\t/* yy_bp points to the position in yy_ch_buf of the start of\n\t\t * the current run.\n\t\t */\n\t\tyy_bp = yy_cp;\n\n\t\tyy_current_state = (yy_start);\nyy_match:\n\t\twhile ( (yy_current_state = yy_nxt[yy_current_state][ yy_ec[YY_SC_TO_UI(*yy_cp)]  ]) > 0 )\n\t\t\t++yy_cp;\n\n\t\tyy_current_state = -yy_current_state;\n\nyy_find_action:\n\t\tyy_act = yy_accept[yy_current_state];\n\n\t\tYY_DO_BEFORE_ACTION;\n\n\t\tif ( yy_act != YY_END_OF_BUFFER && yy_rule_can_match_eol[yy_act] )\n\t\t\t{\n\t\t\tint yyl;\n\t\t\tfor ( yyl = 0; yyl < yyleng; ++yyl )\n\t\t\t\tif ( yytext[yyl] == '\\n' )\n\t\t\t\t\t\n    yylineno++;\n;\n\t\t\t}\n\ndo_action:\t/* This label is used only to access EOF actions. */\n\n\t\tswitch ( yy_act )\n\t{ /* beginning of action switch */\ncase 1:\nYY_RULE_SETUP\n/* ignore comment */\n\tYY_BREAK\ncase 2:\nYY_RULE_SETUP\n/* whitespaces */\n\tYY_BREAK\ncase 3:\n/* rule 3 can match eol */\nYY_RULE_SETUP\n/* escaped new line */\n\tYY_BREAK\ncase 4:\n/* rule 4 can match eol */\nYY_RULE_SETUP\nreturn T_EOL;\n\tYY_BREAK\ncase 5:\nYY_RULE_SETUP\nreturn T_BOOL;\n\tYY_BREAK\ncase 6:\nYY_RULE_SETUP\nreturn T_CHOICE;\n\tYY_BREAK\ncase 7:\nYY_RULE_SETUP\nreturn T_COMMENT;\n\tYY_BREAK\ncase 8:\nYY_RULE_SETUP\nreturn T_CONFIG;\n\tYY_BREAK\ncase 9:\nYY_RULE_SETUP\nreturn T_DEF_BOOL;\n\tYY_BREAK\ncase 10:\nYY_RULE_SETUP\nreturn T_DEF_TRISTATE;\n\tYY_BREAK\ncase 11:\nYY_RULE_SETUP\nreturn T_DEFAULT;\n\tYY_BREAK\ncase 12:\nYY_RULE_SETUP\nreturn T_DEPENDS;\n\tYY_BREAK\ncase 13:\nYY_RULE_SETUP\nreturn T_ENDCHOICE;\n\tYY_BREAK\ncase 14:\nYY_RULE_SETUP\nreturn T_ENDIF;\n\tYY_BREAK\ncase 15:\nYY_RULE_SETUP\nreturn T_ENDMENU;\n\tYY_BREAK\ncase 16:\nYY_RULE_SETUP\nreturn T_HELP;\n\tYY_BREAK\ncase 17:\nYY_RULE_SETUP\nreturn T_HEX;\n\tYY_BREAK\ncase 18:\nYY_RULE_SETUP\nreturn T_IF;\n\tYY_BREAK\ncase 19:\nYY_RULE_SETUP\nreturn T_IMPLY;\n\tYY_BREAK\ncase 20:\nYY_RULE_SETUP\nreturn T_INT;\n\tYY_BREAK\ncase 21:\nYY_RULE_SETUP\nreturn T_MAINMENU;\n\tYY_BREAK\ncase 22:\nYY_RULE_SETUP\nreturn T_MENU;\n\tYY_BREAK\ncase 23:\nYY_RULE_SETUP\nreturn T_MENUCONFIG;\n\tYY_BREAK\ncase 24:\nYY_RULE_SETUP\nreturn T_MODULES;\n\tYY_BREAK\ncase 25:\nYY_RULE_SETUP\nreturn T_ON;\n\tYY_BREAK\ncase 26:\nYY_RULE_SETUP\nreturn T_OPTIONAL;\n\tYY_BREAK\ncase 27:\nYY_RULE_SETUP\nreturn T_PROMPT;\n\tYY_BREAK\ncase 28:\nYY_RULE_SETUP\nreturn T_RANGE;\n\tYY_BREAK\ncase 29:\nYY_RULE_SETUP\nreturn T_RESET;\n\tYY_BREAK\ncase 30:\nYY_RULE_SETUP\nreturn T_SELECT;\n\tYY_BREAK\ncase 31:\nYY_RULE_SETUP\nreturn T_SOURCE;\n\tYY_BREAK\ncase 32:\nYY_RULE_SETUP\nreturn T_STRING;\n\tYY_BREAK\ncase 33:\nYY_RULE_SETUP\nreturn T_TRISTATE;\n\tYY_BREAK\ncase 34:\nYY_RULE_SETUP\nreturn T_VISIBLE;\n\tYY_BREAK\ncase 35:\nYY_RULE_SETUP\nreturn T_OR;\n\tYY_BREAK\ncase 36:\nYY_RULE_SETUP\nreturn T_AND;\n\tYY_BREAK\ncase 37:\nYY_RULE_SETUP\nreturn T_EQUAL;\n\tYY_BREAK\ncase 38:\nYY_RULE_SETUP\nreturn T_UNEQUAL;\n\tYY_BREAK\ncase 39:\nYY_RULE_SETUP\nreturn T_LESS;\n\tYY_BREAK\ncase 40:\nYY_RULE_SETUP\nreturn T_LESS_EQUAL;\n\tYY_BREAK\ncase 41:\nYY_RULE_SETUP\nreturn T_GREATER;\n\tYY_BREAK\ncase 42:\nYY_RULE_SETUP\nreturn T_GREATER_EQUAL;\n\tYY_BREAK\ncase 43:\nYY_RULE_SETUP\nreturn T_NOT;\n\tYY_BREAK\ncase 44:\nYY_RULE_SETUP\nreturn T_OPEN_PAREN;\n\tYY_BREAK\ncase 45:\nYY_RULE_SETUP\nreturn T_CLOSE_PAREN;\n\tYY_BREAK\ncase 46:\nYY_RULE_SETUP\nreturn T_COLON_EQUAL;\n\tYY_BREAK\ncase 47:\nYY_RULE_SETUP\nreturn T_PLUS_EQUAL;\n\tYY_BREAK\ncase 48:\nYY_RULE_SETUP\n{\n\t\t\t\tstr = yytext[0];\n\t\t\t\tnew_string();\n\t\t\t\tBEGIN(STRING);\n\t\t\t}\n\tYY_BREAK\ncase 49:\nYY_RULE_SETUP\n{\n\t\t\t\talloc_string(yytext, yyleng);\n\t\t\t\tyylval.string = text;\n\t\t\t\treturn T_WORD;\n\t\t\t}\n\tYY_BREAK\ncase 50:\nYY_RULE_SETUP\n{\n\t\t\t\t/* this token includes at least one '$' */\n\t\t\t\tyylval.string = expand_token(yytext, yyleng);\n\t\t\t\tif (strlen(yylval.string))\n\t\t\t\t\treturn T_WORD;\n\t\t\t\tfree(yylval.string);\n\t\t\t}\n\tYY_BREAK\ncase 51:\nYY_RULE_SETUP\nwarn_ignored_character(*yytext);\n\tYY_BREAK\n\ncase 52:\nYY_RULE_SETUP\n{\n\t\talloc_string(yytext, yyleng);\n\t\tyylval.string = text;\n\t\treturn T_ASSIGN_VAL;\n\t}\n\tYY_BREAK\ncase 53:\n/* rule 53 can match eol */\nYY_RULE_SETUP\n{ BEGIN(INITIAL); return T_EOL; }\n\tYY_BREAK\ncase 54:\nYY_RULE_SETUP\n\n\tYY_BREAK\n\ncase 55:\nYY_RULE_SETUP\nappend_expanded_string(yytext);\n\tYY_BREAK\ncase 56:\nYY_RULE_SETUP\n{\n\t\tappend_string(yytext, yyleng);\n\t}\n\tYY_BREAK\ncase 57:\nYY_RULE_SETUP\n{\n\t\tappend_string(yytext + 1, yyleng - 1);\n\t}\n\tYY_BREAK\ncase 58:\nYY_RULE_SETUP\n{\n\t\tif (str == yytext[0]) {\n\t\t\tBEGIN(INITIAL);\n\t\t\tyylval.string = text;\n\t\t\treturn T_WORD_QUOTE;\n\t\t} else\n\t\t\tappend_string(yytext, 1);\n\t}\n\tYY_BREAK\ncase 59:\n/* rule 59 can match eol */\nYY_RULE_SETUP\n{\n\t\tfprintf(stderr,\n\t\t\t\"%s:%d:warning: multi-line strings not supported\\n\",\n\t\t\tzconf_curname(), zconf_lineno());\n\t\tunput('\\n');\n\t\tBEGIN(INITIAL);\n\t\tyylval.string = text;\n\t\treturn T_WORD_QUOTE;\n\t}\n\tYY_BREAK\ncase YY_STATE_EOF(STRING):\n{\n\t\tBEGIN(INITIAL);\n\t\tyylval.string = text;\n\t\treturn T_WORD_QUOTE;\n\t}\n\tYY_BREAK\n\ncase 60:\nYY_RULE_SETUP\n{\n\t\tts = 0;\n\t\tfor (i = 0; i < yyleng; i++) {\n\t\t\tif (yytext[i] == '\\t')\n\t\t\t\tts = (ts & ~7) + 8;\n\t\t\telse\n\t\t\t\tts++;\n\t\t}\n\t\tlast_ts = ts;\n\t\tif (first_ts) {\n\t\t\tif (ts < first_ts) {\n\t\t\t\tzconf_endhelp();\n\t\t\t\treturn T_HELPTEXT;\n\t\t\t}\n\t\t\tts -= first_ts;\n\t\t\twhile (ts > 8) {\n\t\t\t\tappend_string(\"        \", 8);\n\t\t\t\tts -= 8;\n\t\t\t}\n\t\t\tappend_string(\"        \", ts);\n\t\t}\n\t}\n\tYY_BREAK\ncase 61:\n/* rule 61 can match eol */\n*yy_cp = (yy_hold_char); /* undo effects of setting up yytext */\nYY_LINENO_REWIND_TO(yy_cp - 1);\n(yy_c_buf_p) = yy_cp -= 1;\nYY_DO_BEFORE_ACTION; /* set up yytext again */\nYY_RULE_SETUP\n{\n\t\tzconf_endhelp();\n\t\treturn T_HELPTEXT;\n\t}\n\tYY_BREAK\ncase 62:\n/* rule 62 can match eol */\nYY_RULE_SETUP\n{\n\t\tappend_string(\"\\n\", 1);\n\t}\n\tYY_BREAK\ncase 63:\nYY_RULE_SETUP\n{\n\t\twhile (yyleng) {\n\t\t\tif ((yytext[yyleng-1] != ' ') && (yytext[yyleng-1] != '\\t'))\n\t\t\t\tbreak;\n\t\t\tyyleng--;\n\t\t}\n\t\tappend_string(yytext, yyleng);\n\t\tif (!first_ts)\n\t\t\tfirst_ts = last_ts;\n\t}\n\tYY_BREAK\ncase YY_STATE_EOF(HELP):\n{\n\t\tzconf_endhelp();\n\t\treturn T_HELPTEXT;\n\t}\n\tYY_BREAK\n\ncase YY_STATE_EOF(INITIAL):\ncase YY_STATE_EOF(ASSIGN_VAL):\n{\n\tBEGIN(INITIAL);\n\n\tif (prev_token != T_EOL && prev_token != T_HELPTEXT)\n\t\tfprintf(stderr, \"%s:%d:warning: no new line at end of file\\n\",\n\t\t\tcurrent_file->name, yylineno);\n\n\tif (current_file) {\n\t\tzconf_endfile();\n\t\treturn T_EOL;\n\t}\n\tfclose(yyin);\n\tyyterminate();\n}\n\tYY_BREAK\ncase 64:\nYY_RULE_SETUP\nYY_FATAL_ERROR( \"flex scanner jammed\" );\n\tYY_BREAK\n\n\tcase YY_END_OF_BUFFER:\n\t\t{\n\t\t/* Amount of text matched not including the EOB char. */\n\t\tint yy_amount_of_matched_text = (int) (yy_cp - (yytext_ptr)) - 1;\n\n\t\t/* Undo the effects of YY_DO_BEFORE_ACTION. */\n\t\t*yy_cp = (yy_hold_char);\n\t\tYY_RESTORE_YY_MORE_OFFSET\n\n\t\tif ( YY_CURRENT_BUFFER_LVALUE->yy_buffer_status == YY_BUFFER_NEW )\n\t\t\t{\n\t\t\t/* We're scanning a new file or input source.  It's\n\t\t\t * possible that this happened because the user\n\t\t\t * just pointed yyin at a new source and called\n\t\t\t * yylex().  If so, then we have to assure\n\t\t\t * consistency between YY_CURRENT_BUFFER and our\n\t\t\t * globals.  Here is the right place to do so, because\n\t\t\t * this is the first action (other than possibly a\n\t\t\t * back-up) that will match for the new input source.\n\t\t\t */\n\t\t\t(yy_n_chars) = YY_CURRENT_BUFFER_LVALUE->yy_n_chars;\n\t\t\tYY_CURRENT_BUFFER_LVALUE->yy_input_file = yyin;\n\t\t\tYY_CURRENT_BUFFER_LVALUE->yy_buffer_status = YY_BUFFER_NORMAL;\n\t\t\t}\n\n\t\t/* Note that here we test for yy_c_buf_p \"<=\" to the position\n\t\t * of the first EOB in the buffer, since yy_c_buf_p will\n\t\t * already have been incremented past the NUL character\n\t\t * (since all states make transitions on EOB to the\n\t\t * end-of-buffer state).  Contrast this with the test\n\t\t * in input().\n\t\t */\n\t\tif ( (yy_c_buf_p) <= &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars)] )\n\t\t\t{ /* This was really a NUL. */\n\t\t\tyy_state_type yy_next_state;\n\n\t\t\t(yy_c_buf_p) = (yytext_ptr) + yy_amount_of_matched_text;\n\n\t\t\tyy_current_state = yy_get_previous_state(  );\n\n\t\t\t/* Okay, we're now positioned to make the NUL\n\t\t\t * transition.  We couldn't have\n\t\t\t * yy_get_previous_state() go ahead and do it\n\t\t\t * for us because it doesn't know how to deal\n\t\t\t * with the possibility of jamming (and we don't\n\t\t\t * want to build jamming into it because then it\n\t\t\t * will run more slowly).\n\t\t\t */\n\n\t\t\tyy_next_state = yy_try_NUL_trans( yy_current_state );\n\n\t\t\tyy_bp = (yytext_ptr) + YY_MORE_ADJ;\n\n\t\t\tif ( yy_next_state )\n\t\t\t\t{\n\t\t\t\t/* Consume the NUL. */\n\t\t\t\tyy_cp = ++(yy_c_buf_p);\n\t\t\t\tyy_current_state = yy_next_state;\n\t\t\t\tgoto yy_match;\n\t\t\t\t}\n\n\t\t\telse\n\t\t\t\t{\n\t\t\t\tyy_cp = (yy_c_buf_p);\n\t\t\t\tgoto yy_find_action;\n\t\t\t\t}\n\t\t\t}\n\n\t\telse switch ( yy_get_next_buffer(  ) )\n\t\t\t{\n\t\t\tcase EOB_ACT_END_OF_FILE:\n\t\t\t\t{\n\t\t\t\t(yy_did_buffer_switch_on_eof) = 0;\n\n\t\t\t\tif ( yywrap(  ) )\n\t\t\t\t\t{\n\t\t\t\t\t/* Note: because we've taken care in\n\t\t\t\t\t * yy_get_next_buffer() to have set up\n\t\t\t\t\t * yytext, we can now set up\n\t\t\t\t\t * yy_c_buf_p so that if some total\n\t\t\t\t\t * hoser (like flex itself) wants to\n\t\t\t\t\t * call the scanner after we return the\n\t\t\t\t\t * YY_NULL, it'll still work - another\n\t\t\t\t\t * YY_NULL will get returned.\n\t\t\t\t\t */\n\t\t\t\t\t(yy_c_buf_p) = (yytext_ptr) + YY_MORE_ADJ;\n\n\t\t\t\t\tyy_act = YY_STATE_EOF(YY_START);\n\t\t\t\t\tgoto do_action;\n\t\t\t\t\t}\n\n\t\t\t\telse\n\t\t\t\t\t{\n\t\t\t\t\tif ( ! (yy_did_buffer_switch_on_eof) )\n\t\t\t\t\t\tYY_NEW_FILE;\n\t\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\t\t}\n\n\t\t\tcase EOB_ACT_CONTINUE_SCAN:\n\t\t\t\t(yy_c_buf_p) =\n\t\t\t\t\t(yytext_ptr) + yy_amount_of_matched_text;\n\n\t\t\t\tyy_current_state = yy_get_previous_state(  );\n\n\t\t\t\tyy_cp = (yy_c_buf_p);\n\t\t\t\tyy_bp = (yytext_ptr) + YY_MORE_ADJ;\n\t\t\t\tgoto yy_match;\n\n\t\t\tcase EOB_ACT_LAST_MATCH:\n\t\t\t\t(yy_c_buf_p) =\n\t\t\t\t&YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars)];\n\n\t\t\t\tyy_current_state = yy_get_previous_state(  );\n\n\t\t\t\tyy_cp = (yy_c_buf_p);\n\t\t\t\tyy_bp = (yytext_ptr) + YY_MORE_ADJ;\n\t\t\t\tgoto yy_find_action;\n\t\t\t}\n\t\tbreak;\n\t\t}\n\n\tdefault:\n\t\tYY_FATAL_ERROR(\n\t\t\t\"fatal flex scanner internal error--no action found\" );\n\t} /* end of action switch */\n\t\t} /* end of scanning one token */\n\t} /* end of user's declarations */\n} /* end of yylex */\n\n/* yy_get_next_buffer - try to read in a new buffer\n *\n * Returns a code representing an action:\n *\tEOB_ACT_LAST_MATCH -\n *\tEOB_ACT_CONTINUE_SCAN - continue scanning from current position\n *\tEOB_ACT_END_OF_FILE - end of file\n */\nstatic int yy_get_next_buffer (void)\n{\n    \tchar *dest = YY_CURRENT_BUFFER_LVALUE->yy_ch_buf;\n\tchar *source = (yytext_ptr);\n\tint number_to_move, i;\n\tint ret_val;\n\n\tif ( (yy_c_buf_p) > &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars) + 1] )\n\t\tYY_FATAL_ERROR(\n\t\t\"fatal flex scanner internal error--end of buffer missed\" );\n\n\tif ( YY_CURRENT_BUFFER_LVALUE->yy_fill_buffer == 0 )\n\t\t{ /* Don't try to fill the buffer, so this is an EOF. */\n\t\tif ( (yy_c_buf_p) - (yytext_ptr) - YY_MORE_ADJ == 1 )\n\t\t\t{\n\t\t\t/* We matched a single character, the EOB, so\n\t\t\t * treat this as a final EOF.\n\t\t\t */\n\t\t\treturn EOB_ACT_END_OF_FILE;\n\t\t\t}\n\n\t\telse\n\t\t\t{\n\t\t\t/* We matched some text prior to the EOB, first\n\t\t\t * process it.\n\t\t\t */\n\t\t\treturn EOB_ACT_LAST_MATCH;\n\t\t\t}\n\t\t}\n\n\t/* Try to read more data. */\n\n\t/* First move last chars to start of buffer. */\n\tnumber_to_move = (int) ((yy_c_buf_p) - (yytext_ptr) - 1);\n\n\tfor ( i = 0; i < number_to_move; ++i )\n\t\t*(dest++) = *(source++);\n\n\tif ( YY_CURRENT_BUFFER_LVALUE->yy_buffer_status == YY_BUFFER_EOF_PENDING )\n\t\t/* don't do the read, it's not guaranteed to return an EOF,\n\t\t * just force an EOF\n\t\t */\n\t\tYY_CURRENT_BUFFER_LVALUE->yy_n_chars = (yy_n_chars) = 0;\n\n\telse\n\t\t{\n\t\t\tint num_to_read =\n\t\t\tYY_CURRENT_BUFFER_LVALUE->yy_buf_size - number_to_move - 1;\n\n\t\twhile ( num_to_read <= 0 )\n\t\t\t{ /* Not enough room in the buffer - grow it. */\n\n\t\t\t/* just a shorter name for the current buffer */\n\t\t\tYY_BUFFER_STATE b = YY_CURRENT_BUFFER_LVALUE;\n\n\t\t\tint yy_c_buf_p_offset =\n\t\t\t\t(int) ((yy_c_buf_p) - b->yy_ch_buf);\n\n\t\t\tif ( b->yy_is_our_buffer )\n\t\t\t\t{\n\t\t\t\tint new_size = b->yy_buf_size * 2;\n\n\t\t\t\tif ( new_size <= 0 )\n\t\t\t\t\tb->yy_buf_size += b->yy_buf_size / 8;\n\t\t\t\telse\n\t\t\t\t\tb->yy_buf_size *= 2;\n\n\t\t\t\tb->yy_ch_buf = (char *)\n\t\t\t\t\t/* Include room in for 2 EOB chars. */\n\t\t\t\t\tyyrealloc( (void *) b->yy_ch_buf,\n\t\t\t\t\t\t\t (yy_size_t) (b->yy_buf_size + 2)  );\n\t\t\t\t}\n\t\t\telse\n\t\t\t\t/* Can't grow it, we don't own it. */\n\t\t\t\tb->yy_ch_buf = NULL;\n\n\t\t\tif ( ! b->yy_ch_buf )\n\t\t\t\tYY_FATAL_ERROR(\n\t\t\t\t\"fatal error - scanner input buffer overflow\" );\n\n\t\t\t(yy_c_buf_p) = &b->yy_ch_buf[yy_c_buf_p_offset];\n\n\t\t\tnum_to_read = YY_CURRENT_BUFFER_LVALUE->yy_buf_size -\n\t\t\t\t\t\tnumber_to_move - 1;\n\n\t\t\t}\n\n\t\tif ( num_to_read > YY_READ_BUF_SIZE )\n\t\t\tnum_to_read = YY_READ_BUF_SIZE;\n\n\t\t/* Read in more data. */\n\t\tYY_INPUT( (&YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[number_to_move]),\n\t\t\t(yy_n_chars), num_to_read );\n\n\t\tYY_CURRENT_BUFFER_LVALUE->yy_n_chars = (yy_n_chars);\n\t\t}\n\n\tif ( (yy_n_chars) == 0 )\n\t\t{\n\t\tif ( number_to_move == YY_MORE_ADJ )\n\t\t\t{\n\t\t\tret_val = EOB_ACT_END_OF_FILE;\n\t\t\tyyrestart( yyin  );\n\t\t\t}\n\n\t\telse\n\t\t\t{\n\t\t\tret_val = EOB_ACT_LAST_MATCH;\n\t\t\tYY_CURRENT_BUFFER_LVALUE->yy_buffer_status =\n\t\t\t\tYY_BUFFER_EOF_PENDING;\n\t\t\t}\n\t\t}\n\n\telse\n\t\tret_val = EOB_ACT_CONTINUE_SCAN;\n\n\tif (((yy_n_chars) + number_to_move) > YY_CURRENT_BUFFER_LVALUE->yy_buf_size) {\n\t\t/* Extend the array by 50%, plus the number we really need. */\n\t\tint new_size = (yy_n_chars) + number_to_move + ((yy_n_chars) >> 1);\n\t\tYY_CURRENT_BUFFER_LVALUE->yy_ch_buf = (char *) yyrealloc(\n\t\t\t(void *) YY_CURRENT_BUFFER_LVALUE->yy_ch_buf, (yy_size_t) new_size  );\n\t\tif ( ! YY_CURRENT_BUFFER_LVALUE->yy_ch_buf )\n\t\t\tYY_FATAL_ERROR( \"out of dynamic memory in yy_get_next_buffer()\" );\n\t\t/* \"- 2\" to take care of EOB's */\n\t\tYY_CURRENT_BUFFER_LVALUE->yy_buf_size = (int) (new_size - 2);\n\t}\n\n\t(yy_n_chars) += number_to_move;\n\tYY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars)] = YY_END_OF_BUFFER_CHAR;\n\tYY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars) + 1] = YY_END_OF_BUFFER_CHAR;\n\n\t(yytext_ptr) = &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[0];\n\n\treturn ret_val;\n}\n\n/* yy_get_previous_state - get the state just before the EOB char was reached */\n\n    static yy_state_type yy_get_previous_state (void)\n{\n\tyy_state_type yy_current_state;\n\tchar *yy_cp;\n    \n\tyy_current_state = (yy_start);\n\n\tfor ( yy_cp = (yytext_ptr) + YY_MORE_ADJ; yy_cp < (yy_c_buf_p); ++yy_cp )\n\t\t{\n\t\tyy_current_state = yy_nxt[yy_current_state][(*yy_cp ? yy_ec[YY_SC_TO_UI(*yy_cp)] : 1)];\n\t\t}\n\n\treturn yy_current_state;\n}\n\n/* yy_try_NUL_trans - try to make a transition on the NUL character\n *\n * synopsis\n *\tnext_state = yy_try_NUL_trans( current_state );\n */\n    static yy_state_type yy_try_NUL_trans  (yy_state_type yy_current_state )\n{\n\tint yy_is_jam;\n    \n\tyy_current_state = yy_nxt[yy_current_state][1];\n\tyy_is_jam = (yy_current_state <= 0);\n\n\t\treturn yy_is_jam ? 0 : yy_current_state;\n}\n\n#ifndef YY_NO_UNPUT\n\n    static void yyunput (int c, char * yy_bp )\n{\n\tchar *yy_cp;\n    \n    yy_cp = (yy_c_buf_p);\n\n\t/* undo effects of setting up yytext */\n\t*yy_cp = (yy_hold_char);\n\n\tif ( yy_cp < YY_CURRENT_BUFFER_LVALUE->yy_ch_buf + 2 )\n\t\t{ /* need to shift things up to make room */\n\t\t/* +2 for EOB chars. */\n\t\tint number_to_move = (yy_n_chars) + 2;\n\t\tchar *dest = &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[\n\t\t\t\t\tYY_CURRENT_BUFFER_LVALUE->yy_buf_size + 2];\n\t\tchar *source =\n\t\t\t\t&YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[number_to_move];\n\n\t\twhile ( source > YY_CURRENT_BUFFER_LVALUE->yy_ch_buf )\n\t\t\t*--dest = *--source;\n\n\t\tyy_cp += (int) (dest - source);\n\t\tyy_bp += (int) (dest - source);\n\t\tYY_CURRENT_BUFFER_LVALUE->yy_n_chars =\n\t\t\t(yy_n_chars) = (int) YY_CURRENT_BUFFER_LVALUE->yy_buf_size;\n\n\t\tif ( yy_cp < YY_CURRENT_BUFFER_LVALUE->yy_ch_buf + 2 )\n\t\t\tYY_FATAL_ERROR( \"flex scanner push-back overflow\" );\n\t\t}\n\n\t*--yy_cp = (char) c;\n\n    if ( c == '\\n' ){\n        --yylineno;\n    }\n\n\t(yytext_ptr) = yy_bp;\n\t(yy_hold_char) = *yy_cp;\n\t(yy_c_buf_p) = yy_cp;\n}\n\n#endif\n\n#ifndef YY_NO_INPUT\n#ifdef __cplusplus\n    static int yyinput (void)\n#else\n    static int input  (void)\n#endif\n\n{\n\tint c;\n    \n\t*(yy_c_buf_p) = (yy_hold_char);\n\n\tif ( *(yy_c_buf_p) == YY_END_OF_BUFFER_CHAR )\n\t\t{\n\t\t/* yy_c_buf_p now points to the character we want to return.\n\t\t * If this occurs *before* the EOB characters, then it's a\n\t\t * valid NUL; if not, then we've hit the end of the buffer.\n\t\t */\n\t\tif ( (yy_c_buf_p) < &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars)] )\n\t\t\t/* This was really a NUL. */\n\t\t\t*(yy_c_buf_p) = '\\0';\n\n\t\telse\n\t\t\t{ /* need more input */\n\t\t\tint offset = (int) ((yy_c_buf_p) - (yytext_ptr));\n\t\t\t++(yy_c_buf_p);\n\n\t\t\tswitch ( yy_get_next_buffer(  ) )\n\t\t\t\t{\n\t\t\t\tcase EOB_ACT_LAST_MATCH:\n\t\t\t\t\t/* This happens because yy_g_n_b()\n\t\t\t\t\t * sees that we've accumulated a\n\t\t\t\t\t * token and flags that we need to\n\t\t\t\t\t * try matching the token before\n\t\t\t\t\t * proceeding.  But for input(),\n\t\t\t\t\t * there's no matching to consider.\n\t\t\t\t\t * So convert the EOB_ACT_LAST_MATCH\n\t\t\t\t\t * to EOB_ACT_END_OF_FILE.\n\t\t\t\t\t */\n\n\t\t\t\t\t/* Reset buffer status. */\n\t\t\t\t\tyyrestart( yyin );\n\n\t\t\t\t\t/*FALLTHROUGH*/\n\n\t\t\t\tcase EOB_ACT_END_OF_FILE:\n\t\t\t\t\t{\n\t\t\t\t\tif ( yywrap(  ) )\n\t\t\t\t\t\treturn 0;\n\n\t\t\t\t\tif ( ! (yy_did_buffer_switch_on_eof) )\n\t\t\t\t\t\tYY_NEW_FILE;\n#ifdef __cplusplus\n\t\t\t\t\treturn yyinput();\n#else\n\t\t\t\t\treturn input();\n#endif\n\t\t\t\t\t}\n\n\t\t\t\tcase EOB_ACT_CONTINUE_SCAN:\n\t\t\t\t\t(yy_c_buf_p) = (yytext_ptr) + offset;\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n\tc = *(unsigned char *) (yy_c_buf_p);\t/* cast for 8-bit char's */\n\t*(yy_c_buf_p) = '\\0';\t/* preserve yytext */\n\t(yy_hold_char) = *++(yy_c_buf_p);\n\n\tif ( c == '\\n' )\n\t\t\n    yylineno++;\n;\n\n\treturn c;\n}\n#endif\t/* ifndef YY_NO_INPUT */\n\n/** Immediately switch to a different input stream.\n * @param input_file A readable stream.\n * \n * @note This function does not reset the start condition to @c INITIAL .\n */\n    void yyrestart  (FILE * input_file )\n{\n    \n\tif ( ! YY_CURRENT_BUFFER ){\n        yyensure_buffer_stack ();\n\t\tYY_CURRENT_BUFFER_LVALUE =\n            yy_create_buffer( yyin, YY_BUF_SIZE );\n\t}\n\n\tyy_init_buffer( YY_CURRENT_BUFFER, input_file );\n\tyy_load_buffer_state(  );\n}\n\n/** Switch to a different input buffer.\n * @param new_buffer The new input buffer.\n * \n */\n    void yy_switch_to_buffer  (YY_BUFFER_STATE  new_buffer )\n{\n    \n\t/* TODO. We should be able to replace this entire function body\n\t * with\n\t *\t\tyypop_buffer_state();\n\t *\t\tyypush_buffer_state(new_buffer);\n     */\n\tyyensure_buffer_stack ();\n\tif ( YY_CURRENT_BUFFER == new_buffer )\n\t\treturn;\n\n\tif ( YY_CURRENT_BUFFER )\n\t\t{\n\t\t/* Flush out information for old buffer. */\n\t\t*(yy_c_buf_p) = (yy_hold_char);\n\t\tYY_CURRENT_BUFFER_LVALUE->yy_buf_pos = (yy_c_buf_p);\n\t\tYY_CURRENT_BUFFER_LVALUE->yy_n_chars = (yy_n_chars);\n\t\t}\n\n\tYY_CURRENT_BUFFER_LVALUE = new_buffer;\n\tyy_load_buffer_state(  );\n\n\t/* We don't actually know whether we did this switch during\n\t * EOF (yywrap()) processing, but the only time this flag\n\t * is looked at is after yywrap() is called, so it's safe\n\t * to go ahead and always set it.\n\t */\n\t(yy_did_buffer_switch_on_eof) = 1;\n}\n\nstatic void yy_load_buffer_state  (void)\n{\n    \t(yy_n_chars) = YY_CURRENT_BUFFER_LVALUE->yy_n_chars;\n\t(yytext_ptr) = (yy_c_buf_p) = YY_CURRENT_BUFFER_LVALUE->yy_buf_pos;\n\tyyin = YY_CURRENT_BUFFER_LVALUE->yy_input_file;\n\t(yy_hold_char) = *(yy_c_buf_p);\n}\n\n/** Allocate and initialize an input buffer state.\n * @param file A readable stream.\n * @param size The character buffer size in bytes. When in doubt, use @c YY_BUF_SIZE.\n * \n * @return the allocated buffer state.\n */\n    YY_BUFFER_STATE yy_create_buffer  (FILE * file, int  size )\n{\n\tYY_BUFFER_STATE b;\n    \n\tb = (YY_BUFFER_STATE) yyalloc( sizeof( struct yy_buffer_state )  );\n\tif ( ! b )\n\t\tYY_FATAL_ERROR( \"out of dynamic memory in yy_create_buffer()\" );\n\n\tb->yy_buf_size = size;\n\n\t/* yy_ch_buf has to be 2 characters longer than the size given because\n\t * we need to put in 2 end-of-buffer characters.\n\t */\n\tb->yy_ch_buf = (char *) yyalloc( (yy_size_t) (b->yy_buf_size + 2)  );\n\tif ( ! b->yy_ch_buf )\n\t\tYY_FATAL_ERROR( \"out of dynamic memory in yy_create_buffer()\" );\n\n\tb->yy_is_our_buffer = 1;\n\n\tyy_init_buffer( b, file );\n\n\treturn b;\n}\n\n/** Destroy the buffer.\n * @param b a buffer created with yy_create_buffer()\n * \n */\n    void yy_delete_buffer (YY_BUFFER_STATE  b )\n{\n    \n\tif ( ! b )\n\t\treturn;\n\n\tif ( b == YY_CURRENT_BUFFER ) /* Not sure if we should pop here. */\n\t\tYY_CURRENT_BUFFER_LVALUE = (YY_BUFFER_STATE) 0;\n\n\tif ( b->yy_is_our_buffer )\n\t\tyyfree( (void *) b->yy_ch_buf  );\n\n\tyyfree( (void *) b  );\n}\n\n/* Initializes or reinitializes a buffer.\n * This function is sometimes called more than once on the same buffer,\n * such as during a yyrestart() or at EOF.\n */\n    static void yy_init_buffer  (YY_BUFFER_STATE  b, FILE * file )\n\n{\n\tint oerrno = errno;\n    \n\tyy_flush_buffer( b );\n\n\tb->yy_input_file = file;\n\tb->yy_fill_buffer = 1;\n\n    /* If b is the current buffer, then yy_init_buffer was _probably_\n     * called from yyrestart() or through yy_get_next_buffer.\n     * In that case, we don't want to reset the lineno or column.\n     */\n    if (b != YY_CURRENT_BUFFER){\n        b->yy_bs_lineno = 1;\n        b->yy_bs_column = 0;\n    }\n\n        b->yy_is_interactive = 0;\n    \n\terrno = oerrno;\n}\n\n/** Discard all buffered characters. On the next scan, YY_INPUT will be called.\n * @param b the buffer state to be flushed, usually @c YY_CURRENT_BUFFER.\n * \n */\n    void yy_flush_buffer (YY_BUFFER_STATE  b )\n{\n    \tif ( ! b )\n\t\treturn;\n\n\tb->yy_n_chars = 0;\n\n\t/* We always need two end-of-buffer characters.  The first causes\n\t * a transition to the end-of-buffer state.  The second causes\n\t * a jam in that state.\n\t */\n\tb->yy_ch_buf[0] = YY_END_OF_BUFFER_CHAR;\n\tb->yy_ch_buf[1] = YY_END_OF_BUFFER_CHAR;\n\n\tb->yy_buf_pos = &b->yy_ch_buf[0];\n\n\tb->yy_at_bol = 1;\n\tb->yy_buffer_status = YY_BUFFER_NEW;\n\n\tif ( b == YY_CURRENT_BUFFER )\n\t\tyy_load_buffer_state(  );\n}\n\n/** Pushes the new state onto the stack. The new state becomes\n *  the current state. This function will allocate the stack\n *  if necessary.\n *  @param new_buffer The new state.\n *  \n */\nvoid yypush_buffer_state (YY_BUFFER_STATE new_buffer )\n{\n    \tif (new_buffer == NULL)\n\t\treturn;\n\n\tyyensure_buffer_stack();\n\n\t/* This block is copied from yy_switch_to_buffer. */\n\tif ( YY_CURRENT_BUFFER )\n\t\t{\n\t\t/* Flush out information for old buffer. */\n\t\t*(yy_c_buf_p) = (yy_hold_char);\n\t\tYY_CURRENT_BUFFER_LVALUE->yy_buf_pos = (yy_c_buf_p);\n\t\tYY_CURRENT_BUFFER_LVALUE->yy_n_chars = (yy_n_chars);\n\t\t}\n\n\t/* Only push if top exists. Otherwise, replace top. */\n\tif (YY_CURRENT_BUFFER)\n\t\t(yy_buffer_stack_top)++;\n\tYY_CURRENT_BUFFER_LVALUE = new_buffer;\n\n\t/* copied from yy_switch_to_buffer. */\n\tyy_load_buffer_state(  );\n\t(yy_did_buffer_switch_on_eof) = 1;\n}\n\n/** Removes and deletes the top of the stack, if present.\n *  The next element becomes the new top.\n *  \n */\nvoid yypop_buffer_state (void)\n{\n    \tif (!YY_CURRENT_BUFFER)\n\t\treturn;\n\n\tyy_delete_buffer(YY_CURRENT_BUFFER );\n\tYY_CURRENT_BUFFER_LVALUE = NULL;\n\tif ((yy_buffer_stack_top) > 0)\n\t\t--(yy_buffer_stack_top);\n\n\tif (YY_CURRENT_BUFFER) {\n\t\tyy_load_buffer_state(  );\n\t\t(yy_did_buffer_switch_on_eof) = 1;\n\t}\n}\n\n/* Allocates the stack if it does not exist.\n *  Guarantees space for at least one push.\n */\nstatic void yyensure_buffer_stack (void)\n{\n\tyy_size_t num_to_alloc;\n    \n\tif (!(yy_buffer_stack)) {\n\n\t\t/* First allocation is just for 2 elements, since we don't know if this\n\t\t * scanner will even need a stack. We use 2 instead of 1 to avoid an\n\t\t * immediate realloc on the next call.\n         */\n      num_to_alloc = 1; /* After all that talk, this was set to 1 anyways... */\n\t\t(yy_buffer_stack) = (struct yy_buffer_state**)yyalloc\n\t\t\t\t\t\t\t\t(num_to_alloc * sizeof(struct yy_buffer_state*)\n\t\t\t\t\t\t\t\t);\n\t\tif ( ! (yy_buffer_stack) )\n\t\t\tYY_FATAL_ERROR( \"out of dynamic memory in yyensure_buffer_stack()\" );\n\n\t\tmemset((yy_buffer_stack), 0, num_to_alloc * sizeof(struct yy_buffer_state*));\n\n\t\t(yy_buffer_stack_max) = num_to_alloc;\n\t\t(yy_buffer_stack_top) = 0;\n\t\treturn;\n\t}\n\n\tif ((yy_buffer_stack_top) >= ((yy_buffer_stack_max)) - 1){\n\n\t\t/* Increase the buffer to prepare for a possible push. */\n\t\tyy_size_t grow_size = 8 /* arbitrary grow size */;\n\n\t\tnum_to_alloc = (yy_buffer_stack_max) + grow_size;\n\t\t(yy_buffer_stack) = (struct yy_buffer_state**)yyrealloc\n\t\t\t\t\t\t\t\t((yy_buffer_stack),\n\t\t\t\t\t\t\t\tnum_to_alloc * sizeof(struct yy_buffer_state*)\n\t\t\t\t\t\t\t\t);\n\t\tif ( ! (yy_buffer_stack) )\n\t\t\tYY_FATAL_ERROR( \"out of dynamic memory in yyensure_buffer_stack()\" );\n\n\t\t/* zero only the new slots.*/\n\t\tmemset((yy_buffer_stack) + (yy_buffer_stack_max), 0, grow_size * sizeof(struct yy_buffer_state*));\n\t\t(yy_buffer_stack_max) = num_to_alloc;\n\t}\n}\n\n/** Setup the input buffer state to scan directly from a user-specified character buffer.\n * @param base the character buffer\n * @param size the size in bytes of the character buffer\n * \n * @return the newly allocated buffer state object.\n */\nYY_BUFFER_STATE yy_scan_buffer  (char * base, yy_size_t  size )\n{\n\tYY_BUFFER_STATE b;\n    \n\tif ( size < 2 ||\n\t     base[size-2] != YY_END_OF_BUFFER_CHAR ||\n\t     base[size-1] != YY_END_OF_BUFFER_CHAR )\n\t\t/* They forgot to leave room for the EOB's. */\n\t\treturn NULL;\n\n\tb = (YY_BUFFER_STATE) yyalloc( sizeof( struct yy_buffer_state )  );\n\tif ( ! b )\n\t\tYY_FATAL_ERROR( \"out of dynamic memory in yy_scan_buffer()\" );\n\n\tb->yy_buf_size = (int) (size - 2);\t/* \"- 2\" to take care of EOB's */\n\tb->yy_buf_pos = b->yy_ch_buf = base;\n\tb->yy_is_our_buffer = 0;\n\tb->yy_input_file = NULL;\n\tb->yy_n_chars = b->yy_buf_size;\n\tb->yy_is_interactive = 0;\n\tb->yy_at_bol = 1;\n\tb->yy_fill_buffer = 0;\n\tb->yy_buffer_status = YY_BUFFER_NEW;\n\n\tyy_switch_to_buffer( b  );\n\n\treturn b;\n}\n\n/** Setup the input buffer state to scan a string. The next call to yylex() will\n * scan from a @e copy of @a str.\n * @param yystr a NUL-terminated string to scan\n * \n * @return the newly allocated buffer state object.\n * @note If you want to scan bytes that may contain NUL values, then use\n *       yy_scan_bytes() instead.\n */\nYY_BUFFER_STATE yy_scan_string (const char * yystr )\n{\n    \n\treturn yy_scan_bytes( yystr, (int) strlen(yystr) );\n}\n\n/** Setup the input buffer state to scan the given bytes. The next call to yylex() will\n * scan from a @e copy of @a bytes.\n * @param yybytes the byte buffer to scan\n * @param _yybytes_len the number of bytes in the buffer pointed to by @a bytes.\n * \n * @return the newly allocated buffer state object.\n */\nYY_BUFFER_STATE yy_scan_bytes  (const char * yybytes, int  _yybytes_len )\n{\n\tYY_BUFFER_STATE b;\n\tchar *buf;\n\tyy_size_t n;\n\tint i;\n    \n\t/* Get memory for full buffer, including space for trailing EOB's. */\n\tn = (yy_size_t) (_yybytes_len + 2);\n\tbuf = (char *) yyalloc( n  );\n\tif ( ! buf )\n\t\tYY_FATAL_ERROR( \"out of dynamic memory in yy_scan_bytes()\" );\n\n\tfor ( i = 0; i < _yybytes_len; ++i )\n\t\tbuf[i] = yybytes[i];\n\n\tbuf[_yybytes_len] = buf[_yybytes_len+1] = YY_END_OF_BUFFER_CHAR;\n\n\tb = yy_scan_buffer( buf, n );\n\tif ( ! b )\n\t\tYY_FATAL_ERROR( \"bad buffer in yy_scan_bytes()\" );\n\n\t/* It's okay to grow etc. this buffer, and we should throw it\n\t * away when we're done.\n\t */\n\tb->yy_is_our_buffer = 1;\n\n\treturn b;\n}\n\n#ifndef YY_EXIT_FAILURE\n#define YY_EXIT_FAILURE 2\n#endif\n\nstatic void yynoreturn yy_fatal_error (const char* msg )\n{\n\t\t\tfprintf( stderr, \"%s\\n\", msg );\n\texit( YY_EXIT_FAILURE );\n}\n\n/* Redefine yyless() so it works in section 3 code. */\n\n#undef yyless\n#define yyless(n) \\\n\tdo \\\n\t\t{ \\\n\t\t/* Undo effects of setting up yytext. */ \\\n        int yyless_macro_arg = (n); \\\n        YY_LESS_LINENO(yyless_macro_arg);\\\n\t\tyytext[yyleng] = (yy_hold_char); \\\n\t\t(yy_c_buf_p) = yytext + yyless_macro_arg; \\\n\t\t(yy_hold_char) = *(yy_c_buf_p); \\\n\t\t*(yy_c_buf_p) = '\\0'; \\\n\t\tyyleng = yyless_macro_arg; \\\n\t\t} \\\n\twhile ( 0 )\n\n/* Accessor  methods (get/set functions) to struct members. */\n\n/** Get the current line number.\n * \n */\nint yyget_lineno  (void)\n{\n    \n    return yylineno;\n}\n\n/** Get the input stream.\n * \n */\nFILE *yyget_in  (void)\n{\n        return yyin;\n}\n\n/** Get the output stream.\n * \n */\nFILE *yyget_out  (void)\n{\n        return yyout;\n}\n\n/** Get the length of the current token.\n * \n */\nint yyget_leng  (void)\n{\n        return yyleng;\n}\n\n/** Get the current token.\n * \n */\n\nchar *yyget_text  (void)\n{\n        return yytext;\n}\n\n/** Set the current line number.\n * @param _line_number line number\n * \n */\nvoid yyset_lineno (int  _line_number )\n{\n    \n    yylineno = _line_number;\n}\n\n/** Set the input stream. This does not discard the current\n * input buffer.\n * @param _in_str A readable stream.\n * \n * @see yy_switch_to_buffer\n */\nvoid yyset_in (FILE *  _in_str )\n{\n        yyin = _in_str ;\n}\n\nvoid yyset_out (FILE *  _out_str )\n{\n        yyout = _out_str ;\n}\n\nint yyget_debug  (void)\n{\n        return yy_flex_debug;\n}\n\nvoid yyset_debug (int  _bdebug )\n{\n        yy_flex_debug = _bdebug ;\n}\n\nstatic int yy_init_globals (void)\n{\n        /* Initialization is the same as for the non-reentrant scanner.\n     * This function is called from yylex_destroy(), so don't allocate here.\n     */\n\n    /* We do not touch yylineno unless the option is enabled. */\n    yylineno =  1;\n    \n    (yy_buffer_stack) = NULL;\n    (yy_buffer_stack_top) = 0;\n    (yy_buffer_stack_max) = 0;\n    (yy_c_buf_p) = NULL;\n    (yy_init) = 0;\n    (yy_start) = 0;\n\n/* Defined in main.c */\n#ifdef YY_STDINIT\n    yyin = stdin;\n    yyout = stdout;\n#else\n    yyin = NULL;\n    yyout = NULL;\n#endif\n\n    /* For future reference: Set errno on error, since we are called by\n     * yylex_init()\n     */\n    return 0;\n}\n\n/* yylex_destroy is for both reentrant and non-reentrant scanners. */\nint yylex_destroy  (void)\n{\n    \n    /* Pop the buffer stack, destroying each element. */\n\twhile(YY_CURRENT_BUFFER){\n\t\tyy_delete_buffer( YY_CURRENT_BUFFER  );\n\t\tYY_CURRENT_BUFFER_LVALUE = NULL;\n\t\tyypop_buffer_state();\n\t}\n\n\t/* Destroy the stack itself. */\n\tyyfree((yy_buffer_stack) );\n\t(yy_buffer_stack) = NULL;\n\n    /* Reset the globals. This is important in a non-reentrant scanner so the next time\n     * yylex() is called, initialization will occur. */\n    yy_init_globals( );\n\n    return 0;\n}\n\n/*\n * Internal utility routines.\n */\n\n#ifndef yytext_ptr\nstatic void yy_flex_strncpy (char* s1, const char * s2, int n )\n{\n\t\t\n\tint i;\n\tfor ( i = 0; i < n; ++i )\n\t\ts1[i] = s2[i];\n}\n#endif\n\n#ifdef YY_NEED_STRLEN\nstatic int yy_flex_strlen (const char * s )\n{\n\tint n;\n\tfor ( n = 0; s[n]; ++n )\n\t\t;\n\n\treturn n;\n}\n#endif\n\nvoid *yyalloc (yy_size_t  size )\n{\n\t\t\treturn malloc(size);\n}\n\nvoid *yyrealloc  (void * ptr, yy_size_t  size )\n{\n\t\t\n\t/* The cast to (char *) in the following accommodates both\n\t * implementations that use char* generic pointers, and those\n\t * that use void* generic pointers.  It works with the latter\n\t * because both ANSI C and C++ allow castless assignment from\n\t * any pointer type to void*, and deal with argument conversions\n\t * as though doing an assignment.\n\t */\n\treturn realloc(ptr, size);\n}\n\nvoid yyfree (void * ptr )\n{\n\t\t\tfree( (char *) ptr );\t/* see yyrealloc() for (char *) cast */\n}\n\n#define YYTABLES_NAME \"yytables\"\n\n/* second stage lexer */\nint yylex(void)\n{\n\tint token;\n\nrepeat:\n\ttoken = yylex1();\n\n\tif (prev_token == T_EOL || prev_token == T_HELPTEXT) {\n\t\tif (token == T_EOL) {\n\t\t\t/* Do not pass unneeded T_EOL to the parser. */\n\t\t\tgoto repeat;\n\t\t} else {\n\t\t\t/*\n\t\t\t * For the parser, update file/lineno at the first token\n\t\t\t * of each statement. Generally, \\n is a statement\n\t\t\t * terminator in Kconfig, but it is not always true\n\t\t\t * because \\n could be escaped by a backslash.\n\t\t\t */\n\t\t\tcurrent_pos.file = current_file;\n\t\t\tcurrent_pos.lineno = yylineno;\n\t\t}\n\t}\n\n\tif (prev_prev_token == T_EOL && prev_token == T_WORD &&\n\t    (token == T_EQUAL || token == T_COLON_EQUAL || token == T_PLUS_EQUAL))\n\t\tBEGIN(ASSIGN_VAL);\n\n\tprev_prev_token = prev_token;\n\tprev_token = token;\n\n\treturn token;\n}\n\nstatic char *expand_token(const char *in, size_t n)\n{\n\tchar *out;\n\tint c;\n\tchar c2;\n\tconst char *rest, *end;\n\n\tnew_string();\n\tappend_string(in, n);\n\n\t/* get the whole line because we do not know the end of token. */\n\twhile ((c = input()) != EOF) {\n\t\tif (c == '\\n') {\n\t\t\tunput(c);\n\t\t\tbreak;\n\t\t}\n\t\tc2 = c;\n\t\tappend_string(&c2, 1);\n\t}\n\n\trest = text;\n\tout = expand_one_token(&rest);\n\n\t/* push back unused characters to the input stream */\n\tend = rest + strlen(rest);\n\twhile (end > rest)\n\t\tunput(*--end);\n\n\tfree(text);\n\n\treturn out;\n}\n\nstatic void append_expanded_string(const char *str)\n{\n\tconst char *end;\n\tchar *res;\n\n\tstr++;\n\n\tres = expand_dollar(&str);\n\n\t/* push back unused characters to the input stream */\n\tend = str + strlen(str);\n\twhile (end > str)\n\t\tunput(*--end);\n\n\tappend_string(res, strlen(res));\n\n\tfree(res);\n}\n\nvoid zconf_starthelp(void)\n{\n\tnew_string();\n\tlast_ts = first_ts = 0;\n\tBEGIN(HELP);\n}\n\nstatic void zconf_endhelp(void)\n{\n\tyylval.string = text;\n\tBEGIN(INITIAL);\n}\n\n/*\n * Try to open specified file with following names:\n * ./name\n * $(srctree)/name\n * The latter is used when srctree is separate from objtree\n * when compiling the kernel.\n * Return NULL if file is not found.\n */\nFILE *zconf_fopen(const char *name)\n{\n\tchar *env, fullname[PATH_MAX+1];\n\tFILE *f;\n\n\tf = fopen(name, \"r\");\n\tif (!f && name != NULL && name[0] != '/') {\n\t\tenv = getenv(SRCTREE);\n\t\tif (env) {\n\t\t\tsnprintf(fullname, sizeof(fullname),\n\t\t\t\t \"%s/%s\", env, name);\n\t\t\tf = fopen(fullname, \"r\");\n\t\t}\n\t}\n\treturn f;\n}\n\nvoid zconf_initscan(const char *name)\n{\n\tyyin = zconf_fopen(name);\n\tif (!yyin) {\n\t\tfprintf(stderr, \"can't find file %s\\n\", name);\n\t\texit(1);\n\t}\n\n\tcurrent_buf = xmalloc(sizeof(*current_buf));\n\tmemset(current_buf, 0, sizeof(*current_buf));\n\n\tcurrent_file = file_lookup(name);\n\tyylineno = 1;\n}\n\nstatic void __zconf_nextfile(const char *name)\n{\n\tstruct file *iter;\n\tstruct file *file = file_lookup(name);\n\tstruct buffer *buf = xmalloc(sizeof(*buf));\n\tmemset(buf, 0, sizeof(*buf));\n\n\tcurrent_buf->state = YY_CURRENT_BUFFER;\n\tyyin = zconf_fopen(file->name);\n\tif (!yyin) {\n\t\tfprintf(stderr, \"%s:%d: can't open file \\\"%s\\\"\\n\",\n\t\t\tzconf_curname(), zconf_lineno(), file->name);\n\t\texit(1);\n\t}\n\tyy_switch_to_buffer(yy_create_buffer(yyin, YY_BUF_SIZE));\n\tbuf->parent = current_buf;\n\tcurrent_buf = buf;\n\n\tcurrent_file->lineno = yylineno;\n\tfile->parent = current_file;\n\n\tfor (iter = current_file; iter; iter = iter->parent) {\n\t\tif (!strcmp(iter->name, file->name)) {\n\t\t\tfprintf(stderr,\n\t\t\t\t\"Recursive inclusion detected.\\n\"\n\t\t\t\t\"Inclusion path:\\n\"\n\t\t\t\t\"  current file : %s\\n\", file->name);\n\t\t\titer = file;\n\t\t\tdo {\n\t\t\t\titer = iter->parent;\n\t\t\t\tfprintf(stderr, \"  included from: %s:%d\\n\",\n\t\t\t\t\titer->name, iter->lineno - 1);\n\t\t\t} while (strcmp(iter->name, file->name));\n\t\t\texit(1);\n\t\t}\n\t}\n\n\tyylineno = 1;\n\tcurrent_file = file;\n}\n\nvoid zconf_nextfile(const char *name)\n{\n\tglob_t gl;\n\tint err;\n\tint i;\n\tchar path[PATH_MAX], *p;\n\n\terr = glob(name, GLOB_ERR | GLOB_MARK, NULL, &gl);\n\n\t/* ignore wildcard patterns that return no result */\n\tif (err == GLOB_NOMATCH && strchr(name, '*')) {\n\t\terr = 0;\n\t\tgl.gl_pathc = 0;\n\t}\n\n\tif (err == GLOB_NOMATCH) {\n\t\tp = strdup(current_file->name);\n\t\tif (p) {\n\t\t\tsnprintf(path, sizeof(path), \"%s/%s\", dirname(p), name);\n\t\t\terr = glob(path, GLOB_ERR | GLOB_MARK, NULL, &gl);\n\t\t\tfree(p);\n\t\t}\n\t}\n\n\tif (err) {\n\t\tconst char *reason = \"unknown error\";\n\n\t\tswitch (err) {\n\t\tcase GLOB_NOSPACE:\n\t\t\treason = \"out of memory\";\n\t\t\tbreak;\n\t\tcase GLOB_ABORTED:\n\t\t\treason = \"read error\";\n\t\t\tbreak;\n\t\tcase GLOB_NOMATCH:\n\t\t\treason = \"No files found\";\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tbreak;\n\t\t}\n\n\t\tprintf(\"%s:%d: glob failed: %s \\\"%s\\\"\\n\", zconf_curname(), zconf_lineno(),\n\t\t\treason, name);\n\n\t\texit(1);\n\t}\n\n\tfor (i = 0; i < gl.gl_pathc; i++)\n\t\t__zconf_nextfile(gl.gl_pathv[i]);\n}\n\nstatic void zconf_endfile(void)\n{\n\tstruct buffer *parent;\n\n\tcurrent_file = current_file->parent;\n\tif (current_file)\n\t\tyylineno = current_file->lineno;\n\n\tparent = current_buf->parent;\n\tif (parent) {\n\t\tfclose(yyin);\n\t\tyy_delete_buffer(YY_CURRENT_BUFFER);\n\t\tyy_switch_to_buffer(parent->state);\n\t}\n\tfree(current_buf);\n\tcurrent_buf = parent;\n}\n\nint zconf_lineno(void)\n{\n\treturn current_pos.lineno;\n}\n\nconst char *zconf_curname(void)\n{\n\treturn current_pos.file ? current_pos.file->name : \"<none>\";\n}\n\n"
  },
  {
    "path": "scripts/config/list.h",
    "content": "/* SPDX-License-Identifier: GPL-2.0-only */\n#ifndef LIST_H\n#define LIST_H\n\n/*\n * Copied from include/linux/...\n */\n\n#undef offsetof\n#define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER)\n\n/**\n * container_of - cast a member of a structure out to the containing structure\n * @ptr:        the pointer to the member.\n * @type:       the type of the container struct this is embedded in.\n * @member:     the name of the member within the struct.\n *\n */\n#define container_of(ptr, type, member) ({                      \\\n\tconst typeof( ((type *)0)->member ) *__mptr = (ptr);    \\\n\t(type *)( (char *)__mptr - offsetof(type,member) );})\n\n\nstruct list_head {\n\tstruct list_head *next, *prev;\n};\n\n\n#define LIST_HEAD_INIT(name) { &(name), &(name) }\n\n#define LIST_HEAD(name) \\\n\tstruct list_head name = LIST_HEAD_INIT(name)\n\n/**\n * list_entry - get the struct for this entry\n * @ptr:\tthe &struct list_head pointer.\n * @type:\tthe type of the struct this is embedded in.\n * @member:\tthe name of the list_head within the struct.\n */\n#define list_entry(ptr, type, member) \\\n\tcontainer_of(ptr, type, member)\n\n/**\n * list_for_each_entry\t-\titerate over list of given type\n * @pos:\tthe type * to use as a loop cursor.\n * @head:\tthe head for your list.\n * @member:\tthe name of the list_head within the struct.\n */\n#define list_for_each_entry(pos, head, member)\t\t\t\t\\\n\tfor (pos = list_entry((head)->next, typeof(*pos), member);\t\\\n\t     &pos->member != (head); \t\\\n\t     pos = list_entry(pos->member.next, typeof(*pos), member))\n\n/**\n * list_for_each_entry_safe - iterate over list of given type safe against removal of list entry\n * @pos:\tthe type * to use as a loop cursor.\n * @n:\t\tanother type * to use as temporary storage\n * @head:\tthe head for your list.\n * @member:\tthe name of the list_head within the struct.\n */\n#define list_for_each_entry_safe(pos, n, head, member)\t\t\t\\\n\tfor (pos = list_entry((head)->next, typeof(*pos), member),\t\\\n\t\tn = list_entry(pos->member.next, typeof(*pos), member);\t\\\n\t     &pos->member != (head);\t\t\t\t\t\\\n\t     pos = n, n = list_entry(n->member.next, typeof(*n), member))\n\n/**\n * list_empty - tests whether a list is empty\n * @head: the list to test.\n */\nstatic inline int list_empty(const struct list_head *head)\n{\n\treturn head->next == head;\n}\n\n/*\n * Insert a new entry between two known consecutive entries.\n *\n * This is only for internal list manipulation where we know\n * the prev/next entries already!\n */\nstatic inline void __list_add(struct list_head *_new,\n\t\t\t      struct list_head *prev,\n\t\t\t      struct list_head *next)\n{\n\tnext->prev = _new;\n\t_new->next = next;\n\t_new->prev = prev;\n\tprev->next = _new;\n}\n\n/**\n * list_add_tail - add a new entry\n * @new: new entry to be added\n * @head: list head to add it before\n *\n * Insert a new entry before the specified head.\n * This is useful for implementing queues.\n */\nstatic inline void list_add_tail(struct list_head *_new, struct list_head *head)\n{\n\t__list_add(_new, head->prev, head);\n}\n\n/*\n * Delete a list entry by making the prev/next entries\n * point to each other.\n *\n * This is only for internal list manipulation where we know\n * the prev/next entries already!\n */\nstatic inline void __list_del(struct list_head *prev, struct list_head *next)\n{\n\tnext->prev = prev;\n\tprev->next = next;\n}\n\n#define LIST_POISON1  ((void *) 0x00100100)\n#define LIST_POISON2  ((void *) 0x00200200)\n/**\n * list_del - deletes entry from list.\n * @entry: the element to delete from the list.\n * Note: list_empty() on entry does not return true after this, the entry is\n * in an undefined state.\n */\nstatic inline void list_del(struct list_head *entry)\n{\n\t__list_del(entry->prev, entry->next);\n\tentry->next = (struct list_head*)LIST_POISON1;\n\tentry->prev = (struct list_head*)LIST_POISON2;\n}\n#endif\n"
  },
  {
    "path": "scripts/config/lkc.h",
    "content": "/* SPDX-License-Identifier: GPL-2.0-only */\n/*\n * Copyright (C) 2002 Roman Zippel <zippel@linux-m68k.org>\n */\n\n#ifndef LKC_H\n#define LKC_H\n\n#include <assert.h>\n#include <stdio.h>\n#include <stdlib.h>\n\n#include \"expr.h\"\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#include \"lkc_proto.h\"\n\n#define SRCTREE \"srctree\"\n\n#ifndef CONFIG_\n#define CONFIG_ \"CONFIG_\"\n#endif\nstatic inline const char *CONFIG_prefix(void)\n{\n\treturn getenv( \"CONFIG_\" ) ?: CONFIG_;\n}\n#undef CONFIG_\n#define CONFIG_ CONFIG_prefix()\n\nextern int yylineno;\nvoid zconfdump(FILE *out);\nvoid zconf_starthelp(void);\nFILE *zconf_fopen(const char *name);\nvoid zconf_initscan(const char *name);\nvoid zconf_nextfile(const char *name);\nint zconf_lineno(void);\nconst char *zconf_curname(void);\nextern int recursive_is_error;\n\n/* confdata.c */\nconst char *conf_get_configname(void);\nvoid set_all_choice_values(struct symbol *csym);\n\n/* confdata.c and expr.c */\nstatic inline void xfwrite(const void *str, size_t len, size_t count, FILE *out)\n{\n\tassert(len != 0);\n\n\tif (fwrite(str, len, count, out) != count)\n\t\tfprintf(stderr, \"Error in writing or end of file.\\n\");\n}\n\n/* util.c */\nstruct file *file_lookup(const char *name);\nvoid *xmalloc(size_t size);\nvoid *xcalloc(size_t nmemb, size_t size);\nvoid *xrealloc(void *p, size_t size);\nchar *xstrdup(const char *s);\nchar *xstrndup(const char *s, size_t n);\n\n/* lexer.l */\nint yylex(void);\n\nstruct gstr {\n\tsize_t len;\n\tchar  *s;\n\t/*\n\t* when max_width is not zero long lines in string s (if any) get\n\t* wrapped not to exceed the max_width value\n\t*/\n\tint max_width;\n};\nstruct gstr str_new(void);\nvoid str_free(struct gstr *gs);\nvoid str_append(struct gstr *gs, const char *s);\nvoid str_printf(struct gstr *gs, const char *fmt, ...);\nconst char *str_get(struct gstr *gs);\n\n/* menu.c */\nvoid _menu_init(void);\nvoid menu_warn(struct menu *menu, const char *fmt, ...);\nstruct menu *menu_add_menu(void);\nvoid menu_end_menu(void);\nvoid menu_add_entry(struct symbol *sym);\nvoid menu_add_dep(struct expr *dep);\nvoid menu_add_visibility(struct expr *dep);\nstruct property *menu_add_prop(enum prop_type type, struct expr *expr, struct expr *dep);\nstruct property *menu_add_prompt(enum prop_type type, char *prompt, struct expr *dep);\nvoid menu_add_expr(enum prop_type type, struct expr *expr, struct expr *dep);\nvoid menu_add_symbol(enum prop_type type, struct symbol *sym, struct expr *dep);\nvoid menu_finalize(struct menu *parent);\nvoid menu_set_type(int type);\n\nextern struct menu rootmenu;\n\nbool menu_is_empty(struct menu *menu);\nbool menu_is_visible(struct menu *menu);\nbool menu_has_prompt(struct menu *menu);\nconst char *menu_get_prompt(struct menu *menu);\nstruct menu *menu_get_root_menu(struct menu *menu);\nstruct menu *menu_get_parent_menu(struct menu *menu);\nbool menu_has_help(struct menu *menu);\nconst char *menu_get_help(struct menu *menu);\nstruct gstr get_relations_str(struct symbol **sym_arr, struct list_head *head);\nvoid menu_get_ext_help(struct menu *menu, struct gstr *help);\n\n/* symbol.c */\nvoid sym_clear_all_valid(void);\nstruct symbol *sym_choice_default(struct symbol *sym);\nstruct property *sym_get_range_prop(struct symbol *sym);\nconst char *sym_get_string_default(struct symbol *sym);\nstruct symbol *sym_check_deps(struct symbol *sym);\nstruct symbol *prop_get_symbol(struct property *prop);\n\nstatic inline tristate sym_get_tristate_value(struct symbol *sym)\n{\n\treturn sym->curr.tri;\n}\n\n\nstatic inline struct symbol *sym_get_choice_value(struct symbol *sym)\n{\n\treturn (struct symbol *)sym->curr.val;\n}\n\nstatic inline bool sym_set_choice_value(struct symbol *ch, struct symbol *chval)\n{\n\treturn sym_set_tristate_value(chval, yes);\n}\n\nstatic inline bool sym_is_choice(struct symbol *sym)\n{\n\treturn sym->flags & SYMBOL_CHOICE ? true : false;\n}\n\nstatic inline bool sym_is_choice_value(struct symbol *sym)\n{\n\treturn sym->flags & SYMBOL_CHOICEVAL ? true : false;\n}\n\nstatic inline bool sym_is_optional(struct symbol *sym)\n{\n\treturn sym->flags & SYMBOL_OPTIONAL ? true : false;\n}\n\nstatic inline bool sym_has_value(struct symbol *sym)\n{\n\treturn sym->flags & SYMBOL_DEF_USER ? true : false;\n}\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* LKC_H */\n"
  },
  {
    "path": "scripts/config/lkc_proto.h",
    "content": "/* SPDX-License-Identifier: GPL-2.0-only */\n#include <stdarg.h>\n\n/* confdata.c */\nvoid conf_parse(const char *name);\nint conf_read(const char *name);\nint conf_read_simple(const char *name, int);\nvoid conf_reset(int def);\nint conf_write_defconfig(const char *name);\nint conf_write(const char *name);\nint conf_write_autoconf(int overwrite);\nvoid conf_set_changed(bool val);\nbool conf_get_changed(void);\nvoid conf_set_changed_callback(void (*fn)(void));\nvoid conf_set_message_callback(void (*fn)(const char *s));\n\n/* symbol.c */\nextern struct symbol * symbol_hash[SYMBOL_HASHSIZE];\n\nstruct symbol * sym_lookup(const char *name, int flags);\nstruct symbol * sym_find(const char *name);\nconst char * sym_escape_string_value(const char *in);\nstruct symbol ** sym_re_search(const char *pattern);\nconst char * sym_type_name(enum symbol_type type);\nvoid sym_calc_value(struct symbol *sym);\nenum symbol_type sym_get_type(struct symbol *sym);\nbool sym_tristate_within_range(struct symbol *sym,tristate tri);\nbool sym_set_tristate_value(struct symbol *sym,tristate tri);\ntristate sym_toggle_tristate_value(struct symbol *sym);\nbool sym_string_valid(struct symbol *sym, const char *newval);\nbool sym_string_within_range(struct symbol *sym, const char *str);\nbool sym_set_string_value(struct symbol *sym, const char *newval);\nbool sym_is_changeable(struct symbol *sym);\nstruct property * sym_get_choice_prop(struct symbol *sym);\nconst char * sym_get_string_value(struct symbol *sym);\n\nconst char * prop_get_type_name(enum prop_type type);\n\n/* preprocess.c */\nenum variable_flavor {\n\tVAR_SIMPLE,\n\tVAR_RECURSIVE,\n\tVAR_APPEND,\n};\nvoid env_write_dep(FILE *f, const char *auto_conf_name);\nvoid variable_add(const char *name, const char *value,\n\t\t  enum variable_flavor flavor);\nvoid variable_all_del(void);\nchar *expand_dollar(const char **str);\nchar *expand_one_token(const char **str);\n\n/* expr.c */\nvoid expr_print(struct expr *e, void (*fn)(void *, struct symbol *, const char *), void *data, int prevtoken);\n"
  },
  {
    "path": "scripts/config/lxdialog/checklist.c",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later\n/*\n *  checklist.c -- implements the checklist box\n *\n *  ORIGINAL AUTHOR: Savio Lam (lam836@cs.cuhk.hk)\n *     Stuart Herbert - S.Herbert@sheffield.ac.uk: radiolist extension\n *     Alessandro Rubini - rubini@ipvvis.unipv.it: merged the two\n *  MODIFIED FOR LINUX KERNEL CONFIG BY: William Roadcap (roadcap@cfw.com)\n */\n\n#include \"dialog.h\"\n\nstatic int list_width, check_x, item_x;\n\n/*\n * Print list item\n */\nstatic void print_item(WINDOW * win, int choice, int selected)\n{\n\tint i;\n\tchar *list_item = malloc(list_width + 1);\n\n\tstrncpy(list_item, item_str(), list_width - item_x);\n\tlist_item[list_width - item_x] = '\\0';\n\n\t/* Clear 'residue' of last item */\n\twattrset(win, dlg.menubox.atr);\n\twmove(win, choice, 0);\n\tfor (i = 0; i < list_width; i++)\n\t\twaddch(win, ' ');\n\n\twmove(win, choice, check_x);\n\twattrset(win, selected ? dlg.check_selected.atr\n\t\t : dlg.check.atr);\n\tif (!item_is_tag(':'))\n\t\twprintw(win, \"(%c)\", item_is_tag('X') ? 'X' : ' ');\n\n\twattrset(win, selected ? dlg.tag_selected.atr : dlg.tag.atr);\n\tmvwaddch(win, choice, item_x, list_item[0]);\n\twattrset(win, selected ? dlg.item_selected.atr : dlg.item.atr);\n\twaddstr(win, list_item + 1);\n\tif (selected) {\n\t\twmove(win, choice, check_x + 1);\n\t\twrefresh(win);\n\t}\n\tfree(list_item);\n}\n\n/*\n * Print the scroll indicators.\n */\nstatic void print_arrows(WINDOW * win, int choice, int item_no, int scroll,\n\t     int y, int x, int height)\n{\n\twmove(win, y, x);\n\n\tif (scroll > 0) {\n\t\twattrset(win, dlg.uarrow.atr);\n\t\twaddch(win, ACS_UARROW);\n\t\twaddstr(win, \"(-)\");\n\t} else {\n\t\twattrset(win, dlg.menubox.atr);\n\t\twaddch(win, ACS_HLINE);\n\t\twaddch(win, ACS_HLINE);\n\t\twaddch(win, ACS_HLINE);\n\t\twaddch(win, ACS_HLINE);\n\t}\n\n\ty = y + height + 1;\n\twmove(win, y, x);\n\n\tif ((height < item_no) && (scroll + choice < item_no - 1)) {\n\t\twattrset(win, dlg.darrow.atr);\n\t\twaddch(win, ACS_DARROW);\n\t\twaddstr(win, \"(+)\");\n\t} else {\n\t\twattrset(win, dlg.menubox_border.atr);\n\t\twaddch(win, ACS_HLINE);\n\t\twaddch(win, ACS_HLINE);\n\t\twaddch(win, ACS_HLINE);\n\t\twaddch(win, ACS_HLINE);\n\t}\n}\n\n/*\n *  Display the termination buttons\n */\nstatic void print_buttons(WINDOW * dialog, int height, int width, int selected)\n{\n\tint x = width / 2 - 11;\n\tint y = height - 2;\n\n\tprint_button(dialog, \"Select\", y, x, selected == 0);\n\tprint_button(dialog, \" Help \", y, x + 14, selected == 1);\n\n\twmove(dialog, y, x + 1 + 14 * selected);\n\twrefresh(dialog);\n}\n\n/*\n * Display a dialog box with a list of options that can be turned on or off\n * in the style of radiolist (only one option turned on at a time).\n */\nint dialog_checklist(const char *title, const char *prompt, int height,\n\t\t     int width, int list_height)\n{\n\tint i, x, y, box_x, box_y;\n\tint key = 0, button = 0, choice = 0, scroll = 0, max_choice;\n\tWINDOW *dialog, *list;\n\n\t/* which item to highlight */\n\titem_foreach() {\n\t\tif (item_is_tag('X'))\n\t\t\tchoice = item_n();\n\t\tif (item_is_selected()) {\n\t\t\tchoice = item_n();\n\t\t\tbreak;\n\t\t}\n\t}\n\ndo_resize:\n\tif (getmaxy(stdscr) < (height + CHECKLIST_HEIGTH_MIN))\n\t\treturn -ERRDISPLAYTOOSMALL;\n\tif (getmaxx(stdscr) < (width + CHECKLIST_WIDTH_MIN))\n\t\treturn -ERRDISPLAYTOOSMALL;\n\n\tmax_choice = MIN(list_height, item_count());\n\n\t/* center dialog box on screen */\n\tx = (getmaxx(stdscr) - width) / 2;\n\ty = (getmaxy(stdscr) - height) / 2;\n\n\tdraw_shadow(stdscr, y, x, height, width);\n\n\tdialog = newwin(height, width, y, x);\n\tkeypad(dialog, TRUE);\n\n\tdraw_box(dialog, 0, 0, height, width,\n\t\t dlg.dialog.atr, dlg.border.atr);\n\twattrset(dialog, dlg.border.atr);\n\tmvwaddch(dialog, height - 3, 0, ACS_LTEE);\n\tfor (i = 0; i < width - 2; i++)\n\t\twaddch(dialog, ACS_HLINE);\n\twattrset(dialog, dlg.dialog.atr);\n\twaddch(dialog, ACS_RTEE);\n\n\tprint_title(dialog, title, width);\n\n\twattrset(dialog, dlg.dialog.atr);\n\tprint_autowrap(dialog, prompt, width - 2, 1, 3);\n\n\tlist_width = width - 6;\n\tbox_y = height - list_height - 5;\n\tbox_x = (width - list_width) / 2 - 1;\n\n\t/* create new window for the list */\n\tlist = subwin(dialog, list_height, list_width, y + box_y + 1,\n\t\t      x + box_x + 1);\n\n\tkeypad(list, TRUE);\n\n\t/* draw a box around the list items */\n\tdraw_box(dialog, box_y, box_x, list_height + 2, list_width + 2,\n\t\t dlg.menubox_border.atr, dlg.menubox.atr);\n\n\t/* Find length of longest item in order to center checklist */\n\tcheck_x = 0;\n\titem_foreach()\n\t\tcheck_x = MAX(check_x, strlen(item_str()) + 4);\n\tcheck_x = MIN(check_x, list_width);\n\n\tcheck_x = (list_width - check_x) / 2;\n\titem_x = check_x + 4;\n\n\tif (choice >= list_height) {\n\t\tscroll = choice - list_height + 1;\n\t\tchoice -= scroll;\n\t}\n\n\t/* Print the list */\n\tfor (i = 0; i < max_choice; i++) {\n\t\titem_set(scroll + i);\n\t\tprint_item(list, i, i == choice);\n\t}\n\n\tprint_arrows(dialog, choice, item_count(), scroll,\n\t\t     box_y, box_x + check_x + 5, list_height);\n\n\tprint_buttons(dialog, height, width, 0);\n\n\twnoutrefresh(dialog);\n\twnoutrefresh(list);\n\tdoupdate();\n\n\twhile (key != KEY_ESC) {\n\t\tkey = wgetch(dialog);\n\n\t\tfor (i = 0; i < max_choice; i++) {\n\t\t\titem_set(i + scroll);\n\t\t\tif (toupper(key) == toupper(item_str()[0]))\n\t\t\t\tbreak;\n\t\t}\n\n\t\tif (i < max_choice || key == KEY_UP || key == KEY_DOWN ||\n\t\t    key == '+' || key == '-') {\n\t\t\tif (key == KEY_UP || key == '-') {\n\t\t\t\tif (!choice) {\n\t\t\t\t\tif (!scroll)\n\t\t\t\t\t\tcontinue;\n\t\t\t\t\t/* Scroll list down */\n\t\t\t\t\tif (list_height > 1) {\n\t\t\t\t\t\t/* De-highlight current first item */\n\t\t\t\t\t\titem_set(scroll);\n\t\t\t\t\t\tprint_item(list, 0, FALSE);\n\t\t\t\t\t\tscrollok(list, TRUE);\n\t\t\t\t\t\twscrl(list, -1);\n\t\t\t\t\t\tscrollok(list, FALSE);\n\t\t\t\t\t}\n\t\t\t\t\tscroll--;\n\t\t\t\t\titem_set(scroll);\n\t\t\t\t\tprint_item(list, 0, TRUE);\n\t\t\t\t\tprint_arrows(dialog, choice, item_count(),\n\t\t\t\t\t\t     scroll, box_y, box_x + check_x + 5, list_height);\n\n\t\t\t\t\twnoutrefresh(dialog);\n\t\t\t\t\twrefresh(list);\n\n\t\t\t\t\tcontinue;\t/* wait for another key press */\n\t\t\t\t} else\n\t\t\t\t\ti = choice - 1;\n\t\t\t} else if (key == KEY_DOWN || key == '+') {\n\t\t\t\tif (choice == max_choice - 1) {\n\t\t\t\t\tif (scroll + choice >= item_count() - 1)\n\t\t\t\t\t\tcontinue;\n\t\t\t\t\t/* Scroll list up */\n\t\t\t\t\tif (list_height > 1) {\n\t\t\t\t\t\t/* De-highlight current last item before scrolling up */\n\t\t\t\t\t\titem_set(scroll + max_choice - 1);\n\t\t\t\t\t\tprint_item(list,\n\t\t\t\t\t\t\t    max_choice - 1,\n\t\t\t\t\t\t\t    FALSE);\n\t\t\t\t\t\tscrollok(list, TRUE);\n\t\t\t\t\t\twscrl(list, 1);\n\t\t\t\t\t\tscrollok(list, FALSE);\n\t\t\t\t\t}\n\t\t\t\t\tscroll++;\n\t\t\t\t\titem_set(scroll + max_choice - 1);\n\t\t\t\t\tprint_item(list, max_choice - 1, TRUE);\n\n\t\t\t\t\tprint_arrows(dialog, choice, item_count(),\n\t\t\t\t\t\t     scroll, box_y, box_x + check_x + 5, list_height);\n\n\t\t\t\t\twnoutrefresh(dialog);\n\t\t\t\t\twrefresh(list);\n\n\t\t\t\t\tcontinue;\t/* wait for another key press */\n\t\t\t\t} else\n\t\t\t\t\ti = choice + 1;\n\t\t\t}\n\t\t\tif (i != choice) {\n\t\t\t\t/* De-highlight current item */\n\t\t\t\titem_set(scroll + choice);\n\t\t\t\tprint_item(list, choice, FALSE);\n\t\t\t\t/* Highlight new item */\n\t\t\t\tchoice = i;\n\t\t\t\titem_set(scroll + choice);\n\t\t\t\tprint_item(list, choice, TRUE);\n\t\t\t\twnoutrefresh(dialog);\n\t\t\t\twrefresh(list);\n\t\t\t}\n\t\t\tcontinue;\t/* wait for another key press */\n\t\t}\n\t\tswitch (key) {\n\t\tcase 'H':\n\t\tcase 'h':\n\t\tcase '?':\n\t\t\tbutton = 1;\n\t\t\t/* fall-through */\n\t\tcase 'S':\n\t\tcase 's':\n\t\tcase ' ':\n\t\tcase '\\n':\n\t\t\titem_foreach()\n\t\t\t\titem_set_selected(0);\n\t\t\titem_set(scroll + choice);\n\t\t\titem_set_selected(1);\n\t\t\tdelwin(list);\n\t\t\tdelwin(dialog);\n\t\t\treturn button;\n\t\tcase TAB:\n\t\tcase KEY_LEFT:\n\t\tcase KEY_RIGHT:\n\t\t\tbutton = ((key == KEY_LEFT ? --button : ++button) < 0)\n\t\t\t    ? 1 : (button > 1 ? 0 : button);\n\n\t\t\tprint_buttons(dialog, height, width, button);\n\t\t\twrefresh(dialog);\n\t\t\tbreak;\n\t\tcase 'X':\n\t\tcase 'x':\n\t\t\tkey = KEY_ESC;\n\t\t\tbreak;\n\t\tcase KEY_ESC:\n\t\t\tkey = on_key_esc(dialog);\n\t\t\tbreak;\n\t\tcase KEY_RESIZE:\n\t\t\tdelwin(list);\n\t\t\tdelwin(dialog);\n\t\t\ton_key_resize();\n\t\t\tgoto do_resize;\n\t\t}\n\n\t\t/* Now, update everything... */\n\t\tdoupdate();\n\t}\n\tdelwin(list);\n\tdelwin(dialog);\n\treturn key;\t\t/* ESC pressed */\n}\n"
  },
  {
    "path": "scripts/config/lxdialog/dialog.h",
    "content": "/* SPDX-License-Identifier: GPL-2.0-or-later */\n/*\n *  dialog.h -- common declarations for all dialog modules\n *\n *  AUTHOR: Savio Lam (lam836@cs.cuhk.hk)\n */\n\n#include <sys/types.h>\n#include <fcntl.h>\n#include <unistd.h>\n#include <ctype.h>\n#include <stdlib.h>\n#include <string.h>\n#include <stdbool.h>\n\n#ifdef __sun__\n#define CURS_MACROS\n#endif\n#include <ncurses.h>\n\n/*\n * Colors in ncurses 1.9.9e do not work properly since foreground and\n * background colors are OR'd rather than separately masked.  This version\n * of dialog was hacked to work with ncurses 1.9.9e, making it incompatible\n * with standard curses.  The simplest fix (to make this work with standard\n * curses) uses the wbkgdset() function, not used in the original hack.\n * Turn it off if we're building with 1.9.9e, since it just confuses things.\n */\n#if defined(NCURSES_VERSION) && defined(_NEED_WRAP) && !defined(GCC_PRINTFLIKE)\n#define OLD_NCURSES 1\n#undef  wbkgdset\n#define wbkgdset(w,p)\t\t/*nothing */\n#else\n#define OLD_NCURSES 0\n#endif\n\n#define TR(params) _tracef params\n\n#define KEY_ESC 27\n#define TAB 9\n#define MAX_LEN 2048\n#define BUF_SIZE (10*1024)\n#define MIN(x,y) (x < y ? x : y)\n#define MAX(x,y) (x > y ? x : y)\n\n#ifndef ACS_ULCORNER\n#define ACS_ULCORNER '+'\n#endif\n#ifndef ACS_LLCORNER\n#define ACS_LLCORNER '+'\n#endif\n#ifndef ACS_URCORNER\n#define ACS_URCORNER '+'\n#endif\n#ifndef ACS_LRCORNER\n#define ACS_LRCORNER '+'\n#endif\n#ifndef ACS_HLINE\n#define ACS_HLINE '-'\n#endif\n#ifndef ACS_VLINE\n#define ACS_VLINE '|'\n#endif\n#ifndef ACS_LTEE\n#define ACS_LTEE '+'\n#endif\n#ifndef ACS_RTEE\n#define ACS_RTEE '+'\n#endif\n#ifndef ACS_UARROW\n#define ACS_UARROW '^'\n#endif\n#ifndef ACS_DARROW\n#define ACS_DARROW 'v'\n#endif\n\n/* error return codes */\n#define ERRDISPLAYTOOSMALL (KEY_MAX + 1)\n\n/*\n *   Color definitions\n */\nstruct dialog_color {\n\tchtype atr;\t/* Color attribute */\n\tint fg;\t\t/* foreground */\n\tint bg;\t\t/* background */\n\tint hl;\t\t/* highlight this item */\n};\n\nstruct subtitle_list {\n\tstruct subtitle_list *next;\n\tconst char *text;\n};\n\nstruct dialog_info {\n\tconst char *backtitle;\n\tstruct subtitle_list *subtitles;\n\tstruct dialog_color screen;\n\tstruct dialog_color shadow;\n\tstruct dialog_color dialog;\n\tstruct dialog_color title;\n\tstruct dialog_color border;\n\tstruct dialog_color button_active;\n\tstruct dialog_color button_inactive;\n\tstruct dialog_color button_key_active;\n\tstruct dialog_color button_key_inactive;\n\tstruct dialog_color button_label_active;\n\tstruct dialog_color button_label_inactive;\n\tstruct dialog_color inputbox;\n\tstruct dialog_color inputbox_border;\n\tstruct dialog_color searchbox;\n\tstruct dialog_color searchbox_title;\n\tstruct dialog_color searchbox_border;\n\tstruct dialog_color position_indicator;\n\tstruct dialog_color menubox;\n\tstruct dialog_color menubox_border;\n\tstruct dialog_color item;\n\tstruct dialog_color item_selected;\n\tstruct dialog_color tag;\n\tstruct dialog_color tag_selected;\n\tstruct dialog_color tag_key;\n\tstruct dialog_color tag_key_selected;\n\tstruct dialog_color check;\n\tstruct dialog_color check_selected;\n\tstruct dialog_color uarrow;\n\tstruct dialog_color darrow;\n};\n\n/*\n * Global variables\n */\nextern struct dialog_info dlg;\nextern char dialog_input_result[];\nextern int saved_x, saved_y;\t\t/* Needed in signal handler in mconf.c */\n\n/*\n * Function prototypes\n */\n\n/* item list as used by checklist and menubox */\nvoid item_reset(void);\nvoid item_make(const char *fmt, ...);\nvoid item_add_str(const char *fmt, ...);\nvoid item_set_tag(char tag);\nvoid item_set_data(void *p);\nvoid item_set_selected(int val);\nint item_activate_selected(void);\nvoid *item_data(void);\nchar item_tag(void);\n\n/* item list manipulation for lxdialog use */\n#define MAXITEMSTR 200\nstruct dialog_item {\n\tchar str[MAXITEMSTR];\t/* prompt displayed */\n\tchar tag;\n\tvoid *data;\t/* pointer to menu item - used by menubox+checklist */\n\tint selected;\t/* Set to 1 by dialog_*() function if selected. */\n};\n\n/* list of lialog_items */\nstruct dialog_list {\n\tstruct dialog_item node;\n\tstruct dialog_list *next;\n};\n\nextern struct dialog_list *item_cur;\nextern struct dialog_list item_nil;\nextern struct dialog_list *item_head;\n\nint item_count(void);\nvoid item_set(int n);\nint item_n(void);\nconst char *item_str(void);\nint item_is_selected(void);\nint item_is_tag(char tag);\n#define item_foreach() \\\n\tfor (item_cur = item_head ? item_head: item_cur; \\\n\t     item_cur && (item_cur != &item_nil); item_cur = item_cur->next)\n\n/* generic key handlers */\nint on_key_esc(WINDOW *win);\nint on_key_resize(void);\n\n/* minimum (re)size values */\n#define CHECKLIST_HEIGTH_MIN 6\t/* For dialog_checklist() */\n#define CHECKLIST_WIDTH_MIN 6\n#define INPUTBOX_HEIGTH_MIN 2\t/* For dialog_inputbox() */\n#define INPUTBOX_WIDTH_MIN 2\n#define MENUBOX_HEIGTH_MIN 15\t/* For dialog_menu() */\n#define MENUBOX_WIDTH_MIN 65\n#define TEXTBOX_HEIGTH_MIN 8\t/* For dialog_textbox() */\n#define TEXTBOX_WIDTH_MIN 8\n#define YESNO_HEIGTH_MIN 4\t/* For dialog_yesno() */\n#define YESNO_WIDTH_MIN 4\n#define WINDOW_HEIGTH_MIN 19\t/* For init_dialog() */\n#define WINDOW_WIDTH_MIN 80\n\nint init_dialog(const char *backtitle);\nvoid set_dialog_backtitle(const char *backtitle);\nvoid set_dialog_subtitles(struct subtitle_list *subtitles);\nvoid end_dialog(int x, int y);\nvoid attr_clear(WINDOW * win, int height, int width, chtype attr);\nvoid dialog_clear(void);\nvoid print_autowrap(WINDOW * win, const char *prompt, int width, int y, int x);\nvoid print_button(WINDOW * win, const char *label, int y, int x, int selected);\nvoid print_title(WINDOW *dialog, const char *title, int width);\nvoid draw_box(WINDOW * win, int y, int x, int height, int width, chtype box,\n\t      chtype border);\nvoid draw_shadow(WINDOW * win, int y, int x, int height, int width);\n\nint first_alpha(const char *string, const char *exempt);\nint dialog_yesno(const char *title, const char *prompt, int height, int width);\nint dialog_msgbox(const char *title, const char *prompt, int height,\n\t\t  int width, int pause);\n\n\ntypedef void (*update_text_fn)(char *buf, size_t start, size_t end, void\n\t\t\t       *_data);\nint dialog_textbox(const char *title, char *tbuf, int initial_height,\n\t\t   int initial_width, int *keys, int *_vscroll, int *_hscroll,\n\t\t   update_text_fn update_text, void *data);\nint dialog_menu(const char *title, const char *prompt,\n\t\tconst void *selected, int *s_scroll);\nint dialog_checklist(const char *title, const char *prompt, int height,\n\t\t     int width, int list_height);\nint dialog_inputbox(const char *title, const char *prompt, int height,\n\t\t    int width, const char *init);\n\n/*\n * This is the base for fictitious keys, which activate\n * the buttons.\n *\n * Mouse-generated keys are the following:\n *   -- the first 32 are used as numbers, in addition to '0'-'9'\n *   -- the lowercase are used to signal mouse-enter events (M_EVENT + 'o')\n *   -- uppercase chars are used to invoke the button (M_EVENT + 'O')\n */\n#define M_EVENT (KEY_MAX+1)\n"
  },
  {
    "path": "scripts/config/lxdialog/inputbox.c",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later\n/*\n *  inputbox.c -- implements the input box\n *\n *  ORIGINAL AUTHOR: Savio Lam (lam836@cs.cuhk.hk)\n *  MODIFIED FOR LINUX KERNEL CONFIG BY: William Roadcap (roadcap@cfw.com)\n */\n\n#include \"dialog.h\"\n\nchar dialog_input_result[MAX_LEN + 1];\n\n/*\n *  Print the termination buttons\n */\nstatic void print_buttons(WINDOW * dialog, int height, int width, int selected)\n{\n\tint x = width / 2 - 11;\n\tint y = height - 2;\n\n\tprint_button(dialog, \"  Ok  \", y, x, selected == 0);\n\tprint_button(dialog, \" Help \", y, x + 14, selected == 1);\n\n\twmove(dialog, y, x + 1 + 14 * selected);\n\twrefresh(dialog);\n}\n\n/*\n * Display a dialog box for inputing a string\n */\nint dialog_inputbox(const char *title, const char *prompt, int height, int width,\n\t\t    const char *init)\n{\n\tint i, x, y, box_y, box_x, box_width;\n\tint input_x = 0, key = 0, button = -1;\n\tint show_x, len, pos;\n\tchar *instr = dialog_input_result;\n\tWINDOW *dialog;\n\n\tif (!init)\n\t\tinstr[0] = '\\0';\n\telse\n\t\tstrcpy(instr, init);\n\ndo_resize:\n\tif (getmaxy(stdscr) <= (height - INPUTBOX_HEIGTH_MIN))\n\t\treturn -ERRDISPLAYTOOSMALL;\n\tif (getmaxx(stdscr) <= (width - INPUTBOX_WIDTH_MIN))\n\t\treturn -ERRDISPLAYTOOSMALL;\n\n\t/* center dialog box on screen */\n\tx = (getmaxx(stdscr) - width) / 2;\n\ty = (getmaxy(stdscr) - height) / 2;\n\n\tdraw_shadow(stdscr, y, x, height, width);\n\n\tdialog = newwin(height, width, y, x);\n\tkeypad(dialog, TRUE);\n\n\tdraw_box(dialog, 0, 0, height, width,\n\t\t dlg.dialog.atr, dlg.border.atr);\n\twattrset(dialog, dlg.border.atr);\n\tmvwaddch(dialog, height - 3, 0, ACS_LTEE);\n\tfor (i = 0; i < width - 2; i++)\n\t\twaddch(dialog, ACS_HLINE);\n\twattrset(dialog, dlg.dialog.atr);\n\twaddch(dialog, ACS_RTEE);\n\n\tprint_title(dialog, title, width);\n\n\twattrset(dialog, dlg.dialog.atr);\n\tprint_autowrap(dialog, prompt, width - 2, 1, 3);\n\n\t/* Draw the input field box */\n\tbox_width = width - 6;\n\tgetyx(dialog, y, x);\n\tbox_y = y + 2;\n\tbox_x = (width - box_width) / 2;\n\tdraw_box(dialog, y + 1, box_x - 1, 3, box_width + 2,\n\t\t dlg.dialog.atr, dlg.border.atr);\n\n\tprint_buttons(dialog, height, width, 0);\n\n\t/* Set up the initial value */\n\twmove(dialog, box_y, box_x);\n\twattrset(dialog, dlg.inputbox.atr);\n\n\tlen = strlen(instr);\n\tpos = len;\n\n\tif (len >= box_width) {\n\t\tshow_x = len - box_width + 1;\n\t\tinput_x = box_width - 1;\n\t\tfor (i = 0; i < box_width - 1; i++)\n\t\t\twaddch(dialog, instr[show_x + i]);\n\t} else {\n\t\tshow_x = 0;\n\t\tinput_x = len;\n\t\twaddstr(dialog, instr);\n\t}\n\n\twmove(dialog, box_y, box_x + input_x);\n\n\twrefresh(dialog);\n\n\twhile (key != KEY_ESC) {\n\t\tkey = wgetch(dialog);\n\n\t\tif (button == -1) {\t/* Input box selected */\n\t\t\tswitch (key) {\n\t\t\tcase TAB:\n\t\t\tcase KEY_UP:\n\t\t\tcase KEY_DOWN:\n\t\t\t\tbreak;\n\t\t\tcase KEY_BACKSPACE:\n\t\t\tcase 8:   /* ^H */\n\t\t\tcase 127: /* ^? */\n\t\t\t\tif (pos) {\n\t\t\t\t\twattrset(dialog, dlg.inputbox.atr);\n\t\t\t\t\tif (input_x == 0) {\n\t\t\t\t\t\tshow_x--;\n\t\t\t\t\t} else\n\t\t\t\t\t\tinput_x--;\n\n\t\t\t\t\tif (pos < len) {\n\t\t\t\t\t\tfor (i = pos - 1; i < len; i++) {\n\t\t\t\t\t\t\tinstr[i] = instr[i+1];\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\n\t\t\t\t\tpos--;\n\t\t\t\t\tlen--;\n\t\t\t\t\tinstr[len] = '\\0';\n\t\t\t\t\twmove(dialog, box_y, box_x);\n\t\t\t\t\tfor (i = 0; i < box_width; i++) {\n\t\t\t\t\t\tif (!instr[show_x + i]) {\n\t\t\t\t\t\t\twaddch(dialog, ' ');\n\t\t\t\t\t\t\tbreak;\n\t\t\t\t\t\t}\n\t\t\t\t\t\twaddch(dialog, instr[show_x + i]);\n\t\t\t\t\t}\n\t\t\t\t\twmove(dialog, box_y, input_x + box_x);\n\t\t\t\t\twrefresh(dialog);\n\t\t\t\t}\n\t\t\t\tcontinue;\n\t\t\tcase KEY_LEFT:\n\t\t\t\tif (pos > 0) {\n\t\t\t\t\tif (input_x > 0) {\n\t\t\t\t\t\twmove(dialog, box_y, --input_x + box_x);\n\t\t\t\t\t} else if (input_x == 0) {\n\t\t\t\t\t\tshow_x--;\n\t\t\t\t\t\twmove(dialog, box_y, box_x);\n\t\t\t\t\t\tfor (i = 0; i < box_width; i++) {\n\t\t\t\t\t\t\tif (!instr[show_x + i]) {\n\t\t\t\t\t\t\t\twaddch(dialog, ' ');\n\t\t\t\t\t\t\t\tbreak;\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\twaddch(dialog, instr[show_x + i]);\n\t\t\t\t\t\t}\n\t\t\t\t\t\twmove(dialog, box_y, box_x);\n\t\t\t\t\t}\n\t\t\t\t\tpos--;\n\t\t\t\t}\n\t\t\t\tcontinue;\n\t\t\tcase KEY_RIGHT:\n\t\t\t\tif (pos < len) {\n\t\t\t\t\tif (input_x < box_width - 1) {\n\t\t\t\t\t\twmove(dialog, box_y, ++input_x + box_x);\n\t\t\t\t\t} else if (input_x == box_width - 1) {\n\t\t\t\t\t\tshow_x++;\n\t\t\t\t\t\twmove(dialog, box_y, box_x);\n\t\t\t\t\t\tfor (i = 0; i < box_width; i++) {\n\t\t\t\t\t\t\tif (!instr[show_x + i]) {\n\t\t\t\t\t\t\t\twaddch(dialog, ' ');\n\t\t\t\t\t\t\t\tbreak;\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\twaddch(dialog, instr[show_x + i]);\n\t\t\t\t\t\t}\n\t\t\t\t\t\twmove(dialog, box_y, input_x + box_x);\n\t\t\t\t\t}\n\t\t\t\t\tpos++;\n\t\t\t\t}\n\t\t\t\tcontinue;\n\t\t\tdefault:\n\t\t\t\tif (key < 0x100 && isprint(key)) {\n\t\t\t\t\tif (len < MAX_LEN) {\n\t\t\t\t\t\twattrset(dialog, dlg.inputbox.atr);\n\t\t\t\t\t\tif (pos < len) {\n\t\t\t\t\t\t\tfor (i = len; i > pos; i--)\n\t\t\t\t\t\t\t\tinstr[i] = instr[i-1];\n\t\t\t\t\t\t\tinstr[pos] = key;\n\t\t\t\t\t\t} else {\n\t\t\t\t\t\t\tinstr[len] = key;\n\t\t\t\t\t\t}\n\t\t\t\t\t\tpos++;\n\t\t\t\t\t\tlen++;\n\t\t\t\t\t\tinstr[len] = '\\0';\n\n\t\t\t\t\t\tif (input_x == box_width - 1) {\n\t\t\t\t\t\t\tshow_x++;\n\t\t\t\t\t\t} else {\n\t\t\t\t\t\t\tinput_x++;\n\t\t\t\t\t\t}\n\n\t\t\t\t\t\twmove(dialog, box_y, box_x);\n\t\t\t\t\t\tfor (i = 0; i < box_width; i++) {\n\t\t\t\t\t\t\tif (!instr[show_x + i]) {\n\t\t\t\t\t\t\t\twaddch(dialog, ' ');\n\t\t\t\t\t\t\t\tbreak;\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\twaddch(dialog, instr[show_x + i]);\n\t\t\t\t\t\t}\n\t\t\t\t\t\twmove(dialog, box_y, input_x + box_x);\n\t\t\t\t\t\twrefresh(dialog);\n\t\t\t\t\t} else\n\t\t\t\t\t\tflash();\t/* Alarm user about overflow */\n\t\t\t\t\tcontinue;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t\tswitch (key) {\n\t\tcase 'O':\n\t\tcase 'o':\n\t\t\tdelwin(dialog);\n\t\t\treturn 0;\n\t\tcase 'H':\n\t\tcase 'h':\n\t\t\tdelwin(dialog);\n\t\t\treturn 1;\n\t\tcase KEY_UP:\n\t\tcase KEY_LEFT:\n\t\t\tswitch (button) {\n\t\t\tcase -1:\n\t\t\t\tbutton = 1;\t/* Indicates \"Help\" button is selected */\n\t\t\t\tprint_buttons(dialog, height, width, 1);\n\t\t\t\tbreak;\n\t\t\tcase 0:\n\t\t\t\tbutton = -1;\t/* Indicates input box is selected */\n\t\t\t\tprint_buttons(dialog, height, width, 0);\n\t\t\t\twmove(dialog, box_y, box_x + input_x);\n\t\t\t\twrefresh(dialog);\n\t\t\t\tbreak;\n\t\t\tcase 1:\n\t\t\t\tbutton = 0;\t/* Indicates \"OK\" button is selected */\n\t\t\t\tprint_buttons(dialog, height, width, 0);\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\tbreak;\n\t\tcase TAB:\n\t\tcase KEY_DOWN:\n\t\tcase KEY_RIGHT:\n\t\t\tswitch (button) {\n\t\t\tcase -1:\n\t\t\t\tbutton = 0;\t/* Indicates \"OK\" button is selected */\n\t\t\t\tprint_buttons(dialog, height, width, 0);\n\t\t\t\tbreak;\n\t\t\tcase 0:\n\t\t\t\tbutton = 1;\t/* Indicates \"Help\" button is selected */\n\t\t\t\tprint_buttons(dialog, height, width, 1);\n\t\t\t\tbreak;\n\t\t\tcase 1:\n\t\t\t\tbutton = -1;\t/* Indicates input box is selected */\n\t\t\t\tprint_buttons(dialog, height, width, 0);\n\t\t\t\twmove(dialog, box_y, box_x + input_x);\n\t\t\t\twrefresh(dialog);\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\tbreak;\n\t\tcase ' ':\n\t\tcase '\\n':\n\t\t\tdelwin(dialog);\n\t\t\treturn (button == -1 ? 0 : button);\n\t\tcase 'X':\n\t\tcase 'x':\n\t\t\tkey = KEY_ESC;\n\t\t\tbreak;\n\t\tcase KEY_ESC:\n\t\t\tkey = on_key_esc(dialog);\n\t\t\tbreak;\n\t\tcase KEY_RESIZE:\n\t\t\tdelwin(dialog);\n\t\t\ton_key_resize();\n\t\t\tgoto do_resize;\n\t\t}\n\t}\n\n\tdelwin(dialog);\n\treturn KEY_ESC;\t\t/* ESC pressed */\n}\n"
  },
  {
    "path": "scripts/config/lxdialog/menubox.c",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later\n/*\n *  menubox.c -- implements the menu box\n *\n *  ORIGINAL AUTHOR: Savio Lam (lam836@cs.cuhk.hk)\n *  MODIFIED FOR LINUX KERNEL CONFIG BY: William Roadcap (roadcapw@cfw.com)\n */\n\n/*\n *  Changes by Clifford Wolf (god@clifford.at)\n *\n *  [ 1998-06-13 ]\n *\n *    *)  A bugfix for the Page-Down problem\n *\n *    *)  Formerly when I used Page Down and Page Up, the cursor would be set\n *        to the first position in the menu box.  Now lxdialog is a bit\n *        smarter and works more like other menu systems (just have a look at\n *        it).\n *\n *    *)  Formerly if I selected something my scrolling would be broken because\n *        lxdialog is re-invoked by the Menuconfig shell script, can't\n *        remember the last scrolling position, and just sets it so that the\n *        cursor is at the bottom of the box.  Now it writes the temporary file\n *        lxdialog.scrltmp which contains this information. The file is\n *        deleted by lxdialog if the user leaves a submenu or enters a new\n *        one, but it would be nice if Menuconfig could make another \"rm -f\"\n *        just to be sure.  Just try it out - you will recognise a difference!\n *\n *  [ 1998-06-14 ]\n *\n *    *)  Now lxdialog is crash-safe against broken \"lxdialog.scrltmp\" files\n *        and menus change their size on the fly.\n *\n *    *)  If for some reason the last scrolling position is not saved by\n *        lxdialog, it sets the scrolling so that the selected item is in the\n *        middle of the menu box, not at the bottom.\n *\n * 02 January 1999, Michael Elizabeth Chastain (mec@shout.net)\n * Reset 'scroll' to 0 if the value from lxdialog.scrltmp is bogus.\n * This fixes a bug in Menuconfig where using ' ' to descend into menus\n * would leave mis-synchronized lxdialog.scrltmp files lying around,\n * fscanf would read in 'scroll', and eventually that value would get used.\n */\n\n#include \"dialog.h\"\n\nstatic int menu_width, item_x;\n\n/*\n * Print menu item\n */\nstatic void do_print_item(WINDOW * win, const char *item, int line_y,\n\t\t\t  int selected, int hotkey)\n{\n\tint j;\n\tchar *menu_item = malloc(menu_width + 1);\n\n\tstrncpy(menu_item, item, menu_width - item_x);\n\tmenu_item[menu_width - item_x] = '\\0';\n\tj = first_alpha(menu_item, \"YyNnMmHh\");\n\n\t/* Clear 'residue' of last item */\n\twattrset(win, dlg.menubox.atr);\n\twmove(win, line_y, 0);\n#if OLD_NCURSES\n\t{\n\t\tint i;\n\t\tfor (i = 0; i < menu_width; i++)\n\t\t\twaddch(win, ' ');\n\t}\n#else\n\twclrtoeol(win);\n#endif\n\twattrset(win, selected ? dlg.item_selected.atr : dlg.item.atr);\n\tmvwaddstr(win, line_y, item_x, menu_item);\n\tif (hotkey) {\n\t\twattrset(win, selected ? dlg.tag_key_selected.atr\n\t\t\t : dlg.tag_key.atr);\n\t\tmvwaddch(win, line_y, item_x + j, menu_item[j]);\n\t}\n\tif (selected) {\n\t\twmove(win, line_y, item_x + 1);\n\t}\n\tfree(menu_item);\n\twrefresh(win);\n}\n\n#define print_item(index, choice, selected)\t\t\t\t\\\ndo {\t\t\t\t\t\t\t\t\t\\\n\titem_set(index);\t\t\t\t\t\t\\\n\tdo_print_item(menu, item_str(), choice, selected, !item_is_tag(':')); \\\n} while (0)\n\n/*\n * Print the scroll indicators.\n */\nstatic void print_arrows(WINDOW * win, int item_no, int scroll, int y, int x,\n\t\t\t int height)\n{\n\tint cur_y, cur_x;\n\n\tgetyx(win, cur_y, cur_x);\n\n\twmove(win, y, x);\n\n\tif (scroll > 0) {\n\t\twattrset(win, dlg.uarrow.atr);\n\t\twaddch(win, ACS_UARROW);\n\t\twaddstr(win, \"(-)\");\n\t} else {\n\t\twattrset(win, dlg.menubox.atr);\n\t\twaddch(win, ACS_HLINE);\n\t\twaddch(win, ACS_HLINE);\n\t\twaddch(win, ACS_HLINE);\n\t\twaddch(win, ACS_HLINE);\n\t}\n\n\ty = y + height + 1;\n\twmove(win, y, x);\n\twrefresh(win);\n\n\tif ((height < item_no) && (scroll + height < item_no)) {\n\t\twattrset(win, dlg.darrow.atr);\n\t\twaddch(win, ACS_DARROW);\n\t\twaddstr(win, \"(+)\");\n\t} else {\n\t\twattrset(win, dlg.menubox_border.atr);\n\t\twaddch(win, ACS_HLINE);\n\t\twaddch(win, ACS_HLINE);\n\t\twaddch(win, ACS_HLINE);\n\t\twaddch(win, ACS_HLINE);\n\t}\n\n\twmove(win, cur_y, cur_x);\n\twrefresh(win);\n}\n\n/*\n * Display the termination buttons.\n */\nstatic void print_buttons(WINDOW * win, int height, int width, int selected)\n{\n\tint x = width / 2 - 28;\n\tint y = height - 2;\n\n\tprint_button(win, \"Select\", y, x, selected == 0);\n\tprint_button(win, \" Exit \", y, x + 12, selected == 1);\n\tprint_button(win, \" Help \", y, x + 24, selected == 2);\n\tprint_button(win, \" Save \", y, x + 36, selected == 3);\n\tprint_button(win, \" Load \", y, x + 48, selected == 4);\n\n\twmove(win, y, x + 1 + 12 * selected);\n\twrefresh(win);\n}\n\n/* scroll up n lines (n may be negative) */\nstatic void do_scroll(WINDOW *win, int *scroll, int n)\n{\n\t/* Scroll menu up */\n\tscrollok(win, TRUE);\n\twscrl(win, n);\n\tscrollok(win, FALSE);\n\t*scroll = *scroll + n;\n\twrefresh(win);\n}\n\n/*\n * Display a menu for choosing among a number of options\n */\nint dialog_menu(const char *title, const char *prompt,\n\t\tconst void *selected, int *s_scroll)\n{\n\tint i, j, x, y, box_x, box_y;\n\tint height, width, menu_height;\n\tint key = 0, button = 0, scroll = 0, choice = 0;\n\tint first_item =  0, max_choice;\n\tWINDOW *dialog, *menu;\n\ndo_resize:\n\theight = getmaxy(stdscr);\n\twidth = getmaxx(stdscr);\n\tif (height < MENUBOX_HEIGTH_MIN || width < MENUBOX_WIDTH_MIN)\n\t\treturn -ERRDISPLAYTOOSMALL;\n\n\theight -= 4;\n\twidth  -= 5;\n\tmenu_height = height - 10;\n\n\tmax_choice = MIN(menu_height, item_count());\n\n\t/* center dialog box on screen */\n\tx = (getmaxx(stdscr) - width) / 2;\n\ty = (getmaxy(stdscr) - height) / 2;\n\n\tdraw_shadow(stdscr, y, x, height, width);\n\n\tdialog = newwin(height, width, y, x);\n\tkeypad(dialog, TRUE);\n\n\tdraw_box(dialog, 0, 0, height, width,\n\t\t dlg.dialog.atr, dlg.border.atr);\n\twattrset(dialog, dlg.border.atr);\n\tmvwaddch(dialog, height - 3, 0, ACS_LTEE);\n\tfor (i = 0; i < width - 2; i++)\n\t\twaddch(dialog, ACS_HLINE);\n\twattrset(dialog, dlg.dialog.atr);\n\twbkgdset(dialog, dlg.dialog.atr & A_COLOR);\n\twaddch(dialog, ACS_RTEE);\n\n\tprint_title(dialog, title, width);\n\n\twattrset(dialog, dlg.dialog.atr);\n\tprint_autowrap(dialog, prompt, width - 2, 1, 3);\n\n\tmenu_width = width - 6;\n\tbox_y = height - menu_height - 5;\n\tbox_x = (width - menu_width) / 2 - 1;\n\n\t/* create new window for the menu */\n\tmenu = subwin(dialog, menu_height, menu_width,\n\t\t      y + box_y + 1, x + box_x + 1);\n\tkeypad(menu, TRUE);\n\n\t/* draw a box around the menu items */\n\tdraw_box(dialog, box_y, box_x, menu_height + 2, menu_width + 2,\n\t\t dlg.menubox_border.atr, dlg.menubox.atr);\n\n\tif (menu_width >= 80)\n\t\titem_x = (menu_width - 70) / 2;\n\telse\n\t\titem_x = 4;\n\n\t/* Set choice to default item */\n\titem_foreach()\n\t\tif (selected && (selected == item_data()))\n\t\t\tchoice = item_n();\n\t/* get the saved scroll info */\n\tscroll = *s_scroll;\n\tif ((scroll <= choice) && (scroll + max_choice > choice) &&\n\t   (scroll >= 0) && (scroll + max_choice <= item_count())) {\n\t\tfirst_item = scroll;\n\t\tchoice = choice - scroll;\n\t} else {\n\t\tscroll = 0;\n\t}\n\tif ((choice >= max_choice)) {\n\t\tif (choice >= item_count() - max_choice / 2)\n\t\t\tscroll = first_item = item_count() - max_choice;\n\t\telse\n\t\t\tscroll = first_item = choice - max_choice / 2;\n\t\tchoice = choice - scroll;\n\t}\n\n\t/* Print the menu */\n\tfor (i = 0; i < max_choice; i++) {\n\t\tprint_item(first_item + i, i, i == choice);\n\t}\n\n\twnoutrefresh(menu);\n\n\tprint_arrows(dialog, item_count(), scroll,\n\t\t     box_y, box_x + item_x + 1, menu_height);\n\n\tprint_buttons(dialog, height, width, 0);\n\twmove(menu, choice, item_x + 1);\n\twrefresh(menu);\n\n\twhile (key != KEY_ESC) {\n\t\tkey = wgetch(menu);\n\n\t\tif (key < 256 && isalpha(key))\n\t\t\tkey = tolower(key);\n\n\t\tif (strchr(\"ynmh\", key))\n\t\t\ti = max_choice;\n\t\telse {\n\t\t\tfor (i = choice + 1; i < max_choice; i++) {\n\t\t\t\titem_set(scroll + i);\n\t\t\t\tj = first_alpha(item_str(), \"YyNnMmHh\");\n\t\t\t\tif (key == tolower(item_str()[j]))\n\t\t\t\t\tbreak;\n\t\t\t}\n\t\t\tif (i == max_choice)\n\t\t\t\tfor (i = 0; i < max_choice; i++) {\n\t\t\t\t\titem_set(scroll + i);\n\t\t\t\t\tj = first_alpha(item_str(), \"YyNnMmHh\");\n\t\t\t\t\tif (key == tolower(item_str()[j]))\n\t\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t}\n\n\t\tif (item_count() != 0 &&\n\t\t    (i < max_choice ||\n\t\t     key == KEY_UP || key == KEY_DOWN ||\n\t\t     key == '-' || key == '+' ||\n\t\t     key == KEY_PPAGE || key == KEY_NPAGE)) {\n\t\t\t/* Remove highligt of current item */\n\t\t\tprint_item(scroll + choice, choice, FALSE);\n\n\t\t\tif (key == KEY_UP || key == '-') {\n\t\t\t\tif (choice < 2 && scroll) {\n\t\t\t\t\t/* Scroll menu down */\n\t\t\t\t\tdo_scroll(menu, &scroll, -1);\n\n\t\t\t\t\tprint_item(scroll, 0, FALSE);\n\t\t\t\t} else\n\t\t\t\t\tchoice = MAX(choice - 1, 0);\n\n\t\t\t} else if (key == KEY_DOWN || key == '+') {\n\t\t\t\tprint_item(scroll+choice, choice, FALSE);\n\n\t\t\t\tif ((choice > max_choice - 3) &&\n\t\t\t\t    (scroll + max_choice < item_count())) {\n\t\t\t\t\t/* Scroll menu up */\n\t\t\t\t\tdo_scroll(menu, &scroll, 1);\n\n\t\t\t\t\tprint_item(scroll+max_choice - 1,\n\t\t\t\t\t\t   max_choice - 1, FALSE);\n\t\t\t\t} else\n\t\t\t\t\tchoice = MIN(choice + 1, max_choice - 1);\n\n\t\t\t} else if (key == KEY_PPAGE) {\n\t\t\t\tscrollok(menu, TRUE);\n\t\t\t\tfor (i = 0; (i < max_choice); i++) {\n\t\t\t\t\tif (scroll > 0) {\n\t\t\t\t\t\tdo_scroll(menu, &scroll, -1);\n\t\t\t\t\t\tprint_item(scroll, 0, FALSE);\n\t\t\t\t\t} else {\n\t\t\t\t\t\tif (choice > 0)\n\t\t\t\t\t\t\tchoice--;\n\t\t\t\t\t}\n\t\t\t\t}\n\n\t\t\t} else if (key == KEY_NPAGE) {\n\t\t\t\tfor (i = 0; (i < max_choice); i++) {\n\t\t\t\t\tif (scroll + max_choice < item_count()) {\n\t\t\t\t\t\tdo_scroll(menu, &scroll, 1);\n\t\t\t\t\t\tprint_item(scroll+max_choice-1,\n\t\t\t\t\t\t\t   max_choice - 1, FALSE);\n\t\t\t\t\t} else {\n\t\t\t\t\t\tif (choice + 1 < max_choice)\n\t\t\t\t\t\t\tchoice++;\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t} else\n\t\t\t\tchoice = i;\n\n\t\t\tprint_item(scroll + choice, choice, TRUE);\n\n\t\t\tprint_arrows(dialog, item_count(), scroll,\n\t\t\t\t     box_y, box_x + item_x + 1, menu_height);\n\n\t\t\twnoutrefresh(dialog);\n\t\t\twrefresh(menu);\n\n\t\t\tcontinue;\t/* wait for another key press */\n\t\t}\n\n\t\tswitch (key) {\n\t\tcase KEY_LEFT:\n\t\tcase TAB:\n\t\tcase KEY_RIGHT:\n\t\t\tbutton = ((key == KEY_LEFT ? --button : ++button) < 0)\n\t\t\t    ? 4 : (button > 4 ? 0 : button);\n\n\t\t\tprint_buttons(dialog, height, width, button);\n\t\t\twrefresh(menu);\n\t\t\tbreak;\n\t\tcase ' ':\n\t\tcase 's':\n\t\tcase 'y':\n\t\tcase 'n':\n\t\tcase 'm':\n\t\tcase '/':\n\t\tcase 'h':\n\t\tcase '?':\n\t\tcase 'z':\n\t\tcase '\\n':\n\t\t\t/* save scroll info */\n\t\t\t*s_scroll = scroll;\n\t\t\tdelwin(menu);\n\t\t\tdelwin(dialog);\n\t\t\titem_set(scroll + choice);\n\t\t\titem_set_selected(1);\n\t\t\tswitch (key) {\n\t\t\tcase 'h':\n\t\t\tcase '?':\n\t\t\t\treturn 2;\n\t\t\tcase 's':\n\t\t\tcase 'y':\n\t\t\t\treturn 5;\n\t\t\tcase 'n':\n\t\t\t\treturn 6;\n\t\t\tcase 'm':\n\t\t\t\treturn 7;\n\t\t\tcase ' ':\n\t\t\t\treturn 8;\n\t\t\tcase '/':\n\t\t\t\treturn 9;\n\t\t\tcase 'z':\n\t\t\t\treturn 10;\n\t\t\tcase '\\n':\n\t\t\t\treturn button;\n\t\t\t}\n\t\t\treturn 0;\n\t\tcase 'e':\n\t\tcase 'x':\n\t\t\tkey = KEY_ESC;\n\t\t\tbreak;\n\t\tcase KEY_ESC:\n\t\t\tkey = on_key_esc(menu);\n\t\t\tbreak;\n\t\tcase KEY_RESIZE:\n\t\t\ton_key_resize();\n\t\t\tdelwin(menu);\n\t\t\tdelwin(dialog);\n\t\t\tgoto do_resize;\n\t\t}\n\t}\n\tdelwin(menu);\n\tdelwin(dialog);\n\treturn key;\t\t/* ESC pressed */\n}\n"
  },
  {
    "path": "scripts/config/lxdialog/textbox.c",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later\n/*\n *  textbox.c -- implements the text box\n *\n *  ORIGINAL AUTHOR: Savio Lam (lam836@cs.cuhk.hk)\n *  MODIFIED FOR LINUX KERNEL CONFIG BY: William Roadcap (roadcap@cfw.com)\n */\n\n#include \"dialog.h\"\n\nstatic void back_lines(int n);\nstatic void print_page(WINDOW *win, int height, int width, update_text_fn\n\t\t       update_text, void *data);\nstatic void print_line(WINDOW *win, int row, int width);\nstatic char *get_line(void);\nstatic void print_position(WINDOW * win);\n\nstatic int hscroll;\nstatic int begin_reached, end_reached, page_length;\nstatic char *buf;\nstatic char *page;\n\n/*\n * refresh window content\n */\nstatic void refresh_text_box(WINDOW *dialog, WINDOW *box, int boxh, int boxw,\n\t\t\t     int cur_y, int cur_x, update_text_fn update_text,\n\t\t\t     void *data)\n{\n\tprint_page(box, boxh, boxw, update_text, data);\n\tprint_position(dialog);\n\twmove(dialog, cur_y, cur_x);\t/* Restore cursor position */\n\twrefresh(dialog);\n}\n\n\n/*\n * Display text from a file in a dialog box.\n *\n * keys is a null-terminated array\n * update_text() may not add or remove any '\\n' or '\\0' in tbuf\n */\nint dialog_textbox(const char *title, char *tbuf, int initial_height,\n\t\t   int initial_width, int *keys, int *_vscroll, int *_hscroll,\n\t\t   update_text_fn update_text, void *data)\n{\n\tint i, x, y, cur_x, cur_y, key = 0;\n\tint height, width, boxh, boxw;\n\tWINDOW *dialog, *box;\n\tbool done = false;\n\n\tbegin_reached = 1;\n\tend_reached = 0;\n\tpage_length = 0;\n\thscroll = 0;\n\tbuf = tbuf;\n\tpage = buf;\t/* page is pointer to start of page to be displayed */\n\n\tif (_vscroll && *_vscroll) {\n\t\tbegin_reached = 0;\n\n\t\tfor (i = 0; i < *_vscroll; i++)\n\t\t\tget_line();\n\t}\n\tif (_hscroll)\n\t\thscroll = *_hscroll;\n\ndo_resize:\n\tgetmaxyx(stdscr, height, width);\n\tif (height < TEXTBOX_HEIGTH_MIN || width < TEXTBOX_WIDTH_MIN)\n\t\treturn -ERRDISPLAYTOOSMALL;\n\tif (initial_height != 0)\n\t\theight = initial_height;\n\telse\n\t\tif (height > 4)\n\t\t\theight -= 4;\n\t\telse\n\t\t\theight = 0;\n\tif (initial_width != 0)\n\t\twidth = initial_width;\n\telse\n\t\tif (width > 5)\n\t\t\twidth -= 5;\n\t\telse\n\t\t\twidth = 0;\n\n\t/* center dialog box on screen */\n\tx = (getmaxx(stdscr) - width) / 2;\n\ty = (getmaxy(stdscr) - height) / 2;\n\n\tdraw_shadow(stdscr, y, x, height, width);\n\n\tdialog = newwin(height, width, y, x);\n\tkeypad(dialog, TRUE);\n\n\t/* Create window for box region, used for scrolling text */\n\tboxh = height - 4;\n\tboxw = width - 2;\n\tbox = subwin(dialog, boxh, boxw, y + 1, x + 1);\n\twattrset(box, dlg.dialog.atr);\n\twbkgdset(box, dlg.dialog.atr & A_COLOR);\n\n\tkeypad(box, TRUE);\n\n\t/* register the new window, along with its borders */\n\tdraw_box(dialog, 0, 0, height, width,\n\t\t dlg.dialog.atr, dlg.border.atr);\n\n\twattrset(dialog, dlg.border.atr);\n\tmvwaddch(dialog, height - 3, 0, ACS_LTEE);\n\tfor (i = 0; i < width - 2; i++)\n\t\twaddch(dialog, ACS_HLINE);\n\twattrset(dialog, dlg.dialog.atr);\n\twbkgdset(dialog, dlg.dialog.atr & A_COLOR);\n\twaddch(dialog, ACS_RTEE);\n\n\tprint_title(dialog, title, width);\n\n\tprint_button(dialog, \" Exit \", height - 2, width / 2 - 4, TRUE);\n\twnoutrefresh(dialog);\n\tgetyx(dialog, cur_y, cur_x);\t/* Save cursor position */\n\n\t/* Print first page of text */\n\tattr_clear(box, boxh, boxw, dlg.dialog.atr);\n\trefresh_text_box(dialog, box, boxh, boxw, cur_y, cur_x, update_text,\n\t\t\t data);\n\n\twhile (!done) {\n\t\tkey = wgetch(dialog);\n\t\tswitch (key) {\n\t\tcase 'E':\t/* Exit */\n\t\tcase 'e':\n\t\tcase 'X':\n\t\tcase 'x':\n\t\tcase 'q':\n\t\tcase '\\n':\n\t\t\tdone = true;\n\t\t\tbreak;\n\t\tcase 'g':\t/* First page */\n\t\tcase KEY_HOME:\n\t\t\tif (!begin_reached) {\n\t\t\t\tbegin_reached = 1;\n\t\t\t\tpage = buf;\n\t\t\t\trefresh_text_box(dialog, box, boxh, boxw,\n\t\t\t\t\t\t cur_y, cur_x, update_text,\n\t\t\t\t\t\t data);\n\t\t\t}\n\t\t\tbreak;\n\t\tcase 'G':\t/* Last page */\n\t\tcase KEY_END:\n\n\t\t\tend_reached = 1;\n\t\t\t/* point to last char in buf */\n\t\t\tpage = buf + strlen(buf);\n\t\t\tback_lines(boxh);\n\t\t\trefresh_text_box(dialog, box, boxh, boxw, cur_y,\n\t\t\t\t\t cur_x, update_text, data);\n\t\t\tbreak;\n\t\tcase 'K':\t/* Previous line */\n\t\tcase 'k':\n\t\tcase KEY_UP:\n\t\t\tif (begin_reached)\n\t\t\t\tbreak;\n\n\t\t\tback_lines(page_length + 1);\n\t\t\trefresh_text_box(dialog, box, boxh, boxw, cur_y,\n\t\t\t\t\t cur_x, update_text, data);\n\t\t\tbreak;\n\t\tcase 'B':\t/* Previous page */\n\t\tcase 'b':\n\t\tcase 'u':\n\t\tcase KEY_PPAGE:\n\t\t\tif (begin_reached)\n\t\t\t\tbreak;\n\t\t\tback_lines(page_length + boxh);\n\t\t\trefresh_text_box(dialog, box, boxh, boxw, cur_y,\n\t\t\t\t\t cur_x, update_text, data);\n\t\t\tbreak;\n\t\tcase 'J':\t/* Next line */\n\t\tcase 'j':\n\t\tcase KEY_DOWN:\n\t\t\tif (end_reached)\n\t\t\t\tbreak;\n\n\t\t\tback_lines(page_length - 1);\n\t\t\trefresh_text_box(dialog, box, boxh, boxw, cur_y,\n\t\t\t\t\t cur_x, update_text, data);\n\t\t\tbreak;\n\t\tcase KEY_NPAGE:\t/* Next page */\n\t\tcase ' ':\n\t\tcase 'd':\n\t\t\tif (end_reached)\n\t\t\t\tbreak;\n\n\t\t\tbegin_reached = 0;\n\t\t\trefresh_text_box(dialog, box, boxh, boxw, cur_y,\n\t\t\t\t\t cur_x, update_text, data);\n\t\t\tbreak;\n\t\tcase '0':\t/* Beginning of line */\n\t\tcase 'H':\t/* Scroll left */\n\t\tcase 'h':\n\t\tcase KEY_LEFT:\n\t\t\tif (hscroll <= 0)\n\t\t\t\tbreak;\n\n\t\t\tif (key == '0')\n\t\t\t\thscroll = 0;\n\t\t\telse\n\t\t\t\thscroll--;\n\t\t\t/* Reprint current page to scroll horizontally */\n\t\t\tback_lines(page_length);\n\t\t\trefresh_text_box(dialog, box, boxh, boxw, cur_y,\n\t\t\t\t\t cur_x, update_text, data);\n\t\t\tbreak;\n\t\tcase 'L':\t/* Scroll right */\n\t\tcase 'l':\n\t\tcase KEY_RIGHT:\n\t\t\tif (hscroll >= MAX_LEN)\n\t\t\t\tbreak;\n\t\t\thscroll++;\n\t\t\t/* Reprint current page to scroll horizontally */\n\t\t\tback_lines(page_length);\n\t\t\trefresh_text_box(dialog, box, boxh, boxw, cur_y,\n\t\t\t\t\t cur_x, update_text, data);\n\t\t\tbreak;\n\t\tcase KEY_ESC:\n\t\t\tif (on_key_esc(dialog) == KEY_ESC)\n\t\t\t\tdone = true;\n\t\t\tbreak;\n\t\tcase KEY_RESIZE:\n\t\t\tback_lines(height);\n\t\t\tdelwin(box);\n\t\t\tdelwin(dialog);\n\t\t\ton_key_resize();\n\t\t\tgoto do_resize;\n\t\tdefault:\n\t\t\tfor (i = 0; keys[i]; i++) {\n\t\t\t\tif (key == keys[i]) {\n\t\t\t\t\tdone = true;\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n\tdelwin(box);\n\tdelwin(dialog);\n\tif (_vscroll) {\n\t\tconst char *s;\n\n\t\ts = buf;\n\t\t*_vscroll = 0;\n\t\tback_lines(page_length);\n\t\twhile (s < page && (s = strchr(s, '\\n'))) {\n\t\t\t(*_vscroll)++;\n\t\t\ts++;\n\t\t}\n\t}\n\tif (_hscroll)\n\t\t*_hscroll = hscroll;\n\treturn key;\n}\n\n/*\n * Go back 'n' lines in text. Called by dialog_textbox().\n * 'page' will be updated to point to the desired line in 'buf'.\n */\nstatic void back_lines(int n)\n{\n\tint i;\n\n\tbegin_reached = 0;\n\t/* Go back 'n' lines */\n\tfor (i = 0; i < n; i++) {\n\t\tif (*page == '\\0') {\n\t\t\tif (end_reached) {\n\t\t\t\tend_reached = 0;\n\t\t\t\tcontinue;\n\t\t\t}\n\t\t}\n\t\tif (page == buf) {\n\t\t\tbegin_reached = 1;\n\t\t\treturn;\n\t\t}\n\t\tpage--;\n\t\tdo {\n\t\t\tif (page == buf) {\n\t\t\t\tbegin_reached = 1;\n\t\t\t\treturn;\n\t\t\t}\n\t\t\tpage--;\n\t\t} while (*page != '\\n');\n\t\tpage++;\n\t}\n}\n\n/*\n * Print a new page of text.\n */\nstatic void print_page(WINDOW *win, int height, int width, update_text_fn\n\t\t       update_text, void *data)\n{\n\tint i, passed_end = 0;\n\n\tif (update_text) {\n\t\tchar *end;\n\n\t\tfor (i = 0; i < height; i++)\n\t\t\tget_line();\n\t\tend = page;\n\t\tback_lines(height);\n\t\tupdate_text(buf, page - buf, end - buf, data);\n\t}\n\n\tpage_length = 0;\n\tfor (i = 0; i < height; i++) {\n\t\tprint_line(win, i, width);\n\t\tif (!passed_end)\n\t\t\tpage_length++;\n\t\tif (end_reached && !passed_end)\n\t\t\tpassed_end = 1;\n\t}\n\twnoutrefresh(win);\n}\n\n/*\n * Print a new line of text.\n */\nstatic void print_line(WINDOW * win, int row, int width)\n{\n\tchar *line;\n\n\tline = get_line();\n\tline += MIN(strlen(line), hscroll);\t/* Scroll horizontally */\n\twmove(win, row, 0);\t/* move cursor to correct line */\n\twaddch(win, ' ');\n\twaddnstr(win, line, MIN(strlen(line), width - 2));\n\n\t/* Clear 'residue' of previous line */\n#if OLD_NCURSES\n\t{\n\t\tint x = getcurx(win);\n\t\tint i;\n\t\tfor (i = 0; i < width - x; i++)\n\t\t\twaddch(win, ' ');\n\t}\n#else\n\twclrtoeol(win);\n#endif\n}\n\n/*\n * Return current line of text. Called by dialog_textbox() and print_line().\n * 'page' should point to start of current line before calling, and will be\n * updated to point to start of next line.\n */\nstatic char *get_line(void)\n{\n\tint i = 0;\n\tstatic char line[MAX_LEN + 1];\n\n\tend_reached = 0;\n\twhile (*page != '\\n') {\n\t\tif (*page == '\\0') {\n\t\t\tend_reached = 1;\n\t\t\tbreak;\n\t\t} else if (i < MAX_LEN)\n\t\t\tline[i++] = *(page++);\n\t\telse {\n\t\t\t/* Truncate lines longer than MAX_LEN characters */\n\t\t\tif (i == MAX_LEN)\n\t\t\t\tline[i++] = '\\0';\n\t\t\tpage++;\n\t\t}\n\t}\n\tif (i <= MAX_LEN)\n\t\tline[i] = '\\0';\n\tif (!end_reached)\n\t\tpage++;\t\t/* move past '\\n' */\n\n\treturn line;\n}\n\n/*\n * Print current position\n */\nstatic void print_position(WINDOW * win)\n{\n\tint percent;\n\n\twattrset(win, dlg.position_indicator.atr);\n\twbkgdset(win, dlg.position_indicator.atr & A_COLOR);\n\tpercent = (page - buf) * 100 / strlen(buf);\n\twmove(win, getmaxy(win) - 3, getmaxx(win) - 9);\n\twprintw(win, \"(%3d%%)\", percent);\n}\n"
  },
  {
    "path": "scripts/config/lxdialog/util.c",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later\n/*\n *  util.c\n *\n *  ORIGINAL AUTHOR: Savio Lam (lam836@cs.cuhk.hk)\n *  MODIFIED FOR LINUX KERNEL CONFIG BY: William Roadcap (roadcap@cfw.com)\n */\n\n#include <stdarg.h>\n\n#include \"dialog.h\"\n\n/* Needed in signal handler in mconf.c */\nint saved_x, saved_y;\n\nstruct dialog_info dlg;\n\nstatic void set_mono_theme(void)\n{\n\tdlg.screen.atr = A_NORMAL;\n\tdlg.shadow.atr = A_NORMAL;\n\tdlg.dialog.atr = A_NORMAL;\n\tdlg.title.atr = A_BOLD;\n\tdlg.border.atr = A_NORMAL;\n\tdlg.button_active.atr = A_REVERSE;\n\tdlg.button_inactive.atr = A_DIM;\n\tdlg.button_key_active.atr = A_REVERSE;\n\tdlg.button_key_inactive.atr = A_BOLD;\n\tdlg.button_label_active.atr = A_REVERSE;\n\tdlg.button_label_inactive.atr = A_NORMAL;\n\tdlg.inputbox.atr = A_NORMAL;\n\tdlg.inputbox_border.atr = A_NORMAL;\n\tdlg.searchbox.atr = A_NORMAL;\n\tdlg.searchbox_title.atr = A_BOLD;\n\tdlg.searchbox_border.atr = A_NORMAL;\n\tdlg.position_indicator.atr = A_BOLD;\n\tdlg.menubox.atr = A_NORMAL;\n\tdlg.menubox_border.atr = A_NORMAL;\n\tdlg.item.atr = A_NORMAL;\n\tdlg.item_selected.atr = A_REVERSE;\n\tdlg.tag.atr = A_BOLD;\n\tdlg.tag_selected.atr = A_REVERSE;\n\tdlg.tag_key.atr = A_BOLD;\n\tdlg.tag_key_selected.atr = A_REVERSE;\n\tdlg.check.atr = A_BOLD;\n\tdlg.check_selected.atr = A_REVERSE;\n\tdlg.uarrow.atr = A_BOLD;\n\tdlg.darrow.atr = A_BOLD;\n}\n\n#define DLG_COLOR(dialog, f, b, h) \\\ndo {                               \\\n\tdlg.dialog.fg = (f);       \\\n\tdlg.dialog.bg = (b);       \\\n\tdlg.dialog.hl = (h);       \\\n} while (0)\n\nstatic void set_classic_theme(void)\n{\n\tDLG_COLOR(screen,                COLOR_CYAN,   COLOR_BLUE,   true);\n\tDLG_COLOR(shadow,                COLOR_BLACK,  COLOR_BLACK,  true);\n\tDLG_COLOR(dialog,                COLOR_BLACK,  COLOR_WHITE,  false);\n\tDLG_COLOR(title,                 COLOR_YELLOW, COLOR_WHITE,  true);\n\tDLG_COLOR(border,                COLOR_WHITE,  COLOR_WHITE,  true);\n\tDLG_COLOR(button_active,         COLOR_WHITE,  COLOR_BLUE,   true);\n\tDLG_COLOR(button_inactive,       COLOR_BLACK,  COLOR_WHITE,  false);\n\tDLG_COLOR(button_key_active,     COLOR_WHITE,  COLOR_BLUE,   true);\n\tDLG_COLOR(button_key_inactive,   COLOR_RED,    COLOR_WHITE,  false);\n\tDLG_COLOR(button_label_active,   COLOR_YELLOW, COLOR_BLUE,   true);\n\tDLG_COLOR(button_label_inactive, COLOR_BLACK,  COLOR_WHITE,  true);\n\tDLG_COLOR(inputbox,              COLOR_BLACK,  COLOR_WHITE,  false);\n\tDLG_COLOR(inputbox_border,       COLOR_BLACK,  COLOR_WHITE,  false);\n\tDLG_COLOR(searchbox,             COLOR_BLACK,  COLOR_WHITE,  false);\n\tDLG_COLOR(searchbox_title,       COLOR_YELLOW, COLOR_WHITE,  true);\n\tDLG_COLOR(searchbox_border,      COLOR_WHITE,  COLOR_WHITE,  true);\n\tDLG_COLOR(position_indicator,    COLOR_YELLOW, COLOR_WHITE,  true);\n\tDLG_COLOR(menubox,               COLOR_BLACK,  COLOR_WHITE,  false);\n\tDLG_COLOR(menubox_border,        COLOR_WHITE,  COLOR_WHITE,  true);\n\tDLG_COLOR(item,                  COLOR_BLACK,  COLOR_WHITE,  false);\n\tDLG_COLOR(item_selected,         COLOR_WHITE,  COLOR_BLUE,   true);\n\tDLG_COLOR(tag,                   COLOR_YELLOW, COLOR_WHITE,  true);\n\tDLG_COLOR(tag_selected,          COLOR_YELLOW, COLOR_BLUE,   true);\n\tDLG_COLOR(tag_key,               COLOR_YELLOW, COLOR_WHITE,  true);\n\tDLG_COLOR(tag_key_selected,      COLOR_YELLOW, COLOR_BLUE,   true);\n\tDLG_COLOR(check,                 COLOR_BLACK,  COLOR_WHITE,  false);\n\tDLG_COLOR(check_selected,        COLOR_WHITE,  COLOR_BLUE,   true);\n\tDLG_COLOR(uarrow,                COLOR_GREEN,  COLOR_WHITE,  true);\n\tDLG_COLOR(darrow,                COLOR_GREEN,  COLOR_WHITE,  true);\n}\n\nstatic void set_blackbg_theme(void)\n{\n\tDLG_COLOR(screen, COLOR_RED,   COLOR_BLACK, true);\n\tDLG_COLOR(shadow, COLOR_BLACK, COLOR_BLACK, false);\n\tDLG_COLOR(dialog, COLOR_WHITE, COLOR_BLACK, false);\n\tDLG_COLOR(title,  COLOR_RED,   COLOR_BLACK, false);\n\tDLG_COLOR(border, COLOR_BLACK, COLOR_BLACK, true);\n\n\tDLG_COLOR(button_active,         COLOR_YELLOW, COLOR_RED,   false);\n\tDLG_COLOR(button_inactive,       COLOR_YELLOW, COLOR_BLACK, false);\n\tDLG_COLOR(button_key_active,     COLOR_YELLOW, COLOR_RED,   true);\n\tDLG_COLOR(button_key_inactive,   COLOR_RED,    COLOR_BLACK, false);\n\tDLG_COLOR(button_label_active,   COLOR_WHITE,  COLOR_RED,   false);\n\tDLG_COLOR(button_label_inactive, COLOR_BLACK,  COLOR_BLACK, true);\n\n\tDLG_COLOR(inputbox,         COLOR_YELLOW, COLOR_BLACK, false);\n\tDLG_COLOR(inputbox_border,  COLOR_YELLOW, COLOR_BLACK, false);\n\n\tDLG_COLOR(searchbox,        COLOR_YELLOW, COLOR_BLACK, false);\n\tDLG_COLOR(searchbox_title,  COLOR_YELLOW, COLOR_BLACK, true);\n\tDLG_COLOR(searchbox_border, COLOR_BLACK,  COLOR_BLACK, true);\n\n\tDLG_COLOR(position_indicator, COLOR_RED, COLOR_BLACK,  false);\n\n\tDLG_COLOR(menubox,          COLOR_YELLOW, COLOR_BLACK, false);\n\tDLG_COLOR(menubox_border,   COLOR_BLACK,  COLOR_BLACK, true);\n\n\tDLG_COLOR(item,             COLOR_WHITE, COLOR_BLACK, false);\n\tDLG_COLOR(item_selected,    COLOR_WHITE, COLOR_RED,   false);\n\n\tDLG_COLOR(tag,              COLOR_RED,    COLOR_BLACK, false);\n\tDLG_COLOR(tag_selected,     COLOR_YELLOW, COLOR_RED,   true);\n\tDLG_COLOR(tag_key,          COLOR_RED,    COLOR_BLACK, false);\n\tDLG_COLOR(tag_key_selected, COLOR_YELLOW, COLOR_RED,   true);\n\n\tDLG_COLOR(check,            COLOR_YELLOW, COLOR_BLACK, false);\n\tDLG_COLOR(check_selected,   COLOR_YELLOW, COLOR_RED,   true);\n\n\tDLG_COLOR(uarrow, COLOR_RED, COLOR_BLACK, false);\n\tDLG_COLOR(darrow, COLOR_RED, COLOR_BLACK, false);\n}\n\nstatic void set_bluetitle_theme(void)\n{\n\tset_classic_theme();\n\tDLG_COLOR(title,               COLOR_BLUE,   COLOR_WHITE, true);\n\tDLG_COLOR(button_key_active,   COLOR_YELLOW, COLOR_BLUE,  true);\n\tDLG_COLOR(button_label_active, COLOR_WHITE,  COLOR_BLUE,  true);\n\tDLG_COLOR(searchbox_title,     COLOR_BLUE,   COLOR_WHITE, true);\n\tDLG_COLOR(position_indicator,  COLOR_BLUE,   COLOR_WHITE, true);\n\tDLG_COLOR(tag,                 COLOR_BLUE,   COLOR_WHITE, true);\n\tDLG_COLOR(tag_key,             COLOR_BLUE,   COLOR_WHITE, true);\n\n}\n\n/*\n * Select color theme\n */\nstatic int set_theme(const char *theme)\n{\n\tint use_color = 1;\n\tif (!theme)\n\t\tset_bluetitle_theme();\n\telse if (strcmp(theme, \"classic\") == 0)\n\t\tset_classic_theme();\n\telse if (strcmp(theme, \"bluetitle\") == 0)\n\t\tset_bluetitle_theme();\n\telse if (strcmp(theme, \"blackbg\") == 0)\n\t\tset_blackbg_theme();\n\telse if (strcmp(theme, \"mono\") == 0)\n\t\tuse_color = 0;\n\n\treturn use_color;\n}\n\nstatic void init_one_color(struct dialog_color *color)\n{\n\tstatic int pair = 0;\n\n\tpair++;\n\tinit_pair(pair, color->fg, color->bg);\n\tif (color->hl)\n\t\tcolor->atr = A_BOLD | COLOR_PAIR(pair);\n\telse\n\t\tcolor->atr = COLOR_PAIR(pair);\n}\n\nstatic void init_dialog_colors(void)\n{\n\tinit_one_color(&dlg.screen);\n\tinit_one_color(&dlg.shadow);\n\tinit_one_color(&dlg.dialog);\n\tinit_one_color(&dlg.title);\n\tinit_one_color(&dlg.border);\n\tinit_one_color(&dlg.button_active);\n\tinit_one_color(&dlg.button_inactive);\n\tinit_one_color(&dlg.button_key_active);\n\tinit_one_color(&dlg.button_key_inactive);\n\tinit_one_color(&dlg.button_label_active);\n\tinit_one_color(&dlg.button_label_inactive);\n\tinit_one_color(&dlg.inputbox);\n\tinit_one_color(&dlg.inputbox_border);\n\tinit_one_color(&dlg.searchbox);\n\tinit_one_color(&dlg.searchbox_title);\n\tinit_one_color(&dlg.searchbox_border);\n\tinit_one_color(&dlg.position_indicator);\n\tinit_one_color(&dlg.menubox);\n\tinit_one_color(&dlg.menubox_border);\n\tinit_one_color(&dlg.item);\n\tinit_one_color(&dlg.item_selected);\n\tinit_one_color(&dlg.tag);\n\tinit_one_color(&dlg.tag_selected);\n\tinit_one_color(&dlg.tag_key);\n\tinit_one_color(&dlg.tag_key_selected);\n\tinit_one_color(&dlg.check);\n\tinit_one_color(&dlg.check_selected);\n\tinit_one_color(&dlg.uarrow);\n\tinit_one_color(&dlg.darrow);\n}\n\n/*\n * Setup for color display\n */\nstatic void color_setup(const char *theme)\n{\n\tint use_color;\n\n\tuse_color = set_theme(theme);\n\tif (use_color && has_colors()) {\n\t\tstart_color();\n\t\tinit_dialog_colors();\n\t} else\n\t\tset_mono_theme();\n}\n\n/*\n * Set window to attribute 'attr'\n */\nvoid attr_clear(WINDOW * win, int height, int width, chtype attr)\n{\n\tint i, j;\n\n\twattrset(win, attr);\n\tfor (i = 0; i < height; i++) {\n\t\twmove(win, i, 0);\n\t\tfor (j = 0; j < width; j++)\n\t\t\twaddch(win, ' ');\n\t}\n\ttouchwin(win);\n}\n\nvoid dialog_clear(void)\n{\n\tint lines, columns;\n\n\tlines = getmaxy(stdscr);\n\tcolumns = getmaxx(stdscr);\n\n\tattr_clear(stdscr, lines, columns, dlg.screen.atr);\n\t/* Display background title if it exists ... - SLH */\n\tif (dlg.backtitle != NULL) {\n\t\tint i, len = 0, skip = 0;\n\t\tstruct subtitle_list *pos;\n\n\t\twattrset(stdscr, dlg.screen.atr);\n\t\tmvwaddstr(stdscr, 0, 1, (char *)dlg.backtitle);\n\n\t\tfor (pos = dlg.subtitles; pos != NULL; pos = pos->next) {\n\t\t\t/* 3 is for the arrow and spaces */\n\t\t\tlen += strlen(pos->text) + 3;\n\t\t}\n\n\t\twmove(stdscr, 1, 1);\n\t\tif (len > columns - 2) {\n\t\t\tconst char *ellipsis = \"[...] \";\n\t\t\twaddstr(stdscr, ellipsis);\n\t\t\tskip = len - (columns - 2 - strlen(ellipsis));\n\t\t}\n\n\t\tfor (pos = dlg.subtitles; pos != NULL; pos = pos->next) {\n\t\t\tif (skip == 0)\n\t\t\t\twaddch(stdscr, ACS_RARROW);\n\t\t\telse\n\t\t\t\tskip--;\n\n\t\t\tif (skip == 0)\n\t\t\t\twaddch(stdscr, ' ');\n\t\t\telse\n\t\t\t\tskip--;\n\n\t\t\tif (skip < strlen(pos->text)) {\n\t\t\t\twaddstr(stdscr, pos->text + skip);\n\t\t\t\tskip = 0;\n\t\t\t} else\n\t\t\t\tskip -= strlen(pos->text);\n\n\t\t\tif (skip == 0)\n\t\t\t\twaddch(stdscr, ' ');\n\t\t\telse\n\t\t\t\tskip--;\n\t\t}\n\n\t\tfor (i = len + 1; i < columns - 1; i++)\n\t\t\twaddch(stdscr, ACS_HLINE);\n\t}\n\twnoutrefresh(stdscr);\n}\n\n/*\n * Do some initialization for dialog\n */\nint init_dialog(const char *backtitle)\n{\n\tint height, width;\n\n\tinitscr();\t\t/* Init curses */\n\n\t/* Get current cursor position for signal handler in mconf.c */\n\tgetyx(stdscr, saved_y, saved_x);\n\n\tgetmaxyx(stdscr, height, width);\n\tif (height < WINDOW_HEIGTH_MIN || width < WINDOW_WIDTH_MIN) {\n\t\tendwin();\n\t\treturn -ERRDISPLAYTOOSMALL;\n\t}\n\n\tdlg.backtitle = backtitle;\n\tcolor_setup(getenv(\"MENUCONFIG_COLOR\"));\n\n\tkeypad(stdscr, TRUE);\n\tcbreak();\n\tnoecho();\n\tdialog_clear();\n\n\treturn 0;\n}\n\nvoid set_dialog_backtitle(const char *backtitle)\n{\n\tdlg.backtitle = backtitle;\n}\n\nvoid set_dialog_subtitles(struct subtitle_list *subtitles)\n{\n\tdlg.subtitles = subtitles;\n}\n\n/*\n * End using dialog functions.\n */\nvoid end_dialog(int x, int y)\n{\n\t/* move cursor back to original position */\n\tmove(y, x);\n\trefresh();\n\tendwin();\n}\n\n/* Print the title of the dialog. Center the title and truncate\n * tile if wider than dialog (- 2 chars).\n **/\nvoid print_title(WINDOW *dialog, const char *title, int width)\n{\n\tif (title) {\n\t\tint tlen = MIN(width - 2, strlen(title));\n\t\twattrset(dialog, dlg.title.atr);\n\t\tmvwaddch(dialog, 0, (width - tlen) / 2 - 1, ' ');\n\t\tmvwaddnstr(dialog, 0, (width - tlen)/2, title, tlen);\n\t\twaddch(dialog, ' ');\n\t}\n}\n\n/*\n * Print a string of text in a window, automatically wrap around to the\n * next line if the string is too long to fit on one line. Newline\n * characters '\\n' are properly processed.  We start on a new line\n * if there is no room for at least 4 nonblanks following a double-space.\n */\nvoid print_autowrap(WINDOW * win, const char *prompt, int width, int y, int x)\n{\n\tint newl, cur_x, cur_y;\n\tint prompt_len, room, wlen;\n\tchar tempstr[MAX_LEN + 1], *word, *sp, *sp2, *newline_separator = 0;\n\n\tstrcpy(tempstr, prompt);\n\n\tprompt_len = strlen(tempstr);\n\n\tif (prompt_len <= width - x * 2) {\t/* If prompt is short */\n\t\twmove(win, y, (width - prompt_len) / 2);\n\t\twaddstr(win, tempstr);\n\t} else {\n\t\tcur_x = x;\n\t\tcur_y = y;\n\t\tnewl = 1;\n\t\tword = tempstr;\n\t\twhile (word && *word) {\n\t\t\tsp = strpbrk(word, \"\\n \");\n\t\t\tif (sp && *sp == '\\n')\n\t\t\t\tnewline_separator = sp;\n\n\t\t\tif (sp)\n\t\t\t\t*sp++ = 0;\n\n\t\t\t/* Wrap to next line if either the word does not fit,\n\t\t\t   or it is the first word of a new sentence, and it is\n\t\t\t   short, and the next word does not fit. */\n\t\t\troom = width - cur_x;\n\t\t\twlen = strlen(word);\n\t\t\tif (wlen > room ||\n\t\t\t    (newl && wlen < 4 && sp\n\t\t\t     && wlen + 1 + strlen(sp) > room\n\t\t\t     && (!(sp2 = strpbrk(sp, \"\\n \"))\n\t\t\t\t || wlen + 1 + (sp2 - sp) > room))) {\n\t\t\t\tcur_y++;\n\t\t\t\tcur_x = x;\n\t\t\t}\n\t\t\twmove(win, cur_y, cur_x);\n\t\t\twaddstr(win, word);\n\t\t\tgetyx(win, cur_y, cur_x);\n\n\t\t\t/* Move to the next line if the word separator was a newline */\n\t\t\tif (newline_separator) {\n\t\t\t\tcur_y++;\n\t\t\t\tcur_x = x;\n\t\t\t\tnewline_separator = 0;\n\t\t\t} else\n\t\t\t\tcur_x++;\n\n\t\t\tif (sp && *sp == ' ') {\n\t\t\t\tcur_x++;\t/* double space */\n\t\t\t\twhile (*++sp == ' ') ;\n\t\t\t\tnewl = 1;\n\t\t\t} else\n\t\t\t\tnewl = 0;\n\t\t\tword = sp;\n\t\t}\n\t}\n}\n\n/*\n * Print a button\n */\nvoid print_button(WINDOW * win, const char *label, int y, int x, int selected)\n{\n\tint i, temp;\n\n\twmove(win, y, x);\n\twattrset(win, selected ? dlg.button_active.atr\n\t\t : dlg.button_inactive.atr);\n\twaddstr(win, \"<\");\n\ttemp = strspn(label, \" \");\n\tlabel += temp;\n\twattrset(win, selected ? dlg.button_label_active.atr\n\t\t : dlg.button_label_inactive.atr);\n\tfor (i = 0; i < temp; i++)\n\t\twaddch(win, ' ');\n\twattrset(win, selected ? dlg.button_key_active.atr\n\t\t : dlg.button_key_inactive.atr);\n\twaddch(win, label[0]);\n\twattrset(win, selected ? dlg.button_label_active.atr\n\t\t : dlg.button_label_inactive.atr);\n\twaddstr(win, (char *)label + 1);\n\twattrset(win, selected ? dlg.button_active.atr\n\t\t : dlg.button_inactive.atr);\n\twaddstr(win, \">\");\n\twmove(win, y, x + temp + 1);\n}\n\n/*\n * Draw a rectangular box with line drawing characters\n */\nvoid\ndraw_box(WINDOW * win, int y, int x, int height, int width,\n\t chtype box, chtype border)\n{\n\tint i, j;\n\n\twattrset(win, 0);\n\tfor (i = 0; i < height; i++) {\n\t\twmove(win, y + i, x);\n\t\tfor (j = 0; j < width; j++)\n\t\t\tif (!i && !j)\n\t\t\t\twaddch(win, border | ACS_ULCORNER);\n\t\t\telse if (i == height - 1 && !j)\n\t\t\t\twaddch(win, border | ACS_LLCORNER);\n\t\t\telse if (!i && j == width - 1)\n\t\t\t\twaddch(win, box | ACS_URCORNER);\n\t\t\telse if (i == height - 1 && j == width - 1)\n\t\t\t\twaddch(win, box | ACS_LRCORNER);\n\t\t\telse if (!i)\n\t\t\t\twaddch(win, border | ACS_HLINE);\n\t\t\telse if (i == height - 1)\n\t\t\t\twaddch(win, box | ACS_HLINE);\n\t\t\telse if (!j)\n\t\t\t\twaddch(win, border | ACS_VLINE);\n\t\t\telse if (j == width - 1)\n\t\t\t\twaddch(win, box | ACS_VLINE);\n\t\t\telse\n\t\t\t\twaddch(win, box | ' ');\n\t}\n}\n\n/*\n * Draw shadows along the right and bottom edge to give a more 3D look\n * to the boxes\n */\nvoid draw_shadow(WINDOW * win, int y, int x, int height, int width)\n{\n\tint i;\n\n\tif (has_colors()) {\t/* Whether terminal supports color? */\n\t\twattrset(win, dlg.shadow.atr);\n\t\twmove(win, y + height, x + 2);\n\t\tfor (i = 0; i < width; i++)\n\t\t\twaddch(win, winch(win) & A_CHARTEXT);\n\t\tfor (i = y + 1; i < y + height + 1; i++) {\n\t\t\twmove(win, i, x + width);\n\t\t\twaddch(win, winch(win) & A_CHARTEXT);\n\t\t\twaddch(win, winch(win) & A_CHARTEXT);\n\t\t}\n\t\twnoutrefresh(win);\n\t}\n}\n\n/*\n *  Return the position of the first alphabetic character in a string.\n */\nint first_alpha(const char *string, const char *exempt)\n{\n\tint i, in_paren = 0, c;\n\n\tfor (i = 0; i < strlen(string); i++) {\n\t\tc = tolower(string[i]);\n\n\t\tif (strchr(\"<[(\", c))\n\t\t\t++in_paren;\n\t\tif (strchr(\">])\", c) && in_paren > 0)\n\t\t\t--in_paren;\n\n\t\tif ((!in_paren) && isalpha(c) && strchr(exempt, c) == 0)\n\t\t\treturn i;\n\t}\n\n\treturn 0;\n}\n\n/*\n * ncurses uses ESC to detect escaped char sequences. This resutl in\n * a small timeout before ESC is actually delivered to the application.\n * lxdialog suggest <ESC> <ESC> which is correctly translated to two\n * times esc. But then we need to ignore the second esc to avoid stepping\n * out one menu too much. Filter away all escaped key sequences since\n * keypad(FALSE) turn off ncurses support for escape sequences - and that's\n * needed to make notimeout() do as expected.\n */\nint on_key_esc(WINDOW *win)\n{\n\tint key;\n\tint key2;\n\tint key3;\n\n\tnodelay(win, TRUE);\n\tkeypad(win, FALSE);\n\tkey = wgetch(win);\n\tkey2 = wgetch(win);\n\tdo {\n\t\tkey3 = wgetch(win);\n\t} while (key3 != ERR);\n\tnodelay(win, FALSE);\n\tkeypad(win, TRUE);\n\tif (key == KEY_ESC && key2 == ERR)\n\t\treturn KEY_ESC;\n\telse if (key != ERR && key != KEY_ESC && key2 == ERR)\n\t\tungetch(key);\n\n\treturn -1;\n}\n\n/* redraw screen in new size */\nint on_key_resize(void)\n{\n\tdialog_clear();\n\treturn KEY_RESIZE;\n}\n\nstruct dialog_list *item_cur;\nstruct dialog_list item_nil;\nstruct dialog_list *item_head;\n\nvoid item_reset(void)\n{\n\tstruct dialog_list *p, *next;\n\n\tfor (p = item_head; p; p = next) {\n\t\tnext = p->next;\n\t\tfree(p);\n\t}\n\titem_head = NULL;\n\titem_cur = &item_nil;\n}\n\nvoid item_make(const char *fmt, ...)\n{\n\tva_list ap;\n\tstruct dialog_list *p = malloc(sizeof(*p));\n\n\tif (item_head)\n\t\titem_cur->next = p;\n\telse\n\t\titem_head = p;\n\titem_cur = p;\n\tmemset(p, 0, sizeof(*p));\n\n\tva_start(ap, fmt);\n\tvsnprintf(item_cur->node.str, sizeof(item_cur->node.str), fmt, ap);\n\tva_end(ap);\n}\n\nvoid item_add_str(const char *fmt, ...)\n{\n\tva_list ap;\n\tsize_t avail;\n\n\tavail = sizeof(item_cur->node.str) - strlen(item_cur->node.str);\n\n\tva_start(ap, fmt);\n\tvsnprintf(item_cur->node.str + strlen(item_cur->node.str),\n\t\t  avail, fmt, ap);\n\titem_cur->node.str[sizeof(item_cur->node.str) - 1] = '\\0';\n\tva_end(ap);\n}\n\nvoid item_set_tag(char tag)\n{\n\titem_cur->node.tag = tag;\n}\nvoid item_set_data(void *ptr)\n{\n\titem_cur->node.data = ptr;\n}\n\nvoid item_set_selected(int val)\n{\n\titem_cur->node.selected = val;\n}\n\nint item_activate_selected(void)\n{\n\titem_foreach()\n\t\tif (item_is_selected())\n\t\t\treturn 1;\n\treturn 0;\n}\n\nvoid *item_data(void)\n{\n\treturn item_cur->node.data;\n}\n\nchar item_tag(void)\n{\n\treturn item_cur->node.tag;\n}\n\nint item_count(void)\n{\n\tint n = 0;\n\tstruct dialog_list *p;\n\n\tfor (p = item_head; p; p = p->next)\n\t\tn++;\n\treturn n;\n}\n\nvoid item_set(int n)\n{\n\tint i = 0;\n\titem_foreach()\n\t\tif (i++ == n)\n\t\t\treturn;\n}\n\nint item_n(void)\n{\n\tint n = 0;\n\tstruct dialog_list *p;\n\n\tfor (p = item_head; p; p = p->next) {\n\t\tif (p == item_cur)\n\t\t\treturn n;\n\t\tn++;\n\t}\n\treturn 0;\n}\n\nconst char *item_str(void)\n{\n\treturn item_cur->node.str;\n}\n\nint item_is_selected(void)\n{\n\treturn (item_cur->node.selected != 0);\n}\n\nint item_is_tag(char tag)\n{\n\treturn (item_cur->node.tag == tag);\n}\n"
  },
  {
    "path": "scripts/config/lxdialog/yesno.c",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later\n/*\n *  yesno.c -- implements the yes/no box\n *\n *  ORIGINAL AUTHOR: Savio Lam (lam836@cs.cuhk.hk)\n *  MODIFIED FOR LINUX KERNEL CONFIG BY: William Roadcap (roadcap@cfw.com)\n */\n\n#include \"dialog.h\"\n\n/*\n * Display termination buttons\n */\nstatic void print_buttons(WINDOW * dialog, int height, int width, int selected)\n{\n\tint x = width / 2 - 10;\n\tint y = height - 2;\n\n\tprint_button(dialog, \" Yes \", y, x, selected == 0);\n\tprint_button(dialog, \"  No  \", y, x + 13, selected == 1);\n\n\twmove(dialog, y, x + 1 + 13 * selected);\n\twrefresh(dialog);\n}\n\n/*\n * Display a dialog box with two buttons - Yes and No\n */\nint dialog_yesno(const char *title, const char *prompt, int height, int width)\n{\n\tint i, x, y, key = 0, button = 0;\n\tWINDOW *dialog;\n\ndo_resize:\n\tif (getmaxy(stdscr) < (height + YESNO_HEIGTH_MIN))\n\t\treturn -ERRDISPLAYTOOSMALL;\n\tif (getmaxx(stdscr) < (width + YESNO_WIDTH_MIN))\n\t\treturn -ERRDISPLAYTOOSMALL;\n\n\t/* center dialog box on screen */\n\tx = (getmaxx(stdscr) - width) / 2;\n\ty = (getmaxy(stdscr) - height) / 2;\n\n\tdraw_shadow(stdscr, y, x, height, width);\n\n\tdialog = newwin(height, width, y, x);\n\tkeypad(dialog, TRUE);\n\n\tdraw_box(dialog, 0, 0, height, width,\n\t\t dlg.dialog.atr, dlg.border.atr);\n\twattrset(dialog, dlg.border.atr);\n\tmvwaddch(dialog, height - 3, 0, ACS_LTEE);\n\tfor (i = 0; i < width - 2; i++)\n\t\twaddch(dialog, ACS_HLINE);\n\twattrset(dialog, dlg.dialog.atr);\n\twaddch(dialog, ACS_RTEE);\n\n\tprint_title(dialog, title, width);\n\n\twattrset(dialog, dlg.dialog.atr);\n\tprint_autowrap(dialog, prompt, width - 2, 1, 3);\n\n\tprint_buttons(dialog, height, width, 0);\n\n\twhile (key != KEY_ESC) {\n\t\tkey = wgetch(dialog);\n\t\tswitch (key) {\n\t\tcase 'Y':\n\t\tcase 'y':\n\t\t\tdelwin(dialog);\n\t\t\treturn 0;\n\t\tcase 'N':\n\t\tcase 'n':\n\t\t\tdelwin(dialog);\n\t\t\treturn 1;\n\n\t\tcase TAB:\n\t\tcase KEY_LEFT:\n\t\tcase KEY_RIGHT:\n\t\t\tbutton = ((key == KEY_LEFT ? --button : ++button) < 0) ? 1 : (button > 1 ? 0 : button);\n\n\t\t\tprint_buttons(dialog, height, width, button);\n\t\t\twrefresh(dialog);\n\t\t\tbreak;\n\t\tcase ' ':\n\t\tcase '\\n':\n\t\t\tdelwin(dialog);\n\t\t\treturn button;\n\t\tcase KEY_ESC:\n\t\t\tkey = on_key_esc(dialog);\n\t\t\tbreak;\n\t\tcase KEY_RESIZE:\n\t\t\tdelwin(dialog);\n\t\t\ton_key_resize();\n\t\t\tgoto do_resize;\n\t\t}\n\t}\n\n\tdelwin(dialog);\n\treturn key;\t\t/* ESC pressed */\n}\n"
  },
  {
    "path": "scripts/config/mconf-cfg.sh",
    "content": "#!/bin/sh\n# SPDX-License-Identifier: GPL-2.0-only\n\nPKG=\"ncursesw\"\nPKG2=\"ncurses\"\n\nif [ -n \"$(command -v pkg-config)\" ]; then\n\tif pkg-config --exists $PKG; then\n\t\techo cflags=\\\"$(pkg-config --cflags $PKG)\\\"\n\t\techo libs=\\\"$(pkg-config --libs $PKG)\\\"\n\t\texit 0\n\tfi\n\n\tif pkg-config --exists $PKG2; then\n\t\techo cflags=\\\"$(pkg-config --cflags $PKG2)\\\"\n\t\techo libs=\\\"$(pkg-config --libs $PKG2)\\\"\n\t\texit 0\n\tfi\nfi\n\n# Check the default paths in case pkg-config is not installed.\n# (Even if it is installed, some distributions such as openSUSE cannot\n# find ncurses by pkg-config.)\nif [ -f /usr/include/ncursesw/ncurses.h ]; then\n\techo cflags=\\\"-D_GNU_SOURCE -I/usr/include/ncursesw\\\"\n\techo libs=\\\"-lncursesw\\\"\n\texit 0\nfi\n\nif [ -f /usr/include/ncurses/ncurses.h ]; then\n\techo cflags=\\\"-D_GNU_SOURCE -I/usr/include/ncurses\\\"\n\techo libs=\\\"-lncurses\\\"\n\texit 0\nfi\n\n# As a final fallback before giving up, check if $HOSTCC knows of a default\n# ncurses installation (e.g. from a vendor-specific sysroot).\nif echo '#include <ncurses.h>' | ${HOSTCC} -E - >/dev/null 2>&1; then\n\techo cflags=\\\"-D_GNU_SOURCE\\\"\n\techo libs=\\\"-lncurses\\\"\n\texit 0\nfi\n\necho >&2 \"*\"\necho >&2 \"* Unable to find the ncurses package.\"\necho >&2 \"* Install ncurses (ncurses-devel or libncurses-dev\"\necho >&2 \"* depending on your distribution).\"\necho >&2 \"*\"\necho >&2 \"* You may also need to install pkg-config to find the\"\necho >&2 \"* ncurses installed in a non-default location.\"\necho >&2 \"*\"\nexit 1\n"
  },
  {
    "path": "scripts/config/mconf.c",
    "content": "// SPDX-License-Identifier: GPL-2.0-only\n/*\n * Copyright (C) 2002 Roman Zippel <zippel@linux-m68k.org>\n *\n * Introduced single menu mode (show all sub-menus in one large tree).\n * 2002-11-06 Petr Baudis <pasky@ucw.cz>\n *\n * i18n, 2005, Arnaldo Carvalho de Melo <acme@conectiva.com.br>\n */\n\n#include <ctype.h>\n#include <errno.h>\n#include <fcntl.h>\n#include <limits.h>\n#include <stdarg.h>\n#include <stdlib.h>\n#include <string.h>\n#include <strings.h>\n#include <signal.h>\n#include <unistd.h>\n\n#include \"lkc.h\"\n#include \"lxdialog/dialog.h\"\n\n#define JUMP_NB\t\t\t9\n\nstatic const char mconf_readme[] =\n\"OpenWrt config is based on Kernel kconfig\\n\"\n\"so ipkg packages are referred here as modules.\\n\"\n\"\\n\"\n\"Overview\\n\"\n\"--------\\n\"\n\"This interface lets you select features and parameters for the build.\\n\"\n\"Features can either be built-in, modularized, or ignored. Parameters\\n\"\n\"must be entered in as decimal or hexadecimal numbers or text.\\n\"\n\"\\n\"\n\"Menu items beginning with following braces represent features that\\n\"\n\"  [ ] can be built in or removed\\n\"\n\"  < > can be built in, modularized or removed\\n\"\n\"  { } can be built in or modularized (selected by other feature)\\n\"\n\"  - - are selected by other feature,\\n\"\n\"while *, M or whitespace inside braces means to build in, build as\\n\"\n\"a module or to exclude the feature respectively.\\n\"\n\"\\n\"\n\"To change any of these features, highlight it with the cursor\\n\"\n\"keys and press <Y> to build it in, <M> to make it a module or\\n\"\n\"<N> to remove it.  You may also press the <Space Bar> to cycle\\n\"\n\"through the available options (i.e. Y->N->M->Y).\\n\"\n\"\\n\"\n\"Some additional keyboard hints:\\n\"\n\"\\n\"\n\"Menus\\n\"\n\"----------\\n\"\n\"o  Use the Up/Down arrow keys (cursor keys) to highlight the item you\\n\"\n\"   wish to change or the submenu you wish to select and press <Enter>.\\n\"\n\"   Submenus are designated by \\\"--->\\\", empty ones by \\\"----\\\".\\n\"\n\"\\n\"\n\"   Shortcut: Press the option's highlighted letter (hotkey).\\n\"\n\"             Pressing a hotkey more than once will sequence\\n\"\n\"             through all visible items which use that hotkey.\\n\"\n\"\\n\"\n\"   You may also use the <PAGE UP> and <PAGE DOWN> keys to scroll\\n\"\n\"   unseen options into view.\\n\"\n\"\\n\"\n\"o  To exit a menu use the cursor keys to highlight the <Exit> button\\n\"\n\"   and press <ENTER>.\\n\"\n\"\\n\"\n\"   Shortcut: Press <ESC><ESC> or <E> or <X> if there is no hotkey\\n\"\n\"             using those letters.  You may press a single <ESC>, but\\n\"\n\"             there is a delayed response which you may find annoying.\\n\"\n\"\\n\"\n\"   Also, the <TAB> and cursor keys will cycle between <Select>,\\n\"\n\"   <Exit>, <Help>, <Save>, and <Load>.\\n\"\n\"\\n\"\n\"o  To get help with an item, use the cursor keys to highlight <Help>\\n\"\n\"   and press <ENTER>.\\n\"\n\"\\n\"\n\"   Shortcut: Press <H> or <?>.\\n\"\n\"\\n\"\n\"o  To toggle the display of hidden options, press <Z>.\\n\"\n\"\\n\"\n\"\\n\"\n\"Radiolists  (Choice lists)\\n\"\n\"-----------\\n\"\n\"o  Use the cursor keys to select the option you wish to set and press\\n\"\n\"   <S> or the <SPACE BAR>.\\n\"\n\"\\n\"\n\"   Shortcut: Press the first letter of the option you wish to set then\\n\"\n\"             press <S> or <SPACE BAR>.\\n\"\n\"\\n\"\n\"o  To see available help for the item, use the cursor keys to highlight\\n\"\n\"   <Help> and Press <ENTER>.\\n\"\n\"\\n\"\n\"   Shortcut: Press <H> or <?>.\\n\"\n\"\\n\"\n\"   Also, the <TAB> and cursor keys will cycle between <Select> and\\n\"\n\"   <Help>\\n\"\n\"\\n\"\n\"\\n\"\n\"Data Entry\\n\"\n\"-----------\\n\"\n\"o  Enter the requested information and press <ENTER>\\n\"\n\"   If you are entering hexadecimal values, it is not necessary to\\n\"\n\"   add the '0x' prefix to the entry.\\n\"\n\"\\n\"\n\"o  For help, use the <TAB> or cursor keys to highlight the help option\\n\"\n\"   and press <ENTER>.  You can try <TAB><H> as well.\\n\"\n\"\\n\"\n\"\\n\"\n\"Text Box    (Help Window)\\n\"\n\"--------\\n\"\n\"o  Use the cursor keys to scroll up/down/left/right.  The VI editor\\n\"\n\"   keys h,j,k,l function here as do <u>, <d>, <SPACE BAR> and <B> for\\n\"\n\"   those who are familiar with less and lynx.\\n\"\n\"\\n\"\n\"o  Press <E>, <X>, <q>, <Enter> or <Esc><Esc> to exit.\\n\"\n\"\\n\"\n\"\\n\"\n\"Alternate Configuration Files\\n\"\n\"-----------------------------\\n\"\n\"Menuconfig supports the use of alternate configuration files for\\n\"\n\"those who, for various reasons, find it necessary to switch\\n\"\n\"between different configurations.\\n\"\n\"\\n\"\n\"The <Save> button will let you save the current configuration to\\n\"\n\"a file of your choosing.  Use the <Load> button to load a previously\\n\"\n\"saved alternate configuration.\\n\"\n\"\\n\"\n\"Even if you don't use alternate configuration files, but you find\\n\"\n\"during a Menuconfig session that you have completely messed up your\\n\"\n\"settings, you may use the <Load> button to restore your previously\\n\"\n\"saved settings from \\\".config\\\" without restarting Menuconfig.\\n\"\n\"\\n\"\n\"Other information\\n\"\n\"-----------------\\n\"\n\"If you use Menuconfig in an XTERM window, make sure you have your\\n\"\n\"$TERM variable set to point to an xterm definition which supports\\n\"\n\"color.  Otherwise, Menuconfig will look rather bad.  Menuconfig will\\n\"\n\"not display correctly in an RXVT window because rxvt displays only one\\n\"\n\"intensity of color, bright.\\n\"\n\"\\n\"\n\"Menuconfig will display larger menus on screens or xterms which are\\n\"\n\"set to display more than the standard 25 row by 80 column geometry.\\n\"\n\"In order for this to work, the \\\"stty size\\\" command must be able to\\n\"\n\"display the screen's current row and column geometry.  I STRONGLY\\n\"\n\"RECOMMEND that you make sure you do NOT have the shell variables\\n\"\n\"LINES and COLUMNS exported into your environment.  Some distributions\\n\"\n\"export those variables via /etc/profile.  Some ncurses programs can\\n\"\n\"become confused when those variables (LINES & COLUMNS) don't reflect\\n\"\n\"the true screen size.\\n\"\n\"\\n\"\n\"Optional personality available\\n\"\n\"------------------------------\\n\"\n\"If you prefer to have all of the options listed in a single menu,\\n\"\n\"rather than the default multimenu hierarchy, run the menuconfig with\\n\"\n\"MENUCONFIG_MODE environment variable set to single_menu. Example:\\n\"\n\"\\n\"\n\"make MENUCONFIG_MODE=single_menu menuconfig\\n\"\n\"\\n\"\n\"<Enter> will then unroll the appropriate category, or enfold it if it\\n\"\n\"is already unrolled.\\n\"\n\"\\n\"\n\"Note that this mode can eventually be a little more CPU expensive\\n\"\n\"(especially with a larger number of unrolled categories) than the\\n\"\n\"default mode.\\n\"\n\"\\n\"\n\"Different color themes available\\n\"\n\"--------------------------------\\n\"\n\"It is possible to select different color themes using the variable\\n\"\n\"MENUCONFIG_COLOR. To select a theme use:\\n\"\n\"\\n\"\n\"make MENUCONFIG_COLOR=<theme> menuconfig\\n\"\n\"\\n\"\n\"Available themes are\\n\"\n\" mono       => selects colors suitable for monochrome displays\\n\"\n\" blackbg    => selects a color scheme with black background\\n\"\n\" classic    => theme with blue background. The classic look\\n\"\n\" bluetitle  => an LCD friendly version of classic. (default)\\n\"\n\"\\n\",\nmenu_instructions[] =\n\t\"Arrow keys navigate the menu.  \"\n\t\"<Enter> selects submenus ---> (or empty submenus ----).  \"\n\t\"Highlighted letters are hotkeys.  \"\n\t\"Pressing <Y> includes, <N> excludes, <M> modularizes features.  \"\n\t\"Press <Esc><Esc> to exit, <?> for Help, </> for Search.  \"\n\t\"Legend: [*] built-in  [ ] excluded  <M> module  < > module capable\",\nradiolist_instructions[] =\n\t\"Use the arrow keys to navigate this window or \"\n\t\"press the hotkey of the item you wish to select \"\n\t\"followed by the <SPACE BAR>. \"\n\t\"Press <?> for additional information about this option.\",\ninputbox_instructions_int[] =\n\t\"Please enter a decimal value. \"\n\t\"Fractions will not be accepted.  \"\n\t\"Use the <TAB> key to move from the input field to the buttons below it.\",\ninputbox_instructions_hex[] =\n\t\"Please enter a hexadecimal value. \"\n\t\"Use the <TAB> key to move from the input field to the buttons below it.\",\ninputbox_instructions_string[] =\n\t\"Please enter a string value. \"\n\t\"Use the <TAB> key to move from the input field to the buttons below it.\",\nsetmod_text[] =\n\t\"This feature depends on another which has been configured as a module.\\n\"\n\t\"As a result, this feature will be built as a module.\",\nload_config_text[] =\n\t\"Enter the name of the configuration file you wish to load.  \"\n\t\"Accept the name shown to restore the configuration you \"\n\t\"last retrieved.  Leave blank to abort.\",\nload_config_help[] =\n\t\"\\n\"\n\t\"For various reasons, one may wish to keep several different\\n\"\n\t\"configurations available on a single machine.\\n\"\n\t\"\\n\"\n\t\"If you have saved a previous configuration in a file other than the\\n\"\n\t\"default one, entering its name here will allow you to modify that\\n\"\n\t\"configuration.\\n\"\n\t\"\\n\"\n\t\"If you are uncertain, then you have probably never used alternate\\n\"\n\t\"configuration files. You should therefore leave this blank to abort.\\n\",\nsave_config_text[] =\n\t\"Enter a filename to which this configuration should be saved \"\n\t\"as an alternate.  Leave blank to abort.\",\nsave_config_help[] =\n\t\"\\n\"\n\t\"For various reasons, one may wish to keep different configurations\\n\"\n\t\"available on a single machine.\\n\"\n\t\"\\n\"\n\t\"Entering a file name here will allow you to later retrieve, modify\\n\"\n\t\"and use the current configuration as an alternate to whatever\\n\"\n\t\"configuration options you have selected at that time.\\n\"\n\t\"\\n\"\n\t\"If you are uncertain what all this means then you should probably\\n\"\n\t\"leave this blank.\\n\",\nsearch_help[] =\n\t\"\\n\"\n\t\"Search for symbols and display their relations.\\n\"\n\t\"Regular expressions are allowed.\\n\"\n\t\"Example: search for \\\"^FOO\\\"\\n\"\n\t\"Result:\\n\"\n\t\"-----------------------------------------------------------------\\n\"\n\t\"Symbol: FOO [=m]\\n\"\n\t\"Type  : tristate\\n\"\n\t\"Prompt: Foo bus is used to drive the bar HW\\n\"\n\t\"  Location:\\n\"\n\t\"    -> Bus options (PCI, PCMCIA, EISA, ISA)\\n\"\n\t\"      -> PCI support (PCI [=y])\\n\"\n\t\"(1)     -> PCI access mode (<choice> [=y])\\n\"\n\t\"  Defined at drivers/pci/Kconfig:47\\n\"\n\t\"  Depends on: X86_LOCAL_APIC && X86_IO_APIC || IA64\\n\"\n\t\"  Selects: LIBCRC32\\n\"\n\t\"  Selected by: BAR [=n]\\n\"\n\t\"-----------------------------------------------------------------\\n\"\n\t\"o The line 'Type:' shows the type of the configuration option for\\n\"\n\t\"  this symbol (bool, tristate, string, ...)\\n\"\n\t\"o The line 'Prompt:' shows the text used in the menu structure for\\n\"\n\t\"  this symbol\\n\"\n\t\"o The 'Defined at' line tells at what file / line number the symbol\\n\"\n\t\"  is defined\\n\"\n\t\"o The 'Depends on:' line tells what symbols need to be defined for\\n\"\n\t\"  this symbol to be visible in the menu (selectable)\\n\"\n\t\"o The 'Location:' lines tells where in the menu structure this symbol\\n\"\n\t\"  is located\\n\"\n\t\"    A location followed by a [=y] indicates that this is a\\n\"\n\t\"    selectable menu item - and the current value is displayed inside\\n\"\n\t\"    brackets.\\n\"\n\t\"    Press the key in the (#) prefix to jump directly to that\\n\"\n\t\"    location. You will be returned to the current search results\\n\"\n\t\"    after exiting this new menu.\\n\"\n\t\"o The 'Selects:' line tells what symbols will be automatically\\n\"\n\t\"  selected if this symbol is selected (y or m)\\n\"\n\t\"o The 'Selected by' line tells what symbol has selected this symbol\\n\"\n\t\"\\n\"\n\t\"Only relevant lines are shown.\\n\"\n\t\"\\n\\n\"\n\t\"Search examples:\\n\"\n\t\"Examples: USB\t=> find all symbols containing USB\\n\"\n\t\"          ^USB => find all symbols starting with USB\\n\"\n\t\"          USB$ => find all symbols ending with USB\\n\"\n\t\"\\n\";\n\nstatic int indent;\nstatic struct menu *current_menu;\nstatic int child_count;\nstatic int single_menu_mode;\nstatic int show_all_options;\nstatic int save_and_exit;\nstatic int silent;\n\nstatic void conf(struct menu *menu, struct menu *active_menu);\nstatic void conf_choice(struct menu *menu);\nstatic void conf_string(struct menu *menu);\nstatic void conf_load(void);\nstatic void conf_save(void);\nstatic int show_textbox_ext(const char *title, char *text, int r, int c,\n\t\t\t    int *keys, int *vscroll, int *hscroll,\n\t\t\t    update_text_fn update_text, void *data);\nstatic void show_textbox(const char *title, const char *text, int r, int c);\nstatic void show_helptext(const char *title, const char *text);\nstatic void show_help(struct menu *menu);\n\nstatic char filename[PATH_MAX+1];\nstatic void set_config_filename(const char *config_filename)\n{\n\tstatic char menu_backtitle[PATH_MAX+128];\n\n\tsnprintf(menu_backtitle, sizeof(menu_backtitle), \"%s - %s\",\n\t\t config_filename, rootmenu.prompt->text);\n\tset_dialog_backtitle(menu_backtitle);\n\n\tsnprintf(filename, sizeof(filename), \"%s\", config_filename);\n}\n\nstruct subtitle_part {\n\tstruct list_head entries;\n\tconst char *text;\n};\nstatic LIST_HEAD(trail);\n\nstatic struct subtitle_list *subtitles;\nstatic void set_subtitle(void)\n{\n\tstruct subtitle_part *sp;\n\tstruct subtitle_list *pos, *tmp;\n\n\tfor (pos = subtitles; pos != NULL; pos = tmp) {\n\t\ttmp = pos->next;\n\t\tfree(pos);\n\t}\n\n\tsubtitles = NULL;\n\tlist_for_each_entry(sp, &trail, entries) {\n\t\tif (sp->text) {\n\t\t\tif (pos) {\n\t\t\t\tpos->next = xcalloc(1, sizeof(*pos));\n\t\t\t\tpos = pos->next;\n\t\t\t} else {\n\t\t\t\tsubtitles = pos = xcalloc(1, sizeof(*pos));\n\t\t\t}\n\t\t\tpos->text = sp->text;\n\t\t}\n\t}\n\n\tset_dialog_subtitles(subtitles);\n}\n\nstatic void reset_subtitle(void)\n{\n\tstruct subtitle_list *pos, *tmp;\n\n\tfor (pos = subtitles; pos != NULL; pos = tmp) {\n\t\ttmp = pos->next;\n\t\tfree(pos);\n\t}\n\tsubtitles = NULL;\n\tset_dialog_subtitles(subtitles);\n}\n\nstruct search_data {\n\tstruct list_head *head;\n\tstruct menu **targets;\n\tint *keys;\n};\n\nstatic void update_text(char *buf, size_t start, size_t end, void *_data)\n{\n\tstruct search_data *data = _data;\n\tstruct jump_key *pos;\n\tint k = 0;\n\n\tlist_for_each_entry(pos, data->head, entries) {\n\t\tif (pos->offset >= start && pos->offset < end) {\n\t\t\tchar header[4];\n\n\t\t\tif (k < JUMP_NB) {\n\t\t\t\tint key = '0' + (pos->index % JUMP_NB) + 1;\n\n\t\t\t\tsprintf(header, \"(%c)\", key);\n\t\t\t\tdata->keys[k] = key;\n\t\t\t\tdata->targets[k] = pos->target;\n\t\t\t\tk++;\n\t\t\t} else {\n\t\t\t\tsprintf(header, \"   \");\n\t\t\t}\n\n\t\t\tmemcpy(buf + pos->offset, header, sizeof(header) - 1);\n\t\t}\n\t}\n\tdata->keys[k] = 0;\n}\n\nstatic void search_conf(void)\n{\n\tstruct symbol **sym_arr;\n\tstruct gstr res;\n\tstruct gstr title;\n\tchar *dialog_input;\n\tint dres, vscroll = 0, hscroll = 0;\n\tbool again;\n\tstruct gstr sttext;\n\tstruct subtitle_part stpart;\n\n\ttitle = str_new();\n\tstr_printf( &title, \"Enter (sub)string or regexp to search for \"\n\t\t\t      \"(with or without \\\"%s\\\")\", CONFIG_);\n\nagain:\n\tdialog_clear();\n\tdres = dialog_inputbox(\"Search Configuration Parameter\",\n\t\t\t      str_get(&title),\n\t\t\t      10, 75, \"\");\n\tswitch (dres) {\n\tcase 0:\n\t\tbreak;\n\tcase 1:\n\t\tshow_helptext(\"Search Configuration\", search_help);\n\t\tgoto again;\n\tdefault:\n\t\tstr_free(&title);\n\t\treturn;\n\t}\n\n\t/* strip the prefix if necessary */\n\tdialog_input = dialog_input_result;\n\tif (strncasecmp(dialog_input_result, CONFIG_, strlen(CONFIG_)) == 0)\n\t\tdialog_input += strlen(CONFIG_);\n\n\tsttext = str_new();\n\tstr_printf(&sttext, \"Search (%s)\", dialog_input_result);\n\tstpart.text = str_get(&sttext);\n\tlist_add_tail(&stpart.entries, &trail);\n\n\tsym_arr = sym_re_search(dialog_input);\n\tdo {\n\t\tLIST_HEAD(head);\n\t\tstruct menu *targets[JUMP_NB];\n\t\tint keys[JUMP_NB + 1], i;\n\t\tstruct search_data data = {\n\t\t\t.head = &head,\n\t\t\t.targets = targets,\n\t\t\t.keys = keys,\n\t\t};\n\t\tstruct jump_key *pos, *tmp;\n\n\t\tres = get_relations_str(sym_arr, &head);\n\t\tset_subtitle();\n\t\tdres = show_textbox_ext(\"Search Results\", (char *)\n\t\t\t\t\tstr_get(&res), 0, 0, keys, &vscroll,\n\t\t\t\t\t&hscroll, &update_text, (void *)\n\t\t\t\t\t&data);\n\t\tagain = false;\n\t\tfor (i = 0; i < JUMP_NB && keys[i]; i++)\n\t\t\tif (dres == keys[i]) {\n\t\t\t\tconf(targets[i]->parent, targets[i]);\n\t\t\t\tagain = true;\n\t\t\t}\n\t\tstr_free(&res);\n\t\tlist_for_each_entry_safe(pos, tmp, &head, entries)\n\t\t\tfree(pos);\n\t} while (again);\n\tfree(sym_arr);\n\tstr_free(&title);\n\tlist_del(trail.prev);\n\tstr_free(&sttext);\n}\n\nstatic void build_conf(struct menu *menu)\n{\n\tstruct symbol *sym;\n\tstruct property *prop;\n\tstruct menu *child;\n\tint type, tmp, doint = 2;\n\ttristate val;\n\tchar ch;\n\tbool visible;\n\n\t/*\n\t * note: menu_is_visible() has side effect that it will\n\t * recalc the value of the symbol.\n\t */\n\tvisible = menu_is_visible(menu);\n\tif (show_all_options && !menu_has_prompt(menu))\n\t\treturn;\n\telse if (!show_all_options && !visible)\n\t\treturn;\n\n\tsym = menu->sym;\n\tprop = menu->prompt;\n\tif (!sym) {\n\t\tif (prop && menu != current_menu) {\n\t\t\tconst char *prompt = menu_get_prompt(menu);\n\t\t\tswitch (prop->type) {\n\t\t\tcase P_MENU:\n\t\t\t\tchild_count++;\n\t\t\t\tif (single_menu_mode) {\n\t\t\t\t\titem_make(\"%s%*c%s\",\n\t\t\t\t\t\t  menu->data ? \"-->\" : \"++>\",\n\t\t\t\t\t\t  indent + 1, ' ', prompt);\n\t\t\t\t} else\n\t\t\t\t\titem_make(\"   %*c%s  %s\",\n\t\t\t\t\t\t  indent + 1, ' ', prompt,\n\t\t\t\t\t\t  menu_is_empty(menu) ? \"----\" : \"--->\");\n\t\t\t\titem_set_tag('m');\n\t\t\t\titem_set_data(menu);\n\t\t\t\tif (single_menu_mode && menu->data)\n\t\t\t\t\tgoto conf_childs;\n\t\t\t\treturn;\n\t\t\tcase P_COMMENT:\n\t\t\t\tif (prompt) {\n\t\t\t\t\tchild_count++;\n\t\t\t\t\titem_make(\"   %*c*** %s ***\", indent + 1, ' ', prompt);\n\t\t\t\t\titem_set_tag(':');\n\t\t\t\t\titem_set_data(menu);\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tdefault:\n\t\t\t\tif (prompt) {\n\t\t\t\t\tchild_count++;\n\t\t\t\t\titem_make(\"---%*c%s\", indent + 1, ' ', prompt);\n\t\t\t\t\titem_set_tag(':');\n\t\t\t\t\titem_set_data(menu);\n\t\t\t\t}\n\t\t\t}\n\t\t} else\n\t\t\tdoint = 0;\n\t\tgoto conf_childs;\n\t}\n\n\ttype = sym_get_type(sym);\n\tif (sym_is_choice(sym)) {\n\t\tstruct symbol *def_sym = sym_get_choice_value(sym);\n\t\tstruct menu *def_menu = NULL;\n\n\t\tchild_count++;\n\t\tfor (child = menu->list; child; child = child->next) {\n\t\t\tif (menu_is_visible(child) && child->sym == def_sym)\n\t\t\t\tdef_menu = child;\n\t\t}\n\n\t\tval = sym_get_tristate_value(sym);\n\t\tif (sym_is_changeable(sym)) {\n\t\t\tswitch (type) {\n\t\t\tcase S_BOOLEAN:\n\t\t\t\titem_make(\"[%c]\", val == no ? ' ' : '*');\n\t\t\t\tbreak;\n\t\t\tcase S_TRISTATE:\n\t\t\t\tswitch (val) {\n\t\t\t\tcase yes: ch = '*'; break;\n\t\t\t\tcase mod: ch = 'M'; break;\n\t\t\t\tdefault:  ch = ' '; break;\n\t\t\t\t}\n\t\t\t\titem_make(\"<%c>\", ch);\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\titem_set_tag('t');\n\t\t\titem_set_data(menu);\n\t\t} else {\n\t\t\titem_make(\"   \");\n\t\t\titem_set_tag(def_menu ? 't' : ':');\n\t\t\titem_set_data(menu);\n\t\t}\n\n\t\titem_add_str(\"%*c%s\", indent + 1, ' ', menu_get_prompt(menu));\n\t\tif (val == yes) {\n\t\t\tif (def_menu) {\n\t\t\t\titem_add_str(\" (%s)\", menu_get_prompt(def_menu));\n\t\t\t\titem_add_str(\"  --->\");\n\t\t\t\tif (def_menu->list) {\n\t\t\t\t\tindent += 2;\n\t\t\t\t\tbuild_conf(def_menu);\n\t\t\t\t\tindent -= 2;\n\t\t\t\t}\n\t\t\t}\n\t\t\treturn;\n\t\t}\n\t} else {\n\t\tif (menu == current_menu) {\n\t\t\titem_make(\"---%*c%s\", indent + 1, ' ', menu_get_prompt(menu));\n\t\t\titem_set_tag(':');\n\t\t\titem_set_data(menu);\n\t\t\tgoto conf_childs;\n\t\t}\n\t\tchild_count++;\n\t\tval = sym_get_tristate_value(sym);\n\t\tif (sym_is_choice_value(sym) && val == yes) {\n\t\t\titem_make(\"   \");\n\t\t\titem_set_tag(':');\n\t\t\titem_set_data(menu);\n\t\t} else {\n\t\t\tswitch (type) {\n\t\t\tcase S_BOOLEAN:\n\t\t\t\tif (sym_is_changeable(sym))\n\t\t\t\t\titem_make(\"[%c]\", val == no ? ' ' : '*');\n\t\t\t\telse\n\t\t\t\t\titem_make(\"-%c-\", val == no ? ' ' : '*');\n\t\t\t\titem_set_tag('t');\n\t\t\t\titem_set_data(menu);\n\t\t\t\tbreak;\n\t\t\tcase S_TRISTATE:\n\t\t\t\tswitch (val) {\n\t\t\t\tcase yes: ch = '*'; break;\n\t\t\t\tcase mod: ch = 'M'; break;\n\t\t\t\tdefault:  ch = ' '; break;\n\t\t\t\t}\n\t\t\t\tif (sym_is_changeable(sym)) {\n\t\t\t\t\tif (sym->rev_dep.tri == mod)\n\t\t\t\t\t\titem_make(\"{%c}\", ch);\n\t\t\t\t\telse\n\t\t\t\t\t\titem_make(\"<%c>\", ch);\n\t\t\t\t} else\n\t\t\t\t\titem_make(\"-%c-\", ch);\n\t\t\t\titem_set_tag('t');\n\t\t\t\titem_set_data(menu);\n\t\t\t\tbreak;\n\t\t\tdefault:\n\t\t\t\ttmp = 2 + strlen(sym_get_string_value(sym)); /* () = 2 */\n\t\t\t\titem_make(\"(%s)\", sym_get_string_value(sym));\n\t\t\t\ttmp = indent - tmp + 4;\n\t\t\t\tif (tmp < 0)\n\t\t\t\t\ttmp = 0;\n\t\t\t\titem_add_str(\"%*c%s%s\", tmp, ' ', menu_get_prompt(menu),\n\t\t\t\t\t     (sym_has_value(sym) || !sym_is_changeable(sym)) ?\n\t\t\t\t\t     \"\" : \" (NEW)\");\n\t\t\t\titem_set_tag('s');\n\t\t\t\titem_set_data(menu);\n\t\t\t\tgoto conf_childs;\n\t\t\t}\n\t\t}\n\t\titem_add_str(\"%*c%s%s\", indent + 1, ' ', menu_get_prompt(menu),\n\t\t\t  (sym_has_value(sym) || !sym_is_changeable(sym)) ?\n\t\t\t  \"\" : \" (NEW)\");\n\t\tif (menu->prompt->type == P_MENU) {\n\t\t\titem_add_str(\"  %s\", menu_is_empty(menu) ? \"----\" : \"--->\");\n\t\t\treturn;\n\t\t}\n\t}\n\nconf_childs:\n\tindent += doint;\n\tfor (child = menu->list; child; child = child->next)\n\t\tbuild_conf(child);\n\tindent -= doint;\n}\n\nstatic void conf(struct menu *menu, struct menu *active_menu)\n{\n\tstruct menu *submenu;\n\tconst char *prompt = menu_get_prompt(menu);\n\tstruct subtitle_part stpart;\n\tstruct symbol *sym;\n\tint res;\n\tint s_scroll = 0;\n\n\tif (menu != &rootmenu)\n\t\tstpart.text = menu_get_prompt(menu);\n\telse\n\t\tstpart.text = NULL;\n\tlist_add_tail(&stpart.entries, &trail);\n\n\twhile (1) {\n\t\titem_reset();\n\t\tcurrent_menu = menu;\n\t\tbuild_conf(menu);\n\t\tif (!child_count)\n\t\t\tbreak;\n\t\tset_subtitle();\n\t\tdialog_clear();\n\t\tres = dialog_menu(prompt ? prompt : \"Main Menu\",\n\t\t\t\t  menu_instructions,\n\t\t\t\t  active_menu, &s_scroll);\n\t\tif (res == 1 || res == KEY_ESC || res == -ERRDISPLAYTOOSMALL)\n\t\t\tbreak;\n\t\tif (item_count() != 0) {\n\t\t\tif (!item_activate_selected())\n\t\t\t\tcontinue;\n\t\t\tif (!item_tag())\n\t\t\t\tcontinue;\n\t\t}\n\t\tsubmenu = item_data();\n\t\tactive_menu = item_data();\n\t\tif (submenu)\n\t\t\tsym = submenu->sym;\n\t\telse\n\t\t\tsym = NULL;\n\n\t\tswitch (res) {\n\t\tcase 0:\n\t\t\tswitch (item_tag()) {\n\t\t\tcase 'm':\n\t\t\t\tif (single_menu_mode)\n\t\t\t\t\tsubmenu->data = (void *) (long) !submenu->data;\n\t\t\t\telse\n\t\t\t\t\tconf(submenu, NULL);\n\t\t\t\tbreak;\n\t\t\tcase 't':\n\t\t\t\tif (sym_is_choice(sym) && sym_get_tristate_value(sym) == yes)\n\t\t\t\t\tconf_choice(submenu);\n\t\t\t\telse if (submenu->prompt->type == P_MENU)\n\t\t\t\t\tconf(submenu, NULL);\n\t\t\t\tbreak;\n\t\t\tcase 's':\n\t\t\t\tconf_string(submenu);\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\tbreak;\n\t\tcase 2:\n\t\t\tif (sym)\n\t\t\t\tshow_help(submenu);\n\t\t\telse {\n\t\t\t\treset_subtitle();\n\t\t\t\tshow_helptext(\"README\", mconf_readme);\n\t\t\t}\n\t\t\tbreak;\n\t\tcase 3:\n\t\t\treset_subtitle();\n\t\t\tconf_save();\n\t\t\tbreak;\n\t\tcase 4:\n\t\t\treset_subtitle();\n\t\t\tconf_load();\n\t\t\tbreak;\n\t\tcase 5:\n\t\t\tif (item_is_tag('t')) {\n\t\t\t\tif (sym_set_tristate_value(sym, yes))\n\t\t\t\t\tbreak;\n\t\t\t\tif (sym_set_tristate_value(sym, mod))\n\t\t\t\t\tshow_textbox(NULL, setmod_text, 6, 74);\n\t\t\t}\n\t\t\tbreak;\n\t\tcase 6:\n\t\t\tif (item_is_tag('t'))\n\t\t\t\tsym_set_tristate_value(sym, no);\n\t\t\tbreak;\n\t\tcase 7:\n\t\t\tif (item_is_tag('t'))\n\t\t\t\tsym_set_tristate_value(sym, mod);\n\t\t\tbreak;\n\t\tcase 8:\n\t\t\tif (item_is_tag('t'))\n\t\t\t\tsym_toggle_tristate_value(sym);\n\t\t\telse if (item_is_tag('m'))\n\t\t\t\tconf(submenu, NULL);\n\t\t\tbreak;\n\t\tcase 9:\n\t\t\tsearch_conf();\n\t\t\tbreak;\n\t\tcase 10:\n\t\t\tshow_all_options = !show_all_options;\n\t\t\tbreak;\n\t\t}\n\t}\n\n\tlist_del(trail.prev);\n}\n\nstatic int show_textbox_ext(const char *title, char *text, int r, int c, int\n\t\t\t    *keys, int *vscroll, int *hscroll, update_text_fn\n\t\t\t    update_text, void *data)\n{\n\tdialog_clear();\n\treturn dialog_textbox(title, text, r, c, keys, vscroll, hscroll,\n\t\t\t      update_text, data);\n}\n\nstatic void show_textbox(const char *title, const char *text, int r, int c)\n{\n\tshow_textbox_ext(title, (char *) text, r, c, (int []) {0}, NULL, NULL,\n\t\t\t NULL, NULL);\n}\n\nstatic void show_helptext(const char *title, const char *text)\n{\n\tshow_textbox(title, text, 0, 0);\n}\n\nstatic void conf_message_callback(const char *s)\n{\n\tif (save_and_exit) {\n\t\tif (!silent)\n\t\t\tprintf(\"%s\", s);\n\t} else {\n\t\tshow_textbox(NULL, s, 6, 60);\n\t}\n}\n\nstatic void show_help(struct menu *menu)\n{\n\tstruct gstr help = str_new();\n\n\thelp.max_width = getmaxx(stdscr) - 10;\n\tmenu_get_ext_help(menu, &help);\n\n\tshow_helptext(menu_get_prompt(menu), str_get(&help));\n\tstr_free(&help);\n}\n\nstatic void conf_choice(struct menu *menu)\n{\n\tconst char *prompt = menu_get_prompt(menu);\n\tstruct menu *child;\n\tstruct symbol *active;\n\tstruct property *prop;\n\n\tactive = sym_get_choice_value(menu->sym);\n\twhile (1) {\n\t\tint res;\n\t\tint selected;\n\t\titem_reset();\n\n\t\tcurrent_menu = menu;\n\t\tfor (child = menu->list; child; child = child->next) {\n\t\t\tif (!menu_is_visible(child))\n\t\t\t\tcontinue;\n\t\t\tif (child->sym)\n\t\t\t\titem_make(\"%s\", menu_get_prompt(child));\n\t\t\telse {\n\t\t\t\titem_make(\"*** %s ***\", menu_get_prompt(child));\n\t\t\t\titem_set_tag(':');\n\t\t\t}\n\t\t\titem_set_data(child);\n\t\t\tif (child->sym == active)\n\t\t\t\titem_set_selected(1);\n\t\t\tif (child->sym == sym_get_choice_value(menu->sym))\n\t\t\t\titem_set_tag('X');\n\t\t}\n\t\tdialog_clear();\n\t\tres = dialog_checklist(prompt ? prompt : \"Main Menu\",\n\t\t\t\t\tradiolist_instructions,\n\t\t\t\t\tMENUBOX_HEIGTH_MIN,\n\t\t\t\t\tMENUBOX_WIDTH_MIN,\n\t\t\t\t\tCHECKLIST_HEIGTH_MIN);\n\t\tselected = item_activate_selected();\n\t\tswitch (res) {\n\t\tcase 0:\n\t\t\tif (selected) {\n\t\t\t\tchild = item_data();\n\t\t\t\tif (!child->sym)\n\t\t\t\t\tbreak;\n\n\t\t\t\tif (sym_get_tristate_value(child->sym) != yes) {\n\t\t\t\t\tfor_all_properties(menu->sym, prop, P_RESET) {\n\t\t\t\t\t\tif (expr_calc_value(prop->visible.expr) == no)\n\t\t\t\t\t\t\tcontinue;\n\n\t\t\t\t\t\tconf_reset(S_DEF_USER);\n\t\t\t\t\t\tbreak;\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\tsym_set_tristate_value(child->sym, yes);\n\t\t\t}\n\t\t\treturn;\n\t\tcase 1:\n\t\t\tif (selected) {\n\t\t\t\tchild = item_data();\n\t\t\t\tshow_help(child);\n\t\t\t\tactive = child->sym;\n\t\t\t} else\n\t\t\t\tshow_help(menu);\n\t\t\tbreak;\n\t\tcase KEY_ESC:\n\t\t\treturn;\n\t\tcase -ERRDISPLAYTOOSMALL:\n\t\t\treturn;\n\t\t}\n\t}\n}\n\nstatic void conf_string(struct menu *menu)\n{\n\tconst char *prompt = menu_get_prompt(menu);\n\n\twhile (1) {\n\t\tint res;\n\t\tconst char *heading;\n\n\t\tswitch (sym_get_type(menu->sym)) {\n\t\tcase S_INT:\n\t\t\theading = inputbox_instructions_int;\n\t\t\tbreak;\n\t\tcase S_HEX:\n\t\t\theading = inputbox_instructions_hex;\n\t\t\tbreak;\n\t\tcase S_STRING:\n\t\t\theading = inputbox_instructions_string;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\theading = \"Internal mconf error!\";\n\t\t}\n\t\tdialog_clear();\n\t\tres = dialog_inputbox(prompt ? prompt : \"Main Menu\",\n\t\t\t\t      heading, 10, 75,\n\t\t\t\t      sym_get_string_value(menu->sym));\n\t\tswitch (res) {\n\t\tcase 0:\n\t\t\tif (sym_set_string_value(menu->sym, dialog_input_result))\n\t\t\t\treturn;\n\t\t\tshow_textbox(NULL, \"You have made an invalid entry.\", 5, 43);\n\t\t\tbreak;\n\t\tcase 1:\n\t\t\tshow_help(menu);\n\t\t\tbreak;\n\t\tcase KEY_ESC:\n\t\t\treturn;\n\t\t}\n\t}\n}\n\nstatic void conf_load(void)\n{\n\n\twhile (1) {\n\t\tint res;\n\t\tdialog_clear();\n\t\tres = dialog_inputbox(NULL, load_config_text,\n\t\t\t\t      11, 55, filename);\n\t\tswitch(res) {\n\t\tcase 0:\n\t\t\tif (!dialog_input_result[0])\n\t\t\t\treturn;\n\t\t\tif (!conf_read(dialog_input_result)) {\n\t\t\t\tset_config_filename(dialog_input_result);\n\t\t\t\tconf_set_changed(true);\n\t\t\t\treturn;\n\t\t\t}\n\t\t\tshow_textbox(NULL, \"File does not exist!\", 5, 38);\n\t\t\tbreak;\n\t\tcase 1:\n\t\t\tshow_helptext(\"Load Alternate Configuration\", load_config_help);\n\t\t\tbreak;\n\t\tcase KEY_ESC:\n\t\t\treturn;\n\t\t}\n\t}\n}\n\nstatic void conf_save(void)\n{\n\twhile (1) {\n\t\tint res;\n\t\tdialog_clear();\n\t\tres = dialog_inputbox(NULL, save_config_text,\n\t\t\t\t      11, 55, filename);\n\t\tswitch(res) {\n\t\tcase 0:\n\t\t\tif (!dialog_input_result[0])\n\t\t\t\treturn;\n\t\t\tif (!conf_write(dialog_input_result)) {\n\t\t\t\tset_config_filename(dialog_input_result);\n\t\t\t\treturn;\n\t\t\t}\n\t\t\tshow_textbox(NULL, \"Can't create file!\", 5, 60);\n\t\t\tbreak;\n\t\tcase 1:\n\t\t\tshow_helptext(\"Save Alternate Configuration\", save_config_help);\n\t\t\tbreak;\n\t\tcase KEY_ESC:\n\t\t\treturn;\n\t\t}\n\t}\n}\n\nstatic int handle_exit(void)\n{\n\tint res;\n\n\tsave_and_exit = 1;\n\treset_subtitle();\n\tdialog_clear();\n\tif (conf_get_changed())\n\t\tres = dialog_yesno(NULL,\n\t\t\t\t   \"Do you wish to save your new configuration?\\n\"\n\t\t\t\t     \"(Press <ESC><ESC> to continue kernel configuration.)\",\n\t\t\t\t   6, 60);\n\telse\n\t\tres = -1;\n\n\tend_dialog(saved_x, saved_y);\n\n\tswitch (res) {\n\tcase 0:\n\t\tif (conf_write(filename)) {\n\t\t\tfprintf(stderr, \"\\n\\n\"\n\t\t\t\t\t  \"Error while writing of the configuration.\\n\"\n\t\t\t\t\t  \"Your configuration changes were NOT saved.\"\n\t\t\t\t\t  \"\\n\\n\");\n\t\t\treturn 1;\n\t\t}\n\t\tconf_write_autoconf(0);\n\t\t/* fall through */\n\tcase -1:\n\t\tif (!silent)\n\t\t\tprintf(\"\\n\\n\"\n\t\t\t\t \"*** End of the configuration.\\n\"\n\t\t\t\t \"*** Execute 'make' to start the build or try 'make help'.\"\n\t\t\t\t \"\\n\\n\");\n\t\tres = 0;\n\t\tbreak;\n\tdefault:\n\t\tif (!silent)\n\t\t\tfprintf(stderr, \"\\n\\n\"\n\t\t\t\t\t  \"Your configuration changes were NOT saved.\"\n\t\t\t\t\t  \"\\n\\n\");\n\t\tif (res != KEY_ESC)\n\t\t\tres = 0;\n\t}\n\n\treturn res;\n}\n\nstatic void sig_handler(int signo)\n{\n\texit(handle_exit());\n}\n\nint main(int ac, char **av)\n{\n\tchar *mode;\n\tint res;\n\n\tsignal(SIGINT, sig_handler);\n\n\tif (ac > 1 && strcmp(av[1], \"-s\") == 0) {\n\t\tsilent = 1;\n\t\t/* Silence conf_read() until the real callback is set up */\n\t\tconf_set_message_callback(NULL);\n\t\tav++;\n\t}\n\tconf_parse(av[1]);\n\tconf_read(NULL);\n\n\tmode = getenv(\"MENUCONFIG_MODE\");\n\tif (mode) {\n\t\tif (!strcasecmp(mode, \"single_menu\"))\n\t\t\tsingle_menu_mode = 1;\n\t}\n\n\tif (init_dialog(NULL)) {\n\t\tfprintf(stderr, \"Your display is too small to run Menuconfig!\\n\");\n\t\tfprintf(stderr, \"It must be at least 19 lines by 80 columns.\\n\");\n\t\treturn 1;\n\t}\n\n\tset_config_filename(conf_get_configname());\n\tconf_set_message_callback(conf_message_callback);\n\tdo {\n\t\tconf(&rootmenu, NULL);\n\t\tres = handle_exit();\n\t} while (res == KEY_ESC);\n\n\treturn res;\n}\n"
  },
  {
    "path": "scripts/config/menu.c",
    "content": "// SPDX-License-Identifier: GPL-2.0-only\n/*\n * Copyright (C) 2002 Roman Zippel <zippel@linux-m68k.org>\n */\n\n#include <ctype.h>\n#include <stdarg.h>\n#include <stdlib.h>\n#include <string.h>\n\n#include \"lkc.h\"\n#include \"internal.h\"\n\nstatic const char nohelp_text[] = \"There is no help available for this option.\";\n\nstruct menu rootmenu;\nstatic struct menu **last_entry_ptr;\n\nstruct file *file_list;\nstruct file *current_file;\n\nvoid menu_warn(struct menu *menu, const char *fmt, ...)\n{\n\tva_list ap;\n\tva_start(ap, fmt);\n\tfprintf(stderr, \"%s:%d:warning: \", menu->file->name, menu->lineno);\n\tvfprintf(stderr, fmt, ap);\n\tfprintf(stderr, \"\\n\");\n\tva_end(ap);\n}\n\nstatic void prop_warn(struct property *prop, const char *fmt, ...)\n{\n\tva_list ap;\n\tva_start(ap, fmt);\n\tfprintf(stderr, \"%s:%d:warning: \", prop->file->name, prop->lineno);\n\tvfprintf(stderr, fmt, ap);\n\tfprintf(stderr, \"\\n\");\n\tva_end(ap);\n}\n\nvoid _menu_init(void)\n{\n\tcurrent_entry = current_menu = &rootmenu;\n\tlast_entry_ptr = &rootmenu.list;\n}\n\nvoid menu_add_entry(struct symbol *sym)\n{\n\tstruct menu *menu;\n\n\tmenu = xmalloc(sizeof(*menu));\n\tmemset(menu, 0, sizeof(*menu));\n\tmenu->sym = sym;\n\tmenu->parent = current_menu;\n\tmenu->file = current_file;\n\tmenu->lineno = zconf_lineno();\n\n\t*last_entry_ptr = menu;\n\tlast_entry_ptr = &menu->next;\n\tcurrent_entry = menu;\n\tif (sym)\n\t\tmenu_add_symbol(P_SYMBOL, sym, NULL);\n}\n\nstruct menu *menu_add_menu(void)\n{\n\tlast_entry_ptr = &current_entry->list;\n\tcurrent_menu = current_entry;\n\treturn current_menu;\n}\n\nvoid menu_end_menu(void)\n{\n\tlast_entry_ptr = &current_menu->next;\n\tcurrent_menu = current_menu->parent;\n}\n\n/*\n * Rewrites 'm' to 'm' && MODULES, so that it evaluates to 'n' when running\n * without modules\n */\nstatic struct expr *rewrite_m(struct expr *e)\n{\n\tif (!e)\n\t\treturn e;\n\n\tswitch (e->type) {\n\tcase E_NOT:\n\t\te->left.expr = rewrite_m(e->left.expr);\n\t\tbreak;\n\tcase E_OR:\n\tcase E_AND:\n\t\te->left.expr = rewrite_m(e->left.expr);\n\t\te->right.expr = rewrite_m(e->right.expr);\n\t\tbreak;\n\tcase E_SYMBOL:\n\t\t/* change 'm' into 'm' && MODULES */\n\t\tif (e->left.sym == &symbol_mod)\n\t\t\treturn expr_alloc_and(e, expr_alloc_symbol(modules_sym));\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\treturn e;\n}\n\nvoid menu_add_dep(struct expr *dep)\n{\n\tcurrent_entry->dep = expr_alloc_and(current_entry->dep, dep);\n}\n\nvoid menu_set_type(int type)\n{\n\tstruct symbol *sym = current_entry->sym;\n\n\tif (sym->type == type)\n\t\treturn;\n\tif (sym->type == S_UNKNOWN) {\n\t\tsym->type = type;\n\t\treturn;\n\t}\n\tmenu_warn(current_entry,\n\t\t\"ignoring type redefinition of '%s' from '%s' to '%s'\",\n\t\tsym->name ? sym->name : \"<choice>\",\n\t\tsym_type_name(sym->type), sym_type_name(type));\n}\n\nstruct property *menu_add_prop(enum prop_type type, struct expr *expr,\n\t\t\t       struct expr *dep)\n{\n\tstruct property *prop;\n\n\tprop = xmalloc(sizeof(*prop));\n\tmemset(prop, 0, sizeof(*prop));\n\tprop->type = type;\n\tprop->file = current_file;\n\tprop->lineno = zconf_lineno();\n\tprop->menu = current_entry;\n\tprop->expr = expr;\n\tprop->visible.expr = dep;\n\n\t/* append property to the prop list of symbol */\n\tif (current_entry->sym) {\n\t\tstruct property **propp;\n\n\t\tfor (propp = &current_entry->sym->prop;\n\t\t     *propp;\n\t\t     propp = &(*propp)->next)\n\t\t\t;\n\t\t*propp = prop;\n\t}\n\n\treturn prop;\n}\n\nstruct property *menu_add_prompt(enum prop_type type, char *prompt,\n\t\t\t\t struct expr *dep)\n{\n\tstruct property *prop = menu_add_prop(type, NULL, dep);\n\n\tif (isspace(*prompt)) {\n\t\tprop_warn(prop, \"leading whitespace ignored\");\n\t\twhile (isspace(*prompt))\n\t\t\tprompt++;\n\t}\n\tif (current_entry->prompt)\n\t\tprop_warn(prop, \"prompt redefined\");\n\n\t/* Apply all upper menus' visibilities to actual prompts. */\n\tif (type == P_PROMPT) {\n\t\tstruct menu *menu = current_entry;\n\n\t\twhile ((menu = menu->parent) != NULL) {\n\t\t\tstruct expr *dup_expr;\n\n\t\t\tif (!menu->visibility)\n\t\t\t\tcontinue;\n\t\t\t/*\n\t\t\t * Do not add a reference to the menu's visibility\n\t\t\t * expression but use a copy of it. Otherwise the\n\t\t\t * expression reduction functions will modify\n\t\t\t * expressions that have multiple references which\n\t\t\t * can cause unwanted side effects.\n\t\t\t */\n\t\t\tdup_expr = expr_copy(menu->visibility);\n\n\t\t\tprop->visible.expr = expr_alloc_and(prop->visible.expr,\n\t\t\t\t\t\t\t    dup_expr);\n\t\t}\n\t}\n\n\tcurrent_entry->prompt = prop;\n\tprop->text = prompt;\n\n\treturn prop;\n}\n\nvoid menu_add_visibility(struct expr *expr)\n{\n\tcurrent_entry->visibility = expr_alloc_and(current_entry->visibility,\n\t    expr);\n}\n\nvoid menu_add_expr(enum prop_type type, struct expr *expr, struct expr *dep)\n{\n\tmenu_add_prop(type, expr, dep);\n}\n\nvoid menu_add_symbol(enum prop_type type, struct symbol *sym, struct expr *dep)\n{\n\tmenu_add_prop(type, expr_alloc_symbol(sym), dep);\n}\n\nstatic int menu_validate_number(struct symbol *sym, struct symbol *sym2)\n{\n\treturn sym2->type == S_INT || sym2->type == S_HEX ||\n\t       (sym2->type == S_UNKNOWN && sym_string_valid(sym, sym2->name));\n}\n\nstatic void sym_check_prop(struct symbol *sym)\n{\n\tstruct property *prop;\n\tstruct symbol *sym2;\n\tchar *use;\n\n\tfor (prop = sym->prop; prop; prop = prop->next) {\n\t\tswitch (prop->type) {\n\t\tcase P_DEFAULT:\n\t\t\tif ((sym->type == S_STRING || sym->type == S_INT || sym->type == S_HEX) &&\n\t\t\t    prop->expr->type != E_SYMBOL)\n\t\t\t\tprop_warn(prop,\n\t\t\t\t    \"default for config symbol '%s'\"\n\t\t\t\t    \" must be a single symbol\", sym->name);\n\t\t\tif (prop->expr->type != E_SYMBOL)\n\t\t\t\tbreak;\n\t\t\tsym2 = prop_get_symbol(prop);\n\t\t\tif (sym->type == S_HEX || sym->type == S_INT) {\n\t\t\t\tif (!menu_validate_number(sym, sym2))\n\t\t\t\t\tprop_warn(prop,\n\t\t\t\t\t    \"'%s': number is invalid\",\n\t\t\t\t\t    sym->name);\n\t\t\t}\n\t\t\tif (sym_is_choice(sym)) {\n\t\t\t\tstruct property *choice_prop =\n\t\t\t\t\tsym_get_choice_prop(sym2);\n\n\t\t\t\tif (!choice_prop ||\n\t\t\t\t    prop_get_symbol(choice_prop) != sym)\n\t\t\t\t\tprop_warn(prop,\n\t\t\t\t\t\t  \"choice default symbol '%s' is not contained in the choice\",\n\t\t\t\t\t\t  sym2->name);\n\t\t\t}\n\t\t\tbreak;\n\t\tcase P_SELECT:\n\t\tcase P_IMPLY:\n\t\t\tuse = prop->type == P_SELECT ? \"select\" : \"imply\";\n\t\t\tsym2 = prop_get_symbol(prop);\n\t\t\tif (sym->type != S_BOOLEAN && sym->type != S_TRISTATE)\n\t\t\t\tprop_warn(prop,\n\t\t\t\t    \"config symbol '%s' uses %s, but is \"\n\t\t\t\t    \"not bool or tristate\", sym->name, use);\n\t\t\telse if (sym2->type != S_UNKNOWN &&\n\t\t\t\t sym2->type != S_BOOLEAN &&\n\t\t\t\t sym2->type != S_TRISTATE)\n\t\t\t\tprop_warn(prop,\n\t\t\t\t    \"'%s' has wrong type. '%s' only \"\n\t\t\t\t    \"accept arguments of bool and \"\n\t\t\t\t    \"tristate type\", sym2->name, use);\n\t\t\tbreak;\n\t\tcase P_RANGE:\n\t\t\tif (sym->type != S_INT && sym->type != S_HEX)\n\t\t\t\tprop_warn(prop, \"range is only allowed \"\n\t\t\t\t\t\t\"for int or hex symbols\");\n\t\t\tif (!menu_validate_number(sym, prop->expr->left.sym) ||\n\t\t\t    !menu_validate_number(sym, prop->expr->right.sym))\n\t\t\t\tprop_warn(prop, \"range is invalid\");\n\t\t\tbreak;\n\t\tdefault:\n\t\t\t;\n\t\t}\n\t}\n}\n\nvoid menu_finalize(struct menu *parent)\n{\n\tstruct menu *menu, *last_menu;\n\tstruct symbol *sym;\n\tstruct property *prop;\n\tstruct expr *parentdep, *basedep, *dep, *dep2, **ep;\n\n\tsym = parent->sym;\n\tif (parent->list) {\n\t\t/*\n\t\t * This menu node has children. We (recursively) process them\n\t\t * and propagate parent dependencies before moving on.\n\t\t */\n\n\t\tif (sym && sym_is_choice(sym)) {\n\t\t\tif (sym->type == S_UNKNOWN) {\n\t\t\t\t/* find the first choice value to find out choice type */\n\t\t\t\tcurrent_entry = parent;\n\t\t\t\tfor (menu = parent->list; menu; menu = menu->next) {\n\t\t\t\t\tif (menu->sym && menu->sym->type != S_UNKNOWN) {\n\t\t\t\t\t\tmenu_set_type(menu->sym->type);\n\t\t\t\t\t\tbreak;\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t\t/* set the type of the remaining choice values */\n\t\t\tfor (menu = parent->list; menu; menu = menu->next) {\n\t\t\t\tcurrent_entry = menu;\n\t\t\t\tif (menu->sym && menu->sym->type == S_UNKNOWN)\n\t\t\t\t\tmenu_set_type(sym->type);\n\t\t\t}\n\n\t\t\t/*\n\t\t\t * Use the choice itself as the parent dependency of\n\t\t\t * the contained items. This turns the mode of the\n\t\t\t * choice into an upper bound on the visibility of the\n\t\t\t * choice value symbols.\n\t\t\t */\n\t\t\tparentdep = expr_alloc_symbol(sym);\n\t\t} else {\n\t\t\t/* Menu node for 'menu', 'if' */\n\t\t\tparentdep = parent->dep;\n\t\t}\n\n\t\t/* For each child menu node... */\n\t\tfor (menu = parent->list; menu; menu = menu->next) {\n\t\t\t/*\n\t\t\t * Propagate parent dependencies to the child menu\n\t\t\t * node, also rewriting and simplifying expressions\n\t\t\t */\n\t\t\tbasedep = rewrite_m(menu->dep);\n\t\t\tbasedep = expr_transform(basedep);\n\t\t\tbasedep = expr_alloc_and(expr_copy(parentdep), basedep);\n\t\t\tbasedep = expr_eliminate_dups(basedep);\n\t\t\tmenu->dep = basedep;\n\n\t\t\tif (menu->sym)\n\t\t\t\t/*\n\t\t\t\t * Note: For symbols, all prompts are included\n\t\t\t\t * too in the symbol's own property list\n\t\t\t\t */\n\t\t\t\tprop = menu->sym->prop;\n\t\t\telse\n\t\t\t\t/*\n\t\t\t\t * For non-symbol menu nodes, we just need to\n\t\t\t\t * handle the prompt\n\t\t\t\t */\n\t\t\t\tprop = menu->prompt;\n\n\t\t\t/* For each property... */\n\t\t\tfor (; prop; prop = prop->next) {\n\t\t\t\tif (prop->menu != menu)\n\t\t\t\t\t/*\n\t\t\t\t\t * Two possibilities:\n\t\t\t\t\t *\n\t\t\t\t\t * 1. The property lacks dependencies\n\t\t\t\t\t *    and so isn't location-specific,\n\t\t\t\t\t *    e.g. an 'option'\n\t\t\t\t\t *\n\t\t\t\t\t * 2. The property belongs to a symbol\n\t\t\t\t\t *    defined in multiple locations and\n\t\t\t\t\t *    is from some other location. It\n\t\t\t\t\t *    will be handled there in that\n\t\t\t\t\t *    case.\n\t\t\t\t\t *\n\t\t\t\t\t * Skip the property.\n\t\t\t\t\t */\n\t\t\t\t\tcontinue;\n\n\t\t\t\t/*\n\t\t\t\t * Propagate parent dependencies to the\n\t\t\t\t * property's condition, rewriting and\n\t\t\t\t * simplifying expressions at the same time\n\t\t\t\t */\n\t\t\t\tdep = rewrite_m(prop->visible.expr);\n\t\t\t\tdep = expr_transform(dep);\n\t\t\t\tdep = expr_alloc_and(expr_copy(basedep), dep);\n\t\t\t\tdep = expr_eliminate_dups(dep);\n\t\t\t\tif (menu->sym && menu->sym->type != S_TRISTATE)\n\t\t\t\t\tdep = expr_trans_bool(dep);\n\t\t\t\tprop->visible.expr = dep;\n\n\t\t\t\t/*\n\t\t\t\t * Handle selects and implies, which modify the\n\t\t\t\t * dependencies of the selected/implied symbol\n\t\t\t\t */\n\t\t\t\tif (prop->type == P_SELECT) {\n\t\t\t\t\tstruct symbol *es = prop_get_symbol(prop);\n\t\t\t\t\tes->rev_dep.expr = expr_alloc_or(es->rev_dep.expr,\n\t\t\t\t\t\t\texpr_alloc_and(expr_alloc_symbol(menu->sym), expr_copy(dep)));\n\t\t\t\t} else if (prop->type == P_IMPLY) {\n\t\t\t\t\tstruct symbol *es = prop_get_symbol(prop);\n\t\t\t\t\tes->implied.expr = expr_alloc_or(es->implied.expr,\n\t\t\t\t\t\t\texpr_alloc_and(expr_alloc_symbol(menu->sym), expr_copy(dep)));\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n\t\tif (sym && sym_is_choice(sym))\n\t\t\texpr_free(parentdep);\n\n\t\t/*\n\t\t * Recursively process children in the same fashion before\n\t\t * moving on\n\t\t */\n\t\tfor (menu = parent->list; menu; menu = menu->next)\n\t\t\tmenu_finalize(menu);\n\t} else if (sym) {\n\t\t/*\n\t\t * Automatic submenu creation. If sym is a symbol and A, B, C,\n\t\t * ... are consecutive items (symbols, menus, ifs, etc.) that\n\t\t * all depend on sym, then the following menu structure is\n\t\t * created:\n\t\t *\n\t\t *\tsym\n\t\t *\t +-A\n\t\t *\t +-B\n\t\t *\t +-C\n\t\t *\t ...\n\t\t *\n\t\t * This also works recursively, giving the following structure\n\t\t * if A is a symbol and B depends on A:\n\t\t *\n\t\t *\tsym\n\t\t *\t +-A\n\t\t *\t | +-B\n\t\t *\t +-C\n\t\t *\t ...\n\t\t */\n\n\t\tbasedep = parent->prompt ? parent->prompt->visible.expr : NULL;\n\t\tbasedep = expr_trans_compare(basedep, E_UNEQUAL, &symbol_no);\n\t\tbasedep = expr_eliminate_dups(expr_transform(basedep));\n\n\t\t/* Examine consecutive elements after sym */\n\t\tlast_menu = NULL;\n\t\tfor (menu = parent->next; menu; menu = menu->next) {\n\t\t\tdep = menu->prompt ? menu->prompt->visible.expr : menu->dep;\n\t\t\tif (!expr_contains_symbol(dep, sym))\n\t\t\t\t/* No dependency, quit */\n\t\t\t\tbreak;\n\t\t\tif (expr_depends_symbol(dep, sym))\n\t\t\t\t/* Absolute dependency, put in submenu */\n\t\t\t\tgoto next;\n\n\t\t\t/*\n\t\t\t * Also consider it a dependency on sym if our\n\t\t\t * dependencies contain sym and are a \"superset\" of\n\t\t\t * sym's dependencies, e.g. '(sym || Q) && R' when sym\n\t\t\t * depends on R.\n\t\t\t *\n\t\t\t * Note that 'R' might be from an enclosing menu or if,\n\t\t\t * making this a more common case than it might seem.\n\t\t\t */\n\t\t\tdep = expr_trans_compare(dep, E_UNEQUAL, &symbol_no);\n\t\t\tdep = expr_eliminate_dups(expr_transform(dep));\n\t\t\tdep2 = expr_copy(basedep);\n\t\t\texpr_eliminate_eq(&dep, &dep2);\n\t\t\texpr_free(dep);\n\t\t\tif (!expr_is_yes(dep2)) {\n\t\t\t\t/* Not superset, quit */\n\t\t\t\texpr_free(dep2);\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\t/* Superset, put in submenu */\n\t\t\texpr_free(dep2);\n\t\tnext:\n\t\t\tmenu_finalize(menu);\n\t\t\tmenu->parent = parent;\n\t\t\tlast_menu = menu;\n\t\t}\n\t\texpr_free(basedep);\n\t\tif (last_menu) {\n\t\t\tparent->list = parent->next;\n\t\t\tparent->next = last_menu->next;\n\t\t\tlast_menu->next = NULL;\n\t\t}\n\n\t\tsym->dir_dep.expr = expr_alloc_or(sym->dir_dep.expr, parent->dep);\n\t}\n\tfor (menu = parent->list; menu; menu = menu->next) {\n\t\tif (sym && sym_is_choice(sym) &&\n\t\t    menu->sym && !sym_is_choice_value(menu->sym)) {\n\t\t\tcurrent_entry = menu;\n\t\t\tmenu->sym->flags |= SYMBOL_CHOICEVAL;\n\t\t\tif (!menu->prompt)\n\t\t\t\tmenu_warn(menu, \"choice value must have a prompt\");\n\t\t\tfor (prop = menu->sym->prop; prop; prop = prop->next) {\n\t\t\t\tif (prop->type == P_DEFAULT)\n\t\t\t\t\tprop_warn(prop, \"defaults for choice \"\n\t\t\t\t\t\t  \"values not supported\");\n\t\t\t\tif (prop->menu == menu)\n\t\t\t\t\tcontinue;\n\t\t\t\tif (prop->type == P_PROMPT &&\n\t\t\t\t    prop->menu->parent->sym != sym)\n\t\t\t\t\tprop_warn(prop, \"choice value used outside its choice group\");\n\t\t\t}\n\t\t\t/* Non-tristate choice values of tristate choices must\n\t\t\t * depend on the choice being set to Y. The choice\n\t\t\t * values' dependencies were propagated to their\n\t\t\t * properties above, so the change here must be re-\n\t\t\t * propagated.\n\t\t\t */\n\t\t\tif (sym->type == S_TRISTATE && menu->sym->type != S_TRISTATE) {\n\t\t\t\tbasedep = expr_alloc_comp(E_EQUAL, sym, &symbol_yes);\n\t\t\t\tmenu->dep = expr_alloc_and(basedep, menu->dep);\n\t\t\t\tfor (prop = menu->sym->prop; prop; prop = prop->next) {\n\t\t\t\t\tif (prop->menu != menu)\n\t\t\t\t\t\tcontinue;\n\t\t\t\t\tprop->visible.expr = expr_alloc_and(expr_copy(basedep),\n\t\t\t\t\t\t\t\t\t    prop->visible.expr);\n\t\t\t\t}\n\t\t\t}\n\t\t\tmenu_add_symbol(P_CHOICE, sym, NULL);\n\t\t\tprop = sym_get_choice_prop(sym);\n\t\t\tfor (ep = &prop->expr; *ep; ep = &(*ep)->left.expr)\n\t\t\t\t;\n\t\t\t*ep = expr_alloc_one(E_LIST, NULL);\n\t\t\t(*ep)->right.sym = menu->sym;\n\t\t}\n\n\t\t/*\n\t\t * This code serves two purposes:\n\t\t *\n\t\t * (1) Flattening 'if' blocks, which do not specify a submenu\n\t\t *     and only add dependencies.\n\t\t *\n\t\t *     (Automatic submenu creation might still create a submenu\n\t\t *     from an 'if' before this code runs.)\n\t\t *\n\t\t * (2) \"Undoing\" any automatic submenus created earlier below\n\t\t *     promptless symbols.\n\t\t *\n\t\t * Before:\n\t\t *\n\t\t *\tA\n\t\t *\tif ... (or promptless symbol)\n\t\t *\t +-B\n\t\t *\t +-C\n\t\t *\tD\n\t\t *\n\t\t * After:\n\t\t *\n\t\t *\tA\n\t\t *\tif ... (or promptless symbol)\n\t\t *\tB\n\t\t *\tC\n\t\t *\tD\n\t\t */\n\t\tif (menu->list && (!menu->prompt || !menu->prompt->text)) {\n\t\t\tfor (last_menu = menu->list; ; last_menu = last_menu->next) {\n\t\t\t\tlast_menu->parent = parent;\n\t\t\t\tif (!last_menu->next)\n\t\t\t\t\tbreak;\n\t\t\t}\n\t\t\tlast_menu->next = menu->next;\n\t\t\tmenu->next = menu->list;\n\t\t\tmenu->list = NULL;\n\t\t}\n\t}\n\n\tif (sym && !(sym->flags & SYMBOL_WARNED)) {\n\t\tif (sym->type == S_UNKNOWN)\n\t\t\tmenu_warn(parent, \"config symbol defined without type\");\n\n\t\tif (sym_is_choice(sym) && !parent->prompt)\n\t\t\tmenu_warn(parent, \"choice must have a prompt\");\n\n\t\t/* Check properties connected to this symbol */\n\t\tsym_check_prop(sym);\n\t\tsym->flags |= SYMBOL_WARNED;\n\t}\n\n\t/*\n\t * For non-optional choices, add a reverse dependency (corresponding to\n\t * a select) of '<visibility> && m'. This prevents the user from\n\t * setting the choice mode to 'n' when the choice is visible.\n\t *\n\t * This would also work for non-choice symbols, but only non-optional\n\t * choices clear SYMBOL_OPTIONAL as of writing. Choices are implemented\n\t * as a type of symbol.\n\t */\n\tif (sym && !sym_is_optional(sym) && parent->prompt) {\n\t\tsym->rev_dep.expr = expr_alloc_or(sym->rev_dep.expr,\n\t\t\t\texpr_alloc_and(parent->prompt->visible.expr,\n\t\t\t\t\texpr_alloc_symbol(&symbol_mod)));\n\t}\n}\n\nbool menu_has_prompt(struct menu *menu)\n{\n\tif (!menu->prompt)\n\t\treturn false;\n\treturn true;\n}\n\n/*\n * Determine if a menu is empty.\n * A menu is considered empty if it contains no or only\n * invisible entries.\n */\nbool menu_is_empty(struct menu *menu)\n{\n\tstruct menu *child;\n\n\tfor (child = menu->list; child; child = child->next) {\n\t\tif (menu_is_visible(child))\n\t\t\treturn(false);\n\t}\n\treturn(true);\n}\n\nbool menu_is_visible(struct menu *menu)\n{\n\tstruct menu *child;\n\tstruct symbol *sym;\n\ttristate visible;\n\n\tif (!menu->prompt)\n\t\treturn false;\n\n\tif (menu->visibility) {\n\t\tif (expr_calc_value(menu->visibility) == no)\n\t\t\treturn false;\n\t}\n\n\tsym = menu->sym;\n\tif (sym) {\n\t\tsym_calc_value(sym);\n\t\tvisible = menu->prompt->visible.tri;\n\t} else\n\t\tvisible = menu->prompt->visible.tri = expr_calc_value(menu->prompt->visible.expr);\n\n\tif (visible != no)\n\t\treturn true;\n\n\tif (!sym || sym_get_tristate_value(menu->sym) == no)\n\t\treturn false;\n\n\tfor (child = menu->list; child; child = child->next) {\n\t\tif (menu_is_visible(child)) {\n\t\t\tif (sym)\n\t\t\t\tsym->flags |= SYMBOL_DEF_USER;\n\t\t\treturn true;\n\t\t}\n\t}\n\n\treturn false;\n}\n\nconst char *menu_get_prompt(struct menu *menu)\n{\n\tif (menu->prompt)\n\t\treturn menu->prompt->text;\n\telse if (menu->sym)\n\t\treturn menu->sym->name;\n\treturn NULL;\n}\n\nstruct menu *menu_get_root_menu(struct menu *menu)\n{\n\treturn &rootmenu;\n}\n\nstruct menu *menu_get_parent_menu(struct menu *menu)\n{\n\tenum prop_type type;\n\n\tfor (; menu != &rootmenu; menu = menu->parent) {\n\t\ttype = menu->prompt ? menu->prompt->type : 0;\n\t\tif (type == P_MENU)\n\t\t\tbreak;\n\t}\n\treturn menu;\n}\n\nbool menu_has_help(struct menu *menu)\n{\n\treturn menu->help != NULL;\n}\n\nconst char *menu_get_help(struct menu *menu)\n{\n\tif (menu->help)\n\t\treturn menu->help;\n\telse\n\t\treturn \"\";\n}\n\nstatic void get_def_str(struct gstr *r, struct menu *menu)\n{\n\tstr_printf(r, \"Defined at %s:%d\\n\",\n\t\t   menu->file->name, menu->lineno);\n}\n\nstatic void get_dep_str(struct gstr *r, struct expr *expr, const char *prefix)\n{\n\tif (!expr_is_yes(expr)) {\n\t\tstr_append(r, prefix);\n\t\texpr_gstr_print(expr, r);\n\t\tstr_append(r, \"\\n\");\n\t}\n}\n\nstatic void get_prompt_str(struct gstr *r, struct property *prop,\n\t\t\t   struct list_head *head)\n{\n\tint i, j;\n\tstruct menu *submenu[8], *menu, *location = NULL;\n\tstruct jump_key *jump = NULL;\n\n\tstr_printf(r, \"  Prompt: %s\\n\", prop->text);\n\n\tget_dep_str(r, prop->menu->dep, \"  Depends on: \");\n\t/*\n\t * Most prompts in Linux have visibility that exactly matches their\n\t * dependencies. For these, we print only the dependencies to improve\n\t * readability. However, prompts with inline \"if\" expressions and\n\t * prompts with a parent that has a \"visible if\" expression have\n\t * differing dependencies and visibility. In these rare cases, we\n\t * print both.\n\t */\n\tif (!expr_eq(prop->menu->dep, prop->visible.expr))\n\t\tget_dep_str(r, prop->visible.expr, \"  Visible if: \");\n\n\tmenu = prop->menu->parent;\n\tfor (i = 0; menu != &rootmenu && i < 8; menu = menu->parent) {\n\t\tbool accessible = menu_is_visible(menu);\n\n\t\tsubmenu[i++] = menu;\n\t\tif (location == NULL && accessible)\n\t\t\tlocation = menu;\n\t}\n\tif (head && location) {\n\t\tjump = xmalloc(sizeof(struct jump_key));\n\n\t\tif (menu_is_visible(prop->menu)) {\n\t\t\t/*\n\t\t\t * There is not enough room to put the hint at the\n\t\t\t * beginning of the \"Prompt\" line. Put the hint on the\n\t\t\t * last \"Location\" line even when it would belong on\n\t\t\t * the former.\n\t\t\t */\n\t\t\tjump->target = prop->menu;\n\t\t} else\n\t\t\tjump->target = location;\n\n\t\tif (list_empty(head))\n\t\t\tjump->index = 0;\n\t\telse\n\t\t\tjump->index = list_entry(head->prev, struct jump_key,\n\t\t\t\t\t\t entries)->index + 1;\n\n\t\tlist_add_tail(&jump->entries, head);\n\t}\n\n\tif (i > 0) {\n\t\tstr_printf(r, \"  Location:\\n\");\n\t\tfor (j = 4; --i >= 0; j += 2) {\n\t\t\tmenu = submenu[i];\n\t\t\tif (jump && menu == location)\n\t\t\t\tjump->offset = strlen(r->s);\n\t\t\tstr_printf(r, \"%*c-> %s\", j, ' ',\n\t\t\t\t   menu_get_prompt(menu));\n\t\t\tif (menu->sym) {\n\t\t\t\tstr_printf(r, \" (%s [=%s])\", menu->sym->name ?\n\t\t\t\t\tmenu->sym->name : \"<choice>\",\n\t\t\t\t\tsym_get_string_value(menu->sym));\n\t\t\t}\n\t\t\tstr_append(r, \"\\n\");\n\t\t}\n\t}\n}\n\nstatic void get_symbol_props_str(struct gstr *r, struct symbol *sym,\n\t\t\t\t enum prop_type tok, const char *prefix)\n{\n\tbool hit = false;\n\tstruct property *prop;\n\n\tfor_all_properties(sym, prop, tok) {\n\t\tif (!hit) {\n\t\t\tstr_append(r, prefix);\n\t\t\thit = true;\n\t\t} else\n\t\t\tstr_printf(r, \" && \");\n\t\texpr_gstr_print(prop->expr, r);\n\t}\n\tif (hit)\n\t\tstr_append(r, \"\\n\");\n}\n\n/*\n * head is optional and may be NULL\n */\nstatic void get_symbol_str(struct gstr *r, struct symbol *sym,\n\t\t    struct list_head *head)\n{\n\tstruct property *prop;\n\n\tif (sym && sym->name) {\n\t\tstr_printf(r, \"Symbol: %s [=%s]\\n\", sym->name,\n\t\t\t   sym_get_string_value(sym));\n\t\tstr_printf(r, \"Type  : %s\\n\", sym_type_name(sym->type));\n\t\tif (sym->type == S_INT || sym->type == S_HEX) {\n\t\t\tprop = sym_get_range_prop(sym);\n\t\t\tif (prop) {\n\t\t\t\tstr_printf(r, \"Range : \");\n\t\t\t\texpr_gstr_print(prop->expr, r);\n\t\t\t\tstr_append(r, \"\\n\");\n\t\t\t}\n\t\t}\n\t}\n\n\t/* Print the definitions with prompts before the ones without */\n\tfor_all_properties(sym, prop, P_SYMBOL) {\n\t\tif (prop->menu->prompt) {\n\t\t\tget_def_str(r, prop->menu);\n\t\t\tget_prompt_str(r, prop->menu->prompt, head);\n\t\t}\n\t}\n\n\tfor_all_properties(sym, prop, P_SYMBOL) {\n\t\tif (!prop->menu->prompt) {\n\t\t\tget_def_str(r, prop->menu);\n\t\t\tget_dep_str(r, prop->menu->dep, \"  Depends on: \");\n\t\t}\n\t}\n\n\tget_symbol_props_str(r, sym, P_SELECT, \"Selects: \");\n\tif (sym->rev_dep.expr) {\n\t\texpr_gstr_print_revdep(sym->rev_dep.expr, r, yes, \"Selected by [y]:\\n\");\n\t\texpr_gstr_print_revdep(sym->rev_dep.expr, r, mod, \"Selected by [m]:\\n\");\n\t\texpr_gstr_print_revdep(sym->rev_dep.expr, r, no, \"Selected by [n]:\\n\");\n\t}\n\n\tget_symbol_props_str(r, sym, P_IMPLY, \"Implies: \");\n\tif (sym->implied.expr) {\n\t\texpr_gstr_print_revdep(sym->implied.expr, r, yes, \"Implied by [y]:\\n\");\n\t\texpr_gstr_print_revdep(sym->implied.expr, r, mod, \"Implied by [m]:\\n\");\n\t\texpr_gstr_print_revdep(sym->implied.expr, r, no, \"Implied by [n]:\\n\");\n\t}\n\n\tstr_append(r, \"\\n\\n\");\n}\n\nstruct gstr get_relations_str(struct symbol **sym_arr, struct list_head *head)\n{\n\tstruct symbol *sym;\n\tstruct gstr res = str_new();\n\tint i;\n\n\tfor (i = 0; sym_arr && (sym = sym_arr[i]); i++)\n\t\tget_symbol_str(&res, sym, head);\n\tif (!i)\n\t\tstr_append(&res, \"No matches found.\\n\");\n\treturn res;\n}\n\n\nvoid menu_get_ext_help(struct menu *menu, struct gstr *help)\n{\n\tstruct symbol *sym = menu->sym;\n\tconst char *help_text = nohelp_text;\n\n\tif (menu_has_help(menu)) {\n\t\tif (sym->name)\n\t\t\tstr_printf(help, \"%s%s:\\n\\n\", CONFIG_, sym->name);\n\t\thelp_text = menu_get_help(menu);\n\t}\n\tstr_printf(help, \"%s\\n\", help_text);\n\tif (sym)\n\t\tget_symbol_str(help, sym, NULL);\n}\n"
  },
  {
    "path": "scripts/config/nconf-cfg.sh",
    "content": "#!/bin/sh\n# SPDX-License-Identifier: GPL-2.0-only\n\nPKG=\"ncursesw menuw panelw\"\nPKG2=\"ncurses menu panel\"\n\nif [ -n \"$(command -v pkg-config)\" ]; then\n\tif pkg-config --exists $PKG; then\n\t\techo cflags=\\\"$(pkg-config --cflags $PKG)\\\"\n\t\techo libs=\\\"$(pkg-config --libs $PKG)\\\"\n\t\texit 0\n\tfi\n\n\tif pkg-config --exists $PKG2; then\n\t\techo cflags=\\\"$(pkg-config --cflags $PKG2)\\\"\n\t\techo libs=\\\"$(pkg-config --libs $PKG2)\\\"\n\t\texit 0\n\tfi\nfi\n\n# Check the default paths in case pkg-config is not installed.\n# (Even if it is installed, some distributions such as openSUSE cannot\n# find ncurses by pkg-config.)\nif [ -f /usr/include/ncursesw/ncurses.h ]; then\n\techo cflags=\\\"-D_GNU_SOURCE -I/usr/include/ncursesw\\\"\n\techo libs=\\\"-lncursesw -lmenuw -lpanelw\\\"\n\texit 0\nfi\n\nif [ -f /usr/include/ncurses/ncurses.h ]; then\n\techo cflags=\\\"-D_GNU_SOURCE -I/usr/include/ncurses\\\"\n\techo libs=\\\"-lncurses -lmenu -lpanel\\\"\n\texit 0\nfi\n\nif [ -f /usr/include/ncurses.h ]; then\n\techo cflags=\\\"-D_GNU_SOURCE\\\"\n\techo libs=\\\"-lncurses -lmenu -lpanel\\\"\n\texit 0\nfi\n\necho >&2 \"*\"\necho >&2 \"* Unable to find the ncurses package.\"\necho >&2 \"* Install ncurses (ncurses-devel or libncurses-dev\"\necho >&2 \"* depending on your distribution).\"\necho >&2 \"*\"\necho >&2 \"* You may also need to install pkg-config to find the\"\necho >&2 \"* ncurses installed in a non-default location.\"\necho >&2 \"*\"\nexit 1\n"
  },
  {
    "path": "scripts/config/nconf.c",
    "content": "// SPDX-License-Identifier: GPL-2.0-only\n/*\n * Copyright (C) 2008 Nir Tzachar <nir.tzachar@gmail.com>\n *\n * Derived from menuconfig.\n */\n#ifndef _GNU_SOURCE\n#define _GNU_SOURCE\n#endif\n#include <string.h>\n#include <strings.h>\n#include <stdlib.h>\n\n#include \"lkc.h\"\n#include \"nconf.h\"\n#include <ctype.h>\n\nstatic const char nconf_global_help[] =\n\"Help windows\\n\"\n\"------------\\n\"\n\"o  Global help:  Unless in a data entry window, pressing <F1> will give \\n\"\n\"   you the global help window, which you are just reading.\\n\"\n\"\\n\"\n\"o  A short version of the global help is available by pressing <F3>.\\n\"\n\"\\n\"\n\"o  Local help:  To get help related to the current menu entry, use any\\n\"\n\"   of <?> <h>, or if in a data entry window then press <F1>.\\n\"\n\"\\n\"\n\"\\n\"\n\"OpenWrt config is based on Kernel kconfig\\n\"\n\"so ipkg packages are referred here as modules.\\n\"\n\"\\n\"\n\"Menu entries\\n\"\n\"------------\\n\"\n\"This interface lets you select features and parameters for the build.\\n\"\n\"Features can either be built-in, modularized, or removed.\\n\"\n\"Parameters must be entered as text or decimal or hexadecimal numbers.\\n\"\n\"\\n\"\n\"Menu entries beginning with following braces represent features that\\n\"\n\"  [ ]  can be built in or removed\\n\"\n\"  < >  can be built in, modularized or removed\\n\"\n\"  { }  can be built in or modularized, are selected by another feature\\n\"\n\"  - -  are selected by another feature\\n\"\n\"  XXX  cannot be selected.  Symbol Info <F2> tells you why.\\n\"\n\"*, M or whitespace inside braces means to build in, build as a module\\n\"\n\"or to exclude the feature respectively.\\n\"\n\"\\n\"\n\"To change any of these features, highlight it with the movement keys\\n\"\n\"listed below and press <y> to build it in, <m> to make it a module or\\n\"\n\"<n> to remove it.  You may press the <Space> key to cycle through the\\n\"\n\"available options.\\n\"\n\"\\n\"\n\"A trailing \\\"--->\\\" designates a submenu, a trailing \\\"----\\\" an\\n\"\n\"empty submenu.\\n\"\n\"\\n\"\n\"Menu navigation keys\\n\"\n\"----------------------------------------------------------------------\\n\"\n\"Linewise up                 <Up>\\n\"\n\"Linewise down               <Down>\\n\"\n\"Pagewise up                 <Page Up>\\n\"\n\"Pagewise down               <Page Down>\\n\"\n\"First entry                 <Home>\\n\"\n\"Last entry                  <End>\\n\"\n\"Enter a submenu             <Right>  <Enter>\\n\"\n\"Go back to parent menu      <Left>   <Esc>  <F5>\\n\"\n\"Close a help window         <Enter>  <Esc>  <F5>\\n\"\n\"Close entry window, apply   <Enter>\\n\"\n\"Close entry window, forget  <Esc>  <F5>\\n\"\n\"Start incremental, case-insensitive search for STRING in menu entries,\\n\"\n\"    no regex support, STRING is displayed in upper left corner\\n\"\n\"                            </>STRING\\n\"\n\"    Remove last character   <Backspace>\\n\"\n\"    Jump to next hit        <Down>\\n\"\n\"    Jump to previous hit    <Up>\\n\"\n\"Exit menu search mode       </>  <Esc>\\n\"\n\"Search for configuration variables with or without leading CONFIG_\\n\"\n\"                            <F8>RegExpr<Enter>\\n\"\n\"Verbose search help         <F8><F1>\\n\"\n\"----------------------------------------------------------------------\\n\"\n\"\\n\"\n\"Unless in a data entry window, key <1> may be used instead of <F1>,\\n\"\n\"<2> instead of <F2>, etc.\\n\"\n\"\\n\"\n\"\\n\"\n\"Radiolist (Choice list)\\n\"\n\"-----------------------\\n\"\n\"Use the movement keys listed above to select the option you wish to set\\n\"\n\"and press <Space>.\\n\"\n\"\\n\"\n\"\\n\"\n\"Data entry\\n\"\n\"----------\\n\"\n\"Enter the requested information and press <Enter>.  Hexadecimal values\\n\"\n\"may be entered without the \\\"0x\\\" prefix.\\n\"\n\"\\n\"\n\"\\n\"\n\"Text Box (Help Window)\\n\"\n\"----------------------\\n\"\n\"Use movement keys as listed in table above.\\n\"\n\"\\n\"\n\"Press any of <Enter> <Esc> <q> <F5> <F9> to exit.\\n\"\n\"\\n\"\n\"\\n\"\n\"Alternate configuration files\\n\"\n\"-----------------------------\\n\"\n\"nconfig supports switching between different configurations.\\n\"\n\"Press <F6> to save your current configuration.  Press <F7> and enter\\n\"\n\"a file name to load a previously saved configuration.\\n\"\n\"\\n\"\n\"\\n\"\n\"Terminal configuration\\n\"\n\"----------------------\\n\"\n\"If you use nconfig in a xterm window, make sure your TERM environment\\n\"\n\"variable specifies a terminal configuration which supports at least\\n\"\n\"16 colors.  Otherwise nconfig will look rather bad.\\n\"\n\"\\n\"\n\"If the \\\"stty size\\\" command reports the current terminalsize correctly,\\n\"\n\"nconfig will adapt to sizes larger than the traditional 80x25 \\\"standard\\\"\\n\"\n\"and display longer menus properly.\\n\"\n\"\\n\"\n\"\\n\"\n\"Single menu mode\\n\"\n\"----------------\\n\"\n\"If you prefer to have all of the menu entries listed in a single menu,\\n\"\n\"rather than the default multimenu hierarchy, run nconfig with\\n\"\n\"NCONFIG_MODE environment variable set to single_menu.  Example:\\n\"\n\"\\n\"\n\"make NCONFIG_MODE=single_menu nconfig\\n\"\n\"\\n\"\n\"<Enter> will then unfold the appropriate category, or fold it if it\\n\"\n\"is already unfolded.  Folded menu entries will be designated by a\\n\"\n\"leading \\\"++>\\\" and unfolded entries by a leading \\\"-->\\\".\\n\"\n\"\\n\"\n\"Note that this mode can eventually be a little more CPU expensive than\\n\"\n\"the default mode, especially with a larger number of unfolded submenus.\\n\"\n\"\\n\",\nmenu_no_f_instructions[] =\n\"Legend:  [*] built-in  [ ] excluded  <M> module  < > module capable.\\n\"\n\"Submenus are designated by a trailing \\\"--->\\\", empty ones by \\\"----\\\".\\n\"\n\"\\n\"\n\"Use the following keys to navigate the menus:\\n\"\n\"Move up or down with <Up> and <Down>.\\n\"\n\"Enter a submenu with <Enter> or <Right>.\\n\"\n\"Exit a submenu to its parent menu with <Esc> or <Left>.\\n\"\n\"Pressing <y> includes, <n> excludes, <m> modularizes features.\\n\"\n\"Pressing <Space> cycles through the available options.\\n\"\n\"To search for menu entries press </>.\\n\"\n\"<Esc> always leaves the current window.\\n\"\n\"\\n\"\n\"You do not have function keys support.\\n\"\n\"Press <1> instead of <F1>, <2> instead of <F2>, etc.\\n\"\n\"For verbose global help use key <1>.\\n\"\n\"For help related to the current menu entry press <?> or <h>.\\n\",\nmenu_instructions[] =\n\"Legend:  [*] built-in  [ ] excluded  <M> module  < > module capable.\\n\"\n\"Submenus are designated by a trailing \\\"--->\\\", empty ones by \\\"----\\\".\\n\"\n\"\\n\"\n\"Use the following keys to navigate the menus:\\n\"\n\"Move up or down with <Up> or <Down>.\\n\"\n\"Enter a submenu with <Enter> or <Right>.\\n\"\n\"Exit a submenu to its parent menu with <Esc> or <Left>.\\n\"\n\"Pressing <y> includes, <n> excludes, <m> modularizes features.\\n\"\n\"Pressing <Space> cycles through the available options.\\n\"\n\"To search for menu entries press </>.\\n\"\n\"<Esc> always leaves the current window.\\n\"\n\"\\n\"\n\"Pressing <1> may be used instead of <F1>, <2> instead of <F2>, etc.\\n\"\n\"For verbose global help press <F1>.\\n\"\n\"For help related to the current menu entry press <?> or <h>.\\n\",\nradiolist_instructions[] =\n\"Press <Up>, <Down>, <Home> or <End> to navigate a radiolist, select\\n\"\n\"with <Space>.\\n\"\n\"For help related to the current entry press <?> or <h>.\\n\"\n\"For global help press <F1>.\\n\",\ninputbox_instructions_int[] =\n\"Please enter a decimal value.\\n\"\n\"Fractions will not be accepted.\\n\"\n\"Press <Enter> to apply, <Esc> to cancel.\",\ninputbox_instructions_hex[] =\n\"Please enter a hexadecimal value.\\n\"\n\"Press <Enter> to apply, <Esc> to cancel.\",\ninputbox_instructions_string[] =\n\"Please enter a string value.\\n\"\n\"Press <Enter> to apply, <Esc> to cancel.\",\nsetmod_text[] =\n\"This feature depends on another feature which has been configured as a\\n\"\n\"module.  As a result, the current feature will be built as a module too.\",\nload_config_text[] =\n\"Enter the name of the configuration file you wish to load.\\n\"\n\"Accept the name shown to restore the configuration you last\\n\"\n\"retrieved.  Leave empty to abort.\",\nload_config_help[] =\n\"For various reasons, one may wish to keep several different\\n\"\n\"configurations available on a single machine.\\n\"\n\"\\n\"\n\"If you have saved a previous configuration in a file other than the\\n\"\n\"default one, entering its name here will allow you to load and modify\\n\"\n\"that configuration.\\n\"\n\"\\n\"\n\"Leave empty to abort.\\n\",\nsave_config_text[] =\n\"Enter a filename to which this configuration should be saved\\n\"\n\"as an alternate.  Leave empty to abort.\",\nsave_config_help[] =\n\"For various reasons, one may wish to keep several different\\n\"\n\"configurations available on a single machine.\\n\"\n\"\\n\"\n\"Entering a file name here will allow you to later retrieve, modify\\n\"\n\"and use the current configuration as an alternate to whatever\\n\"\n\"configuration options you have selected at that time.\\n\"\n\"\\n\"\n\"Leave empty to abort.\\n\",\nsearch_help[] =\n\"Search for symbols (configuration variable names CONFIG_*) and display\\n\"\n\"their relations.  Regular expressions are supported.\\n\"\n\"Example:  Search for \\\"^FOO\\\".\\n\"\n\"Result:\\n\"\n\"-----------------------------------------------------------------\\n\"\n\"Symbol: FOO [ = m]\\n\"\n\"Prompt: Foo bus is used to drive the bar HW\\n\"\n\"Defined at drivers/pci/Kconfig:47\\n\"\n\"Depends on: X86_LOCAL_APIC && X86_IO_APIC || IA64\\n\"\n\"Location:\\n\"\n\"  -> Bus options (PCI, PCMCIA, EISA, ISA)\\n\"\n\"    -> PCI support (PCI [ = y])\\n\"\n\"      -> PCI access mode (<choice> [ = y])\\n\"\n\"Selects: LIBCRC32\\n\"\n\"Selected by: BAR\\n\"\n\"-----------------------------------------------------------------\\n\"\n\"o  The line 'Prompt:' shows the text displayed for this symbol in\\n\"\n\"   the menu hierarchy.\\n\"\n\"o  The 'Defined at' line tells at what file / line number the symbol is\\n\"\n\"   defined.\\n\"\n\"o  The 'Depends on:' line lists symbols that need to be defined for\\n\"\n\"   this symbol to be visible and selectable in the menu.\\n\"\n\"o  The 'Location:' lines tell, where in the menu structure this symbol\\n\"\n\"   is located.  A location followed by a [ = y] indicates that this is\\n\"\n\"   a selectable menu item, and the current value is displayed inside\\n\"\n\"   brackets.\\n\"\n\"o  The 'Selects:' line tells, what symbol will be automatically selected\\n\"\n\"   if this symbol is selected (y or m).\\n\"\n\"o  The 'Selected by' line tells what symbol has selected this symbol.\\n\"\n\"\\n\"\n\"Only relevant lines are shown.\\n\"\n\"\\n\\n\"\n\"Search examples:\\n\"\n\"USB  => find all symbols containing USB\\n\"\n\"^USB => find all symbols starting with USB\\n\"\n\"USB$ => find all symbols ending with USB\\n\"\n\"\\n\";\n\nstruct mitem {\n\tchar str[256];\n\tchar tag;\n\tvoid *usrptr;\n\tint is_visible;\n};\n\n#define MAX_MENU_ITEMS 4096\nstatic int show_all_items;\nstatic int indent;\nstatic struct menu *current_menu;\nstatic int child_count;\nstatic int single_menu_mode;\n/* the window in which all information appears */\nstatic WINDOW *main_window;\n/* the largest size of the menu window */\nstatic int mwin_max_lines;\nstatic int mwin_max_cols;\n/* the window in which we show option buttons */\nstatic MENU *curses_menu;\nstatic ITEM *curses_menu_items[MAX_MENU_ITEMS];\nstatic struct mitem k_menu_items[MAX_MENU_ITEMS];\nstatic unsigned int items_num;\nstatic int global_exit;\n/* the currently selected button */\nstatic const char *current_instructions = menu_instructions;\n\nstatic char *dialog_input_result;\nstatic int dialog_input_result_len;\n\nstatic void conf(struct menu *menu);\nstatic void conf_choice(struct menu *menu);\nstatic void conf_string(struct menu *menu);\nstatic void conf_load(void);\nstatic void conf_save(void);\nstatic void show_help(struct menu *menu);\nstatic int do_exit(void);\nstatic void setup_windows(void);\nstatic void search_conf(void);\n\ntypedef void (*function_key_handler_t)(int *key, struct menu *menu);\nstatic void handle_f1(int *key, struct menu *current_item);\nstatic void handle_f2(int *key, struct menu *current_item);\nstatic void handle_f3(int *key, struct menu *current_item);\nstatic void handle_f4(int *key, struct menu *current_item);\nstatic void handle_f5(int *key, struct menu *current_item);\nstatic void handle_f6(int *key, struct menu *current_item);\nstatic void handle_f7(int *key, struct menu *current_item);\nstatic void handle_f8(int *key, struct menu *current_item);\nstatic void handle_f9(int *key, struct menu *current_item);\n\nstruct function_keys {\n\tconst char *key_str;\n\tconst char *func;\n\tfunction_key key;\n\tfunction_key_handler_t handler;\n};\n\nstatic const int function_keys_num = 9;\nstatic struct function_keys function_keys[] = {\n\t{\n\t\t.key_str = \"F1\",\n\t\t.func = \"Help\",\n\t\t.key = F_HELP,\n\t\t.handler = handle_f1,\n\t},\n\t{\n\t\t.key_str = \"F2\",\n\t\t.func = \"SymInfo\",\n\t\t.key = F_SYMBOL,\n\t\t.handler = handle_f2,\n\t},\n\t{\n\t\t.key_str = \"F3\",\n\t\t.func = \"Help 2\",\n\t\t.key = F_INSTS,\n\t\t.handler = handle_f3,\n\t},\n\t{\n\t\t.key_str = \"F4\",\n\t\t.func = \"ShowAll\",\n\t\t.key = F_CONF,\n\t\t.handler = handle_f4,\n\t},\n\t{\n\t\t.key_str = \"F5\",\n\t\t.func = \"Back\",\n\t\t.key = F_BACK,\n\t\t.handler = handle_f5,\n\t},\n\t{\n\t\t.key_str = \"F6\",\n\t\t.func = \"Save\",\n\t\t.key = F_SAVE,\n\t\t.handler = handle_f6,\n\t},\n\t{\n\t\t.key_str = \"F7\",\n\t\t.func = \"Load\",\n\t\t.key = F_LOAD,\n\t\t.handler = handle_f7,\n\t},\n\t{\n\t\t.key_str = \"F8\",\n\t\t.func = \"SymSearch\",\n\t\t.key = F_SEARCH,\n\t\t.handler = handle_f8,\n\t},\n\t{\n\t\t.key_str = \"F9\",\n\t\t.func = \"Exit\",\n\t\t.key = F_EXIT,\n\t\t.handler = handle_f9,\n\t},\n};\n\nstatic void print_function_line(void)\n{\n\tint i;\n\tint offset = 1;\n\tconst int skip = 1;\n\tint lines = getmaxy(stdscr);\n\n\tfor (i = 0; i < function_keys_num; i++) {\n\t\twattrset(main_window, attr_function_highlight);\n\t\tmvwprintw(main_window, lines-3, offset,\n\t\t\t\t\"%s\",\n\t\t\t\tfunction_keys[i].key_str);\n\t\twattrset(main_window, attr_function_text);\n\t\toffset += strlen(function_keys[i].key_str);\n\t\tmvwprintw(main_window, lines-3,\n\t\t\t\toffset, \"%s\",\n\t\t\t\tfunction_keys[i].func);\n\t\toffset += strlen(function_keys[i].func) + skip;\n\t}\n\twattrset(main_window, attr_normal);\n}\n\n/* help */\nstatic void handle_f1(int *key, struct menu *current_item)\n{\n\tshow_scroll_win(main_window,\n\t\t\t\"Global help\", nconf_global_help);\n\treturn;\n}\n\n/* symbole help */\nstatic void handle_f2(int *key, struct menu *current_item)\n{\n\tshow_help(current_item);\n\treturn;\n}\n\n/* instructions */\nstatic void handle_f3(int *key, struct menu *current_item)\n{\n\tshow_scroll_win(main_window,\n\t\t\t\"Short help\",\n\t\t\tcurrent_instructions);\n\treturn;\n}\n\n/* config */\nstatic void handle_f4(int *key, struct menu *current_item)\n{\n\tint res = btn_dialog(main_window,\n\t\t\t\"Show all symbols?\",\n\t\t\t2,\n\t\t\t\"   <Show All>   \",\n\t\t\t\"<Don't show all>\");\n\tif (res == 0)\n\t\tshow_all_items = 1;\n\telse if (res == 1)\n\t\tshow_all_items = 0;\n\n\treturn;\n}\n\n/* back */\nstatic void handle_f5(int *key, struct menu *current_item)\n{\n\t*key = KEY_LEFT;\n\treturn;\n}\n\n/* save */\nstatic void handle_f6(int *key, struct menu *current_item)\n{\n\tconf_save();\n\treturn;\n}\n\n/* load */\nstatic void handle_f7(int *key, struct menu *current_item)\n{\n\tconf_load();\n\treturn;\n}\n\n/* search */\nstatic void handle_f8(int *key, struct menu *current_item)\n{\n\tsearch_conf();\n\treturn;\n}\n\n/* exit */\nstatic void handle_f9(int *key, struct menu *current_item)\n{\n\tdo_exit();\n\treturn;\n}\n\n/* return != 0 to indicate the key was handles */\nstatic int process_special_keys(int *key, struct menu *menu)\n{\n\tint i;\n\n\tif (*key == KEY_RESIZE) {\n\t\tsetup_windows();\n\t\treturn 1;\n\t}\n\n\tfor (i = 0; i < function_keys_num; i++) {\n\t\tif (*key == KEY_F(function_keys[i].key) ||\n\t\t    *key == '0' + function_keys[i].key){\n\t\t\tfunction_keys[i].handler(key, menu);\n\t\t\treturn 1;\n\t\t}\n\t}\n\n\treturn 0;\n}\n\nstatic void clean_items(void)\n{\n\tint i;\n\tfor (i = 0; curses_menu_items[i]; i++)\n\t\tfree_item(curses_menu_items[i]);\n\tbzero(curses_menu_items, sizeof(curses_menu_items));\n\tbzero(k_menu_items, sizeof(k_menu_items));\n\titems_num = 0;\n}\n\ntypedef enum {MATCH_TINKER_PATTERN_UP, MATCH_TINKER_PATTERN_DOWN,\n\tFIND_NEXT_MATCH_DOWN, FIND_NEXT_MATCH_UP} match_f;\n\n/* return the index of the matched item, or -1 if no such item exists */\nstatic int get_mext_match(const char *match_str, match_f flag)\n{\n\tint match_start, index;\n\n\t/* Do not search if the menu is empty (i.e. items_num == 0) */\n\tmatch_start = item_index(current_item(curses_menu));\n\tif (match_start == ERR)\n\t\treturn -1;\n\n\tif (flag == FIND_NEXT_MATCH_DOWN)\n\t\t++match_start;\n\telse if (flag == FIND_NEXT_MATCH_UP)\n\t\t--match_start;\n\n\tmatch_start = (match_start + items_num) % items_num;\n\tindex = match_start;\n\twhile (true) {\n\t\tchar *str = k_menu_items[index].str;\n\t\tif (strcasestr(str, match_str) != NULL)\n\t\t\treturn index;\n\t\tif (flag == FIND_NEXT_MATCH_UP ||\n\t\t    flag == MATCH_TINKER_PATTERN_UP)\n\t\t\t--index;\n\t\telse\n\t\t\t++index;\n\t\tindex = (index + items_num) % items_num;\n\t\tif (index == match_start)\n\t\t\treturn -1;\n\t}\n}\n\n/* Make a new item. */\nstatic void item_make(struct menu *menu, char tag, const char *fmt, ...)\n{\n\tva_list ap;\n\n\tif (items_num > MAX_MENU_ITEMS-1)\n\t\treturn;\n\n\tbzero(&k_menu_items[items_num], sizeof(k_menu_items[0]));\n\tk_menu_items[items_num].tag = tag;\n\tk_menu_items[items_num].usrptr = menu;\n\tif (menu != NULL)\n\t\tk_menu_items[items_num].is_visible =\n\t\t\tmenu_is_visible(menu);\n\telse\n\t\tk_menu_items[items_num].is_visible = 1;\n\n\tva_start(ap, fmt);\n\tvsnprintf(k_menu_items[items_num].str,\n\t\t  sizeof(k_menu_items[items_num].str),\n\t\t  fmt, ap);\n\tva_end(ap);\n\n\tif (!k_menu_items[items_num].is_visible)\n\t\tmemcpy(k_menu_items[items_num].str, \"XXX\", 3);\n\n\tcurses_menu_items[items_num] = new_item(\n\t\t\tk_menu_items[items_num].str,\n\t\t\tk_menu_items[items_num].str);\n\tset_item_userptr(curses_menu_items[items_num],\n\t\t\t&k_menu_items[items_num]);\n\t/*\n\tif (!k_menu_items[items_num].is_visible)\n\t\titem_opts_off(curses_menu_items[items_num], O_SELECTABLE);\n\t*/\n\n\titems_num++;\n\tcurses_menu_items[items_num] = NULL;\n}\n\n/* very hackish. adds a string to the last item added */\nstatic void item_add_str(const char *fmt, ...)\n{\n\tva_list ap;\n\tint index = items_num-1;\n\tchar new_str[256];\n\tchar tmp_str[256];\n\n\tif (index < 0)\n\t\treturn;\n\n\tva_start(ap, fmt);\n\tvsnprintf(new_str, sizeof(new_str), fmt, ap);\n\tva_end(ap);\n\tsnprintf(tmp_str, sizeof(tmp_str), \"%s%s\",\n\t\t\tk_menu_items[index].str, new_str);\n\tstrncpy(k_menu_items[index].str,\n\t\ttmp_str,\n\t\tsizeof(k_menu_items[index].str));\n\n\tfree_item(curses_menu_items[index]);\n\tcurses_menu_items[index] = new_item(\n\t\t\tk_menu_items[index].str,\n\t\t\tk_menu_items[index].str);\n\tset_item_userptr(curses_menu_items[index],\n\t\t\t&k_menu_items[index]);\n}\n\n/* get the tag of the currently selected item */\nstatic char item_tag(void)\n{\n\tITEM *cur;\n\tstruct mitem *mcur;\n\n\tcur = current_item(curses_menu);\n\tif (cur == NULL)\n\t\treturn 0;\n\tmcur = (struct mitem *) item_userptr(cur);\n\treturn mcur->tag;\n}\n\nstatic int curses_item_index(void)\n{\n\treturn  item_index(current_item(curses_menu));\n}\n\nstatic void *item_data(void)\n{\n\tITEM *cur;\n\tstruct mitem *mcur;\n\n\tcur = current_item(curses_menu);\n\tif (!cur)\n\t\treturn NULL;\n\tmcur = (struct mitem *) item_userptr(cur);\n\treturn mcur->usrptr;\n\n}\n\nstatic int item_is_tag(char tag)\n{\n\treturn item_tag() == tag;\n}\n\nstatic char filename[PATH_MAX+1];\nstatic char menu_backtitle[PATH_MAX+128];\nstatic void set_config_filename(const char *config_filename)\n{\n\tsnprintf(menu_backtitle, sizeof(menu_backtitle), \"%s - %s\",\n\t\t config_filename, rootmenu.prompt->text);\n\n\tsnprintf(filename, sizeof(filename), \"%s\", config_filename);\n}\n\n/* return = 0 means we are successful.\n * -1 means go on doing what you were doing\n */\nstatic int do_exit(void)\n{\n\tint res;\n\tif (!conf_get_changed()) {\n\t\tglobal_exit = 1;\n\t\treturn 0;\n\t}\n\tres = btn_dialog(main_window,\n\t\t\t\"Do you wish to save your new configuration?\\n\"\n\t\t\t\t\"<ESC> to cancel and resume nconfig.\",\n\t\t\t2,\n\t\t\t\"   <save>   \",\n\t\t\t\"<don't save>\");\n\tif (res == KEY_EXIT) {\n\t\tglobal_exit = 0;\n\t\treturn -1;\n\t}\n\n\t/* if we got here, the user really wants to exit */\n\tswitch (res) {\n\tcase 0:\n\t\tres = conf_write(filename);\n\t\tif (res)\n\t\t\tbtn_dialog(\n\t\t\t\tmain_window,\n\t\t\t\t\"Error during writing of configuration.\\n\"\n\t\t\t\t  \"Your configuration changes were NOT saved.\",\n\t\t\t\t  1,\n\t\t\t\t  \"<OK>\");\n\t\tconf_write_autoconf(0);\n\t\tbreak;\n\tdefault:\n\t\tbtn_dialog(\n\t\t\tmain_window,\n\t\t\t\"Your configuration changes were NOT saved.\",\n\t\t\t1,\n\t\t\t\"<OK>\");\n\t\tbreak;\n\t}\n\tglobal_exit = 1;\n\treturn 0;\n}\n\n\nstatic void search_conf(void)\n{\n\tstruct symbol **sym_arr;\n\tstruct gstr res;\n\tstruct gstr title;\n\tchar *dialog_input;\n\tint dres;\n\n\ttitle = str_new();\n\tstr_printf( &title, \"Enter (sub)string or regexp to search for \"\n\t\t\t      \"(with or without \\\"%s\\\")\", CONFIG_);\n\nagain:\n\tdres = dialog_inputbox(main_window,\n\t\t\t\"Search Configuration Parameter\",\n\t\t\tstr_get(&title),\n\t\t\t\"\", &dialog_input_result, &dialog_input_result_len);\n\tswitch (dres) {\n\tcase 0:\n\t\tbreak;\n\tcase 1:\n\t\tshow_scroll_win(main_window,\n\t\t\t\t\"Search Configuration\", search_help);\n\t\tgoto again;\n\tdefault:\n\t\tstr_free(&title);\n\t\treturn;\n\t}\n\n\t/* strip the prefix if necessary */\n\tdialog_input = dialog_input_result;\n\tif (strncasecmp(dialog_input_result, CONFIG_, strlen(CONFIG_)) == 0)\n\t\tdialog_input += strlen(CONFIG_);\n\n\tsym_arr = sym_re_search(dialog_input);\n\tres = get_relations_str(sym_arr, NULL);\n\tfree(sym_arr);\n\tshow_scroll_win(main_window,\n\t\t\t\"Search Results\", str_get(&res));\n\tstr_free(&res);\n\tstr_free(&title);\n}\n\n\nstatic void build_conf(struct menu *menu)\n{\n\tstruct symbol *sym;\n\tstruct property *prop;\n\tstruct menu *child;\n\tint type, tmp, doint = 2;\n\ttristate val;\n\tchar ch;\n\n\tif (!menu || (!show_all_items && !menu_is_visible(menu)))\n\t\treturn;\n\n\tsym = menu->sym;\n\tprop = menu->prompt;\n\tif (!sym) {\n\t\tif (prop && menu != current_menu) {\n\t\t\tconst char *prompt = menu_get_prompt(menu);\n\t\t\tenum prop_type ptype;\n\t\t\tptype = menu->prompt ? menu->prompt->type : P_UNKNOWN;\n\t\t\tswitch (ptype) {\n\t\t\tcase P_MENU:\n\t\t\t\tchild_count++;\n\t\t\t\tif (single_menu_mode) {\n\t\t\t\t\titem_make(menu, 'm',\n\t\t\t\t\t\t\"%s%*c%s\",\n\t\t\t\t\t\tmenu->data ? \"-->\" : \"++>\",\n\t\t\t\t\t\tindent + 1, ' ', prompt);\n\t\t\t\t} else\n\t\t\t\t\titem_make(menu, 'm',\n\t\t\t\t\t\t  \"   %*c%s  %s\",\n\t\t\t\t\t\t  indent + 1, ' ', prompt,\n\t\t\t\t\t\t  menu_is_empty(menu) ? \"----\" : \"--->\");\n\n\t\t\t\tif (single_menu_mode && menu->data)\n\t\t\t\t\tgoto conf_childs;\n\t\t\t\treturn;\n\t\t\tcase P_COMMENT:\n\t\t\t\tif (prompt) {\n\t\t\t\t\tchild_count++;\n\t\t\t\t\titem_make(menu, ':',\n\t\t\t\t\t\t\"   %*c*** %s ***\",\n\t\t\t\t\t\tindent + 1, ' ',\n\t\t\t\t\t\tprompt);\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tdefault:\n\t\t\t\tif (prompt) {\n\t\t\t\t\tchild_count++;\n\t\t\t\t\titem_make(menu, ':', \"---%*c%s\",\n\t\t\t\t\t\tindent + 1, ' ',\n\t\t\t\t\t\tprompt);\n\t\t\t\t}\n\t\t\t}\n\t\t} else\n\t\t\tdoint = 0;\n\t\tgoto conf_childs;\n\t}\n\n\ttype = sym_get_type(sym);\n\tif (sym_is_choice(sym)) {\n\t\tstruct symbol *def_sym = sym_get_choice_value(sym);\n\t\tstruct menu *def_menu = NULL;\n\n\t\tchild_count++;\n\t\tfor (child = menu->list; child; child = child->next) {\n\t\t\tif (menu_is_visible(child) && child->sym == def_sym)\n\t\t\t\tdef_menu = child;\n\t\t}\n\n\t\tval = sym_get_tristate_value(sym);\n\t\tif (sym_is_changeable(sym)) {\n\t\t\tswitch (type) {\n\t\t\tcase S_BOOLEAN:\n\t\t\t\titem_make(menu, 't', \"[%c]\",\n\t\t\t\t\t\tval == no ? ' ' : '*');\n\t\t\t\tbreak;\n\t\t\tcase S_TRISTATE:\n\t\t\t\tswitch (val) {\n\t\t\t\tcase yes:\n\t\t\t\t\tch = '*';\n\t\t\t\t\tbreak;\n\t\t\t\tcase mod:\n\t\t\t\t\tch = 'M';\n\t\t\t\t\tbreak;\n\t\t\t\tdefault:\n\t\t\t\t\tch = ' ';\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t\titem_make(menu, 't', \"<%c>\", ch);\n\t\t\t\tbreak;\n\t\t\t}\n\t\t} else {\n\t\t\titem_make(menu, def_menu ? 't' : ':', \"   \");\n\t\t}\n\n\t\titem_add_str(\"%*c%s\", indent + 1,\n\t\t\t\t' ', menu_get_prompt(menu));\n\t\tif (val == yes) {\n\t\t\tif (def_menu) {\n\t\t\t\titem_add_str(\" (%s)\",\n\t\t\t\t\tmenu_get_prompt(def_menu));\n\t\t\t\titem_add_str(\"  --->\");\n\t\t\t\tif (def_menu->list) {\n\t\t\t\t\tindent += 2;\n\t\t\t\t\tbuild_conf(def_menu);\n\t\t\t\t\tindent -= 2;\n\t\t\t\t}\n\t\t\t}\n\t\t\treturn;\n\t\t}\n\t} else {\n\t\tif (menu == current_menu) {\n\t\t\titem_make(menu, ':',\n\t\t\t\t\"---%*c%s\", indent + 1,\n\t\t\t\t' ', menu_get_prompt(menu));\n\t\t\tgoto conf_childs;\n\t\t}\n\t\tchild_count++;\n\t\tval = sym_get_tristate_value(sym);\n\t\tif (sym_is_choice_value(sym) && val == yes) {\n\t\t\titem_make(menu, ':', \"   \");\n\t\t} else {\n\t\t\tswitch (type) {\n\t\t\tcase S_BOOLEAN:\n\t\t\t\tif (sym_is_changeable(sym))\n\t\t\t\t\titem_make(menu, 't', \"[%c]\",\n\t\t\t\t\t\tval == no ? ' ' : '*');\n\t\t\t\telse\n\t\t\t\t\titem_make(menu, 't', \"-%c-\",\n\t\t\t\t\t\tval == no ? ' ' : '*');\n\t\t\t\tbreak;\n\t\t\tcase S_TRISTATE:\n\t\t\t\tswitch (val) {\n\t\t\t\tcase yes:\n\t\t\t\t\tch = '*';\n\t\t\t\t\tbreak;\n\t\t\t\tcase mod:\n\t\t\t\t\tch = 'M';\n\t\t\t\t\tbreak;\n\t\t\t\tdefault:\n\t\t\t\t\tch = ' ';\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t\tif (sym_is_changeable(sym)) {\n\t\t\t\t\tif (sym->rev_dep.tri == mod)\n\t\t\t\t\t\titem_make(menu,\n\t\t\t\t\t\t\t't', \"{%c}\", ch);\n\t\t\t\t\telse\n\t\t\t\t\t\titem_make(menu,\n\t\t\t\t\t\t\t't', \"<%c>\", ch);\n\t\t\t\t} else\n\t\t\t\t\titem_make(menu, 't', \"-%c-\", ch);\n\t\t\t\tbreak;\n\t\t\tdefault:\n\t\t\t\ttmp = 2 + strlen(sym_get_string_value(sym));\n\t\t\t\titem_make(menu, 's', \"    (%s)\",\n\t\t\t\t\t\tsym_get_string_value(sym));\n\t\t\t\ttmp = indent - tmp + 4;\n\t\t\t\tif (tmp < 0)\n\t\t\t\t\ttmp = 0;\n\t\t\t\titem_add_str(\"%*c%s%s\", tmp, ' ',\n\t\t\t\t\t\tmenu_get_prompt(menu),\n\t\t\t\t\t\t(sym_has_value(sym) ||\n\t\t\t\t\t\t !sym_is_changeable(sym)) ? \"\" :\n\t\t\t\t\t\t\" (NEW)\");\n\t\t\t\tgoto conf_childs;\n\t\t\t}\n\t\t}\n\t\titem_add_str(\"%*c%s%s\", indent + 1, ' ',\n\t\t\t\tmenu_get_prompt(menu),\n\t\t\t\t(sym_has_value(sym) || !sym_is_changeable(sym)) ?\n\t\t\t\t\"\" : \" (NEW)\");\n\t\tif (menu->prompt && menu->prompt->type == P_MENU) {\n\t\t\titem_add_str(\"  %s\", menu_is_empty(menu) ? \"----\" : \"--->\");\n\t\t\treturn;\n\t\t}\n\t}\n\nconf_childs:\n\tindent += doint;\n\tfor (child = menu->list; child; child = child->next)\n\t\tbuild_conf(child);\n\tindent -= doint;\n}\n\nstatic void reset_menu(void)\n{\n\tunpost_menu(curses_menu);\n\tclean_items();\n}\n\n/* adjust the menu to show this item.\n * prefer not to scroll the menu if possible*/\nstatic void center_item(int selected_index, int *last_top_row)\n{\n\tint toprow;\n\n\tset_top_row(curses_menu, *last_top_row);\n\ttoprow = top_row(curses_menu);\n\tif (selected_index < toprow ||\n\t    selected_index >= toprow+mwin_max_lines) {\n\t\ttoprow = max(selected_index-mwin_max_lines/2, 0);\n\t\tif (toprow >= item_count(curses_menu)-mwin_max_lines)\n\t\t\ttoprow = item_count(curses_menu)-mwin_max_lines;\n\t\tset_top_row(curses_menu, toprow);\n\t}\n\tset_current_item(curses_menu,\n\t\t\tcurses_menu_items[selected_index]);\n\t*last_top_row = toprow;\n\tpost_menu(curses_menu);\n\trefresh_all_windows(main_window);\n}\n\n/* this function assumes reset_menu has been called before */\nstatic void show_menu(const char *prompt, const char *instructions,\n\t\tint selected_index, int *last_top_row)\n{\n\tint maxx, maxy;\n\tWINDOW *menu_window;\n\n\tcurrent_instructions = instructions;\n\n\tclear();\n\tprint_in_middle(stdscr, 1, getmaxx(stdscr),\n\t\t\tmenu_backtitle,\n\t\t\tattr_main_heading);\n\n\twattrset(main_window, attr_main_menu_box);\n\tbox(main_window, 0, 0);\n\twattrset(main_window, attr_main_menu_heading);\n\tmvwprintw(main_window, 0, 3, \" %s \", prompt);\n\twattrset(main_window, attr_normal);\n\n\tset_menu_items(curses_menu, curses_menu_items);\n\n\t/* position the menu at the middle of the screen */\n\tscale_menu(curses_menu, &maxy, &maxx);\n\tmaxx = min(maxx, mwin_max_cols-2);\n\tmaxy = mwin_max_lines;\n\tmenu_window = derwin(main_window,\n\t\t\tmaxy,\n\t\t\tmaxx,\n\t\t\t2,\n\t\t\t(mwin_max_cols-maxx)/2);\n\tkeypad(menu_window, TRUE);\n\tset_menu_win(curses_menu, menu_window);\n\tset_menu_sub(curses_menu, menu_window);\n\n\t/* must reassert this after changing items, otherwise returns to a\n\t * default of 16\n\t */\n\tset_menu_format(curses_menu, maxy, 1);\n\tcenter_item(selected_index, last_top_row);\n\tset_menu_format(curses_menu, maxy, 1);\n\n\tprint_function_line();\n\n\t/* Post the menu */\n\tpost_menu(curses_menu);\n\trefresh_all_windows(main_window);\n}\n\nstatic void adj_match_dir(match_f *match_direction)\n{\n\tif (*match_direction == FIND_NEXT_MATCH_DOWN)\n\t\t*match_direction =\n\t\t\tMATCH_TINKER_PATTERN_DOWN;\n\telse if (*match_direction == FIND_NEXT_MATCH_UP)\n\t\t*match_direction =\n\t\t\tMATCH_TINKER_PATTERN_UP;\n\t/* else, do no change.. */\n}\n\nstruct match_state\n{\n\tint in_search;\n\tmatch_f match_direction;\n\tchar pattern[256];\n};\n\n/* Return 0 means I have handled the key. In such a case, ans should hold the\n * item to center, or -1 otherwise.\n * Else return -1 .\n */\nstatic int do_match(int key, struct match_state *state, int *ans)\n{\n\tchar c = (char) key;\n\tint terminate_search = 0;\n\t*ans = -1;\n\tif (key == '/' || (state->in_search && key == 27)) {\n\t\tmove(0, 0);\n\t\trefresh();\n\t\tclrtoeol();\n\t\tstate->in_search = 1-state->in_search;\n\t\tbzero(state->pattern, sizeof(state->pattern));\n\t\tstate->match_direction = MATCH_TINKER_PATTERN_DOWN;\n\t\treturn 0;\n\t} else if (!state->in_search)\n\t\treturn 1;\n\n\tif (isalnum(c) || isgraph(c) || c == ' ') {\n\t\tstate->pattern[strlen(state->pattern)] = c;\n\t\tstate->pattern[strlen(state->pattern)] = '\\0';\n\t\tadj_match_dir(&state->match_direction);\n\t\t*ans = get_mext_match(state->pattern,\n\t\t\t\tstate->match_direction);\n\t} else if (key == KEY_DOWN) {\n\t\tstate->match_direction = FIND_NEXT_MATCH_DOWN;\n\t\t*ans = get_mext_match(state->pattern,\n\t\t\t\tstate->match_direction);\n\t} else if (key == KEY_UP) {\n\t\tstate->match_direction = FIND_NEXT_MATCH_UP;\n\t\t*ans = get_mext_match(state->pattern,\n\t\t\t\tstate->match_direction);\n\t} else if (key == KEY_BACKSPACE || key == 8 || key == 127) {\n\t\tstate->pattern[strlen(state->pattern)-1] = '\\0';\n\t\tadj_match_dir(&state->match_direction);\n\t} else\n\t\tterminate_search = 1;\n\n\tif (terminate_search) {\n\t\tstate->in_search = 0;\n\t\tbzero(state->pattern, sizeof(state->pattern));\n\t\tmove(0, 0);\n\t\trefresh();\n\t\tclrtoeol();\n\t\treturn -1;\n\t}\n\treturn 0;\n}\n\nstatic void conf(struct menu *menu)\n{\n\tstruct menu *submenu = NULL;\n\tstruct symbol *sym;\n\tint res;\n\tint current_index = 0;\n\tint last_top_row = 0;\n\tstruct match_state match_state = {\n\t\t.in_search = 0,\n\t\t.match_direction = MATCH_TINKER_PATTERN_DOWN,\n\t\t.pattern = \"\",\n\t};\n\n\twhile (!global_exit) {\n\t\treset_menu();\n\t\tcurrent_menu = menu;\n\t\tbuild_conf(menu);\n\t\tif (!child_count)\n\t\t\tbreak;\n\n\t\tshow_menu(menu_get_prompt(menu), menu_instructions,\n\t\t\t  current_index, &last_top_row);\n\t\tkeypad((menu_win(curses_menu)), TRUE);\n\t\twhile (!global_exit) {\n\t\t\tif (match_state.in_search) {\n\t\t\t\tmvprintw(0, 0,\n\t\t\t\t\t\"searching: %s\", match_state.pattern);\n\t\t\t\tclrtoeol();\n\t\t\t}\n\t\t\trefresh_all_windows(main_window);\n\t\t\tres = wgetch(menu_win(curses_menu));\n\t\t\tif (!res)\n\t\t\t\tbreak;\n\t\t\tif (do_match(res, &match_state, &current_index) == 0) {\n\t\t\t\tif (current_index != -1)\n\t\t\t\t\tcenter_item(current_index,\n\t\t\t\t\t\t    &last_top_row);\n\t\t\t\tcontinue;\n\t\t\t}\n\t\t\tif (process_special_keys(&res,\n\t\t\t\t\t\t(struct menu *) item_data()))\n\t\t\t\tbreak;\n\t\t\tswitch (res) {\n\t\t\tcase KEY_DOWN:\n\t\t\t\tmenu_driver(curses_menu, REQ_DOWN_ITEM);\n\t\t\t\tbreak;\n\t\t\tcase KEY_UP:\n\t\t\t\tmenu_driver(curses_menu, REQ_UP_ITEM);\n\t\t\t\tbreak;\n\t\t\tcase KEY_NPAGE:\n\t\t\t\tmenu_driver(curses_menu, REQ_SCR_DPAGE);\n\t\t\t\tbreak;\n\t\t\tcase KEY_PPAGE:\n\t\t\t\tmenu_driver(curses_menu, REQ_SCR_UPAGE);\n\t\t\t\tbreak;\n\t\t\tcase KEY_HOME:\n\t\t\t\tmenu_driver(curses_menu, REQ_FIRST_ITEM);\n\t\t\t\tbreak;\n\t\t\tcase KEY_END:\n\t\t\t\tmenu_driver(curses_menu, REQ_LAST_ITEM);\n\t\t\t\tbreak;\n\t\t\tcase 'h':\n\t\t\tcase '?':\n\t\t\t\tshow_help((struct menu *) item_data());\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\tif (res == 10 || res == 27 ||\n\t\t\t\tres == 32 || res == 'n' || res == 'y' ||\n\t\t\t\tres == KEY_LEFT || res == KEY_RIGHT ||\n\t\t\t\tres == 'm')\n\t\t\t\tbreak;\n\t\t\trefresh_all_windows(main_window);\n\t\t}\n\n\t\trefresh_all_windows(main_window);\n\t\t/* if ESC or left*/\n\t\tif (res == 27 || (menu != &rootmenu && res == KEY_LEFT))\n\t\t\tbreak;\n\n\t\t/* remember location in the menu */\n\t\tlast_top_row = top_row(curses_menu);\n\t\tcurrent_index = curses_item_index();\n\n\t\tif (!item_tag())\n\t\t\tcontinue;\n\n\t\tsubmenu = (struct menu *) item_data();\n\t\tif (!submenu || !menu_is_visible(submenu))\n\t\t\tcontinue;\n\t\tsym = submenu->sym;\n\n\t\tswitch (res) {\n\t\tcase ' ':\n\t\t\tif (item_is_tag('t'))\n\t\t\t\tsym_toggle_tristate_value(sym);\n\t\t\telse if (item_is_tag('m'))\n\t\t\t\tconf(submenu);\n\t\t\tbreak;\n\t\tcase KEY_RIGHT:\n\t\tcase 10: /* ENTER WAS PRESSED */\n\t\t\tswitch (item_tag()) {\n\t\t\tcase 'm':\n\t\t\t\tif (single_menu_mode)\n\t\t\t\t\tsubmenu->data =\n\t\t\t\t\t\t(void *) (long) !submenu->data;\n\t\t\t\telse\n\t\t\t\t\tconf(submenu);\n\t\t\t\tbreak;\n\t\t\tcase 't':\n\t\t\t\tif (sym_is_choice(sym) &&\n\t\t\t\t    sym_get_tristate_value(sym) == yes)\n\t\t\t\t\tconf_choice(submenu);\n\t\t\t\telse if (submenu->prompt &&\n\t\t\t\t\t submenu->prompt->type == P_MENU)\n\t\t\t\t\tconf(submenu);\n\t\t\t\telse if (res == 10)\n\t\t\t\t\tsym_toggle_tristate_value(sym);\n\t\t\t\tbreak;\n\t\t\tcase 's':\n\t\t\t\tconf_string(submenu);\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\tbreak;\n\t\tcase 'y':\n\t\t\tif (item_is_tag('t')) {\n\t\t\t\tif (sym_set_tristate_value(sym, yes))\n\t\t\t\t\tbreak;\n\t\t\t\tif (sym_set_tristate_value(sym, mod))\n\t\t\t\t\tbtn_dialog(main_window, setmod_text, 0);\n\t\t\t}\n\t\t\tbreak;\n\t\tcase 'n':\n\t\t\tif (item_is_tag('t'))\n\t\t\t\tsym_set_tristate_value(sym, no);\n\t\t\tbreak;\n\t\tcase 'm':\n\t\t\tif (item_is_tag('t'))\n\t\t\t\tsym_set_tristate_value(sym, mod);\n\t\t\tbreak;\n\t\t}\n\t}\n}\n\nstatic void conf_message_callback(const char *s)\n{\n\tbtn_dialog(main_window, s, 1, \"<OK>\");\n}\n\nstatic void show_help(struct menu *menu)\n{\n\tstruct gstr help;\n\n\tif (!menu)\n\t\treturn;\n\n\thelp = str_new();\n\tmenu_get_ext_help(menu, &help);\n\tshow_scroll_win(main_window, menu_get_prompt(menu), str_get(&help));\n\tstr_free(&help);\n}\n\nstatic void conf_choice(struct menu *menu)\n{\n\tconst char *prompt = menu_get_prompt(menu);\n\tstruct menu *child = NULL;\n\tstruct symbol *active;\n\tstruct property *prop;\n\tint selected_index = 0;\n\tint last_top_row = 0;\n\tint res, i = 0;\n\tstruct match_state match_state = {\n\t\t.in_search = 0,\n\t\t.match_direction = MATCH_TINKER_PATTERN_DOWN,\n\t\t.pattern = \"\",\n\t};\n\n\tactive = sym_get_choice_value(menu->sym);\n\t/* this is mostly duplicated from the conf() function. */\n\twhile (!global_exit) {\n\t\treset_menu();\n\n\t\tfor (i = 0, child = menu->list; child; child = child->next) {\n\t\t\tif (!show_all_items && !menu_is_visible(child))\n\t\t\t\tcontinue;\n\n\t\t\tif (child->sym == sym_get_choice_value(menu->sym))\n\t\t\t\titem_make(child, ':', \"<X> %s\",\n\t\t\t\t\t\tmenu_get_prompt(child));\n\t\t\telse if (child->sym)\n\t\t\t\titem_make(child, ':', \"    %s\",\n\t\t\t\t\t\tmenu_get_prompt(child));\n\t\t\telse\n\t\t\t\titem_make(child, ':', \"*** %s ***\",\n\t\t\t\t\t\tmenu_get_prompt(child));\n\n\t\t\tif (child->sym == active){\n\t\t\t\tlast_top_row = top_row(curses_menu);\n\t\t\t\tselected_index = i;\n\t\t\t}\n\t\t\ti++;\n\t\t}\n\t\tshow_menu(prompt ? prompt : \"Choice Menu\",\n\t\t\t\tradiolist_instructions,\n\t\t\t\tselected_index,\n\t\t\t\t&last_top_row);\n\t\twhile (!global_exit) {\n\t\t\tif (match_state.in_search) {\n\t\t\t\tmvprintw(0, 0, \"searching: %s\",\n\t\t\t\t\t match_state.pattern);\n\t\t\t\tclrtoeol();\n\t\t\t}\n\t\t\trefresh_all_windows(main_window);\n\t\t\tres = wgetch(menu_win(curses_menu));\n\t\t\tif (!res)\n\t\t\t\tbreak;\n\t\t\tif (do_match(res, &match_state, &selected_index) == 0) {\n\t\t\t\tif (selected_index != -1)\n\t\t\t\t\tcenter_item(selected_index,\n\t\t\t\t\t\t    &last_top_row);\n\t\t\t\tcontinue;\n\t\t\t}\n\t\t\tif (process_special_keys(\n\t\t\t\t\t\t&res,\n\t\t\t\t\t\t(struct menu *) item_data()))\n\t\t\t\tbreak;\n\t\t\tswitch (res) {\n\t\t\tcase KEY_DOWN:\n\t\t\t\tmenu_driver(curses_menu, REQ_DOWN_ITEM);\n\t\t\t\tbreak;\n\t\t\tcase KEY_UP:\n\t\t\t\tmenu_driver(curses_menu, REQ_UP_ITEM);\n\t\t\t\tbreak;\n\t\t\tcase KEY_NPAGE:\n\t\t\t\tmenu_driver(curses_menu, REQ_SCR_DPAGE);\n\t\t\t\tbreak;\n\t\t\tcase KEY_PPAGE:\n\t\t\t\tmenu_driver(curses_menu, REQ_SCR_UPAGE);\n\t\t\t\tbreak;\n\t\t\tcase KEY_HOME:\n\t\t\t\tmenu_driver(curses_menu, REQ_FIRST_ITEM);\n\t\t\t\tbreak;\n\t\t\tcase KEY_END:\n\t\t\t\tmenu_driver(curses_menu, REQ_LAST_ITEM);\n\t\t\t\tbreak;\n\t\t\tcase 'h':\n\t\t\tcase '?':\n\t\t\t\tshow_help((struct menu *) item_data());\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\tif (res == 10 || res == 27 || res == ' ' ||\n\t\t\t\t\tres == KEY_LEFT){\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\trefresh_all_windows(main_window);\n\t\t}\n\t\t/* if ESC or left */\n\t\tif (res == 27 || res == KEY_LEFT)\n\t\t\tbreak;\n\n\t\tchild = item_data();\n\t\tif (!child || !menu_is_visible(child) || !child->sym)\n\t\t\tcontinue;\n\t\tswitch (res) {\n\t\tcase ' ':\n\t\tcase  10:\n\t\tcase KEY_RIGHT:\n\t\t\tif (sym_get_tristate_value(child->sym) != yes) {\n\t\t\t\tfor_all_properties(menu->sym, prop, P_RESET) {\n\t\t\t\t\tif (expr_calc_value(prop->visible.expr) == no)\n\t\t\t\t\t\tcontinue;\n\n\t\t\t\t\tconf_reset(S_DEF_USER);\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t}\n\t\t\tsym_set_tristate_value(child->sym, yes);\n\t\t\treturn;\n\t\tcase 'h':\n\t\tcase '?':\n\t\t\tshow_help(child);\n\t\t\tactive = child->sym;\n\t\t\tbreak;\n\t\tcase KEY_EXIT:\n\t\t\treturn;\n\t\t}\n\t}\n}\n\nstatic void conf_string(struct menu *menu)\n{\n\tconst char *prompt = menu_get_prompt(menu);\n\n\twhile (1) {\n\t\tint res;\n\t\tconst char *heading;\n\n\t\tswitch (sym_get_type(menu->sym)) {\n\t\tcase S_INT:\n\t\t\theading = inputbox_instructions_int;\n\t\t\tbreak;\n\t\tcase S_HEX:\n\t\t\theading = inputbox_instructions_hex;\n\t\t\tbreak;\n\t\tcase S_STRING:\n\t\t\theading = inputbox_instructions_string;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\theading = \"Internal nconf error!\";\n\t\t}\n\t\tres = dialog_inputbox(main_window,\n\t\t\t\tprompt ? prompt : \"Main Menu\",\n\t\t\t\theading,\n\t\t\t\tsym_get_string_value(menu->sym),\n\t\t\t\t&dialog_input_result,\n\t\t\t\t&dialog_input_result_len);\n\t\tswitch (res) {\n\t\tcase 0:\n\t\t\tif (sym_set_string_value(menu->sym,\n\t\t\t\t\t\tdialog_input_result))\n\t\t\t\treturn;\n\t\t\tbtn_dialog(main_window,\n\t\t\t\t\"You have made an invalid entry.\", 0);\n\t\t\tbreak;\n\t\tcase 1:\n\t\t\tshow_help(menu);\n\t\t\tbreak;\n\t\tcase KEY_EXIT:\n\t\t\treturn;\n\t\t}\n\t}\n}\n\nstatic void conf_load(void)\n{\n\twhile (1) {\n\t\tint res;\n\t\tres = dialog_inputbox(main_window,\n\t\t\t\tNULL, load_config_text,\n\t\t\t\tfilename,\n\t\t\t\t&dialog_input_result,\n\t\t\t\t&dialog_input_result_len);\n\t\tswitch (res) {\n\t\tcase 0:\n\t\t\tif (!dialog_input_result[0])\n\t\t\t\treturn;\n\t\t\tif (!conf_read(dialog_input_result)) {\n\t\t\t\tset_config_filename(dialog_input_result);\n\t\t\t\tconf_set_changed(true);\n\t\t\t\treturn;\n\t\t\t}\n\t\t\tbtn_dialog(main_window, \"File does not exist!\", 0);\n\t\t\tbreak;\n\t\tcase 1:\n\t\t\tshow_scroll_win(main_window,\n\t\t\t\t\t\"Load Alternate Configuration\",\n\t\t\t\t\tload_config_help);\n\t\t\tbreak;\n\t\tcase KEY_EXIT:\n\t\t\treturn;\n\t\t}\n\t}\n}\n\nstatic void conf_save(void)\n{\n\twhile (1) {\n\t\tint res;\n\t\tres = dialog_inputbox(main_window,\n\t\t\t\tNULL, save_config_text,\n\t\t\t\tfilename,\n\t\t\t\t&dialog_input_result,\n\t\t\t\t&dialog_input_result_len);\n\t\tswitch (res) {\n\t\tcase 0:\n\t\t\tif (!dialog_input_result[0])\n\t\t\t\treturn;\n\t\t\tres = conf_write(dialog_input_result);\n\t\t\tif (!res) {\n\t\t\t\tset_config_filename(dialog_input_result);\n\t\t\t\treturn;\n\t\t\t}\n\t\t\tbtn_dialog(main_window, \"Can't create file!\",\n\t\t\t\t1, \"<OK>\");\n\t\t\tbreak;\n\t\tcase 1:\n\t\t\tshow_scroll_win(main_window,\n\t\t\t\t\"Save Alternate Configuration\",\n\t\t\t\tsave_config_help);\n\t\t\tbreak;\n\t\tcase KEY_EXIT:\n\t\t\treturn;\n\t\t}\n\t}\n}\n\nstatic void setup_windows(void)\n{\n\tint lines, columns;\n\n\tgetmaxyx(stdscr, lines, columns);\n\n\tif (main_window != NULL)\n\t\tdelwin(main_window);\n\n\t/* set up the menu and menu window */\n\tmain_window = newwin(lines-2, columns-2, 2, 1);\n\tkeypad(main_window, TRUE);\n\tmwin_max_lines = lines-7;\n\tmwin_max_cols = columns-6;\n\n\t/* panels order is from bottom to top */\n\tnew_panel(main_window);\n}\n\nint main(int ac, char **av)\n{\n\tint lines, columns;\n\tchar *mode;\n\n\tif (ac > 1 && strcmp(av[1], \"-s\") == 0) {\n\t\t/* Silence conf_read() until the real callback is set up */\n\t\tconf_set_message_callback(NULL);\n\t\tav++;\n\t}\n\tconf_parse(av[1]);\n\tconf_read(NULL);\n\n\tmode = getenv(\"NCONFIG_MODE\");\n\tif (mode) {\n\t\tif (!strcasecmp(mode, \"single_menu\"))\n\t\t\tsingle_menu_mode = 1;\n\t}\n\n\t/* Initialize curses */\n\tinitscr();\n\t/* set color theme */\n\tset_colors();\n\n\tcbreak();\n\tnoecho();\n\tkeypad(stdscr, TRUE);\n\tcurs_set(0);\n\n\tgetmaxyx(stdscr, lines, columns);\n\tif (columns < 75 || lines < 20) {\n\t\tendwin();\n\t\tprintf(\"Your terminal should have at \"\n\t\t\t\"least 20 lines and 75 columns\\n\");\n\t\treturn 1;\n\t}\n\n\tnotimeout(stdscr, FALSE);\n#if NCURSES_REENTRANT\n\tset_escdelay(1);\n#else\n\tESCDELAY = 1;\n#endif\n\n\t/* set btns menu */\n\tcurses_menu = new_menu(curses_menu_items);\n\tmenu_opts_off(curses_menu, O_SHOWDESC);\n\tmenu_opts_on(curses_menu, O_SHOWMATCH);\n\tmenu_opts_on(curses_menu, O_ONEVALUE);\n\tmenu_opts_on(curses_menu, O_NONCYCLIC);\n\tmenu_opts_on(curses_menu, O_IGNORECASE);\n\tset_menu_mark(curses_menu, \" \");\n\tset_menu_fore(curses_menu, attr_main_menu_fore);\n\tset_menu_back(curses_menu, attr_main_menu_back);\n\tset_menu_grey(curses_menu, attr_main_menu_grey);\n\n\tset_config_filename(conf_get_configname());\n\tsetup_windows();\n\n\t/* check for KEY_FUNC(1) */\n\tif (has_key(KEY_F(1)) == FALSE) {\n\t\tshow_scroll_win(main_window,\n\t\t\t\t\"Instructions\",\n\t\t\t\tmenu_no_f_instructions);\n\t}\n\n\tconf_set_message_callback(conf_message_callback);\n\t/* do the work */\n\twhile (!global_exit) {\n\t\tconf(&rootmenu);\n\t\tif (!global_exit && do_exit() == 0)\n\t\t\tbreak;\n\t}\n\t/* ok, we are done */\n\tunpost_menu(curses_menu);\n\tfree_menu(curses_menu);\n\tdelwin(main_window);\n\tclear();\n\trefresh();\n\tendwin();\n\treturn 0;\n}\n"
  },
  {
    "path": "scripts/config/nconf.gui.c",
    "content": "// SPDX-License-Identifier: GPL-2.0-only\n/*\n * Copyright (C) 2008 Nir Tzachar <nir.tzachar@gmail.com>\n *\n * Derived from menuconfig.\n */\n#include \"nconf.h\"\n#include \"lkc.h\"\n\nint attr_normal;\nint attr_main_heading;\nint attr_main_menu_box;\nint attr_main_menu_fore;\nint attr_main_menu_back;\nint attr_main_menu_grey;\nint attr_main_menu_heading;\nint attr_scrollwin_text;\nint attr_scrollwin_heading;\nint attr_scrollwin_box;\nint attr_dialog_text;\nint attr_dialog_menu_fore;\nint attr_dialog_menu_back;\nint attr_dialog_box;\nint attr_input_box;\nint attr_input_heading;\nint attr_input_text;\nint attr_input_field;\nint attr_function_text;\nint attr_function_highlight;\n\n#define COLOR_ATTR(_at, _fg, _bg, _hl) \\\n\t{ .attr = &(_at), .has_color = true, .color_fg = _fg, .color_bg = _bg, .highlight = _hl }\n#define NO_COLOR_ATTR(_at, _hl) \\\n\t{ .attr = &(_at), .has_color = false, .highlight = _hl }\n#define COLOR_DEFAULT\t\t-1\n\nstruct nconf_attr_param {\n\tint *attr;\n\tbool has_color;\n\tint color_fg;\n\tint color_bg;\n\tint highlight;\n};\n\nstatic const struct nconf_attr_param color_theme_params[] = {\n\tCOLOR_ATTR(attr_normal,\t\t\tCOLOR_DEFAULT,\tCOLOR_DEFAULT,\tA_NORMAL),\n\tCOLOR_ATTR(attr_main_heading,\t\tCOLOR_MAGENTA,\tCOLOR_DEFAULT,\tA_BOLD | A_UNDERLINE),\n\tCOLOR_ATTR(attr_main_menu_box,\t\tCOLOR_YELLOW,\tCOLOR_DEFAULT,\tA_NORMAL),\n\tCOLOR_ATTR(attr_main_menu_fore,\t\tCOLOR_DEFAULT,\tCOLOR_DEFAULT,\tA_REVERSE),\n\tCOLOR_ATTR(attr_main_menu_back,\t\tCOLOR_DEFAULT,\tCOLOR_DEFAULT,\tA_NORMAL),\n\tCOLOR_ATTR(attr_main_menu_grey,\t\tCOLOR_DEFAULT,\tCOLOR_DEFAULT,\tA_NORMAL),\n\tCOLOR_ATTR(attr_main_menu_heading,\tCOLOR_GREEN,\tCOLOR_DEFAULT,\tA_BOLD),\n\tCOLOR_ATTR(attr_scrollwin_text,\t\tCOLOR_DEFAULT,\tCOLOR_DEFAULT,\tA_NORMAL),\n\tCOLOR_ATTR(attr_scrollwin_heading,\tCOLOR_GREEN,\tCOLOR_DEFAULT,\tA_BOLD),\n\tCOLOR_ATTR(attr_scrollwin_box,\t\tCOLOR_YELLOW,\tCOLOR_DEFAULT,\tA_BOLD),\n\tCOLOR_ATTR(attr_dialog_text,\t\tCOLOR_DEFAULT,\tCOLOR_DEFAULT,\tA_BOLD),\n\tCOLOR_ATTR(attr_dialog_menu_fore,\tCOLOR_RED,\tCOLOR_DEFAULT,\tA_STANDOUT),\n\tCOLOR_ATTR(attr_dialog_menu_back,\tCOLOR_YELLOW,\tCOLOR_DEFAULT,\tA_NORMAL),\n\tCOLOR_ATTR(attr_dialog_box,\t\tCOLOR_YELLOW,\tCOLOR_DEFAULT,\tA_BOLD),\n\tCOLOR_ATTR(attr_input_box,\t\tCOLOR_YELLOW,\tCOLOR_DEFAULT,\tA_NORMAL),\n\tCOLOR_ATTR(attr_input_heading,\t\tCOLOR_GREEN,\tCOLOR_DEFAULT,\tA_BOLD),\n\tCOLOR_ATTR(attr_input_text,\t\tCOLOR_DEFAULT,\tCOLOR_DEFAULT,\tA_NORMAL),\n\tCOLOR_ATTR(attr_input_field,\t\tCOLOR_DEFAULT,\tCOLOR_DEFAULT,\tA_UNDERLINE),\n\tCOLOR_ATTR(attr_function_text,\t\tCOLOR_YELLOW,\tCOLOR_DEFAULT,\tA_REVERSE),\n\tCOLOR_ATTR(attr_function_highlight,\tCOLOR_DEFAULT,\tCOLOR_DEFAULT,\tA_BOLD),\n\t{ /* sentinel */ }\n};\n\nstatic const struct nconf_attr_param no_color_theme_params[] = {\n\tNO_COLOR_ATTR(attr_normal,\t\tA_NORMAL),\n\tNO_COLOR_ATTR(attr_main_heading,\tA_BOLD | A_UNDERLINE),\n\tNO_COLOR_ATTR(attr_main_menu_box,\tA_NORMAL),\n\tNO_COLOR_ATTR(attr_main_menu_fore,\tA_STANDOUT),\n\tNO_COLOR_ATTR(attr_main_menu_back,\tA_NORMAL),\n\tNO_COLOR_ATTR(attr_main_menu_grey,\tA_NORMAL),\n\tNO_COLOR_ATTR(attr_main_menu_heading,\tA_BOLD),\n\tNO_COLOR_ATTR(attr_scrollwin_text,\tA_NORMAL),\n\tNO_COLOR_ATTR(attr_scrollwin_heading,\tA_BOLD),\n\tNO_COLOR_ATTR(attr_scrollwin_box,\tA_BOLD),\n\tNO_COLOR_ATTR(attr_dialog_text,\t\tA_NORMAL),\n\tNO_COLOR_ATTR(attr_dialog_menu_fore,\tA_STANDOUT),\n\tNO_COLOR_ATTR(attr_dialog_menu_back,\tA_NORMAL),\n\tNO_COLOR_ATTR(attr_dialog_box,\t\tA_BOLD),\n\tNO_COLOR_ATTR(attr_input_box,\t\tA_BOLD),\n\tNO_COLOR_ATTR(attr_input_heading,\tA_BOLD),\n\tNO_COLOR_ATTR(attr_input_text,\t\tA_NORMAL),\n\tNO_COLOR_ATTR(attr_input_field,\t\tA_UNDERLINE),\n\tNO_COLOR_ATTR(attr_function_text,\tA_REVERSE),\n\tNO_COLOR_ATTR(attr_function_highlight,\tA_BOLD),\n\t{ /* sentinel */ }\n};\n\nvoid set_colors(void)\n{\n\tconst struct nconf_attr_param *p;\n\tint pair = 0;\n\n\tif (has_colors()) {\n\t\tstart_color();\n\t\tuse_default_colors();\n\t\tp = color_theme_params;\n\t} else {\n\t\tp = no_color_theme_params;\n\t}\n\n\tfor (; p->attr; p++) {\n\t\tint attr = p->highlight;\n\n\t\tif (p->has_color) {\n\t\t\tpair++;\n\t\t\tinit_pair(pair, p->color_fg, p->color_bg);\n\t\t\tattr |= COLOR_PAIR(pair);\n\t\t}\n\n\t\t*p->attr = attr;\n\t}\n}\n\n/* this changes the windows attributes !!! */\nvoid print_in_middle(WINDOW *win, int y, int width, const char *str, int attrs)\n{\n\twattrset(win, attrs);\n\tmvwprintw(win, y, (width - strlen(str)) / 2, \"%s\", str);\n}\n\nint get_line_no(const char *text)\n{\n\tint i;\n\tint total = 1;\n\n\tif (!text)\n\t\treturn 0;\n\n\tfor (i = 0; text[i] != '\\0'; i++)\n\t\tif (text[i] == '\\n')\n\t\t\ttotal++;\n\treturn total;\n}\n\nconst char *get_line(const char *text, int line_no)\n{\n\tint i;\n\tint lines = 0;\n\n\tif (!text)\n\t\treturn NULL;\n\n\tfor (i = 0; text[i] != '\\0' && lines < line_no; i++)\n\t\tif (text[i] == '\\n')\n\t\t\tlines++;\n\treturn text+i;\n}\n\nint get_line_length(const char *line)\n{\n\tint res = 0;\n\twhile (*line != '\\0' && *line != '\\n') {\n\t\tline++;\n\t\tres++;\n\t}\n\treturn res;\n}\n\n/* print all lines to the window. */\nvoid fill_window(WINDOW *win, const char *text)\n{\n\tint x, y;\n\tint total_lines = get_line_no(text);\n\tint i;\n\n\tgetmaxyx(win, y, x);\n\t/* do not go over end of line */\n\ttotal_lines = min(total_lines, y);\n\tfor (i = 0; i < total_lines; i++) {\n\t\tchar tmp[x+10];\n\t\tconst char *line = get_line(text, i);\n\t\tint len = get_line_length(line);\n\t\tstrncpy(tmp, line, min(len, x));\n\t\ttmp[len] = '\\0';\n\t\tmvwprintw(win, i, 0, \"%s\", tmp);\n\t}\n}\n\n/* get the message, and buttons.\n * each button must be a char*\n * return the selected button\n *\n * this dialog is used for 2 different things:\n * 1) show a text box, no buttons.\n * 2) show a dialog, with horizontal buttons\n */\nint btn_dialog(WINDOW *main_window, const char *msg, int btn_num, ...)\n{\n\tva_list ap;\n\tchar *btn;\n\tint btns_width = 0;\n\tint msg_lines = 0;\n\tint msg_width = 0;\n\tint total_width;\n\tint win_rows = 0;\n\tWINDOW *win;\n\tWINDOW *msg_win;\n\tWINDOW *menu_win;\n\tMENU *menu;\n\tITEM *btns[btn_num+1];\n\tint i, x, y;\n\tint res = -1;\n\n\n\tva_start(ap, btn_num);\n\tfor (i = 0; i < btn_num; i++) {\n\t\tbtn = va_arg(ap, char *);\n\t\tbtns[i] = new_item(btn, \"\");\n\t\tbtns_width += strlen(btn)+1;\n\t}\n\tva_end(ap);\n\tbtns[btn_num] = NULL;\n\n\t/* find the widest line of msg: */\n\tmsg_lines = get_line_no(msg);\n\tfor (i = 0; i < msg_lines; i++) {\n\t\tconst char *line = get_line(msg, i);\n\t\tint len = get_line_length(line);\n\t\tif (msg_width < len)\n\t\t\tmsg_width = len;\n\t}\n\n\ttotal_width = max(msg_width, btns_width);\n\t/* place dialog in middle of screen */\n\ty = (getmaxy(stdscr)-(msg_lines+4))/2;\n\tx = (getmaxx(stdscr)-(total_width+4))/2;\n\n\n\t/* create the windows */\n\tif (btn_num > 0)\n\t\twin_rows = msg_lines+4;\n\telse\n\t\twin_rows = msg_lines+2;\n\n\twin = newwin(win_rows, total_width+4, y, x);\n\tkeypad(win, TRUE);\n\tmenu_win = derwin(win, 1, btns_width, win_rows-2,\n\t\t\t1+(total_width+2-btns_width)/2);\n\tmenu = new_menu(btns);\n\tmsg_win = derwin(win, win_rows-2, msg_width, 1,\n\t\t\t1+(total_width+2-msg_width)/2);\n\n\tset_menu_fore(menu, attr_dialog_menu_fore);\n\tset_menu_back(menu, attr_dialog_menu_back);\n\n\twattrset(win, attr_dialog_box);\n\tbox(win, 0, 0);\n\n\t/* print message */\n\twattrset(msg_win, attr_dialog_text);\n\tfill_window(msg_win, msg);\n\n\tset_menu_win(menu, win);\n\tset_menu_sub(menu, menu_win);\n\tset_menu_format(menu, 1, btn_num);\n\tmenu_opts_off(menu, O_SHOWDESC);\n\tmenu_opts_off(menu, O_SHOWMATCH);\n\tmenu_opts_on(menu, O_ONEVALUE);\n\tmenu_opts_on(menu, O_NONCYCLIC);\n\tset_menu_mark(menu, \"\");\n\tpost_menu(menu);\n\n\n\ttouchwin(win);\n\trefresh_all_windows(main_window);\n\twhile ((res = wgetch(win))) {\n\t\tswitch (res) {\n\t\tcase KEY_LEFT:\n\t\t\tmenu_driver(menu, REQ_LEFT_ITEM);\n\t\t\tbreak;\n\t\tcase KEY_RIGHT:\n\t\t\tmenu_driver(menu, REQ_RIGHT_ITEM);\n\t\t\tbreak;\n\t\tcase 10: /* ENTER */\n\t\tcase 27: /* ESCAPE */\n\t\tcase ' ':\n\t\tcase KEY_F(F_BACK):\n\t\tcase KEY_F(F_EXIT):\n\t\t\tbreak;\n\t\t}\n\t\ttouchwin(win);\n\t\trefresh_all_windows(main_window);\n\n\t\tif (res == 10 || res == ' ') {\n\t\t\tres = item_index(current_item(menu));\n\t\t\tbreak;\n\t\t} else if (res == 27 || res == KEY_F(F_BACK) ||\n\t\t\t\tres == KEY_F(F_EXIT)) {\n\t\t\tres = KEY_EXIT;\n\t\t\tbreak;\n\t\t}\n\t}\n\n\tunpost_menu(menu);\n\tfree_menu(menu);\n\tfor (i = 0; i < btn_num; i++)\n\t\tfree_item(btns[i]);\n\n\tdelwin(win);\n\treturn res;\n}\n\nint dialog_inputbox(WINDOW *main_window,\n\t\tconst char *title, const char *prompt,\n\t\tconst char *init, char **resultp, int *result_len)\n{\n\tint prompt_lines = 0;\n\tint prompt_width = 0;\n\tWINDOW *win;\n\tWINDOW *prompt_win;\n\tWINDOW *form_win;\n\tPANEL *panel;\n\tint i, x, y, lines, columns, win_lines, win_cols;\n\tint res = -1;\n\tint cursor_position = strlen(init);\n\tint cursor_form_win;\n\tchar *result = *resultp;\n\n\tgetmaxyx(stdscr, lines, columns);\n\n\tif (strlen(init)+1 > *result_len) {\n\t\t*result_len = strlen(init)+1;\n\t\t*resultp = result = xrealloc(result, *result_len);\n\t}\n\n\t/* find the widest line of msg: */\n\tprompt_lines = get_line_no(prompt);\n\tfor (i = 0; i < prompt_lines; i++) {\n\t\tconst char *line = get_line(prompt, i);\n\t\tint len = get_line_length(line);\n\t\tprompt_width = max(prompt_width, len);\n\t}\n\n\tif (title)\n\t\tprompt_width = max(prompt_width, strlen(title));\n\n\twin_lines = min(prompt_lines+6, lines-2);\n\twin_cols = min(prompt_width+7, columns-2);\n\tprompt_lines = max(win_lines-6, 0);\n\tprompt_width = max(win_cols-7, 0);\n\n\t/* place dialog in middle of screen */\n\ty = (lines-win_lines)/2;\n\tx = (columns-win_cols)/2;\n\n\tstrncpy(result, init, *result_len);\n\n\t/* create the windows */\n\twin = newwin(win_lines, win_cols, y, x);\n\tprompt_win = derwin(win, prompt_lines+1, prompt_width, 2, 2);\n\tform_win = derwin(win, 1, prompt_width, prompt_lines+3, 2);\n\tkeypad(form_win, TRUE);\n\n\twattrset(form_win, attr_input_field);\n\n\twattrset(win, attr_input_box);\n\tbox(win, 0, 0);\n\twattrset(win, attr_input_heading);\n\tif (title)\n\t\tmvwprintw(win, 0, 3, \"%s\", title);\n\n\t/* print message */\n\twattrset(prompt_win, attr_input_text);\n\tfill_window(prompt_win, prompt);\n\n\tmvwprintw(form_win, 0, 0, \"%*s\", prompt_width, \" \");\n\tcursor_form_win = min(cursor_position, prompt_width-1);\n\tmvwprintw(form_win, 0, 0, \"%s\",\n\t\t  result + cursor_position-cursor_form_win);\n\n\t/* create panels */\n\tpanel = new_panel(win);\n\n\t/* show the cursor */\n\tcurs_set(1);\n\n\ttouchwin(win);\n\trefresh_all_windows(main_window);\n\twhile ((res = wgetch(form_win))) {\n\t\tint len = strlen(result);\n\t\tswitch (res) {\n\t\tcase 10: /* ENTER */\n\t\tcase 27: /* ESCAPE */\n\t\tcase KEY_F(F_HELP):\n\t\tcase KEY_F(F_EXIT):\n\t\tcase KEY_F(F_BACK):\n\t\t\tbreak;\n\t\tcase 8:   /* ^H */\n\t\tcase 127: /* ^? */\n\t\tcase KEY_BACKSPACE:\n\t\t\tif (cursor_position > 0) {\n\t\t\t\tmemmove(&result[cursor_position-1],\n\t\t\t\t\t\t&result[cursor_position],\n\t\t\t\t\t\tlen-cursor_position+1);\n\t\t\t\tcursor_position--;\n\t\t\t\tcursor_form_win--;\n\t\t\t\tlen--;\n\t\t\t}\n\t\t\tbreak;\n\t\tcase KEY_DC:\n\t\t\tif (cursor_position >= 0 && cursor_position < len) {\n\t\t\t\tmemmove(&result[cursor_position],\n\t\t\t\t\t\t&result[cursor_position+1],\n\t\t\t\t\t\tlen-cursor_position+1);\n\t\t\t\tlen--;\n\t\t\t}\n\t\t\tbreak;\n\t\tcase KEY_UP:\n\t\tcase KEY_RIGHT:\n\t\t\tif (cursor_position < len) {\n\t\t\t\tcursor_position++;\n\t\t\t\tcursor_form_win++;\n\t\t\t}\n\t\t\tbreak;\n\t\tcase KEY_DOWN:\n\t\tcase KEY_LEFT:\n\t\t\tif (cursor_position > 0) {\n\t\t\t\tcursor_position--;\n\t\t\t\tcursor_form_win--;\n\t\t\t}\n\t\t\tbreak;\n\t\tcase KEY_HOME:\n\t\t\tcursor_position = 0;\n\t\t\tcursor_form_win = 0;\n\t\t\tbreak;\n\t\tcase KEY_END:\n\t\t\tcursor_position = len;\n\t\t\tcursor_form_win = min(cursor_position, prompt_width-1);\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tif ((isgraph(res) || isspace(res))) {\n\t\t\t\t/* one for new char, one for '\\0' */\n\t\t\t\tif (len+2 > *result_len) {\n\t\t\t\t\t*result_len = len+2;\n\t\t\t\t\t*resultp = result = realloc(result,\n\t\t\t\t\t\t\t\t*result_len);\n\t\t\t\t}\n\t\t\t\t/* insert the char at the proper position */\n\t\t\t\tmemmove(&result[cursor_position+1],\n\t\t\t\t\t\t&result[cursor_position],\n\t\t\t\t\t\tlen-cursor_position+1);\n\t\t\t\tresult[cursor_position] = res;\n\t\t\t\tcursor_position++;\n\t\t\t\tcursor_form_win++;\n\t\t\t\tlen++;\n\t\t\t} else {\n\t\t\t\tmvprintw(0, 0, \"unknown key: %d\\n\", res);\n\t\t\t}\n\t\t\tbreak;\n\t\t}\n\t\tif (cursor_form_win < 0)\n\t\t\tcursor_form_win = 0;\n\t\telse if (cursor_form_win > prompt_width-1)\n\t\t\tcursor_form_win = prompt_width-1;\n\n\t\twmove(form_win, 0, 0);\n\t\twclrtoeol(form_win);\n\t\tmvwprintw(form_win, 0, 0, \"%*s\", prompt_width, \" \");\n\t\tmvwprintw(form_win, 0, 0, \"%s\",\n\t\t\tresult + cursor_position-cursor_form_win);\n\t\twmove(form_win, 0, cursor_form_win);\n\t\ttouchwin(win);\n\t\trefresh_all_windows(main_window);\n\n\t\tif (res == 10) {\n\t\t\tres = 0;\n\t\t\tbreak;\n\t\t} else if (res == 27 || res == KEY_F(F_BACK) ||\n\t\t\t\tres == KEY_F(F_EXIT)) {\n\t\t\tres = KEY_EXIT;\n\t\t\tbreak;\n\t\t} else if (res == KEY_F(F_HELP)) {\n\t\t\tres = 1;\n\t\t\tbreak;\n\t\t}\n\t}\n\n\t/* hide the cursor */\n\tcurs_set(0);\n\tdel_panel(panel);\n\tdelwin(prompt_win);\n\tdelwin(form_win);\n\tdelwin(win);\n\treturn res;\n}\n\n/* refresh all windows in the correct order */\nvoid refresh_all_windows(WINDOW *main_window)\n{\n\tupdate_panels();\n\ttouchwin(main_window);\n\trefresh();\n}\n\n/* layman's scrollable window... */\nvoid show_scroll_win(WINDOW *main_window,\n\t\tconst char *title,\n\t\tconst char *text)\n{\n\tint res;\n\tint total_lines = get_line_no(text);\n\tint x, y, lines, columns;\n\tint start_x = 0, start_y = 0;\n\tint text_lines = 0, text_cols = 0;\n\tint total_cols = 0;\n\tint win_cols = 0;\n\tint win_lines = 0;\n\tint i = 0;\n\tWINDOW *win;\n\tWINDOW *pad;\n\tPANEL *panel;\n\n\tgetmaxyx(stdscr, lines, columns);\n\n\t/* find the widest line of msg: */\n\ttotal_lines = get_line_no(text);\n\tfor (i = 0; i < total_lines; i++) {\n\t\tconst char *line = get_line(text, i);\n\t\tint len = get_line_length(line);\n\t\ttotal_cols = max(total_cols, len+2);\n\t}\n\n\t/* create the pad */\n\tpad = newpad(total_lines+10, total_cols+10);\n\twattrset(pad, attr_scrollwin_text);\n\tfill_window(pad, text);\n\n\twin_lines = min(total_lines+4, lines-2);\n\twin_cols = min(total_cols+2, columns-2);\n\ttext_lines = max(win_lines-4, 0);\n\ttext_cols = max(win_cols-2, 0);\n\n\t/* place window in middle of screen */\n\ty = (lines-win_lines)/2;\n\tx = (columns-win_cols)/2;\n\n\twin = newwin(win_lines, win_cols, y, x);\n\tkeypad(win, TRUE);\n\t/* show the help in the help window, and show the help panel */\n\twattrset(win, attr_scrollwin_box);\n\tbox(win, 0, 0);\n\twattrset(win, attr_scrollwin_heading);\n\tmvwprintw(win, 0, 3, \" %s \", title);\n\tpanel = new_panel(win);\n\n\t/* handle scrolling */\n\tdo {\n\n\t\tcopywin(pad, win, start_y, start_x, 2, 2, text_lines,\n\t\t\t\ttext_cols, 0);\n\t\tprint_in_middle(win,\n\t\t\t\ttext_lines+2,\n\t\t\t\ttext_cols,\n\t\t\t\t\"<OK>\",\n\t\t\t\tattr_dialog_menu_fore);\n\t\twrefresh(win);\n\n\t\tres = wgetch(win);\n\t\tswitch (res) {\n\t\tcase KEY_NPAGE:\n\t\tcase ' ':\n\t\tcase 'd':\n\t\t\tstart_y += text_lines-2;\n\t\t\tbreak;\n\t\tcase KEY_PPAGE:\n\t\tcase 'u':\n\t\t\tstart_y -= text_lines+2;\n\t\t\tbreak;\n\t\tcase KEY_HOME:\n\t\t\tstart_y = 0;\n\t\t\tbreak;\n\t\tcase KEY_END:\n\t\t\tstart_y = total_lines-text_lines;\n\t\t\tbreak;\n\t\tcase KEY_DOWN:\n\t\tcase 'j':\n\t\t\tstart_y++;\n\t\t\tbreak;\n\t\tcase KEY_UP:\n\t\tcase 'k':\n\t\t\tstart_y--;\n\t\t\tbreak;\n\t\tcase KEY_LEFT:\n\t\tcase 'h':\n\t\t\tstart_x--;\n\t\t\tbreak;\n\t\tcase KEY_RIGHT:\n\t\tcase 'l':\n\t\t\tstart_x++;\n\t\t\tbreak;\n\t\t}\n\t\tif (res == 10 || res == 27 || res == 'q' ||\n\t\t\tres == KEY_F(F_HELP) || res == KEY_F(F_BACK) ||\n\t\t\tres == KEY_F(F_EXIT))\n\t\t\tbreak;\n\t\tif (start_y < 0)\n\t\t\tstart_y = 0;\n\t\tif (start_y >= total_lines-text_lines)\n\t\t\tstart_y = total_lines-text_lines;\n\t\tif (start_x < 0)\n\t\t\tstart_x = 0;\n\t\tif (start_x >= total_cols-text_cols)\n\t\t\tstart_x = total_cols-text_cols;\n\t} while (res);\n\n\tdel_panel(panel);\n\tdelwin(win);\n\trefresh_all_windows(main_window);\n}\n"
  },
  {
    "path": "scripts/config/nconf.h",
    "content": "/* SPDX-License-Identifier: GPL-2.0-only */\n/*\n * Copyright (C) 2008 Nir Tzachar <nir.tzachar@gmail.com>\n *\n * Derived from menuconfig.\n */\n\n#include <ctype.h>\n#include <errno.h>\n#include <fcntl.h>\n#include <limits.h>\n#include <stdarg.h>\n#include <stdlib.h>\n#include <string.h>\n#include <unistd.h>\n#include <ncurses.h>\n#include <menu.h>\n#include <panel.h>\n#include <form.h>\n\n#include <stdio.h>\n#include <time.h>\n#include <sys/time.h>\n\n#define max(a, b) ({\\\n\t\ttypeof(a) _a = a;\\\n\t\ttypeof(b) _b = b;\\\n\t\t_a > _b ? _a : _b; })\n\n#define min(a, b) ({\\\n\t\ttypeof(a) _a = a;\\\n\t\ttypeof(b) _b = b;\\\n\t\t_a < _b ? _a : _b; })\n\nextern int attr_normal;\nextern int attr_main_heading;\nextern int attr_main_menu_box;\nextern int attr_main_menu_fore;\nextern int attr_main_menu_back;\nextern int attr_main_menu_grey;\nextern int attr_main_menu_heading;\nextern int attr_scrollwin_text;\nextern int attr_scrollwin_heading;\nextern int attr_scrollwin_box;\nextern int attr_dialog_text;\nextern int attr_dialog_menu_fore;\nextern int attr_dialog_menu_back;\nextern int attr_dialog_box;\nextern int attr_input_box;\nextern int attr_input_heading;\nextern int attr_input_text;\nextern int attr_input_field;\nextern int attr_function_text;\nextern int attr_function_highlight;\n\ntypedef enum {\n\tF_HELP = 1,\n\tF_SYMBOL = 2,\n\tF_INSTS = 3,\n\tF_CONF = 4,\n\tF_BACK = 5,\n\tF_SAVE = 6,\n\tF_LOAD = 7,\n\tF_SEARCH = 8,\n\tF_EXIT = 9,\n} function_key;\n\nvoid set_colors(void);\n\n/* this changes the windows attributes !!! */\nvoid print_in_middle(WINDOW *win, int y, int width, const char *str, int attrs);\nint get_line_length(const char *line);\nint get_line_no(const char *text);\nconst char *get_line(const char *text, int line_no);\nvoid fill_window(WINDOW *win, const char *text);\nint btn_dialog(WINDOW *main_window, const char *msg, int btn_num, ...);\nint dialog_inputbox(WINDOW *main_window,\n\t\tconst char *title, const char *prompt,\n\t\tconst char *init, char **resultp, int *result_len);\nvoid refresh_all_windows(WINDOW *main_window);\nvoid show_scroll_win(WINDOW *main_window,\n\t\tconst char *title,\n\t\tconst char *text);\n"
  },
  {
    "path": "scripts/config/parser.tab.c",
    "content": "/* A Bison parser, made by GNU Bison 3.7.6.  */\n\n/* Bison implementation for Yacc-like parsers in C\n\n   Copyright (C) 1984, 1989-1990, 2000-2015, 2018-2021 Free Software Foundation,\n   Inc.\n\n   This program is free software: you can redistribute it and/or modify\n   it under the terms of the GNU General Public License as published by\n   the Free Software Foundation, either version 3 of the License, or\n   (at your option) any later version.\n\n   This program is distributed in the hope that it will be useful,\n   but WITHOUT ANY WARRANTY; without even the implied warranty of\n   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n   GNU General Public License for more details.\n\n   You should have received a copy of the GNU General Public License\n   along with this program.  If not, see <https://www.gnu.org/licenses/>.  */\n\n/* As a special exception, you may create a larger work that contains\n   part or all of the Bison parser skeleton and distribute that work\n   under terms of your choice, so long as that work isn't itself a\n   parser generator using the skeleton or a modified version thereof\n   as a parser skeleton.  Alternatively, if you modify or redistribute\n   the parser skeleton itself, you may (at your option) remove this\n   special exception, which will cause the skeleton and the resulting\n   Bison output files to be licensed under the GNU General Public\n   License without this special exception.\n\n   This special exception was added by the Free Software Foundation in\n   version 2.2 of Bison.  */\n\n/* C LALR(1) parser skeleton written by Richard Stallman, by\n   simplifying the original so-called \"semantic\" parser.  */\n\n/* DO NOT RELY ON FEATURES THAT ARE NOT DOCUMENTED in the manual,\n   especially those whose name start with YY_ or yy_.  They are\n   private implementation details that can be changed or removed.  */\n\n/* All symbols defined below should begin with yy or YY, to avoid\n   infringing on user name space.  This should be done even for local\n   variables, as they might otherwise be expanded by user macros.\n   There are some unavoidable exceptions within include files to\n   define necessary library symbols; they are noted \"INFRINGES ON\n   USER NAME SPACE\" below.  */\n\n/* Identify Bison output, and Bison version.  */\n#define YYBISON 30706\n\n/* Bison version string.  */\n#define YYBISON_VERSION \"3.7.6\"\n\n/* Skeleton name.  */\n#define YYSKELETON_NAME \"yacc.c\"\n\n/* Pure parsers.  */\n#define YYPURE 0\n\n/* Push parsers.  */\n#define YYPUSH 0\n\n/* Pull parsers.  */\n#define YYPULL 1\n\n\n\n\n/* First part of user prologue.  */\n\n\n#include <ctype.h>\n#include <stdarg.h>\n#include <stdio.h>\n#include <stdlib.h>\n#include <string.h>\n#include <stdbool.h>\n\n#include \"lkc.h\"\n#include \"internal.h\"\n\n#define printd(mask, fmt...) if (cdebug & (mask)) printf(fmt)\n\n#define PRINTD\t\t0x0001\n#define DEBUG_PARSE\t0x0002\n\nint cdebug = PRINTD;\n\nstatic void yyerror(const char *err);\nstatic void zconfprint(const char *err, ...);\nstatic void zconf_error(const char *err, ...);\nstatic bool zconf_endtoken(const char *tokenname,\n\t\t\t   const char *expected_tokenname);\n\nstruct symbol *symbol_hash[SYMBOL_HASHSIZE];\n\nstruct menu *current_menu, *current_entry;\n\n\n\n# ifndef YY_CAST\n#  ifdef __cplusplus\n#   define YY_CAST(Type, Val) static_cast<Type> (Val)\n#   define YY_REINTERPRET_CAST(Type, Val) reinterpret_cast<Type> (Val)\n#  else\n#   define YY_CAST(Type, Val) ((Type) (Val))\n#   define YY_REINTERPRET_CAST(Type, Val) ((Type) (Val))\n#  endif\n# endif\n# ifndef YY_NULLPTR\n#  if defined __cplusplus\n#   if 201103L <= __cplusplus\n#    define YY_NULLPTR nullptr\n#   else\n#    define YY_NULLPTR 0\n#   endif\n#  else\n#   define YY_NULLPTR ((void*)0)\n#  endif\n# endif\n\n#include \"parser.tab.h\"\n/* Symbol kind.  */\nenum yysymbol_kind_t\n{\n  YYSYMBOL_YYEMPTY = -2,\n  YYSYMBOL_YYEOF = 0,                      /* \"end of file\"  */\n  YYSYMBOL_YYerror = 1,                    /* error  */\n  YYSYMBOL_YYUNDEF = 2,                    /* \"invalid token\"  */\n  YYSYMBOL_T_HELPTEXT = 3,                 /* T_HELPTEXT  */\n  YYSYMBOL_T_WORD = 4,                     /* T_WORD  */\n  YYSYMBOL_T_WORD_QUOTE = 5,               /* T_WORD_QUOTE  */\n  YYSYMBOL_T_BOOL = 6,                     /* T_BOOL  */\n  YYSYMBOL_T_CHOICE = 7,                   /* T_CHOICE  */\n  YYSYMBOL_T_CLOSE_PAREN = 8,              /* T_CLOSE_PAREN  */\n  YYSYMBOL_T_COLON_EQUAL = 9,              /* T_COLON_EQUAL  */\n  YYSYMBOL_T_COMMENT = 10,                 /* T_COMMENT  */\n  YYSYMBOL_T_CONFIG = 11,                  /* T_CONFIG  */\n  YYSYMBOL_T_DEFAULT = 12,                 /* T_DEFAULT  */\n  YYSYMBOL_T_DEF_BOOL = 13,                /* T_DEF_BOOL  */\n  YYSYMBOL_T_DEF_TRISTATE = 14,            /* T_DEF_TRISTATE  */\n  YYSYMBOL_T_DEPENDS = 15,                 /* T_DEPENDS  */\n  YYSYMBOL_T_ENDCHOICE = 16,               /* T_ENDCHOICE  */\n  YYSYMBOL_T_ENDIF = 17,                   /* T_ENDIF  */\n  YYSYMBOL_T_ENDMENU = 18,                 /* T_ENDMENU  */\n  YYSYMBOL_T_HELP = 19,                    /* T_HELP  */\n  YYSYMBOL_T_HEX = 20,                     /* T_HEX  */\n  YYSYMBOL_T_IF = 21,                      /* T_IF  */\n  YYSYMBOL_T_IMPLY = 22,                   /* T_IMPLY  */\n  YYSYMBOL_T_INT = 23,                     /* T_INT  */\n  YYSYMBOL_T_MAINMENU = 24,                /* T_MAINMENU  */\n  YYSYMBOL_T_MENU = 25,                    /* T_MENU  */\n  YYSYMBOL_T_MENUCONFIG = 26,              /* T_MENUCONFIG  */\n  YYSYMBOL_T_MODULES = 27,                 /* T_MODULES  */\n  YYSYMBOL_T_ON = 28,                      /* T_ON  */\n  YYSYMBOL_T_OPEN_PAREN = 29,              /* T_OPEN_PAREN  */\n  YYSYMBOL_T_OPTIONAL = 30,                /* T_OPTIONAL  */\n  YYSYMBOL_T_PLUS_EQUAL = 31,              /* T_PLUS_EQUAL  */\n  YYSYMBOL_T_PROMPT = 32,                  /* T_PROMPT  */\n  YYSYMBOL_T_RANGE = 33,                   /* T_RANGE  */\n  YYSYMBOL_T_RESET = 34,                   /* T_RESET  */\n  YYSYMBOL_T_SELECT = 35,                  /* T_SELECT  */\n  YYSYMBOL_T_SOURCE = 36,                  /* T_SOURCE  */\n  YYSYMBOL_T_STRING = 37,                  /* T_STRING  */\n  YYSYMBOL_T_TRISTATE = 38,                /* T_TRISTATE  */\n  YYSYMBOL_T_VISIBLE = 39,                 /* T_VISIBLE  */\n  YYSYMBOL_T_EOL = 40,                     /* T_EOL  */\n  YYSYMBOL_T_ASSIGN_VAL = 41,              /* T_ASSIGN_VAL  */\n  YYSYMBOL_T_OR = 42,                      /* T_OR  */\n  YYSYMBOL_T_AND = 43,                     /* T_AND  */\n  YYSYMBOL_T_EQUAL = 44,                   /* T_EQUAL  */\n  YYSYMBOL_T_UNEQUAL = 45,                 /* T_UNEQUAL  */\n  YYSYMBOL_T_LESS = 46,                    /* T_LESS  */\n  YYSYMBOL_T_LESS_EQUAL = 47,              /* T_LESS_EQUAL  */\n  YYSYMBOL_T_GREATER = 48,                 /* T_GREATER  */\n  YYSYMBOL_T_GREATER_EQUAL = 49,           /* T_GREATER_EQUAL  */\n  YYSYMBOL_T_NOT = 50,                     /* T_NOT  */\n  YYSYMBOL_YYACCEPT = 51,                  /* $accept  */\n  YYSYMBOL_input = 52,                     /* input  */\n  YYSYMBOL_mainmenu_stmt = 53,             /* mainmenu_stmt  */\n  YYSYMBOL_stmt_list = 54,                 /* stmt_list  */\n  YYSYMBOL_stmt_list_in_choice = 55,       /* stmt_list_in_choice  */\n  YYSYMBOL_config_entry_start = 56,        /* config_entry_start  */\n  YYSYMBOL_config_stmt = 57,               /* config_stmt  */\n  YYSYMBOL_menuconfig_entry_start = 58,    /* menuconfig_entry_start  */\n  YYSYMBOL_menuconfig_stmt = 59,           /* menuconfig_stmt  */\n  YYSYMBOL_config_option_list = 60,        /* config_option_list  */\n  YYSYMBOL_config_option = 61,             /* config_option  */\n  YYSYMBOL_choice = 62,                    /* choice  */\n  YYSYMBOL_choice_entry = 63,              /* choice_entry  */\n  YYSYMBOL_choice_end = 64,                /* choice_end  */\n  YYSYMBOL_choice_stmt = 65,               /* choice_stmt  */\n  YYSYMBOL_choice_option_list = 66,        /* choice_option_list  */\n  YYSYMBOL_choice_option = 67,             /* choice_option  */\n  YYSYMBOL_type = 68,                      /* type  */\n  YYSYMBOL_logic_type = 69,                /* logic_type  */\n  YYSYMBOL_default = 70,                   /* default  */\n  YYSYMBOL_if_entry = 71,                  /* if_entry  */\n  YYSYMBOL_if_end = 72,                    /* if_end  */\n  YYSYMBOL_if_stmt = 73,                   /* if_stmt  */\n  YYSYMBOL_if_stmt_in_choice = 74,         /* if_stmt_in_choice  */\n  YYSYMBOL_menu = 75,                      /* menu  */\n  YYSYMBOL_menu_entry = 76,                /* menu_entry  */\n  YYSYMBOL_menu_end = 77,                  /* menu_end  */\n  YYSYMBOL_menu_stmt = 78,                 /* menu_stmt  */\n  YYSYMBOL_menu_option_list = 79,          /* menu_option_list  */\n  YYSYMBOL_source_stmt = 80,               /* source_stmt  */\n  YYSYMBOL_comment = 81,                   /* comment  */\n  YYSYMBOL_comment_stmt = 82,              /* comment_stmt  */\n  YYSYMBOL_comment_option_list = 83,       /* comment_option_list  */\n  YYSYMBOL_help_start = 84,                /* help_start  */\n  YYSYMBOL_help = 85,                      /* help  */\n  YYSYMBOL_depends = 86,                   /* depends  */\n  YYSYMBOL_visible = 87,                   /* visible  */\n  YYSYMBOL_prompt_stmt_opt = 88,           /* prompt_stmt_opt  */\n  YYSYMBOL_end = 89,                       /* end  */\n  YYSYMBOL_if_expr = 90,                   /* if_expr  */\n  YYSYMBOL_expr = 91,                      /* expr  */\n  YYSYMBOL_nonconst_symbol = 92,           /* nonconst_symbol  */\n  YYSYMBOL_symbol = 93,                    /* symbol  */\n  YYSYMBOL_word_opt = 94,                  /* word_opt  */\n  YYSYMBOL_assignment_stmt = 95,           /* assignment_stmt  */\n  YYSYMBOL_assign_op = 96,                 /* assign_op  */\n  YYSYMBOL_assign_val = 97                 /* assign_val  */\n};\ntypedef enum yysymbol_kind_t yysymbol_kind_t;\n\n\n\n\n#ifdef short\n# undef short\n#endif\n\n/* On compilers that do not define __PTRDIFF_MAX__ etc., make sure\n   <limits.h> and (if available) <stdint.h> are included\n   so that the code can choose integer types of a good width.  */\n\n#ifndef __PTRDIFF_MAX__\n# include <limits.h> /* INFRINGES ON USER NAME SPACE */\n# if defined __STDC_VERSION__ && 199901 <= __STDC_VERSION__\n#  include <stdint.h> /* INFRINGES ON USER NAME SPACE */\n#  define YY_STDINT_H\n# endif\n#endif\n\n/* Narrow types that promote to a signed type and that can represent a\n   signed or unsigned integer of at least N bits.  In tables they can\n   save space and decrease cache pressure.  Promoting to a signed type\n   helps avoid bugs in integer arithmetic.  */\n\n#ifdef __INT_LEAST8_MAX__\ntypedef __INT_LEAST8_TYPE__ yytype_int8;\n#elif defined YY_STDINT_H\ntypedef int_least8_t yytype_int8;\n#else\ntypedef signed char yytype_int8;\n#endif\n\n#ifdef __INT_LEAST16_MAX__\ntypedef __INT_LEAST16_TYPE__ yytype_int16;\n#elif defined YY_STDINT_H\ntypedef int_least16_t yytype_int16;\n#else\ntypedef short yytype_int16;\n#endif\n\n/* Work around bug in HP-UX 11.23, which defines these macros\n   incorrectly for preprocessor constants.  This workaround can likely\n   be removed in 2023, as HPE has promised support for HP-UX 11.23\n   (aka HP-UX 11i v2) only through the end of 2022; see Table 2 of\n   <https://h20195.www2.hpe.com/V2/getpdf.aspx/4AA4-7673ENW.pdf>.  */\n#ifdef __hpux\n# undef UINT_LEAST8_MAX\n# undef UINT_LEAST16_MAX\n# define UINT_LEAST8_MAX 255\n# define UINT_LEAST16_MAX 65535\n#endif\n\n#if defined __UINT_LEAST8_MAX__ && __UINT_LEAST8_MAX__ <= __INT_MAX__\ntypedef __UINT_LEAST8_TYPE__ yytype_uint8;\n#elif (!defined __UINT_LEAST8_MAX__ && defined YY_STDINT_H \\\n       && UINT_LEAST8_MAX <= INT_MAX)\ntypedef uint_least8_t yytype_uint8;\n#elif !defined __UINT_LEAST8_MAX__ && UCHAR_MAX <= INT_MAX\ntypedef unsigned char yytype_uint8;\n#else\ntypedef short yytype_uint8;\n#endif\n\n#if defined __UINT_LEAST16_MAX__ && __UINT_LEAST16_MAX__ <= __INT_MAX__\ntypedef __UINT_LEAST16_TYPE__ yytype_uint16;\n#elif (!defined __UINT_LEAST16_MAX__ && defined YY_STDINT_H \\\n       && UINT_LEAST16_MAX <= INT_MAX)\ntypedef uint_least16_t yytype_uint16;\n#elif !defined __UINT_LEAST16_MAX__ && USHRT_MAX <= INT_MAX\ntypedef unsigned short yytype_uint16;\n#else\ntypedef int yytype_uint16;\n#endif\n\n#ifndef YYPTRDIFF_T\n# if defined __PTRDIFF_TYPE__ && defined __PTRDIFF_MAX__\n#  define YYPTRDIFF_T __PTRDIFF_TYPE__\n#  define YYPTRDIFF_MAXIMUM __PTRDIFF_MAX__\n# elif defined PTRDIFF_MAX\n#  ifndef ptrdiff_t\n#   include <stddef.h> /* INFRINGES ON USER NAME SPACE */\n#  endif\n#  define YYPTRDIFF_T ptrdiff_t\n#  define YYPTRDIFF_MAXIMUM PTRDIFF_MAX\n# else\n#  define YYPTRDIFF_T long\n#  define YYPTRDIFF_MAXIMUM LONG_MAX\n# endif\n#endif\n\n#ifndef YYSIZE_T\n# ifdef __SIZE_TYPE__\n#  define YYSIZE_T __SIZE_TYPE__\n# elif defined size_t\n#  define YYSIZE_T size_t\n# elif defined __STDC_VERSION__ && 199901 <= __STDC_VERSION__\n#  include <stddef.h> /* INFRINGES ON USER NAME SPACE */\n#  define YYSIZE_T size_t\n# else\n#  define YYSIZE_T unsigned\n# endif\n#endif\n\n#define YYSIZE_MAXIMUM                                  \\\n  YY_CAST (YYPTRDIFF_T,                                 \\\n           (YYPTRDIFF_MAXIMUM < YY_CAST (YYSIZE_T, -1)  \\\n            ? YYPTRDIFF_MAXIMUM                         \\\n            : YY_CAST (YYSIZE_T, -1)))\n\n#define YYSIZEOF(X) YY_CAST (YYPTRDIFF_T, sizeof (X))\n\n\n/* Stored state numbers (used for stacks). */\ntypedef yytype_uint8 yy_state_t;\n\n/* State numbers in computations.  */\ntypedef int yy_state_fast_t;\n\n#ifndef YY_\n# if defined YYENABLE_NLS && YYENABLE_NLS\n#  if ENABLE_NLS\n#   include <libintl.h> /* INFRINGES ON USER NAME SPACE */\n#   define YY_(Msgid) dgettext (\"bison-runtime\", Msgid)\n#  endif\n# endif\n# ifndef YY_\n#  define YY_(Msgid) Msgid\n# endif\n#endif\n\n\n#ifndef YY_ATTRIBUTE_PURE\n# if defined __GNUC__ && 2 < __GNUC__ + (96 <= __GNUC_MINOR__)\n#  define YY_ATTRIBUTE_PURE __attribute__ ((__pure__))\n# else\n#  define YY_ATTRIBUTE_PURE\n# endif\n#endif\n\n#ifndef YY_ATTRIBUTE_UNUSED\n# if defined __GNUC__ && 2 < __GNUC__ + (7 <= __GNUC_MINOR__)\n#  define YY_ATTRIBUTE_UNUSED __attribute__ ((__unused__))\n# else\n#  define YY_ATTRIBUTE_UNUSED\n# endif\n#endif\n\n/* Suppress unused-variable warnings by \"using\" E.  */\n#if ! defined lint || defined __GNUC__\n# define YY_USE(E) ((void) (E))\n#else\n# define YY_USE(E) /* empty */\n#endif\n\n#if defined __GNUC__ && ! defined __ICC && 407 <= __GNUC__ * 100 + __GNUC_MINOR__\n/* Suppress an incorrect diagnostic about yylval being uninitialized.  */\n# define YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN                            \\\n    _Pragma (\"GCC diagnostic push\")                                     \\\n    _Pragma (\"GCC diagnostic ignored \\\"-Wuninitialized\\\"\")              \\\n    _Pragma (\"GCC diagnostic ignored \\\"-Wmaybe-uninitialized\\\"\")\n# define YY_IGNORE_MAYBE_UNINITIALIZED_END      \\\n    _Pragma (\"GCC diagnostic pop\")\n#else\n# define YY_INITIAL_VALUE(Value) Value\n#endif\n#ifndef YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN\n# define YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN\n# define YY_IGNORE_MAYBE_UNINITIALIZED_END\n#endif\n#ifndef YY_INITIAL_VALUE\n# define YY_INITIAL_VALUE(Value) /* Nothing. */\n#endif\n\n#if defined __cplusplus && defined __GNUC__ && ! defined __ICC && 6 <= __GNUC__\n# define YY_IGNORE_USELESS_CAST_BEGIN                          \\\n    _Pragma (\"GCC diagnostic push\")                            \\\n    _Pragma (\"GCC diagnostic ignored \\\"-Wuseless-cast\\\"\")\n# define YY_IGNORE_USELESS_CAST_END            \\\n    _Pragma (\"GCC diagnostic pop\")\n#endif\n#ifndef YY_IGNORE_USELESS_CAST_BEGIN\n# define YY_IGNORE_USELESS_CAST_BEGIN\n# define YY_IGNORE_USELESS_CAST_END\n#endif\n\n\n#define YY_ASSERT(E) ((void) (0 && (E)))\n\n#if !defined yyoverflow\n\n/* The parser invokes alloca or malloc; define the necessary symbols.  */\n\n# ifdef YYSTACK_USE_ALLOCA\n#  if YYSTACK_USE_ALLOCA\n#   ifdef __GNUC__\n#    define YYSTACK_ALLOC __builtin_alloca\n#   elif defined __BUILTIN_VA_ARG_INCR\n#    include <alloca.h> /* INFRINGES ON USER NAME SPACE */\n#   elif defined _AIX\n#    define YYSTACK_ALLOC __alloca\n#   elif defined _MSC_VER\n#    include <malloc.h> /* INFRINGES ON USER NAME SPACE */\n#    define alloca _alloca\n#   else\n#    define YYSTACK_ALLOC alloca\n#    if ! defined _ALLOCA_H && ! defined EXIT_SUCCESS\n#     include <stdlib.h> /* INFRINGES ON USER NAME SPACE */\n      /* Use EXIT_SUCCESS as a witness for stdlib.h.  */\n#     ifndef EXIT_SUCCESS\n#      define EXIT_SUCCESS 0\n#     endif\n#    endif\n#   endif\n#  endif\n# endif\n\n# ifdef YYSTACK_ALLOC\n   /* Pacify GCC's 'empty if-body' warning.  */\n#  define YYSTACK_FREE(Ptr) do { /* empty */; } while (0)\n#  ifndef YYSTACK_ALLOC_MAXIMUM\n    /* The OS might guarantee only one guard page at the bottom of the stack,\n       and a page size can be as small as 4096 bytes.  So we cannot safely\n       invoke alloca (N) if N exceeds 4096.  Use a slightly smaller number\n       to allow for a few compiler-allocated temporary stack slots.  */\n#   define YYSTACK_ALLOC_MAXIMUM 4032 /* reasonable circa 2006 */\n#  endif\n# else\n#  define YYSTACK_ALLOC YYMALLOC\n#  define YYSTACK_FREE YYFREE\n#  ifndef YYSTACK_ALLOC_MAXIMUM\n#   define YYSTACK_ALLOC_MAXIMUM YYSIZE_MAXIMUM\n#  endif\n#  if (defined __cplusplus && ! defined EXIT_SUCCESS \\\n       && ! ((defined YYMALLOC || defined malloc) \\\n             && (defined YYFREE || defined free)))\n#   include <stdlib.h> /* INFRINGES ON USER NAME SPACE */\n#   ifndef EXIT_SUCCESS\n#    define EXIT_SUCCESS 0\n#   endif\n#  endif\n#  ifndef YYMALLOC\n#   define YYMALLOC malloc\n#   if ! defined malloc && ! defined EXIT_SUCCESS\nvoid *malloc (YYSIZE_T); /* INFRINGES ON USER NAME SPACE */\n#   endif\n#  endif\n#  ifndef YYFREE\n#   define YYFREE free\n#   if ! defined free && ! defined EXIT_SUCCESS\nvoid free (void *); /* INFRINGES ON USER NAME SPACE */\n#   endif\n#  endif\n# endif\n#endif /* !defined yyoverflow */\n\n#if (! defined yyoverflow \\\n     && (! defined __cplusplus \\\n         || (defined YYSTYPE_IS_TRIVIAL && YYSTYPE_IS_TRIVIAL)))\n\n/* A type that is properly aligned for any stack member.  */\nunion yyalloc\n{\n  yy_state_t yyss_alloc;\n  YYSTYPE yyvs_alloc;\n};\n\n/* The size of the maximum gap between one aligned stack and the next.  */\n# define YYSTACK_GAP_MAXIMUM (YYSIZEOF (union yyalloc) - 1)\n\n/* The size of an array large to enough to hold all stacks, each with\n   N elements.  */\n# define YYSTACK_BYTES(N) \\\n     ((N) * (YYSIZEOF (yy_state_t) + YYSIZEOF (YYSTYPE)) \\\n      + YYSTACK_GAP_MAXIMUM)\n\n# define YYCOPY_NEEDED 1\n\n/* Relocate STACK from its old location to the new one.  The\n   local variables YYSIZE and YYSTACKSIZE give the old and new number of\n   elements in the stack, and YYPTR gives the new location of the\n   stack.  Advance YYPTR to a properly aligned location for the next\n   stack.  */\n# define YYSTACK_RELOCATE(Stack_alloc, Stack)                           \\\n    do                                                                  \\\n      {                                                                 \\\n        YYPTRDIFF_T yynewbytes;                                         \\\n        YYCOPY (&yyptr->Stack_alloc, Stack, yysize);                    \\\n        Stack = &yyptr->Stack_alloc;                                    \\\n        yynewbytes = yystacksize * YYSIZEOF (*Stack) + YYSTACK_GAP_MAXIMUM; \\\n        yyptr += yynewbytes / YYSIZEOF (*yyptr);                        \\\n      }                                                                 \\\n    while (0)\n\n#endif\n\n#if defined YYCOPY_NEEDED && YYCOPY_NEEDED\n/* Copy COUNT objects from SRC to DST.  The source and destination do\n   not overlap.  */\n# ifndef YYCOPY\n#  if defined __GNUC__ && 1 < __GNUC__\n#   define YYCOPY(Dst, Src, Count) \\\n      __builtin_memcpy (Dst, Src, YY_CAST (YYSIZE_T, (Count)) * sizeof (*(Src)))\n#  else\n#   define YYCOPY(Dst, Src, Count)              \\\n      do                                        \\\n        {                                       \\\n          YYPTRDIFF_T yyi;                      \\\n          for (yyi = 0; yyi < (Count); yyi++)   \\\n            (Dst)[yyi] = (Src)[yyi];            \\\n        }                                       \\\n      while (0)\n#  endif\n# endif\n#endif /* !YYCOPY_NEEDED */\n\n/* YYFINAL -- State number of the termination state.  */\n#define YYFINAL  6\n/* YYLAST -- Last index in YYTABLE.  */\n#define YYLAST   194\n\n/* YYNTOKENS -- Number of terminals.  */\n#define YYNTOKENS  51\n/* YYNNTS -- Number of nonterminals.  */\n#define YYNNTS  47\n/* YYNRULES -- Number of rules.  */\n#define YYNRULES  106\n/* YYNSTATES -- Number of states.  */\n#define YYNSTATES  187\n\n/* YYMAXUTOK -- Last valid token kind.  */\n#define YYMAXUTOK   305\n\n\n/* YYTRANSLATE(TOKEN-NUM) -- Symbol number corresponding to TOKEN-NUM\n   as returned by yylex, with out-of-bounds checking.  */\n#define YYTRANSLATE(YYX)                                \\\n  (0 <= (YYX) && (YYX) <= YYMAXUTOK                     \\\n   ? YY_CAST (yysymbol_kind_t, yytranslate[YYX])        \\\n   : YYSYMBOL_YYUNDEF)\n\n/* YYTRANSLATE[TOKEN-NUM] -- Symbol number corresponding to TOKEN-NUM\n   as returned by yylex.  */\nstatic const yytype_int8 yytranslate[] =\n{\n       0,     2,     2,     2,     2,     2,     2,     2,     2,     2,\n       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,\n       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,\n       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,\n       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,\n       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,\n       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,\n       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,\n       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,\n       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,\n       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,\n       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,\n       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,\n       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,\n       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,\n       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,\n       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,\n       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,\n       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,\n       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,\n       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,\n       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,\n       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,\n       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,\n       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,\n       2,     2,     2,     2,     2,     2,     1,     2,     3,     4,\n       5,     6,     7,     8,     9,    10,    11,    12,    13,    14,\n      15,    16,    17,    18,    19,    20,    21,    22,    23,    24,\n      25,    26,    27,    28,    29,    30,    31,    32,    33,    34,\n      35,    36,    37,    38,    39,    40,    41,    42,    43,    44,\n      45,    46,    47,    48,    49,    50\n};\n\n#if YYDEBUG\n  /* YYRLINE[YYN] -- Source line where rule number YYN was defined.  */\nstatic const yytype_int16 yyrline[] =\n{\n       0,   110,   110,   110,   114,   119,   121,   122,   123,   124,\n     125,   126,   127,   128,   129,   130,   133,   135,   136,   137,\n     138,   143,   150,   155,   162,   171,   173,   174,   175,   178,\n     186,   192,   202,   208,   214,   220,   230,   240,   245,   253,\n     256,   258,   259,   260,   263,   269,   276,   282,   287,   295,\n     296,   297,   298,   301,   302,   305,   306,   307,   311,   319,\n     327,   330,   335,   342,   347,   355,   358,   360,   361,   364,\n     373,   380,   383,   385,   390,   396,   408,   415,   422,   424,\n     429,   430,   431,   434,   435,   438,   439,   440,   441,   442,\n     443,   444,   445,   446,   447,   448,   452,   454,   455,   458,\n     459,   463,   466,   467,   468,   472,   473\n};\n#endif\n\n/** Accessing symbol of state STATE.  */\n#define YY_ACCESSING_SYMBOL(State) YY_CAST (yysymbol_kind_t, yystos[State])\n\n#if YYDEBUG || 0\n/* The user-facing name of the symbol whose (internal) number is\n   YYSYMBOL.  No bounds checking.  */\nstatic const char *yysymbol_name (yysymbol_kind_t yysymbol) YY_ATTRIBUTE_UNUSED;\n\n/* YYTNAME[SYMBOL-NUM] -- String name of the symbol SYMBOL-NUM.\n   First, the terminals, then, starting at YYNTOKENS, nonterminals.  */\nstatic const char *const yytname[] =\n{\n  \"\\\"end of file\\\"\", \"error\", \"\\\"invalid token\\\"\", \"T_HELPTEXT\", \"T_WORD\",\n  \"T_WORD_QUOTE\", \"T_BOOL\", \"T_CHOICE\", \"T_CLOSE_PAREN\", \"T_COLON_EQUAL\",\n  \"T_COMMENT\", \"T_CONFIG\", \"T_DEFAULT\", \"T_DEF_BOOL\", \"T_DEF_TRISTATE\",\n  \"T_DEPENDS\", \"T_ENDCHOICE\", \"T_ENDIF\", \"T_ENDMENU\", \"T_HELP\", \"T_HEX\",\n  \"T_IF\", \"T_IMPLY\", \"T_INT\", \"T_MAINMENU\", \"T_MENU\", \"T_MENUCONFIG\",\n  \"T_MODULES\", \"T_ON\", \"T_OPEN_PAREN\", \"T_OPTIONAL\", \"T_PLUS_EQUAL\",\n  \"T_PROMPT\", \"T_RANGE\", \"T_RESET\", \"T_SELECT\", \"T_SOURCE\", \"T_STRING\",\n  \"T_TRISTATE\", \"T_VISIBLE\", \"T_EOL\", \"T_ASSIGN_VAL\", \"T_OR\", \"T_AND\",\n  \"T_EQUAL\", \"T_UNEQUAL\", \"T_LESS\", \"T_LESS_EQUAL\", \"T_GREATER\",\n  \"T_GREATER_EQUAL\", \"T_NOT\", \"$accept\", \"input\", \"mainmenu_stmt\",\n  \"stmt_list\", \"stmt_list_in_choice\", \"config_entry_start\", \"config_stmt\",\n  \"menuconfig_entry_start\", \"menuconfig_stmt\", \"config_option_list\",\n  \"config_option\", \"choice\", \"choice_entry\", \"choice_end\", \"choice_stmt\",\n  \"choice_option_list\", \"choice_option\", \"type\", \"logic_type\", \"default\",\n  \"if_entry\", \"if_end\", \"if_stmt\", \"if_stmt_in_choice\", \"menu\",\n  \"menu_entry\", \"menu_end\", \"menu_stmt\", \"menu_option_list\", \"source_stmt\",\n  \"comment\", \"comment_stmt\", \"comment_option_list\", \"help_start\", \"help\",\n  \"depends\", \"visible\", \"prompt_stmt_opt\", \"end\", \"if_expr\", \"expr\",\n  \"nonconst_symbol\", \"symbol\", \"word_opt\", \"assignment_stmt\", \"assign_op\",\n  \"assign_val\", YY_NULLPTR\n};\n\nstatic const char *\nyysymbol_name (yysymbol_kind_t yysymbol)\n{\n  return yytname[yysymbol];\n}\n#endif\n\n#ifdef YYPRINT\n/* YYTOKNUM[NUM] -- (External) token number corresponding to the\n   (internal) symbol number NUM (which must be that of a token).  */\nstatic const yytype_int16 yytoknum[] =\n{\n       0,   256,   257,   258,   259,   260,   261,   262,   263,   264,\n     265,   266,   267,   268,   269,   270,   271,   272,   273,   274,\n     275,   276,   277,   278,   279,   280,   281,   282,   283,   284,\n     285,   286,   287,   288,   289,   290,   291,   292,   293,   294,\n     295,   296,   297,   298,   299,   300,   301,   302,   303,   304,\n     305\n};\n#endif\n\n#define YYPACT_NINF (-105)\n\n#define yypact_value_is_default(Yyn) \\\n  ((Yyn) == YYPACT_NINF)\n\n#define YYTABLE_NINF (-4)\n\n#define yytable_value_is_error(Yyn) \\\n  0\n\n  /* YYPACT[STATE-NUM] -- Index in YYTABLE of the portion describing\n     STATE-NUM.  */\nstatic const yytype_int16 yypact[] =\n{\n      -5,    17,    37,  -105,    57,     8,  -105,    91,    39,    15,\n      46,    72,    80,    10,    82,    80,    83,  -105,  -105,  -105,\n    -105,  -105,  -105,  -105,  -105,  -105,  -105,  -105,  -105,  -105,\n    -105,  -105,  -105,  -105,  -105,    45,  -105,  -105,  -105,    48,\n    -105,    50,    59,  -105,    60,  -105,    10,    10,    -7,  -105,\n      25,    63,    64,    65,   132,   132,   156,   162,   114,    14,\n     114,    95,  -105,  -105,    71,  -105,  -105,  -105,     9,  -105,\n    -105,    10,    10,    27,    27,    27,    27,    27,    27,  -105,\n    -105,  -105,  -105,  -105,  -105,  -105,    69,    73,  -105,    80,\n    -105,    74,   115,    27,    80,  -105,  -105,  -105,   117,  -105,\n      10,   116,  -105,  -105,    80,    86,   118,   107,  -105,   117,\n    -105,  -105,    89,    93,    94,    96,  -105,  -105,  -105,  -105,\n    -105,  -105,  -105,  -105,   107,  -105,  -105,  -105,  -105,  -105,\n    -105,  -105,    98,  -105,  -105,  -105,  -105,  -105,  -105,  -105,\n      10,  -105,   107,  -105,   107,    27,   107,   107,    97,    13,\n    -105,   107,  -105,   107,    10,   102,   103,  -105,  -105,  -105,\n    -105,   162,   108,    23,   109,   113,   107,   120,  -105,  -105,\n     121,   126,   134,    33,  -105,  -105,  -105,  -105,  -105,  -105,\n    -105,   136,  -105,  -105,  -105,  -105,  -105\n};\n\n  /* YYDEFACT[STATE-NUM] -- Default reduction number in state STATE-NUM.\n     Performed when YYTABLE does not specify something else to do.  Zero\n     means the default is an error.  */\nstatic const yytype_int8 yydefact[] =\n{\n       5,     0,     0,     5,     0,     0,     1,     0,     0,     0,\n      99,     0,     0,     0,     0,     0,     0,    25,     9,    25,\n      12,    40,    16,     7,     5,    10,    66,     5,    11,    13,\n      72,     8,     6,     4,    15,     0,   103,   104,   102,   105,\n     100,     0,     0,    96,     0,    98,     0,     0,     0,    97,\n      85,     0,     0,     0,    22,    24,    37,     0,     0,    63,\n       0,    71,    14,   106,     0,    36,    70,    21,     0,    93,\n      58,     0,     0,     0,     0,     0,     0,     0,     0,    62,\n      23,    69,    53,    55,    56,    57,     0,     0,    51,     0,\n      50,     0,     0,     0,     0,    52,    54,    26,    78,    49,\n       0,     0,    28,    27,     0,     0,     0,    83,    41,    78,\n      43,    42,     0,     0,     0,     0,    18,    39,    16,    19,\n      17,    38,    60,    59,    83,    68,    67,    65,    64,    73,\n     101,    92,    94,    95,    90,    91,    86,    87,    88,    89,\n       0,    74,    83,    35,    83,     0,    83,    83,     0,    83,\n      75,    83,    46,    83,     0,     0,     0,    20,    81,    82,\n      80,     0,     0,     0,     0,     0,    83,     0,    79,    29,\n       0,     0,     0,    84,    47,    45,    61,    77,    76,    33,\n      30,     0,    32,    31,    48,    44,    34\n};\n\n  /* YYPGOTO[NTERM-NUM].  */\nstatic const yytype_int16 yypgoto[] =\n{\n    -105,  -105,  -105,     3,    38,  -105,   -55,  -105,  -105,   138,\n    -105,  -105,  -105,  -105,  -105,  -105,  -105,  -105,   125,  -105,\n     -54,    -3,  -105,  -105,  -105,  -105,  -105,  -105,  -105,  -105,\n    -105,   -52,  -105,  -105,   128,   -38,  -105,    68,   -16,  -104,\n     -46,    -8,   -65,  -105,  -105,  -105,  -105\n};\n\n  /* YYDEFGOTO[NTERM-NUM].  */\nstatic const yytype_uint8 yydefgoto[] =\n{\n       0,     2,     3,     4,    57,    17,    18,    19,    20,    54,\n      97,    21,    22,   117,    23,    56,   108,    98,    99,   100,\n      24,   122,    25,   119,    26,    27,   127,    28,    59,    29,\n      30,    31,    61,   101,   102,   103,   126,   148,   123,   155,\n      48,    49,    50,    41,    32,    39,    64\n};\n\n  /* YYTABLE[YYPACT[STATE-NUM]] -- What to do in state STATE-NUM.  If\n     positive, shift that token.  If negative, reduce the rule whose\n     number is the opposite.  If YYTABLE_NINF, syntax error.  */\nstatic const yytype_int16 yytable[] =\n{\n      68,    69,   116,   118,    44,   120,     7,    52,   134,   135,\n     136,   137,   138,   139,    43,    45,    35,   131,   111,     1,\n     162,   125,     5,   129,    36,   132,   133,    58,   145,    86,\n      60,    43,    45,    70,   154,    71,    72,     6,   164,    46,\n     165,   121,   167,   168,   128,   170,    37,   171,    33,   172,\n      40,    71,    72,   124,   149,    71,    72,    -3,     8,    38,\n      47,     9,   181,   178,    10,    71,    72,    11,    12,    73,\n      74,    75,    76,    77,    78,    71,    72,    42,    13,    34,\n     166,   142,    14,    15,    43,    62,   146,    51,    53,    63,\n      65,    -2,     8,    16,   163,     9,   151,   140,    10,    66,\n      67,    11,    12,    79,    80,    81,   116,   118,   173,   120,\n      86,   130,    13,   141,   143,     8,    14,    15,     9,   150,\n     144,    10,   147,   153,    11,    12,   152,    16,   154,   157,\n     113,   114,   115,   158,   159,    13,   160,   169,    82,    14,\n      15,    72,   174,   175,    83,    84,    85,    86,   177,   179,\n      16,    87,    88,   180,    89,    90,   161,    55,   176,    91,\n     182,   183,    82,   112,    92,    93,   184,    94,   104,    95,\n      96,    86,    11,    12,   185,    87,   186,   156,   113,   114,\n     115,   109,     0,    13,   110,     0,   105,     0,   106,     0,\n     107,     0,     0,     0,    96\n};\n\nstatic const yytype_int16 yycheck[] =\n{\n      46,    47,    57,    57,    12,    57,     3,    15,    73,    74,\n      75,    76,    77,    78,     4,     5,     1,     8,    56,    24,\n     124,    59,     5,    61,     9,    71,    72,    24,    93,    15,\n      27,     4,     5,    40,    21,    42,    43,     0,   142,    29,\n     144,    57,   146,   147,    60,   149,    31,   151,    40,   153,\n       4,    42,    43,    39,   100,    42,    43,     0,     1,    44,\n      50,     4,   166,    40,     7,    42,    43,    10,    11,    44,\n      45,    46,    47,    48,    49,    42,    43,     5,    21,    40,\n     145,    89,    25,    26,     4,    40,    94,     5,     5,    41,\n      40,     0,     1,    36,   140,     4,   104,    28,     7,    40,\n      40,    10,    11,    40,    40,    40,   161,   161,   154,   161,\n      15,    40,    21,    40,    40,     1,    25,    26,     4,     3,\n       5,     7,     5,     5,    10,    11,    40,    36,    21,    40,\n      16,    17,    18,    40,    40,    21,    40,    40,     6,    25,\n      26,    43,    40,    40,    12,    13,    14,    15,    40,    40,\n      36,    19,    20,    40,    22,    23,   118,    19,   161,    27,\n      40,    40,     6,     1,    32,    33,    40,    35,    12,    37,\n      38,    15,    10,    11,    40,    19,    40,   109,    16,    17,\n      18,    56,    -1,    21,    56,    -1,    30,    -1,    32,    -1,\n      34,    -1,    -1,    -1,    38\n};\n\n  /* YYSTOS[STATE-NUM] -- The (internal number of the) accessing\n     symbol of state STATE-NUM.  */\nstatic const yytype_int8 yystos[] =\n{\n       0,    24,    52,    53,    54,     5,     0,    54,     1,     4,\n       7,    10,    11,    21,    25,    26,    36,    56,    57,    58,\n      59,    62,    63,    65,    71,    73,    75,    76,    78,    80,\n      81,    82,    95,    40,    40,     1,     9,    31,    44,    96,\n       4,    94,     5,     4,    92,     5,    29,    50,    91,    92,\n      93,     5,    92,     5,    60,    60,    66,    55,    54,    79,\n      54,    83,    40,    41,    97,    40,    40,    40,    91,    91,\n      40,    42,    43,    44,    45,    46,    47,    48,    49,    40,\n      40,    40,     6,    12,    13,    14,    15,    19,    20,    22,\n      23,    27,    32,    33,    35,    37,    38,    61,    68,    69,\n      70,    84,    85,    86,    12,    30,    32,    34,    67,    69,\n      85,    86,     1,    16,    17,    18,    57,    64,    71,    74,\n      82,    89,    72,    89,    39,    86,    87,    77,    89,    86,\n      40,     8,    91,    91,    93,    93,    93,    93,    93,    93,\n      28,    40,    92,    40,     5,    93,    92,     5,    88,    91,\n       3,    92,    40,     5,    21,    90,    88,    40,    40,    40,\n      40,    55,    90,    91,    90,    90,    93,    90,    90,    40,\n      90,    90,    90,    91,    40,    40,    72,    40,    40,    40,\n      40,    90,    40,    40,    40,    40,    40\n};\n\n  /* YYR1[YYN] -- Symbol number of symbol that rule YYN derives.  */\nstatic const yytype_int8 yyr1[] =\n{\n       0,    51,    52,    52,    53,    54,    54,    54,    54,    54,\n      54,    54,    54,    54,    54,    54,    55,    55,    55,    55,\n      55,    56,    57,    58,    59,    60,    60,    60,    60,    61,\n      61,    61,    61,    61,    61,    61,    62,    63,    64,    65,\n      66,    66,    66,    66,    67,    67,    67,    67,    67,    68,\n      68,    68,    68,    69,    69,    70,    70,    70,    71,    72,\n      73,    74,    75,    76,    77,    78,    79,    79,    79,    80,\n      81,    82,    83,    83,    84,    85,    86,    87,    88,    88,\n      89,    89,    89,    90,    90,    91,    91,    91,    91,    91,\n      91,    91,    91,    91,    91,    91,    92,    93,    93,    94,\n      94,    95,    96,    96,    96,    97,    97\n};\n\n  /* YYR2[YYN] -- Number of symbols on the right hand side of rule YYN.  */\nstatic const yytype_int8 yyr2[] =\n{\n       0,     2,     2,     1,     3,     0,     2,     2,     2,     2,\n       2,     2,     2,     2,     4,     3,     0,     2,     2,     2,\n       3,     3,     2,     3,     2,     0,     2,     2,     2,     3,\n       4,     4,     4,     4,     5,     2,     3,     2,     1,     3,\n       0,     2,     2,     2,     4,     3,     2,     3,     4,     1,\n       1,     1,     1,     1,     1,     1,     1,     1,     3,     1,\n       3,     3,     3,     2,     1,     3,     0,     2,     2,     3,\n       3,     2,     0,     2,     2,     2,     4,     3,     0,     2,\n       2,     2,     2,     0,     2,     1,     3,     3,     3,     3,\n       3,     3,     3,     2,     3,     3,     1,     1,     1,     0,\n       1,     4,     1,     1,     1,     0,     1\n};\n\n\nenum { YYENOMEM = -2 };\n\n#define yyerrok         (yyerrstatus = 0)\n#define yyclearin       (yychar = YYEMPTY)\n\n#define YYACCEPT        goto yyacceptlab\n#define YYABORT         goto yyabortlab\n#define YYERROR         goto yyerrorlab\n\n\n#define YYRECOVERING()  (!!yyerrstatus)\n\n#define YYBACKUP(Token, Value)                                    \\\n  do                                                              \\\n    if (yychar == YYEMPTY)                                        \\\n      {                                                           \\\n        yychar = (Token);                                         \\\n        yylval = (Value);                                         \\\n        YYPOPSTACK (yylen);                                       \\\n        yystate = *yyssp;                                         \\\n        goto yybackup;                                            \\\n      }                                                           \\\n    else                                                          \\\n      {                                                           \\\n        yyerror (YY_(\"syntax error: cannot back up\")); \\\n        YYERROR;                                                  \\\n      }                                                           \\\n  while (0)\n\n/* Backward compatibility with an undocumented macro.\n   Use YYerror or YYUNDEF. */\n#define YYERRCODE YYUNDEF\n\n\n/* Enable debugging if requested.  */\n#if YYDEBUG\n\n# ifndef YYFPRINTF\n#  include <stdio.h> /* INFRINGES ON USER NAME SPACE */\n#  define YYFPRINTF fprintf\n# endif\n\n# define YYDPRINTF(Args)                        \\\ndo {                                            \\\n  if (yydebug)                                  \\\n    YYFPRINTF Args;                             \\\n} while (0)\n\n/* This macro is provided for backward compatibility. */\n# ifndef YY_LOCATION_PRINT\n#  define YY_LOCATION_PRINT(File, Loc) ((void) 0)\n# endif\n\n\n# define YY_SYMBOL_PRINT(Title, Kind, Value, Location)                    \\\ndo {                                                                      \\\n  if (yydebug)                                                            \\\n    {                                                                     \\\n      YYFPRINTF (stderr, \"%s \", Title);                                   \\\n      yy_symbol_print (stderr,                                            \\\n                  Kind, Value); \\\n      YYFPRINTF (stderr, \"\\n\");                                           \\\n    }                                                                     \\\n} while (0)\n\n\n/*-----------------------------------.\n| Print this symbol's value on YYO.  |\n`-----------------------------------*/\n\nstatic void\nyy_symbol_value_print (FILE *yyo,\n                       yysymbol_kind_t yykind, YYSTYPE const * const yyvaluep)\n{\n  FILE *yyoutput = yyo;\n  YY_USE (yyoutput);\n  if (!yyvaluep)\n    return;\n# ifdef YYPRINT\n  if (yykind < YYNTOKENS)\n    YYPRINT (yyo, yytoknum[yykind], *yyvaluep);\n# endif\n  YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN\n  YY_USE (yykind);\n  YY_IGNORE_MAYBE_UNINITIALIZED_END\n}\n\n\n/*---------------------------.\n| Print this symbol on YYO.  |\n`---------------------------*/\n\nstatic void\nyy_symbol_print (FILE *yyo,\n                 yysymbol_kind_t yykind, YYSTYPE const * const yyvaluep)\n{\n  YYFPRINTF (yyo, \"%s %s (\",\n             yykind < YYNTOKENS ? \"token\" : \"nterm\", yysymbol_name (yykind));\n\n  yy_symbol_value_print (yyo, yykind, yyvaluep);\n  YYFPRINTF (yyo, \")\");\n}\n\n/*------------------------------------------------------------------.\n| yy_stack_print -- Print the state stack from its BOTTOM up to its |\n| TOP (included).                                                   |\n`------------------------------------------------------------------*/\n\nstatic void\nyy_stack_print (yy_state_t *yybottom, yy_state_t *yytop)\n{\n  YYFPRINTF (stderr, \"Stack now\");\n  for (; yybottom <= yytop; yybottom++)\n    {\n      int yybot = *yybottom;\n      YYFPRINTF (stderr, \" %d\", yybot);\n    }\n  YYFPRINTF (stderr, \"\\n\");\n}\n\n# define YY_STACK_PRINT(Bottom, Top)                            \\\ndo {                                                            \\\n  if (yydebug)                                                  \\\n    yy_stack_print ((Bottom), (Top));                           \\\n} while (0)\n\n\n/*------------------------------------------------.\n| Report that the YYRULE is going to be reduced.  |\n`------------------------------------------------*/\n\nstatic void\nyy_reduce_print (yy_state_t *yyssp, YYSTYPE *yyvsp,\n                 int yyrule)\n{\n  int yylno = yyrline[yyrule];\n  int yynrhs = yyr2[yyrule];\n  int yyi;\n  YYFPRINTF (stderr, \"Reducing stack by rule %d (line %d):\\n\",\n             yyrule - 1, yylno);\n  /* The symbols being reduced.  */\n  for (yyi = 0; yyi < yynrhs; yyi++)\n    {\n      YYFPRINTF (stderr, \"   $%d = \", yyi + 1);\n      yy_symbol_print (stderr,\n                       YY_ACCESSING_SYMBOL (+yyssp[yyi + 1 - yynrhs]),\n                       &yyvsp[(yyi + 1) - (yynrhs)]);\n      YYFPRINTF (stderr, \"\\n\");\n    }\n}\n\n# define YY_REDUCE_PRINT(Rule)          \\\ndo {                                    \\\n  if (yydebug)                          \\\n    yy_reduce_print (yyssp, yyvsp, Rule); \\\n} while (0)\n\n/* Nonzero means print parse trace.  It is left uninitialized so that\n   multiple parsers can coexist.  */\nint yydebug;\n#else /* !YYDEBUG */\n# define YYDPRINTF(Args) ((void) 0)\n# define YY_SYMBOL_PRINT(Title, Kind, Value, Location)\n# define YY_STACK_PRINT(Bottom, Top)\n# define YY_REDUCE_PRINT(Rule)\n#endif /* !YYDEBUG */\n\n\n/* YYINITDEPTH -- initial size of the parser's stacks.  */\n#ifndef YYINITDEPTH\n# define YYINITDEPTH 200\n#endif\n\n/* YYMAXDEPTH -- maximum size the stacks can grow to (effective only\n   if the built-in stack extension method is used).\n\n   Do not make this value too large; the results are undefined if\n   YYSTACK_ALLOC_MAXIMUM < YYSTACK_BYTES (YYMAXDEPTH)\n   evaluated with infinite-precision integer arithmetic.  */\n\n#ifndef YYMAXDEPTH\n# define YYMAXDEPTH 10000\n#endif\n\n\n\n\n\n\n/*-----------------------------------------------.\n| Release the memory associated to this symbol.  |\n`-----------------------------------------------*/\n\nstatic void\nyydestruct (const char *yymsg,\n            yysymbol_kind_t yykind, YYSTYPE *yyvaluep)\n{\n  YY_USE (yyvaluep);\n  if (!yymsg)\n    yymsg = \"Deleting\";\n  YY_SYMBOL_PRINT (yymsg, yykind, yyvaluep, yylocationp);\n\n  YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN\n  switch (yykind)\n    {\n    case YYSYMBOL_choice_entry: /* choice_entry  */\n            {\n\tfprintf(stderr, \"%s:%d: missing end statement for this entry\\n\",\n\t\t((*yyvaluep).menu)->file->name, ((*yyvaluep).menu)->lineno);\n\tif (current_menu == ((*yyvaluep).menu))\n\t\tmenu_end_menu();\n}\n        break;\n\n    case YYSYMBOL_if_entry: /* if_entry  */\n            {\n\tfprintf(stderr, \"%s:%d: missing end statement for this entry\\n\",\n\t\t((*yyvaluep).menu)->file->name, ((*yyvaluep).menu)->lineno);\n\tif (current_menu == ((*yyvaluep).menu))\n\t\tmenu_end_menu();\n}\n        break;\n\n    case YYSYMBOL_menu_entry: /* menu_entry  */\n            {\n\tfprintf(stderr, \"%s:%d: missing end statement for this entry\\n\",\n\t\t((*yyvaluep).menu)->file->name, ((*yyvaluep).menu)->lineno);\n\tif (current_menu == ((*yyvaluep).menu))\n\t\tmenu_end_menu();\n}\n        break;\n\n      default:\n        break;\n    }\n  YY_IGNORE_MAYBE_UNINITIALIZED_END\n}\n\n\n/* Lookahead token kind.  */\nint yychar;\n\n/* The semantic value of the lookahead symbol.  */\nYYSTYPE yylval;\n/* Number of syntax errors so far.  */\nint yynerrs;\n\n\n\n\n/*----------.\n| yyparse.  |\n`----------*/\n\nint\nyyparse (void)\n{\n    yy_state_fast_t yystate = 0;\n    /* Number of tokens to shift before error messages enabled.  */\n    int yyerrstatus = 0;\n\n    /* Refer to the stacks through separate pointers, to allow yyoverflow\n       to reallocate them elsewhere.  */\n\n    /* Their size.  */\n    YYPTRDIFF_T yystacksize = YYINITDEPTH;\n\n    /* The state stack: array, bottom, top.  */\n    yy_state_t yyssa[YYINITDEPTH];\n    yy_state_t *yyss = yyssa;\n    yy_state_t *yyssp = yyss;\n\n    /* The semantic value stack: array, bottom, top.  */\n    YYSTYPE yyvsa[YYINITDEPTH];\n    YYSTYPE *yyvs = yyvsa;\n    YYSTYPE *yyvsp = yyvs;\n\n  int yyn;\n  /* The return value of yyparse.  */\n  int yyresult;\n  /* Lookahead symbol kind.  */\n  yysymbol_kind_t yytoken = YYSYMBOL_YYEMPTY;\n  /* The variables used to return semantic value and location from the\n     action routines.  */\n  YYSTYPE yyval;\n\n\n\n#define YYPOPSTACK(N)   (yyvsp -= (N), yyssp -= (N))\n\n  /* The number of symbols on the RHS of the reduced rule.\n     Keep to zero when no symbol should be popped.  */\n  int yylen = 0;\n\n  YYDPRINTF ((stderr, \"Starting parse\\n\"));\n\n  yychar = YYEMPTY; /* Cause a token to be read.  */\n  goto yysetstate;\n\n\n/*------------------------------------------------------------.\n| yynewstate -- push a new state, which is found in yystate.  |\n`------------------------------------------------------------*/\nyynewstate:\n  /* In all cases, when you get here, the value and location stacks\n     have just been pushed.  So pushing a state here evens the stacks.  */\n  yyssp++;\n\n\n/*--------------------------------------------------------------------.\n| yysetstate -- set current state (the top of the stack) to yystate.  |\n`--------------------------------------------------------------------*/\nyysetstate:\n  YYDPRINTF ((stderr, \"Entering state %d\\n\", yystate));\n  YY_ASSERT (0 <= yystate && yystate < YYNSTATES);\n  YY_IGNORE_USELESS_CAST_BEGIN\n  *yyssp = YY_CAST (yy_state_t, yystate);\n  YY_IGNORE_USELESS_CAST_END\n  YY_STACK_PRINT (yyss, yyssp);\n\n  if (yyss + yystacksize - 1 <= yyssp)\n#if !defined yyoverflow && !defined YYSTACK_RELOCATE\n    goto yyexhaustedlab;\n#else\n    {\n      /* Get the current used size of the three stacks, in elements.  */\n      YYPTRDIFF_T yysize = yyssp - yyss + 1;\n\n# if defined yyoverflow\n      {\n        /* Give user a chance to reallocate the stack.  Use copies of\n           these so that the &'s don't force the real ones into\n           memory.  */\n        yy_state_t *yyss1 = yyss;\n        YYSTYPE *yyvs1 = yyvs;\n\n        /* Each stack pointer address is followed by the size of the\n           data in use in that stack, in bytes.  This used to be a\n           conditional around just the two extra args, but that might\n           be undefined if yyoverflow is a macro.  */\n        yyoverflow (YY_(\"memory exhausted\"),\n                    &yyss1, yysize * YYSIZEOF (*yyssp),\n                    &yyvs1, yysize * YYSIZEOF (*yyvsp),\n                    &yystacksize);\n        yyss = yyss1;\n        yyvs = yyvs1;\n      }\n# else /* defined YYSTACK_RELOCATE */\n      /* Extend the stack our own way.  */\n      if (YYMAXDEPTH <= yystacksize)\n        goto yyexhaustedlab;\n      yystacksize *= 2;\n      if (YYMAXDEPTH < yystacksize)\n        yystacksize = YYMAXDEPTH;\n\n      {\n        yy_state_t *yyss1 = yyss;\n        union yyalloc *yyptr =\n          YY_CAST (union yyalloc *,\n                   YYSTACK_ALLOC (YY_CAST (YYSIZE_T, YYSTACK_BYTES (yystacksize))));\n        if (! yyptr)\n          goto yyexhaustedlab;\n        YYSTACK_RELOCATE (yyss_alloc, yyss);\n        YYSTACK_RELOCATE (yyvs_alloc, yyvs);\n#  undef YYSTACK_RELOCATE\n        if (yyss1 != yyssa)\n          YYSTACK_FREE (yyss1);\n      }\n# endif\n\n      yyssp = yyss + yysize - 1;\n      yyvsp = yyvs + yysize - 1;\n\n      YY_IGNORE_USELESS_CAST_BEGIN\n      YYDPRINTF ((stderr, \"Stack size increased to %ld\\n\",\n                  YY_CAST (long, yystacksize)));\n      YY_IGNORE_USELESS_CAST_END\n\n      if (yyss + yystacksize - 1 <= yyssp)\n        YYABORT;\n    }\n#endif /* !defined yyoverflow && !defined YYSTACK_RELOCATE */\n\n  if (yystate == YYFINAL)\n    YYACCEPT;\n\n  goto yybackup;\n\n\n/*-----------.\n| yybackup.  |\n`-----------*/\nyybackup:\n  /* Do appropriate processing given the current state.  Read a\n     lookahead token if we need one and don't already have one.  */\n\n  /* First try to decide what to do without reference to lookahead token.  */\n  yyn = yypact[yystate];\n  if (yypact_value_is_default (yyn))\n    goto yydefault;\n\n  /* Not known => get a lookahead token if don't already have one.  */\n\n  /* YYCHAR is either empty, or end-of-input, or a valid lookahead.  */\n  if (yychar == YYEMPTY)\n    {\n      YYDPRINTF ((stderr, \"Reading a token\\n\"));\n      yychar = yylex ();\n    }\n\n  if (yychar <= YYEOF)\n    {\n      yychar = YYEOF;\n      yytoken = YYSYMBOL_YYEOF;\n      YYDPRINTF ((stderr, \"Now at end of input.\\n\"));\n    }\n  else if (yychar == YYerror)\n    {\n      /* The scanner already issued an error message, process directly\n         to error recovery.  But do not keep the error token as\n         lookahead, it is too special and may lead us to an endless\n         loop in error recovery. */\n      yychar = YYUNDEF;\n      yytoken = YYSYMBOL_YYerror;\n      goto yyerrlab1;\n    }\n  else\n    {\n      yytoken = YYTRANSLATE (yychar);\n      YY_SYMBOL_PRINT (\"Next token is\", yytoken, &yylval, &yylloc);\n    }\n\n  /* If the proper action on seeing token YYTOKEN is to reduce or to\n     detect an error, take that action.  */\n  yyn += yytoken;\n  if (yyn < 0 || YYLAST < yyn || yycheck[yyn] != yytoken)\n    goto yydefault;\n  yyn = yytable[yyn];\n  if (yyn <= 0)\n    {\n      if (yytable_value_is_error (yyn))\n        goto yyerrlab;\n      yyn = -yyn;\n      goto yyreduce;\n    }\n\n  /* Count tokens shifted since error; after three, turn off error\n     status.  */\n  if (yyerrstatus)\n    yyerrstatus--;\n\n  /* Shift the lookahead token.  */\n  YY_SYMBOL_PRINT (\"Shifting\", yytoken, &yylval, &yylloc);\n  yystate = yyn;\n  YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN\n  *++yyvsp = yylval;\n  YY_IGNORE_MAYBE_UNINITIALIZED_END\n\n  /* Discard the shifted token.  */\n  yychar = YYEMPTY;\n  goto yynewstate;\n\n\n/*-----------------------------------------------------------.\n| yydefault -- do the default action for the current state.  |\n`-----------------------------------------------------------*/\nyydefault:\n  yyn = yydefact[yystate];\n  if (yyn == 0)\n    goto yyerrlab;\n  goto yyreduce;\n\n\n/*-----------------------------.\n| yyreduce -- do a reduction.  |\n`-----------------------------*/\nyyreduce:\n  /* yyn is the number of a rule to reduce with.  */\n  yylen = yyr2[yyn];\n\n  /* If YYLEN is nonzero, implement the default value of the action:\n     '$$ = $1'.\n\n     Otherwise, the following line sets YYVAL to garbage.\n     This behavior is undocumented and Bison\n     users should not rely upon it.  Assigning to YYVAL\n     unconditionally makes the parser a bit smaller, and it avoids a\n     GCC warning that YYVAL may be used uninitialized.  */\n  yyval = yyvsp[1-yylen];\n\n\n  YY_REDUCE_PRINT (yyn);\n  switch (yyn)\n    {\n  case 4: /* mainmenu_stmt: T_MAINMENU T_WORD_QUOTE T_EOL  */\n{\n\tmenu_add_prompt(P_MENU, (yyvsp[-1].string), NULL);\n}\n    break;\n\n  case 14: /* stmt_list: stmt_list T_WORD error T_EOL  */\n                                        { zconf_error(\"unknown statement \\\"%s\\\"\", (yyvsp[-2].string)); }\n    break;\n\n  case 15: /* stmt_list: stmt_list error T_EOL  */\n                                        { zconf_error(\"invalid statement\"); }\n    break;\n\n  case 20: /* stmt_list_in_choice: stmt_list_in_choice error T_EOL  */\n                                                { zconf_error(\"invalid statement\"); }\n    break;\n\n  case 21: /* config_entry_start: T_CONFIG nonconst_symbol T_EOL  */\n{\n\t(yyvsp[-1].symbol)->flags |= SYMBOL_OPTIONAL;\n\tmenu_add_entry((yyvsp[-1].symbol));\n\tprintd(DEBUG_PARSE, \"%s:%d:config %s\\n\", zconf_curname(), zconf_lineno(), (yyvsp[-1].symbol)->name);\n}\n    break;\n\n  case 22: /* config_stmt: config_entry_start config_option_list  */\n{\n\tprintd(DEBUG_PARSE, \"%s:%d:endconfig\\n\", zconf_curname(), zconf_lineno());\n}\n    break;\n\n  case 23: /* menuconfig_entry_start: T_MENUCONFIG nonconst_symbol T_EOL  */\n{\n\t(yyvsp[-1].symbol)->flags |= SYMBOL_OPTIONAL;\n\tmenu_add_entry((yyvsp[-1].symbol));\n\tprintd(DEBUG_PARSE, \"%s:%d:menuconfig %s\\n\", zconf_curname(), zconf_lineno(), (yyvsp[-1].symbol)->name);\n}\n    break;\n\n  case 24: /* menuconfig_stmt: menuconfig_entry_start config_option_list  */\n{\n\tif (current_entry->prompt)\n\t\tcurrent_entry->prompt->type = P_MENU;\n\telse\n\t\tzconfprint(\"warning: menuconfig statement without prompt\");\n\tprintd(DEBUG_PARSE, \"%s:%d:endconfig\\n\", zconf_curname(), zconf_lineno());\n}\n    break;\n\n  case 29: /* config_option: type prompt_stmt_opt T_EOL  */\n{\n\tmenu_set_type((yyvsp[-2].type));\n\tprintd(DEBUG_PARSE, \"%s:%d:type(%u)\\n\",\n\t\tzconf_curname(), zconf_lineno(),\n\t\t(yyvsp[-2].type));\n}\n    break;\n\n  case 30: /* config_option: T_PROMPT T_WORD_QUOTE if_expr T_EOL  */\n{\n\tmenu_add_prompt(P_PROMPT, (yyvsp[-2].string), (yyvsp[-1].expr));\n\tprintd(DEBUG_PARSE, \"%s:%d:prompt\\n\", zconf_curname(), zconf_lineno());\n}\n    break;\n\n  case 31: /* config_option: default expr if_expr T_EOL  */\n{\n\tmenu_add_expr(P_DEFAULT, (yyvsp[-2].expr), (yyvsp[-1].expr));\n\tif ((yyvsp[-3].type) != S_UNKNOWN)\n\t\tmenu_set_type((yyvsp[-3].type));\n\tprintd(DEBUG_PARSE, \"%s:%d:default(%u)\\n\",\n\t\tzconf_curname(), zconf_lineno(),\n\t\t(yyvsp[-3].type));\n}\n    break;\n\n  case 32: /* config_option: T_SELECT nonconst_symbol if_expr T_EOL  */\n{\n\tmenu_add_symbol(P_SELECT, (yyvsp[-2].symbol), (yyvsp[-1].expr));\n\tprintd(DEBUG_PARSE, \"%s:%d:select\\n\", zconf_curname(), zconf_lineno());\n}\n    break;\n\n  case 33: /* config_option: T_IMPLY nonconst_symbol if_expr T_EOL  */\n{\n\tmenu_add_symbol(P_IMPLY, (yyvsp[-2].symbol), (yyvsp[-1].expr));\n\tprintd(DEBUG_PARSE, \"%s:%d:imply\\n\", zconf_curname(), zconf_lineno());\n}\n    break;\n\n  case 34: /* config_option: T_RANGE symbol symbol if_expr T_EOL  */\n{\n\tmenu_add_expr(P_RANGE, expr_alloc_comp(E_RANGE,(yyvsp[-3].symbol), (yyvsp[-2].symbol)), (yyvsp[-1].expr));\n\tprintd(DEBUG_PARSE, \"%s:%d:range\\n\", zconf_curname(), zconf_lineno());\n}\n    break;\n\n  case 35: /* config_option: T_MODULES T_EOL  */\n{\n\tif (modules_sym)\n\t\tzconf_error(\"symbol '%s' redefines option 'modules' already defined by symbol '%s'\",\n\t\t\t    current_entry->sym->name, modules_sym->name);\n\tmodules_sym = current_entry->sym;\n}\n    break;\n\n  case 36: /* choice: T_CHOICE word_opt T_EOL  */\n{\n\tstruct symbol *sym = sym_lookup((yyvsp[-1].string), SYMBOL_CHOICE);\n\tsym->flags |= SYMBOL_NO_WRITE;\n\tmenu_add_entry(sym);\n\tmenu_add_expr(P_CHOICE, NULL, NULL);\n\tfree((yyvsp[-1].string));\n\tprintd(DEBUG_PARSE, \"%s:%d:choice\\n\", zconf_curname(), zconf_lineno());\n}\n    break;\n\n  case 37: /* choice_entry: choice choice_option_list  */\n{\n\t(yyval.menu) = menu_add_menu();\n}\n    break;\n\n  case 38: /* choice_end: end  */\n{\n\tif (zconf_endtoken((yyvsp[0].string), \"choice\")) {\n\t\tmenu_end_menu();\n\t\tprintd(DEBUG_PARSE, \"%s:%d:endchoice\\n\", zconf_curname(), zconf_lineno());\n\t}\n}\n    break;\n\n  case 44: /* choice_option: T_PROMPT T_WORD_QUOTE if_expr T_EOL  */\n{\n\tmenu_add_prompt(P_PROMPT, (yyvsp[-2].string), (yyvsp[-1].expr));\n\tprintd(DEBUG_PARSE, \"%s:%d:prompt\\n\", zconf_curname(), zconf_lineno());\n}\n    break;\n\n  case 45: /* choice_option: logic_type prompt_stmt_opt T_EOL  */\n{\n\tmenu_set_type((yyvsp[-2].type));\n\tprintd(DEBUG_PARSE, \"%s:%d:type(%u)\\n\",\n\t       zconf_curname(), zconf_lineno(), (yyvsp[-2].type));\n}\n    break;\n\n  case 46: /* choice_option: T_OPTIONAL T_EOL  */\n{\n\tcurrent_entry->sym->flags |= SYMBOL_OPTIONAL;\n\tprintd(DEBUG_PARSE, \"%s:%d:optional\\n\", zconf_curname(), zconf_lineno());\n}\n    break;\n\n  case 47: /* choice_option: T_RESET if_expr T_EOL  */\n{\n\tmenu_add_prop(P_RESET, NULL, (yyvsp[-1].expr));\n}\n    break;\n\n  case 48: /* choice_option: T_DEFAULT nonconst_symbol if_expr T_EOL  */\n{\n\tmenu_add_symbol(P_DEFAULT, (yyvsp[-2].symbol), (yyvsp[-1].expr));\n\tprintd(DEBUG_PARSE, \"%s:%d:default\\n\",\n\t       zconf_curname(), zconf_lineno());\n}\n    break;\n\n  case 50: /* type: T_INT  */\n                                { (yyval.type) = S_INT; }\n    break;\n\n  case 51: /* type: T_HEX  */\n                                { (yyval.type) = S_HEX; }\n    break;\n\n  case 52: /* type: T_STRING  */\n                                { (yyval.type) = S_STRING; }\n    break;\n\n  case 53: /* logic_type: T_BOOL  */\n                                { (yyval.type) = S_BOOLEAN; }\n    break;\n\n  case 54: /* logic_type: T_TRISTATE  */\n                                { (yyval.type) = S_TRISTATE; }\n    break;\n\n  case 55: /* default: T_DEFAULT  */\n                                { (yyval.type) = S_UNKNOWN; }\n    break;\n\n  case 56: /* default: T_DEF_BOOL  */\n                                { (yyval.type) = S_BOOLEAN; }\n    break;\n\n  case 57: /* default: T_DEF_TRISTATE  */\n                                { (yyval.type) = S_TRISTATE; }\n    break;\n\n  case 58: /* if_entry: T_IF expr T_EOL  */\n{\n\tprintd(DEBUG_PARSE, \"%s:%d:if\\n\", zconf_curname(), zconf_lineno());\n\tmenu_add_entry(NULL);\n\tmenu_add_dep((yyvsp[-1].expr));\n\t(yyval.menu) = menu_add_menu();\n}\n    break;\n\n  case 59: /* if_end: end  */\n{\n\tif (zconf_endtoken((yyvsp[0].string), \"if\")) {\n\t\tmenu_end_menu();\n\t\tprintd(DEBUG_PARSE, \"%s:%d:endif\\n\", zconf_curname(), zconf_lineno());\n\t}\n}\n    break;\n\n  case 62: /* menu: T_MENU T_WORD_QUOTE T_EOL  */\n{\n\tmenu_add_entry(NULL);\n\tmenu_add_prompt(P_MENU, (yyvsp[-1].string), NULL);\n\tprintd(DEBUG_PARSE, \"%s:%d:menu\\n\", zconf_curname(), zconf_lineno());\n}\n    break;\n\n  case 63: /* menu_entry: menu menu_option_list  */\n{\n\t(yyval.menu) = menu_add_menu();\n}\n    break;\n\n  case 64: /* menu_end: end  */\n{\n\tif (zconf_endtoken((yyvsp[0].string), \"menu\")) {\n\t\tmenu_end_menu();\n\t\tprintd(DEBUG_PARSE, \"%s:%d:endmenu\\n\", zconf_curname(), zconf_lineno());\n\t}\n}\n    break;\n\n  case 69: /* source_stmt: T_SOURCE T_WORD_QUOTE T_EOL  */\n{\n\tprintd(DEBUG_PARSE, \"%s:%d:source %s\\n\", zconf_curname(), zconf_lineno(), (yyvsp[-1].string));\n\tzconf_nextfile((yyvsp[-1].string));\n\tfree((yyvsp[-1].string));\n}\n    break;\n\n  case 70: /* comment: T_COMMENT T_WORD_QUOTE T_EOL  */\n{\n\tmenu_add_entry(NULL);\n\tmenu_add_prompt(P_COMMENT, (yyvsp[-1].string), NULL);\n\tprintd(DEBUG_PARSE, \"%s:%d:comment\\n\", zconf_curname(), zconf_lineno());\n}\n    break;\n\n  case 74: /* help_start: T_HELP T_EOL  */\n{\n\tprintd(DEBUG_PARSE, \"%s:%d:help\\n\", zconf_curname(), zconf_lineno());\n\tzconf_starthelp();\n}\n    break;\n\n  case 75: /* help: help_start T_HELPTEXT  */\n{\n\t/* Is the help text empty or all whitespace? */\n\tif ((yyvsp[0].string)[strspn((yyvsp[0].string), \" \\f\\n\\r\\t\\v\")] == '\\0')\n\t\tzconfprint(\"warning: '%s' defined with blank help text\",\n\t\t\t   current_entry->sym->name ?: \"<choice>\");\n\n\tcurrent_entry->help = (yyvsp[0].string);\n}\n    break;\n\n  case 76: /* depends: T_DEPENDS T_ON expr T_EOL  */\n{\n\tmenu_add_dep((yyvsp[-1].expr));\n\tprintd(DEBUG_PARSE, \"%s:%d:depends on\\n\", zconf_curname(), zconf_lineno());\n}\n    break;\n\n  case 77: /* visible: T_VISIBLE if_expr T_EOL  */\n{\n\tmenu_add_visibility((yyvsp[-1].expr));\n}\n    break;\n\n  case 79: /* prompt_stmt_opt: T_WORD_QUOTE if_expr  */\n{\n\tmenu_add_prompt(P_PROMPT, (yyvsp[-1].string), (yyvsp[0].expr));\n}\n    break;\n\n  case 80: /* end: T_ENDMENU T_EOL  */\n                                { (yyval.string) = \"menu\"; }\n    break;\n\n  case 81: /* end: T_ENDCHOICE T_EOL  */\n                                { (yyval.string) = \"choice\"; }\n    break;\n\n  case 82: /* end: T_ENDIF T_EOL  */\n                                { (yyval.string) = \"if\"; }\n    break;\n\n  case 83: /* if_expr: %empty  */\n                                        { (yyval.expr) = NULL; }\n    break;\n\n  case 84: /* if_expr: T_IF expr  */\n                                        { (yyval.expr) = (yyvsp[0].expr); }\n    break;\n\n  case 85: /* expr: symbol  */\n                                                { (yyval.expr) = expr_alloc_symbol((yyvsp[0].symbol)); }\n    break;\n\n  case 86: /* expr: symbol T_LESS symbol  */\n                                                { (yyval.expr) = expr_alloc_comp(E_LTH, (yyvsp[-2].symbol), (yyvsp[0].symbol)); }\n    break;\n\n  case 87: /* expr: symbol T_LESS_EQUAL symbol  */\n                                                { (yyval.expr) = expr_alloc_comp(E_LEQ, (yyvsp[-2].symbol), (yyvsp[0].symbol)); }\n    break;\n\n  case 88: /* expr: symbol T_GREATER symbol  */\n                                                { (yyval.expr) = expr_alloc_comp(E_GTH, (yyvsp[-2].symbol), (yyvsp[0].symbol)); }\n    break;\n\n  case 89: /* expr: symbol T_GREATER_EQUAL symbol  */\n                                                { (yyval.expr) = expr_alloc_comp(E_GEQ, (yyvsp[-2].symbol), (yyvsp[0].symbol)); }\n    break;\n\n  case 90: /* expr: symbol T_EQUAL symbol  */\n                                                { (yyval.expr) = expr_alloc_comp(E_EQUAL, (yyvsp[-2].symbol), (yyvsp[0].symbol)); }\n    break;\n\n  case 91: /* expr: symbol T_UNEQUAL symbol  */\n                                                { (yyval.expr) = expr_alloc_comp(E_UNEQUAL, (yyvsp[-2].symbol), (yyvsp[0].symbol)); }\n    break;\n\n  case 92: /* expr: T_OPEN_PAREN expr T_CLOSE_PAREN  */\n                                                { (yyval.expr) = (yyvsp[-1].expr); }\n    break;\n\n  case 93: /* expr: T_NOT expr  */\n                                                { (yyval.expr) = expr_alloc_one(E_NOT, (yyvsp[0].expr)); }\n    break;\n\n  case 94: /* expr: expr T_OR expr  */\n                                                { (yyval.expr) = expr_alloc_two(E_OR, (yyvsp[-2].expr), (yyvsp[0].expr)); }\n    break;\n\n  case 95: /* expr: expr T_AND expr  */\n                                                { (yyval.expr) = expr_alloc_two(E_AND, (yyvsp[-2].expr), (yyvsp[0].expr)); }\n    break;\n\n  case 96: /* nonconst_symbol: T_WORD  */\n                        { (yyval.symbol) = sym_lookup((yyvsp[0].string), 0); free((yyvsp[0].string)); }\n    break;\n\n  case 98: /* symbol: T_WORD_QUOTE  */\n                        { (yyval.symbol) = sym_lookup((yyvsp[0].string), SYMBOL_CONST); free((yyvsp[0].string)); }\n    break;\n\n  case 99: /* word_opt: %empty  */\n                                        { (yyval.string) = NULL; }\n    break;\n\n  case 101: /* assignment_stmt: T_WORD assign_op assign_val T_EOL  */\n                                                        { variable_add((yyvsp[-3].string), (yyvsp[-1].string), (yyvsp[-2].flavor)); free((yyvsp[-3].string)); free((yyvsp[-1].string)); }\n    break;\n\n  case 102: /* assign_op: T_EQUAL  */\n                        { (yyval.flavor) = VAR_RECURSIVE; }\n    break;\n\n  case 103: /* assign_op: T_COLON_EQUAL  */\n                        { (yyval.flavor) = VAR_SIMPLE; }\n    break;\n\n  case 104: /* assign_op: T_PLUS_EQUAL  */\n                        { (yyval.flavor) = VAR_APPEND; }\n    break;\n\n  case 105: /* assign_val: %empty  */\n                                { (yyval.string) = xstrdup(\"\"); }\n    break;\n\n\n\n      default: break;\n    }\n  /* User semantic actions sometimes alter yychar, and that requires\n     that yytoken be updated with the new translation.  We take the\n     approach of translating immediately before every use of yytoken.\n     One alternative is translating here after every semantic action,\n     but that translation would be missed if the semantic action invokes\n     YYABORT, YYACCEPT, or YYERROR immediately after altering yychar or\n     if it invokes YYBACKUP.  In the case of YYABORT or YYACCEPT, an\n     incorrect destructor might then be invoked immediately.  In the\n     case of YYERROR or YYBACKUP, subsequent parser actions might lead\n     to an incorrect destructor call or verbose syntax error message\n     before the lookahead is translated.  */\n  YY_SYMBOL_PRINT (\"-> $$ =\", YY_CAST (yysymbol_kind_t, yyr1[yyn]), &yyval, &yyloc);\n\n  YYPOPSTACK (yylen);\n  yylen = 0;\n\n  *++yyvsp = yyval;\n\n  /* Now 'shift' the result of the reduction.  Determine what state\n     that goes to, based on the state we popped back to and the rule\n     number reduced by.  */\n  {\n    const int yylhs = yyr1[yyn] - YYNTOKENS;\n    const int yyi = yypgoto[yylhs] + *yyssp;\n    yystate = (0 <= yyi && yyi <= YYLAST && yycheck[yyi] == *yyssp\n               ? yytable[yyi]\n               : yydefgoto[yylhs]);\n  }\n\n  goto yynewstate;\n\n\n/*--------------------------------------.\n| yyerrlab -- here on detecting error.  |\n`--------------------------------------*/\nyyerrlab:\n  /* Make sure we have latest lookahead translation.  See comments at\n     user semantic actions for why this is necessary.  */\n  yytoken = yychar == YYEMPTY ? YYSYMBOL_YYEMPTY : YYTRANSLATE (yychar);\n  /* If not already recovering from an error, report this error.  */\n  if (!yyerrstatus)\n    {\n      ++yynerrs;\n      yyerror (YY_(\"syntax error\"));\n    }\n\n  if (yyerrstatus == 3)\n    {\n      /* If just tried and failed to reuse lookahead token after an\n         error, discard it.  */\n\n      if (yychar <= YYEOF)\n        {\n          /* Return failure if at end of input.  */\n          if (yychar == YYEOF)\n            YYABORT;\n        }\n      else\n        {\n          yydestruct (\"Error: discarding\",\n                      yytoken, &yylval);\n          yychar = YYEMPTY;\n        }\n    }\n\n  /* Else will try to reuse lookahead token after shifting the error\n     token.  */\n  goto yyerrlab1;\n\n\n/*---------------------------------------------------.\n| yyerrorlab -- error raised explicitly by YYERROR.  |\n`---------------------------------------------------*/\nyyerrorlab:\n  /* Pacify compilers when the user code never invokes YYERROR and the\n     label yyerrorlab therefore never appears in user code.  */\n  if (0)\n    YYERROR;\n\n  /* Do not reclaim the symbols of the rule whose action triggered\n     this YYERROR.  */\n  YYPOPSTACK (yylen);\n  yylen = 0;\n  YY_STACK_PRINT (yyss, yyssp);\n  yystate = *yyssp;\n  goto yyerrlab1;\n\n\n/*-------------------------------------------------------------.\n| yyerrlab1 -- common code for both syntax error and YYERROR.  |\n`-------------------------------------------------------------*/\nyyerrlab1:\n  yyerrstatus = 3;      /* Each real token shifted decrements this.  */\n\n  /* Pop stack until we find a state that shifts the error token.  */\n  for (;;)\n    {\n      yyn = yypact[yystate];\n      if (!yypact_value_is_default (yyn))\n        {\n          yyn += YYSYMBOL_YYerror;\n          if (0 <= yyn && yyn <= YYLAST && yycheck[yyn] == YYSYMBOL_YYerror)\n            {\n              yyn = yytable[yyn];\n              if (0 < yyn)\n                break;\n            }\n        }\n\n      /* Pop the current state because it cannot handle the error token.  */\n      if (yyssp == yyss)\n        YYABORT;\n\n\n      yydestruct (\"Error: popping\",\n                  YY_ACCESSING_SYMBOL (yystate), yyvsp);\n      YYPOPSTACK (1);\n      yystate = *yyssp;\n      YY_STACK_PRINT (yyss, yyssp);\n    }\n\n  YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN\n  *++yyvsp = yylval;\n  YY_IGNORE_MAYBE_UNINITIALIZED_END\n\n\n  /* Shift the error token.  */\n  YY_SYMBOL_PRINT (\"Shifting\", YY_ACCESSING_SYMBOL (yyn), yyvsp, yylsp);\n\n  yystate = yyn;\n  goto yynewstate;\n\n\n/*-------------------------------------.\n| yyacceptlab -- YYACCEPT comes here.  |\n`-------------------------------------*/\nyyacceptlab:\n  yyresult = 0;\n  goto yyreturn;\n\n\n/*-----------------------------------.\n| yyabortlab -- YYABORT comes here.  |\n`-----------------------------------*/\nyyabortlab:\n  yyresult = 1;\n  goto yyreturn;\n\n\n#if !defined yyoverflow\n/*-------------------------------------------------.\n| yyexhaustedlab -- memory exhaustion comes here.  |\n`-------------------------------------------------*/\nyyexhaustedlab:\n  yyerror (YY_(\"memory exhausted\"));\n  yyresult = 2;\n  goto yyreturn;\n#endif\n\n\n/*-------------------------------------------------------.\n| yyreturn -- parsing is finished, clean up and return.  |\n`-------------------------------------------------------*/\nyyreturn:\n  if (yychar != YYEMPTY)\n    {\n      /* Make sure we have latest lookahead translation.  See comments at\n         user semantic actions for why this is necessary.  */\n      yytoken = YYTRANSLATE (yychar);\n      yydestruct (\"Cleanup: discarding lookahead\",\n                  yytoken, &yylval);\n    }\n  /* Do not reclaim the symbols of the rule whose action triggered\n     this YYABORT or YYACCEPT.  */\n  YYPOPSTACK (yylen);\n  YY_STACK_PRINT (yyss, yyssp);\n  while (yyssp != yyss)\n    {\n      yydestruct (\"Cleanup: popping\",\n                  YY_ACCESSING_SYMBOL (+*yyssp), yyvsp);\n      YYPOPSTACK (1);\n    }\n#ifndef yyoverflow\n  if (yyss != yyssa)\n    YYSTACK_FREE (yyss);\n#endif\n\n  return yyresult;\n}\n\n\n\nvoid conf_parse(const char *name)\n{\n\tstruct symbol *sym;\n\tint i;\n\n\tzconf_initscan(name);\n\n\t_menu_init();\n\n#if YYDEBUG\n\tif (getenv(\"ZCONF_DEBUG\"))\n\t\tyydebug = 1;\n#endif\n\tyyparse();\n\n\t/* Variables are expanded in the parse phase. We can free them here. */\n\tvariable_all_del();\n\n\tif (yynerrs)\n\t\texit(1);\n\tif (!modules_sym)\n\t\tmodules_sym = sym_find( \"n\" );\n\n\tif (!menu_has_prompt(&rootmenu)) {\n\t\tcurrent_entry = &rootmenu;\n\t\tmenu_add_prompt(P_MENU, \"Main menu\", NULL);\n\t}\n\n\tmenu_finalize(&rootmenu);\n\tfor_all_symbols(i, sym) {\n\t\tif (sym_check_deps(sym))\n\t\t\tyynerrs++;\n\t}\n\tif (yynerrs)\n\t\texit(1);\n\tconf_set_changed(true);\n}\n\nstatic bool zconf_endtoken(const char *tokenname,\n\t\t\t   const char *expected_tokenname)\n{\n\tif (strcmp(tokenname, expected_tokenname)) {\n\t\tzconf_error(\"unexpected '%s' within %s block\",\n\t\t\t    tokenname, expected_tokenname);\n\t\tyynerrs++;\n\t\treturn false;\n\t}\n\tif (current_menu->file != current_file) {\n\t\tzconf_error(\"'%s' in different file than '%s'\",\n\t\t\t    tokenname, expected_tokenname);\n\t\tfprintf(stderr, \"%s:%d: location of the '%s'\\n\",\n\t\t\tcurrent_menu->file->name, current_menu->lineno,\n\t\t\texpected_tokenname);\n\t\tyynerrs++;\n\t\treturn false;\n\t}\n\treturn true;\n}\n\nstatic void zconfprint(const char *err, ...)\n{\n\tva_list ap;\n\n\tfprintf(stderr, \"%s:%d: \", zconf_curname(), zconf_lineno());\n\tva_start(ap, err);\n\tvfprintf(stderr, err, ap);\n\tva_end(ap);\n\tfprintf(stderr, \"\\n\");\n}\n\nstatic void zconf_error(const char *err, ...)\n{\n\tva_list ap;\n\n\tyynerrs++;\n\tfprintf(stderr, \"%s:%d: \", zconf_curname(), zconf_lineno());\n\tva_start(ap, err);\n\tvfprintf(stderr, err, ap);\n\tva_end(ap);\n\tfprintf(stderr, \"\\n\");\n}\n\nstatic void yyerror(const char *err)\n{\n\tfprintf(stderr, \"%s:%d: %s\\n\", zconf_curname(), zconf_lineno() + 1, err);\n}\n\nstatic void print_quoted_string(FILE *out, const char *str)\n{\n\tconst char *p;\n\tint len;\n\n\tputc('\"', out);\n\twhile ((p = strchr(str, '\"'))) {\n\t\tlen = p - str;\n\t\tif (len)\n\t\t\tfprintf(out, \"%.*s\", len, str);\n\t\tfputs(\"\\\\\\\"\", out);\n\t\tstr = p + 1;\n\t}\n\tfputs(str, out);\n\tputc('\"', out);\n}\n\nstatic void print_symbol(FILE *out, struct menu *menu)\n{\n\tstruct symbol *sym = menu->sym;\n\tstruct property *prop;\n\n\tif (sym_is_choice(sym))\n\t\tfprintf(out, \"\\nchoice\\n\");\n\telse\n\t\tfprintf(out, \"\\nconfig %s\\n\", sym->name);\n\tswitch (sym->type) {\n\tcase S_BOOLEAN:\n\t\tfputs(\"  bool\\n\", out);\n\t\tbreak;\n\tcase S_TRISTATE:\n\t\tfputs(\"  tristate\\n\", out);\n\t\tbreak;\n\tcase S_STRING:\n\t\tfputs(\"  string\\n\", out);\n\t\tbreak;\n\tcase S_INT:\n\t\tfputs(\"  integer\\n\", out);\n\t\tbreak;\n\tcase S_HEX:\n\t\tfputs(\"  hex\\n\", out);\n\t\tbreak;\n\tdefault:\n\t\tfputs(\"  ???\\n\", out);\n\t\tbreak;\n\t}\n\tfor (prop = sym->prop; prop; prop = prop->next) {\n\t\tif (prop->menu != menu)\n\t\t\tcontinue;\n\t\tswitch (prop->type) {\n\t\tcase P_PROMPT:\n\t\t\tfputs(\"  prompt \", out);\n\t\t\tprint_quoted_string(out, prop->text);\n\t\t\tif (!expr_is_yes(prop->visible.expr)) {\n\t\t\t\tfputs(\" if \", out);\n\t\t\t\texpr_fprint(prop->visible.expr, out);\n\t\t\t}\n\t\t\tfputc('\\n', out);\n\t\t\tbreak;\n\t\tcase P_DEFAULT:\n\t\t\tfputs( \"  default \", out);\n\t\t\texpr_fprint(prop->expr, out);\n\t\t\tif (!expr_is_yes(prop->visible.expr)) {\n\t\t\t\tfputs(\" if \", out);\n\t\t\t\texpr_fprint(prop->visible.expr, out);\n\t\t\t}\n\t\t\tfputc('\\n', out);\n\t\t\tbreak;\n\t\tcase P_CHOICE:\n\t\t\tfputs(\"  #choice value\\n\", out);\n\t\t\tbreak;\n\t\tcase P_SELECT:\n\t\t\tfputs( \"  select \", out);\n\t\t\texpr_fprint(prop->expr, out);\n\t\t\tfputc('\\n', out);\n\t\t\tbreak;\n\t\tcase P_IMPLY:\n\t\t\tfputs( \"  imply \", out);\n\t\t\texpr_fprint(prop->expr, out);\n\t\t\tfputc('\\n', out);\n\t\t\tbreak;\n\t\tcase P_RANGE:\n\t\t\tfputs( \"  range \", out);\n\t\t\texpr_fprint(prop->expr, out);\n\t\t\tfputc('\\n', out);\n\t\t\tbreak;\n\t\tcase P_MENU:\n\t\t\tfputs( \"  menu \", out);\n\t\t\tprint_quoted_string(out, prop->text);\n\t\t\tfputc('\\n', out);\n\t\t\tbreak;\n\t\tcase P_SYMBOL:\n\t\t\tfputs( \"  symbol \", out);\n\t\t\tfprintf(out, \"%s\\n\", prop->menu->sym->name);\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tfprintf(out, \"  unknown prop %d!\\n\", prop->type);\n\t\t\tbreak;\n\t\t}\n\t}\n\tif (menu->help) {\n\t\tint len = strlen(menu->help);\n\t\twhile (menu->help[--len] == '\\n')\n\t\t\tmenu->help[len] = 0;\n\t\tfprintf(out, \"  help\\n%s\\n\", menu->help);\n\t}\n}\n\nvoid zconfdump(FILE *out)\n{\n\tstruct property *prop;\n\tstruct symbol *sym;\n\tstruct menu *menu;\n\n\tmenu = rootmenu.list;\n\twhile (menu) {\n\t\tif ((sym = menu->sym))\n\t\t\tprint_symbol(out, menu);\n\t\telse if ((prop = menu->prompt)) {\n\t\t\tswitch (prop->type) {\n\t\t\tcase P_COMMENT:\n\t\t\t\tfputs(\"\\ncomment \", out);\n\t\t\t\tprint_quoted_string(out, prop->text);\n\t\t\t\tfputs(\"\\n\", out);\n\t\t\t\tbreak;\n\t\t\tcase P_MENU:\n\t\t\t\tfputs(\"\\nmenu \", out);\n\t\t\t\tprint_quoted_string(out, prop->text);\n\t\t\t\tfputs(\"\\n\", out);\n\t\t\t\tbreak;\n\t\t\tdefault:\n\t\t\t\t;\n\t\t\t}\n\t\t\tif (!expr_is_yes(prop->visible.expr)) {\n\t\t\t\tfputs(\"  depends \", out);\n\t\t\t\texpr_fprint(prop->visible.expr, out);\n\t\t\t\tfputc('\\n', out);\n\t\t\t}\n\t\t}\n\n\t\tif (menu->list)\n\t\t\tmenu = menu->list;\n\t\telse if (menu->next)\n\t\t\tmenu = menu->next;\n\t\telse while ((menu = menu->parent)) {\n\t\t\tif (menu->prompt && menu->prompt->type == P_MENU)\n\t\t\t\tfputs(\"\\nendmenu\\n\", out);\n\t\t\tif (menu->next) {\n\t\t\t\tmenu = menu->next;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t}\n}\n"
  },
  {
    "path": "scripts/config/parser.tab.h",
    "content": "/* A Bison parser, made by GNU Bison 3.7.6.  */\n\n/* Bison interface for Yacc-like parsers in C\n\n   Copyright (C) 1984, 1989-1990, 2000-2015, 2018-2021 Free Software Foundation,\n   Inc.\n\n   This program is free software: you can redistribute it and/or modify\n   it under the terms of the GNU General Public License as published by\n   the Free Software Foundation, either version 3 of the License, or\n   (at your option) any later version.\n\n   This program is distributed in the hope that it will be useful,\n   but WITHOUT ANY WARRANTY; without even the implied warranty of\n   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n   GNU General Public License for more details.\n\n   You should have received a copy of the GNU General Public License\n   along with this program.  If not, see <https://www.gnu.org/licenses/>.  */\n\n/* As a special exception, you may create a larger work that contains\n   part or all of the Bison parser skeleton and distribute that work\n   under terms of your choice, so long as that work isn't itself a\n   parser generator using the skeleton or a modified version thereof\n   as a parser skeleton.  Alternatively, if you modify or redistribute\n   the parser skeleton itself, you may (at your option) remove this\n   special exception, which will cause the skeleton and the resulting\n   Bison output files to be licensed under the GNU General Public\n   License without this special exception.\n\n   This special exception was added by the Free Software Foundation in\n   version 2.2 of Bison.  */\n\n/* DO NOT RELY ON FEATURES THAT ARE NOT DOCUMENTED in the manual,\n   especially those whose name start with YY_ or yy_.  They are\n   private implementation details that can be changed or removed.  */\n\n#ifndef YY_YY_PARSER_TAB_H_INCLUDED\n# define YY_YY_PARSER_TAB_H_INCLUDED\n/* Debug traces.  */\n#ifndef YYDEBUG\n# define YYDEBUG 0\n#endif\n#if YYDEBUG\nextern int yydebug;\n#endif\n\n/* Token kinds.  */\n#ifndef YYTOKENTYPE\n# define YYTOKENTYPE\n  enum yytokentype\n  {\n    YYEMPTY = -2,\n    YYEOF = 0,                     /* \"end of file\"  */\n    YYerror = 256,                 /* error  */\n    YYUNDEF = 257,                 /* \"invalid token\"  */\n    T_HELPTEXT = 258,              /* T_HELPTEXT  */\n    T_WORD = 259,                  /* T_WORD  */\n    T_WORD_QUOTE = 260,            /* T_WORD_QUOTE  */\n    T_BOOL = 261,                  /* T_BOOL  */\n    T_CHOICE = 262,                /* T_CHOICE  */\n    T_CLOSE_PAREN = 263,           /* T_CLOSE_PAREN  */\n    T_COLON_EQUAL = 264,           /* T_COLON_EQUAL  */\n    T_COMMENT = 265,               /* T_COMMENT  */\n    T_CONFIG = 266,                /* T_CONFIG  */\n    T_DEFAULT = 267,               /* T_DEFAULT  */\n    T_DEF_BOOL = 268,              /* T_DEF_BOOL  */\n    T_DEF_TRISTATE = 269,          /* T_DEF_TRISTATE  */\n    T_DEPENDS = 270,               /* T_DEPENDS  */\n    T_ENDCHOICE = 271,             /* T_ENDCHOICE  */\n    T_ENDIF = 272,                 /* T_ENDIF  */\n    T_ENDMENU = 273,               /* T_ENDMENU  */\n    T_HELP = 274,                  /* T_HELP  */\n    T_HEX = 275,                   /* T_HEX  */\n    T_IF = 276,                    /* T_IF  */\n    T_IMPLY = 277,                 /* T_IMPLY  */\n    T_INT = 278,                   /* T_INT  */\n    T_MAINMENU = 279,              /* T_MAINMENU  */\n    T_MENU = 280,                  /* T_MENU  */\n    T_MENUCONFIG = 281,            /* T_MENUCONFIG  */\n    T_MODULES = 282,               /* T_MODULES  */\n    T_ON = 283,                    /* T_ON  */\n    T_OPEN_PAREN = 284,            /* T_OPEN_PAREN  */\n    T_OPTIONAL = 285,              /* T_OPTIONAL  */\n    T_PLUS_EQUAL = 286,            /* T_PLUS_EQUAL  */\n    T_PROMPT = 287,                /* T_PROMPT  */\n    T_RANGE = 288,                 /* T_RANGE  */\n    T_RESET = 289,                 /* T_RESET  */\n    T_SELECT = 290,                /* T_SELECT  */\n    T_SOURCE = 291,                /* T_SOURCE  */\n    T_STRING = 292,                /* T_STRING  */\n    T_TRISTATE = 293,              /* T_TRISTATE  */\n    T_VISIBLE = 294,               /* T_VISIBLE  */\n    T_EOL = 295,                   /* T_EOL  */\n    T_ASSIGN_VAL = 296,            /* T_ASSIGN_VAL  */\n    T_OR = 297,                    /* T_OR  */\n    T_AND = 298,                   /* T_AND  */\n    T_EQUAL = 299,                 /* T_EQUAL  */\n    T_UNEQUAL = 300,               /* T_UNEQUAL  */\n    T_LESS = 301,                  /* T_LESS  */\n    T_LESS_EQUAL = 302,            /* T_LESS_EQUAL  */\n    T_GREATER = 303,               /* T_GREATER  */\n    T_GREATER_EQUAL = 304,         /* T_GREATER_EQUAL  */\n    T_NOT = 305                    /* T_NOT  */\n  };\n  typedef enum yytokentype yytoken_kind_t;\n#endif\n\n/* Value type.  */\n#if ! defined YYSTYPE && ! defined YYSTYPE_IS_DECLARED\nunion YYSTYPE\n{\n\n\tchar *string;\n\tstruct symbol *symbol;\n\tstruct expr *expr;\n\tstruct menu *menu;\n\tenum symbol_type type;\n\tenum variable_flavor flavor;\n\n\n};\ntypedef union YYSTYPE YYSTYPE;\n# define YYSTYPE_IS_TRIVIAL 1\n# define YYSTYPE_IS_DECLARED 1\n#endif\n\n\nextern YYSTYPE yylval;\n\nint yyparse (void);\n\n#endif /* !YY_YY_PARSER_TAB_H_INCLUDED  */\n"
  },
  {
    "path": "scripts/config/parser.y",
    "content": "/* SPDX-License-Identifier: GPL-2.0-only */\n/*\n * Copyright (C) 2002 Roman Zippel <zippel@linux-m68k.org>\n */\n%{\n\n#include <ctype.h>\n#include <stdarg.h>\n#include <stdio.h>\n#include <stdlib.h>\n#include <string.h>\n#include <stdbool.h>\n\n#include \"lkc.h\"\n#include \"internal.h\"\n\n#define printd(mask, fmt...) if (cdebug & (mask)) printf(fmt)\n\n#define PRINTD\t\t0x0001\n#define DEBUG_PARSE\t0x0002\n\nint cdebug = PRINTD;\n\nstatic void yyerror(const char *err);\nstatic void zconfprint(const char *err, ...);\nstatic void zconf_error(const char *err, ...);\nstatic bool zconf_endtoken(const char *tokenname,\n\t\t\t   const char *expected_tokenname);\n\nstruct symbol *symbol_hash[SYMBOL_HASHSIZE];\n\nstruct menu *current_menu, *current_entry;\n\n%}\n\n%union\n{\n\tchar *string;\n\tstruct symbol *symbol;\n\tstruct expr *expr;\n\tstruct menu *menu;\n\tenum symbol_type type;\n\tenum variable_flavor flavor;\n}\n\n%token <string> T_HELPTEXT\n%token <string> T_WORD\n%token <string> T_WORD_QUOTE\n%token T_BOOL\n%token T_CHOICE\n%token T_CLOSE_PAREN\n%token T_COLON_EQUAL\n%token T_COMMENT\n%token T_CONFIG\n%token T_DEFAULT\n%token T_DEF_BOOL\n%token T_DEF_TRISTATE\n%token T_DEPENDS\n%token T_ENDCHOICE\n%token T_ENDIF\n%token T_ENDMENU\n%token T_HELP\n%token T_HEX\n%token T_IF\n%token T_IMPLY\n%token T_INT\n%token T_MAINMENU\n%token T_MENU\n%token T_MENUCONFIG\n%token T_MODULES\n%token T_ON\n%token T_OPEN_PAREN\n%token T_OPTIONAL\n%token T_PLUS_EQUAL\n%token T_PROMPT\n%token T_RANGE\n%token T_RESET\n%token T_SELECT\n%token T_SOURCE\n%token T_STRING\n%token T_TRISTATE\n%token T_VISIBLE\n%token T_EOL\n%token <string> T_ASSIGN_VAL\n\n%left T_OR\n%left T_AND\n%left T_EQUAL T_UNEQUAL\n%left T_LESS T_LESS_EQUAL T_GREATER T_GREATER_EQUAL\n%nonassoc T_NOT\n\n%type <symbol> nonconst_symbol\n%type <symbol> symbol\n%type <type> type logic_type default\n%type <expr> expr\n%type <expr> if_expr\n%type <string> end\n%type <menu> if_entry menu_entry choice_entry\n%type <string> word_opt assign_val\n%type <flavor> assign_op\n\n%destructor {\n\tfprintf(stderr, \"%s:%d: missing end statement for this entry\\n\",\n\t\t$$->file->name, $$->lineno);\n\tif (current_menu == $$)\n\t\tmenu_end_menu();\n} if_entry menu_entry choice_entry\n\n%%\ninput: mainmenu_stmt stmt_list | stmt_list;\n\n/* mainmenu entry */\n\nmainmenu_stmt: T_MAINMENU T_WORD_QUOTE T_EOL\n{\n\tmenu_add_prompt(P_MENU, $2, NULL);\n};\n\nstmt_list:\n\t  /* empty */\n\t| stmt_list assignment_stmt\n\t| stmt_list choice_stmt\n\t| stmt_list comment_stmt\n\t| stmt_list config_stmt\n\t| stmt_list if_stmt\n\t| stmt_list menu_stmt\n\t| stmt_list menuconfig_stmt\n\t| stmt_list source_stmt\n\t| stmt_list T_WORD error T_EOL\t{ zconf_error(\"unknown statement \\\"%s\\\"\", $2); }\n\t| stmt_list error T_EOL\t\t{ zconf_error(\"invalid statement\"); }\n;\n\nstmt_list_in_choice:\n\t  /* empty */\n\t| stmt_list_in_choice comment_stmt\n\t| stmt_list_in_choice config_stmt\n\t| stmt_list_in_choice if_stmt_in_choice\n\t| stmt_list_in_choice error T_EOL\t{ zconf_error(\"invalid statement\"); }\n;\n\n/* config/menuconfig entry */\n\nconfig_entry_start: T_CONFIG nonconst_symbol T_EOL\n{\n\t$2->flags |= SYMBOL_OPTIONAL;\n\tmenu_add_entry($2);\n\tprintd(DEBUG_PARSE, \"%s:%d:config %s\\n\", zconf_curname(), zconf_lineno(), $2->name);\n};\n\nconfig_stmt: config_entry_start config_option_list\n{\n\tprintd(DEBUG_PARSE, \"%s:%d:endconfig\\n\", zconf_curname(), zconf_lineno());\n};\n\nmenuconfig_entry_start: T_MENUCONFIG nonconst_symbol T_EOL\n{\n\t$2->flags |= SYMBOL_OPTIONAL;\n\tmenu_add_entry($2);\n\tprintd(DEBUG_PARSE, \"%s:%d:menuconfig %s\\n\", zconf_curname(), zconf_lineno(), $2->name);\n};\n\nmenuconfig_stmt: menuconfig_entry_start config_option_list\n{\n\tif (current_entry->prompt)\n\t\tcurrent_entry->prompt->type = P_MENU;\n\telse\n\t\tzconfprint(\"warning: menuconfig statement without prompt\");\n\tprintd(DEBUG_PARSE, \"%s:%d:endconfig\\n\", zconf_curname(), zconf_lineno());\n};\n\nconfig_option_list:\n\t  /* empty */\n\t| config_option_list config_option\n\t| config_option_list depends\n\t| config_option_list help\n;\n\nconfig_option: type prompt_stmt_opt T_EOL\n{\n\tmenu_set_type($1);\n\tprintd(DEBUG_PARSE, \"%s:%d:type(%u)\\n\",\n\t\tzconf_curname(), zconf_lineno(),\n\t\t$1);\n};\n\nconfig_option: T_PROMPT T_WORD_QUOTE if_expr T_EOL\n{\n\tmenu_add_prompt(P_PROMPT, $2, $3);\n\tprintd(DEBUG_PARSE, \"%s:%d:prompt\\n\", zconf_curname(), zconf_lineno());\n};\n\nconfig_option: default expr if_expr T_EOL\n{\n\tmenu_add_expr(P_DEFAULT, $2, $3);\n\tif ($1 != S_UNKNOWN)\n\t\tmenu_set_type($1);\n\tprintd(DEBUG_PARSE, \"%s:%d:default(%u)\\n\",\n\t\tzconf_curname(), zconf_lineno(),\n\t\t$1);\n};\n\nconfig_option: T_SELECT nonconst_symbol if_expr T_EOL\n{\n\tmenu_add_symbol(P_SELECT, $2, $3);\n\tprintd(DEBUG_PARSE, \"%s:%d:select\\n\", zconf_curname(), zconf_lineno());\n};\n\nconfig_option: T_IMPLY nonconst_symbol if_expr T_EOL\n{\n\tmenu_add_symbol(P_IMPLY, $2, $3);\n\tprintd(DEBUG_PARSE, \"%s:%d:imply\\n\", zconf_curname(), zconf_lineno());\n};\n\nconfig_option: T_RANGE symbol symbol if_expr T_EOL\n{\n\tmenu_add_expr(P_RANGE, expr_alloc_comp(E_RANGE,$2, $3), $4);\n\tprintd(DEBUG_PARSE, \"%s:%d:range\\n\", zconf_curname(), zconf_lineno());\n};\n\nconfig_option: T_MODULES T_EOL\n{\n\tif (modules_sym)\n\t\tzconf_error(\"symbol '%s' redefines option 'modules' already defined by symbol '%s'\",\n\t\t\t    current_entry->sym->name, modules_sym->name);\n\tmodules_sym = current_entry->sym;\n};\n\n/* choice entry */\n\nchoice: T_CHOICE word_opt T_EOL\n{\n\tstruct symbol *sym = sym_lookup($2, SYMBOL_CHOICE);\n\tsym->flags |= SYMBOL_NO_WRITE;\n\tmenu_add_entry(sym);\n\tmenu_add_expr(P_CHOICE, NULL, NULL);\n\tfree($2);\n\tprintd(DEBUG_PARSE, \"%s:%d:choice\\n\", zconf_curname(), zconf_lineno());\n};\n\nchoice_entry: choice choice_option_list\n{\n\t$$ = menu_add_menu();\n};\n\nchoice_end: end\n{\n\tif (zconf_endtoken($1, \"choice\")) {\n\t\tmenu_end_menu();\n\t\tprintd(DEBUG_PARSE, \"%s:%d:endchoice\\n\", zconf_curname(), zconf_lineno());\n\t}\n};\n\nchoice_stmt: choice_entry stmt_list_in_choice choice_end\n;\n\nchoice_option_list:\n\t  /* empty */\n\t| choice_option_list choice_option\n\t| choice_option_list depends\n\t| choice_option_list help\n;\n\nchoice_option: T_PROMPT T_WORD_QUOTE if_expr T_EOL\n{\n\tmenu_add_prompt(P_PROMPT, $2, $3);\n\tprintd(DEBUG_PARSE, \"%s:%d:prompt\\n\", zconf_curname(), zconf_lineno());\n};\n\nchoice_option: logic_type prompt_stmt_opt T_EOL\n{\n\tmenu_set_type($1);\n\tprintd(DEBUG_PARSE, \"%s:%d:type(%u)\\n\",\n\t       zconf_curname(), zconf_lineno(), $1);\n};\n\nchoice_option: T_OPTIONAL T_EOL\n{\n\tcurrent_entry->sym->flags |= SYMBOL_OPTIONAL;\n\tprintd(DEBUG_PARSE, \"%s:%d:optional\\n\", zconf_curname(), zconf_lineno());\n};\n\nchoice_option: T_RESET if_expr T_EOL\n{\n\tmenu_add_prop(P_RESET, NULL, $2);\n};\n\nchoice_option: T_DEFAULT nonconst_symbol if_expr T_EOL\n{\n\tmenu_add_symbol(P_DEFAULT, $2, $3);\n\tprintd(DEBUG_PARSE, \"%s:%d:default\\n\",\n\t       zconf_curname(), zconf_lineno());\n};\n\ntype:\n\t  logic_type\n\t| T_INT\t\t\t{ $$ = S_INT; }\n\t| T_HEX\t\t\t{ $$ = S_HEX; }\n\t| T_STRING\t\t{ $$ = S_STRING; }\n\nlogic_type:\n\t  T_BOOL\t\t{ $$ = S_BOOLEAN; }\n\t| T_TRISTATE\t\t{ $$ = S_TRISTATE; }\n\ndefault:\n\t  T_DEFAULT\t\t{ $$ = S_UNKNOWN; }\n\t| T_DEF_BOOL\t\t{ $$ = S_BOOLEAN; }\n\t| T_DEF_TRISTATE\t{ $$ = S_TRISTATE; }\n\n/* if entry */\n\nif_entry: T_IF expr T_EOL\n{\n\tprintd(DEBUG_PARSE, \"%s:%d:if\\n\", zconf_curname(), zconf_lineno());\n\tmenu_add_entry(NULL);\n\tmenu_add_dep($2);\n\t$$ = menu_add_menu();\n};\n\nif_end: end\n{\n\tif (zconf_endtoken($1, \"if\")) {\n\t\tmenu_end_menu();\n\t\tprintd(DEBUG_PARSE, \"%s:%d:endif\\n\", zconf_curname(), zconf_lineno());\n\t}\n};\n\nif_stmt: if_entry stmt_list if_end\n;\n\nif_stmt_in_choice: if_entry stmt_list_in_choice if_end\n;\n\n/* menu entry */\n\nmenu: T_MENU T_WORD_QUOTE T_EOL\n{\n\tmenu_add_entry(NULL);\n\tmenu_add_prompt(P_MENU, $2, NULL);\n\tprintd(DEBUG_PARSE, \"%s:%d:menu\\n\", zconf_curname(), zconf_lineno());\n};\n\nmenu_entry: menu menu_option_list\n{\n\t$$ = menu_add_menu();\n};\n\nmenu_end: end\n{\n\tif (zconf_endtoken($1, \"menu\")) {\n\t\tmenu_end_menu();\n\t\tprintd(DEBUG_PARSE, \"%s:%d:endmenu\\n\", zconf_curname(), zconf_lineno());\n\t}\n};\n\nmenu_stmt: menu_entry stmt_list menu_end\n;\n\nmenu_option_list:\n\t  /* empty */\n\t| menu_option_list visible\n\t| menu_option_list depends\n;\n\nsource_stmt: T_SOURCE T_WORD_QUOTE T_EOL\n{\n\tprintd(DEBUG_PARSE, \"%s:%d:source %s\\n\", zconf_curname(), zconf_lineno(), $2);\n\tzconf_nextfile($2);\n\tfree($2);\n};\n\n/* comment entry */\n\ncomment: T_COMMENT T_WORD_QUOTE T_EOL\n{\n\tmenu_add_entry(NULL);\n\tmenu_add_prompt(P_COMMENT, $2, NULL);\n\tprintd(DEBUG_PARSE, \"%s:%d:comment\\n\", zconf_curname(), zconf_lineno());\n};\n\ncomment_stmt: comment comment_option_list\n;\n\ncomment_option_list:\n\t  /* empty */\n\t| comment_option_list depends\n;\n\n/* help option */\n\nhelp_start: T_HELP T_EOL\n{\n\tprintd(DEBUG_PARSE, \"%s:%d:help\\n\", zconf_curname(), zconf_lineno());\n\tzconf_starthelp();\n};\n\nhelp: help_start T_HELPTEXT\n{\n\t/* Is the help text empty or all whitespace? */\n\tif ($2[strspn($2, \" \\f\\n\\r\\t\\v\")] == '\\0')\n\t\tzconfprint(\"warning: '%s' defined with blank help text\",\n\t\t\t   current_entry->sym->name ?: \"<choice>\");\n\n\tcurrent_entry->help = $2;\n};\n\n/* depends option */\n\ndepends: T_DEPENDS T_ON expr T_EOL\n{\n\tmenu_add_dep($3);\n\tprintd(DEBUG_PARSE, \"%s:%d:depends on\\n\", zconf_curname(), zconf_lineno());\n};\n\n/* visibility option */\nvisible: T_VISIBLE if_expr T_EOL\n{\n\tmenu_add_visibility($2);\n};\n\n/* prompt statement */\n\nprompt_stmt_opt:\n\t  /* empty */\n\t| T_WORD_QUOTE if_expr\n{\n\tmenu_add_prompt(P_PROMPT, $1, $2);\n};\n\nend:\t  T_ENDMENU T_EOL\t{ $$ = \"menu\"; }\n\t| T_ENDCHOICE T_EOL\t{ $$ = \"choice\"; }\n\t| T_ENDIF T_EOL\t\t{ $$ = \"if\"; }\n;\n\nif_expr:  /* empty */\t\t\t{ $$ = NULL; }\n\t| T_IF expr\t\t\t{ $$ = $2; }\n;\n\nexpr:\t  symbol\t\t\t\t{ $$ = expr_alloc_symbol($1); }\n\t| symbol T_LESS symbol\t\t\t{ $$ = expr_alloc_comp(E_LTH, $1, $3); }\n\t| symbol T_LESS_EQUAL symbol\t\t{ $$ = expr_alloc_comp(E_LEQ, $1, $3); }\n\t| symbol T_GREATER symbol\t\t{ $$ = expr_alloc_comp(E_GTH, $1, $3); }\n\t| symbol T_GREATER_EQUAL symbol\t\t{ $$ = expr_alloc_comp(E_GEQ, $1, $3); }\n\t| symbol T_EQUAL symbol\t\t\t{ $$ = expr_alloc_comp(E_EQUAL, $1, $3); }\n\t| symbol T_UNEQUAL symbol\t\t{ $$ = expr_alloc_comp(E_UNEQUAL, $1, $3); }\n\t| T_OPEN_PAREN expr T_CLOSE_PAREN\t{ $$ = $2; }\n\t| T_NOT expr\t\t\t\t{ $$ = expr_alloc_one(E_NOT, $2); }\n\t| expr T_OR expr\t\t\t{ $$ = expr_alloc_two(E_OR, $1, $3); }\n\t| expr T_AND expr\t\t\t{ $$ = expr_alloc_two(E_AND, $1, $3); }\n;\n\n/* For symbol definitions, selects, etc., where quotes are not accepted */\nnonconst_symbol: T_WORD { $$ = sym_lookup($1, 0); free($1); };\n\nsymbol:\t  nonconst_symbol\n\t| T_WORD_QUOTE\t{ $$ = sym_lookup($1, SYMBOL_CONST); free($1); }\n;\n\nword_opt: /* empty */\t\t\t{ $$ = NULL; }\n\t| T_WORD\n\n/* assignment statement */\n\nassignment_stmt:  T_WORD assign_op assign_val T_EOL\t{ variable_add($1, $3, $2); free($1); free($3); }\n\nassign_op:\n\t  T_EQUAL\t{ $$ = VAR_RECURSIVE; }\n\t| T_COLON_EQUAL\t{ $$ = VAR_SIMPLE; }\n\t| T_PLUS_EQUAL\t{ $$ = VAR_APPEND; }\n;\n\nassign_val:\n\t/* empty */\t\t{ $$ = xstrdup(\"\"); };\n\t| T_ASSIGN_VAL\n;\n\n%%\n\nvoid conf_parse(const char *name)\n{\n\tstruct symbol *sym;\n\tint i;\n\n\tzconf_initscan(name);\n\n\t_menu_init();\n\n#if YYDEBUG\n\tif (getenv(\"ZCONF_DEBUG\"))\n\t\tyydebug = 1;\n#endif\n\tyyparse();\n\n\t/* Variables are expanded in the parse phase. We can free them here. */\n\tvariable_all_del();\n\n\tif (yynerrs)\n\t\texit(1);\n\tif (!modules_sym)\n\t\tmodules_sym = sym_find( \"n\" );\n\n\tif (!menu_has_prompt(&rootmenu)) {\n\t\tcurrent_entry = &rootmenu;\n\t\tmenu_add_prompt(P_MENU, \"Main menu\", NULL);\n\t}\n\n\tmenu_finalize(&rootmenu);\n\tfor_all_symbols(i, sym) {\n\t\tif (sym_check_deps(sym))\n\t\t\tyynerrs++;\n\t}\n\tif (yynerrs)\n\t\texit(1);\n\tconf_set_changed(true);\n}\n\nstatic bool zconf_endtoken(const char *tokenname,\n\t\t\t   const char *expected_tokenname)\n{\n\tif (strcmp(tokenname, expected_tokenname)) {\n\t\tzconf_error(\"unexpected '%s' within %s block\",\n\t\t\t    tokenname, expected_tokenname);\n\t\tyynerrs++;\n\t\treturn false;\n\t}\n\tif (current_menu->file != current_file) {\n\t\tzconf_error(\"'%s' in different file than '%s'\",\n\t\t\t    tokenname, expected_tokenname);\n\t\tfprintf(stderr, \"%s:%d: location of the '%s'\\n\",\n\t\t\tcurrent_menu->file->name, current_menu->lineno,\n\t\t\texpected_tokenname);\n\t\tyynerrs++;\n\t\treturn false;\n\t}\n\treturn true;\n}\n\nstatic void zconfprint(const char *err, ...)\n{\n\tva_list ap;\n\n\tfprintf(stderr, \"%s:%d: \", zconf_curname(), zconf_lineno());\n\tva_start(ap, err);\n\tvfprintf(stderr, err, ap);\n\tva_end(ap);\n\tfprintf(stderr, \"\\n\");\n}\n\nstatic void zconf_error(const char *err, ...)\n{\n\tva_list ap;\n\n\tyynerrs++;\n\tfprintf(stderr, \"%s:%d: \", zconf_curname(), zconf_lineno());\n\tva_start(ap, err);\n\tvfprintf(stderr, err, ap);\n\tva_end(ap);\n\tfprintf(stderr, \"\\n\");\n}\n\nstatic void yyerror(const char *err)\n{\n\tfprintf(stderr, \"%s:%d: %s\\n\", zconf_curname(), zconf_lineno() + 1, err);\n}\n\nstatic void print_quoted_string(FILE *out, const char *str)\n{\n\tconst char *p;\n\tint len;\n\n\tputc('\"', out);\n\twhile ((p = strchr(str, '\"'))) {\n\t\tlen = p - str;\n\t\tif (len)\n\t\t\tfprintf(out, \"%.*s\", len, str);\n\t\tfputs(\"\\\\\\\"\", out);\n\t\tstr = p + 1;\n\t}\n\tfputs(str, out);\n\tputc('\"', out);\n}\n\nstatic void print_symbol(FILE *out, struct menu *menu)\n{\n\tstruct symbol *sym = menu->sym;\n\tstruct property *prop;\n\n\tif (sym_is_choice(sym))\n\t\tfprintf(out, \"\\nchoice\\n\");\n\telse\n\t\tfprintf(out, \"\\nconfig %s\\n\", sym->name);\n\tswitch (sym->type) {\n\tcase S_BOOLEAN:\n\t\tfputs(\"  bool\\n\", out);\n\t\tbreak;\n\tcase S_TRISTATE:\n\t\tfputs(\"  tristate\\n\", out);\n\t\tbreak;\n\tcase S_STRING:\n\t\tfputs(\"  string\\n\", out);\n\t\tbreak;\n\tcase S_INT:\n\t\tfputs(\"  integer\\n\", out);\n\t\tbreak;\n\tcase S_HEX:\n\t\tfputs(\"  hex\\n\", out);\n\t\tbreak;\n\tdefault:\n\t\tfputs(\"  ???\\n\", out);\n\t\tbreak;\n\t}\n\tfor (prop = sym->prop; prop; prop = prop->next) {\n\t\tif (prop->menu != menu)\n\t\t\tcontinue;\n\t\tswitch (prop->type) {\n\t\tcase P_PROMPT:\n\t\t\tfputs(\"  prompt \", out);\n\t\t\tprint_quoted_string(out, prop->text);\n\t\t\tif (!expr_is_yes(prop->visible.expr)) {\n\t\t\t\tfputs(\" if \", out);\n\t\t\t\texpr_fprint(prop->visible.expr, out);\n\t\t\t}\n\t\t\tfputc('\\n', out);\n\t\t\tbreak;\n\t\tcase P_DEFAULT:\n\t\t\tfputs( \"  default \", out);\n\t\t\texpr_fprint(prop->expr, out);\n\t\t\tif (!expr_is_yes(prop->visible.expr)) {\n\t\t\t\tfputs(\" if \", out);\n\t\t\t\texpr_fprint(prop->visible.expr, out);\n\t\t\t}\n\t\t\tfputc('\\n', out);\n\t\t\tbreak;\n\t\tcase P_CHOICE:\n\t\t\tfputs(\"  #choice value\\n\", out);\n\t\t\tbreak;\n\t\tcase P_SELECT:\n\t\t\tfputs( \"  select \", out);\n\t\t\texpr_fprint(prop->expr, out);\n\t\t\tfputc('\\n', out);\n\t\t\tbreak;\n\t\tcase P_IMPLY:\n\t\t\tfputs( \"  imply \", out);\n\t\t\texpr_fprint(prop->expr, out);\n\t\t\tfputc('\\n', out);\n\t\t\tbreak;\n\t\tcase P_RANGE:\n\t\t\tfputs( \"  range \", out);\n\t\t\texpr_fprint(prop->expr, out);\n\t\t\tfputc('\\n', out);\n\t\t\tbreak;\n\t\tcase P_MENU:\n\t\t\tfputs( \"  menu \", out);\n\t\t\tprint_quoted_string(out, prop->text);\n\t\t\tfputc('\\n', out);\n\t\t\tbreak;\n\t\tcase P_SYMBOL:\n\t\t\tfputs( \"  symbol \", out);\n\t\t\tfprintf(out, \"%s\\n\", prop->menu->sym->name);\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tfprintf(out, \"  unknown prop %d!\\n\", prop->type);\n\t\t\tbreak;\n\t\t}\n\t}\n\tif (menu->help) {\n\t\tint len = strlen(menu->help);\n\t\twhile (menu->help[--len] == '\\n')\n\t\t\tmenu->help[len] = 0;\n\t\tfprintf(out, \"  help\\n%s\\n\", menu->help);\n\t}\n}\n\nvoid zconfdump(FILE *out)\n{\n\tstruct property *prop;\n\tstruct symbol *sym;\n\tstruct menu *menu;\n\n\tmenu = rootmenu.list;\n\twhile (menu) {\n\t\tif ((sym = menu->sym))\n\t\t\tprint_symbol(out, menu);\n\t\telse if ((prop = menu->prompt)) {\n\t\t\tswitch (prop->type) {\n\t\t\tcase P_COMMENT:\n\t\t\t\tfputs(\"\\ncomment \", out);\n\t\t\t\tprint_quoted_string(out, prop->text);\n\t\t\t\tfputs(\"\\n\", out);\n\t\t\t\tbreak;\n\t\t\tcase P_MENU:\n\t\t\t\tfputs(\"\\nmenu \", out);\n\t\t\t\tprint_quoted_string(out, prop->text);\n\t\t\t\tfputs(\"\\n\", out);\n\t\t\t\tbreak;\n\t\t\tdefault:\n\t\t\t\t;\n\t\t\t}\n\t\t\tif (!expr_is_yes(prop->visible.expr)) {\n\t\t\t\tfputs(\"  depends \", out);\n\t\t\t\texpr_fprint(prop->visible.expr, out);\n\t\t\t\tfputc('\\n', out);\n\t\t\t}\n\t\t}\n\n\t\tif (menu->list)\n\t\t\tmenu = menu->list;\n\t\telse if (menu->next)\n\t\t\tmenu = menu->next;\n\t\telse while ((menu = menu->parent)) {\n\t\t\tif (menu->prompt && menu->prompt->type == P_MENU)\n\t\t\t\tfputs(\"\\nendmenu\\n\", out);\n\t\t\tif (menu->next) {\n\t\t\t\tmenu = menu->next;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t}\n}\n"
  },
  {
    "path": "scripts/config/preprocess.c",
    "content": "// SPDX-License-Identifier: GPL-2.0-only\n//\n// Copyright (C) 2018 Masahiro Yamada <yamada.masahiro@socionext.com>\n\n#include <ctype.h>\n#include <stdarg.h>\n#include <stdbool.h>\n#include <stdio.h>\n#include <stdlib.h>\n#include <string.h>\n\n#include \"list.h\"\n#include \"lkc.h\"\n\n#define ARRAY_SIZE(arr)\t\t(sizeof(arr) / sizeof((arr)[0]))\n\nstatic char *expand_string_with_args(const char *in, int argc, char *argv[]);\nstatic char *expand_string(const char *in);\n\nstatic void __attribute__((noreturn)) pperror(const char *format, ...)\n{\n\tva_list ap;\n\n\tfprintf(stderr, \"%s:%d: \", current_file->name, yylineno);\n\tva_start(ap, format);\n\tvfprintf(stderr, format, ap);\n\tva_end(ap);\n\tfprintf(stderr, \"\\n\");\n\n\texit(1);\n}\n\n/*\n * Environment variables\n */\nstatic LIST_HEAD(env_list);\n\nstruct env {\n\tchar *name;\n\tchar *value;\n\tstruct list_head node;\n};\n\nstatic void env_add(const char *name, const char *value)\n{\n\tstruct env *e;\n\n\te = xmalloc(sizeof(*e));\n\te->name = xstrdup(name);\n\te->value = xstrdup(value);\n\n\tlist_add_tail(&e->node, &env_list);\n}\n\nstatic void env_del(struct env *e)\n{\n\tlist_del(&e->node);\n\tfree(e->name);\n\tfree(e->value);\n\tfree(e);\n}\n\n/* The returned pointer must be freed when done */\nstatic char *env_expand(const char *name)\n{\n\tstruct env *e;\n\tconst char *value;\n\n\tif (!*name)\n\t\treturn NULL;\n\n\tlist_for_each_entry(e, &env_list, node) {\n\t\tif (!strcmp(name, e->name))\n\t\t\treturn xstrdup(e->value);\n\t}\n\n\tvalue = getenv(name);\n\tif (!value)\n\t\treturn NULL;\n\n\t/*\n\t * We need to remember all referenced environment variables.\n\t * They will be written out to include/config/auto.conf.cmd\n\t */\n\tenv_add(name, value);\n\n\treturn xstrdup(value);\n}\n\nvoid env_write_dep(FILE *f, const char *autoconfig_name)\n{\n\tstruct env *e, *tmp;\n\n\tlist_for_each_entry_safe(e, tmp, &env_list, node) {\n\t\tfprintf(f, \"ifneq \\\"$(%s)\\\" \\\"%s\\\"\\n\", e->name, e->value);\n\t\tfprintf(f, \"%s: FORCE\\n\", autoconfig_name);\n\t\tfprintf(f, \"endif\\n\");\n\t\tenv_del(e);\n\t}\n}\n\n/*\n * Built-in functions\n */\nstruct function {\n\tconst char *name;\n\tunsigned int min_args;\n\tunsigned int max_args;\n\tchar *(*func)(int argc, char *argv[]);\n};\n\nstatic char *do_error_if(int argc, char *argv[])\n{\n\tif (!strcmp(argv[0], \"y\"))\n\t\tpperror(\"%s\", argv[1]);\n\n\treturn xstrdup(\"\");\n}\n\nstatic char *do_filename(int argc, char *argv[])\n{\n\treturn xstrdup(current_file->name);\n}\n\nstatic char *do_info(int argc, char *argv[])\n{\n\tprintf(\"%s\\n\", argv[0]);\n\n\treturn xstrdup(\"\");\n}\n\nstatic char *do_lineno(int argc, char *argv[])\n{\n\tchar buf[16];\n\n\tsprintf(buf, \"%d\", yylineno);\n\n\treturn xstrdup(buf);\n}\n\nstatic char *do_shell(int argc, char *argv[])\n{\n\tFILE *p;\n\tchar buf[256];\n\tchar *cmd;\n\tsize_t nread;\n\tint i;\n\n\tcmd = argv[0];\n\n\tp = popen(cmd, \"r\");\n\tif (!p) {\n\t\tperror(cmd);\n\t\texit(1);\n\t}\n\n\tnread = fread(buf, 1, sizeof(buf), p);\n\tif (nread == sizeof(buf))\n\t\tnread--;\n\n\t/* remove trailing new lines */\n\twhile (nread > 0 && buf[nread - 1] == '\\n')\n\t\tnread--;\n\n\tbuf[nread] = 0;\n\n\t/* replace a new line with a space */\n\tfor (i = 0; i < nread; i++) {\n\t\tif (buf[i] == '\\n')\n\t\t\tbuf[i] = ' ';\n\t}\n\n\tif (pclose(p) == -1) {\n\t\tperror(cmd);\n\t\texit(1);\n\t}\n\n\treturn xstrdup(buf);\n}\n\nstatic char *do_warning_if(int argc, char *argv[])\n{\n\tif (!strcmp(argv[0], \"y\"))\n\t\tfprintf(stderr, \"%s:%d: %s\\n\",\n\t\t\tcurrent_file->name, yylineno, argv[1]);\n\n\treturn xstrdup(\"\");\n}\n\nstatic const struct function function_table[] = {\n\t/* Name\t\tMIN\tMAX\tFunction */\n\t{ \"error-if\",\t2,\t2,\tdo_error_if },\n\t{ \"filename\",\t0,\t0,\tdo_filename },\n\t{ \"info\",\t1,\t1,\tdo_info },\n\t{ \"lineno\",\t0,\t0,\tdo_lineno },\n\t{ \"shell\",\t1,\t1,\tdo_shell },\n\t{ \"warning-if\",\t2,\t2,\tdo_warning_if },\n};\n\n#define FUNCTION_MAX_ARGS\t\t16\n\nstatic char *function_expand(const char *name, int argc, char *argv[])\n{\n\tconst struct function *f;\n\tint i;\n\n\tfor (i = 0; i < ARRAY_SIZE(function_table); i++) {\n\t\tf = &function_table[i];\n\t\tif (strcmp(f->name, name))\n\t\t\tcontinue;\n\n\t\tif (argc < f->min_args)\n\t\t\tpperror(\"too few function arguments passed to '%s'\",\n\t\t\t\tname);\n\n\t\tif (argc > f->max_args)\n\t\t\tpperror(\"too many function arguments passed to '%s'\",\n\t\t\t\tname);\n\n\t\treturn f->func(argc, argv);\n\t}\n\n\treturn NULL;\n}\n\n/*\n * Variables (and user-defined functions)\n */\nstatic LIST_HEAD(variable_list);\n\nstruct variable {\n\tchar *name;\n\tchar *value;\n\tenum variable_flavor flavor;\n\tint exp_count;\n\tstruct list_head node;\n};\n\nstatic struct variable *variable_lookup(const char *name)\n{\n\tstruct variable *v;\n\n\tlist_for_each_entry(v, &variable_list, node) {\n\t\tif (!strcmp(name, v->name))\n\t\t\treturn v;\n\t}\n\n\treturn NULL;\n}\n\nstatic char *variable_expand(const char *name, int argc, char *argv[])\n{\n\tstruct variable *v;\n\tchar *res;\n\n\tv = variable_lookup(name);\n\tif (!v)\n\t\treturn NULL;\n\n\tif (argc == 0 && v->exp_count)\n\t\tpperror(\"Recursive variable '%s' references itself (eventually)\",\n\t\t\tname);\n\n\tif (v->exp_count > 1000)\n\t\tpperror(\"Too deep recursive expansion\");\n\n\tv->exp_count++;\n\n\tif (v->flavor == VAR_RECURSIVE)\n\t\tres = expand_string_with_args(v->value, argc, argv);\n\telse\n\t\tres = xstrdup(v->value);\n\n\tv->exp_count--;\n\n\treturn res;\n}\n\nvoid variable_add(const char *name, const char *value,\n\t\t  enum variable_flavor flavor)\n{\n\tstruct variable *v;\n\tchar *new_value;\n\tbool append = false;\n\n\tv = variable_lookup(name);\n\tif (v) {\n\t\t/* For defined variables, += inherits the existing flavor */\n\t\tif (flavor == VAR_APPEND) {\n\t\t\tflavor = v->flavor;\n\t\t\tappend = true;\n\t\t} else {\n\t\t\tfree(v->value);\n\t\t}\n\t} else {\n\t\t/* For undefined variables, += assumes the recursive flavor */\n\t\tif (flavor == VAR_APPEND)\n\t\t\tflavor = VAR_RECURSIVE;\n\n\t\tv = xmalloc(sizeof(*v));\n\t\tv->name = xstrdup(name);\n\t\tv->exp_count = 0;\n\t\tlist_add_tail(&v->node, &variable_list);\n\t}\n\n\tv->flavor = flavor;\n\n\tif (flavor == VAR_SIMPLE)\n\t\tnew_value = expand_string(value);\n\telse\n\t\tnew_value = xstrdup(value);\n\n\tif (append) {\n\t\tv->value = xrealloc(v->value,\n\t\t\t\t    strlen(v->value) + strlen(new_value) + 2);\n\t\tstrcat(v->value, \" \");\n\t\tstrcat(v->value, new_value);\n\t\tfree(new_value);\n\t} else {\n\t\tv->value = new_value;\n\t}\n}\n\nstatic void variable_del(struct variable *v)\n{\n\tlist_del(&v->node);\n\tfree(v->name);\n\tfree(v->value);\n\tfree(v);\n}\n\nvoid variable_all_del(void)\n{\n\tstruct variable *v, *tmp;\n\n\tlist_for_each_entry_safe(v, tmp, &variable_list, node)\n\t\tvariable_del(v);\n}\n\n/*\n * Evaluate a clause with arguments.  argc/argv are arguments from the upper\n * function call.\n *\n * Returned string must be freed when done\n */\nstatic char *eval_clause(const char *str, size_t len, int argc, char *argv[])\n{\n\tchar *tmp, *name, *res, *endptr, *prev, *p;\n\tint new_argc = 0;\n\tchar *new_argv[FUNCTION_MAX_ARGS];\n\tint nest = 0;\n\tint i;\n\tunsigned long n;\n\n\ttmp = xstrndup(str, len);\n\n\t/*\n\t * If variable name is '1', '2', etc.  It is generally an argument\n\t * from a user-function call (i.e. local-scope variable).  If not\n\t * available, then look-up global-scope variables.\n\t */\n\tn = strtoul(tmp, &endptr, 10);\n\tif (!*endptr && n > 0 && n <= argc) {\n\t\tres = xstrdup(argv[n - 1]);\n\t\tgoto free_tmp;\n\t}\n\n\tprev = p = tmp;\n\n\t/*\n\t * Split into tokens\n\t * The function name and arguments are separated by a comma.\n\t * For example, if the function call is like this:\n\t *   $(foo,$(x),$(y))\n\t *\n\t * The input string for this helper should be:\n\t *   foo,$(x),$(y)\n\t *\n\t * and split into:\n\t *   new_argv[0] = 'foo'\n\t *   new_argv[1] = '$(x)'\n\t *   new_argv[2] = '$(y)'\n\t */\n\twhile (*p) {\n\t\tif (nest == 0 && *p == ',') {\n\t\t\t*p = 0;\n\t\t\tif (new_argc >= FUNCTION_MAX_ARGS)\n\t\t\t\tpperror(\"too many function arguments\");\n\t\t\tnew_argv[new_argc++] = prev;\n\t\t\tprev = p + 1;\n\t\t} else if (*p == '(') {\n\t\t\tnest++;\n\t\t} else if (*p == ')') {\n\t\t\tnest--;\n\t\t}\n\n\t\tp++;\n\t}\n\tnew_argv[new_argc++] = prev;\n\n\t/*\n\t * Shift arguments\n\t * new_argv[0] represents a function name or a variable name.  Put it\n\t * into 'name', then shift the rest of the arguments.  This simplifies\n\t * 'const' handling.\n\t */\n\tname = expand_string_with_args(new_argv[0], argc, argv);\n\tnew_argc--;\n\tfor (i = 0; i < new_argc; i++)\n\t\tnew_argv[i] = expand_string_with_args(new_argv[i + 1],\n\t\t\t\t\t\t      argc, argv);\n\n\t/* Search for variables */\n\tres = variable_expand(name, new_argc, new_argv);\n\tif (res)\n\t\tgoto free;\n\n\t/* Look for built-in functions */\n\tres = function_expand(name, new_argc, new_argv);\n\tif (res)\n\t\tgoto free;\n\n\t/* Last, try environment variable */\n\tif (new_argc == 0) {\n\t\tres = env_expand(name);\n\t\tif (res)\n\t\t\tgoto free;\n\t}\n\n\tres = xstrdup(\"\");\nfree:\n\tfor (i = 0; i < new_argc; i++)\n\t\tfree(new_argv[i]);\n\tfree(name);\nfree_tmp:\n\tfree(tmp);\n\n\treturn res;\n}\n\n/*\n * Expand a string that follows '$'\n *\n * For example, if the input string is\n *     ($(FOO)$($(BAR)))$(BAZ)\n * this helper evaluates\n *     $($(FOO)$($(BAR)))\n * and returns a new string containing the expansion (note that the string is\n * recursively expanded), also advancing 'str' to point to the next character\n * after the corresponding closing parenthesis, in this case, *str will be\n *     $(BAR)\n */\nstatic char *expand_dollar_with_args(const char **str, int argc, char *argv[])\n{\n\tconst char *p = *str;\n\tconst char *q;\n\tint nest = 0;\n\n\t/*\n\t * In Kconfig, variable/function references always start with \"$(\".\n\t * Neither single-letter variables as in $A nor curly braces as in ${CC}\n\t * are supported.  '$' not followed by '(' loses its special meaning.\n\t */\n\tif (*p != '(') {\n\t\t*str = p;\n\t\treturn xstrdup(\"$\");\n\t}\n\n\tp++;\n\tq = p;\n\twhile (*q) {\n\t\tif (*q == '(') {\n\t\t\tnest++;\n\t\t} else if (*q == ')') {\n\t\t\tif (nest-- == 0)\n\t\t\t\tbreak;\n\t\t}\n\t\tq++;\n\t}\n\n\tif (!*q)\n\t\tpperror(\"unterminated reference to '%s': missing ')'\", p);\n\n\t/* Advance 'str' to after the expanded initial portion of the string */\n\t*str = q + 1;\n\n\treturn eval_clause(p, q - p, argc, argv);\n}\n\nchar *expand_dollar(const char **str)\n{\n\treturn expand_dollar_with_args(str, 0, NULL);\n}\n\nstatic char *__expand_string(const char **str, bool (*is_end)(char c),\n\t\t\t     int argc, char *argv[])\n{\n\tconst char *in, *p;\n\tchar *expansion, *out;\n\tsize_t in_len, out_len;\n\n\tout = xmalloc(1);\n\t*out = 0;\n\tout_len = 1;\n\n\tp = in = *str;\n\n\twhile (1) {\n\t\tif (*p == '$') {\n\t\t\tin_len = p - in;\n\t\t\tp++;\n\t\t\texpansion = expand_dollar_with_args(&p, argc, argv);\n\t\t\tout_len += in_len + strlen(expansion);\n\t\t\tout = xrealloc(out, out_len);\n\t\t\tstrncat(out, in, in_len);\n\t\t\tstrcat(out, expansion);\n\t\t\tfree(expansion);\n\t\t\tin = p;\n\t\t\tcontinue;\n\t\t}\n\n\t\tif (is_end(*p))\n\t\t\tbreak;\n\n\t\tp++;\n\t}\n\n\tin_len = p - in;\n\tout_len += in_len;\n\tout = xrealloc(out, out_len);\n\tstrncat(out, in, in_len);\n\n\t/* Advance 'str' to the end character */\n\t*str = p;\n\n\treturn out;\n}\n\nstatic bool is_end_of_str(char c)\n{\n\treturn !c;\n}\n\n/*\n * Expand variables and functions in the given string.  Undefined variables\n * expand to an empty string.\n * The returned string must be freed when done.\n */\nstatic char *expand_string_with_args(const char *in, int argc, char *argv[])\n{\n\treturn __expand_string(&in, is_end_of_str, argc, argv);\n}\n\nstatic char *expand_string(const char *in)\n{\n\treturn expand_string_with_args(in, 0, NULL);\n}\n\nstatic bool is_end_of_token(char c)\n{\n\t/* Why are '.' and '/' valid characters for symbols? */\n\treturn !(isalnum(c) || c == '_' || c == '-' || c == '.' || c == '/');\n}\n\n/*\n * Expand variables in a token.  The parsing stops when a token separater\n * (in most cases, it is a whitespace) is encountered.  'str' is updated to\n * point to the next character.\n *\n * The returned string must be freed when done.\n */\nchar *expand_one_token(const char **str)\n{\n\treturn __expand_string(str, is_end_of_token, 0, NULL);\n}\n"
  },
  {
    "path": "scripts/config/qconf-cfg.sh",
    "content": "#!/bin/sh\n# SPDX-License-Identifier: GPL-2.0-only\n\nPKG=\"Qt5Core Qt5Gui Qt5Widgets\"\n\nif [ -z \"$(command -v pkg-config)\" ]; then\n\techo >&2 \"*\"\n\techo >&2 \"* 'make xconfig' requires 'pkg-config'. Please install it.\"\n\techo >&2 \"*\"\n\texit 1\nfi\n\nif pkg-config --exists $PKG; then\n\techo cflags=\\\"-std=c++11 -fPIC $(pkg-config --cflags $PKG)\\\"\n\techo libs=\\\"$(pkg-config --libs $PKG)\\\"\n\techo moc=\\\"$(pkg-config --variable=host_bins Qt5Core)/moc\\\"\n\texit 0\nfi\n\necho >&2 \"*\"\necho >&2 \"* Could not find Qt5 via pkg-config.\"\necho >&2 \"* Please install Qt5 and make sure it's in PKG_CONFIG_PATH\"\necho >&2 \"*\"\nexit 1\n"
  },
  {
    "path": "scripts/config/qconf.cc",
    "content": "// SPDX-License-Identifier: GPL-2.0-only\n/*\n * Copyright (C) 2002 Roman Zippel <zippel@linux-m68k.org>\n * Copyright (C) 2015 Boris Barbulovski <bbarbulovski@gmail.com>\n */\n\n#include <QAction>\n#include <QApplication>\n#include <QCloseEvent>\n#include <QDebug>\n#include <QDesktopWidget>\n#include <QFileDialog>\n#include <QLabel>\n#include <QLayout>\n#include <QList>\n#include <QMenu>\n#include <QMenuBar>\n#include <QMessageBox>\n#include <QToolBar>\n\n#include <stdlib.h>\n\n#include \"lkc.h\"\n#include \"qconf.h\"\n\n#include \"images.h\"\n\n\nstatic QApplication *configApp;\nstatic ConfigSettings *configSettings;\n\nQAction *ConfigMainWindow::saveAction;\n\nConfigSettings::ConfigSettings()\n\t: QSettings(\"kernel.org\", \"qconf\")\n{\n}\n\n/**\n * Reads a list of integer values from the application settings.\n */\nQList<int> ConfigSettings::readSizes(const QString& key, bool *ok)\n{\n\tQList<int> result;\n\n\tif (contains(key))\n\t{\n\t\tQStringList entryList = value(key).toStringList();\n\t\tQStringList::Iterator it;\n\n\t\tfor (it = entryList.begin(); it != entryList.end(); ++it)\n\t\t\tresult.push_back((*it).toInt());\n\n\t\t*ok = true;\n\t}\n\telse\n\t\t*ok = false;\n\n\treturn result;\n}\n\n/**\n * Writes a list of integer values to the application settings.\n */\nbool ConfigSettings::writeSizes(const QString& key, const QList<int>& value)\n{\n\tQStringList stringList;\n\tQList<int>::ConstIterator it;\n\n\tfor (it = value.begin(); it != value.end(); ++it)\n\t\tstringList.push_back(QString::number(*it));\n\tsetValue(key, stringList);\n\n\treturn true;\n}\n\nQIcon ConfigItem::symbolYesIcon;\nQIcon ConfigItem::symbolModIcon;\nQIcon ConfigItem::symbolNoIcon;\nQIcon ConfigItem::choiceYesIcon;\nQIcon ConfigItem::choiceNoIcon;\nQIcon ConfigItem::menuIcon;\nQIcon ConfigItem::menubackIcon;\n\n/*\n * update the displayed of a menu entry\n */\nvoid ConfigItem::updateMenu(void)\n{\n\tConfigList* list;\n\tstruct symbol* sym;\n\tstruct property *prop;\n\tQString prompt;\n\tint type;\n\ttristate expr;\n\n\tlist = listView();\n\tif (goParent) {\n\t\tsetIcon(promptColIdx, menubackIcon);\n\t\tprompt = \"..\";\n\t\tgoto set_prompt;\n\t}\n\n\tsym = menu->sym;\n\tprop = menu->prompt;\n\tprompt = menu_get_prompt(menu);\n\n\tif (prop) switch (prop->type) {\n\tcase P_MENU:\n\t\tif (list->mode == singleMode || list->mode == symbolMode) {\n\t\t\t/* a menuconfig entry is displayed differently\n\t\t\t * depending whether it's at the view root or a child.\n\t\t\t */\n\t\t\tif (sym && list->rootEntry == menu)\n\t\t\t\tbreak;\n\t\t\tsetIcon(promptColIdx, menuIcon);\n\t\t} else {\n\t\t\tif (sym)\n\t\t\t\tbreak;\n\t\t\tsetIcon(promptColIdx, QIcon());\n\t\t}\n\t\tgoto set_prompt;\n\tcase P_COMMENT:\n\t\tsetIcon(promptColIdx, QIcon());\n\t\tprompt = \"*** \" + prompt + \" ***\";\n\t\tgoto set_prompt;\n\tdefault:\n\t\t;\n\t}\n\tif (!sym)\n\t\tgoto set_prompt;\n\n\tsetText(nameColIdx, sym->name);\n\n\ttype = sym_get_type(sym);\n\tswitch (type) {\n\tcase S_BOOLEAN:\n\tcase S_TRISTATE:\n\t\tchar ch;\n\n\t\tif (!sym_is_changeable(sym) && list->optMode == normalOpt) {\n\t\t\tsetIcon(promptColIdx, QIcon());\n\t\t\tbreak;\n\t\t}\n\t\texpr = sym_get_tristate_value(sym);\n\t\tswitch (expr) {\n\t\tcase yes:\n\t\t\tif (sym_is_choice_value(sym) && type == S_BOOLEAN)\n\t\t\t\tsetIcon(promptColIdx, choiceYesIcon);\n\t\t\telse\n\t\t\t\tsetIcon(promptColIdx, symbolYesIcon);\n\t\t\tch = 'Y';\n\t\t\tbreak;\n\t\tcase mod:\n\t\t\tsetIcon(promptColIdx, symbolModIcon);\n\t\t\tch = 'M';\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tif (sym_is_choice_value(sym) && type == S_BOOLEAN)\n\t\t\t\tsetIcon(promptColIdx, choiceNoIcon);\n\t\t\telse\n\t\t\t\tsetIcon(promptColIdx, symbolNoIcon);\n\t\t\tch = 'N';\n\t\t\tbreak;\n\t\t}\n\n\t\tsetText(dataColIdx, QChar(ch));\n\t\tbreak;\n\tcase S_INT:\n\tcase S_HEX:\n\tcase S_STRING:\n\t\tsetText(dataColIdx, sym_get_string_value(sym));\n\t\tbreak;\n\t}\n\tif (!sym_has_value(sym) && visible)\n\t\tprompt += \" (NEW)\";\nset_prompt:\n\tsetText(promptColIdx, prompt);\n}\n\nvoid ConfigItem::testUpdateMenu(bool v)\n{\n\tConfigItem* i;\n\n\tvisible = v;\n\tif (!menu)\n\t\treturn;\n\n\tsym_calc_value(menu->sym);\n\tif (menu->flags & MENU_CHANGED) {\n\t\t/* the menu entry changed, so update all list items */\n\t\tmenu->flags &= ~MENU_CHANGED;\n\t\tfor (i = (ConfigItem*)menu->data; i; i = i->nextItem)\n\t\t\ti->updateMenu();\n\t} else if (listView()->updateAll)\n\t\tupdateMenu();\n}\n\n\n/*\n * construct a menu entry\n */\nvoid ConfigItem::init(void)\n{\n\tif (menu) {\n\t\tConfigList* list = listView();\n\t\tnextItem = (ConfigItem*)menu->data;\n\t\tmenu->data = this;\n\n\t\tif (list->mode != fullMode)\n\t\t\tsetExpanded(true);\n\t\tsym_calc_value(menu->sym);\n\n\t\tif (menu->sym) {\n\t\t\tenum symbol_type type = menu->sym->type;\n\n\t\t\t// Allow to edit \"int\", \"hex\", and \"string\" in-place in\n\t\t\t// the data column. Unfortunately, you cannot specify\n\t\t\t// the flags per column. Set ItemIsEditable for all\n\t\t\t// columns here, and check the column in createEditor().\n\t\t\tif (type == S_INT || type == S_HEX || type == S_STRING)\n\t\t\t\tsetFlags(flags() | Qt::ItemIsEditable);\n\t\t}\n\t}\n\tupdateMenu();\n}\n\n/*\n * destruct a menu entry\n */\nConfigItem::~ConfigItem(void)\n{\n\tif (menu) {\n\t\tConfigItem** ip = (ConfigItem**)&menu->data;\n\t\tfor (; *ip; ip = &(*ip)->nextItem) {\n\t\t\tif (*ip == this) {\n\t\t\t\t*ip = nextItem;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t}\n}\n\nQWidget *ConfigItemDelegate::createEditor(QWidget *parent,\n\t\t\t\t\t  const QStyleOptionViewItem &option,\n\t\t\t\t\t  const QModelIndex &index) const\n{\n\tConfigItem *item;\n\n\t// Only the data column is editable\n\tif (index.column() != dataColIdx)\n\t\treturn nullptr;\n\n\t// You cannot edit invisible menus\n\titem = static_cast<ConfigItem *>(index.internalPointer());\n\tif (!item || !item->menu || !menu_is_visible(item->menu))\n\t\treturn nullptr;\n\n\treturn QStyledItemDelegate::createEditor(parent, option, index);\n}\n\nvoid ConfigItemDelegate::setModelData(QWidget *editor,\n\t\t\t\t      QAbstractItemModel *model,\n\t\t\t\t      const QModelIndex &index) const\n{\n\tQLineEdit *lineEdit;\n\tConfigItem *item;\n\tstruct symbol *sym;\n\tbool success;\n\n\tlineEdit = qobject_cast<QLineEdit *>(editor);\n\t// If this is not a QLineEdit, use the parent's default.\n\t// (does this happen?)\n\tif (!lineEdit)\n\t\tgoto parent;\n\n\titem = static_cast<ConfigItem *>(index.internalPointer());\n\tif (!item || !item->menu)\n\t\tgoto parent;\n\n\tsym = item->menu->sym;\n\tif (!sym)\n\t\tgoto parent;\n\n\tsuccess = sym_set_string_value(sym, lineEdit->text().toUtf8().data());\n\tif (success) {\n\t\tConfigList::updateListForAll();\n\t} else {\n\t\tQMessageBox::information(editor, \"qconf\",\n\t\t\t\"Cannot set the data (maybe due to out of range).\\n\"\n\t\t\t\"Setting the old value.\");\n\t\tlineEdit->setText(sym_get_string_value(sym));\n\t}\n\nparent:\n\tQStyledItemDelegate::setModelData(editor, model, index);\n}\n\nConfigList::ConfigList(QWidget *parent, const char *name)\n\t: QTreeWidget(parent),\n\t  updateAll(false),\n\t  showName(false), mode(singleMode), optMode(normalOpt),\n\t  rootEntry(0), headerPopup(0)\n{\n\tsetObjectName(name);\n\tsetSortingEnabled(false);\n\tsetRootIsDecorated(true);\n\n\tsetVerticalScrollMode(ScrollPerPixel);\n\tsetHorizontalScrollMode(ScrollPerPixel);\n\n\tsetHeaderLabels(QStringList() << \"Option\" << \"Name\" << \"Value\");\n\n\tconnect(this, &ConfigList::itemSelectionChanged,\n\t\tthis, &ConfigList::updateSelection);\n\n\tif (name) {\n\t\tconfigSettings->beginGroup(name);\n\t\tshowName = configSettings->value(\"/showName\", false).toBool();\n\t\toptMode = (enum optionMode)configSettings->value(\"/optionMode\", 0).toInt();\n\t\tconfigSettings->endGroup();\n\t\tconnect(configApp, &QApplication::aboutToQuit,\n\t\t\tthis, &ConfigList::saveSettings);\n\t}\n\n\tshowColumn(promptColIdx);\n\n\tsetItemDelegate(new ConfigItemDelegate(this));\n\n\tallLists.append(this);\n\n\treinit();\n}\n\nConfigList::~ConfigList()\n{\n\tallLists.removeOne(this);\n}\n\nbool ConfigList::menuSkip(struct menu *menu)\n{\n\tif (optMode == normalOpt && menu_is_visible(menu))\n\t\treturn false;\n\tif (optMode == promptOpt && menu_has_prompt(menu))\n\t\treturn false;\n\tif (optMode == allOpt)\n\t\treturn false;\n\treturn true;\n}\n\nvoid ConfigList::reinit(void)\n{\n\thideColumn(nameColIdx);\n\n\tif (showName)\n\t\tshowColumn(nameColIdx);\n\n\tupdateListAll();\n}\n\nvoid ConfigList::setOptionMode(QAction *action)\n{\n\tif (action == showNormalAction)\n\t\toptMode = normalOpt;\n\telse if (action == showAllAction)\n\t\toptMode = allOpt;\n\telse\n\t\toptMode = promptOpt;\n\n\tupdateListAll();\n}\n\nvoid ConfigList::saveSettings(void)\n{\n\tif (!objectName().isEmpty()) {\n\t\tconfigSettings->beginGroup(objectName());\n\t\tconfigSettings->setValue(\"/showName\", showName);\n\t\tconfigSettings->setValue(\"/optionMode\", (int)optMode);\n\t\tconfigSettings->endGroup();\n\t}\n}\n\nConfigItem* ConfigList::findConfigItem(struct menu *menu)\n{\n\tConfigItem* item = (ConfigItem*)menu->data;\n\n\tfor (; item; item = item->nextItem) {\n\t\tif (this == item->listView())\n\t\t\tbreak;\n\t}\n\n\treturn item;\n}\n\nvoid ConfigList::updateSelection(void)\n{\n\tstruct menu *menu;\n\tenum prop_type type;\n\n\tif (selectedItems().count() == 0)\n\t\treturn;\n\n\tConfigItem* item = (ConfigItem*)selectedItems().first();\n\tif (!item)\n\t\treturn;\n\n\tmenu = item->menu;\n\temit menuChanged(menu);\n\tif (!menu)\n\t\treturn;\n\ttype = menu->prompt ? menu->prompt->type : P_UNKNOWN;\n\tif (mode == menuMode && type == P_MENU)\n\t\temit menuSelected(menu);\n}\n\nvoid ConfigList::updateList()\n{\n\tConfigItem* last = 0;\n\tConfigItem *item;\n\n\tif (!rootEntry) {\n\t\tif (mode != listMode)\n\t\t\tgoto update;\n\t\tQTreeWidgetItemIterator it(this);\n\n\t\twhile (*it) {\n\t\t\titem = (ConfigItem*)(*it);\n\t\t\tif (!item->menu)\n\t\t\t\tcontinue;\n\t\t\titem->testUpdateMenu(menu_is_visible(item->menu));\n\n\t\t\t++it;\n\t\t}\n\t\treturn;\n\t}\n\n\tif (rootEntry != &rootmenu && (mode == singleMode ||\n\t    (mode == symbolMode && rootEntry->parent != &rootmenu))) {\n\t\titem = (ConfigItem *)topLevelItem(0);\n\t\tif (!item)\n\t\t\titem = new ConfigItem(this, 0, true);\n\t\tlast = item;\n\t}\n\tif ((mode == singleMode || (mode == symbolMode && !(rootEntry->flags & MENU_ROOT))) &&\n\t    rootEntry->sym && rootEntry->prompt) {\n\t\titem = last ? last->nextSibling() : nullptr;\n\t\tif (!item)\n\t\t\titem = new ConfigItem(this, last, rootEntry, true);\n\t\telse\n\t\t\titem->testUpdateMenu(true);\n\n\t\tupdateMenuList(item, rootEntry);\n\t\tupdate();\n\t\tresizeColumnToContents(0);\n\t\treturn;\n\t}\nupdate:\n\tupdateMenuList(rootEntry);\n\tupdate();\n\tresizeColumnToContents(0);\n}\n\nvoid ConfigList::updateListForAll()\n{\n\tQListIterator<ConfigList *> it(allLists);\n\n\twhile (it.hasNext()) {\n\t\tConfigList *list = it.next();\n\n\t\tlist->updateList();\n\t}\n}\n\nvoid ConfigList::updateListAllForAll()\n{\n\tQListIterator<ConfigList *> it(allLists);\n\n\twhile (it.hasNext()) {\n\t\tConfigList *list = it.next();\n\n\t\tlist->updateList();\n\t}\n}\n\nvoid ConfigList::setValue(ConfigItem* item, tristate val)\n{\n\tstruct symbol* sym;\n\tint type;\n\ttristate oldval;\n\n\tsym = item->menu ? item->menu->sym : 0;\n\tif (!sym)\n\t\treturn;\n\n\ttype = sym_get_type(sym);\n\tswitch (type) {\n\tcase S_BOOLEAN:\n\tcase S_TRISTATE:\n\t\toldval = sym_get_tristate_value(sym);\n\n\t\tif (!sym_set_tristate_value(sym, val))\n\t\t\treturn;\n\t\tif (oldval == no && item->menu->list)\n\t\t\titem->setExpanded(true);\n\t\tConfigList::updateListForAll();\n\t\tbreak;\n\t}\n}\n\nvoid ConfigList::changeValue(ConfigItem* item)\n{\n\tstruct symbol* sym;\n\tstruct menu* menu;\n\tint type, oldexpr, newexpr;\n\n\tmenu = item->menu;\n\tif (!menu)\n\t\treturn;\n\tsym = menu->sym;\n\tif (!sym) {\n\t\tif (item->menu->list)\n\t\t\titem->setExpanded(!item->isExpanded());\n\t\treturn;\n\t}\n\n\ttype = sym_get_type(sym);\n\tswitch (type) {\n\tcase S_BOOLEAN:\n\tcase S_TRISTATE:\n\t\toldexpr = sym_get_tristate_value(sym);\n\t\tnewexpr = sym_toggle_tristate_value(sym);\n\t\tif (item->menu->list) {\n\t\t\tif (oldexpr == newexpr)\n\t\t\t\titem->setExpanded(!item->isExpanded());\n\t\t\telse if (oldexpr == no)\n\t\t\t\titem->setExpanded(true);\n\t\t}\n\t\tif (oldexpr != newexpr)\n\t\t\tConfigList::updateListForAll();\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n}\n\nvoid ConfigList::setRootMenu(struct menu *menu)\n{\n\tenum prop_type type;\n\n\tif (rootEntry == menu)\n\t\treturn;\n\ttype = menu && menu->prompt ? menu->prompt->type : P_UNKNOWN;\n\tif (type != P_MENU)\n\t\treturn;\n\tupdateMenuList(0);\n\trootEntry = menu;\n\tupdateListAll();\n\tif (currentItem()) {\n\t\tsetSelected(currentItem(), hasFocus());\n\t\tscrollToItem(currentItem());\n\t}\n}\n\nvoid ConfigList::setParentMenu(void)\n{\n\tConfigItem* item;\n\tstruct menu *oldroot;\n\n\toldroot = rootEntry;\n\tif (rootEntry == &rootmenu)\n\t\treturn;\n\tsetRootMenu(menu_get_parent_menu(rootEntry->parent));\n\n\tQTreeWidgetItemIterator it(this);\n\twhile (*it) {\n\t\titem = (ConfigItem *)(*it);\n\t\tif (item->menu == oldroot) {\n\t\t\tsetCurrentItem(item);\n\t\t\tscrollToItem(item);\n\t\t\tbreak;\n\t\t}\n\n\t\t++it;\n\t}\n}\n\n/*\n * update all the children of a menu entry\n *   removes/adds the entries from the parent widget as necessary\n *\n * parent: either the menu list widget or a menu entry widget\n * menu: entry to be updated\n */\nvoid ConfigList::updateMenuList(ConfigItem *parent, struct menu* menu)\n{\n\tstruct menu* child;\n\tConfigItem* item;\n\tConfigItem* last;\n\tbool visible;\n\tenum prop_type type;\n\n\tif (!menu) {\n\t\twhile (parent->childCount() > 0)\n\t\t{\n\t\t\tdelete parent->takeChild(0);\n\t\t}\n\n\t\treturn;\n\t}\n\n\tlast = parent->firstChild();\n\tif (last && !last->goParent)\n\t\tlast = 0;\n\tfor (child = menu->list; child; child = child->next) {\n\t\titem = last ? last->nextSibling() : parent->firstChild();\n\t\ttype = child->prompt ? child->prompt->type : P_UNKNOWN;\n\n\t\tswitch (mode) {\n\t\tcase menuMode:\n\t\t\tif (!(child->flags & MENU_ROOT))\n\t\t\t\tgoto hide;\n\t\t\tbreak;\n\t\tcase symbolMode:\n\t\t\tif (child->flags & MENU_ROOT)\n\t\t\t\tgoto hide;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tbreak;\n\t\t}\n\n\t\tvisible = menu_is_visible(child);\n\t\tif (!menuSkip(child)) {\n\t\t\tif (!child->sym && !child->list && !child->prompt)\n\t\t\t\tcontinue;\n\t\t\tif (!item || item->menu != child)\n\t\t\t\titem = new ConfigItem(parent, last, child, visible);\n\t\t\telse\n\t\t\t\titem->testUpdateMenu(visible);\n\n\t\t\tif (mode == fullMode || mode == menuMode || type != P_MENU)\n\t\t\t\tupdateMenuList(item, child);\n\t\t\telse\n\t\t\t\tupdateMenuList(item, 0);\n\t\t\tlast = item;\n\t\t\tcontinue;\n\t\t}\nhide:\n\t\tif (item && item->menu == child) {\n\t\t\tlast = parent->firstChild();\n\t\t\tif (last == item)\n\t\t\t\tlast = 0;\n\t\t\telse while (last->nextSibling() != item)\n\t\t\t\tlast = last->nextSibling();\n\t\t\tdelete item;\n\t\t}\n\t}\n}\n\nvoid ConfigList::updateMenuList(struct menu *menu)\n{\n\tstruct menu* child;\n\tConfigItem* item;\n\tConfigItem* last;\n\tbool visible;\n\tenum prop_type type;\n\n\tif (!menu) {\n\t\twhile (topLevelItemCount() > 0)\n\t\t{\n\t\t\tdelete takeTopLevelItem(0);\n\t\t}\n\n\t\treturn;\n\t}\n\n\tlast = (ConfigItem *)topLevelItem(0);\n\tif (last && !last->goParent)\n\t\tlast = 0;\n\tfor (child = menu->list; child; child = child->next) {\n\t\titem = last ? last->nextSibling() : (ConfigItem *)topLevelItem(0);\n\t\ttype = child->prompt ? child->prompt->type : P_UNKNOWN;\n\n\t\tswitch (mode) {\n\t\tcase menuMode:\n\t\t\tif (!(child->flags & MENU_ROOT))\n\t\t\t\tgoto hide;\n\t\t\tbreak;\n\t\tcase symbolMode:\n\t\t\tif (child->flags & MENU_ROOT)\n\t\t\t\tgoto hide;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tbreak;\n\t\t}\n\n\t\tvisible = menu_is_visible(child);\n\t\tif (!menuSkip(child)) {\n\t\t\tif (!child->sym && !child->list && !child->prompt)\n\t\t\t\tcontinue;\n\t\t\tif (!item || item->menu != child)\n\t\t\t\titem = new ConfigItem(this, last, child, visible);\n\t\t\telse\n\t\t\t\titem->testUpdateMenu(visible);\n\n\t\t\tif (mode == fullMode || mode == menuMode || type != P_MENU)\n\t\t\t\tupdateMenuList(item, child);\n\t\t\telse\n\t\t\t\tupdateMenuList(item, 0);\n\t\t\tlast = item;\n\t\t\tcontinue;\n\t\t}\nhide:\n\t\tif (item && item->menu == child) {\n\t\t\tlast = (ConfigItem *)topLevelItem(0);\n\t\t\tif (last == item)\n\t\t\t\tlast = 0;\n\t\t\telse while (last->nextSibling() != item)\n\t\t\t\tlast = last->nextSibling();\n\t\t\tdelete item;\n\t\t}\n\t}\n}\n\nvoid ConfigList::keyPressEvent(QKeyEvent* ev)\n{\n\tQTreeWidgetItem* i = currentItem();\n\tConfigItem* item;\n\tstruct menu *menu;\n\tenum prop_type type;\n\n\tif (ev->key() == Qt::Key_Escape && mode != fullMode && mode != listMode) {\n\t\temit parentSelected();\n\t\tev->accept();\n\t\treturn;\n\t}\n\n\tif (!i) {\n\t\tParent::keyPressEvent(ev);\n\t\treturn;\n\t}\n\titem = (ConfigItem*)i;\n\n\tswitch (ev->key()) {\n\tcase Qt::Key_Return:\n\tcase Qt::Key_Enter:\n\t\tif (item->goParent) {\n\t\t\temit parentSelected();\n\t\t\tbreak;\n\t\t}\n\t\tmenu = item->menu;\n\t\tif (!menu)\n\t\t\tbreak;\n\t\ttype = menu->prompt ? menu->prompt->type : P_UNKNOWN;\n\t\tif (type == P_MENU && rootEntry != menu &&\n\t\t    mode != fullMode && mode != menuMode) {\n\t\t\tif (mode == menuMode)\n\t\t\t\temit menuSelected(menu);\n\t\t\telse\n\t\t\t\temit itemSelected(menu);\n\t\t\tbreak;\n\t\t}\n\tcase Qt::Key_Space:\n\t\tchangeValue(item);\n\t\tbreak;\n\tcase Qt::Key_N:\n\t\tsetValue(item, no);\n\t\tbreak;\n\tcase Qt::Key_M:\n\t\tsetValue(item, mod);\n\t\tbreak;\n\tcase Qt::Key_Y:\n\t\tsetValue(item, yes);\n\t\tbreak;\n\tdefault:\n\t\tParent::keyPressEvent(ev);\n\t\treturn;\n\t}\n\tev->accept();\n}\n\nvoid ConfigList::mousePressEvent(QMouseEvent* e)\n{\n\t//QPoint p(contentsToViewport(e->pos()));\n\t//printf(\"contentsMousePressEvent: %d,%d\\n\", p.x(), p.y());\n\tParent::mousePressEvent(e);\n}\n\nvoid ConfigList::mouseReleaseEvent(QMouseEvent* e)\n{\n\tQPoint p = e->pos();\n\tConfigItem* item = (ConfigItem*)itemAt(p);\n\tstruct menu *menu;\n\tenum prop_type ptype;\n\tQIcon icon;\n\tint idx, x;\n\n\tif (!item)\n\t\tgoto skip;\n\n\tmenu = item->menu;\n\tx = header()->offset() + p.x();\n\tidx = header()->logicalIndexAt(x);\n\tswitch (idx) {\n\tcase promptColIdx:\n\t\ticon = item->icon(promptColIdx);\n\t\tif (!icon.isNull()) {\n\t\t\tint off = header()->sectionPosition(0) + visualRect(indexAt(p)).x() + 4; // 4 is Hardcoded image offset. There might be a way to do it properly.\n\t\t\tif (x >= off && x < off + icon.availableSizes().first().width()) {\n\t\t\t\tif (item->goParent) {\n\t\t\t\t\temit parentSelected();\n\t\t\t\t\tbreak;\n\t\t\t\t} else if (!menu)\n\t\t\t\t\tbreak;\n\t\t\t\tptype = menu->prompt ? menu->prompt->type : P_UNKNOWN;\n\t\t\t\tif (ptype == P_MENU && rootEntry != menu &&\n\t\t\t\t    mode != fullMode && mode != menuMode &&\n                                    mode != listMode)\n\t\t\t\t\temit menuSelected(menu);\n\t\t\t\telse\n\t\t\t\t\tchangeValue(item);\n\t\t\t}\n\t\t}\n\t\tbreak;\n\tcase dataColIdx:\n\t\tchangeValue(item);\n\t\tbreak;\n\t}\n\nskip:\n\t//printf(\"contentsMouseReleaseEvent: %d,%d\\n\", p.x(), p.y());\n\tParent::mouseReleaseEvent(e);\n}\n\nvoid ConfigList::mouseMoveEvent(QMouseEvent* e)\n{\n\t//QPoint p(contentsToViewport(e->pos()));\n\t//printf(\"contentsMouseMoveEvent: %d,%d\\n\", p.x(), p.y());\n\tParent::mouseMoveEvent(e);\n}\n\nvoid ConfigList::mouseDoubleClickEvent(QMouseEvent* e)\n{\n\tQPoint p = e->pos();\n\tConfigItem* item = (ConfigItem*)itemAt(p);\n\tstruct menu *menu;\n\tenum prop_type ptype;\n\n\tif (!item)\n\t\tgoto skip;\n\tif (item->goParent) {\n\t\temit parentSelected();\n\t\tgoto skip;\n\t}\n\tmenu = item->menu;\n\tif (!menu)\n\t\tgoto skip;\n\tptype = menu->prompt ? menu->prompt->type : P_UNKNOWN;\n\tif (ptype == P_MENU && mode != listMode) {\n\t\tif (mode == singleMode)\n\t\t\temit itemSelected(menu);\n\t\telse if (mode == symbolMode)\n\t\t\temit menuSelected(menu);\n\t} else if (menu->sym)\n\t\tchangeValue(item);\n\nskip:\n\t//printf(\"contentsMouseDoubleClickEvent: %d,%d\\n\", p.x(), p.y());\n\tParent::mouseDoubleClickEvent(e);\n}\n\nvoid ConfigList::focusInEvent(QFocusEvent *e)\n{\n\tstruct menu *menu = NULL;\n\n\tParent::focusInEvent(e);\n\n\tConfigItem* item = (ConfigItem *)currentItem();\n\tif (item) {\n\t\tsetSelected(item, true);\n\t\tmenu = item->menu;\n\t}\n\temit gotFocus(menu);\n}\n\nvoid ConfigList::contextMenuEvent(QContextMenuEvent *e)\n{\n\tif (!headerPopup) {\n\t\tQAction *action;\n\n\t\theaderPopup = new QMenu(this);\n\t\taction = new QAction(\"Show Name\", this);\n\t\taction->setCheckable(true);\n\t\tconnect(action, &QAction::toggled,\n\t\t\tthis, &ConfigList::setShowName);\n\t\tconnect(this, &ConfigList::showNameChanged,\n\t\t\taction, &QAction::setChecked);\n\t\taction->setChecked(showName);\n\t\theaderPopup->addAction(action);\n\t}\n\n\theaderPopup->exec(e->globalPos());\n\te->accept();\n}\n\nvoid ConfigList::setShowName(bool on)\n{\n\tif (showName == on)\n\t\treturn;\n\n\tshowName = on;\n\treinit();\n\temit showNameChanged(on);\n}\n\nQList<ConfigList *> ConfigList::allLists;\nQAction *ConfigList::showNormalAction;\nQAction *ConfigList::showAllAction;\nQAction *ConfigList::showPromptAction;\n\nvoid ConfigList::setAllOpen(bool open)\n{\n\tQTreeWidgetItemIterator it(this);\n\n\twhile (*it) {\n\t\t(*it)->setExpanded(open);\n\n\t\t++it;\n\t}\n}\n\nConfigInfoView::ConfigInfoView(QWidget* parent, const char *name)\n\t: Parent(parent), sym(0), _menu(0)\n{\n\tsetObjectName(name);\n\tsetOpenLinks(false);\n\n\tif (!objectName().isEmpty()) {\n\t\tconfigSettings->beginGroup(objectName());\n\t\tsetShowDebug(configSettings->value(\"/showDebug\", false).toBool());\n\t\tconfigSettings->endGroup();\n\t\tconnect(configApp, &QApplication::aboutToQuit,\n\t\t\tthis, &ConfigInfoView::saveSettings);\n\t}\n\n\tcontextMenu = createStandardContextMenu();\n\tQAction *action = new QAction(\"Show Debug Info\", contextMenu);\n\n\taction->setCheckable(true);\n\tconnect(action, &QAction::toggled,\n\t\tthis, &ConfigInfoView::setShowDebug);\n\tconnect(this, &ConfigInfoView::showDebugChanged,\n\t\taction, &QAction::setChecked);\n\taction->setChecked(showDebug());\n\tcontextMenu->addSeparator();\n\tcontextMenu->addAction(action);\n}\n\nvoid ConfigInfoView::saveSettings(void)\n{\n\tif (!objectName().isEmpty()) {\n\t\tconfigSettings->beginGroup(objectName());\n\t\tconfigSettings->setValue(\"/showDebug\", showDebug());\n\t\tconfigSettings->endGroup();\n\t}\n}\n\nvoid ConfigInfoView::setShowDebug(bool b)\n{\n\tif (_showDebug != b) {\n\t\t_showDebug = b;\n\t\tif (_menu)\n\t\t\tmenuInfo();\n\t\telse if (sym)\n\t\t\tsymbolInfo();\n\t\temit showDebugChanged(b);\n\t}\n}\n\nvoid ConfigInfoView::setInfo(struct menu *m)\n{\n\tif (_menu == m)\n\t\treturn;\n\t_menu = m;\n\tsym = NULL;\n\tif (!_menu)\n\t\tclear();\n\telse\n\t\tmenuInfo();\n}\n\nvoid ConfigInfoView::symbolInfo(void)\n{\n\tQString str;\n\n\tstr += \"<big>Symbol: <b>\";\n\tstr += print_filter(sym->name);\n\tstr += \"</b></big><br><br>value: \";\n\tstr += print_filter(sym_get_string_value(sym));\n\tstr += \"<br>visibility: \";\n\tstr += sym->visible == yes ? \"y\" : sym->visible == mod ? \"m\" : \"n\";\n\tstr += \"<br>\";\n\tstr += debug_info(sym);\n\n\tsetText(str);\n}\n\nvoid ConfigInfoView::menuInfo(void)\n{\n\tstruct symbol* sym;\n\tQString info;\n\tQTextStream stream(&info);\n\n\tsym = _menu->sym;\n\tif (sym) {\n\t\tif (_menu->prompt) {\n\t\t\tstream << \"<big><b>\";\n\t\t\tstream << print_filter(_menu->prompt->text);\n\t\t\tstream << \"</b></big>\";\n\t\t\tif (sym->name) {\n\t\t\t\tstream << \" (\";\n\t\t\t\tif (showDebug())\n\t\t\t\t\tstream << \"<a href=\\\"s\" << sym->name << \"\\\">\";\n\t\t\t\tstream << print_filter(sym->name);\n\t\t\t\tif (showDebug())\n\t\t\t\t\tstream << \"</a>\";\n\t\t\t\tstream << \")\";\n\t\t\t}\n\t\t} else if (sym->name) {\n\t\t\tstream << \"<big><b>\";\n\t\t\tif (showDebug())\n\t\t\t\tstream << \"<a href=\\\"s\" << sym->name << \"\\\">\";\n\t\t\tstream << print_filter(sym->name);\n\t\t\tif (showDebug())\n\t\t\t\tstream << \"</a>\";\n\t\t\tstream << \"</b></big>\";\n\t\t}\n\t\tstream << \"<br><br>\";\n\n\t\tif (showDebug())\n\t\t\tstream << debug_info(sym);\n\n\t\tstruct gstr help_gstr = str_new();\n\n\t\tmenu_get_ext_help(_menu, &help_gstr);\n\t\tstream << print_filter(str_get(&help_gstr));\n\t\tstr_free(&help_gstr);\n\t} else if (_menu->prompt) {\n\t\tstream << \"<big><b>\";\n\t\tstream << print_filter(_menu->prompt->text);\n\t\tstream << \"</b></big><br><br>\";\n\t\tif (showDebug()) {\n\t\t\tif (_menu->prompt->visible.expr) {\n\t\t\t\tstream << \"&nbsp;&nbsp;dep: \";\n\t\t\t\texpr_print(_menu->prompt->visible.expr,\n\t\t\t\t\t   expr_print_help, &stream, E_NONE);\n\t\t\t\tstream << \"<br><br>\";\n\t\t\t}\n\n\t\t\tstream << \"defined at \" << _menu->file->name << \":\"\n\t\t\t       << _menu->lineno << \"<br><br>\";\n\t\t}\n\t}\n\n\tsetText(info);\n}\n\nQString ConfigInfoView::debug_info(struct symbol *sym)\n{\n\tQString debug;\n\tQTextStream stream(&debug);\n\n\tstream << \"type: \";\n\tstream << print_filter(sym_type_name(sym->type));\n\tif (sym_is_choice(sym))\n\t\tstream << \" (choice)\";\n\tdebug += \"<br>\";\n\tif (sym->rev_dep.expr) {\n\t\tstream << \"reverse dep: \";\n\t\texpr_print(sym->rev_dep.expr, expr_print_help, &stream, E_NONE);\n\t\tstream << \"<br>\";\n\t}\n\tfor (struct property *prop = sym->prop; prop; prop = prop->next) {\n\t\tswitch (prop->type) {\n\t\tcase P_PROMPT:\n\t\tcase P_MENU:\n\t\t\tstream << \"prompt: <a href=\\\"m\" << sym->name << \"\\\">\";\n\t\t\tstream << print_filter(prop->text);\n\t\t\tstream << \"</a><br>\";\n\t\t\tbreak;\n\t\tcase P_DEFAULT:\n\t\tcase P_SELECT:\n\t\tcase P_RANGE:\n\t\tcase P_COMMENT:\n\t\tcase P_IMPLY:\n\t\tcase P_SYMBOL:\n\t\t\tstream << prop_get_type_name(prop->type);\n\t\t\tstream << \": \";\n\t\t\texpr_print(prop->expr, expr_print_help,\n\t\t\t\t   &stream, E_NONE);\n\t\t\tstream << \"<br>\";\n\t\t\tbreak;\n\t\tcase P_CHOICE:\n\t\t\tif (sym_is_choice(sym)) {\n\t\t\t\tstream << \"choice: \";\n\t\t\t\texpr_print(prop->expr, expr_print_help,\n\t\t\t\t\t   &stream, E_NONE);\n\t\t\t\tstream << \"<br>\";\n\t\t\t}\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tstream << \"unknown property: \";\n\t\t\tstream << prop_get_type_name(prop->type);\n\t\t\tstream << \"<br>\";\n\t\t}\n\t\tif (prop->visible.expr) {\n\t\t\tstream << \"&nbsp;&nbsp;&nbsp;&nbsp;dep: \";\n\t\t\texpr_print(prop->visible.expr, expr_print_help,\n\t\t\t\t   &stream, E_NONE);\n\t\t\tstream << \"<br>\";\n\t\t}\n\t}\n\tstream << \"<br>\";\n\n\treturn debug;\n}\n\nQString ConfigInfoView::print_filter(const QString &str)\n{\n\tQRegExp re(\"[<>&\\\"\\\\n]\");\n\tQString res = str;\n\tfor (int i = 0; (i = res.indexOf(re, i)) >= 0;) {\n\t\tswitch (res[i].toLatin1()) {\n\t\tcase '<':\n\t\t\tres.replace(i, 1, \"&lt;\");\n\t\t\ti += 4;\n\t\t\tbreak;\n\t\tcase '>':\n\t\t\tres.replace(i, 1, \"&gt;\");\n\t\t\ti += 4;\n\t\t\tbreak;\n\t\tcase '&':\n\t\t\tres.replace(i, 1, \"&amp;\");\n\t\t\ti += 5;\n\t\t\tbreak;\n\t\tcase '\"':\n\t\t\tres.replace(i, 1, \"&quot;\");\n\t\t\ti += 6;\n\t\t\tbreak;\n\t\tcase '\\n':\n\t\t\tres.replace(i, 1, \"<br>\");\n\t\t\ti += 4;\n\t\t\tbreak;\n\t\t}\n\t}\n\treturn res;\n}\n\nvoid ConfigInfoView::expr_print_help(void *data, struct symbol *sym, const char *str)\n{\n\tQTextStream *stream = reinterpret_cast<QTextStream *>(data);\n\n\tif (sym && sym->name && !(sym->flags & SYMBOL_CONST)) {\n\t\t*stream << \"<a href=\\\"s\" << sym->name << \"\\\">\";\n\t\t*stream << print_filter(str);\n\t\t*stream << \"</a>\";\n\t} else {\n\t\t*stream << print_filter(str);\n\t}\n}\n\nvoid ConfigInfoView::clicked(const QUrl &url)\n{\n\tQByteArray str = url.toEncoded();\n\tconst std::size_t count = str.size();\n\tchar *data = new char[count + 1];\n\tstruct symbol **result;\n\tstruct menu *m = NULL;\n\n\tif (count < 1) {\n\t\tdelete[] data;\n\t\treturn;\n\t}\n\n\tmemcpy(data, str.constData(), count);\n\tdata[count] = '\\0';\n\n\t/* Seek for exact match */\n\tdata[0] = '^';\n\tstrcat(data, \"$\");\n\tresult = sym_re_search(data);\n\tif (!result) {\n\t\tdelete[] data;\n\t\treturn;\n\t}\n\n\tsym = *result;\n\n\t/* Seek for the menu which holds the symbol */\n\tfor (struct property *prop = sym->prop; prop; prop = prop->next) {\n\t\t    if (prop->type != P_PROMPT && prop->type != P_MENU)\n\t\t\t    continue;\n\t\t    m = prop->menu;\n\t\t    break;\n\t}\n\n\tif (!m) {\n\t\t/* Symbol is not visible as a menu */\n\t\tsymbolInfo();\n\t\temit showDebugChanged(true);\n\t} else {\n\t\temit menuSelected(m);\n\t}\n\n\tfree(result);\n\tdelete[] data;\n}\n\nvoid ConfigInfoView::contextMenuEvent(QContextMenuEvent *event)\n{\n\tcontextMenu->popup(event->globalPos());\n\tevent->accept();\n}\n\nConfigSearchWindow::ConfigSearchWindow(ConfigMainWindow *parent)\n\t: Parent(parent), result(NULL)\n{\n\tsetObjectName(\"search\");\n\tsetWindowTitle(\"Search Config\");\n\n\tQVBoxLayout* layout1 = new QVBoxLayout(this);\n\tlayout1->setContentsMargins(11, 11, 11, 11);\n\tlayout1->setSpacing(6);\n\n\tQHBoxLayout* layout2 = new QHBoxLayout();\n\tlayout2->setContentsMargins(0, 0, 0, 0);\n\tlayout2->setSpacing(6);\n\tlayout2->addWidget(new QLabel(\"Find:\", this));\n\teditField = new QLineEdit(this);\n\tconnect(editField, &QLineEdit::returnPressed,\n\t\tthis, &ConfigSearchWindow::search);\n\tlayout2->addWidget(editField);\n\tsearchButton = new QPushButton(\"Search\", this);\n\tsearchButton->setAutoDefault(false);\n\tconnect(searchButton, &QPushButton::clicked,\n\t\tthis, &ConfigSearchWindow::search);\n\tlayout2->addWidget(searchButton);\n\tlayout1->addLayout(layout2);\n\n\tsplit = new QSplitter(this);\n\tsplit->setOrientation(Qt::Vertical);\n\tlist = new ConfigList(split, \"search\");\n\tlist->mode = listMode;\n\tinfo = new ConfigInfoView(split, \"search\");\n\tconnect(list, &ConfigList::menuChanged,\n\t\tinfo, &ConfigInfoView::setInfo);\n\tconnect(list, &ConfigList::menuChanged,\n\t\tparent, &ConfigMainWindow::setMenuLink);\n\n\tlayout1->addWidget(split);\n\n\tQVariant x, y;\n\tint width, height;\n\tbool ok;\n\n\tconfigSettings->beginGroup(\"search\");\n\twidth = configSettings->value(\"/window width\", parent->width() / 2).toInt();\n\theight = configSettings->value(\"/window height\", parent->height() / 2).toInt();\n\tresize(width, height);\n\tx = configSettings->value(\"/window x\");\n\ty = configSettings->value(\"/window y\");\n\tif (x.isValid() && y.isValid())\n\t\tmove(x.toInt(), y.toInt());\n\tQList<int> sizes = configSettings->readSizes(\"/split\", &ok);\n\tif (ok)\n\t\tsplit->setSizes(sizes);\n\tconfigSettings->endGroup();\n\tconnect(configApp, &QApplication::aboutToQuit,\n\t\tthis, &ConfigSearchWindow::saveSettings);\n}\n\nvoid ConfigSearchWindow::saveSettings(void)\n{\n\tif (!objectName().isEmpty()) {\n\t\tconfigSettings->beginGroup(objectName());\n\t\tconfigSettings->setValue(\"/window x\", pos().x());\n\t\tconfigSettings->setValue(\"/window y\", pos().y());\n\t\tconfigSettings->setValue(\"/window width\", size().width());\n\t\tconfigSettings->setValue(\"/window height\", size().height());\n\t\tconfigSettings->writeSizes(\"/split\", split->sizes());\n\t\tconfigSettings->endGroup();\n\t}\n}\n\nvoid ConfigSearchWindow::search(void)\n{\n\tstruct symbol **p;\n\tstruct property *prop;\n\tConfigItem *lastItem = NULL;\n\n\tfree(result);\n\tlist->clear();\n\tinfo->clear();\n\n\tresult = sym_re_search(editField->text().toLatin1());\n\tif (!result)\n\t\treturn;\n\tfor (p = result; *p; p++) {\n\t\tfor_all_prompts((*p), prop)\n\t\t\tlastItem = new ConfigItem(list, lastItem, prop->menu,\n\t\t\t\t\t\t  menu_is_visible(prop->menu));\n\t}\n}\n\n/*\n * Construct the complete config widget\n */\nConfigMainWindow::ConfigMainWindow(void)\n\t: searchWindow(0)\n{\n\tbool ok = true;\n\tQVariant x, y;\n\tint width, height;\n\tchar title[256];\n\n\tQDesktopWidget *d = configApp->desktop();\n\tsnprintf(title, sizeof(title), \"%s%s\",\n\t\trootmenu.prompt->text,\n\t\t\"\"\n\t\t);\n\tsetWindowTitle(title);\n\n\twidth = configSettings->value(\"/window width\", d->width() - 64).toInt();\n\theight = configSettings->value(\"/window height\", d->height() - 64).toInt();\n\tresize(width, height);\n\tx = configSettings->value(\"/window x\");\n\ty = configSettings->value(\"/window y\");\n\tif ((x.isValid())&&(y.isValid()))\n\t\tmove(x.toInt(), y.toInt());\n\n\t// set up icons\n\tConfigItem::symbolYesIcon = QIcon(QPixmap(xpm_symbol_yes));\n\tConfigItem::symbolModIcon = QIcon(QPixmap(xpm_symbol_mod));\n\tConfigItem::symbolNoIcon = QIcon(QPixmap(xpm_symbol_no));\n\tConfigItem::choiceYesIcon = QIcon(QPixmap(xpm_choice_yes));\n\tConfigItem::choiceNoIcon = QIcon(QPixmap(xpm_choice_no));\n\tConfigItem::menuIcon = QIcon(QPixmap(xpm_menu));\n\tConfigItem::menubackIcon = QIcon(QPixmap(xpm_menuback));\n\n\tQWidget *widget = new QWidget(this);\n\tQVBoxLayout *layout = new QVBoxLayout(widget);\n\tsetCentralWidget(widget);\n\n\tsplit1 = new QSplitter(widget);\n\tsplit1->setOrientation(Qt::Horizontal);\n\tsplit1->setChildrenCollapsible(false);\n\n\tmenuList = new ConfigList(widget, \"menu\");\n\n\tsplit2 = new QSplitter(widget);\n\tsplit2->setChildrenCollapsible(false);\n\tsplit2->setOrientation(Qt::Vertical);\n\n\t// create config tree\n\tconfigList = new ConfigList(widget, \"config\");\n\n\thelpText = new ConfigInfoView(widget, \"help\");\n\n\tlayout->addWidget(split2);\n\tsplit2->addWidget(split1);\n\tsplit1->addWidget(configList);\n\tsplit1->addWidget(menuList);\n\tsplit2->addWidget(helpText);\n\n\tsetTabOrder(configList, helpText);\n\tconfigList->setFocus();\n\n\tbackAction = new QAction(QPixmap(xpm_back), \"Back\", this);\n\tconnect(backAction, &QAction::triggered,\n\t\tthis, &ConfigMainWindow::goBack);\n\n\tQAction *quitAction = new QAction(\"&Quit\", this);\n\tquitAction->setShortcut(Qt::CTRL + Qt::Key_Q);\n\tconnect(quitAction, &QAction::triggered,\n\t\tthis, &ConfigMainWindow::close);\n\n\tQAction *loadAction = new QAction(QPixmap(xpm_load), \"&Load\", this);\n\tloadAction->setShortcut(Qt::CTRL + Qt::Key_L);\n\tconnect(loadAction, &QAction::triggered,\n\t\tthis, &ConfigMainWindow::loadConfig);\n\n\tsaveAction = new QAction(QPixmap(xpm_save), \"&Save\", this);\n\tsaveAction->setShortcut(Qt::CTRL + Qt::Key_S);\n\tconnect(saveAction, &QAction::triggered,\n\t\tthis, &ConfigMainWindow::saveConfig);\n\n\tconf_set_changed_callback(conf_changed);\n\n\t// Set saveAction's initial state\n\tconf_changed();\n\tconfigname = xstrdup(conf_get_configname());\n\n\tQAction *saveAsAction = new QAction(\"Save &As...\", this);\n\tconnect(saveAsAction, &QAction::triggered,\n\t\tthis, &ConfigMainWindow::saveConfigAs);\n\tQAction *searchAction = new QAction(\"&Find\", this);\n\tsearchAction->setShortcut(Qt::CTRL + Qt::Key_F);\n\tconnect(searchAction, &QAction::triggered,\n\t\tthis, &ConfigMainWindow::searchConfig);\n\tsingleViewAction = new QAction(QPixmap(xpm_single_view), \"Single View\", this);\n\tsingleViewAction->setCheckable(true);\n\tconnect(singleViewAction, &QAction::triggered,\n\t\tthis, &ConfigMainWindow::showSingleView);\n\tsplitViewAction = new QAction(QPixmap(xpm_split_view), \"Split View\", this);\n\tsplitViewAction->setCheckable(true);\n\tconnect(splitViewAction, &QAction::triggered,\n\t\tthis, &ConfigMainWindow::showSplitView);\n\tfullViewAction = new QAction(QPixmap(xpm_tree_view), \"Full View\", this);\n\tfullViewAction->setCheckable(true);\n\tconnect(fullViewAction, &QAction::triggered,\n\t\tthis, &ConfigMainWindow::showFullView);\n\n\tQAction *showNameAction = new QAction(\"Show Name\", this);\n\t  showNameAction->setCheckable(true);\n\tconnect(showNameAction, &QAction::toggled,\n\t\tconfigList, &ConfigList::setShowName);\n\tshowNameAction->setChecked(configList->showName);\n\n\tQActionGroup *optGroup = new QActionGroup(this);\n\toptGroup->setExclusive(true);\n\tconnect(optGroup, &QActionGroup::triggered,\n\t\tconfigList, &ConfigList::setOptionMode);\n\tconnect(optGroup, &QActionGroup::triggered,\n\t\tmenuList, &ConfigList::setOptionMode);\n\n\tConfigList::showNormalAction = new QAction(\"Show Normal Options\", optGroup);\n\tConfigList::showNormalAction->setCheckable(true);\n\tConfigList::showAllAction = new QAction(\"Show All Options\", optGroup);\n\tConfigList::showAllAction->setCheckable(true);\n\tConfigList::showPromptAction = new QAction(\"Show Prompt Options\", optGroup);\n\tConfigList::showPromptAction->setCheckable(true);\n\n\tQAction *showDebugAction = new QAction(\"Show Debug Info\", this);\n\t  showDebugAction->setCheckable(true);\n\tconnect(showDebugAction, &QAction::toggled,\n\t\thelpText, &ConfigInfoView::setShowDebug);\n\t  showDebugAction->setChecked(helpText->showDebug());\n\n\tQAction *showIntroAction = new QAction(\"Introduction\", this);\n\tconnect(showIntroAction, &QAction::triggered,\n\t\tthis, &ConfigMainWindow::showIntro);\n\tQAction *showAboutAction = new QAction(\"About\", this);\n\tconnect(showAboutAction, &QAction::triggered,\n\t\tthis, &ConfigMainWindow::showAbout);\n\n\t// init tool bar\n\tQToolBar *toolBar = addToolBar(\"Tools\");\n\ttoolBar->addAction(backAction);\n\ttoolBar->addSeparator();\n\ttoolBar->addAction(loadAction);\n\ttoolBar->addAction(saveAction);\n\ttoolBar->addSeparator();\n\ttoolBar->addAction(singleViewAction);\n\ttoolBar->addAction(splitViewAction);\n\ttoolBar->addAction(fullViewAction);\n\n\t// create file menu\n\tQMenu *menu = menuBar()->addMenu(\"&File\");\n\tmenu->addAction(loadAction);\n\tmenu->addAction(saveAction);\n\tmenu->addAction(saveAsAction);\n\tmenu->addSeparator();\n\tmenu->addAction(quitAction);\n\n\t// create edit menu\n\tmenu = menuBar()->addMenu(\"&Edit\");\n\tmenu->addAction(searchAction);\n\n\t// create options menu\n\tmenu = menuBar()->addMenu(\"&Option\");\n\tmenu->addAction(showNameAction);\n\tmenu->addSeparator();\n\tmenu->addActions(optGroup->actions());\n\tmenu->addSeparator();\n\tmenu->addAction(showDebugAction);\n\n\t// create help menu\n\tmenu = menuBar()->addMenu(\"&Help\");\n\tmenu->addAction(showIntroAction);\n\tmenu->addAction(showAboutAction);\n\n\tconnect(helpText, &ConfigInfoView::anchorClicked,\n\t\thelpText, &ConfigInfoView::clicked);\n\n\tconnect(configList, &ConfigList::menuChanged,\n\t\thelpText, &ConfigInfoView::setInfo);\n\tconnect(configList, &ConfigList::menuSelected,\n\t\tthis, &ConfigMainWindow::changeMenu);\n\tconnect(configList, &ConfigList::itemSelected,\n\t\tthis, &ConfigMainWindow::changeItens);\n\tconnect(configList, &ConfigList::parentSelected,\n\t\tthis, &ConfigMainWindow::goBack);\n\tconnect(menuList, &ConfigList::menuChanged,\n\t\thelpText, &ConfigInfoView::setInfo);\n\tconnect(menuList, &ConfigList::menuSelected,\n\t\tthis, &ConfigMainWindow::changeMenu);\n\n\tconnect(configList, &ConfigList::gotFocus,\n\t\thelpText, &ConfigInfoView::setInfo);\n\tconnect(menuList, &ConfigList::gotFocus,\n\t\thelpText, &ConfigInfoView::setInfo);\n\tconnect(menuList, &ConfigList::gotFocus,\n\t\tthis, &ConfigMainWindow::listFocusChanged);\n\tconnect(helpText, &ConfigInfoView::menuSelected,\n\t\tthis, &ConfigMainWindow::setMenuLink);\n\n\tQString listMode = configSettings->value(\"/listMode\", \"symbol\").toString();\n\tif (listMode == \"single\")\n\t\tshowSingleView();\n\telse if (listMode == \"full\")\n\t\tshowFullView();\n\telse /*if (listMode == \"split\")*/\n\t\tshowSplitView();\n\n\t// UI setup done, restore splitter positions\n\tQList<int> sizes = configSettings->readSizes(\"/split1\", &ok);\n\tif (ok)\n\t\tsplit1->setSizes(sizes);\n\n\tsizes = configSettings->readSizes(\"/split2\", &ok);\n\tif (ok)\n\t\tsplit2->setSizes(sizes);\n}\n\nvoid ConfigMainWindow::loadConfig(void)\n{\n\tQString str;\n\tQByteArray ba;\n\tconst char *name;\n\n\tstr = QFileDialog::getOpenFileName(this, \"\", configname);\n\tif (str.isNull())\n\t\treturn;\n\n\tba = str.toLocal8Bit();\n\tname = ba.data();\n\n\tif (conf_read(name))\n\t\tQMessageBox::information(this, \"qconf\", \"Unable to load configuration!\");\n\n\tfree(configname);\n\tconfigname = xstrdup(name);\n\n\tConfigList::updateListAllForAll();\n}\n\nbool ConfigMainWindow::saveConfig(void)\n{\n\tif (conf_write(configname)) {\n\t\tQMessageBox::information(this, \"qconf\", \"Unable to save configuration!\");\n\t\treturn false;\n\t}\n\tconf_write_autoconf(0);\n\n\treturn true;\n}\n\nvoid ConfigMainWindow::saveConfigAs(void)\n{\n\tQString str;\n\tQByteArray ba;\n\tconst char *name;\n\n\tstr = QFileDialog::getSaveFileName(this, \"\", configname);\n\tif (str.isNull())\n\t\treturn;\n\n\tba = str.toLocal8Bit();\n\tname = ba.data();\n\n\tif (conf_write(name)) {\n\t\tQMessageBox::information(this, \"qconf\", \"Unable to save configuration!\");\n\t}\n\tconf_write_autoconf(0);\n\n\tfree(configname);\n\tconfigname = xstrdup(name);\n}\n\nvoid ConfigMainWindow::searchConfig(void)\n{\n\tif (!searchWindow)\n\t\tsearchWindow = new ConfigSearchWindow(this);\n\tsearchWindow->show();\n}\n\nvoid ConfigMainWindow::changeItens(struct menu *menu)\n{\n\tconfigList->setRootMenu(menu);\n}\n\nvoid ConfigMainWindow::changeMenu(struct menu *menu)\n{\n\tmenuList->setRootMenu(menu);\n}\n\nvoid ConfigMainWindow::setMenuLink(struct menu *menu)\n{\n\tstruct menu *parent;\n\tConfigList* list = NULL;\n\tConfigItem* item;\n\n\tif (configList->menuSkip(menu))\n\t\treturn;\n\n\tswitch (configList->mode) {\n\tcase singleMode:\n\t\tlist = configList;\n\t\tparent = menu_get_parent_menu(menu);\n\t\tif (!parent)\n\t\t\treturn;\n\t\tlist->setRootMenu(parent);\n\t\tbreak;\n\tcase menuMode:\n\t\tif (menu->flags & MENU_ROOT) {\n\t\t\tmenuList->setRootMenu(menu);\n\t\t\tconfigList->clearSelection();\n\t\t\tlist = configList;\n\t\t} else {\n\t\t\tparent = menu_get_parent_menu(menu->parent);\n\t\t\tif (!parent)\n\t\t\t\treturn;\n\n\t\t\t/* Select the config view */\n\t\t\titem = configList->findConfigItem(parent);\n\t\t\tif (item) {\n\t\t\t\tconfigList->setSelected(item, true);\n\t\t\t\tconfigList->scrollToItem(item);\n\t\t\t}\n\n\t\t\tmenuList->setRootMenu(parent);\n\t\t\tmenuList->clearSelection();\n\t\t\tlist = menuList;\n\t\t}\n\t\tbreak;\n\tcase fullMode:\n\t\tlist = configList;\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\n\tif (list) {\n\t\titem = list->findConfigItem(menu);\n\t\tif (item) {\n\t\t\tlist->setSelected(item, true);\n\t\t\tlist->scrollToItem(item);\n\t\t\tlist->setFocus();\n\t\t\thelpText->setInfo(menu);\n\t\t}\n\t}\n}\n\nvoid ConfigMainWindow::listFocusChanged(void)\n{\n\tif (menuList->mode == menuMode)\n\t\tconfigList->clearSelection();\n}\n\nvoid ConfigMainWindow::goBack(void)\n{\n\tif (configList->rootEntry == &rootmenu)\n\t\treturn;\n\n\tconfigList->setParentMenu();\n}\n\nvoid ConfigMainWindow::showSingleView(void)\n{\n\tsingleViewAction->setEnabled(false);\n\tsingleViewAction->setChecked(true);\n\tsplitViewAction->setEnabled(true);\n\tsplitViewAction->setChecked(false);\n\tfullViewAction->setEnabled(true);\n\tfullViewAction->setChecked(false);\n\n\tbackAction->setEnabled(true);\n\n\tmenuList->hide();\n\tmenuList->setRootMenu(0);\n\tconfigList->mode = singleMode;\n\tif (configList->rootEntry == &rootmenu)\n\t\tconfigList->updateListAll();\n\telse\n\t\tconfigList->setRootMenu(&rootmenu);\n\tconfigList->setFocus();\n}\n\nvoid ConfigMainWindow::showSplitView(void)\n{\n\tsingleViewAction->setEnabled(true);\n\tsingleViewAction->setChecked(false);\n\tsplitViewAction->setEnabled(false);\n\tsplitViewAction->setChecked(true);\n\tfullViewAction->setEnabled(true);\n\tfullViewAction->setChecked(false);\n\n\tbackAction->setEnabled(false);\n\n\tconfigList->mode = menuMode;\n\tif (configList->rootEntry == &rootmenu)\n\t\tconfigList->updateListAll();\n\telse\n\t\tconfigList->setRootMenu(&rootmenu);\n\tconfigList->setAllOpen(true);\n\tconfigApp->processEvents();\n\tmenuList->mode = symbolMode;\n\tmenuList->setRootMenu(&rootmenu);\n\tmenuList->setAllOpen(true);\n\tmenuList->show();\n\tmenuList->setFocus();\n}\n\nvoid ConfigMainWindow::showFullView(void)\n{\n\tsingleViewAction->setEnabled(true);\n\tsingleViewAction->setChecked(false);\n\tsplitViewAction->setEnabled(true);\n\tsplitViewAction->setChecked(false);\n\tfullViewAction->setEnabled(false);\n\tfullViewAction->setChecked(true);\n\n\tbackAction->setEnabled(false);\n\n\tmenuList->hide();\n\tmenuList->setRootMenu(0);\n\tconfigList->mode = fullMode;\n\tif (configList->rootEntry == &rootmenu)\n\t\tconfigList->updateListAll();\n\telse\n\t\tconfigList->setRootMenu(&rootmenu);\n\tconfigList->setFocus();\n}\n\n/*\n * ask for saving configuration before quitting\n */\nvoid ConfigMainWindow::closeEvent(QCloseEvent* e)\n{\n\tif (!conf_get_changed()) {\n\t\te->accept();\n\t\treturn;\n\t}\n\tQMessageBox mb(\"qconf\", \"Save configuration?\", QMessageBox::Warning,\n\t\t\tQMessageBox::Yes | QMessageBox::Default, QMessageBox::No, QMessageBox::Cancel | QMessageBox::Escape);\n\tmb.setButtonText(QMessageBox::Yes, \"&Save Changes\");\n\tmb.setButtonText(QMessageBox::No, \"&Discard Changes\");\n\tmb.setButtonText(QMessageBox::Cancel, \"Cancel Exit\");\n\tswitch (mb.exec()) {\n\tcase QMessageBox::Yes:\n\t\tif (saveConfig())\n\t\t\te->accept();\n\t\telse\n\t\t\te->ignore();\n\t\tbreak;\n\tcase QMessageBox::No:\n\t\te->accept();\n\t\tbreak;\n\tcase QMessageBox::Cancel:\n\t\te->ignore();\n\t\tbreak;\n\t}\n}\n\nvoid ConfigMainWindow::showIntro(void)\n{\n\tstatic const QString str =\n\t\t\"Welcome to the qconf graphical configuration tool.\\n\"\n\t\t\"\\n\"\n\t\t\"For bool and tristate options, a blank box indicates the \"\n\t\t\"feature is disabled, a check indicates it is enabled, and a \"\n\t\t\"dot indicates that it is to be compiled as a module. Clicking \"\n\t\t\"on the box will cycle through the three states. For int, hex, \"\n\t\t\"and string options, double-clicking or pressing F2 on the \"\n\t\t\"Value cell will allow you to edit the value.\\n\"\n\t\t\"\\n\"\n\t\t\"If you do not see an option (e.g., a device driver) that you \"\n\t\t\"believe should be present, try turning on Show All Options \"\n\t\t\"under the Options menu. Enabling Show Debug Info will help you\"\n\t\t\"figure out what other options must be enabled to support the \"\n\t\t\"option you are interested in, and hyperlinks will navigate to \"\n\t\t\"them.\\n\"\n\t\t\"\\n\"\n\t\t\"Toggling Show Debug Info under the Options menu will show the \"\n\t\t\"dependencies, which you can then match by examining other \"\n\t\t\"options.\\n\";\n\n\tQMessageBox::information(this, \"qconf\", str);\n}\n\nvoid ConfigMainWindow::showAbout(void)\n{\n\tstatic const QString str = \"qconf is Copyright (C) 2002 Roman Zippel <zippel@linux-m68k.org>.\\n\"\n\t\t\"Copyright (C) 2015 Boris Barbulovski <bbarbulovski@gmail.com>.\\n\"\n\t\t\"\\n\"\n\t\t\"Bug reports and feature request can also be entered at http://bugzilla.kernel.org/\\n\"\n\t\t\"\\n\"\n\t\t\"Qt Version: \";\n\n\tQMessageBox::information(this, \"qconf\", str + qVersion());\n}\n\nvoid ConfigMainWindow::saveSettings(void)\n{\n\tconfigSettings->setValue(\"/window x\", pos().x());\n\tconfigSettings->setValue(\"/window y\", pos().y());\n\tconfigSettings->setValue(\"/window width\", size().width());\n\tconfigSettings->setValue(\"/window height\", size().height());\n\n\tQString entry;\n\tswitch(configList->mode) {\n\tcase singleMode :\n\t\tentry = \"single\";\n\t\tbreak;\n\n\tcase symbolMode :\n\t\tentry = \"split\";\n\t\tbreak;\n\n\tcase fullMode :\n\t\tentry = \"full\";\n\t\tbreak;\n\n\tdefault:\n\t\tbreak;\n\t}\n\tconfigSettings->setValue(\"/listMode\", entry);\n\n\tconfigSettings->writeSizes(\"/split1\", split1->sizes());\n\tconfigSettings->writeSizes(\"/split2\", split2->sizes());\n}\n\nvoid ConfigMainWindow::conf_changed(void)\n{\n\tif (saveAction)\n\t\tsaveAction->setEnabled(conf_get_changed());\n}\n\nvoid fixup_rootmenu(struct menu *menu)\n{\n\tstruct menu *child;\n\tstatic int menu_cnt = 0;\n\n\tmenu->flags |= MENU_ROOT;\n\tfor (child = menu->list; child; child = child->next) {\n\t\tif (child->prompt && child->prompt->type == P_MENU) {\n\t\t\tmenu_cnt++;\n\t\t\tfixup_rootmenu(child);\n\t\t\tmenu_cnt--;\n\t\t} else if (!menu_cnt)\n\t\t\tfixup_rootmenu(child);\n\t}\n}\n\nstatic const char *progname;\n\nstatic void usage(void)\n{\n\tprintf(\"%s [-s] <config>\\n\", progname);\n\texit(0);\n}\n\nint main(int ac, char** av)\n{\n\tConfigMainWindow* v;\n\tconst char *name;\n\n\tprogname = av[0];\n\tif (ac > 1 && av[1][0] == '-') {\n\t\tswitch (av[1][1]) {\n\t\tcase 's':\n\t\t\tconf_set_message_callback(NULL);\n\t\t\tbreak;\n\t\tcase 'h':\n\t\tcase '?':\n\t\t\tusage();\n\t\t}\n\t\tname = av[2];\n\t} else\n\t\tname = av[1];\n\tif (!name)\n\t\tusage();\n\n\tconf_parse(name);\n\tfixup_rootmenu(&rootmenu);\n\tconf_read(NULL);\n\t//zconfdump(stdout);\n\n\tconfigApp = new QApplication(ac, av);\n\n\tconfigSettings = new ConfigSettings();\n\tconfigSettings->beginGroup(\"/kconfig/qconf\");\n\tv = new ConfigMainWindow();\n\n\t//zconfdump(stdout);\n\tconfigApp->connect(configApp, SIGNAL(lastWindowClosed()), SLOT(quit()));\n\tconfigApp->connect(configApp, SIGNAL(aboutToQuit()), v, SLOT(saveSettings()));\n\tv->show();\n\tconfigApp->exec();\n\n\tconfigSettings->endGroup();\n\tdelete configSettings;\n\tdelete v;\n\tdelete configApp;\n\n\treturn 0;\n}\n"
  },
  {
    "path": "scripts/config/qconf.h",
    "content": "/* SPDX-License-Identifier: GPL-2.0-only */\n/*\n * Copyright (C) 2002 Roman Zippel <zippel@linux-m68k.org>\n */\n\n#include <QCheckBox>\n#include <QDialog>\n#include <QHeaderView>\n#include <QLineEdit>\n#include <QMainWindow>\n#include <QPushButton>\n#include <QSettings>\n#include <QSplitter>\n#include <QStyledItemDelegate>\n#include <QTextBrowser>\n#include <QTreeWidget>\n\n#include \"expr.h\"\n\nclass ConfigList;\nclass ConfigItem;\nclass ConfigMainWindow;\n\nclass ConfigSettings : public QSettings {\npublic:\n\tConfigSettings();\n\tQList<int> readSizes(const QString& key, bool *ok);\n\tbool writeSizes(const QString& key, const QList<int>& value);\n};\n\nenum colIdx {\n\tpromptColIdx, nameColIdx, dataColIdx\n};\nenum listMode {\n\tsingleMode, menuMode, symbolMode, fullMode, listMode\n};\nenum optionMode {\n\tnormalOpt = 0, allOpt, promptOpt\n};\n\nclass ConfigList : public QTreeWidget {\n\tQ_OBJECT\n\ttypedef class QTreeWidget Parent;\npublic:\n\tConfigList(QWidget *parent, const char *name = 0);\n\t~ConfigList();\n\tvoid reinit(void);\n\tConfigItem* findConfigItem(struct menu *);\n\tvoid setSelected(QTreeWidgetItem *item, bool enable) {\n\t\tfor (int i = 0; i < selectedItems().size(); i++)\n\t\t\tselectedItems().at(i)->setSelected(false);\n\n\t\titem->setSelected(enable);\n\t}\n\nprotected:\n\tvoid keyPressEvent(QKeyEvent *e);\n\tvoid mousePressEvent(QMouseEvent *e);\n\tvoid mouseReleaseEvent(QMouseEvent *e);\n\tvoid mouseMoveEvent(QMouseEvent *e);\n\tvoid mouseDoubleClickEvent(QMouseEvent *e);\n\tvoid focusInEvent(QFocusEvent *e);\n\tvoid contextMenuEvent(QContextMenuEvent *e);\n\npublic slots:\n\tvoid setRootMenu(struct menu *menu);\n\n\tvoid updateList();\n\tvoid setValue(ConfigItem* item, tristate val);\n\tvoid changeValue(ConfigItem* item);\n\tvoid updateSelection(void);\n\tvoid saveSettings(void);\n\tvoid setOptionMode(QAction *action);\n\tvoid setShowName(bool on);\n\nsignals:\n\tvoid menuChanged(struct menu *menu);\n\tvoid menuSelected(struct menu *menu);\n\tvoid itemSelected(struct menu *menu);\n\tvoid parentSelected(void);\n\tvoid gotFocus(struct menu *);\n\tvoid showNameChanged(bool on);\n\npublic:\n\tvoid updateListAll(void)\n\t{\n\t\tupdateAll = true;\n\t\tupdateList();\n\t\tupdateAll = false;\n\t}\n\tvoid setAllOpen(bool open);\n\tvoid setParentMenu(void);\n\n\tbool menuSkip(struct menu *);\n\n\tvoid updateMenuList(ConfigItem *parent, struct menu*);\n\tvoid updateMenuList(struct menu *menu);\n\n\tbool updateAll;\n\n\tbool showName;\n\tenum listMode mode;\n\tenum optionMode optMode;\n\tstruct menu *rootEntry;\n\tQPalette disabledColorGroup;\n\tQPalette inactivedColorGroup;\n\tQMenu* headerPopup;\n\n\tstatic QList<ConfigList *> allLists;\n\tstatic void updateListForAll();\n\tstatic void updateListAllForAll();\n\n\tstatic QAction *showNormalAction, *showAllAction, *showPromptAction;\n};\n\nclass ConfigItem : public QTreeWidgetItem {\n\ttypedef class QTreeWidgetItem Parent;\npublic:\n\tConfigItem(ConfigList *parent, ConfigItem *after, struct menu *m, bool v)\n\t: Parent(parent, after), nextItem(0), menu(m), visible(v), goParent(false)\n\t{\n\t\tinit();\n\t}\n\tConfigItem(ConfigItem *parent, ConfigItem *after, struct menu *m, bool v)\n\t: Parent(parent, after), nextItem(0), menu(m), visible(v), goParent(false)\n\t{\n\t\tinit();\n\t}\n\tConfigItem(ConfigList *parent, ConfigItem *after, bool v)\n\t: Parent(parent, after), nextItem(0), menu(0), visible(v), goParent(true)\n\t{\n\t\tinit();\n\t}\n\t~ConfigItem(void);\n\tvoid init(void);\n\tvoid updateMenu(void);\n\tvoid testUpdateMenu(bool v);\n\tConfigList* listView() const\n\t{\n\t\treturn (ConfigList*)Parent::treeWidget();\n\t}\n\tConfigItem* firstChild() const\n\t{\n\t\treturn (ConfigItem *)Parent::child(0);\n\t}\n\tConfigItem* nextSibling()\n\t{\n\t\tConfigItem *ret = NULL;\n\t\tConfigItem *_parent = (ConfigItem *)parent();\n\n\t\tif(_parent) {\n\t\t\tret = (ConfigItem *)_parent->child(_parent->indexOfChild(this)+1);\n\t\t} else {\n\t\t\tQTreeWidget *_treeWidget = treeWidget();\n\t\t\tret = (ConfigItem *)_treeWidget->topLevelItem(_treeWidget->indexOfTopLevelItem(this)+1);\n\t\t}\n\n\t\treturn ret;\n\t}\n\t// TODO: Implement paintCell\n\n\tConfigItem* nextItem;\n\tstruct menu *menu;\n\tbool visible;\n\tbool goParent;\n\n\tstatic QIcon symbolYesIcon, symbolModIcon, symbolNoIcon;\n\tstatic QIcon choiceYesIcon, choiceNoIcon;\n\tstatic QIcon menuIcon, menubackIcon;\n};\n\nclass ConfigItemDelegate : public QStyledItemDelegate\n{\nprivate:\n\tstruct menu *menu;\npublic:\n\tConfigItemDelegate(QObject *parent = nullptr)\n\t\t: QStyledItemDelegate(parent) {}\n\tQWidget *createEditor(QWidget *parent,\n\t\t\t      const QStyleOptionViewItem &option,\n\t\t\t      const QModelIndex &index) const override;\n\tvoid setModelData(QWidget *editor, QAbstractItemModel *model,\n\t\t\t  const QModelIndex &index) const override;\n};\n\nclass ConfigInfoView : public QTextBrowser {\n\tQ_OBJECT\n\ttypedef class QTextBrowser Parent;\n\tQMenu *contextMenu;\npublic:\n\tConfigInfoView(QWidget* parent, const char *name = 0);\n\tbool showDebug(void) const { return _showDebug; }\n\npublic slots:\n\tvoid setInfo(struct menu *menu);\n\tvoid saveSettings(void);\n\tvoid setShowDebug(bool);\n\tvoid clicked (const QUrl &url);\n\nsignals:\n\tvoid showDebugChanged(bool);\n\tvoid menuSelected(struct menu *);\n\nprotected:\n\tvoid symbolInfo(void);\n\tvoid menuInfo(void);\n\tQString debug_info(struct symbol *sym);\n\tstatic QString print_filter(const QString &str);\n\tstatic void expr_print_help(void *data, struct symbol *sym, const char *str);\n\tvoid contextMenuEvent(QContextMenuEvent *event);\n\n\tstruct symbol *sym;\n\tstruct menu *_menu;\n\tbool _showDebug;\n};\n\nclass ConfigSearchWindow : public QDialog {\n\tQ_OBJECT\n\ttypedef class QDialog Parent;\npublic:\n\tConfigSearchWindow(ConfigMainWindow *parent);\n\npublic slots:\n\tvoid saveSettings(void);\n\tvoid search(void);\n\nprotected:\n\tQLineEdit* editField;\n\tQPushButton* searchButton;\n\tQSplitter* split;\n\tConfigList *list;\n\tConfigInfoView* info;\n\n\tstruct symbol **result;\n};\n\nclass ConfigMainWindow : public QMainWindow {\n\tQ_OBJECT\n\n\tchar *configname;\n\tstatic QAction *saveAction;\n\tstatic void conf_changed(void);\npublic:\n\tConfigMainWindow(void);\npublic slots:\n\tvoid changeMenu(struct menu *);\n\tvoid changeItens(struct menu *);\n\tvoid setMenuLink(struct menu *);\n\tvoid listFocusChanged(void);\n\tvoid goBack(void);\n\tvoid loadConfig(void);\n\tbool saveConfig(void);\n\tvoid saveConfigAs(void);\n\tvoid searchConfig(void);\n\tvoid showSingleView(void);\n\tvoid showSplitView(void);\n\tvoid showFullView(void);\n\tvoid showIntro(void);\n\tvoid showAbout(void);\n\tvoid saveSettings(void);\n\nprotected:\n\tvoid closeEvent(QCloseEvent *e);\n\n\tConfigSearchWindow *searchWindow;\n\tConfigList *menuList;\n\tConfigList *configList;\n\tConfigInfoView *helpText;\n\tQAction *backAction;\n\tQAction *singleViewAction;\n\tQAction *splitViewAction;\n\tQAction *fullViewAction;\n\tQSplitter *split1;\n\tQSplitter *split2;\n};\n"
  },
  {
    "path": "scripts/config/symbol.c",
    "content": "// SPDX-License-Identifier: GPL-2.0-only\n/*\n * Copyright (C) 2002 Roman Zippel <zippel@linux-m68k.org>\n */\n\n#include <sys/types.h>\n#include <ctype.h>\n#include <stdlib.h>\n#include <string.h>\n#include <regex.h>\n\n#include \"lkc.h\"\n\nstruct symbol symbol_yes = {\n\t.name = \"y\",\n\t.curr = { \"y\", yes },\n\t.flags = SYMBOL_CONST|SYMBOL_VALID,\n};\n\nstruct symbol symbol_mod = {\n\t.name = \"m\",\n\t.curr = { \"m\", mod },\n\t.flags = SYMBOL_CONST|SYMBOL_VALID,\n};\n\nstruct symbol symbol_no = {\n\t.name = \"n\",\n\t.curr = { \"n\", no },\n\t.flags = SYMBOL_CONST|SYMBOL_VALID,\n};\n\nstatic struct symbol symbol_empty = {\n\t.name = \"\",\n\t.curr = { \"\", no },\n\t.flags = SYMBOL_VALID,\n};\n\nstruct symbol *modules_sym;\nstatic tristate modules_val;\nint recursive_is_error;\n\nenum symbol_type sym_get_type(struct symbol *sym)\n{\n\tenum symbol_type type = sym->type;\n\n\tif (type == S_TRISTATE) {\n\t\tif (sym_is_choice_value(sym) && sym->visible == yes)\n\t\t\ttype = S_BOOLEAN;\n\t\telse if (modules_val == no)\n\t\t\ttype = S_BOOLEAN;\n\t}\n\treturn type;\n}\n\nconst char *sym_type_name(enum symbol_type type)\n{\n\tswitch (type) {\n\tcase S_BOOLEAN:\n\t\treturn \"bool\";\n\tcase S_TRISTATE:\n\t\treturn \"tristate\";\n\tcase S_INT:\n\t\treturn \"integer\";\n\tcase S_HEX:\n\t\treturn \"hex\";\n\tcase S_STRING:\n\t\treturn \"string\";\n\tcase S_UNKNOWN:\n\t\treturn \"unknown\";\n\t}\n\treturn \"???\";\n}\n\nstruct property *sym_get_choice_prop(struct symbol *sym)\n{\n\tstruct property *prop;\n\n\tfor_all_choices(sym, prop)\n\t\treturn prop;\n\treturn NULL;\n}\n\nstatic struct property *sym_get_default_prop(struct symbol *sym)\n{\n\tstruct property *prop;\n\n\tfor_all_defaults(sym, prop) {\n\t\tprop->visible.tri = expr_calc_value(prop->visible.expr);\n\t\tif (prop->visible.tri != no)\n\t\t\treturn prop;\n\t}\n\treturn NULL;\n}\n\nstruct property *sym_get_range_prop(struct symbol *sym)\n{\n\tstruct property *prop;\n\n\tfor_all_properties(sym, prop, P_RANGE) {\n\t\tprop->visible.tri = expr_calc_value(prop->visible.expr);\n\t\tif (prop->visible.tri != no)\n\t\t\treturn prop;\n\t}\n\treturn NULL;\n}\n\nstatic long long sym_get_range_val(struct symbol *sym, int base)\n{\n\tsym_calc_value(sym);\n\tswitch (sym->type) {\n\tcase S_INT:\n\t\tbase = 10;\n\t\tbreak;\n\tcase S_HEX:\n\t\tbase = 16;\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\treturn strtoll(sym->curr.val, NULL, base);\n}\n\nstatic void sym_validate_range(struct symbol *sym)\n{\n\tstruct property *prop;\n\tint base;\n\tlong long val, val2;\n\tchar str[64];\n\n\tswitch (sym->type) {\n\tcase S_INT:\n\t\tbase = 10;\n\t\tbreak;\n\tcase S_HEX:\n\t\tbase = 16;\n\t\tbreak;\n\tdefault:\n\t\treturn;\n\t}\n\tprop = sym_get_range_prop(sym);\n\tif (!prop)\n\t\treturn;\n\tval = strtoll(sym->curr.val, NULL, base);\n\tval2 = sym_get_range_val(prop->expr->left.sym, base);\n\tif (val >= val2) {\n\t\tval2 = sym_get_range_val(prop->expr->right.sym, base);\n\t\tif (val <= val2)\n\t\t\treturn;\n\t}\n\tif (sym->type == S_INT)\n\t\tsprintf(str, \"%lld\", val2);\n\telse\n\t\tsprintf(str, \"0x%llx\", val2);\n\tsym->curr.val = xstrdup(str);\n}\n\nstatic void sym_set_changed(struct symbol *sym)\n{\n\tstruct property *prop;\n\n\tsym->flags |= SYMBOL_CHANGED;\n\tfor (prop = sym->prop; prop; prop = prop->next) {\n\t\tif (prop->menu)\n\t\t\tprop->menu->flags |= MENU_CHANGED;\n\t}\n}\n\nstatic void sym_set_all_changed(void)\n{\n\tstruct symbol *sym;\n\tint i;\n\n\tfor_all_symbols(i, sym)\n\t\tsym_set_changed(sym);\n}\n\nstatic void sym_calc_visibility(struct symbol *sym)\n{\n\tstruct property *prop;\n\tstruct symbol *choice_sym = NULL;\n\ttristate tri;\n\n\t/* any prompt visible? */\n\ttri = no;\n\n\tif (sym_is_choice_value(sym))\n\t\tchoice_sym = prop_get_symbol(sym_get_choice_prop(sym));\n\n\tfor_all_prompts(sym, prop) {\n\t\tprop->visible.tri = expr_calc_value(prop->visible.expr);\n\t\t/*\n\t\t * Tristate choice_values with visibility 'mod' are\n\t\t * not visible if the corresponding choice's value is\n\t\t * 'yes'.\n\t\t */\n\t\tif (choice_sym && sym->type == S_TRISTATE &&\n\t\t    prop->visible.tri == mod && choice_sym->curr.tri == yes)\n\t\t\tprop->visible.tri = no;\n\n\t\ttri = EXPR_OR(tri, prop->visible.tri);\n\t}\n\tif (tri == mod && (sym->type != S_TRISTATE || modules_val == no))\n\t\ttri = yes;\n\tif (sym->visible != tri) {\n\t\tsym->visible = tri;\n\t\tsym_set_changed(sym);\n\t}\n\tif (sym_is_choice_value(sym))\n\t\treturn;\n\t/* defaulting to \"yes\" if no explicit \"depends on\" are given */\n\ttri = yes;\n\tif (sym->dir_dep.expr)\n\t\ttri = expr_calc_value(sym->dir_dep.expr);\n\tif (tri == mod && sym_get_type(sym) == S_BOOLEAN)\n\t\ttri = yes;\n\tif (sym->dir_dep.tri != tri) {\n\t\tsym->dir_dep.tri = tri;\n\t\tsym_set_changed(sym);\n\t}\n\ttri = no;\n\tif (sym->rev_dep.expr)\n\t\ttri = expr_calc_value(sym->rev_dep.expr);\n\tif (tri == mod && sym_get_type(sym) == S_BOOLEAN)\n\t\ttri = yes;\n\tif (sym->rev_dep.tri != tri) {\n\t\tsym->rev_dep.tri = tri;\n\t\tsym_set_changed(sym);\n\t}\n\ttri = no;\n\tif (sym->implied.expr)\n\t\ttri = expr_calc_value(sym->implied.expr);\n\tif (tri == mod && sym_get_type(sym) == S_BOOLEAN)\n\t\ttri = yes;\n\tif (sym->implied.tri != tri) {\n\t\tsym->implied.tri = tri;\n\t\tsym_set_changed(sym);\n\t}\n}\n\n/*\n * Find the default symbol for a choice.\n * First try the default values for the choice symbol\n * Next locate the first visible choice value\n * Return NULL if none was found\n */\nstruct symbol *sym_choice_default(struct symbol *sym)\n{\n\tstruct symbol *def_sym;\n\tstruct property *prop;\n\tstruct expr *e;\n\n\t/* any of the defaults visible? */\n\tfor_all_defaults(sym, prop) {\n\t\tprop->visible.tri = expr_calc_value(prop->visible.expr);\n\t\tif (prop->visible.tri == no)\n\t\t\tcontinue;\n\t\tdef_sym = prop_get_symbol(prop);\n\t\tif (def_sym->visible != no)\n\t\t\treturn def_sym;\n\t}\n\n\t/* just get the first visible value */\n\tprop = sym_get_choice_prop(sym);\n\texpr_list_for_each_sym(prop->expr, e, def_sym)\n\t\tif (def_sym->visible != no)\n\t\t\treturn def_sym;\n\n\t/* failed to locate any defaults */\n\treturn NULL;\n}\n\nstatic struct symbol *sym_calc_choice(struct symbol *sym)\n{\n\tstruct symbol *def_sym;\n\tstruct property *prop;\n\tstruct expr *e;\n\tint flags;\n\n\t/* first calculate all choice values' visibilities */\n\tflags = sym->flags;\n\tprop = sym_get_choice_prop(sym);\n\texpr_list_for_each_sym(prop->expr, e, def_sym) {\n\t\tsym_calc_visibility(def_sym);\n\t\tif (def_sym->visible != no)\n\t\t\tflags &= def_sym->flags;\n\t}\n\n\tsym->flags &= flags | ~SYMBOL_DEF_USER;\n\n\t/* is the user choice visible? */\n\tdef_sym = sym->def[S_DEF_USER].val;\n\tif (def_sym && def_sym->visible != no)\n\t\treturn def_sym;\n\n\tdef_sym = sym_choice_default(sym);\n\n\tif (def_sym == NULL)\n\t\t/* no choice? reset tristate value */\n\t\tsym->curr.tri = no;\n\n\treturn def_sym;\n}\n\nvoid sym_calc_value(struct symbol *sym)\n{\n\tstruct symbol_value newval, oldval;\n\tstruct property *prop;\n\tstruct expr *e;\n\n\tif (!sym)\n\t\treturn;\n\n\tif (sym->flags & SYMBOL_VALID)\n\t\treturn;\n\n\tif (sym_is_choice_value(sym) &&\n\t    sym->flags & SYMBOL_NEED_SET_CHOICE_VALUES) {\n\t\tsym->flags &= ~SYMBOL_NEED_SET_CHOICE_VALUES;\n\t\tprop = sym_get_choice_prop(sym);\n\t\tsym_calc_value(prop_get_symbol(prop));\n\t}\n\n\tsym->flags |= SYMBOL_VALID;\n\n\toldval = sym->curr;\n\n\tswitch (sym->type) {\n\tcase S_INT:\n\tcase S_HEX:\n\tcase S_STRING:\n\t\tnewval = symbol_empty.curr;\n\t\tbreak;\n\tcase S_BOOLEAN:\n\tcase S_TRISTATE:\n\t\tnewval = symbol_no.curr;\n\t\tbreak;\n\tdefault:\n\t\tsym->curr.val = sym->name;\n\t\tsym->curr.tri = no;\n\t\treturn;\n\t}\n\tsym->flags &= ~SYMBOL_WRITE;\n\n\tsym_calc_visibility(sym);\n\n\tif (sym->visible != no)\n\t\tsym->flags |= SYMBOL_WRITE;\n\n\t/* set default if recursively called */\n\tsym->curr = newval;\n\n\tswitch (sym_get_type(sym)) {\n\tcase S_BOOLEAN:\n\tcase S_TRISTATE:\n\t\tif (sym_is_choice_value(sym) && sym->visible == yes) {\n\t\t\tprop = sym_get_choice_prop(sym);\n\t\t\tnewval.tri = (prop_get_symbol(prop)->curr.val == sym) ? yes : no;\n\t\t} else {\n\t\t\tif (sym->visible != no) {\n\t\t\t\t/* if the symbol is visible use the user value\n\t\t\t\t * if available, otherwise try the default value\n\t\t\t\t */\n\t\t\t\tif (sym_has_value(sym)) {\n\t\t\t\t\tnewval.tri = EXPR_AND(sym->def[S_DEF_USER].tri,\n\t\t\t\t\t\t\t      sym->visible);\n\t\t\t\t\tgoto calc_newval;\n\t\t\t\t}\n\t\t\t}\n\t\t\tif (sym->rev_dep.tri != no)\n\t\t\t\tsym->flags |= SYMBOL_WRITE;\n\t\t\tif (!sym_is_choice(sym)) {\n\t\t\t\tprop = sym_get_default_prop(sym);\n\t\t\t\tif (prop) {\n\t\t\t\t\tsym->flags |= SYMBOL_WRITE;\n\t\t\t\t\tnewval.tri = EXPR_AND(expr_calc_value(prop->expr),\n\t\t\t\t\t\t\t      prop->visible.tri);\n\t\t\t\t}\n\t\t\t\tif (sym->implied.tri != no) {\n\t\t\t\t\tsym->flags |= SYMBOL_WRITE;\n\t\t\t\t\tnewval.tri = EXPR_OR(newval.tri, sym->implied.tri);\n\t\t\t\t\tnewval.tri = EXPR_AND(newval.tri,\n\t\t\t\t\t\t\t      sym->dir_dep.tri);\n\t\t\t\t}\n\t\t\t}\n\t\tcalc_newval:\n\t\t\tif (sym->dir_dep.tri == no && sym->rev_dep.tri != no)\n\t\t\t\tnewval.tri = no;\n\t\t\telse\n\t\t\t\tnewval.tri = EXPR_OR(newval.tri, sym->rev_dep.tri);\n\t\t}\n\t\tif (newval.tri == mod && sym_get_type(sym) == S_BOOLEAN)\n\t\t\tnewval.tri = yes;\n\t\tbreak;\n\tcase S_STRING:\n\tcase S_HEX:\n\tcase S_INT:\n\t\tif (sym->visible != no && sym_has_value(sym)) {\n\t\t\tnewval.val = sym->def[S_DEF_USER].val;\n\t\t\tbreak;\n\t\t}\n\t\tprop = sym_get_default_prop(sym);\n\t\tif (prop) {\n\t\t\tstruct symbol *ds = prop_get_symbol(prop);\n\t\t\tif (ds) {\n\t\t\t\tsym->flags |= SYMBOL_WRITE;\n\t\t\t\tsym_calc_value(ds);\n\t\t\t\tnewval.val = ds->curr.val;\n\t\t\t}\n\t\t}\n\t\tbreak;\n\tdefault:\n\t\t;\n\t}\n\n\tsym->curr = newval;\n\tif (sym_is_choice(sym) && newval.tri == yes)\n\t\tsym->curr.val = sym_calc_choice(sym);\n\tsym_validate_range(sym);\n\n\tif (memcmp(&oldval, &sym->curr, sizeof(oldval))) {\n\t\tsym_set_changed(sym);\n\t\tif (modules_sym == sym) {\n\t\t\tsym_set_all_changed();\n\t\t\tmodules_val = modules_sym->curr.tri;\n\t\t}\n\t}\n\n\tif (sym_is_choice(sym)) {\n\t\tstruct symbol *choice_sym;\n\n\t\tprop = sym_get_choice_prop(sym);\n\t\texpr_list_for_each_sym(prop->expr, e, choice_sym) {\n\t\t\tif ((sym->flags & SYMBOL_WRITE) &&\n\t\t\t    choice_sym->visible != no)\n\t\t\t\tchoice_sym->flags |= SYMBOL_WRITE;\n\t\t\tif (sym->flags & SYMBOL_CHANGED)\n\t\t\t\tsym_set_changed(choice_sym);\n\t\t}\n\t}\n\n\tif (sym->flags & SYMBOL_NO_WRITE)\n\t\tsym->flags &= ~SYMBOL_WRITE;\n\n\tif (sym->flags & SYMBOL_NEED_SET_CHOICE_VALUES)\n\t\tset_all_choice_values(sym);\n}\n\nvoid sym_clear_all_valid(void)\n{\n\tstruct symbol *sym;\n\tint i;\n\n\tfor_all_symbols(i, sym)\n\t\tsym->flags &= ~SYMBOL_VALID;\n\tconf_set_changed(true);\n\tsym_calc_value(modules_sym);\n}\n\nbool sym_tristate_within_range(struct symbol *sym, tristate val)\n{\n\tint type = sym_get_type(sym);\n\n\tif (sym->visible == no)\n\t\treturn false;\n\n\tif (type != S_BOOLEAN && type != S_TRISTATE)\n\t\treturn false;\n\n\tif (type == S_BOOLEAN && val == mod)\n\t\treturn false;\n\tif (sym->visible <= sym->rev_dep.tri)\n\t\treturn false;\n\tif (sym_is_choice_value(sym) && sym->visible == yes)\n\t\treturn val == yes;\n\treturn val >= sym->rev_dep.tri && val <= sym->visible;\n}\n\nbool sym_set_tristate_value(struct symbol *sym, tristate val)\n{\n\ttristate oldval = sym_get_tristate_value(sym);\n\n\tif (oldval != val && !sym_tristate_within_range(sym, val))\n\t\treturn false;\n\n\tif (!(sym->flags & SYMBOL_DEF_USER)) {\n\t\tsym->flags |= SYMBOL_DEF_USER;\n\t\tsym_set_changed(sym);\n\t}\n\t/*\n\t * setting a choice value also resets the new flag of the choice\n\t * symbol and all other choice values.\n\t */\n\tif (sym_is_choice_value(sym) && val == yes) {\n\t\tstruct symbol *cs = prop_get_symbol(sym_get_choice_prop(sym));\n\t\tstruct property *prop;\n\t\tstruct expr *e;\n\n\t\tcs->def[S_DEF_USER].val = sym;\n\t\tcs->flags |= SYMBOL_DEF_USER;\n\t\tprop = sym_get_choice_prop(cs);\n\t\tfor (e = prop->expr; e; e = e->left.expr) {\n\t\t\tif (e->right.sym->visible != no)\n\t\t\t\te->right.sym->flags |= SYMBOL_DEF_USER;\n\t\t}\n\t}\n\n\tsym->def[S_DEF_USER].tri = val;\n\tif (oldval != val)\n\t\tsym_clear_all_valid();\n\n\treturn true;\n}\n\ntristate sym_toggle_tristate_value(struct symbol *sym)\n{\n\ttristate oldval, newval;\n\n\toldval = newval = sym_get_tristate_value(sym);\n\tdo {\n\t\tswitch (newval) {\n\t\tcase no:\n\t\t\tnewval = mod;\n\t\t\tbreak;\n\t\tcase mod:\n\t\t\tnewval = yes;\n\t\t\tbreak;\n\t\tcase yes:\n\t\t\tnewval = no;\n\t\t\tbreak;\n\t\t}\n\t\tif (sym_set_tristate_value(sym, newval))\n\t\t\tbreak;\n\t} while (oldval != newval);\n\treturn newval;\n}\n\nbool sym_string_valid(struct symbol *sym, const char *str)\n{\n\tsigned char ch;\n\n\tswitch (sym->type) {\n\tcase S_STRING:\n\t\treturn true;\n\tcase S_INT:\n\t\tch = *str++;\n\t\tif (ch == '-')\n\t\t\tch = *str++;\n\t\tif (!isdigit(ch))\n\t\t\treturn false;\n\t\tif (ch == '0' && *str != 0)\n\t\t\treturn false;\n\t\twhile ((ch = *str++)) {\n\t\t\tif (!isdigit(ch))\n\t\t\t\treturn false;\n\t\t}\n\t\treturn true;\n\tcase S_HEX:\n\t\tif (str[0] == '0' && (str[1] == 'x' || str[1] == 'X'))\n\t\t\tstr += 2;\n\t\tch = *str++;\n\t\tdo {\n\t\t\tif (!isxdigit(ch))\n\t\t\t\treturn false;\n\t\t} while ((ch = *str++));\n\t\treturn true;\n\tcase S_BOOLEAN:\n\tcase S_TRISTATE:\n\t\tswitch (str[0]) {\n\t\tcase 'y': case 'Y':\n\t\tcase 'm': case 'M':\n\t\tcase 'n': case 'N':\n\t\t\treturn true;\n\t\t}\n\t\treturn false;\n\tdefault:\n\t\treturn false;\n\t}\n}\n\nbool sym_string_within_range(struct symbol *sym, const char *str)\n{\n\tstruct property *prop;\n\tlong long val;\n\n\tswitch (sym->type) {\n\tcase S_STRING:\n\t\treturn sym_string_valid(sym, str);\n\tcase S_INT:\n\t\tif (!sym_string_valid(sym, str))\n\t\t\treturn false;\n\t\tprop = sym_get_range_prop(sym);\n\t\tif (!prop)\n\t\t\treturn true;\n\t\tval = strtoll(str, NULL, 10);\n\t\treturn val >= sym_get_range_val(prop->expr->left.sym, 10) &&\n\t\t       val <= sym_get_range_val(prop->expr->right.sym, 10);\n\tcase S_HEX:\n\t\tif (!sym_string_valid(sym, str))\n\t\t\treturn false;\n\t\tprop = sym_get_range_prop(sym);\n\t\tif (!prop)\n\t\t\treturn true;\n\t\tval = strtoll(str, NULL, 16);\n\t\treturn val >= sym_get_range_val(prop->expr->left.sym, 16) &&\n\t\t       val <= sym_get_range_val(prop->expr->right.sym, 16);\n\tcase S_BOOLEAN:\n\tcase S_TRISTATE:\n\t\tswitch (str[0]) {\n\t\tcase 'y': case 'Y':\n\t\t\treturn sym_tristate_within_range(sym, yes);\n\t\tcase 'm': case 'M':\n\t\t\treturn sym_tristate_within_range(sym, mod);\n\t\tcase 'n': case 'N':\n\t\t\treturn sym_tristate_within_range(sym, no);\n\t\t}\n\t\treturn false;\n\tdefault:\n\t\treturn false;\n\t}\n}\n\nbool sym_set_string_value(struct symbol *sym, const char *newval)\n{\n\tconst char *oldval;\n\tchar *val;\n\tint size;\n\n\tswitch (sym->type) {\n\tcase S_BOOLEAN:\n\tcase S_TRISTATE:\n\t\tswitch (newval[0]) {\n\t\tcase 'y': case 'Y':\n\t\t\treturn sym_set_tristate_value(sym, yes);\n\t\tcase 'm': case 'M':\n\t\t\treturn sym_set_tristate_value(sym, mod);\n\t\tcase 'n': case 'N':\n\t\t\treturn sym_set_tristate_value(sym, no);\n\t\t}\n\t\treturn false;\n\tdefault:\n\t\t;\n\t}\n\n\tif (!sym_string_within_range(sym, newval))\n\t\treturn false;\n\n\tif (!(sym->flags & SYMBOL_DEF_USER)) {\n\t\tsym->flags |= SYMBOL_DEF_USER;\n\t\tsym_set_changed(sym);\n\t}\n\n\toldval = sym->def[S_DEF_USER].val;\n\tsize = strlen(newval) + 1;\n\tif (sym->type == S_HEX && (newval[0] != '0' || (newval[1] != 'x' && newval[1] != 'X'))) {\n\t\tsize += 2;\n\t\tsym->def[S_DEF_USER].val = val = xmalloc(size);\n\t\t*val++ = '0';\n\t\t*val++ = 'x';\n\t} else if (!oldval || strcmp(oldval, newval))\n\t\tsym->def[S_DEF_USER].val = val = xmalloc(size);\n\telse\n\t\treturn true;\n\n\tstrcpy(val, newval);\n\tfree((void *)oldval);\n\tsym_clear_all_valid();\n\n\treturn true;\n}\n\n/*\n * Find the default value associated to a symbol.\n * For tristate symbol handle the modules=n case\n * in which case \"m\" becomes \"y\".\n * If the symbol does not have any default then fallback\n * to the fixed default values.\n */\nconst char *sym_get_string_default(struct symbol *sym)\n{\n\tstruct property *prop;\n\tstruct symbol *ds;\n\tconst char *str;\n\ttristate val;\n\n\tsym_calc_visibility(sym);\n\tsym_calc_value(modules_sym);\n\tval = symbol_no.curr.tri;\n\tstr = symbol_empty.curr.val;\n\n\t/* If symbol has a default value look it up */\n\tprop = sym_get_default_prop(sym);\n\tif (prop != NULL) {\n\t\tswitch (sym->type) {\n\t\tcase S_BOOLEAN:\n\t\tcase S_TRISTATE:\n\t\t\t/* The visibility may limit the value from yes => mod */\n\t\t\tval = EXPR_AND(expr_calc_value(prop->expr), prop->visible.tri);\n\t\t\tbreak;\n\t\tdefault:\n\t\t\t/*\n\t\t\t * The following fails to handle the situation\n\t\t\t * where a default value is further limited by\n\t\t\t * the valid range.\n\t\t\t */\n\t\t\tds = prop_get_symbol(prop);\n\t\t\tif (ds != NULL) {\n\t\t\t\tsym_calc_value(ds);\n\t\t\t\tstr = (const char *)ds->curr.val;\n\t\t\t}\n\t\t}\n\t}\n\n\t/* Handle select statements */\n\tval = EXPR_OR(val, sym->rev_dep.tri);\n\n\t/* transpose mod to yes if modules are not enabled */\n\tif (val == mod)\n\t\tif (!sym_is_choice_value(sym) && modules_sym->curr.tri == no)\n\t\t\tval = yes;\n\n\t/* transpose mod to yes if type is bool */\n\tif (sym->type == S_BOOLEAN && val == mod)\n\t\tval = yes;\n\n\t/* adjust the default value if this symbol is implied by another */\n\tif (val < sym->implied.tri)\n\t\tval = sym->implied.tri;\n\n\tswitch (sym->type) {\n\tcase S_BOOLEAN:\n\tcase S_TRISTATE:\n\t\tswitch (val) {\n\t\tcase no: return \"n\";\n\t\tcase mod: return \"m\";\n\t\tcase yes: return \"y\";\n\t\t}\n\tcase S_INT:\n\tcase S_HEX:\n\t\treturn str;\n\tcase S_STRING:\n\t\treturn str;\n\tcase S_UNKNOWN:\n\t\tbreak;\n\t}\n\treturn \"\";\n}\n\nconst char *sym_get_string_value(struct symbol *sym)\n{\n\ttristate val;\n\n\tswitch (sym->type) {\n\tcase S_BOOLEAN:\n\tcase S_TRISTATE:\n\t\tval = sym_get_tristate_value(sym);\n\t\tswitch (val) {\n\t\tcase no:\n\t\t\treturn \"n\";\n\t\tcase mod:\n\t\t\tsym_calc_value(modules_sym);\n\t\t\treturn (modules_sym->curr.tri == no) ? \"n\" : \"m\";\n\t\tcase yes:\n\t\t\treturn \"y\";\n\t\t}\n\t\tbreak;\n\tdefault:\n\t\t;\n\t}\n\treturn (const char *)sym->curr.val;\n}\n\nbool sym_is_changeable(struct symbol *sym)\n{\n\treturn sym->visible > sym->rev_dep.tri;\n}\n\nstatic unsigned strhash(const char *s)\n{\n\t/* fnv32 hash */\n\tunsigned hash = 2166136261U;\n\tfor (; *s; s++)\n\t\thash = (hash ^ *s) * 0x01000193;\n\treturn hash;\n}\n\nstruct symbol *sym_lookup(const char *name, int flags)\n{\n\tstruct symbol *symbol;\n\tchar *new_name;\n\tint hash;\n\n\tif (name) {\n\t\tif (name[0] && !name[1]) {\n\t\t\tswitch (name[0]) {\n\t\t\tcase 'y': return &symbol_yes;\n\t\t\tcase 'm': return &symbol_mod;\n\t\t\tcase 'n': return &symbol_no;\n\t\t\t}\n\t\t}\n\t\thash = strhash(name) % SYMBOL_HASHSIZE;\n\n\t\tfor (symbol = symbol_hash[hash]; symbol; symbol = symbol->next) {\n\t\t\tif (symbol->name &&\n\t\t\t    !strcmp(symbol->name, name) &&\n\t\t\t    (flags ? symbol->flags & flags\n\t\t\t\t   : !(symbol->flags & (SYMBOL_CONST|SYMBOL_CHOICE))))\n\t\t\t\treturn symbol;\n\t\t}\n\t\tnew_name = xstrdup(name);\n\t} else {\n\t\tnew_name = NULL;\n\t\thash = 0;\n\t}\n\n\tsymbol = xmalloc(sizeof(*symbol));\n\tmemset(symbol, 0, sizeof(*symbol));\n\tsymbol->name = new_name;\n\tsymbol->type = S_UNKNOWN;\n\tsymbol->flags = flags;\n\n\tsymbol->next = symbol_hash[hash];\n\tsymbol_hash[hash] = symbol;\n\n\treturn symbol;\n}\n\nstruct symbol *sym_find(const char *name)\n{\n\tstruct symbol *symbol = NULL;\n\tint hash = 0;\n\n\tif (!name)\n\t\treturn NULL;\n\n\tif (name[0] && !name[1]) {\n\t\tswitch (name[0]) {\n\t\tcase 'y': return &symbol_yes;\n\t\tcase 'm': return &symbol_mod;\n\t\tcase 'n': return &symbol_no;\n\t\t}\n\t}\n\thash = strhash(name) % SYMBOL_HASHSIZE;\n\n\tfor (symbol = symbol_hash[hash]; symbol; symbol = symbol->next) {\n\t\tif (symbol->name &&\n\t\t    !strcmp(symbol->name, name) &&\n\t\t    !(symbol->flags & SYMBOL_CONST))\n\t\t\t\tbreak;\n\t}\n\n\treturn symbol;\n}\n\nconst char *sym_escape_string_value(const char *in)\n{\n\tconst char *p;\n\tsize_t reslen;\n\tchar *res;\n\tsize_t l;\n\n\treslen = strlen(in) + strlen(\"\\\"\\\"\") + 1;\n\n\tp = in;\n\tfor (;;) {\n\t\tl = strcspn(p, \"\\\"\\\\\");\n\t\tp += l;\n\n\t\tif (p[0] == '\\0')\n\t\t\tbreak;\n\n\t\treslen++;\n\t\tp++;\n\t}\n\n\tres = xmalloc(reslen);\n\tres[0] = '\\0';\n\n\tstrcat(res, \"\\\"\");\n\n\tp = in;\n\tfor (;;) {\n\t\tl = strcspn(p, \"\\\"\\\\\");\n\t\tstrncat(res, p, l);\n\t\tp += l;\n\n\t\tif (p[0] == '\\0')\n\t\t\tbreak;\n\n\t\tstrcat(res, \"\\\\\");\n\t\tstrncat(res, p++, 1);\n\t}\n\n\tstrcat(res, \"\\\"\");\n\treturn res;\n}\n\nstruct sym_match {\n\tstruct symbol\t*sym;\n\toff_t\t\tso, eo;\n};\n\n/* Compare matched symbols as thus:\n * - first, symbols that match exactly\n * - then, alphabetical sort\n */\nstatic int sym_rel_comp(const void *sym1, const void *sym2)\n{\n\tconst struct sym_match *s1 = sym1;\n\tconst struct sym_match *s2 = sym2;\n\tint exact1, exact2;\n\n\t/* Exact match:\n\t * - if matched length on symbol s1 is the length of that symbol,\n\t *   then this symbol should come first;\n\t * - if matched length on symbol s2 is the length of that symbol,\n\t *   then this symbol should come first.\n\t * Note: since the search can be a regexp, both symbols may match\n\t * exactly; if this is the case, we can't decide which comes first,\n\t * and we fallback to sorting alphabetically.\n\t */\n\texact1 = (s1->eo - s1->so) == strlen(s1->sym->name);\n\texact2 = (s2->eo - s2->so) == strlen(s2->sym->name);\n\tif (exact1 && !exact2)\n\t\treturn -1;\n\tif (!exact1 && exact2)\n\t\treturn 1;\n\n\t/* As a fallback, sort symbols alphabetically */\n\treturn strcmp(s1->sym->name, s2->sym->name);\n}\n\nstruct symbol **sym_re_search(const char *pattern)\n{\n\tstruct symbol *sym, **sym_arr = NULL;\n\tstruct sym_match *sym_match_arr = NULL;\n\tint i, cnt, size;\n\tregex_t re;\n\tregmatch_t match[1];\n\n\tcnt = size = 0;\n\t/* Skip if empty */\n\tif (strlen(pattern) == 0)\n\t\treturn NULL;\n\tif (regcomp(&re, pattern, REG_EXTENDED|REG_ICASE))\n\t\treturn NULL;\n\n\tfor_all_symbols(i, sym) {\n\t\tif (sym->flags & SYMBOL_CONST || !sym->name)\n\t\t\tcontinue;\n\t\tif (regexec(&re, sym->name, 1, match, 0))\n\t\t\tcontinue;\n\t\tif (cnt >= size) {\n\t\t\tvoid *tmp;\n\t\t\tsize += 16;\n\t\t\ttmp = realloc(sym_match_arr, size * sizeof(struct sym_match));\n\t\t\tif (!tmp)\n\t\t\t\tgoto sym_re_search_free;\n\t\t\tsym_match_arr = tmp;\n\t\t}\n\t\tsym_calc_value(sym);\n\t\t/* As regexec returned 0, we know we have a match, so\n\t\t * we can use match[0].rm_[se]o without further checks\n\t\t */\n\t\tsym_match_arr[cnt].so = match[0].rm_so;\n\t\tsym_match_arr[cnt].eo = match[0].rm_eo;\n\t\tsym_match_arr[cnt++].sym = sym;\n\t}\n\tif (sym_match_arr) {\n\t\tqsort(sym_match_arr, cnt, sizeof(struct sym_match), sym_rel_comp);\n\t\tsym_arr = malloc((cnt+1) * sizeof(struct symbol *));\n\t\tif (!sym_arr)\n\t\t\tgoto sym_re_search_free;\n\t\tfor (i = 0; i < cnt; i++)\n\t\t\tsym_arr[i] = sym_match_arr[i].sym;\n\t\tsym_arr[cnt] = NULL;\n\t}\nsym_re_search_free:\n\t/* sym_match_arr can be NULL if no match, but free(NULL) is OK */\n\tfree(sym_match_arr);\n\tregfree(&re);\n\n\treturn sym_arr;\n}\n\n/*\n * When we check for recursive dependencies we use a stack to save\n * current state so we can print out relevant info to user.\n * The entries are located on the call stack so no need to free memory.\n * Note insert() remove() must always match to properly clear the stack.\n */\nstatic struct dep_stack {\n\tstruct dep_stack *prev, *next;\n\tstruct symbol *sym;\n\tstruct property *prop;\n\tstruct expr **expr;\n} *check_top;\n\nstatic void dep_stack_insert(struct dep_stack *stack, struct symbol *sym)\n{\n\tmemset(stack, 0, sizeof(*stack));\n\tif (check_top)\n\t\tcheck_top->next = stack;\n\tstack->prev = check_top;\n\tstack->sym = sym;\n\tcheck_top = stack;\n}\n\nstatic void dep_stack_remove(void)\n{\n\tcheck_top = check_top->prev;\n\tif (check_top)\n\t\tcheck_top->next = NULL;\n}\n\n/*\n * Called when we have detected a recursive dependency.\n * check_top point to the top of the stact so we use\n * the ->prev pointer to locate the bottom of the stack.\n */\nstatic void sym_check_print_recursive(struct symbol *last_sym)\n{\n\tstruct dep_stack *stack;\n\tstruct symbol *sym, *next_sym;\n\tstruct menu *menu = NULL;\n\tstruct property *prop;\n\tstruct dep_stack cv_stack;\n\n\tif (sym_is_choice_value(last_sym)) {\n\t\tdep_stack_insert(&cv_stack, last_sym);\n\t\tlast_sym = prop_get_symbol(sym_get_choice_prop(last_sym));\n\t}\n\n\tfor (stack = check_top; stack != NULL; stack = stack->prev)\n\t\tif (stack->sym == last_sym)\n\t\t\tbreak;\n\tif (!stack) {\n\t\tfprintf(stderr, \"unexpected recursive dependency error\\n\");\n\t\treturn;\n\t}\n\n\tfor (; stack; stack = stack->next) {\n\t\tsym = stack->sym;\n\t\tnext_sym = stack->next ? stack->next->sym : last_sym;\n\t\tprop = stack->prop;\n\t\tif (prop == NULL)\n\t\t\tprop = stack->sym->prop;\n\n\t\t/* for choice values find the menu entry (used below) */\n\t\tif (sym_is_choice(sym) || sym_is_choice_value(sym)) {\n\t\t\tfor (prop = sym->prop; prop; prop = prop->next) {\n\t\t\t\tmenu = prop->menu;\n\t\t\t\tif (prop->menu)\n\t\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t\tif (stack->sym == last_sym)\n\t\t\tfprintf(stderr, \"%s:%d:error: recursive dependency detected!\\n\",\n\t\t\t\tprop->file->name, prop->lineno);\n\n\t\tif (sym_is_choice(sym)) {\n\t\t\tfprintf(stderr, \"%s:%d:\\tchoice %s contains symbol %s\\n\",\n\t\t\t\tmenu->file->name, menu->lineno,\n\t\t\t\tsym->name ? sym->name : \"<choice>\",\n\t\t\t\tnext_sym->name ? next_sym->name : \"<choice>\");\n\t\t} else if (sym_is_choice_value(sym)) {\n\t\t\tfprintf(stderr, \"%s:%d:\\tsymbol %s is part of choice %s\\n\",\n\t\t\t\tmenu->file->name, menu->lineno,\n\t\t\t\tsym->name ? sym->name : \"<choice>\",\n\t\t\t\tnext_sym->name ? next_sym->name : \"<choice>\");\n\t\t} else if (stack->expr == &sym->dir_dep.expr) {\n\t\t\tfprintf(stderr, \"%s:%d:\\tsymbol %s depends on %s\\n\",\n\t\t\t\tprop->file->name, prop->lineno,\n\t\t\t\tsym->name ? sym->name : \"<choice>\",\n\t\t\t\tnext_sym->name ? next_sym->name : \"<choice>\");\n\t\t} else if (stack->expr == &sym->rev_dep.expr) {\n\t\t\tfprintf(stderr, \"%s:%d:\\tsymbol %s is selected by %s\\n\",\n\t\t\t\tprop->file->name, prop->lineno,\n\t\t\t\tsym->name ? sym->name : \"<choice>\",\n\t\t\t\tnext_sym->name ? next_sym->name : \"<choice>\");\n\t\t} else if (stack->expr == &sym->implied.expr) {\n\t\t\tfprintf(stderr, \"%s:%d:\\tsymbol %s is implied by %s\\n\",\n\t\t\t\tprop->file->name, prop->lineno,\n\t\t\t\tsym->name ? sym->name : \"<choice>\",\n\t\t\t\tnext_sym->name ? next_sym->name : \"<choice>\");\n\t\t} else if (stack->expr) {\n\t\t\tfprintf(stderr, \"%s:%d:\\tsymbol %s %s value contains %s\\n\",\n\t\t\t\tprop->file->name, prop->lineno,\n\t\t\t\tsym->name ? sym->name : \"<choice>\",\n\t\t\t\tprop_get_type_name(prop->type),\n\t\t\t\tnext_sym->name ? next_sym->name : \"<choice>\");\n\t\t} else {\n\t\t\tfprintf(stderr, \"%s:%d:\\tsymbol %s %s is visible depending on %s\\n\",\n\t\t\t\tprop->file->name, prop->lineno,\n\t\t\t\tsym->name ? sym->name : \"<choice>\",\n\t\t\t\tprop_get_type_name(prop->type),\n\t\t\t\tnext_sym->name ? next_sym->name : \"<choice>\");\n\t\t}\n\t}\n\n\tfprintf(stderr,\n\t\t\"For a resolution refer to Documentation/kbuild/kconfig-language.rst\\n\"\n\t\t\"subsection \\\"Kconfig recursive dependency limitations\\\"\\n\"\n\t\t\"\\n\");\n\n\tif (check_top == &cv_stack)\n\t\tdep_stack_remove();\n}\n\nstatic struct symbol *sym_check_expr_deps(struct expr *e)\n{\n\tstruct symbol *sym;\n\n\tif (!e)\n\t\treturn NULL;\n\tswitch (e->type) {\n\tcase E_OR:\n\tcase E_AND:\n\t\tsym = sym_check_expr_deps(e->left.expr);\n\t\tif (sym)\n\t\t\treturn sym;\n\t\treturn sym_check_expr_deps(e->right.expr);\n\tcase E_NOT:\n\t\treturn sym_check_expr_deps(e->left.expr);\n\tcase E_EQUAL:\n\tcase E_GEQ:\n\tcase E_GTH:\n\tcase E_LEQ:\n\tcase E_LTH:\n\tcase E_UNEQUAL:\n\t\tsym = sym_check_deps(e->left.sym);\n\t\tif (sym)\n\t\t\treturn sym;\n\t\treturn sym_check_deps(e->right.sym);\n\tcase E_SYMBOL:\n\t\treturn sym_check_deps(e->left.sym);\n\tdefault:\n\t\tbreak;\n\t}\n\tfprintf(stderr, \"Oops! How to check %d?\\n\", e->type);\n\treturn NULL;\n}\n\n/* return NULL when dependencies are OK */\nstatic struct symbol *sym_check_sym_deps(struct symbol *sym)\n{\n\tstruct symbol *sym2;\n\tstruct property *prop;\n\tstruct dep_stack stack;\n\n\tdep_stack_insert(&stack, sym);\n\n\tstack.expr = &sym->dir_dep.expr;\n\tsym2 = sym_check_expr_deps(sym->dir_dep.expr);\n\tif (sym2)\n\t\tgoto out;\n\n\tstack.expr = &sym->rev_dep.expr;\n\tsym2 = sym_check_expr_deps(sym->rev_dep.expr);\n\tif (sym2)\n\t\tgoto out;\n\n\tstack.expr = &sym->implied.expr;\n\tsym2 = sym_check_expr_deps(sym->implied.expr);\n\tif (sym2)\n\t\tgoto out;\n\n\tstack.expr = NULL;\n\n\tfor (prop = sym->prop; prop; prop = prop->next) {\n\t\tif (prop->type == P_CHOICE || prop->type == P_SELECT ||\n\t\t    prop->type == P_IMPLY)\n\t\t\tcontinue;\n\t\tstack.prop = prop;\n\t\tsym2 = sym_check_expr_deps(prop->visible.expr);\n\t\tif (sym2)\n\t\t\tbreak;\n\t\tif (prop->type != P_DEFAULT || sym_is_choice(sym))\n\t\t\tcontinue;\n\t\tstack.expr = &prop->expr;\n\t\tsym2 = sym_check_expr_deps(prop->expr);\n\t\tif (sym2)\n\t\t\tbreak;\n\t\tstack.expr = NULL;\n\t}\n\nout:\n\tdep_stack_remove();\n\n\treturn sym2;\n}\n\nstatic struct symbol *sym_check_choice_deps(struct symbol *choice)\n{\n\tstruct symbol *sym, *sym2;\n\tstruct property *prop;\n\tstruct expr *e;\n\tstruct dep_stack stack;\n\n\tdep_stack_insert(&stack, choice);\n\n\tprop = sym_get_choice_prop(choice);\n\texpr_list_for_each_sym(prop->expr, e, sym)\n\t\tsym->flags |= (SYMBOL_CHECK | SYMBOL_CHECKED);\n\n\tchoice->flags |= (SYMBOL_CHECK | SYMBOL_CHECKED);\n\tsym2 = sym_check_sym_deps(choice);\n\tchoice->flags &= ~SYMBOL_CHECK;\n\tif (sym2)\n\t\tgoto out;\n\n\texpr_list_for_each_sym(prop->expr, e, sym) {\n\t\tsym2 = sym_check_sym_deps(sym);\n\t\tif (sym2)\n\t\t\tbreak;\n\t}\nout:\n\texpr_list_for_each_sym(prop->expr, e, sym)\n\t\tsym->flags &= ~SYMBOL_CHECK;\n\n\tif (sym2 && sym_is_choice_value(sym2) &&\n\t    prop_get_symbol(sym_get_choice_prop(sym2)) == choice)\n\t\tsym2 = choice;\n\n\tdep_stack_remove();\n\n\treturn sym2;\n}\n\nstruct symbol *sym_check_deps(struct symbol *sym)\n{\n\tstruct symbol *sym2;\n\tstruct property *prop;\n\n\tif (sym->flags & SYMBOL_CHECK) {\n\t\tsym_check_print_recursive(sym);\n\t\treturn sym;\n\t}\n\tif (sym->flags & SYMBOL_CHECKED)\n\t\treturn NULL;\n\n\tif (sym_is_choice_value(sym)) {\n\t\tstruct dep_stack stack;\n\n\t\t/* for choice groups start the check with main choice symbol */\n\t\tdep_stack_insert(&stack, sym);\n\t\tprop = sym_get_choice_prop(sym);\n\t\tsym2 = sym_check_deps(prop_get_symbol(prop));\n\t\tdep_stack_remove();\n\t} else if (sym_is_choice(sym)) {\n\t\tsym2 = sym_check_choice_deps(sym);\n\t} else {\n\t\tsym->flags |= (SYMBOL_CHECK | SYMBOL_CHECKED);\n\t\tsym2 = sym_check_sym_deps(sym);\n\t\tsym->flags &= ~SYMBOL_CHECK;\n\t}\n\n\tif (!recursive_is_error && sym2 && sym2 == sym)\n\t\tsym2 = NULL;\n\n\treturn sym2;\n}\n\nstruct symbol *prop_get_symbol(struct property *prop)\n{\n\tif (prop->expr && (prop->expr->type == E_SYMBOL ||\n\t\t\t   prop->expr->type == E_LIST))\n\t\treturn prop->expr->left.sym;\n\treturn NULL;\n}\n\nconst char *prop_get_type_name(enum prop_type type)\n{\n\tswitch (type) {\n\tcase P_PROMPT:\n\t\treturn \"prompt\";\n\tcase P_COMMENT:\n\t\treturn \"comment\";\n\tcase P_MENU:\n\t\treturn \"menu\";\n\tcase P_DEFAULT:\n\t\treturn \"default\";\n\tcase P_CHOICE:\n\t\treturn \"choice\";\n\tcase P_SELECT:\n\t\treturn \"select\";\n\tcase P_IMPLY:\n\t\treturn \"imply\";\n\tcase P_RANGE:\n\t\treturn \"range\";\n\tcase P_SYMBOL:\n\t\treturn \"symbol\";\n\tcase P_RESET:\n\t\treturn \"reset\";\n\tcase P_UNKNOWN:\n\t\tbreak;\n\t}\n\treturn \"unknown\";\n}\n"
  },
  {
    "path": "scripts/config/util.c",
    "content": "// SPDX-License-Identifier: GPL-2.0-only\n/*\n * Copyright (C) 2002-2005 Roman Zippel <zippel@linux-m68k.org>\n * Copyright (C) 2002-2005 Sam Ravnborg <sam@ravnborg.org>\n */\n\n#include <stdarg.h>\n#include <stdlib.h>\n#include <string.h>\n#include \"lkc.h\"\n\n/* file already present in list? If not add it */\nstruct file *file_lookup(const char *name)\n{\n\tstruct file *file;\n\n\tfor (file = file_list; file; file = file->next) {\n\t\tif (!strcmp(name, file->name)) {\n\t\t\treturn file;\n\t\t}\n\t}\n\n\tfile = xmalloc(sizeof(*file));\n\tmemset(file, 0, sizeof(*file));\n\tfile->name = xstrdup(name);\n\tfile->next = file_list;\n\tfile_list = file;\n\treturn file;\n}\n\n/* Allocate initial growable string */\nstruct gstr str_new(void)\n{\n\tstruct gstr gs;\n\tgs.s = xmalloc(sizeof(char) * 64);\n\tgs.len = 64;\n\tgs.max_width = 0;\n\tstrcpy(gs.s, \"\\0\");\n\treturn gs;\n}\n\n/* Free storage for growable string */\nvoid str_free(struct gstr *gs)\n{\n\tif (gs->s)\n\t\tfree(gs->s);\n\tgs->s = NULL;\n\tgs->len = 0;\n}\n\n/* Append to growable string */\nvoid str_append(struct gstr *gs, const char *s)\n{\n\tsize_t l;\n\tif (s) {\n\t\tl = strlen(gs->s) + strlen(s) + 1;\n\t\tif (l > gs->len) {\n\t\t\tgs->s = xrealloc(gs->s, l);\n\t\t\tgs->len = l;\n\t\t}\n\t\tstrcat(gs->s, s);\n\t}\n}\n\n/* Append printf formatted string to growable string */\nvoid str_printf(struct gstr *gs, const char *fmt, ...)\n{\n\tva_list ap;\n\tchar s[10000]; /* big enough... */\n\tva_start(ap, fmt);\n\tvsnprintf(s, sizeof(s), fmt, ap);\n\tstr_append(gs, s);\n\tva_end(ap);\n}\n\n/* Retrieve value of growable string */\nconst char *str_get(struct gstr *gs)\n{\n\treturn gs->s;\n}\n\nvoid *xmalloc(size_t size)\n{\n\tvoid *p = malloc(size);\n\tif (p)\n\t\treturn p;\n\tfprintf(stderr, \"Out of memory.\\n\");\n\texit(1);\n}\n\nvoid *xcalloc(size_t nmemb, size_t size)\n{\n\tvoid *p = calloc(nmemb, size);\n\tif (p)\n\t\treturn p;\n\tfprintf(stderr, \"Out of memory.\\n\");\n\texit(1);\n}\n\nvoid *xrealloc(void *p, size_t size)\n{\n\tp = realloc(p, size);\n\tif (p)\n\t\treturn p;\n\tfprintf(stderr, \"Out of memory.\\n\");\n\texit(1);\n}\n\nchar *xstrdup(const char *s)\n{\n\tchar *p;\n\n\tp = strdup(s);\n\tif (p)\n\t\treturn p;\n\tfprintf(stderr, \"Out of memory.\\n\");\n\texit(1);\n}\n\nchar *xstrndup(const char *s, size_t n)\n{\n\tchar *p;\n\n\tp = strndup(s, n);\n\tif (p)\n\t\treturn p;\n\tfprintf(stderr, \"Out of memory.\\n\");\n\texit(1);\n}\n"
  },
  {
    "path": "scripts/config.guess",
    "content": "#! /bin/sh\n# Attempt to guess a canonical system name.\n#   Copyright 1992-2021 Free Software Foundation, Inc.\n\ntimestamp='2021-05-24'\n\n# This file is free software; you can redistribute it and/or modify it\n# under the terms of the GNU General Public License as published by\n# the Free Software Foundation; either version 3 of the License, or\n# (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful, but\n# WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\n# General Public License for more details.\n#\n# You should have received a copy of the GNU General Public License\n# along with this program; if not, see <https://www.gnu.org/licenses/>.\n#\n# As a special exception to the GNU General Public License, if you\n# distribute this file as part of a program that contains a\n# configuration script generated by Autoconf, you may include it under\n# the same distribution terms that you use for the rest of that\n# program.  This Exception is an additional permission under section 7\n# of the GNU General Public License, version 3 (\"GPLv3\").\n#\n# Originally written by Per Bothner; maintained since 2000 by Ben Elliston.\n#\n# You can get the latest version of this script from:\n# https://git.savannah.gnu.org/cgit/config.git/plain/config.guess\n#\n# Please send patches to <config-patches@gnu.org>.\n\n\nme=$(echo \"$0\" | sed -e 's,.*/,,')\n\nusage=\"\\\nUsage: $0 [OPTION]\n\nOutput the configuration name of the system \\`$me' is run on.\n\nOptions:\n  -h, --help         print this help, then exit\n  -t, --time-stamp   print date of last modification, then exit\n  -v, --version      print version number, then exit\n\nReport bugs and patches to <config-patches@gnu.org>.\"\n\nversion=\"\\\nGNU config.guess ($timestamp)\n\nOriginally written by Per Bothner.\nCopyright 1992-2021 Free Software Foundation, Inc.\n\nThis is free software; see the source for copying conditions.  There is NO\nwarranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.\"\n\nhelp=\"\nTry \\`$me --help' for more information.\"\n\n# Parse command line\nwhile test $# -gt 0 ; do\n  case $1 in\n    --time-stamp | --time* | -t )\n       echo \"$timestamp\" ; exit ;;\n    --version | -v )\n       echo \"$version\" ; exit ;;\n    --help | --h* | -h )\n       echo \"$usage\"; exit ;;\n    -- )     # Stop option processing\n       shift; break ;;\n    - )\t# Use stdin as input.\n       break ;;\n    -* )\n       echo \"$me: invalid option $1$help\" >&2\n       exit 1 ;;\n    * )\n       break ;;\n  esac\ndone\n\nif test $# != 0; then\n  echo \"$me: too many arguments$help\" >&2\n  exit 1\nfi\n\n# CC_FOR_BUILD -- compiler used by this script. Note that the use of a\n# compiler to aid in system detection is discouraged as it requires\n# temporary files to be created and, as you can see below, it is a\n# headache to deal with in a portable fashion.\n\n# Historically, `CC_FOR_BUILD' used to be named `HOST_CC'. We still\n# use `HOST_CC' if defined, but it is deprecated.\n\n# Portable tmp directory creation inspired by the Autoconf team.\n\ntmp=\n# shellcheck disable=SC2172\ntrap 'test -z \"$tmp\" || rm -fr \"$tmp\"' 0 1 2 13 15\n\nset_cc_for_build() {\n    # prevent multiple calls if $tmp is already set\n    test \"$tmp\" && return 0\n    : \"${TMPDIR=/tmp}\"\n    # shellcheck disable=SC2039\n    { tmp=$( (umask 077 && mktemp -d \"$TMPDIR/cgXXXXXX\") 2>/dev/null) && test -n \"$tmp\" && test -d \"$tmp\" ; } ||\n\t{ test -n \"$RANDOM\" && tmp=$TMPDIR/cg$$-$RANDOM && (umask 077 && mkdir \"$tmp\" 2>/dev/null) ; } ||\n\t{ tmp=$TMPDIR/cg-$$ && (umask 077 && mkdir \"$tmp\" 2>/dev/null) && echo \"Warning: creating insecure temp directory\" >&2 ; } ||\n\t{ echo \"$me: cannot create a temporary directory in $TMPDIR\" >&2 ; exit 1 ; }\n    dummy=$tmp/dummy\n    case ${CC_FOR_BUILD-},${HOST_CC-},${CC-} in\n\t,,)    echo \"int x;\" > \"$dummy.c\"\n\t       for driver in cc gcc c89 c99 ; do\n\t\t   if ($driver -c -o \"$dummy.o\" \"$dummy.c\") >/dev/null 2>&1 ; then\n\t\t       CC_FOR_BUILD=\"$driver\"\n\t\t       break\n\t\t   fi\n\t       done\n\t       if test x\"$CC_FOR_BUILD\" = x ; then\n\t\t   CC_FOR_BUILD=no_compiler_found\n\t       fi\n\t       ;;\n\t,,*)   CC_FOR_BUILD=$CC ;;\n\t,*,*)  CC_FOR_BUILD=$HOST_CC ;;\n    esac\n}\n\n# This is needed to find uname on a Pyramid OSx when run in the BSD universe.\n# (ghazi@noc.rutgers.edu 1994-08-24)\nif test -f /.attbin/uname ; then\n\tPATH=$PATH:/.attbin ; export PATH\nfi\n\nUNAME_MACHINE=$( (uname -m) 2>/dev/null) || UNAME_MACHINE=unknown\nUNAME_RELEASE=$( (uname -r) 2>/dev/null) || UNAME_RELEASE=unknown\nUNAME_SYSTEM=$( (uname -s) 2>/dev/null) || UNAME_SYSTEM=unknown\nUNAME_VERSION=$( (uname -v) 2>/dev/null) || UNAME_VERSION=unknown\n\ncase $UNAME_SYSTEM in\nLinux|GNU|GNU/*)\n\tLIBC=unknown\n\n\tset_cc_for_build\n\tcat <<-EOF > \"$dummy.c\"\n\t#include <features.h>\n\t#if defined(__UCLIBC__)\n\tLIBC=uclibc\n\t#elif defined(__dietlibc__)\n\tLIBC=dietlibc\n\t#elif defined(__GLIBC__)\n\tLIBC=gnu\n\t#else\n\t#include <stdarg.h>\n\t/* First heuristic to detect musl libc.  */\n\t#ifdef __DEFINED_va_list\n\tLIBC=musl\n\t#endif\n\t#endif\n\tEOF\n\teval \"$($CC_FOR_BUILD -E \"$dummy.c\" 2>/dev/null | grep '^LIBC' | sed 's, ,,g')\"\n\n\t# Second heuristic to detect musl libc.\n\tif [ \"$LIBC\" = unknown ] &&\n\t   command -v ldd >/dev/null &&\n\t   ldd --version 2>&1 | grep -q ^musl; then\n\t\tLIBC=musl\n\tfi\n\n\t# If the system lacks a compiler, then just pick glibc.\n\t# We could probably try harder.\n\tif [ \"$LIBC\" = unknown ]; then\n\t\tLIBC=gnu\n\tfi\n\t;;\nesac\n\n# Note: order is significant - the case branches are not exclusive.\n\ncase $UNAME_MACHINE:$UNAME_SYSTEM:$UNAME_RELEASE:$UNAME_VERSION in\n    *:NetBSD:*:*)\n\t# NetBSD (nbsd) targets should (where applicable) match one or\n\t# more of the tuples: *-*-netbsdelf*, *-*-netbsdaout*,\n\t# *-*-netbsdecoff* and *-*-netbsd*.  For targets that recently\n\t# switched to ELF, *-*-netbsd* would select the old\n\t# object file format.  This provides both forward\n\t# compatibility and a consistent mechanism for selecting the\n\t# object file format.\n\t#\n\t# Note: NetBSD doesn't particularly care about the vendor\n\t# portion of the name.  We always set it to \"unknown\".\n\tUNAME_MACHINE_ARCH=$( (uname -p 2>/dev/null || \\\n\t    /sbin/sysctl -n hw.machine_arch 2>/dev/null || \\\n\t    /usr/sbin/sysctl -n hw.machine_arch 2>/dev/null || \\\n\t    echo unknown))\n\tcase $UNAME_MACHINE_ARCH in\n\t    aarch64eb) machine=aarch64_be-unknown ;;\n\t    armeb) machine=armeb-unknown ;;\n\t    arm*) machine=arm-unknown ;;\n\t    sh3el) machine=shl-unknown ;;\n\t    sh3eb) machine=sh-unknown ;;\n\t    sh5el) machine=sh5le-unknown ;;\n\t    earmv*)\n\t\tarch=$(echo \"$UNAME_MACHINE_ARCH\" | sed -e 's,^e\\(armv[0-9]\\).*$,\\1,')\n\t\tendian=$(echo \"$UNAME_MACHINE_ARCH\" | sed -ne 's,^.*\\(eb\\)$,\\1,p')\n\t\tmachine=\"${arch}${endian}\"-unknown\n\t\t;;\n\t    *) machine=\"$UNAME_MACHINE_ARCH\"-unknown ;;\n\tesac\n\t# The Operating System including object format, if it has switched\n\t# to ELF recently (or will in the future) and ABI.\n\tcase $UNAME_MACHINE_ARCH in\n\t    earm*)\n\t\tos=netbsdelf\n\t\t;;\n\t    arm*|i386|m68k|ns32k|sh3*|sparc|vax)\n\t\tset_cc_for_build\n\t\tif echo __ELF__ | $CC_FOR_BUILD -E - 2>/dev/null \\\n\t\t\t| grep -q __ELF__\n\t\tthen\n\t\t    # Once all utilities can be ECOFF (netbsdecoff) or a.out (netbsdaout).\n\t\t    # Return netbsd for either.  FIX?\n\t\t    os=netbsd\n\t\telse\n\t\t    os=netbsdelf\n\t\tfi\n\t\t;;\n\t    *)\n\t\tos=netbsd\n\t\t;;\n\tesac\n\t# Determine ABI tags.\n\tcase $UNAME_MACHINE_ARCH in\n\t    earm*)\n\t\texpr='s/^earmv[0-9]/-eabi/;s/eb$//'\n\t\tabi=$(echo \"$UNAME_MACHINE_ARCH\" | sed -e \"$expr\")\n\t\t;;\n\tesac\n\t# The OS release\n\t# Debian GNU/NetBSD machines have a different userland, and\n\t# thus, need a distinct triplet. However, they do not need\n\t# kernel version information, so it can be replaced with a\n\t# suitable tag, in the style of linux-gnu.\n\tcase $UNAME_VERSION in\n\t    Debian*)\n\t\trelease='-gnu'\n\t\t;;\n\t    *)\n\t\trelease=$(echo \"$UNAME_RELEASE\" | sed -e 's/[-_].*//' | cut -d. -f1,2)\n\t\t;;\n\tesac\n\t# Since CPU_TYPE-MANUFACTURER-KERNEL-OPERATING_SYSTEM:\n\t# contains redundant information, the shorter form:\n\t# CPU_TYPE-MANUFACTURER-OPERATING_SYSTEM is used.\n\techo \"$machine-${os}${release}${abi-}\"\n\texit ;;\n    *:Bitrig:*:*)\n\tUNAME_MACHINE_ARCH=$(arch | sed 's/Bitrig.//')\n\techo \"$UNAME_MACHINE_ARCH\"-unknown-bitrig\"$UNAME_RELEASE\"\n\texit ;;\n    *:OpenBSD:*:*)\n\tUNAME_MACHINE_ARCH=$(arch | sed 's/OpenBSD.//')\n\techo \"$UNAME_MACHINE_ARCH\"-unknown-openbsd\"$UNAME_RELEASE\"\n\texit ;;\n    *:SecBSD:*:*)\n\tUNAME_MACHINE_ARCH=$(arch | sed 's/SecBSD.//')\n\techo \"$UNAME_MACHINE_ARCH\"-unknown-secbsd\"$UNAME_RELEASE\"\n\texit ;;\n    *:LibertyBSD:*:*)\n\tUNAME_MACHINE_ARCH=$(arch | sed 's/^.*BSD\\.//')\n\techo \"$UNAME_MACHINE_ARCH\"-unknown-libertybsd\"$UNAME_RELEASE\"\n\texit ;;\n    *:MidnightBSD:*:*)\n\techo \"$UNAME_MACHINE\"-unknown-midnightbsd\"$UNAME_RELEASE\"\n\texit ;;\n    *:ekkoBSD:*:*)\n\techo \"$UNAME_MACHINE\"-unknown-ekkobsd\"$UNAME_RELEASE\"\n\texit ;;\n    *:SolidBSD:*:*)\n\techo \"$UNAME_MACHINE\"-unknown-solidbsd\"$UNAME_RELEASE\"\n\texit ;;\n    *:OS108:*:*)\n\techo \"$UNAME_MACHINE\"-unknown-os108_\"$UNAME_RELEASE\"\n\texit ;;\n    macppc:MirBSD:*:*)\n\techo powerpc-unknown-mirbsd\"$UNAME_RELEASE\"\n\texit ;;\n    *:MirBSD:*:*)\n\techo \"$UNAME_MACHINE\"-unknown-mirbsd\"$UNAME_RELEASE\"\n\texit ;;\n    *:Sortix:*:*)\n\techo \"$UNAME_MACHINE\"-unknown-sortix\n\texit ;;\n    *:Twizzler:*:*)\n\techo \"$UNAME_MACHINE\"-unknown-twizzler\n\texit ;;\n    *:Redox:*:*)\n\techo \"$UNAME_MACHINE\"-unknown-redox\n\texit ;;\n    mips:OSF1:*.*)\n\techo mips-dec-osf1\n\texit ;;\n    alpha:OSF1:*:*)\n\t# Reset EXIT trap before exiting to avoid spurious non-zero exit code.\n\ttrap '' 0\n\tcase $UNAME_RELEASE in\n\t*4.0)\n\t\tUNAME_RELEASE=$(/usr/sbin/sizer -v | awk '{print $3}')\n\t\t;;\n\t*5.*)\n\t\tUNAME_RELEASE=$(/usr/sbin/sizer -v | awk '{print $4}')\n\t\t;;\n\tesac\n\t# According to Compaq, /usr/sbin/psrinfo has been available on\n\t# OSF/1 and Tru64 systems produced since 1995.  I hope that\n\t# covers most systems running today.  This code pipes the CPU\n\t# types through head -n 1, so we only detect the type of CPU 0.\n\tALPHA_CPU_TYPE=$(/usr/sbin/psrinfo -v | sed -n -e 's/^  The alpha \\(.*\\) processor.*$/\\1/p' | head -n 1)\n\tcase $ALPHA_CPU_TYPE in\n\t    \"EV4 (21064)\")\n\t\tUNAME_MACHINE=alpha ;;\n\t    \"EV4.5 (21064)\")\n\t\tUNAME_MACHINE=alpha ;;\n\t    \"LCA4 (21066/21068)\")\n\t\tUNAME_MACHINE=alpha ;;\n\t    \"EV5 (21164)\")\n\t\tUNAME_MACHINE=alphaev5 ;;\n\t    \"EV5.6 (21164A)\")\n\t\tUNAME_MACHINE=alphaev56 ;;\n\t    \"EV5.6 (21164PC)\")\n\t\tUNAME_MACHINE=alphapca56 ;;\n\t    \"EV5.7 (21164PC)\")\n\t\tUNAME_MACHINE=alphapca57 ;;\n\t    \"EV6 (21264)\")\n\t\tUNAME_MACHINE=alphaev6 ;;\n\t    \"EV6.7 (21264A)\")\n\t\tUNAME_MACHINE=alphaev67 ;;\n\t    \"EV6.8CB (21264C)\")\n\t\tUNAME_MACHINE=alphaev68 ;;\n\t    \"EV6.8AL (21264B)\")\n\t\tUNAME_MACHINE=alphaev68 ;;\n\t    \"EV6.8CX (21264D)\")\n\t\tUNAME_MACHINE=alphaev68 ;;\n\t    \"EV6.9A (21264/EV69A)\")\n\t\tUNAME_MACHINE=alphaev69 ;;\n\t    \"EV7 (21364)\")\n\t\tUNAME_MACHINE=alphaev7 ;;\n\t    \"EV7.9 (21364A)\")\n\t\tUNAME_MACHINE=alphaev79 ;;\n\tesac\n\t# A Pn.n version is a patched version.\n\t# A Vn.n version is a released version.\n\t# A Tn.n version is a released field test version.\n\t# A Xn.n version is an unreleased experimental baselevel.\n\t# 1.2 uses \"1.2\" for uname -r.\n\techo \"$UNAME_MACHINE\"-dec-osf\"$(echo \"$UNAME_RELEASE\" | sed -e 's/^[PVTX]//' | tr ABCDEFGHIJKLMNOPQRSTUVWXYZ abcdefghijklmnopqrstuvwxyz)\"\n\texit ;;\n    Amiga*:UNIX_System_V:4.0:*)\n\techo m68k-unknown-sysv4\n\texit ;;\n    *:[Aa]miga[Oo][Ss]:*:*)\n\techo \"$UNAME_MACHINE\"-unknown-amigaos\n\texit ;;\n    *:[Mm]orph[Oo][Ss]:*:*)\n\techo \"$UNAME_MACHINE\"-unknown-morphos\n\texit ;;\n    *:OS/390:*:*)\n\techo i370-ibm-openedition\n\texit ;;\n    *:z/VM:*:*)\n\techo s390-ibm-zvmoe\n\texit ;;\n    *:OS400:*:*)\n\techo powerpc-ibm-os400\n\texit ;;\n    arm:RISC*:1.[012]*:*|arm:riscix:1.[012]*:*)\n\techo arm-acorn-riscix\"$UNAME_RELEASE\"\n\texit ;;\n    arm*:riscos:*:*|arm*:RISCOS:*:*)\n\techo arm-unknown-riscos\n\texit ;;\n    SR2?01:HI-UX/MPP:*:* | SR8000:HI-UX/MPP:*:*)\n\techo hppa1.1-hitachi-hiuxmpp\n\texit ;;\n    Pyramid*:OSx*:*:* | MIS*:OSx*:*:* | MIS*:SMP_DC-OSx*:*:*)\n\t# akee@wpdis03.wpafb.af.mil (Earle F. Ake) contributed MIS and NILE.\n\tif test \"$( (/bin/universe) 2>/dev/null)\" = att ; then\n\t\techo pyramid-pyramid-sysv3\n\telse\n\t\techo pyramid-pyramid-bsd\n\tfi\n\texit ;;\n    NILE*:*:*:dcosx)\n\techo pyramid-pyramid-svr4\n\texit ;;\n    DRS?6000:unix:4.0:6*)\n\techo sparc-icl-nx6\n\texit ;;\n    DRS?6000:UNIX_SV:4.2*:7* | DRS?6000:isis:4.2*:7*)\n\tcase $(/usr/bin/uname -p) in\n\t    sparc) echo sparc-icl-nx7; exit ;;\n\tesac ;;\n    s390x:SunOS:*:*)\n\techo \"$UNAME_MACHINE\"-ibm-solaris2\"$(echo \"$UNAME_RELEASE\" | sed -e 's/[^.]*//')\"\n\texit ;;\n    sun4H:SunOS:5.*:*)\n\techo sparc-hal-solaris2\"$(echo \"$UNAME_RELEASE\"|sed -e 's/[^.]*//')\"\n\texit ;;\n    sun4*:SunOS:5.*:* | tadpole*:SunOS:5.*:*)\n\techo sparc-sun-solaris2\"$(echo \"$UNAME_RELEASE\" | sed -e 's/[^.]*//')\"\n\texit ;;\n    i86pc:AuroraUX:5.*:* | i86xen:AuroraUX:5.*:*)\n\techo i386-pc-auroraux\"$UNAME_RELEASE\"\n\texit ;;\n    i86pc:SunOS:5.*:* | i86xen:SunOS:5.*:*)\n\tset_cc_for_build\n\tSUN_ARCH=i386\n\t# If there is a compiler, see if it is configured for 64-bit objects.\n\t# Note that the Sun cc does not turn __LP64__ into 1 like gcc does.\n\t# This test works for both compilers.\n\tif test \"$CC_FOR_BUILD\" != no_compiler_found; then\n\t    if (echo '#ifdef __amd64'; echo IS_64BIT_ARCH; echo '#endif') | \\\n\t\t(CCOPTS=\"\" $CC_FOR_BUILD -E - 2>/dev/null) | \\\n\t\tgrep IS_64BIT_ARCH >/dev/null\n\t    then\n\t\tSUN_ARCH=x86_64\n\t    fi\n\tfi\n\techo \"$SUN_ARCH\"-pc-solaris2\"$(echo \"$UNAME_RELEASE\"|sed -e 's/[^.]*//')\"\n\texit ;;\n    sun4*:SunOS:6*:*)\n\t# According to config.sub, this is the proper way to canonicalize\n\t# SunOS6.  Hard to guess exactly what SunOS6 will be like, but\n\t# it's likely to be more like Solaris than SunOS4.\n\techo sparc-sun-solaris3\"$(echo \"$UNAME_RELEASE\"|sed -e 's/[^.]*//')\"\n\texit ;;\n    sun4*:SunOS:*:*)\n\tcase $(/usr/bin/arch -k) in\n\t    Series*|S4*)\n\t\tUNAME_RELEASE=$(uname -v)\n\t\t;;\n\tesac\n\t# Japanese Language versions have a version number like `4.1.3-JL'.\n\techo sparc-sun-sunos\"$(echo \"$UNAME_RELEASE\"|sed -e 's/-/_/')\"\n\texit ;;\n    sun3*:SunOS:*:*)\n\techo m68k-sun-sunos\"$UNAME_RELEASE\"\n\texit ;;\n    sun*:*:4.2BSD:*)\n\tUNAME_RELEASE=$( (sed 1q /etc/motd | awk '{print substr($5,1,3)}') 2>/dev/null)\n\ttest \"x$UNAME_RELEASE\" = x && UNAME_RELEASE=3\n\tcase $(/bin/arch) in\n\t    sun3)\n\t\techo m68k-sun-sunos\"$UNAME_RELEASE\"\n\t\t;;\n\t    sun4)\n\t\techo sparc-sun-sunos\"$UNAME_RELEASE\"\n\t\t;;\n\tesac\n\texit ;;\n    aushp:SunOS:*:*)\n\techo sparc-auspex-sunos\"$UNAME_RELEASE\"\n\texit ;;\n    # The situation for MiNT is a little confusing.  The machine name\n    # can be virtually everything (everything which is not\n    # \"atarist\" or \"atariste\" at least should have a processor\n    # > m68000).  The system name ranges from \"MiNT\" over \"FreeMiNT\"\n    # to the lowercase version \"mint\" (or \"freemint\").  Finally\n    # the system name \"TOS\" denotes a system which is actually not\n    # MiNT.  But MiNT is downward compatible to TOS, so this should\n    # be no problem.\n    atarist[e]:*MiNT:*:* | atarist[e]:*mint:*:* | atarist[e]:*TOS:*:*)\n\techo m68k-atari-mint\"$UNAME_RELEASE\"\n\texit ;;\n    atari*:*MiNT:*:* | atari*:*mint:*:* | atarist[e]:*TOS:*:*)\n\techo m68k-atari-mint\"$UNAME_RELEASE\"\n\texit ;;\n    *falcon*:*MiNT:*:* | *falcon*:*mint:*:* | *falcon*:*TOS:*:*)\n\techo m68k-atari-mint\"$UNAME_RELEASE\"\n\texit ;;\n    milan*:*MiNT:*:* | milan*:*mint:*:* | *milan*:*TOS:*:*)\n\techo m68k-milan-mint\"$UNAME_RELEASE\"\n\texit ;;\n    hades*:*MiNT:*:* | hades*:*mint:*:* | *hades*:*TOS:*:*)\n\techo m68k-hades-mint\"$UNAME_RELEASE\"\n\texit ;;\n    *:*MiNT:*:* | *:*mint:*:* | *:*TOS:*:*)\n\techo m68k-unknown-mint\"$UNAME_RELEASE\"\n\texit ;;\n    m68k:machten:*:*)\n\techo m68k-apple-machten\"$UNAME_RELEASE\"\n\texit ;;\n    powerpc:machten:*:*)\n\techo powerpc-apple-machten\"$UNAME_RELEASE\"\n\texit ;;\n    RISC*:Mach:*:*)\n\techo mips-dec-mach_bsd4.3\n\texit ;;\n    RISC*:ULTRIX:*:*)\n\techo mips-dec-ultrix\"$UNAME_RELEASE\"\n\texit ;;\n    VAX*:ULTRIX*:*:*)\n\techo vax-dec-ultrix\"$UNAME_RELEASE\"\n\texit ;;\n    2020:CLIX:*:* | 2430:CLIX:*:*)\n\techo clipper-intergraph-clix\"$UNAME_RELEASE\"\n\texit ;;\n    mips:*:*:UMIPS | mips:*:*:RISCos)\n\tset_cc_for_build\n\tsed 's/^\t//' << EOF > \"$dummy.c\"\n#ifdef __cplusplus\n#include <stdio.h>  /* for printf() prototype */\n\tint main (int argc, char *argv[]) {\n#else\n\tint main (argc, argv) int argc; char *argv[]; {\n#endif\n\t#if defined (host_mips) && defined (MIPSEB)\n\t#if defined (SYSTYPE_SYSV)\n\t  printf (\"mips-mips-riscos%ssysv\\\\n\", argv[1]); exit (0);\n\t#endif\n\t#if defined (SYSTYPE_SVR4)\n\t  printf (\"mips-mips-riscos%ssvr4\\\\n\", argv[1]); exit (0);\n\t#endif\n\t#if defined (SYSTYPE_BSD43) || defined(SYSTYPE_BSD)\n\t  printf (\"mips-mips-riscos%sbsd\\\\n\", argv[1]); exit (0);\n\t#endif\n\t#endif\n\t  exit (-1);\n\t}\nEOF\n\t$CC_FOR_BUILD -o \"$dummy\" \"$dummy.c\" &&\n\t  dummyarg=$(echo \"$UNAME_RELEASE\" | sed -n 's/\\([0-9]*\\).*/\\1/p') &&\n\t  SYSTEM_NAME=$(\"$dummy\" \"$dummyarg\") &&\n\t    { echo \"$SYSTEM_NAME\"; exit; }\n\techo mips-mips-riscos\"$UNAME_RELEASE\"\n\texit ;;\n    Motorola:PowerMAX_OS:*:*)\n\techo powerpc-motorola-powermax\n\texit ;;\n    Motorola:*:4.3:PL8-*)\n\techo powerpc-harris-powermax\n\texit ;;\n    Night_Hawk:*:*:PowerMAX_OS | Synergy:PowerMAX_OS:*:*)\n\techo powerpc-harris-powermax\n\texit ;;\n    Night_Hawk:Power_UNIX:*:*)\n\techo powerpc-harris-powerunix\n\texit ;;\n    m88k:CX/UX:7*:*)\n\techo m88k-harris-cxux7\n\texit ;;\n    m88k:*:4*:R4*)\n\techo m88k-motorola-sysv4\n\texit ;;\n    m88k:*:3*:R3*)\n\techo m88k-motorola-sysv3\n\texit ;;\n    AViiON:dgux:*:*)\n\t# DG/UX returns AViiON for all architectures\n\tUNAME_PROCESSOR=$(/usr/bin/uname -p)\n\tif test \"$UNAME_PROCESSOR\" = mc88100 || test \"$UNAME_PROCESSOR\" = mc88110\n\tthen\n\t    if test \"$TARGET_BINARY_INTERFACE\"x = m88kdguxelfx || \\\n\t       test \"$TARGET_BINARY_INTERFACE\"x = x\n\t    then\n\t\techo m88k-dg-dgux\"$UNAME_RELEASE\"\n\t    else\n\t\techo m88k-dg-dguxbcs\"$UNAME_RELEASE\"\n\t    fi\n\telse\n\t    echo i586-dg-dgux\"$UNAME_RELEASE\"\n\tfi\n\texit ;;\n    M88*:DolphinOS:*:*)\t# DolphinOS (SVR3)\n\techo m88k-dolphin-sysv3\n\texit ;;\n    M88*:*:R3*:*)\n\t# Delta 88k system running SVR3\n\techo m88k-motorola-sysv3\n\texit ;;\n    XD88*:*:*:*) # Tektronix XD88 system running UTekV (SVR3)\n\techo m88k-tektronix-sysv3\n\texit ;;\n    Tek43[0-9][0-9]:UTek:*:*) # Tektronix 4300 system running UTek (BSD)\n\techo m68k-tektronix-bsd\n\texit ;;\n    *:IRIX*:*:*)\n\techo mips-sgi-irix\"$(echo \"$UNAME_RELEASE\"|sed -e 's/-/_/g')\"\n\texit ;;\n    ????????:AIX?:[12].1:2)   # AIX 2.2.1 or AIX 2.1.1 is RT/PC AIX.\n\techo romp-ibm-aix     # uname -m gives an 8 hex-code CPU id\n\texit ;;               # Note that: echo \"'$(uname -s)'\" gives 'AIX '\n    i*86:AIX:*:*)\n\techo i386-ibm-aix\n\texit ;;\n    ia64:AIX:*:*)\n\tif test -x /usr/bin/oslevel ; then\n\t\tIBM_REV=$(/usr/bin/oslevel)\n\telse\n\t\tIBM_REV=\"$UNAME_VERSION.$UNAME_RELEASE\"\n\tfi\n\techo \"$UNAME_MACHINE\"-ibm-aix\"$IBM_REV\"\n\texit ;;\n    *:AIX:2:3)\n\tif grep bos325 /usr/include/stdio.h >/dev/null 2>&1; then\n\t\tset_cc_for_build\n\t\tsed 's/^\t\t//' << EOF > \"$dummy.c\"\n\t\t#include <sys/systemcfg.h>\n\n\t\tmain()\n\t\t\t{\n\t\t\tif (!__power_pc())\n\t\t\t\texit(1);\n\t\t\tputs(\"powerpc-ibm-aix3.2.5\");\n\t\t\texit(0);\n\t\t\t}\nEOF\n\t\tif $CC_FOR_BUILD -o \"$dummy\" \"$dummy.c\" && SYSTEM_NAME=$(\"$dummy\")\n\t\tthen\n\t\t\techo \"$SYSTEM_NAME\"\n\t\telse\n\t\t\techo rs6000-ibm-aix3.2.5\n\t\tfi\n\telif grep bos324 /usr/include/stdio.h >/dev/null 2>&1; then\n\t\techo rs6000-ibm-aix3.2.4\n\telse\n\t\techo rs6000-ibm-aix3.2\n\tfi\n\texit ;;\n    *:AIX:*:[4567])\n\tIBM_CPU_ID=$(/usr/sbin/lsdev -C -c processor -S available | sed 1q | awk '{ print $1 }')\n\tif /usr/sbin/lsattr -El \"$IBM_CPU_ID\" | grep ' POWER' >/dev/null 2>&1; then\n\t\tIBM_ARCH=rs6000\n\telse\n\t\tIBM_ARCH=powerpc\n\tfi\n\tif test -x /usr/bin/lslpp ; then\n\t\tIBM_REV=$(/usr/bin/lslpp -Lqc bos.rte.libc |\n\t\t\t   awk -F: '{ print $3 }' | sed s/[0-9]*$/0/)\n\telse\n\t\tIBM_REV=\"$UNAME_VERSION.$UNAME_RELEASE\"\n\tfi\n\techo \"$IBM_ARCH\"-ibm-aix\"$IBM_REV\"\n\texit ;;\n    *:AIX:*:*)\n\techo rs6000-ibm-aix\n\texit ;;\n    ibmrt:4.4BSD:*|romp-ibm:4.4BSD:*)\n\techo romp-ibm-bsd4.4\n\texit ;;\n    ibmrt:*BSD:*|romp-ibm:BSD:*)            # covers RT/PC BSD and\n\techo romp-ibm-bsd\"$UNAME_RELEASE\"   # 4.3 with uname added to\n\texit ;;                             # report: romp-ibm BSD 4.3\n    *:BOSX:*:*)\n\techo rs6000-bull-bosx\n\texit ;;\n    DPX/2?00:B.O.S.:*:*)\n\techo m68k-bull-sysv3\n\texit ;;\n    9000/[34]??:4.3bsd:1.*:*)\n\techo m68k-hp-bsd\n\texit ;;\n    hp300:4.4BSD:*:* | 9000/[34]??:4.3bsd:2.*:*)\n\techo m68k-hp-bsd4.4\n\texit ;;\n    9000/[34678]??:HP-UX:*:*)\n\tHPUX_REV=$(echo \"$UNAME_RELEASE\"|sed -e 's/[^.]*.[0B]*//')\n\tcase $UNAME_MACHINE in\n\t    9000/31?)            HP_ARCH=m68000 ;;\n\t    9000/[34]??)         HP_ARCH=m68k ;;\n\t    9000/[678][0-9][0-9])\n\t\tif test -x /usr/bin/getconf; then\n\t\t    sc_cpu_version=$(/usr/bin/getconf SC_CPU_VERSION 2>/dev/null)\n\t\t    sc_kernel_bits=$(/usr/bin/getconf SC_KERNEL_BITS 2>/dev/null)\n\t\t    case $sc_cpu_version in\n\t\t      523) HP_ARCH=hppa1.0 ;; # CPU_PA_RISC1_0\n\t\t      528) HP_ARCH=hppa1.1 ;; # CPU_PA_RISC1_1\n\t\t      532)                      # CPU_PA_RISC2_0\n\t\t\tcase $sc_kernel_bits in\n\t\t\t  32) HP_ARCH=hppa2.0n ;;\n\t\t\t  64) HP_ARCH=hppa2.0w ;;\n\t\t\t  '') HP_ARCH=hppa2.0 ;;   # HP-UX 10.20\n\t\t\tesac ;;\n\t\t    esac\n\t\tfi\n\t\tif test \"$HP_ARCH\" = \"\"; then\n\t\t    set_cc_for_build\n\t\t    sed 's/^\t\t//' << EOF > \"$dummy.c\"\n\n\t\t#define _HPUX_SOURCE\n\t\t#include <stdlib.h>\n\t\t#include <unistd.h>\n\n\t\tint main ()\n\t\t{\n\t\t#if defined(_SC_KERNEL_BITS)\n\t\t    long bits = sysconf(_SC_KERNEL_BITS);\n\t\t#endif\n\t\t    long cpu  = sysconf (_SC_CPU_VERSION);\n\n\t\t    switch (cpu)\n\t\t\t{\n\t\t\tcase CPU_PA_RISC1_0: puts (\"hppa1.0\"); break;\n\t\t\tcase CPU_PA_RISC1_1: puts (\"hppa1.1\"); break;\n\t\t\tcase CPU_PA_RISC2_0:\n\t\t#if defined(_SC_KERNEL_BITS)\n\t\t\t    switch (bits)\n\t\t\t\t{\n\t\t\t\tcase 64: puts (\"hppa2.0w\"); break;\n\t\t\t\tcase 32: puts (\"hppa2.0n\"); break;\n\t\t\t\tdefault: puts (\"hppa2.0\"); break;\n\t\t\t\t} break;\n\t\t#else  /* !defined(_SC_KERNEL_BITS) */\n\t\t\t    puts (\"hppa2.0\"); break;\n\t\t#endif\n\t\t\tdefault: puts (\"hppa1.0\"); break;\n\t\t\t}\n\t\t    exit (0);\n\t\t}\nEOF\n\t\t    (CCOPTS=\"\" $CC_FOR_BUILD -o \"$dummy\" \"$dummy.c\" 2>/dev/null) && HP_ARCH=$(\"$dummy\")\n\t\t    test -z \"$HP_ARCH\" && HP_ARCH=hppa\n\t\tfi ;;\n\tesac\n\tif test \"$HP_ARCH\" = hppa2.0w\n\tthen\n\t    set_cc_for_build\n\n\t    # hppa2.0w-hp-hpux* has a 64-bit kernel and a compiler generating\n\t    # 32-bit code.  hppa64-hp-hpux* has the same kernel and a compiler\n\t    # generating 64-bit code.  GNU and HP use different nomenclature:\n\t    #\n\t    # $ CC_FOR_BUILD=cc ./config.guess\n\t    # => hppa2.0w-hp-hpux11.23\n\t    # $ CC_FOR_BUILD=\"cc +DA2.0w\" ./config.guess\n\t    # => hppa64-hp-hpux11.23\n\n\t    if echo __LP64__ | (CCOPTS=\"\" $CC_FOR_BUILD -E - 2>/dev/null) |\n\t\tgrep -q __LP64__\n\t    then\n\t\tHP_ARCH=hppa2.0w\n\t    else\n\t\tHP_ARCH=hppa64\n\t    fi\n\tfi\n\techo \"$HP_ARCH\"-hp-hpux\"$HPUX_REV\"\n\texit ;;\n    ia64:HP-UX:*:*)\n\tHPUX_REV=$(echo \"$UNAME_RELEASE\"|sed -e 's/[^.]*.[0B]*//')\n\techo ia64-hp-hpux\"$HPUX_REV\"\n\texit ;;\n    3050*:HI-UX:*:*)\n\tset_cc_for_build\n\tsed 's/^\t//' << EOF > \"$dummy.c\"\n\t#include <unistd.h>\n\tint\n\tmain ()\n\t{\n\t  long cpu = sysconf (_SC_CPU_VERSION);\n\t  /* The order matters, because CPU_IS_HP_MC68K erroneously returns\n\t     true for CPU_PA_RISC1_0.  CPU_IS_PA_RISC returns correct\n\t     results, however.  */\n\t  if (CPU_IS_PA_RISC (cpu))\n\t    {\n\t      switch (cpu)\n\t\t{\n\t\t  case CPU_PA_RISC1_0: puts (\"hppa1.0-hitachi-hiuxwe2\"); break;\n\t\t  case CPU_PA_RISC1_1: puts (\"hppa1.1-hitachi-hiuxwe2\"); break;\n\t\t  case CPU_PA_RISC2_0: puts (\"hppa2.0-hitachi-hiuxwe2\"); break;\n\t\t  default: puts (\"hppa-hitachi-hiuxwe2\"); break;\n\t\t}\n\t    }\n\t  else if (CPU_IS_HP_MC68K (cpu))\n\t    puts (\"m68k-hitachi-hiuxwe2\");\n\t  else puts (\"unknown-hitachi-hiuxwe2\");\n\t  exit (0);\n\t}\nEOF\n\t$CC_FOR_BUILD -o \"$dummy\" \"$dummy.c\" && SYSTEM_NAME=$(\"$dummy\") &&\n\t\t{ echo \"$SYSTEM_NAME\"; exit; }\n\techo unknown-hitachi-hiuxwe2\n\texit ;;\n    9000/7??:4.3bsd:*:* | 9000/8?[79]:4.3bsd:*:*)\n\techo hppa1.1-hp-bsd\n\texit ;;\n    9000/8??:4.3bsd:*:*)\n\techo hppa1.0-hp-bsd\n\texit ;;\n    *9??*:MPE/iX:*:* | *3000*:MPE/iX:*:*)\n\techo hppa1.0-hp-mpeix\n\texit ;;\n    hp7??:OSF1:*:* | hp8?[79]:OSF1:*:*)\n\techo hppa1.1-hp-osf\n\texit ;;\n    hp8??:OSF1:*:*)\n\techo hppa1.0-hp-osf\n\texit ;;\n    i*86:OSF1:*:*)\n\tif test -x /usr/sbin/sysversion ; then\n\t    echo \"$UNAME_MACHINE\"-unknown-osf1mk\n\telse\n\t    echo \"$UNAME_MACHINE\"-unknown-osf1\n\tfi\n\texit ;;\n    parisc*:Lites*:*:*)\n\techo hppa1.1-hp-lites\n\texit ;;\n    C1*:ConvexOS:*:* | convex:ConvexOS:C1*:*)\n\techo c1-convex-bsd\n\texit ;;\n    C2*:ConvexOS:*:* | convex:ConvexOS:C2*:*)\n\tif getsysinfo -f scalar_acc\n\tthen echo c32-convex-bsd\n\telse echo c2-convex-bsd\n\tfi\n\texit ;;\n    C34*:ConvexOS:*:* | convex:ConvexOS:C34*:*)\n\techo c34-convex-bsd\n\texit ;;\n    C38*:ConvexOS:*:* | convex:ConvexOS:C38*:*)\n\techo c38-convex-bsd\n\texit ;;\n    C4*:ConvexOS:*:* | convex:ConvexOS:C4*:*)\n\techo c4-convex-bsd\n\texit ;;\n    CRAY*Y-MP:*:*:*)\n\techo ymp-cray-unicos\"$UNAME_RELEASE\" | sed -e 's/\\.[^.]*$/.X/'\n\texit ;;\n    CRAY*[A-Z]90:*:*:*)\n\techo \"$UNAME_MACHINE\"-cray-unicos\"$UNAME_RELEASE\" \\\n\t| sed -e 's/CRAY.*\\([A-Z]90\\)/\\1/' \\\n\t      -e y/ABCDEFGHIJKLMNOPQRSTUVWXYZ/abcdefghijklmnopqrstuvwxyz/ \\\n\t      -e 's/\\.[^.]*$/.X/'\n\texit ;;\n    CRAY*TS:*:*:*)\n\techo t90-cray-unicos\"$UNAME_RELEASE\" | sed -e 's/\\.[^.]*$/.X/'\n\texit ;;\n    CRAY*T3E:*:*:*)\n\techo alphaev5-cray-unicosmk\"$UNAME_RELEASE\" | sed -e 's/\\.[^.]*$/.X/'\n\texit ;;\n    CRAY*SV1:*:*:*)\n\techo sv1-cray-unicos\"$UNAME_RELEASE\" | sed -e 's/\\.[^.]*$/.X/'\n\texit ;;\n    *:UNICOS/mp:*:*)\n\techo craynv-cray-unicosmp\"$UNAME_RELEASE\" | sed -e 's/\\.[^.]*$/.X/'\n\texit ;;\n    F30[01]:UNIX_System_V:*:* | F700:UNIX_System_V:*:*)\n\tFUJITSU_PROC=$(uname -m | tr ABCDEFGHIJKLMNOPQRSTUVWXYZ abcdefghijklmnopqrstuvwxyz)\n\tFUJITSU_SYS=$(uname -p | tr ABCDEFGHIJKLMNOPQRSTUVWXYZ abcdefghijklmnopqrstuvwxyz | sed -e 's/\\///')\n\tFUJITSU_REL=$(echo \"$UNAME_RELEASE\" | sed -e 's/ /_/')\n\techo \"${FUJITSU_PROC}-fujitsu-${FUJITSU_SYS}${FUJITSU_REL}\"\n\texit ;;\n    5000:UNIX_System_V:4.*:*)\n\tFUJITSU_SYS=$(uname -p | tr ABCDEFGHIJKLMNOPQRSTUVWXYZ abcdefghijklmnopqrstuvwxyz | sed -e 's/\\///')\n\tFUJITSU_REL=$(echo \"$UNAME_RELEASE\" | tr ABCDEFGHIJKLMNOPQRSTUVWXYZ abcdefghijklmnopqrstuvwxyz | sed -e 's/ /_/')\n\techo \"sparc-fujitsu-${FUJITSU_SYS}${FUJITSU_REL}\"\n\texit ;;\n    i*86:BSD/386:*:* | i*86:BSD/OS:*:* | *:Ascend\\ Embedded/OS:*:*)\n\techo \"$UNAME_MACHINE\"-pc-bsdi\"$UNAME_RELEASE\"\n\texit ;;\n    sparc*:BSD/OS:*:*)\n\techo sparc-unknown-bsdi\"$UNAME_RELEASE\"\n\texit ;;\n    *:BSD/OS:*:*)\n\techo \"$UNAME_MACHINE\"-unknown-bsdi\"$UNAME_RELEASE\"\n\texit ;;\n    arm:FreeBSD:*:*)\n\tUNAME_PROCESSOR=$(uname -p)\n\tset_cc_for_build\n\tif echo __ARM_PCS_VFP | $CC_FOR_BUILD -E - 2>/dev/null \\\n\t    | grep -q __ARM_PCS_VFP\n\tthen\n\t    echo \"${UNAME_PROCESSOR}\"-unknown-freebsd\"$(echo ${UNAME_RELEASE}|sed -e 's/[-(].*//')\"-gnueabi\n\telse\n\t    echo \"${UNAME_PROCESSOR}\"-unknown-freebsd\"$(echo ${UNAME_RELEASE}|sed -e 's/[-(].*//')\"-gnueabihf\n\tfi\n\texit ;;\n    *:FreeBSD:*:*)\n\tUNAME_PROCESSOR=$(/usr/bin/uname -p)\n\tcase $UNAME_PROCESSOR in\n\t    amd64)\n\t\tUNAME_PROCESSOR=x86_64 ;;\n\t    i386)\n\t\tUNAME_PROCESSOR=i586 ;;\n\tesac\n\techo \"$UNAME_PROCESSOR\"-unknown-freebsd\"$(echo \"$UNAME_RELEASE\"|sed -e 's/[-(].*//')\"\n\texit ;;\n    i*:CYGWIN*:*)\n\techo \"$UNAME_MACHINE\"-pc-cygwin\n\texit ;;\n    *:MINGW64*:*)\n\techo \"$UNAME_MACHINE\"-pc-mingw64\n\texit ;;\n    *:MINGW*:*)\n\techo \"$UNAME_MACHINE\"-pc-mingw32\n\texit ;;\n    *:MSYS*:*)\n\techo \"$UNAME_MACHINE\"-pc-msys\n\texit ;;\n    i*:PW*:*)\n\techo \"$UNAME_MACHINE\"-pc-pw32\n\texit ;;\n    *:Interix*:*)\n\tcase $UNAME_MACHINE in\n\t    x86)\n\t\techo i586-pc-interix\"$UNAME_RELEASE\"\n\t\texit ;;\n\t    authenticamd | genuineintel | EM64T)\n\t\techo x86_64-unknown-interix\"$UNAME_RELEASE\"\n\t\texit ;;\n\t    IA64)\n\t\techo ia64-unknown-interix\"$UNAME_RELEASE\"\n\t\texit ;;\n\tesac ;;\n    i*:UWIN*:*)\n\techo \"$UNAME_MACHINE\"-pc-uwin\n\texit ;;\n    amd64:CYGWIN*:*:* | x86_64:CYGWIN*:*:*)\n\techo x86_64-pc-cygwin\n\texit ;;\n    prep*:SunOS:5.*:*)\n\techo powerpcle-unknown-solaris2\"$(echo \"$UNAME_RELEASE\"|sed -e 's/[^.]*//')\"\n\texit ;;\n    *:GNU:*:*)\n\t# the GNU system\n\techo \"$(echo \"$UNAME_MACHINE\"|sed -e 's,[-/].*$,,')-unknown-$LIBC$(echo \"$UNAME_RELEASE\"|sed -e 's,/.*$,,')\"\n\texit ;;\n    *:GNU/*:*:*)\n\t# other systems with GNU libc and userland\n\techo \"$UNAME_MACHINE-unknown-$(echo \"$UNAME_SYSTEM\" | sed 's,^[^/]*/,,' | tr \"[:upper:]\" \"[:lower:]\")$(echo \"$UNAME_RELEASE\"|sed -e 's/[-(].*//')-$LIBC\"\n\texit ;;\n    *:Minix:*:*)\n\techo \"$UNAME_MACHINE\"-unknown-minix\n\texit ;;\n    aarch64:Linux:*:*)\n\techo \"$UNAME_MACHINE\"-unknown-linux-\"$LIBC\"\n\texit ;;\n    aarch64_be:Linux:*:*)\n\tUNAME_MACHINE=aarch64_be\n\techo \"$UNAME_MACHINE\"-unknown-linux-\"$LIBC\"\n\texit ;;\n    alpha:Linux:*:*)\n\tcase $(sed -n '/^cpu model/s/^.*: \\(.*\\)/\\1/p' /proc/cpuinfo 2>/dev/null) in\n\t  EV5)   UNAME_MACHINE=alphaev5 ;;\n\t  EV56)  UNAME_MACHINE=alphaev56 ;;\n\t  PCA56) UNAME_MACHINE=alphapca56 ;;\n\t  PCA57) UNAME_MACHINE=alphapca56 ;;\n\t  EV6)   UNAME_MACHINE=alphaev6 ;;\n\t  EV67)  UNAME_MACHINE=alphaev67 ;;\n\t  EV68*) UNAME_MACHINE=alphaev68 ;;\n\tesac\n\tobjdump --private-headers /bin/sh | grep -q ld.so.1\n\tif test \"$?\" = 0 ; then LIBC=gnulibc1 ; fi\n\techo \"$UNAME_MACHINE\"-unknown-linux-\"$LIBC\"\n\texit ;;\n    arc:Linux:*:* | arceb:Linux:*:* | arc64:Linux:*:*)\n\techo \"$UNAME_MACHINE\"-unknown-linux-\"$LIBC\"\n\texit ;;\n    arm*:Linux:*:*)\n\tset_cc_for_build\n\tif echo __ARM_EABI__ | $CC_FOR_BUILD -E - 2>/dev/null \\\n\t    | grep -q __ARM_EABI__\n\tthen\n\t    echo \"$UNAME_MACHINE\"-unknown-linux-\"$LIBC\"\n\telse\n\t    if echo __ARM_PCS_VFP | $CC_FOR_BUILD -E - 2>/dev/null \\\n\t\t| grep -q __ARM_PCS_VFP\n\t    then\n\t\techo \"$UNAME_MACHINE\"-unknown-linux-\"$LIBC\"eabi\n\t    else\n\t\techo \"$UNAME_MACHINE\"-unknown-linux-\"$LIBC\"eabihf\n\t    fi\n\tfi\n\texit ;;\n    avr32*:Linux:*:*)\n\techo \"$UNAME_MACHINE\"-unknown-linux-\"$LIBC\"\n\texit ;;\n    cris:Linux:*:*)\n\techo \"$UNAME_MACHINE\"-axis-linux-\"$LIBC\"\n\texit ;;\n    crisv32:Linux:*:*)\n\techo \"$UNAME_MACHINE\"-axis-linux-\"$LIBC\"\n\texit ;;\n    e2k:Linux:*:*)\n\techo \"$UNAME_MACHINE\"-unknown-linux-\"$LIBC\"\n\texit ;;\n    frv:Linux:*:*)\n\techo \"$UNAME_MACHINE\"-unknown-linux-\"$LIBC\"\n\texit ;;\n    hexagon:Linux:*:*)\n\techo \"$UNAME_MACHINE\"-unknown-linux-\"$LIBC\"\n\texit ;;\n    i*86:Linux:*:*)\n\techo \"$UNAME_MACHINE\"-pc-linux-\"$LIBC\"\n\texit ;;\n    ia64:Linux:*:*)\n\techo \"$UNAME_MACHINE\"-unknown-linux-\"$LIBC\"\n\texit ;;\n    k1om:Linux:*:*)\n\techo \"$UNAME_MACHINE\"-unknown-linux-\"$LIBC\"\n\texit ;;\n    loongarch32:Linux:*:* | loongarch64:Linux:*:* | loongarchx32:Linux:*:*)\n\techo \"$UNAME_MACHINE\"-unknown-linux-\"$LIBC\"\n\texit ;;\n    m32r*:Linux:*:*)\n\techo \"$UNAME_MACHINE\"-unknown-linux-\"$LIBC\"\n\texit ;;\n    m68*:Linux:*:*)\n\techo \"$UNAME_MACHINE\"-unknown-linux-\"$LIBC\"\n\texit ;;\n    mips:Linux:*:* | mips64:Linux:*:*)\n\tset_cc_for_build\n\tIS_GLIBC=0\n\ttest x\"${LIBC}\" = xgnu && IS_GLIBC=1\n\tsed 's/^\t//' << EOF > \"$dummy.c\"\n\t#undef CPU\n\t#undef mips\n\t#undef mipsel\n\t#undef mips64\n\t#undef mips64el\n\t#if ${IS_GLIBC} && defined(_ABI64)\n\tLIBCABI=gnuabi64\n\t#else\n\t#if ${IS_GLIBC} && defined(_ABIN32)\n\tLIBCABI=gnuabin32\n\t#else\n\tLIBCABI=${LIBC}\n\t#endif\n\t#endif\n\n\t#if ${IS_GLIBC} && defined(__mips64) && defined(__mips_isa_rev) && __mips_isa_rev>=6\n\tCPU=mipsisa64r6\n\t#else\n\t#if ${IS_GLIBC} && !defined(__mips64) && defined(__mips_isa_rev) && __mips_isa_rev>=6\n\tCPU=mipsisa32r6\n\t#else\n\t#if defined(__mips64)\n\tCPU=mips64\n\t#else\n\tCPU=mips\n\t#endif\n\t#endif\n\t#endif\n\n\t#if defined(__MIPSEL__) || defined(__MIPSEL) || defined(_MIPSEL) || defined(MIPSEL)\n\tMIPS_ENDIAN=el\n\t#else\n\t#if defined(__MIPSEB__) || defined(__MIPSEB) || defined(_MIPSEB) || defined(MIPSEB)\n\tMIPS_ENDIAN=\n\t#else\n\tMIPS_ENDIAN=\n\t#endif\n\t#endif\nEOF\n\teval \"$($CC_FOR_BUILD -E \"$dummy.c\" 2>/dev/null | grep '^CPU\\|^MIPS_ENDIAN\\|^LIBCABI')\"\n\ttest \"x$CPU\" != x && { echo \"$CPU${MIPS_ENDIAN}-unknown-linux-$LIBCABI\"; exit; }\n\t;;\n    mips64el:Linux:*:*)\n\techo \"$UNAME_MACHINE\"-unknown-linux-\"$LIBC\"\n\texit ;;\n    openrisc*:Linux:*:*)\n\techo or1k-unknown-linux-\"$LIBC\"\n\texit ;;\n    or32:Linux:*:* | or1k*:Linux:*:*)\n\techo \"$UNAME_MACHINE\"-unknown-linux-\"$LIBC\"\n\texit ;;\n    padre:Linux:*:*)\n\techo sparc-unknown-linux-\"$LIBC\"\n\texit ;;\n    parisc64:Linux:*:* | hppa64:Linux:*:*)\n\techo hppa64-unknown-linux-\"$LIBC\"\n\texit ;;\n    parisc:Linux:*:* | hppa:Linux:*:*)\n\t# Look for CPU level\n\tcase $(grep '^cpu[^a-z]*:' /proc/cpuinfo 2>/dev/null | cut -d' ' -f2) in\n\t  PA7*) echo hppa1.1-unknown-linux-\"$LIBC\" ;;\n\t  PA8*) echo hppa2.0-unknown-linux-\"$LIBC\" ;;\n\t  *)    echo hppa-unknown-linux-\"$LIBC\" ;;\n\tesac\n\texit ;;\n    ppc64:Linux:*:*)\n\techo powerpc64-unknown-linux-\"$LIBC\"\n\texit ;;\n    ppc:Linux:*:*)\n\techo powerpc-unknown-linux-\"$LIBC\"\n\texit ;;\n    ppc64le:Linux:*:*)\n\techo powerpc64le-unknown-linux-\"$LIBC\"\n\texit ;;\n    ppcle:Linux:*:*)\n\techo powerpcle-unknown-linux-\"$LIBC\"\n\texit ;;\n    riscv32:Linux:*:* | riscv32be:Linux:*:* | riscv64:Linux:*:* | riscv64be:Linux:*:*)\n\techo \"$UNAME_MACHINE\"-unknown-linux-\"$LIBC\"\n\texit ;;\n    s390:Linux:*:* | s390x:Linux:*:*)\n\techo \"$UNAME_MACHINE\"-ibm-linux-\"$LIBC\"\n\texit ;;\n    sh64*:Linux:*:*)\n\techo \"$UNAME_MACHINE\"-unknown-linux-\"$LIBC\"\n\texit ;;\n    sh*:Linux:*:*)\n\techo \"$UNAME_MACHINE\"-unknown-linux-\"$LIBC\"\n\texit ;;\n    sparc:Linux:*:* | sparc64:Linux:*:*)\n\techo \"$UNAME_MACHINE\"-unknown-linux-\"$LIBC\"\n\texit ;;\n    tile*:Linux:*:*)\n\techo \"$UNAME_MACHINE\"-unknown-linux-\"$LIBC\"\n\texit ;;\n    vax:Linux:*:*)\n\techo \"$UNAME_MACHINE\"-dec-linux-\"$LIBC\"\n\texit ;;\n    x86_64:Linux:*:*)\n\tset_cc_for_build\n\tLIBCABI=$LIBC\n\tif test \"$CC_FOR_BUILD\" != no_compiler_found; then\n\t    if (echo '#ifdef __ILP32__'; echo IS_X32; echo '#endif') | \\\n\t\t(CCOPTS=\"\" $CC_FOR_BUILD -E - 2>/dev/null) | \\\n\t\tgrep IS_X32 >/dev/null\n\t    then\n\t\tLIBCABI=\"$LIBC\"x32\n\t    fi\n\tfi\n\techo \"$UNAME_MACHINE\"-pc-linux-\"$LIBCABI\"\n\texit ;;\n    xtensa*:Linux:*:*)\n\techo \"$UNAME_MACHINE\"-unknown-linux-\"$LIBC\"\n\texit ;;\n    i*86:DYNIX/ptx:4*:*)\n\t# ptx 4.0 does uname -s correctly, with DYNIX/ptx in there.\n\t# earlier versions are messed up and put the nodename in both\n\t# sysname and nodename.\n\techo i386-sequent-sysv4\n\texit ;;\n    i*86:UNIX_SV:4.2MP:2.*)\n\t# Unixware is an offshoot of SVR4, but it has its own version\n\t# number series starting with 2...\n\t# I am not positive that other SVR4 systems won't match this,\n\t# I just have to hope.  -- rms.\n\t# Use sysv4.2uw... so that sysv4* matches it.\n\techo \"$UNAME_MACHINE\"-pc-sysv4.2uw\"$UNAME_VERSION\"\n\texit ;;\n    i*86:OS/2:*:*)\n\t# If we were able to find `uname', then EMX Unix compatibility\n\t# is probably installed.\n\techo \"$UNAME_MACHINE\"-pc-os2-emx\n\texit ;;\n    i*86:XTS-300:*:STOP)\n\techo \"$UNAME_MACHINE\"-unknown-stop\n\texit ;;\n    i*86:atheos:*:*)\n\techo \"$UNAME_MACHINE\"-unknown-atheos\n\texit ;;\n    i*86:syllable:*:*)\n\techo \"$UNAME_MACHINE\"-pc-syllable\n\texit ;;\n    i*86:LynxOS:2.*:* | i*86:LynxOS:3.[01]*:* | i*86:LynxOS:4.[02]*:*)\n\techo i386-unknown-lynxos\"$UNAME_RELEASE\"\n\texit ;;\n    i*86:*DOS:*:*)\n\techo \"$UNAME_MACHINE\"-pc-msdosdjgpp\n\texit ;;\n    i*86:*:4.*:*)\n\tUNAME_REL=$(echo \"$UNAME_RELEASE\" | sed 's/\\/MP$//')\n\tif grep Novell /usr/include/link.h >/dev/null 2>/dev/null; then\n\t\techo \"$UNAME_MACHINE\"-univel-sysv\"$UNAME_REL\"\n\telse\n\t\techo \"$UNAME_MACHINE\"-pc-sysv\"$UNAME_REL\"\n\tfi\n\texit ;;\n    i*86:*:5:[678]*)\n\t# UnixWare 7.x, OpenUNIX and OpenServer 6.\n\tcase $(/bin/uname -X | grep \"^Machine\") in\n\t    *486*)\t     UNAME_MACHINE=i486 ;;\n\t    *Pentium)\t     UNAME_MACHINE=i586 ;;\n\t    *Pent*|*Celeron) UNAME_MACHINE=i686 ;;\n\tesac\n\techo \"$UNAME_MACHINE-unknown-sysv${UNAME_RELEASE}${UNAME_SYSTEM}${UNAME_VERSION}\"\n\texit ;;\n    i*86:*:3.2:*)\n\tif test -f /usr/options/cb.name; then\n\t\tUNAME_REL=$(sed -n 's/.*Version //p' </usr/options/cb.name)\n\t\techo \"$UNAME_MACHINE\"-pc-isc\"$UNAME_REL\"\n\telif /bin/uname -X 2>/dev/null >/dev/null ; then\n\t\tUNAME_REL=$( (/bin/uname -X|grep Release|sed -e 's/.*= //'))\n\t\t(/bin/uname -X|grep i80486 >/dev/null) && UNAME_MACHINE=i486\n\t\t(/bin/uname -X|grep '^Machine.*Pentium' >/dev/null) \\\n\t\t\t&& UNAME_MACHINE=i586\n\t\t(/bin/uname -X|grep '^Machine.*Pent *II' >/dev/null) \\\n\t\t\t&& UNAME_MACHINE=i686\n\t\t(/bin/uname -X|grep '^Machine.*Pentium Pro' >/dev/null) \\\n\t\t\t&& UNAME_MACHINE=i686\n\t\techo \"$UNAME_MACHINE\"-pc-sco\"$UNAME_REL\"\n\telse\n\t\techo \"$UNAME_MACHINE\"-pc-sysv32\n\tfi\n\texit ;;\n    pc:*:*:*)\n\t# Left here for compatibility:\n\t# uname -m prints for DJGPP always 'pc', but it prints nothing about\n\t# the processor, so we play safe by assuming i586.\n\t# Note: whatever this is, it MUST be the same as what config.sub\n\t# prints for the \"djgpp\" host, or else GDB configure will decide that\n\t# this is a cross-build.\n\techo i586-pc-msdosdjgpp\n\texit ;;\n    Intel:Mach:3*:*)\n\techo i386-pc-mach3\n\texit ;;\n    paragon:*:*:*)\n\techo i860-intel-osf1\n\texit ;;\n    i860:*:4.*:*) # i860-SVR4\n\tif grep Stardent /usr/include/sys/uadmin.h >/dev/null 2>&1 ; then\n\t  echo i860-stardent-sysv\"$UNAME_RELEASE\" # Stardent Vistra i860-SVR4\n\telse # Add other i860-SVR4 vendors below as they are discovered.\n\t  echo i860-unknown-sysv\"$UNAME_RELEASE\"  # Unknown i860-SVR4\n\tfi\n\texit ;;\n    mini*:CTIX:SYS*5:*)\n\t# \"miniframe\"\n\techo m68010-convergent-sysv\n\texit ;;\n    mc68k:UNIX:SYSTEM5:3.51m)\n\techo m68k-convergent-sysv\n\texit ;;\n    M680?0:D-NIX:5.3:*)\n\techo m68k-diab-dnix\n\texit ;;\n    M68*:*:R3V[5678]*:*)\n\ttest -r /sysV68 && { echo 'm68k-motorola-sysv'; exit; } ;;\n    3[345]??:*:4.0:3.0 | 3[34]??A:*:4.0:3.0 | 3[34]??,*:*:4.0:3.0 | 3[34]??/*:*:4.0:3.0 | 4400:*:4.0:3.0 | 4850:*:4.0:3.0 | SKA40:*:4.0:3.0 | SDS2:*:4.0:3.0 | SHG2:*:4.0:3.0 | S7501*:*:4.0:3.0)\n\tOS_REL=''\n\ttest -r /etc/.relid \\\n\t&& OS_REL=.$(sed -n 's/[^ ]* [^ ]* \\([0-9][0-9]\\).*/\\1/p' < /etc/.relid)\n\t/bin/uname -p 2>/dev/null | grep 86 >/dev/null \\\n\t  && { echo i486-ncr-sysv4.3\"$OS_REL\"; exit; }\n\t/bin/uname -p 2>/dev/null | /bin/grep entium >/dev/null \\\n\t  && { echo i586-ncr-sysv4.3\"$OS_REL\"; exit; } ;;\n    3[34]??:*:4.0:* | 3[34]??,*:*:4.0:*)\n\t/bin/uname -p 2>/dev/null | grep 86 >/dev/null \\\n\t  && { echo i486-ncr-sysv4; exit; } ;;\n    NCR*:*:4.2:* | MPRAS*:*:4.2:*)\n\tOS_REL='.3'\n\ttest -r /etc/.relid \\\n\t    && OS_REL=.$(sed -n 's/[^ ]* [^ ]* \\([0-9][0-9]\\).*/\\1/p' < /etc/.relid)\n\t/bin/uname -p 2>/dev/null | grep 86 >/dev/null \\\n\t    && { echo i486-ncr-sysv4.3\"$OS_REL\"; exit; }\n\t/bin/uname -p 2>/dev/null | /bin/grep entium >/dev/null \\\n\t    && { echo i586-ncr-sysv4.3\"$OS_REL\"; exit; }\n\t/bin/uname -p 2>/dev/null | /bin/grep pteron >/dev/null \\\n\t    && { echo i586-ncr-sysv4.3\"$OS_REL\"; exit; } ;;\n    m68*:LynxOS:2.*:* | m68*:LynxOS:3.0*:*)\n\techo m68k-unknown-lynxos\"$UNAME_RELEASE\"\n\texit ;;\n    mc68030:UNIX_System_V:4.*:*)\n\techo m68k-atari-sysv4\n\texit ;;\n    TSUNAMI:LynxOS:2.*:*)\n\techo sparc-unknown-lynxos\"$UNAME_RELEASE\"\n\texit ;;\n    rs6000:LynxOS:2.*:*)\n\techo rs6000-unknown-lynxos\"$UNAME_RELEASE\"\n\texit ;;\n    PowerPC:LynxOS:2.*:* | PowerPC:LynxOS:3.[01]*:* | PowerPC:LynxOS:4.[02]*:*)\n\techo powerpc-unknown-lynxos\"$UNAME_RELEASE\"\n\texit ;;\n    SM[BE]S:UNIX_SV:*:*)\n\techo mips-dde-sysv\"$UNAME_RELEASE\"\n\texit ;;\n    RM*:ReliantUNIX-*:*:*)\n\techo mips-sni-sysv4\n\texit ;;\n    RM*:SINIX-*:*:*)\n\techo mips-sni-sysv4\n\texit ;;\n    *:SINIX-*:*:*)\n\tif uname -p 2>/dev/null >/dev/null ; then\n\t\tUNAME_MACHINE=$( (uname -p) 2>/dev/null)\n\t\techo \"$UNAME_MACHINE\"-sni-sysv4\n\telse\n\t\techo ns32k-sni-sysv\n\tfi\n\texit ;;\n    PENTIUM:*:4.0*:*)\t# Unisys `ClearPath HMP IX 4000' SVR4/MP effort\n\t\t\t# says <Richard.M.Bartel@ccMail.Census.GOV>\n\techo i586-unisys-sysv4\n\texit ;;\n    *:UNIX_System_V:4*:FTX*)\n\t# From Gerald Hewes <hewes@openmarket.com>.\n\t# How about differentiating between stratus architectures? -djm\n\techo hppa1.1-stratus-sysv4\n\texit ;;\n    *:*:*:FTX*)\n\t# From seanf@swdc.stratus.com.\n\techo i860-stratus-sysv4\n\texit ;;\n    i*86:VOS:*:*)\n\t# From Paul.Green@stratus.com.\n\techo \"$UNAME_MACHINE\"-stratus-vos\n\texit ;;\n    *:VOS:*:*)\n\t# From Paul.Green@stratus.com.\n\techo hppa1.1-stratus-vos\n\texit ;;\n    mc68*:A/UX:*:*)\n\techo m68k-apple-aux\"$UNAME_RELEASE\"\n\texit ;;\n    news*:NEWS-OS:6*:*)\n\techo mips-sony-newsos6\n\texit ;;\n    R[34]000:*System_V*:*:* | R4000:UNIX_SYSV:*:* | R*000:UNIX_SV:*:*)\n\tif test -d /usr/nec; then\n\t\techo mips-nec-sysv\"$UNAME_RELEASE\"\n\telse\n\t\techo mips-unknown-sysv\"$UNAME_RELEASE\"\n\tfi\n\texit ;;\n    BeBox:BeOS:*:*)\t# BeOS running on hardware made by Be, PPC only.\n\techo powerpc-be-beos\n\texit ;;\n    BeMac:BeOS:*:*)\t# BeOS running on Mac or Mac clone, PPC only.\n\techo powerpc-apple-beos\n\texit ;;\n    BePC:BeOS:*:*)\t# BeOS running on Intel PC compatible.\n\techo i586-pc-beos\n\texit ;;\n    BePC:Haiku:*:*)\t# Haiku running on Intel PC compatible.\n\techo i586-pc-haiku\n\texit ;;\n    x86_64:Haiku:*:*)\n\techo x86_64-unknown-haiku\n\texit ;;\n    SX-4:SUPER-UX:*:*)\n\techo sx4-nec-superux\"$UNAME_RELEASE\"\n\texit ;;\n    SX-5:SUPER-UX:*:*)\n\techo sx5-nec-superux\"$UNAME_RELEASE\"\n\texit ;;\n    SX-6:SUPER-UX:*:*)\n\techo sx6-nec-superux\"$UNAME_RELEASE\"\n\texit ;;\n    SX-7:SUPER-UX:*:*)\n\techo sx7-nec-superux\"$UNAME_RELEASE\"\n\texit ;;\n    SX-8:SUPER-UX:*:*)\n\techo sx8-nec-superux\"$UNAME_RELEASE\"\n\texit ;;\n    SX-8R:SUPER-UX:*:*)\n\techo sx8r-nec-superux\"$UNAME_RELEASE\"\n\texit ;;\n    SX-ACE:SUPER-UX:*:*)\n\techo sxace-nec-superux\"$UNAME_RELEASE\"\n\texit ;;\n    Power*:Rhapsody:*:*)\n\techo powerpc-apple-rhapsody\"$UNAME_RELEASE\"\n\texit ;;\n    *:Rhapsody:*:*)\n\techo \"$UNAME_MACHINE\"-apple-rhapsody\"$UNAME_RELEASE\"\n\texit ;;\n    arm64:Darwin:*:*)\n\techo aarch64-apple-darwin\"$UNAME_RELEASE\"\n\texit ;;\n    *:Darwin:*:*)\n\tUNAME_PROCESSOR=$(uname -p)\n\tcase $UNAME_PROCESSOR in\n\t    unknown) UNAME_PROCESSOR=powerpc ;;\n\tesac\n\tif command -v xcode-select > /dev/null 2> /dev/null && \\\n\t\t! xcode-select --print-path > /dev/null 2> /dev/null ; then\n\t    # Avoid executing cc if there is no toolchain installed as\n\t    # cc will be a stub that puts up a graphical alert\n\t    # prompting the user to install developer tools.\n\t    CC_FOR_BUILD=no_compiler_found\n\telse\n\t    set_cc_for_build\n\tfi\n\tif test \"$CC_FOR_BUILD\" != no_compiler_found; then\n\t    if (echo '#ifdef __LP64__'; echo IS_64BIT_ARCH; echo '#endif') | \\\n\t\t   (CCOPTS=\"\" $CC_FOR_BUILD -E - 2>/dev/null) | \\\n\t\t   grep IS_64BIT_ARCH >/dev/null\n\t    then\n\t\tcase $UNAME_PROCESSOR in\n\t\t    i386) UNAME_PROCESSOR=x86_64 ;;\n\t\t    powerpc) UNAME_PROCESSOR=powerpc64 ;;\n\t\tesac\n\t    fi\n\t    # On 10.4-10.6 one might compile for PowerPC via gcc -arch ppc\n\t    if (echo '#ifdef __POWERPC__'; echo IS_PPC; echo '#endif') | \\\n\t\t   (CCOPTS=\"\" $CC_FOR_BUILD -E - 2>/dev/null) | \\\n\t\t   grep IS_PPC >/dev/null\n\t    then\n\t\tUNAME_PROCESSOR=powerpc\n\t    fi\n\telif test \"$UNAME_PROCESSOR\" = i386 ; then\n\t    # uname -m returns i386 or x86_64\n\t    UNAME_PROCESSOR=$UNAME_MACHINE\n\tfi\n\techo \"$UNAME_PROCESSOR\"-apple-darwin\"$UNAME_RELEASE\"\n\texit ;;\n    *:procnto*:*:* | *:QNX:[0123456789]*:*)\n\tUNAME_PROCESSOR=$(uname -p)\n\tif test \"$UNAME_PROCESSOR\" = x86; then\n\t\tUNAME_PROCESSOR=i386\n\t\tUNAME_MACHINE=pc\n\tfi\n\techo \"$UNAME_PROCESSOR\"-\"$UNAME_MACHINE\"-nto-qnx\"$UNAME_RELEASE\"\n\texit ;;\n    *:QNX:*:4*)\n\techo i386-pc-qnx\n\texit ;;\n    NEO-*:NONSTOP_KERNEL:*:*)\n\techo neo-tandem-nsk\"$UNAME_RELEASE\"\n\texit ;;\n    NSE-*:NONSTOP_KERNEL:*:*)\n\techo nse-tandem-nsk\"$UNAME_RELEASE\"\n\texit ;;\n    NSR-*:NONSTOP_KERNEL:*:*)\n\techo nsr-tandem-nsk\"$UNAME_RELEASE\"\n\texit ;;\n    NSV-*:NONSTOP_KERNEL:*:*)\n\techo nsv-tandem-nsk\"$UNAME_RELEASE\"\n\texit ;;\n    NSX-*:NONSTOP_KERNEL:*:*)\n\techo nsx-tandem-nsk\"$UNAME_RELEASE\"\n\texit ;;\n    *:NonStop-UX:*:*)\n\techo mips-compaq-nonstopux\n\texit ;;\n    BS2000:POSIX*:*:*)\n\techo bs2000-siemens-sysv\n\texit ;;\n    DS/*:UNIX_System_V:*:*)\n\techo \"$UNAME_MACHINE\"-\"$UNAME_SYSTEM\"-\"$UNAME_RELEASE\"\n\texit ;;\n    *:Plan9:*:*)\n\t# \"uname -m\" is not consistent, so use $cputype instead. 386\n\t# is converted to i386 for consistency with other x86\n\t# operating systems.\n\tif test \"${cputype-}\" = 386; then\n\t    UNAME_MACHINE=i386\n\telif test \"x${cputype-}\" != x; then\n\t    UNAME_MACHINE=\"$cputype\"\n\tfi\n\techo \"$UNAME_MACHINE\"-unknown-plan9\n\texit ;;\n    *:TOPS-10:*:*)\n\techo pdp10-unknown-tops10\n\texit ;;\n    *:TENEX:*:*)\n\techo pdp10-unknown-tenex\n\texit ;;\n    KS10:TOPS-20:*:* | KL10:TOPS-20:*:* | TYPE4:TOPS-20:*:*)\n\techo pdp10-dec-tops20\n\texit ;;\n    XKL-1:TOPS-20:*:* | TYPE5:TOPS-20:*:*)\n\techo pdp10-xkl-tops20\n\texit ;;\n    *:TOPS-20:*:*)\n\techo pdp10-unknown-tops20\n\texit ;;\n    *:ITS:*:*)\n\techo pdp10-unknown-its\n\texit ;;\n    SEI:*:*:SEIUX)\n\techo mips-sei-seiux\"$UNAME_RELEASE\"\n\texit ;;\n    *:DragonFly:*:*)\n\techo \"$UNAME_MACHINE\"-unknown-dragonfly\"$(echo \"$UNAME_RELEASE\"|sed -e 's/[-(].*//')\"\n\texit ;;\n    *:*VMS:*:*)\n\tUNAME_MACHINE=$( (uname -p) 2>/dev/null)\n\tcase $UNAME_MACHINE in\n\t    A*) echo alpha-dec-vms ; exit ;;\n\t    I*) echo ia64-dec-vms ; exit ;;\n\t    V*) echo vax-dec-vms ; exit ;;\n\tesac ;;\n    *:XENIX:*:SysV)\n\techo i386-pc-xenix\n\texit ;;\n    i*86:skyos:*:*)\n\techo \"$UNAME_MACHINE\"-pc-skyos\"$(echo \"$UNAME_RELEASE\" | sed -e 's/ .*$//')\"\n\texit ;;\n    i*86:rdos:*:*)\n\techo \"$UNAME_MACHINE\"-pc-rdos\n\texit ;;\n    *:AROS:*:*)\n\techo \"$UNAME_MACHINE\"-unknown-aros\n\texit ;;\n    x86_64:VMkernel:*:*)\n\techo \"$UNAME_MACHINE\"-unknown-esx\n\texit ;;\n    amd64:Isilon\\ OneFS:*:*)\n\techo x86_64-unknown-onefs\n\texit ;;\n    *:Unleashed:*:*)\n\techo \"$UNAME_MACHINE\"-unknown-unleashed\"$UNAME_RELEASE\"\n\texit ;;\nesac\n\n# No uname command or uname output not recognized.\nset_cc_for_build\ncat > \"$dummy.c\" <<EOF\n#ifdef _SEQUENT_\n#include <sys/types.h>\n#include <sys/utsname.h>\n#endif\n#if defined(ultrix) || defined(_ultrix) || defined(__ultrix) || defined(__ultrix__)\n#if defined (vax) || defined (__vax) || defined (__vax__) || defined(mips) || defined(__mips) || defined(__mips__) || defined(MIPS) || defined(__MIPS__)\n#include <signal.h>\n#if defined(_SIZE_T_) || defined(SIGLOST)\n#include <sys/utsname.h>\n#endif\n#endif\n#endif\nmain ()\n{\n#if defined (sony)\n#if defined (MIPSEB)\n  /* BFD wants \"bsd\" instead of \"newsos\".  Perhaps BFD should be changed,\n     I don't know....  */\n  printf (\"mips-sony-bsd\\n\"); exit (0);\n#else\n#include <sys/param.h>\n  printf (\"m68k-sony-newsos%s\\n\",\n#ifdef NEWSOS4\n  \"4\"\n#else\n  \"\"\n#endif\n  ); exit (0);\n#endif\n#endif\n\n#if defined (NeXT)\n#if !defined (__ARCHITECTURE__)\n#define __ARCHITECTURE__ \"m68k\"\n#endif\n  int version;\n  version=$( (hostinfo | sed -n 's/.*NeXT Mach \\([0-9]*\\).*/\\1/p') 2>/dev/null);\n  if (version < 4)\n    printf (\"%s-next-nextstep%d\\n\", __ARCHITECTURE__, version);\n  else\n    printf (\"%s-next-openstep%d\\n\", __ARCHITECTURE__, version);\n  exit (0);\n#endif\n\n#if defined (MULTIMAX) || defined (n16)\n#if defined (UMAXV)\n  printf (\"ns32k-encore-sysv\\n\"); exit (0);\n#else\n#if defined (CMU)\n  printf (\"ns32k-encore-mach\\n\"); exit (0);\n#else\n  printf (\"ns32k-encore-bsd\\n\"); exit (0);\n#endif\n#endif\n#endif\n\n#if defined (__386BSD__)\n  printf (\"i386-pc-bsd\\n\"); exit (0);\n#endif\n\n#if defined (sequent)\n#if defined (i386)\n  printf (\"i386-sequent-dynix\\n\"); exit (0);\n#endif\n#if defined (ns32000)\n  printf (\"ns32k-sequent-dynix\\n\"); exit (0);\n#endif\n#endif\n\n#if defined (_SEQUENT_)\n  struct utsname un;\n\n  uname(&un);\n  if (strncmp(un.version, \"V2\", 2) == 0) {\n    printf (\"i386-sequent-ptx2\\n\"); exit (0);\n  }\n  if (strncmp(un.version, \"V1\", 2) == 0) { /* XXX is V1 correct? */\n    printf (\"i386-sequent-ptx1\\n\"); exit (0);\n  }\n  printf (\"i386-sequent-ptx\\n\"); exit (0);\n#endif\n\n#if defined (vax)\n#if !defined (ultrix)\n#include <sys/param.h>\n#if defined (BSD)\n#if BSD == 43\n  printf (\"vax-dec-bsd4.3\\n\"); exit (0);\n#else\n#if BSD == 199006\n  printf (\"vax-dec-bsd4.3reno\\n\"); exit (0);\n#else\n  printf (\"vax-dec-bsd\\n\"); exit (0);\n#endif\n#endif\n#else\n  printf (\"vax-dec-bsd\\n\"); exit (0);\n#endif\n#else\n#if defined(_SIZE_T_) || defined(SIGLOST)\n  struct utsname un;\n  uname (&un);\n  printf (\"vax-dec-ultrix%s\\n\", un.release); exit (0);\n#else\n  printf (\"vax-dec-ultrix\\n\"); exit (0);\n#endif\n#endif\n#endif\n#if defined(ultrix) || defined(_ultrix) || defined(__ultrix) || defined(__ultrix__)\n#if defined(mips) || defined(__mips) || defined(__mips__) || defined(MIPS) || defined(__MIPS__)\n#if defined(_SIZE_T_) || defined(SIGLOST)\n  struct utsname *un;\n  uname (&un);\n  printf (\"mips-dec-ultrix%s\\n\", un.release); exit (0);\n#else\n  printf (\"mips-dec-ultrix\\n\"); exit (0);\n#endif\n#endif\n#endif\n\n#if defined (alliant) && defined (i860)\n  printf (\"i860-alliant-bsd\\n\"); exit (0);\n#endif\n\n  exit (1);\n}\nEOF\n\n$CC_FOR_BUILD -o \"$dummy\" \"$dummy.c\" 2>/dev/null && SYSTEM_NAME=$($dummy) &&\n\t{ echo \"$SYSTEM_NAME\"; exit; }\n\n# Apollos put the system type in the environment.\ntest -d /usr/apollo && { echo \"$ISP-apollo-$SYSTYPE\"; exit; }\n\necho \"$0: unable to guess system type\" >&2\n\ncase $UNAME_MACHINE:$UNAME_SYSTEM in\n    mips:Linux | mips64:Linux)\n\t# If we got here on MIPS GNU/Linux, output extra information.\n\tcat >&2 <<EOF\n\nNOTE: MIPS GNU/Linux systems require a C compiler to fully recognize\nthe system type. Please install a C compiler and try again.\nEOF\n\t;;\nesac\n\ncat >&2 <<EOF\n\nThis script (version $timestamp), has failed to recognize the\noperating system you are using. If your script is old, overwrite *all*\ncopies of config.guess and config.sub with the latest versions from:\n\n  https://git.savannah.gnu.org/cgit/config.git/plain/config.guess\nand\n  https://git.savannah.gnu.org/cgit/config.git/plain/config.sub\nEOF\n\nyear=$(echo $timestamp | sed 's,-.*,,')\n# shellcheck disable=SC2003\nif test \"$(expr \"$(date +%Y)\" - \"$year\")\" -lt 3 ; then\n   cat >&2 <<EOF\n\nIf $0 has already been updated, send the following data and any\ninformation you think might be pertinent to config-patches@gnu.org to\nprovide the necessary information to handle your system.\n\nconfig.guess timestamp = $timestamp\n\nuname -m = $( (uname -m) 2>/dev/null || echo unknown)\nuname -r = $( (uname -r) 2>/dev/null || echo unknown)\nuname -s = $( (uname -s) 2>/dev/null || echo unknown)\nuname -v = $( (uname -v) 2>/dev/null || echo unknown)\n\n/usr/bin/uname -p = $( (/usr/bin/uname -p) 2>/dev/null)\n/bin/uname -X     = $( (/bin/uname -X) 2>/dev/null)\n\nhostinfo               = $( (hostinfo) 2>/dev/null)\n/bin/universe          = $( (/bin/universe) 2>/dev/null)\n/usr/bin/arch -k       = $( (/usr/bin/arch -k) 2>/dev/null)\n/bin/arch              = $( (/bin/arch) 2>/dev/null)\n/usr/bin/oslevel       = $( (/usr/bin/oslevel) 2>/dev/null)\n/usr/convex/getsysinfo = $( (/usr/convex/getsysinfo) 2>/dev/null)\n\nUNAME_MACHINE = \"$UNAME_MACHINE\"\nUNAME_RELEASE = \"$UNAME_RELEASE\"\nUNAME_SYSTEM  = \"$UNAME_SYSTEM\"\nUNAME_VERSION = \"$UNAME_VERSION\"\nEOF\nfi\n\nexit 1\n\n# Local variables:\n# eval: (add-hook 'before-save-hook 'time-stamp)\n# time-stamp-start: \"timestamp='\"\n# time-stamp-format: \"%:y-%02m-%02d\"\n# time-stamp-end: \"'\"\n# End:\n"
  },
  {
    "path": "scripts/config.rpath",
    "content": "#! /bin/sh\n# Output a system dependent set of variables, describing how to set the\n# run time search path of shared libraries in an executable.\n#\n#   Copyright 1996-2007 Free Software Foundation, Inc.\n#   Taken from GNU libtool, 2001\n#   Originally by Gordon Matzigkeit <gord@gnu.ai.mit.edu>, 1996\n#\n#   This file is free software; the Free Software Foundation gives\n#   unlimited permission to copy and/or distribute it, with or without\n#   modifications, as long as this notice is preserved.\n#\n# The first argument passed to this file is the canonical host specification,\n#    CPU_TYPE-MANUFACTURER-OPERATING_SYSTEM\n# or\n#    CPU_TYPE-MANUFACTURER-KERNEL-OPERATING_SYSTEM\n# The environment variables CC, GCC, LDFLAGS, LD, with_gnu_ld\n# should be set by the caller.\n#\n# The set of defined variables is at the end of this script.\n\n# Known limitations:\n# - On IRIX 6.5 with CC=\"cc\", the run time search patch must not be longer\n#   than 256 bytes, otherwise the compiler driver will dump core. The only\n#   known workaround is to choose shorter directory names for the build\n#   directory and/or the installation directory.\n\n# All known linkers require a `.a' archive for static linking (except MSVC,\n# which needs '.lib').\nlibext=a\nshrext=.so\n\nhost=\"$1\"\nhost_cpu=`echo \"$host\" | sed 's/^\\([^-]*\\)-\\([^-]*\\)-\\(.*\\)$/\\1/'`\nhost_vendor=`echo \"$host\" | sed 's/^\\([^-]*\\)-\\([^-]*\\)-\\(.*\\)$/\\2/'`\nhost_os=`echo \"$host\" | sed 's/^\\([^-]*\\)-\\([^-]*\\)-\\(.*\\)$/\\3/'`\n\n# Code taken from libtool.m4's _LT_CC_BASENAME.\n\nfor cc_temp in $CC\"\"; do\n  case $cc_temp in\n    compile | *[\\\\/]compile | ccache | *[\\\\/]ccache ) ;;\n    distcc | *[\\\\/]distcc | purify | *[\\\\/]purify ) ;;\n    \\-*) ;;\n    *) break;;\n  esac\ndone\ncc_basename=`echo \"$cc_temp\" | sed -e 's%^.*/%%'`\n\n# Code taken from libtool.m4's AC_LIBTOOL_PROG_COMPILER_PIC.\n\nwl=\nif test \"$GCC\" = yes; then\n  wl='-Wl,'\nelse\n  case \"$host_os\" in\n    aix*)\n      wl='-Wl,'\n      ;;\n    darwin*)\n      case $cc_basename in\n        xlc*)\n          wl='-Wl,'\n          ;;\n      esac\n      ;;\n    mingw* | cygwin* | pw32* | os2*)\n      ;;\n    hpux9* | hpux10* | hpux11*)\n      wl='-Wl,'\n      ;;\n    irix5* | irix6* | nonstopux*)\n      wl='-Wl,'\n      ;;\n    newsos6)\n      ;;\n    linux* | k*bsd*-gnu)\n      case $cc_basename in\n        icc* | ecc*)\n          wl='-Wl,'\n          ;;\n        pgcc | pgf77 | pgf90)\n          wl='-Wl,'\n          ;;\n        ccc*)\n          wl='-Wl,'\n          ;;\n        como)\n          wl='-lopt='\n          ;;\n        *)\n          case `$CC -V 2>&1 | sed 5q` in\n            *Sun\\ C*)\n              wl='-Wl,'\n              ;;\n          esac\n          ;;\n      esac\n      ;;\n    osf3* | osf4* | osf5*)\n      wl='-Wl,'\n      ;;\n    rdos*)\n      ;;\n    solaris*)\n      wl='-Wl,'\n      ;;\n    sunos4*)\n      wl='-Qoption ld '\n      ;;\n    sysv4 | sysv4.2uw2* | sysv4.3*)\n      wl='-Wl,'\n      ;;\n    sysv4*MP*)\n      ;;\n    sysv5* | unixware* | sco3.2v5* | sco5v6* | OpenUNIX*)\n      wl='-Wl,'\n      ;;\n    unicos*)\n      wl='-Wl,'\n      ;;\n    uts4*)\n      ;;\n  esac\nfi\n\n# Code taken from libtool.m4's AC_LIBTOOL_PROG_LD_SHLIBS.\n\nhardcode_libdir_flag_spec=\nhardcode_libdir_separator=\nhardcode_direct=no\nhardcode_minus_L=no\n\ncase \"$host_os\" in\n  cygwin* | mingw* | pw32*)\n    # FIXME: the MSVC++ port hasn't been tested in a loooong time\n    # When not using gcc, we currently assume that we are using\n    # Microsoft Visual C++.\n    if test \"$GCC\" != yes; then\n      with_gnu_ld=no\n    fi\n    ;;\n  interix*)\n    # we just hope/assume this is gcc and not c89 (= MSVC++)\n    with_gnu_ld=yes\n    ;;\n  openbsd*)\n    with_gnu_ld=no\n    ;;\nesac\n\nld_shlibs=yes\nif test \"$with_gnu_ld\" = yes; then\n  # Set some defaults for GNU ld with shared library support. These\n  # are reset later if shared libraries are not supported. Putting them\n  # here allows them to be overridden if necessary.\n  # Unlike libtool, we use -rpath here, not --rpath, since the documented\n  # option of GNU ld is called -rpath, not --rpath.\n  hardcode_libdir_flag_spec='${wl}-rpath ${wl}$libdir'\n  case \"$host_os\" in\n    aix3* | aix4* | aix5*)\n      # On AIX/PPC, the GNU linker is very broken\n      if test \"$host_cpu\" != ia64; then\n        ld_shlibs=no\n      fi\n      ;;\n    amigaos*)\n      hardcode_libdir_flag_spec='-L$libdir'\n      hardcode_minus_L=yes\n      # Samuel A. Falvo II <kc5tja@dolphin.openprojects.net> reports\n      # that the semantics of dynamic libraries on AmigaOS, at least up\n      # to version 4, is to share data among multiple programs linked\n      # with the same dynamic library.  Since this doesn't match the\n      # behavior of shared libraries on other platforms, we cannot use\n      # them.\n      ld_shlibs=no\n      ;;\n    beos*)\n      if $LD --help 2>&1 | grep ': supported targets:.* elf' > /dev/null; then\n        :\n      else\n        ld_shlibs=no\n      fi\n      ;;\n    cygwin* | mingw* | pw32*)\n      # hardcode_libdir_flag_spec is actually meaningless, as there is\n      # no search path for DLLs.\n      hardcode_libdir_flag_spec='-L$libdir'\n      if $LD --help 2>&1 | grep 'auto-import' > /dev/null; then\n        :\n      else\n        ld_shlibs=no\n      fi\n      ;;\n    interix[3-9]*)\n      hardcode_direct=no\n      hardcode_libdir_flag_spec='${wl}-rpath,$libdir'\n      ;;\n    gnu* | linux* | k*bsd*-gnu)\n      if $LD --help 2>&1 | grep ': supported targets:.* elf' > /dev/null; then\n        :\n      else\n        ld_shlibs=no\n      fi\n      ;;\n    netbsd*)\n      ;;\n    solaris*)\n      if $LD -v 2>&1 | grep 'BFD 2\\.8' > /dev/null; then\n        ld_shlibs=no\n      elif $LD --help 2>&1 | grep ': supported targets:.* elf' > /dev/null; then\n        :\n      else\n        ld_shlibs=no\n      fi\n      ;;\n    sysv5* | sco3.2v5* | sco5v6* | unixware* | OpenUNIX*)\n      case `$LD -v 2>&1` in\n        *\\ [01].* | *\\ 2.[0-9].* | *\\ 2.1[0-5].*)\n          ld_shlibs=no\n          ;;\n        *)\n          if $LD --help 2>&1 | grep ': supported targets:.* elf' > /dev/null; then\n            hardcode_libdir_flag_spec='`test -z \"$SCOABSPATH\" && echo ${wl}-rpath,$libdir`'\n          else\n            ld_shlibs=no\n          fi\n          ;;\n      esac\n      ;;\n    sunos4*)\n      hardcode_direct=yes\n      ;;\n    *)\n      if $LD --help 2>&1 | grep ': supported targets:.* elf' > /dev/null; then\n        :\n      else\n        ld_shlibs=no\n      fi\n      ;;\n  esac\n  if test \"$ld_shlibs\" = no; then\n    hardcode_libdir_flag_spec=\n  fi\nelse\n  case \"$host_os\" in\n    aix3*)\n      # Note: this linker hardcodes the directories in LIBPATH if there\n      # are no directories specified by -L.\n      hardcode_minus_L=yes\n      if test \"$GCC\" = yes; then\n        # Neither direct hardcoding nor static linking is supported with a\n        # broken collect2.\n        hardcode_direct=unsupported\n      fi\n      ;;\n    aix4* | aix5*)\n      if test \"$host_cpu\" = ia64; then\n        # On IA64, the linker does run time linking by default, so we don't\n        # have to do anything special.\n        aix_use_runtimelinking=no\n      else\n        aix_use_runtimelinking=no\n        # Test if we are trying to use run time linking or normal\n        # AIX style linking. If -brtl is somewhere in LDFLAGS, we\n        # need to do runtime linking.\n        case $host_os in aix4.[23]|aix4.[23].*|aix5*)\n          for ld_flag in $LDFLAGS; do\n            if (test $ld_flag = \"-brtl\" || test $ld_flag = \"-Wl,-brtl\"); then\n              aix_use_runtimelinking=yes\n              break\n            fi\n          done\n          ;;\n        esac\n      fi\n      hardcode_direct=yes\n      hardcode_libdir_separator=':'\n      if test \"$GCC\" = yes; then\n        case $host_os in aix4.[012]|aix4.[012].*)\n          collect2name=`${CC} -print-prog-name=collect2`\n          if test -f \"$collect2name\" && \\\n            strings \"$collect2name\" | grep resolve_lib_name >/dev/null\n          then\n            # We have reworked collect2\n            :\n          else\n            # We have old collect2\n            hardcode_direct=unsupported\n            hardcode_minus_L=yes\n            hardcode_libdir_flag_spec='-L$libdir'\n            hardcode_libdir_separator=\n          fi\n          ;;\n        esac\n      fi\n      # Begin _LT_AC_SYS_LIBPATH_AIX.\n      echo 'int main () { return 0; }' > conftest.c\n      ${CC} ${LDFLAGS} conftest.c -o conftest\n      aix_libpath=`dump -H conftest 2>/dev/null | sed -n -e '/Import File Strings/,/^$/ { /^0/ { s/^0  *\\(.*\\)$/\\1/; p; }\n}'`\n      if test -z \"$aix_libpath\"; then\n        aix_libpath=`dump -HX64 conftest 2>/dev/null | sed -n -e '/Import File Strings/,/^$/ { /^0/ { s/^0  *\\(.*\\)$/\\1/; p; }\n}'`\n      fi\n      if test -z \"$aix_libpath\"; then\n        aix_libpath=\"/usr/lib:/lib\"\n      fi\n      rm -f conftest.c conftest\n      # End _LT_AC_SYS_LIBPATH_AIX.\n      if test \"$aix_use_runtimelinking\" = yes; then\n        hardcode_libdir_flag_spec='${wl}-blibpath:$libdir:'\"$aix_libpath\"\n      else\n        if test \"$host_cpu\" = ia64; then\n          hardcode_libdir_flag_spec='${wl}-R $libdir:/usr/lib:/lib'\n        else\n          hardcode_libdir_flag_spec='${wl}-blibpath:$libdir:'\"$aix_libpath\"\n        fi\n      fi\n      ;;\n    amigaos*)\n      hardcode_libdir_flag_spec='-L$libdir'\n      hardcode_minus_L=yes\n      # see comment about different semantics on the GNU ld section\n      ld_shlibs=no\n      ;;\n    bsdi[45]*)\n      ;;\n    cygwin* | mingw* | pw32*)\n      # When not using gcc, we currently assume that we are using\n      # Microsoft Visual C++.\n      # hardcode_libdir_flag_spec is actually meaningless, as there is\n      # no search path for DLLs.\n      hardcode_libdir_flag_spec=' '\n      libext=lib\n      ;;\n    darwin* | rhapsody*)\n      hardcode_direct=no\n      if test \"$GCC\" = yes ; then\n        :\n      else\n        case $cc_basename in\n          xlc*)\n            ;;\n          *)\n            ld_shlibs=no\n            ;;\n        esac\n      fi\n      ;;\n    dgux*)\n      hardcode_libdir_flag_spec='-L$libdir'\n      ;;\n    freebsd1*)\n      ld_shlibs=no\n      ;;\n    freebsd2.2*)\n      hardcode_libdir_flag_spec='-R$libdir'\n      hardcode_direct=yes\n      ;;\n    freebsd2*)\n      hardcode_direct=yes\n      hardcode_minus_L=yes\n      ;;\n    freebsd* | dragonfly*)\n      hardcode_libdir_flag_spec='-R$libdir'\n      hardcode_direct=yes\n      ;;\n    hpux9*)\n      hardcode_libdir_flag_spec='${wl}+b ${wl}$libdir'\n      hardcode_libdir_separator=:\n      hardcode_direct=yes\n      # hardcode_minus_L: Not really in the search PATH,\n      # but as the default location of the library.\n      hardcode_minus_L=yes\n      ;;\n    hpux10*)\n      if test \"$with_gnu_ld\" = no; then\n        hardcode_libdir_flag_spec='${wl}+b ${wl}$libdir'\n        hardcode_libdir_separator=:\n        hardcode_direct=yes\n        # hardcode_minus_L: Not really in the search PATH,\n        # but as the default location of the library.\n        hardcode_minus_L=yes\n      fi\n      ;;\n    hpux11*)\n      if test \"$with_gnu_ld\" = no; then\n        hardcode_libdir_flag_spec='${wl}+b ${wl}$libdir'\n        hardcode_libdir_separator=:\n        case $host_cpu in\n          hppa*64*|ia64*)\n            hardcode_direct=no\n            ;;\n          *)\n            hardcode_direct=yes\n            # hardcode_minus_L: Not really in the search PATH,\n            # but as the default location of the library.\n            hardcode_minus_L=yes\n            ;;\n        esac\n      fi\n      ;;\n    irix5* | irix6* | nonstopux*)\n      hardcode_libdir_flag_spec='${wl}-rpath ${wl}$libdir'\n      hardcode_libdir_separator=:\n      ;;\n    netbsd*)\n      hardcode_libdir_flag_spec='-R$libdir'\n      hardcode_direct=yes\n      ;;\n    newsos6)\n      hardcode_direct=yes\n      hardcode_libdir_flag_spec='${wl}-rpath ${wl}$libdir'\n      hardcode_libdir_separator=:\n      ;;\n    openbsd*)\n      if test -f /usr/libexec/ld.so; then\n        hardcode_direct=yes\n        if test -z \"`echo __ELF__ | $CC -E - | grep __ELF__`\" || test \"$host_os-$host_cpu\" = \"openbsd2.8-powerpc\"; then\n          hardcode_libdir_flag_spec='${wl}-rpath,$libdir'\n        else\n          case \"$host_os\" in\n            openbsd[01].* | openbsd2.[0-7] | openbsd2.[0-7].*)\n              hardcode_libdir_flag_spec='-R$libdir'\n              ;;\n            *)\n              hardcode_libdir_flag_spec='${wl}-rpath,$libdir'\n              ;;\n          esac\n        fi\n      else\n        ld_shlibs=no\n      fi\n      ;;\n    os2*)\n      hardcode_libdir_flag_spec='-L$libdir'\n      hardcode_minus_L=yes\n      ;;\n    osf3*)\n      hardcode_libdir_flag_spec='${wl}-rpath ${wl}$libdir'\n      hardcode_libdir_separator=:\n      ;;\n    osf4* | osf5*)\n      if test \"$GCC\" = yes; then\n        hardcode_libdir_flag_spec='${wl}-rpath ${wl}$libdir'\n      else\n        # Both cc and cxx compiler support -rpath directly\n        hardcode_libdir_flag_spec='-rpath $libdir'\n      fi\n      hardcode_libdir_separator=:\n      ;;\n    solaris*)\n      hardcode_libdir_flag_spec='-R$libdir'\n      ;;\n    sunos4*)\n      hardcode_libdir_flag_spec='-L$libdir'\n      hardcode_direct=yes\n      hardcode_minus_L=yes\n      ;;\n    sysv4)\n      case $host_vendor in\n        sni)\n          hardcode_direct=yes # is this really true???\n          ;;\n        siemens)\n          hardcode_direct=no\n          ;;\n        motorola)\n          hardcode_direct=no #Motorola manual says yes, but my tests say they lie\n          ;;\n      esac\n      ;;\n    sysv4.3*)\n      ;;\n    sysv4*MP*)\n      if test -d /usr/nec; then\n        ld_shlibs=yes\n      fi\n      ;;\n    sysv4*uw2* | sysv5OpenUNIX* | sysv5UnixWare7.[01].[10]* | unixware7* | sco3.2v5.0.[024]*)\n      ;;\n    sysv5* | sco3.2v5* | sco5v6*)\n      hardcode_libdir_flag_spec='`test -z \"$SCOABSPATH\" && echo ${wl}-R,$libdir`'\n      hardcode_libdir_separator=':'\n      ;;\n    uts4*)\n      hardcode_libdir_flag_spec='-L$libdir'\n      ;;\n    *)\n      ld_shlibs=no\n      ;;\n  esac\nfi\n\n# Check dynamic linker characteristics\n# Code taken from libtool.m4's AC_LIBTOOL_SYS_DYNAMIC_LINKER.\n# Unlike libtool.m4, here we don't care about _all_ names of the library, but\n# only about the one the linker finds when passed -lNAME. This is the last\n# element of library_names_spec in libtool.m4, or possibly two of them if the\n# linker has special search rules.\nlibrary_names_spec=      # the last element of library_names_spec in libtool.m4\nlibname_spec='lib$name'\ncase \"$host_os\" in\n  aix3*)\n    library_names_spec='$libname.a'\n    ;;\n  aix4* | aix5*)\n    library_names_spec='$libname$shrext'\n    ;;\n  amigaos*)\n    library_names_spec='$libname.a'\n    ;;\n  beos*)\n    library_names_spec='$libname$shrext'\n    ;;\n  bsdi[45]*)\n    library_names_spec='$libname$shrext'\n    ;;\n  cygwin* | mingw* | pw32*)\n    shrext=.dll\n    library_names_spec='$libname.dll.a $libname.lib'\n    ;;\n  darwin* | rhapsody*)\n    shrext=.dylib\n    library_names_spec='$libname$shrext'\n    ;;\n  dgux*)\n    library_names_spec='$libname$shrext'\n    ;;\n  freebsd1*)\n    ;;\n  freebsd* | dragonfly*)\n    case \"$host_os\" in\n      freebsd[123]*)\n        library_names_spec='$libname$shrext$versuffix' ;;\n      *)\n        library_names_spec='$libname$shrext' ;;\n    esac\n    ;;\n  gnu*)\n    library_names_spec='$libname$shrext'\n    ;;\n  hpux9* | hpux10* | hpux11*)\n    case $host_cpu in\n      ia64*)\n        shrext=.so\n        ;;\n      hppa*64*)\n        shrext=.sl\n        ;;\n      *)\n        shrext=.sl\n        ;;\n    esac\n    library_names_spec='$libname$shrext'\n    ;;\n  interix[3-9]*)\n    library_names_spec='$libname$shrext'\n    ;;\n  irix5* | irix6* | nonstopux*)\n    library_names_spec='$libname$shrext'\n    case \"$host_os\" in\n      irix5* | nonstopux*)\n        libsuff= shlibsuff=\n        ;;\n      *)\n        case $LD in\n          *-32|*\"-32 \"|*-melf32bsmip|*\"-melf32bsmip \") libsuff= shlibsuff= ;;\n          *-n32|*\"-n32 \"|*-melf32bmipn32|*\"-melf32bmipn32 \") libsuff=32 shlibsuff=N32 ;;\n          *-64|*\"-64 \"|*-melf64bmip|*\"-melf64bmip \") libsuff=64 shlibsuff=64 ;;\n          *) libsuff= shlibsuff= ;;\n        esac\n        ;;\n    esac\n    ;;\n  linux*oldld* | linux*aout* | linux*coff*)\n    ;;\n  linux* | k*bsd*-gnu)\n    library_names_spec='$libname$shrext'\n    ;;\n  knetbsd*-gnu)\n    library_names_spec='$libname$shrext'\n    ;;\n  netbsd*)\n    library_names_spec='$libname$shrext'\n    ;;\n  newsos6)\n    library_names_spec='$libname$shrext'\n    ;;\n  nto-qnx*)\n    library_names_spec='$libname$shrext'\n    ;;\n  openbsd*)\n    library_names_spec='$libname$shrext$versuffix'\n    ;;\n  os2*)\n    libname_spec='$name'\n    shrext=.dll\n    library_names_spec='$libname.a'\n    ;;\n  osf3* | osf4* | osf5*)\n    library_names_spec='$libname$shrext'\n    ;;\n  rdos*)\n    ;;\n  solaris*)\n    library_names_spec='$libname$shrext'\n    ;;\n  sunos4*)\n    library_names_spec='$libname$shrext$versuffix'\n    ;;\n  sysv4 | sysv4.3*)\n    library_names_spec='$libname$shrext'\n    ;;\n  sysv4*MP*)\n    library_names_spec='$libname$shrext'\n    ;;\n  sysv5* | sco3.2v5* | sco5v6* | unixware* | OpenUNIX* | sysv4*uw2*)\n    library_names_spec='$libname$shrext'\n    ;;\n  uts4*)\n    library_names_spec='$libname$shrext'\n    ;;\nesac\n\nsed_quote_subst='s/\\([\"`$\\\\]\\)/\\\\\\1/g'\nescaped_wl=`echo \"X$wl\" | sed -e 's/^X//' -e \"$sed_quote_subst\"`\nshlibext=`echo \"$shrext\" | sed -e 's,^\\.,,'`\nescaped_libname_spec=`echo \"X$libname_spec\" | sed -e 's/^X//' -e \"$sed_quote_subst\"`\nescaped_library_names_spec=`echo \"X$library_names_spec\" | sed -e 's/^X//' -e \"$sed_quote_subst\"`\nescaped_hardcode_libdir_flag_spec=`echo \"X$hardcode_libdir_flag_spec\" | sed -e 's/^X//' -e \"$sed_quote_subst\"`\n\nLC_ALL=C sed -e 's/^\\([a-zA-Z0-9_]*\\)=/acl_cv_\\1=/' <<EOF\n\n# How to pass a linker flag through the compiler.\nwl=\"$escaped_wl\"\n\n# Static library suffix (normally \"a\").\nlibext=\"$libext\"\n\n# Shared library suffix (normally \"so\").\nshlibext=\"$shlibext\"\n\n# Format of library name prefix.\nlibname_spec=\"$escaped_libname_spec\"\n\n# Library names that the linker finds when passed -lNAME.\nlibrary_names_spec=\"$escaped_library_names_spec\"\n\n# Flag to hardcode \\$libdir into a binary during linking.\n# This must work even if \\$libdir does not exist.\nhardcode_libdir_flag_spec=\"$escaped_hardcode_libdir_flag_spec\"\n\n# Whether we need a single -rpath flag with a separated argument.\nhardcode_libdir_separator=\"$hardcode_libdir_separator\"\n\n# Set to yes if using DIR/libNAME.so during linking hardcodes DIR into the\n# resulting binary.\nhardcode_direct=\"$hardcode_direct\"\n\n# Set to yes if using the -LDIR flag during linking hardcodes DIR into the\n# resulting binary.\nhardcode_minus_L=\"$hardcode_minus_L\"\n\nEOF\n"
  },
  {
    "path": "scripts/config.sub",
    "content": "#! /bin/sh\n# Configuration validation subroutine script.\n#   Copyright 1992-2021 Free Software Foundation, Inc.\n\ntimestamp='2021-04-30'\n\n# This file is free software; you can redistribute it and/or modify it\n# under the terms of the GNU General Public License as published by\n# the Free Software Foundation; either version 3 of the License, or\n# (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful, but\n# WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\n# General Public License for more details.\n#\n# You should have received a copy of the GNU General Public License\n# along with this program; if not, see <https://www.gnu.org/licenses/>.\n#\n# As a special exception to the GNU General Public License, if you\n# distribute this file as part of a program that contains a\n# configuration script generated by Autoconf, you may include it under\n# the same distribution terms that you use for the rest of that\n# program.  This Exception is an additional permission under section 7\n# of the GNU General Public License, version 3 (\"GPLv3\").\n\n\n# Please send patches to <config-patches@gnu.org>.\n#\n# Configuration subroutine to validate and canonicalize a configuration type.\n# Supply the specified configuration type as an argument.\n# If it is invalid, we print an error message on stderr and exit with code 1.\n# Otherwise, we print the canonical config type on stdout and succeed.\n\n# You can get the latest version of this script from:\n# https://git.savannah.gnu.org/cgit/config.git/plain/config.sub\n\n# This file is supposed to be the same for all GNU packages\n# and recognize all the CPU types, system types and aliases\n# that are meaningful with *any* GNU software.\n# Each package is responsible for reporting which valid configurations\n# it does not support.  The user should be able to distinguish\n# a failure to support a valid configuration from a meaningless\n# configuration.\n\n# The goal of this file is to map all the various variations of a given\n# machine specification into a single specification in the form:\n#\tCPU_TYPE-MANUFACTURER-OPERATING_SYSTEM\n# or in some cases, the newer four-part form:\n#\tCPU_TYPE-MANUFACTURER-KERNEL-OPERATING_SYSTEM\n# It is wrong to echo any other type of specification.\n\nme=$(echo \"$0\" | sed -e 's,.*/,,')\n\nusage=\"\\\nUsage: $0 [OPTION] CPU-MFR-OPSYS or ALIAS\n\nCanonicalize a configuration name.\n\nOptions:\n  -h, --help         print this help, then exit\n  -t, --time-stamp   print date of last modification, then exit\n  -v, --version      print version number, then exit\n\nReport bugs and patches to <config-patches@gnu.org>.\"\n\nversion=\"\\\nGNU config.sub ($timestamp)\n\nCopyright 1992-2021 Free Software Foundation, Inc.\n\nThis is free software; see the source for copying conditions.  There is NO\nwarranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.\"\n\nhelp=\"\nTry \\`$me --help' for more information.\"\n\n# Parse command line\nwhile test $# -gt 0 ; do\n  case $1 in\n    --time-stamp | --time* | -t )\n       echo \"$timestamp\" ; exit ;;\n    --version | -v )\n       echo \"$version\" ; exit ;;\n    --help | --h* | -h )\n       echo \"$usage\"; exit ;;\n    -- )     # Stop option processing\n       shift; break ;;\n    - )\t# Use stdin as input.\n       break ;;\n    -* )\n       echo \"$me: invalid option $1$help\" >&2\n       exit 1 ;;\n\n    *local*)\n       # First pass through any local machine types.\n       echo \"$1\"\n       exit ;;\n\n    * )\n       break ;;\n  esac\ndone\n\ncase $# in\n 0) echo \"$me: missing argument$help\" >&2\n    exit 1;;\n 1) ;;\n *) echo \"$me: too many arguments$help\" >&2\n    exit 1;;\nesac\n\n# Split fields of configuration type\n# shellcheck disable=SC2162\nIFS=\"-\" read field1 field2 field3 field4 <<EOF\n$1\nEOF\n\n# Separate into logical components for further validation\ncase $1 in\n\t*-*-*-*-*)\n\t\techo Invalid configuration \\`\"$1\"\\': more than four components >&2\n\t\texit 1\n\t\t;;\n\t*-*-*-*)\n\t\tbasic_machine=$field1-$field2\n\t\tbasic_os=$field3-$field4\n\t\t;;\n\t*-*-*)\n\t\t# Ambiguous whether COMPANY is present, or skipped and KERNEL-OS is two\n\t\t# parts\n\t\tmaybe_os=$field2-$field3\n\t\tcase $maybe_os in\n\t\t\tnto-qnx* | linux-* | uclinux-uclibc* \\\n\t\t\t| uclinux-gnu* | kfreebsd*-gnu* | knetbsd*-gnu* | netbsd*-gnu* \\\n\t\t\t| netbsd*-eabi* | kopensolaris*-gnu* | cloudabi*-eabi* \\\n\t\t\t| storm-chaos* | os2-emx* | rtmk-nova*)\n\t\t\t\tbasic_machine=$field1\n\t\t\t\tbasic_os=$maybe_os\n\t\t\t\t;;\n\t\t\tandroid-linux)\n\t\t\t\tbasic_machine=$field1-unknown\n\t\t\t\tbasic_os=linux-android\n\t\t\t\t;;\n\t\t\t*)\n\t\t\t\tbasic_machine=$field1-$field2\n\t\t\t\tbasic_os=$field3\n\t\t\t\t;;\n\t\tesac\n\t\t;;\n\t*-*)\n\t\t# A lone config we happen to match not fitting any pattern\n\t\tcase $field1-$field2 in\n\t\t\tdecstation-3100)\n\t\t\t\tbasic_machine=mips-dec\n\t\t\t\tbasic_os=\n\t\t\t\t;;\n\t\t\t*-*)\n\t\t\t\t# Second component is usually, but not always the OS\n\t\t\t\tcase $field2 in\n\t\t\t\t\t# Prevent following clause from handling this valid os\n\t\t\t\t\tsun*os*)\n\t\t\t\t\t\tbasic_machine=$field1\n\t\t\t\t\t\tbasic_os=$field2\n\t\t\t\t\t\t;;\n\t\t\t\t\t# Manufacturers\n\t\t\t\t\tdec* | mips* | sequent* | encore* | pc533* | sgi* | sony* \\\n\t\t\t\t\t| att* | 7300* | 3300* | delta* | motorola* | sun[234]* \\\n\t\t\t\t\t| unicom* | ibm* | next | hp | isi* | apollo | altos* \\\n\t\t\t\t\t| convergent* | ncr* | news | 32* | 3600* | 3100* \\\n\t\t\t\t\t| hitachi* | c[123]* | convex* | sun | crds | omron* | dg \\\n\t\t\t\t\t| ultra | tti* | harris | dolphin | highlevel | gould \\\n\t\t\t\t\t| cbm | ns | masscomp | apple | axis | knuth | cray \\\n\t\t\t\t\t| microblaze* | sim | cisco \\\n\t\t\t\t\t| oki | wec | wrs | winbond)\n\t\t\t\t\t\tbasic_machine=$field1-$field2\n\t\t\t\t\t\tbasic_os=\n\t\t\t\t\t\t;;\n\t\t\t\t\t*)\n\t\t\t\t\t\tbasic_machine=$field1\n\t\t\t\t\t\tbasic_os=$field2\n\t\t\t\t\t\t;;\n\t\t\t\tesac\n\t\t\t;;\n\t\tesac\n\t\t;;\n\t*)\n\t\t# Convert single-component short-hands not valid as part of\n\t\t# multi-component configurations.\n\t\tcase $field1 in\n\t\t\t386bsd)\n\t\t\t\tbasic_machine=i386-pc\n\t\t\t\tbasic_os=bsd\n\t\t\t\t;;\n\t\t\ta29khif)\n\t\t\t\tbasic_machine=a29k-amd\n\t\t\t\tbasic_os=udi\n\t\t\t\t;;\n\t\t\tadobe68k)\n\t\t\t\tbasic_machine=m68010-adobe\n\t\t\t\tbasic_os=scout\n\t\t\t\t;;\n\t\t\talliant)\n\t\t\t\tbasic_machine=fx80-alliant\n\t\t\t\tbasic_os=\n\t\t\t\t;;\n\t\t\taltos | altos3068)\n\t\t\t\tbasic_machine=m68k-altos\n\t\t\t\tbasic_os=\n\t\t\t\t;;\n\t\t\tam29k)\n\t\t\t\tbasic_machine=a29k-none\n\t\t\t\tbasic_os=bsd\n\t\t\t\t;;\n\t\t\tamdahl)\n\t\t\t\tbasic_machine=580-amdahl\n\t\t\t\tbasic_os=sysv\n\t\t\t\t;;\n\t\t\tamiga)\n\t\t\t\tbasic_machine=m68k-unknown\n\t\t\t\tbasic_os=\n\t\t\t\t;;\n\t\t\tamigaos | amigados)\n\t\t\t\tbasic_machine=m68k-unknown\n\t\t\t\tbasic_os=amigaos\n\t\t\t\t;;\n\t\t\tamigaunix | amix)\n\t\t\t\tbasic_machine=m68k-unknown\n\t\t\t\tbasic_os=sysv4\n\t\t\t\t;;\n\t\t\tapollo68)\n\t\t\t\tbasic_machine=m68k-apollo\n\t\t\t\tbasic_os=sysv\n\t\t\t\t;;\n\t\t\tapollo68bsd)\n\t\t\t\tbasic_machine=m68k-apollo\n\t\t\t\tbasic_os=bsd\n\t\t\t\t;;\n\t\t\taros)\n\t\t\t\tbasic_machine=i386-pc\n\t\t\t\tbasic_os=aros\n\t\t\t\t;;\n\t\t\taux)\n\t\t\t\tbasic_machine=m68k-apple\n\t\t\t\tbasic_os=aux\n\t\t\t\t;;\n\t\t\tbalance)\n\t\t\t\tbasic_machine=ns32k-sequent\n\t\t\t\tbasic_os=dynix\n\t\t\t\t;;\n\t\t\tblackfin)\n\t\t\t\tbasic_machine=bfin-unknown\n\t\t\t\tbasic_os=linux\n\t\t\t\t;;\n\t\t\tcegcc)\n\t\t\t\tbasic_machine=arm-unknown\n\t\t\t\tbasic_os=cegcc\n\t\t\t\t;;\n\t\t\tconvex-c1)\n\t\t\t\tbasic_machine=c1-convex\n\t\t\t\tbasic_os=bsd\n\t\t\t\t;;\n\t\t\tconvex-c2)\n\t\t\t\tbasic_machine=c2-convex\n\t\t\t\tbasic_os=bsd\n\t\t\t\t;;\n\t\t\tconvex-c32)\n\t\t\t\tbasic_machine=c32-convex\n\t\t\t\tbasic_os=bsd\n\t\t\t\t;;\n\t\t\tconvex-c34)\n\t\t\t\tbasic_machine=c34-convex\n\t\t\t\tbasic_os=bsd\n\t\t\t\t;;\n\t\t\tconvex-c38)\n\t\t\t\tbasic_machine=c38-convex\n\t\t\t\tbasic_os=bsd\n\t\t\t\t;;\n\t\t\tcray)\n\t\t\t\tbasic_machine=j90-cray\n\t\t\t\tbasic_os=unicos\n\t\t\t\t;;\n\t\t\tcrds | unos)\n\t\t\t\tbasic_machine=m68k-crds\n\t\t\t\tbasic_os=\n\t\t\t\t;;\n\t\t\tda30)\n\t\t\t\tbasic_machine=m68k-da30\n\t\t\t\tbasic_os=\n\t\t\t\t;;\n\t\t\tdecstation | pmax | pmin | dec3100 | decstatn)\n\t\t\t\tbasic_machine=mips-dec\n\t\t\t\tbasic_os=\n\t\t\t\t;;\n\t\t\tdelta88)\n\t\t\t\tbasic_machine=m88k-motorola\n\t\t\t\tbasic_os=sysv3\n\t\t\t\t;;\n\t\t\tdicos)\n\t\t\t\tbasic_machine=i686-pc\n\t\t\t\tbasic_os=dicos\n\t\t\t\t;;\n\t\t\tdjgpp)\n\t\t\t\tbasic_machine=i586-pc\n\t\t\t\tbasic_os=msdosdjgpp\n\t\t\t\t;;\n\t\t\tebmon29k)\n\t\t\t\tbasic_machine=a29k-amd\n\t\t\t\tbasic_os=ebmon\n\t\t\t\t;;\n\t\t\tes1800 | OSE68k | ose68k | ose | OSE)\n\t\t\t\tbasic_machine=m68k-ericsson\n\t\t\t\tbasic_os=ose\n\t\t\t\t;;\n\t\t\tgmicro)\n\t\t\t\tbasic_machine=tron-gmicro\n\t\t\t\tbasic_os=sysv\n\t\t\t\t;;\n\t\t\tgo32)\n\t\t\t\tbasic_machine=i386-pc\n\t\t\t\tbasic_os=go32\n\t\t\t\t;;\n\t\t\th8300hms)\n\t\t\t\tbasic_machine=h8300-hitachi\n\t\t\t\tbasic_os=hms\n\t\t\t\t;;\n\t\t\th8300xray)\n\t\t\t\tbasic_machine=h8300-hitachi\n\t\t\t\tbasic_os=xray\n\t\t\t\t;;\n\t\t\th8500hms)\n\t\t\t\tbasic_machine=h8500-hitachi\n\t\t\t\tbasic_os=hms\n\t\t\t\t;;\n\t\t\tharris)\n\t\t\t\tbasic_machine=m88k-harris\n\t\t\t\tbasic_os=sysv3\n\t\t\t\t;;\n\t\t\thp300 | hp300hpux)\n\t\t\t\tbasic_machine=m68k-hp\n\t\t\t\tbasic_os=hpux\n\t\t\t\t;;\n\t\t\thp300bsd)\n\t\t\t\tbasic_machine=m68k-hp\n\t\t\t\tbasic_os=bsd\n\t\t\t\t;;\n\t\t\thppaosf)\n\t\t\t\tbasic_machine=hppa1.1-hp\n\t\t\t\tbasic_os=osf\n\t\t\t\t;;\n\t\t\thppro)\n\t\t\t\tbasic_machine=hppa1.1-hp\n\t\t\t\tbasic_os=proelf\n\t\t\t\t;;\n\t\t\ti386mach)\n\t\t\t\tbasic_machine=i386-mach\n\t\t\t\tbasic_os=mach\n\t\t\t\t;;\n\t\t\tisi68 | isi)\n\t\t\t\tbasic_machine=m68k-isi\n\t\t\t\tbasic_os=sysv\n\t\t\t\t;;\n\t\t\tm68knommu)\n\t\t\t\tbasic_machine=m68k-unknown\n\t\t\t\tbasic_os=linux\n\t\t\t\t;;\n\t\t\tmagnum | m3230)\n\t\t\t\tbasic_machine=mips-mips\n\t\t\t\tbasic_os=sysv\n\t\t\t\t;;\n\t\t\tmerlin)\n\t\t\t\tbasic_machine=ns32k-utek\n\t\t\t\tbasic_os=sysv\n\t\t\t\t;;\n\t\t\tmingw64)\n\t\t\t\tbasic_machine=x86_64-pc\n\t\t\t\tbasic_os=mingw64\n\t\t\t\t;;\n\t\t\tmingw32)\n\t\t\t\tbasic_machine=i686-pc\n\t\t\t\tbasic_os=mingw32\n\t\t\t\t;;\n\t\t\tmingw32ce)\n\t\t\t\tbasic_machine=arm-unknown\n\t\t\t\tbasic_os=mingw32ce\n\t\t\t\t;;\n\t\t\tmonitor)\n\t\t\t\tbasic_machine=m68k-rom68k\n\t\t\t\tbasic_os=coff\n\t\t\t\t;;\n\t\t\tmorphos)\n\t\t\t\tbasic_machine=powerpc-unknown\n\t\t\t\tbasic_os=morphos\n\t\t\t\t;;\n\t\t\tmoxiebox)\n\t\t\t\tbasic_machine=moxie-unknown\n\t\t\t\tbasic_os=moxiebox\n\t\t\t\t;;\n\t\t\tmsdos)\n\t\t\t\tbasic_machine=i386-pc\n\t\t\t\tbasic_os=msdos\n\t\t\t\t;;\n\t\t\tmsys)\n\t\t\t\tbasic_machine=i686-pc\n\t\t\t\tbasic_os=msys\n\t\t\t\t;;\n\t\t\tmvs)\n\t\t\t\tbasic_machine=i370-ibm\n\t\t\t\tbasic_os=mvs\n\t\t\t\t;;\n\t\t\tnacl)\n\t\t\t\tbasic_machine=le32-unknown\n\t\t\t\tbasic_os=nacl\n\t\t\t\t;;\n\t\t\tncr3000)\n\t\t\t\tbasic_machine=i486-ncr\n\t\t\t\tbasic_os=sysv4\n\t\t\t\t;;\n\t\t\tnetbsd386)\n\t\t\t\tbasic_machine=i386-pc\n\t\t\t\tbasic_os=netbsd\n\t\t\t\t;;\n\t\t\tnetwinder)\n\t\t\t\tbasic_machine=armv4l-rebel\n\t\t\t\tbasic_os=linux\n\t\t\t\t;;\n\t\t\tnews | news700 | news800 | news900)\n\t\t\t\tbasic_machine=m68k-sony\n\t\t\t\tbasic_os=newsos\n\t\t\t\t;;\n\t\t\tnews1000)\n\t\t\t\tbasic_machine=m68030-sony\n\t\t\t\tbasic_os=newsos\n\t\t\t\t;;\n\t\t\tnecv70)\n\t\t\t\tbasic_machine=v70-nec\n\t\t\t\tbasic_os=sysv\n\t\t\t\t;;\n\t\t\tnh3000)\n\t\t\t\tbasic_machine=m68k-harris\n\t\t\t\tbasic_os=cxux\n\t\t\t\t;;\n\t\t\tnh[45]000)\n\t\t\t\tbasic_machine=m88k-harris\n\t\t\t\tbasic_os=cxux\n\t\t\t\t;;\n\t\t\tnindy960)\n\t\t\t\tbasic_machine=i960-intel\n\t\t\t\tbasic_os=nindy\n\t\t\t\t;;\n\t\t\tmon960)\n\t\t\t\tbasic_machine=i960-intel\n\t\t\t\tbasic_os=mon960\n\t\t\t\t;;\n\t\t\tnonstopux)\n\t\t\t\tbasic_machine=mips-compaq\n\t\t\t\tbasic_os=nonstopux\n\t\t\t\t;;\n\t\t\tos400)\n\t\t\t\tbasic_machine=powerpc-ibm\n\t\t\t\tbasic_os=os400\n\t\t\t\t;;\n\t\t\tOSE68000 | ose68000)\n\t\t\t\tbasic_machine=m68000-ericsson\n\t\t\t\tbasic_os=ose\n\t\t\t\t;;\n\t\t\tos68k)\n\t\t\t\tbasic_machine=m68k-none\n\t\t\t\tbasic_os=os68k\n\t\t\t\t;;\n\t\t\tparagon)\n\t\t\t\tbasic_machine=i860-intel\n\t\t\t\tbasic_os=osf\n\t\t\t\t;;\n\t\t\tparisc)\n\t\t\t\tbasic_machine=hppa-unknown\n\t\t\t\tbasic_os=linux\n\t\t\t\t;;\n\t\t\tpsp)\n\t\t\t\tbasic_machine=mipsallegrexel-sony\n\t\t\t\tbasic_os=psp\n\t\t\t\t;;\n\t\t\tpw32)\n\t\t\t\tbasic_machine=i586-unknown\n\t\t\t\tbasic_os=pw32\n\t\t\t\t;;\n\t\t\trdos | rdos64)\n\t\t\t\tbasic_machine=x86_64-pc\n\t\t\t\tbasic_os=rdos\n\t\t\t\t;;\n\t\t\trdos32)\n\t\t\t\tbasic_machine=i386-pc\n\t\t\t\tbasic_os=rdos\n\t\t\t\t;;\n\t\t\trom68k)\n\t\t\t\tbasic_machine=m68k-rom68k\n\t\t\t\tbasic_os=coff\n\t\t\t\t;;\n\t\t\tsa29200)\n\t\t\t\tbasic_machine=a29k-amd\n\t\t\t\tbasic_os=udi\n\t\t\t\t;;\n\t\t\tsei)\n\t\t\t\tbasic_machine=mips-sei\n\t\t\t\tbasic_os=seiux\n\t\t\t\t;;\n\t\t\tsequent)\n\t\t\t\tbasic_machine=i386-sequent\n\t\t\t\tbasic_os=\n\t\t\t\t;;\n\t\t\tsps7)\n\t\t\t\tbasic_machine=m68k-bull\n\t\t\t\tbasic_os=sysv2\n\t\t\t\t;;\n\t\t\tst2000)\n\t\t\t\tbasic_machine=m68k-tandem\n\t\t\t\tbasic_os=\n\t\t\t\t;;\n\t\t\tstratus)\n\t\t\t\tbasic_machine=i860-stratus\n\t\t\t\tbasic_os=sysv4\n\t\t\t\t;;\n\t\t\tsun2)\n\t\t\t\tbasic_machine=m68000-sun\n\t\t\t\tbasic_os=\n\t\t\t\t;;\n\t\t\tsun2os3)\n\t\t\t\tbasic_machine=m68000-sun\n\t\t\t\tbasic_os=sunos3\n\t\t\t\t;;\n\t\t\tsun2os4)\n\t\t\t\tbasic_machine=m68000-sun\n\t\t\t\tbasic_os=sunos4\n\t\t\t\t;;\n\t\t\tsun3)\n\t\t\t\tbasic_machine=m68k-sun\n\t\t\t\tbasic_os=\n\t\t\t\t;;\n\t\t\tsun3os3)\n\t\t\t\tbasic_machine=m68k-sun\n\t\t\t\tbasic_os=sunos3\n\t\t\t\t;;\n\t\t\tsun3os4)\n\t\t\t\tbasic_machine=m68k-sun\n\t\t\t\tbasic_os=sunos4\n\t\t\t\t;;\n\t\t\tsun4)\n\t\t\t\tbasic_machine=sparc-sun\n\t\t\t\tbasic_os=\n\t\t\t\t;;\n\t\t\tsun4os3)\n\t\t\t\tbasic_machine=sparc-sun\n\t\t\t\tbasic_os=sunos3\n\t\t\t\t;;\n\t\t\tsun4os4)\n\t\t\t\tbasic_machine=sparc-sun\n\t\t\t\tbasic_os=sunos4\n\t\t\t\t;;\n\t\t\tsun4sol2)\n\t\t\t\tbasic_machine=sparc-sun\n\t\t\t\tbasic_os=solaris2\n\t\t\t\t;;\n\t\t\tsun386 | sun386i | roadrunner)\n\t\t\t\tbasic_machine=i386-sun\n\t\t\t\tbasic_os=\n\t\t\t\t;;\n\t\t\tsv1)\n\t\t\t\tbasic_machine=sv1-cray\n\t\t\t\tbasic_os=unicos\n\t\t\t\t;;\n\t\t\tsymmetry)\n\t\t\t\tbasic_machine=i386-sequent\n\t\t\t\tbasic_os=dynix\n\t\t\t\t;;\n\t\t\tt3e)\n\t\t\t\tbasic_machine=alphaev5-cray\n\t\t\t\tbasic_os=unicos\n\t\t\t\t;;\n\t\t\tt90)\n\t\t\t\tbasic_machine=t90-cray\n\t\t\t\tbasic_os=unicos\n\t\t\t\t;;\n\t\t\ttoad1)\n\t\t\t\tbasic_machine=pdp10-xkl\n\t\t\t\tbasic_os=tops20\n\t\t\t\t;;\n\t\t\ttpf)\n\t\t\t\tbasic_machine=s390x-ibm\n\t\t\t\tbasic_os=tpf\n\t\t\t\t;;\n\t\t\tudi29k)\n\t\t\t\tbasic_machine=a29k-amd\n\t\t\t\tbasic_os=udi\n\t\t\t\t;;\n\t\t\tultra3)\n\t\t\t\tbasic_machine=a29k-nyu\n\t\t\t\tbasic_os=sym1\n\t\t\t\t;;\n\t\t\tv810 | necv810)\n\t\t\t\tbasic_machine=v810-nec\n\t\t\t\tbasic_os=none\n\t\t\t\t;;\n\t\t\tvaxv)\n\t\t\t\tbasic_machine=vax-dec\n\t\t\t\tbasic_os=sysv\n\t\t\t\t;;\n\t\t\tvms)\n\t\t\t\tbasic_machine=vax-dec\n\t\t\t\tbasic_os=vms\n\t\t\t\t;;\n\t\t\tvsta)\n\t\t\t\tbasic_machine=i386-pc\n\t\t\t\tbasic_os=vsta\n\t\t\t\t;;\n\t\t\tvxworks960)\n\t\t\t\tbasic_machine=i960-wrs\n\t\t\t\tbasic_os=vxworks\n\t\t\t\t;;\n\t\t\tvxworks68)\n\t\t\t\tbasic_machine=m68k-wrs\n\t\t\t\tbasic_os=vxworks\n\t\t\t\t;;\n\t\t\tvxworks29k)\n\t\t\t\tbasic_machine=a29k-wrs\n\t\t\t\tbasic_os=vxworks\n\t\t\t\t;;\n\t\t\txbox)\n\t\t\t\tbasic_machine=i686-pc\n\t\t\t\tbasic_os=mingw32\n\t\t\t\t;;\n\t\t\tymp)\n\t\t\t\tbasic_machine=ymp-cray\n\t\t\t\tbasic_os=unicos\n\t\t\t\t;;\n\t\t\t*)\n\t\t\t\tbasic_machine=$1\n\t\t\t\tbasic_os=\n\t\t\t\t;;\n\t\tesac\n\t\t;;\nesac\n\n# Decode 1-component or ad-hoc basic machines\ncase $basic_machine in\n\t# Here we handle the default manufacturer of certain CPU types.  It is in\n\t# some cases the only manufacturer, in others, it is the most popular.\n\tw89k)\n\t\tcpu=hppa1.1\n\t\tvendor=winbond\n\t\t;;\n\top50n)\n\t\tcpu=hppa1.1\n\t\tvendor=oki\n\t\t;;\n\top60c)\n\t\tcpu=hppa1.1\n\t\tvendor=oki\n\t\t;;\n\tibm*)\n\t\tcpu=i370\n\t\tvendor=ibm\n\t\t;;\n\torion105)\n\t\tcpu=clipper\n\t\tvendor=highlevel\n\t\t;;\n\tmac | mpw | mac-mpw)\n\t\tcpu=m68k\n\t\tvendor=apple\n\t\t;;\n\tpmac | pmac-mpw)\n\t\tcpu=powerpc\n\t\tvendor=apple\n\t\t;;\n\n\t# Recognize the various machine names and aliases which stand\n\t# for a CPU type and a company and sometimes even an OS.\n\t3b1 | 7300 | 7300-att | att-7300 | pc7300 | safari | unixpc)\n\t\tcpu=m68000\n\t\tvendor=att\n\t\t;;\n\t3b*)\n\t\tcpu=we32k\n\t\tvendor=att\n\t\t;;\n\tbluegene*)\n\t\tcpu=powerpc\n\t\tvendor=ibm\n\t\tbasic_os=cnk\n\t\t;;\n\tdecsystem10* | dec10*)\n\t\tcpu=pdp10\n\t\tvendor=dec\n\t\tbasic_os=tops10\n\t\t;;\n\tdecsystem20* | dec20*)\n\t\tcpu=pdp10\n\t\tvendor=dec\n\t\tbasic_os=tops20\n\t\t;;\n\tdelta | 3300 | motorola-3300 | motorola-delta \\\n\t      | 3300-motorola | delta-motorola)\n\t\tcpu=m68k\n\t\tvendor=motorola\n\t\t;;\n\tdpx2*)\n\t\tcpu=m68k\n\t\tvendor=bull\n\t\tbasic_os=sysv3\n\t\t;;\n\tencore | umax | mmax)\n\t\tcpu=ns32k\n\t\tvendor=encore\n\t\t;;\n\telxsi)\n\t\tcpu=elxsi\n\t\tvendor=elxsi\n\t\tbasic_os=${basic_os:-bsd}\n\t\t;;\n\tfx2800)\n\t\tcpu=i860\n\t\tvendor=alliant\n\t\t;;\n\tgenix)\n\t\tcpu=ns32k\n\t\tvendor=ns\n\t\t;;\n\th3050r* | hiux*)\n\t\tcpu=hppa1.1\n\t\tvendor=hitachi\n\t\tbasic_os=hiuxwe2\n\t\t;;\n\thp3k9[0-9][0-9] | hp9[0-9][0-9])\n\t\tcpu=hppa1.0\n\t\tvendor=hp\n\t\t;;\n\thp9k2[0-9][0-9] | hp9k31[0-9])\n\t\tcpu=m68000\n\t\tvendor=hp\n\t\t;;\n\thp9k3[2-9][0-9])\n\t\tcpu=m68k\n\t\tvendor=hp\n\t\t;;\n\thp9k6[0-9][0-9] | hp6[0-9][0-9])\n\t\tcpu=hppa1.0\n\t\tvendor=hp\n\t\t;;\n\thp9k7[0-79][0-9] | hp7[0-79][0-9])\n\t\tcpu=hppa1.1\n\t\tvendor=hp\n\t\t;;\n\thp9k78[0-9] | hp78[0-9])\n\t\t# FIXME: really hppa2.0-hp\n\t\tcpu=hppa1.1\n\t\tvendor=hp\n\t\t;;\n\thp9k8[67]1 | hp8[67]1 | hp9k80[24] | hp80[24] | hp9k8[78]9 | hp8[78]9 | hp9k893 | hp893)\n\t\t# FIXME: really hppa2.0-hp\n\t\tcpu=hppa1.1\n\t\tvendor=hp\n\t\t;;\n\thp9k8[0-9][13679] | hp8[0-9][13679])\n\t\tcpu=hppa1.1\n\t\tvendor=hp\n\t\t;;\n\thp9k8[0-9][0-9] | hp8[0-9][0-9])\n\t\tcpu=hppa1.0\n\t\tvendor=hp\n\t\t;;\n\ti*86v32)\n\t\tcpu=$(echo \"$1\" | sed -e 's/86.*/86/')\n\t\tvendor=pc\n\t\tbasic_os=sysv32\n\t\t;;\n\ti*86v4*)\n\t\tcpu=$(echo \"$1\" | sed -e 's/86.*/86/')\n\t\tvendor=pc\n\t\tbasic_os=sysv4\n\t\t;;\n\ti*86v)\n\t\tcpu=$(echo \"$1\" | sed -e 's/86.*/86/')\n\t\tvendor=pc\n\t\tbasic_os=sysv\n\t\t;;\n\ti*86sol2)\n\t\tcpu=$(echo \"$1\" | sed -e 's/86.*/86/')\n\t\tvendor=pc\n\t\tbasic_os=solaris2\n\t\t;;\n\tj90 | j90-cray)\n\t\tcpu=j90\n\t\tvendor=cray\n\t\tbasic_os=${basic_os:-unicos}\n\t\t;;\n\tiris | iris4d)\n\t\tcpu=mips\n\t\tvendor=sgi\n\t\tcase $basic_os in\n\t\t    irix*)\n\t\t\t;;\n\t\t    *)\n\t\t\tbasic_os=irix4\n\t\t\t;;\n\t\tesac\n\t\t;;\n\tminiframe)\n\t\tcpu=m68000\n\t\tvendor=convergent\n\t\t;;\n\t*mint | mint[0-9]* | *MiNT | *MiNT[0-9]*)\n\t\tcpu=m68k\n\t\tvendor=atari\n\t\tbasic_os=mint\n\t\t;;\n\tnews-3600 | risc-news)\n\t\tcpu=mips\n\t\tvendor=sony\n\t\tbasic_os=newsos\n\t\t;;\n\tnext | m*-next)\n\t\tcpu=m68k\n\t\tvendor=next\n\t\tcase $basic_os in\n\t\t    openstep*)\n\t\t        ;;\n\t\t    nextstep*)\n\t\t\t;;\n\t\t    ns2*)\n\t\t      basic_os=nextstep2\n\t\t\t;;\n\t\t    *)\n\t\t      basic_os=nextstep3\n\t\t\t;;\n\t\tesac\n\t\t;;\n\tnp1)\n\t\tcpu=np1\n\t\tvendor=gould\n\t\t;;\n\top50n-* | op60c-*)\n\t\tcpu=hppa1.1\n\t\tvendor=oki\n\t\tbasic_os=proelf\n\t\t;;\n\tpa-hitachi)\n\t\tcpu=hppa1.1\n\t\tvendor=hitachi\n\t\tbasic_os=hiuxwe2\n\t\t;;\n\tpbd)\n\t\tcpu=sparc\n\t\tvendor=tti\n\t\t;;\n\tpbb)\n\t\tcpu=m68k\n\t\tvendor=tti\n\t\t;;\n\tpc532)\n\t\tcpu=ns32k\n\t\tvendor=pc532\n\t\t;;\n\tpn)\n\t\tcpu=pn\n\t\tvendor=gould\n\t\t;;\n\tpower)\n\t\tcpu=power\n\t\tvendor=ibm\n\t\t;;\n\tps2)\n\t\tcpu=i386\n\t\tvendor=ibm\n\t\t;;\n\trm[46]00)\n\t\tcpu=mips\n\t\tvendor=siemens\n\t\t;;\n\trtpc | rtpc-*)\n\t\tcpu=romp\n\t\tvendor=ibm\n\t\t;;\n\tsde)\n\t\tcpu=mipsisa32\n\t\tvendor=sde\n\t\tbasic_os=${basic_os:-elf}\n\t\t;;\n\tsimso-wrs)\n\t\tcpu=sparclite\n\t\tvendor=wrs\n\t\tbasic_os=vxworks\n\t\t;;\n\ttower | tower-32)\n\t\tcpu=m68k\n\t\tvendor=ncr\n\t\t;;\n\tvpp*|vx|vx-*)\n\t\tcpu=f301\n\t\tvendor=fujitsu\n\t\t;;\n\tw65)\n\t\tcpu=w65\n\t\tvendor=wdc\n\t\t;;\n\tw89k-*)\n\t\tcpu=hppa1.1\n\t\tvendor=winbond\n\t\tbasic_os=proelf\n\t\t;;\n\tnone)\n\t\tcpu=none\n\t\tvendor=none\n\t\t;;\n\tleon|leon[3-9])\n\t\tcpu=sparc\n\t\tvendor=$basic_machine\n\t\t;;\n\tleon-*|leon[3-9]-*)\n\t\tcpu=sparc\n\t\tvendor=$(echo \"$basic_machine\" | sed 's/-.*//')\n\t\t;;\n\n\t*-*)\n\t\t# shellcheck disable=SC2162\n\t\tIFS=\"-\" read cpu vendor <<EOF\n$basic_machine\nEOF\n\t\t;;\n\t# We use `pc' rather than `unknown'\n\t# because (1) that's what they normally are, and\n\t# (2) the word \"unknown\" tends to confuse beginning users.\n\ti*86 | x86_64)\n\t\tcpu=$basic_machine\n\t\tvendor=pc\n\t\t;;\n\t# These rules are duplicated from below for sake of the special case above;\n\t# i.e. things that normalized to x86 arches should also default to \"pc\"\n\tpc98)\n\t\tcpu=i386\n\t\tvendor=pc\n\t\t;;\n\tx64 | amd64)\n\t\tcpu=x86_64\n\t\tvendor=pc\n\t\t;;\n\t# Recognize the basic CPU types without company name.\n\t*)\n\t\tcpu=$basic_machine\n\t\tvendor=unknown\n\t\t;;\nesac\n\nunset -v basic_machine\n\n# Decode basic machines in the full and proper CPU-Company form.\ncase $cpu-$vendor in\n\t# Here we handle the default manufacturer of certain CPU types in canonical form. It is in\n\t# some cases the only manufacturer, in others, it is the most popular.\n\tcraynv-unknown)\n\t\tvendor=cray\n\t\tbasic_os=${basic_os:-unicosmp}\n\t\t;;\n\tc90-unknown | c90-cray)\n\t\tvendor=cray\n\t\tbasic_os=${Basic_os:-unicos}\n\t\t;;\n\tfx80-unknown)\n\t\tvendor=alliant\n\t\t;;\n\tromp-unknown)\n\t\tvendor=ibm\n\t\t;;\n\tmmix-unknown)\n\t\tvendor=knuth\n\t\t;;\n\tmicroblaze-unknown | microblazeel-unknown)\n\t\tvendor=xilinx\n\t\t;;\n\trs6000-unknown)\n\t\tvendor=ibm\n\t\t;;\n\tvax-unknown)\n\t\tvendor=dec\n\t\t;;\n\tpdp11-unknown)\n\t\tvendor=dec\n\t\t;;\n\twe32k-unknown)\n\t\tvendor=att\n\t\t;;\n\tcydra-unknown)\n\t\tvendor=cydrome\n\t\t;;\n\ti370-ibm*)\n\t\tvendor=ibm\n\t\t;;\n\torion-unknown)\n\t\tvendor=highlevel\n\t\t;;\n\txps-unknown | xps100-unknown)\n\t\tcpu=xps100\n\t\tvendor=honeywell\n\t\t;;\n\n\t# Here we normalize CPU types with a missing or matching vendor\n\tdpx20-unknown | dpx20-bull)\n\t\tcpu=rs6000\n\t\tvendor=bull\n\t\tbasic_os=${basic_os:-bosx}\n\t\t;;\n\n\t# Here we normalize CPU types irrespective of the vendor\n\tamd64-*)\n\t\tcpu=x86_64\n\t\t;;\n\tblackfin-*)\n\t\tcpu=bfin\n\t\tbasic_os=linux\n\t\t;;\n\tc54x-*)\n\t\tcpu=tic54x\n\t\t;;\n\tc55x-*)\n\t\tcpu=tic55x\n\t\t;;\n\tc6x-*)\n\t\tcpu=tic6x\n\t\t;;\n\te500v[12]-*)\n\t\tcpu=powerpc\n\t\tbasic_os=${basic_os}\"spe\"\n\t\t;;\n\tmips3*-*)\n\t\tcpu=mips64\n\t\t;;\n\tms1-*)\n\t\tcpu=mt\n\t\t;;\n\tm68knommu-*)\n\t\tcpu=m68k\n\t\tbasic_os=linux\n\t\t;;\n\tm9s12z-* | m68hcs12z-* | hcs12z-* | s12z-*)\n\t\tcpu=s12z\n\t\t;;\n\topenrisc-*)\n\t\tcpu=or32\n\t\t;;\n\tparisc-*)\n\t\tcpu=hppa\n\t\tbasic_os=linux\n\t\t;;\n\tpentium-* | p5-* | k5-* | k6-* | nexgen-* | viac3-*)\n\t\tcpu=i586\n\t\t;;\n\tpentiumpro-* | p6-* | 6x86-* | athlon-* | athalon_*-*)\n\t\tcpu=i686\n\t\t;;\n\tpentiumii-* | pentium2-* | pentiumiii-* | pentium3-*)\n\t\tcpu=i686\n\t\t;;\n\tpentium4-*)\n\t\tcpu=i786\n\t\t;;\n\tpc98-*)\n\t\tcpu=i386\n\t\t;;\n\tppc-* | ppcbe-*)\n\t\tcpu=powerpc\n\t\t;;\n\tppcle-* | powerpclittle-*)\n\t\tcpu=powerpcle\n\t\t;;\n\tppc64-*)\n\t\tcpu=powerpc64\n\t\t;;\n\tppc64le-* | powerpc64little-*)\n\t\tcpu=powerpc64le\n\t\t;;\n\tsb1-*)\n\t\tcpu=mipsisa64sb1\n\t\t;;\n\tsb1el-*)\n\t\tcpu=mipsisa64sb1el\n\t\t;;\n\tsh5e[lb]-*)\n\t\tcpu=$(echo \"$cpu\" | sed 's/^\\(sh.\\)e\\(.\\)$/\\1\\2e/')\n\t\t;;\n\tspur-*)\n\t\tcpu=spur\n\t\t;;\n\tstrongarm-* | thumb-*)\n\t\tcpu=arm\n\t\t;;\n\ttx39-*)\n\t\tcpu=mipstx39\n\t\t;;\n\ttx39el-*)\n\t\tcpu=mipstx39el\n\t\t;;\n\tx64-*)\n\t\tcpu=x86_64\n\t\t;;\n\txscale-* | xscalee[bl]-*)\n\t\tcpu=$(echo \"$cpu\" | sed 's/^xscale/arm/')\n\t\t;;\n\tarm64-*)\n\t\tcpu=aarch64\n\t\t;;\n\n\t# Recognize the canonical CPU Types that limit and/or modify the\n\t# company names they are paired with.\n\tcr16-*)\n\t\tbasic_os=${basic_os:-elf}\n\t\t;;\n\tcrisv32-* | etraxfs*-*)\n\t\tcpu=crisv32\n\t\tvendor=axis\n\t\t;;\n\tcris-* | etrax*-*)\n\t\tcpu=cris\n\t\tvendor=axis\n\t\t;;\n\tcrx-*)\n\t\tbasic_os=${basic_os:-elf}\n\t\t;;\n\tneo-tandem)\n\t\tcpu=neo\n\t\tvendor=tandem\n\t\t;;\n\tnse-tandem)\n\t\tcpu=nse\n\t\tvendor=tandem\n\t\t;;\n\tnsr-tandem)\n\t\tcpu=nsr\n\t\tvendor=tandem\n\t\t;;\n\tnsv-tandem)\n\t\tcpu=nsv\n\t\tvendor=tandem\n\t\t;;\n\tnsx-tandem)\n\t\tcpu=nsx\n\t\tvendor=tandem\n\t\t;;\n\tmipsallegrexel-sony)\n\t\tcpu=mipsallegrexel\n\t\tvendor=sony\n\t\t;;\n\ttile*-*)\n\t\tbasic_os=${basic_os:-linux-gnu}\n\t\t;;\n\n\t*)\n\t\t# Recognize the canonical CPU types that are allowed with any\n\t\t# company name.\n\t\tcase $cpu in\n\t\t\t1750a | 580 \\\n\t\t\t| a29k \\\n\t\t\t| aarch64 | aarch64_be \\\n\t\t\t| abacus \\\n\t\t\t| alpha | alphaev[4-8] | alphaev56 | alphaev6[78] \\\n\t\t\t| alpha64 | alpha64ev[4-8] | alpha64ev56 | alpha64ev6[78] \\\n\t\t\t| alphapca5[67] | alpha64pca5[67] \\\n\t\t\t| am33_2.0 \\\n\t\t\t| amdgcn \\\n\t\t\t| arc | arceb | arc64 \\\n\t\t\t| arm | arm[lb]e | arme[lb] | armv* \\\n\t\t\t| avr | avr32 \\\n\t\t\t| asmjs \\\n\t\t\t| ba \\\n\t\t\t| be32 | be64 \\\n\t\t\t| bfin | bpf | bs2000 \\\n\t\t\t| c[123]* | c30 | [cjt]90 | c4x \\\n\t\t\t| c8051 | clipper | craynv | csky | cydra \\\n\t\t\t| d10v | d30v | dlx | dsp16xx \\\n\t\t\t| e2k | elxsi | epiphany \\\n\t\t\t| f30[01] | f700 | fido | fr30 | frv | ft32 | fx80 \\\n\t\t\t| h8300 | h8500 \\\n\t\t\t| hppa | hppa1.[01] | hppa2.0 | hppa2.0[nw] | hppa64 \\\n\t\t\t| hexagon \\\n\t\t\t| i370 | i*86 | i860 | i960 | ia16 | ia64 \\\n\t\t\t| ip2k | iq2000 \\\n\t\t\t| k1om \\\n\t\t\t| le32 | le64 \\\n\t\t\t| lm32 \\\n\t\t\t| loongarch32 | loongarch64 | loongarchx32 \\\n\t\t\t| m32c | m32r | m32rle \\\n\t\t\t| m5200 | m68000 | m680[012346]0 | m68360 | m683?2 | m68k \\\n\t\t\t| m6811 | m68hc11 | m6812 | m68hc12 | m68hcs12x \\\n\t\t\t| m88110 | m88k | maxq | mb | mcore | mep | metag \\\n\t\t\t| microblaze | microblazeel \\\n\t\t\t| mips | mipsbe | mipseb | mipsel | mipsle \\\n\t\t\t| mips16 \\\n\t\t\t| mips64 | mips64eb | mips64el \\\n\t\t\t| mips64octeon | mips64octeonel \\\n\t\t\t| mips64orion | mips64orionel \\\n\t\t\t| mips64r5900 | mips64r5900el \\\n\t\t\t| mips64vr | mips64vrel \\\n\t\t\t| mips64vr4100 | mips64vr4100el \\\n\t\t\t| mips64vr4300 | mips64vr4300el \\\n\t\t\t| mips64vr5000 | mips64vr5000el \\\n\t\t\t| mips64vr5900 | mips64vr5900el \\\n\t\t\t| mipsisa32 | mipsisa32el \\\n\t\t\t| mipsisa32r2 | mipsisa32r2el \\\n\t\t\t| mipsisa32r3 | mipsisa32r3el \\\n\t\t\t| mipsisa32r5 | mipsisa32r5el \\\n\t\t\t| mipsisa32r6 | mipsisa32r6el \\\n\t\t\t| mipsisa64 | mipsisa64el \\\n\t\t\t| mipsisa64r2 | mipsisa64r2el \\\n\t\t\t| mipsisa64r3 | mipsisa64r3el \\\n\t\t\t| mipsisa64r5 | mipsisa64r5el \\\n\t\t\t| mipsisa64r6 | mipsisa64r6el \\\n\t\t\t| mipsisa64sb1 | mipsisa64sb1el \\\n\t\t\t| mipsisa64sr71k | mipsisa64sr71kel \\\n\t\t\t| mipsr5900 | mipsr5900el \\\n\t\t\t| mipstx39 | mipstx39el \\\n\t\t\t| mmix \\\n\t\t\t| mn10200 | mn10300 \\\n\t\t\t| moxie \\\n\t\t\t| mt \\\n\t\t\t| msp430 \\\n\t\t\t| nds32 | nds32le | nds32be \\\n\t\t\t| nfp \\\n\t\t\t| nios | nios2 | nios2eb | nios2el \\\n\t\t\t| none | np1 | ns16k | ns32k | nvptx \\\n\t\t\t| open8 \\\n\t\t\t| or1k* \\\n\t\t\t| or32 \\\n\t\t\t| orion \\\n\t\t\t| picochip \\\n\t\t\t| pdp10 | pdp11 | pj | pjl | pn | power \\\n\t\t\t| powerpc | powerpc64 | powerpc64le | powerpcle | powerpcspe \\\n\t\t\t| pru \\\n\t\t\t| pyramid \\\n\t\t\t| riscv | riscv32 | riscv32be | riscv64 | riscv64be \\\n\t\t\t| rl78 | romp | rs6000 | rx \\\n\t\t\t| s390 | s390x \\\n\t\t\t| score \\\n\t\t\t| sh | shl \\\n\t\t\t| sh[1234] | sh[24]a | sh[24]ae[lb] | sh[23]e | she[lb] | sh[lb]e \\\n\t\t\t| sh[1234]e[lb] |  sh[12345][lb]e | sh[23]ele | sh64 | sh64le \\\n\t\t\t| sparc | sparc64 | sparc64b | sparc64v | sparc86x | sparclet \\\n\t\t\t| sparclite \\\n\t\t\t| sparcv8 | sparcv9 | sparcv9b | sparcv9v | sv1 | sx* \\\n\t\t\t| spu \\\n\t\t\t| tahoe \\\n\t\t\t| thumbv7* \\\n\t\t\t| tic30 | tic4x | tic54x | tic55x | tic6x | tic80 \\\n\t\t\t| tron \\\n\t\t\t| ubicom32 \\\n\t\t\t| v70 | v850 | v850e | v850e1 | v850es | v850e2 | v850e2v3 \\\n\t\t\t| vax \\\n\t\t\t| visium \\\n\t\t\t| w65 \\\n\t\t\t| wasm32 | wasm64 \\\n\t\t\t| we32k \\\n\t\t\t| x86 | x86_64 | xc16x | xgate | xps100 \\\n\t\t\t| xstormy16 | xtensa* \\\n\t\t\t| ymp \\\n\t\t\t| z8k | z80)\n\t\t\t\t;;\n\n\t\t\t*)\n\t\t\t\techo Invalid configuration \\`\"$1\"\\': machine \\`\"$cpu-$vendor\"\\' not recognized 1>&2\n\t\t\t\texit 1\n\t\t\t\t;;\n\t\tesac\n\t\t;;\nesac\n\n# Here we canonicalize certain aliases for manufacturers.\ncase $vendor in\n\tdigital*)\n\t\tvendor=dec\n\t\t;;\n\tcommodore*)\n\t\tvendor=cbm\n\t\t;;\n\t*)\n\t\t;;\nesac\n\n# Decode manufacturer-specific aliases for certain operating systems.\n\nif test x$basic_os != x\nthen\n\n# First recognize some ad-hoc caes, or perhaps split kernel-os, or else just\n# set os.\ncase $basic_os in\n\tgnu/linux*)\n\t\tkernel=linux\n\t\tos=$(echo $basic_os | sed -e 's|gnu/linux|gnu|')\n\t\t;;\n\tos2-emx)\n\t\tkernel=os2\n\t\tos=$(echo $basic_os | sed -e 's|os2-emx|emx|')\n\t\t;;\n\tnto-qnx*)\n\t\tkernel=nto\n\t\tos=$(echo $basic_os | sed -e 's|nto-qnx|qnx|')\n\t\t;;\n\t*-*)\n\t\t# shellcheck disable=SC2162\n\t\tIFS=\"-\" read kernel os <<EOF\n$basic_os\nEOF\n\t\t;;\n\t# Default OS when just kernel was specified\n\tnto*)\n\t\tkernel=nto\n\t\tos=$(echo $basic_os | sed -e 's|nto|qnx|')\n\t\t;;\n\tlinux*)\n\t\tkernel=linux\n\t\tos=$(echo $basic_os | sed -e 's|linux|gnu|')\n\t\t;;\n\t*)\n\t\tkernel=\n\t\tos=$basic_os\n\t\t;;\nesac\n\n# Now, normalize the OS (knowing we just have one component, it's not a kernel,\n# etc.)\ncase $os in\n\t# First match some system type aliases that might get confused\n\t# with valid system types.\n\t# solaris* is a basic system type, with this one exception.\n\tauroraux)\n\t\tos=auroraux\n\t\t;;\n\tbluegene*)\n\t\tos=cnk\n\t\t;;\n\tsolaris1 | solaris1.*)\n\t\tos=$(echo $os | sed -e 's|solaris1|sunos4|')\n\t\t;;\n\tsolaris)\n\t\tos=solaris2\n\t\t;;\n\tunixware*)\n\t\tos=sysv4.2uw\n\t\t;;\n\t# es1800 is here to avoid being matched by es* (a different OS)\n\tes1800*)\n\t\tos=ose\n\t\t;;\n\t# Some version numbers need modification\n\tchorusos*)\n\t\tos=chorusos\n\t\t;;\n\tisc)\n\t\tos=isc2.2\n\t\t;;\n\tsco6)\n\t\tos=sco5v6\n\t\t;;\n\tsco5)\n\t\tos=sco3.2v5\n\t\t;;\n\tsco4)\n\t\tos=sco3.2v4\n\t\t;;\n\tsco3.2.[4-9]*)\n\t\tos=$(echo $os | sed -e 's/sco3.2./sco3.2v/')\n\t\t;;\n\tsco*v* | scout)\n\t\t# Don't match below\n\t\t;;\n\tsco*)\n\t\tos=sco3.2v2\n\t\t;;\n\tpsos*)\n\t\tos=psos\n\t\t;;\n\tqnx*)\n\t\tos=qnx\n\t\t;;\n\thiux*)\n\t\tos=hiuxwe2\n\t\t;;\n\tlynx*178)\n\t\tos=lynxos178\n\t\t;;\n\tlynx*5)\n\t\tos=lynxos5\n\t\t;;\n\tlynxos*)\n\t\t# don't get caught up in next wildcard\n\t\t;;\n\tlynx*)\n\t\tos=lynxos\n\t\t;;\n\tmac[0-9]*)\n\t\tos=$(echo \"$os\" | sed -e 's|mac|macos|')\n\t\t;;\n\topened*)\n\t\tos=openedition\n\t\t;;\n\tos400*)\n\t\tos=os400\n\t\t;;\n\tsunos5*)\n\t\tos=$(echo \"$os\" | sed -e 's|sunos5|solaris2|')\n\t\t;;\n\tsunos6*)\n\t\tos=$(echo \"$os\" | sed -e 's|sunos6|solaris3|')\n\t\t;;\n\twince*)\n\t\tos=wince\n\t\t;;\n\tutek*)\n\t\tos=bsd\n\t\t;;\n\tdynix*)\n\t\tos=bsd\n\t\t;;\n\tacis*)\n\t\tos=aos\n\t\t;;\n\tatheos*)\n\t\tos=atheos\n\t\t;;\n\tsyllable*)\n\t\tos=syllable\n\t\t;;\n\t386bsd)\n\t\tos=bsd\n\t\t;;\n\tctix* | uts*)\n\t\tos=sysv\n\t\t;;\n\tnova*)\n\t\tos=rtmk-nova\n\t\t;;\n\tns2)\n\t\tos=nextstep2\n\t\t;;\n\t# Preserve the version number of sinix5.\n\tsinix5.*)\n\t\tos=$(echo $os | sed -e 's|sinix|sysv|')\n\t\t;;\n\tsinix*)\n\t\tos=sysv4\n\t\t;;\n\ttpf*)\n\t\tos=tpf\n\t\t;;\n\ttriton*)\n\t\tos=sysv3\n\t\t;;\n\toss*)\n\t\tos=sysv3\n\t\t;;\n\tsvr4*)\n\t\tos=sysv4\n\t\t;;\n\tsvr3)\n\t\tos=sysv3\n\t\t;;\n\tsysvr4)\n\t\tos=sysv4\n\t\t;;\n\tose*)\n\t\tos=ose\n\t\t;;\n\t*mint | mint[0-9]* | *MiNT | MiNT[0-9]*)\n\t\tos=mint\n\t\t;;\n\tdicos*)\n\t\tos=dicos\n\t\t;;\n\tpikeos*)\n\t\t# Until real need of OS specific support for\n\t\t# particular features comes up, bare metal\n\t\t# configurations are quite functional.\n\t\tcase $cpu in\n\t\t    arm*)\n\t\t\tos=eabi\n\t\t\t;;\n\t\t    *)\n\t\t\tos=elf\n\t\t\t;;\n\t\tesac\n\t\t;;\n\t*)\n\t\t# No normalization, but not necessarily accepted, that comes below.\n\t\t;;\nesac\n\nelse\n\n# Here we handle the default operating systems that come with various machines.\n# The value should be what the vendor currently ships out the door with their\n# machine or put another way, the most popular os provided with the machine.\n\n# Note that if you're going to try to match \"-MANUFACTURER\" here (say,\n# \"-sun\"), then you have to tell the case statement up towards the top\n# that MANUFACTURER isn't an operating system.  Otherwise, code above\n# will signal an error saying that MANUFACTURER isn't an operating\n# system, and we'll never get to this point.\n\nkernel=\ncase $cpu-$vendor in\n\tscore-*)\n\t\tos=elf\n\t\t;;\n\tspu-*)\n\t\tos=elf\n\t\t;;\n\t*-acorn)\n\t\tos=riscix1.2\n\t\t;;\n\tarm*-rebel)\n\t\tkernel=linux\n\t\tos=gnu\n\t\t;;\n\tarm*-semi)\n\t\tos=aout\n\t\t;;\n\tc4x-* | tic4x-*)\n\t\tos=coff\n\t\t;;\n\tc8051-*)\n\t\tos=elf\n\t\t;;\n\tclipper-intergraph)\n\t\tos=clix\n\t\t;;\n\thexagon-*)\n\t\tos=elf\n\t\t;;\n\ttic54x-*)\n\t\tos=coff\n\t\t;;\n\ttic55x-*)\n\t\tos=coff\n\t\t;;\n\ttic6x-*)\n\t\tos=coff\n\t\t;;\n\t# This must come before the *-dec entry.\n\tpdp10-*)\n\t\tos=tops20\n\t\t;;\n\tpdp11-*)\n\t\tos=none\n\t\t;;\n\t*-dec | vax-*)\n\t\tos=ultrix4.2\n\t\t;;\n\tm68*-apollo)\n\t\tos=domain\n\t\t;;\n\ti386-sun)\n\t\tos=sunos4.0.2\n\t\t;;\n\tm68000-sun)\n\t\tos=sunos3\n\t\t;;\n\tm68*-cisco)\n\t\tos=aout\n\t\t;;\n\tmep-*)\n\t\tos=elf\n\t\t;;\n\tmips*-cisco)\n\t\tos=elf\n\t\t;;\n\tmips*-*)\n\t\tos=elf\n\t\t;;\n\tor32-*)\n\t\tos=coff\n\t\t;;\n\t*-tti)\t# must be before sparc entry or we get the wrong os.\n\t\tos=sysv3\n\t\t;;\n\tsparc-* | *-sun)\n\t\tos=sunos4.1.1\n\t\t;;\n\tpru-*)\n\t\tos=elf\n\t\t;;\n\t*-be)\n\t\tos=beos\n\t\t;;\n\t*-ibm)\n\t\tos=aix\n\t\t;;\n\t*-knuth)\n\t\tos=mmixware\n\t\t;;\n\t*-wec)\n\t\tos=proelf\n\t\t;;\n\t*-winbond)\n\t\tos=proelf\n\t\t;;\n\t*-oki)\n\t\tos=proelf\n\t\t;;\n\t*-hp)\n\t\tos=hpux\n\t\t;;\n\t*-hitachi)\n\t\tos=hiux\n\t\t;;\n\ti860-* | *-att | *-ncr | *-altos | *-motorola | *-convergent)\n\t\tos=sysv\n\t\t;;\n\t*-cbm)\n\t\tos=amigaos\n\t\t;;\n\t*-dg)\n\t\tos=dgux\n\t\t;;\n\t*-dolphin)\n\t\tos=sysv3\n\t\t;;\n\tm68k-ccur)\n\t\tos=rtu\n\t\t;;\n\tm88k-omron*)\n\t\tos=luna\n\t\t;;\n\t*-next)\n\t\tos=nextstep\n\t\t;;\n\t*-sequent)\n\t\tos=ptx\n\t\t;;\n\t*-crds)\n\t\tos=unos\n\t\t;;\n\t*-ns)\n\t\tos=genix\n\t\t;;\n\ti370-*)\n\t\tos=mvs\n\t\t;;\n\t*-gould)\n\t\tos=sysv\n\t\t;;\n\t*-highlevel)\n\t\tos=bsd\n\t\t;;\n\t*-encore)\n\t\tos=bsd\n\t\t;;\n\t*-sgi)\n\t\tos=irix\n\t\t;;\n\t*-siemens)\n\t\tos=sysv4\n\t\t;;\n\t*-masscomp)\n\t\tos=rtu\n\t\t;;\n\tf30[01]-fujitsu | f700-fujitsu)\n\t\tos=uxpv\n\t\t;;\n\t*-rom68k)\n\t\tos=coff\n\t\t;;\n\t*-*bug)\n\t\tos=coff\n\t\t;;\n\t*-apple)\n\t\tos=macos\n\t\t;;\n\t*-atari*)\n\t\tos=mint\n\t\t;;\n\t*-wrs)\n\t\tos=vxworks\n\t\t;;\n\t*)\n\t\tos=none\n\t\t;;\nesac\n\nfi\n\n# Now, validate our (potentially fixed-up) OS.\ncase $os in\n\t# Sometimes we do \"kernel-libc\", so those need to count as OSes.\n\tmusl* | newlib* | uclibc*)\n\t\t;;\n\t# Likewise for \"kernel-abi\"\n\teabi* | gnueabi*)\n\t\t;;\n\t# VxWorks passes extra cpu info in the 4th filed.\n\tsimlinux | simwindows | spe)\n\t\t;;\n\t# Now accept the basic system types.\n\t# The portable systems comes first.\n\t# Each alternative MUST end in a * to match a version number.\n\tgnu* | android* | bsd* | mach* | minix* | genix* | ultrix* | irix* \\\n\t     | *vms* | esix* | aix* | cnk* | sunos | sunos[34]* \\\n\t     | hpux* | unos* | osf* | luna* | dgux* | auroraux* | solaris* \\\n\t     | sym* |  plan9* | psp* | sim* | xray* | os68k* | v88r* \\\n\t     | hiux* | abug | nacl* | netware* | windows* \\\n\t     | os9* | macos* | osx* | ios* \\\n\t     | mpw* | magic* | mmixware* | mon960* | lnews* \\\n\t     | amigaos* | amigados* | msdos* | newsos* | unicos* | aof* \\\n\t     | aos* | aros* | cloudabi* | sortix* | twizzler* \\\n\t     | nindy* | vxsim* | vxworks* | ebmon* | hms* | mvs* \\\n\t     | clix* | riscos* | uniplus* | iris* | isc* | rtu* | xenix* \\\n\t     | mirbsd* | netbsd* | dicos* | openedition* | ose* \\\n\t     | bitrig* | openbsd* | secbsd* | solidbsd* | libertybsd* | os108* \\\n\t     | ekkobsd* | freebsd* | riscix* | lynxos* | os400* \\\n\t     | bosx* | nextstep* | cxux* | aout* | elf* | oabi* \\\n\t     | ptx* | coff* | ecoff* | winnt* | domain* | vsta* \\\n\t     | udi* | lites* | ieee* | go32* | aux* | hcos* \\\n\t     | chorusrdb* | cegcc* | glidix* | serenity* \\\n\t     | cygwin* | msys* | pe* | moss* | proelf* | rtems* \\\n\t     | midipix* | mingw32* | mingw64* | mint* \\\n\t     | uxpv* | beos* | mpeix* | udk* | moxiebox* \\\n\t     | interix* | uwin* | mks* | rhapsody* | darwin* \\\n\t     | openstep* | oskit* | conix* | pw32* | nonstopux* \\\n\t     | storm-chaos* | tops10* | tenex* | tops20* | its* \\\n\t     | os2* | vos* | palmos* | uclinux* | nucleus* | morphos* \\\n\t     | scout* | superux* | sysv* | rtmk* | tpf* | windiss* \\\n\t     | powermax* | dnix* | nx6 | nx7 | sei* | dragonfly* \\\n\t     | skyos* | haiku* | rdos* | toppers* | drops* | es* \\\n\t     | onefs* | tirtos* | phoenix* | fuchsia* | redox* | bme* \\\n\t     | midnightbsd* | amdhsa* | unleashed* | emscripten* | wasi* \\\n\t     | nsk* | powerunix* | genode* | zvmoe* | qnx* | emx*)\n\t\t;;\n\t# This one is extra strict with allowed versions\n\tsco3.2v2 | sco3.2v[4-9]* | sco5v6*)\n\t\t# Don't forget version if it is 3.2v4 or newer.\n\t\t;;\n\tnone)\n\t\t;;\n\t*)\n\t\techo Invalid configuration \\`\"$1\"\\': OS \\`\"$os\"\\' not recognized 1>&2\n\t\texit 1\n\t\t;;\nesac\n\n# As a final step for OS-related things, validate the OS-kernel combination\n# (given a valid OS), if there is a kernel.\ncase $kernel-$os in\n\tlinux-gnu* | linux-dietlibc* | linux-android* | linux-newlib* | linux-musl* | linux-uclibc* )\n\t\t;;\n\tuclinux-uclibc* )\n\t\t;;\n\t-dietlibc* | -newlib* | -musl* | -uclibc* )\n\t\t# These are just libc implementations, not actual OSes, and thus\n\t\t# require a kernel.\n\t\techo \"Invalid configuration \\`$1': libc \\`$os' needs explicit kernel.\" 1>&2\n\t\texit 1\n\t\t;;\n\tkfreebsd*-gnu* | kopensolaris*-gnu*)\n\t\t;;\n\tvxworks-simlinux | vxworks-simwindows | vxworks-spe)\n\t\t;;\n\tnto-qnx*)\n\t\t;;\n\tos2-emx)\n\t\t;;\n\t*-eabi* | *-gnueabi*)\n\t\t;;\n\t-*)\n\t\t# Blank kernel with real OS is always fine.\n\t\t;;\n\t*-*)\n\t\techo \"Invalid configuration \\`$1': Kernel \\`$kernel' not known to work with OS \\`$os'.\" 1>&2\n\t\texit 1\n\t\t;;\nesac\n\n# Here we handle the case where we know the os, and the CPU type, but not the\n# manufacturer.  We pick the logical manufacturer.\ncase $vendor in\n\tunknown)\n\t\tcase $cpu-$os in\n\t\t\t*-riscix*)\n\t\t\t\tvendor=acorn\n\t\t\t\t;;\n\t\t\t*-sunos*)\n\t\t\t\tvendor=sun\n\t\t\t\t;;\n\t\t\t*-cnk* | *-aix*)\n\t\t\t\tvendor=ibm\n\t\t\t\t;;\n\t\t\t*-beos*)\n\t\t\t\tvendor=be\n\t\t\t\t;;\n\t\t\t*-hpux*)\n\t\t\t\tvendor=hp\n\t\t\t\t;;\n\t\t\t*-mpeix*)\n\t\t\t\tvendor=hp\n\t\t\t\t;;\n\t\t\t*-hiux*)\n\t\t\t\tvendor=hitachi\n\t\t\t\t;;\n\t\t\t*-unos*)\n\t\t\t\tvendor=crds\n\t\t\t\t;;\n\t\t\t*-dgux*)\n\t\t\t\tvendor=dg\n\t\t\t\t;;\n\t\t\t*-luna*)\n\t\t\t\tvendor=omron\n\t\t\t\t;;\n\t\t\t*-genix*)\n\t\t\t\tvendor=ns\n\t\t\t\t;;\n\t\t\t*-clix*)\n\t\t\t\tvendor=intergraph\n\t\t\t\t;;\n\t\t\t*-mvs* | *-opened*)\n\t\t\t\tvendor=ibm\n\t\t\t\t;;\n\t\t\t*-os400*)\n\t\t\t\tvendor=ibm\n\t\t\t\t;;\n\t\t\ts390-* | s390x-*)\n\t\t\t\tvendor=ibm\n\t\t\t\t;;\n\t\t\t*-ptx*)\n\t\t\t\tvendor=sequent\n\t\t\t\t;;\n\t\t\t*-tpf*)\n\t\t\t\tvendor=ibm\n\t\t\t\t;;\n\t\t\t*-vxsim* | *-vxworks* | *-windiss*)\n\t\t\t\tvendor=wrs\n\t\t\t\t;;\n\t\t\t*-aux*)\n\t\t\t\tvendor=apple\n\t\t\t\t;;\n\t\t\t*-hms*)\n\t\t\t\tvendor=hitachi\n\t\t\t\t;;\n\t\t\t*-mpw* | *-macos*)\n\t\t\t\tvendor=apple\n\t\t\t\t;;\n\t\t\t*-*mint | *-mint[0-9]* | *-*MiNT | *-MiNT[0-9]*)\n\t\t\t\tvendor=atari\n\t\t\t\t;;\n\t\t\t*-vos*)\n\t\t\t\tvendor=stratus\n\t\t\t\t;;\n\t\tesac\n\t\t;;\nesac\n\necho \"$cpu-$vendor-${kernel:+$kernel-}$os\"\nexit\n\n# Local variables:\n# eval: (add-hook 'before-save-hook 'time-stamp)\n# time-stamp-start: \"timestamp='\"\n# time-stamp-format: \"%:y-%02m-%02d\"\n# time-stamp-end: \"'\"\n# End:\n"
  },
  {
    "path": "scripts/const_structs.checkpatch",
    "content": "acpi_dock_ops\naddress_space_operations\nbacklight_ops\nblock_device_operations\nclk_ops\ncomedi_lrange\ncomponent_ops\ndentry_operations\ndev_pm_ops\ndma_map_ops\ndriver_info\ndrm_connector_funcs\ndrm_encoder_funcs\ndrm_encoder_helper_funcs\nethtool_ops\nextent_io_ops\nfile_lock_operations\nfile_operations\nhv_ops\nide_dma_ops\nide_port_ops\ninode_operations\nintel_dvo_dev_ops\nirq_domain_ops\nitem_operations\niwl_cfg\niwl_ops\nkgdb_arch\nkgdb_io\nkset_uevent_ops\nlock_manager_operations\nmachine_desc\nmicrocode_ops\nmlxsw_reg_info\nmtrr_ops\nneigh_ops\nnet_device_ops\nnlmsvc_binding\nnvkm_device_chip\nof_device_id\npci_raw_ops\nphy_ops\npinctrl_ops\npinmux_ops\npipe_buf_operations\nplatform_hibernation_ops\nplatform_suspend_ops\nproto_ops\nregmap_access_table\nregulator_ops\nrpc_pipe_ops\nrtc_class_ops\nsd_desc\nseq_operations\nsirfsoc_padmux\nsnd_ac97_build_ops\nsnd_soc_component_driver\nsoc_pcmcia_socket_ops\nstacktrace_ops\nsysfs_ops\ntty_operations\nuart_ops\nusb_mon_operations\nv4l2_ctrl_ops\nv4l2_ioctl_ops\nvm_operations_struct\nwacom_features\nwd_ops\n"
  },
  {
    "path": "scripts/deptest.sh",
    "content": "#!/usr/bin/env bash\n#\n# Automated OpenWrt package dependency checker\n#\n# Copyright (C) 2009-2010 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\nSCRIPTDIR=\"$(dirname \"$0\")\"\n[ \"${SCRIPTDIR:0:1}\" = \"/\" ] || SCRIPTDIR=\"$PWD/$SCRIPTDIR\"\nBASEDIR=\"$SCRIPTDIR/..\"\n\nDIR=\"$BASEDIR/tmp/deptest\"\nSTAMP_DIR_SUCCESS=\"$DIR/stamp-success\"\nSTAMP_DIR_FAILED=\"$DIR/stamp-failed\"\nSTAMP_DIR_BLACKLIST=\"$DIR/stamp-blacklist\"\nBUILD_DIR=\"$DIR/build_dir/target\"\nBUILD_DIR_HOST=\"$DIR/build_dir/host\"\nKERNEL_BUILD_DIR=\"$DIR/build_dir/linux\"\nSTAGING_DIR=\"$DIR/staging_dir/target\"\nSTAGING_DIR_HOST=\"$DIR/staging_dir/host\"\nSTAGING_DIR_HOST_TMPL=\"$DIR/staging_dir_host_tmpl\"\nBIN_DIR=\"$DIR/staging_dir/bin_dir\"\nLOG_DIR_NAME=\"logs\"\nLOG_DIR=\"$DIR/$LOG_DIR_NAME\"\n\ndie()\n{\n\techo \"$@\"\n\texit 1\n}\n\nusage()\n{\n\techo \"deptest.sh [OPTIONS] [PACKAGES]\"\n\techo\n\techo \"OPTIONS:\"\n\techo \"  --lean       Run a lean test. Do not clean the build directory for each\"\n\techo \"               package test.\"\n\techo \"  --force      Force a test, even if a success/blacklist stamp is available\"\n\techo \"  -j X         Number of make jobs\"\n\techo\n\techo \"PACKAGES are packages to test. If not specified, all installed packages\"\n\techo \"will be tested.\"\n}\n\ndeptest_make()\n{\n\tlocal target=\"$1\"\n\tshift\n\tlocal logfile=\"$1\"\n\tshift\n\tmake -j$nrjobs \"$target\" \\\n\t\tBUILD_DIR=\"$BUILD_DIR\" \\\n\t\tBUILD_DIR_HOST=\"$BUILD_DIR_HOST\" \\\n\t\tKERNEL_BUILD_DIR=\"$KERNEL_BUILD_DIR\" \\\n\t\tBIN_DIR=\"$BIN_DIR\" \\\n\t\tSTAGING_DIR=\"$STAGING_DIR\" \\\n\t\tSTAGING_DIR_HOST=\"$STAGING_DIR_HOST\" \\\n\t\tFORCE_HOST_INSTALL=1 \\\n\t\tV=99 \"$@\" >\"$LOG_DIR/$logfile\" 2>&1\n}\n\nclean_kernel_build_dir()\n{\n\t# delete everything, except the kernel build dir \"linux-X.X.X\"\n\t(\n\t\tcd \"$KERNEL_BUILD_DIR\" || die \"Failed to enter kernel build dir\"\n\t\tfor entry in *; do\n\t\t\t[ -z \"$(echo \"$entry\" | egrep -e '^linux-*.*.*$')\" ] || continue\n\t\t\trm -rf \"$entry\" || die \"Failed to clean kernel build dir\"\n\t\tdone\n\t)\n}\n\nstamp_exists() # $1=stamp\n{\n\t[ -e \"$1\" -o -L \"$1\" ]\n}\n\ntest_package() # $1=pkgname\n{\n\tlocal pkg=\"$1\"\n\t[ -n \"$pkg\" -a -z \"$(echo \"$pkg\" | grep -e '/')\" -a \"$pkg\" != \".\" -a \"$pkg\" != \"..\" ] || \\\n\t\tdie \"Package name \\\"$pkg\\\" contains illegal characters\"\n\tlocal SELECTED=\n\tfor conf in `grep CONFIG_PACKAGE tmp/.packagedeps | grep -E \"[ /]$pkg\\$\" | sed -e 's,package-$(\\(CONFIG_PACKAGE_.*\\)).*,\\1,'`; do\n\t\tgrep \"$conf=\" .config > /dev/null && SELECTED=1 && break\n\tdone\n\tlocal STAMP_SUCCESS=\"$STAMP_DIR_SUCCESS/$pkg\"\n\tlocal STAMP_FAILED=\"$STAMP_DIR_FAILED/$pkg\"\n\tlocal STAMP_BLACKLIST=\"$STAMP_DIR_BLACKLIST/$pkg\"\n\trm -f \"$STAMP_FAILED\"\n\tstamp_exists \"$STAMP_SUCCESS\" && [ $force -eq 0 ] && return\n\trm -f \"$STAMP_SUCCESS\"\n\t[ -n \"$SELECTED\" ] || {\n\t\techo \"Package $pkg is not selected\"\n\t\treturn\n\t}\n\tstamp_exists \"$STAMP_BLACKLIST\" && [ $force -eq 0 ] && {\n\t\techo \"Package $pkg is blacklisted\"\n\t\treturn\n\t}\n\techo \"Testing package $pkg...\"\n\trm -rf \"$STAGING_DIR\" \"$STAGING_DIR_HOST\"\n\tmkdir -p \"$STAGING_DIR\"\n\tcp -al \"$STAGING_DIR_HOST_TMPL\" \"$STAGING_DIR_HOST\"\n\t[ $lean_test -eq 0 ] && {\n\t\trm -rf \"$BUILD_DIR\" \"$BUILD_DIR_HOST\"\n\t\tclean_kernel_build_dir\n\t}\n\tmkdir -p \"$BUILD_DIR\" \"$BUILD_DIR_HOST\"\n\tlocal logfile=\"$(basename $pkg).log\"\n\tdeptest_make \"package/$pkg/compile\" \"$logfile\"\n\tif [ $? -eq 0 ]; then\n\t\t( cd \"$STAMP_DIR_SUCCESS\"; ln -s \"../$LOG_DIR_NAME/$logfile\" \"./$pkg\" )\n\telse\n\t\t( cd \"$STAMP_DIR_FAILED\"; ln -s \"../$LOG_DIR_NAME/$logfile\" \"./$pkg\" )\n\t\techo \"Building package $pkg FAILED\"\n\tfi\n}\n\n# parse commandline options\npackages=\nlean_test=0\nforce=0\nnrjobs=1\nwhile [ $# -ne 0 ]; do\n\tcase \"$1\" in\n\t--help|-h)\n\t\tusage\n\t\texit 0\n\t\t;;\n\t--lean)\n\t\tlean_test=1\n\t\t;;\n\t--force)\n\t\tforce=1\n\t\t;;\n\t-j*)\n\t\tif [ -n \"${1:2}\" ]; then\n\t\t\tnrjobs=\"${1:2}\"\n\t\telse\n\t\t\tshift\n\t\t\tnrjobs=\"$1\"\n\t\tfi\n\t\t;;\n\t*)\n\t\tpackages=\"$packages $1\"\n\t\t;;\n\tesac\n\tshift\ndone\n\n[ -f \"$BASEDIR/include/toplevel.mk\" ] || \\\n\tdie \"Error: Could not find buildsystem base directory\"\n[ -f \"$BASEDIR/.config\" ] || \\\n\tdie \"The buildsystem is not configured. Please run make menuconfig.\"\ncd \"$BASEDIR\" || die \"Failed to enter base directory\"\n\nmkdir -p \"$STAMP_DIR_SUCCESS\" \"$STAMP_DIR_FAILED\" \"$STAMP_DIR_BLACKLIST\" \\\n\t\"$BIN_DIR\" \"$LOG_DIR\"\n\nbootstrap_deptest_make()\n{\n\tlocal target=\"$1\"\n\tshift\n\tlocal logfile=\"bootstrap-deptest-$(echo \"$target\" | tr / -).log\"\n\techo \"deptest-make $target\"\n\tdeptest_make \"$target\" \"$logfile\" \"$@\" || \\\n\t\tdie \"make $target failed, please check $logfile\"\n}\n\nbootstrap_native_make()\n{\n\tlocal target=\"$1\"\n\tshift\n\tlocal logfile=\"bootstrap-native-$(echo \"$target\" | tr / -).log\"\n\techo \"make $target\"\n\tmake -j$nrjobs \"$target\" \\\n\t\tV=99 \"$@\" >\"$LOG_DIR/$logfile\" 2>&1 || \\\n\t\tdie \"make $target failed, please check $logfile\"\n}\n\n[ -d \"$STAGING_DIR_HOST_TMPL\" ] || {\n\techo \"Bootstrapping build environment...\"\n\trm -rf \"$STAGING_DIR\" \"$STAGING_DIR_HOST\" \"$BUILD_DIR\" \"$BUILD_DIR_HOST\" \"$KERNEL_BUILD_DIR\"\n\tmkdir -p \"$STAGING_DIR\" \"$STAGING_DIR_HOST\" \\\n\t\t\"$BUILD_DIR\" \"$BUILD_DIR_HOST\" \"$KERNEL_BUILD_DIR\"\n\tbootstrap_native_make tools/install\n\tbootstrap_native_make toolchain/install\n\tbootstrap_deptest_make tools/install\n\tbootstrap_deptest_make target/linux/install\n\tcp -al \"$STAGING_DIR_HOST\" \"$STAGING_DIR_HOST_TMPL\"\n\trm -rf \"$STAGING_DIR\" \"$STAGING_DIR_HOST\" \"$BUILD_DIR\" \"$BUILD_DIR_HOST\"\n\techo \"Build environment OK.\"\n}\n\nif [ -z \"$packages\" ]; then\n\t# iterate over all packages\n\tfor pkg in `cat tmp/.packagedeps  | grep CONFIG_PACKAGE | grep -v curdir | sed -e 's,.*[/=]\\s*,,' | sort -u`; do\n\t\ttest_package \"$pkg\"\n\tdone\nelse\n\t# only check the specified packages\n\tfor pkg in $packages; do\n\t\ttest_package \"$pkg\"\n\tdone\nfi\n"
  },
  {
    "path": "scripts/diffconfig.sh",
    "content": "#!/bin/sh\nmake ./scripts/config/conf >/dev/null || { make ./scripts/config/conf; exit 1; }\ngrep \\^CONFIG_TARGET_ .config | head -n3 > tmp/.diffconfig.head\ngrep \\^CONFIG_TARGET_DEVICE_ .config >> tmp/.diffconfig.head\ngrep '^CONFIG_ALL=y' .config >> tmp/.diffconfig.head\ngrep '^CONFIG_ALL_KMODS=y' .config >> tmp/.diffconfig.head\ngrep '^CONFIG_ALL_NONSHARED=y' .config >> tmp/.diffconfig.head\ngrep '^CONFIG_DEVEL=y' .config >> tmp/.diffconfig.head\ngrep '^CONFIG_TOOLCHAINOPTS=y' .config >> tmp/.diffconfig.head\ngrep '^CONFIG_BUSYBOX_CUSTOM=y' .config >> tmp/.diffconfig.head\ngrep '^CONFIG_TARGET_PER_DEVICE_ROOTFS=y' .config >> tmp/.diffconfig.head\n./scripts/config/conf --defconfig=tmp/.diffconfig.head -w tmp/.diffconfig.stage1 Config.in >/dev/null\n./scripts/kconfig.pl '>+' tmp/.diffconfig.stage1 .config >> tmp/.diffconfig.head\n./scripts/config/conf --defconfig=tmp/.diffconfig.head -w tmp/.diffconfig.stage2 Config.in >/dev/null\n./scripts/kconfig.pl '>' tmp/.diffconfig.stage2 .config >> tmp/.diffconfig.head\ncat tmp/.diffconfig.head\nrm -f tmp/.diffconfig tmp/.diffconfig.head\n"
  },
  {
    "path": "scripts/dl_cleanup.py",
    "content": "#!/usr/bin/env python3\n\"\"\"\n# OpenWrt download directory cleanup utility.\n# Delete all but the very last version of the program tarballs.\n#\n# Copyright (C) 2010-2015 Michael Buesch <m@bues.ch>\n# Copyright (C) 2013-2015 OpenWrt.org\n\"\"\"\n\nfrom __future__ import print_function\n\nimport sys\nimport os\nimport re\nimport getopt\n\n# Commandline options\nopt_dryrun = False\n\n\ndef parseVer_1234(match, filepath):\n    progname = match.group(1)\n    progversion = (\n        (int(match.group(2)) << 64)\n        | (int(match.group(3)) << 48)\n        | (int(match.group(4)) << 32)\n        | (int(match.group(5)) << 16)\n    )\n    return (progname, progversion)\n\n\ndef parseVer_123(match, filepath):\n    progname = match.group(1)\n    try:\n        patchlevel = match.group(5)\n    except IndexError as e:\n        patchlevel = None\n    if patchlevel:\n        patchlevel = ord(patchlevel[0])\n    else:\n        patchlevel = 0\n    progversion = (\n        (int(match.group(2)) << 64)\n        | (int(match.group(3)) << 48)\n        | (int(match.group(4)) << 32)\n        | patchlevel\n    )\n    return (progname, progversion)\n\n\ndef parseVer_12(match, filepath):\n    progname = match.group(1)\n    try:\n        patchlevel = match.group(4)\n    except IndexError as e:\n        patchlevel = None\n    if patchlevel:\n        patchlevel = ord(patchlevel[0])\n    else:\n        patchlevel = 0\n    progversion = (int(match.group(2)) << 64) | (int(match.group(3)) << 48) | patchlevel\n    return (progname, progversion)\n\n\ndef parseVer_r(match, filepath):\n    progname = match.group(1)\n    progversion = int(match.group(2)) << 64\n    return (progname, progversion)\n\n\ndef parseVer_ymd_GIT_SHASUM(match, filepath):\n    progname = match.group(1)\n    progversion = (\n        (int(match.group(2)) << 64)\n        | (int(match.group(3)) << 48)\n        | (int(match.group(4)) << 32)\n    )\n    return (progname, progversion)\n\n\ndef parseVer_ymd(match, filepath):\n    progname = match.group(1)\n    progversion = (\n        (int(match.group(2)) << 64)\n        | (int(match.group(3)) << 48)\n        | (int(match.group(4)) << 32)\n    )\n    return (progname, progversion)\n\n\ndef parseVer_GIT(match, filepath):\n    progname = match.group(1)\n    st = os.stat(filepath)\n    progversion = int(st.st_mtime) << 64\n    return (progname, progversion)\n\n\nextensions = (\n    \".tar.gz\",\n    \".tar.bz2\",\n    \".tar.xz\",\n    \".orig.tar.gz\",\n    \".orig.tar.bz2\",\n    \".orig.tar.xz\",\n    \".zip\",\n    \".tgz\",\n    \".tbz\",\n    \".txz\",\n)\n\nversionRegex = (\n    (re.compile(r\"(gcc[-_]\\d+)\\.(\\d+)\\.(\\d+)\"), parseVer_12),  # gcc.1.2\n    (re.compile(r\"(linux[-_]\\d+\\.\\d+)\\.(\\d+)\"), parseVer_r),  # linux.1\n    (re.compile(r\"(.+)[-_](\\d+)\\.(\\d+)\\.(\\d+)\\.(\\d+)\"), parseVer_1234),  # xxx-1.2.3.4\n    (\n        re.compile(r\"(.+)[-_](\\d\\d\\d\\d)-?(\\d\\d)-?(\\d\\d)-\"),\n        parseVer_ymd_GIT_SHASUM,\n    ),  # xxx-YYYY-MM-DD-GIT_SHASUM\n    (re.compile(r\"(.+)[-_](\\d\\d\\d\\d)-?(\\d\\d)-?(\\d\\d)\"), parseVer_ymd),  # xxx-YYYY-MM-DD\n    (re.compile(r\"(.+)[-_]([0-9a-fA-F]{40,40})\"), parseVer_GIT),  # xxx-GIT_SHASUM\n    (re.compile(r\"(.+)[-_](\\d+)\\.(\\d+)\\.(\\d+)(\\w?)\"), parseVer_123),  # xxx-1.2.3a\n    (re.compile(r\"(.+)[-_](\\d+)_(\\d+)_(\\d+)\"), parseVer_123),  # xxx-1_2_3\n    (re.compile(r\"(.+)[-_](\\d+)\\.(\\d+)(\\w?)\"), parseVer_12),  # xxx-1.2a\n    (re.compile(r\"(.+)[-_]r?(\\d+)\"), parseVer_r),  # xxx-r1111\n)\n\nblacklist = [\n    (\"wl_apsta\", re.compile(r\"wl_apsta.*\")),\n    (\".fw\", re.compile(r\".*\\.fw\")),\n    (\".arm\", re.compile(r\".*\\.arm\")),\n    (\".bin\", re.compile(r\".*\\.bin\")),\n    (\"rt-firmware\", re.compile(r\"RT[\\d\\w]+_Firmware.*\")),\n]\n\n\nclass EntryParseError(Exception):\n    pass\n\n\nclass Entry:\n    def __init__(self, directory, filename):\n        self.directory = directory\n        self.filename = filename\n        self.progname = \"\"\n        self.fileext = \"\"\n\n        for ext in extensions:\n            if filename.endswith(ext):\n                filename = filename[0 : 0 - len(ext)]\n                self.fileext = ext\n                break\n        else:\n            print(self.filename, \"has an unknown file-extension\")\n            raise EntryParseError(\"ext\")\n        for (regex, parseVersion) in versionRegex:\n            match = regex.match(filename)\n            if match:\n                (self.progname, self.version) = parseVersion(\n                    match, directory + \"/\" + filename + self.fileext\n                )\n                break\n        else:\n            print(self.filename, \"has an unknown version pattern\")\n            raise EntryParseError(\"ver\")\n\n    def getPath(self):\n        return (self.directory + \"/\" + self.filename).replace(\"//\", \"/\")\n\n    def deleteFile(self):\n        path = self.getPath()\n        print(\"Deleting\", path)\n        if not opt_dryrun:\n            os.unlink(path)\n\n    def __ge__(self, y):\n        return self.version >= y.version\n\n\ndef usage():\n    print(\"OpenWrt download directory cleanup utility\")\n    print(\"Usage: \" + sys.argv[0] + \" [OPTIONS] <path/to/dl>\")\n    print(\"\")\n    print(\" -d|--dry-run            Do a dry-run. Don't delete any files\")\n    print(\" -B|--show-blacklist     Show the blacklist and exit\")\n    print(\" -w|--whitelist ITEM     Remove ITEM from blacklist\")\n\n\ndef main(argv):\n    global opt_dryrun\n\n    try:\n        (opts, args) = getopt.getopt(\n            argv[1:],\n            \"hdBw:\",\n            [\n                \"help\",\n                \"dry-run\",\n                \"show-blacklist\",\n                \"whitelist=\",\n            ],\n        )\n        if len(args) != 1:\n            usage()\n            return 1\n    except getopt.GetoptError as e:\n        usage()\n        return 1\n    directory = args[0]\n\n    if not os.path.exists(directory):\n        print(\"Can't find dl path\", directory)\n        return 1\n\n    for (o, v) in opts:\n        if o in (\"-h\", \"--help\"):\n            usage()\n            return 0\n        if o in (\"-d\", \"--dry-run\"):\n            opt_dryrun = True\n        if o in (\"-w\", \"--whitelist\"):\n            for i in range(0, len(blacklist)):\n                (name, regex) = blacklist[i]\n                if name == v:\n                    del blacklist[i]\n                    break\n            else:\n                print(\"Whitelist error: Item\", v, \"is not in blacklist\")\n                return 1\n        if o in (\"-B\", \"--show-blacklist\"):\n            for (name, regex) in blacklist:\n                sep = \"\\t\\t\"\n                if len(name) >= 8:\n                    sep = \"\\t\"\n                print(\"%s%s(%s)\" % (name, sep, regex.pattern))\n            return 0\n\n    # Create a directory listing and parse the file names.\n    entries = []\n    for filename in os.listdir(directory):\n        if filename == \".\" or filename == \"..\":\n            continue\n        for (name, regex) in blacklist:\n            if regex.match(filename):\n                if opt_dryrun:\n                    print(filename, \"is blacklisted\")\n                break\n        else:\n            try:\n                entries.append(Entry(directory, filename))\n            except EntryParseError as e:\n                pass\n\n    # Create a map of programs\n    progmap = {}\n    for entry in entries:\n        if entry.progname in progmap.keys():\n            progmap[entry.progname].append(entry)\n        else:\n            progmap[entry.progname] = [\n                entry,\n            ]\n\n    # Traverse the program map and delete everything but the last version\n    for prog in progmap:\n        lastVersion = None\n        versions = progmap[prog]\n        for version in versions:\n            if lastVersion is None or version >= lastVersion:\n                lastVersion = version\n        if lastVersion:\n            for version in versions:\n                if version is not lastVersion:\n                    version.deleteFile()\n            if opt_dryrun:\n                print(\"Keeping\", lastVersion.getPath())\n\n    return 0\n\n\nif __name__ == \"__main__\":\n    sys.exit(main(sys.argv))\n"
  },
  {
    "path": "scripts/dl_github_archive.py",
    "content": "#!/usr/bin/env python3\n#\n# Copyright (c) 2018 Yousong Zhou <yszhou4tech@gmail.com>\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n\nimport argparse\nimport calendar\nimport datetime\nimport errno\nimport fcntl\nimport hashlib\nimport json\nimport os\nimport os.path\nimport re\nimport shutil\nimport ssl\nimport subprocess\nimport sys\nimport time\nimport urllib.request\n\nTMPDIR = os.environ.get('TMP_DIR') or '/tmp'\nTMPDIR_DL = os.path.join(TMPDIR, 'dl')\n\n\nclass PathException(Exception): pass\nclass DownloadGitHubError(Exception): pass\n\n\nclass Path(object):\n    \"\"\"Context class for preparing and cleaning up directories.\n\n    If ```preclean` is ``False``, ``path`` will NOT be removed on context enter\n\n    If ``path`` ``isdir``, then it will be created on context enter.\n\n    If ``keep`` is True, then ``path`` will NOT be removed on context exit\n    \"\"\"\n\n    def __init__(self, path, isdir=True, preclean=False, keep=False):\n        self.path = path\n        self.isdir = isdir\n        self.preclean = preclean\n        self.keep = keep\n\n    def __enter__(self):\n        if self.preclean:\n            self.rm_all(self.path)\n        if self.isdir:\n            self.mkdir_all(self.path)\n        return self\n\n    def __exit__(self, exc_type, exc_value, traceback):\n        if not self.keep:\n            self.rm_all(self.path)\n\n    @staticmethod\n    def mkdir_all(path):\n        \"\"\"Same as mkdir -p.\"\"\"\n        names = os.path.split(path)\n        p = ''\n        for name in names:\n            p = os.path.join(p, name)\n            Path._mkdir(p)\n\n    @staticmethod\n    def _rmdir_dir(dir_):\n        names = Path._listdir(dir_)\n        for name in names:\n            p = os.path.join(dir_, name)\n            Path.rm_all(p)\n        Path._rmdir(dir_)\n\n    @staticmethod\n    def _mkdir(path):\n        Path._os_func(os.mkdir, path, errno.EEXIST)\n\n    @staticmethod\n    def _rmdir(path):\n        Path._os_func(os.rmdir, path, errno.ENOENT)\n\n    @staticmethod\n    def _remove(path):\n        Path._os_func(os.remove, path, errno.ENOENT)\n\n    @staticmethod\n    def _listdir(path):\n        return Path._os_func(os.listdir, path, errno.ENOENT, default=[])\n\n    @staticmethod\n    def _os_func(func, path, errno, default=None):\n        \"\"\"Call func(path) in an idempotent way.\n\n        On exception ``ex``, if the type is OSError and ``ex.errno == errno``,\n        return ``default``, otherwise, re-raise\n        \"\"\"\n        try:\n            return func(path)\n        except OSError as e:\n            if e.errno == errno:\n                return default\n            else:\n                raise\n\n    @staticmethod\n    def rm_all(path):\n        \"\"\"Same as rm -r.\"\"\"\n        if os.path.islink(path):\n            Path._remove(path)\n        elif os.path.isdir(path):\n            Path._rmdir_dir(path)\n        else:\n            Path._remove(path)\n\n    @staticmethod\n    def untar(path, into=None):\n        \"\"\"Extract tarball at ``path`` into subdir ``into``.\n\n        return subdir name if and only if there exists one, otherwise raise PathException\n        \"\"\"\n        args = ('tar', '-C', into, '-xzf', path, '--no-same-permissions')\n        subprocess.check_call(args, preexec_fn=lambda: os.umask(0o22))\n        dirs = os.listdir(into)\n        if len(dirs) == 1:\n            return dirs[0]\n        else:\n            raise PathException('untar %s: expecting a single subdir, got %s' % (path, dirs))\n\n    @staticmethod\n    def tar(path, subdir, into=None, ts=None):\n        \"\"\"Pack ``path`` into tarball ``into``.\"\"\"\n        # --sort=name requires a recent build of GNU tar\n        args = ['tar', '--numeric-owner', '--owner=0', '--group=0', '--sort=name']\n        args += ['-C', path, '-cf', into, subdir]\n        envs = os.environ.copy()\n        if ts is not None:\n            args.append('--mtime=@%d' % ts)\n        if into.endswith('.xz'):\n            envs['XZ_OPT'] = '-7e'\n            args.append('-J')\n        elif into.endswith('.bz2'):\n            args.append('-j')\n        elif into.endswith('.gz'):\n            args.append('-z')\n            envs['GZIP'] = '-n'\n        else:\n            raise PathException('unknown compression type %s' % into)\n        subprocess.check_call(args, env=envs)\n\n\nclass GitHubCommitTsCache(object):\n    __cachef = 'github.commit.ts.cache'\n    __cachen = 2048\n\n    def __init__(self):\n        Path.mkdir_all(TMPDIR_DL)\n        self.cachef = os.path.join(TMPDIR_DL, self.__cachef)\n        self.cache = {}\n\n    def get(self, k):\n        \"\"\"Get timestamp with key ``k``.\"\"\"\n        fileno = os.open(self.cachef, os.O_RDONLY | os.O_CREAT)\n        with os.fdopen(fileno) as fin:\n            try:\n                fcntl.lockf(fileno, fcntl.LOCK_SH)\n                self._cache_init(fin)\n                if k in self.cache:\n                    ts = self.cache[k][0]\n                    return ts\n            finally:\n                fcntl.lockf(fileno, fcntl.LOCK_UN)\n        return None\n\n    def set(self, k, v):\n        \"\"\"Update timestamp with ``k``.\"\"\"\n        fileno = os.open(self.cachef, os.O_RDWR | os.O_CREAT)\n        with os.fdopen(fileno, 'w+') as f:\n            try:\n                fcntl.lockf(fileno, fcntl.LOCK_EX)\n                self._cache_init(f)\n                self.cache[k] = (v, int(time.time()))\n                self._cache_flush(f)\n            finally:\n                fcntl.lockf(fileno, fcntl.LOCK_UN)\n\n    def _cache_init(self, fin):\n        for line in fin:\n            k, ts, updated = line.split()\n            ts = int(ts)\n            updated = int(updated)\n            self.cache[k] = (ts, updated)\n\n    def _cache_flush(self, fout):\n        cache = sorted(self.cache.items(), key=lambda a: a[1][1])\n        cache = cache[:self.__cachen]\n        self.cache = {}\n        os.ftruncate(fout.fileno(), 0)\n        fout.seek(0, os.SEEK_SET)\n        for k, ent in cache:\n            ts = ent[0]\n            updated = ent[1]\n            line = '{0} {1} {2}\\n'.format(k, ts, updated)\n            fout.write(line)\n\n\nclass DownloadGitHubTarball(object):\n    \"\"\"Download and repack archive tarball from GitHub.\n\n    Compared with the method of packing after cloning the whole repo, this\n    method is more friendly to users with fragile internet connection.\n\n    However, there are limitations with this method\n\n     - GitHub imposes a 60 reqs/hour limit for unauthenticated API access.\n       This affects fetching commit date for reproducible tarballs.  Download\n       through the archive link is not affected.\n\n     - GitHub archives do not contain source codes for submodules.\n\n     - GitHub archives seem to respect .gitattributes and ignore paths with\n       export-ignore attributes.\n\n    For the first two issues, the method will fail loudly to allow fallback to\n    clone-then-pack method.\n\n    As for the 3rd issue, to make sure that this method only produces identical\n    tarballs as the fallback method, we require the expected hash value to be\n    supplied.  That means the first tarball will need to be prepared by the\n    clone-then-pack method\n    \"\"\"\n\n    __repo_url_regex = re.compile(r'^(?:https|git)://github.com/(?P<owner>[^/]+)/(?P<repo>[^/]+)')\n\n    def __init__(self, args):\n        self.dl_dir = args.dl_dir\n        self.version = args.version\n        self.subdir = args.subdir\n        self.source = args.source\n        self.url = args.url\n        self._init_owner_repo()\n        self.xhash = args.hash\n        self._init_hasher()\n        self.commit_ts = None           # lazy load commit timestamp\n        self.commit_ts_cache = GitHubCommitTsCache()\n        self.name = 'github-tarball'\n\n    def download(self):\n        \"\"\"Download and repack GitHub archive tarball.\"\"\"\n        self._init_commit_ts()\n        with Path(TMPDIR_DL, keep=True) as dir_dl:\n            # fetch tarball from GitHub\n            tarball_path = os.path.join(dir_dl.path, self.subdir + '.tar.gz.dl')\n            with Path(tarball_path, isdir=False):\n                self._fetch(tarball_path)\n                # unpack\n                d = os.path.join(dir_dl.path, self.subdir + '.untar')\n                with Path(d, preclean=True) as dir_untar:\n                    tarball_prefix = Path.untar(tarball_path, into=dir_untar.path)\n                    dir0 = os.path.join(dir_untar.path, tarball_prefix)\n                    dir1 = os.path.join(dir_untar.path, self.subdir)\n                    # submodules check\n                    if self._has_submodule(dir0):\n                        raise self._error('Fetching submodules is not yet supported')\n                    # rename subdir\n                    os.rename(dir0, dir1)\n                    # repack\n                    into=os.path.join(TMPDIR_DL, self.source)\n                    Path.tar(dir_untar.path, self.subdir, into=into, ts=self.commit_ts)\n                    try:\n                        self._hash_check(into)\n                    except Exception:\n                        Path.rm_all(into)\n                        raise\n                    # move to target location\n                    file1 = os.path.join(self.dl_dir, self.source)\n                    if into != file1:\n                        shutil.move(into, file1)\n\n    def _has_submodule(self, dir_):\n        m = os.path.join(dir_, '.gitmodules')\n        try:\n            st = os.stat(m)\n            return st.st_size > 0\n        except OSError as e:\n            return e.errno != errno.ENOENT\n\n    def _init_owner_repo(self):\n        m = self.__repo_url_regex.search(self.url)\n        if m is None:\n            raise self._error('Invalid github url: {}'.format(self.url))\n        owner = m.group('owner')\n        repo = m.group('repo')\n        if repo.endswith('.git'):\n            repo = repo[:-4]\n        self.owner = owner\n        self.repo = repo\n\n    def _init_hasher(self):\n        xhash = self.xhash\n        if len(xhash) == 64:\n            self.hasher = hashlib.sha256()\n        elif len(xhash) == 32:\n            self.hasher = hashlib.md5()\n        else:\n            raise self._error('Requires sha256sum for verification')\n        self.xhash = xhash\n\n    def _hash_check(self, f):\n        with open(f, 'rb') as fin:\n            while True:\n                d = fin.read(4096)\n                if not d:\n                    break\n                self.hasher.update(d)\n        xhash = self.hasher.hexdigest()\n        if xhash != self.xhash:\n            raise self._error('Wrong hash (probably caused by .gitattributes), expecting {}, got {}'.format(self.xhash, xhash))\n\n    def _init_commit_ts(self):\n        if self.commit_ts is not None:\n            return\n        # GitHub provides 2 APIs[1,2] for fetching commit data.  API[1] is more\n        # terse while API[2] provides more verbose info such as commit diff\n        # etc.  That's the main reason why API[1] is preferred: the response\n        # size is predictable.\n        #\n        # However, API[1] only accepts complete commit sha1sum as the parameter\n        # while API[2] is more liberal accepting also partial commit id and\n        # tags, etc.\n        #\n        # [1] Get a single commit, Repositories, https://developer.github.com/v3/repos/commits/#get-a-single-commit\n        # [2] Git Commits, Git Data, https://developer.github.com/v3/git/commits/#get-a-commit\n        apis = [\n            {\n                'url': self._make_repo_url_path('git', 'commits', self.version),\n                'attr_path': ('committer', 'date'),\n            }, {\n                'url': self._make_repo_url_path('commits', self.version),\n                'attr_path': ('commit', 'committer', 'date'),\n            },\n        ]\n        version_is_sha1sum = len(self.version) == 40\n        if not version_is_sha1sum:\n            apis.insert(0, apis.pop())\n        reasons = ''\n        for api in apis:\n            url = api['url']\n            attr_path = api['attr_path']\n            try:\n                ct = self.commit_ts_cache.get(url)\n                if ct is not None:\n                    self.commit_ts = ct\n                    return\n                ct = self._init_commit_ts_remote_get(url, attr_path)\n                self.commit_ts = ct\n                self.commit_ts_cache.set(url, ct)\n                return\n            except Exception as e:\n                reasons += '\\n' + (\"  {}: {}\".format(url, e))\n        raise self._error('Cannot fetch commit ts:{}'.format(reasons))\n\n    def _init_commit_ts_remote_get(self, url, attrpath):\n        resp = self._make_request(url)\n        data = resp.read()\n        date = json.loads(data)\n        for attr in attrpath:\n            date = date[attr]\n        date = datetime.datetime.strptime(date, '%Y-%m-%dT%H:%M:%SZ')\n        date = date.timetuple()\n        ct = calendar.timegm(date)\n        return ct\n\n    def _fetch(self, path):\n        \"\"\"Fetch tarball of the specified version ref.\"\"\"\n        ref = self.version\n        url = self._make_repo_url_path('tarball', ref)\n        resp = self._make_request(url)\n        with open(path, 'wb') as fout:\n            while True:\n                d = resp.read(4096)\n                if not d:\n                    break\n                fout.write(d)\n\n    def _make_repo_url_path(self, *args):\n        url = '/repos/{0}/{1}'.format(self.owner, self.repo)\n        if args:\n            url += '/' + '/'.join(args)\n        return url\n\n    def _make_request(self, path):\n        \"\"\"Request GitHub API endpoint on ``path``.\"\"\"\n        url = 'https://api.github.com' + path\n        headers = {\n            'Accept': 'application/vnd.github.v3+json',\n            'User-Agent': 'OpenWrt',\n        }\n        req = urllib.request.Request(url, headers=headers)\n        sslcontext = ssl._create_unverified_context()\n        fileobj = urllib.request.urlopen(req, context=sslcontext)\n        return fileobj\n\n    def _error(self, msg):\n        return DownloadGitHubError('{}: {}'.format(self.source, msg))\n\n\ndef main():\n    parser = argparse.ArgumentParser()\n    parser.add_argument('--dl-dir', default=os.getcwd(), help='Download dir')\n    parser.add_argument('--url', help='Download URL')\n    parser.add_argument('--subdir', help='Source code subdir name')\n    parser.add_argument('--version', help='Source code version')\n    parser.add_argument('--source', help='Source tarball filename')\n    parser.add_argument('--hash', help='Source tarball\\'s expected sha256sum')\n    args = parser.parse_args()\n    try:\n        method = DownloadGitHubTarball(args)\n        method.download()\n    except Exception as ex:\n        sys.stderr.write('{}: Download from {} failed\\n'.format(args.source, args.url))\n        sys.stderr.write('{}\\n'.format(ex))\n        sys.exit(1)\n\nif __name__ == '__main__':\n    main()\n"
  },
  {
    "path": "scripts/download.pl",
    "content": "#!/usr/bin/env perl\n# \n# Copyright (C) 2006 OpenWrt.org\n# Copyright (C) 2016 LEDE project\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\nuse strict;\nuse warnings;\nuse File::Basename;\nuse File::Copy;\nuse Text::ParseWords;\n\n@ARGV > 2 or die \"Syntax: $0 <target dir> <filename> <hash> <url filename> [<mirror> ...]\\n\";\n\nmy $url_filename;\nmy $target = glob(shift @ARGV);\nmy $filename = shift @ARGV;\nmy $file_hash = shift @ARGV;\n$url_filename = shift @ARGV unless $ARGV[0] =~ /:\\/\\//;\nmy $scriptdir = dirname($0);\nmy @mirrors;\nmy $ok;\n\n$url_filename or $url_filename = $filename;\n\nsub localmirrors {\n\tmy @mlist;\n\topen LM, \"$scriptdir/localmirrors\" and do {\n\t    while (<LM>) {\n\t\t\tchomp $_;\n\t\t\tpush @mlist, $_ if $_;\n\t\t}\n\t\tclose LM;\n\t};\n\topen CONFIG, \"<\".$ENV{'TOPDIR'}.\"/.config\" and do {\n\t\twhile (<CONFIG>) {\n\t\t\t/^CONFIG_LOCALMIRROR=\"(.+)\"/ and do {\n\t\t\t\tchomp;\n\t\t\t\tmy @local_mirrors = split(/;/, $1);\n\t\t\t\tpush @mlist, @local_mirrors;\n\t\t\t};\n\t\t}\n\t\tclose CONFIG;\n\t};\n\n\tmy $mirror = $ENV{'DOWNLOAD_MIRROR'};\n\t$mirror and push @mlist, split(/;/, $mirror);\n\n\treturn @mlist;\n}\n\nsub which($) {\n\tmy $prog = shift;\n\tmy $res = `command -v $prog`;\n\t$res or return undef;\n\treturn $res;\n}\n\nsub hash_cmd() {\n\tmy $len = length($file_hash);\n\tmy $cmd;\n\n\t$len == 64 and return \"$ENV{'MKHASH'} sha256\";\n\t$len == 32 and return \"$ENV{'MKHASH'} md5\";\n\treturn undef;\n}\n\nsub download_cmd($) {\n\tmy $url = shift;\n\tmy $have_curl = 0;\n\n\tif (open CURL, '-|', 'curl', '--version') {\n\t\tif (defined(my $line = readline CURL)) {\n\t\t\t$have_curl = 1 if $line =~ /^curl /;\n\t\t}\n\t\tclose CURL;\n\t}\n\n\treturn $have_curl\n\t\t? (qw(curl -f --connect-timeout 20 --retry 5 --location --insecure), shellwords($ENV{CURL_OPTIONS} || ''), $url)\n\t\t: (qw(wget --tries=5 --timeout=20 --no-check-certificate --output-document=-), shellwords($ENV{WGET_OPTIONS} || ''), $url)\n\t;\n}\n\nmy $hash_cmd = hash_cmd();\n$hash_cmd or ($file_hash eq \"skip\") or die \"Cannot find appropriate hash command, ensure the provided hash is either a MD5 or SHA256 checksum.\\n\";\n\nsub download\n{\n\tmy $mirror = shift;\n\tmy $download_filename = shift;\n\n\t$mirror =~ s!/$!!;\n\n\tif ($mirror =~ s!^file://!!) {\n\t\tif (! -d \"$mirror\") {\n\t\t\tprint STDERR \"Wrong local cache directory -$mirror-.\\n\";\n\t\t\tcleanup();\n\t\t\treturn;\n\t\t}\n\n\t\tif (! -d \"$target\") {\n\t\t\tsystem(\"mkdir\", \"-p\", \"$target/\");\n\t\t}\n\n\t\tif (! open TMPDLS, \"find $mirror -follow -name $filename 2>/dev/null |\") {\n\t\t\tprint(\"Failed to search for $filename in $mirror\\n\");\n\t\t\treturn;\n\t\t}\n\n\t\tmy $link;\n\n\t\twhile (defined(my $line = readline TMPDLS)) {\n\t\t\tchomp ($link = $line);\n\t\t\tif ($. > 1) {\n\t\t\t\tprint(\"$. or more instances of $filename in $mirror found . Only one instance allowed.\\n\");\n\t\t\t\treturn;\n\t\t\t}\n\t\t}\n\n\t\tclose TMPDLS;\n\n\t\tif (! $link) {\n\t\t\tprint(\"No instances of $filename found in $mirror.\\n\");\n\t\t\treturn;\n\t\t}\n\n\t\tprint(\"Copying $filename from $link\\n\");\n\t\tcopy($link, \"$target/$filename.dl\");\n\n\t\t$hash_cmd and do {\n\t\t\tif (system(\"cat '$target/$filename.dl' | $hash_cmd > '$target/$filename.hash'\")) {\n\t\t\t\tprint(\"Failed to generate hash for $filename\\n\");\n\t\t\t\treturn;\n\t\t\t}\n\t\t};\n\t} else {\n\t\tmy @cmd = download_cmd(\"$mirror/$download_filename\");\n\t\tprint STDERR \"+ \".join(\" \",@cmd).\"\\n\";\n\t\topen(FETCH_FD, '-|', @cmd) or die \"Cannot launch curl or wget.\\n\";\n\t\t$hash_cmd and do {\n\t\t\topen MD5SUM, \"| $hash_cmd > '$target/$filename.hash'\" or die \"Cannot launch $hash_cmd.\\n\";\n\t\t};\n\t\topen OUTPUT, \"> $target/$filename.dl\" or die \"Cannot create file $target/$filename.dl: $!\\n\";\n\t\tmy $buffer;\n\t\twhile (read FETCH_FD, $buffer, 1048576) {\n\t\t\t$hash_cmd and print MD5SUM $buffer;\n\t\t\tprint OUTPUT $buffer;\n\t\t}\n\t\t$hash_cmd and close MD5SUM;\n\t\tclose FETCH_FD;\n\t\tclose OUTPUT;\n\n\t\tif ($? >> 8) {\n\t\t\tprint STDERR \"Download failed.\\n\";\n\t\t\tcleanup();\n\t\t\treturn;\n\t\t}\n\t}\n\n\t$hash_cmd and do {\n\t\tmy $sum = `cat \"$target/$filename.hash\"`;\n\t\t$sum =~ /^(\\w+)\\s*/ or die \"Could not generate file hash\\n\";\n\t\t$sum = $1;\n\n\t\tif ($sum ne $file_hash) {\n\t\t\tprint STDERR \"Hash of the downloaded file does not match (file: $sum, requested: $file_hash) - deleting download.\\n\";\n\t\t\tcleanup();\n\t\t\treturn;\n\t\t}\n\t};\n\n\tunlink \"$target/$filename\";\n\tsystem(\"mv\", \"$target/$filename.dl\", \"$target/$filename\");\n\tcleanup();\n}\n\nsub cleanup\n{\n\tunlink \"$target/$filename.dl\";\n\tunlink \"$target/$filename.hash\";\n}\n\n@mirrors = localmirrors();\n\nforeach my $mirror (@ARGV) {\n\tif ($mirror =~ /^\\@SF\\/(.+)$/) {\n\t\t# give sourceforge a few more tries, because it redirects to different mirrors\n\t\tfor (1 .. 5) {\n\t\t\tpush @mirrors, \"https://downloads.sourceforge.net/$1\";\n\t\t}\n\t} elsif ($mirror =~ /^\\@OPENWRT$/) {\n\t\t# use OpenWrt source server directly\n\t} elsif ($mirror =~ /^\\@DEBIAN\\/(.+)$/) {\n\t\tpush @mirrors, \"https://ftp.debian.org/debian/$1\";\n\t\tpush @mirrors, \"https://mirror.leaseweb.com/debian/$1\";\n\t\tpush @mirrors, \"https://mirror.netcologne.de/debian/$1\";\n\t} elsif ($mirror =~ /^\\@APACHE\\/(.+)$/) {\n\t\tpush @mirrors, \"https://mirror.netcologne.de/apache.org/$1\";\n\t\tpush @mirrors, \"https://mirror.aarnet.edu.au/pub/apache/$1\";\n\t\tpush @mirrors, \"https://mirror.csclub.uwaterloo.ca/apache/$1\";\n\t\tpush @mirrors, \"https://archive.apache.org/dist/$1\";\n\t\tpush @mirrors, \"http://mirror.cogentco.com/pub/apache/$1\";\n\t\tpush @mirrors, \"http://mirror.navercorp.com/apache/$1\";\n\t\tpush @mirrors, \"http://ftp.jaist.ac.jp/pub/apache/$1\";\n\t\tpush @mirrors, \"ftp://apache.cs.utah.edu/apache.org/$1\";\n\t\tpush @mirrors, \"ftp://apache.mirrors.ovh.net/ftp.apache.org/dist/$1\";\n\t} elsif ($mirror =~ /^\\@GITHUB\\/(.+)$/) {\n\t\t# give github a few more tries (different mirrors)\n\t\tfor (1 .. 5) {\n\t\t\tpush @mirrors, \"https://raw.githubusercontent.com/$1\";\n\t\t}\n\t} elsif ($mirror =~ /^\\@GNU\\/(.+)$/) {\n\t\tpush @mirrors, \"https://mirror.csclub.uwaterloo.ca/gnu/$1\";\n\t\tpush @mirrors, \"https://mirror.netcologne.de/gnu/$1\";\n\t\tpush @mirrors, \"http://ftp.kddilabs.jp/GNU/gnu/$1\";\n\t\tpush @mirrors, \"http://www.nic.funet.fi/pub/gnu/gnu/$1\";\n\t\tpush @mirrors, \"http://mirror.internode.on.net/pub/gnu/$1\";\n\t\tpush @mirrors, \"http://mirror.navercorp.com/gnu/$1\";\n\t\tpush @mirrors, \"ftp://mirrors.rit.edu/gnu/$1\";\n\t\tpush @mirrors, \"ftp://download.xs4all.nl/pub/gnu/$1\";\n\t\tpush @mirrors, \"https://ftp.gnu.org/gnu/$1\";\n\t} elsif ($mirror =~ /^\\@SAVANNAH\\/(.+)$/) {\n\t\tpush @mirrors, \"https://mirror.netcologne.de/savannah/$1\";\n\t\tpush @mirrors, \"https://mirror.csclub.uwaterloo.ca/nongnu/$1\";\n\t\tpush @mirrors, \"http://ftp.acc.umu.se/mirror/gnu.org/savannah/$1\";\n\t\tpush @mirrors, \"http://nongnu.uib.no/$1\";\n\t\tpush @mirrors, \"http://ftp.igh.cnrs.fr/pub/nongnu/$1\";\n\t\tpush @mirrors, \"ftp://cdimage.debian.org/mirror/gnu.org/savannah/$1\";\n\t\tpush @mirrors, \"ftp://ftp.acc.umu.se/mirror/gnu.org/savannah/$1\";\n\t} elsif ($mirror =~ /^\\@KERNEL\\/(.+)$/) {\n\t\tmy @extra = ( $1 );\n\t\tif ($filename =~ /linux-\\d+\\.\\d+(?:\\.\\d+)?-rc/) {\n\t\t\tpush @extra, \"$extra[0]/testing\";\n\t\t} elsif ($filename =~ /linux-(\\d+\\.\\d+(?:\\.\\d+)?)/) {\n\t\t\tpush @extra, \"$extra[0]/longterm/v$1\";\n\t\t}\n\t\tforeach my $dir (@extra) {\n\t\t\tpush @mirrors, \"https://cdn.kernel.org/pub/$dir\";\n\t\t\tpush @mirrors, \"https://download.xs4all.nl/ftp.kernel.org/pub/$dir\";\n\t\t\tpush @mirrors, \"https://mirrors.mit.edu/kernel/$dir\";\n\t\t\tpush @mirrors, \"http://ftp.nara.wide.ad.jp/pub/kernel.org/$dir\";\n\t\t\tpush @mirrors, \"http://www.ring.gr.jp/archives/linux/kernel.org/$dir\";\n\t\t\tpush @mirrors, \"ftp://ftp.riken.jp/Linux/kernel.org/$dir\";\n\t\t\tpush @mirrors, \"ftp://www.mirrorservice.org/sites/ftp.kernel.org/pub/$dir\";\n\t\t}\n\t} elsif ($mirror =~ /^\\@GNOME\\/(.+)$/) {\n\t\tpush @mirrors, \"https://download.gnome.org/sources/$1\";\n\t\tpush @mirrors, \"https://mirror.csclub.uwaterloo.ca/gnome/sources/$1\";\n\t\tpush @mirrors, \"http://ftp.acc.umu.se/pub/GNOME/sources/$1\";\n\t\tpush @mirrors, \"http://ftp.kaist.ac.kr/gnome/sources/$1\";\n\t\tpush @mirrors, \"http://www.mirrorservice.org/sites/ftp.gnome.org/pub/GNOME/sources/$1\";\n\t\tpush @mirrors, \"http://mirror.internode.on.net/pub/gnome/sources/$1\";\n\t\tpush @mirrors, \"http://ftp.belnet.be/ftp.gnome.org/sources/$1\";\n\t\tpush @mirrors, \"ftp://ftp.cse.buffalo.edu/pub/Gnome/sources/$1\";\n\t\tpush @mirrors, \"ftp://ftp.nara.wide.ad.jp/pub/X11/GNOME/sources/$1\";\n\t} else {\n\t\tpush @mirrors, $mirror;\n\t}\n}\n\npush @mirrors, 'https://sources.cdn.openwrt.org';\npush @mirrors, 'https://sources.openwrt.org';\npush @mirrors, 'https://mirror2.openwrt.org/sources';\n\nif (-f \"$target/$filename\") {\n\t$hash_cmd and do {\n\t\tif (system(\"cat '$target/$filename' | $hash_cmd > '$target/$filename.hash'\")) {\n\t\t\tdie \"Failed to generate hash for $filename\\n\";\n\t\t}\n\n\t\tmy $sum = `cat \"$target/$filename.hash\"`;\n\t\t$sum =~ /^(\\w+)\\s*/ or die \"Could not generate file hash\\n\";\n\t\t$sum = $1;\n\n\t\tcleanup();\n\t\texit 0 if $sum eq $file_hash;\n\n\t\tdie \"Hash of the local file $filename does not match (file: $sum, requested: $file_hash) - deleting download.\\n\";\n\t\tunlink \"$target/$filename\";\n\t};\n}\n\nwhile (!-f \"$target/$filename\") {\n\tmy $mirror = shift @mirrors;\n\t$mirror or die \"No more mirrors to try - giving up.\\n\";\n\n\tdownload($mirror, $url_filename);\n\tif (!-f \"$target/$filename\" && $url_filename ne $filename) {\n\t\tdownload($mirror, $filename);\n\t}\n}\n\n$SIG{INT} = \\&cleanup;\n"
  },
  {
    "path": "scripts/dump-target-info.pl",
    "content": "#!/usr/bin/env perl\n\nuse strict;\nuse warnings;\nuse Cwd;\n\nmy (%targets, %architectures, %kernels);\n\n$ENV{'TOPDIR'} = Cwd::getcwd();\n\n\nsub parse_targetinfo {\n\tmy ($target_dir, $subtarget) = @_;\n\n\tif (open M, \"make -C '$target_dir' --no-print-directory DUMP=1 TARGET_BUILD=1 SUBTARGET='$subtarget' |\") {\n\t\tmy ($target_name, $target_arch, $target_kernel, $target_testing_kernel, @target_features);\n\t\twhile (defined(my $line = readline M)) {\n\t\t\tchomp $line;\n\n\t\t\tif ($line =~ /^Target: (.+)$/) {\n\t\t\t\t$target_name = $1;\n\t\t\t}\n\t\t\telsif ($line =~ /^Target-Arch-Packages: (.+)$/) {\n\t\t\t\t$target_arch = $1;\n\t\t\t}\n\t\t\telsif ($line =~ /^Linux-Version: (\\d\\.\\d+)\\.\\d+$/) {\n\t\t\t\t$target_kernel = $1;\n\t\t\t}\n\t\t\telsif ($line =~ /^Linux-Testing-Version: (\\d\\.\\d+)\\.\\d+$/) {\n\t\t\t\t$target_testing_kernel = $1;\n\t\t\t}\n\t\t\telsif ($line =~ /^Target-Features: (.+)$/) {\n\t\t\t\t@target_features = split /\\s+/, $1;\n\t\t\t}\n\t\t\telsif ($line =~ /^@\\@$/) {\n\t\t\t\tif ($target_name && $target_arch && $target_kernel &&\n\t\t\t\t    !grep { $_ eq 'broken' or $_ eq 'source-only' } @target_features) {\n\t\t\t\t\t$targets{$target_name} = $target_arch;\n\t\t\t\t\t$architectures{$target_arch} ||= [];\n\t\t\t\t\tpush @{$architectures{$target_arch}}, $target_name;\n\t\t\t\t\t$kernels{$target_name} ||= [];\n\t\t\t\t\tpush @{$kernels{$target_name}}, $target_kernel;\n\t\t\t\t\tif ($target_testing_kernel) {\n\t\t\t\t\t\tpush @{$kernels{$target_name}}, $target_testing_kernel;\n\t\t\t\t\t}\n\t\t\t\t}\n\n\t\t\t\tundef $target_name;\n\t\t\t\tundef $target_arch;\n\t\t\t\tundef $target_kernel;\n\t\t\t\tundef $target_testing_kernel;\n\t\t\t\t@target_features = ();\n\t\t\t}\n\t\t}\n\t\tclose M;\n\t}\n}\n\nsub get_targetinfo {\n\tforeach my $target_makefile (glob \"target/linux/*/Makefile\") {\n\t\tmy ($target_dir) = $target_makefile =~ m!^(.+)/Makefile$!;\n\t\tmy @subtargets;\n\n\t\tif (open M, \"make -C '$target_dir' --no-print-directory DUMP=1 TARGET_BUILD=1 val.FEATURES V=s 2>/dev/null |\") {\n\t\t\tif (defined(my $line = readline M)) {\n\t\t\t\tchomp $line;\n\t\t\t\tif (grep { $_ eq 'broken' or $_ eq 'source-only' } split /\\s+/, $line) {\n\t\t\t\t\tnext;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n\t\tif (open M, \"make -C '$target_dir' --no-print-directory DUMP=1 TARGET_BUILD=1 val.SUBTARGETS V=s 2>/dev/null |\") {\n\t\t\tif (defined(my $line = readline M)) {\n\t\t\t\tchomp $line;\n\t\t\t\t@subtargets = split /\\s+/, $line;\n\t\t\t}\n\t\t\tclose M;\n\t\t}\n\n\t\tpush @subtargets, 'generic' if @subtargets == 0;\n\n\t\tforeach my $subtarget (@subtargets) {\n\t\t\tparse_targetinfo($target_dir, $subtarget);\n\t\t}\n\t}\n}\n\nif (@ARGV == 1 && $ARGV[0] eq 'targets') {\n\tget_targetinfo();\n\tforeach my $target_name (sort keys %targets) {\n\t\tprintf \"%s %s\\n\", $target_name, $targets{$target_name};\n\t}\n}\nelsif (@ARGV == 1 && $ARGV[0] eq 'architectures') {\n\tget_targetinfo();\n\tforeach my $target_arch (sort keys %architectures) {\n\t\tprintf \"%s %s\\n\", $target_arch, join ' ', @{$architectures{$target_arch}};\n\t}\n}\nelsif (@ARGV == 1 && $ARGV[0] eq 'kernels') {\n\tget_targetinfo();\n\tforeach my $target_name (sort keys %targets) {\n\t\tprintf \"%s %s\\n\", $target_name, join ' ', @{$kernels{$target_name}};\n\t}\n}\nelse {\n\tprint \"Usage: $0 targets\\n\";\n\tprint \"Usage: $0 architectures\\n\";\n\tprint \"Usage: $0 kernels\\n\";\n}\n"
  },
  {
    "path": "scripts/env",
    "content": "#!/usr/bin/env bash\nBASEDIR=\"$PWD\"\nENVDIR=\"$PWD/env\"\nexport GREP_OPTIONS=\n\nusage() {\n\tcat <<EOF\nUsage: $0 [options] <command> [arguments]\nCommands:\n\thelp              This help text\n\tlist              List environments\n\tclear             Delete all environment and revert to flat config/files\n\tnew <name>        Create a new environment\n\tswitch <name>     Switch to a different environment\n\tdelete <name>     Delete an environment\n\trename <newname>  Rename the current environment\n\tdiff              Show differences between current state and environment\n\tsave [message]    Save your changes to the environment, optionally using\n\t                  the given commit message\n\trevert            Revert your changes since last save\n\nOptions:\n\nEOF\n\texit \"${1:-1}\"\n}\n\nerror() {\n\techo \"$0: $*\"\n\texit 1\n}\n\nask_bool() {\n\tlocal DEFAULT=\"$1\"; shift\n\tlocal def defstr val\n\tcase \"$DEFAULT\" in\n\t\t1) def=0; defstr=\"Y/n\";;\n\t\t0) def=1; defstr=\"y/N\";;\n\t\t*) def=;  defstr=\"y/n\";;\n\tesac\n\twhile [ -z \"$val\" ]; do\n\t\tlocal VAL\n\n\t\techo -n \"$* ($defstr): \"\n\t\tread -r VAL\n\t\tcase \"$VAL\" in\n\t\t\ty*|Y*) val=0;;\n\t\t\tn*|N*) val=1;;\n\t\t\t*) val=\"$def\";;\n\t\tesac\n\tdone\n\treturn \"$val\"\n}\n\nenv_init() {\n\tlocal CREATE=\"$1\"\n\tif [ -z \"$CREATE\" ]; then\n\t\t[ -d \"$ENVDIR\" ] || exit 0\n\tfi\n\tcommand -v git >/dev/null || error \"Git is not installed\"\n\tmkdir -p \"$ENVDIR\" || error \"Failed to create the environment directory\"\n\tcd \"$ENVDIR\" || error \"Failed to switch to the environment directory\"\n\t[ -d .git ] || { \n\t\tgit init -b master &&\n\t\ttouch .config &&\n\t\tmkdir files &&\n\t\tgit add . && \n\t\tgit commit -q -m \"Initial import\"\n\t} || {\n\t\trm -rf .git\n\t\terror \"Failed to initialize the environment directory\"\n\t}\n}\n\nenv_sync_data() {\n\t[ ! -L \"$BASEDIR/.config\" ] && [ -f \"$BASEDIR/.config\" ] && mv \"$BASEDIR/.config\" \"$ENVDIR\"\n\tgit add .\n\tgit add -u\n}\n\nenv_sync() {\n\tlocal STR=\"$1\"\n\tenv_sync_data\n\tgit commit -m \"${STR:-Update} at $(date)\"\n}\n\nenv_link_config() {\n\trm -f \"$BASEDIR/.config\"\n\tln -s env/.config \"$BASEDIR/.config\"\n\tmkdir -p \"$ENVDIR/files\"\n\t[ -L \"$BASEDIR/files\" ] || ln -s env/files \"$BASEDIR/files\"\n}\n\nenv_do_reset() {\n\tgit reset --hard HEAD\n\tgit clean -d -f\n}\n\nenv_list() {\n\tenv_init\n\tgit branch --color | grep -vE '^. master$'\n}\n\nenv_diff() {\n\tenv_init\n\tenv_sync_data\n\tgit diff --cached --color=auto\n\tenv_link_config\n}\n\nenv_save() {\n\tenv_init\n\tenv_sync \"$@\"\n\tenv_link_config\n}\n\nenv_revert() {\n\tenv_init\n\tenv_do_reset\n\tenv_link_config\n}\n\nenv_ask_sync() {\n\tenv_sync_data\n\tLINES=\"$(env_diff | wc -l)\" # implies env_init\n\t[ \"$LINES\" -gt 0 ] && {\n\t\tif ask_bool 1 \"Do you want to save your changes\"; then\n\t\t\tenv_sync\n\t\telse\n\t\t\tenv_do_reset\n\t\tfi\n\t}\n}\n\nenv_clear() {\n\tenv_init\n\t[ -L \"$BASEDIR/.config\" ] && rm -f \"$BASEDIR/.config\"\n\t[ -L \"$BASEDIR/files\" ] && rm -f \"$BASEDIR/files\"\n\t[ -f \"$ENVDIR/.config\" ] || ( cd \"$ENVDIR/files\" && find . | grep -vE '^\\.$' > /dev/null )\n\tenv_sync_data\n\tif ask_bool 1 \"Do you want to keep your current config and files\"; then\n\t\tmkdir -p \"$BASEDIR/files\"\n\t\tshopt -s dotglob\n\t\tcp -a \"$ENVDIR/files/\"* \"$BASEDIR/files\" 2>/dev/null >/dev/null\n\t\tshopt -u dotglob\n\t\tcp \"$ENVDIR/.config\" \"$BASEDIR/\"\n\telse\n\t\trm -rf \"$BASEDIR/files\" \"$BASEDIR/.config\"\n\tfi\n\tcd \"$BASEDIR\" || exit 1\n\trm -rf \"$ENVDIR\"\n}\n\nenv_delete() {\n\tlocal name=\"${1##*/}\"\n\tenv_init\n\t[ -z \"$name\" ] && usage\n\tbranch=\"$(git branch | grep '^\\* ' | awk '{print $2}')\"\n\t[ \"$name\" = \"$branch\" ] && error \"cannot delete the currently selected environment\"\n\tgit branch -D \"$name\"\n}\n\nenv_switch() {\n\tlocal name=\"${1##*/}\"\n\t[ -z \"$name\" ] && usage\n\n\tenv_init\n\tenv_ask_sync\n\tgit checkout \"$name\" || error \"environment '$name' not found\"\n\tenv_link_config\n}\n\nenv_rename() {\n\tlocal NAME=\"${1##*/}\"\n\tenv_init\n\tgit branch -m \"$NAME\"\n}\n\nenv_new() {\n\tlocal NAME=\"$1\"\n\tlocal branch\n\tlocal from=\"master\"\n\n\t[ -z \"$NAME\" ] && usage\n\tenv_init 1\n\t\n\tbranch=\"$(git branch | grep '^\\* ' | awk '{print $2}')\"\n\tif [ -n \"$branch\" ] && [ \"$branch\" != \"master\" ]; then\n\t\tenv_ask_sync\n\t\tif ask_bool 0 \"Do you want to clone the current environment?\"; then\n\t\t\tfrom=\"$branch\"\n\t\tfi\n\t\trm -f \"$BASEDIR/.config\" \"$BASEDIR/files\"\n\tfi\n\tgit checkout -b \"$1\" \"$from\"\n\tif [ -f \"$BASEDIR/.config\" ] || [ -d \"$BASEDIR/files\" ]; then\n\t\tif ask_bool 1 \"Do you want to start your configuration repository with the current configuration?\"; then\n\t\t\tif [ -d \"$BASEDIR/files\" ] && [ ! -L \"$BASEDIR/files\" ]; then\n\t\t\t\tmkdir -p \"$ENVDIR/files\"\n\t\t\t\tshopt -s dotglob\n\t\t\t\tmv \"$BASEDIR/files/\"* \"$ENVDIR/files/\" 2>/dev/null\n\t\t\t\tshopt -u dotglob\n\t\t\t\trmdir \"$BASEDIR/files\"\n\t\t\tfi\n\t\t\tenv_sync\n\t\telse\n\t\t\trm -rf \"$BASEDIR/.config\" \"$BASEDIR/files\"\n\t\tfi\n\tfi\n\tenv_link_config\n}\n\nCOMMAND=\"$1\"; shift\ncase \"$COMMAND\" in\n\thelp) usage 0;;\n\tnew) env_new \"$@\";;\n\tlist) env_list \"$@\";;\n\tclear) env_clear \"$@\";;\n\tswitch) env_switch \"$@\";;\n\tdelete) env_delete \"$@\";;\n\trename) env_rename \"$@\";;\n\tdiff) env_diff \"$@\";;\n\tsave) env_save \"$@\";;\n\trevert) env_revert \"$@\";;\n\t*) usage;;\nesac\n"
  },
  {
    "path": "scripts/ext-toolchain.sh",
    "content": "#!/usr/bin/env bash\n#\n#   Script for various external toolchain tasks, refer to\n#   the --help output for more information.\n#\n#   Copyright (C) 2012 Jo-Philipp Wich <jo@mein.io>\n#\n#   This program is free software; you can redistribute it and/or modify\n#   it under the terms of the GNU General Public License as published by\n#   the Free Software Foundation; either version 2 of the License, or\n#   (at your option) any later version.\n#\n#   This program is distributed in the hope that it will be useful,\n#   but WITHOUT ANY WARRANTY; without even the implied warranty of\n#   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n#   GNU General Public License for more details.\n#\n#   You should have received a copy of the GNU General Public License\n#   along with this program; if not, write to the Free Software\n#   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA\n\nCC=\"\"\nCXX=\"\"\nCPP=\"\"\n\nCFLAGS=\"\"\nTOOLCHAIN=\".\"\n\nLIBC_TYPE=\"\"\n\n\n# Library specs\nLIB_SPECS=\"\n\tc:        ld-* lib{anl,c,cidn,crypt,dl,m,nsl,nss_dns,nss_files,resolv,util}\n\trt:       librt-* librt\n\tpthread:  libpthread-* libpthread\n\tstdcpp:   libstdc++\n\tthread_db: libthread-db\n\tgcc:      libgcc_s\n\tssp:      libssp\n\tgfortran: libgfortran\n\tgomp:\t  libgomp\n\"\n\n# Binary specs\nBIN_SPECS=\"\n\tldd:       ldd\n\tldconfig:  ldconfig\n\tgdb:       gdb\n\tgdbserver: gdbserver\n\"\n\n\ntest_c() {\n\tcat <<-EOT | \"${CC:-false}\" $CFLAGS -o /dev/null -x c - 2>/dev/null\n\t\t#include <stdio.h>\n\n\t\tint main(int argc, char **argv)\n\t\t{\n\t\t\tprintf(\"Hello, world!\\n\");\n\t\t\treturn 0;\n\t\t}\n\tEOT\n}\n\ntest_cxx() {\n\tcat <<-EOT | \"${CXX:-false}\" $CFLAGS -o /dev/null -x c++ - 2>/dev/null\n\t\t#include <iostream>\n\n\t\tusing namespace std;\n\n\t\tint main()\n\t\t{\n\t\t\tcout << \"Hello, world!\" << endl;\n\t\t\treturn 0;\n\t\t}\n\tEOT\n}\n\ntest_softfloat() {\n\tcat <<-EOT | \"$CC\" $CFLAGS -msoft-float -o /dev/null -x c - 2>/dev/null\n\t\tint main(int argc, char **argv)\n\t\t{\n\t\t\tdouble a = 0.1;\n\t\t\tdouble b = 0.2;\n\t\t\tdouble c = (a + b) / (a * b);\n\t\t\treturn 1;\n\t\t}\n\tEOT\n}\n\ntest_uclibc() {\n\tlocal sysroot=\"$(\"$CC\" $CFLAGS -print-sysroot 2>/dev/null)\"\n\tif [ -d \"${sysroot:-$TOOLCHAIN}\" ]; then\n\t\tlocal lib\n\t\tfor lib in \"${sysroot:-$TOOLCHAIN}\"/{lib,usr/lib,usr/local/lib}/ld*-uClibc*.so*; do\n\t\t\tif [ -f \"$lib\" ] && [ ! -h \"$lib\" ]; then\n\t\t\t\treturn 0\n\t\t\tfi\n\t\tdone\n\tfi\n\treturn 1\n}\n\ntest_feature() {\n\tlocal feature=\"$1\"; shift\n\n\t# find compilers, libc type\n\tprobe_cc\n\tprobe_cxx\n\tprobe_libc\n\n\t# common toolchain feature tests\n\tcase \"$feature\" in\n\t\tc)     test_c;         return $? ;;\n\t\tc++)   test_cxx;       return $? ;;\n\t\tsoft*) test_softfloat; return $? ;;\n\tesac\n\n\t# assume eglibc/glibc supports all libc features\n\tif [ \"$LIBC_TYPE\" != \"uclibc\" ]; then\n\t\treturn 0\n\tfi\n\n\t# uclibc feature tests\n\tlocal inc\n\tlocal sysroot=\"$(\"$CC\" \"$@\" -muclibc -print-sysroot 2>/dev/null)\"\n\tfor inc in \"include\" \"usr/include\" \"usr/local/include\"; do\n\t\tlocal conf=\"${sysroot:-$TOOLCHAIN}/$inc/bits/uClibc_config.h\"\n\t\tif [ -f \"$conf\" ]; then\n\t\t\tcase \"$feature\" in\n\t\t\t\tlfs)     grep -q '__UCLIBC_HAS_LFS__ 1'     \"$conf\"; return $?;;\n\t\t\t\tipv6)    grep -q '__UCLIBC_HAS_IPV6__ 1'    \"$conf\"; return $?;;\n\t\t\t\trpc)     grep -q '__UCLIBC_HAS_RPC__ 1'     \"$conf\"; return $?;;\n\t\t\t\tlocale)  grep -q '__UCLIBC_HAS_LOCALE__ 1'  \"$conf\"; return $?;;\n\t\t\t\twchar)   grep -q '__UCLIBC_HAS_WCHAR__ 1'   \"$conf\"; return $?;;\n\t\t\t\tthreads) grep -q '__UCLIBC_HAS_THREADS__ 1' \"$conf\"; return $?;;\n\t\t\tesac\n\t\tfi\n\tdone\n\n\treturn 1\n}\n\n\nfind_libs() {\n\tlocal spec=\"$(echo \"$LIB_SPECS\" | sed -ne \"s#^[[:space:]]*$1:##ip\")\"\n\n\tif [ -n \"$spec\" ] && probe_cpp; then\n\t\tlocal libdir libdirs\n\t\tfor libdir in $(\n\t\t\t\"$CPP\" $CFLAGS -v -x c /dev/null 2>&1 | \\\n\t\t\t\tsed -ne 's#:# #g; s#^LIBRARY_PATH=##p'\n\t\t); do\n\t\t\tif [ -d \"$libdir\" ]; then\n\t\t\t\tlibdirs=\"$libdirs $(cd \"$libdir\"; pwd)/\"\n\t\t\tfi\n\t\tdone\n\n\t\tlocal pattern\n\t\tfor pattern in $(eval echo $spec); do\n\t\t\tfind $libdirs -name \"$pattern.so*\" | sort -u\n\t\tdone\n\n\t\treturn 0\n\tfi\n\n\treturn 1\n}\n\nfind_bins() {\n\tlocal spec=\"$(echo \"$BIN_SPECS\" | sed -ne \"s#^[[:space:]]*$1:##ip\")\"\n\n\tif [ -n \"$spec\" ] && probe_cpp; then\n\t\tlocal sysroot=\"$(\"$CPP\" -print-sysroot)\"\n\n\t\tlocal bindir bindirs\n\t\tfor bindir in $(\n\t\t\techo \"${sysroot:-$TOOLCHAIN}/bin\";\n\t\t\techo \"${sysroot:-$TOOLCHAIN}/usr/bin\";\n\t\t\techo \"${sysroot:-$TOOLCHAIN}/usr/local/bin\";\n \t\t\t\"$CPP\" $CFLAGS -v -x c /dev/null 2>&1 | \\\n\t\t\t\tsed -ne 's#:# #g; s#^COMPILER_PATH=##p'\n\t\t); do\n\t\t\tif [ -d \"$bindir\" ]; then\n\t\t\t\tbindirs=\"$bindirs $(cd \"$bindir\"; pwd)/\"\n\t\t\tfi\n\t\tdone\n\n\t\tlocal pattern\n\t\tfor pattern in $(eval echo $spec); do\n\t\t\tfind $bindirs -name \"$pattern\" | sort -u\n\t\tdone\n\n\t\treturn 0\n\tfi\n\n\treturn 1\n}\n\n\nwrap_bin_cc() {\n\tlocal out=\"$1\"\n\tlocal bin=\"$2\"\n\n\techo    '#!/bin/sh'                                                > \"$out\"\n\techo    'for arg in \"$@\"; do'                                     >> \"$out\"\n\techo    ' case \"$arg\" in -l*|-L*|-shared|-static)'                >> \"$out\"\n\techo -n '  exec \"'\"$bin\"'\" '\"$CFLAGS\"' ${STAGING_DIR:+'           >> \"$out\"\n\techo -n '-idirafter \"$STAGING_DIR/usr/include\" '                  >> \"$out\"\n\techo -n '-L \"$STAGING_DIR/usr/lib\" '                              >> \"$out\"\n\techo    '-Wl,-rpath-link,\"$STAGING_DIR/usr/lib\"} \"$@\" ;;'         >> \"$out\"\n\techo    ' esac'                                                   >> \"$out\"\n\techo    'done'                                                    >> \"$out\"\n\techo -n 'exec \"'\"$bin\"'\" '\"$CFLAGS\"' ${STAGING_DIR:+'             >> \"$out\"\n\techo    '-idirafter \"$STAGING_DIR/usr/include\"} \"$@\"'             >> \"$out\"\n\n\tchmod +x \"$out\"\n}\n\nwrap_bin_ld() {\n\tlocal out=\"$1\"\n\tlocal bin=\"$2\"\n\n\techo    '#!/bin/sh'                                                > \"$out\"\n\techo -n 'exec \"'\"$bin\"'\" ${STAGING_DIR:+'                         >> \"$out\"\n\techo -n '-L \"$STAGING_DIR/usr/lib\" '                              >> \"$out\"\n\techo    '-rpath-link \"$STAGING_DIR/usr/lib\"} \"$@\"'                >> \"$out\"\n\n\tchmod +x \"$out\"\n}\n\nwrap_bin_other() {\n\tlocal out=\"$1\"\n\tlocal bin=\"$2\"\n\n\techo    '#!/bin/sh'                                                > \"$out\"\n\techo    'exec \"'\"$bin\"'\" \"$@\"'                                    >> \"$out\"\n\n\tchmod +x \"$out\"\n}\n\nwrap_bins() {\n\tif probe_cc; then\n\t\tmkdir -p \"$1\" || return 1\n\n\t\tlocal cmd\n\t\tfor cmd in \"${CC%-*}-\"*; do\n\t\t\tif [ -x \"$cmd\" ]; then\n\t\t\t\tlocal out=\"$1/${cmd##*/}\"\n\t\t\t\tlocal bin=\"$cmd\"\n\n\t\t\t\tif [ -x \"$out\" ] && ! grep -q STAGING_DIR \"$out\"; then\n\t\t\t\t\tmv \"$out\" \"$out.bin\"\n\t\t\t\t\tbin='$(dirname \"$0\")/'\"${out##*/}\"'.bin'\n\t\t\t\tfi\n\n\t\t\t\tcase \"${cmd##*/}\" in\n\t\t\t\t\t*-*cc|*-*cc-*|*-*++|*-*++-*|*-cpp)\n\t\t\t\t\t\twrap_bin_cc \"$out\" \"$bin\"\n\t\t\t\t\t;;\n\t\t\t\t\t*-ld)\n\t\t\t\t\t\twrap_bin_ld \"$out\" \"$bin\"\n\t\t\t\t\t;;\n\t\t\t\t\t*)\n\t\t\t\t\t\twrap_bin_other \"$out\" \"$bin\"\n\t\t\t\t\t;;\n\t\t\t\tesac\n\t\t\tfi\n\t\tdone\n\n\t\treturn 0\n\tfi\n\n\treturn 1\n}\n\n\nprint_config() {\n\tlocal mktarget=\"$1\"\n\tlocal mksubtarget\n\n\tlocal target=\"$(\"$CC\" $CFLAGS -dumpmachine)\"\n\tlocal cpuarch=\"${target%%-*}\"\n\tlocal prefix=\"${CC##*/}\"; prefix=\"${prefix%-*}-\"\n\tlocal config=\"${0%/scripts/*}/.config\"\n\n\t# if no target specified, print choice list and exit\n\tif [ -z \"$mktarget\" ]; then\n\t\t# prepare metadata\n\t\tif [ ! -f \"${0%/scripts/*}/tmp/.targetinfo\" ]; then\n\t\t\t\"${0%/*}/scripts/config/mconf\" prepare-tmpinfo\n\t\tfi\n\n\t\tlocal mktargets=$(\n\t\t\tsed -ne \"\n\t\t\t\t/^Target: / { h };\n\t\t\t\t/^Target-Arch: $cpuarch\\$/ { x; s#^Target: ##p }\n\t\t\t\" \"${0%/scripts/*}/tmp/.targetinfo\" | sort -u\n\t\t)\n\n\t\tfor mktarget in $mktargets; do\n\t\t\tcase \"$mktarget\" in */*)\n\t\t\t\tmktargets=$(echo \"$mktargets\" | sed -e \"/^${mktarget%/*}\\$/d\")\n\t\t\tesac\n\t\tdone\n\n\t\tif [ -n \"$mktargets\" ]; then\n\t\t\techo \"Available targets:\"                               >&2\n\t\t\techo $mktargets                                         >&2\n\t\telse\n\t\t\techo -e \"Could not find a suitable OpenWrt target for \" >&2\n\t\t\techo -e \"CPU architecture '$cpuarch' - you need to \"    >&2\n\t\t\techo -e \"define one first!\"                             >&2\n\t\tfi\n\t\treturn 1\n\tfi\n\n\t# bail out if there is a .config already\n\tif [ -f \"${0%/scripts/*}/.config\" ]; then\n\t\techo \"There already is a .config file, refusing to overwrite!\" >&2\n\t\treturn 1\n\tfi\n\n\tcase \"$mktarget\" in */*)\n\t\tmksubtarget=\"${mktarget#*/}\"\n\t\tmktarget=\"${mktarget%/*}\"\n\t;; esac\n\n\n\techo \"CONFIG_TARGET_${mktarget}=y\" > \"$config\"\n\n\tif [ -n \"$mksubtarget\" ]; then\n\t\techo \"CONFIG_TARGET_${mktarget}_${mksubtarget}=y\" >> \"$config\"\n\tfi\n\n\tif test_feature \"softfloat\"; then\n\t\techo \"CONFIG_SOFT_FLOAT=y\" >> \"$config\"\n\telse\n\t\techo \"# CONFIG_SOFT_FLOAT is not set\" >> \"$config\"\n\tfi\n\n\tif test_feature \"ipv6\"; then\n\t\techo \"CONFIG_IPV6=y\" >> \"$config\"\n\telse\n\t\techo \"# CONFIG_IPV6 is not set\" >> \"$config\"\n\tfi\n\n\tif test_feature \"locale\"; then\n\t\techo \"CONFIG_BUILD_NLS=y\" >> \"$config\"\n\telse\n\t\techo \"# CONFIG_BUILD_NLS is not set\" >> \"$config\"\n\tfi\n\n\techo \"CONFIG_DEVEL=y\" >> \"$config\"\n\techo \"CONFIG_EXTERNAL_TOOLCHAIN=y\" >> \"$config\"\n\techo \"CONFIG_TOOLCHAIN_ROOT=\\\"$TOOLCHAIN\\\"\" >> \"$config\"\n\techo \"CONFIG_TOOLCHAIN_PREFIX=\\\"$prefix\\\"\" >> \"$config\"\n\techo \"CONFIG_TARGET_NAME=\\\"$target\\\"\" >> \"$config\"\n\n\tif [ \"$LIBC_TYPE\" != glibc ]; then\n\t\techo \"CONFIG_TOOLCHAIN_LIBC=\\\"$LIBC_TYPE\\\"\" >> \"$config\"\n\tfi\n\n\tlocal lib\n\tfor lib in C RT PTHREAD GCC STDCPP SSP GFORTRAN GOMP; do\n\t\tlocal file\n\t\tlocal spec=\"\"\n\t\tlocal llib=\"$(echo \"$lib\" | sed -e 's#.*#\\L&#')\"\n\t\tfor file in $(find_libs \"$lib\"); do\n\t\t\tspec=\"${spec:+$spec }$(echo \"$file\" | sed -e \"s#^$TOOLCHAIN#.#\")\"\n\t\tdone\n\t\tif [ -n \"$spec\" ]; then\n\t\t\techo \"CONFIG_PACKAGE_lib${llib}=y\" >> \"$config\"\n\t\t\techo \"CONFIG_LIB${lib}_FILE_SPEC=\\\"$spec\\\"\" >> \"$config\"\n\t\telse\n\t\t\techo \"# CONFIG_PACKAGE_lib${llib} is not set\" >> \"$config\"\n\t\tfi\n\tdone\n\n\tlocal bin\n\tfor bin in LDD LDCONFIG; do\n\t\tlocal file\n\t\tlocal spec=\"\"\n\t\tlocal lbin=\"$(echo \"$bin\" | sed -e 's#.*#\\L&#')\"\n\t\tfor file in $(find_bins \"$bin\"); do\n\t\t\tspec=\"${spec:+$spec }$(echo \"$file\" | sed -e \"s#^$TOOLCHAIN#.#\")\"\n\t\tdone\n\t\tif [ -n \"$spec\" ]; then\n\t\t\techo \"CONFIG_PACKAGE_${lbin}=y\" >> \"$config\"\n\t\t\techo \"CONFIG_${bin}_FILE_SPEC=\\\"$spec\\\"\" >> \"$config\"\n\t\telse\n\t\t\techo \"# CONFIG_PACKAGE_${lbin} is not set\" >> \"$config\"\n\t\tfi\n\tdone\n\n\t# inflate\n\tmake -C \"${0%/scripts/*}\" defconfig\n\treturn 0\n}\n\n\nprobe_cc() {\n\tif [ -z \"$CC\" ]; then\n\t\tlocal bin\n\t\tfor bin in \"bin\" \"usr/bin\" \"usr/local/bin\"; do\n\t\t\tlocal cmd\n\t\t\tfor cmd in \"$TOOLCHAIN/$bin/\"*-*cc*; do\n\t\t\t\tif [ -x \"$cmd\" ] && [ ! -h \"$cmd\" ]; then\n\t\t\t\t\tCC=\"$(cd \"${cmd%/*}\"; pwd)/${cmd##*/}\"\n\t\t\t\t\treturn 0\n\t\t\t\tfi\n\t\t\tdone\n\t\tdone\n\t\treturn 1\n\tfi\n\treturn 0\n}\n\nprobe_cxx() {\n\tif [ -z \"$CXX\" ]; then\n\t\tlocal bin\n\t\tfor bin in \"bin\" \"usr/bin\" \"usr/local/bin\"; do\n\t\t\tlocal cmd\n\t\t\tfor cmd in \"$TOOLCHAIN/$bin/\"*-*++*; do\n\t\t\t\tif [ -x \"$cmd\" ] && [ ! -h \"$cmd\" ]; then\n\t\t\t\t\tCXX=\"$(cd \"${cmd%/*}\"; pwd)/${cmd##*/}\"\n\t\t\t\t\treturn 0\n\t\t\t\tfi\n\t\t\tdone\n\t\tdone\n\t\treturn 1\n\tfi\n\treturn 0\n}\n\nprobe_cpp() {\n\tif [ -z \"$CPP\" ]; then\n\t\tlocal bin\n\t\tfor bin in \"bin\" \"usr/bin\" \"usr/local/bin\"; do\n\t\t\tlocal cmd\n\t\t\tfor cmd in \"$TOOLCHAIN/$bin/\"*-cpp*; do\n\t\t\t\tif [ -x \"$cmd\" ] && [ ! -h \"$cmd\" ]; then\n\t\t\t\t\tCPP=\"$(cd \"${cmd%/*}\"; pwd)/${cmd##*/}\"\n\t\t\t\t\treturn 0\n\t\t\t\tfi\n\t\t\tdone\n\t\tdone\n\t\treturn 1\n\tfi\n\treturn 0\n}\n\nprobe_libc() {\n\tif [ -z \"$LIBC_TYPE\" ]; then\n\t\tif test_uclibc; then\n\t\t\tLIBC_TYPE=\"uclibc\"\n\t\telse\n\t\t\tLIBC_TYPE=\"glibc\"\n\t\tfi\n\tfi\n\treturn 0\n}\n\n\nwhile [ -n \"$1\" ]; do\n\targ=\"$1\"; shift\n\tcase \"$arg\" in\n\t\t--toolchain)\n\t\t\t[ -d \"$1\" ] || {\n\t\t\t\techo \"Toolchain directory '$1' does not exist.\" >&2\n\t\t\t\texit 1\n\t\t\t}\n\t\t\tTOOLCHAIN=\"$(cd \"$1\"; pwd)\"; shift\n\t\t;;\n\n\t\t--cflags)\n\t\t\tCFLAGS=\"${CFLAGS:+$CFLAGS }$1\"; shift\n\t\t;;\n\n\t\t--print-libc)\n\t\t\tif probe_cc; then\n\t\t\t\tprobe_libc\n\t\t\t\techo \"$LIBC_TYPE\"\n\t\t\t\texit 0\n\t\t\tfi\n\t\t\techo \"No C compiler found in '$TOOLCHAIN'.\" >&2\n\t\t\texit 1\n\t\t;;\n\n\t\t--print-target)\n\t\t\tif probe_cc; then\n\t\t\t\texec \"$CC\" $CFLAGS -dumpmachine\n\t\t\tfi\n\t\t\techo \"No C compiler found in '$TOOLCHAIN'.\" >&2\n\t\t\texit 1\n\t\t;;\n\n\t\t--print-bin)\n\t\t\tif [ -z \"$1\" ]; then\n\t\t\t\techo \"Available programs:\"                      >&2\n\t\t\t\techo $(echo \"$BIN_SPECS\" | sed -ne 's#:.*$##p') >&2\n\t\t\t\texit 1\n\t\t\tfi\n\n\t\t\tfind_bins \"$1\" || exec \"$0\" --toolchain \"$TOOLCHAIN\" --print-bin\n\t\t\texit 0\n\t\t;;\n\n\t\t--print-libs)\n\t\t\tif [ -z \"$1\" ]; then\n\t\t\t\techo \"Available libraries:\"                     >&2\n\t\t\t\techo $(echo \"$LIB_SPECS\" | sed -ne 's#:.*$##p') >&2\n\t\t\t\texit 1\n\t\t\tfi\n\n\t\t\tfind_libs \"$1\" || exec \"$0\" --toolchain \"$TOOLCHAIN\" --print-libs\n\t\t\texit 0\n\t\t;;\n\n\t\t--test)\n\t\t\ttest_feature \"$1\"\n\t\t\texit $?\n\t\t;;\n\n\t\t--wrap)\n\t\t\t[ -n \"$1\" ] || exec \"$0\" --help\n\t\t\twrap_bins \"$1\"\n\t\t\texit $?\n\t\t;;\n\n\t\t--config)\n\t\t\tif probe_cc; then\n\t\t\t\tprint_config \"$1\"\n\t\t\t\texit $?\n\t\t\tfi\n\t\t\techo \"No C compiler found in '$TOOLCHAIN'.\" >&2\n\t\t\texit 1\n\t\t;;\n\n\t\t-h|--help)\n\t\t\tme=\"$(basename \"$0\")\"\n\t\t\techo -e \"\\nUsage:\\n\"                                            >&2\n\t\t\techo -e \"  $me --toolchain {directory} --print-libc\"            >&2\n\t\t\techo -e \"    Print the libc implementation and exit.\\n\"         >&2\n\t\t\techo -e \"  $me --toolchain {directory} --print-target\"          >&2\n\t\t\techo -e \"    Print the GNU target name and exit.\\n\"             >&2\n\t\t\techo -e \"  $me --toolchain {directory} --print-bin {program}\"   >&2\n\t\t\techo -e \"    Print executables belonging to given program,\"     >&2\n\t\t\techo -e \"    omit program argument to get a list of names.\\n\"   >&2\n\t\t\techo -e \"  $me --toolchain {directory} --print-libs {library}\"  >&2\n\t\t\techo -e \"    Print shared objects belonging to given library,\"  >&2\n\t\t\techo -e \"    omit library argument to get a list of names.\\n\"   >&2\n\t\t\techo -e \"  $me --toolchain {directory} --test {feature}\"        >&2\n\t\t\techo -e \"    Test given feature, exit code indicates success.\"  >&2\n\t\t\techo -e \"    Possible features are 'c', 'c++', 'softfloat',\"    >&2\n\t\t\techo -e \"    'lfs', 'rpc', 'ipv6', 'wchar', 'locale' and \"      >&2\n\t\t\techo -e \"    'threads'.\\n\"                                      >&2\n\t\t\techo -e \"  $me --toolchain {directory} --wrap {directory}\"      >&2\n\t\t\techo -e \"    Create wrapper scripts for C and C++ compiler, \"   >&2\n\t\t\techo -e \"    linker, assembler and other key executables in \"   >&2\n\t\t\techo -e \"    the directory given with --wrap.\\n\"                >&2\n\t\t\techo -e \"  $me --toolchain {directory} --config {target}\"       >&2\n\t\t\techo -e \"    Analyze the given toolchain and print a suitable\"  >&2\n\t\t\techo -e \"    .config for the given target. Omit target \"        >&2\n\t\t\techo -e \"    argument to get a list of names.\\n\"                >&2\n\t\t\techo -e \"  $me --help\"                                          >&2\n\t\t\techo -e \"    Display this help text and exit.\\n\\n\"              >&2\n\t\t\techo -e \"  Most commands also take a --cflags parameter which \" >&2\n\t\t\techo -e \"  is used to specify C flags to be passed to the \"     >&2\n\t\t\techo -e \"  cross compiler when performing tests.\"               >&2\n\t\t\techo -e \"  This parameter may be repeated multiple times.\"      >&2\n\t\t\texit 1\n\t\t;;\n\n\t\t*)\n\t\t\techo \"Unknown argument '$arg'\" >&2\n\t\t\texec $0 --help\n\t\t;;\n\tesac\ndone\n\nexec $0 --help\n"
  },
  {
    "path": "scripts/feeds",
    "content": "#!/usr/bin/env perl\nuse Getopt::Std;\nuse FindBin;\nuse Cwd;\nuse lib \"$FindBin::Bin\";\nuse metadata;\nuse warnings;\nuse strict;\nuse Cwd 'abs_path';\n\nchdir \"$FindBin::Bin/..\";\n$ENV{TOPDIR} //= getcwd();\nchdir $ENV{TOPDIR};\n$ENV{GIT_CONFIG_PARAMETERS}=\"'core.autocrlf=false'\";\n$ENV{GREP_OPTIONS}=\"\";\n\nmy $mk=`command -v gmake 2>/dev/null`;\t# select the right 'make' program\nchomp($mk);\t\t# trim trailing newline\n$mk or $mk = \"make\";\t# default to 'make'\n\n# check version of make\nmy @mkver = split /\\s+/, `$mk -v`, 4;\nmy $valid_mk = 1;\n$mkver[0] =~ /^GNU/ or $valid_mk = 0;\n$mkver[1] =~ /^Make/ or $valid_mk = 0;\n\nmy ($mkv1, $mkv2) = split /\\./, $mkver[2];\n($mkv1 >= 4 || ($mkv1 == 3 && $mkv2 >= 81)) or $valid_mk = 0;\n\n$valid_mk or die \"Unsupported version of make found: $mk\\n\";\n\nmy @feeds;\nmy %build_packages;\nmy %installed;\nmy %installed_pkg;\nmy %installed_targets;\nmy %feed_cache;\n\nmy $feed_package = {};\nmy $feed_src = {};\nmy $feed_target = {};\nmy $feed_vpackage = {};\n\nsub parse_file($$);\n\nsub parse_file($$) {\n\tmy ($fname, $existing) = @_;\n\tmy $line = 0;\n\tmy $fh;\n\n\topen $fh, $fname or return undef;\n\twhile (<$fh>) {\n\t\tchomp;\n\t\ts/#.+$//;\n\t\t$line++;\n\t\tnext unless /\\S/;\n\n\t\tmy ($type, $flags, $name, $urls) = m!^src-([\\w\\-]+)((?:\\s+--\\w+(?:=\\S+)?)*)\\s+(\\w+)(?:\\s+(\\S.*))?$!;\n\t\tunless ($type && $name) {\n\t\t\tdie \"Syntax error in $fname, line $line\\n\";\n\t\t}\n\n\t\tif ($existing->{$name}++) {\n\t\t\tdie \"Duplicate feed name '$name' in '$fname' line: $line\\n\";\n\t\t}\n\n\t\tmy @src = defined($urls) ? split /\\s+/, $urls : ();\n\t\tpush @src, '' if @src == 0;\n\n\t\tmy %flags;\n\t\tif (defined $flags) {\n\t\t\twhile ($flags =~ m!\\s+--(\\w+)(?:=(\\S+))?!g) {\n\t\t\t\t$flags{$1} = defined($2) ? $2 : 1;\n\t\t\t}\n\t\t}\n\n\t\tif ($type eq \"include\") {\n\t\t\tparse_file($urls, $existing) or\n\t\t\t    die \"Unable to open included file '$urls'\";\n\t\t\tnext;\n\t\t}\n\n\t\tpush @feeds, [\"src-$type\", $name, \\@src, \\%flags];\n\t}\n\tclose $fh;\n\treturn 1;\n}\n\nsub parse_config() {\n\tmy %name;\n\tparse_file(\"feeds.conf\", \\%name) or\n\t    parse_file(\"feeds.conf.default\", \\%name)  or\n\t    die \"Unable to open feeds configuration\";\n}\n\nsub update_location($$)\n{\n\tmy $name = shift;\n\tmy $url  = shift;\n\tmy $old_url;\n\n\t-d \"./feeds/$name.tmp\" or mkdir \"./feeds/$name.tmp\" or return 1;\n\n\tif( open LOC, \"< ./feeds/$name.tmp/location\" )\n\t{\n\t\tchomp($old_url = readline LOC);\n\t\tclose LOC;\n\t}\n\n\tif( !$old_url || $old_url ne $url )\n\t{\n\t\tif( open LOC, \"> ./feeds/$name.tmp/location\" )\n\t\t{\n\t\t\tprint LOC $url, \"\\n\";\n\t\t\tclose LOC;\n\t\t}\n\t\treturn $old_url ? 1 : 0;\n\t}\n\n\treturn 0;\n}\n\nsub update_index($)\n{\n\tmy $name = shift;\n\n\t-d \"./feeds/$name.tmp\" or mkdir \"./feeds/$name.tmp\" or return 1;\n\t-d \"./feeds/$name.tmp/info\" or mkdir \"./feeds/$name.tmp/info\" or return 1;\n\n\tsystem(\"$mk -s prepare-mk OPENWRT_BUILD= TMP_DIR=\\\"$ENV{TOPDIR}/feeds/$name.tmp\\\"\");\n\tsystem(\"$mk -s -f include/scan.mk IS_TTY=1 SCAN_TARGET=\\\"packageinfo\\\" SCAN_DIR=\\\"feeds/$name\\\" SCAN_NAME=\\\"package\\\" SCAN_DEPTH=5 SCAN_EXTRA=\\\"\\\" TMP_DIR=\\\"$ENV{TOPDIR}/feeds/$name.tmp\\\"\");\n\tsystem(\"$mk -s -f include/scan.mk IS_TTY=1 SCAN_TARGET=\\\"targetinfo\\\" SCAN_DIR=\\\"feeds/$name\\\" SCAN_NAME=\\\"target\\\" SCAN_DEPTH=5 SCAN_EXTRA=\\\"\\\" SCAN_MAKEOPTS=\\\"TARGET_BUILD=1\\\" TMP_DIR=\\\"$ENV{TOPDIR}/feeds/$name.tmp\\\"\");\n\tsystem(\"ln -sf $name.tmp/.packageinfo ./feeds/$name.index\");\n\tsystem(\"ln -sf $name.tmp/.targetinfo ./feeds/$name.targetindex\");\n\n\treturn 0;\n}\n\nmy %update_method = (\n\t'src-svn' => {\n\t\t'init'\t\t=> \"svn checkout '%s' '%s'\",\n\t\t'update'\t=> \"svn update\",\n\t\t'controldir'\t=> \".svn\",\n\t\t'revision'\t=> \"svn info | grep 'Revision' | cut -d ' ' -f 2 | tr -d '\\n'\"},\n\t'src-cpy' => {\n\t\t'init'\t\t=> \"cp -Rf '%s' '%s'\",\n\t\t'update'\t=> \"\",\n\t\t'revision'\t=> \"echo -n 'local'\"},\n\t'src-link' => {\n\t\t'init'\t\t=> \"ln -s '%s' '%s'\",\n\t\t'update'\t=> \"\",\n\t\t'revision'\t=> \"echo -n 'local'\"},\n\t'src-dummy' => {\n\t\t'init'\t\t=> \"true '%s' && mkdir '%s'\",\n\t\t'update'\t=> \"\",\n\t\t'revision'\t=> \"echo -n 'dummy'\"},\n\t'src-git' => {\n\t\t'init'          => \"git clone --depth 1 '%s' '%s'\",\n\t\t'init_branch'   => \"git clone --depth 1 --branch '%s' '%s' '%s'\",\n\t\t'init_commit'   => \"git clone '%s' '%s' && cd '%s' && git checkout -b '%s' '%s' && cd -\",\n\t\t'update'\t=> \"git pull --ff-only\",\n\t\t'update_force'\t=> \"git pull --ff-only || (git reset --hard HEAD; git pull --ff-only; exit 1)\",\n\t\t'post_update'\t=> \"git submodule update --init --recursive\",\n\t\t'controldir'\t=> \".git\",\n\t\t'revision'\t=> \"git rev-parse --short HEAD | tr -d '\\n'\"},\n\t'src-git-full' => {\n\t\t'init'          => \"git clone '%s' '%s'\",\n\t\t'init_branch'   => \"git clone --branch '%s' '%s' '%s'\",\n\t\t'init_commit'   => \"git clone '%s' '%s' && cd '%s' && git checkout -b '%s' '%s' && cd -\",\n\t\t'update'\t=> \"git pull --ff-only\",\n\t\t'update_force'\t=> \"git pull --ff-only || (git reset --hard HEAD; git pull --ff-only; exit 1)\",\n\t\t'post_update'\t=> \"git submodule update --init --recursive\",\n\t\t'controldir'\t=> \".git\",\n\t\t'revision'\t=> \"git rev-parse --short HEAD | tr -d '\\n'\"},\n\t'src-gitsvn' => {\n\t\t'init'\t=> \"git svn clone -r HEAD '%s' '%s'\",\n\t\t'update'\t=> \"git svn rebase\",\n\t\t'controldir'\t=> \".git\",\n\t\t'revision'\t=> \"git rev-parse --short HEAD | tr -d '\\n'\"},\n\t'src-bzr' => {\n\t\t'init'\t\t=> \"bzr checkout --lightweight '%s' '%s'\",\n\t\t'update'\t=> \"bzr update\",\n\t\t'controldir'\t=> \".bzr\"},\n\t'src-hg' => {\n\t\t'init'\t\t=> \"hg clone '%s' '%s'\",\n\t\t'update'\t=> \"hg pull --update\",\n\t\t'controldir'\t=> \".hg\"},\n\t'src-darcs' => {\n\t\t'init'    => \"darcs get '%s' '%s'\",\n\t\t'update'  => \"darcs pull -a\",\n\t\t'controldir' => \"_darcs\"},\n);\n\n# src-git: pull broken\n# src-cpy: broken if `basename $src` != $name\n\nsub update_feed_via($$$$$) {\n\tmy $type = shift;\n\tmy $name = shift;\n\tmy $src = shift;\n\tmy $relocate = shift;\n\tmy $force = shift;\n\n\tmy $m = $update_method{$type};\n\tmy $localpath = \"./feeds/$name\";\n\tmy $safepath = $localpath;\n\t$safepath =~ s/'/'\\\\''/;\n\tmy ($base_branch, $branch) = split(/;/, $src, 2);\n\tmy ($base_commit, $commit) = split(/\\^/, $src, 2);\n\n\tif( $relocate || !$m->{'update'} || !-d \"$localpath/$m->{'controldir'}\" ) {\n\t\tsystem(\"rm -rf '$safepath'\");\n\t\tif ($m->{'init_branch'} and $branch) {\n\t\t\tsystem(sprintf($m->{'init_branch'}, $branch, $base_branch, $safepath)) == 0 or return 1;\n\t\t} elsif ($m->{'init_commit'} and $commit) {\n\t\t\tsystem(sprintf($m->{'init_commit'}, $base_commit, $safepath, $safepath, $commit, $commit)) == 0 or return 1;\n\t\t} else {\n\t\t\tsystem(sprintf($m->{'init'}, $src, $safepath)) == 0 or return 1;\n\t\t}\n\t} elsif ($m->{'init_commit'} and $commit) {\n\t\t# in case git hash has been provided don't update the feed\n\t} else {\n\t\tmy $update_cmd = $m->{'update'};\n\t\tif ($force && exists $m->{'update_force'}) {\n\t\t\t$update_cmd = $m->{'update_force'};\n\t\t}\n\t\tsystem(\"cd '$safepath'; $update_cmd\") == 0 or return 1;\n\t}\n\tif ($m->{'post_update'}) {\n\t\tmy $cmd = $m->{'post_update'};\n\t\tsystem(\"cd '$safepath'; $cmd\") == 0 or return 1;\n\t}\n\n\treturn 0;\n}\n\nsub get_targets($) {\n\tmy $file = shift;\n\tmy @target = parse_target_metadata($file);\n\tmy %target;\n\tforeach my $target (@target) {\n\t\t$target{$target->{id}} = $target;\n\t}\n\treturn %target\n}\n\nsub get_feed($) {\n\tmy $feed = shift;\n\n\tif (!defined($feed_cache{$feed})) {\n\t\tmy $file = \"./feeds/$feed.index\";\n\n\t\tclear_packages();\n\t\t-f $file or do {\n\t\t\tprint \"Ignoring feed '$feed' - index missing\\n\";\n\t\t\treturn;\n\t\t};\n\t\tparse_package_metadata($file) or return;\n\t\tmy %target = get_targets(\"./feeds/$feed.targetindex\");\n\n\t\t$feed_cache{$feed} = [ { %package }, { %srcpackage }, { %target }, { %vpackage } ];\n\t}\n\n\t$feed_package = $feed_cache{$feed}->[0];\n\t$feed_src = $feed_cache{$feed}->[1];\n\t$feed_target = $feed_cache{$feed}->[2];\n\t$feed_vpackage = $feed_cache{$feed}->[3];\n}\n\nsub get_installed() {\n\tsystem(\"$mk -s prepare-tmpinfo OPENWRT_BUILD=\");\n\tclear_packages();\n\tparse_package_metadata(\"./tmp/.packageinfo\");\n\t%installed_pkg = %vpackage;\n\t%installed = %srcpackage;\n\t%installed_targets = get_targets(\"./tmp/.targetinfo\");\n}\n\nsub search_feed {\n\tmy $feed = shift;\n\tmy @substr = @_;\n\tmy $display;\n\n\treturn unless @substr > 0;\n\tget_feed($feed);\n\tforeach my $name (sort { lc($a) cmp lc($b) } keys %$feed_package) {\n\t\tmy $pkg = $feed_package->{$name};\n\t\tmy $substr;\n\t\tmy $pkgmatch = 1;\n\n\t\tforeach my $substr (@substr) {\n\t\t\tmy $match;\n\t\t\tforeach my $key (qw(name title description src)) {\n\t\t\t\t$pkg->{$key} and $substr and $pkg->{$key} =~ m/$substr/i and $match = 1;\n\t\t\t}\n\t\t\t$match or undef $pkgmatch;\n\t\t};\n\t\t$pkgmatch and do {\n\t\t\t$display or do {\n\t\t\t\tprint \"Search results in feed '$feed':\\n\";\n\t\t\t\t$display = 1;\n\t\t\t};\n\t\t\tprintf \"\\%-25s\\t\\%s\\n\", $pkg->{name}, $pkg->{title};\n\t\t};\n\t}\n\n\tforeach my $name (sort { lc($a) cmp lc($b) } keys %$feed_target) {\n\t\tmy $target = $feed_target->{$name};\n\t\tmy $targetmatch = 1;\n\n\t\tforeach my $substr (@substr) {\n\t\t\tmy $match;\n\t\t\tforeach my $key (qw(id name description)) {\n\t\t\t\t$target->{$key} and $substr and $target->{$key} =~ m/$substr/i and $match = 1;\n\t\t\t}\n\t\t\t$match or undef $targetmatch;\n\t\t};\n\t\t$targetmatch and do {\n\t\t\t$display or do {\n\t\t\t\tprint \"Search results in feed '$feed':\\n\";\n\t\t\t\t$display = 1;\n\t\t\t};\n\t\t\tprintf \"TARGET: \\%-17s\\t\\%s\\n\", $target->{id}, $target->{name};\n\t\t};\n\t}\n\treturn 0;\n}\n\nsub search {\n\tmy %opts;\n\n\tgetopt('r:', \\%opts);\n\tforeach my $feed (@feeds) {\n\t\tsearch_feed($feed->[1], @ARGV) if (!defined($opts{r}) or $opts{r} eq $feed->[1]);\n\t}\n}\n\nsub list_feed {\n\tmy $feed = shift;\n\n\tget_feed($feed);\n\tforeach my $name (sort { lc($a) cmp lc($b) } keys %$feed_package) {\n\t\tmy $pkg = $feed_package->{$name};\n\t\tif($pkg->{name}) {\n\t\t\tprintf \"\\%-32s\\t\\%s\\n\", $pkg->{name}, $pkg->{title};\n\t\t}\n\t}\n\n\tforeach my $name (sort { lc($a) cmp lc($b) } keys %$feed_target) {\n\t\tmy $target = $feed_target->{$name};\n\t\tif($target->{name}) {\n\t\t\tprintf \"TARGET: \\%-24s\\t\\%s\\n\", $target->{id}, $target->{name};\n\t\t}\n\t}\n\n\treturn 0;\n}\n\nsub list {\n\tmy %opts;\n\n\tgetopts('r:d:nshf', \\%opts);\n\tif ($opts{h}) {\n\t\tusage();\n\t\treturn 0;\n\t}\n\tif ($opts{n}) {\n\t\tforeach my $feed (@feeds) {\n\t\t\tprintf \"%s\\n\", $feed->[1];\n\t\t}\n\t\treturn 0;\n\t}\n\tif ($opts{s}) {\n\t\tforeach my $feed (@feeds) {\n\t\t\tmy $localpath = \"./feeds/$feed->[1]\";\n\t\t\tmy $m = $update_method{$feed->[0]};\n\t\t\tmy $revision;\n\t\t\tif (!-d \"$localpath\" || !$m->{'revision'}) {\n\t\t\t\t$revision = \"X\";\n\t\t\t}\n\t\t\telsif( $m->{'controldir'} && -d \"$localpath/$m->{'controldir'}\" ) {\n\t\t\t\t$revision = `cd '$localpath'; $m->{'revision'}`;\n\t\t\t}\n\t\t\telse {\n\t\t\t\t$revision = \"local\";\n\t\t\t}\n\t\t\tif ($opts{d}) {\n\t\t\t\tprintf \"%s%s%s%s%s%s%s\\n\", $feed->[1], $opts{d}, $feed->[0], $opts{d}, $revision, $opts{d}, join(\", \", @{$feed->[2]});\n\t\t\t}\n\t\t\telsif ($opts{f}) {\n\t\t\t\tmy $uri = join(\", \", @{$feed->[2]});\n\t\t\t\tif ($revision ne \"local\" && $revision ne \"X\") {\n\t\t\t\t\t$uri =~ s/[;^].*//;\n\t\t\t\t\t$uri .= \"^\" . $revision;\n\t\t\t\t}\n\t\t\t\tprintf \"%s %s %s\\n\", $feed->[0], $feed->[1], $uri;\n\t\t\t}\n\t\t\telse {\n\t\t\t\tprintf \"\\%-10s \\%-8s \\%-8s \\%s\\n\", $feed->[1], $feed->[0], $revision, join(\", \", @{$feed->[2]});\n\t\t\t}\n\t\t}\n\t\treturn 0;\n\t}\n\tforeach my $feed (@feeds) {\n\t\tlist_feed($feed->[1], @ARGV) if (!defined($opts{r}) or $opts{r} eq $feed->[1]);\n\t}\n\treturn 0;\n}\n\nsub do_install_src($$) {\n\tmy $feed = shift;\n\tmy $src = shift;\n\n\tmy $path = $src->{makefile};\n\tif ($path) {\n\t\t$path =~ s/\\/Makefile$//;\n\n\t\t-d \"./package/feeds\" or mkdir \"./package/feeds\";\n\t\t-d \"./package/feeds/$feed->[1]\" or mkdir \"./package/feeds/$feed->[1]\";\n\t\tsystem(\"ln -sf ../../../$path ./package/feeds/$feed->[1]/\");\n\t} else {\n\t\twarn \"Package is not valid\\n\";\n\t\treturn 1;\n\t}\n\n\treturn 0;\n}\n\nsub do_install_target($) {\n\tmy $target = shift;\n\tmy $path = $target->{makefile};\n\n\tif ($path) {\n\t\t$path =~ s/\\/Makefile$//;\n\t\tmy $name = $path;\n\t\t$name =~ s/.*\\///;\n\t\tmy $dest = \"./target/linux/feeds/$name\";\n\n\t\t-d \"./target/linux/feeds\" or mkdir \"./target/linux/feeds\";\n\n\t\t-e $dest and do {\n\t\t\twarn \"Path $dest already exists\";\n\t\t\treturn 1;\n\t\t};\n\n\t\tsystem(\"ln -sf ../../../$path ./target/linux/feeds/\");\n\t} else {\n\t\twarn \"Target is not valid\\n\";\n\t\treturn 1;\n\t}\n\n\treturn 0;\n}\n\nsub lookup_src($$) {\n\tmy $feed = shift;\n\tmy $src = shift;\n\n\tforeach my $feed ($feed, @feeds) {\n\t\tnext unless $feed->[1];\n\t\tnext unless $feed_cache{$feed->[1]};\n\t\t$feed_cache{$feed->[1]}->[1]->{$src} and return $feed;\n\t}\n\treturn;\n}\n\nsub lookup_package($$) {\n\tmy $feed = shift;\n\tmy $package = shift;\n\n\tforeach my $feed ($feed, @feeds) {\n\t\tnext unless $feed->[1];\n\t\tnext unless $feed_cache{$feed->[1]};\n\t\t$feed_cache{$feed->[1]}->[3]->{$package} and return $feed;\n\t}\n\treturn;\n}\n\nsub lookup_target($$) {\n\tmy $feed = shift;\n\tmy $target = shift;\n\n\tforeach my $feed ($feed, @feeds) {\n\t\tnext unless $feed->[1];\n\t\tnext unless $feed_cache{$feed->[1]};\n\t\t$feed_cache{$feed->[1]}->[2]->{$target} and return $feed;\n\t}\n\treturn;\n}\n\nsub is_core_src($) {\n\tmy $src = shift;\n\tforeach my $file (\"tmp/info/.packageinfo-$src\", glob(\"tmp/info/.packageinfo-*_$src\")) {\n\t\tnext unless index($file, \"tmp/info/.packageinfo-feeds_\");\n\t\treturn 1 if -s $file;\n\t}\n\treturn 0;\n}\n\nsub install_target {\n\tmy $feed = shift;\n\tmy $name = shift;\n\tmy $force = shift;\n\n\t$feed = lookup_target($feed, $name);\n\tmy $feed_name = $feed->[1];\n\n\t-e \"target/linux/feeds/$name\" and return 0;\n\n\t# enable force flag if feed src line was declared with --force\n\tif (exists($feed->[3]{force})) {\n\t\t$force = 1;\n\t}\n\n\t$feed = $feed_cache{$feed_name}->[2];\n\t$feed or return 0;\n\n\tmy $target = $feed->{$name};\n\t$target or return 0;\n\n\tif (-e \"target/linux/$name\") {\n\t\tif ($force) {\n\t\t\twarn \"Overriding target '$name' with version from '$feed_name'\\n\";\n\t\t} else {\n\t\t\twarn \"WARNING: Not overriding core target '$name'; use -f to force\\n\";\n\t\t\treturn 0;\n\t\t}\n\t} else {\n\t\twarn \"Installing target '$name'\\n\";\n\t}\n\treturn do_install_target($target);\n}\n\nsub install_src {\n\tmy $feed = shift;\n\tmy $name = shift;\n\tmy $force = shift;\n\tmy $ret = 0;\n\n\tmy $select_feed = lookup_src($feed, $name);\n\tunless ($select_feed) {\n\t\t$installed{$name} and return 0;\n\t\t$feed_src->{$name} or warn \"WARNING: No feed for source package '$name' found\\n\";\n\t\treturn 0;\n\t}\n\n\t# switch to the metadata for the selected feed\n\tget_feed($select_feed->[1]);\n\tmy $src = $feed_src->{$name} or return 1;\n\n\t# enable force flag if feed src line was declared with --force\n\tif (exists($select_feed->[3]{force})) {\n\t\t$force = 1;\n\t}\n\n\t# If it's a core package and we don't want to override, just return\n\tmy $override = 0;\n\tif (is_core_src($name)) {\n\t\tif (!$force) {\n\t\t\tif ($name ne \"toolchain\" && $name ne \"linux\") {\n\t\t\t\twarn \"WARNING: Not overriding core package '$name'; use -f to force\\n\";\n\t\t\t}\n\t\t\treturn 0;\n\t\t}\n\t\t$override = 1;\n\t}\n\n\tif ($installed{$name}) {\n\t\t# newly installed packages set the source package to 1\n\t\treturn 0 if ($installed{$name} == 1);\n\t\treturn 0 unless ($override);\n\t}\n\n\t$installed{$name} = 1;\n\tforeach my $pkg (@{$src->{packages}}) {\n\t\tforeach my $vpkg (@{$pkg->{provides}}) {\n\t\t\t$installed_pkg{$vpkg} = 1;\n\t\t}\n\t}\n\n\tif ($override) {\n\t\twarn \"Overriding core package '$name' with version from $select_feed->[1]\\n\";\n\t} else {\n\t\twarn \"Installing package '$name' from $select_feed->[1]\\n\";\n\t}\n\n\tdo_install_src($select_feed, $src) == 0 or do {\n\t\twarn \"failed.\\n\";\n\t\treturn 1;\n\t};\n\n\t# install all dependencies referenced from the source package\n\tforeach my $dep (\n\t\t@{$src->{builddepends}},\n\t\t@{$src->{'builddepends/host'}},\n\t) {\n\t\tnext if $dep =~ /@/;\n\t\t$dep =~ s/^.+://;\n\t\t$dep =~ s/\\/.+$//;\n\t\tnext unless $dep;\n\t\tinstall_src($feed, $dep, 0) == 0 or $ret = 1;\n\t}\n\n\tforeach my $pkg (@{$src->{packages}}) {\n\t\tforeach my $dep (@{$pkg->{depends}}) {\n\t\t\tnext if $dep =~ /@/;\n\t\t\t$dep =~ s/^\\+//;\n\t\t\t$dep =~ s/^.+://;\n\t\t\tnext unless $dep;\n\t\t\tinstall_package($feed, $dep, 0) == 0 or $ret = 1;\n\t\t}\n\t}\n\n\treturn $ret;\n}\n\nsub install_package {\n\tmy $feed = shift;\n\tmy $name = shift;\n\tmy $force = shift;\n\n\tmy $select_feed = lookup_package($feed, $name);\n\tunless ($select_feed) {\n\t\t$installed_pkg{$name} and return 0;\n\t\t$feed_vpackage->{$name} or warn \"WARNING: No feed for package '$name' found\\n\";\n\t\treturn 0;\n\t}\n\n\t# switch to the metadata for the selected feed\n\tget_feed($select_feed->[1]);\n\tmy $pkg = $feed_vpackage->{$name} or return 1;\n\treturn install_src($feed, $pkg->[0]{src}{name}, $force);\n}\n\nsub install_target_or_package {\n\tmy $feed = shift;\n\tmy $name = shift;\n\tmy $force = shift;\n\n\tlookup_target($feed, $name) and do {\n\t\treturn install_target($feed, $name, $force);\n\t};\n\n\tlookup_src($feed, $name) and do {\n\t\treturn install_src($feed, $name, $force);\n\t};\n\n\treturn install_package($feed, $name, $force);\n}\n\nsub refresh_config {\n\tmy $default = shift;\n\n\t# Don't create .config if it doesn't already exist so that making a\n\t# config only occurs when the user intends it do (however we do\n\t# want to refresh an existing config).\n\treturn if not (-e '.config');\n\n\t# workaround for timestamp check\n\tsystem(\"rm -f tmp/.packageinfo\");\n\n\t# refresh the config\n\tif ($default) {\n\t\tsystem(\"$mk oldconfig CONFDEFAULT=\\\"$default\\\" Config.in >/dev/null 2>/dev/null\");\n\t} else {\n\t\tsystem(\"$mk defconfig Config.in >/dev/null 2>/dev/null\");\n\t}\n}\n\nsub install {\n\tmy $name;\n\tmy %opts;\n\tmy $feed;\n\tmy $ret = 0;\n\n\tgetopts('ap:d:fh', \\%opts);\n\n\tif ($opts{h}) {\n\t\tusage();\n\t\treturn 0;\n\t}\n\n\tget_installed();\n\n\tforeach my $f (@feeds) {\n\t\t# fetch all feeds\n\t\tget_feed($f->[1]);\n\n\t\t# look up the preferred feed\n\t\t$opts{p} and $f->[1] eq $opts{p} and $feed = $f;\n\t}\n\n\tif($opts{a}) {\n\t\tforeach my $f (@feeds) {\n\t\t\tif (!defined($opts{p}) or $opts{p} eq $f->[1]) {\n\t\t\t\tprintf \"Installing all packages from feed %s.\\n\", $f->[1];\n\t\t\t\tget_feed($f->[1]);\n\t\t\t\tforeach my $name (sort { lc($a) cmp lc($b) } keys %$feed_src) {\n\t\t\t\t\tinstall_src($feed, $name, exists($opts{f})) == 0 or $ret = 1;\n\t\t\t\t\tget_feed($f->[1]);\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t} else {\n\t\twhile ($name = shift @ARGV) {\n\t\t\tinstall_target_or_package($feed, $name, exists($opts{f})) == 0 or $ret = 1;\n\t\t}\n\t}\n\n\t# workaround for timestamp check\n\n\t# set the defaults\n\tif ($opts{d} and $opts{d} =~ /^[ymn]$/) {\n\t\trefresh_config($opts{d});\n\t}\n\n\treturn $ret;\n}\n\nsub uninstall_target($) {\n\tmy $dir = shift;\n\tmy $name = $dir;\n\t$name =~ s/.*\\///g;\n\n\tmy $dest = readlink $dir;\n\treturn unless $dest =~ /..\\/..\\/feeds/;\n\twarn \"Uninstalling target '$name'\\n\";\n\tunlink \"$dir\";\n}\n\nsub uninstall {\n\tmy %opts;\n\tmy $name;\n\tmy $uninstall;\n\n\tgetopts('ah', \\%opts);\n\n\tif ($opts{h}) {\n\t\tusage();\n\t\treturn 0;\n\t}\n\n\tif ($opts{a}) {\n\t\tsystem(\"rm -rvf ./package/feeds\");\n\t\tforeach my $dir (glob \"target/linux/*\") {\n\t\t\tnext unless -l $dir;\n\t\t\tuninstall_target($dir);\n\t\t}\n\t\t$uninstall = 1;\n\t} else {\n\t\tif($#ARGV == -1) {\n\t\t\twarn \"WARNING: no package to uninstall\\n\";\n\t\t\treturn 0;\n\t\t}\n\t\tget_installed();\n\t\twhile ($name = shift @ARGV) {\n\t\t\tmy $target = \"target/linux/feeds/$name\";\n\t\t\t-l \"$target\" and do {\n\t\t\t\tuninstall_target($target);\n\t\t\t\t$uninstall = 1;\n\t\t\t\tnext;\n\t\t\t};\n\n\t\t\tmy $pkg = $installed{$name};\n\t\t\t$pkg or do {\n\t\t\t\twarn \"WARNING: $name not installed\\n\";\n\t\t\t\tnext;\n\t\t\t};\n\t\t\t$pkg->{src} and $name = $pkg->{src}{name};\n\t\t\twarn \"Uninstalling package '$name'\\n\";\n\t\t\tsystem(\"rm -f ./package/feeds/*/$name\");\n\t\t\t$uninstall = 1;\n\t\t}\n\t}\n\t$uninstall and refresh_config();\n\treturn 0;\n}\n\nsub update_feed($$$$)\n{\n\tmy $type=shift;\n\tmy $name=shift;\n\tmy $src=shift;\n\tmy $force_update=shift;\n\tmy $force_relocate=update_location( $name, \"@$src\" );\n\tmy $rv=0;\n\n\tif( $force_relocate ) {\n\t\twarn \"Source of feed $name has changed, replacing copy\\n\";\n\t}\n\t$update_method{$type} or do {\n\t\twarn \"Unknown type '$type' in feed $name\\n\";\n\t\treturn 1;\n\t};\n\n\tmy $failed = 1;\n\tforeach my $feedsrc (@$src) {\n\t\twarn \"Updating feed '$name' from '$feedsrc' ...\\n\";\n\t\tif (update_feed_via($type, $name, $feedsrc, $force_relocate, $force_update) != 0) {\n\t\t\tif ($force_update) {\n\t\t\t\t$rv=1;\n\t\t\t\t$failed=0;\n\t\t\t\twarn \"failed, ignore.\\n\";\n\t\t\t\tnext;\n\t\t\t}\n\t\t\tlast;\n\t\t}\n\t\t$failed = 0;\n\t}\n\t$failed and do {\n\t\twarn \"failed.\\n\";\n\t\treturn 1;\n\t};\n\treturn $rv;\n}\n\nsub update {\n\tmy %opts;\n\tmy %argv_feeds;\n\tmy $failed=0;\n\n\t$ENV{SCAN_COOKIE} = $$;\n\t$ENV{OPENWRT_VERBOSE} = 's';\n\n\tgetopts('ahif', \\%opts);\n\t%argv_feeds = map { $_ => 1 } @ARGV;\n\n\tif ($opts{h}) {\n\t\tusage();\n\t\treturn 0;\n\t}\n\n\t-d \"feeds\" or do {\n\t\t\tmkdir \"feeds\" or die \"Unable to create the feeds directory\";\n\t\t};\n\n\tmy @index_feeds;\n\tforeach my $feed (@feeds) {\n\t\tmy ($type, $name, $src) = @$feed;\n\t\tnext unless $#ARGV == -1 or $opts{a} or $argv_feeds{$name};\n\t\tif (not $opts{i}) {\n\t\t\tupdate_feed($type, $name, $src, $opts{f}) == 0 or $failed=1;\n\t\t}\n\t\tpush @index_feeds, $name;\n\t}\n\tforeach my $name (@index_feeds) {\n\t\twarn \"Create index file './feeds/$name.index' \\n\";\n\t\tupdate_index($name) == 0 or do {\n\t\t\twarn \"failed.\\n\";\n\t\t\t$failed=1;\n\t\t};\n\t}\n\n\trefresh_config();\n\n\treturn $failed;\n}\n\nsub feed_config() {\n\tforeach my $feed (@feeds) {\n\t\tmy $installed = (-f \"feeds/$feed->[1].index\");\n\n\t\tprintf \"\\tconfig FEED_%s\\n\", $feed->[1];\n\t\tprintf \"\\t\\ttristate \\\"Enable feed %s\\\"\\n\", $feed->[1];\n\t\tprintf \"\\t\\tdepends on PER_FEED_REPO\\n\";\n\t\tprintf \"\\t\\tdefault y\\n\" if $installed;\n\t\tprintf \"\\t\\thelp\\n\";\n\t\tprintf \"\\t\\t Enable the \\\\\\\"%s\\\\\\\" feed in opkg distfeeds.conf.\\n\", $feed->[1];\n\t\tprintf \"\\t\\t Say M to add the feed commented out.\\n\";\n\t\tprintf \"\\n\";\n\t}\n\n\treturn 0;\n}\n\nsub usage() {\n\tprint <<EOF;\nUsage: $0 <command> [options]\n\nCommands:\n\tlist [options]: List feeds, their content and revisions (if installed)\n\tOptions:\n\t    -n :            List of feed names.\n\t    -s :            List of feed names and their URL.\n\t    -r <feedname>:  List packages of specified feed.\n\t    -d <delimiter>: Use specified delimiter to distinguish rows (default: spaces)\n\t    -f :            List feeds in feeds.conf compatible format (when using -s).\n\n\tinstall [options] <package>: Install a package\n\tOptions:\n\t    -a :           Install all packages from all feeds or from the specified feed using the -p option.\n\t    -p <feedname>: Prefer this feed when installing packages.\n\t    -d <y|m|n>:    Set default for newly installed packages.\n\t    -f :           Install will be forced even if the package exists in core OpenWrt (override)\n\n\tsearch [options] <substring>: Search for a package\n\tOptions:\n\t    -r <feedname>: Only search in this feed\n\n\tuninstall -a|<package>: Uninstall a package\n\tOptions:\n\t    -a :           Uninstalls all packages.\n\n\tupdate -a|<feedname(s)>: Update packages and lists of feeds in feeds.conf .\n\tOptions:\n\t    -a :           Update all feeds listed within feeds.conf. Otherwise the specified feeds will be updated.\n\t    -i :           Recreate the index only. No feed update from repository is performed.\n\t    -f :           Force updating feeds even if there are changed, uncommitted files.\n\n\tclean:             Remove downloaded/generated files.\n\nEOF\n\texit(1);\n}\n\nmy %commands = (\n\t'list' => \\&list,\n\t'update' => \\&update,\n\t'install' => \\&install,\n\t'search' => \\&search,\n\t'uninstall' => \\&uninstall,\n\t'feed_config' => \\&feed_config,\n\t'clean' => sub {\n\t\tsystem(\"rm -rf ./feeds ./package/feeds ./target/linux/feeds\");\n\t}\n);\n\nmy $arg = shift @ARGV;\n$arg or usage();\nparse_config;\nforeach my $cmd (keys %commands) {\n\t$arg eq $cmd and do {\n\t\texit(&{$commands{$cmd}}());\n\t};\n}\nusage();\n"
  },
  {
    "path": "scripts/fixup-makefile.pl",
    "content": "#!/usr/bin/env perl\nuse strict;\n\nmy $error;\nmy %state;\n\nsub usage() {\ndie <<EOF;\nUsage: $0 <file> <command> [<arguments>]\n\nCommands:\nadd-hash <variable> <value>\nfix-hash <variable> <value>\nrename-var <variable> <name>\n\nEOF\n}\n\nsub set_var($) {\n\tmy $var = shift;\n\n\t$state{var} = $var;\n\tif ($var =~ /(.*):(.*)/) {\n\t\t$state{template} = $1;\n\t\t$state{var} = $2;\n\t\t$state{related_var} = \"URL\";\n\t} else {\n\t\t$state{context} = 1;\n\t\t$state{related_var} = \"PKG_SOURCE_URL\";\n\t}\n}\n\nmy %check_command = (\n\t\"add-hash\" => sub {\n\t\tset_var($ARGV[0]);\n\n\t\t$state{value} = $ARGV[1];\n\t\tlength($ARGV[1]) == 64 or die \"Invalid hash value\\n\";\n\t},\n\t\"fix-hash\" => sub {\n\t\tset_var($ARGV[0]);\n\n\t\t$state{value} = $ARGV[1];\n\t\t$state{prev_value} = $ARGV[2];\n\n\t\tlength($ARGV[1]) == 64 or die \"Invalid hash value\\n\";\n\t},\n\t\"rename-var\" => sub {\n\t\tset_var($ARGV[0]);\n\t\t$state{new_var} = $ARGV[1];\n\t\t$state{new_var} =~ s/.*://g;\n\t},\n);\n\nsub check_context($) {\n\tmy $line = shift;\n\treturn unless $state{template};\n\n\t$state{next} and do {\n\t\t$state{context} = 1;\n\t\tundef $state{next};\n\t\treturn;\n\t};\n\n\tif (not $state{context}) {\n\t\t$line =~ /^\\s*define\\s+$state{template}/ and $state{next} = 1;\n\t} else {\n\t\t$line =~ /^\\s*endef/ and do {\n\t\t\t$state{done} = 1;\n\t\t\tundef $state{context};\n\t\t}\n\t}\n}\n\nmy %commands = (\n\t\"add-hash\" => sub {\n\t\tmy $line = shift;\n\t\tcheck_context($line);\n\t\treturn $line unless $state{context};\n\n\t\t# skip existing hash variable\n\t\treturn \"\" if $line =~ /^(\\s*)$state{var}(\\s*):?=(\\s*)(.*)\\n/;\n\n\t\t# insert md5sum after related variable\n\t\treturn $line unless $line =~ /^(\\s*)$state{related_var}(\\s*):?=(\\s*)(.*)\\n/;\n\t\treturn \"$line$1$state{var}$2:=$3$state{value}\\n\";\n\t},\n\t\"fix-hash\" => sub {\n\t\tmy $line = shift;\n\t\tcheck_context($line);\n\t\treturn $line unless $state{context};\n\t\treturn $line unless $line =~ /^(\\s*)$state{var}(\\s*):?=(\\s*)(.*)$state{prev_value}(.*)\\n/;\n\t\t$state{done} = 1;\n\t\t$4 =~ /\\$/ and do {\n\t\t\twarn \"$state{var} contains a reference to another variable, can't fix automatically\\n\";\n\t\t\treturn $line;\n\t\t};\n\t\treturn \"$1$state{var}$2:=$3$state{value}\\n\";\n\t},\n\t\"rename-var\" => sub {\n\t\tmy $line = shift;\n\t\tcheck_context($line);\n\t\treturn $line unless $state{context};\n\t\treturn $line unless $line =~ /^(\\s*)$state{var}(\\s*:?=.*)\\n/;\n\t\treturn \"$1$state{new_var}$2\\n\";\n\t},\n);\n\nmy $file = shift @ARGV;\nmy $command = shift @ARGV;\n\n($file and $command and $check_command{$command}) or usage;\n&{$check_command{$command}}();\n\n-f $file or die \"File $file not found\\n\";\n\nopen IN, \"<${file}\" or die \"Cannot open input file\\n\";\nopen OUT, \">${file}.new\" or die \"Cannot open output file\\n\";\n\nmy $cmd = $commands{$command};\nwhile (my $line = <IN>) {\n\t$line = &$cmd($line) unless $state{done};\n\tprint OUT $line;\n\tlast if $error;\n}\n\nclose OUT;\nclose IN;\n\n$error and do {\n\tunlink \"${file}.new\";\n\texit 1;\n};\n\nrename \"${file}.new\", \"$file\";\n"
  },
  {
    "path": "scripts/flashing/adam2flash-502T.pl",
    "content": "#!/usr/bin/env perl\n#\n#   D-Link DSL-502T flash utility\n#\n#   Copyright (c) 2007 Oliver Jowett <oliver@opencloud.com>\n#\n#   Based on adam2flash.pl for the D-Link DSL-G6x4T, which is:\n#   Copyright (C) 2005 Felix Fietkau <mailto@nbd.name>\n#   based on fbox recovery util by Enrik Berkhan\n#\n#   This program is free software; you can redistribute it and/or modify\n#   it under the terms of the GNU General Public License as published by\n#   the Free Software Foundation; either version 2 of the License, or\n#   (at your option) any later version.\n#\n#   This program is distributed in the hope that it will be useful,\n#   but WITHOUT ANY WARRANTY; without even the implied warranty of\n#   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n#   GNU General Public License for more details.\n#\n#   You should have received a copy of the GNU General Public License\n#   along with this program; if not, write to the Free Software\n#   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA\n#\n\n# The default DSL-502T mtd map looks like this:\n#\n# mtd0 0x90091000,0x903f0000    # filesystem\n# mtd1 0x90010090,0x90091000    # kernel\n# mtd2 0x90000000,0x90010000    # bootloader - DO NOT MODIFY\n# mtd3 0x903f0000,0x90400000    # config space - DO NOT MODIFY\n# mtd4 0x90010000,0x903f0000    # firmware signature + kernel + filesystem, used to flash new firmware\n#\n# i.e. the flash layout is:\n#\n# 90000000-9000FFFF mtd2 bootloader\n# 90010000-9001008F ---- firmware signature )\n# 90010090-90090FFF mtd1 kernel             ) mtd4 spans these three regions\n# 90091000-903EFFFF mtd0 filesystem         )\n# 903F0000-903FFFFF mtd3 config space\n#\n# The ADAM2 bootloader uses the mtd1 settings to find the start of the image to boot.\n# The image to load contains information about the loadable size of the image. If ADAM2 sees\n# that the image appears to extend beyond the end of mtd1, it will refuse to load it. On\n# the DSL-502T, this manifests as the USB light blinking rapidly on boot.\n#\n# The OpenWRT kernel does not follow quite the same layout:\n#  (a) it does not have a 0x90-byte firmware signature prefix\n#  (b) it is larger than the default mtd1 size\n#\n# (a) would be avoidable (build a custom image with a 0x90-byte prefix) but (b) is unavoidable.\n# So we *have* to change mtd1. The simplest thing to do seems to make it span all of\n# the flashable area, producing this layout:\n#\n# mtd0 0x90091000,0x903f0000    # filesystem\n# mtd1 0x90010000,0x903f0000    # kernel (CHANGED)\n# mtd2 0x90000000,0x90010000    # bootloader - DO NOT MODIFY\n# mtd3 0x903f0000,0x90400000    # config space - DO NOT MODIFY\n# mtd4 0x90010000,0x903f0000    # kernel + filesystem, used to flash new firmware\n#\n# *** NOTE NOTE NOTE NOTE ***\n#\n# /dev/mtd0 .. /dev/mtd4 when using OpenWRT do **NOT** correspond to the ADAM2 mtd0-4 settings!\n# Instead, OpenWRT scans the MTD itself and determines its own boundaries which are arranged\n# quite differently to ADAM2. It will look something like this, see dmsg on boot:\n#\n# (/dev/mtd0) 0x00000000-0x00010000 : \"loader\"        # Bootloader, read-only\n# (/dev/mtd1) 0x003f0000-0x00400000 : \"config\"        # Config space\n# (/dev/mtd2) 0x00010000-0x003f0000 : \"linux\"         # Firmware area (kernel + root fs + JFFS area)\n# (/dev/mtd3) 0x000d0d58-0x003f0000 : \"rootfs\"        # Root FS, starts immediately after kernel\n# (/dev/mtd4) 0x00280000-0x003f0000 : \"rootfs_data\"   # If rootfs is squashfs, start of JFFS area.\n#\n# All of those boundaries are autodetected by examining the data in flash.\n#\n# *** NOTE NOTE NOTE NOTE ***\n\nuse IO::Socket::INET;\nuse Socket;\nuse strict;\nuse warnings;\n\nsub usage() {\n\tprint STDERR \"Usage: $0 <ip> [-setmtd1] [-noflash] [firmware.bin]\\n\\n\";\n\tprint STDERR \"Acquires the ADAM2 bootloader of a D-Link DSL-504T at <ip>\\n\";\n\tprint STDERR \"Power off the device, start this script, then power it on.\\n\";\n\tprint STDERR \"<ip> may be any spare address on the local subnet.\\n\\n\";\n\tprint STDERR \"If a firmware file is specified, MTD settings are verified and\\n\";\n\tprint STDERR \"then the firmware is written to the router's flash.\\n\";\n\tprint STDERR \"The firmware type (D-Link or OpenWRT) is automatically detected.\\n\\n\";\n\tprint STDERR \"  -setmtd1  update mtd1 if it is not the appropriate value for this firmware\\n\";\n\tprint STDERR \"  -noflash  does normal checks, updates mtd1 if requested, but does not actually write firmware\\n\\n\";\n\texit 0;\n}\n\nmy $ip = shift @ARGV;\n$ip and $ip =~ /\\d{1,3}\\.\\d{1,3}\\.\\d{1,3}\\.\\d{1,3}/ or usage();\n\nmy $probe = IO::Socket::INET->new(Proto => 'udp',\n                                  Broadcast => 1,\n                                  LocalPort => 5035) or die \"socket: $!\";\nmy $setip = unpack(\"N\", inet_aton($ip));\n$setip > 0 or usage();\n\nmy @packets;\nforeach my $ver ([18, 1], [22, 2]) {\n\tpush @packets, pack(\"vCCVNV\", 0, @$ver, 1, $setip, 0);\n}\nprint STDERR \"Looking for device: \";\nmy $broadcast = sockaddr_in(5035, INADDR_BROADCAST);\nmy $scanning;\nmy $box;\n\n$SIG{\"ALRM\"} = sub {\n\treturn if --$scanning <= 0;\n\tforeach my $packet (@packets) {\n\t\t$probe->send($packet, 0, $broadcast);\n\t}\n\tprint STDERR \".\";\n};\n\n$scanning = 15;\nforeach my $packet (@packets) {\n\t$probe->send($packet, 0, $broadcast);\n}\nprint STDERR \".\";\n\nwhile($scanning) {\n\tmy $reply;\n\n\talarm(1);\n\tif (my $peer = $probe->recv($reply, 16)) {\n\t\tnext if (length($reply) < 16);\n\t\tmy ($port, $addr) = sockaddr_in($peer);\n\t\tmy ($major, $minor1, $minor2, $code, $addr2) = unpack(\"vCCVV\", $reply);\n\t\t$addr2 = pack(\"N\", $addr2);\n\t\tif ($code == 2) {\n\t\t\t$scanning = 0;\n\t\t\tprintf STDERR \" found!\\nADAM2 version $major.$minor1.$minor2 at %s (%s)\\n\", inet_ntoa($addr), inet_ntoa($addr2);\n\t\t\t$box = inet_ntoa($addr);\n\t\t}\n\t}\n}\n\n$box or die \" not found!\\n\";\n\nalarm(0);\n\n{\n\tpackage ADAM2FTP;\n\tuse base qw(Net::FTP);\n\t\n\t# ADAM2 requires upper case commands, some brain dead firewall doesn't ;-)\n\tsub _USER {\n\t\tshift->command(\"USER\",@_)->response()\n\t}\n\t\n\tsub _GETENV {\n\t\tmy $ftp = shift;\n\t\tmy ($ok, $name, $value);\n\t\t\n\t\t$ftp->command(\"GETENV\",@_);\n\t\t\twhile(length($ok = $ftp->response()) < 1) {\n\t\t\tmy $line = $ftp->getline();\n\t\t\tunless (defined($value)) {\n\t\t\t\tchomp($line);\n\t\t\t\t($name, $value) = split(/\\s+/, $line, 2);\n\t\t\t}\n\t\t}\n\t\t$ftp->debug_print(0, \"getenv: $value\\n\")\n\t\tif $ftp->debug();\n\t\treturn $value;\n\t}\n\t\n\tsub getenv {\n\t\tmy $ftp = shift;\n\t\tmy $name = shift;\n\t\treturn $ftp->_GETENV($name);\n\t}\n\t\n\tsub _REBOOT {\n\t\tshift->command(\"REBOOT\")->response() == Net::FTP::CMD_OK\n\t}\n\t\n\tsub reboot {\n\t\tmy $ftp = shift;\n\t\t$ftp->_REBOOT;\n\t\t$ftp->close;\n\t}\n}\n\nmy $file;\nmy $arg;\nmy $noflash = 0;\nmy $setmtd1 = 0;\nwhile ($arg = shift @ARGV) {\n  if ($arg eq \"-noflash\") { $noflash = 1; }\n  elsif ($arg eq \"-setmtd1\") { $setmtd1 = 1; }\n  else { $file = $arg; }\n}\n\nif (!$file) {\n  print STDERR \"No firmware file specified, exiting.\\n\";\n  exit 0;\n}\n\n#\n# Firmware checks\n#\n\nopen FILE, \"<$file\" or die \"can't open firmware file\\n\";\n\n# D-Link firmware starts with \"MTD4\" little-endian, then has an image header at 0x90\n# OpenWRT firmware just starts with an image header at 0x00\n\nmy $signature;\nmy $sbytes = read FILE, $signature, 4;\n($sbytes == 4) or die \"can't read firmware signature: $!\";\n\nmy $expectedmtd4 = \"0x90010000,0x903f0000\";\nmy $fwtype;\nmy $expectedmtd1;\n\nif ($signature eq \"4DTM\") {\n  seek FILE, 0x90, 0 or die \"can't read firmware signature: $!\";\n  $sbytes = read FILE, $signature, 4;\n  ($sbytes == 4) or die \"can't read firmware signature: $!\";\n  if ($signature eq \"\\x42\\xfa\\xed\\xfe\") {\n    $fwtype = \"D-Link (little-endian)\";\n    $expectedmtd1 = \"0x90010090,0x90091000\";\n  } elsif ($signature eq \"\\xde\\xad\\xbe\\x42\") {\n    $fwtype = \"D-Link (big-endian)\";\n    $expectedmtd1 = \"0x90010090,0x90091000\";\n  }\n} elsif ($signature eq \"\\x42\\xfa\\xed\\xfe\") {\n  $fwtype = \"OpenWRT (little-endian)\";\n  $expectedmtd1 = \"0x90010000,0x903f0000\";\n} elsif ($signature eq \"\\xde\\xad\\xbe\\x42\") {\n  $fwtype = \"OpenWRT (big-endian)\";\n  $expectedmtd1 = \"0x90010000,0x903f0000\";\n}\n\n$fwtype or die \"Unknown firmware signature (are you sure that's the right firmware?)\";\nprint STDERR \"Firmware type: $fwtype\\n\";\n\n#\n# Bootloader login\n#\n\nprint STDERR \"logging into ADAM2 bootloader.. \";\nmy $ftp = ADAM2FTP->new($box, Debug => 0, Timeout => 600) or die \"can't open control connection\\n\";\n$ftp->login(\"adam2\", \"adam2\") or die \"can't login\\n\";\nprint STDERR \"ok.\\n\";\n\n#\n# Hardware checks\n#\n\nprint STDERR \"checking hardware.. \";\nmy $prd = $ftp->getenv(\"ProductID\");\nmy $usb = $ftp->getenv(\"usb_prod\");\nprint STDERR \"$prd / $usb.\\n\";\n($prd eq \"AR7RD\" || $prd eq \"AR7DB\") or die \"doesn't look like a DSL-502T?\";\n($usb eq \"DSL-502T\") or die \"doesn't look like a DSL-502T?\";\n\n#\n# MTD checks and update\n#\n\nprint STDERR \"checking MTD settings.. \";\n\nmy $mtd4 = $ftp->getenv(\"mtd4\");\n($mtd4 eq $expectedmtd4) or die \"MTD4 was not as expected (should be '$expectedmtd4', was '$mtd4'). Cowardly refusing to do anything about it!\";\n\n# check MTD1 setting and update if needed\nmy $mtd1 = $ftp->getenv(\"mtd1\");\nif ($mtd1 ne $expectedmtd1) {\n  die \"MTD1 was not as expected (should be '$expectedmtd1', was '$mtd1'). Run with -setmtd1 to reset mtd1\" unless ($setmtd1);\n  print STDERR \"Setting mtd1.. \";\n  ($ftp->command(\"SETENV\",\"mtd1,$expectedmtd1\")->response() == Net::FTP::CMD_OK) or die \"can't set mtd1\";\n  $file = shift @ARGV;\n}\n\nprint STDERR \"ok.\\n\";\n\n#\n# Firmware size check\n#\n\nmy $fwsize = (stat(FILE))[7];\nprintf STDERR \"Firmware size: 0x%08x\\n\", $fwsize;\nmy $flashsize;\n$mtd4 =~ /^(0x\\w+),(0x\\w+)$/ and $flashsize = hex($2) - hex($1);\nprintf STDERR \"Available flash space: 0x%08x\\n\", $flashsize;\ndie \"firmware is too large\" if ($flashsize < $fwsize);\n\n#\n# Flash it!\n#\n\nif ($noflash) {\n  print STDERR \"Not flashing firmware as -noflash was specified.\\n\";\n  exit 0;\n}\n\nseek FILE, 0, 0, or die \"can't seek in firmware: $!\";\n\nprint STDERR \"Preparing to flash.. \";\n($ftp->command(\"MEDIA FLSH\")->response() == Net::FTP::CMD_OK) or die \"can't set MEDIA FLSH\";\n$ftp->binary() or die \"can't set binary mode\";\nprint STDERR \"ok.\\n\";\nprint STDERR \"Erasing flash and establishing data connection (this may take a while): \";\n\nmy $dc = $ftp->stor(\"fs mtd4\");\n$dc or die \"can't open data connection: $!\\n\";\nprint STDERR \"ok.\\n\";\n\nprint STDERR \"Writing firmware: \";\nwhile ($fwsize > 0) {\n\tmy $buffer;\n\tmy $len = ($fwsize > 1024 ? 1024 : $fwsize);\n\n\tmy $rbytes = read FILE, $buffer, $len;\n\t($rbytes < 0) and die \"read error on firmware file: $!\";\n\t($rbytes == $len) or die \"short read on firmware file ($rbytes < $len)\";\n\n\tmy $wbytes = $dc->write($buffer, $len, 600);\n\t($wbytes < 0) and die \"write error on FTP data connection: $!\";\n\t($rbytes == $wbytes) or die \"short write on FTP data connection ($wbytes < $rbytes)\";\n\n\t$fwsize -= $len;\n\tprint STDERR \".\";\n}\n\n$dc->close();\nprint STDERR \" done.\\n\";\n\n#\n# Reboot\n#\n\nprint STDERR \"Rebooting device.\\n\";\n$ftp->reboot();\n"
  },
  {
    "path": "scripts/flashing/adam2flash-fritzbox.pl",
    "content": "#!/usr/bin/env perl\n#\n#   D-Link DSL-G6x4T flash utility\n#\n#   Copyright (C) 2005 Felix Fietkau <mailto@nbd.name>\n#   based on fbox recovery util by Enrik Berkhan\n#\n#   This program is free software; you can redistribute it and/or modify\n#   it under the terms of the GNU General Public License as published by\n#   the Free Software Foundation; either version 2 of the License, or\n#   (at your option) any later version.\n#\n#   This program is distributed in the hope that it will be useful,\n#   but WITHOUT ANY WARRANTY; without even the implied warranty of\n#   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n#   GNU General Public License for more details.\n#\n#   You should have received a copy of the GNU General Public License\n#   along with this program; if not, write to the Free Software\n#   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA\n#\n\nuse IO::Socket::INET;\nuse IO::Select;\nuse Socket;\nuse strict;\nuse warnings;\n\nsub usage() {\n\tprint STDERR \"Usage: $0 <ip> [firmware.bin]\\n\\n\";\n\texit 0;\n}\n\nmy $ip = shift @ARGV;\n$ip and $ip =~ /\\d{1,3}\\.\\d{1,3}\\.\\d{1,3}\\.\\d{1,3}/ or usage();\n\nmy $setip = unpack(\"N\", inet_aton($ip));\n$setip > 0 or usage();\n\nmy @packets;\nforeach my $ver ([18, 1], [22, 2]) {\n\tpush @packets, pack(\"vCCVNV\", 0, @$ver, 1, $setip, 0);\n}\nprint STDERR \"Looking for device: \";\nmy $scanning;\nmy $box;\n\nmy $probe = IO::Socket::INET->new(Proto => 'udp',\n                                  Broadcast => 1,\n                                  LocalAddr => $ip,\n                                  LocalPort => 5035) or die \"socket: $!\";\nmy $sel = IO::Select->new($probe);\nmy $packet = pack(\"vCCVNV\", 0, 18, 1, 1, 0, 0);\nmy $broadcast = sockaddr_in(5035, INADDR_BROADCAST);\n\n$probe->send($packet, 0, $broadcast);\n\n\nscan_again:\nprint \"Looking for Fritz!Box \";\nmy @boxes = ();\nmy $peer;\n$scanning = 100;\nprint \"o\";\nwhile($scanning) {\n  my $reply;\n  my @ready;\n\n  if (@ready = $sel->can_read(0.2)) {\n    $peer = $probe->recv($reply, 16);\n    next if (length($reply) < 16);\n    my ($port, $addr) = sockaddr_in($peer);\n    my ($major, $minor1, $minor2, $code, $addr2) = unpack(\"vCCVV\", $reply);\n    $addr2 = pack(\"N\", $addr2);\n    if ($code == 2) {\n      print \"O\";\n      push @boxes, [$major, $minor1, $minor2, $addr, $addr2];\n      $scanning = 2 if ($scanning > 2);\n    }\n  } else {\n    $scanning--;\n    if (scalar @boxes == 0) {\n      $probe->send($packet, 0, $broadcast);\n      print \"o\";\n    } else {\n      print \".\";\n    }\n  }\n}\n\nif (scalar @boxes == 0) {\n  print \" none found, giving up.\\n\";\n  exit 1;\n} else {\n  print \" found!\\n\";\n}\n\n{\n  package ADAM2FTP;\n  use base qw(Net::FTP);\n  # ADAM2 requires upper case commands, some brain dead firewall doesn't ;-)\n  sub _USER { shift->command(\"USER\",@_)->response() }\n  sub _PASV { shift->command(\"P\\@SW\")->response() == Net::FTP::CMD_OK }\n  sub _GETENV {\n    my $ftp = shift;\n    my ($ok, $name, $value);\n\n    $ftp->command(\"GETENV\",@_);\n    while(length($ok = $ftp->response()) < 1) {\n      my $line = $ftp->getline();\n      unless (defined($value)) {\n        chomp($line);\n        ($name, $value) = split(/\\s+/, $line, 2);\n      }\n    }\n    $ftp->debug_print(0, \"getenv: $value\\n\")\n      if $ftp->debug();\n    return $value;\n  }\n  sub getenv {\n    my $ftp = shift;\n    my $name = shift;\n    return $ftp->_GETENV($name);\n  }\n  sub _REBOOT { shift->command(\"REBOOT\")->response() == Net::FTP::CMD_OK }\n  sub reboot {\n    my $ftp = shift;\n    $ftp->_REBOOT;\n    $ftp->close;\n  }\n  sub check {\n    my $ftp = shift;\n    \n    delete ${*$ftp}{'net_ftp_port'};\n    delete ${*$ftp}{'net_ftp_pasv'};\n\n    my $data = $ftp->_data_cmd('CHECK' ,@_) or return undef;\n    my $sum;\n    if (${${*$ftp}{'net_cmd_resp'}}[0] =~ /^Flash check 0x([0-9A-F]{8})/) {\n      $sum = hex($1);\n    }\n    $data->_close();\n    return $sum;\n  }\n}\n\n# passive mode geht mit Net::FTP nicht, connected zu spaet fuer ADAM2!\nmy $ftp = ADAM2FTP->new($ip, Passive => 0, Debug => 0, Timeout => 600)\n  or die \"can't FTP ADAM2\";\n$ftp->login(\"adam2\", \"adam2\") or die \"can't login adam2\";\n$ftp->binary();\nmy $pid   = $ftp->getenv('ProductID');\nmy $hwrev = $ftp->getenv('HWRevision');\nmy $fwrev = $ftp->getenv('firmware_info');\nmy $ulrev = $ftp->getenv('urlader-version');\n\nprint \"Product ID: $pid\\n\";\nprint \"Hardware Revision: $hwrev\\n\";\nprint \"Urlader  Revision: $ulrev\\n\";\nprint \"Firmware Revision: $fwrev\\n\";\n\n$ftp->hash(\\*STDOUT, 64 * 1024);\n\nmy $file = shift @ARGV;\n$file || exit 0;\n\nopen FILE, \"<$file\" or die \"can't open firmware file\\n\";\n\nmy $mtd0 = $ftp->getenv(\"mtd0\");\nmy $mtd1 = $ftp->getenv(\"mtd1\");\nmy ($ksize, $fssize);\n\n$mtd1 =~ /^(0x\\w+),(0x\\w+)$/ and $ksize = hex($2) - hex($1);\n$mtd0 =~ /^(0x\\w+),(0x\\w+)$/ and $fssize = hex($2) - hex($1);\n$ksize and $fssize or die 'cannot read partition offsets';\nprintf STDERR \"Available flash space: 0x%08x (0x%08x + 0x%08x)\\n\", $ksize + $fssize, $ksize, $fssize;\n\n$ftp->command(\"MEDIA FLSH\")->response();\n$ftp->binary();\nprint STDERR \"Writing to mtd1...\\n\";\n\nmy $dc = $ftp->stor(\"fs mtd1\");\n$dc or die \"can't open data connection\\n\";\nmy $rbytes = 1;\n\nwhile (($ksize > 0) and ($rbytes > 0)) {\n\tmy $buffer;\n\tmy $len = ($ksize > 1024 ? 1024 : $ksize);\n\t$rbytes = read FILE, $buffer, $len;\n\t$rbytes and $ksize -= $dc->write($buffer, $rbytes, 600);\n}\n\n$dc->close();\n$rbytes or die \"no more data left to write\\n\";\n\nprint STDERR \"Writing to mtd0...\\n\";\n\n$dc = $ftp->stor(\"fs mtd0\");\n$dc or die \"can't open data connection\\n\";\n\nwhile (($fssize > 0) and ($rbytes > 0)) {\n\tmy $buffer;\n\tmy $len = ($fssize > 1024 ? 1024 : $fssize);\n\t$rbytes = read FILE, $buffer, $len;\n\t$rbytes and $fssize -= $dc->write($buffer, $rbytes, 600);\n}\n\n$dc->close();\n$ftp->reboot();\n"
  },
  {
    "path": "scripts/flashing/adam2flash.pl",
    "content": "#!/usr/bin/env perl\n#\n#   D-Link DSL-G6x4T flash utility\n#\n#   Copyright (C) 2005 Felix Fietkau <mailto@nbd.name>\n#   based on fbox recovery util by Enrik Berkhan\n#\n#   This program is free software; you can redistribute it and/or modify\n#   it under the terms of the GNU General Public License as published by\n#   the Free Software Foundation; either version 2 of the License, or\n#   (at your option) any later version.\n#\n#   This program is distributed in the hope that it will be useful,\n#   but WITHOUT ANY WARRANTY; without even the implied warranty of\n#   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n#   GNU General Public License for more details.\n#\n#   You should have received a copy of the GNU General Public License\n#   along with this program; if not, write to the Free Software\n#   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA\n#\n\nuse IO::Socket::INET;\nuse Socket;\nuse strict;\nuse warnings;\n\nsub usage() {\n\tprint STDERR \"Usage: $0 <ip> [firmware.bin]\\n\\n\";\n\texit 0;\n}\n\nmy $ip = shift @ARGV;\n$ip and $ip =~ /\\d{1,3}\\.\\d{1,3}\\.\\d{1,3}\\.\\d{1,3}/ or usage();\n\nmy $probe = IO::Socket::INET->new(Proto => 'udp',\n                                  Broadcast => 1,\n                                  LocalPort => 5035) or die \"socket: $!\";\nmy $setip = unpack(\"N\", inet_aton($ip));\n$setip > 0 or usage();\n\nmy @packets;\nforeach my $ver ([18, 1], [22, 2]) {\n\tpush @packets, pack(\"vCCVNV\", 0, @$ver, 1, $setip, 0);\n}\nprint STDERR \"Looking for device: \";\nmy $broadcast = sockaddr_in(5035, INADDR_BROADCAST);\nmy $scanning;\nmy $box;\n\n$SIG{\"ALRM\"} = sub {\n\treturn if --$scanning <= 0;\n\tforeach my $packet (@packets) {\n\t\t$probe->send($packet, 0, $broadcast);\n\t}\n\tprint STDERR \".\";\n};\n\n$scanning = 10;\nforeach my $packet (@packets) {\n\t$probe->send($packet, 0, $broadcast);\n}\nprint STDERR \".\";\n\nwhile($scanning) {\n\tmy $reply;\n\n\talarm(1);\n\tif (my $peer = $probe->recv($reply, 16)) {\n\t\tnext if (length($reply) < 16);\n\t\tmy ($port, $addr) = sockaddr_in($peer);\n\t\tmy ($major, $minor1, $minor2, $code, $addr2) = unpack(\"vCCVV\", $reply);\n\t\t$addr2 = pack(\"N\", $addr2);\n\t\tif ($code == 2) {\n\t\t\t$scanning = 0;\n\t\t\tprintf STDERR \" found!\\nADAM2 version $major.$minor1.$minor2 at %s (%s)\\n\", inet_ntoa($addr), inet_ntoa($addr2);\n\t\t\t$box = inet_ntoa($addr);\n\t\t}\n\t}\n}\n\n$box or die \" not found!\\n\";\n\n{\n\tpackage ADAM2FTP;\n\tuse base qw(Net::FTP);\n\t\n\t# ADAM2 requires upper case commands, some brain dead firewall doesn't ;-)\n\tsub _USER {\n\t\tshift->command(\"USER\",@_)->response()\n\t}\n\t\n\tsub _GETENV {\n\t\tmy $ftp = shift;\n\t\tmy ($ok, $name, $value);\n\t\t\n\t\t$ftp->command(\"GETENV\",@_);\n\t\t\twhile(length($ok = $ftp->response()) < 1) {\n\t\t\tmy $line = $ftp->getline();\n\t\t\tunless (defined($value)) {\n\t\t\t\tchomp($line);\n\t\t\t\t($name, $value) = split(/\\s+/, $line, 2);\n\t\t\t}\n\t\t}\n\t\t$ftp->debug_print(0, \"getenv: $value\\n\")\n\t\tif $ftp->debug();\n\t\treturn $value;\n\t}\n\t\n\tsub getenv {\n\t\tmy $ftp = shift;\n\t\tmy $name = shift;\n\t\treturn $ftp->_GETENV($name);\n\t}\n\t\n\tsub _REBOOT {\n\t\tshift->command(\"REBOOT\")->response() == Net::FTP::CMD_OK\n\t}\n\t\n\tsub reboot {\n\t\tmy $ftp = shift;\n\t\t$ftp->_REBOOT;\n\t\t$ftp->close;\n\t}\n}\n\nmy $file = shift @ARGV;\n$file || exit 0;\n\nopen FILE, \"<$file\" or die \"can't open firmware file\\n\";\nmy $ftp = ADAM2FTP->new($box, Debug => 0, Timeout => 600) or die \"can't open control connection\\n\";\n$ftp->login(\"adam2\", \"adam2\") or die \"can't login\\n\";\n\nmy $mtd0 = $ftp->getenv(\"mtd0\");\nmy $mtd1 = $ftp->getenv(\"mtd1\");\nmy ($ksize, $fssize);\n\n$mtd1 =~ /^(0x\\w+),(0x\\w+)$/ and $ksize = hex($2) - hex($1);\n$mtd0 =~ /^(0x\\w+),(0x\\w+)$/ and $fssize = hex($2) - hex($1);\n$ksize and $fssize or die 'cannot read partition offsets';\nprintf STDERR \"Available flash space: 0x%08x (0x%08x + 0x%08x)\\n\", $ksize + $fssize, $ksize, $fssize;\n\n$ftp->command(\"MEDIA FLSH\")->response();\n$ftp->binary();\nprint STDERR \"Writing to mtd1...\\n\";\n\nmy $dc = $ftp->stor(\"fs mtd1\");\n$dc or die \"can't open data connection\\n\";\nmy $rbytes = 1;\n\nwhile (($ksize > 0) and ($rbytes > 0)) {\n\tmy $buffer;\n\tmy $len = ($ksize > 1024 ? 1024 : $ksize);\n\t$rbytes = read FILE, $buffer, $len;\n\t$rbytes and $ksize -= $dc->write($buffer, $rbytes, 600);\n}\n\n$dc->close();\n$rbytes or die \"no more data left to write\\n\";\n\nprint STDERR \"Writing to mtd0...\\n\";\n\n$dc = $ftp->stor(\"fs mtd0\");\n$dc or die \"can't open data connection\\n\";\n\nwhile (($fssize > 0) and ($rbytes > 0)) {\n\tmy $buffer;\n\tmy $len = ($fssize > 1024 ? 1024 : $fssize);\n\t$rbytes = read FILE, $buffer, $len;\n\t$rbytes and $fssize -= $dc->write($buffer, $rbytes, 600);\n}\n\n$dc->close();\n$ftp->reboot();\n"
  },
  {
    "path": "scripts/flashing/adsl2mue_flash.pl",
    "content": "#!/usr/bin/env perl\n#\n#   Linksys ADSL2MUE Flash utility.\n#\n#   Copyright (C) 2008 Alexandre Lissy <alexandrelissy@free.fr>\n#   based on D-Link DSL-G6x4T flash utility by Felix Fietkau <mailto@nbd.name>\n#   based on fbox recovery util by Enrik Berkhan\n#\n#   This program is free software; you can redistribute it and/or modify\n#   it under the terms of the GNU General Public License as published by\n#   the Free Software Foundation; either version 2 of the License, or\n#   (at your option) any later version.\n#\n#   This program is distributed in the hope that it will be useful,\n#   but WITHOUT ANY WARRANTY; without even the implied warranty of\n#   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n#   GNU General Public License for more details.\n#\n#   You should have received a copy of the GNU General Public License\n#   along with this program; if not, write to the Free Software\n#   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA\n#\n\nuse IO::Socket::INET;\nuse Socket;\nuse strict;\nuse warnings;\n\nsub usage() {\n\tprint STDERR \"Usage: $0 <ip> [firmware.bin] [partition]\\n\\n\";\n\texit 0;\n}\n\nmy $ip = shift @ARGV;\n$ip and $ip =~ /\\d{1,3}\\.\\d{1,3}\\.\\d{1,3}\\.\\d{1,3}/ or usage();\n\nmy $probe = IO::Socket::INET->new(Proto => 'udp',\n                                  Broadcast => 1,\n                                  LocalPort => 5035) or die \"socket: $!\";\nmy $setip = unpack(\"N\", inet_aton($ip));\n$setip > 0 or usage();\n\nmy @packets;\nforeach my $ver ([18, 1], [22, 2]) {\n\tpush @packets, pack(\"vCCVNV\", 0, @$ver, 1, $setip, 0);\n}\nprint STDERR \"Looking for device: \";\nmy $broadcast = sockaddr_in(5035, INADDR_BROADCAST);\nmy $scanning;\nmy $box;\n\n$SIG{\"ALRM\"} = sub {\n\treturn if --$scanning <= 0;\n\tforeach my $packet (@packets) {\n\t\t$probe->send($packet, 0, $broadcast);\n\t}\n\tprint STDERR \".\";\n};\n\n$scanning = 10;\nforeach my $packet (@packets) {\n\t$probe->send($packet, 0, $broadcast);\n}\nprint STDERR \".\";\n\nwhile($scanning) {\n\tmy $reply;\n\n\talarm(1);\n\tif (my $peer = $probe->recv($reply, 16)) {\n\t\tnext if (length($reply) < 16);\n\t\tmy ($port, $addr) = sockaddr_in($peer);\n\t\tmy ($major, $minor1, $minor2, $code, $addr2) = unpack(\"vCCVN\", $reply);\n\t\t$addr2 = pack(\"N\", $addr2);\n\t\tif ($code == 1) {\n\t\t\t$scanning = 0;\n\t\t\tprintf STDERR \" found!\\nADAM2 version $major.$minor1.$minor2 at %s (%s)\\n\", inet_ntoa($addr2), inet_ntoa($addr);\n\t\t\t$box = inet_ntoa($addr2);\n\t\t}\n\t}\n}\n\n$box or die \" not found!\\n\";\n\n{\n\tpackage ADAM2FTP;\n\tuse base qw(Net::FTP);\n\t\n\t# ADAM2 requires upper case commands, some brain dead firewall doesn't ;-)\n\tsub _USER {\n\t\tshift->command(\"USER\",@_)->response()\n\t}\n\t\n\tsub _GETENV {\n\t\tmy $ftp = shift;\n\t\tmy ($ok, $name, $value);\n\t\t\n\t\t$ftp->command(\"GETENV\",@_);\n\t\t\twhile(length($ok = $ftp->response()) < 1) {\n\t\t\tmy $line = $ftp->getline();\n\t\t\tunless (defined($value)) {\n\t\t\t\tchomp($line);\n\t\t\t\t($name, $value) = split(/\\s+/, $line, 2);\n\t\t\t}\n\t\t}\n\t\t$ftp->debug_print(0, \"getenv: $value\\n\")\n\t\tif $ftp->debug();\n\t\treturn $value;\n\t}\n\t\n\tsub getenv {\n\t\tmy $ftp = shift;\n\t\tmy $name = shift;\n\t\treturn $ftp->_GETENV($name);\n\t}\n\t\n\tsub _REBOOT {\n\t\tshift->command(\"REBOOT\")->response() == Net::FTP::CMD_OK\n\t}\n\t\n\tsub reboot {\n\t\tmy $ftp = shift;\n\t\t$ftp->_REBOOT;\n\t\t$ftp->close;\n\t}\n}\n\nmy $file = shift @ARGV;\nmy $part = shift @ARGV;\n$file || exit 0;\n$part || exit 0;\n\nopen FILE, \"<$file\" or die \"can't open firmware file\\n\";\nmy $ftp = ADAM2FTP->new($box, Debug => 0, Timeout => 600) or die \"can't open control connection\\n\";\n$ftp->login(\"adam2\", \"adam2\") or die \"can't login\\n\";\n\n# my $mtd0 = $ftp->getenv(\"mtd0\");\n# my $mtd1 = $ftp->getenv(\"mtd1\");\nmy $mtd4 = $ftp->getenv($part);\n# my ($ksize, $fssize);\nmy ($ossize, $mtd_start, $mtd_end);\n\n# $mtd1 =~ /^(0x\\w+),(0x\\w+)$/ and $ksize = hex($2) - hex($1);\n# $mtd0 =~ /^(0x\\w+),(0x\\w+)$/ and $fssize = hex($2) - hex($1);\n$mtd4 =~ /^(0x\\w+),(0x\\w+)$/;\n$ossize = hex($2) - hex($1);\n$mtd_start = hex($1);\n$mtd_end = hex($2);\n$ossize and $mtd_start and $mtd_end or die 'cannot read partition offsets';\nprintf STDERR \"Available flash space: 0x%08x ($part: 0x%08x to 0x%08x)\\n\", $ossize, $mtd_start, $mtd_end;\n\n$ftp->command(\"MEDIA FLSH\")->response();\n$ftp->binary();\n\nprint STDERR \"Writing to $part ...\\n\";\nmy $dc = $ftp->stor(\"data $part\");\n$dc or die \"can't open data connection\\n\";\nmy $rbytes = 1;\n\nwhile (($ossize > 0) and ($rbytes > 0)) {\n\tmy $buffer;\n\tmy $len = ($ossize > 1024 ? 1024 : $ossize);\n\t$rbytes = read FILE, $buffer, $len;\n\tprintf STDERR \".\";\n\t$rbytes and $ossize -= $dc->write($buffer, $rbytes, 600);\n}\n\nprintf STDERR \"\\nDone.\\n\";\n\n$dc->close();\n"
  },
  {
    "path": "scripts/flashing/eva_ramboot.py",
    "content": "#!/usr/bin/env python3\n\nimport argparse\n\nfrom ftplib import FTP\nfrom os import stat\n\nparser = argparse.ArgumentParser(description='Tool to boot AVM EVA ramdisk images.')\nparser.add_argument('ip', type=str, help='IP-address to transfer the image to')\nparser.add_argument('image', type=str, help='Location of the ramdisk image')\nparser.add_argument('--offset', type=lambda x: int(x,0), help='Offset to load the image to in hex format with leading 0x. Only needed for non-lantiq devices.')\nargs = parser.parse_args()\n\nsize = stat(args.image).st_size\n# arbitrary size limit, to prevent the address calculations from overflows etc.\nassert size < 0x2000000\n\nif args.offset:\n\taddr = size\n\thaddr = args.offset\nelse:\n\t# We need to align the address.\n\t# A page boundary seems to be sufficient on 7362sl and 7412\n\taddr = ((0x8000000 - size) & ~0xfff)\n\thaddr = 0x80000000 + addr\n\nimg = open(args.image, \"rb\")\nftp = FTP(args.ip, 'adam2', 'adam2')\n\ndef adam(cmd):\n\tprint(\"> %s\"%(cmd))\n\tresp = ftp.sendcmd(cmd)\n\tprint(\"< %s\"%(resp))\n\tassert resp[0:3] == \"200\"\n\nftp.set_pasv(True)\n# The following parameters allow booting the avm recovery system with this\n# script.\nadam('SETENV memsize 0x%08x'%(addr))\nadam('SETENV kernel_args_tmp mtdram1=0x%08x,0x88000000'%(haddr))\nadam('MEDIA SDRAM')\nftp.storbinary('STOR 0x%08x 0x88000000'%(haddr), img)\nimg.close()\nftp.close()\n"
  },
  {
    "path": "scripts/flashing/flash.sh",
    "content": "#!/bin/bash\n#\n# tftp flash script for wireless routers\n#\n# Copyright (C) 2004 by Oleg I. Vdovikin <oleg@cs.msu.su>\n# Copyright (C) 2005 by Waldemar Brodkorb <wbx@openwrt.org>\n#\n# This program is free software; you can redistribute it and/or modify\n# it under the terms of the GNU General Public License as published by\n# the Free Software Foundation; either version 2 of the License, or\n# (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU\n# General Public License for more details.\n#\n# You should have received a copy of the GNU General Public License\n# along with this program; if not, write to the Free Software\n# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\n#\n\nif [ -z \"$1\" ] || [ ! -f \"$1\" ] || [ -z \"$2\" ]; then\n    echo Usage: \"$0\" firmware vendor\ncat << EOF\nIMPORTANT:\nNotes for Linksys / Asus WL500gx router:\n   be sure you have set boot_wait to yes. Power on your router\n   after executing this script.\n\nNotes for Asus WL500g router:\n   be sure POWER led is flashing (If this is not the case\n   poweroff the device, push the reset button & power on\n   it again, then release button)\n\n1) connect your pc to the LAN port\n2) be sure your link is up and has an address in the\n   192.168.1.0/24 address range (and not the 192.168.1.1)\n\nNotes for Toshiba router:\n   boot_wait is enabled by default on these units.\n\n1) connect your pc to any of the four LAN ports\n2) be sure your link is up and has an address in the\n   192.168.10.1/24 address range (and not the 192.168.10.1)\n3) run this script (unit will only accept .trx images)\n4) Turn unit power on.\n\nEOF\n    exit 0\nfi\nif [ \"$2\" = \"asus\" ]; then\necho Confirming IP address setting...\necho -en \"get ASUSSPACELINK\\x01\\x01\\xa8\\xc0 /dev/null\\nquit\\n\" | tftp 192.168.1.1\necho Flashing 192.168.1.1 using \"$1\"...\necho -en \"binary\\nput $1 ASUSSPACELINK\\nquit\\n\" | tftp 192.168.1.1\necho Please wait until leds stops flashing.\nelif [ \"$2\" = \"linksys\" ]; then\necho Flashing 192.168.1.1 using \"$1\"...\necho -en \"rexmt 1\\ntrace\\nbinary\\nput $1\\nquit\\n\" | tftp 192.168.1.1\necho Please wait until power led stops flashing. Do not poweroff! Then you can login via telnet 192.168.1.1.\nelif [ \"$2\" = \"toshiba\" ]; then\necho Flashing 192.168.10.1 using \"$1\"...\necho -en \"rexmt 1\\ntrace\\nbinary\\nput $1\\nquit\\n\" | tftp 192.168.10.1\necho Unit will automatically reboot within 5 minutes.  Do not power off.  Then you can login via telnet 192.168.10.1.\nfi\n"
  },
  {
    "path": "scripts/flashing/jungo-image.py",
    "content": "#!/usr/bin/env python3\n#\n# Copyright 2008, 2009 (C) Jose Vasconcellos <jvasco@verizon.net>\n#\n# A script that can communicate with jungo-based routers\n# (such as MI424-WR, USR8200 and WRV54G) to backup the installed\n# firmware and replace the boot loader.\n#\n# Tested with Python 2.5 on Linux and Windows\n#\n\"\"\"Usage: %s [options] <IP_address> [image.bin | url]\nValid options:\n\\t-h | --help: usage statement\n\\t-d | --dump: create a flash dump\n\\t-f | --file: use <filename> to store dump contents\n\\t-u | --user: provide username (default admin)\n\\t-p | --pass: provide password (default password1)\n\\t     --port: set port for http (default 8080)\n\\t-q | --quiet: don't display unnecessary information\n\\t-r | --reboot: reboot target on successful transfer\n\\t-V | --version: display version information\n\nIf no image (or url) is given, a flash dump is created.\nA built-in http server is used when an image file is provided.\n\"\"\"\n\nimport os\nimport sys\nimport getopt\nimport getpass\nimport telnetlib\nimport string\nimport binascii\nimport socket\nimport _thread\nimport socketserver\nimport http.server\n\nreboot = 0\nHOST = \"192.168.1.1\"\nPORT = 8080\nuser = \"admin\"\n#password = getpass.getpass()\npassword = \"password1\"\nproto = \"http\"\nurl = \"\"\nimagefile = \"\"\ndumpfile = \"\"\nverbose = 1\ndo_dump = 0\ndumplen = 0x10000\nflashsize=4*1024*1024\n#device=\"br0\"\ndevice=\"ixp0\"\n\n####################\n\ndef start_server(server):\n    httpd = socketserver.TCPServer((server,PORT),http.server.SimpleHTTPRequestHandler)\n    _thread.start_new_thread(httpd.serve_forever,())\n\n####################\n\ndef get_flash_size():\n    # make sure we don't have an A0 stepping\n    tn.write(\"cat /proc/cpuinfo\\n\")\n    buf = tn.read_until(\"Returned 0\", 3)\n    if not buf:\n        print(\"Unable to obtain CPU information; make sure to not use A0 stepping!\")\n    elif buf.find('rev 0') > 0:\n        print(\"Warning: IXP42x stepping A0 detected!\")\n        if imagefile or url:\n            print(\"Error: No linux support for A0 stepping!\")\n            sys.exit(2)\n\n    # now get flash size\n    tn.write(\"cat /proc/mtd\\n\")\n    buf = tn.read_until(\"Returned 0\", 3)\n    if buf:\n        i = buf.find('mtd0:')\n        if i > 0:\n            return int(buf[i+6:].split()[0],16)\n        # use different command\n        tn.write(\"flash_layout\\n\")\n        buf = tn.read_until(\"Returned 0\", 3)\n        i = buf.rfind('Range ')\n        if i > 0:\n            return int(buf[i+17:].split()[0],16)\n        print(\"Can't determine flash size!\")\n    else:\n        print(\"Unable to obtain flash size!\")\n    sys.exit(2)\n\ndef image_dump(tn, dumpfile):\n    if not dumpfile:\n        tn.write(\"ver\\n\");\n        buf = tn.read_until(\"Returned 0\",2)\n        i = buf.find(\"Platform:\")\n        if i < 0:\n\t    platform=\"jungo\"\n\telse:\n\t    line=buf[i+9:]\n\t    i=line.find('\\n')\n\t    platform=line[:i].split()[-1]\n\n        tn.write(\"rg_conf_print /dev/%s/mac\\n\" % device);\n        buf = tn.read_until(\"Returned 0\",3)\n\n\ti = buf.find(\"mac(\")\n\tif i > 0:\n\t    i += 4\n\telse:\n\t    print(\"No MAC address found! (use -f option)\")\n\t    sys.exit(1)\n        dumpfile = \"%s-%s.bin\" % (platform, buf[i:i+17].replace(':',''))\n    else:\n        tn.write(\"\\n\")\n\n    print(\"Dumping flash contents (%dMB) to %s\" % (flashsize/1048576, dumpfile))\n    f = open(dumpfile, \"wb\")\n\n    t=flashsize/dumplen\n    for addr in range(t):\n\tif verbose:\n\t    sys.stdout.write('\\r%d%%'%(100*addr/t))\n\t    sys.stdout.flush()\n\n        tn.write(\"flash_dump -r 0x%x -l %d -4\\n\" % (addr*dumplen, dumplen))\n\ttn.read_until(\"\\n\")\n\n\tcount = addr*dumplen\n        while 1:\n            buf = tn.read_until(\"\\n\")\n            if buf.strip() == \"Returned 0\":\n                break\n            s = buf.split()\n            if s and s[0][-1] == ':':\n\t\ta=int(s[0][:-1],16)\n\t\tif a != count:\n\t\t    print(\"Format error: %x != %x\"%(a,count))\n\t\t    sys.exit(2)\n\t    \tcount += 16\n\t\tf.write(binascii.a2b_hex(string.join(s[1:],'')))\n\ttn.read_until(\">\",1)\n\n    f.close()\n    if verbose:\n\tprint(\"\")\n\ndef telnet_option(sock,cmd,option):\n    #print \"Option: %d %d\" % (ord(cmd), ord(option))\n    if cmd == telnetlib.DO:\n        c=telnetlib.WILL\n    elif cmd == telnetlib.WILL:\n        c=telnetlib.DO\n    sock.sendall(telnetlib.IAC + c + option)\n\ndef telnet_timeout():\n    print(\"Fatal error: telnet timeout!\")\n    sys.exit(1)\n\ndef usage():\n    print(__doc__ % os.path.basename(sys.argv[0]))\n\n####################\n\ntry:\n    opts, args = getopt.getopt(sys.argv[1:], \"hdf:qp:P:rvV\", \\\n\t[\"help\", \"dump\", \"file=\", \"user=\", \"pass=\", \"port=\",\n\t \"quiet=\", \"reboot\", \"verbose\", \"version\"])\nexcept getopt.GetoptError:\n    # print help information and exit:\n    usage()\n    sys.exit(1)\n\nfor o, a in opts:\n    if o in (\"-h\", \"--help\"):\n\tusage()\n\tsys.exit(1)\n    elif o in (\"-V\", \"--version\"):\n\tprint(\"%s: 0.11\" % sys.argv[0])\n\tsys.exit(1)\n    elif o in (\"-d\", \"--no-dump\"):\n\tdo_dump = 1\n    elif o in (\"-f\", \"--file\"):\n\tdumpfile = a\n    elif o in (\"-u\", \"--user\"):\n\tuser = a\n    elif o in (\"-p\", \"--pass\"):\n\tpassword = a\n    elif o == \"--port\":\n\tPORT = int(a)\n    elif o in (\"-q\", \"--quiet\"):\n\tverbose = 0\n    elif o in (\"-r\", \"--reboot\"):\n\treboot = 1\n    elif o in (\"-v\", \"--verbose\"):\n\tverbose = 1\n\n# make sure we have enough arguments\nif len(args) > 0:\n    HOST = args[0]\n\nif len(args) == 2:\n    if args[1].split(':')[0] in (\"tftp\", \"http\", \"ftp\"):\n        url = args[1]\n    else:\n        imagefile = args[1]\nelse:\n    do_dump = 1;\n\n####################\n# create a telnet session to the router\ntry:\n    tn = telnetlib.Telnet(HOST)\nexcept socket.error as msg:\n    print(\"Unable to establish telnet session to %s: %s\" % (HOST, msg))\n    sys.exit(1)\n\ntn.set_option_negotiation_callback(telnet_option)\n\nbuf = tn.read_until(\"Username: \", 3)\nif not buf:\n    telnet_timeout()\ntn.write(user+\"\\n\")\nif password:\n    buf = tn.read_until(\"Password: \", 3)\n    if not buf:\n        telnet_timeout()\n    tn.write(password+\"\\n\")\n\n# wait for prompt\nbuf = tn.read_until(\"> \", 3)\nif not buf:\n    telnet_timeout()\n\nflashsize = get_flash_size()\n\nif do_dump:\n    image_dump(tn, dumpfile)\n\nif imagefile or url:\n    splitpath = os.path.split(imagefile)\n\n    # create load command\n    if url:\n        cmd = \"load -u %s -r 0\\n\" % (url)\n    else:\n        server = tn.get_socket().getsockname()[0]\n        cmd = \"load -u http://%s:%d/%s -r 0\\n\" % (server, PORT, splitpath[1])\n\n        if not os.access(imagefile, os.R_OK):\n            print(\"File access error: %s\" % (imagefile))\n            sys.exit(3)\n\n        # make sure we're in the directory where the image is located\n        if splitpath[0]:\n            os.chdir(splitpath[0])\n\n        start_server(server)\n\n    if verbose:\n\tprint(\"Unlocking flash...\")\n    tn.write(\"unlock 0 0x%x\\n\" % flashsize)\n    buf = tn.read_until(\"Returned 0\",5)\n\n    if verbose:\n\tprint(\"Writing new image...\")\n    print(cmd, end=' ')\n    tn.write(cmd)\n    buf = tn.read_until(\"Returned 0\",10)\n\n    # wait till the transfer completed\n    buf = tn.read_until(\"Download completed successfully\",20)\n    if buf:\n\tprint(\"Flash update complete!\")\n        if reboot:\n            tn.write(\"reboot\\n\")\n            print(\"Rebooting...\")\n\ntn.write(\"exit\\n\")\ntn.close()\n\n"
  },
  {
    "path": "scripts/functions.sh",
    "content": "#!/bin/sh\n\n\nget_magic_word() {\n\tdd if=$1 bs=4 count=1 2>/dev/null | od -A n -N 4 -t x1 | tr -d ' '\n}\n\nget_post_padding_word() {\n\tlocal rootfs_length=\"$(stat -c%s \"$1\")\"\n\t[ \"$rootfs_length\" -ge 4 ] || return\n\trootfs_length=$((rootfs_length-4))\n\n\t# the JFFS2 end marker must be on a 4K boundary (often 64K or 256K)\n\tlocal unaligned_bytes=$((rootfs_length%4096))\n\t[ \"$unaligned_bytes\" = 0 ] || return\n\n\t# skip rootfs data except the potential EOF marker\n\tdd if=\"$1\" bs=1 skip=\"$rootfs_length\" 2>/dev/null | od -A n -N 4 -t x1 | tr -d ' '\n}\n\nget_fs_type() {\n\tlocal magic_word=\"$(get_magic_word \"$1\")\"\n\n\tcase \"$magic_word\" in\n\t\"3118\"*)\n\t\techo \"ubifs\"\n\t\t;;\n\t\"68737173\")\n\t\tlocal post_padding_word=\"$(get_post_padding_word \"$1\")\"\n\n\t\tcase \"$post_padding_word\" in\n\t\t\"deadc0de\")\n\t\t\techo \"squashfs-jffs2\"\n\t\t\t;;\n\t\t*)\n\t\t\techo \"squashfs\"\n\t\t\t;;\n\t\tesac\n\t\t;;\n\t*)\n\t\techo \"unknown\"\n\t\t;;\n\tesac\n}\n\nround_up() {\n\techo \"$(((($1 + ($2 - 1))/ $2) * $2))\"\n}\n"
  },
  {
    "path": "scripts/gen-dependencies.sh",
    "content": "#!/bin/sh\n#\n# Copyright (C) 2012 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\nSELF=${0##*/}\n\nREADELF=\"${READELF:-readelf}\"\nOBJCOPY=\"${OBJCOPY:-objcopy}\"\nTARGETS=$*\nXARGS=\"${XARGS:-xargs -r}\"\n\n[ -z \"$TARGETS\" ] && {\n  echo \"$SELF: no directories / files specified\"\n  echo \"usage: $SELF [PATH...]\"\n  exit 1\n}\n\nfind $TARGETS -type f -a -exec file {} \\; | \\\n  sed -n -e 's/^\\(.*\\):.*ELF.*\\(executable\\|shared object\\).*,.*/\\1/p' | \\\n  $XARGS -n1 $READELF -d | \\\n  awk '$2 ~ /NEEDED/ && $NF !~ /interpreter/ && $NF ~ /^\\[?lib.*\\.so/ { gsub(/[\\[\\]]/, \"\", $NF); print $NF }' | \\\n  sort -u\n\ntmp=$(mktemp $TMP_DIR/dep.XXXXXXXX)\nfor kmod in $(find $TARGETS -type f -name \\*.ko); do\n\t$OBJCOPY -O binary -j .modinfo $kmod $tmp\n\tsed -e 's,\\x00,\\n,g' $tmp | \\\n\t\tsed -ne '/^depends=.\\+/ { s/^depends=//; s/,/.ko\\n/g; s/$/.ko/p; q }'\ndone | sort -u\nrm -f $tmp\n"
  },
  {
    "path": "scripts/gen_image_generic.sh",
    "content": "#!/bin/sh\n# Copyright (C) 2006-2012 OpenWrt.org\nset -e -x\nif [ $# -ne 5 ] && [ $# -ne 6 ]; then\n    echo \"SYNTAX: $0 <file> <kernel size> <kernel directory> <rootfs size> <rootfs image> [<align>]\"\n    exit 1\nfi\n\nOUTPUT=\"$1\"\nKERNELSIZE=\"$2\"\nKERNELDIR=\"$3\"\nROOTFSSIZE=\"$4\"\nROOTFSIMAGE=\"$5\"\nALIGN=\"$6\"\n\nrm -f \"$OUTPUT\"\n\nhead=16\nsect=63\n\n# create partition table\nset $(ptgen -o \"$OUTPUT\" -h $head -s $sect ${GUID:+-g} -p \"${KERNELSIZE}m\" -p \"${ROOTFSSIZE}m\" ${ALIGN:+-l $ALIGN} ${SIGNATURE:+-S 0x$SIGNATURE} ${GUID:+-G $GUID})\n\nKERNELOFFSET=\"$(($1 / 512))\"\nKERNELSIZE=\"$2\"\nROOTFSOFFSET=\"$(($3 / 512))\"\nROOTFSSIZE=\"$(($4 / 512))\"\n\n# Using mcopy -s ... is using READDIR(3) to iterate through the directory\n# entries, hence they end up in the FAT filesystem in traversal order which\n# breaks reproducibility.\n# Implement recursive copy with reproducible order.\ndos_dircopy() {\n  local entry\n  local baseentry\n  for entry in \"$1\"/* ; do\n    if [ -f \"$entry\" ]; then\n      mcopy -i \"$OUTPUT.kernel\" \"$entry\" ::\"$2\"\n    elif [ -d \"$entry\" ]; then\n      baseentry=\"$(basename \"$entry\")\"\n      mmd -i \"$OUTPUT.kernel\" ::\"$2\"\"$baseentry\"\n      dos_dircopy \"$entry\" \"$2\"\"$baseentry\"/\n    fi\n  done\n}\n\n[ -n \"$PADDING\" ] && dd if=/dev/zero of=\"$OUTPUT\" bs=512 seek=\"$ROOTFSOFFSET\" conv=notrunc count=\"$ROOTFSSIZE\"\ndd if=\"$ROOTFSIMAGE\" of=\"$OUTPUT\" bs=512 seek=\"$ROOTFSOFFSET\" conv=notrunc\n\nif [ -n \"$GUID\" ]; then\n    [ -n \"$PADDING\" ] && dd if=/dev/zero of=\"$OUTPUT\" bs=512 seek=\"$((ROOTFSOFFSET + ROOTFSSIZE))\" conv=notrunc count=\"$sect\"\n    mkfs.fat --invariant -n kernel -C \"$OUTPUT.kernel\" -S 512 \"$((KERNELSIZE / 1024))\"\n    LC_ALL=C dos_dircopy \"$KERNELDIR\" /\nelse\n    make_ext4fs -J -L kernel -l \"$KERNELSIZE\" ${SOURCE_DATE_EPOCH:+-T ${SOURCE_DATE_EPOCH}} \"$OUTPUT.kernel\" \"$KERNELDIR\"\nfi\ndd if=\"$OUTPUT.kernel\" of=\"$OUTPUT\" bs=512 seek=\"$KERNELOFFSET\" conv=notrunc\nrm -f \"$OUTPUT.kernel\"\n"
  },
  {
    "path": "scripts/get_source_date_epoch.sh",
    "content": "#!/usr/bin/env bash\nexport LANG=C\nexport LC_ALL=C\n\nif [ -n \"$TOPDIR\" ]; then\n\tcd \"$TOPDIR\" || exit 1\nfi\n\nSOURCE=\"${1:-.}\"\n\ntry_version() {\n\t[ -f \"$SOURCE/version.date\" ] || return 1\n\tSOURCE_DATE_EPOCH=$(cat \"$SOURCE/version.date\")\n\t[ -n \"$SOURCE_DATE_EPOCH\" ]\n}\n\ntry_git() {\n\tSOURCE_DATE_EPOCH=$(git -C \"$SOURCE\" log -1 --format=format:%ct \\\n\t\t\"$SOURCE\" 2>/dev/null)\n\t[ -n \"$SOURCE_DATE_EPOCH\" ]\n}\n\ntry_hg() {\n\tSOURCE_DATE_EPOCH=$(hg --cwd \"$SOURCE\" log --template '{date}' -l 1 \\\n\t\t\"$SOURCE\" 2>/dev/null | cut -d. -f1)\n\t[ -n \"$SOURCE_DATE_EPOCH\" ]\n}\n\ntry_mtime() {\n\tSOURCE_DATE_EPOCH=$(perl -e 'print((stat $ARGV[0])[9])' \"$0\")\n\t[ -n \"$SOURCE_DATE_EPOCH\" ]\n}\n\ntry_version || try_git || try_hg || try_mtime || SOURCE_DATE_EPOCH=\"\"\necho \"$SOURCE_DATE_EPOCH\"\n"
  },
  {
    "path": "scripts/getver.sh",
    "content": "#!/usr/bin/env bash\nexport LANG=C\nexport LC_ALL=C\n[ -n \"$TOPDIR\" ] && cd $TOPDIR\n\nGET_REV=$1\n\ntry_version() {\n\t[ -f version ] || return 1\n\tREV=\"$(cat version)\"\n\t[ -n \"$REV\" ]\n}\n\ntry_git() {\n\tREBOOT=ee53a240ac902dc83209008a2671e7fdcf55957a\n\tgit rev-parse --git-dir >/dev/null 2>&1 || return 1\n\n\t[ -n \"$GET_REV\" ] || GET_REV=\"HEAD\"\n\n\tcase \"$GET_REV\" in\n\tr*)\n\t\tGET_REV=\"$(echo $GET_REV | tr -d 'r')\"\n\t\tBASE_REV=\"$(git rev-list ${REBOOT}..HEAD 2>/dev/null | wc -l | awk '{print $1}')\"\n\t\tREV=\"$(git rev-parse HEAD~$((BASE_REV - GET_REV)))\"\n\t\t;;\n\t*)\n\t\tBRANCH=\"$(git rev-parse --abbrev-ref HEAD)\"\n\t\tORIGIN=\"$(git rev-parse --verify --symbolic-full-name ${BRANCH}@{u} 2>/dev/null)\"\n\t\t[ -n \"$ORIGIN\" ] || ORIGIN=\"$(git rev-parse --verify --symbolic-full-name master@{u} 2>/dev/null)\"\n\t\tREV=\"$(git rev-list ${REBOOT}..$GET_REV 2>/dev/null | wc -l | awk '{print $1}')\"\n\n\t\tif [ -n \"$ORIGIN\" ]; then\n\t\t\tUPSTREAM_BASE=\"$(git merge-base $GET_REV $ORIGIN)\"\n\t\t\tUPSTREAM_REV=\"$(git rev-list ${REBOOT}..$UPSTREAM_BASE 2>/dev/null | wc -l | awk '{print $1}')\"\n\t\telse\n\t\t\tUPSTREAM_REV=0\n\t\tfi\n\n\t\tif [ \"$REV\" -gt \"$UPSTREAM_REV\" ]; then\n\t\t\tREV=\"${UPSTREAM_REV}+$((REV - UPSTREAM_REV))\"\n\t\tfi\n\n\t\tREV=\"${REV:+r$REV-$(git log -n 1 --format=\"%h\" $UPSTREAM_BASE)}\"\n\n\t\t;;\n\tesac\n\n\t[ -n \"$REV\" ]\n}\n\ntry_hg() {\n\t[ -d .hg ] || return 1\n\tREV=\"$(hg log -r-1 --template '{desc}' | awk '{print $2}' | sed 's/\\].*//')\"\n\tREV=\"${REV:+r$REV}\"\n\t[ -n \"$REV\" ]\n}\n\ntry_version || try_git || try_hg || REV=\"unknown\"\necho \"$REV\"\n"
  },
  {
    "path": "scripts/ipkg-build",
    "content": "#!/bin/sh\n\n# ipkg-build -- construct a .ipk from a directory\n# Carl Worth <cworth@east.isi.edu>\n# based on a script by Steve Redler IV, steve@sr-tech.com 5-21-2001\n# 2003-04-25 rea@sr.unh.edu\n#   Updated to work on Familiar Pre0.7rc1, with busybox tar.\n#   Note it Requires: binutils-ar (since the busybox ar can't create)\n#   For UID debugging it needs a better \"find\".\nset -e\n\nversion=1.0\nFIND=\"$(command -v find)\"\nFIND=\"${FIND:-$(command -v gfind)}\"\nTAR=\"${TAR:-$(command -v tar)}\"\n\n# try to use fixed source epoch\nif [ -n \"$PKG_SOURCE_DATE_EPOCH\" ]; then\n\tTIMESTAMP=$(date --date=\"@$PKG_SOURCE_DATE_EPOCH\")\nelif [ -n \"$SOURCE_DATE_EPOCH\" ]; then\n\tTIMESTAMP=$(date --date=\"@$SOURCE_DATE_EPOCH\")\nelse\n\tTIMESTAMP=$(date)\nfi\n\nipkg_extract_value() {\n\tsed -e \"s/^[^:]*:[[:space:]]*//\"\n}\n\nrequired_field() {\n\tfield=$1\n\n\tgrep \"^$field:\" < \"$CONTROL/control\" | ipkg_extract_value\n}\n\npkg_appears_sane() {\n\tlocal pkg_dir=\"$1\"\n\n\tlocal owd=\"$PWD\"\n\tcd \"$pkg_dir\"\n\n\tPKG_ERROR=0\n\tpkg=\"$(required_field Package)\"\n\tversion=\"$(required_field Version | sed 's/Version://; s/^.://g;')\"\n\tarch=\"$(required_field Architecture)\"\n\n\tif echo \"$pkg\" | grep '[^a-zA-Z0-9_.+-]'; then\n\t\techo \"*** Error: Package name $name contains illegal characters, (other than [a-z0-9.+-])\" >&2\n\t\tPKG_ERROR=1;\n\tfi\n\n\tif [ -f \"$CONTROL/conffiles\" ]; then\n\t\trm -f \"$CONTROL/conffiles.resolved\"\n\n\t\tfor cf in $($FIND $(sed -e \"s!^/!$pkg_dir/!\" \"$CONTROL/conffiles\") -type f); do\n\t\t\techo \"${cf#$pkg_dir}\" >> \"$CONTROL/conffiles.resolved\"\n\t\tdone\n\n\t\trm \"$CONTROL\"/conffiles\n\t\tif [ -f \"$CONTROL\"/conffiles.resolved ]; then\n\t\t\tLC_ALL=C sort -o \"$CONTROL\"/conffiles \"$CONTROL\"/conffiles.resolved\n\t\t\trm \"$CONTROL\"/conffiles.resolved\n\t\t\tchmod 0644 \"$CONTROL\"/conffiles\n\t\tfi\n\tfi\n\n\tcd \"$owd\"\n\treturn $PKG_ERROR\n}\n\nresolve_file_mode_id() {\n\tlocal var=$1 type=$2 name=$3 id\n\n\tcase \"$name\" in\n\t\troot)\n\t\t\tid=0\n\t\t;;\n\t\t*[!0-9]*)\n\t\t\tid=$(sed -ne \"s#^$type $name \\\\([0-9]\\\\+\\\\)\\\\b.*\\$#\\\\1#p\" \"$TOPDIR/tmp/.packageusergroup\" 2>/dev/null)\n\t\t;;\n\t\t*)\n\t\t\tid=$name\n\t\t;;\n\tesac\n\n\texport \"$var=$id\"\n\n\t[ -n \"$id\" ]\n}\n\n###\n# ipkg-build \"main\"\n###\nfile_modes=\"\"\nusage=\"Usage: $0 [-v] [-h] [-m] <pkg_directory> [<destination_directory>]\"\nwhile getopts \"hvm:\" opt; do\n    case $opt in\n\tv ) echo \"$version\"\n\t    exit 0\n\t    ;;\n\th ) \techo \"$usage\"  >&2 ;;\n\tm )\tfile_modes=$OPTARG ;;\n\t\\? ) \techo \"$usage\"  >&2\n\tesac\ndone\n\n\nshift $((OPTIND - 1))\n\n# continue on to process additional arguments\n\ncase $# in\n1)\n\tdest_dir=$PWD\n\t;;\n2)\n\tdest_dir=$2\n\tif [ \"$dest_dir\" = \".\" ] || [ \"$dest_dir\" = \"./\" ] ; then\n\t    dest_dir=$PWD\n\tfi\n\t;;\n*)\n\techo \"$usage\" >&2\n\texit 1\n\t;;\nesac\n\npkg_dir=\"$(realpath \"$1\")\"\n\nif [ ! -d \"$pkg_dir\" ]; then\n\techo \"*** Error: Directory $pkg_dir does not exist\" >&2\n\texit 1\nfi\n\n# CONTROL is second so that it takes precedence\nCONTROL=\n[ -d \"$pkg_dir\"/CONTROL ] && CONTROL=CONTROL\nif [ -z \"$CONTROL\" ]; then\n\techo \"*** Error: Directory $pkg_dir has no CONTROL subdirectory.\" >&2\n\texit 1\nfi\n\nif ! pkg_appears_sane \"$pkg_dir\"; then\n\techo >&2\n\techo \"ipkg-build: Please fix the above errors and try again.\" >&2\n\texit 1\nfi\n\ntmp_dir=$dest_dir/IPKG_BUILD.$$\nmkdir \"$tmp_dir\"\n\necho $CONTROL > \"$tmp_dir\"/tarX\ncd \"$pkg_dir\"\nfor file_mode in $file_modes; do\n\tcase $file_mode in\n\t/*:*:*:*)\n\t    ;;\n\t*)\n\t    echo \"ERROR: file modes must use absolute path and contain user:group:mode\"\n\t    echo \"$file_mode\"\n\t    exit 1\n\t    ;;\n\tesac\n\n\tmode=${file_mode##*:}; path=${file_mode%:*}\n\tgroup=${path##*:};     path=${path%:*}\n\tuser=${path##*:};      path=${path%:*}\n\n\tif ! resolve_file_mode_id uid user \"$user\"; then\n\t\techo \"ERROR: unable to resolve uid of $user\" >&2\n\t\texit 1\n\tfi\n\n\tif ! resolve_file_mode_id gid group \"$group\"; then\n\t\techo \"ERROR: unable to resolve gid of $group\" >&2\n\t\texit 1\n\tfi\n\n\tchown \"$uid:$gid\" \"$pkg_dir/$path\"\n\tchmod  \"$mode\" \"$pkg_dir/$path\"\ndone\n$TAR -X \"$tmp_dir\"/tarX --format=gnu --numeric-owner --sort=name -cpf - --mtime=\"$TIMESTAMP\" . | gzip -n - > \"$tmp_dir\"/data.tar.gz\n\ninstalled_size=$(stat -c \"%s\" \"$tmp_dir\"/data.tar.gz)\nsed -i -e \"s/^Installed-Size: .*/Installed-Size: $installed_size/\" \\\n\t\"$pkg_dir\"/$CONTROL/control\n\n( cd \"$pkg_dir\"/$CONTROL && $TAR --format=gnu --numeric-owner --sort=name -cf -  --mtime=\"$TIMESTAMP\" . | gzip -n - > \"$tmp_dir\"/control.tar.gz )\nrm \"$tmp_dir\"/tarX\n\necho \"2.0\" > \"$tmp_dir\"/debian-binary\n\npkg_file=$dest_dir/${pkg}_${version}_${arch}.ipk\nrm -f \"$pkg_file\"\n( cd \"$tmp_dir\" && $TAR --format=gnu --numeric-owner --sort=name -cf -  --mtime=\"$TIMESTAMP\" ./debian-binary ./data.tar.gz ./control.tar.gz | gzip -n - > \"$pkg_file\" )\n\nrm \"$tmp_dir\"/debian-binary \"$tmp_dir\"/data.tar.gz \"$tmp_dir\"/control.tar.gz\nrmdir \"$tmp_dir\"\n\necho \"Packaged contents of $pkg_dir into $pkg_file\"\n"
  },
  {
    "path": "scripts/ipkg-make-index.sh",
    "content": "#!/usr/bin/env bash\nset -e\n\npkg_dir=$1\n\nif [ -z $pkg_dir ] || [ ! -d $pkg_dir ]; then\n\techo \"Usage: ipkg-make-index <package_directory>\" >&2\n\texit 1\nfi\n\nempty=1\n\nfor pkg in `find $pkg_dir -name '*.ipk' | sort`; do\n\tempty=\n\tname=\"${pkg##*/}\"\n\tname=\"${name%%_*}\"\n\t[[ \"$name\" = \"kernel\" ]] && continue\n\t[[ \"$name\" = \"libc\" ]] && continue\n\techo \"Generating index for package $pkg\" >&2\n\tfile_size=$(stat -L -c%s $pkg)\n\tsha256sum=$($MKHASH sha256 $pkg)\n\t# Take pains to make variable value sed-safe\n\tsed_safe_pkg=`echo $pkg | sed -e 's/^\\.\\///g' -e 's/\\\\//\\\\\\\\\\\\//g'`\n\ttar -xzOf $pkg ./control.tar.gz | tar xzOf - ./control | sed -e \"s/^Description:/Filename: $sed_safe_pkg\\\\\nSize: $file_size\\\\\nSHA256sum: $sha256sum\\\\\nDescription:/\"\n\techo \"\"\ndone\n[ -n \"$empty\" ] && echo\nexit 0\n"
  },
  {
    "path": "scripts/ipkg-remove",
    "content": "#!/usr/bin/env bash\n\nsourcename=\"$1\"; shift\n\nfor pkg in \"$@\"; do\n\ttar -Ozxf \"$pkg\" ./control.tar.gz 2>/dev/null | tar -Ozxf - ./control 2>/dev/null | \\\n\twhile read field value; do\n\t\tif [ \"$field\" = \"SourceName:\" ] && [ \"$value\" = \"$sourcename\" ]; then\n\t\t\trm -vf \"$pkg\"\n\t\t\tbreak\n\t\tfi\n\tdone\n\tcase \"$pkg\" in\n\t\t*/\"${sourcename}_\"*.ipk)\n\t\t\trm -vf \"$pkg\"\n\t\t;;\n\tesac\ndone\n\nexit 0\n"
  },
  {
    "path": "scripts/json_add_image_info.py",
    "content": "#!/usr/bin/env python3\n\nfrom os import getenv\nfrom pathlib import Path\nfrom sys import argv\nimport hashlib\nimport json\n\nif len(argv) != 2:\n    print(\"ERROR: JSON info script requires output arg\")\n    exit(1)\n\njson_path = Path(argv[1])\nfile_path = Path(getenv(\"FILE_DIR\")) / getenv(\"FILE_NAME\")\n\n\nif not file_path.is_file():\n    print(\"Skip JSON creation for non existing file\", file_path)\n    exit(0)\n\n\ndef get_titles():\n    titles = []\n    for prefix in [\"\", \"ALT0_\", \"ALT1_\", \"ALT2_\"]:\n        title = {}\n        for var in [\"vendor\", \"model\", \"variant\"]:\n            if getenv(\"DEVICE_{}{}\".format(prefix, var.upper())):\n                title[var] = getenv(\"DEVICE_{}{}\".format(prefix, var.upper()))\n\n        if title:\n            titles.append(title)\n\n    if not titles:\n        titles.append({\"title\": getenv(\"DEVICE_TITLE\")})\n\n    return titles\n\n\ndevice_id = getenv(\"DEVICE_ID\")\nhash_file = hashlib.sha256(file_path.read_bytes()).hexdigest()\n\nif file_path.with_suffix(file_path.suffix + \".sha256sum\").exists():\n    hash_unsigned = (\n        file_path.with_suffix(file_path.suffix + \".sha256sum\").read_text().strip()\n    )\nelse:\n    hash_unsigned = hash_file\n\nfile_info = {\n    \"metadata_version\": 1,\n    \"target\": \"{}/{}\".format(getenv(\"TARGET\"), getenv(\"SUBTARGET\")),\n    \"version_code\": getenv(\"VERSION_CODE\"),\n    \"version_number\": getenv(\"VERSION_NUMBER\"),\n    \"source_date_epoch\": int(getenv(\"SOURCE_DATE_EPOCH\")),\n    \"profiles\": {\n        device_id: {\n            \"image_prefix\": getenv(\"DEVICE_IMG_PREFIX\"),\n            \"images\": [\n                {\n                    \"type\": getenv(\"FILE_TYPE\"),\n                    \"name\": getenv(\"FILE_NAME\"),\n                    \"sha256\": hash_file,\n                    \"sha256_unsigned\": hash_unsigned,\n                }\n            ],\n            \"device_packages\": getenv(\"DEVICE_PACKAGES\").split(),\n            \"supported_devices\": getenv(\"SUPPORTED_DEVICES\").split(),\n            \"titles\": get_titles(),\n        }\n    },\n}\n\nif getenv(\"FILE_FILESYSTEM\"):\n    file_info[\"profiles\"][device_id][\"images\"][0][\"filesystem\"] = getenv(\n        \"FILE_FILESYSTEM\"\n    )\n\njson_path.write_text(json.dumps(file_info, separators=(\",\", \":\")))\n"
  },
  {
    "path": "scripts/json_overview_image_info.py",
    "content": "#!/usr/bin/env python3\n\nfrom os import getenv, environ\nfrom pathlib import Path\nfrom subprocess import run, PIPE\nfrom sys import argv\nimport json\n\nif len(argv) != 2:\n    print(\"JSON info files script requires output file as argument\")\n    exit(1)\n\noutput_path = Path(argv[1])\n\nassert getenv(\"WORK_DIR\"), \"$WORK_DIR required\"\n\nwork_dir = Path(getenv(\"WORK_DIR\"))\n\noutput = {}\n\n\ndef get_initial_output(image_info):\n    # preserve existing profiles.json\n    if output_path.is_file():\n        profiles = json.loads(output_path.read_text())\n        if profiles[\"version_code\"] == image_info[\"version_code\"]:\n            return profiles\n    return image_info\n\n\nfor json_file in work_dir.glob(\"*.json\"):\n    image_info = json.loads(json_file.read_text())\n\n    if not output:\n        output = get_initial_output(image_info)\n\n    # get first and only profile in json file\n    device_id, profile = next(iter(image_info[\"profiles\"].items()))\n    if device_id not in output[\"profiles\"]:\n        output[\"profiles\"][device_id] = profile\n    else:\n        output[\"profiles\"][device_id][\"images\"].extend(profile[\"images\"])\n\n# make image lists unique by name, keep last/latest\nfor device_id, profile in output.get(\"profiles\", {}).items():\n    profile[\"images\"] = list({e[\"name\"]: e for e in profile[\"images\"]}.values())\n\n\nif output:\n    default_packages, output[\"arch_packages\"] = run(\n        [\n            \"make\",\n            \"--no-print-directory\",\n            \"-C\",\n            \"target/linux/\",\n            \"val.DEFAULT_PACKAGES\",\n            \"val.ARCH_PACKAGES\",\n        ],\n        stdout=PIPE,\n        stderr=PIPE,\n        check=True,\n        env=environ.copy().update({\"TOPDIR\": Path().cwd()}),\n        universal_newlines=True,\n    ).stdout.splitlines()\n\n    output[\"default_packages\"] = sorted(default_packages.split())\n\n    output_path.write_text(json.dumps(output, sort_keys=True, separators=(\",\", \":\")))\nelse:\n    print(\"JSON info file script could not find any JSON files for target\")\n"
  },
  {
    "path": "scripts/kconfig.pl",
    "content": "#!/usr/bin/env perl\n# \n# Copyright (C) 2006 Felix Fietkau <nbd@nbd.name>\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\nuse warnings;\nuse strict;\n\nmy @arg;\nmy $PREFIX = \"CONFIG_\";\n\nsub set_config($$$$) {\n\tmy $config = shift;\n\tmy $idx = shift;\n\tmy $newval = shift;\n\tmy $mod_plus = shift;\n\n\tif (!defined($config->{$idx}) or !$mod_plus or\n\t    $config->{$idx} eq '#undef' or $newval eq 'y') {\n\t\t$config->{$idx} = $newval;\n\t}\n}\n\nsub load_config($$) {\n\tmy $file = shift;\n\tmy $mod_plus = shift;\n\tmy %config;\n\n\topen FILE, \"$file\" or die \"can't open file '$file'\";\n\twhile (<FILE>) {\n\t\tchomp;\n\t\t/^$PREFIX(.+?)=(.+)/ and do {\n\t\t\tset_config(\\%config, $1, $2, $mod_plus);\n\t\t\tnext;\n\t\t};\n\t\t/^# $PREFIX(.+?) is not set/ and do {\n\t\t\tset_config(\\%config, $1, \"#undef\", $mod_plus);\n\t\t\tnext;\n\t\t};\n\t\t/^#/ and next;\n\t\t/^(.+)$/ and warn \"WARNING: can't parse line: $1\\n\";\n\t}\n\treturn \\%config;\n}\n\n\nsub config_and($$) {\n\tmy $cfg1 = shift;\n\tmy $cfg2 = shift;\n\tmy %config;\n\n\tforeach my $config (keys %$cfg1) {\n\t\tmy $val1 = $cfg1->{$config};\n\t\tmy $val2 = $cfg2->{$config};\n\t\t$val2 and ($val1 eq $val2) and do {\n\t\t\t$config{$config} = $val1;\n\t\t};\n\t}\n\treturn \\%config;\n}\n\n\nsub config_add($$$) {\n\tmy $cfg1 = shift;\n\tmy $cfg2 = shift;\n\tmy $mod_plus = shift;\n\tmy %config;\n\t\n\tfor ($cfg1, $cfg2) {\n\t\tmy %cfg = %$_;\n\t\t\n\t\tforeach my $config (keys %cfg) {\n\t\t\tif ($mod_plus and $config{$config}) {\n\t\t\t\tnext if $config{$config} eq \"y\";\n\t\t\t\tnext if $cfg{$config} eq '#undef';\n\t\t\t}\n\t\t\t$config{$config} = $cfg{$config};\n\t\t}\n\t}\n\treturn \\%config;\n}\n\nsub config_diff($$$) {\n\tmy $cfg1 = shift;\n\tmy $cfg2 = shift;\n\tmy $new_only = shift;\n\tmy %config;\n\t\n\tforeach my $config (keys %$cfg2) {\n\t\tif (!defined($cfg1->{$config}) or $cfg1->{$config} ne $cfg2->{$config}) {\n\t\t\tnext if $new_only and !defined($cfg1->{$config}) and $cfg2->{$config} eq '#undef';\n\t\t\t$config{$config} = $cfg2->{$config};\n\t\t}\n\t}\n\treturn \\%config\n}\n\nsub config_sub($$) {\n\tmy $cfg1 = shift;\n\tmy $cfg2 = shift;\n\tmy %config = %{$cfg1};\n\tmy @keys = map {\n\t\tmy $expr = $_;\n\t\t$expr =~ /[?.*]/ ?\n\t\t\tmap {\n\t\t\t\t/^$expr$/ ? $_ : ()\n\t\t\t} keys %config : $expr;\n\t} keys %$cfg2;\n\n\tforeach my $config (@keys) {\n\t\tdelete $config{$config};\n\t}\n\treturn \\%config;\n}\n\nsub print_cfgline($$) {\n\tmy $name = shift;\n\tmy $val = shift;\n\tif ($val eq '#undef' or $val eq 'n') {\n\t\tprint \"# $PREFIX$name is not set\\n\";\n\t} else {\n\t\tprint \"$PREFIX$name=$val\\n\";\n\t}\n}\n\n\nsub dump_config($) {\n\tmy $cfg = shift;\n\tdie \"argument error in dump_config\" unless ($cfg);\n\tmy %config = %$cfg;\n\tforeach my $config (sort keys %config) {\n\t\tprint_cfgline($config, $config{$config});\n\t}\n}\n\nsub parse_expr {\n\tmy $pos = shift;\n\tmy $mod_plus = shift;\n\tmy $arg = $arg[$$pos++];\n\n\tdie \"Parse error\" if (!$arg);\n\n\tif ($arg eq '&') {\n\t\tmy $arg1 = parse_expr($pos);\n\t\tmy $arg2 = parse_expr($pos);\n\t\treturn config_and($arg1, $arg2);\n\t} elsif ($arg =~ /^\\+/) {\n\t\tmy $arg1 = parse_expr($pos);\n\t\tmy $arg2 = parse_expr($pos);\n\t\treturn config_add($arg1, $arg2, 0);\n\t} elsif ($arg =~ /^m\\+/) {\n\t\tmy $arg1 = parse_expr($pos);\n\t\tmy $arg2 = parse_expr($pos, 1);\n\t\treturn config_add($arg1, $arg2, 1);\n\t} elsif ($arg eq '>') {\n\t\tmy $arg1 = parse_expr($pos);\n\t\tmy $arg2 = parse_expr($pos);\n\t\treturn config_diff($arg1, $arg2, 0);\n\t} elsif ($arg eq '>+') {\n\t\tmy $arg1 = parse_expr($pos);\n\t\tmy $arg2 = parse_expr($pos);\n\t\treturn config_diff($arg1, $arg2, 1);\n\t} elsif ($arg eq '-') {\n\t\tmy $arg1 = parse_expr($pos);\n\t\tmy $arg2 = parse_expr($pos);\n\t\treturn config_sub($arg1, $arg2);\n\t} else {\n\t\treturn load_config($arg, $mod_plus);\n\t}\n}\n\nwhile (@ARGV > 0 and $ARGV[0] =~ /^-\\w+$/) {\n\tmy $cmd = shift @ARGV;\n\tif ($cmd =~ /^-n$/) {\n\t\t$PREFIX = \"\";\n\t} elsif ($cmd =~ /^-p$/) {\n\t\t$PREFIX = shift @ARGV;\n\t} else {\n\t\tdie \"Invalid option: $cmd\\n\";\n\t}\n}\n@arg = @ARGV;\n\nmy $pos = 0;\ndump_config(parse_expr(\\$pos));\ndie \"Parse error\" if ($arg[$pos]);\n"
  },
  {
    "path": "scripts/linksys-image.sh",
    "content": "#!/bin/sh\n#\n# Copyright (C) 2018 Oceanic Systems (UK) Ltd\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n# Maintained by: Ryan Pannell <ryan [at] o s u k l .com> <github.com/Escalion>\n#\n# Write Linksys signature for factory image\n# This is appended to the factory image and is tested by the Linksys Upgrader - as observed in civic.\n# The footer is 256 bytes. The format is:\n#  .LINKSYS.        This is detected by the Linksys upgrader before continuing with upgrade. (9 bytes)\n#  <VERSION>        The version number of upgrade. Not checked so use arbitrary value (8 bytes)\n#  <TYPE>           Model of target device, padded (0x20) to (15 bytes)\n#  <CRC>      \t    CRC checksum of the image to flash (8 byte)\n#  <padding>\t    Padding (0x20) (7 bytes)\n#  <signature>\t    Signature of signer. Not checked so use arbitrary value (16 bytes)\n#  <padding>        Padding (0x00) (192 bytes)\n#  0x0A\t\t    (1 byte)\n\n## version history\n# * version 1: initial commit\n\nset -e\n\nME=\"${0##*/}\"\n\nusage() {\n\techo \"Usage: $ME <type> <in filename>\"\n\t[ \"$IMG_OUT\" ] && rm -f \"$IMG_OUT\"\n\texit 1\n}\n\n[ \"$#\" -lt 3 ] && usage\n\nTYPE=$1\n\ntmpdir=\"$( mktemp -d 2> /dev/null )\"\nif [ -z \"$tmpdir\" ]; then\n\t# try OSX signature\n\ttmpdir=\"$( mktemp -t 'ubitmp' -d )\"\nfi\n\nif [ -z \"$tmpdir\" ]; then\n\texit 1\nfi\n\ntrap \"rm -rf $tmpdir\" EXIT\n\nIMG_TMP_OUT=\"${tmpdir}/out\"\n\nIMG_IN=$2\nIMG_OUT=\"${IMG_IN}.new\"\n\n[ ! -f \"$IMG_IN\" ] && echo \"$ME: Not a valid image: $IMG_IN\" && usage\n\ndd if=\"${IMG_IN}\" of=\"${IMG_TMP_OUT}\"\nCRC=$(printf \"%08X\" $(dd if=\"${IMG_IN}\" bs=$(stat -c%s \"${IMG_IN}\") count=1|cksum| cut -d ' ' -f1))\n\nprintf \".LINKSYS.01000409%-15s%-8s%-7s%-16s\" \"${TYPE}\" \"${CRC}\" \"\" \"K0000000F0246434\" >> \"${IMG_TMP_OUT}\"\n\ndd if=/dev/zero bs=1 count=192 conv=notrunc >> \"${IMG_TMP_OUT}\"\n\nprintf '\\12' >> \"${IMG_TMP_OUT}\"\n\ncp \"${IMG_TMP_OUT}\" \"${IMG_OUT}\"\n"
  },
  {
    "path": "scripts/make-ipkg-dir.sh",
    "content": "#!/bin/sh\nBASE=http://svn.openwrt.org/openwrt/trunk/openwrt\nTARGET=$1\nCONTROL=$2\nVERSION=$3\nARCH=$4\n\nWD=$(pwd)\n\nmkdir -p \"$TARGET/CONTROL\"\ngrep '^[^(Version|Architecture)]' \"$CONTROL\" > \"$TARGET/CONTROL/control\"\ngrep '^Maintainer' \"$CONTROL\" 2>&1 >/dev/null || \\\n        echo \"Maintainer: LEDE Community <lede-dev@lists.infradead.org>\" >> \"$TARGET/CONTROL/control\"\ngrep '^Source' \"$CONTROL\" 2>&1 >/dev/null || {\n        pkgbase=$(echo \"$WD\" | sed -e \"s|^$TOPDIR/||g\")\n        [ \"$pkgbase\" = \"$WD\" ] && src=\"N/A\" || src=\"$BASE/$pkgbase\"\n        echo \"Source: $src\" >> \"$TARGET/CONTROL/control\"\n}\necho \"Version: $VERSION\" >> \"$TARGET/CONTROL/control\"\necho \"Architecture: $ARCH\" >> \"$TARGET/CONTROL/control\"\nchmod 644 \"$TARGET/CONTROL/control\"\n"
  },
  {
    "path": "scripts/md5sum",
    "content": "#!/bin/sh\ncat \"$@\" | md5\n"
  },
  {
    "path": "scripts/metadata.pm",
    "content": "package metadata;\nuse base 'Exporter';\nuse strict;\nuse warnings;\nour @EXPORT = qw(%package %vpackage %srcpackage %category %overrides clear_packages parse_package_metadata parse_target_metadata get_multiline @ignore %usernames %groupnames);\n\nour %package;\nour %vpackage;\nour %srcpackage;\nour %category;\nour %overrides;\nour @ignore;\n\nour %usernames;\nour %groupnames;\nour %userids;\nour %groupids;\n\nsub get_multiline {\n\tmy $fh = shift;\n\tmy $prefix = shift;\n\tmy $str;\n\twhile (<$fh>) {\n\t\tlast if /^@@/;\n\t\t$str .= (($_ and $prefix) ? $prefix . $_ : $_);\n\t}\n\n\treturn $str ? $str : \"\";\n}\n\nsub confstr($) {\n\tmy $conf = shift;\n\t$conf =~ tr#/\\.\\-/#___#;\n\treturn $conf;\n}\n\nsub parse_package_metadata_usergroup($$$$$) {\n\tmy $makefile = shift;\n\tmy $typename = shift;\n\tmy $names = shift;\n\tmy $ids = shift;\n\tmy $spec = shift;\n\tmy $name;\n\tmy $id;\n\n\t# the regex for name is taken from is_valid_name() of package shadow\n\tif ($spec =~ /^([a-z_][a-z0-9_-]*\\$?)$/) {\n\t\t$name = $spec;\n\t\t$id = -1;\n\t} elsif ($spec =~ /^([a-z_][a-z0-9_-]*\\$?)=(\\d+)$/) {\n\t\t$name = $1;\n\t\t$id = $2;\n\t} else {\n\t\twarn \"$makefile: invalid $typename spec $spec\\n\";\n\t\treturn 0;\n\t}\n\n\tif ($id =~ /^[1-9]\\d*$/) {\n\t\tif ($id >= 65536) {\n\t\t\twarn \"$makefile: $typename $name id $id >= 65536\";\n\t\t\treturn 0;\n\t\t}\n\t\tif (not exists $ids->{$id}) {\n\t\t\t$ids->{$id} = {\n\t\t\t\tname => $name,\n\t\t\t\tmakefile => $makefile,\n\t\t\t};\n\t\t} elsif ($ids->{$id}{name} ne $name) {\n\t\t\twarn \"$makefile: $typename $name id $id is already taken by $ids->{$id}{makefile}\\n\";\n\t\t\treturn 0;\n\t\t}\n\t} elsif ($id != -1) {\n\t\twarn \"$makefile: $typename $name has invalid id $id\\n\";\n\t\treturn 0;\n\t}\n\n\tif (not exists $names->{$name}) {\n\t\t$names->{$name} = {\n\t\t\tid => $id,\n\t\t\tmakefile => $makefile,\n\t\t};\n\t} elsif ($names->{$name}{id} != $id) {\n\t\twarn \"$makefile: id of $typename $name collides with that defined defined in $names->{$name}{makefile}\\n\";\n\t\treturn 0;\n\t}\n\treturn 1;\n}\n\nsub parse_target_metadata($) {\n\tmy $file = shift;\n\tmy ($target, @target, $profile);\n\tmy %target;\n\tmy $makefile;\n\n\topen FILE, \"<$file\" or do {\n\t\twarn \"Can't open file '$file': $!\\n\";\n\t\treturn;\n\t};\n\twhile (<FILE>) {\n\t\tchomp;\n\t\t/^Source-Makefile: \\s*((.+\\/)([^\\/]+)\\/Makefile)\\s*$/ and $makefile = $1;\n\t\t/^Target:\\s*(.+)\\s*$/ and do {\n\t\t\tmy $name = $1;\n\t\t\t$target = {\n\t\t\t\tid => $name,\n\t\t\t\tboard => $name,\n\t\t\t\tmakefile => $makefile,\n\t\t\t\tboardconf => confstr($name),\n\t\t\t\tconf => confstr($name),\n\t\t\t\tprofiles => [],\n\t\t\t\tfeatures => [],\n\t\t\t\tdepends => [],\n\t\t\t\tsubtargets => []\n\t\t\t};\n\t\t\tpush @target, $target;\n\t\t\t$target{$name} = $target;\n\t\t\tif ($name =~ /([^\\/]+)\\/([^\\/]+)/) {\n\t\t\t\tpush @{$target{$1}->{subtargets}}, $2;\n\t\t\t\t$target->{board} = $1;\n\t\t\t\t$target->{boardconf} = confstr($1);\n\t\t\t\t$target->{subtarget} = 1;\n\t\t\t\t$target->{parent} = $target{$1};\n\t\t\t}\n\t\t};\n\t\t/^Target-Name:\\s*(.+)\\s*$/ and $target->{name} = $1;\n\t\t/^Target-Arch:\\s*(.+)\\s*$/ and $target->{arch} = $1;\n\t\t/^Target-Arch-Packages:\\s*(.+)\\s*$/ and $target->{arch_packages} = $1;\n\t\t/^Target-Features:\\s*(.+)\\s*$/ and $target->{features} = [ split(/\\s+/, $1) ];\n\t\t/^Target-Depends:\\s*(.+)\\s*$/ and $target->{depends} = [ split(/\\s+/, $1) ];\n\t\t/^Target-Description:/ and $target->{desc} = get_multiline(*FILE);\n\t\t/^Target-Optimization:\\s*(.+)\\s*$/ and $target->{cflags} = $1;\n\t\t/^CPU-Type:\\s*(.+)\\s*$/ and $target->{cputype} = $1;\n\t\t/^Linux-Version:\\s*(.+)\\s*$/ and $target->{version} = $1;\n\t\t/^Linux-Testing-Version:\\s*(.+)\\s*$/ and $target->{testing_version} = $1;\n\t\t/^Linux-Release:\\s*(.+)\\s*$/ and $target->{release} = $1;\n\t\t/^Linux-Kernel-Arch:\\s*(.+)\\s*$/ and $target->{karch} = $1;\n\t\t/^Default-Subtarget:\\s*(.+)\\s*$/ and $target->{def_subtarget} = $1;\n\t\t/^Default-Packages:\\s*(.+)\\s*$/ and $target->{packages} = [ split(/\\s+/, $1) ];\n\t\t/^Target-Profile:\\s*(.+)\\s*$/ and do {\n\t\t\t$profile = {\n\t\t\t\tid => $1,\n\t\t\t\tname => $1,\n\t\t\t\thas_image_metadata => 0,\n\t\t\t\tsupported_devices => [],\n\t\t\t\tpriority => 999,\n\t\t\t\tpackages => [],\n\t\t\t\tdefault => \"y if TARGET_ALL_PROFILES\"\n\t\t\t};\n\t\t\t$1 =~ /^DEVICE_/ and $target->{has_devices} = 1;\n\t\t\tpush @{$target->{profiles}}, $profile;\n\t\t};\n\t\t/^Target-Profile-Name:\\s*(.+)\\s*$/ and $profile->{name} = $1;\n\t\t/^Target-Profile-hasImageMetadata:\\s*(\\d+)\\s*$/ and $profile->{has_image_metadata} = $1;\n\t\t/^Target-Profile-SupportedDevices:\\s*(.+)\\s*$/ and $profile->{supported_devices} = [ split(/\\s+/, $1) ];\n\t\t/^Target-Profile-Priority:\\s*(\\d+)\\s*$/ and do {\n\t\t\t$profile->{priority} = $1;\n\t\t\t$target->{sort} = 1;\n\t\t};\n\t\t/^Target-Profile-Packages:\\s*(.*)\\s*$/ and $profile->{packages} = [ split(/\\s+/, $1) ];\n\t\t/^Target-Profile-Description:\\s*(.*)\\s*/ and $profile->{desc} = get_multiline(*FILE);\n\t\t/^Target-Profile-Broken:\\s*(.+)\\s*$/ and do {\n\t\t\t$profile->{broken} = 1;\n\t\t\t$profile->{default} = \"n\";\n\t\t};\n\t\t/^Target-Profile-Default:\\s*(.+)\\s*$/ and $profile->{default} = $1;\n\t}\n\tclose FILE;\n\tforeach my $target (@target) {\n\t\tif (@{$target->{subtargets}} > 0) {\n\t\t\t$target->{profiles} = [];\n\t\t\tnext;\n\t\t}\n\t\t@{$target->{profiles}} > 0 or $target->{profiles} = [\n\t\t\t{\n\t\t\t\tid => 'Default',\n\t\t\t\tname => 'Default',\n\t\t\t\tpackages => []\n\t\t\t}\n\t\t];\n\n\t\t$target->{sort} and @{$target->{profiles}} = sort {\n\t\t\t$a->{priority} <=> $b->{priority} or\n\t\t\t$a->{name} cmp $b->{name};\n\t\t} @{$target->{profiles}};\n\t}\n\treturn @target;\n}\n\nsub clear_packages() {\n\t%package = ();\n\t%vpackage = ();\n\t%srcpackage = ();\n\t%category = ();\n\t%overrides = ();\n\t%usernames = ();\n\t%groupnames = ();\n}\n\nsub parse_package_metadata($) {\n\tmy $file = shift;\n\tmy $pkg;\n\tmy $src;\n\tmy $override;\n\tmy %ignore = map { $_ => 1 } @ignore;\n\n\topen FILE, \"<$file\" or do {\n\t\twarn \"Cannot open '$file': $!\\n\";\n\t\treturn undef;\n\t};\n\twhile (<FILE>) {\n\t\tchomp;\n\t\t/^Source-Makefile: \\s*((?:package\\/)?((?:.+\\/)?([^\\/]+))\\/Makefile)\\s*$/ and do {\n\t\t\t$src = {\n\t\t\t\tmakefile => $1,\n\t\t\t\tpath => $2,\n\t\t\t\tname => $3,\n\t\t\t\tignore => $ignore{$3},\n\t\t\t\tpackages => [],\n\t\t\t\tbuildtypes => [],\n\t\t\t\tbuilddepends => [],\n\t\t\t};\n\t\t\t$srcpackage{$3} = $src;\n\t\t\t$override = \"\";\n\t\t\tundef $pkg;\n\t\t};\n\t\t/^Override: \\s*(.+?)\\s*$/ and do {\n\t\t\t$override = $1;\n\t\t\t$overrides{$src->{name}} = 1;\n\t\t};\n\t\tnext unless $src;\n\t\t/^Package:\\s*(.+?)\\s*$/ and do {\n\t\t\t$pkg = {};\n\t\t\t$pkg->{src} = $src;\n\t\t\t$pkg->{name} = $1;\n\t\t\t$pkg->{title} = \"\";\n\t\t\t$pkg->{depends} = [];\n\t\t\t$pkg->{mdepends} = [];\n\t\t\t$pkg->{provides} = [$1];\n\t\t\t$pkg->{tristate} = 1;\n\t\t\t$pkg->{override} = $override;\n\t\t\t$package{$1} = $pkg;\n\t\t\tpush @{$src->{packages}}, $pkg;\n\n\t\t\t$vpackage{$1} or $vpackage{$1} = [];\n\t\t\tunshift @{$vpackage{$1}}, $pkg;\n\t\t};\n\t\t/^Build-Depends: \\s*(.+)\\s*$/ and $src->{builddepends} = [ split /\\s+/, $1 ];\n\t\t/^Build-Depends\\/(\\w+): \\s*(.+)\\s*$/ and $src->{\"builddepends/$1\"} = [ split /\\s+/, $2 ];\n\t\t/^Build-Types:\\s*(.+)\\s*$/ and $src->{buildtypes} = [ split /\\s+/, $1 ];\n\t\tnext unless $pkg;\n\t\t/^Version: \\s*(.+)\\s*$/ and $pkg->{version} = $1;\n\t\t/^Title: \\s*(.+)\\s*$/ and $pkg->{title} = $1;\n\t\t/^Menu: \\s*(.+)\\s*$/ and $pkg->{menu} = $1;\n\t\t/^Submenu: \\s*(.+)\\s*$/ and $pkg->{submenu} = $1;\n\t\t/^Submenu-Depends: \\s*(.+)\\s*$/ and $pkg->{submenudep} = $1;\n\t\t/^Source: \\s*(.+)\\s*$/ and $pkg->{source} = $1;\n\t\t/^License: \\s*(.+)\\s*$/ and $pkg->{license} = $1;\n\t\t/^LicenseFiles: \\s*(.+)\\s*$/ and $pkg->{licensefiles} = $1;\n\t\t/^Default: \\s*(.+)\\s*$/ and $pkg->{default} = $1;\n\t\t/^Provides: \\s*(.+)\\s*$/ and do {\n\t\t\tmy @vpkg = split /\\s+/, $1;\n\t\t\t@{$pkg->{provides}} = ($pkg->{name}, @vpkg);\n\t\t\tforeach my $vpkg (@vpkg) {\n\t\t\t\tnext if ($vpkg eq $pkg->{name});\n\t\t\t\t$vpackage{$vpkg} or $vpackage{$vpkg} = [];\n\t\t\t\tpush @{$vpackage{$vpkg}}, $pkg;\n\t\t\t}\n\t\t};\n\t\t/^Menu-Depends: \\s*(.+)\\s*$/ and $pkg->{mdepends} = [ split /\\s+/, $1 ];\n\t\t/^Depends: \\s*(.+)\\s*$/ and $pkg->{depends} = [ split /\\s+/, $1 ];\n\t\t/^Conflicts: \\s*(.+)\\s*$/ and $pkg->{conflicts} = [ split /\\s+/, $1 ];\n\t\t/^Hidden: \\s*(.+)\\s*$/ and $pkg->{hidden} = 1;\n\t\t/^Build-Variant: \\s*([\\w\\-]+)\\s*/ and $pkg->{variant} = $1;\n\t\t/^Default-Variant: .*/ and $pkg->{variant_default} = 1;\n\t\t/^Build-Only: \\s*(.+)\\s*$/ and $pkg->{buildonly} = 1;\n\t\t/^Repository:\\s*(.+?)\\s*$/ and $pkg->{repository} = $1;\n\t\t/^Category: \\s*(.+)\\s*$/ and do {\n\t\t\t$pkg->{category} = $1;\n\t\t\tdefined $category{$1} or $category{$1} = {};\n\t\t\tdefined $category{$1}{$src->{name}} or $category{$1}{$src->{name}} = [];\n\t\t\tpush @{$category{$1}{$src->{name}}}, $pkg;\n\t\t};\n\t\t/^Description: \\s*(.*)\\s*$/ and $pkg->{description} = \"\\t\\t $1\\n\". get_multiline(*FILE, \"\\t\\t \");\n\t\t/^Type: \\s*(.+)\\s*$/ and do {\n\t\t\t$pkg->{type} = [ split /\\s+/, $1 ];\n\t\t\tundef $pkg->{tristate};\n\t\t\tforeach my $type (@{$pkg->{type}}) {\n\t\t\t\t$type =~ /ipkg/ and $pkg->{tristate} = 1;\n\t\t\t}\n\t\t};\n\t\t/^Config:\\s*(.*)\\s*$/ and $pkg->{config} = \"$1\\n\".get_multiline(*FILE, \"\\t\");\n\t\t/^Prereq-Check:/ and $pkg->{prereq} = 1;\n\t\t/^Maintainer: \\s*(.+)\\s*$/ and $pkg->{maintainer} = [ split /, /, $1 ];\n\t\t/^Require-User:\\s*(.*?)\\s*$/ and do {\n\t\t\tmy @ugspecs = split /\\s+/, $1;\n\n\t\t\tfor my $ugspec (@ugspecs) {\n\t\t\t\tmy @ugspec = split /:/, $ugspec, 3;\n\t\t\t\tif ($ugspec[0]) {\n\t\t\t\t\tparse_package_metadata_usergroup($src->{makefile}, \"user\", \\%usernames, \\%userids, $ugspec[0]) or return 0;\n\t\t\t\t}\n\t\t\t\tif ($ugspec[1]) {\n\t\t\t\t\tparse_package_metadata_usergroup($src->{makefile}, \"group\", \\%groupnames, \\%groupids, $ugspec[1]) or return 0;\n\t\t\t\t}\n\t\t\t\tif ($ugspec[2]) {\n\t\t\t\t\tmy @addngroups = split /,/, $ugspec[2];\n\t\t\t\t\tfor my $addngroup (@addngroups) {\n\t\t\t\t\t\tparse_package_metadata_usergroup($src->{makefile}, \"group\", \\%groupnames, \\%groupids, $addngroup) or return 0;\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t};\n\t}\n\tclose FILE;\n\treturn 1;\n}\n\n1;\n"
  },
  {
    "path": "scripts/mkhash.c",
    "content": "/*\n * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n * -- MD5 code:\n *\n * This is an OpenSSL-compatible implementation of the RSA Data Security, Inc.\n * MD5 Message-Digest Algorithm (RFC 1321).\n *\n * Homepage:\n * http://openwall.info/wiki/people/solar/software/public-domain-source-code/md5\n *\n * Author:\n * Alexander Peslyak, better known as Solar Designer <solar at openwall.com>\n *\n * This software was written by Alexander Peslyak in 2001.  No copyright is\n * claimed, and the software is hereby placed in the public domain.\n * In case this attempt to disclaim copyright and place the software in the\n * public domain is deemed null and void, then the software is\n * Copyright (c) 2001 Alexander Peslyak and it is hereby released to the\n * general public under the following terms:\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted.\n *\n * There's ABSOLUTELY NO WARRANTY, express or implied.\n *\n * (This is a heavily cut-down \"BSD license\".)\n *\n * This differs from Colin Plumb's older public domain implementation in that\n * no exactly 32-bit integer data type is required (any 32-bit or wider\n * unsigned integer data type will do), there's no compile-time endianness\n * configuration, and the function prototypes match OpenSSL's.  No code from\n * Colin Plumb's implementation has been reused; this comment merely compares\n * the properties of the two independent implementations.\n *\n * The primary goals of this implementation are portability and ease of use.\n * It is meant to be fast, but not as fast as possible.  Some known\n * optimizations are not included to reduce source code size and avoid\n * compile-time configuration.\n *\n * -- SHA256 Code:\n *\n * Copyright 2005 Colin Percival\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n *\n * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n */\n\n\n\n#ifndef __FreeBSD__\n#include <endian.h>\n#else\n#include <sys/endian.h>\n#endif\n\n#include <stdio.h>\n#include <string.h>\n#include <stdint.h>\n#include <stdbool.h>\n#include <unistd.h>\n#include <sys/stat.h>\n\n#define ARRAY_SIZE(_n) (sizeof(_n) / sizeof((_n)[0]))\n\n#ifndef __FreeBSD__\nstatic void\nbe32enc(void *buf, uint32_t u)\n{\n\tuint8_t *p = buf;\n\n\tp[0] = ((uint8_t) ((u >> 24) & 0xff));\n\tp[1] = ((uint8_t) ((u >> 16) & 0xff));\n\tp[2] = ((uint8_t) ((u >> 8) & 0xff));\n\tp[3] = ((uint8_t) (u & 0xff));\n}\n\nstatic void\nbe64enc(void *buf, uint64_t u)\n{\n\tuint8_t *p = buf;\n\n\tbe32enc(p, ((uint32_t) (u >> 32)));\n\tbe32enc(p + 4, ((uint32_t) (u & 0xffffffffULL)));\n}\n\n\nstatic uint16_t\nbe16dec(const void *buf)\n{\n\tconst uint8_t *p = buf;\n\n\treturn (((uint16_t) p[0]) << 8) | p[1];\n}\n\nstatic uint32_t\nbe32dec(const void *buf)\n{\n\tconst uint8_t *p = buf;\n\n\treturn (((uint32_t) be16dec(p)) << 16) | be16dec(p + 2);\n}\n#endif\n\n#define MD5_DIGEST_LENGTH\t16\n\ntypedef struct MD5_CTX {\n\tuint32_t lo, hi;\n\tuint32_t a, b, c, d;\n\tunsigned char buffer[64];\n} MD5_CTX;\n\n/*\n * The basic MD5 functions.\n *\n * F and G are optimized compared to their RFC 1321 definitions for\n * architectures that lack an AND-NOT instruction, just like in Colin Plumb's\n * implementation.\n */\n#define F(x, y, z)\t\t\t((z) ^ ((x) & ((y) ^ (z))))\n#define G(x, y, z)\t\t\t((y) ^ ((z) & ((x) ^ (y))))\n#define H(x, y, z)\t\t\t(((x) ^ (y)) ^ (z))\n#define H2(x, y, z)\t\t\t((x) ^ ((y) ^ (z)))\n#define I(x, y, z)\t\t\t((y) ^ ((x) | ~(z)))\n\n/*\n * The MD5 transformation for all four rounds.\n */\n#define STEP(f, a, b, c, d, x, t, s) \\\n\t(a) += f((b), (c), (d)) + (x) + (t); \\\n\t(a) = (((a) << (s)) | (((a) & 0xffffffff) >> (32 - (s)))); \\\n\t(a) += (b);\n\n/*\n * SET reads 4 input bytes in little-endian byte order and stores them\n * in a properly aligned word in host byte order.\n */\n#if __BYTE_ORDER == __LITTLE_ENDIAN\n#define SET(n) \\\n\t(*(uint32_t *)&ptr[(n) * 4])\n#define GET(n) \\\n\tSET(n)\n#else\n#define SET(n) \\\n\t(block[(n)] = \\\n\t(uint32_t)ptr[(n) * 4] | \\\n\t((uint32_t)ptr[(n) * 4 + 1] << 8) | \\\n\t((uint32_t)ptr[(n) * 4 + 2] << 16) | \\\n\t((uint32_t)ptr[(n) * 4 + 3] << 24))\n#define GET(n) \\\n\t(block[(n)])\n#endif\n\n/*\n * This processes one or more 64-byte data blocks, but does NOT update\n * the bit counters.  There are no alignment requirements.\n */\nstatic const void *MD5_body(MD5_CTX *ctx, const void *data, unsigned long size)\n{\n\tconst unsigned char *ptr;\n\tuint32_t a, b, c, d;\n\tuint32_t saved_a, saved_b, saved_c, saved_d;\n#if __BYTE_ORDER != __LITTLE_ENDIAN\n\tuint32_t block[16];\n#endif\n\n\tptr = (const unsigned char *)data;\n\n\ta = ctx->a;\n\tb = ctx->b;\n\tc = ctx->c;\n\td = ctx->d;\n\n\tdo {\n\t\tsaved_a = a;\n\t\tsaved_b = b;\n\t\tsaved_c = c;\n\t\tsaved_d = d;\n\n/* Round 1 */\n\t\tSTEP(F, a, b, c, d, SET(0), 0xd76aa478, 7)\n\t\tSTEP(F, d, a, b, c, SET(1), 0xe8c7b756, 12)\n\t\tSTEP(F, c, d, a, b, SET(2), 0x242070db, 17)\n\t\tSTEP(F, b, c, d, a, SET(3), 0xc1bdceee, 22)\n\t\tSTEP(F, a, b, c, d, SET(4), 0xf57c0faf, 7)\n\t\tSTEP(F, d, a, b, c, SET(5), 0x4787c62a, 12)\n\t\tSTEP(F, c, d, a, b, SET(6), 0xa8304613, 17)\n\t\tSTEP(F, b, c, d, a, SET(7), 0xfd469501, 22)\n\t\tSTEP(F, a, b, c, d, SET(8), 0x698098d8, 7)\n\t\tSTEP(F, d, a, b, c, SET(9), 0x8b44f7af, 12)\n\t\tSTEP(F, c, d, a, b, SET(10), 0xffff5bb1, 17)\n\t\tSTEP(F, b, c, d, a, SET(11), 0x895cd7be, 22)\n\t\tSTEP(F, a, b, c, d, SET(12), 0x6b901122, 7)\n\t\tSTEP(F, d, a, b, c, SET(13), 0xfd987193, 12)\n\t\tSTEP(F, c, d, a, b, SET(14), 0xa679438e, 17)\n\t\tSTEP(F, b, c, d, a, SET(15), 0x49b40821, 22)\n\n/* Round 2 */\n\t\tSTEP(G, a, b, c, d, GET(1), 0xf61e2562, 5)\n\t\tSTEP(G, d, a, b, c, GET(6), 0xc040b340, 9)\n\t\tSTEP(G, c, d, a, b, GET(11), 0x265e5a51, 14)\n\t\tSTEP(G, b, c, d, a, GET(0), 0xe9b6c7aa, 20)\n\t\tSTEP(G, a, b, c, d, GET(5), 0xd62f105d, 5)\n\t\tSTEP(G, d, a, b, c, GET(10), 0x02441453, 9)\n\t\tSTEP(G, c, d, a, b, GET(15), 0xd8a1e681, 14)\n\t\tSTEP(G, b, c, d, a, GET(4), 0xe7d3fbc8, 20)\n\t\tSTEP(G, a, b, c, d, GET(9), 0x21e1cde6, 5)\n\t\tSTEP(G, d, a, b, c, GET(14), 0xc33707d6, 9)\n\t\tSTEP(G, c, d, a, b, GET(3), 0xf4d50d87, 14)\n\t\tSTEP(G, b, c, d, a, GET(8), 0x455a14ed, 20)\n\t\tSTEP(G, a, b, c, d, GET(13), 0xa9e3e905, 5)\n\t\tSTEP(G, d, a, b, c, GET(2), 0xfcefa3f8, 9)\n\t\tSTEP(G, c, d, a, b, GET(7), 0x676f02d9, 14)\n\t\tSTEP(G, b, c, d, a, GET(12), 0x8d2a4c8a, 20)\n\n/* Round 3 */\n\t\tSTEP(H, a, b, c, d, GET(5), 0xfffa3942, 4)\n\t\tSTEP(H2, d, a, b, c, GET(8), 0x8771f681, 11)\n\t\tSTEP(H, c, d, a, b, GET(11), 0x6d9d6122, 16)\n\t\tSTEP(H2, b, c, d, a, GET(14), 0xfde5380c, 23)\n\t\tSTEP(H, a, b, c, d, GET(1), 0xa4beea44, 4)\n\t\tSTEP(H2, d, a, b, c, GET(4), 0x4bdecfa9, 11)\n\t\tSTEP(H, c, d, a, b, GET(7), 0xf6bb4b60, 16)\n\t\tSTEP(H2, b, c, d, a, GET(10), 0xbebfbc70, 23)\n\t\tSTEP(H, a, b, c, d, GET(13), 0x289b7ec6, 4)\n\t\tSTEP(H2, d, a, b, c, GET(0), 0xeaa127fa, 11)\n\t\tSTEP(H, c, d, a, b, GET(3), 0xd4ef3085, 16)\n\t\tSTEP(H2, b, c, d, a, GET(6), 0x04881d05, 23)\n\t\tSTEP(H, a, b, c, d, GET(9), 0xd9d4d039, 4)\n\t\tSTEP(H2, d, a, b, c, GET(12), 0xe6db99e5, 11)\n\t\tSTEP(H, c, d, a, b, GET(15), 0x1fa27cf8, 16)\n\t\tSTEP(H2, b, c, d, a, GET(2), 0xc4ac5665, 23)\n\n/* Round 4 */\n\t\tSTEP(I, a, b, c, d, GET(0), 0xf4292244, 6)\n\t\tSTEP(I, d, a, b, c, GET(7), 0x432aff97, 10)\n\t\tSTEP(I, c, d, a, b, GET(14), 0xab9423a7, 15)\n\t\tSTEP(I, b, c, d, a, GET(5), 0xfc93a039, 21)\n\t\tSTEP(I, a, b, c, d, GET(12), 0x655b59c3, 6)\n\t\tSTEP(I, d, a, b, c, GET(3), 0x8f0ccc92, 10)\n\t\tSTEP(I, c, d, a, b, GET(10), 0xffeff47d, 15)\n\t\tSTEP(I, b, c, d, a, GET(1), 0x85845dd1, 21)\n\t\tSTEP(I, a, b, c, d, GET(8), 0x6fa87e4f, 6)\n\t\tSTEP(I, d, a, b, c, GET(15), 0xfe2ce6e0, 10)\n\t\tSTEP(I, c, d, a, b, GET(6), 0xa3014314, 15)\n\t\tSTEP(I, b, c, d, a, GET(13), 0x4e0811a1, 21)\n\t\tSTEP(I, a, b, c, d, GET(4), 0xf7537e82, 6)\n\t\tSTEP(I, d, a, b, c, GET(11), 0xbd3af235, 10)\n\t\tSTEP(I, c, d, a, b, GET(2), 0x2ad7d2bb, 15)\n\t\tSTEP(I, b, c, d, a, GET(9), 0xeb86d391, 21)\n\n\t\ta += saved_a;\n\t\tb += saved_b;\n\t\tc += saved_c;\n\t\td += saved_d;\n\n\t\tptr += 64;\n\t} while (size -= 64);\n\n\tctx->a = a;\n\tctx->b = b;\n\tctx->c = c;\n\tctx->d = d;\n\n\treturn ptr;\n}\n\nvoid MD5_begin(MD5_CTX *ctx)\n{\n\tctx->a = 0x67452301;\n\tctx->b = 0xefcdab89;\n\tctx->c = 0x98badcfe;\n\tctx->d = 0x10325476;\n\n\tctx->lo = 0;\n\tctx->hi = 0;\n}\n\nstatic void\nMD5_hash(const void *data, size_t size, MD5_CTX *ctx)\n{\n\tuint32_t saved_lo;\n\tunsigned long used, available;\n\n\tsaved_lo = ctx->lo;\n\tif ((ctx->lo = (saved_lo + size) & 0x1fffffff) < saved_lo)\n\t\tctx->hi++;\n\tctx->hi += size >> 29;\n\n\tused = saved_lo & 0x3f;\n\n\tif (used) {\n\t\tavailable = 64 - used;\n\n\t\tif (size < available) {\n\t\t\tmemcpy(&ctx->buffer[used], data, size);\n\t\t\treturn;\n\t\t}\n\n\t\tmemcpy(&ctx->buffer[used], data, available);\n\t\tdata = (const unsigned char *)data + available;\n\t\tsize -= available;\n\t\tMD5_body(ctx, ctx->buffer, 64);\n\t}\n\n\tif (size >= 64) {\n\t\tdata = MD5_body(ctx, data, size & ~((size_t) 0x3f));\n\t\tsize &= 0x3f;\n\t}\n\n\tmemcpy(ctx->buffer, data, size);\n}\n\nstatic void\nMD5_end(void *resbuf, MD5_CTX *ctx)\n{\n\tunsigned char *result = resbuf;\n\tunsigned long used, available;\n\n\tused = ctx->lo & 0x3f;\n\n\tctx->buffer[used++] = 0x80;\n\n\tavailable = 64 - used;\n\n\tif (available < 8) {\n\t\tmemset(&ctx->buffer[used], 0, available);\n\t\tMD5_body(ctx, ctx->buffer, 64);\n\t\tused = 0;\n\t\tavailable = 64;\n\t}\n\n\tmemset(&ctx->buffer[used], 0, available - 8);\n\n\tctx->lo <<= 3;\n\tctx->buffer[56] = ctx->lo;\n\tctx->buffer[57] = ctx->lo >> 8;\n\tctx->buffer[58] = ctx->lo >> 16;\n\tctx->buffer[59] = ctx->lo >> 24;\n\tctx->buffer[60] = ctx->hi;\n\tctx->buffer[61] = ctx->hi >> 8;\n\tctx->buffer[62] = ctx->hi >> 16;\n\tctx->buffer[63] = ctx->hi >> 24;\n\n\tMD5_body(ctx, ctx->buffer, 64);\n\n\tresult[0] = ctx->a;\n\tresult[1] = ctx->a >> 8;\n\tresult[2] = ctx->a >> 16;\n\tresult[3] = ctx->a >> 24;\n\tresult[4] = ctx->b;\n\tresult[5] = ctx->b >> 8;\n\tresult[6] = ctx->b >> 16;\n\tresult[7] = ctx->b >> 24;\n\tresult[8] = ctx->c;\n\tresult[9] = ctx->c >> 8;\n\tresult[10] = ctx->c >> 16;\n\tresult[11] = ctx->c >> 24;\n\tresult[12] = ctx->d;\n\tresult[13] = ctx->d >> 8;\n\tresult[14] = ctx->d >> 16;\n\tresult[15] = ctx->d >> 24;\n\n\tmemset(ctx, 0, sizeof(*ctx));\n}\n\n#define SHA256_BLOCK_LENGTH\t\t64\n#define SHA256_DIGEST_LENGTH\t\t32\n#define SHA256_DIGEST_STRING_LENGTH\t(SHA256_DIGEST_LENGTH * 2 + 1)\n\ntypedef struct SHA256Context {\n\tuint32_t state[8];\n\tuint64_t count;\n\tuint8_t buf[SHA256_BLOCK_LENGTH];\n} SHA256_CTX;\n\n#if BYTE_ORDER == BIG_ENDIAN\n\n/* Copy a vector of big-endian uint32_t into a vector of bytes */\n#define be32enc_vect(dst, src, len)\t\\\n\tmemcpy((void *)dst, (const void *)src, (size_t)len)\n\n/* Copy a vector of bytes into a vector of big-endian uint32_t */\n#define be32dec_vect(dst, src, len)\t\\\n\tmemcpy((void *)dst, (const void *)src, (size_t)len)\n\n#else /* BYTE_ORDER != BIG_ENDIAN */\n\n/*\n * Encode a length len/4 vector of (uint32_t) into a length len vector of\n * (unsigned char) in big-endian form.  Assumes len is a multiple of 4.\n */\nstatic void\nbe32enc_vect(unsigned char *dst, const uint32_t *src, size_t len)\n{\n\tsize_t i;\n\n\tfor (i = 0; i < len / 4; i++)\n\t\tbe32enc(dst + i * 4, src[i]);\n}\n\n/*\n * Decode a big-endian length len vector of (unsigned char) into a length\n * len/4 vector of (uint32_t).  Assumes len is a multiple of 4.\n */\nstatic void\nbe32dec_vect(uint32_t *dst, const unsigned char *src, size_t len)\n{\n\tsize_t i;\n\n\tfor (i = 0; i < len / 4; i++)\n\t\tdst[i] = be32dec(src + i * 4);\n}\n\n#endif /* BYTE_ORDER != BIG_ENDIAN */\n\n\n/* Elementary functions used by SHA256 */\n#define Ch(x, y, z)\t((x & (y ^ z)) ^ z)\n#define Maj(x, y, z)\t((x & (y | z)) | (y & z))\n#define ROTR(x, n)\t((x >> n) | (x << (32 - n)))\n\n/*\n * SHA256 block compression function.  The 256-bit state is transformed via\n * the 512-bit input block to produce a new state.\n */\nstatic void\nSHA256_Transform(uint32_t * state, const unsigned char block[64])\n{\n\t/* SHA256 round constants. */\n\tstatic const uint32_t K[64] = {\n\t\t0x428a2f98, 0x71374491, 0xb5c0fbcf, 0xe9b5dba5,\n\t\t0x3956c25b, 0x59f111f1, 0x923f82a4, 0xab1c5ed5,\n\t\t0xd807aa98, 0x12835b01, 0x243185be, 0x550c7dc3,\n\t\t0x72be5d74, 0x80deb1fe, 0x9bdc06a7, 0xc19bf174,\n\t\t0xe49b69c1, 0xefbe4786, 0x0fc19dc6, 0x240ca1cc,\n\t\t0x2de92c6f, 0x4a7484aa, 0x5cb0a9dc, 0x76f988da,\n\t\t0x983e5152, 0xa831c66d, 0xb00327c8, 0xbf597fc7,\n\t\t0xc6e00bf3, 0xd5a79147, 0x06ca6351, 0x14292967,\n\t\t0x27b70a85, 0x2e1b2138, 0x4d2c6dfc, 0x53380d13,\n\t\t0x650a7354, 0x766a0abb, 0x81c2c92e, 0x92722c85,\n\t\t0xa2bfe8a1, 0xa81a664b, 0xc24b8b70, 0xc76c51a3,\n\t\t0xd192e819, 0xd6990624, 0xf40e3585, 0x106aa070,\n\t\t0x19a4c116, 0x1e376c08, 0x2748774c, 0x34b0bcb5,\n\t\t0x391c0cb3, 0x4ed8aa4a, 0x5b9cca4f, 0x682e6ff3,\n\t\t0x748f82ee, 0x78a5636f, 0x84c87814, 0x8cc70208,\n\t\t0x90befffa, 0xa4506ceb, 0xbef9a3f7, 0xc67178f2\n\t};\n\tuint32_t W[64];\n\tuint32_t S[8];\n\tint i;\n\n#define S0(x)\t\t(ROTR(x, 2) ^ ROTR(x, 13) ^ ROTR(x, 22))\n#define S1(x)\t\t(ROTR(x, 6) ^ ROTR(x, 11) ^ ROTR(x, 25))\n#define s0(x)\t\t(ROTR(x, 7) ^ ROTR(x, 18) ^ (x >> 3))\n#define s1(x)\t\t(ROTR(x, 17) ^ ROTR(x, 19) ^ (x >> 10))\n\n/* SHA256 round function */\n#define RND(a, b, c, d, e, f, g, h, k)\t\t\t\\\n\th += S1(e) + Ch(e, f, g) + k;\t\t\t\\\n\td += h;\t\t\t\t\t\t\\\n\th += S0(a) + Maj(a, b, c);\n\n/* Adjusted round function for rotating state */\n#define RNDr(S, W, i, ii)\t\t\t\\\n\tRND(S[(64 - i) % 8], S[(65 - i) % 8],\t\\\n\t    S[(66 - i) % 8], S[(67 - i) % 8],\t\\\n\t    S[(68 - i) % 8], S[(69 - i) % 8],\t\\\n\t    S[(70 - i) % 8], S[(71 - i) % 8],\t\\\n\t    W[i + ii] + K[i + ii])\n\n/* Message schedule computation */\n#define MSCH(W, ii, i)\t\t\t\t\\\n\tW[i + ii + 16] = s1(W[i + ii + 14]) + W[i + ii + 9] + s0(W[i + ii + 1]) + W[i + ii]\n\n\t/* 1. Prepare the first part of the message schedule W. */\n\tbe32dec_vect(W, block, 64);\n\n\t/* 2. Initialize working variables. */\n\tmemcpy(S, state, 32);\n\n\t/* 3. Mix. */\n\tfor (i = 0; i < 64; i += 16) {\n\t\tRNDr(S, W, 0, i);\n\t\tRNDr(S, W, 1, i);\n\t\tRNDr(S, W, 2, i);\n\t\tRNDr(S, W, 3, i);\n\t\tRNDr(S, W, 4, i);\n\t\tRNDr(S, W, 5, i);\n\t\tRNDr(S, W, 6, i);\n\t\tRNDr(S, W, 7, i);\n\t\tRNDr(S, W, 8, i);\n\t\tRNDr(S, W, 9, i);\n\t\tRNDr(S, W, 10, i);\n\t\tRNDr(S, W, 11, i);\n\t\tRNDr(S, W, 12, i);\n\t\tRNDr(S, W, 13, i);\n\t\tRNDr(S, W, 14, i);\n\t\tRNDr(S, W, 15, i);\n\n\t\tif (i == 48)\n\t\t\tbreak;\n\t\tMSCH(W, 0, i);\n\t\tMSCH(W, 1, i);\n\t\tMSCH(W, 2, i);\n\t\tMSCH(W, 3, i);\n\t\tMSCH(W, 4, i);\n\t\tMSCH(W, 5, i);\n\t\tMSCH(W, 6, i);\n\t\tMSCH(W, 7, i);\n\t\tMSCH(W, 8, i);\n\t\tMSCH(W, 9, i);\n\t\tMSCH(W, 10, i);\n\t\tMSCH(W, 11, i);\n\t\tMSCH(W, 12, i);\n\t\tMSCH(W, 13, i);\n\t\tMSCH(W, 14, i);\n\t\tMSCH(W, 15, i);\n\t}\n\n#undef S0\n#undef s0\n#undef S1\n#undef s1\n#undef RND\n#undef RNDr\n#undef MSCH\n\n\t/* 4. Mix local working variables into global state */\n\tfor (i = 0; i < 8; i++)\n\t\tstate[i] += S[i];\n}\n\nstatic unsigned char PAD[64] = {\n\t0x80, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\n\t0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\n\t0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\n\t0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0\n};\n\n/* Add padding and terminating bit-count. */\nstatic void\nSHA256_Pad(SHA256_CTX * ctx)\n{\n\tsize_t r;\n\n\t/* Figure out how many bytes we have buffered. */\n\tr = (ctx->count >> 3) & 0x3f;\n\n\t/* Pad to 56 mod 64, transforming if we finish a block en route. */\n\tif (r < 56) {\n\t\t/* Pad to 56 mod 64. */\n\t\tmemcpy(&ctx->buf[r], PAD, 56 - r);\n\t} else {\n\t\t/* Finish the current block and mix. */\n\t\tmemcpy(&ctx->buf[r], PAD, 64 - r);\n\t\tSHA256_Transform(ctx->state, ctx->buf);\n\n\t\t/* The start of the final block is all zeroes. */\n\t\tmemset(&ctx->buf[0], 0, 56);\n\t}\n\n\t/* Add the terminating bit-count. */\n\tbe64enc(&ctx->buf[56], ctx->count);\n\n\t/* Mix in the final block. */\n\tSHA256_Transform(ctx->state, ctx->buf);\n}\n\n/* SHA-256 initialization.  Begins a SHA-256 operation. */\nstatic void\nSHA256_Init(SHA256_CTX * ctx)\n{\n\n\t/* Zero bits processed so far */\n\tctx->count = 0;\n\n\t/* Magic initialization constants */\n\tctx->state[0] = 0x6A09E667;\n\tctx->state[1] = 0xBB67AE85;\n\tctx->state[2] = 0x3C6EF372;\n\tctx->state[3] = 0xA54FF53A;\n\tctx->state[4] = 0x510E527F;\n\tctx->state[5] = 0x9B05688C;\n\tctx->state[6] = 0x1F83D9AB;\n\tctx->state[7] = 0x5BE0CD19;\n}\n\n/* Add bytes into the hash */\nstatic void\nSHA256_Update(SHA256_CTX * ctx, const void *in, size_t len)\n{\n\tuint64_t bitlen;\n\tuint32_t r;\n\tconst unsigned char *src = in;\n\n\t/* Number of bytes left in the buffer from previous updates */\n\tr = (ctx->count >> 3) & 0x3f;\n\n\t/* Convert the length into a number of bits */\n\tbitlen = len << 3;\n\n\t/* Update number of bits */\n\tctx->count += bitlen;\n\n\t/* Handle the case where we don't need to perform any transforms */\n\tif (len < 64 - r) {\n\t\tmemcpy(&ctx->buf[r], src, len);\n\t\treturn;\n\t}\n\n\t/* Finish the current block */\n\tmemcpy(&ctx->buf[r], src, 64 - r);\n\tSHA256_Transform(ctx->state, ctx->buf);\n\tsrc += 64 - r;\n\tlen -= 64 - r;\n\n\t/* Perform complete blocks */\n\twhile (len >= 64) {\n\t\tSHA256_Transform(ctx->state, src);\n\t\tsrc += 64;\n\t\tlen -= 64;\n\t}\n\n\t/* Copy left over data into buffer */\n\tmemcpy(ctx->buf, src, len);\n}\n\n/*\n * SHA-256 finalization.  Pads the input data, exports the hash value,\n * and clears the context state.\n */\nstatic void\nSHA256_Final(unsigned char digest[static SHA256_DIGEST_LENGTH], SHA256_CTX *ctx)\n{\n\t/* Add padding */\n\tSHA256_Pad(ctx);\n\n\t/* Write the hash */\n\tbe32enc_vect(digest, ctx->state, SHA256_DIGEST_LENGTH);\n\n\t/* Clear the context state */\n\tmemset(ctx, 0, sizeof(*ctx));\n}\n\nstatic void *hash_buf(FILE *f, int *len)\n{\n\tstatic char buf[1024];\n\n\t*len = fread(buf, 1, sizeof(buf), f);\n\n\treturn *len > 0 ? buf : NULL;\n}\n\nstatic char *hash_string(unsigned char *buf, int len)\n{\n\tstatic char str[SHA256_DIGEST_LENGTH * 2 + 1];\n\tint i;\n\n\tif (len * 2 + 1 > sizeof(str))\n\t\treturn NULL;\n\n\tfor (i = 0; i < len; i++)\n\t\tsprintf(&str[i * 2], \"%02x\", buf[i]);\n\n\treturn str;\n}\n\nstatic const char *md5_hash(FILE *f)\n{\n\tMD5_CTX ctx;\n\tunsigned char val[MD5_DIGEST_LENGTH];\n\tvoid *buf;\n\tint len;\n\n\tMD5_begin(&ctx);\n\twhile ((buf = hash_buf(f, &len)) != NULL)\n\t\tMD5_hash(buf, len, &ctx);\n\tMD5_end(val, &ctx);\n\n\treturn hash_string(val, MD5_DIGEST_LENGTH);\n}\n\nstatic const char *sha256_hash(FILE *f)\n{\n\tSHA256_CTX ctx;\n\tunsigned char val[SHA256_DIGEST_LENGTH];\n\tvoid *buf;\n\tint len;\n\n\tSHA256_Init(&ctx);\n\twhile ((buf = hash_buf(f, &len)) != NULL)\n\t\tSHA256_Update(&ctx, buf, len);\n\tSHA256_Final(val, &ctx);\n\n\treturn hash_string(val, SHA256_DIGEST_LENGTH);\n}\n\n\nstruct hash_type {\n\tconst char *name;\n\tconst char *(*func)(FILE *f);\n\tint len;\n};\n\nstruct hash_type types[] = {\n\t{ \"md5\", md5_hash, MD5_DIGEST_LENGTH },\n\t{ \"sha256\", sha256_hash, SHA256_DIGEST_LENGTH },\n};\n\n\nstatic int usage(const char *progname)\n{\n\tint i;\n\n\tfprintf(stderr, \"Usage: %s <hash type> [options] [<file>...]\\n\"\n\t\t\"Options:\\n\"\n\t\t\"\t-n\t\tPrint filename(s)\\n\"\n\t\t\"\t-N\t\tSuppress trailing newline\\n\"\n\t\t\"\\n\"\n\t\t\"Supported hash types:\", progname);\n\n\tfor (i = 0; i < ARRAY_SIZE(types); i++)\n\t\tfprintf(stderr, \"%s %s\", i ? \",\" : \"\", types[i].name);\n\n\tfprintf(stderr, \"\\n\");\n\treturn 1;\n}\n\nstatic struct hash_type *get_hash_type(const char *name)\n{\n\tint i;\n\n\tfor (i = 0; i < ARRAY_SIZE(types); i++) {\n\t\tstruct hash_type *t = &types[i];\n\n\t\tif (!strcmp(t->name, name))\n\t\t\treturn t;\n\t}\n\treturn NULL;\n}\n\n\nstatic int hash_file(struct hash_type *t, const char *filename, bool add_filename,\n\tbool no_newline)\n{\n\tconst char *str;\n\n\tif (!filename || !strcmp(filename, \"-\")) {\n\t\tstr = t->func(stdin);\n\t} else {\n\t\tstruct stat path_stat;\n\t\tstat(filename, &path_stat);\n\t\tif (S_ISDIR(path_stat.st_mode)) {\n\t\t\tfprintf(stderr, \"Failed to open '%s': Is a directory\\n\", filename);\n\t\t\treturn 1;\n\t\t}\n\n\t\tFILE *f = fopen(filename, \"r\");\n\n\t\tif (!f) {\n\t\t\tfprintf(stderr, \"Failed to open '%s'\\n\", filename);\n\t\t\treturn 1;\n\t\t}\n\t\tstr = t->func(f);\n\t\tfclose(f);\n\t}\n\n\tif (!str) {\n\t\tfprintf(stderr, \"Failed to generate hash\\n\");\n\t\treturn 1;\n\t}\n\n\tif (add_filename)\n\t\tprintf(\"%s %s%s\", str, filename ? filename : \"-\",\n\t\t\tno_newline ? \"\" : \"\\n\");\n\telse\n\t\tprintf(\"%s%s\", str, no_newline ? \"\" : \"\\n\");\n\treturn 0;\n}\n\n\nint main(int argc, char **argv)\n{\n\tstruct hash_type *t;\n\tconst char *progname = argv[0];\n\tint i, ch;\n\tbool add_filename = false, no_newline = false;\n\n\twhile ((ch = getopt(argc, argv, \"nN\")) != -1) {\n\t\tswitch (ch) {\n\t\tcase 'n':\n\t\t\tadd_filename = true;\n\t\t\tbreak;\n\t\tcase 'N':\n\t\t\tno_newline = true;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\treturn usage(progname);\n\t\t}\n\t}\n\n\targc -= optind;\n\targv += optind;\n\n\tif (argc < 1)\n\t\treturn usage(progname);\n\n\tt = get_hash_type(argv[0]);\n\tif (!t)\n\t\treturn usage(progname);\n\n\tif (argc < 2)\n\t\treturn hash_file(t, NULL, add_filename, no_newline);\n\n\tfor (i = 0; i < argc - 1; i++) {\n\t\tint ret = hash_file(t, argv[1 + i], add_filename, no_newline);\n\t\tif (ret)\n\t\t\treturn ret;\n\t}\n\n\treturn 0;\n}\n"
  },
  {
    "path": "scripts/mkits-qsdk-ipq-image.sh",
    "content": "#!/usr/bin/env bash\n#\n# Licensed under the terms of the GNU GPL License version 2 or later.\n# Author: Piotr Dymacz <pepe2k@gmail.com>, based on mkits.sh.\n#\n# Qualcomm SDK (QSDK) sysupgrade compatible images for IPQ40xx, IPQ806x\n# and IPQ807x use FIT format together with 'dumpimage' tool from U-Boot\n# for verifying and extracting them. Based on 'images' sections names,\n# corresponding mtd partitions are flashed.\n# This is a simple script for generating FIT images tree source files,\n# compatible with the QSDK sysupgrade format. Resulting images can be\n# used for initial (factory -> OpenWrt) installation and would work\n# both in CLI and GUI. The script is also universal in a way it allows\n# to include as many sections as needed.\n#\n\nusage() {\n\techo \"Usage: `basename $0` output img0_name img0_file [[img1_name img1_file] ...]\"\n\texit 1\n}\n\n# We need at least 3 arguments\n[ \"$#\" -lt 3 ] && usage\n\n# Target output file\nOUTPUT=\"$1\"; shift\n\n# Create a default, fully populated DTS file\necho \"\\\n/dts-v1/;\n\n/ {\n\tdescription = \\\"OpenWrt factory image\\\";\n\t#address-cells = <1>;\n\n\timages {\" > ${OUTPUT}\n\nwhile [ -n \"$1\" -a -n \"$2\" ]; do\n\t[ -f \"$2\" ] || usage\n\n\tname=\"$1\"; shift\n\tfile=\"$1\"; shift\n\n\techo \\\n\"\t\t${name} {\n\t\t\tdescription = \\\"${name}\\\";\n\t\t\tdata = /incbin/(\\\"${file}\\\");\n\t\t\ttype = \\\"Firmware\\\";\n\t\t\tarch = \\\"ARM\\\";\n\t\t\tcompression = \\\"none\\\";\n\t\t\thash@1 {\n\t\t\t\talgo = \\\"crc32\\\";\n\t\t\t};\n\t\t};\" >> ${OUTPUT}\ndone\n\necho \\\n\"\t};\n};\" >> ${OUTPUT}\n"
  },
  {
    "path": "scripts/mkits.sh",
    "content": "#!/bin/sh\n#\n# Licensed under the terms of the GNU GPL License version 2 or later.\n#\n# Author: Peter Tyser <ptyser@xes-inc.com>\n#\n# U-Boot firmware supports the booting of images in the Flattened Image\n# Tree (FIT) format.  The FIT format uses a device tree structure to\n# describe a kernel image, device tree blob, ramdisk, etc.  This script\n# creates an Image Tree Source (.its file) which can be passed to the\n# 'mkimage' utility to generate an Image Tree Blob (.itb file).  The .itb\n# file can then be booted by U-Boot (or other bootloaders which support\n# FIT images).  See doc/uImage.FIT/howto.txt in U-Boot source code for\n# additional information on FIT images.\n#\n\nusage() {\n\tprintf \"Usage: %s -A arch -C comp -a addr -e entry\" \"$(basename \"$0\")\"\n\tprintf \" -v version -k kernel [-D name -n address -d dtb] -o its_file\"\n\n\tprintf \"\\n\\t-A ==> set architecture to 'arch'\"\n\tprintf \"\\n\\t-C ==> set compression type 'comp'\"\n\tprintf \"\\n\\t-c ==> set config name 'config'\"\n\tprintf \"\\n\\t-a ==> set load address to 'addr' (hex)\"\n\tprintf \"\\n\\t-e ==> set entry point to 'entry' (hex)\"\n\tprintf \"\\n\\t-f ==> set device tree compatible string\"\n\tprintf \"\\n\\t-i ==> include initrd Blob 'initrd'\"\n\tprintf \"\\n\\t-v ==> set kernel version to 'version'\"\n\tprintf \"\\n\\t-k ==> include kernel image 'kernel'\"\n\tprintf \"\\n\\t-D ==> human friendly Device Tree Blob 'name'\"\n\tprintf \"\\n\\t-n ==> fdt unit-address 'address'\"\n\tprintf \"\\n\\t-d ==> include Device Tree Blob 'dtb'\"\n\tprintf \"\\n\\t-r ==> include RootFS blob 'rootfs'\"\n\tprintf \"\\n\\t-H ==> specify hash algo instead of SHA1\"\n\tprintf \"\\n\\t-l ==> legacy mode character (@ etc otherwise -)\"\n\tprintf \"\\n\\t-o ==> create output file 'its_file'\"\n\tprintf \"\\n\\t-O ==> create config with dt overlay 'name:dtb'\"\n\tprintf \"\\n\\t\\t(can be specified more than once)\\n\"\n\texit 1\n}\n\nREFERENCE_CHAR='-'\nFDTNUM=1\nROOTFSNUM=1\nINITRDNUM=1\nHASH=sha1\nLOADABLES=\nDTOVERLAY=\nDTADDR=\n\nwhile getopts \":A:a:c:C:D:d:e:f:i:k:l:n:o:O:v:r:H:\" OPTION\ndo\n\tcase $OPTION in\n\t\tA ) ARCH=$OPTARG;;\n\t\ta ) LOAD_ADDR=$OPTARG;;\n\t\tc ) CONFIG=$OPTARG;;\n\t\tC ) COMPRESS=$OPTARG;;\n\t\tD ) DEVICE=$OPTARG;;\n\t\td ) DTB=$OPTARG;;\n\t\te ) ENTRY_ADDR=$OPTARG;;\n\t\tf ) COMPATIBLE=$OPTARG;;\n\t\ti ) INITRD=$OPTARG;;\n\t\tk ) KERNEL=$OPTARG;;\n\t\tl ) REFERENCE_CHAR=$OPTARG;;\n\t\tn ) FDTNUM=$OPTARG;;\n\t\to ) OUTPUT=$OPTARG;;\n\t\tO ) DTOVERLAY=\"$DTOVERLAY ${OPTARG}\";;\n\t\tr ) ROOTFS=$OPTARG;;\n\t\tH ) HASH=$OPTARG;;\n\t\tv ) VERSION=$OPTARG;;\n\t\t* ) echo \"Invalid option passed to '$0' (options:$*)\"\n\t\tusage;;\n\tesac\ndone\n\n# Make sure user entered all required parameters\nif [ -z \"${ARCH}\" ] || [ -z \"${COMPRESS}\" ] || [ -z \"${LOAD_ADDR}\" ] || \\\n\t[ -z \"${ENTRY_ADDR}\" ] || [ -z \"${VERSION}\" ] || [ -z \"${KERNEL}\" ] || \\\n\t[ -z \"${OUTPUT}\" ] || [ -z \"${CONFIG}\" ]; then\n\tusage\nfi\n\nARCH_UPPER=$(echo \"$ARCH\" | tr '[:lower:]' '[:upper:]')\n\nif [ -n \"${COMPATIBLE}\" ]; then\n\tCOMPATIBLE_PROP=\"compatible = \\\"${COMPATIBLE}\\\";\"\nfi\n\n[ \"$DTOVERLAY\" ] && {\n\tdtbsize=$(wc -c \"$DTB\" | cut -d' ' -f1)\n\tDTADDR=$(printf \"0x%08x\" $(($LOAD_ADDR - $dtbsize)) )\n}\n\n# Conditionally create fdt information\nif [ -n \"${DTB}\" ]; then\n\tFDT_NODE=\"\n\t\tfdt${REFERENCE_CHAR}$FDTNUM {\n\t\t\tdescription = \\\"${ARCH_UPPER} OpenWrt ${DEVICE} device tree blob\\\";\n\t\t\t${COMPATIBLE_PROP}\n\t\t\tdata = /incbin/(\\\"${DTB}\\\");\n\t\t\ttype = \\\"flat_dt\\\";\n\t\t\t${DTADDR:+load = <${DTADDR}>;}\n\t\t\tarch = \\\"${ARCH}\\\";\n\t\t\tcompression = \\\"none\\\";\n\t\t\thash@1 {\n\t\t\t\talgo = \\\"crc32\\\";\n\t\t\t};\n\t\t\thash@2 {\n\t\t\t\talgo = \\\"${HASH}\\\";\n\t\t\t};\n\t\t};\n\"\n\tFDT_PROP=\"fdt = \\\"fdt${REFERENCE_CHAR}$FDTNUM\\\";\"\nfi\n\nif [ -n \"${INITRD}\" ]; then\n\tINITRD_NODE=\"\n\t\tinitrd${REFERENCE_CHAR}$INITRDNUM {\n\t\t\tdescription = \\\"${ARCH_UPPER} OpenWrt ${DEVICE} initrd\\\";\n\t\t\t${COMPATIBLE_PROP}\n\t\t\tdata = /incbin/(\\\"${INITRD}\\\");\n\t\t\ttype = \\\"ramdisk\\\";\n\t\t\tarch = \\\"${ARCH}\\\";\n\t\t\tos = \\\"linux\\\";\n\t\t\thash@1 {\n\t\t\t\talgo = \\\"crc32\\\";\n\t\t\t};\n\t\t\thash@2 {\n\t\t\t\talgo = \\\"${HASH}\\\";\n\t\t\t};\n\t\t};\n\"\n\tINITRD_PROP=\"ramdisk=\\\"initrd${REFERENCE_CHAR}${INITRDNUM}\\\";\"\nfi\n\n\nif [ -n \"${ROOTFS}\" ]; then\n\tdd if=\"${ROOTFS}\" of=\"${ROOTFS}.pagesync\" bs=4096 conv=sync\n\tROOTFS_NODE=\"\n\t\trootfs${REFERENCE_CHAR}$ROOTFSNUM {\n\t\t\tdescription = \\\"${ARCH_UPPER} OpenWrt ${DEVICE} rootfs\\\";\n\t\t\t${COMPATIBLE_PROP}\n\t\t\tdata = /incbin/(\\\"${ROOTFS}.pagesync\\\");\n\t\t\ttype = \\\"filesystem\\\";\n\t\t\tarch = \\\"${ARCH}\\\";\n\t\t\tcompression = \\\"none\\\";\n\t\t\thash@1 {\n\t\t\t\talgo = \\\"crc32\\\";\n\t\t\t};\n\t\t\thash@2 {\n\t\t\t\talgo = \\\"${HASH}\\\";\n\t\t\t};\n\t\t};\n\"\n\tLOADABLES=\"${LOADABLES:+$LOADABLES, }\\\"rootfs${REFERENCE_CHAR}${ROOTFSNUM}\\\"\"\nfi\n\n# add DT overlay blobs\nFDTOVERLAY_NODE=\"\"\nOVCONFIGS=\"\"\n[ \"$DTOVERLAY\" ] && for overlay in $DTOVERLAY ; do\n\toverlay_blob=${overlay##*:}\n\tovname=${overlay%%:*}\n\tovnode=\"fdt-$ovname\"\n\tovsize=$(wc -c \"$overlay_blob\" | cut -d' ' -f1)\n\techo \"$ovname ($overlay_blob) : $ovsize\" >&2\n\tDTADDR=$(printf \"0x%08x\" $(($DTADDR - $ovsize)))\n\tFDTOVERLAY_NODE=\"$FDTOVERLAY_NODE\n\n\t\t$ovnode {\n\t\t\tdescription = \\\"${ARCH_UPPER} OpenWrt ${DEVICE} device tree overlay $ovname\\\";\n\t\t\t${COMPATIBLE_PROP}\n\t\t\tdata = /incbin/(\\\"${overlay_blob}\\\");\n\t\t\ttype = \\\"flat_dt\\\";\n\t\t\tarch = \\\"${ARCH}\\\";\n\t\t\tload = <${DTADDR}>;\n\t\t\tcompression = \\\"none\\\";\n\t\t\thash@1 {\n\t\t\t\talgo = \\\"crc32\\\";\n\t\t\t};\n\t\t\thash@2 {\n\t\t\t\talgo = \\\"${HASH}\\\";\n\t\t\t};\n\t\t};\n\"\n\tOVCONFIGS=\"$OVCONFIGS\n\n\t\tconfig-$ovname {\n\t\t\tdescription = \\\"OpenWrt ${DEVICE} with $ovname\\\";\n\t\t\tkernel = \\\"kernel${REFERENCE_CHAR}1\\\";\n\t\t\tfdt = \\\"fdt${REFERENCE_CHAR}$FDTNUM\\\", \\\"$ovnode\\\";\n\t\t\t${LOADABLES:+loadables = ${LOADABLES};}\n\t\t\t${COMPATIBLE_PROP}\n\t\t\t${INITRD_PROP}\n\t\t};\n\t\"\ndone\n\n# Create a default, fully populated DTS file\nDATA=\"/dts-v1/;\n\n/ {\n\tdescription = \\\"${ARCH_UPPER} OpenWrt FIT (Flattened Image Tree)\\\";\n\t#address-cells = <1>;\n\n\timages {\n\t\tkernel${REFERENCE_CHAR}1 {\n\t\t\tdescription = \\\"${ARCH_UPPER} OpenWrt Linux-${VERSION}\\\";\n\t\t\tdata = /incbin/(\\\"${KERNEL}\\\");\n\t\t\ttype = \\\"kernel\\\";\n\t\t\tarch = \\\"${ARCH}\\\";\n\t\t\tos = \\\"linux\\\";\n\t\t\tcompression = \\\"${COMPRESS}\\\";\n\t\t\tload = <${LOAD_ADDR}>;\n\t\t\tentry = <${ENTRY_ADDR}>;\n\t\t\thash@1 {\n\t\t\t\talgo = \\\"crc32\\\";\n\t\t\t};\n\t\t\thash@2 {\n\t\t\t\talgo = \\\"$HASH\\\";\n\t\t\t};\n\t\t};\n${INITRD_NODE}\n${FDT_NODE}\n${FDTOVERLAY_NODE}\n${ROOTFS_NODE}\n\t};\n\n\tconfigurations {\n\t\tdefault = \\\"${CONFIG}\\\";\n\t\t${CONFIG} {\n\t\t\tdescription = \\\"OpenWrt ${DEVICE}\\\";\n\t\t\tkernel = \\\"kernel${REFERENCE_CHAR}1\\\";\n\t\t\t${FDT_PROP}\n\t\t\t${LOADABLES:+loadables = ${LOADABLES};}\n\t\t\t${COMPATIBLE_PROP}\n\t\t\t${INITRD_PROP}\n\t\t};\n\t\t${OVCONFIGS}\n\t};\n};\"\n\n# Write .its file to disk\necho \"$DATA\" > \"${OUTPUT}\"\n"
  },
  {
    "path": "scripts/om-fwupgradecfg-gen.sh",
    "content": "#!/bin/sh\n#\n# Copyright (C) 2011 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\nusage() {\n\techo \"Usage: $0 <OM2P|OM5P|OM5PAC|MR600|MR900|MR1750|A60|A42|A62|PA300|PA1200|PA2200> <out file path> <kernel path> <rootfs path>\"\n\trm -f $CFG_OUT\n\texit 1\n}\n\n[ \"$#\" -lt 4 ] && usage\n\nCE_TYPE=$1\nCFG_OUT=$2\nKERNEL_PATH=$3\nROOTFS_PATH=$4\n\ncase $CE_TYPE in\n\tPA300|\\\n\tOM2P)\n\t\tMAX_PART_SIZE=7168\n\t\tKERNEL_FLASH_ADDR=0x1c0000\n\t\tSIZE_FACTOR=1\n\t\tSIZE_FORMAT=\"%d\"\n\t\t;;\n\tOM5P|OM5PAC|MR600|MR900|MR1750|A60)\n\t\tMAX_PART_SIZE=7808\n\t\tKERNEL_FLASH_ADDR=0xb0000\n\t\tSIZE_FACTOR=1\n\t\tSIZE_FORMAT=\"%d\"\n\t\t;;\n\tA42|PA1200)\n\t\tMAX_PART_SIZE=15616\n\t\tKERNEL_FLASH_ADDR=0x180000\n\t\tSIZE_FACTOR=1024\n\t\tSIZE_FORMAT=\"0x%08x\"\n\t\t;;\n\tA62|PA2200)\n\t\tMAX_PART_SIZE=15552\n\t\tKERNEL_FLASH_ADDR=0x1a0000\n\t\tSIZE_FACTOR=1024\n\t\tSIZE_FORMAT=\"0x%08x\"\n\t\t;;\n\t*)\n\t\techo \"Error - unsupported ce type: $CE_TYPE\"\n\t\texit 1\n\t\t;;\nesac\n\nCHECK_BS=65536\n\nKERNEL_SIZE=$(stat -c%s \"$KERNEL_PATH\")\nKERNEL_MD5=$($MKHASH md5 $KERNEL_PATH)\nKERNEL_SHA256=$($MKHASH sha256 $KERNEL_PATH)\nKERNEL_PART_SIZE_KB=$((KERNEL_SIZE / 1024))\nKERNEL_PART_SIZE=$(printf $SIZE_FORMAT $(($KERNEL_PART_SIZE_KB * $SIZE_FACTOR)))\n\nROOTFS_FLASH_ADDR=$(addr=$(($KERNEL_FLASH_ADDR + ($KERNEL_PART_SIZE_KB * 1024))); printf \"0x%x\" $addr)\nROOTFS_SIZE=$(stat -c%s \"$ROOTFS_PATH\")\nROOTFS_SQUASHFS_SIZE=$((ROOTFS_SIZE-4))\nROOTFS_CHECK_BLOCKS=$((ROOTFS_SQUASHFS_SIZE / CHECK_BS))\nROOTFS_MD5=$(dd if=$ROOTFS_PATH bs=$CHECK_BS count=$ROOTFS_CHECK_BLOCKS 2>&- | $MKHASH md5)\nROOTFS_MD5_FULL=$($MKHASH md5 $ROOTFS_PATH)\nROOTFS_SHA256_FULL=$($MKHASH sha256 $ROOTFS_PATH)\nROOTFS_CHECK_SIZE=$(printf '0x%x' $ROOTFS_SQUASHFS_SIZE)\nROOTFS_PART_SIZE_KB=$(($MAX_PART_SIZE - $KERNEL_PART_SIZE_KB))\nROOTFS_PART_SIZE=$(printf $SIZE_FORMAT $(($ROOTFS_PART_SIZE_KB * $SIZE_FACTOR)))\n\ncat << EOF > $CFG_OUT\n[vmlinux]\nfilename=kernel\nmd5sum=$KERNEL_MD5\nfilemd5sum=$KERNEL_MD5\nfilesha256sum=$KERNEL_SHA256\nflashaddr=$KERNEL_FLASH_ADDR\nchecksize=0x0\ncmd_success=setenv bootseq 1,2; setenv kernel_size_1 $KERNEL_PART_SIZE; saveenv\ncmd_fail=reset\n\n[rootfs]\nfilename=rootfs\nmd5sum=$ROOTFS_MD5\nfilemd5sum=$ROOTFS_MD5_FULL\nfilesha256sum=$ROOTFS_SHA256_FULL\nflashaddr=$ROOTFS_FLASH_ADDR\nchecksize=$ROOTFS_CHECK_SIZE\ncmd_success=setenv bootseq 1,2; setenv kernel_size_1 $KERNEL_PART_SIZE; setenv rootfs_size_1 $ROOTFS_PART_SIZE; saveenv\ncmd_fail=reset\nEOF\n"
  },
  {
    "path": "scripts/package-metadata.pl",
    "content": "#!/usr/bin/env perl\nuse FindBin;\nuse lib \"$FindBin::Bin\";\nuse strict;\nuse metadata;\nuse Getopt::Long;\n\nmy %board;\n\nsub version_to_num($) {\n\tmy $str = shift;\n\tmy $num = 0;\n\n\tif (defined($str) && $str =~ /^\\d+(?:\\.\\d+)+$/)\n\t{\n\t\tmy @n = (split(/\\./, $str), 0, 0, 0, 0);\n\t\t$num = ($n[0] << 24) | ($n[1] << 16) | ($n[2] << 8) | $n[3];\n\t}\n\n\treturn $num;\n}\n\nsub version_filter_list(@) {\n\tmy $cmpver = version_to_num(shift @_);\n\tmy @items;\n\n\tforeach my $item (@_)\n\t{\n\t\tif ($item =~ s/@(lt|le|gt|ge|eq|ne)(\\d+(?:\\.\\d+)+)\\b//)\n\t\t{\n\t\t\tmy $op = $1;\n\t\t\tmy $symver = version_to_num($2);\n\n\t\t\tif ($symver > 0 && $cmpver > 0)\n\t\t\t{\n\t\t\t\tnext unless (($op eq 'lt' && $cmpver <  $symver) ||\n\t\t\t\t             ($op eq 'le' && $cmpver <= $symver) ||\n\t\t\t\t             ($op eq 'gt' && $cmpver >  $symver) ||\n\t\t\t\t             ($op eq 'ge' && $cmpver >= $symver) ||\n\t\t\t\t             ($op eq 'eq' && $cmpver == $symver) ||\n\t\t\t\t             ($op eq 'ne' && $cmpver != $symver));\n\t\t\t}\n\t\t}\n\n\t\tpush @items, $item;\n\t}\n\n\treturn @items;\n}\n\nsub gen_kconfig_overrides() {\n\tmy %config;\n\tmy %kconfig;\n\tmy $package;\n\tmy $pkginfo = shift @ARGV;\n\tmy $cfgfile = shift @ARGV;\n\tmy $patchver = shift @ARGV;\n\n\t# parameter 2: build system config\n\topen FILE, \"<$cfgfile\" or return;\n\twhile (<FILE>) {\n\t\t/^(CONFIG_.+?)=(.+)$/ and $config{$1} = 1;\n\t}\n\tclose FILE;\n\n\t# parameter 1: package metadata\n\topen FILE, \"<$pkginfo\" or return;\n\twhile (<FILE>) {\n\t\t/^Package:\\s*(.+?)\\s*$/ and $package = $1;\n\t\t/^Kernel-Config:\\s*(.+?)\\s*$/ and do {\n\t\t\tmy @config = split /\\s+/, $1;\n\t\t\tforeach my $config (version_filter_list($patchver, @config)) {\n\t\t\t\tmy $val = 'm';\n\t\t\t\tmy $override;\n\t\t\t\tif ($config =~ /^(.+?)=(.+)$/) {\n\t\t\t\t\t$config = $1;\n\t\t\t\t\t$override = 1;\n\t\t\t\t\t$val = $2;\n\t\t\t\t}\n\t\t\t\tif ($config{\"CONFIG_PACKAGE_$package\"} and ($config ne 'n')) {\n\t\t\t\t\tnext if $kconfig{$config} eq 'y';\n\t\t\t\t\t$kconfig{$config} = $val;\n\t\t\t\t} elsif (!$override) {\n\t\t\t\t\t$kconfig{$config} or $kconfig{$config} = 'n';\n\t\t\t\t}\n\t\t\t}\n\t\t};\n\t};\n\tclose FILE;\n\n\tforeach my $kconfig (sort keys %kconfig) {\n\t\tif ($kconfig{$kconfig} eq 'n') {\n\t\t\tprint \"# $kconfig is not set\\n\";\n\t\t} else {\n\t\t\tprint \"$kconfig=$kconfig{$kconfig}\\n\";\n\t\t}\n\t}\n}\n\nmy %dep_check;\nsub __find_package_dep($$) {\n\tmy $pkg = shift;\n\tmy $name = shift;\n\tmy $deps = $pkg->{depends};\n\n\treturn 0 unless defined $deps;\n\tforeach my $vpkg (@{$deps}) {\n\t\tforeach my $dep (@{$vpackage{$vpkg}}) {\n\t\t\tnext if $dep_check{$dep->{name}};\n\t\t\t$dep_check{$dep->{name}} = 1;\n\t\t\treturn 1 if $dep->{name} eq $name;\n\t\t\treturn 1 if (__find_package_dep($dep, $name) == 1);\n\t\t}\n\t}\n\treturn 0;\n}\n\n# wrapper to avoid infinite recursion\nsub find_package_dep($$) {\n\tmy $pkg = shift;\n\tmy $name = shift;\n\n\t%dep_check = ();\n\treturn __find_package_dep($pkg, $name);\n}\n\nsub package_depends($$) {\n\tmy $a = shift;\n\tmy $b = shift;\n\tmy $ret;\n\n\treturn 0 if ($a->{submenu} ne $b->{submenu});\n\tif (find_package_dep($a, $b->{name}) == 1) {\n\t\t$ret = 1;\n\t} elsif (find_package_dep($b, $a->{name}) == 1) {\n\t\t$ret = -1;\n\t} else {\n\t\treturn 0;\n\t}\n\treturn $ret;\n}\n\nsub mconf_depends {\n\tmy $pkgname = shift;\n\tmy $depends = shift;\n\tmy $only_dep = shift;\n\tmy $res;\n\tmy $dep = shift;\n\tmy $seen = shift;\n\tmy $parent_condition = shift;\n\t$dep or $dep = {};\n\t$seen or $seen = {};\n\tmy @t_depends;\n\n\t$depends or return;\n\tmy @depends = @$depends;\n\tforeach my $depend (@depends) {\n\t\tmy $m = \"depends on\";\n\t\tmy $flags = \"\";\n\t\t$depend =~ s/^([@\\+]+)// and $flags = $1;\n\t\tmy $condition = $parent_condition;\n\n\t\tnext if $condition eq $depend;\n\t\tnext if $seen->{\"$parent_condition:$depend\"};\n\t\tnext if $seen->{\":$depend\"};\n\t\t$seen->{\"$parent_condition:$depend\"} = 1;\n\t\tif ($depend =~ /^(.+):(.+)$/) {\n\t\t\tif ($1 ne \"PACKAGE_$pkgname\") {\n\t\t\t\tif ($condition) {\n\t\t\t\t\t$condition = \"$condition && $1\";\n\t\t\t\t} else {\n\t\t\t\t\t$condition = $1;\n\t\t\t\t}\n\t\t\t}\n\t\t\t$depend = $2;\n\t\t}\n\t\tif ($flags =~ /\\+/) {\n\t\t\tmy $vdep = $vpackage{$depend};\n\t\t\tif ($vdep) {\n\t\t\t\tmy @vdeps;\n\n\t\t\t\tforeach my $v (@$vdep) {\n\t\t\t\t\tnext if $v->{buildonly};\n\t\t\t\t\tif ($v->{variant_default}) {\n\t\t\t\t\t\tunshift @vdeps, $v->{name};\n\t\t\t\t\t} else {\n\t\t\t\t\t\tpush @vdeps, $v->{name};\n\t\t\t\t\t}\n\t\t\t\t}\n\n\t\t\t\t$depend = shift @vdeps;\n\n\t\t\t\tif (@vdeps > 1) {\n\t\t\t\t\t$condition = ($condition ? \"$condition && \" : '') . join(\"&&\", map { \"PACKAGE_$_<PACKAGE_$pkgname\" } @vdeps);\n\t\t\t\t} elsif (@vdeps > 0) {\n\t\t\t\t\t$condition = ($condition ? \"$condition && \" : '') . \"PACKAGE_${vdeps[0]}<PACKAGE_$pkgname\";\n\t\t\t\t}\n\t\t\t}\n\n\t\t\t# Menuconfig will not treat 'select FOO' as a real dependency\n\t\t\t# thus if FOO depends on other config options, these dependencies\n\t\t\t# will not be checked. To fix this, we simply emit all of FOO's\n\t\t\t# depends here as well.\n\t\t\t$package{$depend} and push @t_depends, [ $package{$depend}->{depends}, $condition ];\n\n\t\t\t$m = \"select\";\n\t\t\tnext if $only_dep;\n\n\t\t\t$flags =~ /@/ or $depend = \"PACKAGE_$depend\";\n\t\t} else {\n\t\t\tmy $vdep = $vpackage{$depend};\n\t\t\tif ($vdep && @$vdep > 0) {\n\t\t\t\t$depend = join(\"||\", map { \"PACKAGE_\".$_->{name} } @$vdep);\n\t\t\t} else {\n\t\t\t\t$flags =~ /@/ or $depend = \"PACKAGE_$depend\";\n\t\t\t}\n\t\t}\n\n\t\tif ($condition) {\n\t\t\tif ($m =~ /select/) {\n\t\t\t\tnext if $depend eq $condition;\n\t\t\t\t$depend = \"$depend if $condition\";\n\t\t\t} else {\n\t\t\t\tnext if $dep->{\"$depend if $condition\"};\n\t\t\t\t$depend = \"!($condition) || $depend\" unless $dep->{$condition} eq 'select';\n\t\t\t}\n\t\t}\n\t\t$dep->{$depend} =~ /select/ or $dep->{$depend} = $m;\n\t}\n\n\tforeach my $tdep (@t_depends) {\n\t\tmconf_depends($pkgname, $tdep->[0], 1, $dep, $seen, $tdep->[1]);\n\t}\n\n\tforeach my $depend (keys %$dep) {\n\t\tmy $m = $dep->{$depend};\n\t\t$res .= \"\\t\\t$m $depend\\n\";\n\t}\n\treturn $res;\n}\n\nsub mconf_conflicts {\n\tmy $pkgname = shift;\n\tmy $depends = shift;\n\tmy $res = \"\";\n\n\tforeach my $depend (@$depends) {\n\t\tnext unless $package{$depend};\n\t\t$res .= \"\\t\\tdepends on m || (PACKAGE_$depend != y)\\n\";\n\t}\n\treturn $res;\n}\n\nsub print_package_config_category($) {\n\tmy $cat = shift;\n\tmy %menus;\n\tmy %menu_dep;\n\n\treturn unless $category{$cat};\n\n\tprint \"menu \\\"$cat\\\"\\n\\n\";\n\tmy %spkg = %{$category{$cat}};\n\n\tforeach my $spkg (sort {uc($a) cmp uc($b)} keys %spkg) {\n\t\tforeach my $pkg (@{$spkg{$spkg}}) {\n\t\t\tnext if $pkg->{buildonly};\n\t\t\tmy $menu = $pkg->{submenu};\n\t\t\tif ($menu) {\n\t\t\t\t$menu_dep{$menu} or $menu_dep{$menu} = $pkg->{submenudep};\n\t\t\t} else {\n\t\t\t\t$menu = 'undef';\n\t\t\t}\n\t\t\t$menus{$menu} or $menus{$menu} = [];\n\t\t\tpush @{$menus{$menu}}, $pkg;\n\t\t}\n\t}\n\tmy @menus = sort {\n\t\t($a eq 'undef' ?  1 : 0) or\n\t\t($b eq 'undef' ? -1 : 0) or\n\t\t($a cmp $b)\n\t} keys %menus;\n\n\tforeach my $menu (@menus) {\n\t\tmy @pkgs = sort {\n\t\t\tpackage_depends($a, $b) or\n\t\t\t($a->{name} cmp $b->{name})\n\t\t} @{$menus{$menu}};\n\t\tif ($menu ne 'undef') {\n\t\t\t$menu_dep{$menu} and print \"if $menu_dep{$menu}\\n\";\n\t\t\tprint \"menu \\\"$menu\\\"\\n\";\n\t\t}\n\t\tforeach my $pkg (@pkgs) {\n\t\t\tnext if $pkg->{src}{ignore};\n\t\t\tmy $title = $pkg->{name};\n\t\t\tmy $c = (72 - length($pkg->{name}) - length($pkg->{title}));\n\t\t\tif ($c > 0) {\n\t\t\t\t$title .= (\".\" x $c). \" \". $pkg->{title};\n\t\t\t}\n\t\t\t$title = \"\\\"$title\\\"\";\n\t\t\tprint \"\\t\";\n\t\t\t$pkg->{menu} and print \"menu\";\n\t\t\tprint \"config PACKAGE_\".$pkg->{name}.\"\\n\";\n\t\t\t$pkg->{hidden} and $title = \"\";\n\t\t\tprint \"\\t\\t\".($pkg->{tristate} ? 'tristate' : 'bool').\" $title\\n\";\n\t\t\tprint \"\\t\\tdefault y if DEFAULT_\".$pkg->{name}.\"\\n\";\n\t\t\tunless ($pkg->{hidden}) {\n\t\t\t\tmy @def = (\"ALL\");\n\t\t\t\tif (!exists($pkg->{repository})) {\n\t\t\t\t\tpush @def, \"ALL_NONSHARED\";\n\t\t\t\t}\n\t\t\t\tif ($pkg->{name} =~ /^kmod-/) {\n\t\t\t\t\tpush @def, \"ALL_KMODS\";\n\t\t\t\t}\n\t\t\t\t$pkg->{default} ||= \"m if \" . join(\"||\", @def);\n\t\t\t}\n\t\t\tif ($pkg->{default}) {\n\t\t\t\tforeach my $default (split /\\s*,\\s*/, $pkg->{default}) {\n\t\t\t\t\tprint \"\\t\\tdefault $default\\n\";\n\t\t\t\t}\n\t\t\t}\n\t\t\tprint mconf_depends($pkg->{name}, $pkg->{depends}, 0);\n\t\t\tprint mconf_depends($pkg->{name}, $pkg->{mdepends}, 0);\n\t\t\tprint mconf_conflicts($pkg->{name}, $pkg->{conflicts});\n\t\t\tprint \"\\t\\thelp\\n\";\n\t\t\tprint $pkg->{description};\n\t\t\tprint \"\\n\";\n\n\t\t\t$pkg->{config} and print $pkg->{config}.\"\\n\";\n\t\t}\n\t\tif ($menu ne 'undef') {\n\t\t\tprint \"endmenu\\n\";\n\t\t\t$menu_dep{$menu} and print \"endif\\n\";\n\t\t}\n\t}\n\tprint \"endmenu\\n\\n\";\n\n\tundef $category{$cat};\n}\n\nsub print_package_overrides() {\n\tkeys %overrides > 0 or return;\n\tprint \"\\tconfig OVERRIDE_PKGS\\n\";\n\tprint \"\\t\\tstring\\n\";\n\tprint \"\\t\\tdefault \\\"\".join(\" \", sort keys %overrides).\"\\\"\\n\\n\";\n}\n\nsub gen_package_config() {\n\tparse_package_metadata($ARGV[0]) or exit 1;\n\tprint \"menuconfig IMAGEOPT\\n\\tbool \\\"Image configuration\\\"\\n\\tdefault n\\n\";\n\tprint \"source \\\"package/*/image-config.in\\\"\\n\";\n\tif (scalar glob \"package/feeds/*/*/image-config.in\") {\n\t    print \"source \\\"package/feeds/*/*/image-config.in\\\"\\n\";\n\t}\n\tprint_package_config_category 'Base system';\n\tforeach my $cat (sort {uc($a) cmp uc($b)} keys %category) {\n\t\tprint_package_config_category $cat;\n\t}\n\tprint_package_overrides();\n}\n\nsub and_condition($) {\n\tmy $condition = shift;\n\tmy @spl_and = split('\\&\\&', $condition);\n\tif (@spl_and == 1) {\n\t\treturn \"\\$(CONFIG_$spl_and[0])\";\n\t}\n\treturn \"\\$(and \" . join (',', map(\"\\$(CONFIG_$_)\", @spl_and)) . \")\";\n}\n\nsub gen_condition ($) {\n\tmy $condition = shift;\n\t# remove '!()', just as include/package-ipkg.mk does\n\t$condition =~ s/[()!]//g;\n\treturn join(\"\", map(and_condition($_), split('\\|\\|', $condition)));\n}\n\nsub get_conditional_dep($$) {\n\tmy $condition = shift;\n\tmy $depstr = shift;\n\tif ($condition) {\n\t\tif ($condition =~ /^!(.+)/) {\n\t\t\treturn \"\\$(if \" . gen_condition($1) . \",,$depstr)\";\n\t\t} else {\n\t\t\treturn \"\\$(if \" . gen_condition($condition) . \",$depstr)\";\n\t\t}\n\t} else {\n\t\treturn $depstr;\n\t}\n}\n\nsub gen_package_mk() {\n\tmy $line;\n\n\tparse_package_metadata($ARGV[0]) or exit 1;\n\tforeach my $srcname (sort {uc($a) cmp uc($b)} keys %srcpackage) {\n\t\tmy $src = $srcpackage{$srcname};\n\t\tmy $variant_default;\n\t\tmy %deplines = ('' => {});\n\n\t\tforeach my $pkg (@{$src->{packages}}) {\n\t\t\tforeach my $dep (@{$pkg->{depends}}) {\n\t\t\t\tnext if ($dep =~ /@/);\n\n\t\t\t\tmy $condition;\n\n\t\t\t\t$dep =~ s/\\+//g;\n\t\t\t\tif ($dep =~ /^(.+):(.+)/) {\n\t\t\t\t\t$condition = $1;\n\t\t\t\t\t$dep = $2;\n\t\t\t\t}\n\n\t\t\t\tmy $vpkg_dep = $vpackage{$dep};\n\t\t\t\tunless (defined $vpkg_dep) {\n\t\t\t\t\twarn sprintf \"WARNING: Makefile '%s' has a dependency on '%s', which does not exist\\n\",\n\t\t\t\t\t\t$src->{makefile}, $dep;\n\t\t\t\t\tnext;\n\t\t\t\t}\n\n\t\t\t\t# Filter out self-depends\n\t\t\t\tmy @vdeps = grep { $srcname ne $_->{src}{name} } @{$vpkg_dep};\n\n\t\t\t\tforeach my $vdep (@vdeps) {\n\t\t\t\t\tmy $depstr = sprintf '$(curdir)/%s/compile', $vdep->{src}{path};\n\t\t\t\t\tif (@vdeps > 1) {\n\t\t\t\t\t\t$depstr = sprintf '$(if $(CONFIG_PACKAGE_%s),%s)', $vdep->{name}, $depstr;\n\t\t\t\t\t}\n\t\t\t\t\tmy $depline = get_conditional_dep($condition, $depstr);\n\t\t\t\t\tif ($depline) {\n\t\t\t\t\t\t$deplines{''}{$depline}++;\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\n\t\t\tmy $config = '';\n\t\t\t$config = sprintf '$(CONFIG_PACKAGE_%s)', $pkg->{name} unless $pkg->{buildonly};\n\n\t\t\t$pkg->{prereq} and printf \"prereq-%s += %s\\n\", $config, $src->{path};\n\n\t\t\tnext if $pkg->{buildonly};\n\n\t\t\tprintf \"package-%s += %s\\n\", $config, $src->{path};\n\n\t\t\tif ($pkg->{variant}) {\n\t\t\t\tif (!defined($variant_default) or $pkg->{variant_default}) {\n\t\t\t\t\t$variant_default = $pkg->{variant};\n\t\t\t\t}\n\t\t\t\tprintf \"\\$(curdir)/%s/variants += \\$(if %s,%s)\\n\", $src->{path}, $config, $pkg->{variant};\n\t\t\t}\n\t\t}\n\n\t\tif (defined($variant_default)) {\n\t\t\tprintf \"\\$(curdir)/%s/default-variant := %s\\n\", $src->{path}, $variant_default;\n\t\t}\n\n\t\tunless (grep {!$_->{buildonly}} @{$src->{packages}}) {\n\t\t\tprintf \"package- += %s\\n\", $src->{path};\n\t\t}\n\n\t\tif (@{$src->{buildtypes}} > 0) {\n\t\t\tprintf \"buildtypes-%s = %s\\n\", $src->{path}, join(' ', @{$src->{buildtypes}});\n\t\t}\n\n\t\tforeach my $type ('', @{$src->{buildtypes}}) {\n\t\t\tmy $suffix = '';\n\n\t\t\t$suffix = \"/$type\" if $type;\n\n\t\t\tnext unless $src->{\"builddepends$suffix\"};\n\n\t\t\tdefined $deplines{$suffix} or $deplines{$suffix} = {};\n\n\t\t\tforeach my $dep (@{$src->{\"builddepends$suffix\"}}) {\n\t\t\t\tmy $depsuffix = \"\";\n\t\t\t\tmy $deptype = \"\";\n\t\t\t\tmy $condition;\n\n\t\t\t\tif ($dep =~ /^(.+):(.+)/) {\n\t\t\t\t\t$condition = $1;\n\t\t\t\t\t$dep = $2;\n\t\t\t\t}\n\t\t\t\tif ($dep =~ /^(.+)\\/(.+)/) {\n\t\t\t\t\t$dep = $1;\n\t\t\t\t\t$deptype = $2;\n\t\t\t\t\t$depsuffix = \"/$2\";\n\t\t\t\t}\n\n\t\t\t\tnext if $srcname.$suffix eq $dep.$depsuffix;\n\n\t\t\t\tmy $src_dep = $srcpackage{$dep};\n\t\t\t\tunless (defined($src_dep) && (!$deptype || grep { $_ eq $deptype } @{$src_dep->{buildtypes}})) {\n\t\t\t\t\twarn sprintf \"WARNING: Makefile '%s' has a build dependency on '%s', which does not exist\\n\",\n\t\t\t\t\t\t$src->{makefile}, $dep.$depsuffix;\n\t\t\t\t\tnext;\n\t\t\t\t}\n\n\t\t\t\tmy $depstr = sprintf '$(curdir)/%s/compile', $src_dep->{path}.$depsuffix;\n\t\t\t\tmy $depline = get_conditional_dep($condition, $depstr);\n\t\t\t\tif ($depline) {\n\t\t\t\t\t$deplines{$suffix}{$depline}++;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n\t\tforeach my $suffix (sort keys %deplines) {\n\t\t\tmy $depline = join(\" \", sort keys %{$deplines{$suffix}});\n\t\t\tif ($depline) {\n\t\t\t\t$line .= sprintf \"\\$(curdir)/%s/compile += %s\\n\", $src->{path}.$suffix, $depline;\n\t\t\t}\n\t\t}\n\t}\n\n\tif ($line ne \"\") {\n\t\tprint \"\\n$line\";\n\t}\n}\n\nsub gen_package_source() {\n\tparse_package_metadata($ARGV[0]) or exit 1;\n\tforeach my $name (sort {uc($a) cmp uc($b)} keys %package) {\n\t\tmy $pkg = $package{$name};\n\t\tif ($pkg->{name} && $pkg->{source}) {\n\t\t\tprint \"$pkg->{name}: \";\n\t\t\tprint \"$pkg->{source}\\n\";\n\t\t}\n\t}\n}\n\nsub gen_package_auxiliary() {\n\tparse_package_metadata($ARGV[0]) or exit 1;\n\tforeach my $name (sort {uc($a) cmp uc($b)} keys %package) {\n\t\tmy $pkg = $package{$name};\n\t\tif ($pkg->{name} && $pkg->{repository}) {\n\t\t\tprint \"Package/$name/subdir = $pkg->{repository}\\n\";\n\t\t}\n\t\tmy %depends;\n\t\tforeach my $dep (@{$pkg->{depends} || []}) {\n\t\t\tif ($dep =~ m!^\\+?(?:[^:]+:)?([^@]+)$!) {\n\t\t\t\t$depends{$1}++;\n\t\t\t}\n\t\t}\n\t\tmy @depends = sort keys %depends;\n\t\tif (@depends > 0) {\n\t\t\tforeach my $n (@{$pkg->{provides}}) {\n\t\t\t\tprint \"Package/$n/depends = @depends\\n\";\n\t\t\t}\n\t\t}\n\t}\n}\n\nsub gen_package_license($) {\n\tmy $level = shift;\n\tparse_package_metadata($ARGV[0]) or exit 1;\n\tforeach my $name (sort {uc($a) cmp uc($b)} keys %package) {\n\t\tmy $pkg = $package{$name};\n\t\tif ($pkg->{name}) {\n\t\t\tif ($pkg->{license}) {\n\t\t\t\tprint \"$pkg->{name}: \";\n\t\t\t\tprint \"$pkg->{license}\\n\";\n\t\t\t\tif ($pkg->{licensefiles} && $level == 0) {\n\t\t\t\t\tprint \"\\tFiles: $pkg->{licensefiles}\\n\";\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\tif ($level == 1) {\n\t\t\t\t\tprint \"$pkg->{name}: Missing license! \";\n\t\t\t\t\tprint \"Please fix $pkg->{src}{makefile}\\n\";\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n}\n\nsub gen_version_filtered_list() {\n\tforeach my $item (version_filter_list(@ARGV)) {\n\t\tprint \"$item\\n\";\n\t}\n}\n\nsub gen_usergroup_list() {\n\tparse_package_metadata($ARGV[0]) or exit 1;\n\tfor my $name (keys %usernames) {\n\t\tprint \"user $name $usernames{$name}{id} $usernames{$name}{makefile}\\n\";\n\t}\n\tfor my $name (keys %groupnames) {\n\t\tprint \"group $name $groupnames{$name}{id} $groupnames{$name}{makefile}\\n\";\n\t}\n}\n\nsub gen_package_manifest_json() {\n\tmy $json;\n\tparse_package_metadata($ARGV[0]) or exit 1;\n\tforeach my $name (sort {uc($a) cmp uc($b)} keys %package) {\n\t\tmy %depends;\n\t\tmy $pkg = $package{$name};\n\t\tforeach my $dep (@{$pkg->{depends} || []}) {\n\t\t\tif ($dep =~ m!^\\+?(?:[^:]+:)?([^@]+)$!) {\n\t\t\t\t$depends{$1}++;\n\t\t\t}\n\t\t}\n\t\tmy @depends = sort keys %depends;\n\t\tmy $pkg_deps = join ' ', map { qq/\"$_\",/ } @depends;\n\t\t$pkg_deps =~ s/\\,$//;\n\n\t\tmy $pkg_maintainer = join ' ', map { qq/\"$_\",/ } @{$pkg->{maintainer} || []};\n\t\t$pkg_maintainer =~ s/\\,$//;\n\n\t\t$json = <<\"END_JSON\";\n${json}{\n\"name\":\"$name\",\n\"version\":\"$pkg->{version}\",\n\"category\":\"$pkg->{category}\",\n\"license\":\"$pkg->{license}\",\n\"maintainer\": [$pkg_maintainer],\n\"depends\":[$pkg_deps]},\nEND_JSON\n\t}\n\n\t$json =~ s/[\\n\\r]//g;\n\t$json =~ s/\\,$//;\n\tprint \"[$json]\";\n}\n\nsub parse_command() {\n\tGetOptions(\"ignore=s\", \\@ignore);\n\tmy $cmd = shift @ARGV;\n\tfor ($cmd) {\n\t\t/^mk$/ and return gen_package_mk();\n\t\t/^config$/ and return gen_package_config();\n\t\t/^kconfig/ and return gen_kconfig_overrides();\n\t\t/^source$/ and return gen_package_source();\n\t\t/^pkgaux$/ and return gen_package_auxiliary();\n\t\t/^pkgmanifestjson$/ and return gen_package_manifest_json();\n\t\t/^license$/ and return gen_package_license(0);\n\t\t/^licensefull$/ and return gen_package_license(1);\n\t\t/^usergroup$/ and return gen_usergroup_list();\n\t\t/^version_filter$/ and return gen_version_filtered_list();\n\t}\n\tdie <<EOF\nAvailable Commands:\n\t$0 mk [file]\t\t\t\tPackage metadata in makefile format\n\t$0 config [file] \t\t\tPackage metadata in Kconfig format\n\t$0 kconfig [file] [config] [patchver]\tKernel config overrides\n\t$0 source [file] \t\t\tPackage source file information\n\t$0 pkgaux [file]\t\t\tPackage auxiliary variables in makefile format\n\t$0 pkgmanifestjson [file]\t\tPackage manifests in JSON format\n\t$0 license [file] \t\t\tPackage license information\n\t$0 licensefull [file] \t\t\tPackage license information (full list)\n\t$0 usergroup [file]\t\t\tPackage usergroup allocation list\n\t$0 version_filter [patchver] [list...]\tFilter list of version tagged strings\n\nOptions:\n\t--ignore <name>\t\t\t\tIgnore the source package <name>\nEOF\n}\n\nparse_command();\n"
  },
  {
    "path": "scripts/pad_image",
    "content": "#!/usr/bin/env bash\n\nfunction usage {\n  echo \"Usage: prepare_image image_type kernel_image rootfs_image header_size\"\n  echo \"Pad root and kernel image to the correct size and append the jffs2 start marker as needed\"\n  exit 1\n}\n\nfunction pad_file {\n\techo \"Padding $1 to size $2\"\n\tdd if=$1 of=$1.paddingtempfile bs=$2 count=1 conv=sync &> /dev/null\n\tmv $1.paddingtempfile $1\n}\n\n#filesize filestart padding\nfunction calc_pad {\n\t[  $((($1 + $2) & ($3 - 1))) == 0 ] && {\n\t\techo $1\n\t\treturn 0\n        }\n\techo $(((($1 + $2) | ($3 - 1)) + 1 - $2))\n}\n\nfunction prep_squash {\n\techo \"kernel_size: $kernel_size\"\n\techo \"header_size: $header_size\"\n\tkernel_pad_size=$(calc_pad $kernel_size $header_size 32)\n\tkernel_end=$(($header_size + $kernel_pad_size))\n\tpad_file $kernel_image $kernel_pad_size\n\n\t#4k\n\trootfs_pad_size=$(calc_pad $rootfs_size $kernel_end 4096)\n\tpad_file $rootfs_image $rootfs_pad_size\n\techo -ne '\\xde\\xad\\xc0\\xde' >> $rootfs_image\n\t\n\t#8k\n\trootfs_pad_size=$(calc_pad $rootfs_size $kernel_end 8192)\n\t[ $rootfs_pad_size == rootfs_old_padsize ] || {\n\t\tpad_file $rootfs_image $rootfs_pad_size\n\t\trootfs_old_padsize=$rootfs_pad_size\n\t\techo -ne '\\xde\\xad\\xc0\\xde' >> $rootfs_image\n\t}\n\n\t#64k\n\trootfs_pad_size=$(calc_pad $rootfs_size $kernel_end 65536)\n\t[ $rootfs_pad_size == rootfs_old_padsize ] || {\n\t\tpad_file $rootfs_image $rootfs_pad_size\n\t\trootfs_old_padsize=$rootfs_pad_size\n\t\techo -ne '\\xde\\xad\\xc0\\xde' >> $rootfs_image\n\t}\n\n\t#128k\n\trootfs_pad_size=$(calc_pad $rootfs_size $kernel_end 131072)\n\t[ $rootfs_pad_size == rootfs_old_padsize ] || {\n\t\tpad_file $rootfs_image $rootfs_pad_size\n\t\trootfs_old_padsize=$rootfs_pad_size\n\t\techo -ne '\\xde\\xad\\xc0\\xde' >> $rootfs_image\n\t}\n\t\n}\n\nfunction prep_jffs2 {\n\tkernel_pad_size=$(calc_pad $kernel_size $header_size $1)\n\tpad_file $kernel_image $kernel_pad_size\n}\n\nimage_type=$1\nkernel_image=$2\nrootfs_image=$3\nheader_size=$4\n\nif [ -z \"$image_type\" ] || [ -z \"$rootfs_image\" ] || [ -z \"$kernel_image\" ] || [ -z \"$header_size\" ]; then\n\tusage\nfi\n\nif [ ! -e \"$rootfs_image\" ] || [ -z \"$kernel_image\" ]; then\n\techo \"input file not found\"\n\texit 1\nfi\n\nkernel_size=$(stat -c \"%s\" \"$kernel_image\")\nrootfs_size=$(stat -c \"%s\" \"$rootfs_image\")\n\nif [ $kernel_size == 0 ] || [ $rootfs_size == 0 ]; then\n\techo \"kernel or rootfs empty\"\n\texit 1\nfi\n\ncase $image_type in\n\tsquashfs )\n\t\tprep_squash ;;\n\tjffs2-64k )\n\t\tprep_jffs2 65536 ;;\n\tjffs2-128k )\n\t\tprep_jffs2 131072 ;;\n\t* )\n\t\techo \"Unknown image type\"\n\t\texit 1 ;;\nesac\n\n"
  },
  {
    "path": "scripts/patch-kernel.sh",
    "content": "#! /bin/sh\n# A little script I whipped up to make it easy to\n# patch source trees and have sane error handling\n# -Erik\n#\n# (c) 2002 Erik Andersen <andersen@codepoet.org>\n\n# Set directories from arguments, or use defaults.\ntargetdir=${1-.}\npatchdir=${2-../kernel-patches}\npatchpattern=${3-*}\n\nif [ ! -d \"${targetdir}\" ] ; then\n    echo \"Aborting.  '${targetdir}' is not a directory.\"\n    exit 1\nfi\nif [ ! -d \"${patchdir}\" ] ; then\n    echo \"Aborting.  '${patchdir}' is not a directory.\"\n    exit 1\nfi\n    \nfor i in ${patchdir}/${patchpattern} ; do \n    case \"$i\" in\n\t*.gz)\n\ttype=\"gzip\"; uncomp=\"gunzip -dc\"; ;; \n\t*.bz)\n\ttype=\"bzip\"; uncomp=\"bunzip -dc\"; ;; \n\t*.bz2)\n\ttype=\"bzip2\"; uncomp=\"bunzip2 -dc\"; ;; \n\t*.zip)\n\ttype=\"zip\"; uncomp=\"unzip -d\"; ;; \n\t*.Z)\n\ttype=\"compress\"; uncomp=\"uncompress -c\"; ;; \n\t*)\n\ttype=\"plaintext\"; uncomp=\"cat\"; ;; \n    esac\n    [ -d \"${i}\" ] && echo \"Ignoring subdirectory ${i}\" && continue\t\n    echo \"\"\n    echo \"Applying ${i} using ${type}: \" \n    ${uncomp} ${i} | ${PATCH:-patch} -f -p1 -d ${targetdir}\n    if [ $? != 0 ] ; then\n        echo \"Patch failed!  Please fix $i!\"\n\texit 1\n    fi\ndone\n\n# Check for rejects...\nif [ \"`find $targetdir/ '(' -name '*.rej' -o -name '.*.rej' ')' -print`\" ] ; then\n    echo \"Aborting.  Reject files found.\"\n    exit 1\nfi\n\n# Remove backup files\nfind $targetdir/ '(' -name '*.orig' -o -name '.*.orig' ')' -exec rm -f {} \\;\n"
  },
  {
    "path": "scripts/patch-specs.sh",
    "content": "#!/usr/bin/env bash\n\nDIR=\"$1\"\n\nif [ -d \"$DIR\" ]; then\n\tDIR=\"$(cd \"$DIR\"; pwd)\"\nelse\n\techo \"Usage: $0 toolchain-dir\"\n\texit 1\nfi\n\necho -n \"Locating cpp ... \"\nfor bin in bin usr/bin usr/local/bin; do\n\tfor cmd in \"$DIR/$bin/\"*-cpp; do\n\t\tif [ -x \"$cmd\" ]; then\n\t\t\techo \"$cmd\"\n\t\t\tCPP=\"$cmd\"\n\t\t\tbreak\n\t\tfi\n\tdone\ndone\n\nif [ ! -x \"$CPP\" ]; then\n\techo \"Can't locate a cpp executable in '$DIR' !\"\n\texit 1\nfi\n\npatch_specs() {\n\tlocal found=0\n\n\tfor lib in $(STAGING_DIR=\"$DIR\" \"$CPP\" -x c -v /dev/null 2>&1 | sed -ne 's#:# #g; s#^LIBRARY_PATH=##p'); do\n\t\tif [ -d \"$lib\" ]; then\n\t\t\tgrep -qs \"STAGING_DIR\" \"$lib/specs\" && rm -f \"$lib/specs\"\n\t\t\tif [ $found -lt 1 ]; then\n\t\t\t\techo -n \"Patching specs ... \"\n\t\t\t\tSTAGING_DIR=\"$DIR\" \"$CPP\" -dumpspecs | awk '\n\t\t\t\t\tmode ~ \"link\" {\n\t\t\t\t\t\tsub(/(%@?\\{L.\\})/, \"& -L %:getenv(STAGING_DIR /usr/lib) -rpath-link %:getenv(STAGING_DIR /usr/lib)\")\n\t\t\t\t\t}\n\t\t\t\t\tmode ~ \"cpp\" {\n\t\t\t\t\t\t$0 = $0 \" -idirafter %:getenv(STAGING_DIR /usr/include)\"\n\t\t\t\t\t}\n\t\t\t\t\t{\n\t\t\t\t\t\tprint $0\n\t\t\t\t\t\tmode = \"\"\n\t\t\t\t\t}\n\t\t\t\t\t/^\\*cpp:/ {\n\t\t\t\t\t\tmode = \"cpp\"\n\t\t\t\t\t}\n\t\t\t\t\t/^\\*link.*:/ {\n\t\t\t\t\t\tmode = \"link\"\n\t\t\t\t\t}\n\t\t\t\t' > \"$lib/specs\"\n\t\t\t\techo \"ok\"\n\t\t\t\tfound=1\n\t\t\tfi\n\t\tfi\n\tdone\n\n\t[ $found -gt 0 ]\n\treturn $?\n}\n\n\nVERSION=\"$(STAGING_DIR=\"$DIR\" \"$CPP\" --version | sed -ne 's/^.* (.*) //; s/ .*$//; 1p')\"\nVERSION=\"${VERSION:-unknown}\"\n\ncase \"${VERSION##* }\" in\n\t2.*|3.*|4.0.*|4.1.*|4.2.*)\n\t\techo \"The compiler version does not support getenv() in spec files.\"\n\t\techo -n \"Wrapping binaries instead ... \"\n\n\t\tif \"${0%/*}/ext-toolchain.sh\" --toolchain \"$DIR\" --wrap \"${CPP%/*}\"; then\n\t\t\techo \"ok\"\n\t\t\texit 0\n\t\telse\n\t\t\techo \"failed\"\n\t\t\texit $?\n\t\tfi\n\t;;\n\t*)\n\t\tif patch_specs; then\n\t\t\techo \"Toolchain successfully patched.\"\n\t\t\texit 0\n\t\telse\n\t\t\techo \"Failed to locate library directory!\"\n\t\t\texit 1\n\t\tfi\n\t;;\nesac\n"
  },
  {
    "path": "scripts/portable_date.sh",
    "content": "#!/bin/sh\n\ncase $(uname) in\n\tNetBSD|OpenBSD|DragonFly|FreeBSD|Darwin)\n\t\tdate -j -f \"%Y-%m-%d %H:%M:%S %z\" \"$1\" \"$2\" 2>/dev/null\n\t\t;;\n\t*)\n\t\tdate -d \"$1\" \"$2\"\nesac\n\nexit $?\n"
  },
  {
    "path": "scripts/qemustart",
    "content": "#!/usr/bin/env bash\n\nSELF=\"$0\"\n\n# Linux bridge for connecting lan and wan network of guest machines\nBR_LAN=\"${BR_LAN:-br-lan}\"\nBR_WAN=\"${BR_WAN:-br-wan}\"\n\n# Host network interface providing internet access for guest machines\nIF_INET=\"${IF_INET:-eth0}\"\n\n# qemu-bridge-helper does two things here\n#\n# - create tap interface\n# - add the tap interface to bridge\n#\n# as such it requires CAP_NET_ADMIN to do its job.  It will be convenient to\n# have it as a root setuid program.  Be aware of the security risks implied\n#\n# the helper has an acl list which defaults to deny all bridge.  we need to add\n# $BR_LAN and $BR_WAN to its allow list\n#\n#\t# sudo vim /etc/qemu/bridge.conf\n#\tallow br-lan\n#\tallow br-wan\n#\n# Other allowed directives can be 'allow all', 'deny all', 'include xxx',  See\n# qemu-bridge-helper.c of qemu source code for details.\n#\n# The helper can be provided by package qemu-system-common on debian, or\n# qemu-kvm-common on rhel\n#\nHELPER=\"${HELPER:-/usr/libexec/qemu-bridge-helper}\"\n\n### end of global settings\n\n__errmsg() {\n\techo \"$*\" >&2\n}\n\ndo_setup() {\n\t# setup bridge for LAN network\n\tsudo ip link add dev \"$BR_LAN\" type bridge\n\tsudo ip link set dev \"$BR_LAN\" up\n\tsudo ip addr add 192.168.1.3/24 dev \"$BR_LAN\"\n\n\t# setup bridge for WAN network\n\t#\n\t# minimal dnsmasq config for configuring guest wan network with dhcp\n\t#\n\t#\t# sudo apt-get install dnsmasq\n\t#\t# sudo vi /etc/dnsmasq.conf\n\t#\tinterface=br-wan\n\t#\tdhcp-range=192.168.7.50,192.168.7.150,255.255.255.0,30m\n\t#\n\tsudo ip link add dev \"$BR_WAN\" type bridge\n\tsudo ip link set dev \"$BR_WAN\" up\n\tsudo ip addr add 192.168.7.1/24 dev \"$BR_WAN\"\n\n\t# guest internet access\n\tsudo sysctl -w \"net.ipv4.ip_forward=1\"\n\tsudo sysctl -w \"net.ipv4.conf.$BR_WAN.proxy_arp=1\"\n\twhile sudo iptables -t nat -D POSTROUTING -o \"$IF_INET\" -j MASQUERADE 2>/dev/null; do true; done\n\t      sudo iptables -t nat -A POSTROUTING -o \"$IF_INET\" -j MASQUERADE\n}\n\ncheck_setup_() {\n\tip link show \"$BR_LAN\" >/dev/null || return 1\n\tip link show \"$BR_WAN\" >/dev/null || return 1\n\t[ -x \"$HELPER\" ] || {\n\t\t__errmsg \"helper $HELPER is not an executable\"\n\t\treturn 1\n\t}\n}\n\ncheck_setup() {\n\t[ -n \"$o_network\" ] || return 0\n\tcheck_setup_ || {\n\t\t__errmsg \"please check the script content to see the environment requirement\"\n\t\treturn 1\n\t}\n}\n#do_setup; check_setup; exit $?\n\nusage() {\n\tcat >&2 <<EOF\nUsage: $SELF [-h|--help]\n       $SELF <target>\n         [<subtarget> [<extra-qemu-options>]]\n         [--kernel <kernel>]\n         [--rootfs <rootfs>]\n         [--machine <machine>]\n         [-n|--network]\n\n<subtarget> will default to \"generic\" and must be specified if\n<extra-qemu-options> are present\n\ne.g. <subtarget> for malta can be le, be, le64, be64, le-glibc, le64-glibc, etc\n\n<kernel>, <rootfs> can be required or optional arguments to qemu depending on\nthe actual <target> in use.  They will default to files under bin/targets/\n\nExamples\n\n  $SELF x86 64\n  $SELF x86 64 --machine q35,accel=kvm -device virtio-balloon-pci\n  $SELF x86 64 -incoming tcp:0:4444\n  $SELF x86 64-glibc\n  $SELF malta be -m 64\n  $SELF malta le64\n  $SELF malta be-glibc\n  $SELF armvirt 32 \\\\\n                --machine virt,highmem=off \\\\\n                --kernel bin/targets/armvirt/32/openwrt-armvirt-32-zImage \\\\\n                --rootfs bin/targets/armvirt/32/openwrt-armvirt-32-root.ext4\nEOF\n}\n\nrand_mac() {\n\thexdump -n 3 -e '\"52:54:00\" 3/1 \":%02x\"' /dev/urandom\n}\n\nparse_args() {\n\to_network=\n\to_qemu_extra=()\n\twhile [ \"$#\" -gt 0 ]; do\n\t\t# Cmdline options for the script itself SHOULD try to be\n\t\t# prefixed with two dashes to distinguish them from those for\n\t\t# qemu executables.\n\t\t#\n\t\t# Also note that qemu accepts both --opt and -opt\n\t\tcase \"$1\" in\n\t\t\t--kernel) o_kernel=\"$2\"; shift 2 ;;\n\t\t\t--rootfs) o_rootfs=\"$2\"; shift 2 ;;\n\t\t\t--machine|-machine|-M) o_mach=\"$2\"; shift 2 ;;\n\t\t\t--network|-n) o_network=1; shift ;;\n\t\t\t--help|-h)\n\t\t\t\tusage\n\t\t\t\texit 0\n\t\t\t\t;;\n\t\t\t*)\n\t\t\t\tif [ -z \"$o_target\" ]; then\n\t\t\t\t\to_target=\"$1\"\n\t\t\t\telif [ -z \"$o_subtarget\" ]; then\n\t\t\t\t\to_subtarget=\"$1\"\n\t\t\t\telse\n\t\t\t\t\to_qemu_extra+=(\"$1\")\n\t\t\t\tfi\n\t\t\t\tshift\n\t\t\t\t;;\n\t\tesac\n\tdone\n\n\tMAC_LAN=\"$(rand_mac)\"\n\tMAC_WAN=\"$(rand_mac)\"\n\t[ -n \"$o_target\" ] || {\n\t\tusage\n\t\treturn 1\n\t}\n\t[ -n \"$o_subtarget\" ] || o_subtarget=\"generic\"\n\to_bindir=\"bin/targets/$o_target/$o_subtarget\"\n}\n\nstart_qemu_armvirt() {\n\tlocal kernel=\"$o_kernel\"\n\tlocal rootfs=\"$o_rootfs\"\n\tlocal mach=\"${o_mach:-virt}\"\n\tlocal cpu\n\tlocal qemu_exe\n\n\tcase \"${o_subtarget%-*}\" in\n\t\t32)\n\t\t\tqemu_exe=\"qemu-system-arm\"\n\t\t\tcpu=\"cortex-a15\"\n\t\t\t[ -n \"$kernel\" ] || kernel=\"$o_bindir/openwrt-$o_target-${o_subtarget%-*}-zImage-initramfs\"\n\t\t\t;;\n\t\t64)\n\t\t\tqemu_exe=\"qemu-system-aarch64\"\n\t\t\tcpu=\"cortex-a57\"\n\t\t\t[ -n \"$kernel\" ] || kernel=\"$o_bindir/openwrt-$o_target-${o_subtarget%-*}-Image-initramfs\"\n\t\t\t;;\n\t\t*)\n\t\t\t__errmsg \"target $o_target: unknown subtarget $o_subtarget\"\n\t\t\treturn 1\n\t\t\t;;\n\tesac\n\t[ -z \"$rootfs\" ] || {\n\t\tif [ ! -f \"$rootfs\" -a -s \"$rootfs.gz\" ]; then\n\t\t\tgunzip \"$rootfs.gz\"\n\t\tfi\n\t\to_qemu_extra+=( \\\n\t\t\t\"-drive\" \"file=$rootfs,format=raw,if=virtio\" \\\n\t\t\t\"-append\" \"root=/dev/vda rootwait\" \\\n\t\t)\n\t}\n\n\t[ -z \"$o_network\" ] || {\n\t\to_qemu_extra+=( \\\n\t\t\t\"-netdev\" \"bridge,id=lan,br=$BR_LAN,helper=$HELPER\" \\\n\t\t\t    \"-device\" \"virtio-net-pci,id=devlan,netdev=lan,mac=$MAC_LAN\" \\\n\t\t\t\"-netdev\" \"bridge,id=wan,br=$BR_WAN,helper=$HELPER\" \"-device\" \\\n\t\t\t    \"virtio-net-pci,id=devwan,netdev=wan,mac=$MAC_WAN\" \\\n\t\t)\n\t}\n\n\t\"$qemu_exe\" -machine \"$mach\" -cpu \"$cpu\" -nographic \\\n\t\t-kernel \"$kernel\" \\\n\t\t\"${o_qemu_extra[@]}\"\n}\n\nstart_qemu_malta() {\n\tlocal is64\n\tlocal isel\n\tlocal qemu_exe\n\tlocal cpu\n\tlocal rootfs=\"$o_rootfs\"\n\tlocal kernel=\"$o_kernel\"\n\tlocal mach=\"${o_mach:-malta}\"\n\n\t# o_subtarget can be le, be, le64, be64, le-glibc, le64-glibc, etc..\n\tis64=\"$(echo $o_subtarget | grep -o 64)\"\n\t[ \"$(echo \"$o_subtarget\" | grep -o '^..')\" = \"le\" ] && isel=\"el\"\n\tqemu_exe=\"qemu-system-mips$is64$isel\"\n\t[ -n \"$is64\" ] && cpu=\"MIPS64R2-generic\" || cpu=\"24Kc\"\n\n\t[ -n \"$kernel\" ] || kernel=\"$o_bindir/openwrt-malta-${o_subtarget%-*}-vmlinux-initramfs.elf\"\n\n\t[ -z \"$rootfs\" ] || {\n\t\tif [ ! -f \"$rootfs\" -a -s \"$rootfs.gz\" ]; then\n\t\t\tgunzip \"$rootfs.gz\"\n\t\tfi\n\t\to_qemu_extra+=( \\\n\t\t\t\"-drive\" \"file=$rootfs,format=raw\" \\\n\t\t\t\"-append\" \"root=/dev/sda rootwait\" \\\n\t\t)\n\t}\n\n\t# NOTE: order of wan, lan -device arguments matters as it will affect which\n\t# one will be actually used as the wan, lan network interface inside the\n\t# guest machine\n\t[ -z \"$o_network\" ] || {\n\t\to_qemu_extra+=(\n\t\t\t-netdev bridge,id=wan,br=\"$BR_WAN,helper=$HELPER\" -device pcnet,netdev=wan,mac=\"$MAC_WAN\"\n\t\t\t-netdev bridge,id=lan,br=\"$BR_LAN,helper=$HELPER\" -device pcnet,netdev=lan,mac=\"$MAC_LAN\"\n\t\t)\n\t}\n\n\t\"$qemu_exe\" -machine \"$mach\" -cpu \"$cpu\" -nographic \\\n\t\t-kernel \"$kernel\" \\\n\t\t\"${o_qemu_extra[@]}\"\n}\n\nstart_qemu_x86() {\n\tlocal qemu_exe\n\tlocal kernel=\"$o_kernel\"\n\tlocal rootfs=\"$o_rootfs\"\n\tlocal mach=\"${o_mach:-pc}\"\n\n\t[ -n \"$rootfs\" ] || {\n\t\trootfs=\"$o_bindir/openwrt-$o_target-${o_subtarget%-*}-generic-squashfs-combined.img\"\n\t\tif [ ! -f \"$rootfs\" -a -s \"$rootfs.gz\" ]; then\n\t\t\tgunzip \"$rootfs.gz\"\n\t\tfi\n\t}\n\t#\n\t# generic: 32-bit, pentium4 (CONFIG_MPENTIUM4), kvm guest, virtio\n\t# legacy: 32-bit, i486 (CONFIG_M486)\n\t# 64: 64-bit, kvm guest, virtio\n\t#\n\tcase \"${o_subtarget%-*}\" in\n\t\tlegacy)\t\t\tqemu_exe=\"qemu-system-i386\"\t;;\n\t\tgeneric|64)\t\tqemu_exe=\"qemu-system-x86_64\"\t;;\n\t\t*)\n\t\t\t__errmsg \"target $o_target: unknown subtarget $o_subtarget\"\n\t\t\treturn 1\n\t\t\t;;\n\tesac\n\n\t[ -n \"$kernel\" ] && {\n\t    o_qemu_extra+=( \\\n\t\t\"-kernel\" \"$kernel\" \\\n\t\t\"-append\" \"root=/dev/vda console=ttyS0 rootwait\" \\\n\t    )\n\t}\n\n\t[ -z \"$o_network\" ] || {\n\t\tcase \"${o_subtarget%-*}\" in\n\t\t\tlegacy)\n\t\t\t\to_qemu_extra+=(\n\t\t\t\t\t-netdev \"bridge,id=lan,br=$BR_LAN,helper=$HELPER\" -device \"e1000,id=devlan,netdev=lan,mac=$MAC_LAN\"\n\t\t\t\t\t-netdev \"bridge,id=wan,br=$BR_WAN,helper=$HELPER\" -device \"e1000,id=devwan,netdev=wan,mac=$MAC_WAN\"\n\t\t\t\t)\n\t\t\t\t;;\n\t\t\tgeneric|64)\n\t\t\t\to_qemu_extra+=(\n\t\t\t\t\t-netdev \"bridge,id=lan,br=$BR_LAN,helper=$HELPER\" -device \"virtio-net-pci,id=devlan,netdev=lan,mac=$MAC_LAN\"\n\t\t\t\t\t-netdev \"bridge,id=wan,br=$BR_WAN,helper=$HELPER\" -device \"virtio-net-pci,id=devwan,netdev=wan,mac=$MAC_WAN\"\n\t\t\t\t)\n\t\t\t\t;;\n\t\tesac\n\t}\n\n\tcase \"${o_subtarget%-*}\" in\n\t\tlegacy)\n\t\t\t# use IDE (PATA) disk instead of AHCI (SATA).  Refer to link\n\t\t\t# [1] for related discussions\n\t\t\t#\n\t\t\t# To use AHCI interface\n\t\t\t#\n\t\t\t#\t-device ich9-ahci,id=ahci \\\n\t\t\t#\t-device ide-drive,drive=drv0,bus=ahci.0 \\\n\t\t\t#\t-drive \"file=$rootfs,format=raw,id=drv0,if=none\" \\\n\t\t\t#\n\t\t\t# [1] https://dev.openwrt.org/ticket/17947\n\t\t\t\"$qemu_exe\" -machine \"$mach\" -nographic \\\n\t\t\t\t-device ide-drive,drive=drv0 \\\n\t\t\t\t-drive \"file=$rootfs,format=raw,id=drv0,if=none\" \\\n\t\t\t\t\"${o_qemu_extra[@]}\"\n\t\t\t;;\n\t\tgeneric|64)\n\t\t\t\"$qemu_exe\" -machine \"$mach\" -nographic \\\n\t\t\t\t-drive \"file=$rootfs,format=raw,if=virtio\" \\\n\t\t\t\t\"${o_qemu_extra[@]}\"\n\t\t\t;;\n\tesac\n}\n\nstart_qemu() {\n\tcase \"$o_target\" in\n\t\tarmvirt)\tstart_qemu_armvirt\t;;\n\t\tmalta)\t\tstart_qemu_malta\t;;\n\t\tx86)\t\tstart_qemu_x86\t\t;;\n\t\t*)\n\t\t\t__errmsg \"target $o_target is not supported yet\"\n\t\t\treturn 1\n\t\t\t;;\n\tesac\n}\n\nparse_args \"$@\" \\\n\t&& check_setup \\\n\t&& start_qemu\n"
  },
  {
    "path": "scripts/redboot-script.pl",
    "content": "#!/usr/bin/env perl\n#\n# Script for generating redboot configs, based on brcmImage.pl\n#\n# Copyright (C) 2015 Álvaro Fernández Rojas <noltari@gmail.com>\n#\n# This program is free software; you can redistribute it and/or modify\n# it under the terms of the GNU General Public License as published by\n# the Free Software Foundation; either version 2 of the License, or\n# (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n# GNU General Public License for more details.\n#\n# You should have received a copy of the GNU General Public License\n# along with this program; if not, write to the Free Software\n# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.\n#\n\nuse strict;\nuse Getopt::Std;\nuse File::stat;\n\nmy $version = \"0.1\";\nmy %arg = (\n\to => 'redboot.script',\n\ts => 0x1000,\n\tf => 0xbe430000,\n\ta => 0x80010000,\n\tl => 0x7c0000,\n\tt => 20,\n);\nmy $prog = $0;\n$prog =~ s/^.*\\///;\ngetopts(\"r:k:o:s:f:a:l:t:vh\", \\%arg);\n\ndie \"usage: $prog ~opts~\n\n  -r <file>\t: input rootfs file\n  -k <file>\t: input kernel file\n  -o <file>\t: output image file, default $arg{o}\n  -s <size_kb>\t: redboot script size, default \".sprintf('%d', parse_num($arg{s})).\"\n  -f <baseaddr>\t: flash base, default \".sprintf('0x%x', parse_num($arg{f})).\"\n  -a <loadaddr>\t: Kernel load address, default \".sprintf('0x%x', parse_num($arg{a})).\"\n  -l <linux_kb>\t: linux partition size, default \".sprintf('0x%x', parse_num($arg{l})).\"\n  -t <timeout> \t: redboot script timeout, default \".sprintf('%d', parse_num($arg{t})).\"\n  -v\t\t: be more verbose\n  -h\t\t: help, version $version\n\nEXAMPLES:\n    $prog -k kern -r rootfs\n\" if $arg{h} || !$arg{k} || !$arg{r};\n\nsub parse_num\n{\n\tmy $num = @_[0];\n\tif (index(lc($num), lc(\"0x\")) == 0) {\n\t\treturn hex($num);\n\t} else {\n\t\treturn $num + 0;\n\t}\n}\n\nsub gen_script\n{\n\tmy $kernel_off = parse_num($arg{s});\n\tmy $kernel_addr = parse_num($arg{f});\n\tmy $kernel_len = stat($arg{k})->size;\n\n\tmy $rootfs_off = $kernel_off + $kernel_len;\n\tmy $rootfs_addr = $kernel_addr + $kernel_len;\n\tmy $rootfs_len = parse_num($arg{l}) - $kernel_len;\n\tmy $rootfs_size = stat($arg{r})->size;\n\n\tmy $load_addr = parse_num($arg{a});\n\n\tmy $timeout = parse_num($arg{t});\n\n\tif ($arg{v}) {\n\t\tprintf \"kernel_off: 0x%x(%u)\\n\", $kernel_off, $kernel_off;\n\t\tprintf \"kernel_addr: 0x%x(%u)\\n\", $kernel_addr, $kernel_addr;\n\t\tprintf \"kernel_len: 0x%x(%u)\\n\", $kernel_len, $kernel_len;\n\n\t\tprintf \"rootfs_off: 0x%x(%u)\\n\", $rootfs_off, $rootfs_off;\n\t\tprintf \"rootfs_addr: 0x%x(%u)\\n\", $rootfs_addr, $rootfs_addr;\n\t\tprintf \"rootfs_len: 0x%x(%u)\\n\", $rootfs_len, $rootfs_len;\n\t\tprintf \"rootfs_size: 0x%x(%u)\\n\", $rootfs_size, $rootfs_size;\n\t}\n\n\topen(FO, \">$arg{o}\");\n\tprintf FO \"fis init -f\\n\";\n\tprintf FO \"\\n\";\n\tprintf FO \"fconfig boot_script true\\n\";\n\tprintf FO \"fconfig boot_script_data\\n\";\n\tprintf FO \"fis load -b 0x%x -d kernel\\n\", $load_addr;\n\tprintf FO \"exec -c \\\"noinitrd\\\" 0x%x\\n\", $load_addr;\n\tprintf FO \"\\n\";\n\tprintf FO \"fconfig boot_script_timeout %d\\n\", $timeout;\n\tprintf FO \"\\n\";\n\tprintf FO \"fis create -o 0x%x -f 0x%x -l 0x%x kernel\\n\", $kernel_off, $kernel_addr, $kernel_len;\n\tprintf FO \"\\n\";\n\tprintf FO \"fis create -o 0x%x -s 0x%x -f 0x%x -l 0x%x rootfs\\n\", $rootfs_off, $rootfs_size, $rootfs_addr, $rootfs_len;\n\tprintf FO \"\\n\";\n\tprintf FO \"reset\\n\";\n\tclose FO;\n}\n\n# MAIN\ngen_script();\n"
  },
  {
    "path": "scripts/relink-lib.sh",
    "content": "#!/bin/sh\n[ $# -lt 4 -o -z \"$1\" -o -z \"$2\" -o -z \"$3\" -o -z \"$4\" ] && {\n\techo \"Usage: $0 <cross> <reference> <pic .a> <destination>\"\n\texit 1\n}\n\ncross=\"$1\"; shift\nref=\"$1\"; shift\npic=\"$1\"; shift\ndest=\"$1\"; shift\n\nSYMBOLS=\"$(${cross}nm \"$ref\" | grep -E '........ [TW] ' | awk '$3 {printf \"-u%s \", $3}')\"\nset -x\n${cross}gcc -nostdlib -nostartfiles -shared -Wl,--gc-sections -o \"$dest\" $SYMBOLS \"$pic\" \"$@\"\n"
  },
  {
    "path": "scripts/remote-gdb",
    "content": "#!/usr/bin/env perl\n\nuse strict;\nuse warnings;\nuse FindBin '$Bin';\nuse File::Temp 'tempfile';\n\n@ARGV == 2 || do {\n\tdie \"Usage: $0 <corefile|host:port> <executable>\\n\";\n\texit 1;\n};\n\nif( opendir SD, \"$Bin/../staging_dir\" )\n{\n\tmy ( $tid, $arch, $libc, @arches );\n\n\tif( $ARGV[1] =~ m!\\btarget-(.+?)_([^/_]+libc|musl)_?([^/]*).*\\b!i )\n\t{\n\t\tprint(\"Using target $1 ($2, $3)\\n\");\n\t\t($arch, $libc) = ($1, $2);\n\t}\n\telse\n\t{\n\t\t# Find arches\n\t\tprint(\"Choose target:\\n\");\n\n\t\twhile( defined( my $e = readdir SD ) )\n\t\t{\n\t\t\tif( -d \"$Bin/../staging_dir/$e\" && $e =~ /^target-(.+?)_([^\\/_]+libc|musl)_?([^\\/]*).*/i )\n\t\t\t{\n\t\t\t\tpush @arches, [ $1, $2 ];\n\t\t\t\tprintf(\" %2d) %s (%s %s)\\n\", @arches + 0, $1, $2, $3);\n\t\t\t}\n\t\t}\n\n\t\tif( @arches > 1 )\n\t\t{\n\t\t\t# Query arch\n\t\t\tdo {\n\t\t\t\tprint(\"Target? > \");\n\t\t\t\tchomp($tid = <STDIN>);\n\t\t\t} while( !defined($tid) || $tid !~ /^\\d+$/ || $tid < 1 || $tid > @arches );\n\n\t\t\t($arch, $libc) = @{$arches[$tid-1]};\n\t\t}\n\t\telse\n\t\t{\n\t\t\t($arch, $libc) = @{$arches[0]};\n\t\t}\n\t}\n\n\tclosedir SD;\n\n\t# Find gdb\n\tmy ($gdb) = glob(\"$Bin/../staging_dir/toolchain-${arch}_*_${libc}*/bin/*-gdb\");\n\tif( defined($gdb) && -x $gdb )\n\t{\n\t\tmy ( $fh, $fp ) = tempfile();\n\n\t\t# Find sysroot\n\t\tmy ($sysroot) = glob(\"$Bin/../staging_dir/target-${arch}_${libc}*/root-*/\");\n\n\t\tprint $fh \"set sysroot $sysroot\\n\" if $sysroot;\n\t\tmy $cmd = \"target extended-remote\";\n\t\t-f $ARGV[0] and $cmd = \"core-file\";\n\t\tprint $fh \"$cmd $ARGV[0]\\n\";\n\n\t\t# History settings\n\t\tprint $fh \"set history filename $Bin/../tmp/.gdb_history\\n\";\n\t\tprint $fh \"set history size 100000000\\n\";\n\t\tprint $fh \"set history save on\\n\";\n\n\t\tmy $file = -f \"$sysroot/$ARGV[1]\" ? \"$sysroot/$ARGV[1]\" : $ARGV[1];\n\t\tsystem($gdb, '-x', $fp, $file);\n\n\t\tclose($fh);\n\t\tunlink($fp);\n\t}\n\telse\n\t{\n\t\tprint(\"No gdb found! Make sure that CONFIG_GDB is set!\\n\");\n\t\texit(1);\n\t}\n}\nelse\n{\n\tprint(\"No staging_dir found! You need to compile at least once!\\n\");\n\texit(1);\n}\n"
  },
  {
    "path": "scripts/rstrip.sh",
    "content": "#!/usr/bin/env bash\n# \n# Copyright (C) 2006 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\nSELF=${0##*/}\n\n[ -z \"$STRIP\" ] && {\n  echo \"$SELF: strip command not defined (STRIP variable not set)\"\n  exit 1\n}\n\nTARGETS=$*\n\n[ -z \"$TARGETS\" ] && {\n  echo \"$SELF: no directories / files specified\"\n  echo \"usage: $SELF [PATH...]\"\n  exit 1\n}\n\nfind $TARGETS -type f -a -exec file {} \\; | \\\n  sed -n -e 's/^\\(.*\\):.*ELF.*\\(executable\\|relocatable\\|shared object\\).*,.*/\\1:\\2/p' | \\\n(\n  IFS=\":\"\n  while read F S; do\n    echo \"$SELF: $F: $S\"\n\t[ \"${S}\" = \"relocatable\" ] && {\n\t\t[ \"${F##*.}\" == \"o\" ] && continue\n\t\teval \"$STRIP_KMOD $F\"\n\t} || {\n\t\tb=$(stat -c '%a' $F)\n\t\t[ -z \"$PATCHELF\" ] || [ -z \"$TOPDIR\" ] || {\n\t\t\told_rpath=\"$($PATCHELF --print-rpath $F)\"; new_rpath=\"\"\n\t\t\tfor path in $old_rpath; do\n\t\t\t\tcase \"$path\" in\n\t\t\t\t\t/lib/[^/]*|/usr/lib/[^/]*|\\$ORIGIN/*|\\$ORIGIN) new_rpath=\"${new_rpath:+$new_rpath:}$path\" ;;\n\t\t\t\t\t*) echo \"$SELF: $F: removing rpath $path\" ;;\n\t\t\t\tesac\n\t\t\tdone\n\t\t\t[ \"$new_rpath\" = \"$old_rpath\" ] || $PATCHELF --set-rpath \"$new_rpath\" $F\n\t\t}\n\t\teval \"$STRIP $F\"\n\t\ta=$(stat -c '%a' $F)\n\t\t[ \"$a\" = \"$b\" ] || chmod $b $F\n\t}\n  done\n  true\n)\n"
  },
  {
    "path": "scripts/sercomm-crypto.py",
    "content": "#!/usr/bin/env python3\n\nimport argparse\nimport binascii\nimport hashlib\nimport os\nimport struct\n\ndef create_header(key, version, iv, random, size):\n\theader = struct.pack('32s32s32s32s32s', key, version, iv, random, size)\n\n\treturn header\n\ndef create_output(args):\n\tin_st = os.stat(args.input_file)\n\tin_size = in_st.st_size\n\n\tkey = \"\".encode('ascii')\n\tversion = args.version.encode('ascii')\n\tiv = \"\".encode('ascii')\n\trandom = \"\".encode('ascii')\n\tsize = str(in_size).encode('ascii')\n\theader = create_header(key, version, iv, random, size)\n\n\tout_f = open(args.output_file, 'w+b')\n\tout_f.write(header)\n\tout_f.close()\n\n\tmd5 = hashlib.md5()\n\tmd5.update(header[0x60:0x80])\n\tmd5.update(header[0x20:0x40])\n\tmd5_1 = md5.digest()\n\n\tmd5 = hashlib.md5()\n\tmd5.update(header[0x80:0xA0])\n\tmd5.update(header[0x20:0x40])\n\tmd5_2 = md5.digest()\n\n\tkey = md5_1 + md5_2\n\n\tkey_f = open(args.key_file, 'w+b')\n\tkey_f.write(binascii.hexlify(bytearray(key)))\n\tkey_f.close()\n\n\tprint(\"AES 256 CBC Key:\", binascii.hexlify(bytearray(key)))\n\ndef main():\n\tglobal args\n\n\tparser = argparse.ArgumentParser(description='')\n\n\tparser.add_argument('--input-file',\n\t\tdest='input_file',\n\t\taction='store',\n\t\ttype=str,\n\t\thelp='Input file')\n\n\tparser.add_argument('--key-file',\n\t\tdest='key_file',\n\t\taction='store',\n\t\ttype=str,\n\t\thelp='AES 256 CBC Key File')\n\n\tparser.add_argument('--output-file',\n\t\tdest='output_file',\n\t\taction='store',\n\t\ttype=str,\n\t\thelp='Output file')\n\n\tparser.add_argument('--version',\n\t\tdest='version',\n\t\taction='store',\n\t\ttype=str,\n\t\thelp='Version')\n\n\targs = parser.parse_args()\n\n\tif ((not args.input_file) or\n\t    (not args.key_file) or\n\t    (not args.output_file) or\n\t    (not args.version)):\n\t\tparser.print_help()\n\n\tcreate_output(args)\n\nmain()\n"
  },
  {
    "path": "scripts/sercomm-partition-tag.py",
    "content": "#!/usr/bin/env python3\n\nimport argparse\nimport os\nimport struct\n\ndef create_header(args, size):\n\theader = struct.pack('32s32s32s32s32s',\n\t\targs.part_name.encode('ascii'),\n\t\tstr(size).encode('ascii'),\n\t\targs.part_version.encode('ascii'),\n\t\t\"\".encode('ascii'),\n\t\targs.rootfs_version.encode('ascii'))\n\n\treturn header\n\ndef create_output(args):\n\tin_st = os.stat(args.input_file)\n\tin_size = in_st.st_size\n\n\theader = create_header(args, in_size)\n\tprint(header)\n\n\tin_f = open(args.input_file, 'r+b')\n\tin_bytes = in_f.read(in_size)\n\tin_f.close()\n\n\tout_f = open(args.output_file, 'w+b')\n\tout_f.write(header)\n\tout_f.write(in_bytes)\n\tout_f.close()\n\ndef main():\n\tglobal args\n\n\tparser = argparse.ArgumentParser(description='')\n\n\tparser.add_argument('--input-file',\n\t\tdest='input_file',\n\t\taction='store',\n\t\ttype=str,\n\t\thelp='Input file')\n\n\tparser.add_argument('--output-file',\n\t\tdest='output_file',\n\t\taction='store',\n\t\ttype=str,\n\t\thelp='Output file')\n\n\tparser.add_argument('--part-name',\n\t\tdest='part_name',\n\t\taction='store',\n\t\ttype=str,\n\t\thelp='Partition Name')\n\n\tparser.add_argument('--part-version',\n\t\tdest='part_version',\n\t\taction='store',\n\t\ttype=str,\n\t\thelp='Partition Version')\n\n\tparser.add_argument('--rootfs-version',\n\t\tdest='rootfs_version',\n\t\taction='store',\n\t\ttype=str,\n\t\thelp='RootFS lib version')\n\n\targs = parser.parse_args()\n\n\tif not args.rootfs_version:\n\t\targs.rootfs_version = \"\"\n\n\tif ((not args.input_file) or\n\t    (not args.output_file) or\n\t    (not args.part_name) or\n\t    (not args.part_version)):\n\t\tparser.print_help()\n\n\tcreate_output(args)\n\nmain()\n"
  },
  {
    "path": "scripts/sercomm-payload.py",
    "content": "#!/usr/bin/env python3\n\nimport argparse\nimport hashlib\nimport os\n\ndef create_output(args):\n\tin_st = os.stat(args.input_file)\n\tin_size = in_st.st_size\n\n\tin_f = open(args.input_file, 'r+b')\n\tin_bytes = in_f.read(in_size)\n\tin_f.close()\n\n\tsha256 = hashlib.sha256()\n\tsha256.update(in_bytes)\n\n\tout_f = open(args.output_file, 'w+b')\n\tout_f.write(bytes.fromhex(args.pid))\n\tout_f.write(sha256.digest())\n\tout_f.write(in_bytes)\n\tout_f.close()\n\ndef main():\n\tglobal args\n\n\tparser = argparse.ArgumentParser(description='')\n\n\tparser.add_argument('--input-file',\n\t\tdest='input_file',\n\t\taction='store',\n\t\ttype=str,\n\t\thelp='Input file')\n\n\tparser.add_argument('--output-file',\n\t\tdest='output_file',\n\t\taction='store',\n\t\ttype=str,\n\t\thelp='Output file')\n\n\tparser.add_argument('--pid',\n\t\tdest='pid',\n\t\taction='store',\n\t\ttype=str,\n\t\thelp='Sercomm PID')\n\n\targs = parser.parse_args()\n\n\tif ((not args.input_file) or\n\t    (not args.output_file) or\n\t    (not args.pid)):\n\t\tparser.print_help()\n\n\tcreate_output(args)\n\nmain()\n"
  },
  {
    "path": "scripts/sign_images.sh",
    "content": "#!/bin/sh\n\n# directory where search for images\nTOP_DIR=\"${TOP_DIR:-./bin/targets}\"\n# key to sign images\nBUILD_KEY=\"${BUILD_KEY:-key-build}\" # TODO unify naming?\n# remove other signatures (added e.g.  by buildbot)\nREMOVE_OTER_SIGNATURES=\"${REMOVE_OTER_SIGNATURES:-1}\"\n\n# find all sysupgrade images in TOP_DIR\n# factory images don't need signatures as non OpenWrt system doesn't check them anyway\nfor image in $(find $TOP_DIR -type f -name \"*-sysupgrade.bin\"); do\n\t# check if image actually support metadata\n\tif fwtool -i /dev/null \"$image\"; then\n\t\t# remove all previous signatures\n\t\tif [ -n \"$REMOVE_OTER_SIGNATURES\" ]; then\n\t\t\twhile [ \"$?\" = 0 ]; do\n\t\t\t\tfwtool -t -s /dev/null \"$image\"\n\t\t\tdone\n\t\tfi\n\t\t# run same operation as build root does for signing\n\t\tcp \"$BUILD_KEY.ucert\" \"$image.ucert\"\n\t\tusign -S -m \"$image\" -s \"$BUILD_KEY\" -x \"$image.sig\"\n\t\tucert -A -c \"$image.ucert\" -x \"$image.sig\"\n\t\tfwtool -S \"$image.ucert\" \"$image\"\n\tfi\ndone\n"
  },
  {
    "path": "scripts/size_compare.sh",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n#\n# Copyright (C) 2020 Paul Spooren <mail@aparcar.org>\n#\n###\n### size_compare - compare size of OpenWrt packages against upstream\n###\n### The script compares locally compiled package with the package indexes\n### available upstream. This way the storage impact of optimizations or\n### feature modifications is easy to see.\n###\n### If no environmental variables are set the script reads the current\n### .config file. The evaluated env variables are the following:\n###\n###   TARGET SUBTARGET ARCH PACKAGES BIN_DIR BASE_URL CHECK_INSTALLED\n###\n### Usage:\n###   ./scripts/size_compare.sh\n###\n### Options:\n###   -p --package-size \tCheck IPK package size and not installed size\n###   -h --help \t\tThis message\n\nCONFIG_TARGET=$(sed -n 's/^CONFIG_TARGET_BOARD=\"\\(.*\\)\"$/\\1/p' .config)\nCONFIG_SUBTARGET=$(sed -n 's/^CONFIG_TARGET_SUBTARGET=\"\\(.*\\)\"$/\\1/p' .config)\nCONFIG_ARCH=$(sed -n 's/^CONFIG_TARGET_ARCH_PACKAGES=\"\\(.*\\)\"$/\\1/p' .config)\nCONFIG_PACKAGES=$(sed -n 's/^CONFIG_PACKAGE_\\(.*\\)=y$/\\1/p' .config | tr '\\n' ' ')\nCONFIG_BIN_DIR=$(sed -n 's/^CONFIG_BINARY_DIR=\"\\(.*\\)\"$/\\1/p' .config)\n\nTARGET=${TARGET:-$CONFIG_TARGET}\nSUBTARGET=${SUBTARGET:-$CONFIG_SUBTARGET}\nARCH=${ARCH:-$CONFIG_ARCH}\nPACKAGES=${PACKAGES:-$CONFIG_PACKAGES}\nBIN_DIR=${CONFIG_BIN_DIR:-./bin}\nBASE_URL=\"${BASE_URL:-https://downloads.openwrt.org/snapshots}\"\nCHECK_INSTALLED=\"${CHECK_INSTALLED:-y}\"\n\nTARGET_URL=\"$BASE_URL/targets/$TARGET/$SUBTARGET/packages/Packages.gz\"\nCONFIG_URL=\"$BASE_URL/targets/$TARGET/$SUBTARGET/config.buildinfo\"\nPACKAGES_URL=\"$BASE_URL/packages/$ARCH/base/Packages.gz\"\n\nif command -v curl > /dev/null; then\n\tDOWNLOAD_METHOD=\"curl\"\nelse\n\tDOWNLOAD_METHOD=\"wget --output-document=-\"\nfi\n\nhelp() {\n    sed -rn 's/^### ?//;T;p' \"$0\"\n}\n\npackage_size () {\n\tFOUND_PACKAGE=\n\tif [ -z \"$CHECK_INSTALLED\" ]; then\n\t\tSEARCH_PATTERN=\"Size\"\n\telse\n\t\tSEARCH_PATTERN=\"Installed-Size\"\n\tfi\n\twhile IFS= read -r line; do\n\t\tif [ \"$line\" = \"Package: $2\" ]; then\n\t\t\tFOUND_PACKAGE=y\n\t\tfi\n\t\tif [ -n \"$FOUND_PACKAGE\" ]; then\n\t\t\tcase $line in\n\t\t\t\t\"$SEARCH_PATTERN\"*)\n\t\t\t\t\techo \"$line\" | cut -d ' ' -f 2\n\t\t\t\t\tbreak\n\t\t\t\t\t;;\n\t\t\tesac\n\t\tfi\n\tdone < \"$1\"\n}\n\ncompare_sizes () {\n\tfor PACKAGE in $PACKAGES; do\n\t\tif [ \"$PACKAGE\" = \"libc\" ]; then\n\t\t\tcontinue\n\t\tfi\n\t\tPACKAGE_FILE=$(find \"$BIN_DIR/packages/$ARCH/\" \\\n\t\t\t\"$BIN_DIR/targets/$TARGET/$SUBTARGET/\" \\\n\t\t\t-name \"${PACKAGE}_*.ipk\" 2>/dev/null | head -n1)\n\n\t\tif [ -z \"$PACKAGE_FILE\" ]; then\n\t\t\tcontinue\n\t\tfi\n\t\tif [ -z \"$CHECK_INSTALLED\" ]; then\n\t\t\tSIZE_LOCAL=$(stat -c '%s' \"$PACKAGE_FILE\")\n\t\telse\n\t\t\tSIZE_LOCAL=$(tar tzvf \"$PACKAGE_FILE\" ./data.tar.gz | awk '{ print $3 }')\n\t\tfi\n\t\tSIZE_UPSTREAM=$(package_size \"$TMP_INDEX\" \"$PACKAGE\")\n\t\tSIZE_DIFF=\"$((SIZE_LOCAL-SIZE_UPSTREAM))\"\n\t\tif [ \"$SIZE_DIFF\" -gt 0 ]; then\n\t\t\tSIZE_DIFF=\"+$SIZE_DIFF\"\n\t\tfi\n\t\tif [ -n \"$SIZE_UPSTREAM\" ]; then\n\t\t\techo \"${SIZE_DIFF}\t${SIZE_LOCAL}\t${SIZE_UPSTREAM}\t$PACKAGE\"\n\t\telse\n\t\t\techo \"$PACKAGE is missing upstream\"\n\t\tfi\n\tdone\n}\n\nif [ \"$1\" = \"-h\" ]; then\n    help\n    exit 0\nfi\n\nif [ \"$1\" = \"-p\" ]; then\n    CHECK_INSTALLED=\nfi\n\necho \"Compare packages of $TARGET/$SUBTARGET/$ARCH\":\necho \"$PACKAGES\"\necho\n\necho \"Checking configuration difference\"\nTMP_CONFIG=$(mktemp /tmp/config.XXXXXX)\nsed -n 's/^\t\\+config \\(.*\\)/\\1/p' config/Config-build.in config/Config-devel.in > \"${TMP_CONFIG}-FOCUS\"\nsort .config | grep -f \"${TMP_CONFIG}-FOCUS\" | grep -v \"^#\" | sort > \"${TMP_CONFIG}-LOCAL\"\nmv .config .config.bak\n\"$DOWNLOAD_METHOD\" \"$CONFIG_URL\" > .config\nmake defconfig > /dev/null 2> /dev/null\ngrep -f \"${TMP_CONFIG}-FOCUS\" .config | grep -v \"^#\" | sort > \"${TMP_CONFIG}-UPSTREAM\"\nmv .config.bak .config\n\necho\necho \" --- start config diff ---\"\ndiff -u \"${TMP_CONFIG}-LOCAL\" \"${TMP_CONFIG}-UPSTREAM\"\necho \" --- end config diff ---\"\nrm \"${TMP_CONFIG}-FOCUS\" \"${TMP_CONFIG}-UPSTREAM\" \"${TMP_CONFIG}-LOCAL\"\necho\n\nif [ -z \"$CHECK_INSTALLED\" ]; then\n\techo \"Checking IPK package size\"\nelse\n\techo \"Checking installed size\"\nfi\necho\n\necho \"Fetching latest package indexes...\"\nTMP_INDEX=$(mktemp /tmp/size_compare_package_index.XXXXXX)\n\"$DOWNLOAD_METHOD\" \"$TARGET_URL\" | gzip -d > \"$TMP_INDEX\" || exit 1\n\"$DOWNLOAD_METHOD\" \"$PACKAGES_URL\" | gzip -d >> \"$TMP_INDEX\" || exit 1\necho\n\necho \"Comparing package sizes...\"\necho \"Change \tLocal\tRemote \tPackage\"\ncompare_sizes | sort -g -r\n\nrm \"$TMP_INDEX\"\n"
  },
  {
    "path": "scripts/slugimage.pl",
    "content": "#!/usr/bin/env perl\n# \n# SlugImage : Manipulate NSLU2 firmware images\n#             Dwayne Fontenot (jacques)\n#             Rod Whitby (rwhitby)\n#\t      www.nslu2-linux.org\n#\n# Copyright (c) 2004, 2006, Dwayne Fontenot & Rod Whitby\n# All rights reserved.\n# \n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n# \n# Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in the\n# documentation and/or other materials provided with the distribution.\n# Neither the name of the NSLU2-Linux Development Team nor the names\n# of its contributors may be used to endorse or promote products\n# derived from this software without specific prior written\n# permission.\n# \n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n# POSSIBILITY OF SUCH DAMAGE.\n#\n\nuse strict;\nuse warnings;\n\nuse Getopt::Long qw(:config no_ignore_case);\nuse File::Temp qw(tempfile);\n\nmy($debug) = 0;\nmy($quiet) = 0;\nmy($flash_start)    = 0x50000000;\nmy($flash_len)      = 0x00800000;\nmy($block_size)     = 0x00020000;\nmy($kernel_offset)  = 0x00060000;\nmy($kernel_size)    = 0x00100000;\nmy($ramdisk_offset) = 0x00160000;\nmy(@cleanup);\n\n# The last 70 bytes of the SercommRedBootTrailer (i.e. excluding MAC\n# address).  Needed to create an image with an empty RedBoot partition\n# since the Sercomm upgrade tool checks for this trailer.\n# http://www.nslu2-linux.org/wiki/Info/SercommRedBootTrailer\nmy @sercomm_redboot_trailer = (0x4573, 0x4372, 0x4d6f, 0x006d, 0x0001,\n       0x0400, 0x3170, 0x5895, 0x0010, 0x0000, 0x0000, 0x0000, 0x0000,\n       0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n       0x0000, 0x0000, 0x0001, 0x0000, 0x0000, 0x0000, 0x0003, 0x2300,\n       0x0063, 0x0000, 0x7320, 0x7245, 0x6f43, 0x6d4d);\n\n# There's a 16 byte Sercomm trailer at the end of the flash. It is used\n# by RedBoot to detect a Sercomm flash layout and to configure the\n# Sercomm upgrade system.\n# http://www.nslu2-linux.org/wiki/Info/SercommFlashTrailer\nmy @sercomm_flash_trailer = (0x0100, 0x0000, 0x6323, 0xf790, 0x5265,\n                             0x4f63, 0x4d6d, 0xb400);\n\n# Take $data, and pad it out to $total_len bytes, appending 0xff's.\nsub padBytes {\n    my($data,$total_len) = @_;\n\n    # 0xFF is used to pad, as it's the erase value of the flash.\n    my($pad_char) = pack(\"C\",0xff);\n    my($pad_len) = $total_len - length($data);\n\n    # A request for negative padding is indicative of a logic error ...\n    if (length($data) > $total_len) {\n\tdie sprintf(\"padBytes error: data (%d) is longer than total_len (%d)\", length($data), $total_len);\n    }\n\n    return $data . ($pad_char x $pad_len);\n}\n\n# Return the next multiple of block_size larger than or equal to $data_len.\nsub paddedSize {\n    my($data_len) = @_;\n\n    use integer;\n    return (($data_len - 1) / $block_size) * $block_size + $block_size;\n}\n\n# Return the number of block_size blocks required to hold $data_len.\nsub numBlocks {\n    my($data_len) = @_;\n\n    use integer;\n    return (($data_len - 1) / $block_size) + 1;\n}\n\n# Pack the name, address, size and optional skip regions of a partition entry into binary form.\nsub createPartitionEntry {\n    my($name, $flash_base, $size, $skips) = @_;\n    my $entry;\n\n    my($zero_long) = 0x0000;\n\n    # Pack the partition entry according to the format that RedBoot (and the MTD partition parsing code) requires.\n    $entry = pack(\"a16N5x212N2\",$name,$flash_base,$zero_long,$size,$zero_long,$zero_long,$zero_long,$zero_long);\n\n    # Optionally put a skip header into the padding area.\n    if (defined $skips) {\n\tmy $i = scalar(@$skips);\n\tforeach my $region (@$skips) {\n\t    substr($entry, -8 - 12*$i, 12) =\n\t\tpack(\"a4N2\", \"skip\", $region->{'offset'}, $region->{'size'});\n\t    $i--;\n\t}\n    }\n\n    return $entry;\n}\n\n# Parse partition entry and return anon array ref [$name, $offset, $size, $skip] or return 0 on partition terminator.\nsub parsePartitionEntry {\n    my($partition_entry) = @_;\n\n    my($entry_len) = 0x100;\n    length($partition_entry) eq $entry_len or die \"parsePartitionEntry: partition entry length is not $entry_len!\\n\";\n\n    # Unpack the partition table entry, saving those values in which we are interested.\n    my($name, $flash_base, $size, $dummy_long, $padding, $skips);\n    ($name, $flash_base, $dummy_long, $size, $dummy_long, $dummy_long, $padding, $dummy_long, $dummy_long) =\n\tunpack(\"a16N5a212N2\",$partition_entry);\n\n    # A partition entry starting with 0xFF terminates the table.\n    if (unpack(\"C\", $name) eq 0xff) {\n\t# %%% FIXME: This should only skip, not terminate. %%%\n\t$debug and print \"Found terminator for <FIS directory>\\n\";\n\treturn 0;\n    }\n\n    # Remove trailing nulls from the partition name.\n    $name =~ s/\\000+//;\n\n    # Extract the skip regions out of the padding area.\n    $padding =~ s/^\\000+//;\n    $padding =~ s/\\000*skip(........)\\000*/$1/g;\n    $padding =~ s/\\000+$//;\n\n    # Store the skip regions in an array for later use.\n    while (length($padding)) {\n\tmy $region = {};\n\t($region->{'offset'}, $region->{'size'}) =\n\t    unpack(\"N2\", $padding);\n\t$debug and printf(\"Found skip region at 0x%05X, size 0x%05X\\n\",\n\t\t\t  $region->{'offset'}, $region->{'size'});\n\tpush(@$skips, $region);\n\t$padding = substr($padding,8);\n    }\n\n    return [$name, $flash_base - $flash_start, $size, $skips];\n}\n\n# Return partition table from data is one exists, otherwise return 0.\nsub findPartitionTable {\n    my($data_buf) = @_;\n\n    unpack(\"a7\", $data_buf) eq 'RedBoot' or return 0;\n    return substr($data_buf, 0, 0x1000)\n}\n\n# Parse partition table and return array of anonymous array references ([$name, $offset, $size, $skips], ...).\nsub parsePartitionTable {\n    my($partition_table) = @_;\n\n    my(@partitions, $fields_ref);\n    my($entry_len) = 0x100;\n    my($partition_count) = 0;\n\n    # Loop through the fixed size partition table entries, and store the entries in @partitions.\n    # %%% FIXME: This doesn't handle the case of a completely full partition table. %%%\n    while ($fields_ref = parsePartitionEntry(substr($partition_table, $partition_count * $entry_len, $entry_len))) {\n\t$debug and printf(\"Found <%s> at 0x%08X (%s)%s\\n\", $fields_ref->[0], $fields_ref->[1],\n\t\t\t  ($fields_ref->[2] >= $block_size ?\n\t\t\t   sprintf(\"%d blocks\", numBlocks($fields_ref->[2])) :\n\t\t\t   sprintf(\"0x%05X bytes\", $fields_ref->[2])),\n\t\t\t  (defined $fields_ref->[3] ?\n\t\t\t   sprintf(\" [%s]\",\n\t\t\t\t   join(\", \",\n\t\t\t\t\tmap { sprintf(\"0x%05X/0x%05X\", $_->{'offset'},$_->{'size'}) }\n\t\t\t\t\t@{$fields_ref->[3]})) :\n\t\t\t   \"\"));\n\t$partitions[$partition_count++] = $fields_ref;\n    }\n    return(@partitions);\n}\n\n# Create an empty jffs2 block.\nsub jffs2Block {\n    return padBytes(pack(\"N3\", 0x19852003, 0x0000000c, 0xf060dc98), $block_size);\n}\n\n# Write out $data to $filename,\nsub writeOut {\n    my($data, $filename) = @_;\n\n    open FILE,\">$filename\" or die \"Can't open file \\\"$filename\\\": $!\\n\";\n\n    if (defined($data)) { print FILE $data;}\n\n    close FILE or die \"Can't close file \\\"$filename\\\": $!\\n\";\n}\n\n# Not used at the moment.\nsub trailerData {\n    my($product_id)       = 0x0001;\n    my($protocol_id)      = 0x0000;\n    my($firmware_version) = 0x2325;\n    my($unknown1)         = 0x90f7;\n    my($magic_number)     = 'eRcOmM';\n    my($unknown2)         = 0x00b9;\n\n    return pack(\"n4a6n\",$product_id,$protocol_id,$firmware_version,$unknown1,$magic_number,$unknown2);\n}\n\n# Print the contents of the Sercomm RedBoot trailer.\nsub printRedbootTrailer {\n    my($redboot_data) = @_;\n\n    my($correct_redboot_len) = 0x40000;\n    my($redboot_data_len) = length($redboot_data);\n\n    if ($redboot_data_len != $correct_redboot_len) {\n\tprintf(\"Redboot length (0x%08X) is not 0x%08X\\n\", $redboot_data_len, $correct_redboot_len);\n\treturn;\n    }\n\n    # The trailer is the last 80 bytes of the redboot partition.\n    my($redboot_trailer) = substr($redboot_data, -80);\n\n    writeOut($redboot_trailer, 'RedbootTrailer');\n\n    my($mac_addr0, $mac_addr1, $mac_addr2, $unknown, $prefix, $ver_ctrl, $down_ctrl, $hid, $hver, $prodid, $prodidmask,\n       $protid, $protidmask, $funcid, $funcidmask, $fver, $cseg, $csize, $postfix) =\n\t   unpack(\"n3Na7n2a32n10a7\",$redboot_trailer);\n\n    printf(\"MAC address is %04X%04X%04X\\n\", $mac_addr0, $mac_addr1, $mac_addr2);\n    printf(\"unknown: %08X\\n\", $unknown);\n    printf(\"%s:%04X:%04X:%s\\n\", $prefix, $ver_ctrl, $down_ctrl, $postfix);\n    printf(\"VerControl: %04X\\nDownControl: %04X\\n\", $ver_ctrl, $down_ctrl);\n    printf(\"hid: %04X %04X %04X %04X %04X %04X %04X %04X %04X %04X %04X %04X %04X %04X %04X %04X\\n\", unpack(\"n16\", $hid));\n    printf(\"Hver: %04X\\nProdID: %04X\\nProtID: %04X\\nFuncID: %04X\\nFver: %04X\\nCseg: %04X\\nCsize: %04X\\n\",\n\t   $hver, $prodid, $protid, $funcid, $fver, $cseg, $csize);\n}\n\n# remove the optional Loader partition\nsub removeOptionalLoader {\n    my($partitions_ref) = @_;\n\n    my $index;\n    my $count = 0;\n    map {\n\tif (not defined $index) {\n\t    if ($_->{'name'} eq \"Loader\") {\n\t\t$index = $count;\n\t    }\n\t    $count++;\n\t}\n    } @$partitions_ref;\n    \n    defined $index or die \"Cannot find the Loader partition\\n\";\n\n    splice(@$partitions_ref, $index, 1);\n\n    # Set fixed offsets and sizes for Kernel and Ramdisk\n    map {\n\tif ($_->{'name'} eq 'Kernel') {\n\t    $_->{'offset'}   = $kernel_offset;\n\t    $_->{'size'}     = $kernel_size;\n\t    $_->{'variable'} = 0;\n\t}\n\tif ($_->{'name'} eq 'Ramdisk') {\n\t    $_->{'offset'}   = $ramdisk_offset;\n\t}\n    } @$partitions_ref;\n\n    return;\n}\n\n\n# populate @partitions based on the firmware's partition table\nsub spliceFirmwarePartitions {\n    my($firmware_buf, $partitions_ref) = @_;\n\n    # we know that partition table, if it exists, begins at start of 'FIS directory' and has max length 0x1000\n    my($partition_table);\n    map {\n\t$_->{'name'} eq 'FIS directory' and\n\t    $partition_table = findPartitionTable(substr($firmware_buf, $_->{'offset'}, $_->{'size'}));\n    } @$partitions_ref;\n\n    # return 0 here if no partition table in FIS directory\n    return if not $partition_table;\n\n    my @new_partitions = parsePartitionTable($partition_table);\n\n    # Remove the optional second stage bootloader if it is not found in the FIS directory.\n    if (not grep { $_->[0] eq 'Loader' } @new_partitions) {\n\tremoveOptionalLoader($partitions_ref);\n    }\n\n    my($partition_count) = 0;\n    my($splice) = 0;\n    map {\n\n\t# Skip pseudo partitions.\n\twhile (($partition_count < scalar(@$partitions_ref)) and\n\t       $partitions_ref->[$partition_count]->{'pseudo'}) {\n\t    $debug and printf(\"Skipped <%s> (pseudo partition)\\n\", $partitions_ref->[$partition_count]->{'name'});\n\t    $partition_count++;\n\t}\n\n\t# If we are in a variable area, and we haven't reached the end of it,\n\t# then splice in another partition for use by the later code.\n\tif ($splice and ($partitions_ref->[$partition_count]->{'name'} ne $_->[0])) {\n\t    $debug and printf(\"Splicing new partition <%s> before <%s>\\n\",\n\t\t\t      $_->[0], $partitions_ref->[$partition_count]->{'name'});\n\t    splice(@{$partitions_ref}, $partition_count, 0, ({'name' => \"\",'variable'=>1,'header'=>0}));\n\t}\n\n\tmy $partition = $partitions_ref->[$partition_count];\n\n\t# Variable partitions can be overridden by the real FIS directory\n\tif ($partition->{'variable'}) {\n\n\t    # Only override the filename if the partition name is not set or doesn't match\n\t    if ($partition->{'name'} ne $_->[0]) {\n\n\t\tif (length($partition->{'name'})) {\n\t\t    $debug and printf(\"Overwriting <%s> with <%s>\\n\",\n\t\t\t\t      $partitions_ref->[$partition_count]->{'name'}, $_->[0]);\n\t\t}\n\n\t\t$partition->{'name'} = $_->[0];\n\t\t$partition->{'file'} = $_->[0];\n\t    }\n\n\t    # Set the offset, size and skips based on the real partition table\n\t    $partition->{'offset'} = $_->[1];\n\t    $partition->{'size'}   = $_->[2];\n\t    $partition->{'skips'}  = $_->[3];\n\n\t    $debug and printf(\"Locating <%s> at 0x%08X (%s)\\n\",\n\t\t\t      $partition->{'name'}, $partition->{'offset'},\n\t\t\t      ($partition->{'size'} >= $block_size ?\n\t\t\t       sprintf(\"%d blocks\", numBlocks($partition->{'size'})) :\n\t\t\t       sprintf(\"0x%05X bytes\", $partition->{'size'})));\n\n\t    $splice = 1;\n\t}\n\n\t# Fixed partitions cannot be overridden\n\telse {\n\t    ($partition->{'name'} eq $_->[0]) or\n\t\tdie \"Unexpected partition <\",$_->[0],\"> (expecting <\",$partition->{'name'},\">)\\n\";\n\n\t    $debug and printf(\"Locating <%s> at 0x%08X (%s)\\n\",\n\t\t\t      $partition->{'name'}, $partition->{'offset'},\n\t\t\t      ($partition->{'size'} >= $block_size ?\n\t\t\t       sprintf(\"%d blocks\", numBlocks($partition->{'size'})) :\n\t\t\t       sprintf(\"0x%05X bytes\", $partition->{'size'})));\n\t    \n\t    $splice = 0;\n\t}\n\t\n\t$partition_count++;\n\n    } @new_partitions;\n\n    return;\n}\n\n# Read in an 8MB firmware file, and store the data into @partitions.\n# Note that the data is only stored in a partition if 'offset' and 'size' are defined,\n# and it does not already have data stored in it.\nsub readInFirmware {\n    my($filename, $partitions_ref) = @_;\n\n    my($firmware_buf);\n\n    open FILE,$filename or die \"Can't find firmware image \\\"$filename\\\": $!\\n\";\n    read FILE,$firmware_buf,$flash_len or die \"Can't read $flash_len bytes from \\\"$filename\\\": $!\\n\";\n    close FILE or die \"Can't close \\\"$filename\\\": $!\\n\";\n\n    $debug and printf(\"Read 0x%08X bytes from \\\"%s\\\"\\n\", length($firmware_buf), $filename);\n\n    spliceFirmwarePartitions($firmware_buf, $partitions_ref);\n\n    # Read the parts of the firmware file into the partitions table.\n    map {\n\tif (defined $_->{'offset'} and defined $_->{'size'}) {\n\n\t    if (defined $_->{'data'}) {\n\t\t$debug and printf(\"Not overwriting data in <%s>\\n\", $_->{'name'});\n\t    }\n\t    else {\n\n\t\t# Slurp up the data, based on whether a header and/or data is present or not\n\t\tif ($_->{'header'}) {\n\n\t\t    # Read the length, and grab the data based on the length.\n\t\t    my($data_len) = unpack(\"N\", substr($firmware_buf, $_->{'offset'}));\n\n\t\t    # A length of 0xFFFFFFFF means that the area is not initialised\n\t\t    if ($data_len != 0xFFFFFFFF) {\n\t\t\t$debug and printf(\"Found header size of 0x%08X bytes for <%s>\\n\", $data_len, $_->{'name'});\n\t\t\t$_->{'data'} = substr($firmware_buf, $_->{'offset'} + $_->{'header'}, $data_len);\n\t\t    }\n\t\t}\n\t\telsif ($_->{'pseudo'} and not defined $_->{'file'} and\n\t\t       (substr($firmware_buf, $_->{'offset'}, $_->{'size'}) eq\n\t\t\t(pack(\"C\", 0xff) x $_->{'size'}))) {\n\t\t    $debug and printf(\"Skipping empty pseudo partition <%s>\\n\", $_->{'name'});\n\t\t}\n\t\telse {\n\n\t\t    # Grab the whole partition, using the maximum size.\n\t\t    $_->{'data'} = substr($firmware_buf, $_->{'offset'}, $_->{'size'});\n\t\t}\n\n\t\t# If skip regions are defined, remove them from the data.\n\t\tif (defined $_->{'skips'}) {\n\t\t    my $removed = 0;\n\t\t    foreach my $region (@{$_->{'skips'}}) {\n\t\t\tif (($region->{'offset'} > 0) or\n\t\t\t    not ($_->{'header'} > 0)) {\n\t\t\t    $debug and printf(\"Removing 0x%05X bytes from offset 0x%05X\\n\",\n\t\t\t\t\t      $region->{'size'}, $region->{'offset'});\n\t\t\t    $region->{'data'} = substr($_->{'data'}, $region->{'offset'} - $removed, $region->{'size'}, '');\n\t\t\t}\n\t\t\t$removed += $region->{'size'};\n\t\t    }\n\t\t}\n\n\t\t$quiet or defined $_->{'data'} and printf(\"Read %s into <%s>\\n\",\n\t\t\t\t\t\t\t  (length($_->{'data'}) >= $block_size ?\n\t\t\t\t\t\t\t   sprintf(\"%d blocks\", numBlocks(length($_->{'data'}))) :\n\t\t\t\t\t\t\t   sprintf(\"0x%05X bytes\", length($_->{'data'}))), $_->{'name'});\n\t    }\n\t}\n    } @$partitions_ref;\n}\n\n# Write the partition data stored in memory out into the files associated with each.\nsub writeOutFirmwareParts {\n    my(@partitions) = @_;\n\n    # Write out the parts of the firmware file.\n    map {\n\n\t# We can only write if 'data' and 'file' are defined.\n\tif (defined $_->{'file'} and defined $_->{'data'} and length($_->{'data'})) {\n\t    writeOut($_->{'data'}, $_->{'file'});\n\t    $quiet or printf(\"Wrote 0x%08X bytes from <%s> into \\\"%s\\\"\\n\",\n\t\t\t      length($_->{'data'}), $_->{'name'}, $_->{'file'});\n\t}\n\telse {\n\t    $debug and printf(\"Skipping <%s> (%s)\\n\", $_->{'name'},\n\t\t\t      (not defined $_->{'file'}) ?\n\t\t\t      \"no filename specified\" :\n\t\t\t      \"no data to write\");\n\t}\n\n    } @partitions;\n\n    return;\n}\n\n# Read in the partition data from the files associated with each and store in memory.\nsub readInFirmwareParts {\n    my(@partitions) = (@_);\n    \n    undef $/; # we want to slurp\n\n    map {\n\n\tmy $file = $_->{'file'};\n\tif (defined $file) {\n\t    open FILE,$file or die \"Can't find firmware part \\\"$file\\\": $!\\n\";\n\n\t    # Slurp in the data\n\t    $_->{'data'} = <FILE>;\n\n\t    # close the file\n\t    close FILE or die \"Can't close file \\\"$file\\\": $!\\n\";\n\n\t    # Optionally byteswap the data\n\t    if ($_->{'byteswap'}) {\n\t\t# Byte swap the data (which has to be padded to a multiple of 4 bytes).\n\t\t$_->{'data'} = pack(\"N*\", unpack(\"V*\", $_->{'data'}.pack(\"CCC\", 0)));\n\t    }\n\n\t    # Keep track of the actual size.\n\t    my $size;\n\n\t    if ($_->{'header'}) {\n\t\tif ($_->{'pseudo'}) {\n\t\t    $size = $_->{'header'} + length($_->{'data'});\n\t\t}\n\t\telse {\n\t\t    $size = paddedSize($_->{'header'} + length($_->{'data'}));\n\t\t}\n\t    }\n\t    elsif (not $_->{'pseudo'}) {\n\t\t$size = paddedSize(length($_->{'data'}));\n\t    }\n\t    else {\n\t\t$size = length($_->{'data'});\n\t    }\n\n\t    # Check to make sure the file contents are not too large.\n\t    if (defined $_->{'size'} and ($size > $_->{'size'})) {\n\t\tdie sprintf(\"Ran out of flash space in <%s> - %s too large.\\n\", $_->{'name'},\n\t\t\t    sprintf(\"0x%05X bytes\", ($size - $_->{'size'})));\n\t    }\n\n\t    # If the partition does not have a fixed size, the calculate the size.\n\t    if (not defined $_->{'size'}) {\n\t\t$_->{'size'} = $size;\n\t    }\n\n\t    # Keep the user appraised ...\n\t    $quiet or printf(\"Read 0x%08X bytes from \\\"%s\\\" into <%s> (%s / %s)%s\\n\",\n\t\t\t     length($_->{'data'}), $_->{'file'}, $_->{'name'},\n\t\t\t     ($size >= $block_size ?\n\t\t\t      sprintf(\"%d blocks\", numBlocks($size)) :\n\t\t\t      sprintf(\"0x%05X bytes\", $size)),\n\t\t\t     ($_->{'size'} >= $block_size ?\n\t\t\t      sprintf(\"%d blocks\", numBlocks($_->{'size'})) :\n\t\t\t      sprintf(\"0x%05X bytes\", $_->{'size'})),\n\t\t\t     ($_->{'byteswap'} ? \" (byte-swapped)\" : \"\"));\n\t}\n\n    } @partitions;\n\n    return;\n}\n\n# layoutPartitions : this function must be ugly - it needs to verify RedBoot, SysConf, Kernel, Ramdisk, and\n#     FIS directory partitions exist, are in the correct order, and do not have more data than can fit in\n#     their lengths (fixed for all but Ramdisk, which has a minimum length of one block).\n#     If Rootdisk and/or Userdisk exist, it must also verify that their block padded lengths are not\n#     too great for the available space.\n# input : an array of hashes, some of which are populated with data\n# output: same reference with start and size (partition not data) also populated. this populated structure\n#         can then be passed to buildPartitionTable() to generate the actual partition table data\nsub layoutPartitions {\n    my(@partitions) = @_;\n\n    # Find the kernel partition, and save a pointer to it for later use\n    my $kernel;\n    map { ($_->{'name'} eq \"Kernel\") && ($kernel = $_); } @partitions;\n    $kernel or die \"Couldn't find the kernel partition\\n\";\n\n    # Find the last variable size partition, and save a pointer to it for later use\n    my $lastdisk;\n    my $directory_offset;\n    my $curdisk = $partitions[0];\n    map {\n\tif (not defined $lastdisk) {\n\t    if ($_->{'name'} eq \"FIS directory\") {\n\t\t$lastdisk = $curdisk;\n\t\t$directory_offset = $_->{'offset'};\n\t    }\n\t    else {\n\t\t$curdisk = $_;\n\t    }\n\t}\n    } @partitions;\n\n    $lastdisk or die \"Couldn't find the last variable size partition\\n\";\n\n    $debug and printf(\"Last variable size partition is <%s>\\n\", $lastdisk->{'name'});\n\n    #\n    # here we go through the $partitions array ref and fill in all the values\n    #\n\n    # This points to where the next partition should be placed.\n    my $pointer = $flash_start;\n\n    map {\n\n\t$debug and printf(\"Pointer is 0x%08X\\n\", $pointer);\n\n\t# Determine the start and offset of the current partition.\n\tif (defined $_->{'offset'}) {\n\t    $_->{'start'} = $flash_start + $_->{'offset'};\n\t    # Check for running past the defined start of the partition.\n\t    if (($pointer > $_->{'start'}) and not $_->{'pseudo'}) {\n\t\tdie sprintf(\"Ran out of flash space before <%s> - %s too large.\\n\", $_->{'name'},\n\t\t\t    sprintf(\"0x%05X bytes\", ($pointer - $_->{'start'})));\n\t    }\n\t}\n\n\t# If offset is not defined, then calculate it.\n\telse {\n\t    $_->{'start'} = $pointer;\n\t    $_->{'offset'} = $_->{'start'} - $flash_start;\n\t}\n\n\tmy $size = defined $_->{'data'} ? length($_->{'data'}) : 0;\n\n\t# Add skip regions for the partitions with headers.\n\tif ($_->{'header'} > 0) {\n\t    # Define the skip region for the initial Sercomm header.\n\t    push(@{$_->{'skips'}},\n\t\t { 'offset' => 0, 'size' => $_->{'header'}, 'data' => undef });\n\t    # Allow for the Sercomm header to be prepended to the data.\n\t    $size += $_->{'header'};\n\n\t    # Determine if the partition overlaps the ramdisk boundary.\n\t    if (($_->{'offset'} < $ramdisk_offset) and\n\t\t(($_->{'offset'} + $size) > $ramdisk_offset)) {\n\t\t# Define the skip region for the inline Sercomm header.\n\t\tpush(@{$_->{'skips'}},\n\t\t     { 'offset' => ($ramdisk_offset - $_->{'offset'}), 'size' => 16,\n\t\t       'data' => pack(\"N4\", $block_size) });\n\t\t# Allow for the Sercomm header to be inserted in the data.\n\t\t$size += 16;\n\t    }\n\t}\n\n\t# Partitions without headers cannot have skip regions.\n\telsif (($_->{'offset'} <= $ramdisk_offset) and\n\t       (($_->{'offset'} + $size) > $ramdisk_offset)) {\n\t    # Pad the kernel until it extends past the ramdisk offset.\n\t    push(@{$kernel->{'skips'}},\n\t\t { 'offset' => ($ramdisk_offset - $kernel->{'offset'}), 'size' => 16,\n\t\t   'data' => pack(\"N4\", $block_size) });\n\t    $kernel->{'size'} = $ramdisk_offset - $kernel->{'offset'} + $block_size;\n\t    $kernel->{'data'} = padBytes($kernel->{'data'},\n\t\t\t\t\t $kernel->{'size'} - $kernel->{'header'} - 16);\n\t    $_->{'offset'} = $ramdisk_offset + $block_size;\n\t    $_->{'start'} = $flash_start + $_->{'offset'};\n\t    $pointer = $_->{'start'};\n\t    $debug and printf(\"Extending kernel partition past ramdisk offset.\\n\");\n\t}\n\n\t# If this is the last variable size partition, then fill the rest of the space.\n\tif ($_->{'name'} eq $lastdisk->{'name'}) {\n\t    $_->{'size'} = paddedSize($directory_offset + $flash_start - $pointer);\n\t    $debug and printf(\"Padding last variable partition <%s> to 0x%08X bytes\\n\", $_->{'name'}, $_->{'size'});\n\t}\n\n\tdie sprintf(\"Partition size not defined in <%s>.\\n\", $_->{'name'})\n\t    unless defined $_->{'size'};\n\n\t# Extend to another block if required.\n\tif ($size > $_->{'size'}) {\n\t    if ($_->{'name'} eq $lastdisk->{'name'}) {\n\t\tdie sprintf(\"Ran out of flash space in <%s> - %s too large.\\n\", $_->{'name'},\n\t\t\t    sprintf(\"0x%05X bytes\", ($size - $_->{'size'})));\n\t    }\n\t    $_->{'size'} = $size;\n\t    printf(\"Extending partition <%s> to 0x%08X bytes\\n\", $_->{'name'}, $_->{'size'});\n\t}\n\n\t# Keep the user appraised ...\n\t$debug and printf(\"Allocated <%s> from 0x%08X to 0x%08X (%s / %s)\\n\",\n\t\t\t  $_->{'name'}, $_->{'start'}, $_->{'start'} + $_->{'size'},\n\t\t\t  ($size >= $block_size ?\n\t\t\t   sprintf(\"%d blocks\", numBlocks($size)) :\n\t\t\t   sprintf(\"0x%05X bytes\", $size)),\n\t\t\t  ($_->{'size'} >= $block_size ?\n\t\t\t   sprintf(\"%d blocks\", numBlocks($_->{'size'})) :\n\t\t\t   sprintf(\"0x%05X bytes\", $_->{'size'})));\n\n\t# Check to make sure we have not run out of room.\n\tif (($_->{'start'} + $_->{'size'}) > ($flash_start + $flash_len)) {\n\t    die \"Ran out of flash space in <\", $_->{'name'}, \">\\n\";\n\t}\n\n\t$debug and printf(\"Moving pointer from 0x%08X to 0x%08X (0x%08X + 0x%08X)\\n\",\n\t\t\t  $pointer, paddedSize($_->{'start'} + $_->{'size'}),\n\t\t\t  $_->{'start'}, $_->{'size'});\n\n\t# Move the pointer up, in preparation for the next partition.\n\t$pointer = paddedSize($_->{'start'} + $_->{'size'});\n\n    } @partitions;\n\n    return;\n}\n\nsub buildPartitionTable {\n    my(@partitions) = @_;\n\n    my($flash_start) = 0x50000000;\n    my($partition_data) = '';\n\n    map {\n\n\t# Collate the partition data for all known partitions.\n\tif (not $_->{'pseudo'} and defined $_->{'offset'} and defined $_->{'size'}) {\n\n\t    # Pack and append the binary table entry for this partition.\n\t    $partition_data .= createPartitionEntry($_->{'name'}, $_->{'offset'} + $flash_start,\n\t\t\t\t\t\t    $_->{'size'}, $_->{'skips'});\n\n\t    # If this is the FIS directory, then write the partition table data into it.\n\t    if ($_->{'name'} eq \"FIS directory\") {\n\t\t# Explicitly terminate the partition data.\n\t\t$partition_data .= pack(\"C\",0xff) x 0x100;\n\t\t$_->{'data'} = padBytes($partition_data, $_->{'size'});\n\t    }\n\n\t    my $size = length($_->{'data'});\n\n\t    # Keep the user appraised ...\n\t    $debug and printf(\"Table entry <%s> from 0x%08X to 0x%08X (%s / %s)%s\\n\",\n\t\t\t      $_->{'name'}, $_->{'start'}, $_->{'start'} + $_->{'size'},\n\t\t\t      ($size >= $block_size ?\n\t\t\t       sprintf(\"%d blocks\", numBlocks($size)) :\n\t\t\t       sprintf(\"0x%05X bytes\", $size)),\n\t\t\t      ($_->{'size'} >= $block_size ?\n\t\t\t       sprintf(\"%d blocks\", numBlocks($_->{'size'})) :\n\t\t\t       sprintf(\"0x%05X bytes\", $_->{'size'})),\n\t\t\t      (defined $_->{'skips'} ?\n\t\t\t       sprintf(\"\\nTable entry <%s> skip %s\", $_->{'name'},\n\t\t\t\t       join(\", \",\n\t\t\t\t\t    map { sprintf(\"0x%08X to 0x%08X\", $_->{'offset'},\n\t\t\t\t\t\t\t  $_->{'offset'} + $_->{'size'} - 1) }\n\t\t\t\t\t    @{$_->{'skips'}})) :\n\t\t\t       \"\")\n\t\t\t      );\n\t}\n\telse {\n\t    $debug and print \"No table entry required for <\", $_->{'name'}, \">\\n\";\n\t}\n\n    } @partitions;\n\n    return;\n}\n\nsub writeOutFirmware {\n    my($filename, @partitions) = @_;\n\n    # Clear the image to start.\n    my $image_buf = \"\";\n\n    map {\n\n\t# We can only write a partition if it has an offset, a size, and some data to write.\n\tif (defined $_->{'offset'} and defined $_->{'size'} and defined $_->{'data'}) {\n\n\t    # Keep track of the end of the image.\n\t    my $end_point = length($image_buf);\n\n\t    # If the next partition is well past the end of the current image, then pad it.\n\t    if ($_->{'offset'} > $end_point) {\n\t\t$image_buf .= padBytes(\"\", $_->{'offset'} - $end_point);\n\t\t$quiet or printf(\"Padded %s before <%s> in \\\"%s\\\"\\n\",\n\t\t\t\t ((length($image_buf) - $end_point) >= $block_size ?\n\t\t\t\t  sprintf(\"%d blocks\", numBlocks(length($image_buf) - $end_point)) :\n\t\t\t\t  sprintf(\"0x%05X bytes\", length($image_buf) - $end_point)),\n\t\t\t\t $_->{'name'}, $filename);\n\t    }\n\n\t    # If the next partition is before the end of the current image, then rewind.\n\t    elsif ($_->{'offset'} < $end_point) {\n\t\t$debug and printf(\"Rewound %s before <%s> in \\\"%s\\\"\\n\",\n\t\t\t\t  (($end_point - $_->{'offset'}) >= $block_size ?\n\t\t\t\t   sprintf(\"%d blocks\", numBlocks($end_point - $_->{'offset'})) :\n\t\t\t\t   sprintf(\"0x%05X bytes\", $end_point - $_->{'offset'})),\n\t\t\t\t  $_->{'name'}, $filename);\n# \t\tif (($end_point - $_->{'offset'}) >= $block_size) {\n# \t\t    die \"Allocation error: rewound a full block or more ...\\n\";\n# \t\t}\n\t    }\n\n\t    # If skip regions are defined, add them to the data.\n\t    if (defined $_->{'skips'}) {\n\t\tmy $added = 0;\n\t\tforeach my $region (@{$_->{'skips'}}) {\n\t\t    if (($region->{'offset'} > 0) or\n\t\t\tnot ($_->{'header'} > 0)) {\n\t\t\t$debug and printf(\"Inserted 0x%05X bytes (at offset 0x%05X) into <%s>\\n\",\n\t\t\t\t\t  $region->{'size'}, $region->{'offset'}, $_->{'name'});\n\t\t\tsubstr($_->{'data'},\n\t\t\t       $region->{'offset'} + $added - $_->{'header'},\n\t\t\t       0, $region->{'data'});\n\t\t\t$added += $region->{'size'};\n\t\t    }\n\t\t}\n\t    }\n\n\t    # Splice the data into the image at the appropriate place, padding as required.\n\t    substr($image_buf, $_->{'offset'}, $_->{'size'},\n\t\t   $_->{'header'} ?\n\t\t   padBytes(pack(\"N4\",length($_->{'data'})).$_->{'data'}, $_->{'size'}) :\n\t\t   padBytes($_->{'data'}, $_->{'size'}));\n\t    \n\t    # Keep the user appraised ...\n\t    $quiet or printf(\"Wrote %s (0x%08X to 0x%08X) from <%s> into \\\"%s\\\"\\n\",\n\t\t\t     ($_->{'size'} >= $block_size ?\n\t\t\t      sprintf(\"%2d blocks\", numBlocks($_->{'size'})) :\n\t\t\t      sprintf(\"0x%05X bytes\", $_->{'size'})),\n\t\t\t     $_->{'offset'}, $_->{'offset'}+$_->{'size'}, $_->{'name'}, $filename);\n\t}\n\n\t# If we are not able to write a partition, then give debug information about why.\n\telse {\n\t    $debug and printf(\"Skipping <%s> (%s)\\n\", $_->{'name'},\n\t\t\t      (not defined $_->{'offset'}) ? \"no offset defined\" :\n\t\t\t      ((not defined $_->{'size'}) ? \"no size defined\" :\n\t\t\t       \"no data available\"));\n\t}\n\n    } @partitions;\n\n    # Write the image to the specified file.\n    writeOut($image_buf, $filename);\n\n    return;\n}\n\n# checkPartitionTable: sanity check partition table - for testing but might evolve into setting @partitions\n#    so that we can write out jffs2 partitions from a read image\n#    currently not nearly paranoid enough\nsub checkPartitionTable {\n    my($data) = @_;\n\n    my($pointer) = 0;\n    my($entry);\n\n    my($name, $flash_base, $size, $done, $dummy_long, $padding);\n    do {\n\t$entry = substr($data, $pointer, 0x100);\n\n\t($name,$flash_base,$dummy_long,$size,$dummy_long,$dummy_long,$padding,$dummy_long,$dummy_long) = unpack(\"a16N5x212N2\",$entry);\n\t$name =~ s/\\0//g;\n\t$debug and printf(\"pointer: %d\\tname: %s%sflash_base: 0x%08X\\tsize: 0x%08X\\n\",\n\t\t\t  $pointer, $name, (\" \" x (16 - length($name))), $flash_base, $size);\n\t$pointer += 0x100;\n\t$debug and printf(\"terminator: 0x%08X\\n\", unpack(\"C\", substr($data, $pointer, 1)));\n\tif (unpack(\"C\", substr($data, $pointer, 1)) eq 0xff) {\n\t    $done = 1;\n\t}\n    } until $done;\n}\n\nsub printPartitions {\n    my(@partitions) = @_;\n\n    my($offset, $size, $skips);\n    map {\n#\tdefined $_->{'size'} ? $size = $_->{'size'} : $size = undef;\n\n\tif (defined  $_->{'size'}) {\n\t    $size = $_->{'size'};\n\t}\n\telse {\n\t    $size = undef;\n\t}\n\tif (defined  $_->{'offset'}) {\n\t    $offset = $_->{'offset'};\n\t}\n\telse {\n\t    $offset = undef;\n\t}\n\tif (defined  $_->{'skips'}) {\n\t    $skips = $_->{'skips'};\n\t}\n\telse {\n\t    $skips = undef;\n\t}\n\tprintf(\"%s%s\", $_->{'name'}, (\" \" x (16 - length($_->{'name'}))));\n\tif (defined $offset) { printf(\"0x%08X\\t\", $offset); } else { printf(\"(undefined)\\t\");   };\n\tif (defined $size)   { printf(\"0x%08X\", $size); } else { printf(\"(undefined)\"); };\n\tif (defined $skips) {\n\t    printf(\"\\t[%s]\",\n\t\t   join(\", \",\n\t\t\tmap { sprintf(\"0x%05X/0x%05X\", $_->{'offset'}, $_->{'size'}); }\n\t\t\t@$skips));\n\t}\n\tprintf(\"\\n\");\n    } @partitions;\n}\n\nsub defaultPartitions {\n\n    return ({'name'=>'RedBoot',          'file'=>'RedBoot',\n\t     'offset'=>0x00000000,        'size'=>0x00040000,\n\t     'variable'=>0, 'header'=>0,  'pseudo'=>0, 'data'=>undef, 'byteswap'=>0},\n\t    {'name'=>'EthAddr',           'file'=>undef,\n\t     'offset'=>0x0003ffb0,        'size'=>0x00000006,\n\t     'variable'=>0, 'header'=>0,  'pseudo'=>1, 'data'=>undef, 'byteswap'=>0},\n\t    {'name'=>'SysConf',           'file'=>'SysConf',\n\t     'offset'=>0x00040000,        'size'=>0x00020000,\n\t     'variable'=>0, 'header'=>0,  'pseudo'=>0, 'data'=>undef, 'byteswap'=>0},\n\t    {'name'=>'Loader',            'file'=>'apex.bin',\n\t     'offset'=>undef,             'size'=>undef,\n\t     'variable'=>1, 'header'=>16, 'pseudo'=>0, 'data'=>undef, 'byteswap'=>0},\n\t    {'name'=>'Kernel',            'file'=>'vmlinuz',\n\t     'offset'=>undef,             'size'=>undef,\n\t     'variable'=>1, 'header'=>16, 'pseudo'=>0, 'data'=>undef, 'byteswap'=>0},\n\t    {'name'=>'Ramdisk',           'file'=>'ramdisk.gz',\n\t     'offset'=>undef,             'size'=>undef,\n\t     'variable'=>1, 'header'=>16, 'pseudo'=>0, 'data'=>undef, 'byteswap'=>0},\n\t    {'name'=>'FIS directory',     'file'=>undef,\n\t     'offset'=>0x007e0000,        'size'=>0x00020000,\n\t     'variable'=>0, 'header'=>0,  'pseudo'=>0, 'data'=>undef, 'byteswap'=>0},\n\t    {'name'=>'Loader config',\t  'file'=>undef,\n\t     'offset'=>0x007f8000,        'size'=>0x00004000,\n\t     'variable'=>0, 'header'=>0,  'pseudo'=>1, 'data'=>undef, 'byteswap'=>0},\n\t    {'name'=>'Microcode',\t  'file'=>'NPE-B',\n\t     'offset'=>0x007fc000,        'size'=>0x00003fe0,\n\t     'variable'=>0, 'header'=>16, 'pseudo'=>1, 'data'=>undef, 'byteswap'=>0},\n\t    {'name'=>'Trailer',           'file'=>'Trailer',\n\t     'offset'=>0x007ffff0,        'size'=>0x00000010,\n\t     'variable'=>0, 'header'=>0,  'pseudo'=>1, 'data'=>undef, 'byteswap'=>0});\n}\n\n# Main routine starts here ...\n\nmy($unpack, $pack, $little, $fatflash, $input, $output, $redboot);\nmy($kernel, $sysconf, $ramdisk, $fisdir);\nmy($microcode, $trailer, $ethaddr, $loader);\n\nEND {\n    # Remove temporary files\n    for my $file (@cleanup) {\n\tunlink $file;\n    }\n}\n\nif (!GetOptions(\"d|debug\"       => \\$debug,\n\t\t\"q|quiet\"       => \\$quiet,\n\t\t\"u|unpack\"      => \\$unpack,\n\t\t\"p|pack\"        => \\$pack,\n\t\t\"l|little\"      => \\$little,\n\t\t\"F|fatflash\"    => \\$fatflash,\n\t\t\"i|input=s\"     => \\$input,\n\t\t\"o|output=s\"    => \\$output,\n\t\t\"b|redboot=s\"   => \\$redboot,\n\t\t\"k|kernel=s\"    => \\$kernel,\n\t\t\"s|sysconf=s\"   => \\$sysconf,\n\t\t\"r|ramdisk=s\"   => \\$ramdisk,\n\t\t\"f|fisdir=s\"    => \\$fisdir,\n\t\t\"m|microcode=s\" => \\$microcode,\n\t\t\"t|trailer=s\"   => \\$trailer,\n\t\t\"e|ethaddr=s\"   => \\$ethaddr,\n\t\t\"L|loader=s\"    => \\$loader,\n\t\t) or (not defined $pack and not defined $unpack)) {\n    print \"Usage: slugimage <options>\\n\";\n    print \"\\n\";\n    print \"  [-d|--debug]\t\t\tTurn on debugging output\\n\";\n    print \"  [-q|--quiet]\t\t\tTurn off status messages\\n\";\n    print \"  [-u|--unpack]\t\t\tUnpack a firmware image\\n\";\n    print \"  [-p|--pack]\t\t\tPack a firmware image\\n\";\n    print \"  [-l|--little]\t\t\tConvert Kernel and Ramdisk to little-endian\\n\";\n    print \"  [-F|--fatflash]\t\t\tGenerate an image for 16MB flash\\n\";\n    print \"  [-i|--input]     <file>\t\tInput firmware image filename\\n\";\n    print \"  [-o|--output]    <file>\t\tOutput firmware image filename\\n\";\n    print \"  [-b|--redboot]   <file>\t\tInput/Output RedBoot filename\\n\";\n    print \"  [-s|--sysconf]   <file>\t\tInput/Output SysConf filename\\n\";\n    print \"  [-L|--loader]    <file>\t\tSecond stage boot loader filename\\n\";\n    print \"  [-k|--kernel]    <file>\t\tInput/Output Kernel filename\\n\";\n    print \"  [-r|--ramdisk]   <file>\t\tInput/Output Ramdisk filename(s)\\n\";\n    print \"  [-f|--fisdir]    <file>\t\tInput/Output FIS directory filename\\n\";\n    print \"  [-m|--microcode] <file>\t\tInput/Output Microcode filename\\n\";\n    print \"  [-t|--trailer]   <file>\t\tInput/Output Trailer filename\\n\";\n    print \"  [-e|--ethaddr]   <AABBCCDDEEFF>\tSet the Ethernet address\\n\";\n\n    # %%% TODO %%% Document --ramdisk syntax\n\n    exit 1;\n}\n\nmy(@partitions) = defaultPartitions();\n\nif ($pack) {\n    die \"Output filename must be specified\\n\" unless defined $output;\n\n    # If we're creating an image and no RedBoot, SysConf partition is\n    # explicitly specified, simply write an empty one as the upgrade tools\n    # don't touch RedBoot and SysConf anyway.  If no Trailer is specified,\n    # put in one.\n    if (not defined $redboot and not -e \"RedBoot\") {\n\t$redboot = tempfile();\n\topen TMP, \">$redboot\" or die \"Cannot open file $redboot: $!\";\n\tpush @cleanup, $redboot;\n\t# The RedBoot partition is 256 * 1024 = 262144; the trailer we add\n\t# is 70 bytes.\n\tprint TMP \"\\0\"x(262144-70);\n\t# Upgrade tools check for an appropriate Sercomm trailer.\n\tfor my $i (@sercomm_redboot_trailer) {\n\t    print TMP pack \"S\", $i;\n\t}\n\tclose TMP;\n    }\n    if (not defined $sysconf and not -e \"SysConf\") {\n\t$sysconf = tempfile();\n\topen TMP, \">$sysconf\" or die \"Cannot open file $sysconf: $!\";\n\tpush @cleanup, $sysconf;\n\t# The SysConf partition is 128 * 1024 = 131072\n\tprint TMP \"\\0\"x131072;\n\tclose TMP;\n    }\n    if (not defined $trailer and not -e \"Trailer\") {\n\t$trailer = tempfile();\n\topen TMP, \">$trailer\" or die \"Cannot open file $trailer: $!\";\n\tpush @cleanup, $trailer;\n\tfor my $i (@sercomm_flash_trailer) {\n\t    print TMP pack \"S\", $i;\n\t}\n\tclose TMP;\n    }\n\n    # If the microcode was not specified, then don't complain that it's missing.\n    if (not defined $microcode and not -e \"NPE-B\") {\n\tmap { ($_->{'name'} eq 'Microcode') && ($_->{'file'} = undef);   } @partitions;\n    }\n}\n\n# Go through the partition options, and set the names and files in @partitions\nif (defined $redboot)   { map { ($_->{'name'} eq 'RedBoot')\t  && ($_->{'file'} = $redboot);   } @partitions; }\nif (defined $sysconf)   { map { ($_->{'name'} eq 'SysConf')\t  && ($_->{'file'} = $sysconf);   } @partitions; }\nif (defined $loader)    { map { ($_->{'name'} eq 'Loader')\t  && ($_->{'file'} = $loader);    } @partitions; }\nif (defined $kernel)    { map { ($_->{'name'} eq 'Kernel')\t  && ($_->{'file'} = $kernel);    } @partitions; }\nif (defined $fisdir)    { map { ($_->{'name'} eq 'FIS directory') && ($_->{'file'} = $fisdir);    } @partitions; }\nif (defined $microcode) { map { ($_->{'name'} eq 'Microcode')\t  && ($_->{'file'} = $microcode); } @partitions; }\nif (defined $trailer)   { map { ($_->{'name'} eq 'Trailer')\t  && ($_->{'file'} = $trailer);   } @partitions; }\n\nif (defined $little)  {\n    map {\n\tif (($_->{'name'} eq 'Loader') or\n\t    ($_->{'name'} eq 'Kernel') or\n\t    ($_->{'name'} eq 'Ramdisk')) {\n\t    $_->{'byteswap'} = 1;\n\t}\n    } @partitions;\n}\n\nif (defined $fatflash)  {\n    $flash_len = 0x01000000;\n    map {\n\tif (($_->{'name'} eq 'FIS directory') or\n\t    ($_->{'name'} eq 'Loader config') or\n\t    ($_->{'name'} eq 'Microcode') or\n\t    ($_->{'name'} eq 'Trailer')) {\n\t    $_->{'offset'} += 0x00800000;\n\t}\n    } @partitions;\n}\n\nif (defined $ethaddr) {\n    map {\n\tif ($_->{'name'} eq 'EthAddr') {\n\t    $ethaddr =~ s/://g;\n\t    if (($ethaddr !~ m/^[0-9A-Fa-f]+$/) or (length($ethaddr) != 12)) {\n\t\tdie \"Invalid ethernet address specification: '\".$ethaddr.\"'\\n\";\n\t    }\n\t    $_->{'data'} = pack(\"H12\", $ethaddr);\n\t}\n    } @partitions;\n}\n\nif (defined $ramdisk) {\n\n    # A single filename is used for the ramdisk filename\n    if ($ramdisk !~ m/[:,]/) {\n\tmap { ($_->{'name'} eq 'Ramdisk') && ($_->{'file'} = $ramdisk); } @partitions;\n    }\n\n    # otherwise, it's a list of name:file mappings\n    else {\n\tmy @mappings = split(',', $ramdisk);\n\n\t# Find the index of the Ramdisk entry\n\tmy $index;\n\tmy $count = 0;\n\tmap {\n\t    if (not defined $index) {\n\t\tif ($_->{'name'} eq \"Ramdisk\") {\n\t\t    $index = $count;\n\t\t}\n\t\t$count++;\n\t    }\n\t} @partitions;\n\n\tdefined $index or die \"Cannot find the Ramdisk partition\\n\";\n\n\t# Replace the Ramdisk entry with the new mappings\n\tsplice(@partitions, $index, 1, map {\n\n\t    # Preserve the information from the ramdisk entry\n\t    my %entry = %{$partitions[$index]};\n\n\t    # Parse the mapping\n\t    ($_ =~ m/^([^:]+):([^:]+)(:([^:]+))?$/) or die \"Invalid syntax in --ramdisk\\n\";\n\t    $entry{'name'} = $1; $entry{'file'} = $2; my $size = $4;\n\n\t    # If the mapping is not for the ramdisk, then undefine its attributes\n\t    if ($entry{'name'} ne 'Ramdisk') {\n\t\t$entry{'offset'} = undef;\n\t\t$entry{'size'} = undef;\n\t\t$entry{'variable'} = 1;\n\t\t$entry{'header'} = 0;\n\t\t$entry{'pseudo'} = 0;\n\t\t$entry{'data'} = undef;\n\t\t$entry{'byteswap'} = 0;\n\t    }\n\n\t    # Support specification of the number of blocks for empty jffs2\n\t    if ($entry{'file'} =~ m/^[0-9]+$/) {\n\t\t$size = $entry{'file'};\n\t\t$entry{'file'} = undef;\n\t    }\n\n\t    # If the user has specified a size, then respect their wishes\n\t    if (defined $size) {\n\t\t$entry{'size'} = $size * $block_size;\n\t\t# Create an empty partition of the requested size.\n\t\t$entry{'data'} = padBytes(\"\", $entry{'size'} - $entry{'header'});\n\t    }\n\n\t    \\%entry;\n\n\t} @mappings);\n    }\n}\n\n# Read in the firmware image\nif ($input) {\n    if ($debug) {\n\tprint \"Initial partition map:\\n\";\n\tprintPartitions(@partitions);\n    }\n    \n    my $result = readInFirmware($input, \\@partitions);\n\n    if ($debug) {\n\tprint \"After reading firmware:\\n\";\n\tprintPartitions(@partitions);\n    }\n}\n\n# Unpack the firmware if requested\nif ($unpack) {\n    die \"Input filename must be specified\\n\" unless defined $input;\n\n#    map {\n#\t($_->{'name'} eq 'FIS directory') and @partitions = checkPartitionTable($_->{'data'});\n#    } @partitions;\n\n    writeOutFirmwareParts(@partitions);\n\n}\n\n# Pack the firmware if requested\nif ($pack) {\n\n    if (!defined $loader) {\n\tremoveOptionalLoader(\\@partitions);\n    }\n\n    if ($debug) {\n\tprint \"Initial partition map:\\n\";\n\tprintPartitions(@partitions);\n    }\n    \n    my $result = readInFirmwareParts(@partitions);\n\n    if ($debug) {\n\tprint \"after readInFirmwareParts():\\n\";\n\tprintPartitions(@partitions);\n# \tmap {\n# \t    ($_->{'name'} eq 'RedBoot') && (printRedbootTrailer($_->{'data'}));\n# \t} @partitions;\n    }\n    \n    layoutPartitions(@partitions);\n\n    if ($debug) {\n \tprint \"after layoutPartitions():\\n\";\n \tprintPartitions(@partitions);\n    }\n    \n    buildPartitionTable(@partitions);\n\n    if ($debug) {\n \tprint \"after buildPartitionTable():\\n\";\n \tprintPartitions(@partitions);\n\n#  \tmy($lastblock);\n#  \tmap {\n#  \t    if ($_->{'name'} eq 'FIS directory') {\n#  \t\t$lastblock = $_->{'data'};\n#  \t    }\n#  \t} @partitions;\n\n#  \tprint \"checkPartitionTable():\\n\";\n#  \tcheckPartitionTable($lastblock);\n    }\n    \n    writeOutFirmware($output, @partitions);\n\n}\n\nexit 0;\n"
  },
  {
    "path": "scripts/spelling.txt",
    "content": "# Originally from Debian's Lintian tool. Various false positives have been\n# removed, and various additions have been made as they've been discovered\n# in the kernel source.\n#\n# License: GPLv2\n#\n# The format of each line is:\n# mistake||correction\n#\nabandonning||abandoning\nabigious||ambiguous\nabitrate||arbitrate\nabnornally||abnormally\nabnrormal||abnormal\nabord||abort\naboslute||absolute\nabov||above\nabreviated||abbreviated\nabsense||absence\nabsolut||absolute\nabsoulte||absolute\nacccess||access\nacceess||access\nacceleratoin||acceleration\naccelleration||acceleration\naccesing||accessing\naccesnt||accent\naccessable||accessible\naccesss||access\naccidentaly||accidentally\naccidentually||accidentally\nacclerated||accelerated\naccoding||according\naccomodate||accommodate\naccomodates||accommodates\naccordign||according\naccoring||according\naccout||account\naccquire||acquire\naccquired||acquired\naccross||across\naccumalate||accumulate\naccumalator||accumulator\nacessable||accessible\nacess||access\nacessing||accessing\nachitecture||architecture\nacient||ancient\nacitions||actions\nacitve||active\nacknowldegement||acknowledgment\nacknowledgement||acknowledgment\nackowledge||acknowledge\nackowledged||acknowledged\nacording||according\nactivete||activate\nactived||activated\nactualy||actually\nacumulating||accumulating\nacumulative||accumulative\nacumulator||accumulator\nacutally||actually\nadapater||adapter\naddional||additional\nadditionaly||additionally\nadditonal||additional\naddres||address\nadddress||address\naddreses||addresses\naddresss||address\naddrress||address\naditional||additional\naditionally||additionally\naditionaly||additionally\nadminstrative||administrative\nadress||address\nadresses||addresses\nadrresses||addresses\nadvertisment||advertisement\nadviced||advised\nafecting||affecting\nagaint||against\nagaist||against\naggreataon||aggregation\naggreation||aggregation\nalbumns||albums\nalegorical||allegorical\nalgined||aligned\nalgorith||algorithm\nalgorithmical||algorithmically\nalgoritm||algorithm\nalgoritms||algorithms\nalgorithmn||algorithm\nalgorrithm||algorithm\nalgorritm||algorithm\naligment||alignment\nalignement||alignment\nallign||align\nalligned||aligned\nalllocate||allocate\nalloated||allocated\nallocatote||allocate\nallocatrd||allocated\nallocte||allocate\nallpication||application\nalocate||allocate\nalogirhtms||algorithms\nalogrithm||algorithm\nalot||a lot\nalow||allow\nalows||allows\nalreay||already\nalredy||already\naltough||although\nalue||value\nambigious||ambiguous\nambigous||ambiguous\namoung||among\namout||amount\namplifer||amplifier\namplifyer||amplifier\nan union||a union\nan user||a user\nan userspace||a userspace\nan one||a one\nanalysator||analyzer\nang||and\nanniversery||anniversary\nannoucement||announcement\nanomolies||anomalies\nanomoly||anomaly\nanway||anyway\naplication||application\nappearence||appearance\napplicaion||application\nappliction||application\napplictions||applications\napplys||applies\nappplications||applications\nappropiate||appropriate\nappropriatly||appropriately\napproriate||appropriate\napproriately||appropriately\napropriate||appropriate\naquainted||acquainted\naquired||acquired\naquisition||acquisition\narbitary||arbitrary\narchitechture||architecture\narguement||argument\narguements||arguments\naritmetic||arithmetic\narne't||aren't\narraival||arrival\nartifical||artificial\nartillary||artillery\nasign||assign\nasser||assert\nassertation||assertion\nassertting||asserting\nassiged||assigned\nassigment||assignment\nassigments||assignments\nassistent||assistant\nassocation||association\nassocicated||associated\nassotiated||associated\nasssert||assert\nassum||assume\nassumtpion||assumption\nasuming||assuming\nasycronous||asynchronous\nasynchnous||asynchronous\nasynchromous||asynchronous\nasymetric||asymmetric\nasymmeric||asymmetric\natomatically||automatically\natomicly||atomically\natempt||attempt\nattachement||attachment\nattatch||attach\nattched||attached\nattemp||attempt\nattemps||attempts\nattemping||attempting\nattepmpt||attempt\nattnetion||attention\nattruibutes||attributes\nauthentification||authentication\nauthenicated||authenticated\nautomaticaly||automatically\nautomaticly||automatically\nautomatize||automate\nautomatized||automated\nautomatizes||automates\nautonymous||autonomous\nauxillary||auxiliary\nauxilliary||auxiliary\navaiable||available\navaible||available\navailabe||available\navailabled||available\navailablity||availability\navailaible||available\navailale||available\navailavility||availability\navailble||available\navailiable||available\navailible||available\navalable||available\navaliable||available\naysnc||async\nbackgroud||background\nbackword||backward\nbackwords||backwards\nbahavior||behavior\nbakup||backup\nbaloon||balloon\nbaloons||balloons\nbandwith||bandwidth\nbanlance||balance\nbatery||battery\nbeacuse||because\nbecasue||because\nbecomming||becoming\nbecuase||because\nbeeing||being\nbefor||before\nbegining||beginning\nbeter||better\nbetweeen||between\nbianries||binaries\nbitmast||bitmask\nboardcast||broadcast\nborad||board\nboundry||boundary\nbrievely||briefly\nbrigde||bridge\nbroadcase||broadcast\nbroadcat||broadcast\nbufer||buffer\nbufufer||buffer\ncacluated||calculated\ncaculate||calculate\ncaculation||calculation\ncadidate||candidate\ncahces||caches\ncalender||calendar\ncalescing||coalescing\ncalle||called\ncallibration||calibration\ncallled||called\ncallser||caller\ncalucate||calculate\ncalulate||calculate\ncancelation||cancellation\ncancle||cancel\ncapabilites||capabilities\ncapabilties||capabilities\ncapabilty||capability\ncapabitilies||capabilities\ncapablity||capability\ncapatibilities||capabilities\ncapapbilities||capabilities\ncaputure||capture\ncarefuly||carefully\ncariage||carriage\ncatagory||category\ncehck||check\nchallange||challenge\nchallanges||challenges\nchache||cache\nchanell||channel\nchangable||changeable\nchanined||chained\nchannle||channel\nchannnel||channel\ncharachter||character\ncharachters||characters\ncharactor||character\ncharater||character\ncharaters||characters\ncharcter||character\nchcek||check\nchck||check\nchecksumed||checksummed\nchecksuming||checksumming\nchildern||children\nchilds||children\nchiled||child\nchked||checked\nchnage||change\nchnages||changes\nchnnel||channel\nchoosen||chosen\nchouse||chose\ncircumvernt||circumvent\nclaread||cleared\nclared||cleared\ncloseing||closing\nclustred||clustered\ncnfiguration||configuration\ncoexistance||coexistence\ncolescing||coalescing\ncollapsable||collapsible\ncolorfull||colorful\ncomand||command\ncomit||commit\ncommerical||commercial\ncomming||coming\ncomminucation||communication\ncommited||committed\ncommiting||committing\ncommitt||commit\ncommoditiy||commodity\ncomsume||consume\ncomsumer||consumer\ncomsuming||consuming\ncompability||compatibility\ncompaibility||compatibility\ncomparsion||comparison\ncompatability||compatibility\ncompatable||compatible\ncompatibililty||compatibility\ncompatibiliy||compatibility\ncompatibilty||compatibility\ncompatiblity||compatibility\ncompetion||completion\ncompilant||compliant\ncompleatly||completely\ncompletition||completion\ncompletly||completely\ncomplient||compliant\ncomponnents||components\ncompoment||component\ncomppatible||compatible\ncompres||compress\ncompresion||compression\ncomression||compression\ncomunication||communication\nconbination||combination\nconditionaly||conditionally\nconditon||condition\ncondtion||condition\nconected||connected\nconector||connector\nconfigration||configuration\nconfiguartion||configuration\nconfiguation||configuration\nconfigued||configured\nconfiguratoin||configuration\nconfiguraton||configuration\nconfigureti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nexplictly||explicitly\nexpresion||expression\nexprimental||experimental\nextened||extended\nextensability||extensibility\nextention||extension\nextenstion||extension\nextracter||extractor\nfaied||failed\nfaield||failed\nfalied||failed\nfaild||failed\nfailded||failed\nfailer||failure\nfaill||fail\nfailied||failed\nfaillure||failure\nfailue||failure\nfailuer||failure\nfailng||failing\nfaireness||fairness\nfalied||failed\nfaliure||failure\nfallbck||fallback\nfamilar||familiar\nfatser||faster\nfeauture||feature\nfeautures||features\nfetaure||feature\nfetaures||features\nfileystem||filesystem\nfimware||firmware\nfirmare||firmware\nfirmaware||firmware\nfirware||firmware\nfinanize||finalize\nfindn||find\nfinilizes||finalizes\nfinsih||finish\nflusing||flushing\nfolloing||following\nfollowign||following\nfollowings||following\nfollwing||following\nfonud||found\nforseeable||foreseeable\nforse||force\nfortan||fortran\nforwardig||forwarding\nframbuffer||framebuffer\nframming||framing\nframwork||framework\nfrequncy||frequency\nfrequancy||frequency\nfrome||from\nfucntion||function\nfuction||function\nfuctions||functions\nfullill||fulfill\nfuncation||function\nfuncion||function\nfunctionallity||functionality\nfunctionaly||functionally\nfunctionnality||functionality\nfunctonality||functionality\nfuntion||function\nfuntions||functions\nfurthur||further\nfuthermore||furthermore\nfutrue||future\ngatable||gateable\ngateing||gating\ngauage||gauge\ngaurenteed||guaranteed\ngeneriously||generously\ngenereate||generate\ngenereted||generated\ngenric||generic\nglobel||global\ngrabing||grabbing\ngrahical||graphical\ngrahpical||graphical\ngrapic||graphic\ngrranted||granted\nguage||gauge\nguarenteed||guaranteed\nguarentee||guarantee\nhalfs||halves\nhander||handler\nhandfull||handful\nhanlde||handle\nhanled||handled\nhappend||happened\nharware||hardware\nhavind||having\nheirarchically||hierarchically\nhelpfull||helpful\nhexdecimal||hexadecimal\nhybernate||hibernate\nhierachy||hierarchy\nhierarchie||hierarchy\nhomogenous||homogeneous\nhowver||however\nhsould||should\nhypervior||hypervisor\nhypter||hyper\nidentidier||identifier\niligal||illegal\nilligal||illegal\nillgal||illegal\niomaped||iomapped\nimblance||imbalance\nimmeadiately||immediately\nimmedaite||immediate\nimmedate||immediate\nimmediatelly||immediately\nimmediatly||immediately\nimmidiate||immediate\nimmutible||immutable\nimpelentation||implementation\nimpementated||implemented\nimplemantation||implementation\nimplemenation||implementation\nimplementaiton||implementation\nimplementated||implemented\nimplemention||implementation\nimplementd||implemented\nimplemetation||implementation\nimplemntation||implementation\nimplentation||implementation\nimplmentation||implementation\nimplmenting||implementing\nincative||inactive\nincomming||incoming\nincompatabilities||incompatibilities\nincompatable||incompatible\nincompatble||incompatible\ninconsistant||inconsistent\nincreas||increase\nincremeted||incremented\nincrment||increment\ninculde||include\nindendation||indentation\nindended||intended\nindependant||independent\nindependantly||independently\nindepended||independent\nindiate||indicate\nindicat||indicate\ninexpect||inexpected\ninferface||interface\ninfomation||information\ninformatiom||information\ninformations||information\ninformtion||information\ninfromation||information\ningore||ignore\ninital||initial\ninitalized||initialized\ninitalised||initialized\ninitalise||initialize\ninitalize||initialize\ninitation||initiation\ninitators||initiators\ninitialiazation||initialization\ninitializationg||initialization\ninitializiation||initialization\ninitialze||initialize\ninitialzed||initialized\ninitialzing||initializing\ninitilization||initialization\ninitilize||initialize\ninitliaze||initialize\ninitilized||initialized\ninofficial||unofficial\ninrerface||interface\ninsititute||institute\ninstace||instance\ninstal||install\ninstanciate||instantiate\ninstanciated||instantiated\ninsufficent||insufficient\ninteface||interface\nintegreated||integrated\nintegrety||integrity\nintegrey||integrity\nintendet||intended\nintented||intended\ninteranl||internal\ninterchangable||interchangeable\ninterferring||interfering\ninterger||integer\nintermittant||intermittent\ninternel||internal\ninteroprability||interoperability\ninteruupt||interrupt\ninterupt||interrupt\ninterupts||interrupts\ninterrface||interface\ninterrrupt||interrupt\ninterrup||interrupt\ninterrups||interrupts\ninterruptted||interrupted\ninterupted||interrupted\ninterupt||interrupt\nintial||initial\nintialisation||initialisation\nintialised||initialised\nintialise||initialise\nintialization||initialization\nintialized||initialized\nintialize||initialize\nintregral||integral\nintrerrupt||interrupt\nintrrupt||interrupt\nintterrupt||interrupt\nintuative||intuitive\ninavlid||invalid\ninvaid||invalid\ninvaild||invalid\ninvailid||invalid\ninvald||invalid\ninvalde||invalid\ninvalide||invalid\ninvalidiate||invalidate\ninvalud||invalid\ninvididual||individual\ninvokation||invocation\ninvokations||invocations\nireelevant||irrelevant\nirrelevent||irrelevant\nisnt||isn't\nisssue||issue\nissus||issues\niteraions||iterations\niternations||iterations\nitertation||iteration\nitslef||itself\njave||java\njeffies||jiffies\njumpimng||jumping\njuse||just\njus||just\nkown||known\nlangage||language\nlangauage||language\nlangauge||language\nlangugage||language\nlauch||launch\nlayed||laid\nlegnth||length\nleightweight||lightweight\nlengh||length\nlenght||length\nlenth||length\nlesstiff||lesstif\nlibaries||libraries\nlibary||library\nlibrairies||libraries\nlibraris||libraries\nlicenceing||licencing\nlimted||limited\nlogaritmic||logarithmic\nloggging||logging\nloggin||login\nlogile||logfile\nloobpack||loopback\nloosing||losing\nlosted||lost\nmaangement||management\nmachinary||machinery\nmaibox||mailbox\nmaintainance||maintenance\nmaintainence||maintenance\nmaintan||maintain\nmakeing||making\nmailformed||malformed\nmalplaced||misplaced\nmalplace||misplace\nmanagable||manageable\nmanagment||management\nmangement||management\nmanoeuvering||maneuvering\nmanufaucturing||manufacturing\nmappping||mapping\nmatchs||matches\nmathimatical||mathematical\nmathimatic||mathematic\nmathimatics||mathematics\nmaximium||maximum\nmaxium||maximum\nmechamism||mechanism\nmeetign||meeting\nmemeory||memory\nmemmber||member\nmemoery||memory\nment||meant\nmergable||mergeable\nmesage||message\nmessags||messages\nmessgaes||messages\nmesssage||message\nmesssages||messages\nmetdata||metadata\nmicropone||microphone\nmicroprocesspr||microprocessor\nmigrateable||migratable\nmilliseonds||milliseconds\nminium||minimum\nminimam||minimum\nminiumum||minimum\nminumum||minimum\nmisalinged||misaligned\nmiscelleneous||miscellaneous\nmisformed||malformed\nmispelled||misspelled\nmispelt||misspelt\nmising||missing\nmismactch||mismatch\nmissign||missing\nmissmanaged||mismanaged\nmissmatch||mismatch\nmisssing||missing\nmiximum||maximum\nmmnemonic||mnemonic\nmnay||many\nmodfiy||modify\nmodulues||modules\nmomery||memory\nmemomry||memory\nmonitring||monitoring\nmonochorome||monochrome\nmonochromo||monochrome\nmonocrome||monochrome\nmopdule||module\nmroe||more\nmulitplied||multiplied\nmultidimensionnal||multidimensional\nmultipe||multiple\nmultple||multiple\nmumber||number\nmuticast||multicast\nmutilcast||multicast\nmutiple||multiple\nmutli||multi\nnams||names\nnavagating||navigating\nnead||need\nneccecary||necessary\nneccesary||necessary\nneccessary||necessary\nnecesary||necessary\nneded||needed\nnegaive||negative\nnegoitation||negotiation\nnegotation||negotiation\nnerver||never\nnescessary||necessary\nnessessary||necessary\nnoticable||noticeable\nnotication||notification\nnotications||notifications\nnotifcations||notifications\nnotifed||notified\nnotity||notify\nnumebr||number\nnumner||number\nobtaion||obtain\nobusing||abusing\noccassionally||occasionally\noccationally||occasionally\noccurance||occurrence\noccurances||occurrences\noccured||occurred\noccurence||occurrence\noccure||occurred\noccured||occurred\noccuring||occurring\noffser||offset\noffet||offset\nofflaod||offload\noffloded||offloaded\noffseting||offsetting\nomited||omitted\nomiting||omitting\nomitt||omit\nommiting||omitting\nommitted||omitted\nonself||oneself\nony||only\noperatione||operation\nopertaions||operations\noptionnal||optional\noptmizations||optimizations\norientatied||orientated\norientied||oriented\norignal||original\noriginial||original\notherise||otherwise\nouput||output\noustanding||outstanding\noveraall||overall\noverhread||overhead\noverlaping||overlapping\noveride||override\noverrided||overridden\noverriden||overridden\noverun||overrun\noverwritting||overwriting\noverwriten||overwritten\npacakge||package\npachage||package\npackacge||package\npackege||package\npackge||package\npacktes||packets\npakage||package\npaket||packet\npallette||palette\npaln||plan\nparamameters||parameters\nparamaters||parameters\nparamater||parameter\nparametes||parameters\nparametised||parametrised\nparamter||parameter\nparamters||parameters\nparmaters||parameters\nparticuarly||particularly\nparticularily||particularly\npartion||partition\npartions||partitions\npartiton||partition\npased||passed\npassin||passing\npathes||paths\npattrns||patterns\npecularities||peculiarities\npeformance||performance\npeforming||performing\npeice||piece\npendantic||pedantic\npeprocessor||preprocessor\nperfoming||performing\nperfomring||performing\nperiperal||peripheral\nperipherial||peripheral\npermissons||permissions\nperoid||period\npersistance||persistence\npersistant||persistent\nphoneticly||phonetically\nplalform||platform\nplatfoem||platform\nplatfrom||platform\nplattform||platform\npleaes||please\nploting||plotting\nplugable||pluggable\npoinnter||pointer\npointeur||pointer\npoiter||pointer\nposible||possible\npositon||position\npossibilites||possibilities\npotocol||protocol\npowerfull||powerful\npramater||parameter\npreamle||preamble\npreample||preamble\npreapre||prepare\npreceeded||preceded\npreceeding||preceding\npreceed||precede\nprecendence||precedence\nprecission||precision\npreemptable||preemptible\nprefered||preferred\nprefferably||preferably\npremption||preemption\nprepaired||prepared\npreperation||preparation\npreprare||prepare\npressre||pressure\nprimative||primitive\nprincliple||principle\npriorty||priority\nprivilaged||privileged\nprivilage||privilege\npriviledge||privilege\npriviledges||privileges\nprobaly||probably\nprocceed||proceed\nproccesors||processors\nprocesed||processed\nproces||process\nprocesing||processing\nprocessessing||processing\nprocessess||processes\nprocesspr||processor\nprocesssed||processed\nprocesssing||processing\nprocteted||protected\nprodecure||procedure\nprogamming||programming\nprogams||programs\nprogess||progress\nprogramers||programmers\nprogramm||program\nprogramms||programs\nprogresss||progress\nprohibitted||prohibited\nprohibitting||prohibiting\npromiscous||promiscuous\npromps||prompts\npronnounced||pronounced\nprononciation||pronunciation\npronouce||pronounce\npronunce||pronounce\npropery||property\npropigate||propagate\npropigation||propagation\npropogate||propagate\nprosess||process\nprotable||portable\nprotcol||protocol\nprotecion||protection\nprotedcted||protected\nprotocoll||protocol\npromixity||proximity\npsudo||pseudo\npsuedo||pseudo\npsychadelic||psychedelic\npwoer||power\nqueing||queuing\nquering||querying\nqueus||queues\nrandomally||randomly\nraoming||roaming\nreasearcher||researcher\nreasearchers||researchers\nreasearch||research\nreceieve||receive\nrecepient||recipient\nrecevied||received\nreceving||receiving\nrecieved||received\nrecieve||receive\nreciever||receiver\nrecieves||receives\nrecogniced||recognised\nrecognizeable||recognizable\nrecommanded||recommended\nrecyle||recycle\nredircet||redirect\nredirectrion||redirection\nredundacy||redundancy\nreename||rename\nrefcounf||refcount\nrefence||reference\nrefered||referred\nreferenace||reference\nrefering||referring\nrefernces||references\nrefernnce||reference\nrefrence||reference\nregisted||registered\nregisterd||registered\nregisteration||registration\nregisteresd||registered\nregisterred||registered\nregistes||registers\nregistraration||registration\nregsiter||register\nregster||register\nregualar||regular\nreguator||regulator\nregulamentations||regulations\nreigstration||registration\nreleated||related\nrelevent||relevant\nreloade||reload\nremoote||remote\nremore||remote\nremoveable||removable\nrepectively||respectively\nreplacable||replaceable\nreplacments||replacements\nreplys||replies\nreponse||response\nrepresentaion||representation\nreqeust||request\nreqister||register\nrequestied||requested\nrequiere||require\nrequirment||requirement\nrequred||required\nrequried||required\nrequst||request\nrequsted||requested\nreregisteration||reregistration\nreseting||resetting\nreseved||reserved\nreseverd||reserved\nresizeable||resizable\nresouce||resource\nresouces||resources\nresoures||resources\nresponce||response\nresrouce||resource\nressizes||resizes\nressource||resource\nressources||resources\nrestesting||retesting\nresumbmitting||resubmitting\nretransmited||retransmitted\nretreived||retrieved\nretreive||retrieve\nretreiving||retrieving\nretrive||retrieve\nretrived||retrieved\nretrun||return\nretun||return\nretuned||returned\nreudce||reduce\nreuest||request\nreuqest||request\nreutnred||returned\nrevsion||revision\nrmeoved||removed\nrmeove||remove\nrmeoves||removes\nrountine||routine\nroutins||routines\nrquest||request\nruning||running\nrunned||ran\nrunnning||running\nruntine||runtime\nsacrifying||sacrificing\nsafly||safely\nsafty||safety\nsavable||saveable\nscaleing||scaling\nscaned||scanned\nscaning||scanning\nscarch||search\nschdule||schedule\nseach||search\nsearchs||searches\nsecquence||sequence\nsecund||second\nsegement||segment\nsemaphone||semaphore\nsenario||scenario\nsenarios||scenarios\nsentivite||sensitive\nseparatly||separately\nsepcify||specify\nseperated||separated\nseperately||separately\nseperate||separate\nseperatly||separately\nseperator||separator\nsepperate||separate\nseqeunce||sequence\nseqeuncer||sequencer\nseqeuencer||sequencer\nsequece||sequence\nsequencial||sequential\nserivce||service\nserveral||several\nservive||service\nsetts||sets\nsettting||setting\nshapshot||snapshot\nshotdown||shutdown\nshoud||should\nshouldnt||shouldn't\nshoule||should\nshrinked||shrunk\nsiginificantly||significantly\nsignabl||signal\nsignificanly||significantly\nsimilary||similarly\nsimiliar||similar\nsimlar||similar\nsimliar||similar\nsimpified||simplified\nsingaled||signaled\nsingal||signal\nsinged||signed\nsleeped||slept\nsliped||slipped\nsoftwares||software\nspeach||speech\nspecfic||specific\nspecfield||specified\nspeciefied||specified\nspecifc||specific\nspecifed||specified\nspecificatin||specification\nspecificaton||specification\nspecifing||specifying\nspecifiying||specifying\nspeficied||specified\nspeicify||specify\nspeling||spelling\nspinlcok||spinlock\nspinock||spinlock\nsplitted||split\nspreaded||spread\nspurrious||spurious\nsructure||structure\nstablilization||stabilization\nstaically||statically\nstaion||station\nstandardss||standards\nstandartization||standardization\nstandart||standard\nstandy||standby\nstardard||standard\nstaticly||statically\nstatuss||status\nstoped||stopped\nstoping||stopping\nstoppped||stopped\nstraming||streaming\nstruc||struct\nstructres||structures\nstuct||struct\nstrucuture||structure\nstucture||structure\nsturcture||structure\nsubdirectoires||subdirectories\nsuble||subtle\nsubstract||subtract\nsubmition||submission\nsuceed||succeed\nsuccesfully||successfully\nsuccesful||successful\nsuccessed||succeeded\nsuccessfull||successful\nsuccessfuly||successfully\nsucessfully||successfully\nsucess||success\nsuperflous||superfluous\nsuperseeded||superseded\nsuplied||supplied\nsuported||supported\nsuport||support\nsupportet||supported\nsuppored||supported\nsupportin||supporting\nsuppoted||supported\nsuppported||supported\nsuppport||support\nsupress||suppress\nsurpressed||suppressed\nsurpresses||suppresses\nsusbsystem||subsystem\nsuspeneded||suspended\nsuspsend||suspend\nsuspicously||suspiciously\nswaping||swapping\nswitchs||switches\nswith||switch\nswithable||switchable\nswithc||switch\nswithced||switched\nswithcing||switching\nswithed||switched\nswithing||switching\nswtich||switch\nsyfs||sysfs\nsymetric||symmetric\nsynax||syntax\nsynchonized||synchronized\nsynchronuously||synchronously\nsyncronize||synchronize\nsyncronized||synchronized\nsyncronizing||synchronizing\nsyncronus||synchronous\nsyste||system\nsytem||system\nsythesis||synthesis\ntaht||that\ntansmit||transmit\ntargetted||targeted\ntargetting||targeting\ntaskelt||tasklet\nteh||the\ntemorary||temporary\ntemproarily||temporarily\ntemperture||temperature\nthead||thread\ntherfore||therefore\nthier||their\nthreds||threads\nthreee||three\nthreshhold||threshold\nthresold||threshold\nthrought||through\ntrackling||tracking\ntroughput||throughput\nthses||these\ntiggers||triggers\ntiggered||triggered\ntipically||typically\ntimeing||timing\ntimout||timeout\ntmis||this\ntoogle||toggle\ntorerable||tolerable\ntraking||tracking\ntramsmitted||transmitted\ntramsmit||transmit\ntranasction||transaction\ntranfer||transfer\ntranscevier||transceiver\ntransciever||transceiver\ntransferd||transferred\ntransfered||transferred\ntransfering||transferring\ntransision||transition\ntransmittd||transmitted\ntransormed||transformed\ntrasfer||transfer\ntrasmission||transmission\ntreshold||threshold\ntrigerred||triggered\ntrigerring||triggering\ntrun||turn\ntunning||tuning\nture||true\ntyep||type\nudpate||update\nuesd||used\nuknown||unknown\nusccess||success\nusupported||unsupported\nuncommited||uncommitted\nunconditionaly||unconditionally\nundeflow||underflow\nunderun||underrun\nunecessary||unnecessary\nunexecpted||unexpected\nunexepected||unexpected\nunexpcted||unexpected\nunexpectd||unexpected\nunexpeted||unexpected\nunexpexted||unexpected\nunfortunatelly||unfortunately\nunifiy||unify\nuniterrupted||uninterrupted\nunintialized||uninitialized\nunitialized||uninitialized\nunkmown||unknown\nunknonw||unknown\nunknow||unknown\nunkown||unknown\nunamed||unnamed\nuneeded||unneeded\nunneded||unneeded\nunneccecary||unnecessary\nunneccesary||unnecessary\nunneccessary||unnecessary\nunnecesary||unnecessary\nunneedingly||unnecessarily\nunnsupported||unsupported\nunmached||unmatched\nunregester||unregister\nunresgister||unregister\nunrgesiter||unregister\nunsinged||unsigned\nunstabel||unstable\nunsolicitied||unsolicited\nunsuccessfull||unsuccessful\nunsuported||unsupported\nuntill||until\nunuseful||useless\nunvalid||invalid\nupate||update\nupsupported||unsupported\nusefule||useful\nusefull||useful\nusege||usage\nusera||users\nusualy||usually\nusupported||unsupported\nutilites||utilities\nutillities||utilities\nutilties||utilities\nutiltity||utility\nutitity||utility\nutitlty||utility\nvaid||valid\nvaild||valid\nvalide||valid\nvariantions||variations\nvarible||variable\nvarient||variant\nvaule||value\nverbse||verbose\nveify||verify\nverisons||versions\nverison||version\nverson||version\nvicefersa||vice-versa\nvirtal||virtual\nvirtaul||virtual\nvirtiual||virtual\nvisiters||visitors\nvitual||virtual\nvunerable||vulnerable\nwakeus||wakeups\nwathdog||watchdog\nwating||waiting\nwiat||wait\nwether||whether\nwhataver||whatever\nwhcih||which\nwhenver||whenever\nwheter||whether\nwhe||when\nwierd||weird\nwiil||will\nwirte||write\nwithing||within\nwnat||want\nworkarould||workaround\nwriteing||writing\nwritting||writing\nwtih||with\nzombe||zombie\nzomebie||zombie\n"
  },
  {
    "path": "scripts/srecimage.pl",
    "content": "#!/usr/bin/env perl\n#\n# srecimage.pl - script to convert a binary image into srec\n# Copyright (c) 2015 - Jo-Philipp Wich <jo@mein.io>\n#\n# This script is in the public domain.\n\nuse strict;\n\nmy ($input, $output, $offset) = @ARGV;\n\nif (!defined($input) || !-f $input || !defined($output) ||\n    !defined($offset) || $offset !~ /^(0x)?[a-fA-F0-9]+$/) {\n\tdie \"Usage: $0 <input file> <output file> <load address>\\n\";\n}\n\nsub srec\n{\n\tmy ($type, $addr, $data, $len) = @_;\n\tmy @addrtypes = qw(%04X %04X %06X %08X %08X %04X %06X %08X %06X %04X);\n\tmy $addrstr = sprintf $addrtypes[$type], $addr;\n\n\t$len = length($data) if ($len <= 0);\n\t$len += 1 + (length($addrstr) / 2);\n\n\tmy $sum = $len;\n\n\tforeach my $byte (unpack('C*', pack('H*', $addrstr)), unpack('C*', $data))\n\t{\n\t\t$sum += $byte;\n\t}\n\n\treturn sprintf \"S%d%02X%s%s%02X\\r\\n\",\n\t       $type, $len, $addrstr, uc(unpack('H*', $data)), ~($sum & 0xFF) & 0xFF;\n}\n\n\nopen(IN, '<:raw', $input) || die \"Unable to open $input: $!\\n\";\nopen(OUT, '>:raw', $output) || die \"Unable to open $output: $!\\n\";\n\nmy ($basename) = $output =~ m!([^/]+)$!;\n\nprint OUT srec(0, 0, $basename, 0);\n\nmy $off = hex($offset);\nmy $len;\n\nwhile (defined($len = read(IN, my $buf, 16)) && $len > 0)\n{\n\tprint OUT srec(3, $off, $buf, $len);\n\t$off += $len;\n}\n\nprint OUT srec(7, hex($offset), \"\", 0);\n\nclose OUT;\nclose IN;\n"
  },
  {
    "path": "scripts/strip-kmod.sh",
    "content": "#!/bin/sh\n[ -n \"$CROSS\" ] || {\n\techo \"The variable CROSS must be set to point to the cross-compiler prefix\"\n\texit 1\n}\n\nMODULE=\"$1\"\n\n[ \"$#\" -ne 1 ] && {\n\techo \"Usage: $0 <module>\"\n\texit 1\n}\n\nARGS=\nif [ -n \"$KEEP_SYMBOLS\" ]; then\n\tARGS=\"-X --strip-debug\"\nelse\n\tARGS=\"-x -G __this_module --strip-unneeded\"\nfi\n\nif [ -z \"$KEEP_BUILD_ID\" ]; then\n\tARGS=\"$ARGS -R .note.gnu.build-id\"\nfi\n\n${CROSS}objcopy \\\n\t-R .comment \\\n\t-R .pdr \\\n\t-R .mdebug.abi32 \\\n\t-R .gnu.attributes \\\n\t-R .reginfo \\\n\t-R .MIPS.abiflags \\\n\t-R .note.GNU-stack \\\n\t$ARGS \\\n\t\"$MODULE\" \"$MODULE.tmp\"\n\n[ -n \"$NO_RENAME\" ] && {\n\tmv \"${MODULE}.tmp\" \"$MODULE\"\n\texit 0\n}\n\n${CROSS}nm \"$MODULE.tmp\" | awk '\nBEGIN {\n\tn = 0\n}\n\n$3 && $2 ~ /[brtd]/ && $3 !~ /\\$LC/ && !def[$3] {\n\tprint \"--redefine-sym \"$3\"=_\"n;\n\tn = n + 1\n\tdef[$3] = 1\n}\n' > \"$MODULE.tmp1\"\n\n${CROSS}objcopy $(cat ${MODULE}.tmp1) ${MODULE}.tmp ${MODULE}.out\nmv \"${MODULE}.out\" \"${MODULE}\"\nrm -f \"${MODULE}\".t*\n"
  },
  {
    "path": "scripts/symlink-tree.sh",
    "content": "#!/bin/sh\n# Create a new openwrt tree with symlinks pointing at the current tree\n# Usage: ./scripts/symlink-tree.sh <destination>\n\nFILES=\"\n\tBSDmakefile\n\tconfig\n\tConfig.in\n\tLICENSE\n\tMakefile\n\tREADME\n\tdl\n\tfeeds.conf.default\n\tinclude\n\tpackage\n\trules.mk\n\tscripts\n\ttarget\n\ttoolchain\n\ttools\"\n\nOPTIONAL_FILES=\"\n\t.git\"\n\nif [ -f feeds.conf ] ; then\n\tFILES=\"$FILES feeds.conf\"\nfi\n\nif [ -z \"$1\" ]; then\n\techo \"Syntax: $0 <destination>\" >&2\n\texit 1\nfi\n\nif [ -e \"$1\" ]; then\n\techo \"Error: $1 already exists\" >&2\n\texit 1\nfi\n\nset -e # fail if any commands fails\nmkdir -p dl \"$1\"\nfor file in $FILES; do\n\t[ -e \"$PWD/$file\" ] || {\n\t\techo \"ERROR: $file does not exist in the current tree\" >&2\n\t\texit 1\n\t}\n\tln -s \"$PWD/$file\" \"$1/\"\ndone\nfor file in $OPTIONAL_FILES; do\n\t[ -e \"$PWD/$file\" ] && ln -s \"$PWD/$file\" \"$1/\"\ndone\nexit 0\n"
  },
  {
    "path": "scripts/sysupgrade-tar.sh",
    "content": "#!/bin/sh\n\n. $TOPDIR/scripts/functions.sh\n\nboard=\"\"\nkernel=\"\"\nrootfs=\"\"\noutfile=\"\"\nerr=\"\"\n\nwhile [ \"$1\" ]; do\n\tcase \"$1\" in\n\t\"--board\")\n\t\tboard=\"$2\"\n\t\tshift\n\t\tshift\n\t\tcontinue\n\t\t;;\n\t\"--kernel\")\n\t\tkernel=\"$2\"\n\t\tshift\n\t\tshift\n\t\tcontinue\n\t\t;;\n\t\"--rootfs\")\n\t\trootfs=\"$2\"\n\t\tshift\n\t\tshift\n\t\tcontinue\n\t\t;;\n\t*)\n\t\tif [ ! \"$outfile\" ]; then\n\t\t\toutfile=$1\n\t\t\tshift\n\t\t\tcontinue\n\t\tfi\n\t\t;;\n\tesac\ndone\n\nif [ ! -n \"$board\" -o ! -r \"$kernel\" -a  ! -r \"$rootfs\" -o ! \"$outfile\" ]; then\n\techo \"syntax: $0 [--board boardname] [--kernel kernelimage] [--rootfs rootfs] out\"\n\texit 1\nfi\n\ntmpdir=\"$( mktemp -d 2> /dev/null )\"\nif [ -z \"$tmpdir\" ]; then\n\t# try OSX signature\n\ttmpdir=\"$( mktemp -t 'ubitmp' -d )\"\nfi\n\nif [ -z \"$tmpdir\" ]; then\n\texit 1\nfi\n\nmkdir -p \"${tmpdir}/sysupgrade-${board}\"\necho \"BOARD=${board}\" > \"${tmpdir}/sysupgrade-${board}/CONTROL\"\nif [ -n \"${rootfs}\" ]; then\n\tcase \"$( get_fs_type ${rootfs} )\" in\n\t\"squashfs\")\n\t\tdd if=\"${rootfs}\" of=\"${tmpdir}/sysupgrade-${board}/root\" bs=1024 conv=sync\n\t\t;;\n\t*)\n\t\tcp \"${rootfs}\" \"${tmpdir}/sysupgrade-${board}/root\"\n\t\t;;\n\tesac\nfi\n[ -z \"${kernel}\" ] || cp \"${kernel}\" \"${tmpdir}/sysupgrade-${board}/kernel\"\n\nmtime=\"\"\nif [ -n \"$SOURCE_DATE_EPOCH\" ]; then\n\tmtime=\"--mtime=@${SOURCE_DATE_EPOCH}\"\nfi\n\n(cd \"$tmpdir\"; tar --sort=name --owner=0 --group=0 --numeric-owner -cvf sysupgrade.tar sysupgrade-${board} ${mtime})\nerr=\"$?\"\nif [ -e \"$tmpdir/sysupgrade.tar\" ]; then\n\tcp \"$tmpdir/sysupgrade.tar\" \"$outfile\"\nelse\n\terr=2\nfi\nrm -rf \"$tmpdir\"\n\nexit $err\n"
  },
  {
    "path": "scripts/target-metadata.pl",
    "content": "#!/usr/bin/env perl\nuse FindBin;\nuse lib \"$FindBin::Bin\";\nuse strict;\nuse metadata;\nuse Getopt::Long;\n\nsub target_config_features(@) {\n\tmy $ret;\n\n\twhile ($_ = shift @_) {\n\t\t/^arm_v(\\w+)$/ and $ret .= \"\\tselect arm_v$1\\n\";\n\t\t/^audio$/ and $ret .= \"\\tselect AUDIO_SUPPORT\\n\";\n\t\t/^boot-part$/ and $ret .= \"\\tselect USES_BOOT_PART\\n\";\n\t\t/^broken$/ and $ret .= \"\\tdepends on BROKEN\\n\";\n\t\t/^cpiogz$/ and $ret .= \"\\tselect USES_CPIOGZ\\n\";\n\t\t/^display$/ and $ret .= \"\\tselect DISPLAY_SUPPORT\\n\";\n\t\t/^dt$/ and $ret .= \"\\tselect USES_DEVICETREE\\n\";\n\t\t/^dt-overlay$/ and $ret .= \"\\tselect HAS_DT_OVERLAY_SUPPORT\\n\";\n\t\t/^emmc$/ and $ret .= \"\\tselect EMMC_SUPPORT\\n\";\n\t\t/^ext4$/ and $ret .= \"\\tselect USES_EXT4\\n\";\n\t\t/^fpu$/ and $ret .= \"\\tselect HAS_FPU\\n\";\n\t\t/^gpio$/ and $ret .= \"\\tselect GPIO_SUPPORT\\n\";\n\t\t/^jffs2$/ and $ret .= \"\\tselect USES_JFFS2\\n\";\n\t\t/^jffs2_nand$/ and $ret .= \"\\tselect USES_JFFS2_NAND\\n\";\n\t\t/^legacy-sdcard$/ and $ret .= \"\\tselect LEGACY_SDCARD_SUPPORT\\n\";\n\t\t/^low_mem$/ and $ret .= \"\\tselect LOW_MEMORY_FOOTPRINT\\n\";\n\t\t/^minor$/ and $ret .= \"\\tselect USES_MINOR\\n\";\n\t\t/^mips16$/ and $ret .= \"\\tselect HAS_MIPS16\\n\";\n\t\t/^nand$/ and $ret .= \"\\tselect NAND_SUPPORT\\n\";\n\t\t/^nommu$/ and $ret .= \"\\tselect NOMMU\\n\";\n\t\t/^pci$/ and $ret .= \"\\tselect PCI_SUPPORT\\n\";\n\t\t/^pcie$/ and $ret .= \"\\tselect PCIE_SUPPORT\\n\";\n\t\t/^pcmcia$/ and $ret .= \"\\tselect PCMCIA_SUPPORT\\n\";\n\t\t/^powerpc64$/ and $ret .= \"\\tselect powerpc64\\n\";\n\t\t/^pwm$/ and $ret .= \"\\select PWM_SUPPORT\\n\";\n\t\t/^ramdisk$/ and $ret .= \"\\tselect USES_INITRAMFS\\n\";\n\t\t/^rfkill$/ and $ret .= \"\\tselect RFKILL_SUPPORT\\n\";\n\t\t/^rootfs-part$/ and $ret .= \"\\tselect USES_ROOTFS_PART\\n\";\n\t\t/^rtc$/ and $ret .= \"\\tselect RTC_SUPPORT\\n\";\n\t\t/^separate_ramdisk$/ and $ret .= \"\\tselect USES_INITRAMFS\\n\\tselect USES_SEPARATE_INITRAMFS\\n\";\n\t\t/^small_flash$/ and $ret .= \"\\tselect SMALL_FLASH\\n\";\n\t\t/^spe_fpu$/ and $ret .= \"\\tselect HAS_SPE_FPU\\n\";\n\t\t/^squashfs$/ and $ret .= \"\\tselect USES_SQUASHFS\\n\";\n\t\t/^targz$/ and $ret .= \"\\tselect USES_TARGZ\\n\";\n\t\t/^testing-kernel$/ and $ret .= \"\\tselect HAS_TESTING_KERNEL\\n\";\n\t\t/^ubifs$/ and $ret .= \"\\tselect USES_UBIFS\\n\";\n\t\t/^usb$/ and $ret .= \"\\tselect USB_SUPPORT\\n\";\n\t\t/^usbgadget$/ and $ret .= \"\\tselect USB_GADGET_SUPPORT\\n\";\n\t\t/^virtio$/ and $ret .= \"\\tselect VIRTIO_SUPPORT\\n\";\n\t}\n\treturn $ret;\n}\n\nsub target_name($) {\n\tmy $target = shift;\n\tmy $parent = $target->{parent};\n\tif ($parent) {\n\t\treturn $target->{parent}->{name}.\" - \".$target->{name};\n\t} else {\n\t\treturn $target->{name};\n\t}\n}\n\nsub kver($) {\n\tmy $v = shift;\n\t$v =~ tr/\\./_/;\n\tif (substr($v,0,2) eq \"2_\") {\n\t\t$v =~ /(\\d+_\\d+_\\d+)(_\\d+)?/ and $v = $1;\n\t} else {\n\t\t$v =~ /(\\d+_\\d+)(_\\d+)?/ and $v = $1;\n\t}\n\treturn $v;\n}\n\nsub print_target($) {\n\tmy $target = shift;\n\tmy $features = target_config_features(@{$target->{features}});\n\tmy $help = $target->{desc};\n\tmy $confstr;\n\n\tchomp $features;\n\t$features .= \"\\n\";\n\tif ($help =~ /\\w+/) {\n\t\t$help =~ s/^\\s*/\\t  /mg;\n\t\t$help = \"\\thelp\\n$help\";\n\t} else {\n\t\tundef $help;\n\t}\n\n\tmy $v = kver($target->{version});\n\tmy $tv = kver($target->{testing_version});\n\t$tv or $tv = $v;\n\tif (@{$target->{subtargets}} == 0) {\n\t$confstr = <<EOF;\nconfig TARGET_$target->{conf}\n\tbool \"$target->{name}\"\n\tselect LINUX_$v if !TESTING_KERNEL\n\tselect LINUX_$tv if TESTING_KERNEL\nEOF\n\t}\n\telse {\n\t\t$confstr = <<EOF;\nconfig TARGET_$target->{conf}\n\tbool \"$target->{name}\"\nEOF\n\t}\n\tif ($target->{subtarget}) {\n\t\t$confstr .= \"\\tdepends on TARGET_$target->{boardconf}\\n\";\n\t}\n\tif (@{$target->{subtargets}} > 0) {\n\t\t$confstr .= \"\\tselect HAS_SUBTARGETS\\n\";\n\t\tgrep { /broken/ } @{$target->{features}} and $confstr .= \"\\tdepends on BROKEN\\n\";\n\t} else {\n\t\t$confstr .= $features;\n\t\tif ($target->{arch} =~ /\\w/) {\n\t\t\t$confstr .= \"\\tselect $target->{arch}\\n\";\n\t\t}\n\t\tif ($target->{has_devices}) {\n\t\t\t$confstr .= \"\\tselect HAS_DEVICES\\n\";\n\t\t}\n\t}\n\n\tforeach my $dep (@{$target->{depends}}) {\n\t\tmy $mode = \"depends on\";\n\t\tmy $flags;\n\t\tmy $name;\n\n\t\t$dep =~ /^([@\\+\\-]+)(.+)$/;\n\t\t$flags = $1;\n\t\t$name = $2;\n\n\t\tnext if $name =~ /:/;\n\t\t$flags =~ /-/ and $mode = \"deselect\";\n\t\t$flags =~ /\\+/ and $mode = \"select\";\n\t\t$flags =~ /@/ and $confstr .= \"\\t$mode $name\\n\";\n\t}\n\t$confstr .= \"$help\\n\\n\";\n\tprint $confstr;\n}\n\nsub merge_package_lists($$) {\n\tmy $list1 = shift;\n\tmy $list2 = shift;\n\tmy @l = ();\n\tmy %pkgs;\n\n\tforeach my $pkg (@$list1, @$list2) {\n\t\t$pkgs{$pkg} = 1;\n\t}\n\tforeach my $pkg (keys %pkgs) {\n\t\tpush @l, $pkg unless ($pkg =~ /^-/ or $pkgs{\"-$pkg\"});\n\t}\n\treturn sort(@l);\n}\n\nsub gen_target_config() {\n\tmy $file = shift @ARGV;\n\tmy @target = parse_target_metadata($file);\n\tmy %defaults;\n\n\tmy @target_sort = sort {\n\t\ttarget_name($a) cmp target_name($b);\n\t} @target;\n\n\tforeach my $target (@target_sort) {\n\t\tnext if @{$target->{subtargets}} > 0;\n\t\tprint <<EOF;\nconfig DEFAULT_TARGET_$target->{conf}\n\tbool\n\tdepends on TARGET_PER_DEVICE_ROOTFS\n\tdefault y if TARGET_$target->{conf}\nEOF\n\t\tforeach my $pkg (@{$target->{packages}}) {\n\t\t\tprint \"\\tselect DEFAULT_$pkg if TARGET_PER_DEVICE_ROOTFS\\n\";\n\t\t}\n\t}\n\n\tprint <<EOF;\nchoice\n\tprompt \"Target System\"\n\tdefault TARGET_ath79\n\treset if !DEVEL\n\t\nEOF\n\n\tforeach my $target (@target_sort) {\n\t\tnext if $target->{subtarget};\n\t\tprint_target($target);\n\t}\n\n\tprint <<EOF;\nendchoice\n\nchoice\n\tprompt \"Subtarget\" if HAS_SUBTARGETS\nEOF\n\tforeach my $target (@target) {\n\t\tnext unless $target->{def_subtarget};\n\t\tprint <<EOF;\n\tdefault TARGET_$target->{conf}_$target->{def_subtarget} if TARGET_$target->{conf}\nEOF\n\t}\n\tprint <<EOF;\n\nEOF\n\tforeach my $target (@target) {\n\t\tnext unless $target->{subtarget};\n\t\tprint_target($target);\n\t}\n\nprint <<EOF;\nendchoice\n\nchoice\n\tprompt \"Target Profile\"\n\tdefault TARGET_MULTI_PROFILE if BUILDBOT\n\nEOF\n\tforeach my $target (@target) {\n\t\tmy $profile = $target->{profiles}->[0];\n\t\t$profile or next;\n\t\tprint <<EOF;\n\tdefault TARGET_$target->{conf}_$profile->{id} if TARGET_$target->{conf} && !BUILDBOT\nEOF\n\t}\n\n\tprint <<EOF;\n\nconfig TARGET_MULTI_PROFILE\n\tbool \"Multiple devices\"\n\tdepends on HAS_DEVICES\n\thelp\n\tInstead of only building a single image, or all images, this allows you\n\tto select images to be built for multiple devices in one build.\n\nEOF\n\n\tforeach my $target (@target) {\n\t\tmy $profiles = $target->{profiles};\n\t\tforeach my $profile (@{$target->{profiles}}) {\n\t\t\tprint <<EOF;\nconfig TARGET_$target->{conf}_$profile->{id}\n\tbool \"$profile->{name}\"\n\tdepends on TARGET_$target->{conf}\nEOF\n\t\t\t$profile->{broken} and print \"\\tdepends on BROKEN\\n\";\n\t\t\tmy @pkglist = merge_package_lists($target->{packages}, $profile->{packages});\n\t\t\tforeach my $pkg (@pkglist) {\n\t\t\t\tprint \"\\tselect DEFAULT_$pkg\\n\";\n\t\t\t\t$defaults{$pkg} = 1;\n\t\t\t}\n\t\t\tmy $help = $profile->{desc};\n\t\t\tif ($help =~ /\\w+/) {\n\t\t\t\t$help =~ s/^\\s*/\\t  /mg;\n\t\t\t\t$help = \"\\thelp\\n$help\";\n\t\t\t} else {\n\t\t\t\tundef $help;\n\t\t\t}\n\t\t\tprint \"$help\\n\";\n\t\t}\n\t}\n\n\tprint <<EOF;\nendchoice\n\nmenu \"Target Devices\"\n\tdepends on TARGET_MULTI_PROFILE\n\n\tconfig TARGET_ALL_PROFILES\n\t\tbool \"Enable all profiles by default\"\n\t\tdefault BUILDBOT\n\n\tconfig TARGET_PER_DEVICE_ROOTFS\n\t\tbool \"Use a per-device root filesystem that adds profile packages\"\n\t\tdefault BUILDBOT\n\t\thelp\n\t\tWhen disabled, all device packages from all selected devices\n\t\twill be included in all images by default. (Marked as <*>) You will\n\t\tstill be able to manually deselect any/all packages.\n\t\tWhen enabled, each device builds it's own image, including only the\n\t\tprofile packages for that device.  (Marked as {M}) You will be able\n\t\tto change a package to included in all images by marking as {*}, but\n\t\twill not be able to disable a profile package completely.\n\t\t\n\t\tTo get the most use of this setting, you must set in a .config stub\n\t\tbefore calling \"make defconfig\".  Selecting TARGET_MULTI_PROFILE and\n\t\tthen manually selecting (via menuconfig for instance) this option\n\t\twill have pre-defaulted all profile packages to included, making this\n\t\toption appear to have had no effect.\n\nEOF\n\tforeach my $target (@target) {\n\t\tmy @profiles = sort {\n\t\t\tmy $x = $a->{name};\n\t\t\tmy $y = $b->{name};\n\t\t\t\"\\L$x\" cmp \"\\L$y\";\n\t\t} @{$target->{profiles}};\n\t\tforeach my $profile (@profiles) {\n\t\t\tnext unless $profile->{id} =~ /^DEVICE_/;\n\t\t\tprint <<EOF;\nmenuconfig TARGET_DEVICE_$target->{conf}_$profile->{id}\n\tbool \"$profile->{name}\"\n\tdepends on TARGET_$target->{conf}\n\tdefault $profile->{default}\nEOF\n\t\t\t$profile->{broken} and print \"\\tdepends on BROKEN\\n\";\n\t\t\tmy @pkglist = merge_package_lists($target->{packages}, $profile->{packages});\n\t\t\tforeach my $pkg (@pkglist) {\n\t\t\t\tprint \"\\tselect DEFAULT_$pkg if !TARGET_PER_DEVICE_ROOTFS\\n\";\n\t\t\t\tprint \"\\tselect MODULE_DEFAULT_$pkg if TARGET_PER_DEVICE_ROOTFS\\n\";\n\t\t\t\t$defaults{$pkg} = 1;\n\t\t\t}\n\n\t\t\tprint <<EOF;\n\n\n\tconfig TARGET_DEVICE_PACKAGES_$target->{conf}_$profile->{id}\n\t\tstring \"$profile->{name} additional packages\"\n\t\tdefault \"\"\n\t\tdepends on TARGET_PER_DEVICE_ROOTFS\n\t\tdepends on TARGET_DEVICE_$target->{conf}_$profile->{id}\n\nEOF\n\t\t}\n\t}\n\n\tprint <<EOF;\n\nendmenu\n\nconfig HAS_SUBTARGETS\n\tbool\n\nconfig HAS_DEVICES\n\tbool\n\nconfig TARGET_BOARD\n\tstring\n\nEOF\n\tforeach my $target (@target) {\n\t\t$target->{subtarget} or\tprint \"\\t\\tdefault \\\"\".$target->{board}.\"\\\" if TARGET_\".$target->{conf}.\"\\n\";\n\t}\n\tprint <<EOF;\nconfig TARGET_SUBTARGET\n\tstring\n\tdefault \"generic\" if !HAS_SUBTARGETS\n\nEOF\n\n\tforeach my $target (@target) {\n\t\tforeach my $subtarget (@{$target->{subtargets}}) {\n\t\t\tprint \"\\t\\tdefault \\\"$subtarget\\\" if TARGET_\".$target->{conf}.\"_$subtarget\\n\";\n\t\t}\n\t}\n\tprint <<EOF;\nconfig TARGET_PROFILE\n\tstring\nEOF\n\tforeach my $target (@target) {\n\t\tmy $profiles = $target->{profiles};\n\t\tforeach my $profile (@$profiles) {\n\t\t\tprint \"\\tdefault \\\"$profile->{id}\\\" if TARGET_$target->{conf}_$profile->{id}\\n\";\n\t\t}\n\t}\n\n\tprint <<EOF;\n\nconfig TARGET_ARCH_PACKAGES\n\tstring\n\t\nEOF\n\tforeach my $target (@target) {\n\t\tnext if @{$target->{subtargets}} > 0;\n\t\tprint \"\\t\\tdefault \\\"\".($target->{arch_packages} || $target->{board}).\"\\\" if TARGET_\".$target->{conf}.\"\\n\";\n\t}\n\tprint <<EOF;\n\nconfig DEFAULT_TARGET_OPTIMIZATION\n\tstring\nEOF\n\tforeach my $target (@target) {\n\t\tnext if @{$target->{subtargets}} > 0;\n\t\tprint \"\\tdefault \\\"\".$target->{cflags}.\"\\\" if TARGET_\".$target->{conf}.\"\\n\";\n\t}\n\tprint \"\\tdefault \\\"-Os -pipe -funit-at-a-time\\\"\\n\";\n\tprint <<EOF;\n\nconfig CPU_TYPE\n\tstring\nEOF\n\tforeach my $target (@target) {\n\t\tnext if @{$target->{subtargets}} > 0;\n\t\tprint \"\\tdefault \\\"\".$target->{cputype}.\"\\\" if TARGET_\".$target->{conf}.\"\\n\";\n\t}\n\tprint \"\\tdefault \\\"\\\"\\n\";\n\n\tmy %kver;\n\tforeach my $target (@target) {\n\t\tforeach my $tv ($target->{version}, $target->{testing_version}) {\n\t\t\tnext unless $tv;\n\t\t\tmy $v = kver($tv);\n\t\t\tnext if $kver{$v};\n\t\t\t$kver{$v} = 1;\n\t\t\tprint <<EOF;\n\nconfig LINUX_$v\n\tbool\n\nEOF\n\t\t}\n\t}\n\tforeach my $def (sort keys %defaults) {\n\t\tprint <<EOF;\n\tconfig DEFAULT_$def\n\t\tbool\n\n\tconfig MODULE_DEFAULT_$def\n\t\ttristate\n\t\tdepends on TARGET_PER_DEVICE_ROOTFS\n\t\tdepends on m\n\t\tdefault m if DEFAULT_$def\n\t\tselect PACKAGE_$def\n\nEOF\n\t}\n}\n\nsub gen_profile_mk() {\n\tmy $file = shift @ARGV;\n\tmy $target = shift @ARGV;\n\tmy @targets = parse_target_metadata($file);\n\tforeach my $cur (@targets) {\n\t\tnext unless $cur->{id} eq $target;\n\t\tmy @profile_ids_unique =  do { my %seen; grep { !$seen{$_}++} map { $_->{id} } @{$cur->{profiles}}};\n\t\tprint \"PROFILE_NAMES = \".join(\" \", @profile_ids_unique).\"\\n\";\n\t\tforeach my $profile (@{$cur->{profiles}}) {\n\t\t\tprint $profile->{id}.'_NAME:='.$profile->{name}.\"\\n\";\n\t\t\tprint $profile->{id}.'_HAS_IMAGE_METADATA:='.$profile->{has_image_metadata}.\"\\n\";\n\t\t\tif (defined($profile->{supported_devices}) and @{$profile->{supported_devices}} > 0) {\n\t\t\t\tprint $profile->{id}.'_SUPPORTED_DEVICES:='.join(' ', @{$profile->{supported_devices}}).\"\\n\";\n\t\t\t}\n\t\t\tprint $profile->{id}.'_PACKAGES:='.join(' ', @{$profile->{packages}}).\"\\n\";\n\t\t}\n\t}\n}\n\nsub parse_command() {\n\tGetOptions(\"ignore=s\", \\@ignore);\n\tmy $cmd = shift @ARGV;\n\tfor ($cmd) {\n\t\t/^config$/ and return gen_target_config();\n\t\t/^profile_mk$/ and return gen_profile_mk();\n\t}\n\tdie <<EOF\nAvailable Commands:\n\t$0 config [file] \t\t\tTarget metadata in Kconfig format\n\t$0 profile_mk [file] [target]\t\tProfile metadata in makefile format\n\nEOF\n}\n\nparse_command();\n"
  },
  {
    "path": "scripts/time.pl",
    "content": "#!/usr/bin/env perl\n\nuse strict;\nuse warnings;\nuse Config;\n\nif (@ARGV < 2) {\n\tdie \"Usage: $0 <prefix> <command...>\\n\";\n}\n\nsub gettime {\n\tmy ($sec, $usec);\n\n\teval {\n\t\trequire Time::HiRes;\n\t\t($sec, $usec) = Time::HiRes::gettimeofday();\n\t};\n\n\tunless (defined($sec) && defined($usec)) {\n\t\tmy $tv_t = ($Config{'longsize'} == 8) ? 'qq' : 'll';\n\t\tmy $tv = pack $tv_t, 0, 0;\n\n\t\teval {\n\t\t\trequire 'syscall.ph';\n\t\t\tsyscall(SYS_gettimeofday(), $tv, 0);\n\t\t};\n\n\t\t($sec, $usec) = unpack $tv_t, $tv;\n\t}\n\n\treturn ($sec, $usec);\n}\n\nmy ($prefix, @cmd) = @ARGV;\nmy ($sec, $usec) = gettime();\nmy $pid = fork();\n\nif (!defined($pid)) {\n\tdie \"$0: Failure to fork(): $!\\n\";\n}\nelsif ($pid == 0) {\n\texec(@cmd);\n\tdie \"$0: Failure to exec(): $!\\n\";\n}\nelse {\n\t$SIG{'INT'} = 'IGNORE';\n\t$SIG{'QUIT'} = 'IGNORE';\n\n\tif (waitpid($pid, 0) == -1) {\n\t\tdie \"$0: Failure to waitpid(): $!\\n\";\n\t}\n\n\tmy $exitcode = $? >> 8;\n\tmy ($sec2, $usec2) = gettime();\n\tmy (undef, undef, $cuser, $csystem) = times();\n\n\tprintf STDOUT \"%s#%.2f#%.2f#%.2f\\n\",\n\t\t$prefix, $cuser, $csystem,\n\t\t($sec2 - $sec) + ($usec2 - $usec) / 1000000;\n\n\t$SIG{'INT'} = 'DEFAULT';\n\t$SIG{'QUIT'} = 'DEFAULT';\n\n\texit $exitcode;\n}\n"
  },
  {
    "path": "scripts/timestamp.pl",
    "content": "#!/usr/bin/env perl\n# \n# Copyright (C) 2006 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\nuse strict;\n\nsub get_ts($$) {\n\tmy $path = shift;\n\tmy $options = shift;\n\tmy $ts = 0;\n\tmy $fn = \"\";\n\t$path .= \"/\" if( -d $path);\n\topen FIND, \"find $path -type f -and -not -path \\\\*/.svn\\\\* -and -not -path \\\\*CVS\\\\* $options 2>/dev/null |\";\n\twhile (<FIND>) {\n\t\tchomp;\n\t\tmy $file = $_;\n\t\tnext if -l $file;\n\t\tmy $mt = (stat $file)[9];\n\t\tif ($mt > $ts) {\n\t\t\t$ts = $mt;\n\t\t\t$fn = $file;\n\t\t}\n\t}\n\tclose FIND;\n\treturn ($ts, $fn);\n}\n\n(@ARGV > 0) or push @ARGV, \".\";\nmy $ts = 0;\nmy $n = \".\";\nmy %options;\nwhile (@ARGV > 0) {\n\tmy $path = shift @ARGV;\n\tif ($path =~ /^-x/) {\n\t\tmy $str = shift @ARGV;\n\t\t$options{\"findopts\"} .= \" -and -not -path '\".$str.\"'\"\n\t} elsif ($path =~ /^-f/) {\n\t\t$options{\"findopts\"} .= \" -follow\";\n\t} elsif ($path =~ /^-n/) {\n\t\tmy $arg = $ARGV[0];\n\t\t$options{$path} = $arg;\n\t} elsif ($path =~ /^-/) {\n\t\t$options{$path} = 1;\n\t} else {\n\t\tmy ($tmp, $fname) = get_ts($path, $options{\"findopts\"});\n\t\tif ($tmp > $ts) {\n\t\t\tif ($options{'-F'}) {\n\t\t\t\t$n = $fname;\n\t\t\t} else {\n\t\t\t\t$n = $path;\n\t\t\t}\n\t\t\t$ts = $tmp;\n\t\t}\n\t}\n}\n\nif ($options{\"-n\"}) {\n\texit ($n eq $options{\"-n\"} ? 0 : 1);\n} elsif ($options{\"-p\"}) {\n\tprint \"$n\\n\";\n} elsif ($options{\"-t\"}) {\n\tprint \"$ts\\n\";\n} else {\n\tprint \"$n\\t$ts\\n\";\n}\n"
  },
  {
    "path": "scripts/ubinize-image.sh",
    "content": "#!/bin/sh\n\n. $TOPDIR/scripts/functions.sh\n\npart=\"\"\nubootenv=\"\"\nubinize_param=\"\"\nkernel=\"\"\nrootfs=\"\"\noutfile=\"\"\nerr=\"\"\nubinize_seq=\"\"\n\nubivol() {\n\tvolid=$1\n\tname=$2\n\timage=$3\n\tautoresize=$4\n\tsize=\"$5\"\n\techo \"[$name]\"\n\techo \"mode=ubi\"\n\techo \"vol_id=$volid\"\n\techo \"vol_type=dynamic\"\n\techo \"vol_name=$name\"\n\tif [ \"$image\" ]; then\n\t\techo \"image=$image\"\n\t\t[ -n \"$size\" ] && echo \"vol_size=${size}\"\n\telse\n\t\techo \"vol_size=1MiB\"\n\tfi\n\tif [ \"$autoresize\" ]; then\n\t\techo \"vol_flags=autoresize\"\n\tfi\n}\n\nubilayout() {\n\tlocal vol_id=0\n\tlocal rootsize=\n\tlocal autoresize=\n\tlocal rootfs_type=\"$( get_fs_type \"$2\" )\"\n\n\tif [ \"$1\" = \"ubootenv\" ]; then\n\t\tubivol $vol_id ubootenv\n\t\tvol_id=$(( $vol_id + 1 ))\n\t\tubivol $vol_id ubootenv2\n\t\tvol_id=$(( $vol_id + 1 ))\n\tfi\n\tfor part in $parts; do\n\t\tname=\"${part%%=*}\"\n\t\tprev=\"$part\"\n\t\tpart=\"${part#*=}\"\n\t\t[ \"$prev\" = \"$part\" ] && part=\n\n\t\timage=\"${part%%=*}\"\n\t\tprev=\"$part\"\n\t\tpart=\"${part#*=}\"\n\t\t[ \"$prev\" = \"$part\" ] && part=\n\n\t\tsize=\"$part\"\n\n\t\tubivol $vol_id \"$name\" \"$image\" \"\" \"${size}MiB\"\n\t\tvol_id=$(( $vol_id + 1 ))\n\tdone\n\tif [ \"$3\" ]; then\n\t\tubivol $vol_id kernel \"$3\"\n\t\tvol_id=$(( $vol_id + 1 ))\n\tfi\n\n\tif [ \"$2\" ]; then\n\t\tcase \"$rootfs_type\" in\n\t\t\"ubifs\")\n\t\t\tautoresize=1\n\t\t\t;;\n\t\t\"squashfs\")\n\t\t\t# squashfs uses 1k block size, ensure we do not\n\t\t\t# violate that\n\t\t\trootsize=\"$( round_up \"$( stat -c%s \"$2\" )\" 1024 )\"\n\t\t\t;;\n\t\tesac\n\t\tubivol $vol_id rootfs \"$2\" \"$autoresize\" \"$rootsize\"\n\n\t\tvol_id=$(( $vol_id + 1 ))\n\t\t[ \"$rootfs_type\" = \"ubifs\" ] || ubivol $vol_id rootfs_data \"\" 1\n\tfi\n}\n\nset_ubinize_seq() {\n\tif [ -n \"$SOURCE_DATE_EPOCH\" ] ; then\n\t\tubinize_seq=\"-Q $SOURCE_DATE_EPOCH\"\n\tfi\n}\n\nwhile [ \"$1\" ]; do\n\tcase \"$1\" in\n\t\"--uboot-env\")\n\t\tubootenv=\"ubootenv\"\n\t\tshift\n\t\tcontinue\n\t\t;;\n\t\"--kernel\")\n\t\tkernel=\"$2\"\n\t\tshift\n\t\tshift\n\t\tcontinue\n\t\t;;\n\t\"--rootfs\")\n\t\trootfs=\"$2\"\n\t\tshift\n\t\tshift\n\t\tcontinue\n\t\t;;\n\t\"--part\")\n\t\tparts=\"$parts $2\"\n\t\tshift\n\t\tshift\n\t\tcontinue\n\t\t;;\n\t\"-\"*)\n\t\tubinize_param=\"$@\"\n\t\tbreak\n\t\t;;\n\t*)\n\t\tif [ ! \"$outfile\" ]; then\n\t\t\toutfile=$1\n\t\t\tshift\n\t\t\tcontinue\n\t\tfi\n\t\t;;\n\tesac\ndone\n\nif [ ! -r \"$rootfs\" -a ! -r \"$kernel\" -a ! \"$outfile\" ]; then\n\techo \"syntax: $0 [--uboot-env] [--part <name>=<file>] [--kernel kernelimage] [--rootfs rootfsimage] out [ubinize opts]\"\n\texit 1\nfi\n\nubinize=\"$( command -v ubinize )\"\nif [ ! -x \"$ubinize\" ]; then\n\techo \"ubinize tool not found or not usable\"\n\texit 1\nfi\n\nubinizecfg=\"$( mktemp 2> /dev/null )\"\nif [ -z \"$ubinizecfg\" ]; then\n\t# try OSX signature\n\tubinizecfg=\"$( mktemp -t 'ubitmp' )\"\nfi\nubilayout \"$ubootenv\" \"$rootfs\" \"$kernel\" > \"$ubinizecfg\"\n\nset_ubinize_seq\ncat \"$ubinizecfg\"\nubinize $ubinize_seq -o \"$outfile\" $ubinize_param \"$ubinizecfg\"\nerr=\"$?\"\n[ ! -e \"$outfile\" ] && err=2\nrm \"$ubinizecfg\"\n\nexit $err\n"
  },
  {
    "path": "target/Config.in",
    "content": "source \"tmp/.config-target.in\"\n\n# Kernel/Hardware features\n\nconfig HAS_TESTING_KERNEL\n\tbool\n\nconfig HAS_SPE_FPU\n\tdepends on powerpc\n\tselect HAS_FPU\n\tbool\n\nconfig HAS_FPU\n\tbool\n\nconfig HAS_DT_OVERLAY_SUPPORT\n\tbool\n\nconfig AUDIO_SUPPORT\n\tbool\n\nconfig GPIO_SUPPORT\n\tbool\n\nconfig PCI_SUPPORT\n\tselect AUDIO_SUPPORT\n\tbool\n\nconfig PCIE_SUPPORT\n\tbool\n\nconfig PCMCIA_SUPPORT\n\tbool\n\nconfig PWM_SUPPORT\n\tbool\n\nconfig USB_SUPPORT\n\tselect AUDIO_SUPPORT\n\tbool\n\nconfig USB_GADGET_SUPPORT\n\tbool\n\nconfig RTC_SUPPORT\n\tbool\n\nconfig BIG_ENDIAN\n\tbool\n\nconfig USES_DEVICETREE\n\tbool\n\nconfig USES_INITRAMFS\n\tbool\n\nconfig USES_SEPARATE_INITRAMFS\n\tbool\n\nconfig USES_SQUASHFS\n\tbool\n\nconfig USES_JFFS2\n\tbool\n\nconfig USES_JFFS2_NAND\n\tbool\n\nconfig USES_EXT4\n\tbool\n\nconfig USES_TARGZ\n\tbool\n\nconfig USES_CPIOGZ\n\tbool\n\nconfig USES_MINOR\n\tbool\n\nconfig USES_UBIFS\n\tbool\n\tselect NAND_SUPPORT\n\nconfig LOW_MEMORY_FOOTPRINT\n\tbool\n\nconfig SMALL_FLASH\n\tbool\n\nconfig NOMMU\n\tbool\n\nconfig HAS_MIPS16\n\tdepends on (mips || mipsel || mips64 || mips64el)\n\tbool\n\nconfig RFKILL_SUPPORT\n\tbool\n\nconfig EMMC_SUPPORT\n\tbool\n\nconfig NAND_SUPPORT\n\tbool\n\nconfig LEGACY_SDCARD_SUPPORT\n\tbool\n\nconfig ARCH_64BIT\n\tbool\n\nconfig VIRTIO_SUPPORT\n\tbool\n\nconfig USES_ROOTFS_PART\n\tbool\n\nconfig USES_BOOT_PART\n\tbool\n\n# Architecture selection\n\nconfig aarch64\n\tselect ARCH_64BIT\n\tbool\n\nconfig aarch64_be\n\tselect ARCH_64BIT\n\tselect BIG_ENDIAN\n\tbool\n\nconfig arc\n\tbool\n\nconfig arceb\n\tselect BIG_ENDIAN\n\tbool\n\nconfig arm\n\tbool\n\nconfig armeb\n\tselect BIG_ENDIAN\n\tbool\n\nconfig arm_v6\n\tbool\n\nconfig arm_v7\n\tbool\n\nconfig i386\n\tbool\n\nconfig i686\n\tbool \n\nconfig m68k\n\tbool\n\nconfig mips\n\tselect BIG_ENDIAN\n\tbool\n\nconfig mipsel\n\tbool\n\nconfig mips64\n\tselect BIG_ENDIAN\n\tselect ARCH_64BIT\n\tbool\n\nconfig mips64el\n\tselect ARCH_64BIT\n\tbool\n\nconfig powerpc\n\tselect BIG_ENDIAN\n\tbool\n\nconfig powerpc64\n\tselect BIG_ENDIAN\n\tselect ARCH_64BIT\n\tbool\n\nconfig sh3\n\tbool\n\nconfig sh3eb\n\tselect BIG_ENDIAN\n\tbool\n\nconfig sh4\n\tbool\n\nconfig sh4eb\n\tselect BIG_ENDIAN\n\tbool\n\nconfig sparc\n\tselect BIG_ENDIAN\n\tbool\n\nconfig x86_64\n\tselect ARCH_64BIT\n\tbool\n\nconfig ARCH\n\tstring\n\tdefault \"aarch64\"   if aarch64\n\tdefault \"aarch64_be\" if aarch64_be\n\tdefault \"arc\"       if arc\n\tdefault \"arceb\"     if arceb\n\tdefault \"arm\"       if arm\n\tdefault \"armeb\"     if armeb\n\tdefault \"i386\"      if i386\n\tdefault \"i686\"      if i686\n\tdefault \"m68k\"      if m68k\n\tdefault \"mips\"      if mips\n\tdefault \"mipsel\"    if mipsel\n\tdefault \"mips64\"    if mips64\n\tdefault \"mips64el\"  if mips64el\n\tdefault \"powerpc\"   if powerpc\n\tdefault \"powerpc64\" if powerpc64\n\tdefault \"sh3\"       if sh3\n\tdefault \"sh3eb\"     if sh3eb\n\tdefault \"sh4\"       if sh4\n\tdefault \"sh4eb\"     if sh4eb\n\tdefault \"sparc\"     if sparc\n\tdefault \"x86_64\"    if x86_64\n\n"
  },
  {
    "path": "target/Makefile",
    "content": "# \n# Copyright (C) 2007 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\ncurdir:=target\n\n$(curdir)/subtargets:=install\n$(curdir)/builddirs:=linux sdk imagebuilder toolchain llvm-bpf\n$(curdir)/builddirs-default:=linux\n$(curdir)/builddirs-install:=\\\n\tlinux \\\n\t$(if $(CONFIG_SDK),sdk) \\\n\t$(if $(CONFIG_IB),imagebuilder) \\\n\t$(if $(CONFIG_MAKE_TOOLCHAIN),toolchain) \\\n\t$(if $(CONFIG_SDK_LLVM_BPF),llvm-bpf)\n\n$(curdir)/sdk/install:=$(curdir)/linux/install\n$(curdir)/imagebuilder/install:=$(curdir)/linux/install\n\n$(eval $(call stampfile,$(curdir),target,prereq,.config))\n$(eval $(call stampfile,$(curdir),target,compile,$(TMP_DIR)/.build))\n$(eval $(call stampfile,$(curdir),target,install,$(TMP_DIR)/.build))\n\n$($(curdir)/stamp-install): $($(curdir)/stamp-compile) \n\n$(eval $(call subdir,$(curdir)))\n"
  },
  {
    "path": "target/imagebuilder/Config.in",
    "content": "config IB\n\tbool \"Build the OpenWrt Image Builder\"\n\tdepends on !EXTERNAL_TOOLCHAIN\n\tdefault BUILDBOT\n\thelp\n\t  This is essentially a stripped-down version of the buildroot\n\t  with precompiled packages, kernel image and image building tools.\n\t  You can use it to generate custom images without compiling anything\n\nconfig IB_STANDALONE\n\tbool \"Include package repositories\"\n\tdefault y if !BUILDBOT\n\tdepends on IB\n\thelp\n\t  Disabling this option will cause the ImageBuilder to embed only\n\t  toolchain and kmod packages while all other ipk archives will be\n\t  fetched from online repositories.\n"
  },
  {
    "path": "target/imagebuilder/Makefile",
    "content": "#\n# Copyright (C) 2006-2015 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\ninclude $(INCLUDE_DIR)/kernel.mk\ninclude $(INCLUDE_DIR)/version.mk\ninclude $(INCLUDE_DIR)/feeds.mk\n\noverride MAKEFLAGS=\n\nIB_NAME:=$(VERSION_DIST_SANITIZED)-imagebuilder-$(if $(CONFIG_VERSION_FILENAMES),$(VERSION_NUMBER)-)$(BOARD)$(if $(SUBTARGET),-$(SUBTARGET)).$(HOST_OS)-$(HOST_ARCH)\nPKG_BUILD_DIR:=$(BUILD_DIR)/$(IB_NAME)\nIB_KDIR:=$(patsubst $(TOPDIR)/%,$(PKG_BUILD_DIR)/%,$(KERNEL_BUILD_DIR))\nIB_LDIR:=$(patsubst $(TOPDIR)/%,$(PKG_BUILD_DIR)/%,$(LINUX_DIR))\nIB_DTSDIR:=$(patsubst $(TOPDIR)/%,$(PKG_BUILD_DIR)/%,$(LINUX_DIR))/arch/$(LINUX_KARCH)/boot/dts/\nIB_IDIR:=$(patsubst $(TOPDIR)/%,$(PKG_BUILD_DIR)/%,$(STAGING_DIR_IMAGE))\n\nBUNDLER_PATH := $(subst $(space),:,$(filter-out $(TOPDIR)/%,$(subst :,$(space),$(PATH))))\nBUNDLER_COMMAND := PATH=$(BUNDLER_PATH) $(XARGS) $(SCRIPT_DIR)/bundle-libraries.sh $(PKG_BUILD_DIR)/staging_dir/host\n\nall: compile\n\n$(BIN_DIR)/$(IB_NAME).tar.xz: clean\n\trm -rf $(PKG_BUILD_DIR)\n\tmkdir -p $(IB_KDIR) $(IB_LDIR) $(PKG_BUILD_DIR)/staging_dir/host/lib \\\n\t\t$(PKG_BUILD_DIR)/target $(PKG_BUILD_DIR)/scripts $(IB_DTSDIR)\n\t-cp $(TOPDIR)/.config $(PKG_BUILD_DIR)/.config\n\t$(SED) 's/^CONFIG_BINARY_FOLDER=.*/# CONFIG_BINARY_FOLDER is not set/' $(PKG_BUILD_DIR)/.config\n\t$(SED) 's/^CONFIG_DOWNLOAD_FOLDER=.*/# CONFIG_DOWNLOAD_FOLDER is not set/' $(PKG_BUILD_DIR)/.config\n\t$(CP) -L \\\n\t\t$(INCLUDE_DIR) $(SCRIPT_DIR) \\\n\t\t$(TOPDIR)/rules.mk \\\n\t\t./files/Makefile \\\n\t\t./files/repositories.conf \\\n\t\t$(TMP_DIR)/.targetinfo \\\n\t\t$(TMP_DIR)/.packageinfo \\\n\t\t$(PKG_BUILD_DIR)/\n\nifeq ($(CONFIG_IB_STANDALONE),)\n\techo '## Remote package repositories' >> $(PKG_BUILD_DIR)/repositories.conf\n\t$(call FeedSourcesAppend,$(PKG_BUILD_DIR)/repositories.conf)\n\t$(VERSION_SED_SCRIPT) $(PKG_BUILD_DIR)/repositories.conf\nendif\n\n\t$(INSTALL_DIR) $(PKG_BUILD_DIR)/packages\n\t# create an empty package index so `opkg` doesn't report an error\n\ttouch $(PKG_BUILD_DIR)/packages/Packages\n\t$(INSTALL_DATA) ./files/README.md $(PKG_BUILD_DIR)/packages/\n\n\techo ''                                                        >> $(PKG_BUILD_DIR)/repositories.conf\n\techo '## This is the local package repository, do not remove!' >> $(PKG_BUILD_DIR)/repositories.conf\n\techo 'src imagebuilder file:packages'                          >> $(PKG_BUILD_DIR)/repositories.conf\n\nifeq ($(CONFIG_BUILDBOT),)\n  ifeq ($(CONFIG_IB_STANDALONE),)\n\t$(FIND) $(call FeedPackageDir,libc) -type f \\\n\t\t\\( -name 'libc_*.ipk' -or -name 'kernel_*.ipk' -or -name 'kmod-*.ipk' \\) \\\n\t\t-exec $(CP) -t $(PKG_BUILD_DIR)/packages {} +\n  else\n\t$(FIND) $(wildcard $(PACKAGE_SUBDIRS)) -type f -name '*.ipk' \\\n\t\t-exec $(CP) -t $(PKG_BUILD_DIR)/packages/ {} +\n  endif\nelse\n\t$(FIND) $(call FeedPackageDir,libc) -type f \\\n\t\t\\( -name 'libc_*.ipk' -or -name 'kernel_*.ipk' \\) \\\n\t\t-exec $(CP) -t $(IB_LDIR)/ {} +\nendif\n\nifneq ($(CONFIG_SIGNATURE_CHECK),)\n\techo ''                                                        >> $(PKG_BUILD_DIR)/repositories.conf\n\techo 'option check_signature'                                  >> $(PKG_BUILD_DIR)/repositories.conf\n\t$(INSTALL_DIR) $(PKG_BUILD_DIR)/keys\n\t$(CP) -L $(STAGING_DIR_ROOT)/etc/opkg/keys/ $(PKG_BUILD_DIR)/\n\t$(CP) -L $(STAGING_DIR_ROOT)/usr/sbin/opkg-key $(PKG_BUILD_DIR)/scripts/\nendif\n\n\t$(CP) -L $(TOPDIR)/target/linux $(PKG_BUILD_DIR)/target/\n\tif [ -d $(TOPDIR)/staging_dir/host/lib/grub ]; then \\\n\t\t$(CP) $(TOPDIR)/staging_dir/host/lib/grub/ $(PKG_BUILD_DIR)/staging_dir/host/lib; \\\n\tfi\n\trm -rf \\\n\t\t$(PKG_BUILD_DIR)/target/linux/*/files{,-*} \\\n\t\t$(PKG_BUILD_DIR)/target/linux/*/patches{,-*} \\\n\t\t$(PKG_BUILD_DIR)/target/linux/generic/{pending,backport,hack}{,-*}\n\t-cp $(KERNEL_BUILD_DIR)/* $(IB_KDIR)/ # don't copy subdirectories here\n\t-cp $(LINUX_DIR)/.config $(IB_LDIR)/\n\trm -f $(IB_KDIR)/root.*\n\trm -f $(IB_KDIR)/vmlinux.debug\n\tif [ -x $(LINUX_DIR)/scripts/dtc/dtc ]; then \\\n\t\t$(INSTALL_DIR) $(IB_LDIR)/scripts/dtc; \\\n\t\t$(INSTALL_BIN) $(LINUX_DIR)/scripts/dtc/dtc $(IB_LDIR)/scripts/dtc/dtc; \\\n\tfi\n\tif [ -d $(LINUX_DIR)/arch/$(LINUX_KARCH)/boot/dts ]; then \\\n\t\t$(CP) -L $(LINUX_DIR)/arch/$(LINUX_KARCH)/boot/dts/* $(IB_DTSDIR); \\\n\tfi\n\t$(SED) 's,^# REVISION:=.*,REVISION:=$(REVISION),g' $(PKG_BUILD_DIR)/include/version.mk\n\t$(SED) 's,^# SOURCE_DATE_EPOCH:=.*,SOURCE_DATE_EPOCH:=$(SOURCE_DATE_EPOCH),g' $(PKG_BUILD_DIR)/include/version.mk\n\t$(SED) '/LINUX_VERMAGIC:=/ { s,unknown,$(LINUX_VERMAGIC),g }' $(PKG_BUILD_DIR)/include/kernel.mk\n\tfind $(PKG_BUILD_DIR) -name CVS -o -name .git -o -name .svn \\\n\t  | $(XARGS) rm -rf\n\t$(INSTALL_DIR) $(IB_IDIR)\n\t-$(CP) $(STAGING_DIR_IMAGE)/* $(IB_IDIR)/\n\t$(INSTALL_DIR) $(PKG_BUILD_DIR)/staging_dir/host/bin\n\t$(CP) $(STAGING_DIR_HOST)/bin/* $(PKG_BUILD_DIR)/staging_dir/host/bin/\n\t(cd $(PKG_BUILD_DIR); find staging_dir/host/bin/ $(IB_LDIR)/scripts/dtc/ -type f | \\\n\t\t$(BUNDLER_COMMAND))\n\t$(CP) $(TOPDIR)/staging_dir/host/lib/libfakeroot* $(PKG_BUILD_DIR)/staging_dir/host/lib\n\tSTRIP=$(STAGING_DIR_HOST)/bin/sstrip $(SCRIPT_DIR)/rstrip.sh $(PKG_BUILD_DIR)/staging_dir/host/bin/\n\t(cd $(BUILD_DIR); \\\n\t\ttar -I '$(STAGING_DIR_HOST)/bin/xz -7e -T$(if $(filter 1,$(NPROC)),2,0)' -cf $@ $(IB_NAME) \\\n\t\t--mtime=\"$(shell date --date=@$(SOURCE_DATE_EPOCH))\"; \\\n\t)\n\ndownload:\nprepare:\ncompile: $(BIN_DIR)/$(IB_NAME).tar.xz\ninstall: compile\n\nclean: FORCE\n\trm -rf $(PKG_BUILD_DIR) $(BIN_DIR)/$(IB_NAME).tar.xz\n"
  },
  {
    "path": "target/imagebuilder/files/Makefile",
    "content": "# Makefile for OpenWrt\n#\n# Copyright (C) 2007-2015 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\nTOPDIR:=${CURDIR}\nLC_ALL:=C\nLANG:=C\nexport TOPDIR LC_ALL LANG\nexport OPENWRT_VERBOSE=s\nall: help\n\nexport PATH:=$(TOPDIR)/staging_dir/host/bin:$(PATH)\n\nifneq ($(OPENWRT_BUILD),1)\n  override OPENWRT_BUILD=1\n  export OPENWRT_BUILD\nendif\n\ninclude rules.mk\ninclude $(INCLUDE_DIR)/debug.mk\ninclude $(INCLUDE_DIR)/depends.mk\ninclude $(INCLUDE_DIR)/rootfs.mk\n\ninclude $(INCLUDE_DIR)/version.mk\nexport REVISION\nexport SOURCE_DATE_EPOCH\n\ndefine Helptext\nAvailable Commands:\n\thelp:\tThis help text\n\tinfo:\tShow a list of available target profiles\n\tclean:\tRemove images and temporary build files\n\timage:\tBuild an image (see below for more information).\n\nBuilding images:\n\tBy default 'make image' will create an image with the default\n\ttarget profile and package set. You can use the following parameters\n\tto change that:\n\n\tmake image PROFILE=\"<profilename>\" # override the default target profile\n\tmake image PACKAGES=\"<pkg1> [<pkg2> [<pkg3> ...]]\" # include extra packages\n\tmake image FILES=\"<path>\" # include extra files from <path>\n\tmake image BIN_DIR=\"<path>\" # alternative output directory for the images\n\tmake image EXTRA_IMAGE_NAME=\"<string>\" # Add this to the output image filename (sanitized)\n\tmake image DISABLED_SERVICES=\"<svc1> [<svc2> [<svc3> ..]]\" # Which services in /etc/init.d/ should be disabled\n\tmake image ADD_LOCAL_KEY=1 # store locally generated signing key in built images\n\nPrint manifest:\n\tList \"all\" packages which get installed into the image.\n\tYou can use the following parameters:\n\n\tmake manifest PROFILE=\"<profilename>\" # override the default target profile\n\tmake manifest PACKAGES=\"<pkg1> [<pkg2> [<pkg3> ...]]\" # include extra packages\n\tmake manifest STRIP_ABI=1 # remove ABI version from printed package names\n\nendef\n$(eval $(call shexport,Helptext))\n\nhelp: FORCE\n\techo \"$$$(call shvar,Helptext)\"\n\n\n# override variables from rules.mk\nPACKAGE_DIR:=$(TOPDIR)/packages\nLISTS_DIR:=$(subst $(space),/,$(patsubst %,..,$(subst /,$(space),$(TARGET_DIR))))$(DL_DIR)\nexport OPKG_KEYS:=$(TOPDIR)/keys\nOPKG:=$(call opkg,$(TARGET_DIR)) \\\n\t-f $(TOPDIR)/repositories.conf \\\n\t--verify-program $(SCRIPT_DIR)/opkg-key \\\n\t--cache $(DL_DIR) \\\n\t--lists-dir $(LISTS_DIR)\n\ninclude $(INCLUDE_DIR)/target.mk\n-include .profiles.mk\n\nUSER_PROFILE ?= $(firstword $(PROFILE_NAMES))\nPROFILE_LIST = $(foreach p,$(PROFILE_NAMES), \\\n\techo '$(patsubst DEVICE_%,%,$(p)):'; $(if $($(p)_NAME),echo '    $(subst ','\"'\"',$($(p)_NAME))'; ) \\\n\techo '    Packages: $($(p)_PACKAGES)'; echo '    hasImageMetadata: $($(p)_HAS_IMAGE_METADATA)'; \\\n\t$(if $($(p)_SUPPORTED_DEVICES),echo '    SupportedDevices: $($(p)_SUPPORTED_DEVICES)';) )\n\n\n.profiles.mk: .targetinfo\n\t@$(SCRIPT_DIR)/target-metadata.pl profile_mk $< '$(BOARD)$(if $(SUBTARGET),/$(SUBTARGET))' > $@\n\nstaging_dir/host/.prereq-build: include/prereq-build.mk\n\tmkdir -p tmp\n\t@$(_SINGLE)$(NO_TRACE_MAKE) -j1 -r -s -f $(TOPDIR)/include/prereq-build.mk prereq IB=1 2>/dev/null || { \\\n\t\techo \"Prerequisite check failed. Use FORCE=1 to override.\"; \\\n\t\tfalse; \\\n\t}\n  ifneq ($(realpath $(TOPDIR)/include/prepare.mk),)\n\t@$(_SINGLE)$(NO_TRACE_MAKE) -j1 -r -s -f $(TOPDIR)/include/prepare.mk prepare 2>/dev/null || { \\\n\t\techo \"Preparation failed.\"; \\\n\t\tfalse; \\\n\t}\n  endif\n\ttouch $@\n\n_call_info: FORCE\n\techo 'Current Target: \"$(TARGETID)\"'\n\techo 'Current Architecture: \"$(ARCH)\"'\n\techo 'Current Revision: \"$(REVISION)\"'\n\techo 'Default Packages: $(DEFAULT_PACKAGES)'\n\techo 'Available Profiles:'\n\techo; $(PROFILE_LIST)\n\nBUILD_PACKAGES:=$(USER_PACKAGES) $(sort $(DEFAULT_PACKAGES) $($(USER_PROFILE)_PACKAGES) kernel)\n# \"-pkgname\" in the package list means remove \"pkgname\" from the package list\nBUILD_PACKAGES:=$(filter-out $(filter -%,$(BUILD_PACKAGES)) $(patsubst -%,%,$(filter -%,$(BUILD_PACKAGES))),$(BUILD_PACKAGES))\nPACKAGES:=\n\n_call_image: staging_dir/host/.prereq-build\n\techo 'Building images for $(BOARD)$(if $($(USER_PROFILE)_NAME), - $($(USER_PROFILE)_NAME))'\n\techo 'Packages: $(BUILD_PACKAGES)'\n\techo\n\trm -rf $(TARGET_DIR) $(TARGET_DIR_ORIG)\n\tmkdir -p $(TARGET_DIR) $(BIN_DIR) $(TMP_DIR) $(DL_DIR)\n\t$(MAKE) package_reload\n\t$(MAKE) package_install\n\t$(MAKE) -s prepare_rootfs\n\t$(MAKE) -s build_image\n\t$(MAKE) -s json_overview_image_info\n\t$(MAKE) -s checksum\n\n_call_manifest: FORCE\n\trm -rf $(TARGET_DIR)\n\tmkdir -p $(TARGET_DIR) $(BIN_DIR) $(TMP_DIR) $(DL_DIR)\n\t$(MAKE) package_reload >/dev/null\n\t$(MAKE) package_install >/dev/null\n\t$(OPKG) list-installed $(if $(STRIP_ABI),--strip-abi)\n\npackage_index: FORCE\n\t@echo >&2\n\t@echo Building package index... >&2\n\t@mkdir -p $(TMP_DIR) $(TARGET_DIR)/tmp\n\t(cd $(PACKAGE_DIR); $(SCRIPT_DIR)/ipkg-make-index.sh . > Packages && \\\n\t\tgzip -9nc Packages > Packages.gz; \\\n\t\t$(if $(CONFIG_SIGNATURE_CHECK), \\\n\t\t\t$(STAGING_DIR_HOST)/bin/usign -S -m Packages -s $(BUILD_KEY)) \\\n\t) >/dev/null 2>/dev/null\n\t$(OPKG) update >&2 || true\n\npackage_reload:\n\tif [ -d \"$(PACKAGE_DIR)\" ] && ( \\\n\t\t\t[ ! -f \"$(PACKAGE_DIR)/Packages\" ] || \\\n\t\t\t[ ! -f \"$(PACKAGE_DIR)/Packages.gz\" ] || \\\n\t\t\t[ \"`find $(PACKAGE_DIR) -cnewer $(PACKAGE_DIR)/Packages.gz`\" ] ); then \\\n\t\techo \"Package list missing or not up-to-date, generating it.\" >&2 ;\\\n\t\t$(MAKE) package_index; \\\n\telse \\\n\t\tmkdir -p $(TARGET_DIR)/tmp; \\\n\t\t$(OPKG) update >&2 || true; \\\n\tfi\n\npackage_list: FORCE\n\t@$(MAKE) -s package_reload\n\t@$(OPKG) list --size 2>/dev/null\n\npackage_install: FORCE\n\t@echo\n\t@echo Installing packages...\n\t$(OPKG) install $(firstword $(wildcard $(LINUX_DIR)/libc_*.ipk $(PACKAGE_DIR)/libc_*.ipk))\n\t$(OPKG) install $(firstword $(wildcard $(LINUX_DIR)/kernel_*.ipk $(PACKAGE_DIR)/kernel_*.ipk))\n\t$(OPKG) install $(BUILD_PACKAGES)\n\nprepare_rootfs: FORCE\n\t@echo\n\t@echo Finalizing root filesystem...\n\n\t$(CP) $(TARGET_DIR) $(TARGET_DIR_ORIG)\n\t$(if $(CONFIG_SIGNATURE_CHECK), \\\n\t\t$(if $(ADD_LOCAL_KEY), \\\n\t\t\tOPKG_KEYS=$(TARGET_DIR)/etc/opkg/keys/ \\\n\t\t\t$(SCRIPT_DIR)/opkg-key add $(BUILD_KEY).pub \\\n\t\t) \\\n\t)\n\t$(call prepare_rootfs,$(TARGET_DIR),$(USER_FILES),$(DISABLED_SERVICES))\n\nbuild_image: FORCE\n\t@echo\n\t@echo Building images...\n\trm -rf $(BUILD_DIR)/json_info_files/\n\t$(NO_TRACE_MAKE) -C target/linux/$(BOARD)/image install TARGET_BUILD=1 IB=1 EXTRA_IMAGE_NAME=\"$(EXTRA_IMAGE_NAME)\" \\\n\t\t$(if $(USER_PROFILE),PROFILE=\"$(USER_PROFILE)\")\n\n$(BIN_DIR)/profiles.json: FORCE\n\t$(if $(CONFIG_JSON_OVERVIEW_IMAGE_INFO), \\\n\t\tWORK_DIR=$(BUILD_DIR)/json_info_files \\\n\t\t\t$(SCRIPT_DIR)/json_overview_image_info.py $@ \\\n\t)\n\njson_overview_image_info: $(BIN_DIR)/profiles.json\n\nchecksum: FORCE\n\t@echo\n\t@echo Calculating checksums...\n\t@$(call sha256sums,$(BIN_DIR))\n\nclean:\n\trm -rf $(TMP_DIR) $(DL_DIR) $(TARGET_DIR) $(BIN_DIR)\n\n\ninfo:\n\t(unset PROFILE FILES PACKAGES MAKEFLAGS; $(MAKE) -s _call_info)\n\nPROFILE_FILTER = $(filter DEVICE_$(PROFILE) $(PROFILE),$(PROFILE_NAMES))\n\n_check_profile: FORCE\nifneq ($(PROFILE),)\n  ifeq ($(PROFILE_FILTER),)\n\t@echo 'Profile \"$(PROFILE)\" does not exist!'\n\t@echo 'Use \"make info\" to get a list of available profile names.'\n\t@exit 1\n  endif\nendif\n\n_check_keys: FORCE\nifneq ($(CONFIG_SIGNATURE_CHECK),)\n\t@if [ ! -s $(BUILD_KEY) -o ! -s $(BUILD_KEY).pub ]; then \\\n\t\techo Generate local signing keys... >&2; \\\n\t\t$(STAGING_DIR_HOST)/bin/usign -G \\\n\t\t\t-s $(BUILD_KEY) -p $(BUILD_KEY).pub -c \"Local build key\"; \\\n\t\t$(SCRIPT_DIR)/opkg-key add $(BUILD_KEY).pub; \\\n\tfi\n\tif [ ! -s $(BUILD_KEY).ucert ]; then \\\n\t\techo Generate local certificate... >&2; \\\n\t\t$(STAGING_DIR_HOST)/bin/ucert -I \\\n\t\t\t-c $(BUILD_KEY).ucert \\\n\t\t\t-p $(BUILD_KEY).pub \\\n\t\t\t-s $(BUILD_KEY); \\\n\tfi\nendif\n\nimage:\n\t$(MAKE) -s _check_profile\n\t$(MAKE) -s _check_keys\n\t(unset PROFILE FILES PACKAGES MAKEFLAGS; \\\n\t$(MAKE) -s _call_image \\\n\t\t$(if $(PROFILE),USER_PROFILE=\"$(PROFILE_FILTER)\") \\\n\t\t$(if $(FILES),USER_FILES=\"$(FILES)\") \\\n\t\t$(if $(PACKAGES),USER_PACKAGES=\"$(PACKAGES)\") \\\n\t\t$(if $(BIN_DIR),BIN_DIR=\"$(BIN_DIR)\") \\\n\t\t$(if $(DISABLED_SERVICES),DISABLED_SERVICES=\"$(DISABLED_SERVICES)\"))\n\nmanifest: FORCE\n\t$(MAKE) -s _check_profile\n\t$(MAKE) -s _check_keys\n\t(unset PROFILE FILES PACKAGES MAKEFLAGS; \\\n\t$(MAKE) -s _call_manifest \\\n\t\t$(if $(PROFILE),USER_PROFILE=\"$(PROFILE_FILTER)\") \\\n\t\t$(if $(PACKAGES),USER_PACKAGES=\"$(PACKAGES)\"))\n\nwhatdepends: FORCE\nifeq ($(PACKAGE),)\n\t@echo 'Variable `PACKAGE` is not set but required by `whatdepends`'\n\t@exit 1\nendif\n\t@$(MAKE) -s package_reload\n\t@$(OPKG) whatdepends -A $(PACKAGE)\n\n.SILENT: help info image manifest whatdepends\n"
  },
  {
    "path": "target/imagebuilder/files/README.md",
    "content": "# ./packages folder\n\nAdd `.ipk` packages to this folder will allow the ImageBuilder to install them.\n\nFor more complex setups consider adding a custom feed containing packages.\n\n    src custom file:///path/to/packages\n\nWhenever the ImageBuilder builds a firmware image this folder will be reloaded\nand a new package index created. In case signature checks are enabled the\n`./packages/Packages` index will be signed with a locally generated key pair.\n"
  },
  {
    "path": "target/imagebuilder/files/repositories.conf",
    "content": "## Place your custom repositories here, they must match the architecture and version.\n# src/gz %n %U\n# src custom file:///usr/src/openwrt/bin/%T/packages\n\n"
  },
  {
    "path": "target/linux/Makefile",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2006-2007 OpenWrt.org\n\ninclude $(TOPDIR)/rules.mk\ninclude $(INCLUDE_DIR)/target.mk\n\nexport TARGET_BUILD=1\n\nprereq clean download prepare compile install oldconfig menuconfig nconfig xconfig update refresh: FORCE\n\t@+$(NO_TRACE_MAKE) -C $(BOARD) $@\n"
  },
  {
    "path": "target/linux/apm821xx/Makefile",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n\ninclude $(TOPDIR)/rules.mk\n\nARCH:=powerpc\nBOARD:=apm821xx\nBOARDNAME:=AppliedMicro APM821xx\nCPU_TYPE:=464fp\nFEATURES:=fpu dt gpio ramdisk squashfs usb\nSUBTARGETS:=nand sata\n\nKERNEL_PATCHVER:=5.10\nKERNEL_TESTING_PATCHVER:=5.15\n\ndefine Target/Description\n\tBuild images for AppliedMicro APM821xx based boards.\nendef\n\ninclude $(INCLUDE_DIR)/target.mk\n\nKERNELNAME:=uImage\n\nDEFAULT_PACKAGES += \\\n\tkmod-leds-gpio kmod-i2c-core kmod-gpio-button-hotplug\n\n$(eval $(call BuildTarget))\n"
  },
  {
    "path": "target/linux/apm821xx/base-files/etc/board.d/01_leds",
    "content": "\n. /lib/functions/uci-defaults.sh\n\nboard_config_update\n\nboard=$(board_name)\n\ncase \"$board\" in\nmeraki,mr24)\n\tucidef_set_led_netdev \"wan\" \"WAN\" \"green:wan\" \"eth0\"\n\tucidef_set_led_wlan \"wlan5g_1\" \"WIFI 5GHz-1\" \"green:wlan-0\" \"phy1tpt\"\n\tucidef_set_led_wlan \"wlan5g_0\" \"WIFI 5GHz-0\" \"green:wlan-1\" \"phy1radio\"\n\tucidef_set_led_wlan \"wlan2g_1\" \"WIFI 2.4GHz-1\" \"green:wlan-2\" \"phy0tpt\"\n\tucidef_set_led_wlan \"wlan2g_0\" \"WIFI 2.4GHz-0\" \"green:wlan-3\" \"phy0radio\"\n\t;;\n\nmeraki,mx60)\n\tucidef_set_led_switch \"wan\" \"WAN\" \"green:wan\" \"switch0\" \"0x20\"\n\tucidef_set_led_switch \"lan1\" \"LAN1\" \"green:lan-0\" \"switch0\" \"0x10\"\n\tucidef_set_led_switch \"lan2\" \"LAN2\" \"green:lan-1\" \"switch0\" \"0x08\"\n\tucidef_set_led_switch \"lan3\" \"LAN3\" \"green:lan-2\" \"switch0\" \"0x04\"\n\tucidef_set_led_switch \"lan4\" \"LAN4\" \"green:lan-3\" \"switch0\" \"0x02\"\n\t;;\n\nnetgear,wndap620)\n\tucidef_set_led_switch \"lan_act\" \"LAN (Activity)\" \"green:activity\" \"switch0\" \"0x04\" \"0x0f\" \"rx tx\"\n\tucidef_set_led_switch \"lan_100\" \"LAN 100Mbps\" \"amber:lan\" \"switch0\" \"0x04\" \"0x04\" \"link\"\n\tucidef_set_led_switch \"lan_1000\" \"LAN 1000Mbps\" \"green:lan\" \"switch0\" \"0x04\" \"0x08\" \"link\"\n\t;;\n\nnetgear,wndap660)\n\tucidef_set_led_netdev \"lan_act\" \"LAN (Activity)\" \"green:activity\" \"eth0\"\n\tucidef_set_led_switch \"lan1_100\" \"LAN 100Mbps\" \"amber:lan-0\" \"switch0\" \"0x04\" \"0x04\" \"link\"\n\tucidef_set_led_switch \"lan1_1000\" \"LAN 1000Mbps\" \"green:lan-0\" \"switch0\" \"0x04\" \"0x08\" \"link\"\n\tucidef_set_led_switch \"lan2_100\" \"LAN 100Mbps\" \"amber:lan-1\" \"switch0\" \"0x02\" \"0x04\" \"link\"\n\tucidef_set_led_switch \"lan2_1000\" \"LAN 1000Mbps\" \"green:lan-1\" \"switch0\" \"0x02\" \"0x08\" \"link\"\n\tucidef_set_led_wlan \"wlan2g\" \"WLAN2G\" \"green:wlan-0\" \"phy0tpt\"\n\tucidef_set_led_wlan \"wlan5g\" \"WLAN5G\" \"green:wlan-1\" \"phy1tpt\"\n\t;;\n\nnetgear,wndr4700)\n\tucidef_set_led_switch \"wan_green\" \"WAN (green)\" \"green:wan\" \"switch0\" \"0x20\"\n\tucidef_set_led_netdev \"wan_yellow\" \"WAN (yellow)\" \"yellow:wan\" \"eth0.2\" \"tx rx\"\n\t;;\n\nesac\n\nboard_config_flush\n\nexit 0\n"
  },
  {
    "path": "target/linux/apm821xx/base-files/etc/board.d/02_network",
    "content": "\n. /lib/functions/system.sh\n. /lib/functions/uci-defaults.sh\n\nboard_config_update\n\nboard=$(board_name)\n\ncase \"$board\" in\nmeraki,mr24|\\\nwd,mybooklive|\\\nwd,mybooklive-duo)\n\tucidef_set_interface_lan \"eth0\" \"dhcp\"\n\t;;\nnetgear,wndap620)\n\tucidef_add_switch \"switch0\" \"2:lan\" \"5@eth0\"\n\t;;\nnetgear,wndap660)\n\tucidef_add_switch \"switch0\" \"1:lan:2\" \"2:lan:1\" \"5@eth0\"\n\t;;\nmeraki,mx60|\\\nnetgear,wndr4700)\n\tucidef_add_switch \"switch0\" \\\n\t\t\"0@eth0\" \"4:lan\" \"3:lan\" \"2:lan\" \"1:lan\" \"5:wan\"\n\t;;\n\n*)\n\tucidef_set_interfaces_lan_wan \"eth0\" \"eth1\"\n\t;;\nesac\n\nboard_config_flush\n\nexit 0\n"
  },
  {
    "path": "target/linux/apm821xx/base-files/etc/diag.sh",
    "content": "#!/bin/sh\n# SPDX-License-Identifier: GPL-2.0-only\n\n. /lib/functions/leds.sh\n\nget_status_led() {\n\tlocal status_led_file\n\n\tstatus_led_file=$(find /sys/class/leds/ -name \"*:power\" | head -n1)\n\tif [ -d \"$status_led_file\" ]; then\n\t\tbasename $status_led_file\n\t\treturn\n\tfi;\n}\n\nget_failsafe_led() {\n\tlocal status_led_file\n\n\tstatus_led_file=$(find /sys/class/leds/ -name \"*:fault\" | head -n1)\n\tif [ -d \"$status_led_file\" ]; then\n\t\tbasename $status_led_file\n\t\treturn\n\tfi;\n}\n\nset_state() {\n\tstatus_led=$(get_status_led)\n\n\t[ -z \"$status_led\" ] && return\n\n\tcase \"$1\" in\n\tpreinit)\n\t\tstatus_led_blink_preinit\n\t\t;;\n\tfailsafe)\n\t\tstatus_led_off\n\t\tstatus_led=$(get_failsafe_led)\n\t\tstatus_led_blink_failsafe\n\t\t;;\n\tpreinit_regular)\n\t\tstatus_led_blink_preinit_regular\n\t\t;;\n        upgrade)\n                status_led_blink_preinit_regular\n                ;;\n\tdone)\n\t\tstatus_led_on\n\t\t;;\n\tesac\n}\n"
  },
  {
    "path": "target/linux/apm821xx/base-files/etc/hotplug.d/ieee80211/10_fix_wifi_mac",
    "content": "#!/bin/ash\n\n[ \"$ACTION\" = \"add\" ] || exit 0\n\nPHYNBR=${DEVPATH##*/phy}\n\n[ -n \"$PHYNBR\" ] || exit 0\n\n. /lib/functions.sh\n. /lib/functions/system.sh\n\nboard=$(board_name)\n\ncase \"$board\" in\nnetgear,wndap620|\\\nnetgear,wndap660)\n\tmacaddr_add $(mtd_get_mac_ascii u-boot-env baseMAC) $(($PHYNBR + 1)) > /sys${DEVPATH}/macaddress\n\t;;\nesac\n"
  },
  {
    "path": "target/linux/apm821xx/base-files/etc/init.d/hwmon_fancontrol",
    "content": "#!/bin/sh /etc/rc.common\n\nSTART=98\n\nboot() {\n\t# configuring onboard temp/fan controller to run the fan on its own\n\t# for more information, please read https://www.kernel.org/doc/Documentation/hwmon/sysfs-interface\n\n\tcase $(board_name) in\n\tnetgear,wndr4700)\n\t\tpath_to_hwmon='/sys/devices/platform/plb/plb:opb/4ef600700.i2c/i2c-0/0-001b/hwmon/hwmon1'\n\t\techo 1 > \"$path_to_hwmon/pwm1_enable\"\n\t\t;;\n\tesac\n}\n"
  },
  {
    "path": "target/linux/apm821xx/base-files/etc/inittab",
    "content": "::sysinit:/etc/init.d/rcS S boot\n::shutdown:/etc/init.d/rcS K shutdown\n::askconsole:/usr/libexec/login.sh\nttyS0::askfirst:/usr/libexec/login.sh\n"
  },
  {
    "path": "target/linux/apm821xx/base-files/etc/uci-defaults/04_led_migration",
    "content": ". /lib/functions.sh\n. /lib/functions/migrations.sh\n\nboard=$(board_name)\n\ncase \"$board\" in\nmeraki,mr24)\n\tmigrate_leds \"orange:power=amber:fault\" \\\n\t\t\":wifi1=:wlan-0\" \\\n\t\t\":wifi2=:wlan-1\" \\\n\t\t\":wifi3=:wlan-2\" \\\n\t\t\":wifi4=:wlan-3\"\n\t;;\nmeraki,mx60)\n\tmigrate_leds \":lan1=:lan-0\" \\\n\t\t\":lan2=:lan-1\" \\\n\t\t\":lan3=:lan-2\" \\\n\t\t\":lan4=:lan-3\" \\\n\t\t\"orange:power=amber:power\" \\\n\t\t\"orange:wan=amber:wan\"\n\t;;\nnetgear,wndap620)\n\tmigrate_leds \":activity=:lan-0\" \\\n\t\t\":test=:fault\" \\\n\t\t\":wlan2g=:wlan-0\" \\\n\t\t\":wlan5g=:wlan-1\" \\\n\t\t\":link100=:lan\" \\\n\t\t\":link1000=:lan-1\"\n\t;;\nnetgear,wndap660)\n\tmigrate_leds \":activity=:lan-0\" \\\n\t\t\":test=:fault\" \\\n\t\t\":wlan2g=:wlan-0\" \\\n\t\t\":wlan5g=:wlan-1\" \\\n\t\t\":lan1-link100=:lan-0\" \\\n\t\t\":lan1-link1000=:lan-1\" \\\n\t\t\":lan2-link100=:lan-1\" \\\n\t\t\":lan2-link1000=:lan-2\"\n\t;;\nnetgear,wndr4700)\n\tmigrate_leds \"orange:power=amber:fault\" \\\n\t\t\"white:logo=white:indicator\" \\\n\t\t\"green:hd=green:disk\" \\\n\t\t\"red:hd=red:disk-err\"\n\t;;\nwd,mybooklive)\n\tmigrate_leds \"red:power=red:fault\" \\\n\t\t\"blue:power=blue:disk\"\n\t;;\nesac\n\nremove_devicename_leds\n\nmigrations_apply system\n\nexit 0\n"
  },
  {
    "path": "target/linux/apm821xx/base-files/etc/uci-defaults/05_fix-compat-version",
    "content": ". /lib/functions.sh\n\ncase \"$(board_name)\" in\nmeraki,mx60|\\\nnetgear,wndap620|\\\nnetgear,wndap660)\n\tuci set system.@system[0].compat_version=\"2.0\"\n\tuci commit system\n\t;;\nesac\n\nexit 0\n"
  },
  {
    "path": "target/linux/apm821xx/base-files/lib/preinit/05_set_iface_mac_apm821xx",
    "content": "preinit_set_mac_address() {\n\t. /lib/functions.sh\n\n\tcase $(board_name) in\n\t\tmeraki,mr24|\\\n\t\tmeraki,mx60)\n\t\t\tmac_lan=$(mtd_get_mac_binary_ubi board-config 0x66)\n\t\t\t[ -n \"$mac_lan\" ] && ip link set eth0 address \"$mac_lan\"\n\t\t\t;;\n\tesac\n}\n\nboot_hook_add preinit_main preinit_set_mac_address\n"
  },
  {
    "path": "target/linux/apm821xx/base-files/lib/preinit/05_set_preinit_iface_apm821xx",
    "content": "apm821xx_set_preinit_iface() {\n\tifname=eth0\n}\n\nboot_hook_add preinit_main apm821xx_set_preinit_iface\n"
  },
  {
    "path": "target/linux/apm821xx/base-files/lib/preinit/79_move_config",
    "content": "BOOTPART=/dev/sda1\n\nmove_config() {\n\t. /lib/functions.sh\n\t. /lib/upgrade/common.sh\n\n\tcase \"$(board_name)\" in\n\twd,mybooklive)\n\t\tif [ -b $BOOTPART ]; then\n\t\t\tmkdir -p /boot\n\t\t\tmount -t ext4 -o rw,noatime $BOOTPART /boot\n\t\t\t[ -f \"/boot/$BACKUP_FILE\" ] && mv -f \"/boot/$BACKUP_FILE\" /\n\t\tfi\n\t\t;;\n\tesac\n}\n\nboot_hook_add preinit_mount_root move_config\n"
  },
  {
    "path": "target/linux/apm821xx/base-files/lib/upgrade/platform.sh",
    "content": "PART_NAME=firmware\nREQUIRE_IMAGE_METADATA=1\n\nplatform_check_image() {\n\tlocal board=$(board_name)\n\n\tcase \"$board\" in\n\twd,mybooklive)\n\t\tmbl_do_platform_check \"$1\"\n\t\treturn $?;\n\t\t;;\n\t*)\n\t\treturn 0\n\t\t;;\n\tesac\n}\n\nplatform_do_upgrade() {\n\tlocal board=$(board_name)\n\n\tcase \"$board\" in\n\twd,mybooklive)\n\t\tmbl_do_upgrade \"$1\"\n\t\t;;\n\tmeraki,mr24|\\\n\tmeraki,mx60|\\\n\tnetgear,wndap620|\\\n\tnetgear,wndap660|\\\n\tnetgear,wndr4700)\n\t\tnand_do_upgrade \"$1\"\n\t\t;;\n\t*)\n\t\tdefault_do_upgrade \"$1\"\n\t\t;;\n\tesac\n}\n\nplatform_copy_config() {\n\tlocal board=$(board_name)\n\n\tcase \"$board\" in\n\twd,mybooklive|\\\n\twd,mybooklive-duo)\n\t\tmbl_copy_config\n\t\t;;\n\tesac\n}\n"
  },
  {
    "path": "target/linux/apm821xx/base-files/lib/upgrade/wdbook.sh",
    "content": ". /lib/functions.sh\n\n# copied from x86's platform.sh\n\nmbl_do_platform_check() {\n\tlocal diskdev partdev diff\n\n\t[ \"$#\" -gt 1 ] && return 1\n\n\texport_bootdevice && export_partdevice diskdev 0 || {\n\t\techo \"Unable to determine upgrade device\"\n\t\treturn 1\n\t}\n\n\tget_partitions \"/dev/$diskdev\" bootdisk\n\n\t#extract the boot sector from the image\n\tget_image \"$@\" | dd of=/tmp/image.bs count=1 bs=512b 2>/dev/null\n\n\tget_partitions /tmp/image.bs image\n\n\t#compare tables\n\tdiff=\"$(grep -F -x -v -f /tmp/partmap.bootdisk /tmp/partmap.image)\"\n\n\trm -f /tmp/image.bs /tmp/partmap.bootdisk /tmp/partmap.image\n\n\tif [ -n \"$diff\" ]; then\n\t\techo \"Partition layout has changed. Full image will be written.\"\n\t\task_bool 0 \"Abort\" && exit 1\n\t\treturn 0\n\tfi\n\n\treturn 0;\n}\n\nmbl_do_upgrade() {\n\tlocal diskdev partdev diff\n\n\texport_bootdevice && export_partdevice diskdev 0 || {\n\t\techo \"Unable to determine upgrade device\"\n\t\treturn 1\n\t}\n\n\tsync\n\n\tif [ \"$UPGRADE_OPT_SAVE_PARTITIONS\" = \"1\" ]; then\n\t\tget_partitions \"/dev/$diskdev\" bootdisk\n\n\t\t#extract the boot sector from the image\n\t\tget_image \"$@\" | dd of=/tmp/image.bs count=1 bs=512b\n\n\t\tget_partitions /tmp/image.bs image\n\n\t\t#compare tables\n\t\tdiff=\"$(grep -F -x -v -f /tmp/partmap.bootdisk /tmp/partmap.image)\"\n\telse\n\t\tdiff=1\n\tfi\n\n\tif [ -n \"$diff\" ]; then\n\t\tget_image \"$@\" | dd of=\"/dev/$diskdev\" bs=4096 conv=fsync\n\n\t\t# Separate removal and addtion is necessary; otherwise, partition 1\n\t\t# will be missing if it overlaps with the old partition 2\n\t\tpartx -d - \"/dev/$diskdev\"\n\t\tpartx -a - \"/dev/$diskdev\"\n\n\t\treturn 0\n\tfi\n\n\t#iterate over each partition from the image and write it to the boot disk\n\twhile read part start size; do\n\t\tif export_partdevice partdev $part; then\n\t\t\techo \"Writing image to /dev/$partdev...\"\n\t\t\tget_image \"$@\" | dd of=\"/dev/$partdev\" ibs=\"512\" obs=1M skip=\"$start\" count=\"$size\" conv=fsync\n\t\telse\n\t\t\techo \"Unable to find partition $part device, skipped.\"\n\tfi\n\tdone < /tmp/partmap.image\n\n\t#copy partition uuid\n\techo \"Writing new UUID to /dev/$diskdev...\"\n\tget_image \"$@\" | dd of=\"/dev/$diskdev\" bs=1 skip=440 count=4 seek=440 conv=fsync\n}\n\nmbl_copy_config() {\n\tlocal partdev\n\n\tif export_partdevice partdev 1; then\n\t\tmount -t ext4 -o rw,noatime \"/dev/$partdev\" /mnt\n\t\tcp -af \"$UPGRADE_BACKUP\" \"/mnt/$BACKUP_FILE\"\n\t\tumount /mnt\n\tfi\n}\n"
  },
  {
    "path": "target/linux/apm821xx/config-5.10",
    "content": "# CONFIG_40x is not set\nCONFIG_44x=y\nCONFIG_4xx=y\nCONFIG_4xx_SOC=y\n# CONFIG_ADVANCED_OPTIONS is not set\nCONFIG_APM821xx=y\n# CONFIG_APOLLO3G is not set\n# CONFIG_ARCHES is not set\nCONFIG_ARCH_32BIT_OFF_T=y\nCONFIG_ARCH_DMA_ADDR_T_64BIT=y\nCONFIG_ARCH_HIBERNATION_POSSIBLE=y\nCONFIG_ARCH_KEEP_MEMBLOCK=y\nCONFIG_ARCH_MAY_HAVE_PC_FDC=y\nCONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y\nCONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y\nCONFIG_ARCH_MMAP_RND_BITS=11\nCONFIG_ARCH_MMAP_RND_BITS_MAX=17\nCONFIG_ARCH_MMAP_RND_BITS_MIN=11\nCONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=17\nCONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11\nCONFIG_ARCH_OPTIONAL_KERNEL_RWX=y\nCONFIG_ARCH_SUSPEND_POSSIBLE=y\nCONFIG_ARCH_WEAK_RELEASE_ACQUIRE=y\nCONFIG_AUDIT_ARCH=y\n# CONFIG_BAMBOO is not set\n# CONFIG_BLK_DEV_INITRD is not set\nCONFIG_BLK_MQ_PCI=y\nCONFIG_BLUESTONE=y\nCONFIG_BOOKE=y\nCONFIG_BOOKE_WDT=y\n# CONFIG_CANYONLANDS is not set\nCONFIG_CLKDEV_LOOKUP=y\nCONFIG_CLONE_BACKWARDS=y\nCONFIG_CMDLINE=\"rootfstype=squashfs noinitrd\"\nCONFIG_CMDLINE_FROM_BOOTLOADER=y\nCONFIG_COMMON_CLK=y\nCONFIG_COMPAT_32BIT_TIME=y\nCONFIG_CPU_BIG_ENDIAN=y\nCONFIG_CRC16=y\n# CONFIG_CRC32_SARWATE is not set\nCONFIG_CRC32_SLICEBY8=y\nCONFIG_CRYPTO_DEFLATE=y\nCONFIG_CRYPTO_DEV_PPC4XX=y\nCONFIG_CRYPTO_HW=y\nCONFIG_CRYPTO_JITTERENTROPY=y\nCONFIG_CRYPTO_LIB_POLY1305_RSIZE=1\nCONFIG_CRYPTO_LIB_SHA256=y\nCONFIG_CRYPTO_LZO=y\n# CONFIG_CRYPTO_MD5_PPC is not set\nCONFIG_CRYPTO_RNG=y\nCONFIG_CRYPTO_RNG2=y\n# CONFIG_CRYPTO_SHA1_PPC is not set\nCONFIG_DATA_SHIFT=12\nCONFIG_DMADEVICES=y\nCONFIG_DMA_DIRECT_REMAP=y\nCONFIG_DMA_ENGINE=y\nCONFIG_DMA_OF=y\nCONFIG_DMA_REMAP=y\nCONFIG_DTC=y\nCONFIG_DW_DMAC=y\nCONFIG_DW_DMAC_CORE=y\n# CONFIG_E200 is not set\nCONFIG_EARLY_PRINTK=y\n# CONFIG_EBONY is not set\nCONFIG_EDAC_ATOMIC_SCRUB=y\nCONFIG_EDAC_SUPPORT=y\n# CONFIG_EIGER is not set\nCONFIG_EXTRA_TARGETS=\"uImage\"\nCONFIG_FIXED_PHY=y\nCONFIG_FORCE_PCI=y\n# CONFIG_FSL_LBC is not set\nCONFIG_FW_LOADER_PAGED_BUF=y\nCONFIG_GENERIC_ALLOCATOR=y\nCONFIG_GENERIC_ATOMIC64=y\nCONFIG_GENERIC_BUG=y\nCONFIG_GENERIC_CLOCKEVENTS=y\nCONFIG_GENERIC_CMOS_UPDATE=y\nCONFIG_GENERIC_CPU=y\nCONFIG_GENERIC_CPU_AUTOPROBE=y\nCONFIG_GENERIC_EARLY_IOREMAP=y\nCONFIG_GENERIC_IRQ_SHOW=y\nCONFIG_GENERIC_IRQ_SHOW_LEVEL=y\nCONFIG_GENERIC_ISA_DMA=y\nCONFIG_GENERIC_MSI_IRQ=y\nCONFIG_GENERIC_MSI_IRQ_DOMAIN=y\nCONFIG_GENERIC_PCI_IOMAP=y\nCONFIG_GENERIC_SMP_IDLE_THREAD=y\nCONFIG_GENERIC_STRNCPY_FROM_USER=y\nCONFIG_GENERIC_STRNLEN_USER=y\nCONFIG_GENERIC_TIME_VSYSCALL=y\n# CONFIG_GEN_RTC is not set\n# CONFIG_GLACIER is not set\nCONFIG_GPIOLIB=y\nCONFIG_GPIO_GENERIC=y\nCONFIG_GPIO_GENERIC_PLATFORM=y\nCONFIG_HAS_DMA=y\nCONFIG_HAS_IOMEM=y\nCONFIG_HAS_IOPORT_MAP=y\nCONFIG_HW_RANDOM=y\nCONFIG_HW_RANDOM_PPC4XX=y\nCONFIG_I2C=y\nCONFIG_I2C_BOARDINFO=y\nCONFIG_I2C_CHARDEV=y\nCONFIG_I2C_IBM_IIC=y\nCONFIG_IBM_EMAC=y\nCONFIG_IBM_EMAC_EMAC4=y\nCONFIG_IBM_EMAC_POLL_WEIGHT=32\nCONFIG_IBM_EMAC_RGMII=y\nCONFIG_IBM_EMAC_RXB=128\nCONFIG_IBM_EMAC_RX_COPY_THRESHOLD=256\nCONFIG_IBM_EMAC_TAH=y\nCONFIG_IBM_EMAC_TXB=128\n# CONFIG_ICON is not set\nCONFIG_ILLEGAL_POINTER_VALUE=0\nCONFIG_IRQCHIP=y\nCONFIG_IRQ_DOMAIN=y\nCONFIG_IRQ_DOMAIN_HIERARCHY=y\nCONFIG_IRQ_FORCED_THREADING=y\nCONFIG_IRQ_WORK=y\nCONFIG_ISA_DMA_API=y\n# CONFIG_JFFS2_FS is not set\n# CONFIG_KATMAI is not set\nCONFIG_KERNEL_START=0xc0000000\nCONFIG_LEDS_TRIGGER_MTD=y\nCONFIG_LEDS_TRIGGER_PATTERN=y\nCONFIG_LIBFDT=y\nCONFIG_LOCK_DEBUGGING_SUPPORT=y\nCONFIG_LOWMEM_SIZE=0x30000000\nCONFIG_LZO_COMPRESS=y\nCONFIG_LZO_DECOMPRESS=y\n# CONFIG_MATH_EMULATION is not set\nCONFIG_MDIO_BUS=y\nCONFIG_MDIO_DEVICE=y\nCONFIG_MDIO_DEVRES=y\nCONFIG_MEMFD_CREATE=y\nCONFIG_MIGRATION=y\nCONFIG_MMU_GATHER_PAGE_SIZE=y\nCONFIG_MODULES_USE_ELF_RELA=y\nCONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS=y\nCONFIG_MTD_CFI_ADV_OPTIONS=y\n# CONFIG_MTD_CFI_GEOMETRY is not set\n# CONFIG_MTD_SPLIT_SQUASHFS_ROOT is not set\nCONFIG_NEED_DMA_MAP_STATE=y\nCONFIG_NEED_PER_CPU_KM=y\nCONFIG_NEED_SG_DMA_LENGTH=y\nCONFIG_NOT_COHERENT_CACHE=y\nCONFIG_NO_HZ=y\nCONFIG_NO_HZ_COMMON=y\nCONFIG_NO_HZ_IDLE=y\nCONFIG_NR_IRQS=512\nCONFIG_NVMEM=y\nCONFIG_NVMEM_SYSFS=y\nCONFIG_OF=y\nCONFIG_OF_ADDRESS=y\nCONFIG_OF_EARLY_FLATTREE=y\nCONFIG_OF_FLATTREE=y\nCONFIG_OF_GPIO=y\nCONFIG_OF_IRQ=y\nCONFIG_OF_KOBJ=y\nCONFIG_OF_MDIO=y\nCONFIG_OF_NET=y\nCONFIG_OLD_SIGACTION=y\nCONFIG_OLD_SIGSUSPEND=y\nCONFIG_PACKING=y\nCONFIG_PAGE_OFFSET=0xc0000000\nCONFIG_PCI=y\nCONFIG_PCIEAER=y\nCONFIG_PCIEPORTBUS=y\nCONFIG_PCI_DISABLE_COMMON_QUIRKS=y\nCONFIG_PCI_DOMAINS=y\nCONFIG_PCI_MSI=y\nCONFIG_PCI_MSI_ARCH_FALLBACKS=y\nCONFIG_PCI_MSI_IRQ_DOMAIN=y\nCONFIG_PGTABLE_LEVELS=2\nCONFIG_PHYLIB=y\nCONFIG_PHYSICAL_START=0x00000000\nCONFIG_PHYS_64BIT=y\nCONFIG_PHYS_ADDR_T_64BIT=y\n# CONFIG_PMU_SYSFS is not set\nCONFIG_PPC=y\nCONFIG_PPC32=y\nCONFIG_PPC44x_SIMPLE=y\nCONFIG_PPC4xx_GPIO=y\nCONFIG_PPC4xx_MSI=y\nCONFIG_PPC4xx_PCI_EXPRESS=y\n# CONFIG_PPC64 is not set\n# CONFIG_PPC_47x is not set\n# CONFIG_PPC_85xx is not set\n# CONFIG_PPC_8xx is not set\nCONFIG_PPC_ADV_DEBUG_DACS=2\nCONFIG_PPC_ADV_DEBUG_DAC_RANGE=y\nCONFIG_PPC_ADV_DEBUG_DVCS=2\nCONFIG_PPC_ADV_DEBUG_IACS=4\nCONFIG_PPC_ADV_DEBUG_REGS=y\n# CONFIG_PPC_BOOK3S_6xx is not set\nCONFIG_PPC_DCR=y\nCONFIG_PPC_DCR_NATIVE=y\n# CONFIG_PPC_EARLY_DEBUG is not set\nCONFIG_PPC_FPU=y\nCONFIG_PPC_INDIRECT_PCI=y\n# CONFIG_PPC_IRQ_SOFT_MASK_DEBUG is not set\nCONFIG_PPC_MMU_NOHASH=y\nCONFIG_PPC_MMU_NOHASH_32=y\nCONFIG_PPC_MSI_BITMAP=y\nCONFIG_PPC_PAGE_SHIFT=12\n# CONFIG_PPC_PTDUMP is not set\nCONFIG_PPC_UDBG_16550=y\nCONFIG_PPC_WERROR=y\nCONFIG_PTE_64BIT=y\n# CONFIG_RAINIER is not set\nCONFIG_RAS=y\nCONFIG_RATIONAL=y\nCONFIG_REGULATOR=y\nCONFIG_RSEQ=y\n# CONFIG_SAM440EP is not set\n# CONFIG_SCOM_DEBUGFS is not set\n# CONFIG_SEQUOIA is not set\nCONFIG_SERIAL_8250_FSL=y\nCONFIG_SERIAL_MCTRL_GPIO=y\nCONFIG_SERIAL_OF_PLATFORM=y\nCONFIG_SGL_ALLOC=y\nCONFIG_SPARSE_IRQ=y\nCONFIG_SRCU=y\nCONFIG_SWPHY=y\nCONFIG_SYSCTL_EXCEPTION_TRACE=y\n# CONFIG_TAISHAN is not set\nCONFIG_TASK_SIZE=0xc0000000\nCONFIG_THREAD_INFO_IN_TASK=y\nCONFIG_THREAD_SHIFT=13\nCONFIG_TICK_CPU_ACCOUNTING=y\nCONFIG_TINY_SRCU=y\nCONFIG_USB_SUPPORT=y\nCONFIG_VDSO32=y\n# CONFIG_VIRTIO_MENU is not set\n# CONFIG_VIRT_CPU_ACCOUNTING_NATIVE is not set\n# CONFIG_WARP is not set\nCONFIG_WATCHDOG_CORE=y\n# CONFIG_XILINX_SYSACE is not set\nCONFIG_XZ_DEC_BCJ=y\nCONFIG_XZ_DEC_POWERPC=y\n# CONFIG_YOSEMITE is not set\nCONFIG_ZLIB_DEFLATE=y\nCONFIG_ZLIB_INFLATE=y\n"
  },
  {
    "path": "target/linux/apm821xx/config-5.15",
    "content": "# CONFIG_40x is not set\nCONFIG_44x=y\nCONFIG_4xx=y\nCONFIG_4xx_SOC=y\n# CONFIG_ADVANCED_OPTIONS is not set\nCONFIG_APM821xx=y\n# CONFIG_APOLLO3G is not set\n# CONFIG_ARCHES is not set\nCONFIG_ARCH_32BIT_OFF_T=y\nCONFIG_ARCH_DMA_ADDR_T_64BIT=y\nCONFIG_ARCH_HIBERNATION_POSSIBLE=y\nCONFIG_ARCH_KEEP_MEMBLOCK=y\nCONFIG_ARCH_MAY_HAVE_PC_FDC=y\nCONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y\nCONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y\nCONFIG_ARCH_MMAP_RND_BITS=11\nCONFIG_ARCH_MMAP_RND_BITS_MAX=17\nCONFIG_ARCH_MMAP_RND_BITS_MIN=11\nCONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=17\nCONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11\nCONFIG_ARCH_STACKWALK=y\nCONFIG_ARCH_SUSPEND_POSSIBLE=y\nCONFIG_ARCH_WEAK_RELEASE_ACQUIRE=y\nCONFIG_AUDIT_ARCH=y\n# CONFIG_BAMBOO is not set\n# CONFIG_BLK_DEV_INITRD is not set\nCONFIG_BLK_MQ_PCI=y\nCONFIG_BLUESTONE=y\nCONFIG_BOOKE=y\nCONFIG_BOOKE_WDT=y\n# CONFIG_CANYONLANDS is not set\nCONFIG_CLONE_BACKWARDS=y\nCONFIG_CMDLINE=\"rootfstype=squashfs noinitrd\"\nCONFIG_CMDLINE_FROM_BOOTLOADER=y\nCONFIG_COMMON_CLK=y\nCONFIG_COMPAT_32BIT_TIME=y\nCONFIG_CPU_BIG_ENDIAN=y\nCONFIG_CRC16=y\n# CONFIG_CRC32_SARWATE is not set\nCONFIG_CRC32_SLICEBY8=y\nCONFIG_CRYPTO_DEFLATE=y\nCONFIG_CRYPTO_DEV_PPC4XX=y\nCONFIG_CRYPTO_HW=y\nCONFIG_CRYPTO_JITTERENTROPY=y\nCONFIG_CRYPTO_LIB_POLY1305_RSIZE=1\nCONFIG_CRYPTO_LZO=y\n# CONFIG_CRYPTO_MD5_PPC is not set\nCONFIG_CRYPTO_RNG=y\nCONFIG_CRYPTO_RNG2=y\n# CONFIG_CRYPTO_SHA1_PPC is not set\nCONFIG_DATA_SHIFT=12\nCONFIG_DMADEVICES=y\nCONFIG_DMA_DIRECT_REMAP=y\nCONFIG_DMA_ENGINE=y\nCONFIG_DMA_OF=y\nCONFIG_DMA_REMAP=y\nCONFIG_DTC=y\nCONFIG_DW_DMAC=y\nCONFIG_DW_DMAC_CORE=y\nCONFIG_EARLY_PRINTK=y\n# CONFIG_EBONY is not set\nCONFIG_EDAC_ATOMIC_SCRUB=y\nCONFIG_EDAC_SUPPORT=y\n# CONFIG_EIGER is not set\nCONFIG_EXTRA_TARGETS=\"uImage\"\nCONFIG_FIXED_PHY=y\nCONFIG_FORCE_PCI=y\n# CONFIG_FSL_LBC is not set\nCONFIG_FWNODE_MDIO=y\nCONFIG_FW_LOADER_PAGED_BUF=y\nCONFIG_GENERIC_ALLOCATOR=y\nCONFIG_GENERIC_ATOMIC64=y\nCONFIG_GENERIC_BUG=y\nCONFIG_GENERIC_BUG_RELATIVE_POINTERS=y\nCONFIG_GENERIC_CLOCKEVENTS=y\nCONFIG_GENERIC_CMOS_UPDATE=y\nCONFIG_GENERIC_CPU=y\nCONFIG_GENERIC_CPU_AUTOPROBE=y\nCONFIG_GENERIC_EARLY_IOREMAP=y\nCONFIG_GENERIC_GETTIMEOFDAY=y\nCONFIG_GENERIC_IRQ_SHOW=y\nCONFIG_GENERIC_IRQ_SHOW_LEVEL=y\nCONFIG_GENERIC_ISA_DMA=y\nCONFIG_GENERIC_MSI_IRQ=y\nCONFIG_GENERIC_MSI_IRQ_DOMAIN=y\nCONFIG_GENERIC_PCI_IOMAP=y\nCONFIG_GENERIC_SMP_IDLE_THREAD=y\nCONFIG_GENERIC_STRNCPY_FROM_USER=y\nCONFIG_GENERIC_STRNLEN_USER=y\nCONFIG_GENERIC_TIME_VSYSCALL=y\n# CONFIG_GEN_RTC is not set\n# CONFIG_GLACIER is not set\nCONFIG_GPIOLIB=y\nCONFIG_GPIO_CDEV=y\nCONFIG_GPIO_GENERIC=y\nCONFIG_GPIO_GENERIC_PLATFORM=y\nCONFIG_HAS_DMA=y\nCONFIG_HAS_IOMEM=y\nCONFIG_HAS_IOPORT_MAP=y\nCONFIG_HW_RANDOM=y\nCONFIG_HW_RANDOM_PPC4XX=y\nCONFIG_I2C=y\nCONFIG_I2C_BOARDINFO=y\nCONFIG_I2C_CHARDEV=y\nCONFIG_I2C_IBM_IIC=y\nCONFIG_IBM_EMAC=y\nCONFIG_IBM_EMAC_EMAC4=y\nCONFIG_IBM_EMAC_POLL_WEIGHT=32\nCONFIG_IBM_EMAC_RGMII=y\nCONFIG_IBM_EMAC_RXB=128\nCONFIG_IBM_EMAC_RX_COPY_THRESHOLD=256\nCONFIG_IBM_EMAC_TAH=y\nCONFIG_IBM_EMAC_TXB=128\n# CONFIG_ICON is not set\nCONFIG_ILLEGAL_POINTER_VALUE=0\nCONFIG_IRQCHIP=y\nCONFIG_IRQ_DOMAIN=y\nCONFIG_IRQ_DOMAIN_HIERARCHY=y\nCONFIG_IRQ_FORCED_THREADING=y\nCONFIG_IRQ_WORK=y\nCONFIG_ISA_DMA_API=y\n# CONFIG_JFFS2_FS is not set\n# CONFIG_KATMAI is not set\nCONFIG_KERNEL_START=0xc0000000\nCONFIG_LEDS_TRIGGER_MTD=y\nCONFIG_LEDS_TRIGGER_PATTERN=y\nCONFIG_LIBFDT=y\nCONFIG_LOCK_DEBUGGING_SUPPORT=y\nCONFIG_LOWMEM_SIZE=0x30000000\nCONFIG_LZO_COMPRESS=y\nCONFIG_LZO_DECOMPRESS=y\n# CONFIG_MATH_EMULATION is not set\nCONFIG_MDIO_BUS=y\nCONFIG_MDIO_DEVICE=y\nCONFIG_MDIO_DEVRES=y\nCONFIG_MEMFD_CREATE=y\nCONFIG_MIGRATION=y\nCONFIG_MMU_GATHER_PAGE_SIZE=y\nCONFIG_MODULES_USE_ELF_RELA=y\nCONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS=y\nCONFIG_MTD_CFI_ADV_OPTIONS=y\n# CONFIG_MTD_CFI_GEOMETRY is not set\n# CONFIG_MTD_SPLIT_SQUASHFS_ROOT is not set\nCONFIG_NEED_DMA_MAP_STATE=y\nCONFIG_NEED_PER_CPU_KM=y\nCONFIG_NEED_SG_DMA_LENGTH=y\nCONFIG_NET_SELFTESTS=y\nCONFIG_NOT_COHERENT_CACHE=y\nCONFIG_NO_HZ=y\nCONFIG_NO_HZ_COMMON=y\nCONFIG_NO_HZ_IDLE=y\nCONFIG_NR_CPUS=1\nCONFIG_NR_IRQS=512\nCONFIG_NVMEM=y\nCONFIG_NVMEM_SYSFS=y\nCONFIG_OF=y\nCONFIG_OF_ADDRESS=y\nCONFIG_OF_EARLY_FLATTREE=y\nCONFIG_OF_FLATTREE=y\nCONFIG_OF_GPIO=y\nCONFIG_OF_IRQ=y\nCONFIG_OF_KOBJ=y\nCONFIG_OF_MDIO=y\nCONFIG_OLD_SIGACTION=y\nCONFIG_OLD_SIGSUSPEND=y\nCONFIG_PACKING=y\nCONFIG_PAGE_OFFSET=0xc0000000\nCONFIG_PCI=y\nCONFIG_PCIEAER=y\nCONFIG_PCIEPORTBUS=y\nCONFIG_PCI_DISABLE_COMMON_QUIRKS=y\nCONFIG_PCI_DOMAINS=y\nCONFIG_PCI_MSI=y\nCONFIG_PCI_MSI_ARCH_FALLBACKS=y\nCONFIG_PCI_MSI_IRQ_DOMAIN=y\nCONFIG_PGTABLE_LEVELS=2\nCONFIG_PHYLIB=y\nCONFIG_PHYSICAL_START=0x00000000\nCONFIG_PHYS_64BIT=y\nCONFIG_PHYS_ADDR_T_64BIT=y\n# CONFIG_PMU_SYSFS is not set\nCONFIG_PPC=y\nCONFIG_PPC32=y\nCONFIG_PPC44x_SIMPLE=y\nCONFIG_PPC4xx_GPIO=y\nCONFIG_PPC4xx_MSI=y\nCONFIG_PPC4xx_PCI_EXPRESS=y\n# CONFIG_PPC64 is not set\n# CONFIG_PPC_47x is not set\n# CONFIG_PPC_85xx is not set\n# CONFIG_PPC_8xx is not set\nCONFIG_PPC_ADV_DEBUG_DACS=2\nCONFIG_PPC_ADV_DEBUG_DAC_RANGE=y\nCONFIG_PPC_ADV_DEBUG_DVCS=2\nCONFIG_PPC_ADV_DEBUG_IACS=4\nCONFIG_PPC_ADV_DEBUG_REGS=y\n# CONFIG_PPC_BOOK3S_32 is not set\nCONFIG_PPC_DCR=y\nCONFIG_PPC_DCR_NATIVE=y\n# CONFIG_PPC_EARLY_DEBUG is not set\nCONFIG_PPC_FPU=y\nCONFIG_PPC_FPU_REGS=y\nCONFIG_PPC_HAVE_KUEP=y\nCONFIG_PPC_INDIRECT_PCI=y\nCONFIG_PPC_KUEP=y\nCONFIG_PPC_MMU_NOHASH=y\nCONFIG_PPC_MSI_BITMAP=y\nCONFIG_PPC_PAGE_SHIFT=12\nCONFIG_PPC_UDBG_16550=y\nCONFIG_PPC_WERROR=y\nCONFIG_PTE_64BIT=y\nCONFIG_PTP_1588_CLOCK_OPTIONAL=y\n# CONFIG_RAINIER is not set\nCONFIG_RAS=y\nCONFIG_RATIONAL=y\nCONFIG_REGULATOR=y\nCONFIG_RSEQ=y\n# CONFIG_SAM440EP is not set\n# CONFIG_SCOM_DEBUGFS is not set\n# CONFIG_SEQUOIA is not set\nCONFIG_SERIAL_8250_FSL=y\nCONFIG_SERIAL_MCTRL_GPIO=y\nCONFIG_SERIAL_OF_PLATFORM=y\nCONFIG_SGL_ALLOC=y\nCONFIG_SPARSE_IRQ=y\nCONFIG_SRCU=y\nCONFIG_SWPHY=y\nCONFIG_SYSCTL_EXCEPTION_TRACE=y\n# CONFIG_TAISHAN is not set\nCONFIG_TASK_SIZE=0xc0000000\nCONFIG_THREAD_INFO_IN_TASK=y\nCONFIG_THREAD_SHIFT=13\nCONFIG_TICK_CPU_ACCOUNTING=y\nCONFIG_TINY_SRCU=y\nCONFIG_USB_SUPPORT=y\nCONFIG_VDSO32=y\n# CONFIG_VIRTIO_MENU is not set\n# CONFIG_VIRT_CPU_ACCOUNTING_NATIVE is not set\n# CONFIG_WARP is not set\nCONFIG_WATCHDOG_CORE=y\nCONFIG_XZ_DEC_BCJ=y\nCONFIG_XZ_DEC_POWERPC=y\n# CONFIG_YOSEMITE is not set\nCONFIG_ZLIB_DEFLATE=y\nCONFIG_ZLIB_INFLATE=y\n"
  },
  {
    "path": "target/linux/apm821xx/dts/apm82181.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later\n/*\n * Device Tree for Bluestone (APM821xx) board.\n *\n * Copyright (c) 2010, Applied Micro Circuits Corporation\n * Author: Tirumala R Marri <tmarri@apm.com>\n */\n\n#include <dt-bindings/dma/dw-dmac.h>\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/interrupt-controller/irq.h>\n#include <dt-bindings/gpio/gpio.h>\n\n/ {\n\t#address-cells = <2>;\n\t#size-cells = <1>;\n\tdcr-parent = <&{/cpus/cpu@0}>;\n\tcompatible = \"apm,bluestone\";\n\n\taliases {\n\t\tethernet0 = &EMAC0; /* needed for BSP u-boot */\n\t};\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tCPU0: cpu@0 {\n\t\t\tdevice_type = \"cpu\";\n\t\t\tmodel = \"PowerPC,apm82181\";\n\t\t\treg = <0x00000000>;\n\t\t\tclock-frequency = <0>; /* Filled in by U-Boot */\n\t\t\ttimebase-frequency = <0>; /* Filled in by U-Boot */\n\t\t\ti-cache-line-size = <32>;\n\t\t\td-cache-line-size = <32>;\n\t\t\ti-cache-size = <32768>;\n\t\t\td-cache-size = <32768>;\n\t\t\tdcr-controller;\n\t\t\tdcr-access-method = \"native\";\n\t\t\tnext-level-cache = <&L2C0>;\n\t\t};\n\t};\n\n\tmemory {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */\n\t};\n\n\tUIC0: interrupt-controller0 {\n\t\tcompatible = \"apm,uic-apm82181\", \"ibm,uic\";\n\t\tinterrupt-controller;\n\t\tcell-index = <0>;\n\t\tdcr-reg = <0x0c0 0x009>;\n\t\t#address-cells = <0>;\n\t\t#size-cells = <0>;\n\t\t#interrupt-cells = <2>;\n\t};\n\n\tUIC1: interrupt-controller1 {\n\t\tcompatible = \"apm,uic-apm82181\", \"ibm,uic\";\n\t\tinterrupt-controller;\n\t\tcell-index = <1>;\n\t\tdcr-reg = <0x0d0 0x009>;\n\t\t#address-cells = <0>;\n\t\t#size-cells = <0>;\n\t\t#interrupt-cells = <2>;\n\t\tinterrupts = <0x1e IRQ_TYPE_LEVEL_HIGH>,\n\t\t\t     <0x1f IRQ_TYPE_LEVEL_HIGH>; /* cascade */\n\t\tinterrupt-parent = <&UIC0>;\n\t};\n\n\tUIC2: interrupt-controller2 {\n\t\tcompatible = \"apm,uic-apm82181\", \"ibm,uic\";\n\t\tinterrupt-controller;\n\t\tcell-index = <2>;\n\t\tdcr-reg = <0x0e0 0x009>;\n\t\t#address-cells = <0>;\n\t\t#size-cells = <0>;\n\t\t#interrupt-cells = <2>;\n\t\tinterrupts = <0x0a IRQ_TYPE_LEVEL_HIGH>,\n\t\t\t     <0x0b IRQ_TYPE_LEVEL_HIGH>; /* cascade */\n\t\tinterrupt-parent = <&UIC0>;\n\t};\n\n\tUIC3: interrupt-controller3 {\n\t\tcompatible = \"apm,uic-apm82181\",\"ibm,uic\";\n\t\tinterrupt-controller;\n\t\tcell-index = <3>;\n\t\tdcr-reg = <0x0f0 0x009>;\n\t\t#address-cells = <0>;\n\t\t#size-cells = <0>;\n\t\t#interrupt-cells = <2>;\n\t\tinterrupts = <0x10 IRQ_TYPE_LEVEL_HIGH>,\n\t\t\t     <0x11 IRQ_TYPE_LEVEL_HIGH>; /* cascade */\n\t\tinterrupt-parent = <&UIC0>;\n\t};\n\n\tOCM1: ocm@400040000 {\n\t\tcompatible = \"apm,ocm-apm82181\", \"ibm,ocm\";\n\t\tstatus = \"okay\";\n\t\tcell-index = <1>;\n\t\t/* configured in U-Boot */\n\t\treg = <4 0x00040000 0x8000>; /* 32K */\n\t};\n\n\tSDR0: sdr {\n\t\tcompatible = \"apm,sdr-apm82181\", \"ibm,sdr-460ex\";\n\t\tdcr-reg = <0x00e 0x002>;\n\t};\n\n\tCPR0: cpr {\n\t\tcompatible = \"apm,cpr-apm82181\", \"ibm,cpr-460ex\";\n\t\tdcr-reg = <0x00c 0x002>;\n\t};\n\n\tL2C0: l2c {\n\t\tcompatible = \"ibm,l2-cache-apm82181\", \"ibm,l2-cache\";\n\t\tdcr-reg = <0x020 0x008\n\t\t\t   0x030 0x008>;\n\t\tcache-line-size = <32>;\n\t\tcache-size = <262144>;\n\t\tinterrupt-parent = <&UIC1>;\n\t\tinterrupts = <0x0b IRQ_TYPE_EDGE_RISING>;\n\t};\n\n\tCPM0: cpm {\n\t\tcompatible = \"ibm,cpm-apm821xx\", \"ibm,cpm\";\n\t\tcell-index = <0>;\n\t\tdcr-reg = <0x160 0x003>;\n\t\tpm-cpu = <0x02000000>;\n\t\tpm-doze = <0x302570F0>;\n\t\tpm-nap = <0x302570F0>;\n\t\tpm-deepsleep = <0x302570F0>;\n\t\tpm-iic-device = <&IIC0>;\n\t\tpm-emac-device = <&EMAC0>;\n\t\tunused-units = <0x00000100>;\n\t\tidle-doze = <0x02000000>;\n\t\tstandby = <0xfeff791d>;\n\t};\n\n\tplb {\n\t\tcompatible = \"apm,plb-apm82181\", \"ibm,plb-460ex\", \"ibm,plb4\";\n\t\t#address-cells = <2>;\n\t\t#size-cells = <1>;\n\t\tranges; /* Filled in by U-Boot */\n\t\tclock-frequency = <0>; /* Filled in by U-Boot */\n\n\t\tSDRAM0: sdram {\n\t\t\tcompatible = \"apm,sdram-apm82181\", \"ibm,sdram-460ex\", \"ibm,sdram-405gp\";\n\t\t\tdcr-reg = <0x010 0x002>;\n\t\t};\n\n\t\tRTC: rtc {\n\t\t\tcompatible = \"ibm,rtc\";\n\t\t\tdcr-reg = <0x240 0x009>;\n\t\t\tinterrupts = <0x1a IRQ_TYPE_LEVEL_HIGH>;\n\t\t\tinterrupt-parent = <&UIC2>;\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tTRNG: trng@110000 {\n\t\t\tcompatible = \"amcc,ppc460ex-rng\", \"ppc4xx-rng\", \"amcc, ppc4xx-trng\";\n\t\t\treg = <4 0x00110000 0x100>;\n\t\t\tinterrupt-parent = <&UIC1>;\n\t\t\tinterrupts = <0x03 IRQ_TYPE_LEVEL_HIGH>;\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tPKA: pka@114000 {\n\t\t\tcompatible = \"ppc4xx-pka\", \"amcc,ppc4xx-pka\", \"amcc, ppc4xx-pka\";\n\t\t\treg = <4 0x00114000 0x4000>;\n\t\t\tinterrupt-parent = <&UIC0>;\n\t\t\tinterrupts = <0x14 IRQ_TYPE_EDGE_RISING>;\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tCRYPTO: crypto@180000 {\n\t\t\tcompatible = \"amcc,ppc460ex-crypto\", \"amcc,ppc4xx-crypto\";\n\t\t\treg = <4 0x00180000 0x80400>;\n\t\t\tinterrupt-parent = <&UIC0>;\n\t\t\tinterrupts = <0x1d IRQ_TYPE_LEVEL_HIGH>;\n\t\t\tstatus = \"disabled\"; /* hardware option */\n\t\t};\n\n\t\tMAL0: mcmal {\n\t\t\tcompatible = \"ibm,mcmal-460ex\", \"ibm,mcmal2\";\n\t\t\tdescriptor-memory = \"ocm\";\n\t\t\tdcr-reg = <0x180 0x062>;\n\t\t\tnum-tx-chans = <1>;\n\t\t\tnum-rx-chans = <1>;\n\t\t\t#address-cells = <0>;\n\t\t\t#size-cells = <0>;\n\t\t\tinterrupt-parent = <&UIC2>;\n\t\t\tinterrupts = <0x06 IRQ_TYPE_LEVEL_HIGH>,\n\t\t\t\t     <0x07 IRQ_TYPE_LEVEL_HIGH>,\n\t\t\t\t     <0x03 IRQ_TYPE_LEVEL_HIGH>,\n\t\t\t\t     <0x04 IRQ_TYPE_LEVEL_HIGH>,\n\t\t\t\t     <0x05 IRQ_TYPE_LEVEL_HIGH>,\n\t\t\t\t     <0x08 IRQ_TYPE_EDGE_FALLING>,\n\t\t\t\t     <0x09 IRQ_TYPE_EDGE_FALLING>,\n\t\t\t\t     <0x0c IRQ_TYPE_EDGE_FALLING>,\n\t\t\t\t     <0x0d IRQ_TYPE_EDGE_FALLING>;\n\t\t\tinterrupt-names = \"txeob\", \"rxeob\", \"serr\",\n\t\t\t\t\t  \"txde\", \"rxde\",\n\t\t\t\t\t  \"tx0coal\", \"tx1coal\",\n\t\t\t\t\t  \"rx0coal\", \"rx1coal\";\n\t\t};\n\n\t\tPOB0: opb {\n\t\t\tcompatible = \"ibm,opb-460ex\", \"ibm,opb\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\t\t\tranges = <0xb0000000 0x00000004 0xb0000000 0x50000000>;\n\t\t\tclock-frequency = <0>; /* Filled in by U-Boot */\n\n\t\t\tEBC0: ebc {\n\t\t\t\tcompatible = \"ibm,ebc-460ex\", \"ibm,ebc\";\n\t\t\t\tdcr-reg = <0x012 0x002>;\n\t\t\t\t#address-cells = <2>;\n\t\t\t\t#size-cells = <1>;\n\t\t\t\tclock-frequency = <0>; /* Filled in by U-Boot */\n\t\t\t\t/* ranges property is supplied by U-Boot */\n\t\t\t\tranges = <0x00000003 0x00000000 0xe0000000 0x8000000>;\n\t\t\t\tinterrupts = <0x06 IRQ_TYPE_LEVEL_HIGH>;\n\t\t\t\tinterrupt-parent = <&UIC1>;\n\n\t\t\t\tnor_flash@0,0 {\n\t\t\t\t\tcompatible = \"cfi-flash\";\n\t\t\t\t\tbank-width = <1>;\n\t\t\t\t\treg = <0x00000000 0x00000000 0x00100000>;\n\t\t\t\t\t#address-cells = <1>;\n\t\t\t\t\t#size-cells = <1>;\n\t\t\t\t\tstatus = \"disabled\";\n\t\t\t\t};\n\n\t\t\t\tndfc: ndfc@1,0 {\n\t\t\t\t\tcompatible = \"ibm,ndfc\";\n\t\t\t\t\treg = <00000003 00000000 00002000>;\n\t\t\t\t\tccr = <0x00001000>;\n\t\t\t\t\tbank-settings = <0x80002222>;\n\t\t\t\t\tstatus = \"disabled\";\n\n\t\t\t\t\tnand {\n\t\t\t\t\t\t/*\n\t\t\t\t\t\t * These are the same fixed \"MAGIC\" values\n\t\t\t\t\t\t * settings as in the drivers code.\n\t\t\t\t\t\t * They are the same for all devices that\n\t\t\t\t\t\t * have NAND.\n\t\t\t\t\t\t */\n\t\t\t\t\t\tnand-ecc-engine = <&ndfc>;\n\t\t\t\t\t\tnand-ecc-algo = \"hamming\";\n\t\t\t\t\t\tnand-ecc-step-size = <256>;\n\t\t\t\t\t\tnand-ecc-strength = <1>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tUART0: serial@ef600300 {\n\t\t\t\t/*\n\t\t\t\t * AMCC's BSP u-boot scans for the \"ns16550\"\n\t\t\t\t * compatible, without it, u-boot wouldn't\n\t\t\t\t * set the required \"clock-frequency\".\n\t\t\t\t *\n\t\t\t\t * The hardware documentation states:\n\t\t\t\t * \"Register compatibility with 16750 register set\"\n\t\t\t\t */\n\t\t\t\tcompatible = \"ns16750\", \"ns16550\";\n\t\t\t\treg = <0xef600300 0x00000008>;\n\t\t\t\tvirtual-reg = <0xef600300>;\n\t\t\t\tclock-frequency = <0>; /* Filled in by U-Boot */\n\t\t\t\tinterrupt-parent = <&UIC1>;\n\t\t\t\tinterrupts = <0x01 IRQ_TYPE_LEVEL_HIGH>;\n\t\t\t\tstatus = \"disabled\";\n\t\t\t};\n\n\t\t\tUART1: serial@ef600400 {\n\t\t\t\t/* same \"ns16750\" as with UART0 */\n\t\t\t\tcompatible = \"ns16750\", \"ns16550\";\n\t\t\t\treg = <0xef600400 0x00000008>;\n\t\t\t\tvirtual-reg = <0xef600400>;\n\t\t\t\tclock-frequency = <0>; /* Filled in by U-Boot */\n\t\t\t\tinterrupt-parent = <&UIC0>;\n\t\t\t\tinterrupts = <0x01 IRQ_TYPE_LEVEL_HIGH>;\n\t\t\t\tstatus = \"disabled\";\n\t\t\t};\n\n\t\t\tIIC0: i2c@ef600700 {\n\t\t\t\tcompatible = \"ibm,iic-460ex\", \"ibm,iic\";\n\t\t\t\treg = <0xef600700 0x00000014>;\n\t\t\t\tinterrupt-parent = <&UIC0>;\n\t\t\t\tinterrupts = <0x02 IRQ_TYPE_LEVEL_HIGH>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\t\t\t\tstatus = \"disabled\";\n\t\t\t};\n\n\t\t\tIIC1: i2c@ef600800 {\n\t\t\t\tcompatible = \"ibm,iic-460ex\", \"ibm,iic\";\n\t\t\t\treg = <0xef600800 0x00000014>;\n\t\t\t\tinterrupt-parent = <&UIC0>;\n\t\t\t\tinterrupts = <0x03 IRQ_TYPE_LEVEL_HIGH>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\t\t\t\tstatus = \"disabled\";\n\t\t\t};\n\n\t\t\tGPIO0: gpio@ef600b00 {\n\t\t\t\tcompatible = \"ibm,ppc4xx-gpio\";\n\t\t\t\treg = <0xef600b00 0x00000048>;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\tgpio-controller;\n\t\t\t\tstatus = \"disabled\";\n\t\t\t};\n\n\t\t\tEMAC0: ethernet@ef600c00 {\n\t\t\t\tdevice_type = \"network\";\n\t\t\t\tcompatible = \"ibm,emac-apm821xx\", \"ibm,emac4sync\";\n\t\t\t\tinterrupt-parent = <&EMAC0>;\n\t\t\t\tinterrupts = <0 1>;\n\t\t\t\t#interrupt-cells = <1>;\n\t\t\t\t#address-cells = <0>;\n\t\t\t\t#size-cells = <0>;\n\t\t\t\tinterrupt-map = <0 &UIC2 0x10 IRQ_TYPE_LEVEL_HIGH>,\n\t\t\t\t\t\t<1 &UIC2 0x14 IRQ_TYPE_LEVEL_HIGH>;\n\t\t\t\tinterrupt-names = \"status\", \"wake\";\n\n\t\t\t\treg = <0xef600c00 0x000000c4>;\n\t\t\t\tlocal-mac-address = [000000000000]; /* Filled in by U-Boot */\n\t\t\t\tmal-device = <&MAL0>;\n\t\t\t\tmal-tx-channel = <0>;\n\t\t\t\tmal-rx-channel = <0>;\n\t\t\t\tcell-index = <0>;\n\t\t\t\tmax-frame-size = <9000>;\n\t\t\t\trx-fifo-size = <16384>;\n\t\t\t\ttx-fifo-size = <2048>;\n\t\t\t\tphy-mode = \"rgmii\";\n\t\t\t\tphy-map = <0x00000000>;\n\t\t\t\trgmii-device = <&RGMII0>;\n\t\t\t\trgmii-channel = <0>;\n\t\t\t\ttah-device = <&TAH0>;\n\t\t\t\ttah-channel = <0>;\n\t\t\t\thas-inverted-stacr-oc;\n\t\t\t\thas-new-stacr-staopc;\n\t\t\t\tstatus = \"disabled\";\n\t\t\t};\n\n\t\t\tTAH0: emac-tah@ef601350 {\n\t\t\t\tcompatible = \"ibm,tah-460ex\", \"ibm,tah\";\n\t\t\t\treg = <0xef601350 0x00000030>;\n\t\t\t};\n\n\t\t\tRGMII0: emac-rgmii@ef601500 {\n\t\t\t\tcompatible = \"ibm,rgmii-405ex\", \"ibm,rgmii\";\n\t\t\t\treg = <0xef601500 0x00000008>;\n\t\t\t\thas-mdio;\n\t\t\t};\n\t\t};\n\n\t\tUSBOTG0: usbotg@bff80000 {\n\t\t\tcompatible = \"amcc,dwc-otg\";\n\t\t\treg = <4 0xbff80000 0x10000>;\n\t\t\tinterrupt-parent = <&USBOTG0>;\n\t\t\tinterrupts = <0 1 2>;\n\t\t\t#interrupt-cells = <1>;\n\t\t\t#address-cells = <0>;\n\t\t\t#size-cells = <0>;\n\t\t\tinterrupt-map = <0 &UIC2 0x1c IRQ_TYPE_LEVEL_HIGH>,\n\t\t\t\t\t<1 &UIC1 0x1a IRQ_TYPE_LEVEL_LOW>,\n\t\t\t\t\t<2 &UIC0 0x0c IRQ_TYPE_LEVEL_HIGH>;\n\t\t\tinterrupt-names = \"usb-otg\", \"high-power\", \"dma\";\n\t\t\tdr_mode = \"host\";\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tAHBDMA0: dma@bffd0800 {\n\t\t\tcompatible = \"snps,dma-spear1340\";\n\t\t\treg = <4 0xbffd0800 0x400>;\n\t\t\tinterrupt-parent = <&UIC0>;\n\t\t\tinterrupts = <0x19 IRQ_TYPE_LEVEL_HIGH>;\n\t\t\t#dma-cells = <3>;\n\n\t\t\tdma-channels = <2>;\n\t\t\tdma-masters = <3>;\n\t\t\tblock_size = <4095>;\n\t\t\tdata-width = <4>, <4>, <4>;\n\t\t\tmulti-block = <1>, <1>;\n\n\t\t\tchan_allocation_order = <1>;\n\t\t\tchan_priority = <1>;\n\n\t\t\tsnps,dma-protection-control =\n\t\t\t\t<(DW_DMAC_HPROT1_PRIVILEGED_MODE |\n\t\t\t\t  DW_DMAC_HPROT2_BUFFERABLE)>;\n\t\t\tis_memcpy;\n\t\t};\n\n\t\tSATA0: sata@bffd1000 {\n\t\t\tcompatible = \"amcc,sata-460ex\";\n\t\t\treg = <4 0xbffd1000 0x800>;\n\t\t\tinterrupt-parent = <&UIC0>;\n\t\t\tinterrupts = <0x1a IRQ_TYPE_LEVEL_HIGH>;\n\t\t\tdmas = <&AHBDMA0 0 0 1>;\n\t\t\tdma-names = \"sata-dma\";\n\t\t\tstatus = \"disabled\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tSATA1: sata@bffd1800 {\n\t\t\tcompatible = \"amcc,sata-460ex\";\n\t\t\treg = <4 0xbffd1800 0x800>;\n\t\t\tinterrupt-parent = <&UIC0>;\n\t\t\tinterrupts = <0x1b IRQ_TYPE_LEVEL_HIGH>;\n\t\t\tdmas = <&AHBDMA0 1 0 2>;\n\t\t\tdma-names = \"sata-dma\";\n\t\t\tstatus = \"disabled\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tPCIE0: pciex@d00000000 {\n\t\t\tdevice_type = \"pci\"; /* see ppc4xx_pci_find_bridge */\n\t\t\t#interrupt-cells = <1>;\n\t\t\t#size-cells = <2>;\n\t\t\t#address-cells = <3>;\n\t\t\tcompatible = \"ibm,plb-pciex-apm821xx\", \"ibm,plb-pciex\";\n\t\t\tprimary;\n\t\t\tport = <0x0>; /* port number */\n\t\t\treg = <0x0000000d 0x00000000 0x20000000>, /* Config space access */\n\t\t\t      <0x0000000c 0x08010000 0x00001000>; /* Registers */\n\t\t\tdcr-reg = <0x100 0x020>;\n\t\t\tsdr-base = <0x300>;\n\n\t\t\t/*\n\t\t\t * Outbound ranges, one memory and one IO,\n\t\t\t * later cannot be changed\n\t\t\t */\n\t\t\tranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000>,\n\t\t\t\t <0x02000000 0x00000000 0x00000000 0x0000000f 0x00000000 0x00000000 0x00100000>,\n\t\t\t\t <0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>;\n\n\t\t\t/* Inbound 2GB range starting at 0 */\n\t\t\tdma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;\n\n\t\t\t/* This drives busses 0x40 to 0x7f */\n\t\t\tbus-range = <0x40 0x7f>;\n\n\t\t\t/*\n\t\t\t * Legacy interrupts (note the weird polarity, the bridge seems\n\t\t\t * to invert PCIe legacy interrupts).\n\t\t\t * We are de-swizzling here because the numbers are actually for\n\t\t\t * port of the root complex virtual P2P bridge. But I want\n\t\t\t * to avoid putting a node for it in the tree, so the numbers\n\t\t\t * below are basically de-swizzled numbers.\n\t\t\t * The real slot is on idsel 0, so the swizzling is 1:1\n\t\t\t */\n\t\t\tinterrupt-map-mask = <0x0 0x0 0x0 0x7>;\n\t\t\tinterrupt-map =\n\t\t\t\t<0x0 0x0 0x0 0x1 &UIC3 0x0c IRQ_TYPE_LEVEL_HIGH>, /* swizzled int A */\n\t\t\t\t<0x0 0x0 0x0 0x2 &UIC3 0x0d IRQ_TYPE_LEVEL_HIGH>, /* swizzled int B */\n\t\t\t\t<0x0 0x0 0x0 0x3 &UIC3 0x0e IRQ_TYPE_LEVEL_HIGH>, /* swizzled int C */\n\t\t\t\t<0x0 0x0 0x0 0x4 &UIC3 0x0f IRQ_TYPE_LEVEL_HIGH>; /* swizzled int D */\n\t\t\tstatus = \"disabled\";\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/apm821xx/dts/meraki-mr24.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-only\n/*\n * Device Tree Source for Meraki MR24 (Ikarem)\n *\n * Copyright (C) 2016 Chris Blake <chrisrblake93@gmail.com>\n *\n * Based on Cisco Meraki GPL Release r23-20150601 MR24 DTS\n */\n\n/dts-v1/;\n\n#include <dt-bindings/leds/common.h>\n#include \"apm82181.dtsi\"\n\n/ {\n\tmodel = \"Meraki MR24 Access Point\";\n\tcompatible = \"meraki,mr24\", \"meraki,ikarem\", \"apm,bluestone\";\n\n\taliases {\n\t\tserial0 = &UART1;\n\t};\n\n\tchosen {\n\t\tstdout-path = \"/plb/opb/serial@ef600400\";\n\t};\n};\n\n\n&CRYPTO {\n\tstatus = \"okay\";\n};\n\n&PKA {\n\tstatus = \"okay\";\n};\n\n&TRNG {\n\tstatus = \"okay\";\n};\n\n&ndfc {\n\t/* Ikarem has 32MB of NAND */\n\tstatus = \"okay\";\n\n\tnand {\n\t\tnand-is-boot-medium;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x00000000 0x00150000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@150000 {\n\t\t\t\t/*\n\t\t\t\t * The u-boot environment size is one NAND\n\t\t\t\t * block (16KiB). u-boot allocates four NAND\n\t\t\t\t * blocks (64KiB) in order to have spares\n\t\t\t\t * around for bad block management\n\t\t\t\t */\n\t\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\t\treg = <0x00150000 0x00010000>;\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\tpartition@160000 {\n\t\t\t\t/*\n\t\t\t\t * redundant u-boot environment.\n\t\t\t\t * has to be kept it in sync with the\n\t\t\t\t * data in \"u-boot-env\".\n\t\t\t\t */\n\t\t\t\tlabel = \"u-boot-env-redundant\";\n\t\t\t\treg = <0x00160000 0x00010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@170000 {\n\t\t\t\tlabel = \"oops\";\n\t\t\t\treg = <0x00170000 0x00010000>;\n\t\t\t};\n\n\t\t\tpartition@180000 {\n\t\t\t\tlabel = \"ubi\";\n\t\t\t\treg = <0x00180000 0x01e80000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&UART1 {\n\tstatus = \"okay\";\n};\n\n&GPIO0 {\n\tstatus = \"okay\";\n};\n\n&IIC0 {\n\tstatus = \"okay\";\n\t/* Boot ROM is at 0x52-0x53, do not touch */\n\t/* Unknown chip at 0x6e, not sure what it is */\n};\n\n&EMAC0 {\n\tstatus = \"okay\";\n\n\tphy-mode = \"rgmii-id\";\n\tphy-map = <0x2>;\n\tphy-address = <0x1>;\n\tphy-handle = <&phy>;\n\n\tmdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tphy: phy@1 {\n\t\t\tcompatible = \"ethernet-phy-ieee802.3-c22\";\n\t\t\treg = <1>;\n\t\t};\n\t};\n};\n\n&POB0 {\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled-0 {\n\t\t\tcolor = <LED_COLOR_ID_GREEN>;\n\t\t\tfunction = LED_FUNCTION_POWER;\n\t\t\tgpios = <&GPIO0 18 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled-1 {\n\t\t\tcolor = <LED_COLOR_ID_AMBER>;\n\t\t\tfunction = LED_FUNCTION_FAULT;\n\t\t\tgpios = <&GPIO0 19 GPIO_ACTIVE_LOW>;\n\t\t\tpanic-indicator;\n\t\t};\n\n\t\tled-2 {\n\t\t\tcolor = <LED_COLOR_ID_GREEN>;\n\t\t\tfunction = LED_FUNCTION_WAN;\n\t\t\tgpios = <&GPIO0 17 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled-3 {\n\t\t\tcolor = <LED_COLOR_ID_GREEN>;\n\t\t\tfunction = LED_FUNCTION_WLAN;\n\t\t\tfunction-enumerator = <0>;\n\t\t\tgpios = <&GPIO0 23 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled-4 {\n\t\t\tcolor = <LED_COLOR_ID_GREEN>;\n\t\t\tfunction = LED_FUNCTION_WLAN;\n\t\t\tfunction-enumerator = <1>;\n\t\t\tgpios = <&GPIO0 22 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled-5 {\n\t\t\tcolor = <LED_COLOR_ID_GREEN>;\n\t\t\tfunction = LED_FUNCTION_WLAN;\n\t\t\tfunction-enumerator = <2>;\n\t\t\tgpios = <&GPIO0 21 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled-6 {\n\t\t\tcolor = <LED_COLOR_ID_GREEN>;\n\t\t\tfunction = LED_FUNCTION_WLAN;\n\t\t\tfunction-enumerator = <3>;\n\t\t\tgpios = <&GPIO0 20 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\t/* Label as per Meraki's \"MR24 Installation Guide\" */\n\t\t\tlabel = \"Factory Reset Button\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tinterrupt-parent = <&UIC1>;\n\t\t\tinterrupts = <0x15 IRQ_TYPE_EDGE_FALLING>;\n\t\t\tgpios = <&GPIO0 16 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n};\n\n&PCIE0 {\n\tstatus = \"okay\";\n\t/*\n\t * relevant lspci topology:\n\t *\n\t *\t-+-[0000:40]---00.0-[41-7f]----00.0-[42-45]--+-02.0-[43]----00.0\n\t *\t                                             +-03.0-[44]----00.0\n\t *\n\t */\n\n\tbridge@64,0 {\n\t\treg = <0x00400000 0 0 0 0>;\n\t\t#address-cells = <3>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tbridge@65,0 {\n\t\t\t/* IDT PES3T3 PCI Express Switch */\n\t\t\tcompatible = \"pci111d,8039\";\n\t\t\treg = <0x00410000 0 0 0 0>;\n\t\t\t#address-cells = <3>;\n\t\t\t#size-cells = <2>;\n\t\t\tranges;\n\n\t\t\tbridge@66,2 {\n\t\t\t\tcompatible = \"pci111d,8039\";\n\t\t\t\treg = <0x00421000 0 0 0 0>;\n\t\t\t\t#address-cells = <3>;\n\t\t\t\t#size-cells = <2>;\n\t\t\t\tranges;\n\n\t\t\t\twifi0: wifi@67,0 {\n\t\t\t\t\t/* Atheros AR9380 2.4GHz */\n\t\t\t\t\tcompatible = \"pci168c,0030\";\n\t\t\t\t\treg = <0x00430000 0 0 0 0>;\n\t\t\t\t\tinterrupts = <3>; /* INTC 4.1.1 */\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tbridge@66,3 {\n\t\t\t\tcompatible = \"pci111d,8039\";\n\t\t\t\treg = <0x00421800 0 0 0 0>;\n\t\t\t\t#address-cells = <3>;\n\t\t\t\t#size-cells = <2>;\n\t\t\t\tranges;\n\n\t\t\t\twifi1: wifi@68,0 {\n\t\t\t\t\t/* Atheros AR9380 5GHz */\n\t\t\t\t\tcompatible = \"pci168c,0030\";\n\t\t\t\t\treg = <0x00440000 0 0 0 0>;\n\t\t\t\t\tinterrupts = <4>; /* INTD 4.1.1 */\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/apm821xx/dts/meraki-mx60.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-only\n/*\n * Device Tree Source for Meraki MX60/MX60W (Buckminster)\n *\n * Copyright (C) 2016 Chris Blake <chrisrblake93@gmail.com>\n *\n * Based on Cisco Meraki DTS extracted from release wired-12-217818\n */\n\n/dts-v1/;\n\n#include <dt-bindings/leds/common.h>\n#include \"apm82181.dtsi\"\n\n/ {\n\tmodel = \"Meraki MX60/MX60W Security Appliance\";\n\tcompatible = \"meraki,mx60\", \"meraki,buckminster\", \"apm,bluestone\";\n\n\taliases {\n\t\tserial0 = &UART1;\n\t};\n\n\tchosen {\n\t\tstdout-path = \"/plb/opb/serial@ef600400\";\n\t};\n};\n\n&CRYPTO {\n\tstatus = \"okay\";\n};\n\n&PKA {\n\tstatus = \"okay\";\n};\n\n&TRNG {\n\tstatus = \"okay\";\n};\n\n&USBOTG0 {\n\tstatus = \"okay\";\n\tdr_mode = \"host\";\n};\n\n&ndfc {\n\t/* Buckminster has 1GiB of NAND */\n\tstatus = \"okay\";\n\n\tnand {\n\t\tnand-is-boot-medium;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x00000000 0x00100000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@100000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x00100000 0x00100000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@200000 {\n\t\t\t\tlabel = \"oops\";\n\t\t\t\treg = <0x00200000 0x00040000>;\n\t\t\t};\n\n\t\t\tpartition@240000 {\n\t\t\t\tlabel = \"ubi\";\n\t\t\t\treg = <0x00240000 0x3fdc0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&UART1 {\n\tstatus = \"okay\";\n};\n\n&GPIO0 {\n\tstatus = \"okay\";\n};\n\n&IIC0 {\n\tstatus = \"okay\";\n};\n\n&EMAC0 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy0>;\n\n\tmdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: ethernet-phy@0 {\n\t\t\tcompatible = \"ethernet-phy-id004d.d034\";\n\t\t\treg = <0>;\n\t\t\tqca,mib-poll-interval = <500>;\n\n\t\t\tqca,ar8327-initvals = <\n\t\t\t\t0x0010 0x40000000\n\t\t\t\t0x0624 0x007f7f7f\n\t\t\t\t0x0004 0x07a00000\t/* PAD0_MODE */\n\t\t\t\t0x000c 0x01000000\t/* PAD6_MODE */\n\t\t\t\t0x007c 0x0000007e\t/* PORT0_STATUS */\n\t\t\t>;\n\t\t};\n\t};\n};\n\n&POB0 {\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled-0 {\n\t\t\tcolor = <LED_COLOR_ID_GREEN>;\n\t\t\tfunction = LED_FUNCTION_POWER;\n\t\t\tgpios = <&GPIO0 18 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled-1 {\n\t\t\tcolor = <LED_COLOR_ID_AMBER>;\n\t\t\tfunction = LED_FUNCTION_FAULT;\n\t\t\tgpios = <&GPIO0 19 GPIO_ACTIVE_LOW>;\n\t\t\tpanic-indicator;\n\t\t};\n\n\t\tled-2 {\n\t\t\tcolor = <LED_COLOR_ID_GREEN>;\n\t\t\tfunction = LED_FUNCTION_WAN;\n\t\t\tgpios = <&GPIO0 17 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled-3 {\n\t\t\tcolor = <LED_COLOR_ID_AMBER>;\n\t\t\tfunction = LED_FUNCTION_WAN;\n\t\t\tgpios = <&GPIO0 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled-4 {\n\t\t\tcolor = <LED_COLOR_ID_GREEN>;\n\t\t\tfunction = LED_FUNCTION_LAN;\n\t\t\tfunction-enumerator = <0>;\n\t\t\tgpios = <&GPIO0 20 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled-5 {\n\t\t\tcolor = <LED_COLOR_ID_GREEN>;\n\t\t\tfunction = LED_FUNCTION_LAN;\n\t\t\tfunction-enumerator = <1>;\n\t\t\tgpios = <&GPIO0 21 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled-6 {\n\t\t\tcolor = <LED_COLOR_ID_GREEN>;\n\t\t\tfunction = LED_FUNCTION_LAN;\n\t\t\tfunction-enumerator = <2>;\n\t\t\tgpios = <&GPIO0 22 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled-7 {\n\t\t\tcolor = <LED_COLOR_ID_GREEN>;\n\t\t\tfunction = LED_FUNCTION_LAN;\n\t\t\tfunction-enumerator = <3>;\n\t\t\tgpios = <&GPIO0 23 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"Reset button\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&GPIO0 16 GPIO_ACTIVE_LOW>;\n\t\t\tinterrupt-parent = <&UIC1>;\n\t\t\tinterrupts = <0x15 IRQ_TYPE_EDGE_FALLING>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n};\n\n&PCIE0 {\n\t/* Leave this enabled as u-boot on the MX60 will disable it for us */\n\tstatus = \"okay\";\n\n\t/*\n\t * relevant lspci topology:\n\t *\n\t *\t-+-[0000:40]---00.0-[41-7f]----00.0\n\t */\n\n\tbridge@64,0 {\n\t\treg = <0x00400000 0 0 0 0>;\n\t\t#address-cells = <3>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\twifi0: wifi@65,0 {\n\t\t\t/* Atheros AR9380 2.4/5GHz */\n\t\t\tcompatible = \"pci168c,0030\";\n\t\t\treg = <0x00410000 0 0 0 0>;\n\t\t\tinterrupts = <1>; /* INTA */\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/apm821xx/dts/netgear-wndap620.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-only\n\n/dts-v1/;\n\n#include \"netgear-wndap6x0.dtsi\"\n\n/ {\n\tmodel = \"Netgear WNDAP620\";\n\tcompatible = \"netgear,wndap620\", \"apm,bluestone\";\n};\n\n&LEDS {\n\tled-5 {\n\t\tfunction = LED_FUNCTION_LAN;\n\t\tfunction-enumerator = <1>;\n\t\tcolor = <LED_COLOR_ID_GREEN>;\n\t\tgpios = <&GPIO0 9 GPIO_ACTIVE_HIGH>;\n\t};\n\n\tled-6 {\n\t\tfunction = LED_FUNCTION_LAN;\n\t\tcolor = <LED_COLOR_ID_AMBER>;\n\t\tgpios = <&GPIO0 10 GPIO_ACTIVE_HIGH>;\n\t};\n};\n\n&PCIE0 {\n\t/*\n\t * relevant lspci topology:\n\t *\n\t *\t-+-[0000:40]---00.0-[41-7f]----00.0\n\t */\n\n\tbridge@64,0 {\n\t\treg = <0x00400000 0 0 0 0>;\n\t\t#address-cells = <3>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\twifi0: wifi@65,0 {\n\t\t\t/* Atheros AR9380 5GHz */\n\t\t\tcompatible = \"pci168c,0030\";\n\t\t\treg = <0x00410000 0 0 0 0>;\n\t\t\tinterrupts = <1>; /* INTA */\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/apm821xx/dts/netgear-wndap660.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-only\n\n/dts-v1/;\n\n#include \"netgear-wndap6x0.dtsi\"\n\n/ {\n\tmodel = \"Netgear WNDAP660\";\n\tcompatible = \"netgear,wndap660\", \"apm,bluestone\";\n};\n\n&LEDS {\n\tled-5 {\n\t\tcolor = <LED_COLOR_ID_GREEN>;\n\t\tfunction = LED_FUNCTION_LAN;\n\t\tfunction-enumerator = <1>;\n\t\tgpios = <&GPIO0 22 GPIO_ACTIVE_HIGH>;\n\t};\n\n\tled-6 {\n\t\tcolor = <LED_COLOR_ID_AMBER>;\n\t\tfunction = LED_FUNCTION_LAN;\n\t\tfunction-enumerator = <0>;\n\t\tgpios = <&GPIO0 23 GPIO_ACTIVE_HIGH>;\n\t};\n\n\tled-7 {\n\t\tcolor = <LED_COLOR_ID_GREEN>;\n\t\tfunction = LED_FUNCTION_LAN;\n\t\tfunction-enumerator = <2>;\n\t\tgpios = <&GPIO0 9 GPIO_ACTIVE_HIGH>;\n\t};\n\n\tled-8 {\n\t\tcolor = <LED_COLOR_ID_AMBER>;\n\t\tfunction = LED_FUNCTION_LAN;\n\t\tfunction-enumerator = <1>;\n\t\tgpios = <&GPIO0 10 GPIO_ACTIVE_HIGH>;\n\t};\n};\n\n&PCIE0 {\n\t/*\n\t * relevant lspci topology:\n\t *\n\t *\t-+-[0000:40]---00.0-[41-7f]----00.0-[42-45]--+-02.0-[43]----00.0\n\t *\t                                             +-03.0-[44]----00.0\n\t *\n\t */\n\n\tbridge@64,0 {\n\t\treg = <0x00400000 0 0 0 0>;\n\t\t#address-cells = <3>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tbridge@65,0 {\n\t\t\t/* IDT PES3T3 PCI Express Switch */\n\t\t\tcompatible = \"pci111d,8039\";\n\t\t\treg = <0x00410000 0 0 0 0>;\n\t\t\t#address-cells = <3>;\n\t\t\t#size-cells = <2>;\n\t\t\tranges;\n\n\t\t\tbridge@66,2 {\n\t\t\t\tcompatible = \"pci111d,8039\";\n\t\t\t\treg = <0x00421000 0 0 0 0>;\n\t\t\t\t#address-cells = <3>;\n\t\t\t\t#size-cells = <2>;\n\t\t\t\tranges;\n\n\t\t\t\twifi0: wifi@67,0 {\n\t\t\t\t\t/* Atheros AR9380 2.4/5GHz */\n\t\t\t\t\tcompatible = \"pci168c,0030\";\n\t\t\t\t\treg = <0x00430000 0 0 0 0>;\n\t\t\t\t\tinterrupts = <3>; /* INTC */\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tbridge@66,3 {\n\t\t\t\tcompatible = \"pci111d,8039\";\n\t\t\t\treg = <0x00421800 0 0 0 0>;\n\t\t\t\t#address-cells = <3>;\n\t\t\t\t#size-cells = <2>;\n\t\t\t\tranges;\n\n\t\t                wifi1: wifi@68,0 {\n\t\t\t\t\t/* Atheros AR9380 2.4/5GHz */\n\t\t\t\t\tcompatible = \"pci168c,0030\";\n\t\t\t\t\treg = <0x00440000 0 0 0 0>;\n\t\t\t\t\tinterrupts = <4>; /* INTD */\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/apm821xx/dts/netgear-wndap6x0.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-only\n/*\n * Device Tree Source for Netgear WNDAP620 and WNDAP660\n */\n\n#include <dt-bindings/leds/common.h>\n#include \"apm82181.dtsi\"\n\n/ {\n\taliases {\n\t\tserial0 = &UART0;\n\t};\n\n\tchosen {\n\t\tstdout-path = \"/plb/opb/serial@ef600300\";\n\t};\n};\n\n&CRYPTO {\n\tstatus = \"okay\";\n};\n\n&PKA {\n\tstatus = \"okay\";\n};\n\n&TRNG {\n\tstatus = \"okay\";\n};\n\n&ndfc {\n\tstatus = \"okay\";\n\t/* 32 MiB SLC NAND Flash */\n\n\tnand {\n\t\tnand-is-boot-medium;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x00000000 0x00100000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@100000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x00100000 0x00010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@110000 {\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x00110000 0x01ac0000>;\n\n\t\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\n\t\t\t\tpartition@0 {\n\t\t\t\t\t/*\n\t\t\t\t\t * The u-boot bootloader will look at this\n\t\t\t\t\t * offset (0x110000) for an uImage binary.\n\t\t\t\t\t */\n\t\t\t\t\tlabel = \"kernel\";\n\t\t\t\t\treg = <0x00000000 0x005f0000>;\n\t\t\t\t};\n\n\t\t\t\tpartition@5f0000 {\n\t\t\t\t\tlabel = \"ubi\";\n\t\t\t\t\treg = <0x005f0000 0x014d0000>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tpartition@1bd0000 {\n\t\t\t\t/*\n\t\t\t\t * original vendor device-tree - do not use or\n\t\t\t\t * overwrite. The original u-boot also supports\n\t\t\t\t * the gzipped legacy monolithic/Multi-File Image\n\t\t\t\t * format, which is a better choice.\n\t\t\t\t */\n\t\t\t\tlabel = \"device-tree\";\n\t\t\t\treg = <0x01bd0000 0x0010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@1be0000 {\n\t\t\t\tlabel = \"var\";\n\t\t\t\treg = <0x01be0000 0x00400000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@1fe0000 {\n\t\t\t\tlabel = \"manudata\";\n\t\t\t\treg = <0x01fe0000 0x00020000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&UART0 {\n\tstatus = \"okay\";\n};\n\n&GPIO0 {\n\tstatus = \"okay\";\n};\n\n&EMAC0 {\n\tstatus = \"okay\";\n\n\tfixed-link {\n\t\tspeed = <1000>;\n\t\tfull-duplex;\n\t\tpause;\n\t\tasym-pause;\n\t};\n\n\tmdio0: mdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t};\n};\n\n&POB0 {\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"Reset Button\";\n\t\t\tgpios = <&GPIO0 16 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tinterrupt-parent = <&UIC1>;\n\t\t\tinterrupts = <0x15 IRQ_TYPE_EDGE_FALLING>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tLEDS: leds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled-0 {\n\t\t\tcolor = <LED_COLOR_ID_GREEN>;\n\t\t\tfunction = LED_FUNCTION_POWER;\n\t\t\tgpios = <&GPIO0 18 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tled-1 {\n\t\t\tcolor = <LED_COLOR_ID_AMBER>;\n\t\t\tfunction = LED_FUNCTION_FAULT;\n\t\t\tgpios = <&GPIO0 17 GPIO_ACTIVE_HIGH>;\n\t\t\tpanic-indicator;\n\t\t};\n\n\t\tled-2 {\n\t\t\tcolor = <LED_COLOR_ID_GREEN>;\n\t\t\tfunction = LED_FUNCTION_LAN;\n\t\t\tfunction-enumerator = <0>;\n\t\t\tgpios = <&GPIO0 21 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tled-3 {\n\t\t\tcolor = <LED_COLOR_ID_GREEN>;\n\t\t\tfunction = LED_FUNCTION_WLAN;\n\t\t\tfunction-enumerator = <0>;\n\t\t\tgpios = <&GPIO0 19 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tled-4 {\n\t\t\tcolor = <LED_COLOR_ID_GREEN>;\n\t\t\tfunction = LED_FUNCTION_WLAN;\n\t\t\tfunction-enumerator = <1>;\n\t\t\tgpios = <&GPIO0 20 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n\n\tgpio-export {\n\t\tcompatible = \"gpio-export\";\n\n\t\tinternal-antenna {\n\t\t\tgpio-export,name = \"wndap6x0:internal-antenna\";\n\t\t\tgpio-export,output = <1>;\n\t\t\tgpios = <&GPIO0 11 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\texternal-antenna {\n\t\t\tgpio-export,name = \"wndap6x0:external-antenna\";\n\t\t\tgpio-export,output = <0>;\n\t\t\tgpios = <&GPIO0 14 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tmains-powered {\n\t\t\t/*\n\t\t\t * Input pin describing what powers the AP\n\t\t\t * 0/Low = PoE\n\t\t\t * 1/High = 12v mains powered\n\t\t\t */\n\t\t\tgpio-export,name = \"wndap620:mains-powered\";\n\t\t\tgpios = <&GPIO0 3 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n\n\trtl8367b {\n\t\tcompatible = \"realtek,rtl8367b\";\n\t\tcpu_port = <5>;\n\t\trealtek,extif0 = <1 2 1 1 1 1 1 1 2>;\n\t\tmii-bus = <&mdio0>;\n\t};\n};\n\n&PCIE0 {\n\tstatus = \"okay\";\n};\n\n&IIC0 {\n\tstatus = \"okay\";\n\n\tat24@52 {\n\t\tcompatible = \"atmel,24c04\";\n\t\treg = <0x52>;\n\t\tpagesize = <16>;\n\t\tread-only;\n\t};\n};\n"
  },
  {
    "path": "target/linux/apm821xx/dts/netgear-wndr4700.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-only\n/*\n * Device Tree Source for Netgear WNDR4700/WNDR4720 Series\n *\n * Copyright 2008 DENX Software Engineering, Stefan Roese <sr@denx.de>\n */\n\n/dts-v1/;\n\n#include <dt-bindings/thermal/thermal.h>\n#include <dt-bindings/leds/common.h>\n#include \"apm82181.dtsi\"\n\n/ {\n\tmodel = \"Netgear WNDR4700/WNDR4720 Series\";\n\tcompatible = \"netgear,wndr4700\", \"apm,bluestone\";\n\n\taliases {\n\t\tserial0 = &UART0;\n\t};\n\n\tchosen {\n\t\tstdout-path = \"/plb/opb/serial@ef600300:115200n8\";\n\t};\n\n\tthermal-zones {\n\t\tcpu_thermal: cpu-thermal {\n\t\t\tpolling-delay-passive = <10000>; /* milliseconds */\n\t\t\tpolling-delay = <20000>; /* milliseconds */\n\n\t\t\tthermal-sensors = <&temp0 1>;\n\n\t\t\t/*\n\t\t\t * REVISIT:\n\t\t\t *\n\t\t\t * Add the <&drive_temp>; sensor there and wire up\n\t\t\t * the coefficients = <1 1>; property.\n\t\t\t *\n\t\t\t * Note: The kernel does not yet support more than\n\t\t\t * one sensor (see of_thermal.c's function:\n\t\t\t * thermal_of_build_thermal_zon()). Once this is\n\t\t\t * implemented.\n\t\t\t */\n\n\t\t\ttrips {\n\t\t\t\t/*\n\t\t\t\t * Once the thermal governers are a bit smarter\n\t\t\t\t * and do hysteresis properly, we can disable\n\t\t\t\t * the fan when the HDD and CPU has < 39 C.\n\t\t\t\t */\n\t\t\t\tcpu_alert0: board-alert0 {\n\t\t\t\t\ttemperature = <25000>;\n\t\t\t\t\thysteresis = <2000>;\n\t\t\t\t\ttype = \"active\";\n\t\t\t\t};\n\n\t\t\t\tcpu_alert1: cpu-alert1 {\n\t\t\t\t\ttemperature = <27000>; /* millicelsius */\n\t\t\t\t\thysteresis = <2000>; /* millicelsius */\n\t\t\t\t\ttype = \"active\";\n\t\t\t\t};\n\n\t\t\t\tcpu_alert2: cpu-alert2 {\n\t\t\t\t\ttemperature = <65000>; /* millicelsius */\n\t\t\t\t\thysteresis = <2000>; /* millicelsius */\n\t\t\t\t\ttype = \"active\";\n\t\t\t\t};\n\n\t\t\t\tcpu_alert3: cpu-alert3 {\n\t\t\t\t\ttemperature = <70000>; /* millicelsius */\n\t\t\t\t\thysteresis = <2000>; /* millicelsius */\n\t\t\t\t\ttype = \"active\";\n\t\t\t\t};\n\n\t\t\t\tcpu_alert4: cpu-alert4 {\n\t\t\t\t\ttemperature = <75000>; /* millicelsius */\n\t\t\t\t\thysteresis = <2000>; /* millicelsius */\n\t\t\t\t\ttype = \"active\";\n\t\t\t\t};\n\n\t\t\t\tcpu_alert5: cpu-alert5 {\n\t\t\t\t\ttemperature = <80000>; /* millicelsius */\n\t\t\t\t\thysteresis = <2000>; /* millicelsius */\n\t\t\t\t\ttype = \"active\";\n\t\t\t\t};\n\n\t\t\t\tcpu_alert6: cpu-alert6 {\n\t\t\t\t\ttemperature = <85000>; /* millicelsius */\n\t\t\t\t\thysteresis = <2000>; /* millicelsius */\n\t\t\t\t\ttype = \"active\";\n\t\t\t\t};\n\n\t\t\t\tcpu_crit: cpu-crit {\n\t\t\t\t\ttemperature = <90000>; /* millicelsius */\n\t\t\t\t\thysteresis = <2000>; /* millicelsius */\n\t\t\t\t\ttype = \"critical\";\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tcooling-maps {\n\t\t\t\tmap0 {\n\t\t\t\t\ttrip = <&cpu_alert0>;\n\t\t\t\t\tcooling-device = <&fan0 THERMAL_NO_LIMIT 0>;\n\t\t\t\t};\n\n\t\t\t\tmap1 {\n\t\t\t\t\ttrip = <&cpu_alert1>;\n\t\t\t\t\tcooling-device = <&fan0 1 1>;\n\t\t\t\t};\n\n\t\t\t\tmap2 {\n\t\t\t\t\ttrip = <&cpu_alert2>;\n\t\t\t\t\tcooling-device = <&fan0 2 4>;\n\t\t\t\t};\n\n\t\t\t\tmap3 {\n\t\t\t\t\ttrip = <&cpu_alert3>;\n\t\t\t\t\tcooling-device = <&fan0 4 8>;\n\t\t\t\t};\n\n\t\t\t\tmap4 {\n\t\t\t\t\ttrip = <&cpu_alert4>;\n\t\t\t\t\tcooling-device = <&fan0 9 12>;\n\t\t\t\t};\n\n\t\t\t\tmap5 {\n\t\t\t\t\ttrip = <&cpu_alert5>;\n\t\t\t\t\tcooling-device = <&fan0 13 15>;\n\t\t\t\t};\n\n\t\t\t\tmap6 {\n\t\t\t\t\ttrip = <&cpu_alert6>;\n\t\t\t\t\tcooling-device =<&fan0 16 THERMAL_NO_LIMIT>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t};\n};\n\n&CRYPTO {\n\tstatus = \"okay\";\n};\n\n&PKA {\n\tstatus = \"okay\";\n};\n\n&TRNG {\n\tstatus = \"okay\";\n};\n\n&SATA1 {\n\tstatus = \"okay\";\n\n\t/*\n\t * This drive may have a temperature sensor with a\n\t * thermal zone we can use for thermal control of the\n\t * chassis temperature using the fan.\n\t */\n\n\tdrive_temp: sata-port@0 {\n\t\treg = <0>;\n\t\t#thermal-sensor-cells = <0>;\n\t};\n};\n\n&USBOTG0 {\n\tstatus = \"okay\";\n\tdr_mode = \"host\";\n};\n\n&ndfc {\n\tstatus = \"okay\";\n\t/* 128 MiB Nand Flash */\n\tnand {\n\t\tnand-is-boot-medium;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"uboot\";\n\t\t\t\treg = <0x00000000 0x00180000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@180000 {\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x00180000 0x01860000>;\n\n\t\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\n\t\t\t\tpartition@0 {\n\t\t\t\t\tlabel = \"kernel\";\n\t\t\t\t\treg = <0x00000000 0x00380000>;\n\n\t\t\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t\t\t#address-cells = <1>;\n\t\t\t\t\t#size-cells = <1>;\n\n\t\t\t\t\t/*\n\t\t\t\t\t * device-tree is @ 0x00180000 - 0x0019ffff\n\t\t\t\t\t * kernel starts from 0x20000.\n\t\t\t\t\t * this is coded into netgear's u-boot.\n\t\t\t\t\t */\n\t\t\t\t\tpartition@0 {\n\t\t\t\t\t\tlabel = \"dtb\";\n\t\t\t\t\t\treg = <0x00000000 0x20000>;\n\t\t\t\t\t};\n\t\t\t\t/*\n\t\t\t\t * this partition will also contain a\n\t\t\t\t * fake/empty rootfs at the end to fool\n\t\t\t\t * Netgear's uboot rootfs integrety checks.\n\t\t\t\t */\n\t\t\t\t};\n\n\t\t\t\tpartition@380000 {\n\t\t\t\t\tlabel = \"ubi\";\n\t\t\t\t\treg = <0x00380000 0x014e0000>;\n\t\t\t\t};\n\t\t\t};\n\n\n\t\t\t/*\n\t\t\t * Netgear's u-boot in the fw_recovery mode (can be\n\t\t\t * triggered by holding the reset button, or if\n\t\t\t * \"bootm\" fails) will not flash past this point\n\t\t\t * (= 0x19E0000).\n\t\t\t */\n\n\t\t\tpartition@19e0000 {\n\t\t\t\tlabel = \"config\";\n\t\t\t\treg = <0x019e0000 0x00080000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@1a60000 {\n\t\t\t\tlabel = \"pot\";\n\t\t\t\treg = <0x01a60000 0x00080000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@1ae0000 {\n\t\t\t\tlabel = \"traffic_meter\";\n\t\t\t\treg = <0x01ae0000 0x00300000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@1de0000 {\n\t\t\t\tlabel = \"language\";\n\t\t\t\treg = <0x01de0000 0x001c0000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@1fa0000 {\n\t\t\t\tlabel = \"ecos\";\n\t\t\t\treg = <0x01fa0000 0x06020000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@7fc0000 {\n\t\t\t\tlabel = \"wifi_data\";\n\t\t\t\treg = <0x07fc0000 0x00040000>;\n\t\t\t\tread-only;\n\n\t\t\t\tcompatible = \"nvmem-cells\";\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\n\t\t\t\tmacaddr_wifi_0: macaddr@0 {\n\t\t\t\t\treg = <0x0 0x6>;\n\t\t\t\t};\n\t\t\t\tmacaddr_wifi_c: macaddr@c {\n\t\t\t\t\treg = <0xc 0x6>;\n\t\t\t\t};\n\n\t\t\t\tcalibration_wifi_1000: calibration@1000 {\n\t\t\t\t\treg = <0x1000 0x440>;\n\t\t\t\t};\n\n\t\t\t\tcalibration_wifi_5000: calibration@5000 {\n\t\t\t\t\treg = <0x5000 0x440>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t};\n};\n\n&UART0 {\n\tstatus = \"okay\";\n};\n\n&GPIO0 {\n\tstatus = \"okay\";\n};\n\n&IIC0 {\n\tstatus = \"okay\";\n\n\tfan0: fan@1b {\n\t\tcompatible = \"microchip,tc654\";\n\t\treg = <0x1b>;\n\t\t#cooling-cells = <2>; /* min followed by max */\n\n\t\tgpios = <&GPIO0 16 GPIO_ACTIVE_LOW>; /* fan status */\n\t\talarm-gpios = <&GPIO0 5 GPIO_ACTIVE_LOW>; /* fault */\n\t\tinterrupt-parent = <&UIC3>;\n\t\tinterrupts = <0x16 IRQ_TYPE_EDGE_FALLING>; /* fault */\n\t};\n\n\ttemp0: temp@4d {\n\t\tcompatible = \"gmt,g781\";\n\t\treg = <0x4d>;\n\t\t#thermal-sensor-cells = <1>;\n\n\t\t/*\n\t\t * The LM90 has two sensors:\n\t\t *   temp0 -> internal to LM90\n\t\t *   temp1 -> external NTC near CPU\n\t\t */\n\t};\n};\n\n\n&EMAC0 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy0>;\n\tfifo-entry-size = <10>;\n\n\tmdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tphy0: ethernet-phy@0 {\n\t\t\tdevice_type = \"ethernet-phy\";\n\t\t\treg = <0>;\n\t\t\tqca,mib-poll-interval = <500>;\n\n\t\t\tqca,ar8327-initvals = <\n\t\t\t\t0x0010 0x40000000\n\t\t\t\t0x0624 0x007f7f7f\n\t\t\t\t0x0004 0x07a00000\t/* PAD0_MODE */\n\t\t\t\t0x000c 0x01000000\t/* PAD6_MODE */\n\t\t\t\t0x007c 0x0000007e\t/* PORT0_STATUS */\n\t\t\t>;\n\t\t};\n\t};\n};\n\n&POB0 {\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"Reset button\";\n\t\t\tgpios = <&GPIO0 15 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tinterrupt-parent = <&UIC1>;\n\t\t\tinterrupts = <0x14 IRQ_TYPE_EDGE_FALLING>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\tbackup_hd {\n\t\t\tlabel = \"Backup HD button\";\n\t\t\tgpios = <&GPIO0 19 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_0>;\n\t\t\tinterrupt-parent = <&UIC1>;\n\t\t\tinterrupts = <0x1e IRQ_TYPE_EDGE_FALLING>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\trfkill {\n\t\t\tlabel = \"RFKILL button\";\n\t\t\tgpios = <&GPIO0 20 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RFKILL>;\n\t\t\tinterrupt-parent = <&UIC1>;\n\t\t\tinterrupts = <0x1f IRQ_TYPE_EDGE_FALLING>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"WPS button\";\n\t\t\tgpios = <&GPIO0 23 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tinterrupt-parent = <&UIC2>;\n\t\t\tinterrupts = <0x19 IRQ_TYPE_EDGE_FALLING>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled-0 {\n\t\t\tcolor = <LED_COLOR_ID_GREEN>;\n\t\t\tfunction = LED_FUNCTION_POWER;\n\t\t\tgpios = <&GPIO0 8 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tled-1 {\n\t\t\tcolor = <LED_COLOR_ID_AMBER>;\n\t\t\tfunction = LED_FUNCTION_FAULT;\n\t\t\tgpios = <&GPIO0 9 GPIO_ACTIVE_LOW>;\n\t\t\tpanic-indicator;\n\t\t};\n\n\t\tled-2 {\n\t\t\tcolor = <LED_COLOR_ID_BLUE>;\n\t\t\tfunction = LED_FUNCTION_USB;\n\t\t\tgpios = <&GPIO0 10 GPIO_ACTIVE_HIGH>;\n\t\t\ttrigger-sources = <&usb2_port 1>, <&usb2_port 2>,\n\t\t\t\t\t  <&usb3_port 1>, <&usb3_port 2>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\n\t\tled-3 {\n\t\t\tcolor = <LED_COLOR_ID_WHITE>;\n\t\t\tfunction = LED_FUNCTION_INDICATOR;\n\t\t\tgpios = <&GPIO0 11 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tled-4 {\n\t\t\tcolor = <LED_COLOR_ID_YELLOW>;\n\t\t\tfunction = LED_FUNCTION_WAN;\n\t\t\tgpios = <&GPIO0 3 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tled-5 {\n\t\t\tcolor = <LED_COLOR_ID_GREEN>;\n\t\t\tfunction = LED_FUNCTION_WAN;\n\t\t\tgpios = <&GPIO0 12 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tled-6 {\n\t\t\tcolor = <LED_COLOR_ID_GREEN>;\n\t\t\tfunction = LED_FUNCTION_DISK;\n\t\t\tgpios = <&GPIO0 14 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"disk-activity\";\n\t\t};\n\n\t\tled-7 {\n\t\t\tcolor = <LED_COLOR_ID_RED>;\n\t\t\tfunction = LED_FUNCTION_DISK_ERR;\n\t\t\tgpios = <&GPIO0 17 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tled-8 {\n\t\t\tcolor = <LED_COLOR_ID_BLUE>;\n\t\t\tfunction = LED_FUNCTION_WLAN;\n\t\t\tgpios = <&GPIO0 18 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\t};\n};\n\n&PCIE0 {\n\tstatus = \"okay\";\n\n\t/*\n\t * relevant lspci topology:\n\t *\n\t *\t-+-[0000:40]---00.0-[41-7f]----00.0-[42-45]--+-02.0-[43]----00.0\n\t *\t                                             +-03.0-[44]----00.0\n\t *\t                                             \\-04.0-[45]----00.0\n\t *\n\t */\n\n\tbridge@64,0 {\n\t\treg = <0x00400000 0 0 0 0>;\n\t\t#address-cells = <3>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tbridge@65,0 {\n\t\t\t/* IDT PES4T4 PCI Express Switch */\n\t\t\tcompatible = \"pci111d,803a\";\n\t\t\treg = <0x00410000 0 0 0 0>;\n\t\t\t#address-cells = <3>;\n\t\t\t#size-cells = <2>;\n\t\t\tranges;\n\n\t\t\tbridge@66,2 {\n\t\t\t\tcompatible = \"pci111d,803a\";\n\t\t\t\treg = <0x00421000 0 0 0 0>;\n\t\t\t\t#address-cells = <3>;\n\t\t\t\t#size-cells = <2>;\n\t\t\t\tranges;\n\n\t\t\t\twifi0: wifi@67,0 {\n\t\t\t\t\t/* Atheros AR9380 5GHz */\n\t\t\t\t\tcompatible = \"pci168c,0030\";\n\t\t\t\t\treg = <0x00430000 0 0 0 0>;\n\t\t\t\t\tinterrupts = <3>; /* INTC */\n\t\t\t\t\tnvmem-cell-names = \"mac-address\", \"calibration\";\n\t\t\t\t\tnvmem-cells = <&macaddr_wifi_0>, <&calibration_wifi_1000>;\n\n\t\t\t\t\t/*\n\t\t\t\t\t * Because this was such a pain.\n\t\t\t\t\t * Here's the full device path:\n\t\t\t\t\t * pci0000:40/0000:40:00.0/0000:41:00.0/0000:42:02.0/0000:43:00.0\n\t\t\t\t\t */\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tbridge@66,3 {\n\t\t\t\tcompatible = \"pci111d,803a\";\n\t\t\t\treg = <0x00421800 0 0 0 0>;\n\t\t\t\t#address-cells = <3>;\n\t\t\t\t#size-cells = <2>;\n\t\t\t\tranges;\n\n\t\t\t\twifi1: wifi@68,0 {\n\t\t\t\t\t/* Atheros AR9381 2.4GHz */\n\t\t\t\t\tcompatible = \"pci168c,0033\";\n\t\t\t\t\treg = <0x00440000 0 0 0 0>;\n\t\t\t\t\tinterrupts = <4>; /* INTD */\n\t\t\t\t\tnvmem-cell-names = \"mac-address\", \"calibration\";\n\t\t\t\t\tnvmem-cells = <&macaddr_wifi_c>, <&calibration_wifi_5000>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tbridge@66,4 {\n\t\t\t\tcompatible = \"pci111d,803a\";\n\t\t\t\treg = <0x00422000 0 0 0 0>;\n\t\t\t\t#address-cells = <3>;\n\t\t\t\t#size-cells = <2>;\n\t\t\t\tranges;\n\n\t\t\t\tusb1: usb@69,0 {\n\t\t\t\t\t/* Renesas uPD720202 */\n\t\t\t\t\tcompatible = \"pci1912,0015\";\n\t\t\t\t\treg = <0x00450000 0 0 0 0>;\n\t\t\t\t\tinterrupts = <1>; /* INTA */\n\n\t\t\t\t\t#address-cells = <1>;\n\t\t\t\t\t#size-cells = <0>;\n\n\t\t\t\t\tusb2_port: port@1 {\n\t\t\t\t\t\treg = <1>;\n\t\t\t\t\t\t#trigger-source-cells = <1>;\n\t\t\t\t\t};\n\n\t\t\t\t\tusb3_port: port@2 {\n\t\t\t\t\t\treg = <2>;\n\t\t\t\t\t\t#trigger-source-cells = <1>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/apm821xx/dts/wd-mybooklive.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-only\n/*\n * Copyright 2008 DENX Software Engineering, Stefan Roese <sr@denx.de>\n * (c) Copyright 2010 Western Digital Technologies, Inc. All Rights Reserved.\n */\n\n/dts-v1/;\n\n#include <dt-bindings/leds/common.h>\n#include \"apm82181.dtsi\"\n\n/ {\n\tcompatible = \"wd,mybooklive\", \"amcc,apollo3g\";\n\tmodel = \"MyBook Live\";\n\n\taliases {\n\t\tserial0 = &UART0;\n\t};\n};\n\n&POB0 {\n\tebc {\n\t\tnor_flash@0,0 {\n\t\t\tstatus = \"okay\";\n\t\t\tcompatible = \"amd,s29gl512n\", \"jedec-probe\", \"cfi-flash\", \"mtd-rom\";\n\t\t\tbank-width = <1>;\n\t\t\treg = <0x00000000 0x00000000 0x00080000>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\t/* Part of bootrom - Don't use it without a jump */\n\t\t\t\tlabel = \"free\";\n\t\t\t\treg = <0x00000000 0x0001e000>;\n\t\t\t};\n\n\t\t\tpartition@1e000 {\n\t\t\t\tlabel = \"env\";\n\t\t\t\treg = <0x0001e000 0x00002000>;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tlabel = \"uboot\";\n\t\t\t\treg = <0x00020000 0x00050000>;\n\t\t\t};\n\t\t};\n\t};\n\n\tGPIO1: gpio@e0000000 {\n\t\tcompatible = \"wd,mbl-gpio\", \"ti,74273\";\n\t\treg-names = \"dat\";\n\t\treg = <0xe0000000 0x1>;\n\t\t#gpio-cells = <2>;\n\t\tgpio-controller;\n\n\t\tenable-button {\n\t\t\t/* Defined in u-boot as: NOT_NOR\n\t\t\t * \"enables features other than NOR\n\t\t\t * specifically, the buffer at CS2\"\n\t\t\t * (button).\n\t\t\t *\n\t\t\t * Note: This option is disabled as\n\t\t\t * it prevents the system from being\n\t\t\t * rebooted successfully.\n\t\t\t */\n\n\t\t\tgpio-hog;\n\t\t\tline-name = \"Enable Reset Button, disable NOR\";\n\t\t\tgpios = <1 GPIO_ACTIVE_HIGH>;\n\t\t\toutput-low;\n\t\t};\n\t};\n\n\tGPIO2: gpio@e0100000 {\n\t\tcompatible = \"wd,mbl-gpio\", \"ti,74244\";\n\t\treg-names = \"dat\";\n\t\treg = <0xe0100000 0x1>;\n\t\t#gpio-cells = <2>;\n\t\tgpio-controller;\n\t\tno-output;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\t/* There's just one tri-color LED with three separate pins.\n\t\t * One pin for each color (red, green and blue). Each has\n\t\t * a different meaning.\n\t\t */\n\t\tled-0 {\n\t\t\tcolor = <LED_COLOR_ID_RED>;\n\t\t\tfunction = LED_FUNCTION_FAULT;\n\t\t\tgpios = <&GPIO1 4 GPIO_ACTIVE_HIGH>;\n\t\t\tpanic-indicator;\n\t\t};\n\n\t\tled-1 {\n\t\t\tcolor = <LED_COLOR_ID_GREEN>;\n\t\t\tfunction = LED_FUNCTION_POWER;\n\t\t\tgpios = <&GPIO1 5 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tled-2 {\n\t\t\tcolor = <LED_COLOR_ID_BLUE>;\n\t\t\tfunction = LED_FUNCTION_DISK;\n\t\t\tgpios = <&GPIO1 6 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"disk-activity\";\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <60>;\t/* 3 * 20 = 60ms */\n\t\tautorepeat;\n\n\t\treset-button {\n\t\t\tlabel = \"Reset button\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&GPIO2 2 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tusbpwr: usb-regulator {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"Power USB Core\";\n\t\tgpios = <&GPIO1 2 GPIO_ACTIVE_HIGH>;\n\t\tregulator-min-microvolt = <5000000>;\n\t\tregulator-max-microvolt = <5000000>;\n\t\tregulator-boot-on; /* uboot sets this */\n\t\tenable-active-high;\n\t};\n\n\tsata1pwr: sata1-regulator {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"Power Drive Port 1\";\n\t\tgpios = <&GPIO1 3 GPIO_ACTIVE_HIGH>;\n\t\tregulator-min-microvolt = <12000000>;\n\t\tregulator-max-microvolt = <12000000>;\n\t\tregulator-boot-on;   /* uboot sets this */\n\t\tregulator-always-on; /* needed to read OS from HDD */\n\t\tenable-active-high;\n\t};\n\n\tsata0pwr: sata0-regulator {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"Power Drive Port 0\";\n\t\tgpios = <&GPIO1 7 GPIO_ACTIVE_HIGH>;\n\t\tregulator-min-microvolt = <12000000>;\n\t\tregulator-max-microvolt = <12000000>;\n\t\tregulator-boot-on;   /* uboot sets this */\n\t\tregulator-always-on; /* needed to read OS from HDD */\n\t\tenable-active-high;\n\t};\n};\n\n&EMAC0 {\n\tstatus = \"okay\";\n\n\tphy-map = <0x2>;\n\tphy-address = <0x1>;\n\tphy-handle = <&phy>;\n\tphy-mode = \"rgmii-id\";\n\n\tmdio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treset-gpios = <&GPIO1 0 GPIO_ACTIVE_LOW>;\n\n\t\tphy: phy@1 {\n\t\t\tcompatible = \"ethernet-phy-ieee802.3-c22\";\n\t\t\treg = <1>;\n\t\t};\n\t};\n};\n\n&CRYPTO {\n\tstatus = \"okay\";\n};\n\n&PKA {\n\tstatus = \"okay\";\n};\n\n&TRNG {\n\tstatus = \"okay\";\n};\n\n&SATA0 {\n\tstatus = \"okay\";\n\n\tdrive0: sata-port@0 {\n\t\treg = <0>;\n\t\t#thermal-sensor-cells = <0>;\n\t};\n};\n\n&SATA1 {\n\tstatus = \"okay\";\n\n\tdrive1: sata-port@0 {\n\t\treg = <0>;\n\t\t#thermal-sensor-cells = <0>;\n\t};\n};\n\n&UART0 {\n\tstatus = \"okay\";\n};\n\n&USBOTG0 {\n\tstatus = \"okay\";\n\tdr_mode = \"host\";\n\tvbus-supply = <&usbpwr>;\n};\n"
  },
  {
    "path": "target/linux/apm821xx/image/Makefile",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n\ninclude $(TOPDIR)/rules.mk\ninclude $(INCLUDE_DIR)/image.mk\n\nDEVICE_VARS += DTB_SIZE\n\ndefine Build/boot-img\n\t$(RM) -rf $@.bootdir\n\tmkdir -p $@.bootdir/boot\n\n\t$(CP) $@.scr $@.bootdir/boot/boot.scr\n\t$(CP) $(IMAGE_KERNEL).dtb $@.bootdir/boot/$(DEVICE_DTB)\n\t$(CP) $(IMAGE_KERNEL) $@.bootdir/boot/uImage\n\n\tgenext2fs --block-size $(BLOCKSIZE:%k=%Ki) \\\n\t\t--size-in-blocks $$((1024 * $(CONFIG_TARGET_KERNEL_PARTSIZE))) \\\n\t\t--root $@.bootdir $@.boot\n\n\t# convert it to revision 1 - needed for u-boot ext2load\n\t$(STAGING_DIR_HOST)/bin/tune2fs -O filetype $@.boot\n\t$(STAGING_DIR_HOST)/bin/e2fsck -pDf $@.boot > /dev/null\nendef\n\ndefine Build/boot-script\n\t$(STAGING_DIR_HOST)/bin/mkimage -A powerpc -T script -C none -n \"$(PROFILE) Boot Script\" \\\n\t\t-d mbl_boot.scr \\\n\t\t$@.scr\nendef\n\ndefine Build/dtb\n\t$(call Image/BuildDTB,../dts/$(DEVICE_DTS).dts,$@.dtb,,--space $(DTB_SIZE))\nendef\n\ndefine Build/export-dtb\n\tcp $(IMAGE_KERNEL).dtb $@\nendef\n\ndefine Build/MuImage-initramfs\n\trm -rf $@.fakerd $@.new\n\n\tdd if=/dev/zero of=$@.fakerd bs=32 count=1 conv=sync\n\n\t# Netgear used an old uboot that doesn't have FIT support.\n\t# So we are stuck with either a full ext2/4 fs in a initrd.\n\t# ... or we try to make the \"multi\" image approach to work\n\t# for us.\n\t#\n\t# Sadly, the \"multi\" image has to consists of three\n\t# \"fixed\" parts in the following \"fixed\" order:\n\t# 1. The kernel which is in $@\n\t# 2. The (fake) initrd which is in $@.fakerd\n\t# 3. The device tree binary which is in $@.dtb\n\t#\n\t# Now, given that we use the function for the kernel which\n\t# already has a initramfs image inside, we still have to\n\t# add a \"fake\" initrd (which a mkimage header) in the second\n\t# part of the legacy multi image. Since we need to put the\n\t# device tree stuff into part 3.\n\n\t-$(STAGING_DIR_HOST)/bin/mkimage -A $(LINUX_KARCH) -O linux -T multi \\\n\t\t-C $(1) -a $(KERNEL_LOADADDR) -e $(KERNEL_ENTRY) \\\n\t\t-n '$(BOARD_NAME) initramfs' -d $@:$@.fakerd:$@.dtb $@.new\n\tmv $@.new $@\n\trm -rf $@.fakerd\nendef\n\ndefine Build/prepend-dtb\n\tcat \"$@.dtb.uimage\" \"$@\" > \"$@.new\"\n\tmv \"$@.new\" \"$@\"\nendef\n\ndefine Image/cpiogz\n\t( cd $(TARGET_DIR); find . | cpio -o -H newc | gzip -9n >$(KDIR_TMP)/$(IMG_PREFIX)-rootfs.cpio.gz )\nendef\n\ndefine Device/Default\n  PROFILES := Default\n  KERNEL_DEPENDS = $$(wildcard ../dts/$$(DEVICE_DTS).dts)\n  DEVICE_DTS :=\n  KERNEL_ENTRY := 0x00000000\n  KERNEL_LOADADDR := 0x00000000\n  DEVICE_DTS_DIR := ../dts\n  DEVICE_DTS = $(subst _,-,$(1))\nendef\n\ninclude $(SUBTARGET).mk\n\n$(eval $(call BuildImage))\n"
  },
  {
    "path": "target/linux/apm821xx/image/mbl_boot.scr",
    "content": "setenv boot_args 'setenv bootargs root=/dev/sda2 rw rootfstype=squashfs,ext4'\nsetenv load_part1 'ext2load sata 0:1 ${kernel_addr_r} /boot/uImage; ext2load sata 0:1 ${fdt_addr_r} /boot/apollo3g.dtb'\nsetenv load_part2 'ext2load sata 1:1 ${kernel_addr_r} /boot/uImage; ext2load sata 1:1 ${fdt_addr_r} /boot/apollo3g.dtb'\nsetenv load_sata 'sata init; if run load_part1; then echo Loaded part 1; elif run load_part2; then echo Loaded part 2; fi'\nsetenv boot_sata 'run load_sata; run boot_args addtty; bootm ${kernel_addr_r} - ${fdt_addr_r}'\nrun boot_sata\n"
  },
  {
    "path": "target/linux/apm821xx/image/mbl_gen_hdd_img.sh",
    "content": "#!/bin/sh\n\nset -x\n[ $# -eq 5 ] || {\n    echo \"SYNTAX: $0 <file> <bootfs image> <rootfs image> <bootfs size> <rootfs size>\"\n    exit 1\n}\n\nOUTPUT=\"$1\"\nBOOTFS=\"$2\"\nROOTFS=\"$3\"\nBOOTFSSIZE=\"$4\"\nROOTFSSIZE=\"$5\"\n\nhead=4\nsect=63\n\nset $(ptgen -o $OUTPUT -h $head -s $sect -l 4096 -t 83 -p ${BOOTFSSIZE}M -t 83 -p ${ROOTFSSIZE}M)\n\nBOOTOFFSET=\"$(($1 / 512))\"\nBOOTSIZE=\"$(($2 / 512))\"\nROOTFSOFFSET=\"$(($3 / 512))\"\nROOTFSSIZE=\"$(($4 / 512))\"\n\ndd bs=512 if=\"$BOOTFS\" of=\"$OUTPUT\" seek=\"$BOOTOFFSET\" conv=notrunc\ndd bs=512 if=\"$ROOTFS\" of=\"$OUTPUT\" seek=\"$ROOTFSOFFSET\" conv=notrunc\n\n"
  },
  {
    "path": "target/linux/apm821xx/image/nand.mk",
    "content": "define Build/create-uImage-dtb\n\t# flat_dt target expect FIT image - which WNDR4700's uboot doesn't support\n\t-$(STAGING_DIR_HOST)/bin/mkimage -A $(LINUX_KARCH) \\\n\t\t-O linux -T kernel -C none \\\n\t\t-n '$(call toupper,$(LINUX_KARCH)) $(VERSION_DIST) Linux-$(LINUX_VERSION)' \\\n\t\t-d \"$@.dtb\" \"$@.dtb.uimage\"\nendef\n\ndefine Build/MerakiAdd-dtb\n\t$(call Image/BuildDTB,../dts/$(DEVICE_DTS).dts,$@.dtb)\n\t( \\\n\t\tdd if=$@.dtb bs=$(DTB_SIZE) conv=sync; \\\n\t\tcat $@ ; \\\n\t) > $@.new\n\t@mv $@.new $@\nendef\n\ndefine Build/MerakiNAND\n\t-$(STAGING_DIR_HOST)/bin/mkmerakifw \\\n\t\t-B $(BOARD_NAME) -s \\\n\t\t-i $@ \\\n\t\t-o $@.new\n\t@cp $@.new $@\nendef\n\n\ndefine Device/meraki_mr24\n  DEVICE_VENDOR := Cisco Meraki\n  DEVICE_MODEL := MR24\n  DEVICE_PACKAGES := kmod-spi-gpio -swconfig\n  BOARD_NAME := mr24\n  IMAGES := sysupgrade.bin\n  DTB_SIZE := 64512\n  IMAGE_SIZE := 8191k\n  KERNEL := kernel-bin | lzma | uImage lzma | MerakiAdd-dtb | MerakiNAND\n  KERNEL_INITRAMFS := kernel-bin | lzma | dtb | MuImage-initramfs lzma\n  IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata\n  UBINIZE_OPTS := -E 5\n  SUPPORTED_DEVICES += mr24\nendef\nTARGET_DEVICES += meraki_mr24\n\ndefine Device/meraki_mx60\n  DEVICE_VENDOR := Cisco Meraki\n  DEVICE_MODEL := MX60\n  DEVICE_ALT0_VENDOR := Cisco Meraki\n  DEVICE_ALT0_MODEL := MX60W\n  DEVICE_PACKAGES := kmod-spi-gpio kmod-usb-ledtrig-usbport kmod-usb-dwc2 \\\n\t\t     kmod-usb-storage block-mount\n  BLOCKSIZE := 128k\n  IMAGES := sysupgrade.bin\n  DTB_SIZE := 20480\n  IMAGE_SIZE := 1021m\n  KERNEL := kernel-bin | gzip | dtb | MuImage-initramfs gzip\n  IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata\n  UBINIZE_OPTS := -E 5\n  DEVICE_COMPAT_VERSION := 2.0\n  DEVICE_COMPAT_MESSAGE := uboot's bootcmd has to be updated to support standard multi-image uImages. \\\n       Upgrade via sysupgrade mechanism is not possible.\nendef\nTARGET_DEVICES += meraki_mx60\n\ndefine Device/netgear_wndap6x0\n  DEVICE_VENDOR := NETGEAR\n  DEVICE_PACKAGES := kmod-eeprom-at24\n  SUBPAGESIZE := 256\n  PAGESIZE := 512\n  BLOCKSIZE := 16k\n  DTB_SIZE := 32768\n  IMAGE_SIZE := 27392k\n  IMAGES := sysupgrade.bin factory.img\n  KERNEL_SIZE := 6080k\n  KERNEL := dtb | kernel-bin | gzip | MuImage-initramfs gzip\n  IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata\n  IMAGE/factory.img := append-kernel | pad-to $$$$(KERNEL_SIZE) | append-ubi\n  UBINIZE_OPTS := -E 5\n  DEVICE_COMPAT_VERSION := 2.0\n  DEVICE_COMPAT_MESSAGE := kernel and ubi partitions had to be resized. \\\n       Upgrade via sysupgrade mechanism is not possible.\nendef\n\ndefine Device/netgear_wndap620\n  $(Device/netgear_wndap6x0)\n  DEVICE_MODEL := WNDAP620 (Premium Wireless-N)\nendef\nTARGET_DEVICES += netgear_wndap620\n\ndefine Device/netgear_wndap660\n  $(Device/netgear_wndap6x0)\n  DEVICE_MODEL := WNDAP660 (Dual Radio Dual Band Wireless-N)\nendef\nTARGET_DEVICES += netgear_wndap660\n\ndefine Device/netgear_wndr4700\n  DEVICE_VENDOR := NETGEAR\n  DEVICE_MODEL := Centria N900 WNDR4700\n  DEVICE_ALT0_VENDOR := NETGEAR\n  DEVICE_ALT0_MODEL := Centria N900 WNDR4720\n  DEVICE_PACKAGES := badblocks block-mount e2fsprogs kmod-hwmon-drivetemp \\\n\tkmod-dm kmod-fs-ext4 kmod-fs-vfat kmod-usb-ledtrig-usbport \\\n\tkmod-md-mod kmod-nls-cp437 kmod-nls-iso8859-1 kmod-nls-iso8859-15 \\\n\tkmod-nls-utf8 kmod-usb3 kmod-usb-dwc2 kmod-usb-storage \\\n\tpartx-utils\n  BOARD_NAME := wndr4700\n  PAGESIZE := 2048\n  SUBPAGESIZE := 512\n  BLOCKSIZE := 128k\n  DTB_SIZE := 131008\n  IMAGE_SIZE := 24960k\n  IMAGES := factory.img sysupgrade.bin\n  ARTIFACTS := device-tree.dtb\n  KERNEL_SIZE := 3584k\n  # append a fake/empty rootfs to fool netgear's uboot\n  # CHECK_DNI_FIRMWARE_ROOTFS_INTEGRITY in do_chk_dniimg()\n  KERNEL := kernel-bin | lzma -d16 | uImage lzma | pad-offset $$(BLOCKSIZE) 64 | \\\n\t    append-uImage-fakehdr filesystem | dtb | create-uImage-dtb | prepend-dtb\n  KERNEL_INITRAMFS := kernel-bin | gzip | dtb | MuImage-initramfs gzip\n  IMAGE/factory.img := append-kernel | pad-to $$$$(KERNEL_SIZE) | append-ubi | \\\n\t\t       netgear-dni | check-size\n  IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata\n  ARTIFACT/device-tree.dtb := export-dtb | uImage none\n  NETGEAR_BOARD_ID := WNDR4700\n  NETGEAR_HW_ID := 29763875+128+256\n  UBINIZE_OPTS := -E 5\n  SUPPORTED_DEVICES += wndr4700\nendef\nTARGET_DEVICES += netgear_wndr4700\n"
  },
  {
    "path": "target/linux/apm821xx/image/sata.mk",
    "content": "define Build/hdd-img\n\t./mbl_gen_hdd_img.sh $@ $@.boot $(IMAGE_ROOTFS) $(CONFIG_TARGET_KERNEL_PARTSIZE) $(CONFIG_TARGET_ROOTFS_PARTSIZE)\nendef\n\n\ndefine Device/wd_mybooklive\n  DEVICE_VENDOR := Western Digital\n  DEVICE_MODEL := My Book Live\n  DEVICE_ALT0_VENDOR := Western Digital\n  DEVICE_ALT0_MODEL := My Book Live Duo\n  DEVICE_PACKAGES := kmod-usb-dwc2 kmod-usb-ledtrig-usbport kmod-usb-storage kmod-fs-vfat wpad-basic-wolfssl\n  SUPPORTED_DEVICES += mbl wd,mybooklive-duo\n  BLOCKSIZE := 1k\n  DTB_SIZE := 16384\n  KERNEL := kernel-bin | dtb | gzip | uImage gzip\n  KERNEL_INITRAMFS := kernel-bin | gzip | dtb | MuImage-initramfs gzip\n  IMAGES := factory.img.gz sysupgrade.img.gz\n  ARTIFACTS := apollo3g.dtb\n  DEVICE_DTB := apollo3g.dtb\n  FILESYSTEMS := ext4 squashfs\n  IMAGE/factory.img.gz := boot-script | boot-img | hdd-img | gzip\n  IMAGE/sysupgrade.img.gz := boot-script | boot-img | hdd-img | gzip | append-metadata\n  ARTIFACT/apollo3g.dtb := export-dtb\nendef\n\nTARGET_DEVICES += wd_mybooklive\n"
  },
  {
    "path": "target/linux/apm821xx/nand/config-default",
    "content": "CONFIG_AT803X_PHY=y\nCONFIG_AR8216_PHY=y\n# CONFIG_SATA_DWC_OLD_DMA is not set\nCONFIG_IKAREM=y\nCONFIG_ATA=y\nCONFIG_ATA_SFF=y\nCONFIG_ATA_BMDMA=y\n# CONFIG_PCI_DISABLE_COMMON_QUIRKS is not set\nCONFIG_SATA_PMP=y\nCONFIG_GENERIC_PHY=y\nCONFIG_SATA_DWC=y\n# CONFIG_SATA_DWC_DEBUG is not set\nCONFIG_SCSI=y\nCONFIG_BLK_DEV_SD=y\nCONFIG_GPIOLIB=y\nCONFIG_GPIO_GENERIC=y\nCONFIG_GPIO_GENERIC_PLATFORM=y\nCONFIG_LEDS_TRIGGER_DISK=y\nCONFIG_RTC_CLASS=y\nCONFIG_RTC_DRV_M48T86=y\nCONFIG_THERMAL=y\nCONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0\nCONFIG_THERMAL_OF=y\nCONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y\nCONFIG_THERMAL_HWMON=y\nCONFIG_HWMON=y\nCONFIG_SENSORS_GPIO_FAN=y\nCONFIG_CMDLINE=\"rootfstype=squashfs noinitrd\"\nCONFIG_MTD_NAND_ECC_SW_BCH=y\nCONFIG_MTD_NAND_NDFC=y\nCONFIG_MTD_RAW_NAND=y\nCONFIG_MTD_UBI=y\nCONFIG_MTD_UBI_BEB_LIMIT=20\nCONFIG_MTD_UBI_BLOCK=y\nCONFIG_MTD_UBI_WL_THRESHOLD=4096\nCONFIG_UBIFS_FS=y\nCONFIG_RTL8366_SMI=y\nCONFIG_RTL8367B_PHY=y\nCONFIG_SENSORS_LM90=y\nCONFIG_SENSORS_TC654=y\nCONFIG_SWCONFIG=y\nCONFIG_SWCONFIG_LEDS=y\n\n"
  },
  {
    "path": "target/linux/apm821xx/nand/profiles/00-default.mk",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2011 OpenWrt.org\n\ndefine Profile/Default\n  NAME:=Default Profile\n  PRIORITY:=1\n  PACKAGES := badblocks block-mount e2fsprogs \\\n\tkmod-dm kmod-fs-ext4 kmod-fs-vfat kmod-usb-ledtrig-usbport \\\n\tkmod-md-mod kmod-nls-cp437 kmod-nls-iso8859-1 kmod-nls-iso8859-15 \\\n\tkmod-nls-utf8 kmod-usb3 kmod-usb-dwc2 kmod-usb-storage \\\n\tkmod-spi-gpio partx-utils\nendef\n\ndefine Profile/Default/Description\n\tDefault package set\nendef\n\n$(eval $(call Profile,Default))\n"
  },
  {
    "path": "target/linux/apm821xx/nand/target.mk",
    "content": "BOARDNAME:=Devices with NAND flash (Routers)\nFEATURES += nand pcie\n\nDEFAULT_PACKAGES += kmod-ath9k swconfig wpad-basic-wolfssl\n\ndefine Target/Description\n\tBuild firmware images for APM821XX boards with NAND flash.\n\tFor routers like the MR24 or the WNDR4700.\nendef\n"
  },
  {
    "path": "target/linux/apm821xx/patches-5.10/100-dwc2-disable-powerdown.patch",
    "content": "From 88ca61467a0897c79b1fbf8f5c30691b43b52613 Mon Sep 17 00:00:00 2001\nFrom: Christian Lamparter <chunkeey@gmail.com>\nDate: Sun, 26 Dec 2021 22:36:29 +0200\nSubject: [PATCH] dwc2: temporary force to be powered up all times\n\nthe APM821xx's onchip dwc2 misbehaves with 5.4 and 5.10\nwhen a USB device gets connected. Instead of announcing\nand setting up the USB devices it crashes and burns with:\n\n[   22.023476] dwc2 4bff80000.usbotg: dwc2_restore_global_registers: no global registers to restore\n[   22.032245] dwc2 4bff80000.usbotg: dwc2_exit_partial_power_down: failed to restore registers\n[   22.040647] dwc2 4bff80000.usbotg: exit partial_power_down failed\n[   22.058765] dwc2 4bff80000.usbotg: HC died; cleaning up\n\nThis is all seemingly fixed with dwc2 from a 5.16-rc6.\n\nSigned-off-by: Christian Lamparter <chunkeey@gmail.com>\n---\n\n--- a/drivers/usb/dwc2/params.c\n+++ b/drivers/usb/dwc2/params.c\n@@ -137,6 +137,7 @@ static void dwc2_set_amcc_params(struct\n \tstruct dwc2_core_params *p = &hsotg->params;\n \n \tp->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT;\n+\tp->power_down = DWC2_POWER_DOWN_PARAM_NONE;\n }\n \n static void dwc2_set_stm32f4x9_fsotg_params(struct dwc2_hsotg *hsotg)\n"
  },
  {
    "path": "target/linux/apm821xx/patches-5.10/201-add-amcc-apollo3g-support.patch",
    "content": "--- a/arch/powerpc/platforms/44x/Kconfig\n+++ b/arch/powerpc/platforms/44x/Kconfig\n@@ -121,6 +121,17 @@ config CANYONLANDS\n \thelp\n \t  This option enables support for the AMCC PPC460EX evaluation board.\n \n+config APOLLO3G\n+\tbool \"Apollo3G\"\n+\tdepends on 44x\n+\tdefault n\n+\tselect PPC44x_SIMPLE\n+\tselect APM821xx\n+\tselect IBM_EMAC_RGMII\n+\tselect 460EX\n+\thelp\n+\t  This option enables support for the AMCC Apollo 3G board.\n+\n config GLACIER\n \tbool \"Glacier\"\n \tdepends on 44x\n--- a/arch/powerpc/platforms/44x/ppc44x_simple.c\n+++ b/arch/powerpc/platforms/44x/ppc44x_simple.c\n@@ -47,6 +47,7 @@ machine_device_initcall(ppc44x_simple, p\n  * board.c file for it rather than adding it to this list.\n  */\n static char *board[] __initdata = {\n+\t\"amcc,apollo3g\",\n \t\"amcc,arches\",\n \t\"amcc,bamboo\",\n \t\"apm,bluestone\",\n"
  },
  {
    "path": "target/linux/apm821xx/patches-5.10/300-fix-atheros-nics-on-apm82181.patch",
    "content": "--- a/arch/powerpc/platforms/4xx/pci.c\n+++ b/arch/powerpc/platforms/4xx/pci.c\n@@ -1060,15 +1060,24 @@ static int __init apm821xx_pciex_init_po\n \tu32 val;\n \n \t/*\n-\t * Do a software reset on PCIe ports.\n-\t * This code is to fix the issue that pci drivers doesn't re-assign\n-\t * bus number for PCIE devices after Uboot\n-\t * scanned and configured all the buses (eg. PCIE NIC IntelPro/1000\n-\t * PT quad port, SAS LSI 1064E)\n+\t * Only reset the PHY when no link is currently established.\n+\t * This is for the Atheros PCIe board which has problems to establish\n+\t * the link (again) after this PHY reset. All other currently tested\n+\t * PCIe boards don't show this problem.\n \t */\n-\n-\tmtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x0);\n-\tmdelay(10);\n+\tval = mfdcri(SDR0, port->sdr_base + PESDRn_LOOP);\n+\tif (!(val & 0x00001000)) {\n+\t\t/*\n+\t\t * Do a software reset on PCIe ports.\n+\t\t * This code is to fix the issue that pci drivers doesn't re-assign\n+\t\t * bus number for PCIE devices after Uboot\n+\t\t * scanned and configured all the buses (eg. PCIE NIC IntelPro/1000\n+\t\t * PT quad port, SAS LSI 1064E)\n+\t\t */\n+\n+\t\tmtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x0);\n+\t\tmdelay(10);\n+\t}\n \n \tif (port->endpoint)\n \t\tval = PTYPE_LEGACY_ENDPOINT << 20;\n@@ -1085,9 +1094,12 @@ static int __init apm821xx_pciex_init_po\n \tmtdcri(SDR0, PESDR0_460EX_L0DRV, 0x00000130);\n \tmtdcri(SDR0, PESDR0_460EX_L0CLK, 0x00000006);\n \n-\tmtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x10000000);\n-\tmdelay(50);\n-\tmtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x30000000);\n+\tval = mfdcri(SDR0, port->sdr_base + PESDRn_LOOP);\n+\tif (!(val & 0x00001000)) {\n+\t\tmtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x10000000);\n+\t\tmdelay(50);\n+\t\tmtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x30000000);\n+\t}\n \n \tmtdcri(SDR0, port->sdr_base + PESDRn_RCSSET,\n \t\tmfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) |\n"
  },
  {
    "path": "target/linux/apm821xx/patches-5.10/301-fix-memory-map-wndr4700.patch",
    "content": "--- a/arch/powerpc/platforms/4xx/pci.c\n+++ b/arch/powerpc/platforms/4xx/pci.c\n@@ -1902,9 +1902,9 @@ static void __init ppc4xx_configure_pcie\n \t\t * if it works\n \t\t */\n \t\tout_le32(mbase + PECFG_PIM0LAL, 0x00000000);\n-\t\tout_le32(mbase + PECFG_PIM0LAH, 0x00000000);\n+\t\tout_le32(mbase + PECFG_PIM0LAH, 0x00000008);\n \t\tout_le32(mbase + PECFG_PIM1LAL, 0x00000000);\n-\t\tout_le32(mbase + PECFG_PIM1LAH, 0x00000000);\n+\t\tout_le32(mbase + PECFG_PIM1LAH, 0x0000000c);\n \t\tout_le32(mbase + PECFG_PIM01SAH, 0xffff0000);\n \t\tout_le32(mbase + PECFG_PIM01SAL, 0x00000000);\n \n"
  },
  {
    "path": "target/linux/apm821xx/patches-5.10/802-usb-xhci-force-msi-renesas-xhci.patch",
    "content": "From a0dc613140bab907a3d5787a7ae7b0638bf674d0 Mon Sep 17 00:00:00 2001\nFrom: Christian Lamparter <chunkeey@gmail.com>\nDate: Thu, 23 Jun 2016 20:28:20 +0200\nSubject: [PATCH] usb: xhci: force MSI for uPD720201 and\n uPD720202\n\nThe APM82181 does not support MSI-X. When probed, it will\nproduce a noisy warning.\n\n---\n drivers/usb/host/pci-quirks.c | 362 ++++++++++++++++++++++++++++++++++++++++++\n 1 file changed, 362 insertions(+)\n\n--- a/drivers/usb/host/xhci-pci.c\n+++ b/drivers/usb/host/xhci-pci.c\n@@ -279,6 +279,7 @@ static void xhci_pci_quirks(struct devic\n \t    pdev->device == 0x0015) {\n \t\txhci->quirks |= XHCI_RESET_ON_RESUME;\n \t\txhci->quirks |= XHCI_ZERO_64B_REGS;\n+\t\txhci->quirks |= XHCI_FORCE_MSI;\n \t}\n \tif (pdev->vendor == PCI_VENDOR_ID_VIA)\n \t\txhci->quirks |= XHCI_RESET_ON_RESUME;\n--- a/drivers/usb/host/xhci.c\n+++ b/drivers/usb/host/xhci.c\n@@ -425,10 +425,14 @@ static int xhci_try_enable_msi(struct us\n \t\tfree_irq(hcd->irq, hcd);\n \thcd->irq = 0;\n \n-\tret = xhci_setup_msix(xhci);\n-\tif (ret)\n-\t\t/* fall back to msi*/\n+\tif (xhci->quirks & XHCI_FORCE_MSI) {\n \t\tret = xhci_setup_msi(xhci);\n+\t} else {\n+\t\tret = xhci_setup_msix(xhci);\n+\t\tif (ret)\n+\t\t\t/* fall back to msi*/\n+\t\t\tret = xhci_setup_msi(xhci);\n+\t}\n \n \tif (!ret) {\n \t\thcd->msi_enabled = 1;\n--- a/drivers/usb/host/xhci.h\n+++ b/drivers/usb/host/xhci.h\n@@ -1895,6 +1895,7 @@ struct xhci_hcd {\n \tstruct xhci_hub\t\tusb2_rhub;\n \tstruct xhci_hub\t\tusb3_rhub;\n \t/* support xHCI 1.0 spec USB2 hardware LPM */\n+#define XHCI_FORCE_MSI\t\t(1 << 24)\n \tunsigned\t\thw_lpm_support:1;\n \t/* Broken Suspend flag for SNPS Suspend resume issue */\n \tunsigned\t\tbroken_suspend:1;\n"
  },
  {
    "path": "target/linux/apm821xx/patches-5.10/803-hwmon-tc654-add-detection-routine.patch",
    "content": "From 694f9bfb8efaef8a33e8992015ff9d0866faf4a2 Mon Sep 17 00:00:00 2001\nFrom: Christian Lamparter <chunkeey@gmail.com>\nDate: Sun, 17 Dec 2017 17:27:15 +0100\nSubject: [PATCH 1/2] hwmon: tc654 add detection routine\n\nThis patch adds a detection routine for the TC654/TC655\nchips.  Both IDs are listed in the Datasheet.\n\nSigned-off-by: Christian Lamparter <chunkeey@gmail.com>\n---\n drivers/hwmon/tc654.c | 29 +++++++++++++++++++++++++++++\n 1 file changed, 29 insertions(+)\n\n--- a/drivers/hwmon/tc654.c\n+++ b/drivers/hwmon/tc654.c\n@@ -55,6 +55,11 @@ enum tc654_regs {\n /* Register data is read (and cached) at most once per second. */\n #define TC654_UPDATE_INTERVAL\t\tHZ\n \n+/* Manufacturer and Version Identification Register Values */\n+#define TC654_MFR_ID_MICROCHIP\t\t0x84\n+#define TC654_VER_ID\t\t\t0x00\n+#define TC655_VER_ID\t\t\t0x01\n+\n struct tc654_data {\n \tstruct i2c_client *client;\n \n@@ -481,6 +486,29 @@ static const struct i2c_device_id tc654_\n \t{}\n };\n \n+static int\n+tc654_detect(struct i2c_client *new_client, struct i2c_board_info *info)\n+{\n+\tstruct i2c_adapter *adapter = new_client->adapter;\n+\tint manufacturer, product;\n+\n+\tif (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA))\n+\t\treturn -ENODEV;\n+\n+\tmanufacturer = i2c_smbus_read_byte_data(new_client, TC654_REG_MFR_ID);\n+\tif (manufacturer != TC654_MFR_ID_MICROCHIP)\n+\t\treturn -ENODEV;\n+\n+\tproduct = i2c_smbus_read_byte_data(new_client, TC654_REG_VER_ID);\n+\tif (!((product == TC654_VER_ID) || (product == TC655_VER_ID)))\n+\t\treturn -ENODEV;\n+\n+\tstrlcpy(info->type, product == TC654_VER_ID ? \"tc654\" : \"tc655\",\n+\t\tI2C_NAME_SIZE);\n+\treturn 0;\n+}\n+\n+\n MODULE_DEVICE_TABLE(i2c, tc654_id);\n \n static struct i2c_driver tc654_driver = {\n@@ -489,6 +517,7 @@ static struct i2c_driver tc654_driver =\n \t\t   },\n \t.probe_new = tc654_probe,\n \t.id_table = tc654_id,\n+\t.detect = tc654_detect,\n };\n \n module_i2c_driver(tc654_driver);\n"
  },
  {
    "path": "target/linux/apm821xx/patches-5.10/804-hwmon-tc654-add-thermal_cooling-device.patch",
    "content": "From 4d49367c5303e3ebd17502a45b74de280f6be539 Mon Sep 17 00:00:00 2001\nFrom: Christian Lamparter <chunkeey@gmail.com>\nDate: Sun, 13 Feb 2022 01:47:33 +0100\nSubject: hwmon: (tc654) Add thermal_cooling device support\n\nAdds thermal_cooling device support to the tc654/tc655\ndriver. This make it possible to integrate it into a\ndevice-tree supported thermal-zone node as a\ncooling device.\n\nI have been using this patch as part of the Netgear WNDR4700\nCentria NAS Router support within OpenWrt since 2016.\n\nSigned-off-by: Christian Lamparter <chunkeey@gmail.com>\nLink: https://lore.kernel.org/r/20220213004733.2421193-1-chunkeey@gmail.com\nSigned-off-by: Guenter Roeck <linux@roeck-us.net>\n---\n--- a/drivers/hwmon/tc654.c\n+++ b/drivers/hwmon/tc654.c\n@@ -15,6 +15,7 @@\n #include <linux/module.h>\n #include <linux/mutex.h>\n #include <linux/slab.h>\n+#include <linux/thermal.h>\n #include <linux/util_macros.h>\n \n enum tc654_regs {\n@@ -384,28 +385,20 @@ static ssize_t pwm_show(struct device *d\n \treturn sprintf(buf, \"%d\\n\", pwm);\n }\n \n-static ssize_t pwm_store(struct device *dev, struct device_attribute *da,\n-\t\t\t const char *buf, size_t count)\n+static int _set_pwm(struct tc654_data *data, unsigned long val)\n {\n-\tstruct tc654_data *data = dev_get_drvdata(dev);\n \tstruct i2c_client *client = data->client;\n-\tunsigned long val;\n \tint ret;\n \n-\tif (kstrtoul(buf, 10, &val))\n-\t\treturn -EINVAL;\n-\tif (val > 255)\n-\t\treturn -EINVAL;\n-\n \tmutex_lock(&data->update_lock);\n \n-\tif (val == 0)\n+\tif (val == 0) {\n \t\tdata->config |= TC654_REG_CONFIG_SDM;\n-\telse\n+\t\tdata->duty_cycle = 0;\n+\t} else {\n \t\tdata->config &= ~TC654_REG_CONFIG_SDM;\n-\n-\tdata->duty_cycle = find_closest(val, tc654_pwm_map,\n-\t\t\t\t\tARRAY_SIZE(tc654_pwm_map));\n+\t\tdata->duty_cycle = val - 1;\n+\t}\n \n \tret = i2c_smbus_write_byte_data(client, TC654_REG_CONFIG, data->config);\n \tif (ret < 0)\n@@ -416,6 +409,24 @@ static ssize_t pwm_store(struct device *\n \n out:\n \tmutex_unlock(&data->update_lock);\n+\treturn ret;\n+}\n+\n+static ssize_t pwm_store(struct device *dev, struct device_attribute *da,\n+\t\t\t const char *buf, size_t count)\n+{\n+\tstruct tc654_data *data = dev_get_drvdata(dev);\n+\tunsigned long val;\n+\tint ret;\n+\n+\tif (kstrtoul(buf, 10, &val))\n+\t\treturn -EINVAL;\n+\tif (val > 255)\n+\t\treturn -EINVAL;\n+\tif (val > 0)\n+\t\tval = find_closest(val, tc654_pwm_map, ARRAY_SIZE(tc654_pwm_map)) + 1;\n+\n+\tret = _set_pwm(data, val);\n \treturn ret < 0 ? ret : count;\n }\n \n@@ -448,6 +459,58 @@ static struct attribute *tc654_attrs[] =\n ATTRIBUTE_GROUPS(tc654);\n \n /*\n+ * thermal cooling device functions\n+ *\n+ * Account for the \"ShutDown Mode (SDM)\" state by offsetting\n+ * the 16 PWM duty cycle states by 1.\n+ *\n+ * State  0 =   0% PWM | Shutdown - Fan(s) are off\n+ * State  1 =  30% PWM | duty_cycle =  0\n+ * State  2 = ~35% PWM | duty_cycle =  1\n+ * [...]\n+ * State 15 = ~95% PWM | duty_cycle = 14\n+ * State 16 = 100% PWM | duty_cycle = 15\n+ */\n+#define TC654_MAX_COOLING_STATE\t16\n+\n+static int tc654_get_max_state(struct thermal_cooling_device *cdev, unsigned long *state)\n+{\n+\t*state = TC654_MAX_COOLING_STATE;\n+\treturn 0;\n+}\n+\n+static int tc654_get_cur_state(struct thermal_cooling_device *cdev, unsigned long *state)\n+{\n+\tstruct tc654_data *data = tc654_update_client(cdev->devdata);\n+\n+\tif (IS_ERR(data))\n+\t\treturn PTR_ERR(data);\n+\n+\tif (data->config & TC654_REG_CONFIG_SDM)\n+\t\t*state = 0;\t/* FAN is off */\n+\telse\n+\t\t*state = data->duty_cycle + 1;\t/* offset PWM States by 1 */\n+\n+\treturn 0;\n+}\n+\n+static int tc654_set_cur_state(struct thermal_cooling_device *cdev, unsigned long state)\n+{\n+\tstruct tc654_data *data = tc654_update_client(cdev->devdata);\n+\n+\tif (IS_ERR(data))\n+\t\treturn PTR_ERR(data);\n+\n+\treturn _set_pwm(data, clamp_val(state, 0, TC654_MAX_COOLING_STATE));\n+}\n+\n+static const struct thermal_cooling_device_ops tc654_fan_cool_ops = {\n+\t.get_max_state = tc654_get_max_state,\n+\t.get_cur_state = tc654_get_cur_state,\n+\t.set_cur_state = tc654_set_cur_state,\n+};\n+\n+/*\n  * device probe and removal\n  */\n \n@@ -477,7 +540,18 @@ static int tc654_probe(struct i2c_client\n \thwmon_dev =\n \t    devm_hwmon_device_register_with_groups(dev, client->name, data,\n \t\t\t\t\t\t   tc654_groups);\n-\treturn PTR_ERR_OR_ZERO(hwmon_dev);\n+\tif (IS_ERR(hwmon_dev))\n+\t\treturn PTR_ERR(hwmon_dev);\n+\n+\tif (IS_ENABLED(CONFIG_THERMAL)) {\n+\t\tstruct thermal_cooling_device *cdev;\n+\n+\t\tcdev = devm_thermal_of_cooling_device_register(dev, dev->of_node, client->name,\n+\t\t\t\t\t\t\t       hwmon_dev, &tc654_fan_cool_ops);\n+\t\treturn PTR_ERR_OR_ZERO(cdev);\n+\t}\n+\n+\treturn 0;\n }\n \n static const struct i2c_device_id tc654_id[] = {\n"
  },
  {
    "path": "target/linux/apm821xx/patches-5.10/900-powerpc-bootwrapper-force-gzip-as-mkimage-s-compress.patch",
    "content": "From c9395ad54e2cabb87d408becc37566f3d8248933 Mon Sep 17 00:00:00 2001\nFrom: Christian Lamparter <chunkeey@gmail.com>\nDate: Sun, 1 Dec 2019 02:08:23 +0100\nSubject: [PATCH] powerpc: bootwrapper: force gzip as mkimage's compression\n method\n\nDue to CONFIG_KERNEL_XZ symbol, the bootwrapper code tries to\ninstruct the mkimage to use the xz compression, which isn't\nsupported. This patch forces the gzip compression, which is\nsupported and doesn't matter because the generated uImage for\nthe apm821xx target gets ignored as the OpenWrt toolchain will\ndo separate U-Boot kernel images for each device individually.\n\nSigned-off-by: Christian Lamparter <chunkeey@gmail.com>\n---\n arch/powerpc/boot/Makefile | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/arch/powerpc/boot/Makefile\n+++ b/arch/powerpc/boot/Makefile\n@@ -250,7 +250,7 @@ compressor-$(CONFIG_KERNEL_LZO) := lzo\n \n # args (to if_changed): 1 = (this rule), 2 = platform, 3 = dts 4=dtb 5=initrd\n quiet_cmd_wrap\t= WRAP    $@\n-      cmd_wrap\t=$(CONFIG_SHELL) $(wrapper) -Z $(compressor-y) -c -o $@ -p $2 \\\n+      cmd_wrap\t=$(CONFIG_SHELL) $(wrapper) -Z gzip -c -o $@ -p $2 \\\n \t\t$(CROSSWRAP) $(if $3, -s $3)$(if $4, -d $4)$(if $5, -i $5) \\\n \t\tvmlinux\n \n"
  },
  {
    "path": "target/linux/apm821xx/patches-5.15/010-hwmon-tc654-add-thermal_cooling-device.patch",
    "content": "From 4d49367c5303e3ebd17502a45b74de280f6be539 Mon Sep 17 00:00:00 2001\nFrom: Christian Lamparter <chunkeey@gmail.com>\nDate: Sun, 13 Feb 2022 01:47:33 +0100\nSubject: hwmon: (tc654) Add thermal_cooling device support\n\nAdds thermal_cooling device support to the tc654/tc655\ndriver. This make it possible to integrate it into a\ndevice-tree supported thermal-zone node as a\ncooling device.\n\nI have been using this patch as part of the Netgear WNDR4700\nCentria NAS Router support within OpenWrt since 2016.\n\nSigned-off-by: Christian Lamparter <chunkeey@gmail.com>\nLink: https://lore.kernel.org/r/20220213004733.2421193-1-chunkeey@gmail.com\nSigned-off-by: Guenter Roeck <linux@roeck-us.net>\n---\n--- a/drivers/hwmon/tc654.c\n+++ b/drivers/hwmon/tc654.c\n@@ -15,6 +15,7 @@\n #include <linux/module.h>\n #include <linux/mutex.h>\n #include <linux/slab.h>\n+#include <linux/thermal.h>\n #include <linux/util_macros.h>\n \n enum tc654_regs {\n@@ -379,28 +380,20 @@ static ssize_t pwm_show(struct device *d\n \treturn sprintf(buf, \"%d\\n\", pwm);\n }\n \n-static ssize_t pwm_store(struct device *dev, struct device_attribute *da,\n-\t\t\t const char *buf, size_t count)\n+static int _set_pwm(struct tc654_data *data, unsigned long val)\n {\n-\tstruct tc654_data *data = dev_get_drvdata(dev);\n \tstruct i2c_client *client = data->client;\n-\tunsigned long val;\n \tint ret;\n \n-\tif (kstrtoul(buf, 10, &val))\n-\t\treturn -EINVAL;\n-\tif (val > 255)\n-\t\treturn -EINVAL;\n-\n \tmutex_lock(&data->update_lock);\n \n-\tif (val == 0)\n+\tif (val == 0) {\n \t\tdata->config |= TC654_REG_CONFIG_SDM;\n-\telse\n+\t\tdata->duty_cycle = 0;\n+\t} else {\n \t\tdata->config &= ~TC654_REG_CONFIG_SDM;\n-\n-\tdata->duty_cycle = find_closest(val, tc654_pwm_map,\n-\t\t\t\t\tARRAY_SIZE(tc654_pwm_map));\n+\t\tdata->duty_cycle = val - 1;\n+\t}\n \n \tret = i2c_smbus_write_byte_data(client, TC654_REG_CONFIG, data->config);\n \tif (ret < 0)\n@@ -411,6 +404,24 @@ static ssize_t pwm_store(struct device *\n \n out:\n \tmutex_unlock(&data->update_lock);\n+\treturn ret;\n+}\n+\n+static ssize_t pwm_store(struct device *dev, struct device_attribute *da,\n+\t\t\t const char *buf, size_t count)\n+{\n+\tstruct tc654_data *data = dev_get_drvdata(dev);\n+\tunsigned long val;\n+\tint ret;\n+\n+\tif (kstrtoul(buf, 10, &val))\n+\t\treturn -EINVAL;\n+\tif (val > 255)\n+\t\treturn -EINVAL;\n+\tif (val > 0)\n+\t\tval = find_closest(val, tc654_pwm_map, ARRAY_SIZE(tc654_pwm_map)) + 1;\n+\n+\tret = _set_pwm(data, val);\n \treturn ret < 0 ? ret : count;\n }\n \n@@ -443,6 +454,58 @@ static struct attribute *tc654_attrs[] =\n ATTRIBUTE_GROUPS(tc654);\n \n /*\n+ * thermal cooling device functions\n+ *\n+ * Account for the \"ShutDown Mode (SDM)\" state by offsetting\n+ * the 16 PWM duty cycle states by 1.\n+ *\n+ * State  0 =   0% PWM | Shutdown - Fan(s) are off\n+ * State  1 =  30% PWM | duty_cycle =  0\n+ * State  2 = ~35% PWM | duty_cycle =  1\n+ * [...]\n+ * State 15 = ~95% PWM | duty_cycle = 14\n+ * State 16 = 100% PWM | duty_cycle = 15\n+ */\n+#define TC654_MAX_COOLING_STATE\t16\n+\n+static int tc654_get_max_state(struct thermal_cooling_device *cdev, unsigned long *state)\n+{\n+\t*state = TC654_MAX_COOLING_STATE;\n+\treturn 0;\n+}\n+\n+static int tc654_get_cur_state(struct thermal_cooling_device *cdev, unsigned long *state)\n+{\n+\tstruct tc654_data *data = tc654_update_client(cdev->devdata);\n+\n+\tif (IS_ERR(data))\n+\t\treturn PTR_ERR(data);\n+\n+\tif (data->config & TC654_REG_CONFIG_SDM)\n+\t\t*state = 0;\t/* FAN is off */\n+\telse\n+\t\t*state = data->duty_cycle + 1;\t/* offset PWM States by 1 */\n+\n+\treturn 0;\n+}\n+\n+static int tc654_set_cur_state(struct thermal_cooling_device *cdev, unsigned long state)\n+{\n+\tstruct tc654_data *data = tc654_update_client(cdev->devdata);\n+\n+\tif (IS_ERR(data))\n+\t\treturn PTR_ERR(data);\n+\n+\treturn _set_pwm(data, clamp_val(state, 0, TC654_MAX_COOLING_STATE));\n+}\n+\n+static const struct thermal_cooling_device_ops tc654_fan_cool_ops = {\n+\t.get_max_state = tc654_get_max_state,\n+\t.get_cur_state = tc654_get_cur_state,\n+\t.set_cur_state = tc654_set_cur_state,\n+};\n+\n+/*\n  * device probe and removal\n  */\n \n@@ -472,7 +535,18 @@ static int tc654_probe(struct i2c_client\n \thwmon_dev =\n \t    devm_hwmon_device_register_with_groups(dev, client->name, data,\n \t\t\t\t\t\t   tc654_groups);\n-\treturn PTR_ERR_OR_ZERO(hwmon_dev);\n+\tif (IS_ERR(hwmon_dev))\n+\t\treturn PTR_ERR(hwmon_dev);\n+\n+\tif (IS_ENABLED(CONFIG_THERMAL)) {\n+\t\tstruct thermal_cooling_device *cdev;\n+\n+\t\tcdev = devm_thermal_of_cooling_device_register(dev, dev->of_node, client->name,\n+\t\t\t\t\t\t\t       hwmon_dev, &tc654_fan_cool_ops);\n+\t\treturn PTR_ERR_OR_ZERO(cdev);\n+\t}\n+\n+\treturn 0;\n }\n \n static const struct i2c_device_id tc654_id[] = {\n"
  },
  {
    "path": "target/linux/apm821xx/patches-5.15/201-add-amcc-apollo3g-support.patch",
    "content": "--- a/arch/powerpc/platforms/44x/Kconfig\n+++ b/arch/powerpc/platforms/44x/Kconfig\n@@ -121,6 +121,17 @@ config CANYONLANDS\n \thelp\n \t  This option enables support for the AMCC PPC460EX evaluation board.\n \n+config APOLLO3G\n+\tbool \"Apollo3G\"\n+\tdepends on 44x\n+\tdefault n\n+\tselect PPC44x_SIMPLE\n+\tselect APM821xx\n+\tselect IBM_EMAC_RGMII\n+\tselect 460EX\n+\thelp\n+\t  This option enables support for the AMCC Apollo 3G board.\n+\n config GLACIER\n \tbool \"Glacier\"\n \tdepends on 44x\n--- a/arch/powerpc/platforms/44x/ppc44x_simple.c\n+++ b/arch/powerpc/platforms/44x/ppc44x_simple.c\n@@ -47,6 +47,7 @@ machine_device_initcall(ppc44x_simple, p\n  * board.c file for it rather than adding it to this list.\n  */\n static char *board[] __initdata = {\n+\t\"amcc,apollo3g\",\n \t\"amcc,arches\",\n \t\"amcc,bamboo\",\n \t\"apm,bluestone\",\n"
  },
  {
    "path": "target/linux/apm821xx/patches-5.15/300-fix-atheros-nics-on-apm82181.patch",
    "content": "--- a/arch/powerpc/platforms/4xx/pci.c\n+++ b/arch/powerpc/platforms/4xx/pci.c\n@@ -1060,15 +1060,24 @@ static int __init apm821xx_pciex_init_po\n \tu32 val;\n \n \t/*\n-\t * Do a software reset on PCIe ports.\n-\t * This code is to fix the issue that pci drivers doesn't re-assign\n-\t * bus number for PCIE devices after Uboot\n-\t * scanned and configured all the buses (eg. PCIE NIC IntelPro/1000\n-\t * PT quad port, SAS LSI 1064E)\n+\t * Only reset the PHY when no link is currently established.\n+\t * This is for the Atheros PCIe board which has problems to establish\n+\t * the link (again) after this PHY reset. All other currently tested\n+\t * PCIe boards don't show this problem.\n \t */\n-\n-\tmtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x0);\n-\tmdelay(10);\n+\tval = mfdcri(SDR0, port->sdr_base + PESDRn_LOOP);\n+\tif (!(val & 0x00001000)) {\n+\t\t/*\n+\t\t * Do a software reset on PCIe ports.\n+\t\t * This code is to fix the issue that pci drivers doesn't re-assign\n+\t\t * bus number for PCIE devices after Uboot\n+\t\t * scanned and configured all the buses (eg. PCIE NIC IntelPro/1000\n+\t\t * PT quad port, SAS LSI 1064E)\n+\t\t */\n+\n+\t\tmtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x0);\n+\t\tmdelay(10);\n+\t}\n \n \tif (port->endpoint)\n \t\tval = PTYPE_LEGACY_ENDPOINT << 20;\n@@ -1085,9 +1094,12 @@ static int __init apm821xx_pciex_init_po\n \tmtdcri(SDR0, PESDR0_460EX_L0DRV, 0x00000130);\n \tmtdcri(SDR0, PESDR0_460EX_L0CLK, 0x00000006);\n \n-\tmtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x10000000);\n-\tmdelay(50);\n-\tmtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x30000000);\n+\tval = mfdcri(SDR0, port->sdr_base + PESDRn_LOOP);\n+\tif (!(val & 0x00001000)) {\n+\t\tmtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x10000000);\n+\t\tmdelay(50);\n+\t\tmtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x30000000);\n+\t}\n \n \tmtdcri(SDR0, port->sdr_base + PESDRn_RCSSET,\n \t\tmfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) |\n"
  },
  {
    "path": "target/linux/apm821xx/patches-5.15/301-fix-memory-map-wndr4700.patch",
    "content": "--- a/arch/powerpc/platforms/4xx/pci.c\n+++ b/arch/powerpc/platforms/4xx/pci.c\n@@ -1902,9 +1902,9 @@ static void __init ppc4xx_configure_pcie\n \t\t * if it works\n \t\t */\n \t\tout_le32(mbase + PECFG_PIM0LAL, 0x00000000);\n-\t\tout_le32(mbase + PECFG_PIM0LAH, 0x00000000);\n+\t\tout_le32(mbase + PECFG_PIM0LAH, 0x00000008);\n \t\tout_le32(mbase + PECFG_PIM1LAL, 0x00000000);\n-\t\tout_le32(mbase + PECFG_PIM1LAH, 0x00000000);\n+\t\tout_le32(mbase + PECFG_PIM1LAH, 0x0000000c);\n \t\tout_le32(mbase + PECFG_PIM01SAH, 0xffff0000);\n \t\tout_le32(mbase + PECFG_PIM01SAL, 0x00000000);\n \n"
  },
  {
    "path": "target/linux/apm821xx/patches-5.15/900-powerpc-bootwrapper-force-gzip-as-mkimage-s-compress.patch",
    "content": "From c9395ad54e2cabb87d408becc37566f3d8248933 Mon Sep 17 00:00:00 2001\nFrom: Christian Lamparter <chunkeey@gmail.com>\nDate: Sun, 1 Dec 2019 02:08:23 +0100\nSubject: [PATCH] powerpc: bootwrapper: force gzip as mkimage's compression\n method\n\nDue to CONFIG_KERNEL_XZ symbol, the bootwrapper code tries to\ninstruct the mkimage to use the xz compression, which isn't\nsupported. This patch forces the gzip compression, which is\nsupported and doesn't matter because the generated uImage for\nthe apm821xx target gets ignored as the OpenWrt toolchain will\ndo separate U-Boot kernel images for each device individually.\n\nSigned-off-by: Christian Lamparter <chunkeey@gmail.com>\n---\n arch/powerpc/boot/Makefile | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/arch/powerpc/boot/Makefile\n+++ b/arch/powerpc/boot/Makefile\n@@ -257,7 +257,7 @@ compressor-$(CONFIG_KERNEL_LZO) := lzo\n \n # args (to if_changed): 1 = (this rule), 2 = platform, 3 = dts 4=dtb 5=initrd\n quiet_cmd_wrap\t= WRAP    $@\n-      cmd_wrap\t=$(CONFIG_SHELL) $(wrapper) -Z $(compressor-y) -c -o $@ -p $2 \\\n+      cmd_wrap\t=$(CONFIG_SHELL) $(wrapper) -Z gzip -c -o $@ -p $2 \\\n \t\t$(CROSSWRAP) $(if $3, -s $3)$(if $4, -d $4)$(if $5, -i $5) \\\n \t\tvmlinux\n \n"
  },
  {
    "path": "target/linux/apm821xx/sata/config-default",
    "content": "CONFIG_APOLLO3G=y\nCONFIG_BROADCOM_PHY=y\nCONFIG_EXT4_FS=y\n# CONFIG_SATA_DWC_OLD_DMA is not set\nCONFIG_ATA=y\nCONFIG_ATA_SFF=y\nCONFIG_ATA_BMDMA=y\nCONFIG_SATA_PMP=y\nCONFIG_GENERIC_PHY=y\nCONFIG_SATA_DWC=y\n# CONFIG_SATA_DWC_DEBUG is not set\nCONFIG_CRYPTO_MD5_PPC=y\nCONFIG_CRYPTO_SHA1_PPC=y\nCONFIG_EXT4_FS=y\nCONFIG_F2FS_FS=y\nCONFIG_FREEZER=y\nCONFIG_FW_CACHE=y\nCONFIG_SCSI=y\nCONFIG_BLK_DEV_SD=y\nCONFIG_BLK_PM=y\nCONFIG_GPIOLIB=y\nCONFIG_GPIO_GENERIC=y\nCONFIG_GPIO_GENERIC_PLATFORM=y\nCONFIG_GPIO_74XX_MMIO=y\nCONFIG_LEDS_TRIGGER_DISK=y\nCONFIG_BLK_DEV_LOOP=y\nCONFIG_BLK_DEV_DM=y\nCONFIG_BLK_DEV_DM_BUILTIN=y\nCONFIG_BLK_DEV_MD=y\nCONFIG_MD=y\nCONFIG_MD_AUTODETECT=y\n# CONFIG_MD_LINEAR is not set\n# CONFIG_MD_MULTIPATH is not set\nCONFIG_MD_RAID0=y\nCONFIG_MD_RAID1=y\n# CONFIG_MD_RAID10 is not set\n# CONFIG_MD_RAID456 is not set\nCONFIG_PM=y\nCONFIG_PM_AUTOSLEEP=y\nCONFIG_PM_CLK=y\nCONFIG_PM_SLEEP=y\nCONFIG_PM_WAKELOCKS=y\nCONFIG_PM_WAKELOCKS_GC=y\nCONFIG_PM_WAKELOCKS_LIMIT=100\nCONFIG_PPC_EARLY_DEBUG=y\nCONFIG_PPC_EARLY_DEBUG_44x=y\n# CONFIG_PPC_EARLY_DEBUG_MEMCONS is not set\nCONFIG_PPC_EARLY_DEBUG_44x_PHYSHIGH=0x4\nCONFIG_PPC_EARLY_DEBUG_44x_PHYSLOW=0xef600300\nCONFIG_PPC4xx_CPM=y\nCONFIG_REGULATOR_FIXED_VOLTAGE=y\nCONFIG_SUSPEND=y\nCONFIG_SUSPEND_FREEZER=y\n"
  },
  {
    "path": "target/linux/apm821xx/sata/profiles/00-default.mk",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2011 OpenWrt.org\n\ndefine Profile/Default\n  NAME:=Default Profile\n  PRIORITY:=1\n  PACKAGES := kmod-usb-dwc2 kmod-usb-ledtrig-usbport kmod-usb-storage kmod-fs-vfat wpad-basic-wolfssl\nendef\n\ndefine Profile/Default/Description\n\tDefault package set\nendef\n\n$(eval $(call Profile,Default))\n"
  },
  {
    "path": "target/linux/apm821xx/sata/target.mk",
    "content": "BOARDNAME := Devices which boot from SATA (NAS)\nDEVICE_TYPE := nas\nFEATURES += boot-part ext4 rootfs-part\nDEFAULT_PACKAGES += badblocks block-mount e2fsprogs kmod-hwmon-drivetemp \\\n\t\t    kmod-dm kmod-md-mod partx-utils mkf2fs f2fsck\n\ndefine Target/Description\n\tBuild firmware images for APM82181 boards that boot from SATA.\n\tFor NAS like the MyBook Live Series.\nendef\n"
  },
  {
    "path": "target/linux/archs38/Makefile",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2016 OpenWrt.org\n\ninclude $(TOPDIR)/rules.mk\n\nARCH:=arc\nCPU_TYPE:=archs\nBOARD:=archs38\nBOARDNAME:=Synopsys DesignWare ARC HS38\nSUBTARGETS:=generic\n\nKERNEL_PATCHVER:=5.10\n\nDEVICE_TYPE:=basic\n\ndefine Target/Description\n\tSynopsys DesignWare boards\nendef\n\ninclude $(INCLUDE_DIR)/target.mk\n\n$(eval $(call BuildTarget))\n"
  },
  {
    "path": "target/linux/archs38/base-files/etc/board.d/02_network",
    "content": "#\n# Copyright (C) 2016 OpenWrt.org\n#\n\n. /lib/functions/uci-defaults.sh\n\nboard_config_update\n\ncase \"$(board_name)\" in\nsnps,axs103|\\\nsnps,hsdk)\n\tucidef_set_interface_lan \"eth0\" \"dhcp\"\n\t;;\nesac\n\nboard_config_flush\n\nexit 0\n"
  },
  {
    "path": "target/linux/archs38/config-5.10",
    "content": "# CONFIG_16KSTACKS is not set\nCONFIG_ARC=y\nCONFIG_ARCH_32BIT_OFF_T=y\nCONFIG_ARCH_HAS_CACHE_LINE_SIZE=y\nCONFIG_ARCH_HAS_DMA_COHERENT_TO_PFN=y\nCONFIG_ARCH_HAS_DMA_PREP_COHERENT=y\nCONFIG_ARCH_HAS_PTE_SPECIAL=y\nCONFIG_ARCH_HAS_SETUP_DMA_OPS=y\nCONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU=y\nCONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y\nCONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y\nCONFIG_ARC_BUILTIN_DTB_NAME=\"\"\nCONFIG_ARC_CACHE=y\nCONFIG_ARC_CACHE_LINE_SHIFT=6\nCONFIG_ARC_CACHE_PAGES=y\nCONFIG_ARC_CPU_HS=y\nCONFIG_ARC_CURR_IN_REG=y\nCONFIG_ARC_DBG=y\n# CONFIG_ARC_DBG_TLB_PARANOIA is not set\nCONFIG_ARC_DW2_UNWIND=y\nCONFIG_ARC_HAS_ACCL_REGS=y\nCONFIG_ARC_HAS_DCACHE=y\n# CONFIG_ARC_HAS_DCCM is not set\nCONFIG_ARC_HAS_DIV_REM=y\nCONFIG_ARC_HAS_ICACHE=y\n# CONFIG_ARC_HAS_ICCM is not set\nCONFIG_ARC_HAS_LL64=y\nCONFIG_ARC_HAS_LLSC=y\n# CONFIG_ARC_HAS_PAE40 is not set\nCONFIG_ARC_HAS_SWAPE=y\nCONFIG_ARC_IRQ_NO_AUTOSAVE=y\nCONFIG_ARC_KVADDR_SIZE=256\nCONFIG_ARC_MCIP=y\n# CONFIG_ARC_METAWARE_HLINK is not set\nCONFIG_ARC_MMU_V4=y\n# CONFIG_ARC_PAGE_SIZE_16K is not set\n# CONFIG_ARC_PAGE_SIZE_4K is not set\nCONFIG_ARC_PAGE_SIZE_8K=y\nCONFIG_ARC_PLAT_AXS10X=y\n# CONFIG_ARC_PLAT_EZNPS is not set\n# CONFIG_ARC_PLAT_TB10X is not set\n# CONFIG_ARC_SMP_HALT_ON_RESET is not set\nCONFIG_ARC_SOC_HSDK=y\nCONFIG_ARC_TIMERS=y\nCONFIG_ARC_TIMERS_64BIT=y\nCONFIG_ARC_USE_UNALIGNED_MEM_ACCESS=y\nCONFIG_AXS103=y\nCONFIG_BLK_DEV_RAM=y\nCONFIG_BLK_DEV_RAM_COUNT=16\nCONFIG_BLK_DEV_RAM_SIZE=4096\nCONFIG_BLK_DEV_SD=y\nCONFIG_BLK_SCSI_REQUEST=y\nCONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0\nCONFIG_CC_DISABLE_WARN_MAYBE_UNINITIALIZED=y\nCONFIG_CC_HAS_KASAN_GENERIC=y\nCONFIG_CLKDEV_LOOKUP=y\nCONFIG_CC_OPTIMIZE_FOR_PERFORMANCE_O3=y\nCONFIG_CLK_HSDK=y\nCONFIG_ARC_TUNE_MCPU=\"\"\nCONFIG_ARC_DSP_NONE=y\n# CONFIG_ARC_FPU_SAVE_RESTORE is not set\n# CONFIG_ARC_DSP_KERNEL is not set\n# CONFIG_ARC_DSP_USERSPACE is not set\n# CONFIG_ARC_DSP_AGU_USERSPACE is not set\n# CONFIG_ARC_LPB_DISABLE is not set\n# CONFIG_SPI_DW_DMA is not set\nCONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y\n# CONFIG_HARDENED_USERCOPY is not set\nCONFIG_CLONE_BACKWARDS=y\nCONFIG_COMMON_CLK=y\nCONFIG_COMPAT_32BIT_TIME=y\nCONFIG_CPU_RMAP=y\nCONFIG_CRC16=y\nCONFIG_CRYPTO_CRC32C=y\nCONFIG_CRYPTO_DRBG=y\nCONFIG_CRYPTO_DRBG_HMAC=y\nCONFIG_CRYPTO_DRBG_MENU=y\nCONFIG_CRYPTO_ECHAINIV=y\nCONFIG_CRYPTO_HMAC=y\nCONFIG_CRYPTO_JITTERENTROPY=y\nCONFIG_CRYPTO_LIB_SHA256=y\nCONFIG_CRYPTO_NULL=y\nCONFIG_CRYPTO_RNG=y\nCONFIG_CRYPTO_RNG2=y\nCONFIG_CRYPTO_RNG_DEFAULT=y\nCONFIG_CRYPTO_SHA256=y\nCONFIG_DMADEVICES=y\nCONFIG_DMA_DIRECT_REMAP=y\nCONFIG_DMA_ENGINE=y\nCONFIG_DMA_OF=y\nCONFIG_DMA_REMAP=y\nCONFIG_DMA_VIRTUAL_CHANNELS=y\nCONFIG_DTC=y\nCONFIG_DWMAC_ANARION=y\nCONFIG_DWMAC_GENERIC=y\nCONFIG_DW_APB_ICTL=y\nCONFIG_DW_AXI_DMAC=y\nCONFIG_EXT4_FS=y\n# CONFIG_EZNPS_GIC is not set\nCONFIG_FAT_FS=y\nCONFIG_FB=y\nCONFIG_FB_CMDLINE=y\nCONFIG_FIXED_PHY=y\nCONFIG_FS_IOMAP=y\nCONFIG_FS_MBCACHE=y\nCONFIG_FS_POSIX_ACL=y\nCONFIG_FW_LOADER_PAGED_BUF=y\nCONFIG_GENERIC_ALLOCATOR=y\nCONFIG_GENERIC_CLOCKEVENTS=y\nCONFIG_GENERIC_CSUM=y\nCONFIG_GENERIC_FIND_FIRST_BIT=y\nCONFIG_GENERIC_IRQ_CHIP=y\nCONFIG_GENERIC_IRQ_SHOW=y\nCONFIG_GENERIC_PCI_IOMAP=y\nCONFIG_GENERIC_PENDING_IRQ=y\nCONFIG_GENERIC_SCHED_CLOCK=y\nCONFIG_GENERIC_SMP_IDLE_THREAD=y\nCONFIG_GPIOLIB=y\nCONFIG_GPIO_DWAPB=y\nCONFIG_GPIO_GENERIC=y\nCONFIG_GPIO_SNPS_CREG=y\nCONFIG_GRACE_PERIOD=y\nCONFIG_HANDLE_DOMAIN_IRQ=y\nCONFIG_HAS_DMA=y\nCONFIG_HAS_IOMEM=y\nCONFIG_HAVE_ARCH_KGDB=y\nCONFIG_HAVE_ARCH_TRACEHOOK=y\nCONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y\nCONFIG_HAVE_CLK=y\nCONFIG_HAVE_CLK_PREPARE=y\nCONFIG_HAVE_DEBUG_STACKOVERFLOW=y\nCONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y\nCONFIG_HAVE_FUTEX_CMPXCHG=y\nCONFIG_HAVE_IOREMAP_PROT=y\nCONFIG_HAVE_MOD_ARCH_SPECIFIC=y\nCONFIG_HAVE_NET_DSA=y\nCONFIG_HAVE_OPROFILE=y\nCONFIG_HAVE_PCI=y\nCONFIG_HAVE_PERF_EVENTS=y\nCONFIG_HZ_PERIODIC=y\nCONFIG_I2C=y\nCONFIG_I2C_BOARDINFO=y\nCONFIG_IIO=y\nCONFIG_IIO_BUFFER=y\nCONFIG_IIO_KFIFO_BUF=y\nCONFIG_IIO_ST_PRESS=y\nCONFIG_IIO_ST_PRESS_I2C=y\nCONFIG_IIO_ST_PRESS_SPI=y\nCONFIG_IIO_ST_SENSORS_CORE=y\nCONFIG_IIO_ST_SENSORS_I2C=y\nCONFIG_IIO_ST_SENSORS_SPI=y\nCONFIG_IIO_TRIGGER=y\nCONFIG_IIO_TRIGGERED_BUFFER=y\nCONFIG_IKCONFIG=y\nCONFIG_IKCONFIG_PROC=y\nCONFIG_INITRAMFS_SOURCE=\"\"\nCONFIG_IRQCHIP=y\nCONFIG_IRQ_DOMAIN=y\nCONFIG_IRQ_WORK=y\n# CONFIG_ISA_ARCOMPACT is not set\nCONFIG_ISA_ARCV2=y\nCONFIG_JBD2=y\nCONFIG_KALLSYMS=y\nCONFIG_KERNEL_GZIP=y\nCONFIG_LIBFDT=y\nCONFIG_LINUX_LINK_BASE=0x90000000\nCONFIG_LINUX_RAM_BASE=0x80000000\nCONFIG_LOCKD=y\nCONFIG_LOCKUP_DETECTOR=y\nCONFIG_LOCK_DEBUGGING_SUPPORT=y\nCONFIG_LOCK_SPIN_ON_OWNER=y\nCONFIG_MDIO_BUS=y\nCONFIG_MDIO_DEVICE=y\nCONFIG_MEMFD_CREATE=y\nCONFIG_MFD_SYSCON=y\nCONFIG_MICREL_PHY=y\nCONFIG_MIGRATION=y\nCONFIG_MMC=y\nCONFIG_MMC_BLOCK=y\nCONFIG_MMC_DW=y\n# CONFIG_MMC_DW_BLUEFIELD is not set\n# CONFIG_MMC_DW_EXYNOS is not set\n# CONFIG_MMC_DW_HI3798CV200 is not set\n# CONFIG_MMC_DW_K3 is not set\nCONFIG_MMC_DW_PLTFM=y\nCONFIG_MMC_SDHCI=y\nCONFIG_MMC_SDHCI_PLTFM=y\nCONFIG_MODULES_TREE_LOOKUP=y\nCONFIG_MODULES_USE_ELF_RELA=y\nCONFIG_MTD_SPI_NOR=y\nCONFIG_MUTEX_SPIN_ON_OWNER=y\nCONFIG_NAMESPACES=y\nCONFIG_NATIONAL_PHY=y\nCONFIG_NEED_DMA_MAP_STATE=y\nCONFIG_NET_FLOW_LIMIT=y\nCONFIG_NET_NS=y\nCONFIG_NET_PTP_CLASSIFY=y\nCONFIG_NFS_ACL_SUPPORT=y\nCONFIG_NFS_FS=y\nCONFIG_NFS_V3_ACL=y\nCONFIG_NLS=y\nCONFIG_NLS_CODEPAGE_437=y\nCONFIG_NLS_ISO8859_1=y\nCONFIG_NO_IOPORT_MAP=y\nCONFIG_NR_CPUS=4\nCONFIG_OF=y\nCONFIG_OF_ADDRESS=y\nCONFIG_OF_EARLY_FLATTREE=y\nCONFIG_OF_FLATTREE=y\nCONFIG_OF_GPIO=y\nCONFIG_OF_IRQ=y\nCONFIG_OF_KOBJ=y\nCONFIG_OF_MDIO=y\nCONFIG_OF_NET=y\nCONFIG_PADATA=y\nCONFIG_PAGE_POOL=y\nCONFIG_PGTABLE_LEVELS=2\nCONFIG_PHYLIB=y\nCONFIG_PHYLINK=y\nCONFIG_PPS=y\nCONFIG_PREEMPT=y\nCONFIG_PREEMPTION=y\nCONFIG_PREEMPT_COUNT=y\n# CONFIG_PREEMPT_NONE is not set\nCONFIG_PREEMPT_RCU=y\n# CONFIG_PREVENT_FIRMWARE_BUILD is not set\nCONFIG_PTP_1588_CLOCK=y\nCONFIG_RATIONAL=y\nCONFIG_REGMAP=y\nCONFIG_REGMAP_I2C=y\nCONFIG_REGMAP_MMIO=y\nCONFIG_REGMAP_SPI=y\nCONFIG_RESET_AXS10X=y\nCONFIG_RESET_CONTROLLER=y\nCONFIG_RESET_HSDK=y\nCONFIG_RESET_SIMPLE=y\nCONFIG_RFS_ACCEL=y\nCONFIG_RPS=y\nCONFIG_RWSEM_SPIN_ON_OWNER=y\nCONFIG_SCSI=y\nCONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y\nCONFIG_SERIAL_8250_DW=y\nCONFIG_SERIAL_8250_DWLIB=y\nCONFIG_SERIAL_8250_NR_UARTS=4\nCONFIG_SERIAL_8250_RUNTIME_UARTS=4\nCONFIG_SERIAL_ARC=y\nCONFIG_SERIAL_ARC_CONSOLE=y\nCONFIG_SERIAL_ARC_NR_PORTS=1\nCONFIG_SERIAL_MCTRL_GPIO=y\nCONFIG_SERIAL_OF_PLATFORM=y\nCONFIG_SG_POOL=y\nCONFIG_SMP=y\nCONFIG_SOFTLOCKUP_DETECTOR=y\nCONFIG_SPI=y\nCONFIG_SPI_DESIGNWARE=y\nCONFIG_SPI_DW_MMIO=y\nCONFIG_SPI_MASTER=y\nCONFIG_SPI_MEM=y\nCONFIG_SRCU=y\nCONFIG_STACKTRACE=y\n# CONFIG_STANDALONE is not set\nCONFIG_STMMAC_ETH=y\nCONFIG_STMMAC_PLATFORM=y\n# CONFIG_STMMAC_SELFTESTS is not set\nCONFIG_SUNRPC=y\nCONFIG_SWPHY=y\nCONFIG_TASKS_RCU=y\nCONFIG_TICK_CPU_ACCOUNTING=y\nCONFIG_TIMER_OF=y\nCONFIG_TIMER_PROBE=y\nCONFIG_TI_ADC108S102=y\nCONFIG_TREE_SRCU=y\nCONFIG_UNINLINE_SPIN_UNLOCK=y\nCONFIG_USB_SUPPORT=y\n# CONFIG_USER_NS is not set\nCONFIG_VFAT_FS=y\nCONFIG_WATCHDOG_CORE=y\nCONFIG_XPS=y\n"
  },
  {
    "path": "target/linux/archs38/generic/profiles/00-default.mk",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2016 OpenWrt.org\n\ndefine Profile/Default\n\tNAME:=Default Profile (all drivers)\n\tPACKAGES:= kmod-usb2 kmod-ath9k-htc wpad-basic-wolfssl\nendef\n\ndefine Profile/Default/Description\n\tDefault package set compatible with most boards.\nendef\n$(eval $(call Profile,Default))\n"
  },
  {
    "path": "target/linux/archs38/generic/target.mk",
    "content": "BOARDNAME:=Generic\nFEATURES += ext4 usb ramdisk\n\ndefine Target/Description\n\tBuild firmware images for ARC HS38 based boards.\nendef\n\n\n"
  },
  {
    "path": "target/linux/archs38/image/Config.in",
    "content": "config AXS10X_SD_BOOT_PARTSIZE\n\tint \"Boot (SD Card) filesystem partition size (in MB)\"\n\tdepends on TARGET_archs38\n\tdefault 20\n\n"
  },
  {
    "path": "target/linux/archs38/image/Makefile",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2016 OpenWrt.org\n\ninclude $(TOPDIR)/rules.mk\ninclude $(INCLUDE_DIR)/image.mk\n\n# On ARC initramfs is put before entry point and so entry point moves\n# in memory from build to built. Thus we need to extract EP from vmlinux\n# every time before generation of uImage.\nkernel_ep = `$(KERNEL_CROSS)readelf -h $(1) | grep \"Entry point address\" | grep -o 0x.*`\n\ndefine Build/patch-dtb\n\t$(STAGING_DIR_HOST)/bin/patch-dtb $@ $(DTS_DIR)/$(DEVICE_DTS).dtb\nendef\n\nifneq ($(CONFIG_TARGET_ROOTFS_INITRAMFS),)\n# Root FS built-in\ndefine Device/vmlinux\n\tKERNEL_SUFFIX := .elf\n\tKERNEL := kernel-bin | patch-dtb\n\tKERNEL_INITRAMFS_NAME = vmlinux-initramfs.elf\nendef\n\ndefine Device/nsim_hs\n\t$(call Device/vmlinux)\n\tDEVICE_VENDOR := Synopsys\n\tDEVICE_MODEL := nSIM HS\n\tDEVICE_PROFILE := nsim_hs\n\tDEVICE_DTS := haps_hs\nendef\nTARGET_DEVICES += nsim_hs\nendif\n\n# Root FS on SD-card\nKERNEL_LOADADDR := 0x90000000\nDEVICE_DTS_LIST:= axs103_idu haps_hs hsdk\nFAT32_BLOCK_SIZE=1024\nFAT32_BLOCKS=$(shell echo $$(($(CONFIG_AXS10X_SD_BOOT_PARTSIZE)*1024*1024/$(FAT32_BLOCK_SIZE))))\n\ndefine Image/Prepare\n\t# Build .dtb for all boards we may run on\n\t$(foreach dts,$(DEVICE_DTS_LIST),\n\t\t$(call Image/BuildDTB,$(DTS_DIR)/$(dts).dts,$(DTS_DIR)/$(dts).dtb)\n\t)\nendef\n\ndefine Image/Build/SDCard\n\trm -f $(KDIR_TMP)/$(IMG_PREFIX)-$(PROFILE)-boot.img\n\tmkfs.fat $(KDIR_TMP)/$(IMG_PREFIX)-$(PROFILE)-boot.img -C $(FAT32_BLOCKS)\n\tmkimage -C none -A arc -T script -d uEnv.txt $(BIN_DIR)/uEnv.scr\n\tmkenvimage -s 0x4000 -o $(BIN_DIR)/uboot.env ./uboot.env.txt\n\tmcopy -i $(KDIR_TMP)/$(IMG_PREFIX)-$(PROFILE)-boot.img $(BIN_DIR)/uEnv.scr ::boot.scr\n\tmcopy -i $(KDIR_TMP)/$(IMG_PREFIX)-$(PROFILE)-boot.img $(DTS_DIR)/*.dtb ::\n\tmcopy -i $(KDIR_TMP)/$(IMG_PREFIX)-$(PROFILE)-boot.img $(BIN_DIR)/$(IMG_PREFIX)-uImage ::uImage\n\tmcopy -i $(KDIR_TMP)/$(IMG_PREFIX)-$(PROFILE)-boot.img $(BIN_DIR)/uboot.env ::uboot.env\n\n\t./gen_axs10x_sdcard_img.sh \\\n\t\t$(BIN_DIR)/$(IMG_PREFIX)-$(PROFILE)-sdcard-vfat-$(1).img \\\n\t\t$(KDIR_TMP)/$(IMG_PREFIX)-$(PROFILE)-boot.img \\\n\t\t$(KDIR)/root.$(1) \\\n\t\t$(CONFIG_AXS10X_SD_BOOT_PARTSIZE) \\\n\t\t$(CONFIG_TARGET_ROOTFS_PARTSIZE)\n\nifneq ($(CONFIG_TARGET_IMAGES_GZIP),)\n\tgzip -f9n $(BIN_DIR)/$(IMG_PREFIX)-$(PROFILE)-sdcard-vfat-$(1).img\nendif\nendef\n\ndefine Image/BuildKernel\n\t# Build unified uImage\n\t$(call Image/BuildKernel/MkuImage, \\\n\t\tnone, $(KERNEL_LOADADDR),$(call kernel_ep,$(KDIR)/vmlinux.elf) , \\\n\t\t$(KDIR)/vmlinux, \\\n\t\t$(BIN_DIR)/$(IMG_PREFIX)-uImage \\\n\t)\nendef\n\ndefine Image/Build\n\t$(call Image/Build/$(1),$(1))\n\t$(call Image/Build/SDCard,$(1))\n\tdd if=$(KDIR)/root.$(1) of=$(BIN_DIR)/$(IMG_PREFIX)-root.$(1) bs=128k conv=sync\n\t$(call Image/Gzip,$(BIN_DIR)/$(IMG_PREFIX)-root.$(1))\nendef\n\n$(eval $(call BuildImage))\n"
  },
  {
    "path": "target/linux/archs38/image/gen_axs10x_sdcard_img.sh",
    "content": "#!/bin/sh\n# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2016 OpenWrt.org\n\nset -x\n[ $# -eq 5 ] || {\n    echo \"SYNTAX: $0 <file> <bootfs image> <rootfs image> <bootfs size> <rootfs size>\"\n    exit 1\n}\n\nOUTPUT=\"$1\"\nBOOTFS=\"$2\"\nROOTFS=\"$3\"\nBOOTFSSIZE=\"$4\"\nROOTFSSIZE=\"$5\"\n\nhead=4\nsect=63\n\nset $(ptgen -o $OUTPUT -h $head -s $sect -l 1024 -t c -p ${BOOTFSSIZE}M -t 83 -p ${ROOTFSSIZE}M)\n\nBOOTOFFSET=\"$(($1 / 512))\"\nBOOTSIZE=\"$(($2 / 512))\"\nROOTFSOFFSET=\"$(($3 / 512))\"\nROOTFSSIZE=\"$(($4 / 512))\"\n\ndd bs=512 if=\"$BOOTFS\" of=\"$OUTPUT\" seek=\"$BOOTOFFSET\" conv=notrunc\ndd bs=512 if=\"$ROOTFS\" of=\"$OUTPUT\" seek=\"$ROOTFSOFFSET\" conv=notrunc\n"
  },
  {
    "path": "target/linux/archs38/image/uEnv.txt",
    "content": "setenv kernel_addr_r 0x82000000\nsetenv fdt_addr_r 0x83000000\nsetenv loadkernel fatload mmc 0 \\${kernel_addr_r} uImage\nsetenv loaddtb fatload mmc 0 \\${fdt_addr_r} \\${dts}\nsetenv bootargs earlycon=uart8250,mmio32,0xe0022000,115200n8 console=ttyS3,115200n8 root=/dev/mmcblk0p2 rootwait print-fatal-signals=1\nsetenv uenvcmd run loadkernel\\; run loaddtb\\; bootm \\${kernel_addr_r} - \\${fdt_addr_r}\nrun uenvcmd\n"
  },
  {
    "path": "target/linux/archs38/image/uboot.env.txt",
    "content": "baudrate=115200\nbootargs=console=ttyS0,115200n8 root=/dev/mmcblk0p2 rootwait\nbootcmd=fatload mmc 0:1 0x82000000 uImage && fatload mmc 0:1 0x81000000 hsdk.dtb && bootm 0x82000000 - 0x81000000\nbootdelay=2\nbootfile=uImage\nloadaddr=0x82000000\nstderr=serial0@f0005000\nstdin=serial0@f0005000\nstdout=serial0@f0005000\ncore_dccm_0=0x10\ncore_dccm_1=0x6\ncore_dccm_2=0x10\ncore_dccm_3=0x6\ncore_iccm_0=0x10\ncore_iccm_1=0x6\ncore_iccm_2=0x10\ncore_iccm_3=0x6\ncore_mask=0xF\ndcache_ena=0x1\nicache_ena=0x1\nnon_volatile_limit=0xE\nhsdk_hs34=setenv core_mask 0x2; setenv icache_ena 0x0; setenv dcache_ena 0x0; setenv core_iccm_1 0x7; setenv core_dccm_1 0x8; setenv non_volatile_limit 0x0;\nhsdk_hs36=setenv core_mask 0x1; setenv icache_ena 0x1; setenv dcache_ena 0x1; setenv core_iccm_0 0x10; setenv core_dccm_0 0x10; setenv non_volatile_limit 0xE;\nhsdk_hs36_ccm=setenv core_mask 0x2; setenv icache_ena 0x1; setenv dcache_ena 0x1; setenv core_iccm_1 0x7; setenv core_dccm_1 0x8; setenv non_volatile_limit 0xE;\nhsdk_hs38=setenv core_mask 0x1; setenv icache_ena 0x1; setenv dcache_ena 0x1; setenv core_iccm_0 0x10; setenv core_dccm_0 0x10; setenv non_volatile_limit 0xE;\nhsdk_hs38_ccm=setenv core_mask 0x2; setenv icache_ena 0x1; setenv dcache_ena 0x1; setenv core_iccm_1 0x7; setenv core_dccm_1 0x8; setenv non_volatile_limit 0xE;\nhsdk_hs38x2=setenv core_mask 0x3; setenv icache_ena 0x1; setenv dcache_ena 0x1; setenv core_iccm_0 0x10; setenv core_dccm_0 0x10; setenv non_volatile_limit 0xE; setenv core_iccm_1 0x6; setenv core_dccm_1 0x6;\nhsdk_hs38x3=setenv core_mask 0x7; setenv icache_ena 0x1; setenv dcache_ena 0x1; setenv core_iccm_0 0x10; setenv core_dccm_0 0x10; setenv non_volatile_limit 0xE; setenv core_iccm_1 0x6; setenv core_dccm_1 0x6; setenv core_iccm_2 0x10; setenv core_dccm_2 0x10;\nhsdk_hs38x4=setenv core_mask 0xF; setenv icache_ena 0x1; setenv dcache_ena 0x1; setenv core_iccm_0 0x10; setenv core_dccm_0 0x10; setenv non_volatile_limit 0xE; setenv core_iccm_1 0x6; setenv core_dccm_1 0x6; setenv core_iccm_2 0x10; setenv core_dccm_2 0x10; setenv core_iccm_3 0x6; setenv core_dccm_3 0x6;\n"
  },
  {
    "path": "target/linux/armvirt/32/config-5.10",
    "content": "CONFIG_ALIGNMENT_TRAP=y\nCONFIG_ARCH_32BIT_OFF_T=y\nCONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y\nCONFIG_ARCH_MULTIPLATFORM=y\nCONFIG_ARCH_MULTI_V6_V7=y\nCONFIG_ARCH_MULTI_V7=y\nCONFIG_ARCH_NR_GPIO=0\nCONFIG_ARCH_OPTIONAL_KERNEL_RWX=y\nCONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y\nCONFIG_ARCH_VIRT=y\nCONFIG_ARM=y\nCONFIG_ARM_CPU_SUSPEND=y\nCONFIG_ARM_HAS_SG_CHAIN=y\nCONFIG_ARM_HEAVY_MB=y\nCONFIG_ARM_L1_CACHE_SHIFT=6\nCONFIG_ARM_L1_CACHE_SHIFT_6=y\nCONFIG_ARM_LPAE=y\nCONFIG_ARM_PATCH_IDIV=y\nCONFIG_ARM_PATCH_PHYS_VIRT=y\nCONFIG_ARM_PSCI=y\nCONFIG_ARM_THUMB=y\nCONFIG_ARM_UNWIND=y\nCONFIG_ARM_VIRT_EXT=y\nCONFIG_AUTO_ZRELADDR=y\nCONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y\nCONFIG_CACHE_L2X0=y\nCONFIG_COMPAT_32BIT_TIME=y\nCONFIG_CPU_32v6K=y\nCONFIG_CPU_32v7=y\nCONFIG_CPU_ABRT_EV7=y\nCONFIG_CPU_CACHE_V7=y\nCONFIG_CPU_CACHE_VIPT=y\nCONFIG_CPU_COPY_V6=y\nCONFIG_CPU_CP15=y\nCONFIG_CPU_CP15_MMU=y\nCONFIG_CPU_HAS_ASID=y\nCONFIG_CPU_PABRT_V7=y\nCONFIG_CPU_SPECTRE=y\nCONFIG_CPU_THUMB_CAPABLE=y\nCONFIG_CPU_TLB_V7=y\nCONFIG_CPU_V7=y\nCONFIG_DEBUG_LL_INCLUDE=\"mach/debug-macro.S\"\nCONFIG_DMA_OPS=y\nCONFIG_EDAC_ATOMIC_SCRUB=y\nCONFIG_GENERIC_VDSO_32=y\nCONFIG_HARDEN_BRANCH_PREDICTOR=y\nCONFIG_HAVE_SMP=y\nCONFIG_HZ_FIXED=0\nCONFIG_HZ_PERIODIC=y\nCONFIG_MIGHT_HAVE_CACHE_L2X0=y\nCONFIG_MODULES_USE_ELF_REL=y\nCONFIG_NEON=y\nCONFIG_NR_CPUS=4\nCONFIG_OLD_SIGACTION=y\nCONFIG_OLD_SIGSUSPEND3=y\nCONFIG_OUTER_CACHE=y\nCONFIG_OUTER_CACHE_SYNC=y\nCONFIG_PAGE_OFFSET=0xC0000000\nCONFIG_PERF_USE_VMALLOC=y\nCONFIG_RTC_MC146818_LIB=y\nCONFIG_SERIAL_OF_PLATFORM=y\nCONFIG_SMP_ON_UP=y\nCONFIG_SWP_EMULATE=y\nCONFIG_SYS_SUPPORTS_APM_EMULATION=y\nCONFIG_UNCOMPRESS_INCLUDE=\"debug/uncompress.h\"\nCONFIG_UNWINDER_ARM=y\nCONFIG_USE_OF=y\nCONFIG_VFP=y\nCONFIG_VFPv3=y\nCONFIG_XZ_DEC_ARM=y\nCONFIG_XZ_DEC_BCJ=y\nCONFIG_ZBOOT_ROM_BSS=0\nCONFIG_ZBOOT_ROM_TEXT=0\n"
  },
  {
    "path": "target/linux/armvirt/32/config-5.15",
    "content": "CONFIG_ALIGNMENT_TRAP=y\nCONFIG_ARCH_32BIT_OFF_T=y\nCONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y\nCONFIG_ARCH_MULTIPLATFORM=y\nCONFIG_ARCH_MULTI_V6_V7=y\nCONFIG_ARCH_MULTI_V7=y\nCONFIG_ARCH_NR_GPIO=0\nCONFIG_ARCH_OPTIONAL_KERNEL_RWX=y\nCONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y\nCONFIG_ARCH_SELECT_MEMORY_MODEL=y\nCONFIG_ARCH_VIRT=y\nCONFIG_ARM=y\nCONFIG_ARM_CPU_SUSPEND=y\nCONFIG_ARM_HAS_SG_CHAIN=y\nCONFIG_ARM_HEAVY_MB=y\nCONFIG_ARM_L1_CACHE_SHIFT=6\nCONFIG_ARM_L1_CACHE_SHIFT_6=y\nCONFIG_ARM_LPAE=y\nCONFIG_ARM_PATCH_IDIV=y\nCONFIG_ARM_PATCH_PHYS_VIRT=y\nCONFIG_ARM_PSCI=y\nCONFIG_ARM_THUMB=y\nCONFIG_ARM_UNWIND=y\nCONFIG_ARM_VIRT_EXT=y\nCONFIG_AUTO_ZRELADDR=y\nCONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y\nCONFIG_CACHE_L2X0=y\nCONFIG_COMPAT_32BIT_TIME=y\nCONFIG_CPU_32v6K=y\nCONFIG_CPU_32v7=y\nCONFIG_CPU_ABRT_EV7=y\nCONFIG_CPU_CACHE_V7=y\nCONFIG_CPU_CACHE_VIPT=y\nCONFIG_CPU_COPY_V6=y\nCONFIG_CPU_CP15=y\nCONFIG_CPU_CP15_MMU=y\nCONFIG_CPU_HAS_ASID=y\nCONFIG_CPU_PABRT_V7=y\nCONFIG_CPU_SPECTRE=y\nCONFIG_CPU_THUMB_CAPABLE=y\nCONFIG_CPU_TLB_V7=y\nCONFIG_CPU_V7=y\nCONFIG_DEBUG_LL_INCLUDE=\"mach/debug-macro.S\"\nCONFIG_DMA_OPS=y\nCONFIG_EDAC_ATOMIC_SCRUB=y\nCONFIG_GENERIC_IRQ_MULTI_HANDLER=y\nCONFIG_GENERIC_VDSO_32=y\nCONFIG_HARDEN_BRANCH_PREDICTOR=y\nCONFIG_HAVE_SMP=y\nCONFIG_HZ_FIXED=0\nCONFIG_HZ_PERIODIC=y\nCONFIG_MIGHT_HAVE_CACHE_L2X0=y\nCONFIG_MODULES_USE_ELF_REL=y\nCONFIG_NEON=y\nCONFIG_NR_CPUS=4\nCONFIG_OLD_SIGACTION=y\nCONFIG_OLD_SIGSUSPEND3=y\nCONFIG_OUTER_CACHE=y\nCONFIG_OUTER_CACHE_SYNC=y\nCONFIG_PAGE_OFFSET=0xC0000000\nCONFIG_PERF_USE_VMALLOC=y\nCONFIG_RTC_MC146818_LIB=y\nCONFIG_SERIAL_OF_PLATFORM=y\nCONFIG_SMP_ON_UP=y\nCONFIG_SWP_EMULATE=y\nCONFIG_SYS_SUPPORTS_APM_EMULATION=y\nCONFIG_UNCOMPRESS_INCLUDE=\"debug/uncompress.h\"\nCONFIG_UNWINDER_ARM=y\nCONFIG_USE_OF=y\nCONFIG_VFP=y\nCONFIG_VFPv3=y\nCONFIG_XZ_DEC_ARM=y\nCONFIG_XZ_DEC_BCJ=y\nCONFIG_ZBOOT_ROM_BSS=0\nCONFIG_ZBOOT_ROM_TEXT=0\n"
  },
  {
    "path": "target/linux/armvirt/32/target.mk",
    "content": "ARCH:=arm\nSUBTARGET:=32\nBOARDNAME:=QEMU ARM Virtual Machine (cortex-a15)\nCPU_TYPE:=cortex-a15\nCPU_SUBTYPE:=neon-vfpv4\nKERNELNAME:=zImage\n\ndefine Target/Description\n  Build images for $(BOARDNAME)\nendef\n"
  },
  {
    "path": "target/linux/armvirt/64/config-5.10",
    "content": "CONFIG_64BIT=y\nCONFIG_ARCH_MMAP_RND_BITS=18\nCONFIG_ARCH_MMAP_RND_BITS_MAX=24\nCONFIG_ARCH_MMAP_RND_BITS_MIN=18\nCONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11\nCONFIG_ARCH_PROC_KCORE_TEXT=y\nCONFIG_ARCH_SPARSEMEM_DEFAULT=y\nCONFIG_ARCH_STACKWALK=y\nCONFIG_ARCH_VEXPRESS=y\nCONFIG_ARM64=y\nCONFIG_ARM64_4K_PAGES=y\nCONFIG_ARM64_CNP=y\nCONFIG_ARM64_CRYPTO=y\nCONFIG_ARM64_ERRATUM_1165522=y\nCONFIG_ARM64_ERRATUM_1286807=y\nCONFIG_ARM64_ERRATUM_819472=y\nCONFIG_ARM64_ERRATUM_824069=y\nCONFIG_ARM64_ERRATUM_826319=y\nCONFIG_ARM64_ERRATUM_827319=y\nCONFIG_ARM64_ERRATUM_832075=y\nCONFIG_ARM64_ERRATUM_843419=y\nCONFIG_ARM64_HW_AFDBM=y\nCONFIG_ARM64_MODULE_PLTS=y\nCONFIG_ARM64_PAGE_SHIFT=12\nCONFIG_ARM64_PAN=y\nCONFIG_ARM64_PA_BITS=48\nCONFIG_ARM64_PA_BITS_48=y\nCONFIG_ARM64_PTR_AUTH=y\nCONFIG_ARM64_SVE=y\nCONFIG_ARM64_TAGGED_ADDR_ABI=y\nCONFIG_ARM64_UAO=y\nCONFIG_ARM64_VA_BITS=39\nCONFIG_ARM64_VA_BITS_39=y\nCONFIG_ARM64_VHE=y\nCONFIG_ARM64_WORKAROUND_CLEAN_CACHE=y\nCONFIG_ARM64_WORKAROUND_REPEAT_TLBI=y\nCONFIG_ARM64_WORKAROUND_SPECULATIVE_AT=y\nCONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y\nCONFIG_ARM_SBSA_WATCHDOG=y\nCONFIG_ATOMIC64_SELFTEST=y\nCONFIG_AUDIT_ARCH_COMPAT_GENERIC=y\nCONFIG_BACKLIGHT_CLASS_DEVICE=y\nCONFIG_BLK_PM=y\nCONFIG_CAVIUM_TX2_ERRATUM_219=y\nCONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y\nCONFIG_CLK_SP810=y\nCONFIG_CLK_VEXPRESS_OSC=y\n# CONFIG_COMPAT_32BIT_TIME is not set\nCONFIG_CPU_IDLE=y\nCONFIG_CPU_IDLE_GOV_MENU=y\nCONFIG_CPU_PM=y\nCONFIG_CRYPTO_AES_ARM64=y\nCONFIG_CRYPTO_AES_ARM64_BS=y\nCONFIG_CRYPTO_AES_ARM64_CE=y\nCONFIG_CRYPTO_AES_ARM64_CE_BLK=y\nCONFIG_CRYPTO_AES_ARM64_CE_CCM=y\nCONFIG_CRYPTO_AES_ARM64_NEON_BLK=y\nCONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=y\nCONFIG_CRYPTO_CHACHA20=y\nCONFIG_CRYPTO_CHACHA20_NEON=y\nCONFIG_CRYPTO_CRYPTD=y\nCONFIG_CRYPTO_GHASH_ARM64_CE=y\nCONFIG_CRYPTO_LIB_CHACHA_GENERIC=y\nCONFIG_CRYPTO_SHA1=y\nCONFIG_CRYPTO_SHA1_ARM64_CE=y\nCONFIG_CRYPTO_SHA256_ARM64=y\nCONFIG_CRYPTO_SHA2_ARM64_CE=y\nCONFIG_CRYPTO_SHA512_ARM64=y\nCONFIG_CRYPTO_SIMD=y\nCONFIG_DMA_DIRECT_REMAP=y\nCONFIG_DMA_SHARED_BUFFER=y\nCONFIG_DRM=y\nCONFIG_DRM_BOCHS=y\nCONFIG_DRM_BRIDGE=y\nCONFIG_DRM_GEM_SHMEM_HELPER=y\nCONFIG_DRM_KMS_HELPER=y\nCONFIG_DRM_PANEL=y\nCONFIG_DRM_PANEL_BRIDGE=y\nCONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y\nCONFIG_DRM_QXL=y\nCONFIG_DRM_TTM=y\nCONFIG_DRM_TTM_DMA_PAGE_POOL=y\nCONFIG_DRM_TTM_HELPER=y\nCONFIG_DRM_VIRTIO_GPU=y\nCONFIG_DRM_VRAM_HELPER=y\nCONFIG_FB=y\nCONFIG_FB_ARMCLCD=y\nCONFIG_FB_CFB_COPYAREA=y\nCONFIG_FB_CFB_FILLRECT=y\nCONFIG_FB_CFB_IMAGEBLIT=y\nCONFIG_FB_CMDLINE=y\nCONFIG_FB_MODE_HELPERS=y\n# CONFIG_FLATMEM_MANUAL is not set\nCONFIG_FRAME_POINTER=y\nCONFIG_FSL_ERRATUM_A008585=y\nCONFIG_FUJITSU_ERRATUM_010001=y\nCONFIG_GENERIC_BUG_RELATIVE_POINTERS=y\nCONFIG_GENERIC_CSUM=y\nCONFIG_GPIO_GENERIC=y\nCONFIG_GPIO_GENERIC_PLATFORM=y\nCONFIG_HDMI=y\nCONFIG_HOLES_IN_ZONE=y\nCONFIG_HW_RANDOM=y\nCONFIG_HW_RANDOM_VIRTIO=y\nCONFIG_I2C=y\nCONFIG_I2C_ALGOBIT=y\nCONFIG_I2C_BOARDINFO=y\n# CONFIG_ICST is not set\nCONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000\nCONFIG_KCMP=y\nCONFIG_LCD_CLASS_DEVICE=m\n# CONFIG_LCD_PLATFORM is not set\nCONFIG_MFD_CORE=y\nCONFIG_MFD_SYSCON=y\nCONFIG_MFD_VEXPRESS_SYSREG=y\nCONFIG_MMC=y\nCONFIG_MMC_ARMMMCI=y\nCONFIG_MODULES_USE_ELF_RELA=y\nCONFIG_NEED_SG_DMA_LENGTH=y\nCONFIG_NO_HZ=y\nCONFIG_NO_HZ_COMMON=y\nCONFIG_NO_HZ_IDLE=y\nCONFIG_NR_CPUS=64\nCONFIG_PM=y\nCONFIG_PM_CLK=y\nCONFIG_PM_GENERIC_DOMAINS=y\nCONFIG_PM_GENERIC_DOMAINS_OF=y\nCONFIG_POWER_RESET=y\nCONFIG_POWER_RESET_VEXPRESS=y\nCONFIG_POWER_SUPPLY=y\nCONFIG_QUEUED_RWLOCKS=y\nCONFIG_QUEUED_SPINLOCKS=y\nCONFIG_REGMAP=y\nCONFIG_REGMAP_MMIO=y\nCONFIG_RODATA_FULL_DEFAULT_ENABLED=y\nCONFIG_RTC_I2C_AND_SPI=y\nCONFIG_SMC91X=y\nCONFIG_SPARSEMEM=y\nCONFIG_SPARSEMEM_EXTREME=y\nCONFIG_SPARSEMEM_MANUAL=y\nCONFIG_SPARSEMEM_VMEMMAP=y\nCONFIG_SPARSEMEM_VMEMMAP_ENABLE=y\nCONFIG_SYNC_FILE=y\nCONFIG_SYSCTL_EXCEPTION_TRACE=y\nCONFIG_THREAD_INFO_IN_TASK=y\nCONFIG_UNMAP_KERNEL_AT_EL0=y\nCONFIG_VEXPRESS_CONFIG=y\nCONFIG_VIDEOMODE_HELPERS=y\nCONFIG_VIRTIO_DMA_SHARED_BUFFER=y\nCONFIG_VMAP_STACK=y\nCONFIG_WATCHDOG_CORE=y\nCONFIG_ZONE_DMA32=y\n"
  },
  {
    "path": "target/linux/armvirt/64/config-5.15",
    "content": "CONFIG_64BIT=y\nCONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y\nCONFIG_ARCH_MMAP_RND_BITS=18\nCONFIG_ARCH_MMAP_RND_BITS_MAX=24\nCONFIG_ARCH_MMAP_RND_BITS_MIN=18\nCONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11\nCONFIG_ARCH_PROC_KCORE_TEXT=y\nCONFIG_ARCH_STACKWALK=y\nCONFIG_ARCH_VEXPRESS=y\nCONFIG_ARCH_WANTS_NO_INSTR=y\nCONFIG_ARM64=y\nCONFIG_ARM64_4K_PAGES=y\nCONFIG_ARM64_CNP=y\nCONFIG_ARM64_CRYPTO=y\nCONFIG_ARM64_EPAN=y\nCONFIG_ARM64_ERRATUM_1165522=y\nCONFIG_ARM64_ERRATUM_1286807=y\nCONFIG_ARM64_ERRATUM_819472=y\nCONFIG_ARM64_ERRATUM_824069=y\nCONFIG_ARM64_ERRATUM_826319=y\nCONFIG_ARM64_ERRATUM_827319=y\nCONFIG_ARM64_ERRATUM_832075=y\nCONFIG_ARM64_ERRATUM_843419=y\nCONFIG_ARM64_HW_AFDBM=y\nCONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y\nCONFIG_ARM64_MODULE_PLTS=y\nCONFIG_ARM64_PAGE_SHIFT=12\nCONFIG_ARM64_PAN=y\nCONFIG_ARM64_PA_BITS=48\nCONFIG_ARM64_PA_BITS_48=y\nCONFIG_ARM64_PTR_AUTH=y\nCONFIG_ARM64_PTR_AUTH_KERNEL=y\nCONFIG_ARM64_SVE=y\nCONFIG_ARM64_TAGGED_ADDR_ABI=y\nCONFIG_ARM64_VA_BITS=39\nCONFIG_ARM64_VA_BITS_39=y\nCONFIG_ARM64_WORKAROUND_CLEAN_CACHE=y\nCONFIG_ARM64_WORKAROUND_REPEAT_TLBI=y\nCONFIG_ARM64_WORKAROUND_SPECULATIVE_AT=y\nCONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y\nCONFIG_ARM_SBSA_WATCHDOG=y\nCONFIG_ATOMIC64_SELFTEST=y\nCONFIG_AUDIT_ARCH_COMPAT_GENERIC=y\nCONFIG_BACKLIGHT_CLASS_DEVICE=y\nCONFIG_BLK_PM=y\nCONFIG_CAVIUM_TX2_ERRATUM_219=y\nCONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y\nCONFIG_CLK_SP810=y\nCONFIG_CLK_VEXPRESS_OSC=y\n# CONFIG_COMPAT_32BIT_TIME is not set\nCONFIG_CPU_IDLE=y\nCONFIG_CPU_IDLE_GOV_MENU=y\nCONFIG_CPU_PM=y\nCONFIG_CRYPTO_AES_ARM64=y\nCONFIG_CRYPTO_AES_ARM64_BS=y\nCONFIG_CRYPTO_AES_ARM64_CE=y\nCONFIG_CRYPTO_AES_ARM64_CE_BLK=y\nCONFIG_CRYPTO_AES_ARM64_CE_CCM=y\nCONFIG_CRYPTO_AES_ARM64_NEON_BLK=y\nCONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=y\nCONFIG_CRYPTO_CHACHA20=y\nCONFIG_CRYPTO_CHACHA20_NEON=y\nCONFIG_CRYPTO_CRYPTD=y\nCONFIG_CRYPTO_GHASH_ARM64_CE=y\nCONFIG_CRYPTO_LIB_CHACHA_GENERIC=y\nCONFIG_CRYPTO_SHA1=y\nCONFIG_CRYPTO_SHA1_ARM64_CE=y\nCONFIG_CRYPTO_SHA256_ARM64=y\nCONFIG_CRYPTO_SHA2_ARM64_CE=y\nCONFIG_CRYPTO_SHA512_ARM64=y\nCONFIG_CRYPTO_SIMD=y\nCONFIG_DMA_DIRECT_REMAP=y\nCONFIG_DMA_SHARED_BUFFER=y\nCONFIG_DRM=y\nCONFIG_DRM_BOCHS=y\nCONFIG_DRM_BRIDGE=y\nCONFIG_DRM_GEM_SHMEM_HELPER=y\nCONFIG_DRM_KMS_HELPER=y\nCONFIG_DRM_PANEL=y\nCONFIG_DRM_PANEL_BRIDGE=y\nCONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y\nCONFIG_DRM_QXL=y\nCONFIG_DRM_TTM=y\nCONFIG_DRM_TTM_HELPER=y\nCONFIG_DRM_VIRTIO_GPU=y\nCONFIG_DRM_VRAM_HELPER=y\nCONFIG_FB=y\nCONFIG_FB_ARMCLCD=y\nCONFIG_FB_CFB_COPYAREA=y\nCONFIG_FB_CFB_FILLRECT=y\nCONFIG_FB_CFB_IMAGEBLIT=y\nCONFIG_FB_CMDLINE=y\nCONFIG_FB_MODE_HELPERS=y\nCONFIG_FRAME_POINTER=y\nCONFIG_FSL_ERRATUM_A008585=y\nCONFIG_FUJITSU_ERRATUM_010001=y\nCONFIG_GENERIC_BUG_RELATIVE_POINTERS=y\nCONFIG_GENERIC_CSUM=y\nCONFIG_GENERIC_FIND_FIRST_BIT=y\nCONFIG_GPIO_GENERIC=y\nCONFIG_GPIO_GENERIC_PLATFORM=y\nCONFIG_HDMI=y\nCONFIG_HW_RANDOM=y\nCONFIG_HW_RANDOM_ARM_SMCCC_TRNG=y\nCONFIG_HW_RANDOM_VIRTIO=y\nCONFIG_I2C=y\nCONFIG_I2C_ALGOBIT=y\nCONFIG_I2C_BOARDINFO=y\nCONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000\nCONFIG_KCMP=y\nCONFIG_LCD_CLASS_DEVICE=m\n# CONFIG_LCD_PLATFORM is not set\nCONFIG_MFD_CORE=y\nCONFIG_MFD_SYSCON=y\nCONFIG_MFD_VEXPRESS_SYSREG=y\nCONFIG_MMC=y\nCONFIG_MMC_ARMMMCI=y\nCONFIG_MODULES_USE_ELF_RELA=y\nCONFIG_NEED_SG_DMA_LENGTH=y\nCONFIG_NO_HZ=y\nCONFIG_NO_HZ_COMMON=y\nCONFIG_NO_HZ_IDLE=y\nCONFIG_NR_CPUS=64\nCONFIG_NVIDIA_CARMEL_CNP_ERRATUM=y\nCONFIG_PM=y\nCONFIG_PM_CLK=y\nCONFIG_PM_GENERIC_DOMAINS=y\nCONFIG_PM_GENERIC_DOMAINS_OF=y\nCONFIG_POWER_RESET=y\nCONFIG_POWER_RESET_VEXPRESS=y\nCONFIG_POWER_SUPPLY=y\nCONFIG_QUEUED_RWLOCKS=y\nCONFIG_QUEUED_SPINLOCKS=y\nCONFIG_REGMAP=y\nCONFIG_REGMAP_MMIO=y\nCONFIG_RODATA_FULL_DEFAULT_ENABLED=y\nCONFIG_RTC_I2C_AND_SPI=y\nCONFIG_SMC91X=y\nCONFIG_SPARSEMEM=y\nCONFIG_SPARSEMEM_EXTREME=y\nCONFIG_SPARSEMEM_VMEMMAP=y\nCONFIG_SPARSEMEM_VMEMMAP_ENABLE=y\nCONFIG_SYNC_FILE=y\nCONFIG_SYSCTL_EXCEPTION_TRACE=y\nCONFIG_THREAD_INFO_IN_TASK=y\nCONFIG_UNMAP_KERNEL_AT_EL0=y\nCONFIG_VEXPRESS_CONFIG=y\nCONFIG_VIDEOMODE_HELPERS=y\nCONFIG_VIRTIO_DMA_SHARED_BUFFER=y\nCONFIG_VMAP_STACK=y\nCONFIG_WATCHDOG_CORE=y\nCONFIG_ZONE_DMA32=y\n"
  },
  {
    "path": "target/linux/armvirt/64/target.mk",
    "content": "ARCH:=aarch64\nSUBTARGET:=64\nBOARDNAME:=QEMU ARMv8 Virtual Machine (cortex-a53)\nCPU_TYPE:=cortex-a53\nKERNELNAME:=Image\n\ndefine Target/Description\n  Build multi-platform images for the ARMv8 instruction set architecture\nendef\n"
  },
  {
    "path": "target/linux/armvirt/Makefile",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2017 Yousong Zhou <yszhou4tech@gmail.com>\n\ninclude $(TOPDIR)/rules.mk\n\nBOARD:=armvirt\nBOARDNAME:=QEMU ARM Virtual Machine\nFEATURES:=fpu pci rtc usb\nFEATURES+=cpiogz ext4 ramdisk squashfs targz\n\nKERNEL_PATCHVER:=5.10\nKERNEL_TESTING_PATCHVER:=5.15\n\ninclude $(INCLUDE_DIR)/target.mk\n\nDEFAULT_PACKAGES += mkf2fs e2fsprogs\n\n$(eval $(call BuildTarget))\n"
  },
  {
    "path": "target/linux/armvirt/README",
    "content": "This is intended to be used with OpenWrt project to provide image for use with\nQEMU ARM virt machine.\n\nRun with qemu-system-arm\n\n\t# boot with initramfs embedded in\n\tqemu-system-arm -nographic -M virt -m 64 -kernel openwrt-armvirt-32-zImage-initramfs\n\n\t# boot with accel=kvm\n\tqemu-system-arm -nographic -M virt,accel=kvm -cpu host -m 64 -kernel\n\topenwrt-armvirt-32-zImage-initramfs\n\n\t# boot with a separate rootfs\n\tqemu-system-arm -nographic -M virt -m 64 -kernel openwrt-armvirt-32-zImage \\\n\t  -drive file=openwrt-armvirt-32-root.ext4,format=raw,if=virtio -append 'root=/dev/vda rootwait'\n\n\t# boot with local dir as rootfs\n\tqemu-system-arm -nographic -M virt -m 64 -kernel openwrt-armvirt-32-zImage \\\n\t  -fsdev local,id=rootdev,path=root-armvirt/,security_model=none \\\n\t  -device virtio-9p-pci,fsdev=rootdev,mount_tag=/dev/root \\\n\t  -append 'rootflags=trans=virtio,version=9p2000.L,cache=loose rootfstype=9p'\n\nRun with kvmtool\n\n\t# start a named machine\n\tlkvm run -k openwrt-armvirt-32-zImage -i openwrt-armvirt-32-rootfs.cpio --name armvirt0\n\n\t# start with virtio-9p rootfs\n\tlkvm run -k openwrt-armvirt-32-zImage -d root-armvirt/\n\n\t# stop \"armvirt0\"\n\tlkvm stop --name armvirt0\n\n\t# stop all\n\tlkvm stop --all\n\nThe multi-platform ARMv8 target can be used with QEMU:\n\n\tqemu-system-aarch64 -machine virt -cpu cortex-a57 -nographic \\\n\t\t-kernel openwrt-armvirt-64-Image-initramfs \\\n"
  },
  {
    "path": "target/linux/armvirt/base-files/etc/board.d/00_model",
    "content": "# Copyright (C) 2015 OpenWrt.org\n# Copyright (C) 2016 Yousong Zhou <yszhou4tech@gmail.com>\n\n. /lib/functions/uci-defaults.sh\n\nboard_config_update\n\nucidef_set_board_id \"armvirt\"\nucidef_set_model_name \"QEMU ARM Virtual Machine\"\n\nboard_config_flush\n\nexit 0\n"
  },
  {
    "path": "target/linux/armvirt/base-files/etc/inittab",
    "content": "::sysinit:/etc/init.d/rcS S boot\n::shutdown:/etc/init.d/rcS K shutdown\nttyAMA0::askfirst:/usr/libexec/login.sh\nttyS0::askfirst:/usr/libexec/login.sh\nhvc0::askfirst:/usr/libexec/login.sh\n"
  },
  {
    "path": "target/linux/armvirt/config-5.10",
    "content": "CONFIG_9P_FS=y\n# CONFIG_9P_FS_POSIX_ACL is not set\n# CONFIG_9P_FS_SECURITY is not set\nCONFIG_ARCH_DMA_ADDR_T_64BIT=y\nCONFIG_ARCH_HIBERNATION_POSSIBLE=y\nCONFIG_ARCH_KEEP_MEMBLOCK=y\nCONFIG_ARCH_SELECT_MEMORY_MODEL=y\nCONFIG_ARCH_SPARSEMEM_ENABLE=y\nCONFIG_ARCH_SUSPEND_POSSIBLE=y\nCONFIG_ARM_AMBA=y\nCONFIG_ARM_ARCH_TIMER=y\nCONFIG_ARM_ARCH_TIMER_EVTSTREAM=y\nCONFIG_ARM_GIC=y\nCONFIG_ARM_GIC_V2M=y\nCONFIG_ARM_GIC_V3=y\nCONFIG_ARM_GIC_V3_ITS=y\nCONFIG_ARM_GIC_V3_ITS_PCI=y\nCONFIG_ARM_PSCI_FW=y\nCONFIG_BALLOON_COMPACTION=y\nCONFIG_BLK_DEV_LOOP=y\nCONFIG_BLK_MQ_PCI=y\nCONFIG_BLK_MQ_VIRTIO=y\nCONFIG_BLK_SCSI_REQUEST=y\nCONFIG_CLKDEV_LOOKUP=y\nCONFIG_CLONE_BACKWARDS=y\nCONFIG_COMMON_CLK=y\nCONFIG_CPU_RMAP=y\nCONFIG_CRC16=y\nCONFIG_CRYPTO_CRC32=y\nCONFIG_CRYPTO_CRC32C=y\nCONFIG_CRYPTO_RNG2=y\nCONFIG_DCACHE_WORD_ACCESS=y\nCONFIG_DEBUG_BUGVERBOSE=y\nCONFIG_DMADEVICES=y\nCONFIG_DMA_ENGINE=y\nCONFIG_DMA_OF=y\nCONFIG_DMA_REMAP=y\nCONFIG_DTC=y\nCONFIG_EDAC_SUPPORT=y\nCONFIG_EXT4_FS=y\nCONFIG_F2FS_FS=y\nCONFIG_FAILOVER=y\nCONFIG_FIX_EARLYCON_MEM=y\nCONFIG_FS_IOMAP=y\nCONFIG_FS_MBCACHE=y\nCONFIG_FW_LOADER_PAGED_BUF=y\nCONFIG_GENERIC_ALLOCATOR=y\nCONFIG_GENERIC_ARCH_TOPOLOGY=y\nCONFIG_GENERIC_BUG=y\nCONFIG_GENERIC_CLOCKEVENTS=y\nCONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y\nCONFIG_GENERIC_CPU_AUTOPROBE=y\nCONFIG_GENERIC_CPU_VULNERABILITIES=y\nCONFIG_GENERIC_EARLY_IOREMAP=y\nCONFIG_GENERIC_GETTIMEOFDAY=y\nCONFIG_GENERIC_IDLE_POLL_SETUP=y\nCONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y\nCONFIG_GENERIC_IRQ_MIGRATION=y\nCONFIG_GENERIC_IRQ_MULTI_HANDLER=y\nCONFIG_GENERIC_IRQ_SHOW=y\nCONFIG_GENERIC_IRQ_SHOW_LEVEL=y\nCONFIG_GENERIC_MSI_IRQ=y\nCONFIG_GENERIC_MSI_IRQ_DOMAIN=y\nCONFIG_GENERIC_PCI_IOMAP=y\nCONFIG_GENERIC_SCHED_CLOCK=y\nCONFIG_GENERIC_SMP_IDLE_THREAD=y\nCONFIG_GENERIC_STRNCPY_FROM_USER=y\nCONFIG_GENERIC_STRNLEN_USER=y\nCONFIG_GENERIC_TIME_VSYSCALL=y\nCONFIG_GPIOLIB=y\nCONFIG_GPIOLIB_IRQCHIP=y\nCONFIG_GPIO_PL061=y\nCONFIG_HANDLE_DOMAIN_IRQ=y\nCONFIG_HARDIRQS_SW_RESEND=y\nCONFIG_HAS_DMA=y\nCONFIG_HAS_IOMEM=y\nCONFIG_HAS_IOPORT_MAP=y\nCONFIG_HOTPLUG_CPU=y\nCONFIG_HVC_DRIVER=y\nCONFIG_INITRAMFS_SOURCE=\"\"\nCONFIG_IRQCHIP=y\nCONFIG_IRQ_DOMAIN=y\nCONFIG_IRQ_DOMAIN_HIERARCHY=y\nCONFIG_IRQ_FORCED_THREADING=y\nCONFIG_IRQ_WORK=y\nCONFIG_JBD2=y\nCONFIG_LIBFDT=y\nCONFIG_LOCK_DEBUGGING_SUPPORT=y\nCONFIG_LOCK_SPIN_ON_OWNER=y\nCONFIG_MEMFD_CREATE=y\nCONFIG_MEMORY_BALLOON=y\nCONFIG_MIGRATION=y\nCONFIG_MUTEX_SPIN_ON_OWNER=y\nCONFIG_NEED_DMA_MAP_STATE=y\nCONFIG_NET_9P=y\n# CONFIG_NET_9P_DEBUG is not set\nCONFIG_NET_9P_VIRTIO=y\nCONFIG_NET_FAILOVER=y\nCONFIG_NET_FLOW_LIMIT=y\nCONFIG_NLS=y\nCONFIG_NVMEM=y\nCONFIG_OF=y\nCONFIG_OF_ADDRESS=y\nCONFIG_OF_EARLY_FLATTREE=y\nCONFIG_OF_FLATTREE=y\nCONFIG_OF_GPIO=y\nCONFIG_OF_IRQ=y\nCONFIG_OF_KOBJ=y\nCONFIG_OF_NET=y\nCONFIG_PADATA=y\nCONFIG_PAGE_REPORTING=y\nCONFIG_PARTITION_PERCPU=y\nCONFIG_PCI=y\nCONFIG_PCI_DOMAINS=y\nCONFIG_PCI_DOMAINS_GENERIC=y\nCONFIG_PCI_ECAM=y\nCONFIG_PCI_HOST_COMMON=y\nCONFIG_PCI_HOST_GENERIC=y\nCONFIG_PCI_MSI=y\nCONFIG_PCI_MSI_IRQ_DOMAIN=y\nCONFIG_PGTABLE_LEVELS=3\nCONFIG_PHYS_ADDR_T_64BIT=y\nCONFIG_RATIONAL=y\nCONFIG_RFS_ACCEL=y\nCONFIG_RPS=y\nCONFIG_RTC_CLASS=y\nCONFIG_RTC_DRV_PL031=y\nCONFIG_RWSEM_SPIN_ON_OWNER=y\nCONFIG_SCSI=y\nCONFIG_SCSI_VIRTIO=y\nCONFIG_SERIAL_8250_FSL=y\nCONFIG_SERIAL_AMBA_PL011=y\nCONFIG_SERIAL_AMBA_PL011_CONSOLE=y\nCONFIG_SERIAL_MCTRL_GPIO=y\nCONFIG_SG_POOL=y\nCONFIG_SMP=y\nCONFIG_SPARSE_IRQ=y\nCONFIG_SRCU=y\nCONFIG_SWIOTLB=y\nCONFIG_SYS_SUPPORTS_HUGETLBFS=y\nCONFIG_TICK_CPU_ACCOUNTING=y\nCONFIG_TIMER_OF=y\nCONFIG_TIMER_PROBE=y\nCONFIG_TREE_RCU=y\nCONFIG_TREE_SRCU=y\nCONFIG_USB_SUPPORT=y\nCONFIG_VIRTIO=y\nCONFIG_VIRTIO_BALLOON=y\nCONFIG_VIRTIO_BLK=y\nCONFIG_VIRTIO_CONSOLE=y\nCONFIG_VIRTIO_MMIO=y\nCONFIG_VIRTIO_MMIO_CMDLINE_DEVICES=y\nCONFIG_VIRTIO_NET=y\nCONFIG_VIRTIO_PCI=y\nCONFIG_VIRTIO_PCI_LEGACY=y\nCONFIG_XPS=y\n"
  },
  {
    "path": "target/linux/armvirt/config-5.15",
    "content": "CONFIG_9P_FS=y\n# CONFIG_9P_FS_POSIX_ACL is not set\n# CONFIG_9P_FS_SECURITY is not set\nCONFIG_ARCH_DMA_ADDR_T_64BIT=y\nCONFIG_ARCH_HIBERNATION_POSSIBLE=y\nCONFIG_ARCH_KEEP_MEMBLOCK=y\nCONFIG_ARCH_SPARSEMEM_ENABLE=y\nCONFIG_ARCH_SUSPEND_POSSIBLE=y\nCONFIG_ARM_AMBA=y\nCONFIG_ARM_ARCH_TIMER=y\nCONFIG_ARM_ARCH_TIMER_EVTSTREAM=y\nCONFIG_ARM_GIC=y\nCONFIG_ARM_GIC_V2M=y\nCONFIG_ARM_GIC_V3=y\nCONFIG_ARM_GIC_V3_ITS=y\nCONFIG_ARM_GIC_V3_ITS_PCI=y\nCONFIG_ARM_PSCI_FW=y\nCONFIG_BALLOON_COMPACTION=y\nCONFIG_BLK_DEV_LOOP=y\nCONFIG_BLK_MQ_PCI=y\nCONFIG_BLK_MQ_VIRTIO=y\nCONFIG_CLONE_BACKWARDS=y\nCONFIG_COMMON_CLK=y\nCONFIG_CPU_RMAP=y\nCONFIG_CRC16=y\nCONFIG_CRYPTO_CRC32=y\nCONFIG_CRYPTO_CRC32C=y\nCONFIG_CRYPTO_RNG2=y\nCONFIG_DCACHE_WORD_ACCESS=y\nCONFIG_DEBUG_BUGVERBOSE=y\nCONFIG_DMADEVICES=y\nCONFIG_DMA_ENGINE=y\nCONFIG_DMA_OF=y\nCONFIG_DMA_REMAP=y\nCONFIG_DTC=y\nCONFIG_EDAC_SUPPORT=y\nCONFIG_EXT4_FS=y\nCONFIG_F2FS_FS=y\nCONFIG_FAILOVER=y\nCONFIG_FIX_EARLYCON_MEM=y\nCONFIG_FS_IOMAP=y\nCONFIG_FS_MBCACHE=y\nCONFIG_FW_LOADER_PAGED_BUF=y\nCONFIG_GENERIC_ALLOCATOR=y\nCONFIG_GENERIC_ARCH_TOPOLOGY=y\nCONFIG_GENERIC_BUG=y\nCONFIG_GENERIC_CLOCKEVENTS=y\nCONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y\nCONFIG_GENERIC_CPU_AUTOPROBE=y\nCONFIG_GENERIC_CPU_VULNERABILITIES=y\nCONFIG_GENERIC_EARLY_IOREMAP=y\nCONFIG_GENERIC_GETTIMEOFDAY=y\nCONFIG_GENERIC_IDLE_POLL_SETUP=y\nCONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y\nCONFIG_GENERIC_IRQ_MIGRATION=y\nCONFIG_GENERIC_IRQ_SHOW=y\nCONFIG_GENERIC_IRQ_SHOW_LEVEL=y\nCONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y\nCONFIG_GENERIC_MSI_IRQ=y\nCONFIG_GENERIC_MSI_IRQ_DOMAIN=y\nCONFIG_GENERIC_PCI_IOMAP=y\nCONFIG_GENERIC_SCHED_CLOCK=y\nCONFIG_GENERIC_SMP_IDLE_THREAD=y\nCONFIG_GENERIC_STRNCPY_FROM_USER=y\nCONFIG_GENERIC_STRNLEN_USER=y\nCONFIG_GENERIC_TIME_VSYSCALL=y\nCONFIG_GPIOLIB=y\nCONFIG_GPIOLIB_IRQCHIP=y\nCONFIG_GPIO_CDEV=y\nCONFIG_GPIO_PL061=y\nCONFIG_HANDLE_DOMAIN_IRQ=y\nCONFIG_HARDIRQS_SW_RESEND=y\nCONFIG_HAS_DMA=y\nCONFIG_HAS_IOMEM=y\nCONFIG_HAS_IOPORT_MAP=y\nCONFIG_HOTPLUG_CPU=y\nCONFIG_HVC_DRIVER=y\nCONFIG_INITRAMFS_SOURCE=\"\"\nCONFIG_IRQCHIP=y\nCONFIG_IRQ_DOMAIN=y\nCONFIG_IRQ_DOMAIN_HIERARCHY=y\nCONFIG_IRQ_FORCED_THREADING=y\nCONFIG_IRQ_WORK=y\nCONFIG_JBD2=y\nCONFIG_LIBFDT=y\nCONFIG_LOCK_DEBUGGING_SUPPORT=y\nCONFIG_LOCK_SPIN_ON_OWNER=y\nCONFIG_MEMFD_CREATE=y\nCONFIG_MEMORY_BALLOON=y\nCONFIG_MIGRATION=y\nCONFIG_MUTEX_SPIN_ON_OWNER=y\nCONFIG_NEED_DMA_MAP_STATE=y\nCONFIG_NET_9P=y\n# CONFIG_NET_9P_DEBUG is not set\nCONFIG_NET_9P_VIRTIO=y\nCONFIG_NET_FAILOVER=y\nCONFIG_NET_FLOW_LIMIT=y\nCONFIG_NLS=y\nCONFIG_NVMEM=y\nCONFIG_OF=y\nCONFIG_OF_ADDRESS=y\nCONFIG_OF_EARLY_FLATTREE=y\nCONFIG_OF_FLATTREE=y\nCONFIG_OF_GPIO=y\nCONFIG_OF_IRQ=y\nCONFIG_OF_KOBJ=y\nCONFIG_PADATA=y\nCONFIG_PAGE_REPORTING=y\nCONFIG_PARTITION_PERCPU=y\nCONFIG_PCI=y\nCONFIG_PCI_DOMAINS=y\nCONFIG_PCI_DOMAINS_GENERIC=y\nCONFIG_PCI_ECAM=y\nCONFIG_PCI_HOST_COMMON=y\nCONFIG_PCI_HOST_GENERIC=y\nCONFIG_PCI_MSI=y\nCONFIG_PCI_MSI_IRQ_DOMAIN=y\nCONFIG_PGTABLE_LEVELS=3\nCONFIG_PHYS_ADDR_T_64BIT=y\nCONFIG_PTP_1588_CLOCK_OPTIONAL=y\nCONFIG_RATIONAL=y\nCONFIG_RFS_ACCEL=y\nCONFIG_RPS=y\nCONFIG_RTC_CLASS=y\nCONFIG_RTC_DRV_PL031=y\nCONFIG_RWSEM_SPIN_ON_OWNER=y\nCONFIG_SCSI=y\nCONFIG_SCSI_COMMON=y\nCONFIG_SCSI_VIRTIO=y\nCONFIG_SERIAL_8250_FSL=y\nCONFIG_SERIAL_AMBA_PL011=y\nCONFIG_SERIAL_AMBA_PL011_CONSOLE=y\nCONFIG_SERIAL_MCTRL_GPIO=y\nCONFIG_SG_POOL=y\nCONFIG_SMP=y\nCONFIG_SOCK_RX_QUEUE_MAPPING=y\nCONFIG_SPARSE_IRQ=y\nCONFIG_SRCU=y\nCONFIG_SWIOTLB=y\nCONFIG_TICK_CPU_ACCOUNTING=y\nCONFIG_TIMER_OF=y\nCONFIG_TIMER_PROBE=y\nCONFIG_TREE_RCU=y\nCONFIG_TREE_SRCU=y\nCONFIG_USB_SUPPORT=y\nCONFIG_VIRTIO=y\nCONFIG_VIRTIO_BALLOON=y\nCONFIG_VIRTIO_BLK=y\nCONFIG_VIRTIO_CONSOLE=y\nCONFIG_VIRTIO_MMIO=y\nCONFIG_VIRTIO_MMIO_CMDLINE_DEVICES=y\nCONFIG_VIRTIO_NET=y\nCONFIG_VIRTIO_PCI=y\nCONFIG_VIRTIO_PCI_LEGACY=y\nCONFIG_VIRTIO_PCI_LIB=y\nCONFIG_XPS=y\n"
  },
  {
    "path": "target/linux/armvirt/image/Makefile",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2016-2017 Yousong Zhou <yszhou4tech@gmail.com>\n\ninclude $(TOPDIR)/rules.mk\ninclude $(INCLUDE_DIR)/image.mk\n\ndefine Image/BuildKernel\n\t$(foreach k,$(filter zImage Image,$(KERNELNAME)), \\\n\t\tcp $(KDIR)/$(KERNELNAME) $(BIN_DIR)/$(IMG_PREFIX)-$(k) \\\n\t)\nendef\n\ndefine Image/Build/Initramfs\n\t$(foreach k,$(filter zImage Image,$(KERNELNAME)), \\\n\t\tcp $(KDIR)/$(k)-initramfs $(BIN_DIR)/$(IMG_PREFIX)-$(k)-initramfs \\\n\t)\nendef\n\ndefine Image/Build/gzip\n\tgzip -f9n $(BIN_DIR)/$(IMG_ROOTFS)-$(1).img\nendef\n\n$(eval $(call Image/gzip-ext4-padded-squashfs))\n\ndefine Image/Build\n\t$(call Image/Build/$(1))\n\t$(CP) $(KDIR)/root.$(1) $(BIN_DIR)/$(IMG_ROOTFS)-$(1).img\n\t$(call Image/Build/gzip/$(1))\nendef\n\n$(eval $(call BuildImage))\n"
  },
  {
    "path": "target/linux/at91/Makefile",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2006-2013 OpenWrt.org\n\ninclude $(TOPDIR)/rules.mk\n\nARCH:=arm\nBOARD:=at91\nBOARDNAME:=Microchip (Atmel AT91)\nFEATURES:=ext4 squashfs targz usbgadget ubifs\nSUBTARGETS:=sama7 sama5 sam9x\n\nKERNEL_PATCHVER:=5.10\n\ninclude $(INCLUDE_DIR)/target.mk\n\nKERNELNAME:=zImage dtbs\n\nDEFAULT_PACKAGES += kmod-usb-ohci kmod-at91-udc kmod-usb-gadget-eth\n\n$(eval $(call BuildTarget))\n"
  },
  {
    "path": "target/linux/at91/base-files/etc/board.d/02_network",
    "content": "#\n# Copyright (C) 2014-2015 OpenWrt.org\n#\n\n. /lib/functions/uci-defaults.sh\n\nboard_config_update\n\ncase \"$(board_name)\" in\n\natmel,sama5d3-xplained|microchip,sama7g5ek)\n\tucidef_set_interfaces_lan_wan \"eth0\" \"eth1\"\n\t;;\n\n*)\n\tucidef_set_interface_lan \"eth0\"\n\t;;\n\nesac\n\nboard_config_flush\n\nexit 0\n"
  },
  {
    "path": "target/linux/at91/base-files/etc/config/network",
    "content": "config interface loopback\n\toption ifname\tlo\n\toption proto\tstatic\n\toption ipaddr\t127.0.0.1\n\toption netmask\t255.0.0.0\n\nconfig interface lan\n\toption ifname\teth0\n\toption type \tnone\n\toption proto\tstatic\n\toption ipaddr\t192.168.1.1\n\toption netmask\t255.255.255.0\n\nconfig interface debug\n\toption ifname \tusb0\n\toption type \tnone\n\toption proto \tstatic\n\toption ipaddr\t172.18.0.18\n\toption netmask\t255.255.255.0\n\n"
  },
  {
    "path": "target/linux/at91/files/arch/arm/boot/dts/at91-q5xr5.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-only\n/*\n * q5xr5.dts - Device Tree file for Exegin Q5xR5 board\n *\n * Copyright (C) 2014 Owen Kirby <osk@exegin.com>\n */\n\n/dts-v1/;\n#include \"at91sam9g20.dtsi\"\n\n/ {\n\tmodel = \"Exegin Q5x (rev5)\";\n\tcompatible = \"exegin,q5xr5\", \"atmel,at91sam9g20\", \"atmel,at91sam9\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200 rootfstype=squashfs,jffs2\";\n\t};\n\n\tmemory {\n\t\treg = <0x20000000 0x0>;\n\t};\n\n\tclocks {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tranges;\n\n\t\tmain_clock: clock@0 {\n\t\t\tcompatible = \"atmel,osc\", \"fixed-clock\";\n\t\t\tclock-frequency = <18432000>;\n\t\t};\n\n\t\tslow_xtal {\n\t\t\tclock-frequency = <32768>;\n\t\t};\n\n\t\tmain_xtal {\n\t\t\tclock-frequency = <18432000>;\n\t\t};\n\t};\n\n\tahb {\n\t\tapb {\n\t\t\tpinctrl@fffff400 {\n\t\t\t\tboard {\n\t\t\t\t\tpinctrl_pck0_as_mck: pck0_as_mck {\n\t\t\t\t\t\tatmel,pins = <2 1 0x2 0x0>; /* PC1 periph B */\n\t\t\t\t\t};\n\t\t\t\t\tpinctrl_spi0_npcs0: spi0_npcs0 {\n\t\t\t\t\t\tatmel,pins = <0 3 0x1 0x0>; /* PA3 periph A */\n\t\t\t\t\t};\n\t\t\t\t\tpinctrl_spi0_npcs1: spi0_npcs1 {\n\t\t\t\t\t\tatmel,pins = <2 11 0x2 0x0>; /* PC11 periph B */\n\t\t\t\t\t};\n\t\t\t\t\tpinctrl_spi1_npcs0: spi1_npcs0 {\n\t\t\t\t\t\tatmel,pins = <1 3 0x1 0x0>; /* PB3 periph A */\n\t\t\t\t\t};\n\t\t\t\t\tpinctrl_spi1_npcs1: spi1_npcs1 {\n\t\t\t\t\t\tatmel,pins = <2 5 0x2 0x0>; /* PC5 periph B */\n\t\t\t\t\t};\n\t\t\t\t};\n\n\t\t\t\tspi0 {\n\t\t\t\t\tpinctrl_spi0: spi0-0 {\n\t\t\t\t\t\tatmel,pins =\n\t\t\t\t\t\t\t<0 0 0x1 0x0\t/* PA0 periph A SPI0_MISO pin */\n\t\t\t\t\t\t\t 0 1 0x1 0x0\t/* PA1 periph A SPI0_MOSI pin */\n\t\t\t\t\t\t\t 0 2 0x1 0x0>;\t/* PA2 periph A SPI0_SPCK pin */\n\t\t\t\t\t};\n\t\t\t\t};\n\n\t\t\t\tspi1 {\n\t\t\t\t\tpinctrl_spi1: spi1-0 {\n\t\t\t\t\t\tatmel,pins =\n\t\t\t\t\t\t\t<1 0 0x1 0x0\t/* PB0 periph A SPI1_MISO pin */\n\t\t\t\t\t\t\t 1 1 0x1 0x0\t/* PB1 periph A SPI1_MOSI pin */\n\t\t\t\t\t\t\t 1 2 0x1 0x0>;\t/* PB2 periph A SPI1_SPCK pin */\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tdbgu: serial@fffff200 {\n\t\t\t\tstatus = \"okay\";\n\t\t\t};\n\n\t\t\tusart0: serial@fffb0000 {\n\t\t\t\tpinctrl-0 =\n\t\t\t\t\t<&pinctrl_usart0\n\t\t\t\t\t &pinctrl_usart0_rts\n\t\t\t\t\t &pinctrl_usart0_cts\n\t\t\t\t\t &pinctrl_usart0_dtr_dsr\n\t\t\t\t\t &pinctrl_usart0_dcd\n\t\t\t\t\t &pinctrl_usart0_ri>;\n\t\t\t\tstatus = \"okay\";\n\t\t\t};\n\n\t\t\tmacb0: ethernet@fffc4000 {\n\t\t\t\tphy-mode = \"mii\";\n\t\t\t\tstatus = \"okay\";\n\t\t\t};\n\n\t\t\tusb1: gadget@fffa4000 {\n\t\t\t\tstatus = \"okay\";\n\t\t\t};\n\n\t\t\twatchdog@fffffd40 {\n\t\t\t\tstatus = \"okay\";\n\t\t\t};\n\n\t\t\tspi0: spi@fffc8000 {\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\t\t\t\tcompatible = \"atmel,at91rm9200-spi\";\n\t\t\t\treg = <0xfffc8000 0x200>;\n\t\t\t\tinterrupts = <12 4 3>;\n\t\t\t\tpinctrl-names = \"default\";\n\t\t\t\tpinctrl-0 = <&pinctrl_spi0>;\n\t\t\t\tstatus = \"okay\";\n\t\t\t\tcs-gpios = <&pioA 3 0>, <&pioC 11 1>, <0>, <0>;\n\n\t\t\t\tm25p80@0 {\n\t\t\t\t\tcompatible = \"sst,sst25vf040b\";\n\t\t\t\t\tspi-max-frequency = <20000000>;\n\t\t\t\t\treg = <0>;\n\t\t\t\t\t#address-cells = <1>;\n\t\t\t\t\t#size-cells = <1>;\n\n\t\t\t\t\tat91boot@0 {\n\t\t\t\t\t\tlabel = \"at91boot\";\n\t\t\t\t\t\treg = <0x0 0x4000>;\n\t\t\t\t\t};\n\t\t\t\t\tuenv@4000 {\n\t\t\t\t\t\tlabel = \"uboot-env\";\n\t\t\t\t\t\treg = <0x4000 0x4000>;\n\t\t\t\t\t};\n\t\t\t\t\tuboot@8000 {\n\t\t\t\t\t\tlabel = \"uboot\";\n\t\t\t\t\t\treg = <0x8000 0x3E000>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t\tspidev@1 {\n\t\t\t\t\tcompatible = \"spidev\";\n\t\t\t\t\tspi-max-frequency = <2000000>;\n\t\t\t\t\treg = <1>;\n\t\t\t\t};\n\t\t\t};\n\t\t\tspi1: spi@fffcc000 {\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\t\t\t\tcompatible = \"atmel,at91rm9200-spi\";\n\t\t\t\treg = <0xfffcc000 0x200>;\n\t\t\t\tinterrupts = <13 4 3>;\n\t\t\t\tpinctrl-names = \"default\";\n\t\t\t\tpinctrl-0 = <&pinctrl_spi1>;\n\t\t\t\tcs-gpios = <&pioB 3 0>, <&pioC 5 1>, <0>, <0>;\n\t\t\t\tstatus = \"okay\";\n\n\t\t\t\tspidev@0 {\n\t\t\t\t\tcompatible = \"spidev\";\n\t\t\t\t\tspi-max-frequency = <2000000>;\n\t\t\t\t\treg = <0>;\n\t\t\t\t};\n\t\t\t\tspidev@1 {\n\t\t\t\t\tcompatible = \"spidev\";\n\t\t\t\t\tspi-max-frequency = <2000000>;\n\t\t\t\t\treg = <1>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tusb0: ohci@500000 {\n\t\t\tnum-ports = <2>;\n\t\t\tstatus = \"okay\";\n\t\t};\n\t};\n\n\tflash@10000000 {\n\t\tcompatible = \"cfi-flash\";\n\t\tbank-width = <2>;\n\t\treg = <0x10000000 0x00800000>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tkernel@0 {\n\t\t\tlabel = \"kernel\";\n\t\t\treg = <0x0 0x200000>;\n\t\t};\n\t\trootfs@200000 {\n\t\t\tlabel = \"rootfs\";\n\t\t\treg = <0x200000 0x600000>;\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/at91/files/arch/arm/boot/dts/lmu5000.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-only\n/*\n * lmu5000.dst - Device Tree file for CalAmp LMU5000 board\n *\n * Copyright (C) 2013 Adam Porter <porter.adam@gmail.com>\n */\n\n/dts-v1/;\n#include \"at91sam9g20.dtsi\"\n\n/ {\n\tmodel = \"CalAmp LMU5000\";\n\tcompatible = \"calamp,lmu5000\", \"atmel,at91sam9g20\", \"atmel,at91sam9\";\n\n\tchosen {\n\t\tbootargs = \"mem=64M console=ttyS0,115200 rootfstype=jffs2\";\n\t};\n\n\tmemory {\n\t\treg = <0x20000000 0x4000000>;\n\t};\n\n\tclocks {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tranges;\n\n\t\tmain_clock: clock@0 {\n\t\t\tcompatible = \"atmel,osc\", \"fixed-clock\";\n\t\t\tclock-frequency = <18432000>;\n\t\t};\n\t};\n\n\tahb {\n\t\tapb {\n\t\t\tpinctrl@fffff400 {\n\t\t\t\tboard {\n\t\t\t\t\tpinctrl_pck0_as_mck: pck0_as_mck {\n\t\t\t\t\t\tatmel,pins =\n\t\t\t\t\t\t\t<2 1 0x2 0x0>;\t/* PC1 periph B */\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tdbgu: serial@fffff200 {\n\t\t\t\tstatus = \"okay\";\n\t\t\t};\n\n\t\t\tusart0: serial@fffb0000 {\n\t\t\t\tpinctrl-0 =\n\t\t\t\t\t<&pinctrl_usart0\n\t\t\t\t\t &pinctrl_usart0_rts\n\t\t\t\t\t &pinctrl_usart0_cts\n\t\t\t\t\t &pinctrl_usart0_dtr_dsr\n\t\t\t\t\t &pinctrl_usart0_dcd\n\t\t\t\t\t &pinctrl_usart0_ri>;\n\t\t\t\tstatus = \"okay\";\n\t\t\t};\n\n\t\t\tusart2: serial@fffb8000 {\n\t\t\t\tstatus = \"okay\";\n\t\t\t};\n\n\t\t\tuart0: serial@fffd4000 {\n\t\t\t\tstatus = \"okay\";\n\t\t\t};\n\n\t\t\tuart1: serial@fffd8000 {\n\t\t\t\tstatus = \"okay\";\n\t\t\t};\n\n\t\t\tmacb0: ethernet@fffc4000 {\n\t\t\t\tphy-mode = \"mii\";\n\t\t\t\tstatus = \"okay\";\n\t\t\t};\n\n\t\t\tusb1: gadget@fffa4000 {\n\t\t\t\tatmel,vbus-gpio = <&pioC 5 0>;\n\t\t\t\tstatus = \"okay\";\n\t\t\t};\n\n\t\t\tssc0: ssc@fffbc000 {\n\t\t\t\tstatus = \"okay\";\n\t\t\t\tpinctrl-0 = <&pinctrl_ssc0_tx>;\n\t\t\t};\n\n\t\t\twatchdog@fffffd40 {\n\t\t\t\tstatus = \"okay\";\n\t\t\t};\n\t\t};\n\n\t\tnand0: nand@40000000 {\n\t\t\tnand-bus-width = <8>;\n\t\t\tnand-ecc-mode = \"soft\";\n\t\t\tnand-on-flash-bbt;\n\t\t\tstatus = \"okay\";\n\n\t\t\tkernel@0 {\n\t\t\t\tlabel = \"kernel\";\n\t\t\t\treg = <0x0 0x400000>;\n\t\t\t};\n\n\t\t\trootfs@400000 {\n\t\t\t\tlabel = \"rootfs\";\n\t\t\t\treg = <0x400000 0x3C00000>;\n\t\t\t};\n\n\t\t\tuser1@4000000 {\n\t\t\t\tlabel = \"user1\";\n\t\t\t\treg = <0x4000000 0x2000000>;\n\t\t\t};\n\n\t\t\tuser2@6000000 {\n\t\t\t\tlabel = \"user2\";\n\t\t\t\treg = <0x6000000 0x2000000>;\n\t\t\t};\n\t\t};\n\n\t\tusb0: ohci@500000 {\n\t\t\tnum-ports = <2>;\n\t\t\tstatus = \"okay\";\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/at91/image/Config.in",
    "content": "config AT91_DFBOOT\n\tbool \"Build dataflashboot loader\"\n\tdepends on TARGET_at91\n\tdefault n\n\nconfig FLEXIBITY_ROOT\n\tbool \"Build Flexibity RootFS (with embedded kernel)\"\n\tdepends on TARGET_at91_flexibity\n\tdefault n\n\n"
  },
  {
    "path": "target/linux/at91/image/Makefile",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2006-2013 OpenWrt.org\n\ninclude $(TOPDIR)/rules.mk\ninclude $(INCLUDE_DIR)/image.mk\n\nKERNEL_LOADADDR := 0x20008000\n\ndefine Build/at91-install-zImage\n\t$(CP) $(KDIR)/zImage $@\nendef\n\ninclude $(SUBTARGET).mk\n\nAT91_SD_BOOT_PARTSIZE:=64\nFAT32_BLOCK_SIZE:=1024\nFAT32_BLOCKS:=$(shell echo \\\n  $$(($(AT91_SD_BOOT_PARTSIZE)*1024*1024/$(FAT32_BLOCK_SIZE))))\n\ndefine Device/Default\n  $(Device/default-nand)\n  PROFILES := Default\n  FILESYSTEMS := squashfs ubifs ext4\n  DEVICE_DTS = $(lastword $(subst _, ,$(1)))\n  KERNEL_NAME := zImage\n  KERNEL_SIZE := 4096k\n  KERNEL := kernel-bin | append-dtb | lzma | uImage lzma\n  DTB_SIZE := 128k\nendef\n\ndefine Device/dtb\n  KERNEL := kernel-bin | lzma | uImage lzma\nendef\n\ndefine Device/evaluation-sdimage\n  IMAGES += sdcard.img.gz\n  IMAGE/sdcard.img.gz := at91-sdcard\nendef\n\ndefine Device/evaluation\n  KERNEL_INSTALL := 1\n  KERNEL_SUFFIX := -uImage\n  IMAGES := root.ubi\n  IMAGE/root.ubi := append-ubi\nendef\n\ndefine Device/evaluation-zImage\n  IMAGES += zImage\n  IMAGE/zImage := at91-install-zImage\nendef\n\ndefine Device/evaluation-dtb\n  $(Device/evaluation)\n  $(Device/dtb)\n  KERNEL_SUFFIX := -fit-zImage.itb\n  KERNEL = kernel-bin | gzip | fit gzip $$(KDIR)/image-$$(DEVICE_DTS).dtb\nendef\n\ndefine Device/evaluation-fit\n  $(Device/evaluation)\n  KERNEL_SUFFIX := -fit-uImage.itb\n  KERNEL = kernel-bin | lzma | fit lzma $$(KDIR)/image-$$(DEVICE_DTS).dtb\nendef\n\ndefine Device/production\n  UBINIZE_OPTS := -E 5\n  IMAGES := factory.bin\n  IMAGE/factory.bin := append-kernel | pad-to $$$$(KERNEL_SIZE) | append-ubi\nendef\n\ndefine Device/production-dtb\n  $(Device/production)\n  $(Device/dtb)\n  IMAGE/factory.bin := append-dtb | pad-to $$$$(DTB_SIZE) | \\\n\tappend-kernel | pad-to $$$$(KERNEL_SIZE) | append-ubi\nendef\n\n$(eval $(call BuildImage))\n"
  },
  {
    "path": "target/linux/at91/image/dfboot/Makefile",
    "content": "#\n# Copyright (C) 2006 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\ninclude $(INCLUDE_DIR)/kernel.mk\n\nPKG_NAME:=dfboot\nPKG_VERSION:=0.1\nPKG_RELEASE:=1\n\nPKG_BUILD_DIR:=$(KERNEL_BUILD_DIR)/$(PKG_NAME)\n\ninclude $(INCLUDE_DIR)/package.mk\n\ndefine Build/Prepare\n\tmkdir -p $(PKG_BUILD_DIR)\n\t$(CP) ./src/* $(PKG_BUILD_DIR)/\nendef\n\ndefine Build/Compile\n\t$(MAKE) -C $(PKG_BUILD_DIR) \\\n\t\t$(TARGET_CONFIGURE_OPTS) \\\n\t\tCFLAGS=\"$(TARGET_CFLAGS)\" \\\n\t\tLDFLAGS=\"$(LIBGCC_S)\"\nendef\n\ndefine Build/InstallDev\n\tdd if=$(PKG_BUILD_DIR)/binary/dfboot.bin of=$(PKG_BUILD_DIR)/binary/dfboot.block bs=32k count=1 conv=sync\nendef\n\n$(eval $(call Build/DefaultTargets))\n"
  },
  {
    "path": "target/linux/at91/image/dfboot/src/Makefile",
    "content": "# Makefile for DataFlashBoot.bin\n# Must use toolchain with H/W FLoating Point\n\nBASENAME=dfboot\nBINNAME=$(BASENAME).bin\nOUTNAME=$(BASENAME).out\nLSSNAME=$(BASENAME).lss\nMAPNAME=$(BASENAME).map\n\nBASENAME2=dfbptest\nBINNAME2=$(BASENAME2).bin\nOUTNAME2=$(BASENAME2).out\nLSSNAME2=$(BASENAME2).lss\nMAPNAME2=$(BASENAME2).map\n\nINCPATH=include\n\nCFLAGS_LOCAL=-Os -Wall -I$(INCPATH)\nBUILD=$(CC) $(CFLAGS) $(CFLAGS_LOCAL)\n\nLDFLAGS+=-T elf32-littlearm.lds -Ttext 0\nLINK=$(LD) $(LDFLAGS)\n\nOBJS=objs/cstartup_ram.o objs/at45.o objs/com.o objs/dataflash.o\\\n\tobjs/div0.o objs/init.o objs/main.o objs/asm_isr.o objs/asm_mci_isr.o\\\n\tobjs/mci_device.o objs/jump.o objs/_udivsi3.o objs/_umodsi3.o\n\nOBJS2=objs/cstartup_ram.o objs/at45.o objs/com.o objs/dataflash.o\\\n\tobjs/div0.o objs/init.o objs/ptmain.o objs/asm_isr.o objs/asm_mci_isr.o\\\n\tobjs/mci_device.o objs/jump.o objs/_udivsi3.o objs/_umodsi3.o\n\nI=config.h com.h dataflash.h embedded_services.h main.h stdio.h include/AT91RM9200.h include/lib_AT91RM9200.h \n\nall:clean $(BASENAME) $(BASENAME2)\n\n$(BASENAME): $(OBJS)\n\t$(LINK) -n -o $(OUTNAME) $(OBJS)\n\t$(OBJCOPY) $(OUTNAME) -O binary $(BINNAME)\n\t$(OBJDUMP) -h -s $(OUTNAME) > $(LSSNAME)\n\t$(NM) -n $(OUTNAME) | grep -v '\\( [aUw] \\)\\|\\(__crc_\\)\\|\\( \\$[adt]\\)' > $(MAPNAME)\n\tcp $(BINNAME) binary\n\t\n$(BASENAME2): $(OBJS2)\n\t$(LINK) -n -o $(OUTNAME2) $(OBJS2)\n\t$(OBJCOPY) $(OUTNAME2) -O binary $(BINNAME2)\n\t$(OBJDUMP) -h -s $(OUTNAME2) > $(LSSNAME2)\n\t$(NM) -n $(OUTNAME2) | grep -v '\\( [aUw] \\)\\|\\(__crc_\\)\\|\\( \\$[adt]\\)' > $(MAPNAME2)\n\tcp $(BINNAME2) binary\n\t\n# C objects here\nobjs/at45.o: at45.c\t$(I)\n\t$(BUILD) -c -o objs/at45.o\t\tat45.c\nobjs/com.o: com.c\t$(I)\n\t$(BUILD) -c -o objs/com.o\t\tcom.c\nobjs/dataflash.o: dataflash.c\t$(I)\n\t$(BUILD) -c -o objs/dataflash.o\t\tdataflash.c\nobjs/mci_device.o: mci_device.c\t$(I)\n\t$(BUILD) -c -o objs/mci_device.o\t\tmci_device.c\nobjs/div0.o: div0.c\t$(I)\n\t$(BUILD) -c -o objs/div0.o\t\tdiv0.c\nobjs/init.o: init.c\t$(I)\n\t$(BUILD) -c -o objs/init.o\t\tinit.c\nobjs/main.o: main.c\t$(I)\n\t$(BUILD) -c -o objs/main.o\t\tmain.c\nobjs/ptmain.o: main.c\t$(I)\n\t$(BUILD) -c -D PRODTEST -o objs/ptmain.o\t\tmain.c\n\n# ASM objects here\nobjs/asm_isr.o: asm_isr.S\n\t$(BUILD) -c -o objs/asm_isr.o\t\tasm_isr.S\nobjs/asm_mci_isr.o: asm_mci_isr.S\n\t$(BUILD) -c -o objs/asm_mci_isr.o\t\tasm_mci_isr.S\nobjs/cstartup_ram.o: cstartup_ram.S\n\t$(BUILD) -c -o objs/cstartup_ram.o\tcstartup_ram.S\nobjs/jump.o: jump.S\n\t$(BUILD) -c -o objs/jump.o\t\tjump.S\nobjs/_udivsi3.o: _udivsi3.S\n\t$(BUILD) -c -o objs/_udivsi3.o\t\t_udivsi3.S\nobjs/_umodsi3.o: _umodsi3.S\n\t$(BUILD) -c -o objs/_umodsi3.o \t\t_umodsi3.S\n\ninstall:\t$(BINNAME) $(BINNAME2)\n\tcp $(BINNAME) binary\n\tcp $(BINNAME2) binary\n\nclean:\n\trm -f *~\n\trm -f objs/*\n\trm -f *.out\n\trm -f *.bin\n\trm -f *.lss\n\trm -f *.map\n\trm -f .unpacked\n\tmkdir -p objs\n"
  },
  {
    "path": "target/linux/at91/image/dfboot/src/_udivsi3.S",
    "content": "/* # 1 \"libgcc1.S\" */\n@ libgcc1 routines for ARM cpu.\n@ Division routines, written by Richard Earnshaw, (rearnsha@armltd.co.uk)\ndividend\t.req\tr0\ndivisor\t\t.req\tr1\nresult\t\t.req\tr2\ncurbit\t\t.req\tr3\n/* ip\t\t.req\tr12\t*/\n/* sp\t\t.req\tr13\t*/\n/* lr\t\t.req\tr14\t*/\n/* pc\t\t.req\tr15\t*/\n\t.text\n\t.globl\t __udivsi3\n\t.type  __udivsi3       ,function\n\t.align\t0\n __udivsi3      :\n\tcmp\tdivisor, #0\n\tbeq\tLdiv0\n\tmov\tcurbit, #1\n\tmov\tresult, #0\n\tcmp\tdividend, divisor\n\tbcc\tLgot_result\nLoop1:\n\t@ Unless the divisor is very big, shift it up in multiples of\n\t@ four bits, since this is the amount of unwinding in the main\n\t@ division loop.  Continue shifting until the divisor is\n\t@ larger than the dividend.\n\tcmp\tdivisor, #0x10000000\n\tcmpcc\tdivisor, dividend\n\tmovcc\tdivisor, divisor, lsl #4\n\tmovcc\tcurbit, curbit, lsl #4\n\tbcc\tLoop1\nLbignum:\n\t@ For very big divisors, we must shift it a bit at a time, or\n\t@ we will be in danger of overflowing.\n\tcmp\tdivisor, #0x80000000\n\tcmpcc\tdivisor, dividend\n\tmovcc\tdivisor, divisor, lsl #1\n\tmovcc\tcurbit, curbit, lsl #1\n\tbcc\tLbignum\nLoop3:\n\t@ Test for possible subtractions, and note which bits\n\t@ are done in the result.  On the final pass, this may subtract\n\t@ too much from the dividend, but the result will be ok, since the\n\t@ \"bit\" will have been shifted out at the bottom.\n\tcmp\tdividend, divisor\n\tsubcs\tdividend, dividend, divisor\n\torrcs\tresult, result, curbit\n\tcmp\tdividend, divisor, lsr #1\n\tsubcs\tdividend, dividend, divisor, lsr #1\n\torrcs\tresult, result, curbit, lsr #1\n\tcmp\tdividend, divisor, lsr #2\n\tsubcs\tdividend, dividend, divisor, lsr #2\n\torrcs\tresult, result, curbit, lsr #2\n\tcmp\tdividend, divisor, lsr #3\n\tsubcs\tdividend, dividend, divisor, lsr #3\n\torrcs\tresult, result, curbit, lsr #3\n\tcmp\tdividend, #0\t\t\t@ Early termination?\n\tmovnes\tcurbit, curbit, lsr #4\t\t@ No, any more bits to do?\n\tmovne\tdivisor, divisor, lsr #4\n\tbne\tLoop3\nLgot_result:\n\tmov\tr0, result\n\tmov \tpc, lr\nLdiv0:\n\tstr\tlr, [sp, #-4]!\n\tbl\t __div0       (PLT)\n\tmov\tr0, #0\t\t\t@ about as wrong as it could be\n\tldmia\tsp!, {pc}\n\t.size  __udivsi3       , . -  __udivsi3\n/* # 235 \"libgcc1.S\" */\n/* # 320 \"libgcc1.S\" */\n/* # 421 \"libgcc1.S\" */\n/* # 433 \"libgcc1.S\" */\n/* # 456 \"libgcc1.S\" */\n/* # 500 \"libgcc1.S\" */\n/* # 580 \"libgcc1.S\" */\n"
  },
  {
    "path": "target/linux/at91/image/dfboot/src/_umodsi3.S",
    "content": "/* # 1 \"libgcc1.S\" */\n@ libgcc1 routines for ARM cpu.\n@ Division routines, written by Richard Earnshaw, (rearnsha@armltd.co.uk)\n/* # 145 \"libgcc1.S\" */\ndividend\t.req\tr0\ndivisor\t\t.req\tr1\noverdone\t.req\tr2\ncurbit\t\t.req\tr3\n/* ip\t\t.req\tr12\t*/\n/* sp\t\t.req\tr13\t*/\n/* lr\t\t.req\tr14\t*/\n/* pc\t\t.req\tr15\t*/\n\t.text\n\t.globl\t __umodsi3\n\t.type  __umodsi3       ,function\n\t.align 0\n __umodsi3      :\n\tcmp\tdivisor, #0\n\tbeq\tLdiv0\n\tmov\tcurbit, #1\n\tcmp\tdividend, divisor\n\tmovcc  \tpc, lr\nLoop1:\n\t@ Unless the divisor is very big, shift it up in multiples of\n\t@ four bits, since this is the amount of unwinding in the main\n\t@ division loop.  Continue shifting until the divisor is\n\t@ larger than the dividend.\n\tcmp\tdivisor, #0x10000000\n\tcmpcc\tdivisor, dividend\n\tmovcc\tdivisor, divisor, lsl #4\n\tmovcc\tcurbit, curbit, lsl #4\n\tbcc\tLoop1\nLbignum:\n\t@ For very big divisors, we must shift it a bit at a time, or\n\t@ we will be in danger of overflowing.\n\tcmp\tdivisor, #0x80000000\n\tcmpcc\tdivisor, dividend\n\tmovcc\tdivisor, divisor, lsl #1\n\tmovcc\tcurbit, curbit, lsl #1\n\tbcc\tLbignum\nLoop3:\n\t@ Test for possible subtractions.  On the final pass, this may\n\t@ subtract too much from the dividend, so keep track of which\n\t@ subtractions are done, we can fix them up afterwards...\n\tmov\toverdone, #0\n\tcmp\tdividend, divisor\n\tsubcs\tdividend, dividend, divisor\n\tcmp\tdividend, divisor, lsr #1\n\tsubcs\tdividend, dividend, divisor, lsr #1\n\torrcs\toverdone, overdone, curbit, ror #1\n\tcmp\tdividend, divisor, lsr #2\n\tsubcs\tdividend, dividend, divisor, lsr #2\n\torrcs\toverdone, overdone, curbit, ror #2\n\tcmp\tdividend, divisor, lsr #3\n\tsubcs\tdividend, dividend, divisor, lsr #3\n\torrcs\toverdone, overdone, curbit, ror #3\n\tmov\tip, curbit\n\tcmp\tdividend, #0\t\t\t@ Early termination?\n\tmovnes\tcurbit, curbit, lsr #4\t\t@ No, any more bits to do?\n\tmovne\tdivisor, divisor, lsr #4\n\tbne\tLoop3\n\t@ Any subtractions that we should not have done will be recorded in\n\t@ the top three bits of \"overdone\".  Exactly which were not needed\n\t@ are governed by the position of the bit, stored in ip.\n\t@ If we terminated early, because dividend became zero,\n\t@ then none of the below will match, since the bit in ip will not be\n\t@ in the bottom nibble.\n\tands\toverdone, overdone, #0xe0000000\n\tmoveq  \tpc, lr\t\t\t\t@ No fixups needed\n\ttst\toverdone, ip, ror #3\n\taddne\tdividend, dividend, divisor, lsr #3\n\ttst\toverdone, ip, ror #2\n\taddne\tdividend, dividend, divisor, lsr #2\n\ttst\toverdone, ip, ror #1\n\taddne\tdividend, dividend, divisor, lsr #1\n\tmov \tpc, lr\nLdiv0:\n\tstr\tlr, [sp, #-4]!\n\tbl\t __div0       (PLT)\n\tmov\tr0, #0\t\t\t@ about as wrong as it could be\n\tldmia\tsp!, {pc}\n\t.size  __umodsi3       , . -  __umodsi3\n/* # 320 \"libgcc1.S\" */\n/* # 421 \"libgcc1.S\" */\n/* # 433 \"libgcc1.S\" */\n/* # 456 \"libgcc1.S\" */\n/* # 500 \"libgcc1.S\" */\n/* # 580 \"libgcc1.S\" */\n"
  },
  {
    "path": "target/linux/at91/image/dfboot/src/asm_isr.S",
    "content": "#include \"AT91RM9200_inc.h\"\n\n#define ARM_MODE_USER           0x10\n#define ARM_MODE_FIQ            0x11\n#define ARM_MODE_IRQ            0x12\n#define ARM_MODE_SVC            0x13\n#define ARM_MODE_ABORT          0x17\n#define ARM_MODE_UNDEF          0x1B\n#define ARM_MODE_SYS            0x1F\n\n#define I_BIT                   0x80\n#define F_BIT                   0x40\n#define T_BIT                   0x20\n\n\n/* -----------------------------------------------------------------------------\n   AT91F_ASM_SPI_Handler\n   ---------------------\n      Handler called by the AIC\n        \n      Save context\n        Call C handler\n    Restore context\n   ----------------------------------------------------------------------------- */\n\t\t\n.global AT91F_ST_ASM_HANDLER\n\nAT91F_ST_ASM_HANDLER:\n/*  Adjust and save LR_irq in IRQ stack */\n \tsub         r14, r14, #4\n\tstmfd       sp!, {r14}\n\n/*  Write in the IVR to support Protect Mode\n  No effect in Normal Mode\n  De-assert the NIRQ and clear the source in Protect Mode */\n\tldr         r14, =AT91C_BASE_AIC\n\tstr         r14, [r14, #AIC_IVR]\n\n/*  Save SPSR and r0 in IRQ stack */\n\tmrs         r14, SPSR\n\tstmfd       sp!, {r0, r14}\n\n/*  Enable Interrupt and Switch in SYS Mode */\n\tmrs         r0, CPSR\n\tbic         r0, r0, #I_BIT\n\torr         r0, r0, #ARM_MODE_SYS\n\tmsr         CPSR_c, r0\n \n/* Save scratch/used registers and LR in User Stack */\n\tstmfd       sp!, { r1-r3, r12, r14}\n\n\tldr     r1, =AT91F_ST_HANDLER\n\tmov     r14, pc\n\tbx      r1\n\n/*  Restore scratch/used registers and LR from User Stack */\n\tldmia       sp!, { r1-r3, r12, r14}\n\n/*  Disable Interrupt and switch back in IRQ mode */\n\tmrs         r0, CPSR\n\tbic         r0, r0, #ARM_MODE_SYS\n\torr         r0, r0, #I_BIT | ARM_MODE_IRQ\n\tmsr         CPSR_c, r0\n\n/*  Mark the End of Interrupt on the AIC */\n\tldr         r0, =AT91C_BASE_AIC\n\tstr         r0, [r0, #AIC_EOICR]\n\n/*  Restore SPSR_irq and r0 from IRQ stack */\n\tldmia       sp!, {r0, r14}\n\tmsr         SPSR_cxsf, r14\n\n/*  Restore adjusted  LR_irq from IRQ stack directly in the PC */\n\tldmia       sp!, {pc}^\n\n"
  },
  {
    "path": "target/linux/at91/image/dfboot/src/asm_mci_isr.S",
    "content": "#include <AT91RM9200_inc.h>\n\n#define ARM_MODE_USER           0x10\n#define ARM_MODE_FIQ            0x11\n#define ARM_MODE_IRQ            0x12\n#define ARM_MODE_SVC            0x13\n#define ARM_MODE_ABORT          0x17\n#define ARM_MODE_UNDEF          0x1B\n#define ARM_MODE_SYS            0x1F\n\n#define I_BIT                   0x80\n#define F_BIT                   0x40\n#define T_BIT                   0x20\n\n\n/* -----------------------------------------------------------------------------\n   AT91F_ASM_MCI_Handler\n   ---------------------\n      Handler called by the AIC\n        \n      Save context\n        Call C handler\n    Restore context\n   ----------------------------------------------------------------------------- */\n\t\t\n.global AT91F_ASM_MCI_Handler  \n\nAT91F_ASM_MCI_Handler:\n/*  Adjust and save LR_irq in IRQ stack */\n \tsub         r14, r14, #4\n\tstmfd       sp!, {r14}\n\n/*  Write in the IVR to support Protect Mode\n  No effect in Normal Mode\n  De-assert the NIRQ and clear the source in Protect Mode */\n\tldr         r14, =AT91C_BASE_AIC\n\tstr         r14, [r14, #AIC_IVR]\n\n/*  Save SPSR and r0 in IRQ stack */\n\tmrs         r14, SPSR\n\tstmfd       sp!, {r0, r14}\n\n/*  Enable Interrupt and Switch in SYS Mode */\n\tmrs         r0, CPSR\n\tbic         r0, r0, #I_BIT\n\torr         r0, r0, #ARM_MODE_SYS\n\tmsr         CPSR_c, r0\n \n/* Save scratch/used registers and LR in User Stack */\n\tstmfd       sp!, { r1-r3, r12, r14}\n\n\tldr     r1, =AT91F_MCI_Handler\n\tmov     r14, pc\n\tbx      r1\n\n/*  Restore scratch/used registers and LR from User Stack */\n\tldmia       sp!, { r1-r3, r12, r14}\n\n/*  Disable Interrupt and switch back in IRQ mode */\n\tmrs         r0, CPSR\n\tbic         r0, r0, #ARM_MODE_SYS\n\torr         r0, r0, #I_BIT | ARM_MODE_IRQ\n\tmsr         CPSR_c, r0\n\n/*  Mark the End of Interrupt on the AIC */\n\tldr         r0, =AT91C_BASE_AIC\n\tstr         r0, [r0, #AIC_EOICR]\n\n/*  Restore SPSR_irq and r0 from IRQ stack */\n\tldmia       sp!, {r0, r14}\n\tmsr         SPSR_cxsf, r14\n\n/*  Restore adjusted  LR_irq from IRQ stack directly in the PC */\n\tldmia       sp!, {pc}^\n\n"
  },
  {
    "path": "target/linux/at91/image/dfboot/src/at45.c",
    "content": "/*----------------------------------------------------------------------------\n *      ATMEL Microcontroller Software Support  -  ROUSSET  -\n *----------------------------------------------------------------------------\n * The software is delivered \"AS IS\" without warranty or condition of any\n * kind, either express, implied or statutory. This includes without\n * limitation any warranty or condition with respect to merchantability or\n * fitness for any particular purpose, or against the infringements of\n * intellectual property rights of others.\n *----------------------------------------------------------------------------\n * File Name           : at45c.h\n * Object              : \n *\n * 1.0  10/12/03 HIi    : Creation.\n * 1.01 03/05/04 HIi    : Bug Fix in AT91F_DataFlashWaitReady() Function.\n *----------------------------------------------------------------------------\n */\n#include \"config.h\"\n#include \"stdio.h\"\n#include \"AT91RM9200.h\"\n#include \"lib_AT91RM9200.h\"\n#include \"dataflash.h\"\n#include \"main.h\"\n\n\n/*----------------------------------------------------------------------------*/\n/* \\fn    AT91F_SpiInit                                                       */\n/* \\brief SPI Low level Init                                                  */\n/*----------------------------------------------------------------------------*/\nvoid AT91F_SpiInit(void) {\n\t/* Configure PIOs */\n\tAT91C_BASE_PIOA->PIO_ASR = AT91C_PA3_NPCS0 | AT91C_PA4_NPCS1 | \n\t                           AT91C_PA1_MOSI | AT91C_PA5_NPCS2 |\n\t                           AT91C_PA6_NPCS3 | AT91C_PA0_MISO |\n\t                           AT91C_PA2_SPCK;\n\tAT91C_BASE_PIOA->PIO_PDR = AT91C_PA3_NPCS0 | AT91C_PA4_NPCS1 |\n\t                           AT91C_PA1_MOSI | AT91C_PA5_NPCS2 |\n\t                           AT91C_PA6_NPCS3 | AT91C_PA0_MISO |\n\t                           AT91C_PA2_SPCK;\n\t/* Enable CLock */\n\tAT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_SPI;\n\n\t/* Reset the SPI */\n\tAT91C_BASE_SPI->SPI_CR = AT91C_SPI_SWRST;\n\n\t/* Configure SPI in Master Mode with No CS selected !!! */\n\tAT91C_BASE_SPI->SPI_MR = AT91C_SPI_MSTR | AT91C_SPI_MODFDIS | AT91C_SPI_PCS;\n\n\t/* Configure CS0 and CS3 */\n\t*(AT91C_SPI_CSR + 0) = AT91C_SPI_CPOL | (AT91C_SPI_DLYBS & DATAFLASH_TCSS) |\n\t                       (AT91C_SPI_DLYBCT & DATAFLASH_TCHS) |\n\t                       ((AT91C_MASTER_CLOCK / (2*AT91C_SPI_CLK)) << 8);\n\t*(AT91C_SPI_CSR + 3) = AT91C_SPI_CPOL | (AT91C_SPI_DLYBS & DATAFLASH_TCSS) |\n\t                       (AT91C_SPI_DLYBCT & DATAFLASH_TCHS) |\n\t                       ((AT91C_MASTER_CLOCK / (2*AT91C_SPI_CLK)) << 8);\n}\n\n\n/*----------------------------------------------------------------------------*/\n/* \\fn    AT91F_SpiEnable                                                     */\n/* \\brief Enable SPI chip select                                              */\n/*----------------------------------------------------------------------------*/\nstatic void AT91F_SpiEnable(int cs) {\n\tswitch(cs) {\n\tcase 0:\t/* Configure SPI CS0 for Serial DataFlash AT45DBxx */\n\t\tAT91C_BASE_SPI->SPI_MR &= 0xFFF0FFFF;\n\t\tAT91C_BASE_SPI->SPI_MR |= ((AT91C_SPI_PCS0_SERIAL_DATAFLASH << 16) & AT91C_SPI_PCS);\n\t\tbreak;\n\tcase 3:\t/* Configure SPI CS3 for Serial DataFlash Card */\n\t\t/* Set up PIO SDC_TYPE to switch on DataFlash Card and not MMC/SDCard */\n\t\tAT91C_BASE_PIOB->PIO_PER = AT91C_PIO_PB7;\t/* Set in PIO mode */\n\t\tAT91C_BASE_PIOB->PIO_OER = AT91C_PIO_PB7;\t/* Configure in output */\n\t\t/* Clear Output */\n\t\tAT91C_BASE_PIOB->PIO_CODR = AT91C_PIO_PB7;\n\t\t/* Configure PCS */\n\t\tAT91C_BASE_SPI->SPI_MR &= 0xFFF0FFFF;\n\t\tAT91C_BASE_SPI->SPI_MR |= ((AT91C_SPI_PCS3_DATAFLASH_CARD<<16) & AT91C_SPI_PCS);\n\t\tbreak;\n\t}\n\n\t/* SPI_Enable */\n\tAT91C_BASE_SPI->SPI_CR = AT91C_SPI_SPIEN;\n}\n\n/*----------------------------------------------------------------------------*/\n/* \\fn    AT91F_SpiWrite                                                      */\n/* \\brief Set the PDC registers for a transfert                               */\n/*----------------------------------------------------------------------------*/\nstatic unsigned int AT91F_SpiWrite(AT91PS_DataflashDesc pDesc)\n{\n   \tunsigned int timeout;\n\t\n   \tAT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTDIS + AT91C_PDC_RXTDIS;\n\n   \t/* Initialize the Transmit and Receive Pointer */\n    \tAT91C_BASE_SPI->SPI_RPR = (unsigned int)pDesc->rx_cmd_pt ;\n    \tAT91C_BASE_SPI->SPI_TPR = (unsigned int)pDesc->tx_cmd_pt ;\n\n    \t/* Intialize the Transmit and Receive Counters */\n    \tAT91C_BASE_SPI->SPI_RCR = pDesc->rx_cmd_size;\n    \tAT91C_BASE_SPI->SPI_TCR = pDesc->tx_cmd_size;\n\n\tif ( pDesc->tx_data_size != 0 ) {\n\t   \t/* Initialize the Next Transmit and Next Receive Pointer */\n\t   \tAT91C_BASE_SPI->SPI_RNPR = (unsigned int)pDesc->rx_data_pt ;\n\t\tAT91C_BASE_SPI->SPI_TNPR = (unsigned int)pDesc->tx_data_pt ;\n\n\t\t/* Intialize the Next Transmit and Next Receive Counters */\n\t\tAT91C_BASE_SPI->SPI_RNCR = pDesc->rx_data_size ;\n\t \tAT91C_BASE_SPI->SPI_TNCR = pDesc->tx_data_size ;\n   \t}\n\n\t/* ARM simple, non interrupt dependent timer */\n\ttimeout = 0;\n\n\tAT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTEN + AT91C_PDC_RXTEN;\n\twhile(!(AT91C_BASE_SPI->SPI_SR & AT91C_SPI_RXBUFF));\n\n   \tAT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTDIS + AT91C_PDC_RXTDIS;\n\n\tif (timeout >= AT91C_DATAFLASH_TIMEOUT){\n\t\treturn AT91C_DATAFLASH_ERROR;\n\t}\n\n\treturn AT91C_DATAFLASH_OK;\n}\n\n\n/*----------------------------------------------------------------------*/\n/* \\fn    AT91F_DataFlashSendCommand\t\t\t\t\t*/\n/* \\brief Generic function to send a command to the dataflash\t\t*/\n/*----------------------------------------------------------------------*/\nstatic AT91S_DataFlashStatus AT91F_DataFlashSendCommand(\n\tAT91PS_DataFlash pDataFlash,\n\tunsigned char OpCode,\n\tunsigned int CmdSize,\n\tunsigned int DataflashAddress)\n{\n\tunsigned int adr;\n\n\t/* process the address to obtain page address and byte address */\n\tadr = ((DataflashAddress / (pDataFlash->pDevice->pages_size)) \n\t        << pDataFlash->pDevice->page_offset) +\n\t        (DataflashAddress % (pDataFlash->pDevice->pages_size));\n\n\t/* fill the  command  buffer */\n\tpDataFlash->pDataFlashDesc->command[0] = OpCode;\n\tif (pDataFlash->pDevice->pages_number >= 16384)\n\t{\n\t\tpDataFlash->pDataFlashDesc->command[1] = (unsigned char)((adr & 0x0F000000) >> 24);\n\t\tpDataFlash->pDataFlashDesc->command[2] = (unsigned char)((adr & 0x00FF0000) >> 16);\n\t\tpDataFlash->pDataFlashDesc->command[3] = (unsigned char)((adr & 0x0000FF00) >> 8);\n\t\tpDataFlash->pDataFlashDesc->command[4] = (unsigned char)(adr & 0x000000FF);\n\t}\n\telse\n\t{\t\n\t\tpDataFlash->pDataFlashDesc->command[1] = (unsigned char)((adr & 0x00FF0000) >> 16);\n\t\tpDataFlash->pDataFlashDesc->command[2] = (unsigned char)((adr & 0x0000FF00) >> 8);\n\t\tpDataFlash->pDataFlashDesc->command[3] = (unsigned char)(adr & 0x000000FF) ;\n\t\tpDataFlash->pDataFlashDesc->command[4] = 0;\n\t}\n\tpDataFlash->pDataFlashDesc->command[5] = 0;\n\tpDataFlash->pDataFlashDesc->command[6] = 0;\n\tpDataFlash->pDataFlashDesc->command[7] = 0;\n\n\t/* Initialize the SpiData structure for the spi write fuction */\n\tpDataFlash->pDataFlashDesc->tx_cmd_pt   =  pDataFlash->pDataFlashDesc->command ;\n\tpDataFlash->pDataFlashDesc->tx_cmd_size =  CmdSize ;\n\tpDataFlash->pDataFlashDesc->rx_cmd_pt   =  pDataFlash->pDataFlashDesc->command ;\n\tpDataFlash->pDataFlashDesc->rx_cmd_size =  CmdSize ;\n\n\treturn AT91F_SpiWrite(pDataFlash->pDataFlashDesc);\t\t\t\n}\n\n\n/*----------------------------------------------------------------------*/\n/* \\fn    AT91F_DataFlashGetStatus\t\t\t\t\t*/\n/* \\brief Read the status register of the dataflash\t\t\t*/\n/*----------------------------------------------------------------------*/\nstatic AT91S_DataFlashStatus AT91F_DataFlashGetStatus(AT91PS_DataflashDesc pDesc)\n{\n\tAT91S_DataFlashStatus status;\n\n\t/* first send the read status command (D7H) */\n\tpDesc->command[0] = DB_STATUS;\n\tpDesc->command[1] = 0;\n\n\tpDesc->DataFlash_state = GET_STATUS;\n    \tpDesc->tx_data_size    = 0 ; /* Transmit the command and receive response */\n    \tpDesc->tx_cmd_pt       = pDesc->command ;\n    \tpDesc->rx_cmd_pt       = pDesc->command ;\n    \tpDesc->rx_cmd_size     = 2 ;\n    \tpDesc->tx_cmd_size     = 2 ;\n    \tstatus = AT91F_SpiWrite (pDesc);\n\n\tpDesc->DataFlash_state = *( (unsigned char *) (pDesc->rx_cmd_pt) +1);\n\treturn status;\n}\n\n/*-----------------------------------------------------------------------------\n * Function Name       : AT91F_DataFlashWaitReady\n * Object              : wait for dataflash ready (bit7 of the status register == 1)\n * Input Parameters    : DataFlash Service and timeout\n * Return value        : DataFlash status \"ready or not\"\n *-----------------------------------------------------------------------------\n */\nstatic AT91S_DataFlashStatus AT91F_DataFlashWaitReady(\n\tAT91PS_DataflashDesc pDataFlashDesc,\n\tunsigned int timeout)\n{\n\tpDataFlashDesc->DataFlash_state = IDLE;\n        do {\n                AT91F_DataFlashGetStatus(pDataFlashDesc);\n                timeout--;\n        }\n        while(((pDataFlashDesc->DataFlash_state & 0x80) != 0x80) && (timeout > 0));\n\n        if((pDataFlashDesc->DataFlash_state & 0x80) != 0x80)\n                return AT91C_DATAFLASH_ERROR;\n\n        return AT91C_DATAFLASH_OK;\n}\n\n\n/*------------------------------------------------------------------------------*/\n/* Function Name       : AT91F_DataFlashContinuousRead                          */\n/* Object              : Continuous stream Read                                 */\n/* Input Parameters    : DataFlash Service                                      */\n/*                     : <src> = dataflash address                              */\n/*                     : <*dataBuffer> = data buffer pointer                    */\n/*                     : <sizeToRead> = data buffer size                        */\n/* Return value        : State of the dataflash                                 */\n/*------------------------------------------------------------------------------*/\nstatic AT91S_DataFlashStatus AT91F_DataFlashContinuousRead(\n \tAT91PS_DataFlash pDataFlash,\n\tint src,\n\tunsigned char *dataBuffer,\n\tint sizeToRead )\n{\n\tAT91S_DataFlashStatus status;\n\t/* Test the size to read in the device */\n\tif ( (src + sizeToRead) > (pDataFlash->pDevice->pages_size * (pDataFlash->pDevice->pages_number)))\n\t\treturn AT91C_DATAFLASH_MEMORY_OVERFLOW;\n\n\tpDataFlash->pDataFlashDesc->rx_data_pt = dataBuffer;\n\tpDataFlash->pDataFlashDesc->rx_data_size = sizeToRead;\n\tpDataFlash->pDataFlashDesc->tx_data_pt = dataBuffer;\n\tpDataFlash->pDataFlashDesc->tx_data_size = sizeToRead;\n\t\n\tstatus = AT91F_DataFlashSendCommand(pDataFlash, DB_CONTINUOUS_ARRAY_READ, 8, src);\n\t/* Send the command to the dataflash */\n\treturn(status);\n}\n\n\n\n/*------------------------------------------------------------------------------*/\n/* Function Name       : AT91F_MainMemoryToBufferTransfer                       */\n/* Object              : Read a page in the SRAM Buffer 1 or 2                  */\n/* Input Parameters    : DataFlash Service                                      */\n/*                     : Page concerned                                         */\n/*                     :                                                        */\n/* Return value        : State of the dataflash                                 */\n/*------------------------------------------------------------------------------*/\nstatic AT91S_DataFlashStatus AT91F_MainMemoryToBufferTransfer(\n\tAT91PS_DataFlash pDataFlash,\n\tunsigned char BufferCommand,\n\tunsigned int page)\n{\n\tint cmdsize;\n\t/* Test if the buffer command is legal */\n\tif ((BufferCommand != DB_PAGE_2_BUF1_TRF) && (BufferCommand != DB_PAGE_2_BUF2_TRF))\n\t\treturn AT91C_DATAFLASH_BAD_COMMAND;\n\n\t/* no data to transmit or receive */\n    \tpDataFlash->pDataFlashDesc->tx_data_size = 0;\n\tcmdsize = 4;\n\tif (pDataFlash->pDevice->pages_number >= 16384)\n\t\tcmdsize = 5;\n\treturn(AT91F_DataFlashSendCommand(pDataFlash, BufferCommand, cmdsize,\n\t                                  page*pDataFlash->pDevice->pages_size));\n}\n\n\n\n/*----------------------------------------------------------------------------- */\n/* Function Name       : AT91F_DataFlashWriteBuffer                             */\n/* Object              : Write data to the internal sram buffer 1 or 2          */\n/* Input Parameters    : DataFlash Service                                      */\n/*                     : <BufferCommand> = command to write buffer1 or buffer2  */\n/*                     : <*dataBuffer> = data buffer to write                   */\n/*                     : <bufferAddress> = address in the internal buffer       */\n/*                     : <SizeToWrite> = data buffer size                       */\n/* Return value        : State of the dataflash                                 */\n/*------------------------------------------------------------------------------*/\nstatic AT91S_DataFlashStatus AT91F_DataFlashWriteBuffer(\n\tAT91PS_DataFlash pDataFlash,\n\tunsigned char BufferCommand,\n\tunsigned char *dataBuffer,\n\tunsigned int bufferAddress,\n\tint SizeToWrite )\n{\n\tint cmdsize;\n\t/* Test if the buffer command is legal */\n\tif ((BufferCommand != DB_BUF1_WRITE) && (BufferCommand != DB_BUF2_WRITE))\n\t\treturn AT91C_DATAFLASH_BAD_COMMAND;\n\n\t/* buffer address must be lower than page size */\n\tif (bufferAddress > pDataFlash->pDevice->pages_size)\n\t\treturn AT91C_DATAFLASH_BAD_ADDRESS;\n\n    \t/* Send first Write Command */\n\tpDataFlash->pDataFlashDesc->command[0] = BufferCommand;\n\tpDataFlash->pDataFlashDesc->command[1] = 0;\n\tif (pDataFlash->pDevice->pages_number >= 16384)\n\t{\n\t   \tpDataFlash->pDataFlashDesc->command[2] = 0;\n\t   \tpDataFlash->pDataFlashDesc->command[3] = (unsigned char)(((unsigned int)(bufferAddress &  pDataFlash->pDevice->byte_mask)) >> 8) ;\n\t   \tpDataFlash->pDataFlashDesc->command[4] = (unsigned char)((unsigned int)bufferAddress  & 0x00FF) ;\n\t\tcmdsize = 5;\n\t}\n\telse\n\t{\n\t   \tpDataFlash->pDataFlashDesc->command[2] = (unsigned char)(((unsigned int)(bufferAddress &  pDataFlash->pDevice->byte_mask)) >> 8) ;\n\t   \tpDataFlash->pDataFlashDesc->command[3] = (unsigned char)((unsigned int)bufferAddress  & 0x00FF) ;\n\t   \tpDataFlash->pDataFlashDesc->command[4] = 0;\n\t\tcmdsize = 4;\n\t}\n\t\t\n\tpDataFlash->pDataFlashDesc->tx_cmd_pt \t = pDataFlash->pDataFlashDesc->command ;\n\tpDataFlash->pDataFlashDesc->tx_cmd_size  = cmdsize ;\n\tpDataFlash->pDataFlashDesc->rx_cmd_pt \t = pDataFlash->pDataFlashDesc->command ;\n\tpDataFlash->pDataFlashDesc->rx_cmd_size  = cmdsize ;\n\n\tpDataFlash->pDataFlashDesc->rx_data_pt \t = dataBuffer ;\n\tpDataFlash->pDataFlashDesc->tx_data_pt \t = dataBuffer ;\n\tpDataFlash->pDataFlashDesc->rx_data_size = SizeToWrite ;\n\tpDataFlash->pDataFlashDesc->tx_data_size = SizeToWrite ;\n\n\treturn AT91F_SpiWrite(pDataFlash->pDataFlashDesc);\n}\n\n\n/*------------------------------------------------------------------------------*/\n/* Function Name       : AT91F_PageErase                                        */             \n/* Object              : Read a page in the SRAM Buffer 1 or 2                  */\n/* Input Parameters    : DataFlash Service                                      */\n/*                     : Page concerned                                         */\n/*                     :                                                        */\n/* Return value        : State of the dataflash                                 */\n/*------------------------------------------------------------------------------*/\nstatic AT91S_DataFlashStatus AT91F_PageErase(\n\tAT91PS_DataFlash pDataFlash,\n\tunsigned int page)\n{\n\tint cmdsize;\n\t/* Test if the buffer command is legal */\t\n\t/* no data to transmit or receive */\n    \tpDataFlash->pDataFlashDesc->tx_data_size = 0;\n\t\n\tcmdsize = 4;\n\tif (pDataFlash->pDevice->pages_number >= 16384)\n\t\tcmdsize = 5;\n\treturn(AT91F_DataFlashSendCommand(pDataFlash, DB_PAGE_ERASE, cmdsize,\n\t                                  page*pDataFlash->pDevice->pages_size));\n}\n\n\n/*------------------------------------------------------------------------------*/\n/* Function Name       : AT91F_WriteBufferToMain                                */\n/* Object              : Write buffer to the main memory                        */\n/* Input Parameters    : DataFlash Service                                      */\n/*                     : <BufferCommand> = command to send to buf1 or buf2      */\n/*                     : <dest> = main memory address                           */\n/* Return value        : State of the dataflash                                 */\n/*------------------------------------------------------------------------------*/\nstatic AT91S_DataFlashStatus AT91F_WriteBufferToMain (\n\tAT91PS_DataFlash pDataFlash,\n\tunsigned char BufferCommand,\n\tunsigned int dest )\n{\n\tint cmdsize;\n\t/* Test if the buffer command is correct */\n\tif ((BufferCommand != DB_BUF1_PAGE_PGM) &&\n\t    (BufferCommand != DB_BUF1_PAGE_ERASE_PGM) &&\n\t    (BufferCommand != DB_BUF2_PAGE_PGM) &&\n\t    (BufferCommand != DB_BUF2_PAGE_ERASE_PGM) )\n\t\treturn AT91C_DATAFLASH_BAD_COMMAND;\n\n\t/* no data to transmit or receive */\n\tpDataFlash->pDataFlashDesc->tx_data_size = 0;\n\n\tcmdsize = 4;\n\tif (pDataFlash->pDevice->pages_number >= 16384)\n\t\tcmdsize = 5;\n\t/* Send the command to the dataflash */\n\treturn(AT91F_DataFlashSendCommand (pDataFlash, BufferCommand, cmdsize, dest));\n}\n\n\n/*------------------------------------------------------------------------------*/\n/* Function Name       : AT91F_PartialPageWrite                                 */\n/* Object              : Erase partially a page                                 */\n/* Input Parameters    : <page> = page number                                   */\n/*                     : <AdrInpage> = adr to begin the fading                  */\n/*                     : <length> = Number of bytes to erase                    */\n/*------------------------------------------------------------------------------*/\nstatic AT91S_DataFlashStatus AT91F_PartialPageWrite (\n\tAT91PS_DataFlash pDataFlash,\n\tunsigned char *src,\n\tunsigned int dest,\n\tunsigned int size)\n{\n\tunsigned int page;\n\tunsigned int AdrInPage;\n\n\tpage = dest / (pDataFlash->pDevice->pages_size);\n\tAdrInPage = dest % (pDataFlash->pDevice->pages_size);\n\n\t/* Read the contents of the page in the Sram Buffer */\n\tAT91F_MainMemoryToBufferTransfer(pDataFlash, DB_PAGE_2_BUF1_TRF, page);\n\tAT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_DATAFLASH_TIMEOUT);\n\t\n\t/*Update the SRAM buffer */\n\tAT91F_DataFlashWriteBuffer(pDataFlash, DB_BUF1_WRITE, src, AdrInPage, size);\n\tAT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_DATAFLASH_TIMEOUT);\n\t\n\t/* Erase page if a 128 Mbits device */\n\tif (pDataFlash->pDevice->pages_number >= 16384)\n\t{\n\t\tAT91F_PageErase(pDataFlash, page);\n\t\tAT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_DATAFLASH_TIMEOUT);\n\t}\n\n\t/* Rewrite the modified Sram Buffer in the main memory */\n\treturn(AT91F_WriteBufferToMain(pDataFlash, DB_BUF1_PAGE_ERASE_PGM,\n\t                               (page*pDataFlash->pDevice->pages_size)));\n}\n\n\n/*------------------------------------------------------------------------------*/\n/* Function Name       : AT91F_DataFlashWrite                                   */\n/* Object              :                                                        */\n/* Input Parameters    : <*src> = Source buffer                                 */\n/*                     : <dest> = dataflash adress                              */\n/*                     : <size> = data buffer size                              */\n/*------------------------------------------------------------------------------*/\nAT91S_DataFlashStatus AT91F_DataFlashWrite(\n\tAT91PS_DataFlash pDataFlash,\n\tunsigned char *src,\n\tint dest,\n\tint size )\n{\n\tunsigned int length;\n\tunsigned int page;\n\tunsigned int status;\n\n\tAT91F_SpiEnable(pDataFlash->pDevice->cs);\n\n\tif ( (dest + size) > (pDataFlash->pDevice->pages_size * (pDataFlash->pDevice->pages_number)))\n\t\treturn AT91C_DATAFLASH_MEMORY_OVERFLOW;\n\n    \t/* If destination does not fit a page start address */\n\tif ((dest % ((unsigned int)(pDataFlash->pDevice->pages_size)))  != 0 ) {\n\t\tlength = pDataFlash->pDevice->pages_size - (dest % ((unsigned int)(pDataFlash->pDevice->pages_size)));\n\n\t\tif (size < length)\n\t\t\tlength = size;\n\n\t\tif(!AT91F_PartialPageWrite(pDataFlash,src, dest, length))\n\t\t\treturn AT91C_DATAFLASH_ERROR;\n\n\t\tAT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_DATAFLASH_TIMEOUT);\n\n\t\t/* Update size, source and destination pointers */\n        \tsize -= length;\n        \tdest += length;\n        \tsrc += length;\n\t}\n\n\twhile (( size - pDataFlash->pDevice->pages_size ) >= 0 ) \n\t{\n\t\t/* program dataflash page */\t\t\n\t\tpage = (unsigned int)dest / (pDataFlash->pDevice->pages_size);\n\n\t\tstatus = AT91F_DataFlashWriteBuffer(pDataFlash, DB_BUF1_WRITE, src,\n\t\t                                    0, pDataFlash->pDevice->pages_size);\n\t\tAT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_DATAFLASH_TIMEOUT);\n\t\n\t\tstatus = AT91F_PageErase(pDataFlash, page);\n\t\tAT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_DATAFLASH_TIMEOUT);\n\t\tif (!status)\n\t\t\treturn AT91C_DATAFLASH_ERROR;\n\t\t\n\t\tstatus = AT91F_WriteBufferToMain (pDataFlash, DB_BUF1_PAGE_PGM, dest);\n\t\tif(!status)\n\t\t\treturn AT91C_DATAFLASH_ERROR;\n\n\t\tAT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_DATAFLASH_TIMEOUT);\n\t\n\t\t/* Update size, source and destination pointers */\n\t   \tsize -= pDataFlash->pDevice->pages_size ;\n\t   \tdest += pDataFlash->pDevice->pages_size ;\n\t   \tsrc  += pDataFlash->pDevice->pages_size ;\n\t}\n\n\t/* If still some bytes to read */\n\tif ( size > 0 ) {\n\t\t/* program dataflash page */\n\t\tif(!AT91F_PartialPageWrite(pDataFlash, src, dest, size) )\n\t\t\treturn AT91C_DATAFLASH_ERROR;\n\t\tAT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_DATAFLASH_TIMEOUT);\n\t}\n\treturn AT91C_DATAFLASH_OK;\n}\n\n\n/*------------------------------------------------------------------------------*/\n/* Function Name       : AT91F_DataFlashRead                                    */\n/* Object              : Read a block in dataflash                              */\n/* Input Parameters    :                                                        */\n/* Return value        :                                                        */\n/*------------------------------------------------------------------------------*/\nint AT91F_DataFlashRead(\n\tAT91PS_DataFlash pDataFlash,\n\tunsigned long addr,\n\tunsigned long size,\n\tchar *buffer)\n{\n\tunsigned long SizeToRead;\n\n\tAT91F_SpiEnable(pDataFlash->pDevice->cs);\n\n\tif(AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_DATAFLASH_TIMEOUT) != AT91C_DATAFLASH_OK)\n\t\treturn -1;\n\n\twhile (size)\n\t{\n\t\tSizeToRead = (size < 0x8000)? size:0x8000;\n\n\t\tif (AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_DATAFLASH_TIMEOUT)\n\t\t    != AT91C_DATAFLASH_OK)\n\t\t\treturn -1;\n\n\t\tif (AT91F_DataFlashContinuousRead (pDataFlash, addr, (unsigned char *)buffer,\n\t\t                                   SizeToRead) != AT91C_DATAFLASH_OK)\n\t\t\treturn -1;\n\n\t\tsize -= SizeToRead;\n\t\taddr += SizeToRead;\n\t\tbuffer += SizeToRead;\n\t}\n\n   \treturn AT91C_DATAFLASH_OK;\n}\n\n\n/*------------------------------------------------------------------------------*/\n/* Function Name       : AT91F_DataflashProbe                                   */\n/* Object              :                                                        */\n/* Input Parameters    :                                                        */\n/* Return value\t       : Dataflash status register                              */\n/*------------------------------------------------------------------------------*/\nint AT91F_DataflashProbe(int cs, AT91PS_DataflashDesc pDesc)\n{\n\tAT91F_SpiEnable(cs);\n   \tAT91F_DataFlashGetStatus(pDesc);\n   \treturn ((pDesc->command[1] == 0xFF)? 0: (pDesc->command[1] & 0x3C));\n}\n\n/*------------------------------------------------------------------------------*/\n/* Function Name       : AT91F_DataFlashErase                                   */\n/* Object              :                                                        */\n/* Input Parameters    : <*pDataFlash> = Device info                            */\n/*------------------------------------------------------------------------------*/\nAT91S_DataFlashStatus AT91F_DataFlashErase(AT91PS_DataFlash pDataFlash)\n{\n\tunsigned int page;\n\tunsigned int status;\n\n\tAT91F_SpiEnable(pDataFlash->pDevice->cs);\n \n \tfor(page=0; page < pDataFlash->pDevice->pages_number; page++)\n\t    {\n\t\t/* Erase dataflash page */\n\t\tif ((page & 0x00FF) == 0)\n\t\t\tprintf(\"\\rERA %d/%d\", page, pDataFlash->pDevice->pages_number);\n\t\tstatus = AT91F_PageErase(pDataFlash, page);\n\t\tAT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_DATAFLASH_TIMEOUT);\n\t\tif (!status)\n\t\t\treturn AT91C_DATAFLASH_ERROR;\n   \t}\n\n\treturn AT91C_DATAFLASH_OK;\n}\n\n"
  },
  {
    "path": "target/linux/at91/image/dfboot/src/com.c",
    "content": "/*----------------------------------------------------------------------------\n *         ATMEL Microcontroller Software Support  -  ROUSSET  -\n *----------------------------------------------------------------------------\n * The software is delivered \"AS IS\" without warranty or condition of any\n * kind, either express, implied or statutory. This includes without\n * limitation any warranty or condition with respect to merchantability or\n * fitness for any particular purpose, or against the infringements of\n * intellectual property rights of others.\n *----------------------------------------------------------------------------\n * File Name           : com.c\n * Object              : \n * Creation            : HIi   03/27/2003\n *\n *----------------------------------------------------------------------------\n */\n#include \"AT91RM9200.h\"\n#include \"lib_AT91RM9200.h\"\n#include \"config.h\"\n#include \"com.h\"\n#include \"stdio.h\"\n\nstatic char erase_seq[] = \"\\b \\b\";\t\t/* erase sequence\t*/\n\n#define MAX_UARTS 1\n\n//unsigned int usa[2] = {(unsigned int)AT91C_BASE_DBGU, (unsigned int)AT91C_ALTERNATE_USART};\nunsigned int usa[1] = {(unsigned int)AT91C_BASE_DBGU};\nunsigned int us;\nint port_detected;\n\nvoid at91_init_uarts(void)\n{\n\tint i;\n\n\tport_detected = 0;\n\tAT91F_DBGU_CfgPIO();\n\tAT91F_US0_CfgPIO();\n\tAT91F_US0_CfgPMC();\n\n\tfor(i=0; i<MAX_UARTS; i++) {\n\t\tus = usa[i];\n\t\tAT91F_US_ResetRx((AT91PS_USART)us);\n\t\tAT91F_US_ResetTx((AT91PS_USART)us);\n\n\t\t// Configure DBGU\n\t\tAT91F_US_Configure(\n\t\t\t(AT91PS_USART)us, // DBGU base address\n\t\t\tAT91C_MASTER_CLOCK,            // 60 MHz\n\t\t\tAT91C_US_ASYNC_MODE,           // mode Register to be programmed\n\t\t\t115200,                        // baudrate to be programmed\n\t\t\t0                              // timeguard to be programmed\n\t\t\t);\n\n\t\t// Enable Transmitter\n\t\tAT91F_US_EnableTx((AT91PS_USART)us);\n\t\t// Enable Receiver\n\t\tAT91F_US_EnableRx((AT91PS_USART)us);\n\t}\n\tus = usa[0];\n}\n\nint at91_serial_putc(int ch)\n{\n\tif (ch == '\\n')\n\t\tat91_serial_putc('\\r');\n\twhile (!AT91F_US_TxReady((AT91PS_USART)us));\n\tAT91F_US_PutChar((AT91PS_USART)us, (char)ch);\n\treturn ch;\n}\n\n/* This getc is modified to be able work on more than one port. On certain\n * boards (i.e. Figment Designs VersaLink), the debug port is not available\n * once the unit is in it's enclosure, so, if one needs to get into dfboot\n * for any reason it is impossible. With this getc, it scans between the debug\n * port and another port and once it receives a character, it sets that port\n * as the debug port. */\nint at91_serial_getc()\n{\n\twhile(1) {\n#if 0\n\t\tif (!port_detected) {\n\t\t\tif (us == usa[0]) {\n\t\t\t\tus = usa[1];\n\t\t\t}\n\t\t\telse {\n\t\t\t\tus = usa[0];\n\t\t\t}\n\t\t}\n#endif\n\t\tif(AT91F_US_RxReady((AT91PS_USART)us)) {\n#if 0\n\t\t\tport_detected = 1;\n#endif\n\t\t\treturn((int)AT91F_US_GetChar((AT91PS_USART)us));\n\t\t}\n\t}\n}\n\n/*-----------------------------------------------------------------------------\n * Function Name       : AT91F_ReadLine()\n * Object              : \n * Input Parameters    : \n * Return value\t\t: \n *-----------------------------------------------------------------------------\n */\nint AT91F_ReadLine (const char *const prompt, char *console_buffer)\n{\n\tchar *p = console_buffer;\n\tint\tn = 0;\t\t\t\t\t/* buffer index\t\t*/\n\tint\tplen = strlen (prompt);\t/* prompt length\t*/\n\tint\tcol;\t\t\t\t\t/* output column cnt\t*/\n\tchar\tc;\n\n\t/* print prompt */\n\tif (prompt)\n\t\tprintf(prompt);\n\tcol = plen;\n\n\tfor (;;) {\n\t\tc = getc();\n\n\t\tswitch (c) {\n\t\t\tcase '\\r':\t\t\t\t/* Enter\t\t*/\n\t\t\tcase '\\n':\n\t\t\t\t*p = '\\0';\n\t\t\t\tputs (\"\\n\");\n\t\t\t\treturn (p - console_buffer);\n\n\t\t\tcase 0x03:\t\t\t\t/* ^C - break\t*/\n\t\t\t\tconsole_buffer[0] = '\\0';\t/* discard input */\n\t\t\t\treturn (-1);\n\n\t\t\tcase 0x08:\t\t\t\t/* ^H  - backspace\t*/\n\t\t\tcase 0x7F:\t\t\t\t/* DEL - backspace\t*/\n\t\t\t\tif (n) {\n\t\t\t\t\t--p;\n\t\t\t\t\tprintf(erase_seq);\n\t\t\t\t\tcol--;\n\t\t\t\t\tn--;\n\t\t\t\t\t}\n\t\t\t\tcontinue;\n\n\t\t\tdefault:\n\t\t\t/*\n\t\t\t * Must be a normal character then\n\t\t\t */\n\t\t\tif (n < (AT91C_CB_SIZE -2)) \n\t\t\t{\n\t\t\t\t++col;\t\t/* echo input\t\t*/\n\t\t\t\tputc(c);\n\t\t\t\t*p++ = c;\n\t\t\t\t++n;\n\t\t\t} \n\t\t\telse \n\t\t\t{\t\t\t/* Buffer full\t\t*/\n\t\t\t\tputc('\\a');\n\t\t\t}\n\t\t}\n\t}\n}\n\n\n/*-----------------------------------------------------------------------------\n * Function Name       : AT91F_WaitKeyPressed()\n * Object              : \n * Input Parameters    : \n * Return value\t\t: \n *-----------------------------------------------------------------------------\n */\nvoid AT91F_WaitKeyPressed(void)\n{\n\tint c;\n    \tputs(\"KEY\");\n\t\tc = getc();\n\tputc('\\n');\n}\n\nint puts(const char *str)\n{\n  while(*str != 0) {\n\t\tat91_serial_putc(*str);\n\t\tstr++;\n\t\t}\n\treturn 1;\n}\n\nint putc(int c)\n{\n  return at91_serial_putc(c);\n}\n\nint putchar(c)\n{\n\treturn putc(c);\n}\n\nint getc()\n{\n  return at91_serial_getc();\n}\n\nint strlen(const char *str)\n{\n  int len = 0;\n\n  if(str == (char *)0)\n    return 0;\n\n  while(*str++ != 0)\n    len++;\n\n  return len;\n}\n\n#define ZEROPAD 1               /* pad with zero */\n#define SIGN    2               /* unsigned/signed long */\n#define LEFT    4              /* left justified */\n#define LARGE   8              /* use 'ABCDEF' instead of 'abcdef' */\n\n#define do_div(n,base) ({ \\\n        int __res; \\\n        __res = ((unsigned) n) % (unsigned) base; \\\n        n = ((unsigned) n) / (unsigned) base; \\\n        __res; \\\n})\n\nstatic int number(int num, int base, int size,\n                  int precision, int type)\n{\n  char c, sign, tmp[66];\n  const char *digits=\"0123456789ABCDEF\";\n  int i;\n\n  if (type & LEFT)\n    type &= ~ZEROPAD;\n  if (base < 2 || base > 16)\n    return 0;\n  c = (type & ZEROPAD) ? '0' : ' ';\n  sign = 0;\n\n  if(type & SIGN && num < 0)\n    {\n      sign = '-';\n      num = -num;\n      size--;\n    }\n  \n  i = 0;\n  if(num == 0)\n    tmp[i++] = digits[0];\n  else while(num != 0)\n    tmp[i++] = digits[do_div(num, base)];\n\n  if(i > precision)\n    precision = i;\n  size -= precision;\n  \n  if(!(type&(ZEROPAD+LEFT)))\n    while(size-->0)\n      putc(' ');\n  \n  if(sign)\n    putc(sign);\n\n  if (!(type & LEFT))\n    while (size-- > 0)\n      putc(c);\n\n  while (i < precision--)\n    putc('0');\n  \n  while (i-- > 0)\n    putc(tmp[i]);\n\n  while (size-- > 0)\n    putc(' ');;\n\n  return 1;\n}\n\nint hvfprintf(const char *fmt, va_list va)\n{\n  char *s;\n\n\tdo {\n\t\tif(*fmt == '%')\t{\n\t\t\tbool done = false;\n\n\t\t\tint type = 0;\n\t\t\tint precision = 0;\n\n\t\t\tdo {\n\t\t\t\tfmt++;\n\t\t\t\tswitch(*fmt) {\n\t\t\t\tcase '0' :\n\t\t\t\t\tif(!precision)\n\t\t\t\t\t\ttype |= ZEROPAD;\n\t\t\t\tcase '1' :\n\t\t\t\tcase '2' :\n\t\t\t\tcase '3' :\n\t\t\t\tcase '4' :\n\t\t\t\tcase '5' :\n\t\t\t\tcase '6' :\n\t\t\t\tcase '7' :\n\t\t\t\tcase '8' :\n\t\t\t\tcase '9' :\n\t\t\t\t\tprecision = precision * 10 + (*fmt - '0');\n\t\t\t\t\tbreak;\n\t\t\t\tcase '.' :\n\t\t\t\t\tbreak;\n\t\t\t\tcase 's' :\n\t\t\t\t\ts = va_arg(va, char *);\n\t\t\t\t\tif(!s)\n\t\t\t\t\t\tputs(\"<NULL>\");\n\t\t\t\t\telse\n\t\t\t\t\t\tputs(s);\n\t\t\t\t\tdone = true;\n\t\t\t\t\tbreak;\n\t\t\t\tcase 'c' :\n\t\t\t\t\tputc(va_arg(va, int));\n\t\t\t\t\tdone = true;\n\t\t\t\t\tbreak;\n\t\t\t\tcase 'd' :\n\t\t\t\t\tnumber(va_arg(va, int), 10, 0, precision, type);\n\t\t\t\t\tdone = true;\n\t\t\t\t\tbreak;\n\t\t\t\tcase 'x' :\n\t\t\t\tcase 'X' :\n\t\t\t\t\tnumber(va_arg(va, int), 16, 0, precision, type);\n\t\t\t\t\tdone = true;\n\t\t\t\t\tbreak;\n\t\t\t\tcase '%' :\n\t\t\t\t\tputc(*fmt);\n\t\t\t\t\tdone = true;\n\t\t\t\tdefault: \n\t\t\t\t\tputc('%');\n\t\t\t\t\tputc(*fmt);\n\t\t\t\t\tdone = true;\n\t\t\t\t\tbreak;\n\t\t\t\t} \n\t\t\t} while(!done);\n\t\t} else if(*fmt == '\\\\') {\n\t\t\tfmt++;\n\t\t\tif(*fmt == 'r') {\n\t\t\t\tputc('\\r');\n\t\t\t} else if(*fmt == 'n') { \n\t\t\t\tputc('\\n');\n\t\t\t}\n        \t} else {\n         \t\tputc(*fmt);\n        \t}\n\t\tfmt++;\n\t} while(*fmt != 0);\n  \n  return 0;\n}\n\nint printf(const char *fmt, ...)\n{\n  va_list ap;\n  int i;\n\n  va_start(ap, fmt);\n  i = hvfprintf(fmt, ap);\n  va_end(ap);\n\n  return i;\n}\n"
  },
  {
    "path": "target/linux/at91/image/dfboot/src/com.h",
    "content": "/*----------------------------------------------------------------------------\n *      ATMEL Microcontroller Software Support  -  ROUSSET  -\n *----------------------------------------------------------------------------\n * The software is delivered \"AS IS\" without warranty or condition of any\n * kind, either express, implied or statutory. This includes without\n * limitation any warranty or condition with respect to merchantability or\n * fitness for any particular purpose, or against the infringements of\n * intellectual property rights of others.\n *----------------------------------------------------------------------------\n * File Name           : com.h\n * Object              : \n *\n * 1.0 27/03/03 HIi    : Creation\n *----------------------------------------------------------------------------\n */\n#ifndef com_h\n#define com_h\n\n#define AT91C_CB_SIZE 20 /* size of the console buffer */\n\n/* Escape sequences */\n#define ESC \\033\n\nextern int AT91F_ReadLine (const char *const prompt, char *console_buffer);\nextern void AT91F_WaitKeyPressed(void);\n\n#endif\n\n"
  },
  {
    "path": "target/linux/at91/image/dfboot/src/config.h",
    "content": "\n#ifndef _CONFIG_H\n#define _CONFIG_H\n\n//#define\tPAGESZ_1056\t\t\t1\n#undef PAGESZ_1056\n#define\tSPI_LOW_SPEED\t\t\t1\n#define AT91C_DELAY_TO_BOOT \t\t1500\n\n#define\tCRC_RETRIES\t\t\t0x100\n\n#define AT91C_MASTER_CLOCK              59904000\n#define AT91C_BAUD_RATE                 115200\n\n#define AT91C_ALTERNATE_USART\tAT91C_BASE_US0\n\n#endif\n"
  },
  {
    "path": "target/linux/at91/image/dfboot/src/cstartup_ram.S",
    "content": "#include \"AT91RM9200_inc.h\"\n\t\t\n/*---------------------------\nARM Core Mode and Status Bits\n---------------------------*/\n.section start\n\t.text\n\t\t\t\n#define ARM_MODE_USER   0x10\n#define ARM_MODE_FIQ    0x11\n#define ARM_MODE_IRQ    0x12\n#define ARM_MODE_SVC    0x13\n#define ARM_MODE_ABORT  0x17\n#define ARM_MODE_UNDEF  0x1B\n#define ARM_MODE_SYS    0x1F\n\n#define I_BIT           0x80\n#define F_BIT           0x40\n#define T_BIT           0x20\n\n/*----------------------------------------------------------------------------\n Area Definition\n----------------\n Must be defined as function to put first in the code as it must be mapped\n at offset 0 of the flash EBI_CSR0, ie. at address 0 before remap.\n_---------------------------------------------------------------------------*/\n\n  .align  4\n\t.globl _start\n_start:\n\n/*----------------------------------------------------------------------------\n Exception vectors ( before Remap )\n------------------------------------\n These vectors are read at address 0.\n They absolutely requires to be in relative addresssing mode in order to\n guarantee a valid jump. For the moment, all are just looping (what may be\n dangerous in a final system). If an exception occurs before remap, this\n would result in an infinite loop.\n----------------------------------------------------------------------------*/\n                b           reset\t\t\t       \t/* reset */\n                b           undefvec        \t/* Undefined Instruction */\n                b           swivec          \t/* Software Interrupt */\n                b           pabtvec         \t/* Prefetch Abort */\n                b           dabtvec         \t/* Data Abort */\n                b           rsvdvec         \t/* reserved */\n                b           aicvec\t\t\t\t    /* IRQ : read the AIC */\n                b           fiqvec          \t/* FIQ */\n\nundefvec:\nswivec:\npabtvec:\ndabtvec:\nrsvdvec:\naicvec:\nfiqvec:\n\tb\tundefvec\n\nreset:\n\n#define MEMEND 0x00004000\n\n/* ----------------------------\n Setup the stack for each mode\n---------------------------- */\n\n#define IRQ_STACK_SIZE  0x10\n#define FIQ_STACK_SIZE  0x04\n#define ABT_STACK_SIZE  0x04\n#define UND_STACK_SIZE  0x04\n#define SVC_STACK_SIZE  0x10\n#define USER_STACK_SIZE 0x400\n\t\n                ldr     r0,= MEMEND\n\n/*- Set up Supervisor Mode and set Supervisor Mode Stack*/\n                msr     CPSR_c, #ARM_MODE_SVC | I_BIT | F_BIT\n                mov     r13, r0                     /* Init stack Undef*/\n                sub     r0, r0, #SVC_STACK_SIZE\n\n/*- Set up Interrupt Mode and set IRQ Mode Stack*/\n                msr     CPSR_c, #ARM_MODE_IRQ | I_BIT | F_BIT\n                mov     r13, r0                     /* Init stack IRQ*/\n                sub     r0, r0, #IRQ_STACK_SIZE\n\n/*- Set up Fast Interrupt Mode and set FIQ Mode Stack*/\n                msr     CPSR_c, #ARM_MODE_FIQ | I_BIT | F_BIT\n                mov     r13, r0                     /* Init stack FIQ*/\n                sub     r0, r0, #FIQ_STACK_SIZE\n\n/*- Set up Abort Mode and set Abort Mode Stack*/\n                msr     CPSR_c, #ARM_MODE_ABORT | I_BIT | F_BIT\n                mov     r13, r0                     /* Init stack Abort*/\n                sub     r0, r0, #ABT_STACK_SIZE\n\n/*- Set up Undefined Instruction Mode and set Undef Mode Stack*/\n                msr     CPSR_c, #ARM_MODE_UNDEF | I_BIT | F_BIT\n                mov     r13, r0                     /* Init stack Undef*/\n                sub     r0, r0, #UND_STACK_SIZE\n\n/*- Set up user Mode and set System Mode Stack*/\n                msr     CPSR_c, #ARM_MODE_SYS | I_BIT | F_BIT\n                bic     r0, r0, #3                  /* Insure word alignement */\n               \tmov     sp, r0                      /* Init stack System */\n\n\n\t\tldr       r0, = AT91F_LowLevelInit\n\t\tmov       lr, pc\n\t\tbx        r0\n\n/*----------------------------------------\n Read/modify/write CP15 control register\n----------------------------------------*/\n\t\tmrc     p15, 0, r0, c1, c0,0  /* read cp15 control registre (cp15 r1) in r0 */\n\t\tldr     r3,= 0xC0000080      /* Reset bit :Little Endian end fast bus mode */\n\t\tldr     r4,= 0xC0001000      /* Set bit :Asynchronous clock mode, Not Fast Bus, I-Cache enable */\n\t\tbic     r0, r0, r3\n\t\torr     r0, r0, r4\n\t\tmcr     p15, 0, r0, c1, c0,0 /* write r0 in cp15 control registre (cp15 r1) */\n\n/* Enable interrupts */\n\t\tmsr     CPSR_c, #ARM_MODE_SYS | F_BIT\n\n/*------------------------------------------------------------------------------\n- Branch on C code Main function (with interworking)\n----------------------------------------------------\n- Branch must be performed by an interworking call as either an ARM or Thumb\n- _start function must be supported. This makes the code not position-\n- independent. A Branch with link would generate errors\n----------------------------------------------------------------------------*/\n\t\n/*- Branch to _start by interworking*/\n\t\tldr     r4, = main\n\t        mov     lr, pc\n\t        bx      r4\n\t\n/*-----------------------------------------------------------------------------\n- Loop for ever\n---------------\n- End of application. Normally, never occur.\n- Could jump on Software Reset ( B 0x0 ).\n------------------------------------------------------------------------------*/\nEnd:\n\t        b       End\n"
  },
  {
    "path": "target/linux/at91/image/dfboot/src/dataflash.c",
    "content": "/*----------------------------------------------------------------------------\n *         ATMEL Microcontroller Software Support  -  ROUSSET  -\n *----------------------------------------------------------------------------\n * The software is delivered \"AS IS\" without warranty or condition of any\n * kind, either express, implied or statutory. This includes without\n * limitation any warranty or condition with respect to merchantability or\n * fitness for any particular purpose, or against the infringements of\n * intellectual property rights of others.\n *----------------------------------------------------------------------------\n * File Name           : dataflash.c\n * Object              : High level functions for the dataflash\n * Creation            : HIi   10/10/2003\n *----------------------------------------------------------------------------\n */\n#include \"config.h\"\n#include \"stdio.h\"\n#include \"dataflash.h\"\n\n\nAT91S_DATAFLASH_INFO dataflash_info[CFG_MAX_DATAFLASH_BANKS];\nstatic AT91S_DataFlash DataFlashInst;\n\nint cs[][CFG_MAX_DATAFLASH_BANKS] = {\n\t{CFG_DATAFLASH_LOGIC_ADDR_CS0, 0},\t/* Logical adress, CS */\n\t{CFG_DATAFLASH_LOGIC_ADDR_CS3, 3}\n};\n\nint AT91F_DataflashInit(void)\n{\n\tint i;\n\tint dfcode;\n\tint Nb_device = 0;\n\t\t\n\tAT91F_SpiInit();\n\n\tfor (i = 0; i < CFG_MAX_DATAFLASH_BANKS; i++) {\n\t\tdataflash_info[i].id = 0;\n\t\tdataflash_info[i].Device.pages_number = 0;\n\t\tdfcode = AT91F_DataflashProbe (cs[i][1], &dataflash_info[i].Desc);\n\n\t\tswitch (dfcode) {\n\t\tcase AT45DB161:\n\t\t\tdataflash_info[i].Device.pages_number = 4096;\n\t\t\tdataflash_info[i].Device.pages_size = 528;\n\t\t\tdataflash_info[i].Device.page_offset = 10;\n\t\t\tdataflash_info[i].Device.byte_mask = 0x300;\n\t\t\tdataflash_info[i].Device.cs = cs[i][1];\n\t\t\tdataflash_info[i].Desc.DataFlash_state = IDLE;\n\t\t\tdataflash_info[i].logical_address = cs[i][0];\n\t\t\tdataflash_info[i].id = dfcode;\n\t\t\tNb_device++;\n\t\t\tbreak;\n\n\t\tcase AT45DB321:\n\t\t\tdataflash_info[i].Device.pages_number = 8192;\n\t\t\tdataflash_info[i].Device.pages_size = 528;\n\t\t\tdataflash_info[i].Device.page_offset = 10;\n\t\t\tdataflash_info[i].Device.byte_mask = 0x300;\n\t\t\tdataflash_info[i].Device.cs = cs[i][1];\n\t\t\tdataflash_info[i].Desc.DataFlash_state = IDLE;\n\t\t\tdataflash_info[i].logical_address = cs[i][0];\n\t\t\tdataflash_info[i].id = dfcode;\n\t\t\tNb_device++;\n\t\t\tbreak;\n\n\t\tcase AT45DB642:\n\t\t\tdataflash_info[i].Device.pages_number = 8192;\n\t\t\tdataflash_info[i].Device.pages_size = 1056;\n\t\t\tdataflash_info[i].Device.page_offset = 11;\n\t\t\tdataflash_info[i].Device.byte_mask = 0x700;\n\t\t\tdataflash_info[i].Device.cs = cs[i][1];\n\t\t\tdataflash_info[i].Desc.DataFlash_state = IDLE;\n\t\t\tdataflash_info[i].logical_address = cs[i][0];\n\t\t\tdataflash_info[i].id = dfcode;\n\t\t\tNb_device++;\n\t\t\tbreak;\n\t\tcase AT45DB128:\n\t\t\tdataflash_info[i].Device.pages_number = 16384;\n\t\t\tdataflash_info[i].Device.pages_size = 1056;\n\t\t\tdataflash_info[i].Device.page_offset = 11;\n\t\t\tdataflash_info[i].Device.byte_mask = 0x700;\n\t\t\tdataflash_info[i].Device.cs = cs[i][1];\n\t\t\tdataflash_info[i].Desc.DataFlash_state = IDLE;\n\t\t\tdataflash_info[i].logical_address = cs[i][0];\n\t\t\tdataflash_info[i].id = dfcode;\n\t\t\tNb_device++;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tbreak;\n\t\t}\n\t}\t\t\t\n\treturn (Nb_device);\n}\n\n\nvoid AT91F_DataflashPrintInfo(void)\n{\n\tint i;\n\tfor (i = 0; i < CFG_MAX_DATAFLASH_BANKS; i++) {\n\t\tif (dataflash_info[i].id != 0) {\n\t\t\tprintf (\"DF:AT45DB\");\n\t\t\tswitch (dataflash_info[i].id) {\n\t\t\tcase AT45DB161:\n\t\t\t\tprintf (\"161\");\n\t\t\t\tbreak;\n\n\t\t\tcase AT45DB321:\n\t\t\t\tprintf (\"321\");\n\t\t\t\tbreak;\n\n\t\t\tcase AT45DB642:\n\t\t\t\tprintf (\"642\");\n\t\t\t\tbreak;\n\t\t\tcase AT45DB128:\t\t\t\t\n\t\t\t\tprintf (\"128\");\n\t\t\t\tbreak;\n\t\t\t}\n\n\t\t\tprintf (\"\\n# PG: %6d\\n\"\n\t\t\t\t\"PG SZ: %6d\\n\"\n\t\t\t\t\"SZ=%8d bytes\\n\"\n\t\t\t\t\"ADDR: %08X\\n\",\n\t\t\t\t(unsigned int) dataflash_info[i].Device.pages_number,\n\t\t\t\t(unsigned int) dataflash_info[i].Device.pages_size,\n\t\t\t\t(unsigned int) dataflash_info[i].Device.pages_number *\n\t\t\t\tdataflash_info[i].Device.pages_size,\n\t\t\t\t(unsigned int) dataflash_info[i].logical_address);\n\t\t}\n\t}\n}\n\n\n/*------------------------------------------------------------------------------*/\n/* Function Name       : AT91F_DataflashSelect                                  */\n/* Object              : Select the correct device                              */\n/*------------------------------------------------------------------------------*/\nstatic AT91PS_DataFlash AT91F_DataflashSelect(AT91PS_DataFlash pFlash,\n                                              unsigned int *addr)\n{\n\tchar addr_valid = 0;\n\tint i;\n\n\tfor (i = 0; i < CFG_MAX_DATAFLASH_BANKS; i++)\n\t\tif ((*addr & 0xFF000000) == dataflash_info[i].logical_address) {\n\t\t\taddr_valid = 1;\n\t\t\tbreak;\n\t\t}\n\tif (!addr_valid) {\n\t\tpFlash = (AT91PS_DataFlash) 0;\n\t\treturn pFlash;\n\t}\n\tpFlash->pDataFlashDesc = &(dataflash_info[i].Desc);\n\tpFlash->pDevice = &(dataflash_info[i].Device);\n\t*addr -= dataflash_info[i].logical_address;\n\treturn (pFlash);\n}\n\n\n/*------------------------------------------------------------------------------*/\n/* Function Name       : read_dataflash                                         */\n/* Object              : dataflash memory read                                  */\n/*------------------------------------------------------------------------------*/\nint read_dataflash(unsigned long addr, unsigned long size, char *result)\n{\n\tunsigned int AddrToRead = addr;\n\tAT91PS_DataFlash pFlash = &DataFlashInst;\n\n\tpFlash = AT91F_DataflashSelect (pFlash, &AddrToRead);\n\tif (pFlash == 0)\n\t\treturn -1;\n\n\treturn (AT91F_DataFlashRead(pFlash, AddrToRead, size, result));\n}\n\n\n/*-----------------------------------------------------------------------------*/\n/* Function Name       : write_dataflash                                       */\n/* Object              : write a block in dataflash                            */\n/*-----------------------------------------------------------------------------*/\nint write_dataflash(unsigned long addr_dest, unsigned int addr_src,\n                    unsigned int size)\n{\n\tunsigned int AddrToWrite = addr_dest;\n\tAT91PS_DataFlash pFlash = &DataFlashInst;\n\n\tpFlash = AT91F_DataflashSelect(pFlash, &AddrToWrite);\n\tif (AddrToWrite == -1)\n\t\treturn -1;\n\n\treturn AT91F_DataFlashWrite(pFlash, (unsigned char *) addr_src, AddrToWrite, size);\n}\n\n/*-----------------------------------------------------------------------------*/\n/* Function Name       : erase_dataflash                                       */\n/* Object              : Erase entire dataflash                                */\n/*-----------------------------------------------------------------------------*/\nint erase_dataflash(unsigned long addr_dest)\n{\n\tunsigned int AddrToWrite = addr_dest;\n\tAT91PS_DataFlash pFlash = &DataFlashInst;\n\n\tpFlash = AT91F_DataflashSelect (pFlash, &AddrToWrite);\n\tif (AddrToWrite == -1)\n\t\treturn -1;\n\n\treturn AT91F_DataFlashErase(pFlash);\n}\n\n"
  },
  {
    "path": "target/linux/at91/image/dfboot/src/dataflash.h",
    "content": "//*---------------------------------------------------------------------------\n//*         ATMEL Microcontroller Software Support  -  ROUSSET  -\n//*---------------------------------------------------------------------------\n//* The software is delivered \"AS IS\" without warranty or condition of any\n//* kind, either express, implied or statutory. This includes without\n//* limitation any warranty or condition with respect to merchantability or\n//* fitness for any particular purpose, or against the infringements of\n//* intellectual property rights of others.\n//*---------------------------------------------------------------------------\n//* File Name           : AT91_SpiDataFlash.h\n//* Object              : Data Flash Atmel Description File\n//* Translator          :\n//*\n//* 1.0 03/04/01 HI\t: Creation\n//*\n//*---------------------------------------------------------------------------\n\n#ifndef _DataFlash_h\n#define _DataFlash_h\n\n/* Max value = 15Mhz to be compliant with the Continuous array read function */\n#ifdef\tSPI_LOW_SPEED\n#define AT91C_SPI_CLK 14976000/4\n#else\n#define AT91C_SPI_CLK 14976000 \n#endif\n\n/* AC characteristics */\n/* DLYBS = tCSS= 250ns min and DLYBCT = tCSH = 250ns */\n\n#define DATAFLASH_TCSS (0xf << 16)\t/* 250ns 15/60000000 */\n#define DATAFLASH_TCHS (0x1 << 24)\t/* 250ns 32*1/60000000 */\n\n\n#define AT91C_SPI_PCS0_SERIAL_DATAFLASH\t\t0xE     /* Chip Select 0 : NPCS0 %1110 */\n#define AT91C_SPI_PCS3_DATAFLASH_CARD\t\t0x7     /* Chip Select 3 : NPCS3 %0111 */\n\n#define CFG_MAX_DATAFLASH_BANKS \t    2\n#define CFG_DATAFLASH_LOGIC_ADDR_CS0\t0xC0000000\n#define CFG_DATAFLASH_LOGIC_ADDR_CS3\t0xD0000000\n\ntypedef struct {\n\tunsigned long base;\t\t/* logical base address for a bank */\n\tunsigned long size;\t\t/* total bank size */\n\tunsigned long page_count;\n\tunsigned long page_size;\n\tunsigned long id;\t\t/* device id */\n} dataflash_info_t;\n\ntypedef unsigned int AT91S_DataFlashStatus;\n\n/*----------------------------------------------------------------------*/\n/* DataFlash Structures\t\t\t\t\t\t\t*/\n/*----------------------------------------------------------------------*/\n\n/*---------------------------------------------*/\n/* DataFlash Descriptor Structure Definition   */\n/*---------------------------------------------*/\ntypedef struct _AT91S_DataflashDesc {\n\tunsigned char *tx_cmd_pt;\n\tunsigned int tx_cmd_size;\n\tunsigned char *rx_cmd_pt;\n\tunsigned int rx_cmd_size;\n\tunsigned char *tx_data_pt;\n\tunsigned int tx_data_size;\n\tunsigned char *rx_data_pt;\n\tunsigned int rx_data_size;\n\tvolatile unsigned char DataFlash_state;\n\tunsigned char command[8];\n} AT91S_DataflashDesc, *AT91PS_DataflashDesc;\n\n/*---------------------------------------------*/\n/* DataFlash device definition structure       */\n/*---------------------------------------------*/\ntypedef struct _AT91S_Dataflash {\n\tint pages_number;\t\t\t/* dataflash page number */\n\tint pages_size;\t\t\t\t/* dataflash page size */\n\tint page_offset;\t\t\t/* page offset in command */\n\tint byte_mask;\t\t\t\t/* byte mask in command */\n\tint cs;\n} AT91S_DataflashFeatures, *AT91PS_DataflashFeatures;\n\n\n/*---------------------------------------------*/\n/* DataFlash Structure Definition\t       */\n/*---------------------------------------------*/\ntypedef struct _AT91S_DataFlash {\n\tAT91PS_DataflashDesc pDataFlashDesc;\t/* dataflash descriptor */\n\tAT91PS_DataflashFeatures pDevice;\t/* Pointer on a dataflash features array */\n} AT91S_DataFlash, *AT91PS_DataFlash;\n\n\ntypedef struct _AT91S_DATAFLASH_INFO {\n\n\tAT91S_DataflashDesc \tDesc;\n\tAT91S_DataflashFeatures Device; /* Pointer on a dataflash features array */\n\tunsigned long \t\t\tlogical_address;\n\tunsigned int \t\t\tid;\t\t\t/* device id */\n} AT91S_DATAFLASH_INFO, *AT91PS_DATAFLASH_INFO;\n\n\n/*-------------------------------------------------------------------------------------------------*/\n\n#define AT45DB161\t\t0x2c\n#define AT45DB321\t\t0x34\n#define AT45DB642\t\t0x3c\n#define AT45DB128\t\t0x10\n\n#define AT91C_DATAFLASH_TIMEOUT\t\t\t20000\t/* For AT91F_DataFlashWaitReady */\n\n/* DataFlash return value */\n#define AT91C_DATAFLASH_BUSY\t\t\t0x00\n#define AT91C_DATAFLASH_OK\t\t\t0x01\n#define AT91C_DATAFLASH_ERROR\t\t\t0x02\n#define AT91C_DATAFLASH_MEMORY_OVERFLOW\t\t0x03\n#define AT91C_DATAFLASH_BAD_COMMAND\t\t0x04\n#define AT91C_DATAFLASH_BAD_ADDRESS\t\t0x05\n\n\n/* Driver State */\n#define IDLE\t\t0x0\n#define BUSY\t\t0x1\n#define ERROR\t\t0x2\n\n/* DataFlash Driver State */\n#define GET_STATUS\t0x0F\n\n/*-------------------------------------------------------------------------------------------------*/\n/* Command Definition\t\t\t\t\t\t\t\t\t\t   */\n/*-------------------------------------------------------------------------------------------------*/\n\n/* READ COMMANDS */\n#define DB_CONTINUOUS_ARRAY_READ\t0xE8\t/* Continuous array read */\n#define DB_BURST_ARRAY_READ\t\t0xE8\t/* Burst array read */\n#define DB_PAGE_READ\t\t\t0xD2\t/* Main memory page read */\n#define DB_BUF1_READ\t\t\t0xD4\t/* Buffer 1 read */\n#define DB_BUF2_READ\t\t\t0xD6\t/* Buffer 2 read */\n#define DB_STATUS\t\t\t0xD7\t/* Status Register */\n\n/* PROGRAM and ERASE COMMANDS */\n#define DB_BUF1_WRITE\t\t\t0x84\t/* Buffer 1 write */\n#define DB_BUF2_WRITE\t\t\t0x87\t/* Buffer 2 write */\n#define DB_BUF1_PAGE_ERASE_PGM\t\t0x83\t/* Buffer 1 to main memory page program with built-In erase */\n#define DB_BUF1_PAGE_ERASE_FASTPGM\t0x93\t/* Buffer 1 to main memory page program with built-In erase, Fast program */\n#define DB_BUF2_PAGE_ERASE_PGM\t\t0x86\t/* Buffer 2 to main memory page program with built-In erase */\n#define DB_BUF2_PAGE_ERASE_FASTPGM\t0x96\t/* Buffer 1 to main memory page program with built-In erase, Fast program */\n#define DB_BUF1_PAGE_PGM\t\t0x88\t/* Buffer 1 to main memory page program without built-In erase */\n#define DB_BUF1_PAGE_FASTPGM\t\t0x98\t/* Buffer 1 to main memory page program without built-In erase, Fast program */\n#define DB_BUF2_PAGE_PGM\t\t0x89\t/* Buffer 2 to main memory page program without built-In erase */\n#define DB_BUF2_PAGE_FASTPGM\t\t0x99\t/* Buffer 1 to main memory page program without built-In erase, Fast program */\n#define DB_PAGE_ERASE\t\t\t0x81\t/* Page Erase */\n#define DB_BLOCK_ERASE\t\t\t0x50\t/* Block Erase */\n#define DB_PAGE_PGM_BUF1\t\t0x82\t/* Main memory page through buffer 1 */\n#define DB_PAGE_FASTPGM_BUF1\t\t0x92\t/* Main memory page through buffer 1, Fast program */\n#define DB_PAGE_PGM_BUF2\t\t0x85\t/* Main memory page through buffer 2 */\n#define DB_PAGE_FastPGM_BUF2\t\t0x95\t/* Main memory page through buffer 2, Fast program */\n\n/* ADDITIONAL COMMANDS */\n#define DB_PAGE_2_BUF1_TRF\t\t0x53\t/* Main memory page to buffer 1 transfert */\n#define DB_PAGE_2_BUF2_TRF\t\t0x55\t/* Main memory page to buffer 2 transfert */\n#define DB_PAGE_2_BUF1_CMP\t\t0x60\t/* Main memory page to buffer 1 compare */\n#define DB_PAGE_2_BUF2_CMP\t\t0x61\t/* Main memory page to buffer 2 compare */\n#define DB_AUTO_PAGE_PGM_BUF1\t\t0x58\t/* Auto page rewrite throught buffer 1 */\n#define DB_AUTO_PAGE_PGM_BUF2\t\t0x59\t/* Auto page rewrite throught buffer 2 */\n\n/*-------------------------------------------------------------------------------------------------*/\n\nextern AT91S_DATAFLASH_INFO dataflash_info[CFG_MAX_DATAFLASH_BANKS];\n\nextern void AT91F_SpiInit(void);\nextern int AT91F_DataflashProbe(int i, AT91PS_DataflashDesc pDesc);\nextern int AT91F_DataFlashRead(AT91PS_DataFlash, unsigned long , unsigned long, char *);\nextern AT91S_DataFlashStatus AT91F_DataFlashWrite(AT91PS_DataFlash ,unsigned char *, int, int);\nextern AT91S_DataFlashStatus AT91F_DataFlashErase(AT91PS_DataFlash pDataFlash);\nextern int AT91F_DataflashInit(void);\nextern void AT91F_DataflashPrintInfo(void);\nextern int read_dataflash(unsigned long addr, unsigned long size, char *result);\nextern int write_dataflash(unsigned long addr_dest, unsigned int addr_src, unsigned int size);\nextern int erase_dataflash(unsigned long addr_dest);\n\n#endif\n"
  },
  {
    "path": "target/linux/at91/image/dfboot/src/div0.c",
    "content": "/*\n * (C) Copyright 2002\n * Wolfgang Denk, DENX Software Engineering, wd@denx.de.\n *\n * See file CREDITS for list of people who contributed to this\n * project.\n *\n * This program is free software; you can redistribute it and/or\n * modify it under the terms of the GNU General Public License as\n * published by the Free Software Foundation; either version 2 of\n * the License, or (at your option) any later version.\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n * GNU General Public License for more details.\n *\n * You should have received a copy of the GNU General Public License\n * along with this program; if not, write to the Free Software\n * Foundation, Inc., 59 Temple Place, Suite 330, Boston,\n * MA 02111-1307 USA\n */\n\n/* Replacement (=dummy) for GNU/Linux division-by zero handler */\nvoid __div0 (void)\n{\n\twhile(-1);\n}\n"
  },
  {
    "path": "target/linux/at91/image/dfboot/src/elf32-littlearm.lds",
    "content": "OUTPUT_FORMAT(\"elf32-littlearm\", \"elf32-littlearm\", \"elf32-littlearm\")\nOUTPUT_ARCH(arm)\nENTRY(_start)\nSECTIONS\n{\n        . = 0x00000000;\n\n        . = ALIGN(4);\n        .text : { *(.text) }\n\n        . = ALIGN(4);\n        .rodata : { *(.rodata) }\n\n        . = ALIGN(4);\n        .data : { *(.data) }\n\n        . = ALIGN(4);\n        .bss : { *(.bss) }\n}"
  },
  {
    "path": "target/linux/at91/image/dfboot/src/embedded_services.h",
    "content": "//*----------------------------------------------------------------------------\n//*      ATMEL Microcontroller Software Support  -  ROUSSET  -\n//*----------------------------------------------------------------------------\n//* The software is delivered \"AS IS\" without warranty or condition of any\n//* kind, either express, implied or statutory. This includes without\n//* limitation any warranty or condition with respect to merchantability or\n//* fitness for any particular purpose, or against the infringements of\n//* intellectual property rights of others.\n//*----------------------------------------------------------------------------\n//* File Name           : embedded_sevices.h\n//* Object              : Header File with all the embedded software services definitions\n//*\n//* 1.0 24 Jan 2003 FB  : Creation\n//*----------------------------------------------------------------------------\n#ifndef embedded_sevices_h\n#define embedded_sevices_h\n\n#include \"AT91RM9200.h\"\n\n#define AT91C_BASE_ROM\t(char *)0x00100000\n\n/* Return values */\n#define AT91C_BUFFER_SUCCESS\t\t   0\n#define AT91C_BUFFER_ERROR_SHIFT      16\n#define AT91C_BUFFER_ERROR            (0x0F << AT91C_BUFFER_ERROR_SHIFT)\n\n#define AT91C_BUFFER_OVERFLOW         (0x01 << AT91C_BUFFER_ERROR_SHIFT)\n#define AT91C_BUFFER_UNDERRUN         (0x02 << AT91C_BUFFER_ERROR_SHIFT)\n\ntypedef unsigned int AT91S_BufferStatus;\n\nstruct _AT91S_Pipe;\n\n// This structure is a virtual object of a buffer\ntypedef struct _AT91S_Buffer\n{\n\tstruct _AT91S_Pipe *pPipe;\n\tvoid *pChild;\n\n\t// Functions invoked by the pipe\n\tAT91S_BufferStatus (*SetRdBuffer)     (struct _AT91S_Buffer *pSBuffer, char *pBuffer, unsigned int Size);\n\tAT91S_BufferStatus (*SetWrBuffer)     (struct _AT91S_Buffer *pSBuffer, char const *pBuffer, unsigned int Size);\n\tAT91S_BufferStatus (*RstRdBuffer)     (struct _AT91S_Buffer *pSBuffer);\n\tAT91S_BufferStatus (*RstWrBuffer)     (struct _AT91S_Buffer *pSBuffer);\n\tchar (*MsgWritten)      (struct _AT91S_Buffer *pSBuffer, char const *pBuffer);\n\tchar (*MsgRead)         (struct _AT91S_Buffer *pSBuffer, char const *pBuffer);\n\t// Functions invoked by the peripheral\n\tAT91S_BufferStatus (*GetWrBuffer)     (struct _AT91S_Buffer *pSBuffer, char const **pData, unsigned int *pSize);\n\tAT91S_BufferStatus (*GetRdBuffer)     (struct _AT91S_Buffer *pSBuffer, char **pData, unsigned int *pSize);\n\tAT91S_BufferStatus (*EmptyWrBuffer)   (struct _AT91S_Buffer *pSBuffer, unsigned int size);\n\tAT91S_BufferStatus (*FillRdBuffer)    (struct _AT91S_Buffer *pSBuffer, unsigned int size);\n\tchar (*IsWrEmpty)      (struct _AT91S_Buffer *pSBuffer);\n\tchar (*IsRdFull)       (struct _AT91S_Buffer *pSBuffer);\n} AT91S_Buffer, *AT91PS_Buffer;\n\n// ===========================================================================================\n// SimpleBuffer definition\n//\n// This structure is pointed by pRealBuffer field in the SBuffer\n// It contains usefull information for a real implementation of\n// a SBuffer object.\n// The application just create an instance of SSBUffer and SBuffer,\n// call OpenSimpleBuffer, and continue using SBuffer instance\n\ntypedef struct _AT91S_SBuffer\n{\n\tAT91S_Buffer parent;\n\tchar         *pRdBuffer;\n\tchar const   *pWrBuffer;\n\tunsigned int szRdBuffer;\n\tunsigned int szWrBuffer;\n\tunsigned int stRdBuffer;\n\tunsigned int stWrBuffer;\n} AT91S_SBuffer, *AT91PS_SBuffer;\n\ntypedef AT91PS_Buffer (*AT91PF_OpenSBuffer) (AT91PS_SBuffer);\n\n// This function is called by the application\nextern AT91PS_Buffer AT91F_OpenSBuffer(AT91PS_SBuffer pBuffer);\n\n// Functions invoked by the pipe\nextern AT91S_BufferStatus AT91F_SbSetRdBuffer  (AT91PS_Buffer pBuffer, char *pData, unsigned int Size);\nextern AT91S_BufferStatus AT91F_SbSetWrBuffer  (AT91PS_Buffer pBuffer, char const *pData, unsigned int Size);\nextern AT91S_BufferStatus AT91F_SbRstRdBuffer  (AT91PS_Buffer pBuffer);\nextern AT91S_BufferStatus AT91F_SbRstWrBuffer  (AT91PS_Buffer pBuffer);\nextern char AT91F_SbMsgWritten   (AT91PS_Buffer pBuffer, char const *pMsg);\nextern char AT91F_SbMsgRead      (AT91PS_Buffer pBuffer, char const *pMsg);\n// Functions invoked by the peripheral\nextern AT91S_BufferStatus AT91F_SbGetWrBuffer  (AT91PS_Buffer pBuffer, char const **pData, unsigned int *pSize);\nextern AT91S_BufferStatus AT91F_SbGetRdBuffer  (AT91PS_Buffer pBuffer, char **pData, unsigned int *pSize);\nextern AT91S_BufferStatus AT91F_SbEmptyWrBuffer(AT91PS_Buffer pBuffer, unsigned int size);\nextern AT91S_BufferStatus AT91F_SbFillRdBuffer (AT91PS_Buffer pBuffer, unsigned int size);\nextern char AT91F_SbIsWrEmpty   (AT91PS_Buffer pBuffer);\nextern char AT91F_SbIsRdFull    (AT91PS_Buffer pBuffer);\n\n#ifdef DBG_DRV_BUFFER\nextern char const *AT91F_SbGetError(AT91S_BufferStatus errorNumber);\n#endif\n\n\n#define AT91C_OPEN_CTRLTEMPO_SUCCESS\t0\n#define AT91C_ERROR_OPEN_CTRLTEMPO\t\t1\n#define AT91C_START_OK\t\t\t\t\t2\n#define AT91C_STOP_OK\t\t\t\t\t3\n#define AT91C_TIMEOUT_REACHED\t\t\t4\n\ntypedef enum _AT91E_SvcTempo {\n\tAT91E_SVCTEMPO_DIS,\n\tAT91E_SVCTEMPO_EN\n} AT91E_SvcTempo;\n\ntypedef unsigned int AT91S_TempoStatus;\n\n// AT91S_SvcTempo\ntypedef struct _AT91S_SvcTempo\n{\n\n\t// Methods:\n\tAT91S_TempoStatus (*Start)  (\n\t\tstruct _AT91S_SvcTempo *pSvc,\n\t\tunsigned int timeout,\n\t\tunsigned int reload,\n\t\tvoid (*callback) (AT91S_TempoStatus, void *),\n\t\tvoid *pData);\n\tAT91S_TempoStatus (*Stop)   (struct _AT91S_SvcTempo *pSvc);\n\n\tstruct _AT91S_SvcTempo *pPreviousTempo;\n\tstruct _AT91S_SvcTempo *pNextTempo;\n\n\t// Data\n\tunsigned int TickTempo;\t//* timeout value\n\tunsigned int ReloadTempo;//* Reload value for periodic execution\n\tvoid (*TempoCallback)(AT91S_TempoStatus, void *);\n\tvoid *pPrivateData;\n\tAT91E_SvcTempo flag;\n} AT91S_SvcTempo, *AT91PS_SvcTempo;\n\n\n// AT91S_CtrlTempo\ntypedef struct _AT91S_CtlTempo\n{\n\t// Members:\n\n\t// Start and stop for Timer\thardware\n\tAT91S_TempoStatus (*CtlTempoStart)  (void *pTimer);\n\tAT91S_TempoStatus (*CtlTempoStop)   (void *pTimer);\n\n\t// Start and stop for Tempo service\n\tAT91S_TempoStatus (*SvcTempoStart)  (\n\t\tstruct _AT91S_SvcTempo *pSvc,\n\t\tunsigned int timeout,\n\t\tunsigned int reload,\n\t\tvoid (*callback) (AT91S_TempoStatus, void *),\n\t\tvoid *pData);\n\tAT91S_TempoStatus (*SvcTempoStop)   (struct _AT91S_SvcTempo *pSvc);\n\tAT91S_TempoStatus (*CtlTempoSetTime)(struct _AT91S_CtlTempo *pCtrl, unsigned int NewTime);\n\tAT91S_TempoStatus (*CtlTempoGetTime)(struct _AT91S_CtlTempo *pCtrl);\n\tAT91S_TempoStatus (*CtlTempoIsStart)(struct _AT91S_CtlTempo *pCtrl);\n\tAT91S_TempoStatus (*CtlTempoCreate) (\n\t\t\t\t\t\t\t\tstruct _AT91S_CtlTempo *pCtrl,\n\t\t\t\t\t\t\t\tstruct _AT91S_SvcTempo *pTempo);\n\tAT91S_TempoStatus (*CtlTempoRemove) (\n\t\t\t\t\t\t\t\tstruct _AT91S_CtlTempo *pCtrl,\n\t\t\t\t\t\t\t\tstruct _AT91S_SvcTempo *pTempo);\n\tAT91S_TempoStatus (*CtlTempoTick)   (struct _AT91S_CtlTempo *pCtrl);\n\n\t// Data:\n\n\tvoid *pPrivateData;     // Pointer to devived class\n\tvoid const *pTimer;\t\t\t// hardware\n\tAT91PS_SvcTempo pFirstTempo;\n\tAT91PS_SvcTempo pNewTempo;\n} AT91S_CtlTempo, *AT91PS_CtlTempo;\ntypedef AT91S_TempoStatus (*AT91PF_OpenCtlTempo)   ( AT91PS_CtlTempo, void const *);\n\n// This function is called by the application.\nextern AT91S_TempoStatus AT91F_OpenCtlTempo( AT91PS_CtlTempo pCtrlTempo, void const *pTempoTimer );\n\nextern AT91S_TempoStatus AT91F_STStart   (void *);\nextern AT91S_TempoStatus AT91F_STStop    (void *);\nextern AT91S_TempoStatus AT91F_STSetTime (AT91PS_CtlTempo, unsigned int);\nextern AT91S_TempoStatus AT91F_STGetTime (AT91PS_CtlTempo);\nextern AT91S_TempoStatus AT91F_STIsStart (AT91PS_CtlTempo);\nextern AT91S_TempoStatus AT91F_CtlTempoCreate (AT91PS_CtlTempo, AT91PS_SvcTempo);\nextern AT91S_TempoStatus AT91F_CtlTempoRemove (AT91PS_CtlTempo, AT91PS_SvcTempo);\nextern AT91S_TempoStatus AT91F_CtlTempoTick   (AT91PS_CtlTempo);\nextern AT91S_TempoStatus AT91F_SvcTempoStart (\n\t\tAT91PS_SvcTempo pSvc,\n\t\tunsigned int timeout,\n\t\tunsigned int reload,\n\t\tvoid (*callback) (AT91S_TempoStatus, void *),\n\t\tvoid *pData);\nextern AT91S_TempoStatus AT91F_SvcTempoStop (AT91PS_SvcTempo);\n\n\n// Following types are defined in another header files\nstruct _AT91S_Buffer;\n\n// Constants:\n#define AT91C_COMMSVC_SUCCESS     0\n#define AT91C_COMMSVC_ERROR_SHIFT 8\n#define AT91C_COMMSVC_ERROR       (0x0f << AT91C_COMMSVC_ERROR_SHIFT)\n\ntypedef unsigned int AT91S_SvcCommStatus;\n\n// AT91S_Service definition\n// This structure is an abstraction of a communication peripheral\ntypedef struct _AT91S_Service\n{\n\t// Methods:\n\tAT91S_SvcCommStatus (*Reset)  (struct _AT91S_Service *pService);\n\tAT91S_SvcCommStatus (*StartTx)(struct _AT91S_Service *pService);\n\tAT91S_SvcCommStatus (*StartRx)(struct _AT91S_Service *pService);\n\tAT91S_SvcCommStatus (*StopTx) (struct _AT91S_Service *pService);\n\tAT91S_SvcCommStatus (*StopRx) (struct _AT91S_Service *pService);\n\tchar                (*TxReady)(struct _AT91S_Service *pService);\n\tchar                (*RxReady)(struct _AT91S_Service *pService);\n\t// Data:\n\tstruct _AT91S_Buffer *pBuffer; // Link to a buffer object\n\tvoid *pChild;\n} AT91S_SvcComm, *AT91PS_SvcComm;\n\n// Constants:\n#define AT91C_XMODEM_SOH         0x01         /* Start of Heading for 128 bytes */\n#define AT91C_XMODEM_STX         0x02         /* Start of heading for 1024 bytes */\n#define AT91C_XMODEM_EOT         0x04         /* End of transmission */\n#define AT91C_XMODEM_ACK         0x06         /* Acknowledge */\n#define AT91C_XMODEM_NAK         0x15         /* Negative Acknowledge */\n#define AT91C_XMODEM_CRCCHR      'C'\n\n#define AT91C_XMODEM_PACKET_SIZE 2                 // packet + packetCRC\n#define AT91C_XMODEM_CRC_SIZE    2                 // crcLSB + crcMSB\n#define AT91C_XMODEM_DATA_SIZE_SOH    128          // data 128 corresponding to SOH header\n#define AT91C_XMODEM_DATA_SIZE_STX    1024         // data 1024 corresponding to STX header\n\n//* Following structure is used by SPipe to refer to the USB device peripheral endpoint\ntypedef struct _AT91PS_SvcXmodem {\n\n\t// Public Methods:\n\tAT91S_SvcCommStatus (*Handler) (struct _AT91PS_SvcXmodem *, unsigned int);\n\tAT91S_SvcCommStatus (*StartTx) (struct _AT91PS_SvcXmodem *, unsigned int);\n\tAT91S_SvcCommStatus (*StopTx)  (struct _AT91PS_SvcXmodem *, unsigned int);\n\n\t// Private Methods:\n\tAT91S_SvcCommStatus (*ReadHandler)  (struct _AT91PS_SvcXmodem *, unsigned int csr);\n\tAT91S_SvcCommStatus (*WriteHandler) (struct _AT91PS_SvcXmodem *, unsigned int csr);\n\tunsigned short      (*GetCrc)       (char *ptr, unsigned int count);\n\tchar                (*CheckHeader)  (unsigned char currentPacket, char *packet);\n\tchar                (*CheckData)    (struct _AT91PS_SvcXmodem *);\n\n\tAT91S_SvcComm  parent;      // Base class\n\tAT91PS_USART  pUsart;\n\n\tAT91S_SvcTempo tempo; // Link to a AT91S_Tempo object\n\n\tchar          *pData;\n\tunsigned int  dataSize;        // = XMODEM_DATA_STX or XMODEM_DATA_SOH\n\tchar          packetDesc[AT91C_XMODEM_PACKET_SIZE];\n\tunsigned char packetId;         // Current packet\n\tchar          packetStatus;\n\tchar          isPacketDesc;\n\tchar          eot;            // end of transmition\n} AT91S_SvcXmodem, *AT91PS_SvcXmodem;\n\ntypedef AT91PS_SvcComm      (*AT91PF_OpenSvcXmodem) ( AT91PS_SvcXmodem, AT91PS_USART, AT91PS_CtlTempo);\n\n// This function is called by the application.\nextern AT91PS_SvcComm AT91F_OpenSvcXmodem( AT91PS_SvcXmodem, AT91PS_USART, AT91PS_CtlTempo);\n\nextern unsigned short AT91F_SvcXmodemGetCrc     (char *ptr, unsigned int count);\nextern char           AT91F_SvcXmodemCheckHeader(unsigned char currentPacket, char *packet);\nextern char           AT91F_SvcXmodemCheckData  (AT91PS_SvcXmodem pSvcXmodem);\nextern AT91S_SvcCommStatus AT91F_SvcXmodemReadHandler(AT91PS_SvcXmodem pSvcXmodem, unsigned int csr);\nextern AT91S_SvcCommStatus AT91F_SvcXmodemWriteHandler(AT91PS_SvcXmodem pSvcXmodem, unsigned int csr);\nextern AT91S_SvcCommStatus AT91F_SvcXmodemStartTx(AT91PS_SvcComm pSvcComm);\nextern AT91S_SvcCommStatus AT91F_SvcXmodemStopTx(AT91PS_SvcComm pSvcComm);\nextern AT91S_SvcCommStatus AT91F_SvcXmodemStartRx(AT91PS_SvcComm pSvcComm);\nextern AT91S_SvcCommStatus AT91F_SvcXmodemStopRx(AT91PS_SvcComm pSvcComm);\nextern char AT91F_SvcXmodemTxReady(AT91PS_SvcComm pService);\nextern char AT91F_SvcXmodemRxReady(AT91PS_SvcComm pSvcComm);\n\n\n// Constants:\n#define AT91C_PIPE_SUCCESS\t      0\n#define AT91C_PIPE_ERROR_SHIFT    8\n#define AT91C_PIPE_ERROR          (0x0F << AT91C_PIPE_ERROR_SHIFT)\n\n#define AT91C_PIPE_OPEN_FAILED    (1 << AT91C_PIPE_ERROR_SHIFT)\n#define AT91C_PIPE_WRITE_FAILED   (2 << AT91C_PIPE_ERROR_SHIFT)\n#define AT91C_PIPE_WRITE_ABORTED  (3 << AT91C_PIPE_ERROR_SHIFT)\n#define AT91C_PIPE_READ_FAILED    (4 << AT91C_PIPE_ERROR_SHIFT)\n#define AT91C_PIPE_READ_ABORTED   (5 << AT91C_PIPE_ERROR_SHIFT)\n#define AT91C_PIPE_ABORT_FAILED   (6 << AT91C_PIPE_ERROR_SHIFT)\n#define AT91C_PIPE_RESET_FAILED   (7 << AT91C_PIPE_ERROR_SHIFT)\n\n/* _AT91S_Pipe stucture */\ntypedef unsigned int AT91S_PipeStatus;\n\ntypedef struct _AT91S_Pipe\n{\n\t// A pipe is linked with a peripheral and a buffer\n\tAT91PS_SvcComm pSvcComm;\n\tAT91PS_Buffer  pBuffer;\n\n\t// Callback functions with their arguments\n\tvoid (*WriteCallback) (AT91S_PipeStatus, void *);\n\tvoid (*ReadCallback)  (AT91S_PipeStatus, void *);\n\tvoid *pPrivateReadData;\n\tvoid *pPrivateWriteData;\n\n\t// Pipe methods\n\tAT91S_PipeStatus (*Write) (\n\t\tstruct _AT91S_Pipe   *pPipe,\n\t\tchar const *         pData,\n\t\tunsigned int         size,\n\t\tvoid                 (*callback) (AT91S_PipeStatus, void *),\n\t\tvoid                 *privateData);\n\tAT91S_PipeStatus (*Read) (\n\t\tstruct _AT91S_Pipe  *pPipe,\n\t\tchar                *pData,\n\t\tunsigned int        size,\n\t\tvoid                (*callback) (AT91S_PipeStatus, void *),\n\t\tvoid                *privateData);\n\tAT91S_PipeStatus (*AbortWrite) (\n\t\tstruct _AT91S_Pipe  *pPipe);\n\tAT91S_PipeStatus (*AbortRead) (\n\t\tstruct _AT91S_Pipe *pPipe);\n\tAT91S_PipeStatus (*Reset) (\n\t\tstruct _AT91S_Pipe *pPipe);\n\tchar (*IsWritten) (\n\t\tstruct _AT91S_Pipe *pPipe,\n\t\tchar const *pVoid);\n\tchar (*IsReceived) (\n\t\tstruct _AT91S_Pipe *pPipe,\n\t\tchar const *pVoid);\n} AT91S_Pipe, *AT91PS_Pipe;\n\n// types used in AT91S_Pipe\ntypedef AT91PS_Pipe (*AT91PF_OpenPipe)   (AT91PS_Pipe, AT91PS_SvcComm, AT91PS_Buffer);\ntypedef void (*AT91PF_PipeWriteCallBack) (AT91S_PipeStatus, void *);\ntypedef void (*AT91PF_PipeReadCallBack)  (AT91S_PipeStatus, void *);\ntypedef AT91S_PipeStatus (*AT91PF_PipeWrite) (AT91PS_Pipe, char const *, unsigned int, void (*) (AT91S_PipeStatus, void *),\tvoid *);\ntypedef AT91S_PipeStatus (*AT91PF_PipeRead)  (AT91PS_Pipe, char const *, unsigned int, void (*) (AT91S_PipeStatus, void *),\tvoid *);\ntypedef AT91S_PipeStatus (*AT91PF_PipeAbortWrite) (AT91PS_Pipe);\ntypedef AT91S_PipeStatus (*AT91PF_PipeAbortRead)  (AT91PS_Pipe);\ntypedef AT91S_PipeStatus (*AT91PF_PipeReset)      (AT91PS_Pipe);\ntypedef char (*AT91PF_PipeIsWritten)              (AT91PS_Pipe, char const *);\ntypedef char (*AT91PF_PipeIsReceived)             (AT91PS_Pipe, char const *);\n\n// This function is called by the application\nextern AT91PS_Pipe AT91F_OpenPipe(\n\tAT91PS_Pipe    pPipe,\n\tAT91PS_SvcComm pSvcComm,\n\tAT91PS_Buffer  pBuffer);\n\n// Following functions are called through AT91S_Pipe pointers\n\nextern AT91S_PipeStatus AT91F_PipeWrite(\n\tAT91PS_Pipe pPipe,\n\tchar const *pVoid,\n\tunsigned int size,\n\tAT91PF_PipeWriteCallBack callback,\n\tvoid *privateData);\nextern AT91S_PipeStatus AT91F_PipeRead(\n\tAT91PS_Pipe pPipe,\n\tchar *pVoid,\n\tunsigned int Size,\n\tAT91PF_PipeReadCallBack callback,\n\tvoid *privateData);\nextern AT91S_PipeStatus AT91F_PipeAbortWrite(AT91PS_Pipe pPipe);\nextern AT91S_PipeStatus AT91F_PipeAbortRead(AT91PS_Pipe pPipe);\nextern AT91S_PipeStatus AT91F_PipeReset(AT91PS_Pipe pPipe);\nextern char AT91F_PipeMsgWritten(AT91PS_Pipe pPipe, char const *pVoid);\nextern char AT91F_PipeMsgReceived(AT91PS_Pipe pPipe, char const *pVoid);\n\n#ifdef DBG_DRV_PIPE\n// This function parse the error number and return a string\n// describing the error message\nextern char const *AT91F_PipeGetError(AT91S_PipeStatus msgId);\n#endif\n\nextern const unsigned char bit_rev[256];\n\nextern void CalculateCrc32(const unsigned char *,unsigned int, unsigned int *);\nextern void CalculateCrc16(const unsigned char *, unsigned int , unsigned short *); \nextern void CalculateCrcHdlc(const unsigned char *, unsigned int, unsigned short *);\nextern void CalculateCrc16ccitt(const unsigned char *, unsigned int , unsigned short *);\n\ntypedef const unsigned char* AT91PS_SVC_CRC_BIT_REV ;\n\ntypedef void  (*AT91PF_SVC_CRC32)   (const unsigned char *, unsigned int, unsigned int *);\ntypedef void  (*AT91PF_SVC_CRC16)   (const unsigned char *, unsigned int, unsigned short *);\ntypedef void  (*AT91PF_SVC_CRCHDLC) (const unsigned char *, unsigned int, unsigned short *);\ntypedef\tvoid  (*AT91PF_SVC_CRCCCITT)(const unsigned char *, unsigned int , unsigned short *);\n\n\ntypedef short (*AT91PF_Sinus) (int angle);\ntypedef const short * AT91PS_SINE_TAB;\n\nextern short AT91F_Sinus(int angle);\nextern const short AT91C_SINUS180_TAB[256];\n\n\ntypedef void (TypeAICHandler) (void) ;\n\n\n// ROM BOOT Structure Element Definition (liv v2)\ntypedef struct _AT91S_MEMCDesc\n{\n    AT91PS_MC\t\tmemc_base ;\t\t/* Peripheral base */\n    unsigned char\tperiph_id ;\t\t/* MC Peripheral Identifier */\n} AT91S_MEMCDesc, *AT91PS_MEMCDesc ;\n\ntypedef struct _AT91S_Pio2Desc\n{\n   AT91PS_PIO      pio_base ;       /* Base Address */\n   unsigned char   periph_id ;      /* Peripheral Identifier */\n   unsigned char   pio_number ;     /* Total Pin Number */\n} AT91S_Pio2Desc, *AT91PS_Pio2Desc ;\n\ntypedef struct _AT91S_SPIDesc\n{\n    AT91PS_SPI         \t\tspi_base ;\n    const AT91PS_PIO        pio_base ;\n    unsigned char           periph_id ;\n    unsigned char           pin_spck ;\n    unsigned char           pin_miso ;\n    unsigned char           pin_mosi ;\n    unsigned char           pin_npcs[4] ;\n} AT91S_SPIDesc, *AT91PS_SPIDesc ;\n\ntypedef struct _AT91S_USART2Desc\n{\n    AT91PS_USART           \tusart_base ;   \t/* Peripheral base */\n    const AT91PS_PIO   \t\tpio_base ;     \t/* IO controller descriptor */\n    unsigned int            pin_rxd ;       /* RXD pin number in the PIO */\n    unsigned int            pin_txd ;       /* TXD pin number in the PIO */\n    unsigned int            pin_sck ;       /* SCK pin number in the PIO */\n    unsigned int            pin_rts ;       /* RTS pin number in the PIO */\n    unsigned int            pin_cts ;       /* CTS pin number in the PIO */\n    unsigned int            pin_dtr ;       /* DTR pin number in the PIO */\n    unsigned int            pin_ri ;        /* RI pin number in the PIO */\n    unsigned int            pin_dsr ;       /* DSR pin number in the PIO */\n    unsigned int            pin_dcd ;       /* DCD pin number in the PIO */\n    unsigned int            periph_id ;     /* USART Peripheral Identifier */\n} AT91S_USART2Desc, *AT91PS_USART2Desc ;\n\ntypedef struct _AT91S_TWIDesc\n{\n    AT91PS_TWI \t\t\t\tTWI_base ;\n    const AT91PS_PIO        pio_base ;\n    unsigned int\t\t\tpin_sck ;\n    unsigned int\t\t\tpin_sda ;\n    unsigned int \t\t\tperiph_id;\n}AT91S_TWIDesc, *AT91PS_TWIDesc;\n\ntypedef struct _AT91S_STDesc\n{\n    AT91PS_ST  \t\tst_base ;          \t/* Peripheral base address */\n    TypeAICHandler  *AsmSTHandler ;     /* Assembly interrupt handler */\n    unsigned char   PeriphId ;          /* Peripheral Identifier */\n} AT91S_STDesc, *AT91PS_STDesc;\n\ntypedef struct _AT91S_RomBoot {\n\tconst unsigned int     version;\n\t// Peripheral descriptors\n\tconst AT91S_MEMCDesc   MEMC_DESC;\n\tconst AT91S_STDesc     SYSTIMER_DESC;\n\tconst AT91S_Pio2Desc   PIOA_DESC;\n\tconst AT91S_Pio2Desc   PIOB_DESC;\n\tconst AT91S_USART2Desc DBGU_DESC;\n\tconst AT91S_USART2Desc USART0_DESC;\n\tconst AT91S_USART2Desc USART1_DESC;\n\tconst AT91S_USART2Desc USART2_DESC;\n\tconst AT91S_USART2Desc USART3_DESC;\n\tconst AT91S_TWIDesc    TWI_DESC;\n\tconst AT91S_SPIDesc    SPI_DESC;\n\n\t// Objects entry\n\tconst AT91PF_OpenPipe      \t\tOpenPipe;\n\tconst AT91PF_OpenSBuffer   \t\tOpenSBuffer;\n\tconst unsigned int\t\t\t\treserved1;\n\tconst AT91PF_OpenSvcXmodem \t\tOpenSvcXmodem;\n\tconst AT91PF_OpenCtlTempo  \t\tOpenCtlTempo;\n\tconst unsigned int\t\t\t\treserved2;\n\tconst unsigned int\t\t\t\treserved3;\n\tconst unsigned int\t\t\t\treserved4;\n\tconst AT91PF_SVC_CRC16\t\t\tCRC16;\n\tconst AT91PF_SVC_CRCCCITT\t\tCRCCCITT;\n\tconst AT91PF_SVC_CRCHDLC\t\tCRCHDLC;\n\tconst AT91PF_SVC_CRC32\t\t\tCRC32;\n\tconst AT91PS_SVC_CRC_BIT_REV\tBit_Reverse_Array;\n\tconst AT91PS_SINE_TAB\t\t\tSineTab; \n\tconst AT91PF_Sinus              Sine;\n} AT91S_RomBoot, *AT91PS_RomBoot;\n\n#define AT91C_ROM_BOOT_ADDRESS ((const AT91S_RomBoot *) ( *((unsigned int *) (AT91C_BASE_ROM + 0x20))) )\n\n#endif\n\n"
  },
  {
    "path": "target/linux/at91/image/dfboot/src/include/AT91C_MCI_Device.h",
    "content": "//*---------------------------------------------------------------------------\n//*         ATMEL Microcontroller Software Support  -  ROUSSET  -\n//*---------------------------------------------------------------------------\n//* The software is delivered \"AS IS\" without warranty or condition of any\n//* kind, either express, implied or statutory. This includes without\n//* limitation any warranty or condition with respect to merchantability or\n//* fitness for any particular purpose, or against the infringements of\n//* intellectual property rights of others.\n//*---------------------------------------------------------------------------\n//* File Name           : AT91C_MCI_Device.h\n//* Object              : Data Flash Atmel Description File\n//* Translator          :\n//*\n//* 1.0 26/11/02 FB\t\t: Creation\n//*---------------------------------------------------------------------------\n\n#ifndef AT91C_MCI_Device_h\n#define AT91C_MCI_Device_h\n\n#include \"AT91RM9200.h\"\n#include \"lib_AT91RM9200.h\"\n\ntypedef unsigned int AT91S_MCIDeviceStatus;\n\n/////////////////////////////////////////////////////////////////////////////////////////////////////\n\n#define AT91C_CARD_REMOVED\t\t\t0\n#define AT91C_MMC_CARD_INSERTED\t\t1\n#define AT91C_SD_CARD_INSERTED\t\t2\n\n#define AT91C_NO_ARGUMENT\t\t\t0x0\n\n#define AT91C_FIRST_RCA\t\t\t\t0xCAFE\n#define AT91C_MAX_MCI_CARDS\t\t\t10\n\n#define AT91C_BUS_WIDTH_1BIT\t\t0x00\n#define AT91C_BUS_WIDTH_4BITS\t\t0x02\n\n/* Driver State */\n#define AT91C_MCI_IDLE       \t\t0x0\n#define AT91C_MCI_TIMEOUT_ERROR\t\t0x1\n#define AT91C_MCI_RX_SINGLE_BLOCK\t0x2\n#define AT91C_MCI_RX_MULTIPLE_BLOCK\t0x3\n#define AT91C_MCI_RX_STREAM\t\t\t0x4\n#define AT91C_MCI_TX_SINGLE_BLOCK\t0x5\n#define AT91C_MCI_TX_MULTIPLE_BLOCK\t0x6\n#define AT91C_MCI_TX_STREAM \t\t0x7\n\n/* TimeOut */\n#define AT91C_TIMEOUT_CMDRDY\t\t30\n\n/////////////////////////////////////////////////////////////////////////////////////////////////////\n// MMC & SDCard Structures \n/////////////////////////////////////////////////////////////////////////////////////////////////////\n\n/*-----------------------------------------------*/\n/* SDCard Device Descriptor Structure Definition */\n/*-----------------------------------------------*/\ntypedef struct\t_AT91S_MciDeviceDesc\n{\n    volatile unsigned char\tstate;\n\tunsigned char\t\t\tSDCard_bus_width;\n\n} AT91S_MciDeviceDesc, *AT91PS_MciDeviceDesc;\n\n/*---------------------------------------------*/\n/* MMC & SDCard Structure Device Features\t   */\n/*---------------------------------------------*/\ntypedef struct\t_AT91S_MciDeviceFeatures\n{\n    unsigned char\tCard_Inserted;\t\t\t\t// (0=AT91C_CARD_REMOVED) (1=AT91C_MMC_CARD_INSERTED) (2=AT91C_SD_CARD_INSERTED)\n    unsigned int \tRelative_Card_Address;\t\t// RCA\n\tunsigned int \tMax_Read_DataBlock_Length;\t// 2^(READ_BL_LEN) in CSD \n\tunsigned int \tMax_Write_DataBlock_Length;\t// 2^(WRITE_BL_LEN) in CSD\n\tunsigned char\tRead_Partial;\t\t\t\t// READ_BL_PARTIAL\n\tunsigned char\tWrite_Partial;\t\t\t\t// WRITE_BL_PARTIAL\n\tunsigned char\tErase_Block_Enable;\t\t\t// ERASE_BLK_EN\n\tunsigned char\tRead_Block_Misalignment;\t// READ_BLK_MISALIGN\n\tunsigned char\tWrite_Block_Misalignment;\t// WRITE_BLK_MISALIGN\n\tunsigned char\tSector_Size;\t\t\t\t// SECTOR_SIZE\n\tunsigned int\tMemory_Capacity;\t\t\t// Size in bits of the device\n\t\n}\tAT91S_MciDeviceFeatures, *AT91PS_MciDeviceFeatures ;\n\n/*---------------------------------------------*/\n/* MCI Device Structure Definition \t\t\t   */\n/*---------------------------------------------*/\ntypedef struct _AT91S_MciDevice\n{\n\tAT91PS_MciDeviceDesc\t\t \tpMCI_DeviceDesc;\t// MCI device descriptor\n\tAT91PS_MciDeviceFeatures\t\tpMCI_DeviceFeatures;// Pointer on a MCI device features array  \n}AT91S_MciDevice, *AT91PS_MciDevice;\n\n/////////////////////////////////////////////////////////////////////////////////////////////////////\n// MCI_CMD Register Value \n/////////////////////////////////////////////////////////////////////////////////////////////////////\n#define AT91C_POWER_ON_INIT\t\t\t\t\t\t(0\t| AT91C_MCI_TRCMD_NO \t| AT91C_MCI_SPCMD_INIT | AT91C_MCI_OPDCMD)\n\n/////////////////////////////////////////////////////////////////\t\n// Class 0 & 1 commands: Basic commands and Read Stream commands\n/////////////////////////////////////////////////////////////////\n\n#define AT91C_GO_IDLE_STATE_CMD\t\t\t\t\t(0 \t| AT91C_MCI_TRCMD_NO \t| AT91C_MCI_SPCMD_NONE )\n#define AT91C_MMC_GO_IDLE_STATE_CMD\t\t\t\t(0 \t| AT91C_MCI_TRCMD_NO \t| AT91C_MCI_SPCMD_NONE  | AT91C_MCI_OPDCMD)\n#define AT91C_MMC_SEND_OP_COND_CMD\t\t\t\t(1\t| AT91C_MCI_TRCMD_NO \t| AT91C_MCI_SPCMD_NONE\t| AT91C_MCI_RSPTYP_48 | AT91C_MCI_OPDCMD)\n#define AT91C_ALL_SEND_CID_CMD\t\t\t\t\t(2\t| AT91C_MCI_TRCMD_NO \t| AT91C_MCI_SPCMD_NONE\t| AT91C_MCI_RSPTYP_136 )\n#define AT91C_MMC_ALL_SEND_CID_CMD\t\t\t\t(2\t| AT91C_MCI_TRCMD_NO \t| AT91C_MCI_SPCMD_NONE\t| AT91C_MCI_RSPTYP_136 | AT91C_MCI_OPDCMD)\n#define AT91C_SET_RELATIVE_ADDR_CMD\t\t\t\t(3\t| AT91C_MCI_TRCMD_NO \t| AT91C_MCI_SPCMD_NONE\t| AT91C_MCI_RSPTYP_48\t\t| AT91C_MCI_MAXLAT )\n#define AT91C_MMC_SET_RELATIVE_ADDR_CMD\t\t\t(3\t| AT91C_MCI_TRCMD_NO \t| AT91C_MCI_SPCMD_NONE\t| AT91C_MCI_RSPTYP_48\t\t| AT91C_MCI_MAXLAT | AT91C_MCI_OPDCMD)\n\n#define AT91C_SET_DSR_CMD\t\t\t\t\t\t(4\t| AT91C_MCI_TRCMD_NO \t| AT91C_MCI_SPCMD_NONE\t| AT91C_MCI_RSPTYP_NO\t\t| AT91C_MCI_MAXLAT )\t// no tested\n\n#define AT91C_SEL_DESEL_CARD_CMD\t\t\t\t(7\t| AT91C_MCI_TRCMD_NO \t| AT91C_MCI_SPCMD_NONE\t| AT91C_MCI_RSPTYP_48  \t\t| AT91C_MCI_MAXLAT )\n#define AT91C_SEND_CSD_CMD\t\t\t\t\t\t(9\t| AT91C_MCI_TRCMD_NO \t| AT91C_MCI_SPCMD_NONE\t| AT91C_MCI_RSPTYP_136 \t\t| AT91C_MCI_MAXLAT )\n#define AT91C_SEND_CID_CMD\t\t\t\t\t\t(10\t| AT91C_MCI_TRCMD_NO \t| AT91C_MCI_SPCMD_NONE\t| AT91C_MCI_RSPTYP_136 \t\t| AT91C_MCI_MAXLAT )\n#define AT91C_MMC_READ_DAT_UNTIL_STOP_CMD\t\t(11\t| AT91C_MCI_TRTYP_STREAM| AT91C_MCI_SPCMD_NONE\t| AT91C_MCI_RSPTYP_48\t| AT91C_MCI_TRDIR\t| AT91C_MCI_TRCMD_START | AT91C_MCI_MAXLAT )\n\n#define AT91C_STOP_TRANSMISSION_CMD\t\t\t\t(12\t| AT91C_MCI_TRCMD_STOP \t| AT91C_MCI_SPCMD_NONE\t| AT91C_MCI_RSPTYP_48 \t\t| AT91C_MCI_MAXLAT )\n#define AT91C_STOP_TRANSMISSION_SYNC_CMD\t\t(12\t| AT91C_MCI_TRCMD_STOP \t| AT91C_MCI_SPCMD_SYNC\t| AT91C_MCI_RSPTYP_48 \t\t| AT91C_MCI_MAXLAT )\n#define AT91C_SEND_STATUS_CMD\t\t\t\t\t(13\t| AT91C_MCI_TRCMD_NO \t| AT91C_MCI_SPCMD_NONE\t| AT91C_MCI_RSPTYP_48 \t\t| AT91C_MCI_MAXLAT )\n#define AT91C_GO_INACTIVE_STATE_CMD\t\t\t\t(15\t| AT91C_MCI_RSPTYP_NO )\n\n//*------------------------------------------------\n//* Class 2 commands: Block oriented Read commands\n//*------------------------------------------------\n\n#define AT91C_SET_BLOCKLEN_CMD\t\t\t\t\t(16 | AT91C_MCI_TRCMD_NO \t| AT91C_MCI_SPCMD_NONE\t| AT91C_MCI_RSPTYP_48\t\t| AT91C_MCI_MAXLAT )\n#define AT91C_READ_SINGLE_BLOCK_CMD\t\t\t\t(17 | AT91C_MCI_SPCMD_NONE\t| AT91C_MCI_RSPTYP_48 \t| AT91C_MCI_TRCMD_START\t| AT91C_MCI_TRTYP_BLOCK\t| AT91C_MCI_TRDIR\t| AT91C_MCI_MAXLAT)\n#define AT91C_READ_MULTIPLE_BLOCK_CMD\t\t\t(18 | AT91C_MCI_SPCMD_NONE\t| AT91C_MCI_RSPTYP_48 \t| AT91C_MCI_TRCMD_START\t| AT91C_MCI_TRTYP_MULTIPLE\t| AT91C_MCI_TRDIR\t| AT91C_MCI_MAXLAT)\n\n//*--------------------------------------------\n//* Class 3 commands: Sequential write commands\n//*--------------------------------------------\n\n#define AT91C_MMC_WRITE_DAT_UNTIL_STOP_CMD\t\t(20 | AT91C_MCI_TRTYP_STREAM| AT91C_MCI_SPCMD_NONE\t| AT91C_MCI_RSPTYP_48 & ~(AT91C_MCI_TRDIR) | AT91C_MCI_TRCMD_START | AT91C_MCI_MAXLAT )\t// MMC\n\n//*------------------------------------------------\n//* Class 4 commands: Block oriented write commands\n//*------------------------------------------------\n\t\n#define AT91C_WRITE_BLOCK_CMD\t\t\t\t\t(24 | AT91C_MCI_SPCMD_NONE\t| AT91C_MCI_RSPTYP_48\t| AT91C_MCI_TRCMD_START\t| (AT91C_MCI_TRTYP_BLOCK \t&  ~(AT91C_MCI_TRDIR))\t| AT91C_MCI_MAXLAT)\n#define AT91C_WRITE_MULTIPLE_BLOCK_CMD\t\t\t(25 | AT91C_MCI_SPCMD_NONE\t| AT91C_MCI_RSPTYP_48\t| AT91C_MCI_TRCMD_START\t| (AT91C_MCI_TRTYP_MULTIPLE\t&  ~(AT91C_MCI_TRDIR)) \t| AT91C_MCI_MAXLAT)\n#define AT91C_PROGRAM_CSD_CMD\t\t\t\t\t(27 | AT91C_MCI_RSPTYP_48 )\n\n\n//*----------------------------------------\n//* Class 6 commands: Group Write protect\n//*----------------------------------------\n\n#define AT91C_SET_WRITE_PROT_CMD\t\t\t\t(28\t| AT91C_MCI_RSPTYP_48 )\n#define AT91C_CLR_WRITE_PROT_CMD\t\t\t\t(29\t| AT91C_MCI_RSPTYP_48 )\n#define AT91C_SEND_WRITE_PROT_CMD\t\t\t\t(30\t| AT91C_MCI_RSPTYP_48 )\n\n\n//*----------------------------------------\n//* Class 5 commands: Erase commands\n//*----------------------------------------\n\n#define AT91C_TAG_SECTOR_START_CMD\t\t\t\t(32 | AT91C_MCI_SPCMD_NONE\t| AT91C_MCI_RSPTYP_48\t| AT91C_MCI_TRCMD_NO\t| AT91C_MCI_MAXLAT)\n#define AT91C_TAG_SECTOR_END_CMD  \t\t\t\t(33 | AT91C_MCI_SPCMD_NONE\t| AT91C_MCI_RSPTYP_48\t| AT91C_MCI_TRCMD_NO\t| AT91C_MCI_MAXLAT)\n#define AT91C_MMC_UNTAG_SECTOR_CMD\t\t\t\t(34 | AT91C_MCI_RSPTYP_48 )\n#define AT91C_MMC_TAG_ERASE_GROUP_START_CMD\t\t(35 | AT91C_MCI_RSPTYP_48 )\n#define AT91C_MMC_TAG_ERASE_GROUP_END_CMD\t\t(36 | AT91C_MCI_RSPTYP_48 )\n#define AT91C_MMC_UNTAG_ERASE_GROUP_CMD\t\t\t(37 | AT91C_MCI_RSPTYP_48 )\n#define AT91C_ERASE_CMD\t\t\t\t\t\t\t(38 | AT91C_MCI_SPCMD_NONE\t| AT91C_MCI_RSPTYP_48\t| AT91C_MCI_TRCMD_NO\t| AT91C_MCI_MAXLAT )\n\n//*----------------------------------------\n//* Class 7 commands: Lock commands\n//*----------------------------------------\n\n#define AT91C_LOCK_UNLOCK\t\t\t\t\t\t(42 | AT91C_MCI_SPCMD_NONE\t| AT91C_MCI_RSPTYP_48\t| AT91C_MCI_TRCMD_NO\t| AT91C_MCI_MAXLAT)\t// no tested\n\n//*-----------------------------------------------\n// Class 8 commands: Application specific commands\n//*-----------------------------------------------\n\n#define AT91C_APP_CMD\t\t\t\t\t\t\t(55 | AT91C_MCI_SPCMD_NONE\t| AT91C_MCI_RSPTYP_48\t| AT91C_MCI_TRCMD_NO | AT91C_MCI_MAXLAT)\n#define AT91C_GEN_CMD\t\t\t\t\t\t\t(56 | AT91C_MCI_SPCMD_NONE\t| AT91C_MCI_RSPTYP_48\t| AT91C_MCI_TRCMD_NO | AT91C_MCI_MAXLAT)\t// no tested\n\n#define AT91C_SDCARD_SET_BUS_WIDTH_CMD\t\t\t(6 \t| AT91C_MCI_SPCMD_NONE\t| AT91C_MCI_RSPTYP_48\t| AT91C_MCI_TRCMD_NO\t| AT91C_MCI_MAXLAT)\n#define AT91C_SDCARD_STATUS_CMD\t\t\t\t\t(13 | AT91C_MCI_SPCMD_NONE\t| AT91C_MCI_RSPTYP_48\t| AT91C_MCI_TRCMD_NO\t| AT91C_MCI_MAXLAT)\n#define AT91C_SDCARD_SEND_NUM_WR_BLOCKS_CMD\t\t(22 | AT91C_MCI_SPCMD_NONE\t| AT91C_MCI_RSPTYP_48\t| AT91C_MCI_TRCMD_NO\t| AT91C_MCI_MAXLAT)\n#define AT91C_SDCARD_SET_WR_BLK_ERASE_COUNT_CMD\t(23 | AT91C_MCI_SPCMD_NONE\t| AT91C_MCI_RSPTYP_48\t| AT91C_MCI_TRCMD_NO\t| AT91C_MCI_MAXLAT)\n#define AT91C_SDCARD_APP_OP_COND_CMD\t\t\t(41 | AT91C_MCI_SPCMD_NONE\t| AT91C_MCI_RSPTYP_48\t| AT91C_MCI_TRCMD_NO )\n#define AT91C_SDCARD_SET_CLR_CARD_DETECT_CMD\t(42 | AT91C_MCI_SPCMD_NONE\t| AT91C_MCI_RSPTYP_48\t| AT91C_MCI_TRCMD_NO\t| AT91C_MCI_MAXLAT)\n#define AT91C_SDCARD_SEND_SCR_CMD\t\t\t\t(51 | AT91C_MCI_SPCMD_NONE\t| AT91C_MCI_RSPTYP_48\t| AT91C_MCI_TRCMD_NO\t| AT91C_MCI_MAXLAT)\n\n#define AT91C_SDCARD_APP_ALL_CMD\t\t\t\t(AT91C_SDCARD_SET_BUS_WIDTH_CMD +\\\n\t\t\t\t\t\t\t\t\t\t\t\tAT91C_SDCARD_STATUS_CMD +\\\n\t\t\t\t\t\t\t\t\t\t\t\tAT91C_SDCARD_SEND_NUM_WR_BLOCKS_CMD +\\\n\t\t\t\t\t\t\t\t\t\t\t\tAT91C_SDCARD_SET_WR_BLK_ERASE_COUNT_CMD +\\\n\t\t\t\t\t\t\t\t\t\t\t\tAT91C_SDCARD_APP_OP_COND_CMD +\\\n\t\t\t\t\t\t\t\t\t\t\t\tAT91C_SDCARD_SET_CLR_CARD_DETECT_CMD +\\\n\t\t\t\t\t\t\t\t\t\t\t\tAT91C_SDCARD_SEND_SCR_CMD)\n\n//*----------------------------------------\n//* Class 9 commands: IO Mode commands\n//*----------------------------------------\n\n#define AT91C_MMC_FAST_IO_CMD\t\t\t\t\t(39 | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_MAXLAT)\n#define AT91C_MMC_GO_IRQ_STATE_CMD\t\t\t\t(40 | AT91C_MCI_SPCMD_NONE | AT91C_MCI_RSPTYP_48 | AT91C_MCI_TRCMD_NO\t| AT91C_MCI_MAXLAT)\n\n/////////////////////////////////////////////////////////////////////////////////////////////////////\n// Functions returnals\n/////////////////////////////////////////////////////////////////////////////////////////////////////\n#define AT91C_CMD_SEND_OK\t\t\t\t\t0\t\t// Command ok\n#define AT91C_CMD_SEND_ERROR\t\t\t\t-1\t\t// Command failed\n#define AT91C_INIT_OK\t\t\t\t\t\t2\t\t// Init Successfull\n#define AT91C_INIT_ERROR\t\t\t\t\t3\t\t// Init Failed\n#define AT91C_READ_OK\t\t\t\t\t\t4\t\t// Read Successfull\n#define AT91C_READ_ERROR\t\t\t\t\t5\t\t// Read Failed\n#define AT91C_WRITE_OK\t\t\t\t\t\t6\t\t// Write Successfull\n#define AT91C_WRITE_ERROR\t\t\t\t\t7\t\t// Write Failed\n#define AT91C_ERASE_OK\t\t\t\t\t\t8\t\t// Erase Successfull\n#define AT91C_ERASE_ERROR\t\t\t\t\t9\t\t// Erase Failed\n#define AT91C_CARD_SELECTED_OK\t\t\t\t10\t\t// Card Selection Successfull\n#define AT91C_CARD_SELECTED_ERROR\t\t\t11\t\t// Card Selection Failed\n\n/////////////////////////////////////////////////////////////////////////////////////////////////////\n// MCI_SR Errors\n/////////////////////////////////////////////////////////////////////////////////////////////////////\n#define \tAT91C_MCI_SR_ERROR\t\t(AT91C_MCI_UNRE |\\\n\t\t\t\t\t\t\t\t\t AT91C_MCI_OVRE |\\\n\t\t\t\t\t\t\t\t\t AT91C_MCI_DTOE |\\\n\t\t\t\t\t\t\t\t\t AT91C_MCI_DCRCE |\\\n\t\t\t\t\t\t\t\t\t AT91C_MCI_RTOE |\\\n\t\t\t\t\t\t\t\t\t AT91C_MCI_RENDE |\\\n\t\t\t\t\t\t\t\t\t AT91C_MCI_RCRCE |\\\n\t\t\t\t\t\t\t\t\t AT91C_MCI_RDIRE |\\\n\t\t\t\t\t\t\t\t\t AT91C_MCI_RINDE)\n\n////////////////////////////////////////////////////////////////////////////////////////////////////\n// OCR Register\n////////////////////////////////////////////////////////////////////////////////////////////////////\n#define AT91C_VDD_16_17\t\t\t\t\t(1 << 4)\n#define AT91C_VDD_17_18\t\t\t\t\t(1 << 5)\n#define AT91C_VDD_18_19\t\t\t\t\t(1 << 6)\n#define AT91C_VDD_19_20\t\t\t\t\t(1 << 7)\n#define AT91C_VDD_20_21\t\t\t\t\t(1 << 8)\n#define AT91C_VDD_21_22\t\t\t\t\t(1 << 9)\n#define AT91C_VDD_22_23\t\t\t\t\t(1 << 10)\n#define AT91C_VDD_23_24\t\t\t\t\t(1 << 11)\n#define AT91C_VDD_24_25\t\t\t\t\t(1 << 12)\n#define AT91C_VDD_25_26\t\t\t\t\t(1 << 13)\n#define AT91C_VDD_26_27\t\t\t\t\t(1 << 14)\n#define AT91C_VDD_27_28\t\t\t\t\t(1 << 15)\n#define AT91C_VDD_28_29\t\t\t\t\t(1 << 16)\n#define AT91C_VDD_29_30\t\t\t\t\t(1 << 17)\n#define AT91C_VDD_30_31\t\t\t\t\t(1 << 18)\n#define AT91C_VDD_31_32\t\t\t\t\t(1 << 19)\n#define AT91C_VDD_32_33\t\t\t\t\t(1 << 20)\n#define AT91C_VDD_33_34\t\t\t\t\t(1 << 21)\n#define AT91C_VDD_34_35\t\t\t\t\t(1 << 22)\n#define AT91C_VDD_35_36\t\t\t\t\t(1 << 23)\n#define AT91C_CARD_POWER_UP_BUSY\t\t(1 << 31)\n\n#define AT91C_MMC_HOST_VOLTAGE_RANGE\t(AT91C_VDD_27_28 +\\\n\t\t\t\t\t\t\t\t\t\tAT91C_VDD_28_29 +\\\n\t\t\t\t\t\t\t\t\t\tAT91C_VDD_29_30 +\\\n\t\t\t\t\t\t\t\t\t\tAT91C_VDD_30_31 +\\\n\t\t\t\t\t\t\t\t\t\tAT91C_VDD_31_32 +\\\n\t\t\t\t\t\t\t\t\t\tAT91C_VDD_32_33)\n\n////////////////////////////////////////////////////////////////////////////////////////////////////\n// CURRENT_STATE & READY_FOR_DATA in SDCard Status Register definition (response type R1)\n////////////////////////////////////////////////////////////////////////////////////////////////////\n#define AT91C_SR_READY_FOR_DATA\t\t\t\t(1 << 8)\t// corresponds to buffer empty signalling on the bus\n#define AT91C_SR_IDLE\t\t\t\t\t\t(0 << 9)\n#define AT91C_SR_READY\t\t\t\t\t\t(1 << 9)\n#define AT91C_SR_IDENT\t\t\t\t\t\t(2 << 9)\n#define AT91C_SR_STBY\t\t\t\t\t\t(3 << 9)\n#define AT91C_SR_TRAN\t\t\t\t\t\t(4 << 9)\n#define AT91C_SR_DATA\t\t\t\t\t\t(5 << 9)\n#define AT91C_SR_RCV\t\t\t\t\t\t(6 << 9)\n#define AT91C_SR_PRG\t\t\t\t\t\t(7 << 9)\n#define AT91C_SR_DIS\t\t\t\t\t\t(8 << 9)\n\n#define AT91C_SR_CARD_SELECTED\t\t\t\t(AT91C_SR_READY_FOR_DATA + AT91C_SR_TRAN)\n\n/////////////////////////////////////////////////////////////////////////////////////////////////////\n// MMC CSD register header File\t\t\t\t\t\n// AT91C_CSD_xxx_S\tfor shift value\n// AT91C_CSD_xxx_M\tfor mask  value\n/////////////////////////////////////////////////////////////////////////////////////////////////////\n\n// First Response INT <=> CSD[3] : bits 0 to 31\n#define\tAT91C_CSD_BIT0_S\t\t\t0\t\t// [0:0]\t\t\t\n#define\tAT91C_CSD_BIT0_M\t\t\t0x01\t\t\t\t\n#define\tAT91C_CSD_CRC_S\t\t\t\t1\t\t// [7:1]\n#define\tAT91C_CSD_CRC_M\t\t\t\t0x7F\n#define\tAT91C_CSD_MMC_ECC_S\t\t\t8\t\t// [9:8]\t\treserved for MMC compatibility\n#define\tAT91C_CSD_MMC_ECC_M\t\t\t0x03\n#define\tAT91C_CSD_FILE_FMT_S\t\t10\t\t// [11:10]\n#define\tAT91C_CSD_FILE_FMT_M\t\t0x03\n#define\tAT91C_CSD_TMP_WP_S\t\t\t12\t\t// [12:12]\n#define\tAT91C_CSD_TMP_WP_M\t\t\t0x01\n#define\tAT91C_CSD_PERM_WP_S \t\t13\t\t// [13:13]\n#define\tAT91C_CSD_PERM_WP_M \t\t0x01\n#define\tAT91C_CSD_COPY_S\t \t\t14\t\t// [14:14]\n#define\tAT91C_CSD_COPY_M \t\t\t0x01\n#define\tAT91C_CSD_FILE_FMT_GRP_S\t15\t\t// [15:15]\n#define\tAT91C_CSD_FILE_FMT_GRP_M\t0x01\n//\treserved\t\t\t\t\t\t16\t\t// [20:16]\n//\treserved\t\t\t\t\t\t0x1F\n#define\tAT91C_CSD_WBLOCK_P_S \t\t21\t\t// [21:21]\n#define\tAT91C_CSD_WBLOCK_P_M \t\t0x01\n#define\tAT91C_CSD_WBLEN_S \t\t\t22\t\t// [25:22]\n#define\tAT91C_CSD_WBLEN_M \t\t\t0x0F\n#define\tAT91C_CSD_R2W_F_S \t\t\t26\t\t// [28:26]\n#define\tAT91C_CSD_R2W_F_M \t\t\t0x07\n#define\tAT91C_CSD_MMC_DEF_ECC_S\t\t29\t\t// [30:29]\t\treserved for MMC compatibility\n#define\tAT91C_CSD_MMC_DEF_ECC_M\t\t0x03\n#define\tAT91C_CSD_WP_GRP_EN_S\t\t31\t\t// [31:31]\n#define\tAT91C_CSD_WP_GRP_EN_M \t\t0x01\n\n// Seconde Response INT <=> CSD[2] : bits 32 to 63\n#define\tAT91C_CSD_v21_WP_GRP_SIZE_S\t0\t\t// [38:32]\t\t\t\t\n#define\tAT91C_CSD_v21_WP_GRP_SIZE_M\t0x7F\t\t\t\t\n#define\tAT91C_CSD_v21_SECT_SIZE_S\t7\t\t// [45:39]\n#define\tAT91C_CSD_v21_SECT_SIZE_M\t0x7F\n#define\tAT91C_CSD_v21_ER_BLEN_EN_S\t14\t\t// [46:46]\n#define\tAT91C_CSD_v21_ER_BLEN_EN_M\t0x01\n\n#define\tAT91C_CSD_v22_WP_GRP_SIZE_S\t0\t\t// [36:32]\t\t\t\t\n#define\tAT91C_CSD_v22_WP_GRP_SIZE_M\t0x1F\t\t\t\t\n#define\tAT91C_CSD_v22_ER_GRP_SIZE_S\t5\t\t// [41:37]\n#define\tAT91C_CSD_v22_ER_GRP_SIZE_M\t0x1F\n#define\tAT91C_CSD_v22_SECT_SIZE_S\t10\t\t// [46:42]\n#define\tAT91C_CSD_v22_SECT_SIZE_M\t0x1F\n\n#define\tAT91C_CSD_C_SIZE_M_S\t\t15\t\t// [49:47]\n#define\tAT91C_CSD_C_SIZE_M_M\t\t0x07\n#define\tAT91C_CSD_VDD_WMAX_S \t\t18\t\t// [52:50]\n#define\tAT91C_CSD_VDD_WMAX_M \t\t0x07\n#define\tAT91C_CSD_VDD_WMIN_S\t \t21\t\t// [55:53]\n#define\tAT91C_CSD_VDD_WMIN_M \t\t0x07\n#define\tAT91C_CSD_RCUR_MAX_S \t\t24\t\t// [58:56]\n#define\tAT91C_CSD_RCUR_MAX_M \t\t0x07\n#define\tAT91C_CSD_RCUR_MIN_S \t\t27\t\t// [61:59]\n#define\tAT91C_CSD_RCUR_MIN_M \t\t0x07\n#define\tAT91C_CSD_CSIZE_L_S \t\t30\t\t// [63:62] <=> 2 LSB of CSIZE\n#define\tAT91C_CSD_CSIZE_L_M \t\t0x03\n\n// Third Response INT <=> CSD[1] : bits 64 to 95\n#define\tAT91C_CSD_CSIZE_H_S \t\t0\t\t// [73:64]\t<=> 10 MSB of CSIZE\n#define\tAT91C_CSD_CSIZE_H_M \t\t0x03FF\n// reserved\t\t\t\t\t\t\t10\t\t// [75:74]\n// reserved\t\t\t\t\t\t\t0x03\t\t\n#define\tAT91C_CSD_DSR_I_S \t\t\t12\t\t// [76:76]\n#define\tAT91C_CSD_DSR_I_M \t\t\t0x01\n#define\tAT91C_CSD_RD_B_MIS_S \t\t13\t\t// [77:77]\n#define\tAT91C_CSD_RD_B_MIS_M \t\t0x01\n#define\tAT91C_CSD_WR_B_MIS_S \t\t14\t\t// [78:78]\n#define\tAT91C_CSD_WR_B_MIS_M \t\t0x01\n#define\tAT91C_CSD_RD_B_PAR_S \t\t15\t\t// [79:79]\n#define\tAT91C_CSD_RD_B_PAR_M \t\t0x01\n#define\tAT91C_CSD_RD_B_LEN_S \t\t16\t\t// [83:80]\n#define\tAT91C_CSD_RD_B_LEN_M \t\t0x0F\n#define\tAT91C_CSD_CCC_S\t \t\t\t20\t\t// [95:84]\n#define\tAT91C_CSD_CCC_M \t\t\t0x0FFF\n\n// Fourth Response INT <=> CSD[0] : bits 96 to 127\n#define\tAT91C_CSD_TRANS_SPEED_S \t0\t\t// [103:96]\n#define\tAT91C_CSD_TRANS_SPEED_M \t0xFF\n#define\tAT91C_CSD_NSAC_S \t\t\t8\t\t// [111:104]\n#define\tAT91C_CSD_NSAC_M \t\t\t0xFF\n#define\tAT91C_CSD_TAAC_S \t\t\t16\t\t// [119:112]\n#define\tAT91C_CSD_TAAC_M \t\t\t0xFF\n//\treserved\t\t\t\t\t\t24\t\t// [121:120]\n//\treserved\t\t\t\t\t\t0x03\n#define\tAT91C_CSD_MMC_SPEC_VERS_S\t26\t\t// [125:122]\treserved for MMC compatibility\n#define\tAT91C_CSD_MMC_SPEC_VERS_M\t0x0F\n#define\tAT91C_CSD_STRUCT_S\t\t\t30\t\t// [127:126]\n#define\tAT91C_CSD_STRUCT_M \t\t\t0x03\n\n/////////////////////////////////////////////////////////////////////////////////////////////////////\n\n#endif\n\n"
  },
  {
    "path": "target/linux/at91/image/dfboot/src/include/AT91RM9200.h",
    "content": "// ----------------------------------------------------------------------------\n//          ATMEL Microcontroller Software Support  -  ROUSSET  -\n// ----------------------------------------------------------------------------\n//  The software is delivered \"AS IS\" without warranty or condition of any\n//  kind, either express, implied or statutory. This includes without\n//  limitation any warranty or condition with respect to merchantability or\n//  fitness for any particular purpose, or against the infringements of\n//  intellectual property rights of others.\n// ----------------------------------------------------------------------------\n// File Name           : AT91RM9200.h\n// Object              : AT91RM9200 definitions\n// Generated           : AT91 SW Application Group  11/19/2003 (17:20:50)\n// \n// CVS Reference       : /AT91RM9200.pl/1.16/Fri Feb 07 10:29:51 2003//\n// CVS Reference       : /SYS_AT91RM9200.pl/1.2/Fri Jan 17 12:44:37 2003//\n// CVS Reference       : /MC_1760A.pl/1.1/Fri Aug 23 14:38:22 2002//\n// CVS Reference       : /AIC_1796B.pl/1.1.1.1/Fri Jun 28 09:36:47 2002//\n// CVS Reference       : /PMC_2636A.pl/1.1.1.1/Fri Jun 28 09:36:48 2002//\n// CVS Reference       : /ST_1763B.pl/1.1/Fri Aug 23 14:41:42 2002//\n// CVS Reference       : /RTC_1245D.pl/1.2/Fri Jan 31 12:19:06 2003//\n// CVS Reference       : /PIO_1725D.pl/1.1.1.1/Fri Jun 28 09:36:47 2002//\n// CVS Reference       : /DBGU_1754A.pl/1.4/Fri Jan 31 12:18:24 2003//\n// CVS Reference       : /UDP_1765B.pl/1.3/Fri Aug 02 14:45:38 2002//\n// CVS Reference       : /MCI_1764A.pl/1.2/Thu Nov 14 17:48:24 2002//\n// CVS Reference       : /US_1739C.pl/1.2/Fri Jul 12 07:49:25 2002//\n// CVS Reference       : /SPI_AT91RMxxxx.pl/1.3/Tue Nov 26 10:20:29 2002//\n// CVS Reference       : /SSC_1762A.pl/1.2/Fri Nov 08 13:26:39 2002//\n// CVS Reference       : /TC_1753B.pl/1.2/Fri Jan 31 12:19:55 2003//\n// CVS Reference       : /TWI_1761B.pl/1.4/Fri Feb 07 10:30:07 2003//\n// CVS Reference       : /PDC_1734B.pl/1.2/Thu Nov 21 16:38:23 2002//\n// CVS Reference       : /UHP_xxxxA.pl/1.1/Mon Jul 22 12:21:58 2002//\n// CVS Reference       : /EMAC_1794A.pl/1.4/Fri Jan 17 12:11:54 2003//\n// CVS Reference       : /EBI_1759B.pl/1.10/Fri Jan 17 12:44:29 2003//\n// CVS Reference       : /SMC_1783A.pl/1.3/Thu Oct 31 14:38:17 2002//\n// CVS Reference       : /SDRC_1758B.pl/1.2/Thu Oct 03 13:04:41 2002//\n// CVS Reference       : /BFC_1757B.pl/1.3/Thu Oct 31 14:38:00 2002//\n// ----------------------------------------------------------------------------\n\n#ifndef AT91RM9200_H\n#define AT91RM9200_H\n\ntypedef volatile unsigned int AT91_REG;// Hardware register definition\n\n// *****************************************************************************\n//              SOFTWARE API DEFINITION  FOR System Peripherals\n// *****************************************************************************\ntypedef struct _AT91S_SYS {\n\tAT91_REG\t AIC_SMR[32]; \t// Source Mode Register\n\tAT91_REG\t AIC_SVR[32]; \t// Source Vector Register\n\tAT91_REG\t AIC_IVR; \t// IRQ Vector Register\n\tAT91_REG\t AIC_FVR; \t// FIQ Vector Register\n\tAT91_REG\t AIC_ISR; \t// Interrupt Status Register\n\tAT91_REG\t AIC_IPR; \t// Interrupt Pending Register\n\tAT91_REG\t AIC_IMR; \t// Interrupt Mask Register\n\tAT91_REG\t AIC_CISR; \t// Core Interrupt Status Register\n\tAT91_REG\t Reserved0[2]; \t// \n\tAT91_REG\t AIC_IECR; \t// Interrupt Enable Command Register\n\tAT91_REG\t AIC_IDCR; \t// Interrupt Disable Command Register\n\tAT91_REG\t AIC_ICCR; \t// Interrupt Clear Command Register\n\tAT91_REG\t AIC_ISCR; \t// Interrupt Set Command Register\n\tAT91_REG\t AIC_EOICR; \t// End of Interrupt Command Register\n\tAT91_REG\t AIC_SPU; \t// Spurious Vector Register\n\tAT91_REG\t AIC_DCR; \t// Debug Control Register (Protect)\n\tAT91_REG\t Reserved1[1]; \t// \n\tAT91_REG\t AIC_FFER; \t// Fast Forcing Enable Register\n\tAT91_REG\t AIC_FFDR; \t// Fast Forcing Disable Register\n\tAT91_REG\t AIC_FFSR; \t// Fast Forcing Status Register\n\tAT91_REG\t Reserved2[45]; \t// \n\tAT91_REG\t DBGU_CR; \t// Control Register\n\tAT91_REG\t DBGU_MR; \t// Mode Register\n\tAT91_REG\t DBGU_IER; \t// Interrupt Enable Register\n\tAT91_REG\t DBGU_IDR; \t// Interrupt Disable Register\n\tAT91_REG\t DBGU_IMR; \t// Interrupt Mask Register\n\tAT91_REG\t DBGU_CSR; \t// Channel Status Register\n\tAT91_REG\t DBGU_RHR; \t// Receiver Holding Register\n\tAT91_REG\t DBGU_THR; \t// Transmitter Holding Register\n\tAT91_REG\t DBGU_BRGR; \t// Baud Rate Generator Register\n\tAT91_REG\t Reserved3[7]; \t// \n\tAT91_REG\t DBGU_C1R; \t// Chip ID1 Register\n\tAT91_REG\t DBGU_C2R; \t// Chip ID2 Register\n\tAT91_REG\t DBGU_FNTR; \t// Force NTRST Register\n\tAT91_REG\t Reserved4[45]; \t// \n\tAT91_REG\t DBGU_RPR; \t// Receive Pointer Register\n\tAT91_REG\t DBGU_RCR; \t// Receive Counter Register\n\tAT91_REG\t DBGU_TPR; \t// Transmit Pointer Register\n\tAT91_REG\t DBGU_TCR; \t// Transmit Counter Register\n\tAT91_REG\t DBGU_RNPR; \t// Receive Next Pointer Register\n\tAT91_REG\t DBGU_RNCR; \t// Receive Next Counter Register\n\tAT91_REG\t DBGU_TNPR; \t// Transmit Next Pointer Register\n\tAT91_REG\t DBGU_TNCR; \t// Transmit Next Counter Register\n\tAT91_REG\t DBGU_PTCR; \t// PDC Transfer Control Register\n\tAT91_REG\t DBGU_PTSR; \t// PDC Transfer Status Register\n\tAT91_REG\t Reserved5[54]; \t// \n\tAT91_REG\t PIOA_PER; \t// PIO Enable Register\n\tAT91_REG\t PIOA_PDR; \t// PIO Disable Register\n\tAT91_REG\t PIOA_PSR; \t// PIO Status Register\n\tAT91_REG\t Reserved6[1]; \t// \n\tAT91_REG\t PIOA_OER; \t// Output Enable Register\n\tAT91_REG\t PIOA_ODR; \t// Output Disable Registerr\n\tAT91_REG\t PIOA_OSR; \t// Output Status Register\n\tAT91_REG\t Reserved7[1]; \t// \n\tAT91_REG\t PIOA_IFER; \t// Input Filter Enable Register\n\tAT91_REG\t PIOA_IFDR; \t// Input Filter Disable Register\n\tAT91_REG\t PIOA_IFSR; \t// Input Filter Status Register\n\tAT91_REG\t Reserved8[1]; \t// \n\tAT91_REG\t PIOA_SODR; \t// Set Output Data Register\n\tAT91_REG\t PIOA_CODR; \t// Clear Output Data Register\n\tAT91_REG\t PIOA_ODSR; \t// Output Data Status Register\n\tAT91_REG\t PIOA_PDSR; \t// Pin Data Status Register\n\tAT91_REG\t PIOA_IER; \t// Interrupt Enable Register\n\tAT91_REG\t PIOA_IDR; \t// Interrupt Disable Register\n\tAT91_REG\t PIOA_IMR; \t// Interrupt Mask Register\n\tAT91_REG\t PIOA_ISR; \t// Interrupt Status Register\n\tAT91_REG\t PIOA_MDER; \t// Multi-driver Enable Register\n\tAT91_REG\t PIOA_MDDR; \t// Multi-driver Disable Register\n\tAT91_REG\t PIOA_MDSR; \t// Multi-driver Status Register\n\tAT91_REG\t Reserved9[1]; \t// \n\tAT91_REG\t PIOA_PPUDR; \t// Pull-up Disable Register\n\tAT91_REG\t PIOA_PPUER; \t// Pull-up Enable Register\n\tAT91_REG\t PIOA_PPUSR; \t// Pad Pull-up Status Register\n\tAT91_REG\t Reserved10[1]; \t// \n\tAT91_REG\t PIOA_ASR; \t// Select A Register\n\tAT91_REG\t PIOA_BSR; \t// Select B Register\n\tAT91_REG\t PIOA_ABSR; \t// AB Select Status Register\n\tAT91_REG\t Reserved11[9]; \t// \n\tAT91_REG\t PIOA_OWER; \t// Output Write Enable Register\n\tAT91_REG\t PIOA_OWDR; \t// Output Write Disable Register\n\tAT91_REG\t PIOA_OWSR; \t// Output Write Status Register\n\tAT91_REG\t Reserved12[85]; \t// \n\tAT91_REG\t PIOB_PER; \t// PIO Enable Register\n\tAT91_REG\t PIOB_PDR; \t// PIO Disable Register\n\tAT91_REG\t PIOB_PSR; \t// PIO Status Register\n\tAT91_REG\t Reserved13[1]; \t// \n\tAT91_REG\t PIOB_OER; \t// Output Enable Register\n\tAT91_REG\t PIOB_ODR; \t// Output Disable Registerr\n\tAT91_REG\t PIOB_OSR; \t// Output Status Register\n\tAT91_REG\t Reserved14[1]; \t// \n\tAT91_REG\t PIOB_IFER; \t// Input Filter Enable Register\n\tAT91_REG\t PIOB_IFDR; \t// Input Filter Disable Register\n\tAT91_REG\t PIOB_IFSR; \t// Input Filter Status Register\n\tAT91_REG\t Reserved15[1]; \t// \n\tAT91_REG\t PIOB_SODR; \t// Set Output Data Register\n\tAT91_REG\t PIOB_CODR; \t// Clear Output Data Register\n\tAT91_REG\t PIOB_ODSR; \t// Output Data Status Register\n\tAT91_REG\t PIOB_PDSR; \t// Pin Data Status Register\n\tAT91_REG\t PIOB_IER; \t// Interrupt Enable Register\n\tAT91_REG\t PIOB_IDR; \t// Interrupt Disable Register\n\tAT91_REG\t PIOB_IMR; \t// Interrupt Mask Register\n\tAT91_REG\t PIOB_ISR; \t// Interrupt Status Register\n\tAT91_REG\t PIOB_MDER; \t// Multi-driver Enable Register\n\tAT91_REG\t PIOB_MDDR; \t// Multi-driver Disable Register\n\tAT91_REG\t PIOB_MDSR; \t// Multi-driver Status Register\n\tAT91_REG\t Reserved16[1]; \t// \n\tAT91_REG\t PIOB_PPUDR; \t// Pull-up Disable Register\n\tAT91_REG\t PIOB_PPUER; \t// Pull-up Enable Register\n\tAT91_REG\t PIOB_PPUSR; \t// Pad Pull-up Status Register\n\tAT91_REG\t Reserved17[1]; \t// \n\tAT91_REG\t PIOB_ASR; \t// Select A Register\n\tAT91_REG\t PIOB_BSR; \t// Select B Register\n\tAT91_REG\t PIOB_ABSR; \t// AB Select Status Register\n\tAT91_REG\t Reserved18[9]; \t// \n\tAT91_REG\t PIOB_OWER; \t// Output Write Enable Register\n\tAT91_REG\t PIOB_OWDR; \t// Output Write Disable Register\n\tAT91_REG\t PIOB_OWSR; \t// Output Write Status Register\n\tAT91_REG\t Reserved19[85]; \t// \n\tAT91_REG\t PIOC_PER; \t// PIO Enable Register\n\tAT91_REG\t PIOC_PDR; \t// PIO Disable Register\n\tAT91_REG\t PIOC_PSR; \t// PIO Status Register\n\tAT91_REG\t Reserved20[1]; \t// \n\tAT91_REG\t PIOC_OER; \t// Output Enable Register\n\tAT91_REG\t PIOC_ODR; \t// Output Disable Registerr\n\tAT91_REG\t PIOC_OSR; \t// Output Status Register\n\tAT91_REG\t Reserved21[1]; \t// \n\tAT91_REG\t PIOC_IFER; \t// Input Filter Enable Register\n\tAT91_REG\t PIOC_IFDR; \t// Input Filter Disable Register\n\tAT91_REG\t PIOC_IFSR; \t// Input Filter Status Register\n\tAT91_REG\t Reserved22[1]; \t// \n\tAT91_REG\t PIOC_SODR; \t// Set Output Data Register\n\tAT91_REG\t PIOC_CODR; \t// Clear Output Data Register\n\tAT91_REG\t PIOC_ODSR; \t// Output Data Status Register\n\tAT91_REG\t PIOC_PDSR; \t// Pin Data Status Register\n\tAT91_REG\t PIOC_IER; \t// Interrupt Enable Register\n\tAT91_REG\t PIOC_IDR; \t// Interrupt Disable Register\n\tAT91_REG\t PIOC_IMR; \t// Interrupt Mask Register\n\tAT91_REG\t PIOC_ISR; \t// Interrupt Status Register\n\tAT91_REG\t PIOC_MDER; \t// Multi-driver Enable Register\n\tAT91_REG\t PIOC_MDDR; \t// Multi-driver Disable Register\n\tAT91_REG\t PIOC_MDSR; \t// Multi-driver Status Register\n\tAT91_REG\t Reserved23[1]; \t// \n\tAT91_REG\t PIOC_PPUDR; \t// Pull-up Disable Register\n\tAT91_REG\t PIOC_PPUER; \t// Pull-up Enable Register\n\tAT91_REG\t PIOC_PPUSR; \t// Pad Pull-up Status Register\n\tAT91_REG\t Reserved24[1]; \t// \n\tAT91_REG\t PIOC_ASR; \t// Select A Register\n\tAT91_REG\t PIOC_BSR; \t// Select B Register\n\tAT91_REG\t PIOC_ABSR; \t// AB Select Status Register\n\tAT91_REG\t Reserved25[9]; \t// \n\tAT91_REG\t PIOC_OWER; \t// Output Write Enable Register\n\tAT91_REG\t PIOC_OWDR; \t// Output Write Disable Register\n\tAT91_REG\t PIOC_OWSR; \t// Output Write Status Register\n\tAT91_REG\t Reserved26[85]; \t// \n\tAT91_REG\t PIOD_PER; \t// PIO Enable Register\n\tAT91_REG\t PIOD_PDR; \t// PIO Disable Register\n\tAT91_REG\t PIOD_PSR; \t// PIO Status Register\n\tAT91_REG\t Reserved27[1]; \t// \n\tAT91_REG\t PIOD_OER; \t// Output Enable Register\n\tAT91_REG\t PIOD_ODR; \t// Output Disable Registerr\n\tAT91_REG\t PIOD_OSR; \t// Output Status Register\n\tAT91_REG\t Reserved28[1]; \t// \n\tAT91_REG\t PIOD_IFER; \t// Input Filter Enable Register\n\tAT91_REG\t PIOD_IFDR; \t// Input Filter Disable Register\n\tAT91_REG\t PIOD_IFSR; \t// Input Filter Status Register\n\tAT91_REG\t Reserved29[1]; \t// \n\tAT91_REG\t PIOD_SODR; \t// Set Output Data Register\n\tAT91_REG\t PIOD_CODR; \t// Clear Output Data Register\n\tAT91_REG\t PIOD_ODSR; \t// Output Data Status Register\n\tAT91_REG\t PIOD_PDSR; \t// Pin Data Status Register\n\tAT91_REG\t PIOD_IER; \t// Interrupt Enable Register\n\tAT91_REG\t PIOD_IDR; \t// Interrupt Disable Register\n\tAT91_REG\t PIOD_IMR; \t// Interrupt Mask Register\n\tAT91_REG\t PIOD_ISR; \t// Interrupt Status Register\n\tAT91_REG\t PIOD_MDER; \t// Multi-driver Enable Register\n\tAT91_REG\t PIOD_MDDR; \t// Multi-driver Disable Register\n\tAT91_REG\t PIOD_MDSR; \t// Multi-driver Status Register\n\tAT91_REG\t Reserved30[1]; \t// \n\tAT91_REG\t PIOD_PPUDR; \t// Pull-up Disable Register\n\tAT91_REG\t PIOD_PPUER; \t// Pull-up Enable Register\n\tAT91_REG\t PIOD_PPUSR; \t// Pad Pull-up Status Register\n\tAT91_REG\t Reserved31[1]; \t// \n\tAT91_REG\t PIOD_ASR; \t// Select A Register\n\tAT91_REG\t PIOD_BSR; \t// Select B Register\n\tAT91_REG\t PIOD_ABSR; \t// AB Select Status Register\n\tAT91_REG\t Reserved32[9]; \t// \n\tAT91_REG\t PIOD_OWER; \t// Output Write Enable Register\n\tAT91_REG\t PIOD_OWDR; \t// Output Write Disable Register\n\tAT91_REG\t PIOD_OWSR; \t// Output Write Status Register\n\tAT91_REG\t Reserved33[85]; \t// \n\tAT91_REG\t PMC_SCER; \t// System Clock Enable Register\n\tAT91_REG\t PMC_SCDR; \t// System Clock Disable Register\n\tAT91_REG\t PMC_SCSR; \t// System Clock Status Register\n\tAT91_REG\t Reserved34[1]; \t// \n\tAT91_REG\t PMC_PCER; \t// Peripheral Clock Enable Register\n\tAT91_REG\t PMC_PCDR; \t// Peripheral Clock Disable Register\n\tAT91_REG\t PMC_PCSR; \t// Peripheral Clock Status Register\n\tAT91_REG\t Reserved35[1]; \t// \n\tAT91_REG\t CKGR_MOR; \t// Main Oscillator Register\n\tAT91_REG\t CKGR_MCFR; \t// Main Clock  Frequency Register\n\tAT91_REG\t CKGR_PLLAR; \t// PLL A Register\n\tAT91_REG\t CKGR_PLLBR; \t// PLL B Register\n\tAT91_REG\t PMC_MCKR; \t// Master Clock Register\n\tAT91_REG\t Reserved36[3]; \t// \n\tAT91_REG\t PMC_PCKR[8]; \t// Programmable Clock Register\n\tAT91_REG\t PMC_IER; \t// Interrupt Enable Register\n\tAT91_REG\t PMC_IDR; \t// Interrupt Disable Register\n\tAT91_REG\t PMC_SR; \t// Status Register\n\tAT91_REG\t PMC_IMR; \t// Interrupt Mask Register\n\tAT91_REG\t Reserved37[36]; \t// \n\tAT91_REG\t ST_CR; \t// Control Register\n\tAT91_REG\t ST_PIMR; \t// Period Interval Mode Register\n\tAT91_REG\t ST_WDMR; \t// Watchdog Mode Register\n\tAT91_REG\t ST_RTMR; \t// Real-time Mode Register\n\tAT91_REG\t ST_SR; \t// Status Register\n\tAT91_REG\t ST_IER; \t// Interrupt Enable Register\n\tAT91_REG\t ST_IDR; \t// Interrupt Disable Register\n\tAT91_REG\t ST_IMR; \t// Interrupt Mask Register\n\tAT91_REG\t ST_RTAR; \t// Real-time Alarm Register\n\tAT91_REG\t ST_CRTR; \t// Current Real-time Register\n\tAT91_REG\t Reserved38[54]; \t// \n\tAT91_REG\t RTC_CR; \t// Control Register\n\tAT91_REG\t RTC_MR; \t// Mode Register\n\tAT91_REG\t RTC_TIMR; \t// Time Register\n\tAT91_REG\t RTC_CALR; \t// Calendar Register\n\tAT91_REG\t RTC_TIMALR; \t// Time Alarm Register\n\tAT91_REG\t RTC_CALALR; \t// Calendar Alarm Register\n\tAT91_REG\t RTC_SR; \t// Status Register\n\tAT91_REG\t RTC_SCCR; \t// Status Clear Command Register\n\tAT91_REG\t RTC_IER; \t// Interrupt Enable Register\n\tAT91_REG\t RTC_IDR; \t// Interrupt Disable Register\n\tAT91_REG\t RTC_IMR; \t// Interrupt Mask Register\n\tAT91_REG\t RTC_VER; \t// Valid Entry Register\n\tAT91_REG\t Reserved39[52]; \t// \n\tAT91_REG\t MC_RCR; \t// MC Remap Control Register\n\tAT91_REG\t MC_ASR; \t// MC Abort Status Register\n\tAT91_REG\t MC_AASR; \t// MC Abort Address Status Register\n\tAT91_REG\t Reserved40[1]; \t// \n\tAT91_REG\t MC_PUIA[16]; \t// MC Protection Unit Area\n\tAT91_REG\t MC_PUP; \t// MC Protection Unit Peripherals\n\tAT91_REG\t MC_PUER; \t// MC Protection Unit Enable Register\n\tAT91_REG\t Reserved41[2]; \t// \n\tAT91_REG\t EBI_CSA; \t// Chip Select Assignment Register\n\tAT91_REG\t EBI_CFGR; \t// Configuration Register\n\tAT91_REG\t Reserved42[2]; \t// \n\tAT91_REG\t EBI_SMC2_CSR[8]; \t// SMC2 Chip Select Register\n\tAT91_REG\t EBI_SDRC_MR; \t// SDRAM Controller Mode Register\n\tAT91_REG\t EBI_SDRC_TR; \t// SDRAM Controller Refresh Timer Register\n\tAT91_REG\t EBI_SDRC_CR; \t// SDRAM Controller Configuration Register\n\tAT91_REG\t EBI_SDRC_SRR; \t// SDRAM Controller Self Refresh Register\n\tAT91_REG\t EBI_SDRC_LPR; \t// SDRAM Controller Low Power Register\n\tAT91_REG\t EBI_SDRC_IER; \t// SDRAM Controller Interrupt Enable Register\n\tAT91_REG\t EBI_SDRC_IDR; \t// SDRAM Controller Interrupt Disable Register\n\tAT91_REG\t EBI_SDRC_IMR; \t// SDRAM Controller Interrupt Mask Register\n\tAT91_REG\t EBI_SDRC_ISR; \t// SDRAM Controller Interrupt Mask Register\n\tAT91_REG\t Reserved43[3]; \t// \n\tAT91_REG\t EBI_BFC_MR; \t// BFC Mode Register\n} AT91S_SYS, *AT91PS_SYS;\n\n\n// *****************************************************************************\n//              SOFTWARE API DEFINITION  FOR Memory Controller Interface\n// *****************************************************************************\ntypedef struct _AT91S_MC {\n\tAT91_REG\t MC_RCR; \t// MC Remap Control Register\n\tAT91_REG\t MC_ASR; \t// MC Abort Status Register\n\tAT91_REG\t MC_AASR; \t// MC Abort Address Status Register\n\tAT91_REG\t Reserved0[1]; \t// \n\tAT91_REG\t MC_PUIA[16]; \t// MC Protection Unit Area\n\tAT91_REG\t MC_PUP; \t// MC Protection Unit Peripherals\n\tAT91_REG\t MC_PUER; \t// MC Protection Unit Enable Register\n} AT91S_MC, *AT91PS_MC;\n\n// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- \n#define AT91C_MC_RCB          ((unsigned int) 0x1 <<  0) // (MC) Remap Command Bit\n// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- \n#define AT91C_MC_UNDADD       ((unsigned int) 0x1 <<  0) // (MC) Undefined Addess Abort Status\n#define AT91C_MC_MISADD       ((unsigned int) 0x1 <<  1) // (MC) Misaligned Addess Abort Status\n#define AT91C_MC_MPU          ((unsigned int) 0x1 <<  2) // (MC) Memory protection Unit Abort Status\n#define AT91C_MC_ABTSZ        ((unsigned int) 0x3 <<  8) // (MC) Abort Size Status\n#define \tAT91C_MC_ABTSZ_BYTE                 ((unsigned int) 0x0 <<  8) // (MC) Byte\n#define \tAT91C_MC_ABTSZ_HWORD                ((unsigned int) 0x1 <<  8) // (MC) Half-word\n#define \tAT91C_MC_ABTSZ_WORD                 ((unsigned int) 0x2 <<  8) // (MC) Word\n#define AT91C_MC_ABTTYP       ((unsigned int) 0x3 << 10) // (MC) Abort Type Status\n#define \tAT91C_MC_ABTTYP_DATAR                ((unsigned int) 0x0 << 10) // (MC) Data Read\n#define \tAT91C_MC_ABTTYP_DATAW                ((unsigned int) 0x1 << 10) // (MC) Data Write\n#define \tAT91C_MC_ABTTYP_FETCH                ((unsigned int) 0x2 << 10) // (MC) Code Fetch\n#define AT91C_MC_MST0         ((unsigned int) 0x1 << 16) // (MC) Master 0 Abort Source\n#define AT91C_MC_MST1         ((unsigned int) 0x1 << 17) // (MC) Master 1 Abort Source\n#define AT91C_MC_SVMST0       ((unsigned int) 0x1 << 24) // (MC) Saved Master 0 Abort Source\n#define AT91C_MC_SVMST1       ((unsigned int) 0x1 << 25) // (MC) Saved Master 1 Abort Source\n// -------- MC_PUIA : (MC Offset: 0x10) MC Protection Unit Area -------- \n#define AT91C_MC_PROT         ((unsigned int) 0x3 <<  0) // (MC) Protection\n#define \tAT91C_MC_PROT_PNAUNA               ((unsigned int) 0x0) // (MC) Privilege: No Access, User: No Access\n#define \tAT91C_MC_PROT_PRWUNA               ((unsigned int) 0x1) // (MC) Privilege: Read/Write, User: No Access\n#define \tAT91C_MC_PROT_PRWURO               ((unsigned int) 0x2) // (MC) Privilege: Read/Write, User: Read Only\n#define \tAT91C_MC_PROT_PRWURW               ((unsigned int) 0x3) // (MC) Privilege: Read/Write, User: Read/Write\n#define AT91C_MC_SIZE         ((unsigned int) 0xF <<  4) // (MC) Internal Area Size\n#define \tAT91C_MC_SIZE_1KB                  ((unsigned int) 0x0 <<  4) // (MC) Area size 1KByte\n#define \tAT91C_MC_SIZE_2KB                  ((unsigned int) 0x1 <<  4) // (MC) Area size 2KByte\n#define \tAT91C_MC_SIZE_4KB                  ((unsigned int) 0x2 <<  4) // (MC) Area size 4KByte\n#define \tAT91C_MC_SIZE_8KB                  ((unsigned int) 0x3 <<  4) // (MC) Area size 8KByte\n#define \tAT91C_MC_SIZE_16KB                 ((unsigned int) 0x4 <<  4) // (MC) Area size 16KByte\n#define \tAT91C_MC_SIZE_32KB                 ((unsigned int) 0x5 <<  4) // (MC) Area size 32KByte\n#define \tAT91C_MC_SIZE_64KB                 ((unsigned int) 0x6 <<  4) // (MC) Area size 64KByte\n#define \tAT91C_MC_SIZE_128KB                ((unsigned int) 0x7 <<  4) // (MC) Area size 128KByte\n#define \tAT91C_MC_SIZE_256KB                ((unsigned int) 0x8 <<  4) // (MC) Area size 256KByte\n#define \tAT91C_MC_SIZE_512KB                ((unsigned int) 0x9 <<  4) // (MC) Area size 512KByte\n#define \tAT91C_MC_SIZE_1MB                  ((unsigned int) 0xA <<  4) // (MC) Area size 1MByte\n#define \tAT91C_MC_SIZE_2MB                  ((unsigned int) 0xB <<  4) // (MC) Area size 2MByte\n#define \tAT91C_MC_SIZE_4MB                  ((unsigned int) 0xC <<  4) // (MC) Area size 4MByte\n#define \tAT91C_MC_SIZE_8MB                  ((unsigned int) 0xD <<  4) // (MC) Area size 8MByte\n#define \tAT91C_MC_SIZE_16MB                 ((unsigned int) 0xE <<  4) // (MC) Area size 16MByte\n#define \tAT91C_MC_SIZE_64MB                 ((unsigned int) 0xF <<  4) // (MC) Area size 64MByte\n#define AT91C_MC_BA           ((unsigned int) 0x3FFFF << 10) // (MC) Internal Area Base Address\n// -------- MC_PUP : (MC Offset: 0x50) MC Protection Unit Peripheral -------- \n// -------- MC_PUER : (MC Offset: 0x54) MC Protection Unit Area -------- \n#define AT91C_MC_PUEB         ((unsigned int) 0x1 <<  0) // (MC) Protection Unit enable Bit\n\n// *****************************************************************************\n//              SOFTWARE API DEFINITION  FOR Real-time Clock Alarm and Parallel Load Interface\n// *****************************************************************************\ntypedef struct _AT91S_RTC {\n\tAT91_REG\t RTC_CR; \t// Control Register\n\tAT91_REG\t RTC_MR; \t// Mode Register\n\tAT91_REG\t RTC_TIMR; \t// Time Register\n\tAT91_REG\t RTC_CALR; \t// Calendar Register\n\tAT91_REG\t RTC_TIMALR; \t// Time Alarm Register\n\tAT91_REG\t RTC_CALALR; \t// Calendar Alarm Register\n\tAT91_REG\t RTC_SR; \t// Status Register\n\tAT91_REG\t RTC_SCCR; \t// Status Clear Command Register\n\tAT91_REG\t RTC_IER; \t// Interrupt Enable Register\n\tAT91_REG\t RTC_IDR; \t// Interrupt Disable Register\n\tAT91_REG\t RTC_IMR; \t// Interrupt Mask Register\n\tAT91_REG\t RTC_VER; \t// Valid Entry Register\n} AT91S_RTC, *AT91PS_RTC;\n\n// -------- RTC_CR : (RTC Offset: 0x0) RTC Control Register -------- \n#define AT91C_RTC_UPDTIM      ((unsigned int) 0x1 <<  0) // (RTC) Update Request Time Register\n#define AT91C_RTC_UPDCAL      ((unsigned int) 0x1 <<  1) // (RTC) Update Request Calendar Register\n#define AT91C_RTC_TIMEVSEL    ((unsigned int) 0x3 <<  8) // (RTC) Time Event Selection\n#define \tAT91C_RTC_TIMEVSEL_MINUTE               ((unsigned int) 0x0 <<  8) // (RTC) Minute change.\n#define \tAT91C_RTC_TIMEVSEL_HOUR                 ((unsigned int) 0x1 <<  8) // (RTC) Hour change.\n#define \tAT91C_RTC_TIMEVSEL_DAY24                ((unsigned int) 0x2 <<  8) // (RTC) Every day at midnight.\n#define \tAT91C_RTC_TIMEVSEL_DAY12                ((unsigned int) 0x3 <<  8) // (RTC) Every day at noon.\n#define AT91C_RTC_CALEVSEL    ((unsigned int) 0x3 << 16) // (RTC) Calendar Event Selection\n#define \tAT91C_RTC_CALEVSEL_WEEK                 ((unsigned int) 0x0 << 16) // (RTC) Week change (every Monday at time 00:00:00).\n#define \tAT91C_RTC_CALEVSEL_MONTH                ((unsigned int) 0x1 << 16) // (RTC) Month change (every 01 of each month at time 00:00:00).\n#define \tAT91C_RTC_CALEVSEL_YEAR                 ((unsigned int) 0x2 << 16) // (RTC) Year change (every January 1 at time 00:00:00).\n// -------- RTC_MR : (RTC Offset: 0x4) RTC Mode Register -------- \n#define AT91C_RTC_HRMOD       ((unsigned int) 0x1 <<  0) // (RTC) 12-24 hour Mode\n// -------- RTC_TIMR : (RTC Offset: 0x8) RTC Time Register -------- \n#define AT91C_RTC_SEC         ((unsigned int) 0x7F <<  0) // (RTC) Current Second\n#define AT91C_RTC_MIN         ((unsigned int) 0x7F <<  8) // (RTC) Current Minute\n#define AT91C_RTC_HOUR        ((unsigned int) 0x1F << 16) // (RTC) Current Hour\n#define AT91C_RTC_AMPM        ((unsigned int) 0x1 << 22) // (RTC) Ante Meridiem, Post Meridiem Indicator\n// -------- RTC_CALR : (RTC Offset: 0xc) RTC Calendar Register -------- \n#define AT91C_RTC_CENT        ((unsigned int) 0x3F <<  0) // (RTC) Current Century\n#define AT91C_RTC_YEAR        ((unsigned int) 0xFF <<  8) // (RTC) Current Year\n#define AT91C_RTC_MONTH       ((unsigned int) 0x1F << 16) // (RTC) Current Month\n#define AT91C_RTC_DAY         ((unsigned int) 0x7 << 21) // (RTC) Current Day\n#define AT91C_RTC_DATE        ((unsigned int) 0x3F << 24) // (RTC) Current Date\n// -------- RTC_TIMALR : (RTC Offset: 0x10) RTC Time Alarm Register -------- \n#define AT91C_RTC_SECEN       ((unsigned int) 0x1 <<  7) // (RTC) Second Alarm Enable\n#define AT91C_RTC_MINEN       ((unsigned int) 0x1 << 15) // (RTC) Minute Alarm\n#define AT91C_RTC_HOUREN      ((unsigned int) 0x1 << 23) // (RTC) Current Hour\n// -------- RTC_CALALR : (RTC Offset: 0x14) RTC Calendar Alarm Register -------- \n#define AT91C_RTC_MONTHEN     ((unsigned int) 0x1 << 23) // (RTC) Month Alarm Enable\n#define AT91C_RTC_DATEEN      ((unsigned int) 0x1 << 31) // (RTC) Date Alarm Enable\n// -------- RTC_SR : (RTC Offset: 0x18) RTC Status Register -------- \n#define AT91C_RTC_ACKUPD      ((unsigned int) 0x1 <<  0) // (RTC) Acknowledge for Update\n#define AT91C_RTC_ALARM       ((unsigned int) 0x1 <<  1) // (RTC) Alarm Flag\n#define AT91C_RTC_SECEV       ((unsigned int) 0x1 <<  2) // (RTC) Second Event\n#define AT91C_RTC_TIMEV       ((unsigned int) 0x1 <<  3) // (RTC) Time Event\n#define AT91C_RTC_CALEV       ((unsigned int) 0x1 <<  4) // (RTC) Calendar event\n// -------- RTC_SCCR : (RTC Offset: 0x1c) RTC Status Clear Command Register -------- \n// -------- RTC_IER : (RTC Offset: 0x20) RTC Interrupt Enable Register -------- \n// -------- RTC_IDR : (RTC Offset: 0x24) RTC Interrupt Disable Register -------- \n// -------- RTC_IMR : (RTC Offset: 0x28) RTC Interrupt Mask Register -------- \n// -------- RTC_VER : (RTC Offset: 0x2c) RTC Valid Entry Register -------- \n#define AT91C_RTC_NVTIM       ((unsigned int) 0x1 <<  0) // (RTC) Non valid Time\n#define AT91C_RTC_NVCAL       ((unsigned int) 0x1 <<  1) // (RTC) Non valid Calendar\n#define AT91C_RTC_NVTIMALR    ((unsigned int) 0x1 <<  2) // (RTC) Non valid time Alarm\n#define AT91C_RTC_NVCALALR    ((unsigned int) 0x1 <<  3) // (RTC) Nonvalid Calendar Alarm\n\n// *****************************************************************************\n//              SOFTWARE API DEFINITION  FOR System Timer Interface\n// *****************************************************************************\ntypedef struct _AT91S_ST {\n\tAT91_REG\t ST_CR; \t// Control Register\n\tAT91_REG\t ST_PIMR; \t// Period Interval Mode Register\n\tAT91_REG\t ST_WDMR; \t// Watchdog Mode Register\n\tAT91_REG\t ST_RTMR; \t// Real-time Mode Register\n\tAT91_REG\t ST_SR; \t// Status Register\n\tAT91_REG\t ST_IER; \t// Interrupt Enable Register\n\tAT91_REG\t ST_IDR; \t// Interrupt Disable Register\n\tAT91_REG\t ST_IMR; \t// Interrupt Mask Register\n\tAT91_REG\t ST_RTAR; \t// Real-time Alarm Register\n\tAT91_REG\t ST_CRTR; \t// Current Real-time Register\n} AT91S_ST, *AT91PS_ST;\n\n// -------- ST_CR : (ST Offset: 0x0) System Timer Control Register -------- \n#define AT91C_ST_WDRST        ((unsigned int) 0x1 <<  0) // (ST) Watchdog Timer Restart\n// -------- ST_PIMR : (ST Offset: 0x4) System Timer Period Interval Mode Register -------- \n#define AT91C_ST_PIV          ((unsigned int) 0xFFFF <<  0) // (ST) Watchdog Timer Restart\n// -------- ST_WDMR : (ST Offset: 0x8) System Timer Watchdog Mode Register -------- \n#define AT91C_ST_WDV          ((unsigned int) 0xFFFF <<  0) // (ST) Watchdog Timer Restart\n#define AT91C_ST_RSTEN        ((unsigned int) 0x1 << 16) // (ST) Reset Enable\n#define AT91C_ST_EXTEN        ((unsigned int) 0x1 << 17) // (ST) External Signal Assertion Enable\n// -------- ST_RTMR : (ST Offset: 0xc) System Timer Real-time Mode Register -------- \n#define AT91C_ST_RTPRES       ((unsigned int) 0xFFFF <<  0) // (ST) Real-time Timer Prescaler Value\n// -------- ST_SR : (ST Offset: 0x10) System Timer Status Register -------- \n#define AT91C_ST_PITS         ((unsigned int) 0x1 <<  0) // (ST) Period Interval Timer Interrupt\n#define AT91C_ST_WDOVF        ((unsigned int) 0x1 <<  1) // (ST) Watchdog Overflow\n#define AT91C_ST_RTTINC       ((unsigned int) 0x1 <<  2) // (ST) Real-time Timer Increment\n#define AT91C_ST_ALMS         ((unsigned int) 0x1 <<  3) // (ST) Alarm Status\n// -------- ST_IER : (ST Offset: 0x14) System Timer Interrupt Enable Register -------- \n// -------- ST_IDR : (ST Offset: 0x18) System Timer Interrupt Disable Register -------- \n// -------- ST_IMR : (ST Offset: 0x1c) System Timer Interrupt Mask Register -------- \n// -------- ST_RTAR : (ST Offset: 0x20) System Timer Real-time Alarm Register -------- \n#define AT91C_ST_ALMV         ((unsigned int) 0xFFFFF <<  0) // (ST) Alarm Value Value\n// -------- ST_CRTR : (ST Offset: 0x24) System Timer Current Real-time Register -------- \n#define AT91C_ST_CRTV         ((unsigned int) 0xFFFFF <<  0) // (ST) Current Real-time Value\n\n// *****************************************************************************\n//              SOFTWARE API DEFINITION  FOR Power Management Controler\n// *****************************************************************************\ntypedef struct _AT91S_PMC {\n\tAT91_REG\t PMC_SCER; \t// System Clock Enable Register\n\tAT91_REG\t PMC_SCDR; \t// System Clock Disable Register\n\tAT91_REG\t PMC_SCSR; \t// System Clock Status Register\n\tAT91_REG\t Reserved0[1]; \t// \n\tAT91_REG\t PMC_PCER; \t// Peripheral Clock Enable Register\n\tAT91_REG\t PMC_PCDR; \t// Peripheral Clock Disable Register\n\tAT91_REG\t PMC_PCSR; \t// Peripheral Clock Status Register\n\tAT91_REG\t Reserved1[5]; \t// \n\tAT91_REG\t PMC_MCKR; \t// Master Clock Register\n\tAT91_REG\t Reserved2[3]; \t// \n\tAT91_REG\t PMC_PCKR[8]; \t// Programmable Clock Register\n\tAT91_REG\t PMC_IER; \t// Interrupt Enable Register\n\tAT91_REG\t PMC_IDR; \t// Interrupt Disable Register\n\tAT91_REG\t PMC_SR; \t// Status Register\n\tAT91_REG\t PMC_IMR; \t// Interrupt Mask Register\n} AT91S_PMC, *AT91PS_PMC;\n\n// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- \n#define AT91C_PMC_PCK         ((unsigned int) 0x1 <<  0) // (PMC) Processor Clock\n#define AT91C_PMC_UDP         ((unsigned int) 0x1 <<  1) // (PMC) USB Device Port Clock\n#define AT91C_PMC_MCKUDP      ((unsigned int) 0x1 <<  2) // (PMC) USB Device Port Master Clock Automatic Disable on Suspend\n#define AT91C_PMC_UHP         ((unsigned int) 0x1 <<  4) // (PMC) USB Host Port Clock\n#define AT91C_PMC_PCK0        ((unsigned int) 0x1 <<  8) // (PMC) Programmable Clock Output\n#define AT91C_PMC_PCK1        ((unsigned int) 0x1 <<  9) // (PMC) Programmable Clock Output\n#define AT91C_PMC_PCK2        ((unsigned int) 0x1 << 10) // (PMC) Programmable Clock Output\n#define AT91C_PMC_PCK3        ((unsigned int) 0x1 << 11) // (PMC) Programmable Clock Output\n#define AT91C_PMC_PCK4        ((unsigned int) 0x1 << 12) // (PMC) Programmable Clock Output\n#define AT91C_PMC_PCK5        ((unsigned int) 0x1 << 13) // (PMC) Programmable Clock Output\n#define AT91C_PMC_PCK6        ((unsigned int) 0x1 << 14) // (PMC) Programmable Clock Output\n#define AT91C_PMC_PCK7        ((unsigned int) 0x1 << 15) // (PMC) Programmable Clock Output\n// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- \n// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- \n// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- \n#define AT91C_PMC_CSS         ((unsigned int) 0x3 <<  0) // (PMC) Programmable Clock Selection\n#define \tAT91C_PMC_CSS_SLOW_CLK             ((unsigned int) 0x0) // (PMC) Slow Clock is selected\n#define \tAT91C_PMC_CSS_MAIN_CLK             ((unsigned int) 0x1) // (PMC) Main Clock is selected\n#define \tAT91C_PMC_CSS_PLLA_CLK             ((unsigned int) 0x2) // (PMC) Clock from PLL A is selected\n#define \tAT91C_PMC_CSS_PLLB_CLK             ((unsigned int) 0x3) // (PMC) Clock from PLL B is selected\n#define AT91C_PMC_PRES        ((unsigned int) 0x7 <<  2) // (PMC) Programmable Clock Prescaler\n#define \tAT91C_PMC_PRES_CLK                  ((unsigned int) 0x0 <<  2) // (PMC) Selected clock\n#define \tAT91C_PMC_PRES_CLK_2                ((unsigned int) 0x1 <<  2) // (PMC) Selected clock divided by 2\n#define \tAT91C_PMC_PRES_CLK_4                ((unsigned int) 0x2 <<  2) // (PMC) Selected clock divided by 4\n#define \tAT91C_PMC_PRES_CLK_8                ((unsigned int) 0x3 <<  2) // (PMC) Selected clock divided by 8\n#define \tAT91C_PMC_PRES_CLK_16               ((unsigned int) 0x4 <<  2) // (PMC) Selected clock divided by 16\n#define \tAT91C_PMC_PRES_CLK_32               ((unsigned int) 0x5 <<  2) // (PMC) Selected clock divided by 32\n#define \tAT91C_PMC_PRES_CLK_64               ((unsigned int) 0x6 <<  2) // (PMC) Selected clock divided by 64\n#define AT91C_PMC_MDIV        ((unsigned int) 0x3 <<  8) // (PMC) Master Clock Division\n#define \tAT91C_PMC_MDIV_1                    ((unsigned int) 0x0 <<  8) // (PMC) The master clock and the processor clock are the same\n#define \tAT91C_PMC_MDIV_2                    ((unsigned int) 0x1 <<  8) // (PMC) The processor clock is twice as fast as the master clock\n#define \tAT91C_PMC_MDIV_3                    ((unsigned int) 0x2 <<  8) // (PMC) The processor clock is three times faster than the master clock\n#define \tAT91C_PMC_MDIV_4                    ((unsigned int) 0x3 <<  8) // (PMC) The processor clock is four times faster than the master clock\n// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- \n// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- \n#define AT91C_PMC_MOSCS       ((unsigned int) 0x1 <<  0) // (PMC) MOSC Status/Enable/Disable/Mask\n#define AT91C_PMC_LOCKA       ((unsigned int) 0x1 <<  1) // (PMC) PLL A Status/Enable/Disable/Mask\n#define AT91C_PMC_LOCKB       ((unsigned int) 0x1 <<  2) // (PMC) PLL B Status/Enable/Disable/Mask\n#define AT91C_PMC_MCKRDY      ((unsigned int) 0x1 <<  3) // (PMC) MCK_RDY Status/Enable/Disable/Mask\n#define AT91C_PMC_PCK0RDY     ((unsigned int) 0x1 <<  8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask\n#define AT91C_PMC_PCK1RDY     ((unsigned int) 0x1 <<  9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask\n#define AT91C_PMC_PCK2RDY     ((unsigned int) 0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask\n#define AT91C_PMC_PCK3RDY     ((unsigned int) 0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask\n#define AT91C_PMC_PCK4RDY     ((unsigned int) 0x1 << 12) // (PMC) PCK4_RDY Status/Enable/Disable/Mask\n#define AT91C_PMC_PCK5RDY     ((unsigned int) 0x1 << 13) // (PMC) PCK5_RDY Status/Enable/Disable/Mask\n#define AT91C_PMC_PCK6RDY     ((unsigned int) 0x1 << 14) // (PMC) PCK6_RDY Status/Enable/Disable/Mask\n#define AT91C_PMC_PCK7RDY     ((unsigned int) 0x1 << 15) // (PMC) PCK7_RDY Status/Enable/Disable/Mask\n// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- \n// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- \n// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- \n\n// *****************************************************************************\n//              SOFTWARE API DEFINITION  FOR Clock Generator Controler\n// *****************************************************************************\ntypedef struct _AT91S_CKGR {\n\tAT91_REG\t CKGR_MOR; \t// Main Oscillator Register\n\tAT91_REG\t CKGR_MCFR; \t// Main Clock  Frequency Register\n\tAT91_REG\t CKGR_PLLAR; \t// PLL A Register\n\tAT91_REG\t CKGR_PLLBR; \t// PLL B Register\n} AT91S_CKGR, *AT91PS_CKGR;\n\n// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- \n#define AT91C_CKGR_MOSCEN     ((unsigned int) 0x1 <<  0) // (CKGR) Main Oscillator Enable\n#define AT91C_CKGR_OSCTEST    ((unsigned int) 0x1 <<  1) // (CKGR) Oscillator Test\n#define AT91C_CKGR_OSCOUNT    ((unsigned int) 0xFF <<  8) // (CKGR) Main Oscillator Start-up Time\n// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- \n#define AT91C_CKGR_MAINF      ((unsigned int) 0xFFFF <<  0) // (CKGR) Main Clock Frequency\n#define AT91C_CKGR_MAINRDY    ((unsigned int) 0x1 << 16) // (CKGR) Main Clock Ready\n// -------- CKGR_PLLAR : (CKGR Offset: 0x8) PLL A Register -------- \n#define AT91C_CKGR_DIVA       ((unsigned int) 0xFF <<  0) // (CKGR) Divider Selected\n#define \tAT91C_CKGR_DIVA_0                    ((unsigned int) 0x0) // (CKGR) Divider output is 0\n#define \tAT91C_CKGR_DIVA_BYPASS               ((unsigned int) 0x1) // (CKGR) Divider is bypassed\n#define AT91C_CKGR_PLLACOUNT  ((unsigned int) 0x3F <<  8) // (CKGR) PLL A Counter\n#define AT91C_CKGR_OUTA       ((unsigned int) 0x3 << 14) // (CKGR) PLL A Output Frequency Range\n#define \tAT91C_CKGR_OUTA_0                    ((unsigned int) 0x0 << 14) // (CKGR) Please refer to the PLLA datasheet\n#define \tAT91C_CKGR_OUTA_1                    ((unsigned int) 0x1 << 14) // (CKGR) Please refer to the PLLA datasheet\n#define \tAT91C_CKGR_OUTA_2                    ((unsigned int) 0x2 << 14) // (CKGR) Please refer to the PLLA datasheet\n#define \tAT91C_CKGR_OUTA_3                    ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLLA datasheet\n#define AT91C_CKGR_MULA       ((unsigned int) 0x7FF << 16) // (CKGR) PLL A Multiplier\n#define AT91C_CKGR_SRCA       ((unsigned int) 0x1 << 29) // (CKGR) PLL A Source\n// -------- CKGR_PLLBR : (CKGR Offset: 0xc) PLL B Register -------- \n#define AT91C_CKGR_DIVB       ((unsigned int) 0xFF <<  0) // (CKGR) Divider Selected\n#define \tAT91C_CKGR_DIVB_0                    ((unsigned int) 0x0) // (CKGR) Divider output is 0\n#define \tAT91C_CKGR_DIVB_BYPASS               ((unsigned int) 0x1) // (CKGR) Divider is bypassed\n#define AT91C_CKGR_PLLBCOUNT  ((unsigned int) 0x3F <<  8) // (CKGR) PLL B Counter\n#define AT91C_CKGR_OUTB       ((unsigned int) 0x3 << 14) // (CKGR) PLL B Output Frequency Range\n#define \tAT91C_CKGR_OUTB_0                    ((unsigned int) 0x0 << 14) // (CKGR) Please refer to the PLLB datasheet\n#define \tAT91C_CKGR_OUTB_1                    ((unsigned int) 0x1 << 14) // (CKGR) Please refer to the PLLB datasheet\n#define \tAT91C_CKGR_OUTB_2                    ((unsigned int) 0x2 << 14) // (CKGR) Please refer to the PLLB datasheet\n#define \tAT91C_CKGR_OUTB_3                    ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLLB datasheet\n#define AT91C_CKGR_MULB       ((unsigned int) 0x7FF << 16) // (CKGR) PLL B Multiplier\n#define AT91C_CKGR_USB_96M    ((unsigned int) 0x1 << 28) // (CKGR) Divider for USB Ports\n#define AT91C_CKGR_USB_PLL    ((unsigned int) 0x1 << 29) // (CKGR) PLL Use\n\n// *****************************************************************************\n//              SOFTWARE API DEFINITION  FOR Parallel Input Output Controler\n// *****************************************************************************\ntypedef struct _AT91S_PIO {\n\tAT91_REG\t PIO_PER; \t// PIO Enable Register\n\tAT91_REG\t PIO_PDR; \t// PIO Disable Register\n\tAT91_REG\t PIO_PSR; \t// PIO Status Register\n\tAT91_REG\t Reserved0[1]; \t// \n\tAT91_REG\t PIO_OER; \t// Output Enable Register\n\tAT91_REG\t PIO_ODR; \t// Output Disable Registerr\n\tAT91_REG\t PIO_OSR; \t// Output Status Register\n\tAT91_REG\t Reserved1[1]; \t// \n\tAT91_REG\t PIO_IFER; \t// Input Filter Enable Register\n\tAT91_REG\t PIO_IFDR; \t// Input Filter Disable Register\n\tAT91_REG\t PIO_IFSR; \t// Input Filter Status Register\n\tAT91_REG\t Reserved2[1]; \t// \n\tAT91_REG\t PIO_SODR; \t// Set Output Data Register\n\tAT91_REG\t PIO_CODR; \t// Clear Output Data Register\n\tAT91_REG\t PIO_ODSR; \t// Output Data Status Register\n\tAT91_REG\t PIO_PDSR; \t// Pin Data Status Register\n\tAT91_REG\t PIO_IER; \t// Interrupt Enable Register\n\tAT91_REG\t PIO_IDR; \t// Interrupt Disable Register\n\tAT91_REG\t PIO_IMR; \t// Interrupt Mask Register\n\tAT91_REG\t PIO_ISR; \t// Interrupt Status Register\n\tAT91_REG\t PIO_MDER; \t// Multi-driver Enable Register\n\tAT91_REG\t PIO_MDDR; \t// Multi-driver Disable Register\n\tAT91_REG\t PIO_MDSR; \t// Multi-driver Status Register\n\tAT91_REG\t Reserved3[1]; \t// \n\tAT91_REG\t PIO_PPUDR; \t// Pull-up Disable Register\n\tAT91_REG\t PIO_PPUER; \t// Pull-up Enable Register\n\tAT91_REG\t PIO_PPUSR; \t// Pad Pull-up Status Register\n\tAT91_REG\t Reserved4[1]; \t// \n\tAT91_REG\t PIO_ASR; \t// Select A Register\n\tAT91_REG\t PIO_BSR; \t// Select B Register\n\tAT91_REG\t PIO_ABSR; \t// AB Select Status Register\n\tAT91_REG\t Reserved5[9]; \t// \n\tAT91_REG\t PIO_OWER; \t// Output Write Enable Register\n\tAT91_REG\t PIO_OWDR; \t// Output Write Disable Register\n\tAT91_REG\t PIO_OWSR; \t// Output Write Status Register\n} AT91S_PIO, *AT91PS_PIO;\n\n\n// *****************************************************************************\n//              SOFTWARE API DEFINITION  FOR Debug Unit\n// *****************************************************************************\ntypedef struct _AT91S_DBGU {\n\tAT91_REG\t DBGU_CR; \t// Control Register\n\tAT91_REG\t DBGU_MR; \t// Mode Register\n\tAT91_REG\t DBGU_IER; \t// Interrupt Enable Register\n\tAT91_REG\t DBGU_IDR; \t// Interrupt Disable Register\n\tAT91_REG\t DBGU_IMR; \t// Interrupt Mask Register\n\tAT91_REG\t DBGU_CSR; \t// Channel Status Register\n\tAT91_REG\t DBGU_RHR; \t// Receiver Holding Register\n\tAT91_REG\t DBGU_THR; \t// Transmitter Holding Register\n\tAT91_REG\t DBGU_BRGR; \t// Baud Rate Generator Register\n\tAT91_REG\t Reserved0[7]; \t// \n\tAT91_REG\t DBGU_C1R; \t// Chip ID1 Register\n\tAT91_REG\t DBGU_C2R; \t// Chip ID2 Register\n\tAT91_REG\t DBGU_FNTR; \t// Force NTRST Register\n\tAT91_REG\t Reserved1[45]; \t// \n\tAT91_REG\t DBGU_RPR; \t// Receive Pointer Register\n\tAT91_REG\t DBGU_RCR; \t// Receive Counter Register\n\tAT91_REG\t DBGU_TPR; \t// Transmit Pointer Register\n\tAT91_REG\t DBGU_TCR; \t// Transmit Counter Register\n\tAT91_REG\t DBGU_RNPR; \t// Receive Next Pointer Register\n\tAT91_REG\t DBGU_RNCR; \t// Receive Next Counter Register\n\tAT91_REG\t DBGU_TNPR; \t// Transmit Next Pointer Register\n\tAT91_REG\t DBGU_TNCR; \t// Transmit Next Counter Register\n\tAT91_REG\t DBGU_PTCR; \t// PDC Transfer Control Register\n\tAT91_REG\t DBGU_PTSR; \t// PDC Transfer Status Register\n} AT91S_DBGU, *AT91PS_DBGU;\n\n// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- \n#define AT91C_US_RSTRX        ((unsigned int) 0x1 <<  2) // (DBGU) Reset Receiver\n#define AT91C_US_RSTTX        ((unsigned int) 0x1 <<  3) // (DBGU) Reset Transmitter\n#define AT91C_US_RXEN         ((unsigned int) 0x1 <<  4) // (DBGU) Receiver Enable\n#define AT91C_US_RXDIS        ((unsigned int) 0x1 <<  5) // (DBGU) Receiver Disable\n#define AT91C_US_TXEN         ((unsigned int) 0x1 <<  6) // (DBGU) Transmitter Enable\n#define AT91C_US_TXDIS        ((unsigned int) 0x1 <<  7) // (DBGU) Transmitter Disable\n// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- \n#define AT91C_US_PAR          ((unsigned int) 0x7 <<  9) // (DBGU) Parity type\n#define \tAT91C_US_PAR_EVEN                 ((unsigned int) 0x0 <<  9) // (DBGU) Even Parity\n#define \tAT91C_US_PAR_ODD                  ((unsigned int) 0x1 <<  9) // (DBGU) Odd Parity\n#define \tAT91C_US_PAR_SPACE                ((unsigned int) 0x2 <<  9) // (DBGU) Parity forced to 0 (Space)\n#define \tAT91C_US_PAR_MARK                 ((unsigned int) 0x3 <<  9) // (DBGU) Parity forced to 1 (Mark)\n#define \tAT91C_US_PAR_NONE                 ((unsigned int) 0x4 <<  9) // (DBGU) No Parity\n#define \tAT91C_US_PAR_MULTI_DROP           ((unsigned int) 0x6 <<  9) // (DBGU) Multi-drop mode\n#define AT91C_US_CHMODE       ((unsigned int) 0x3 << 14) // (DBGU) Channel Mode\n#define \tAT91C_US_CHMODE_NORMAL               ((unsigned int) 0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.\n#define \tAT91C_US_CHMODE_AUTO                 ((unsigned int) 0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.\n#define \tAT91C_US_CHMODE_LOCAL                ((unsigned int) 0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.\n#define \tAT91C_US_CHMODE_REMOTE               ((unsigned int) 0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.\n// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- \n#define AT91C_US_RXRDY        ((unsigned int) 0x1 <<  0) // (DBGU) RXRDY Interrupt\n#define AT91C_US_TXRDY        ((unsigned int) 0x1 <<  1) // (DBGU) TXRDY Interrupt\n#define AT91C_US_ENDRX        ((unsigned int) 0x1 <<  3) // (DBGU) End of Receive Transfer Interrupt\n#define AT91C_US_ENDTX        ((unsigned int) 0x1 <<  4) // (DBGU) End of Transmit Interrupt\n#define AT91C_US_OVRE         ((unsigned int) 0x1 <<  5) // (DBGU) Overrun Interrupt\n#define AT91C_US_FRAME        ((unsigned int) 0x1 <<  6) // (DBGU) Framing Error Interrupt\n#define AT91C_US_PARE         ((unsigned int) 0x1 <<  7) // (DBGU) Parity Error Interrupt\n#define AT91C_US_TXEMPTY      ((unsigned int) 0x1 <<  9) // (DBGU) TXEMPTY Interrupt\n#define AT91C_US_TXBUFE       ((unsigned int) 0x1 << 11) // (DBGU) TXBUFE Interrupt\n#define AT91C_US_RXBUFF       ((unsigned int) 0x1 << 12) // (DBGU) RXBUFF Interrupt\n#define AT91C_US_COMM_TX      ((unsigned int) 0x1 << 30) // (DBGU) COMM_TX Interrupt\n#define AT91C_US_COMM_RX      ((unsigned int) 0x1 << 31) // (DBGU) COMM_RX Interrupt\n// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- \n// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- \n// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- \n// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- \n#define AT91C_US_FORCE_NTRST  ((unsigned int) 0x1 <<  0) // (DBGU) Force NTRST in JTAG\n\n// *****************************************************************************\n//              SOFTWARE API DEFINITION  FOR Peripheral Data Controller\n// *****************************************************************************\ntypedef struct _AT91S_PDC {\n\tAT91_REG\t PDC_RPR; \t// Receive Pointer Register\n\tAT91_REG\t PDC_RCR; \t// Receive Counter Register\n\tAT91_REG\t PDC_TPR; \t// Transmit Pointer Register\n\tAT91_REG\t PDC_TCR; \t// Transmit Counter Register\n\tAT91_REG\t PDC_RNPR; \t// Receive Next Pointer Register\n\tAT91_REG\t PDC_RNCR; \t// Receive Next Counter Register\n\tAT91_REG\t PDC_TNPR; \t// Transmit Next Pointer Register\n\tAT91_REG\t PDC_TNCR; \t// Transmit Next Counter Register\n\tAT91_REG\t PDC_PTCR; \t// PDC Transfer Control Register\n\tAT91_REG\t PDC_PTSR; \t// PDC Transfer Status Register\n} AT91S_PDC, *AT91PS_PDC;\n\n// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- \n#define AT91C_PDC_RXTEN       ((unsigned int) 0x1 <<  0) // (PDC) Receiver Transfer Enable\n#define AT91C_PDC_RXTDIS      ((unsigned int) 0x1 <<  1) // (PDC) Receiver Transfer Disable\n#define AT91C_PDC_TXTEN       ((unsigned int) 0x1 <<  8) // (PDC) Transmitter Transfer Enable\n#define AT91C_PDC_TXTDIS      ((unsigned int) 0x1 <<  9) // (PDC) Transmitter Transfer Disable\n// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- \n\n// *****************************************************************************\n//              SOFTWARE API DEFINITION  FOR Advanced Interrupt Controller\n// *****************************************************************************\ntypedef struct _AT91S_AIC {\n\tAT91_REG\t AIC_SMR[32]; \t// Source Mode Register\n\tAT91_REG\t AIC_SVR[32]; \t// Source Vector Register\n\tAT91_REG\t AIC_IVR; \t// IRQ Vector Register\n\tAT91_REG\t AIC_FVR; \t// FIQ Vector Register\n\tAT91_REG\t AIC_ISR; \t// Interrupt Status Register\n\tAT91_REG\t AIC_IPR; \t// Interrupt Pending Register\n\tAT91_REG\t AIC_IMR; \t// Interrupt Mask Register\n\tAT91_REG\t AIC_CISR; \t// Core Interrupt Status Register\n\tAT91_REG\t Reserved0[2]; \t// \n\tAT91_REG\t AIC_IECR; \t// Interrupt Enable Command Register\n\tAT91_REG\t AIC_IDCR; \t// Interrupt Disable Command Register\n\tAT91_REG\t AIC_ICCR; \t// Interrupt Clear Command Register\n\tAT91_REG\t AIC_ISCR; \t// Interrupt Set Command Register\n\tAT91_REG\t AIC_EOICR; \t// End of Interrupt Command Register\n\tAT91_REG\t AIC_SPU; \t// Spurious Vector Register\n\tAT91_REG\t AIC_DCR; \t// Debug Control Register (Protect)\n\tAT91_REG\t Reserved1[1]; \t// \n\tAT91_REG\t AIC_FFER; \t// Fast Forcing Enable Register\n\tAT91_REG\t AIC_FFDR; \t// Fast Forcing Disable Register\n\tAT91_REG\t AIC_FFSR; \t// Fast Forcing Status Register\n} AT91S_AIC, *AT91PS_AIC;\n\n// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- \n#define AT91C_AIC_PRIOR       ((unsigned int) 0x7 <<  0) // (AIC) Priority Level\n#define \tAT91C_AIC_PRIOR_LOWEST               ((unsigned int) 0x0) // (AIC) Lowest priority level\n#define \tAT91C_AIC_PRIOR_HIGHEST              ((unsigned int) 0x7) // (AIC) Highest priority level\n#define AT91C_AIC_SRCTYPE     ((unsigned int) 0x3 <<  5) // (AIC) Interrupt Source Type\n#define \tAT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE  ((unsigned int) 0x0 <<  5) // (AIC) Internal Sources Code Label Level Sensitive\n#define \tAT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED   ((unsigned int) 0x1 <<  5) // (AIC) Internal Sources Code Label Edge triggered\n#define \tAT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL       ((unsigned int) 0x2 <<  5) // (AIC) External Sources Code Label High-level Sensitive\n#define \tAT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE    ((unsigned int) 0x3 <<  5) // (AIC) External Sources Code Label Positive Edge triggered\n// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- \n#define AT91C_AIC_NFIQ        ((unsigned int) 0x1 <<  0) // (AIC) NFIQ Status\n#define AT91C_AIC_NIRQ        ((unsigned int) 0x1 <<  1) // (AIC) NIRQ Status\n// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- \n#define AT91C_AIC_DCR_PROT    ((unsigned int) 0x1 <<  0) // (AIC) Protection Mode\n#define AT91C_AIC_DCR_GMSK    ((unsigned int) 0x1 <<  1) // (AIC) General Mask\n\n// *****************************************************************************\n//              SOFTWARE API DEFINITION  FOR Serial Parallel Interface\n// *****************************************************************************\ntypedef struct _AT91S_SPI {\n\tAT91_REG\t SPI_CR; \t// Control Register\n\tAT91_REG\t SPI_MR; \t// Mode Register\n\tAT91_REG\t SPI_RDR; \t// Receive Data Register\n\tAT91_REG\t SPI_TDR; \t// Transmit Data Register\n\tAT91_REG\t SPI_SR; \t// Status Register\n\tAT91_REG\t SPI_IER; \t// Interrupt Enable Register\n\tAT91_REG\t SPI_IDR; \t// Interrupt Disable Register\n\tAT91_REG\t SPI_IMR; \t// Interrupt Mask Register\n\tAT91_REG\t Reserved0[4]; \t// \n\tAT91_REG\t SPI_CSR[4]; \t// Chip Select Register\n\tAT91_REG\t Reserved1[48]; \t// \n\tAT91_REG\t SPI_RPR; \t// Receive Pointer Register\n\tAT91_REG\t SPI_RCR; \t// Receive Counter Register\n\tAT91_REG\t SPI_TPR; \t// Transmit Pointer Register\n\tAT91_REG\t SPI_TCR; \t// Transmit Counter Register\n\tAT91_REG\t SPI_RNPR; \t// Receive Next Pointer Register\n\tAT91_REG\t SPI_RNCR; \t// Receive Next Counter Register\n\tAT91_REG\t SPI_TNPR; \t// Transmit Next Pointer Register\n\tAT91_REG\t SPI_TNCR; \t// Transmit Next Counter Register\n\tAT91_REG\t SPI_PTCR; \t// PDC Transfer Control Register\n\tAT91_REG\t SPI_PTSR; \t// PDC Transfer Status Register\n} AT91S_SPI, *AT91PS_SPI;\n\n// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- \n#define AT91C_SPI_SPIEN       ((unsigned int) 0x1 <<  0) // (SPI) SPI Enable\n#define AT91C_SPI_SPIDIS      ((unsigned int) 0x1 <<  1) // (SPI) SPI Disable\n#define AT91C_SPI_SWRST       ((unsigned int) 0x1 <<  7) // (SPI) SPI Software reset\n// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- \n#define AT91C_SPI_MSTR        ((unsigned int) 0x1 <<  0) // (SPI) Master/Slave Mode\n#define AT91C_SPI_PS          ((unsigned int) 0x1 <<  1) // (SPI) Peripheral Select\n#define \tAT91C_SPI_PS_FIXED                ((unsigned int) 0x0 <<  1) // (SPI) Fixed Peripheral Select\n#define \tAT91C_SPI_PS_VARIABLE             ((unsigned int) 0x1 <<  1) // (SPI) Variable Peripheral Select\n#define AT91C_SPI_PCSDEC      ((unsigned int) 0x1 <<  2) // (SPI) Chip Select Decode\n#define AT91C_SPI_DIV32       ((unsigned int) 0x1 <<  3) // (SPI) Clock Selection\n#define AT91C_SPI_MODFDIS     ((unsigned int) 0x1 <<  4) // (SPI) Mode Fault Detection\n#define AT91C_SPI_LLB         ((unsigned int) 0x1 <<  7) // (SPI) Clock Selection\n#define AT91C_SPI_PCS         ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select\n#define AT91C_SPI_DLYBCS      ((unsigned int) 0xFF << 24) // (SPI) Delay Between Chip Selects\n// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- \n#define AT91C_SPI_RD          ((unsigned int) 0xFFFF <<  0) // (SPI) Receive Data\n#define AT91C_SPI_RPCS        ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status\n// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- \n#define AT91C_SPI_TD          ((unsigned int) 0xFFFF <<  0) // (SPI) Transmit Data\n#define AT91C_SPI_TPCS        ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status\n// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- \n#define AT91C_SPI_RDRF        ((unsigned int) 0x1 <<  0) // (SPI) Receive Data Register Full\n#define AT91C_SPI_TDRE        ((unsigned int) 0x1 <<  1) // (SPI) Transmit Data Register Empty\n#define AT91C_SPI_MODF        ((unsigned int) 0x1 <<  2) // (SPI) Mode Fault Error\n#define AT91C_SPI_OVRES       ((unsigned int) 0x1 <<  3) // (SPI) Overrun Error Status\n#define AT91C_SPI_SPENDRX     ((unsigned int) 0x1 <<  4) // (SPI) End of Receiver Transfer\n#define AT91C_SPI_SPENDTX     ((unsigned int) 0x1 <<  5) // (SPI) End of Receiver Transfer\n#define AT91C_SPI_RXBUFF      ((unsigned int) 0x1 <<  6) // (SPI) RXBUFF Interrupt\n#define AT91C_SPI_TXBUFE      ((unsigned int) 0x1 <<  7) // (SPI) TXBUFE Interrupt\n#define AT91C_SPI_SPIENS      ((unsigned int) 0x1 << 16) // (SPI) Enable Status\n// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- \n// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- \n// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- \n// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- \n#define AT91C_SPI_CPOL        ((unsigned int) 0x1 <<  0) // (SPI) Clock Polarity\n#define AT91C_SPI_NCPHA       ((unsigned int) 0x1 <<  1) // (SPI) Clock Phase\n#define AT91C_SPI_BITS        ((unsigned int) 0xF <<  4) // (SPI) Bits Per Transfer\n#define \tAT91C_SPI_BITS_8                    ((unsigned int) 0x0 <<  4) // (SPI) 8 Bits Per transfer\n#define \tAT91C_SPI_BITS_9                    ((unsigned int) 0x1 <<  4) // (SPI) 9 Bits Per transfer\n#define \tAT91C_SPI_BITS_10                   ((unsigned int) 0x2 <<  4) // (SPI) 10 Bits Per transfer\n#define \tAT91C_SPI_BITS_11                   ((unsigned int) 0x3 <<  4) // (SPI) 11 Bits Per transfer\n#define \tAT91C_SPI_BITS_12                   ((unsigned int) 0x4 <<  4) // (SPI) 12 Bits Per transfer\n#define \tAT91C_SPI_BITS_13                   ((unsigned int) 0x5 <<  4) // (SPI) 13 Bits Per transfer\n#define \tAT91C_SPI_BITS_14                   ((unsigned int) 0x6 <<  4) // (SPI) 14 Bits Per transfer\n#define \tAT91C_SPI_BITS_15                   ((unsigned int) 0x7 <<  4) // (SPI) 15 Bits Per transfer\n#define \tAT91C_SPI_BITS_16                   ((unsigned int) 0x8 <<  4) // (SPI) 16 Bits Per transfer\n#define AT91C_SPI_SCBR        ((unsigned int) 0xFF <<  8) // (SPI) Serial Clock Baud Rate\n#define AT91C_SPI_DLYBS       ((unsigned int) 0xFF << 16) // (SPI) Serial Clock Baud Rate\n#define AT91C_SPI_DLYBCT      ((unsigned int) 0xFF << 24) // (SPI) Delay Between Consecutive Transfers\n\n// *****************************************************************************\n//              SOFTWARE API DEFINITION  FOR Synchronous Serial Controller Interface\n// *****************************************************************************\ntypedef struct _AT91S_SSC {\n\tAT91_REG\t SSC_CR; \t// Control Register\n\tAT91_REG\t SSC_CMR; \t// Clock Mode Register\n\tAT91_REG\t Reserved0[2]; \t// \n\tAT91_REG\t SSC_RCMR; \t// Receive Clock ModeRegister\n\tAT91_REG\t SSC_RFMR; \t// Receive Frame Mode Register\n\tAT91_REG\t SSC_TCMR; \t// Transmit Clock Mode Register\n\tAT91_REG\t SSC_TFMR; \t// Transmit Frame Mode Register\n\tAT91_REG\t SSC_RHR; \t// Receive Holding Register\n\tAT91_REG\t SSC_THR; \t// Transmit Holding Register\n\tAT91_REG\t Reserved1[2]; \t// \n\tAT91_REG\t SSC_RSHR; \t// Receive Sync Holding Register\n\tAT91_REG\t SSC_TSHR; \t// Transmit Sync Holding Register\n\tAT91_REG\t SSC_RC0R; \t// Receive Compare 0 Register\n\tAT91_REG\t SSC_RC1R; \t// Receive Compare 1 Register\n\tAT91_REG\t SSC_SR; \t// Status Register\n\tAT91_REG\t SSC_IER; \t// Interrupt Enable Register\n\tAT91_REG\t SSC_IDR; \t// Interrupt Disable Register\n\tAT91_REG\t SSC_IMR; \t// Interrupt Mask Register\n\tAT91_REG\t Reserved2[44]; \t// \n\tAT91_REG\t SSC_RPR; \t// Receive Pointer Register\n\tAT91_REG\t SSC_RCR; \t// Receive Counter Register\n\tAT91_REG\t SSC_TPR; \t// Transmit Pointer Register\n\tAT91_REG\t SSC_TCR; \t// Transmit Counter Register\n\tAT91_REG\t SSC_RNPR; \t// Receive Next Pointer Register\n\tAT91_REG\t SSC_RNCR; \t// Receive Next Counter Register\n\tAT91_REG\t SSC_TNPR; \t// Transmit Next Pointer Register\n\tAT91_REG\t SSC_TNCR; \t// Transmit Next Counter Register\n\tAT91_REG\t SSC_PTCR; \t// PDC Transfer Control Register\n\tAT91_REG\t SSC_PTSR; \t// PDC Transfer Status Register\n} AT91S_SSC, *AT91PS_SSC;\n\n// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- \n#define AT91C_SSC_RXEN        ((unsigned int) 0x1 <<  0) // (SSC) Receive Enable\n#define AT91C_SSC_RXDIS       ((unsigned int) 0x1 <<  1) // (SSC) Receive Disable\n#define AT91C_SSC_TXEN        ((unsigned int) 0x1 <<  8) // (SSC) Transmit Enable\n#define AT91C_SSC_TXDIS       ((unsigned int) 0x1 <<  9) // (SSC) Transmit Disable\n#define AT91C_SSC_SWRST       ((unsigned int) 0x1 << 15) // (SSC) Software Reset\n// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- \n#define AT91C_SSC_CKS         ((unsigned int) 0x3 <<  0) // (SSC) Receive/Transmit Clock Selection\n#define \tAT91C_SSC_CKS_DIV                  ((unsigned int) 0x0) // (SSC) Divided Clock\n#define \tAT91C_SSC_CKS_TK                   ((unsigned int) 0x1) // (SSC) TK Clock signal\n#define \tAT91C_SSC_CKS_RK                   ((unsigned int) 0x2) // (SSC) RK pin\n#define AT91C_SSC_CKO         ((unsigned int) 0x7 <<  2) // (SSC) Receive/Transmit Clock Output Mode Selection\n#define \tAT91C_SSC_CKO_NONE                 ((unsigned int) 0x0 <<  2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only\n#define \tAT91C_SSC_CKO_CONTINOUS            ((unsigned int) 0x1 <<  2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output\n#define \tAT91C_SSC_CKO_DATA_TX              ((unsigned int) 0x2 <<  2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output\n#define AT91C_SSC_CKI         ((unsigned int) 0x1 <<  5) // (SSC) Receive/Transmit Clock Inversion\n#define AT91C_SSC_CKG         ((unsigned int) 0x3 <<  6) // (SSC) Receive/Transmit Clock Gating Selection\n#define \tAT91C_SSC_CKG_NONE                 ((unsigned int) 0x0 <<  6) // (SSC) Receive/Transmit Clock Gating: None, continuous clock\n#define \tAT91C_SSC_CKG_LOW                  ((unsigned int) 0x1 <<  6) // (SSC) Receive/Transmit Clock enabled only if RF Low\n#define \tAT91C_SSC_CKG_HIGH                 ((unsigned int) 0x2 <<  6) // (SSC) Receive/Transmit Clock enabled only if RF High\n#define AT91C_SSC_START       ((unsigned int) 0xF <<  8) // (SSC) Receive/Transmit Start Selection\n#define \tAT91C_SSC_START_CONTINOUS            ((unsigned int) 0x0 <<  8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.\n#define \tAT91C_SSC_START_TX                   ((unsigned int) 0x1 <<  8) // (SSC) Transmit/Receive start\n#define \tAT91C_SSC_START_LOW_RF               ((unsigned int) 0x2 <<  8) // (SSC) Detection of a low level on RF input\n#define \tAT91C_SSC_START_HIGH_RF              ((unsigned int) 0x3 <<  8) // (SSC) Detection of a high level on RF input\n#define \tAT91C_SSC_START_FALL_RF              ((unsigned int) 0x4 <<  8) // (SSC) Detection of a falling edge on RF input\n#define \tAT91C_SSC_START_RISE_RF              ((unsigned int) 0x5 <<  8) // (SSC) Detection of a rising edge on RF input\n#define \tAT91C_SSC_START_LEVEL_RF             ((unsigned int) 0x6 <<  8) // (SSC) Detection of any level change on RF input\n#define \tAT91C_SSC_START_EDGE_RF              ((unsigned int) 0x7 <<  8) // (SSC) Detection of any edge on RF input\n#define \tAT91C_SSC_START_0                    ((unsigned int) 0x8 <<  8) // (SSC) Compare 0\n#define AT91C_SSC_STOP        ((unsigned int) 0x1 << 12) // (SSC) Receive Stop Selection\n#define AT91C_SSC_STTOUT      ((unsigned int) 0x1 << 15) // (SSC) Receive/Transmit Start Output Selection\n#define AT91C_SSC_STTDLY      ((unsigned int) 0xFF << 16) // (SSC) Receive/Transmit Start Delay\n#define AT91C_SSC_PERIOD      ((unsigned int) 0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection\n// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- \n#define AT91C_SSC_DATLEN      ((unsigned int) 0x1F <<  0) // (SSC) Data Length\n#define AT91C_SSC_LOOP        ((unsigned int) 0x1 <<  5) // (SSC) Loop Mode\n#define AT91C_SSC_MSBF        ((unsigned int) 0x1 <<  7) // (SSC) Most Significant Bit First\n#define AT91C_SSC_DATNB       ((unsigned int) 0xF <<  8) // (SSC) Data Number per Frame\n#define AT91C_SSC_FSLEN       ((unsigned int) 0xF << 16) // (SSC) Receive/Transmit Frame Sync length\n#define AT91C_SSC_FSOS        ((unsigned int) 0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection\n#define \tAT91C_SSC_FSOS_NONE                 ((unsigned int) 0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only\n#define \tAT91C_SSC_FSOS_NEGATIVE             ((unsigned int) 0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse\n#define \tAT91C_SSC_FSOS_POSITIVE             ((unsigned int) 0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse\n#define \tAT91C_SSC_FSOS_LOW                  ((unsigned int) 0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer\n#define \tAT91C_SSC_FSOS_HIGH                 ((unsigned int) 0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer\n#define \tAT91C_SSC_FSOS_TOGGLE               ((unsigned int) 0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer\n#define AT91C_SSC_FSEDGE      ((unsigned int) 0x1 << 24) // (SSC) Frame Sync Edge Detection\n// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- \n// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- \n#define AT91C_SSC_DATDEF      ((unsigned int) 0x1 <<  5) // (SSC) Data Default Value\n#define AT91C_SSC_FSDEN       ((unsigned int) 0x1 << 23) // (SSC) Frame Sync Data Enable\n// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- \n#define AT91C_SSC_TXRDY       ((unsigned int) 0x1 <<  0) // (SSC) Transmit Ready\n#define AT91C_SSC_TXEMPTY     ((unsigned int) 0x1 <<  1) // (SSC) Transmit Empty\n#define AT91C_SSC_ENDTX       ((unsigned int) 0x1 <<  2) // (SSC) End Of Transmission\n#define AT91C_SSC_TXBUFE      ((unsigned int) 0x1 <<  3) // (SSC) Transmit Buffer Empty\n#define AT91C_SSC_RXRDY       ((unsigned int) 0x1 <<  4) // (SSC) Receive Ready\n#define AT91C_SSC_OVRUN       ((unsigned int) 0x1 <<  5) // (SSC) Receive Overrun\n#define AT91C_SSC_ENDRX       ((unsigned int) 0x1 <<  6) // (SSC) End of Reception\n#define AT91C_SSC_RXBUFF      ((unsigned int) 0x1 <<  7) // (SSC) Receive Buffer Full\n#define AT91C_SSC_CP0         ((unsigned int) 0x1 <<  8) // (SSC) Compare 0\n#define AT91C_SSC_CP1         ((unsigned int) 0x1 <<  9) // (SSC) Compare 1\n#define AT91C_SSC_TXSYN       ((unsigned int) 0x1 << 10) // (SSC) Transmit Sync\n#define AT91C_SSC_RXSYN       ((unsigned int) 0x1 << 11) // (SSC) Receive Sync\n#define AT91C_SSC_TXENA       ((unsigned int) 0x1 << 16) // (SSC) Transmit Enable\n#define AT91C_SSC_RXENA       ((unsigned int) 0x1 << 17) // (SSC) Receive Enable\n// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- \n// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- \n// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- \n\n// *****************************************************************************\n//              SOFTWARE API DEFINITION  FOR Usart\n// *****************************************************************************\ntypedef struct _AT91S_USART {\n\tAT91_REG\t US_CR; \t// Control Register\n\tAT91_REG\t US_MR; \t// Mode Register\n\tAT91_REG\t US_IER; \t// Interrupt Enable Register\n\tAT91_REG\t US_IDR; \t// Interrupt Disable Register\n\tAT91_REG\t US_IMR; \t// Interrupt Mask Register\n\tAT91_REG\t US_CSR; \t// Channel Status Register\n\tAT91_REG\t US_RHR; \t// Receiver Holding Register\n\tAT91_REG\t US_THR; \t// Transmitter Holding Register\n\tAT91_REG\t US_BRGR; \t// Baud Rate Generator Register\n\tAT91_REG\t US_RTOR; \t// Receiver Time-out Register\n\tAT91_REG\t US_TTGR; \t// Transmitter Time-guard Register\n\tAT91_REG\t Reserved0[5]; \t// \n\tAT91_REG\t US_FIDI; \t// FI_DI_Ratio Register\n\tAT91_REG\t US_NER; \t// Nb Errors Register\n\tAT91_REG\t US_XXR; \t// XON_XOFF Register\n\tAT91_REG\t US_IF; \t// IRDA_FILTER Register\n\tAT91_REG\t Reserved1[44]; \t// \n\tAT91_REG\t US_RPR; \t// Receive Pointer Register\n\tAT91_REG\t US_RCR; \t// Receive Counter Register\n\tAT91_REG\t US_TPR; \t// Transmit Pointer Register\n\tAT91_REG\t US_TCR; \t// Transmit Counter Register\n\tAT91_REG\t US_RNPR; \t// Receive Next Pointer Register\n\tAT91_REG\t US_RNCR; \t// Receive Next Counter Register\n\tAT91_REG\t US_TNPR; \t// Transmit Next Pointer Register\n\tAT91_REG\t US_TNCR; \t// Transmit Next Counter Register\n\tAT91_REG\t US_PTCR; \t// PDC Transfer Control Register\n\tAT91_REG\t US_PTSR; \t// PDC Transfer Status Register\n} AT91S_USART, *AT91PS_USART;\n\n// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- \n#define AT91C_US_RSTSTA       ((unsigned int) 0x1 <<  8) // (USART) Reset Status Bits\n#define AT91C_US_STTBRK       ((unsigned int) 0x1 <<  9) // (USART) Start Break\n#define AT91C_US_STPBRK       ((unsigned int) 0x1 << 10) // (USART) Stop Break\n#define AT91C_US_STTTO        ((unsigned int) 0x1 << 11) // (USART) Start Time-out\n#define AT91C_US_SENDA        ((unsigned int) 0x1 << 12) // (USART) Send Address\n#define AT91C_US_RSTIT        ((unsigned int) 0x1 << 13) // (USART) Reset Iterations\n#define AT91C_US_RSTNACK      ((unsigned int) 0x1 << 14) // (USART) Reset Non Acknowledge\n#define AT91C_US_RETTO        ((unsigned int) 0x1 << 15) // (USART) Rearm Time-out\n#define AT91C_US_DTREN        ((unsigned int) 0x1 << 16) // (USART) Data Terminal ready Enable\n#define AT91C_US_DTRDIS       ((unsigned int) 0x1 << 17) // (USART) Data Terminal ready Disable\n#define AT91C_US_RTSEN        ((unsigned int) 0x1 << 18) // (USART) Request to Send enable\n#define AT91C_US_RTSDIS       ((unsigned int) 0x1 << 19) // (USART) Request to Send Disable\n// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- \n#define AT91C_US_USMODE       ((unsigned int) 0xF <<  0) // (USART) Usart mode\n#define \tAT91C_US_USMODE_NORMAL               ((unsigned int) 0x0) // (USART) Normal\n#define \tAT91C_US_USMODE_RS485                ((unsigned int) 0x1) // (USART) RS485\n#define \tAT91C_US_USMODE_HWHSH                ((unsigned int) 0x2) // (USART) Hardware Handshaking\n#define \tAT91C_US_USMODE_MODEM                ((unsigned int) 0x3) // (USART) Modem\n#define \tAT91C_US_USMODE_ISO7816_0            ((unsigned int) 0x4) // (USART) ISO7816 protocol: T = 0\n#define \tAT91C_US_USMODE_ISO7816_1            ((unsigned int) 0x6) // (USART) ISO7816 protocol: T = 1\n#define \tAT91C_US_USMODE_IRDA                 ((unsigned int) 0x8) // (USART) IrDA\n#define \tAT91C_US_USMODE_SWHSH                ((unsigned int) 0xC) // (USART) Software Handshaking\n#define AT91C_US_CLKS         ((unsigned int) 0x3 <<  4) // (USART) Clock Selection (Baud Rate generator Input Clock\n#define \tAT91C_US_CLKS_CLOCK                ((unsigned int) 0x0 <<  4) // (USART) Clock\n#define \tAT91C_US_CLKS_FDIV1                ((unsigned int) 0x1 <<  4) // (USART) fdiv1\n#define \tAT91C_US_CLKS_SLOW                 ((unsigned int) 0x2 <<  4) // (USART) slow_clock (ARM)\n#define \tAT91C_US_CLKS_EXT                  ((unsigned int) 0x3 <<  4) // (USART) External (SCK)\n#define AT91C_US_CHRL         ((unsigned int) 0x3 <<  6) // (USART) Clock Selection (Baud Rate generator Input Clock\n#define \tAT91C_US_CHRL_5_BITS               ((unsigned int) 0x0 <<  6) // (USART) Character Length: 5 bits\n#define \tAT91C_US_CHRL_6_BITS               ((unsigned int) 0x1 <<  6) // (USART) Character Length: 6 bits\n#define \tAT91C_US_CHRL_7_BITS               ((unsigned int) 0x2 <<  6) // (USART) Character Length: 7 bits\n#define \tAT91C_US_CHRL_8_BITS               ((unsigned int) 0x3 <<  6) // (USART) Character Length: 8 bits\n#define AT91C_US_SYNC         ((unsigned int) 0x1 <<  8) // (USART) Synchronous Mode Select\n#define AT91C_US_NBSTOP       ((unsigned int) 0x3 << 12) // (USART) Number of Stop bits\n#define \tAT91C_US_NBSTOP_1_BIT                ((unsigned int) 0x0 << 12) // (USART) 1 stop bit\n#define \tAT91C_US_NBSTOP_15_BIT               ((unsigned int) 0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits\n#define \tAT91C_US_NBSTOP_2_BIT                ((unsigned int) 0x2 << 12) // (USART) 2 stop bits\n#define AT91C_US_MSBF         ((unsigned int) 0x1 << 16) // (USART) Bit Order\n#define AT91C_US_MODE9        ((unsigned int) 0x1 << 17) // (USART) 9-bit Character length\n#define AT91C_US_CKLO         ((unsigned int) 0x1 << 18) // (USART) Clock Output Select\n#define AT91C_US_OVER         ((unsigned int) 0x1 << 19) // (USART) Over Sampling Mode\n#define AT91C_US_INACK        ((unsigned int) 0x1 << 20) // (USART) Inhibit Non Acknowledge\n#define AT91C_US_DSNACK       ((unsigned int) 0x1 << 21) // (USART) Disable Successive NACK\n#define AT91C_US_MAX_ITER     ((unsigned int) 0x1 << 24) // (USART) Number of Repetitions\n#define AT91C_US_FILTER       ((unsigned int) 0x1 << 28) // (USART) Receive Line Filter\n// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- \n#define AT91C_US_RXBRK        ((unsigned int) 0x1 <<  2) // (USART) Break Received/End of Break\n#define AT91C_US_TIMEOUT      ((unsigned int) 0x1 <<  8) // (USART) Receiver Time-out\n#define AT91C_US_ITERATION    ((unsigned int) 0x1 << 10) // (USART) Max number of Repetitions Reached\n#define AT91C_US_NACK         ((unsigned int) 0x1 << 13) // (USART) Non Acknowledge\n#define AT91C_US_RIIC         ((unsigned int) 0x1 << 16) // (USART) Ring INdicator Input Change Flag\n#define AT91C_US_DSRIC        ((unsigned int) 0x1 << 17) // (USART) Data Set Ready Input Change Flag\n#define AT91C_US_DCDIC        ((unsigned int) 0x1 << 18) // (USART) Data Carrier Flag\n#define AT91C_US_CTSIC        ((unsigned int) 0x1 << 19) // (USART) Clear To Send Input Change Flag\n// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- \n// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- \n// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- \n#define AT91C_US_RI           ((unsigned int) 0x1 << 20) // (USART) Image of RI Input\n#define AT91C_US_DSR          ((unsigned int) 0x1 << 21) // (USART) Image of DSR Input\n#define AT91C_US_DCD          ((unsigned int) 0x1 << 22) // (USART) Image of DCD Input\n#define AT91C_US_CTS          ((unsigned int) 0x1 << 23) // (USART) Image of CTS Input\n\n// *****************************************************************************\n//              SOFTWARE API DEFINITION  FOR Two-wire Interface\n// *****************************************************************************\ntypedef struct _AT91S_TWI {\n\tAT91_REG\t TWI_CR; \t// Control Register\n\tAT91_REG\t TWI_MMR; \t// Master Mode Register\n\tAT91_REG\t TWI_SMR; \t// Slave Mode Register\n\tAT91_REG\t TWI_IADR; \t// Internal Address Register\n\tAT91_REG\t TWI_CWGR; \t// Clock Waveform Generator Register\n\tAT91_REG\t Reserved0[3]; \t// \n\tAT91_REG\t TWI_SR; \t// Status Register\n\tAT91_REG\t TWI_IER; \t// Interrupt Enable Register\n\tAT91_REG\t TWI_IDR; \t// Interrupt Disable Register\n\tAT91_REG\t TWI_IMR; \t// Interrupt Mask Register\n\tAT91_REG\t TWI_RHR; \t// Receive Holding Register\n\tAT91_REG\t TWI_THR; \t// Transmit Holding Register\n} AT91S_TWI, *AT91PS_TWI;\n\n// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- \n#define AT91C_TWI_START       ((unsigned int) 0x1 <<  0) // (TWI) Send a START Condition\n#define AT91C_TWI_STOP        ((unsigned int) 0x1 <<  1) // (TWI) Send a STOP Condition\n#define AT91C_TWI_MSEN        ((unsigned int) 0x1 <<  2) // (TWI) TWI Master Transfer Enabled\n#define AT91C_TWI_MSDIS       ((unsigned int) 0x1 <<  3) // (TWI) TWI Master Transfer Disabled\n#define AT91C_TWI_SVEN        ((unsigned int) 0x1 <<  4) // (TWI) TWI Slave Transfer Enabled\n#define AT91C_TWI_SVDIS       ((unsigned int) 0x1 <<  5) // (TWI) TWI Slave Transfer Disabled\n#define AT91C_TWI_SWRST       ((unsigned int) 0x1 <<  7) // (TWI) Software Reset\n// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- \n#define AT91C_TWI_IADRSZ      ((unsigned int) 0x3 <<  8) // (TWI) Internal Device Address Size\n#define \tAT91C_TWI_IADRSZ_NO                   ((unsigned int) 0x0 <<  8) // (TWI) No internal device address\n#define \tAT91C_TWI_IADRSZ_1_BYTE               ((unsigned int) 0x1 <<  8) // (TWI) One-byte internal device address\n#define \tAT91C_TWI_IADRSZ_2_BYTE               ((unsigned int) 0x2 <<  8) // (TWI) Two-byte internal device address\n#define \tAT91C_TWI_IADRSZ_3_BYTE               ((unsigned int) 0x3 <<  8) // (TWI) Three-byte internal device address\n#define AT91C_TWI_MREAD       ((unsigned int) 0x1 << 12) // (TWI) Master Read Direction\n#define AT91C_TWI_DADR        ((unsigned int) 0x7F << 16) // (TWI) Device Address\n// -------- TWI_SMR : (TWI Offset: 0x8) TWI Slave Mode Register -------- \n#define AT91C_TWI_SADR        ((unsigned int) 0x7F << 16) // (TWI) Slave Device Address\n// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- \n#define AT91C_TWI_CLDIV       ((unsigned int) 0xFF <<  0) // (TWI) Clock Low Divider\n#define AT91C_TWI_CHDIV       ((unsigned int) 0xFF <<  8) // (TWI) Clock High Divider\n#define AT91C_TWI_CKDIV       ((unsigned int) 0x7 << 16) // (TWI) Clock Divider\n// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- \n#define AT91C_TWI_TXCOMP      ((unsigned int) 0x1 <<  0) // (TWI) Transmission Completed\n#define AT91C_TWI_RXRDY       ((unsigned int) 0x1 <<  1) // (TWI) Receive holding register ReaDY\n#define AT91C_TWI_TXRDY       ((unsigned int) 0x1 <<  2) // (TWI) Transmit holding register ReaDY\n#define AT91C_TWI_SVREAD      ((unsigned int) 0x1 <<  3) // (TWI) Slave Read\n#define AT91C_TWI_SVACC       ((unsigned int) 0x1 <<  4) // (TWI) Slave Access\n#define AT91C_TWI_GCACC       ((unsigned int) 0x1 <<  5) // (TWI) General Call Access\n#define AT91C_TWI_OVRE        ((unsigned int) 0x1 <<  6) // (TWI) Overrun Error\n#define AT91C_TWI_UNRE        ((unsigned int) 0x1 <<  7) // (TWI) Underrun Error\n#define AT91C_TWI_NACK        ((unsigned int) 0x1 <<  8) // (TWI) Not Acknowledged\n#define AT91C_TWI_ARBLST      ((unsigned int) 0x1 <<  9) // (TWI) Arbitration Lost\n// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- \n// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- \n// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- \n\n// *****************************************************************************\n//              SOFTWARE API DEFINITION  FOR Multimedia Card Interface\n// *****************************************************************************\ntypedef struct _AT91S_MCI {\n\tAT91_REG\t MCI_CR; \t// MCI Control Register\n\tAT91_REG\t MCI_MR; \t// MCI Mode Register\n\tAT91_REG\t MCI_DTOR; \t// MCI Data Timeout Register\n\tAT91_REG\t MCI_SDCR; \t// MCI SD Card Register\n\tAT91_REG\t MCI_ARGR; \t// MCI Argument Register\n\tAT91_REG\t MCI_CMDR; \t// MCI Command Register\n\tAT91_REG\t Reserved0[2]; \t// \n\tAT91_REG\t MCI_RSPR[4]; \t// MCI Response Register\n\tAT91_REG\t MCI_RDR; \t// MCI Receive Data Register\n\tAT91_REG\t MCI_TDR; \t// MCI Transmit Data Register\n\tAT91_REG\t Reserved1[2]; \t// \n\tAT91_REG\t MCI_SR; \t// MCI Status Register\n\tAT91_REG\t MCI_IER; \t// MCI Interrupt Enable Register\n\tAT91_REG\t MCI_IDR; \t// MCI Interrupt Disable Register\n\tAT91_REG\t MCI_IMR; \t// MCI Interrupt Mask Register\n\tAT91_REG\t Reserved2[44]; \t// \n\tAT91_REG\t MCI_RPR; \t// Receive Pointer Register\n\tAT91_REG\t MCI_RCR; \t// Receive Counter Register\n\tAT91_REG\t MCI_TPR; \t// Transmit Pointer Register\n\tAT91_REG\t MCI_TCR; \t// Transmit Counter Register\n\tAT91_REG\t MCI_RNPR; \t// Receive Next Pointer Register\n\tAT91_REG\t MCI_RNCR; \t// Receive Next Counter Register\n\tAT91_REG\t MCI_TNPR; \t// Transmit Next Pointer Register\n\tAT91_REG\t MCI_TNCR; \t// Transmit Next Counter Register\n\tAT91_REG\t MCI_PTCR; \t// PDC Transfer Control Register\n\tAT91_REG\t MCI_PTSR; \t// PDC Transfer Status Register\n} AT91S_MCI, *AT91PS_MCI;\n\n// -------- MCI_CR : (MCI Offset: 0x0) MCI Control Register -------- \n#define AT91C_MCI_MCIEN       ((unsigned int) 0x1 <<  0) // (MCI) Multimedia Interface Enable\n#define AT91C_MCI_MCIDIS      ((unsigned int) 0x1 <<  1) // (MCI) Multimedia Interface Disable\n#define AT91C_MCI_PWSEN       ((unsigned int) 0x1 <<  2) // (MCI) Power Save Mode Enable\n#define AT91C_MCI_PWSDIS      ((unsigned int) 0x1 <<  3) // (MCI) Power Save Mode Disable\n// -------- MCI_MR : (MCI Offset: 0x4) MCI Mode Register -------- \n#define AT91C_MCI_CLKDIV      ((unsigned int) 0x1 <<  0) // (MCI) Clock Divider\n#define AT91C_MCI_PWSDIV      ((unsigned int) 0x1 <<  8) // (MCI) Power Saving Divider\n#define AT91C_MCI_PDCPADV     ((unsigned int) 0x1 << 14) // (MCI) PDC Padding Value\n#define AT91C_MCI_PDCMODE     ((unsigned int) 0x1 << 15) // (MCI) PDC Oriented Mode\n#define AT91C_MCI_BLKLEN      ((unsigned int) 0x1 << 18) // (MCI) Data Block Length\n// -------- MCI_DTOR : (MCI Offset: 0x8) MCI Data Timeout Register -------- \n#define AT91C_MCI_DTOCYC      ((unsigned int) 0x1 <<  0) // (MCI) Data Timeout Cycle Number\n#define AT91C_MCI_DTOMUL      ((unsigned int) 0x7 <<  4) // (MCI) Data Timeout Multiplier\n#define \tAT91C_MCI_DTOMUL_1                    ((unsigned int) 0x0 <<  4) // (MCI) DTOCYC x 1\n#define \tAT91C_MCI_DTOMUL_16                   ((unsigned int) 0x1 <<  4) // (MCI) DTOCYC x 16\n#define \tAT91C_MCI_DTOMUL_128                  ((unsigned int) 0x2 <<  4) // (MCI) DTOCYC x 128\n#define \tAT91C_MCI_DTOMUL_256                  ((unsigned int) 0x3 <<  4) // (MCI) DTOCYC x 256\n#define \tAT91C_MCI_DTOMUL_1024                 ((unsigned int) 0x4 <<  4) // (MCI) DTOCYC x 1024\n#define \tAT91C_MCI_DTOMUL_4096                 ((unsigned int) 0x5 <<  4) // (MCI) DTOCYC x 4096\n#define \tAT91C_MCI_DTOMUL_65536                ((unsigned int) 0x6 <<  4) // (MCI) DTOCYC x 65536\n#define \tAT91C_MCI_DTOMUL_1048576              ((unsigned int) 0x7 <<  4) // (MCI) DTOCYC x 1048576\n// -------- MCI_SDCR : (MCI Offset: 0xc) MCI SD Card Register -------- \n#define AT91C_MCI_SCDSEL      ((unsigned int) 0x1 <<  0) // (MCI) SD Card Selector\n#define AT91C_MCI_SCDBUS      ((unsigned int) 0x1 <<  7) // (MCI) SD Card Bus Width\n// -------- MCI_CMDR : (MCI Offset: 0x14) MCI Command Register -------- \n#define AT91C_MCI_CMDNB       ((unsigned int) 0x1F <<  0) // (MCI) Command Number\n#define AT91C_MCI_RSPTYP      ((unsigned int) 0x3 <<  6) // (MCI) Response Type\n#define \tAT91C_MCI_RSPTYP_NO                   ((unsigned int) 0x0 <<  6) // (MCI) No response\n#define \tAT91C_MCI_RSPTYP_48                   ((unsigned int) 0x1 <<  6) // (MCI) 48-bit response\n#define \tAT91C_MCI_RSPTYP_136                  ((unsigned int) 0x2 <<  6) // (MCI) 136-bit response\n#define AT91C_MCI_SPCMD       ((unsigned int) 0x7 <<  8) // (MCI) Special CMD\n#define \tAT91C_MCI_SPCMD_NONE                 ((unsigned int) 0x0 <<  8) // (MCI) Not a special CMD\n#define \tAT91C_MCI_SPCMD_INIT                 ((unsigned int) 0x1 <<  8) // (MCI) Initialization CMD\n#define \tAT91C_MCI_SPCMD_SYNC                 ((unsigned int) 0x2 <<  8) // (MCI) Synchronized CMD\n#define \tAT91C_MCI_SPCMD_IT_CMD               ((unsigned int) 0x4 <<  8) // (MCI) Interrupt command\n#define \tAT91C_MCI_SPCMD_IT_REP               ((unsigned int) 0x5 <<  8) // (MCI) Interrupt response\n#define AT91C_MCI_OPDCMD      ((unsigned int) 0x1 << 11) // (MCI) Open Drain Command\n#define AT91C_MCI_MAXLAT      ((unsigned int) 0x1 << 12) // (MCI) Maximum Latency for Command to respond\n#define AT91C_MCI_TRCMD       ((unsigned int) 0x3 << 16) // (MCI) Transfer CMD\n#define \tAT91C_MCI_TRCMD_NO                   ((unsigned int) 0x0 << 16) // (MCI) No transfer\n#define \tAT91C_MCI_TRCMD_START                ((unsigned int) 0x1 << 16) // (MCI) Start transfer\n#define \tAT91C_MCI_TRCMD_STOP                 ((unsigned int) 0x2 << 16) // (MCI) Stop transfer\n#define AT91C_MCI_TRDIR       ((unsigned int) 0x1 << 18) // (MCI) Transfer Direction\n#define AT91C_MCI_TRTYP       ((unsigned int) 0x3 << 19) // (MCI) Transfer Type\n#define \tAT91C_MCI_TRTYP_BLOCK                ((unsigned int) 0x0 << 19) // (MCI) Block Transfer type\n#define \tAT91C_MCI_TRTYP_MULTIPLE             ((unsigned int) 0x1 << 19) // (MCI) Multiple Block transfer type\n#define \tAT91C_MCI_TRTYP_STREAM               ((unsigned int) 0x2 << 19) // (MCI) Stream transfer type\n// -------- MCI_SR : (MCI Offset: 0x40) MCI Status Register -------- \n#define AT91C_MCI_CMDRDY      ((unsigned int) 0x1 <<  0) // (MCI) Command Ready flag\n#define AT91C_MCI_RXRDY       ((unsigned int) 0x1 <<  1) // (MCI) RX Ready flag\n#define AT91C_MCI_TXRDY       ((unsigned int) 0x1 <<  2) // (MCI) TX Ready flag\n#define AT91C_MCI_BLKE        ((unsigned int) 0x1 <<  3) // (MCI) Data Block Transfer Ended flag\n#define AT91C_MCI_DTIP        ((unsigned int) 0x1 <<  4) // (MCI) Data Transfer in Progress flag\n#define AT91C_MCI_NOTBUSY     ((unsigned int) 0x1 <<  5) // (MCI) Data Line Not Busy flag\n#define AT91C_MCI_ENDRX       ((unsigned int) 0x1 <<  6) // (MCI) End of RX Buffer flag\n#define AT91C_MCI_ENDTX       ((unsigned int) 0x1 <<  7) // (MCI) End of TX Buffer flag\n#define AT91C_MCI_RXBUFF      ((unsigned int) 0x1 << 14) // (MCI) RX Buffer Full flag\n#define AT91C_MCI_TXBUFE      ((unsigned int) 0x1 << 15) // (MCI) TX Buffer Empty flag\n#define AT91C_MCI_RINDE       ((unsigned int) 0x1 << 16) // (MCI) Response Index Error flag\n#define AT91C_MCI_RDIRE       ((unsigned int) 0x1 << 17) // (MCI) Response Direction Error flag\n#define AT91C_MCI_RCRCE       ((unsigned int) 0x1 << 18) // (MCI) Response CRC Error flag\n#define AT91C_MCI_RENDE       ((unsigned int) 0x1 << 19) // (MCI) Response End Bit Error flag\n#define AT91C_MCI_RTOE        ((unsigned int) 0x1 << 20) // (MCI) Response Time-out Error flag\n#define AT91C_MCI_DCRCE       ((unsigned int) 0x1 << 21) // (MCI) data CRC Error flag\n#define AT91C_MCI_DTOE        ((unsigned int) 0x1 << 22) // (MCI) Data timeout Error flag\n#define AT91C_MCI_OVRE        ((unsigned int) 0x1 << 30) // (MCI) Overrun flag\n#define AT91C_MCI_UNRE        ((unsigned int) 0x1 << 31) // (MCI) Underrun flag\n// -------- MCI_IER : (MCI Offset: 0x44) MCI Interrupt Enable Register -------- \n// -------- MCI_IDR : (MCI Offset: 0x48) MCI Interrupt Disable Register -------- \n// -------- MCI_IMR : (MCI Offset: 0x4c) MCI Interrupt Mask Register -------- \n\n// *****************************************************************************\n//              SOFTWARE API DEFINITION  FOR USB Device Interface\n// *****************************************************************************\ntypedef struct _AT91S_UDP {\n\tAT91_REG\t UDP_NUM; \t// Frame Number Register\n\tAT91_REG\t UDP_GLBSTATE; \t// Global State Register\n\tAT91_REG\t UDP_FADDR; \t// Function Address Register\n\tAT91_REG\t Reserved0[1]; \t// \n\tAT91_REG\t UDP_IER; \t// Interrupt Enable Register\n\tAT91_REG\t UDP_IDR; \t// Interrupt Disable Register\n\tAT91_REG\t UDP_IMR; \t// Interrupt Mask Register\n\tAT91_REG\t UDP_ISR; \t// Interrupt Status Register\n\tAT91_REG\t UDP_ICR; \t// Interrupt Clear Register\n\tAT91_REG\t Reserved1[1]; \t// \n\tAT91_REG\t UDP_RSTEP; \t// Reset Endpoint Register\n\tAT91_REG\t Reserved2[1]; \t// \n\tAT91_REG\t UDP_CSR[8]; \t// Endpoint Control and Status Register\n\tAT91_REG\t UDP_FDR[8]; \t// Endpoint FIFO Data Register\n} AT91S_UDP, *AT91PS_UDP;\n\n// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- \n#define AT91C_UDP_FRM_NUM     ((unsigned int) 0x7FF <<  0) // (UDP) Frame Number as Defined in the Packet Field Formats\n#define AT91C_UDP_FRM_ERR     ((unsigned int) 0x1 << 16) // (UDP) Frame Error\n#define AT91C_UDP_FRM_OK      ((unsigned int) 0x1 << 17) // (UDP) Frame OK\n// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- \n#define AT91C_UDP_FADDEN      ((unsigned int) 0x1 <<  0) // (UDP) Function Address Enable\n#define AT91C_UDP_CONFG       ((unsigned int) 0x1 <<  1) // (UDP) Configured\n#define AT91C_UDP_RMWUPE      ((unsigned int) 0x1 <<  2) // (UDP) Remote Wake Up Enable\n#define AT91C_UDP_RSMINPR     ((unsigned int) 0x1 <<  3) // (UDP) A Resume Has Been Sent to the Host\n// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- \n#define AT91C_UDP_FADD        ((unsigned int) 0xFF <<  0) // (UDP) Function Address Value\n#define AT91C_UDP_FEN         ((unsigned int) 0x1 <<  8) // (UDP) Function Enable\n// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- \n#define AT91C_UDP_EPINT0      ((unsigned int) 0x1 <<  0) // (UDP) Endpoint 0 Interrupt\n#define AT91C_UDP_EPINT1      ((unsigned int) 0x1 <<  1) // (UDP) Endpoint 0 Interrupt\n#define AT91C_UDP_EPINT2      ((unsigned int) 0x1 <<  2) // (UDP) Endpoint 2 Interrupt\n#define AT91C_UDP_EPINT3      ((unsigned int) 0x1 <<  3) // (UDP) Endpoint 3 Interrupt\n#define AT91C_UDP_EPINT4      ((unsigned int) 0x1 <<  4) // (UDP) Endpoint 4 Interrupt\n#define AT91C_UDP_EPINT5      ((unsigned int) 0x1 <<  5) // (UDP) Endpoint 5 Interrupt\n#define AT91C_UDP_EPINT6      ((unsigned int) 0x1 <<  6) // (UDP) Endpoint 6 Interrupt\n#define AT91C_UDP_EPINT7      ((unsigned int) 0x1 <<  7) // (UDP) Endpoint 7 Interrupt\n#define AT91C_UDP_RXSUSP      ((unsigned int) 0x1 <<  8) // (UDP) USB Suspend Interrupt\n#define AT91C_UDP_RXRSM       ((unsigned int) 0x1 <<  9) // (UDP) USB Resume Interrupt\n#define AT91C_UDP_EXTRSM      ((unsigned int) 0x1 << 10) // (UDP) USB External Resume Interrupt\n#define AT91C_UDP_SOFINT      ((unsigned int) 0x1 << 11) // (UDP) USB Start Of frame Interrupt\n#define AT91C_UDP_WAKEUP      ((unsigned int) 0x1 << 13) // (UDP) USB Resume Interrupt\n// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- \n// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- \n// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- \n#define AT91C_UDP_ENDBUSRES   ((unsigned int) 0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt\n// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- \n// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- \n#define AT91C_UDP_EP0         ((unsigned int) 0x1 <<  0) // (UDP) Reset Endpoint 0\n#define AT91C_UDP_EP1         ((unsigned int) 0x1 <<  1) // (UDP) Reset Endpoint 1\n#define AT91C_UDP_EP2         ((unsigned int) 0x1 <<  2) // (UDP) Reset Endpoint 2\n#define AT91C_UDP_EP3         ((unsigned int) 0x1 <<  3) // (UDP) Reset Endpoint 3\n#define AT91C_UDP_EP4         ((unsigned int) 0x1 <<  4) // (UDP) Reset Endpoint 4\n#define AT91C_UDP_EP5         ((unsigned int) 0x1 <<  5) // (UDP) Reset Endpoint 5\n#define AT91C_UDP_EP6         ((unsigned int) 0x1 <<  6) // (UDP) Reset Endpoint 6\n#define AT91C_UDP_EP7         ((unsigned int) 0x1 <<  7) // (UDP) Reset Endpoint 7\n// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- \n#define AT91C_UDP_TXCOMP      ((unsigned int) 0x1 <<  0) // (UDP) Generates an IN packet with data previously written in the DPR\n#define AT91C_UDP_RX_DATA_BK0 ((unsigned int) 0x1 <<  1) // (UDP) Receive Data Bank 0\n#define AT91C_UDP_RXSETUP     ((unsigned int) 0x1 <<  2) // (UDP) Sends STALL to the Host (Control endpoints)\n#define AT91C_UDP_ISOERROR    ((unsigned int) 0x1 <<  3) // (UDP) Isochronous error (Isochronous endpoints)\n#define AT91C_UDP_TXPKTRDY    ((unsigned int) 0x1 <<  4) // (UDP) Transmit Packet Ready\n#define AT91C_UDP_FORCESTALL  ((unsigned int) 0x1 <<  5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).\n#define AT91C_UDP_RX_DATA_BK1 ((unsigned int) 0x1 <<  6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).\n#define AT91C_UDP_DIR         ((unsigned int) 0x1 <<  7) // (UDP) Transfer Direction\n#define AT91C_UDP_EPTYPE      ((unsigned int) 0x7 <<  8) // (UDP) Endpoint type\n#define \tAT91C_UDP_EPTYPE_CTRL                 ((unsigned int) 0x0 <<  8) // (UDP) Control\n#define \tAT91C_UDP_EPTYPE_ISO_OUT              ((unsigned int) 0x1 <<  8) // (UDP) Isochronous OUT\n#define \tAT91C_UDP_EPTYPE_BULK_OUT             ((unsigned int) 0x2 <<  8) // (UDP) Bulk OUT\n#define \tAT91C_UDP_EPTYPE_INT_OUT              ((unsigned int) 0x3 <<  8) // (UDP) Interrupt OUT\n#define \tAT91C_UDP_EPTYPE_ISO_IN               ((unsigned int) 0x5 <<  8) // (UDP) Isochronous IN\n#define \tAT91C_UDP_EPTYPE_BULK_IN              ((unsigned int) 0x6 <<  8) // (UDP) Bulk IN\n#define \tAT91C_UDP_EPTYPE_INT_IN               ((unsigned int) 0x7 <<  8) // (UDP) Interrupt IN\n#define AT91C_UDP_DTGLE       ((unsigned int) 0x1 << 11) // (UDP) Data Toggle\n#define AT91C_UDP_EPEDS       ((unsigned int) 0x1 << 15) // (UDP) Endpoint Enable Disable\n#define AT91C_UDP_RXBYTECNT   ((unsigned int) 0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO\n\n// *****************************************************************************\n//              SOFTWARE API DEFINITION  FOR Timer Counter Channel Interface\n// *****************************************************************************\ntypedef struct _AT91S_TC {\n\tAT91_REG\t TC_CCR; \t// Channel Control Register\n\tAT91_REG\t TC_CMR; \t// Channel Mode Register\n\tAT91_REG\t Reserved0[2]; \t// \n\tAT91_REG\t TC_CV; \t// Counter Value\n\tAT91_REG\t TC_RA; \t// Register A\n\tAT91_REG\t TC_RB; \t// Register B\n\tAT91_REG\t TC_RC; \t// Register C\n\tAT91_REG\t TC_SR; \t// Status Register\n\tAT91_REG\t TC_IER; \t// Interrupt Enable Register\n\tAT91_REG\t TC_IDR; \t// Interrupt Disable Register\n\tAT91_REG\t TC_IMR; \t// Interrupt Mask Register\n} AT91S_TC, *AT91PS_TC;\n\n// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- \n#define AT91C_TC_CLKEN        ((unsigned int) 0x1 <<  0) // (TC) Counter Clock Enable Command\n#define AT91C_TC_CLKDIS       ((unsigned int) 0x1 <<  1) // (TC) Counter Clock Disable Command\n#define AT91C_TC_SWTRG        ((unsigned int) 0x1 <<  2) // (TC) Software Trigger Command\n// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- \n#define AT91C_TC_CPCSTOP      ((unsigned int) 0x1 <<  6) // (TC) Counter Clock Stopped with RC Compare\n#define AT91C_TC_CPCDIS       ((unsigned int) 0x1 <<  7) // (TC) Counter Clock Disable with RC Compare\n#define AT91C_TC_EEVTEDG      ((unsigned int) 0x3 <<  8) // (TC) External Event Edge Selection\n#define \tAT91C_TC_EEVTEDG_NONE                 ((unsigned int) 0x0 <<  8) // (TC) Edge: None\n#define \tAT91C_TC_EEVTEDG_RISING               ((unsigned int) 0x1 <<  8) // (TC) Edge: rising edge\n#define \tAT91C_TC_EEVTEDG_FALLING              ((unsigned int) 0x2 <<  8) // (TC) Edge: falling edge\n#define \tAT91C_TC_EEVTEDG_BOTH                 ((unsigned int) 0x3 <<  8) // (TC) Edge: each edge\n#define AT91C_TC_EEVT         ((unsigned int) 0x3 << 10) // (TC) External Event  Selection\n#define \tAT91C_TC_EEVT_NONE                 ((unsigned int) 0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input\n#define \tAT91C_TC_EEVT_RISING               ((unsigned int) 0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output\n#define \tAT91C_TC_EEVT_FALLING              ((unsigned int) 0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output\n#define \tAT91C_TC_EEVT_BOTH                 ((unsigned int) 0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output\n#define AT91C_TC_ENETRG       ((unsigned int) 0x1 << 12) // (TC) External Event Trigger enable\n#define AT91C_TC_WAVESEL      ((unsigned int) 0x3 << 13) // (TC) Waveform  Selection\n#define \tAT91C_TC_WAVESEL_UP                   ((unsigned int) 0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare\n#define \tAT91C_TC_WAVESEL_UPDOWN               ((unsigned int) 0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare\n#define \tAT91C_TC_WAVESEL_UP_AUTO              ((unsigned int) 0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare\n#define \tAT91C_TC_WAVESEL_UPDOWN_AUTO          ((unsigned int) 0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare\n#define AT91C_TC_CPCTRG       ((unsigned int) 0x1 << 14) // (TC) RC Compare Trigger Enable\n#define AT91C_TC_WAVE         ((unsigned int) 0x1 << 15) // (TC) \n#define AT91C_TC_ACPA         ((unsigned int) 0x3 << 16) // (TC) RA Compare Effect on TIOA\n#define \tAT91C_TC_ACPA_NONE                 ((unsigned int) 0x0 << 16) // (TC) Effect: none\n#define \tAT91C_TC_ACPA_SET                  ((unsigned int) 0x1 << 16) // (TC) Effect: set\n#define \tAT91C_TC_ACPA_CLEAR                ((unsigned int) 0x2 << 16) // (TC) Effect: clear\n#define \tAT91C_TC_ACPA_TOGGLE               ((unsigned int) 0x3 << 16) // (TC) Effect: toggle\n#define AT91C_TC_ACPC         ((unsigned int) 0x3 << 18) // (TC) RC Compare Effect on TIOA\n#define \tAT91C_TC_ACPC_NONE                 ((unsigned int) 0x0 << 18) // (TC) Effect: none\n#define \tAT91C_TC_ACPC_SET                  ((unsigned int) 0x1 << 18) // (TC) Effect: set\n#define \tAT91C_TC_ACPC_CLEAR                ((unsigned int) 0x2 << 18) // (TC) Effect: clear\n#define \tAT91C_TC_ACPC_TOGGLE               ((unsigned int) 0x3 << 18) // (TC) Effect: toggle\n#define AT91C_TC_AEEVT        ((unsigned int) 0x3 << 20) // (TC) External Event Effect on TIOA\n#define \tAT91C_TC_AEEVT_NONE                 ((unsigned int) 0x0 << 20) // (TC) Effect: none\n#define \tAT91C_TC_AEEVT_SET                  ((unsigned int) 0x1 << 20) // (TC) Effect: set\n#define \tAT91C_TC_AEEVT_CLEAR                ((unsigned int) 0x2 << 20) // (TC) Effect: clear\n#define \tAT91C_TC_AEEVT_TOGGLE               ((unsigned int) 0x3 << 20) // (TC) Effect: toggle\n#define AT91C_TC_ASWTRG       ((unsigned int) 0x3 << 22) // (TC) Software Trigger Effect on TIOA\n#define \tAT91C_TC_ASWTRG_NONE                 ((unsigned int) 0x0 << 22) // (TC) Effect: none\n#define \tAT91C_TC_ASWTRG_SET                  ((unsigned int) 0x1 << 22) // (TC) Effect: set\n#define \tAT91C_TC_ASWTRG_CLEAR                ((unsigned int) 0x2 << 22) // (TC) Effect: clear\n#define \tAT91C_TC_ASWTRG_TOGGLE               ((unsigned int) 0x3 << 22) // (TC) Effect: toggle\n#define AT91C_TC_BCPB         ((unsigned int) 0x3 << 24) // (TC) RB Compare Effect on TIOB\n#define \tAT91C_TC_BCPB_NONE                 ((unsigned int) 0x0 << 24) // (TC) Effect: none\n#define \tAT91C_TC_BCPB_SET                  ((unsigned int) 0x1 << 24) // (TC) Effect: set\n#define \tAT91C_TC_BCPB_CLEAR                ((unsigned int) 0x2 << 24) // (TC) Effect: clear\n#define \tAT91C_TC_BCPB_TOGGLE               ((unsigned int) 0x3 << 24) // (TC) Effect: toggle\n#define AT91C_TC_BCPC         ((unsigned int) 0x3 << 26) // (TC) RC Compare Effect on TIOB\n#define \tAT91C_TC_BCPC_NONE                 ((unsigned int) 0x0 << 26) // (TC) Effect: none\n#define \tAT91C_TC_BCPC_SET                  ((unsigned int) 0x1 << 26) // (TC) Effect: set\n#define \tAT91C_TC_BCPC_CLEAR                ((unsigned int) 0x2 << 26) // (TC) Effect: clear\n#define \tAT91C_TC_BCPC_TOGGLE               ((unsigned int) 0x3 << 26) // (TC) Effect: toggle\n#define AT91C_TC_BEEVT        ((unsigned int) 0x3 << 28) // (TC) External Event Effect on TIOB\n#define \tAT91C_TC_BEEVT_NONE                 ((unsigned int) 0x0 << 28) // (TC) Effect: none\n#define \tAT91C_TC_BEEVT_SET                  ((unsigned int) 0x1 << 28) // (TC) Effect: set\n#define \tAT91C_TC_BEEVT_CLEAR                ((unsigned int) 0x2 << 28) // (TC) Effect: clear\n#define \tAT91C_TC_BEEVT_TOGGLE               ((unsigned int) 0x3 << 28) // (TC) Effect: toggle\n#define AT91C_TC_BSWTRG       ((unsigned int) 0x3 << 30) // (TC) Software Trigger Effect on TIOB\n#define \tAT91C_TC_BSWTRG_NONE                 ((unsigned int) 0x0 << 30) // (TC) Effect: none\n#define \tAT91C_TC_BSWTRG_SET                  ((unsigned int) 0x1 << 30) // (TC) Effect: set\n#define \tAT91C_TC_BSWTRG_CLEAR                ((unsigned int) 0x2 << 30) // (TC) Effect: clear\n#define \tAT91C_TC_BSWTRG_TOGGLE               ((unsigned int) 0x3 << 30) // (TC) Effect: toggle\n// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- \n#define AT91C_TC_COVFS        ((unsigned int) 0x1 <<  0) // (TC) Counter Overflow\n#define AT91C_TC_LOVRS        ((unsigned int) 0x1 <<  1) // (TC) Load Overrun\n#define AT91C_TC_CPAS         ((unsigned int) 0x1 <<  2) // (TC) RA Compare\n#define AT91C_TC_CPBS         ((unsigned int) 0x1 <<  3) // (TC) RB Compare\n#define AT91C_TC_CPCS         ((unsigned int) 0x1 <<  4) // (TC) RC Compare\n#define AT91C_TC_LDRAS        ((unsigned int) 0x1 <<  5) // (TC) RA Loading\n#define AT91C_TC_LDRBS        ((unsigned int) 0x1 <<  6) // (TC) RB Loading\n#define AT91C_TC_ETRCS        ((unsigned int) 0x1 <<  7) // (TC) External Trigger\n#define AT91C_TC_ETRGS        ((unsigned int) 0x1 << 16) // (TC) Clock Enabling\n#define AT91C_TC_MTIOA        ((unsigned int) 0x1 << 17) // (TC) TIOA Mirror\n#define AT91C_TC_MTIOB        ((unsigned int) 0x1 << 18) // (TC) TIOA Mirror\n// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- \n// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- \n// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- \n\n// *****************************************************************************\n//              SOFTWARE API DEFINITION  FOR Timer Counter Interface\n// *****************************************************************************\ntypedef struct _AT91S_TCB {\n\tAT91S_TC\t TCB_TC0; \t// TC Channel 0\n\tAT91_REG\t Reserved0[4]; \t// \n\tAT91S_TC\t TCB_TC1; \t// TC Channel 1\n\tAT91_REG\t Reserved1[4]; \t// \n\tAT91S_TC\t TCB_TC2; \t// TC Channel 2\n\tAT91_REG\t Reserved2[4]; \t// \n\tAT91_REG\t TCB_BCR; \t// TC Block Control Register\n\tAT91_REG\t TCB_BMR; \t// TC Block Mode Register\n} AT91S_TCB, *AT91PS_TCB;\n\n// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- \n#define AT91C_TCB_SYNC        ((unsigned int) 0x1 <<  0) // (TCB) Synchro Command\n// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- \n#define AT91C_TCB_TC0XC0S     ((unsigned int) 0x1 <<  0) // (TCB) External Clock Signal 0 Selection\n#define \tAT91C_TCB_TC0XC0S_TCLK0                ((unsigned int) 0x0) // (TCB) TCLK0 connected to XC0\n#define \tAT91C_TCB_TC0XC0S_NONE                 ((unsigned int) 0x1) // (TCB) None signal connected to XC0\n#define \tAT91C_TCB_TC0XC0S_TIOA1                ((unsigned int) 0x2) // (TCB) TIOA1 connected to XC0\n#define \tAT91C_TCB_TC0XC0S_TIOA2                ((unsigned int) 0x3) // (TCB) TIOA2 connected to XC0\n#define AT91C_TCB_TC1XC1S     ((unsigned int) 0x1 <<  2) // (TCB) External Clock Signal 1 Selection\n#define \tAT91C_TCB_TC1XC1S_TCLK1                ((unsigned int) 0x0 <<  2) // (TCB) TCLK1 connected to XC1\n#define \tAT91C_TCB_TC1XC1S_NONE                 ((unsigned int) 0x1 <<  2) // (TCB) None signal connected to XC1\n#define \tAT91C_TCB_TC1XC1S_TIOA0                ((unsigned int) 0x2 <<  2) // (TCB) TIOA0 connected to XC1\n#define \tAT91C_TCB_TC1XC1S_TIOA2                ((unsigned int) 0x3 <<  2) // (TCB) TIOA2 connected to XC1\n#define AT91C_TCB_TC2XC2S     ((unsigned int) 0x1 <<  4) // (TCB) External Clock Signal 2 Selection\n#define \tAT91C_TCB_TC2XC2S_TCLK2                ((unsigned int) 0x0 <<  4) // (TCB) TCLK2 connected to XC2\n#define \tAT91C_TCB_TC2XC2S_NONE                 ((unsigned int) 0x1 <<  4) // (TCB) None signal connected to XC2\n#define \tAT91C_TCB_TC2XC2S_TIOA0                ((unsigned int) 0x2 <<  4) // (TCB) TIOA0 connected to XC2\n#define \tAT91C_TCB_TC2XC2S_TIOA2                ((unsigned int) 0x3 <<  4) // (TCB) TIOA2 connected to XC2\n\n// *****************************************************************************\n//              SOFTWARE API DEFINITION  FOR USB Host Interface\n// *****************************************************************************\ntypedef struct _AT91S_UHP {\n\tAT91_REG\t UHP_HcRevision; \t// Revision\n\tAT91_REG\t UHP_HcControl; \t// Operating modes for the Host Controller\n\tAT91_REG\t UHP_HcCommandStatus; \t// Command & status Register\n\tAT91_REG\t UHP_HcInterruptStatus; \t// Interrupt Status Register\n\tAT91_REG\t UHP_HcInterruptEnable; \t// Interrupt Enable Register\n\tAT91_REG\t UHP_HcInterruptDisable; \t// Interrupt Disable Register\n\tAT91_REG\t UHP_HcHCCA; \t// Pointer to the Host Controller Communication Area\n\tAT91_REG\t UHP_HcPeriodCurrentED; \t// Current Isochronous or Interrupt Endpoint Descriptor\n\tAT91_REG\t UHP_HcControlHeadED; \t// First Endpoint Descriptor of the Control list\n\tAT91_REG\t UHP_HcControlCurrentED; \t// Endpoint Control and Status Register\n\tAT91_REG\t UHP_HcBulkHeadED; \t// First endpoint register of the Bulk list\n\tAT91_REG\t UHP_HcBulkCurrentED; \t// Current endpoint of the Bulk list\n\tAT91_REG\t UHP_HcBulkDoneHead; \t// Last completed transfer descriptor\n\tAT91_REG\t UHP_HcFmInterval; \t// Bit time between 2 consecutive SOFs\n\tAT91_REG\t UHP_HcFmRemaining; \t// Bit time remaining in the current Frame\n\tAT91_REG\t UHP_HcFmNumber; \t// Frame number\n\tAT91_REG\t UHP_HcPeriodicStart; \t// Periodic Start\n\tAT91_REG\t UHP_HcLSThreshold; \t// LS Threshold\n\tAT91_REG\t UHP_HcRhDescriptorA; \t// Root Hub characteristics A\n\tAT91_REG\t UHP_HcRhDescriptorB; \t// Root Hub characteristics B\n\tAT91_REG\t UHP_HcRhStatus; \t// Root Hub Status register\n\tAT91_REG\t UHP_HcRhPortStatus[2]; \t// Root Hub Port Status Register\n} AT91S_UHP, *AT91PS_UHP;\n\n\n// *****************************************************************************\n//              SOFTWARE API DEFINITION  FOR Ethernet MAC\n// *****************************************************************************\ntypedef struct _AT91S_EMAC {\n\tAT91_REG\t EMAC_CTL; \t// Network Control Register\n\tAT91_REG\t EMAC_CFG; \t// Network Configuration Register\n\tAT91_REG\t EMAC_SR; \t// Network Status Register\n\tAT91_REG\t EMAC_TAR; \t// Transmit Address Register\n\tAT91_REG\t EMAC_TCR; \t// Transmit Control Register\n\tAT91_REG\t EMAC_TSR; \t// Transmit Status Register\n\tAT91_REG\t EMAC_RBQP; \t// Receive Buffer Queue Pointer\n\tAT91_REG\t Reserved0[1]; \t// \n\tAT91_REG\t EMAC_RSR; \t// Receive Status Register\n\tAT91_REG\t EMAC_ISR; \t// Interrupt Status Register\n\tAT91_REG\t EMAC_IER; \t// Interrupt Enable Register\n\tAT91_REG\t EMAC_IDR; \t// Interrupt Disable Register\n\tAT91_REG\t EMAC_IMR; \t// Interrupt Mask Register\n\tAT91_REG\t EMAC_MAN; \t// PHY Maintenance Register\n\tAT91_REG\t Reserved1[2]; \t// \n\tAT91_REG\t EMAC_FRA; \t// Frames Transmitted OK Register\n\tAT91_REG\t EMAC_SCOL; \t// Single Collision Frame Register\n\tAT91_REG\t EMAC_MCOL; \t// Multiple Collision Frame Register\n\tAT91_REG\t EMAC_OK; \t// Frames Received OK Register\n\tAT91_REG\t EMAC_SEQE; \t// Frame Check Sequence Error Register\n\tAT91_REG\t EMAC_ALE; \t// Alignment Error Register\n\tAT91_REG\t EMAC_DTE; \t// Deferred Transmission Frame Register\n\tAT91_REG\t EMAC_LCOL; \t// Late Collision Register\n\tAT91_REG\t EMAC_ECOL; \t// Excessive Collision Register\n\tAT91_REG\t EMAC_CSE; \t// Carrier Sense Error Register\n\tAT91_REG\t EMAC_TUE; \t// Transmit Underrun Error Register\n\tAT91_REG\t EMAC_CDE; \t// Code Error Register\n\tAT91_REG\t EMAC_ELR; \t// Excessive Length Error Register\n\tAT91_REG\t EMAC_RJB; \t// Receive Jabber Register\n\tAT91_REG\t EMAC_USF; \t// Undersize Frame Register\n\tAT91_REG\t EMAC_SQEE; \t// SQE Test Error Register\n\tAT91_REG\t EMAC_DRFC; \t// Discarded RX Frame Register\n\tAT91_REG\t Reserved2[3]; \t// \n\tAT91_REG\t EMAC_HSH; \t// Hash Address High[63:32]\n\tAT91_REG\t EMAC_HSL; \t// Hash Address Low[31:0]\n\tAT91_REG\t EMAC_SA1L; \t// Specific Address 1 Low, First 4 bytes\n\tAT91_REG\t EMAC_SA1H; \t// Specific Address 1 High, Last 2 bytes\n\tAT91_REG\t EMAC_SA2L; \t// Specific Address 2 Low, First 4 bytes\n\tAT91_REG\t EMAC_SA2H; \t// Specific Address 2 High, Last 2 bytes\n\tAT91_REG\t EMAC_SA3L; \t// Specific Address 3 Low, First 4 bytes\n\tAT91_REG\t EMAC_SA3H; \t// Specific Address 3 High, Last 2 bytes\n\tAT91_REG\t EMAC_SA4L; \t// Specific Address 4 Low, First 4 bytes\n\tAT91_REG\t EMAC_SA4H; \t// Specific Address 4 High, Last 2 bytesr\n} AT91S_EMAC, *AT91PS_EMAC;\n\n// -------- EMAC_CTL : (EMAC Offset: 0x0)  -------- \n#define AT91C_EMAC_LB         ((unsigned int) 0x1 <<  0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level.\n#define AT91C_EMAC_LBL        ((unsigned int) 0x1 <<  1) // (EMAC) Loopback local. \n#define AT91C_EMAC_RE         ((unsigned int) 0x1 <<  2) // (EMAC) Receive enable. \n#define AT91C_EMAC_TE         ((unsigned int) 0x1 <<  3) // (EMAC) Transmit enable. \n#define AT91C_EMAC_MPE        ((unsigned int) 0x1 <<  4) // (EMAC) Management port enable. \n#define AT91C_EMAC_CSR        ((unsigned int) 0x1 <<  5) // (EMAC) Clear statistics registers. \n#define AT91C_EMAC_ISR        ((unsigned int) 0x1 <<  6) // (EMAC) Increment statistics registers. \n#define AT91C_EMAC_WES        ((unsigned int) 0x1 <<  7) // (EMAC) Write enable for statistics registers. \n#define AT91C_EMAC_BP         ((unsigned int) 0x1 <<  8) // (EMAC) Back pressure. \n// -------- EMAC_CFG : (EMAC Offset: 0x4) Network Configuration Register -------- \n#define AT91C_EMAC_SPD        ((unsigned int) 0x1 <<  0) // (EMAC) Speed. \n#define AT91C_EMAC_FD         ((unsigned int) 0x1 <<  1) // (EMAC) Full duplex. \n#define AT91C_EMAC_BR         ((unsigned int) 0x1 <<  2) // (EMAC) Bit rate. \n#define AT91C_EMAC_CAF        ((unsigned int) 0x1 <<  4) // (EMAC) Copy all frames. \n#define AT91C_EMAC_NBC        ((unsigned int) 0x1 <<  5) // (EMAC) No broadcast. \n#define AT91C_EMAC_MTI        ((unsigned int) 0x1 <<  6) // (EMAC) Multicast hash enable\n#define AT91C_EMAC_UNI        ((unsigned int) 0x1 <<  7) // (EMAC) Unicast hash enable. \n#define AT91C_EMAC_BIG        ((unsigned int) 0x1 <<  8) // (EMAC) Receive 1522 bytes. \n#define AT91C_EMAC_EAE        ((unsigned int) 0x1 <<  9) // (EMAC) External address match enable. \n#define AT91C_EMAC_CLK        ((unsigned int) 0x3 << 10) // (EMAC) \n#define \tAT91C_EMAC_CLK_HCLK_8               ((unsigned int) 0x0 << 10) // (EMAC) HCLK divided by 8\n#define \tAT91C_EMAC_CLK_HCLK_16              ((unsigned int) 0x1 << 10) // (EMAC) HCLK divided by 16\n#define \tAT91C_EMAC_CLK_HCLK_32              ((unsigned int) 0x2 << 10) // (EMAC) HCLK divided by 32\n#define \tAT91C_EMAC_CLK_HCLK_64              ((unsigned int) 0x3 << 10) // (EMAC) HCLK divided by 64\n#define AT91C_EMAC_RTY        ((unsigned int) 0x1 << 12) // (EMAC) \n#define AT91C_EMAC_RMII       ((unsigned int) 0x1 << 13) // (EMAC) \n// -------- EMAC_SR : (EMAC Offset: 0x8) Network Status Register -------- \n#define AT91C_EMAC_MDIO       ((unsigned int) 0x1 <<  1) // (EMAC) \n#define AT91C_EMAC_IDLE       ((unsigned int) 0x1 <<  2) // (EMAC) \n// -------- EMAC_TCR : (EMAC Offset: 0x10) Transmit Control Register -------- \n#define AT91C_EMAC_LEN        ((unsigned int) 0x7FF <<  0) // (EMAC) \n#define AT91C_EMAC_NCRC       ((unsigned int) 0x1 << 15) // (EMAC) \n// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Control Register -------- \n#define AT91C_EMAC_OVR        ((unsigned int) 0x1 <<  0) // (EMAC) \n#define AT91C_EMAC_COL        ((unsigned int) 0x1 <<  1) // (EMAC) \n#define AT91C_EMAC_RLE        ((unsigned int) 0x1 <<  2) // (EMAC) \n#define AT91C_EMAC_TXIDLE     ((unsigned int) 0x1 <<  3) // (EMAC) \n#define AT91C_EMAC_BNQ        ((unsigned int) 0x1 <<  4) // (EMAC) \n#define AT91C_EMAC_COMP       ((unsigned int) 0x1 <<  5) // (EMAC) \n#define AT91C_EMAC_UND        ((unsigned int) 0x1 <<  6) // (EMAC) \n// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- \n#define AT91C_EMAC_BNA        ((unsigned int) 0x1 <<  0) // (EMAC) \n#define AT91C_EMAC_REC        ((unsigned int) 0x1 <<  1) // (EMAC) \n// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- \n#define AT91C_EMAC_DONE       ((unsigned int) 0x1 <<  0) // (EMAC) \n#define AT91C_EMAC_RCOM       ((unsigned int) 0x1 <<  1) // (EMAC) \n#define AT91C_EMAC_RBNA       ((unsigned int) 0x1 <<  2) // (EMAC) \n#define AT91C_EMAC_TOVR       ((unsigned int) 0x1 <<  3) // (EMAC) \n#define AT91C_EMAC_TUND       ((unsigned int) 0x1 <<  4) // (EMAC) \n#define AT91C_EMAC_RTRY       ((unsigned int) 0x1 <<  5) // (EMAC) \n#define AT91C_EMAC_TBRE       ((unsigned int) 0x1 <<  6) // (EMAC) \n#define AT91C_EMAC_TCOM       ((unsigned int) 0x1 <<  7) // (EMAC) \n#define AT91C_EMAC_TIDLE      ((unsigned int) 0x1 <<  8) // (EMAC) \n#define AT91C_EMAC_LINK       ((unsigned int) 0x1 <<  9) // (EMAC) \n#define AT91C_EMAC_ROVR       ((unsigned int) 0x1 << 10) // (EMAC) \n#define AT91C_EMAC_HRESP      ((unsigned int) 0x1 << 11) // (EMAC) \n// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- \n// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- \n// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- \n// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- \n#define AT91C_EMAC_DATA       ((unsigned int) 0xFFFF <<  0) // (EMAC) \n#define AT91C_EMAC_CODE       ((unsigned int) 0x3 << 16) // (EMAC) \n#define AT91C_EMAC_REGA       ((unsigned int) 0x1F << 18) // (EMAC) \n#define AT91C_EMAC_PHYA       ((unsigned int) 0x1F << 23) // (EMAC) \n#define AT91C_EMAC_RW         ((unsigned int) 0x3 << 28) // (EMAC) \n#define AT91C_EMAC_HIGH       ((unsigned int) 0x1 << 30) // (EMAC) \n#define AT91C_EMAC_LOW        ((unsigned int) 0x1 << 31) // (EMAC) \n\n// *****************************************************************************\n//              SOFTWARE API DEFINITION  FOR External Bus Interface\n// *****************************************************************************\ntypedef struct _AT91S_EBI {\n\tAT91_REG\t EBI_CSA; \t// Chip Select Assignment Register\n\tAT91_REG\t EBI_CFGR; \t// Configuration Register\n} AT91S_EBI, *AT91PS_EBI;\n\n// -------- EBI_CSA : (EBI Offset: 0x0) Chip Select Assignment Register -------- \n#define AT91C_EBI_CS0A        ((unsigned int) 0x1 <<  0) // (EBI) Chip Select 0 Assignment\n#define \tAT91C_EBI_CS0A_SMC                  ((unsigned int) 0x0) // (EBI) Chip Select 0 is assigned to the Static Memory Controller.\n#define \tAT91C_EBI_CS0A_BFC                  ((unsigned int) 0x1) // (EBI) Chip Select 0 is assigned to the Burst Flash Controller.\n#define AT91C_EBI_CS1A        ((unsigned int) 0x1 <<  1) // (EBI) Chip Select 1 Assignment\n#define \tAT91C_EBI_CS1A_SMC                  ((unsigned int) 0x0 <<  1) // (EBI) Chip Select 1 is assigned to the Static Memory Controller.\n#define \tAT91C_EBI_CS1A_SDRAMC               ((unsigned int) 0x1 <<  1) // (EBI) Chip Select 1 is assigned to the SDRAM Controller.\n#define AT91C_EBI_CS3A        ((unsigned int) 0x1 <<  3) // (EBI) Chip Select 3 Assignment\n#define \tAT91C_EBI_CS3A_SMC                  ((unsigned int) 0x0 <<  3) // (EBI) Chip Select 3 is only assigned to the Static Memory Controller and NCS3 behaves as defined by the SMC2.\n#define \tAT91C_EBI_CS3A_SMC_SmartMedia       ((unsigned int) 0x1 <<  3) // (EBI) Chip Select 3 is assigned to the Static Memory Controller and the SmartMedia Logic is activated.\n#define AT91C_EBI_CS4A        ((unsigned int) 0x1 <<  4) // (EBI) Chip Select 4 Assignment\n#define \tAT91C_EBI_CS4A_SMC                  ((unsigned int) 0x0 <<  4) // (EBI) Chip Select 4 is assigned to the Static Memory Controller and NCS4,NCS5 and NCS6 behave as defined by the SMC2.\n#define \tAT91C_EBI_CS4A_SMC_CompactFlash     ((unsigned int) 0x1 <<  4) // (EBI) Chip Select 4 is assigned to the Static Memory Controller and the CompactFlash Logic is activated.\n// -------- EBI_CFGR : (EBI Offset: 0x4) Configuration Register -------- \n#define AT91C_EBI_DBPUC       ((unsigned int) 0x1 <<  0) // (EBI) Data Bus Pull-Up Configuration\n#define AT91C_EBI_EBSEN       ((unsigned int) 0x1 <<  1) // (EBI) Bus Sharing Enable\n\n// *****************************************************************************\n//              SOFTWARE API DEFINITION  FOR Static Memory Controller 2 Interface\n// *****************************************************************************\ntypedef struct _AT91S_SMC2 {\n\tAT91_REG\t SMC2_CSR[8]; \t// SMC2 Chip Select Register\n} AT91S_SMC2, *AT91PS_SMC2;\n\n// -------- SMC2_CSR : (SMC2 Offset: 0x0) SMC2 Chip Select Register -------- \n#define AT91C_SMC2_NWS        ((unsigned int) 0x7F <<  0) // (SMC2) Number of Wait States\n#define AT91C_SMC2_WSEN       ((unsigned int) 0x1 <<  7) // (SMC2) Wait State Enable\n#define AT91C_SMC2_TDF        ((unsigned int) 0xF <<  8) // (SMC2) Data Float Time\n#define AT91C_SMC2_BAT        ((unsigned int) 0x1 << 12) // (SMC2) Byte Access Type\n#define AT91C_SMC2_DBW        ((unsigned int) 0x1 << 13) // (SMC2) Data Bus Width\n#define \tAT91C_SMC2_DBW_16                   ((unsigned int) 0x1 << 13) // (SMC2) 16-bit.\n#define \tAT91C_SMC2_DBW_8                    ((unsigned int) 0x2 << 13) // (SMC2) 8-bit.\n#define AT91C_SMC2_DRP        ((unsigned int) 0x1 << 15) // (SMC2) Data Read Protocol\n#define AT91C_SMC2_ACSS       ((unsigned int) 0x3 << 16) // (SMC2) Address to Chip Select Setup\n#define \tAT91C_SMC2_ACSS_STANDARD             ((unsigned int) 0x0 << 16) // (SMC2) Standard, asserted at the beginning of the access and deasserted at the end.\n#define \tAT91C_SMC2_ACSS_1_CYCLE              ((unsigned int) 0x1 << 16) // (SMC2) One cycle less at the beginning and the end of the access.\n#define \tAT91C_SMC2_ACSS_2_CYCLES             ((unsigned int) 0x2 << 16) // (SMC2) Two cycles less at the beginning and the end of the access.\n#define \tAT91C_SMC2_ACSS_3_CYCLES             ((unsigned int) 0x3 << 16) // (SMC2) Three cycles less at the beginning and the end of the access.\n#define AT91C_SMC2_RWSETUP    ((unsigned int) 0x7 << 24) // (SMC2) Read and Write Signal Setup Time\n#define AT91C_SMC2_RWHOLD     ((unsigned int) 0x7 << 29) // (SMC2) Read and Write Signal Hold Time\n\n// *****************************************************************************\n//              SOFTWARE API DEFINITION  FOR SDRAM Controller Interface\n// *****************************************************************************\ntypedef struct _AT91S_SDRC {\n\tAT91_REG\t SDRC_MR; \t// SDRAM Controller Mode Register\n\tAT91_REG\t SDRC_TR; \t// SDRAM Controller Refresh Timer Register\n\tAT91_REG\t SDRC_CR; \t// SDRAM Controller Configuration Register\n\tAT91_REG\t SDRC_SRR; \t// SDRAM Controller Self Refresh Register\n\tAT91_REG\t SDRC_LPR; \t// SDRAM Controller Low Power Register\n\tAT91_REG\t SDRC_IER; \t// SDRAM Controller Interrupt Enable Register\n\tAT91_REG\t SDRC_IDR; \t// SDRAM Controller Interrupt Disable Register\n\tAT91_REG\t SDRC_IMR; \t// SDRAM Controller Interrupt Mask Register\n\tAT91_REG\t SDRC_ISR; \t// SDRAM Controller Interrupt Mask Register\n} AT91S_SDRC, *AT91PS_SDRC;\n\n// -------- SDRC_MR : (SDRC Offset: 0x0) SDRAM Controller Mode Register -------- \n#define AT91C_SDRC_MODE       ((unsigned int) 0xF <<  0) // (SDRC) Mode\n#define \tAT91C_SDRC_MODE_NORMAL_CMD           ((unsigned int) 0x0) // (SDRC) Normal Mode\n#define \tAT91C_SDRC_MODE_NOP_CMD              ((unsigned int) 0x1) // (SDRC) NOP Command\n#define \tAT91C_SDRC_MODE_PRCGALL_CMD          ((unsigned int) 0x2) // (SDRC) All Banks Precharge Command\n#define \tAT91C_SDRC_MODE_LMR_CMD              ((unsigned int) 0x3) // (SDRC) Load Mode Register Command\n#define \tAT91C_SDRC_MODE_RFSH_CMD             ((unsigned int) 0x4) // (SDRC) Refresh Command\n#define AT91C_SDRC_DBW        ((unsigned int) 0x1 <<  4) // (SDRC) Data Bus Width\n#define \tAT91C_SDRC_DBW_32_BITS              ((unsigned int) 0x0 <<  4) // (SDRC) 32 Bits datas bus\n#define \tAT91C_SDRC_DBW_16_BITS              ((unsigned int) 0x1 <<  4) // (SDRC) 16 Bits datas bus\n// -------- SDRC_TR : (SDRC Offset: 0x4) SDRC Refresh Timer Register -------- \n#define AT91C_SDRC_COUNT      ((unsigned int) 0xFFF <<  0) // (SDRC) Refresh Counter\n// -------- SDRC_CR : (SDRC Offset: 0x8) SDRAM Configuration Register -------- \n#define AT91C_SDRC_NC         ((unsigned int) 0x3 <<  0) // (SDRC) Number of Column Bits\n#define \tAT91C_SDRC_NC_8                    ((unsigned int) 0x0) // (SDRC) 8 Bits\n#define \tAT91C_SDRC_NC_9                    ((unsigned int) 0x1) // (SDRC) 9 Bits\n#define \tAT91C_SDRC_NC_10                   ((unsigned int) 0x2) // (SDRC) 10 Bits\n#define \tAT91C_SDRC_NC_11                   ((unsigned int) 0x3) // (SDRC) 11 Bits\n#define AT91C_SDRC_NR         ((unsigned int) 0x3 <<  2) // (SDRC) Number of Row Bits\n#define \tAT91C_SDRC_NR_11                   ((unsigned int) 0x0 <<  2) // (SDRC) 11 Bits\n#define \tAT91C_SDRC_NR_12                   ((unsigned int) 0x1 <<  2) // (SDRC) 12 Bits\n#define \tAT91C_SDRC_NR_13                   ((unsigned int) 0x2 <<  2) // (SDRC) 13 Bits\n#define AT91C_SDRC_NB         ((unsigned int) 0x1 <<  4) // (SDRC) Number of Banks\n#define \tAT91C_SDRC_NB_2_BANKS              ((unsigned int) 0x0 <<  4) // (SDRC) 2 banks\n#define \tAT91C_SDRC_NB_4_BANKS              ((unsigned int) 0x1 <<  4) // (SDRC) 4 banks\n#define AT91C_SDRC_CAS        ((unsigned int) 0x3 <<  5) // (SDRC) CAS Latency\n#define \tAT91C_SDRC_CAS_2                    ((unsigned int) 0x2 <<  5) // (SDRC) 2 cycles\n#define AT91C_SDRC_TWR        ((unsigned int) 0xF <<  7) // (SDRC) Number of Write Recovery Time Cycles\n#define AT91C_SDRC_TRC        ((unsigned int) 0xF << 11) // (SDRC) Number of RAS Cycle Time Cycles\n#define AT91C_SDRC_TRP        ((unsigned int) 0xF << 15) // (SDRC) Number of RAS Precharge Time Cycles\n#define AT91C_SDRC_TRCD       ((unsigned int) 0xF << 19) // (SDRC) Number of RAS to CAS Delay Cycles\n#define AT91C_SDRC_TRAS       ((unsigned int) 0xF << 23) // (SDRC) Number of RAS Active Time Cycles\n#define AT91C_SDRC_TXSR       ((unsigned int) 0xF << 27) // (SDRC) Number of Command Recovery Time Cycles\n// -------- SDRC_SRR : (SDRC Offset: 0xc) SDRAM Controller Self-refresh Register -------- \n#define AT91C_SDRC_SRCB       ((unsigned int) 0x1 <<  0) // (SDRC) Self-refresh Command Bit\n// -------- SDRC_LPR : (SDRC Offset: 0x10) SDRAM Controller Low-power Register -------- \n#define AT91C_SDRC_LPCB       ((unsigned int) 0x1 <<  0) // (SDRC) Low-power Command Bit\n// -------- SDRC_IER : (SDRC Offset: 0x14) SDRAM Controller Interrupt Enable Register -------- \n#define AT91C_SDRC_RES        ((unsigned int) 0x1 <<  0) // (SDRC) Refresh Error Status\n// -------- SDRC_IDR : (SDRC Offset: 0x18) SDRAM Controller Interrupt Disable Register -------- \n// -------- SDRC_IMR : (SDRC Offset: 0x1c) SDRAM Controller Interrupt Mask Register -------- \n// -------- SDRC_ISR : (SDRC Offset: 0x20) SDRAM Controller Interrupt Status Register -------- \n\n// *****************************************************************************\n//              SOFTWARE API DEFINITION  FOR Burst Flash Controller Interface\n// *****************************************************************************\ntypedef struct _AT91S_BFC {\n\tAT91_REG\t BFC_MR; \t// BFC Mode Register\n} AT91S_BFC, *AT91PS_BFC;\n\n// -------- BFC_MR : (BFC Offset: 0x0) BFC Mode Register -------- \n#define AT91C_BFC_BFCOM       ((unsigned int) 0x3 <<  0) // (BFC) Burst Flash Controller Operating Mode\n#define \tAT91C_BFC_BFCOM_DISABLED             ((unsigned int) 0x0) // (BFC) NPCS0 is driven by the SMC or remains high.\n#define \tAT91C_BFC_BFCOM_ASYNC                ((unsigned int) 0x1) // (BFC) Asynchronous\n#define \tAT91C_BFC_BFCOM_BURST_READ           ((unsigned int) 0x2) // (BFC) Burst Read\n#define AT91C_BFC_BFCC        ((unsigned int) 0x3 <<  2) // (BFC) Burst Flash Controller Operating Mode\n#define \tAT91C_BFC_BFCC_MCK                  ((unsigned int) 0x1 <<  2) // (BFC) Master Clock.\n#define \tAT91C_BFC_BFCC_MCK_DIV_2            ((unsigned int) 0x2 <<  2) // (BFC) Master Clock divided by 2.\n#define \tAT91C_BFC_BFCC_MCK_DIV_4            ((unsigned int) 0x3 <<  2) // (BFC) Master Clock divided by 4.\n#define AT91C_BFC_AVL         ((unsigned int) 0xF <<  4) // (BFC) Address Valid Latency\n#define AT91C_BFC_PAGES       ((unsigned int) 0x7 <<  8) // (BFC) Page Size\n#define \tAT91C_BFC_PAGES_NO_PAGE              ((unsigned int) 0x0 <<  8) // (BFC) No page handling.\n#define \tAT91C_BFC_PAGES_16                   ((unsigned int) 0x1 <<  8) // (BFC) 16 bytes page size.\n#define \tAT91C_BFC_PAGES_32                   ((unsigned int) 0x2 <<  8) // (BFC) 32 bytes page size.\n#define \tAT91C_BFC_PAGES_64                   ((unsigned int) 0x3 <<  8) // (BFC) 64 bytes page size.\n#define \tAT91C_BFC_PAGES_128                  ((unsigned int) 0x4 <<  8) // (BFC) 128 bytes page size.\n#define \tAT91C_BFC_PAGES_256                  ((unsigned int) 0x5 <<  8) // (BFC) 256 bytes page size.\n#define \tAT91C_BFC_PAGES_512                  ((unsigned int) 0x6 <<  8) // (BFC) 512 bytes page size.\n#define \tAT91C_BFC_PAGES_1024                 ((unsigned int) 0x7 <<  8) // (BFC) 1024 bytes page size.\n#define AT91C_BFC_OEL         ((unsigned int) 0x3 << 12) // (BFC) Output Enable Latency\n#define AT91C_BFC_BAAEN       ((unsigned int) 0x1 << 16) // (BFC) Burst Address Advance Enable\n#define AT91C_BFC_BFOEH       ((unsigned int) 0x1 << 17) // (BFC) Burst Flash Output Enable Handling\n#define AT91C_BFC_MUXEN       ((unsigned int) 0x1 << 18) // (BFC) Multiplexed Bus Enable\n#define AT91C_BFC_RDYEN       ((unsigned int) 0x1 << 19) // (BFC) Ready Enable Mode\n\n// *****************************************************************************\n//               REGISTER ADDRESS DEFINITION FOR AT91RM9200\n// *****************************************************************************\n// ========== Register definition for SYS peripheral ========== \n// ========== Register definition for MC peripheral ========== \n#define AT91C_MC_PUER   ((AT91_REG *) \t0xFFFFFF54) // (MC) MC Protection Unit Enable Register\n#define AT91C_MC_ASR    ((AT91_REG *) \t0xFFFFFF04) // (MC) MC Abort Status Register\n#define AT91C_MC_PUP    ((AT91_REG *) \t0xFFFFFF50) // (MC) MC Protection Unit Peripherals\n#define AT91C_MC_PUIA   ((AT91_REG *) \t0xFFFFFF10) // (MC) MC Protection Unit Area\n#define AT91C_MC_AASR   ((AT91_REG *) \t0xFFFFFF08) // (MC) MC Abort Address Status Register\n#define AT91C_MC_RCR    ((AT91_REG *) \t0xFFFFFF00) // (MC) MC Remap Control Register\n// ========== Register definition for RTC peripheral ========== \n#define AT91C_RTC_IMR   ((AT91_REG *) \t0xFFFFFE28) // (RTC) Interrupt Mask Register\n#define AT91C_RTC_IER   ((AT91_REG *) \t0xFFFFFE20) // (RTC) Interrupt Enable Register\n#define AT91C_RTC_SR    ((AT91_REG *) \t0xFFFFFE18) // (RTC) Status Register\n#define AT91C_RTC_TIMALR ((AT91_REG *) \t0xFFFFFE10) // (RTC) Time Alarm Register\n#define AT91C_RTC_TIMR  ((AT91_REG *) \t0xFFFFFE08) // (RTC) Time Register\n#define AT91C_RTC_CR    ((AT91_REG *) \t0xFFFFFE00) // (RTC) Control Register\n#define AT91C_RTC_VER   ((AT91_REG *) \t0xFFFFFE2C) // (RTC) Valid Entry Register\n#define AT91C_RTC_IDR   ((AT91_REG *) \t0xFFFFFE24) // (RTC) Interrupt Disable Register\n#define AT91C_RTC_SCCR  ((AT91_REG *) \t0xFFFFFE1C) // (RTC) Status Clear Command Register\n#define AT91C_RTC_CALALR ((AT91_REG *) \t0xFFFFFE14) // (RTC) Calendar Alarm Register\n#define AT91C_RTC_CALR  ((AT91_REG *) \t0xFFFFFE0C) // (RTC) Calendar Register\n#define AT91C_RTC_MR    ((AT91_REG *) \t0xFFFFFE04) // (RTC) Mode Register\n// ========== Register definition for ST peripheral ========== \n#define AT91C_ST_CRTR   ((AT91_REG *) \t0xFFFFFD24) // (ST) Current Real-time Register\n#define AT91C_ST_IMR    ((AT91_REG *) \t0xFFFFFD1C) // (ST) Interrupt Mask Register\n#define AT91C_ST_IER    ((AT91_REG *) \t0xFFFFFD14) // (ST) Interrupt Enable Register\n#define AT91C_ST_RTMR   ((AT91_REG *) \t0xFFFFFD0C) // (ST) Real-time Mode Register\n#define AT91C_ST_PIMR   ((AT91_REG *) \t0xFFFFFD04) // (ST) Period Interval Mode Register\n#define AT91C_ST_RTAR   ((AT91_REG *) \t0xFFFFFD20) // (ST) Real-time Alarm Register\n#define AT91C_ST_IDR    ((AT91_REG *) \t0xFFFFFD18) // (ST) Interrupt Disable Register\n#define AT91C_ST_SR     ((AT91_REG *) \t0xFFFFFD10) // (ST) Status Register\n#define AT91C_ST_WDMR   ((AT91_REG *) \t0xFFFFFD08) // (ST) Watchdog Mode Register\n#define AT91C_ST_CR     ((AT91_REG *) \t0xFFFFFD00) // (ST) Control Register\n// ========== Register definition for PMC peripheral ========== \n#define AT91C_PMC_SCSR  ((AT91_REG *) \t0xFFFFFC08) // (PMC) System Clock Status Register\n#define AT91C_PMC_SCER  ((AT91_REG *) \t0xFFFFFC00) // (PMC) System Clock Enable Register\n#define AT91C_PMC_IMR   ((AT91_REG *) \t0xFFFFFC6C) // (PMC) Interrupt Mask Register\n#define AT91C_PMC_IDR   ((AT91_REG *) \t0xFFFFFC64) // (PMC) Interrupt Disable Register\n#define AT91C_PMC_PCDR  ((AT91_REG *) \t0xFFFFFC14) // (PMC) Peripheral Clock Disable Register\n#define AT91C_PMC_SCDR  ((AT91_REG *) \t0xFFFFFC04) // (PMC) System Clock Disable Register\n#define AT91C_PMC_SR    ((AT91_REG *) \t0xFFFFFC68) // (PMC) Status Register\n#define AT91C_PMC_IER   ((AT91_REG *) \t0xFFFFFC60) // (PMC) Interrupt Enable Register\n#define AT91C_PMC_MCKR  ((AT91_REG *) \t0xFFFFFC30) // (PMC) Master Clock Register\n#define AT91C_PMC_PCER  ((AT91_REG *) \t0xFFFFFC10) // (PMC) Peripheral Clock Enable Register\n#define AT91C_PMC_PCSR  ((AT91_REG *) \t0xFFFFFC18) // (PMC) Peripheral Clock Status Register\n#define AT91C_PMC_PCKR  ((AT91_REG *) \t0xFFFFFC40) // (PMC) Programmable Clock Register\n// ========== Register definition for CKGR peripheral ========== \n#define AT91C_CKGR_PLLBR ((AT91_REG *) \t0xFFFFFC2C) // (CKGR) PLL B Register\n#define AT91C_CKGR_MCFR ((AT91_REG *) \t0xFFFFFC24) // (CKGR) Main Clock  Frequency Register\n#define AT91C_CKGR_PLLAR ((AT91_REG *) \t0xFFFFFC28) // (CKGR) PLL A Register\n#define AT91C_CKGR_MOR  ((AT91_REG *) \t0xFFFFFC20) // (CKGR) Main Oscillator Register\n// ========== Register definition for PIOD peripheral ========== \n#define AT91C_PIOD_PDSR ((AT91_REG *) \t0xFFFFFA3C) // (PIOD) Pin Data Status Register\n#define AT91C_PIOD_CODR ((AT91_REG *) \t0xFFFFFA34) // (PIOD) Clear Output Data Register\n#define AT91C_PIOD_OWER ((AT91_REG *) \t0xFFFFFAA0) // (PIOD) Output Write Enable Register\n#define AT91C_PIOD_MDER ((AT91_REG *) \t0xFFFFFA50) // (PIOD) Multi-driver Enable Register\n#define AT91C_PIOD_IMR  ((AT91_REG *) \t0xFFFFFA48) // (PIOD) Interrupt Mask Register\n#define AT91C_PIOD_IER  ((AT91_REG *) \t0xFFFFFA40) // (PIOD) Interrupt Enable Register\n#define AT91C_PIOD_ODSR ((AT91_REG *) \t0xFFFFFA38) // (PIOD) Output Data Status Register\n#define AT91C_PIOD_SODR ((AT91_REG *) \t0xFFFFFA30) // (PIOD) Set Output Data Register\n#define AT91C_PIOD_PER  ((AT91_REG *) \t0xFFFFFA00) // (PIOD) PIO Enable Register\n#define AT91C_PIOD_OWDR ((AT91_REG *) \t0xFFFFFAA4) // (PIOD) Output Write Disable Register\n#define AT91C_PIOD_PPUER ((AT91_REG *) \t0xFFFFFA64) // (PIOD) Pull-up Enable Register\n#define AT91C_PIOD_MDDR ((AT91_REG *) \t0xFFFFFA54) // (PIOD) Multi-driver Disable Register\n#define AT91C_PIOD_ISR  ((AT91_REG *) \t0xFFFFFA4C) // (PIOD) Interrupt Status Register\n#define AT91C_PIOD_IDR  ((AT91_REG *) \t0xFFFFFA44) // (PIOD) Interrupt Disable Register\n#define AT91C_PIOD_PDR  ((AT91_REG *) \t0xFFFFFA04) // (PIOD) PIO Disable Register\n#define AT91C_PIOD_ODR  ((AT91_REG *) \t0xFFFFFA14) // (PIOD) Output Disable Registerr\n#define AT91C_PIOD_OWSR ((AT91_REG *) \t0xFFFFFAA8) // (PIOD) Output Write Status Register\n#define AT91C_PIOD_ABSR ((AT91_REG *) \t0xFFFFFA78) // (PIOD) AB Select Status Register\n#define AT91C_PIOD_ASR  ((AT91_REG *) \t0xFFFFFA70) // (PIOD) Select A Register\n#define AT91C_PIOD_PPUSR ((AT91_REG *) \t0xFFFFFA68) // (PIOD) Pad Pull-up Status Register\n#define AT91C_PIOD_PPUDR ((AT91_REG *) \t0xFFFFFA60) // (PIOD) Pull-up Disable Register\n#define AT91C_PIOD_MDSR ((AT91_REG *) \t0xFFFFFA58) // (PIOD) Multi-driver Status Register\n#define AT91C_PIOD_PSR  ((AT91_REG *) \t0xFFFFFA08) // (PIOD) PIO Status Register\n#define AT91C_PIOD_OER  ((AT91_REG *) \t0xFFFFFA10) // (PIOD) Output Enable Register\n#define AT91C_PIOD_OSR  ((AT91_REG *) \t0xFFFFFA18) // (PIOD) Output Status Register\n#define AT91C_PIOD_IFER ((AT91_REG *) \t0xFFFFFA20) // (PIOD) Input Filter Enable Register\n#define AT91C_PIOD_BSR  ((AT91_REG *) \t0xFFFFFA74) // (PIOD) Select B Register\n#define AT91C_PIOD_IFDR ((AT91_REG *) \t0xFFFFFA24) // (PIOD) Input Filter Disable Register\n#define AT91C_PIOD_IFSR ((AT91_REG *) \t0xFFFFFA28) // (PIOD) Input Filter Status Register\n// ========== Register definition for PIOC peripheral ========== \n#define AT91C_PIOC_IFDR ((AT91_REG *) \t0xFFFFF824) // (PIOC) Input Filter Disable Register\n#define AT91C_PIOC_ODR  ((AT91_REG *) \t0xFFFFF814) // (PIOC) Output Disable Registerr\n#define AT91C_PIOC_ABSR ((AT91_REG *) \t0xFFFFF878) // (PIOC) AB Select Status Register\n#define AT91C_PIOC_SODR ((AT91_REG *) \t0xFFFFF830) // (PIOC) Set Output Data Register\n#define AT91C_PIOC_IFSR ((AT91_REG *) \t0xFFFFF828) // (PIOC) Input Filter Status Register\n#define AT91C_PIOC_CODR ((AT91_REG *) \t0xFFFFF834) // (PIOC) Clear Output Data Register\n#define AT91C_PIOC_ODSR ((AT91_REG *) \t0xFFFFF838) // (PIOC) Output Data Status Register\n#define AT91C_PIOC_IER  ((AT91_REG *) \t0xFFFFF840) // (PIOC) Interrupt Enable Register\n#define AT91C_PIOC_IMR  ((AT91_REG *) \t0xFFFFF848) // (PIOC) Interrupt Mask Register\n#define AT91C_PIOC_OWDR ((AT91_REG *) \t0xFFFFF8A4) // (PIOC) Output Write Disable Register\n#define AT91C_PIOC_MDDR ((AT91_REG *) \t0xFFFFF854) // (PIOC) Multi-driver Disable Register\n#define AT91C_PIOC_PDSR ((AT91_REG *) \t0xFFFFF83C) // (PIOC) Pin Data Status Register\n#define AT91C_PIOC_IDR  ((AT91_REG *) \t0xFFFFF844) // (PIOC) Interrupt Disable Register\n#define AT91C_PIOC_ISR  ((AT91_REG *) \t0xFFFFF84C) // (PIOC) Interrupt Status Register\n#define AT91C_PIOC_PDR  ((AT91_REG *) \t0xFFFFF804) // (PIOC) PIO Disable Register\n#define AT91C_PIOC_OWSR ((AT91_REG *) \t0xFFFFF8A8) // (PIOC) Output Write Status Register\n#define AT91C_PIOC_OWER ((AT91_REG *) \t0xFFFFF8A0) // (PIOC) Output Write Enable Register\n#define AT91C_PIOC_ASR  ((AT91_REG *) \t0xFFFFF870) // (PIOC) Select A Register\n#define AT91C_PIOC_PPUSR ((AT91_REG *) \t0xFFFFF868) // (PIOC) Pad Pull-up Status Register\n#define AT91C_PIOC_PPUDR ((AT91_REG *) \t0xFFFFF860) // (PIOC) Pull-up Disable Register\n#define AT91C_PIOC_MDSR ((AT91_REG *) \t0xFFFFF858) // (PIOC) Multi-driver Status Register\n#define AT91C_PIOC_MDER ((AT91_REG *) \t0xFFFFF850) // (PIOC) Multi-driver Enable Register\n#define AT91C_PIOC_IFER ((AT91_REG *) \t0xFFFFF820) // (PIOC) Input Filter Enable Register\n#define AT91C_PIOC_OSR  ((AT91_REG *) \t0xFFFFF818) // (PIOC) Output Status Register\n#define AT91C_PIOC_OER  ((AT91_REG *) \t0xFFFFF810) // (PIOC) Output Enable Register\n#define AT91C_PIOC_PSR  ((AT91_REG *) \t0xFFFFF808) // (PIOC) PIO Status Register\n#define AT91C_PIOC_PER  ((AT91_REG *) \t0xFFFFF800) // (PIOC) PIO Enable Register\n#define AT91C_PIOC_BSR  ((AT91_REG *) \t0xFFFFF874) // (PIOC) Select B Register\n#define AT91C_PIOC_PPUER ((AT91_REG *) \t0xFFFFF864) // (PIOC) Pull-up Enable Register\n// ========== Register definition for PIOB peripheral ========== \n#define AT91C_PIOB_OWSR ((AT91_REG *) \t0xFFFFF6A8) // (PIOB) Output Write Status Register\n#define AT91C_PIOB_PPUSR ((AT91_REG *) \t0xFFFFF668) // (PIOB) Pad Pull-up Status Register\n#define AT91C_PIOB_PPUDR ((AT91_REG *) \t0xFFFFF660) // (PIOB) Pull-up Disable Register\n#define AT91C_PIOB_MDSR ((AT91_REG *) \t0xFFFFF658) // (PIOB) Multi-driver Status Register\n#define AT91C_PIOB_MDER ((AT91_REG *) \t0xFFFFF650) // (PIOB) Multi-driver Enable Register\n#define AT91C_PIOB_IMR  ((AT91_REG *) \t0xFFFFF648) // (PIOB) Interrupt Mask Register\n#define AT91C_PIOB_OSR  ((AT91_REG *) \t0xFFFFF618) // (PIOB) Output Status Register\n#define AT91C_PIOB_OER  ((AT91_REG *) \t0xFFFFF610) // (PIOB) Output Enable Register\n#define AT91C_PIOB_PSR  ((AT91_REG *) \t0xFFFFF608) // (PIOB) PIO Status Register\n#define AT91C_PIOB_PER  ((AT91_REG *) \t0xFFFFF600) // (PIOB) PIO Enable Register\n#define AT91C_PIOB_BSR  ((AT91_REG *) \t0xFFFFF674) // (PIOB) Select B Register\n#define AT91C_PIOB_PPUER ((AT91_REG *) \t0xFFFFF664) // (PIOB) Pull-up Enable Register\n#define AT91C_PIOB_IFDR ((AT91_REG *) \t0xFFFFF624) // (PIOB) Input Filter Disable Register\n#define AT91C_PIOB_ODR  ((AT91_REG *) \t0xFFFFF614) // (PIOB) Output Disable Registerr\n#define AT91C_PIOB_ABSR ((AT91_REG *) \t0xFFFFF678) // (PIOB) AB Select Status Register\n#define AT91C_PIOB_ASR  ((AT91_REG *) \t0xFFFFF670) // (PIOB) Select A Register\n#define AT91C_PIOB_IFER ((AT91_REG *) \t0xFFFFF620) // (PIOB) Input Filter Enable Register\n#define AT91C_PIOB_IFSR ((AT91_REG *) \t0xFFFFF628) // (PIOB) Input Filter Status Register\n#define AT91C_PIOB_SODR ((AT91_REG *) \t0xFFFFF630) // (PIOB) Set Output Data Register\n#define AT91C_PIOB_ODSR ((AT91_REG *) \t0xFFFFF638) // (PIOB) Output Data Status Register\n#define AT91C_PIOB_CODR ((AT91_REG *) \t0xFFFFF634) // (PIOB) Clear Output Data Register\n#define AT91C_PIOB_PDSR ((AT91_REG *) \t0xFFFFF63C) // (PIOB) Pin Data Status Register\n#define AT91C_PIOB_OWER ((AT91_REG *) \t0xFFFFF6A0) // (PIOB) Output Write Enable Register\n#define AT91C_PIOB_IER  ((AT91_REG *) \t0xFFFFF640) // (PIOB) Interrupt Enable Register\n#define AT91C_PIOB_OWDR ((AT91_REG *) \t0xFFFFF6A4) // (PIOB) Output Write Disable Register\n#define AT91C_PIOB_MDDR ((AT91_REG *) \t0xFFFFF654) // (PIOB) Multi-driver Disable Register\n#define AT91C_PIOB_ISR  ((AT91_REG *) \t0xFFFFF64C) // (PIOB) Interrupt Status Register\n#define AT91C_PIOB_IDR  ((AT91_REG *) \t0xFFFFF644) // (PIOB) Interrupt Disable Register\n#define AT91C_PIOB_PDR  ((AT91_REG *) \t0xFFFFF604) // (PIOB) PIO Disable Register\n// ========== Register definition for PIOA peripheral ========== \n#define AT91C_PIOA_IMR  ((AT91_REG *) \t0xFFFFF448) // (PIOA) Interrupt Mask Register\n#define AT91C_PIOA_IER  ((AT91_REG *) \t0xFFFFF440) // (PIOA) Interrupt Enable Register\n#define AT91C_PIOA_OWDR ((AT91_REG *) \t0xFFFFF4A4) // (PIOA) Output Write Disable Register\n#define AT91C_PIOA_ISR  ((AT91_REG *) \t0xFFFFF44C) // (PIOA) Interrupt Status Register\n#define AT91C_PIOA_PPUDR ((AT91_REG *) \t0xFFFFF460) // (PIOA) Pull-up Disable Register\n#define AT91C_PIOA_MDSR ((AT91_REG *) \t0xFFFFF458) // (PIOA) Multi-driver Status Register\n#define AT91C_PIOA_MDER ((AT91_REG *) \t0xFFFFF450) // (PIOA) Multi-driver Enable Register\n#define AT91C_PIOA_PER  ((AT91_REG *) \t0xFFFFF400) // (PIOA) PIO Enable Register\n#define AT91C_PIOA_PSR  ((AT91_REG *) \t0xFFFFF408) // (PIOA) PIO Status Register\n#define AT91C_PIOA_OER  ((AT91_REG *) \t0xFFFFF410) // (PIOA) Output Enable Register\n#define AT91C_PIOA_BSR  ((AT91_REG *) \t0xFFFFF474) // (PIOA) Select B Register\n#define AT91C_PIOA_PPUER ((AT91_REG *) \t0xFFFFF464) // (PIOA) Pull-up Enable Register\n#define AT91C_PIOA_MDDR ((AT91_REG *) \t0xFFFFF454) // (PIOA) Multi-driver Disable Register\n#define AT91C_PIOA_PDR  ((AT91_REG *) \t0xFFFFF404) // (PIOA) PIO Disable Register\n#define AT91C_PIOA_ODR  ((AT91_REG *) \t0xFFFFF414) // (PIOA) Output Disable Registerr\n#define AT91C_PIOA_IFDR ((AT91_REG *) \t0xFFFFF424) // (PIOA) Input Filter Disable Register\n#define AT91C_PIOA_ABSR ((AT91_REG *) \t0xFFFFF478) // (PIOA) AB Select Status Register\n#define AT91C_PIOA_ASR  ((AT91_REG *) \t0xFFFFF470) // (PIOA) Select A Register\n#define AT91C_PIOA_PPUSR ((AT91_REG *) \t0xFFFFF468) // (PIOA) Pad Pull-up Status Register\n#define AT91C_PIOA_ODSR ((AT91_REG *) \t0xFFFFF438) // (PIOA) Output Data Status Register\n#define AT91C_PIOA_SODR ((AT91_REG *) \t0xFFFFF430) // (PIOA) Set Output Data Register\n#define AT91C_PIOA_IFSR ((AT91_REG *) \t0xFFFFF428) // (PIOA) Input Filter Status Register\n#define AT91C_PIOA_IFER ((AT91_REG *) \t0xFFFFF420) // (PIOA) Input Filter Enable Register\n#define AT91C_PIOA_OSR  ((AT91_REG *) \t0xFFFFF418) // (PIOA) Output Status Register\n#define AT91C_PIOA_IDR  ((AT91_REG *) \t0xFFFFF444) // (PIOA) Interrupt Disable Register\n#define AT91C_PIOA_PDSR ((AT91_REG *) \t0xFFFFF43C) // (PIOA) Pin Data Status Register\n#define AT91C_PIOA_CODR ((AT91_REG *) \t0xFFFFF434) // (PIOA) Clear Output Data Register\n#define AT91C_PIOA_OWSR ((AT91_REG *) \t0xFFFFF4A8) // (PIOA) Output Write Status Register\n#define AT91C_PIOA_OWER ((AT91_REG *) \t0xFFFFF4A0) // (PIOA) Output Write Enable Register\n// ========== Register definition for DBGU peripheral ========== \n#define AT91C_DBGU_C2R  ((AT91_REG *) \t0xFFFFF244) // (DBGU) Chip ID2 Register\n#define AT91C_DBGU_THR  ((AT91_REG *) \t0xFFFFF21C) // (DBGU) Transmitter Holding Register\n#define AT91C_DBGU_CSR  ((AT91_REG *) \t0xFFFFF214) // (DBGU) Channel Status Register\n#define AT91C_DBGU_IDR  ((AT91_REG *) \t0xFFFFF20C) // (DBGU) Interrupt Disable Register\n#define AT91C_DBGU_MR   ((AT91_REG *) \t0xFFFFF204) // (DBGU) Mode Register\n#define AT91C_DBGU_FNTR ((AT91_REG *) \t0xFFFFF248) // (DBGU) Force NTRST Register\n#define AT91C_DBGU_C1R  ((AT91_REG *) \t0xFFFFF240) // (DBGU) Chip ID1 Register\n#define AT91C_DBGU_BRGR ((AT91_REG *) \t0xFFFFF220) // (DBGU) Baud Rate Generator Register\n#define AT91C_DBGU_RHR  ((AT91_REG *) \t0xFFFFF218) // (DBGU) Receiver Holding Register\n#define AT91C_DBGU_IMR  ((AT91_REG *) \t0xFFFFF210) // (DBGU) Interrupt Mask Register\n#define AT91C_DBGU_IER  ((AT91_REG *) \t0xFFFFF208) // (DBGU) Interrupt Enable Register\n#define AT91C_DBGU_CR   ((AT91_REG *) \t0xFFFFF200) // (DBGU) Control Register\n// ========== Register definition for PDC_DBGU peripheral ========== \n#define AT91C_DBGU_TNCR ((AT91_REG *) \t0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register\n#define AT91C_DBGU_RNCR ((AT91_REG *) \t0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register\n#define AT91C_DBGU_PTCR ((AT91_REG *) \t0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register\n#define AT91C_DBGU_PTSR ((AT91_REG *) \t0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register\n#define AT91C_DBGU_RCR  ((AT91_REG *) \t0xFFFFF304) // (PDC_DBGU) Receive Counter Register\n#define AT91C_DBGU_TCR  ((AT91_REG *) \t0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register\n#define AT91C_DBGU_RPR  ((AT91_REG *) \t0xFFFFF300) // (PDC_DBGU) Receive Pointer Register\n#define AT91C_DBGU_TPR  ((AT91_REG *) \t0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register\n#define AT91C_DBGU_RNPR ((AT91_REG *) \t0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register\n#define AT91C_DBGU_TNPR ((AT91_REG *) \t0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register\n// ========== Register definition for AIC peripheral ========== \n#define AT91C_AIC_ICCR  ((AT91_REG *) \t0xFFFFF128) // (AIC) Interrupt Clear Command Register\n#define AT91C_AIC_IECR  ((AT91_REG *) \t0xFFFFF120) // (AIC) Interrupt Enable Command Register\n#define AT91C_AIC_SMR   ((AT91_REG *) \t0xFFFFF000) // (AIC) Source Mode Register\n#define AT91C_AIC_ISCR  ((AT91_REG *) \t0xFFFFF12C) // (AIC) Interrupt Set Command Register\n#define AT91C_AIC_EOICR ((AT91_REG *) \t0xFFFFF130) // (AIC) End of Interrupt Command Register\n#define AT91C_AIC_DCR   ((AT91_REG *) \t0xFFFFF138) // (AIC) Debug Control Register (Protect)\n#define AT91C_AIC_FFER  ((AT91_REG *) \t0xFFFFF140) // (AIC) Fast Forcing Enable Register\n#define AT91C_AIC_SVR   ((AT91_REG *) \t0xFFFFF080) // (AIC) Source Vector Register\n#define AT91C_AIC_SPU   ((AT91_REG *) \t0xFFFFF134) // (AIC) Spurious Vector Register\n#define AT91C_AIC_FFDR  ((AT91_REG *) \t0xFFFFF144) // (AIC) Fast Forcing Disable Register\n#define AT91C_AIC_FVR   ((AT91_REG *) \t0xFFFFF104) // (AIC) FIQ Vector Register\n#define AT91C_AIC_FFSR  ((AT91_REG *) \t0xFFFFF148) // (AIC) Fast Forcing Status Register\n#define AT91C_AIC_IMR   ((AT91_REG *) \t0xFFFFF110) // (AIC) Interrupt Mask Register\n#define AT91C_AIC_ISR   ((AT91_REG *) \t0xFFFFF108) // (AIC) Interrupt Status Register\n#define AT91C_AIC_IVR   ((AT91_REG *) \t0xFFFFF100) // (AIC) IRQ Vector Register\n#define AT91C_AIC_IDCR  ((AT91_REG *) \t0xFFFFF124) // (AIC) Interrupt Disable Command Register\n#define AT91C_AIC_CISR  ((AT91_REG *) \t0xFFFFF114) // (AIC) Core Interrupt Status Register\n#define AT91C_AIC_IPR   ((AT91_REG *) \t0xFFFFF10C) // (AIC) Interrupt Pending Register\n// ========== Register definition for PDC_SPI peripheral ========== \n#define AT91C_SPI_PTCR  ((AT91_REG *) \t0xFFFE0120) // (PDC_SPI) PDC Transfer Control Register\n#define AT91C_SPI_TNPR  ((AT91_REG *) \t0xFFFE0118) // (PDC_SPI) Transmit Next Pointer Register\n#define AT91C_SPI_RNPR  ((AT91_REG *) \t0xFFFE0110) // (PDC_SPI) Receive Next Pointer Register\n#define AT91C_SPI_TPR   ((AT91_REG *) \t0xFFFE0108) // (PDC_SPI) Transmit Pointer Register\n#define AT91C_SPI_RPR   ((AT91_REG *) \t0xFFFE0100) // (PDC_SPI) Receive Pointer Register\n#define AT91C_SPI_PTSR  ((AT91_REG *) \t0xFFFE0124) // (PDC_SPI) PDC Transfer Status Register\n#define AT91C_SPI_TNCR  ((AT91_REG *) \t0xFFFE011C) // (PDC_SPI) Transmit Next Counter Register\n#define AT91C_SPI_RNCR  ((AT91_REG *) \t0xFFFE0114) // (PDC_SPI) Receive Next Counter Register\n#define AT91C_SPI_TCR   ((AT91_REG *) \t0xFFFE010C) // (PDC_SPI) Transmit Counter Register\n#define AT91C_SPI_RCR   ((AT91_REG *) \t0xFFFE0104) // (PDC_SPI) Receive Counter Register\n// ========== Register definition for SPI peripheral ========== \n#define AT91C_SPI_CSR   ((AT91_REG *) \t0xFFFE0030) // (SPI) Chip Select Register\n#define AT91C_SPI_IDR   ((AT91_REG *) \t0xFFFE0018) // (SPI) Interrupt Disable Register\n#define AT91C_SPI_SR    ((AT91_REG *) \t0xFFFE0010) // (SPI) Status Register\n#define AT91C_SPI_RDR   ((AT91_REG *) \t0xFFFE0008) // (SPI) Receive Data Register\n#define AT91C_SPI_CR    ((AT91_REG *) \t0xFFFE0000) // (SPI) Control Register\n#define AT91C_SPI_IMR   ((AT91_REG *) \t0xFFFE001C) // (SPI) Interrupt Mask Register\n#define AT91C_SPI_IER   ((AT91_REG *) \t0xFFFE0014) // (SPI) Interrupt Enable Register\n#define AT91C_SPI_TDR   ((AT91_REG *) \t0xFFFE000C) // (SPI) Transmit Data Register\n#define AT91C_SPI_MR    ((AT91_REG *) \t0xFFFE0004) // (SPI) Mode Register\n// ========== Register definition for PDC_SSC2 peripheral ========== \n#define AT91C_SSC2_PTCR ((AT91_REG *) \t0xFFFD8120) // (PDC_SSC2) PDC Transfer Control Register\n#define AT91C_SSC2_TNPR ((AT91_REG *) \t0xFFFD8118) // (PDC_SSC2) Transmit Next Pointer Register\n#define AT91C_SSC2_RNPR ((AT91_REG *) \t0xFFFD8110) // (PDC_SSC2) Receive Next Pointer Register\n#define AT91C_SSC2_TPR  ((AT91_REG *) \t0xFFFD8108) // (PDC_SSC2) Transmit Pointer Register\n#define AT91C_SSC2_RPR  ((AT91_REG *) \t0xFFFD8100) // (PDC_SSC2) Receive Pointer Register\n#define AT91C_SSC2_PTSR ((AT91_REG *) \t0xFFFD8124) // (PDC_SSC2) PDC Transfer Status Register\n#define AT91C_SSC2_TNCR ((AT91_REG *) \t0xFFFD811C) // (PDC_SSC2) Transmit Next Counter Register\n#define AT91C_SSC2_RNCR ((AT91_REG *) \t0xFFFD8114) // (PDC_SSC2) Receive Next Counter Register\n#define AT91C_SSC2_TCR  ((AT91_REG *) \t0xFFFD810C) // (PDC_SSC2) Transmit Counter Register\n#define AT91C_SSC2_RCR  ((AT91_REG *) \t0xFFFD8104) // (PDC_SSC2) Receive Counter Register\n// ========== Register definition for SSC2 peripheral ========== \n#define AT91C_SSC2_IMR  ((AT91_REG *) \t0xFFFD804C) // (SSC2) Interrupt Mask Register\n#define AT91C_SSC2_IER  ((AT91_REG *) \t0xFFFD8044) // (SSC2) Interrupt Enable Register\n#define AT91C_SSC2_RC1R ((AT91_REG *) \t0xFFFD803C) // (SSC2) Receive Compare 1 Register\n#define AT91C_SSC2_TSHR ((AT91_REG *) \t0xFFFD8034) // (SSC2) Transmit Sync Holding Register\n#define AT91C_SSC2_CMR  ((AT91_REG *) \t0xFFFD8004) // (SSC2) Clock Mode Register\n#define AT91C_SSC2_IDR  ((AT91_REG *) \t0xFFFD8048) // (SSC2) Interrupt Disable Register\n#define AT91C_SSC2_TCMR ((AT91_REG *) \t0xFFFD8018) // (SSC2) Transmit Clock Mode Register\n#define AT91C_SSC2_RCMR ((AT91_REG *) \t0xFFFD8010) // (SSC2) Receive Clock ModeRegister\n#define AT91C_SSC2_CR   ((AT91_REG *) \t0xFFFD8000) // (SSC2) Control Register\n#define AT91C_SSC2_RFMR ((AT91_REG *) \t0xFFFD8014) // (SSC2) Receive Frame Mode Register\n#define AT91C_SSC2_TFMR ((AT91_REG *) \t0xFFFD801C) // (SSC2) Transmit Frame Mode Register\n#define AT91C_SSC2_THR  ((AT91_REG *) \t0xFFFD8024) // (SSC2) Transmit Holding Register\n#define AT91C_SSC2_SR   ((AT91_REG *) \t0xFFFD8040) // (SSC2) Status Register\n#define AT91C_SSC2_RC0R ((AT91_REG *) \t0xFFFD8038) // (SSC2) Receive Compare 0 Register\n#define AT91C_SSC2_RSHR ((AT91_REG *) \t0xFFFD8030) // (SSC2) Receive Sync Holding Register\n#define AT91C_SSC2_RHR  ((AT91_REG *) \t0xFFFD8020) // (SSC2) Receive Holding Register\n// ========== Register definition for PDC_SSC1 peripheral ========== \n#define AT91C_SSC1_PTCR ((AT91_REG *) \t0xFFFD4120) // (PDC_SSC1) PDC Transfer Control Register\n#define AT91C_SSC1_TNPR ((AT91_REG *) \t0xFFFD4118) // (PDC_SSC1) Transmit Next Pointer Register\n#define AT91C_SSC1_RNPR ((AT91_REG *) \t0xFFFD4110) // (PDC_SSC1) Receive Next Pointer Register\n#define AT91C_SSC1_TPR  ((AT91_REG *) \t0xFFFD4108) // (PDC_SSC1) Transmit Pointer Register\n#define AT91C_SSC1_RPR  ((AT91_REG *) \t0xFFFD4100) // (PDC_SSC1) Receive Pointer Register\n#define AT91C_SSC1_PTSR ((AT91_REG *) \t0xFFFD4124) // (PDC_SSC1) PDC Transfer Status Register\n#define AT91C_SSC1_TNCR ((AT91_REG *) \t0xFFFD411C) // (PDC_SSC1) Transmit Next Counter Register\n#define AT91C_SSC1_RNCR ((AT91_REG *) \t0xFFFD4114) // (PDC_SSC1) Receive Next Counter Register\n#define AT91C_SSC1_TCR  ((AT91_REG *) \t0xFFFD410C) // (PDC_SSC1) Transmit Counter Register\n#define AT91C_SSC1_RCR  ((AT91_REG *) \t0xFFFD4104) // (PDC_SSC1) Receive Counter Register\n// ========== Register definition for SSC1 peripheral ========== \n#define AT91C_SSC1_RFMR ((AT91_REG *) \t0xFFFD4014) // (SSC1) Receive Frame Mode Register\n#define AT91C_SSC1_CMR  ((AT91_REG *) \t0xFFFD4004) // (SSC1) Clock Mode Register\n#define AT91C_SSC1_IDR  ((AT91_REG *) \t0xFFFD4048) // (SSC1) Interrupt Disable Register\n#define AT91C_SSC1_SR   ((AT91_REG *) \t0xFFFD4040) // (SSC1) Status Register\n#define AT91C_SSC1_RC0R ((AT91_REG *) \t0xFFFD4038) // (SSC1) Receive Compare 0 Register\n#define AT91C_SSC1_RSHR ((AT91_REG *) \t0xFFFD4030) // (SSC1) Receive Sync Holding Register\n#define AT91C_SSC1_RHR  ((AT91_REG *) \t0xFFFD4020) // (SSC1) Receive Holding Register\n#define AT91C_SSC1_TCMR ((AT91_REG *) \t0xFFFD4018) // (SSC1) Transmit Clock Mode Register\n#define AT91C_SSC1_RCMR ((AT91_REG *) \t0xFFFD4010) // (SSC1) Receive Clock ModeRegister\n#define AT91C_SSC1_CR   ((AT91_REG *) \t0xFFFD4000) // (SSC1) Control Register\n#define AT91C_SSC1_IMR  ((AT91_REG *) \t0xFFFD404C) // (SSC1) Interrupt Mask Register\n#define AT91C_SSC1_IER  ((AT91_REG *) \t0xFFFD4044) // (SSC1) Interrupt Enable Register\n#define AT91C_SSC1_RC1R ((AT91_REG *) \t0xFFFD403C) // (SSC1) Receive Compare 1 Register\n#define AT91C_SSC1_TSHR ((AT91_REG *) \t0xFFFD4034) // (SSC1) Transmit Sync Holding Register\n#define AT91C_SSC1_THR  ((AT91_REG *) \t0xFFFD4024) // (SSC1) Transmit Holding Register\n#define AT91C_SSC1_TFMR ((AT91_REG *) \t0xFFFD401C) // (SSC1) Transmit Frame Mode Register\n// ========== Register definition for PDC_SSC0 peripheral ========== \n#define AT91C_SSC0_PTCR ((AT91_REG *) \t0xFFFD0120) // (PDC_SSC0) PDC Transfer Control Register\n#define AT91C_SSC0_TNPR ((AT91_REG *) \t0xFFFD0118) // (PDC_SSC0) Transmit Next Pointer Register\n#define AT91C_SSC0_RNPR ((AT91_REG *) \t0xFFFD0110) // (PDC_SSC0) Receive Next Pointer Register\n#define AT91C_SSC0_TPR  ((AT91_REG *) \t0xFFFD0108) // (PDC_SSC0) Transmit Pointer Register\n#define AT91C_SSC0_RPR  ((AT91_REG *) \t0xFFFD0100) // (PDC_SSC0) Receive Pointer Register\n#define AT91C_SSC0_PTSR ((AT91_REG *) \t0xFFFD0124) // (PDC_SSC0) PDC Transfer Status Register\n#define AT91C_SSC0_TNCR ((AT91_REG *) \t0xFFFD011C) // (PDC_SSC0) Transmit Next Counter Register\n#define AT91C_SSC0_RNCR ((AT91_REG *) \t0xFFFD0114) // (PDC_SSC0) Receive Next Counter Register\n#define AT91C_SSC0_TCR  ((AT91_REG *) \t0xFFFD010C) // (PDC_SSC0) Transmit Counter Register\n#define AT91C_SSC0_RCR  ((AT91_REG *) \t0xFFFD0104) // (PDC_SSC0) Receive Counter Register\n// ========== Register definition for SSC0 peripheral ========== \n#define AT91C_SSC0_IMR  ((AT91_REG *) \t0xFFFD004C) // (SSC0) Interrupt Mask Register\n#define AT91C_SSC0_IER  ((AT91_REG *) \t0xFFFD0044) // (SSC0) Interrupt Enable Register\n#define AT91C_SSC0_RC1R ((AT91_REG *) \t0xFFFD003C) // (SSC0) Receive Compare 1 Register\n#define AT91C_SSC0_TSHR ((AT91_REG *) \t0xFFFD0034) // (SSC0) Transmit Sync Holding Register\n#define AT91C_SSC0_THR  ((AT91_REG *) \t0xFFFD0024) // (SSC0) Transmit Holding Register\n#define AT91C_SSC0_TFMR ((AT91_REG *) \t0xFFFD001C) // (SSC0) Transmit Frame Mode Register\n#define AT91C_SSC0_RFMR ((AT91_REG *) \t0xFFFD0014) // (SSC0) Receive Frame Mode Register\n#define AT91C_SSC0_CMR  ((AT91_REG *) \t0xFFFD0004) // (SSC0) Clock Mode Register\n#define AT91C_SSC0_IDR  ((AT91_REG *) \t0xFFFD0048) // (SSC0) Interrupt Disable Register\n#define AT91C_SSC0_SR   ((AT91_REG *) \t0xFFFD0040) // (SSC0) Status Register\n#define AT91C_SSC0_RC0R ((AT91_REG *) \t0xFFFD0038) // (SSC0) Receive Compare 0 Register\n#define AT91C_SSC0_RSHR ((AT91_REG *) \t0xFFFD0030) // (SSC0) Receive Sync Holding Register\n#define AT91C_SSC0_RHR  ((AT91_REG *) \t0xFFFD0020) // (SSC0) Receive Holding Register\n#define AT91C_SSC0_TCMR ((AT91_REG *) \t0xFFFD0018) // (SSC0) Transmit Clock Mode Register\n#define AT91C_SSC0_RCMR ((AT91_REG *) \t0xFFFD0010) // (SSC0) Receive Clock ModeRegister\n#define AT91C_SSC0_CR   ((AT91_REG *) \t0xFFFD0000) // (SSC0) Control Register\n// ========== Register definition for PDC_US3 peripheral ========== \n#define AT91C_US3_PTSR  ((AT91_REG *) \t0xFFFCC124) // (PDC_US3) PDC Transfer Status Register\n#define AT91C_US3_TNCR  ((AT91_REG *) \t0xFFFCC11C) // (PDC_US3) Transmit Next Counter Register\n#define AT91C_US3_RNCR  ((AT91_REG *) \t0xFFFCC114) // (PDC_US3) Receive Next Counter Register\n#define AT91C_US3_TCR   ((AT91_REG *) \t0xFFFCC10C) // (PDC_US3) Transmit Counter Register\n#define AT91C_US3_RCR   ((AT91_REG *) \t0xFFFCC104) // (PDC_US3) Receive Counter Register\n#define AT91C_US3_PTCR  ((AT91_REG *) \t0xFFFCC120) // (PDC_US3) PDC Transfer Control Register\n#define AT91C_US3_TNPR  ((AT91_REG *) \t0xFFFCC118) // (PDC_US3) Transmit Next Pointer Register\n#define AT91C_US3_RNPR  ((AT91_REG *) \t0xFFFCC110) // (PDC_US3) Receive Next Pointer Register\n#define AT91C_US3_TPR   ((AT91_REG *) \t0xFFFCC108) // (PDC_US3) Transmit Pointer Register\n#define AT91C_US3_RPR   ((AT91_REG *) \t0xFFFCC100) // (PDC_US3) Receive Pointer Register\n// ========== Register definition for US3 peripheral ========== \n#define AT91C_US3_IF    ((AT91_REG *) \t0xFFFCC04C) // (US3) IRDA_FILTER Register\n#define AT91C_US3_NER   ((AT91_REG *) \t0xFFFCC044) // (US3) Nb Errors Register\n#define AT91C_US3_RTOR  ((AT91_REG *) \t0xFFFCC024) // (US3) Receiver Time-out Register\n#define AT91C_US3_THR   ((AT91_REG *) \t0xFFFCC01C) // (US3) Transmitter Holding Register\n#define AT91C_US3_CSR   ((AT91_REG *) \t0xFFFCC014) // (US3) Channel Status Register\n#define AT91C_US3_IDR   ((AT91_REG *) \t0xFFFCC00C) // (US3) Interrupt Disable Register\n#define AT91C_US3_MR    ((AT91_REG *) \t0xFFFCC004) // (US3) Mode Register\n#define AT91C_US3_XXR   ((AT91_REG *) \t0xFFFCC048) // (US3) XON_XOFF Register\n#define AT91C_US3_FIDI  ((AT91_REG *) \t0xFFFCC040) // (US3) FI_DI_Ratio Register\n#define AT91C_US3_TTGR  ((AT91_REG *) \t0xFFFCC028) // (US3) Transmitter Time-guard Register\n#define AT91C_US3_BRGR  ((AT91_REG *) \t0xFFFCC020) // (US3) Baud Rate Generator Register\n#define AT91C_US3_RHR   ((AT91_REG *) \t0xFFFCC018) // (US3) Receiver Holding Register\n#define AT91C_US3_IMR   ((AT91_REG *) \t0xFFFCC010) // (US3) Interrupt Mask Register\n#define AT91C_US3_IER   ((AT91_REG *) \t0xFFFCC008) // (US3) Interrupt Enable Register\n#define AT91C_US3_CR    ((AT91_REG *) \t0xFFFCC000) // (US3) Control Register\n// ========== Register definition for PDC_US2 peripheral ========== \n#define AT91C_US2_PTSR  ((AT91_REG *) \t0xFFFC8124) // (PDC_US2) PDC Transfer Status Register\n#define AT91C_US2_TNCR  ((AT91_REG *) \t0xFFFC811C) // (PDC_US2) Transmit Next Counter Register\n#define AT91C_US2_RNCR  ((AT91_REG *) \t0xFFFC8114) // (PDC_US2) Receive Next Counter Register\n#define AT91C_US2_TCR   ((AT91_REG *) \t0xFFFC810C) // (PDC_US2) Transmit Counter Register\n#define AT91C_US2_PTCR  ((AT91_REG *) \t0xFFFC8120) // (PDC_US2) PDC Transfer Control Register\n#define AT91C_US2_RCR   ((AT91_REG *) \t0xFFFC8104) // (PDC_US2) Receive Counter Register\n#define AT91C_US2_TNPR  ((AT91_REG *) \t0xFFFC8118) // (PDC_US2) Transmit Next Pointer Register\n#define AT91C_US2_RPR   ((AT91_REG *) \t0xFFFC8100) // (PDC_US2) Receive Pointer Register\n#define AT91C_US2_TPR   ((AT91_REG *) \t0xFFFC8108) // (PDC_US2) Transmit Pointer Register\n#define AT91C_US2_RNPR  ((AT91_REG *) \t0xFFFC8110) // (PDC_US2) Receive Next Pointer Register\n// ========== Register definition for US2 peripheral ========== \n#define AT91C_US2_XXR   ((AT91_REG *) \t0xFFFC8048) // (US2) XON_XOFF Register\n#define AT91C_US2_FIDI  ((AT91_REG *) \t0xFFFC8040) // (US2) FI_DI_Ratio Register\n#define AT91C_US2_TTGR  ((AT91_REG *) \t0xFFFC8028) // (US2) Transmitter Time-guard Register\n#define AT91C_US2_BRGR  ((AT91_REG *) \t0xFFFC8020) // (US2) Baud Rate Generator Register\n#define AT91C_US2_RHR   ((AT91_REG *) \t0xFFFC8018) // (US2) Receiver Holding Register\n#define AT91C_US2_IMR   ((AT91_REG *) \t0xFFFC8010) // (US2) Interrupt Mask Register\n#define AT91C_US2_IER   ((AT91_REG *) \t0xFFFC8008) // (US2) Interrupt Enable Register\n#define AT91C_US2_CR    ((AT91_REG *) \t0xFFFC8000) // (US2) Control Register\n#define AT91C_US2_IF    ((AT91_REG *) \t0xFFFC804C) // (US2) IRDA_FILTER Register\n#define AT91C_US2_NER   ((AT91_REG *) \t0xFFFC8044) // (US2) Nb Errors Register\n#define AT91C_US2_RTOR  ((AT91_REG *) \t0xFFFC8024) // (US2) Receiver Time-out Register\n#define AT91C_US2_THR   ((AT91_REG *) \t0xFFFC801C) // (US2) Transmitter Holding Register\n#define AT91C_US2_CSR   ((AT91_REG *) \t0xFFFC8014) // (US2) Channel Status Register\n#define AT91C_US2_IDR   ((AT91_REG *) \t0xFFFC800C) // (US2) Interrupt Disable Register\n#define AT91C_US2_MR    ((AT91_REG *) \t0xFFFC8004) // (US2) Mode Register\n// ========== Register definition for PDC_US1 peripheral ========== \n#define AT91C_US1_PTSR  ((AT91_REG *) \t0xFFFC4124) // (PDC_US1) PDC Transfer Status Register\n#define AT91C_US1_TNCR  ((AT91_REG *) \t0xFFFC411C) // (PDC_US1) Transmit Next Counter Register\n#define AT91C_US1_RNCR  ((AT91_REG *) \t0xFFFC4114) // (PDC_US1) Receive Next Counter Register\n#define AT91C_US1_TCR   ((AT91_REG *) \t0xFFFC410C) // (PDC_US1) Transmit Counter Register\n#define AT91C_US1_RCR   ((AT91_REG *) \t0xFFFC4104) // (PDC_US1) Receive Counter Register\n#define AT91C_US1_PTCR  ((AT91_REG *) \t0xFFFC4120) // (PDC_US1) PDC Transfer Control Register\n#define AT91C_US1_TNPR  ((AT91_REG *) \t0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register\n#define AT91C_US1_RNPR  ((AT91_REG *) \t0xFFFC4110) // (PDC_US1) Receive Next Pointer Register\n#define AT91C_US1_TPR   ((AT91_REG *) \t0xFFFC4108) // (PDC_US1) Transmit Pointer Register\n#define AT91C_US1_RPR   ((AT91_REG *) \t0xFFFC4100) // (PDC_US1) Receive Pointer Register\n// ========== Register definition for US1 peripheral ========== \n#define AT91C_US1_XXR   ((AT91_REG *) \t0xFFFC4048) // (US1) XON_XOFF Register\n#define AT91C_US1_RHR   ((AT91_REG *) \t0xFFFC4018) // (US1) Receiver Holding Register\n#define AT91C_US1_IMR   ((AT91_REG *) \t0xFFFC4010) // (US1) Interrupt Mask Register\n#define AT91C_US1_IER   ((AT91_REG *) \t0xFFFC4008) // (US1) Interrupt Enable Register\n#define AT91C_US1_CR    ((AT91_REG *) \t0xFFFC4000) // (US1) Control Register\n#define AT91C_US1_RTOR  ((AT91_REG *) \t0xFFFC4024) // (US1) Receiver Time-out Register\n#define AT91C_US1_THR   ((AT91_REG *) \t0xFFFC401C) // (US1) Transmitter Holding Register\n#define AT91C_US1_CSR   ((AT91_REG *) \t0xFFFC4014) // (US1) Channel Status Register\n#define AT91C_US1_IDR   ((AT91_REG *) \t0xFFFC400C) // (US1) Interrupt Disable Register\n#define AT91C_US1_FIDI  ((AT91_REG *) \t0xFFFC4040) // (US1) FI_DI_Ratio Register\n#define AT91C_US1_BRGR  ((AT91_REG *) \t0xFFFC4020) // (US1) Baud Rate Generator Register\n#define AT91C_US1_TTGR  ((AT91_REG *) \t0xFFFC4028) // (US1) Transmitter Time-guard Register\n#define AT91C_US1_IF    ((AT91_REG *) \t0xFFFC404C) // (US1) IRDA_FILTER Register\n#define AT91C_US1_NER   ((AT91_REG *) \t0xFFFC4044) // (US1) Nb Errors Register\n#define AT91C_US1_MR    ((AT91_REG *) \t0xFFFC4004) // (US1) Mode Register\n// ========== Register definition for PDC_US0 peripheral ========== \n#define AT91C_US0_PTCR  ((AT91_REG *) \t0xFFFC0120) // (PDC_US0) PDC Transfer Control Register\n#define AT91C_US0_TNPR  ((AT91_REG *) \t0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register\n#define AT91C_US0_RNPR  ((AT91_REG *) \t0xFFFC0110) // (PDC_US0) Receive Next Pointer Register\n#define AT91C_US0_TPR   ((AT91_REG *) \t0xFFFC0108) // (PDC_US0) Transmit Pointer Register\n#define AT91C_US0_RPR   ((AT91_REG *) \t0xFFFC0100) // (PDC_US0) Receive Pointer Register\n#define AT91C_US0_PTSR  ((AT91_REG *) \t0xFFFC0124) // (PDC_US0) PDC Transfer Status Register\n#define AT91C_US0_TNCR  ((AT91_REG *) \t0xFFFC011C) // (PDC_US0) Transmit Next Counter Register\n#define AT91C_US0_RNCR  ((AT91_REG *) \t0xFFFC0114) // (PDC_US0) Receive Next Counter Register\n#define AT91C_US0_TCR   ((AT91_REG *) \t0xFFFC010C) // (PDC_US0) Transmit Counter Register\n#define AT91C_US0_RCR   ((AT91_REG *) \t0xFFFC0104) // (PDC_US0) Receive Counter Register\n// ========== Register definition for US0 peripheral ========== \n#define AT91C_US0_TTGR  ((AT91_REG *) \t0xFFFC0028) // (US0) Transmitter Time-guard Register\n#define AT91C_US0_BRGR  ((AT91_REG *) \t0xFFFC0020) // (US0) Baud Rate Generator Register\n#define AT91C_US0_RHR   ((AT91_REG *) \t0xFFFC0018) // (US0) Receiver Holding Register\n#define AT91C_US0_IMR   ((AT91_REG *) \t0xFFFC0010) // (US0) Interrupt Mask Register\n#define AT91C_US0_NER   ((AT91_REG *) \t0xFFFC0044) // (US0) Nb Errors Register\n#define AT91C_US0_RTOR  ((AT91_REG *) \t0xFFFC0024) // (US0) Receiver Time-out Register\n#define AT91C_US0_XXR   ((AT91_REG *) \t0xFFFC0048) // (US0) XON_XOFF Register\n#define AT91C_US0_FIDI  ((AT91_REG *) \t0xFFFC0040) // (US0) FI_DI_Ratio Register\n#define AT91C_US0_CR    ((AT91_REG *) \t0xFFFC0000) // (US0) Control Register\n#define AT91C_US0_IER   ((AT91_REG *) \t0xFFFC0008) // (US0) Interrupt Enable Register\n#define AT91C_US0_IF    ((AT91_REG *) \t0xFFFC004C) // (US0) IRDA_FILTER Register\n#define AT91C_US0_MR    ((AT91_REG *) \t0xFFFC0004) // (US0) Mode Register\n#define AT91C_US0_IDR   ((AT91_REG *) \t0xFFFC000C) // (US0) Interrupt Disable Register\n#define AT91C_US0_CSR   ((AT91_REG *) \t0xFFFC0014) // (US0) Channel Status Register\n#define AT91C_US0_THR   ((AT91_REG *) \t0xFFFC001C) // (US0) Transmitter Holding Register\n// ========== Register definition for TWI peripheral ========== \n#define AT91C_TWI_RHR   ((AT91_REG *) \t0xFFFB8030) // (TWI) Receive Holding Register\n#define AT91C_TWI_IDR   ((AT91_REG *) \t0xFFFB8028) // (TWI) Interrupt Disable Register\n#define AT91C_TWI_SR    ((AT91_REG *) \t0xFFFB8020) // (TWI) Status Register\n#define AT91C_TWI_CWGR  ((AT91_REG *) \t0xFFFB8010) // (TWI) Clock Waveform Generator Register\n#define AT91C_TWI_SMR   ((AT91_REG *) \t0xFFFB8008) // (TWI) Slave Mode Register\n#define AT91C_TWI_CR    ((AT91_REG *) \t0xFFFB8000) // (TWI) Control Register\n#define AT91C_TWI_THR   ((AT91_REG *) \t0xFFFB8034) // (TWI) Transmit Holding Register\n#define AT91C_TWI_IMR   ((AT91_REG *) \t0xFFFB802C) // (TWI) Interrupt Mask Register\n#define AT91C_TWI_IER   ((AT91_REG *) \t0xFFFB8024) // (TWI) Interrupt Enable Register\n#define AT91C_TWI_IADR  ((AT91_REG *) \t0xFFFB800C) // (TWI) Internal Address Register\n#define AT91C_TWI_MMR   ((AT91_REG *) \t0xFFFB8004) // (TWI) Master Mode Register\n// ========== Register definition for PDC_MCI peripheral ========== \n#define AT91C_MCI_PTCR  ((AT91_REG *) \t0xFFFB4120) // (PDC_MCI) PDC Transfer Control Register\n#define AT91C_MCI_TNPR  ((AT91_REG *) \t0xFFFB4118) // (PDC_MCI) Transmit Next Pointer Register\n#define AT91C_MCI_RNPR  ((AT91_REG *) \t0xFFFB4110) // (PDC_MCI) Receive Next Pointer Register\n#define AT91C_MCI_TPR   ((AT91_REG *) \t0xFFFB4108) // (PDC_MCI) Transmit Pointer Register\n#define AT91C_MCI_RPR   ((AT91_REG *) \t0xFFFB4100) // (PDC_MCI) Receive Pointer Register\n#define AT91C_MCI_PTSR  ((AT91_REG *) \t0xFFFB4124) // (PDC_MCI) PDC Transfer Status Register\n#define AT91C_MCI_TNCR  ((AT91_REG *) \t0xFFFB411C) // (PDC_MCI) Transmit Next Counter Register\n#define AT91C_MCI_RNCR  ((AT91_REG *) \t0xFFFB4114) // (PDC_MCI) Receive Next Counter Register\n#define AT91C_MCI_TCR   ((AT91_REG *) \t0xFFFB410C) // (PDC_MCI) Transmit Counter Register\n#define AT91C_MCI_RCR   ((AT91_REG *) \t0xFFFB4104) // (PDC_MCI) Receive Counter Register\n// ========== Register definition for MCI peripheral ========== \n#define AT91C_MCI_IDR   ((AT91_REG *) \t0xFFFB4048) // (MCI) MCI Interrupt Disable Register\n#define AT91C_MCI_SR    ((AT91_REG *) \t0xFFFB4040) // (MCI) MCI Status Register\n#define AT91C_MCI_RDR   ((AT91_REG *) \t0xFFFB4030) // (MCI) MCI Receive Data Register\n#define AT91C_MCI_RSPR  ((AT91_REG *) \t0xFFFB4020) // (MCI) MCI Response Register\n#define AT91C_MCI_ARGR  ((AT91_REG *) \t0xFFFB4010) // (MCI) MCI Argument Register\n#define AT91C_MCI_DTOR  ((AT91_REG *) \t0xFFFB4008) // (MCI) MCI Data Timeout Register\n#define AT91C_MCI_CR    ((AT91_REG *) \t0xFFFB4000) // (MCI) MCI Control Register\n#define AT91C_MCI_IMR   ((AT91_REG *) \t0xFFFB404C) // (MCI) MCI Interrupt Mask Register\n#define AT91C_MCI_IER   ((AT91_REG *) \t0xFFFB4044) // (MCI) MCI Interrupt Enable Register\n#define AT91C_MCI_TDR   ((AT91_REG *) \t0xFFFB4034) // (MCI) MCI Transmit Data Register\n#define AT91C_MCI_CMDR  ((AT91_REG *) \t0xFFFB4014) // (MCI) MCI Command Register\n#define AT91C_MCI_SDCR  ((AT91_REG *) \t0xFFFB400C) // (MCI) MCI SD Card Register\n#define AT91C_MCI_MR    ((AT91_REG *) \t0xFFFB4004) // (MCI) MCI Mode Register\n// ========== Register definition for UDP peripheral ========== \n#define AT91C_UDP_ISR   ((AT91_REG *) \t0xFFFB001C) // (UDP) Interrupt Status Register\n#define AT91C_UDP_IDR   ((AT91_REG *) \t0xFFFB0014) // (UDP) Interrupt Disable Register\n#define AT91C_UDP_GLBSTATE ((AT91_REG *) \t0xFFFB0004) // (UDP) Global State Register\n#define AT91C_UDP_FDR   ((AT91_REG *) \t0xFFFB0050) // (UDP) Endpoint FIFO Data Register\n#define AT91C_UDP_CSR   ((AT91_REG *) \t0xFFFB0030) // (UDP) Endpoint Control and Status Register\n#define AT91C_UDP_RSTEP ((AT91_REG *) \t0xFFFB0028) // (UDP) Reset Endpoint Register\n#define AT91C_UDP_ICR   ((AT91_REG *) \t0xFFFB0020) // (UDP) Interrupt Clear Register\n#define AT91C_UDP_IMR   ((AT91_REG *) \t0xFFFB0018) // (UDP) Interrupt Mask Register\n#define AT91C_UDP_IER   ((AT91_REG *) \t0xFFFB0010) // (UDP) Interrupt Enable Register\n#define AT91C_UDP_FADDR ((AT91_REG *) \t0xFFFB0008) // (UDP) Function Address Register\n#define AT91C_UDP_NUM   ((AT91_REG *) \t0xFFFB0000) // (UDP) Frame Number Register\n// ========== Register definition for TC5 peripheral ========== \n#define AT91C_TC5_CMR   ((AT91_REG *) \t0xFFFA4084) // (TC5) Channel Mode Register\n#define AT91C_TC5_IDR   ((AT91_REG *) \t0xFFFA40A8) // (TC5) Interrupt Disable Register\n#define AT91C_TC5_SR    ((AT91_REG *) \t0xFFFA40A0) // (TC5) Status Register\n#define AT91C_TC5_RB    ((AT91_REG *) \t0xFFFA4098) // (TC5) Register B\n#define AT91C_TC5_CV    ((AT91_REG *) \t0xFFFA4090) // (TC5) Counter Value\n#define AT91C_TC5_CCR   ((AT91_REG *) \t0xFFFA4080) // (TC5) Channel Control Register\n#define AT91C_TC5_IMR   ((AT91_REG *) \t0xFFFA40AC) // (TC5) Interrupt Mask Register\n#define AT91C_TC5_IER   ((AT91_REG *) \t0xFFFA40A4) // (TC5) Interrupt Enable Register\n#define AT91C_TC5_RC    ((AT91_REG *) \t0xFFFA409C) // (TC5) Register C\n#define AT91C_TC5_RA    ((AT91_REG *) \t0xFFFA4094) // (TC5) Register A\n// ========== Register definition for TC4 peripheral ========== \n#define AT91C_TC4_IMR   ((AT91_REG *) \t0xFFFA406C) // (TC4) Interrupt Mask Register\n#define AT91C_TC4_IER   ((AT91_REG *) \t0xFFFA4064) // (TC4) Interrupt Enable Register\n#define AT91C_TC4_RC    ((AT91_REG *) \t0xFFFA405C) // (TC4) Register C\n#define AT91C_TC4_RA    ((AT91_REG *) \t0xFFFA4054) // (TC4) Register A\n#define AT91C_TC4_CMR   ((AT91_REG *) \t0xFFFA4044) // (TC4) Channel Mode Register\n#define AT91C_TC4_IDR   ((AT91_REG *) \t0xFFFA4068) // (TC4) Interrupt Disable Register\n#define AT91C_TC4_SR    ((AT91_REG *) \t0xFFFA4060) // (TC4) Status Register\n#define AT91C_TC4_RB    ((AT91_REG *) \t0xFFFA4058) // (TC4) Register B\n#define AT91C_TC4_CV    ((AT91_REG *) \t0xFFFA4050) // (TC4) Counter Value\n#define AT91C_TC4_CCR   ((AT91_REG *) \t0xFFFA4040) // (TC4) Channel Control Register\n// ========== Register definition for TC3 peripheral ========== \n#define AT91C_TC3_IMR   ((AT91_REG *) \t0xFFFA402C) // (TC3) Interrupt Mask Register\n#define AT91C_TC3_CV    ((AT91_REG *) \t0xFFFA4010) // (TC3) Counter Value\n#define AT91C_TC3_CCR   ((AT91_REG *) \t0xFFFA4000) // (TC3) Channel Control Register\n#define AT91C_TC3_IER   ((AT91_REG *) \t0xFFFA4024) // (TC3) Interrupt Enable Register\n#define AT91C_TC3_CMR   ((AT91_REG *) \t0xFFFA4004) // (TC3) Channel Mode Register\n#define AT91C_TC3_RA    ((AT91_REG *) \t0xFFFA4014) // (TC3) Register A\n#define AT91C_TC3_RC    ((AT91_REG *) \t0xFFFA401C) // (TC3) Register C\n#define AT91C_TC3_IDR   ((AT91_REG *) \t0xFFFA4028) // (TC3) Interrupt Disable Register\n#define AT91C_TC3_RB    ((AT91_REG *) \t0xFFFA4018) // (TC3) Register B\n#define AT91C_TC3_SR    ((AT91_REG *) \t0xFFFA4020) // (TC3) Status Register\n// ========== Register definition for TCB1 peripheral ========== \n#define AT91C_TCB1_BCR  ((AT91_REG *) \t0xFFFA4140) // (TCB1) TC Block Control Register\n#define AT91C_TCB1_BMR  ((AT91_REG *) \t0xFFFA4144) // (TCB1) TC Block Mode Register\n// ========== Register definition for TC2 peripheral ========== \n#define AT91C_TC2_IMR   ((AT91_REG *) \t0xFFFA00AC) // (TC2) Interrupt Mask Register\n#define AT91C_TC2_IER   ((AT91_REG *) \t0xFFFA00A4) // (TC2) Interrupt Enable Register\n#define AT91C_TC2_RC    ((AT91_REG *) \t0xFFFA009C) // (TC2) Register C\n#define AT91C_TC2_RA    ((AT91_REG *) \t0xFFFA0094) // (TC2) Register A\n#define AT91C_TC2_CMR   ((AT91_REG *) \t0xFFFA0084) // (TC2) Channel Mode Register\n#define AT91C_TC2_IDR   ((AT91_REG *) \t0xFFFA00A8) // (TC2) Interrupt Disable Register\n#define AT91C_TC2_SR    ((AT91_REG *) \t0xFFFA00A0) // (TC2) Status Register\n#define AT91C_TC2_RB    ((AT91_REG *) \t0xFFFA0098) // (TC2) Register B\n#define AT91C_TC2_CV    ((AT91_REG *) \t0xFFFA0090) // (TC2) Counter Value\n#define AT91C_TC2_CCR   ((AT91_REG *) \t0xFFFA0080) // (TC2) Channel Control Register\n// ========== Register definition for TC1 peripheral ========== \n#define AT91C_TC1_IMR   ((AT91_REG *) \t0xFFFA006C) // (TC1) Interrupt Mask Register\n#define AT91C_TC1_IER   ((AT91_REG *) \t0xFFFA0064) // (TC1) Interrupt Enable Register\n#define AT91C_TC1_RC    ((AT91_REG *) \t0xFFFA005C) // (TC1) Register C\n#define AT91C_TC1_RA    ((AT91_REG *) \t0xFFFA0054) // (TC1) Register A\n#define AT91C_TC1_CMR   ((AT91_REG *) \t0xFFFA0044) // (TC1) Channel Mode Register\n#define AT91C_TC1_IDR   ((AT91_REG *) \t0xFFFA0068) // (TC1) Interrupt Disable Register\n#define AT91C_TC1_SR    ((AT91_REG *) \t0xFFFA0060) // (TC1) Status Register\n#define AT91C_TC1_RB    ((AT91_REG *) \t0xFFFA0058) // (TC1) Register B\n#define AT91C_TC1_CV    ((AT91_REG *) \t0xFFFA0050) // (TC1) Counter Value\n#define AT91C_TC1_CCR   ((AT91_REG *) \t0xFFFA0040) // (TC1) Channel Control Register\n// ========== Register definition for TC0 peripheral ========== \n#define AT91C_TC0_IMR   ((AT91_REG *) \t0xFFFA002C) // (TC0) Interrupt Mask Register\n#define AT91C_TC0_IER   ((AT91_REG *) \t0xFFFA0024) // (TC0) Interrupt Enable Register\n#define AT91C_TC0_RC    ((AT91_REG *) \t0xFFFA001C) // (TC0) Register C\n#define AT91C_TC0_RA    ((AT91_REG *) \t0xFFFA0014) // (TC0) Register A\n#define AT91C_TC0_CMR   ((AT91_REG *) \t0xFFFA0004) // (TC0) Channel Mode Register\n#define AT91C_TC0_IDR   ((AT91_REG *) \t0xFFFA0028) // (TC0) Interrupt Disable Register\n#define AT91C_TC0_SR    ((AT91_REG *) \t0xFFFA0020) // (TC0) Status Register\n#define AT91C_TC0_RB    ((AT91_REG *) \t0xFFFA0018) // (TC0) Register B\n#define AT91C_TC0_CV    ((AT91_REG *) \t0xFFFA0010) // (TC0) Counter Value\n#define AT91C_TC0_CCR   ((AT91_REG *) \t0xFFFA0000) // (TC0) Channel Control Register\n// ========== Register definition for TCB0 peripheral ========== \n#define AT91C_TCB0_BMR  ((AT91_REG *) \t0xFFFA00C4) // (TCB0) TC Block Mode Register\n#define AT91C_TCB0_BCR  ((AT91_REG *) \t0xFFFA00C0) // (TCB0) TC Block Control Register\n// ========== Register definition for UHP peripheral ========== \n#define AT91C_UHP_HcRhDescriptorA ((AT91_REG *) \t0x00300048) // (UHP) Root Hub characteristics A\n#define AT91C_UHP_HcRhPortStatus ((AT91_REG *) \t0x00300054) // (UHP) Root Hub Port Status Register\n#define AT91C_UHP_HcRhDescriptorB ((AT91_REG *) \t0x0030004C) // (UHP) Root Hub characteristics B\n#define AT91C_UHP_HcControl ((AT91_REG *) \t0x00300004) // (UHP) Operating modes for the Host Controller\n#define AT91C_UHP_HcInterruptStatus ((AT91_REG *) \t0x0030000C) // (UHP) Interrupt Status Register\n#define AT91C_UHP_HcRhStatus ((AT91_REG *) \t0x00300050) // (UHP) Root Hub Status register\n#define AT91C_UHP_HcRevision ((AT91_REG *) \t0x00300000) // (UHP) Revision\n#define AT91C_UHP_HcCommandStatus ((AT91_REG *) \t0x00300008) // (UHP) Command & status Register\n#define AT91C_UHP_HcInterruptEnable ((AT91_REG *) \t0x00300010) // (UHP) Interrupt Enable Register\n#define AT91C_UHP_HcHCCA ((AT91_REG *) \t0x00300018) // (UHP) Pointer to the Host Controller Communication Area\n#define AT91C_UHP_HcControlHeadED ((AT91_REG *) \t0x00300020) // (UHP) First Endpoint Descriptor of the Control list\n#define AT91C_UHP_HcInterruptDisable ((AT91_REG *) \t0x00300014) // (UHP) Interrupt Disable Register\n#define AT91C_UHP_HcPeriodCurrentED ((AT91_REG *) \t0x0030001C) // (UHP) Current Isochronous or Interrupt Endpoint Descriptor\n#define AT91C_UHP_HcControlCurrentED ((AT91_REG *) \t0x00300024) // (UHP) Endpoint Control and Status Register\n#define AT91C_UHP_HcBulkCurrentED ((AT91_REG *) \t0x0030002C) // (UHP) Current endpoint of the Bulk list\n#define AT91C_UHP_HcFmInterval ((AT91_REG *) \t0x00300034) // (UHP) Bit time between 2 consecutive SOFs\n#define AT91C_UHP_HcBulkHeadED ((AT91_REG *) \t0x00300028) // (UHP) First endpoint register of the Bulk list\n#define AT91C_UHP_HcBulkDoneHead ((AT91_REG *) \t0x00300030) // (UHP) Last completed transfer descriptor\n#define AT91C_UHP_HcFmRemaining ((AT91_REG *) \t0x00300038) // (UHP) Bit time remaining in the current Frame\n#define AT91C_UHP_HcPeriodicStart ((AT91_REG *) \t0x00300040) // (UHP) Periodic Start\n#define AT91C_UHP_HcLSThreshold ((AT91_REG *) \t0x00300044) // (UHP) LS Threshold\n#define AT91C_UHP_HcFmNumber ((AT91_REG *) \t0x0030003C) // (UHP) Frame number\n// ========== Register definition for EMAC peripheral ========== \n#define AT91C_EMAC_RSR  ((AT91_REG *) \t0xFFFBC020) // (EMAC) Receive Status Register\n#define AT91C_EMAC_MAN  ((AT91_REG *) \t0xFFFBC034) // (EMAC) PHY Maintenance Register\n#define AT91C_EMAC_HSH  ((AT91_REG *) \t0xFFFBC090) // (EMAC) Hash Address High[63:32]\n#define AT91C_EMAC_MCOL ((AT91_REG *) \t0xFFFBC048) // (EMAC) Multiple Collision Frame Register\n#define AT91C_EMAC_IER  ((AT91_REG *) \t0xFFFBC028) // (EMAC) Interrupt Enable Register\n#define AT91C_EMAC_SA2H ((AT91_REG *) \t0xFFFBC0A4) // (EMAC) Specific Address 2 High, Last 2 bytes\n#define AT91C_EMAC_HSL  ((AT91_REG *) \t0xFFFBC094) // (EMAC) Hash Address Low[31:0]\n#define AT91C_EMAC_LCOL ((AT91_REG *) \t0xFFFBC05C) // (EMAC) Late Collision Register\n#define AT91C_EMAC_OK   ((AT91_REG *) \t0xFFFBC04C) // (EMAC) Frames Received OK Register\n#define AT91C_EMAC_CFG  ((AT91_REG *) \t0xFFFBC004) // (EMAC) Network Configuration Register\n#define AT91C_EMAC_SA3L ((AT91_REG *) \t0xFFFBC0A8) // (EMAC) Specific Address 3 Low, First 4 bytes\n#define AT91C_EMAC_SEQE ((AT91_REG *) \t0xFFFBC050) // (EMAC) Frame Check Sequence Error Register\n#define AT91C_EMAC_ECOL ((AT91_REG *) \t0xFFFBC060) // (EMAC) Excessive Collision Register\n#define AT91C_EMAC_ELR  ((AT91_REG *) \t0xFFFBC070) // (EMAC) Excessive Length Error Register\n#define AT91C_EMAC_SR   ((AT91_REG *) \t0xFFFBC008) // (EMAC) Network Status Register\n#define AT91C_EMAC_RBQP ((AT91_REG *) \t0xFFFBC018) // (EMAC) Receive Buffer Queue Pointer\n#define AT91C_EMAC_CSE  ((AT91_REG *) \t0xFFFBC064) // (EMAC) Carrier Sense Error Register\n#define AT91C_EMAC_RJB  ((AT91_REG *) \t0xFFFBC074) // (EMAC) Receive Jabber Register\n#define AT91C_EMAC_USF  ((AT91_REG *) \t0xFFFBC078) // (EMAC) Undersize Frame Register\n#define AT91C_EMAC_IDR  ((AT91_REG *) \t0xFFFBC02C) // (EMAC) Interrupt Disable Register\n#define AT91C_EMAC_SA1L ((AT91_REG *) \t0xFFFBC098) // (EMAC) Specific Address 1 Low, First 4 bytes\n#define AT91C_EMAC_IMR  ((AT91_REG *) \t0xFFFBC030) // (EMAC) Interrupt Mask Register\n#define AT91C_EMAC_FRA  ((AT91_REG *) \t0xFFFBC040) // (EMAC) Frames Transmitted OK Register\n#define AT91C_EMAC_SA3H ((AT91_REG *) \t0xFFFBC0AC) // (EMAC) Specific Address 3 High, Last 2 bytes\n#define AT91C_EMAC_SA1H ((AT91_REG *) \t0xFFFBC09C) // (EMAC) Specific Address 1 High, Last 2 bytes\n#define AT91C_EMAC_SCOL ((AT91_REG *) \t0xFFFBC044) // (EMAC) Single Collision Frame Register\n#define AT91C_EMAC_ALE  ((AT91_REG *) \t0xFFFBC054) // (EMAC) Alignment Error Register\n#define AT91C_EMAC_TAR  ((AT91_REG *) \t0xFFFBC00C) // (EMAC) Transmit Address Register\n#define AT91C_EMAC_SA4L ((AT91_REG *) \t0xFFFBC0B0) // (EMAC) Specific Address 4 Low, First 4 bytes\n#define AT91C_EMAC_SA2L ((AT91_REG *) \t0xFFFBC0A0) // (EMAC) Specific Address 2 Low, First 4 bytes\n#define AT91C_EMAC_TUE  ((AT91_REG *) \t0xFFFBC068) // (EMAC) Transmit Underrun Error Register\n#define AT91C_EMAC_DTE  ((AT91_REG *) \t0xFFFBC058) // (EMAC) Deferred Transmission Frame Register\n#define AT91C_EMAC_TCR  ((AT91_REG *) \t0xFFFBC010) // (EMAC) Transmit Control Register\n#define AT91C_EMAC_CTL  ((AT91_REG *) \t0xFFFBC000) // (EMAC) Network Control Register\n#define AT91C_EMAC_SA4H ((AT91_REG *) \t0xFFFBC0B4) // (EMAC) Specific Address 4 High, Last 2 bytesr\n#define AT91C_EMAC_CDE  ((AT91_REG *) \t0xFFFBC06C) // (EMAC) Code Error Register\n#define AT91C_EMAC_SQEE ((AT91_REG *) \t0xFFFBC07C) // (EMAC) SQE Test Error Register\n#define AT91C_EMAC_TSR  ((AT91_REG *) \t0xFFFBC014) // (EMAC) Transmit Status Register\n#define AT91C_EMAC_DRFC ((AT91_REG *) \t0xFFFBC080) // (EMAC) Discarded RX Frame Register\n// ========== Register definition for EBI peripheral ========== \n#define AT91C_EBI_CFGR  ((AT91_REG *) \t0xFFFFFF64) // (EBI) Configuration Register\n#define AT91C_EBI_CSA   ((AT91_REG *) \t0xFFFFFF60) // (EBI) Chip Select Assignment Register\n// ========== Register definition for SMC2 peripheral ========== \n#define AT91C_SMC2_CSR  ((AT91_REG *) \t0xFFFFFF70) // (SMC2) SMC2 Chip Select Register\n// ========== Register definition for SDRC peripheral ========== \n#define AT91C_SDRC_IMR  ((AT91_REG *) \t0xFFFFFFAC) // (SDRC) SDRAM Controller Interrupt Mask Register\n#define AT91C_SDRC_IER  ((AT91_REG *) \t0xFFFFFFA4) // (SDRC) SDRAM Controller Interrupt Enable Register\n#define AT91C_SDRC_SRR  ((AT91_REG *) \t0xFFFFFF9C) // (SDRC) SDRAM Controller Self Refresh Register\n#define AT91C_SDRC_TR   ((AT91_REG *) \t0xFFFFFF94) // (SDRC) SDRAM Controller Refresh Timer Register\n#define AT91C_SDRC_ISR  ((AT91_REG *) \t0xFFFFFFB0) // (SDRC) SDRAM Controller Interrupt Mask Register\n#define AT91C_SDRC_IDR  ((AT91_REG *) \t0xFFFFFFA8) // (SDRC) SDRAM Controller Interrupt Disable Register\n#define AT91C_SDRC_LPR  ((AT91_REG *) \t0xFFFFFFA0) // (SDRC) SDRAM Controller Low Power Register\n#define AT91C_SDRC_CR   ((AT91_REG *) \t0xFFFFFF98) // (SDRC) SDRAM Controller Configuration Register\n#define AT91C_SDRC_MR   ((AT91_REG *) \t0xFFFFFF90) // (SDRC) SDRAM Controller Mode Register\n// ========== Register definition for BFC peripheral ========== \n#define AT91C_BFC_MR    ((AT91_REG *) \t0xFFFFFFC0) // (BFC) BFC Mode Register\n\n// *****************************************************************************\n//               PIO DEFINITIONS FOR AT91RM9200\n// *****************************************************************************\n#define AT91C_PIO_PA0        ((unsigned int) 1 <<  0) // Pin Controlled by PA0\n#define AT91C_PA0_MISO     ((unsigned int) AT91C_PIO_PA0) //  SPI Master In Slave\n#define AT91C_PA0_PCK3     ((unsigned int) AT91C_PIO_PA0) //  PMC Programmable Clock Output 3\n#define AT91C_PIO_PA1        ((unsigned int) 1 <<  1) // Pin Controlled by PA1\n#define AT91C_PA1_MOSI     ((unsigned int) AT91C_PIO_PA1) //  SPI Master Out Slave\n#define AT91C_PA1_PCK0     ((unsigned int) AT91C_PIO_PA1) //  PMC Programmable Clock Output 0\n#define AT91C_PIO_PA10       ((unsigned int) 1 << 10) // Pin Controlled by PA10\n#define AT91C_PA10_ETX1     ((unsigned int) AT91C_PIO_PA10) //  Ethernet MAC Transmit Data 1\n#define AT91C_PA10_MCDB1    ((unsigned int) AT91C_PIO_PA10) //  Multimedia Card B Data 1\n#define AT91C_PIO_PA11       ((unsigned int) 1 << 11) // Pin Controlled by PA11\n#define AT91C_PA11_ECRS_ECRSDV ((unsigned int) AT91C_PIO_PA11) //  Ethernet MAC Carrier Sense/Carrier Sense and Data Valid\n#define AT91C_PA11_MCDB2    ((unsigned int) AT91C_PIO_PA11) //  Multimedia Card B Data 2\n#define AT91C_PIO_PA12       ((unsigned int) 1 << 12) // Pin Controlled by PA12\n#define AT91C_PA12_ERX0     ((unsigned int) AT91C_PIO_PA12) //  Ethernet MAC Receive Data 0\n#define AT91C_PA12_MCDB3    ((unsigned int) AT91C_PIO_PA12) //  Multimedia Card B Data 3\n#define AT91C_PIO_PA13       ((unsigned int) 1 << 13) // Pin Controlled by PA13\n#define AT91C_PA13_ERX1     ((unsigned int) AT91C_PIO_PA13) //  Ethernet MAC Receive Data 1\n#define AT91C_PA13_TCLK0    ((unsigned int) AT91C_PIO_PA13) //  Timer Counter 0 external clock input\n#define AT91C_PIO_PA14       ((unsigned int) 1 << 14) // Pin Controlled by PA14\n#define AT91C_PA14_ERXER    ((unsigned int) AT91C_PIO_PA14) //  Ethernet MAC Receive Error\n#define AT91C_PA14_TCLK1    ((unsigned int) AT91C_PIO_PA14) //  Timer Counter 1 external clock input\n#define AT91C_PIO_PA15       ((unsigned int) 1 << 15) // Pin Controlled by PA15\n#define AT91C_PA15_EMDC     ((unsigned int) AT91C_PIO_PA15) //  Ethernet MAC Management Data Clock\n#define AT91C_PA15_TCLK2    ((unsigned int) AT91C_PIO_PA15) //  Timer Counter 2 external clock input\n#define AT91C_PIO_PA16       ((unsigned int) 1 << 16) // Pin Controlled by PA16\n#define AT91C_PA16_EMDIO    ((unsigned int) AT91C_PIO_PA16) //  Ethernet MAC Management Data Input/Output\n#define AT91C_PA16_IRQ6     ((unsigned int) AT91C_PIO_PA16) //  AIC Interrupt input 6\n#define AT91C_PIO_PA17       ((unsigned int) 1 << 17) // Pin Controlled by PA17\n#define AT91C_PA17_TXD0     ((unsigned int) AT91C_PIO_PA17) //  USART 0 Transmit Data\n#define AT91C_PA17_TIOA0    ((unsigned int) AT91C_PIO_PA17) //  Timer Counter 0 Multipurpose Timer I/O Pin A\n#define AT91C_PIO_PA18       ((unsigned int) 1 << 18) // Pin Controlled by PA18\n#define AT91C_PA18_RXD0     ((unsigned int) AT91C_PIO_PA18) //  USART 0 Receive Data\n#define AT91C_PA18_TIOB0    ((unsigned int) AT91C_PIO_PA18) //  Timer Counter 0 Multipurpose Timer I/O Pin B\n#define AT91C_PIO_PA19       ((unsigned int) 1 << 19) // Pin Controlled by PA19\n#define AT91C_PA19_SCK0     ((unsigned int) AT91C_PIO_PA19) //  USART 0 Serial Clock\n#define AT91C_PA19_TIOA1    ((unsigned int) AT91C_PIO_PA19) //  Timer Counter 1 Multipurpose Timer I/O Pin A\n#define AT91C_PIO_PA2        ((unsigned int) 1 <<  2) // Pin Controlled by PA2\n#define AT91C_PA2_SPCK     ((unsigned int) AT91C_PIO_PA2) //  SPI Serial Clock\n#define AT91C_PA2_IRQ4     ((unsigned int) AT91C_PIO_PA2) //  AIC Interrupt Input 4\n#define AT91C_PIO_PA20       ((unsigned int) 1 << 20) // Pin Controlled by PA20\n#define AT91C_PA20_CTS0     ((unsigned int) AT91C_PIO_PA20) //  USART 0 Clear To Send\n#define AT91C_PA20_TIOB1    ((unsigned int) AT91C_PIO_PA20) //  Timer Counter 1 Multipurpose Timer I/O Pin B\n#define AT91C_PIO_PA21       ((unsigned int) 1 << 21) // Pin Controlled by PA21\n#define AT91C_PA21_RTS0     ((unsigned int) AT91C_PIO_PA21) //  Usart 0 Ready To Send\n#define AT91C_PA21_TIOA2    ((unsigned int) AT91C_PIO_PA21) //  Timer Counter 2 Multipurpose Timer I/O Pin A\n#define AT91C_PIO_PA22       ((unsigned int) 1 << 22) // Pin Controlled by PA22\n#define AT91C_PA22_RXD2     ((unsigned int) AT91C_PIO_PA22) //  USART 2 Receive Data\n#define AT91C_PA22_TIOB2    ((unsigned int) AT91C_PIO_PA22) //  Timer Counter 2 Multipurpose Timer I/O Pin B\n#define AT91C_PIO_PA23       ((unsigned int) 1 << 23) // Pin Controlled by PA23\n#define AT91C_PA23_TXD2     ((unsigned int) AT91C_PIO_PA23) //  USART 2 Transmit Data\n#define AT91C_PA23_IRQ3     ((unsigned int) AT91C_PIO_PA23) //  Interrupt input 3\n#define AT91C_PIO_PA24       ((unsigned int) 1 << 24) // Pin Controlled by PA24\n#define AT91C_PA24_SCK2     ((unsigned int) AT91C_PIO_PA24) //  USART2 Serial Clock\n#define AT91C_PA24_PCK1     ((unsigned int) AT91C_PIO_PA24) //  PMC Programmable Clock Output 1\n#define AT91C_PIO_PA25       ((unsigned int) 1 << 25) // Pin Controlled by PA25\n#define AT91C_PA25_TWD      ((unsigned int) AT91C_PIO_PA25) //  TWI Two-wire Serial Data\n#define AT91C_PA25_IRQ2     ((unsigned int) AT91C_PIO_PA25) //  Interrupt input 2\n#define AT91C_PIO_PA26       ((unsigned int) 1 << 26) // Pin Controlled by PA26\n#define AT91C_PA26_TWCK     ((unsigned int) AT91C_PIO_PA26) //  TWI Two-wire Serial Clock\n#define AT91C_PA26_IRQ1     ((unsigned int) AT91C_PIO_PA26) //  Interrupt input 1\n#define AT91C_PIO_PA27       ((unsigned int) 1 << 27) // Pin Controlled by PA27\n#define AT91C_PA27_MCCK     ((unsigned int) AT91C_PIO_PA27) //  Multimedia Card Clock\n#define AT91C_PA27_TCLK3    ((unsigned int) AT91C_PIO_PA27) //  Timer Counter 3 External Clock Input\n#define AT91C_PIO_PA28       ((unsigned int) 1 << 28) // Pin Controlled by PA28\n#define AT91C_PA28_MCCDA    ((unsigned int) AT91C_PIO_PA28) //  Multimedia Card A Command\n#define AT91C_PA28_TCLK4    ((unsigned int) AT91C_PIO_PA28) //  Timer Counter 4 external Clock Input\n#define AT91C_PIO_PA29       ((unsigned int) 1 << 29) // Pin Controlled by PA29\n#define AT91C_PA29_MCDA0    ((unsigned int) AT91C_PIO_PA29) //  Multimedia Card A Data 0\n#define AT91C_PA29_TCLK5    ((unsigned int) AT91C_PIO_PA29) //  Timer Counter 5 external clock input\n#define AT91C_PIO_PA3        ((unsigned int) 1 <<  3) // Pin Controlled by PA3\n#define AT91C_PA3_NPCS0    ((unsigned int) AT91C_PIO_PA3) //  SPI Peripheral Chip Select 0\n#define AT91C_PA3_IRQ5     ((unsigned int) AT91C_PIO_PA3) //  AIC Interrupt Input 5\n#define AT91C_PIO_PA30       ((unsigned int) 1 << 30) // Pin Controlled by PA30\n#define AT91C_PA30_DRXD     ((unsigned int) AT91C_PIO_PA30) //  DBGU Debug Receive Data\n#define AT91C_PA30_CTS2     ((unsigned int) AT91C_PIO_PA30) //  Usart 2 Clear To Send\n#define AT91C_PIO_PA31       ((unsigned int) 1 << 31) // Pin Controlled by PA31\n#define AT91C_PA31_DTXD     ((unsigned int) AT91C_PIO_PA31) //  DBGU Debug Transmit Data\n#define AT91C_PA31_RTS2     ((unsigned int) AT91C_PIO_PA31) //  USART 2 Ready To Send\n#define AT91C_PIO_PA4        ((unsigned int) 1 <<  4) // Pin Controlled by PA4\n#define AT91C_PA4_NPCS1    ((unsigned int) AT91C_PIO_PA4) //  SPI Peripheral Chip Select 1\n#define AT91C_PA4_PCK1     ((unsigned int) AT91C_PIO_PA4) //  PMC Programmable Clock Output 1\n#define AT91C_PIO_PA5        ((unsigned int) 1 <<  5) // Pin Controlled by PA5\n#define AT91C_PA5_NPCS2    ((unsigned int) AT91C_PIO_PA5) //  SPI Peripheral Chip Select 2\n#define AT91C_PA5_TXD3     ((unsigned int) AT91C_PIO_PA5) //  USART 3 Transmit Data\n#define AT91C_PIO_PA6        ((unsigned int) 1 <<  6) // Pin Controlled by PA6\n#define AT91C_PA6_NPCS3    ((unsigned int) AT91C_PIO_PA6) //  SPI Peripheral Chip Select 3\n#define AT91C_PA6_RXD3     ((unsigned int) AT91C_PIO_PA6) //  USART 3 Receive Data\n#define AT91C_PIO_PA7        ((unsigned int) 1 <<  7) // Pin Controlled by PA7\n#define AT91C_PA7_ETXCK_EREFCK ((unsigned int) AT91C_PIO_PA7) //  Ethernet MAC Transmit Clock/Reference Clock\n#define AT91C_PA7_PCK2     ((unsigned int) AT91C_PIO_PA7) //  PMC Programmable Clock 2\n#define AT91C_PIO_PA8        ((unsigned int) 1 <<  8) // Pin Controlled by PA8\n#define AT91C_PA8_ETXEN    ((unsigned int) AT91C_PIO_PA8) //  Ethernet MAC Transmit Enable\n#define AT91C_PA8_MCCDB    ((unsigned int) AT91C_PIO_PA8) //  Multimedia Card B Command\n#define AT91C_PIO_PA9        ((unsigned int) 1 <<  9) // Pin Controlled by PA9\n#define AT91C_PA9_ETX0     ((unsigned int) AT91C_PIO_PA9) //  Ethernet MAC Transmit Data 0\n#define AT91C_PA9_MCDB0    ((unsigned int) AT91C_PIO_PA9) //  Multimedia Card B Data 0\n#define AT91C_PIO_PB0        ((unsigned int) 1 <<  0) // Pin Controlled by PB0\n#define AT91C_PB0_TF0      ((unsigned int) AT91C_PIO_PB0) //  SSC Transmit Frame Sync 0\n#define AT91C_PB0_TIOB3    ((unsigned int) AT91C_PIO_PB0) //  Timer Counter 3 Multipurpose Timer I/O Pin B\n#define AT91C_PIO_PB1        ((unsigned int) 1 <<  1) // Pin Controlled by PB1\n#define AT91C_PB1_TK0      ((unsigned int) AT91C_PIO_PB1) //  SSC Transmit Clock 0\n#define AT91C_PB1_CTS3     ((unsigned int) AT91C_PIO_PB1) //  USART 3 Clear To Send\n#define AT91C_PIO_PB10       ((unsigned int) 1 << 10) // Pin Controlled by PB10\n#define AT91C_PB10_RK1      ((unsigned int) AT91C_PIO_PB10) //  SSC Receive Clock 1\n#define AT91C_PB10_TIOA5    ((unsigned int) AT91C_PIO_PB10) //  Timer Counter 5 Multipurpose Timer I/O Pin A\n#define AT91C_PIO_PB11       ((unsigned int) 1 << 11) // Pin Controlled by PB11\n#define AT91C_PB11_RF1      ((unsigned int) AT91C_PIO_PB11) //  SSC Receive Frame Sync 1\n#define AT91C_PB11_TIOB5    ((unsigned int) AT91C_PIO_PB11) //  Timer Counter 5 Multipurpose Timer I/O Pin B\n#define AT91C_PIO_PB12       ((unsigned int) 1 << 12) // Pin Controlled by PB12\n#define AT91C_PB12_TF2      ((unsigned int) AT91C_PIO_PB12) //  SSC Transmit Frame Sync 2\n#define AT91C_PB12_ETX2     ((unsigned int) AT91C_PIO_PB12) //  Ethernet MAC Transmit Data 2\n#define AT91C_PIO_PB13       ((unsigned int) 1 << 13) // Pin Controlled by PB13\n#define AT91C_PB13_TK2      ((unsigned int) AT91C_PIO_PB13) //  SSC Transmit Clock 2\n#define AT91C_PB13_ETX3     ((unsigned int) AT91C_PIO_PB13) //  Ethernet MAC Transmit Data 3\n#define AT91C_PIO_PB14       ((unsigned int) 1 << 14) // Pin Controlled by PB14\n#define AT91C_PB14_TD2      ((unsigned int) AT91C_PIO_PB14) //  SSC Transmit Data 2\n#define AT91C_PB14_ETXER    ((unsigned int) AT91C_PIO_PB14) //  Ethernet MAC Transmikt Coding Error\n#define AT91C_PIO_PB15       ((unsigned int) 1 << 15) // Pin Controlled by PB15\n#define AT91C_PB15_RD2      ((unsigned int) AT91C_PIO_PB15) //  SSC Receive Data 2\n#define AT91C_PB15_ERX2     ((unsigned int) AT91C_PIO_PB15) //  Ethernet MAC Receive Data 2\n#define AT91C_PIO_PB16       ((unsigned int) 1 << 16) // Pin Controlled by PB16\n#define AT91C_PB16_RK2      ((unsigned int) AT91C_PIO_PB16) //  SSC Receive Clock 2\n#define AT91C_PB16_ERX3     ((unsigned int) AT91C_PIO_PB16) //  Ethernet MAC Receive Data 3\n#define AT91C_PIO_PB17       ((unsigned int) 1 << 17) // Pin Controlled by PB17\n#define AT91C_PB17_RF2      ((unsigned int) AT91C_PIO_PB17) //  SSC Receive Frame Sync 2\n#define AT91C_PB17_ERXDV    ((unsigned int) AT91C_PIO_PB17) //  Ethernet MAC Receive Data Valid\n#define AT91C_PIO_PB18       ((unsigned int) 1 << 18) // Pin Controlled by PB18\n#define AT91C_PB18_RI1      ((unsigned int) AT91C_PIO_PB18) //  USART 1 Ring Indicator\n#define AT91C_PB18_ECOL     ((unsigned int) AT91C_PIO_PB18) //  Ethernet MAC Collision Detected\n#define AT91C_PIO_PB19       ((unsigned int) 1 << 19) // Pin Controlled by PB19\n#define AT91C_PB19_DTR1     ((unsigned int) AT91C_PIO_PB19) //  USART 1 Data Terminal ready\n#define AT91C_PB19_ERXCK    ((unsigned int) AT91C_PIO_PB19) //  Ethernet MAC Receive Clock\n#define AT91C_PIO_PB2        ((unsigned int) 1 <<  2) // Pin Controlled by PB2\n#define AT91C_PB2_TD0      ((unsigned int) AT91C_PIO_PB2) //  SSC Transmit data\n#define AT91C_PB2_SCK3     ((unsigned int) AT91C_PIO_PB2) //  USART 3 Serial Clock\n#define AT91C_PIO_PB20       ((unsigned int) 1 << 20) // Pin Controlled by PB20\n#define AT91C_PB20_TXD1     ((unsigned int) AT91C_PIO_PB20) //  USART 1 Transmit Data\n#define AT91C_PIO_PB21       ((unsigned int) 1 << 21) // Pin Controlled by PB21\n#define AT91C_PB21_RXD1     ((unsigned int) AT91C_PIO_PB21) //  USART 1 Receive Data\n#define AT91C_PIO_PB22       ((unsigned int) 1 << 22) // Pin Controlled by PB22\n#define AT91C_PB22_SCK1     ((unsigned int) AT91C_PIO_PB22) //  USART1 Serial Clock\n#define AT91C_PIO_PB23       ((unsigned int) 1 << 23) // Pin Controlled by PB23\n#define AT91C_PB23_DCD1     ((unsigned int) AT91C_PIO_PB23) //  USART 1 Data Carrier Detect\n#define AT91C_PIO_PB24       ((unsigned int) 1 << 24) // Pin Controlled by PB24\n#define AT91C_PB24_CTS1     ((unsigned int) AT91C_PIO_PB24) //  USART 1 Clear To Send\n#define AT91C_PIO_PB25       ((unsigned int) 1 << 25) // Pin Controlled by PB25\n#define AT91C_PB25_DSR1     ((unsigned int) AT91C_PIO_PB25) //  USART 1 Data Set ready\n#define AT91C_PB25_EF100    ((unsigned int) AT91C_PIO_PB25) //  Ethernet MAC Force 100 Mbits/sec\n#define AT91C_PIO_PB26       ((unsigned int) 1 << 26) // Pin Controlled by PB26\n#define AT91C_PB26_RTS1     ((unsigned int) AT91C_PIO_PB26) //  Usart 0 Ready To Send\n#define AT91C_PIO_PB27       ((unsigned int) 1 << 27) // Pin Controlled by PB27\n#define AT91C_PB27_PCK0     ((unsigned int) AT91C_PIO_PB27) //  PMC Programmable Clock Output 0\n#define AT91C_PIO_PB28       ((unsigned int) 1 << 28) // Pin Controlled by PB28\n#define AT91C_PB28_FIQ      ((unsigned int) AT91C_PIO_PB28) //  AIC Fast Interrupt Input\n#define AT91C_PIO_PB29       ((unsigned int) 1 << 29) // Pin Controlled by PB29\n#define AT91C_PB29_IRQ0     ((unsigned int) AT91C_PIO_PB29) //  Interrupt input 0\n#define AT91C_PIO_PB3        ((unsigned int) 1 <<  3) // Pin Controlled by PB3\n#define AT91C_PB3_RD0      ((unsigned int) AT91C_PIO_PB3) //  SSC Receive Data\n#define AT91C_PB3_MCDA1    ((unsigned int) AT91C_PIO_PB3) //  Multimedia Card A Data 1\n#define AT91C_PIO_PB4        ((unsigned int) 1 <<  4) // Pin Controlled by PB4\n#define AT91C_PB4_RK0      ((unsigned int) AT91C_PIO_PB4) //  SSC Receive Clock\n#define AT91C_PB4_MCDA2    ((unsigned int) AT91C_PIO_PB4) //  Multimedia Card A Data 2\n#define AT91C_PIO_PB5        ((unsigned int) 1 <<  5) // Pin Controlled by PB5\n#define AT91C_PB5_RF0      ((unsigned int) AT91C_PIO_PB5) //  SSC Receive Frame Sync 0\n#define AT91C_PB5_MCDA3    ((unsigned int) AT91C_PIO_PB5) //  Multimedia Card A Data 3\n#define AT91C_PIO_PB6        ((unsigned int) 1 <<  6) // Pin Controlled by PB6\n#define AT91C_PB6_TF1      ((unsigned int) AT91C_PIO_PB6) //  SSC Transmit Frame Sync 1\n#define AT91C_PB6_TIOA3    ((unsigned int) AT91C_PIO_PB6) //  Timer Counter 4 Multipurpose Timer I/O Pin A\n#define AT91C_PIO_PB7        ((unsigned int) 1 <<  7) // Pin Controlled by PB7\n#define AT91C_PB7_TK1      ((unsigned int) AT91C_PIO_PB7) //  SSC Transmit Clock 1\n#define AT91C_PB7_TIOB3    ((unsigned int) AT91C_PIO_PB7) //  Timer Counter 3 Multipurpose Timer I/O Pin B\n#define AT91C_PIO_PB8        ((unsigned int) 1 <<  8) // Pin Controlled by PB8\n#define AT91C_PB8_TD1      ((unsigned int) AT91C_PIO_PB8) //  SSC Transmit Data 1\n#define AT91C_PB8_TIOA4    ((unsigned int) AT91C_PIO_PB8) //  Timer Counter 4 Multipurpose Timer I/O Pin A\n#define AT91C_PIO_PB9        ((unsigned int) 1 <<  9) // Pin Controlled by PB9\n#define AT91C_PB9_RD1      ((unsigned int) AT91C_PIO_PB9) //  SSC Receive Data 1\n#define AT91C_PB9_TIOB4    ((unsigned int) AT91C_PIO_PB9) //  Timer Counter 4 Multipurpose Timer I/O Pin B\n#define AT91C_PIO_PC0        ((unsigned int) 1 <<  0) // Pin Controlled by PC0\n#define AT91C_PC0_BFCK     ((unsigned int) AT91C_PIO_PC0) //  Burst Flash Clock\n#define AT91C_PIO_PC1        ((unsigned int) 1 <<  1) // Pin Controlled by PC1\n#define AT91C_PC1_BFRDY_SMOE ((unsigned int) AT91C_PIO_PC1) //  Burst Flash Ready\n#define AT91C_PIO_PC10       ((unsigned int) 1 << 10) // Pin Controlled by PC10\n#define AT91C_PC10_NCS4_CFCS ((unsigned int) AT91C_PIO_PC10) //  Compact Flash Chip Select\n#define AT91C_PIO_PC11       ((unsigned int) 1 << 11) // Pin Controlled by PC11\n#define AT91C_PC11_NCS5_CFCE1 ((unsigned int) AT91C_PIO_PC11) //  Chip Select 5 / Compact Flash Chip Enable 1\n#define AT91C_PIO_PC12       ((unsigned int) 1 << 12) // Pin Controlled by PC12\n#define AT91C_PC12_NCS6_CFCE2 ((unsigned int) AT91C_PIO_PC12) //  Chip Select 6 / Compact Flash Chip Enable 2\n#define AT91C_PIO_PC13       ((unsigned int) 1 << 13) // Pin Controlled by PC13\n#define AT91C_PC13_NCS7     ((unsigned int) AT91C_PIO_PC13) //  Chip Select 7\n#define AT91C_PIO_PC14       ((unsigned int) 1 << 14) // Pin Controlled by PC14\n#define AT91C_PIO_PC15       ((unsigned int) 1 << 15) // Pin Controlled by PC15\n#define AT91C_PIO_PC16       ((unsigned int) 1 << 16) // Pin Controlled by PC16\n#define AT91C_PC16_D16      ((unsigned int) AT91C_PIO_PC16) //  Data Bus [16]\n#define AT91C_PIO_PC17       ((unsigned int) 1 << 17) // Pin Controlled by PC17\n#define AT91C_PC17_D17      ((unsigned int) AT91C_PIO_PC17) //  Data Bus [17]\n#define AT91C_PIO_PC18       ((unsigned int) 1 << 18) // Pin Controlled by PC18\n#define AT91C_PC18_D18      ((unsigned int) AT91C_PIO_PC18) //  Data Bus [18]\n#define AT91C_PIO_PC19       ((unsigned int) 1 << 19) // Pin Controlled by PC19\n#define AT91C_PC19_D19      ((unsigned int) AT91C_PIO_PC19) //  Data Bus [19]\n#define AT91C_PIO_PC2        ((unsigned int) 1 <<  2) // Pin Controlled by PC2\n#define AT91C_PC2_BFAVD    ((unsigned int) AT91C_PIO_PC2) //  Burst Flash Address Valid\n#define AT91C_PIO_PC20       ((unsigned int) 1 << 20) // Pin Controlled by PC20\n#define AT91C_PC20_D20      ((unsigned int) AT91C_PIO_PC20) //  Data Bus [20]\n#define AT91C_PIO_PC21       ((unsigned int) 1 << 21) // Pin Controlled by PC21\n#define AT91C_PC21_D21      ((unsigned int) AT91C_PIO_PC21) //  Data Bus [21]\n#define AT91C_PIO_PC22       ((unsigned int) 1 << 22) // Pin Controlled by PC22\n#define AT91C_PC22_D22      ((unsigned int) AT91C_PIO_PC22) //  Data Bus [22]\n#define AT91C_PIO_PC23       ((unsigned int) 1 << 23) // Pin Controlled by PC23\n#define AT91C_PC23_D23      ((unsigned int) AT91C_PIO_PC23) //  Data Bus [23]\n#define AT91C_PIO_PC24       ((unsigned int) 1 << 24) // Pin Controlled by PC24\n#define AT91C_PC24_D24      ((unsigned int) AT91C_PIO_PC24) //  Data Bus [24]\n#define AT91C_PIO_PC25       ((unsigned int) 1 << 25) // Pin Controlled by PC25\n#define AT91C_PC25_D25      ((unsigned int) AT91C_PIO_PC25) //  Data Bus [25]\n#define AT91C_PIO_PC26       ((unsigned int) 1 << 26) // Pin Controlled by PC26\n#define AT91C_PC26_D26      ((unsigned int) AT91C_PIO_PC26) //  Data Bus [26]\n#define AT91C_PIO_PC27       ((unsigned int) 1 << 27) // Pin Controlled by PC27\n#define AT91C_PC27_D27      ((unsigned int) AT91C_PIO_PC27) //  Data Bus [27]\n#define AT91C_PIO_PC28       ((unsigned int) 1 << 28) // Pin Controlled by PC28\n#define AT91C_PC28_D28      ((unsigned int) AT91C_PIO_PC28) //  Data Bus [28]\n#define AT91C_PIO_PC29       ((unsigned int) 1 << 29) // Pin Controlled by PC29\n#define AT91C_PC29_D29      ((unsigned int) AT91C_PIO_PC29) //  Data Bus [29]\n#define AT91C_PIO_PC3        ((unsigned int) 1 <<  3) // Pin Controlled by PC3\n#define AT91C_PC3_BFBAA_SMWE ((unsigned int) AT91C_PIO_PC3) //  Burst Flash Address Advance / SmartMedia Write Enable\n#define AT91C_PIO_PC30       ((unsigned int) 1 << 30) // Pin Controlled by PC30\n#define AT91C_PC30_D30      ((unsigned int) AT91C_PIO_PC30) //  Data Bus [30]\n#define AT91C_PIO_PC31       ((unsigned int) 1 << 31) // Pin Controlled by PC31\n#define AT91C_PC31_D31      ((unsigned int) AT91C_PIO_PC31) //  Data Bus [31]\n#define AT91C_PIO_PC4        ((unsigned int) 1 <<  4) // Pin Controlled by PC4\n#define AT91C_PC4_BFOE     ((unsigned int) AT91C_PIO_PC4) //  Burst Flash Output Enable\n#define AT91C_PIO_PC5        ((unsigned int) 1 <<  5) // Pin Controlled by PC5\n#define AT91C_PC5_BFWE     ((unsigned int) AT91C_PIO_PC5) //  Burst Flash Write Enable\n#define AT91C_PIO_PC6        ((unsigned int) 1 <<  6) // Pin Controlled by PC6\n#define AT91C_PC6_NWAIT    ((unsigned int) AT91C_PIO_PC6) //  NWAIT\n#define AT91C_PIO_PC7        ((unsigned int) 1 <<  7) // Pin Controlled by PC7\n#define AT91C_PC7_A23      ((unsigned int) AT91C_PIO_PC7) //  Address Bus[23]\n#define AT91C_PIO_PC8        ((unsigned int) 1 <<  8) // Pin Controlled by PC8\n#define AT91C_PC8_A24      ((unsigned int) AT91C_PIO_PC8) //  Address Bus[24]\n#define AT91C_PIO_PC9        ((unsigned int) 1 <<  9) // Pin Controlled by PC9\n#define AT91C_PC9_A25_CFRNW ((unsigned int) AT91C_PIO_PC9) //  Address Bus[25] /  Compact Flash Read Not Write\n#define AT91C_PIO_PD0        ((unsigned int) 1 <<  0) // Pin Controlled by PD0\n#define AT91C_PD0_ETX0     ((unsigned int) AT91C_PIO_PD0) //  Ethernet MAC Transmit Data 0\n#define AT91C_PIO_PD1        ((unsigned int) 1 <<  1) // Pin Controlled by PD1\n#define AT91C_PD1_ETX1     ((unsigned int) AT91C_PIO_PD1) //  Ethernet MAC Transmit Data 1\n#define AT91C_PIO_PD10       ((unsigned int) 1 << 10) // Pin Controlled by PD10\n#define AT91C_PD10_PCK3     ((unsigned int) AT91C_PIO_PD10) //  PMC Programmable Clock Output 3\n#define AT91C_PD10_TPS1     ((unsigned int) AT91C_PIO_PD10) //  ETM ARM9 pipeline status 1\n#define AT91C_PIO_PD11       ((unsigned int) 1 << 11) // Pin Controlled by PD11\n#define AT91C_PD11_         ((unsigned int) AT91C_PIO_PD11) //  \n#define AT91C_PD11_TPS2     ((unsigned int) AT91C_PIO_PD11) //  ETM ARM9 pipeline status 2\n#define AT91C_PIO_PD12       ((unsigned int) 1 << 12) // Pin Controlled by PD12\n#define AT91C_PD12_         ((unsigned int) AT91C_PIO_PD12) //  \n#define AT91C_PD12_TPK0     ((unsigned int) AT91C_PIO_PD12) //  ETM Trace Packet 0\n#define AT91C_PIO_PD13       ((unsigned int) 1 << 13) // Pin Controlled by PD13\n#define AT91C_PD13_         ((unsigned int) AT91C_PIO_PD13) //  \n#define AT91C_PD13_TPK1     ((unsigned int) AT91C_PIO_PD13) //  ETM Trace Packet 1\n#define AT91C_PIO_PD14       ((unsigned int) 1 << 14) // Pin Controlled by PD14\n#define AT91C_PD14_         ((unsigned int) AT91C_PIO_PD14) //  \n#define AT91C_PD14_TPK2     ((unsigned int) AT91C_PIO_PD14) //  ETM Trace Packet 2\n#define AT91C_PIO_PD15       ((unsigned int) 1 << 15) // Pin Controlled by PD15\n#define AT91C_PD15_TD0      ((unsigned int) AT91C_PIO_PD15) //  SSC Transmit data\n#define AT91C_PD15_TPK3     ((unsigned int) AT91C_PIO_PD15) //  ETM Trace Packet 3\n#define AT91C_PIO_PD16       ((unsigned int) 1 << 16) // Pin Controlled by PD16\n#define AT91C_PD16_TD1      ((unsigned int) AT91C_PIO_PD16) //  SSC Transmit Data 1\n#define AT91C_PD16_TPK4     ((unsigned int) AT91C_PIO_PD16) //  ETM Trace Packet 4\n#define AT91C_PIO_PD17       ((unsigned int) 1 << 17) // Pin Controlled by PD17\n#define AT91C_PD17_TD2      ((unsigned int) AT91C_PIO_PD17) //  SSC Transmit Data 2\n#define AT91C_PD17_TPK5     ((unsigned int) AT91C_PIO_PD17) //  ETM Trace Packet 5\n#define AT91C_PIO_PD18       ((unsigned int) 1 << 18) // Pin Controlled by PD18\n#define AT91C_PD18_NPCS1    ((unsigned int) AT91C_PIO_PD18) //  SPI Peripheral Chip Select 1\n#define AT91C_PD18_TPK6     ((unsigned int) AT91C_PIO_PD18) //  ETM Trace Packet 6\n#define AT91C_PIO_PD19       ((unsigned int) 1 << 19) // Pin Controlled by PD19\n#define AT91C_PD19_NPCS2    ((unsigned int) AT91C_PIO_PD19) //  SPI Peripheral Chip Select 2\n#define AT91C_PD19_TPK7     ((unsigned int) AT91C_PIO_PD19) //  ETM Trace Packet 7\n#define AT91C_PIO_PD2        ((unsigned int) 1 <<  2) // Pin Controlled by PD2\n#define AT91C_PD2_ETX2     ((unsigned int) AT91C_PIO_PD2) //  Ethernet MAC Transmit Data 2\n#define AT91C_PIO_PD20       ((unsigned int) 1 << 20) // Pin Controlled by PD20\n#define AT91C_PD20_NPCS3    ((unsigned int) AT91C_PIO_PD20) //  SPI Peripheral Chip Select 3\n#define AT91C_PD20_TPK8     ((unsigned int) AT91C_PIO_PD20) //  ETM Trace Packet 8\n#define AT91C_PIO_PD21       ((unsigned int) 1 << 21) // Pin Controlled by PD21\n#define AT91C_PD21_RTS0     ((unsigned int) AT91C_PIO_PD21) //  Usart 0 Ready To Send\n#define AT91C_PD21_TPK9     ((unsigned int) AT91C_PIO_PD21) //  ETM Trace Packet 9\n#define AT91C_PIO_PD22       ((unsigned int) 1 << 22) // Pin Controlled by PD22\n#define AT91C_PD22_RTS1     ((unsigned int) AT91C_PIO_PD22) //  Usart 0 Ready To Send\n#define AT91C_PD22_TPK10    ((unsigned int) AT91C_PIO_PD22) //  ETM Trace Packet 10\n#define AT91C_PIO_PD23       ((unsigned int) 1 << 23) // Pin Controlled by PD23\n#define AT91C_PD23_RTS2     ((unsigned int) AT91C_PIO_PD23) //  USART 2 Ready To Send\n#define AT91C_PD23_TPK11    ((unsigned int) AT91C_PIO_PD23) //  ETM Trace Packet 11\n#define AT91C_PIO_PD24       ((unsigned int) 1 << 24) // Pin Controlled by PD24\n#define AT91C_PD24_RTS3     ((unsigned int) AT91C_PIO_PD24) //  USART 3 Ready To Send\n#define AT91C_PD24_TPK12    ((unsigned int) AT91C_PIO_PD24) //  ETM Trace Packet 12\n#define AT91C_PIO_PD25       ((unsigned int) 1 << 25) // Pin Controlled by PD25\n#define AT91C_PD25_DTR1     ((unsigned int) AT91C_PIO_PD25) //  USART 1 Data Terminal ready\n#define AT91C_PD25_TPK13    ((unsigned int) AT91C_PIO_PD25) //  ETM Trace Packet 13\n#define AT91C_PIO_PD26       ((unsigned int) 1 << 26) // Pin Controlled by PD26\n#define AT91C_PD26_TPK14    ((unsigned int) AT91C_PIO_PD26) //  ETM Trace Packet 14\n#define AT91C_PIO_PD27       ((unsigned int) 1 << 27) // Pin Controlled by PD27\n#define AT91C_PD27_TPK15    ((unsigned int) AT91C_PIO_PD27) //  ETM Trace Packet 15\n#define AT91C_PIO_PD3        ((unsigned int) 1 <<  3) // Pin Controlled by PD3\n#define AT91C_PD3_ETX3     ((unsigned int) AT91C_PIO_PD3) //  Ethernet MAC Transmit Data 3\n#define AT91C_PIO_PD4        ((unsigned int) 1 <<  4) // Pin Controlled by PD4\n#define AT91C_PD4_ETXEN    ((unsigned int) AT91C_PIO_PD4) //  Ethernet MAC Transmit Enable\n#define AT91C_PIO_PD5        ((unsigned int) 1 <<  5) // Pin Controlled by PD5\n#define AT91C_PD5_ETXER    ((unsigned int) AT91C_PIO_PD5) //  Ethernet MAC Transmikt Coding Error\n#define AT91C_PIO_PD6        ((unsigned int) 1 <<  6) // Pin Controlled by PD6\n#define AT91C_PD6_DTXD     ((unsigned int) AT91C_PIO_PD6) //  DBGU Debug Transmit Data\n#define AT91C_PIO_PD7        ((unsigned int) 1 <<  7) // Pin Controlled by PD7\n#define AT91C_PD7_PCK0     ((unsigned int) AT91C_PIO_PD7) //  PMC Programmable Clock Output 0\n#define AT91C_PD7_TSYNC    ((unsigned int) AT91C_PIO_PD7) //  ETM Synchronization signal\n#define AT91C_PIO_PD8        ((unsigned int) 1 <<  8) // Pin Controlled by PD8\n#define AT91C_PD8_PCK1     ((unsigned int) AT91C_PIO_PD8) //  PMC Programmable Clock Output 1\n#define AT91C_PD8_TCLK     ((unsigned int) AT91C_PIO_PD8) //  ETM Trace Clock signal\n#define AT91C_PIO_PD9        ((unsigned int) 1 <<  9) // Pin Controlled by PD9\n#define AT91C_PD9_PCK2     ((unsigned int) AT91C_PIO_PD9) //  PMC Programmable Clock 2\n#define AT91C_PD9_TPS0     ((unsigned int) AT91C_PIO_PD9) //  ETM ARM9 pipeline status 0\n\n// *****************************************************************************\n//               PERIPHERAL ID DEFINITIONS FOR AT91RM9200\n// *****************************************************************************\n#define AT91C_ID_FIQ    ((unsigned int)  0) // Advanced Interrupt Controller (FIQ)\n#define AT91C_ID_SYS    ((unsigned int)  1) // System Peripheral\n#define AT91C_ID_PIOA   ((unsigned int)  2) // Parallel IO Controller A \n#define AT91C_ID_PIOB   ((unsigned int)  3) // Parallel IO Controller B\n#define AT91C_ID_PIOC   ((unsigned int)  4) // Parallel IO Controller C\n#define AT91C_ID_PIOD   ((unsigned int)  5) // Parallel IO Controller D\n#define AT91C_ID_US0    ((unsigned int)  6) // USART 0\n#define AT91C_ID_US1    ((unsigned int)  7) // USART 1\n#define AT91C_ID_US2    ((unsigned int)  8) // USART 2\n#define AT91C_ID_US3    ((unsigned int)  9) // USART 3\n#define AT91C_ID_MCI    ((unsigned int) 10) // Multimedia Card Interface\n#define AT91C_ID_UDP    ((unsigned int) 11) // USB Device Port\n#define AT91C_ID_TWI    ((unsigned int) 12) // Two-Wire Interface\n#define AT91C_ID_SPI    ((unsigned int) 13) // Serial Peripheral Interface\n#define AT91C_ID_SSC0   ((unsigned int) 14) // Serial Synchronous Controller 0\n#define AT91C_ID_SSC1   ((unsigned int) 15) // Serial Synchronous Controller 1\n#define AT91C_ID_SSC2   ((unsigned int) 16) // Serial Synchronous Controller 2\n#define AT91C_ID_TC0    ((unsigned int) 17) // Timer Counter 0\n#define AT91C_ID_TC1    ((unsigned int) 18) // Timer Counter 1\n#define AT91C_ID_TC2    ((unsigned int) 19) // Timer Counter 2\n#define AT91C_ID_TC3    ((unsigned int) 20) // Timer Counter 3\n#define AT91C_ID_TC4    ((unsigned int) 21) // Timer Counter 4\n#define AT91C_ID_TC5    ((unsigned int) 22) // Timer Counter 5\n#define AT91C_ID_UHP    ((unsigned int) 23) // USB Host port\n#define AT91C_ID_EMAC   ((unsigned int) 24) // Ethernet MAC\n#define AT91C_ID_IRQ0   ((unsigned int) 25) // Advanced Interrupt Controller (IRQ0)\n#define AT91C_ID_IRQ1   ((unsigned int) 26) // Advanced Interrupt Controller (IRQ1)\n#define AT91C_ID_IRQ2   ((unsigned int) 27) // Advanced Interrupt Controller (IRQ2)\n#define AT91C_ID_IRQ3   ((unsigned int) 28) // Advanced Interrupt Controller (IRQ3)\n#define AT91C_ID_IRQ4   ((unsigned int) 29) // Advanced Interrupt Controller (IRQ4)\n#define AT91C_ID_IRQ5   ((unsigned int) 30) // Advanced Interrupt Controller (IRQ5)\n#define AT91C_ID_IRQ6   ((unsigned int) 31) // Advanced Interrupt Controller (IRQ6)\n\n// *****************************************************************************\n//               BASE ADDRESS DEFINITIONS FOR AT91RM9200\n// *****************************************************************************\n#define AT91C_BASE_SYS       ((AT91PS_SYS) \t0xFFFFF000) // (SYS) Base Address\n#define AT91C_BASE_MC        ((AT91PS_MC) \t0xFFFFFF00) // (MC) Base Address\n#define AT91C_BASE_RTC       ((AT91PS_RTC) \t0xFFFFFE00) // (RTC) Base Address\n#define AT91C_BASE_ST        ((AT91PS_ST) \t0xFFFFFD00) // (ST) Base Address\n#define AT91C_BASE_PMC       ((AT91PS_PMC) \t0xFFFFFC00) // (PMC) Base Address\n#define AT91C_BASE_CKGR      ((AT91PS_CKGR) \t0xFFFFFC20) // (CKGR) Base Address\n#define AT91C_BASE_PIOD      ((AT91PS_PIO) \t0xFFFFFA00) // (PIOD) Base Address\n#define AT91C_BASE_PIOC      ((AT91PS_PIO) \t0xFFFFF800) // (PIOC) Base Address\n#define AT91C_BASE_PIOB      ((AT91PS_PIO) \t0xFFFFF600) // (PIOB) Base Address\n#define AT91C_BASE_PIOA      ((AT91PS_PIO) \t0xFFFFF400) // (PIOA) Base Address\n#define AT91C_BASE_DBGU      ((AT91PS_DBGU) \t0xFFFFF200) // (DBGU) Base Address\n#define AT91C_BASE_PDC_DBGU  ((AT91PS_PDC) \t0xFFFFF300) // (PDC_DBGU) Base Address\n#define AT91C_BASE_AIC       ((AT91PS_AIC) \t0xFFFFF000) // (AIC) Base Address\n#define AT91C_BASE_PDC_SPI   ((AT91PS_PDC) \t0xFFFE0100) // (PDC_SPI) Base Address\n#define AT91C_BASE_SPI       ((AT91PS_SPI) \t0xFFFE0000) // (SPI) Base Address\n#define AT91C_BASE_PDC_SSC2  ((AT91PS_PDC) \t0xFFFD8100) // (PDC_SSC2) Base Address\n#define AT91C_BASE_SSC2      ((AT91PS_SSC) \t0xFFFD8000) // (SSC2) Base Address\n#define AT91C_BASE_PDC_SSC1  ((AT91PS_PDC) \t0xFFFD4100) // (PDC_SSC1) Base Address\n#define AT91C_BASE_SSC1      ((AT91PS_SSC) \t0xFFFD4000) // (SSC1) Base Address\n#define AT91C_BASE_PDC_SSC0  ((AT91PS_PDC) \t0xFFFD0100) // (PDC_SSC0) Base Address\n#define AT91C_BASE_SSC0      ((AT91PS_SSC) \t0xFFFD0000) // (SSC0) Base Address\n#define AT91C_BASE_PDC_US3   ((AT91PS_PDC) \t0xFFFCC100) // (PDC_US3) Base Address\n#define AT91C_BASE_US3       ((AT91PS_USART) \t0xFFFCC000) // (US3) Base Address\n#define AT91C_BASE_PDC_US2   ((AT91PS_PDC) \t0xFFFC8100) // (PDC_US2) Base Address\n#define AT91C_BASE_US2       ((AT91PS_USART) \t0xFFFC8000) // (US2) Base Address\n#define AT91C_BASE_PDC_US1   ((AT91PS_PDC) \t0xFFFC4100) // (PDC_US1) Base Address\n#define AT91C_BASE_US1       ((AT91PS_USART) \t0xFFFC4000) // (US1) Base Address\n#define AT91C_BASE_PDC_US0   ((AT91PS_PDC) \t0xFFFC0100) // (PDC_US0) Base Address\n#define AT91C_BASE_US0       ((AT91PS_USART) \t0xFFFC0000) // (US0) Base Address\n#define AT91C_BASE_TWI       ((AT91PS_TWI) \t0xFFFB8000) // (TWI) Base Address\n#define AT91C_BASE_PDC_MCI   ((AT91PS_PDC) \t0xFFFB4100) // (PDC_MCI) Base Address\n#define AT91C_BASE_MCI       ((AT91PS_MCI) \t0xFFFB4000) // (MCI) Base Address\n#define AT91C_BASE_UDP       ((AT91PS_UDP) \t0xFFFB0000) // (UDP) Base Address\n#define AT91C_BASE_TC5       ((AT91PS_TC) \t0xFFFA4080) // (TC5) Base Address\n#define AT91C_BASE_TC4       ((AT91PS_TC) \t0xFFFA4040) // (TC4) Base Address\n#define AT91C_BASE_TC3       ((AT91PS_TC) \t0xFFFA4000) // (TC3) Base Address\n#define AT91C_BASE_TCB1      ((AT91PS_TCB) \t0xFFFA4080) // (TCB1) Base Address\n#define AT91C_BASE_TC2       ((AT91PS_TC) \t0xFFFA0080) // (TC2) Base Address\n#define AT91C_BASE_TC1       ((AT91PS_TC) \t0xFFFA0040) // (TC1) Base Address\n#define AT91C_BASE_TC0       ((AT91PS_TC) \t0xFFFA0000) // (TC0) Base Address\n#define AT91C_BASE_TCB0      ((AT91PS_TCB) \t0xFFFA0000) // (TCB0) Base Address\n#define AT91C_BASE_UHP       ((AT91PS_UHP) \t0x00300000) // (UHP) Base Address\n#define AT91C_BASE_EMAC      ((AT91PS_EMAC) \t0xFFFBC000) // (EMAC) Base Address\n#define AT91C_BASE_EBI       ((AT91PS_EBI) \t0xFFFFFF60) // (EBI) Base Address\n#define AT91C_BASE_SMC2      ((AT91PS_SMC2) \t0xFFFFFF70) // (SMC2) Base Address\n#define AT91C_BASE_SDRC      ((AT91PS_SDRC) \t0xFFFFFF90) // (SDRC) Base Address\n#define AT91C_BASE_BFC       ((AT91PS_BFC) \t0xFFFFFFC0) // (BFC) Base Address\n\n// *****************************************************************************\n//               MEMORY MAPPING DEFINITIONS FOR AT91RM9200\n// *****************************************************************************\n#define AT91C_ISRAM\t ((char *) \t0x00200000) // Internal SRAM base address\n#define AT91C_ISRAM_SIZE\t ((unsigned int) 0x00004000) // Internal SRAM size in byte (16 Kbyte)\n#define AT91C_IROM \t ((char *) \t0x00100000) // Internal ROM base address\n#define AT91C_IROM_SIZE\t ((unsigned int) 0x00020000) // Internal ROM size in byte (128 Kbyte)\n\n#endif\n"
  },
  {
    "path": "target/linux/at91/image/dfboot/src/include/AT91RM9200.inc",
    "content": ";- ----------------------------------------------------------------------------\n;-          ATMEL Microcontroller Software Support  -  ROUSSET  -\n;- ----------------------------------------------------------------------------\n;-  The software is delivered \"AS IS\" without warranty or condition of any\n;-  kind, either express, implied or statutory. This includes without\n;-  limitation any warranty or condition with respect to merchantability or\n;-  fitness for any particular purpose, or against the infringements of\n;-  intellectual property rights of others.\n;- ----------------------------------------------------------------------------\n;- File Name           : AT91RM9200.h\n;- Object              : AT91RM9200 definitions\n;- Generated           : AT91 SW Application Group  11/19/2003 (17:20:51)\n;- \n;- CVS Reference       : /AT91RM9200.pl/1.16/Fri Feb 07 10:29:51 2003//\n;- CVS Reference       : /SYS_AT91RM9200.pl/1.2/Fri Jan 17 12:44:37 2003//\n;- CVS Reference       : /MC_1760A.pl/1.1/Fri Aug 23 14:38:22 2002//\n;- CVS Reference       : /AIC_1796B.pl/1.1.1.1/Fri Jun 28 09:36:47 2002//\n;- CVS Reference       : /PMC_2636A.pl/1.1.1.1/Fri Jun 28 09:36:48 2002//\n;- CVS Reference       : /ST_1763B.pl/1.1/Fri Aug 23 14:41:42 2002//\n;- CVS Reference       : /RTC_1245D.pl/1.2/Fri Jan 31 12:19:06 2003//\n;- CVS Reference       : /PIO_1725D.pl/1.1.1.1/Fri Jun 28 09:36:47 2002//\n;- CVS Reference       : /DBGU_1754A.pl/1.4/Fri Jan 31 12:18:24 2003//\n;- CVS Reference       : /UDP_1765B.pl/1.3/Fri Aug 02 14:45:38 2002//\n;- CVS Reference       : /MCI_1764A.pl/1.2/Thu Nov 14 17:48:24 2002//\n;- CVS Reference       : /US_1739C.pl/1.2/Fri Jul 12 07:49:25 2002//\n;- CVS Reference       : /SPI_AT91RMxxxx.pl/1.3/Tue Nov 26 10:20:29 2002//\n;- CVS Reference       : /SSC_1762A.pl/1.2/Fri Nov 08 13:26:39 2002//\n;- CVS Reference       : /TC_1753B.pl/1.2/Fri Jan 31 12:19:55 2003//\n;- CVS Reference       : /TWI_1761B.pl/1.4/Fri Feb 07 10:30:07 2003//\n;- CVS Reference       : /PDC_1734B.pl/1.2/Thu Nov 21 16:38:23 2002//\n;- CVS Reference       : /UHP_xxxxA.pl/1.1/Mon Jul 22 12:21:58 2002//\n;- CVS Reference       : /EMAC_1794A.pl/1.4/Fri Jan 17 12:11:54 2003//\n;- CVS Reference       : /EBI_1759B.pl/1.10/Fri Jan 17 12:44:29 2003//\n;- CVS Reference       : /SMC_1783A.pl/1.3/Thu Oct 31 14:38:17 2002//\n;- CVS Reference       : /SDRC_1758B.pl/1.2/Thu Oct 03 13:04:41 2002//\n;- CVS Reference       : /BFC_1757B.pl/1.3/Thu Oct 31 14:38:00 2002//\n;- ----------------------------------------------------------------------------\n\n;- Hardware register definition\n\n;- *****************************************************************************\n;-              SOFTWARE API DEFINITION  FOR System Peripherals\n;- *****************************************************************************\n\n;- *****************************************************************************\n;-              SOFTWARE API DEFINITION  FOR Memory Controller Interface\n;- *****************************************************************************\n                ^ 0 ;- AT91S_MC\nMC_RCR          #  4 ;- MC Remap Control Register\nMC_ASR          #  4 ;- MC Abort Status Register\nMC_AASR         #  4 ;- MC Abort Address Status Register\n                #  4 ;- Reserved\nMC_PUIA         # 64 ;- MC Protection Unit Area\nMC_PUP          #  4 ;- MC Protection Unit Peripherals\nMC_PUER         #  4 ;- MC Protection Unit Enable Register\n;- -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- \nAT91C_MC_RCB              EQU (0x1:SHL:0) ;- (MC) Remap Command Bit\n;- -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- \nAT91C_MC_UNDADD           EQU (0x1:SHL:0) ;- (MC) Undefined Addess Abort Status\nAT91C_MC_MISADD           EQU (0x1:SHL:1) ;- (MC) Misaligned Addess Abort Status\nAT91C_MC_MPU              EQU (0x1:SHL:2) ;- (MC) Memory protection Unit Abort Status\nAT91C_MC_ABTSZ            EQU (0x3:SHL:8) ;- (MC) Abort Size Status\nAT91C_MC_ABTSZ_BYTE       EQU (0x0:SHL:8) ;- (MC) Byte\nAT91C_MC_ABTSZ_HWORD      EQU (0x1:SHL:8) ;- (MC) Half-word\nAT91C_MC_ABTSZ_WORD       EQU (0x2:SHL:8) ;- (MC) Word\nAT91C_MC_ABTTYP           EQU (0x3:SHL:10) ;- (MC) Abort Type Status\nAT91C_MC_ABTTYP_DATAR     EQU (0x0:SHL:10) ;- (MC) Data Read\nAT91C_MC_ABTTYP_DATAW     EQU (0x1:SHL:10) ;- (MC) Data Write\nAT91C_MC_ABTTYP_FETCH     EQU (0x2:SHL:10) ;- (MC) Code Fetch\nAT91C_MC_MST0             EQU (0x1:SHL:16) ;- (MC) Master 0 Abort Source\nAT91C_MC_MST1             EQU (0x1:SHL:17) ;- (MC) Master 1 Abort Source\nAT91C_MC_SVMST0           EQU (0x1:SHL:24) ;- (MC) Saved Master 0 Abort Source\nAT91C_MC_SVMST1           EQU (0x1:SHL:25) ;- (MC) Saved Master 1 Abort Source\n;- -------- MC_PUIA : (MC Offset: 0x10) MC Protection Unit Area -------- \nAT91C_MC_PROT             EQU (0x3:SHL:0) ;- (MC) Protection\nAT91C_MC_PROT_PNAUNA      EQU (0x0) ;- (MC) Privilege: No Access, User: No Access\nAT91C_MC_PROT_PRWUNA      EQU (0x1) ;- (MC) Privilege: Read/Write, User: No Access\nAT91C_MC_PROT_PRWURO      EQU (0x2) ;- (MC) Privilege: Read/Write, User: Read Only\nAT91C_MC_PROT_PRWURW      EQU (0x3) ;- (MC) Privilege: Read/Write, User: Read/Write\nAT91C_MC_SIZE             EQU (0xF:SHL:4) ;- (MC) Internal Area Size\nAT91C_MC_SIZE_1KB         EQU (0x0:SHL:4) ;- (MC) Area size 1KByte\nAT91C_MC_SIZE_2KB         EQU (0x1:SHL:4) ;- (MC) Area size 2KByte\nAT91C_MC_SIZE_4KB         EQU (0x2:SHL:4) ;- (MC) Area size 4KByte\nAT91C_MC_SIZE_8KB         EQU (0x3:SHL:4) ;- (MC) Area size 8KByte\nAT91C_MC_SIZE_16KB        EQU (0x4:SHL:4) ;- (MC) Area size 16KByte\nAT91C_MC_SIZE_32KB        EQU (0x5:SHL:4) ;- (MC) Area size 32KByte\nAT91C_MC_SIZE_64KB        EQU (0x6:SHL:4) ;- (MC) Area size 64KByte\nAT91C_MC_SIZE_128KB       EQU (0x7:SHL:4) ;- (MC) Area size 128KByte\nAT91C_MC_SIZE_256KB       EQU (0x8:SHL:4) ;- (MC) Area size 256KByte\nAT91C_MC_SIZE_512KB       EQU (0x9:SHL:4) ;- (MC) Area size 512KByte\nAT91C_MC_SIZE_1MB         EQU (0xA:SHL:4) ;- (MC) Area size 1MByte\nAT91C_MC_SIZE_2MB         EQU (0xB:SHL:4) ;- (MC) Area size 2MByte\nAT91C_MC_SIZE_4MB         EQU (0xC:SHL:4) ;- (MC) Area size 4MByte\nAT91C_MC_SIZE_8MB         EQU (0xD:SHL:4) ;- (MC) Area size 8MByte\nAT91C_MC_SIZE_16MB        EQU (0xE:SHL:4) ;- (MC) Area size 16MByte\nAT91C_MC_SIZE_64MB        EQU (0xF:SHL:4) ;- (MC) Area size 64MByte\nAT91C_MC_BA               EQU (0x3FFFF:SHL:10) ;- (MC) Internal Area Base Address\n;- -------- MC_PUP : (MC Offset: 0x50) MC Protection Unit Peripheral -------- \n;- -------- MC_PUER : (MC Offset: 0x54) MC Protection Unit Area -------- \nAT91C_MC_PUEB             EQU (0x1:SHL:0) ;- (MC) Protection Unit enable Bit\n\n;- *****************************************************************************\n;-              SOFTWARE API DEFINITION  FOR Real-time Clock Alarm and Parallel Load Interface\n;- *****************************************************************************\n                ^ 0 ;- AT91S_RTC\nRTC_CR          #  4 ;- Control Register\nRTC_MR          #  4 ;- Mode Register\nRTC_TIMR        #  4 ;- Time Register\nRTC_CALR        #  4 ;- Calendar Register\nRTC_TIMALR      #  4 ;- Time Alarm Register\nRTC_CALALR      #  4 ;- Calendar Alarm Register\nRTC_SR          #  4 ;- Status Register\nRTC_SCCR        #  4 ;- Status Clear Command Register\nRTC_IER         #  4 ;- Interrupt Enable Register\nRTC_IDR         #  4 ;- Interrupt Disable Register\nRTC_IMR         #  4 ;- Interrupt Mask Register\nRTC_VER         #  4 ;- Valid Entry Register\n;- -------- RTC_CR : (RTC Offset: 0x0) RTC Control Register -------- \nAT91C_RTC_UPDTIM          EQU (0x1:SHL:0) ;- (RTC) Update Request Time Register\nAT91C_RTC_UPDCAL          EQU (0x1:SHL:1) ;- (RTC) Update Request Calendar Register\nAT91C_RTC_TIMEVSEL        EQU (0x3:SHL:8) ;- (RTC) Time Event Selection\nAT91C_RTC_TIMEVSEL_MINUTE EQU (0x0:SHL:8) ;- (RTC) Minute change.\nAT91C_RTC_TIMEVSEL_HOUR   EQU (0x1:SHL:8) ;- (RTC) Hour change.\nAT91C_RTC_TIMEVSEL_DAY24  EQU (0x2:SHL:8) ;- (RTC) Every day at midnight.\nAT91C_RTC_TIMEVSEL_DAY12  EQU (0x3:SHL:8) ;- (RTC) Every day at noon.\nAT91C_RTC_CALEVSEL        EQU (0x3:SHL:16) ;- (RTC) Calendar Event Selection\nAT91C_RTC_CALEVSEL_WEEK   EQU (0x0:SHL:16) ;- (RTC) Week change (every Monday at time 00:00:00).\nAT91C_RTC_CALEVSEL_MONTH  EQU (0x1:SHL:16) ;- (RTC) Month change (every 01 of each month at time 00:00:00).\nAT91C_RTC_CALEVSEL_YEAR   EQU (0x2:SHL:16) ;- (RTC) Year change (every January 1 at time 00:00:00).\n;- -------- RTC_MR : (RTC Offset: 0x4) RTC Mode Register -------- \nAT91C_RTC_HRMOD           EQU (0x1:SHL:0) ;- (RTC) 12-24 hour Mode\n;- -------- RTC_TIMR : (RTC Offset: 0x8) RTC Time Register -------- \nAT91C_RTC_SEC             EQU (0x7F:SHL:0) ;- (RTC) Current Second\nAT91C_RTC_MIN             EQU (0x7F:SHL:8) ;- (RTC) Current Minute\nAT91C_RTC_HOUR            EQU (0x1F:SHL:16) ;- (RTC) Current Hour\nAT91C_RTC_AMPM            EQU (0x1:SHL:22) ;- (RTC) Ante Meridiem, Post Meridiem Indicator\n;- -------- RTC_CALR : (RTC Offset: 0xc) RTC Calendar Register -------- \nAT91C_RTC_CENT            EQU (0x3F:SHL:0) ;- (RTC) Current Century\nAT91C_RTC_YEAR            EQU (0xFF:SHL:8) ;- (RTC) Current Year\nAT91C_RTC_MONTH           EQU (0x1F:SHL:16) ;- (RTC) Current Month\nAT91C_RTC_DAY             EQU (0x7:SHL:21) ;- (RTC) Current Day\nAT91C_RTC_DATE            EQU (0x3F:SHL:24) ;- (RTC) Current Date\n;- -------- RTC_TIMALR : (RTC Offset: 0x10) RTC Time Alarm Register -------- \nAT91C_RTC_SECEN           EQU (0x1:SHL:7) ;- (RTC) Second Alarm Enable\nAT91C_RTC_MINEN           EQU (0x1:SHL:15) ;- (RTC) Minute Alarm\nAT91C_RTC_HOUREN          EQU (0x1:SHL:23) ;- (RTC) Current Hour\n;- -------- RTC_CALALR : (RTC Offset: 0x14) RTC Calendar Alarm Register -------- \nAT91C_RTC_MONTHEN         EQU (0x1:SHL:23) ;- (RTC) Month Alarm Enable\nAT91C_RTC_DATEEN          EQU (0x1:SHL:31) ;- (RTC) Date Alarm Enable\n;- -------- RTC_SR : (RTC Offset: 0x18) RTC Status Register -------- \nAT91C_RTC_ACKUPD          EQU (0x1:SHL:0) ;- (RTC) Acknowledge for Update\nAT91C_RTC_ALARM           EQU (0x1:SHL:1) ;- (RTC) Alarm Flag\nAT91C_RTC_SECEV           EQU (0x1:SHL:2) ;- (RTC) Second Event\nAT91C_RTC_TIMEV           EQU (0x1:SHL:3) ;- (RTC) Time Event\nAT91C_RTC_CALEV           EQU (0x1:SHL:4) ;- (RTC) Calendar event\n;- -------- RTC_SCCR : (RTC Offset: 0x1c) RTC Status Clear Command Register -------- \n;- -------- RTC_IER : (RTC Offset: 0x20) RTC Interrupt Enable Register -------- \n;- -------- RTC_IDR : (RTC Offset: 0x24) RTC Interrupt Disable Register -------- \n;- -------- RTC_IMR : (RTC Offset: 0x28) RTC Interrupt Mask Register -------- \n;- -------- RTC_VER : (RTC Offset: 0x2c) RTC Valid Entry Register -------- \nAT91C_RTC_NVTIM           EQU (0x1:SHL:0) ;- (RTC) Non valid Time\nAT91C_RTC_NVCAL           EQU (0x1:SHL:1) ;- (RTC) Non valid Calendar\nAT91C_RTC_NVTIMALR        EQU (0x1:SHL:2) ;- (RTC) Non valid time Alarm\nAT91C_RTC_NVCALALR        EQU (0x1:SHL:3) ;- (RTC) Nonvalid Calendar Alarm\n\n;- *****************************************************************************\n;-              SOFTWARE API DEFINITION  FOR System Timer Interface\n;- *****************************************************************************\n                ^ 0 ;- AT91S_ST\nST_CR           #  4 ;- Control Register\nST_PIMR         #  4 ;- Period Interval Mode Register\nST_WDMR         #  4 ;- Watchdog Mode Register\nST_RTMR         #  4 ;- Real-time Mode Register\nST_SR           #  4 ;- Status Register\nST_IER          #  4 ;- Interrupt Enable Register\nST_IDR          #  4 ;- Interrupt Disable Register\nST_IMR          #  4 ;- Interrupt Mask Register\nST_RTAR         #  4 ;- Real-time Alarm Register\nST_CRTR         #  4 ;- Current Real-time Register\n;- -------- ST_CR : (ST Offset: 0x0) System Timer Control Register -------- \nAT91C_ST_WDRST            EQU (0x1:SHL:0) ;- (ST) Watchdog Timer Restart\n;- -------- ST_PIMR : (ST Offset: 0x4) System Timer Period Interval Mode Register -------- \nAT91C_ST_PIV              EQU (0xFFFF:SHL:0) ;- (ST) Watchdog Timer Restart\n;- -------- ST_WDMR : (ST Offset: 0x8) System Timer Watchdog Mode Register -------- \nAT91C_ST_WDV              EQU (0xFFFF:SHL:0) ;- (ST) Watchdog Timer Restart\nAT91C_ST_RSTEN            EQU (0x1:SHL:16) ;- (ST) Reset Enable\nAT91C_ST_EXTEN            EQU (0x1:SHL:17) ;- (ST) External Signal Assertion Enable\n;- -------- ST_RTMR : (ST Offset: 0xc) System Timer Real-time Mode Register -------- \nAT91C_ST_RTPRES           EQU (0xFFFF:SHL:0) ;- (ST) Real-time Timer Prescaler Value\n;- -------- ST_SR : (ST Offset: 0x10) System Timer Status Register -------- \nAT91C_ST_PITS             EQU (0x1:SHL:0) ;- (ST) Period Interval Timer Interrupt\nAT91C_ST_WDOVF            EQU (0x1:SHL:1) ;- (ST) Watchdog Overflow\nAT91C_ST_RTTINC           EQU (0x1:SHL:2) ;- (ST) Real-time Timer Increment\nAT91C_ST_ALMS             EQU (0x1:SHL:3) ;- (ST) Alarm Status\n;- -------- ST_IER : (ST Offset: 0x14) System Timer Interrupt Enable Register -------- \n;- -------- ST_IDR : (ST Offset: 0x18) System Timer Interrupt Disable Register -------- \n;- -------- ST_IMR : (ST Offset: 0x1c) System Timer Interrupt Mask Register -------- \n;- -------- ST_RTAR : (ST Offset: 0x20) System Timer Real-time Alarm Register -------- \nAT91C_ST_ALMV             EQU (0xFFFFF:SHL:0) ;- (ST) Alarm Value Value\n;- -------- ST_CRTR : (ST Offset: 0x24) System Timer Current Real-time Register -------- \nAT91C_ST_CRTV             EQU (0xFFFFF:SHL:0) ;- (ST) Current Real-time Value\n\n;- *****************************************************************************\n;-              SOFTWARE API DEFINITION  FOR Power Management Controler\n;- *****************************************************************************\n                ^ 0 ;- AT91S_PMC\nPMC_SCER        #  4 ;- System Clock Enable Register\nPMC_SCDR        #  4 ;- System Clock Disable Register\nPMC_SCSR        #  4 ;- System Clock Status Register\n                #  4 ;- Reserved\nPMC_PCER        #  4 ;- Peripheral Clock Enable Register\nPMC_PCDR        #  4 ;- Peripheral Clock Disable Register\nPMC_PCSR        #  4 ;- Peripheral Clock Status Register\n                # 20 ;- Reserved\nPMC_MCKR        #  4 ;- Master Clock Register\n                # 12 ;- Reserved\nPMC_PCKR        # 32 ;- Programmable Clock Register\nPMC_IER         #  4 ;- Interrupt Enable Register\nPMC_IDR         #  4 ;- Interrupt Disable Register\nPMC_SR          #  4 ;- Status Register\nPMC_IMR         #  4 ;- Interrupt Mask Register\n;- -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- \nAT91C_PMC_PCK             EQU (0x1:SHL:0) ;- (PMC) Processor Clock\nAT91C_PMC_UDP             EQU (0x1:SHL:1) ;- (PMC) USB Device Port Clock\nAT91C_PMC_MCKUDP          EQU (0x1:SHL:2) ;- (PMC) USB Device Port Master Clock Automatic Disable on Suspend\nAT91C_PMC_UHP             EQU (0x1:SHL:4) ;- (PMC) USB Host Port Clock\nAT91C_PMC_PCK0            EQU (0x1:SHL:8) ;- (PMC) Programmable Clock Output\nAT91C_PMC_PCK1            EQU (0x1:SHL:9) ;- (PMC) Programmable Clock Output\nAT91C_PMC_PCK2            EQU (0x1:SHL:10) ;- (PMC) Programmable Clock Output\nAT91C_PMC_PCK3            EQU (0x1:SHL:11) ;- (PMC) Programmable Clock Output\nAT91C_PMC_PCK4            EQU (0x1:SHL:12) ;- (PMC) Programmable Clock Output\nAT91C_PMC_PCK5            EQU (0x1:SHL:13) ;- (PMC) Programmable Clock Output\nAT91C_PMC_PCK6            EQU (0x1:SHL:14) ;- (PMC) Programmable Clock Output\nAT91C_PMC_PCK7            EQU (0x1:SHL:15) ;- (PMC) Programmable Clock Output\n;- -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- \n;- -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- \n;- -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- \nAT91C_PMC_CSS             EQU (0x3:SHL:0) ;- (PMC) Programmable Clock Selection\nAT91C_PMC_CSS_SLOW_CLK    EQU (0x0) ;- (PMC) Slow Clock is selected\nAT91C_PMC_CSS_MAIN_CLK    EQU (0x1) ;- (PMC) Main Clock is selected\nAT91C_PMC_CSS_PLLA_CLK    EQU (0x2) ;- (PMC) Clock from PLL A is selected\nAT91C_PMC_CSS_PLLB_CLK    EQU (0x3) ;- (PMC) Clock from PLL B is selected\nAT91C_PMC_PRES            EQU (0x7:SHL:2) ;- (PMC) Programmable Clock Prescaler\nAT91C_PMC_PRES_CLK        EQU (0x0:SHL:2) ;- (PMC) Selected clock\nAT91C_PMC_PRES_CLK_2      EQU (0x1:SHL:2) ;- (PMC) Selected clock divided by 2\nAT91C_PMC_PRES_CLK_4      EQU (0x2:SHL:2) ;- (PMC) Selected clock divided by 4\nAT91C_PMC_PRES_CLK_8      EQU (0x3:SHL:2) ;- (PMC) Selected clock divided by 8\nAT91C_PMC_PRES_CLK_16     EQU (0x4:SHL:2) ;- (PMC) Selected clock divided by 16\nAT91C_PMC_PRES_CLK_32     EQU (0x5:SHL:2) ;- (PMC) Selected clock divided by 32\nAT91C_PMC_PRES_CLK_64     EQU (0x6:SHL:2) ;- (PMC) Selected clock divided by 64\nAT91C_PMC_MDIV            EQU (0x3:SHL:8) ;- (PMC) Master Clock Division\nAT91C_PMC_MDIV_1          EQU (0x0:SHL:8) ;- (PMC) The master clock and the processor clock are the same\nAT91C_PMC_MDIV_2          EQU (0x1:SHL:8) ;- (PMC) The processor clock is twice as fast as the master clock\nAT91C_PMC_MDIV_3          EQU (0x2:SHL:8) ;- (PMC) The processor clock is three times faster than the master clock\nAT91C_PMC_MDIV_4          EQU (0x3:SHL:8) ;- (PMC) The processor clock is four times faster than the master clock\n;- -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- \n;- -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- \nAT91C_PMC_MOSCS           EQU (0x1:SHL:0) ;- (PMC) MOSC Status/Enable/Disable/Mask\nAT91C_PMC_LOCKA           EQU (0x1:SHL:1) ;- (PMC) PLL A Status/Enable/Disable/Mask\nAT91C_PMC_LOCKB           EQU (0x1:SHL:2) ;- (PMC) PLL B Status/Enable/Disable/Mask\nAT91C_PMC_MCKRDY          EQU (0x1:SHL:3) ;- (PMC) MCK_RDY Status/Enable/Disable/Mask\nAT91C_PMC_PCK0RDY         EQU (0x1:SHL:8) ;- (PMC) PCK0_RDY Status/Enable/Disable/Mask\nAT91C_PMC_PCK1RDY         EQU (0x1:SHL:9) ;- (PMC) PCK1_RDY Status/Enable/Disable/Mask\nAT91C_PMC_PCK2RDY         EQU (0x1:SHL:10) ;- (PMC) PCK2_RDY Status/Enable/Disable/Mask\nAT91C_PMC_PCK3RDY         EQU (0x1:SHL:11) ;- (PMC) PCK3_RDY Status/Enable/Disable/Mask\nAT91C_PMC_PCK4RDY         EQU (0x1:SHL:12) ;- (PMC) PCK4_RDY Status/Enable/Disable/Mask\nAT91C_PMC_PCK5RDY         EQU (0x1:SHL:13) ;- (PMC) PCK5_RDY Status/Enable/Disable/Mask\nAT91C_PMC_PCK6RDY         EQU (0x1:SHL:14) ;- (PMC) PCK6_RDY Status/Enable/Disable/Mask\nAT91C_PMC_PCK7RDY         EQU (0x1:SHL:15) ;- (PMC) PCK7_RDY Status/Enable/Disable/Mask\n;- -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- \n;- -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- \n;- -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- \n\n;- *****************************************************************************\n;-              SOFTWARE API DEFINITION  FOR Clock Generator Controler\n;- *****************************************************************************\n                ^ 0 ;- AT91S_CKGR\nCKGR_MOR        #  4 ;- Main Oscillator Register\nCKGR_MCFR       #  4 ;- Main Clock  Frequency Register\nCKGR_PLLAR      #  4 ;- PLL A Register\nCKGR_PLLBR      #  4 ;- PLL B Register\n;- -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- \nAT91C_CKGR_MOSCEN         EQU (0x1:SHL:0) ;- (CKGR) Main Oscillator Enable\nAT91C_CKGR_OSCTEST        EQU (0x1:SHL:1) ;- (CKGR) Oscillator Test\nAT91C_CKGR_OSCOUNT        EQU (0xFF:SHL:8) ;- (CKGR) Main Oscillator Start-up Time\n;- -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- \nAT91C_CKGR_MAINF          EQU (0xFFFF:SHL:0) ;- (CKGR) Main Clock Frequency\nAT91C_CKGR_MAINRDY        EQU (0x1:SHL:16) ;- (CKGR) Main Clock Ready\n;- -------- CKGR_PLLAR : (CKGR Offset: 0x8) PLL A Register -------- \nAT91C_CKGR_DIVA           EQU (0xFF:SHL:0) ;- (CKGR) Divider Selected\nAT91C_CKGR_DIVA_0         EQU (0x0) ;- (CKGR) Divider output is 0\nAT91C_CKGR_DIVA_BYPASS    EQU (0x1) ;- (CKGR) Divider is bypassed\nAT91C_CKGR_PLLACOUNT      EQU (0x3F:SHL:8) ;- (CKGR) PLL A Counter\nAT91C_CKGR_OUTA           EQU (0x3:SHL:14) ;- (CKGR) PLL A Output Frequency Range\nAT91C_CKGR_OUTA_0         EQU (0x0:SHL:14) ;- (CKGR) Please refer to the PLLA datasheet\nAT91C_CKGR_OUTA_1         EQU (0x1:SHL:14) ;- (CKGR) Please refer to the PLLA datasheet\nAT91C_CKGR_OUTA_2         EQU (0x2:SHL:14) ;- (CKGR) Please refer to the PLLA datasheet\nAT91C_CKGR_OUTA_3         EQU (0x3:SHL:14) ;- (CKGR) Please refer to the PLLA datasheet\nAT91C_CKGR_MULA           EQU (0x7FF:SHL:16) ;- (CKGR) PLL A Multiplier\nAT91C_CKGR_SRCA           EQU (0x1:SHL:29) ;- (CKGR) PLL A Source\n;- -------- CKGR_PLLBR : (CKGR Offset: 0xc) PLL B Register -------- \nAT91C_CKGR_DIVB           EQU (0xFF:SHL:0) ;- (CKGR) Divider Selected\nAT91C_CKGR_DIVB_0         EQU (0x0) ;- (CKGR) Divider output is 0\nAT91C_CKGR_DIVB_BYPASS    EQU (0x1) ;- (CKGR) Divider is bypassed\nAT91C_CKGR_PLLBCOUNT      EQU (0x3F:SHL:8) ;- (CKGR) PLL B Counter\nAT91C_CKGR_OUTB           EQU (0x3:SHL:14) ;- (CKGR) PLL B Output Frequency Range\nAT91C_CKGR_OUTB_0         EQU (0x0:SHL:14) ;- (CKGR) Please refer to the PLLB datasheet\nAT91C_CKGR_OUTB_1         EQU (0x1:SHL:14) ;- (CKGR) Please refer to the PLLB datasheet\nAT91C_CKGR_OUTB_2         EQU (0x2:SHL:14) ;- (CKGR) Please refer to the PLLB datasheet\nAT91C_CKGR_OUTB_3         EQU (0x3:SHL:14) ;- (CKGR) Please refer to the PLLB datasheet\nAT91C_CKGR_MULB           EQU (0x7FF:SHL:16) ;- (CKGR) PLL B Multiplier\nAT91C_CKGR_USB_96M        EQU (0x1:SHL:28) ;- (CKGR) Divider for USB Ports\nAT91C_CKGR_USB_PLL        EQU (0x1:SHL:29) ;- (CKGR) PLL Use\n\n;- *****************************************************************************\n;-              SOFTWARE API DEFINITION  FOR Parallel Input Output Controler\n;- *****************************************************************************\n                ^ 0 ;- AT91S_PIO\nPIO_PER         #  4 ;- PIO Enable Register\nPIO_PDR         #  4 ;- PIO Disable Register\nPIO_PSR         #  4 ;- PIO Status Register\n                #  4 ;- Reserved\nPIO_OER         #  4 ;- Output Enable Register\nPIO_ODR         #  4 ;- Output Disable Registerr\nPIO_OSR         #  4 ;- Output Status Register\n                #  4 ;- Reserved\nPIO_IFER        #  4 ;- Input Filter Enable Register\nPIO_IFDR        #  4 ;- Input Filter Disable Register\nPIO_IFSR        #  4 ;- Input Filter Status Register\n                #  4 ;- Reserved\nPIO_SODR        #  4 ;- Set Output Data Register\nPIO_CODR        #  4 ;- Clear Output Data Register\nPIO_ODSR        #  4 ;- Output Data Status Register\nPIO_PDSR        #  4 ;- Pin Data Status Register\nPIO_IER         #  4 ;- Interrupt Enable Register\nPIO_IDR         #  4 ;- Interrupt Disable Register\nPIO_IMR         #  4 ;- Interrupt Mask Register\nPIO_ISR         #  4 ;- Interrupt Status Register\nPIO_MDER        #  4 ;- Multi-driver Enable Register\nPIO_MDDR        #  4 ;- Multi-driver Disable Register\nPIO_MDSR        #  4 ;- Multi-driver Status Register\n                #  4 ;- Reserved\nPIO_PPUDR       #  4 ;- Pull-up Disable Register\nPIO_PPUER       #  4 ;- Pull-up Enable Register\nPIO_PPUSR       #  4 ;- Pad Pull-up Status Register\n                #  4 ;- Reserved\nPIO_ASR         #  4 ;- Select A Register\nPIO_BSR         #  4 ;- Select B Register\nPIO_ABSR        #  4 ;- AB Select Status Register\n                # 36 ;- Reserved\nPIO_OWER        #  4 ;- Output Write Enable Register\nPIO_OWDR        #  4 ;- Output Write Disable Register\nPIO_OWSR        #  4 ;- Output Write Status Register\n\n;- *****************************************************************************\n;-              SOFTWARE API DEFINITION  FOR Debug Unit\n;- *****************************************************************************\n                ^ 0 ;- AT91S_DBGU\nDBGU_CR         #  4 ;- Control Register\nDBGU_MR         #  4 ;- Mode Register\nDBGU_IER        #  4 ;- Interrupt Enable Register\nDBGU_IDR        #  4 ;- Interrupt Disable Register\nDBGU_IMR        #  4 ;- Interrupt Mask Register\nDBGU_CSR        #  4 ;- Channel Status Register\nDBGU_RHR        #  4 ;- Receiver Holding Register\nDBGU_THR        #  4 ;- Transmitter Holding Register\nDBGU_BRGR       #  4 ;- Baud Rate Generator Register\n                # 28 ;- Reserved\nDBGU_C1R        #  4 ;- Chip ID1 Register\nDBGU_C2R        #  4 ;- Chip ID2 Register\nDBGU_FNTR       #  4 ;- Force NTRST Register\n                # 180 ;- Reserved\nDBGU_RPR        #  4 ;- Receive Pointer Register\nDBGU_RCR        #  4 ;- Receive Counter Register\nDBGU_TPR        #  4 ;- Transmit Pointer Register\nDBGU_TCR        #  4 ;- Transmit Counter Register\nDBGU_RNPR       #  4 ;- Receive Next Pointer Register\nDBGU_RNCR       #  4 ;- Receive Next Counter Register\nDBGU_TNPR       #  4 ;- Transmit Next Pointer Register\nDBGU_TNCR       #  4 ;- Transmit Next Counter Register\nDBGU_PTCR       #  4 ;- PDC Transfer Control Register\nDBGU_PTSR       #  4 ;- PDC Transfer Status Register\n;- -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- \nAT91C_US_RSTRX            EQU (0x1:SHL:2) ;- (DBGU) Reset Receiver\nAT91C_US_RSTTX            EQU (0x1:SHL:3) ;- (DBGU) Reset Transmitter\nAT91C_US_RXEN             EQU (0x1:SHL:4) ;- (DBGU) Receiver Enable\nAT91C_US_RXDIS            EQU (0x1:SHL:5) ;- (DBGU) Receiver Disable\nAT91C_US_TXEN             EQU (0x1:SHL:6) ;- (DBGU) Transmitter Enable\nAT91C_US_TXDIS            EQU (0x1:SHL:7) ;- (DBGU) Transmitter Disable\n;- -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- \nAT91C_US_PAR              EQU (0x7:SHL:9) ;- (DBGU) Parity type\nAT91C_US_PAR_EVEN         EQU (0x0:SHL:9) ;- (DBGU) Even Parity\nAT91C_US_PAR_ODD          EQU (0x1:SHL:9) ;- (DBGU) Odd Parity\nAT91C_US_PAR_SPACE        EQU (0x2:SHL:9) ;- (DBGU) Parity forced to 0 (Space)\nAT91C_US_PAR_MARK         EQU (0x3:SHL:9) ;- (DBGU) Parity forced to 1 (Mark)\nAT91C_US_PAR_NONE         EQU (0x4:SHL:9) ;- (DBGU) No Parity\nAT91C_US_PAR_MULTI_DROP   EQU (0x6:SHL:9) ;- (DBGU) Multi-drop mode\nAT91C_US_CHMODE           EQU (0x3:SHL:14) ;- (DBGU) Channel Mode\nAT91C_US_CHMODE_NORMAL    EQU (0x0:SHL:14) ;- (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.\nAT91C_US_CHMODE_AUTO      EQU (0x1:SHL:14) ;- (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.\nAT91C_US_CHMODE_LOCAL     EQU (0x2:SHL:14) ;- (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.\nAT91C_US_CHMODE_REMOTE    EQU (0x3:SHL:14) ;- (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.\n;- -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- \nAT91C_US_RXRDY            EQU (0x1:SHL:0) ;- (DBGU) RXRDY Interrupt\nAT91C_US_TXRDY            EQU (0x1:SHL:1) ;- (DBGU) TXRDY Interrupt\nAT91C_US_ENDRX            EQU (0x1:SHL:3) ;- (DBGU) End of Receive Transfer Interrupt\nAT91C_US_ENDTX            EQU (0x1:SHL:4) ;- (DBGU) End of Transmit Interrupt\nAT91C_US_OVRE             EQU (0x1:SHL:5) ;- (DBGU) Overrun Interrupt\nAT91C_US_FRAME            EQU (0x1:SHL:6) ;- (DBGU) Framing Error Interrupt\nAT91C_US_PARE             EQU (0x1:SHL:7) ;- (DBGU) Parity Error Interrupt\nAT91C_US_TXEMPTY          EQU (0x1:SHL:9) ;- (DBGU) TXEMPTY Interrupt\nAT91C_US_TXBUFE           EQU (0x1:SHL:11) ;- (DBGU) TXBUFE Interrupt\nAT91C_US_RXBUFF           EQU (0x1:SHL:12) ;- (DBGU) RXBUFF Interrupt\nAT91C_US_COMM_TX          EQU (0x1:SHL:30) ;- (DBGU) COMM_TX Interrupt\nAT91C_US_COMM_RX          EQU (0x1:SHL:31) ;- (DBGU) COMM_RX Interrupt\n;- -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- \n;- -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- \n;- -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- \n;- -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- \nAT91C_US_FORCE_NTRST      EQU (0x1:SHL:0) ;- (DBGU) Force NTRST in JTAG\n\n;- *****************************************************************************\n;-              SOFTWARE API DEFINITION  FOR Peripheral Data Controller\n;- *****************************************************************************\n                ^ 0 ;- AT91S_PDC\nPDC_RPR         #  4 ;- Receive Pointer Register\nPDC_RCR         #  4 ;- Receive Counter Register\nPDC_TPR         #  4 ;- Transmit Pointer Register\nPDC_TCR         #  4 ;- Transmit Counter Register\nPDC_RNPR        #  4 ;- Receive Next Pointer Register\nPDC_RNCR        #  4 ;- Receive Next Counter Register\nPDC_TNPR        #  4 ;- Transmit Next Pointer Register\nPDC_TNCR        #  4 ;- Transmit Next Counter Register\nPDC_PTCR        #  4 ;- PDC Transfer Control Register\nPDC_PTSR        #  4 ;- PDC Transfer Status Register\n;- -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- \nAT91C_PDC_RXTEN           EQU (0x1:SHL:0) ;- (PDC) Receiver Transfer Enable\nAT91C_PDC_RXTDIS          EQU (0x1:SHL:1) ;- (PDC) Receiver Transfer Disable\nAT91C_PDC_TXTEN           EQU (0x1:SHL:8) ;- (PDC) Transmitter Transfer Enable\nAT91C_PDC_TXTDIS          EQU (0x1:SHL:9) ;- (PDC) Transmitter Transfer Disable\n;- -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- \n\n;- *****************************************************************************\n;-              SOFTWARE API DEFINITION  FOR Advanced Interrupt Controller\n;- *****************************************************************************\n                ^ 0 ;- AT91S_AIC\nAIC_SMR         # 128 ;- Source Mode Register\nAIC_SVR         # 128 ;- Source Vector Register\nAIC_IVR         #  4 ;- IRQ Vector Register\nAIC_FVR         #  4 ;- FIQ Vector Register\nAIC_ISR         #  4 ;- Interrupt Status Register\nAIC_IPR         #  4 ;- Interrupt Pending Register\nAIC_IMR         #  4 ;- Interrupt Mask Register\nAIC_CISR        #  4 ;- Core Interrupt Status Register\n                #  8 ;- Reserved\nAIC_IECR        #  4 ;- Interrupt Enable Command Register\nAIC_IDCR        #  4 ;- Interrupt Disable Command Register\nAIC_ICCR        #  4 ;- Interrupt Clear Command Register\nAIC_ISCR        #  4 ;- Interrupt Set Command Register\nAIC_EOICR       #  4 ;- End of Interrupt Command Register\nAIC_SPU         #  4 ;- Spurious Vector Register\nAIC_DCR         #  4 ;- Debug Control Register (Protect)\n                #  4 ;- Reserved\nAIC_FFER        #  4 ;- Fast Forcing Enable Register\nAIC_FFDR        #  4 ;- Fast Forcing Disable Register\nAIC_FFSR        #  4 ;- Fast Forcing Status Register\n;- -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- \nAT91C_AIC_PRIOR           EQU (0x7:SHL:0) ;- (AIC) Priority Level\nAT91C_AIC_PRIOR_LOWEST    EQU (0x0) ;- (AIC) Lowest priority level\nAT91C_AIC_PRIOR_HIGHEST   EQU (0x7) ;- (AIC) Highest priority level\nAT91C_AIC_SRCTYPE         EQU (0x3:SHL:5) ;- (AIC) Interrupt Source Type\nAT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE EQU (0x0:SHL:5) ;- (AIC) Internal Sources Code Label Level Sensitive\nAT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED EQU (0x1:SHL:5) ;- (AIC) Internal Sources Code Label Edge triggered\nAT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL EQU (0x2:SHL:5) ;- (AIC) External Sources Code Label High-level Sensitive\nAT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE EQU (0x3:SHL:5) ;- (AIC) External Sources Code Label Positive Edge triggered\n;- -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- \nAT91C_AIC_NFIQ            EQU (0x1:SHL:0) ;- (AIC) NFIQ Status\nAT91C_AIC_NIRQ            EQU (0x1:SHL:1) ;- (AIC) NIRQ Status\n;- -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- \nAT91C_AIC_DCR_PROT        EQU (0x1:SHL:0) ;- (AIC) Protection Mode\nAT91C_AIC_DCR_GMSK        EQU (0x1:SHL:1) ;- (AIC) General Mask\n\n;- *****************************************************************************\n;-              SOFTWARE API DEFINITION  FOR Serial Parallel Interface\n;- *****************************************************************************\n                ^ 0 ;- AT91S_SPI\nSPI_CR          #  4 ;- Control Register\nSPI_MR          #  4 ;- Mode Register\nSPI_RDR         #  4 ;- Receive Data Register\nSPI_TDR         #  4 ;- Transmit Data Register\nSPI_SR          #  4 ;- Status Register\nSPI_IER         #  4 ;- Interrupt Enable Register\nSPI_IDR         #  4 ;- Interrupt Disable Register\nSPI_IMR         #  4 ;- Interrupt Mask Register\n                # 16 ;- Reserved\nSPI_CSR         # 16 ;- Chip Select Register\n                # 192 ;- Reserved\nSPI_RPR         #  4 ;- Receive Pointer Register\nSPI_RCR         #  4 ;- Receive Counter Register\nSPI_TPR         #  4 ;- Transmit Pointer Register\nSPI_TCR         #  4 ;- Transmit Counter Register\nSPI_RNPR        #  4 ;- Receive Next Pointer Register\nSPI_RNCR        #  4 ;- Receive Next Counter Register\nSPI_TNPR        #  4 ;- Transmit Next Pointer Register\nSPI_TNCR        #  4 ;- Transmit Next Counter Register\nSPI_PTCR        #  4 ;- PDC Transfer Control Register\nSPI_PTSR        #  4 ;- PDC Transfer Status Register\n;- -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- \nAT91C_SPI_SPIEN           EQU (0x1:SHL:0) ;- (SPI) SPI Enable\nAT91C_SPI_SPIDIS          EQU (0x1:SHL:1) ;- (SPI) SPI Disable\nAT91C_SPI_SWRST           EQU (0x1:SHL:7) ;- (SPI) SPI Software reset\n;- -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- \nAT91C_SPI_MSTR            EQU (0x1:SHL:0) ;- (SPI) Master/Slave Mode\nAT91C_SPI_PS              EQU (0x1:SHL:1) ;- (SPI) Peripheral Select\nAT91C_SPI_PS_FIXED        EQU (0x0:SHL:1) ;- (SPI) Fixed Peripheral Select\nAT91C_SPI_PS_VARIABLE     EQU (0x1:SHL:1) ;- (SPI) Variable Peripheral Select\nAT91C_SPI_PCSDEC          EQU (0x1:SHL:2) ;- (SPI) Chip Select Decode\nAT91C_SPI_DIV32           EQU (0x1:SHL:3) ;- (SPI) Clock Selection\nAT91C_SPI_MODFDIS         EQU (0x1:SHL:4) ;- (SPI) Mode Fault Detection\nAT91C_SPI_LLB             EQU (0x1:SHL:7) ;- (SPI) Clock Selection\nAT91C_SPI_PCS             EQU (0xF:SHL:16) ;- (SPI) Peripheral Chip Select\nAT91C_SPI_DLYBCS          EQU (0xFF:SHL:24) ;- (SPI) Delay Between Chip Selects\n;- -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- \nAT91C_SPI_RD              EQU (0xFFFF:SHL:0) ;- (SPI) Receive Data\nAT91C_SPI_RPCS            EQU (0xF:SHL:16) ;- (SPI) Peripheral Chip Select Status\n;- -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- \nAT91C_SPI_TD              EQU (0xFFFF:SHL:0) ;- (SPI) Transmit Data\nAT91C_SPI_TPCS            EQU (0xF:SHL:16) ;- (SPI) Peripheral Chip Select Status\n;- -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- \nAT91C_SPI_RDRF            EQU (0x1:SHL:0) ;- (SPI) Receive Data Register Full\nAT91C_SPI_TDRE            EQU (0x1:SHL:1) ;- (SPI) Transmit Data Register Empty\nAT91C_SPI_MODF            EQU (0x1:SHL:2) ;- (SPI) Mode Fault Error\nAT91C_SPI_OVRES           EQU (0x1:SHL:3) ;- (SPI) Overrun Error Status\nAT91C_SPI_SPENDRX         EQU (0x1:SHL:4) ;- (SPI) End of Receiver Transfer\nAT91C_SPI_SPENDTX         EQU (0x1:SHL:5) ;- (SPI) End of Receiver Transfer\nAT91C_SPI_RXBUFF          EQU (0x1:SHL:6) ;- (SPI) RXBUFF Interrupt\nAT91C_SPI_TXBUFE          EQU (0x1:SHL:7) ;- (SPI) TXBUFE Interrupt\nAT91C_SPI_SPIENS          EQU (0x1:SHL:16) ;- (SPI) Enable Status\n;- -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- \n;- -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- \n;- -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- \n;- -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- \nAT91C_SPI_CPOL            EQU (0x1:SHL:0) ;- (SPI) Clock Polarity\nAT91C_SPI_NCPHA           EQU (0x1:SHL:1) ;- (SPI) Clock Phase\nAT91C_SPI_BITS            EQU (0xF:SHL:4) ;- (SPI) Bits Per Transfer\nAT91C_SPI_BITS_8          EQU (0x0:SHL:4) ;- (SPI) 8 Bits Per transfer\nAT91C_SPI_BITS_9          EQU (0x1:SHL:4) ;- (SPI) 9 Bits Per transfer\nAT91C_SPI_BITS_10         EQU (0x2:SHL:4) ;- (SPI) 10 Bits Per transfer\nAT91C_SPI_BITS_11         EQU (0x3:SHL:4) ;- (SPI) 11 Bits Per transfer\nAT91C_SPI_BITS_12         EQU (0x4:SHL:4) ;- (SPI) 12 Bits Per transfer\nAT91C_SPI_BITS_13         EQU (0x5:SHL:4) ;- (SPI) 13 Bits Per transfer\nAT91C_SPI_BITS_14         EQU (0x6:SHL:4) ;- (SPI) 14 Bits Per transfer\nAT91C_SPI_BITS_15         EQU (0x7:SHL:4) ;- (SPI) 15 Bits Per transfer\nAT91C_SPI_BITS_16         EQU (0x8:SHL:4) ;- (SPI) 16 Bits Per transfer\nAT91C_SPI_SCBR            EQU (0xFF:SHL:8) ;- (SPI) Serial Clock Baud Rate\nAT91C_SPI_DLYBS           EQU (0xFF:SHL:16) ;- (SPI) Serial Clock Baud Rate\nAT91C_SPI_DLYBCT          EQU (0xFF:SHL:24) ;- (SPI) Delay Between Consecutive Transfers\n\n;- *****************************************************************************\n;-              SOFTWARE API DEFINITION  FOR Synchronous Serial Controller Interface\n;- *****************************************************************************\n                ^ 0 ;- AT91S_SSC\nSSC_CR          #  4 ;- Control Register\nSSC_CMR         #  4 ;- Clock Mode Register\n                #  8 ;- Reserved\nSSC_RCMR        #  4 ;- Receive Clock ModeRegister\nSSC_RFMR        #  4 ;- Receive Frame Mode Register\nSSC_TCMR        #  4 ;- Transmit Clock Mode Register\nSSC_TFMR        #  4 ;- Transmit Frame Mode Register\nSSC_RHR         #  4 ;- Receive Holding Register\nSSC_THR         #  4 ;- Transmit Holding Register\n                #  8 ;- Reserved\nSSC_RSHR        #  4 ;- Receive Sync Holding Register\nSSC_TSHR        #  4 ;- Transmit Sync Holding Register\nSSC_RC0R        #  4 ;- Receive Compare 0 Register\nSSC_RC1R        #  4 ;- Receive Compare 1 Register\nSSC_SR          #  4 ;- Status Register\nSSC_IER         #  4 ;- Interrupt Enable Register\nSSC_IDR         #  4 ;- Interrupt Disable Register\nSSC_IMR         #  4 ;- Interrupt Mask Register\n                # 176 ;- Reserved\nSSC_RPR         #  4 ;- Receive Pointer Register\nSSC_RCR         #  4 ;- Receive Counter Register\nSSC_TPR         #  4 ;- Transmit Pointer Register\nSSC_TCR         #  4 ;- Transmit Counter Register\nSSC_RNPR        #  4 ;- Receive Next Pointer Register\nSSC_RNCR        #  4 ;- Receive Next Counter Register\nSSC_TNPR        #  4 ;- Transmit Next Pointer Register\nSSC_TNCR        #  4 ;- Transmit Next Counter Register\nSSC_PTCR        #  4 ;- PDC Transfer Control Register\nSSC_PTSR        #  4 ;- PDC Transfer Status Register\n;- -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- \nAT91C_SSC_RXEN            EQU (0x1:SHL:0) ;- (SSC) Receive Enable\nAT91C_SSC_RXDIS           EQU (0x1:SHL:1) ;- (SSC) Receive Disable\nAT91C_SSC_TXEN            EQU (0x1:SHL:8) ;- (SSC) Transmit Enable\nAT91C_SSC_TXDIS           EQU (0x1:SHL:9) ;- (SSC) Transmit Disable\nAT91C_SSC_SWRST           EQU (0x1:SHL:15) ;- (SSC) Software Reset\n;- -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- \nAT91C_SSC_CKS             EQU (0x3:SHL:0) ;- (SSC) Receive/Transmit Clock Selection\nAT91C_SSC_CKS_DIV         EQU (0x0) ;- (SSC) Divided Clock\nAT91C_SSC_CKS_TK          EQU (0x1) ;- (SSC) TK Clock signal\nAT91C_SSC_CKS_RK          EQU (0x2) ;- (SSC) RK pin\nAT91C_SSC_CKO             EQU (0x7:SHL:2) ;- (SSC) Receive/Transmit Clock Output Mode Selection\nAT91C_SSC_CKO_NONE        EQU (0x0:SHL:2) ;- (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only\nAT91C_SSC_CKO_CONTINOUS   EQU (0x1:SHL:2) ;- (SSC) Continuous Receive/Transmit Clock RK pin: Output\nAT91C_SSC_CKO_DATA_TX     EQU (0x2:SHL:2) ;- (SSC) Receive/Transmit Clock only during data transfers RK pin: Output\nAT91C_SSC_CKI             EQU (0x1:SHL:5) ;- (SSC) Receive/Transmit Clock Inversion\nAT91C_SSC_CKG             EQU (0x3:SHL:6) ;- (SSC) Receive/Transmit Clock Gating Selection\nAT91C_SSC_CKG_NONE        EQU (0x0:SHL:6) ;- (SSC) Receive/Transmit Clock Gating: None, continuous clock\nAT91C_SSC_CKG_LOW         EQU (0x1:SHL:6) ;- (SSC) Receive/Transmit Clock enabled only if RF Low\nAT91C_SSC_CKG_HIGH        EQU (0x2:SHL:6) ;- (SSC) Receive/Transmit Clock enabled only if RF High\nAT91C_SSC_START           EQU (0xF:SHL:8) ;- (SSC) Receive/Transmit Start Selection\nAT91C_SSC_START_CONTINOUS EQU (0x0:SHL:8) ;- (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.\nAT91C_SSC_START_TX        EQU (0x1:SHL:8) ;- (SSC) Transmit/Receive start\nAT91C_SSC_START_LOW_RF    EQU (0x2:SHL:8) ;- (SSC) Detection of a low level on RF input\nAT91C_SSC_START_HIGH_RF   EQU (0x3:SHL:8) ;- (SSC) Detection of a high level on RF input\nAT91C_SSC_START_FALL_RF   EQU (0x4:SHL:8) ;- (SSC) Detection of a falling edge on RF input\nAT91C_SSC_START_RISE_RF   EQU (0x5:SHL:8) ;- (SSC) Detection of a rising edge on RF input\nAT91C_SSC_START_LEVEL_RF  EQU (0x6:SHL:8) ;- (SSC) Detection of any level change on RF input\nAT91C_SSC_START_EDGE_RF   EQU (0x7:SHL:8) ;- (SSC) Detection of any edge on RF input\nAT91C_SSC_START_0         EQU (0x8:SHL:8) ;- (SSC) Compare 0\nAT91C_SSC_STOP            EQU (0x1:SHL:12) ;- (SSC) Receive Stop Selection\nAT91C_SSC_STTOUT          EQU (0x1:SHL:15) ;- (SSC) Receive/Transmit Start Output Selection\nAT91C_SSC_STTDLY          EQU (0xFF:SHL:16) ;- (SSC) Receive/Transmit Start Delay\nAT91C_SSC_PERIOD          EQU (0xFF:SHL:24) ;- (SSC) Receive/Transmit Period Divider Selection\n;- -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- \nAT91C_SSC_DATLEN          EQU (0x1F:SHL:0) ;- (SSC) Data Length\nAT91C_SSC_LOOP            EQU (0x1:SHL:5) ;- (SSC) Loop Mode\nAT91C_SSC_MSBF            EQU (0x1:SHL:7) ;- (SSC) Most Significant Bit First\nAT91C_SSC_DATNB           EQU (0xF:SHL:8) ;- (SSC) Data Number per Frame\nAT91C_SSC_FSLEN           EQU (0xF:SHL:16) ;- (SSC) Receive/Transmit Frame Sync length\nAT91C_SSC_FSOS            EQU (0x7:SHL:20) ;- (SSC) Receive/Transmit Frame Sync Output Selection\nAT91C_SSC_FSOS_NONE       EQU (0x0:SHL:20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only\nAT91C_SSC_FSOS_NEGATIVE   EQU (0x1:SHL:20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse\nAT91C_SSC_FSOS_POSITIVE   EQU (0x2:SHL:20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse\nAT91C_SSC_FSOS_LOW        EQU (0x3:SHL:20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer\nAT91C_SSC_FSOS_HIGH       EQU (0x4:SHL:20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer\nAT91C_SSC_FSOS_TOGGLE     EQU (0x5:SHL:20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer\nAT91C_SSC_FSEDGE          EQU (0x1:SHL:24) ;- (SSC) Frame Sync Edge Detection\n;- -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- \n;- -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- \nAT91C_SSC_DATDEF          EQU (0x1:SHL:5) ;- (SSC) Data Default Value\nAT91C_SSC_FSDEN           EQU (0x1:SHL:23) ;- (SSC) Frame Sync Data Enable\n;- -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- \nAT91C_SSC_TXRDY           EQU (0x1:SHL:0) ;- (SSC) Transmit Ready\nAT91C_SSC_TXEMPTY         EQU (0x1:SHL:1) ;- (SSC) Transmit Empty\nAT91C_SSC_ENDTX           EQU (0x1:SHL:2) ;- (SSC) End Of Transmission\nAT91C_SSC_TXBUFE          EQU (0x1:SHL:3) ;- (SSC) Transmit Buffer Empty\nAT91C_SSC_RXRDY           EQU (0x1:SHL:4) ;- (SSC) Receive Ready\nAT91C_SSC_OVRUN           EQU (0x1:SHL:5) ;- (SSC) Receive Overrun\nAT91C_SSC_ENDRX           EQU (0x1:SHL:6) ;- (SSC) End of Reception\nAT91C_SSC_RXBUFF          EQU (0x1:SHL:7) ;- (SSC) Receive Buffer Full\nAT91C_SSC_CP0             EQU (0x1:SHL:8) ;- (SSC) Compare 0\nAT91C_SSC_CP1             EQU (0x1:SHL:9) ;- (SSC) Compare 1\nAT91C_SSC_TXSYN           EQU (0x1:SHL:10) ;- (SSC) Transmit Sync\nAT91C_SSC_RXSYN           EQU (0x1:SHL:11) ;- (SSC) Receive Sync\nAT91C_SSC_TXENA           EQU (0x1:SHL:16) ;- (SSC) Transmit Enable\nAT91C_SSC_RXENA           EQU (0x1:SHL:17) ;- (SSC) Receive Enable\n;- -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- \n;- -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- \n;- -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- \n\n;- *****************************************************************************\n;-              SOFTWARE API DEFINITION  FOR Usart\n;- *****************************************************************************\n                ^ 0 ;- AT91S_USART\nUS_CR           #  4 ;- Control Register\nUS_MR           #  4 ;- Mode Register\nUS_IER          #  4 ;- Interrupt Enable Register\nUS_IDR          #  4 ;- Interrupt Disable Register\nUS_IMR          #  4 ;- Interrupt Mask Register\nUS_CSR          #  4 ;- Channel Status Register\nUS_RHR          #  4 ;- Receiver Holding Register\nUS_THR          #  4 ;- Transmitter Holding Register\nUS_BRGR         #  4 ;- Baud Rate Generator Register\nUS_RTOR         #  4 ;- Receiver Time-out Register\nUS_TTGR         #  4 ;- Transmitter Time-guard Register\n                # 20 ;- Reserved\nUS_FIDI         #  4 ;- FI_DI_Ratio Register\nUS_NER          #  4 ;- Nb Errors Register\nUS_XXR          #  4 ;- XON_XOFF Register\nUS_IF           #  4 ;- IRDA_FILTER Register\n                # 176 ;- Reserved\nUS_RPR          #  4 ;- Receive Pointer Register\nUS_RCR          #  4 ;- Receive Counter Register\nUS_TPR          #  4 ;- Transmit Pointer Register\nUS_TCR          #  4 ;- Transmit Counter Register\nUS_RNPR         #  4 ;- Receive Next Pointer Register\nUS_RNCR         #  4 ;- Receive Next Counter Register\nUS_TNPR         #  4 ;- Transmit Next Pointer Register\nUS_TNCR         #  4 ;- Transmit Next Counter Register\nUS_PTCR         #  4 ;- PDC Transfer Control Register\nUS_PTSR         #  4 ;- PDC Transfer Status Register\n;- -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- \nAT91C_US_RSTSTA           EQU (0x1:SHL:8) ;- (USART) Reset Status Bits\nAT91C_US_STTBRK           EQU (0x1:SHL:9) ;- (USART) Start Break\nAT91C_US_STPBRK           EQU (0x1:SHL:10) ;- (USART) Stop Break\nAT91C_US_STTTO            EQU (0x1:SHL:11) ;- (USART) Start Time-out\nAT91C_US_SENDA            EQU (0x1:SHL:12) ;- (USART) Send Address\nAT91C_US_RSTIT            EQU (0x1:SHL:13) ;- (USART) Reset Iterations\nAT91C_US_RSTNACK          EQU (0x1:SHL:14) ;- (USART) Reset Non Acknowledge\nAT91C_US_RETTO            EQU (0x1:SHL:15) ;- (USART) Rearm Time-out\nAT91C_US_DTREN            EQU (0x1:SHL:16) ;- (USART) Data Terminal ready Enable\nAT91C_US_DTRDIS           EQU (0x1:SHL:17) ;- (USART) Data Terminal ready Disable\nAT91C_US_RTSEN            EQU (0x1:SHL:18) ;- (USART) Request to Send enable\nAT91C_US_RTSDIS           EQU (0x1:SHL:19) ;- (USART) Request to Send Disable\n;- -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- \nAT91C_US_USMODE           EQU (0xF:SHL:0) ;- (USART) Usart mode\nAT91C_US_USMODE_NORMAL    EQU (0x0) ;- (USART) Normal\nAT91C_US_USMODE_RS485     EQU (0x1) ;- (USART) RS485\nAT91C_US_USMODE_HWHSH     EQU (0x2) ;- (USART) Hardware Handshaking\nAT91C_US_USMODE_MODEM     EQU (0x3) ;- (USART) Modem\nAT91C_US_USMODE_ISO7816_0 EQU (0x4) ;- (USART) ISO7816 protocol: T = 0\nAT91C_US_USMODE_ISO7816_1 EQU (0x6) ;- (USART) ISO7816 protocol: T = 1\nAT91C_US_USMODE_IRDA      EQU (0x8) ;- (USART) IrDA\nAT91C_US_USMODE_SWHSH     EQU (0xC) ;- (USART) Software Handshaking\nAT91C_US_CLKS             EQU (0x3:SHL:4) ;- (USART) Clock Selection (Baud Rate generator Input Clock\nAT91C_US_CLKS_CLOCK       EQU (0x0:SHL:4) ;- (USART) Clock\nAT91C_US_CLKS_FDIV1       EQU (0x1:SHL:4) ;- (USART) fdiv1\nAT91C_US_CLKS_SLOW        EQU (0x2:SHL:4) ;- (USART) slow_clock (ARM)\nAT91C_US_CLKS_EXT         EQU (0x3:SHL:4) ;- (USART) External (SCK)\nAT91C_US_CHRL             EQU (0x3:SHL:6) ;- (USART) Clock Selection (Baud Rate generator Input Clock\nAT91C_US_CHRL_5_BITS      EQU (0x0:SHL:6) ;- (USART) Character Length: 5 bits\nAT91C_US_CHRL_6_BITS      EQU (0x1:SHL:6) ;- (USART) Character Length: 6 bits\nAT91C_US_CHRL_7_BITS      EQU (0x2:SHL:6) ;- (USART) Character Length: 7 bits\nAT91C_US_CHRL_8_BITS      EQU (0x3:SHL:6) ;- (USART) Character Length: 8 bits\nAT91C_US_SYNC             EQU (0x1:SHL:8) ;- (USART) Synchronous Mode Select\nAT91C_US_NBSTOP           EQU (0x3:SHL:12) ;- (USART) Number of Stop bits\nAT91C_US_NBSTOP_1_BIT     EQU (0x0:SHL:12) ;- (USART) 1 stop bit\nAT91C_US_NBSTOP_15_BIT    EQU (0x1:SHL:12) ;- (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits\nAT91C_US_NBSTOP_2_BIT     EQU (0x2:SHL:12) ;- (USART) 2 stop bits\nAT91C_US_MSBF             EQU (0x1:SHL:16) ;- (USART) Bit Order\nAT91C_US_MODE9            EQU (0x1:SHL:17) ;- (USART) 9-bit Character length\nAT91C_US_CKLO             EQU (0x1:SHL:18) ;- (USART) Clock Output Select\nAT91C_US_OVER             EQU (0x1:SHL:19) ;- (USART) Over Sampling Mode\nAT91C_US_INACK            EQU (0x1:SHL:20) ;- (USART) Inhibit Non Acknowledge\nAT91C_US_DSNACK           EQU (0x1:SHL:21) ;- (USART) Disable Successive NACK\nAT91C_US_MAX_ITER         EQU (0x1:SHL:24) ;- (USART) Number of Repetitions\nAT91C_US_FILTER           EQU (0x1:SHL:28) ;- (USART) Receive Line Filter\n;- -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- \nAT91C_US_RXBRK            EQU (0x1:SHL:2) ;- (USART) Break Received/End of Break\nAT91C_US_TIMEOUT          EQU (0x1:SHL:8) ;- (USART) Receiver Time-out\nAT91C_US_ITERATION        EQU (0x1:SHL:10) ;- (USART) Max number of Repetitions Reached\nAT91C_US_NACK             EQU (0x1:SHL:13) ;- (USART) Non Acknowledge\nAT91C_US_RIIC             EQU (0x1:SHL:16) ;- (USART) Ring INdicator Input Change Flag\nAT91C_US_DSRIC            EQU (0x1:SHL:17) ;- (USART) Data Set Ready Input Change Flag\nAT91C_US_DCDIC            EQU (0x1:SHL:18) ;- (USART) Data Carrier Flag\nAT91C_US_CTSIC            EQU (0x1:SHL:19) ;- (USART) Clear To Send Input Change Flag\n;- -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- \n;- -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- \n;- -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- \nAT91C_US_RI               EQU (0x1:SHL:20) ;- (USART) Image of RI Input\nAT91C_US_DSR              EQU (0x1:SHL:21) ;- (USART) Image of DSR Input\nAT91C_US_DCD              EQU (0x1:SHL:22) ;- (USART) Image of DCD Input\nAT91C_US_CTS              EQU (0x1:SHL:23) ;- (USART) Image of CTS Input\n\n;- *****************************************************************************\n;-              SOFTWARE API DEFINITION  FOR Two-wire Interface\n;- *****************************************************************************\n                ^ 0 ;- AT91S_TWI\nTWI_CR          #  4 ;- Control Register\nTWI_MMR         #  4 ;- Master Mode Register\nTWI_SMR         #  4 ;- Slave Mode Register\nTWI_IADR        #  4 ;- Internal Address Register\nTWI_CWGR        #  4 ;- Clock Waveform Generator Register\n                # 12 ;- Reserved\nTWI_SR          #  4 ;- Status Register\nTWI_IER         #  4 ;- Interrupt Enable Register\nTWI_IDR         #  4 ;- Interrupt Disable Register\nTWI_IMR         #  4 ;- Interrupt Mask Register\nTWI_RHR         #  4 ;- Receive Holding Register\nTWI_THR         #  4 ;- Transmit Holding Register\n;- -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- \nAT91C_TWI_START           EQU (0x1:SHL:0) ;- (TWI) Send a START Condition\nAT91C_TWI_STOP            EQU (0x1:SHL:1) ;- (TWI) Send a STOP Condition\nAT91C_TWI_MSEN            EQU (0x1:SHL:2) ;- (TWI) TWI Master Transfer Enabled\nAT91C_TWI_MSDIS           EQU (0x1:SHL:3) ;- (TWI) TWI Master Transfer Disabled\nAT91C_TWI_SVEN            EQU (0x1:SHL:4) ;- (TWI) TWI Slave Transfer Enabled\nAT91C_TWI_SVDIS           EQU (0x1:SHL:5) ;- (TWI) TWI Slave Transfer Disabled\nAT91C_TWI_SWRST           EQU (0x1:SHL:7) ;- (TWI) Software Reset\n;- -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- \nAT91C_TWI_IADRSZ          EQU (0x3:SHL:8) ;- (TWI) Internal Device Address Size\nAT91C_TWI_IADRSZ_NO       EQU (0x0:SHL:8) ;- (TWI) No internal device address\nAT91C_TWI_IADRSZ_1_BYTE   EQU (0x1:SHL:8) ;- (TWI) One-byte internal device address\nAT91C_TWI_IADRSZ_2_BYTE   EQU (0x2:SHL:8) ;- (TWI) Two-byte internal device address\nAT91C_TWI_IADRSZ_3_BYTE   EQU (0x3:SHL:8) ;- (TWI) Three-byte internal device address\nAT91C_TWI_MREAD           EQU (0x1:SHL:12) ;- (TWI) Master Read Direction\nAT91C_TWI_DADR            EQU (0x7F:SHL:16) ;- (TWI) Device Address\n;- -------- TWI_SMR : (TWI Offset: 0x8) TWI Slave Mode Register -------- \nAT91C_TWI_SADR            EQU (0x7F:SHL:16) ;- (TWI) Slave Device Address\n;- -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- \nAT91C_TWI_CLDIV           EQU (0xFF:SHL:0) ;- (TWI) Clock Low Divider\nAT91C_TWI_CHDIV           EQU (0xFF:SHL:8) ;- (TWI) Clock High Divider\nAT91C_TWI_CKDIV           EQU (0x7:SHL:16) ;- (TWI) Clock Divider\n;- -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- \nAT91C_TWI_TXCOMP          EQU (0x1:SHL:0) ;- (TWI) Transmission Completed\nAT91C_TWI_RXRDY           EQU (0x1:SHL:1) ;- (TWI) Receive holding register ReaDY\nAT91C_TWI_TXRDY           EQU (0x1:SHL:2) ;- (TWI) Transmit holding register ReaDY\nAT91C_TWI_SVREAD          EQU (0x1:SHL:3) ;- (TWI) Slave Read\nAT91C_TWI_SVACC           EQU (0x1:SHL:4) ;- (TWI) Slave Access\nAT91C_TWI_GCACC           EQU (0x1:SHL:5) ;- (TWI) General Call Access\nAT91C_TWI_OVRE            EQU (0x1:SHL:6) ;- (TWI) Overrun Error\nAT91C_TWI_UNRE            EQU (0x1:SHL:7) ;- (TWI) Underrun Error\nAT91C_TWI_NACK            EQU (0x1:SHL:8) ;- (TWI) Not Acknowledged\nAT91C_TWI_ARBLST          EQU (0x1:SHL:9) ;- (TWI) Arbitration Lost\n;- -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- \n;- -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- \n;- -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- \n\n;- *****************************************************************************\n;-              SOFTWARE API DEFINITION  FOR Multimedia Card Interface\n;- *****************************************************************************\n                ^ 0 ;- AT91S_MCI\nMCI_CR          #  4 ;- MCI Control Register\nMCI_MR          #  4 ;- MCI Mode Register\nMCI_DTOR        #  4 ;- MCI Data Timeout Register\nMCI_SDCR        #  4 ;- MCI SD Card Register\nMCI_ARGR        #  4 ;- MCI Argument Register\nMCI_CMDR        #  4 ;- MCI Command Register\n                #  8 ;- Reserved\nMCI_RSPR        # 16 ;- MCI Response Register\nMCI_RDR         #  4 ;- MCI Receive Data Register\nMCI_TDR         #  4 ;- MCI Transmit Data Register\n                #  8 ;- Reserved\nMCI_SR          #  4 ;- MCI Status Register\nMCI_IER         #  4 ;- MCI Interrupt Enable Register\nMCI_IDR         #  4 ;- MCI Interrupt Disable Register\nMCI_IMR         #  4 ;- MCI Interrupt Mask Register\n                # 176 ;- Reserved\nMCI_RPR         #  4 ;- Receive Pointer Register\nMCI_RCR         #  4 ;- Receive Counter Register\nMCI_TPR         #  4 ;- Transmit Pointer Register\nMCI_TCR         #  4 ;- Transmit Counter Register\nMCI_RNPR        #  4 ;- Receive Next Pointer Register\nMCI_RNCR        #  4 ;- Receive Next Counter Register\nMCI_TNPR        #  4 ;- Transmit Next Pointer Register\nMCI_TNCR        #  4 ;- Transmit Next Counter Register\nMCI_PTCR        #  4 ;- PDC Transfer Control Register\nMCI_PTSR        #  4 ;- PDC Transfer Status Register\n;- -------- MCI_CR : (MCI Offset: 0x0) MCI Control Register -------- \nAT91C_MCI_MCIEN           EQU (0x1:SHL:0) ;- (MCI) Multimedia Interface Enable\nAT91C_MCI_MCIDIS          EQU (0x1:SHL:1) ;- (MCI) Multimedia Interface Disable\nAT91C_MCI_PWSEN           EQU (0x1:SHL:2) ;- (MCI) Power Save Mode Enable\nAT91C_MCI_PWSDIS          EQU (0x1:SHL:3) ;- (MCI) Power Save Mode Disable\n;- -------- MCI_MR : (MCI Offset: 0x4) MCI Mode Register -------- \nAT91C_MCI_CLKDIV          EQU (0x1:SHL:0) ;- (MCI) Clock Divider\nAT91C_MCI_PWSDIV          EQU (0x1:SHL:8) ;- (MCI) Power Saving Divider\nAT91C_MCI_PDCPADV         EQU (0x1:SHL:14) ;- (MCI) PDC Padding Value\nAT91C_MCI_PDCMODE         EQU (0x1:SHL:15) ;- (MCI) PDC Oriented Mode\nAT91C_MCI_BLKLEN          EQU (0x1:SHL:18) ;- (MCI) Data Block Length\n;- -------- MCI_DTOR : (MCI Offset: 0x8) MCI Data Timeout Register -------- \nAT91C_MCI_DTOCYC          EQU (0x1:SHL:0) ;- (MCI) Data Timeout Cycle Number\nAT91C_MCI_DTOMUL          EQU (0x7:SHL:4) ;- (MCI) Data Timeout Multiplier\nAT91C_MCI_DTOMUL_1        EQU (0x0:SHL:4) ;- (MCI) DTOCYC x 1\nAT91C_MCI_DTOMUL_16       EQU (0x1:SHL:4) ;- (MCI) DTOCYC x 16\nAT91C_MCI_DTOMUL_128      EQU (0x2:SHL:4) ;- (MCI) DTOCYC x 128\nAT91C_MCI_DTOMUL_256      EQU (0x3:SHL:4) ;- (MCI) DTOCYC x 256\nAT91C_MCI_DTOMUL_1024     EQU (0x4:SHL:4) ;- (MCI) DTOCYC x 1024\nAT91C_MCI_DTOMUL_4096     EQU (0x5:SHL:4) ;- (MCI) DTOCYC x 4096\nAT91C_MCI_DTOMUL_65536    EQU (0x6:SHL:4) ;- (MCI) DTOCYC x 65536\nAT91C_MCI_DTOMUL_1048576  EQU (0x7:SHL:4) ;- (MCI) DTOCYC x 1048576\n;- -------- MCI_SDCR : (MCI Offset: 0xc) MCI SD Card Register -------- \nAT91C_MCI_SCDSEL          EQU (0x1:SHL:0) ;- (MCI) SD Card Selector\nAT91C_MCI_SCDBUS          EQU (0x1:SHL:7) ;- (MCI) SD Card Bus Width\n;- -------- MCI_CMDR : (MCI Offset: 0x14) MCI Command Register -------- \nAT91C_MCI_CMDNB           EQU (0x1F:SHL:0) ;- (MCI) Command Number\nAT91C_MCI_RSPTYP          EQU (0x3:SHL:6) ;- (MCI) Response Type\nAT91C_MCI_RSPTYP_NO       EQU (0x0:SHL:6) ;- (MCI) No response\nAT91C_MCI_RSPTYP_48       EQU (0x1:SHL:6) ;- (MCI) 48-bit response\nAT91C_MCI_RSPTYP_136      EQU (0x2:SHL:6) ;- (MCI) 136-bit response\nAT91C_MCI_SPCMD           EQU (0x7:SHL:8) ;- (MCI) Special CMD\nAT91C_MCI_SPCMD_NONE      EQU (0x0:SHL:8) ;- (MCI) Not a special CMD\nAT91C_MCI_SPCMD_INIT      EQU (0x1:SHL:8) ;- (MCI) Initialization CMD\nAT91C_MCI_SPCMD_SYNC      EQU (0x2:SHL:8) ;- (MCI) Synchronized CMD\nAT91C_MCI_SPCMD_IT_CMD    EQU (0x4:SHL:8) ;- (MCI) Interrupt command\nAT91C_MCI_SPCMD_IT_REP    EQU (0x5:SHL:8) ;- (MCI) Interrupt response\nAT91C_MCI_OPDCMD          EQU (0x1:SHL:11) ;- (MCI) Open Drain Command\nAT91C_MCI_MAXLAT          EQU (0x1:SHL:12) ;- (MCI) Maximum Latency for Command to respond\nAT91C_MCI_TRCMD           EQU (0x3:SHL:16) ;- (MCI) Transfer CMD\nAT91C_MCI_TRCMD_NO        EQU (0x0:SHL:16) ;- (MCI) No transfer\nAT91C_MCI_TRCMD_START     EQU (0x1:SHL:16) ;- (MCI) Start transfer\nAT91C_MCI_TRCMD_STOP      EQU (0x2:SHL:16) ;- (MCI) Stop transfer\nAT91C_MCI_TRDIR           EQU (0x1:SHL:18) ;- (MCI) Transfer Direction\nAT91C_MCI_TRTYP           EQU (0x3:SHL:19) ;- (MCI) Transfer Type\nAT91C_MCI_TRTYP_BLOCK     EQU (0x0:SHL:19) ;- (MCI) Block Transfer type\nAT91C_MCI_TRTYP_MULTIPLE  EQU (0x1:SHL:19) ;- (MCI) Multiple Block transfer type\nAT91C_MCI_TRTYP_STREAM    EQU (0x2:SHL:19) ;- (MCI) Stream transfer type\n;- -------- MCI_SR : (MCI Offset: 0x40) MCI Status Register -------- \nAT91C_MCI_CMDRDY          EQU (0x1:SHL:0) ;- (MCI) Command Ready flag\nAT91C_MCI_RXRDY           EQU (0x1:SHL:1) ;- (MCI) RX Ready flag\nAT91C_MCI_TXRDY           EQU (0x1:SHL:2) ;- (MCI) TX Ready flag\nAT91C_MCI_BLKE            EQU (0x1:SHL:3) ;- (MCI) Data Block Transfer Ended flag\nAT91C_MCI_DTIP            EQU (0x1:SHL:4) ;- (MCI) Data Transfer in Progress flag\nAT91C_MCI_NOTBUSY         EQU (0x1:SHL:5) ;- (MCI) Data Line Not Busy flag\nAT91C_MCI_ENDRX           EQU (0x1:SHL:6) ;- (MCI) End of RX Buffer flag\nAT91C_MCI_ENDTX           EQU (0x1:SHL:7) ;- (MCI) End of TX Buffer flag\nAT91C_MCI_RXBUFF          EQU (0x1:SHL:14) ;- (MCI) RX Buffer Full flag\nAT91C_MCI_TXBUFE          EQU (0x1:SHL:15) ;- (MCI) TX Buffer Empty flag\nAT91C_MCI_RINDE           EQU (0x1:SHL:16) ;- (MCI) Response Index Error flag\nAT91C_MCI_RDIRE           EQU (0x1:SHL:17) ;- (MCI) Response Direction Error flag\nAT91C_MCI_RCRCE           EQU (0x1:SHL:18) ;- (MCI) Response CRC Error flag\nAT91C_MCI_RENDE           EQU (0x1:SHL:19) ;- (MCI) Response End Bit Error flag\nAT91C_MCI_RTOE            EQU (0x1:SHL:20) ;- (MCI) Response Time-out Error flag\nAT91C_MCI_DCRCE           EQU (0x1:SHL:21) ;- (MCI) data CRC Error flag\nAT91C_MCI_DTOE            EQU (0x1:SHL:22) ;- (MCI) Data timeout Error flag\nAT91C_MCI_OVRE            EQU (0x1:SHL:30) ;- (MCI) Overrun flag\nAT91C_MCI_UNRE            EQU (0x1:SHL:31) ;- (MCI) Underrun flag\n;- -------- MCI_IER : (MCI Offset: 0x44) MCI Interrupt Enable Register -------- \n;- -------- MCI_IDR : (MCI Offset: 0x48) MCI Interrupt Disable Register -------- \n;- -------- MCI_IMR : (MCI Offset: 0x4c) MCI Interrupt Mask Register -------- \n\n;- *****************************************************************************\n;-              SOFTWARE API DEFINITION  FOR USB Device Interface\n;- *****************************************************************************\n                ^ 0 ;- AT91S_UDP\nUDP_NUM         #  4 ;- Frame Number Register\nUDP_GLBSTATE    #  4 ;- Global State Register\nUDP_FADDR       #  4 ;- Function Address Register\n                #  4 ;- Reserved\nUDP_IER         #  4 ;- Interrupt Enable Register\nUDP_IDR         #  4 ;- Interrupt Disable Register\nUDP_IMR         #  4 ;- Interrupt Mask Register\nUDP_ISR         #  4 ;- Interrupt Status Register\nUDP_ICR         #  4 ;- Interrupt Clear Register\n                #  4 ;- Reserved\nUDP_RSTEP       #  4 ;- Reset Endpoint Register\n                #  4 ;- Reserved\nUDP_CSR         # 32 ;- Endpoint Control and Status Register\nUDP_FDR         # 32 ;- Endpoint FIFO Data Register\n;- -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- \nAT91C_UDP_FRM_NUM         EQU (0x7FF:SHL:0) ;- (UDP) Frame Number as Defined in the Packet Field Formats\nAT91C_UDP_FRM_ERR         EQU (0x1:SHL:16) ;- (UDP) Frame Error\nAT91C_UDP_FRM_OK          EQU (0x1:SHL:17) ;- (UDP) Frame OK\n;- -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- \nAT91C_UDP_FADDEN          EQU (0x1:SHL:0) ;- (UDP) Function Address Enable\nAT91C_UDP_CONFG           EQU (0x1:SHL:1) ;- (UDP) Configured\nAT91C_UDP_RMWUPE          EQU (0x1:SHL:2) ;- (UDP) Remote Wake Up Enable\nAT91C_UDP_RSMINPR         EQU (0x1:SHL:3) ;- (UDP) A Resume Has Been Sent to the Host\n;- -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- \nAT91C_UDP_FADD            EQU (0xFF:SHL:0) ;- (UDP) Function Address Value\nAT91C_UDP_FEN             EQU (0x1:SHL:8) ;- (UDP) Function Enable\n;- -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- \nAT91C_UDP_EPINT0          EQU (0x1:SHL:0) ;- (UDP) Endpoint 0 Interrupt\nAT91C_UDP_EPINT1          EQU (0x1:SHL:1) ;- (UDP) Endpoint 0 Interrupt\nAT91C_UDP_EPINT2          EQU (0x1:SHL:2) ;- (UDP) Endpoint 2 Interrupt\nAT91C_UDP_EPINT3          EQU (0x1:SHL:3) ;- (UDP) Endpoint 3 Interrupt\nAT91C_UDP_EPINT4          EQU (0x1:SHL:4) ;- (UDP) Endpoint 4 Interrupt\nAT91C_UDP_EPINT5          EQU (0x1:SHL:5) ;- (UDP) Endpoint 5 Interrupt\nAT91C_UDP_EPINT6          EQU (0x1:SHL:6) ;- (UDP) Endpoint 6 Interrupt\nAT91C_UDP_EPINT7          EQU (0x1:SHL:7) ;- (UDP) Endpoint 7 Interrupt\nAT91C_UDP_RXSUSP          EQU (0x1:SHL:8) ;- (UDP) USB Suspend Interrupt\nAT91C_UDP_RXRSM           EQU (0x1:SHL:9) ;- (UDP) USB Resume Interrupt\nAT91C_UDP_EXTRSM          EQU (0x1:SHL:10) ;- (UDP) USB External Resume Interrupt\nAT91C_UDP_SOFINT          EQU (0x1:SHL:11) ;- (UDP) USB Start Of frame Interrupt\nAT91C_UDP_WAKEUP          EQU (0x1:SHL:13) ;- (UDP) USB Resume Interrupt\n;- -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- \n;- -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- \n;- -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- \nAT91C_UDP_ENDBUSRES       EQU (0x1:SHL:12) ;- (UDP) USB End Of Bus Reset Interrupt\n;- -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- \n;- -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- \nAT91C_UDP_EP0             EQU (0x1:SHL:0) ;- (UDP) Reset Endpoint 0\nAT91C_UDP_EP1             EQU (0x1:SHL:1) ;- (UDP) Reset Endpoint 1\nAT91C_UDP_EP2             EQU (0x1:SHL:2) ;- (UDP) Reset Endpoint 2\nAT91C_UDP_EP3             EQU (0x1:SHL:3) ;- (UDP) Reset Endpoint 3\nAT91C_UDP_EP4             EQU (0x1:SHL:4) ;- (UDP) Reset Endpoint 4\nAT91C_UDP_EP5             EQU (0x1:SHL:5) ;- (UDP) Reset Endpoint 5\nAT91C_UDP_EP6             EQU (0x1:SHL:6) ;- (UDP) Reset Endpoint 6\nAT91C_UDP_EP7             EQU (0x1:SHL:7) ;- (UDP) Reset Endpoint 7\n;- -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- \nAT91C_UDP_TXCOMP          EQU (0x1:SHL:0) ;- (UDP) Generates an IN packet with data previously written in the DPR\nAT91C_UDP_RX_DATA_BK0     EQU (0x1:SHL:1) ;- (UDP) Receive Data Bank 0\nAT91C_UDP_RXSETUP         EQU (0x1:SHL:2) ;- (UDP) Sends STALL to the Host (Control endpoints)\nAT91C_UDP_ISOERROR        EQU (0x1:SHL:3) ;- (UDP) Isochronous error (Isochronous endpoints)\nAT91C_UDP_TXPKTRDY        EQU (0x1:SHL:4) ;- (UDP) Transmit Packet Ready\nAT91C_UDP_FORCESTALL      EQU (0x1:SHL:5) ;- (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).\nAT91C_UDP_RX_DATA_BK1     EQU (0x1:SHL:6) ;- (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).\nAT91C_UDP_DIR             EQU (0x1:SHL:7) ;- (UDP) Transfer Direction\nAT91C_UDP_EPTYPE          EQU (0x7:SHL:8) ;- (UDP) Endpoint type\nAT91C_UDP_EPTYPE_CTRL     EQU (0x0:SHL:8) ;- (UDP) Control\nAT91C_UDP_EPTYPE_ISO_OUT  EQU (0x1:SHL:8) ;- (UDP) Isochronous OUT\nAT91C_UDP_EPTYPE_BULK_OUT EQU (0x2:SHL:8) ;- (UDP) Bulk OUT\nAT91C_UDP_EPTYPE_INT_OUT  EQU (0x3:SHL:8) ;- (UDP) Interrupt OUT\nAT91C_UDP_EPTYPE_ISO_IN   EQU (0x5:SHL:8) ;- (UDP) Isochronous IN\nAT91C_UDP_EPTYPE_BULK_IN  EQU (0x6:SHL:8) ;- (UDP) Bulk IN\nAT91C_UDP_EPTYPE_INT_IN   EQU (0x7:SHL:8) ;- (UDP) Interrupt IN\nAT91C_UDP_DTGLE           EQU (0x1:SHL:11) ;- (UDP) Data Toggle\nAT91C_UDP_EPEDS           EQU (0x1:SHL:15) ;- (UDP) Endpoint Enable Disable\nAT91C_UDP_RXBYTECNT       EQU (0x7FF:SHL:16) ;- (UDP) Number Of Bytes Available in the FIFO\n\n;- *****************************************************************************\n;-              SOFTWARE API DEFINITION  FOR Timer Counter Channel Interface\n;- *****************************************************************************\n                ^ 0 ;- AT91S_TC\nTC_CCR          #  4 ;- Channel Control Register\nTC_CMR          #  4 ;- Channel Mode Register\n                #  8 ;- Reserved\nTC_CV           #  4 ;- Counter Value\nTC_RA           #  4 ;- Register A\nTC_RB           #  4 ;- Register B\nTC_RC           #  4 ;- Register C\nTC_SR           #  4 ;- Status Register\nTC_IER          #  4 ;- Interrupt Enable Register\nTC_IDR          #  4 ;- Interrupt Disable Register\nTC_IMR          #  4 ;- Interrupt Mask Register\n;- -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- \nAT91C_TC_CLKEN            EQU (0x1:SHL:0) ;- (TC) Counter Clock Enable Command\nAT91C_TC_CLKDIS           EQU (0x1:SHL:1) ;- (TC) Counter Clock Disable Command\nAT91C_TC_SWTRG            EQU (0x1:SHL:2) ;- (TC) Software Trigger Command\n;- -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- \nAT91C_TC_CPCSTOP          EQU (0x1:SHL:6) ;- (TC) Counter Clock Stopped with RC Compare\nAT91C_TC_CPCDIS           EQU (0x1:SHL:7) ;- (TC) Counter Clock Disable with RC Compare\nAT91C_TC_EEVTEDG          EQU (0x3:SHL:8) ;- (TC) External Event Edge Selection\nAT91C_TC_EEVTEDG_NONE     EQU (0x0:SHL:8) ;- (TC) Edge: None\nAT91C_TC_EEVTEDG_RISING   EQU (0x1:SHL:8) ;- (TC) Edge: rising edge\nAT91C_TC_EEVTEDG_FALLING  EQU (0x2:SHL:8) ;- (TC) Edge: falling edge\nAT91C_TC_EEVTEDG_BOTH     EQU (0x3:SHL:8) ;- (TC) Edge: each edge\nAT91C_TC_EEVT             EQU (0x3:SHL:10) ;- (TC) External Event  Selection\nAT91C_TC_EEVT_NONE        EQU (0x0:SHL:10) ;- (TC) Signal selected as external event: TIOB TIOB direction: input\nAT91C_TC_EEVT_RISING      EQU (0x1:SHL:10) ;- (TC) Signal selected as external event: XC0 TIOB direction: output\nAT91C_TC_EEVT_FALLING     EQU (0x2:SHL:10) ;- (TC) Signal selected as external event: XC1 TIOB direction: output\nAT91C_TC_EEVT_BOTH        EQU (0x3:SHL:10) ;- (TC) Signal selected as external event: XC2 TIOB direction: output\nAT91C_TC_ENETRG           EQU (0x1:SHL:12) ;- (TC) External Event Trigger enable\nAT91C_TC_WAVESEL          EQU (0x3:SHL:13) ;- (TC) Waveform  Selection\nAT91C_TC_WAVESEL_UP       EQU (0x0:SHL:13) ;- (TC) UP mode without atomatic trigger on RC Compare\nAT91C_TC_WAVESEL_UPDOWN   EQU (0x1:SHL:13) ;- (TC) UPDOWN mode without automatic trigger on RC Compare\nAT91C_TC_WAVESEL_UP_AUTO  EQU (0x2:SHL:13) ;- (TC) UP mode with automatic trigger on RC Compare\nAT91C_TC_WAVESEL_UPDOWN_AUTO EQU (0x3:SHL:13) ;- (TC) UPDOWN mode with automatic trigger on RC Compare\nAT91C_TC_CPCTRG           EQU (0x1:SHL:14) ;- (TC) RC Compare Trigger Enable\nAT91C_TC_WAVE             EQU (0x1:SHL:15) ;- (TC) \nAT91C_TC_ACPA             EQU (0x3:SHL:16) ;- (TC) RA Compare Effect on TIOA\nAT91C_TC_ACPA_NONE        EQU (0x0:SHL:16) ;- (TC) Effect: none\nAT91C_TC_ACPA_SET         EQU (0x1:SHL:16) ;- (TC) Effect: set\nAT91C_TC_ACPA_CLEAR       EQU (0x2:SHL:16) ;- (TC) Effect: clear\nAT91C_TC_ACPA_TOGGLE      EQU (0x3:SHL:16) ;- (TC) Effect: toggle\nAT91C_TC_ACPC             EQU (0x3:SHL:18) ;- (TC) RC Compare Effect on TIOA\nAT91C_TC_ACPC_NONE        EQU (0x0:SHL:18) ;- (TC) Effect: none\nAT91C_TC_ACPC_SET         EQU (0x1:SHL:18) ;- (TC) Effect: set\nAT91C_TC_ACPC_CLEAR       EQU (0x2:SHL:18) ;- (TC) Effect: clear\nAT91C_TC_ACPC_TOGGLE      EQU (0x3:SHL:18) ;- (TC) Effect: toggle\nAT91C_TC_AEEVT            EQU (0x3:SHL:20) ;- (TC) External Event Effect on TIOA\nAT91C_TC_AEEVT_NONE       EQU (0x0:SHL:20) ;- (TC) Effect: none\nAT91C_TC_AEEVT_SET        EQU (0x1:SHL:20) ;- (TC) Effect: set\nAT91C_TC_AEEVT_CLEAR      EQU (0x2:SHL:20) ;- (TC) Effect: clear\nAT91C_TC_AEEVT_TOGGLE     EQU (0x3:SHL:20) ;- (TC) Effect: toggle\nAT91C_TC_ASWTRG           EQU (0x3:SHL:22) ;- (TC) Software Trigger Effect on TIOA\nAT91C_TC_ASWTRG_NONE      EQU (0x0:SHL:22) ;- (TC) Effect: none\nAT91C_TC_ASWTRG_SET       EQU (0x1:SHL:22) ;- (TC) Effect: set\nAT91C_TC_ASWTRG_CLEAR     EQU (0x2:SHL:22) ;- (TC) Effect: clear\nAT91C_TC_ASWTRG_TOGGLE    EQU (0x3:SHL:22) ;- (TC) Effect: toggle\nAT91C_TC_BCPB             EQU (0x3:SHL:24) ;- (TC) RB Compare Effect on TIOB\nAT91C_TC_BCPB_NONE        EQU (0x0:SHL:24) ;- (TC) Effect: none\nAT91C_TC_BCPB_SET         EQU (0x1:SHL:24) ;- (TC) Effect: set\nAT91C_TC_BCPB_CLEAR       EQU (0x2:SHL:24) ;- (TC) Effect: clear\nAT91C_TC_BCPB_TOGGLE      EQU (0x3:SHL:24) ;- (TC) Effect: toggle\nAT91C_TC_BCPC             EQU (0x3:SHL:26) ;- (TC) RC Compare Effect on TIOB\nAT91C_TC_BCPC_NONE        EQU (0x0:SHL:26) ;- (TC) Effect: none\nAT91C_TC_BCPC_SET         EQU (0x1:SHL:26) ;- (TC) Effect: set\nAT91C_TC_BCPC_CLEAR       EQU (0x2:SHL:26) ;- (TC) Effect: clear\nAT91C_TC_BCPC_TOGGLE      EQU (0x3:SHL:26) ;- (TC) Effect: toggle\nAT91C_TC_BEEVT            EQU (0x3:SHL:28) ;- (TC) External Event Effect on TIOB\nAT91C_TC_BEEVT_NONE       EQU (0x0:SHL:28) ;- (TC) Effect: none\nAT91C_TC_BEEVT_SET        EQU (0x1:SHL:28) ;- (TC) Effect: set\nAT91C_TC_BEEVT_CLEAR      EQU (0x2:SHL:28) ;- (TC) Effect: clear\nAT91C_TC_BEEVT_TOGGLE     EQU (0x3:SHL:28) ;- (TC) Effect: toggle\nAT91C_TC_BSWTRG           EQU (0x3:SHL:30) ;- (TC) Software Trigger Effect on TIOB\nAT91C_TC_BSWTRG_NONE      EQU (0x0:SHL:30) ;- (TC) Effect: none\nAT91C_TC_BSWTRG_SET       EQU (0x1:SHL:30) ;- (TC) Effect: set\nAT91C_TC_BSWTRG_CLEAR     EQU (0x2:SHL:30) ;- (TC) Effect: clear\nAT91C_TC_BSWTRG_TOGGLE    EQU (0x3:SHL:30) ;- (TC) Effect: toggle\n;- -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- \nAT91C_TC_COVFS            EQU (0x1:SHL:0) ;- (TC) Counter Overflow\nAT91C_TC_LOVRS            EQU (0x1:SHL:1) ;- (TC) Load Overrun\nAT91C_TC_CPAS             EQU (0x1:SHL:2) ;- (TC) RA Compare\nAT91C_TC_CPBS             EQU (0x1:SHL:3) ;- (TC) RB Compare\nAT91C_TC_CPCS             EQU (0x1:SHL:4) ;- (TC) RC Compare\nAT91C_TC_LDRAS            EQU (0x1:SHL:5) ;- (TC) RA Loading\nAT91C_TC_LDRBS            EQU (0x1:SHL:6) ;- (TC) RB Loading\nAT91C_TC_ETRCS            EQU (0x1:SHL:7) ;- (TC) External Trigger\nAT91C_TC_ETRGS            EQU (0x1:SHL:16) ;- (TC) Clock Enabling\nAT91C_TC_MTIOA            EQU (0x1:SHL:17) ;- (TC) TIOA Mirror\nAT91C_TC_MTIOB            EQU (0x1:SHL:18) ;- (TC) TIOA Mirror\n;- -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- \n;- -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- \n;- -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- \n\n;- *****************************************************************************\n;-              SOFTWARE API DEFINITION  FOR Timer Counter Interface\n;- *****************************************************************************\n                ^ 0 ;- AT91S_TCB\nTCB_TC0         # 48 ;- TC Channel 0\n                # 16 ;- Reserved\nTCB_TC1         # 48 ;- TC Channel 1\n                # 16 ;- Reserved\nTCB_TC2         # 48 ;- TC Channel 2\n                # 16 ;- Reserved\nTCB_BCR         #  4 ;- TC Block Control Register\nTCB_BMR         #  4 ;- TC Block Mode Register\n;- -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- \nAT91C_TCB_SYNC            EQU (0x1:SHL:0) ;- (TCB) Synchro Command\n;- -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- \nAT91C_TCB_TC0XC0S         EQU (0x1:SHL:0) ;- (TCB) External Clock Signal 0 Selection\nAT91C_TCB_TC0XC0S_TCLK0   EQU (0x0) ;- (TCB) TCLK0 connected to XC0\nAT91C_TCB_TC0XC0S_NONE    EQU (0x1) ;- (TCB) None signal connected to XC0\nAT91C_TCB_TC0XC0S_TIOA1   EQU (0x2) ;- (TCB) TIOA1 connected to XC0\nAT91C_TCB_TC0XC0S_TIOA2   EQU (0x3) ;- (TCB) TIOA2 connected to XC0\nAT91C_TCB_TC1XC1S         EQU (0x1:SHL:2) ;- (TCB) External Clock Signal 1 Selection\nAT91C_TCB_TC1XC1S_TCLK1   EQU (0x0:SHL:2) ;- (TCB) TCLK1 connected to XC1\nAT91C_TCB_TC1XC1S_NONE    EQU (0x1:SHL:2) ;- (TCB) None signal connected to XC1\nAT91C_TCB_TC1XC1S_TIOA0   EQU (0x2:SHL:2) ;- (TCB) TIOA0 connected to XC1\nAT91C_TCB_TC1XC1S_TIOA2   EQU (0x3:SHL:2) ;- (TCB) TIOA2 connected to XC1\nAT91C_TCB_TC2XC2S         EQU (0x1:SHL:4) ;- (TCB) External Clock Signal 2 Selection\nAT91C_TCB_TC2XC2S_TCLK2   EQU (0x0:SHL:4) ;- (TCB) TCLK2 connected to XC2\nAT91C_TCB_TC2XC2S_NONE    EQU (0x1:SHL:4) ;- (TCB) None signal connected to XC2\nAT91C_TCB_TC2XC2S_TIOA0   EQU (0x2:SHL:4) ;- (TCB) TIOA0 connected to XC2\nAT91C_TCB_TC2XC2S_TIOA2   EQU (0x3:SHL:4) ;- (TCB) TIOA2 connected to XC2\n\n;- *****************************************************************************\n;-              SOFTWARE API DEFINITION  FOR USB Host Interface\n;- *****************************************************************************\n                ^ 0 ;- AT91S_UHP\nUHP_HcRevision  #  4 ;- Revision\nUHP_HcControl   #  4 ;- Operating modes for the Host Controller\nUHP_HcCommandStatus #  4 ;- Command & status Register\nUHP_HcInterruptStatus #  4 ;- Interrupt Status Register\nUHP_HcInterruptEnable #  4 ;- Interrupt Enable Register\nUHP_HcInterruptDisable #  4 ;- Interrupt Disable Register\nUHP_HcHCCA      #  4 ;- Pointer to the Host Controller Communication Area\nUHP_HcPeriodCurrentED #  4 ;- Current Isochronous or Interrupt Endpoint Descriptor\nUHP_HcControlHeadED #  4 ;- First Endpoint Descriptor of the Control list\nUHP_HcControlCurrentED #  4 ;- Endpoint Control and Status Register\nUHP_HcBulkHeadED #  4 ;- First endpoint register of the Bulk list\nUHP_HcBulkCurrentED #  4 ;- Current endpoint of the Bulk list\nUHP_HcBulkDoneHead #  4 ;- Last completed transfer descriptor\nUHP_HcFmInterval #  4 ;- Bit time between 2 consecutive SOFs\nUHP_HcFmRemaining #  4 ;- Bit time remaining in the current Frame\nUHP_HcFmNumber  #  4 ;- Frame number\nUHP_HcPeriodicStart #  4 ;- Periodic Start\nUHP_HcLSThreshold #  4 ;- LS Threshold\nUHP_HcRhDescriptorA #  4 ;- Root Hub characteristics A\nUHP_HcRhDescriptorB #  4 ;- Root Hub characteristics B\nUHP_HcRhStatus  #  4 ;- Root Hub Status register\nUHP_HcRhPortStatus #  8 ;- Root Hub Port Status Register\n\n;- *****************************************************************************\n;-              SOFTWARE API DEFINITION  FOR Ethernet MAC\n;- *****************************************************************************\n                ^ 0 ;- AT91S_EMAC\nEMAC_CTL        #  4 ;- Network Control Register\nEMAC_CFG        #  4 ;- Network Configuration Register\nEMAC_SR         #  4 ;- Network Status Register\nEMAC_TAR        #  4 ;- Transmit Address Register\nEMAC_TCR        #  4 ;- Transmit Control Register\nEMAC_TSR        #  4 ;- Transmit Status Register\nEMAC_RBQP       #  4 ;- Receive Buffer Queue Pointer\n                #  4 ;- Reserved\nEMAC_RSR        #  4 ;- Receive Status Register\nEMAC_ISR        #  4 ;- Interrupt Status Register\nEMAC_IER        #  4 ;- Interrupt Enable Register\nEMAC_IDR        #  4 ;- Interrupt Disable Register\nEMAC_IMR        #  4 ;- Interrupt Mask Register\nEMAC_MAN        #  4 ;- PHY Maintenance Register\n                #  8 ;- Reserved\nEMAC_FRA        #  4 ;- Frames Transmitted OK Register\nEMAC_SCOL       #  4 ;- Single Collision Frame Register\nEMAC_MCOL       #  4 ;- Multiple Collision Frame Register\nEMAC_OK         #  4 ;- Frames Received OK Register\nEMAC_SEQE       #  4 ;- Frame Check Sequence Error Register\nEMAC_ALE        #  4 ;- Alignment Error Register\nEMAC_DTE        #  4 ;- Deferred Transmission Frame Register\nEMAC_LCOL       #  4 ;- Late Collision Register\nEMAC_ECOL       #  4 ;- Excessive Collision Register\nEMAC_CSE        #  4 ;- Carrier Sense Error Register\nEMAC_TUE        #  4 ;- Transmit Underrun Error Register\nEMAC_CDE        #  4 ;- Code Error Register\nEMAC_ELR        #  4 ;- Excessive Length Error Register\nEMAC_RJB        #  4 ;- Receive Jabber Register\nEMAC_USF        #  4 ;- Undersize Frame Register\nEMAC_SQEE       #  4 ;- SQE Test Error Register\nEMAC_DRFC       #  4 ;- Discarded RX Frame Register\n                # 12 ;- Reserved\nEMAC_HSH        #  4 ;- Hash Address High[63:32]\nEMAC_HSL        #  4 ;- Hash Address Low[31:0]\nEMAC_SA1L       #  4 ;- Specific Address 1 Low, First 4 bytes\nEMAC_SA1H       #  4 ;- Specific Address 1 High, Last 2 bytes\nEMAC_SA2L       #  4 ;- Specific Address 2 Low, First 4 bytes\nEMAC_SA2H       #  4 ;- Specific Address 2 High, Last 2 bytes\nEMAC_SA3L       #  4 ;- Specific Address 3 Low, First 4 bytes\nEMAC_SA3H       #  4 ;- Specific Address 3 High, Last 2 bytes\nEMAC_SA4L       #  4 ;- Specific Address 4 Low, First 4 bytes\nEMAC_SA4H       #  4 ;- Specific Address 4 High, Last 2 bytesr\n;- -------- EMAC_CTL : (EMAC Offset: 0x0)  -------- \nAT91C_EMAC_LB             EQU (0x1:SHL:0) ;- (EMAC) Loopback. Optional. When set, loopback signal is at high level.\nAT91C_EMAC_LBL            EQU (0x1:SHL:1) ;- (EMAC) Loopback local. \nAT91C_EMAC_RE             EQU (0x1:SHL:2) ;- (EMAC) Receive enable. \nAT91C_EMAC_TE             EQU (0x1:SHL:3) ;- (EMAC) Transmit enable. \nAT91C_EMAC_MPE            EQU (0x1:SHL:4) ;- (EMAC) Management port enable. \nAT91C_EMAC_CSR            EQU (0x1:SHL:5) ;- (EMAC) Clear statistics registers. \nAT91C_EMAC_ISR            EQU (0x1:SHL:6) ;- (EMAC) Increment statistics registers. \nAT91C_EMAC_WES            EQU (0x1:SHL:7) ;- (EMAC) Write enable for statistics registers. \nAT91C_EMAC_BP             EQU (0x1:SHL:8) ;- (EMAC) Back pressure. \n;- -------- EMAC_CFG : (EMAC Offset: 0x4) Network Configuration Register -------- \nAT91C_EMAC_SPD            EQU (0x1:SHL:0) ;- (EMAC) Speed. \nAT91C_EMAC_FD             EQU (0x1:SHL:1) ;- (EMAC) Full duplex. \nAT91C_EMAC_BR             EQU (0x1:SHL:2) ;- (EMAC) Bit rate. \nAT91C_EMAC_CAF            EQU (0x1:SHL:4) ;- (EMAC) Copy all frames. \nAT91C_EMAC_NBC            EQU (0x1:SHL:5) ;- (EMAC) No broadcast. \nAT91C_EMAC_MTI            EQU (0x1:SHL:6) ;- (EMAC) Multicast hash enable\nAT91C_EMAC_UNI            EQU (0x1:SHL:7) ;- (EMAC) Unicast hash enable. \nAT91C_EMAC_BIG            EQU (0x1:SHL:8) ;- (EMAC) Receive 1522 bytes. \nAT91C_EMAC_EAE            EQU (0x1:SHL:9) ;- (EMAC) External address match enable. \nAT91C_EMAC_CLK            EQU (0x3:SHL:10) ;- (EMAC) \nAT91C_EMAC_CLK_HCLK_8     EQU (0x0:SHL:10) ;- (EMAC) HCLK divided by 8\nAT91C_EMAC_CLK_HCLK_16    EQU (0x1:SHL:10) ;- (EMAC) HCLK divided by 16\nAT91C_EMAC_CLK_HCLK_32    EQU (0x2:SHL:10) ;- (EMAC) HCLK divided by 32\nAT91C_EMAC_CLK_HCLK_64    EQU (0x3:SHL:10) ;- (EMAC) HCLK divided by 64\nAT91C_EMAC_RTY            EQU (0x1:SHL:12) ;- (EMAC) \nAT91C_EMAC_RMII           EQU (0x1:SHL:13) ;- (EMAC) \n;- -------- EMAC_SR : (EMAC Offset: 0x8) Network Status Register -------- \nAT91C_EMAC_MDIO           EQU (0x1:SHL:1) ;- (EMAC) \nAT91C_EMAC_IDLE           EQU (0x1:SHL:2) ;- (EMAC) \n;- -------- EMAC_TCR : (EMAC Offset: 0x10) Transmit Control Register -------- \nAT91C_EMAC_LEN            EQU (0x7FF:SHL:0) ;- (EMAC) \nAT91C_EMAC_NCRC           EQU (0x1:SHL:15) ;- (EMAC) \n;- -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Control Register -------- \nAT91C_EMAC_OVR            EQU (0x1:SHL:0) ;- (EMAC) \nAT91C_EMAC_COL            EQU (0x1:SHL:1) ;- (EMAC) \nAT91C_EMAC_RLE            EQU (0x1:SHL:2) ;- (EMAC) \nAT91C_EMAC_TXIDLE         EQU (0x1:SHL:3) ;- (EMAC) \nAT91C_EMAC_BNQ            EQU (0x1:SHL:4) ;- (EMAC) \nAT91C_EMAC_COMP           EQU (0x1:SHL:5) ;- (EMAC) \nAT91C_EMAC_UND            EQU (0x1:SHL:6) ;- (EMAC) \n;- -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- \nAT91C_EMAC_BNA            EQU (0x1:SHL:0) ;- (EMAC) \nAT91C_EMAC_REC            EQU (0x1:SHL:1) ;- (EMAC) \n;- -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- \nAT91C_EMAC_DONE           EQU (0x1:SHL:0) ;- (EMAC) \nAT91C_EMAC_RCOM           EQU (0x1:SHL:1) ;- (EMAC) \nAT91C_EMAC_RBNA           EQU (0x1:SHL:2) ;- (EMAC) \nAT91C_EMAC_TOVR           EQU (0x1:SHL:3) ;- (EMAC) \nAT91C_EMAC_TUND           EQU (0x1:SHL:4) ;- (EMAC) \nAT91C_EMAC_RTRY           EQU (0x1:SHL:5) ;- (EMAC) \nAT91C_EMAC_TBRE           EQU (0x1:SHL:6) ;- (EMAC) \nAT91C_EMAC_TCOM           EQU (0x1:SHL:7) ;- (EMAC) \nAT91C_EMAC_TIDLE          EQU (0x1:SHL:8) ;- (EMAC) \nAT91C_EMAC_LINK           EQU (0x1:SHL:9) ;- (EMAC) \nAT91C_EMAC_ROVR           EQU (0x1:SHL:10) ;- (EMAC) \nAT91C_EMAC_HRESP          EQU (0x1:SHL:11) ;- (EMAC) \n;- -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- \n;- -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- \n;- -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- \n;- -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- \nAT91C_EMAC_DATA           EQU (0xFFFF:SHL:0) ;- (EMAC) \nAT91C_EMAC_CODE           EQU (0x3:SHL:16) ;- (EMAC) \nAT91C_EMAC_REGA           EQU (0x1F:SHL:18) ;- (EMAC) \nAT91C_EMAC_PHYA           EQU (0x1F:SHL:23) ;- (EMAC) \nAT91C_EMAC_RW             EQU (0x3:SHL:28) ;- (EMAC) \nAT91C_EMAC_HIGH           EQU (0x1:SHL:30) ;- (EMAC) \nAT91C_EMAC_LOW            EQU (0x1:SHL:31) ;- (EMAC) \n\n;- *****************************************************************************\n;-              SOFTWARE API DEFINITION  FOR External Bus Interface\n;- *****************************************************************************\n                ^ 0 ;- AT91S_EBI\nEBI_CSA         #  4 ;- Chip Select Assignment Register\nEBI_CFGR        #  4 ;- Configuration Register\n;- -------- EBI_CSA : (EBI Offset: 0x0) Chip Select Assignment Register -------- \nAT91C_EBI_CS0A            EQU (0x1:SHL:0) ;- (EBI) Chip Select 0 Assignment\nAT91C_EBI_CS0A_SMC        EQU (0x0) ;- (EBI) Chip Select 0 is assigned to the Static Memory Controller.\nAT91C_EBI_CS0A_BFC        EQU (0x1) ;- (EBI) Chip Select 0 is assigned to the Burst Flash Controller.\nAT91C_EBI_CS1A            EQU (0x1:SHL:1) ;- (EBI) Chip Select 1 Assignment\nAT91C_EBI_CS1A_SMC        EQU (0x0:SHL:1) ;- (EBI) Chip Select 1 is assigned to the Static Memory Controller.\nAT91C_EBI_CS1A_SDRAMC     EQU (0x1:SHL:1) ;- (EBI) Chip Select 1 is assigned to the SDRAM Controller.\nAT91C_EBI_CS3A            EQU (0x1:SHL:3) ;- (EBI) Chip Select 3 Assignment\nAT91C_EBI_CS3A_SMC        EQU (0x0:SHL:3) ;- (EBI) Chip Select 3 is only assigned to the Static Memory Controller and NCS3 behaves as defined by the SMC2.\nAT91C_EBI_CS3A_SMC_SmartMedia EQU (0x1:SHL:3) ;- (EBI) Chip Select 3 is assigned to the Static Memory Controller and the SmartMedia Logic is activated.\nAT91C_EBI_CS4A            EQU (0x1:SHL:4) ;- (EBI) Chip Select 4 Assignment\nAT91C_EBI_CS4A_SMC        EQU (0x0:SHL:4) ;- (EBI) Chip Select 4 is assigned to the Static Memory Controller and NCS4,NCS5 and NCS6 behave as defined by the SMC2.\nAT91C_EBI_CS4A_SMC_CompactFlash EQU (0x1:SHL:4) ;- (EBI) Chip Select 4 is assigned to the Static Memory Controller and the CompactFlash Logic is activated.\n;- -------- EBI_CFGR : (EBI Offset: 0x4) Configuration Register -------- \nAT91C_EBI_DBPUC           EQU (0x1:SHL:0) ;- (EBI) Data Bus Pull-Up Configuration\nAT91C_EBI_EBSEN           EQU (0x1:SHL:1) ;- (EBI) Bus Sharing Enable\n\n;- *****************************************************************************\n;-              SOFTWARE API DEFINITION  FOR Static Memory Controller 2 Interface\n;- *****************************************************************************\n                ^ 0 ;- AT91S_SMC2\nSMC2_CSR        # 32 ;- SMC2 Chip Select Register\n;- -------- SMC2_CSR : (SMC2 Offset: 0x0) SMC2 Chip Select Register -------- \nAT91C_SMC2_NWS            EQU (0x7F:SHL:0) ;- (SMC2) Number of Wait States\nAT91C_SMC2_WSEN           EQU (0x1:SHL:7) ;- (SMC2) Wait State Enable\nAT91C_SMC2_TDF            EQU (0xF:SHL:8) ;- (SMC2) Data Float Time\nAT91C_SMC2_BAT            EQU (0x1:SHL:12) ;- (SMC2) Byte Access Type\nAT91C_SMC2_DBW            EQU (0x1:SHL:13) ;- (SMC2) Data Bus Width\nAT91C_SMC2_DBW_16         EQU (0x1:SHL:13) ;- (SMC2) 16-bit.\nAT91C_SMC2_DBW_8          EQU (0x2:SHL:13) ;- (SMC2) 8-bit.\nAT91C_SMC2_DRP            EQU (0x1:SHL:15) ;- (SMC2) Data Read Protocol\nAT91C_SMC2_ACSS           EQU (0x3:SHL:16) ;- (SMC2) Address to Chip Select Setup\nAT91C_SMC2_ACSS_STANDARD  EQU (0x0:SHL:16) ;- (SMC2) Standard, asserted at the beginning of the access and deasserted at the end.\nAT91C_SMC2_ACSS_1_CYCLE   EQU (0x1:SHL:16) ;- (SMC2) One cycle less at the beginning and the end of the access.\nAT91C_SMC2_ACSS_2_CYCLES  EQU (0x2:SHL:16) ;- (SMC2) Two cycles less at the beginning and the end of the access.\nAT91C_SMC2_ACSS_3_CYCLES  EQU (0x3:SHL:16) ;- (SMC2) Three cycles less at the beginning and the end of the access.\nAT91C_SMC2_RWSETUP        EQU (0x7:SHL:24) ;- (SMC2) Read and Write Signal Setup Time\nAT91C_SMC2_RWHOLD         EQU (0x7:SHL:29) ;- (SMC2) Read and Write Signal Hold Time\n\n;- *****************************************************************************\n;-              SOFTWARE API DEFINITION  FOR SDRAM Controller Interface\n;- *****************************************************************************\n                ^ 0 ;- AT91S_SDRC\nSDRC_MR         #  4 ;- SDRAM Controller Mode Register\nSDRC_TR         #  4 ;- SDRAM Controller Refresh Timer Register\nSDRC_CR         #  4 ;- SDRAM Controller Configuration Register\nSDRC_SRR        #  4 ;- SDRAM Controller Self Refresh Register\nSDRC_LPR        #  4 ;- SDRAM Controller Low Power Register\nSDRC_IER        #  4 ;- SDRAM Controller Interrupt Enable Register\nSDRC_IDR        #  4 ;- SDRAM Controller Interrupt Disable Register\nSDRC_IMR        #  4 ;- SDRAM Controller Interrupt Mask Register\nSDRC_ISR        #  4 ;- SDRAM Controller Interrupt Mask Register\n;- -------- SDRC_MR : (SDRC Offset: 0x0) SDRAM Controller Mode Register -------- \nAT91C_SDRC_MODE           EQU (0xF:SHL:0) ;- (SDRC) Mode\nAT91C_SDRC_MODE_NORMAL_CMD EQU (0x0) ;- (SDRC) Normal Mode\nAT91C_SDRC_MODE_NOP_CMD   EQU (0x1) ;- (SDRC) NOP Command\nAT91C_SDRC_MODE_PRCGALL_CMD EQU (0x2) ;- (SDRC) All Banks Precharge Command\nAT91C_SDRC_MODE_LMR_CMD   EQU (0x3) ;- (SDRC) Load Mode Register Command\nAT91C_SDRC_MODE_RFSH_CMD  EQU (0x4) ;- (SDRC) Refresh Command\nAT91C_SDRC_DBW            EQU (0x1:SHL:4) ;- (SDRC) Data Bus Width\nAT91C_SDRC_DBW_32_BITS    EQU (0x0:SHL:4) ;- (SDRC) 32 Bits datas bus\nAT91C_SDRC_DBW_16_BITS    EQU (0x1:SHL:4) ;- (SDRC) 16 Bits datas bus\n;- -------- SDRC_TR : (SDRC Offset: 0x4) SDRC Refresh Timer Register -------- \nAT91C_SDRC_COUNT          EQU (0xFFF:SHL:0) ;- (SDRC) Refresh Counter\n;- -------- SDRC_CR : (SDRC Offset: 0x8) SDRAM Configuration Register -------- \nAT91C_SDRC_NC             EQU (0x3:SHL:0) ;- (SDRC) Number of Column Bits\nAT91C_SDRC_NC_8           EQU (0x0) ;- (SDRC) 8 Bits\nAT91C_SDRC_NC_9           EQU (0x1) ;- (SDRC) 9 Bits\nAT91C_SDRC_NC_10          EQU (0x2) ;- (SDRC) 10 Bits\nAT91C_SDRC_NC_11          EQU (0x3) ;- (SDRC) 11 Bits\nAT91C_SDRC_NR             EQU (0x3:SHL:2) ;- (SDRC) Number of Row Bits\nAT91C_SDRC_NR_11          EQU (0x0:SHL:2) ;- (SDRC) 11 Bits\nAT91C_SDRC_NR_12          EQU (0x1:SHL:2) ;- (SDRC) 12 Bits\nAT91C_SDRC_NR_13          EQU (0x2:SHL:2) ;- (SDRC) 13 Bits\nAT91C_SDRC_NB             EQU (0x1:SHL:4) ;- (SDRC) Number of Banks\nAT91C_SDRC_NB_2_BANKS     EQU (0x0:SHL:4) ;- (SDRC) 2 banks\nAT91C_SDRC_NB_4_BANKS     EQU (0x1:SHL:4) ;- (SDRC) 4 banks\nAT91C_SDRC_CAS            EQU (0x3:SHL:5) ;- (SDRC) CAS Latency\nAT91C_SDRC_CAS_2          EQU (0x2:SHL:5) ;- (SDRC) 2 cycles\nAT91C_SDRC_TWR            EQU (0xF:SHL:7) ;- (SDRC) Number of Write Recovery Time Cycles\nAT91C_SDRC_TRC            EQU (0xF:SHL:11) ;- (SDRC) Number of RAS Cycle Time Cycles\nAT91C_SDRC_TRP            EQU (0xF:SHL:15) ;- (SDRC) Number of RAS Precharge Time Cycles\nAT91C_SDRC_TRCD           EQU (0xF:SHL:19) ;- (SDRC) Number of RAS to CAS Delay Cycles\nAT91C_SDRC_TRAS           EQU (0xF:SHL:23) ;- (SDRC) Number of RAS Active Time Cycles\nAT91C_SDRC_TXSR           EQU (0xF:SHL:27) ;- (SDRC) Number of Command Recovery Time Cycles\n;- -------- SDRC_SRR : (SDRC Offset: 0xc) SDRAM Controller Self-refresh Register -------- \nAT91C_SDRC_SRCB           EQU (0x1:SHL:0) ;- (SDRC) Self-refresh Command Bit\n;- -------- SDRC_LPR : (SDRC Offset: 0x10) SDRAM Controller Low-power Register -------- \nAT91C_SDRC_LPCB           EQU (0x1:SHL:0) ;- (SDRC) Low-power Command Bit\n;- -------- SDRC_IER : (SDRC Offset: 0x14) SDRAM Controller Interrupt Enable Register -------- \nAT91C_SDRC_RES            EQU (0x1:SHL:0) ;- (SDRC) Refresh Error Status\n;- -------- SDRC_IDR : (SDRC Offset: 0x18) SDRAM Controller Interrupt Disable Register -------- \n;- -------- SDRC_IMR : (SDRC Offset: 0x1c) SDRAM Controller Interrupt Mask Register -------- \n;- -------- SDRC_ISR : (SDRC Offset: 0x20) SDRAM Controller Interrupt Status Register -------- \n\n;- *****************************************************************************\n;-              SOFTWARE API DEFINITION  FOR Burst Flash Controller Interface\n;- *****************************************************************************\n                ^ 0 ;- AT91S_BFC\nBFC_MR          #  4 ;- BFC Mode Register\n;- -------- BFC_MR : (BFC Offset: 0x0) BFC Mode Register -------- \nAT91C_BFC_BFCOM           EQU (0x3:SHL:0) ;- (BFC) Burst Flash Controller Operating Mode\nAT91C_BFC_BFCOM_DISABLED  EQU (0x0) ;- (BFC) NPCS0 is driven by the SMC or remains high.\nAT91C_BFC_BFCOM_ASYNC     EQU (0x1) ;- (BFC) Asynchronous\nAT91C_BFC_BFCOM_BURST_READ EQU (0x2) ;- (BFC) Burst Read\nAT91C_BFC_BFCC            EQU (0x3:SHL:2) ;- (BFC) Burst Flash Controller Operating Mode\nAT91C_BFC_BFCC_MCK        EQU (0x1:SHL:2) ;- (BFC) Master Clock.\nAT91C_BFC_BFCC_MCK_DIV_2  EQU (0x2:SHL:2) ;- (BFC) Master Clock divided by 2.\nAT91C_BFC_BFCC_MCK_DIV_4  EQU (0x3:SHL:2) ;- (BFC) Master Clock divided by 4.\nAT91C_BFC_AVL             EQU (0xF:SHL:4) ;- (BFC) Address Valid Latency\nAT91C_BFC_PAGES           EQU (0x7:SHL:8) ;- (BFC) Page Size\nAT91C_BFC_PAGES_NO_PAGE   EQU (0x0:SHL:8) ;- (BFC) No page handling.\nAT91C_BFC_PAGES_16        EQU (0x1:SHL:8) ;- (BFC) 16 bytes page size.\nAT91C_BFC_PAGES_32        EQU (0x2:SHL:8) ;- (BFC) 32 bytes page size.\nAT91C_BFC_PAGES_64        EQU (0x3:SHL:8) ;- (BFC) 64 bytes page size.\nAT91C_BFC_PAGES_128       EQU (0x4:SHL:8) ;- (BFC) 128 bytes page size.\nAT91C_BFC_PAGES_256       EQU (0x5:SHL:8) ;- (BFC) 256 bytes page size.\nAT91C_BFC_PAGES_512       EQU (0x6:SHL:8) ;- (BFC) 512 bytes page size.\nAT91C_BFC_PAGES_1024      EQU (0x7:SHL:8) ;- (BFC) 1024 bytes page size.\nAT91C_BFC_OEL             EQU (0x3:SHL:12) ;- (BFC) Output Enable Latency\nAT91C_BFC_BAAEN           EQU (0x1:SHL:16) ;- (BFC) Burst Address Advance Enable\nAT91C_BFC_BFOEH           EQU (0x1:SHL:17) ;- (BFC) Burst Flash Output Enable Handling\nAT91C_BFC_MUXEN           EQU (0x1:SHL:18) ;- (BFC) Multiplexed Bus Enable\nAT91C_BFC_RDYEN           EQU (0x1:SHL:19) ;- (BFC) Ready Enable Mode\n\n;- *****************************************************************************\n;-               REGISTER ADDRESS DEFINITION FOR AT91RM9200\n;- *****************************************************************************\n;- ========== Register definition for SYS peripheral ========== \n;- ========== Register definition for MC peripheral ========== \nAT91C_MC_PUER             EQU (0xFFFFFF54) ;- (MC) MC Protection Unit Enable Register\nAT91C_MC_ASR              EQU (0xFFFFFF04) ;- (MC) MC Abort Status Register\nAT91C_MC_PUP              EQU (0xFFFFFF50) ;- (MC) MC Protection Unit Peripherals\nAT91C_MC_PUIA             EQU (0xFFFFFF10) ;- (MC) MC Protection Unit Area\nAT91C_MC_AASR             EQU (0xFFFFFF08) ;- (MC) MC Abort Address Status Register\nAT91C_MC_RCR              EQU (0xFFFFFF00) ;- (MC) MC Remap Control Register\n;- ========== Register definition for RTC peripheral ========== \nAT91C_RTC_IMR             EQU (0xFFFFFE28) ;- (RTC) Interrupt Mask Register\nAT91C_RTC_IER             EQU (0xFFFFFE20) ;- (RTC) Interrupt Enable Register\nAT91C_RTC_SR              EQU (0xFFFFFE18) ;- (RTC) Status Register\nAT91C_RTC_TIMALR          EQU (0xFFFFFE10) ;- (RTC) Time Alarm Register\nAT91C_RTC_TIMR            EQU (0xFFFFFE08) ;- (RTC) Time Register\nAT91C_RTC_CR              EQU (0xFFFFFE00) ;- (RTC) Control Register\nAT91C_RTC_VER             EQU (0xFFFFFE2C) ;- (RTC) Valid Entry Register\nAT91C_RTC_IDR             EQU (0xFFFFFE24) ;- (RTC) Interrupt Disable Register\nAT91C_RTC_SCCR            EQU (0xFFFFFE1C) ;- (RTC) Status Clear Command Register\nAT91C_RTC_CALALR          EQU (0xFFFFFE14) ;- (RTC) Calendar Alarm Register\nAT91C_RTC_CALR            EQU (0xFFFFFE0C) ;- (RTC) Calendar Register\nAT91C_RTC_MR              EQU (0xFFFFFE04) ;- (RTC) Mode Register\n;- ========== Register definition for ST peripheral ========== \nAT91C_ST_CRTR             EQU (0xFFFFFD24) ;- (ST) Current Real-time Register\nAT91C_ST_IMR              EQU (0xFFFFFD1C) ;- (ST) Interrupt Mask Register\nAT91C_ST_IER              EQU (0xFFFFFD14) ;- (ST) Interrupt Enable Register\nAT91C_ST_RTMR             EQU (0xFFFFFD0C) ;- (ST) Real-time Mode Register\nAT91C_ST_PIMR             EQU (0xFFFFFD04) ;- (ST) Period Interval Mode Register\nAT91C_ST_RTAR             EQU (0xFFFFFD20) ;- (ST) Real-time Alarm Register\nAT91C_ST_IDR              EQU (0xFFFFFD18) ;- (ST) Interrupt Disable Register\nAT91C_ST_SR               EQU (0xFFFFFD10) ;- (ST) Status Register\nAT91C_ST_WDMR             EQU (0xFFFFFD08) ;- (ST) Watchdog Mode Register\nAT91C_ST_CR               EQU (0xFFFFFD00) ;- (ST) Control Register\n;- ========== Register definition for PMC peripheral ========== \nAT91C_PMC_SCSR            EQU (0xFFFFFC08) ;- (PMC) System Clock Status Register\nAT91C_PMC_SCER            EQU (0xFFFFFC00) ;- (PMC) System Clock Enable Register\nAT91C_PMC_IMR             EQU (0xFFFFFC6C) ;- (PMC) Interrupt Mask Register\nAT91C_PMC_IDR             EQU (0xFFFFFC64) ;- (PMC) Interrupt Disable Register\nAT91C_PMC_PCDR            EQU (0xFFFFFC14) ;- (PMC) Peripheral Clock Disable Register\nAT91C_PMC_SCDR            EQU (0xFFFFFC04) ;- (PMC) System Clock Disable Register\nAT91C_PMC_SR              EQU (0xFFFFFC68) ;- (PMC) Status Register\nAT91C_PMC_IER             EQU (0xFFFFFC60) ;- (PMC) Interrupt Enable Register\nAT91C_PMC_MCKR            EQU (0xFFFFFC30) ;- (PMC) Master Clock Register\nAT91C_PMC_PCER            EQU (0xFFFFFC10) ;- (PMC) Peripheral Clock Enable Register\nAT91C_PMC_PCSR            EQU (0xFFFFFC18) ;- (PMC) Peripheral Clock Status Register\nAT91C_PMC_PCKR            EQU (0xFFFFFC40) ;- (PMC) Programmable Clock Register\n;- ========== Register definition for CKGR peripheral ========== \nAT91C_CKGR_PLLBR          EQU (0xFFFFFC2C) ;- (CKGR) PLL B Register\nAT91C_CKGR_MCFR           EQU (0xFFFFFC24) ;- (CKGR) Main Clock  Frequency Register\nAT91C_CKGR_PLLAR          EQU (0xFFFFFC28) ;- (CKGR) PLL A Register\nAT91C_CKGR_MOR            EQU (0xFFFFFC20) ;- (CKGR) Main Oscillator Register\n;- ========== Register definition for PIOD peripheral ========== \nAT91C_PIOD_PDSR           EQU (0xFFFFFA3C) ;- (PIOD) Pin Data Status Register\nAT91C_PIOD_CODR           EQU (0xFFFFFA34) ;- (PIOD) Clear Output Data Register\nAT91C_PIOD_OWER           EQU (0xFFFFFAA0) ;- (PIOD) Output Write Enable Register\nAT91C_PIOD_MDER           EQU (0xFFFFFA50) ;- (PIOD) Multi-driver Enable Register\nAT91C_PIOD_IMR            EQU (0xFFFFFA48) ;- (PIOD) Interrupt Mask Register\nAT91C_PIOD_IER            EQU (0xFFFFFA40) ;- (PIOD) Interrupt Enable Register\nAT91C_PIOD_ODSR           EQU (0xFFFFFA38) ;- (PIOD) Output Data Status Register\nAT91C_PIOD_SODR           EQU (0xFFFFFA30) ;- (PIOD) Set Output Data Register\nAT91C_PIOD_PER            EQU (0xFFFFFA00) ;- (PIOD) PIO Enable Register\nAT91C_PIOD_OWDR           EQU (0xFFFFFAA4) ;- (PIOD) Output Write Disable Register\nAT91C_PIOD_PPUER          EQU (0xFFFFFA64) ;- (PIOD) Pull-up Enable Register\nAT91C_PIOD_MDDR           EQU (0xFFFFFA54) ;- (PIOD) Multi-driver Disable Register\nAT91C_PIOD_ISR            EQU (0xFFFFFA4C) ;- (PIOD) Interrupt Status Register\nAT91C_PIOD_IDR            EQU (0xFFFFFA44) ;- (PIOD) Interrupt Disable Register\nAT91C_PIOD_PDR            EQU (0xFFFFFA04) ;- (PIOD) PIO Disable Register\nAT91C_PIOD_ODR            EQU (0xFFFFFA14) ;- (PIOD) Output Disable Registerr\nAT91C_PIOD_OWSR           EQU (0xFFFFFAA8) ;- (PIOD) Output Write Status Register\nAT91C_PIOD_ABSR           EQU (0xFFFFFA78) ;- (PIOD) AB Select Status Register\nAT91C_PIOD_ASR            EQU (0xFFFFFA70) ;- (PIOD) Select A Register\nAT91C_PIOD_PPUSR          EQU (0xFFFFFA68) ;- (PIOD) Pad Pull-up Status Register\nAT91C_PIOD_PPUDR          EQU (0xFFFFFA60) ;- (PIOD) Pull-up Disable Register\nAT91C_PIOD_MDSR           EQU (0xFFFFFA58) ;- (PIOD) Multi-driver Status Register\nAT91C_PIOD_PSR            EQU (0xFFFFFA08) ;- (PIOD) PIO Status Register\nAT91C_PIOD_OER            EQU (0xFFFFFA10) ;- (PIOD) Output Enable Register\nAT91C_PIOD_OSR            EQU (0xFFFFFA18) ;- (PIOD) Output Status Register\nAT91C_PIOD_IFER           EQU (0xFFFFFA20) ;- (PIOD) Input Filter Enable Register\nAT91C_PIOD_BSR            EQU (0xFFFFFA74) ;- (PIOD) Select B Register\nAT91C_PIOD_IFDR           EQU (0xFFFFFA24) ;- (PIOD) Input Filter Disable Register\nAT91C_PIOD_IFSR           EQU (0xFFFFFA28) ;- (PIOD) Input Filter Status Register\n;- ========== Register definition for PIOC peripheral ========== \nAT91C_PIOC_IFDR           EQU (0xFFFFF824) ;- (PIOC) Input Filter Disable Register\nAT91C_PIOC_ODR            EQU (0xFFFFF814) ;- (PIOC) Output Disable Registerr\nAT91C_PIOC_ABSR           EQU (0xFFFFF878) ;- (PIOC) AB Select Status Register\nAT91C_PIOC_SODR           EQU (0xFFFFF830) ;- (PIOC) Set Output Data Register\nAT91C_PIOC_IFSR           EQU (0xFFFFF828) ;- (PIOC) Input Filter Status Register\nAT91C_PIOC_CODR           EQU (0xFFFFF834) ;- (PIOC) Clear Output Data Register\nAT91C_PIOC_ODSR           EQU (0xFFFFF838) ;- (PIOC) Output Data Status Register\nAT91C_PIOC_IER            EQU (0xFFFFF840) ;- (PIOC) Interrupt Enable Register\nAT91C_PIOC_IMR            EQU (0xFFFFF848) ;- (PIOC) Interrupt Mask Register\nAT91C_PIOC_OWDR           EQU (0xFFFFF8A4) ;- (PIOC) Output Write Disable Register\nAT91C_PIOC_MDDR           EQU (0xFFFFF854) ;- (PIOC) Multi-driver Disable Register\nAT91C_PIOC_PDSR           EQU (0xFFFFF83C) ;- (PIOC) Pin Data Status Register\nAT91C_PIOC_IDR            EQU (0xFFFFF844) ;- (PIOC) Interrupt Disable Register\nAT91C_PIOC_ISR            EQU (0xFFFFF84C) ;- (PIOC) Interrupt Status Register\nAT91C_PIOC_PDR            EQU (0xFFFFF804) ;- (PIOC) PIO Disable Register\nAT91C_PIOC_OWSR           EQU (0xFFFFF8A8) ;- (PIOC) Output Write Status Register\nAT91C_PIOC_OWER           EQU (0xFFFFF8A0) ;- (PIOC) Output Write Enable Register\nAT91C_PIOC_ASR            EQU (0xFFFFF870) ;- (PIOC) Select A Register\nAT91C_PIOC_PPUSR          EQU (0xFFFFF868) ;- (PIOC) Pad Pull-up Status Register\nAT91C_PIOC_PPUDR          EQU (0xFFFFF860) ;- (PIOC) Pull-up Disable Register\nAT91C_PIOC_MDSR           EQU (0xFFFFF858) ;- (PIOC) Multi-driver Status Register\nAT91C_PIOC_MDER           EQU (0xFFFFF850) ;- (PIOC) Multi-driver Enable Register\nAT91C_PIOC_IFER           EQU (0xFFFFF820) ;- (PIOC) Input Filter Enable Register\nAT91C_PIOC_OSR            EQU (0xFFFFF818) ;- (PIOC) Output Status Register\nAT91C_PIOC_OER            EQU (0xFFFFF810) ;- (PIOC) Output Enable Register\nAT91C_PIOC_PSR            EQU (0xFFFFF808) ;- (PIOC) PIO Status Register\nAT91C_PIOC_PER            EQU (0xFFFFF800) ;- (PIOC) PIO Enable Register\nAT91C_PIOC_BSR            EQU (0xFFFFF874) ;- (PIOC) Select B Register\nAT91C_PIOC_PPUER          EQU (0xFFFFF864) ;- (PIOC) Pull-up Enable Register\n;- ========== Register definition for PIOB peripheral ========== \nAT91C_PIOB_OWSR           EQU (0xFFFFF6A8) ;- (PIOB) Output Write Status Register\nAT91C_PIOB_PPUSR          EQU (0xFFFFF668) ;- (PIOB) Pad Pull-up Status Register\nAT91C_PIOB_PPUDR          EQU (0xFFFFF660) ;- (PIOB) Pull-up Disable Register\nAT91C_PIOB_MDSR           EQU (0xFFFFF658) ;- (PIOB) Multi-driver Status Register\nAT91C_PIOB_MDER           EQU (0xFFFFF650) ;- (PIOB) Multi-driver Enable Register\nAT91C_PIOB_IMR            EQU (0xFFFFF648) ;- (PIOB) Interrupt Mask Register\nAT91C_PIOB_OSR            EQU (0xFFFFF618) ;- (PIOB) Output Status Register\nAT91C_PIOB_OER            EQU (0xFFFFF610) ;- (PIOB) Output Enable Register\nAT91C_PIOB_PSR            EQU (0xFFFFF608) ;- (PIOB) PIO Status Register\nAT91C_PIOB_PER            EQU (0xFFFFF600) ;- (PIOB) PIO Enable Register\nAT91C_PIOB_BSR            EQU (0xFFFFF674) ;- (PIOB) Select B Register\nAT91C_PIOB_PPUER          EQU (0xFFFFF664) ;- (PIOB) Pull-up Enable Register\nAT91C_PIOB_IFDR           EQU (0xFFFFF624) ;- (PIOB) Input Filter Disable Register\nAT91C_PIOB_ODR            EQU (0xFFFFF614) ;- (PIOB) Output Disable Registerr\nAT91C_PIOB_ABSR           EQU (0xFFFFF678) ;- (PIOB) AB Select Status Register\nAT91C_PIOB_ASR            EQU (0xFFFFF670) ;- (PIOB) Select A Register\nAT91C_PIOB_IFER           EQU (0xFFFFF620) ;- (PIOB) Input Filter Enable Register\nAT91C_PIOB_IFSR           EQU (0xFFFFF628) ;- (PIOB) Input Filter Status Register\nAT91C_PIOB_SODR           EQU (0xFFFFF630) ;- (PIOB) Set Output Data Register\nAT91C_PIOB_ODSR           EQU (0xFFFFF638) ;- (PIOB) Output Data Status Register\nAT91C_PIOB_CODR           EQU (0xFFFFF634) ;- (PIOB) Clear Output Data Register\nAT91C_PIOB_PDSR           EQU (0xFFFFF63C) ;- (PIOB) Pin Data Status Register\nAT91C_PIOB_OWER           EQU (0xFFFFF6A0) ;- (PIOB) Output Write Enable Register\nAT91C_PIOB_IER            EQU (0xFFFFF640) ;- (PIOB) Interrupt Enable Register\nAT91C_PIOB_OWDR           EQU (0xFFFFF6A4) ;- (PIOB) Output Write Disable Register\nAT91C_PIOB_MDDR           EQU (0xFFFFF654) ;- (PIOB) Multi-driver Disable Register\nAT91C_PIOB_ISR            EQU (0xFFFFF64C) ;- (PIOB) Interrupt Status Register\nAT91C_PIOB_IDR            EQU (0xFFFFF644) ;- (PIOB) Interrupt Disable Register\nAT91C_PIOB_PDR            EQU (0xFFFFF604) ;- (PIOB) PIO Disable Register\n;- ========== Register definition for PIOA peripheral ========== \nAT91C_PIOA_IMR            EQU (0xFFFFF448) ;- (PIOA) Interrupt Mask Register\nAT91C_PIOA_IER            EQU (0xFFFFF440) ;- (PIOA) Interrupt Enable Register\nAT91C_PIOA_OWDR           EQU (0xFFFFF4A4) ;- (PIOA) Output Write Disable Register\nAT91C_PIOA_ISR            EQU (0xFFFFF44C) ;- (PIOA) Interrupt Status Register\nAT91C_PIOA_PPUDR          EQU (0xFFFFF460) ;- (PIOA) Pull-up Disable Register\nAT91C_PIOA_MDSR           EQU (0xFFFFF458) ;- (PIOA) Multi-driver Status Register\nAT91C_PIOA_MDER           EQU (0xFFFFF450) ;- (PIOA) Multi-driver Enable Register\nAT91C_PIOA_PER            EQU (0xFFFFF400) ;- (PIOA) PIO Enable Register\nAT91C_PIOA_PSR            EQU (0xFFFFF408) ;- (PIOA) PIO Status Register\nAT91C_PIOA_OER            EQU (0xFFFFF410) ;- (PIOA) Output Enable Register\nAT91C_PIOA_BSR            EQU (0xFFFFF474) ;- (PIOA) Select B Register\nAT91C_PIOA_PPUER          EQU (0xFFFFF464) ;- (PIOA) Pull-up Enable Register\nAT91C_PIOA_MDDR           EQU (0xFFFFF454) ;- (PIOA) Multi-driver Disable Register\nAT91C_PIOA_PDR            EQU (0xFFFFF404) ;- (PIOA) PIO Disable Register\nAT91C_PIOA_ODR            EQU (0xFFFFF414) ;- (PIOA) Output Disable Registerr\nAT91C_PIOA_IFDR           EQU (0xFFFFF424) ;- (PIOA) Input Filter Disable Register\nAT91C_PIOA_ABSR           EQU (0xFFFFF478) ;- (PIOA) AB Select Status Register\nAT91C_PIOA_ASR            EQU (0xFFFFF470) ;- (PIOA) Select A Register\nAT91C_PIOA_PPUSR          EQU (0xFFFFF468) ;- (PIOA) Pad Pull-up Status Register\nAT91C_PIOA_ODSR           EQU (0xFFFFF438) ;- (PIOA) Output Data Status Register\nAT91C_PIOA_SODR           EQU (0xFFFFF430) ;- (PIOA) Set Output Data Register\nAT91C_PIOA_IFSR           EQU (0xFFFFF428) ;- (PIOA) Input Filter Status Register\nAT91C_PIOA_IFER           EQU (0xFFFFF420) ;- (PIOA) Input Filter Enable Register\nAT91C_PIOA_OSR            EQU (0xFFFFF418) ;- (PIOA) Output Status Register\nAT91C_PIOA_IDR            EQU (0xFFFFF444) ;- (PIOA) Interrupt Disable Register\nAT91C_PIOA_PDSR           EQU (0xFFFFF43C) ;- (PIOA) Pin Data Status Register\nAT91C_PIOA_CODR           EQU (0xFFFFF434) ;- (PIOA) Clear Output Data Register\nAT91C_PIOA_OWSR           EQU (0xFFFFF4A8) ;- (PIOA) Output Write Status Register\nAT91C_PIOA_OWER           EQU (0xFFFFF4A0) ;- (PIOA) Output Write Enable Register\n;- ========== Register definition for DBGU peripheral ========== \nAT91C_DBGU_C2R            EQU (0xFFFFF244) ;- (DBGU) Chip ID2 Register\nAT91C_DBGU_THR            EQU (0xFFFFF21C) ;- (DBGU) Transmitter Holding Register\nAT91C_DBGU_CSR            EQU (0xFFFFF214) ;- (DBGU) Channel Status Register\nAT91C_DBGU_IDR            EQU (0xFFFFF20C) ;- (DBGU) Interrupt Disable Register\nAT91C_DBGU_MR             EQU (0xFFFFF204) ;- (DBGU) Mode Register\nAT91C_DBGU_FNTR           EQU (0xFFFFF248) ;- (DBGU) Force NTRST Register\nAT91C_DBGU_C1R            EQU (0xFFFFF240) ;- (DBGU) Chip ID1 Register\nAT91C_DBGU_BRGR           EQU (0xFFFFF220) ;- (DBGU) Baud Rate Generator Register\nAT91C_DBGU_RHR            EQU (0xFFFFF218) ;- (DBGU) Receiver Holding Register\nAT91C_DBGU_IMR            EQU (0xFFFFF210) ;- (DBGU) Interrupt Mask Register\nAT91C_DBGU_IER            EQU (0xFFFFF208) ;- (DBGU) Interrupt Enable Register\nAT91C_DBGU_CR             EQU (0xFFFFF200) ;- (DBGU) Control Register\n;- ========== Register definition for PDC_DBGU peripheral ========== \nAT91C_DBGU_TNCR           EQU (0xFFFFF31C) ;- (PDC_DBGU) Transmit Next Counter Register\nAT91C_DBGU_RNCR           EQU (0xFFFFF314) ;- (PDC_DBGU) Receive Next Counter Register\nAT91C_DBGU_PTCR           EQU (0xFFFFF320) ;- (PDC_DBGU) PDC Transfer Control Register\nAT91C_DBGU_PTSR           EQU (0xFFFFF324) ;- (PDC_DBGU) PDC Transfer Status Register\nAT91C_DBGU_RCR            EQU (0xFFFFF304) ;- (PDC_DBGU) Receive Counter Register\nAT91C_DBGU_TCR            EQU (0xFFFFF30C) ;- (PDC_DBGU) Transmit Counter Register\nAT91C_DBGU_RPR            EQU (0xFFFFF300) ;- (PDC_DBGU) Receive Pointer Register\nAT91C_DBGU_TPR            EQU (0xFFFFF308) ;- (PDC_DBGU) Transmit Pointer Register\nAT91C_DBGU_RNPR           EQU (0xFFFFF310) ;- (PDC_DBGU) Receive Next Pointer Register\nAT91C_DBGU_TNPR           EQU (0xFFFFF318) ;- (PDC_DBGU) Transmit Next Pointer Register\n;- ========== Register definition for AIC peripheral ========== \nAT91C_AIC_ICCR            EQU (0xFFFFF128) ;- (AIC) Interrupt Clear Command Register\nAT91C_AIC_IECR            EQU (0xFFFFF120) ;- (AIC) Interrupt Enable Command Register\nAT91C_AIC_SMR             EQU (0xFFFFF000) ;- (AIC) Source Mode Register\nAT91C_AIC_ISCR            EQU (0xFFFFF12C) ;- (AIC) Interrupt Set Command Register\nAT91C_AIC_EOICR           EQU (0xFFFFF130) ;- (AIC) End of Interrupt Command Register\nAT91C_AIC_DCR             EQU (0xFFFFF138) ;- (AIC) Debug Control Register (Protect)\nAT91C_AIC_FFER            EQU (0xFFFFF140) ;- (AIC) Fast Forcing Enable Register\nAT91C_AIC_SVR             EQU (0xFFFFF080) ;- (AIC) Source Vector Register\nAT91C_AIC_SPU             EQU (0xFFFFF134) ;- (AIC) Spurious Vector Register\nAT91C_AIC_FFDR            EQU (0xFFFFF144) ;- (AIC) Fast Forcing Disable Register\nAT91C_AIC_FVR             EQU (0xFFFFF104) ;- (AIC) FIQ Vector Register\nAT91C_AIC_FFSR            EQU (0xFFFFF148) ;- (AIC) Fast Forcing Status Register\nAT91C_AIC_IMR             EQU (0xFFFFF110) ;- (AIC) Interrupt Mask Register\nAT91C_AIC_ISR             EQU (0xFFFFF108) ;- (AIC) Interrupt Status Register\nAT91C_AIC_IVR             EQU (0xFFFFF100) ;- (AIC) IRQ Vector Register\nAT91C_AIC_IDCR            EQU (0xFFFFF124) ;- (AIC) Interrupt Disable Command Register\nAT91C_AIC_CISR            EQU (0xFFFFF114) ;- (AIC) Core Interrupt Status Register\nAT91C_AIC_IPR             EQU (0xFFFFF10C) ;- (AIC) Interrupt Pending Register\n;- ========== Register definition for PDC_SPI peripheral ========== \nAT91C_SPI_PTCR            EQU (0xFFFE0120) ;- (PDC_SPI) PDC Transfer Control Register\nAT91C_SPI_TNPR            EQU (0xFFFE0118) ;- (PDC_SPI) Transmit Next Pointer Register\nAT91C_SPI_RNPR            EQU (0xFFFE0110) ;- (PDC_SPI) Receive Next Pointer Register\nAT91C_SPI_TPR             EQU (0xFFFE0108) ;- (PDC_SPI) Transmit Pointer Register\nAT91C_SPI_RPR             EQU (0xFFFE0100) ;- (PDC_SPI) Receive Pointer Register\nAT91C_SPI_PTSR            EQU (0xFFFE0124) ;- (PDC_SPI) PDC Transfer Status Register\nAT91C_SPI_TNCR            EQU (0xFFFE011C) ;- (PDC_SPI) Transmit Next Counter Register\nAT91C_SPI_RNCR            EQU (0xFFFE0114) ;- (PDC_SPI) Receive Next Counter Register\nAT91C_SPI_TCR             EQU (0xFFFE010C) ;- (PDC_SPI) Transmit Counter Register\nAT91C_SPI_RCR             EQU (0xFFFE0104) ;- (PDC_SPI) Receive Counter Register\n;- ========== Register definition for SPI peripheral ========== \nAT91C_SPI_CSR             EQU (0xFFFE0030) ;- (SPI) Chip Select Register\nAT91C_SPI_IDR             EQU (0xFFFE0018) ;- (SPI) Interrupt Disable Register\nAT91C_SPI_SR              EQU (0xFFFE0010) ;- (SPI) Status Register\nAT91C_SPI_RDR             EQU (0xFFFE0008) ;- (SPI) Receive Data Register\nAT91C_SPI_CR              EQU (0xFFFE0000) ;- (SPI) Control Register\nAT91C_SPI_IMR             EQU (0xFFFE001C) ;- (SPI) Interrupt Mask Register\nAT91C_SPI_IER             EQU (0xFFFE0014) ;- (SPI) Interrupt Enable Register\nAT91C_SPI_TDR             EQU (0xFFFE000C) ;- (SPI) Transmit Data Register\nAT91C_SPI_MR              EQU (0xFFFE0004) ;- (SPI) Mode Register\n;- ========== Register definition for PDC_SSC2 peripheral ========== \nAT91C_SSC2_PTCR           EQU (0xFFFD8120) ;- (PDC_SSC2) PDC Transfer Control Register\nAT91C_SSC2_TNPR           EQU (0xFFFD8118) ;- (PDC_SSC2) Transmit Next Pointer Register\nAT91C_SSC2_RNPR           EQU (0xFFFD8110) ;- (PDC_SSC2) Receive Next Pointer Register\nAT91C_SSC2_TPR            EQU (0xFFFD8108) ;- (PDC_SSC2) Transmit Pointer Register\nAT91C_SSC2_RPR            EQU (0xFFFD8100) ;- (PDC_SSC2) Receive Pointer Register\nAT91C_SSC2_PTSR           EQU (0xFFFD8124) ;- (PDC_SSC2) PDC Transfer Status Register\nAT91C_SSC2_TNCR           EQU (0xFFFD811C) ;- (PDC_SSC2) Transmit Next Counter Register\nAT91C_SSC2_RNCR           EQU (0xFFFD8114) ;- (PDC_SSC2) Receive Next Counter Register\nAT91C_SSC2_TCR            EQU (0xFFFD810C) ;- (PDC_SSC2) Transmit Counter Register\nAT91C_SSC2_RCR            EQU (0xFFFD8104) ;- (PDC_SSC2) Receive Counter Register\n;- ========== Register definition for SSC2 peripheral ========== \nAT91C_SSC2_IMR            EQU (0xFFFD804C) ;- (SSC2) Interrupt Mask Register\nAT91C_SSC2_IER            EQU (0xFFFD8044) ;- (SSC2) Interrupt Enable Register\nAT91C_SSC2_RC1R           EQU (0xFFFD803C) ;- (SSC2) Receive Compare 1 Register\nAT91C_SSC2_TSHR           EQU (0xFFFD8034) ;- (SSC2) Transmit Sync Holding Register\nAT91C_SSC2_CMR            EQU (0xFFFD8004) ;- (SSC2) Clock Mode Register\nAT91C_SSC2_IDR            EQU (0xFFFD8048) ;- (SSC2) Interrupt Disable Register\nAT91C_SSC2_TCMR           EQU (0xFFFD8018) ;- (SSC2) Transmit Clock Mode Register\nAT91C_SSC2_RCMR           EQU (0xFFFD8010) ;- (SSC2) Receive Clock ModeRegister\nAT91C_SSC2_CR             EQU (0xFFFD8000) ;- (SSC2) Control Register\nAT91C_SSC2_RFMR           EQU (0xFFFD8014) ;- (SSC2) Receive Frame Mode Register\nAT91C_SSC2_TFMR           EQU (0xFFFD801C) ;- (SSC2) Transmit Frame Mode Register\nAT91C_SSC2_THR            EQU (0xFFFD8024) ;- (SSC2) Transmit Holding Register\nAT91C_SSC2_SR             EQU (0xFFFD8040) ;- (SSC2) Status Register\nAT91C_SSC2_RC0R           EQU (0xFFFD8038) ;- (SSC2) Receive Compare 0 Register\nAT91C_SSC2_RSHR           EQU (0xFFFD8030) ;- (SSC2) Receive Sync Holding Register\nAT91C_SSC2_RHR            EQU (0xFFFD8020) ;- (SSC2) Receive Holding Register\n;- ========== Register definition for PDC_SSC1 peripheral ========== \nAT91C_SSC1_PTCR           EQU (0xFFFD4120) ;- (PDC_SSC1) PDC Transfer Control Register\nAT91C_SSC1_TNPR           EQU (0xFFFD4118) ;- (PDC_SSC1) Transmit Next Pointer Register\nAT91C_SSC1_RNPR           EQU (0xFFFD4110) ;- (PDC_SSC1) Receive Next Pointer Register\nAT91C_SSC1_TPR            EQU (0xFFFD4108) ;- (PDC_SSC1) Transmit Pointer Register\nAT91C_SSC1_RPR            EQU (0xFFFD4100) ;- (PDC_SSC1) Receive Pointer Register\nAT91C_SSC1_PTSR           EQU (0xFFFD4124) ;- (PDC_SSC1) PDC Transfer Status Register\nAT91C_SSC1_TNCR           EQU (0xFFFD411C) ;- (PDC_SSC1) Transmit Next Counter Register\nAT91C_SSC1_RNCR           EQU (0xFFFD4114) ;- (PDC_SSC1) Receive Next Counter Register\nAT91C_SSC1_TCR            EQU (0xFFFD410C) ;- (PDC_SSC1) Transmit Counter Register\nAT91C_SSC1_RCR            EQU (0xFFFD4104) ;- (PDC_SSC1) Receive Counter Register\n;- ========== Register definition for SSC1 peripheral ========== \nAT91C_SSC1_RFMR           EQU (0xFFFD4014) ;- (SSC1) Receive Frame Mode Register\nAT91C_SSC1_CMR            EQU (0xFFFD4004) ;- (SSC1) Clock Mode Register\nAT91C_SSC1_IDR            EQU (0xFFFD4048) ;- (SSC1) Interrupt Disable Register\nAT91C_SSC1_SR             EQU (0xFFFD4040) ;- (SSC1) Status Register\nAT91C_SSC1_RC0R           EQU (0xFFFD4038) ;- (SSC1) Receive Compare 0 Register\nAT91C_SSC1_RSHR           EQU (0xFFFD4030) ;- (SSC1) Receive Sync Holding Register\nAT91C_SSC1_RHR            EQU (0xFFFD4020) ;- (SSC1) Receive Holding Register\nAT91C_SSC1_TCMR           EQU (0xFFFD4018) ;- (SSC1) Transmit Clock Mode Register\nAT91C_SSC1_RCMR           EQU (0xFFFD4010) ;- (SSC1) Receive Clock ModeRegister\nAT91C_SSC1_CR             EQU (0xFFFD4000) ;- (SSC1) Control Register\nAT91C_SSC1_IMR            EQU (0xFFFD404C) ;- (SSC1) Interrupt Mask Register\nAT91C_SSC1_IER            EQU (0xFFFD4044) ;- (SSC1) Interrupt Enable Register\nAT91C_SSC1_RC1R           EQU (0xFFFD403C) ;- (SSC1) Receive Compare 1 Register\nAT91C_SSC1_TSHR           EQU (0xFFFD4034) ;- (SSC1) Transmit Sync Holding Register\nAT91C_SSC1_THR            EQU (0xFFFD4024) ;- (SSC1) Transmit Holding Register\nAT91C_SSC1_TFMR           EQU (0xFFFD401C) ;- (SSC1) Transmit Frame Mode Register\n;- ========== Register definition for PDC_SSC0 peripheral ========== \nAT91C_SSC0_PTCR           EQU (0xFFFD0120) ;- (PDC_SSC0) PDC Transfer Control Register\nAT91C_SSC0_TNPR           EQU (0xFFFD0118) ;- (PDC_SSC0) Transmit Next Pointer Register\nAT91C_SSC0_RNPR           EQU (0xFFFD0110) ;- (PDC_SSC0) Receive Next Pointer Register\nAT91C_SSC0_TPR            EQU (0xFFFD0108) ;- (PDC_SSC0) Transmit Pointer Register\nAT91C_SSC0_RPR            EQU (0xFFFD0100) ;- (PDC_SSC0) Receive Pointer Register\nAT91C_SSC0_PTSR           EQU (0xFFFD0124) ;- (PDC_SSC0) PDC Transfer Status Register\nAT91C_SSC0_TNCR           EQU (0xFFFD011C) ;- (PDC_SSC0) Transmit Next Counter Register\nAT91C_SSC0_RNCR           EQU (0xFFFD0114) ;- (PDC_SSC0) Receive Next Counter Register\nAT91C_SSC0_TCR            EQU (0xFFFD010C) ;- (PDC_SSC0) Transmit Counter Register\nAT91C_SSC0_RCR            EQU (0xFFFD0104) ;- (PDC_SSC0) Receive Counter Register\n;- ========== Register definition for SSC0 peripheral ========== \nAT91C_SSC0_IMR            EQU (0xFFFD004C) ;- (SSC0) Interrupt Mask Register\nAT91C_SSC0_IER            EQU (0xFFFD0044) ;- (SSC0) Interrupt Enable Register\nAT91C_SSC0_RC1R           EQU (0xFFFD003C) ;- (SSC0) Receive Compare 1 Register\nAT91C_SSC0_TSHR           EQU (0xFFFD0034) ;- (SSC0) Transmit Sync Holding Register\nAT91C_SSC0_THR            EQU (0xFFFD0024) ;- (SSC0) Transmit Holding Register\nAT91C_SSC0_TFMR           EQU (0xFFFD001C) ;- (SSC0) Transmit Frame Mode Register\nAT91C_SSC0_RFMR           EQU (0xFFFD0014) ;- (SSC0) Receive Frame Mode Register\nAT91C_SSC0_CMR            EQU (0xFFFD0004) ;- (SSC0) Clock Mode Register\nAT91C_SSC0_IDR            EQU (0xFFFD0048) ;- (SSC0) Interrupt Disable Register\nAT91C_SSC0_SR             EQU (0xFFFD0040) ;- (SSC0) Status Register\nAT91C_SSC0_RC0R           EQU (0xFFFD0038) ;- (SSC0) Receive Compare 0 Register\nAT91C_SSC0_RSHR           EQU (0xFFFD0030) ;- (SSC0) Receive Sync Holding Register\nAT91C_SSC0_RHR            EQU (0xFFFD0020) ;- (SSC0) Receive Holding Register\nAT91C_SSC0_TCMR           EQU (0xFFFD0018) ;- (SSC0) Transmit Clock Mode Register\nAT91C_SSC0_RCMR           EQU (0xFFFD0010) ;- (SSC0) Receive Clock ModeRegister\nAT91C_SSC0_CR             EQU (0xFFFD0000) ;- (SSC0) Control Register\n;- ========== Register definition for PDC_US3 peripheral ========== \nAT91C_US3_PTSR            EQU (0xFFFCC124) ;- (PDC_US3) PDC Transfer Status Register\nAT91C_US3_TNCR            EQU (0xFFFCC11C) ;- (PDC_US3) Transmit Next Counter Register\nAT91C_US3_RNCR            EQU (0xFFFCC114) ;- (PDC_US3) Receive Next Counter Register\nAT91C_US3_TCR             EQU (0xFFFCC10C) ;- (PDC_US3) Transmit Counter Register\nAT91C_US3_RCR             EQU (0xFFFCC104) ;- (PDC_US3) Receive Counter Register\nAT91C_US3_PTCR            EQU (0xFFFCC120) ;- (PDC_US3) PDC Transfer Control Register\nAT91C_US3_TNPR            EQU (0xFFFCC118) ;- (PDC_US3) Transmit Next Pointer Register\nAT91C_US3_RNPR            EQU (0xFFFCC110) ;- (PDC_US3) Receive Next Pointer Register\nAT91C_US3_TPR             EQU (0xFFFCC108) ;- (PDC_US3) Transmit Pointer Register\nAT91C_US3_RPR             EQU (0xFFFCC100) ;- (PDC_US3) Receive Pointer Register\n;- ========== Register definition for US3 peripheral ========== \nAT91C_US3_IF              EQU (0xFFFCC04C) ;- (US3) IRDA_FILTER Register\nAT91C_US3_NER             EQU (0xFFFCC044) ;- (US3) Nb Errors Register\nAT91C_US3_RTOR            EQU (0xFFFCC024) ;- (US3) Receiver Time-out Register\nAT91C_US3_THR             EQU (0xFFFCC01C) ;- (US3) Transmitter Holding Register\nAT91C_US3_CSR             EQU (0xFFFCC014) ;- (US3) Channel Status Register\nAT91C_US3_IDR             EQU (0xFFFCC00C) ;- (US3) Interrupt Disable Register\nAT91C_US3_MR              EQU (0xFFFCC004) ;- (US3) Mode Register\nAT91C_US3_XXR             EQU (0xFFFCC048) ;- (US3) XON_XOFF Register\nAT91C_US3_FIDI            EQU (0xFFFCC040) ;- (US3) FI_DI_Ratio Register\nAT91C_US3_TTGR            EQU (0xFFFCC028) ;- (US3) Transmitter Time-guard Register\nAT91C_US3_BRGR            EQU (0xFFFCC020) ;- (US3) Baud Rate Generator Register\nAT91C_US3_RHR             EQU (0xFFFCC018) ;- (US3) Receiver Holding Register\nAT91C_US3_IMR             EQU (0xFFFCC010) ;- (US3) Interrupt Mask Register\nAT91C_US3_IER             EQU (0xFFFCC008) ;- (US3) Interrupt Enable Register\nAT91C_US3_CR              EQU (0xFFFCC000) ;- (US3) Control Register\n;- ========== Register definition for PDC_US2 peripheral ========== \nAT91C_US2_PTSR            EQU (0xFFFC8124) ;- (PDC_US2) PDC Transfer Status Register\nAT91C_US2_TNCR            EQU (0xFFFC811C) ;- (PDC_US2) Transmit Next Counter Register\nAT91C_US2_RNCR            EQU (0xFFFC8114) ;- (PDC_US2) Receive Next Counter Register\nAT91C_US2_TCR             EQU (0xFFFC810C) ;- (PDC_US2) Transmit Counter Register\nAT91C_US2_PTCR            EQU (0xFFFC8120) ;- (PDC_US2) PDC Transfer Control Register\nAT91C_US2_RCR             EQU (0xFFFC8104) ;- (PDC_US2) Receive Counter Register\nAT91C_US2_TNPR            EQU (0xFFFC8118) ;- (PDC_US2) Transmit Next Pointer Register\nAT91C_US2_RPR             EQU (0xFFFC8100) ;- (PDC_US2) Receive Pointer Register\nAT91C_US2_TPR             EQU (0xFFFC8108) ;- (PDC_US2) Transmit Pointer Register\nAT91C_US2_RNPR            EQU (0xFFFC8110) ;- (PDC_US2) Receive Next Pointer Register\n;- ========== Register definition for US2 peripheral ========== \nAT91C_US2_XXR             EQU (0xFFFC8048) ;- (US2) XON_XOFF Register\nAT91C_US2_FIDI            EQU (0xFFFC8040) ;- (US2) FI_DI_Ratio Register\nAT91C_US2_TTGR            EQU (0xFFFC8028) ;- (US2) Transmitter Time-guard Register\nAT91C_US2_BRGR            EQU (0xFFFC8020) ;- (US2) Baud Rate Generator Register\nAT91C_US2_RHR             EQU (0xFFFC8018) ;- (US2) Receiver Holding Register\nAT91C_US2_IMR             EQU (0xFFFC8010) ;- (US2) Interrupt Mask Register\nAT91C_US2_IER             EQU (0xFFFC8008) ;- (US2) Interrupt Enable Register\nAT91C_US2_CR              EQU (0xFFFC8000) ;- (US2) Control Register\nAT91C_US2_IF              EQU (0xFFFC804C) ;- (US2) IRDA_FILTER Register\nAT91C_US2_NER             EQU (0xFFFC8044) ;- (US2) Nb Errors Register\nAT91C_US2_RTOR            EQU (0xFFFC8024) ;- (US2) Receiver Time-out Register\nAT91C_US2_THR             EQU (0xFFFC801C) ;- (US2) Transmitter Holding Register\nAT91C_US2_CSR             EQU (0xFFFC8014) ;- (US2) Channel Status Register\nAT91C_US2_IDR             EQU (0xFFFC800C) ;- (US2) Interrupt Disable Register\nAT91C_US2_MR              EQU (0xFFFC8004) ;- (US2) Mode Register\n;- ========== Register definition for PDC_US1 peripheral ========== \nAT91C_US1_PTSR            EQU (0xFFFC4124) ;- (PDC_US1) PDC Transfer Status Register\nAT91C_US1_TNCR            EQU (0xFFFC411C) ;- (PDC_US1) Transmit Next Counter Register\nAT91C_US1_RNCR            EQU (0xFFFC4114) ;- (PDC_US1) Receive Next Counter Register\nAT91C_US1_TCR             EQU (0xFFFC410C) ;- (PDC_US1) Transmit Counter Register\nAT91C_US1_RCR             EQU (0xFFFC4104) ;- (PDC_US1) Receive Counter Register\nAT91C_US1_PTCR            EQU (0xFFFC4120) ;- (PDC_US1) PDC Transfer Control Register\nAT91C_US1_TNPR            EQU (0xFFFC4118) ;- (PDC_US1) Transmit Next Pointer Register\nAT91C_US1_RNPR            EQU (0xFFFC4110) ;- (PDC_US1) Receive Next Pointer Register\nAT91C_US1_TPR             EQU (0xFFFC4108) ;- (PDC_US1) Transmit Pointer Register\nAT91C_US1_RPR             EQU (0xFFFC4100) ;- (PDC_US1) Receive Pointer Register\n;- ========== Register definition for US1 peripheral ========== \nAT91C_US1_XXR             EQU (0xFFFC4048) ;- (US1) XON_XOFF Register\nAT91C_US1_RHR             EQU (0xFFFC4018) ;- (US1) Receiver Holding Register\nAT91C_US1_IMR             EQU (0xFFFC4010) ;- (US1) Interrupt Mask Register\nAT91C_US1_IER             EQU (0xFFFC4008) ;- (US1) Interrupt Enable Register\nAT91C_US1_CR              EQU (0xFFFC4000) ;- (US1) Control Register\nAT91C_US1_RTOR            EQU (0xFFFC4024) ;- (US1) Receiver Time-out Register\nAT91C_US1_THR             EQU (0xFFFC401C) ;- (US1) Transmitter Holding Register\nAT91C_US1_CSR             EQU (0xFFFC4014) ;- (US1) Channel Status Register\nAT91C_US1_IDR             EQU (0xFFFC400C) ;- (US1) Interrupt Disable Register\nAT91C_US1_FIDI            EQU (0xFFFC4040) ;- (US1) FI_DI_Ratio Register\nAT91C_US1_BRGR            EQU (0xFFFC4020) ;- (US1) Baud Rate Generator Register\nAT91C_US1_TTGR            EQU (0xFFFC4028) ;- (US1) Transmitter Time-guard Register\nAT91C_US1_IF              EQU (0xFFFC404C) ;- (US1) IRDA_FILTER Register\nAT91C_US1_NER             EQU (0xFFFC4044) ;- (US1) Nb Errors Register\nAT91C_US1_MR              EQU (0xFFFC4004) ;- (US1) Mode Register\n;- ========== Register definition for PDC_US0 peripheral ========== \nAT91C_US0_PTCR            EQU (0xFFFC0120) ;- (PDC_US0) PDC Transfer Control Register\nAT91C_US0_TNPR            EQU (0xFFFC0118) ;- (PDC_US0) Transmit Next Pointer Register\nAT91C_US0_RNPR            EQU (0xFFFC0110) ;- (PDC_US0) Receive Next Pointer Register\nAT91C_US0_TPR             EQU (0xFFFC0108) ;- (PDC_US0) Transmit Pointer Register\nAT91C_US0_RPR             EQU (0xFFFC0100) ;- (PDC_US0) Receive Pointer Register\nAT91C_US0_PTSR            EQU (0xFFFC0124) ;- (PDC_US0) PDC Transfer Status Register\nAT91C_US0_TNCR            EQU (0xFFFC011C) ;- (PDC_US0) Transmit Next Counter Register\nAT91C_US0_RNCR            EQU (0xFFFC0114) ;- (PDC_US0) Receive Next Counter Register\nAT91C_US0_TCR             EQU (0xFFFC010C) ;- (PDC_US0) Transmit Counter Register\nAT91C_US0_RCR             EQU (0xFFFC0104) ;- (PDC_US0) Receive Counter Register\n;- ========== Register definition for US0 peripheral ========== \nAT91C_US0_TTGR            EQU (0xFFFC0028) ;- (US0) Transmitter Time-guard Register\nAT91C_US0_BRGR            EQU (0xFFFC0020) ;- (US0) Baud Rate Generator Register\nAT91C_US0_RHR             EQU (0xFFFC0018) ;- (US0) Receiver Holding Register\nAT91C_US0_IMR             EQU (0xFFFC0010) ;- (US0) Interrupt Mask Register\nAT91C_US0_NER             EQU (0xFFFC0044) ;- (US0) Nb Errors Register\nAT91C_US0_RTOR            EQU (0xFFFC0024) ;- (US0) Receiver Time-out Register\nAT91C_US0_XXR             EQU (0xFFFC0048) ;- (US0) XON_XOFF Register\nAT91C_US0_FIDI            EQU (0xFFFC0040) ;- (US0) FI_DI_Ratio Register\nAT91C_US0_CR              EQU (0xFFFC0000) ;- (US0) Control Register\nAT91C_US0_IER             EQU (0xFFFC0008) ;- (US0) Interrupt Enable Register\nAT91C_US0_IF              EQU (0xFFFC004C) ;- (US0) IRDA_FILTER Register\nAT91C_US0_MR              EQU (0xFFFC0004) ;- (US0) Mode Register\nAT91C_US0_IDR             EQU (0xFFFC000C) ;- (US0) Interrupt Disable Register\nAT91C_US0_CSR             EQU (0xFFFC0014) ;- (US0) Channel Status Register\nAT91C_US0_THR             EQU (0xFFFC001C) ;- (US0) Transmitter Holding Register\n;- ========== Register definition for TWI peripheral ========== \nAT91C_TWI_RHR             EQU (0xFFFB8030) ;- (TWI) Receive Holding Register\nAT91C_TWI_IDR             EQU (0xFFFB8028) ;- (TWI) Interrupt Disable Register\nAT91C_TWI_SR              EQU (0xFFFB8020) ;- (TWI) Status Register\nAT91C_TWI_CWGR            EQU (0xFFFB8010) ;- (TWI) Clock Waveform Generator Register\nAT91C_TWI_SMR             EQU (0xFFFB8008) ;- (TWI) Slave Mode Register\nAT91C_TWI_CR              EQU (0xFFFB8000) ;- (TWI) Control Register\nAT91C_TWI_THR             EQU (0xFFFB8034) ;- (TWI) Transmit Holding Register\nAT91C_TWI_IMR             EQU (0xFFFB802C) ;- (TWI) Interrupt Mask Register\nAT91C_TWI_IER             EQU (0xFFFB8024) ;- (TWI) Interrupt Enable Register\nAT91C_TWI_IADR            EQU (0xFFFB800C) ;- (TWI) Internal Address Register\nAT91C_TWI_MMR             EQU (0xFFFB8004) ;- (TWI) Master Mode Register\n;- ========== Register definition for PDC_MCI peripheral ========== \nAT91C_MCI_PTCR            EQU (0xFFFB4120) ;- (PDC_MCI) PDC Transfer Control Register\nAT91C_MCI_TNPR            EQU (0xFFFB4118) ;- (PDC_MCI) Transmit Next Pointer Register\nAT91C_MCI_RNPR            EQU (0xFFFB4110) ;- (PDC_MCI) Receive Next Pointer Register\nAT91C_MCI_TPR             EQU (0xFFFB4108) ;- (PDC_MCI) Transmit Pointer Register\nAT91C_MCI_RPR             EQU (0xFFFB4100) ;- (PDC_MCI) Receive Pointer Register\nAT91C_MCI_PTSR            EQU (0xFFFB4124) ;- (PDC_MCI) PDC Transfer Status Register\nAT91C_MCI_TNCR            EQU (0xFFFB411C) ;- (PDC_MCI) Transmit Next Counter Register\nAT91C_MCI_RNCR            EQU (0xFFFB4114) ;- (PDC_MCI) Receive Next Counter Register\nAT91C_MCI_TCR             EQU (0xFFFB410C) ;- (PDC_MCI) Transmit Counter Register\nAT91C_MCI_RCR             EQU (0xFFFB4104) ;- (PDC_MCI) Receive Counter Register\n;- ========== Register definition for MCI peripheral ========== \nAT91C_MCI_IDR             EQU (0xFFFB4048) ;- (MCI) MCI Interrupt Disable Register\nAT91C_MCI_SR              EQU (0xFFFB4040) ;- (MCI) MCI Status Register\nAT91C_MCI_RDR             EQU (0xFFFB4030) ;- (MCI) MCI Receive Data Register\nAT91C_MCI_RSPR            EQU (0xFFFB4020) ;- (MCI) MCI Response Register\nAT91C_MCI_ARGR            EQU (0xFFFB4010) ;- (MCI) MCI Argument Register\nAT91C_MCI_DTOR            EQU (0xFFFB4008) ;- (MCI) MCI Data Timeout Register\nAT91C_MCI_CR              EQU (0xFFFB4000) ;- (MCI) MCI Control Register\nAT91C_MCI_IMR             EQU (0xFFFB404C) ;- (MCI) MCI Interrupt Mask Register\nAT91C_MCI_IER             EQU (0xFFFB4044) ;- (MCI) MCI Interrupt Enable Register\nAT91C_MCI_TDR             EQU (0xFFFB4034) ;- (MCI) MCI Transmit Data Register\nAT91C_MCI_CMDR            EQU (0xFFFB4014) ;- (MCI) MCI Command Register\nAT91C_MCI_SDCR            EQU (0xFFFB400C) ;- (MCI) MCI SD Card Register\nAT91C_MCI_MR              EQU (0xFFFB4004) ;- (MCI) MCI Mode Register\n;- ========== Register definition for UDP peripheral ========== \nAT91C_UDP_ISR             EQU (0xFFFB001C) ;- (UDP) Interrupt Status Register\nAT91C_UDP_IDR             EQU (0xFFFB0014) ;- (UDP) Interrupt Disable Register\nAT91C_UDP_GLBSTATE        EQU (0xFFFB0004) ;- (UDP) Global State Register\nAT91C_UDP_FDR             EQU (0xFFFB0050) ;- (UDP) Endpoint FIFO Data Register\nAT91C_UDP_CSR             EQU (0xFFFB0030) ;- (UDP) Endpoint Control and Status Register\nAT91C_UDP_RSTEP           EQU (0xFFFB0028) ;- (UDP) Reset Endpoint Register\nAT91C_UDP_ICR             EQU (0xFFFB0020) ;- (UDP) Interrupt Clear Register\nAT91C_UDP_IMR             EQU (0xFFFB0018) ;- (UDP) Interrupt Mask Register\nAT91C_UDP_IER             EQU (0xFFFB0010) ;- (UDP) Interrupt Enable Register\nAT91C_UDP_FADDR           EQU (0xFFFB0008) ;- (UDP) Function Address Register\nAT91C_UDP_NUM             EQU (0xFFFB0000) ;- (UDP) Frame Number Register\n;- ========== Register definition for TC5 peripheral ========== \nAT91C_TC5_CMR             EQU (0xFFFA4084) ;- (TC5) Channel Mode Register\nAT91C_TC5_IDR             EQU (0xFFFA40A8) ;- (TC5) Interrupt Disable Register\nAT91C_TC5_SR              EQU (0xFFFA40A0) ;- (TC5) Status Register\nAT91C_TC5_RB              EQU (0xFFFA4098) ;- (TC5) Register B\nAT91C_TC5_CV              EQU (0xFFFA4090) ;- (TC5) Counter Value\nAT91C_TC5_CCR             EQU (0xFFFA4080) ;- (TC5) Channel Control Register\nAT91C_TC5_IMR             EQU (0xFFFA40AC) ;- (TC5) Interrupt Mask Register\nAT91C_TC5_IER             EQU (0xFFFA40A4) ;- (TC5) Interrupt Enable Register\nAT91C_TC5_RC              EQU (0xFFFA409C) ;- (TC5) Register C\nAT91C_TC5_RA              EQU (0xFFFA4094) ;- (TC5) Register A\n;- ========== Register definition for TC4 peripheral ========== \nAT91C_TC4_IMR             EQU (0xFFFA406C) ;- (TC4) Interrupt Mask Register\nAT91C_TC4_IER             EQU (0xFFFA4064) ;- (TC4) Interrupt Enable Register\nAT91C_TC4_RC              EQU (0xFFFA405C) ;- (TC4) Register C\nAT91C_TC4_RA              EQU (0xFFFA4054) ;- (TC4) Register A\nAT91C_TC4_CMR             EQU (0xFFFA4044) ;- (TC4) Channel Mode Register\nAT91C_TC4_IDR             EQU (0xFFFA4068) ;- (TC4) Interrupt Disable Register\nAT91C_TC4_SR              EQU (0xFFFA4060) ;- (TC4) Status Register\nAT91C_TC4_RB              EQU (0xFFFA4058) ;- (TC4) Register B\nAT91C_TC4_CV              EQU (0xFFFA4050) ;- (TC4) Counter Value\nAT91C_TC4_CCR             EQU (0xFFFA4040) ;- (TC4) Channel Control Register\n;- ========== Register definition for TC3 peripheral ========== \nAT91C_TC3_IMR             EQU (0xFFFA402C) ;- (TC3) Interrupt Mask Register\nAT91C_TC3_CV              EQU (0xFFFA4010) ;- (TC3) Counter Value\nAT91C_TC3_CCR             EQU (0xFFFA4000) ;- (TC3) Channel Control Register\nAT91C_TC3_IER             EQU (0xFFFA4024) ;- (TC3) Interrupt Enable Register\nAT91C_TC3_CMR             EQU (0xFFFA4004) ;- (TC3) Channel Mode Register\nAT91C_TC3_RA              EQU (0xFFFA4014) ;- (TC3) Register A\nAT91C_TC3_RC              EQU (0xFFFA401C) ;- (TC3) Register C\nAT91C_TC3_IDR             EQU (0xFFFA4028) ;- (TC3) Interrupt Disable Register\nAT91C_TC3_RB              EQU (0xFFFA4018) ;- (TC3) Register B\nAT91C_TC3_SR              EQU (0xFFFA4020) ;- (TC3) Status Register\n;- ========== Register definition for TCB1 peripheral ========== \nAT91C_TCB1_BCR            EQU (0xFFFA4140) ;- (TCB1) TC Block Control Register\nAT91C_TCB1_BMR            EQU (0xFFFA4144) ;- (TCB1) TC Block Mode Register\n;- ========== Register definition for TC2 peripheral ========== \nAT91C_TC2_IMR             EQU (0xFFFA00AC) ;- (TC2) Interrupt Mask Register\nAT91C_TC2_IER             EQU (0xFFFA00A4) ;- (TC2) Interrupt Enable Register\nAT91C_TC2_RC              EQU (0xFFFA009C) ;- (TC2) Register C\nAT91C_TC2_RA              EQU (0xFFFA0094) ;- (TC2) Register A\nAT91C_TC2_CMR             EQU (0xFFFA0084) ;- (TC2) Channel Mode Register\nAT91C_TC2_IDR             EQU (0xFFFA00A8) ;- (TC2) Interrupt Disable Register\nAT91C_TC2_SR              EQU (0xFFFA00A0) ;- (TC2) Status Register\nAT91C_TC2_RB              EQU (0xFFFA0098) ;- (TC2) Register B\nAT91C_TC2_CV              EQU (0xFFFA0090) ;- (TC2) Counter Value\nAT91C_TC2_CCR             EQU (0xFFFA0080) ;- (TC2) Channel Control Register\n;- ========== Register definition for TC1 peripheral ========== \nAT91C_TC1_IMR             EQU (0xFFFA006C) ;- (TC1) Interrupt Mask Register\nAT91C_TC1_IER             EQU (0xFFFA0064) ;- (TC1) Interrupt Enable Register\nAT91C_TC1_RC              EQU (0xFFFA005C) ;- (TC1) Register C\nAT91C_TC1_RA              EQU (0xFFFA0054) ;- (TC1) Register A\nAT91C_TC1_CMR             EQU (0xFFFA0044) ;- (TC1) Channel Mode Register\nAT91C_TC1_IDR             EQU (0xFFFA0068) ;- (TC1) Interrupt Disable Register\nAT91C_TC1_SR              EQU (0xFFFA0060) ;- (TC1) Status Register\nAT91C_TC1_RB              EQU (0xFFFA0058) ;- (TC1) Register B\nAT91C_TC1_CV              EQU (0xFFFA0050) ;- (TC1) Counter Value\nAT91C_TC1_CCR             EQU (0xFFFA0040) ;- (TC1) Channel Control Register\n;- ========== Register definition for TC0 peripheral ========== \nAT91C_TC0_IMR             EQU (0xFFFA002C) ;- (TC0) Interrupt Mask Register\nAT91C_TC0_IER             EQU (0xFFFA0024) ;- (TC0) Interrupt Enable Register\nAT91C_TC0_RC              EQU (0xFFFA001C) ;- (TC0) Register C\nAT91C_TC0_RA              EQU (0xFFFA0014) ;- (TC0) Register A\nAT91C_TC0_CMR             EQU (0xFFFA0004) ;- (TC0) Channel Mode Register\nAT91C_TC0_IDR             EQU (0xFFFA0028) ;- (TC0) Interrupt Disable Register\nAT91C_TC0_SR              EQU (0xFFFA0020) ;- (TC0) Status Register\nAT91C_TC0_RB              EQU (0xFFFA0018) ;- (TC0) Register B\nAT91C_TC0_CV              EQU (0xFFFA0010) ;- (TC0) Counter Value\nAT91C_TC0_CCR             EQU (0xFFFA0000) ;- (TC0) Channel Control Register\n;- ========== Register definition for TCB0 peripheral ========== \nAT91C_TCB0_BMR            EQU (0xFFFA00C4) ;- (TCB0) TC Block Mode Register\nAT91C_TCB0_BCR            EQU (0xFFFA00C0) ;- (TCB0) TC Block Control Register\n;- ========== Register definition for UHP peripheral ========== \nAT91C_UHP_HcRhDescriptorA EQU (0x00300048) ;- (UHP) Root Hub characteristics A\nAT91C_UHP_HcRhPortStatus  EQU (0x00300054) ;- (UHP) Root Hub Port Status Register\nAT91C_UHP_HcRhDescriptorB EQU (0x0030004C) ;- (UHP) Root Hub characteristics B\nAT91C_UHP_HcControl       EQU (0x00300004) ;- (UHP) Operating modes for the Host Controller\nAT91C_UHP_HcInterruptStatus EQU (0x0030000C) ;- (UHP) Interrupt Status Register\nAT91C_UHP_HcRhStatus      EQU (0x00300050) ;- (UHP) Root Hub Status register\nAT91C_UHP_HcRevision      EQU (0x00300000) ;- (UHP) Revision\nAT91C_UHP_HcCommandStatus EQU (0x00300008) ;- (UHP) Command & status Register\nAT91C_UHP_HcInterruptEnable EQU (0x00300010) ;- (UHP) Interrupt Enable Register\nAT91C_UHP_HcHCCA          EQU (0x00300018) ;- (UHP) Pointer to the Host Controller Communication Area\nAT91C_UHP_HcControlHeadED EQU (0x00300020) ;- (UHP) First Endpoint Descriptor of the Control list\nAT91C_UHP_HcInterruptDisable EQU (0x00300014) ;- (UHP) Interrupt Disable Register\nAT91C_UHP_HcPeriodCurrentED EQU (0x0030001C) ;- (UHP) Current Isochronous or Interrupt Endpoint Descriptor\nAT91C_UHP_HcControlCurrentED EQU (0x00300024) ;- (UHP) Endpoint Control and Status Register\nAT91C_UHP_HcBulkCurrentED EQU (0x0030002C) ;- (UHP) Current endpoint of the Bulk list\nAT91C_UHP_HcFmInterval    EQU (0x00300034) ;- (UHP) Bit time between 2 consecutive SOFs\nAT91C_UHP_HcBulkHeadED    EQU (0x00300028) ;- (UHP) First endpoint register of the Bulk list\nAT91C_UHP_HcBulkDoneHead  EQU (0x00300030) ;- (UHP) Last completed transfer descriptor\nAT91C_UHP_HcFmRemaining   EQU (0x00300038) ;- (UHP) Bit time remaining in the current Frame\nAT91C_UHP_HcPeriodicStart EQU (0x00300040) ;- (UHP) Periodic Start\nAT91C_UHP_HcLSThreshold   EQU (0x00300044) ;- (UHP) LS Threshold\nAT91C_UHP_HcFmNumber      EQU (0x0030003C) ;- (UHP) Frame number\n;- ========== Register definition for EMAC peripheral ========== \nAT91C_EMAC_RSR            EQU (0xFFFBC020) ;- (EMAC) Receive Status Register\nAT91C_EMAC_MAN            EQU (0xFFFBC034) ;- (EMAC) PHY Maintenance Register\nAT91C_EMAC_HSH            EQU (0xFFFBC090) ;- (EMAC) Hash Address High[63:32]\nAT91C_EMAC_MCOL           EQU (0xFFFBC048) ;- (EMAC) Multiple Collision Frame Register\nAT91C_EMAC_IER            EQU (0xFFFBC028) ;- (EMAC) Interrupt Enable Register\nAT91C_EMAC_SA2H           EQU (0xFFFBC0A4) ;- (EMAC) Specific Address 2 High, Last 2 bytes\nAT91C_EMAC_HSL            EQU (0xFFFBC094) ;- (EMAC) Hash Address Low[31:0]\nAT91C_EMAC_LCOL           EQU (0xFFFBC05C) ;- (EMAC) Late Collision Register\nAT91C_EMAC_OK             EQU (0xFFFBC04C) ;- (EMAC) Frames Received OK Register\nAT91C_EMAC_CFG            EQU (0xFFFBC004) ;- (EMAC) Network Configuration Register\nAT91C_EMAC_SA3L           EQU (0xFFFBC0A8) ;- (EMAC) Specific Address 3 Low, First 4 bytes\nAT91C_EMAC_SEQE           EQU (0xFFFBC050) ;- (EMAC) Frame Check Sequence Error Register\nAT91C_EMAC_ECOL           EQU (0xFFFBC060) ;- (EMAC) Excessive Collision Register\nAT91C_EMAC_ELR            EQU (0xFFFBC070) ;- (EMAC) Excessive Length Error Register\nAT91C_EMAC_SR             EQU (0xFFFBC008) ;- (EMAC) Network Status Register\nAT91C_EMAC_RBQP           EQU (0xFFFBC018) ;- (EMAC) Receive Buffer Queue Pointer\nAT91C_EMAC_CSE            EQU (0xFFFBC064) ;- (EMAC) Carrier Sense Error Register\nAT91C_EMAC_RJB            EQU (0xFFFBC074) ;- (EMAC) Receive Jabber Register\nAT91C_EMAC_USF            EQU (0xFFFBC078) ;- (EMAC) Undersize Frame Register\nAT91C_EMAC_IDR            EQU (0xFFFBC02C) ;- (EMAC) Interrupt Disable Register\nAT91C_EMAC_SA1L           EQU (0xFFFBC098) ;- (EMAC) Specific Address 1 Low, First 4 bytes\nAT91C_EMAC_IMR            EQU (0xFFFBC030) ;- (EMAC) Interrupt Mask Register\nAT91C_EMAC_FRA            EQU (0xFFFBC040) ;- (EMAC) Frames Transmitted OK Register\nAT91C_EMAC_SA3H           EQU (0xFFFBC0AC) ;- (EMAC) Specific Address 3 High, Last 2 bytes\nAT91C_EMAC_SA1H           EQU (0xFFFBC09C) ;- (EMAC) Specific Address 1 High, Last 2 bytes\nAT91C_EMAC_SCOL           EQU (0xFFFBC044) ;- (EMAC) Single Collision Frame Register\nAT91C_EMAC_ALE            EQU (0xFFFBC054) ;- (EMAC) Alignment Error Register\nAT91C_EMAC_TAR            EQU (0xFFFBC00C) ;- (EMAC) Transmit Address Register\nAT91C_EMAC_SA4L           EQU (0xFFFBC0B0) ;- (EMAC) Specific Address 4 Low, First 4 bytes\nAT91C_EMAC_SA2L           EQU (0xFFFBC0A0) ;- (EMAC) Specific Address 2 Low, First 4 bytes\nAT91C_EMAC_TUE            EQU (0xFFFBC068) ;- (EMAC) Transmit Underrun Error Register\nAT91C_EMAC_DTE            EQU (0xFFFBC058) ;- (EMAC) Deferred Transmission Frame Register\nAT91C_EMAC_TCR            EQU (0xFFFBC010) ;- (EMAC) Transmit Control Register\nAT91C_EMAC_CTL            EQU (0xFFFBC000) ;- (EMAC) Network Control Register\nAT91C_EMAC_SA4H           EQU (0xFFFBC0B4) ;- (EMAC) Specific Address 4 High, Last 2 bytesr\nAT91C_EMAC_CDE            EQU (0xFFFBC06C) ;- (EMAC) Code Error Register\nAT91C_EMAC_SQEE           EQU (0xFFFBC07C) ;- (EMAC) SQE Test Error Register\nAT91C_EMAC_TSR            EQU (0xFFFBC014) ;- (EMAC) Transmit Status Register\nAT91C_EMAC_DRFC           EQU (0xFFFBC080) ;- (EMAC) Discarded RX Frame Register\n;- ========== Register definition for EBI peripheral ========== \nAT91C_EBI_CFGR            EQU (0xFFFFFF64) ;- (EBI) Configuration Register\nAT91C_EBI_CSA             EQU (0xFFFFFF60) ;- (EBI) Chip Select Assignment Register\n;- ========== Register definition for SMC2 peripheral ========== \nAT91C_SMC2_CSR            EQU (0xFFFFFF70) ;- (SMC2) SMC2 Chip Select Register\n;- ========== Register definition for SDRC peripheral ========== \nAT91C_SDRC_IMR            EQU (0xFFFFFFAC) ;- (SDRC) SDRAM Controller Interrupt Mask Register\nAT91C_SDRC_IER            EQU (0xFFFFFFA4) ;- (SDRC) SDRAM Controller Interrupt Enable Register\nAT91C_SDRC_SRR            EQU (0xFFFFFF9C) ;- (SDRC) SDRAM Controller Self Refresh Register\nAT91C_SDRC_TR             EQU (0xFFFFFF94) ;- (SDRC) SDRAM Controller Refresh Timer Register\nAT91C_SDRC_ISR            EQU (0xFFFFFFB0) ;- (SDRC) SDRAM Controller Interrupt Mask Register\nAT91C_SDRC_IDR            EQU (0xFFFFFFA8) ;- (SDRC) SDRAM Controller Interrupt Disable Register\nAT91C_SDRC_LPR            EQU (0xFFFFFFA0) ;- (SDRC) SDRAM Controller Low Power Register\nAT91C_SDRC_CR             EQU (0xFFFFFF98) ;- (SDRC) SDRAM Controller Configuration Register\nAT91C_SDRC_MR             EQU (0xFFFFFF90) ;- (SDRC) SDRAM Controller Mode Register\n;- ========== Register definition for BFC peripheral ========== \nAT91C_BFC_MR              EQU (0xFFFFFFC0) ;- (BFC) BFC Mode Register\n\n;- *****************************************************************************\n;-               PIO DEFINITIONS FOR AT91RM9200\n;- *****************************************************************************\nAT91C_PIO_PA0             EQU (1:SHL:0) ;- Pin Controlled by PA0\nAT91C_PA0_MISO            EQU (AT91C_PIO_PA0) ;-  SPI Master In Slave\nAT91C_PA0_PCK3            EQU (AT91C_PIO_PA0) ;-  PMC Programmable Clock Output 3\nAT91C_PIO_PA1             EQU (1:SHL:1) ;- Pin Controlled by PA1\nAT91C_PA1_MOSI            EQU (AT91C_PIO_PA1) ;-  SPI Master Out Slave\nAT91C_PA1_PCK0            EQU (AT91C_PIO_PA1) ;-  PMC Programmable Clock Output 0\nAT91C_PIO_PA10            EQU (1:SHL:10) ;- Pin Controlled by PA10\nAT91C_PA10_ETX1           EQU (AT91C_PIO_PA10) ;-  Ethernet MAC Transmit Data 1\nAT91C_PA10_MCDB1          EQU (AT91C_PIO_PA10) ;-  Multimedia Card B Data 1\nAT91C_PIO_PA11            EQU (1:SHL:11) ;- Pin Controlled by PA11\nAT91C_PA11_ECRS_ECRSDV    EQU (AT91C_PIO_PA11) ;-  Ethernet MAC Carrier Sense/Carrier Sense and Data Valid\nAT91C_PA11_MCDB2          EQU (AT91C_PIO_PA11) ;-  Multimedia Card B Data 2\nAT91C_PIO_PA12            EQU (1:SHL:12) ;- Pin Controlled by PA12\nAT91C_PA12_ERX0           EQU (AT91C_PIO_PA12) ;-  Ethernet MAC Receive Data 0\nAT91C_PA12_MCDB3          EQU (AT91C_PIO_PA12) ;-  Multimedia Card B Data 3\nAT91C_PIO_PA13            EQU (1:SHL:13) ;- Pin Controlled by PA13\nAT91C_PA13_ERX1           EQU (AT91C_PIO_PA13) ;-  Ethernet MAC Receive Data 1\nAT91C_PA13_TCLK0          EQU (AT91C_PIO_PA13) ;-  Timer Counter 0 external clock input\nAT91C_PIO_PA14            EQU (1:SHL:14) ;- Pin Controlled by PA14\nAT91C_PA14_ERXER          EQU (AT91C_PIO_PA14) ;-  Ethernet MAC Receive Error\nAT91C_PA14_TCLK1          EQU (AT91C_PIO_PA14) ;-  Timer Counter 1 external clock input\nAT91C_PIO_PA15            EQU (1:SHL:15) ;- Pin Controlled by PA15\nAT91C_PA15_EMDC           EQU (AT91C_PIO_PA15) ;-  Ethernet MAC Management Data Clock\nAT91C_PA15_TCLK2          EQU (AT91C_PIO_PA15) ;-  Timer Counter 2 external clock input\nAT91C_PIO_PA16            EQU (1:SHL:16) ;- Pin Controlled by PA16\nAT91C_PA16_EMDIO          EQU (AT91C_PIO_PA16) ;-  Ethernet MAC Management Data Input/Output\nAT91C_PA16_IRQ6           EQU (AT91C_PIO_PA16) ;-  AIC Interrupt input 6\nAT91C_PIO_PA17            EQU (1:SHL:17) ;- Pin Controlled by PA17\nAT91C_PA17_TXD0           EQU (AT91C_PIO_PA17) ;-  USART 0 Transmit Data\nAT91C_PA17_TIOA0          EQU (AT91C_PIO_PA17) ;-  Timer Counter 0 Multipurpose Timer I/O Pin A\nAT91C_PIO_PA18            EQU (1:SHL:18) ;- Pin Controlled by PA18\nAT91C_PA18_RXD0           EQU (AT91C_PIO_PA18) ;-  USART 0 Receive Data\nAT91C_PA18_TIOB0          EQU (AT91C_PIO_PA18) ;-  Timer Counter 0 Multipurpose Timer I/O Pin B\nAT91C_PIO_PA19            EQU (1:SHL:19) ;- Pin Controlled by PA19\nAT91C_PA19_SCK0           EQU (AT91C_PIO_PA19) ;-  USART 0 Serial Clock\nAT91C_PA19_TIOA1          EQU (AT91C_PIO_PA19) ;-  Timer Counter 1 Multipurpose Timer I/O Pin A\nAT91C_PIO_PA2             EQU (1:SHL:2) ;- Pin Controlled by PA2\nAT91C_PA2_SPCK            EQU (AT91C_PIO_PA2) ;-  SPI Serial Clock\nAT91C_PA2_IRQ4            EQU (AT91C_PIO_PA2) ;-  AIC Interrupt Input 4\nAT91C_PIO_PA20            EQU (1:SHL:20) ;- Pin Controlled by PA20\nAT91C_PA20_CTS0           EQU (AT91C_PIO_PA20) ;-  USART 0 Clear To Send\nAT91C_PA20_TIOB1          EQU (AT91C_PIO_PA20) ;-  Timer Counter 1 Multipurpose Timer I/O Pin B\nAT91C_PIO_PA21            EQU (1:SHL:21) ;- Pin Controlled by PA21\nAT91C_PA21_RTS0           EQU (AT91C_PIO_PA21) ;-  Usart 0 Ready To Send\nAT91C_PA21_TIOA2          EQU (AT91C_PIO_PA21) ;-  Timer Counter 2 Multipurpose Timer I/O Pin A\nAT91C_PIO_PA22            EQU (1:SHL:22) ;- Pin Controlled by PA22\nAT91C_PA22_RXD2           EQU (AT91C_PIO_PA22) ;-  USART 2 Receive Data\nAT91C_PA22_TIOB2          EQU (AT91C_PIO_PA22) ;-  Timer Counter 2 Multipurpose Timer I/O Pin B\nAT91C_PIO_PA23            EQU (1:SHL:23) ;- Pin Controlled by PA23\nAT91C_PA23_TXD2           EQU (AT91C_PIO_PA23) ;-  USART 2 Transmit Data\nAT91C_PA23_IRQ3           EQU (AT91C_PIO_PA23) ;-  Interrupt input 3\nAT91C_PIO_PA24            EQU (1:SHL:24) ;- Pin Controlled by PA24\nAT91C_PA24_SCK2           EQU (AT91C_PIO_PA24) ;-  USART2 Serial Clock\nAT91C_PA24_PCK1           EQU (AT91C_PIO_PA24) ;-  PMC Programmable Clock Output 1\nAT91C_PIO_PA25            EQU (1:SHL:25) ;- Pin Controlled by PA25\nAT91C_PA25_TWD            EQU (AT91C_PIO_PA25) ;-  TWI Two-wire Serial Data\nAT91C_PA25_IRQ2           EQU (AT91C_PIO_PA25) ;-  Interrupt input 2\nAT91C_PIO_PA26            EQU (1:SHL:26) ;- Pin Controlled by PA26\nAT91C_PA26_TWCK           EQU (AT91C_PIO_PA26) ;-  TWI Two-wire Serial Clock\nAT91C_PA26_IRQ1           EQU (AT91C_PIO_PA26) ;-  Interrupt input 1\nAT91C_PIO_PA27            EQU (1:SHL:27) ;- Pin Controlled by PA27\nAT91C_PA27_MCCK           EQU (AT91C_PIO_PA27) ;-  Multimedia Card Clock\nAT91C_PA27_TCLK3          EQU (AT91C_PIO_PA27) ;-  Timer Counter 3 External Clock Input\nAT91C_PIO_PA28            EQU (1:SHL:28) ;- Pin Controlled by PA28\nAT91C_PA28_MCCDA          EQU (AT91C_PIO_PA28) ;-  Multimedia Card A Command\nAT91C_PA28_TCLK4          EQU (AT91C_PIO_PA28) ;-  Timer Counter 4 external Clock Input\nAT91C_PIO_PA29            EQU (1:SHL:29) ;- Pin Controlled by PA29\nAT91C_PA29_MCDA0          EQU (AT91C_PIO_PA29) ;-  Multimedia Card A Data 0\nAT91C_PA29_TCLK5          EQU (AT91C_PIO_PA29) ;-  Timer Counter 5 external clock input\nAT91C_PIO_PA3             EQU (1:SHL:3) ;- Pin Controlled by PA3\nAT91C_PA3_NPCS0           EQU (AT91C_PIO_PA3) ;-  SPI Peripheral Chip Select 0\nAT91C_PA3_IRQ5            EQU (AT91C_PIO_PA3) ;-  AIC Interrupt Input 5\nAT91C_PIO_PA30            EQU (1:SHL:30) ;- Pin Controlled by PA30\nAT91C_PA30_DRXD           EQU (AT91C_PIO_PA30) ;-  DBGU Debug Receive Data\nAT91C_PA30_CTS2           EQU (AT91C_PIO_PA30) ;-  Usart 2 Clear To Send\nAT91C_PIO_PA31            EQU (1:SHL:31) ;- Pin Controlled by PA31\nAT91C_PA31_DTXD           EQU (AT91C_PIO_PA31) ;-  DBGU Debug Transmit Data\nAT91C_PA31_RTS2           EQU (AT91C_PIO_PA31) ;-  USART 2 Ready To Send\nAT91C_PIO_PA4             EQU (1:SHL:4) ;- Pin Controlled by PA4\nAT91C_PA4_NPCS1           EQU (AT91C_PIO_PA4) ;-  SPI Peripheral Chip Select 1\nAT91C_PA4_PCK1            EQU (AT91C_PIO_PA4) ;-  PMC Programmable Clock Output 1\nAT91C_PIO_PA5             EQU (1:SHL:5) ;- Pin Controlled by PA5\nAT91C_PA5_NPCS2           EQU (AT91C_PIO_PA5) ;-  SPI Peripheral Chip Select 2\nAT91C_PA5_TXD3            EQU (AT91C_PIO_PA5) ;-  USART 3 Transmit Data\nAT91C_PIO_PA6             EQU (1:SHL:6) ;- Pin Controlled by PA6\nAT91C_PA6_NPCS3           EQU (AT91C_PIO_PA6) ;-  SPI Peripheral Chip Select 3\nAT91C_PA6_RXD3            EQU (AT91C_PIO_PA6) ;-  USART 3 Receive Data\nAT91C_PIO_PA7             EQU (1:SHL:7) ;- Pin Controlled by PA7\nAT91C_PA7_ETXCK_EREFCK    EQU (AT91C_PIO_PA7) ;-  Ethernet MAC Transmit Clock/Reference Clock\nAT91C_PA7_PCK2            EQU (AT91C_PIO_PA7) ;-  PMC Programmable Clock 2\nAT91C_PIO_PA8             EQU (1:SHL:8) ;- Pin Controlled by PA8\nAT91C_PA8_ETXEN           EQU (AT91C_PIO_PA8) ;-  Ethernet MAC Transmit Enable\nAT91C_PA8_MCCDB           EQU (AT91C_PIO_PA8) ;-  Multimedia Card B Command\nAT91C_PIO_PA9             EQU (1:SHL:9) ;- Pin Controlled by PA9\nAT91C_PA9_ETX0            EQU (AT91C_PIO_PA9) ;-  Ethernet MAC Transmit Data 0\nAT91C_PA9_MCDB0           EQU (AT91C_PIO_PA9) ;-  Multimedia Card B Data 0\nAT91C_PIO_PB0             EQU (1:SHL:0) ;- Pin Controlled by PB0\nAT91C_PB0_TF0             EQU (AT91C_PIO_PB0) ;-  SSC Transmit Frame Sync 0\nAT91C_PB0_TIOB3           EQU (AT91C_PIO_PB0) ;-  Timer Counter 3 Multipurpose Timer I/O Pin B\nAT91C_PIO_PB1             EQU (1:SHL:1) ;- Pin Controlled by PB1\nAT91C_PB1_TK0             EQU (AT91C_PIO_PB1) ;-  SSC Transmit Clock 0\nAT91C_PB1_CTS3            EQU (AT91C_PIO_PB1) ;-  USART 3 Clear To Send\nAT91C_PIO_PB10            EQU (1:SHL:10) ;- Pin Controlled by PB10\nAT91C_PB10_RK1            EQU (AT91C_PIO_PB10) ;-  SSC Receive Clock 1\nAT91C_PB10_TIOA5          EQU (AT91C_PIO_PB10) ;-  Timer Counter 5 Multipurpose Timer I/O Pin A\nAT91C_PIO_PB11            EQU (1:SHL:11) ;- Pin Controlled by PB11\nAT91C_PB11_RF1            EQU (AT91C_PIO_PB11) ;-  SSC Receive Frame Sync 1\nAT91C_PB11_TIOB5          EQU (AT91C_PIO_PB11) ;-  Timer Counter 5 Multipurpose Timer I/O Pin B\nAT91C_PIO_PB12            EQU (1:SHL:12) ;- Pin Controlled by PB12\nAT91C_PB12_TF2            EQU (AT91C_PIO_PB12) ;-  SSC Transmit Frame Sync 2\nAT91C_PB12_ETX2           EQU (AT91C_PIO_PB12) ;-  Ethernet MAC Transmit Data 2\nAT91C_PIO_PB13            EQU (1:SHL:13) ;- Pin Controlled by PB13\nAT91C_PB13_TK2            EQU (AT91C_PIO_PB13) ;-  SSC Transmit Clock 2\nAT91C_PB13_ETX3           EQU (AT91C_PIO_PB13) ;-  Ethernet MAC Transmit Data 3\nAT91C_PIO_PB14            EQU (1:SHL:14) ;- Pin Controlled by PB14\nAT91C_PB14_TD2            EQU (AT91C_PIO_PB14) ;-  SSC Transmit Data 2\nAT91C_PB14_ETXER          EQU (AT91C_PIO_PB14) ;-  Ethernet MAC Transmikt Coding Error\nAT91C_PIO_PB15            EQU (1:SHL:15) ;- Pin Controlled by PB15\nAT91C_PB15_RD2            EQU (AT91C_PIO_PB15) ;-  SSC Receive Data 2\nAT91C_PB15_ERX2           EQU (AT91C_PIO_PB15) ;-  Ethernet MAC Receive Data 2\nAT91C_PIO_PB16            EQU (1:SHL:16) ;- Pin Controlled by PB16\nAT91C_PB16_RK2            EQU (AT91C_PIO_PB16) ;-  SSC Receive Clock 2\nAT91C_PB16_ERX3           EQU (AT91C_PIO_PB16) ;-  Ethernet MAC Receive Data 3\nAT91C_PIO_PB17            EQU (1:SHL:17) ;- Pin Controlled by PB17\nAT91C_PB17_RF2            EQU (AT91C_PIO_PB17) ;-  SSC Receive Frame Sync 2\nAT91C_PB17_ERXDV          EQU (AT91C_PIO_PB17) ;-  Ethernet MAC Receive Data Valid\nAT91C_PIO_PB18            EQU (1:SHL:18) ;- Pin Controlled by PB18\nAT91C_PB18_RI1            EQU (AT91C_PIO_PB18) ;-  USART 1 Ring Indicator\nAT91C_PB18_ECOL           EQU (AT91C_PIO_PB18) ;-  Ethernet MAC Collision Detected\nAT91C_PIO_PB19            EQU (1:SHL:19) ;- Pin Controlled by PB19\nAT91C_PB19_DTR1           EQU (AT91C_PIO_PB19) ;-  USART 1 Data Terminal ready\nAT91C_PB19_ERXCK          EQU (AT91C_PIO_PB19) ;-  Ethernet MAC Receive Clock\nAT91C_PIO_PB2             EQU (1:SHL:2) ;- Pin Controlled by PB2\nAT91C_PB2_TD0             EQU (AT91C_PIO_PB2) ;-  SSC Transmit data\nAT91C_PB2_SCK3            EQU (AT91C_PIO_PB2) ;-  USART 3 Serial Clock\nAT91C_PIO_PB20            EQU (1:SHL:20) ;- Pin Controlled by PB20\nAT91C_PB20_TXD1           EQU (AT91C_PIO_PB20) ;-  USART 1 Transmit Data\nAT91C_PIO_PB21            EQU (1:SHL:21) ;- Pin Controlled by PB21\nAT91C_PB21_RXD1           EQU (AT91C_PIO_PB21) ;-  USART 1 Receive Data\nAT91C_PIO_PB22            EQU (1:SHL:22) ;- Pin Controlled by PB22\nAT91C_PB22_SCK1           EQU (AT91C_PIO_PB22) ;-  USART1 Serial Clock\nAT91C_PIO_PB23            EQU (1:SHL:23) ;- Pin Controlled by PB23\nAT91C_PB23_DCD1           EQU (AT91C_PIO_PB23) ;-  USART 1 Data Carrier Detect\nAT91C_PIO_PB24            EQU (1:SHL:24) ;- Pin Controlled by PB24\nAT91C_PB24_CTS1           EQU (AT91C_PIO_PB24) ;-  USART 1 Clear To Send\nAT91C_PIO_PB25            EQU (1:SHL:25) ;- Pin Controlled by PB25\nAT91C_PB25_DSR1           EQU (AT91C_PIO_PB25) ;-  USART 1 Data Set ready\nAT91C_PB25_EF100          EQU (AT91C_PIO_PB25) ;-  Ethernet MAC Force 100 Mbits/sec\nAT91C_PIO_PB26            EQU (1:SHL:26) ;- Pin Controlled by PB26\nAT91C_PB26_RTS1           EQU (AT91C_PIO_PB26) ;-  Usart 0 Ready To Send\nAT91C_PIO_PB27            EQU (1:SHL:27) ;- Pin Controlled by PB27\nAT91C_PB27_PCK0           EQU (AT91C_PIO_PB27) ;-  PMC Programmable Clock Output 0\nAT91C_PIO_PB28            EQU (1:SHL:28) ;- Pin Controlled by PB28\nAT91C_PB28_FIQ            EQU (AT91C_PIO_PB28) ;-  AIC Fast Interrupt Input\nAT91C_PIO_PB29            EQU (1:SHL:29) ;- Pin Controlled by PB29\nAT91C_PB29_IRQ0           EQU (AT91C_PIO_PB29) ;-  Interrupt input 0\nAT91C_PIO_PB3             EQU (1:SHL:3) ;- Pin Controlled by PB3\nAT91C_PB3_RD0             EQU (AT91C_PIO_PB3) ;-  SSC Receive Data\nAT91C_PB3_MCDA1           EQU (AT91C_PIO_PB3) ;-  Multimedia Card A Data 1\nAT91C_PIO_PB4             EQU (1:SHL:4) ;- Pin Controlled by PB4\nAT91C_PB4_RK0             EQU (AT91C_PIO_PB4) ;-  SSC Receive Clock\nAT91C_PB4_MCDA2           EQU (AT91C_PIO_PB4) ;-  Multimedia Card A Data 2\nAT91C_PIO_PB5             EQU (1:SHL:5) ;- Pin Controlled by PB5\nAT91C_PB5_RF0             EQU (AT91C_PIO_PB5) ;-  SSC Receive Frame Sync 0\nAT91C_PB5_MCDA3           EQU (AT91C_PIO_PB5) ;-  Multimedia Card A Data 3\nAT91C_PIO_PB6             EQU (1:SHL:6) ;- Pin Controlled by PB6\nAT91C_PB6_TF1             EQU (AT91C_PIO_PB6) ;-  SSC Transmit Frame Sync 1\nAT91C_PB6_TIOA3           EQU (AT91C_PIO_PB6) ;-  Timer Counter 4 Multipurpose Timer I/O Pin A\nAT91C_PIO_PB7             EQU (1:SHL:7) ;- Pin Controlled by PB7\nAT91C_PB7_TK1             EQU (AT91C_PIO_PB7) ;-  SSC Transmit Clock 1\nAT91C_PB7_TIOB3           EQU (AT91C_PIO_PB7) ;-  Timer Counter 3 Multipurpose Timer I/O Pin B\nAT91C_PIO_PB8             EQU (1:SHL:8) ;- Pin Controlled by PB8\nAT91C_PB8_TD1             EQU (AT91C_PIO_PB8) ;-  SSC Transmit Data 1\nAT91C_PB8_TIOA4           EQU (AT91C_PIO_PB8) ;-  Timer Counter 4 Multipurpose Timer I/O Pin A\nAT91C_PIO_PB9             EQU (1:SHL:9) ;- Pin Controlled by PB9\nAT91C_PB9_RD1             EQU (AT91C_PIO_PB9) ;-  SSC Receive Data 1\nAT91C_PB9_TIOB4           EQU (AT91C_PIO_PB9) ;-  Timer Counter 4 Multipurpose Timer I/O Pin B\nAT91C_PIO_PC0             EQU (1:SHL:0) ;- Pin Controlled by PC0\nAT91C_PC0_BFCK            EQU (AT91C_PIO_PC0) ;-  Burst Flash Clock\nAT91C_PIO_PC1             EQU (1:SHL:1) ;- Pin Controlled by PC1\nAT91C_PC1_BFRDY_SMOE      EQU (AT91C_PIO_PC1) ;-  Burst Flash Ready\nAT91C_PIO_PC10            EQU (1:SHL:10) ;- Pin Controlled by PC10\nAT91C_PC10_NCS4_CFCS      EQU (AT91C_PIO_PC10) ;-  Compact Flash Chip Select\nAT91C_PIO_PC11            EQU (1:SHL:11) ;- Pin Controlled by PC11\nAT91C_PC11_NCS5_CFCE1     EQU (AT91C_PIO_PC11) ;-  Chip Select 5 / Compact Flash Chip Enable 1\nAT91C_PIO_PC12            EQU (1:SHL:12) ;- Pin Controlled by PC12\nAT91C_PC12_NCS6_CFCE2     EQU (AT91C_PIO_PC12) ;-  Chip Select 6 / Compact Flash Chip Enable 2\nAT91C_PIO_PC13            EQU (1:SHL:13) ;- Pin Controlled by PC13\nAT91C_PC13_NCS7           EQU (AT91C_PIO_PC13) ;-  Chip Select 7\nAT91C_PIO_PC14            EQU (1:SHL:14) ;- Pin Controlled by PC14\nAT91C_PIO_PC15            EQU (1:SHL:15) ;- Pin Controlled by PC15\nAT91C_PIO_PC16            EQU (1:SHL:16) ;- Pin Controlled by PC16\nAT91C_PC16_D16            EQU (AT91C_PIO_PC16) ;-  Data Bus [16]\nAT91C_PIO_PC17            EQU (1:SHL:17) ;- Pin Controlled by PC17\nAT91C_PC17_D17            EQU (AT91C_PIO_PC17) ;-  Data Bus [17]\nAT91C_PIO_PC18            EQU (1:SHL:18) ;- Pin Controlled by PC18\nAT91C_PC18_D18            EQU (AT91C_PIO_PC18) ;-  Data Bus [18]\nAT91C_PIO_PC19            EQU (1:SHL:19) ;- Pin Controlled by PC19\nAT91C_PC19_D19            EQU (AT91C_PIO_PC19) ;-  Data Bus [19]\nAT91C_PIO_PC2             EQU (1:SHL:2) ;- Pin Controlled by PC2\nAT91C_PC2_BFAVD           EQU (AT91C_PIO_PC2) ;-  Burst Flash Address Valid\nAT91C_PIO_PC20            EQU (1:SHL:20) ;- Pin Controlled by PC20\nAT91C_PC20_D20            EQU (AT91C_PIO_PC20) ;-  Data Bus [20]\nAT91C_PIO_PC21            EQU (1:SHL:21) ;- Pin Controlled by PC21\nAT91C_PC21_D21            EQU (AT91C_PIO_PC21) ;-  Data Bus [21]\nAT91C_PIO_PC22            EQU (1:SHL:22) ;- Pin Controlled by PC22\nAT91C_PC22_D22            EQU (AT91C_PIO_PC22) ;-  Data Bus [22]\nAT91C_PIO_PC23            EQU (1:SHL:23) ;- Pin Controlled by PC23\nAT91C_PC23_D23            EQU (AT91C_PIO_PC23) ;-  Data Bus [23]\nAT91C_PIO_PC24            EQU (1:SHL:24) ;- Pin Controlled by PC24\nAT91C_PC24_D24            EQU (AT91C_PIO_PC24) ;-  Data Bus [24]\nAT91C_PIO_PC25            EQU (1:SHL:25) ;- Pin Controlled by PC25\nAT91C_PC25_D25            EQU (AT91C_PIO_PC25) ;-  Data Bus [25]\nAT91C_PIO_PC26            EQU (1:SHL:26) ;- Pin Controlled by PC26\nAT91C_PC26_D26            EQU (AT91C_PIO_PC26) ;-  Data Bus [26]\nAT91C_PIO_PC27            EQU (1:SHL:27) ;- Pin Controlled by PC27\nAT91C_PC27_D27            EQU (AT91C_PIO_PC27) ;-  Data Bus [27]\nAT91C_PIO_PC28            EQU (1:SHL:28) ;- Pin Controlled by PC28\nAT91C_PC28_D28            EQU (AT91C_PIO_PC28) ;-  Data Bus [28]\nAT91C_PIO_PC29            EQU (1:SHL:29) ;- Pin Controlled by PC29\nAT91C_PC29_D29            EQU (AT91C_PIO_PC29) ;-  Data Bus [29]\nAT91C_PIO_PC3             EQU (1:SHL:3) ;- Pin Controlled by PC3\nAT91C_PC3_BFBAA_SMWE      EQU (AT91C_PIO_PC3) ;-  Burst Flash Address Advance / SmartMedia Write Enable\nAT91C_PIO_PC30            EQU (1:SHL:30) ;- Pin Controlled by PC30\nAT91C_PC30_D30            EQU (AT91C_PIO_PC30) ;-  Data Bus [30]\nAT91C_PIO_PC31            EQU (1:SHL:31) ;- Pin Controlled by PC31\nAT91C_PC31_D31            EQU (AT91C_PIO_PC31) ;-  Data Bus [31]\nAT91C_PIO_PC4             EQU (1:SHL:4) ;- Pin Controlled by PC4\nAT91C_PC4_BFOE            EQU (AT91C_PIO_PC4) ;-  Burst Flash Output Enable\nAT91C_PIO_PC5             EQU (1:SHL:5) ;- Pin Controlled by PC5\nAT91C_PC5_BFWE            EQU (AT91C_PIO_PC5) ;-  Burst Flash Write Enable\nAT91C_PIO_PC6             EQU (1:SHL:6) ;- Pin Controlled by PC6\nAT91C_PC6_NWAIT           EQU (AT91C_PIO_PC6) ;-  NWAIT\nAT91C_PIO_PC7             EQU (1:SHL:7) ;- Pin Controlled by PC7\nAT91C_PC7_A23             EQU (AT91C_PIO_PC7) ;-  Address Bus[23]\nAT91C_PIO_PC8             EQU (1:SHL:8) ;- Pin Controlled by PC8\nAT91C_PC8_A24             EQU (AT91C_PIO_PC8) ;-  Address Bus[24]\nAT91C_PIO_PC9             EQU (1:SHL:9) ;- Pin Controlled by PC9\nAT91C_PC9_A25_CFRNW       EQU (AT91C_PIO_PC9) ;-  Address Bus[25] /  Compact Flash Read Not Write\nAT91C_PIO_PD0             EQU (1:SHL:0) ;- Pin Controlled by PD0\nAT91C_PD0_ETX0            EQU (AT91C_PIO_PD0) ;-  Ethernet MAC Transmit Data 0\nAT91C_PIO_PD1             EQU (1:SHL:1) ;- Pin Controlled by PD1\nAT91C_PD1_ETX1            EQU (AT91C_PIO_PD1) ;-  Ethernet MAC Transmit Data 1\nAT91C_PIO_PD10            EQU (1:SHL:10) ;- Pin Controlled by PD10\nAT91C_PD10_PCK3           EQU (AT91C_PIO_PD10) ;-  PMC Programmable Clock Output 3\nAT91C_PD10_TPS1           EQU (AT91C_PIO_PD10) ;-  ETM ARM9 pipeline status 1\nAT91C_PIO_PD11            EQU (1:SHL:11) ;- Pin Controlled by PD11\nAT91C_PD11_               EQU (AT91C_PIO_PD11) ;-  \nAT91C_PD11_TPS2           EQU (AT91C_PIO_PD11) ;-  ETM ARM9 pipeline status 2\nAT91C_PIO_PD12            EQU (1:SHL:12) ;- Pin Controlled by PD12\nAT91C_PD12_               EQU (AT91C_PIO_PD12) ;-  \nAT91C_PD12_TPK0           EQU (AT91C_PIO_PD12) ;-  ETM Trace Packet 0\nAT91C_PIO_PD13            EQU (1:SHL:13) ;- Pin Controlled by PD13\nAT91C_PD13_               EQU (AT91C_PIO_PD13) ;-  \nAT91C_PD13_TPK1           EQU (AT91C_PIO_PD13) ;-  ETM Trace Packet 1\nAT91C_PIO_PD14            EQU (1:SHL:14) ;- Pin Controlled by PD14\nAT91C_PD14_               EQU (AT91C_PIO_PD14) ;-  \nAT91C_PD14_TPK2           EQU (AT91C_PIO_PD14) ;-  ETM Trace Packet 2\nAT91C_PIO_PD15            EQU (1:SHL:15) ;- Pin Controlled by PD15\nAT91C_PD15_TD0            EQU (AT91C_PIO_PD15) ;-  SSC Transmit data\nAT91C_PD15_TPK3           EQU (AT91C_PIO_PD15) ;-  ETM Trace Packet 3\nAT91C_PIO_PD16            EQU (1:SHL:16) ;- Pin Controlled by PD16\nAT91C_PD16_TD1            EQU (AT91C_PIO_PD16) ;-  SSC Transmit Data 1\nAT91C_PD16_TPK4           EQU (AT91C_PIO_PD16) ;-  ETM Trace Packet 4\nAT91C_PIO_PD17            EQU (1:SHL:17) ;- Pin Controlled by PD17\nAT91C_PD17_TD2            EQU (AT91C_PIO_PD17) ;-  SSC Transmit Data 2\nAT91C_PD17_TPK5           EQU (AT91C_PIO_PD17) ;-  ETM Trace Packet 5\nAT91C_PIO_PD18            EQU (1:SHL:18) ;- Pin Controlled by PD18\nAT91C_PD18_NPCS1          EQU (AT91C_PIO_PD18) ;-  SPI Peripheral Chip Select 1\nAT91C_PD18_TPK6           EQU (AT91C_PIO_PD18) ;-  ETM Trace Packet 6\nAT91C_PIO_PD19            EQU (1:SHL:19) ;- Pin Controlled by PD19\nAT91C_PD19_NPCS2          EQU (AT91C_PIO_PD19) ;-  SPI Peripheral Chip Select 2\nAT91C_PD19_TPK7           EQU (AT91C_PIO_PD19) ;-  ETM Trace Packet 7\nAT91C_PIO_PD2             EQU (1:SHL:2) ;- Pin Controlled by PD2\nAT91C_PD2_ETX2            EQU (AT91C_PIO_PD2) ;-  Ethernet MAC Transmit Data 2\nAT91C_PIO_PD20            EQU (1:SHL:20) ;- Pin Controlled by PD20\nAT91C_PD20_NPCS3          EQU (AT91C_PIO_PD20) ;-  SPI Peripheral Chip Select 3\nAT91C_PD20_TPK8           EQU (AT91C_PIO_PD20) ;-  ETM Trace Packet 8\nAT91C_PIO_PD21            EQU (1:SHL:21) ;- Pin Controlled by PD21\nAT91C_PD21_RTS0           EQU (AT91C_PIO_PD21) ;-  Usart 0 Ready To Send\nAT91C_PD21_TPK9           EQU (AT91C_PIO_PD21) ;-  ETM Trace Packet 9\nAT91C_PIO_PD22            EQU (1:SHL:22) ;- Pin Controlled by PD22\nAT91C_PD22_RTS1           EQU (AT91C_PIO_PD22) ;-  Usart 0 Ready To Send\nAT91C_PD22_TPK10          EQU (AT91C_PIO_PD22) ;-  ETM Trace Packet 10\nAT91C_PIO_PD23            EQU (1:SHL:23) ;- Pin Controlled by PD23\nAT91C_PD23_RTS2           EQU (AT91C_PIO_PD23) ;-  USART 2 Ready To Send\nAT91C_PD23_TPK11          EQU (AT91C_PIO_PD23) ;-  ETM Trace Packet 11\nAT91C_PIO_PD24            EQU (1:SHL:24) ;- Pin Controlled by PD24\nAT91C_PD24_RTS3           EQU (AT91C_PIO_PD24) ;-  USART 3 Ready To Send\nAT91C_PD24_TPK12          EQU (AT91C_PIO_PD24) ;-  ETM Trace Packet 12\nAT91C_PIO_PD25            EQU (1:SHL:25) ;- Pin Controlled by PD25\nAT91C_PD25_DTR1           EQU (AT91C_PIO_PD25) ;-  USART 1 Data Terminal ready\nAT91C_PD25_TPK13          EQU (AT91C_PIO_PD25) ;-  ETM Trace Packet 13\nAT91C_PIO_PD26            EQU (1:SHL:26) ;- Pin Controlled by PD26\nAT91C_PD26_TPK14          EQU (AT91C_PIO_PD26) ;-  ETM Trace Packet 14\nAT91C_PIO_PD27            EQU (1:SHL:27) ;- Pin Controlled by PD27\nAT91C_PD27_TPK15          EQU (AT91C_PIO_PD27) ;-  ETM Trace Packet 15\nAT91C_PIO_PD3             EQU (1:SHL:3) ;- Pin Controlled by PD3\nAT91C_PD3_ETX3            EQU (AT91C_PIO_PD3) ;-  Ethernet MAC Transmit Data 3\nAT91C_PIO_PD4             EQU (1:SHL:4) ;- Pin Controlled by PD4\nAT91C_PD4_ETXEN           EQU (AT91C_PIO_PD4) ;-  Ethernet MAC Transmit Enable\nAT91C_PIO_PD5             EQU (1:SHL:5) ;- Pin Controlled by PD5\nAT91C_PD5_ETXER           EQU (AT91C_PIO_PD5) ;-  Ethernet MAC Transmikt Coding Error\nAT91C_PIO_PD6             EQU (1:SHL:6) ;- Pin Controlled by PD6\nAT91C_PD6_DTXD            EQU (AT91C_PIO_PD6) ;-  DBGU Debug Transmit Data\nAT91C_PIO_PD7             EQU (1:SHL:7) ;- Pin Controlled by PD7\nAT91C_PD7_PCK0            EQU (AT91C_PIO_PD7) ;-  PMC Programmable Clock Output 0\nAT91C_PD7_TSYNC           EQU (AT91C_PIO_PD7) ;-  ETM Synchronization signal\nAT91C_PIO_PD8             EQU (1:SHL:8) ;- Pin Controlled by PD8\nAT91C_PD8_PCK1            EQU (AT91C_PIO_PD8) ;-  PMC Programmable Clock Output 1\nAT91C_PD8_TCLK            EQU (AT91C_PIO_PD8) ;-  ETM Trace Clock signal\nAT91C_PIO_PD9             EQU (1:SHL:9) ;- Pin Controlled by PD9\nAT91C_PD9_PCK2            EQU (AT91C_PIO_PD9) ;-  PMC Programmable Clock 2\nAT91C_PD9_TPS0            EQU (AT91C_PIO_PD9) ;-  ETM ARM9 pipeline status 0\n\n;- *****************************************************************************\n;-               PERIPHERAL ID DEFINITIONS FOR AT91RM9200\n;- *****************************************************************************\nAT91C_ID_FIQ              EQU ( 0) ;- Advanced Interrupt Controller (FIQ)\nAT91C_ID_SYS              EQU ( 1) ;- System Peripheral\nAT91C_ID_PIOA             EQU ( 2) ;- Parallel IO Controller A \nAT91C_ID_PIOB             EQU ( 3) ;- Parallel IO Controller B\nAT91C_ID_PIOC             EQU ( 4) ;- Parallel IO Controller C\nAT91C_ID_PIOD             EQU ( 5) ;- Parallel IO Controller D\nAT91C_ID_US0              EQU ( 6) ;- USART 0\nAT91C_ID_US1              EQU ( 7) ;- USART 1\nAT91C_ID_US2              EQU ( 8) ;- USART 2\nAT91C_ID_US3              EQU ( 9) ;- USART 3\nAT91C_ID_MCI              EQU (10) ;- Multimedia Card Interface\nAT91C_ID_UDP              EQU (11) ;- USB Device Port\nAT91C_ID_TWI              EQU (12) ;- Two-Wire Interface\nAT91C_ID_SPI              EQU (13) ;- Serial Peripheral Interface\nAT91C_ID_SSC0             EQU (14) ;- Serial Synchronous Controller 0\nAT91C_ID_SSC1             EQU (15) ;- Serial Synchronous Controller 1\nAT91C_ID_SSC2             EQU (16) ;- Serial Synchronous Controller 2\nAT91C_ID_TC0              EQU (17) ;- Timer Counter 0\nAT91C_ID_TC1              EQU (18) ;- Timer Counter 1\nAT91C_ID_TC2              EQU (19) ;- Timer Counter 2\nAT91C_ID_TC3              EQU (20) ;- Timer Counter 3\nAT91C_ID_TC4              EQU (21) ;- Timer Counter 4\nAT91C_ID_TC5              EQU (22) ;- Timer Counter 5\nAT91C_ID_UHP              EQU (23) ;- USB Host port\nAT91C_ID_EMAC             EQU (24) ;- Ethernet MAC\nAT91C_ID_IRQ0             EQU (25) ;- Advanced Interrupt Controller (IRQ0)\nAT91C_ID_IRQ1             EQU (26) ;- Advanced Interrupt Controller (IRQ1)\nAT91C_ID_IRQ2             EQU (27) ;- Advanced Interrupt Controller (IRQ2)\nAT91C_ID_IRQ3             EQU (28) ;- Advanced Interrupt Controller (IRQ3)\nAT91C_ID_IRQ4             EQU (29) ;- Advanced Interrupt Controller (IRQ4)\nAT91C_ID_IRQ5             EQU (30) ;- Advanced Interrupt Controller (IRQ5)\nAT91C_ID_IRQ6             EQU (31) ;- Advanced Interrupt Controller (IRQ6)\n\n;- *****************************************************************************\n;-               BASE ADDRESS DEFINITIONS FOR AT91RM9200\n;- *****************************************************************************\nAT91C_BASE_SYS            EQU (0xFFFFF000) ;- (SYS) Base Address\nAT91C_BASE_MC             EQU (0xFFFFFF00) ;- (MC) Base Address\nAT91C_BASE_RTC            EQU (0xFFFFFE00) ;- (RTC) Base Address\nAT91C_BASE_ST             EQU (0xFFFFFD00) ;- (ST) Base Address\nAT91C_BASE_PMC            EQU (0xFFFFFC00) ;- (PMC) Base Address\nAT91C_BASE_CKGR           EQU (0xFFFFFC20) ;- (CKGR) Base Address\nAT91C_BASE_PIOD           EQU (0xFFFFFA00) ;- (PIOD) Base Address\nAT91C_BASE_PIOC           EQU (0xFFFFF800) ;- (PIOC) Base Address\nAT91C_BASE_PIOB           EQU (0xFFFFF600) ;- (PIOB) Base Address\nAT91C_BASE_PIOA           EQU (0xFFFFF400) ;- (PIOA) Base Address\nAT91C_BASE_DBGU           EQU (0xFFFFF200) ;- (DBGU) Base Address\nAT91C_BASE_PDC_DBGU       EQU (0xFFFFF300) ;- (PDC_DBGU) Base Address\nAT91C_BASE_AIC            EQU (0xFFFFF000) ;- (AIC) Base Address\nAT91C_BASE_PDC_SPI        EQU (0xFFFE0100) ;- (PDC_SPI) Base Address\nAT91C_BASE_SPI            EQU (0xFFFE0000) ;- (SPI) Base Address\nAT91C_BASE_PDC_SSC2       EQU (0xFFFD8100) ;- (PDC_SSC2) Base Address\nAT91C_BASE_SSC2           EQU (0xFFFD8000) ;- (SSC2) Base Address\nAT91C_BASE_PDC_SSC1       EQU (0xFFFD4100) ;- (PDC_SSC1) Base Address\nAT91C_BASE_SSC1           EQU (0xFFFD4000) ;- (SSC1) Base Address\nAT91C_BASE_PDC_SSC0       EQU (0xFFFD0100) ;- (PDC_SSC0) Base Address\nAT91C_BASE_SSC0           EQU (0xFFFD0000) ;- (SSC0) Base Address\nAT91C_BASE_PDC_US3        EQU (0xFFFCC100) ;- (PDC_US3) Base Address\nAT91C_BASE_US3            EQU (0xFFFCC000) ;- (US3) Base Address\nAT91C_BASE_PDC_US2        EQU (0xFFFC8100) ;- (PDC_US2) Base Address\nAT91C_BASE_US2            EQU (0xFFFC8000) ;- (US2) Base Address\nAT91C_BASE_PDC_US1        EQU (0xFFFC4100) ;- (PDC_US1) Base Address\nAT91C_BASE_US1            EQU (0xFFFC4000) ;- (US1) Base Address\nAT91C_BASE_PDC_US0        EQU (0xFFFC0100) ;- (PDC_US0) Base Address\nAT91C_BASE_US0            EQU (0xFFFC0000) ;- (US0) Base Address\nAT91C_BASE_TWI            EQU (0xFFFB8000) ;- (TWI) Base Address\nAT91C_BASE_PDC_MCI        EQU (0xFFFB4100) ;- (PDC_MCI) Base Address\nAT91C_BASE_MCI            EQU (0xFFFB4000) ;- (MCI) Base Address\nAT91C_BASE_UDP            EQU (0xFFFB0000) ;- (UDP) Base Address\nAT91C_BASE_TC5            EQU (0xFFFA4080) ;- (TC5) Base Address\nAT91C_BASE_TC4            EQU (0xFFFA4040) ;- (TC4) Base Address\nAT91C_BASE_TC3            EQU (0xFFFA4000) ;- (TC3) Base Address\nAT91C_BASE_TCB1           EQU (0xFFFA4080) ;- (TCB1) Base Address\nAT91C_BASE_TC2            EQU (0xFFFA0080) ;- (TC2) Base Address\nAT91C_BASE_TC1            EQU (0xFFFA0040) ;- (TC1) Base Address\nAT91C_BASE_TC0            EQU (0xFFFA0000) ;- (TC0) Base Address\nAT91C_BASE_TCB0           EQU (0xFFFA0000) ;- (TCB0) Base Address\nAT91C_BASE_UHP            EQU (0x00300000) ;- (UHP) Base Address\nAT91C_BASE_EMAC           EQU (0xFFFBC000) ;- (EMAC) Base Address\nAT91C_BASE_EBI            EQU (0xFFFFFF60) ;- (EBI) Base Address\nAT91C_BASE_SMC2           EQU (0xFFFFFF70) ;- (SMC2) Base Address\nAT91C_BASE_SDRC           EQU (0xFFFFFF90) ;- (SDRC) Base Address\nAT91C_BASE_BFC            EQU (0xFFFFFFC0) ;- (BFC) Base Address\n\n;- *****************************************************************************\n;-               MEMORY MAPPING DEFINITIONS FOR AT91RM9200\n;- *****************************************************************************\nAT91C_ISRAM               EQU (0x00200000) ;- Internal SRAM base address\nAT91C_ISRAM_SIZE          EQU (0x00004000) ;- Internal SRAM size in byte (16 Kbyte)\nAT91C_IROM                EQU (0x00100000) ;- Internal ROM base address\nAT91C_IROM_SIZE           EQU (0x00020000) ;- Internal ROM size in byte (128 Kbyte)\n\n\n\tEND\n"
  },
  {
    "path": "target/linux/at91/image/dfboot/src/include/AT91RM9200_inc.h",
    "content": "// ----------------------------------------------------------------------------\n//          ATMEL Microcontroller Software Support  -  ROUSSET  -\n// ----------------------------------------------------------------------------\n//  The software is delivered \"AS IS\" without warranty or condition of any\n//  kind, either express, implied or statutory. This includes without\n//  limitation any warranty or condition with respect to merchantability or\n//  fitness for any particular purpose, or against the infringements of\n//  intellectual property rights of others.\n// ----------------------------------------------------------------------------\n// File Name           : AT91RM9200.h\n// Object              : AT91RM9200 definitions\n// Generated           : AT91 SW Application Group  11/19/2003 (17:20:51)\n// \n// CVS Reference       : /AT91RM9200.pl/1.16/Fri Feb 07 10:29:51 2003//\n// CVS Reference       : /SYS_AT91RM9200.pl/1.2/Fri Jan 17 12:44:37 2003//\n// CVS Reference       : /MC_1760A.pl/1.1/Fri Aug 23 14:38:22 2002//\n// CVS Reference       : /AIC_1796B.pl/1.1.1.1/Fri Jun 28 09:36:47 2002//\n// CVS Reference       : /PMC_2636A.pl/1.1.1.1/Fri Jun 28 09:36:48 2002//\n// CVS Reference       : /ST_1763B.pl/1.1/Fri Aug 23 14:41:42 2002//\n// CVS Reference       : /RTC_1245D.pl/1.2/Fri Jan 31 12:19:06 2003//\n// CVS Reference       : /PIO_1725D.pl/1.1.1.1/Fri Jun 28 09:36:47 2002//\n// CVS Reference       : /DBGU_1754A.pl/1.4/Fri Jan 31 12:18:24 2003//\n// CVS Reference       : /UDP_1765B.pl/1.3/Fri Aug 02 14:45:38 2002//\n// CVS Reference       : /MCI_1764A.pl/1.2/Thu Nov 14 17:48:24 2002//\n// CVS Reference       : /US_1739C.pl/1.2/Fri Jul 12 07:49:25 2002//\n// CVS Reference       : /SPI_AT91RMxxxx.pl/1.3/Tue Nov 26 10:20:29 2002//\n// CVS Reference       : /SSC_1762A.pl/1.2/Fri Nov 08 13:26:39 2002//\n// CVS Reference       : /TC_1753B.pl/1.2/Fri Jan 31 12:19:55 2003//\n// CVS Reference       : /TWI_1761B.pl/1.4/Fri Feb 07 10:30:07 2003//\n// CVS Reference       : /PDC_1734B.pl/1.2/Thu Nov 21 16:38:23 2002//\n// CVS Reference       : /UHP_xxxxA.pl/1.1/Mon Jul 22 12:21:58 2002//\n// CVS Reference       : /EMAC_1794A.pl/1.4/Fri Jan 17 12:11:54 2003//\n// CVS Reference       : /EBI_1759B.pl/1.10/Fri Jan 17 12:44:29 2003//\n// CVS Reference       : /SMC_1783A.pl/1.3/Thu Oct 31 14:38:17 2002//\n// CVS Reference       : /SDRC_1758B.pl/1.2/Thu Oct 03 13:04:41 2002//\n// CVS Reference       : /BFC_1757B.pl/1.3/Thu Oct 31 14:38:00 2002//\n// ----------------------------------------------------------------------------\n\n// Hardware register definition\n\n// *****************************************************************************\n//              SOFTWARE API DEFINITION  FOR System Peripherals\n// *****************************************************************************\n\n// *****************************************************************************\n//              SOFTWARE API DEFINITION  FOR Memory Controller Interface\n// *****************************************************************************\n// *** Register offset in AT91S_MC structure ***\n#define MC_RCR          ( 0) // MC Remap Control Register\n#define MC_ASR          ( 4) // MC Abort Status Register\n#define MC_AASR         ( 8) // MC Abort Address Status Register\n#define MC_PUIA         (16) // MC Protection Unit Area\n#define MC_PUP          (80) // MC Protection Unit Peripherals\n#define MC_PUER         (84) // MC Protection Unit Enable Register\n// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- \n#define AT91C_MC_RCB              (0x1 <<  0) // (MC) Remap Command Bit\n// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- \n#define AT91C_MC_UNDADD           (0x1 <<  0) // (MC) Undefined Addess Abort Status\n#define AT91C_MC_MISADD           (0x1 <<  1) // (MC) Misaligned Addess Abort Status\n#define AT91C_MC_MPU              (0x1 <<  2) // (MC) Memory protection Unit Abort Status\n#define AT91C_MC_ABTSZ            (0x3 <<  8) // (MC) Abort Size Status\n#define \tAT91C_MC_ABTSZ_BYTE                 (0x0 <<  8) // (MC) Byte\n#define \tAT91C_MC_ABTSZ_HWORD                (0x1 <<  8) // (MC) Half-word\n#define \tAT91C_MC_ABTSZ_WORD                 (0x2 <<  8) // (MC) Word\n#define AT91C_MC_ABTTYP           (0x3 << 10) // (MC) Abort Type Status\n#define \tAT91C_MC_ABTTYP_DATAR                (0x0 << 10) // (MC) Data Read\n#define \tAT91C_MC_ABTTYP_DATAW                (0x1 << 10) // (MC) Data Write\n#define \tAT91C_MC_ABTTYP_FETCH                (0x2 << 10) // (MC) Code Fetch\n#define AT91C_MC_MST0             (0x1 << 16) // (MC) Master 0 Abort Source\n#define AT91C_MC_MST1             (0x1 << 17) // (MC) Master 1 Abort Source\n#define AT91C_MC_SVMST0           (0x1 << 24) // (MC) Saved Master 0 Abort Source\n#define AT91C_MC_SVMST1           (0x1 << 25) // (MC) Saved Master 1 Abort Source\n// -------- MC_PUIA : (MC Offset: 0x10) MC Protection Unit Area -------- \n#define AT91C_MC_PROT             (0x3 <<  0) // (MC) Protection\n#define \tAT91C_MC_PROT_PNAUNA               (0x0) // (MC) Privilege: No Access, User: No Access\n#define \tAT91C_MC_PROT_PRWUNA               (0x1) // (MC) Privilege: Read/Write, User: No Access\n#define \tAT91C_MC_PROT_PRWURO               (0x2) // (MC) Privilege: Read/Write, User: Read Only\n#define \tAT91C_MC_PROT_PRWURW               (0x3) // (MC) Privilege: Read/Write, User: Read/Write\n#define AT91C_MC_SIZE             (0xF <<  4) // (MC) Internal Area Size\n#define \tAT91C_MC_SIZE_1KB                  (0x0 <<  4) // (MC) Area size 1KByte\n#define \tAT91C_MC_SIZE_2KB                  (0x1 <<  4) // (MC) Area size 2KByte\n#define \tAT91C_MC_SIZE_4KB                  (0x2 <<  4) // (MC) Area size 4KByte\n#define \tAT91C_MC_SIZE_8KB                  (0x3 <<  4) // (MC) Area size 8KByte\n#define \tAT91C_MC_SIZE_16KB                 (0x4 <<  4) // (MC) Area size 16KByte\n#define \tAT91C_MC_SIZE_32KB                 (0x5 <<  4) // (MC) Area size 32KByte\n#define \tAT91C_MC_SIZE_64KB                 (0x6 <<  4) // (MC) Area size 64KByte\n#define \tAT91C_MC_SIZE_128KB                (0x7 <<  4) // (MC) Area size 128KByte\n#define \tAT91C_MC_SIZE_256KB                (0x8 <<  4) // (MC) Area size 256KByte\n#define \tAT91C_MC_SIZE_512KB                (0x9 <<  4) // (MC) Area size 512KByte\n#define \tAT91C_MC_SIZE_1MB                  (0xA <<  4) // (MC) Area size 1MByte\n#define \tAT91C_MC_SIZE_2MB                  (0xB <<  4) // (MC) Area size 2MByte\n#define \tAT91C_MC_SIZE_4MB                  (0xC <<  4) // (MC) Area size 4MByte\n#define \tAT91C_MC_SIZE_8MB                  (0xD <<  4) // (MC) Area size 8MByte\n#define \tAT91C_MC_SIZE_16MB                 (0xE <<  4) // (MC) Area size 16MByte\n#define \tAT91C_MC_SIZE_64MB                 (0xF <<  4) // (MC) Area size 64MByte\n#define AT91C_MC_BA               (0x3FFFF << 10) // (MC) Internal Area Base Address\n// -------- MC_PUP : (MC Offset: 0x50) MC Protection Unit Peripheral -------- \n// -------- MC_PUER : (MC Offset: 0x54) MC Protection Unit Area -------- \n#define AT91C_MC_PUEB             (0x1 <<  0) // (MC) Protection Unit enable Bit\n\n// *****************************************************************************\n//              SOFTWARE API DEFINITION  FOR Real-time Clock Alarm and Parallel Load Interface\n// *****************************************************************************\n// *** Register offset in AT91S_RTC structure ***\n#define RTC_CR          ( 0) // Control Register\n#define RTC_MR          ( 4) // Mode Register\n#define RTC_TIMR        ( 8) // Time Register\n#define RTC_CALR        (12) // Calendar Register\n#define RTC_TIMALR      (16) // Time Alarm Register\n#define RTC_CALALR      (20) // Calendar Alarm Register\n#define RTC_SR          (24) // Status Register\n#define RTC_SCCR        (28) // Status Clear Command Register\n#define RTC_IER         (32) // Interrupt Enable Register\n#define RTC_IDR         (36) // Interrupt Disable Register\n#define RTC_IMR         (40) // Interrupt Mask Register\n#define RTC_VER         (44) // Valid Entry Register\n// -------- RTC_CR : (RTC Offset: 0x0) RTC Control Register -------- \n#define AT91C_RTC_UPDTIM          (0x1 <<  0) // (RTC) Update Request Time Register\n#define AT91C_RTC_UPDCAL          (0x1 <<  1) // (RTC) Update Request Calendar Register\n#define AT91C_RTC_TIMEVSEL        (0x3 <<  8) // (RTC) Time Event Selection\n#define \tAT91C_RTC_TIMEVSEL_MINUTE               (0x0 <<  8) // (RTC) Minute change.\n#define \tAT91C_RTC_TIMEVSEL_HOUR                 (0x1 <<  8) // (RTC) Hour change.\n#define \tAT91C_RTC_TIMEVSEL_DAY24                (0x2 <<  8) // (RTC) Every day at midnight.\n#define \tAT91C_RTC_TIMEVSEL_DAY12                (0x3 <<  8) // (RTC) Every day at noon.\n#define AT91C_RTC_CALEVSEL        (0x3 << 16) // (RTC) Calendar Event Selection\n#define \tAT91C_RTC_CALEVSEL_WEEK                 (0x0 << 16) // (RTC) Week change (every Monday at time 00:00:00).\n#define \tAT91C_RTC_CALEVSEL_MONTH                (0x1 << 16) // (RTC) Month change (every 01 of each month at time 00:00:00).\n#define \tAT91C_RTC_CALEVSEL_YEAR                 (0x2 << 16) // (RTC) Year change (every January 1 at time 00:00:00).\n// -------- RTC_MR : (RTC Offset: 0x4) RTC Mode Register -------- \n#define AT91C_RTC_HRMOD           (0x1 <<  0) // (RTC) 12-24 hour Mode\n// -------- RTC_TIMR : (RTC Offset: 0x8) RTC Time Register -------- \n#define AT91C_RTC_SEC             (0x7F <<  0) // (RTC) Current Second\n#define AT91C_RTC_MIN             (0x7F <<  8) // (RTC) Current Minute\n#define AT91C_RTC_HOUR            (0x1F << 16) // (RTC) Current Hour\n#define AT91C_RTC_AMPM            (0x1 << 22) // (RTC) Ante Meridiem, Post Meridiem Indicator\n// -------- RTC_CALR : (RTC Offset: 0xc) RTC Calendar Register -------- \n#define AT91C_RTC_CENT            (0x3F <<  0) // (RTC) Current Century\n#define AT91C_RTC_YEAR            (0xFF <<  8) // (RTC) Current Year\n#define AT91C_RTC_MONTH           (0x1F << 16) // (RTC) Current Month\n#define AT91C_RTC_DAY             (0x7 << 21) // (RTC) Current Day\n#define AT91C_RTC_DATE            (0x3F << 24) // (RTC) Current Date\n// -------- RTC_TIMALR : (RTC Offset: 0x10) RTC Time Alarm Register -------- \n#define AT91C_RTC_SECEN           (0x1 <<  7) // (RTC) Second Alarm Enable\n#define AT91C_RTC_MINEN           (0x1 << 15) // (RTC) Minute Alarm\n#define AT91C_RTC_HOUREN          (0x1 << 23) // (RTC) Current Hour\n// -------- RTC_CALALR : (RTC Offset: 0x14) RTC Calendar Alarm Register -------- \n#define AT91C_RTC_MONTHEN         (0x1 << 23) // (RTC) Month Alarm Enable\n#define AT91C_RTC_DATEEN          (0x1 << 31) // (RTC) Date Alarm Enable\n// -------- RTC_SR : (RTC Offset: 0x18) RTC Status Register -------- \n#define AT91C_RTC_ACKUPD          (0x1 <<  0) // (RTC) Acknowledge for Update\n#define AT91C_RTC_ALARM           (0x1 <<  1) // (RTC) Alarm Flag\n#define AT91C_RTC_SECEV           (0x1 <<  2) // (RTC) Second Event\n#define AT91C_RTC_TIMEV           (0x1 <<  3) // (RTC) Time Event\n#define AT91C_RTC_CALEV           (0x1 <<  4) // (RTC) Calendar event\n// -------- RTC_SCCR : (RTC Offset: 0x1c) RTC Status Clear Command Register -------- \n// -------- RTC_IER : (RTC Offset: 0x20) RTC Interrupt Enable Register -------- \n// -------- RTC_IDR : (RTC Offset: 0x24) RTC Interrupt Disable Register -------- \n// -------- RTC_IMR : (RTC Offset: 0x28) RTC Interrupt Mask Register -------- \n// -------- RTC_VER : (RTC Offset: 0x2c) RTC Valid Entry Register -------- \n#define AT91C_RTC_NVTIM           (0x1 <<  0) // (RTC) Non valid Time\n#define AT91C_RTC_NVCAL           (0x1 <<  1) // (RTC) Non valid Calendar\n#define AT91C_RTC_NVTIMALR        (0x1 <<  2) // (RTC) Non valid time Alarm\n#define AT91C_RTC_NVCALALR        (0x1 <<  3) // (RTC) Nonvalid Calendar Alarm\n\n// *****************************************************************************\n//              SOFTWARE API DEFINITION  FOR System Timer Interface\n// *****************************************************************************\n// *** Register offset in AT91S_ST structure ***\n#define ST_CR           ( 0) // Control Register\n#define ST_PIMR         ( 4) // Period Interval Mode Register\n#define ST_WDMR         ( 8) // Watchdog Mode Register\n#define ST_RTMR         (12) // Real-time Mode Register\n#define ST_SR           (16) // Status Register\n#define ST_IER          (20) // Interrupt Enable Register\n#define ST_IDR          (24) // Interrupt Disable Register\n#define ST_IMR          (28) // Interrupt Mask Register\n#define ST_RTAR         (32) // Real-time Alarm Register\n#define ST_CRTR         (36) // Current Real-time Register\n// -------- ST_CR : (ST Offset: 0x0) System Timer Control Register -------- \n#define AT91C_ST_WDRST            (0x1 <<  0) // (ST) Watchdog Timer Restart\n// -------- ST_PIMR : (ST Offset: 0x4) System Timer Period Interval Mode Register -------- \n#define AT91C_ST_PIV              (0xFFFF <<  0) // (ST) Watchdog Timer Restart\n// -------- ST_WDMR : (ST Offset: 0x8) System Timer Watchdog Mode Register -------- \n#define AT91C_ST_WDV              (0xFFFF <<  0) // (ST) Watchdog Timer Restart\n#define AT91C_ST_RSTEN            (0x1 << 16) // (ST) Reset Enable\n#define AT91C_ST_EXTEN            (0x1 << 17) // (ST) External Signal Assertion Enable\n// -------- ST_RTMR : (ST Offset: 0xc) System Timer Real-time Mode Register -------- \n#define AT91C_ST_RTPRES           (0xFFFF <<  0) // (ST) Real-time Timer Prescaler Value\n// -------- ST_SR : (ST Offset: 0x10) System Timer Status Register -------- \n#define AT91C_ST_PITS             (0x1 <<  0) // (ST) Period Interval Timer Interrupt\n#define AT91C_ST_WDOVF            (0x1 <<  1) // (ST) Watchdog Overflow\n#define AT91C_ST_RTTINC           (0x1 <<  2) // (ST) Real-time Timer Increment\n#define AT91C_ST_ALMS             (0x1 <<  3) // (ST) Alarm Status\n// -------- ST_IER : (ST Offset: 0x14) System Timer Interrupt Enable Register -------- \n// -------- ST_IDR : (ST Offset: 0x18) System Timer Interrupt Disable Register -------- \n// -------- ST_IMR : (ST Offset: 0x1c) System Timer Interrupt Mask Register -------- \n// -------- ST_RTAR : (ST Offset: 0x20) System Timer Real-time Alarm Register -------- \n#define AT91C_ST_ALMV             (0xFFFFF <<  0) // (ST) Alarm Value Value\n// -------- ST_CRTR : (ST Offset: 0x24) System Timer Current Real-time Register -------- \n#define AT91C_ST_CRTV             (0xFFFFF <<  0) // (ST) Current Real-time Value\n\n// *****************************************************************************\n//              SOFTWARE API DEFINITION  FOR Power Management Controler\n// *****************************************************************************\n// *** Register offset in AT91S_PMC structure ***\n#define PMC_SCER        ( 0) // System Clock Enable Register\n#define PMC_SCDR        ( 4) // System Clock Disable Register\n#define PMC_SCSR        ( 8) // System Clock Status Register\n#define PMC_PCER        (16) // Peripheral Clock Enable Register\n#define PMC_PCDR        (20) // Peripheral Clock Disable Register\n#define PMC_PCSR        (24) // Peripheral Clock Status Register\n#define PMC_MCKR        (48) // Master Clock Register\n#define PMC_PCKR        (64) // Programmable Clock Register\n#define PMC_IER         (96) // Interrupt Enable Register\n#define PMC_IDR         (100) // Interrupt Disable Register\n#define PMC_SR          (104) // Status Register\n#define PMC_IMR         (108) // Interrupt Mask Register\n// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- \n#define AT91C_PMC_PCK             (0x1 <<  0) // (PMC) Processor Clock\n#define AT91C_PMC_UDP             (0x1 <<  1) // (PMC) USB Device Port Clock\n#define AT91C_PMC_MCKUDP          (0x1 <<  2) // (PMC) USB Device Port Master Clock Automatic Disable on Suspend\n#define AT91C_PMC_UHP             (0x1 <<  4) // (PMC) USB Host Port Clock\n#define AT91C_PMC_PCK0            (0x1 <<  8) // (PMC) Programmable Clock Output\n#define AT91C_PMC_PCK1            (0x1 <<  9) // (PMC) Programmable Clock Output\n#define AT91C_PMC_PCK2            (0x1 << 10) // (PMC) Programmable Clock Output\n#define AT91C_PMC_PCK3            (0x1 << 11) // (PMC) Programmable Clock Output\n#define AT91C_PMC_PCK4            (0x1 << 12) // (PMC) Programmable Clock Output\n#define AT91C_PMC_PCK5            (0x1 << 13) // (PMC) Programmable Clock Output\n#define AT91C_PMC_PCK6            (0x1 << 14) // (PMC) Programmable Clock Output\n#define AT91C_PMC_PCK7            (0x1 << 15) // (PMC) Programmable Clock Output\n// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- \n// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- \n// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- \n#define AT91C_PMC_CSS             (0x3 <<  0) // (PMC) Programmable Clock Selection\n#define \tAT91C_PMC_CSS_SLOW_CLK             (0x0) // (PMC) Slow Clock is selected\n#define \tAT91C_PMC_CSS_MAIN_CLK             (0x1) // (PMC) Main Clock is selected\n#define \tAT91C_PMC_CSS_PLLA_CLK             (0x2) // (PMC) Clock from PLL A is selected\n#define \tAT91C_PMC_CSS_PLLB_CLK             (0x3) // (PMC) Clock from PLL B is selected\n#define AT91C_PMC_PRES            (0x7 <<  2) // (PMC) Programmable Clock Prescaler\n#define \tAT91C_PMC_PRES_CLK                  (0x0 <<  2) // (PMC) Selected clock\n#define \tAT91C_PMC_PRES_CLK_2                (0x1 <<  2) // (PMC) Selected clock divided by 2\n#define \tAT91C_PMC_PRES_CLK_4                (0x2 <<  2) // (PMC) Selected clock divided by 4\n#define \tAT91C_PMC_PRES_CLK_8                (0x3 <<  2) // (PMC) Selected clock divided by 8\n#define \tAT91C_PMC_PRES_CLK_16               (0x4 <<  2) // (PMC) Selected clock divided by 16\n#define \tAT91C_PMC_PRES_CLK_32               (0x5 <<  2) // (PMC) Selected clock divided by 32\n#define \tAT91C_PMC_PRES_CLK_64               (0x6 <<  2) // (PMC) Selected clock divided by 64\n#define AT91C_PMC_MDIV            (0x3 <<  8) // (PMC) Master Clock Division\n#define \tAT91C_PMC_MDIV_1                    (0x0 <<  8) // (PMC) The master clock and the processor clock are the same\n#define \tAT91C_PMC_MDIV_2                    (0x1 <<  8) // (PMC) The processor clock is twice as fast as the master clock\n#define \tAT91C_PMC_MDIV_3                    (0x2 <<  8) // (PMC) The processor clock is three times faster than the master clock\n#define \tAT91C_PMC_MDIV_4                    (0x3 <<  8) // (PMC) The processor clock is four times faster than the master clock\n// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- \n// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- \n#define AT91C_PMC_MOSCS           (0x1 <<  0) // (PMC) MOSC Status/Enable/Disable/Mask\n#define AT91C_PMC_LOCKA           (0x1 <<  1) // (PMC) PLL A Status/Enable/Disable/Mask\n#define AT91C_PMC_LOCKB           (0x1 <<  2) // (PMC) PLL B Status/Enable/Disable/Mask\n#define AT91C_PMC_MCKRDY          (0x1 <<  3) // (PMC) MCK_RDY Status/Enable/Disable/Mask\n#define AT91C_PMC_PCK0RDY         (0x1 <<  8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask\n#define AT91C_PMC_PCK1RDY         (0x1 <<  9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask\n#define AT91C_PMC_PCK2RDY         (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask\n#define AT91C_PMC_PCK3RDY         (0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask\n#define AT91C_PMC_PCK4RDY         (0x1 << 12) // (PMC) PCK4_RDY Status/Enable/Disable/Mask\n#define AT91C_PMC_PCK5RDY         (0x1 << 13) // (PMC) PCK5_RDY Status/Enable/Disable/Mask\n#define AT91C_PMC_PCK6RDY         (0x1 << 14) // (PMC) PCK6_RDY Status/Enable/Disable/Mask\n#define AT91C_PMC_PCK7RDY         (0x1 << 15) // (PMC) PCK7_RDY Status/Enable/Disable/Mask\n// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- \n// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- \n// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- \n\n// *****************************************************************************\n//              SOFTWARE API DEFINITION  FOR Clock Generator Controler\n// *****************************************************************************\n// *** Register offset in AT91S_CKGR structure ***\n#define CKGR_MOR        ( 0) // Main Oscillator Register\n#define CKGR_MCFR       ( 4) // Main Clock  Frequency Register\n#define CKGR_PLLAR      ( 8) // PLL A Register\n#define CKGR_PLLBR      (12) // PLL B Register\n// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- \n#define AT91C_CKGR_MOSCEN         (0x1 <<  0) // (CKGR) Main Oscillator Enable\n#define AT91C_CKGR_OSCTEST        (0x1 <<  1) // (CKGR) Oscillator Test\n#define AT91C_CKGR_OSCOUNT        (0xFF <<  8) // (CKGR) Main Oscillator Start-up Time\n// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- \n#define AT91C_CKGR_MAINF          (0xFFFF <<  0) // (CKGR) Main Clock Frequency\n#define AT91C_CKGR_MAINRDY        (0x1 << 16) // (CKGR) Main Clock Ready\n// -------- CKGR_PLLAR : (CKGR Offset: 0x8) PLL A Register -------- \n#define AT91C_CKGR_DIVA           (0xFF <<  0) // (CKGR) Divider Selected\n#define \tAT91C_CKGR_DIVA_0                    (0x0) // (CKGR) Divider output is 0\n#define \tAT91C_CKGR_DIVA_BYPASS               (0x1) // (CKGR) Divider is bypassed\n#define AT91C_CKGR_PLLACOUNT      (0x3F <<  8) // (CKGR) PLL A Counter\n#define AT91C_CKGR_OUTA           (0x3 << 14) // (CKGR) PLL A Output Frequency Range\n#define \tAT91C_CKGR_OUTA_0                    (0x0 << 14) // (CKGR) Please refer to the PLLA datasheet\n#define \tAT91C_CKGR_OUTA_1                    (0x1 << 14) // (CKGR) Please refer to the PLLA datasheet\n#define \tAT91C_CKGR_OUTA_2                    (0x2 << 14) // (CKGR) Please refer to the PLLA datasheet\n#define \tAT91C_CKGR_OUTA_3                    (0x3 << 14) // (CKGR) Please refer to the PLLA datasheet\n#define AT91C_CKGR_MULA           (0x7FF << 16) // (CKGR) PLL A Multiplier\n#define AT91C_CKGR_SRCA           (0x1 << 29) // (CKGR) PLL A Source\n// -------- CKGR_PLLBR : (CKGR Offset: 0xc) PLL B Register -------- \n#define AT91C_CKGR_DIVB           (0xFF <<  0) // (CKGR) Divider Selected\n#define \tAT91C_CKGR_DIVB_0                    (0x0) // (CKGR) Divider output is 0\n#define \tAT91C_CKGR_DIVB_BYPASS               (0x1) // (CKGR) Divider is bypassed\n#define AT91C_CKGR_PLLBCOUNT      (0x3F <<  8) // (CKGR) PLL B Counter\n#define AT91C_CKGR_OUTB           (0x3 << 14) // (CKGR) PLL B Output Frequency Range\n#define \tAT91C_CKGR_OUTB_0                    (0x0 << 14) // (CKGR) Please refer to the PLLB datasheet\n#define \tAT91C_CKGR_OUTB_1                    (0x1 << 14) // (CKGR) Please refer to the PLLB datasheet\n#define \tAT91C_CKGR_OUTB_2                    (0x2 << 14) // (CKGR) Please refer to the PLLB datasheet\n#define \tAT91C_CKGR_OUTB_3                    (0x3 << 14) // (CKGR) Please refer to the PLLB datasheet\n#define AT91C_CKGR_MULB           (0x7FF << 16) // (CKGR) PLL B Multiplier\n#define AT91C_CKGR_USB_96M        (0x1 << 28) // (CKGR) Divider for USB Ports\n#define AT91C_CKGR_USB_PLL        (0x1 << 29) // (CKGR) PLL Use\n\n// *****************************************************************************\n//              SOFTWARE API DEFINITION  FOR Parallel Input Output Controler\n// *****************************************************************************\n// *** Register offset in AT91S_PIO structure ***\n#define PIO_PER         ( 0) // PIO Enable Register\n#define PIO_PDR         ( 4) // PIO Disable Register\n#define PIO_PSR         ( 8) // PIO Status Register\n#define PIO_OER         (16) // Output Enable Register\n#define PIO_ODR         (20) // Output Disable Registerr\n#define PIO_OSR         (24) // Output Status Register\n#define PIO_IFER        (32) // Input Filter Enable Register\n#define PIO_IFDR        (36) // Input Filter Disable Register\n#define PIO_IFSR        (40) // Input Filter Status Register\n#define PIO_SODR        (48) // Set Output Data Register\n#define PIO_CODR        (52) // Clear Output Data Register\n#define PIO_ODSR        (56) // Output Data Status Register\n#define PIO_PDSR        (60) // Pin Data Status Register\n#define PIO_IER         (64) // Interrupt Enable Register\n#define PIO_IDR         (68) // Interrupt Disable Register\n#define PIO_IMR         (72) // Interrupt Mask Register\n#define PIO_ISR         (76) // Interrupt Status Register\n#define PIO_MDER        (80) // Multi-driver Enable Register\n#define PIO_MDDR        (84) // Multi-driver Disable Register\n#define PIO_MDSR        (88) // Multi-driver Status Register\n#define PIO_PPUDR       (96) // Pull-up Disable Register\n#define PIO_PPUER       (100) // Pull-up Enable Register\n#define PIO_PPUSR       (104) // Pad Pull-up Status Register\n#define PIO_ASR         (112) // Select A Register\n#define PIO_BSR         (116) // Select B Register\n#define PIO_ABSR        (120) // AB Select Status Register\n#define PIO_OWER        (160) // Output Write Enable Register\n#define PIO_OWDR        (164) // Output Write Disable Register\n#define PIO_OWSR        (168) // Output Write Status Register\n\n// *****************************************************************************\n//              SOFTWARE API DEFINITION  FOR Debug Unit\n// *****************************************************************************\n// *** Register offset in AT91S_DBGU structure ***\n#define DBGU_CR         ( 0) // Control Register\n#define DBGU_MR         ( 4) // Mode Register\n#define DBGU_IER        ( 8) // Interrupt Enable Register\n#define DBGU_IDR        (12) // Interrupt Disable Register\n#define DBGU_IMR        (16) // Interrupt Mask Register\n#define DBGU_CSR        (20) // Channel Status Register\n#define DBGU_RHR        (24) // Receiver Holding Register\n#define DBGU_THR        (28) // Transmitter Holding Register\n#define DBGU_BRGR       (32) // Baud Rate Generator Register\n#define DBGU_C1R        (64) // Chip ID1 Register\n#define DBGU_C2R        (68) // Chip ID2 Register\n#define DBGU_FNTR       (72) // Force NTRST Register\n#define DBGU_RPR        (256) // Receive Pointer Register\n#define DBGU_RCR        (260) // Receive Counter Register\n#define DBGU_TPR        (264) // Transmit Pointer Register\n#define DBGU_TCR        (268) // Transmit Counter Register\n#define DBGU_RNPR       (272) // Receive Next Pointer Register\n#define DBGU_RNCR       (276) // Receive Next Counter Register\n#define DBGU_TNPR       (280) // Transmit Next Pointer Register\n#define DBGU_TNCR       (284) // Transmit Next Counter Register\n#define DBGU_PTCR       (288) // PDC Transfer Control Register\n#define DBGU_PTSR       (292) // PDC Transfer Status Register\n// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- \n#define AT91C_US_RSTRX            (0x1 <<  2) // (DBGU) Reset Receiver\n#define AT91C_US_RSTTX            (0x1 <<  3) // (DBGU) Reset Transmitter\n#define AT91C_US_RXEN             (0x1 <<  4) // (DBGU) Receiver Enable\n#define AT91C_US_RXDIS            (0x1 <<  5) // (DBGU) Receiver Disable\n#define AT91C_US_TXEN             (0x1 <<  6) // (DBGU) Transmitter Enable\n#define AT91C_US_TXDIS            (0x1 <<  7) // (DBGU) Transmitter Disable\n// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- \n#define AT91C_US_PAR              (0x7 <<  9) // (DBGU) Parity type\n#define \tAT91C_US_PAR_EVEN                 (0x0 <<  9) // (DBGU) Even Parity\n#define \tAT91C_US_PAR_ODD                  (0x1 <<  9) // (DBGU) Odd Parity\n#define \tAT91C_US_PAR_SPACE                (0x2 <<  9) // (DBGU) Parity forced to 0 (Space)\n#define \tAT91C_US_PAR_MARK                 (0x3 <<  9) // (DBGU) Parity forced to 1 (Mark)\n#define \tAT91C_US_PAR_NONE                 (0x4 <<  9) // (DBGU) No Parity\n#define \tAT91C_US_PAR_MULTI_DROP           (0x6 <<  9) // (DBGU) Multi-drop mode\n#define AT91C_US_CHMODE           (0x3 << 14) // (DBGU) Channel Mode\n#define \tAT91C_US_CHMODE_NORMAL               (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.\n#define \tAT91C_US_CHMODE_AUTO                 (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.\n#define \tAT91C_US_CHMODE_LOCAL                (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.\n#define \tAT91C_US_CHMODE_REMOTE               (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.\n// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- \n#define AT91C_US_RXRDY            (0x1 <<  0) // (DBGU) RXRDY Interrupt\n#define AT91C_US_TXRDY            (0x1 <<  1) // (DBGU) TXRDY Interrupt\n#define AT91C_US_ENDRX            (0x1 <<  3) // (DBGU) End of Receive Transfer Interrupt\n#define AT91C_US_ENDTX            (0x1 <<  4) // (DBGU) End of Transmit Interrupt\n#define AT91C_US_OVRE             (0x1 <<  5) // (DBGU) Overrun Interrupt\n#define AT91C_US_FRAME            (0x1 <<  6) // (DBGU) Framing Error Interrupt\n#define AT91C_US_PARE             (0x1 <<  7) // (DBGU) Parity Error Interrupt\n#define AT91C_US_TXEMPTY          (0x1 <<  9) // (DBGU) TXEMPTY Interrupt\n#define AT91C_US_TXBUFE           (0x1 << 11) // (DBGU) TXBUFE Interrupt\n#define AT91C_US_RXBUFF           (0x1 << 12) // (DBGU) RXBUFF Interrupt\n#define AT91C_US_COMM_TX          (0x1 << 30) // (DBGU) COMM_TX Interrupt\n#define AT91C_US_COMM_RX          (0x1 << 31) // (DBGU) COMM_RX Interrupt\n// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- \n// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- \n// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- \n// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- \n#define AT91C_US_FORCE_NTRST      (0x1 <<  0) // (DBGU) Force NTRST in JTAG\n\n// *****************************************************************************\n//              SOFTWARE API DEFINITION  FOR Peripheral Data Controller\n// *****************************************************************************\n// *** Register offset in AT91S_PDC structure ***\n#define PDC_RPR         ( 0) // Receive Pointer Register\n#define PDC_RCR         ( 4) // Receive Counter Register\n#define PDC_TPR         ( 8) // Transmit Pointer Register\n#define PDC_TCR         (12) // Transmit Counter Register\n#define PDC_RNPR        (16) // Receive Next Pointer Register\n#define PDC_RNCR        (20) // Receive Next Counter Register\n#define PDC_TNPR        (24) // Transmit Next Pointer Register\n#define PDC_TNCR        (28) // Transmit Next Counter Register\n#define PDC_PTCR        (32) // PDC Transfer Control Register\n#define PDC_PTSR        (36) // PDC Transfer Status Register\n// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- \n#define AT91C_PDC_RXTEN           (0x1 <<  0) // (PDC) Receiver Transfer Enable\n#define AT91C_PDC_RXTDIS          (0x1 <<  1) // (PDC) Receiver Transfer Disable\n#define AT91C_PDC_TXTEN           (0x1 <<  8) // (PDC) Transmitter Transfer Enable\n#define AT91C_PDC_TXTDIS          (0x1 <<  9) // (PDC) Transmitter Transfer Disable\n// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- \n\n// *****************************************************************************\n//              SOFTWARE API DEFINITION  FOR Advanced Interrupt Controller\n// *****************************************************************************\n// *** Register offset in AT91S_AIC structure ***\n#define AIC_SMR         ( 0) // Source Mode Register\n#define AIC_SVR         (128) // Source Vector Register\n#define AIC_IVR         (256) // IRQ Vector Register\n#define AIC_FVR         (260) // FIQ Vector Register\n#define AIC_ISR         (264) // Interrupt Status Register\n#define AIC_IPR         (268) // Interrupt Pending Register\n#define AIC_IMR         (272) // Interrupt Mask Register\n#define AIC_CISR        (276) // Core Interrupt Status Register\n#define AIC_IECR        (288) // Interrupt Enable Command Register\n#define AIC_IDCR        (292) // Interrupt Disable Command Register\n#define AIC_ICCR        (296) // Interrupt Clear Command Register\n#define AIC_ISCR        (300) // Interrupt Set Command Register\n#define AIC_EOICR       (304) // End of Interrupt Command Register\n#define AIC_SPU         (308) // Spurious Vector Register\n#define AIC_DCR         (312) // Debug Control Register (Protect)\n#define AIC_FFER        (320) // Fast Forcing Enable Register\n#define AIC_FFDR        (324) // Fast Forcing Disable Register\n#define AIC_FFSR        (328) // Fast Forcing Status Register\n// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- \n#define AT91C_AIC_PRIOR           (0x7 <<  0) // (AIC) Priority Level\n#define \tAT91C_AIC_PRIOR_LOWEST               (0x0) // (AIC) Lowest priority level\n#define \tAT91C_AIC_PRIOR_HIGHEST              (0x7) // (AIC) Highest priority level\n#define AT91C_AIC_SRCTYPE         (0x3 <<  5) // (AIC) Interrupt Source Type\n#define \tAT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE  (0x0 <<  5) // (AIC) Internal Sources Code Label Level Sensitive\n#define \tAT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED   (0x1 <<  5) // (AIC) Internal Sources Code Label Edge triggered\n#define \tAT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL       (0x2 <<  5) // (AIC) External Sources Code Label High-level Sensitive\n#define \tAT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE    (0x3 <<  5) // (AIC) External Sources Code Label Positive Edge triggered\n// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- \n#define AT91C_AIC_NFIQ            (0x1 <<  0) // (AIC) NFIQ Status\n#define AT91C_AIC_NIRQ            (0x1 <<  1) // (AIC) NIRQ Status\n// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- \n#define AT91C_AIC_DCR_PROT        (0x1 <<  0) // (AIC) Protection Mode\n#define AT91C_AIC_DCR_GMSK        (0x1 <<  1) // (AIC) General Mask\n\n// *****************************************************************************\n//              SOFTWARE API DEFINITION  FOR Serial Parallel Interface\n// *****************************************************************************\n// *** Register offset in AT91S_SPI structure ***\n#define SPI_CR          ( 0) // Control Register\n#define SPI_MR          ( 4) // Mode Register\n#define SPI_RDR         ( 8) // Receive Data Register\n#define SPI_TDR         (12) // Transmit Data Register\n#define SPI_SR          (16) // Status Register\n#define SPI_IER         (20) // Interrupt Enable Register\n#define SPI_IDR         (24) // Interrupt Disable Register\n#define SPI_IMR         (28) // Interrupt Mask Register\n#define SPI_CSR         (48) // Chip Select Register\n#define SPI_RPR         (256) // Receive Pointer Register\n#define SPI_RCR         (260) // Receive Counter Register\n#define SPI_TPR         (264) // Transmit Pointer Register\n#define SPI_TCR         (268) // Transmit Counter Register\n#define SPI_RNPR        (272) // Receive Next Pointer Register\n#define SPI_RNCR        (276) // Receive Next Counter Register\n#define SPI_TNPR        (280) // Transmit Next Pointer Register\n#define SPI_TNCR        (284) // Transmit Next Counter Register\n#define SPI_PTCR        (288) // PDC Transfer Control Register\n#define SPI_PTSR        (292) // PDC Transfer Status Register\n// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- \n#define AT91C_SPI_SPIEN           (0x1 <<  0) // (SPI) SPI Enable\n#define AT91C_SPI_SPIDIS          (0x1 <<  1) // (SPI) SPI Disable\n#define AT91C_SPI_SWRST           (0x1 <<  7) // (SPI) SPI Software reset\n// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- \n#define AT91C_SPI_MSTR            (0x1 <<  0) // (SPI) Master/Slave Mode\n#define AT91C_SPI_PS              (0x1 <<  1) // (SPI) Peripheral Select\n#define \tAT91C_SPI_PS_FIXED                (0x0 <<  1) // (SPI) Fixed Peripheral Select\n#define \tAT91C_SPI_PS_VARIABLE             (0x1 <<  1) // (SPI) Variable Peripheral Select\n#define AT91C_SPI_PCSDEC          (0x1 <<  2) // (SPI) Chip Select Decode\n#define AT91C_SPI_DIV32           (0x1 <<  3) // (SPI) Clock Selection\n#define AT91C_SPI_MODFDIS         (0x1 <<  4) // (SPI) Mode Fault Detection\n#define AT91C_SPI_LLB             (0x1 <<  7) // (SPI) Clock Selection\n#define AT91C_SPI_PCS             (0xF << 16) // (SPI) Peripheral Chip Select\n#define AT91C_SPI_DLYBCS          (0xFF << 24) // (SPI) Delay Between Chip Selects\n// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- \n#define AT91C_SPI_RD              (0xFFFF <<  0) // (SPI) Receive Data\n#define AT91C_SPI_RPCS            (0xF << 16) // (SPI) Peripheral Chip Select Status\n// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- \n#define AT91C_SPI_TD              (0xFFFF <<  0) // (SPI) Transmit Data\n#define AT91C_SPI_TPCS            (0xF << 16) // (SPI) Peripheral Chip Select Status\n// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- \n#define AT91C_SPI_RDRF            (0x1 <<  0) // (SPI) Receive Data Register Full\n#define AT91C_SPI_TDRE            (0x1 <<  1) // (SPI) Transmit Data Register Empty\n#define AT91C_SPI_MODF            (0x1 <<  2) // (SPI) Mode Fault Error\n#define AT91C_SPI_OVRES           (0x1 <<  3) // (SPI) Overrun Error Status\n#define AT91C_SPI_SPENDRX         (0x1 <<  4) // (SPI) End of Receiver Transfer\n#define AT91C_SPI_SPENDTX         (0x1 <<  5) // (SPI) End of Receiver Transfer\n#define AT91C_SPI_RXBUFF          (0x1 <<  6) // (SPI) RXBUFF Interrupt\n#define AT91C_SPI_TXBUFE          (0x1 <<  7) // (SPI) TXBUFE Interrupt\n#define AT91C_SPI_SPIENS          (0x1 << 16) // (SPI) Enable Status\n// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- \n// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- \n// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- \n// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- \n#define AT91C_SPI_CPOL            (0x1 <<  0) // (SPI) Clock Polarity\n#define AT91C_SPI_NCPHA           (0x1 <<  1) // (SPI) Clock Phase\n#define AT91C_SPI_BITS            (0xF <<  4) // (SPI) Bits Per Transfer\n#define \tAT91C_SPI_BITS_8                    (0x0 <<  4) // (SPI) 8 Bits Per transfer\n#define \tAT91C_SPI_BITS_9                    (0x1 <<  4) // (SPI) 9 Bits Per transfer\n#define \tAT91C_SPI_BITS_10                   (0x2 <<  4) // (SPI) 10 Bits Per transfer\n#define \tAT91C_SPI_BITS_11                   (0x3 <<  4) // (SPI) 11 Bits Per transfer\n#define \tAT91C_SPI_BITS_12                   (0x4 <<  4) // (SPI) 12 Bits Per transfer\n#define \tAT91C_SPI_BITS_13                   (0x5 <<  4) // (SPI) 13 Bits Per transfer\n#define \tAT91C_SPI_BITS_14                   (0x6 <<  4) // (SPI) 14 Bits Per transfer\n#define \tAT91C_SPI_BITS_15                   (0x7 <<  4) // (SPI) 15 Bits Per transfer\n#define \tAT91C_SPI_BITS_16                   (0x8 <<  4) // (SPI) 16 Bits Per transfer\n#define AT91C_SPI_SCBR            (0xFF <<  8) // (SPI) Serial Clock Baud Rate\n#define AT91C_SPI_DLYBS           (0xFF << 16) // (SPI) Serial Clock Baud Rate\n#define AT91C_SPI_DLYBCT          (0xFF << 24) // (SPI) Delay Between Consecutive Transfers\n\n// *****************************************************************************\n//              SOFTWARE API DEFINITION  FOR Synchronous Serial Controller Interface\n// *****************************************************************************\n// *** Register offset in AT91S_SSC structure ***\n#define SSC_CR          ( 0) // Control Register\n#define SSC_CMR         ( 4) // Clock Mode Register\n#define SSC_RCMR        (16) // Receive Clock ModeRegister\n#define SSC_RFMR        (20) // Receive Frame Mode Register\n#define SSC_TCMR        (24) // Transmit Clock Mode Register\n#define SSC_TFMR        (28) // Transmit Frame Mode Register\n#define SSC_RHR         (32) // Receive Holding Register\n#define SSC_THR         (36) // Transmit Holding Register\n#define SSC_RSHR        (48) // Receive Sync Holding Register\n#define SSC_TSHR        (52) // Transmit Sync Holding Register\n#define SSC_RC0R        (56) // Receive Compare 0 Register\n#define SSC_RC1R        (60) // Receive Compare 1 Register\n#define SSC_SR          (64) // Status Register\n#define SSC_IER         (68) // Interrupt Enable Register\n#define SSC_IDR         (72) // Interrupt Disable Register\n#define SSC_IMR         (76) // Interrupt Mask Register\n#define SSC_RPR         (256) // Receive Pointer Register\n#define SSC_RCR         (260) // Receive Counter Register\n#define SSC_TPR         (264) // Transmit Pointer Register\n#define SSC_TCR         (268) // Transmit Counter Register\n#define SSC_RNPR        (272) // Receive Next Pointer Register\n#define SSC_RNCR        (276) // Receive Next Counter Register\n#define SSC_TNPR        (280) // Transmit Next Pointer Register\n#define SSC_TNCR        (284) // Transmit Next Counter Register\n#define SSC_PTCR        (288) // PDC Transfer Control Register\n#define SSC_PTSR        (292) // PDC Transfer Status Register\n// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- \n#define AT91C_SSC_RXEN            (0x1 <<  0) // (SSC) Receive Enable\n#define AT91C_SSC_RXDIS           (0x1 <<  1) // (SSC) Receive Disable\n#define AT91C_SSC_TXEN            (0x1 <<  8) // (SSC) Transmit Enable\n#define AT91C_SSC_TXDIS           (0x1 <<  9) // (SSC) Transmit Disable\n#define AT91C_SSC_SWRST           (0x1 << 15) // (SSC) Software Reset\n// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- \n#define AT91C_SSC_CKS             (0x3 <<  0) // (SSC) Receive/Transmit Clock Selection\n#define \tAT91C_SSC_CKS_DIV                  (0x0) // (SSC) Divided Clock\n#define \tAT91C_SSC_CKS_TK                   (0x1) // (SSC) TK Clock signal\n#define \tAT91C_SSC_CKS_RK                   (0x2) // (SSC) RK pin\n#define AT91C_SSC_CKO             (0x7 <<  2) // (SSC) Receive/Transmit Clock Output Mode Selection\n#define \tAT91C_SSC_CKO_NONE                 (0x0 <<  2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only\n#define \tAT91C_SSC_CKO_CONTINOUS            (0x1 <<  2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output\n#define \tAT91C_SSC_CKO_DATA_TX              (0x2 <<  2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output\n#define AT91C_SSC_CKI             (0x1 <<  5) // (SSC) Receive/Transmit Clock Inversion\n#define AT91C_SSC_CKG             (0x3 <<  6) // (SSC) Receive/Transmit Clock Gating Selection\n#define \tAT91C_SSC_CKG_NONE                 (0x0 <<  6) // (SSC) Receive/Transmit Clock Gating: None, continuous clock\n#define \tAT91C_SSC_CKG_LOW                  (0x1 <<  6) // (SSC) Receive/Transmit Clock enabled only if RF Low\n#define \tAT91C_SSC_CKG_HIGH                 (0x2 <<  6) // (SSC) Receive/Transmit Clock enabled only if RF High\n#define AT91C_SSC_START           (0xF <<  8) // (SSC) Receive/Transmit Start Selection\n#define \tAT91C_SSC_START_CONTINOUS            (0x0 <<  8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.\n#define \tAT91C_SSC_START_TX                   (0x1 <<  8) // (SSC) Transmit/Receive start\n#define \tAT91C_SSC_START_LOW_RF               (0x2 <<  8) // (SSC) Detection of a low level on RF input\n#define \tAT91C_SSC_START_HIGH_RF              (0x3 <<  8) // (SSC) Detection of a high level on RF input\n#define \tAT91C_SSC_START_FALL_RF              (0x4 <<  8) // (SSC) Detection of a falling edge on RF input\n#define \tAT91C_SSC_START_RISE_RF              (0x5 <<  8) // (SSC) Detection of a rising edge on RF input\n#define \tAT91C_SSC_START_LEVEL_RF             (0x6 <<  8) // (SSC) Detection of any level change on RF input\n#define \tAT91C_SSC_START_EDGE_RF              (0x7 <<  8) // (SSC) Detection of any edge on RF input\n#define \tAT91C_SSC_START_0                    (0x8 <<  8) // (SSC) Compare 0\n#define AT91C_SSC_STOP            (0x1 << 12) // (SSC) Receive Stop Selection\n#define AT91C_SSC_STTOUT          (0x1 << 15) // (SSC) Receive/Transmit Start Output Selection\n#define AT91C_SSC_STTDLY          (0xFF << 16) // (SSC) Receive/Transmit Start Delay\n#define AT91C_SSC_PERIOD          (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection\n// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- \n#define AT91C_SSC_DATLEN          (0x1F <<  0) // (SSC) Data Length\n#define AT91C_SSC_LOOP            (0x1 <<  5) // (SSC) Loop Mode\n#define AT91C_SSC_MSBF            (0x1 <<  7) // (SSC) Most Significant Bit First\n#define AT91C_SSC_DATNB           (0xF <<  8) // (SSC) Data Number per Frame\n#define AT91C_SSC_FSLEN           (0xF << 16) // (SSC) Receive/Transmit Frame Sync length\n#define AT91C_SSC_FSOS            (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection\n#define \tAT91C_SSC_FSOS_NONE                 (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only\n#define \tAT91C_SSC_FSOS_NEGATIVE             (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse\n#define \tAT91C_SSC_FSOS_POSITIVE             (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse\n#define \tAT91C_SSC_FSOS_LOW                  (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer\n#define \tAT91C_SSC_FSOS_HIGH                 (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer\n#define \tAT91C_SSC_FSOS_TOGGLE               (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer\n#define AT91C_SSC_FSEDGE          (0x1 << 24) // (SSC) Frame Sync Edge Detection\n// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- \n// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- \n#define AT91C_SSC_DATDEF          (0x1 <<  5) // (SSC) Data Default Value\n#define AT91C_SSC_FSDEN           (0x1 << 23) // (SSC) Frame Sync Data Enable\n// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- \n#define AT91C_SSC_TXRDY           (0x1 <<  0) // (SSC) Transmit Ready\n#define AT91C_SSC_TXEMPTY         (0x1 <<  1) // (SSC) Transmit Empty\n#define AT91C_SSC_ENDTX           (0x1 <<  2) // (SSC) End Of Transmission\n#define AT91C_SSC_TXBUFE          (0x1 <<  3) // (SSC) Transmit Buffer Empty\n#define AT91C_SSC_RXRDY           (0x1 <<  4) // (SSC) Receive Ready\n#define AT91C_SSC_OVRUN           (0x1 <<  5) // (SSC) Receive Overrun\n#define AT91C_SSC_ENDRX           (0x1 <<  6) // (SSC) End of Reception\n#define AT91C_SSC_RXBUFF          (0x1 <<  7) // (SSC) Receive Buffer Full\n#define AT91C_SSC_CP0             (0x1 <<  8) // (SSC) Compare 0\n#define AT91C_SSC_CP1             (0x1 <<  9) // (SSC) Compare 1\n#define AT91C_SSC_TXSYN           (0x1 << 10) // (SSC) Transmit Sync\n#define AT91C_SSC_RXSYN           (0x1 << 11) // (SSC) Receive Sync\n#define AT91C_SSC_TXENA           (0x1 << 16) // (SSC) Transmit Enable\n#define AT91C_SSC_RXENA           (0x1 << 17) // (SSC) Receive Enable\n// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- \n// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- \n// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- \n\n// *****************************************************************************\n//              SOFTWARE API DEFINITION  FOR Usart\n// *****************************************************************************\n// *** Register offset in AT91S_USART structure ***\n#define US_CR           ( 0) // Control Register\n#define US_MR           ( 4) // Mode Register\n#define US_IER          ( 8) // Interrupt Enable Register\n#define US_IDR          (12) // Interrupt Disable Register\n#define US_IMR          (16) // Interrupt Mask Register\n#define US_CSR          (20) // Channel Status Register\n#define US_RHR          (24) // Receiver Holding Register\n#define US_THR          (28) // Transmitter Holding Register\n#define US_BRGR         (32) // Baud Rate Generator Register\n#define US_RTOR         (36) // Receiver Time-out Register\n#define US_TTGR         (40) // Transmitter Time-guard Register\n#define US_FIDI         (64) // FI_DI_Ratio Register\n#define US_NER          (68) // Nb Errors Register\n#define US_XXR          (72) // XON_XOFF Register\n#define US_IF           (76) // IRDA_FILTER Register\n#define US_RPR          (256) // Receive Pointer Register\n#define US_RCR          (260) // Receive Counter Register\n#define US_TPR          (264) // Transmit Pointer Register\n#define US_TCR          (268) // Transmit Counter Register\n#define US_RNPR         (272) // Receive Next Pointer Register\n#define US_RNCR         (276) // Receive Next Counter Register\n#define US_TNPR         (280) // Transmit Next Pointer Register\n#define US_TNCR         (284) // Transmit Next Counter Register\n#define US_PTCR         (288) // PDC Transfer Control Register\n#define US_PTSR         (292) // PDC Transfer Status Register\n// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- \n#define AT91C_US_RSTSTA           (0x1 <<  8) // (USART) Reset Status Bits\n#define AT91C_US_STTBRK           (0x1 <<  9) // (USART) Start Break\n#define AT91C_US_STPBRK           (0x1 << 10) // (USART) Stop Break\n#define AT91C_US_STTTO            (0x1 << 11) // (USART) Start Time-out\n#define AT91C_US_SENDA            (0x1 << 12) // (USART) Send Address\n#define AT91C_US_RSTIT            (0x1 << 13) // (USART) Reset Iterations\n#define AT91C_US_RSTNACK          (0x1 << 14) // (USART) Reset Non Acknowledge\n#define AT91C_US_RETTO            (0x1 << 15) // (USART) Rearm Time-out\n#define AT91C_US_DTREN            (0x1 << 16) // (USART) Data Terminal ready Enable\n#define AT91C_US_DTRDIS           (0x1 << 17) // (USART) Data Terminal ready Disable\n#define AT91C_US_RTSEN            (0x1 << 18) // (USART) Request to Send enable\n#define AT91C_US_RTSDIS           (0x1 << 19) // (USART) Request to Send Disable\n// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- \n#define AT91C_US_USMODE           (0xF <<  0) // (USART) Usart mode\n#define \tAT91C_US_USMODE_NORMAL               (0x0) // (USART) Normal\n#define \tAT91C_US_USMODE_RS485                (0x1) // (USART) RS485\n#define \tAT91C_US_USMODE_HWHSH                (0x2) // (USART) Hardware Handshaking\n#define \tAT91C_US_USMODE_MODEM                (0x3) // (USART) Modem\n#define \tAT91C_US_USMODE_ISO7816_0            (0x4) // (USART) ISO7816 protocol: T = 0\n#define \tAT91C_US_USMODE_ISO7816_1            (0x6) // (USART) ISO7816 protocol: T = 1\n#define \tAT91C_US_USMODE_IRDA                 (0x8) // (USART) IrDA\n#define \tAT91C_US_USMODE_SWHSH                (0xC) // (USART) Software Handshaking\n#define AT91C_US_CLKS             (0x3 <<  4) // (USART) Clock Selection (Baud Rate generator Input Clock\n#define \tAT91C_US_CLKS_CLOCK                (0x0 <<  4) // (USART) Clock\n#define \tAT91C_US_CLKS_FDIV1                (0x1 <<  4) // (USART) fdiv1\n#define \tAT91C_US_CLKS_SLOW                 (0x2 <<  4) // (USART) slow_clock (ARM)\n#define \tAT91C_US_CLKS_EXT                  (0x3 <<  4) // (USART) External (SCK)\n#define AT91C_US_CHRL             (0x3 <<  6) // (USART) Clock Selection (Baud Rate generator Input Clock\n#define \tAT91C_US_CHRL_5_BITS               (0x0 <<  6) // (USART) Character Length: 5 bits\n#define \tAT91C_US_CHRL_6_BITS               (0x1 <<  6) // (USART) Character Length: 6 bits\n#define \tAT91C_US_CHRL_7_BITS               (0x2 <<  6) // (USART) Character Length: 7 bits\n#define \tAT91C_US_CHRL_8_BITS               (0x3 <<  6) // (USART) Character Length: 8 bits\n#define AT91C_US_SYNC             (0x1 <<  8) // (USART) Synchronous Mode Select\n#define AT91C_US_NBSTOP           (0x3 << 12) // (USART) Number of Stop bits\n#define \tAT91C_US_NBSTOP_1_BIT                (0x0 << 12) // (USART) 1 stop bit\n#define \tAT91C_US_NBSTOP_15_BIT               (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits\n#define \tAT91C_US_NBSTOP_2_BIT                (0x2 << 12) // (USART) 2 stop bits\n#define AT91C_US_MSBF             (0x1 << 16) // (USART) Bit Order\n#define AT91C_US_MODE9            (0x1 << 17) // (USART) 9-bit Character length\n#define AT91C_US_CKLO             (0x1 << 18) // (USART) Clock Output Select\n#define AT91C_US_OVER             (0x1 << 19) // (USART) Over Sampling Mode\n#define AT91C_US_INACK            (0x1 << 20) // (USART) Inhibit Non Acknowledge\n#define AT91C_US_DSNACK           (0x1 << 21) // (USART) Disable Successive NACK\n#define AT91C_US_MAX_ITER         (0x1 << 24) // (USART) Number of Repetitions\n#define AT91C_US_FILTER           (0x1 << 28) // (USART) Receive Line Filter\n// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- \n#define AT91C_US_RXBRK            (0x1 <<  2) // (USART) Break Received/End of Break\n#define AT91C_US_TIMEOUT          (0x1 <<  8) // (USART) Receiver Time-out\n#define AT91C_US_ITERATION        (0x1 << 10) // (USART) Max number of Repetitions Reached\n#define AT91C_US_NACK             (0x1 << 13) // (USART) Non Acknowledge\n#define AT91C_US_RIIC             (0x1 << 16) // (USART) Ring INdicator Input Change Flag\n#define AT91C_US_DSRIC            (0x1 << 17) // (USART) Data Set Ready Input Change Flag\n#define AT91C_US_DCDIC            (0x1 << 18) // (USART) Data Carrier Flag\n#define AT91C_US_CTSIC            (0x1 << 19) // (USART) Clear To Send Input Change Flag\n// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- \n// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- \n// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- \n#define AT91C_US_RI               (0x1 << 20) // (USART) Image of RI Input\n#define AT91C_US_DSR              (0x1 << 21) // (USART) Image of DSR Input\n#define AT91C_US_DCD              (0x1 << 22) // (USART) Image of DCD Input\n#define AT91C_US_CTS              (0x1 << 23) // (USART) Image of CTS Input\n\n// *****************************************************************************\n//              SOFTWARE API DEFINITION  FOR Two-wire Interface\n// *****************************************************************************\n// *** Register offset in AT91S_TWI structure ***\n#define TWI_CR          ( 0) // Control Register\n#define TWI_MMR         ( 4) // Master Mode Register\n#define TWI_SMR         ( 8) // Slave Mode Register\n#define TWI_IADR        (12) // Internal Address Register\n#define TWI_CWGR        (16) // Clock Waveform Generator Register\n#define TWI_SR          (32) // Status Register\n#define TWI_IER         (36) // Interrupt Enable Register\n#define TWI_IDR         (40) // Interrupt Disable Register\n#define TWI_IMR         (44) // Interrupt Mask Register\n#define TWI_RHR         (48) // Receive Holding Register\n#define TWI_THR         (52) // Transmit Holding Register\n// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- \n#define AT91C_TWI_START           (0x1 <<  0) // (TWI) Send a START Condition\n#define AT91C_TWI_STOP            (0x1 <<  1) // (TWI) Send a STOP Condition\n#define AT91C_TWI_MSEN            (0x1 <<  2) // (TWI) TWI Master Transfer Enabled\n#define AT91C_TWI_MSDIS           (0x1 <<  3) // (TWI) TWI Master Transfer Disabled\n#define AT91C_TWI_SVEN            (0x1 <<  4) // (TWI) TWI Slave Transfer Enabled\n#define AT91C_TWI_SVDIS           (0x1 <<  5) // (TWI) TWI Slave Transfer Disabled\n#define AT91C_TWI_SWRST           (0x1 <<  7) // (TWI) Software Reset\n// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- \n#define AT91C_TWI_IADRSZ          (0x3 <<  8) // (TWI) Internal Device Address Size\n#define \tAT91C_TWI_IADRSZ_NO                   (0x0 <<  8) // (TWI) No internal device address\n#define \tAT91C_TWI_IADRSZ_1_BYTE               (0x1 <<  8) // (TWI) One-byte internal device address\n#define \tAT91C_TWI_IADRSZ_2_BYTE               (0x2 <<  8) // (TWI) Two-byte internal device address\n#define \tAT91C_TWI_IADRSZ_3_BYTE               (0x3 <<  8) // (TWI) Three-byte internal device address\n#define AT91C_TWI_MREAD           (0x1 << 12) // (TWI) Master Read Direction\n#define AT91C_TWI_DADR            (0x7F << 16) // (TWI) Device Address\n// -------- TWI_SMR : (TWI Offset: 0x8) TWI Slave Mode Register -------- \n#define AT91C_TWI_SADR            (0x7F << 16) // (TWI) Slave Device Address\n// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- \n#define AT91C_TWI_CLDIV           (0xFF <<  0) // (TWI) Clock Low Divider\n#define AT91C_TWI_CHDIV           (0xFF <<  8) // (TWI) Clock High Divider\n#define AT91C_TWI_CKDIV           (0x7 << 16) // (TWI) Clock Divider\n// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- \n#define AT91C_TWI_TXCOMP          (0x1 <<  0) // (TWI) Transmission Completed\n#define AT91C_TWI_RXRDY           (0x1 <<  1) // (TWI) Receive holding register ReaDY\n#define AT91C_TWI_TXRDY           (0x1 <<  2) // (TWI) Transmit holding register ReaDY\n#define AT91C_TWI_SVREAD          (0x1 <<  3) // (TWI) Slave Read\n#define AT91C_TWI_SVACC           (0x1 <<  4) // (TWI) Slave Access\n#define AT91C_TWI_GCACC           (0x1 <<  5) // (TWI) General Call Access\n#define AT91C_TWI_OVRE            (0x1 <<  6) // (TWI) Overrun Error\n#define AT91C_TWI_UNRE            (0x1 <<  7) // (TWI) Underrun Error\n#define AT91C_TWI_NACK            (0x1 <<  8) // (TWI) Not Acknowledged\n#define AT91C_TWI_ARBLST          (0x1 <<  9) // (TWI) Arbitration Lost\n// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- \n// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- \n// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- \n\n// *****************************************************************************\n//              SOFTWARE API DEFINITION  FOR Multimedia Card Interface\n// *****************************************************************************\n// *** Register offset in AT91S_MCI structure ***\n#define MCI_CR          ( 0) // MCI Control Register\n#define MCI_MR          ( 4) // MCI Mode Register\n#define MCI_DTOR        ( 8) // MCI Data Timeout Register\n#define MCI_SDCR        (12) // MCI SD Card Register\n#define MCI_ARGR        (16) // MCI Argument Register\n#define MCI_CMDR        (20) // MCI Command Register\n#define MCI_RSPR        (32) // MCI Response Register\n#define MCI_RDR         (48) // MCI Receive Data Register\n#define MCI_TDR         (52) // MCI Transmit Data Register\n#define MCI_SR          (64) // MCI Status Register\n#define MCI_IER         (68) // MCI Interrupt Enable Register\n#define MCI_IDR         (72) // MCI Interrupt Disable Register\n#define MCI_IMR         (76) // MCI Interrupt Mask Register\n#define MCI_RPR         (256) // Receive Pointer Register\n#define MCI_RCR         (260) // Receive Counter Register\n#define MCI_TPR         (264) // Transmit Pointer Register\n#define MCI_TCR         (268) // Transmit Counter Register\n#define MCI_RNPR        (272) // Receive Next Pointer Register\n#define MCI_RNCR        (276) // Receive Next Counter Register\n#define MCI_TNPR        (280) // Transmit Next Pointer Register\n#define MCI_TNCR        (284) // Transmit Next Counter Register\n#define MCI_PTCR        (288) // PDC Transfer Control Register\n#define MCI_PTSR        (292) // PDC Transfer Status Register\n// -------- MCI_CR : (MCI Offset: 0x0) MCI Control Register -------- \n#define AT91C_MCI_MCIEN           (0x1 <<  0) // (MCI) Multimedia Interface Enable\n#define AT91C_MCI_MCIDIS          (0x1 <<  1) // (MCI) Multimedia Interface Disable\n#define AT91C_MCI_PWSEN           (0x1 <<  2) // (MCI) Power Save Mode Enable\n#define AT91C_MCI_PWSDIS          (0x1 <<  3) // (MCI) Power Save Mode Disable\n// -------- MCI_MR : (MCI Offset: 0x4) MCI Mode Register -------- \n#define AT91C_MCI_CLKDIV          (0x1 <<  0) // (MCI) Clock Divider\n#define AT91C_MCI_PWSDIV          (0x1 <<  8) // (MCI) Power Saving Divider\n#define AT91C_MCI_PDCPADV         (0x1 << 14) // (MCI) PDC Padding Value\n#define AT91C_MCI_PDCMODE         (0x1 << 15) // (MCI) PDC Oriented Mode\n#define AT91C_MCI_BLKLEN          (0x1 << 18) // (MCI) Data Block Length\n// -------- MCI_DTOR : (MCI Offset: 0x8) MCI Data Timeout Register -------- \n#define AT91C_MCI_DTOCYC          (0x1 <<  0) // (MCI) Data Timeout Cycle Number\n#define AT91C_MCI_DTOMUL          (0x7 <<  4) // (MCI) Data Timeout Multiplier\n#define \tAT91C_MCI_DTOMUL_1                    (0x0 <<  4) // (MCI) DTOCYC x 1\n#define \tAT91C_MCI_DTOMUL_16                   (0x1 <<  4) // (MCI) DTOCYC x 16\n#define \tAT91C_MCI_DTOMUL_128                  (0x2 <<  4) // (MCI) DTOCYC x 128\n#define \tAT91C_MCI_DTOMUL_256                  (0x3 <<  4) // (MCI) DTOCYC x 256\n#define \tAT91C_MCI_DTOMUL_1024                 (0x4 <<  4) // (MCI) DTOCYC x 1024\n#define \tAT91C_MCI_DTOMUL_4096                 (0x5 <<  4) // (MCI) DTOCYC x 4096\n#define \tAT91C_MCI_DTOMUL_65536                (0x6 <<  4) // (MCI) DTOCYC x 65536\n#define \tAT91C_MCI_DTOMUL_1048576              (0x7 <<  4) // (MCI) DTOCYC x 1048576\n// -------- MCI_SDCR : (MCI Offset: 0xc) MCI SD Card Register -------- \n#define AT91C_MCI_SCDSEL          (0x1 <<  0) // (MCI) SD Card Selector\n#define AT91C_MCI_SCDBUS          (0x1 <<  7) // (MCI) SD Card Bus Width\n// -------- MCI_CMDR : (MCI Offset: 0x14) MCI Command Register -------- \n#define AT91C_MCI_CMDNB           (0x1F <<  0) // (MCI) Command Number\n#define AT91C_MCI_RSPTYP          (0x3 <<  6) // (MCI) Response Type\n#define \tAT91C_MCI_RSPTYP_NO                   (0x0 <<  6) // (MCI) No response\n#define \tAT91C_MCI_RSPTYP_48                   (0x1 <<  6) // (MCI) 48-bit response\n#define \tAT91C_MCI_RSPTYP_136                  (0x2 <<  6) // (MCI) 136-bit response\n#define AT91C_MCI_SPCMD           (0x7 <<  8) // (MCI) Special CMD\n#define \tAT91C_MCI_SPCMD_NONE                 (0x0 <<  8) // (MCI) Not a special CMD\n#define \tAT91C_MCI_SPCMD_INIT                 (0x1 <<  8) // (MCI) Initialization CMD\n#define \tAT91C_MCI_SPCMD_SYNC                 (0x2 <<  8) // (MCI) Synchronized CMD\n#define \tAT91C_MCI_SPCMD_IT_CMD               (0x4 <<  8) // (MCI) Interrupt command\n#define \tAT91C_MCI_SPCMD_IT_REP               (0x5 <<  8) // (MCI) Interrupt response\n#define AT91C_MCI_OPDCMD          (0x1 << 11) // (MCI) Open Drain Command\n#define AT91C_MCI_MAXLAT          (0x1 << 12) // (MCI) Maximum Latency for Command to respond\n#define AT91C_MCI_TRCMD           (0x3 << 16) // (MCI) Transfer CMD\n#define \tAT91C_MCI_TRCMD_NO                   (0x0 << 16) // (MCI) No transfer\n#define \tAT91C_MCI_TRCMD_START                (0x1 << 16) // (MCI) Start transfer\n#define \tAT91C_MCI_TRCMD_STOP                 (0x2 << 16) // (MCI) Stop transfer\n#define AT91C_MCI_TRDIR           (0x1 << 18) // (MCI) Transfer Direction\n#define AT91C_MCI_TRTYP           (0x3 << 19) // (MCI) Transfer Type\n#define \tAT91C_MCI_TRTYP_BLOCK                (0x0 << 19) // (MCI) Block Transfer type\n#define \tAT91C_MCI_TRTYP_MULTIPLE             (0x1 << 19) // (MCI) Multiple Block transfer type\n#define \tAT91C_MCI_TRTYP_STREAM               (0x2 << 19) // (MCI) Stream transfer type\n// -------- MCI_SR : (MCI Offset: 0x40) MCI Status Register -------- \n#define AT91C_MCI_CMDRDY          (0x1 <<  0) // (MCI) Command Ready flag\n#define AT91C_MCI_RXRDY           (0x1 <<  1) // (MCI) RX Ready flag\n#define AT91C_MCI_TXRDY           (0x1 <<  2) // (MCI) TX Ready flag\n#define AT91C_MCI_BLKE            (0x1 <<  3) // (MCI) Data Block Transfer Ended flag\n#define AT91C_MCI_DTIP            (0x1 <<  4) // (MCI) Data Transfer in Progress flag\n#define AT91C_MCI_NOTBUSY         (0x1 <<  5) // (MCI) Data Line Not Busy flag\n#define AT91C_MCI_ENDRX           (0x1 <<  6) // (MCI) End of RX Buffer flag\n#define AT91C_MCI_ENDTX           (0x1 <<  7) // (MCI) End of TX Buffer flag\n#define AT91C_MCI_RXBUFF          (0x1 << 14) // (MCI) RX Buffer Full flag\n#define AT91C_MCI_TXBUFE          (0x1 << 15) // (MCI) TX Buffer Empty flag\n#define AT91C_MCI_RINDE           (0x1 << 16) // (MCI) Response Index Error flag\n#define AT91C_MCI_RDIRE           (0x1 << 17) // (MCI) Response Direction Error flag\n#define AT91C_MCI_RCRCE           (0x1 << 18) // (MCI) Response CRC Error flag\n#define AT91C_MCI_RENDE           (0x1 << 19) // (MCI) Response End Bit Error flag\n#define AT91C_MCI_RTOE            (0x1 << 20) // (MCI) Response Time-out Error flag\n#define AT91C_MCI_DCRCE           (0x1 << 21) // (MCI) data CRC Error flag\n#define AT91C_MCI_DTOE            (0x1 << 22) // (MCI) Data timeout Error flag\n#define AT91C_MCI_OVRE            (0x1 << 30) // (MCI) Overrun flag\n#define AT91C_MCI_UNRE            (0x1 << 31) // (MCI) Underrun flag\n// -------- MCI_IER : (MCI Offset: 0x44) MCI Interrupt Enable Register -------- \n// -------- MCI_IDR : (MCI Offset: 0x48) MCI Interrupt Disable Register -------- \n// -------- MCI_IMR : (MCI Offset: 0x4c) MCI Interrupt Mask Register -------- \n\n// *****************************************************************************\n//              SOFTWARE API DEFINITION  FOR USB Device Interface\n// *****************************************************************************\n// *** Register offset in AT91S_UDP structure ***\n#define UDP_NUM         ( 0) // Frame Number Register\n#define UDP_GLBSTATE    ( 4) // Global State Register\n#define UDP_FADDR       ( 8) // Function Address Register\n#define UDP_IER         (16) // Interrupt Enable Register\n#define UDP_IDR         (20) // Interrupt Disable Register\n#define UDP_IMR         (24) // Interrupt Mask Register\n#define UDP_ISR         (28) // Interrupt Status Register\n#define UDP_ICR         (32) // Interrupt Clear Register\n#define UDP_RSTEP       (40) // Reset Endpoint Register\n#define UDP_CSR         (48) // Endpoint Control and Status Register\n#define UDP_FDR         (80) // Endpoint FIFO Data Register\n// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- \n#define AT91C_UDP_FRM_NUM         (0x7FF <<  0) // (UDP) Frame Number as Defined in the Packet Field Formats\n#define AT91C_UDP_FRM_ERR         (0x1 << 16) // (UDP) Frame Error\n#define AT91C_UDP_FRM_OK          (0x1 << 17) // (UDP) Frame OK\n// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- \n#define AT91C_UDP_FADDEN          (0x1 <<  0) // (UDP) Function Address Enable\n#define AT91C_UDP_CONFG           (0x1 <<  1) // (UDP) Configured\n#define AT91C_UDP_RMWUPE          (0x1 <<  2) // (UDP) Remote Wake Up Enable\n#define AT91C_UDP_RSMINPR         (0x1 <<  3) // (UDP) A Resume Has Been Sent to the Host\n// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- \n#define AT91C_UDP_FADD            (0xFF <<  0) // (UDP) Function Address Value\n#define AT91C_UDP_FEN             (0x1 <<  8) // (UDP) Function Enable\n// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- \n#define AT91C_UDP_EPINT0          (0x1 <<  0) // (UDP) Endpoint 0 Interrupt\n#define AT91C_UDP_EPINT1          (0x1 <<  1) // (UDP) Endpoint 0 Interrupt\n#define AT91C_UDP_EPINT2          (0x1 <<  2) // (UDP) Endpoint 2 Interrupt\n#define AT91C_UDP_EPINT3          (0x1 <<  3) // (UDP) Endpoint 3 Interrupt\n#define AT91C_UDP_EPINT4          (0x1 <<  4) // (UDP) Endpoint 4 Interrupt\n#define AT91C_UDP_EPINT5          (0x1 <<  5) // (UDP) Endpoint 5 Interrupt\n#define AT91C_UDP_EPINT6          (0x1 <<  6) // (UDP) Endpoint 6 Interrupt\n#define AT91C_UDP_EPINT7          (0x1 <<  7) // (UDP) Endpoint 7 Interrupt\n#define AT91C_UDP_RXSUSP          (0x1 <<  8) // (UDP) USB Suspend Interrupt\n#define AT91C_UDP_RXRSM           (0x1 <<  9) // (UDP) USB Resume Interrupt\n#define AT91C_UDP_EXTRSM          (0x1 << 10) // (UDP) USB External Resume Interrupt\n#define AT91C_UDP_SOFINT          (0x1 << 11) // (UDP) USB Start Of frame Interrupt\n#define AT91C_UDP_WAKEUP          (0x1 << 13) // (UDP) USB Resume Interrupt\n// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- \n// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- \n// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- \n#define AT91C_UDP_ENDBUSRES       (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt\n// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- \n// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- \n#define AT91C_UDP_EP0             (0x1 <<  0) // (UDP) Reset Endpoint 0\n#define AT91C_UDP_EP1             (0x1 <<  1) // (UDP) Reset Endpoint 1\n#define AT91C_UDP_EP2             (0x1 <<  2) // (UDP) Reset Endpoint 2\n#define AT91C_UDP_EP3             (0x1 <<  3) // (UDP) Reset Endpoint 3\n#define AT91C_UDP_EP4             (0x1 <<  4) // (UDP) Reset Endpoint 4\n#define AT91C_UDP_EP5             (0x1 <<  5) // (UDP) Reset Endpoint 5\n#define AT91C_UDP_EP6             (0x1 <<  6) // (UDP) Reset Endpoint 6\n#define AT91C_UDP_EP7             (0x1 <<  7) // (UDP) Reset Endpoint 7\n// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- \n#define AT91C_UDP_TXCOMP          (0x1 <<  0) // (UDP) Generates an IN packet with data previously written in the DPR\n#define AT91C_UDP_RX_DATA_BK0     (0x1 <<  1) // (UDP) Receive Data Bank 0\n#define AT91C_UDP_RXSETUP         (0x1 <<  2) // (UDP) Sends STALL to the Host (Control endpoints)\n#define AT91C_UDP_ISOERROR        (0x1 <<  3) // (UDP) Isochronous error (Isochronous endpoints)\n#define AT91C_UDP_TXPKTRDY        (0x1 <<  4) // (UDP) Transmit Packet Ready\n#define AT91C_UDP_FORCESTALL      (0x1 <<  5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).\n#define AT91C_UDP_RX_DATA_BK1     (0x1 <<  6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).\n#define AT91C_UDP_DIR             (0x1 <<  7) // (UDP) Transfer Direction\n#define AT91C_UDP_EPTYPE          (0x7 <<  8) // (UDP) Endpoint type\n#define \tAT91C_UDP_EPTYPE_CTRL                 (0x0 <<  8) // (UDP) Control\n#define \tAT91C_UDP_EPTYPE_ISO_OUT              (0x1 <<  8) // (UDP) Isochronous OUT\n#define \tAT91C_UDP_EPTYPE_BULK_OUT             (0x2 <<  8) // (UDP) Bulk OUT\n#define \tAT91C_UDP_EPTYPE_INT_OUT              (0x3 <<  8) // (UDP) Interrupt OUT\n#define \tAT91C_UDP_EPTYPE_ISO_IN               (0x5 <<  8) // (UDP) Isochronous IN\n#define \tAT91C_UDP_EPTYPE_BULK_IN              (0x6 <<  8) // (UDP) Bulk IN\n#define \tAT91C_UDP_EPTYPE_INT_IN               (0x7 <<  8) // (UDP) Interrupt IN\n#define AT91C_UDP_DTGLE           (0x1 << 11) // (UDP) Data Toggle\n#define AT91C_UDP_EPEDS           (0x1 << 15) // (UDP) Endpoint Enable Disable\n#define AT91C_UDP_RXBYTECNT       (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO\n\n// *****************************************************************************\n//              SOFTWARE API DEFINITION  FOR Timer Counter Channel Interface\n// *****************************************************************************\n// *** Register offset in AT91S_TC structure ***\n#define TC_CCR          ( 0) // Channel Control Register\n#define TC_CMR          ( 4) // Channel Mode Register\n#define TC_CV           (16) // Counter Value\n#define TC_RA           (20) // Register A\n#define TC_RB           (24) // Register B\n#define TC_RC           (28) // Register C\n#define TC_SR           (32) // Status Register\n#define TC_IER          (36) // Interrupt Enable Register\n#define TC_IDR          (40) // Interrupt Disable Register\n#define TC_IMR          (44) // Interrupt Mask Register\n// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- \n#define AT91C_TC_CLKEN            (0x1 <<  0) // (TC) Counter Clock Enable Command\n#define AT91C_TC_CLKDIS           (0x1 <<  1) // (TC) Counter Clock Disable Command\n#define AT91C_TC_SWTRG            (0x1 <<  2) // (TC) Software Trigger Command\n// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- \n#define AT91C_TC_CPCSTOP          (0x1 <<  6) // (TC) Counter Clock Stopped with RC Compare\n#define AT91C_TC_CPCDIS           (0x1 <<  7) // (TC) Counter Clock Disable with RC Compare\n#define AT91C_TC_EEVTEDG          (0x3 <<  8) // (TC) External Event Edge Selection\n#define \tAT91C_TC_EEVTEDG_NONE                 (0x0 <<  8) // (TC) Edge: None\n#define \tAT91C_TC_EEVTEDG_RISING               (0x1 <<  8) // (TC) Edge: rising edge\n#define \tAT91C_TC_EEVTEDG_FALLING              (0x2 <<  8) // (TC) Edge: falling edge\n#define \tAT91C_TC_EEVTEDG_BOTH                 (0x3 <<  8) // (TC) Edge: each edge\n#define AT91C_TC_EEVT             (0x3 << 10) // (TC) External Event  Selection\n#define \tAT91C_TC_EEVT_NONE                 (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input\n#define \tAT91C_TC_EEVT_RISING               (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output\n#define \tAT91C_TC_EEVT_FALLING              (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output\n#define \tAT91C_TC_EEVT_BOTH                 (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output\n#define AT91C_TC_ENETRG           (0x1 << 12) // (TC) External Event Trigger enable\n#define AT91C_TC_WAVESEL          (0x3 << 13) // (TC) Waveform  Selection\n#define \tAT91C_TC_WAVESEL_UP                   (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare\n#define \tAT91C_TC_WAVESEL_UPDOWN               (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare\n#define \tAT91C_TC_WAVESEL_UP_AUTO              (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare\n#define \tAT91C_TC_WAVESEL_UPDOWN_AUTO          (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare\n#define AT91C_TC_CPCTRG           (0x1 << 14) // (TC) RC Compare Trigger Enable\n#define AT91C_TC_WAVE             (0x1 << 15) // (TC) \n#define AT91C_TC_ACPA             (0x3 << 16) // (TC) RA Compare Effect on TIOA\n#define \tAT91C_TC_ACPA_NONE                 (0x0 << 16) // (TC) Effect: none\n#define \tAT91C_TC_ACPA_SET                  (0x1 << 16) // (TC) Effect: set\n#define \tAT91C_TC_ACPA_CLEAR                (0x2 << 16) // (TC) Effect: clear\n#define \tAT91C_TC_ACPA_TOGGLE               (0x3 << 16) // (TC) Effect: toggle\n#define AT91C_TC_ACPC             (0x3 << 18) // (TC) RC Compare Effect on TIOA\n#define \tAT91C_TC_ACPC_NONE                 (0x0 << 18) // (TC) Effect: none\n#define \tAT91C_TC_ACPC_SET                  (0x1 << 18) // (TC) Effect: set\n#define \tAT91C_TC_ACPC_CLEAR                (0x2 << 18) // (TC) Effect: clear\n#define \tAT91C_TC_ACPC_TOGGLE               (0x3 << 18) // (TC) Effect: toggle\n#define AT91C_TC_AEEVT            (0x3 << 20) // (TC) External Event Effect on TIOA\n#define \tAT91C_TC_AEEVT_NONE                 (0x0 << 20) // (TC) Effect: none\n#define \tAT91C_TC_AEEVT_SET                  (0x1 << 20) // (TC) Effect: set\n#define \tAT91C_TC_AEEVT_CLEAR                (0x2 << 20) // (TC) Effect: clear\n#define \tAT91C_TC_AEEVT_TOGGLE               (0x3 << 20) // (TC) Effect: toggle\n#define AT91C_TC_ASWTRG           (0x3 << 22) // (TC) Software Trigger Effect on TIOA\n#define \tAT91C_TC_ASWTRG_NONE                 (0x0 << 22) // (TC) Effect: none\n#define \tAT91C_TC_ASWTRG_SET                  (0x1 << 22) // (TC) Effect: set\n#define \tAT91C_TC_ASWTRG_CLEAR                (0x2 << 22) // (TC) Effect: clear\n#define \tAT91C_TC_ASWTRG_TOGGLE               (0x3 << 22) // (TC) Effect: toggle\n#define AT91C_TC_BCPB             (0x3 << 24) // (TC) RB Compare Effect on TIOB\n#define \tAT91C_TC_BCPB_NONE                 (0x0 << 24) // (TC) Effect: none\n#define \tAT91C_TC_BCPB_SET                  (0x1 << 24) // (TC) Effect: set\n#define \tAT91C_TC_BCPB_CLEAR                (0x2 << 24) // (TC) Effect: clear\n#define \tAT91C_TC_BCPB_TOGGLE               (0x3 << 24) // (TC) Effect: toggle\n#define AT91C_TC_BCPC             (0x3 << 26) // (TC) RC Compare Effect on TIOB\n#define \tAT91C_TC_BCPC_NONE                 (0x0 << 26) // (TC) Effect: none\n#define \tAT91C_TC_BCPC_SET                  (0x1 << 26) // (TC) Effect: set\n#define \tAT91C_TC_BCPC_CLEAR                (0x2 << 26) // (TC) Effect: clear\n#define \tAT91C_TC_BCPC_TOGGLE               (0x3 << 26) // (TC) Effect: toggle\n#define AT91C_TC_BEEVT            (0x3 << 28) // (TC) External Event Effect on TIOB\n#define \tAT91C_TC_BEEVT_NONE                 (0x0 << 28) // (TC) Effect: none\n#define \tAT91C_TC_BEEVT_SET                  (0x1 << 28) // (TC) Effect: set\n#define \tAT91C_TC_BEEVT_CLEAR                (0x2 << 28) // (TC) Effect: clear\n#define \tAT91C_TC_BEEVT_TOGGLE               (0x3 << 28) // (TC) Effect: toggle\n#define AT91C_TC_BSWTRG           (0x3 << 30) // (TC) Software Trigger Effect on TIOB\n#define \tAT91C_TC_BSWTRG_NONE                 (0x0 << 30) // (TC) Effect: none\n#define \tAT91C_TC_BSWTRG_SET                  (0x1 << 30) // (TC) Effect: set\n#define \tAT91C_TC_BSWTRG_CLEAR                (0x2 << 30) // (TC) Effect: clear\n#define \tAT91C_TC_BSWTRG_TOGGLE               (0x3 << 30) // (TC) Effect: toggle\n// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- \n#define AT91C_TC_COVFS            (0x1 <<  0) // (TC) Counter Overflow\n#define AT91C_TC_LOVRS            (0x1 <<  1) // (TC) Load Overrun\n#define AT91C_TC_CPAS             (0x1 <<  2) // (TC) RA Compare\n#define AT91C_TC_CPBS             (0x1 <<  3) // (TC) RB Compare\n#define AT91C_TC_CPCS             (0x1 <<  4) // (TC) RC Compare\n#define AT91C_TC_LDRAS            (0x1 <<  5) // (TC) RA Loading\n#define AT91C_TC_LDRBS            (0x1 <<  6) // (TC) RB Loading\n#define AT91C_TC_ETRCS            (0x1 <<  7) // (TC) External Trigger\n#define AT91C_TC_ETRGS            (0x1 << 16) // (TC) Clock Enabling\n#define AT91C_TC_MTIOA            (0x1 << 17) // (TC) TIOA Mirror\n#define AT91C_TC_MTIOB            (0x1 << 18) // (TC) TIOA Mirror\n// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- \n// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- \n// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- \n\n// *****************************************************************************\n//              SOFTWARE API DEFINITION  FOR Timer Counter Interface\n// *****************************************************************************\n// *** Register offset in AT91S_TCB structure ***\n#define TCB_TC0         ( 0) // TC Channel 0\n#define TCB_TC1         (64) // TC Channel 1\n#define TCB_TC2         (128) // TC Channel 2\n#define TCB_BCR         (192) // TC Block Control Register\n#define TCB_BMR         (196) // TC Block Mode Register\n// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- \n#define AT91C_TCB_SYNC            (0x1 <<  0) // (TCB) Synchro Command\n// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- \n#define AT91C_TCB_TC0XC0S         (0x1 <<  0) // (TCB) External Clock Signal 0 Selection\n#define \tAT91C_TCB_TC0XC0S_TCLK0                (0x0) // (TCB) TCLK0 connected to XC0\n#define \tAT91C_TCB_TC0XC0S_NONE                 (0x1) // (TCB) None signal connected to XC0\n#define \tAT91C_TCB_TC0XC0S_TIOA1                (0x2) // (TCB) TIOA1 connected to XC0\n#define \tAT91C_TCB_TC0XC0S_TIOA2                (0x3) // (TCB) TIOA2 connected to XC0\n#define AT91C_TCB_TC1XC1S         (0x1 <<  2) // (TCB) External Clock Signal 1 Selection\n#define \tAT91C_TCB_TC1XC1S_TCLK1                (0x0 <<  2) // (TCB) TCLK1 connected to XC1\n#define \tAT91C_TCB_TC1XC1S_NONE                 (0x1 <<  2) // (TCB) None signal connected to XC1\n#define \tAT91C_TCB_TC1XC1S_TIOA0                (0x2 <<  2) // (TCB) TIOA0 connected to XC1\n#define \tAT91C_TCB_TC1XC1S_TIOA2                (0x3 <<  2) // (TCB) TIOA2 connected to XC1\n#define AT91C_TCB_TC2XC2S         (0x1 <<  4) // (TCB) External Clock Signal 2 Selection\n#define \tAT91C_TCB_TC2XC2S_TCLK2                (0x0 <<  4) // (TCB) TCLK2 connected to XC2\n#define \tAT91C_TCB_TC2XC2S_NONE                 (0x1 <<  4) // (TCB) None signal connected to XC2\n#define \tAT91C_TCB_TC2XC2S_TIOA0                (0x2 <<  4) // (TCB) TIOA0 connected to XC2\n#define \tAT91C_TCB_TC2XC2S_TIOA2                (0x3 <<  4) // (TCB) TIOA2 connected to XC2\n\n// *****************************************************************************\n//              SOFTWARE API DEFINITION  FOR USB Host Interface\n// *****************************************************************************\n// *** Register offset in AT91S_UHP structure ***\n#define UHP_HcRevision  ( 0) // Revision\n#define UHP_HcControl   ( 4) // Operating modes for the Host Controller\n#define UHP_HcCommandStatus ( 8) // Command & status Register\n#define UHP_HcInterruptStatus (12) // Interrupt Status Register\n#define UHP_HcInterruptEnable (16) // Interrupt Enable Register\n#define UHP_HcInterruptDisable (20) // Interrupt Disable Register\n#define UHP_HcHCCA      (24) // Pointer to the Host Controller Communication Area\n#define UHP_HcPeriodCurrentED (28) // Current Isochronous or Interrupt Endpoint Descriptor\n#define UHP_HcControlHeadED (32) // First Endpoint Descriptor of the Control list\n#define UHP_HcControlCurrentED (36) // Endpoint Control and Status Register\n#define UHP_HcBulkHeadED (40) // First endpoint register of the Bulk list\n#define UHP_HcBulkCurrentED (44) // Current endpoint of the Bulk list\n#define UHP_HcBulkDoneHead (48) // Last completed transfer descriptor\n#define UHP_HcFmInterval (52) // Bit time between 2 consecutive SOFs\n#define UHP_HcFmRemaining (56) // Bit time remaining in the current Frame\n#define UHP_HcFmNumber  (60) // Frame number\n#define UHP_HcPeriodicStart (64) // Periodic Start\n#define UHP_HcLSThreshold (68) // LS Threshold\n#define UHP_HcRhDescriptorA (72) // Root Hub characteristics A\n#define UHP_HcRhDescriptorB (76) // Root Hub characteristics B\n#define UHP_HcRhStatus  (80) // Root Hub Status register\n#define UHP_HcRhPortStatus (84) // Root Hub Port Status Register\n\n// *****************************************************************************\n//              SOFTWARE API DEFINITION  FOR Ethernet MAC\n// *****************************************************************************\n// *** Register offset in AT91S_EMAC structure ***\n#define EMAC_CTL        ( 0) // Network Control Register\n#define EMAC_CFG        ( 4) // Network Configuration Register\n#define EMAC_SR         ( 8) // Network Status Register\n#define EMAC_TAR        (12) // Transmit Address Register\n#define EMAC_TCR        (16) // Transmit Control Register\n#define EMAC_TSR        (20) // Transmit Status Register\n#define EMAC_RBQP       (24) // Receive Buffer Queue Pointer\n#define EMAC_RSR        (32) // Receive Status Register\n#define EMAC_ISR        (36) // Interrupt Status Register\n#define EMAC_IER        (40) // Interrupt Enable Register\n#define EMAC_IDR        (44) // Interrupt Disable Register\n#define EMAC_IMR        (48) // Interrupt Mask Register\n#define EMAC_MAN        (52) // PHY Maintenance Register\n#define EMAC_FRA        (64) // Frames Transmitted OK Register\n#define EMAC_SCOL       (68) // Single Collision Frame Register\n#define EMAC_MCOL       (72) // Multiple Collision Frame Register\n#define EMAC_OK         (76) // Frames Received OK Register\n#define EMAC_SEQE       (80) // Frame Check Sequence Error Register\n#define EMAC_ALE        (84) // Alignment Error Register\n#define EMAC_DTE        (88) // Deferred Transmission Frame Register\n#define EMAC_LCOL       (92) // Late Collision Register\n#define EMAC_ECOL       (96) // Excessive Collision Register\n#define EMAC_CSE        (100) // Carrier Sense Error Register\n#define EMAC_TUE        (104) // Transmit Underrun Error Register\n#define EMAC_CDE        (108) // Code Error Register\n#define EMAC_ELR        (112) // Excessive Length Error Register\n#define EMAC_RJB        (116) // Receive Jabber Register\n#define EMAC_USF        (120) // Undersize Frame Register\n#define EMAC_SQEE       (124) // SQE Test Error Register\n#define EMAC_DRFC       (128) // Discarded RX Frame Register\n#define EMAC_HSH        (144) // Hash Address High[63:32]\n#define EMAC_HSL        (148) // Hash Address Low[31:0]\n#define EMAC_SA1L       (152) // Specific Address 1 Low, First 4 bytes\n#define EMAC_SA1H       (156) // Specific Address 1 High, Last 2 bytes\n#define EMAC_SA2L       (160) // Specific Address 2 Low, First 4 bytes\n#define EMAC_SA2H       (164) // Specific Address 2 High, Last 2 bytes\n#define EMAC_SA3L       (168) // Specific Address 3 Low, First 4 bytes\n#define EMAC_SA3H       (172) // Specific Address 3 High, Last 2 bytes\n#define EMAC_SA4L       (176) // Specific Address 4 Low, First 4 bytes\n#define EMAC_SA4H       (180) // Specific Address 4 High, Last 2 bytesr\n// -------- EMAC_CTL : (EMAC Offset: 0x0)  -------- \n#define AT91C_EMAC_LB             (0x1 <<  0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level.\n#define AT91C_EMAC_LBL            (0x1 <<  1) // (EMAC) Loopback local. \n#define AT91C_EMAC_RE             (0x1 <<  2) // (EMAC) Receive enable. \n#define AT91C_EMAC_TE             (0x1 <<  3) // (EMAC) Transmit enable. \n#define AT91C_EMAC_MPE            (0x1 <<  4) // (EMAC) Management port enable. \n#define AT91C_EMAC_CSR            (0x1 <<  5) // (EMAC) Clear statistics registers. \n#define AT91C_EMAC_ISR            (0x1 <<  6) // (EMAC) Increment statistics registers. \n#define AT91C_EMAC_WES            (0x1 <<  7) // (EMAC) Write enable for statistics registers. \n#define AT91C_EMAC_BP             (0x1 <<  8) // (EMAC) Back pressure. \n// -------- EMAC_CFG : (EMAC Offset: 0x4) Network Configuration Register -------- \n#define AT91C_EMAC_SPD            (0x1 <<  0) // (EMAC) Speed. \n#define AT91C_EMAC_FD             (0x1 <<  1) // (EMAC) Full duplex. \n#define AT91C_EMAC_BR             (0x1 <<  2) // (EMAC) Bit rate. \n#define AT91C_EMAC_CAF            (0x1 <<  4) // (EMAC) Copy all frames. \n#define AT91C_EMAC_NBC            (0x1 <<  5) // (EMAC) No broadcast. \n#define AT91C_EMAC_MTI            (0x1 <<  6) // (EMAC) Multicast hash enable\n#define AT91C_EMAC_UNI            (0x1 <<  7) // (EMAC) Unicast hash enable. \n#define AT91C_EMAC_BIG            (0x1 <<  8) // (EMAC) Receive 1522 bytes. \n#define AT91C_EMAC_EAE            (0x1 <<  9) // (EMAC) External address match enable. \n#define AT91C_EMAC_CLK            (0x3 << 10) // (EMAC) \n#define \tAT91C_EMAC_CLK_HCLK_8               (0x0 << 10) // (EMAC) HCLK divided by 8\n#define \tAT91C_EMAC_CLK_HCLK_16              (0x1 << 10) // (EMAC) HCLK divided by 16\n#define \tAT91C_EMAC_CLK_HCLK_32              (0x2 << 10) // (EMAC) HCLK divided by 32\n#define \tAT91C_EMAC_CLK_HCLK_64              (0x3 << 10) // (EMAC) HCLK divided by 64\n#define AT91C_EMAC_RTY            (0x1 << 12) // (EMAC) \n#define AT91C_EMAC_RMII           (0x1 << 13) // (EMAC) \n// -------- EMAC_SR : (EMAC Offset: 0x8) Network Status Register -------- \n#define AT91C_EMAC_MDIO           (0x1 <<  1) // (EMAC) \n#define AT91C_EMAC_IDLE           (0x1 <<  2) // (EMAC) \n// -------- EMAC_TCR : (EMAC Offset: 0x10) Transmit Control Register -------- \n#define AT91C_EMAC_LEN            (0x7FF <<  0) // (EMAC) \n#define AT91C_EMAC_NCRC           (0x1 << 15) // (EMAC) \n// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Control Register -------- \n#define AT91C_EMAC_OVR            (0x1 <<  0) // (EMAC) \n#define AT91C_EMAC_COL            (0x1 <<  1) // (EMAC) \n#define AT91C_EMAC_RLE            (0x1 <<  2) // (EMAC) \n#define AT91C_EMAC_TXIDLE         (0x1 <<  3) // (EMAC) \n#define AT91C_EMAC_BNQ            (0x1 <<  4) // (EMAC) \n#define AT91C_EMAC_COMP           (0x1 <<  5) // (EMAC) \n#define AT91C_EMAC_UND            (0x1 <<  6) // (EMAC) \n// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- \n#define AT91C_EMAC_BNA            (0x1 <<  0) // (EMAC) \n#define AT91C_EMAC_REC            (0x1 <<  1) // (EMAC) \n// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- \n#define AT91C_EMAC_DONE           (0x1 <<  0) // (EMAC) \n#define AT91C_EMAC_RCOM           (0x1 <<  1) // (EMAC) \n#define AT91C_EMAC_RBNA           (0x1 <<  2) // (EMAC) \n#define AT91C_EMAC_TOVR           (0x1 <<  3) // (EMAC) \n#define AT91C_EMAC_TUND           (0x1 <<  4) // (EMAC) \n#define AT91C_EMAC_RTRY           (0x1 <<  5) // (EMAC) \n#define AT91C_EMAC_TBRE           (0x1 <<  6) // (EMAC) \n#define AT91C_EMAC_TCOM           (0x1 <<  7) // (EMAC) \n#define AT91C_EMAC_TIDLE          (0x1 <<  8) // (EMAC) \n#define AT91C_EMAC_LINK           (0x1 <<  9) // (EMAC) \n#define AT91C_EMAC_ROVR           (0x1 << 10) // (EMAC) \n#define AT91C_EMAC_HRESP          (0x1 << 11) // (EMAC) \n// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- \n// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- \n// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- \n// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- \n#define AT91C_EMAC_DATA           (0xFFFF <<  0) // (EMAC) \n#define AT91C_EMAC_CODE           (0x3 << 16) // (EMAC) \n#define AT91C_EMAC_REGA           (0x1F << 18) // (EMAC) \n#define AT91C_EMAC_PHYA           (0x1F << 23) // (EMAC) \n#define AT91C_EMAC_RW             (0x3 << 28) // (EMAC) \n#define AT91C_EMAC_HIGH           (0x1 << 30) // (EMAC) \n#define AT91C_EMAC_LOW            (0x1 << 31) // (EMAC) \n\n// *****************************************************************************\n//              SOFTWARE API DEFINITION  FOR External Bus Interface\n// *****************************************************************************\n// *** Register offset in AT91S_EBI structure ***\n#define EBI_CSA         ( 0) // Chip Select Assignment Register\n#define EBI_CFGR        ( 4) // Configuration Register\n// -------- EBI_CSA : (EBI Offset: 0x0) Chip Select Assignment Register -------- \n#define AT91C_EBI_CS0A            (0x1 <<  0) // (EBI) Chip Select 0 Assignment\n#define \tAT91C_EBI_CS0A_SMC                  (0x0) // (EBI) Chip Select 0 is assigned to the Static Memory Controller.\n#define \tAT91C_EBI_CS0A_BFC                  (0x1) // (EBI) Chip Select 0 is assigned to the Burst Flash Controller.\n#define AT91C_EBI_CS1A            (0x1 <<  1) // (EBI) Chip Select 1 Assignment\n#define \tAT91C_EBI_CS1A_SMC                  (0x0 <<  1) // (EBI) Chip Select 1 is assigned to the Static Memory Controller.\n#define \tAT91C_EBI_CS1A_SDRAMC               (0x1 <<  1) // (EBI) Chip Select 1 is assigned to the SDRAM Controller.\n#define AT91C_EBI_CS3A            (0x1 <<  3) // (EBI) Chip Select 3 Assignment\n#define \tAT91C_EBI_CS3A_SMC                  (0x0 <<  3) // (EBI) Chip Select 3 is only assigned to the Static Memory Controller and NCS3 behaves as defined by the SMC2.\n#define \tAT91C_EBI_CS3A_SMC_SmartMedia       (0x1 <<  3) // (EBI) Chip Select 3 is assigned to the Static Memory Controller and the SmartMedia Logic is activated.\n#define AT91C_EBI_CS4A            (0x1 <<  4) // (EBI) Chip Select 4 Assignment\n#define \tAT91C_EBI_CS4A_SMC                  (0x0 <<  4) // (EBI) Chip Select 4 is assigned to the Static Memory Controller and NCS4,NCS5 and NCS6 behave as defined by the SMC2.\n#define \tAT91C_EBI_CS4A_SMC_CompactFlash     (0x1 <<  4) // (EBI) Chip Select 4 is assigned to the Static Memory Controller and the CompactFlash Logic is activated.\n// -------- EBI_CFGR : (EBI Offset: 0x4) Configuration Register -------- \n#define AT91C_EBI_DBPUC           (0x1 <<  0) // (EBI) Data Bus Pull-Up Configuration\n#define AT91C_EBI_EBSEN           (0x1 <<  1) // (EBI) Bus Sharing Enable\n\n// *****************************************************************************\n//              SOFTWARE API DEFINITION  FOR Static Memory Controller 2 Interface\n// *****************************************************************************\n// *** Register offset in AT91S_SMC2 structure ***\n#define SMC2_CSR        ( 0) // SMC2 Chip Select Register\n// -------- SMC2_CSR : (SMC2 Offset: 0x0) SMC2 Chip Select Register -------- \n#define AT91C_SMC2_NWS            (0x7F <<  0) // (SMC2) Number of Wait States\n#define AT91C_SMC2_WSEN           (0x1 <<  7) // (SMC2) Wait State Enable\n#define AT91C_SMC2_TDF            (0xF <<  8) // (SMC2) Data Float Time\n#define AT91C_SMC2_BAT            (0x1 << 12) // (SMC2) Byte Access Type\n#define AT91C_SMC2_DBW            (0x1 << 13) // (SMC2) Data Bus Width\n#define \tAT91C_SMC2_DBW_16                   (0x1 << 13) // (SMC2) 16-bit.\n#define \tAT91C_SMC2_DBW_8                    (0x2 << 13) // (SMC2) 8-bit.\n#define AT91C_SMC2_DRP            (0x1 << 15) // (SMC2) Data Read Protocol\n#define AT91C_SMC2_ACSS           (0x3 << 16) // (SMC2) Address to Chip Select Setup\n#define \tAT91C_SMC2_ACSS_STANDARD             (0x0 << 16) // (SMC2) Standard, asserted at the beginning of the access and deasserted at the end.\n#define \tAT91C_SMC2_ACSS_1_CYCLE              (0x1 << 16) // (SMC2) One cycle less at the beginning and the end of the access.\n#define \tAT91C_SMC2_ACSS_2_CYCLES             (0x2 << 16) // (SMC2) Two cycles less at the beginning and the end of the access.\n#define \tAT91C_SMC2_ACSS_3_CYCLES             (0x3 << 16) // (SMC2) Three cycles less at the beginning and the end of the access.\n#define AT91C_SMC2_RWSETUP        (0x7 << 24) // (SMC2) Read and Write Signal Setup Time\n#define AT91C_SMC2_RWHOLD         (0x7 << 29) // (SMC2) Read and Write Signal Hold Time\n\n// *****************************************************************************\n//              SOFTWARE API DEFINITION  FOR SDRAM Controller Interface\n// *****************************************************************************\n// *** Register offset in AT91S_SDRC structure ***\n#define SDRC_MR         ( 0) // SDRAM Controller Mode Register\n#define SDRC_TR         ( 4) // SDRAM Controller Refresh Timer Register\n#define SDRC_CR         ( 8) // SDRAM Controller Configuration Register\n#define SDRC_SRR        (12) // SDRAM Controller Self Refresh Register\n#define SDRC_LPR        (16) // SDRAM Controller Low Power Register\n#define SDRC_IER        (20) // SDRAM Controller Interrupt Enable Register\n#define SDRC_IDR        (24) // SDRAM Controller Interrupt Disable Register\n#define SDRC_IMR        (28) // SDRAM Controller Interrupt Mask Register\n#define SDRC_ISR        (32) // SDRAM Controller Interrupt Mask Register\n// -------- SDRC_MR : (SDRC Offset: 0x0) SDRAM Controller Mode Register -------- \n#define AT91C_SDRC_MODE           (0xF <<  0) // (SDRC) Mode\n#define \tAT91C_SDRC_MODE_NORMAL_CMD           (0x0) // (SDRC) Normal Mode\n#define \tAT91C_SDRC_MODE_NOP_CMD              (0x1) // (SDRC) NOP Command\n#define \tAT91C_SDRC_MODE_PRCGALL_CMD          (0x2) // (SDRC) All Banks Precharge Command\n#define \tAT91C_SDRC_MODE_LMR_CMD              (0x3) // (SDRC) Load Mode Register Command\n#define \tAT91C_SDRC_MODE_RFSH_CMD             (0x4) // (SDRC) Refresh Command\n#define AT91C_SDRC_DBW            (0x1 <<  4) // (SDRC) Data Bus Width\n#define \tAT91C_SDRC_DBW_32_BITS              (0x0 <<  4) // (SDRC) 32 Bits datas bus\n#define \tAT91C_SDRC_DBW_16_BITS              (0x1 <<  4) // (SDRC) 16 Bits datas bus\n// -------- SDRC_TR : (SDRC Offset: 0x4) SDRC Refresh Timer Register -------- \n#define AT91C_SDRC_COUNT          (0xFFF <<  0) // (SDRC) Refresh Counter\n// -------- SDRC_CR : (SDRC Offset: 0x8) SDRAM Configuration Register -------- \n#define AT91C_SDRC_NC             (0x3 <<  0) // (SDRC) Number of Column Bits\n#define \tAT91C_SDRC_NC_8                    (0x0) // (SDRC) 8 Bits\n#define \tAT91C_SDRC_NC_9                    (0x1) // (SDRC) 9 Bits\n#define \tAT91C_SDRC_NC_10                   (0x2) // (SDRC) 10 Bits\n#define \tAT91C_SDRC_NC_11                   (0x3) // (SDRC) 11 Bits\n#define AT91C_SDRC_NR             (0x3 <<  2) // (SDRC) Number of Row Bits\n#define \tAT91C_SDRC_NR_11                   (0x0 <<  2) // (SDRC) 11 Bits\n#define \tAT91C_SDRC_NR_12                   (0x1 <<  2) // (SDRC) 12 Bits\n#define \tAT91C_SDRC_NR_13                   (0x2 <<  2) // (SDRC) 13 Bits\n#define AT91C_SDRC_NB             (0x1 <<  4) // (SDRC) Number of Banks\n#define \tAT91C_SDRC_NB_2_BANKS              (0x0 <<  4) // (SDRC) 2 banks\n#define \tAT91C_SDRC_NB_4_BANKS              (0x1 <<  4) // (SDRC) 4 banks\n#define AT91C_SDRC_CAS            (0x3 <<  5) // (SDRC) CAS Latency\n#define \tAT91C_SDRC_CAS_2                    (0x2 <<  5) // (SDRC) 2 cycles\n#define AT91C_SDRC_TWR            (0xF <<  7) // (SDRC) Number of Write Recovery Time Cycles\n#define AT91C_SDRC_TRC            (0xF << 11) // (SDRC) Number of RAS Cycle Time Cycles\n#define AT91C_SDRC_TRP            (0xF << 15) // (SDRC) Number of RAS Precharge Time Cycles\n#define AT91C_SDRC_TRCD           (0xF << 19) // (SDRC) Number of RAS to CAS Delay Cycles\n#define AT91C_SDRC_TRAS           (0xF << 23) // (SDRC) Number of RAS Active Time Cycles\n#define AT91C_SDRC_TXSR           (0xF << 27) // (SDRC) Number of Command Recovery Time Cycles\n// -------- SDRC_SRR : (SDRC Offset: 0xc) SDRAM Controller Self-refresh Register -------- \n#define AT91C_SDRC_SRCB           (0x1 <<  0) // (SDRC) Self-refresh Command Bit\n// -------- SDRC_LPR : (SDRC Offset: 0x10) SDRAM Controller Low-power Register -------- \n#define AT91C_SDRC_LPCB           (0x1 <<  0) // (SDRC) Low-power Command Bit\n// -------- SDRC_IER : (SDRC Offset: 0x14) SDRAM Controller Interrupt Enable Register -------- \n#define AT91C_SDRC_RES            (0x1 <<  0) // (SDRC) Refresh Error Status\n// -------- SDRC_IDR : (SDRC Offset: 0x18) SDRAM Controller Interrupt Disable Register -------- \n// -------- SDRC_IMR : (SDRC Offset: 0x1c) SDRAM Controller Interrupt Mask Register -------- \n// -------- SDRC_ISR : (SDRC Offset: 0x20) SDRAM Controller Interrupt Status Register -------- \n\n// *****************************************************************************\n//              SOFTWARE API DEFINITION  FOR Burst Flash Controller Interface\n// *****************************************************************************\n// *** Register offset in AT91S_BFC structure ***\n#define BFC_MR          ( 0) // BFC Mode Register\n// -------- BFC_MR : (BFC Offset: 0x0) BFC Mode Register -------- \n#define AT91C_BFC_BFCOM           (0x3 <<  0) // (BFC) Burst Flash Controller Operating Mode\n#define \tAT91C_BFC_BFCOM_DISABLED             (0x0) // (BFC) NPCS0 is driven by the SMC or remains high.\n#define \tAT91C_BFC_BFCOM_ASYNC                (0x1) // (BFC) Asynchronous\n#define \tAT91C_BFC_BFCOM_BURST_READ           (0x2) // (BFC) Burst Read\n#define AT91C_BFC_BFCC            (0x3 <<  2) // (BFC) Burst Flash Controller Operating Mode\n#define \tAT91C_BFC_BFCC_MCK                  (0x1 <<  2) // (BFC) Master Clock.\n#define \tAT91C_BFC_BFCC_MCK_DIV_2            (0x2 <<  2) // (BFC) Master Clock divided by 2.\n#define \tAT91C_BFC_BFCC_MCK_DIV_4            (0x3 <<  2) // (BFC) Master Clock divided by 4.\n#define AT91C_BFC_AVL             (0xF <<  4) // (BFC) Address Valid Latency\n#define AT91C_BFC_PAGES           (0x7 <<  8) // (BFC) Page Size\n#define \tAT91C_BFC_PAGES_NO_PAGE              (0x0 <<  8) // (BFC) No page handling.\n#define \tAT91C_BFC_PAGES_16                   (0x1 <<  8) // (BFC) 16 bytes page size.\n#define \tAT91C_BFC_PAGES_32                   (0x2 <<  8) // (BFC) 32 bytes page size.\n#define \tAT91C_BFC_PAGES_64                   (0x3 <<  8) // (BFC) 64 bytes page size.\n#define \tAT91C_BFC_PAGES_128                  (0x4 <<  8) // (BFC) 128 bytes page size.\n#define \tAT91C_BFC_PAGES_256                  (0x5 <<  8) // (BFC) 256 bytes page size.\n#define \tAT91C_BFC_PAGES_512                  (0x6 <<  8) // (BFC) 512 bytes page size.\n#define \tAT91C_BFC_PAGES_1024                 (0x7 <<  8) // (BFC) 1024 bytes page size.\n#define AT91C_BFC_OEL             (0x3 << 12) // (BFC) Output Enable Latency\n#define AT91C_BFC_BAAEN           (0x1 << 16) // (BFC) Burst Address Advance Enable\n#define AT91C_BFC_BFOEH           (0x1 << 17) // (BFC) Burst Flash Output Enable Handling\n#define AT91C_BFC_MUXEN           (0x1 << 18) // (BFC) Multiplexed Bus Enable\n#define AT91C_BFC_RDYEN           (0x1 << 19) // (BFC) Ready Enable Mode\n\n// *****************************************************************************\n//               REGISTER ADDRESS DEFINITION FOR AT91RM9200\n// *****************************************************************************\n// ========== Register definition for SYS peripheral ========== \n// ========== Register definition for MC peripheral ========== \n#define AT91C_MC_PUER             (0xFFFFFF54) // (MC) MC Protection Unit Enable Register\n#define AT91C_MC_ASR              (0xFFFFFF04) // (MC) MC Abort Status Register\n#define AT91C_MC_PUP              (0xFFFFFF50) // (MC) MC Protection Unit Peripherals\n#define AT91C_MC_PUIA             (0xFFFFFF10) // (MC) MC Protection Unit Area\n#define AT91C_MC_AASR             (0xFFFFFF08) // (MC) MC Abort Address Status Register\n#define AT91C_MC_RCR              (0xFFFFFF00) // (MC) MC Remap Control Register\n// ========== Register definition for RTC peripheral ========== \n#define AT91C_RTC_IMR             (0xFFFFFE28) // (RTC) Interrupt Mask Register\n#define AT91C_RTC_IER             (0xFFFFFE20) // (RTC) Interrupt Enable Register\n#define AT91C_RTC_SR              (0xFFFFFE18) // (RTC) Status Register\n#define AT91C_RTC_TIMALR          (0xFFFFFE10) // (RTC) Time Alarm Register\n#define AT91C_RTC_TIMR            (0xFFFFFE08) // (RTC) Time Register\n#define AT91C_RTC_CR              (0xFFFFFE00) // (RTC) Control Register\n#define AT91C_RTC_VER             (0xFFFFFE2C) // (RTC) Valid Entry Register\n#define AT91C_RTC_IDR             (0xFFFFFE24) // (RTC) Interrupt Disable Register\n#define AT91C_RTC_SCCR            (0xFFFFFE1C) // (RTC) Status Clear Command Register\n#define AT91C_RTC_CALALR          (0xFFFFFE14) // (RTC) Calendar Alarm Register\n#define AT91C_RTC_CALR            (0xFFFFFE0C) // (RTC) Calendar Register\n#define AT91C_RTC_MR              (0xFFFFFE04) // (RTC) Mode Register\n// ========== Register definition for ST peripheral ========== \n#define AT91C_ST_CRTR             (0xFFFFFD24) // (ST) Current Real-time Register\n#define AT91C_ST_IMR              (0xFFFFFD1C) // (ST) Interrupt Mask Register\n#define AT91C_ST_IER              (0xFFFFFD14) // (ST) Interrupt Enable Register\n#define AT91C_ST_RTMR             (0xFFFFFD0C) // (ST) Real-time Mode Register\n#define AT91C_ST_PIMR             (0xFFFFFD04) // (ST) Period Interval Mode Register\n#define AT91C_ST_RTAR             (0xFFFFFD20) // (ST) Real-time Alarm Register\n#define AT91C_ST_IDR              (0xFFFFFD18) // (ST) Interrupt Disable Register\n#define AT91C_ST_SR               (0xFFFFFD10) // (ST) Status Register\n#define AT91C_ST_WDMR             (0xFFFFFD08) // (ST) Watchdog Mode Register\n#define AT91C_ST_CR               (0xFFFFFD00) // (ST) Control Register\n// ========== Register definition for PMC peripheral ========== \n#define AT91C_PMC_SCSR            (0xFFFFFC08) // (PMC) System Clock Status Register\n#define AT91C_PMC_SCER            (0xFFFFFC00) // (PMC) System Clock Enable Register\n#define AT91C_PMC_IMR             (0xFFFFFC6C) // (PMC) Interrupt Mask Register\n#define AT91C_PMC_IDR             (0xFFFFFC64) // (PMC) Interrupt Disable Register\n#define AT91C_PMC_PCDR            (0xFFFFFC14) // (PMC) Peripheral Clock Disable Register\n#define AT91C_PMC_SCDR            (0xFFFFFC04) // (PMC) System Clock Disable Register\n#define AT91C_PMC_SR              (0xFFFFFC68) // (PMC) Status Register\n#define AT91C_PMC_IER             (0xFFFFFC60) // (PMC) Interrupt Enable Register\n#define AT91C_PMC_MCKR            (0xFFFFFC30) // (PMC) Master Clock Register\n#define AT91C_PMC_PCER            (0xFFFFFC10) // (PMC) Peripheral Clock Enable Register\n#define AT91C_PMC_PCSR            (0xFFFFFC18) // (PMC) Peripheral Clock Status Register\n#define AT91C_PMC_PCKR            (0xFFFFFC40) // (PMC) Programmable Clock Register\n// ========== Register definition for CKGR peripheral ========== \n#define AT91C_CKGR_PLLBR          (0xFFFFFC2C) // (CKGR) PLL B Register\n#define AT91C_CKGR_MCFR           (0xFFFFFC24) // (CKGR) Main Clock  Frequency Register\n#define AT91C_CKGR_PLLAR          (0xFFFFFC28) // (CKGR) PLL A Register\n#define AT91C_CKGR_MOR            (0xFFFFFC20) // (CKGR) Main Oscillator Register\n// ========== Register definition for PIOD peripheral ========== \n#define AT91C_PIOD_PDSR           (0xFFFFFA3C) // (PIOD) Pin Data Status Register\n#define AT91C_PIOD_CODR           (0xFFFFFA34) // (PIOD) Clear Output Data Register\n#define AT91C_PIOD_OWER           (0xFFFFFAA0) // (PIOD) Output Write Enable Register\n#define AT91C_PIOD_MDER           (0xFFFFFA50) // (PIOD) Multi-driver Enable Register\n#define AT91C_PIOD_IMR            (0xFFFFFA48) // (PIOD) Interrupt Mask Register\n#define AT91C_PIOD_IER            (0xFFFFFA40) // (PIOD) Interrupt Enable Register\n#define AT91C_PIOD_ODSR           (0xFFFFFA38) // (PIOD) Output Data Status Register\n#define AT91C_PIOD_SODR           (0xFFFFFA30) // (PIOD) Set Output Data Register\n#define AT91C_PIOD_PER            (0xFFFFFA00) // (PIOD) PIO Enable Register\n#define AT91C_PIOD_OWDR           (0xFFFFFAA4) // (PIOD) Output Write Disable Register\n#define AT91C_PIOD_PPUER          (0xFFFFFA64) // (PIOD) Pull-up Enable Register\n#define AT91C_PIOD_MDDR           (0xFFFFFA54) // (PIOD) Multi-driver Disable Register\n#define AT91C_PIOD_ISR            (0xFFFFFA4C) // (PIOD) Interrupt Status Register\n#define AT91C_PIOD_IDR            (0xFFFFFA44) // (PIOD) Interrupt Disable Register\n#define AT91C_PIOD_PDR            (0xFFFFFA04) // (PIOD) PIO Disable Register\n#define AT91C_PIOD_ODR            (0xFFFFFA14) // (PIOD) Output Disable Registerr\n#define AT91C_PIOD_OWSR           (0xFFFFFAA8) // (PIOD) Output Write Status Register\n#define AT91C_PIOD_ABSR           (0xFFFFFA78) // (PIOD) AB Select Status Register\n#define AT91C_PIOD_ASR            (0xFFFFFA70) // (PIOD) Select A Register\n#define AT91C_PIOD_PPUSR          (0xFFFFFA68) // (PIOD) Pad Pull-up Status Register\n#define AT91C_PIOD_PPUDR          (0xFFFFFA60) // (PIOD) Pull-up Disable Register\n#define AT91C_PIOD_MDSR           (0xFFFFFA58) // (PIOD) Multi-driver Status Register\n#define AT91C_PIOD_PSR            (0xFFFFFA08) // (PIOD) PIO Status Register\n#define AT91C_PIOD_OER            (0xFFFFFA10) // (PIOD) Output Enable Register\n#define AT91C_PIOD_OSR            (0xFFFFFA18) // (PIOD) Output Status Register\n#define AT91C_PIOD_IFER           (0xFFFFFA20) // (PIOD) Input Filter Enable Register\n#define AT91C_PIOD_BSR            (0xFFFFFA74) // (PIOD) Select B Register\n#define AT91C_PIOD_IFDR           (0xFFFFFA24) // (PIOD) Input Filter Disable Register\n#define AT91C_PIOD_IFSR           (0xFFFFFA28) // (PIOD) Input Filter Status Register\n// ========== Register definition for PIOC peripheral ========== \n#define AT91C_PIOC_IFDR           (0xFFFFF824) // (PIOC) Input Filter Disable Register\n#define AT91C_PIOC_ODR            (0xFFFFF814) // (PIOC) Output Disable Registerr\n#define AT91C_PIOC_ABSR           (0xFFFFF878) // (PIOC) AB Select Status Register\n#define AT91C_PIOC_SODR           (0xFFFFF830) // (PIOC) Set Output Data Register\n#define AT91C_PIOC_IFSR           (0xFFFFF828) // (PIOC) Input Filter Status Register\n#define AT91C_PIOC_CODR           (0xFFFFF834) // (PIOC) Clear Output Data Register\n#define AT91C_PIOC_ODSR           (0xFFFFF838) // (PIOC) Output Data Status Register\n#define AT91C_PIOC_IER            (0xFFFFF840) // (PIOC) Interrupt Enable Register\n#define AT91C_PIOC_IMR            (0xFFFFF848) // (PIOC) Interrupt Mask Register\n#define AT91C_PIOC_OWDR           (0xFFFFF8A4) // (PIOC) Output Write Disable Register\n#define AT91C_PIOC_MDDR           (0xFFFFF854) // (PIOC) Multi-driver Disable Register\n#define AT91C_PIOC_PDSR           (0xFFFFF83C) // (PIOC) Pin Data Status Register\n#define AT91C_PIOC_IDR            (0xFFFFF844) // (PIOC) Interrupt Disable Register\n#define AT91C_PIOC_ISR            (0xFFFFF84C) // (PIOC) Interrupt Status Register\n#define AT91C_PIOC_PDR            (0xFFFFF804) // (PIOC) PIO Disable Register\n#define AT91C_PIOC_OWSR           (0xFFFFF8A8) // (PIOC) Output Write Status Register\n#define AT91C_PIOC_OWER           (0xFFFFF8A0) // (PIOC) Output Write Enable Register\n#define AT91C_PIOC_ASR            (0xFFFFF870) // (PIOC) Select A Register\n#define AT91C_PIOC_PPUSR          (0xFFFFF868) // (PIOC) Pad Pull-up Status Register\n#define AT91C_PIOC_PPUDR          (0xFFFFF860) // (PIOC) Pull-up Disable Register\n#define AT91C_PIOC_MDSR           (0xFFFFF858) // (PIOC) Multi-driver Status Register\n#define AT91C_PIOC_MDER           (0xFFFFF850) // (PIOC) Multi-driver Enable Register\n#define AT91C_PIOC_IFER           (0xFFFFF820) // (PIOC) Input Filter Enable Register\n#define AT91C_PIOC_OSR            (0xFFFFF818) // (PIOC) Output Status Register\n#define AT91C_PIOC_OER            (0xFFFFF810) // (PIOC) Output Enable Register\n#define AT91C_PIOC_PSR            (0xFFFFF808) // (PIOC) PIO Status Register\n#define AT91C_PIOC_PER            (0xFFFFF800) // (PIOC) PIO Enable Register\n#define AT91C_PIOC_BSR            (0xFFFFF874) // (PIOC) Select B Register\n#define AT91C_PIOC_PPUER          (0xFFFFF864) // (PIOC) Pull-up Enable Register\n// ========== Register definition for PIOB peripheral ========== \n#define AT91C_PIOB_OWSR           (0xFFFFF6A8) // (PIOB) Output Write Status Register\n#define AT91C_PIOB_PPUSR          (0xFFFFF668) // (PIOB) Pad Pull-up Status Register\n#define AT91C_PIOB_PPUDR          (0xFFFFF660) // (PIOB) Pull-up Disable Register\n#define AT91C_PIOB_MDSR           (0xFFFFF658) // (PIOB) Multi-driver Status Register\n#define AT91C_PIOB_MDER           (0xFFFFF650) // (PIOB) Multi-driver Enable Register\n#define AT91C_PIOB_IMR            (0xFFFFF648) // (PIOB) Interrupt Mask Register\n#define AT91C_PIOB_OSR            (0xFFFFF618) // (PIOB) Output Status Register\n#define AT91C_PIOB_OER            (0xFFFFF610) // (PIOB) Output Enable Register\n#define AT91C_PIOB_PSR            (0xFFFFF608) // (PIOB) PIO Status Register\n#define AT91C_PIOB_PER            (0xFFFFF600) // (PIOB) PIO Enable Register\n#define AT91C_PIOB_BSR            (0xFFFFF674) // (PIOB) Select B Register\n#define AT91C_PIOB_PPUER          (0xFFFFF664) // (PIOB) Pull-up Enable Register\n#define AT91C_PIOB_IFDR           (0xFFFFF624) // (PIOB) Input Filter Disable Register\n#define AT91C_PIOB_ODR            (0xFFFFF614) // (PIOB) Output Disable Registerr\n#define AT91C_PIOB_ABSR           (0xFFFFF678) // (PIOB) AB Select Status Register\n#define AT91C_PIOB_ASR            (0xFFFFF670) // (PIOB) Select A Register\n#define AT91C_PIOB_IFER           (0xFFFFF620) // (PIOB) Input Filter Enable Register\n#define AT91C_PIOB_IFSR           (0xFFFFF628) // (PIOB) Input Filter Status Register\n#define AT91C_PIOB_SODR           (0xFFFFF630) // (PIOB) Set Output Data Register\n#define AT91C_PIOB_ODSR           (0xFFFFF638) // (PIOB) Output Data Status Register\n#define AT91C_PIOB_CODR           (0xFFFFF634) // (PIOB) Clear Output Data Register\n#define AT91C_PIOB_PDSR           (0xFFFFF63C) // (PIOB) Pin Data Status Register\n#define AT91C_PIOB_OWER           (0xFFFFF6A0) // (PIOB) Output Write Enable Register\n#define AT91C_PIOB_IER            (0xFFFFF640) // (PIOB) Interrupt Enable Register\n#define AT91C_PIOB_OWDR           (0xFFFFF6A4) // (PIOB) Output Write Disable Register\n#define AT91C_PIOB_MDDR           (0xFFFFF654) // (PIOB) Multi-driver Disable Register\n#define AT91C_PIOB_ISR            (0xFFFFF64C) // (PIOB) Interrupt Status Register\n#define AT91C_PIOB_IDR            (0xFFFFF644) // (PIOB) Interrupt Disable Register\n#define AT91C_PIOB_PDR            (0xFFFFF604) // (PIOB) PIO Disable Register\n// ========== Register definition for PIOA peripheral ========== \n#define AT91C_PIOA_IMR            (0xFFFFF448) // (PIOA) Interrupt Mask Register\n#define AT91C_PIOA_IER            (0xFFFFF440) // (PIOA) Interrupt Enable Register\n#define AT91C_PIOA_OWDR           (0xFFFFF4A4) // (PIOA) Output Write Disable Register\n#define AT91C_PIOA_ISR            (0xFFFFF44C) // (PIOA) Interrupt Status Register\n#define AT91C_PIOA_PPUDR          (0xFFFFF460) // (PIOA) Pull-up Disable Register\n#define AT91C_PIOA_MDSR           (0xFFFFF458) // (PIOA) Multi-driver Status Register\n#define AT91C_PIOA_MDER           (0xFFFFF450) // (PIOA) Multi-driver Enable Register\n#define AT91C_PIOA_PER            (0xFFFFF400) // (PIOA) PIO Enable Register\n#define AT91C_PIOA_PSR            (0xFFFFF408) // (PIOA) PIO Status Register\n#define AT91C_PIOA_OER            (0xFFFFF410) // (PIOA) Output Enable Register\n#define AT91C_PIOA_BSR            (0xFFFFF474) // (PIOA) Select B Register\n#define AT91C_PIOA_PPUER          (0xFFFFF464) // (PIOA) Pull-up Enable Register\n#define AT91C_PIOA_MDDR           (0xFFFFF454) // (PIOA) Multi-driver Disable Register\n#define AT91C_PIOA_PDR            (0xFFFFF404) // (PIOA) PIO Disable Register\n#define AT91C_PIOA_ODR            (0xFFFFF414) // (PIOA) Output Disable Registerr\n#define AT91C_PIOA_IFDR           (0xFFFFF424) // (PIOA) Input Filter Disable Register\n#define AT91C_PIOA_ABSR           (0xFFFFF478) // (PIOA) AB Select Status Register\n#define AT91C_PIOA_ASR            (0xFFFFF470) // (PIOA) Select A Register\n#define AT91C_PIOA_PPUSR          (0xFFFFF468) // (PIOA) Pad Pull-up Status Register\n#define AT91C_PIOA_ODSR           (0xFFFFF438) // (PIOA) Output Data Status Register\n#define AT91C_PIOA_SODR           (0xFFFFF430) // (PIOA) Set Output Data Register\n#define AT91C_PIOA_IFSR           (0xFFFFF428) // (PIOA) Input Filter Status Register\n#define AT91C_PIOA_IFER           (0xFFFFF420) // (PIOA) Input Filter Enable Register\n#define AT91C_PIOA_OSR            (0xFFFFF418) // (PIOA) Output Status Register\n#define AT91C_PIOA_IDR            (0xFFFFF444) // (PIOA) Interrupt Disable Register\n#define AT91C_PIOA_PDSR           (0xFFFFF43C) // (PIOA) Pin Data Status Register\n#define AT91C_PIOA_CODR           (0xFFFFF434) // (PIOA) Clear Output Data Register\n#define AT91C_PIOA_OWSR           (0xFFFFF4A8) // (PIOA) Output Write Status Register\n#define AT91C_PIOA_OWER           (0xFFFFF4A0) // (PIOA) Output Write Enable Register\n// ========== Register definition for DBGU peripheral ========== \n#define AT91C_DBGU_C2R            (0xFFFFF244) // (DBGU) Chip ID2 Register\n#define AT91C_DBGU_THR            (0xFFFFF21C) // (DBGU) Transmitter Holding Register\n#define AT91C_DBGU_CSR            (0xFFFFF214) // (DBGU) Channel Status Register\n#define AT91C_DBGU_IDR            (0xFFFFF20C) // (DBGU) Interrupt Disable Register\n#define AT91C_DBGU_MR             (0xFFFFF204) // (DBGU) Mode Register\n#define AT91C_DBGU_FNTR           (0xFFFFF248) // (DBGU) Force NTRST Register\n#define AT91C_DBGU_C1R            (0xFFFFF240) // (DBGU) Chip ID1 Register\n#define AT91C_DBGU_BRGR           (0xFFFFF220) // (DBGU) Baud Rate Generator Register\n#define AT91C_DBGU_RHR            (0xFFFFF218) // (DBGU) Receiver Holding Register\n#define AT91C_DBGU_IMR            (0xFFFFF210) // (DBGU) Interrupt Mask Register\n#define AT91C_DBGU_IER            (0xFFFFF208) // (DBGU) Interrupt Enable Register\n#define AT91C_DBGU_CR             (0xFFFFF200) // (DBGU) Control Register\n// ========== Register definition for PDC_DBGU peripheral ========== \n#define AT91C_DBGU_TNCR           (0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register\n#define AT91C_DBGU_RNCR           (0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register\n#define AT91C_DBGU_PTCR           (0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register\n#define AT91C_DBGU_PTSR           (0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register\n#define AT91C_DBGU_RCR            (0xFFFFF304) // (PDC_DBGU) Receive Counter Register\n#define AT91C_DBGU_TCR            (0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register\n#define AT91C_DBGU_RPR            (0xFFFFF300) // (PDC_DBGU) Receive Pointer Register\n#define AT91C_DBGU_TPR            (0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register\n#define AT91C_DBGU_RNPR           (0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register\n#define AT91C_DBGU_TNPR           (0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register\n// ========== Register definition for AIC peripheral ========== \n#define AT91C_AIC_ICCR            (0xFFFFF128) // (AIC) Interrupt Clear Command Register\n#define AT91C_AIC_IECR            (0xFFFFF120) // (AIC) Interrupt Enable Command Register\n#define AT91C_AIC_SMR             (0xFFFFF000) // (AIC) Source Mode Register\n#define AT91C_AIC_ISCR            (0xFFFFF12C) // (AIC) Interrupt Set Command Register\n#define AT91C_AIC_EOICR           (0xFFFFF130) // (AIC) End of Interrupt Command Register\n#define AT91C_AIC_DCR             (0xFFFFF138) // (AIC) Debug Control Register (Protect)\n#define AT91C_AIC_FFER            (0xFFFFF140) // (AIC) Fast Forcing Enable Register\n#define AT91C_AIC_SVR             (0xFFFFF080) // (AIC) Source Vector Register\n#define AT91C_AIC_SPU             (0xFFFFF134) // (AIC) Spurious Vector Register\n#define AT91C_AIC_FFDR            (0xFFFFF144) // (AIC) Fast Forcing Disable Register\n#define AT91C_AIC_FVR             (0xFFFFF104) // (AIC) FIQ Vector Register\n#define AT91C_AIC_FFSR            (0xFFFFF148) // (AIC) Fast Forcing Status Register\n#define AT91C_AIC_IMR             (0xFFFFF110) // (AIC) Interrupt Mask Register\n#define AT91C_AIC_ISR             (0xFFFFF108) // (AIC) Interrupt Status Register\n#define AT91C_AIC_IVR             (0xFFFFF100) // (AIC) IRQ Vector Register\n#define AT91C_AIC_IDCR            (0xFFFFF124) // (AIC) Interrupt Disable Command Register\n#define AT91C_AIC_CISR            (0xFFFFF114) // (AIC) Core Interrupt Status Register\n#define AT91C_AIC_IPR             (0xFFFFF10C) // (AIC) Interrupt Pending Register\n// ========== Register definition for PDC_SPI peripheral ========== \n#define AT91C_SPI_PTCR            (0xFFFE0120) // (PDC_SPI) PDC Transfer Control Register\n#define AT91C_SPI_TNPR            (0xFFFE0118) // (PDC_SPI) Transmit Next Pointer Register\n#define AT91C_SPI_RNPR            (0xFFFE0110) // (PDC_SPI) Receive Next Pointer Register\n#define AT91C_SPI_TPR             (0xFFFE0108) // (PDC_SPI) Transmit Pointer Register\n#define AT91C_SPI_RPR             (0xFFFE0100) // (PDC_SPI) Receive Pointer Register\n#define AT91C_SPI_PTSR            (0xFFFE0124) // (PDC_SPI) PDC Transfer Status Register\n#define AT91C_SPI_TNCR            (0xFFFE011C) // (PDC_SPI) Transmit Next Counter Register\n#define AT91C_SPI_RNCR            (0xFFFE0114) // (PDC_SPI) Receive Next Counter Register\n#define AT91C_SPI_TCR             (0xFFFE010C) // (PDC_SPI) Transmit Counter Register\n#define AT91C_SPI_RCR             (0xFFFE0104) // (PDC_SPI) Receive Counter Register\n// ========== Register definition for SPI peripheral ========== \n#define AT91C_SPI_CSR             (0xFFFE0030) // (SPI) Chip Select Register\n#define AT91C_SPI_IDR             (0xFFFE0018) // (SPI) Interrupt Disable Register\n#define AT91C_SPI_SR              (0xFFFE0010) // (SPI) Status Register\n#define AT91C_SPI_RDR             (0xFFFE0008) // (SPI) Receive Data Register\n#define AT91C_SPI_CR              (0xFFFE0000) // (SPI) Control Register\n#define AT91C_SPI_IMR             (0xFFFE001C) // (SPI) Interrupt Mask Register\n#define AT91C_SPI_IER             (0xFFFE0014) // (SPI) Interrupt Enable Register\n#define AT91C_SPI_TDR             (0xFFFE000C) // (SPI) Transmit Data Register\n#define AT91C_SPI_MR              (0xFFFE0004) // (SPI) Mode Register\n// ========== Register definition for PDC_SSC2 peripheral ========== \n#define AT91C_SSC2_PTCR           (0xFFFD8120) // (PDC_SSC2) PDC Transfer Control Register\n#define AT91C_SSC2_TNPR           (0xFFFD8118) // (PDC_SSC2) Transmit Next Pointer Register\n#define AT91C_SSC2_RNPR           (0xFFFD8110) // (PDC_SSC2) Receive Next Pointer Register\n#define AT91C_SSC2_TPR            (0xFFFD8108) // (PDC_SSC2) Transmit Pointer Register\n#define AT91C_SSC2_RPR            (0xFFFD8100) // (PDC_SSC2) Receive Pointer Register\n#define AT91C_SSC2_PTSR           (0xFFFD8124) // (PDC_SSC2) PDC Transfer Status Register\n#define AT91C_SSC2_TNCR           (0xFFFD811C) // (PDC_SSC2) Transmit Next Counter Register\n#define AT91C_SSC2_RNCR           (0xFFFD8114) // (PDC_SSC2) Receive Next Counter Register\n#define AT91C_SSC2_TCR            (0xFFFD810C) // (PDC_SSC2) Transmit Counter Register\n#define AT91C_SSC2_RCR            (0xFFFD8104) // (PDC_SSC2) Receive Counter Register\n// ========== Register definition for SSC2 peripheral ========== \n#define AT91C_SSC2_IMR            (0xFFFD804C) // (SSC2) Interrupt Mask Register\n#define AT91C_SSC2_IER            (0xFFFD8044) // (SSC2) Interrupt Enable Register\n#define AT91C_SSC2_RC1R           (0xFFFD803C) // (SSC2) Receive Compare 1 Register\n#define AT91C_SSC2_TSHR           (0xFFFD8034) // (SSC2) Transmit Sync Holding Register\n#define AT91C_SSC2_CMR            (0xFFFD8004) // (SSC2) Clock Mode Register\n#define AT91C_SSC2_IDR            (0xFFFD8048) // (SSC2) Interrupt Disable Register\n#define AT91C_SSC2_TCMR           (0xFFFD8018) // (SSC2) Transmit Clock Mode Register\n#define AT91C_SSC2_RCMR           (0xFFFD8010) // (SSC2) Receive Clock ModeRegister\n#define AT91C_SSC2_CR             (0xFFFD8000) // (SSC2) Control Register\n#define AT91C_SSC2_RFMR           (0xFFFD8014) // (SSC2) Receive Frame Mode Register\n#define AT91C_SSC2_TFMR           (0xFFFD801C) // (SSC2) Transmit Frame Mode Register\n#define AT91C_SSC2_THR            (0xFFFD8024) // (SSC2) Transmit Holding Register\n#define AT91C_SSC2_SR             (0xFFFD8040) // (SSC2) Status Register\n#define AT91C_SSC2_RC0R           (0xFFFD8038) // (SSC2) Receive Compare 0 Register\n#define AT91C_SSC2_RSHR           (0xFFFD8030) // (SSC2) Receive Sync Holding Register\n#define AT91C_SSC2_RHR            (0xFFFD8020) // (SSC2) Receive Holding Register\n// ========== Register definition for PDC_SSC1 peripheral ========== \n#define AT91C_SSC1_PTCR           (0xFFFD4120) // (PDC_SSC1) PDC Transfer Control Register\n#define AT91C_SSC1_TNPR           (0xFFFD4118) // (PDC_SSC1) Transmit Next Pointer Register\n#define AT91C_SSC1_RNPR           (0xFFFD4110) // (PDC_SSC1) Receive Next Pointer Register\n#define AT91C_SSC1_TPR            (0xFFFD4108) // (PDC_SSC1) Transmit Pointer Register\n#define AT91C_SSC1_RPR            (0xFFFD4100) // (PDC_SSC1) Receive Pointer Register\n#define AT91C_SSC1_PTSR           (0xFFFD4124) // (PDC_SSC1) PDC Transfer Status Register\n#define AT91C_SSC1_TNCR           (0xFFFD411C) // (PDC_SSC1) Transmit Next Counter Register\n#define AT91C_SSC1_RNCR           (0xFFFD4114) // (PDC_SSC1) Receive Next Counter Register\n#define AT91C_SSC1_TCR            (0xFFFD410C) // (PDC_SSC1) Transmit Counter Register\n#define AT91C_SSC1_RCR            (0xFFFD4104) // (PDC_SSC1) Receive Counter Register\n// ========== Register definition for SSC1 peripheral ========== \n#define AT91C_SSC1_RFMR           (0xFFFD4014) // (SSC1) Receive Frame Mode Register\n#define AT91C_SSC1_CMR            (0xFFFD4004) // (SSC1) Clock Mode Register\n#define AT91C_SSC1_IDR            (0xFFFD4048) // (SSC1) Interrupt Disable Register\n#define AT91C_SSC1_SR             (0xFFFD4040) // (SSC1) Status Register\n#define AT91C_SSC1_RC0R           (0xFFFD4038) // (SSC1) Receive Compare 0 Register\n#define AT91C_SSC1_RSHR           (0xFFFD4030) // (SSC1) Receive Sync Holding Register\n#define AT91C_SSC1_RHR            (0xFFFD4020) // (SSC1) Receive Holding Register\n#define AT91C_SSC1_TCMR           (0xFFFD4018) // (SSC1) Transmit Clock Mode Register\n#define AT91C_SSC1_RCMR           (0xFFFD4010) // (SSC1) Receive Clock ModeRegister\n#define AT91C_SSC1_CR             (0xFFFD4000) // (SSC1) Control Register\n#define AT91C_SSC1_IMR            (0xFFFD404C) // (SSC1) Interrupt Mask Register\n#define AT91C_SSC1_IER            (0xFFFD4044) // (SSC1) Interrupt Enable Register\n#define AT91C_SSC1_RC1R           (0xFFFD403C) // (SSC1) Receive Compare 1 Register\n#define AT91C_SSC1_TSHR           (0xFFFD4034) // (SSC1) Transmit Sync Holding Register\n#define AT91C_SSC1_THR            (0xFFFD4024) // (SSC1) Transmit Holding Register\n#define AT91C_SSC1_TFMR           (0xFFFD401C) // (SSC1) Transmit Frame Mode Register\n// ========== Register definition for PDC_SSC0 peripheral ========== \n#define AT91C_SSC0_PTCR           (0xFFFD0120) // (PDC_SSC0) PDC Transfer Control Register\n#define AT91C_SSC0_TNPR           (0xFFFD0118) // (PDC_SSC0) Transmit Next Pointer Register\n#define AT91C_SSC0_RNPR           (0xFFFD0110) // (PDC_SSC0) Receive Next Pointer Register\n#define AT91C_SSC0_TPR            (0xFFFD0108) // (PDC_SSC0) Transmit Pointer Register\n#define AT91C_SSC0_RPR            (0xFFFD0100) // (PDC_SSC0) Receive Pointer Register\n#define AT91C_SSC0_PTSR           (0xFFFD0124) // (PDC_SSC0) PDC Transfer Status Register\n#define AT91C_SSC0_TNCR           (0xFFFD011C) // (PDC_SSC0) Transmit Next Counter Register\n#define AT91C_SSC0_RNCR           (0xFFFD0114) // (PDC_SSC0) Receive Next Counter Register\n#define AT91C_SSC0_TCR            (0xFFFD010C) // (PDC_SSC0) Transmit Counter Register\n#define AT91C_SSC0_RCR            (0xFFFD0104) // (PDC_SSC0) Receive Counter Register\n// ========== Register definition for SSC0 peripheral ========== \n#define AT91C_SSC0_IMR            (0xFFFD004C) // (SSC0) Interrupt Mask Register\n#define AT91C_SSC0_IER            (0xFFFD0044) // (SSC0) Interrupt Enable Register\n#define AT91C_SSC0_RC1R           (0xFFFD003C) // (SSC0) Receive Compare 1 Register\n#define AT91C_SSC0_TSHR           (0xFFFD0034) // (SSC0) Transmit Sync Holding Register\n#define AT91C_SSC0_THR            (0xFFFD0024) // (SSC0) Transmit Holding Register\n#define AT91C_SSC0_TFMR           (0xFFFD001C) // (SSC0) Transmit Frame Mode Register\n#define AT91C_SSC0_RFMR           (0xFFFD0014) // (SSC0) Receive Frame Mode Register\n#define AT91C_SSC0_CMR            (0xFFFD0004) // (SSC0) Clock Mode Register\n#define AT91C_SSC0_IDR            (0xFFFD0048) // (SSC0) Interrupt Disable Register\n#define AT91C_SSC0_SR             (0xFFFD0040) // (SSC0) Status Register\n#define AT91C_SSC0_RC0R           (0xFFFD0038) // (SSC0) Receive Compare 0 Register\n#define AT91C_SSC0_RSHR           (0xFFFD0030) // (SSC0) Receive Sync Holding Register\n#define AT91C_SSC0_RHR            (0xFFFD0020) // (SSC0) Receive Holding Register\n#define AT91C_SSC0_TCMR           (0xFFFD0018) // (SSC0) Transmit Clock Mode Register\n#define AT91C_SSC0_RCMR           (0xFFFD0010) // (SSC0) Receive Clock ModeRegister\n#define AT91C_SSC0_CR             (0xFFFD0000) // (SSC0) Control Register\n// ========== Register definition for PDC_US3 peripheral ========== \n#define AT91C_US3_PTSR            (0xFFFCC124) // (PDC_US3) PDC Transfer Status Register\n#define AT91C_US3_TNCR            (0xFFFCC11C) // (PDC_US3) Transmit Next Counter Register\n#define AT91C_US3_RNCR            (0xFFFCC114) // (PDC_US3) Receive Next Counter Register\n#define AT91C_US3_TCR             (0xFFFCC10C) // (PDC_US3) Transmit Counter Register\n#define AT91C_US3_RCR             (0xFFFCC104) // (PDC_US3) Receive Counter Register\n#define AT91C_US3_PTCR            (0xFFFCC120) // (PDC_US3) PDC Transfer Control Register\n#define AT91C_US3_TNPR            (0xFFFCC118) // (PDC_US3) Transmit Next Pointer Register\n#define AT91C_US3_RNPR            (0xFFFCC110) // (PDC_US3) Receive Next Pointer Register\n#define AT91C_US3_TPR             (0xFFFCC108) // (PDC_US3) Transmit Pointer Register\n#define AT91C_US3_RPR             (0xFFFCC100) // (PDC_US3) Receive Pointer Register\n// ========== Register definition for US3 peripheral ========== \n#define AT91C_US3_IF              (0xFFFCC04C) // (US3) IRDA_FILTER Register\n#define AT91C_US3_NER             (0xFFFCC044) // (US3) Nb Errors Register\n#define AT91C_US3_RTOR            (0xFFFCC024) // (US3) Receiver Time-out Register\n#define AT91C_US3_THR             (0xFFFCC01C) // (US3) Transmitter Holding Register\n#define AT91C_US3_CSR             (0xFFFCC014) // (US3) Channel Status Register\n#define AT91C_US3_IDR             (0xFFFCC00C) // (US3) Interrupt Disable Register\n#define AT91C_US3_MR              (0xFFFCC004) // (US3) Mode Register\n#define AT91C_US3_XXR             (0xFFFCC048) // (US3) XON_XOFF Register\n#define AT91C_US3_FIDI            (0xFFFCC040) // (US3) FI_DI_Ratio Register\n#define AT91C_US3_TTGR            (0xFFFCC028) // (US3) Transmitter Time-guard Register\n#define AT91C_US3_BRGR            (0xFFFCC020) // (US3) Baud Rate Generator Register\n#define AT91C_US3_RHR             (0xFFFCC018) // (US3) Receiver Holding Register\n#define AT91C_US3_IMR             (0xFFFCC010) // (US3) Interrupt Mask Register\n#define AT91C_US3_IER             (0xFFFCC008) // (US3) Interrupt Enable Register\n#define AT91C_US3_CR              (0xFFFCC000) // (US3) Control Register\n// ========== Register definition for PDC_US2 peripheral ========== \n#define AT91C_US2_PTSR            (0xFFFC8124) // (PDC_US2) PDC Transfer Status Register\n#define AT91C_US2_TNCR            (0xFFFC811C) // (PDC_US2) Transmit Next Counter Register\n#define AT91C_US2_RNCR            (0xFFFC8114) // (PDC_US2) Receive Next Counter Register\n#define AT91C_US2_TCR             (0xFFFC810C) // (PDC_US2) Transmit Counter Register\n#define AT91C_US2_PTCR            (0xFFFC8120) // (PDC_US2) PDC Transfer Control Register\n#define AT91C_US2_RCR             (0xFFFC8104) // (PDC_US2) Receive Counter Register\n#define AT91C_US2_TNPR            (0xFFFC8118) // (PDC_US2) Transmit Next Pointer Register\n#define AT91C_US2_RPR             (0xFFFC8100) // (PDC_US2) Receive Pointer Register\n#define AT91C_US2_TPR             (0xFFFC8108) // (PDC_US2) Transmit Pointer Register\n#define AT91C_US2_RNPR            (0xFFFC8110) // (PDC_US2) Receive Next Pointer Register\n// ========== Register definition for US2 peripheral ========== \n#define AT91C_US2_XXR             (0xFFFC8048) // (US2) XON_XOFF Register\n#define AT91C_US2_FIDI            (0xFFFC8040) // (US2) FI_DI_Ratio Register\n#define AT91C_US2_TTGR            (0xFFFC8028) // (US2) Transmitter Time-guard Register\n#define AT91C_US2_BRGR            (0xFFFC8020) // (US2) Baud Rate Generator Register\n#define AT91C_US2_RHR             (0xFFFC8018) // (US2) Receiver Holding Register\n#define AT91C_US2_IMR             (0xFFFC8010) // (US2) Interrupt Mask Register\n#define AT91C_US2_IER             (0xFFFC8008) // (US2) Interrupt Enable Register\n#define AT91C_US2_CR              (0xFFFC8000) // (US2) Control Register\n#define AT91C_US2_IF              (0xFFFC804C) // (US2) IRDA_FILTER Register\n#define AT91C_US2_NER             (0xFFFC8044) // (US2) Nb Errors Register\n#define AT91C_US2_RTOR            (0xFFFC8024) // (US2) Receiver Time-out Register\n#define AT91C_US2_THR             (0xFFFC801C) // (US2) Transmitter Holding Register\n#define AT91C_US2_CSR             (0xFFFC8014) // (US2) Channel Status Register\n#define AT91C_US2_IDR             (0xFFFC800C) // (US2) Interrupt Disable Register\n#define AT91C_US2_MR              (0xFFFC8004) // (US2) Mode Register\n// ========== Register definition for PDC_US1 peripheral ========== \n#define AT91C_US1_PTSR            (0xFFFC4124) // (PDC_US1) PDC Transfer Status Register\n#define AT91C_US1_TNCR            (0xFFFC411C) // (PDC_US1) Transmit Next Counter Register\n#define AT91C_US1_RNCR            (0xFFFC4114) // (PDC_US1) Receive Next Counter Register\n#define AT91C_US1_TCR             (0xFFFC410C) // (PDC_US1) Transmit Counter Register\n#define AT91C_US1_RCR             (0xFFFC4104) // (PDC_US1) Receive Counter Register\n#define AT91C_US1_PTCR            (0xFFFC4120) // (PDC_US1) PDC Transfer Control Register\n#define AT91C_US1_TNPR            (0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register\n#define AT91C_US1_RNPR            (0xFFFC4110) // (PDC_US1) Receive Next Pointer Register\n#define AT91C_US1_TPR             (0xFFFC4108) // (PDC_US1) Transmit Pointer Register\n#define AT91C_US1_RPR             (0xFFFC4100) // (PDC_US1) Receive Pointer Register\n// ========== Register definition for US1 peripheral ========== \n#define AT91C_US1_XXR             (0xFFFC4048) // (US1) XON_XOFF Register\n#define AT91C_US1_RHR             (0xFFFC4018) // (US1) Receiver Holding Register\n#define AT91C_US1_IMR             (0xFFFC4010) // (US1) Interrupt Mask Register\n#define AT91C_US1_IER             (0xFFFC4008) // (US1) Interrupt Enable Register\n#define AT91C_US1_CR              (0xFFFC4000) // (US1) Control Register\n#define AT91C_US1_RTOR            (0xFFFC4024) // (US1) Receiver Time-out Register\n#define AT91C_US1_THR             (0xFFFC401C) // (US1) Transmitter Holding Register\n#define AT91C_US1_CSR             (0xFFFC4014) // (US1) Channel Status Register\n#define AT91C_US1_IDR             (0xFFFC400C) // (US1) Interrupt Disable Register\n#define AT91C_US1_FIDI            (0xFFFC4040) // (US1) FI_DI_Ratio Register\n#define AT91C_US1_BRGR            (0xFFFC4020) // (US1) Baud Rate Generator Register\n#define AT91C_US1_TTGR            (0xFFFC4028) // (US1) Transmitter Time-guard Register\n#define AT91C_US1_IF              (0xFFFC404C) // (US1) IRDA_FILTER Register\n#define AT91C_US1_NER             (0xFFFC4044) // (US1) Nb Errors Register\n#define AT91C_US1_MR              (0xFFFC4004) // (US1) Mode Register\n// ========== Register definition for PDC_US0 peripheral ========== \n#define AT91C_US0_PTCR            (0xFFFC0120) // (PDC_US0) PDC Transfer Control Register\n#define AT91C_US0_TNPR            (0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register\n#define AT91C_US0_RNPR            (0xFFFC0110) // (PDC_US0) Receive Next Pointer Register\n#define AT91C_US0_TPR             (0xFFFC0108) // (PDC_US0) Transmit Pointer Register\n#define AT91C_US0_RPR             (0xFFFC0100) // (PDC_US0) Receive Pointer Register\n#define AT91C_US0_PTSR            (0xFFFC0124) // (PDC_US0) PDC Transfer Status Register\n#define AT91C_US0_TNCR            (0xFFFC011C) // (PDC_US0) Transmit Next Counter Register\n#define AT91C_US0_RNCR            (0xFFFC0114) // (PDC_US0) Receive Next Counter Register\n#define AT91C_US0_TCR             (0xFFFC010C) // (PDC_US0) Transmit Counter Register\n#define AT91C_US0_RCR             (0xFFFC0104) // (PDC_US0) Receive Counter Register\n// ========== Register definition for US0 peripheral ========== \n#define AT91C_US0_TTGR            (0xFFFC0028) // (US0) Transmitter Time-guard Register\n#define AT91C_US0_BRGR            (0xFFFC0020) // (US0) Baud Rate Generator Register\n#define AT91C_US0_RHR             (0xFFFC0018) // (US0) Receiver Holding Register\n#define AT91C_US0_IMR             (0xFFFC0010) // (US0) Interrupt Mask Register\n#define AT91C_US0_NER             (0xFFFC0044) // (US0) Nb Errors Register\n#define AT91C_US0_RTOR            (0xFFFC0024) // (US0) Receiver Time-out Register\n#define AT91C_US0_XXR             (0xFFFC0048) // (US0) XON_XOFF Register\n#define AT91C_US0_FIDI            (0xFFFC0040) // (US0) FI_DI_Ratio Register\n#define AT91C_US0_CR              (0xFFFC0000) // (US0) Control Register\n#define AT91C_US0_IER             (0xFFFC0008) // (US0) Interrupt Enable Register\n#define AT91C_US0_IF              (0xFFFC004C) // (US0) IRDA_FILTER Register\n#define AT91C_US0_MR              (0xFFFC0004) // (US0) Mode Register\n#define AT91C_US0_IDR             (0xFFFC000C) // (US0) Interrupt Disable Register\n#define AT91C_US0_CSR             (0xFFFC0014) // (US0) Channel Status Register\n#define AT91C_US0_THR             (0xFFFC001C) // (US0) Transmitter Holding Register\n// ========== Register definition for TWI peripheral ========== \n#define AT91C_TWI_RHR             (0xFFFB8030) // (TWI) Receive Holding Register\n#define AT91C_TWI_IDR             (0xFFFB8028) // (TWI) Interrupt Disable Register\n#define AT91C_TWI_SR              (0xFFFB8020) // (TWI) Status Register\n#define AT91C_TWI_CWGR            (0xFFFB8010) // (TWI) Clock Waveform Generator Register\n#define AT91C_TWI_SMR             (0xFFFB8008) // (TWI) Slave Mode Register\n#define AT91C_TWI_CR              (0xFFFB8000) // (TWI) Control Register\n#define AT91C_TWI_THR             (0xFFFB8034) // (TWI) Transmit Holding Register\n#define AT91C_TWI_IMR             (0xFFFB802C) // (TWI) Interrupt Mask Register\n#define AT91C_TWI_IER             (0xFFFB8024) // (TWI) Interrupt Enable Register\n#define AT91C_TWI_IADR            (0xFFFB800C) // (TWI) Internal Address Register\n#define AT91C_TWI_MMR             (0xFFFB8004) // (TWI) Master Mode Register\n// ========== Register definition for PDC_MCI peripheral ========== \n#define AT91C_MCI_PTCR            (0xFFFB4120) // (PDC_MCI) PDC Transfer Control Register\n#define AT91C_MCI_TNPR            (0xFFFB4118) // (PDC_MCI) Transmit Next Pointer Register\n#define AT91C_MCI_RNPR            (0xFFFB4110) // (PDC_MCI) Receive Next Pointer Register\n#define AT91C_MCI_TPR             (0xFFFB4108) // (PDC_MCI) Transmit Pointer Register\n#define AT91C_MCI_RPR             (0xFFFB4100) // (PDC_MCI) Receive Pointer Register\n#define AT91C_MCI_PTSR            (0xFFFB4124) // (PDC_MCI) PDC Transfer Status Register\n#define AT91C_MCI_TNCR            (0xFFFB411C) // (PDC_MCI) Transmit Next Counter Register\n#define AT91C_MCI_RNCR            (0xFFFB4114) // (PDC_MCI) Receive Next Counter Register\n#define AT91C_MCI_TCR             (0xFFFB410C) // (PDC_MCI) Transmit Counter Register\n#define AT91C_MCI_RCR             (0xFFFB4104) // (PDC_MCI) Receive Counter Register\n// ========== Register definition for MCI peripheral ========== \n#define AT91C_MCI_IDR             (0xFFFB4048) // (MCI) MCI Interrupt Disable Register\n#define AT91C_MCI_SR              (0xFFFB4040) // (MCI) MCI Status Register\n#define AT91C_MCI_RDR             (0xFFFB4030) // (MCI) MCI Receive Data Register\n#define AT91C_MCI_RSPR            (0xFFFB4020) // (MCI) MCI Response Register\n#define AT91C_MCI_ARGR            (0xFFFB4010) // (MCI) MCI Argument Register\n#define AT91C_MCI_DTOR            (0xFFFB4008) // (MCI) MCI Data Timeout Register\n#define AT91C_MCI_CR              (0xFFFB4000) // (MCI) MCI Control Register\n#define AT91C_MCI_IMR             (0xFFFB404C) // (MCI) MCI Interrupt Mask Register\n#define AT91C_MCI_IER             (0xFFFB4044) // (MCI) MCI Interrupt Enable Register\n#define AT91C_MCI_TDR             (0xFFFB4034) // (MCI) MCI Transmit Data Register\n#define AT91C_MCI_CMDR            (0xFFFB4014) // (MCI) MCI Command Register\n#define AT91C_MCI_SDCR            (0xFFFB400C) // (MCI) MCI SD Card Register\n#define AT91C_MCI_MR              (0xFFFB4004) // (MCI) MCI Mode Register\n// ========== Register definition for UDP peripheral ========== \n#define AT91C_UDP_ISR             (0xFFFB001C) // (UDP) Interrupt Status Register\n#define AT91C_UDP_IDR             (0xFFFB0014) // (UDP) Interrupt Disable Register\n#define AT91C_UDP_GLBSTATE        (0xFFFB0004) // (UDP) Global State Register\n#define AT91C_UDP_FDR             (0xFFFB0050) // (UDP) Endpoint FIFO Data Register\n#define AT91C_UDP_CSR             (0xFFFB0030) // (UDP) Endpoint Control and Status Register\n#define AT91C_UDP_RSTEP           (0xFFFB0028) // (UDP) Reset Endpoint Register\n#define AT91C_UDP_ICR             (0xFFFB0020) // (UDP) Interrupt Clear Register\n#define AT91C_UDP_IMR             (0xFFFB0018) // (UDP) Interrupt Mask Register\n#define AT91C_UDP_IER             (0xFFFB0010) // (UDP) Interrupt Enable Register\n#define AT91C_UDP_FADDR           (0xFFFB0008) // (UDP) Function Address Register\n#define AT91C_UDP_NUM             (0xFFFB0000) // (UDP) Frame Number Register\n// ========== Register definition for TC5 peripheral ========== \n#define AT91C_TC5_CMR             (0xFFFA4084) // (TC5) Channel Mode Register\n#define AT91C_TC5_IDR             (0xFFFA40A8) // (TC5) Interrupt Disable Register\n#define AT91C_TC5_SR              (0xFFFA40A0) // (TC5) Status Register\n#define AT91C_TC5_RB              (0xFFFA4098) // (TC5) Register B\n#define AT91C_TC5_CV              (0xFFFA4090) // (TC5) Counter Value\n#define AT91C_TC5_CCR             (0xFFFA4080) // (TC5) Channel Control Register\n#define AT91C_TC5_IMR             (0xFFFA40AC) // (TC5) Interrupt Mask Register\n#define AT91C_TC5_IER             (0xFFFA40A4) // (TC5) Interrupt Enable Register\n#define AT91C_TC5_RC              (0xFFFA409C) // (TC5) Register C\n#define AT91C_TC5_RA              (0xFFFA4094) // (TC5) Register A\n// ========== Register definition for TC4 peripheral ========== \n#define AT91C_TC4_IMR             (0xFFFA406C) // (TC4) Interrupt Mask Register\n#define AT91C_TC4_IER             (0xFFFA4064) // (TC4) Interrupt Enable Register\n#define AT91C_TC4_RC              (0xFFFA405C) // (TC4) Register C\n#define AT91C_TC4_RA              (0xFFFA4054) // (TC4) Register A\n#define AT91C_TC4_CMR             (0xFFFA4044) // (TC4) Channel Mode Register\n#define AT91C_TC4_IDR             (0xFFFA4068) // (TC4) Interrupt Disable Register\n#define AT91C_TC4_SR              (0xFFFA4060) // (TC4) Status Register\n#define AT91C_TC4_RB              (0xFFFA4058) // (TC4) Register B\n#define AT91C_TC4_CV              (0xFFFA4050) // (TC4) Counter Value\n#define AT91C_TC4_CCR             (0xFFFA4040) // (TC4) Channel Control Register\n// ========== Register definition for TC3 peripheral ========== \n#define AT91C_TC3_IMR             (0xFFFA402C) // (TC3) Interrupt Mask Register\n#define AT91C_TC3_CV              (0xFFFA4010) // (TC3) Counter Value\n#define AT91C_TC3_CCR             (0xFFFA4000) // (TC3) Channel Control Register\n#define AT91C_TC3_IER             (0xFFFA4024) // (TC3) Interrupt Enable Register\n#define AT91C_TC3_CMR             (0xFFFA4004) // (TC3) Channel Mode Register\n#define AT91C_TC3_RA              (0xFFFA4014) // (TC3) Register A\n#define AT91C_TC3_RC              (0xFFFA401C) // (TC3) Register C\n#define AT91C_TC3_IDR             (0xFFFA4028) // (TC3) Interrupt Disable Register\n#define AT91C_TC3_RB              (0xFFFA4018) // (TC3) Register B\n#define AT91C_TC3_SR              (0xFFFA4020) // (TC3) Status Register\n// ========== Register definition for TCB1 peripheral ========== \n#define AT91C_TCB1_BCR            (0xFFFA4140) // (TCB1) TC Block Control Register\n#define AT91C_TCB1_BMR            (0xFFFA4144) // (TCB1) TC Block Mode Register\n// ========== Register definition for TC2 peripheral ========== \n#define AT91C_TC2_IMR             (0xFFFA00AC) // (TC2) Interrupt Mask Register\n#define AT91C_TC2_IER             (0xFFFA00A4) // (TC2) Interrupt Enable Register\n#define AT91C_TC2_RC              (0xFFFA009C) // (TC2) Register C\n#define AT91C_TC2_RA              (0xFFFA0094) // (TC2) Register A\n#define AT91C_TC2_CMR             (0xFFFA0084) // (TC2) Channel Mode Register\n#define AT91C_TC2_IDR             (0xFFFA00A8) // (TC2) Interrupt Disable Register\n#define AT91C_TC2_SR              (0xFFFA00A0) // (TC2) Status Register\n#define AT91C_TC2_RB              (0xFFFA0098) // (TC2) Register B\n#define AT91C_TC2_CV              (0xFFFA0090) // (TC2) Counter Value\n#define AT91C_TC2_CCR             (0xFFFA0080) // (TC2) Channel Control Register\n// ========== Register definition for TC1 peripheral ========== \n#define AT91C_TC1_IMR             (0xFFFA006C) // (TC1) Interrupt Mask Register\n#define AT91C_TC1_IER             (0xFFFA0064) // (TC1) Interrupt Enable Register\n#define AT91C_TC1_RC              (0xFFFA005C) // (TC1) Register C\n#define AT91C_TC1_RA              (0xFFFA0054) // (TC1) Register A\n#define AT91C_TC1_CMR             (0xFFFA0044) // (TC1) Channel Mode Register\n#define AT91C_TC1_IDR             (0xFFFA0068) // (TC1) Interrupt Disable Register\n#define AT91C_TC1_SR              (0xFFFA0060) // (TC1) Status Register\n#define AT91C_TC1_RB              (0xFFFA0058) // (TC1) Register B\n#define AT91C_TC1_CV              (0xFFFA0050) // (TC1) Counter Value\n#define AT91C_TC1_CCR             (0xFFFA0040) // (TC1) Channel Control Register\n// ========== Register definition for TC0 peripheral ========== \n#define AT91C_TC0_IMR             (0xFFFA002C) // (TC0) Interrupt Mask Register\n#define AT91C_TC0_IER             (0xFFFA0024) // (TC0) Interrupt Enable Register\n#define AT91C_TC0_RC              (0xFFFA001C) // (TC0) Register C\n#define AT91C_TC0_RA              (0xFFFA0014) // (TC0) Register A\n#define AT91C_TC0_CMR             (0xFFFA0004) // (TC0) Channel Mode Register\n#define AT91C_TC0_IDR             (0xFFFA0028) // (TC0) Interrupt Disable Register\n#define AT91C_TC0_SR              (0xFFFA0020) // (TC0) Status Register\n#define AT91C_TC0_RB              (0xFFFA0018) // (TC0) Register B\n#define AT91C_TC0_CV              (0xFFFA0010) // (TC0) Counter Value\n#define AT91C_TC0_CCR             (0xFFFA0000) // (TC0) Channel Control Register\n// ========== Register definition for TCB0 peripheral ========== \n#define AT91C_TCB0_BMR            (0xFFFA00C4) // (TCB0) TC Block Mode Register\n#define AT91C_TCB0_BCR            (0xFFFA00C0) // (TCB0) TC Block Control Register\n// ========== Register definition for UHP peripheral ========== \n#define AT91C_UHP_HcRhDescriptorA (0x00300048) // (UHP) Root Hub characteristics A\n#define AT91C_UHP_HcRhPortStatus  (0x00300054) // (UHP) Root Hub Port Status Register\n#define AT91C_UHP_HcRhDescriptorB (0x0030004C) // (UHP) Root Hub characteristics B\n#define AT91C_UHP_HcControl       (0x00300004) // (UHP) Operating modes for the Host Controller\n#define AT91C_UHP_HcInterruptStatus (0x0030000C) // (UHP) Interrupt Status Register\n#define AT91C_UHP_HcRhStatus      (0x00300050) // (UHP) Root Hub Status register\n#define AT91C_UHP_HcRevision      (0x00300000) // (UHP) Revision\n#define AT91C_UHP_HcCommandStatus (0x00300008) // (UHP) Command & status Register\n#define AT91C_UHP_HcInterruptEnable (0x00300010) // (UHP) Interrupt Enable Register\n#define AT91C_UHP_HcHCCA          (0x00300018) // (UHP) Pointer to the Host Controller Communication Area\n#define AT91C_UHP_HcControlHeadED (0x00300020) // (UHP) First Endpoint Descriptor of the Control list\n#define AT91C_UHP_HcInterruptDisable (0x00300014) // (UHP) Interrupt Disable Register\n#define AT91C_UHP_HcPeriodCurrentED (0x0030001C) // (UHP) Current Isochronous or Interrupt Endpoint Descriptor\n#define AT91C_UHP_HcControlCurrentED (0x00300024) // (UHP) Endpoint Control and Status Register\n#define AT91C_UHP_HcBulkCurrentED (0x0030002C) // (UHP) Current endpoint of the Bulk list\n#define AT91C_UHP_HcFmInterval    (0x00300034) // (UHP) Bit time between 2 consecutive SOFs\n#define AT91C_UHP_HcBulkHeadED    (0x00300028) // (UHP) First endpoint register of the Bulk list\n#define AT91C_UHP_HcBulkDoneHead  (0x00300030) // (UHP) Last completed transfer descriptor\n#define AT91C_UHP_HcFmRemaining   (0x00300038) // (UHP) Bit time remaining in the current Frame\n#define AT91C_UHP_HcPeriodicStart (0x00300040) // (UHP) Periodic Start\n#define AT91C_UHP_HcLSThreshold   (0x00300044) // (UHP) LS Threshold\n#define AT91C_UHP_HcFmNumber      (0x0030003C) // (UHP) Frame number\n// ========== Register definition for EMAC peripheral ========== \n#define AT91C_EMAC_RSR            (0xFFFBC020) // (EMAC) Receive Status Register\n#define AT91C_EMAC_MAN            (0xFFFBC034) // (EMAC) PHY Maintenance Register\n#define AT91C_EMAC_HSH            (0xFFFBC090) // (EMAC) Hash Address High[63:32]\n#define AT91C_EMAC_MCOL           (0xFFFBC048) // (EMAC) Multiple Collision Frame Register\n#define AT91C_EMAC_IER            (0xFFFBC028) // (EMAC) Interrupt Enable Register\n#define AT91C_EMAC_SA2H           (0xFFFBC0A4) // (EMAC) Specific Address 2 High, Last 2 bytes\n#define AT91C_EMAC_HSL            (0xFFFBC094) // (EMAC) Hash Address Low[31:0]\n#define AT91C_EMAC_LCOL           (0xFFFBC05C) // (EMAC) Late Collision Register\n#define AT91C_EMAC_OK             (0xFFFBC04C) // (EMAC) Frames Received OK Register\n#define AT91C_EMAC_CFG            (0xFFFBC004) // (EMAC) Network Configuration Register\n#define AT91C_EMAC_SA3L           (0xFFFBC0A8) // (EMAC) Specific Address 3 Low, First 4 bytes\n#define AT91C_EMAC_SEQE           (0xFFFBC050) // (EMAC) Frame Check Sequence Error Register\n#define AT91C_EMAC_ECOL           (0xFFFBC060) // (EMAC) Excessive Collision Register\n#define AT91C_EMAC_ELR            (0xFFFBC070) // (EMAC) Excessive Length Error Register\n#define AT91C_EMAC_SR             (0xFFFBC008) // (EMAC) Network Status Register\n#define AT91C_EMAC_RBQP           (0xFFFBC018) // (EMAC) Receive Buffer Queue Pointer\n#define AT91C_EMAC_CSE            (0xFFFBC064) // (EMAC) Carrier Sense Error Register\n#define AT91C_EMAC_RJB            (0xFFFBC074) // (EMAC) Receive Jabber Register\n#define AT91C_EMAC_USF            (0xFFFBC078) // (EMAC) Undersize Frame Register\n#define AT91C_EMAC_IDR            (0xFFFBC02C) // (EMAC) Interrupt Disable Register\n#define AT91C_EMAC_SA1L           (0xFFFBC098) // (EMAC) Specific Address 1 Low, First 4 bytes\n#define AT91C_EMAC_IMR            (0xFFFBC030) // (EMAC) Interrupt Mask Register\n#define AT91C_EMAC_FRA            (0xFFFBC040) // (EMAC) Frames Transmitted OK Register\n#define AT91C_EMAC_SA3H           (0xFFFBC0AC) // (EMAC) Specific Address 3 High, Last 2 bytes\n#define AT91C_EMAC_SA1H           (0xFFFBC09C) // (EMAC) Specific Address 1 High, Last 2 bytes\n#define AT91C_EMAC_SCOL           (0xFFFBC044) // (EMAC) Single Collision Frame Register\n#define AT91C_EMAC_ALE            (0xFFFBC054) // (EMAC) Alignment Error Register\n#define AT91C_EMAC_TAR            (0xFFFBC00C) // (EMAC) Transmit Address Register\n#define AT91C_EMAC_SA4L           (0xFFFBC0B0) // (EMAC) Specific Address 4 Low, First 4 bytes\n#define AT91C_EMAC_SA2L           (0xFFFBC0A0) // (EMAC) Specific Address 2 Low, First 4 bytes\n#define AT91C_EMAC_TUE            (0xFFFBC068) // (EMAC) Transmit Underrun Error Register\n#define AT91C_EMAC_DTE            (0xFFFBC058) // (EMAC) Deferred Transmission Frame Register\n#define AT91C_EMAC_TCR            (0xFFFBC010) // (EMAC) Transmit Control Register\n#define AT91C_EMAC_CTL            (0xFFFBC000) // (EMAC) Network Control Register\n#define AT91C_EMAC_SA4H           (0xFFFBC0B4) // (EMAC) Specific Address 4 High, Last 2 bytesr\n#define AT91C_EMAC_CDE            (0xFFFBC06C) // (EMAC) Code Error Register\n#define AT91C_EMAC_SQEE           (0xFFFBC07C) // (EMAC) SQE Test Error Register\n#define AT91C_EMAC_TSR            (0xFFFBC014) // (EMAC) Transmit Status Register\n#define AT91C_EMAC_DRFC           (0xFFFBC080) // (EMAC) Discarded RX Frame Register\n// ========== Register definition for EBI peripheral ========== \n#define AT91C_EBI_CFGR            (0xFFFFFF64) // (EBI) Configuration Register\n#define AT91C_EBI_CSA             (0xFFFFFF60) // (EBI) Chip Select Assignment Register\n// ========== Register definition for SMC2 peripheral ========== \n#define AT91C_SMC2_CSR            (0xFFFFFF70) // (SMC2) SMC2 Chip Select Register\n// ========== Register definition for SDRC peripheral ========== \n#define AT91C_SDRC_IMR            (0xFFFFFFAC) // (SDRC) SDRAM Controller Interrupt Mask Register\n#define AT91C_SDRC_IER            (0xFFFFFFA4) // (SDRC) SDRAM Controller Interrupt Enable Register\n#define AT91C_SDRC_SRR            (0xFFFFFF9C) // (SDRC) SDRAM Controller Self Refresh Register\n#define AT91C_SDRC_TR             (0xFFFFFF94) // (SDRC) SDRAM Controller Refresh Timer Register\n#define AT91C_SDRC_ISR            (0xFFFFFFB0) // (SDRC) SDRAM Controller Interrupt Mask Register\n#define AT91C_SDRC_IDR            (0xFFFFFFA8) // (SDRC) SDRAM Controller Interrupt Disable Register\n#define AT91C_SDRC_LPR            (0xFFFFFFA0) // (SDRC) SDRAM Controller Low Power Register\n#define AT91C_SDRC_CR             (0xFFFFFF98) // (SDRC) SDRAM Controller Configuration Register\n#define AT91C_SDRC_MR             (0xFFFFFF90) // (SDRC) SDRAM Controller Mode Register\n// ========== Register definition for BFC peripheral ========== \n#define AT91C_BFC_MR              (0xFFFFFFC0) // (BFC) BFC Mode Register\n\n// *****************************************************************************\n//               PIO DEFINITIONS FOR AT91RM9200\n// *****************************************************************************\n#define AT91C_PIO_PA0             (1 <<  0) // Pin Controlled by PA0\n#define AT91C_PA0_MISO            (AT91C_PIO_PA0) //  SPI Master In Slave\n#define AT91C_PA0_PCK3            (AT91C_PIO_PA0) //  PMC Programmable Clock Output 3\n#define AT91C_PIO_PA1             (1 <<  1) // Pin Controlled by PA1\n#define AT91C_PA1_MOSI            (AT91C_PIO_PA1) //  SPI Master Out Slave\n#define AT91C_PA1_PCK0            (AT91C_PIO_PA1) //  PMC Programmable Clock Output 0\n#define AT91C_PIO_PA10            (1 << 10) // Pin Controlled by PA10\n#define AT91C_PA10_ETX1           (AT91C_PIO_PA10) //  Ethernet MAC Transmit Data 1\n#define AT91C_PA10_MCDB1          (AT91C_PIO_PA10) //  Multimedia Card B Data 1\n#define AT91C_PIO_PA11            (1 << 11) // Pin Controlled by PA11\n#define AT91C_PA11_ECRS_ECRSDV    (AT91C_PIO_PA11) //  Ethernet MAC Carrier Sense/Carrier Sense and Data Valid\n#define AT91C_PA11_MCDB2          (AT91C_PIO_PA11) //  Multimedia Card B Data 2\n#define AT91C_PIO_PA12            (1 << 12) // Pin Controlled by PA12\n#define AT91C_PA12_ERX0           (AT91C_PIO_PA12) //  Ethernet MAC Receive Data 0\n#define AT91C_PA12_MCDB3          (AT91C_PIO_PA12) //  Multimedia Card B Data 3\n#define AT91C_PIO_PA13            (1 << 13) // Pin Controlled by PA13\n#define AT91C_PA13_ERX1           (AT91C_PIO_PA13) //  Ethernet MAC Receive Data 1\n#define AT91C_PA13_TCLK0          (AT91C_PIO_PA13) //  Timer Counter 0 external clock input\n#define AT91C_PIO_PA14            (1 << 14) // Pin Controlled by PA14\n#define AT91C_PA14_ERXER          (AT91C_PIO_PA14) //  Ethernet MAC Receive Error\n#define AT91C_PA14_TCLK1          (AT91C_PIO_PA14) //  Timer Counter 1 external clock input\n#define AT91C_PIO_PA15            (1 << 15) // Pin Controlled by PA15\n#define AT91C_PA15_EMDC           (AT91C_PIO_PA15) //  Ethernet MAC Management Data Clock\n#define AT91C_PA15_TCLK2          (AT91C_PIO_PA15) //  Timer Counter 2 external clock input\n#define AT91C_PIO_PA16            (1 << 16) // Pin Controlled by PA16\n#define AT91C_PA16_EMDIO          (AT91C_PIO_PA16) //  Ethernet MAC Management Data Input/Output\n#define AT91C_PA16_IRQ6           (AT91C_PIO_PA16) //  AIC Interrupt input 6\n#define AT91C_PIO_PA17            (1 << 17) // Pin Controlled by PA17\n#define AT91C_PA17_TXD0           (AT91C_PIO_PA17) //  USART 0 Transmit Data\n#define AT91C_PA17_TIOA0          (AT91C_PIO_PA17) //  Timer Counter 0 Multipurpose Timer I/O Pin A\n#define AT91C_PIO_PA18            (1 << 18) // Pin Controlled by PA18\n#define AT91C_PA18_RXD0           (AT91C_PIO_PA18) //  USART 0 Receive Data\n#define AT91C_PA18_TIOB0          (AT91C_PIO_PA18) //  Timer Counter 0 Multipurpose Timer I/O Pin B\n#define AT91C_PIO_PA19            (1 << 19) // Pin Controlled by PA19\n#define AT91C_PA19_SCK0           (AT91C_PIO_PA19) //  USART 0 Serial Clock\n#define AT91C_PA19_TIOA1          (AT91C_PIO_PA19) //  Timer Counter 1 Multipurpose Timer I/O Pin A\n#define AT91C_PIO_PA2             (1 <<  2) // Pin Controlled by PA2\n#define AT91C_PA2_SPCK            (AT91C_PIO_PA2) //  SPI Serial Clock\n#define AT91C_PA2_IRQ4            (AT91C_PIO_PA2) //  AIC Interrupt Input 4\n#define AT91C_PIO_PA20            (1 << 20) // Pin Controlled by PA20\n#define AT91C_PA20_CTS0           (AT91C_PIO_PA20) //  USART 0 Clear To Send\n#define AT91C_PA20_TIOB1          (AT91C_PIO_PA20) //  Timer Counter 1 Multipurpose Timer I/O Pin B\n#define AT91C_PIO_PA21            (1 << 21) // Pin Controlled by PA21\n#define AT91C_PA21_RTS0           (AT91C_PIO_PA21) //  Usart 0 Ready To Send\n#define AT91C_PA21_TIOA2          (AT91C_PIO_PA21) //  Timer Counter 2 Multipurpose Timer I/O Pin A\n#define AT91C_PIO_PA22            (1 << 22) // Pin Controlled by PA22\n#define AT91C_PA22_RXD2           (AT91C_PIO_PA22) //  USART 2 Receive Data\n#define AT91C_PA22_TIOB2          (AT91C_PIO_PA22) //  Timer Counter 2 Multipurpose Timer I/O Pin B\n#define AT91C_PIO_PA23            (1 << 23) // Pin Controlled by PA23\n#define AT91C_PA23_TXD2           (AT91C_PIO_PA23) //  USART 2 Transmit Data\n#define AT91C_PA23_IRQ3           (AT91C_PIO_PA23) //  Interrupt input 3\n#define AT91C_PIO_PA24            (1 << 24) // Pin Controlled by PA24\n#define AT91C_PA24_SCK2           (AT91C_PIO_PA24) //  USART2 Serial Clock\n#define AT91C_PA24_PCK1           (AT91C_PIO_PA24) //  PMC Programmable Clock Output 1\n#define AT91C_PIO_PA25            (1 << 25) // Pin Controlled by PA25\n#define AT91C_PA25_TWD            (AT91C_PIO_PA25) //  TWI Two-wire Serial Data\n#define AT91C_PA25_IRQ2           (AT91C_PIO_PA25) //  Interrupt input 2\n#define AT91C_PIO_PA26            (1 << 26) // Pin Controlled by PA26\n#define AT91C_PA26_TWCK           (AT91C_PIO_PA26) //  TWI Two-wire Serial Clock\n#define AT91C_PA26_IRQ1           (AT91C_PIO_PA26) //  Interrupt input 1\n#define AT91C_PIO_PA27            (1 << 27) // Pin Controlled by PA27\n#define AT91C_PA27_MCCK           (AT91C_PIO_PA27) //  Multimedia Card Clock\n#define AT91C_PA27_TCLK3          (AT91C_PIO_PA27) //  Timer Counter 3 External Clock Input\n#define AT91C_PIO_PA28            (1 << 28) // Pin Controlled by PA28\n#define AT91C_PA28_MCCDA          (AT91C_PIO_PA28) //  Multimedia Card A Command\n#define AT91C_PA28_TCLK4          (AT91C_PIO_PA28) //  Timer Counter 4 external Clock Input\n#define AT91C_PIO_PA29            (1 << 29) // Pin Controlled by PA29\n#define AT91C_PA29_MCDA0          (AT91C_PIO_PA29) //  Multimedia Card A Data 0\n#define AT91C_PA29_TCLK5          (AT91C_PIO_PA29) //  Timer Counter 5 external clock input\n#define AT91C_PIO_PA3             (1 <<  3) // Pin Controlled by PA3\n#define AT91C_PA3_NPCS0           (AT91C_PIO_PA3) //  SPI Peripheral Chip Select 0\n#define AT91C_PA3_IRQ5            (AT91C_PIO_PA3) //  AIC Interrupt Input 5\n#define AT91C_PIO_PA30            (1 << 30) // Pin Controlled by PA30\n#define AT91C_PA30_DRXD           (AT91C_PIO_PA30) //  DBGU Debug Receive Data\n#define AT91C_PA30_CTS2           (AT91C_PIO_PA30) //  Usart 2 Clear To Send\n#define AT91C_PIO_PA31            (1 << 31) // Pin Controlled by PA31\n#define AT91C_PA31_DTXD           (AT91C_PIO_PA31) //  DBGU Debug Transmit Data\n#define AT91C_PA31_RTS2           (AT91C_PIO_PA31) //  USART 2 Ready To Send\n#define AT91C_PIO_PA4             (1 <<  4) // Pin Controlled by PA4\n#define AT91C_PA4_NPCS1           (AT91C_PIO_PA4) //  SPI Peripheral Chip Select 1\n#define AT91C_PA4_PCK1            (AT91C_PIO_PA4) //  PMC Programmable Clock Output 1\n#define AT91C_PIO_PA5             (1 <<  5) // Pin Controlled by PA5\n#define AT91C_PA5_NPCS2           (AT91C_PIO_PA5) //  SPI Peripheral Chip Select 2\n#define AT91C_PA5_TXD3            (AT91C_PIO_PA5) //  USART 3 Transmit Data\n#define AT91C_PIO_PA6             (1 <<  6) // Pin Controlled by PA6\n#define AT91C_PA6_NPCS3           (AT91C_PIO_PA6) //  SPI Peripheral Chip Select 3\n#define AT91C_PA6_RXD3            (AT91C_PIO_PA6) //  USART 3 Receive Data\n#define AT91C_PIO_PA7             (1 <<  7) // Pin Controlled by PA7\n#define AT91C_PA7_ETXCK_EREFCK    (AT91C_PIO_PA7) //  Ethernet MAC Transmit Clock/Reference Clock\n#define AT91C_PA7_PCK2            (AT91C_PIO_PA7) //  PMC Programmable Clock 2\n#define AT91C_PIO_PA8             (1 <<  8) // Pin Controlled by PA8\n#define AT91C_PA8_ETXEN           (AT91C_PIO_PA8) //  Ethernet MAC Transmit Enable\n#define AT91C_PA8_MCCDB           (AT91C_PIO_PA8) //  Multimedia Card B Command\n#define AT91C_PIO_PA9             (1 <<  9) // Pin Controlled by PA9\n#define AT91C_PA9_ETX0            (AT91C_PIO_PA9) //  Ethernet MAC Transmit Data 0\n#define AT91C_PA9_MCDB0           (AT91C_PIO_PA9) //  Multimedia Card B Data 0\n#define AT91C_PIO_PB0             (1 <<  0) // Pin Controlled by PB0\n#define AT91C_PB0_TF0             (AT91C_PIO_PB0) //  SSC Transmit Frame Sync 0\n#define AT91C_PB0_TIOB3           (AT91C_PIO_PB0) //  Timer Counter 3 Multipurpose Timer I/O Pin B\n#define AT91C_PIO_PB1             (1 <<  1) // Pin Controlled by PB1\n#define AT91C_PB1_TK0             (AT91C_PIO_PB1) //  SSC Transmit Clock 0\n#define AT91C_PB1_CTS3            (AT91C_PIO_PB1) //  USART 3 Clear To Send\n#define AT91C_PIO_PB10            (1 << 10) // Pin Controlled by PB10\n#define AT91C_PB10_RK1            (AT91C_PIO_PB10) //  SSC Receive Clock 1\n#define AT91C_PB10_TIOA5          (AT91C_PIO_PB10) //  Timer Counter 5 Multipurpose Timer I/O Pin A\n#define AT91C_PIO_PB11            (1 << 11) // Pin Controlled by PB11\n#define AT91C_PB11_RF1            (AT91C_PIO_PB11) //  SSC Receive Frame Sync 1\n#define AT91C_PB11_TIOB5          (AT91C_PIO_PB11) //  Timer Counter 5 Multipurpose Timer I/O Pin B\n#define AT91C_PIO_PB12            (1 << 12) // Pin Controlled by PB12\n#define AT91C_PB12_TF2            (AT91C_PIO_PB12) //  SSC Transmit Frame Sync 2\n#define AT91C_PB12_ETX2           (AT91C_PIO_PB12) //  Ethernet MAC Transmit Data 2\n#define AT91C_PIO_PB13            (1 << 13) // Pin Controlled by PB13\n#define AT91C_PB13_TK2            (AT91C_PIO_PB13) //  SSC Transmit Clock 2\n#define AT91C_PB13_ETX3           (AT91C_PIO_PB13) //  Ethernet MAC Transmit Data 3\n#define AT91C_PIO_PB14            (1 << 14) // Pin Controlled by PB14\n#define AT91C_PB14_TD2            (AT91C_PIO_PB14) //  SSC Transmit Data 2\n#define AT91C_PB14_ETXER          (AT91C_PIO_PB14) //  Ethernet MAC Transmikt Coding Error\n#define AT91C_PIO_PB15            (1 << 15) // Pin Controlled by PB15\n#define AT91C_PB15_RD2            (AT91C_PIO_PB15) //  SSC Receive Data 2\n#define AT91C_PB15_ERX2           (AT91C_PIO_PB15) //  Ethernet MAC Receive Data 2\n#define AT91C_PIO_PB16            (1 << 16) // Pin Controlled by PB16\n#define AT91C_PB16_RK2            (AT91C_PIO_PB16) //  SSC Receive Clock 2\n#define AT91C_PB16_ERX3           (AT91C_PIO_PB16) //  Ethernet MAC Receive Data 3\n#define AT91C_PIO_PB17            (1 << 17) // Pin Controlled by PB17\n#define AT91C_PB17_RF2            (AT91C_PIO_PB17) //  SSC Receive Frame Sync 2\n#define AT91C_PB17_ERXDV          (AT91C_PIO_PB17) //  Ethernet MAC Receive Data Valid\n#define AT91C_PIO_PB18            (1 << 18) // Pin Controlled by PB18\n#define AT91C_PB18_RI1            (AT91C_PIO_PB18) //  USART 1 Ring Indicator\n#define AT91C_PB18_ECOL           (AT91C_PIO_PB18) //  Ethernet MAC Collision Detected\n#define AT91C_PIO_PB19            (1 << 19) // Pin Controlled by PB19\n#define AT91C_PB19_DTR1           (AT91C_PIO_PB19) //  USART 1 Data Terminal ready\n#define AT91C_PB19_ERXCK          (AT91C_PIO_PB19) //  Ethernet MAC Receive Clock\n#define AT91C_PIO_PB2             (1 <<  2) // Pin Controlled by PB2\n#define AT91C_PB2_TD0             (AT91C_PIO_PB2) //  SSC Transmit data\n#define AT91C_PB2_SCK3            (AT91C_PIO_PB2) //  USART 3 Serial Clock\n#define AT91C_PIO_PB20            (1 << 20) // Pin Controlled by PB20\n#define AT91C_PB20_TXD1           (AT91C_PIO_PB20) //  USART 1 Transmit Data\n#define AT91C_PIO_PB21            (1 << 21) // Pin Controlled by PB21\n#define AT91C_PB21_RXD1           (AT91C_PIO_PB21) //  USART 1 Receive Data\n#define AT91C_PIO_PB22            (1 << 22) // Pin Controlled by PB22\n#define AT91C_PB22_SCK1           (AT91C_PIO_PB22) //  USART1 Serial Clock\n#define AT91C_PIO_PB23            (1 << 23) // Pin Controlled by PB23\n#define AT91C_PB23_DCD1           (AT91C_PIO_PB23) //  USART 1 Data Carrier Detect\n#define AT91C_PIO_PB24            (1 << 24) // Pin Controlled by PB24\n#define AT91C_PB24_CTS1           (AT91C_PIO_PB24) //  USART 1 Clear To Send\n#define AT91C_PIO_PB25            (1 << 25) // Pin Controlled by PB25\n#define AT91C_PB25_DSR1           (AT91C_PIO_PB25) //  USART 1 Data Set ready\n#define AT91C_PB25_EF100          (AT91C_PIO_PB25) //  Ethernet MAC Force 100 Mbits/sec\n#define AT91C_PIO_PB26            (1 << 26) // Pin Controlled by PB26\n#define AT91C_PB26_RTS1           (AT91C_PIO_PB26) //  Usart 0 Ready To Send\n#define AT91C_PIO_PB27            (1 << 27) // Pin Controlled by PB27\n#define AT91C_PB27_PCK0           (AT91C_PIO_PB27) //  PMC Programmable Clock Output 0\n#define AT91C_PIO_PB28            (1 << 28) // Pin Controlled by PB28\n#define AT91C_PB28_FIQ            (AT91C_PIO_PB28) //  AIC Fast Interrupt Input\n#define AT91C_PIO_PB29            (1 << 29) // Pin Controlled by PB29\n#define AT91C_PB29_IRQ0           (AT91C_PIO_PB29) //  Interrupt input 0\n#define AT91C_PIO_PB3             (1 <<  3) // Pin Controlled by PB3\n#define AT91C_PB3_RD0             (AT91C_PIO_PB3) //  SSC Receive Data\n#define AT91C_PB3_MCDA1           (AT91C_PIO_PB3) //  Multimedia Card A Data 1\n#define AT91C_PIO_PB4             (1 <<  4) // Pin Controlled by PB4\n#define AT91C_PB4_RK0             (AT91C_PIO_PB4) //  SSC Receive Clock\n#define AT91C_PB4_MCDA2           (AT91C_PIO_PB4) //  Multimedia Card A Data 2\n#define AT91C_PIO_PB5             (1 <<  5) // Pin Controlled by PB5\n#define AT91C_PB5_RF0             (AT91C_PIO_PB5) //  SSC Receive Frame Sync 0\n#define AT91C_PB5_MCDA3           (AT91C_PIO_PB5) //  Multimedia Card A Data 3\n#define AT91C_PIO_PB6             (1 <<  6) // Pin Controlled by PB6\n#define AT91C_PB6_TF1             (AT91C_PIO_PB6) //  SSC Transmit Frame Sync 1\n#define AT91C_PB6_TIOA3           (AT91C_PIO_PB6) //  Timer Counter 4 Multipurpose Timer I/O Pin A\n#define AT91C_PIO_PB7             (1 <<  7) // Pin Controlled by PB7\n#define AT91C_PB7_TK1             (AT91C_PIO_PB7) //  SSC Transmit Clock 1\n#define AT91C_PB7_TIOB3           (AT91C_PIO_PB7) //  Timer Counter 3 Multipurpose Timer I/O Pin B\n#define AT91C_PIO_PB8             (1 <<  8) // Pin Controlled by PB8\n#define AT91C_PB8_TD1             (AT91C_PIO_PB8) //  SSC Transmit Data 1\n#define AT91C_PB8_TIOA4           (AT91C_PIO_PB8) //  Timer Counter 4 Multipurpose Timer I/O Pin A\n#define AT91C_PIO_PB9             (1 <<  9) // Pin Controlled by PB9\n#define AT91C_PB9_RD1             (AT91C_PIO_PB9) //  SSC Receive Data 1\n#define AT91C_PB9_TIOB4           (AT91C_PIO_PB9) //  Timer Counter 4 Multipurpose Timer I/O Pin B\n#define AT91C_PIO_PC0             (1 <<  0) // Pin Controlled by PC0\n#define AT91C_PC0_BFCK            (AT91C_PIO_PC0) //  Burst Flash Clock\n#define AT91C_PIO_PC1             (1 <<  1) // Pin Controlled by PC1\n#define AT91C_PC1_BFRDY_SMOE      (AT91C_PIO_PC1) //  Burst Flash Ready\n#define AT91C_PIO_PC10            (1 << 10) // Pin Controlled by PC10\n#define AT91C_PC10_NCS4_CFCS      (AT91C_PIO_PC10) //  Compact Flash Chip Select\n#define AT91C_PIO_PC11            (1 << 11) // Pin Controlled by PC11\n#define AT91C_PC11_NCS5_CFCE1     (AT91C_PIO_PC11) //  Chip Select 5 / Compact Flash Chip Enable 1\n#define AT91C_PIO_PC12            (1 << 12) // Pin Controlled by PC12\n#define AT91C_PC12_NCS6_CFCE2     (AT91C_PIO_PC12) //  Chip Select 6 / Compact Flash Chip Enable 2\n#define AT91C_PIO_PC13            (1 << 13) // Pin Controlled by PC13\n#define AT91C_PC13_NCS7           (AT91C_PIO_PC13) //  Chip Select 7\n#define AT91C_PIO_PC14            (1 << 14) // Pin Controlled by PC14\n#define AT91C_PIO_PC15            (1 << 15) // Pin Controlled by PC15\n#define AT91C_PIO_PC16            (1 << 16) // Pin Controlled by PC16\n#define AT91C_PC16_D16            (AT91C_PIO_PC16) //  Data Bus [16]\n#define AT91C_PIO_PC17            (1 << 17) // Pin Controlled by PC17\n#define AT91C_PC17_D17            (AT91C_PIO_PC17) //  Data Bus [17]\n#define AT91C_PIO_PC18            (1 << 18) // Pin Controlled by PC18\n#define AT91C_PC18_D18            (AT91C_PIO_PC18) //  Data Bus [18]\n#define AT91C_PIO_PC19            (1 << 19) // Pin Controlled by PC19\n#define AT91C_PC19_D19            (AT91C_PIO_PC19) //  Data Bus [19]\n#define AT91C_PIO_PC2             (1 <<  2) // Pin Controlled by PC2\n#define AT91C_PC2_BFAVD           (AT91C_PIO_PC2) //  Burst Flash Address Valid\n#define AT91C_PIO_PC20            (1 << 20) // Pin Controlled by PC20\n#define AT91C_PC20_D20            (AT91C_PIO_PC20) //  Data Bus [20]\n#define AT91C_PIO_PC21            (1 << 21) // Pin Controlled by PC21\n#define AT91C_PC21_D21            (AT91C_PIO_PC21) //  Data Bus [21]\n#define AT91C_PIO_PC22            (1 << 22) // Pin Controlled by PC22\n#define AT91C_PC22_D22            (AT91C_PIO_PC22) //  Data Bus [22]\n#define AT91C_PIO_PC23            (1 << 23) // Pin Controlled by PC23\n#define AT91C_PC23_D23            (AT91C_PIO_PC23) //  Data Bus [23]\n#define AT91C_PIO_PC24            (1 << 24) // Pin Controlled by PC24\n#define AT91C_PC24_D24            (AT91C_PIO_PC24) //  Data Bus [24]\n#define AT91C_PIO_PC25            (1 << 25) // Pin Controlled by PC25\n#define AT91C_PC25_D25            (AT91C_PIO_PC25) //  Data Bus [25]\n#define AT91C_PIO_PC26            (1 << 26) // Pin Controlled by PC26\n#define AT91C_PC26_D26            (AT91C_PIO_PC26) //  Data Bus [26]\n#define AT91C_PIO_PC27            (1 << 27) // Pin Controlled by PC27\n#define AT91C_PC27_D27            (AT91C_PIO_PC27) //  Data Bus [27]\n#define AT91C_PIO_PC28            (1 << 28) // Pin Controlled by PC28\n#define AT91C_PC28_D28            (AT91C_PIO_PC28) //  Data Bus [28]\n#define AT91C_PIO_PC29            (1 << 29) // Pin Controlled by PC29\n#define AT91C_PC29_D29            (AT91C_PIO_PC29) //  Data Bus [29]\n#define AT91C_PIO_PC3             (1 <<  3) // Pin Controlled by PC3\n#define AT91C_PC3_BFBAA_SMWE      (AT91C_PIO_PC3) //  Burst Flash Address Advance / SmartMedia Write Enable\n#define AT91C_PIO_PC30            (1 << 30) // Pin Controlled by PC30\n#define AT91C_PC30_D30            (AT91C_PIO_PC30) //  Data Bus [30]\n#define AT91C_PIO_PC31            (1 << 31) // Pin Controlled by PC31\n#define AT91C_PC31_D31            (AT91C_PIO_PC31) //  Data Bus [31]\n#define AT91C_PIO_PC4             (1 <<  4) // Pin Controlled by PC4\n#define AT91C_PC4_BFOE            (AT91C_PIO_PC4) //  Burst Flash Output Enable\n#define AT91C_PIO_PC5             (1 <<  5) // Pin Controlled by PC5\n#define AT91C_PC5_BFWE            (AT91C_PIO_PC5) //  Burst Flash Write Enable\n#define AT91C_PIO_PC6             (1 <<  6) // Pin Controlled by PC6\n#define AT91C_PC6_NWAIT           (AT91C_PIO_PC6) //  NWAIT\n#define AT91C_PIO_PC7             (1 <<  7) // Pin Controlled by PC7\n#define AT91C_PC7_A23             (AT91C_PIO_PC7) //  Address Bus[23]\n#define AT91C_PIO_PC8             (1 <<  8) // Pin Controlled by PC8\n#define AT91C_PC8_A24             (AT91C_PIO_PC8) //  Address Bus[24]\n#define AT91C_PIO_PC9             (1 <<  9) // Pin Controlled by PC9\n#define AT91C_PC9_A25_CFRNW       (AT91C_PIO_PC9) //  Address Bus[25] /  Compact Flash Read Not Write\n#define AT91C_PIO_PD0             (1 <<  0) // Pin Controlled by PD0\n#define AT91C_PD0_ETX0            (AT91C_PIO_PD0) //  Ethernet MAC Transmit Data 0\n#define AT91C_PIO_PD1             (1 <<  1) // Pin Controlled by PD1\n#define AT91C_PD1_ETX1            (AT91C_PIO_PD1) //  Ethernet MAC Transmit Data 1\n#define AT91C_PIO_PD10            (1 << 10) // Pin Controlled by PD10\n#define AT91C_PD10_PCK3           (AT91C_PIO_PD10) //  PMC Programmable Clock Output 3\n#define AT91C_PD10_TPS1           (AT91C_PIO_PD10) //  ETM ARM9 pipeline status 1\n#define AT91C_PIO_PD11            (1 << 11) // Pin Controlled by PD11\n#define AT91C_PD11_               (AT91C_PIO_PD11) //  \n#define AT91C_PD11_TPS2           (AT91C_PIO_PD11) //  ETM ARM9 pipeline status 2\n#define AT91C_PIO_PD12            (1 << 12) // Pin Controlled by PD12\n#define AT91C_PD12_               (AT91C_PIO_PD12) //  \n#define AT91C_PD12_TPK0           (AT91C_PIO_PD12) //  ETM Trace Packet 0\n#define AT91C_PIO_PD13            (1 << 13) // Pin Controlled by PD13\n#define AT91C_PD13_               (AT91C_PIO_PD13) //  \n#define AT91C_PD13_TPK1           (AT91C_PIO_PD13) //  ETM Trace Packet 1\n#define AT91C_PIO_PD14            (1 << 14) // Pin Controlled by PD14\n#define AT91C_PD14_               (AT91C_PIO_PD14) //  \n#define AT91C_PD14_TPK2           (AT91C_PIO_PD14) //  ETM Trace Packet 2\n#define AT91C_PIO_PD15            (1 << 15) // Pin Controlled by PD15\n#define AT91C_PD15_TD0            (AT91C_PIO_PD15) //  SSC Transmit data\n#define AT91C_PD15_TPK3           (AT91C_PIO_PD15) //  ETM Trace Packet 3\n#define AT91C_PIO_PD16            (1 << 16) // Pin Controlled by PD16\n#define AT91C_PD16_TD1            (AT91C_PIO_PD16) //  SSC Transmit Data 1\n#define AT91C_PD16_TPK4           (AT91C_PIO_PD16) //  ETM Trace Packet 4\n#define AT91C_PIO_PD17            (1 << 17) // Pin Controlled by PD17\n#define AT91C_PD17_TD2            (AT91C_PIO_PD17) //  SSC Transmit Data 2\n#define AT91C_PD17_TPK5           (AT91C_PIO_PD17) //  ETM Trace Packet 5\n#define AT91C_PIO_PD18            (1 << 18) // Pin Controlled by PD18\n#define AT91C_PD18_NPCS1          (AT91C_PIO_PD18) //  SPI Peripheral Chip Select 1\n#define AT91C_PD18_TPK6           (AT91C_PIO_PD18) //  ETM Trace Packet 6\n#define AT91C_PIO_PD19            (1 << 19) // Pin Controlled by PD19\n#define AT91C_PD19_NPCS2          (AT91C_PIO_PD19) //  SPI Peripheral Chip Select 2\n#define AT91C_PD19_TPK7           (AT91C_PIO_PD19) //  ETM Trace Packet 7\n#define AT91C_PIO_PD2             (1 <<  2) // Pin Controlled by PD2\n#define AT91C_PD2_ETX2            (AT91C_PIO_PD2) //  Ethernet MAC Transmit Data 2\n#define AT91C_PIO_PD20            (1 << 20) // Pin Controlled by PD20\n#define AT91C_PD20_NPCS3          (AT91C_PIO_PD20) //  SPI Peripheral Chip Select 3\n#define AT91C_PD20_TPK8           (AT91C_PIO_PD20) //  ETM Trace Packet 8\n#define AT91C_PIO_PD21            (1 << 21) // Pin Controlled by PD21\n#define AT91C_PD21_RTS0           (AT91C_PIO_PD21) //  Usart 0 Ready To Send\n#define AT91C_PD21_TPK9           (AT91C_PIO_PD21) //  ETM Trace Packet 9\n#define AT91C_PIO_PD22            (1 << 22) // Pin Controlled by PD22\n#define AT91C_PD22_RTS1           (AT91C_PIO_PD22) //  Usart 0 Ready To Send\n#define AT91C_PD22_TPK10          (AT91C_PIO_PD22) //  ETM Trace Packet 10\n#define AT91C_PIO_PD23            (1 << 23) // Pin Controlled by PD23\n#define AT91C_PD23_RTS2           (AT91C_PIO_PD23) //  USART 2 Ready To Send\n#define AT91C_PD23_TPK11          (AT91C_PIO_PD23) //  ETM Trace Packet 11\n#define AT91C_PIO_PD24            (1 << 24) // Pin Controlled by PD24\n#define AT91C_PD24_RTS3           (AT91C_PIO_PD24) //  USART 3 Ready To Send\n#define AT91C_PD24_TPK12          (AT91C_PIO_PD24) //  ETM Trace Packet 12\n#define AT91C_PIO_PD25            (1 << 25) // Pin Controlled by PD25\n#define AT91C_PD25_DTR1           (AT91C_PIO_PD25) //  USART 1 Data Terminal ready\n#define AT91C_PD25_TPK13          (AT91C_PIO_PD25) //  ETM Trace Packet 13\n#define AT91C_PIO_PD26            (1 << 26) // Pin Controlled by PD26\n#define AT91C_PD26_TPK14          (AT91C_PIO_PD26) //  ETM Trace Packet 14\n#define AT91C_PIO_PD27            (1 << 27) // Pin Controlled by PD27\n#define AT91C_PD27_TPK15          (AT91C_PIO_PD27) //  ETM Trace Packet 15\n#define AT91C_PIO_PD3             (1 <<  3) // Pin Controlled by PD3\n#define AT91C_PD3_ETX3            (AT91C_PIO_PD3) //  Ethernet MAC Transmit Data 3\n#define AT91C_PIO_PD4             (1 <<  4) // Pin Controlled by PD4\n#define AT91C_PD4_ETXEN           (AT91C_PIO_PD4) //  Ethernet MAC Transmit Enable\n#define AT91C_PIO_PD5             (1 <<  5) // Pin Controlled by PD5\n#define AT91C_PD5_ETXER           (AT91C_PIO_PD5) //  Ethernet MAC Transmikt Coding Error\n#define AT91C_PIO_PD6             (1 <<  6) // Pin Controlled by PD6\n#define AT91C_PD6_DTXD            (AT91C_PIO_PD6) //  DBGU Debug Transmit Data\n#define AT91C_PIO_PD7             (1 <<  7) // Pin Controlled by PD7\n#define AT91C_PD7_PCK0            (AT91C_PIO_PD7) //  PMC Programmable Clock Output 0\n#define AT91C_PD7_TSYNC           (AT91C_PIO_PD7) //  ETM Synchronization signal\n#define AT91C_PIO_PD8             (1 <<  8) // Pin Controlled by PD8\n#define AT91C_PD8_PCK1            (AT91C_PIO_PD8) //  PMC Programmable Clock Output 1\n#define AT91C_PD8_TCLK            (AT91C_PIO_PD8) //  ETM Trace Clock signal\n#define AT91C_PIO_PD9             (1 <<  9) // Pin Controlled by PD9\n#define AT91C_PD9_PCK2            (AT91C_PIO_PD9) //  PMC Programmable Clock 2\n#define AT91C_PD9_TPS0            (AT91C_PIO_PD9) //  ETM ARM9 pipeline status 0\n\n// *****************************************************************************\n//               PERIPHERAL ID DEFINITIONS FOR AT91RM9200\n// *****************************************************************************\n#define AT91C_ID_FIQ              ( 0) // Advanced Interrupt Controller (FIQ)\n#define AT91C_ID_SYS              ( 1) // System Peripheral\n#define AT91C_ID_PIOA             ( 2) // Parallel IO Controller A \n#define AT91C_ID_PIOB             ( 3) // Parallel IO Controller B\n#define AT91C_ID_PIOC             ( 4) // Parallel IO Controller C\n#define AT91C_ID_PIOD             ( 5) // Parallel IO Controller D\n#define AT91C_ID_US0              ( 6) // USART 0\n#define AT91C_ID_US1              ( 7) // USART 1\n#define AT91C_ID_US2              ( 8) // USART 2\n#define AT91C_ID_US3              ( 9) // USART 3\n#define AT91C_ID_MCI              (10) // Multimedia Card Interface\n#define AT91C_ID_UDP              (11) // USB Device Port\n#define AT91C_ID_TWI              (12) // Two-Wire Interface\n#define AT91C_ID_SPI              (13) // Serial Peripheral Interface\n#define AT91C_ID_SSC0             (14) // Serial Synchronous Controller 0\n#define AT91C_ID_SSC1             (15) // Serial Synchronous Controller 1\n#define AT91C_ID_SSC2             (16) // Serial Synchronous Controller 2\n#define AT91C_ID_TC0              (17) // Timer Counter 0\n#define AT91C_ID_TC1              (18) // Timer Counter 1\n#define AT91C_ID_TC2              (19) // Timer Counter 2\n#define AT91C_ID_TC3              (20) // Timer Counter 3\n#define AT91C_ID_TC4              (21) // Timer Counter 4\n#define AT91C_ID_TC5              (22) // Timer Counter 5\n#define AT91C_ID_UHP              (23) // USB Host port\n#define AT91C_ID_EMAC             (24) // Ethernet MAC\n#define AT91C_ID_IRQ0             (25) // Advanced Interrupt Controller (IRQ0)\n#define AT91C_ID_IRQ1             (26) // Advanced Interrupt Controller (IRQ1)\n#define AT91C_ID_IRQ2             (27) // Advanced Interrupt Controller (IRQ2)\n#define AT91C_ID_IRQ3             (28) // Advanced Interrupt Controller (IRQ3)\n#define AT91C_ID_IRQ4             (29) // Advanced Interrupt Controller (IRQ4)\n#define AT91C_ID_IRQ5             (30) // Advanced Interrupt Controller (IRQ5)\n#define AT91C_ID_IRQ6             (31) // Advanced Interrupt Controller (IRQ6)\n\n// *****************************************************************************\n//               BASE ADDRESS DEFINITIONS FOR AT91RM9200\n// *****************************************************************************\n#define AT91C_BASE_SYS            (0xFFFFF000) // (SYS) Base Address\n#define AT91C_BASE_MC             (0xFFFFFF00) // (MC) Base Address\n#define AT91C_BASE_RTC            (0xFFFFFE00) // (RTC) Base Address\n#define AT91C_BASE_ST             (0xFFFFFD00) // (ST) Base Address\n#define AT91C_BASE_PMC            (0xFFFFFC00) // (PMC) Base Address\n#define AT91C_BASE_CKGR           (0xFFFFFC20) // (CKGR) Base Address\n#define AT91C_BASE_PIOD           (0xFFFFFA00) // (PIOD) Base Address\n#define AT91C_BASE_PIOC           (0xFFFFF800) // (PIOC) Base Address\n#define AT91C_BASE_PIOB           (0xFFFFF600) // (PIOB) Base Address\n#define AT91C_BASE_PIOA           (0xFFFFF400) // (PIOA) Base Address\n#define AT91C_BASE_DBGU           (0xFFFFF200) // (DBGU) Base Address\n#define AT91C_BASE_PDC_DBGU       (0xFFFFF300) // (PDC_DBGU) Base Address\n#define AT91C_BASE_AIC            (0xFFFFF000) // (AIC) Base Address\n#define AT91C_BASE_PDC_SPI        (0xFFFE0100) // (PDC_SPI) Base Address\n#define AT91C_BASE_SPI            (0xFFFE0000) // (SPI) Base Address\n#define AT91C_BASE_PDC_SSC2       (0xFFFD8100) // (PDC_SSC2) Base Address\n#define AT91C_BASE_SSC2           (0xFFFD8000) // (SSC2) Base Address\n#define AT91C_BASE_PDC_SSC1       (0xFFFD4100) // (PDC_SSC1) Base Address\n#define AT91C_BASE_SSC1           (0xFFFD4000) // (SSC1) Base Address\n#define AT91C_BASE_PDC_SSC0       (0xFFFD0100) // (PDC_SSC0) Base Address\n#define AT91C_BASE_SSC0           (0xFFFD0000) // (SSC0) Base Address\n#define AT91C_BASE_PDC_US3        (0xFFFCC100) // (PDC_US3) Base Address\n#define AT91C_BASE_US3            (0xFFFCC000) // (US3) Base Address\n#define AT91C_BASE_PDC_US2        (0xFFFC8100) // (PDC_US2) Base Address\n#define AT91C_BASE_US2            (0xFFFC8000) // (US2) Base Address\n#define AT91C_BASE_PDC_US1        (0xFFFC4100) // (PDC_US1) Base Address\n#define AT91C_BASE_US1            (0xFFFC4000) // (US1) Base Address\n#define AT91C_BASE_PDC_US0        (0xFFFC0100) // (PDC_US0) Base Address\n#define AT91C_BASE_US0            (0xFFFC0000) // (US0) Base Address\n#define AT91C_BASE_TWI            (0xFFFB8000) // (TWI) Base Address\n#define AT91C_BASE_PDC_MCI        (0xFFFB4100) // (PDC_MCI) Base Address\n#define AT91C_BASE_MCI            (0xFFFB4000) // (MCI) Base Address\n#define AT91C_BASE_UDP            (0xFFFB0000) // (UDP) Base Address\n#define AT91C_BASE_TC5            (0xFFFA4080) // (TC5) Base Address\n#define AT91C_BASE_TC4            (0xFFFA4040) // (TC4) Base Address\n#define AT91C_BASE_TC3            (0xFFFA4000) // (TC3) Base Address\n#define AT91C_BASE_TCB1           (0xFFFA4080) // (TCB1) Base Address\n#define AT91C_BASE_TC2            (0xFFFA0080) // (TC2) Base Address\n#define AT91C_BASE_TC1            (0xFFFA0040) // (TC1) Base Address\n#define AT91C_BASE_TC0            (0xFFFA0000) // (TC0) Base Address\n#define AT91C_BASE_TCB0           (0xFFFA0000) // (TCB0) Base Address\n#define AT91C_BASE_UHP            (0x00300000) // (UHP) Base Address\n#define AT91C_BASE_EMAC           (0xFFFBC000) // (EMAC) Base Address\n#define AT91C_BASE_EBI            (0xFFFFFF60) // (EBI) Base Address\n#define AT91C_BASE_SMC2           (0xFFFFFF70) // (SMC2) Base Address\n#define AT91C_BASE_SDRC           (0xFFFFFF90) // (SDRC) Base Address\n#define AT91C_BASE_BFC            (0xFFFFFFC0) // (BFC) Base Address\n\n// *****************************************************************************\n//               MEMORY MAPPING DEFINITIONS FOR AT91RM9200\n// *****************************************************************************\n#define AT91C_ISRAM\t              (0x00200000) // Internal SRAM base address\n#define AT91C_ISRAM_SIZE\t         (0x00004000) // Internal SRAM size in byte (16 Kbyte)\n#define AT91C_IROM \t              (0x00100000) // Internal ROM base address\n#define AT91C_IROM_SIZE\t          (0x00020000) // Internal ROM size in byte (128 Kbyte)\n\n\n"
  },
  {
    "path": "target/linux/at91/image/dfboot/src/include/led.h",
    "content": "/*\n * (C) Copyright 2006\n * Atmel Nordic AB <www.atmel.com>\n * Ulf Samuelsson <ulf@atmel.com>\n *\n * See file CREDITS for list of people who contributed to this\n * project.\n *\n * This program is free software; you can redistribute it and/or\n * modify it under the terms of the GNU General Public License as\n * published by the Free Software Foundation; either version 2 of\n * the License, or (at your option) any later version.\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n * GNU General Public License for more details.\n *\n * You should have received a copy of the GNU General Public License\n * along with this program; if not, write to the Free Software\n * Foundation, Inc., 59 Temple Place, Suite 330, Boston,\n * MA 02111-1307 USA\n */\n \n #ifndef __LED_H\n#define __LED_H\n\n#ifndef\t__ASSEMBLY__\nextern void\tLED_init (void);\nextern void\tLED_set(unsigned int led);\nextern void\tred_LED_on(void);\nextern void\tred_LED_off(void);\nextern void\tgreen_LED_on(void);\nextern void\tgreen_LED_off(void);\nextern void\tyellow_LED_on(void);\nextern void\tyellow_LED_off(void);\nextern void\tLED_blink(unsigned int led);\n#else\n\t.extern LED_init\n\t.extern LED_set\n\t.extern LED_blink\n\t.extern red_LED_on\n\t.extern red_LED_off\n\t.extern yellow_LED_on\n\t.extern yellow_LED_off\n\t.extern green_LED_on\n\t.extern green_LED_off\n#endif\n#endif\n"
  },
  {
    "path": "target/linux/at91/image/dfboot/src/include/lib_AT91RM9200.h",
    "content": "//*----------------------------------------------------------------------------\n//*         ATMEL Microcontroller Software Support  -  ROUSSET  -\n//*----------------------------------------------------------------------------\n//* The software is delivered \"AS IS\" without warranty or condition of any\n//* kind, either express, implied or statutory. This includes without\n//* limitation any warranty or condition with respect to merchantability or\n//* fitness for any particular purpose, or against the infringements of\n//* intellectual property rights of others.\n//*----------------------------------------------------------------------------\n//* File Name           : lib_AT91RM9200.h\n//* Object              : AT91RM9200 inlined functions\n//* Generated           : AT91 SW Application Group  11/19/2003 (17:20:51)\n//*\n//* CVS Reference       : /lib_pdc.h/1.2/Tue Jul 02 12:29:40 2002//\n//* CVS Reference       : /lib_dbgu.h/1.1/Fri Jan 31 12:18:40 2003//\n//* CVS Reference       : /lib_rtc_1245d.h/1.1/Fri Jan 31 12:19:12 2003//\n//* CVS Reference       : /lib_ssc.h/1.4/Fri Jan 31 12:19:20 2003//\n//* CVS Reference       : /lib_spi_AT91RMxxxx.h/1.2/Fri Jan 31 12:19:31 2003//\n//* CVS Reference       : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003//\n//* CVS Reference       : /lib_pmc.h/1.3/Thu Nov 14 07:40:45 2002//\n//* CVS Reference       : /lib_pio.h/1.3/Fri Jan 31 12:18:56 2003//\n//* CVS Reference       : /lib_twi.h/1.2/Fri Jan 31 12:19:38 2003//\n//* CVS Reference       : /lib_usart.h/1.5/Thu Nov 21 16:01:53 2002//\n//* CVS Reference       : /lib_mci.h/1.2/Wed Nov 20 14:18:55 2002//\n//* CVS Reference       : /lib_aic.h/1.3/Fri Jul 12 07:46:11 2002//\n//* CVS Reference       : /lib_udp.h/1.3/Fri Jan 31 12:19:48 2003//\n//* CVS Reference       : /lib_st.h/1.4/Fri Jan 31 12:20:13 2003//\n//*----------------------------------------------------------------------------\n\n#ifndef lib_AT91RM9200_H\n#define lib_AT91RM9200_H\n\n/* *****************************************************************************\n                SOFTWARE API FOR PDC\n   ***************************************************************************** */\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_PDC_SetNextRx\n//* \\brief Set the next receive transfer descriptor\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_PDC_SetNextRx (\n\tAT91PS_PDC pPDC,     // \\arg pointer to a PDC controller\n\tchar *address,       // \\arg address to the next bloc to be received\n\tunsigned int bytes)  // \\arg number of bytes to be received\n{\n\tpPDC->PDC_RNPR = (unsigned int) address;\n\tpPDC->PDC_RNCR = bytes;\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_PDC_SetNextTx\n//* \\brief Set the next transmit transfer descriptor\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_PDC_SetNextTx (\n\tAT91PS_PDC pPDC,       // \\arg pointer to a PDC controller\n\tchar *address,         // \\arg address to the next bloc to be transmitted\n\tunsigned int bytes)    // \\arg number of bytes to be transmitted\n{\n\tpPDC->PDC_TNPR = (unsigned int) address;\n\tpPDC->PDC_TNCR = bytes;\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_PDC_SetRx\n//* \\brief Set the receive transfer descriptor\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_PDC_SetRx (\n\tAT91PS_PDC pPDC,       // \\arg pointer to a PDC controller\n\tchar *address,         // \\arg address to the next bloc to be received\n\tunsigned int bytes)    // \\arg number of bytes to be received\n{\n\tpPDC->PDC_RPR = (unsigned int) address;\n\tpPDC->PDC_RCR = bytes;\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_PDC_SetTx\n//* \\brief Set the transmit transfer descriptor\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_PDC_SetTx (\n\tAT91PS_PDC pPDC,       // \\arg pointer to a PDC controller\n\tchar *address,         // \\arg address to the next bloc to be transmitted\n\tunsigned int bytes)    // \\arg number of bytes to be transmitted\n{\n\tpPDC->PDC_TPR = (unsigned int) address;\n\tpPDC->PDC_TCR = bytes;\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_PDC_EnableTx\n//* \\brief Enable transmit\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_PDC_EnableTx (\n\tAT91PS_PDC pPDC )       // \\arg pointer to a PDC controller\n{\n\tpPDC->PDC_PTCR = AT91C_PDC_TXTEN;\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_PDC_EnableRx\n//* \\brief Enable receive\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_PDC_EnableRx (\n\tAT91PS_PDC pPDC )       // \\arg pointer to a PDC controller\n{\n\tpPDC->PDC_PTCR = AT91C_PDC_RXTEN;\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_PDC_DisableTx\n//* \\brief Disable transmit\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_PDC_DisableTx (\n\tAT91PS_PDC pPDC )       // \\arg pointer to a PDC controller\n{\n\tpPDC->PDC_PTCR = AT91C_PDC_TXTDIS;\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_PDC_DisableRx\n//* \\brief Disable receive\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_PDC_DisableRx (\n\tAT91PS_PDC pPDC )       // \\arg pointer to a PDC controller\n{\n\tpPDC->PDC_PTCR = AT91C_PDC_RXTDIS;\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_PDC_IsTxEmpty\n//* \\brief Test if the current transfer descriptor has been sent\n//*----------------------------------------------------------------------------\nstatic inline int AT91F_PDC_IsTxEmpty ( // \\return return 1 if transfer is complete\n\tAT91PS_PDC pPDC )       // \\arg pointer to a PDC controller\n{\n\treturn !(pPDC->PDC_TCR);\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_PDC_IsNextTxEmpty\n//* \\brief Test if the next transfer descriptor has been moved to the current td\n//*----------------------------------------------------------------------------\nstatic inline int AT91F_PDC_IsNextTxEmpty ( // \\return return 1 if transfer is complete\n\tAT91PS_PDC pPDC )       // \\arg pointer to a PDC controller\n{\n\treturn !(pPDC->PDC_TNCR);\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_PDC_IsRxEmpty\n//* \\brief Test if the current transfer descriptor has been filled\n//*----------------------------------------------------------------------------\nstatic inline int AT91F_PDC_IsRxEmpty ( // \\return return 1 if transfer is complete\n\tAT91PS_PDC pPDC )       // \\arg pointer to a PDC controller\n{\n\treturn !(pPDC->PDC_RCR);\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_PDC_IsNextRxEmpty\n//* \\brief Test if the next transfer descriptor has been moved to the current td\n//*----------------------------------------------------------------------------\nstatic inline int AT91F_PDC_IsNextRxEmpty ( // \\return return 1 if transfer is complete\n\tAT91PS_PDC pPDC )       // \\arg pointer to a PDC controller\n{\n\treturn !(pPDC->PDC_RNCR);\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_PDC_Open\n//* \\brief Open PDC: disable TX and RX reset transfer descriptors, re-enable RX and TX\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_PDC_Open (\n\tAT91PS_PDC pPDC)       // \\arg pointer to a PDC controller\n{\n    //* Disable the RX and TX PDC transfer requests\n\tAT91F_PDC_DisableRx(pPDC);\n\tAT91F_PDC_DisableTx(pPDC);\n\n\t//* Reset all Counter register Next buffer first\n\tAT91F_PDC_SetNextTx(pPDC, (char *) 0, 0);\n\tAT91F_PDC_SetNextRx(pPDC, (char *) 0, 0);\n\tAT91F_PDC_SetTx(pPDC, (char *) 0, 0);\n\tAT91F_PDC_SetRx(pPDC, (char *) 0, 0);\n\n    //* Enable the RX and TX PDC transfer requests\n\tAT91F_PDC_EnableRx(pPDC);\n\tAT91F_PDC_EnableTx(pPDC);\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_PDC_Close\n//* \\brief Close PDC: disable TX and RX reset transfer descriptors\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_PDC_Close (\n\tAT91PS_PDC pPDC)       // \\arg pointer to a PDC controller\n{\n    //* Disable the RX and TX PDC transfer requests\n\tAT91F_PDC_DisableRx(pPDC);\n\tAT91F_PDC_DisableTx(pPDC);\n\n\t//* Reset all Counter register Next buffer first\n\tAT91F_PDC_SetNextTx(pPDC, (char *) 0, 0);\n\tAT91F_PDC_SetNextRx(pPDC, (char *) 0, 0);\n\tAT91F_PDC_SetTx(pPDC, (char *) 0, 0);\n\tAT91F_PDC_SetRx(pPDC, (char *) 0, 0);\n\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_PDC_SendFrame\n//* \\brief Close PDC: disable TX and RX reset transfer descriptors\n//*----------------------------------------------------------------------------\nstatic inline unsigned int AT91F_PDC_SendFrame(\n\tAT91PS_PDC pPDC,\n\tchar *pBuffer,\n\tunsigned int szBuffer,\n\tchar *pNextBuffer,\n\tunsigned int szNextBuffer )\n{\n\tif (AT91F_PDC_IsTxEmpty(pPDC)) {\n\t\t//* Buffer and next buffer can be initialized\n\t\tAT91F_PDC_SetTx(pPDC, pBuffer, szBuffer);\n\t\tAT91F_PDC_SetNextTx(pPDC, pNextBuffer, szNextBuffer);\n\t\treturn 2;\n\t}\n\telse if (AT91F_PDC_IsNextTxEmpty(pPDC)) {\n\t\t//* Only one buffer can be initialized\n\t\tAT91F_PDC_SetNextTx(pPDC, pBuffer, szBuffer);\n\t\treturn 1;\n\t}\n\telse {\n\t\t//* All buffer are in use...\n\t\treturn 0;\n\t}\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_PDC_ReceiveFrame\n//* \\brief Close PDC: disable TX and RX reset transfer descriptors\n//*----------------------------------------------------------------------------\nstatic inline unsigned int AT91F_PDC_ReceiveFrame (\n\tAT91PS_PDC pPDC,\n\tchar *pBuffer,\n\tunsigned int szBuffer,\n\tchar *pNextBuffer,\n\tunsigned int szNextBuffer )\n{\n\tif (AT91F_PDC_IsRxEmpty(pPDC)) {\n\t\t//* Buffer and next buffer can be initialized\n\t\tAT91F_PDC_SetRx(pPDC, pBuffer, szBuffer);\n\t\tAT91F_PDC_SetNextRx(pPDC, pNextBuffer, szNextBuffer);\n\t\treturn 2;\n\t}\n\telse if (AT91F_PDC_IsNextRxEmpty(pPDC)) {\n\t\t//* Only one buffer can be initialized\n\t\tAT91F_PDC_SetNextRx(pPDC, pBuffer, szBuffer);\n\t\treturn 1;\n\t}\n\telse {\n\t\t//* All buffer are in use...\n\t\treturn 0;\n\t}\n}\n/* *****************************************************************************\n                SOFTWARE API FOR DBGU\n   ***************************************************************************** */\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_DBGU_InterruptEnable\n//* \\brief Enable DBGU Interrupt\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_DBGU_InterruptEnable(\n        AT91PS_DBGU pDbgu,   // \\arg  pointer to a DBGU controller\n        unsigned int flag) // \\arg  dbgu interrupt to be enabled\n{\n        pDbgu->DBGU_IER = flag;\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_DBGU_InterruptDisable\n//* \\brief Disable DBGU Interrupt\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_DBGU_InterruptDisable(\n        AT91PS_DBGU pDbgu,   // \\arg  pointer to a DBGU controller\n        unsigned int flag) // \\arg  dbgu interrupt to be disabled\n{\n        pDbgu->DBGU_IDR = flag;\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_DBGU_GetInterruptMaskStatus\n//* \\brief Return DBGU Interrupt Mask Status\n//*----------------------------------------------------------------------------\nstatic inline unsigned int AT91F_DBGU_GetInterruptMaskStatus( // \\return DBGU Interrupt Mask Status\n        AT91PS_DBGU pDbgu) // \\arg  pointer to a DBGU controller\n{\n        return pDbgu->DBGU_IMR;\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_DBGU_IsInterruptMasked\n//* \\brief Test if DBGU Interrupt is Masked \n//*----------------------------------------------------------------------------\nstatic inline int AT91F_DBGU_IsInterruptMasked(\n        AT91PS_DBGU pDbgu,   // \\arg  pointer to a DBGU controller\n        unsigned int flag) // \\arg  flag to be tested\n{\n        return (AT91F_DBGU_GetInterruptMaskStatus(pDbgu) & flag);\n}\n\n/* *****************************************************************************\n                SOFTWARE API FOR RTC\n   ***************************************************************************** */\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_RTC_InterruptEnable\n//* \\brief Enable RTC Interrupt\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_RTC_InterruptEnable(\n        AT91PS_RTC pRtc,   // \\arg  pointer to a RTC controller\n        unsigned int flag) // \\arg  RTC interrupt to be enabled\n{\n        pRtc->RTC_IER = flag;\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_RTC_InterruptDisable\n//* \\brief Disable RTC Interrupt\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_RTC_InterruptDisable(\n        AT91PS_RTC pRtc,   // \\arg  pointer to a RTC controller\n        unsigned int flag) // \\arg  RTC interrupt to be disabled\n{\n        pRtc->RTC_IDR = flag;\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_RTC_GetInterruptMaskStatus\n//* \\brief Return RTC Interrupt Mask Status\n//*----------------------------------------------------------------------------\nstatic inline unsigned int AT91F_RTC_GetInterruptMaskStatus( // \\return RTC Interrupt Mask Status\n        AT91PS_RTC pRtc) // \\arg  pointer to a RTC controller\n{\n        return pRtc->RTC_IMR;\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_RTC_IsInterruptMasked\n//* \\brief Test if RTC Interrupt is Masked \n//*----------------------------------------------------------------------------\nstatic inline int AT91F_RTC_IsInterruptMasked(\n        AT91PS_RTC pRtc,   // \\arg  pointer to a RTC controller\n        unsigned int flag) // \\arg  flag to be tested\n{\n        return (AT91F_RTC_GetInterruptMaskStatus(pRtc) & flag);\n}\n\n/* *****************************************************************************\n                SOFTWARE API FOR SSC\n   ***************************************************************************** */\n//* Define the standard I2S mode configuration\n\n//* Configuration to set in the SSC Transmit Clock Mode Register\n//* Parameters :  nb_bit_by_slot : 8, 16 or 32 bits\n//* \t\t\t  nb_slot_by_frame : number of channels\n#define AT91C_I2S_ASY_MASTER_TX_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\\\n\t\t\t\t\t\t\t\t\t   AT91C_SSC_CKS_DIV   +\\\n                            \t\t   AT91C_SSC_CKO_CONTINOUS      +\\\n                            \t\t   AT91C_SSC_CKG_NONE    +\\\n                                       AT91C_SSC_START_FALL_RF +\\\n                           \t\t\t   AT91C_SSC_STTOUT  +\\\n                            \t\t   ((1<<16) & AT91C_SSC_STTDLY) +\\\n                            \t\t   ((((nb_bit_by_slot*nb_slot_by_frame)/2)-1) <<24))\n\n\n//* Configuration to set in the SSC Transmit Frame Mode Register\n//* Parameters : nb_bit_by_slot : 8, 16 or 32 bits\n//* \t\t\t nb_slot_by_frame : number of channels\n#define AT91C_I2S_ASY_TX_FRAME_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\\\n\t\t\t\t\t\t\t\t\t(nb_bit_by_slot-1)  +\\\n                            \t\tAT91C_SSC_MSBF   +\\\n                            \t\t(((nb_slot_by_frame-1)<<8) & AT91C_SSC_DATNB)  +\\\n                            \t\t(((nb_bit_by_slot-1)<<16) & AT91C_SSC_FSLEN) +\\\n                            \t\tAT91C_SSC_FSOS_NEGATIVE)\n\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_SSC_SetBaudrate\n//* \\brief Set the baudrate according to the CPU clock\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_SSC_SetBaudrate (\n        AT91PS_SSC pSSC,        // \\arg pointer to a SSC controller\n        unsigned int mainClock, // \\arg peripheral clock\n        unsigned int speed)     // \\arg SSC baudrate\n{\n        unsigned int baud_value;\n        //* Define the baud rate divisor register\n        if (speed == 0)\n           baud_value = 0;\n        else\n        {\n           baud_value = (unsigned int) (mainClock * 10)/(2*speed);\n           if ((baud_value % 10) >= 5)\n                  baud_value = (baud_value / 10) + 1;\n           else\n                  baud_value /= 10;\n        }\n\n        pSSC->SSC_CMR = baud_value;\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_SSC_Configure\n//* \\brief Configure SSC\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_SSC_Configure (\n             AT91PS_SSC pSSC,          // \\arg pointer to a SSC controller\n             unsigned int syst_clock,  // \\arg System Clock Frequency\n             unsigned int baud_rate,   // \\arg Expected Baud Rate Frequency\n             unsigned int clock_rx,    // \\arg Receiver Clock Parameters\n             unsigned int mode_rx,     // \\arg mode Register to be programmed\n             unsigned int clock_tx,    // \\arg Transmitter Clock Parameters\n             unsigned int mode_tx)     // \\arg mode Register to be programmed\n{\n    //* Disable interrupts\n\tpSSC->SSC_IDR = (unsigned int) -1;\n\n    //* Reset receiver and transmitter\n\tpSSC->SSC_CR = AT91C_SSC_SWRST | AT91C_SSC_RXDIS | AT91C_SSC_TXDIS ;\n\n    //* Define the Clock Mode Register\n\tAT91F_SSC_SetBaudrate(pSSC, syst_clock, baud_rate);\n\n     //* Write the Receive Clock Mode Register\n\tpSSC->SSC_RCMR =  clock_rx;\n\n     //* Write the Transmit Clock Mode Register\n\tpSSC->SSC_TCMR =  clock_tx;\n\n     //* Write the Receive Frame Mode Register\n\tpSSC->SSC_RFMR =  mode_rx;\n\n     //* Write the Transmit Frame Mode Register\n\tpSSC->SSC_TFMR =  mode_tx;\n\n    //* Clear Transmit and Receive Counters\n\tAT91F_PDC_Open((AT91PS_PDC) &(pSSC->SSC_RPR));\n\n\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_SSC_EnableRx\n//* \\brief Enable receiving datas\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_SSC_EnableRx (\n\tAT91PS_SSC pSSC)     // \\arg pointer to a SSC controller\n{\n    //* Enable receiver\n    pSSC->SSC_CR = AT91C_SSC_RXEN;\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_SSC_DisableRx\n//* \\brief Disable receiving datas\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_SSC_DisableRx (\n\tAT91PS_SSC pSSC)     // \\arg pointer to a SSC controller\n{\n    //* Disable receiver\n    pSSC->SSC_CR = AT91C_SSC_RXDIS;\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_SSC_EnableTx\n//* \\brief Enable sending datas\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_SSC_EnableTx (\n\tAT91PS_SSC pSSC)     // \\arg pointer to a SSC controller\n{\n    //* Enable  transmitter\n    pSSC->SSC_CR = AT91C_SSC_TXEN;\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_SSC_DisableTx\n//* \\brief Disable sending datas\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_SSC_DisableTx (\n\tAT91PS_SSC pSSC)     // \\arg pointer to a SSC controller\n{\n    //* Disable  transmitter\n    pSSC->SSC_CR = AT91C_SSC_TXDIS;\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_SSC_EnableIt\n//* \\brief Enable SSC IT\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_SSC_EnableIt (\n\tAT91PS_SSC pSSC, // \\arg pointer to a SSC controller\n\tunsigned int flag)   // \\arg IT to be enabled\n{\n\t//* Write to the IER register\n\tpSSC->SSC_IER = flag;\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_SSC_DisableIt\n//* \\brief Disable SSC IT\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_SSC_DisableIt (\n\tAT91PS_SSC pSSC, // \\arg pointer to a SSC controller\n\tunsigned int flag)   // \\arg IT to be disabled\n{\n\t//* Write to the IDR register\n\tpSSC->SSC_IDR = flag;\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_SSC_ReceiveFrame\n//* \\brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy\n//*----------------------------------------------------------------------------\nstatic inline unsigned int AT91F_SSC_ReceiveFrame (\n\tAT91PS_SSC pSSC,\n\tchar *pBuffer,\n\tunsigned int szBuffer,\n\tchar *pNextBuffer,\n\tunsigned int szNextBuffer )\n{\n\treturn AT91F_PDC_ReceiveFrame(\n\t\t(AT91PS_PDC) &(pSSC->SSC_RPR),\n\t\tpBuffer,\n\t\tszBuffer,\n\t\tpNextBuffer,\n\t\tszNextBuffer);\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_SSC_SendFrame\n//* \\brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy\n//*----------------------------------------------------------------------------\nstatic inline unsigned int AT91F_SSC_SendFrame(\n\tAT91PS_SSC pSSC,\n\tchar *pBuffer,\n\tunsigned int szBuffer,\n\tchar *pNextBuffer,\n\tunsigned int szNextBuffer )\n{\n\treturn AT91F_PDC_SendFrame(\n\t\t(AT91PS_PDC) &(pSSC->SSC_RPR),\n\t\tpBuffer,\n\t\tszBuffer,\n\t\tpNextBuffer,\n\t\tszNextBuffer);\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_SSC_GetInterruptMaskStatus\n//* \\brief Return SSC Interrupt Mask Status\n//*----------------------------------------------------------------------------\nstatic inline unsigned int AT91F_SSC_GetInterruptMaskStatus( // \\return SSC Interrupt Mask Status\n        AT91PS_SSC pSsc) // \\arg  pointer to a SSC controller\n{\n        return pSsc->SSC_IMR;\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_SSC_IsInterruptMasked\n//* \\brief Test if SSC Interrupt is Masked \n//*----------------------------------------------------------------------------\nstatic inline int AT91F_SSC_IsInterruptMasked(\n        AT91PS_SSC pSsc,   // \\arg  pointer to a SSC controller\n        unsigned int flag) // \\arg  flag to be tested\n{\n        return (AT91F_SSC_GetInterruptMaskStatus(pSsc) & flag);\n}\n\n/* *****************************************************************************\n                SOFTWARE API FOR SPI\n   ***************************************************************************** */\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_SPI_Open\n//* \\brief Open a SPI Port\n//*----------------------------------------------------------------------------\nstatic inline unsigned int AT91F_SPI_Open (\n        const unsigned int null)  // \\arg\n{\n        /* NOT DEFINED AT THIS MOMENT */\n        return ( 0 );\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_SPI_CfgCs\n//* \\brief Configure SPI chip select register\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_SPI_CfgCs (\n\tint cs,     // SPI cs number (0 to 3)\n \tint val)   //  chip select register\n{\n\t//* Write to the CSR register\n\t*(AT91C_SPI_CSR + cs) = val;\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_SPI_EnableIt\n//* \\brief Enable SPI interrupt\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_SPI_EnableIt (\n\tAT91PS_SPI pSPI,     // pointer to a SPI controller\n\tunsigned int flag)   // IT to be enabled\n{\n\t//* Write to the IER register\n\tpSPI->SPI_IER = flag;\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_SPI_DisableIt\n//* \\brief Disable SPI interrupt\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_SPI_DisableIt (\n\tAT91PS_SPI pSPI, // pointer to a SPI controller\n\tunsigned int flag) // IT to be disabled\n{\n\t//* Write to the IDR register\n\tpSPI->SPI_IDR = flag;\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_SPI_Reset\n//* \\brief Reset the SPI controller\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_SPI_Reset (\n\tAT91PS_SPI pSPI // pointer to a SPI controller\n\t)\n{\n\t//* Write to the CR register\n\tpSPI->SPI_CR = AT91C_SPI_SWRST;\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_SPI_Enable\n//* \\brief Enable the SPI controller\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_SPI_Enable (\n\tAT91PS_SPI pSPI // pointer to a SPI controller\n\t)\n{\n\t//* Write to the CR register\n\tpSPI->SPI_CR = AT91C_SPI_SPIEN;\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_SPI_Disable\n//* \\brief Disable the SPI controller\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_SPI_Disable (\n\tAT91PS_SPI pSPI // pointer to a SPI controller\n\t)\n{\n\t//* Write to the CR register\n\tpSPI->SPI_CR = AT91C_SPI_SPIDIS;\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_SPI_CfgMode\n//* \\brief Enable the SPI controller\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_SPI_CfgMode (\n\tAT91PS_SPI pSPI, // pointer to a SPI controller\n\tint mode)        // mode register \n{\n\t//* Write to the MR register\n\tpSPI->SPI_MR = mode;\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_SPI_CfgPCS\n//* \\brief Switch to the correct PCS of SPI Mode Register : Fixed Peripheral Selected\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_SPI_CfgPCS (\n\tAT91PS_SPI pSPI, // pointer to a SPI controller\n\tchar PCS_Device) // PCS of the Device\n{\t\n \t//* Write to the MR register\n\tpSPI->SPI_MR &= 0xFFF0FFFF;\n\tpSPI->SPI_MR |= ( (PCS_Device<<16) & AT91C_SPI_PCS );\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_SPI_ReceiveFrame\n//* \\brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy\n//*----------------------------------------------------------------------------\nstatic inline unsigned int AT91F_SPI_ReceiveFrame (\n\tAT91PS_SPI pSPI,\n\tchar *pBuffer,\n\tunsigned int szBuffer,\n\tchar *pNextBuffer,\n\tunsigned int szNextBuffer )\n{\n\treturn AT91F_PDC_ReceiveFrame(\n\t\t(AT91PS_PDC) &(pSPI->SPI_RPR),\n\t\tpBuffer,\n\t\tszBuffer,\n\t\tpNextBuffer,\n\t\tszNextBuffer);\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_SPI_SendFrame\n//* \\brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is bSPIy\n//*----------------------------------------------------------------------------\nstatic inline unsigned int AT91F_SPI_SendFrame(\n\tAT91PS_SPI pSPI,\n\tchar *pBuffer,\n\tunsigned int szBuffer,\n\tchar *pNextBuffer,\n\tunsigned int szNextBuffer )\n{\n\treturn AT91F_PDC_SendFrame(\n\t\t(AT91PS_PDC) &(pSPI->SPI_RPR),\n\t\tpBuffer,\n\t\tszBuffer,\n\t\tpNextBuffer,\n\t\tszNextBuffer);\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_SPI_Close\n//* \\brief Close SPI: disable IT disable transfert, close PDC\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_SPI_Close (\n\tAT91PS_SPI pSPI)     // \\arg pointer to a SPI controller\n{\n    //* Reset all the Chip Select register\n    pSPI->SPI_CSR[0] = 0 ;\n    pSPI->SPI_CSR[1] = 0 ;\n    pSPI->SPI_CSR[2] = 0 ;\n    pSPI->SPI_CSR[3] = 0 ;\n\n    //* Reset the SPI mode\n    pSPI->SPI_MR = 0  ;\n\n    //* Disable all interrupts\n    pSPI->SPI_IDR = 0xFFFFFFFF ;\n\n    //* Abort the Peripheral Data Transfers\n    AT91F_PDC_Close((AT91PS_PDC) &(pSPI->SPI_RPR));\n\n    //* Disable receiver and transmitter and stop any activity immediately\n    pSPI->SPI_CR = AT91C_SPI_SPIDIS;\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_SPI_PutChar\n//* \\brief Send a character,does not check if ready to send\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_SPI_PutChar (\n\tAT91PS_SPI pSPI,\n\tunsigned int character,\n             unsigned int cs_number )\n{\n    unsigned int value_for_cs;\n    value_for_cs = (~(1 << cs_number)) & 0xF;  //Place a zero among a 4 ONEs number\n    pSPI->SPI_TDR = (character & 0xFFFF) | (value_for_cs << 16);\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_SPI_GetChar\n//* \\brief Receive a character,does not check if a character is available\n//*----------------------------------------------------------------------------\nstatic inline int AT91F_SPI_GetChar (\n\tconst AT91PS_SPI pSPI)\n{\n    return((pSPI->SPI_RDR) & 0xFFFF);\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_SPI_GetInterruptMaskStatus\n//* \\brief Return SPI Interrupt Mask Status\n//*----------------------------------------------------------------------------\nstatic inline unsigned int AT91F_SPI_GetInterruptMaskStatus( // \\return SPI Interrupt Mask Status\n        AT91PS_SPI pSpi) // \\arg  pointer to a SPI controller\n{\n        return pSpi->SPI_IMR;\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_SPI_IsInterruptMasked\n//* \\brief Test if SPI Interrupt is Masked \n//*----------------------------------------------------------------------------\nstatic inline int AT91F_SPI_IsInterruptMasked(\n        AT91PS_SPI pSpi,   // \\arg  pointer to a SPI controller\n        unsigned int flag) // \\arg  flag to be tested\n{\n        return (AT91F_SPI_GetInterruptMaskStatus(pSpi) & flag);\n}\n\n/* *****************************************************************************\n                SOFTWARE API FOR TC\n   ***************************************************************************** */\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_TC_InterruptEnable\n//* \\brief Enable TC Interrupt\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_TC_InterruptEnable(\n        AT91PS_TC pTc,   // \\arg  pointer to a TC controller\n        unsigned int flag) // \\arg  TC interrupt to be enabled\n{\n        pTc->TC_IER = flag;\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_TC_InterruptDisable\n//* \\brief Disable TC Interrupt\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_TC_InterruptDisable(\n        AT91PS_TC pTc,   // \\arg  pointer to a TC controller\n        unsigned int flag) // \\arg  TC interrupt to be disabled\n{\n        pTc->TC_IDR = flag;\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_TC_GetInterruptMaskStatus\n//* \\brief Return TC Interrupt Mask Status\n//*----------------------------------------------------------------------------\nstatic inline unsigned int AT91F_TC_GetInterruptMaskStatus( // \\return TC Interrupt Mask Status\n        AT91PS_TC pTc) // \\arg  pointer to a TC controller\n{\n        return pTc->TC_IMR;\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_TC_IsInterruptMasked\n//* \\brief Test if TC Interrupt is Masked \n//*----------------------------------------------------------------------------\nstatic inline int AT91F_TC_IsInterruptMasked(\n        AT91PS_TC pTc,   // \\arg  pointer to a TC controller\n        unsigned int flag) // \\arg  flag to be tested\n{\n        return (AT91F_TC_GetInterruptMaskStatus(pTc) & flag);\n}\n\n/* *****************************************************************************\n                SOFTWARE API FOR PMC\n   ***************************************************************************** */\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_CKGR_GetMainClock\n//* \\brief Return Main clock in Hz\n//*----------------------------------------------------------------------------\nstatic inline unsigned int AT91F_CKGR_GetMainClock (\n\tAT91PS_CKGR pCKGR, // \\arg pointer to CKGR controller\n\tunsigned int slowClock)  // \\arg slowClock in Hz\n{\n\treturn ((pCKGR->CKGR_MCFR  & AT91C_CKGR_MAINF) * slowClock) >> 4;\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_PMC_GetProcessorClock\n//* \\brief Return processor clock in Hz (for AT91RM3400 and AT91RM9200)\n//*----------------------------------------------------------------------------\nstatic inline unsigned int AT91F_PMC_GetProcessorClock (\n\tAT91PS_PMC pPMC, // \\arg pointer to PMC controller\n\tAT91PS_CKGR pCKGR, // \\arg pointer to CKGR controller\n\tunsigned int slowClock)  // \\arg slowClock in Hz\n{\n\tunsigned int reg = pPMC->PMC_MCKR;\n\tunsigned int prescaler = (1 << ((reg & AT91C_PMC_PRES) >> 2));\n\tunsigned int pllDivider, pllMultiplier;\n\n\tswitch (reg & AT91C_PMC_CSS) {\n\t\tcase AT91C_PMC_CSS_SLOW_CLK: // Slow clock selected\n\t\t\treturn slowClock / prescaler;\n\t\tcase AT91C_PMC_CSS_MAIN_CLK: // Main clock is selected\n\t\t\treturn AT91F_CKGR_GetMainClock(pCKGR, slowClock) / prescaler;\n\t\tcase AT91C_PMC_CSS_PLLA_CLK: // PLLA clock is selected\n\t\t\treg = pCKGR->CKGR_PLLAR;\n\t\t\tpllDivider    = (reg  & AT91C_CKGR_DIVA);\n\t\t\tpllMultiplier = ((reg  & AT91C_CKGR_MULA) >> 16) + 1;\n\t\t\tif (reg & AT91C_CKGR_SRCA) // Source is Main clock\n\t\t\t\treturn AT91F_CKGR_GetMainClock(pCKGR, slowClock) / pllDivider * pllMultiplier / prescaler;\n\t\t\telse                       // Source is Slow clock\n\t\t\t\treturn slowClock / pllDivider * pllMultiplier / prescaler;\n\t\tcase AT91C_PMC_CSS_PLLB_CLK: // PLLB clock is selected\n\t\t\treg = pCKGR->CKGR_PLLBR;\n\t\t\tpllDivider    = (reg  & AT91C_CKGR_DIVB);\n\t\t\tpllMultiplier = ((reg  & AT91C_CKGR_MULB) >> 16) + 1;\n\t\t\treturn AT91F_CKGR_GetMainClock(pCKGR, slowClock) / pllDivider * pllMultiplier / prescaler;\n\t}\n\treturn 0;\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_PMC_GetMasterClock\n//* \\brief Return master clock in Hz (just for AT91RM9200)\n//*----------------------------------------------------------------------------\nstatic inline unsigned int AT91F_PMC_GetMasterClock (\n\tAT91PS_PMC pPMC, // \\arg pointer to PMC controller\n\tAT91PS_CKGR pCKGR, // \\arg pointer to CKGR controller\n\tunsigned int slowClock)  // \\arg slowClock in Hz\n{\n\treturn AT91F_PMC_GetProcessorClock(pPMC, pCKGR, slowClock) /\n\t\t(((pPMC->PMC_MCKR & AT91C_PMC_MDIV) >> 8)+1);\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_PMC_EnablePeriphClock\n//* \\brief Enable peripheral clock\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_PMC_EnablePeriphClock (\n\tAT91PS_PMC pPMC, // \\arg pointer to PMC controller\n\tunsigned int periphIds)  // \\arg IDs of peripherals to enable\n{\n\tpPMC->PMC_PCER = periphIds;\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_PMC_DisablePeriphClock\n//* \\brief Enable peripheral clock\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_PMC_DisablePeriphClock (\n\tAT91PS_PMC pPMC, // \\arg pointer to PMC controller\n\tunsigned int periphIds)  // \\arg IDs of peripherals to enable\n{\n\tpPMC->PMC_PCDR = periphIds;\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_PMC_EnablePCK\n//* \\brief Enable peripheral clock\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_PMC_EnablePCK (\n\tAT91PS_PMC pPMC, // \\arg pointer to PMC controller\n\tunsigned int pck,  // \\arg Peripheral clock identifier 0 .. 7\n\tunsigned int ccs,  // \\arg clock selection: AT91C_PMC_CSS_SLOW_CLK, AT91C_PMC_CSS_MAIN_CLK, AT91C_PMC_CSS_PLLA_CLK, AT91C_PMC_CSS_PLLB_CLK\n\tunsigned int pres) // \\arg Programmable clock prescalar AT91C_PMC_PRES_CLK, AT91C_PMC_PRES_CLK_2, ..., AT91C_PMC_PRES_CLK_64\n{\n\tpPMC->PMC_PCKR[pck] = ccs | pres;\n\tpPMC->PMC_SCER = (1 << pck) << 8;\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_PMC_DisablePCK\n//* \\brief Enable peripheral clock\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_PMC_DisablePCK (\n\tAT91PS_PMC pPMC, // \\arg pointer to PMC controller\n\tunsigned int pck)  // \\arg Peripheral clock identifier 0 .. 7\n{\n\tpPMC->PMC_SCDR = (1 << pck) << 8;\n}\n\n/* *****************************************************************************\n                SOFTWARE API FOR PIO\n   ***************************************************************************** */\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_PIO_CfgPeriph\n//* \\brief Enable pins to be drived by peripheral\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_PIO_CfgPeriph(\n\tAT91PS_PIO pPio,             // \\arg pointer to a PIO controller\n\tunsigned int periphAEnable,  // \\arg PERIPH A to enable\n\tunsigned int periphBEnable)  // \\arg PERIPH B to enable\n\n{\n\tpPio->PIO_ASR = periphAEnable;\n\tpPio->PIO_BSR = periphBEnable;\n\tpPio->PIO_PDR = (periphAEnable | periphBEnable); // Set in Periph mode\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_PIO_CfgOutput\n//* \\brief Enable PIO in output mode\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_PIO_CfgOutput(\n\tAT91PS_PIO pPio,             // \\arg pointer to a PIO controller\n\tunsigned int pioEnable)      // \\arg PIO to be enabled\n{\n\tpPio->PIO_PER = pioEnable; // Set in PIO mode\n\tpPio->PIO_OER = pioEnable; // Configure in Output\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_PIO_CfgInput\n//* \\brief Enable PIO in input mode\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_PIO_CfgInput(\n\tAT91PS_PIO pPio,             // \\arg pointer to a PIO controller\n\tunsigned int inputEnable)      // \\arg PIO to be enabled\n{\n\t// Disable output\n\tpPio->PIO_ODR  = inputEnable;\n\tpPio->PIO_PER  = inputEnable;\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_PIO_CfgOpendrain\n//* \\brief Configure PIO in open drain\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_PIO_CfgOpendrain(\n\tAT91PS_PIO pPio,             // \\arg pointer to a PIO controller\n\tunsigned int multiDrvEnable) // \\arg pio to be configured in open drain\n{\n\t// Configure the multi-drive option\n\tpPio->PIO_MDDR = ~multiDrvEnable;\n\tpPio->PIO_MDER = multiDrvEnable;\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_PIO_CfgPullup\n//* \\brief Enable pullup on PIO\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_PIO_CfgPullup(\n\tAT91PS_PIO pPio,             // \\arg pointer to a PIO controller\n\tunsigned int pullupEnable)   // \\arg enable pullup on PIO\n{\n\t\t// Connect or not Pullup\n\tpPio->PIO_PPUDR = ~pullupEnable;\n\tpPio->PIO_PPUER = pullupEnable;\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_PIO_CfgDirectDrive\n//* \\brief Enable direct drive on PIO\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_PIO_CfgDirectDrive(\n\tAT91PS_PIO pPio,             // \\arg pointer to a PIO controller\n\tunsigned int directDrive)    // \\arg PIO to be configured with direct drive\n\n{\n\t// Configure the Direct Drive\n\tpPio->PIO_OWDR  = ~directDrive;\n\tpPio->PIO_OWER  = directDrive;\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_PIO_CfgInputFilter\n//* \\brief Enable input filter on input PIO\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_PIO_CfgInputFilter(\n\tAT91PS_PIO pPio,             // \\arg pointer to a PIO controller\n\tunsigned int inputFilter)    // \\arg PIO to be configured with input filter\n\n{\n\t// Configure the Direct Drive\n\tpPio->PIO_IFDR  = ~inputFilter;\n\tpPio->PIO_IFER  = inputFilter;\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_PIO_GetInput\n//* \\brief Return PIO input value\n//*----------------------------------------------------------------------------\nstatic inline unsigned int AT91F_PIO_GetInput( // \\return PIO input\n\tAT91PS_PIO pPio) // \\arg  pointer to a PIO controller\n{\n\treturn pPio->PIO_PDSR;\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_PIO_IsInputSet\n//* \\brief Test if PIO is input flag is active\n//*----------------------------------------------------------------------------\nstatic inline int AT91F_PIO_IsInputSet(\n\tAT91PS_PIO pPio,   // \\arg  pointer to a PIO controller\n\tunsigned int flag) // \\arg  flag to be tested\n{\n\treturn (AT91F_PIO_GetInput(pPio) & flag);\n}\n\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_PIO_SetOutput\n//* \\brief Set to 1 output PIO\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_PIO_SetOutput(\n\tAT91PS_PIO pPio,   // \\arg  pointer to a PIO controller\n\tunsigned int flag) // \\arg  output to be set\n{\n\tpPio->PIO_SODR = flag;\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_PIO_ClearOutput\n//* \\brief Set to 0 output PIO\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_PIO_ClearOutput(\n\tAT91PS_PIO pPio,   // \\arg  pointer to a PIO controller\n\tunsigned int flag) // \\arg  output to be cleared\n{\n\tpPio->PIO_CODR = flag;\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_PIO_ForceOutput\n//* \\brief Force output when Direct drive option is enabled\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_PIO_ForceOutput(\n\tAT91PS_PIO pPio,   // \\arg  pointer to a PIO controller\n\tunsigned int flag) // \\arg  output to be forced\n{\n\tpPio->PIO_ODSR = flag;\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_PIO_Enable\n//* \\brief Enable PIO\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_PIO_Enable(\n        AT91PS_PIO pPio,   // \\arg  pointer to a PIO controller\n        unsigned int flag) // \\arg  pio to be enabled \n{\n        pPio->PIO_PER = flag;\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_PIO_Disable\n//* \\brief Disable PIO\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_PIO_Disable(\n        AT91PS_PIO pPio,   // \\arg  pointer to a PIO controller\n        unsigned int flag) // \\arg  pio to be disabled \n{\n        pPio->PIO_PDR = flag;\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_PIO_GetStatus\n//* \\brief Return PIO Status\n//*----------------------------------------------------------------------------\nstatic inline unsigned int AT91F_PIO_GetStatus( // \\return PIO Status\n        AT91PS_PIO pPio) // \\arg  pointer to a PIO controller\n{\n        return pPio->PIO_PSR;\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_PIO_IsSet\n//* \\brief Test if PIO is Set\n//*----------------------------------------------------------------------------\nstatic inline int AT91F_PIO_IsSet(\n        AT91PS_PIO pPio,   // \\arg  pointer to a PIO controller\n        unsigned int flag) // \\arg  flag to be tested\n{\n        return (AT91F_PIO_GetStatus(pPio) & flag);\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_PIO_OutputEnable\n//* \\brief Output Enable PIO\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_PIO_OutputEnable(\n        AT91PS_PIO pPio,   // \\arg  pointer to a PIO controller\n        unsigned int flag) // \\arg  pio output to be enabled\n{\n        pPio->PIO_OER = flag;\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_PIO_OutputDisable\n//* \\brief Output Enable PIO\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_PIO_OutputDisable(\n        AT91PS_PIO pPio,   // \\arg  pointer to a PIO controller\n        unsigned int flag) // \\arg  pio output to be disabled\n{\n        pPio->PIO_ODR = flag;\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_PIO_GetOutputStatus\n//* \\brief Return PIO Output Status\n//*----------------------------------------------------------------------------\nstatic inline unsigned int AT91F_PIO_GetOutputStatus( // \\return PIO Output Status\n        AT91PS_PIO pPio) // \\arg  pointer to a PIO controller\n{\n        return pPio->PIO_OSR;\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_PIO_IsOuputSet\n//* \\brief Test if PIO Output is Set\n//*----------------------------------------------------------------------------\nstatic inline int AT91F_PIO_IsOutputSet(\n        AT91PS_PIO pPio,   // \\arg  pointer to a PIO controller\n        unsigned int flag) // \\arg  flag to be tested\n{\n        return (AT91F_PIO_GetOutputStatus(pPio) & flag);\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_PIO_InputFilterEnable\n//* \\brief Input Filter Enable PIO\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_PIO_InputFilterEnable(\n        AT91PS_PIO pPio,   // \\arg  pointer to a PIO controller\n        unsigned int flag) // \\arg  pio input filter to be enabled\n{\n        pPio->PIO_IFER = flag;\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_PIO_InputFilterDisable\n//* \\brief Input Filter Disable PIO\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_PIO_InputFilterDisable(\n        AT91PS_PIO pPio,   // \\arg  pointer to a PIO controller\n        unsigned int flag) // \\arg  pio input filter to be disabled\n{\n        pPio->PIO_IFDR = flag;\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_PIO_GetInputFilterStatus\n//* \\brief Return PIO Input Filter Status\n//*----------------------------------------------------------------------------\nstatic inline unsigned int AT91F_PIO_GetInputFilterStatus( // \\return PIO Input Filter Status\n        AT91PS_PIO pPio) // \\arg  pointer to a PIO controller\n{\n        return pPio->PIO_IFSR;\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_PIO_IsInputFilterSet\n//* \\brief Test if PIO Input filter is Set\n//*----------------------------------------------------------------------------\nstatic inline int AT91F_PIO_IsInputFilterSet(\n        AT91PS_PIO pPio,   // \\arg  pointer to a PIO controller\n        unsigned int flag) // \\arg  flag to be tested\n{\n        return (AT91F_PIO_GetInputFilterStatus(pPio) & flag);\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_PIO_GetOutputDataStatus\n//* \\brief Return PIO Output Data Status \n//*----------------------------------------------------------------------------\nstatic inline unsigned int AT91F_PIO_GetOutputDataStatus( // \\return PIO Output Data Status \n\tAT91PS_PIO pPio) // \\arg  pointer to a PIO controller\n{\n        return pPio->PIO_ODSR;\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_PIO_InterruptEnable\n//* \\brief Enable PIO Interrupt\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_PIO_InterruptEnable(\n        AT91PS_PIO pPio,   // \\arg  pointer to a PIO controller\n        unsigned int flag) // \\arg  pio interrupt to be enabled\n{\n        pPio->PIO_IER = flag;\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_PIO_InterruptDisable\n//* \\brief Disable PIO Interrupt\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_PIO_InterruptDisable(\n        AT91PS_PIO pPio,   // \\arg  pointer to a PIO controller\n        unsigned int flag) // \\arg  pio interrupt to be disabled\n{\n        pPio->PIO_IDR = flag;\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_PIO_GetInterruptMaskStatus\n//* \\brief Return PIO Interrupt Mask Status\n//*----------------------------------------------------------------------------\nstatic inline unsigned int AT91F_PIO_GetInterruptMaskStatus( // \\return PIO Interrupt Mask Status\n        AT91PS_PIO pPio) // \\arg  pointer to a PIO controller\n{\n        return pPio->PIO_IMR;\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_PIO_GetInterruptStatus\n//* \\brief Return PIO Interrupt Status\n//*----------------------------------------------------------------------------\nstatic inline unsigned int AT91F_PIO_GetInterruptStatus( // \\return PIO Interrupt Status\n        AT91PS_PIO pPio) // \\arg  pointer to a PIO controller\n{\n        return pPio->PIO_ISR;\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_PIO_IsInterruptMasked\n//* \\brief Test if PIO Interrupt is Masked \n//*----------------------------------------------------------------------------\nstatic inline int AT91F_PIO_IsInterruptMasked(\n        AT91PS_PIO pPio,   // \\arg  pointer to a PIO controller\n        unsigned int flag) // \\arg  flag to be tested\n{\n        return (AT91F_PIO_GetInterruptMaskStatus(pPio) & flag);\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_PIO_IsInterruptSet\n//* \\brief Test if PIO Interrupt is Set\n//*----------------------------------------------------------------------------\nstatic inline int AT91F_PIO_IsInterruptSet(\n        AT91PS_PIO pPio,   // \\arg  pointer to a PIO controller\n        unsigned int flag) // \\arg  flag to be tested\n{\n        return (AT91F_PIO_GetInterruptStatus(pPio) & flag);\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_PIO_MultiDriverEnable\n//* \\brief Multi Driver Enable PIO\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_PIO_MultiDriverEnable(\n        AT91PS_PIO pPio,   // \\arg  pointer to a PIO controller\n        unsigned int flag) // \\arg  pio to be enabled\n{\n        pPio->PIO_MDER = flag;\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_PIO_MultiDriverDisable\n//* \\brief Multi Driver Disable PIO\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_PIO_MultiDriverDisable(\n        AT91PS_PIO pPio,   // \\arg  pointer to a PIO controller\n        unsigned int flag) // \\arg  pio to be disabled\n{\n        pPio->PIO_MDDR = flag;\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_PIO_GetMultiDriverStatus\n//* \\brief Return PIO Multi Driver Status\n//*----------------------------------------------------------------------------\nstatic inline unsigned int AT91F_PIO_GetMultiDriverStatus( // \\return PIO Multi Driver Status\n        AT91PS_PIO pPio) // \\arg  pointer to a PIO controller\n{\n        return pPio->PIO_MDSR;\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_PIO_IsMultiDriverSet\n//* \\brief Test if PIO MultiDriver is Set\n//*----------------------------------------------------------------------------\nstatic inline int AT91F_PIO_IsMultiDriverSet(\n        AT91PS_PIO pPio,   // \\arg  pointer to a PIO controller\n        unsigned int flag) // \\arg  flag to be tested\n{\n        return (AT91F_PIO_GetMultiDriverStatus(pPio) & flag);\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_PIO_A_RegisterSelection\n//* \\brief PIO A Register Selection \n//*----------------------------------------------------------------------------\nstatic inline void AT91F_PIO_A_RegisterSelection(\n        AT91PS_PIO pPio,   // \\arg  pointer to a PIO controller\n        unsigned int flag) // \\arg  pio A register selection\n{\n        pPio->PIO_ASR = flag;\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_PIO_B_RegisterSelection\n//* \\brief PIO B Register Selection \n//*----------------------------------------------------------------------------\nstatic inline void AT91F_PIO_B_RegisterSelection(\n        AT91PS_PIO pPio,   // \\arg  pointer to a PIO controller\n        unsigned int flag) // \\arg  pio B register selection \n{\n        pPio->PIO_BSR = flag;\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_PIO_Get_AB_RegisterStatus\n//* \\brief Return PIO Interrupt Status\n//*----------------------------------------------------------------------------\nstatic inline unsigned int AT91F_PIO_Get_AB_RegisterStatus( // \\return PIO AB Register Status\n        AT91PS_PIO pPio) // \\arg  pointer to a PIO controller\n{\n        return pPio->PIO_ABSR;\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_PIO_IsAB_RegisterSet\n//* \\brief Test if PIO AB Register is Set\n//*----------------------------------------------------------------------------\nstatic inline int AT91F_PIO_IsAB_RegisterSet(\n        AT91PS_PIO pPio,   // \\arg  pointer to a PIO controller\n        unsigned int flag) // \\arg  flag to be tested\n{\n        return (AT91F_PIO_Get_AB_RegisterStatus(pPio) & flag);\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_PIO_OutputWriteEnable\n//* \\brief Output Write Enable PIO\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_PIO_OutputWriteEnable(\n        AT91PS_PIO pPio,   // \\arg  pointer to a PIO controller\n        unsigned int flag) // \\arg  pio output write to be enabled\n{\n        pPio->PIO_OWER = flag;\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_PIO_OutputWriteDisable\n//* \\brief Output Write Disable PIO\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_PIO_OutputWriteDisable(\n        AT91PS_PIO pPio,   // \\arg  pointer to a PIO controller\n        unsigned int flag) // \\arg  pio output write to be disabled\n{\n        pPio->PIO_OWDR = flag;\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_PIO_GetOutputWriteStatus\n//* \\brief Return PIO Output Write Status\n//*----------------------------------------------------------------------------\nstatic inline unsigned int AT91F_PIO_GetOutputWriteStatus( // \\return PIO Output Write Status\n        AT91PS_PIO pPio) // \\arg  pointer to a PIO controller\n{\n        return pPio->PIO_OWSR;\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_PIO_IsOutputWriteSet\n//* \\brief Test if PIO OutputWrite is Set\n//*----------------------------------------------------------------------------\nstatic inline int AT91F_PIO_IsOutputWriteSet(\n        AT91PS_PIO pPio,   // \\arg  pointer to a PIO controller\n        unsigned int flag) // \\arg  flag to be tested\n{\n        return (AT91F_PIO_GetOutputWriteStatus(pPio) & flag);\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_PIO_GetCfgPullup\n//* \\brief Return PIO Configuration Pullup\n//*----------------------------------------------------------------------------\nstatic inline unsigned int AT91F_PIO_GetCfgPullup( // \\return PIO Configuration Pullup \n        AT91PS_PIO pPio) // \\arg  pointer to a PIO controller\n{\n        return pPio->PIO_PPUSR;\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_PIO_IsOutputDataStatusSet\n//* \\brief Test if PIO Output Data Status is Set \n//*----------------------------------------------------------------------------\nstatic inline int AT91F_PIO_IsOutputDataStatusSet(\n        AT91PS_PIO pPio,   // \\arg  pointer to a PIO controller\n        unsigned int flag) // \\arg  flag to be tested\n{\n        return (AT91F_PIO_GetOutputDataStatus(pPio) & flag);\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_PIO_IsCfgPullupStatusSet\n//* \\brief Test if PIO Configuration Pullup Status is Set\n//*----------------------------------------------------------------------------\nstatic inline int AT91F_PIO_IsCfgPullupStatusSet(\n        AT91PS_PIO pPio,   // \\arg  pointer to a PIO controller\n        unsigned int flag) // \\arg  flag to be tested\n{\n        return (~AT91F_PIO_GetCfgPullup(pPio) & flag);\n}\n\n/* *****************************************************************************\n                SOFTWARE API FOR TWI\n   ***************************************************************************** */\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_TWI_EnableIt\n//* \\brief Enable TWI IT\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_TWI_EnableIt (\n\tAT91PS_TWI pTWI, // \\arg pointer to a TWI controller\n\tunsigned int flag)   // \\arg IT to be enabled\n{\n\t//* Write to the IER register\n\tpTWI->TWI_IER = flag;\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_TWI_DisableIt\n//* \\brief Disable TWI IT\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_TWI_DisableIt (\n\tAT91PS_TWI pTWI, // \\arg pointer to a TWI controller\n\tunsigned int flag)   // \\arg IT to be disabled\n{\n\t//* Write to the IDR register\n\tpTWI->TWI_IDR = flag;\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_TWI_Configure\n//* \\brief Configure TWI in master mode\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_TWI_Configure ( AT91PS_TWI pTWI )          // \\arg pointer to a TWI controller\n{\n    //* Disable interrupts\n\tpTWI->TWI_IDR = (unsigned int) -1;\n\n    //* Reset peripheral\n\tpTWI->TWI_CR = AT91C_TWI_SWRST;\n\n\t//* Set Master mode\n\tpTWI->TWI_CR = AT91C_TWI_MSEN | AT91C_TWI_SVDIS;\n\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_TWI_GetInterruptMaskStatus\n//* \\brief Return TWI Interrupt Mask Status\n//*----------------------------------------------------------------------------\nstatic inline unsigned int AT91F_TWI_GetInterruptMaskStatus( // \\return TWI Interrupt Mask Status\n        AT91PS_TWI pTwi) // \\arg  pointer to a TWI controller\n{\n        return pTwi->TWI_IMR;\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_TWI_IsInterruptMasked\n//* \\brief Test if TWI Interrupt is Masked \n//*----------------------------------------------------------------------------\nstatic inline int AT91F_TWI_IsInterruptMasked(\n        AT91PS_TWI pTwi,   // \\arg  pointer to a TWI controller\n        unsigned int flag) // \\arg  flag to be tested\n{\n        return (AT91F_TWI_GetInterruptMaskStatus(pTwi) & flag);\n}\n\n/* *****************************************************************************\n                SOFTWARE API FOR USART\n   ***************************************************************************** */\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_US_Baudrate\n//* \\brief Calculate the baudrate\n//* Standard Asynchronous Mode : 8 bits , 1 stop , no parity\n#define AT91C_US_ASYNC_MODE ( AT91C_US_USMODE_NORMAL + \\\n                        AT91C_US_NBSTOP_1_BIT + \\\n                        AT91C_US_PAR_NONE + \\\n                        AT91C_US_CHRL_8_BITS + \\\n                        AT91C_US_CLKS_CLOCK )\n\n//* Standard External Asynchronous Mode : 8 bits , 1 stop , no parity\n#define AT91C_US_ASYNC_SCK_MODE ( AT91C_US_USMODE_NORMAL + \\\n                            AT91C_US_NBSTOP_1_BIT + \\\n                            AT91C_US_PAR_NONE + \\\n                            AT91C_US_CHRL_8_BITS + \\\n                            AT91C_US_CLKS_EXT )\n\n//* Standard Synchronous Mode : 8 bits , 1 stop , no parity\n#define AT91C_US_SYNC_MODE ( AT91C_US_SYNC + \\\n                       AT91C_US_USMODE_NORMAL + \\\n                       AT91C_US_NBSTOP_1_BIT + \\\n                       AT91C_US_PAR_NONE + \\\n                       AT91C_US_CHRL_8_BITS + \\\n                       AT91C_US_CLKS_CLOCK )\n\n//* SCK used Label\n#define AT91C_US_SCK_USED (AT91C_US_CKLO | AT91C_US_CLKS_EXT)\n\n//* Standard ISO T=0 Mode : 8 bits , 1 stop , parity\n#define AT91C_US_ISO_READER_MODE ( AT91C_US_USMODE_ISO7816_0 + \\\n\t\t\t\t\t   \t\t AT91C_US_CLKS_CLOCK +\\\n                       \t\t AT91C_US_NBSTOP_1_BIT + \\\n                       \t\t AT91C_US_PAR_EVEN + \\\n                       \t\t AT91C_US_CHRL_8_BITS + \\\n                       \t\t AT91C_US_CKLO +\\\n                       \t\t AT91C_US_OVER)\n\n//* Standard IRDA mode\n#define AT91C_US_ASYNC_IRDA_MODE (  AT91C_US_USMODE_IRDA + \\\n                            AT91C_US_NBSTOP_1_BIT + \\\n                            AT91C_US_PAR_NONE + \\\n                            AT91C_US_CHRL_8_BITS + \\\n                            AT91C_US_CLKS_CLOCK )\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_US_Baudrate\n//* \\brief Caluculate baud_value according to the main clock and the baud rate\n//*----------------------------------------------------------------------------\nstatic inline unsigned int AT91F_US_Baudrate (\n\tconst unsigned int main_clock, // \\arg peripheral clock\n\tconst unsigned int baud_rate)  // \\arg UART baudrate\n{\n\tunsigned int baud_value = ((main_clock*10)/(baud_rate * 16));\n\tif ((baud_value % 10) >= 5)\n\t\tbaud_value = (baud_value / 10) + 1;\n\telse\n\t\tbaud_value /= 10;\n\treturn baud_value;\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_US_SetBaudrate\n//* \\brief Set the baudrate according to the CPU clock\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_US_SetBaudrate (\n\tAT91PS_USART pUSART,    // \\arg pointer to a USART controller\n\tunsigned int mainClock, // \\arg peripheral clock\n\tunsigned int speed)     // \\arg UART baudrate\n{\n\t//* Define the baud rate divisor register\n\tpUSART->US_BRGR = AT91F_US_Baudrate(mainClock, speed);\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_US_SetTimeguard\n//* \\brief Set USART timeguard\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_US_SetTimeguard (\n\tAT91PS_USART pUSART,    // \\arg pointer to a USART controller\n\tunsigned int timeguard) // \\arg timeguard value\n{\n\t//* Write the Timeguard Register\n\tpUSART->US_TTGR = timeguard ;\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_US_EnableIt\n//* \\brief Enable USART IT\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_US_EnableIt (\n\tAT91PS_USART pUSART, // \\arg pointer to a USART controller\n\tunsigned int flag)   // \\arg IT to be enabled\n{\n\t//* Write to the IER register\n\tpUSART->US_IER = flag;\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_US_DisableIt\n//* \\brief Disable USART IT\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_US_DisableIt (\n\tAT91PS_USART pUSART, // \\arg pointer to a USART controller\n\tunsigned int flag)   // \\arg IT to be disabled\n{\n\t//* Write to the IER register\n\tpUSART->US_IDR = flag;\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_US_Configure\n//* \\brief Configure USART\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_US_Configure (\n\tAT91PS_USART pUSART,     // \\arg pointer to a USART controller\n\tunsigned int mainClock,  // \\arg peripheral clock\n\tunsigned int mode ,      // \\arg mode Register to be programmed\n\tunsigned int baudRate ,  // \\arg baudrate to be programmed\n\tunsigned int timeguard ) // \\arg timeguard to be programmed\n{\n    //* Disable interrupts\n    pUSART->US_IDR = (unsigned int) -1;\n\n    //* Reset receiver and transmitter\n    pUSART->US_CR = AT91C_US_RSTRX | AT91C_US_RSTTX | AT91C_US_RXDIS | AT91C_US_TXDIS ;\n\n\t//* Define the baud rate divisor register\n\tAT91F_US_SetBaudrate(pUSART, mainClock, baudRate);\n\n\t//* Write the Timeguard Register\n\tAT91F_US_SetTimeguard(pUSART, timeguard);\n\n    //* Clear Transmit and Receive Counters\n    AT91F_PDC_Open((AT91PS_PDC) &(pUSART->US_RPR));\n\n    //* Define the USART mode\n    pUSART->US_MR = mode  ;\n\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_US_EnableRx\n//* \\brief Enable receiving characters\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_US_EnableRx (\n\tAT91PS_USART pUSART)     // \\arg pointer to a USART controller\n{\n    //* Enable receiver\n    pUSART->US_CR = AT91C_US_RXEN;\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_US_EnableTx\n//* \\brief Enable sending characters\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_US_EnableTx (\n\tAT91PS_USART pUSART)     // \\arg pointer to a USART controller\n{\n    //* Enable  transmitter\n    pUSART->US_CR = AT91C_US_TXEN;\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_US_ResetRx\n//* \\brief Reset Receiver and re-enable it\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_US_ResetRx (\n\tAT91PS_USART pUSART)     // \\arg pointer to a USART controller\n{\n\t//* Reset receiver\n\tpUSART->US_CR = AT91C_US_RSTRX;\n    //* Re-Enable receiver\n    pUSART->US_CR = AT91C_US_RXEN;\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_US_ResetTx\n//* \\brief Reset Transmitter and re-enable it\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_US_ResetTx (\n\tAT91PS_USART pUSART)     // \\arg pointer to a USART controller\n{\n\t//* Reset transmitter\n\tpUSART->US_CR = AT91C_US_RSTTX;\n    //* Enable transmitter\n    pUSART->US_CR = AT91C_US_TXEN;\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_US_DisableRx\n//* \\brief Disable Receiver\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_US_DisableRx (\n\tAT91PS_USART pUSART)     // \\arg pointer to a USART controller\n{\n    //* Disable receiver\n    pUSART->US_CR = AT91C_US_RXDIS;\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_US_DisableTx\n//* \\brief Disable Transmitter\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_US_DisableTx (\n\tAT91PS_USART pUSART)     // \\arg pointer to a USART controller\n{\n    //* Disable transmitter\n    pUSART->US_CR = AT91C_US_TXDIS;\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_US_Close\n//* \\brief Close USART: disable IT disable receiver and transmitter, close PDC\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_US_Close (\n\tAT91PS_USART pUSART)     // \\arg pointer to a USART controller\n{\n    //* Reset the baud rate divisor register\n    pUSART->US_BRGR = 0 ;\n\n    //* Reset the USART mode\n    pUSART->US_MR = 0  ;\n\n    //* Reset the Timeguard Register\n    pUSART->US_TTGR = 0;\n\n    //* Disable all interrupts\n    pUSART->US_IDR = 0xFFFFFFFF ;\n\n    //* Abort the Peripheral Data Transfers\n    AT91F_PDC_Close((AT91PS_PDC) &(pUSART->US_RPR));\n\n    //* Disable receiver and transmitter and stop any activity immediately\n    pUSART->US_CR = AT91C_US_TXDIS | AT91C_US_RXDIS | AT91C_US_RSTTX | AT91C_US_RSTRX ;\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_US_TxReady\n//* \\brief Return 1 if a character can be written in US_THR\n//*----------------------------------------------------------------------------\nstatic inline unsigned int AT91F_US_TxReady (\n\tAT91PS_USART pUSART )     // \\arg pointer to a USART controller\n{\n    return (pUSART->US_CSR & AT91C_US_TXRDY);\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_US_RxReady\n//* \\brief Return 1 if a character can be read in US_RHR\n//*----------------------------------------------------------------------------\nstatic inline unsigned int AT91F_US_RxReady (\n\tAT91PS_USART pUSART )     // \\arg pointer to a USART controller\n{\n    return (pUSART->US_CSR & AT91C_US_RXRDY);\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_US_Error\n//* \\brief Return the error flag\n//*----------------------------------------------------------------------------\nstatic inline unsigned int AT91F_US_Error (\n\tAT91PS_USART pUSART )     // \\arg pointer to a USART controller\n{\n    return (pUSART->US_CSR &\n    \t(AT91C_US_OVRE |  // Overrun error\n    \t AT91C_US_FRAME | // Framing error\n    \t AT91C_US_PARE));  // Parity error\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_US_PutChar\n//* \\brief Send a character,does not check if ready to send\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_US_PutChar (\n\tAT91PS_USART pUSART,\n\tint character )\n{\n    pUSART->US_THR = (character & 0x1FF);\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_US_GetChar\n//* \\brief Receive a character,does not check if a character is available\n//*----------------------------------------------------------------------------\nstatic inline int AT91F_US_GetChar (\n\tconst AT91PS_USART pUSART)\n{\n    return((pUSART->US_RHR) & 0x1FF);\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_US_SendFrame\n//* \\brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy\n//*----------------------------------------------------------------------------\nstatic inline unsigned int AT91F_US_SendFrame(\n\tAT91PS_USART pUSART,\n\tchar *pBuffer,\n\tunsigned int szBuffer,\n\tchar *pNextBuffer,\n\tunsigned int szNextBuffer )\n{\n\treturn AT91F_PDC_SendFrame(\n\t\t(AT91PS_PDC) &(pUSART->US_RPR),\n\t\tpBuffer,\n\t\tszBuffer,\n\t\tpNextBuffer,\n\t\tszNextBuffer);\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_US_ReceiveFrame\n//* \\brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy\n//*----------------------------------------------------------------------------\nstatic inline unsigned int AT91F_US_ReceiveFrame (\n\tAT91PS_USART pUSART,\n\tchar *pBuffer,\n\tunsigned int szBuffer,\n\tchar *pNextBuffer,\n\tunsigned int szNextBuffer )\n{\n\treturn AT91F_PDC_ReceiveFrame(\n\t\t(AT91PS_PDC) &(pUSART->US_RPR),\n\t\tpBuffer,\n\t\tszBuffer,\n\t\tpNextBuffer,\n\t\tszNextBuffer);\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_US_SetIrdaFilter\n//* \\brief Set the value of IrDa filter tregister\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_US_SetIrdaFilter (\n\tAT91PS_USART pUSART,\n\tunsigned char value\n)\n{\n\tpUSART->US_IF = value;\n}\n\n/* *****************************************************************************\n                SOFTWARE API FOR MCI\n   ***************************************************************************** */\n//* Classic MCI Mode Register Configuration with PDC mode enabled and MCK = MCI Clock\n#define AT91C_MCI_MR_PDCMODE\t(AT91C_MCI_CLKDIV |\\\n                                AT91C_MCI_PWSDIV |\\\n                                (AT91C_MCI_PWSDIV<<1) |\\\n                                AT91C_MCI_PDCMODE)\n\n//* Classic MCI Data Timeout Register Configuration with 1048576 MCK cycles between 2 data transfer\n#define AT91C_MCI_DTOR_1MEGA_CYCLES\t(AT91C_MCI_DTOCYC | AT91C_MCI_DTOMUL)\n\n//* Classic MCI SDCard Register Configuration with 1-bit data bus on slot A\n#define AT91C_MCI_MMC_SLOTA\t(AT91C_MCI_SCDSEL & 0x0)\n\n//* Classic MCI SDCard Register Configuration with 1-bit data bus on slot B\n#define AT91C_MCI_MMC_SLOTB\t(AT91C_MCI_SCDSEL)\n\n//* Classic MCI SDCard Register Configuration with 4-bit data bus on slot A\n#define AT91C_MCI_SDCARD_4BITS_SLOTA\t( (AT91C_MCI_SCDSEL & 0x0) | AT91C_MCI_SCDBUS )\n\n//* Classic MCI SDCard Register Configuration with 4-bit data bus on slot B\n#define AT91C_MCI_SDCARD_4BITS_SLOTB\t(AT91C_MCI_SCDSEL | AT91C_MCI_SCDBUS)\n\n\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_MCI_Configure\n//* \\brief Configure the MCI\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_MCI_Configure (\n        AT91PS_MCI pMCI,  \t\t\t // \\arg pointer to a MCI controller\n        unsigned int DTOR_register,  // \\arg Data Timeout Register to be programmed\n        unsigned int MR_register,  \t // \\arg Mode Register to be programmed\n        unsigned int SDCR_register)  // \\arg SDCard Register to be programmed\n{\n    //* Reset the MCI\n    pMCI->MCI_CR = AT91C_MCI_MCIEN | AT91C_MCI_PWSEN;\n\n    //* Disable all the interrupts\n    pMCI->MCI_IDR = 0xFFFFFFFF;\n\n    //* Set the Data Timeout Register\n    pMCI->MCI_DTOR = DTOR_register;\n\n    //* Set the Mode Register\n    pMCI->MCI_MR = MR_register;\n\n    //* Set the SDCard Register\n    pMCI->MCI_SDCR = SDCR_register;\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_MCI_EnableIt\n//* \\brief Enable MCI IT\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_MCI_EnableIt (\n        AT91PS_MCI pMCI, // \\arg pointer to a MCI controller\n        unsigned int flag)   // \\arg IT to be enabled\n{\n    //* Write to the IER register\n    pMCI->MCI_IER = flag;\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_MCI_DisableIt\n//* \\brief Disable MCI IT\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_MCI_DisableIt (\n        AT91PS_MCI pMCI, // \\arg pointer to a MCI controller\n        unsigned int flag)   // \\arg IT to be disabled\n{\n    //* Write to the IDR register\n    pMCI->MCI_IDR = flag;\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_MCI_Enable_Interface\n//* \\brief Enable the MCI Interface\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_MCI_Enable_Interface (\n        AT91PS_MCI pMCI)     // \\arg pointer to a MCI controller\n{\n    //* Enable the MCI\n    pMCI->MCI_CR = AT91C_MCI_MCIEN;\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_MCI_Disable_Interface\n//* \\brief Disable the MCI Interface\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_MCI_Disable_Interface (\n        AT91PS_MCI pMCI)     // \\arg pointer to a MCI controller\n{\n    //* Disable the MCI\n    pMCI->MCI_CR = AT91C_MCI_MCIDIS;\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_MCI_Cfg_ModeRegister\n//* \\brief Configure the MCI Mode Register\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_MCI_Cfg_ModeRegister (\n        AT91PS_MCI pMCI, // \\arg pointer to a MCI controller\n        unsigned int mode_register)   // \\arg value to set in the mode register\n{\n    //* Configure the MCI MR\n    pMCI->MCI_MR = mode_register;\n}\n/* *****************************************************************************\n                SOFTWARE API FOR AIC\n   ***************************************************************************** */\n#define AT91C_AIC_BRANCH_OPCODE ((void (*) ()) 0xE51FFF20) // ldr, pc, [pc, #-&F20]\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_AIC_ConfigureIt\n//* \\brief Interrupt Handler Initialization\n//*----------------------------------------------------------------------------\nstatic inline unsigned int AT91F_AIC_ConfigureIt (\n\tAT91PS_AIC pAic,  // \\arg pointer to the AIC registers\n\tunsigned int irq_id,     // \\arg interrupt number to initialize\n\tunsigned int priority,   // \\arg priority to give to the interrupt\n\tunsigned int src_type,   // \\arg activation and sense of activation\n\tvoid (*newHandler) (void) ) // \\arg address of the interrupt handler\n{\n\tunsigned int oldHandler;\n    unsigned int mask ;\n\n    oldHandler = pAic->AIC_SVR[irq_id];\n\n    mask = 0x1 << irq_id ;\n    //* Disable the interrupt on the interrupt controller\n    pAic->AIC_IDCR = mask ;\n    //* Save the interrupt handler routine pointer and the interrupt priority\n    pAic->AIC_SVR[irq_id] = (unsigned int) newHandler ;\n    //* Store the Source Mode Register\n    pAic->AIC_SMR[irq_id] = src_type | priority  ;\n    //* Clear the interrupt on the interrupt controller\n    pAic->AIC_ICCR = mask ;\n\n\treturn oldHandler;\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_AIC_EnableIt\n//* \\brief Enable corresponding IT number\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_AIC_EnableIt (\n\tAT91PS_AIC pAic,      // \\arg pointer to the AIC registers\n\tunsigned int irq_id ) // \\arg interrupt number to initialize\n{\n    //* Enable the interrupt on the interrupt controller\n    pAic->AIC_IECR = 0x1 << irq_id ;\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_AIC_DisableIt\n//* \\brief Disable corresponding IT number\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_AIC_DisableIt (\n\tAT91PS_AIC pAic,      // \\arg pointer to the AIC registers\n\tunsigned int irq_id ) // \\arg interrupt number to initialize\n{\n    unsigned int mask = 0x1 << irq_id;\n    //* Disable the interrupt on the interrupt controller\n    pAic->AIC_IDCR = mask ;\n    //* Clear the interrupt on the Interrupt Controller ( if one is pending )\n    pAic->AIC_ICCR = mask ;\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_AIC_ClearIt\n//* \\brief Clear corresponding IT number\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_AIC_ClearIt (\n\tAT91PS_AIC pAic,     // \\arg pointer to the AIC registers\n\tunsigned int irq_id) // \\arg interrupt number to initialize\n{\n    //* Clear the interrupt on the Interrupt Controller ( if one is pending )\n    pAic->AIC_ICCR = (0x1 << irq_id);\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_AIC_AcknowledgeIt\n//* \\brief Acknowledge corresponding IT number\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_AIC_AcknowledgeIt (\n\tAT91PS_AIC pAic)     // \\arg pointer to the AIC registers\n{\n    pAic->AIC_EOICR = pAic->AIC_EOICR;\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_AIC_SetExceptionVector\n//* \\brief Configure vector handler\n//*----------------------------------------------------------------------------\nstatic inline unsigned int  AT91F_AIC_SetExceptionVector (\n\tunsigned int *pVector, // \\arg pointer to the AIC registers\n\tvoid (*Handler) () )   // \\arg Interrupt Handler\n{\n\tunsigned int oldVector = *pVector;\n\n\tif ((unsigned int) Handler == (unsigned int) AT91C_AIC_BRANCH_OPCODE)\n\t\t*pVector = (unsigned int) AT91C_AIC_BRANCH_OPCODE;\n\telse\n\t\t*pVector = (((((unsigned int) Handler) - ((unsigned int) pVector) - 0x8) >> 2) & 0x00FFFFFF) | 0xEA000000;\n\n\treturn oldVector;\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_AIC_Trig\n//* \\brief Trig an IT\n//*----------------------------------------------------------------------------\nstatic inline void  AT91F_AIC_Trig (\n\tAT91PS_AIC pAic,     // \\arg pointer to the AIC registers\n\tunsigned int irq_id) // \\arg interrupt number\n{\n\tpAic->AIC_ISCR = (0x1 << irq_id) ;\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_AIC_IsActive\n//* \\brief Test if an IT is active\n//*----------------------------------------------------------------------------\nstatic inline unsigned int  AT91F_AIC_IsActive (\n\tAT91PS_AIC pAic,     // \\arg pointer to the AIC registers\n\tunsigned int irq_id) // \\arg Interrupt Number\n{\n\treturn (pAic->AIC_ISR & (0x1 << irq_id));\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_AIC_IsPending\n//* \\brief Test if an IT is pending\n//*----------------------------------------------------------------------------\nstatic inline unsigned int  AT91F_AIC_IsPending (\n\tAT91PS_AIC pAic,     // \\arg pointer to the AIC registers\n\tunsigned int irq_id) // \\arg Interrupt Number\n{\n\treturn (pAic->AIC_IPR & (0x1 << irq_id));\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_AIC_Open\n//* \\brief Set exception vectors and AIC registers to default values\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_AIC_Open(\n\tAT91PS_AIC pAic,        // \\arg pointer to the AIC registers\n\tvoid (*IrqHandler) (),  // \\arg Default IRQ vector exception\n\tvoid (*FiqHandler) (),  // \\arg Default FIQ vector exception\n\tvoid (*DefaultHandler)  (), // \\arg Default Handler set in ISR\n\tvoid (*SpuriousHandler) (), // \\arg Default Spurious Handler\n\tunsigned int protectMode)   // \\arg Debug Control Register\n{\n\tint i;\n\n\t// Disable all interrupts and set IVR to the default handler\n\tfor (i = 0; i < 32; ++i) {\n\t\tAT91F_AIC_DisableIt(pAic, i);\n\t\tAT91F_AIC_ConfigureIt(pAic, i, AT91C_AIC_PRIOR_LOWEST, AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE, DefaultHandler);\n\t}\n\n\t// Set the IRQ exception vector\n\tAT91F_AIC_SetExceptionVector((unsigned int *) 0x18, IrqHandler);\n\t// Set the Fast Interrupt exception vector\n\tAT91F_AIC_SetExceptionVector((unsigned int *) 0x1C, FiqHandler);\n\n\tpAic->AIC_SPU = (unsigned int) SpuriousHandler;\n\tpAic->AIC_DCR = protectMode;\n}\n/* *****************************************************************************\n                SOFTWARE API FOR UDP\n   ***************************************************************************** */\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_UDP_EnableIt\n//* \\brief Enable UDP IT\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_UDP_EnableIt (\n\tAT91PS_UDP pUDP,     // \\arg pointer to a UDP controller\n\tunsigned int flag)   // \\arg IT to be enabled\n{\n\t//* Write to the IER register\n\tpUDP->UDP_IER = flag;\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_UDP_DisableIt\n//* \\brief Disable UDP IT\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_UDP_DisableIt (\n\tAT91PS_UDP pUDP,     // \\arg pointer to a UDP controller\n\tunsigned int flag)   // \\arg IT to be disabled\n{\n\t//* Write to the IDR register\n\tpUDP->UDP_IDR = flag;\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_UDP_SetAddress\n//* \\brief Set UDP functional address\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_UDP_SetAddress (\n\tAT91PS_UDP pUDP,     // \\arg pointer to a UDP controller\n\tunsigned char address)   // \\arg new UDP address\n{\n\tpUDP->UDP_FADDR = (AT91C_UDP_FEN | address);\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_UDP_EnableEp\n//* \\brief Enable Endpoint\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_UDP_EnableEp (\n\tAT91PS_UDP pUDP,     // \\arg pointer to a UDP controller\n\tunsigned int flag)   // \\arg endpoints to be enabled\n{\n\tpUDP->UDP_GLBSTATE  |= flag;\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_UDP_DisableEp\n//* \\brief Enable Endpoint\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_UDP_DisableEp (\n\tAT91PS_UDP pUDP,     // \\arg pointer to a UDP controller\n\tunsigned int flag)   // \\arg endpoints to be enabled\n{\n\tpUDP->UDP_GLBSTATE  &= ~(flag);\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_UDP_SetState\n//* \\brief Set UDP Device state\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_UDP_SetState (\n\tAT91PS_UDP pUDP,     // \\arg pointer to a UDP controller\n\tunsigned int flag)   // \\arg new UDP address\n{\n\tpUDP->UDP_GLBSTATE  &= ~(AT91C_UDP_FADDEN | AT91C_UDP_CONFG);\n\tpUDP->UDP_GLBSTATE  |= flag;\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_UDP_GetState\n//* \\brief return UDP Device state\n//*----------------------------------------------------------------------------\nstatic inline unsigned int AT91F_UDP_GetState ( // \\return the UDP device state\n\tAT91PS_UDP pUDP)     // \\arg pointer to a UDP controller\n{\n\treturn (pUDP->UDP_GLBSTATE  & (AT91C_UDP_FADDEN | AT91C_UDP_CONFG));\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_UDP_ResetEp\n//* \\brief Reset UDP endpoint\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_UDP_ResetEp ( // \\return the UDP device state\n\tAT91PS_UDP pUDP,     // \\arg pointer to a UDP controller\n\tunsigned int flag)   // \\arg Endpoints to be reset\n{\n\tpUDP->UDP_RSTEP = flag;\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_UDP_EpStall\n//* \\brief Endpoint will STALL requests\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_UDP_EpStall(\n\tAT91PS_UDP pUDP,     // \\arg pointer to a UDP controller\n\tunsigned char endpoint)   // \\arg endpoint number\n{\n\tpUDP->UDP_CSR[endpoint] |= AT91C_UDP_FORCESTALL;\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_UDP_EpWrite\n//* \\brief Write value in the DPR\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_UDP_EpWrite(\n\tAT91PS_UDP pUDP,         // \\arg pointer to a UDP controller\n\tunsigned char endpoint,  // \\arg endpoint number\n\tunsigned char value)     // \\arg value to be written in the DPR\n{\n\tpUDP->UDP_FDR[endpoint] = value;\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_UDP_EpRead\n//* \\brief Return value from the DPR\n//*----------------------------------------------------------------------------\nstatic inline unsigned int AT91F_UDP_EpRead(\n\tAT91PS_UDP pUDP,         // \\arg pointer to a UDP controller\n\tunsigned char endpoint)  // \\arg endpoint number\n{\n\treturn pUDP->UDP_FDR[endpoint];\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_UDP_EpEndOfWr\n//* \\brief Notify the UDP that values in DPR are ready to be sent\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_UDP_EpEndOfWr(\n\tAT91PS_UDP pUDP,         // \\arg pointer to a UDP controller\n\tunsigned char endpoint)  // \\arg endpoint number\n{\n\tpUDP->UDP_CSR[endpoint] |= AT91C_UDP_TXPKTRDY;\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_UDP_EpClear\n//* \\brief Clear flag in the endpoint CSR register\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_UDP_EpClear(\n\tAT91PS_UDP pUDP,         // \\arg pointer to a UDP controller\n\tunsigned char endpoint,  // \\arg endpoint number\n\tunsigned int flag)       // \\arg flag to be cleared\n{\n\tpUDP->UDP_CSR[endpoint] &= ~(flag);\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_UDP_EpSet\n//* \\brief Set flag in the endpoint CSR register\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_UDP_EpSet(\n\tAT91PS_UDP pUDP,         // \\arg pointer to a UDP controller\n\tunsigned char endpoint,  // \\arg endpoint number\n\tunsigned int flag)       // \\arg flag to be cleared\n{\n\tpUDP->UDP_CSR[endpoint] |= flag;\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_UDP_EpStatus\n//* \\brief Return the endpoint CSR register\n//*----------------------------------------------------------------------------\nstatic inline unsigned int AT91F_UDP_EpStatus(\n\tAT91PS_UDP pUDP,         // \\arg pointer to a UDP controller\n\tunsigned char endpoint)  // \\arg endpoint number\n{\n\treturn pUDP->UDP_CSR[endpoint];\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_UDP_GetInterruptMaskStatus\n//* \\brief Return UDP Interrupt Mask Status\n//*----------------------------------------------------------------------------\nstatic inline unsigned int AT91F_UDP_GetInterruptMaskStatus( // \\return UDP Interrupt Mask Status\n        AT91PS_UDP pUdp) // \\arg  pointer to a UDP controller\n{\n        return pUdp->UDP_IMR;\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_UDP_IsInterruptMasked\n//* \\brief Test if UDP Interrupt is Masked \n//*----------------------------------------------------------------------------\nstatic inline int AT91F_UDP_IsInterruptMasked(\n        AT91PS_UDP pUdp,   // \\arg  pointer to a UDP controller\n        unsigned int flag) // \\arg  flag to be tested\n{\n        return (AT91F_UDP_GetInterruptMaskStatus(pUdp) & flag);\n}\n\n/* *****************************************************************************\n                SOFTWARE API FOR ST\n   ***************************************************************************** */\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_ST_SetPeriodInterval\n//* \\brief Set Periodic Interval Interrupt (period in ms)\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_ST_SetPeriodInterval(\n\tAT91PS_ST pSt,\n\tunsigned int period)\n{\n\tvolatile int status;\n\tpSt->ST_IDR = AT91C_ST_PITS;\t\t\t/* Interrupt disable Register */\n\n\tstatus = pSt->ST_SR;\n    pSt->ST_PIMR = period << 5;   \t\t\t/* Period Interval Mode Register == timer interval = 1ms*/\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_ST_EnableIt\n//* \\brief Enable system timer interrupt\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_ST_EnableIt(\n\tAT91PS_ST pSt,\n\tunsigned int flag)\n{\n\tpSt->ST_IER = flag;\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_ST_DisableIt\n//* \\brief Disable system timer interrupt\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_ST_DisableIt(\n\tAT91PS_ST pSt,\n\tunsigned int flag)\n{\n\tpSt->ST_IDR = flag;\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_ST_GetInterruptMaskStatus\n//* \\brief Return ST Interrupt Mask Status\n//*----------------------------------------------------------------------------\nstatic inline unsigned int AT91F_ST_GetInterruptMaskStatus( // \\return ST Interrupt Mask Status\n        AT91PS_ST pSt) // \\arg  pointer to a ST controller\n{\n        return pSt->ST_IMR;\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_ST_IsInterruptMasked\n//* \\brief Test if ST Interrupt is Masked \n//*----------------------------------------------------------------------------\nstatic inline int AT91F_ST_IsInterruptMasked(\n        AT91PS_ST pSt,   // \\arg  pointer to a ST controller\n        unsigned int flag) // \\arg  flag to be tested\n{\n        return (AT91F_ST_GetInterruptMaskStatus(pSt) & flag);\n}\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_EBI_CfgPIO\n//* \\brief Configure PIO controllers to drive EBI signals\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_EBI_CfgPIO (void)\n{\n\t// Configure PIO controllers to periph mode\n\tAT91F_PIO_CfgPeriph(\n\t\tAT91C_BASE_PIOC, // PIO controller base address\n\t\t((unsigned int) AT91C_PC8_A24     ) |\n\t\t((unsigned int) AT91C_PC7_A23     ), // Peripheral A\n\t\t0); // Peripheral B\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_DBGU_CfgPMC\n//* \\brief Enable Peripheral clock in PMC for  DBGU\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_DBGU_CfgPMC (void)\n{\n\tAT91F_PMC_EnablePeriphClock(\n\t\tAT91C_BASE_PMC, // PIO controller base address\n\t\t((unsigned int) 1 << AT91C_ID_SYS));\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_DBGU_CfgPIO\n//* \\brief Configure PIO controllers to drive DBGU signals\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_DBGU_CfgPIO (void)\n{\n\t// Configure PIO controllers to periph mode\n\tAT91F_PIO_CfgPeriph(\n\t\tAT91C_BASE_PIOA, // PIO controller base address\n\t\t((unsigned int) AT91C_PA31_DTXD    ) |\n\t\t((unsigned int) AT91C_PA30_DRXD    ), // Peripheral A\n\t\t0); // Peripheral B\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_SYS_CfgPMC\n//* \\brief Enable Peripheral clock in PMC for  SYS\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_SYS_CfgPMC (void)\n{\n\tAT91F_PMC_EnablePeriphClock(\n\t\tAT91C_BASE_PMC, // PIO controller base address\n\t\t((unsigned int) 1 << AT91C_ID_SYS));\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_UHP_CfgPMC\n//* \\brief Enable Peripheral clock in PMC for  UHP\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_UHP_CfgPMC (void)\n{\n\tAT91F_PMC_EnablePeriphClock(\n\t\tAT91C_BASE_PMC, // PIO controller base address\n\t\t((unsigned int) 1 << AT91C_ID_UHP));\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_SDRC_CfgPIO\n//* \\brief Configure PIO controllers to drive SDRC signals\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_SDRC_CfgPIO (void)\n{\n\t// Configure PIO controllers to periph mode\n\tAT91F_PIO_CfgPeriph(\n\t\tAT91C_BASE_PIOC, // PIO controller base address\n\t\t((unsigned int) AT91C_PC20_D20     ) |\n\t\t((unsigned int) AT91C_PC21_D21     ) |\n\t\t((unsigned int) AT91C_PC30_D30     ) |\n\t\t((unsigned int) AT91C_PC22_D22     ) |\n\t\t((unsigned int) AT91C_PC31_D31     ) |\n\t\t((unsigned int) AT91C_PC23_D23     ) |\n\t\t((unsigned int) AT91C_PC16_D16     ) |\n\t\t((unsigned int) AT91C_PC24_D24     ) |\n\t\t((unsigned int) AT91C_PC17_D17     ) |\n\t\t((unsigned int) AT91C_PC25_D25     ) |\n\t\t((unsigned int) AT91C_PC18_D18     ) |\n\t\t((unsigned int) AT91C_PC26_D26     ) |\n\t\t((unsigned int) AT91C_PC19_D19     ) |\n\t\t((unsigned int) AT91C_PC27_D27     ) |\n\t\t((unsigned int) AT91C_PC28_D28     ) |\n\t\t((unsigned int) AT91C_PC29_D29     ), // Peripheral A\n\t\t0); // Peripheral B\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_EMAC_CfgPMC\n//* \\brief Enable Peripheral clock in PMC for  EMAC\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_EMAC_CfgPMC (void)\n{\n\tAT91F_PMC_EnablePeriphClock(\n\t\tAT91C_BASE_PMC, // PIO controller base address\n\t\t((unsigned int) 1 << AT91C_ID_EMAC));\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_EMAC_CfgPIO\n//* \\brief Configure PIO controllers to drive EMAC signals\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_EMAC_CfgPIO (void)\n{\n\t// Configure PIO controllers to periph mode\n\tAT91F_PIO_CfgPeriph(\n\t\tAT91C_BASE_PIOA, // PIO controller base address\n\t\t((unsigned int) AT91C_PA14_ERXER   ) |\n\t\t((unsigned int) AT91C_PA12_ERX0    ) |\n\t\t((unsigned int) AT91C_PA13_ERX1    ) |\n\t\t((unsigned int) AT91C_PA8_ETXEN   ) |\n\t\t((unsigned int) AT91C_PA16_EMDIO   ) |\n\t\t((unsigned int) AT91C_PA9_ETX0    ) |\n\t\t((unsigned int) AT91C_PA10_ETX1    ) |\n\t\t((unsigned int) AT91C_PA11_ECRS_ECRSDV) |\n\t\t((unsigned int) AT91C_PA15_EMDC    ) |\n\t\t((unsigned int) AT91C_PA7_ETXCK_EREFCK), // Peripheral A\n\t\t0); // Peripheral B\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_RTC_CfgPMC\n//* \\brief Enable Peripheral clock in PMC for  RTC\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_RTC_CfgPMC (void)\n{\n\tAT91F_PMC_EnablePeriphClock(\n\t\tAT91C_BASE_PMC, // PIO controller base address\n\t\t((unsigned int) 1 << AT91C_ID_SYS));\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_SSC2_CfgPMC\n//* \\brief Enable Peripheral clock in PMC for  SSC2\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_SSC2_CfgPMC (void)\n{\n\tAT91F_PMC_EnablePeriphClock(\n\t\tAT91C_BASE_PMC, // PIO controller base address\n\t\t((unsigned int) 1 << AT91C_ID_SSC2));\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_SSC2_CfgPIO\n//* \\brief Configure PIO controllers to drive SSC2 signals\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_SSC2_CfgPIO (void)\n{\n\t// Configure PIO controllers to periph mode\n\tAT91F_PIO_CfgPeriph(\n\t\tAT91C_BASE_PIOB, // PIO controller base address\n\t\t((unsigned int) AT91C_PB12_TF2     ) |\n\t\t((unsigned int) AT91C_PB17_RF2     ) |\n\t\t((unsigned int) AT91C_PB13_TK2     ) |\n\t\t((unsigned int) AT91C_PB16_RK2     ) |\n\t\t((unsigned int) AT91C_PB14_TD2     ) |\n\t\t((unsigned int) AT91C_PB15_RD2     ), // Peripheral A\n\t\t0); // Peripheral B\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_SSC1_CfgPMC\n//* \\brief Enable Peripheral clock in PMC for  SSC1\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_SSC1_CfgPMC (void)\n{\n\tAT91F_PMC_EnablePeriphClock(\n\t\tAT91C_BASE_PMC, // PIO controller base address\n\t\t((unsigned int) 1 << AT91C_ID_SSC1));\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_SSC1_CfgPIO\n//* \\brief Configure PIO controllers to drive SSC1 signals\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_SSC1_CfgPIO (void)\n{\n\t// Configure PIO controllers to periph mode\n\tAT91F_PIO_CfgPeriph(\n\t\tAT91C_BASE_PIOB, // PIO controller base address\n\t\t((unsigned int) AT91C_PB11_RF1     ) |\n\t\t((unsigned int) AT91C_PB10_RK1     ) |\n\t\t((unsigned int) AT91C_PB8_TD1     ) |\n\t\t((unsigned int) AT91C_PB9_RD1     ), // Peripheral A\n\t\t0); // Peripheral B\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_SSC0_CfgPMC\n//* \\brief Enable Peripheral clock in PMC for  SSC0\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_SSC0_CfgPMC (void)\n{\n\tAT91F_PMC_EnablePeriphClock(\n\t\tAT91C_BASE_PMC, // PIO controller base address\n\t\t((unsigned int) 1 << AT91C_ID_SSC0));\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_SPI_CfgPMC\n//* \\brief Enable Peripheral clock in PMC for  SPI\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_SPI_CfgPMC (void)\n{\n\tAT91F_PMC_EnablePeriphClock(\n\t\tAT91C_BASE_PMC, // PIO controller base address\n\t\t((unsigned int) 1 << AT91C_ID_SPI));\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_SPI_CfgPIO\n//* \\brief Configure PIO controllers to drive SPI signals\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_SPI_CfgPIO (void)\n{\n\t// Configure PIO controllers to periph mode\n\tAT91F_PIO_CfgPeriph(\n\t\tAT91C_BASE_PIOA, // PIO controller base address\n\t\t((unsigned int) AT91C_PA3_NPCS0   ) |\n\t\t((unsigned int) AT91C_PA4_NPCS1   ) |\n\t\t((unsigned int) AT91C_PA1_MOSI    ) |\n\t\t((unsigned int) AT91C_PA5_NPCS2   ) |\n\t\t((unsigned int) AT91C_PA6_NPCS3   ) |\n\t\t((unsigned int) AT91C_PA0_MISO    ) |\n\t\t((unsigned int) AT91C_PA2_SPCK    ), // Peripheral A\n\t\t0); // Peripheral B\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_TC5_CfgPMC\n//* \\brief Enable Peripheral clock in PMC for  TC5\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_TC5_CfgPMC (void)\n{\n\tAT91F_PMC_EnablePeriphClock(\n\t\tAT91C_BASE_PMC, // PIO controller base address\n\t\t((unsigned int) 1 << AT91C_ID_TC5));\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_TC4_CfgPMC\n//* \\brief Enable Peripheral clock in PMC for  TC4\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_TC4_CfgPMC (void)\n{\n\tAT91F_PMC_EnablePeriphClock(\n\t\tAT91C_BASE_PMC, // PIO controller base address\n\t\t((unsigned int) 1 << AT91C_ID_TC4));\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_TC3_CfgPMC\n//* \\brief Enable Peripheral clock in PMC for  TC3\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_TC3_CfgPMC (void)\n{\n\tAT91F_PMC_EnablePeriphClock(\n\t\tAT91C_BASE_PMC, // PIO controller base address\n\t\t((unsigned int) 1 << AT91C_ID_TC3));\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_TC2_CfgPMC\n//* \\brief Enable Peripheral clock in PMC for  TC2\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_TC2_CfgPMC (void)\n{\n\tAT91F_PMC_EnablePeriphClock(\n\t\tAT91C_BASE_PMC, // PIO controller base address\n\t\t((unsigned int) 1 << AT91C_ID_TC2));\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_TC1_CfgPMC\n//* \\brief Enable Peripheral clock in PMC for  TC1\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_TC1_CfgPMC (void)\n{\n\tAT91F_PMC_EnablePeriphClock(\n\t\tAT91C_BASE_PMC, // PIO controller base address\n\t\t((unsigned int) 1 << AT91C_ID_TC1));\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_TC0_CfgPMC\n//* \\brief Enable Peripheral clock in PMC for  TC0\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_TC0_CfgPMC (void)\n{\n\tAT91F_PMC_EnablePeriphClock(\n\t\tAT91C_BASE_PMC, // PIO controller base address\n\t\t((unsigned int) 1 << AT91C_ID_TC0));\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_SMC2_CfgPIO\n//* \\brief Configure PIO controllers to drive SMC2 signals\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_SMC2_CfgPIO (void)\n{\n\t// Configure PIO controllers to periph mode\n\tAT91F_PIO_CfgPeriph(\n\t\tAT91C_BASE_PIOC, // PIO controller base address\n\t\t((unsigned int) AT91C_PC10_NCS4_CFCS) |\n\t\t((unsigned int) AT91C_PC9_A25_CFRNW) |\n\t\t((unsigned int) AT91C_PC12_NCS6_CFCE2) |\n\t\t((unsigned int) AT91C_PC11_NCS5_CFCE1), // Peripheral A\n\t\t0); // Peripheral B\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_PMC_CfgPMC\n//* \\brief Enable Peripheral clock in PMC for  PMC\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_PMC_CfgPMC (void)\n{\n\tAT91F_PMC_EnablePeriphClock(\n\t\tAT91C_BASE_PMC, // PIO controller base address\n\t\t((unsigned int) 1 << AT91C_ID_SYS));\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_PMC_CfgPIO\n//* \\brief Configure PIO controllers to drive PMC signals\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_PMC_CfgPIO (void)\n{\n\t// Configure PIO controllers to periph mode\n\tAT91F_PIO_CfgPeriph(\n\t\tAT91C_BASE_PIOA, // PIO controller base address\n\t\t0, // Peripheral A\n\t\t((unsigned int) AT91C_PA24_PCK1    )); // Peripheral B\n\t// Configure PIO controllers to periph mode\n\tAT91F_PIO_CfgPeriph(\n\t\tAT91C_BASE_PIOB, // PIO controller base address\n\t\t((unsigned int) AT91C_PB27_PCK0    ), // Peripheral A\n\t\t0); // Peripheral B\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_PIOD_CfgPMC\n//* \\brief Enable Peripheral clock in PMC for  PIOD\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_PIOD_CfgPMC (void)\n{\n\tAT91F_PMC_EnablePeriphClock(\n\t\tAT91C_BASE_PMC, // PIO controller base address\n\t\t((unsigned int) 1 << AT91C_ID_PIOD));\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_PIOC_CfgPMC\n//* \\brief Enable Peripheral clock in PMC for  PIOC\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_PIOC_CfgPMC (void)\n{\n\tAT91F_PMC_EnablePeriphClock(\n\t\tAT91C_BASE_PMC, // PIO controller base address\n\t\t((unsigned int) 1 << AT91C_ID_PIOC));\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_PIOB_CfgPMC\n//* \\brief Enable Peripheral clock in PMC for  PIOB\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_PIOB_CfgPMC (void)\n{\n\tAT91F_PMC_EnablePeriphClock(\n\t\tAT91C_BASE_PMC, // PIO controller base address\n\t\t((unsigned int) 1 << AT91C_ID_PIOB));\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_PIOA_CfgPMC\n//* \\brief Enable Peripheral clock in PMC for  PIOA\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_PIOA_CfgPMC (void)\n{\n\tAT91F_PMC_EnablePeriphClock(\n\t\tAT91C_BASE_PMC, // PIO controller base address\n\t\t((unsigned int) 1 << AT91C_ID_PIOA));\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_TWI_CfgPMC\n//* \\brief Enable Peripheral clock in PMC for  TWI\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_TWI_CfgPMC (void)\n{\n\tAT91F_PMC_EnablePeriphClock(\n\t\tAT91C_BASE_PMC, // PIO controller base address\n\t\t((unsigned int) 1 << AT91C_ID_TWI));\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_TWI_CfgPIO\n//* \\brief Configure PIO controllers to drive TWI signals\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_TWI_CfgPIO (void)\n{\n\t// Configure PIO controllers to periph mode\n\tAT91F_PIO_CfgPeriph(\n\t\tAT91C_BASE_PIOA, // PIO controller base address\n\t\t((unsigned int) AT91C_PA25_TWD     ) |\n\t\t((unsigned int) AT91C_PA26_TWCK    ), // Peripheral A\n\t\t0); // Peripheral B\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_US3_CfgPMC\n//* \\brief Enable Peripheral clock in PMC for  US3\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_US3_CfgPMC (void)\n{\n\tAT91F_PMC_EnablePeriphClock(\n\t\tAT91C_BASE_PMC, // PIO controller base address\n\t\t((unsigned int) 1 << AT91C_ID_US3));\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_US2_CfgPMC\n//* \\brief Enable Peripheral clock in PMC for  US2\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_US2_CfgPMC (void)\n{\n\tAT91F_PMC_EnablePeriphClock(\n\t\tAT91C_BASE_PMC, // PIO controller base address\n\t\t((unsigned int) 1 << AT91C_ID_US2));\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_US2_CfgPIO\n//* \\brief Configure PIO controllers to drive US2 signals\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_US2_CfgPIO (void)\n{\n\t// Configure PIO controllers to periph mode\n\tAT91F_PIO_CfgPeriph(\n\t\tAT91C_BASE_PIOA, // PIO controller base address\n\t\t((unsigned int) AT91C_PA23_TXD2    ) |\n\t\t((unsigned int) AT91C_PA22_RXD2    ), // Peripheral A\n\t\t0); // Peripheral B\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_US1_CfgPMC\n//* \\brief Enable Peripheral clock in PMC for  US1\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_US1_CfgPMC (void)\n{\n\tAT91F_PMC_EnablePeriphClock(\n\t\tAT91C_BASE_PMC, // PIO controller base address\n\t\t((unsigned int) 1 << AT91C_ID_US1));\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_US1_CfgPIO\n//* \\brief Configure PIO controllers to drive US1 signals\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_US1_CfgPIO (void)\n{\n\t// Configure PIO controllers to periph mode\n\tAT91F_PIO_CfgPeriph(\n\t\tAT91C_BASE_PIOB, // PIO controller base address\n\t\t((unsigned int) AT91C_PB21_RXD1    ) |\n\t\t((unsigned int) AT91C_PB26_RTS1    ) |\n\t\t((unsigned int) AT91C_PB25_DSR1    ) |\n\t\t((unsigned int) AT91C_PB24_CTS1    ) |\n\t\t((unsigned int) AT91C_PB19_DTR1    ) |\n\t\t((unsigned int) AT91C_PB23_DCD1    ) |\n\t\t((unsigned int) AT91C_PB20_TXD1    ) |\n\t\t((unsigned int) AT91C_PB18_RI1     ), // Peripheral A\n\t\t0); // Peripheral B\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_US0_CfgPMC\n//* \\brief Enable Peripheral clock in PMC for  US0\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_US0_CfgPMC (void)\n{\n\tAT91F_PMC_EnablePeriphClock(\n\t\tAT91C_BASE_PMC, // PIO controller base address\n\t\t((unsigned int) 1 << AT91C_ID_US0));\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_US0_CfgPIO\n//* \\brief Configure PIO controllers to drive US0 signals\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_US0_CfgPIO (void)\n{\n\t// Configure PIO controllers to periph mode\n\tAT91F_PIO_CfgPeriph(\n\t\tAT91C_BASE_PIOA, // PIO controller base address\n\t\t((unsigned int) AT91C_PA17_TXD0    ) |\n\t\t((unsigned int) AT91C_PA21_RTS0    ) |\n\t\t((unsigned int) AT91C_PA19_SCK0    ) |\n\t\t((unsigned int) AT91C_PA20_CTS0    ), // Peripheral A\n\t\t0); // Peripheral B\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_MCI_CfgPMC\n//* \\brief Enable Peripheral clock in PMC for  MCI\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_MCI_CfgPMC (void)\n{\n\tAT91F_PMC_EnablePeriphClock(\n\t\tAT91C_BASE_PMC, // PIO controller base address\n\t\t((unsigned int) 1 << AT91C_ID_MCI));\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_MCI_CfgPIO\n//* \\brief Configure PIO controllers to drive MCI signals\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_MCI_CfgPIO (void)\n{\n\t// Configure PIO controllers to periph mode\n\tAT91F_PIO_CfgPeriph(\n\t\tAT91C_BASE_PIOA, // PIO controller base address\n\t\t((unsigned int) AT91C_PA28_MCCDA   ) |\n\t\t((unsigned int) AT91C_PA29_MCDA0   ) |\n\t\t((unsigned int) AT91C_PA27_MCCK    ), // Peripheral A\n\t\t0); // Peripheral B\n\t// Configure PIO controllers to periph mode\n\tAT91F_PIO_CfgPeriph(\n\t\tAT91C_BASE_PIOB, // PIO controller base address\n\t\t0, // Peripheral A\n\t\t((unsigned int) AT91C_PB5_MCDA3   ) |\n\t\t((unsigned int) AT91C_PB3_MCDA1   ) |\n\t\t((unsigned int) AT91C_PB4_MCDA2   )); // Peripheral B\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_AIC_CfgPMC\n//* \\brief Enable Peripheral clock in PMC for  AIC\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_AIC_CfgPMC (void)\n{\n\tAT91F_PMC_EnablePeriphClock(\n\t\tAT91C_BASE_PMC, // PIO controller base address\n\t\t((unsigned int) 1 << AT91C_ID_IRQ4) |\n\t\t((unsigned int) 1 << AT91C_ID_FIQ) |\n\t\t((unsigned int) 1 << AT91C_ID_IRQ5) |\n\t\t((unsigned int) 1 << AT91C_ID_IRQ6) |\n\t\t((unsigned int) 1 << AT91C_ID_IRQ0) |\n\t\t((unsigned int) 1 << AT91C_ID_IRQ1) |\n\t\t((unsigned int) 1 << AT91C_ID_IRQ2) |\n\t\t((unsigned int) 1 << AT91C_ID_IRQ3));\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_UDP_CfgPMC\n//* \\brief Enable Peripheral clock in PMC for  UDP\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_UDP_CfgPMC (void)\n{\n\tAT91F_PMC_EnablePeriphClock(\n\t\tAT91C_BASE_PMC, // PIO controller base address\n\t\t((unsigned int) 1 << AT91C_ID_UDP));\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_ST_CfgPMC\n//* \\brief Enable Peripheral clock in PMC for  ST\n//*----------------------------------------------------------------------------\nstatic inline void AT91F_ST_CfgPMC (void)\n{\n\tAT91F_PMC_EnablePeriphClock(\n\t\tAT91C_BASE_PMC, // PIO controller base address\n\t\t((unsigned int) 1 << AT91C_ID_SYS));\n}\n\n#endif // lib_AT91RM9200_H\n"
  },
  {
    "path": "target/linux/at91/image/dfboot/src/init.c",
    "content": "//*----------------------------------------------------------------------------\n//*         ATMEL Microcontroller Software Support  -  ROUSSET  -\n//*----------------------------------------------------------------------------\n//* The software is delivered \"AS IS\" without warranty or condition of any\n//* kind, either express, implied or statutory. This includes without\n//* limitation any warranty or condition with respect to merchantability or\n//* fitness for any particular purpose, or against the infringements of\n//* intellectual property rights of others.\n//*----------------------------------------------------------------------------\n//* File Name           : init.c\n//* Object              : Low level initialisations written in C\n//* Creation            : HIi   10/10/2003\n//*\n//*----------------------------------------------------------------------------\n#include \"config.h\"\n#include \"AT91RM9200.h\"\n#include \"lib_AT91RM9200.h\"\n#include \"stdio.h\"\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_DataAbort\n//* \\brief This function reports an Abort\n//*----------------------------------------------------------------------------\nstatic void AT91F_SpuriousHandler() \n{\n\tputs(\"ISI\");\n\twhile (1);\n}\n\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_DataAbort\n//* \\brief This function reports an Abort\n//*----------------------------------------------------------------------------\nstatic void AT91F_DataAbort() \n{\n\tputs(\"IDA\");\n\twhile (1);\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_FetchAbort\n//* \\brief This function reports an Abort\n//*----------------------------------------------------------------------------\nstatic void AT91F_FetchAbort()\n{\n\tputs(\"IFA\");\n\twhile (1);\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_UndefHandler\n//* \\brief This function reports that no handler have been set for current IT\n//*----------------------------------------------------------------------------\nstatic void AT91F_UndefHandler() \n{\n\tputs(\"IUD\");\n\twhile (1);\n}\n\n\n//*--------------------------------------------------------------------------------------\n//* Function Name       : AT91F_InitSdram\n//* Object              : Initialize the SDRAM\n//* Input Parameters    :\n//* Output Parameters   :\n//*--------------------------------------------------------------------------------------\nstatic void AT91F_InitSdram()\n{\n\tint *pRegister;\n\t\n\t//* Configure PIOC as peripheral (D16/D31)\n\t\n\tAT91F_PIO_CfgPeriph(\n\t\tAT91C_BASE_PIOC, // PIO controller base address\n\t\t0xFFFF0030,\n\t\t0\n\t);\n\t\n\t//*Init SDRAM\n\tpRegister = (int *)0xFFFFFF98;\n\t*pRegister = 0x2188c155; \n\tpRegister = (int *)0xFFFFFF90;\n\t*pRegister = 0x2; \n\tpRegister = (int *)0x20000000;\n\t*pRegister = 0; \n\tpRegister = (int *)0xFFFFFF90;\n\t*pRegister = 0x4; \n\tpRegister = (int *)0x20000000;\n\t*pRegister = 0; \n\t*pRegister = 0; \n\t*pRegister = 0; \n\t*pRegister = 0; \n\t*pRegister = 0; \n\t*pRegister = 0; \n\t*pRegister = 0; \n\t*pRegister = 0; \n\tpRegister = (int *)0xFFFFFF90;\n\t*pRegister = 0x3; \n\tpRegister = (int *)0x20000080;\n\t*pRegister = 0; \n\n\tpRegister = (int *)0xFFFFFF94;\n\t*pRegister = 0x2e0; \n\tpRegister = (int *)0x20000000;\n\t*pRegister = 0; \n\n\tpRegister = (int *)0xFFFFFF90;\n\t*pRegister = 0x00; \n\tpRegister = (int *)0x20000000;\n\t*pRegister = 0; \n}\n\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_InitFlash\n//* \\brief This function performs low level HW initialization\n//*----------------------------------------------------------------------------\nstatic void AT91F_InitMemories()\n{\n\tint *pEbi = (int *)0xFFFFFF60;\n\n\t//* Setup MEMC to support all connected memories (CS0 = FLASH; CS1=SDRAM)\n\tpEbi  = (int *)0xFFFFFF60;\n\t*pEbi = 0x00000002;\n\n\t//* CS0 cs for flash\n\tpEbi  = (int *)0xFFFFFF70;\n\t*pEbi = 0x00003284;\n\t\n\tAT91F_InitSdram();\n}\n\n\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_LowLevelInit\n//* \\brief This function performs very low level HW initialization\n//*----------------------------------------------------------------------------\nvoid AT91F_LowLevelInit(void)\n{\n\tint i;\n\n\t// Init Interrupt Controller\n\tAT91F_AIC_Open(\n\t\tAT91C_BASE_AIC,          // pointer to the AIC registers\n\t\tAT91C_AIC_BRANCH_OPCODE, // IRQ exception vector\n\t\tAT91F_UndefHandler,      // FIQ exception vector\n\t\tAT91F_UndefHandler,      // AIC default handler\n\t\tAT91F_SpuriousHandler,   // AIC spurious handler\n\t\t0);                      // Protect mode\n\n\t// Perform 8 End Of Interrupt Command to make sre AIC will not Lock out nIRQ \n\tfor(i=0; i<8; i++)\n\t\tAT91F_AIC_AcknowledgeIt(AT91C_BASE_AIC);\n\n\tAT91F_AIC_SetExceptionVector((unsigned int *)0x0C, AT91F_FetchAbort);\n\tAT91F_AIC_SetExceptionVector((unsigned int *)0x10, AT91F_DataAbort);\n\tAT91F_AIC_SetExceptionVector((unsigned int *)0x4, AT91F_UndefHandler);\n\n\t//Initialize SDRAM and Flash\n\tAT91F_InitMemories();\n\n}\n\n"
  },
  {
    "path": "target/linux/at91/image/dfboot/src/jump.S",
    "content": ".global\t\tJump\n\t\nJump:\t\tmov pc, r0\t\t\t\t\n\n"
  },
  {
    "path": "target/linux/at91/image/dfboot/src/led.c",
    "content": "/*\n * (C) Copyright 2006\n * Atmel Nordic AB <www.atmel.com>\n * Ulf Samuelsson <ulf@atmel.com>\n *\n * See file CREDITS for list of people who contributed to this\n * project.\n *\n * This program is free software; you can redistribute it and/or\n * modify it under the terms of the GNU General Public License as\n * published by the Free Software Foundation; either version 2 of\n * the License, or (at your option) any later version.\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n * GNU General Public License for more details.\n *\n * You should have received a copy of the GNU General Public License\n * along with this program; if not, write to the Free Software\n * Foundation, Inc., 59 Temple Place, Suite 330, Boston,\n * MA 02111-1307 USA\n */\n\n#include <AT91RM9200.h>\n\n#define\tGREEN_LED\tAT91C_PIO_PB0\n#define\tYELLOW_LED\tAT91C_PIO_PB1\n#define\tRED_LED\tAT91C_PIO_PB2\n\nvoid\tLED_set(unsigned int led)\n{\n\tAT91PS_PIO\tPIOB\t= AT91C_BASE_PIOB;\n\tPIOB->PIO_SODR\t\t= (led ^ 0x7) & 0x7;\t\t// All 0's => Set PIO high => OFF\n\tPIOB->PIO_CODR\t\t=  led & 0x7;\t\t\t// All 1's => Set PIO low   => ON\n}\n\nvoid\tgreen_LED_on(void)\n{\n\tAT91PS_PIO\tPIOB\t= AT91C_BASE_PIOB;\n//\tPIOB->PIO_CODR\t\t= GREEN_LED;\n\tPIOB->PIO_CODR\t\t= (1 << 0);\n}\n\nvoid\t yellow_LED_on(void)\n{\n\tAT91PS_PIO\tPIOB\t= AT91C_BASE_PIOB;\n//\tPIOB->PIO_CODR\t\t= YELLOW_LED;\n\tPIOB->PIO_CODR\t\t= (1 << 1);\n}\n\nvoid\t red_LED_on(void)\n{\n\tAT91PS_PIO\tPIOB\t= AT91C_BASE_PIOB;\n//\tPIOB->PIO_CODR\t\t= RED_LED;\n\tPIOB->PIO_CODR\t\t= (1 << 2);\n}\n\nvoid\tgreen_LED_off(void)\n{\n\tAT91PS_PIO\tPIOB\t= AT91C_BASE_PIOB;\n//\tPIOB->PIO_SODR\t\t= GREEN_LED;\n\tPIOB->PIO_SODR\t\t= (1 << 0);\n}\n\nvoid\tyellow_LED_off(void)\n{\n\tAT91PS_PIO\tPIOB\t= AT91C_BASE_PIOB;\n//\tPIOB->PIO_SODR\t\t= YELLOW_LED;\n\tPIOB->PIO_SODR\t\t= (1 << 1);\n}\n\nvoid\tred_LED_off(void)\n{\n\tAT91PS_PIO\tPIOB\t= AT91C_BASE_PIOB;\n//\tPIOB->PIO_SODR\t\t= RED_LED;\n\tPIOB->PIO_SODR\t\t= (1 << 2);\n}\n\nvoid\tLED_blink(unsigned int led)\n{\n\tvolatile int i,j;\n\tfor(i = 0; i < 5; i++) {\n\t\tLED_set((1 << led)&0x7);\n\t\tfor(j= 0; j < 200000; j++);\n\t\tLED_set(0);\n\t\tfor(j= 0; j < 200000; j++);\n\t}\t\t\n}\n\n\nvoid LED_init (void)\n{\n\tAT91PS_PIO\tPIOB\t= AT91C_BASE_PIOB;\n\tAT91PS_PMC\tPMC\t= AT91C_BASE_PMC;\n\tPMC->PMC_PCER\t\t= (1 << AT91C_ID_PIOB);\t// Enable PIOB clock\n\t// Disable peripherals on LEDs\n\tPIOB->PIO_PER\t\t= AT91C_PIO_PB2 | AT91C_PIO_PB1 | AT91C_PIO_PB0;\n\t// Enable pins as outputs\n\tPIOB->PIO_OER\t\t= AT91C_PIO_PB2 | AT91C_PIO_PB1 | AT91C_PIO_PB0;\n\t// Turn all LEDs OFF\n\tPIOB->PIO_SODR\t\t= AT91C_PIO_PB2 | AT91C_PIO_PB1 | AT91C_PIO_PB0;\n}\n"
  },
  {
    "path": "target/linux/at91/image/dfboot/src/main.c",
    "content": "/*----------------------------------------------------------------------------\n *         ATMEL Microcontroller Software Support  -  ROUSSET  -\n *----------------------------------------------------------------------------\n * The software is delivered \"AS IS\" without warranty or condition of any\n * kind, either express, implied or statutory. This includes without\n * limitation any warranty or condition with respect to merchantability or\n * fitness for any particular purpose, or against the infringements of\n * intellectual property rights of others.\n *----------------------------------------------------------------------------\n * File Name\t\t: main.c\n * Object\t\t: \n * Creation\t\t: HIi\t10/10/2003\n * Modif\t\t: HIi\t15/06/2004 :\tadd crc32 to verify the download\n *                                          \tfrom dataflash\n *\t\t\t: HIi\t21/09/2004 :\tSet first PLLA to 180Mhz and MCK to\n *\t\t\t\t\t\t60Mhz to speed up dataflash boot (15Mhz)\n *\t\t\t: MLC\t12/04/2005 :\tModify SetPLL() to avoid errata\n *\t\t\t: USA\t30/12/2005 :\tChange to page Size 1056\n *\t\t\t\t\t\tChange startaddress to C0008400\n *\t\t\t\t\t\tChange SPI Speed to ~4 Mhz\n *\t\t\t\t\t\tAdd retry on CRC Error\n *----------------------------------------------------------------------------\n */\n#include \"config.h\"\n#include \"stdio.h\"\n#include \"AT91RM9200.h\"\n#include \"lib_AT91RM9200.h\"\n#include \"com.h\"\n#include \"main.h\"\n#include \"dataflash.h\"\n#include \"AT91C_MCI_Device.h\"\n\n#define\tDEBUGOUT\n#define XMODEM\n#define MEMDISP\n\n#ifdef\tPAGESZ_1056\n#define\tPAGESIZE\t1056\n#else\n#define\tPAGESIZE\t1024\n#endif\n\n#define AT91C_SDRAM_START 0x20000000\n#define AT91C_BOOT_ADDR 0x21F00000\n#define AT91C_BOOT_SIZE 128*PAGESIZE\n#ifdef\tPAGESZ_1056\n#define AT91C_BOOT_DATAFLASH_ADDR 0xC0008400\n#else\n#define AT91C_BOOT_DATAFLASH_ADDR 0xC0008000\n#endif\n#define AT91C_PLLA_VALUE 0x237A3E5A  // crystal= 18.432MHz - fixes BRG error at 115kbps\n//#define AT91C_PLLA_VALUE 0x2026BE04\t// crystal= 18.432MHz\n//#define AT91C_PLLA_VALUE 0x202CBE01\t// crystal= 4MHz\n\n\n\n#define DISP_LINE_LEN 16\n\n// Reason for boot failure\n#define\tIMAGE_BAD_SIZE\t\t\t0\n#define\tIMAGE_READ_FAILURE\t1\n#define\tIMAGE_CRC_ERROR\t\t2\n#define\tIMAGE_ERROR\t\t\t3\n#define\tSUCCESS\t\t\t\t-1\n\n/* prototypes*/\nextern void AT91F_ST_ASM_HANDLER(void);\nextern void Jump(unsigned int addr);\n\nconst char *menu_dataflash[] = {\n#ifdef XMODEM\n\t\"1: P DFboot\\n\",\n\t\"2: P U-Boot\\n\",\n#endif\n\t\"3: P SDCard\\n\",\n#ifdef\tPAGESZ_1056\n\t\"4: R UBOOT\\n\",\n#else\n\t\"4: R UBOOT\\n\",\n#endif\n#ifdef XMODEM\n\t\"5: P DF [addr]\\n\",\n#endif\n\t\"6: RD DF [addr]\\n\",\n\t\"7: E DF\\n\"\n};\n#ifdef XMODEM\n#define\tMAXMENU 7\n#else\n#define MAXMENU 4\n#endif\n\nchar message[20];\n#ifdef XMODEM\nvolatile char XmodemComplete = 0;\n#endif\nunsigned int StTick = 0;\n\nAT91S_RomBoot const *pAT91;\n#ifdef XMODEM\nAT91S_SBuffer sXmBuffer;\nAT91S_SvcXmodem svcXmodem;\nAT91S_Pipe xmodemPipe;\n#endif\nAT91S_CtlTempo ctlTempo;\n\n\n//*--------------------------------------------------------------------------------------\n//* Function Name       : GetTickCount()\n//* Object              : Return the number of systimer tick \n//* Input Parameters    :\n//* Output Parameters   :\n//*--------------------------------------------------------------------------------------\nunsigned int GetTickCount(void)\n{\n\treturn StTick;\n}\n\n#ifdef XMODEM\n//*--------------------------------------------------------------------------------------\n//* Function Name       : AT91_XmodemComplete()\n//* Object              : Perform the remap and jump to appli in RAM\n//* Input Parameters    :\n//* Output Parameters   :\n//*--------------------------------------------------------------------------------------\nstatic void AT91_XmodemComplete(AT91S_PipeStatus status, void *pVoid)\n{\n\t/* stop the Xmodem tempo */\n\tsvcXmodem.tempo.Stop(&(svcXmodem.tempo));\n\tXmodemComplete = 1;\n}\n\n\n//*--------------------------------------------------------------------------------------\n//* Function Name       : AT91F_XmodemProtocol(AT91S_PipeStatus status, void *pVoid)\n//* Object              : Xmodem dispatcher\n//* Input Parameters    :\n//* Output Parameters   :\n//*--------------------------------------------------------------------------------------\nstatic void XmodemProtocol(AT91S_PipeStatus status, void *pVoid)\n{\n\tAT91PS_SBuffer pSBuffer = (AT91PS_SBuffer) xmodemPipe.pBuffer->pChild;\n\tAT91PS_USART   pUsart     = svcXmodem.pUsart;\n\t\t\t\n\tif (pSBuffer->szRdBuffer == 0) {\n\t\t/* Start a tempo to wait the Xmodem protocol complete */\n\t\tsvcXmodem.tempo.Start(&(svcXmodem.tempo), 10, 0, AT91_XmodemComplete, pUsart);\t\t\t\t\t\t\t\t\n\t}\n}\n#endif\n\n//*--------------------------------------------------------------------------------------\n//* Function Name       : irq1_c_handler()\n//* Object              : C Interrupt handler for Interrutp source 1\n//* Input Parameters    : none\n//* Output Parameters   : none\n//*--------------------------------------------------------------------------------------\nvoid AT91F_ST_HANDLER(void)\n{\n\tvolatile unsigned int csr = *AT91C_DBGU_CSR;\n#ifdef XMODEM\n\tunsigned int error;\n#endif\n\t\n\tif (AT91C_BASE_ST->ST_SR & 0x01) {\n\t\tStTick++;\n\t\tctlTempo.CtlTempoTick(&ctlTempo);\n\t\treturn;\n\t}\n\n#ifdef XMODEM\n\terror = AT91F_US_Error((AT91PS_USART)AT91C_BASE_DBGU);\n\tif (csr & error) {\n\t\t/* Stop previous Xmodem transmition*/\n\t\t*(AT91C_DBGU_CR) = AT91C_US_RSTSTA;\n\t\tAT91F_US_DisableIt((AT91PS_USART)AT91C_BASE_DBGU, AT91C_US_ENDRX);\n\t\tAT91F_US_EnableIt((AT91PS_USART)AT91C_BASE_DBGU, AT91C_US_RXRDY);\n\n\t}\n\t\n\telse if (csr & (AT91C_US_TXRDY | AT91C_US_ENDTX | AT91C_US_TXEMPTY | \n\t                AT91C_US_RXRDY | AT91C_US_ENDRX | AT91C_US_TIMEOUT | \n\t                AT91C_US_RXBUFF)) {\n\t\tif ( !(svcXmodem.eot) )\n\t\t\tsvcXmodem.Handler(&svcXmodem, csr);\n\t}\n#endif\n}\n\n\n//*-----------------------------------------------------------------------------\n//* Function Name       : AT91F_DisplayMenu()\n//* Object              : \n//* Input Parameters    : \n//* Return value\t\t: \n//*-----------------------------------------------------------------------------\nstatic int AT91F_DisplayMenu(void)\n{\n\tint i, mci_present = 0;\n\tprintf(\"\\nDF LOADER %s %s %s\\n\",AT91C_VERSION,__DATE__,__TIME__);\n\tAT91F_DataflashPrintInfo();\n\tmci_present = AT91F_MCI_Init();\n\tfor(i = 0; i < MAXMENU; i++) {\n\t\tputs(menu_dataflash[i]);\n\t}\n\treturn mci_present;\n}\t\n\n\n//*-----------------------------------------------------------------------------\n//* Function Name       : AsciiToHex()\n//* Object              : ascii to hexa conversion\n//* Input Parameters    : \n//* Return value\t\t: \n//*-----------------------------------------------------------------------------\nstatic unsigned int AsciiToHex(char *s, unsigned int *val)\n{\n\tint n;\n\n\t*val=0;\n\t\n\tif(s[0] == '0' && ((s[1] == 'x') || (s[1] == 'X')))\n\t\ts+=2;\n\tn = 0;\t\n\twhile((n < 8) && (s[n] !=0))\n\t{\n\t\t*val <<= 4;\n\t\tif ( (s[n] >= '0') && (s[n] <='9'))\n\t\t\t*val += (s[n] - '0');\n\t\telse\t\n\t\t\tif ((s[n] >= 'a') && (s[n] <='f'))\n\t\t\t\t*val += (s[n] - 0x57);\n\t\t\telse\n\t\t\t\tif ((s[n] >= 'A') && (s[n] <='F'))\n\t\t\t\t\t*val += (s[n] - 0x37);\n\t\t\telse\n\t\t\t\treturn 0;\n\t\tn++;\n\t}\n\n\treturn 1;\t\t\t\t\n}\n\n\n#ifdef MEMDISP\n//*-----------------------------------------------------------------------------\n//* Function Name       : AT91F_MemoryDisplay()\n//* Object              : Display the content of the dataflash\n//* Input Parameters    : \n//* Return value\t\t: \n//*-----------------------------------------------------------------------------\nstatic int AT91F_MemoryDisplay(unsigned int addr, unsigned int length)\n{\n\tunsigned long\ti, nbytes, linebytes;\n\tchar\t*cp;\n//\tunsigned int \t*uip;\n//\tunsigned short \t*usp;\n\tunsigned char \t*ucp;\n\tchar linebuf[DISP_LINE_LEN];\n\n//\tnbytes = length * size;\n\tnbytes = length;\n   \tdo\n   \t{\n//   \t\tuip = (unsigned int *)linebuf;\n//   \t\tusp = (unsigned short *)linebuf;\n\t\tucp = (unsigned char *)linebuf;\n\t\t\n\t\tprintf(\"%08x:\", addr);\n\t\tlinebytes = (nbytes > DISP_LINE_LEN)?DISP_LINE_LEN:nbytes;\n                if((addr & 0xF0000000) == 0x20000000) {\n\t\t\tfor(i = 0; i < linebytes; i ++) {\n\t\t\t\tlinebuf[i] =  *(char *)(addr+i);\n\t\t\t}\n\t\t} else {\n\t\t\tread_dataflash(addr, linebytes, linebuf);\n\t\t}\n\t\tfor (i=0; i<linebytes; i++)\n\t\t{\n/*\t\t\tif (size == 4) \n\t\t\t\tprintf(\" %08x\", *uip++);\n\t\t\telse if (size == 2)\n\t\t\t\tprintf(\" %04x\", *usp++);\n\t\t\telse\n*/\n\t\t\t\tprintf(\" %02x\", *ucp++);\n//\t\t\taddr += size;\n\t\t\taddr++;\n\t\t}\n\t\tprintf(\"    \");\n\t\tcp = linebuf;\n\t\tfor (i=0; i<linebytes; i++) {\n\t\t\tif ((*cp < 0x20) || (*cp > 0x7e))\n\t\t\t\tprintf(\".\");\n\t\t\telse\n\t\t\t\tprintf(\"%c\", *cp);\n\t\t\tcp++;\n\t\t}\n\t\tprintf(\"\\n\");\n\t\tnbytes -= linebytes;\n\t} while (nbytes > 0);\n\treturn 0;\n}\n#endif\n\n//*--------------------------------------------------------------------------------------\n//* Function Name       : AT91F_SetPLL\n//* Object              : Set the PLLA to 180Mhz and Master clock to 60 Mhz\n//* Input Parameters    :\n//* Output Parameters   :\n//*--------------------------------------------------------------------------------------\nstatic unsigned int AT91F_SetPLL(void)\n{\n\tAT91_REG tmp;\n\tAT91PS_PMC pPmc = AT91C_BASE_PMC;\n\tAT91PS_CKGR pCkgr = AT91C_BASE_CKGR;\n\n\tpPmc->PMC_IDR = 0xFFFFFFFF;\n\n\t/* -Setup the PLL A */\n\tpCkgr->CKGR_PLLAR = AT91C_PLLA_VALUE;\n\n\twhile (!(*AT91C_PMC_SR & AT91C_PMC_LOCKA));\n\t\n\t/* - Switch Master Clock from PLLB to PLLA/3 */\n\ttmp = pPmc->PMC_MCKR;\n\t/* See Atmel Errata #27 and #28 */\n\tif (tmp & 0x0000001C) {\n\t\ttmp = (tmp & ~0x0000001C);\n\t\tpPmc->PMC_MCKR = tmp;\n\t\twhile (!(*AT91C_PMC_SR & AT91C_PMC_MCKRDY));\n\t}\n\tif (tmp != 0x00000202) {\n\t\tpPmc->PMC_MCKR = 0x00000202;\n\t\tif ((tmp & 0x00000003) != 0x00000002)\n\t\t\twhile (!(*AT91C_PMC_SR & AT91C_PMC_MCKRDY));\n\t}\n\n\treturn 1;\t\n}\n\n\n//*--------------------------------------------------------------------------------------\n//* Function Name       : AT91F_ResetRegisters\n//* Object              : Restore the initial state to registers\n//* Input Parameters    :\n//* Output Parameters   :\n//*--------------------------------------------------------------------------------------\nstatic unsigned int AT91F_ResetRegisters(void)\n{\n\tvolatile int i = 0;\n\n\t/* set the PIOs in input*/\n\t/* This disables the UART output, so dont execute for now*/\n\n#ifndef\tDEBUGOUT\n\t*AT91C_PIOA_ODR = 0xFFFFFFFF;\t/* Disables all the output pins */\n\t*AT91C_PIOA_PER = 0xFFFFFFFF;\t/* Enables the PIO to control all the pins */\n#endif\n\n\tAT91F_AIC_DisableIt (AT91C_BASE_AIC, AT91C_ID_SYS);\n\t/* close all peripheral clocks */\n\n#ifndef\tDEBUGOUT\n\tAT91C_BASE_PMC->PMC_PCDR = 0xFFFFFFFC;\n#endif\n\t/* Disable core interrupts and set supervisor mode */\n\t__asm__ (\"msr CPSR_c, #0xDF\"); //* ARM_MODE_SYS(0x1F) | I_BIT(0x80) | F_BIT(0x40)\n\t/* Clear all the interrupts */\n\t*AT91C_AIC_ICCR = 0xffffffff;\n\n\t/* read the AIC_IVR and AIC_FVR */\n\ti = *AT91C_AIC_IVR;\n\ti = *AT91C_AIC_FVR;\n\n\t/* write the end of interrupt control register */\n\t*AT91C_AIC_EOICR\t= 0;\n\n\treturn 1;\n}\n\n\nstatic int AT91F_LoadBoot(void)\n{\n//\tvolatile unsigned int crc1 = 0, crc2 = 0;\n\tvolatile unsigned int SizeToDownload = 0x21400;\n\tvolatile unsigned int AddressToDownload = AT91C_BOOT_ADDR;\n\n#if 0\n\t/* Read vector 6 to extract size to load */\t\n\tif (read_dataflash(AT91C_BOOT_DATAFLASH_ADDR, 32,\n\t                   (char *)AddressToDownload) != AT91C_DATAFLASH_OK)\n\t{\n\t\tprintf(\"Bad Code Size\\n\");\n\t\treturn IMAGE_BAD_SIZE;\n\t}\n\t/* calculate the size to download */\n\tSizeToDownload = *(int *)(AddressToDownload + AT91C_OFFSET_VECT6);\n#endif\n\t\n//\tprintf(\"\\nLoad UBOOT from dataflash[%x] to SDRAM[%x]\\n\",\n//\t       AT91C_BOOT_DATAFLASH_ADDR, AT91C_BOOT_ADDR);\n\tif (read_dataflash(AT91C_BOOT_DATAFLASH_ADDR, SizeToDownload + 8,\n\t                   (char *)AddressToDownload) != AT91C_DATAFLASH_OK)\n\t{\n\t\tprintf(\"F DF RD\\n\");\n\t\treturn IMAGE_READ_FAILURE;\n\t}\n#if 0\n\tpAT91->CRC32((const unsigned char *)AT91C_BOOT_ADDR,\n\t             (unsigned int)SizeToDownload , (unsigned int *)&crc2);\n\tcrc1 = (int)(*(char *)(AddressToDownload + SizeToDownload)) +\n\t       (int)(*(char *)(AddressToDownload + SizeToDownload + 1) << 8) +\n\t       (int)(*(char *)(AddressToDownload + SizeToDownload + 2) << 16) +\n\t       (int)(*(char *)(AddressToDownload + SizeToDownload + 3) << 24);\n\n\t/* Restore the value of Vector 6 */\n\t*(int *)(AddressToDownload + AT91C_OFFSET_VECT6) =\n\t\t*(int *)(AddressToDownload + SizeToDownload + 4);\n\t\n\tif (crc1 != crc2) {\n\t\tprintf(\"DF CRC bad %x != %x\\n\",crc1,crc2);\n\t \treturn\tIMAGE_CRC_ERROR;\n\t}\n#endif\n\treturn SUCCESS;\n}\n\nstatic int AT91F_StartBoot(void)\n{\n\tint\tsts;\n\tif((sts = AT91F_LoadBoot()) != SUCCESS) return sts;\n//\tprintf(\"\\n\");\n//\tprintf(\"PLLA[180MHz], MCK[60Mhz] ==> Start UBOOT\\n\");\n\tif (AT91F_ResetRegisters())\n\t{\n\t\tprintf(\"Jump\");\n\t\tJump(AT91C_BOOT_ADDR);\n//\t\tLED_blink(0);\n\t}\n\treturn\tIMAGE_ERROR;\n}\n\n#if 0\nstatic void\tAT91F_RepeatedStartBoot(void)\n{\n\tint\ti;\n\tfor(i = 0; i < CRC_RETRIES; i++) {\n\t\tif(AT91F_StartBoot() != IMAGE_CRC_ERROR){\n//\t\t\tLED_blink(1);\n\t\t\treturn;\n\t\t}\n\t}\n\treturn;\n}\n#endif\n\n#define TRUE 1\n#define FALSE 0\n#define TRX_MAGIC 0x30524448  /* \"HDR0\" */\n#define TRX_VERSION 1\n\nstruct trx_header {\n\tunsigned int magic;\n\tunsigned int len;\n\tunsigned int crc32;\n\tunsigned int flag_version;\n\tunsigned int offsets[3];\n};\n\n#define AT91C_MCI_TIMEOUT 1000000\n\nextern AT91S_MciDevice MCI_Device;\nextern void AT91F_MCIDeviceWaitReady(unsigned int);\nextern int AT91F_MCI_ReadBlockSwab(AT91PS_MciDevice, int, unsigned int *, int);\n\nint Program_From_MCI(void)\n{\n  int i;\n  unsigned int Max_Read_DataBlock_Length;\n  int block = 0;\n  int buffer = AT91C_DOWNLOAD_BASE_ADDRESS;\n  int bufpos = AT91C_DOWNLOAD_BASE_ADDRESS;\n  int NbPage = 0;\n  struct trx_header *p;\n\n\tp = (struct trx_header *)bufpos;\n\n\tMax_Read_DataBlock_Length = MCI_Device.pMCI_DeviceFeatures->Max_Read_DataBlock_Length;\n\n\tAT91F_MCIDeviceWaitReady(AT91C_MCI_TIMEOUT);\n\n  AT91F_MCI_ReadBlockSwab(&MCI_Device, block*Max_Read_DataBlock_Length, (unsigned int *)bufpos, Max_Read_DataBlock_Length);\n\n  if (p->magic != TRX_MAGIC) {\n\t\tprintf(\"Inv IMG 0x%08x\\n\", p->magic);\n\t\treturn FALSE;\n\t\t}\n\n\tprintf(\"RDSD\");\n\tAT91C_BASE_PIOC->PIO_CODR = AT91C_PIO_PC7 | AT91C_PIO_PC15 | AT91C_PIO_PC8 | AT91C_PIO_PC14;\n\tfor (i=0; i<(p->len/512); i++) {\n\t\tAT91F_MCI_ReadBlockSwab(&MCI_Device, block*Max_Read_DataBlock_Length, (unsigned int *)bufpos, Max_Read_DataBlock_Length);\n\t\tblock++;\n\t\tbufpos += Max_Read_DataBlock_Length;\n\t\t}\n\n\tNbPage = 0;\n\ti = dataflash_info[0].Device.pages_number;\n\twhile(i >>= 1)\n\t\tNbPage++;\n\ti = ((p->offsets[1] - p->offsets[0])/ 512) + 1 + (NbPage << 13) + (dataflash_info[0].Device.pages_size << 17);\n\t*(int *)(buffer + p->offsets[0] + AT91C_OFFSET_VECT6) = i;\n\n\tprintf(\" WDFB\");\n\tAT91C_BASE_PIOC->PIO_CODR = AT91C_PIO_PC7 | AT91C_PIO_PC15 | AT91C_PIO_PC14;\n\tAT91C_BASE_PIOC->PIO_SODR = AT91C_PIO_PC8;\n\twrite_dataflash(0xc0000000, buffer + p->offsets[0], p->offsets[1] - p->offsets[0]);\n\tprintf(\" WUB\");\n\tAT91C_BASE_PIOC->PIO_CODR = AT91C_PIO_PC7 | AT91C_PIO_PC15;\n\tAT91C_BASE_PIOC->PIO_SODR = AT91C_PIO_PC8 | AT91C_PIO_PC14;\n\twrite_dataflash(0xc0008000, buffer + p->offsets[1], p->offsets[2] - p->offsets[1]);\n\tprintf(\" WKRFS\");\n\tAT91C_BASE_PIOC->PIO_CODR = AT91C_PIO_PC8 | AT91C_PIO_PC15;\n\tAT91C_BASE_PIOC->PIO_SODR = AT91C_PIO_PC7 | AT91C_PIO_PC14;\n\twrite_dataflash(0xc0042000, buffer + p->offsets[2], p->len - p->offsets[2]);\n\tAT91C_BASE_PIOC->PIO_CODR = AT91C_PIO_PC8 | AT91C_PIO_PC14;\n\tAT91C_BASE_PIOC->PIO_SODR = AT91C_PIO_PC7 | AT91C_PIO_PC15;\n\treturn TRUE;\n}\n\n//*----------------------------------------------------------------------------\n//* Function Name       : main\n//* Object              : Main function\n//* Input Parameters    : none\n//* Output Parameters   : True\n//*----------------------------------------------------------------------------\nint main(void)\n{\n#ifdef XMODEM\n\tAT91PS_Buffer  \t\tpXmBuffer;\n\tAT91PS_SvcComm \t\tpSvcXmodem;\n#endif\n\tAT91S_SvcTempo \t\tsvcBootTempo; \t // Link to a AT91S_Tempo object\n\tunsigned int\t\tix;\n\tvolatile unsigned int AddressToDownload, SizeToDownload;\t\n \tunsigned int DeviceAddress = 0;\n\tchar command = 0;\n#ifdef XMODEM\n\tvolatile int i = 0;\t\n\tunsigned int crc1 = 0, crc2 = 0;\n\tvolatile int device;\n\tint NbPage;\n#endif\n\tvolatile int Nb_Device = 0;\n\tint mci_present = 0;\n\n\tpAT91 = AT91C_ROM_BOOT_ADDRESS;\n\n\tif (!AT91F_SetPLL())\n\t{\n\t\tprintf(\"F SetPLL\");\n\t\twhile(1);\n\t}\n\n\tat91_init_uarts();\n\n\t/* Tempo Initialisation */\n\tpAT91->OpenCtlTempo(&ctlTempo, (void *) &(pAT91->SYSTIMER_DESC));\n\tctlTempo.CtlTempoStart((void *) &(pAT91->SYSTIMER_DESC));\n\t\n\t// Attach the tempo to a tempo controler\n\tctlTempo.CtlTempoCreate(&ctlTempo, &svcBootTempo);\n//\tLED_init();\n//\tLED_blink(2);\n\n#ifdef XMODEM\n\t/* Xmodem Initialisation */\n\tpXmBuffer = pAT91->OpenSBuffer(&sXmBuffer);\n\tpSvcXmodem = pAT91->OpenSvcXmodem(&svcXmodem,\n\t             (AT91PS_USART)AT91C_BASE_DBGU, &ctlTempo);\n\tpAT91->OpenPipe(&xmodemPipe, pSvcXmodem, pXmBuffer);\n#endif\n\n\t/* System Timer initialization */\n\tAT91F_AIC_ConfigureIt(\n\t\tAT91C_BASE_AIC,                        // AIC base address\n\t\tAT91C_ID_SYS,                          // System peripheral ID\n\t\tAT91C_AIC_PRIOR_HIGHEST,               // Max priority\n\t\tAT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE, // Level sensitive\n\t\tAT91F_ST_ASM_HANDLER\n\t);\n\t/* Enable ST interrupt */\n\tAT91F_AIC_EnableIt(AT91C_BASE_AIC, AT91C_ID_SYS);\n\n#ifndef PRODTEST\n\t/* Start tempo to start Boot in a delay of\n\t * AT91C_DELAY_TO_BOOT sec if no key pressed */\n\tsvcBootTempo.Start(&svcBootTempo, AT91C_DELAY_TO_BOOT,\n\t                   0, AT91F_StartBoot, NULL);\n#endif\n\n\twhile(1)\n\t{\n\t\twhile(command == 0)\n\t\t{\n\t\t\tAddressToDownload = AT91C_DOWNLOAD_BASE_ADDRESS;\n\t\t\tSizeToDownload = AT91C_DOWNLOAD_MAX_SIZE;\n\t\t\tDeviceAddress = 0;\n\t\t\t\n\t\t\t/* try to detect Dataflash */\n\t\t\tif (!Nb_Device)\n\t\t\t\tNb_Device = AT91F_DataflashInit();\t\t\t\t\n\t\t\t\t\t\t\t\n\t\t\tmci_present = AT91F_DisplayMenu();\n\n#ifdef PRODTEST\n\t\t\tif (mci_present) {\n\t\t\t\tif (Program_From_MCI())\n\t\t\t\t\tAT91F_StartBoot();\n\t\t\t}\n#endif\n\n\t\t\tmessage[0] = 0;\n\t\t\tAT91F_ReadLine (\"Enter: \", message);\n\n#ifndef PRODTEST\n\t\t\t/* stop tempo ==> stop autoboot */\n\t\t\tsvcBootTempo.Stop(&svcBootTempo);\n#endif\n\n\t\t\tcommand = message[0];\n\t\t\tfor(ix = 1; (message[ix] == ' ') && (ix < 12); ix++);\t// Skip some whitespace\n\t\t\t\t\n\t\t\tif(!AsciiToHex(&message[ix], &DeviceAddress) )\n\t\t\t\tDeviceAddress = 0;\t\t\t// Illegal DeviceAddress\n\t\t\t\t\n\t\t\tswitch(command)\n\t\t\t{\n#ifdef XMODEM\n\t\t\t\tcase '1':\n\t\t\t\tcase '2':\n\t\t\t\tcase '5':\n\t\t\t\t\tif(command == '1') {\n\t\t\t\t\t\tDeviceAddress = 0xC0000000;\n//\t\t\t\t\t\tprintf(\"Download DataflashBoot.bin to [0x%x]\\n\", DeviceAddress);\n\t\t\t\t\t} else if(command == '2') {\n\t\t\t\t\t\tDeviceAddress = AT91C_BOOT_DATAFLASH_ADDR;\n//\t\t\t\t\t\tprintf(\"Download u-boot.bin to [0x%x]\\n\", DeviceAddress);\n\t\t\t\t\t} else {\n//\t\t\t\t\t\tprintf(\"Download Dataflash to [0x%x]\\n\", DeviceAddress);\n\t\t\t\t\t}\n\t\t\t\t\tswitch(DeviceAddress & 0xFF000000)\n\t\t\t\t\t{\n\t\t\t\t\t\tcase CFG_DATAFLASH_LOGIC_ADDR_CS0:\n\t\t\t\t\t\t\tif (dataflash_info[0].id == 0){\n\t\t\t\t\t\t\t\tprintf(\"No DF\");\n\t\t\t\t\t\t\t\tAT91F_WaitKeyPressed();\n\t\t\t\t\t\t\t\tcommand = 0;\n\t\t\t\t\t\t\t}\n\n\t\t\t\t\t\t\tdevice = 0;\n\t\t\t\t\t\tbreak;\n\t\t\t\t\t\n\t\t\t\t\t\tcase CFG_DATAFLASH_LOGIC_ADDR_CS3:\n\t\t\t\t\t\t\tif (dataflash_info[1].id == 0){\n\t\t\t\t\t\t\t\tprintf(\"No DF\");\n\t\t\t\t\t\t\t\tAT91F_WaitKeyPressed();\n\t\t\t\t\t\t\t\tcommand = 0;\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\tdevice = 1;\n\t\t\t\t\t\tbreak;\n\t\t\t\t\t\n\t\t\t\t\t\tdefault:\n\t\t\t\t\t\t\tcommand = 0;\n\t\t\t\t\t\tbreak;\n\t\t\t\t\t}\n\t\t\t\tbreak;\n#endif\n\n\t\t\t\tcase '3':\n\t\t\t\t\tif (mci_present)\n\t\t\t\t\t\tProgram_From_MCI();\n\t\t\t\t\tcommand = 0;\n\t\t\t\t\tbreak;\n\n\t\t\t\tcase '4':\n\t\t\t\t\tAT91F_StartBoot();\n\t\t\t\t\tcommand = 0;\n\t\t\t\tbreak;\n\n#ifdef MEMDISP\n\t\t\t\tcase '6':\n\t\t\t\t\tdo \n\t\t\t\t\t{\n\t\t\t\t\t\tAT91F_MemoryDisplay(DeviceAddress, 256);\n\t\t\t\t\t\tAT91F_ReadLine (NULL, message);\n\t\t\t\t\t\tDeviceAddress += 0x100;\n\t\t\t\t\t}\n\t\t\t\t\twhile(message[0] == '\\0');\n\t\t\t\t\tcommand = 0;\n\t\t\t\tbreak;\n#endif\n\n\t\t\t\tcase '7':\n\t\t\t\t\tswitch(DeviceAddress & 0xFF000000)\n\t\t\t\t\t{\n\t\t\t\t\t\tcase CFG_DATAFLASH_LOGIC_ADDR_CS0:\n\t\t\t\t\t\t\tbreak;\n\t\t\t\t\t\tcase CFG_DATAFLASH_LOGIC_ADDR_CS3:\n\t\t\t\t\t\t\tbreak;\n\t\t\t\t\t\tdefault:\n\t\t\t\t\t\t\tcommand = 0;\n\t\t\t\t\t\t\tbreak;\n\t\t\t\t\t}\n\n\t\t\t\t\tif (command != 0) {\n\t\t\t\t\t\tAT91F_ReadLine (\"RDY ERA\\nSure?\",\n\t\t\t\t\t\t\t\tmessage);\n\t\t\t\t\t\tif(message[0] == 'Y' || message[0] == 'y') {\n\t\t\t\t\t\t\terase_dataflash(DeviceAddress & 0xFF000000);\n//\t\t\t\t\t\t\tprintf(\"Erase complete\\n\\n\");\n\t\t\t\t\t\t}\n//\t\t\t\t\t\telse\n//\t\t\t\t\t\t\tprintf(\"Erase aborted\\n\");\n\t\t\t\t\t}\n\t\t\t\t\tcommand = 0;\n\n\t\t\t\tbreak;\n\n\t\t\t\tdefault:\n\t\t\t\t\tcommand = 0;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n#ifdef XMODEM\n\t\tfor(i = 0; i <= AT91C_DOWNLOAD_MAX_SIZE; i++)\n\t\t\t*(unsigned char *)(AddressToDownload + i) = 0;\n\t\n\t\txmodemPipe.Read(&xmodemPipe, (char *)AddressToDownload,\n\t\t                SizeToDownload, XmodemProtocol, 0);\t\n\t\twhile(XmodemComplete !=1);\n\t\tSizeToDownload = (unsigned int)((svcXmodem.pData) -\n\t\t                 (unsigned int)AddressToDownload);\n\n\t\t/* Modification of vector 6 */\n\t\tif ((DeviceAddress == CFG_DATAFLASH_LOGIC_ADDR_CS0)) {\n\t\t\t// Vector 6 must be compliant to the BootRom description (ref Datasheet)\n\t   \t\tNbPage = 0;\n\t    \ti = dataflash_info[device].Device.pages_number;\n\t    \twhile(i >>= 1)\n\t    \t\tNbPage++;\n\t\t\ti = (SizeToDownload / 512)+1 + (NbPage << 13) +\n\t\t\t    (dataflash_info[device].Device.pages_size << 17); //+4 to add crc32\n\t\t    SizeToDownload = 512 * (i &0xFF);\n\t\t}\t\n\t\telse\n\t\t{\n\t\t\t/* Save the contents of vector 6 ==> will be restored \n\t\t\t * at boot time (AT91F_StartBoot) */\n\t\t\t*(int *)(AddressToDownload + SizeToDownload + 4) =\n\t\t\t\t*(int *)(AddressToDownload + AT91C_OFFSET_VECT6);\n\t\t\t/* Modify Vector 6 to contain the size of the\n\t\t\t * file to copy (Dataflash -> SDRAM)*/\n\t\t\ti = SizeToDownload;\t\n\t\t}\t\t\n\n\t\t*(int *)(AddressToDownload + AT91C_OFFSET_VECT6) = i;\n//\t\tprintf(\"\\nModification of Arm Vector 6 :%x\\n\", i);\n\t\t\t    \n//\t\tprintf(\"\\nWrite %d bytes in DataFlash [0x%x]\\n\",SizeToDownload, DeviceAddress);\n\t\tcrc1 = 0;\n\t\tpAT91->CRC32((const unsigned char *)AddressToDownload, SizeToDownload , &crc1);\n\n\t\t/* Add the crc32 at the end of the code */\n\t\t*(char *)(AddressToDownload + SizeToDownload)     = (char)(crc1 & 0x000000FF);\n\t\t*(char *)(AddressToDownload + SizeToDownload + 1) = (char)((crc1 & 0x0000FF00) >> 8);\n\t\t*(char *)(AddressToDownload + SizeToDownload + 2) = (char)((crc1 & 0x00FF0000) >> 16);\n\t\t*(char *)(AddressToDownload + SizeToDownload + 3) = (char)((crc1 & 0xFF000000) >> 24);\n\n\t\t/* write dataflash */\n\t\twrite_dataflash (DeviceAddress, AddressToDownload, (SizeToDownload + 8));\n\n\t\t/* clear the buffer before read */\n\t\tfor(i=0; i <= SizeToDownload; i++)\n\t\t\t*(unsigned char *)(AddressToDownload + i) = 0;\n\t\t\t\t\t\n\t\t/* Read dataflash to check the validity of the data */\n\t\tread_dataflash (DeviceAddress, (SizeToDownload + 4), (char *)(AddressToDownload));\n\n\t\tprintf(\"VFY: \");\t\n\t\tcrc2 = 0;\n\t\t\t\t\n\t\tpAT91->CRC32((const unsigned char *)AddressToDownload, SizeToDownload , &crc2);\n \t\tcrc1 = (int)(*(char *)(AddressToDownload + SizeToDownload))          +\n\t\t\t   (int)(*(char *)(AddressToDownload + SizeToDownload + 1) << 8) +\n\t\t\t   (int)(*(char *)(AddressToDownload + SizeToDownload + 2) << 16) +\n\t\t\t   (int)(*(char *)(AddressToDownload + SizeToDownload + 3) << 24);\n\n\t\tif (crc1 != crc2)\n\t\t \tprintf(\"ERR\");\n\t\telse\n\t\t \tprintf(\"OK\");\n\t\t \t\n \t\tcommand = 0;\n \t\tXmodemComplete = 0;\n\t\tAT91F_WaitKeyPressed();\n#endif\n \t}\n}\n\n"
  },
  {
    "path": "target/linux/at91/image/dfboot/src/main.h",
    "content": "//*----------------------------------------------------------------------------\n//*      ATMEL Microcontroller Software Support  -  ROUSSET  -\n//*----------------------------------------------------------------------------\n//* The software is delivered \"AS IS\" without warranty or condition of any\n//* kind, either express, implied or statutory. This includes without\n//* limitation any warranty or condition with respect to merchantability or\n//* fitness for any particular purpose, or against the infringements of\n//* intellectual property rights of others.\n//*----------------------------------------------------------------------------\n//* File Name           : main.h\n//* Object              :\n//*\n//* 1.0 27/03/03 HIi    : Creation\n//* 1.01 03/05/04 HIi   : AT9C_VERSION incremented to 1.01\n//* 1.02 15/06/04 HIi   : AT9C_VERSION incremented to 1.02 ==> \n//*                       Add crc32 to verify dataflash download\n//* 1.03 18/04/05 MLC   : AT91C_VERSION incremented to 1.03g\n//*\t\t\t  Repeat boot on CRC Failure\n//*\t\t\t  Change Page Size to 1056\n//*\t\t\t  Reduce SPI speed to 4 Mbit\n//*\t\t\t  Change U-Boot boot address to a 1056 byte page boundary\n//* 1.04 30/04/05 USA\t: AT91C_VERSION incremented to 1.04\n//* 1.05 07/08/06 USA\t: AT91C_VERSION incremented to 1.05\n//*\t\t\t  Will only support loading Dataflashboot.bin and U-Boot\n//*----------------------------------------------------------------------------\n\n#ifndef main_h\n#define main_h\n\n#include    \"embedded_services.h\"\n\n#define AT91C_DOWNLOAD_BASE_ADDRESS     0x20000000\n#define AT91C_DOWNLOAD_MAX_SIZE         0x00040000\n\n#define AT91C_OFFSET_VECT6              0x14        //* Offset for ARM vector 6\n\n#define AT91C_VERSION   \"VER 1.05\"\n\n\n// Global variables and functions definition\nextern unsigned int GetTickCount(void);\n#endif\n\n"
  },
  {
    "path": "target/linux/at91/image/dfboot/src/mci_device.c",
    "content": "//*----------------------------------------------------------------------------\n//*         ATMEL Microcontroller Software Support  -  ROUSSET  -\n//*----------------------------------------------------------------------------\n//* The software is delivered \"AS IS\" without warranty or condition of any\n//* kind, either express, implied or statutory. This includes without\n//* limitation any warranty or condition with respect to merchantability or\n//* fitness for any particular purpose, or against the infringements of\n//* intellectual property rights of others.\n//*----------------------------------------------------------------------------\n//* File Name           : mci_device.c\n//* Object              : TEST DataFlash Functions\n//* Creation            : FB   26/11/2002\n//*\n//*----------------------------------------------------------------------------\n\n#include <AT91C_MCI_Device.h>\n#include \"stdio.h\"\n\n#define AT91C_MCI_TIMEOUT\t\t\t1000000   /* For AT91F_MCIDeviceWaitReady */\n#define BUFFER_SIZE_MCI_DEVICE\t\t512\n#define MASTER_CLOCK\t\t\t\t60000000\n#define FALSE\t\t\t\t\t\t0\n#define TRUE\t\t\t\t\t\t1\n\n//* External Functions\nextern void AT91F_ASM_MCI_Handler(void);\n//* Global Variables\nAT91S_MciDeviceFeatures\t\t\tMCI_Device_Features;\nAT91S_MciDeviceDesc\t\t\t\tMCI_Device_Desc;\nAT91S_MciDevice\t\t\t\t\tMCI_Device;\n\n#undef ENABLE_WRITE\n#undef MMC\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_MCI_SendCommand\n//* \\brief Generic function to send a command to the MMC or SDCard\n//*----------------------------------------------------------------------------\nint AT91F_MCI_SendCommand (\n\tAT91PS_MciDevice pMCI_Device,\n\tunsigned int Cmd,\n\tunsigned int Arg)\n{\n\tunsigned int\terror,status;\n\t//unsigned int\ttick=0;\n\n    // Send the command\n    AT91C_BASE_MCI->MCI_ARGR = Arg;\n    AT91C_BASE_MCI->MCI_CMDR = Cmd;\n\n\t// wait for CMDRDY Status flag to read the response\n\tdo\n\t{\n\t\tstatus = AT91C_BASE_MCI->MCI_SR;\n\t\t//tick++;\n\t}\n\twhile( !(status & AT91C_MCI_CMDRDY) );//&& (tick<100) );\n\n    // Test error  ==> if crc error and response R3 ==> don't check error\n    error = (AT91C_BASE_MCI->MCI_SR) & AT91C_MCI_SR_ERROR;\n\tif(error != 0 )\n\t{\n\t\t// if the command is SEND_OP_COND the CRC error flag is always present (cf : R3 response)\n\t\tif ( (Cmd != AT91C_SDCARD_APP_OP_COND_CMD) && (Cmd != AT91C_MMC_SEND_OP_COND_CMD) )\n\t\t\treturn ((AT91C_BASE_MCI->MCI_SR) & AT91C_MCI_SR_ERROR);\n\t\telse\n\t\t{\n\t\t\tif (error != AT91C_MCI_RCRCE)\n\t\t\t\treturn ((AT91C_BASE_MCI->MCI_SR) & AT91C_MCI_SR_ERROR);\n\t\t}\n\t}\n    return AT91C_CMD_SEND_OK;\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_MCI_SDCard_SendAppCommand\n//* \\brief Specific function to send a specific command to the SDCard\n//*----------------------------------------------------------------------------\nint AT91F_MCI_SDCard_SendAppCommand (\n\tAT91PS_MciDevice pMCI_Device,\n\tunsigned int Cmd_App,\n\tunsigned int Arg\t)\n{\n\tunsigned int status;\n\t//unsigned int\ttick=0;\n\n\t// Send the CMD55 for application specific command\n    AT91C_BASE_MCI->MCI_ARGR = (pMCI_Device->pMCI_DeviceFeatures->Relative_Card_Address << 16 );\n    AT91C_BASE_MCI->MCI_CMDR = AT91C_APP_CMD;\n\n\t// wait for CMDRDY Status flag to read the response\n\tdo\n\t{\n\t\tstatus = AT91C_BASE_MCI->MCI_SR;\n\t\t//tick++;\n\t}\n\twhile( !(status & AT91C_MCI_CMDRDY) );//&& (tick<100) );\t\n\n    // if an error occurs\n    if (((AT91C_BASE_MCI->MCI_SR) & AT91C_MCI_SR_ERROR) != 0 )\n\t\treturn ((AT91C_BASE_MCI->MCI_SR) & AT91C_MCI_SR_ERROR);\n\n    // check if it is a specific command and then send the command\n\tif ( (Cmd_App && AT91C_SDCARD_APP_ALL_CMD) == 0)\n\t\treturn AT91C_CMD_SEND_ERROR;\n\n   return( AT91F_MCI_SendCommand(pMCI_Device,Cmd_App,Arg) );\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_MCI_GetStatus\n//* \\brief Addressed card sends its status register\n//*----------------------------------------------------------------------------\nint AT91F_MCI_GetStatus(AT91PS_MciDevice pMCI_Device,unsigned int relative_card_address)\n{\n\tif (AT91F_MCI_SendCommand(pMCI_Device,\n\t\t\t\t\t\t\t\tAT91C_SEND_STATUS_CMD,\n\t\t\t\t\t\t\t\trelative_card_address <<16) == AT91C_CMD_SEND_OK)\n    \treturn (AT91C_BASE_MCI->MCI_RSPR[0]);\n\n    return AT91C_CMD_SEND_ERROR;\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_MCI_Device_Handler\n//* \\brief MCI C interrupt handler\n//*----------------------------------------------------------------------------\nvoid AT91F_MCI_Device_Handler(\n\tAT91PS_MciDevice pMCI_Device,\n\tunsigned int status)\n{\n\t// If End of Tx Buffer Empty interrupt occurred\n\tif ( status & AT91C_MCI_TXBUFE )\n    {\n\t\tAT91C_BASE_MCI->MCI_IDR = AT91C_MCI_TXBUFE;\n \t\tAT91C_BASE_PDC_MCI->PDC_PTCR = AT91C_PDC_TXTDIS;\n        \t\n\t\tpMCI_Device->pMCI_DeviceDesc->state = AT91C_MCI_IDLE;\n\t}\t// End of if AT91C_MCI_TXBUFF\t\t\n\t\n    // If End of Rx Buffer Full interrupt occurred\n    if ( status & AT91C_MCI_RXBUFF )\n    {        \n       \tAT91C_BASE_MCI->MCI_IDR = AT91C_MCI_RXBUFF;\n \t\tAT91C_BASE_PDC_MCI->PDC_PTCR = AT91C_PDC_RXTDIS;\n\t\n\t\tpMCI_Device->pMCI_DeviceDesc->state = AT91C_MCI_IDLE;\n\t}\t// End of if AT91C_MCI_RXBUFF\n\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_MCI_Handler\n//* \\brief MCI Handler\n//*----------------------------------------------------------------------------\nvoid AT91F_MCI_Handler(void)\n{\n\tint status;\n\n\tstatus = ( AT91C_BASE_MCI->MCI_SR & AT91C_BASE_MCI->MCI_IMR );\n\n\tAT91F_MCI_Device_Handler(&MCI_Device,status);\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_MCI_ReadBlock\n//* \\brief Read an ENTIRE block or PARTIAL block\n//*----------------------------------------------------------------------------\nint AT91F_MCI_ReadBlock(\n\tAT91PS_MciDevice pMCI_Device,\n\tint src,\n\tunsigned int *dataBuffer,\n\tint sizeToRead )\n{\n    ////////////////////////////////////////////////////////////////////////////////////////////\n    if(pMCI_Device->pMCI_DeviceDesc->state != AT91C_MCI_IDLE)\n    \treturn AT91C_READ_ERROR;\n    \n    if( (AT91F_MCI_GetStatus(pMCI_Device,pMCI_Device->pMCI_DeviceFeatures->Relative_Card_Address) & AT91C_SR_READY_FOR_DATA) != AT91C_SR_READY_FOR_DATA)\n    \treturn AT91C_READ_ERROR;\n    \t\n    if ( (src + sizeToRead) > pMCI_Device->pMCI_DeviceFeatures->Memory_Capacity )\n\t\treturn AT91C_READ_ERROR;\n\n    // If source does not fit a begin of a block\n\tif ( (src % pMCI_Device->pMCI_DeviceFeatures->Max_Read_DataBlock_Length) != 0 )\n\t\treturn AT91C_READ_ERROR;\n   \n     // Test if the MMC supports Partial Read Block\n     // ALWAYS SUPPORTED IN SD Memory Card\n     if( (sizeToRead < pMCI_Device->pMCI_DeviceFeatures->Max_Read_DataBlock_Length) \n    \t&& (pMCI_Device->pMCI_DeviceFeatures->Read_Partial == 0x00) )\n   \t\treturn AT91C_READ_ERROR;\n   \t\t\n    if( sizeToRead > pMCI_Device->pMCI_DeviceFeatures->Max_Read_DataBlock_Length)\n   \t\treturn AT91C_READ_ERROR;\n    ////////////////////////////////////////////////////////////////////////////////////////////\n      \n    // Init Mode Register\n\tAT91C_BASE_MCI->MCI_MR |= ((pMCI_Device->pMCI_DeviceFeatures->Max_Read_DataBlock_Length << 16) | AT91C_MCI_PDCMODE);\n\t \n    if (sizeToRead %4)\n\t\tsizeToRead = (sizeToRead /4)+1;\n\telse\n\t\tsizeToRead = sizeToRead/4;\n\n\tAT91C_BASE_PDC_MCI->PDC_PTCR = (AT91C_PDC_TXTDIS | AT91C_PDC_RXTDIS);\n    AT91C_BASE_PDC_MCI->PDC_RPR  = (unsigned int)dataBuffer;\n    AT91C_BASE_PDC_MCI->PDC_RCR  = sizeToRead;\n\n\t// Send the Read single block command\n    if ( AT91F_MCI_SendCommand(pMCI_Device, AT91C_READ_SINGLE_BLOCK_CMD, src) != AT91C_CMD_SEND_OK )\n    \treturn AT91C_READ_ERROR;\n\n\tpMCI_Device->pMCI_DeviceDesc->state = AT91C_MCI_RX_SINGLE_BLOCK;\n\n\t// Enable AT91C_MCI_RXBUFF Interrupt\n    AT91C_BASE_MCI->MCI_IER = AT91C_MCI_RXBUFF;\n\n\t// (PDC) Receiver Transfer Enable\n\tAT91C_BASE_PDC_MCI->PDC_PTCR = AT91C_PDC_RXTEN;\n\t\n\treturn AT91C_READ_OK;\n}\n\n\n#ifdef ENABLE_WRITE\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_MCI_WriteBlock\n//* \\brief  Write an ENTIRE block but not always PARTIAL block !!!\n//*----------------------------------------------------------------------------\nint AT91F_MCI_WriteBlock(\n\tAT91PS_MciDevice pMCI_Device,\n\tint dest,\n\tunsigned int *dataBuffer,\n\tint sizeToWrite )\n{\n    ////////////////////////////////////////////////////////////////////////////////////////////\n\tif( pMCI_Device->pMCI_DeviceDesc->state != AT91C_MCI_IDLE)\n    \treturn AT91C_WRITE_ERROR;\n    \n    if( (AT91F_MCI_GetStatus(pMCI_Device,pMCI_Device->pMCI_DeviceFeatures->Relative_Card_Address) & AT91C_SR_READY_FOR_DATA) != AT91C_SR_READY_FOR_DATA)\n    \treturn AT91C_WRITE_ERROR;\n    \t\n    if ( (dest + sizeToWrite) > pMCI_Device->pMCI_DeviceFeatures->Memory_Capacity )\n\t\treturn AT91C_WRITE_ERROR;\n\n    // If source does not fit a begin of a block\n\tif ( (dest % pMCI_Device->pMCI_DeviceFeatures->Max_Read_DataBlock_Length) != 0 )\n\t\treturn AT91C_WRITE_ERROR;\n   \n    // Test if the MMC supports Partial Write Block \n    if( (sizeToWrite < pMCI_Device->pMCI_DeviceFeatures->Max_Write_DataBlock_Length) \n    \t&& (pMCI_Device->pMCI_DeviceFeatures->Write_Partial == 0x00) )\n   \t\treturn AT91C_WRITE_ERROR;\n   \t\t\n   \tif( sizeToWrite > pMCI_Device->pMCI_DeviceFeatures->Max_Write_DataBlock_Length )\n   \t\treturn AT91C_WRITE_ERROR;\n    ////////////////////////////////////////////////////////////////////////////////////////////\n  \n    // Init Mode Register\n\tAT91C_BASE_MCI->MCI_MR |= ((pMCI_Device->pMCI_DeviceFeatures->Max_Write_DataBlock_Length << 16) | AT91C_MCI_PDCMODE);\n\t\n\tif (sizeToWrite %4)\n\t\tsizeToWrite = (sizeToWrite /4)+1;\n\telse\n\t\tsizeToWrite = sizeToWrite/4;\n\n\t// Init PDC for write sequence\n    AT91C_BASE_PDC_MCI->PDC_PTCR = (AT91C_PDC_TXTDIS | AT91C_PDC_RXTDIS);\n    AT91C_BASE_PDC_MCI->PDC_TPR = (unsigned int) dataBuffer;\n    AT91C_BASE_PDC_MCI->PDC_TCR = sizeToWrite;\n\n\t// Send the write single block command\n    if ( AT91F_MCI_SendCommand(pMCI_Device, AT91C_WRITE_BLOCK_CMD, dest) != AT91C_CMD_SEND_OK)\n    \treturn AT91C_WRITE_ERROR;\n\n\tpMCI_Device->pMCI_DeviceDesc->state = AT91C_MCI_TX_SINGLE_BLOCK;\n\n\t// Enable AT91C_MCI_TXBUFE Interrupt\n    AT91C_BASE_MCI->MCI_IER = AT91C_MCI_TXBUFE;\n  \n  \t// Enables TX for PDC transfert requests\n    AT91C_BASE_PDC_MCI->PDC_PTCR = AT91C_PDC_TXTEN;\n  \n\treturn AT91C_WRITE_OK;\n}\n#endif\n\n#ifdef MMC\n//*------------------------------------------------------------------------------------------------------------\n//* \\fn    AT91F_MCI_MMC_SelectCard\n//* \\brief Toggles a card between the Stand_by and Transfer states or between Programming and Disconnect states\n//*------------------------------------------------------------------------------------------------------------\nint AT91F_MCI_MMC_SelectCard(AT91PS_MciDevice pMCI_Device, unsigned int relative_card_address)\n{\n    int status;\n\t\n\t//* Check if the MMC card chosen is already the selected one\n\tstatus = AT91F_MCI_GetStatus(pMCI_Device,relative_card_address);\n\n\tif (status < 0)\n\t\treturn AT91C_CARD_SELECTED_ERROR;\n\n\tif ((status & AT91C_SR_CARD_SELECTED) == AT91C_SR_CARD_SELECTED)\n\t\treturn AT91C_CARD_SELECTED_OK;\n\n\t//* Search for the MMC Card to be selected, status = the Corresponding Device Number\n\tstatus = 0;\n\twhile( (pMCI_Device->pMCI_DeviceFeatures[status].Relative_Card_Address != relative_card_address)\n\t\t   && (status < AT91C_MAX_MCI_CARDS) )\n\t\tstatus++;\n\n\tif (status > AT91C_MAX_MCI_CARDS)\n    \treturn AT91C_CARD_SELECTED_ERROR;\n\n    if (AT91F_MCI_SendCommand( pMCI_Device,\n    \t\t\t\t\t\t\t\t   AT91C_SEL_DESEL_CARD_CMD,\n    \t\t\t\t\t\t\t\t   pMCI_Device->pMCI_DeviceFeatures[status].Relative_Card_Address << 16) == AT91C_CMD_SEND_OK)\n    \treturn AT91C_CARD_SELECTED_OK;\n    return AT91C_CARD_SELECTED_ERROR;\n}\n#endif\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_MCI_GetCSD\n//* \\brief Asks to the specified card to send its CSD\n//*----------------------------------------------------------------------------\nint AT91F_MCI_GetCSD (AT91PS_MciDevice pMCI_Device, unsigned int relative_card_address , unsigned int * response)\n{\n \t\n \tif(AT91F_MCI_SendCommand(pMCI_Device,\n\t\t\t\t\t\t\t\t  AT91C_SEND_CSD_CMD,\n\t\t\t\t\t\t\t\t  (relative_card_address << 16)) != AT91C_CMD_SEND_OK)\n\t\treturn AT91C_CMD_SEND_ERROR;\n\t\n    response[0] = AT91C_BASE_MCI->MCI_RSPR[0];\n   \tresponse[1] = AT91C_BASE_MCI->MCI_RSPR[1];\n    response[2] = AT91C_BASE_MCI->MCI_RSPR[2];\n    response[3] = AT91C_BASE_MCI->MCI_RSPR[3];\n    \n    return AT91C_CMD_SEND_OK;\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_MCI_SetBlocklength\n//* \\brief Select a block length for all following block commands (R/W)\n//*----------------------------------------------------------------------------\nint AT91F_MCI_SetBlocklength(AT91PS_MciDevice pMCI_Device,unsigned int length)\n{\n    return( AT91F_MCI_SendCommand(pMCI_Device, AT91C_SET_BLOCKLEN_CMD, length) );\n}\n\n#ifdef MMC\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_MCI_MMC_GetAllOCR\n//* \\brief Asks to all cards to send their operations conditions\n//*----------------------------------------------------------------------------\nint AT91F_MCI_MMC_GetAllOCR (AT91PS_MciDevice pMCI_Device)\n{\n\tunsigned int\tresponse =0x0;\n \t\n \twhile(1)\n    {\n    \tresponse = AT91F_MCI_SendCommand(pMCI_Device,\n  \t\t\t\t\t\t\t\t\t\tAT91C_MMC_SEND_OP_COND_CMD,\n  \t\t\t\t\t\t\t\t\t\tAT91C_MMC_HOST_VOLTAGE_RANGE);\n\t\tif (response != AT91C_CMD_SEND_OK)\n\t\t\treturn AT91C_INIT_ERROR;\n\t\t\n\t\tresponse = AT91C_BASE_MCI->MCI_RSPR[0];\n\t\t\n\t\tif ( (response & AT91C_CARD_POWER_UP_BUSY) == AT91C_CARD_POWER_UP_BUSY)\n\t\t\treturn(response);\t\n\t}\n}\n#endif\n\n#ifdef MMC\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_MCI_MMC_GetAllCID\n//* \\brief Asks to the MMC on the chosen slot to send its CID\n//*----------------------------------------------------------------------------\nint AT91F_MCI_MMC_GetAllCID (AT91PS_MciDevice pMCI_Device, unsigned int *response)\n{\n\tint Nb_Cards_Found=-1;\n  \n\twhile(1)\n\t{\n\t \tif(AT91F_MCI_SendCommand(pMCI_Device,\n\t\t\t\t\t\t\t\tAT91C_MMC_ALL_SEND_CID_CMD,\n\t\t\t\t\t\t\t\tAT91C_NO_ARGUMENT) != AT91C_CMD_SEND_OK)\n\t\t\treturn Nb_Cards_Found;\n\t\telse\n\t\t{\t\t\n\t\t\tNb_Cards_Found = 0;\n\t\t\t//* Assignation of the relative address to the MMC CARD\n\t\t\tpMCI_Device->pMCI_DeviceFeatures[Nb_Cards_Found].Relative_Card_Address = Nb_Cards_Found + AT91C_FIRST_RCA;\n\t\t\t//* Set the insert flag\n\t\t\tpMCI_Device->pMCI_DeviceFeatures[Nb_Cards_Found].Card_Inserted = AT91C_MMC_CARD_INSERTED;\n\t\n\t\t\tif (AT91F_MCI_SendCommand(pMCI_Device,\n\t\t\t\t\t\t\t\t\t AT91C_MMC_SET_RELATIVE_ADDR_CMD,\n\t\t\t\t\t\t\t\t\t (Nb_Cards_Found + AT91C_FIRST_RCA) << 16) != AT91C_CMD_SEND_OK)\n\t\t\t\treturn AT91C_CMD_SEND_ERROR;\n\t\t\t\t \n\t\t\t//* If no error during assignation address ==> Increment Nb_cards_Found\n\t\t\tNb_Cards_Found++ ;\n\t\t}\n\t}\n}\n#endif\n#ifdef MMC\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_MCI_MMC_Init\n//* \\brief Return the MMC initialisation status\n//*----------------------------------------------------------------------------\nint AT91F_MCI_MMC_Init (AT91PS_MciDevice pMCI_Device)\n{\n    unsigned int\ttab_response[4];\n\tunsigned int\tmult,blocknr;\n\tunsigned int \ti,Nb_Cards_Found=0;\n\n\t//* Resets all MMC Cards in Idle state\n\tAT91F_MCI_SendCommand(pMCI_Device, AT91C_MMC_GO_IDLE_STATE_CMD, AT91C_NO_ARGUMENT);\n\n    if(AT91F_MCI_MMC_GetAllOCR(pMCI_Device) == AT91C_INIT_ERROR)\n    \treturn AT91C_INIT_ERROR;\n\n\tNb_Cards_Found = AT91F_MCI_MMC_GetAllCID(pMCI_Device,tab_response);\n\tif (Nb_Cards_Found != AT91C_CMD_SEND_ERROR)\n\t{\n\t    //* Set the Mode Register\n    \tAT91C_BASE_MCI->MCI_MR = AT91C_MCI_MR_PDCMODE;\n\n\t\tfor(i = 0; i < Nb_Cards_Found; i++)\n\t\t{\n\t\t\tif (AT91F_MCI_GetCSD(pMCI_Device,\n\t\t\t\t\t\t\t\t\t  pMCI_Device->pMCI_DeviceFeatures[i].Relative_Card_Address,\n\t\t\t\t\t\t\t\t\t  tab_response) != AT91C_CMD_SEND_OK)\n\t\t\t\tpMCI_Device->pMCI_DeviceFeatures[i].Relative_Card_Address = 0;\t\t\t\t\t  \n\t\t\telse\n\t\t\t{\n\t\t\t\tpMCI_Device->pMCI_DeviceFeatures[i].Max_Read_DataBlock_Length = 1 << ((tab_response[1] >> AT91C_CSD_RD_B_LEN_S) & AT91C_CSD_RD_B_LEN_M );\n\t \t\t\tpMCI_Device->pMCI_DeviceFeatures[i].Max_Write_DataBlock_Length =\t1 << ((tab_response[3] >> AT91C_CSD_WBLEN_S) & AT91C_CSD_WBLEN_M );\n\t\t\t\tpMCI_Device->pMCI_DeviceFeatures[i].Sector_Size = 1 + ((tab_response[2] >> AT91C_CSD_v22_SECT_SIZE_S) & AT91C_CSD_v22_SECT_SIZE_M );\n\t\t  \t\tpMCI_Device->pMCI_DeviceFeatures[i].Read_Partial = (tab_response[1] >> AT91C_CSD_RD_B_PAR_S) & AT91C_CSD_RD_B_PAR_M;\n\t\t\t\tpMCI_Device->pMCI_DeviceFeatures[i].Write_Partial = (tab_response[3] >> AT91C_CSD_WBLOCK_P_S) & AT91C_CSD_WBLOCK_P_M;\n\t\t\t\t\n\t\t\t\t// None in MMC specification version 2.2\n\t\t\t\tpMCI_Device->pMCI_DeviceFeatures[i].Erase_Block_Enable = 0;\n\t\t\t\t\n\t\t\t\tpMCI_Device->pMCI_DeviceFeatures[i].Read_Block_Misalignment = (tab_response[1] >> AT91C_CSD_RD_B_MIS_S) & AT91C_CSD_RD_B_MIS_M;\n\t\t\t\tpMCI_Device->pMCI_DeviceFeatures[i].Write_Block_Misalignment = (tab_response[1] >> AT91C_CSD_WR_B_MIS_S) & AT91C_CSD_WR_B_MIS_M;\n\n\t\t\t\t//// Compute Memory Capacity\n\t\t\t\t// compute MULT\n\t\t\t\tmult = 1 << ( ((tab_response[2] >> AT91C_CSD_C_SIZE_M_S) & AT91C_CSD_C_SIZE_M_M) + 2 );\n\t\t\t\t// compute MSB of C_SIZE\n\t\t\t\tblocknr = ((tab_response[1] >> AT91C_CSD_CSIZE_H_S) & AT91C_CSD_CSIZE_H_M) << 2;\n\t\t\t\t// compute MULT * (LSB of C-SIZE + MSB already computed + 1) = BLOCKNR\n\t\t\t\tblocknr = mult * ( ( blocknr + ( (tab_response[2] >> AT91C_CSD_CSIZE_L_S) & AT91C_CSD_CSIZE_L_M) ) + 1 );\n\n\t\t\t\tpMCI_Device->pMCI_DeviceFeatures[i].Memory_Capacity =  pMCI_Device->pMCI_DeviceFeatures[i].Max_Read_DataBlock_Length * blocknr;\n\t\t  \t\t//// End of Compute Memory Capacity\n\t\t  \t\t\n\t\t\t}\t// end of else\t\t\t  \n\t\t}\t// end of for\n\t\t\n\t\treturn AT91C_INIT_OK;\n\t}\t// end of if\n\n    return AT91C_INIT_ERROR;\n}\n#endif\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_MCI_SDCard_GetOCR\n//* \\brief Asks to all cards to send their operations conditions\n//*----------------------------------------------------------------------------\nint AT91F_MCI_SDCard_GetOCR (AT91PS_MciDevice pMCI_Device)\n{\n\tunsigned int\tresponse =0x0;\n\n\t// The RCA to be used for CMD55 in Idle state shall be the card's default RCA=0x0000.\n\tpMCI_Device->pMCI_DeviceFeatures->Relative_Card_Address = 0x0;\n \t\n \twhile( (response & AT91C_CARD_POWER_UP_BUSY) != AT91C_CARD_POWER_UP_BUSY )\n    {\n    \tresponse = AT91F_MCI_SDCard_SendAppCommand(pMCI_Device,\n  \t\t\t\t\t\t\t\t\t\tAT91C_SDCARD_APP_OP_COND_CMD,\n  \t\t\t\t\t\t\t\t\t\tAT91C_MMC_HOST_VOLTAGE_RANGE);\n\t\tif (response != AT91C_CMD_SEND_OK)\n\t\t\treturn AT91C_INIT_ERROR;\n\t\t\n\t\tresponse = AT91C_BASE_MCI->MCI_RSPR[0];\n\t}\n\t\n\treturn(AT91C_BASE_MCI->MCI_RSPR[0]);\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_MCI_SDCard_GetCID\n//* \\brief Asks to the SDCard on the chosen slot to send its CID\n//*----------------------------------------------------------------------------\nint AT91F_MCI_SDCard_GetCID (AT91PS_MciDevice pMCI_Device, unsigned int *response)\n{\n \tif(AT91F_MCI_SendCommand(pMCI_Device,\n\t\t\t\t\t\t\tAT91C_ALL_SEND_CID_CMD,\n\t\t\t\t\t\t\tAT91C_NO_ARGUMENT) != AT91C_CMD_SEND_OK)\n\t\treturn AT91C_CMD_SEND_ERROR;\n\t\n    response[0] = AT91C_BASE_MCI->MCI_RSPR[0];\n   \tresponse[1] = AT91C_BASE_MCI->MCI_RSPR[1];\n    response[2] = AT91C_BASE_MCI->MCI_RSPR[2];\n    response[3] = AT91C_BASE_MCI->MCI_RSPR[3];\n    \n    return AT91C_CMD_SEND_OK;\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_MCI_SDCard_SetBusWidth\n//* \\brief  Set bus width for SDCard\n//*----------------------------------------------------------------------------\nint AT91F_MCI_SDCard_SetBusWidth(AT91PS_MciDevice pMCI_Device)\n{\n\tvolatile int\tret_value;\n\tchar\t\t\tbus_width;\n\n\tdo\n\t{\n\t\tret_value =AT91F_MCI_GetStatus(pMCI_Device,pMCI_Device->pMCI_DeviceFeatures->Relative_Card_Address);\n\t}\n\twhile((ret_value > 0) && ((ret_value & AT91C_SR_READY_FOR_DATA) == 0));\n\n\t// Select Card\n    AT91F_MCI_SendCommand(pMCI_Device,\n    \t\t\t\t\t\tAT91C_SEL_DESEL_CARD_CMD,\n    \t\t\t\t\t\t(pMCI_Device->pMCI_DeviceFeatures->Relative_Card_Address)<<16);\n\n\t// Set bus width for Sdcard\n\tif(pMCI_Device->pMCI_DeviceDesc->SDCard_bus_width == AT91C_MCI_SCDBUS)\n\t\t \tbus_width = AT91C_BUS_WIDTH_4BITS;\n\telse\tbus_width = AT91C_BUS_WIDTH_1BIT;\n\n\tif (AT91F_MCI_SDCard_SendAppCommand(pMCI_Device,AT91C_SDCARD_SET_BUS_WIDTH_CMD,bus_width) != AT91C_CMD_SEND_OK)\n\t\treturn AT91C_CMD_SEND_ERROR;\n\n\treturn AT91C_CMD_SEND_OK;\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_MCI_SDCard_Init\n//* \\brief Return the SDCard initialisation status\n//*----------------------------------------------------------------------------\nint AT91F_MCI_SDCard_Init (AT91PS_MciDevice pMCI_Device)\n{\n    unsigned int\ttab_response[4];\n\tunsigned int\tmult,blocknr;\n\n\tAT91F_MCI_SendCommand(pMCI_Device, AT91C_GO_IDLE_STATE_CMD, AT91C_NO_ARGUMENT);\n\n    if(AT91F_MCI_SDCard_GetOCR(pMCI_Device) == AT91C_INIT_ERROR)\n    \treturn AT91C_INIT_ERROR;\n\n\tif (AT91F_MCI_SDCard_GetCID(pMCI_Device,tab_response) == AT91C_CMD_SEND_OK)\n\t{\n\t    pMCI_Device->pMCI_DeviceFeatures->Card_Inserted = AT91C_SD_CARD_INSERTED;\n\n\t    if (AT91F_MCI_SendCommand(pMCI_Device, AT91C_SET_RELATIVE_ADDR_CMD, 0) == AT91C_CMD_SEND_OK)\n\t\t{\n\t\t\tpMCI_Device->pMCI_DeviceFeatures->Relative_Card_Address = (AT91C_BASE_MCI->MCI_RSPR[0] >> 16);\n\t\t\tif (AT91F_MCI_GetCSD(pMCI_Device,pMCI_Device->pMCI_DeviceFeatures->Relative_Card_Address,tab_response) == AT91C_CMD_SEND_OK)\n\t\t\t{\n\t\t  \t\tpMCI_Device->pMCI_DeviceFeatures->Max_Read_DataBlock_Length = 1 << ((tab_response[1] >> AT91C_CSD_RD_B_LEN_S) & AT91C_CSD_RD_B_LEN_M );\n\t \t\t\tpMCI_Device->pMCI_DeviceFeatures->Max_Write_DataBlock_Length =\t1 << ((tab_response[3] >> AT91C_CSD_WBLEN_S) & AT91C_CSD_WBLEN_M );\n\t\t\t\tpMCI_Device->pMCI_DeviceFeatures->Sector_Size = 1 + ((tab_response[2] >> AT91C_CSD_v21_SECT_SIZE_S) & AT91C_CSD_v21_SECT_SIZE_M );\n\t\t  \t\tpMCI_Device->pMCI_DeviceFeatures->Read_Partial = (tab_response[1] >> AT91C_CSD_RD_B_PAR_S) & AT91C_CSD_RD_B_PAR_M;\n\t\t\t\tpMCI_Device->pMCI_DeviceFeatures->Write_Partial = (tab_response[3] >> AT91C_CSD_WBLOCK_P_S) & AT91C_CSD_WBLOCK_P_M;\n\t\t\t\tpMCI_Device->pMCI_DeviceFeatures->Erase_Block_Enable = (tab_response[3] >> AT91C_CSD_v21_ER_BLEN_EN_S) & AT91C_CSD_v21_ER_BLEN_EN_M;\n\t\t\t\tpMCI_Device->pMCI_DeviceFeatures->Read_Block_Misalignment = (tab_response[1] >> AT91C_CSD_RD_B_MIS_S) & AT91C_CSD_RD_B_MIS_M;\n\t\t\t\tpMCI_Device->pMCI_DeviceFeatures->Write_Block_Misalignment = (tab_response[1] >> AT91C_CSD_WR_B_MIS_S) & AT91C_CSD_WR_B_MIS_M;\n\n\t\t\t\t//// Compute Memory Capacity\n\t\t\t\t\t// compute MULT\n\t\t\t\t\tmult = 1 << ( ((tab_response[2] >> AT91C_CSD_C_SIZE_M_S) & AT91C_CSD_C_SIZE_M_M) + 2 );\n\t\t\t\t\t// compute MSB of C_SIZE\n\t\t\t\t\tblocknr = ((tab_response[1] >> AT91C_CSD_CSIZE_H_S) & AT91C_CSD_CSIZE_H_M) << 2;\n\t\t\t\t\t// compute MULT * (LSB of C-SIZE + MSB already computed + 1) = BLOCKNR\n\t\t\t\t\tblocknr = mult * ( ( blocknr + ( (tab_response[2] >> AT91C_CSD_CSIZE_L_S) & AT91C_CSD_CSIZE_L_M) ) + 1 );\n\n\t\t\t\t\tpMCI_Device->pMCI_DeviceFeatures->Memory_Capacity =  pMCI_Device->pMCI_DeviceFeatures->Max_Read_DataBlock_Length * blocknr;\n\t\t\t  \t//// End of Compute Memory Capacity\n\t\t\t\t\tprintf(\"SD-Card: %d Bytes\\n\\r\", pMCI_Device->pMCI_DeviceFeatures->Memory_Capacity);\n\n\t\t  \t\tif( AT91F_MCI_SDCard_SetBusWidth(pMCI_Device) == AT91C_CMD_SEND_OK )\n\t\t\t\t{\t\n\t\t\t\t\t if (AT91F_MCI_SetBlocklength(pMCI_Device,pMCI_Device->pMCI_DeviceFeatures->Max_Read_DataBlock_Length) == AT91C_CMD_SEND_OK)\n\t\t\t\t\treturn AT91C_INIT_OK;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n    return AT91C_INIT_ERROR;\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_CfgDevice\n//* \\brief This function is used to initialise MMC or SDCard Features\n//*----------------------------------------------------------------------------\nvoid AT91F_CfgDevice(void)\n{\n\t// Init Device Structure\n\n\tMCI_Device_Features.Relative_Card_Address \t\t= 0;\n\tMCI_Device_Features.Card_Inserted \t\t\t\t= AT91C_CARD_REMOVED;\n\tMCI_Device_Features.Max_Read_DataBlock_Length\t= 0;\n\tMCI_Device_Features.Max_Write_DataBlock_Length \t= 0;\n\tMCI_Device_Features.Read_Partial \t\t\t\t= 0;\n\tMCI_Device_Features.Write_Partial \t\t\t\t= 0;\n\tMCI_Device_Features.Erase_Block_Enable \t\t\t= 0;\n\tMCI_Device_Features.Sector_Size \t\t\t\t= 0;\n\tMCI_Device_Features.Memory_Capacity \t\t\t= 0;\n\t\n\tMCI_Device_Desc.state\t\t\t\t\t\t\t= AT91C_MCI_IDLE;\n\tMCI_Device_Desc.SDCard_bus_width\t\t\t\t= AT91C_MCI_SCDBUS;\n\t\n\t// Init AT91S_DataFlash Global Structure, by default AT45DB choosen !!!\n\tMCI_Device.pMCI_DeviceDesc \t\t= &MCI_Device_Desc;\n\tMCI_Device.pMCI_DeviceFeatures \t= &MCI_Device_Features;\n\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_MCI_Init\n//* \\brief Initialsise Card\n//*----------------------------------------------------------------------------\nint AT91F_MCI_Init(void)\n{\n\n///////////////////////////////////////////////////////////////////////////////////////////\n//  MCI Init : common to MMC and SDCard\n///////////////////////////////////////////////////////////////////////////////////////////\n\n    // Set up PIO SDC_TYPE to switch on MMC/SDCard and not DataFlash Card\n\tAT91F_PIO_CfgOutput(AT91C_BASE_PIOB,AT91C_PIO_PB7);\n\tAT91F_PIO_SetOutput(AT91C_BASE_PIOB,AT91C_PIO_PB7);\n\t\n\t// Init MCI for MMC and SDCard interface\n\tAT91F_MCI_CfgPIO();\t\n\tAT91F_MCI_CfgPMC();\n\tAT91F_PDC_Open(AT91C_BASE_PDC_MCI);\n\n    // Disable all the interrupts\n    AT91C_BASE_MCI->MCI_IDR = 0xFFFFFFFF;\n\n\t// Init MCI Device Structures\n\tAT91F_CfgDevice();\n\n\t// Configure MCI interrupt \n\tAT91F_AIC_ConfigureIt(AT91C_BASE_AIC,\n\t\t\t\t\t\t AT91C_ID_MCI,\n\t\t\t\t\t\t AT91C_AIC_PRIOR_HIGHEST,\n\t\t\t\t\t\t AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE,\n\t\t\t\t\t\t AT91F_ASM_MCI_Handler);\n\n\t// Enable MCI interrupt\n\tAT91F_AIC_EnableIt(AT91C_BASE_AIC,AT91C_ID_MCI);\n\n\t// Enable Receiver\n\tAT91F_US_EnableRx((AT91PS_USART) AT91C_BASE_DBGU);\n\n\tAT91F_MCI_Configure(AT91C_BASE_MCI,\n\t\t\t\t\t\tAT91C_MCI_DTOR_1MEGA_CYCLES,\n\t\t\t\t\t\tAT91C_MCI_MR_PDCMODE,\t\t\t// 15MHz for MCK = 60MHz (CLKDIV = 1)\n\t\t\t\t\t\tAT91C_MCI_SDCARD_4BITS_SLOTA);\n\t\n\tif(AT91F_MCI_SDCard_Init(&MCI_Device) != AT91C_INIT_OK)\n\t\treturn FALSE;\n\telse\n\t\treturn TRUE;\n\n}\n\n//*----------------------------------------------------------------------------\n//* \\fn    AT91F_MCIDeviceWaitReady\n//* \\brief Wait for MCI Device ready\n//*----------------------------------------------------------------------------\nvoid AT91F_MCIDeviceWaitReady(unsigned int timeout)\n{\n\tvolatile int status;\n\t\n\tdo\n\t{\n\t\tstatus = AT91C_BASE_MCI->MCI_SR;\n\t\ttimeout--;\n\t}\n\twhile( !(status & AT91C_MCI_NOTBUSY)  && (timeout>0) );\t\n}\n\nunsigned int swab32(unsigned int data)\n{\n\tunsigned int res = 0;\n\n\tres = (data & 0x000000ff) << 24 |\n\t\t\t\t(data & 0x0000ff00) << 8  |\n\t\t\t\t(data & 0x00ff0000) >> 8  |\n\t\t\t\t(data & 0xff000000) >> 24;\n\n\treturn res;\n}\n\n//*--------------------------------------------------------------------\n//* \\fn    AT91F_MCI_ReadBlockSwab\n//* \\brief Read Block and swap byte order\n//*--------------------------------------------------------------------\nint AT91F_MCI_ReadBlockSwab(\n\tAT91PS_MciDevice pMCI_Device,\n\tint src,\n\tunsigned int *databuffer,\n\tint sizeToRead)\n{\n\tint i;\n\tunsigned char *buf = (unsigned char *)databuffer;\n\n\t//* Read Block 1\n\tfor(i=0;i<BUFFER_SIZE_MCI_DEVICE;i++)\n\t\t*buf++ = 0x00;\t\n\tAT91F_MCI_ReadBlock(&MCI_Device,src,databuffer,sizeToRead);\n\n\t//* Wait end of Read\n\tAT91F_MCIDeviceWaitReady(AT91C_MCI_TIMEOUT);\n\n\t{\n\t\tint index;\n\t\tunsigned int *uiBuffer = databuffer;\n\n\t\tfor(index = 0; index < 512/4; index++)\n\t\t\tuiBuffer[index] = swab32(uiBuffer[index]);\n\t}\n\treturn(1);\n}\n\n"
  },
  {
    "path": "target/linux/at91/image/dfboot/src/stdio.h",
    "content": "#include <stdarg.h>\n#include <stdbool.h>\n\n#ifndef NULL\n#define NULL ((void *)0)\n#endif\n\nvoid at91_init_uarts(void);\nint puts(const char *str);\nint putc(int c);\nint putchar(int c);\nint getc();\n\nint strlen(const char *str);\n\nint hvfprintf(const char *fmt, va_list ap);\n\nint printf(const char *fmt, ...);\n"
  },
  {
    "path": "target/linux/at91/image/gen_at91_sdcard_img.sh",
    "content": "#!/bin/sh\n# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2017 OpenWrt.org\n\nset -x\n[ $# -eq 5 ] || {\n    echo \"SYNTAX: $0 <file> <bootfs image> <rootfs image> <bootfs size> <rootfs size>\"\n    exit 1\n}\n\nOUTPUT=\"$1\"\nBOOTFS=\"$2\"\nROOTFS=\"$3\"\nBOOTFSSIZE=\"$4\"\nROOTFSSIZE=\"$5\"\n\nhead=4\nsect=2048\n\nset $(ptgen -o $OUTPUT -h $head -s $sect -l 1024 -t c -p ${BOOTFSSIZE}M -t 83 -p ${ROOTFSSIZE}M)\n\nBOOTOFFSET=\"$(($1 / 512))\"\nBOOTSIZE=\"$(($2 / 512))\"\nROOTFSOFFSET=\"$(($3 / 512))\"\nROOTFSSIZE=\"$(($4 / 512))\"\n\ndd bs=512 if=\"$BOOTFS\" of=\"$OUTPUT\" seek=\"$BOOTOFFSET\" conv=notrunc\ndd bs=512 if=\"$ROOTFS\" of=\"$OUTPUT\" seek=\"$ROOTFSOFFSET\" conv=notrunc\n"
  },
  {
    "path": "target/linux/at91/image/sam9x.mk",
    "content": "\ndefine Device/default-nand\n  BLOCKSIZE := 128k\n  PAGESIZE := 2048\n  SUBPAGESIZE := 512\n  MKUBIFS_OPTS := -m $$(PAGESIZE) -e 126KiB -c 2048\nendef\n\ndefine Build/at91-sdcard\n  $(if $(findstring ext4,$@), \\\n  rm -f $@.boot\n  mkfs.fat -C $@.boot $(FAT32_BLOCKS)\n\n  mcopy -i $@.boot \\\n\t$(KDIR)/$(DEVICE_NAME)-fit-zImage.itb \\\n\t::$(DEVICE_NAME)-fit.itb\n\n  mcopy -i $@.boot \\\n\t$(BIN_DIR)/u-boot-$(if $(findstring sam9x60,$@),$(DEVICE_DTS:at91-%=%),at91sam9x5ek)_mmc/u-boot.bin \\\n\t::u-boot.bin\n\n  mcopy -i $@.boot \\\n\t$(BIN_DIR)/at91bootstrap-$(if $(findstring sam9x60,$@),$(DEVICE_DTS:at91-%=%),at91sam9x5ek)sd_uboot/at91bootstrap.bin \\\n\t::BOOT.bin\n\n  $(CP) uboot-env.txt $@-uboot-env.txt\n  sed -i '2d;3d' $@-uboot-env.txt\n  sed -i '2i board='\"$(DEVICE_NAME)\"'' $@-uboot-env.txt\n  sed -i '3i board_name='\"$(firstword $(SUPPORTED_DEVICES))\"'' $@-uboot-env.txt\n\n  mkenvimage -s 0x4000 -o $@-uboot.env $@-uboot-env.txt\n\n  mcopy -i $@.boot $@-uboot.env ::uboot.env\n\n  ./gen_at91_sdcard_img.sh \\\n\t$@.img \\\n\t$@.boot \\\n\t$(KDIR)/root.ext4 \\\n\t$(AT91_SD_BOOT_PARTSIZE) \\\n\t$(CONFIG_TARGET_ROOTFS_PARTSIZE)\n\n  gzip -nc9 $@.img > $@\n\n  rm -f $@.img $@.boot $@-uboot.env $@-uboot-env.txt)\nendef\n\ndefine Device/atmel_at91sam9263ek\n  $(Device/evaluation-dtb)\n  DEVICE_VENDOR := Atmel\n  DEVICE_MODEL := AT91SAM9263-EK\nendef\nTARGET_DEVICES += atmel_at91sam9263ek\n\ndefine Device/atmel_at91sam9g15ek\n  $(Device/evaluation)\n  DEVICE_VENDOR := Atmel\n  DEVICE_MODEL := AT91SAM9G15-EK\nendef\nTARGET_DEVICES += atmel_at91sam9g15ek\n\ndefine Device/atmel_at91sam9g20ek\n  $(Device/evaluation-dtb)\n  DEVICE_VENDOR := Atmel\n  DEVICE_MODEL := AT91SAM9G20-EK\nendef\nTARGET_DEVICES += atmel_at91sam9g20ek\n\ndefine Device/atmel_at91sam9g20ek-2mmc\n  $(Device/evaluation-dtb)\n  DEVICE_VENDOR := Atmel\n  DEVICE_MODEL := AT91SAM9G20-EK\n  DEVICE_VARIANT := 2MMC\n  DEVICE_DTS := at91sam9g20ek_2mmc\n  SUPPORTED_DEVICES := atmel,at91sam9g20ek_2mmc\nendef\nTARGET_DEVICES += atmel_at91sam9g20ek-2mmc\n\ndefine Device/atmel_at91sam9g25ek\n  $(Device/evaluation)\n  DEVICE_VENDOR := Atmel\n  DEVICE_MODEL := AT91SAM9G25-EK\nendef\nTARGET_DEVICES += atmel_at91sam9g25ek\n\ndefine Device/atmel_at91sam9g35ek\n  $(Device/evaluation)\n  DEVICE_VENDOR := Atmel\n  DEVICE_MODEL := AT91SAM9G35-EK\nendef\nTARGET_DEVICES += atmel_at91sam9g35ek\n\ndefine Device/atmel_at91sam9m10g45ek\n  $(Device/evaluation)\n  DEVICE_VENDOR := Atmel\n  DEVICE_MODEL := AT91SAM9M10G45-EK\nendef\nTARGET_DEVICES += atmel_at91sam9m10g45ek\n\ndefine Device/atmel_at91sam9x25ek\n  $(Device/evaluation-dtb)\n  DEVICE_VENDOR := Atmel\n  DEVICE_MODEL := AT91SAM9X25-EK\n  $(Device/evaluation-sdimage)\nendef\nTARGET_DEVICES += atmel_at91sam9x25ek\n\ndefine Device/atmel_at91sam9x35ek\n  $(Device/evaluation-dtb)\n  DEVICE_VENDOR := Atmel\n  DEVICE_MODEL := AT91SAM9X35-EK\n  $(Device/evaluation-sdimage)\nendef\nTARGET_DEVICES += atmel_at91sam9x35ek\n\ndefine Device/microchip_sam9x60ek\n  $(Device/evaluation-dtb)\n  DEVICE_VENDOR := Microchip\n  DEVICE_MODEL := SAM9X60-EK\n  DEVICE_DTS := at91-sam9x60ek\n  $(Device/evaluation-sdimage)\nendef\nTARGET_DEVICES += microchip_sam9x60ek\n\ndefine Device/calamp_lmu5000\n  $(Device/production)\n  DEVICE_VENDOR := CalAmp\n  DEVICE_MODEL := LMU5000\n  DEVICE_PACKAGES := kmod-rtc-pcf2123 kmod-usb-acm \\\n\tkmod-usb-serial-option kmod-usb-serial-sierrawireless kmod-gpio-mcp23s08\nendef\nTARGET_DEVICES += calamp_lmu5000\n\ndefine Device/calao_tny-a9260\n  $(Device/production-dtb)\n  DEVICE_VENDOR := Calao\n  DEVICE_MODEL := TNY A9260\n  DEVICE_DTS := tny_a9260\nendef\nTARGET_DEVICES += calao_tny-a9260\n\ndefine Device/calao_tny-a9263\n  $(Device/production-dtb)\n  DEVICE_VENDOR := Calao\n  DEVICE_MODEL := TNY A9263\n  DEVICE_DTS := tny_a9263\n  SUPPORTED_DEVICES := atmel,tny-a9263\nendef\nTARGET_DEVICES += calao_tny-a9263\n\ndefine Device/calao_tny-a9g20\n  $(Device/production-dtb)\n  DEVICE_VENDOR := Calao\n  DEVICE_MODEL := TNY A9G20\n  DEVICE_DTS := tny_a9g20\nendef\nTARGET_DEVICES += calao_tny-a9g20\n\ndefine Device/calao_usb-a9260\n  $(Device/production-dtb)\n  DEVICE_VENDOR := Calao\n  DEVICE_MODEL := USB A9260\n  DEVICE_DTS := usb_a9260\nendef\nTARGET_DEVICES += calao_usb-a9260\n\ndefine Device/calao_usb-a9263\n  $(Device/production-dtb)\n  DEVICE_VENDOR := Calao\n  DEVICE_MODEL := USB A9263\n  DEVICE_DTS := usb_a9263\n  SUPPORTED_DEVICES := atmel,usb-a9263\nendef\nTARGET_DEVICES += calao_usb-a9263\n\ndefine Device/calao_usb-a9g20\n  $(Device/production-dtb)\n  DEVICE_VENDOR := Calao\n  DEVICE_MODEL := USB A9G20\n  DEVICE_DTS := usb_a9g20\nendef\nTARGET_DEVICES += calao_usb-a9g20\n\ndefine Device/egnite_ethernut5\n  $(Device/evaluation)\n  DEVICE_VENDOR := egnite\n  DEVICE_MODEL := Ethernut 5\n  UBINIZE_OPTS := -E 5\nendef\nTARGET_DEVICES += egnite_ethernut5\n\ndefine Device/exegin_q5xr5\n  $(Device/production-dtb)\n  DEVICE_VENDOR := Exegin\n  DEVICE_MODEL := Q5x\n  DEVICE_VARIANT := rev5\n  DEVICE_DTS := at91-q5xr5\n  KERNEL_SIZE := 2048k\n  DEFAULT := n\nendef\nTARGET_DEVICES += exegin_q5xr5\n\ndefine Device/laird_wb45n\n  $(Device/evaluation-fit)\n  DEVICE_VENDOR := Laird\n  DEVICE_MODEL := WB45N\n  DEVICE_DTS := at91-wb45n\n  DEVICE_PACKAGES := \\\n\tkmod-mmc-at91 kmod-ath6kl-sdio ath6k-firmware \\\n\tkmod-usb-storage kmod-fs-vfat kmod-fs-msdos \\\n\tkmod-leds-gpio\n  BLOCKSIZE := 128k\n  PAGESIZE := 2048\n  SUBPAGESIZE := 2048\n  MKUBIFS_OPTS := -m $$(PAGESIZE) -e 124KiB -c 955\nendef\nTARGET_DEVICES += laird_wb45n\n"
  },
  {
    "path": "target/linux/at91/image/sama5.mk",
    "content": "\ndefine Device/default-nand\n  BLOCKSIZE := 128k\n  PAGESIZE := 2048\n  SUBPAGESIZE := 2048\n  MKUBIFS_OPTS := -m $$(PAGESIZE) -e 124KiB -c 2048\nendef\n\ndefine Build/at91-sdcard\n  $(if $(findstring ext4,$@), \\\n  rm -f $@.boot\n  mkfs.fat -C $@.boot $(FAT32_BLOCKS)\n\n  mcopy -i $@.boot \\\n\t$(KDIR)/$(DEVICE_NAME)-fit-zImage.itb \\\n\t::$(DEVICE_NAME)-fit.itb\n\n  $(if $(findstring sama5d27-som1-ek,$@), \\\n      mcopy -i $@.boot \\\n          $(BIN_DIR)/u-boot-$(DEVICE_DTS:at91-%=%)_mmc1/u-boot.bin \\\n          ::u-boot.bin\n      mcopy -i $@.boot \\\n          $(BIN_DIR)/at91bootstrap-$(DEVICE_DTS:at91-%=%)sd1_uboot/at91bootstrap.bin \\\n          ::BOOT.bin,\n      mcopy -i $@.boot \\\n          $(BIN_DIR)/u-boot-$(DEVICE_DTS:at91-%=%)_mmc/u-boot.bin \\\n          ::u-boot.bin\n      $(if $(findstring sama5d4-xplained,$@), \\\n          mcopy -i $@.boot \\\n              $(BIN_DIR)/at91bootstrap-$(DEVICE_DTS:at91-%=%)sd_uboot_secure/at91bootstrap.bin \\\n              ::BOOT.bin,\n          mcopy -i $@.boot \\\n              $(BIN_DIR)/at91bootstrap-$(DEVICE_DTS:at91-%=%)sd_uboot/at91bootstrap.bin \\\n              ::BOOT.bin))\n\n  $(CP) uboot-env.txt $@-uboot-env.txt\n  sed -i '2d;3d' $@-uboot-env.txt\n  sed -i '2i board='\"$(DEVICE_NAME)\"'' $@-uboot-env.txt\n  sed -i '3i board_name='\"$(firstword $(SUPPORTED_DEVICES))\"'' $@-uboot-env.txt\n\n  mkenvimage -s 0x4000 -o $@-uboot.env $@-uboot-env.txt\n\n  mcopy -i $@.boot $@-uboot.env ::uboot.env\n\n  ./gen_at91_sdcard_img.sh \\\n\t$@.img \\\n\t$@.boot \\\n\t$(KDIR)/root.ext4 \\\n\t$(AT91_SD_BOOT_PARTSIZE) \\\n\t$(CONFIG_TARGET_ROOTFS_PARTSIZE)\n\n  gzip -nc9 $@.img > $@\n\n  rm -f $@.img $@.boot $@-uboot.env $@-uboot-env.txt)\nendef\n\ndefine Device/microchip_sama5d2-icp\n  $(Device/evaluation-dtb)\n  DEVICE_VENDOR := Microchip\n  DEVICE_MODEL := SAMA5D2 ICP\n  DEVICE_DTS := at91-sama5d2_icp\n  SUPPORTED_DEVICES := microchip,sama5d2-icp\n  KERNEL_SIZE := 6144k\n  $(Device/evaluation-sdimage)\nendef\nTARGET_DEVICES += microchip_sama5d2-icp\n\ndefine Device/microchip_sama5d2-xplained\n  $(Device/evaluation-dtb)\n  DEVICE_VENDOR := Microchip\n  DEVICE_MODEL := SAMA5D2 Xplained\n  DEVICE_DTS := at91-sama5d2_xplained\n  SUPPORTED_DEVICES := atmel,sama5d2-xplained\n  KERNEL_SIZE := 6144k\n  $(Device/evaluation-sdimage)\nendef\nTARGET_DEVICES += microchip_sama5d2-xplained\n\ndefine Device/microchip_sama5d27-som1-ek\n  $(Device/evaluation-dtb)\n  DEVICE_VENDOR := Microchip\n  DEVICE_MODEL := SAMA5D27 SOM1 Ek\n  DEVICE_DTS := at91-sama5d27_som1_ek\n  SUPPORTED_DEVICES := atmel,sama5d27-som1-ek\n  KERNEL_SIZE := 6144k\n  $(Device/evaluation-sdimage)\nendef\nTARGET_DEVICES += microchip_sama5d27-som1-ek\n\ndefine Device/microchip_sama5d27-wlsom1-ek\n  $(Device/evaluation-dtb)\n  DEVICE_VENDOR := Microchip\n  DEVICE_MODEL := SAMA5D27 WSOM1 Ek\n  DEVICE_DTS := at91-sama5d27_wlsom1_ek\n  SUPPORTED_DEVICES := microchip,sama5d27-wlsom1-ek\n  KERNEL_SIZE := 6144k\n  $(Device/evaluation-sdimage)\nendef\nTARGET_DEVICES += microchip_sama5d27-wlsom1-ek\n\ndefine Device/microchip_sama5d2-ptc-ek\n  $(Device/evaluation-dtb)\n  DEVICE_VENDOR := Microchip\n  DEVICE_MODEL := SAMA5D2 PTC Ek\n  DEVICE_DTS := at91-sama5d2_ptc_ek\n  SUPPORTED_DEVICES := atmel,sama5d2-ptc_ek\n  KERNEL_SIZE := 6144k\n  $(Device/evaluation-sdimage)\nendef\nTARGET_DEVICES += microchip_sama5d2-ptc-ek\n\ndefine Device/microchip_sama5d3-xplained\n  $(Device/evaluation-dtb)\n  DEVICE_VENDOR := Microchip\n  DEVICE_MODEL := SAMA5D3 Xplained\n  DEVICE_DTS := at91-sama5d3_xplained\n  SUPPORTED_DEVICES := atmel,sama5d3-xplained\n  KERNEL_SIZE := 6144k\n  $(Device/evaluation-sdimage)\nendef\nTARGET_DEVICES += microchip_sama5d3-xplained\n\nifeq ($(strip $(CONFIG_EXTERNAL_KERNEL_TREE)),\"\")\n ifeq ($(strip $(CONFIG_KERNEL_GIT_CLONE_URI)),\"\")\n  define Device/laird_wb50n\n    $(Device/evaluation-fit)\n    DEVICE_VENDOR := Laird\n    DEVICE_MODEL := WB50N\n    DEVICE_DTS := at91-wb50n\n    DEVICE_PACKAGES := \\\n\t  kmod-mmc-at91 kmod-ath6kl-sdio ath6k-firmware \\\n\t  kmod-usb-storage kmod-fs-vfat kmod-fs-msdos \\\n\t  kmod-leds-gpio\n    BLOCKSIZE := 128k\n    PAGESIZE := 2048\n    SUBPAGESIZE := 2048\n    MKUBIFS_OPTS := -m $$(PAGESIZE) -e 124KiB -c 955\n  endef\n  TARGET_DEVICES += laird_wb50n\n endif\nendif\n\ndefine Device/microchip_sama5d4-xplained\n  $(Device/evaluation-dtb)\n  DEVICE_VENDOR := Microchip\n  DEVICE_MODEL := SAMA5D4 Xplained\n  DEVICE_DTS := at91-sama5d4_xplained\n  SUPPORTED_DEVICES := atmel,sama5d4-xplained\n  KERNEL_SIZE := 6144k\n  BLOCKSIZE := 256k\n  PAGESIZE := 4096\n  SUBPAGESIZE := 2048\n  MKUBIFS_OPTS := -m $$(PAGESIZE) -e 248KiB -c 2082\n  $(Device/evaluation-sdimage)\nendef\nTARGET_DEVICES += microchip_sama5d4-xplained\n"
  },
  {
    "path": "target/linux/at91/image/sama7.mk",
    "content": "\ndefine Device/default-nand\n  BLOCKSIZE := 128k\n  PAGESIZE := 2048\n  SUBPAGESIZE := 2048\n  MKUBIFS_OPTS := -m $$(PAGESIZE) -e 124KiB -c 2048\nendef\n\ndefine Build/at91-sdcard\n  $(if $(findstring ext4,$@), \\\n  rm -f $@.boot\n  mkfs.fat -C $@.boot $(FAT32_BLOCKS)\n\n  mcopy -i $@.boot \\\n\t$(KDIR)/$(DEVICE_NAME)-fit-zImage.itb \\\n\t::$(DEVICE_NAME)-fit.itb\n\n  mcopy -i $@.boot \\\n\t$(BIN_DIR)/u-boot-$(DEVICE_DTS:at91-%=%)_mmc1/u-boot.bin \\\n\t::u-boot.bin\n\n  mcopy -i $@.boot \\\n\t$(BIN_DIR)/at91bootstrap-$(DEVICE_DTS:at91-%=%)sd_uboot/at91bootstrap.bin \\\n\t::BOOT.bin\n\n  $(CP) uboot-env.txt $@-uboot-env.txt\n  sed -i '2d;3d' $@-uboot-env.txt\n  sed -i '2i board='\"$(DEVICE_NAME)\"'' $@-uboot-env.txt\n  sed -i '3i board_name='\"$(firstword $(SUPPORTED_DEVICES))\"'' $@-uboot-env.txt\n\n  mkenvimage -s 0x4000 -o $@-uboot.env $@-uboot-env.txt\n\n  mcopy -i $@.boot $@-uboot.env ::uboot.env\n\n  ./gen_at91_sdcard_img.sh \\\n\t$@.img \\\n\t$@.boot \\\n\t$(KDIR)/root.ext4 \\\n\t$(AT91_SD_BOOT_PARTSIZE) \\\n\t$(CONFIG_TARGET_ROOTFS_PARTSIZE)\n\n  gzip -nc9 $@.img > $@\n\n  rm -f $@.img $@.boot $@-uboot.env $@-uboot-env.txt)\nendef\n\ndefine Device/microchip_sama7g5-ek\n  $(Device/evaluation-dtb)\n  DEVICE_VENDOR := Microchip\n  DEVICE_MODEL := SAMA7G5-EK\n  DEVICE_DTS := at91-sama7g5ek\n  SUPPORTED_DEVICES := microchip,sama7g5ek\n  KERNEL_SIZE := 6144k\n  KERNEL_LOADADDR := 0x62000000\n  $(Device/evaluation-sdimage)\nendef\nTARGET_DEVICES += microchip_sama7g5-ek\n"
  },
  {
    "path": "target/linux/at91/image/uboot-env.txt",
    "content": "/* Do Not remove First 2 lines, Makefile will modify these lines with proper board names */\nboard=atmel_at91sam9x25ek\nboard_name=atmel,at91sam9x25ek\nbootargs=console=ttyS0,115200 earlyprintk root=/dev/mmcblk0p2 rw rootwait rootfstype=ext4\nbootargsd2=console=ttyS0,115200 earlyprintk root=/dev/mmcblk1p2 rw rootwait rootfstype=ext4\nbootargsxx=console=ttyS0,115200 earlyprintk root=/dev/mmcblk0p2 rw rootwait rootfstype=ext4\nbootcmd=run setloadaddr; run setbootargs; run fatload_mmc; bootm ${loadaddr}\nbootdelay=1\nfatload_mmc=if test ${board_name} = atmel,sama5d2-xplained || test ${board_name} = atmel,sama5d27-som1-ek || test ${board_name} = microchip,sama7g5ek; then fatload mmc 1:1 ${loadaddr} ${board}-fit.itb; else fatload mmc 0:1 ${loadaddr} ${board}-fit.itb; fi\nsetbootargs=if test ${board_name} = atmel,sama5d2-xplained || test ${board_name} = atmel,sama5d27-som1-ek || test ${board_name} = microchip,sama7g5ek; then setenv bootargs ${bootargsd2}; else setenv bootargs ${bootargsxx}; fi\nsetloadaddr=if test ${board_name} = microchip,sama7g5ek; then setenv loadaddr 0x63000000; else setenv loadaddr 0x21000000; fi\nethact=gmac0\nstderr=serial\nstdin=serial\nstdout=serial\n"
  },
  {
    "path": "target/linux/at91/modules.mk",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2010 OpenWrt.org\n\ndefine KernelPackage/mmc-at91\n  SUBMENU:=$(OTHER_MENU)\n  TITLE:=MMC/SD Card Support on AT91\n  DEPENDS:=@TARGET_at91 +kmod-mmc\n  KCONFIG:=CONFIG_MMC_AT91\n  FILES:=$(LINUX_DIR)/drivers/mmc/host/at91_mci.ko\n  AUTOLOAD:=$(call AutoLoad,90,at91_mci,1)\nendef\n\ndefine KernelPackage/mmc-at91/description\n Kernel support for MMC/SD cards on the AT91 target\nendef\n\n$(eval $(call KernelPackage,mmc-at91))\n\ndefine KernelPackage/pwm-atmel\n  SUBMENU:=$(OTHER_MENU)\n  TITLE:=PWM on atmel SoC\n  DEPENDS:=@TARGET_at91\n  KCONFIG:=CONFIG_ATMEL_PWM\n  FILES:=$(LINUX_DIR)/drivers/misc/atmel_pwm.ko\n  AUTOLOAD:=$(call AutoLoad,51,atmel_pwm)\nendef\n\ndefine KernelPackage/pwm-atmel/description\n Kernel module to use the PWM channel on ATMEL SoC\nendef\n\n$(eval $(call KernelPackage,pwm-atmel))\n\ndefine KernelPackage/at91-adc\n  SUBMENU:=$(OTHER_MENU)\n  TITLE:=ADC on atmel SoC\n  DEPENDS:=@TARGET_at91 +kmod-iio-core +kmod-input-core\n  KCONFIG:=CONFIG_AT91_ADC\n  FILES:=$(LINUX_DIR)/drivers/iio/adc/at91_adc.ko\n  AUTOLOAD:=$(call AutoLoad,40,at91_adc)\nendef\n\ndefine KernelPackage/at91-adc/description\n Kernel module to use the ADC channels of SoC\nendef\n\n$(eval $(call KernelPackage,at91-adc))\n\ndefine KernelPackage/at91-udc\n  SUBMENU:=$(USB_MENU)\n  TITLE:=USB Device Controller on atmel SoC\n  DEPENDS:=@TARGET_at91 +kmod-usb-gadget +kmod-regmap-core\n  KCONFIG:=CONFIG_USB_AT91\nifneq ($(wildcard $(LINUX_DIR)/drivers/usb/gadget/udc/at91_udc.ko),)\n  FILES:=$(LINUX_DIR)/drivers/usb/gadget/udc/at91_udc.ko\nelse\n  FILES:=$(LINUX_DIR)/drivers/usb/gadget/at91_udc.ko\nendif\n  AUTOLOAD:=$(call AutoLoad,51,at91_udc)\nendef\n\ndefine KernelPackage/at91-udc/description\n Kernel module to use the USB Device controller for Atmel AT91\nendef\n\n$(eval $(call KernelPackage,at91-udc))\n\ndefine KernelPackage/atmel-usba-udc\n  SUBMENU:=$(USB_MENU)\n  TITLE:=High-speed USB Device Controller on atmel SoC\n  DEPENDS:=@TARGET_at91 +kmod-usb-gadget\n  KCONFIG:=CONFIG_USB_ATMEL_USBA\nifneq ($(wildcard $(LINUX_DIR)/drivers/usb/gadget/udc/atmel_usba_udc.ko),)\n  FILES:=$(LINUX_DIR)/drivers/usb/gadget/udc/atmel_usba_udc.ko\nelse\n  FILES:=$(LINUX_DIR)/drivers/usb/gadget/atmel_usba_udc.ko\nendif\n  AUTOLOAD:=$(call AutoLoad,51,atmel_usba_udc)\nendef\n\ndefine KernelPackage/atmel-usba-udc/description\n Kernel module to use the High-speed USB Device controller for Atmel AT91\nendef\n\n$(eval $(call KernelPackage,atmel-usba-udc))\n\nI2C_AT91_MODULES:=\\\n  CONFIG_I2C_AT91:drivers/i2c/busses/i2c-at91\n\ndefine KernelPackage/at91-i2c\n  $(call i2c_defaults,$(I2C_AT91_MODULES),55)\n  TITLE:=I2C (TWI) master driver for Atmel AT91\n  DEPENDS:=@TARGET_at91 +kmod-i2c-core\nendef\n\ndefine KernelPackage/at91-i2c/description\n Kernel module to use the I2C (TWI) master driver for Atmel AT91\nendef\n\n$(eval $(call KernelPackage,at91-i2c))\n\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/101-ARM-at91-build-dtb-for-q5xr5.patch",
    "content": "--- a/arch/arm/boot/dts/Makefile\n+++ b/arch/arm/boot/dts/Makefile\n@@ -41,6 +41,7 @@ dtb-$(CONFIG_SOC_AT91SAM9) += \\\n \tat91-kizboxmini-mb.dtb \\\n \tat91-kizboxmini-rd.dtb \\\n \tat91-smartkiz.dtb \\\n+\tat91-q5xr5.dtb \\\n \tat91-wb45n.dtb \\\n \tat91sam9g15ek.dtb \\\n \tat91sam9g25-gardena-smart-gateway.dtb \\\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/102-dt-bindings-clock-at91-add-sama7g5-pll-defines.patch",
    "content": "From 44bb7c72cdd830f54fe18e730205f892d9cbfe39 Mon Sep 17 00:00:00 2001\nFrom: Eugen Hristev <eugen.hristev@microchip.com>\nDate: Thu, 19 Nov 2020 17:43:08 +0200\nSubject: [PATCH 102/247] dt-bindings: clock: at91: add sama7g5 pll defines\n\nAdd SAMA7G5 specific PLL defines to be referenced in a phandle as a\nPMC_TYPE_CORE clock.\n\nSuggested-by: Claudiu Beznea <claudiu.beznea@microchip.com>\nSigned-off-by: Eugen Hristev <eugen.hristev@microchip.com>\n[claudiu.beznea@microchip.com: adapt comit message, adapt sama7g5.c]\nSigned-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>\nLink: https://lore.kernel.org/r/1605800597-16720-3-git-send-email-claudiu.beznea@microchip.com\nSigned-off-by: Stephen Boyd <sboyd@kernel.org>\n---\n drivers/clk/at91/sama7g5.c       |  6 +++---\n include/dt-bindings/clock/at91.h | 10 ++++++++++\n 2 files changed, 13 insertions(+), 3 deletions(-)\n\n--- a/drivers/clk/at91/sama7g5.c\n+++ b/drivers/clk/at91/sama7g5.c\n@@ -182,13 +182,13 @@ static const struct {\n \t\t  .p = \"audiopll_fracck\",\n \t\t  .l = &pll_layout_divpmc,\n \t\t  .t = PLL_TYPE_DIV,\n-\t\t  .eid = PMC_I2S0_MUX, },\n+\t\t  .eid = PMC_AUDIOPMCPLL, },\n \n \t\t{ .n = \"audiopll_diviock\",\n \t\t  .p = \"audiopll_fracck\",\n \t\t  .l = &pll_layout_divio,\n \t\t  .t = PLL_TYPE_DIV,\n-\t\t  .eid = PMC_I2S1_MUX, },\n+\t\t  .eid = PMC_AUDIOIOPLL, },\n \t},\n \n \t[PLL_ID_ETH] = {\n@@ -835,7 +835,7 @@ static void __init sama7g5_pmc_setup(str\n \tif (IS_ERR(regmap))\n \t\treturn;\n \n-\tsama7g5_pmc = pmc_data_allocate(PMC_I2S1_MUX + 1,\n+\tsama7g5_pmc = pmc_data_allocate(PMC_ETHPLL + 1,\n \t\t\t\t\tnck(sama7g5_systemck),\n \t\t\t\t\tnck(sama7g5_periphck),\n \t\t\t\t\tnck(sama7g5_gck), 8);\n--- a/include/dt-bindings/clock/at91.h\n+++ b/include/dt-bindings/clock/at91.h\n@@ -25,6 +25,16 @@\n #define PMC_PLLBCK\t\t8\n #define PMC_AUDIOPLLCK\t\t9\n \n+/* SAMA7G5 */\n+#define PMC_CPUPLL\t\t(PMC_MAIN + 1)\n+#define PMC_SYSPLL\t\t(PMC_MAIN + 2)\n+#define PMC_DDRPLL\t\t(PMC_MAIN + 3)\n+#define PMC_IMGPLL\t\t(PMC_MAIN + 4)\n+#define PMC_BAUDPLL\t\t(PMC_MAIN + 5)\n+#define PMC_AUDIOPMCPLL\t\t(PMC_MAIN + 6)\n+#define PMC_AUDIOIOPLL\t\t(PMC_MAIN + 7)\n+#define PMC_ETHPLL\t\t(PMC_MAIN + 8)\n+\n #ifndef AT91_PMC_MOSCS\n #define AT91_PMC_MOSCS\t\t0\t\t/* MOSCS Flag */\n #define AT91_PMC_LOCKA\t\t1\t\t/* PLLA Lock */\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/103-clk-at91-sama7g5-allow-SYS-and-CPU-PLLs-to-be-export.patch",
    "content": "From 55c14526f970805a6bf2ed4b820f062334375abe Mon Sep 17 00:00:00 2001\nFrom: Eugen Hristev <eugen.hristev@microchip.com>\nDate: Thu, 19 Nov 2020 17:43:09 +0200\nSubject: [PATCH 103/247] clk: at91: sama7g5: allow SYS and CPU PLLs to be\n exported and referenced in DT\n\nAllow SYSPLL and CPUPLL to be referenced as a PMC_TYPE_CORE clock\nfrom phandle in DT.\n\nSuggested-by: Claudiu Beznea <claudiu.beznea@microchip.com>\nSigned-off-by: Eugen Hristev <eugen.hristev@microchip.com>\n[claudiu.beznea@microchip.com: adapt commit message, add CPU PLL]\nSigned-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>\nLink: https://lore.kernel.org/r/1605800597-16720-4-git-send-email-claudiu.beznea@microchip.com\nSigned-off-by: Stephen Boyd <sboyd@kernel.org>\n---\n drivers/clk/at91/sama7g5.c | 6 ++++--\n 1 file changed, 4 insertions(+), 2 deletions(-)\n\n--- a/drivers/clk/at91/sama7g5.c\n+++ b/drivers/clk/at91/sama7g5.c\n@@ -117,7 +117,8 @@ static const struct {\n \t\t  .p = \"cpupll_fracck\",\n \t\t  .l = &pll_layout_divpmc,\n \t\t  .t = PLL_TYPE_DIV,\n-\t\t  .c = 1, },\n+\t\t  .c = 1,\n+\t\t  .eid = PMC_CPUPLL, },\n \t},\n \n \t[PLL_ID_SYS] = {\n@@ -131,7 +132,8 @@ static const struct {\n \t\t  .p = \"syspll_fracck\",\n \t\t  .l = &pll_layout_divpmc,\n \t\t  .t = PLL_TYPE_DIV,\n-\t\t  .c = 1, },\n+\t\t  .c = 1,\n+\t\t  .eid = PMC_SYSPLL, },\n \t},\n \n \t[PLL_ID_DDR] = {\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/104-clk-at91-clk-master-add-5th-divisor-for-mck-master.patch",
    "content": "From b2349278894bb381fa26a8717d3093d53f08fd36 Mon Sep 17 00:00:00 2001\nFrom: Eugen Hristev <eugen.hristev@microchip.com>\nDate: Thu, 19 Nov 2020 17:43:10 +0200\nSubject: [PATCH 104/247] clk: at91: clk-master: add 5th divisor for mck master\n\nclk-master can have 5 divisors with a field width of 3 bits\non some products.\n\nChange the mask and number of divisors accordingly.\n\nReported-by: Mihai Sain <mihai.sain@microchip.com>\nSigned-off-by: Eugen Hristev <eugen.hristev@microchip.com>\nSigned-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>\nLink: https://lore.kernel.org/r/1605800597-16720-5-git-send-email-claudiu.beznea@microchip.com\nSigned-off-by: Stephen Boyd <sboyd@kernel.org>\n---\n drivers/clk/at91/clk-master.c | 2 +-\n drivers/clk/at91/pmc.h        | 2 +-\n 2 files changed, 2 insertions(+), 2 deletions(-)\n\n--- a/drivers/clk/at91/clk-master.c\n+++ b/drivers/clk/at91/clk-master.c\n@@ -15,7 +15,7 @@\n #define MASTER_PRES_MASK\t0x7\n #define MASTER_PRES_MAX\t\tMASTER_PRES_MASK\n #define MASTER_DIV_SHIFT\t8\n-#define MASTER_DIV_MASK\t\t0x3\n+#define MASTER_DIV_MASK\t\t0x7\n \n #define PMC_MCR\t\t\t0x30\n #define PMC_MCR_ID_MSK\t\tGENMASK(3, 0)\n--- a/drivers/clk/at91/pmc.h\n+++ b/drivers/clk/at91/pmc.h\n@@ -48,7 +48,7 @@ extern const struct clk_master_layout at\n \n struct clk_master_characteristics {\n \tstruct clk_range output;\n-\tu32 divisors[4];\n+\tu32 divisors[5];\n \tu8 have_div3_pres;\n };\n \n"
  },
  {
    "path": "target/linux/at91/patches-5.10/105-clk-at91-sama7g5-add-5th-divisor-for-mck0-layout-and.patch",
    "content": "From c41f013e13962dcc78239d5e4834214d44556cfb Mon Sep 17 00:00:00 2001\nFrom: Eugen Hristev <eugen.hristev@microchip.com>\nDate: Thu, 19 Nov 2020 17:43:11 +0200\nSubject: [PATCH 105/247] clk: at91: sama7g5: add 5th divisor for mck0 layout\n and characteristics\n\nThis SoC has the 5th divisor for the mck0 master clock.\nAdapt the characteristics accordingly.\n\nReported-by: Mihai Sain <mihai.sain@microchip.com>\nSigned-off-by: Eugen Hristev <eugen.hristev@microchip.com>\nSigned-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>\nLink: https://lore.kernel.org/r/1605800597-16720-6-git-send-email-claudiu.beznea@microchip.com\nSigned-off-by: Stephen Boyd <sboyd@kernel.org>\n---\n drivers/clk/at91/sama7g5.c | 4 ++--\n 1 file changed, 2 insertions(+), 2 deletions(-)\n\n--- a/drivers/clk/at91/sama7g5.c\n+++ b/drivers/clk/at91/sama7g5.c\n@@ -775,13 +775,13 @@ static const struct clk_pll_characterist\n /* MCK0 characteristics. */\n static const struct clk_master_characteristics mck0_characteristics = {\n \t.output = { .min = 140000000, .max = 200000000 },\n-\t.divisors = { 1, 2, 4, 3 },\n+\t.divisors = { 1, 2, 4, 3, 5 },\n \t.have_div3_pres = 1,\n };\n \n /* MCK0 layout. */\n static const struct clk_master_layout mck0_layout = {\n-\t.mask = 0x373,\n+\t.mask = 0x773,\n \t.pres_shift = 4,\n \t.offset = 0x28,\n };\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/106-clk-at91-clk-sam9x60-pll-allow-runtime-changes-for-p.patch",
    "content": "From 6fe2927863de96edf35d8357712dbf83a489f556 Mon Sep 17 00:00:00 2001\nFrom: Claudiu Beznea <claudiu.beznea@microchip.com>\nDate: Thu, 19 Nov 2020 17:43:12 +0200\nSubject: [PATCH 106/247] clk: at91: clk-sam9x60-pll: allow runtime changes for\n pll\n\nAllow runtime frequency changes for PLLs registered with proper flags.\nThis is necessary for CPU PLL on SAMA7G5 which is used by DVFS.\n\nSigned-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>\nLink: https://lore.kernel.org/r/1605800597-16720-7-git-send-email-claudiu.beznea@microchip.com\nSigned-off-by: Stephen Boyd <sboyd@kernel.org>\n---\n drivers/clk/at91/clk-sam9x60-pll.c | 145 +++++++++++++++++++++++++----\n drivers/clk/at91/pmc.h             |   4 +-\n drivers/clk/at91/sam9x60.c         |  22 ++++-\n drivers/clk/at91/sama7g5.c         |  67 +++++++++----\n 4 files changed, 197 insertions(+), 41 deletions(-)\n\n--- a/drivers/clk/at91/clk-sam9x60-pll.c\n+++ b/drivers/clk/at91/clk-sam9x60-pll.c\n@@ -229,6 +229,57 @@ static int sam9x60_frac_pll_set_rate(str\n \treturn sam9x60_frac_pll_compute_mul_frac(core, rate, parent_rate, true);\n }\n \n+static int sam9x60_frac_pll_set_rate_chg(struct clk_hw *hw, unsigned long rate,\n+\t\t\t\t\t unsigned long parent_rate)\n+{\n+\tstruct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);\n+\tstruct sam9x60_frac *frac = to_sam9x60_frac(core);\n+\tstruct regmap *regmap = core->regmap;\n+\tunsigned long irqflags;\n+\tunsigned int val, cfrac, cmul;\n+\tlong ret;\n+\n+\tret = sam9x60_frac_pll_compute_mul_frac(core, rate, parent_rate, true);\n+\tif (ret <= 0)\n+\t\treturn ret;\n+\n+\tspin_lock_irqsave(core->lock, irqflags);\n+\n+\tregmap_update_bits(regmap, AT91_PMC_PLL_UPDT, AT91_PMC_PLL_UPDT_ID_MSK,\n+\t\t\t   core->id);\n+\tregmap_read(regmap, AT91_PMC_PLL_CTRL1, &val);\n+\tcmul = (val & core->layout->mul_mask) >> core->layout->mul_shift;\n+\tcfrac = (val & core->layout->frac_mask) >> core->layout->frac_shift;\n+\n+\tif (cmul == frac->mul && cfrac == frac->frac)\n+\t\tgoto unlock;\n+\n+\tregmap_write(regmap, AT91_PMC_PLL_CTRL1,\n+\t\t     (frac->mul << core->layout->mul_shift) |\n+\t\t     (frac->frac << core->layout->frac_shift));\n+\n+\tregmap_update_bits(regmap, AT91_PMC_PLL_UPDT,\n+\t\t\t   AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,\n+\t\t\t   AT91_PMC_PLL_UPDT_UPDATE | core->id);\n+\n+\tregmap_update_bits(regmap, AT91_PMC_PLL_CTRL0,\n+\t\t\t   AT91_PMC_PLL_CTRL0_ENLOCK | AT91_PMC_PLL_CTRL0_ENPLL,\n+\t\t\t   AT91_PMC_PLL_CTRL0_ENLOCK |\n+\t\t\t   AT91_PMC_PLL_CTRL0_ENPLL);\n+\n+\tregmap_update_bits(regmap, AT91_PMC_PLL_UPDT,\n+\t\t\t   AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,\n+\t\t\t   AT91_PMC_PLL_UPDT_UPDATE | core->id);\n+\n+\twhile (!sam9x60_pll_ready(regmap, core->id))\n+\t\tcpu_relax();\n+\n+unlock:\n+\tspin_unlock_irqrestore(core->lock, irqflags);\n+\n+\treturn ret;\n+}\n+\n static const struct clk_ops sam9x60_frac_pll_ops = {\n \t.prepare = sam9x60_frac_pll_prepare,\n \t.unprepare = sam9x60_frac_pll_unprepare,\n@@ -238,6 +289,15 @@ static const struct clk_ops sam9x60_frac\n \t.set_rate = sam9x60_frac_pll_set_rate,\n };\n \n+static const struct clk_ops sam9x60_frac_pll_ops_chg = {\n+\t.prepare = sam9x60_frac_pll_prepare,\n+\t.unprepare = sam9x60_frac_pll_unprepare,\n+\t.is_prepared = sam9x60_frac_pll_is_prepared,\n+\t.recalc_rate = sam9x60_frac_pll_recalc_rate,\n+\t.round_rate = sam9x60_frac_pll_round_rate,\n+\t.set_rate = sam9x60_frac_pll_set_rate_chg,\n+};\n+\n static int sam9x60_div_pll_prepare(struct clk_hw *hw)\n {\n \tstruct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);\n@@ -384,6 +444,44 @@ static int sam9x60_div_pll_set_rate(stru\n \treturn 0;\n }\n \n+static int sam9x60_div_pll_set_rate_chg(struct clk_hw *hw, unsigned long rate,\n+\t\t\t\t\tunsigned long parent_rate)\n+{\n+\tstruct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);\n+\tstruct sam9x60_div *div = to_sam9x60_div(core);\n+\tstruct regmap *regmap = core->regmap;\n+\tunsigned long irqflags;\n+\tunsigned int val, cdiv;\n+\n+\tdiv->div = DIV_ROUND_CLOSEST(parent_rate, rate) - 1;\n+\n+\tspin_lock_irqsave(core->lock, irqflags);\n+\tregmap_update_bits(regmap, AT91_PMC_PLL_UPDT, AT91_PMC_PLL_UPDT_ID_MSK,\n+\t\t\t   core->id);\n+\tregmap_read(regmap, AT91_PMC_PLL_CTRL0, &val);\n+\tcdiv = (val & core->layout->div_mask) >> core->layout->div_shift;\n+\n+\t/* Stop if nothing changed. */\n+\tif (cdiv == div->div)\n+\t\tgoto unlock;\n+\n+\tregmap_update_bits(regmap, AT91_PMC_PLL_CTRL0,\n+\t\t\t   core->layout->div_mask,\n+\t\t\t   (div->div << core->layout->div_shift));\n+\n+\tregmap_update_bits(regmap, AT91_PMC_PLL_UPDT,\n+\t\t\t   AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,\n+\t\t\t   AT91_PMC_PLL_UPDT_UPDATE | core->id);\n+\n+\twhile (!sam9x60_pll_ready(regmap, core->id))\n+\t\tcpu_relax();\n+\n+unlock:\n+\tspin_unlock_irqrestore(core->lock, irqflags);\n+\n+\treturn 0;\n+}\n+\n static const struct clk_ops sam9x60_div_pll_ops = {\n \t.prepare = sam9x60_div_pll_prepare,\n \t.unprepare = sam9x60_div_pll_unprepare,\n@@ -393,17 +491,26 @@ static const struct clk_ops sam9x60_div_\n \t.set_rate = sam9x60_div_pll_set_rate,\n };\n \n+static const struct clk_ops sam9x60_div_pll_ops_chg = {\n+\t.prepare = sam9x60_div_pll_prepare,\n+\t.unprepare = sam9x60_div_pll_unprepare,\n+\t.is_prepared = sam9x60_div_pll_is_prepared,\n+\t.recalc_rate = sam9x60_div_pll_recalc_rate,\n+\t.round_rate = sam9x60_div_pll_round_rate,\n+\t.set_rate = sam9x60_div_pll_set_rate_chg,\n+};\n+\n struct clk_hw * __init\n sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock,\n \t\t\t      const char *name, const char *parent_name,\n \t\t\t      struct clk_hw *parent_hw, u8 id,\n \t\t\t      const struct clk_pll_characteristics *characteristics,\n-\t\t\t      const struct clk_pll_layout *layout, bool critical)\n+\t\t\t      const struct clk_pll_layout *layout, u32 flags)\n {\n \tstruct sam9x60_frac *frac;\n \tstruct clk_hw *hw;\n \tstruct clk_init_data init;\n-\tunsigned long parent_rate, flags;\n+\tunsigned long parent_rate, irqflags;\n \tunsigned int val;\n \tint ret;\n \n@@ -417,10 +524,12 @@ sam9x60_clk_register_frac_pll(struct reg\n \tinit.name = name;\n \tinit.parent_names = &parent_name;\n \tinit.num_parents = 1;\n-\tinit.ops = &sam9x60_frac_pll_ops;\n-\tinit.flags = CLK_SET_RATE_GATE;\n-\tif (critical)\n-\t\tinit.flags |= CLK_IS_CRITICAL;\n+\tif (flags & CLK_SET_RATE_GATE)\n+\t\tinit.ops = &sam9x60_frac_pll_ops;\n+\telse\n+\t\tinit.ops = &sam9x60_frac_pll_ops_chg;\n+\n+\tinit.flags = flags;\n \n \tfrac->core.id = id;\n \tfrac->core.hw.init = &init;\n@@ -429,7 +538,7 @@ sam9x60_clk_register_frac_pll(struct reg\n \tfrac->core.regmap = regmap;\n \tfrac->core.lock = lock;\n \n-\tspin_lock_irqsave(frac->core.lock, flags);\n+\tspin_lock_irqsave(frac->core.lock, irqflags);\n \tif (sam9x60_pll_ready(regmap, id)) {\n \t\tregmap_update_bits(regmap, AT91_PMC_PLL_UPDT,\n \t\t\t\t   AT91_PMC_PLL_UPDT_ID_MSK, id);\n@@ -457,7 +566,7 @@ sam9x60_clk_register_frac_pll(struct reg\n \t\t\tgoto free;\n \t\t}\n \t}\n-\tspin_unlock_irqrestore(frac->core.lock, flags);\n+\tspin_unlock_irqrestore(frac->core.lock, irqflags);\n \n \thw = &frac->core.hw;\n \tret = clk_hw_register(NULL, hw);\n@@ -469,7 +578,7 @@ sam9x60_clk_register_frac_pll(struct reg\n \treturn hw;\n \n free:\n-\tspin_unlock_irqrestore(frac->core.lock, flags);\n+\tspin_unlock_irqrestore(frac->core.lock, irqflags);\n \tkfree(frac);\n \treturn hw;\n }\n@@ -478,12 +587,12 @@ struct clk_hw * __init\n sam9x60_clk_register_div_pll(struct regmap *regmap, spinlock_t *lock,\n \t\t\t     const char *name, const char *parent_name, u8 id,\n \t\t\t     const struct clk_pll_characteristics *characteristics,\n-\t\t\t     const struct clk_pll_layout *layout, bool critical)\n+\t\t\t     const struct clk_pll_layout *layout, u32 flags)\n {\n \tstruct sam9x60_div *div;\n \tstruct clk_hw *hw;\n \tstruct clk_init_data init;\n-\tunsigned long flags;\n+\tunsigned long irqflags;\n \tunsigned int val;\n \tint ret;\n \n@@ -497,11 +606,11 @@ sam9x60_clk_register_div_pll(struct regm\n \tinit.name = name;\n \tinit.parent_names = &parent_name;\n \tinit.num_parents = 1;\n-\tinit.ops = &sam9x60_div_pll_ops;\n-\tinit.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |\n-\t\t     CLK_SET_RATE_PARENT;\n-\tif (critical)\n-\t\tinit.flags |= CLK_IS_CRITICAL;\n+\tif (flags & CLK_SET_RATE_GATE)\n+\t\tinit.ops = &sam9x60_div_pll_ops;\n+\telse\n+\t\tinit.ops = &sam9x60_div_pll_ops_chg;\n+\tinit.flags = flags;\n \n \tdiv->core.id = id;\n \tdiv->core.hw.init = &init;\n@@ -510,14 +619,14 @@ sam9x60_clk_register_div_pll(struct regm\n \tdiv->core.regmap = regmap;\n \tdiv->core.lock = lock;\n \n-\tspin_lock_irqsave(div->core.lock, flags);\n+\tspin_lock_irqsave(div->core.lock, irqflags);\n \n \tregmap_update_bits(regmap, AT91_PMC_PLL_UPDT,\n \t\t\t   AT91_PMC_PLL_UPDT_ID_MSK, id);\n \tregmap_read(regmap, AT91_PMC_PLL_CTRL0, &val);\n \tdiv->div = FIELD_GET(PMC_PLL_CTRL0_DIV_MSK, val);\n \n-\tspin_unlock_irqrestore(div->core.lock, flags);\n+\tspin_unlock_irqrestore(div->core.lock, irqflags);\n \n \thw = &div->core.hw;\n \tret = clk_hw_register(NULL, hw);\n--- a/drivers/clk/at91/pmc.h\n+++ b/drivers/clk/at91/pmc.h\n@@ -190,14 +190,14 @@ struct clk_hw * __init\n sam9x60_clk_register_div_pll(struct regmap *regmap, spinlock_t *lock,\n \t\t\t     const char *name, const char *parent_name, u8 id,\n \t\t\t     const struct clk_pll_characteristics *characteristics,\n-\t\t\t     const struct clk_pll_layout *layout, bool critical);\n+\t\t\t     const struct clk_pll_layout *layout, u32 flags);\n \n struct clk_hw * __init\n sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock,\n \t\t\t      const char *name, const char *parent_name,\n \t\t\t      struct clk_hw *parent_hw, u8 id,\n \t\t\t      const struct clk_pll_characteristics *characteristics,\n-\t\t\t      const struct clk_pll_layout *layout, bool critical);\n+\t\t\t      const struct clk_pll_layout *layout, u32 flags);\n \n struct clk_hw * __init\n at91_clk_register_programmable(struct regmap *regmap, const char *name,\n--- a/drivers/clk/at91/sam9x60.c\n+++ b/drivers/clk/at91/sam9x60.c\n@@ -224,13 +224,24 @@ static void __init sam9x60_pmc_setup(str\n \thw = sam9x60_clk_register_frac_pll(regmap, &pmc_pll_lock, \"pllack_fracck\",\n \t\t\t\t\t   \"mainck\", sam9x60_pmc->chws[PMC_MAIN],\n \t\t\t\t\t   0, &plla_characteristics,\n-\t\t\t\t\t   &pll_frac_layout, true);\n+\t\t\t\t\t   &pll_frac_layout,\n+\t\t\t\t\t   /*\n+\t\t\t\t\t    * This feeds pllack_divck which\n+\t\t\t\t\t    * feeds CPU. It should not be\n+\t\t\t\t\t    * disabled.\n+\t\t\t\t\t    */\n+\t\t\t\t\t   CLK_IS_CRITICAL | CLK_SET_RATE_GATE);\n \tif (IS_ERR(hw))\n \t\tgoto err_free;\n \n \thw = sam9x60_clk_register_div_pll(regmap, &pmc_pll_lock, \"pllack_divck\",\n \t\t\t\t\t  \"pllack_fracck\", 0, &plla_characteristics,\n-\t\t\t\t\t  &pll_div_layout, true);\n+\t\t\t\t\t  &pll_div_layout,\n+\t\t\t\t\t   /*\n+\t\t\t\t\t    * This feeds CPU. It should not\n+\t\t\t\t\t    * be disabled.\n+\t\t\t\t\t    */\n+\t\t\t\t\t  CLK_IS_CRITICAL | CLK_SET_RATE_GATE);\n \tif (IS_ERR(hw))\n \t\tgoto err_free;\n \n@@ -239,13 +250,16 @@ static void __init sam9x60_pmc_setup(str\n \thw = sam9x60_clk_register_frac_pll(regmap, &pmc_pll_lock, \"upllck_fracck\",\n \t\t\t\t\t   \"main_osc\", main_osc_hw, 1,\n \t\t\t\t\t   &upll_characteristics,\n-\t\t\t\t\t   &pll_frac_layout, false);\n+\t\t\t\t\t   &pll_frac_layout, CLK_SET_RATE_GATE);\n \tif (IS_ERR(hw))\n \t\tgoto err_free;\n \n \thw = sam9x60_clk_register_div_pll(regmap, &pmc_pll_lock, \"upllck_divck\",\n \t\t\t\t\t  \"upllck_fracck\", 1, &upll_characteristics,\n-\t\t\t\t\t  &pll_div_layout, false);\n+\t\t\t\t\t  &pll_div_layout,\n+\t\t\t\t\t  CLK_SET_RATE_GATE |\n+\t\t\t\t\t  CLK_SET_PARENT_GATE |\n+\t\t\t\t\t  CLK_SET_RATE_PARENT);\n \tif (IS_ERR(hw))\n \t\tgoto err_free;\n \n--- a/drivers/clk/at91/sama7g5.c\n+++ b/drivers/clk/at91/sama7g5.c\n@@ -95,15 +95,15 @@ static const struct clk_pll_layout pll_l\n  * @p:\t\tclock parent\n  * @l:\t\tclock layout\n  * @t:\t\tclock type\n- * @f:\t\ttrue if clock is critical and cannot be disabled\n+ * @f:\t\tclock flags\n  * @eid:\texport index in sama7g5->chws[] array\n  */\n static const struct {\n \tconst char *n;\n \tconst char *p;\n \tconst struct clk_pll_layout *l;\n+\tunsigned long f;\n \tu8 t;\n-\tu8 c;\n \tu8 eid;\n } sama7g5_plls[][PLL_ID_MAX] = {\n \t[PLL_ID_CPU] = {\n@@ -111,13 +111,18 @@ static const struct {\n \t\t  .p = \"mainck\",\n \t\t  .l = &pll_layout_frac,\n \t\t  .t = PLL_TYPE_FRAC,\n-\t\t  .c = 1, },\n+\t\t   /*\n+\t\t    * This feeds cpupll_divpmcck which feeds CPU. It should\n+\t\t    * not be disabled.\n+\t\t    */\n+\t\t  .f = CLK_IS_CRITICAL, },\n \n \t\t{ .n = \"cpupll_divpmcck\",\n \t\t  .p = \"cpupll_fracck\",\n \t\t  .l = &pll_layout_divpmc,\n \t\t  .t = PLL_TYPE_DIV,\n-\t\t  .c = 1,\n+\t\t   /* This feeds CPU. It should not be disabled. */\n+\t\t  .f = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,\n \t\t  .eid = PMC_CPUPLL, },\n \t},\n \n@@ -126,13 +131,22 @@ static const struct {\n \t\t  .p = \"mainck\",\n \t\t  .l = &pll_layout_frac,\n \t\t  .t = PLL_TYPE_FRAC,\n-\t\t  .c = 1, },\n+\t\t   /*\n+\t\t    * This feeds syspll_divpmcck which may feed critial parts\n+\t\t    * of the systems like timers. Therefore it should not be\n+\t\t    * disabled.\n+\t\t    */\n+\t\t  .f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE, },\n \n \t\t{ .n = \"syspll_divpmcck\",\n \t\t  .p = \"syspll_fracck\",\n \t\t  .l = &pll_layout_divpmc,\n \t\t  .t = PLL_TYPE_DIV,\n-\t\t  .c = 1,\n+\t\t   /*\n+\t\t    * This may feed critial parts of the systems like timers.\n+\t\t    * Therefore it should not be disabled.\n+\t\t    */\n+\t\t  .f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE,\n \t\t  .eid = PMC_SYSPLL, },\n \t},\n \n@@ -141,55 +155,71 @@ static const struct {\n \t\t  .p = \"mainck\",\n \t\t  .l = &pll_layout_frac,\n \t\t  .t = PLL_TYPE_FRAC,\n-\t\t  .c = 1, },\n+\t\t   /*\n+\t\t    * This feeds ddrpll_divpmcck which feeds DDR. It should not\n+\t\t    * be disabled.\n+\t\t    */\n+\t\t  .f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE, },\n \n \t\t{ .n = \"ddrpll_divpmcck\",\n \t\t  .p = \"ddrpll_fracck\",\n \t\t  .l = &pll_layout_divpmc,\n \t\t  .t = PLL_TYPE_DIV,\n-\t\t  .c = 1, },\n+\t\t   /* This feeds DDR. It should not be disabled. */\n+\t\t  .f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE, },\n \t},\n \n \t[PLL_ID_IMG] = {\n \t\t{ .n = \"imgpll_fracck\",\n \t\t  .p = \"mainck\",\n \t\t  .l = &pll_layout_frac,\n-\t\t  .t = PLL_TYPE_FRAC, },\n+\t\t  .t = PLL_TYPE_FRAC,\n+\t\t  .f = CLK_SET_RATE_GATE, },\n \n \t\t{ .n = \"imgpll_divpmcck\",\n \t\t  .p = \"imgpll_fracck\",\n \t\t  .l = &pll_layout_divpmc,\n-\t\t  .t = PLL_TYPE_DIV, },\n+\t\t  .t = PLL_TYPE_DIV,\n+\t\t  .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |\n+\t\t       CLK_SET_RATE_PARENT, },\n \t},\n \n \t[PLL_ID_BAUD] = {\n \t\t{ .n = \"baudpll_fracck\",\n \t\t  .p = \"mainck\",\n \t\t  .l = &pll_layout_frac,\n-\t\t  .t = PLL_TYPE_FRAC, },\n+\t\t  .t = PLL_TYPE_FRAC,\n+\t\t  .f = CLK_SET_RATE_GATE, },\n \n \t\t{ .n = \"baudpll_divpmcck\",\n \t\t  .p = \"baudpll_fracck\",\n \t\t  .l = &pll_layout_divpmc,\n-\t\t  .t = PLL_TYPE_DIV, },\n+\t\t  .t = PLL_TYPE_DIV,\n+\t\t  .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |\n+\t\t       CLK_SET_RATE_PARENT, },\n \t},\n \n \t[PLL_ID_AUDIO] = {\n \t\t{ .n = \"audiopll_fracck\",\n \t\t  .p = \"main_xtal\",\n \t\t  .l = &pll_layout_frac,\n-\t\t  .t = PLL_TYPE_FRAC, },\n+\t\t  .t = PLL_TYPE_FRAC,\n+\t\t  .f = CLK_SET_RATE_GATE, },\n \n \t\t{ .n = \"audiopll_divpmcck\",\n \t\t  .p = \"audiopll_fracck\",\n \t\t  .l = &pll_layout_divpmc,\n \t\t  .t = PLL_TYPE_DIV,\n+\t\t  .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |\n+\t\t       CLK_SET_RATE_PARENT,\n \t\t  .eid = PMC_AUDIOPMCPLL, },\n \n \t\t{ .n = \"audiopll_diviock\",\n \t\t  .p = \"audiopll_fracck\",\n \t\t  .l = &pll_layout_divio,\n \t\t  .t = PLL_TYPE_DIV,\n+\t\t  .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |\n+\t\t       CLK_SET_RATE_PARENT,\n \t\t  .eid = PMC_AUDIOIOPLL, },\n \t},\n \n@@ -197,12 +227,15 @@ static const struct {\n \t\t{ .n = \"ethpll_fracck\",\n \t\t  .p = \"main_xtal\",\n \t\t  .l = &pll_layout_frac,\n-\t\t  .t = PLL_TYPE_FRAC, },\n+\t\t  .t = PLL_TYPE_FRAC,\n+\t\t  .f = CLK_SET_RATE_GATE, },\n \n \t\t{ .n = \"ethpll_divpmcck\",\n \t\t  .p = \"ethpll_fracck\",\n \t\t  .l = &pll_layout_divpmc,\n-\t\t  .t = PLL_TYPE_DIV, },\n+\t\t  .t = PLL_TYPE_DIV,\n+\t\t  .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |\n+\t\t       CLK_SET_RATE_PARENT, },\n \t},\n };\n \n@@ -890,7 +923,7 @@ static void __init sama7g5_pmc_setup(str\n \t\t\t\t\tsama7g5_plls[i][j].p, parent_hw, i,\n \t\t\t\t\t&pll_characteristics,\n \t\t\t\t\tsama7g5_plls[i][j].l,\n-\t\t\t\t\tsama7g5_plls[i][j].c);\n+\t\t\t\t\tsama7g5_plls[i][j].f);\n \t\t\t\tbreak;\n \n \t\t\tcase PLL_TYPE_DIV:\n@@ -899,7 +932,7 @@ static void __init sama7g5_pmc_setup(str\n \t\t\t\t\tsama7g5_plls[i][j].p, i,\n \t\t\t\t\t&pll_characteristics,\n \t\t\t\t\tsama7g5_plls[i][j].l,\n-\t\t\t\t\tsama7g5_plls[i][j].c);\n+\t\t\t\t\tsama7g5_plls[i][j].f);\n \t\t\t\tbreak;\n \n \t\t\tdefault:\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/107-clk-at91-sama7g5-remove-mck0-from-parent-list-of-oth.patch",
    "content": "From 7cfe2dfe5ac7c72b904e4b59b240caa42721ee07 Mon Sep 17 00:00:00 2001\nFrom: Claudiu Beznea <claudiu.beznea@microchip.com>\nDate: Thu, 19 Nov 2020 17:43:13 +0200\nSubject: [PATCH 107/247] clk: at91: sama7g5: remove mck0 from parent list of\n other clocks\n\nMCK0 is changed at runtime by DVFS. Due to this, since not all IPs\nare glitch free aware at MCK0 changes, remove MCK0 from parent list\nof other clocks (e.g. generic clock, programmable/system clock, MCKX).\n\nSigned-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>\nLink: https://lore.kernel.org/r/1605800597-16720-8-git-send-email-claudiu.beznea@microchip.com\nSigned-off-by: Stephen Boyd <sboyd@kernel.org>\n---\n drivers/clk/at91/sama7g5.c | 55 ++++++++++++++++++--------------------\n 1 file changed, 26 insertions(+), 29 deletions(-)\n\n--- a/drivers/clk/at91/sama7g5.c\n+++ b/drivers/clk/at91/sama7g5.c\n@@ -280,7 +280,7 @@ static const struct {\n \t  .ep = { \"syspll_divpmcck\", \"ddrpll_divpmcck\", \"imgpll_divpmcck\", },\n \t  .ep_mux_table = { 5, 6, 7, },\n \t  .ep_count = 3,\n-\t  .ep_chg_id = 6, },\n+\t  .ep_chg_id = 5, },\n \n \t{ .n = \"mck4\",\n \t  .id = 4,\n@@ -313,7 +313,7 @@ static const struct {\n };\n \n /* Mux table for programmable clocks. */\n-static u32 sama7g5_prog_mux_table[] = { 0, 1, 2, 3, 5, 6, 7, 8, 9, 10, };\n+static u32 sama7g5_prog_mux_table[] = { 0, 1, 2, 5, 6, 7, 8, 9, 10, };\n \n /**\n  * Peripheral clock description\n@@ -436,7 +436,7 @@ static const struct {\n \t  .pp = { \"audiopll_divpmcck\", },\n \t  .pp_mux_table = { 9, },\n \t  .pp_count = 1,\n-\t  .pp_chg_id = 4, },\n+\t  .pp_chg_id = 3, },\n \n \t{ .n  = \"csi_gclk\",\n \t  .id = 33,\n@@ -548,7 +548,7 @@ static const struct {\n \t  .pp = { \"ethpll_divpmcck\", },\n \t  .pp_mux_table = { 10, },\n \t  .pp_count = 1,\n-\t  .pp_chg_id = 4, },\n+\t  .pp_chg_id = 3, },\n \n \t{ .n  = \"gmac1_gclk\",\n \t  .id = 52,\n@@ -580,7 +580,7 @@ static const struct {\n \t  .pp = { \"syspll_divpmcck\", \"audiopll_divpmcck\", },\n \t  .pp_mux_table = { 5, 9, },\n \t  .pp_count = 2,\n-\t  .pp_chg_id = 5, },\n+\t  .pp_chg_id = 4, },\n \n \t{ .n  = \"i2smcc1_gclk\",\n \t  .id = 58,\n@@ -588,7 +588,7 @@ static const struct {\n \t  .pp = { \"syspll_divpmcck\", \"audiopll_divpmcck\", },\n \t  .pp_mux_table = { 5, 9, },\n \t  .pp_count = 2,\n-\t  .pp_chg_id = 5, },\n+\t  .pp_chg_id = 4, },\n \n \t{ .n  = \"mcan0_gclk\",\n \t  .id = 61,\n@@ -730,7 +730,7 @@ static const struct {\n \t  .pp = { \"syspll_divpmcck\", \"baudpll_divpmcck\", },\n \t  .pp_mux_table = { 5, 8, },\n \t  .pp_count = 2,\n-\t  .pp_chg_id = 5, },\n+\t  .pp_chg_id = 4, },\n \n \t{ .n  = \"sdmmc1_gclk\",\n \t  .id = 81,\n@@ -738,7 +738,7 @@ static const struct {\n \t  .pp = { \"syspll_divpmcck\", \"baudpll_divpmcck\", },\n \t  .pp_mux_table = { 5, 8, },\n \t  .pp_count = 2,\n-\t  .pp_chg_id = 5, },\n+\t  .pp_chg_id = 4, },\n \n \t{ .n  = \"sdmmc2_gclk\",\n \t  .id = 82,\n@@ -746,7 +746,7 @@ static const struct {\n \t  .pp = { \"syspll_divpmcck\", \"baudpll_divpmcck\", },\n \t  .pp_mux_table = { 5, 8, },\n \t  .pp_count = 2,\n-\t  .pp_chg_id = 5, },\n+\t  .pp_chg_id = 4, },\n \n \t{ .n  = \"spdifrx_gclk\",\n \t  .id = 84,\n@@ -754,7 +754,7 @@ static const struct {\n \t  .pp = { \"syspll_divpmcck\", \"audiopll_divpmcck\", },\n \t  .pp_mux_table = { 5, 9, },\n \t  .pp_count = 2,\n-\t  .pp_chg_id = 5, },\n+\t  .pp_chg_id = 4, },\n \n \t{ .n = \"spdiftx_gclk\",\n \t  .id = 85,\n@@ -762,7 +762,7 @@ static const struct {\n \t  .pp = { \"syspll_divpmcck\", \"audiopll_divpmcck\", },\n \t  .pp_mux_table = { 5, 9, },\n \t  .pp_count = 2,\n-\t  .pp_chg_id = 5, },\n+\t  .pp_chg_id = 4, },\n \n \t{ .n  = \"tcb0_ch0_gclk\",\n \t  .id = 88,\n@@ -961,9 +961,8 @@ static void __init sama7g5_pmc_setup(str\n \tparent_names[0] = md_slck_name;\n \tparent_names[1] = td_slck_name;\n \tparent_names[2] = \"mainck\";\n-\tparent_names[3] = \"mck0\";\n \tfor (i = 0; i < ARRAY_SIZE(sama7g5_mckx); i++) {\n-\t\tu8 num_parents = 4 + sama7g5_mckx[i].ep_count;\n+\t\tu8 num_parents = 3 + sama7g5_mckx[i].ep_count;\n \t\tu32 *mux_table;\n \n \t\tmux_table = kmalloc_array(num_parents, sizeof(*mux_table),\n@@ -971,10 +970,10 @@ static void __init sama7g5_pmc_setup(str\n \t\tif (!mux_table)\n \t\t\tgoto err_free;\n \n-\t\tSAMA7G5_INIT_TABLE(mux_table, 4);\n-\t\tSAMA7G5_FILL_TABLE(&mux_table[4], sama7g5_mckx[i].ep_mux_table,\n+\t\tSAMA7G5_INIT_TABLE(mux_table, 3);\n+\t\tSAMA7G5_FILL_TABLE(&mux_table[3], sama7g5_mckx[i].ep_mux_table,\n \t\t\t\t   sama7g5_mckx[i].ep_count);\n-\t\tSAMA7G5_FILL_TABLE(&parent_names[4], sama7g5_mckx[i].ep,\n+\t\tSAMA7G5_FILL_TABLE(&parent_names[3], sama7g5_mckx[i].ep,\n \t\t\t\t   sama7g5_mckx[i].ep_count);\n \n \t\thw = at91_clk_sama7g5_register_master(regmap, sama7g5_mckx[i].n,\n@@ -997,20 +996,19 @@ static void __init sama7g5_pmc_setup(str\n \tparent_names[0] = md_slck_name;\n \tparent_names[1] = td_slck_name;\n \tparent_names[2] = \"mainck\";\n-\tparent_names[3] = \"mck0\";\n-\tparent_names[4] = \"syspll_divpmcck\";\n-\tparent_names[5] = \"ddrpll_divpmcck\";\n-\tparent_names[6] = \"imgpll_divpmcck\";\n-\tparent_names[7] = \"baudpll_divpmcck\";\n-\tparent_names[8] = \"audiopll_divpmcck\";\n-\tparent_names[9] = \"ethpll_divpmcck\";\n+\tparent_names[3] = \"syspll_divpmcck\";\n+\tparent_names[4] = \"ddrpll_divpmcck\";\n+\tparent_names[5] = \"imgpll_divpmcck\";\n+\tparent_names[6] = \"baudpll_divpmcck\";\n+\tparent_names[7] = \"audiopll_divpmcck\";\n+\tparent_names[8] = \"ethpll_divpmcck\";\n \tfor (i = 0; i < 8; i++) {\n \t\tchar name[6];\n \n \t\tsnprintf(name, sizeof(name), \"prog%d\", i);\n \n \t\thw = at91_clk_register_programmable(regmap, name, parent_names,\n-\t\t\t\t\t\t    10, i,\n+\t\t\t\t\t\t    9, i,\n \t\t\t\t\t\t    &programmable_layout,\n \t\t\t\t\t\t    sama7g5_prog_mux_table);\n \t\tif (IS_ERR(hw))\n@@ -1047,9 +1045,8 @@ static void __init sama7g5_pmc_setup(str\n \tparent_names[0] = md_slck_name;\n \tparent_names[1] = td_slck_name;\n \tparent_names[2] = \"mainck\";\n-\tparent_names[3] = \"mck0\";\n \tfor (i = 0; i < ARRAY_SIZE(sama7g5_gck); i++) {\n-\t\tu8 num_parents = 4 + sama7g5_gck[i].pp_count;\n+\t\tu8 num_parents = 3 + sama7g5_gck[i].pp_count;\n \t\tu32 *mux_table;\n \n \t\tmux_table = kmalloc_array(num_parents, sizeof(*mux_table),\n@@ -1057,10 +1054,10 @@ static void __init sama7g5_pmc_setup(str\n \t\tif (!mux_table)\n \t\t\tgoto err_free;\n \n-\t\tSAMA7G5_INIT_TABLE(mux_table, 4);\n-\t\tSAMA7G5_FILL_TABLE(&mux_table[4], sama7g5_gck[i].pp_mux_table,\n+\t\tSAMA7G5_INIT_TABLE(mux_table, 3);\n+\t\tSAMA7G5_FILL_TABLE(&mux_table[3], sama7g5_gck[i].pp_mux_table,\n \t\t\t\t   sama7g5_gck[i].pp_count);\n-\t\tSAMA7G5_FILL_TABLE(&parent_names[4], sama7g5_gck[i].pp,\n+\t\tSAMA7G5_FILL_TABLE(&parent_names[3], sama7g5_gck[i].pp,\n \t\t\t\t   sama7g5_gck[i].pp_count);\n \n \t\thw = at91_clk_register_generated(regmap, &pmc_pcr_lock,\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/108-clk-at91-sama7g5-decrease-lower-limit-for-MCK0-rate.patch",
    "content": "From 8b88f1e9918c173b24b43015cdb713cdde9e4d17 Mon Sep 17 00:00:00 2001\nFrom: Claudiu Beznea <claudiu.beznea@microchip.com>\nDate: Thu, 19 Nov 2020 17:43:14 +0200\nSubject: [PATCH 108/247] clk: at91: sama7g5: decrease lower limit for MCK0\n rate\n\nOn SAMA7G5 CPU clock is changed at run-time by DVFS. Since MCK0 and\nCPU clock shares the same parent clock (CPUPLL clock) the MCK0 is\nalso changed by DVFS to avoid over/under clocking of MCK0 consumers.\nThe lower limit is changed to be able to set MCK0 accordingly by\nDVFS.\n\nSigned-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>\nLink: https://lore.kernel.org/r/1605800597-16720-9-git-send-email-claudiu.beznea@microchip.com\nSigned-off-by: Stephen Boyd <sboyd@kernel.org>\n---\n drivers/clk/at91/sama7g5.c | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/drivers/clk/at91/sama7g5.c\n+++ b/drivers/clk/at91/sama7g5.c\n@@ -807,7 +807,7 @@ static const struct clk_pll_characterist\n \n /* MCK0 characteristics. */\n static const struct clk_master_characteristics mck0_characteristics = {\n-\t.output = { .min = 140000000, .max = 200000000 },\n+\t.output = { .min = 50000000, .max = 200000000 },\n \t.divisors = { 1, 2, 4, 3, 5 },\n \t.have_div3_pres = 1,\n };\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/109-clk-at91-sama7g5-do-not-allow-cpu-pll-to-go-higher-t.patch",
    "content": "From 943ed75a2a5ab08582d3bc8025e8111903698763 Mon Sep 17 00:00:00 2001\nFrom: Claudiu Beznea <claudiu.beznea@microchip.com>\nDate: Thu, 19 Nov 2020 17:43:15 +0200\nSubject: [PATCH 109/247] clk: at91: sama7g5: do not allow cpu pll to go higher\n than 1GHz\n\nSince CPU PLL feeds both CPU clock and MCK0, MCK0 cannot go higher\nthan 200MHz and MCK0 maximum prescaller is 5 limit the CPU PLL at\n1GHz to avoid MCK0 overclocking while CPU PLL is changed by DVFS.\n\nSigned-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>\nLink: https://lore.kernel.org/r/1605800597-16720-10-git-send-email-claudiu.beznea@microchip.com\nSigned-off-by: Stephen Boyd <sboyd@kernel.org>\n---\n drivers/clk/at91/sama7g5.c | 61 +++++++++++++++++++++++++++++---------\n 1 file changed, 47 insertions(+), 14 deletions(-)\n\n--- a/drivers/clk/at91/sama7g5.c\n+++ b/drivers/clk/at91/sama7g5.c\n@@ -89,11 +89,40 @@ static const struct clk_pll_layout pll_l\n \t.endiv_shift\t= 30,\n };\n \n+/*\n+ * CPU PLL output range.\n+ * Notice: The upper limit has been setup to 1000000002 due to hardware\n+ * block which cannot output exactly 1GHz.\n+ */\n+static const struct clk_range cpu_pll_outputs[] = {\n+\t{ .min = 2343750, .max = 1000000002 },\n+};\n+\n+/* PLL output range. */\n+static const struct clk_range pll_outputs[] = {\n+\t{ .min = 2343750, .max = 1200000000 },\n+};\n+\n+/* CPU PLL characteristics. */\n+static const struct clk_pll_characteristics cpu_pll_characteristics = {\n+\t.input = { .min = 12000000, .max = 50000000 },\n+\t.num_output = ARRAY_SIZE(cpu_pll_outputs),\n+\t.output = cpu_pll_outputs,\n+};\n+\n+/* PLL characteristics. */\n+static const struct clk_pll_characteristics pll_characteristics = {\n+\t.input = { .min = 12000000, .max = 50000000 },\n+\t.num_output = ARRAY_SIZE(pll_outputs),\n+\t.output = pll_outputs,\n+};\n+\n /**\n  * PLL clocks description\n  * @n:\t\tclock name\n  * @p:\t\tclock parent\n  * @l:\t\tclock layout\n+ * @c:\t\tclock characteristics\n  * @t:\t\tclock type\n  * @f:\t\tclock flags\n  * @eid:\texport index in sama7g5->chws[] array\n@@ -102,6 +131,7 @@ static const struct {\n \tconst char *n;\n \tconst char *p;\n \tconst struct clk_pll_layout *l;\n+\tconst struct clk_pll_characteristics *c;\n \tunsigned long f;\n \tu8 t;\n \tu8 eid;\n@@ -110,6 +140,7 @@ static const struct {\n \t\t{ .n = \"cpupll_fracck\",\n \t\t  .p = \"mainck\",\n \t\t  .l = &pll_layout_frac,\n+\t\t  .c = &cpu_pll_characteristics,\n \t\t  .t = PLL_TYPE_FRAC,\n \t\t   /*\n \t\t    * This feeds cpupll_divpmcck which feeds CPU. It should\n@@ -120,6 +151,7 @@ static const struct {\n \t\t{ .n = \"cpupll_divpmcck\",\n \t\t  .p = \"cpupll_fracck\",\n \t\t  .l = &pll_layout_divpmc,\n+\t\t  .c = &cpu_pll_characteristics,\n \t\t  .t = PLL_TYPE_DIV,\n \t\t   /* This feeds CPU. It should not be disabled. */\n \t\t  .f = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,\n@@ -130,6 +162,7 @@ static const struct {\n \t\t{ .n = \"syspll_fracck\",\n \t\t  .p = \"mainck\",\n \t\t  .l = &pll_layout_frac,\n+\t\t  .c = &pll_characteristics,\n \t\t  .t = PLL_TYPE_FRAC,\n \t\t   /*\n \t\t    * This feeds syspll_divpmcck which may feed critial parts\n@@ -141,6 +174,7 @@ static const struct {\n \t\t{ .n = \"syspll_divpmcck\",\n \t\t  .p = \"syspll_fracck\",\n \t\t  .l = &pll_layout_divpmc,\n+\t\t  .c = &pll_characteristics,\n \t\t  .t = PLL_TYPE_DIV,\n \t\t   /*\n \t\t    * This may feed critial parts of the systems like timers.\n@@ -154,6 +188,7 @@ static const struct {\n \t\t{ .n = \"ddrpll_fracck\",\n \t\t  .p = \"mainck\",\n \t\t  .l = &pll_layout_frac,\n+\t\t  .c = &pll_characteristics,\n \t\t  .t = PLL_TYPE_FRAC,\n \t\t   /*\n \t\t    * This feeds ddrpll_divpmcck which feeds DDR. It should not\n@@ -164,6 +199,7 @@ static const struct {\n \t\t{ .n = \"ddrpll_divpmcck\",\n \t\t  .p = \"ddrpll_fracck\",\n \t\t  .l = &pll_layout_divpmc,\n+\t\t  .c = &pll_characteristics,\n \t\t  .t = PLL_TYPE_DIV,\n \t\t   /* This feeds DDR. It should not be disabled. */\n \t\t  .f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE, },\n@@ -173,12 +209,14 @@ static const struct {\n \t\t{ .n = \"imgpll_fracck\",\n \t\t  .p = \"mainck\",\n \t\t  .l = &pll_layout_frac,\n+\t\t  .c = &pll_characteristics,\n \t\t  .t = PLL_TYPE_FRAC,\n \t\t  .f = CLK_SET_RATE_GATE, },\n \n \t\t{ .n = \"imgpll_divpmcck\",\n \t\t  .p = \"imgpll_fracck\",\n \t\t  .l = &pll_layout_divpmc,\n+\t\t  .c = &pll_characteristics,\n \t\t  .t = PLL_TYPE_DIV,\n \t\t  .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |\n \t\t       CLK_SET_RATE_PARENT, },\n@@ -188,12 +226,14 @@ static const struct {\n \t\t{ .n = \"baudpll_fracck\",\n \t\t  .p = \"mainck\",\n \t\t  .l = &pll_layout_frac,\n+\t\t  .c = &pll_characteristics,\n \t\t  .t = PLL_TYPE_FRAC,\n \t\t  .f = CLK_SET_RATE_GATE, },\n \n \t\t{ .n = \"baudpll_divpmcck\",\n \t\t  .p = \"baudpll_fracck\",\n \t\t  .l = &pll_layout_divpmc,\n+\t\t  .c = &pll_characteristics,\n \t\t  .t = PLL_TYPE_DIV,\n \t\t  .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |\n \t\t       CLK_SET_RATE_PARENT, },\n@@ -203,12 +243,14 @@ static const struct {\n \t\t{ .n = \"audiopll_fracck\",\n \t\t  .p = \"main_xtal\",\n \t\t  .l = &pll_layout_frac,\n+\t\t  .c = &pll_characteristics,\n \t\t  .t = PLL_TYPE_FRAC,\n \t\t  .f = CLK_SET_RATE_GATE, },\n \n \t\t{ .n = \"audiopll_divpmcck\",\n \t\t  .p = \"audiopll_fracck\",\n \t\t  .l = &pll_layout_divpmc,\n+\t\t  .c = &pll_characteristics,\n \t\t  .t = PLL_TYPE_DIV,\n \t\t  .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |\n \t\t       CLK_SET_RATE_PARENT,\n@@ -217,6 +259,7 @@ static const struct {\n \t\t{ .n = \"audiopll_diviock\",\n \t\t  .p = \"audiopll_fracck\",\n \t\t  .l = &pll_layout_divio,\n+\t\t  .c = &pll_characteristics,\n \t\t  .t = PLL_TYPE_DIV,\n \t\t  .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |\n \t\t       CLK_SET_RATE_PARENT,\n@@ -227,12 +270,14 @@ static const struct {\n \t\t{ .n = \"ethpll_fracck\",\n \t\t  .p = \"main_xtal\",\n \t\t  .l = &pll_layout_frac,\n+\t\t  .c = &pll_characteristics,\n \t\t  .t = PLL_TYPE_FRAC,\n \t\t  .f = CLK_SET_RATE_GATE, },\n \n \t\t{ .n = \"ethpll_divpmcck\",\n \t\t  .p = \"ethpll_fracck\",\n \t\t  .l = &pll_layout_divpmc,\n+\t\t  .c = &pll_characteristics,\n \t\t  .t = PLL_TYPE_DIV,\n \t\t  .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |\n \t\t       CLK_SET_RATE_PARENT, },\n@@ -793,18 +838,6 @@ static const struct {\n \t  .pp_chg_id = INT_MIN, },\n };\n \n-/* PLL output range. */\n-static const struct clk_range pll_outputs[] = {\n-\t{ .min = 2343750, .max = 1200000000 },\n-};\n-\n-/* PLL characteristics. */\n-static const struct clk_pll_characteristics pll_characteristics = {\n-\t.input = { .min = 12000000, .max = 50000000 },\n-\t.num_output = ARRAY_SIZE(pll_outputs),\n-\t.output = pll_outputs,\n-};\n-\n /* MCK0 characteristics. */\n static const struct clk_master_characteristics mck0_characteristics = {\n \t.output = { .min = 50000000, .max = 200000000 },\n@@ -921,7 +954,7 @@ static void __init sama7g5_pmc_setup(str\n \t\t\t\thw = sam9x60_clk_register_frac_pll(regmap,\n \t\t\t\t\t&pmc_pll_lock, sama7g5_plls[i][j].n,\n \t\t\t\t\tsama7g5_plls[i][j].p, parent_hw, i,\n-\t\t\t\t\t&pll_characteristics,\n+\t\t\t\t\tsama7g5_plls[i][j].c,\n \t\t\t\t\tsama7g5_plls[i][j].l,\n \t\t\t\t\tsama7g5_plls[i][j].f);\n \t\t\t\tbreak;\n@@ -930,7 +963,7 @@ static void __init sama7g5_pmc_setup(str\n \t\t\t\thw = sam9x60_clk_register_div_pll(regmap,\n \t\t\t\t\t&pmc_pll_lock, sama7g5_plls[i][j].n,\n \t\t\t\t\tsama7g5_plls[i][j].p, i,\n-\t\t\t\t\t&pll_characteristics,\n+\t\t\t\t\tsama7g5_plls[i][j].c,\n \t\t\t\t\tsama7g5_plls[i][j].l,\n \t\t\t\t\tsama7g5_plls[i][j].f);\n \t\t\t\tbreak;\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/110-clk-at91-clk-master-re-factor-master-clock.patch",
    "content": "From 9109b768fe65994547ef464b13e508b22de3e89b Mon Sep 17 00:00:00 2001\nFrom: Claudiu Beznea <claudiu.beznea@microchip.com>\nDate: Thu, 19 Nov 2020 17:43:16 +0200\nSubject: [PATCH 110/247] clk: at91: clk-master: re-factor master clock\n\nRe-factor master clock driver by splitting it into 2 clocks: prescaller\nand divider clocks. Based on registered clock flags the prescaler's rate\ncould be changed at runtime. This is necessary for platforms supporting\nDVFS (e.g. SAMA7G5) where master clock could be changed at run-time.\n\nSigned-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>\nLink: https://lore.kernel.org/r/1605800597-16720-11-git-send-email-claudiu.beznea@microchip.com\nSigned-off-by: Stephen Boyd <sboyd@kernel.org>\n---\n drivers/clk/at91/at91rm9200.c  |  21 ++-\n drivers/clk/at91/at91sam9260.c |  26 ++-\n drivers/clk/at91/at91sam9g45.c |  32 +++-\n drivers/clk/at91/at91sam9n12.c |  36 ++--\n drivers/clk/at91/at91sam9rl.c  |  23 ++-\n drivers/clk/at91/at91sam9x5.c  |  28 ++-\n drivers/clk/at91/clk-master.c  | 335 ++++++++++++++++++++++++++++-----\n drivers/clk/at91/dt-compat.c   |  15 +-\n drivers/clk/at91/pmc.h         |  16 +-\n drivers/clk/at91/sam9x60.c     |  23 ++-\n drivers/clk/at91/sama5d2.c     |  42 +++--\n drivers/clk/at91/sama5d3.c     |  38 ++--\n drivers/clk/at91/sama5d4.c     |  40 ++--\n drivers/clk/at91/sama7g5.c     |  13 +-\n 14 files changed, 542 insertions(+), 146 deletions(-)\n\n--- a/drivers/clk/at91/at91rm9200.c\n+++ b/drivers/clk/at91/at91rm9200.c\n@@ -7,6 +7,8 @@\n \n #include \"pmc.h\"\n \n+static DEFINE_SPINLOCK(rm9200_mck_lock);\n+\n struct sck {\n \tchar *n;\n \tchar *p;\n@@ -137,9 +139,20 @@ static void __init at91rm9200_pmc_setup(\n \tparent_names[1] = \"mainck\";\n \tparent_names[2] = \"pllack\";\n \tparent_names[3] = \"pllbck\";\n-\thw = at91_clk_register_master(regmap, \"masterck\", 4, parent_names,\n-\t\t\t\t      &at91rm9200_master_layout,\n-\t\t\t\t      &rm9200_mck_characteristics);\n+\thw = at91_clk_register_master_pres(regmap, \"masterck_pres\", 4,\n+\t\t\t\t\t   parent_names,\n+\t\t\t\t\t   &at91rm9200_master_layout,\n+\t\t\t\t\t   &rm9200_mck_characteristics,\n+\t\t\t\t\t   &rm9200_mck_lock, CLK_SET_RATE_GATE,\n+\t\t\t\t\t   INT_MIN);\n+\tif (IS_ERR(hw))\n+\t\tgoto err_free;\n+\n+\thw = at91_clk_register_master_div(regmap, \"masterck_div\",\n+\t\t\t\t\t  \"masterck_pres\",\n+\t\t\t\t\t  &at91rm9200_master_layout,\n+\t\t\t\t\t  &rm9200_mck_characteristics,\n+\t\t\t\t\t  &rm9200_mck_lock, CLK_SET_RATE_GATE);\n \tif (IS_ERR(hw))\n \t\tgoto err_free;\n \n@@ -181,7 +194,7 @@ static void __init at91rm9200_pmc_setup(\n \tfor (i = 0; i < ARRAY_SIZE(at91rm9200_periphck); i++) {\n \t\thw = at91_clk_register_peripheral(regmap,\n \t\t\t\t\t\t  at91rm9200_periphck[i].n,\n-\t\t\t\t\t\t  \"masterck\",\n+\t\t\t\t\t\t  \"masterck_div\",\n \t\t\t\t\t\t  at91rm9200_periphck[i].id);\n \t\tif (IS_ERR(hw))\n \t\t\tgoto err_free;\n--- a/drivers/clk/at91/at91sam9260.c\n+++ b/drivers/clk/at91/at91sam9260.c\n@@ -32,6 +32,8 @@ struct at91sam926x_data {\n \tbool has_slck;\n };\n \n+static DEFINE_SPINLOCK(at91sam9260_mck_lock);\n+\n static const struct clk_master_characteristics sam9260_mck_characteristics = {\n \t.output = { .min = 0, .max = 105000000 },\n \t.divisors = { 1, 2, 4, 0 },\n@@ -218,8 +220,8 @@ static const struct sck at91sam9261_syst\n \t{ .n = \"pck1\",  .p = \"prog1\",    .id = 9 },\n \t{ .n = \"pck2\",  .p = \"prog2\",    .id = 10 },\n \t{ .n = \"pck3\",  .p = \"prog3\",    .id = 11 },\n-\t{ .n = \"hclk0\", .p = \"masterck\", .id = 16 },\n-\t{ .n = \"hclk1\", .p = \"masterck\", .id = 17 },\n+\t{ .n = \"hclk0\", .p = \"masterck_div\", .id = 16 },\n+\t{ .n = \"hclk1\", .p = \"masterck_div\", .id = 17 },\n };\n \n static const struct pck at91sam9261_periphck[] = {\n@@ -413,9 +415,21 @@ static void __init at91sam926x_pmc_setup\n \tparent_names[1] = \"mainck\";\n \tparent_names[2] = \"pllack\";\n \tparent_names[3] = \"pllbck\";\n-\thw = at91_clk_register_master(regmap, \"masterck\", 4, parent_names,\n-\t\t\t\t      &at91rm9200_master_layout,\n-\t\t\t\t      data->mck_characteristics);\n+\thw = at91_clk_register_master_pres(regmap, \"masterck_pres\", 4,\n+\t\t\t\t\t   parent_names,\n+\t\t\t\t\t   &at91rm9200_master_layout,\n+\t\t\t\t\t   data->mck_characteristics,\n+\t\t\t\t\t   &at91sam9260_mck_lock,\n+\t\t\t\t\t   CLK_SET_RATE_GATE, INT_MIN);\n+\tif (IS_ERR(hw))\n+\t\tgoto err_free;\n+\n+\thw = at91_clk_register_master_div(regmap, \"masterck_div\",\n+\t\t\t\t\t  \"masterck_pres\",\n+\t\t\t\t\t  &at91rm9200_master_layout,\n+\t\t\t\t\t  data->mck_characteristics,\n+\t\t\t\t\t  &at91sam9260_mck_lock,\n+\t\t\t\t\t  CLK_SET_RATE_GATE);\n \tif (IS_ERR(hw))\n \t\tgoto err_free;\n \n@@ -457,7 +471,7 @@ static void __init at91sam926x_pmc_setup\n \tfor (i = 0; i < data->num_pck; i++) {\n \t\thw = at91_clk_register_peripheral(regmap,\n \t\t\t\t\t\t  data->pck[i].n,\n-\t\t\t\t\t\t  \"masterck\",\n+\t\t\t\t\t\t  \"masterck_div\",\n \t\t\t\t\t\t  data->pck[i].id);\n \t\tif (IS_ERR(hw))\n \t\t\tgoto err_free;\n--- a/drivers/clk/at91/at91sam9g45.c\n+++ b/drivers/clk/at91/at91sam9g45.c\n@@ -7,6 +7,8 @@\n \n #include \"pmc.h\"\n \n+static DEFINE_SPINLOCK(at91sam9g45_mck_lock);\n+\n static const struct clk_master_characteristics mck_characteristics = {\n \t.output = { .min = 0, .max = 133333333 },\n \t.divisors = { 1, 2, 4, 3 },\n@@ -40,10 +42,10 @@ static const struct {\n \tchar *p;\n \tu8 id;\n } at91sam9g45_systemck[] = {\n-\t{ .n = \"ddrck\", .p = \"masterck\", .id = 2 },\n-\t{ .n = \"uhpck\", .p = \"usbck\",    .id = 6 },\n-\t{ .n = \"pck0\",  .p = \"prog0\",    .id = 8 },\n-\t{ .n = \"pck1\",  .p = \"prog1\",    .id = 9 },\n+\t{ .n = \"ddrck\", .p = \"masterck_div\", .id = 2 },\n+\t{ .n = \"uhpck\", .p = \"usbck\",        .id = 6 },\n+\t{ .n = \"pck0\",  .p = \"prog0\",        .id = 8 },\n+\t{ .n = \"pck1\",  .p = \"prog1\",        .id = 9 },\n };\n \n struct pck {\n@@ -148,9 +150,21 @@ static void __init at91sam9g45_pmc_setup\n \tparent_names[1] = \"mainck\";\n \tparent_names[2] = \"plladivck\";\n \tparent_names[3] = \"utmick\";\n-\thw = at91_clk_register_master(regmap, \"masterck\", 4, parent_names,\n-\t\t\t\t      &at91rm9200_master_layout,\n-\t\t\t\t      &mck_characteristics);\n+\thw = at91_clk_register_master_pres(regmap, \"masterck_pres\", 4,\n+\t\t\t\t\t   parent_names,\n+\t\t\t\t\t   &at91rm9200_master_layout,\n+\t\t\t\t\t   &mck_characteristics,\n+\t\t\t\t\t   &at91sam9g45_mck_lock,\n+\t\t\t\t\t   CLK_SET_RATE_GATE, INT_MIN);\n+\tif (IS_ERR(hw))\n+\t\tgoto err_free;\n+\n+\thw = at91_clk_register_master_div(regmap, \"masterck_div\",\n+\t\t\t\t\t  \"masterck_pres\",\n+\t\t\t\t\t  &at91rm9200_master_layout,\n+\t\t\t\t\t  &mck_characteristics,\n+\t\t\t\t\t  &at91sam9g45_mck_lock,\n+\t\t\t\t\t  CLK_SET_RATE_GATE);\n \tif (IS_ERR(hw))\n \t\tgoto err_free;\n \n@@ -166,7 +180,7 @@ static void __init at91sam9g45_pmc_setup\n \tparent_names[1] = \"mainck\";\n \tparent_names[2] = \"plladivck\";\n \tparent_names[3] = \"utmick\";\n-\tparent_names[4] = \"masterck\";\n+\tparent_names[4] = \"masterck_div\";\n \tfor (i = 0; i < 2; i++) {\n \t\tchar name[6];\n \n@@ -195,7 +209,7 @@ static void __init at91sam9g45_pmc_setup\n \tfor (i = 0; i < ARRAY_SIZE(at91sam9g45_periphck); i++) {\n \t\thw = at91_clk_register_peripheral(regmap,\n \t\t\t\t\t\t  at91sam9g45_periphck[i].n,\n-\t\t\t\t\t\t  \"masterck\",\n+\t\t\t\t\t\t  \"masterck_div\",\n \t\t\t\t\t\t  at91sam9g45_periphck[i].id);\n \t\tif (IS_ERR(hw))\n \t\t\tgoto err_free;\n--- a/drivers/clk/at91/at91sam9n12.c\n+++ b/drivers/clk/at91/at91sam9n12.c\n@@ -7,6 +7,8 @@\n \n #include \"pmc.h\"\n \n+static DEFINE_SPINLOCK(at91sam9n12_mck_lock);\n+\n static const struct clk_master_characteristics mck_characteristics = {\n \t.output = { .min = 0, .max = 133333333 },\n \t.divisors = { 1, 2, 4, 3 },\n@@ -54,12 +56,12 @@ static const struct {\n \tchar *p;\n \tu8 id;\n } at91sam9n12_systemck[] = {\n-\t{ .n = \"ddrck\", .p = \"masterck\", .id = 2 },\n-\t{ .n = \"lcdck\", .p = \"masterck\", .id = 3 },\n-\t{ .n = \"uhpck\", .p = \"usbck\",    .id = 6 },\n-\t{ .n = \"udpck\", .p = \"usbck\",    .id = 7 },\n-\t{ .n = \"pck0\",  .p = \"prog0\",    .id = 8 },\n-\t{ .n = \"pck1\",  .p = \"prog1\",    .id = 9 },\n+\t{ .n = \"ddrck\", .p = \"masterck_div\", .id = 2 },\n+\t{ .n = \"lcdck\", .p = \"masterck_div\", .id = 3 },\n+\t{ .n = \"uhpck\", .p = \"usbck\",        .id = 6 },\n+\t{ .n = \"udpck\", .p = \"usbck\",        .id = 7 },\n+\t{ .n = \"pck0\",  .p = \"prog0\",        .id = 8 },\n+\t{ .n = \"pck1\",  .p = \"prog1\",        .id = 9 },\n };\n \n static const struct clk_pcr_layout at91sam9n12_pcr_layout = {\n@@ -175,9 +177,21 @@ static void __init at91sam9n12_pmc_setup\n \tparent_names[1] = \"mainck\";\n \tparent_names[2] = \"plladivck\";\n \tparent_names[3] = \"pllbck\";\n-\thw = at91_clk_register_master(regmap, \"masterck\", 4, parent_names,\n-\t\t\t\t      &at91sam9x5_master_layout,\n-\t\t\t\t      &mck_characteristics);\n+\thw = at91_clk_register_master_pres(regmap, \"masterck_pres\", 4,\n+\t\t\t\t\t   parent_names,\n+\t\t\t\t\t   &at91sam9x5_master_layout,\n+\t\t\t\t\t   &mck_characteristics,\n+\t\t\t\t\t   &at91sam9n12_mck_lock,\n+\t\t\t\t\t   CLK_SET_RATE_GATE, INT_MIN);\n+\tif (IS_ERR(hw))\n+\t\tgoto err_free;\n+\n+\thw = at91_clk_register_master_div(regmap, \"masterck_div\",\n+\t\t\t\t\t  \"masterck_pres\",\n+\t\t\t\t\t  &at91sam9x5_master_layout,\n+\t\t\t\t\t  &mck_characteristics,\n+\t\t\t\t\t  &at91sam9n12_mck_lock,\n+\t\t\t\t\t  CLK_SET_RATE_GATE);\n \tif (IS_ERR(hw))\n \t\tgoto err_free;\n \n@@ -191,7 +205,7 @@ static void __init at91sam9n12_pmc_setup\n \tparent_names[1] = \"mainck\";\n \tparent_names[2] = \"plladivck\";\n \tparent_names[3] = \"pllbck\";\n-\tparent_names[4] = \"masterck\";\n+\tparent_names[4] = \"masterck_div\";\n \tfor (i = 0; i < 2; i++) {\n \t\tchar name[6];\n \n@@ -221,7 +235,7 @@ static void __init at91sam9n12_pmc_setup\n \t\thw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,\n \t\t\t\t\t\t\t &at91sam9n12_pcr_layout,\n \t\t\t\t\t\t\t at91sam9n12_periphck[i].n,\n-\t\t\t\t\t\t\t \"masterck\",\n+\t\t\t\t\t\t\t \"masterck_div\",\n \t\t\t\t\t\t\t at91sam9n12_periphck[i].id,\n \t\t\t\t\t\t\t &range, INT_MIN);\n \t\tif (IS_ERR(hw))\n--- a/drivers/clk/at91/at91sam9rl.c\n+++ b/drivers/clk/at91/at91sam9rl.c\n@@ -7,6 +7,8 @@\n \n #include \"pmc.h\"\n \n+static DEFINE_SPINLOCK(sam9rl_mck_lock);\n+\n static const struct clk_master_characteristics sam9rl_mck_characteristics = {\n \t.output = { .min = 0, .max = 94000000 },\n \t.divisors = { 1, 2, 4, 0 },\n@@ -117,9 +119,20 @@ static void __init at91sam9rl_pmc_setup(\n \tparent_names[1] = \"mainck\";\n \tparent_names[2] = \"pllack\";\n \tparent_names[3] = \"utmick\";\n-\thw = at91_clk_register_master(regmap, \"masterck\", 4, parent_names,\n-\t\t\t\t      &at91rm9200_master_layout,\n-\t\t\t\t      &sam9rl_mck_characteristics);\n+\thw = at91_clk_register_master_pres(regmap, \"masterck_pres\", 4,\n+\t\t\t\t\t   parent_names,\n+\t\t\t\t\t   &at91rm9200_master_layout,\n+\t\t\t\t\t   &sam9rl_mck_characteristics,\n+\t\t\t\t\t   &sam9rl_mck_lock, CLK_SET_RATE_GATE,\n+\t\t\t\t\t   INT_MIN);\n+\tif (IS_ERR(hw))\n+\t\tgoto err_free;\n+\n+\thw = at91_clk_register_master_div(regmap, \"masterck_div\",\n+\t\t\t\t\t  \"masterck_pres\",\n+\t\t\t\t\t  &at91rm9200_master_layout,\n+\t\t\t\t\t  &sam9rl_mck_characteristics,\n+\t\t\t\t\t  &sam9rl_mck_lock, CLK_SET_RATE_GATE);\n \tif (IS_ERR(hw))\n \t\tgoto err_free;\n \n@@ -129,7 +142,7 @@ static void __init at91sam9rl_pmc_setup(\n \tparent_names[1] = \"mainck\";\n \tparent_names[2] = \"pllack\";\n \tparent_names[3] = \"utmick\";\n-\tparent_names[4] = \"masterck\";\n+\tparent_names[4] = \"masterck_div\";\n \tfor (i = 0; i < 2; i++) {\n \t\tchar name[6];\n \n@@ -158,7 +171,7 @@ static void __init at91sam9rl_pmc_setup(\n \tfor (i = 0; i < ARRAY_SIZE(at91sam9rl_periphck); i++) {\n \t\thw = at91_clk_register_peripheral(regmap,\n \t\t\t\t\t\t  at91sam9rl_periphck[i].n,\n-\t\t\t\t\t\t  \"masterck\",\n+\t\t\t\t\t\t  \"masterck_div\",\n \t\t\t\t\t\t  at91sam9rl_periphck[i].id);\n \t\tif (IS_ERR(hw))\n \t\t\tgoto err_free;\n--- a/drivers/clk/at91/at91sam9x5.c\n+++ b/drivers/clk/at91/at91sam9x5.c\n@@ -7,6 +7,8 @@\n \n #include \"pmc.h\"\n \n+static DEFINE_SPINLOCK(mck_lock);\n+\n static const struct clk_master_characteristics mck_characteristics = {\n \t.output = { .min = 0, .max = 133333333 },\n \t.divisors = { 1, 2, 4, 3 },\n@@ -41,7 +43,7 @@ static const struct {\n \tchar *p;\n \tu8 id;\n } at91sam9x5_systemck[] = {\n-\t{ .n = \"ddrck\", .p = \"masterck\", .id = 2 },\n+\t{ .n = \"ddrck\", .p = \"masterck_div\", .id = 2 },\n \t{ .n = \"smdck\", .p = \"smdclk\",   .id = 4 },\n \t{ .n = \"uhpck\", .p = \"usbck\",    .id = 6 },\n \t{ .n = \"udpck\", .p = \"usbck\",    .id = 7 },\n@@ -196,9 +198,19 @@ static void __init at91sam9x5_pmc_setup(\n \tparent_names[1] = \"mainck\";\n \tparent_names[2] = \"plladivck\";\n \tparent_names[3] = \"utmick\";\n-\thw = at91_clk_register_master(regmap, \"masterck\", 4, parent_names,\n-\t\t\t\t      &at91sam9x5_master_layout,\n-\t\t\t\t      &mck_characteristics);\n+\thw = at91_clk_register_master_pres(regmap, \"masterck_pres\", 4,\n+\t\t\t\t\t   parent_names,\n+\t\t\t\t\t   &at91sam9x5_master_layout,\n+\t\t\t\t\t   &mck_characteristics, &mck_lock,\n+\t\t\t\t\t   CLK_SET_RATE_GATE, INT_MIN);\n+\tif (IS_ERR(hw))\n+\t\tgoto err_free;\n+\n+\thw = at91_clk_register_master_div(regmap, \"masterck_div\",\n+\t\t\t\t\t  \"masterck_pres\",\n+\t\t\t\t\t  &at91sam9x5_master_layout,\n+\t\t\t\t\t  &mck_characteristics, &mck_lock,\n+\t\t\t\t\t  CLK_SET_RATE_GATE);\n \tif (IS_ERR(hw))\n \t\tgoto err_free;\n \n@@ -218,7 +230,7 @@ static void __init at91sam9x5_pmc_setup(\n \tparent_names[1] = \"mainck\";\n \tparent_names[2] = \"plladivck\";\n \tparent_names[3] = \"utmick\";\n-\tparent_names[4] = \"masterck\";\n+\tparent_names[4] = \"masterck_div\";\n \tfor (i = 0; i < 2; i++) {\n \t\tchar name[6];\n \n@@ -245,7 +257,7 @@ static void __init at91sam9x5_pmc_setup(\n \t}\n \n \tif (has_lcdck) {\n-\t\thw = at91_clk_register_system(regmap, \"lcdck\", \"masterck\", 3);\n+\t\thw = at91_clk_register_system(regmap, \"lcdck\", \"masterck_div\", 3);\n \t\tif (IS_ERR(hw))\n \t\t\tgoto err_free;\n \n@@ -256,7 +268,7 @@ static void __init at91sam9x5_pmc_setup(\n \t\thw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,\n \t\t\t\t\t\t\t &at91sam9x5_pcr_layout,\n \t\t\t\t\t\t\t at91sam9x5_periphck[i].n,\n-\t\t\t\t\t\t\t \"masterck\",\n+\t\t\t\t\t\t\t \"masterck_div\",\n \t\t\t\t\t\t\t at91sam9x5_periphck[i].id,\n \t\t\t\t\t\t\t &range, INT_MIN);\n \t\tif (IS_ERR(hw))\n@@ -269,7 +281,7 @@ static void __init at91sam9x5_pmc_setup(\n \t\thw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,\n \t\t\t\t\t\t\t &at91sam9x5_pcr_layout,\n \t\t\t\t\t\t\t extra_pcks[i].n,\n-\t\t\t\t\t\t\t \"masterck\",\n+\t\t\t\t\t\t\t \"masterck_div\",\n \t\t\t\t\t\t\t extra_pcks[i].id,\n \t\t\t\t\t\t\t &range, INT_MIN);\n \t\tif (IS_ERR(hw))\n--- a/drivers/clk/at91/clk-master.c\n+++ b/drivers/clk/at91/clk-master.c\n@@ -58,83 +58,309 @@ static inline bool clk_master_ready(stru\n static int clk_master_prepare(struct clk_hw *hw)\n {\n \tstruct clk_master *master = to_clk_master(hw);\n+\tunsigned long flags;\n+\n+\tspin_lock_irqsave(master->lock, flags);\n \n \twhile (!clk_master_ready(master))\n \t\tcpu_relax();\n \n+\tspin_unlock_irqrestore(master->lock, flags);\n+\n \treturn 0;\n }\n \n static int clk_master_is_prepared(struct clk_hw *hw)\n {\n \tstruct clk_master *master = to_clk_master(hw);\n+\tunsigned long flags;\n+\tbool status;\n+\n+\tspin_lock_irqsave(master->lock, flags);\n+\tstatus = clk_master_ready(master);\n+\tspin_unlock_irqrestore(master->lock, flags);\n \n-\treturn clk_master_ready(master);\n+\treturn status;\n }\n \n-static unsigned long clk_master_recalc_rate(struct clk_hw *hw,\n-\t\t\t\t\t    unsigned long parent_rate)\n+static unsigned long clk_master_div_recalc_rate(struct clk_hw *hw,\n+\t\t\t\t\t\tunsigned long parent_rate)\n {\n-\tu8 pres;\n \tu8 div;\n-\tunsigned long rate = parent_rate;\n+\tunsigned long flags, rate = parent_rate;\n \tstruct clk_master *master = to_clk_master(hw);\n \tconst struct clk_master_layout *layout = master->layout;\n \tconst struct clk_master_characteristics *characteristics =\n \t\t\t\t\t\tmaster->characteristics;\n \tunsigned int mckr;\n \n+\tspin_lock_irqsave(master->lock, flags);\n \tregmap_read(master->regmap, master->layout->offset, &mckr);\n+\tspin_unlock_irqrestore(master->lock, flags);\n+\n \tmckr &= layout->mask;\n \n-\tpres = (mckr >> layout->pres_shift) & MASTER_PRES_MASK;\n \tdiv = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK;\n \n-\tif (characteristics->have_div3_pres && pres == MASTER_PRES_MAX)\n-\t\trate /= 3;\n-\telse\n-\t\trate >>= pres;\n-\n \trate /= characteristics->divisors[div];\n \n \tif (rate < characteristics->output.min)\n-\t\tpr_warn(\"master clk is underclocked\");\n+\t\tpr_warn(\"master clk div is underclocked\");\n \telse if (rate > characteristics->output.max)\n-\t\tpr_warn(\"master clk is overclocked\");\n+\t\tpr_warn(\"master clk div is overclocked\");\n \n \treturn rate;\n }\n \n-static u8 clk_master_get_parent(struct clk_hw *hw)\n+static const struct clk_ops master_div_ops = {\n+\t.prepare = clk_master_prepare,\n+\t.is_prepared = clk_master_is_prepared,\n+\t.recalc_rate = clk_master_div_recalc_rate,\n+};\n+\n+static int clk_master_div_set_rate(struct clk_hw *hw, unsigned long rate,\n+\t\t\t\t   unsigned long parent_rate)\n+{\n+\tstruct clk_master *master = to_clk_master(hw);\n+\tconst struct clk_master_characteristics *characteristics =\n+\t\t\t\t\t\tmaster->characteristics;\n+\tunsigned long flags;\n+\tint div, i;\n+\n+\tdiv = DIV_ROUND_CLOSEST(parent_rate, rate);\n+\tif (div > ARRAY_SIZE(characteristics->divisors))\n+\t\treturn -EINVAL;\n+\n+\tfor (i = 0; i < ARRAY_SIZE(characteristics->divisors); i++) {\n+\t\tif (!characteristics->divisors[i])\n+\t\t\tbreak;\n+\n+\t\tif (div == characteristics->divisors[i]) {\n+\t\t\tdiv = i;\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\n+\tif (i == ARRAY_SIZE(characteristics->divisors))\n+\t\treturn -EINVAL;\n+\n+\tspin_lock_irqsave(master->lock, flags);\n+\tregmap_update_bits(master->regmap, master->layout->offset,\n+\t\t\t   (MASTER_DIV_MASK << MASTER_DIV_SHIFT),\n+\t\t\t   (div << MASTER_DIV_SHIFT));\n+\twhile (!clk_master_ready(master))\n+\t\tcpu_relax();\n+\tspin_unlock_irqrestore(master->lock, flags);\n+\n+\treturn 0;\n+}\n+\n+static int clk_master_div_determine_rate(struct clk_hw *hw,\n+\t\t\t\t\t struct clk_rate_request *req)\n+{\n+\tstruct clk_master *master = to_clk_master(hw);\n+\tconst struct clk_master_characteristics *characteristics =\n+\t\t\t\t\t\tmaster->characteristics;\n+\tstruct clk_hw *parent;\n+\tunsigned long parent_rate, tmp_rate, best_rate = 0;\n+\tint i, best_diff = INT_MIN, tmp_diff;\n+\n+\tparent = clk_hw_get_parent(hw);\n+\tif (!parent)\n+\t\treturn -EINVAL;\n+\n+\tparent_rate = clk_hw_get_rate(parent);\n+\tif (!parent_rate)\n+\t\treturn -EINVAL;\n+\n+\tfor (i = 0; i < ARRAY_SIZE(characteristics->divisors); i++) {\n+\t\tif (!characteristics->divisors[i])\n+\t\t\tbreak;\n+\n+\t\ttmp_rate = DIV_ROUND_CLOSEST_ULL(parent_rate,\n+\t\t\t\t\t\t characteristics->divisors[i]);\n+\t\ttmp_diff = abs(tmp_rate - req->rate);\n+\n+\t\tif (!best_rate || best_diff > tmp_diff) {\n+\t\t\tbest_diff = tmp_diff;\n+\t\t\tbest_rate = tmp_rate;\n+\t\t}\n+\n+\t\tif (!best_diff)\n+\t\t\tbreak;\n+\t}\n+\n+\treq->best_parent_rate = best_rate;\n+\treq->best_parent_hw = parent;\n+\treq->rate = best_rate;\n+\n+\treturn 0;\n+}\n+\n+static const struct clk_ops master_div_ops_chg = {\n+\t.prepare = clk_master_prepare,\n+\t.is_prepared = clk_master_is_prepared,\n+\t.recalc_rate = clk_master_div_recalc_rate,\n+\t.determine_rate = clk_master_div_determine_rate,\n+\t.set_rate = clk_master_div_set_rate,\n+};\n+\n+static void clk_sama7g5_master_best_diff(struct clk_rate_request *req,\n+\t\t\t\t\t struct clk_hw *parent,\n+\t\t\t\t\t unsigned long parent_rate,\n+\t\t\t\t\t long *best_rate,\n+\t\t\t\t\t long *best_diff,\n+\t\t\t\t\t u32 div)\n+{\n+\tunsigned long tmp_rate, tmp_diff;\n+\n+\tif (div == MASTER_PRES_MAX)\n+\t\ttmp_rate = parent_rate / 3;\n+\telse\n+\t\ttmp_rate = parent_rate >> div;\n+\n+\ttmp_diff = abs(req->rate - tmp_rate);\n+\n+\tif (*best_diff < 0 || *best_diff >= tmp_diff) {\n+\t\t*best_rate = tmp_rate;\n+\t\t*best_diff = tmp_diff;\n+\t\treq->best_parent_rate = parent_rate;\n+\t\treq->best_parent_hw = parent;\n+\t}\n+}\n+\n+static int clk_master_pres_determine_rate(struct clk_hw *hw,\n+\t\t\t\t\t  struct clk_rate_request *req)\n+{\n+\tstruct clk_master *master = to_clk_master(hw);\n+\tstruct clk_rate_request req_parent = *req;\n+\tconst struct clk_master_characteristics *characteristics =\n+\t\t\t\t\t\t\tmaster->characteristics;\n+\tstruct clk_hw *parent;\n+\tlong best_rate = LONG_MIN, best_diff = LONG_MIN;\n+\tu32 pres;\n+\tint i;\n+\n+\tif (master->chg_pid < 0)\n+\t\treturn -EOPNOTSUPP;\n+\n+\tparent = clk_hw_get_parent_by_index(hw, master->chg_pid);\n+\tif (!parent)\n+\t\treturn -EOPNOTSUPP;\n+\n+\tfor (i = 0; i <= MASTER_PRES_MAX; i++) {\n+\t\tif (characteristics->have_div3_pres && i == MASTER_PRES_MAX)\n+\t\t\tpres = 3;\n+\t\telse\n+\t\t\tpres = 1 << i;\n+\n+\t\treq_parent.rate = req->rate * pres;\n+\t\tif (__clk_determine_rate(parent, &req_parent))\n+\t\t\tcontinue;\n+\n+\t\tclk_sama7g5_master_best_diff(req, parent, req_parent.rate,\n+\t\t\t\t\t     &best_diff, &best_rate, pres);\n+\t\tif (!best_diff)\n+\t\t\tbreak;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int clk_master_pres_set_rate(struct clk_hw *hw, unsigned long rate,\n+\t\t\t\t    unsigned long parent_rate)\n+{\n+\tstruct clk_master *master = to_clk_master(hw);\n+\tunsigned long flags;\n+\tunsigned int pres;\n+\n+\tpres = DIV_ROUND_CLOSEST(parent_rate, rate);\n+\tif (pres > MASTER_PRES_MAX)\n+\t\treturn -EINVAL;\n+\n+\telse if (pres == 3)\n+\t\tpres = MASTER_PRES_MAX;\n+\telse\n+\t\tpres = ffs(pres) - 1;\n+\n+\tspin_lock_irqsave(master->lock, flags);\n+\tregmap_update_bits(master->regmap, master->layout->offset,\n+\t\t\t   (MASTER_PRES_MASK << master->layout->pres_shift),\n+\t\t\t   (pres << master->layout->pres_shift));\n+\n+\twhile (!clk_master_ready(master))\n+\t\tcpu_relax();\n+\tspin_unlock_irqrestore(master->lock, flags);\n+\n+\treturn 0;\n+}\n+\n+static unsigned long clk_master_pres_recalc_rate(struct clk_hw *hw,\n+\t\t\t\t\t\t unsigned long parent_rate)\n+{\n+\tstruct clk_master *master = to_clk_master(hw);\n+\tconst struct clk_master_characteristics *characteristics =\n+\t\t\t\t\t\tmaster->characteristics;\n+\tunsigned long flags;\n+\tunsigned int val, pres;\n+\n+\tspin_lock_irqsave(master->lock, flags);\n+\tregmap_read(master->regmap, master->layout->offset, &val);\n+\tspin_unlock_irqrestore(master->lock, flags);\n+\n+\tpres = (val >> master->layout->pres_shift) & MASTER_PRES_MASK;\n+\tif (pres == 3 && characteristics->have_div3_pres)\n+\t\tpres = 3;\n+\telse\n+\t\tpres = (1 << pres);\n+\n+\treturn DIV_ROUND_CLOSEST_ULL(parent_rate, pres);\n+}\n+\n+static u8 clk_master_pres_get_parent(struct clk_hw *hw)\n {\n \tstruct clk_master *master = to_clk_master(hw);\n+\tunsigned long flags;\n \tunsigned int mckr;\n \n+\tspin_lock_irqsave(master->lock, flags);\n \tregmap_read(master->regmap, master->layout->offset, &mckr);\n+\tspin_unlock_irqrestore(master->lock, flags);\n \n \treturn mckr & AT91_PMC_CSS;\n }\n \n-static const struct clk_ops master_ops = {\n+static const struct clk_ops master_pres_ops = {\n \t.prepare = clk_master_prepare,\n \t.is_prepared = clk_master_is_prepared,\n-\t.recalc_rate = clk_master_recalc_rate,\n-\t.get_parent = clk_master_get_parent,\n+\t.recalc_rate = clk_master_pres_recalc_rate,\n+\t.get_parent = clk_master_pres_get_parent,\n };\n \n-struct clk_hw * __init\n-at91_clk_register_master(struct regmap *regmap,\n+static const struct clk_ops master_pres_ops_chg = {\n+\t.prepare = clk_master_prepare,\n+\t.is_prepared = clk_master_is_prepared,\n+\t.determine_rate = clk_master_pres_determine_rate,\n+\t.recalc_rate = clk_master_pres_recalc_rate,\n+\t.get_parent = clk_master_pres_get_parent,\n+\t.set_rate = clk_master_pres_set_rate,\n+};\n+\n+static struct clk_hw * __init\n+at91_clk_register_master_internal(struct regmap *regmap,\n \t\tconst char *name, int num_parents,\n \t\tconst char **parent_names,\n \t\tconst struct clk_master_layout *layout,\n-\t\tconst struct clk_master_characteristics *characteristics)\n+\t\tconst struct clk_master_characteristics *characteristics,\n+\t\tconst struct clk_ops *ops, spinlock_t *lock, u32 flags,\n+\t\tint chg_pid)\n {\n \tstruct clk_master *master;\n \tstruct clk_init_data init;\n \tstruct clk_hw *hw;\n \tint ret;\n \n-\tif (!name || !num_parents || !parent_names)\n+\tif (!name || !num_parents || !parent_names || !lock)\n \t\treturn ERR_PTR(-EINVAL);\n \n \tmaster = kzalloc(sizeof(*master), GFP_KERNEL);\n@@ -142,15 +368,17 @@ at91_clk_register_master(struct regmap *\n \t\treturn ERR_PTR(-ENOMEM);\n \n \tinit.name = name;\n-\tinit.ops = &master_ops;\n+\tinit.ops = ops;\n \tinit.parent_names = parent_names;\n \tinit.num_parents = num_parents;\n-\tinit.flags = 0;\n+\tinit.flags = flags;\n \n \tmaster->hw.init = &init;\n \tmaster->layout = layout;\n \tmaster->characteristics = characteristics;\n \tmaster->regmap = regmap;\n+\tmaster->chg_pid = chg_pid;\n+\tmaster->lock = lock;\n \n \thw = &master->hw;\n \tret = clk_hw_register(NULL, &master->hw);\n@@ -162,37 +390,54 @@ at91_clk_register_master(struct regmap *\n \treturn hw;\n }\n \n-static unsigned long\n-clk_sama7g5_master_recalc_rate(struct clk_hw *hw,\n-\t\t\t       unsigned long parent_rate)\n+struct clk_hw * __init\n+at91_clk_register_master_pres(struct regmap *regmap,\n+\t\tconst char *name, int num_parents,\n+\t\tconst char **parent_names,\n+\t\tconst struct clk_master_layout *layout,\n+\t\tconst struct clk_master_characteristics *characteristics,\n+\t\tspinlock_t *lock, u32 flags, int chg_pid)\n {\n-\tstruct clk_master *master = to_clk_master(hw);\n+\tconst struct clk_ops *ops;\n \n-\treturn DIV_ROUND_CLOSEST_ULL(parent_rate, (1 << master->div));\n+\tif (flags & CLK_SET_RATE_GATE)\n+\t\tops = &master_pres_ops;\n+\telse\n+\t\tops = &master_pres_ops_chg;\n+\n+\treturn at91_clk_register_master_internal(regmap, name, num_parents,\n+\t\t\t\t\t\t parent_names, layout,\n+\t\t\t\t\t\t characteristics, ops,\n+\t\t\t\t\t\t lock, flags, chg_pid);\n }\n \n-static void clk_sama7g5_master_best_diff(struct clk_rate_request *req,\n-\t\t\t\t\t struct clk_hw *parent,\n-\t\t\t\t\t unsigned long parent_rate,\n-\t\t\t\t\t long *best_rate,\n-\t\t\t\t\t long *best_diff,\n-\t\t\t\t\t u32 div)\n+struct clk_hw * __init\n+at91_clk_register_master_div(struct regmap *regmap,\n+\t\tconst char *name, const char *parent_name,\n+\t\tconst struct clk_master_layout *layout,\n+\t\tconst struct clk_master_characteristics *characteristics,\n+\t\tspinlock_t *lock, u32 flags)\n {\n-\tunsigned long tmp_rate, tmp_diff;\n+\tconst struct clk_ops *ops;\n \n-\tif (div == MASTER_PRES_MAX)\n-\t\ttmp_rate = parent_rate / 3;\n+\tif (flags & CLK_SET_RATE_GATE)\n+\t\tops = &master_div_ops;\n \telse\n-\t\ttmp_rate = parent_rate >> div;\n+\t\tops = &master_div_ops_chg;\n \n-\ttmp_diff = abs(req->rate - tmp_rate);\n+\treturn at91_clk_register_master_internal(regmap, name, 1,\n+\t\t\t\t\t\t &parent_name, layout,\n+\t\t\t\t\t\t characteristics, ops,\n+\t\t\t\t\t\t lock, flags, -EINVAL);\n+}\n \n-\tif (*best_diff < 0 || *best_diff >= tmp_diff) {\n-\t\t*best_rate = tmp_rate;\n-\t\t*best_diff = tmp_diff;\n-\t\treq->best_parent_rate = parent_rate;\n-\t\treq->best_parent_hw = parent;\n-\t}\n+static unsigned long\n+clk_sama7g5_master_recalc_rate(struct clk_hw *hw,\n+\t\t\t       unsigned long parent_rate)\n+{\n+\tstruct clk_master *master = to_clk_master(hw);\n+\n+\treturn DIV_ROUND_CLOSEST_ULL(parent_rate, (1 << master->div));\n }\n \n static int clk_sama7g5_master_determine_rate(struct clk_hw *hw,\n--- a/drivers/clk/at91/dt-compat.c\n+++ b/drivers/clk/at91/dt-compat.c\n@@ -24,6 +24,8 @@\n \n #define GCK_INDEX_DT_AUDIO_PLL\t5\n \n+static DEFINE_SPINLOCK(mck_lock);\n+\n #ifdef CONFIG_HAVE_AT91_AUDIO_PLL\n static void __init of_sama5d2_clk_audio_pll_frac_setup(struct device_node *np)\n {\n@@ -388,9 +390,16 @@ of_at91_clk_master_setup(struct device_n\n \tif (IS_ERR(regmap))\n \t\treturn;\n \n-\thw = at91_clk_register_master(regmap, name, num_parents,\n-\t\t\t\t      parent_names, layout,\n-\t\t\t\t      characteristics);\n+\thw = at91_clk_register_master_pres(regmap, \"masterck_pres\", num_parents,\n+\t\t\t\t\t   parent_names, layout,\n+\t\t\t\t\t   characteristics, &mck_lock,\n+\t\t\t\t\t   CLK_SET_RATE_GATE, INT_MIN);\n+\tif (IS_ERR(hw))\n+\t\tgoto out_free_characteristics;\n+\n+\thw = at91_clk_register_master_div(regmap, name, \"masterck_pres\",\n+\t\t\t\t\t  layout, characteristics,\n+\t\t\t\t\t  &mck_lock, CLK_SET_RATE_GATE);\n \tif (IS_ERR(hw))\n \t\tgoto out_free_characteristics;\n \n--- a/drivers/clk/at91/pmc.h\n+++ b/drivers/clk/at91/pmc.h\n@@ -155,10 +155,18 @@ at91_clk_register_sam9x5_main(struct reg\n \t\t\t      const char **parent_names, int num_parents);\n \n struct clk_hw * __init\n-at91_clk_register_master(struct regmap *regmap, const char *name,\n-\t\t\t int num_parents, const char **parent_names,\n-\t\t\t const struct clk_master_layout *layout,\n-\t\t\t const struct clk_master_characteristics *characteristics);\n+at91_clk_register_master_pres(struct regmap *regmap, const char *name,\n+\t\t\t      int num_parents, const char **parent_names,\n+\t\t\t      const struct clk_master_layout *layout,\n+\t\t\t      const struct clk_master_characteristics *characteristics,\n+\t\t\t      spinlock_t *lock, u32 flags, int chg_pid);\n+\n+struct clk_hw * __init\n+at91_clk_register_master_div(struct regmap *regmap, const char *name,\n+\t\t\t     const char *parent_names,\n+\t\t\t     const struct clk_master_layout *layout,\n+\t\t\t     const struct clk_master_characteristics *characteristics,\n+\t\t\t     spinlock_t *lock, u32 flags);\n \n struct clk_hw * __init\n at91_clk_sama7g5_register_master(struct regmap *regmap,\n--- a/drivers/clk/at91/sam9x60.c\n+++ b/drivers/clk/at91/sam9x60.c\n@@ -8,6 +8,7 @@\n #include \"pmc.h\"\n \n static DEFINE_SPINLOCK(pmc_pll_lock);\n+static DEFINE_SPINLOCK(mck_lock);\n \n static const struct clk_master_characteristics mck_characteristics = {\n \t.output = { .min = 140000000, .max = 200000000 },\n@@ -76,11 +77,11 @@ static const struct {\n \tchar *p;\n \tu8 id;\n } sam9x60_systemck[] = {\n-\t{ .n = \"ddrck\",  .p = \"masterck\", .id = 2 },\n+\t{ .n = \"ddrck\",  .p = \"masterck_div\", .id = 2 },\n \t{ .n = \"uhpck\",  .p = \"usbck\",    .id = 6 },\n \t{ .n = \"pck0\",   .p = \"prog0\",    .id = 8 },\n \t{ .n = \"pck1\",   .p = \"prog1\",    .id = 9 },\n-\t{ .n = \"qspick\", .p = \"masterck\", .id = 19 },\n+\t{ .n = \"qspick\", .p = \"masterck_div\", .id = 19 },\n };\n \n static const struct {\n@@ -268,9 +269,17 @@ static void __init sam9x60_pmc_setup(str\n \tparent_names[0] = md_slck_name;\n \tparent_names[1] = \"mainck\";\n \tparent_names[2] = \"pllack_divck\";\n-\thw = at91_clk_register_master(regmap, \"masterck\", 3, parent_names,\n-\t\t\t\t      &sam9x60_master_layout,\n-\t\t\t\t      &mck_characteristics);\n+\thw = at91_clk_register_master_pres(regmap, \"masterck_pres\", 3,\n+\t\t\t\t\t   parent_names, &sam9x60_master_layout,\n+\t\t\t\t\t   &mck_characteristics, &mck_lock,\n+\t\t\t\t\t   CLK_SET_RATE_GATE, INT_MIN);\n+\tif (IS_ERR(hw))\n+\t\tgoto err_free;\n+\n+\thw = at91_clk_register_master_div(regmap, \"masterck_div\",\n+\t\t\t\t\t  \"masterck_pres\", &sam9x60_master_layout,\n+\t\t\t\t\t  &mck_characteristics, &mck_lock,\n+\t\t\t\t\t  CLK_SET_RATE_GATE);\n \tif (IS_ERR(hw))\n \t\tgoto err_free;\n \n@@ -286,7 +295,7 @@ static void __init sam9x60_pmc_setup(str\n \tparent_names[0] = md_slck_name;\n \tparent_names[1] = td_slck_name;\n \tparent_names[2] = \"mainck\";\n-\tparent_names[3] = \"masterck\";\n+\tparent_names[3] = \"masterck_div\";\n \tparent_names[4] = \"pllack_divck\";\n \tparent_names[5] = \"upllck_divck\";\n \tfor (i = 0; i < 2; i++) {\n@@ -318,7 +327,7 @@ static void __init sam9x60_pmc_setup(str\n \t\thw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,\n \t\t\t\t\t\t\t &sam9x60_pcr_layout,\n \t\t\t\t\t\t\t sam9x60_periphck[i].n,\n-\t\t\t\t\t\t\t \"masterck\",\n+\t\t\t\t\t\t\t \"masterck_div\",\n \t\t\t\t\t\t\t sam9x60_periphck[i].id,\n \t\t\t\t\t\t\t &range, INT_MIN);\n \t\tif (IS_ERR(hw))\n--- a/drivers/clk/at91/sama5d2.c\n+++ b/drivers/clk/at91/sama5d2.c\n@@ -7,6 +7,8 @@\n \n #include \"pmc.h\"\n \n+static DEFINE_SPINLOCK(mck_lock);\n+\n static const struct clk_master_characteristics mck_characteristics = {\n \t.output = { .min = 124000000, .max = 166000000 },\n \t.divisors = { 1, 2, 4, 3 },\n@@ -40,14 +42,14 @@ static const struct {\n \tchar *p;\n \tu8 id;\n } sama5d2_systemck[] = {\n-\t{ .n = \"ddrck\", .p = \"masterck\", .id = 2 },\n-\t{ .n = \"lcdck\", .p = \"masterck\", .id = 3 },\n-\t{ .n = \"uhpck\", .p = \"usbck\",    .id = 6 },\n-\t{ .n = \"udpck\", .p = \"usbck\",    .id = 7 },\n-\t{ .n = \"pck0\",  .p = \"prog0\",    .id = 8 },\n-\t{ .n = \"pck1\",  .p = \"prog1\",    .id = 9 },\n-\t{ .n = \"pck2\",  .p = \"prog2\",    .id = 10 },\n-\t{ .n = \"iscck\", .p = \"masterck\", .id = 18 },\n+\t{ .n = \"ddrck\", .p = \"masterck_div\", .id = 2 },\n+\t{ .n = \"lcdck\", .p = \"masterck_div\", .id = 3 },\n+\t{ .n = \"uhpck\", .p = \"usbck\",        .id = 6 },\n+\t{ .n = \"udpck\", .p = \"usbck\",        .id = 7 },\n+\t{ .n = \"pck0\",  .p = \"prog0\",        .id = 8 },\n+\t{ .n = \"pck1\",  .p = \"prog1\",        .id = 9 },\n+\t{ .n = \"pck2\",  .p = \"prog2\",        .id = 10 },\n+\t{ .n = \"iscck\", .p = \"masterck_div\", .id = 18 },\n };\n \n static const struct {\n@@ -235,15 +237,25 @@ static void __init sama5d2_pmc_setup(str\n \tparent_names[1] = \"mainck\";\n \tparent_names[2] = \"plladivck\";\n \tparent_names[3] = \"utmick\";\n-\thw = at91_clk_register_master(regmap, \"masterck\", 4, parent_names,\n-\t\t\t\t      &at91sam9x5_master_layout,\n-\t\t\t\t      &mck_characteristics);\n+\thw = at91_clk_register_master_pres(regmap, \"masterck_pres\", 4,\n+\t\t\t\t\t   parent_names,\n+\t\t\t\t\t   &at91sam9x5_master_layout,\n+\t\t\t\t\t   &mck_characteristics, &mck_lock,\n+\t\t\t\t\t   CLK_SET_RATE_GATE, INT_MIN);\n+\tif (IS_ERR(hw))\n+\t\tgoto err_free;\n+\n+\thw = at91_clk_register_master_div(regmap, \"masterck_div\",\n+\t\t\t\t\t  \"masterck_pres\",\n+\t\t\t\t\t  &at91sam9x5_master_layout,\n+\t\t\t\t\t  &mck_characteristics, &mck_lock,\n+\t\t\t\t\t  CLK_SET_RATE_GATE);\n \tif (IS_ERR(hw))\n \t\tgoto err_free;\n \n \tsama5d2_pmc->chws[PMC_MCK] = hw;\n \n-\thw = at91_clk_register_h32mx(regmap, \"h32mxck\", \"masterck\");\n+\thw = at91_clk_register_h32mx(regmap, \"h32mxck\", \"masterck_div\");\n \tif (IS_ERR(hw))\n \t\tgoto err_free;\n \n@@ -259,7 +271,7 @@ static void __init sama5d2_pmc_setup(str\n \tparent_names[1] = \"mainck\";\n \tparent_names[2] = \"plladivck\";\n \tparent_names[3] = \"utmick\";\n-\tparent_names[4] = \"masterck\";\n+\tparent_names[4] = \"masterck_div\";\n \tparent_names[5] = \"audiopll_pmcck\";\n \tfor (i = 0; i < 3; i++) {\n \t\tchar name[6];\n@@ -290,7 +302,7 @@ static void __init sama5d2_pmc_setup(str\n \t\thw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,\n \t\t\t\t\t\t\t &sama5d2_pcr_layout,\n \t\t\t\t\t\t\t sama5d2_periphck[i].n,\n-\t\t\t\t\t\t\t \"masterck\",\n+\t\t\t\t\t\t\t \"masterck_div\",\n \t\t\t\t\t\t\t sama5d2_periphck[i].id,\n \t\t\t\t\t\t\t &range, INT_MIN);\n \t\tif (IS_ERR(hw))\n@@ -317,7 +329,7 @@ static void __init sama5d2_pmc_setup(str\n \tparent_names[1] = \"mainck\";\n \tparent_names[2] = \"plladivck\";\n \tparent_names[3] = \"utmick\";\n-\tparent_names[4] = \"masterck\";\n+\tparent_names[4] = \"masterck_div\";\n \tparent_names[5] = \"audiopll_pmcck\";\n \tfor (i = 0; i < ARRAY_SIZE(sama5d2_gck); i++) {\n \t\thw = at91_clk_register_generated(regmap, &pmc_pcr_lock,\n--- a/drivers/clk/at91/sama5d3.c\n+++ b/drivers/clk/at91/sama5d3.c\n@@ -7,6 +7,8 @@\n \n #include \"pmc.h\"\n \n+static DEFINE_SPINLOCK(mck_lock);\n+\n static const struct clk_master_characteristics mck_characteristics = {\n \t.output = { .min = 0, .max = 166000000 },\n \t.divisors = { 1, 2, 4, 3 },\n@@ -40,14 +42,14 @@ static const struct {\n \tchar *p;\n \tu8 id;\n } sama5d3_systemck[] = {\n-\t{ .n = \"ddrck\", .p = \"masterck\", .id = 2 },\n-\t{ .n = \"lcdck\", .p = \"masterck\", .id = 3 },\n-\t{ .n = \"smdck\", .p = \"smdclk\",   .id = 4 },\n-\t{ .n = \"uhpck\", .p = \"usbck\",    .id = 6 },\n-\t{ .n = \"udpck\", .p = \"usbck\",    .id = 7 },\n-\t{ .n = \"pck0\",  .p = \"prog0\",    .id = 8 },\n-\t{ .n = \"pck1\",  .p = \"prog1\",    .id = 9 },\n-\t{ .n = \"pck2\",  .p = \"prog2\",    .id = 10 },\n+\t{ .n = \"ddrck\", .p = \"masterck_div\", .id = 2 },\n+\t{ .n = \"lcdck\", .p = \"masterck_div\", .id = 3 },\n+\t{ .n = \"smdck\", .p = \"smdclk\",       .id = 4 },\n+\t{ .n = \"uhpck\", .p = \"usbck\",        .id = 6 },\n+\t{ .n = \"udpck\", .p = \"usbck\",        .id = 7 },\n+\t{ .n = \"pck0\",  .p = \"prog0\",        .id = 8 },\n+\t{ .n = \"pck1\",  .p = \"prog1\",        .id = 9 },\n+\t{ .n = \"pck2\",  .p = \"prog2\",        .id = 10 },\n };\n \n static const struct {\n@@ -170,9 +172,19 @@ static void __init sama5d3_pmc_setup(str\n \tparent_names[1] = \"mainck\";\n \tparent_names[2] = \"plladivck\";\n \tparent_names[3] = \"utmick\";\n-\thw = at91_clk_register_master(regmap, \"masterck\", 4, parent_names,\n-\t\t\t\t      &at91sam9x5_master_layout,\n-\t\t\t\t      &mck_characteristics);\n+\thw = at91_clk_register_master_pres(regmap, \"masterck_pres\", 4,\n+\t\t\t\t\t   parent_names,\n+\t\t\t\t\t   &at91sam9x5_master_layout,\n+\t\t\t\t\t   &mck_characteristics, &mck_lock,\n+\t\t\t\t\t   CLK_SET_RATE_GATE, INT_MIN);\n+\tif (IS_ERR(hw))\n+\t\tgoto err_free;\n+\n+\thw = at91_clk_register_master_div(regmap, \"masterck_div\",\n+\t\t\t\t\t  \"masterck_pres\",\n+\t\t\t\t\t  &at91sam9x5_master_layout,\n+\t\t\t\t\t  &mck_characteristics, &mck_lock,\n+\t\t\t\t\t  CLK_SET_RATE_GATE);\n \tif (IS_ERR(hw))\n \t\tgoto err_free;\n \n@@ -192,7 +204,7 @@ static void __init sama5d3_pmc_setup(str\n \tparent_names[1] = \"mainck\";\n \tparent_names[2] = \"plladivck\";\n \tparent_names[3] = \"utmick\";\n-\tparent_names[4] = \"masterck\";\n+\tparent_names[4] = \"masterck_div\";\n \tfor (i = 0; i < 3; i++) {\n \t\tchar name[6];\n \n@@ -222,7 +234,7 @@ static void __init sama5d3_pmc_setup(str\n \t\thw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,\n \t\t\t\t\t\t\t &sama5d3_pcr_layout,\n \t\t\t\t\t\t\t sama5d3_periphck[i].n,\n-\t\t\t\t\t\t\t \"masterck\",\n+\t\t\t\t\t\t\t \"masterck_div\",\n \t\t\t\t\t\t\t sama5d3_periphck[i].id,\n \t\t\t\t\t\t\t &sama5d3_periphck[i].r,\n \t\t\t\t\t\t\t INT_MIN);\n--- a/drivers/clk/at91/sama5d4.c\n+++ b/drivers/clk/at91/sama5d4.c\n@@ -7,6 +7,8 @@\n \n #include \"pmc.h\"\n \n+static DEFINE_SPINLOCK(mck_lock);\n+\n static const struct clk_master_characteristics mck_characteristics = {\n \t.output = { .min = 125000000, .max = 200000000 },\n \t.divisors = { 1, 2, 4, 3 },\n@@ -39,14 +41,14 @@ static const struct {\n \tchar *p;\n \tu8 id;\n } sama5d4_systemck[] = {\n-\t{ .n = \"ddrck\", .p = \"masterck\", .id = 2 },\n-\t{ .n = \"lcdck\", .p = \"masterck\", .id = 3 },\n-\t{ .n = \"smdck\", .p = \"smdclk\",   .id = 4 },\n-\t{ .n = \"uhpck\", .p = \"usbck\",    .id = 6 },\n-\t{ .n = \"udpck\", .p = \"usbck\",    .id = 7 },\n-\t{ .n = \"pck0\",  .p = \"prog0\",    .id = 8 },\n-\t{ .n = \"pck1\",  .p = \"prog1\",    .id = 9 },\n-\t{ .n = \"pck2\",  .p = \"prog2\",    .id = 10 },\n+\t{ .n = \"ddrck\", .p = \"masterck_div\", .id = 2 },\n+\t{ .n = \"lcdck\", .p = \"masterck_div\", .id = 3 },\n+\t{ .n = \"smdck\", .p = \"smdclk\",       .id = 4 },\n+\t{ .n = \"uhpck\", .p = \"usbck\",        .id = 6 },\n+\t{ .n = \"udpck\", .p = \"usbck\",        .id = 7 },\n+\t{ .n = \"pck0\",  .p = \"prog0\",        .id = 8 },\n+\t{ .n = \"pck1\",  .p = \"prog1\",        .id = 9 },\n+\t{ .n = \"pck2\",  .p = \"prog2\",        .id = 10 },\n };\n \n static const struct {\n@@ -185,15 +187,25 @@ static void __init sama5d4_pmc_setup(str\n \tparent_names[1] = \"mainck\";\n \tparent_names[2] = \"plladivck\";\n \tparent_names[3] = \"utmick\";\n-\thw = at91_clk_register_master(regmap, \"masterck\", 4, parent_names,\n-\t\t\t\t      &at91sam9x5_master_layout,\n-\t\t\t\t      &mck_characteristics);\n+\thw = at91_clk_register_master_pres(regmap, \"masterck_pres\", 4,\n+\t\t\t\t\t   parent_names,\n+\t\t\t\t\t   &at91sam9x5_master_layout,\n+\t\t\t\t\t   &mck_characteristics, &mck_lock,\n+\t\t\t\t\t   CLK_SET_RATE_GATE, INT_MIN);\n+\tif (IS_ERR(hw))\n+\t\tgoto err_free;\n+\n+\thw = at91_clk_register_master_div(regmap, \"masterck_div\",\n+\t\t\t\t\t  \"masterck_pres\",\n+\t\t\t\t\t  &at91sam9x5_master_layout,\n+\t\t\t\t\t  &mck_characteristics, &mck_lock,\n+\t\t\t\t\t  CLK_SET_RATE_GATE);\n \tif (IS_ERR(hw))\n \t\tgoto err_free;\n \n \tsama5d4_pmc->chws[PMC_MCK] = hw;\n \n-\thw = at91_clk_register_h32mx(regmap, \"h32mxck\", \"masterck\");\n+\thw = at91_clk_register_h32mx(regmap, \"h32mxck\", \"masterck_div\");\n \tif (IS_ERR(hw))\n \t\tgoto err_free;\n \n@@ -215,7 +227,7 @@ static void __init sama5d4_pmc_setup(str\n \tparent_names[1] = \"mainck\";\n \tparent_names[2] = \"plladivck\";\n \tparent_names[3] = \"utmick\";\n-\tparent_names[4] = \"masterck\";\n+\tparent_names[4] = \"masterck_div\";\n \tfor (i = 0; i < 3; i++) {\n \t\tchar name[6];\n \n@@ -245,7 +257,7 @@ static void __init sama5d4_pmc_setup(str\n \t\thw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,\n \t\t\t\t\t\t\t &sama5d4_pcr_layout,\n \t\t\t\t\t\t\t sama5d4_periphck[i].n,\n-\t\t\t\t\t\t\t \"masterck\",\n+\t\t\t\t\t\t\t \"masterck_div\",\n \t\t\t\t\t\t\t sama5d4_periphck[i].id,\n \t\t\t\t\t\t\t &range, INT_MIN);\n \t\tif (IS_ERR(hw))\n--- a/drivers/clk/at91/sama7g5.c\n+++ b/drivers/clk/at91/sama7g5.c\n@@ -32,6 +32,7 @@\n \t} while (0)\n \n static DEFINE_SPINLOCK(pmc_pll_lock);\n+static DEFINE_SPINLOCK(pmc_mck0_lock);\n static DEFINE_SPINLOCK(pmc_mckX_lock);\n \n /**\n@@ -984,8 +985,16 @@ static void __init sama7g5_pmc_setup(str\n \tparent_names[1] = \"mainck\";\n \tparent_names[2] = \"cpupll_divpmcck\";\n \tparent_names[3] = \"syspll_divpmcck\";\n-\thw = at91_clk_register_master(regmap, \"mck0\", 4, parent_names,\n-\t\t\t\t      &mck0_layout, &mck0_characteristics);\n+\thw = at91_clk_register_master_pres(regmap, \"mck0_pres\", 4, parent_names,\n+\t\t\t\t\t   &mck0_layout, &mck0_characteristics,\n+\t\t\t\t\t   &pmc_mck0_lock,\n+\t\t\t\t\t   CLK_SET_RATE_PARENT, 0);\n+\tif (IS_ERR(hw))\n+\t\tgoto err_free;\n+\n+\thw = at91_clk_register_master_div(regmap, \"mck0_div\", \"mck0_pres\",\n+\t\t\t\t\t  &mck0_layout, &mck0_characteristics,\n+\t\t\t\t\t  &pmc_mck0_lock, 0);\n \tif (IS_ERR(hw))\n \t\tgoto err_free;\n \n"
  },
  {
    "path": "target/linux/at91/patches-5.10/111-clk-at91-sama7g5-register-cpu-clock.patch",
    "content": "From 36e97c421dd9f866e31fe14bcb7af01334791890 Mon Sep 17 00:00:00 2001\nFrom: Claudiu Beznea <claudiu.beznea@microchip.com>\nDate: Thu, 19 Nov 2020 17:43:17 +0200\nSubject: [PATCH 111/247] clk: at91: sama7g5: register cpu clock\n\nRegister CPU clock as being the master clock prescaler. This would\nbe used by DVFS. The block schema of SAMA7G5's PMC contains also a divider\nbetween master clock prescaler and CPU (PMC_CPU_RATIO.RATIO) but the\nfrequencies supported by SAMA7G5 could be directly received from\nCPUPLL + master clock prescaler and the extra divider would do no work in\ncase it would be enabled.\n\nSigned-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>\nLink: https://lore.kernel.org/r/1605800597-16720-12-git-send-email-claudiu.beznea@microchip.com\nSigned-off-by: Stephen Boyd <sboyd@kernel.org>\n---\n drivers/clk/at91/sama7g5.c       | 13 ++++++-------\n include/dt-bindings/clock/at91.h |  1 +\n 2 files changed, 7 insertions(+), 7 deletions(-)\n\n--- a/drivers/clk/at91/sama7g5.c\n+++ b/drivers/clk/at91/sama7g5.c\n@@ -904,7 +904,7 @@ static void __init sama7g5_pmc_setup(str\n \tif (IS_ERR(regmap))\n \t\treturn;\n \n-\tsama7g5_pmc = pmc_data_allocate(PMC_ETHPLL + 1,\n+\tsama7g5_pmc = pmc_data_allocate(PMC_CPU + 1,\n \t\t\t\t\tnck(sama7g5_systemck),\n \t\t\t\t\tnck(sama7g5_periphck),\n \t\t\t\t\tnck(sama7g5_gck), 8);\n@@ -981,18 +981,17 @@ static void __init sama7g5_pmc_setup(str\n \t\t}\n \t}\n \n-\tparent_names[0] = md_slck_name;\n-\tparent_names[1] = \"mainck\";\n-\tparent_names[2] = \"cpupll_divpmcck\";\n-\tparent_names[3] = \"syspll_divpmcck\";\n-\thw = at91_clk_register_master_pres(regmap, \"mck0_pres\", 4, parent_names,\n+\tparent_names[0] = \"cpupll_divpmcck\";\n+\thw = at91_clk_register_master_pres(regmap, \"cpuck\", 1, parent_names,\n \t\t\t\t\t   &mck0_layout, &mck0_characteristics,\n \t\t\t\t\t   &pmc_mck0_lock,\n \t\t\t\t\t   CLK_SET_RATE_PARENT, 0);\n \tif (IS_ERR(hw))\n \t\tgoto err_free;\n \n-\thw = at91_clk_register_master_div(regmap, \"mck0_div\", \"mck0_pres\",\n+\tsama7g5_pmc->chws[PMC_CPU] = hw;\n+\n+\thw = at91_clk_register_master_div(regmap, \"mck0\", \"cpuck\",\n \t\t\t\t\t  &mck0_layout, &mck0_characteristics,\n \t\t\t\t\t  &pmc_mck0_lock, 0);\n \tif (IS_ERR(hw))\n--- a/include/dt-bindings/clock/at91.h\n+++ b/include/dt-bindings/clock/at91.h\n@@ -34,6 +34,7 @@\n #define PMC_AUDIOPMCPLL\t\t(PMC_MAIN + 6)\n #define PMC_AUDIOIOPLL\t\t(PMC_MAIN + 7)\n #define PMC_ETHPLL\t\t(PMC_MAIN + 8)\n+#define PMC_CPU\t\t\t(PMC_MAIN + 9)\n \n #ifndef AT91_PMC_MOSCS\n #define AT91_PMC_MOSCS\t\t0\t\t/* MOSCS Flag */\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/112-clk-at91-Fix-the-declaration-of-the-clocks.patch",
    "content": "From 5a25e2437af0db535b17da352fb16680a8dfdeda Mon Sep 17 00:00:00 2001\nFrom: Tudor Ambarus <tudor.ambarus@microchip.com>\nDate: Wed, 3 Feb 2021 17:43:32 +0200\nSubject: [PATCH 112/247] clk: at91: Fix the declaration of the clocks\n\nThese are all \"early clocks\" that require initialization just at\nof_clk_init() time. Use CLK_OF_DECLARE() to declare them.\n\nThis also fixes a problem that was spotted when fw_devlink was\nset to 'on' by default: the boards failed to boot. The reason is\nthat CLK_OF_DECLARE_DRIVER() clears the OF_POPULATED and causes\nthe consumers of the clock to be postponed by fw_devlink until\nthe second initialization routine of the clock has been completed.\nOne of the consumers of the clock is the timer, which is used as a\nclocksource, and needs the clock initialized early. Postponing the\ntimers caused the fail at boot.\n\nSigned-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>\nLink: https://lore.kernel.org/r/20210203154332.470587-1-tudor.ambarus@microchip.com\nAcked-by: Saravana Kannan <saravanak@google.com>\nTested-by: Eugen Hristev <eugen.hristev@microchip.com>\nAcked-by: Nicolas Ferre <nicolas.ferre@microchip.com>\nReviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>\nSigned-off-by: Stephen Boyd <sboyd@kernel.org>\n---\n drivers/clk/at91/at91rm9200.c  |  3 +--\n drivers/clk/at91/at91sam9260.c | 16 ++++++++--------\n drivers/clk/at91/at91sam9g45.c |  3 +--\n drivers/clk/at91/at91sam9n12.c |  3 +--\n drivers/clk/at91/at91sam9rl.c  |  3 ++-\n drivers/clk/at91/at91sam9x5.c  | 20 ++++++++++----------\n drivers/clk/at91/sama5d2.c     |  3 ++-\n drivers/clk/at91/sama5d3.c     |  2 +-\n drivers/clk/at91/sama5d4.c     |  3 ++-\n 9 files changed, 28 insertions(+), 28 deletions(-)\n\n--- a/drivers/clk/at91/at91rm9200.c\n+++ b/drivers/clk/at91/at91rm9200.c\n@@ -215,5 +215,4 @@ err_free:\n  * deferring properly. Once this is fixed, this can be switched to a platform\n  * driver.\n  */\n-CLK_OF_DECLARE_DRIVER(at91rm9200_pmc, \"atmel,at91rm9200-pmc\",\n-\t\t      at91rm9200_pmc_setup);\n+CLK_OF_DECLARE(at91rm9200_pmc, \"atmel,at91rm9200-pmc\", at91rm9200_pmc_setup);\n--- a/drivers/clk/at91/at91sam9260.c\n+++ b/drivers/clk/at91/at91sam9260.c\n@@ -491,26 +491,26 @@ static void __init at91sam9260_pmc_setup\n {\n \tat91sam926x_pmc_setup(np, &at91sam9260_data);\n }\n-CLK_OF_DECLARE_DRIVER(at91sam9260_pmc, \"atmel,at91sam9260-pmc\",\n-\t\t      at91sam9260_pmc_setup);\n+\n+CLK_OF_DECLARE(at91sam9260_pmc, \"atmel,at91sam9260-pmc\", at91sam9260_pmc_setup);\n \n static void __init at91sam9261_pmc_setup(struct device_node *np)\n {\n \tat91sam926x_pmc_setup(np, &at91sam9261_data);\n }\n-CLK_OF_DECLARE_DRIVER(at91sam9261_pmc, \"atmel,at91sam9261-pmc\",\n-\t\t      at91sam9261_pmc_setup);\n+\n+CLK_OF_DECLARE(at91sam9261_pmc, \"atmel,at91sam9261-pmc\", at91sam9261_pmc_setup);\n \n static void __init at91sam9263_pmc_setup(struct device_node *np)\n {\n \tat91sam926x_pmc_setup(np, &at91sam9263_data);\n }\n-CLK_OF_DECLARE_DRIVER(at91sam9263_pmc, \"atmel,at91sam9263-pmc\",\n-\t\t      at91sam9263_pmc_setup);\n+\n+CLK_OF_DECLARE(at91sam9263_pmc, \"atmel,at91sam9263-pmc\", at91sam9263_pmc_setup);\n \n static void __init at91sam9g20_pmc_setup(struct device_node *np)\n {\n \tat91sam926x_pmc_setup(np, &at91sam9g20_data);\n }\n-CLK_OF_DECLARE_DRIVER(at91sam9g20_pmc, \"atmel,at91sam9g20-pmc\",\n-\t\t      at91sam9g20_pmc_setup);\n+\n+CLK_OF_DECLARE(at91sam9g20_pmc, \"atmel,at91sam9g20-pmc\", at91sam9g20_pmc_setup);\n--- a/drivers/clk/at91/at91sam9g45.c\n+++ b/drivers/clk/at91/at91sam9g45.c\n@@ -228,5 +228,4 @@ err_free:\n  * The TCB is used as the clocksource so its clock is needed early. This means\n  * this can't be a platform driver.\n  */\n-CLK_OF_DECLARE_DRIVER(at91sam9g45_pmc, \"atmel,at91sam9g45-pmc\",\n-\t\t      at91sam9g45_pmc_setup);\n+CLK_OF_DECLARE(at91sam9g45_pmc, \"atmel,at91sam9g45-pmc\", at91sam9g45_pmc_setup);\n--- a/drivers/clk/at91/at91sam9n12.c\n+++ b/drivers/clk/at91/at91sam9n12.c\n@@ -255,5 +255,4 @@ err_free:\n  * The TCB is used as the clocksource so its clock is needed early. This means\n  * this can't be a platform driver.\n  */\n-CLK_OF_DECLARE_DRIVER(at91sam9n12_pmc, \"atmel,at91sam9n12-pmc\",\n-\t\t      at91sam9n12_pmc_setup);\n+CLK_OF_DECLARE(at91sam9n12_pmc, \"atmel,at91sam9n12-pmc\", at91sam9n12_pmc_setup);\n--- a/drivers/clk/at91/at91sam9rl.c\n+++ b/drivers/clk/at91/at91sam9rl.c\n@@ -186,4 +186,5 @@ static void __init at91sam9rl_pmc_setup(\n err_free:\n \tkfree(at91sam9rl_pmc);\n }\n-CLK_OF_DECLARE_DRIVER(at91sam9rl_pmc, \"atmel,at91sam9rl-pmc\", at91sam9rl_pmc_setup);\n+\n+CLK_OF_DECLARE(at91sam9rl_pmc, \"atmel,at91sam9rl-pmc\", at91sam9rl_pmc_setup);\n--- a/drivers/clk/at91/at91sam9x5.c\n+++ b/drivers/clk/at91/at91sam9x5.c\n@@ -302,33 +302,33 @@ static void __init at91sam9g15_pmc_setup\n {\n \tat91sam9x5_pmc_setup(np, at91sam9g15_periphck, true);\n }\n-CLK_OF_DECLARE_DRIVER(at91sam9g15_pmc, \"atmel,at91sam9g15-pmc\",\n-\t\t      at91sam9g15_pmc_setup);\n+\n+CLK_OF_DECLARE(at91sam9g15_pmc, \"atmel,at91sam9g15-pmc\", at91sam9g15_pmc_setup);\n \n static void __init at91sam9g25_pmc_setup(struct device_node *np)\n {\n \tat91sam9x5_pmc_setup(np, at91sam9g25_periphck, false);\n }\n-CLK_OF_DECLARE_DRIVER(at91sam9g25_pmc, \"atmel,at91sam9g25-pmc\",\n-\t\t      at91sam9g25_pmc_setup);\n+\n+CLK_OF_DECLARE(at91sam9g25_pmc, \"atmel,at91sam9g25-pmc\", at91sam9g25_pmc_setup);\n \n static void __init at91sam9g35_pmc_setup(struct device_node *np)\n {\n \tat91sam9x5_pmc_setup(np, at91sam9g35_periphck, true);\n }\n-CLK_OF_DECLARE_DRIVER(at91sam9g35_pmc, \"atmel,at91sam9g35-pmc\",\n-\t\t      at91sam9g35_pmc_setup);\n+\n+CLK_OF_DECLARE(at91sam9g35_pmc, \"atmel,at91sam9g35-pmc\", at91sam9g35_pmc_setup);\n \n static void __init at91sam9x25_pmc_setup(struct device_node *np)\n {\n \tat91sam9x5_pmc_setup(np, at91sam9x25_periphck, false);\n }\n-CLK_OF_DECLARE_DRIVER(at91sam9x25_pmc, \"atmel,at91sam9x25-pmc\",\n-\t\t      at91sam9x25_pmc_setup);\n+\n+CLK_OF_DECLARE(at91sam9x25_pmc, \"atmel,at91sam9x25-pmc\", at91sam9x25_pmc_setup);\n \n static void __init at91sam9x35_pmc_setup(struct device_node *np)\n {\n \tat91sam9x5_pmc_setup(np, at91sam9x35_periphck, true);\n }\n-CLK_OF_DECLARE_DRIVER(at91sam9x35_pmc, \"atmel,at91sam9x35-pmc\",\n-\t\t      at91sam9x35_pmc_setup);\n+\n+CLK_OF_DECLARE(at91sam9x35_pmc, \"atmel,at91sam9x35-pmc\", at91sam9x35_pmc_setup);\n--- a/drivers/clk/at91/sama5d2.c\n+++ b/drivers/clk/at91/sama5d2.c\n@@ -372,4 +372,5 @@ static void __init sama5d2_pmc_setup(str\n err_free:\n \tkfree(sama5d2_pmc);\n }\n-CLK_OF_DECLARE_DRIVER(sama5d2_pmc, \"atmel,sama5d2-pmc\", sama5d2_pmc_setup);\n+\n+CLK_OF_DECLARE(sama5d2_pmc, \"atmel,sama5d2-pmc\", sama5d2_pmc_setup);\n--- a/drivers/clk/at91/sama5d3.c\n+++ b/drivers/clk/at91/sama5d3.c\n@@ -255,4 +255,4 @@ err_free:\n  * The TCB is used as the clocksource so its clock is needed early. This means\n  * this can't be a platform driver.\n  */\n-CLK_OF_DECLARE_DRIVER(sama5d3_pmc, \"atmel,sama5d3-pmc\", sama5d3_pmc_setup);\n+CLK_OF_DECLARE(sama5d3_pmc, \"atmel,sama5d3-pmc\", sama5d3_pmc_setup);\n--- a/drivers/clk/at91/sama5d4.c\n+++ b/drivers/clk/at91/sama5d4.c\n@@ -286,4 +286,5 @@ static void __init sama5d4_pmc_setup(str\n err_free:\n \tkfree(sama5d4_pmc);\n }\n-CLK_OF_DECLARE_DRIVER(sama5d4_pmc, \"atmel,sama5d4-pmc\", sama5d4_pmc_setup);\n+\n+CLK_OF_DECLARE(sama5d4_pmc, \"atmel,sama5d4-pmc\", sama5d4_pmc_setup);\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/113-clk-at91-Trivial-typo-fixes-in-the-file-sama7g5.c.patch",
    "content": "From 268b36c42b7d1e480dd56ecfec626a46f4b5975e Mon Sep 17 00:00:00 2001\nFrom: Bhaskar Chowdhury <unixbhaskar@gmail.com>\nDate: Sat, 13 Mar 2021 11:02:22 +0530\nSubject: [PATCH 113/247] clk: at91: Trivial typo fixes in the file sama7g5.c\n\ns/critial/critical/  ......two different places\ns/parrent/parent/\n\nSigned-off-by: Bhaskar Chowdhury <unixbhaskar@gmail.com>\nLink: https://lore.kernel.org/r/20210313053222.14706-1-unixbhaskar@gmail.com\nAcked-by: Randy Dunlap <rdunlap@infradead.org>\nSigned-off-by: Stephen Boyd <sboyd@kernel.org>\n---\n drivers/clk/at91/sama7g5.c | 6 +++---\n 1 file changed, 3 insertions(+), 3 deletions(-)\n\n--- a/drivers/clk/at91/sama7g5.c\n+++ b/drivers/clk/at91/sama7g5.c\n@@ -166,7 +166,7 @@ static const struct {\n \t\t  .c = &pll_characteristics,\n \t\t  .t = PLL_TYPE_FRAC,\n \t\t   /*\n-\t\t    * This feeds syspll_divpmcck which may feed critial parts\n+\t\t    * This feeds syspll_divpmcck which may feed critical parts\n \t\t    * of the systems like timers. Therefore it should not be\n \t\t    * disabled.\n \t\t    */\n@@ -178,7 +178,7 @@ static const struct {\n \t\t  .c = &pll_characteristics,\n \t\t  .t = PLL_TYPE_DIV,\n \t\t   /*\n-\t\t    * This may feed critial parts of the systems like timers.\n+\t\t    * This may feed critical parts of the systems like timers.\n \t\t    * Therefore it should not be disabled.\n \t\t    */\n \t\t  .f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE,\n@@ -455,7 +455,7 @@ static const struct {\n  * @pp:\t\t\tPLL parents\n  * @pp_mux_table:\tPLL parents mux table\n  * @r:\t\t\tclock output range\n- * @pp_chg_id:\t\tid in parrent array of changeable PLL parent\n+ * @pp_chg_id:\t\tid in parent array of changeable PLL parent\n  * @pp_count:\t\tPLL parents count\n  * @id:\t\t\tclock id\n  */\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/114-clk-at91-sama7g5-remove-all-kernel-doc-kernel-doc-wa.patch",
    "content": "From 9997227090cf529675aeb775585ec9f6c2f0f131 Mon Sep 17 00:00:00 2001\nFrom: Randy Dunlap <rdunlap@infradead.org>\nDate: Thu, 19 Aug 2021 15:32:37 -0700\nSubject: [PATCH 114/247] clk: at91: sama7g5: remove all kernel-doc &\n kernel-doc warnings\n\nRemove all \"/**\" kernel-doc markers from sama7g5.c since they are\nall internal to this driver source file only.\nThis eliminates 14 warnings that were reported by the kernel test robot.\n\nSigned-off-by: Randy Dunlap <rdunlap@infradead.org>\nReported-by: kernel test robot <lkp@intel.com>\nCc: Claudiu Beznea <claudiu.beznea@microchip.com>\nCc: Michael Turquette <mturquette@baylibre.com>\nCc: Stephen Boyd <sboyd@kernel.org>\nCc: Eugen Hristev <eugen.hristev@microchip.com>\nCc: linux-clk@vger.kernel.org\nCc: linux-arm-kernel@lists.infradead.org\nLink: https://lore.kernel.org/r/20210819223237.20115-1-rdunlap@infradead.org\nReviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>\nSigned-off-by: Stephen Boyd <sboyd@kernel.org>\n---\n drivers/clk/at91/sama7g5.c | 14 +++++++-------\n 1 file changed, 7 insertions(+), 7 deletions(-)\n\n--- a/drivers/clk/at91/sama7g5.c\n+++ b/drivers/clk/at91/sama7g5.c\n@@ -35,7 +35,7 @@ static DEFINE_SPINLOCK(pmc_pll_lock);\n static DEFINE_SPINLOCK(pmc_mck0_lock);\n static DEFINE_SPINLOCK(pmc_mckX_lock);\n \n-/**\n+/*\n  * PLL clocks identifiers\n  * @PLL_ID_CPU:\t\tCPU PLL identifier\n  * @PLL_ID_SYS:\t\tSystem PLL identifier\n@@ -56,7 +56,7 @@ enum pll_ids {\n \tPLL_ID_MAX,\n };\n \n-/**\n+/*\n  * PLL type identifiers\n  * @PLL_TYPE_FRAC:\tfractional PLL identifier\n  * @PLL_TYPE_DIV:\tdivider PLL identifier\n@@ -118,7 +118,7 @@ static const struct clk_pll_characterist\n \t.output = pll_outputs,\n };\n \n-/**\n+/*\n  * PLL clocks description\n  * @n:\t\tclock name\n  * @p:\t\tclock parent\n@@ -285,7 +285,7 @@ static const struct {\n \t},\n };\n \n-/**\n+/*\n  * Master clock (MCK[1..4]) description\n  * @n:\t\t\tclock name\n  * @ep:\t\t\textra parents names array\n@@ -337,7 +337,7 @@ static const struct {\n \t  .c = 1, },\n };\n \n-/**\n+/*\n  * System clock description\n  * @n:\tclock name\n  * @p:\tclock parent name\n@@ -361,7 +361,7 @@ static const struct {\n /* Mux table for programmable clocks. */\n static u32 sama7g5_prog_mux_table[] = { 0, 1, 2, 5, 6, 7, 8, 9, 10, };\n \n-/**\n+/*\n  * Peripheral clock description\n  * @n:\t\tclock name\n  * @p:\t\tclock parent name\n@@ -449,7 +449,7 @@ static const struct {\n \t{ .n = \"uhphs_clk\",\t.p = \"mck1\", .id = 106, },\n };\n \n-/**\n+/*\n  * Generic clock description\n  * @n:\t\t\tclock name\n  * @pp:\t\t\tPLL parents\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/115-net-macb-add-userio-bits-as-platform-configuration.patch",
    "content": "From 89f37ac2780d113d3c17d329726c0e92a1400744 Mon Sep 17 00:00:00 2001\nFrom: Claudiu Beznea <claudiu.beznea@microchip.com>\nDate: Wed, 9 Dec 2020 15:03:32 +0200\nSubject: [PATCH 115/247] net: macb: add userio bits as platform configuration\n\nThis is necessary for SAMA7G5 as it uses different values for\nPHY interface and also introduces hdfctlen bit.\n\nSigned-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>\nReviewed-by: Andrew Lunn <andrew@lunn.ch>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/ethernet/cadence/macb.h      | 10 +++++++++\n drivers/net/ethernet/cadence/macb_main.c | 28 ++++++++++++++++++++----\n 2 files changed, 34 insertions(+), 4 deletions(-)\n\n--- a/drivers/net/ethernet/cadence/macb.h\n+++ b/drivers/net/ethernet/cadence/macb.h\n@@ -1104,6 +1104,14 @@ struct macb_pm_data {\n \tu32 usrio;\n };\n \n+struct macb_usrio_config {\n+\tu32 mii;\n+\tu32 rmii;\n+\tu32 rgmii;\n+\tu32 refclk;\n+\tu32 hdfctlen;\n+};\n+\n struct macb_config {\n \tu32\t\t\tcaps;\n \tunsigned int\t\tdma_burst_length;\n@@ -1112,6 +1120,7 @@ struct macb_config {\n \t\t\t    struct clk **rx_clk, struct clk **tsu_clk);\n \tint\t(*init)(struct platform_device *pdev);\n \tint\tjumbo_max_len;\n+\tconst struct macb_usrio_config *usrio;\n };\n \n struct tsu_incr {\n@@ -1244,6 +1253,7 @@ struct macb {\n \tu32\trx_intr_mask;\n \n \tstruct macb_pm_data pm_data;\n+\tconst struct macb_usrio_config *usrio;\n };\n \n #ifdef CONFIG_MACB_USE_HWSTAMP\n--- a/drivers/net/ethernet/cadence/macb_main.c\n+++ b/drivers/net/ethernet/cadence/macb_main.c\n@@ -3831,15 +3831,15 @@ static int macb_init(struct platform_dev\n \tif (!(bp->caps & MACB_CAPS_USRIO_DISABLED)) {\n \t\tval = 0;\n \t\tif (phy_interface_mode_is_rgmii(bp->phy_interface))\n-\t\t\tval = GEM_BIT(RGMII);\n+\t\t\tval = bp->usrio->rgmii;\n \t\telse if (bp->phy_interface == PHY_INTERFACE_MODE_RMII &&\n \t\t\t (bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII))\n-\t\t\tval = MACB_BIT(RMII);\n+\t\t\tval = bp->usrio->rmii;\n \t\telse if (!(bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII))\n-\t\t\tval = MACB_BIT(MII);\n+\t\t\tval = bp->usrio->mii;\n \n \t\tif (bp->caps & MACB_CAPS_USRIO_HAS_CLKEN)\n-\t\t\tval |= MACB_BIT(CLKEN);\n+\t\t\tval |= bp->usrio->refclk;\n \n \t\tmacb_or_gem_writel(bp, USRIO, val);\n \t}\n@@ -4357,6 +4357,13 @@ static int fu540_c000_init(struct platfo\n \treturn macb_init(pdev);\n }\n \n+static const struct macb_usrio_config macb_default_usrio = {\n+\t.mii = MACB_BIT(MII),\n+\t.rmii = MACB_BIT(RMII),\n+\t.rgmii = GEM_BIT(RGMII),\n+\t.refclk = MACB_BIT(CLKEN),\n+};\n+\n static const struct macb_config fu540_c000_config = {\n \t.caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_JUMBO |\n \t\tMACB_CAPS_GEM_HAS_PTP,\n@@ -4364,12 +4371,14 @@ static const struct macb_config fu540_c0\n \t.clk_init = fu540_c000_clk_init,\n \t.init = fu540_c000_init,\n \t.jumbo_max_len = 10240,\n+\t.usrio = &macb_default_usrio,\n };\n \n static const struct macb_config at91sam9260_config = {\n \t.caps = MACB_CAPS_USRIO_HAS_CLKEN | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,\n \t.clk_init = macb_clk_init,\n \t.init = macb_init,\n+\t.usrio = &macb_default_usrio,\n };\n \n static const struct macb_config sama5d3macb_config = {\n@@ -4377,6 +4386,7 @@ static const struct macb_config sama5d3m\n \t      | MACB_CAPS_USRIO_HAS_CLKEN | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,\n \t.clk_init = macb_clk_init,\n \t.init = macb_init,\n+\t.usrio = &macb_default_usrio,\n };\n \n static const struct macb_config pc302gem_config = {\n@@ -4384,6 +4394,7 @@ static const struct macb_config pc302gem\n \t.dma_burst_length = 16,\n \t.clk_init = macb_clk_init,\n \t.init = macb_init,\n+\t.usrio = &macb_default_usrio,\n };\n \n static const struct macb_config sama5d2_config = {\n@@ -4391,6 +4402,7 @@ static const struct macb_config sama5d2_\n \t.dma_burst_length = 16,\n \t.clk_init = macb_clk_init,\n \t.init = macb_init,\n+\t.usrio = &macb_default_usrio,\n };\n \n static const struct macb_config sama5d3_config = {\n@@ -4400,6 +4412,7 @@ static const struct macb_config sama5d3_\n \t.clk_init = macb_clk_init,\n \t.init = macb_init,\n \t.jumbo_max_len = 10240,\n+\t.usrio = &macb_default_usrio,\n };\n \n static const struct macb_config sama5d4_config = {\n@@ -4407,18 +4420,21 @@ static const struct macb_config sama5d4_\n \t.dma_burst_length = 4,\n \t.clk_init = macb_clk_init,\n \t.init = macb_init,\n+\t.usrio = &macb_default_usrio,\n };\n \n static const struct macb_config emac_config = {\n \t.caps = MACB_CAPS_NEEDS_RSTONUBR | MACB_CAPS_MACB_IS_EMAC,\n \t.clk_init = at91ether_clk_init,\n \t.init = at91ether_init,\n+\t.usrio = &macb_default_usrio,\n };\n \n static const struct macb_config np4_config = {\n \t.caps = MACB_CAPS_USRIO_DISABLED,\n \t.clk_init = macb_clk_init,\n \t.init = macb_init,\n+\t.usrio = &macb_default_usrio,\n };\n \n static const struct macb_config zynqmp_config = {\n@@ -4429,6 +4445,7 @@ static const struct macb_config zynqmp_c\n \t.clk_init = macb_clk_init,\n \t.init = macb_init,\n \t.jumbo_max_len = 10240,\n+\t.usrio = &macb_default_usrio,\n };\n \n static const struct macb_config zynq_config = {\n@@ -4437,6 +4454,7 @@ static const struct macb_config zynq_con\n \t.dma_burst_length = 16,\n \t.clk_init = macb_clk_init,\n \t.init = macb_init,\n+\t.usrio = &macb_default_usrio,\n };\n \n static const struct of_device_id macb_dt_ids[] = {\n@@ -4557,6 +4575,8 @@ static int macb_probe(struct platform_de\n \t\tbp->wol |= MACB_WOL_HAS_MAGIC_PACKET;\n \tdevice_set_wakeup_capable(&pdev->dev, bp->wol & MACB_WOL_HAS_MAGIC_PACKET);\n \n+\tbp->usrio = macb_config->usrio;\n+\n \tspin_lock_init(&bp->lock);\n \n \t/* setup capabilities */\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/116-net-macb-add-capability-to-not-set-the-clock-rate.patch",
    "content": "From 1b15259551b701f416aa024050a2e619860bd0d8 Mon Sep 17 00:00:00 2001\nFrom: Claudiu Beznea <claudiu.beznea@microchip.com>\nDate: Wed, 9 Dec 2020 15:03:33 +0200\nSubject: [PATCH 116/247] net: macb: add capability to not set the clock rate\n\nSAMA7G5's ethernet IPs TX clock could be provided by its generic clock or\nby the external clock provided by the PHY. The internal IP logic divides\nproperly this clock depending on the link speed. The patch adds a new\ncapability so that macb_set_tx_clock() to not be called for IPs having\nthis capability (the clock rate, in case of generic clock, is set at the\nboot time via device tree and the driver only enables it).\n\nSigned-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>\nReviewed-by: Andrew Lunn <andrew@lunn.ch>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/ethernet/cadence/macb.h      |  1 +\n drivers/net/ethernet/cadence/macb_main.c | 18 +++++++++---------\n 2 files changed, 10 insertions(+), 9 deletions(-)\n\n--- a/drivers/net/ethernet/cadence/macb.h\n+++ b/drivers/net/ethernet/cadence/macb.h\n@@ -658,6 +658,7 @@\n #define MACB_CAPS_GEM_HAS_PTP\t\t\t0x00000040\n #define MACB_CAPS_BD_RD_PREFETCH\t\t0x00000080\n #define MACB_CAPS_NEEDS_RSTONUBR\t\t0x00000100\n+#define MACB_CAPS_CLK_HW_CHG\t\t\t0x04000000\n #define MACB_CAPS_MACB_IS_EMAC\t\t\t0x08000000\n #define MACB_CAPS_FIFO_MODE\t\t\t0x10000000\n #define MACB_CAPS_GIGABIT_MODE_AVAILABLE\t0x20000000\n--- a/drivers/net/ethernet/cadence/macb_main.c\n+++ b/drivers/net/ethernet/cadence/macb_main.c\n@@ -457,15 +457,14 @@ static void macb_init_buffers(struct mac\n \n /**\n  * macb_set_tx_clk() - Set a clock to a new frequency\n- * @clk:\tPointer to the clock to change\n+ * @bp:\t\tpointer to struct macb\n  * @speed:\tNew frequency in Hz\n- * @dev:\tPointer to the struct net_device\n  */\n-static void macb_set_tx_clk(struct clk *clk, int speed, struct net_device *dev)\n+static void macb_set_tx_clk(struct macb *bp, int speed)\n {\n \tlong ferr, rate, rate_rounded;\n \n-\tif (!clk)\n+\tif (!bp->tx_clk || !(bp->caps & MACB_CAPS_CLK_HW_CHG))\n \t\treturn;\n \n \tswitch (speed) {\n@@ -482,7 +481,7 @@ static void macb_set_tx_clk(struct clk *\n \t\treturn;\n \t}\n \n-\trate_rounded = clk_round_rate(clk, rate);\n+\trate_rounded = clk_round_rate(bp->tx_clk, rate);\n \tif (rate_rounded < 0)\n \t\treturn;\n \n@@ -492,11 +491,12 @@ static void macb_set_tx_clk(struct clk *\n \tferr = abs(rate_rounded - rate);\n \tferr = DIV_ROUND_UP(ferr, rate / 100000);\n \tif (ferr > 5)\n-\t\tnetdev_warn(dev, \"unable to generate target frequency: %ld Hz\\n\",\n+\t\tnetdev_warn(bp->dev,\n+\t\t\t    \"unable to generate target frequency: %ld Hz\\n\",\n \t\t\t    rate);\n \n-\tif (clk_set_rate(clk, rate_rounded))\n-\t\tnetdev_err(dev, \"adjusting tx_clk failed.\\n\");\n+\tif (clk_set_rate(bp->tx_clk, rate_rounded))\n+\t\tnetdev_err(bp->dev, \"adjusting tx_clk failed.\\n\");\n }\n \n static void macb_validate(struct phylink_config *config,\n@@ -649,7 +649,7 @@ static void macb_mac_link_up(struct phyl\n \t\tif (rx_pause)\n \t\t\tctrl |= MACB_BIT(PAE);\n \n-\t\tmacb_set_tx_clk(bp->tx_clk, speed, ndev);\n+\t\tmacb_set_tx_clk(bp, speed);\n \n \t\t/* Initialize rings & buffers as clearing MACB_BIT(TE) in link down\n \t\t * cleared the pipeline and control registers.\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/117-net-macb-add-function-to-disable-all-macb-clocks.patch",
    "content": "From 935d9aae15ee245a1bc6e322cbef02566a8996cc Mon Sep 17 00:00:00 2001\nFrom: Claudiu Beznea <claudiu.beznea@microchip.com>\nDate: Wed, 9 Dec 2020 15:03:34 +0200\nSubject: [PATCH 117/247] net: macb: add function to disable all macb clocks\n\nAdd function to disable all macb clocks.\n\nSigned-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>\nSuggested-by: Andrew Lunn <andrew@lunn.ch>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/ethernet/cadence/macb_main.c | 38 +++++++++++++-----------\n 1 file changed, 21 insertions(+), 17 deletions(-)\n\n--- a/drivers/net/ethernet/cadence/macb_main.c\n+++ b/drivers/net/ethernet/cadence/macb_main.c\n@@ -3606,6 +3606,20 @@ static void macb_probe_queues(void __iom\n \t*num_queues = hweight32(*queue_mask);\n }\n \n+static void macb_clks_disable(struct clk *pclk, struct clk *hclk, struct clk *tx_clk,\n+\t\t\t      struct clk *rx_clk, struct clk *tsu_clk)\n+{\n+\tstruct clk_bulk_data clks[] = {\n+\t\t{ .clk = tsu_clk, },\n+\t\t{ .clk = rx_clk, },\n+\t\t{ .clk = pclk, },\n+\t\t{ .clk = hclk, },\n+\t\t{ .clk = tx_clk },\n+\t};\n+\n+\tclk_bulk_disable_unprepare(ARRAY_SIZE(clks), clks);\n+}\n+\n static int macb_clk_init(struct platform_device *pdev, struct clk **pclk,\n \t\t\t struct clk **hclk, struct clk **tx_clk,\n \t\t\t struct clk **rx_clk, struct clk **tsu_clk)\n@@ -4668,11 +4682,7 @@ err_out_free_netdev:\n \tfree_netdev(dev);\n \n err_disable_clocks:\n-\tclk_disable_unprepare(tx_clk);\n-\tclk_disable_unprepare(hclk);\n-\tclk_disable_unprepare(pclk);\n-\tclk_disable_unprepare(rx_clk);\n-\tclk_disable_unprepare(tsu_clk);\n+\tmacb_clks_disable(pclk, hclk, tx_clk, rx_clk, tsu_clk);\n \tpm_runtime_disable(&pdev->dev);\n \tpm_runtime_set_suspended(&pdev->dev);\n \tpm_runtime_dont_use_autosuspend(&pdev->dev);\n@@ -4697,11 +4707,8 @@ static int macb_remove(struct platform_d\n \t\tpm_runtime_disable(&pdev->dev);\n \t\tpm_runtime_dont_use_autosuspend(&pdev->dev);\n \t\tif (!pm_runtime_suspended(&pdev->dev)) {\n-\t\t\tclk_disable_unprepare(bp->tx_clk);\n-\t\t\tclk_disable_unprepare(bp->hclk);\n-\t\t\tclk_disable_unprepare(bp->pclk);\n-\t\t\tclk_disable_unprepare(bp->rx_clk);\n-\t\t\tclk_disable_unprepare(bp->tsu_clk);\n+\t\t\tmacb_clks_disable(bp->pclk, bp->hclk, bp->tx_clk,\n+\t\t\t\t\t  bp->rx_clk, bp->tsu_clk);\n \t\t\tpm_runtime_set_suspended(&pdev->dev);\n \t\t}\n \t\tphylink_destroy(bp->phylink);\n@@ -4880,13 +4887,10 @@ static int __maybe_unused macb_runtime_s\n \tstruct net_device *netdev = dev_get_drvdata(dev);\n \tstruct macb *bp = netdev_priv(netdev);\n \n-\tif (!(device_may_wakeup(dev))) {\n-\t\tclk_disable_unprepare(bp->tx_clk);\n-\t\tclk_disable_unprepare(bp->hclk);\n-\t\tclk_disable_unprepare(bp->pclk);\n-\t\tclk_disable_unprepare(bp->rx_clk);\n-\t}\n-\tclk_disable_unprepare(bp->tsu_clk);\n+\tif (!(device_may_wakeup(dev)))\n+\t\tmacb_clks_disable(bp->pclk, bp->hclk, bp->tx_clk, bp->rx_clk, bp->tsu_clk);\n+\telse\n+\t\tmacb_clks_disable(NULL, NULL, NULL, NULL, bp->tsu_clk);\n \n \treturn 0;\n }\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/118-net-macb-unprepare-clocks-in-case-of-failure.patch",
    "content": "From 9692c07ee8bf8f68b74d553d861d092e33264781 Mon Sep 17 00:00:00 2001\nFrom: Claudiu Beznea <claudiu.beznea@microchip.com>\nDate: Wed, 9 Dec 2020 15:03:35 +0200\nSubject: [PATCH 118/247] net: macb: unprepare clocks in case of failure\n\nUnprepare clocks in case of any failure in fu540_c000_clk_init().\n\nFixes: c218ad559020 (\"macb: Add support for SiFive FU540-C000\")\nSigned-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/ethernet/cadence/macb_main.c | 24 ++++++++++++++++++------\n 1 file changed, 18 insertions(+), 6 deletions(-)\n\n--- a/drivers/net/ethernet/cadence/macb_main.c\n+++ b/drivers/net/ethernet/cadence/macb_main.c\n@@ -4338,8 +4338,10 @@ static int fu540_c000_clk_init(struct pl\n \t\treturn err;\n \n \tmgmt = devm_kzalloc(&pdev->dev, sizeof(*mgmt), GFP_KERNEL);\n-\tif (!mgmt)\n-\t\treturn -ENOMEM;\n+\tif (!mgmt) {\n+\t\terr = -ENOMEM;\n+\t\tgoto err_disable_clks;\n+\t}\n \n \tinit.name = \"sifive-gemgxl-mgmt\";\n \tinit.ops = &fu540_c000_ops;\n@@ -4350,16 +4352,26 @@ static int fu540_c000_clk_init(struct pl\n \tmgmt->hw.init = &init;\n \n \t*tx_clk = devm_clk_register(&pdev->dev, &mgmt->hw);\n-\tif (IS_ERR(*tx_clk))\n-\t\treturn PTR_ERR(*tx_clk);\n+\tif (IS_ERR(*tx_clk)) {\n+\t\terr = PTR_ERR(*tx_clk);\n+\t\tgoto err_disable_clks;\n+\t}\n \n \terr = clk_prepare_enable(*tx_clk);\n-\tif (err)\n+\tif (err) {\n \t\tdev_err(&pdev->dev, \"failed to enable tx_clk (%u)\\n\", err);\n-\telse\n+\t\t*tx_clk = NULL;\n+\t\tgoto err_disable_clks;\n+\t} else {\n \t\tdev_info(&pdev->dev, \"Registered clk switch '%s'\\n\", init.name);\n+\t}\n \n \treturn 0;\n+\n+err_disable_clks:\n+\tmacb_clks_disable(*pclk, *hclk, *tx_clk, *rx_clk, *tsu_clk);\n+\n+\treturn err;\n }\n \n static int fu540_c000_init(struct platform_device *pdev)\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/119-net-macb-add-support-for-sama7g5-gem-interface.patch",
    "content": "From 0085cd8576ceeaddeedf973b939b41ba96e3f77c Mon Sep 17 00:00:00 2001\nFrom: Claudiu Beznea <claudiu.beznea@microchip.com>\nDate: Wed, 9 Dec 2020 15:03:38 +0200\nSubject: [PATCH 119/247] net: macb: add support for sama7g5 gem interface\n\nAdd support for SAMA7G5 gigabit ethernet interface.\n\nSigned-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>\nReviewed-by: Andrew Lunn <andrew@lunn.ch>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/ethernet/cadence/macb_main.c | 17 +++++++++++++++++\n 1 file changed, 17 insertions(+)\n\n--- a/drivers/net/ethernet/cadence/macb_main.c\n+++ b/drivers/net/ethernet/cadence/macb_main.c\n@@ -4390,6 +4390,14 @@ static const struct macb_usrio_config ma\n \t.refclk = MACB_BIT(CLKEN),\n };\n \n+static const struct macb_usrio_config sama7g5_usrio = {\n+\t.mii = 0,\n+\t.rmii = 1,\n+\t.rgmii = 2,\n+\t.refclk = BIT(2),\n+\t.hdfctlen = BIT(6),\n+};\n+\n static const struct macb_config fu540_c000_config = {\n \t.caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_JUMBO |\n \t\tMACB_CAPS_GEM_HAS_PTP,\n@@ -4483,6 +4491,14 @@ static const struct macb_config zynq_con\n \t.usrio = &macb_default_usrio,\n };\n \n+static const struct macb_config sama7g5_gem_config = {\n+\t.caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_CLK_HW_CHG,\n+\t.dma_burst_length = 16,\n+\t.clk_init = macb_clk_init,\n+\t.init = macb_init,\n+\t.usrio = &sama7g5_usrio,\n+};\n+\n static const struct of_device_id macb_dt_ids[] = {\n \t{ .compatible = \"cdns,at32ap7000-macb\" },\n \t{ .compatible = \"cdns,at91sam9260-macb\", .data = &at91sam9260_config },\n@@ -4500,6 +4516,7 @@ static const struct of_device_id macb_dt\n \t{ .compatible = \"cdns,zynqmp-gem\", .data = &zynqmp_config},\n \t{ .compatible = \"cdns,zynq-gem\", .data = &zynq_config },\n \t{ .compatible = \"sifive,fu540-c000-gem\", .data = &fu540_c000_config },\n+\t{ .compatible = \"microchip,sama7g5-gem\", .data = &sama7g5_gem_config },\n \t{ /* sentinel */ }\n };\n MODULE_DEVICE_TABLE(of, macb_dt_ids);\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/120-net-macb-add-support-for-sama7g5-emac-interface.patch",
    "content": "From a42f90357cfcfcf5cdade4594ad79a1eae633a9f Mon Sep 17 00:00:00 2001\nFrom: Claudiu Beznea <claudiu.beznea@microchip.com>\nDate: Wed, 9 Dec 2020 15:03:39 +0200\nSubject: [PATCH 120/247] net: macb: add support for sama7g5 emac interface\n\nAdd support for SAMA7G5 10/100Mbps interface.\n\nSigned-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>\nReviewed-by: Andrew Lunn <andrew@lunn.ch>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/ethernet/cadence/macb_main.c | 9 +++++++++\n 1 file changed, 9 insertions(+)\n\n--- a/drivers/net/ethernet/cadence/macb_main.c\n+++ b/drivers/net/ethernet/cadence/macb_main.c\n@@ -4499,6 +4499,14 @@ static const struct macb_config sama7g5_\n \t.usrio = &sama7g5_usrio,\n };\n \n+static const struct macb_config sama7g5_emac_config = {\n+\t.caps = MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII | MACB_CAPS_USRIO_HAS_CLKEN,\n+\t.dma_burst_length = 16,\n+\t.clk_init = macb_clk_init,\n+\t.init = macb_init,\n+\t.usrio = &sama7g5_usrio,\n+};\n+\n static const struct of_device_id macb_dt_ids[] = {\n \t{ .compatible = \"cdns,at32ap7000-macb\" },\n \t{ .compatible = \"cdns,at91sam9260-macb\", .data = &at91sam9260_config },\n@@ -4517,6 +4525,7 @@ static const struct of_device_id macb_dt\n \t{ .compatible = \"cdns,zynq-gem\", .data = &zynq_config },\n \t{ .compatible = \"sifive,fu540-c000-gem\", .data = &fu540_c000_config },\n \t{ .compatible = \"microchip,sama7g5-gem\", .data = &sama7g5_gem_config },\n+\t{ .compatible = \"microchip,sama7g5-emac\", .data = &sama7g5_emac_config },\n \t{ /* sentinel */ }\n };\n MODULE_DEVICE_TABLE(of, macb_dt_ids);\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/121-ASoC-pcm5102a-Make-codec-selectable.patch",
    "content": "From 5ac0e1f5577b266543756521b1a749003b0f3686 Mon Sep 17 00:00:00 2001\nFrom: Codrin Ciubotariu <codrin.ciubotariu@microchip.com>\nDate: Mon, 12 Oct 2020 17:19:11 +0300\nSubject: [PATCH 121/247] ASoC: pcm5102a: Make codec selectable\n\nThe TI PCM5102A codec driver can be used with the generic sound card\ndrivers, so it should be selectable. For example, with the addition\nof #sound-dai-cells = <0> property in DT, it can be used with simple/graph\ncard drivers.\n\nSigned-off-by: Codrin Ciubotariu <codrin.ciubotariu@microchip.com>\nLink: https://lore.kernel.org/r/20201012141911.3150996-1-codrin.ciubotariu@microchip.com\nSigned-off-by: Mark Brown <broonie@kernel.org>\n---\n sound/soc/codecs/Kconfig | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/sound/soc/codecs/Kconfig\n+++ b/sound/soc/codecs/Kconfig\n@@ -1008,7 +1008,7 @@ config SND_SOC_PCM3168A_SPI\n \tselect REGMAP_SPI\n \n config SND_SOC_PCM5102A\n-\ttristate\n+\ttristate \"Texas Instruments PCM5102A CODEC\"\n \n config SND_SOC_PCM512x\n \ttristate\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/122-ASoC-atmel-i2s-do-not-warn-if-muxclk-is-missing.patch",
    "content": "From f4389949bf422fe04775c17b833100fa0e95ea68 Mon Sep 17 00:00:00 2001\nFrom: Codrin Ciubotariu <codrin.ciubotariu@microchip.com>\nDate: Tue, 3 Nov 2020 12:05:54 +0200\nSubject: [PATCH 122/247] ASoC: atmel-i2s: do not warn if muxclk is missing\n\nBesides the fact that muxclk is optional, muxclk can be set using\nassigned-clocks, removing the need to set it in driver. The warning is\nthus unneeded, so we can transform it in a debug print, eventually to just\nreflect that muxclk was not set by the driver.\n\nSigned-off-by: Codrin Ciubotariu <codrin.ciubotariu@microchip.com>\nLink: https://lore.kernel.org/r/20201103100554.1307190-1-codrin.ciubotariu@microchip.com\nSigned-off-by: Mark Brown <broonie@kernel.org>\n---\n sound/soc/atmel/atmel-i2s.c | 4 ++--\n 1 file changed, 2 insertions(+), 2 deletions(-)\n\n--- a/sound/soc/atmel/atmel-i2s.c\n+++ b/sound/soc/atmel/atmel-i2s.c\n@@ -581,8 +581,8 @@ static int atmel_i2s_sama5d2_mck_init(st\n \t\terr = PTR_ERR(muxclk);\n \t\tif (err == -EPROBE_DEFER)\n \t\t\treturn -EPROBE_DEFER;\n-\t\tdev_warn(dev->dev,\n-\t\t\t \"failed to get the I2S clock control: %d\\n\", err);\n+\t\tdev_dbg(dev->dev,\n+\t\t\t\"failed to get the I2S clock control: %d\\n\", err);\n \t\treturn 0;\n \t}\n \n"
  },
  {
    "path": "target/linux/at91/patches-5.10/123-regulator-mcp16502-add-linear_min_sel.patch",
    "content": "From f5a73f3bb600b96b6149f2115360e1d0d51fbac4 Mon Sep 17 00:00:00 2001\nFrom: Claudiu Beznea <claudiu.beznea@microchip.com>\nDate: Fri, 13 Nov 2020 17:21:07 +0200\nSubject: [PATCH 123/247] regulator: mcp16502: add linear_min_sel\n\nSelectors b/w zero and VDD_LOW_SEL are not valid. Use linear_min_sel.\n\nFixes: 919261c03e7ca (\"regulator: mcp16502: add regulator driver for MCP16502\")\nSigned-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>\nLink: https://lore.kernel.org/r/1605280870-32432-4-git-send-email-claudiu.beznea@microchip.com\nSigned-off-by: Mark Brown <broonie@kernel.org>\n---\n drivers/regulator/mcp16502.c | 1 +\n 1 file changed, 1 insertion(+)\n\n--- a/drivers/regulator/mcp16502.c\n+++ b/drivers/regulator/mcp16502.c\n@@ -93,6 +93,7 @@ static unsigned int mcp16502_of_map_mode\n \t\t.owner\t\t\t= THIS_MODULE,\t\t\t\\\n \t\t.n_voltages\t\t= MCP16502_VSEL + 1,\t\t\\\n \t\t.linear_ranges\t\t= _ranges,\t\t\t\\\n+\t\t.linear_min_sel\t\t= VDD_LOW_SEL,\t\t\t\\\n \t\t.n_linear_ranges\t= ARRAY_SIZE(_ranges),\t\t\\\n \t\t.of_match\t\t= of_match_ptr(_name),\t\t\\\n \t\t.of_map_mode\t\t= mcp16502_of_map_mode,\t\t\\\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/124-regulator-mcp16502-adapt-for-get-set-on-other-regist.patch",
    "content": "From 5295f4c122258a11fb6012b7e043248e681db5a2 Mon Sep 17 00:00:00 2001\nFrom: Claudiu Beznea <claudiu.beznea@microchip.com>\nDate: Fri, 13 Nov 2020 17:21:08 +0200\nSubject: [PATCH 124/247] regulator: mcp16502: adapt for get/set on other\n registers\n\nMCP16502 have multiple registers for each regulator (as described\nin enum mcp16502_reg). Adapt the code to be able to get/set all these\nregisters. This is necessary for the following commits.\n\nSigned-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>\nLink: https://lore.kernel.org/r/1605280870-32432-5-git-send-email-claudiu.beznea@microchip.com\nSigned-off-by: Mark Brown <broonie@kernel.org>\n---\n drivers/regulator/mcp16502.c | 43 ++++++++++++++++++++++--------------\n 1 file changed, 27 insertions(+), 16 deletions(-)\n\n--- a/drivers/regulator/mcp16502.c\n+++ b/drivers/regulator/mcp16502.c\n@@ -54,13 +54,9 @@\n  * This function is useful for iterating over all regulators and accessing their\n  * registers in a generic way or accessing a regulator device by its id.\n  */\n-#define MCP16502_BASE(i) (((i) + 1) << 4)\n+#define MCP16502_REG_BASE(i, r) ((((i) + 1) << 4) + MCP16502_REG_##r)\n #define MCP16502_STAT_BASE(i) ((i) + 5)\n \n-#define MCP16502_OFFSET_MODE_A 0\n-#define MCP16502_OFFSET_MODE_LPM 1\n-#define MCP16502_OFFSET_MODE_HIB 2\n-\n #define MCP16502_OPMODE_ACTIVE REGULATOR_MODE_NORMAL\n #define MCP16502_OPMODE_LPM REGULATOR_MODE_IDLE\n #define MCP16502_OPMODE_HIB REGULATOR_MODE_STANDBY\n@@ -75,6 +71,23 @@\n #define MCP16502_MIN_REG 0x0\n #define MCP16502_MAX_REG 0x65\n \n+/**\n+ * enum mcp16502_reg - MCP16502 regulators's registers\n+ * @MCP16502_REG_A: active state register\n+ * @MCP16502_REG_LPM: low power mode state register\n+ * @MCP16502_REG_HIB: hibernate state register\n+ * @MCP16502_REG_SEQ: startup sequence register\n+ * @MCP16502_REG_CFG: configuration register\n+ */\n+enum mcp16502_reg {\n+\tMCP16502_REG_A,\n+\tMCP16502_REG_LPM,\n+\tMCP16502_REG_HIB,\n+\tMCP16502_REG_HPM,\n+\tMCP16502_REG_SEQ,\n+\tMCP16502_REG_CFG,\n+};\n+\n static unsigned int mcp16502_of_map_mode(unsigned int mode)\n {\n \tif (mode == REGULATOR_MODE_NORMAL || mode == REGULATOR_MODE_IDLE)\n@@ -144,22 +157,20 @@ static void mcp16502_gpio_set_mode(struc\n }\n \n /*\n- * mcp16502_get_reg() - get the PMIC's configuration register for opmode\n+ * mcp16502_get_reg() - get the PMIC's state configuration register for opmode\n  *\n  * @rdev: the regulator whose register we are searching\n  * @opmode: the PMIC's operating mode ACTIVE, Low-power, Hibernate\n  */\n-static int mcp16502_get_reg(struct regulator_dev *rdev, int opmode)\n+static int mcp16502_get_state_reg(struct regulator_dev *rdev, int opmode)\n {\n-\tint reg = MCP16502_BASE(rdev_get_id(rdev));\n-\n \tswitch (opmode) {\n \tcase MCP16502_OPMODE_ACTIVE:\n-\t\treturn reg + MCP16502_OFFSET_MODE_A;\n+\t\treturn MCP16502_REG_BASE(rdev_get_id(rdev), A);\n \tcase MCP16502_OPMODE_LPM:\n-\t\treturn reg + MCP16502_OFFSET_MODE_LPM;\n+\t\treturn MCP16502_REG_BASE(rdev_get_id(rdev), LPM);\n \tcase MCP16502_OPMODE_HIB:\n-\t\treturn reg + MCP16502_OFFSET_MODE_HIB;\n+\t\treturn MCP16502_REG_BASE(rdev_get_id(rdev), HIB);\n \tdefault:\n \t\treturn -EINVAL;\n \t}\n@@ -179,7 +190,7 @@ static unsigned int mcp16502_get_mode(st\n \tunsigned int val;\n \tint ret, reg;\n \n-\treg = mcp16502_get_reg(rdev, MCP16502_OPMODE_ACTIVE);\n+\treg = mcp16502_get_state_reg(rdev, MCP16502_OPMODE_ACTIVE);\n \tif (reg < 0)\n \t\treturn reg;\n \n@@ -210,7 +221,7 @@ static int _mcp16502_set_mode(struct reg\n \tint val;\n \tint reg;\n \n-\treg = mcp16502_get_reg(rdev, op_mode);\n+\treg = mcp16502_get_state_reg(rdev, op_mode);\n \tif (reg < 0)\n \t\treturn reg;\n \n@@ -269,10 +280,10 @@ static int mcp16502_suspend_get_target_r\n {\n \tswitch (pm_suspend_target_state) {\n \tcase PM_SUSPEND_STANDBY:\n-\t\treturn mcp16502_get_reg(rdev, MCP16502_OPMODE_LPM);\n+\t\treturn mcp16502_get_state_reg(rdev, MCP16502_OPMODE_LPM);\n \tcase PM_SUSPEND_ON:\n \tcase PM_SUSPEND_MEM:\n-\t\treturn mcp16502_get_reg(rdev, MCP16502_OPMODE_HIB);\n+\t\treturn mcp16502_get_state_reg(rdev, MCP16502_OPMODE_HIB);\n \tdefault:\n \t\tdev_err(&rdev->dev, \"invalid suspend target: %d\\n\",\n \t\t\tpm_suspend_target_state);\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/125-regulator-mcp16502-add-support-for-ramp-delay.patch",
    "content": "From 7f13433e11a3c88f1fd6417c4c5e5a6c98370b9a Mon Sep 17 00:00:00 2001\nFrom: Claudiu Beznea <claudiu.beznea@microchip.com>\nDate: Fri, 13 Nov 2020 17:21:09 +0200\nSubject: [PATCH 125/247] regulator: mcp16502: add support for ramp delay\n\nMCP16502 have configurable ramp delay support (via DVSR bits in\nregulators' CFG register).\n\nSigned-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>\nLink: https://lore.kernel.org/r/1605280870-32432-6-git-send-email-claudiu.beznea@microchip.com\nSigned-off-by: Mark Brown <broonie@kernel.org>\n---\n drivers/regulator/mcp16502.c | 89 +++++++++++++++++++++++++++++++++++-\n 1 file changed, 87 insertions(+), 2 deletions(-)\n\n--- a/drivers/regulator/mcp16502.c\n+++ b/drivers/regulator/mcp16502.c\n@@ -22,8 +22,9 @@\n #define VDD_LOW_SEL 0x0D\n #define VDD_HIGH_SEL 0x3F\n \n-#define MCP16502_FLT BIT(7)\n-#define MCP16502_ENS BIT(0)\n+#define MCP16502_FLT\t\tBIT(7)\n+#define MCP16502_DVSR\t\tGENMASK(3, 2)\n+#define MCP16502_ENS\t\tBIT(0)\n \n /*\n  * The PMIC has four sets of registers corresponding to four power modes:\n@@ -88,6 +89,12 @@ enum mcp16502_reg {\n \tMCP16502_REG_CFG,\n };\n \n+/* Ramp delay (uV/us) for buck1, ldo1, ldo2. */\n+static const int mcp16502_ramp_b1l12[] = { 6250, 3125, 2083, 1563 };\n+\n+/* Ramp delay (uV/us) for buck2, buck3, buck4. */\n+static const int mcp16502_ramp_b234[] = { 3125, 1563, 1042, 781 };\n+\n static unsigned int mcp16502_of_map_mode(unsigned int mode)\n {\n \tif (mode == REGULATOR_MODE_NORMAL || mode == REGULATOR_MODE_IDLE)\n@@ -271,6 +278,80 @@ static int mcp16502_get_status(struct re\n \treturn REGULATOR_STATUS_UNDEFINED;\n }\n \n+static int mcp16502_set_voltage_time_sel(struct regulator_dev *rdev,\n+\t\t\t\t\t unsigned int old_sel,\n+\t\t\t\t\t unsigned int new_sel)\n+{\n+\tstatic const u8 us_ramp[] = { 8, 16, 24, 32 };\n+\tint id = rdev_get_id(rdev);\n+\tunsigned int uV_delta, val;\n+\tint ret;\n+\n+\tret = regmap_read(rdev->regmap, MCP16502_REG_BASE(id, CFG), &val);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tval = (val & MCP16502_DVSR) >> 2;\n+\tuV_delta = abs(new_sel * rdev->desc->linear_ranges->step -\n+\t\t       old_sel * rdev->desc->linear_ranges->step);\n+\tswitch (id) {\n+\tcase BUCK1:\n+\tcase LDO1:\n+\tcase LDO2:\n+\t\tret = DIV_ROUND_CLOSEST(uV_delta * us_ramp[val],\n+\t\t\t\t\tmcp16502_ramp_b1l12[val]);\n+\t\tbreak;\n+\n+\tcase BUCK2:\n+\tcase BUCK3:\n+\tcase BUCK4:\n+\t\tret = DIV_ROUND_CLOSEST(uV_delta * us_ramp[val],\n+\t\t\t\t\tmcp16502_ramp_b234[val]);\n+\t\tbreak;\n+\n+\tdefault:\n+\t\treturn -EINVAL;\n+\t}\n+\n+\treturn ret;\n+}\n+\n+static int mcp16502_set_ramp_delay(struct regulator_dev *rdev, int ramp_delay)\n+{\n+\tconst int *ramp;\n+\tint id = rdev_get_id(rdev);\n+\tunsigned int i, size;\n+\n+\tswitch (id) {\n+\tcase BUCK1:\n+\tcase LDO1:\n+\tcase LDO2:\n+\t\tramp = mcp16502_ramp_b1l12;\n+\t\tsize = ARRAY_SIZE(mcp16502_ramp_b1l12);\n+\t\tbreak;\n+\n+\tcase BUCK2:\n+\tcase BUCK3:\n+\tcase BUCK4:\n+\t\tramp = mcp16502_ramp_b234;\n+\t\tsize = ARRAY_SIZE(mcp16502_ramp_b234);\n+\t\tbreak;\n+\n+\tdefault:\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tfor (i = 0; i < size; i++) {\n+\t\tif (ramp[i] == ramp_delay)\n+\t\t\tbreak;\n+\t}\n+\tif (i == size)\n+\t\treturn -EINVAL;\n+\n+\treturn regmap_update_bits(rdev->regmap, MCP16502_REG_BASE(id, CFG),\n+\t\t\t\t  MCP16502_DVSR, (i << 2));\n+}\n+\n #ifdef CONFIG_SUSPEND\n /*\n  * mcp16502_suspend_get_target_reg() - get the reg of the target suspend PMIC\n@@ -365,6 +446,8 @@ static const struct regulator_ops mcp165\n \t.disable\t\t\t= regulator_disable_regmap,\n \t.is_enabled\t\t\t= regulator_is_enabled_regmap,\n \t.get_status\t\t\t= mcp16502_get_status,\n+\t.set_voltage_time_sel\t\t= mcp16502_set_voltage_time_sel,\n+\t.set_ramp_delay\t\t\t= mcp16502_set_ramp_delay,\n \n \t.set_mode\t\t\t= mcp16502_set_mode,\n \t.get_mode\t\t\t= mcp16502_get_mode,\n@@ -389,6 +472,8 @@ static const struct regulator_ops mcp165\n \t.disable\t\t\t= regulator_disable_regmap,\n \t.is_enabled\t\t\t= regulator_is_enabled_regmap,\n \t.get_status\t\t\t= mcp16502_get_status,\n+\t.set_voltage_time_sel\t\t= mcp16502_set_voltage_time_sel,\n+\t.set_ramp_delay\t\t\t= mcp16502_set_ramp_delay,\n \n #ifdef CONFIG_SUSPEND\n \t.set_suspend_voltage\t\t= mcp16502_set_suspend_voltage,\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/126-regulator-mcp16502-remove-void-documentation-of-stru.patch",
    "content": "From 8dcbcb052f682478dcbfa7fc9abdd909e1deab87 Mon Sep 17 00:00:00 2001\nFrom: Claudiu Beznea <claudiu.beznea@microchip.com>\nDate: Fri, 13 Nov 2020 17:21:10 +0200\nSubject: [PATCH 126/247] regulator: mcp16502: remove void documentation of\n struct mcp16502\n\nstruct mcp16502 has no members called rdev or rmap. Remove the\ndocumentation.\n\nSigned-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>\nLink: https://lore.kernel.org/r/1605280870-32432-7-git-send-email-claudiu.beznea@microchip.com\nSigned-off-by: Mark Brown <broonie@kernel.org>\n---\n drivers/regulator/mcp16502.c | 2 --\n 1 file changed, 2 deletions(-)\n\n--- a/drivers/regulator/mcp16502.c\n+++ b/drivers/regulator/mcp16502.c\n@@ -135,8 +135,6 @@ enum {\n \n /*\n  * struct mcp16502 - PMIC representation\n- * @rdev: the regulators belonging to this chip\n- * @rmap: regmap to be used for I2C communication\n  * @lpm: LPM GPIO descriptor\n  */\n struct mcp16502 {\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/127-regulator-core-validate-selector-against-linear_min_.patch",
    "content": "From 3aee4f22ed0a22d3d6d22fc49812c03d876c7637 Mon Sep 17 00:00:00 2001\nFrom: Claudiu Beznea <claudiu.beznea@microchip.com>\nDate: Fri, 13 Nov 2020 17:21:05 +0200\nSubject: [PATCH 127/247] regulator: core: validate selector against\n linear_min_sel\n\nThere are regulators who's min selector is not zero. Selectors loops\n(looping b/w zero and regulator::desc::n_voltages) might throw errors\nbecause invalid selectors are used (lower than\nregulator::desc::linear_min_sel). For this situations validate selectors\nagainst regulator::desc::linear_min_sel.\n\nSigned-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>\nLink: https://lore.kernel.org/r/1605280870-32432-2-git-send-email-claudiu.beznea@microchip.com\nSigned-off-by: Mark Brown <broonie@kernel.org>\n---\n drivers/regulator/core.c    | 9 +++++++--\n drivers/regulator/helpers.c | 3 ++-\n 2 files changed, 9 insertions(+), 3 deletions(-)\n\n--- a/drivers/regulator/core.c\n+++ b/drivers/regulator/core.c\n@@ -2984,7 +2984,8 @@ static int _regulator_list_voltage(struc\n \t\treturn rdev->desc->fixed_uV;\n \n \tif (ops->list_voltage) {\n-\t\tif (selector >= rdev->desc->n_voltages)\n+\t\tif (selector >= rdev->desc->n_voltages ||\n+\t\t    selector < rdev->desc->linear_min_sel)\n \t\t\treturn -EINVAL;\n \t\tif (lock)\n \t\t\tregulator_lock(rdev);\n@@ -3135,7 +3136,8 @@ int regulator_list_hardware_vsel(struct\n \tstruct regulator_dev *rdev = regulator->rdev;\n \tconst struct regulator_ops *ops = rdev->desc->ops;\n \n-\tif (selector >= rdev->desc->n_voltages)\n+\tif (selector >= rdev->desc->n_voltages ||\n+\t    selector < rdev->desc->linear_min_sel)\n \t\treturn -EINVAL;\n \tif (ops->set_voltage_sel != regulator_set_voltage_sel_regmap)\n \t\treturn -EOPNOTSUPP;\n@@ -4058,6 +4060,9 @@ int regulator_set_voltage_time(struct re\n \n \tfor (i = 0; i < rdev->desc->n_voltages; i++) {\n \t\t/* We only look for exact voltage matches here */\n+\t\tif (i < rdev->desc->linear_min_sel)\n+\t\t\tcontinue;\n+\n \t\tvoltage = regulator_list_voltage(regulator, i);\n \t\tif (voltage < 0)\n \t\t\treturn -EINVAL;\n--- a/drivers/regulator/helpers.c\n+++ b/drivers/regulator/helpers.c\n@@ -647,7 +647,8 @@ int regulator_list_voltage_table(struct\n \t\treturn -EINVAL;\n \t}\n \n-\tif (selector >= rdev->desc->n_voltages)\n+\tif (selector >= rdev->desc->n_voltages ||\n+\t    selector < rdev->desc->linear_min_sel)\n \t\treturn -EINVAL;\n \n \treturn rdev->desc->volt_table[selector];\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/128-regulator-core-do-not-continue-if-selector-match.patch",
    "content": "From 42b56e8bd343f34d5f2a601d8a8a05d8c861c08c Mon Sep 17 00:00:00 2001\nFrom: Claudiu Beznea <claudiu.beznea@microchip.com>\nDate: Fri, 13 Nov 2020 19:56:04 +0200\nSubject: [PATCH 128/247] regulator: core: do not continue if selector match\n\nDo not continue if selector has already been located.\n\nSigned-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>\nLink: https://lore.kernel.org/r/1605290164-11556-1-git-send-email-claudiu.beznea@microchip.com\nSigned-off-by: Mark Brown <broonie@kernel.org>\n---\n drivers/regulator/core.c | 3 +++\n 1 file changed, 3 insertions(+)\n\n--- a/drivers/regulator/core.c\n+++ b/drivers/regulator/core.c\n@@ -4063,6 +4063,9 @@ int regulator_set_voltage_time(struct re\n \t\tif (i < rdev->desc->linear_min_sel)\n \t\t\tcontinue;\n \n+\t\tif (old_sel >= 0 && new_sel >= 0)\n+\t\t\tbreak;\n+\n \t\tvoltage = regulator_list_voltage(regulator, i);\n \t\tif (voltage < 0)\n \t\t\treturn -EINVAL;\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/129-regulator-core-return-zero-for-selectors-lower-than-.patch",
    "content": "From 0e933ffc049a0e181b5a6c3af1933976d6959ba9 Mon Sep 17 00:00:00 2001\nFrom: Claudiu Beznea <claudiu.beznea@microchip.com>\nDate: Wed, 25 Nov 2020 19:25:47 +0200\nSubject: [PATCH 129/247] regulator: core: return zero for selectors lower than\n linear_min_sel\n\nSelectors lower than linear_min_sel should not be considered invalid.\nThus return zero in case _regulator_list_voltage(),\nregulator_list_hardware_vsel() or regulator_list_voltage_table()\nreceives such selectors as argument.\n\nFixes: bdcd1177578c (\"regulator: core: validate selector against linear_min_sel\")\nReported-by: Jon Hunter <jonathanh@nvidia.com>\nSigned-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>\nLink: https://lore.kernel.org/r/1606325147-606-1-git-send-email-claudiu.beznea@microchip.com\nSigned-off-by: Mark Brown <broonie@kernel.org>\n---\n drivers/regulator/core.c    | 10 ++++++----\n drivers/regulator/helpers.c |  5 +++--\n 2 files changed, 9 insertions(+), 6 deletions(-)\n\n--- a/drivers/regulator/core.c\n+++ b/drivers/regulator/core.c\n@@ -2984,9 +2984,10 @@ static int _regulator_list_voltage(struc\n \t\treturn rdev->desc->fixed_uV;\n \n \tif (ops->list_voltage) {\n-\t\tif (selector >= rdev->desc->n_voltages ||\n-\t\t    selector < rdev->desc->linear_min_sel)\n+\t\tif (selector >= rdev->desc->n_voltages)\n \t\t\treturn -EINVAL;\n+\t\tif (selector < rdev->desc->linear_min_sel)\n+\t\t\treturn 0;\n \t\tif (lock)\n \t\t\tregulator_lock(rdev);\n \t\tret = ops->list_voltage(rdev, selector);\n@@ -3136,9 +3137,10 @@ int regulator_list_hardware_vsel(struct\n \tstruct regulator_dev *rdev = regulator->rdev;\n \tconst struct regulator_ops *ops = rdev->desc->ops;\n \n-\tif (selector >= rdev->desc->n_voltages ||\n-\t    selector < rdev->desc->linear_min_sel)\n+\tif (selector >= rdev->desc->n_voltages)\n \t\treturn -EINVAL;\n+\tif (selector < rdev->desc->linear_min_sel)\n+\t\treturn 0;\n \tif (ops->set_voltage_sel != regulator_set_voltage_sel_regmap)\n \t\treturn -EOPNOTSUPP;\n \n--- a/drivers/regulator/helpers.c\n+++ b/drivers/regulator/helpers.c\n@@ -647,9 +647,10 @@ int regulator_list_voltage_table(struct\n \t\treturn -EINVAL;\n \t}\n \n-\tif (selector >= rdev->desc->n_voltages ||\n-\t    selector < rdev->desc->linear_min_sel)\n+\tif (selector >= rdev->desc->n_voltages)\n \t\treturn -EINVAL;\n+\tif (selector < rdev->desc->linear_min_sel)\n+\t\treturn 0;\n \n \treturn rdev->desc->volt_table[selector];\n }\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/130-regulator-mcp16502-lpm-pin-can-be-optional-on-some-p.patch",
    "content": "From 763fe72f607d4e929d2c710c88e5c6978dd6ad97 Mon Sep 17 00:00:00 2001\nFrom: Claudiu Beznea <claudiu.beznea@microchip.com>\nDate: Thu, 7 Jan 2021 16:15:26 +0200\nSubject: [PATCH 130/247] regulator: mcp16502: lpm pin can be optional on some\n platforms\n\nOn some platform (e.g. SAMA7G5) LPM pin should be optional as it can\nbe controlled explicitly (via shutdown controller registers) in the\nplatform specific power saving code to decrease the power consumption\nwhile suspended as this SoC pin may be connected to other devices that\ncould take power saving actions based on its value.\n\nSigned-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>\nLink: https://lore.kernel.org/r/1610028927-9842-3-git-send-email-claudiu.beznea@microchip.com\nSigned-off-by: Mark Brown <broonie@kernel.org>\n---\n drivers/regulator/mcp16502.c | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/drivers/regulator/mcp16502.c\n+++ b/drivers/regulator/mcp16502.c\n@@ -550,7 +550,7 @@ static int mcp16502_probe(struct i2c_cli\n \tconfig.regmap = rmap;\n \tconfig.driver_data = mcp;\n \n-\tmcp->lpm = devm_gpiod_get(dev, \"lpm\", GPIOD_OUT_LOW);\n+\tmcp->lpm = devm_gpiod_get_optional(dev, \"lpm\", GPIOD_OUT_LOW);\n \tif (IS_ERR(mcp->lpm)) {\n \t\tdev_err(dev, \"failed to get lpm pin: %ld\\n\", PTR_ERR(mcp->lpm));\n \t\treturn PTR_ERR(mcp->lpm);\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/131-pinctrl-at91-pio4-add-support-for-fewer-lines-on-las.patch",
    "content": "From 7cb1dad7a7dfe4cfe55ebe86930dd6aef0de66b4 Mon Sep 17 00:00:00 2001\nFrom: Eugen Hristev <eugen.hristev@microchip.com>\nDate: Fri, 13 Nov 2020 15:24:29 +0200\nSubject: [PATCH 131/247] pinctrl: at91-pio4: add support for fewer lines on\n last PIO bank\n\nSome products, like sama7g5, do not have a full last bank of PIO lines.\nIn this case for example, sama7g5 only has 8 lines for the PE bank.\nPA0-31, PB0-31, PC0-31, PD0-31, PE0-7, in total 136 lines.\nTo cope with this situation, added a data attribute that is product dependent,\nto specify the number of lines of the last bank.\nIn case this number is different from the macro ATMEL_PIO_NPINS_PER_BANK,\nadjust the total number of lines accordingly.\nThis will avoid advertising 160 lines instead of the actual 136, as this\nproduct supports, and to avoid reading/writing to invalid register addresses.\n\nSigned-off-by: Eugen Hristev <eugen.hristev@microchip.com>\nAcked-by: Ludovic Desroches <ludovic.desroches@microchip.com>\nLink: https://lore.kernel.org/r/20201113132429.420940-1-eugen.hristev@microchip.com\nSigned-off-by: Linus Walleij <linus.walleij@linaro.org>\n---\n drivers/pinctrl/pinctrl-at91-pio4.c | 18 ++++++++++++++++--\n 1 file changed, 16 insertions(+), 2 deletions(-)\n\n--- a/drivers/pinctrl/pinctrl-at91-pio4.c\n+++ b/drivers/pinctrl/pinctrl-at91-pio4.c\n@@ -71,8 +71,15 @@\n /* Custom pinconf parameters */\n #define ATMEL_PIN_CONFIG_DRIVE_STRENGTH\t(PIN_CONFIG_END + 1)\n \n+/**\n+ * struct atmel_pioctrl_data - Atmel PIO controller (pinmux + gpio) data struct\n+ * @nbanks: number of PIO banks\n+ * @last_bank_count: number of lines in the last bank (can be less than\n+ *\tthe rest of the banks).\n+ */\n struct atmel_pioctrl_data {\n \tunsigned nbanks;\n+\tunsigned last_bank_count;\n };\n \n struct atmel_group {\n@@ -980,11 +987,13 @@ static const struct dev_pm_ops atmel_pct\n  * We can have up to 16 banks.\n  */\n static const struct atmel_pioctrl_data atmel_sama5d2_pioctrl_data = {\n-\t.nbanks\t\t= 4,\n+\t.nbanks\t\t\t= 4,\n+\t.last_bank_count\t= ATMEL_PIO_NPINS_PER_BANK,\n };\n \n static const struct atmel_pioctrl_data microchip_sama7g5_pioctrl_data = {\n-\t.nbanks\t\t= 5,\n+\t.nbanks\t\t\t= 5,\n+\t.last_bank_count\t= 8, /* sama7g5 has only PE0 to PE7 */\n };\n \n static const struct of_device_id atmel_pctrl_of_match[] = {\n@@ -1025,6 +1034,11 @@ static int atmel_pinctrl_probe(struct pl\n \tatmel_pioctrl_data = match->data;\n \tatmel_pioctrl->nbanks = atmel_pioctrl_data->nbanks;\n \tatmel_pioctrl->npins = atmel_pioctrl->nbanks * ATMEL_PIO_NPINS_PER_BANK;\n+\t/* if last bank has limited number of pins, adjust accordingly */\n+\tif (atmel_pioctrl_data->last_bank_count != ATMEL_PIO_NPINS_PER_BANK) {\n+\t\tatmel_pioctrl->npins -= ATMEL_PIO_NPINS_PER_BANK;\n+\t\tatmel_pioctrl->npins += atmel_pioctrl_data->last_bank_count;\n+\t}\n \n \tatmel_pioctrl->reg_base = devm_platform_ioremap_resource(pdev, 0);\n \tif (IS_ERR(atmel_pioctrl->reg_base))\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/132-dmaengine-at_xdmac-adapt-perid-for-mem2mem-operation.patch",
    "content": "From 1dccaa4c1e99cd8bd27684a2c87ec806d426c088 Mon Sep 17 00:00:00 2001\nFrom: Eugen Hristev <eugen.hristev@microchip.com>\nDate: Fri, 16 Oct 2020 12:37:25 +0300\nSubject: [PATCH 132/247] dmaengine: at_xdmac: adapt perid for mem2mem\n operations\n\nThe PERID in the CC register for mem2mem operations must match an unused\nPERID.\nThe PERID field is 7 bits, but the selected value is 0x3f.\nOn later products we can have more reserved PERIDs for actual peripherals,\nthus this needs to be increased to maximum size.\nChanging the value to 0x7f, which is the maximum for 7 bits field.\n\nSigned-off-by: Eugen Hristev <eugen.hristev@microchip.com>\nReviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com>\nLink: https://lore.kernel.org/r/20201016093725.289880-1-eugen.hristev@microchip.com\nSigned-off-by: Vinod Koul <vkoul@kernel.org>\n---\n drivers/dma/at_xdmac.c | 6 +++---\n 1 file changed, 3 insertions(+), 3 deletions(-)\n\n--- a/drivers/dma/at_xdmac.c\n+++ b/drivers/dma/at_xdmac.c\n@@ -865,7 +865,7 @@ at_xdmac_interleaved_queue_desc(struct d\n \t * match the one of another channel. If not, it could lead to spurious\n \t * flag status.\n \t */\n-\tu32\t\t\tchan_cc = AT_XDMAC_CC_PERID(0x3f)\n+\tu32\t\t\tchan_cc = AT_XDMAC_CC_PERID(0x7f)\n \t\t\t\t\t| AT_XDMAC_CC_DIF(0)\n \t\t\t\t\t| AT_XDMAC_CC_SIF(0)\n \t\t\t\t\t| AT_XDMAC_CC_MBSIZE_SIXTEEN\n@@ -1047,7 +1047,7 @@ at_xdmac_prep_dma_memcpy(struct dma_chan\n \t * match the one of another channel. If not, it could lead to spurious\n \t * flag status.\n \t */\n-\tu32\t\t\tchan_cc = AT_XDMAC_CC_PERID(0x3f)\n+\tu32\t\t\tchan_cc = AT_XDMAC_CC_PERID(0x7f)\n \t\t\t\t\t| AT_XDMAC_CC_DAM_INCREMENTED_AM\n \t\t\t\t\t| AT_XDMAC_CC_SAM_INCREMENTED_AM\n \t\t\t\t\t| AT_XDMAC_CC_DIF(0)\n@@ -1153,7 +1153,7 @@ static struct at_xdmac_desc *at_xdmac_me\n \t * match the one of another channel. If not, it could lead to spurious\n \t * flag status.\n \t */\n-\tu32\t\t\tchan_cc = AT_XDMAC_CC_PERID(0x3f)\n+\tu32\t\t\tchan_cc = AT_XDMAC_CC_PERID(0x7f)\n \t\t\t\t\t| AT_XDMAC_CC_DAM_UBS_AM\n \t\t\t\t\t| AT_XDMAC_CC_SAM_INCREMENTED_AM\n \t\t\t\t\t| AT_XDMAC_CC_DIF(0)\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/133-dmaengine-at_xdmac-add-support-for-sama7g5-based-at_.patch",
    "content": "From 613af756b93fe005d9db11ea26fd0318f239d5a2 Mon Sep 17 00:00:00 2001\nFrom: Eugen Hristev <eugen.hristev@microchip.com>\nDate: Fri, 16 Oct 2020 12:38:50 +0300\nSubject: [PATCH 133/247] dmaengine: at_xdmac: add support for sama7g5 based\n at_xdmac\n\nSAMA7G5 SoC uses a slightly different variant of the AT_XDMAC.\nAdded support by a new compatible and a layout struct that copes\nto the specific version considering the compatible string.\nOnly the differences in register map are present in the layout struct.\nI reworked the register access for this part that has the differences.\nAlso the Source/Destination Interface bits are no longer valid for this\nvariant of the XDMAC. Thus, the layout also has a bool for specifying\nwhether these bits are required or not.\n\nSigned-off-by: Eugen Hristev <eugen.hristev@microchip.com>\nLink: https://lore.kernel.org/r/20201016093850.290053-1-eugen.hristev@microchip.com\nSigned-off-by: Vinod Koul <vkoul@kernel.org>\n---\n drivers/dma/at_xdmac.c | 110 +++++++++++++++++++++++++++++++----------\n 1 file changed, 84 insertions(+), 26 deletions(-)\n\n--- a/drivers/dma/at_xdmac.c\n+++ b/drivers/dma/at_xdmac.c\n@@ -38,13 +38,6 @@\n #define AT_XDMAC_GE\t\t0x1C\t/* Global Channel Enable Register */\n #define AT_XDMAC_GD\t\t0x20\t/* Global Channel Disable Register */\n #define AT_XDMAC_GS\t\t0x24\t/* Global Channel Status Register */\n-#define AT_XDMAC_GRS\t\t0x28\t/* Global Channel Read Suspend Register */\n-#define AT_XDMAC_GWS\t\t0x2C\t/* Global Write Suspend Register */\n-#define AT_XDMAC_GRWS\t\t0x30\t/* Global Channel Read Write Suspend Register */\n-#define AT_XDMAC_GRWR\t\t0x34\t/* Global Channel Read Write Resume Register */\n-#define AT_XDMAC_GSWR\t\t0x38\t/* Global Channel Software Request Register */\n-#define AT_XDMAC_GSWS\t\t0x3C\t/* Global channel Software Request Status Register */\n-#define AT_XDMAC_GSWF\t\t0x40\t/* Global Channel Software Flush Request Register */\n #define AT_XDMAC_VERSION\t0xFFC\t/* XDMAC Version Register */\n \n /* Channel relative registers offsets */\n@@ -151,8 +144,6 @@\n #define AT_XDMAC_CSUS\t\t0x30\t/* Channel Source Microblock Stride */\n #define AT_XDMAC_CDUS\t\t0x34\t/* Channel Destination Microblock Stride */\n \n-#define AT_XDMAC_CHAN_REG_BASE\t0x50\t/* Channel registers base address */\n-\n /* Microblock control members */\n #define AT_XDMAC_MBR_UBC_UBLEN_MAX\t0xFFFFFFUL\t/* Maximum Microblock Length */\n #define AT_XDMAC_MBR_UBC_NDE\t\t(0x1 << 24)\t/* Next Descriptor Enable */\n@@ -180,6 +171,27 @@ enum atc_status {\n \tAT_XDMAC_CHAN_IS_PAUSED,\n };\n \n+struct at_xdmac_layout {\n+\t/* Global Channel Read Suspend Register */\n+\tu8\t\t\t\tgrs;\n+\t/* Global Write Suspend Register */\n+\tu8\t\t\t\tgws;\n+\t/* Global Channel Read Write Suspend Register */\n+\tu8\t\t\t\tgrws;\n+\t/* Global Channel Read Write Resume Register */\n+\tu8\t\t\t\tgrwr;\n+\t/* Global Channel Software Request Register */\n+\tu8\t\t\t\tgswr;\n+\t/* Global channel Software Request Status Register */\n+\tu8\t\t\t\tgsws;\n+\t/* Global Channel Software Flush Request Register */\n+\tu8\t\t\t\tgswf;\n+\t/* Channel reg base */\n+\tu8\t\t\t\tchan_cc_reg_base;\n+\t/* Source/Destination Interface must be specified or not */\n+\tbool\t\t\t\tsdif;\n+};\n+\n /* ----- Channels ----- */\n struct at_xdmac_chan {\n \tstruct dma_chan\t\t\tchan;\n@@ -213,6 +225,7 @@ struct at_xdmac {\n \tstruct clk\t\t*clk;\n \tu32\t\t\tsave_gim;\n \tstruct dma_pool\t\t*at_xdmac_desc_pool;\n+\tconst struct at_xdmac_layout\t*layout;\n \tstruct at_xdmac_chan\tchan[];\n };\n \n@@ -245,9 +258,33 @@ struct at_xdmac_desc {\n \tstruct list_head\t\txfer_node;\n } __aligned(sizeof(u64));\n \n+static const struct at_xdmac_layout at_xdmac_sama5d4_layout = {\n+\t.grs = 0x28,\n+\t.gws = 0x2C,\n+\t.grws = 0x30,\n+\t.grwr = 0x34,\n+\t.gswr = 0x38,\n+\t.gsws = 0x3C,\n+\t.gswf = 0x40,\n+\t.chan_cc_reg_base = 0x50,\n+\t.sdif = true,\n+};\n+\n+static const struct at_xdmac_layout at_xdmac_sama7g5_layout = {\n+\t.grs = 0x30,\n+\t.gws = 0x38,\n+\t.grws = 0x40,\n+\t.grwr = 0x44,\n+\t.gswr = 0x48,\n+\t.gsws = 0x4C,\n+\t.gswf = 0x50,\n+\t.chan_cc_reg_base = 0x60,\n+\t.sdif = false,\n+};\n+\n static inline void __iomem *at_xdmac_chan_reg_base(struct at_xdmac *atxdmac, unsigned int chan_nb)\n {\n-\treturn atxdmac->regs + (AT_XDMAC_CHAN_REG_BASE + chan_nb * 0x40);\n+\treturn atxdmac->regs + (atxdmac->layout->chan_cc_reg_base + chan_nb * 0x40);\n }\n \n #define at_xdmac_read(atxdmac, reg) readl_relaxed((atxdmac)->regs + (reg))\n@@ -343,8 +380,10 @@ static void at_xdmac_start_xfer(struct a\n \tfirst->active_xfer = true;\n \n \t/* Tell xdmac where to get the first descriptor. */\n-\treg = AT_XDMAC_CNDA_NDA(first->tx_dma_desc.phys)\n-\t      | AT_XDMAC_CNDA_NDAIF(atchan->memif);\n+\treg = AT_XDMAC_CNDA_NDA(first->tx_dma_desc.phys);\n+\tif (atxdmac->layout->sdif)\n+\t\treg |= AT_XDMAC_CNDA_NDAIF(atchan->memif);\n+\n \tat_xdmac_chan_write(atchan, AT_XDMAC_CNDA, reg);\n \n \t/*\n@@ -539,6 +578,7 @@ static int at_xdmac_compute_chan_conf(st\n \t\t\t\t      enum dma_transfer_direction direction)\n {\n \tstruct at_xdmac_chan\t*atchan = to_at_xdmac_chan(chan);\n+\tstruct at_xdmac\t\t*atxdmac = to_at_xdmac(atchan->chan.device);\n \tint\t\t\tcsize, dwidth;\n \n \tif (direction == DMA_DEV_TO_MEM) {\n@@ -546,12 +586,14 @@ static int at_xdmac_compute_chan_conf(st\n \t\t\tAT91_XDMAC_DT_PERID(atchan->perid)\n \t\t\t| AT_XDMAC_CC_DAM_INCREMENTED_AM\n \t\t\t| AT_XDMAC_CC_SAM_FIXED_AM\n-\t\t\t| AT_XDMAC_CC_DIF(atchan->memif)\n-\t\t\t| AT_XDMAC_CC_SIF(atchan->perif)\n \t\t\t| AT_XDMAC_CC_SWREQ_HWR_CONNECTED\n \t\t\t| AT_XDMAC_CC_DSYNC_PER2MEM\n \t\t\t| AT_XDMAC_CC_MBSIZE_SIXTEEN\n \t\t\t| AT_XDMAC_CC_TYPE_PER_TRAN;\n+\t\tif (atxdmac->layout->sdif)\n+\t\t\tatchan->cfg |= AT_XDMAC_CC_DIF(atchan->memif) |\n+\t\t\t\t       AT_XDMAC_CC_SIF(atchan->perif);\n+\n \t\tcsize = ffs(atchan->sconfig.src_maxburst) - 1;\n \t\tif (csize < 0) {\n \t\t\tdev_err(chan2dev(chan), \"invalid src maxburst value\\n\");\n@@ -569,12 +611,14 @@ static int at_xdmac_compute_chan_conf(st\n \t\t\tAT91_XDMAC_DT_PERID(atchan->perid)\n \t\t\t| AT_XDMAC_CC_DAM_FIXED_AM\n \t\t\t| AT_XDMAC_CC_SAM_INCREMENTED_AM\n-\t\t\t| AT_XDMAC_CC_DIF(atchan->perif)\n-\t\t\t| AT_XDMAC_CC_SIF(atchan->memif)\n \t\t\t| AT_XDMAC_CC_SWREQ_HWR_CONNECTED\n \t\t\t| AT_XDMAC_CC_DSYNC_MEM2PER\n \t\t\t| AT_XDMAC_CC_MBSIZE_SIXTEEN\n \t\t\t| AT_XDMAC_CC_TYPE_PER_TRAN;\n+\t\tif (atxdmac->layout->sdif)\n+\t\t\tatchan->cfg |= AT_XDMAC_CC_DIF(atchan->perif) |\n+\t\t\t\t       AT_XDMAC_CC_SIF(atchan->memif);\n+\n \t\tcsize = ffs(atchan->sconfig.dst_maxburst) - 1;\n \t\tif (csize < 0) {\n \t\t\tdev_err(chan2dev(chan), \"invalid src maxburst value\\n\");\n@@ -864,10 +908,12 @@ at_xdmac_interleaved_queue_desc(struct d\n \t * ERRATA: Even if useless for memory transfers, the PERID has to not\n \t * match the one of another channel. If not, it could lead to spurious\n \t * flag status.\n+\t * For SAMA7G5x case, the SIF and DIF fields are no longer used.\n+\t * Thus, no need to have the SIF/DIF interfaces here.\n+\t * For SAMA5D4x and SAMA5D2x the SIF and DIF are already configured as\n+\t * zero.\n \t */\n \tu32\t\t\tchan_cc = AT_XDMAC_CC_PERID(0x7f)\n-\t\t\t\t\t| AT_XDMAC_CC_DIF(0)\n-\t\t\t\t\t| AT_XDMAC_CC_SIF(0)\n \t\t\t\t\t| AT_XDMAC_CC_MBSIZE_SIXTEEN\n \t\t\t\t\t| AT_XDMAC_CC_TYPE_MEM_TRAN;\n \n@@ -1046,12 +1092,14 @@ at_xdmac_prep_dma_memcpy(struct dma_chan\n \t * ERRATA: Even if useless for memory transfers, the PERID has to not\n \t * match the one of another channel. If not, it could lead to spurious\n \t * flag status.\n+\t * For SAMA7G5x case, the SIF and DIF fields are no longer used.\n+\t * Thus, no need to have the SIF/DIF interfaces here.\n+\t * For SAMA5D4x and SAMA5D2x the SIF and DIF are already configured as\n+\t * zero.\n \t */\n \tu32\t\t\tchan_cc = AT_XDMAC_CC_PERID(0x7f)\n \t\t\t\t\t| AT_XDMAC_CC_DAM_INCREMENTED_AM\n \t\t\t\t\t| AT_XDMAC_CC_SAM_INCREMENTED_AM\n-\t\t\t\t\t| AT_XDMAC_CC_DIF(0)\n-\t\t\t\t\t| AT_XDMAC_CC_SIF(0)\n \t\t\t\t\t| AT_XDMAC_CC_MBSIZE_SIXTEEN\n \t\t\t\t\t| AT_XDMAC_CC_TYPE_MEM_TRAN;\n \tunsigned long\t\tirqflags;\n@@ -1152,12 +1200,14 @@ static struct at_xdmac_desc *at_xdmac_me\n \t * ERRATA: Even if useless for memory transfers, the PERID has to not\n \t * match the one of another channel. If not, it could lead to spurious\n \t * flag status.\n+\t * For SAMA7G5x case, the SIF and DIF fields are no longer used.\n+\t * Thus, no need to have the SIF/DIF interfaces here.\n+\t * For SAMA5D4x and SAMA5D2x the SIF and DIF are already configured as\n+\t * zero.\n \t */\n \tu32\t\t\tchan_cc = AT_XDMAC_CC_PERID(0x7f)\n \t\t\t\t\t| AT_XDMAC_CC_DAM_UBS_AM\n \t\t\t\t\t| AT_XDMAC_CC_SAM_INCREMENTED_AM\n-\t\t\t\t\t| AT_XDMAC_CC_DIF(0)\n-\t\t\t\t\t| AT_XDMAC_CC_SIF(0)\n \t\t\t\t\t| AT_XDMAC_CC_MBSIZE_SIXTEEN\n \t\t\t\t\t| AT_XDMAC_CC_MEMSET_HW_MODE\n \t\t\t\t\t| AT_XDMAC_CC_TYPE_MEM_TRAN;\n@@ -1436,7 +1486,7 @@ at_xdmac_tx_status(struct dma_chan *chan\n \tmask = AT_XDMAC_CC_TYPE | AT_XDMAC_CC_DSYNC;\n \tvalue = AT_XDMAC_CC_TYPE_PER_TRAN | AT_XDMAC_CC_DSYNC_PER2MEM;\n \tif ((desc->lld.mbr_cfg & mask) == value) {\n-\t\tat_xdmac_write(atxdmac, AT_XDMAC_GSWF, atchan->mask);\n+\t\tat_xdmac_write(atxdmac, atxdmac->layout->gswf, atchan->mask);\n \t\twhile (!(at_xdmac_chan_read(atchan, AT_XDMAC_CIS) & AT_XDMAC_CIS_FIS))\n \t\t\tcpu_relax();\n \t}\n@@ -1494,7 +1544,7 @@ at_xdmac_tx_status(struct dma_chan *chan\n \t * FIFO flush ensures that data are really written.\n \t */\n \tif ((desc->lld.mbr_cfg & mask) == value) {\n-\t\tat_xdmac_write(atxdmac, AT_XDMAC_GSWF, atchan->mask);\n+\t\tat_xdmac_write(atxdmac, atxdmac->layout->gswf, atchan->mask);\n \t\twhile (!(at_xdmac_chan_read(atchan, AT_XDMAC_CIS) & AT_XDMAC_CIS_FIS))\n \t\t\tcpu_relax();\n \t}\n@@ -1762,7 +1812,7 @@ static int at_xdmac_device_pause(struct\n \t\treturn 0;\n \n \tspin_lock_irqsave(&atchan->lock, flags);\n-\tat_xdmac_write(atxdmac, AT_XDMAC_GRWS, atchan->mask);\n+\tat_xdmac_write(atxdmac, atxdmac->layout->grws, atchan->mask);\n \twhile (at_xdmac_chan_read(atchan, AT_XDMAC_CC)\n \t       & (AT_XDMAC_CC_WRIP | AT_XDMAC_CC_RDIP))\n \t\tcpu_relax();\n@@ -1785,7 +1835,7 @@ static int at_xdmac_device_resume(struct\n \t\treturn 0;\n \t}\n \n-\tat_xdmac_write(atxdmac, AT_XDMAC_GRWR, atchan->mask);\n+\tat_xdmac_write(atxdmac, atxdmac->layout->grwr, atchan->mask);\n \tclear_bit(AT_XDMAC_CHAN_IS_PAUSED, &atchan->status);\n \tspin_unlock_irqrestore(&atchan->lock, flags);\n \n@@ -1987,6 +2037,10 @@ static int at_xdmac_probe(struct platfor\n \tatxdmac->regs = base;\n \tatxdmac->irq = irq;\n \n+\tatxdmac->layout = of_device_get_match_data(&pdev->dev);\n+\tif (!atxdmac->layout)\n+\t\treturn -ENODEV;\n+\n \tatxdmac->clk = devm_clk_get(&pdev->dev, \"dma_clk\");\n \tif (IS_ERR(atxdmac->clk)) {\n \t\tdev_err(&pdev->dev, \"can't get dma_clk\\n\");\n@@ -2129,6 +2183,10 @@ static const struct dev_pm_ops atmel_xdm\n static const struct of_device_id atmel_xdmac_dt_ids[] = {\n \t{\n \t\t.compatible = \"atmel,sama5d4-dma\",\n+\t\t.data = &at_xdmac_sama5d4_layout,\n+\t}, {\n+\t\t.compatible = \"microchip,sama7g5-dma\",\n+\t\t.data = &at_xdmac_sama7g5_layout,\n \t}, {\n \t\t/* sentinel */\n \t}\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/134-dmaengine-at_xdmac-add-AXI-priority-support-and-reco.patch",
    "content": "From 4833d6ea13a6d2c44a91247991a82c3eb6c1613e Mon Sep 17 00:00:00 2001\nFrom: Eugen Hristev <eugen.hristev@microchip.com>\nDate: Fri, 16 Oct 2020 12:39:18 +0300\nSubject: [PATCH 134/247] dmaengine: at_xdmac: add AXI priority support and\n recommended settings\n\nThe sama7g5 version of the XDMAC supports priority configuration and\noutstanding capabilities.\nAdd defines for the specific registers for this configuration, together\nwith recommended settings.\nHowever the settings are very different if the XDMAC is a mem2mem or a\nper2mem controller.\nThus, we need to differentiate according to device tree property.\n\nSigned-off-by: Eugen Hristev <eugen.hristev@microchip.com>\nLink: https://lore.kernel.org/r/20201016093918.290137-1-eugen.hristev@microchip.com\nSigned-off-by: Vinod Koul <vkoul@kernel.org>\n---\n drivers/dma/at_xdmac.c | 47 ++++++++++++++++++++++++++++++++++++++++++\n 1 file changed, 47 insertions(+)\n\n--- a/drivers/dma/at_xdmac.c\n+++ b/drivers/dma/at_xdmac.c\n@@ -30,7 +30,24 @@\n #define\t\tAT_XDMAC_FIFO_SZ(i)\t(((i) >> 5) & 0x7FF)\t\t/* Number of Bytes */\n #define\t\tAT_XDMAC_NB_REQ(i)\t((((i) >> 16) & 0x3F) + 1)\t/* Number of Peripheral Requests Minus One */\n #define AT_XDMAC_GCFG\t\t0x04\t/* Global Configuration Register */\n+#define\t\tAT_XDMAC_WRHP(i)\t\t(((i) & 0xF) << 4)\n+#define\t\tAT_XDMAC_WRMP(i)\t\t(((i) & 0xF) << 8)\n+#define\t\tAT_XDMAC_WRLP(i)\t\t(((i) & 0xF) << 12)\n+#define\t\tAT_XDMAC_RDHP(i)\t\t(((i) & 0xF) << 16)\n+#define\t\tAT_XDMAC_RDMP(i)\t\t(((i) & 0xF) << 20)\n+#define\t\tAT_XDMAC_RDLP(i)\t\t(((i) & 0xF) << 24)\n+#define\t\tAT_XDMAC_RDSG(i)\t\t(((i) & 0xF) << 28)\n+#define AT_XDMAC_GCFG_M2M\t(AT_XDMAC_RDLP(0xF) | AT_XDMAC_WRLP(0xF))\n+#define AT_XDMAC_GCFG_P2M\t(AT_XDMAC_RDSG(0x1) | AT_XDMAC_RDHP(0x3) | \\\n+\t\t\t\tAT_XDMAC_WRHP(0x5))\n #define AT_XDMAC_GWAC\t\t0x08\t/* Global Weighted Arbiter Configuration Register */\n+#define\t\tAT_XDMAC_PW0(i)\t\t(((i) & 0xF) << 0)\n+#define\t\tAT_XDMAC_PW1(i)\t\t(((i) & 0xF) << 4)\n+#define\t\tAT_XDMAC_PW2(i)\t\t(((i) & 0xF) << 8)\n+#define\t\tAT_XDMAC_PW3(i)\t\t(((i) & 0xF) << 12)\n+#define AT_XDMAC_GWAC_M2M\t0\n+#define AT_XDMAC_GWAC_P2M\t(AT_XDMAC_PW0(0xF) | AT_XDMAC_PW2(0xF))\n+\n #define AT_XDMAC_GIE\t\t0x0C\t/* Global Interrupt Enable Register */\n #define AT_XDMAC_GID\t\t0x10\t/* Global Interrupt Disable Register */\n #define AT_XDMAC_GIM\t\t0x14\t/* Global Interrupt Mask Register */\n@@ -190,6 +207,8 @@ struct at_xdmac_layout {\n \tu8\t\t\t\tchan_cc_reg_base;\n \t/* Source/Destination Interface must be specified or not */\n \tbool\t\t\t\tsdif;\n+\t/* AXI queue priority configuration supported */\n+\tbool\t\t\t\taxi_config;\n };\n \n /* ----- Channels ----- */\n@@ -268,6 +287,7 @@ static const struct at_xdmac_layout at_x\n \t.gswf = 0x40,\n \t.chan_cc_reg_base = 0x50,\n \t.sdif = true,\n+\t.axi_config = false,\n };\n \n static const struct at_xdmac_layout at_xdmac_sama7g5_layout = {\n@@ -280,6 +300,7 @@ static const struct at_xdmac_layout at_x\n \t.gswf = 0x50,\n \t.chan_cc_reg_base = 0x60,\n \t.sdif = false,\n+\t.axi_config = true,\n };\n \n static inline void __iomem *at_xdmac_chan_reg_base(struct at_xdmac *atxdmac, unsigned int chan_nb)\n@@ -1998,6 +2019,30 @@ static int atmel_xdmac_resume(struct dev\n }\n #endif /* CONFIG_PM_SLEEP */\n \n+static void at_xdmac_axi_config(struct platform_device *pdev)\n+{\n+\tstruct at_xdmac\t*atxdmac = (struct at_xdmac *)platform_get_drvdata(pdev);\n+\tbool dev_m2m = false;\n+\tu32 dma_requests;\n+\n+\tif (!atxdmac->layout->axi_config)\n+\t\treturn; /* Not supported */\n+\n+\tif (!of_property_read_u32(pdev->dev.of_node, \"dma-requests\",\n+\t\t\t\t  &dma_requests)) {\n+\t\tdev_info(&pdev->dev, \"controller in mem2mem mode.\\n\");\n+\t\tdev_m2m = true;\n+\t}\n+\n+\tif (dev_m2m) {\n+\t\tat_xdmac_write(atxdmac, AT_XDMAC_GCFG, AT_XDMAC_GCFG_M2M);\n+\t\tat_xdmac_write(atxdmac, AT_XDMAC_GWAC, AT_XDMAC_GWAC_M2M);\n+\t} else {\n+\t\tat_xdmac_write(atxdmac, AT_XDMAC_GCFG, AT_XDMAC_GCFG_P2M);\n+\t\tat_xdmac_write(atxdmac, AT_XDMAC_GWAC, AT_XDMAC_GWAC_P2M);\n+\t}\n+}\n+\n static int at_xdmac_probe(struct platform_device *pdev)\n {\n \tstruct at_xdmac\t*atxdmac;\n@@ -2142,6 +2187,8 @@ static int at_xdmac_probe(struct platfor\n \tdev_info(&pdev->dev, \"%d channels, mapped at 0x%p\\n\",\n \t\t nr_channels, atxdmac->regs);\n \n+\tat_xdmac_axi_config(pdev);\n+\n \treturn 0;\n \n err_dma_unregister:\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/135-net-macb-Correct-usage-of-MACB_CAPS_CLK_HW_CHG-flag.patch",
    "content": "From 982347f757b85ef526afaf243867ddd515475e1b Mon Sep 17 00:00:00 2001\nFrom: Charles Keepax <ckeepax@opensource.cirrus.com>\nDate: Mon, 4 Jan 2021 10:38:02 +0000\nSubject: [PATCH 135/247] net: macb: Correct usage of MACB_CAPS_CLK_HW_CHG flag\n\nA new flag MACB_CAPS_CLK_HW_CHG was added and all callers of\nmacb_set_tx_clk were gated on the presence of this flag.\n\n-   if (!clk)\n+ if (!bp->tx_clk || !(bp->caps & MACB_CAPS_CLK_HW_CHG))\n\nHowever the flag was not added to anything other than the new\nsama7g5_gem, turning that function call into a no op for all other\nsystems. This breaks the networking on Zynq.\n\nThe commit message adding this states: a new capability so that\nmacb_set_tx_clock() to not be called for IPs having this\ncapability\n\nThis strongly implies that present of the flag was intended to skip\nthe function not absence of the flag. Update the if statement to\nthis effect, which repairs the existing users.\n\nFixes: daafa1d33cc9 (\"net: macb: add capability to not set the clock rate\")\nSuggested-by: Andrew Lunn <andrew@lunn.ch>\nSigned-off-by: Charles Keepax <ckeepax@opensource.cirrus.com>\nReviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>\nReviewed-by: Andrew Lunn <andrew@lunn.ch>\nLink: https://lore.kernel.org/r/20210104103802.13091-1-ckeepax@opensource.cirrus.com\nSigned-off-by: Jakub Kicinski <kuba@kernel.org>\n---\n drivers/net/ethernet/cadence/macb_main.c | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/drivers/net/ethernet/cadence/macb_main.c\n+++ b/drivers/net/ethernet/cadence/macb_main.c\n@@ -464,7 +464,7 @@ static void macb_set_tx_clk(struct macb\n {\n \tlong ferr, rate, rate_rounded;\n \n-\tif (!bp->tx_clk || !(bp->caps & MACB_CAPS_CLK_HW_CHG))\n+\tif (!bp->tx_clk || (bp->caps & MACB_CAPS_CLK_HW_CHG))\n \t\treturn;\n \n \tswitch (speed) {\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/136-ARM-at91-sam9x60-SiP-types-added-to-soc-description.patch",
    "content": "From a2eda4ef1e3d617cdd669e256e45e969fab62398 Mon Sep 17 00:00:00 2001\nFrom: Kai Stuhlemmer <kai.stuhlemmer@ebee.de>\nDate: Thu, 8 Oct 2020 14:50:28 +0200\nSubject: [PATCH 136/247] ARM: at91: sam9x60 SiP types added to soc description\n\nAdding SAM9X60 SIP variants to the soc description list.\n\nSigned-off-by: Kai Stuhlemmer <kai.stuhlemmer@ebee.de>\nSigned-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>\nSigned-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>\nLink: https://lore.kernel.org/r/20201008125028.21071-1-nicolas.ferre@microchip.com\n---\n drivers/soc/atmel/soc.c | 6 ++++++\n drivers/soc/atmel/soc.h | 3 +++\n 2 files changed, 9 insertions(+)\n\n--- a/drivers/soc/atmel/soc.c\n+++ b/drivers/soc/atmel/soc.c\n@@ -69,6 +69,12 @@ static const struct at91_soc __initconst\n #endif\n #ifdef CONFIG_SOC_SAM9X60\n \tAT91_SOC(SAM9X60_CIDR_MATCH, SAM9X60_EXID_MATCH, \"sam9x60\", \"sam9x60\"),\n+\tAT91_SOC(SAM9X60_CIDR_MATCH, SAM9X60_D5M_EXID_MATCH,\n+\t\t \"sam9x60 64MiB DDR2 SiP\", \"sam9x60\"),\n+\tAT91_SOC(SAM9X60_CIDR_MATCH, SAM9X60_D1G_EXID_MATCH,\n+\t\t \"sam9x60 128MiB DDR2 SiP\", \"sam9x60\"),\n+\tAT91_SOC(SAM9X60_CIDR_MATCH, SAM9X60_D6K_EXID_MATCH,\n+\t\t \"sam9x60 8MiB SDRAM SiP\", \"sam9x60\"),\n #endif\n #ifdef CONFIG_SOC_SAMA5\n \tAT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D21CU_EXID_MATCH,\n--- a/drivers/soc/atmel/soc.h\n+++ b/drivers/soc/atmel/soc.h\n@@ -60,6 +60,9 @@ at91_soc_init(const struct at91_soc *soc\n #define AT91SAM9CN11_EXID_MATCH\t\t0x00000009\n \n #define SAM9X60_EXID_MATCH\t\t0x00000000\n+#define SAM9X60_D5M_EXID_MATCH\t\t0x00000001\n+#define SAM9X60_D1G_EXID_MATCH\t\t0x00000010\n+#define SAM9X60_D6K_EXID_MATCH\t\t0x00000011\n \n #define AT91SAM9XE128_CIDR_MATCH\t0x329973a0\n #define AT91SAM9XE256_CIDR_MATCH\t0x329a93a0\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/137-drivers-soc-atmel-use-GENMASK.patch",
    "content": "From 8d858d9c57a0210ca1ce9e5ba76fab8bdb4d7b39 Mon Sep 17 00:00:00 2001\nFrom: Claudiu Beznea <claudiu.beznea@microchip.com>\nDate: Fri, 22 Jan 2021 14:21:32 +0200\nSubject: [PATCH 137/247] drivers: soc: atmel: use GENMASK\n\nUse GENMASK() to define CIDR match mask.\n\nSigned-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>\nSigned-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>\nLink: https://lore.kernel.org/r/1611318097-8970-3-git-send-email-claudiu.beznea@microchip.com\n---\n drivers/soc/atmel/soc.c | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/drivers/soc/atmel/soc.c\n+++ b/drivers/soc/atmel/soc.c\n@@ -27,7 +27,7 @@\n #define AT91_CHIPID_EXID\t\t0x04\n #define AT91_CIDR_VERSION(x)\t\t((x) & 0x1f)\n #define AT91_CIDR_EXT\t\t\tBIT(31)\n-#define AT91_CIDR_MATCH_MASK\t\t0x7fffffe0\n+#define AT91_CIDR_MATCH_MASK\t\tGENMASK(30, 5)\n \n static const struct at91_soc __initconst socs[] = {\n #ifdef CONFIG_SOC_AT91RM9200\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/138-drivers-soc-atmel-fix-__initconst-should-be-placed-a.patch",
    "content": "From ed871f95827e9b6d4ee9f9eafec4e18b87fb1a56 Mon Sep 17 00:00:00 2001\nFrom: Claudiu Beznea <claudiu.beznea@microchip.com>\nDate: Fri, 22 Jan 2021 14:21:33 +0200\nSubject: [PATCH 138/247] drivers: soc: atmel: fix \"__initconst should be\n placed after socs[]\" warning\n\nFix checkpatch.pl warning: \"__initconst should be placed after socs[]\".\n\nSigned-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>\nSigned-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>\nLink: https://lore.kernel.org/r/1611318097-8970-4-git-send-email-claudiu.beznea@microchip.com\n---\n drivers/soc/atmel/soc.c | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/drivers/soc/atmel/soc.c\n+++ b/drivers/soc/atmel/soc.c\n@@ -29,7 +29,7 @@\n #define AT91_CIDR_EXT\t\t\tBIT(31)\n #define AT91_CIDR_MATCH_MASK\t\tGENMASK(30, 5)\n \n-static const struct at91_soc __initconst socs[] = {\n+static const struct at91_soc socs[] __initconst = {\n #ifdef CONFIG_SOC_AT91RM9200\n \tAT91_SOC(AT91RM9200_CIDR_MATCH, 0, \"at91rm9200 BGA\", \"at91rm9200\"),\n #endif\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/139-drivers-soc-atmel-add-per-soc-id-and-version-match-m.patch",
    "content": "From 8f6f7ef363268f417f1729bb0b234326dd1e8e2a Mon Sep 17 00:00:00 2001\nFrom: Claudiu Beznea <claudiu.beznea@microchip.com>\nDate: Fri, 22 Jan 2021 14:21:35 +0200\nSubject: [PATCH 139/247] drivers: soc: atmel: add per soc id and version match\n masks\n\nSAMA7G5 has different masks for chip ID and chip version on CIDR\nregister compared to previous AT91 SoCs. For this the commit adapts\nthe code for SAMA7G5 addition by introducing 2 new members in\nstruct at91_soc and fill them properly and also preparing the\nparsing of proper DT binding.\n\nSigned-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>\nSigned-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>\nLink: https://lore.kernel.org/r/1611318097-8970-6-git-send-email-claudiu.beznea@microchip.com\n---\n drivers/soc/atmel/soc.c | 199 +++++++++++++++++++++++++++-------------\n drivers/soc/atmel/soc.h |   7 +-\n 2 files changed, 140 insertions(+), 66 deletions(-)\n\n--- a/drivers/soc/atmel/soc.c\n+++ b/drivers/soc/atmel/soc.c\n@@ -25,135 +25,200 @@\n #define AT91_DBGU_EXID\t\t\t0x44\n #define AT91_CHIPID_CIDR\t\t0x00\n #define AT91_CHIPID_EXID\t\t0x04\n-#define AT91_CIDR_VERSION(x)\t\t((x) & 0x1f)\n+#define AT91_CIDR_VERSION(x, m)\t\t((x) & (m))\n+#define AT91_CIDR_VERSION_MASK\t\tGENMASK(4, 0)\n #define AT91_CIDR_EXT\t\t\tBIT(31)\n #define AT91_CIDR_MATCH_MASK\t\tGENMASK(30, 5)\n \n static const struct at91_soc socs[] __initconst = {\n #ifdef CONFIG_SOC_AT91RM9200\n-\tAT91_SOC(AT91RM9200_CIDR_MATCH, 0, \"at91rm9200 BGA\", \"at91rm9200\"),\n+\tAT91_SOC(AT91RM9200_CIDR_MATCH, AT91_CIDR_MATCH_MASK,\n+\t\t AT91_CIDR_VERSION_MASK, 0, \"at91rm9200 BGA\", \"at91rm9200\"),\n #endif\n #ifdef CONFIG_SOC_AT91SAM9\n-\tAT91_SOC(AT91SAM9260_CIDR_MATCH, 0, \"at91sam9260\", NULL),\n-\tAT91_SOC(AT91SAM9261_CIDR_MATCH, 0, \"at91sam9261\", NULL),\n-\tAT91_SOC(AT91SAM9263_CIDR_MATCH, 0, \"at91sam9263\", NULL),\n-\tAT91_SOC(AT91SAM9G20_CIDR_MATCH, 0, \"at91sam9g20\", NULL),\n-\tAT91_SOC(AT91SAM9RL64_CIDR_MATCH, 0, \"at91sam9rl64\", NULL),\n-\tAT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91SAM9M11_EXID_MATCH,\n+\tAT91_SOC(AT91SAM9260_CIDR_MATCH, AT91_CIDR_MATCH_MASK,\n+\t\t AT91_CIDR_VERSION_MASK, 0, \"at91sam9260\", NULL),\n+\tAT91_SOC(AT91SAM9261_CIDR_MATCH, AT91_CIDR_MATCH_MASK,\n+\t\t AT91_CIDR_VERSION_MASK, 0, \"at91sam9261\", NULL),\n+\tAT91_SOC(AT91SAM9263_CIDR_MATCH, AT91_CIDR_MATCH_MASK,\n+\t\t AT91_CIDR_VERSION_MASK, 0, \"at91sam9263\", NULL),\n+\tAT91_SOC(AT91SAM9G20_CIDR_MATCH, AT91_CIDR_MATCH_MASK,\n+\t\t AT91_CIDR_VERSION_MASK, 0, \"at91sam9g20\", NULL),\n+\tAT91_SOC(AT91SAM9RL64_CIDR_MATCH, AT91_CIDR_MATCH_MASK,\n+\t\t AT91_CIDR_VERSION_MASK, 0, \"at91sam9rl64\", NULL),\n+\tAT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91_CIDR_MATCH_MASK,\n+\t\t AT91_CIDR_VERSION_MASK, AT91SAM9M11_EXID_MATCH,\n \t\t \"at91sam9m11\", \"at91sam9g45\"),\n-\tAT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91SAM9M10_EXID_MATCH,\n+\tAT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91_CIDR_MATCH_MASK,\n+\t\t AT91_CIDR_VERSION_MASK, AT91SAM9M10_EXID_MATCH,\n \t\t \"at91sam9m10\", \"at91sam9g45\"),\n-\tAT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91SAM9G46_EXID_MATCH,\n+\tAT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91_CIDR_MATCH_MASK,\n+\t\t AT91_CIDR_VERSION_MASK, AT91SAM9G46_EXID_MATCH,\n \t\t \"at91sam9g46\", \"at91sam9g45\"),\n-\tAT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91SAM9G45_EXID_MATCH,\n+\tAT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91_CIDR_MATCH_MASK,\n+\t\t AT91_CIDR_VERSION_MASK, AT91SAM9G45_EXID_MATCH,\n \t\t \"at91sam9g45\", \"at91sam9g45\"),\n-\tAT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91SAM9G15_EXID_MATCH,\n+\tAT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91_CIDR_MATCH_MASK,\n+\t\t AT91_CIDR_VERSION_MASK, AT91SAM9G15_EXID_MATCH,\n \t\t \"at91sam9g15\", \"at91sam9x5\"),\n-\tAT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91SAM9G35_EXID_MATCH,\n+\tAT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91_CIDR_MATCH_MASK,\n+\t\t AT91_CIDR_VERSION_MASK, AT91SAM9G35_EXID_MATCH,\n \t\t \"at91sam9g35\", \"at91sam9x5\"),\n-\tAT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91SAM9X35_EXID_MATCH,\n+\tAT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91_CIDR_MATCH_MASK,\n+\t\t AT91_CIDR_VERSION_MASK, AT91SAM9X35_EXID_MATCH,\n \t\t \"at91sam9x35\", \"at91sam9x5\"),\n-\tAT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91SAM9G25_EXID_MATCH,\n+\tAT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91_CIDR_MATCH_MASK,\n+\t\t AT91_CIDR_VERSION_MASK, AT91SAM9G25_EXID_MATCH,\n \t\t \"at91sam9g25\", \"at91sam9x5\"),\n-\tAT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91SAM9X25_EXID_MATCH,\n+\tAT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91_CIDR_MATCH_MASK,\n+\t\t AT91_CIDR_VERSION_MASK, AT91SAM9X25_EXID_MATCH,\n \t\t \"at91sam9x25\", \"at91sam9x5\"),\n-\tAT91_SOC(AT91SAM9N12_CIDR_MATCH, AT91SAM9CN12_EXID_MATCH,\n+\tAT91_SOC(AT91SAM9N12_CIDR_MATCH, AT91_CIDR_MATCH_MASK,\n+\t\t AT91_CIDR_VERSION_MASK, AT91SAM9CN12_EXID_MATCH,\n \t\t \"at91sam9cn12\", \"at91sam9n12\"),\n-\tAT91_SOC(AT91SAM9N12_CIDR_MATCH, AT91SAM9N12_EXID_MATCH,\n+\tAT91_SOC(AT91SAM9N12_CIDR_MATCH, AT91_CIDR_MATCH_MASK,\n+\t\t AT91_CIDR_VERSION_MASK, AT91SAM9N12_EXID_MATCH,\n \t\t \"at91sam9n12\", \"at91sam9n12\"),\n-\tAT91_SOC(AT91SAM9N12_CIDR_MATCH, AT91SAM9CN11_EXID_MATCH,\n+\tAT91_SOC(AT91SAM9N12_CIDR_MATCH, AT91_CIDR_MATCH_MASK,\n+\t\t AT91_CIDR_VERSION_MASK, AT91SAM9CN11_EXID_MATCH,\n \t\t \"at91sam9cn11\", \"at91sam9n12\"),\n-\tAT91_SOC(AT91SAM9XE128_CIDR_MATCH, 0, \"at91sam9xe128\", \"at91sam9xe128\"),\n-\tAT91_SOC(AT91SAM9XE256_CIDR_MATCH, 0, \"at91sam9xe256\", \"at91sam9xe256\"),\n-\tAT91_SOC(AT91SAM9XE512_CIDR_MATCH, 0, \"at91sam9xe512\", \"at91sam9xe512\"),\n+\tAT91_SOC(AT91SAM9XE128_CIDR_MATCH, AT91_CIDR_MATCH_MASK,\n+\t\t AT91_CIDR_VERSION_MASK, 0, \"at91sam9xe128\", \"at91sam9xe128\"),\n+\tAT91_SOC(AT91SAM9XE256_CIDR_MATCH, AT91_CIDR_MATCH_MASK,\n+\t\t AT91_CIDR_VERSION_MASK, 0, \"at91sam9xe256\", \"at91sam9xe256\"),\n+\tAT91_SOC(AT91SAM9XE512_CIDR_MATCH, AT91_CIDR_MATCH_MASK,\n+\t\t AT91_CIDR_VERSION_MASK, 0, \"at91sam9xe512\", \"at91sam9xe512\"),\n #endif\n #ifdef CONFIG_SOC_SAM9X60\n-\tAT91_SOC(SAM9X60_CIDR_MATCH, SAM9X60_EXID_MATCH, \"sam9x60\", \"sam9x60\"),\n+\tAT91_SOC(SAM9X60_CIDR_MATCH, AT91_CIDR_MATCH_MASK,\n+\t\t AT91_CIDR_VERSION_MASK, SAM9X60_EXID_MATCH,\n+\t\t \"sam9x60\", \"sam9x60\"),\n \tAT91_SOC(SAM9X60_CIDR_MATCH, SAM9X60_D5M_EXID_MATCH,\n+\t\t AT91_CIDR_VERSION_MASK, SAM9X60_EXID_MATCH,\n \t\t \"sam9x60 64MiB DDR2 SiP\", \"sam9x60\"),\n \tAT91_SOC(SAM9X60_CIDR_MATCH, SAM9X60_D1G_EXID_MATCH,\n+\t\t AT91_CIDR_VERSION_MASK, SAM9X60_EXID_MATCH,\n \t\t \"sam9x60 128MiB DDR2 SiP\", \"sam9x60\"),\n \tAT91_SOC(SAM9X60_CIDR_MATCH, SAM9X60_D6K_EXID_MATCH,\n+\t\t AT91_CIDR_VERSION_MASK, SAM9X60_EXID_MATCH,\n \t\t \"sam9x60 8MiB SDRAM SiP\", \"sam9x60\"),\n #endif\n #ifdef CONFIG_SOC_SAMA5\n-\tAT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D21CU_EXID_MATCH,\n+\tAT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,\n+\t\t AT91_CIDR_VERSION_MASK, SAMA5D21CU_EXID_MATCH,\n \t\t \"sama5d21\", \"sama5d2\"),\n-\tAT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D22CU_EXID_MATCH,\n+\tAT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,\n+\t\t AT91_CIDR_VERSION_MASK, SAMA5D22CU_EXID_MATCH,\n \t\t \"sama5d22\", \"sama5d2\"),\n-\tAT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D225C_D1M_EXID_MATCH,\n+\tAT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,\n+\t\t AT91_CIDR_VERSION_MASK, SAMA5D225C_D1M_EXID_MATCH,\n \t\t \"sama5d225c 16MiB SiP\", \"sama5d2\"),\n-\tAT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D23CU_EXID_MATCH,\n+\tAT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,\n+\t\t AT91_CIDR_VERSION_MASK, SAMA5D23CU_EXID_MATCH,\n \t\t \"sama5d23\", \"sama5d2\"),\n-\tAT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D24CX_EXID_MATCH,\n+\tAT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,\n+\t\t AT91_CIDR_VERSION_MASK, SAMA5D24CX_EXID_MATCH,\n \t\t \"sama5d24\", \"sama5d2\"),\n-\tAT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D24CU_EXID_MATCH,\n+\tAT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,\n+\t\t AT91_CIDR_VERSION_MASK, SAMA5D24CU_EXID_MATCH,\n \t\t \"sama5d24\", \"sama5d2\"),\n-\tAT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D26CU_EXID_MATCH,\n+\tAT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,\n+\t\t AT91_CIDR_VERSION_MASK, SAMA5D26CU_EXID_MATCH,\n \t\t \"sama5d26\", \"sama5d2\"),\n-\tAT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D27CU_EXID_MATCH,\n+\tAT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,\n+\t\t AT91_CIDR_VERSION_MASK, SAMA5D27CU_EXID_MATCH,\n \t\t \"sama5d27\", \"sama5d2\"),\n-\tAT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D27CN_EXID_MATCH,\n+\tAT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,\n+\t\t AT91_CIDR_VERSION_MASK, SAMA5D27CN_EXID_MATCH,\n \t\t \"sama5d27\", \"sama5d2\"),\n-\tAT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D27C_D1G_EXID_MATCH,\n+\tAT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,\n+\t\t AT91_CIDR_VERSION_MASK, SAMA5D27C_D1G_EXID_MATCH,\n \t\t \"sama5d27c 128MiB SiP\", \"sama5d2\"),\n-\tAT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D27C_D5M_EXID_MATCH,\n+\tAT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,\n+\t\t AT91_CIDR_VERSION_MASK, SAMA5D27C_D5M_EXID_MATCH,\n \t\t \"sama5d27c 64MiB SiP\", \"sama5d2\"),\n-\tAT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D27C_LD1G_EXID_MATCH,\n+\tAT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,\n+\t\t AT91_CIDR_VERSION_MASK, SAMA5D27C_LD1G_EXID_MATCH,\n \t\t \"sama5d27c 128MiB LPDDR2 SiP\", \"sama5d2\"),\n-\tAT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D27C_LD2G_EXID_MATCH,\n+\tAT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,\n+\t\t AT91_CIDR_VERSION_MASK, SAMA5D27C_LD2G_EXID_MATCH,\n \t\t \"sama5d27c 256MiB LPDDR2 SiP\", \"sama5d2\"),\n-\tAT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D28CU_EXID_MATCH,\n+\tAT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,\n+\t\t AT91_CIDR_VERSION_MASK, SAMA5D28CU_EXID_MATCH,\n \t\t \"sama5d28\", \"sama5d2\"),\n-\tAT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D28CN_EXID_MATCH,\n+\tAT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,\n+\t\t AT91_CIDR_VERSION_MASK, SAMA5D28CN_EXID_MATCH,\n \t\t \"sama5d28\", \"sama5d2\"),\n-\tAT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D28C_D1G_EXID_MATCH,\n+\tAT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,\n+\t\t AT91_CIDR_VERSION_MASK, SAMA5D28C_D1G_EXID_MATCH,\n \t\t \"sama5d28c 128MiB SiP\", \"sama5d2\"),\n-\tAT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D28C_LD1G_EXID_MATCH,\n+\tAT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,\n+\t\t AT91_CIDR_VERSION_MASK, SAMA5D28C_LD1G_EXID_MATCH,\n \t\t \"sama5d28c 128MiB LPDDR2 SiP\", \"sama5d2\"),\n-\tAT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D28C_LD2G_EXID_MATCH,\n+\tAT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,\n+\t\t AT91_CIDR_VERSION_MASK, SAMA5D28C_LD2G_EXID_MATCH,\n \t\t \"sama5d28c 256MiB LPDDR2 SiP\", \"sama5d2\"),\n-\tAT91_SOC(SAMA5D3_CIDR_MATCH, SAMA5D31_EXID_MATCH,\n+\tAT91_SOC(SAMA5D3_CIDR_MATCH, AT91_CIDR_MATCH_MASK,\n+\t\t AT91_CIDR_VERSION_MASK, SAMA5D31_EXID_MATCH,\n \t\t \"sama5d31\", \"sama5d3\"),\n-\tAT91_SOC(SAMA5D3_CIDR_MATCH, SAMA5D33_EXID_MATCH,\n+\tAT91_SOC(SAMA5D3_CIDR_MATCH, AT91_CIDR_MATCH_MASK,\n+\t\t AT91_CIDR_VERSION_MASK, SAMA5D33_EXID_MATCH,\n \t\t \"sama5d33\", \"sama5d3\"),\n-\tAT91_SOC(SAMA5D3_CIDR_MATCH, SAMA5D34_EXID_MATCH,\n+\tAT91_SOC(SAMA5D3_CIDR_MATCH, AT91_CIDR_MATCH_MASK,\n+\t\t AT91_CIDR_VERSION_MASK, SAMA5D34_EXID_MATCH,\n \t\t \"sama5d34\", \"sama5d3\"),\n-\tAT91_SOC(SAMA5D3_CIDR_MATCH, SAMA5D35_EXID_MATCH,\n+\tAT91_SOC(SAMA5D3_CIDR_MATCH, AT91_CIDR_MATCH_MASK,\n+\t\t AT91_CIDR_VERSION_MASK, SAMA5D35_EXID_MATCH,\n \t\t \"sama5d35\", \"sama5d3\"),\n-\tAT91_SOC(SAMA5D3_CIDR_MATCH, SAMA5D36_EXID_MATCH,\n+\tAT91_SOC(SAMA5D3_CIDR_MATCH, AT91_CIDR_MATCH_MASK,\n+\t\t AT91_CIDR_VERSION_MASK, SAMA5D36_EXID_MATCH,\n \t\t \"sama5d36\", \"sama5d3\"),\n-\tAT91_SOC(SAMA5D4_CIDR_MATCH, SAMA5D41_EXID_MATCH,\n+\tAT91_SOC(SAMA5D4_CIDR_MATCH, AT91_CIDR_MATCH_MASK,\n+\t\t AT91_CIDR_VERSION_MASK, SAMA5D41_EXID_MATCH,\n \t\t \"sama5d41\", \"sama5d4\"),\n-\tAT91_SOC(SAMA5D4_CIDR_MATCH, SAMA5D42_EXID_MATCH,\n+\tAT91_SOC(SAMA5D4_CIDR_MATCH, AT91_CIDR_MATCH_MASK,\n+\t\t AT91_CIDR_VERSION_MASK, SAMA5D42_EXID_MATCH,\n \t\t \"sama5d42\", \"sama5d4\"),\n-\tAT91_SOC(SAMA5D4_CIDR_MATCH, SAMA5D43_EXID_MATCH,\n+\tAT91_SOC(SAMA5D4_CIDR_MATCH, AT91_CIDR_MATCH_MASK,\n+\t\t AT91_CIDR_VERSION_MASK, SAMA5D43_EXID_MATCH,\n \t\t \"sama5d43\", \"sama5d4\"),\n-\tAT91_SOC(SAMA5D4_CIDR_MATCH, SAMA5D44_EXID_MATCH,\n+\tAT91_SOC(SAMA5D4_CIDR_MATCH, AT91_CIDR_MATCH_MASK,\n+\t\t AT91_CIDR_VERSION_MASK, SAMA5D44_EXID_MATCH,\n \t\t \"sama5d44\", \"sama5d4\"),\n #endif\n #ifdef CONFIG_SOC_SAMV7\n-\tAT91_SOC(SAME70Q21_CIDR_MATCH, SAME70Q21_EXID_MATCH,\n+\tAT91_SOC(SAME70Q21_CIDR_MATCH, AT91_CIDR_MATCH_MASK,\n+\t\t AT91_CIDR_VERSION_MASK, SAME70Q21_EXID_MATCH,\n \t\t \"same70q21\", \"same7\"),\n-\tAT91_SOC(SAME70Q20_CIDR_MATCH, SAME70Q20_EXID_MATCH,\n+\tAT91_SOC(SAME70Q20_CIDR_MATCH, AT91_CIDR_MATCH_MASK,\n+\t\t AT91_CIDR_VERSION_MASK, SAME70Q20_EXID_MATCH,\n \t\t \"same70q20\", \"same7\"),\n-\tAT91_SOC(SAME70Q19_CIDR_MATCH, SAME70Q19_EXID_MATCH,\n+\tAT91_SOC(SAME70Q19_CIDR_MATCH, AT91_CIDR_MATCH_MASK\n+\t\t AT91_CIDR_VERSION_MASK, SAME70Q19_EXID_MATCH,\n \t\t \"same70q19\", \"same7\"),\n-\tAT91_SOC(SAMS70Q21_CIDR_MATCH, SAMS70Q21_EXID_MATCH,\n+\tAT91_SOC(SAMS70Q21_CIDR_MATCH, AT91_CIDR_MATCH_MASK,\n+\t\t AT91_CIDR_VERSION_MASK, SAMS70Q21_EXID_MATCH,\n \t\t \"sams70q21\", \"sams7\"),\n-\tAT91_SOC(SAMS70Q20_CIDR_MATCH, SAMS70Q20_EXID_MATCH,\n+\tAT91_SOC(SAMS70Q20_CIDR_MATCH, AT91_CIDR_MATCH_MASK,\n+\t\t AT91_CIDR_VERSION_MASK, SAMS70Q20_EXID_MATCH,\n \t\t \"sams70q20\", \"sams7\"),\n-\tAT91_SOC(SAMS70Q19_CIDR_MATCH, SAMS70Q19_EXID_MATCH,\n+\tAT91_SOC(SAMS70Q19_CIDR_MATCH, AT91_CIDR_MATCH_MASK,\n+\t\t AT91_CIDR_VERSION_MASK, SAMS70Q19_EXID_MATCH,\n \t\t \"sams70q19\", \"sams7\"),\n-\tAT91_SOC(SAMV71Q21_CIDR_MATCH, SAMV71Q21_EXID_MATCH,\n+\tAT91_SOC(SAMV71Q21_CIDR_MATCH, AT91_CIDR_MATCH_MASK,\n+\t\t AT91_CIDR_VERSION_MASK, SAMV71Q21_EXID_MATCH,\n \t\t \"samv71q21\", \"samv7\"),\n-\tAT91_SOC(SAMV71Q20_CIDR_MATCH, SAMV71Q20_EXID_MATCH,\n+\tAT91_SOC(SAMV71Q20_CIDR_MATCH, AT91_CIDR_MATCH_MASK,\n+\t\t AT91_CIDR_VERSION_MASK, SAMV71Q20_EXID_MATCH,\n \t\t \"samv71q20\", \"samv7\"),\n-\tAT91_SOC(SAMV71Q19_CIDR_MATCH, SAMV71Q19_EXID_MATCH,\n+\tAT91_SOC(SAMV71Q19_CIDR_MATCH, AT91_CIDR_MATCH_MASK,\n+\t\t AT91_CIDR_VERSION_MASK, SAMV71Q19_EXID_MATCH,\n \t\t \"samv71q19\", \"samv7\"),\n-\tAT91_SOC(SAMV70Q20_CIDR_MATCH, SAMV70Q20_EXID_MATCH,\n+\tAT91_SOC(SAMV70Q20_CIDR_MATCH, AT91_CIDR_MATCH_MASK,\n+\t\t AT91_CIDR_VERSION_MASK, SAMV70Q20_EXID_MATCH,\n \t\t \"samv70q20\", \"samv7\"),\n-\tAT91_SOC(SAMV70Q19_CIDR_MATCH, SAMV70Q19_EXID_MATCH,\n+\tAT91_SOC(SAMV70Q19_CIDR_MATCH, AT91_CIDR_MATCH_MASK,\n+\t\t AT91_CIDR_VERSION_MASK, SAMV70Q19_EXID_MATCH,\n \t\t \"samv70q19\", \"samv7\"),\n #endif\n \t{ /* sentinel */ },\n@@ -191,8 +256,12 @@ static int __init at91_get_cidr_exid_fro\n {\n \tstruct device_node *np;\n \tvoid __iomem *regs;\n+\tstatic const struct of_device_id chipids[] = {\n+\t\t{ .compatible = \"atmel,sama5d2-chipid\" },\n+\t\t{ },\n+\t};\n \n-\tnp = of_find_compatible_node(NULL, NULL, \"atmel,sama5d2-chipid\");\n+\tnp = of_find_matching_node(NULL, chipids);\n \tif (!np)\n \t\treturn -ENODEV;\n \n@@ -235,7 +304,7 @@ struct soc_device * __init at91_soc_init\n \t}\n \n \tfor (soc = socs; soc->name; soc++) {\n-\t\tif (soc->cidr_match != (cidr & AT91_CIDR_MATCH_MASK))\n+\t\tif (soc->cidr_match != (cidr & soc->cidr_mask))\n \t\t\tcontinue;\n \n \t\tif (!(cidr & AT91_CIDR_EXT) || soc->exid_match == exid)\n@@ -254,7 +323,7 @@ struct soc_device * __init at91_soc_init\n \tsoc_dev_attr->family = soc->family;\n \tsoc_dev_attr->soc_id = soc->name;\n \tsoc_dev_attr->revision = kasprintf(GFP_KERNEL, \"%X\",\n-\t\t\t\t\t   AT91_CIDR_VERSION(cidr));\n+\t\t\t\t\t   AT91_CIDR_VERSION(cidr, soc->version_mask));\n \tsoc_dev = soc_device_register(soc_dev_attr);\n \tif (IS_ERR(soc_dev)) {\n \t\tkfree(soc_dev_attr->revision);\n@@ -266,7 +335,7 @@ struct soc_device * __init at91_soc_init\n \tif (soc->family)\n \t\tpr_info(\"Detected SoC family: %s\\n\", soc->family);\n \tpr_info(\"Detected SoC: %s, revision %X\\n\", soc->name,\n-\t\tAT91_CIDR_VERSION(cidr));\n+\t\tAT91_CIDR_VERSION(cidr, soc->version_mask));\n \n \treturn soc_dev;\n }\n--- a/drivers/soc/atmel/soc.h\n+++ b/drivers/soc/atmel/soc.h\n@@ -16,14 +16,19 @@\n \n struct at91_soc {\n \tu32 cidr_match;\n+\tu32 cidr_mask;\n+\tu32 version_mask;\n \tu32 exid_match;\n \tconst char *name;\n \tconst char *family;\n };\n \n-#define AT91_SOC(__cidr, __exid, __name, __family)\t\t\\\n+#define AT91_SOC(__cidr, __cidr_mask, __version_mask, __exid,\t\\\n+\t\t __name, __family)\t\t\t\t\\\n \t{\t\t\t\t\t\t\t\\\n \t\t.cidr_match = (__cidr),\t\t\t\t\\\n+\t\t.cidr_mask = (__cidr_mask),\t\t\t\\\n+\t\t.version_mask = (__version_mask),\t\t\\\n \t\t.exid_match = (__exid),\t\t\t\t\\\n \t\t.name = (__name),\t\t\t\t\\\n \t\t.family = (__family),\t\t\t\t\\\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/140-drivers-soc-atmel-add-support-for-sama7g5.patch",
    "content": "From e20bb57fc51741677a6fcae04e564797fd18921b Mon Sep 17 00:00:00 2001\nFrom: Claudiu Beznea <claudiu.beznea@microchip.com>\nDate: Fri, 22 Jan 2021 14:21:37 +0200\nSubject: [PATCH 140/247] drivers: soc: atmel: add support for sama7g5\n\nAdd support for SAMA7G5 SoCs.\n\nSigned-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>\nSigned-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>\nLink: https://lore.kernel.org/r/1611318097-8970-8-git-send-email-claudiu.beznea@microchip.com\n---\n drivers/soc/atmel/soc.c | 18 ++++++++++++++++++\n drivers/soc/atmel/soc.h |  6 ++++++\n 2 files changed, 24 insertions(+)\n\n--- a/drivers/soc/atmel/soc.c\n+++ b/drivers/soc/atmel/soc.c\n@@ -27,8 +27,10 @@\n #define AT91_CHIPID_EXID\t\t0x04\n #define AT91_CIDR_VERSION(x, m)\t\t((x) & (m))\n #define AT91_CIDR_VERSION_MASK\t\tGENMASK(4, 0)\n+#define AT91_CIDR_VERSION_MASK_SAMA7G5\tGENMASK(3, 0)\n #define AT91_CIDR_EXT\t\t\tBIT(31)\n #define AT91_CIDR_MATCH_MASK\t\tGENMASK(30, 5)\n+#define AT91_CIDR_MASK_SAMA7G5\t\tGENMASK(27, 5)\n \n static const struct at91_soc socs[] __initconst = {\n #ifdef CONFIG_SOC_AT91RM9200\n@@ -221,6 +223,20 @@ static const struct at91_soc socs[] __in\n \t\t AT91_CIDR_VERSION_MASK, SAMV70Q19_EXID_MATCH,\n \t\t \"samv70q19\", \"samv7\"),\n #endif\n+#ifdef CONFIG_SOC_SAMA7\n+\tAT91_SOC(SAMA7G5_CIDR_MATCH, AT91_CIDR_MATCH_MASK,\n+\t\t AT91_CIDR_VERSION_MASK_SAMA7G5, SAMA7G51_EXID_MATCH,\n+\t\t \"sama7g51\", \"sama7g5\"),\n+\tAT91_SOC(SAMA7G5_CIDR_MATCH, AT91_CIDR_MATCH_MASK,\n+\t\t AT91_CIDR_VERSION_MASK_SAMA7G5, SAMA7G52_EXID_MATCH,\n+\t\t \"sama7g52\", \"sama7g5\"),\n+\tAT91_SOC(SAMA7G5_CIDR_MATCH, AT91_CIDR_MATCH_MASK,\n+\t\t AT91_CIDR_VERSION_MASK_SAMA7G5, SAMA7G53_EXID_MATCH,\n+\t\t \"sama7g53\", \"sama7g5\"),\n+\tAT91_SOC(SAMA7G5_CIDR_MATCH, AT91_CIDR_MATCH_MASK,\n+\t\t AT91_CIDR_VERSION_MASK_SAMA7G5, SAMA7G54_EXID_MATCH,\n+\t\t \"sama7g54\", \"sama7g5\"),\n+#endif\n \t{ /* sentinel */ },\n };\n \n@@ -258,6 +274,7 @@ static int __init at91_get_cidr_exid_fro\n \tvoid __iomem *regs;\n \tstatic const struct of_device_id chipids[] = {\n \t\t{ .compatible = \"atmel,sama5d2-chipid\" },\n+\t\t{ .compatible = \"microchip,sama7g5-chipid\" },\n \t\t{ },\n \t};\n \n@@ -345,6 +362,7 @@ static const struct of_device_id at91_so\n \t{ .compatible = \"atmel,at91sam9\", },\n \t{ .compatible = \"atmel,sama5\", },\n \t{ .compatible = \"atmel,samv7\", },\n+\t{ .compatible = \"microchip,sama7g5\", },\n \t{ }\n };\n \n--- a/drivers/soc/atmel/soc.h\n+++ b/drivers/soc/atmel/soc.h\n@@ -48,6 +48,7 @@ at91_soc_init(const struct at91_soc *soc\n #define AT91SAM9X5_CIDR_MATCH\t\t0x019a05a0\n #define AT91SAM9N12_CIDR_MATCH\t\t0x019a07a0\n #define SAM9X60_CIDR_MATCH\t\t0x019b35a0\n+#define SAMA7G5_CIDR_MATCH\t\t0x00162100\n \n #define AT91SAM9M11_EXID_MATCH\t\t0x00000001\n #define AT91SAM9M10_EXID_MATCH\t\t0x00000002\n@@ -69,6 +70,11 @@ at91_soc_init(const struct at91_soc *soc\n #define SAM9X60_D1G_EXID_MATCH\t\t0x00000010\n #define SAM9X60_D6K_EXID_MATCH\t\t0x00000011\n \n+#define SAMA7G51_EXID_MATCH\t\t0x3\n+#define SAMA7G52_EXID_MATCH\t\t0x2\n+#define SAMA7G53_EXID_MATCH\t\t0x1\n+#define SAMA7G54_EXID_MATCH\t\t0x0\n+\n #define AT91SAM9XE128_CIDR_MATCH\t0x329973a0\n #define AT91SAM9XE256_CIDR_MATCH\t0x329a93a0\n #define AT91SAM9XE512_CIDR_MATCH\t0x329aa3a0\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/141-drivers-soc-atmel-add-spdx-license-identifier.patch",
    "content": "From acd4816cfa7811b13ca2864645f2de41031ccf4d Mon Sep 17 00:00:00 2001\nFrom: Claudiu Beznea <claudiu.beznea@microchip.com>\nDate: Tue, 26 Jan 2021 11:29:30 +0200\nSubject: [PATCH 141/247] drivers: soc: atmel: add spdx license identifier\n\nAdd SPDX-License-Identifier.\n\nSigned-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>\n[nicolas.ferre@microhcip.com: remove license boilerplate now it's useless]\nSigned-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>\nLink: https://lore.kernel.org/r/1611653376-24168-2-git-send-email-claudiu.beznea@microchip.com\n---\n drivers/soc/atmel/soc.c | 6 +-----\n drivers/soc/atmel/soc.h | 6 +-----\n 2 files changed, 2 insertions(+), 10 deletions(-)\n\n--- a/drivers/soc/atmel/soc.c\n+++ b/drivers/soc/atmel/soc.c\n@@ -1,13 +1,9 @@\n+// SPDX-License-Identifier: GPL-2.0-only\n /*\n  * Copyright (C) 2015 Atmel\n  *\n  * Alexandre Belloni <alexandre.belloni@free-electrons.com\n  * Boris Brezillon <boris.brezillon@free-electrons.com\n- *\n- * This file is licensed under the terms of the GNU General Public\n- * License version 2.  This program is licensed \"as is\" without any\n- * warranty of any kind, whether express or implied.\n- *\n  */\n \n #define pr_fmt(fmt)\t\"AT91: \" fmt\n--- a/drivers/soc/atmel/soc.h\n+++ b/drivers/soc/atmel/soc.h\n@@ -1,12 +1,8 @@\n+/* SPDX-License-Identifier: GPL-2.0-only */\n /*\n  * Copyright (C) 2015 Atmel\n  *\n  * Boris Brezillon <boris.brezillon@free-electrons.com\n- *\n- * This file is licensed under the terms of the GNU General Public\n- * License version 2.  This program is licensed \"as is\" without any\n- * warranty of any kind, whether express or implied.\n- *\n  */\n \n #ifndef __AT91_SOC_H\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/142-drivers-soc-atmel-fix-type-for-same7.patch",
    "content": "From b105d1dfab46c13070b8bdea1ab28d223a9c1bee Mon Sep 17 00:00:00 2001\nFrom: Arnd Bergmann <arnd@arndb.de>\nDate: Thu, 4 Feb 2021 16:49:25 +0100\nSubject: [PATCH 142/247] drivers: soc: atmel: fix type for same7\n\nA missing comma caused a build failure:\n\ndrivers/soc/atmel/soc.c:196:24: error: too few arguments provided to function-like macro invocation\n\nFixes: af3a10513cd6 (\"drivers: soc: atmel: add per soc id and version match masks\")\nSigned-off-by: Arnd Bergmann <arnd@arndb.de>\nAcked-by: Alexandre Belloni <alexandre.belloni@bootlin.com>\nSigned-off-by: Arnd Bergmann <arnd@arndb.de>\n---\n drivers/soc/atmel/soc.c | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/drivers/soc/atmel/soc.c\n+++ b/drivers/soc/atmel/soc.c\n@@ -191,7 +191,7 @@ static const struct at91_soc socs[] __in\n \tAT91_SOC(SAME70Q20_CIDR_MATCH, AT91_CIDR_MATCH_MASK,\n \t\t AT91_CIDR_VERSION_MASK, SAME70Q20_EXID_MATCH,\n \t\t \"same70q20\", \"same7\"),\n-\tAT91_SOC(SAME70Q19_CIDR_MATCH, AT91_CIDR_MATCH_MASK\n+\tAT91_SOC(SAME70Q19_CIDR_MATCH, AT91_CIDR_MATCH_MASK,\n \t\t AT91_CIDR_VERSION_MASK, SAME70Q19_EXID_MATCH,\n \t\t \"same70q19\", \"same7\"),\n \tAT91_SOC(SAMS70Q21_CIDR_MATCH, AT91_CIDR_MATCH_MASK,\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/143-clocksource-drivers-timer-microchip-pit64b-Add-clock.patch",
    "content": "From 5f090a664d62ceeaf9a0f482426e35cab18d65a9 Mon Sep 17 00:00:00 2001\nFrom: Claudiu Beznea <claudiu.beznea@microchip.com>\nDate: Tue, 19 Jan 2021 14:59:25 +0200\nSubject: [PATCH 143/247] clocksource/drivers/timer-microchip-pit64b: Add\n clocksource suspend/resume\n\nAdd suspend/resume support for clocksource timer.\n\nSigned-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>\nSigned-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>\nLink: https://lore.kernel.org/r/1611061165-30180-1-git-send-email-claudiu.beznea@microchip.com\n---\n drivers/clocksource/timer-microchip-pit64b.c | 86 ++++++++++++++++----\n 1 file changed, 71 insertions(+), 15 deletions(-)\n\n--- a/drivers/clocksource/timer-microchip-pit64b.c\n+++ b/drivers/clocksource/timer-microchip-pit64b.c\n@@ -71,10 +71,24 @@ struct mchp_pit64b_clkevt {\n \tstruct clock_event_device\tclkevt;\n };\n \n-#define to_mchp_pit64b_timer(x) \\\n+#define clkevt_to_mchp_pit64b_timer(x) \\\n \t((struct mchp_pit64b_timer *)container_of(x,\\\n \t\tstruct mchp_pit64b_clkevt, clkevt))\n \n+/**\n+ * mchp_pit64b_clksrc - PIT64B clocksource data structure\n+ * @timer: PIT64B timer\n+ * @clksrc: clocksource\n+ */\n+struct mchp_pit64b_clksrc {\n+\tstruct mchp_pit64b_timer\ttimer;\n+\tstruct clocksource\t\tclksrc;\n+};\n+\n+#define clksrc_to_mchp_pit64b_timer(x) \\\n+\t((struct mchp_pit64b_timer *)container_of(x,\\\n+\t\tstruct mchp_pit64b_clksrc, clksrc))\n+\n /* Base address for clocksource timer. */\n static void __iomem *mchp_pit64b_cs_base;\n /* Default cycles for clockevent timer. */\n@@ -116,6 +130,36 @@ static inline void mchp_pit64b_reset(str\n \twritel_relaxed(MCHP_PIT64B_CR_START, timer->base + MCHP_PIT64B_CR);\n }\n \n+static void mchp_pit64b_suspend(struct mchp_pit64b_timer *timer)\n+{\n+\twritel_relaxed(MCHP_PIT64B_CR_SWRST, timer->base + MCHP_PIT64B_CR);\n+\tif (timer->mode & MCHP_PIT64B_MR_SGCLK)\n+\t\tclk_disable_unprepare(timer->gclk);\n+\tclk_disable_unprepare(timer->pclk);\n+}\n+\n+static void mchp_pit64b_resume(struct mchp_pit64b_timer *timer)\n+{\n+\tclk_prepare_enable(timer->pclk);\n+\tif (timer->mode & MCHP_PIT64B_MR_SGCLK)\n+\t\tclk_prepare_enable(timer->gclk);\n+}\n+\n+static void mchp_pit64b_clksrc_suspend(struct clocksource *cs)\n+{\n+\tstruct mchp_pit64b_timer *timer = clksrc_to_mchp_pit64b_timer(cs);\n+\n+\tmchp_pit64b_suspend(timer);\n+}\n+\n+static void mchp_pit64b_clksrc_resume(struct clocksource *cs)\n+{\n+\tstruct mchp_pit64b_timer *timer = clksrc_to_mchp_pit64b_timer(cs);\n+\n+\tmchp_pit64b_resume(timer);\n+\tmchp_pit64b_reset(timer, ULLONG_MAX, MCHP_PIT64B_MR_CONT, 0);\n+}\n+\n static u64 mchp_pit64b_clksrc_read(struct clocksource *cs)\n {\n \treturn mchp_pit64b_cnt_read(mchp_pit64b_cs_base);\n@@ -128,7 +172,7 @@ static u64 notrace mchp_pit64b_sched_rea\n \n static int mchp_pit64b_clkevt_shutdown(struct clock_event_device *cedev)\n {\n-\tstruct mchp_pit64b_timer *timer = to_mchp_pit64b_timer(cedev);\n+\tstruct mchp_pit64b_timer *timer = clkevt_to_mchp_pit64b_timer(cedev);\n \n \twritel_relaxed(MCHP_PIT64B_CR_SWRST, timer->base + MCHP_PIT64B_CR);\n \n@@ -137,7 +181,7 @@ static int mchp_pit64b_clkevt_shutdown(s\n \n static int mchp_pit64b_clkevt_set_periodic(struct clock_event_device *cedev)\n {\n-\tstruct mchp_pit64b_timer *timer = to_mchp_pit64b_timer(cedev);\n+\tstruct mchp_pit64b_timer *timer = clkevt_to_mchp_pit64b_timer(cedev);\n \n \tmchp_pit64b_reset(timer, mchp_pit64b_ce_cycles, MCHP_PIT64B_MR_CONT,\n \t\t\t  MCHP_PIT64B_IER_PERIOD);\n@@ -148,7 +192,7 @@ static int mchp_pit64b_clkevt_set_period\n static int mchp_pit64b_clkevt_set_next_event(unsigned long evt,\n \t\t\t\t\t     struct clock_event_device *cedev)\n {\n-\tstruct mchp_pit64b_timer *timer = to_mchp_pit64b_timer(cedev);\n+\tstruct mchp_pit64b_timer *timer = clkevt_to_mchp_pit64b_timer(cedev);\n \n \tmchp_pit64b_reset(timer, evt, MCHP_PIT64B_MR_ONE_SHOT,\n \t\t\t  MCHP_PIT64B_IER_PERIOD);\n@@ -158,21 +202,16 @@ static int mchp_pit64b_clkevt_set_next_e\n \n static void mchp_pit64b_clkevt_suspend(struct clock_event_device *cedev)\n {\n-\tstruct mchp_pit64b_timer *timer = to_mchp_pit64b_timer(cedev);\n+\tstruct mchp_pit64b_timer *timer = clkevt_to_mchp_pit64b_timer(cedev);\n \n-\twritel_relaxed(MCHP_PIT64B_CR_SWRST, timer->base + MCHP_PIT64B_CR);\n-\tif (timer->mode & MCHP_PIT64B_MR_SGCLK)\n-\t\tclk_disable_unprepare(timer->gclk);\n-\tclk_disable_unprepare(timer->pclk);\n+\tmchp_pit64b_suspend(timer);\n }\n \n static void mchp_pit64b_clkevt_resume(struct clock_event_device *cedev)\n {\n-\tstruct mchp_pit64b_timer *timer = to_mchp_pit64b_timer(cedev);\n+\tstruct mchp_pit64b_timer *timer = clkevt_to_mchp_pit64b_timer(cedev);\n \n-\tclk_prepare_enable(timer->pclk);\n-\tif (timer->mode & MCHP_PIT64B_MR_SGCLK)\n-\t\tclk_prepare_enable(timer->gclk);\n+\tmchp_pit64b_resume(timer);\n }\n \n static irqreturn_t mchp_pit64b_interrupt(int irq, void *dev_id)\n@@ -296,20 +335,37 @@ done:\n static int __init mchp_pit64b_init_clksrc(struct mchp_pit64b_timer *timer,\n \t\t\t\t\t  u32 clk_rate)\n {\n+\tstruct mchp_pit64b_clksrc *cs;\n \tint ret;\n \n+\tcs = kzalloc(sizeof(*cs), GFP_KERNEL);\n+\tif (!cs)\n+\t\treturn -ENOMEM;\n+\n \tmchp_pit64b_reset(timer, ULLONG_MAX, MCHP_PIT64B_MR_CONT, 0);\n \n \tmchp_pit64b_cs_base = timer->base;\n \n-\tret = clocksource_mmio_init(timer->base, MCHP_PIT64B_NAME, clk_rate,\n-\t\t\t\t    210, 64, mchp_pit64b_clksrc_read);\n+\tcs->timer.base = timer->base;\n+\tcs->timer.pclk = timer->pclk;\n+\tcs->timer.gclk = timer->gclk;\n+\tcs->timer.mode = timer->mode;\n+\tcs->clksrc.name = MCHP_PIT64B_NAME;\n+\tcs->clksrc.mask = CLOCKSOURCE_MASK(64);\n+\tcs->clksrc.flags = CLOCK_SOURCE_IS_CONTINUOUS;\n+\tcs->clksrc.rating = 210;\n+\tcs->clksrc.read = mchp_pit64b_clksrc_read;\n+\tcs->clksrc.suspend = mchp_pit64b_clksrc_suspend;\n+\tcs->clksrc.resume = mchp_pit64b_clksrc_resume;\n+\n+\tret = clocksource_register_hz(&cs->clksrc, clk_rate);\n \tif (ret) {\n \t\tpr_debug(\"clksrc: Failed to register PIT64B clocksource!\\n\");\n \n \t\t/* Stop timer. */\n \t\twritel_relaxed(MCHP_PIT64B_CR_SWRST,\n \t\t\t       timer->base + MCHP_PIT64B_CR);\n+\t\tkfree(cs);\n \n \t\treturn ret;\n \t}\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/144-ASoC-atmel-pdc-Use-managed-DMA-buffer-allocation.patch",
    "content": "From 0b20c174a17dcfa805ddac1301a5af7298877ec3 Mon Sep 17 00:00:00 2001\nFrom: Lars-Peter Clausen <lars@metafoo.de>\nDate: Wed, 6 Jan 2021 14:36:48 +0100\nSubject: [PATCH 144/247] ASoC: atmel-pdc: Use managed DMA buffer allocation\n\nInstead of manually managing its DMA buffers using\ndma_{alloc,free}_coherent() lets the sound core take care of this using\nmanaged buffers.\n\nOn one hand this reduces the amount of boiler plate code, but the main\nmotivation for the change is to use the shared code where possible. This\nmakes it easier to argue about correctness and that the code does not\ncontain subtle bugs like data leakage or similar.\n\nSigned-off-by: Lars-Peter Clausen <lars@metafoo.de>\nReviewed-by: Codrin Ciubotariu <codrin.ciubotariu@microchip.com>\nLink: https://lore.kernel.org/r/20210106133650.13509-1-lars@metafoo.de\nSigned-off-by: Mark Brown <broonie@kernel.org>\n---\n sound/soc/atmel/atmel-pcm-pdc.c | 78 ++-------------------------------\n 1 file changed, 4 insertions(+), 74 deletions(-)\n\n--- a/sound/soc/atmel/atmel-pcm-pdc.c\n+++ b/sound/soc/atmel/atmel-pcm-pdc.c\n@@ -34,86 +34,21 @@\n #include \"atmel-pcm.h\"\n \n \n-static int atmel_pcm_preallocate_dma_buffer(struct snd_pcm *pcm,\n-\tint stream)\n-{\n-\tstruct snd_pcm_substream *substream = pcm->streams[stream].substream;\n-\tstruct snd_dma_buffer *buf = &substream->dma_buffer;\n-\tsize_t size = ATMEL_SSC_DMABUF_SIZE;\n-\n-\tbuf->dev.type = SNDRV_DMA_TYPE_DEV;\n-\tbuf->dev.dev = pcm->card->dev;\n-\tbuf->private_data = NULL;\n-\tbuf->area = dma_alloc_coherent(pcm->card->dev, size,\n-\t\t\t&buf->addr, GFP_KERNEL);\n-\tpr_debug(\"atmel-pcm: alloc dma buffer: area=%p, addr=%p, size=%zu\\n\",\n-\t\t\t(void *)buf->area, (void *)(long)buf->addr, size);\n-\n-\tif (!buf->area)\n-\t\treturn -ENOMEM;\n-\n-\tbuf->bytes = size;\n-\treturn 0;\n-}\n-\n-static int atmel_pcm_mmap(struct snd_soc_component *component,\n-\t\t\t  struct snd_pcm_substream *substream,\n-\t\t\t  struct vm_area_struct *vma)\n-{\n-\treturn remap_pfn_range(vma, vma->vm_start,\n-\t\t       substream->dma_buffer.addr >> PAGE_SHIFT,\n-\t\t       vma->vm_end - vma->vm_start, vma->vm_page_prot);\n-}\n-\n static int atmel_pcm_new(struct snd_soc_component *component,\n \t\t\t struct snd_soc_pcm_runtime *rtd)\n {\n \tstruct snd_card *card = rtd->card->snd_card;\n-\tstruct snd_pcm *pcm = rtd->pcm;\n \tint ret;\n \n \tret = dma_coerce_mask_and_coherent(card->dev, DMA_BIT_MASK(32));\n \tif (ret)\n \t\treturn ret;\n \n-\tif (pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream) {\n-\t\tpr_debug(\"atmel-pcm: allocating PCM playback DMA buffer\\n\");\n-\t\tret = atmel_pcm_preallocate_dma_buffer(pcm,\n-\t\t\tSNDRV_PCM_STREAM_PLAYBACK);\n-\t\tif (ret)\n-\t\t\tgoto out;\n-\t}\n+\tsnd_pcm_set_managed_buffer_all(rtd->pcm, SNDRV_DMA_TYPE_DEV,\n+\t\t\t\t       card->dev, ATMEL_SSC_DMABUF_SIZE,\n+\t\t\t\t       ATMEL_SSC_DMABUF_SIZE);\n \n-\tif (pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream) {\n-\t\tpr_debug(\"atmel-pcm: allocating PCM capture DMA buffer\\n\");\n-\t\tret = atmel_pcm_preallocate_dma_buffer(pcm,\n-\t\t\tSNDRV_PCM_STREAM_CAPTURE);\n-\t\tif (ret)\n-\t\t\tgoto out;\n-\t}\n- out:\n-\treturn ret;\n-}\n-\n-static void atmel_pcm_free(struct snd_soc_component *component,\n-\t\t\t   struct snd_pcm *pcm)\n-{\n-\tstruct snd_pcm_substream *substream;\n-\tstruct snd_dma_buffer *buf;\n-\tint stream;\n-\n-\tfor (stream = 0; stream < 2; stream++) {\n-\t\tsubstream = pcm->streams[stream].substream;\n-\t\tif (!substream)\n-\t\t\tcontinue;\n-\n-\t\tbuf = &substream->dma_buffer;\n-\t\tif (!buf->area)\n-\t\t\tcontinue;\n-\t\tdma_free_coherent(pcm->card->dev, buf->bytes,\n-\t\t\t\t  buf->area, buf->addr);\n-\t\tbuf->area = NULL;\n-\t}\n+\treturn 0;\n }\n \n /*--------------------------------------------------------------------------*\\\n@@ -210,9 +145,6 @@ static int atmel_pcm_hw_params(struct sn\n \t/* this may get called several times by oss emulation\n \t * with different params */\n \n-\tsnd_pcm_set_runtime_buffer(substream, &substream->dma_buffer);\n-\truntime->dma_bytes = params_buffer_bytes(params);\n-\n \tprtd->params = snd_soc_dai_get_dma_data(asoc_rtd_to_cpu(rtd, 0), substream);\n \tprtd->params->dma_intr_handler = atmel_pcm_dma_irq;\n \n@@ -384,9 +316,7 @@ static const struct snd_soc_component_dr\n \t.prepare\t= atmel_pcm_prepare,\n \t.trigger\t= atmel_pcm_trigger,\n \t.pointer\t= atmel_pcm_pointer,\n-\t.mmap\t\t= atmel_pcm_mmap,\n \t.pcm_construct\t= atmel_pcm_new,\n-\t.pcm_destruct\t= atmel_pcm_free,\n };\n \n int atmel_pcm_pdc_platform_register(struct device *dev)\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/145-power-reset-at91-sama5d2_shdwc-add-support-for-sama7.patch",
    "content": "From f39f2312a68ec0843adba08f9c9182ffa5624190 Mon Sep 17 00:00:00 2001\nFrom: Claudiu Beznea <claudiu.beznea@microchip.com>\nDate: Wed, 16 Dec 2020 14:57:33 +0200\nSubject: [PATCH 145/247] power: reset: at91-sama5d2_shdwc: add support for\n sama7g5\n\nAdd support for SAMA7G5 by adding proper struct reg_config structure\nand since SAMA7G5 is not currently on LPDDR setups the commit also\navoid the mapping of DDR controller.\n\nSigned-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>\nSigned-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>\n---\n drivers/power/reset/at91-sama5d2_shdwc.c | 72 ++++++++++++++++++------\n 1 file changed, 54 insertions(+), 18 deletions(-)\n\n--- a/drivers/power/reset/at91-sama5d2_shdwc.c\n+++ b/drivers/power/reset/at91-sama5d2_shdwc.c\n@@ -78,9 +78,15 @@ struct pmc_reg_config {\n \tu8 mckr;\n };\n \n+struct ddrc_reg_config {\n+\tu32 type_offset;\n+\tu32 type_mask;\n+};\n+\n struct reg_config {\n \tstruct shdwc_reg_config shdwc;\n \tstruct pmc_reg_config pmc;\n+\tstruct ddrc_reg_config ddrc;\n };\n \n struct shdwc {\n@@ -262,6 +268,10 @@ static const struct reg_config sama5d2_r\n \t.pmc = {\n \t\t.mckr\t\t= 0x30,\n \t},\n+\t.ddrc = {\n+\t\t.type_offset\t= AT91_DDRSDRC_MDR,\n+\t\t.type_mask\t= AT91_DDRSDRC_MD\n+\t},\n };\n \n static const struct reg_config sam9x60_reg_config = {\n@@ -275,6 +285,23 @@ static const struct reg_config sam9x60_r\n \t.pmc = {\n \t\t.mckr\t\t= 0x28,\n \t},\n+\t.ddrc = {\n+\t\t.type_offset\t= AT91_DDRSDRC_MDR,\n+\t\t.type_mask\t= AT91_DDRSDRC_MD\n+\t},\n+};\n+\n+static const struct reg_config sama7g5_reg_config = {\n+\t.shdwc = {\n+\t\t.wkup_pin_input = 0,\n+\t\t.mr_rtcwk_shift = 17,\n+\t\t.mr_rttwk_shift = 16,\n+\t\t.sr_rtcwk_shift = 5,\n+\t\t.sr_rttwk_shift = 4,\n+\t},\n+\t.pmc = {\n+\t\t.mckr\t\t= 0x28,\n+\t},\n };\n \n static const struct of_device_id at91_shdwc_of_match[] = {\n@@ -285,6 +312,10 @@ static const struct of_device_id at91_sh\n \t{\n \t\t.compatible = \"microchip,sam9x60-shdwc\",\n \t\t.data = &sam9x60_reg_config,\n+\t},\n+\t{\n+\t\t.compatible = \"microchip,sama7g5-shdwc\",\n+\t\t.data = &sama7g5_reg_config,\n \t}, {\n \t\t/*sentinel*/\n \t}\n@@ -294,6 +325,7 @@ MODULE_DEVICE_TABLE(of, at91_shdwc_of_ma\n static const struct of_device_id at91_pmc_ids[] = {\n \t{ .compatible = \"atmel,sama5d2-pmc\" },\n \t{ .compatible = \"microchip,sam9x60-pmc\" },\n+\t{ .compatible = \"microchip,sama7g5-pmc\" },\n \t{ /* Sentinel. */ }\n };\n \n@@ -355,30 +387,34 @@ static int __init at91_shdwc_probe(struc\n \t\tgoto clk_disable;\n \t}\n \n-\tnp = of_find_compatible_node(NULL, NULL, \"atmel,sama5d3-ddramc\");\n-\tif (!np) {\n-\t\tret = -ENODEV;\n-\t\tgoto unmap;\n-\t}\n+\tif (at91_shdwc->rcfg->ddrc.type_mask) {\n+\t\tnp = of_find_compatible_node(NULL, NULL,\n+\t\t\t\t\t     \"atmel,sama5d3-ddramc\");\n+\t\tif (!np) {\n+\t\t\tret = -ENODEV;\n+\t\t\tgoto unmap;\n+\t\t}\n \n-\tat91_shdwc->mpddrc_base = of_iomap(np, 0);\n-\tof_node_put(np);\n+\t\tat91_shdwc->mpddrc_base = of_iomap(np, 0);\n+\t\tof_node_put(np);\n \n-\tif (!at91_shdwc->mpddrc_base) {\n-\t\tret = -ENOMEM;\n-\t\tgoto unmap;\n+\t\tif (!at91_shdwc->mpddrc_base) {\n+\t\t\tret = -ENOMEM;\n+\t\t\tgoto unmap;\n+\t\t}\n+\n+\t\tddr_type = readl(at91_shdwc->mpddrc_base +\n+\t\t\t\t at91_shdwc->rcfg->ddrc.type_offset) &\n+\t\t\t\t at91_shdwc->rcfg->ddrc.type_mask;\n+\t\tif (ddr_type != AT91_DDRSDRC_MD_LPDDR2 &&\n+\t\t    ddr_type != AT91_DDRSDRC_MD_LPDDR3) {\n+\t\t\tiounmap(at91_shdwc->mpddrc_base);\n+\t\t\tat91_shdwc->mpddrc_base = NULL;\n+\t\t}\n \t}\n \n \tpm_power_off = at91_poweroff;\n \n-\tddr_type = readl(at91_shdwc->mpddrc_base + AT91_DDRSDRC_MDR) &\n-\t\t\t AT91_DDRSDRC_MD;\n-\tif (ddr_type != AT91_DDRSDRC_MD_LPDDR2 &&\n-\t    ddr_type != AT91_DDRSDRC_MD_LPDDR3) {\n-\t\tiounmap(at91_shdwc->mpddrc_base);\n-\t\tat91_shdwc->mpddrc_base = NULL;\n-\t}\n-\n \treturn 0;\n \n unmap:\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/146-pinctrl-at91-pio4-add-support-for-slew-rate.patch",
    "content": "From bd819c78346012ae0627b1cd4f6ceb1b51162c71 Mon Sep 17 00:00:00 2001\nFrom: Claudiu Beznea <claudiu.beznea@microchip.com>\nDate: Wed, 27 Jan 2021 13:45:44 +0200\nSubject: [PATCH 146/247] pinctrl: at91-pio4: add support for slew-rate\n\nSAMA7G5 supports slew rate configuration. Adapt the driver for this.\nFor output switching frequencies lower than 50MHz the slew rate needs to\nbe enabled. Since most of the pins on SAMA7G5 fall into this category\nenabled the slew rate by default.\n\nSigned-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>\nAcked-by: Ludovic Desroches <ludovic.desroches@microchip.com>\nLink: https://lore.kernel.org/r/1611747945-29960-3-git-send-email-claudiu.beznea@microchip.com\nSigned-off-by: Linus Walleij <linus.walleij@linaro.org>\n---\n drivers/pinctrl/pinctrl-at91-pio4.c | 27 +++++++++++++++++++++++++++\n 1 file changed, 27 insertions(+)\n\n--- a/drivers/pinctrl/pinctrl-at91-pio4.c\n+++ b/drivers/pinctrl/pinctrl-at91-pio4.c\n@@ -36,6 +36,7 @@\n #define\t\tATMEL_PIO_DIR_MASK\t\tBIT(8)\n #define\t\tATMEL_PIO_PUEN_MASK\t\tBIT(9)\n #define\t\tATMEL_PIO_PDEN_MASK\t\tBIT(10)\n+#define\t\tATMEL_PIO_SR_MASK\t\tBIT(11)\n #define\t\tATMEL_PIO_IFEN_MASK\t\tBIT(12)\n #define\t\tATMEL_PIO_IFSCEN_MASK\t\tBIT(13)\n #define\t\tATMEL_PIO_OPD_MASK\t\tBIT(14)\n@@ -76,10 +77,12 @@\n  * @nbanks: number of PIO banks\n  * @last_bank_count: number of lines in the last bank (can be less than\n  *\tthe rest of the banks).\n+ * @slew_rate_support: slew rate support\n  */\n struct atmel_pioctrl_data {\n \tunsigned nbanks;\n \tunsigned last_bank_count;\n+\tunsigned int slew_rate_support;\n };\n \n struct atmel_group {\n@@ -117,6 +120,7 @@ struct atmel_pin {\n  * @pm_suspend_backup: backup/restore register values on suspend/resume\n  * @dev: device entry for the Atmel PIO controller.\n  * @node: node of the Atmel PIO controller.\n+ * @slew_rate_support: slew rate support\n  */\n struct atmel_pioctrl {\n \tvoid __iomem\t\t*reg_base;\n@@ -138,6 +142,7 @@ struct atmel_pioctrl {\n \t} *pm_suspend_backup;\n \tstruct device\t\t*dev;\n \tstruct device_node\t*node;\n+\tunsigned int\t\tslew_rate_support;\n };\n \n static const char * const atmel_functions[] = {\n@@ -760,6 +765,13 @@ static int atmel_conf_pin_config_group_g\n \t\t\treturn -EINVAL;\n \t\targ = 1;\n \t\tbreak;\n+\tcase PIN_CONFIG_SLEW_RATE:\n+\t\tif (!atmel_pioctrl->slew_rate_support)\n+\t\t\treturn -EOPNOTSUPP;\n+\t\tif (!(res & ATMEL_PIO_SR_MASK))\n+\t\t\treturn -EINVAL;\n+\t\targ = 1;\n+\t\tbreak;\n \tcase ATMEL_PIN_CONFIG_DRIVE_STRENGTH:\n \t\tif (!(res & ATMEL_PIO_DRVSTR_MASK))\n \t\t\treturn -EINVAL;\n@@ -793,6 +805,10 @@ static int atmel_conf_pin_config_group_s\n \t\tdev_dbg(pctldev->dev, \"%s: pin=%u, config=0x%lx\\n\",\n \t\t\t__func__, pin_id, configs[i]);\n \n+\t\t/* Keep slew rate enabled by default. */\n+\t\tif (atmel_pioctrl->slew_rate_support)\n+\t\t\tconf |= ATMEL_PIO_SR_MASK;\n+\n \t\tswitch (param) {\n \t\tcase PIN_CONFIG_BIAS_DISABLE:\n \t\t\tconf &= (~ATMEL_PIO_PUEN_MASK);\n@@ -850,6 +866,13 @@ static int atmel_conf_pin_config_group_s\n \t\t\t\t\tATMEL_PIO_SODR);\n \t\t\t}\n \t\t\tbreak;\n+\t\tcase PIN_CONFIG_SLEW_RATE:\n+\t\t\tif (!atmel_pioctrl->slew_rate_support)\n+\t\t\t\tbreak;\n+\t\t\t/* And remove it if explicitly requested. */\n+\t\t\tif (arg == 0)\n+\t\t\t\tconf &= ~ATMEL_PIO_SR_MASK;\n+\t\t\tbreak;\n \t\tcase ATMEL_PIN_CONFIG_DRIVE_STRENGTH:\n \t\t\tswitch (arg) {\n \t\t\tcase ATMEL_PIO_DRVSTR_LO:\n@@ -901,6 +924,8 @@ static void atmel_conf_pin_config_dbg_sh\n \t\tseq_printf(s, \"%s \", \"open-drain\");\n \tif (conf & ATMEL_PIO_SCHMITT_MASK)\n \t\tseq_printf(s, \"%s \", \"schmitt\");\n+\tif (atmel_pioctrl->slew_rate_support && (conf & ATMEL_PIO_SR_MASK))\n+\t\tseq_printf(s, \"%s \", \"slew-rate\");\n \tif (conf & ATMEL_PIO_DRVSTR_MASK) {\n \t\tswitch ((conf & ATMEL_PIO_DRVSTR_MASK) >> ATMEL_PIO_DRVSTR_OFFSET) {\n \t\tcase ATMEL_PIO_DRVSTR_ME:\n@@ -994,6 +1019,7 @@ static const struct atmel_pioctrl_data a\n static const struct atmel_pioctrl_data microchip_sama7g5_pioctrl_data = {\n \t.nbanks\t\t\t= 5,\n \t.last_bank_count\t= 8, /* sama7g5 has only PE0 to PE7 */\n+\t.slew_rate_support\t= 1,\n };\n \n static const struct of_device_id atmel_pctrl_of_match[] = {\n@@ -1039,6 +1065,7 @@ static int atmel_pinctrl_probe(struct pl\n \t\tatmel_pioctrl->npins -= ATMEL_PIO_NPINS_PER_BANK;\n \t\tatmel_pioctrl->npins += atmel_pioctrl_data->last_bank_count;\n \t}\n+\tatmel_pioctrl->slew_rate_support = atmel_pioctrl_data->slew_rate_support;\n \n \tatmel_pioctrl->reg_base = devm_platform_ioremap_resource(pdev, 0);\n \tif (IS_ERR(atmel_pioctrl->reg_base))\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/147-pinctrl-at91-pio4-fix-Prefer-unsigned-int-to-bare-us.patch",
    "content": "From 99629d1ad7e4e03ac3324d36b703220555b65566 Mon Sep 17 00:00:00 2001\nFrom: Claudiu Beznea <claudiu.beznea@microchip.com>\nDate: Wed, 27 Jan 2021 13:45:45 +0200\nSubject: [PATCH 147/247] pinctrl: at91-pio4: fix \"Prefer 'unsigned int' to\n bare use of 'unsigned'\"\n\nFix \"Prefer 'unsigned int' to bare use of 'unsigned'\" checkpatch.pl\nwarning.\n\nSigned-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>\nAcked-by: Ludovic Desroches <ludovic.desroches@microchip.com>\nLink: https://lore.kernel.org/r/1611747945-29960-4-git-send-email-claudiu.beznea@microchip.com\nSigned-off-by: Linus Walleij <linus.walleij@linaro.org>\n---\n drivers/pinctrl/pinctrl-at91-pio4.c | 110 ++++++++++++++--------------\n 1 file changed, 57 insertions(+), 53 deletions(-)\n\n--- a/drivers/pinctrl/pinctrl-at91-pio4.c\n+++ b/drivers/pinctrl/pinctrl-at91-pio4.c\n@@ -80,8 +80,8 @@\n  * @slew_rate_support: slew rate support\n  */\n struct atmel_pioctrl_data {\n-\tunsigned nbanks;\n-\tunsigned last_bank_count;\n+\tunsigned int nbanks;\n+\tunsigned int last_bank_count;\n \tunsigned int slew_rate_support;\n };\n \n@@ -91,11 +91,11 @@ struct atmel_group {\n };\n \n struct atmel_pin {\n-\tunsigned pin_id;\n-\tunsigned mux;\n-\tunsigned ioset;\n-\tunsigned bank;\n-\tunsigned line;\n+\tunsigned int pin_id;\n+\tunsigned int mux;\n+\tunsigned int ioset;\n+\tunsigned int bank;\n+\tunsigned int line;\n \tconst char *device;\n };\n \n@@ -125,16 +125,16 @@ struct atmel_pin {\n struct atmel_pioctrl {\n \tvoid __iomem\t\t*reg_base;\n \tstruct clk\t\t*clk;\n-\tunsigned\t\tnbanks;\n+\tunsigned int\t\tnbanks;\n \tstruct pinctrl_dev\t*pinctrl_dev;\n \tstruct atmel_group\t*groups;\n \tconst char * const\t*group_names;\n \tstruct atmel_pin\t**pins;\n-\tunsigned\t\tnpins;\n+\tunsigned int\t\tnpins;\n \tstruct gpio_chip\t*gpio_chip;\n \tstruct irq_domain\t*irq_domain;\n \tint\t\t\t*irqs;\n-\tunsigned\t\t*pm_wakeup_sources;\n+\tunsigned int\t\t*pm_wakeup_sources;\n \tstruct {\n \t\tu32\t\timr;\n \t\tu32\t\todsr;\n@@ -177,11 +177,11 @@ static void atmel_gpio_irq_ack(struct ir\n \t */\n }\n \n-static int atmel_gpio_irq_set_type(struct irq_data *d, unsigned type)\n+static int atmel_gpio_irq_set_type(struct irq_data *d, unsigned int type)\n {\n \tstruct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d);\n \tstruct atmel_pin *pin = atmel_pioctrl->pins[d->hwirq];\n-\tunsigned reg;\n+\tunsigned int reg;\n \n \tatmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR,\n \t\t\t BIT(pin->line));\n@@ -268,7 +268,7 @@ static struct irq_chip atmel_gpio_irq_ch\n \t.irq_set_wake\t= atmel_gpio_irq_set_wake,\n };\n \n-static int atmel_gpio_to_irq(struct gpio_chip *chip, unsigned offset)\n+static int atmel_gpio_to_irq(struct gpio_chip *chip, unsigned int offset)\n {\n \tstruct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);\n \n@@ -316,11 +316,12 @@ static void atmel_gpio_irq_handler(struc\n \tchained_irq_exit(chip, desc);\n }\n \n-static int atmel_gpio_direction_input(struct gpio_chip *chip, unsigned offset)\n+static int atmel_gpio_direction_input(struct gpio_chip *chip,\n+\t\t\t\t      unsigned int offset)\n {\n \tstruct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);\n \tstruct atmel_pin *pin = atmel_pioctrl->pins[offset];\n-\tunsigned reg;\n+\tunsigned int reg;\n \n \tatmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR,\n \t\t\t BIT(pin->line));\n@@ -331,11 +332,11 @@ static int atmel_gpio_direction_input(st\n \treturn 0;\n }\n \n-static int atmel_gpio_get(struct gpio_chip *chip, unsigned offset)\n+static int atmel_gpio_get(struct gpio_chip *chip, unsigned int offset)\n {\n \tstruct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);\n \tstruct atmel_pin *pin = atmel_pioctrl->pins[offset];\n-\tunsigned reg;\n+\tunsigned int reg;\n \n \treg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_PDSR);\n \n@@ -369,12 +370,13 @@ static int atmel_gpio_get_multiple(struc\n \treturn 0;\n }\n \n-static int atmel_gpio_direction_output(struct gpio_chip *chip, unsigned offset,\n+static int atmel_gpio_direction_output(struct gpio_chip *chip,\n+\t\t\t\t       unsigned int offset,\n \t\t\t\t       int value)\n {\n \tstruct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);\n \tstruct atmel_pin *pin = atmel_pioctrl->pins[offset];\n-\tunsigned reg;\n+\tunsigned int reg;\n \n \tatmel_gpio_write(atmel_pioctrl, pin->bank,\n \t\t\t value ? ATMEL_PIO_SODR : ATMEL_PIO_CODR,\n@@ -389,7 +391,7 @@ static int atmel_gpio_direction_output(s\n \treturn 0;\n }\n \n-static void atmel_gpio_set(struct gpio_chip *chip, unsigned offset, int val)\n+static void atmel_gpio_set(struct gpio_chip *chip, unsigned int offset, int val)\n {\n \tstruct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);\n \tstruct atmel_pin *pin = atmel_pioctrl->pins[offset];\n@@ -445,11 +447,11 @@ static struct gpio_chip atmel_gpio_chip\n \n /* --- PINCTRL --- */\n static unsigned int atmel_pin_config_read(struct pinctrl_dev *pctldev,\n-\t\t\t\t\t  unsigned pin_id)\n+\t\t\t\t\t  unsigned int pin_id)\n {\n \tstruct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);\n-\tunsigned bank = atmel_pioctrl->pins[pin_id]->bank;\n-\tunsigned line = atmel_pioctrl->pins[pin_id]->line;\n+\tunsigned int bank = atmel_pioctrl->pins[pin_id]->bank;\n+\tunsigned int line = atmel_pioctrl->pins[pin_id]->line;\n \tvoid __iomem *addr = atmel_pioctrl->reg_base\n \t\t\t     + bank * ATMEL_PIO_BANK_OFFSET;\n \n@@ -461,11 +463,11 @@ static unsigned int atmel_pin_config_rea\n }\n \n static void atmel_pin_config_write(struct pinctrl_dev *pctldev,\n-\t\t\t\t   unsigned pin_id, u32 conf)\n+\t\t\t\t   unsigned int pin_id, u32 conf)\n {\n \tstruct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);\n-\tunsigned bank = atmel_pioctrl->pins[pin_id]->bank;\n-\tunsigned line = atmel_pioctrl->pins[pin_id]->line;\n+\tunsigned int bank = atmel_pioctrl->pins[pin_id]->bank;\n+\tunsigned int line = atmel_pioctrl->pins[pin_id]->line;\n \tvoid __iomem *addr = atmel_pioctrl->reg_base\n \t\t\t     + bank * ATMEL_PIO_BANK_OFFSET;\n \n@@ -483,7 +485,7 @@ static int atmel_pctl_get_groups_count(s\n }\n \n static const char *atmel_pctl_get_group_name(struct pinctrl_dev *pctldev,\n-\t\t\t\t\t     unsigned selector)\n+\t\t\t\t\t     unsigned int selector)\n {\n \tstruct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);\n \n@@ -491,19 +493,20 @@ static const char *atmel_pctl_get_group_\n }\n \n static int atmel_pctl_get_group_pins(struct pinctrl_dev *pctldev,\n-\t\t\t\t     unsigned selector, const unsigned **pins,\n-\t\t\t\t     unsigned *num_pins)\n+\t\t\t\t     unsigned int selector,\n+\t\t\t\t     const unsigned int **pins,\n+\t\t\t\t     unsigned int *num_pins)\n {\n \tstruct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);\n \n-\t*pins = (unsigned *)&atmel_pioctrl->groups[selector].pin;\n+\t*pins = (unsigned int *)&atmel_pioctrl->groups[selector].pin;\n \t*num_pins = 1;\n \n \treturn 0;\n }\n \n static struct atmel_group *\n-atmel_pctl_find_group_by_pin(struct pinctrl_dev *pctldev, unsigned pin)\n+atmel_pctl_find_group_by_pin(struct pinctrl_dev *pctldev, unsigned int pin)\n {\n \tstruct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);\n \tint i;\n@@ -524,7 +527,7 @@ static int atmel_pctl_xlate_pinfunc(stru\n \t\t\t\t    const char **func_name)\n {\n \tstruct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);\n-\tunsigned pin_id, func_id;\n+\tunsigned int pin_id, func_id;\n \tstruct atmel_group *grp;\n \n \tpin_id = ATMEL_GET_PIN_NO(pinfunc);\n@@ -554,10 +557,10 @@ static int atmel_pctl_xlate_pinfunc(stru\n static int atmel_pctl_dt_subnode_to_map(struct pinctrl_dev *pctldev,\n \t\t\t\t\tstruct device_node *np,\n \t\t\t\t\tstruct pinctrl_map **map,\n-\t\t\t\t\tunsigned *reserved_maps,\n-\t\t\t\t\tunsigned *num_maps)\n+\t\t\t\t\tunsigned int *reserved_maps,\n+\t\t\t\t\tunsigned int *num_maps)\n {\n-\tunsigned num_pins, num_configs, reserve;\n+\tunsigned int num_pins, num_configs, reserve;\n \tunsigned long *configs;\n \tstruct property\t*pins;\n \tu32 pinfunc;\n@@ -628,10 +631,10 @@ exit:\n static int atmel_pctl_dt_node_to_map(struct pinctrl_dev *pctldev,\n \t\t\t\t     struct device_node *np_config,\n \t\t\t\t     struct pinctrl_map **map,\n-\t\t\t\t     unsigned *num_maps)\n+\t\t\t\t     unsigned int *num_maps)\n {\n \tstruct device_node *np;\n-\tunsigned reserved_maps;\n+\tunsigned int reserved_maps;\n \tint ret;\n \n \t*map = NULL;\n@@ -679,13 +682,13 @@ static int atmel_pmx_get_functions_count\n }\n \n static const char *atmel_pmx_get_function_name(struct pinctrl_dev *pctldev,\n-\t\t\t\t\t       unsigned selector)\n+\t\t\t\t\t       unsigned int selector)\n {\n \treturn atmel_functions[selector];\n }\n \n static int atmel_pmx_get_function_groups(struct pinctrl_dev *pctldev,\n-\t\t\t\t\t unsigned selector,\n+\t\t\t\t\t unsigned int selector,\n \t\t\t\t\t const char * const **groups,\n \t\t\t\t\t unsigned * const num_groups)\n {\n@@ -698,11 +701,11 @@ static int atmel_pmx_get_function_groups\n }\n \n static int atmel_pmx_set_mux(struct pinctrl_dev *pctldev,\n-\t\t\t     unsigned function,\n-\t\t\t     unsigned group)\n+\t\t\t     unsigned int function,\n+\t\t\t     unsigned int group)\n {\n \tstruct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);\n-\tunsigned pin;\n+\tunsigned int pin;\n \tu32 conf;\n \n \tdev_dbg(pctldev->dev, \"enable function %s group %s\\n\",\n@@ -726,13 +729,13 @@ static const struct pinmux_ops atmel_pmx\n };\n \n static int atmel_conf_pin_config_group_get(struct pinctrl_dev *pctldev,\n-\t\t\t\t\t   unsigned group,\n+\t\t\t\t\t   unsigned int group,\n \t\t\t\t\t   unsigned long *config)\n {\n \tstruct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);\n-\tunsigned param = pinconf_to_config_param(*config), arg = 0;\n+\tunsigned int param = pinconf_to_config_param(*config), arg = 0;\n \tstruct atmel_group *grp = atmel_pioctrl->groups + group;\n-\tunsigned pin_id = grp->pin;\n+\tunsigned int pin_id = grp->pin;\n \tu32 res;\n \n \tres = atmel_pin_config_read(pctldev, pin_id);\n@@ -786,21 +789,21 @@ static int atmel_conf_pin_config_group_g\n }\n \n static int atmel_conf_pin_config_group_set(struct pinctrl_dev *pctldev,\n-\t\t\t\t\t   unsigned group,\n+\t\t\t\t\t   unsigned int group,\n \t\t\t\t\t   unsigned long *configs,\n-\t\t\t\t\t   unsigned num_configs)\n+\t\t\t\t\t   unsigned int num_configs)\n {\n \tstruct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);\n \tstruct atmel_group *grp = atmel_pioctrl->groups + group;\n-\tunsigned bank, pin, pin_id = grp->pin;\n+\tunsigned int bank, pin, pin_id = grp->pin;\n \tu32 mask, conf = 0;\n \tint i;\n \n \tconf = atmel_pin_config_read(pctldev, pin_id);\n \n \tfor (i = 0; i < num_configs; i++) {\n-\t\tunsigned param = pinconf_to_config_param(configs[i]);\n-\t\tunsigned arg = pinconf_to_config_argument(configs[i]);\n+\t\tunsigned int param = pinconf_to_config_param(configs[i]);\n+\t\tunsigned int arg = pinconf_to_config_argument(configs[i]);\n \n \t\tdev_dbg(pctldev->dev, \"%s: pin=%u, config=0x%lx\\n\",\n \t\t\t__func__, pin_id, configs[i]);\n@@ -900,7 +903,8 @@ static int atmel_conf_pin_config_group_s\n }\n \n static void atmel_conf_pin_config_dbg_show(struct pinctrl_dev *pctldev,\n-\t\t\t\t\t   struct seq_file *s, unsigned pin_id)\n+\t\t\t\t\t   struct seq_file *s,\n+\t\t\t\t\t   unsigned int pin_id)\n {\n \tstruct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);\n \tu32 conf;\n@@ -1108,8 +1112,8 @@ static int atmel_pinctrl_probe(struct pl\n \t\treturn -ENOMEM;\n \tfor (i = 0 ; i < atmel_pioctrl->npins; i++) {\n \t\tstruct atmel_group *group = atmel_pioctrl->groups + i;\n-\t\tunsigned bank = ATMEL_PIO_BANK(i);\n-\t\tunsigned line = ATMEL_PIO_LINE(i);\n+\t\tunsigned int bank = ATMEL_PIO_BANK(i);\n+\t\tunsigned int line = ATMEL_PIO_LINE(i);\n \n \t\tatmel_pioctrl->pins[i] = devm_kzalloc(dev,\n \t\t\t\tsizeof(**atmel_pioctrl->pins), GFP_KERNEL);\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/148-net-macb-Add-default-usrio-config-to-default-gem-con.patch",
    "content": "From 096f58e564aed56936ef6de42a44c3101e9b8ed1 Mon Sep 17 00:00:00 2001\nFrom: Atish Patra <atish.patra@wdc.com>\nDate: Wed, 3 Mar 2021 11:55:49 -0800\nSubject: [PATCH 148/247] net: macb: Add default usrio config to default gem\n config\n\nThere is no usrio config defined for default gem config leading to\na kernel panic devices that don't define a data. This issue can be\nreprdouced with microchip polar fire soc where compatible string\nis defined as \"cdns,macb\".\n\nFixes: edac63861db7 (\"add userio bits as platform configuration\")\n\nSigned-off-by: Atish Patra <atish.patra@wdc.com>\nAcked-by: Nicolas Ferre <nicolas.ferre@microchip.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/ethernet/cadence/macb_main.c | 15 ++++++++-------\n 1 file changed, 8 insertions(+), 7 deletions(-)\n\n--- a/drivers/net/ethernet/cadence/macb_main.c\n+++ b/drivers/net/ethernet/cadence/macb_main.c\n@@ -3868,6 +3868,13 @@ static int macb_init(struct platform_dev\n \treturn 0;\n }\n \n+static const struct macb_usrio_config macb_default_usrio = {\n+\t.mii = MACB_BIT(MII),\n+\t.rmii = MACB_BIT(RMII),\n+\t.rgmii = GEM_BIT(RGMII),\n+\t.refclk = MACB_BIT(CLKEN),\n+};\n+\n #if defined(CONFIG_OF)\n /* 1518 rounded up */\n #define AT91ETHER_MAX_RBUFF_SZ\t0x600\n@@ -4383,13 +4390,6 @@ static int fu540_c000_init(struct platfo\n \treturn macb_init(pdev);\n }\n \n-static const struct macb_usrio_config macb_default_usrio = {\n-\t.mii = MACB_BIT(MII),\n-\t.rmii = MACB_BIT(RMII),\n-\t.rgmii = GEM_BIT(RGMII),\n-\t.refclk = MACB_BIT(CLKEN),\n-};\n-\n static const struct macb_usrio_config sama7g5_usrio = {\n \t.mii = 0,\n \t.rmii = 1,\n@@ -4538,6 +4538,7 @@ static const struct macb_config default_\n \t.dma_burst_length = 16,\n \t.clk_init = macb_clk_init,\n \t.init = macb_init,\n+\t.usrio = &macb_default_usrio,\n \t.jumbo_max_len = 10240,\n };\n \n"
  },
  {
    "path": "target/linux/at91/patches-5.10/149-ARM-at91-pm-Move-prototypes-to-mutually-included-hea.patch",
    "content": "From 746aba88c64e409cbc3757a5f81fad5b5c74bbcc Mon Sep 17 00:00:00 2001\nFrom: Lee Jones <lee.jones@linaro.org>\nDate: Wed, 3 Mar 2021 12:41:49 +0000\nSubject: [PATCH 149/247] ARM: at91: pm: Move prototypes to mutually included\n header\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nBoth the caller and the supplier's source file should have access to\nthe include file containing the prototypes.\n\nFixes the following W=1 kernel build warning(s):\n\n drivers/pinctrl/pinctrl-at91.c:1637:6: warning: no previous prototype for ‘at91_pinctrl_gpio_suspend’ [-Wmissing-prototypes]\n 1637 | void at91_pinctrl_gpio_suspend(void)\n | ^~~~~~~~~~~~~~~~~~~~~~~~~\n drivers/pinctrl/pinctrl-at91.c:1661:6: warning: no previous prototype for ‘at91_pinctrl_gpio_resume’ [-Wmissing-prototypes]\n 1661 | void at91_pinctrl_gpio_resume(void)\n | ^~~~~~~~~~~~~~~~~~~~~~~~\n\nCc: Russell King <linux@armlinux.org.uk>\nCc: Nicolas Ferre <nicolas.ferre@microchip.com>\nCc: Alexandre Belloni <alexandre.belloni@bootlin.com>\nCc: Ludovic Desroches <ludovic.desroches@microchip.com>\nSigned-off-by: Lee Jones <lee.jones@linaro.org>\nAcked-by: Linus Walleij <linus.walleij@linaro.org>\nSigned-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>\nLink: https://lore.kernel.org/r/20210303124149.3149511-1-lee.jones@linaro.org\n---\n arch/arm/mach-at91/pm.c        | 19 ++++++++-----------\n drivers/pinctrl/pinctrl-at91.c |  2 ++\n include/soc/at91/pm.h          | 16 ++++++++++++++++\n 3 files changed, 26 insertions(+), 11 deletions(-)\n create mode 100644 include/soc/at91/pm.h\n\n--- a/arch/arm/mach-at91/pm.c\n+++ b/arch/arm/mach-at91/pm.c\n@@ -17,6 +17,8 @@\n #include <linux/clk/at91_pmc.h>\n #include <linux/platform_data/atmel.h>\n \n+#include <soc/at91/pm.h>\n+\n #include <asm/cacheflush.h>\n #include <asm/fncpy.h>\n #include <asm/system_misc.h>\n@@ -25,17 +27,6 @@\n #include \"generic.h\"\n #include \"pm.h\"\n \n-/*\n- * FIXME: this is needed to communicate between the pinctrl driver and\n- * the PM implementation in the machine. Possibly part of the PM\n- * implementation should be moved down into the pinctrl driver and get\n- * called as part of the generic suspend/resume path.\n- */\n-#ifdef CONFIG_PINCTRL_AT91\n-extern void at91_pinctrl_gpio_suspend(void);\n-extern void at91_pinctrl_gpio_resume(void);\n-#endif\n-\n struct at91_soc_pm {\n \tint (*config_shdwc_ws)(void __iomem *shdwc, u32 *mode, u32 *polarity);\n \tint (*config_pmc_ws)(void __iomem *pmc, u32 mode, u32 polarity);\n@@ -326,6 +317,12 @@ static void at91_pm_suspend(suspend_stat\n static int at91_pm_enter(suspend_state_t state)\n {\n #ifdef CONFIG_PINCTRL_AT91\n+\t/*\n+\t * FIXME: this is needed to communicate between the pinctrl driver and\n+\t * the PM implementation in the machine. Possibly part of the PM\n+\t * implementation should be moved down into the pinctrl driver and get\n+\t * called as part of the generic suspend/resume path.\n+\t */\n \tat91_pinctrl_gpio_suspend();\n #endif\n \n--- a/drivers/pinctrl/pinctrl-at91.c\n+++ b/drivers/pinctrl/pinctrl-at91.c\n@@ -23,6 +23,8 @@\n /* Since we request GPIOs from ourself */\n #include <linux/pinctrl/consumer.h>\n \n+#include <soc/at91/pm.h>\n+\n #include \"pinctrl-at91.h\"\n #include \"core.h\"\n \n--- /dev/null\n+++ b/include/soc/at91/pm.h\n@@ -0,0 +1,16 @@\n+/* SPDX-License-Identifier: GPL-2.0-only */\n+/*\n+ * Atmel Power Management\n+ *\n+ * Copyright (C) 2020 Atmel\n+ *\n+ * Author: Lee Jones <lee.jones@linaro.org>\n+ */\n+\n+#ifndef __SOC_ATMEL_PM_H\n+#define __SOC_ATMEL_PM_H\n+\n+void at91_pinctrl_gpio_suspend(void);\n+void at91_pinctrl_gpio_resume(void);\n+\n+#endif /* __SOC_ATMEL_PM_H */\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/150-ASoC-mchp-i2s-mcc-Add-compatible-for-SAMA7G5.patch",
    "content": "From d6493e6f1c42f7ad350ea25e11f0e71fc32e6116 Mon Sep 17 00:00:00 2001\nFrom: Codrin Ciubotariu <codrin.ciubotariu@microchip.com>\nDate: Mon, 1 Mar 2021 19:09:00 +0200\nSubject: [PATCH 150/247] ASoC: mchp-i2s-mcc: Add compatible for SAMA7G5\n\nMicrochip's new SAMA7G5 includes an updated I2S-MCC compatible with the\nprevious version found on SAM9X60. The new controller includes 8 (4 * 2)\ninput and output data pins for up to 8 channels for I2S and Left-Justified\nformats.\n\nSigned-off-by: Codrin Ciubotariu <codrin.ciubotariu@microchip.com>\nLink: https://lore.kernel.org/r/20210301170905.835091-3-codrin.ciubotariu@microchip.com\nSigned-off-by: Mark Brown <broonie@kernel.org>\n---\n sound/soc/atmel/Kconfig        | 3 +++\n sound/soc/atmel/mchp-i2s-mcc.c | 3 +++\n 2 files changed, 6 insertions(+)\n\n--- a/sound/soc/atmel/Kconfig\n+++ b/sound/soc/atmel/Kconfig\n@@ -126,10 +126,13 @@ config SND_MCHP_SOC_I2S_MCC\n \t  Say Y or M if you want to add support for I2S Multi-Channel ASoC\n \t  driver on the following Microchip platforms:\n \t  - sam9x60\n+\t  - sama7g5\n \n \t  The I2SMCC complies with the Inter-IC Sound (I2S) bus specification\n \t  and supports a Time Division Multiplexed (TDM) interface with\n \t  external multi-channel audio codecs.\n+\t  Starting with sama7g5, I2S and Left-Justified multi-channel is\n+\t  supported by using multiple data pins, output and input, without TDM.\n \n config SND_MCHP_SOC_SPDIFTX\n \ttristate \"Microchip ASoC driver for boards using S/PDIF TX\"\n--- a/sound/soc/atmel/mchp-i2s-mcc.c\n+++ b/sound/soc/atmel/mchp-i2s-mcc.c\n@@ -873,6 +873,9 @@ static const struct of_device_id mchp_i2\n \t{\n \t\t.compatible = \"microchip,sam9x60-i2smcc\",\n \t},\n+\t{\n+\t\t.compatible = \"microchip,sama7g5-i2smcc\",\n+\t},\n \t{ /* sentinel */ }\n };\n MODULE_DEVICE_TABLE(of, mchp_i2s_mcc_dt_ids);\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/151-ASoC-mchp-i2s-mcc-Add-multi-channel-support-for-I2S-.patch",
    "content": "From 5bef4e8125d09443b5486971d5550ed285cde4b1 Mon Sep 17 00:00:00 2001\nFrom: Codrin Ciubotariu <codrin.ciubotariu@microchip.com>\nDate: Mon, 1 Mar 2021 19:09:01 +0200\nSubject: [PATCH 151/247] ASoC: mchp-i2s-mcc: Add multi-channel support for I2S\n and LEFT_J formats\n\nThe latest I2S-MCC available in SAMA7G5 supports multi-channel for I2S and\nLeft-Justified formats. For this, the new version uses 8 (4 * 2) input and\noutput pins, with each pin being responsible for 2 channels. This sums up\nto a total of 8 channels for synchronous capture and playback.\n\nSigned-off-by: Codrin Ciubotariu <codrin.ciubotariu@microchip.com>\nLink: https://lore.kernel.org/r/20210301170905.835091-4-codrin.ciubotariu@microchip.com\nSigned-off-by: Mark Brown <broonie@kernel.org>\n---\n sound/soc/atmel/mchp-i2s-mcc.c | 38 ++++++++++++++++++++++++++++++++++\n 1 file changed, 38 insertions(+)\n\n--- a/sound/soc/atmel/mchp-i2s-mcc.c\n+++ b/sound/soc/atmel/mchp-i2s-mcc.c\n@@ -16,6 +16,7 @@\n #include <linux/clk.h>\n #include <linux/mfd/syscon.h>\n #include <linux/lcm.h>\n+#include <linux/of_device.h>\n \n #include <sound/core.h>\n #include <sound/pcm.h>\n@@ -225,6 +226,10 @@ static const struct regmap_config mchp_i\n \t.max_register = MCHP_I2SMCC_VERSION,\n };\n \n+struct mchp_i2s_mcc_soc_data {\n+\tunsigned int\tdata_pin_pair_num;\n+};\n+\n struct mchp_i2s_mcc_dev {\n \tstruct wait_queue_head\t\t\twq_txrdy;\n \tstruct wait_queue_head\t\t\twq_rxrdy;\n@@ -232,6 +237,7 @@ struct mchp_i2s_mcc_dev {\n \tstruct regmap\t\t\t\t*regmap;\n \tstruct clk\t\t\t\t*pclk;\n \tstruct clk\t\t\t\t*gclk;\n+\tconst struct mchp_i2s_mcc_soc_data\t*soc;\n \tstruct snd_dmaengine_dai_dma_data\tplayback;\n \tstruct snd_dmaengine_dai_dma_data\tcapture;\n \tunsigned int\t\t\t\tfmt;\n@@ -549,6 +555,17 @@ static int mchp_i2s_mcc_hw_params(struct\n \t}\n \n \tif (dev->fmt & (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_LEFT_J)) {\n+\t\t/* for I2S and LEFT_J one pin is needed for every 2 channels */\n+\t\tif (channels > dev->soc->data_pin_pair_num * 2) {\n+\t\t\tdev_err(dev->dev,\n+\t\t\t\t\"unsupported number of audio channels: %d\\n\",\n+\t\t\t\tchannels);\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\n+\t\t/* enable for interleaved format */\n+\t\tmrb |= MCHP_I2SMCC_MRB_CRAMODE_REGULAR;\n+\n \t\tswitch (channels) {\n \t\tcase 1:\n \t\t\tif (is_playback)\n@@ -558,6 +575,12 @@ static int mchp_i2s_mcc_hw_params(struct\n \t\t\tbreak;\n \t\tcase 2:\n \t\t\tbreak;\n+\t\tcase 4:\n+\t\t\tmra |= MCHP_I2SMCC_MRA_WIRECFG_I2S_2_TDM_1;\n+\t\t\tbreak;\n+\t\tcase 8:\n+\t\t\tmra |= MCHP_I2SMCC_MRA_WIRECFG_I2S_4_TDM_2;\n+\t\t\tbreak;\n \t\tdefault:\n \t\t\tdev_err(dev->dev, \"unsupported number of audio channels\\n\");\n \t\t\treturn -EINVAL;\n@@ -869,12 +892,22 @@ static const struct snd_soc_component_dr\n };\n \n #ifdef CONFIG_OF\n+static struct mchp_i2s_mcc_soc_data mchp_i2s_mcc_sam9x60 = {\n+\t.data_pin_pair_num = 1,\n+};\n+\n+static struct mchp_i2s_mcc_soc_data mchp_i2s_mcc_sama7g5 = {\n+\t.data_pin_pair_num = 4,\n+};\n+\n static const struct of_device_id mchp_i2s_mcc_dt_ids[] = {\n \t{\n \t\t.compatible = \"microchip,sam9x60-i2smcc\",\n+\t\t.data = &mchp_i2s_mcc_sam9x60,\n \t},\n \t{\n \t\t.compatible = \"microchip,sama7g5-i2smcc\",\n+\t\t.data = &mchp_i2s_mcc_sama7g5,\n \t},\n \t{ /* sentinel */ }\n };\n@@ -932,6 +965,11 @@ static int mchp_i2s_mcc_probe(struct pla\n \t\tdev->gclk = NULL;\n \t}\n \n+\tdev->soc = of_device_get_match_data(&pdev->dev);\n+\tif (!dev->soc) {\n+\t\tdev_err(&pdev->dev, \"failed to get soc data\\n\");\n+\t\treturn -ENODEV;\n+\t}\n \tdev->dev = &pdev->dev;\n \tdev->regmap = regmap;\n \tplatform_set_drvdata(pdev, dev);\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/152-ASoC-mchp-i2s-mcc-Add-support-to-select-TDM-pins.patch",
    "content": "From 2bbdc5b38603384996271a8817b0578a2360af2f Mon Sep 17 00:00:00 2001\nFrom: Codrin Ciubotariu <codrin.ciubotariu@microchip.com>\nDate: Mon, 1 Mar 2021 19:09:03 +0200\nSubject: [PATCH 152/247] ASoC: mchp-i2s-mcc: Add support to select TDM pins\n\nSAMA7G5's I2S-MCC has 4 pairs of DIN/DOUT pins. Since TDM only uses a\nsingle pair of pins for synchronous capture and playback, the controller\nneeds to be told which of the pair is connected. This can be mentioned\nusing the \"microchip,tdm-data-pair\" property from DT. The property is\noptional, useful only if TDM is used. If it's missing, DIN/DOUT 0 pins\nwill be used by default.\n\nSigned-off-by: Codrin Ciubotariu <codrin.ciubotariu@microchip.com>\nLink: https://lore.kernel.org/r/20210301170905.835091-6-codrin.ciubotariu@microchip.com\nSigned-off-by: Mark Brown <broonie@kernel.org>\n---\n sound/soc/atmel/mchp-i2s-mcc.c | 52 +++++++++++++++++++++++++++++++---\n 1 file changed, 48 insertions(+), 4 deletions(-)\n\n--- a/sound/soc/atmel/mchp-i2s-mcc.c\n+++ b/sound/soc/atmel/mchp-i2s-mcc.c\n@@ -100,6 +100,8 @@\n #define MCHP_I2SMCC_MRA_DATALENGTH_8_BITS_COMPACT\t(7 << 1)\n \n #define MCHP_I2SMCC_MRA_WIRECFG_MASK\t\tGENMASK(5, 4)\n+#define MCHP_I2SMCC_MRA_WIRECFG_TDM(pin)\t(((pin) << 4) & \\\n+\t\t\t\t\t\t MCHP_I2SMCC_MRA_WIRECFG_MASK)\n #define MCHP_I2SMCC_MRA_WIRECFG_I2S_1_TDM_0\t(0 << 4)\n #define MCHP_I2SMCC_MRA_WIRECFG_I2S_2_TDM_1\t(1 << 4)\n #define MCHP_I2SMCC_MRA_WIRECFG_I2S_4_TDM_2\t(2 << 4)\n@@ -245,6 +247,7 @@ struct mchp_i2s_mcc_dev {\n \tunsigned int\t\t\t\tframe_length;\n \tint\t\t\t\t\ttdm_slots;\n \tint\t\t\t\t\tchannels;\n+\tu8\t\t\t\t\ttdm_data_pair;\n \tunsigned int\t\t\t\tgclk_use:1;\n \tunsigned int\t\t\t\tgclk_running:1;\n \tunsigned int\t\t\t\ttx_rdy:1;\n@@ -589,6 +592,8 @@ static int mchp_i2s_mcc_hw_params(struct\n \t\tif (!frame_length)\n \t\t\tframe_length = 2 * params_physical_width(params);\n \t} else if (dev->fmt & SND_SOC_DAIFMT_DSP_A) {\n+\t\tmra |= MCHP_I2SMCC_MRA_WIRECFG_TDM(dev->tdm_data_pair);\n+\n \t\tif (dev->tdm_slots) {\n \t\t\tif (channels % 2 && channels * 2 <= dev->tdm_slots) {\n \t\t\t\t/*\n@@ -914,6 +919,45 @@ static const struct of_device_id mchp_i2\n MODULE_DEVICE_TABLE(of, mchp_i2s_mcc_dt_ids);\n #endif\n \n+static int mchp_i2s_mcc_soc_data_parse(struct platform_device *pdev,\n+\t\t\t\t       struct mchp_i2s_mcc_dev *dev)\n+{\n+\tint err;\n+\n+\tif (!dev->soc) {\n+\t\tdev_err(&pdev->dev, \"failed to get soc data\\n\");\n+\t\treturn -ENODEV;\n+\t}\n+\n+\tif (dev->soc->data_pin_pair_num == 1)\n+\t\treturn 0;\n+\n+\terr = of_property_read_u8(pdev->dev.of_node, \"microchip,tdm-data-pair\",\n+\t\t\t\t  &dev->tdm_data_pair);\n+\tif (err < 0 && err != -EINVAL) {\n+\t\tdev_err(&pdev->dev,\n+\t\t\t\"bad property data for 'microchip,tdm-data-pair': %d\",\n+\t\t\terr);\n+\t\treturn err;\n+\t}\n+\tif (err == -EINVAL) {\n+\t\tdev_info(&pdev->dev,\n+\t\t\t \"'microchip,tdm-data-pair' not found; assuming DIN/DOUT 0 for TDM\\n\");\n+\t\tdev->tdm_data_pair = 0;\n+\t} else {\n+\t\tif (dev->tdm_data_pair > dev->soc->data_pin_pair_num - 1) {\n+\t\t\tdev_err(&pdev->dev,\n+\t\t\t\t\"invalid value for 'microchip,tdm-data-pair': %d\\n\",\n+\t\t\t\tdev->tdm_data_pair);\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t\tdev_dbg(&pdev->dev, \"TMD format on DIN/DOUT %d pins\\n\",\n+\t\t\tdev->tdm_data_pair);\n+\t}\n+\n+\treturn 0;\n+}\n+\n static int mchp_i2s_mcc_probe(struct platform_device *pdev)\n {\n \tstruct mchp_i2s_mcc_dev *dev;\n@@ -966,10 +1010,10 @@ static int mchp_i2s_mcc_probe(struct pla\n \t}\n \n \tdev->soc = of_device_get_match_data(&pdev->dev);\n-\tif (!dev->soc) {\n-\t\tdev_err(&pdev->dev, \"failed to get soc data\\n\");\n-\t\treturn -ENODEV;\n-\t}\n+\terr = mchp_i2s_mcc_soc_data_parse(pdev, dev);\n+\tif (err < 0)\n+\t\treturn err;\n+\n \tdev->dev = &pdev->dev;\n \tdev->regmap = regmap;\n \tplatform_set_drvdata(pdev, dev);\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/153-ASoC-mchp-i2s-mcc-Add-FIFOs-support.patch",
    "content": "From 36bb4f0ab8e7ef69cc11d4d888aa898223b0e901 Mon Sep 17 00:00:00 2001\nFrom: Codrin Ciubotariu <codrin.ciubotariu@microchip.com>\nDate: Mon, 1 Mar 2021 19:09:04 +0200\nSubject: [PATCH 153/247] ASoC: mchp-i2s-mcc: Add FIFOs support\n\nI2S-MCC found on SAMA7G5 includes 2 FIFOs (capture and playback). When\nFIFOs are enabled, bits I2SMCC_ISRA.TXLRDYx and I2SMCC_ISRA.TXRRDYx must\nnot be used. Bits I2SMCC_ISRB.TXFFRDY and I2SMCC_ISRB.RXFFRDY must be used\ninstead.\n\nSigned-off-by: Codrin Ciubotariu <codrin.ciubotariu@microchip.com>\nLink: https://lore.kernel.org/r/20210301170905.835091-7-codrin.ciubotariu@microchip.com\nSigned-off-by: Mark Brown <broonie@kernel.org>\n---\n sound/soc/atmel/mchp-i2s-mcc.c | 76 +++++++++++++++++++++++++---------\n 1 file changed, 56 insertions(+), 20 deletions(-)\n\n--- a/sound/soc/atmel/mchp-i2s-mcc.c\n+++ b/sound/soc/atmel/mchp-i2s-mcc.c\n@@ -176,7 +176,7 @@\n  */\n #define MCHP_I2SMCC_MRB_CRAMODE_REGULAR\t\t(1 << 0)\n \n-#define MCHP_I2SMCC_MRB_FIFOEN\t\t\tBIT(1)\n+#define MCHP_I2SMCC_MRB_FIFOEN\t\t\tBIT(4)\n \n #define MCHP_I2SMCC_MRB_DMACHUNK_MASK\t\tGENMASK(9, 8)\n #define MCHP_I2SMCC_MRB_DMACHUNK(no_words) \\\n@@ -230,6 +230,7 @@ static const struct regmap_config mchp_i\n \n struct mchp_i2s_mcc_soc_data {\n \tunsigned int\tdata_pin_pair_num;\n+\tbool\t\thas_fifo;\n };\n \n struct mchp_i2s_mcc_dev {\n@@ -257,7 +258,7 @@ struct mchp_i2s_mcc_dev {\n static irqreturn_t mchp_i2s_mcc_interrupt(int irq, void *dev_id)\n {\n \tstruct mchp_i2s_mcc_dev *dev = dev_id;\n-\tu32 sra, imra, srb, imrb, pendinga, pendingb, idra = 0;\n+\tu32 sra, imra, srb, imrb, pendinga, pendingb, idra = 0, idrb = 0;\n \tirqreturn_t ret = IRQ_NONE;\n \n \tregmap_read(dev->regmap, MCHP_I2SMCC_IMRA, &imra);\n@@ -275,24 +276,36 @@ static irqreturn_t mchp_i2s_mcc_interrup\n \t * Tx/Rx ready interrupts are enabled when stopping only, to assure\n \t * availability and to disable clocks if necessary\n \t */\n-\tidra |= pendinga & (MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels) |\n-\t\t\t    MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels));\n-\tif (idra)\n+\tif (dev->soc->has_fifo) {\n+\t\tidrb |= pendingb & (MCHP_I2SMCC_INT_TXFFRDY |\n+\t\t\t\t    MCHP_I2SMCC_INT_RXFFRDY);\n+\t} else {\n+\t\tidra |= pendinga & (MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels) |\n+\t\t\t\t    MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels));\n+\t}\n+\tif (idra || idrb)\n \t\tret = IRQ_HANDLED;\n \n-\tif ((imra & MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels)) &&\n-\t    (imra & MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels)) ==\n-\t    (idra & MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels))) {\n+\tif ((!dev->soc->has_fifo &&\n+\t     (imra & MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels)) &&\n+\t     (imra & MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels)) ==\n+\t     (idra & MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels))) ||\n+\t    (dev->soc->has_fifo && imrb & MCHP_I2SMCC_INT_TXFFRDY)) {\n \t\tdev->tx_rdy = 1;\n \t\twake_up_interruptible(&dev->wq_txrdy);\n \t}\n-\tif ((imra & MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels)) &&\n-\t    (imra & MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels)) ==\n-\t    (idra & MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels))) {\n+\tif ((!dev->soc->has_fifo &&\n+\t     (imra & MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels)) &&\n+\t     (imra & MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels)) ==\n+\t     (idra & MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels))) ||\n+\t    (dev->soc->has_fifo && imrb & MCHP_I2SMCC_INT_RXFFRDY)) {\n \t\tdev->rx_rdy = 1;\n \t\twake_up_interruptible(&dev->wq_rxrdy);\n \t}\n-\tregmap_write(dev->regmap, MCHP_I2SMCC_IDRA, idra);\n+\tif (dev->soc->has_fifo)\n+\t\tregmap_write(dev->regmap, MCHP_I2SMCC_IDRB, idrb);\n+\telse\n+\t\tregmap_write(dev->regmap, MCHP_I2SMCC_IDRA, idra);\n \n \treturn ret;\n }\n@@ -664,6 +677,10 @@ static int mchp_i2s_mcc_hw_params(struct\n \t\t}\n \t}\n \n+\t/* enable FIFO if available */\n+\tif (dev->soc->has_fifo)\n+\t\tmrb |= MCHP_I2SMCC_MRB_FIFOEN;\n+\n \t/*\n \t * If we are already running, the wanted setup must be\n \t * the same with the one that's currently ongoing\n@@ -726,8 +743,13 @@ static int mchp_i2s_mcc_hw_free(struct s\n \t\tif (err == 0) {\n \t\t\tdev_warn_once(dev->dev,\n \t\t\t\t      \"Timeout waiting for Tx ready\\n\");\n-\t\t\tregmap_write(dev->regmap, MCHP_I2SMCC_IDRA,\n-\t\t\t\t     MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels));\n+\t\t\tif (dev->soc->has_fifo)\n+\t\t\t\tregmap_write(dev->regmap, MCHP_I2SMCC_IDRB,\n+\t\t\t\t\t     MCHP_I2SMCC_INT_TXFFRDY);\n+\t\t\telse\n+\t\t\t\tregmap_write(dev->regmap, MCHP_I2SMCC_IDRA,\n+\t\t\t\t\t     MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels));\n+\n \t\t\tdev->tx_rdy = 1;\n \t\t}\n \t} else {\n@@ -737,8 +759,12 @@ static int mchp_i2s_mcc_hw_free(struct s\n \t\tif (err == 0) {\n \t\t\tdev_warn_once(dev->dev,\n \t\t\t\t      \"Timeout waiting for Rx ready\\n\");\n-\t\t\tregmap_write(dev->regmap, MCHP_I2SMCC_IDRA,\n-\t\t\t\t     MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels));\n+\t\t\tif (dev->soc->has_fifo)\n+\t\t\t\tregmap_write(dev->regmap, MCHP_I2SMCC_IDRB,\n+\t\t\t\t\t     MCHP_I2SMCC_INT_RXFFRDY);\n+\t\t\telse\n+\t\t\t\tregmap_write(dev->regmap, MCHP_I2SMCC_IDRA,\n+\t\t\t\t\t     MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels));\n \t\t\tdev->rx_rdy = 1;\n \t\t}\n \t}\n@@ -765,7 +791,7 @@ static int mchp_i2s_mcc_trigger(struct s\n \tstruct mchp_i2s_mcc_dev *dev = snd_soc_dai_get_drvdata(dai);\n \tbool is_playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);\n \tu32 cr = 0;\n-\tu32 iera = 0;\n+\tu32 iera = 0, ierb = 0;\n \tu32 sr;\n \tint err;\n \n@@ -789,7 +815,10 @@ static int mchp_i2s_mcc_trigger(struct s\n \t\t\t * Enable Tx Ready interrupts on all channels\n \t\t\t * to assure all data is sent\n \t\t\t */\n-\t\t\tiera = MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels);\n+\t\t\tif (dev->soc->has_fifo)\n+\t\t\t\tierb = MCHP_I2SMCC_INT_TXFFRDY;\n+\t\t\telse\n+\t\t\t\tiera = MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels);\n \t\t} else if (!is_playback && (sr & MCHP_I2SMCC_SR_RXEN)) {\n \t\t\tcr = MCHP_I2SMCC_CR_RXDIS;\n \t\t\tdev->rx_rdy = 0;\n@@ -797,7 +826,10 @@ static int mchp_i2s_mcc_trigger(struct s\n \t\t\t * Enable Rx Ready interrupts on all channels\n \t\t\t * to assure all data is received\n \t\t\t */\n-\t\t\tiera = MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels);\n+\t\t\tif (dev->soc->has_fifo)\n+\t\t\t\tierb = MCHP_I2SMCC_INT_RXFFRDY;\n+\t\t\telse\n+\t\t\t\tiera = MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels);\n \t\t}\n \t\tbreak;\n \tdefault:\n@@ -815,7 +847,10 @@ static int mchp_i2s_mcc_trigger(struct s\n \t\t}\n \t}\n \n-\tregmap_write(dev->regmap, MCHP_I2SMCC_IERA, iera);\n+\tif (dev->soc->has_fifo)\n+\t\tregmap_write(dev->regmap, MCHP_I2SMCC_IERB, ierb);\n+\telse\n+\t\tregmap_write(dev->regmap, MCHP_I2SMCC_IERA, iera);\n \tregmap_write(dev->regmap, MCHP_I2SMCC_CR, cr);\n \n \treturn 0;\n@@ -903,6 +938,7 @@ static struct mchp_i2s_mcc_soc_data mchp\n \n static struct mchp_i2s_mcc_soc_data mchp_i2s_mcc_sama7g5 = {\n \t.data_pin_pair_num = 4,\n+\t.has_fifo = true,\n };\n \n static const struct of_device_id mchp_i2s_mcc_dt_ids[] = {\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/154-pinctrl-at91-pio4-Fix-slew-rate-disablement.patch",
    "content": "From dc07cbae6e96843d26e8f10b16e901620bd16462 Mon Sep 17 00:00:00 2001\nFrom: Tudor Ambarus <tudor.ambarus@microchip.com>\nDate: Fri, 9 Apr 2021 11:25:22 +0300\nSubject: [PATCH 154/247] pinctrl: at91-pio4: Fix slew rate disablement\n\nThe slew rate was enabled by default for each configuration of the\npin. In case the pin had more than one configuration, even if\nwe set the slew rate as disabled in the device tree, the next pin\nconfiguration would set again the slew rate enabled by default,\noverwriting the slew rate disablement.\nInstead of enabling the slew rate by default for each pin configuration,\nenable the slew rate by default just once per pin, regardless of the\nnumber of configurations. This way the slew rate disablement will also\nwork for cases where pins have multiple configurations.\n\nFixes: c709135e576b (\"pinctrl: at91-pio4: add support for slew-rate\")\nSigned-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>\nReviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>\nAcked-by: Ludovic Desroches <ludovic.desroches@microchip.com>\nLink: https://lore.kernel.org/r/20210409082522.625168-1-tudor.ambarus@microchip.com\nSigned-off-by: Linus Walleij <linus.walleij@linaro.org>\n---\n drivers/pinctrl/pinctrl-at91-pio4.c | 8 ++++----\n 1 file changed, 4 insertions(+), 4 deletions(-)\n\n--- a/drivers/pinctrl/pinctrl-at91-pio4.c\n+++ b/drivers/pinctrl/pinctrl-at91-pio4.c\n@@ -801,6 +801,10 @@ static int atmel_conf_pin_config_group_s\n \n \tconf = atmel_pin_config_read(pctldev, pin_id);\n \n+\t/* Keep slew rate enabled by default. */\n+\tif (atmel_pioctrl->slew_rate_support)\n+\t\tconf |= ATMEL_PIO_SR_MASK;\n+\n \tfor (i = 0; i < num_configs; i++) {\n \t\tunsigned int param = pinconf_to_config_param(configs[i]);\n \t\tunsigned int arg = pinconf_to_config_argument(configs[i]);\n@@ -808,10 +812,6 @@ static int atmel_conf_pin_config_group_s\n \t\tdev_dbg(pctldev->dev, \"%s: pin=%u, config=0x%lx\\n\",\n \t\t\t__func__, pin_id, configs[i]);\n \n-\t\t/* Keep slew rate enabled by default. */\n-\t\tif (atmel_pioctrl->slew_rate_support)\n-\t\t\tconf |= ATMEL_PIO_SR_MASK;\n-\n \t\tswitch (param) {\n \t\tcase PIN_CONFIG_BIAS_DISABLE:\n \t\t\tconf &= (~ATMEL_PIO_PUEN_MASK);\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/155-media-atmel-properly-get-pm_runtime.patch",
    "content": "From c7660cc977621c4a14d870d523918df067f0db39 Mon Sep 17 00:00:00 2001\nFrom: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>\nDate: Fri, 23 Apr 2021 16:47:42 +0200\nSubject: [PATCH 155/247] media: atmel: properly get pm_runtime\n\nThere are several issues in the way the atmel driver handles\npm_runtime_get_sync():\n\n- it doesn't check return codes;\n- it doesn't properly decrement the usage_count on all places;\n- it starts streaming even if pm_runtime_get_sync() fails.\n- while it tries to get pm_runtime at the clock enable logic,\n  it doesn't check if the operation was suceeded.\n\nReplace all occurrences of it to use the new kAPI:\npm_runtime_resume_and_get(), which ensures that, if the\nreturn code is not negative, the usage_count was incremented.\n\nWith that, add additional checks when this is called, in order\nto ensure that errors will be properly addressed.\n\nSigned-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>\n---\n drivers/media/platform/atmel/atmel-isc-base.c | 30 ++++++++++++++-----\n drivers/media/platform/atmel/atmel-isi.c      | 19 +++++++++---\n 2 files changed, 38 insertions(+), 11 deletions(-)\n\n--- a/drivers/media/platform/atmel/atmel-isc-base.c\n+++ b/drivers/media/platform/atmel/atmel-isc-base.c\n@@ -294,9 +294,13 @@ static int isc_wait_clk_stable(struct cl\n static int isc_clk_prepare(struct clk_hw *hw)\n {\n \tstruct isc_clk *isc_clk = to_isc_clk(hw);\n+\tint ret;\n \n-\tif (isc_clk->id == ISC_ISPCK)\n-\t\tpm_runtime_get_sync(isc_clk->dev);\n+\tif (isc_clk->id == ISC_ISPCK) {\n+\t\tret = pm_runtime_resume_and_get(isc_clk->dev);\n+\t\tif (ret < 0)\n+\t\t\treturn ret;\n+\t}\n \n \treturn isc_wait_clk_stable(hw);\n }\n@@ -353,9 +357,13 @@ static int isc_clk_is_enabled(struct clk\n {\n \tstruct isc_clk *isc_clk = to_isc_clk(hw);\n \tu32 status;\n+\tint ret;\n \n-\tif (isc_clk->id == ISC_ISPCK)\n-\t\tpm_runtime_get_sync(isc_clk->dev);\n+\tif (isc_clk->id == ISC_ISPCK) {\n+\t\tret = pm_runtime_resume_and_get(isc_clk->dev);\n+\t\tif (ret < 0)\n+\t\t\treturn 0;\n+\t}\n \n \tregmap_read(isc_clk->regmap, ISC_CLKSR, &status);\n \n@@ -807,7 +815,12 @@ static int isc_start_streaming(struct vb\n \t\tgoto err_start_stream;\n \t}\n \n-\tpm_runtime_get_sync(isc->dev);\n+\tret = pm_runtime_resume_and_get(isc->dev);\n+\tif (ret < 0) {\n+\t\tv4l2_err(&isc->v4l2_dev, \"RPM resume failed in subdev %d\\n\",\n+\t\t\t ret);\n+\t\tgoto err_pm_get;\n+\t}\n \n \tret = isc_configure(isc);\n \tif (unlikely(ret))\n@@ -838,7 +851,7 @@ static int isc_start_streaming(struct vb\n \n err_configure:\n \tpm_runtime_put_sync(isc->dev);\n-\n+err_pm_get:\n \tv4l2_subdev_call(isc->current_subdev->sd, video, s_stream, 0);\n \n err_start_stream:\n@@ -1809,6 +1822,7 @@ static void isc_awb_work(struct work_str\n \tu32 baysel;\n \tunsigned long flags;\n \tu32 min, max;\n+\tint ret;\n \n \t/* streaming is not active anymore */\n \tif (isc->stop)\n@@ -1831,7 +1845,9 @@ static void isc_awb_work(struct work_str\n \tctrls->hist_id = hist_id;\n \tbaysel = isc->config.sd_format->cfa_baycfg << ISC_HIS_CFG_BAYSEL_SHIFT;\n \n-\tpm_runtime_get_sync(isc->dev);\n+\tret = pm_runtime_resume_and_get(isc->dev);\n+\tif (ret < 0)\n+\t\treturn;\n \n \t/*\n \t * only update if we have all the required histograms and controls\n--- a/drivers/media/platform/atmel/atmel-isi.c\n+++ b/drivers/media/platform/atmel/atmel-isi.c\n@@ -423,7 +423,9 @@ static int start_streaming(struct vb2_qu\n \tstruct frame_buffer *buf, *node;\n \tint ret;\n \n-\tpm_runtime_get_sync(isi->dev);\n+\tret = pm_runtime_resume_and_get(isi->dev);\n+\tif (ret < 0)\n+\t\treturn ret;\n \n \t/* Enable stream on the sub device */\n \tret = v4l2_subdev_call(isi->entity.subdev, video, s_stream, 1);\n@@ -783,9 +785,10 @@ static int isi_enum_frameintervals(struc\n \treturn 0;\n }\n \n-static void isi_camera_set_bus_param(struct atmel_isi *isi)\n+static int isi_camera_set_bus_param(struct atmel_isi *isi)\n {\n \tu32 cfg1 = 0;\n+\tint ret;\n \n \t/* set bus param for ISI */\n \tif (isi->pdata.hsync_act_low)\n@@ -802,12 +805,16 @@ static void isi_camera_set_bus_param(str\n \tcfg1 |= ISI_CFG1_THMASK_BEATS_16;\n \n \t/* Enable PM and peripheral clock before operate isi registers */\n-\tpm_runtime_get_sync(isi->dev);\n+\tret = pm_runtime_resume_and_get(isi->dev);\n+\tif (ret < 0)\n+\t\treturn ret;\n \n \tisi_writel(isi, ISI_CTRL, ISI_CTRL_DIS);\n \tisi_writel(isi, ISI_CFG1, cfg1);\n \n \tpm_runtime_put(isi->dev);\n+\n+\treturn 0;\n }\n \n /* -----------------------------------------------------------------------*/\n@@ -1086,7 +1093,11 @@ static int isi_graph_notify_complete(str\n \t\tdev_err(isi->dev, \"No supported mediabus format found\\n\");\n \t\treturn ret;\n \t}\n-\tisi_camera_set_bus_param(isi);\n+\tret = isi_camera_set_bus_param(isi);\n+\tif (ret) {\n+\t\tdev_err(isi->dev, \"Can't wake up device\\n\");\n+\t\treturn ret;\n+\t}\n \n \tret = isi_set_default_fmt(isi);\n \tif (ret) {\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/156-media-atmel-atmel-isc-Remove-redundant-assignment-to.patch",
    "content": "From b074b4695004b793a9199716295cb76da6c41686 Mon Sep 17 00:00:00 2001\nFrom: Jiapeng Chong <jiapeng.chong@linux.alibaba.com>\nDate: Mon, 17 May 2021 12:07:48 +0200\nSubject: [PATCH 156/247] media: atmel: atmel-isc: Remove redundant assignment\n to i\n\nVariable i is being assigned a value however the assignment is\nnever read, so this redundant assignment can be removed.\n\nClean up the following clang-analyzer warning:\n\ndrivers/media/platform/atmel/atmel-isc-base.c:975:2: warning: Value\nstored to 'i' is never read [clang-analyzer-deadcode.DeadStores].\n\nReported-by: Abaci Robot <abaci@linux.alibaba.com>\nSigned-off-by: Jiapeng Chong <jiapeng.chong@linux.alibaba.com>\nSigned-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>\nSigned-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>\n---\n drivers/media/platform/atmel/atmel-isc-base.c | 1 -\n 1 file changed, 1 deletion(-)\n\n--- a/drivers/media/platform/atmel/atmel-isc-base.c\n+++ b/drivers/media/platform/atmel/atmel-isc-base.c\n@@ -972,7 +972,6 @@ static int isc_enum_fmt_vid_cap(struct f\n \n \tindex -= ARRAY_SIZE(controller_formats);\n \n-\ti = 0;\n \tsupported_index = 0;\n \n \tfor (i = 0; i < ARRAY_SIZE(formats_list); i++) {\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/157-media-atmel-atmel-isc-specialize-gamma-table-into-pr.patch",
    "content": "From c3f54d192dc7344c5216a3628b67c4bbccbf8c3c Mon Sep 17 00:00:00 2001\nFrom: Eugen Hristev <eugen.hristev@microchip.com>\nDate: Tue, 13 Apr 2021 12:56:59 +0200\nSubject: [PATCH 157/247] media: atmel: atmel-isc: specialize gamma table into\n product specific\n\nSeparate the gamma table from the isc base file into the specific sama5d2\nproduct file.\nAdd a pointer to the gamma table and entries count inside the platform\ndriver specific struct.\n\n[hverkuil: made isc_sama5d2_gamma_table static]\n\nSigned-off-by: Eugen Hristev <eugen.hristev@microchip.com>\nSigned-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>\nSigned-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>\n---\n drivers/media/platform/atmel/atmel-isc-base.c | 47 ++-----------------\n drivers/media/platform/atmel/atmel-isc.h      | 11 +++--\n .../media/platform/atmel/atmel-sama5d2-isc.c  | 45 ++++++++++++++++++\n 3 files changed, 56 insertions(+), 47 deletions(-)\n\n--- a/drivers/media/platform/atmel/atmel-isc-base.c\n+++ b/drivers/media/platform/atmel/atmel-isc-base.c\n@@ -176,48 +176,6 @@ struct isc_format formats_list[] = {\n \n };\n \n-/* Gamma table with gamma 1/2.2 */\n-const u32 isc_gamma_table[GAMMA_MAX + 1][GAMMA_ENTRIES] = {\n-\t/* 0 --> gamma 1/1.8 */\n-\t{      0x65,  0x66002F,  0x950025,  0xBB0020,  0xDB001D,  0xF8001A,\n-\t  0x1130018, 0x12B0017, 0x1420016, 0x1580014, 0x16D0013, 0x1810012,\n-\t  0x1940012, 0x1A60012, 0x1B80011, 0x1C90010, 0x1DA0010, 0x1EA000F,\n-\t  0x1FA000F, 0x209000F, 0x218000F, 0x227000E, 0x235000E, 0x243000E,\n-\t  0x251000E, 0x25F000D, 0x26C000D, 0x279000D, 0x286000D, 0x293000C,\n-\t  0x2A0000C, 0x2AC000C, 0x2B8000C, 0x2C4000C, 0x2D0000B, 0x2DC000B,\n-\t  0x2E7000B, 0x2F3000B, 0x2FE000B, 0x309000B, 0x314000B, 0x31F000A,\n-\t  0x32A000A, 0x334000B, 0x33F000A, 0x349000A, 0x354000A, 0x35E000A,\n-\t  0x368000A, 0x372000A, 0x37C000A, 0x386000A, 0x3900009, 0x399000A,\n-\t  0x3A30009, 0x3AD0009, 0x3B60009, 0x3BF000A, 0x3C90009, 0x3D20009,\n-\t  0x3DB0009, 0x3E40009, 0x3ED0009, 0x3F60009 },\n-\n-\t/* 1 --> gamma 1/2 */\n-\t{      0x7F,  0x800034,  0xB50028,  0xDE0021, 0x100001E, 0x11E001B,\n-\t  0x1390019, 0x1520017, 0x16A0015, 0x1800014, 0x1940014, 0x1A80013,\n-\t  0x1BB0012, 0x1CD0011, 0x1DF0010, 0x1EF0010, 0x200000F, 0x20F000F,\n-\t  0x21F000E, 0x22D000F, 0x23C000E, 0x24A000E, 0x258000D, 0x265000D,\n-\t  0x273000C, 0x27F000D, 0x28C000C, 0x299000C, 0x2A5000C, 0x2B1000B,\n-\t  0x2BC000C, 0x2C8000B, 0x2D3000C, 0x2DF000B, 0x2EA000A, 0x2F5000A,\n-\t  0x2FF000B, 0x30A000A, 0x314000B, 0x31F000A, 0x329000A, 0x333000A,\n-\t  0x33D0009, 0x3470009, 0x350000A, 0x35A0009, 0x363000A, 0x36D0009,\n-\t  0x3760009, 0x37F0009, 0x3880009, 0x3910009, 0x39A0009, 0x3A30009,\n-\t  0x3AC0008, 0x3B40009, 0x3BD0008, 0x3C60008, 0x3CE0008, 0x3D60009,\n-\t  0x3DF0008, 0x3E70008, 0x3EF0008, 0x3F70008 },\n-\n-\t/* 2 --> gamma 1/2.2 */\n-\t{      0x99,  0x9B0038,  0xD4002A,  0xFF0023, 0x122001F, 0x141001B,\n-\t  0x15D0019, 0x1760017, 0x18E0015, 0x1A30015, 0x1B80013, 0x1CC0012,\n-\t  0x1DE0011, 0x1F00010, 0x2010010, 0x2110010, 0x221000F, 0x230000F,\n-\t  0x23F000E, 0x24D000E, 0x25B000D, 0x269000C, 0x276000C, 0x283000C,\n-\t  0x28F000C, 0x29B000C, 0x2A7000C, 0x2B3000B, 0x2BF000B, 0x2CA000B,\n-\t  0x2D5000B, 0x2E0000A, 0x2EB000A, 0x2F5000A, 0x2FF000A, 0x30A000A,\n-\t  0x3140009, 0x31E0009, 0x327000A, 0x3310009, 0x33A0009, 0x3440009,\n-\t  0x34D0009, 0x3560009, 0x35F0009, 0x3680008, 0x3710008, 0x3790009,\n-\t  0x3820008, 0x38A0008, 0x3930008, 0x39B0008, 0x3A30008, 0x3AB0008,\n-\t  0x3B30008, 0x3BB0008, 0x3C30008, 0x3CB0007, 0x3D20008, 0x3DA0007,\n-\t  0x3E20007, 0x3E90007, 0x3F00008, 0x3F80007 },\n-};\n-\n #define ISC_IS_FORMAT_RAW(mbus_code) \\\n \t(((mbus_code) & 0xf000) == 0x3000)\n \n@@ -691,7 +649,7 @@ static void isc_set_pipeline(struct isc_\n \n \tregmap_write(regmap, ISC_CFA_CFG, bay_cfg | ISC_CFA_CFG_EITPOL);\n \n-\tgamma = &isc_gamma_table[ctrls->gamma_index][0];\n+\tgamma = &isc->gamma_table[ctrls->gamma_index][0];\n \tregmap_bulk_write(regmap, ISC_GAM_BENTRY, gamma, GAMMA_ENTRIES);\n \tregmap_bulk_write(regmap, ISC_GAM_GENTRY, gamma, GAMMA_ENTRIES);\n \tregmap_bulk_write(regmap, ISC_GAM_RENTRY, gamma, GAMMA_ENTRIES);\n@@ -2085,7 +2043,8 @@ static int isc_ctrl_init(struct isc_devi\n \n \tv4l2_ctrl_new_std(hdl, ops, V4L2_CID_BRIGHTNESS, -1024, 1023, 1, 0);\n \tv4l2_ctrl_new_std(hdl, ops, V4L2_CID_CONTRAST, -2048, 2047, 1, 256);\n-\tv4l2_ctrl_new_std(hdl, ops, V4L2_CID_GAMMA, 0, GAMMA_MAX, 1, 2);\n+\tv4l2_ctrl_new_std(hdl, ops, V4L2_CID_GAMMA, 0, isc->gamma_max, 1,\n+\t\t\t  isc->gamma_max);\n \tisc->awb_ctrl = v4l2_ctrl_new_std(hdl, &isc_awb_ops,\n \t\t\t\t\t  V4L2_CID_AUTO_WHITE_BALANCE,\n \t\t\t\t\t  0, 1, 1, 1);\n--- a/drivers/media/platform/atmel/atmel-isc.h\n+++ b/drivers/media/platform/atmel/atmel-isc.h\n@@ -186,6 +186,10 @@ struct isc_ctrls {\n  *\n  * @current_subdev:\tcurrent subdevice: the sensor\n  * @subdev_entities:\tlist of subdevice entitites\n+ *\n+ * @gamma_table:\tpointer to the table with gamma values, has\n+ *\t\t\tgamma_max sets of GAMMA_ENTRIES entries each\n+ * @gamma_max:\t\tmaximum number of sets of inside the gamma_table\n  */\n struct isc_device {\n \tstruct regmap\t\t*regmap;\n@@ -244,16 +248,17 @@ struct isc_device {\n \t\tstruct v4l2_ctrl\t*gr_off_ctrl;\n \t\tstruct v4l2_ctrl\t*gb_off_ctrl;\n \t};\n-};\n \n-#define GAMMA_MAX\t2\n #define GAMMA_ENTRIES\t64\n+\t/* pointer to the defined gamma table */\n+\tconst u32\t(*gamma_table)[GAMMA_ENTRIES];\n+\tu32\t\tgamma_max;\n+};\n \n #define ATMEL_ISC_NAME \"atmel-isc\"\n \n extern struct isc_format formats_list[];\n extern const struct isc_format controller_formats[];\n-extern const u32 isc_gamma_table[GAMMA_MAX + 1][GAMMA_ENTRIES];\n extern const struct regmap_config isc_regmap_config;\n extern const struct v4l2_async_notifier_operations isc_async_ops;\n \n--- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c\n+++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c\n@@ -54,6 +54,48 @@\n \n #define ISC_CLK_MAX_DIV\t\t255\n \n+/* Gamma table with gamma 1/2.2 */\n+static const u32 isc_sama5d2_gamma_table[][GAMMA_ENTRIES] = {\n+\t/* 0 --> gamma 1/1.8 */\n+\t{      0x65,  0x66002F,  0x950025,  0xBB0020,  0xDB001D,  0xF8001A,\n+\t  0x1130018, 0x12B0017, 0x1420016, 0x1580014, 0x16D0013, 0x1810012,\n+\t  0x1940012, 0x1A60012, 0x1B80011, 0x1C90010, 0x1DA0010, 0x1EA000F,\n+\t  0x1FA000F, 0x209000F, 0x218000F, 0x227000E, 0x235000E, 0x243000E,\n+\t  0x251000E, 0x25F000D, 0x26C000D, 0x279000D, 0x286000D, 0x293000C,\n+\t  0x2A0000C, 0x2AC000C, 0x2B8000C, 0x2C4000C, 0x2D0000B, 0x2DC000B,\n+\t  0x2E7000B, 0x2F3000B, 0x2FE000B, 0x309000B, 0x314000B, 0x31F000A,\n+\t  0x32A000A, 0x334000B, 0x33F000A, 0x349000A, 0x354000A, 0x35E000A,\n+\t  0x368000A, 0x372000A, 0x37C000A, 0x386000A, 0x3900009, 0x399000A,\n+\t  0x3A30009, 0x3AD0009, 0x3B60009, 0x3BF000A, 0x3C90009, 0x3D20009,\n+\t  0x3DB0009, 0x3E40009, 0x3ED0009, 0x3F60009 },\n+\n+\t/* 1 --> gamma 1/2 */\n+\t{      0x7F,  0x800034,  0xB50028,  0xDE0021, 0x100001E, 0x11E001B,\n+\t  0x1390019, 0x1520017, 0x16A0015, 0x1800014, 0x1940014, 0x1A80013,\n+\t  0x1BB0012, 0x1CD0011, 0x1DF0010, 0x1EF0010, 0x200000F, 0x20F000F,\n+\t  0x21F000E, 0x22D000F, 0x23C000E, 0x24A000E, 0x258000D, 0x265000D,\n+\t  0x273000C, 0x27F000D, 0x28C000C, 0x299000C, 0x2A5000C, 0x2B1000B,\n+\t  0x2BC000C, 0x2C8000B, 0x2D3000C, 0x2DF000B, 0x2EA000A, 0x2F5000A,\n+\t  0x2FF000B, 0x30A000A, 0x314000B, 0x31F000A, 0x329000A, 0x333000A,\n+\t  0x33D0009, 0x3470009, 0x350000A, 0x35A0009, 0x363000A, 0x36D0009,\n+\t  0x3760009, 0x37F0009, 0x3880009, 0x3910009, 0x39A0009, 0x3A30009,\n+\t  0x3AC0008, 0x3B40009, 0x3BD0008, 0x3C60008, 0x3CE0008, 0x3D60009,\n+\t  0x3DF0008, 0x3E70008, 0x3EF0008, 0x3F70008 },\n+\n+\t/* 2 --> gamma 1/2.2 */\n+\t{      0x99,  0x9B0038,  0xD4002A,  0xFF0023, 0x122001F, 0x141001B,\n+\t  0x15D0019, 0x1760017, 0x18E0015, 0x1A30015, 0x1B80013, 0x1CC0012,\n+\t  0x1DE0011, 0x1F00010, 0x2010010, 0x2110010, 0x221000F, 0x230000F,\n+\t  0x23F000E, 0x24D000E, 0x25B000D, 0x269000C, 0x276000C, 0x283000C,\n+\t  0x28F000C, 0x29B000C, 0x2A7000C, 0x2B3000B, 0x2BF000B, 0x2CA000B,\n+\t  0x2D5000B, 0x2E0000A, 0x2EB000A, 0x2F5000A, 0x2FF000A, 0x30A000A,\n+\t  0x3140009, 0x31E0009, 0x327000A, 0x3310009, 0x33A0009, 0x3440009,\n+\t  0x34D0009, 0x3560009, 0x35F0009, 0x3680008, 0x3710008, 0x3790009,\n+\t  0x3820008, 0x38A0008, 0x3930008, 0x39B0008, 0x3A30008, 0x3AB0008,\n+\t  0x3B30008, 0x3BB0008, 0x3C30008, 0x3CB0007, 0x3D20008, 0x3DA0007,\n+\t  0x3E20007, 0x3E90007, 0x3F00008, 0x3F80007 },\n+};\n+\n static int isc_parse_dt(struct device *dev, struct isc_device *isc)\n {\n \tstruct device_node *np = dev->of_node;\n@@ -171,6 +213,9 @@ static int atmel_isc_probe(struct platfo\n \t\treturn ret;\n \t}\n \n+\tisc->gamma_table = isc_sama5d2_gamma_table;\n+\tisc->gamma_max = 2;\n+\n \tret = isc_pipeline_init(isc);\n \tif (ret)\n \t\treturn ret;\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/158-media-atmel-atmel-isc-specialize-driver-name-constan.patch",
    "content": "From 0576e163d93d08a1ed112bd23f40478ef3fd323d Mon Sep 17 00:00:00 2001\nFrom: Eugen Hristev <eugen.hristev@microchip.com>\nDate: Tue, 13 Apr 2021 12:57:00 +0200\nSubject: [PATCH 158/247] media: atmel: atmel-isc: specialize driver name\n constant\n\nThe driver name constant must defined based on product driver, thus moving\nthe constant directly where it's required. This will allow each ISC based\nproduct to define it's own name.\n\nSigned-off-by: Eugen Hristev <eugen.hristev@microchip.com>\nSigned-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>\nSigned-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>\n---\n drivers/media/platform/atmel/atmel-isc-base.c    | 4 ++--\n drivers/media/platform/atmel/atmel-isc.h         | 2 --\n drivers/media/platform/atmel/atmel-sama5d2-isc.c | 4 ++--\n 3 files changed, 4 insertions(+), 6 deletions(-)\n\n--- a/drivers/media/platform/atmel/atmel-isc-base.c\n+++ b/drivers/media/platform/atmel/atmel-isc-base.c\n@@ -909,7 +909,7 @@ static int isc_querycap(struct file *fil\n {\n \tstruct isc_device *isc = video_drvdata(file);\n \n-\tstrscpy(cap->driver, ATMEL_ISC_NAME, sizeof(cap->driver));\n+\tstrscpy(cap->driver, \"microchip-isc\", sizeof(cap->driver));\n \tstrscpy(cap->card, \"Atmel Image Sensor Controller\", sizeof(cap->card));\n \tsnprintf(cap->bus_info, sizeof(cap->bus_info),\n \t\t \"platform:%s\", isc->v4l2_dev.name);\n@@ -2261,7 +2261,7 @@ static int isc_async_complete(struct v4l\n \t}\n \n \t/* Register video device */\n-\tstrscpy(vdev->name, ATMEL_ISC_NAME, sizeof(vdev->name));\n+\tstrscpy(vdev->name, \"microchip-isc\", sizeof(vdev->name));\n \tvdev->release\t\t= video_device_release_empty;\n \tvdev->fops\t\t= &isc_fops;\n \tvdev->ioctl_ops\t\t= &isc_ioctl_ops;\n--- a/drivers/media/platform/atmel/atmel-isc.h\n+++ b/drivers/media/platform/atmel/atmel-isc.h\n@@ -255,8 +255,6 @@ struct isc_device {\n \tu32\t\tgamma_max;\n };\n \n-#define ATMEL_ISC_NAME \"atmel-isc\"\n-\n extern struct isc_format formats_list[];\n extern const struct isc_format controller_formats[];\n extern const struct regmap_config isc_regmap_config;\n--- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c\n+++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c\n@@ -206,7 +206,7 @@ static int atmel_isc_probe(struct platfo\n \t\treturn irq;\n \n \tret = devm_request_irq(dev, irq, isc_interrupt, 0,\n-\t\t\t       ATMEL_ISC_NAME, isc);\n+\t\t\t       \"atmel-sama5d2-isc\", isc);\n \tif (ret < 0) {\n \t\tdev_err(dev, \"can't register ISR for IRQ %u (ret=%i)\\n\",\n \t\t\tirq, ret);\n@@ -378,7 +378,7 @@ static struct platform_driver atmel_isc_\n \t.probe\t= atmel_isc_probe,\n \t.remove\t= atmel_isc_remove,\n \t.driver\t= {\n-\t\t.name\t\t= ATMEL_ISC_NAME,\n+\t\t.name\t\t= \"atmel-sama5d2-isc\",\n \t\t.pm\t\t= &atmel_isc_dev_pm_ops,\n \t\t.of_match_table = of_match_ptr(atmel_isc_of_match),\n \t},\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/159-media-atmel-atmel-isc-add-checks-for-limiting-frame-.patch",
    "content": "From de8fa25cdf3726c83ac0d7b3b1e28bcb6334aadd Mon Sep 17 00:00:00 2001\nFrom: Eugen Hristev <eugen.hristev@microchip.com>\nDate: Tue, 13 Apr 2021 12:57:01 +0200\nSubject: [PATCH 159/247] media: atmel: atmel-isc: add checks for limiting\n frame sizes\n\nWhen calling the subdev, certain subdev drivers will overwrite the\nframe size and adding sizes which are beyond the ISC's capabilities.\nThus we need to ensure the frame size is cropped to the maximum caps.\n\nSigned-off-by: Eugen Hristev <eugen.hristev@microchip.com>\nSigned-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>\nSigned-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>\n---\n drivers/media/platform/atmel/atmel-isc-base.c | 12 ++++++++++++\n 1 file changed, 12 insertions(+)\n\n--- a/drivers/media/platform/atmel/atmel-isc-base.c\n+++ b/drivers/media/platform/atmel/atmel-isc-base.c\n@@ -1338,6 +1338,12 @@ static int isc_try_fmt(struct isc_device\n \n \tv4l2_fill_pix_format(pixfmt, &format.format);\n \n+\t/* Limit to Atmel ISC hardware capabilities */\n+\tif (pixfmt->width > ISC_MAX_SUPPORT_WIDTH)\n+\t\tpixfmt->width = ISC_MAX_SUPPORT_WIDTH;\n+\tif (pixfmt->height > ISC_MAX_SUPPORT_HEIGHT)\n+\t\tpixfmt->height = ISC_MAX_SUPPORT_HEIGHT;\n+\n \tpixfmt->field = V4L2_FIELD_NONE;\n \tpixfmt->bytesperline = (pixfmt->width * isc->try_config.bpp) >> 3;\n \tpixfmt->sizeimage = pixfmt->bytesperline * pixfmt->height;\n@@ -1373,6 +1379,12 @@ static int isc_set_fmt(struct isc_device\n \tif (ret < 0)\n \t\treturn ret;\n \n+\t/* Limit to Atmel ISC hardware capabilities */\n+\tif (pixfmt->width > ISC_MAX_SUPPORT_WIDTH)\n+\t\tpixfmt->width = ISC_MAX_SUPPORT_WIDTH;\n+\tif (pixfmt->height > ISC_MAX_SUPPORT_HEIGHT)\n+\t\tpixfmt->height = ISC_MAX_SUPPORT_HEIGHT;\n+\n \tisc->fmt = *f;\n \n \tif (isc->try_config.sd_format && isc->config.sd_format &&\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/160-media-atmel-atmel-isc-specialize-max-width-and-max-h.patch",
    "content": "From b51819e17260af2ecc152b7dcd61e63bcaa35edf Mon Sep 17 00:00:00 2001\nFrom: Eugen Hristev <eugen.hristev@microchip.com>\nDate: Tue, 13 Apr 2021 12:57:02 +0200\nSubject: [PATCH 160/247] media: atmel: atmel-isc: specialize max width and max\n height\n\nMove the max width and max height constants to the product specific driver\nand have them in the device struct.\n\nSigned-off-by: Eugen Hristev <eugen.hristev@microchip.com>\nSigned-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>\nSigned-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>\n---\n drivers/media/platform/atmel/atmel-isc-base.c | 28 +++++++++----------\n drivers/media/platform/atmel/atmel-isc.h      |  9 ++++--\n .../media/platform/atmel/atmel-sama5d2-isc.c  |  7 +++--\n 3 files changed, 25 insertions(+), 19 deletions(-)\n\n--- a/drivers/media/platform/atmel/atmel-isc-base.c\n+++ b/drivers/media/platform/atmel/atmel-isc-base.c\n@@ -1216,8 +1216,8 @@ static void isc_try_fse(struct isc_devic\n \t * just use the maximum ISC can receive.\n \t */\n \tif (ret) {\n-\t\tpad_cfg->try_crop.width = ISC_MAX_SUPPORT_WIDTH;\n-\t\tpad_cfg->try_crop.height = ISC_MAX_SUPPORT_HEIGHT;\n+\t\tpad_cfg->try_crop.width = isc->max_width;\n+\t\tpad_cfg->try_crop.height = isc->max_height;\n \t} else {\n \t\tpad_cfg->try_crop.width = fse.max_width;\n \t\tpad_cfg->try_crop.height = fse.max_height;\n@@ -1294,10 +1294,10 @@ static int isc_try_fmt(struct isc_device\n \tisc->try_config.sd_format = sd_fmt;\n \n \t/* Limit to Atmel ISC hardware capabilities */\n-\tif (pixfmt->width > ISC_MAX_SUPPORT_WIDTH)\n-\t\tpixfmt->width = ISC_MAX_SUPPORT_WIDTH;\n-\tif (pixfmt->height > ISC_MAX_SUPPORT_HEIGHT)\n-\t\tpixfmt->height = ISC_MAX_SUPPORT_HEIGHT;\n+\tif (pixfmt->width > isc->max_width)\n+\t\tpixfmt->width = isc->max_width;\n+\tif (pixfmt->height > isc->max_height)\n+\t\tpixfmt->height = isc->max_height;\n \n \t/*\n \t * The mbus format is the one the subdev outputs.\n@@ -1339,10 +1339,10 @@ static int isc_try_fmt(struct isc_device\n \tv4l2_fill_pix_format(pixfmt, &format.format);\n \n \t/* Limit to Atmel ISC hardware capabilities */\n-\tif (pixfmt->width > ISC_MAX_SUPPORT_WIDTH)\n-\t\tpixfmt->width = ISC_MAX_SUPPORT_WIDTH;\n-\tif (pixfmt->height > ISC_MAX_SUPPORT_HEIGHT)\n-\t\tpixfmt->height = ISC_MAX_SUPPORT_HEIGHT;\n+\tif (pixfmt->width > isc->max_width)\n+\t\tpixfmt->width = isc->max_width;\n+\tif (pixfmt->height > isc->max_height)\n+\t\tpixfmt->height = isc->max_height;\n \n \tpixfmt->field = V4L2_FIELD_NONE;\n \tpixfmt->bytesperline = (pixfmt->width * isc->try_config.bpp) >> 3;\n@@ -1380,10 +1380,10 @@ static int isc_set_fmt(struct isc_device\n \t\treturn ret;\n \n \t/* Limit to Atmel ISC hardware capabilities */\n-\tif (pixfmt->width > ISC_MAX_SUPPORT_WIDTH)\n-\t\tpixfmt->width = ISC_MAX_SUPPORT_WIDTH;\n-\tif (pixfmt->height > ISC_MAX_SUPPORT_HEIGHT)\n-\t\tpixfmt->height = ISC_MAX_SUPPORT_HEIGHT;\n+\tif (f->fmt.pix.width > isc->max_width)\n+\t\tf->fmt.pix.width = isc->max_width;\n+\tif (f->fmt.pix.height > isc->max_height)\n+\t\tf->fmt.pix.height = isc->max_height;\n \n \tisc->fmt = *f;\n \n--- a/drivers/media/platform/atmel/atmel-isc.h\n+++ b/drivers/media/platform/atmel/atmel-isc.h\n@@ -10,9 +10,6 @@\n  */\n #ifndef _ATMEL_ISC_H_\n \n-#define ISC_MAX_SUPPORT_WIDTH   2592\n-#define ISC_MAX_SUPPORT_HEIGHT  1944\n-\n #define ISC_CLK_MAX_DIV\t\t255\n \n enum isc_clk_id {\n@@ -190,6 +187,9 @@ struct isc_ctrls {\n  * @gamma_table:\tpointer to the table with gamma values, has\n  *\t\t\tgamma_max sets of GAMMA_ENTRIES entries each\n  * @gamma_max:\t\tmaximum number of sets of inside the gamma_table\n+ *\n+ * @max_width:\t\tmaximum frame width, dependent on the internal RAM\n+ * @max_height:\t\tmaximum frame height, dependent on the internal RAM\n  */\n struct isc_device {\n \tstruct regmap\t\t*regmap;\n@@ -253,6 +253,9 @@ struct isc_device {\n \t/* pointer to the defined gamma table */\n \tconst u32\t(*gamma_table)[GAMMA_ENTRIES];\n \tu32\t\tgamma_max;\n+\n+\tu32\t\tmax_width;\n+\tu32\t\tmax_height;\n };\n \n extern struct isc_format formats_list[];\n--- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c\n+++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c\n@@ -49,8 +49,8 @@\n #include \"atmel-isc-regs.h\"\n #include \"atmel-isc.h\"\n \n-#define ISC_MAX_SUPPORT_WIDTH   2592\n-#define ISC_MAX_SUPPORT_HEIGHT  1944\n+#define ISC_SAMA5D2_MAX_SUPPORT_WIDTH   2592\n+#define ISC_SAMA5D2_MAX_SUPPORT_HEIGHT  1944\n \n #define ISC_CLK_MAX_DIV\t\t255\n \n@@ -216,6 +216,9 @@ static int atmel_isc_probe(struct platfo\n \tisc->gamma_table = isc_sama5d2_gamma_table;\n \tisc->gamma_max = 2;\n \n+\tisc->max_width = ISC_SAMA5D2_MAX_SUPPORT_WIDTH;\n+\tisc->max_height = ISC_SAMA5D2_MAX_SUPPORT_HEIGHT;\n+\n \tret = isc_pipeline_init(isc);\n \tif (ret)\n \t\treturn ret;\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/161-media-atmel-atmel-isc-specialize-dma-cfg.patch",
    "content": "From c42305f52560a1be6fc25a2f23579c7b323de654 Mon Sep 17 00:00:00 2001\nFrom: Eugen Hristev <eugen.hristev@microchip.com>\nDate: Tue, 13 Apr 2021 12:57:03 +0200\nSubject: [PATCH 161/247] media: atmel: atmel-isc: specialize dma cfg\n\nThe dma configuration (DCFG) is specific to the product.\nMove this configuration in the product specific driver, and add the\nfield inside the driver struct.\n\nSigned-off-by: Eugen Hristev <eugen.hristev@microchip.com>\nSigned-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>\nSigned-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>\n---\n drivers/media/platform/atmel/atmel-isc-base.c    | 3 +--\n drivers/media/platform/atmel/atmel-isc.h         | 2 ++\n drivers/media/platform/atmel/atmel-sama5d2-isc.c | 3 +++\n 3 files changed, 6 insertions(+), 2 deletions(-)\n\n--- a/drivers/media/platform/atmel/atmel-isc-base.c\n+++ b/drivers/media/platform/atmel/atmel-isc-base.c\n@@ -724,8 +724,7 @@ static int isc_configure(struct isc_devi\n \trlp_mode = isc->config.rlp_cfg_mode;\n \tpipeline = isc->config.bits_pipeline;\n \n-\tdcfg = isc->config.dcfg_imode |\n-\t\t       ISC_DCFG_YMBSIZE_BEATS8 | ISC_DCFG_CMBSIZE_BEATS8;\n+\tdcfg = isc->config.dcfg_imode | isc->dcfg;\n \n \tpfe_cfg0  |= subdev->pfe_cfg0 | ISC_PFE_CFG0_MODE_PROGRESSIVE;\n \tmask = ISC_PFE_CFG0_BPS_MASK | ISC_PFE_CFG0_HPOL_LOW |\n--- a/drivers/media/platform/atmel/atmel-isc.h\n+++ b/drivers/media/platform/atmel/atmel-isc.h\n@@ -149,6 +149,7 @@ struct isc_ctrls {\n  * @hclock:\t\tHclock clock input (refer datasheet)\n  * @ispck:\t\tiscpck clock (refer datasheet)\n  * @isc_clks:\t\tISC clocks\n+ * @dcfg:\t\tDMA master configuration, architecture dependent\n  *\n  * @dev:\t\tRegistered device driver\n  * @v4l2_dev:\t\tv4l2 registered device\n@@ -196,6 +197,7 @@ struct isc_device {\n \tstruct clk\t\t*hclock;\n \tstruct clk\t\t*ispck;\n \tstruct isc_clk\t\tisc_clks[2];\n+\tu32\t\t\tdcfg;\n \n \tstruct device\t\t*dev;\n \tstruct v4l2_device\tv4l2_dev;\n--- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c\n+++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c\n@@ -219,6 +219,9 @@ static int atmel_isc_probe(struct platfo\n \tisc->max_width = ISC_SAMA5D2_MAX_SUPPORT_WIDTH;\n \tisc->max_height = ISC_SAMA5D2_MAX_SUPPORT_HEIGHT;\n \n+\t/* sama5d2-isc - 8 bits per beat */\n+\tisc->dcfg = ISC_DCFG_YMBSIZE_BEATS8 | ISC_DCFG_CMBSIZE_BEATS8;\n+\n \tret = isc_pipeline_init(isc);\n \tif (ret)\n \t\treturn ret;\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/162-media-atmel-atmel-isc-extract-CSC-submodule-config-i.patch",
    "content": "From 6ccda3cf6a102ac4f6e21386d0dd0fedfb066525 Mon Sep 17 00:00:00 2001\nFrom: Eugen Hristev <eugen.hristev@microchip.com>\nDate: Tue, 13 Apr 2021 12:57:04 +0200\nSubject: [PATCH 162/247] media: atmel: atmel-isc: extract CSC submodule config\n into separate function\n\nThe CSC submodule is a part of the atmel-isc pipeline, and stands for\nColor Space Conversion. It is used to apply a matrix transformation to\nRGB pixels to convert them to the YUV components.\nThe CSC submodule should be initialized in the product specific driver\nas it's product specific. Other products can implement it differently.\n\n[hverkuil: made isc_sama5d2_config_csc static]\n\nSigned-off-by: Eugen Hristev <eugen.hristev@microchip.com>\nSigned-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>\nSigned-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>\n---\n drivers/media/platform/atmel/atmel-isc-base.c    |  8 +-------\n drivers/media/platform/atmel/atmel-isc.h         |  7 +++++++\n drivers/media/platform/atmel/atmel-sama5d2-isc.c | 15 +++++++++++++++\n 3 files changed, 23 insertions(+), 7 deletions(-)\n\n--- a/drivers/media/platform/atmel/atmel-isc-base.c\n+++ b/drivers/media/platform/atmel/atmel-isc-base.c\n@@ -654,13 +654,7 @@ static void isc_set_pipeline(struct isc_\n \tregmap_bulk_write(regmap, ISC_GAM_GENTRY, gamma, GAMMA_ENTRIES);\n \tregmap_bulk_write(regmap, ISC_GAM_RENTRY, gamma, GAMMA_ENTRIES);\n \n-\t/* Convert RGB to YUV */\n-\tregmap_write(regmap, ISC_CSC_YR_YG, 0x42 | (0x81 << 16));\n-\tregmap_write(regmap, ISC_CSC_YB_OY, 0x19 | (0x10 << 16));\n-\tregmap_write(regmap, ISC_CSC_CBR_CBG, 0xFDA | (0xFB6 << 16));\n-\tregmap_write(regmap, ISC_CSC_CBB_OCB, 0x70 | (0x80 << 16));\n-\tregmap_write(regmap, ISC_CSC_CRR_CRG, 0x70 | (0xFA2 << 16));\n-\tregmap_write(regmap, ISC_CSC_CRB_OCR, 0xFEE | (0x80 << 16));\n+\tisc->config_csc(isc);\n \n \tregmap_write(regmap, ISC_CBC_BRIGHT, ctrls->brightness);\n \tregmap_write(regmap, ISC_CBC_CONTRAST, ctrls->contrast);\n--- a/drivers/media/platform/atmel/atmel-isc.h\n+++ b/drivers/media/platform/atmel/atmel-isc.h\n@@ -191,6 +191,9 @@ struct isc_ctrls {\n  *\n  * @max_width:\t\tmaximum frame width, dependent on the internal RAM\n  * @max_height:\t\tmaximum frame height, dependent on the internal RAM\n+ *\n+ * @config_csc:\t\tpointer to a function that initializes product\n+ *\t\t\tspecific CSC module\n  */\n struct isc_device {\n \tstruct regmap\t\t*regmap;\n@@ -258,6 +261,10 @@ struct isc_device {\n \n \tu32\t\tmax_width;\n \tu32\t\tmax_height;\n+\n+\tstruct {\n+\t\tvoid (*config_csc)(struct isc_device *isc);\n+\t};\n };\n \n extern struct isc_format formats_list[];\n--- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c\n+++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c\n@@ -54,6 +54,19 @@\n \n #define ISC_CLK_MAX_DIV\t\t255\n \n+static void isc_sama5d2_config_csc(struct isc_device *isc)\n+{\n+\tstruct regmap *regmap = isc->regmap;\n+\n+\t/* Convert RGB to YUV */\n+\tregmap_write(regmap, ISC_CSC_YR_YG, 0x42 | (0x81 << 16));\n+\tregmap_write(regmap, ISC_CSC_YB_OY, 0x19 | (0x10 << 16));\n+\tregmap_write(regmap, ISC_CSC_CBR_CBG, 0xFDA | (0xFB6 << 16));\n+\tregmap_write(regmap, ISC_CSC_CBB_OCB, 0x70 | (0x80 << 16));\n+\tregmap_write(regmap, ISC_CSC_CRR_CRG, 0x70 | (0xFA2 << 16));\n+\tregmap_write(regmap, ISC_CSC_CRB_OCR, 0xFEE | (0x80 << 16));\n+}\n+\n /* Gamma table with gamma 1/2.2 */\n static const u32 isc_sama5d2_gamma_table[][GAMMA_ENTRIES] = {\n \t/* 0 --> gamma 1/1.8 */\n@@ -219,6 +232,8 @@ static int atmel_isc_probe(struct platfo\n \tisc->max_width = ISC_SAMA5D2_MAX_SUPPORT_WIDTH;\n \tisc->max_height = ISC_SAMA5D2_MAX_SUPPORT_HEIGHT;\n \n+\tisc->config_csc = isc_sama5d2_config_csc;\n+\n \t/* sama5d2-isc - 8 bits per beat */\n \tisc->dcfg = ISC_DCFG_YMBSIZE_BEATS8 | ISC_DCFG_CMBSIZE_BEATS8;\n \n"
  },
  {
    "path": "target/linux/at91/patches-5.10/163-media-atmel-atmel-isc-base-add-id-to-clock-debug-mes.patch",
    "content": "From 19dd7c72c6c457c147133a7dad8ab28d35538f99 Mon Sep 17 00:00:00 2001\nFrom: Eugen Hristev <eugen.hristev@microchip.com>\nDate: Tue, 13 Apr 2021 12:57:05 +0200\nSubject: [PATCH 163/247] media: atmel: atmel-isc-base: add id to clock debug\n message\n\nAdd the clock id to the debug message regarding clock setup\n\nSigned-off-by: Eugen Hristev <eugen.hristev@microchip.com>\nSigned-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>\nSigned-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>\n---\n drivers/media/platform/atmel/atmel-isc-base.c | 4 ++--\n 1 file changed, 2 insertions(+), 2 deletions(-)\n\n--- a/drivers/media/platform/atmel/atmel-isc-base.c\n+++ b/drivers/media/platform/atmel/atmel-isc-base.c\n@@ -281,8 +281,8 @@ static int isc_clk_enable(struct clk_hw\n \tunsigned long flags;\n \tunsigned int status;\n \n-\tdev_dbg(isc_clk->dev, \"ISC CLK: %s, div = %d, parent id = %d\\n\",\n-\t\t__func__, isc_clk->div, isc_clk->parent_id);\n+\tdev_dbg(isc_clk->dev, \"ISC CLK: %s, id = %d, div = %d, parent id = %d\\n\",\n+\t\t__func__, id, isc_clk->div, isc_clk->parent_id);\n \n \tspin_lock_irqsave(&isc_clk->lock, flags);\n \tregmap_update_bits(regmap, ISC_CLKCFG,\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/164-media-atmel-atmel-isc-create-register-offsets-struct.patch",
    "content": "From 7a1b082cd81a2496e2687cee7ea1ef04a3020f48 Mon Sep 17 00:00:00 2001\nFrom: Eugen Hristev <eugen.hristev@microchip.com>\nDate: Tue, 13 Apr 2021 12:57:06 +0200\nSubject: [PATCH 164/247] media: atmel: atmel-isc: create register offsets\n struct\n\nCreate a struct that holds register offsets that are product specific.\nAdd initially the CSC register.\nThis allows each product that contains a variant of the ISC to add their\nown register offset.\n\nSigned-off-by: Eugen Hristev <eugen.hristev@microchip.com>\nSigned-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>\nSigned-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>\n---\n drivers/media/platform/atmel/atmel-isc-base.c |  2 +-\n drivers/media/platform/atmel/atmel-isc-regs.h |  3 +++\n drivers/media/platform/atmel/atmel-isc.h      | 12 +++++++++++\n .../media/platform/atmel/atmel-sama5d2-isc.c  | 20 +++++++++++++------\n 4 files changed, 30 insertions(+), 7 deletions(-)\n\n--- a/drivers/media/platform/atmel/atmel-isc-base.c\n+++ b/drivers/media/platform/atmel/atmel-isc-base.c\n@@ -2326,7 +2326,7 @@ int isc_pipeline_init(struct isc_device\n \t\tREG_FIELD(ISC_GAM_CTRL, 1, 1),\n \t\tREG_FIELD(ISC_GAM_CTRL, 2, 2),\n \t\tREG_FIELD(ISC_GAM_CTRL, 3, 3),\n-\t\tREG_FIELD(ISC_CSC_CTRL, 0, 0),\n+\t\tREG_FIELD(ISC_CSC_CTRL + isc->offsets.csc, 0, 0),\n \t\tREG_FIELD(ISC_CBC_CTRL, 0, 0),\n \t\tREG_FIELD(ISC_SUB422_CTRL, 0, 0),\n \t\tREG_FIELD(ISC_SUB420_CTRL, 0, 0),\n--- a/drivers/media/platform/atmel/atmel-isc-regs.h\n+++ b/drivers/media/platform/atmel/atmel-isc-regs.h\n@@ -153,6 +153,9 @@\n /* ISC_Gamma Correction Green Entry Register */\n #define ISC_GAM_RENTRY\t0x00000298\n \n+/* Offset for CSC register specific to sama5d2 product */\n+#define ISC_SAMA5D2_CSC_OFFSET\t0\n+\n /* Color Space Conversion Control Register */\n #define ISC_CSC_CTRL    0x00000398\n \n--- a/drivers/media/platform/atmel/atmel-isc.h\n+++ b/drivers/media/platform/atmel/atmel-isc.h\n@@ -144,6 +144,14 @@ struct isc_ctrls {\n #define ISC_PIPE_LINE_NODE_NUM\t11\n \n /*\n+ * struct isc_reg_offsets - ISC device register offsets\n+ * @csc:\t\tOffset for the CSC register\n+ */\n+struct isc_reg_offsets {\n+\tu32 csc;\n+};\n+\n+/*\n  * struct isc_device - ISC device driver data/config struct\n  * @regmap:\t\tRegister map\n  * @hclock:\t\tHclock clock input (refer datasheet)\n@@ -194,6 +202,8 @@ struct isc_ctrls {\n  *\n  * @config_csc:\t\tpointer to a function that initializes product\n  *\t\t\tspecific CSC module\n+ *\n+ * @offsets:\t\tstruct holding the product specific register offsets\n  */\n struct isc_device {\n \tstruct regmap\t\t*regmap;\n@@ -265,6 +275,8 @@ struct isc_device {\n \tstruct {\n \t\tvoid (*config_csc)(struct isc_device *isc);\n \t};\n+\n+\tstruct isc_reg_offsets\t\toffsets;\n };\n \n extern struct isc_format formats_list[];\n--- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c\n+++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c\n@@ -59,12 +59,18 @@ static void isc_sama5d2_config_csc(struc\n \tstruct regmap *regmap = isc->regmap;\n \n \t/* Convert RGB to YUV */\n-\tregmap_write(regmap, ISC_CSC_YR_YG, 0x42 | (0x81 << 16));\n-\tregmap_write(regmap, ISC_CSC_YB_OY, 0x19 | (0x10 << 16));\n-\tregmap_write(regmap, ISC_CSC_CBR_CBG, 0xFDA | (0xFB6 << 16));\n-\tregmap_write(regmap, ISC_CSC_CBB_OCB, 0x70 | (0x80 << 16));\n-\tregmap_write(regmap, ISC_CSC_CRR_CRG, 0x70 | (0xFA2 << 16));\n-\tregmap_write(regmap, ISC_CSC_CRB_OCR, 0xFEE | (0x80 << 16));\n+\tregmap_write(regmap, ISC_CSC_YR_YG + isc->offsets.csc,\n+\t\t     0x42 | (0x81 << 16));\n+\tregmap_write(regmap, ISC_CSC_YB_OY + isc->offsets.csc,\n+\t\t     0x19 | (0x10 << 16));\n+\tregmap_write(regmap, ISC_CSC_CBR_CBG + isc->offsets.csc,\n+\t\t     0xFDA | (0xFB6 << 16));\n+\tregmap_write(regmap, ISC_CSC_CBB_OCB + isc->offsets.csc,\n+\t\t     0x70 | (0x80 << 16));\n+\tregmap_write(regmap, ISC_CSC_CRR_CRG + isc->offsets.csc,\n+\t\t     0x70 | (0xFA2 << 16));\n+\tregmap_write(regmap, ISC_CSC_CRB_OCR + isc->offsets.csc,\n+\t\t     0xFEE | (0x80 << 16));\n }\n \n /* Gamma table with gamma 1/2.2 */\n@@ -234,6 +240,8 @@ static int atmel_isc_probe(struct platfo\n \n \tisc->config_csc = isc_sama5d2_config_csc;\n \n+\tisc->offsets.csc = ISC_SAMA5D2_CSC_OFFSET;\n+\n \t/* sama5d2-isc - 8 bits per beat */\n \tisc->dcfg = ISC_DCFG_YMBSIZE_BEATS8 | ISC_DCFG_CMBSIZE_BEATS8;\n \n"
  },
  {
    "path": "target/linux/at91/patches-5.10/165-media-atmel-atmel-isc-extract-CBC-submodule-config-i.patch",
    "content": "From aa31e58d80d233385fa3b972e6b85f293e2a9093 Mon Sep 17 00:00:00 2001\nFrom: Eugen Hristev <eugen.hristev@microchip.com>\nDate: Tue, 13 Apr 2021 12:57:07 +0200\nSubject: [PATCH 165/247] media: atmel: atmel-isc: extract CBC submodule config\n into separate function\n\nThe CBC submodule is a part of the atmel-isc pipeline, and stands for\nContrast Brightness Control. It is used to apply gains and offsets to the\nluma (Y) and chroma (U, V) components of the YUV elements.\nThe CBC submodule should be initialized in the product specific driver\nas it's product specific. Other products can implement it differently\n\n[hverkuil: made isc_sama5d2_config_cbc static]\n\nSigned-off-by: Eugen Hristev <eugen.hristev@microchip.com>\nSigned-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>\nSigned-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>\n---\n drivers/media/platform/atmel/atmel-isc-base.c    | 4 +---\n drivers/media/platform/atmel/atmel-isc.h         | 3 +++\n drivers/media/platform/atmel/atmel-sama5d2-isc.c | 9 +++++++++\n 3 files changed, 13 insertions(+), 3 deletions(-)\n\n--- a/drivers/media/platform/atmel/atmel-isc-base.c\n+++ b/drivers/media/platform/atmel/atmel-isc-base.c\n@@ -655,9 +655,7 @@ static void isc_set_pipeline(struct isc_\n \tregmap_bulk_write(regmap, ISC_GAM_RENTRY, gamma, GAMMA_ENTRIES);\n \n \tisc->config_csc(isc);\n-\n-\tregmap_write(regmap, ISC_CBC_BRIGHT, ctrls->brightness);\n-\tregmap_write(regmap, ISC_CBC_CONTRAST, ctrls->contrast);\n+\tisc->config_cbc(isc);\n }\n \n static int isc_update_profile(struct isc_device *isc)\n--- a/drivers/media/platform/atmel/atmel-isc.h\n+++ b/drivers/media/platform/atmel/atmel-isc.h\n@@ -202,6 +202,8 @@ struct isc_reg_offsets {\n  *\n  * @config_csc:\t\tpointer to a function that initializes product\n  *\t\t\tspecific CSC module\n+ * @config_cbc:\t\tpointer to a function that initializes product\n+ *\t\t\tspecific CBC module\n  *\n  * @offsets:\t\tstruct holding the product specific register offsets\n  */\n@@ -274,6 +276,7 @@ struct isc_device {\n \n \tstruct {\n \t\tvoid (*config_csc)(struct isc_device *isc);\n+\t\tvoid (*config_cbc)(struct isc_device *isc);\n \t};\n \n \tstruct isc_reg_offsets\t\toffsets;\n--- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c\n+++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c\n@@ -73,6 +73,14 @@ static void isc_sama5d2_config_csc(struc\n \t\t     0xFEE | (0x80 << 16));\n }\n \n+static void isc_sama5d2_config_cbc(struct isc_device *isc)\n+{\n+\tstruct regmap *regmap = isc->regmap;\n+\n+\tregmap_write(regmap, ISC_CBC_BRIGHT, isc->ctrls.brightness);\n+\tregmap_write(regmap, ISC_CBC_CONTRAST, isc->ctrls.contrast);\n+}\n+\n /* Gamma table with gamma 1/2.2 */\n static const u32 isc_sama5d2_gamma_table[][GAMMA_ENTRIES] = {\n \t/* 0 --> gamma 1/1.8 */\n@@ -239,6 +247,7 @@ static int atmel_isc_probe(struct platfo\n \tisc->max_height = ISC_SAMA5D2_MAX_SUPPORT_HEIGHT;\n \n \tisc->config_csc = isc_sama5d2_config_csc;\n+\tisc->config_cbc = isc_sama5d2_config_cbc;\n \n \tisc->offsets.csc = ISC_SAMA5D2_CSC_OFFSET;\n \n"
  },
  {
    "path": "target/linux/at91/patches-5.10/166-media-atmel-atmel-isc-add-CBC-to-the-reg-offsets-str.patch",
    "content": "From 52e4b779ae1af3e322d0c673375dcd51315739d4 Mon Sep 17 00:00:00 2001\nFrom: Eugen Hristev <eugen.hristev@microchip.com>\nDate: Tue, 13 Apr 2021 12:57:08 +0200\nSubject: [PATCH 166/247] media: atmel: atmel-isc: add CBC to the reg offsets\n struct\n\nThe CBC submodule is a part of the atmel-isc pipeline, and stands for\nContrast Brightness Control. It is used to apply gains and offsets to the\nluma (Y) and chroma (U, V) components of the YUV elements.\nAdd cbc to the reg offsets struct. This will allow different products\nto have a different reg offset for this particular module.\n\nSigned-off-by: Eugen Hristev <eugen.hristev@microchip.com>\nSigned-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>\nSigned-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>\n---\n drivers/media/platform/atmel/atmel-isc-base.c    | 2 +-\n drivers/media/platform/atmel/atmel-isc-regs.h    | 3 +++\n drivers/media/platform/atmel/atmel-isc.h         | 2 ++\n drivers/media/platform/atmel/atmel-sama5d2-isc.c | 7 +++++--\n 4 files changed, 11 insertions(+), 3 deletions(-)\n\n--- a/drivers/media/platform/atmel/atmel-isc-base.c\n+++ b/drivers/media/platform/atmel/atmel-isc-base.c\n@@ -2325,7 +2325,7 @@ int isc_pipeline_init(struct isc_device\n \t\tREG_FIELD(ISC_GAM_CTRL, 2, 2),\n \t\tREG_FIELD(ISC_GAM_CTRL, 3, 3),\n \t\tREG_FIELD(ISC_CSC_CTRL + isc->offsets.csc, 0, 0),\n-\t\tREG_FIELD(ISC_CBC_CTRL, 0, 0),\n+\t\tREG_FIELD(ISC_CBC_CTRL + isc->offsets.cbc, 0, 0),\n \t\tREG_FIELD(ISC_SUB422_CTRL, 0, 0),\n \t\tREG_FIELD(ISC_SUB420_CTRL, 0, 0),\n \t};\n--- a/drivers/media/platform/atmel/atmel-isc-regs.h\n+++ b/drivers/media/platform/atmel/atmel-isc-regs.h\n@@ -177,6 +177,9 @@\n /* Color Space Conversion CRB OCR Register */\n #define ISC_CSC_CRB_OCR\t0x000003b0\n \n+/* Offset for CBC register specific to sama5d2 product */\n+#define ISC_SAMA5D2_CBC_OFFSET\t0\n+\n /* Contrast And Brightness Control Register */\n #define ISC_CBC_CTRL    0x000003b4\n \n--- a/drivers/media/platform/atmel/atmel-isc.h\n+++ b/drivers/media/platform/atmel/atmel-isc.h\n@@ -146,9 +146,11 @@ struct isc_ctrls {\n /*\n  * struct isc_reg_offsets - ISC device register offsets\n  * @csc:\t\tOffset for the CSC register\n+ * @cbc:\t\tOffset for the CBC register\n  */\n struct isc_reg_offsets {\n \tu32 csc;\n+\tu32 cbc;\n };\n \n /*\n--- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c\n+++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c\n@@ -77,8 +77,10 @@ static void isc_sama5d2_config_cbc(struc\n {\n \tstruct regmap *regmap = isc->regmap;\n \n-\tregmap_write(regmap, ISC_CBC_BRIGHT, isc->ctrls.brightness);\n-\tregmap_write(regmap, ISC_CBC_CONTRAST, isc->ctrls.contrast);\n+\tregmap_write(regmap, ISC_CBC_BRIGHT + isc->offsets.cbc,\n+\t\t     isc->ctrls.brightness);\n+\tregmap_write(regmap, ISC_CBC_CONTRAST + isc->offsets.cbc,\n+\t\t     isc->ctrls.contrast);\n }\n \n /* Gamma table with gamma 1/2.2 */\n@@ -250,6 +252,7 @@ static int atmel_isc_probe(struct platfo\n \tisc->config_cbc = isc_sama5d2_config_cbc;\n \n \tisc->offsets.csc = ISC_SAMA5D2_CSC_OFFSET;\n+\tisc->offsets.cbc = ISC_SAMA5D2_CBC_OFFSET;\n \n \t/* sama5d2-isc - 8 bits per beat */\n \tisc->dcfg = ISC_DCFG_YMBSIZE_BEATS8 | ISC_DCFG_CMBSIZE_BEATS8;\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/167-media-atmel-atmel-isc-add-SUB422-and-SUB420-to-regis.patch",
    "content": "From aebb741058a63c3493f4139d11d6f290d5691e9b Mon Sep 17 00:00:00 2001\nFrom: Eugen Hristev <eugen.hristev@microchip.com>\nDate: Tue, 13 Apr 2021 12:57:09 +0200\nSubject: [PATCH 167/247] media: atmel: atmel-isc: add SUB422 and SUB420 to\n register offsets\n\nThe SUB submodules are a part of the atmel-isc pipeline, and stand for\nSubsampling. They are used to subsample the original YUV 4:4:4 pixel ratio\naspect to either 4:2:2 or 4:2:0.\nAdd sub420 and sub422 to the reg offsets struct.\nThis will allow different products to have a different reg offset for these\nparticular modules.\n\nSigned-off-by: Eugen Hristev <eugen.hristev@microchip.com>\nSigned-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>\nSigned-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>\n---\n drivers/media/platform/atmel/atmel-isc-base.c    | 4 ++--\n drivers/media/platform/atmel/atmel-isc-regs.h    | 4 ++++\n drivers/media/platform/atmel/atmel-isc.h         | 4 ++++\n drivers/media/platform/atmel/atmel-sama5d2-isc.c | 2 ++\n 4 files changed, 12 insertions(+), 2 deletions(-)\n\n--- a/drivers/media/platform/atmel/atmel-isc-base.c\n+++ b/drivers/media/platform/atmel/atmel-isc-base.c\n@@ -2326,8 +2326,8 @@ int isc_pipeline_init(struct isc_device\n \t\tREG_FIELD(ISC_GAM_CTRL, 3, 3),\n \t\tREG_FIELD(ISC_CSC_CTRL + isc->offsets.csc, 0, 0),\n \t\tREG_FIELD(ISC_CBC_CTRL + isc->offsets.cbc, 0, 0),\n-\t\tREG_FIELD(ISC_SUB422_CTRL, 0, 0),\n-\t\tREG_FIELD(ISC_SUB420_CTRL, 0, 0),\n+\t\tREG_FIELD(ISC_SUB422_CTRL + isc->offsets.sub422, 0, 0),\n+\t\tREG_FIELD(ISC_SUB420_CTRL + isc->offsets.sub420, 0, 0),\n \t};\n \n \tfor (i = 0; i < ISC_PIPE_LINE_NODE_NUM; i++) {\n--- a/drivers/media/platform/atmel/atmel-isc-regs.h\n+++ b/drivers/media/platform/atmel/atmel-isc-regs.h\n@@ -194,9 +194,13 @@\n #define ISC_CBC_CONTRAST\t0x000003c0\n #define ISC_CBC_CONTRAST_MASK\tGENMASK(11, 0)\n \n+/* Offset for SUB422 register specific to sama5d2 product */\n+#define ISC_SAMA5D2_SUB422_OFFSET\t0\n /* Subsampling 4:4:4 to 4:2:2 Control Register */\n #define ISC_SUB422_CTRL 0x000003c4\n \n+/* Offset for SUB420 register specific to sama5d2 product */\n+#define ISC_SAMA5D2_SUB420_OFFSET\t0\n /* Subsampling 4:2:2 to 4:2:0 Control Register */\n #define ISC_SUB420_CTRL 0x000003cc\n \n--- a/drivers/media/platform/atmel/atmel-isc.h\n+++ b/drivers/media/platform/atmel/atmel-isc.h\n@@ -147,10 +147,14 @@ struct isc_ctrls {\n  * struct isc_reg_offsets - ISC device register offsets\n  * @csc:\t\tOffset for the CSC register\n  * @cbc:\t\tOffset for the CBC register\n+ * @sub422:\t\tOffset for the SUB422 register\n+ * @sub420:\t\tOffset for the SUB420 register\n  */\n struct isc_reg_offsets {\n \tu32 csc;\n \tu32 cbc;\n+\tu32 sub422;\n+\tu32 sub420;\n };\n \n /*\n--- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c\n+++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c\n@@ -253,6 +253,8 @@ static int atmel_isc_probe(struct platfo\n \n \tisc->offsets.csc = ISC_SAMA5D2_CSC_OFFSET;\n \tisc->offsets.cbc = ISC_SAMA5D2_CBC_OFFSET;\n+\tisc->offsets.sub422 = ISC_SAMA5D2_SUB422_OFFSET;\n+\tisc->offsets.sub420 = ISC_SAMA5D2_SUB420_OFFSET;\n \n \t/* sama5d2-isc - 8 bits per beat */\n \tisc->dcfg = ISC_DCFG_YMBSIZE_BEATS8 | ISC_DCFG_CMBSIZE_BEATS8;\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/168-media-atmel-atmel-isc-add-RLP-to-register-offsets.patch",
    "content": "From b432a8b0fc88de5b49236482053d8d372c68ee55 Mon Sep 17 00:00:00 2001\nFrom: Eugen Hristev <eugen.hristev@microchip.com>\nDate: Tue, 13 Apr 2021 12:57:10 +0200\nSubject: [PATCH 168/247] media: atmel: atmel-isc: add RLP to register offsets\n\nThe RLP submodule is a part of the atmel-isc pipeline, and stands for\nRounding,Limiting and Packaging. It used to extract specific data from the\nISC pipeline. For example if we want to output greyscale 8 bit, we would\nuse limiting to 8 bits, and packaging to Luma component only.\nAdd rlp to the reg offsets struct.\nThis will allow different products to have a different reg offset for this\nparticular module.\n\nSigned-off-by: Eugen Hristev <eugen.hristev@microchip.com>\nSigned-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>\nSigned-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>\n---\n drivers/media/platform/atmel/atmel-isc-base.c    | 4 ++--\n drivers/media/platform/atmel/atmel-isc-regs.h    | 2 ++\n drivers/media/platform/atmel/atmel-isc.h         | 2 ++\n drivers/media/platform/atmel/atmel-sama5d2-isc.c | 1 +\n 4 files changed, 7 insertions(+), 2 deletions(-)\n\n--- a/drivers/media/platform/atmel/atmel-isc-base.c\n+++ b/drivers/media/platform/atmel/atmel-isc-base.c\n@@ -726,8 +726,8 @@ static int isc_configure(struct isc_devi\n \n \tregmap_update_bits(regmap, ISC_PFE_CFG0, mask, pfe_cfg0);\n \n-\tregmap_update_bits(regmap, ISC_RLP_CFG, ISC_RLP_CFG_MODE_MASK,\n-\t\t\t   rlp_mode);\n+\tregmap_update_bits(regmap, ISC_RLP_CFG + isc->offsets.rlp,\n+\t\t\t   ISC_RLP_CFG_MODE_MASK, rlp_mode);\n \n \tregmap_write(regmap, ISC_DCFG, dcfg);\n \n--- a/drivers/media/platform/atmel/atmel-isc-regs.h\n+++ b/drivers/media/platform/atmel/atmel-isc-regs.h\n@@ -204,6 +204,8 @@\n /* Subsampling 4:2:2 to 4:2:0 Control Register */\n #define ISC_SUB420_CTRL 0x000003cc\n \n+/* Offset for RLP register specific to sama5d2 product */\n+#define ISC_SAMA5D2_RLP_OFFSET\t0\n /* Rounding, Limiting and Packing Configuration Register */\n #define ISC_RLP_CFG     0x000003d0\n \n--- a/drivers/media/platform/atmel/atmel-isc.h\n+++ b/drivers/media/platform/atmel/atmel-isc.h\n@@ -149,12 +149,14 @@ struct isc_ctrls {\n  * @cbc:\t\tOffset for the CBC register\n  * @sub422:\t\tOffset for the SUB422 register\n  * @sub420:\t\tOffset for the SUB420 register\n+ * @rlp:\t\tOffset for the RLP register\n  */\n struct isc_reg_offsets {\n \tu32 csc;\n \tu32 cbc;\n \tu32 sub422;\n \tu32 sub420;\n+\tu32 rlp;\n };\n \n /*\n--- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c\n+++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c\n@@ -255,6 +255,7 @@ static int atmel_isc_probe(struct platfo\n \tisc->offsets.cbc = ISC_SAMA5D2_CBC_OFFSET;\n \tisc->offsets.sub422 = ISC_SAMA5D2_SUB422_OFFSET;\n \tisc->offsets.sub420 = ISC_SAMA5D2_SUB420_OFFSET;\n+\tisc->offsets.rlp = ISC_SAMA5D2_RLP_OFFSET;\n \n \t/* sama5d2-isc - 8 bits per beat */\n \tisc->dcfg = ISC_DCFG_YMBSIZE_BEATS8 | ISC_DCFG_CMBSIZE_BEATS8;\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/169-media-atmel-atmel-isc-add-HIS-to-register-offsets.patch",
    "content": "From 8c19aa14b8303a0e7c4bae42f3f00f9a2a65b0db Mon Sep 17 00:00:00 2001\nFrom: Eugen Hristev <eugen.hristev@microchip.com>\nDate: Tue, 13 Apr 2021 12:57:11 +0200\nSubject: [PATCH 169/247] media: atmel: atmel-isc: add HIS to register offsets\n\nThe HIS submodule is a part of the atmel-isc pipeline, and stands for\nHistogram. This module performs a color histogram that can be read and used\nby the main processor.\nAdd his to the reg offsets struct.\nThis will allow different products to have a different reg offset for this\nparticular module.\n\nSigned-off-by: Eugen Hristev <eugen.hristev@microchip.com>\nSigned-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>\nSigned-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>\n---\n drivers/media/platform/atmel/atmel-isc-base.c    | 11 +++++++----\n drivers/media/platform/atmel/atmel-isc-regs.h    |  2 ++\n drivers/media/platform/atmel/atmel-isc.h         |  2 ++\n drivers/media/platform/atmel/atmel-sama5d2-isc.c |  1 +\n 4 files changed, 12 insertions(+), 4 deletions(-)\n\n--- a/drivers/media/platform/atmel/atmel-isc-base.c\n+++ b/drivers/media/platform/atmel/atmel-isc-base.c\n@@ -686,12 +686,13 @@ static void isc_set_histogram(struct isc\n \tstruct isc_ctrls *ctrls = &isc->ctrls;\n \n \tif (enable) {\n-\t\tregmap_write(regmap, ISC_HIS_CFG,\n+\t\tregmap_write(regmap, ISC_HIS_CFG + isc->offsets.his,\n \t\t\t     ISC_HIS_CFG_MODE_GR |\n \t\t\t     (isc->config.sd_format->cfa_baycfg\n \t\t\t\t\t<< ISC_HIS_CFG_BAYSEL_SHIFT) |\n \t\t\t\t\tISC_HIS_CFG_RAR);\n-\t\tregmap_write(regmap, ISC_HIS_CTRL, ISC_HIS_CTRL_EN);\n+\t\tregmap_write(regmap, ISC_HIS_CTRL + isc->offsets.his,\n+\t\t\t     ISC_HIS_CTRL_EN);\n \t\tregmap_write(regmap, ISC_INTEN, ISC_INT_HISDONE);\n \t\tctrls->hist_id = ISC_HIS_CFG_MODE_GR;\n \t\tisc_update_profile(isc);\n@@ -700,7 +701,8 @@ static void isc_set_histogram(struct isc\n \t\tctrls->hist_stat = HIST_ENABLED;\n \t} else {\n \t\tregmap_write(regmap, ISC_INTDIS, ISC_INT_HISDONE);\n-\t\tregmap_write(regmap, ISC_HIS_CTRL, ISC_HIS_CTRL_DIS);\n+\t\tregmap_write(regmap, ISC_HIS_CTRL + isc->offsets.his,\n+\t\t\t     ISC_HIS_CTRL_DIS);\n \n \t\tctrls->hist_stat = HIST_DISABLED;\n \t}\n@@ -1836,7 +1838,8 @@ static void isc_awb_work(struct work_str\n \t\t\tctrls->awb = ISC_WB_NONE;\n \t\t}\n \t}\n-\tregmap_write(regmap, ISC_HIS_CFG, hist_id | baysel | ISC_HIS_CFG_RAR);\n+\tregmap_write(regmap, ISC_HIS_CFG + isc->offsets.his,\n+\t\t     hist_id | baysel | ISC_HIS_CFG_RAR);\n \tisc_update_profile(isc);\n \t/* if awb has been disabled, we don't need to start another histogram */\n \tif (ctrls->awb)\n--- a/drivers/media/platform/atmel/atmel-isc-regs.h\n+++ b/drivers/media/platform/atmel/atmel-isc-regs.h\n@@ -224,6 +224,8 @@\n #define ISC_RLP_CFG_MODE_YYCC_LIMITED   0xc\n #define ISC_RLP_CFG_MODE_MASK           GENMASK(3, 0)\n \n+/* Offset for HIS register specific to sama5d2 product */\n+#define ISC_SAMA5D2_HIS_OFFSET\t0\n /* Histogram Control Register */\n #define ISC_HIS_CTRL\t0x000003d4\n \n--- a/drivers/media/platform/atmel/atmel-isc.h\n+++ b/drivers/media/platform/atmel/atmel-isc.h\n@@ -150,6 +150,7 @@ struct isc_ctrls {\n  * @sub422:\t\tOffset for the SUB422 register\n  * @sub420:\t\tOffset for the SUB420 register\n  * @rlp:\t\tOffset for the RLP register\n+ * @his:\t\tOffset for the HIS related registers\n  */\n struct isc_reg_offsets {\n \tu32 csc;\n@@ -157,6 +158,7 @@ struct isc_reg_offsets {\n \tu32 sub422;\n \tu32 sub420;\n \tu32 rlp;\n+\tu32 his;\n };\n \n /*\n--- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c\n+++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c\n@@ -256,6 +256,7 @@ static int atmel_isc_probe(struct platfo\n \tisc->offsets.sub422 = ISC_SAMA5D2_SUB422_OFFSET;\n \tisc->offsets.sub420 = ISC_SAMA5D2_SUB420_OFFSET;\n \tisc->offsets.rlp = ISC_SAMA5D2_RLP_OFFSET;\n+\tisc->offsets.his = ISC_SAMA5D2_HIS_OFFSET;\n \n \t/* sama5d2-isc - 8 bits per beat */\n \tisc->dcfg = ISC_DCFG_YMBSIZE_BEATS8 | ISC_DCFG_CMBSIZE_BEATS8;\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/170-media-atmel-atmel-isc-add-DMA-to-register-offsets.patch",
    "content": "From 7173e54070a9b530c8c16e0a507be71385133abd Mon Sep 17 00:00:00 2001\nFrom: Eugen Hristev <eugen.hristev@microchip.com>\nDate: Tue, 13 Apr 2021 12:57:12 +0200\nSubject: [PATCH 170/247] media: atmel: atmel-isc: add DMA to register offsets\n\nThe DMA submodule is a part of the atmel-isc pipeline, and stands for\nDirect Memory Access. It acts like a master on the AXI bus of the SoC, and\ncan directly write the RAM area with the pixel data from the ISC internal\nsram.\nAdd dma to the reg offsets struct.\nThis will allow different products to have a different reg offset for this\nparticular module.\n\nSigned-off-by: Eugen Hristev <eugen.hristev@microchip.com>\nSigned-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>\nSigned-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>\n---\n drivers/media/platform/atmel/atmel-isc-base.c | 19 ++++++++++++-------\n drivers/media/platform/atmel/atmel-isc-regs.h |  3 +++\n drivers/media/platform/atmel/atmel-isc.h      |  2 ++\n .../media/platform/atmel/atmel-sama5d2-isc.c  |  1 +\n 4 files changed, 18 insertions(+), 7 deletions(-)\n\n--- a/drivers/media/platform/atmel/atmel-isc-base.c\n+++ b/drivers/media/platform/atmel/atmel-isc-base.c\n@@ -601,16 +601,20 @@ static void isc_start_dma(struct isc_dev\n \t\t\t   ISC_PFE_CFG0_COLEN | ISC_PFE_CFG0_ROWEN);\n \n \taddr0 = vb2_dma_contig_plane_dma_addr(&isc->cur_frm->vb.vb2_buf, 0);\n-\tregmap_write(regmap, ISC_DAD0, addr0);\n+\tregmap_write(regmap, ISC_DAD0 + isc->offsets.dma, addr0);\n \n \tswitch (isc->config.fourcc) {\n \tcase V4L2_PIX_FMT_YUV420:\n-\t\tregmap_write(regmap, ISC_DAD1, addr0 + (sizeimage * 2) / 3);\n-\t\tregmap_write(regmap, ISC_DAD2, addr0 + (sizeimage * 5) / 6);\n+\t\tregmap_write(regmap, ISC_DAD1 + isc->offsets.dma,\n+\t\t\t     addr0 + (sizeimage * 2) / 3);\n+\t\tregmap_write(regmap, ISC_DAD2 + isc->offsets.dma,\n+\t\t\t     addr0 + (sizeimage * 5) / 6);\n \t\tbreak;\n \tcase V4L2_PIX_FMT_YUV422P:\n-\t\tregmap_write(regmap, ISC_DAD1, addr0 + sizeimage / 2);\n-\t\tregmap_write(regmap, ISC_DAD2, addr0 + (sizeimage * 3) / 4);\n+\t\tregmap_write(regmap, ISC_DAD1 + isc->offsets.dma,\n+\t\t\t     addr0 + sizeimage / 2);\n+\t\tregmap_write(regmap, ISC_DAD2 + isc->offsets.dma,\n+\t\t\t     addr0 + (sizeimage * 3) / 4);\n \t\tbreak;\n \tdefault:\n \t\tbreak;\n@@ -618,7 +622,8 @@ static void isc_start_dma(struct isc_dev\n \n \tdctrl_dview = isc->config.dctrl_dview;\n \n-\tregmap_write(regmap, ISC_DCTRL, dctrl_dview | ISC_DCTRL_IE_IS);\n+\tregmap_write(regmap, ISC_DCTRL + isc->offsets.dma,\n+\t\t     dctrl_dview | ISC_DCTRL_IE_IS);\n \tspin_lock(&isc->awb_lock);\n \tregmap_write(regmap, ISC_CTRLEN, ISC_CTRL_CAPTURE);\n \tspin_unlock(&isc->awb_lock);\n@@ -731,7 +736,7 @@ static int isc_configure(struct isc_devi\n \tregmap_update_bits(regmap, ISC_RLP_CFG + isc->offsets.rlp,\n \t\t\t   ISC_RLP_CFG_MODE_MASK, rlp_mode);\n \n-\tregmap_write(regmap, ISC_DCFG, dcfg);\n+\tregmap_write(regmap, ISC_DCFG + isc->offsets.dma, dcfg);\n \n \t/* Set the pipeline */\n \tisc_set_pipeline(isc, pipeline);\n--- a/drivers/media/platform/atmel/atmel-isc-regs.h\n+++ b/drivers/media/platform/atmel/atmel-isc-regs.h\n@@ -247,6 +247,9 @@\n \n #define ISC_HIS_CFG_RAR\t\t\tBIT(8)\n \n+/* Offset for DMA register specific to sama5d2 product */\n+#define ISC_SAMA5D2_DMA_OFFSET\t0\n+\n /* DMA Configuration Register */\n #define ISC_DCFG        0x000003e0\n #define ISC_DCFG_IMODE_PACKED8          0x0\n--- a/drivers/media/platform/atmel/atmel-isc.h\n+++ b/drivers/media/platform/atmel/atmel-isc.h\n@@ -151,6 +151,7 @@ struct isc_ctrls {\n  * @sub420:\t\tOffset for the SUB420 register\n  * @rlp:\t\tOffset for the RLP register\n  * @his:\t\tOffset for the HIS related registers\n+ * @dma:\t\tOffset for the DMA related registers\n  */\n struct isc_reg_offsets {\n \tu32 csc;\n@@ -159,6 +160,7 @@ struct isc_reg_offsets {\n \tu32 sub420;\n \tu32 rlp;\n \tu32 his;\n+\tu32 dma;\n };\n \n /*\n--- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c\n+++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c\n@@ -257,6 +257,7 @@ static int atmel_isc_probe(struct platfo\n \tisc->offsets.sub420 = ISC_SAMA5D2_SUB420_OFFSET;\n \tisc->offsets.rlp = ISC_SAMA5D2_RLP_OFFSET;\n \tisc->offsets.his = ISC_SAMA5D2_HIS_OFFSET;\n+\tisc->offsets.dma = ISC_SAMA5D2_DMA_OFFSET;\n \n \t/* sama5d2-isc - 8 bits per beat */\n \tisc->dcfg = ISC_DCFG_YMBSIZE_BEATS8 | ISC_DCFG_CMBSIZE_BEATS8;\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/171-media-atmel-atmel-isc-add-support-for-version-regist.patch",
    "content": "From 0939b0a92acca11a5a3b0de5dd70434e17e40ed3 Mon Sep 17 00:00:00 2001\nFrom: Eugen Hristev <eugen.hristev@microchip.com>\nDate: Tue, 13 Apr 2021 12:57:13 +0200\nSubject: [PATCH 171/247] media: atmel: atmel-isc: add support for version\n register\n\nAdd support for version register and print it at probe time.\n\nSigned-off-by: Eugen Hristev <eugen.hristev@microchip.com>\nSigned-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>\nSigned-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>\n---\n drivers/media/platform/atmel/atmel-isc-regs.h    | 5 +++++\n drivers/media/platform/atmel/atmel-isc.h         | 2 ++\n drivers/media/platform/atmel/atmel-sama5d2-isc.c | 5 +++++\n 3 files changed, 12 insertions(+)\n\n--- a/drivers/media/platform/atmel/atmel-isc-regs.h\n+++ b/drivers/media/platform/atmel/atmel-isc-regs.h\n@@ -295,6 +295,11 @@\n /* DMA Address 2 Register */\n #define ISC_DAD2        0x000003fc\n \n+/* Offset for version register specific to sama5d2 product */\n+#define ISC_SAMA5D2_VERSION_OFFSET\t0\n+/* Version Register */\n+#define ISC_VERSION\t0x0000040c\n+\n /* Histogram Entry */\n #define ISC_HIS_ENTRY\t0x00000410\n \n--- a/drivers/media/platform/atmel/atmel-isc.h\n+++ b/drivers/media/platform/atmel/atmel-isc.h\n@@ -152,6 +152,7 @@ struct isc_ctrls {\n  * @rlp:\t\tOffset for the RLP register\n  * @his:\t\tOffset for the HIS related registers\n  * @dma:\t\tOffset for the DMA related registers\n+ * @version:\t\tOffset for the version register\n  */\n struct isc_reg_offsets {\n \tu32 csc;\n@@ -161,6 +162,7 @@ struct isc_reg_offsets {\n \tu32 rlp;\n \tu32 his;\n \tu32 dma;\n+\tu32 version;\n };\n \n /*\n--- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c\n+++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c\n@@ -210,6 +210,7 @@ static int atmel_isc_probe(struct platfo\n \tstruct isc_subdev_entity *subdev_entity;\n \tint irq;\n \tint ret;\n+\tu32 ver;\n \n \tisc = devm_kzalloc(dev, sizeof(*isc), GFP_KERNEL);\n \tif (!isc)\n@@ -258,6 +259,7 @@ static int atmel_isc_probe(struct platfo\n \tisc->offsets.rlp = ISC_SAMA5D2_RLP_OFFSET;\n \tisc->offsets.his = ISC_SAMA5D2_HIS_OFFSET;\n \tisc->offsets.dma = ISC_SAMA5D2_DMA_OFFSET;\n+\tisc->offsets.version = ISC_SAMA5D2_VERSION_OFFSET;\n \n \t/* sama5d2-isc - 8 bits per beat */\n \tisc->dcfg = ISC_DCFG_YMBSIZE_BEATS8 | ISC_DCFG_CMBSIZE_BEATS8;\n@@ -346,6 +348,9 @@ static int atmel_isc_probe(struct platfo\n \tpm_runtime_enable(dev);\n \tpm_request_idle(dev);\n \n+\tregmap_read(isc->regmap, ISC_VERSION + isc->offsets.version, &ver);\n+\tdev_info(dev, \"Microchip ISC version %x\\n\", ver);\n+\n \treturn 0;\n \n cleanup_subdev:\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/172-media-atmel-atmel-isc-add-his_entry-to-register-offs.patch",
    "content": "From bce46a8a620a796ca3cfe5bff61baf6744074986 Mon Sep 17 00:00:00 2001\nFrom: Eugen Hristev <eugen.hristev@microchip.com>\nDate: Tue, 13 Apr 2021 12:57:14 +0200\nSubject: [PATCH 172/247] media: atmel: atmel-isc: add his_entry to register\n offsets\n\nAdd his_entry to the reg offsets struct.\nThis will allow different products to have a different reg offset for this\nparticular module.\n\nSigned-off-by: Eugen Hristev <eugen.hristev@microchip.com>\nSigned-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>\nSigned-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>\n---\n drivers/media/platform/atmel/atmel-isc-base.c    | 3 ++-\n drivers/media/platform/atmel/atmel-isc-regs.h    | 2 ++\n drivers/media/platform/atmel/atmel-isc.h         | 2 ++\n drivers/media/platform/atmel/atmel-sama5d2-isc.c | 1 +\n 4 files changed, 7 insertions(+), 1 deletion(-)\n\n--- a/drivers/media/platform/atmel/atmel-isc-base.c\n+++ b/drivers/media/platform/atmel/atmel-isc-base.c\n@@ -1684,7 +1684,8 @@ static void isc_hist_count(struct isc_de\n \t*min = 0;\n \t*max = HIST_ENTRIES;\n \n-\tregmap_bulk_read(regmap, ISC_HIS_ENTRY, hist_entry, HIST_ENTRIES);\n+\tregmap_bulk_read(regmap, ISC_HIS_ENTRY + isc->offsets.his_entry,\n+\t\t\t hist_entry, HIST_ENTRIES);\n \n \t*hist_count = 0;\n \t/*\n--- a/drivers/media/platform/atmel/atmel-isc-regs.h\n+++ b/drivers/media/platform/atmel/atmel-isc-regs.h\n@@ -300,6 +300,8 @@\n /* Version Register */\n #define ISC_VERSION\t0x0000040c\n \n+/* Offset for version register specific to sama5d2 product */\n+#define ISC_SAMA5D2_HIS_ENTRY_OFFSET\t0\n /* Histogram Entry */\n #define ISC_HIS_ENTRY\t0x00000410\n \n--- a/drivers/media/platform/atmel/atmel-isc.h\n+++ b/drivers/media/platform/atmel/atmel-isc.h\n@@ -153,6 +153,7 @@ struct isc_ctrls {\n  * @his:\t\tOffset for the HIS related registers\n  * @dma:\t\tOffset for the DMA related registers\n  * @version:\t\tOffset for the version register\n+ * @his_entry:\t\tOffset for the HIS entries registers\n  */\n struct isc_reg_offsets {\n \tu32 csc;\n@@ -163,6 +164,7 @@ struct isc_reg_offsets {\n \tu32 his;\n \tu32 dma;\n \tu32 version;\n+\tu32 his_entry;\n };\n \n /*\n--- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c\n+++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c\n@@ -260,6 +260,7 @@ static int atmel_isc_probe(struct platfo\n \tisc->offsets.his = ISC_SAMA5D2_HIS_OFFSET;\n \tisc->offsets.dma = ISC_SAMA5D2_DMA_OFFSET;\n \tisc->offsets.version = ISC_SAMA5D2_VERSION_OFFSET;\n+\tisc->offsets.his_entry = ISC_SAMA5D2_HIS_ENTRY_OFFSET;\n \n \t/* sama5d2-isc - 8 bits per beat */\n \tisc->dcfg = ISC_DCFG_YMBSIZE_BEATS8 | ISC_DCFG_CMBSIZE_BEATS8;\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/173-media-atmel-atmel-isc-add-register-description-for-a.patch",
    "content": "From 87b581b1197df5f77bd65819d0428f2404c6b764 Mon Sep 17 00:00:00 2001\nFrom: Eugen Hristev <eugen.hristev@microchip.com>\nDate: Tue, 13 Apr 2021 12:57:15 +0200\nSubject: [PATCH 173/247] media: atmel: atmel-isc: add register description for\n additional modules\n\nAdd register description for additional pipeline modules: the\nDefective Pixel Correction (DPC) and the Vertical and Horizontal Scaler(VHXS)\n\nSigned-off-by: Eugen Hristev <eugen.hristev@microchip.com>\nSigned-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>\nSigned-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>\n---\n drivers/media/platform/atmel/atmel-isc-regs.h | 67 +++++++++++++++++++\n 1 file changed, 67 insertions(+)\n\n--- a/drivers/media/platform/atmel/atmel-isc-regs.h\n+++ b/drivers/media/platform/atmel/atmel-isc-regs.h\n@@ -90,6 +90,46 @@\n #define ISC_INT_DDONE\t\tBIT(8)\n #define ISC_INT_HISDONE\t\tBIT(12)\n \n+/* ISC DPC Control Register */\n+#define ISC_DPC_CTRL\t0x40\n+\n+#define ISC_DPC_CTRL_DPCEN\tBIT(0)\n+#define ISC_DPC_CTRL_GDCEN\tBIT(1)\n+#define ISC_DPC_CTRL_BLCEN\tBIT(2)\n+\n+/* ISC DPC Config Register */\n+#define ISC_DPC_CFG\t0x44\n+\n+#define ISC_DPC_CFG_BAYSEL_SHIFT\t0\n+\n+#define ISC_DPC_CFG_EITPOL\t\tBIT(4)\n+\n+#define ISC_DPC_CFG_TA_ENABLE\t\tBIT(14)\n+#define ISC_DPC_CFG_TC_ENABLE\t\tBIT(13)\n+#define ISC_DPC_CFG_TM_ENABLE\t\tBIT(12)\n+\n+#define ISC_DPC_CFG_RE_MODE\t\tBIT(17)\n+\n+#define ISC_DPC_CFG_GDCCLP_SHIFT\t20\n+#define ISC_DPC_CFG_GDCCLP_MASK\t\tGENMASK(22, 20)\n+\n+#define ISC_DPC_CFG_BLOFF_SHIFT\t\t24\n+#define ISC_DPC_CFG_BLOFF_MASK\t\tGENMASK(31, 24)\n+\n+#define ISC_DPC_CFG_BAYCFG_SHIFT\t0\n+#define ISC_DPC_CFG_BAYCFG_MASK\t\tGENMASK(1, 0)\n+/* ISC DPC Threshold Median Register */\n+#define ISC_DPC_THRESHM\t0x48\n+\n+/* ISC DPC Threshold Closest Register */\n+#define ISC_DPC_THRESHC\t0x4C\n+\n+/* ISC DPC Threshold Average Register */\n+#define ISC_DPC_THRESHA\t0x50\n+\n+/* ISC DPC STatus Register */\n+#define ISC_DPC_SR\t0x54\n+\n /* ISC White Balance Control Register */\n #define ISC_WB_CTRL     0x00000058\n \n@@ -153,6 +193,33 @@\n /* ISC_Gamma Correction Green Entry Register */\n #define ISC_GAM_RENTRY\t0x00000298\n \n+/* ISC VHXS Control Register */\n+#define ISC_VHXS_CTRL\t0x398\n+\n+/* ISC VHXS Source Size Register */\n+#define ISC_VHXS_SS\t0x39C\n+\n+/* ISC VHXS Destination Size Register */\n+#define ISC_VHXS_DS\t0x3A0\n+\n+/* ISC Vertical Factor Register */\n+#define ISC_VXS_FACT\t0x3a4\n+\n+/* ISC Horizontal Factor Register */\n+#define ISC_HXS_FACT\t0x3a8\n+\n+/* ISC Vertical Config Register */\n+#define ISC_VXS_CFG\t0x3ac\n+\n+/* ISC Horizontal Config Register */\n+#define ISC_HXS_CFG\t0x3b0\n+\n+/* ISC Vertical Tap Register */\n+#define ISC_VXS_TAP\t0x3b4\n+\n+/* ISC Horizontal Tap Register */\n+#define ISC_HXS_TAP\t0x434\n+\n /* Offset for CSC register specific to sama5d2 product */\n #define ISC_SAMA5D2_CSC_OFFSET\t0\n \n"
  },
  {
    "path": "target/linux/at91/patches-5.10/174-media-atmel-atmel-isc-extend-pipeline-with-extra-mod.patch",
    "content": "From 58a6cc3c7eecd16208cd16b92b4eaf8385e69696 Mon Sep 17 00:00:00 2001\nFrom: Eugen Hristev <eugen.hristev@microchip.com>\nDate: Tue, 13 Apr 2021 12:57:16 +0200\nSubject: [PATCH 174/247] media: atmel: atmel-isc: extend pipeline with extra\n modules\n\nNewer ISC pipelines have the additional modules of\nDefective Pixel Correction -> DPC itself,\nDefective Pixel Correction -> Green Disparity Correction (DPC_GDC)\nDefective Pixel Correction -> Black Level Correction (DPC_BLC)\nVertical and Horizontal Scaler -> VHXS\n\nSome products have this full pipeline (sama7g5), other products do not (sama5d2)\n\nAdd the modules to the isc base, and also extend the register range to include\nthe modules.\n\nSigned-off-by: Eugen Hristev <eugen.hristev@microchip.com>\nSigned-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>\nSigned-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>\n---\n drivers/media/platform/atmel/atmel-isc-base.c | 11 ++++++--\n drivers/media/platform/atmel/atmel-isc.h      | 28 +++++++++++--------\n 2 files changed, 25 insertions(+), 14 deletions(-)\n\n--- a/drivers/media/platform/atmel/atmel-isc-base.c\n+++ b/drivers/media/platform/atmel/atmel-isc-base.c\n@@ -2324,8 +2324,14 @@ int isc_pipeline_init(struct isc_device\n \tstruct regmap_field *regs;\n \tunsigned int i;\n \n-\t/* WB-->CFA-->CC-->GAM-->CSC-->CBC-->SUB422-->SUB420 */\n+\t/*\n+\t * DPCEN-->GDCEN-->BLCEN-->WB-->CFA-->CC-->\n+\t * GAM-->VHXS-->CSC-->CBC-->SUB422-->SUB420\n+\t */\n \tconst struct reg_field regfields[ISC_PIPE_LINE_NODE_NUM] = {\n+\t\tREG_FIELD(ISC_DPC_CTRL, 0, 0),\n+\t\tREG_FIELD(ISC_DPC_CTRL, 1, 1),\n+\t\tREG_FIELD(ISC_DPC_CTRL, 2, 2),\n \t\tREG_FIELD(ISC_WB_CTRL, 0, 0),\n \t\tREG_FIELD(ISC_CFA_CTRL, 0, 0),\n \t\tREG_FIELD(ISC_CC_CTRL, 0, 0),\n@@ -2333,6 +2339,7 @@ int isc_pipeline_init(struct isc_device\n \t\tREG_FIELD(ISC_GAM_CTRL, 1, 1),\n \t\tREG_FIELD(ISC_GAM_CTRL, 2, 2),\n \t\tREG_FIELD(ISC_GAM_CTRL, 3, 3),\n+\t\tREG_FIELD(ISC_VHXS_CTRL, 0, 0),\n \t\tREG_FIELD(ISC_CSC_CTRL + isc->offsets.csc, 0, 0),\n \t\tREG_FIELD(ISC_CBC_CTRL + isc->offsets.cbc, 0, 0),\n \t\tREG_FIELD(ISC_SUB422_CTRL + isc->offsets.sub422, 0, 0),\n@@ -2351,7 +2358,7 @@ int isc_pipeline_init(struct isc_device\n }\n \n /* regmap configuration */\n-#define ATMEL_ISC_REG_MAX    0xbfc\n+#define ATMEL_ISC_REG_MAX    0xd5c\n const struct regmap_config isc_regmap_config = {\n \t.reg_bits       = 32,\n \t.reg_stride     = 4,\n--- a/drivers/media/platform/atmel/atmel-isc.h\n+++ b/drivers/media/platform/atmel/atmel-isc.h\n@@ -67,17 +67,21 @@ struct isc_format {\n };\n \n /* Pipeline bitmap */\n-#define WB_ENABLE\tBIT(0)\n-#define CFA_ENABLE\tBIT(1)\n-#define CC_ENABLE\tBIT(2)\n-#define GAM_ENABLE\tBIT(3)\n-#define GAM_BENABLE\tBIT(4)\n-#define GAM_GENABLE\tBIT(5)\n-#define GAM_RENABLE\tBIT(6)\n-#define CSC_ENABLE\tBIT(7)\n-#define CBC_ENABLE\tBIT(8)\n-#define SUB422_ENABLE\tBIT(9)\n-#define SUB420_ENABLE\tBIT(10)\n+#define DPC_DPCENABLE\tBIT(0)\n+#define DPC_GDCENABLE\tBIT(1)\n+#define DPC_BLCENABLE\tBIT(2)\n+#define WB_ENABLE\tBIT(3)\n+#define CFA_ENABLE\tBIT(4)\n+#define CC_ENABLE\tBIT(5)\n+#define GAM_ENABLE\tBIT(6)\n+#define GAM_BENABLE\tBIT(7)\n+#define GAM_GENABLE\tBIT(8)\n+#define GAM_RENABLE\tBIT(9)\n+#define VHXS_ENABLE\tBIT(10)\n+#define CSC_ENABLE\tBIT(11)\n+#define CBC_ENABLE\tBIT(12)\n+#define SUB422_ENABLE\tBIT(13)\n+#define SUB420_ENABLE\tBIT(14)\n \n #define GAM_ENABLES\t(GAM_RENABLE | GAM_GENABLE | GAM_BENABLE | GAM_ENABLE)\n \n@@ -141,7 +145,7 @@ struct isc_ctrls {\n \tu32 hist_minmax[HIST_BAYER][2];\n };\n \n-#define ISC_PIPE_LINE_NODE_NUM\t11\n+#define ISC_PIPE_LINE_NODE_NUM\t15\n \n /*\n  * struct isc_reg_offsets - ISC device register offsets\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/175-media-atmel-atmel-isc-add-CC-initialization-function.patch",
    "content": "From 0db91d2a803221c313c9f2cd1d71050d7c5a7b5b Mon Sep 17 00:00:00 2001\nFrom: Eugen Hristev <eugen.hristev@microchip.com>\nDate: Tue, 13 Apr 2021 12:57:17 +0200\nSubject: [PATCH 175/247] media: atmel: atmel-isc: add CC initialization\n function\n\nThe CC submodule is a part of the atmel-isc pipeline, and stands for\nColor Correction. It is used to apply gains and offsets to the\nchroma (U, V) components of the YUV elements.\nImplement the CC submodule initialization, as a product\nspecific function, which currently configures the neutral point in color\ncorrection.\n\n[hverkuil: made isc_sama5d2_config_cc static]\n\nSigned-off-by: Eugen Hristev <eugen.hristev@microchip.com>\nSigned-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>\nSigned-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>\n---\n drivers/media/platform/atmel/atmel-isc-base.c    |  1 +\n drivers/media/platform/atmel/atmel-isc.h         |  3 +++\n drivers/media/platform/atmel/atmel-sama5d2-isc.c | 14 ++++++++++++++\n 3 files changed, 18 insertions(+)\n\n--- a/drivers/media/platform/atmel/atmel-isc-base.c\n+++ b/drivers/media/platform/atmel/atmel-isc-base.c\n@@ -661,6 +661,7 @@ static void isc_set_pipeline(struct isc_\n \n \tisc->config_csc(isc);\n \tisc->config_cbc(isc);\n+\tisc->config_cc(isc);\n }\n \n static int isc_update_profile(struct isc_device *isc)\n--- a/drivers/media/platform/atmel/atmel-isc.h\n+++ b/drivers/media/platform/atmel/atmel-isc.h\n@@ -224,6 +224,8 @@ struct isc_reg_offsets {\n  *\t\t\tspecific CSC module\n  * @config_cbc:\t\tpointer to a function that initializes product\n  *\t\t\tspecific CBC module\n+ * @config_cc:\t\tpointer to a function that initializes product\n+ *\t\t\tspecific CC module\n  *\n  * @offsets:\t\tstruct holding the product specific register offsets\n  */\n@@ -297,6 +299,7 @@ struct isc_device {\n \tstruct {\n \t\tvoid (*config_csc)(struct isc_device *isc);\n \t\tvoid (*config_cbc)(struct isc_device *isc);\n+\t\tvoid (*config_cc)(struct isc_device *isc);\n \t};\n \n \tstruct isc_reg_offsets\t\toffsets;\n--- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c\n+++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c\n@@ -83,6 +83,19 @@ static void isc_sama5d2_config_cbc(struc\n \t\t     isc->ctrls.contrast);\n }\n \n+static void isc_sama5d2_config_cc(struct isc_device *isc)\n+{\n+\tstruct regmap *regmap = isc->regmap;\n+\n+\t/* Configure each register at the neutral fixed point 1.0 or 0.0 */\n+\tregmap_write(regmap, ISC_CC_RR_RG, (1 << 8));\n+\tregmap_write(regmap, ISC_CC_RB_OR, 0);\n+\tregmap_write(regmap, ISC_CC_GR_GG, (1 << 8) << 16);\n+\tregmap_write(regmap, ISC_CC_GB_OG, 0);\n+\tregmap_write(regmap, ISC_CC_BR_BG, 0);\n+\tregmap_write(regmap, ISC_CC_BB_OB, (1 << 8));\n+}\n+\n /* Gamma table with gamma 1/2.2 */\n static const u32 isc_sama5d2_gamma_table[][GAMMA_ENTRIES] = {\n \t/* 0 --> gamma 1/1.8 */\n@@ -251,6 +264,7 @@ static int atmel_isc_probe(struct platfo\n \n \tisc->config_csc = isc_sama5d2_config_csc;\n \tisc->config_cbc = isc_sama5d2_config_cbc;\n+\tisc->config_cc = isc_sama5d2_config_cc;\n \n \tisc->offsets.csc = ISC_SAMA5D2_CSC_OFFSET;\n \tisc->offsets.cbc = ISC_SAMA5D2_CBC_OFFSET;\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/176-media-atmel-atmel-isc-create-product-specific-v4l2-c.patch",
    "content": "From 0a75c502eac4f2ef71b6c3e0b3a01db1b3c37ba9 Mon Sep 17 00:00:00 2001\nFrom: Eugen Hristev <eugen.hristev@microchip.com>\nDate: Tue, 13 Apr 2021 12:57:18 +0200\nSubject: [PATCH 176/247] media: atmel: atmel-isc: create product specific v4l2\n controls config\n\nCreate product specific callback for initializing v4l2 controls.\nCall this from v4l2 controls init function.\n\n[hverkuil: made isc_sama5d2_config_ctrls static]\n\nSigned-off-by: Eugen Hristev <eugen.hristev@microchip.com>\nSigned-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>\nSigned-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>\n---\n drivers/media/platform/atmel/atmel-isc-base.c    |  5 +++--\n drivers/media/platform/atmel/atmel-isc.h         |  5 +++++\n drivers/media/platform/atmel/atmel-sama5d2-isc.c | 12 ++++++++++++\n 3 files changed, 20 insertions(+), 2 deletions(-)\n\n--- a/drivers/media/platform/atmel/atmel-isc-base.c\n+++ b/drivers/media/platform/atmel/atmel-isc-base.c\n@@ -2051,11 +2051,12 @@ static int isc_ctrl_init(struct isc_devi\n \tif (ret < 0)\n \t\treturn ret;\n \n+\t/* Initialize product specific controls. For example, contrast */\n+\tisc->config_ctrls(isc, ops);\n+\n \tctrls->brightness = 0;\n-\tctrls->contrast = 256;\n \n \tv4l2_ctrl_new_std(hdl, ops, V4L2_CID_BRIGHTNESS, -1024, 1023, 1, 0);\n-\tv4l2_ctrl_new_std(hdl, ops, V4L2_CID_CONTRAST, -2048, 2047, 1, 256);\n \tv4l2_ctrl_new_std(hdl, ops, V4L2_CID_GAMMA, 0, isc->gamma_max, 1,\n \t\t\t  isc->gamma_max);\n \tisc->awb_ctrl = v4l2_ctrl_new_std(hdl, &isc_awb_ops,\n--- a/drivers/media/platform/atmel/atmel-isc.h\n+++ b/drivers/media/platform/atmel/atmel-isc.h\n@@ -226,6 +226,8 @@ struct isc_reg_offsets {\n  *\t\t\tspecific CBC module\n  * @config_cc:\t\tpointer to a function that initializes product\n  *\t\t\tspecific CC module\n+ * @config_ctrls:\tpointer to a functoin that initializes product\n+ *\t\t\tspecific v4l2 controls.\n  *\n  * @offsets:\t\tstruct holding the product specific register offsets\n  */\n@@ -300,6 +302,9 @@ struct isc_device {\n \t\tvoid (*config_csc)(struct isc_device *isc);\n \t\tvoid (*config_cbc)(struct isc_device *isc);\n \t\tvoid (*config_cc)(struct isc_device *isc);\n+\n+\t\tvoid (*config_ctrls)(struct isc_device *isc,\n+\t\t\t\t     const struct v4l2_ctrl_ops *ops);\n \t};\n \n \tstruct isc_reg_offsets\t\toffsets;\n--- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c\n+++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c\n@@ -96,6 +96,17 @@ static void isc_sama5d2_config_cc(struct\n \tregmap_write(regmap, ISC_CC_BB_OB, (1 << 8));\n }\n \n+static void isc_sama5d2_config_ctrls(struct isc_device *isc,\n+\t\t\t\t     const struct v4l2_ctrl_ops *ops)\n+{\n+\tstruct isc_ctrls *ctrls = &isc->ctrls;\n+\tstruct v4l2_ctrl_handler *hdl = &ctrls->handler;\n+\n+\tctrls->contrast = 256;\n+\n+\tv4l2_ctrl_new_std(hdl, ops, V4L2_CID_CONTRAST, -2048, 2047, 1, 256);\n+}\n+\n /* Gamma table with gamma 1/2.2 */\n static const u32 isc_sama5d2_gamma_table[][GAMMA_ENTRIES] = {\n \t/* 0 --> gamma 1/1.8 */\n@@ -265,6 +276,7 @@ static int atmel_isc_probe(struct platfo\n \tisc->config_csc = isc_sama5d2_config_csc;\n \tisc->config_cbc = isc_sama5d2_config_cbc;\n \tisc->config_cc = isc_sama5d2_config_cc;\n+\tisc->config_ctrls = isc_sama5d2_config_ctrls;\n \n \tisc->offsets.csc = ISC_SAMA5D2_CSC_OFFSET;\n \tisc->offsets.cbc = ISC_SAMA5D2_CBC_OFFSET;\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/177-media-atmel-atmel-isc-create-callback-for-DPC-submod.patch",
    "content": "From d53eb90044c19ba22b51978fcb007d9b5200b83a Mon Sep 17 00:00:00 2001\nFrom: Eugen Hristev <eugen.hristev@microchip.com>\nDate: Tue, 13 Apr 2021 12:57:19 +0200\nSubject: [PATCH 177/247] media: atmel: atmel-isc: create callback for DPC\n submodule product specific\n\nThe DPC submodule is a part of the atmel-isc pipeline, and stands for\nDefective Pixel Correction. Its purpose is to detect defective pixels and\ncorrect them if possible with the help of adjacent pixels.\nCreate a product specific callback for initializing the DPC submodule\nof the pipeline.\nFor sama5d2 product, this module does not exist, thus this function is a noop.\n\n[hverkuil: made isc_sama5d2_config_dpc static]\n\nSigned-off-by: Eugen Hristev <eugen.hristev@microchip.com>\nSigned-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>\nSigned-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>\n---\n drivers/media/platform/atmel/atmel-isc-base.c    | 1 +\n drivers/media/platform/atmel/atmel-isc.h         | 3 +++\n drivers/media/platform/atmel/atmel-sama5d2-isc.c | 6 ++++++\n 3 files changed, 10 insertions(+)\n\n--- a/drivers/media/platform/atmel/atmel-isc-base.c\n+++ b/drivers/media/platform/atmel/atmel-isc-base.c\n@@ -659,6 +659,7 @@ static void isc_set_pipeline(struct isc_\n \tregmap_bulk_write(regmap, ISC_GAM_GENTRY, gamma, GAMMA_ENTRIES);\n \tregmap_bulk_write(regmap, ISC_GAM_RENTRY, gamma, GAMMA_ENTRIES);\n \n+\tisc->config_dpc(isc);\n \tisc->config_csc(isc);\n \tisc->config_cbc(isc);\n \tisc->config_cc(isc);\n--- a/drivers/media/platform/atmel/atmel-isc.h\n+++ b/drivers/media/platform/atmel/atmel-isc.h\n@@ -220,6 +220,8 @@ struct isc_reg_offsets {\n  * @max_width:\t\tmaximum frame width, dependent on the internal RAM\n  * @max_height:\t\tmaximum frame height, dependent on the internal RAM\n  *\n+ * @config_dpc:\t\tpointer to a function that initializes product\n+ *\t\t\tspecific DPC module\n  * @config_csc:\t\tpointer to a function that initializes product\n  *\t\t\tspecific CSC module\n  * @config_cbc:\t\tpointer to a function that initializes product\n@@ -299,6 +301,7 @@ struct isc_device {\n \tu32\t\tmax_height;\n \n \tstruct {\n+\t\tvoid (*config_dpc)(struct isc_device *isc);\n \t\tvoid (*config_csc)(struct isc_device *isc);\n \t\tvoid (*config_cbc)(struct isc_device *isc);\n \t\tvoid (*config_cc)(struct isc_device *isc);\n--- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c\n+++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c\n@@ -107,6 +107,11 @@ static void isc_sama5d2_config_ctrls(str\n \tv4l2_ctrl_new_std(hdl, ops, V4L2_CID_CONTRAST, -2048, 2047, 1, 256);\n }\n \n+static void isc_sama5d2_config_dpc(struct isc_device *isc)\n+{\n+\t/* This module is not present on sama5d2 pipeline */\n+}\n+\n /* Gamma table with gamma 1/2.2 */\n static const u32 isc_sama5d2_gamma_table[][GAMMA_ENTRIES] = {\n \t/* 0 --> gamma 1/1.8 */\n@@ -273,6 +278,7 @@ static int atmel_isc_probe(struct platfo\n \tisc->max_width = ISC_SAMA5D2_MAX_SUPPORT_WIDTH;\n \tisc->max_height = ISC_SAMA5D2_MAX_SUPPORT_HEIGHT;\n \n+\tisc->config_dpc = isc_sama5d2_config_dpc;\n \tisc->config_csc = isc_sama5d2_config_csc;\n \tisc->config_cbc = isc_sama5d2_config_cbc;\n \tisc->config_cc = isc_sama5d2_config_cc;\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/178-media-atmel-atmel-isc-create-callback-for-GAM-submod.patch",
    "content": "From 96936a6753a13dea5a8f66de949e6594dd82ce22 Mon Sep 17 00:00:00 2001\nFrom: Eugen Hristev <eugen.hristev@microchip.com>\nDate: Tue, 13 Apr 2021 12:57:20 +0200\nSubject: [PATCH 178/247] media: atmel: atmel-isc: create callback for GAM\n submodule product specific\n\nThe GAM submodule is a part of the atmel-isc pipeline, and stands for\nGamma Correction. It is used to apply the gamma curve to the incoming pixels.\nCreate a product specific callback for initializing the GAM submodule\nof the pipeline.\nFor sama5d2 product, there is no special configuration at this moment,\nthus this function is a noop.\n\n[hverkuil: made isc_sama5d2_config_gam static]\n\nSigned-off-by: Eugen Hristev <eugen.hristev@microchip.com>\nSigned-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>\nSigned-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>\n---\n drivers/media/platform/atmel/atmel-isc-base.c    | 1 +\n drivers/media/platform/atmel/atmel-isc.h         | 3 +++\n drivers/media/platform/atmel/atmel-sama5d2-isc.c | 6 ++++++\n 3 files changed, 10 insertions(+)\n\n--- a/drivers/media/platform/atmel/atmel-isc-base.c\n+++ b/drivers/media/platform/atmel/atmel-isc-base.c\n@@ -663,6 +663,7 @@ static void isc_set_pipeline(struct isc_\n \tisc->config_csc(isc);\n \tisc->config_cbc(isc);\n \tisc->config_cc(isc);\n+\tisc->config_gam(isc);\n }\n \n static int isc_update_profile(struct isc_device *isc)\n--- a/drivers/media/platform/atmel/atmel-isc.h\n+++ b/drivers/media/platform/atmel/atmel-isc.h\n@@ -228,6 +228,8 @@ struct isc_reg_offsets {\n  *\t\t\tspecific CBC module\n  * @config_cc:\t\tpointer to a function that initializes product\n  *\t\t\tspecific CC module\n+ * @config_gam:\t\tpointer to a function that initializes product\n+ *\t\t\tspecific GAMMA module\n  * @config_ctrls:\tpointer to a functoin that initializes product\n  *\t\t\tspecific v4l2 controls.\n  *\n@@ -305,6 +307,7 @@ struct isc_device {\n \t\tvoid (*config_csc)(struct isc_device *isc);\n \t\tvoid (*config_cbc)(struct isc_device *isc);\n \t\tvoid (*config_cc)(struct isc_device *isc);\n+\t\tvoid (*config_gam)(struct isc_device *isc);\n \n \t\tvoid (*config_ctrls)(struct isc_device *isc,\n \t\t\t\t     const struct v4l2_ctrl_ops *ops);\n--- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c\n+++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c\n@@ -112,6 +112,11 @@ static void isc_sama5d2_config_dpc(struc\n \t/* This module is not present on sama5d2 pipeline */\n }\n \n+static void isc_sama5d2_config_gam(struct isc_device *isc)\n+{\n+\t/* No specific gamma configuration */\n+}\n+\n /* Gamma table with gamma 1/2.2 */\n static const u32 isc_sama5d2_gamma_table[][GAMMA_ENTRIES] = {\n \t/* 0 --> gamma 1/1.8 */\n@@ -282,6 +287,7 @@ static int atmel_isc_probe(struct platfo\n \tisc->config_csc = isc_sama5d2_config_csc;\n \tisc->config_cbc = isc_sama5d2_config_cbc;\n \tisc->config_cc = isc_sama5d2_config_cc;\n+\tisc->config_gam = isc_sama5d2_config_gam;\n \tisc->config_ctrls = isc_sama5d2_config_ctrls;\n \n \tisc->offsets.csc = ISC_SAMA5D2_CSC_OFFSET;\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/179-media-atmel-atmel-isc-create-callback-for-RLP-submod.patch",
    "content": "From ece1d7059731e31875e6eb464da4fb4a16465305 Mon Sep 17 00:00:00 2001\nFrom: Eugen Hristev <eugen.hristev@microchip.com>\nDate: Tue, 13 Apr 2021 12:57:21 +0200\nSubject: [PATCH 179/247] media: atmel: atmel-isc: create callback for RLP\n submodule product specific\n\nThe RLP submodule is a part of the atmel-isc pipeline, and stands for\nRounding,Limiting and Packaging. It used to extract specific data from the\nISC pipeline. For example if we want to output greyscale 8 bit, we would\nuse limiting to 8 bits, and packaging to Luma component only.\n\nCreate a product specific callback for initializing the RLP submodule\nof the pipeline\n\n[hverkuil: made isc_sama5d2_config_rlp static]\n\nSigned-off-by: Eugen Hristev <eugen.hristev@microchip.com>\nSigned-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>\nSigned-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>\n---\n drivers/media/platform/atmel/atmel-isc-base.c    |  6 ++----\n drivers/media/platform/atmel/atmel-isc.h         |  3 +++\n drivers/media/platform/atmel/atmel-sama5d2-isc.c | 10 ++++++++++\n 3 files changed, 15 insertions(+), 4 deletions(-)\n\n--- a/drivers/media/platform/atmel/atmel-isc-base.c\n+++ b/drivers/media/platform/atmel/atmel-isc-base.c\n@@ -719,11 +719,10 @@ static void isc_set_histogram(struct isc\n static int isc_configure(struct isc_device *isc)\n {\n \tstruct regmap *regmap = isc->regmap;\n-\tu32 pfe_cfg0, rlp_mode, dcfg, mask, pipeline;\n+\tu32 pfe_cfg0, dcfg, mask, pipeline;\n \tstruct isc_subdev_entity *subdev = isc->current_subdev;\n \n \tpfe_cfg0 = isc->config.sd_format->pfe_cfg0_bps;\n-\trlp_mode = isc->config.rlp_cfg_mode;\n \tpipeline = isc->config.bits_pipeline;\n \n \tdcfg = isc->config.dcfg_imode | isc->dcfg;\n@@ -736,8 +735,7 @@ static int isc_configure(struct isc_devi\n \n \tregmap_update_bits(regmap, ISC_PFE_CFG0, mask, pfe_cfg0);\n \n-\tregmap_update_bits(regmap, ISC_RLP_CFG + isc->offsets.rlp,\n-\t\t\t   ISC_RLP_CFG_MODE_MASK, rlp_mode);\n+\tisc->config_rlp(isc);\n \n \tregmap_write(regmap, ISC_DCFG + isc->offsets.dma, dcfg);\n \n--- a/drivers/media/platform/atmel/atmel-isc.h\n+++ b/drivers/media/platform/atmel/atmel-isc.h\n@@ -230,6 +230,8 @@ struct isc_reg_offsets {\n  *\t\t\tspecific CC module\n  * @config_gam:\t\tpointer to a function that initializes product\n  *\t\t\tspecific GAMMA module\n+ * @config_rlp:\t\tpointer to a function that initializes product\n+ *\t\t\tspecific RLP module\n  * @config_ctrls:\tpointer to a functoin that initializes product\n  *\t\t\tspecific v4l2 controls.\n  *\n@@ -308,6 +310,7 @@ struct isc_device {\n \t\tvoid (*config_cbc)(struct isc_device *isc);\n \t\tvoid (*config_cc)(struct isc_device *isc);\n \t\tvoid (*config_gam)(struct isc_device *isc);\n+\t\tvoid (*config_rlp)(struct isc_device *isc);\n \n \t\tvoid (*config_ctrls)(struct isc_device *isc,\n \t\t\t\t     const struct v4l2_ctrl_ops *ops);\n--- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c\n+++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c\n@@ -117,6 +117,15 @@ static void isc_sama5d2_config_gam(struc\n \t/* No specific gamma configuration */\n }\n \n+static void isc_sama5d2_config_rlp(struct isc_device *isc)\n+{\n+\tstruct regmap *regmap = isc->regmap;\n+\tu32 rlp_mode = isc->config.rlp_cfg_mode;\n+\n+\tregmap_update_bits(regmap, ISC_RLP_CFG + isc->offsets.rlp,\n+\t\t\t   ISC_RLP_CFG_MODE_MASK, rlp_mode);\n+}\n+\n /* Gamma table with gamma 1/2.2 */\n static const u32 isc_sama5d2_gamma_table[][GAMMA_ENTRIES] = {\n \t/* 0 --> gamma 1/1.8 */\n@@ -288,6 +297,7 @@ static int atmel_isc_probe(struct platfo\n \tisc->config_cbc = isc_sama5d2_config_cbc;\n \tisc->config_cc = isc_sama5d2_config_cc;\n \tisc->config_gam = isc_sama5d2_config_gam;\n+\tisc->config_rlp = isc_sama5d2_config_rlp;\n \tisc->config_ctrls = isc_sama5d2_config_ctrls;\n \n \tisc->offsets.csc = ISC_SAMA5D2_CSC_OFFSET;\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/180-media-atmel-atmel-isc-move-the-formats-list-into-pro.patch",
    "content": "From dda51aa2e4524914d25022864466fa9d8713a5e9 Mon Sep 17 00:00:00 2001\nFrom: Eugen Hristev <eugen.hristev@microchip.com>\nDate: Tue, 13 Apr 2021 12:57:22 +0200\nSubject: [PATCH 180/247] media: atmel: atmel-isc: move the formats list into\n product specific code\n\nThe list of input and output formats has to be product specific.\nMove this list into the product specific code.\nHave pointers to these arrays inside the device struct.\n\nSigned-off-by: Eugen Hristev <eugen.hristev@microchip.com>\nSigned-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>\nSigned-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>\n---\n drivers/media/platform/atmel/atmel-isc-base.c | 167 ++----------------\n drivers/media/platform/atmel/atmel-isc.h      |  12 +-\n .../media/platform/atmel/atmel-sama5d2-isc.c  | 136 ++++++++++++++\n 3 files changed, 165 insertions(+), 150 deletions(-)\n\n--- a/drivers/media/platform/atmel/atmel-isc-base.c\n+++ b/drivers/media/platform/atmel/atmel-isc-base.c\n@@ -45,137 +45,6 @@ module_param(sensor_preferred, uint, 064\n MODULE_PARM_DESC(sensor_preferred,\n \t\t \"Sensor is preferred to output the specified format (1-on 0-off), default 1\");\n \n-/* This is a list of the formats that the ISC can *output* */\n-const struct isc_format controller_formats[] = {\n-\t{\n-\t\t.fourcc\t\t= V4L2_PIX_FMT_ARGB444,\n-\t},\n-\t{\n-\t\t.fourcc\t\t= V4L2_PIX_FMT_ARGB555,\n-\t},\n-\t{\n-\t\t.fourcc\t\t= V4L2_PIX_FMT_RGB565,\n-\t},\n-\t{\n-\t\t.fourcc\t\t= V4L2_PIX_FMT_ABGR32,\n-\t},\n-\t{\n-\t\t.fourcc\t\t= V4L2_PIX_FMT_XBGR32,\n-\t},\n-\t{\n-\t\t.fourcc\t\t= V4L2_PIX_FMT_YUV420,\n-\t},\n-\t{\n-\t\t.fourcc\t\t= V4L2_PIX_FMT_YUYV,\n-\t},\n-\t{\n-\t\t.fourcc\t\t= V4L2_PIX_FMT_YUV422P,\n-\t},\n-\t{\n-\t\t.fourcc\t\t= V4L2_PIX_FMT_GREY,\n-\t},\n-\t{\n-\t\t.fourcc\t\t= V4L2_PIX_FMT_Y10,\n-\t},\n-};\n-\n-/* This is a list of formats that the ISC can receive as *input* */\n-struct isc_format formats_list[] = {\n-\t{\n-\t\t.fourcc\t\t= V4L2_PIX_FMT_SBGGR8,\n-\t\t.mbus_code\t= MEDIA_BUS_FMT_SBGGR8_1X8,\n-\t\t.pfe_cfg0_bps\t= ISC_PFE_CFG0_BPS_EIGHT,\n-\t\t.cfa_baycfg\t= ISC_BAY_CFG_BGBG,\n-\t},\n-\t{\n-\t\t.fourcc\t\t= V4L2_PIX_FMT_SGBRG8,\n-\t\t.mbus_code\t= MEDIA_BUS_FMT_SGBRG8_1X8,\n-\t\t.pfe_cfg0_bps\t= ISC_PFE_CFG0_BPS_EIGHT,\n-\t\t.cfa_baycfg\t= ISC_BAY_CFG_GBGB,\n-\t},\n-\t{\n-\t\t.fourcc\t\t= V4L2_PIX_FMT_SGRBG8,\n-\t\t.mbus_code\t= MEDIA_BUS_FMT_SGRBG8_1X8,\n-\t\t.pfe_cfg0_bps\t= ISC_PFE_CFG0_BPS_EIGHT,\n-\t\t.cfa_baycfg\t= ISC_BAY_CFG_GRGR,\n-\t},\n-\t{\n-\t\t.fourcc\t\t= V4L2_PIX_FMT_SRGGB8,\n-\t\t.mbus_code\t= MEDIA_BUS_FMT_SRGGB8_1X8,\n-\t\t.pfe_cfg0_bps\t= ISC_PFE_CFG0_BPS_EIGHT,\n-\t\t.cfa_baycfg\t= ISC_BAY_CFG_RGRG,\n-\t},\n-\t{\n-\t\t.fourcc\t\t= V4L2_PIX_FMT_SBGGR10,\n-\t\t.mbus_code\t= MEDIA_BUS_FMT_SBGGR10_1X10,\n-\t\t.pfe_cfg0_bps\t= ISC_PFG_CFG0_BPS_TEN,\n-\t\t.cfa_baycfg\t= ISC_BAY_CFG_RGRG,\n-\t},\n-\t{\n-\t\t.fourcc\t\t= V4L2_PIX_FMT_SGBRG10,\n-\t\t.mbus_code\t= MEDIA_BUS_FMT_SGBRG10_1X10,\n-\t\t.pfe_cfg0_bps\t= ISC_PFG_CFG0_BPS_TEN,\n-\t\t.cfa_baycfg\t= ISC_BAY_CFG_GBGB,\n-\t},\n-\t{\n-\t\t.fourcc\t\t= V4L2_PIX_FMT_SGRBG10,\n-\t\t.mbus_code\t= MEDIA_BUS_FMT_SGRBG10_1X10,\n-\t\t.pfe_cfg0_bps\t= ISC_PFG_CFG0_BPS_TEN,\n-\t\t.cfa_baycfg\t= ISC_BAY_CFG_GRGR,\n-\t},\n-\t{\n-\t\t.fourcc\t\t= V4L2_PIX_FMT_SRGGB10,\n-\t\t.mbus_code\t= MEDIA_BUS_FMT_SRGGB10_1X10,\n-\t\t.pfe_cfg0_bps\t= ISC_PFG_CFG0_BPS_TEN,\n-\t\t.cfa_baycfg\t= ISC_BAY_CFG_RGRG,\n-\t},\n-\t{\n-\t\t.fourcc\t\t= V4L2_PIX_FMT_SBGGR12,\n-\t\t.mbus_code\t= MEDIA_BUS_FMT_SBGGR12_1X12,\n-\t\t.pfe_cfg0_bps\t= ISC_PFG_CFG0_BPS_TWELVE,\n-\t\t.cfa_baycfg\t= ISC_BAY_CFG_BGBG,\n-\t},\n-\t{\n-\t\t.fourcc\t\t= V4L2_PIX_FMT_SGBRG12,\n-\t\t.mbus_code\t= MEDIA_BUS_FMT_SGBRG12_1X12,\n-\t\t.pfe_cfg0_bps\t= ISC_PFG_CFG0_BPS_TWELVE,\n-\t\t.cfa_baycfg\t= ISC_BAY_CFG_GBGB,\n-\t},\n-\t{\n-\t\t.fourcc\t\t= V4L2_PIX_FMT_SGRBG12,\n-\t\t.mbus_code\t= MEDIA_BUS_FMT_SGRBG12_1X12,\n-\t\t.pfe_cfg0_bps\t= ISC_PFG_CFG0_BPS_TWELVE,\n-\t\t.cfa_baycfg\t= ISC_BAY_CFG_GRGR,\n-\t},\n-\t{\n-\t\t.fourcc\t\t= V4L2_PIX_FMT_SRGGB12,\n-\t\t.mbus_code\t= MEDIA_BUS_FMT_SRGGB12_1X12,\n-\t\t.pfe_cfg0_bps\t= ISC_PFG_CFG0_BPS_TWELVE,\n-\t\t.cfa_baycfg\t= ISC_BAY_CFG_RGRG,\n-\t},\n-\t{\n-\t\t.fourcc\t\t= V4L2_PIX_FMT_GREY,\n-\t\t.mbus_code\t= MEDIA_BUS_FMT_Y8_1X8,\n-\t\t.pfe_cfg0_bps\t= ISC_PFE_CFG0_BPS_EIGHT,\n-\t},\n-\t{\n-\t\t.fourcc\t\t= V4L2_PIX_FMT_YUYV,\n-\t\t.mbus_code\t= MEDIA_BUS_FMT_YUYV8_2X8,\n-\t\t.pfe_cfg0_bps\t= ISC_PFE_CFG0_BPS_EIGHT,\n-\t},\n-\t{\n-\t\t.fourcc\t\t= V4L2_PIX_FMT_RGB565,\n-\t\t.mbus_code\t= MEDIA_BUS_FMT_RGB565_2X8_LE,\n-\t\t.pfe_cfg0_bps\t= ISC_PFE_CFG0_BPS_EIGHT,\n-\t},\n-\t{\n-\t\t.fourcc\t\t= V4L2_PIX_FMT_Y10,\n-\t\t.mbus_code\t= MEDIA_BUS_FMT_Y10_1X10,\n-\t\t.pfe_cfg0_bps\t= ISC_PFG_CFG0_BPS_TEN,\n-\t},\n-\n-};\n-\n #define ISC_IS_FORMAT_RAW(mbus_code) \\\n \t(((mbus_code) & 0xf000) == 0x3000)\n \n@@ -919,24 +788,25 @@ static int isc_querycap(struct file *fil\n static int isc_enum_fmt_vid_cap(struct file *file, void *priv,\n \t\t\t\t struct v4l2_fmtdesc *f)\n {\n+\tstruct isc_device *isc = video_drvdata(file);\n \tu32 index = f->index;\n \tu32 i, supported_index;\n \n-\tif (index < ARRAY_SIZE(controller_formats)) {\n-\t\tf->pixelformat = controller_formats[index].fourcc;\n+\tif (index < isc->controller_formats_size) {\n+\t\tf->pixelformat = isc->controller_formats[index].fourcc;\n \t\treturn 0;\n \t}\n \n-\tindex -= ARRAY_SIZE(controller_formats);\n+\tindex -= isc->controller_formats_size;\n \n \tsupported_index = 0;\n \n-\tfor (i = 0; i < ARRAY_SIZE(formats_list); i++) {\n-\t\tif (!ISC_IS_FORMAT_RAW(formats_list[i].mbus_code) ||\n-\t\t    !formats_list[i].sd_support)\n+\tfor (i = 0; i < isc->formats_list_size; i++) {\n+\t\tif (!ISC_IS_FORMAT_RAW(isc->formats_list[i].mbus_code) ||\n+\t\t    !isc->formats_list[i].sd_support)\n \t\t\tcontinue;\n \t\tif (supported_index == index) {\n-\t\t\tf->pixelformat = formats_list[i].fourcc;\n+\t\t\tf->pixelformat = isc->formats_list[i].fourcc;\n \t\t\treturn 0;\n \t\t}\n \t\tsupported_index++;\n@@ -1477,8 +1347,8 @@ static int isc_enum_framesizes(struct fi\n \t\tif (isc->user_formats[i]->fourcc == fsize->pixel_format)\n \t\t\tret = 0;\n \n-\tfor (i = 0; i < ARRAY_SIZE(controller_formats); i++)\n-\t\tif (controller_formats[i].fourcc == fsize->pixel_format)\n+\tfor (i = 0; i < isc->controller_formats_size; i++)\n+\t\tif (isc->controller_formats[i].fourcc == fsize->pixel_format)\n \t\t\tret = 0;\n \n \tif (ret)\n@@ -1514,8 +1384,8 @@ static int isc_enum_frameintervals(struc\n \t\tif (isc->user_formats[i]->fourcc == fival->pixel_format)\n \t\t\tret = 0;\n \n-\tfor (i = 0; i < ARRAY_SIZE(controller_formats); i++)\n-\t\tif (controller_formats[i].fourcc == fival->pixel_format)\n+\tfor (i = 0; i < isc->controller_formats_size; i++)\n+\t\tif (isc->controller_formats[i].fourcc == fival->pixel_format)\n \t\t\tret = 0;\n \n \tif (ret)\n@@ -2126,12 +1996,13 @@ static void isc_async_unbind(struct v4l2\n \tv4l2_ctrl_handler_free(&isc->ctrls.handler);\n }\n \n-static struct isc_format *find_format_by_code(unsigned int code, int *index)\n+static struct isc_format *find_format_by_code(struct isc_device *isc,\n+\t\t\t\t\t      unsigned int code, int *index)\n {\n-\tstruct isc_format *fmt = &formats_list[0];\n+\tstruct isc_format *fmt = &isc->formats_list[0];\n \tunsigned int i;\n \n-\tfor (i = 0; i < ARRAY_SIZE(formats_list); i++) {\n+\tfor (i = 0; i < isc->formats_list_size; i++) {\n \t\tif (fmt->mbus_code == code) {\n \t\t\t*index = i;\n \t\t\treturn fmt;\n@@ -2148,7 +2019,7 @@ static int isc_formats_init(struct isc_d\n \tstruct isc_format *fmt;\n \tstruct v4l2_subdev *subdev = isc->current_subdev->sd;\n \tunsigned int num_fmts, i, j;\n-\tu32 list_size = ARRAY_SIZE(formats_list);\n+\tu32 list_size = isc->formats_list_size;\n \tstruct v4l2_subdev_mbus_code_enum mbus_code = {\n \t\t.which = V4L2_SUBDEV_FORMAT_ACTIVE,\n \t};\n@@ -2158,7 +2029,7 @@ static int isc_formats_init(struct isc_d\n \t       NULL, &mbus_code)) {\n \t\tmbus_code.index++;\n \n-\t\tfmt = find_format_by_code(mbus_code.code, &i);\n+\t\tfmt = find_format_by_code(isc, mbus_code.code, &i);\n \t\tif (!fmt) {\n \t\t\tv4l2_warn(&isc->v4l2_dev, \"Mbus code %x not supported\\n\",\n \t\t\t\t  mbus_code.code);\n@@ -2179,7 +2050,7 @@ static int isc_formats_init(struct isc_d\n \tif (!isc->user_formats)\n \t\treturn -ENOMEM;\n \n-\tfmt = &formats_list[0];\n+\tfmt = &isc->formats_list[0];\n \tfor (i = 0, j = 0; i < list_size; i++) {\n \t\tif (fmt->sd_support)\n \t\t\tisc->user_formats[j++] = fmt;\n--- a/drivers/media/platform/atmel/atmel-isc.h\n+++ b/drivers/media/platform/atmel/atmel-isc.h\n@@ -236,6 +236,12 @@ struct isc_reg_offsets {\n  *\t\t\tspecific v4l2 controls.\n  *\n  * @offsets:\t\tstruct holding the product specific register offsets\n+ * @controller_formats:\tpointer to the array of possible formats that the\n+ *\t\t\tcontroller can output\n+ * @formats_list:\tpointer to the array of possible formats that can\n+ *\t\t\tbe used as an input to the controller\n+ * @controller_formats_size:\tsize of controller_formats array\n+ * @formats_list_size:\tsize of formats_list array\n  */\n struct isc_device {\n \tstruct regmap\t\t*regmap;\n@@ -317,10 +323,12 @@ struct isc_device {\n \t};\n \n \tstruct isc_reg_offsets\t\toffsets;\n+\tconst struct isc_format\t\t*controller_formats;\n+\tstruct isc_format\t\t*formats_list;\n+\tu32\t\t\t\tcontroller_formats_size;\n+\tu32\t\t\t\tformats_list_size;\n };\n \n-extern struct isc_format formats_list[];\n-extern const struct isc_format controller_formats[];\n extern const struct regmap_config isc_regmap_config;\n extern const struct v4l2_async_notifier_operations isc_async_ops;\n \n--- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c\n+++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c\n@@ -54,6 +54,137 @@\n \n #define ISC_CLK_MAX_DIV\t\t255\n \n+/* This is a list of the formats that the ISC can *output* */\n+static const struct isc_format sama5d2_controller_formats[] = {\n+\t{\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_ARGB444,\n+\t},\n+\t{\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_ARGB555,\n+\t},\n+\t{\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_RGB565,\n+\t},\n+\t{\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_ABGR32,\n+\t},\n+\t{\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_XBGR32,\n+\t},\n+\t{\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_YUV420,\n+\t},\n+\t{\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_YUYV,\n+\t},\n+\t{\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_YUV422P,\n+\t},\n+\t{\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_GREY,\n+\t},\n+\t{\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_Y10,\n+\t},\n+};\n+\n+/* This is a list of formats that the ISC can receive as *input* */\n+static struct isc_format sama5d2_formats_list[] = {\n+\t{\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_SBGGR8,\n+\t\t.mbus_code\t= MEDIA_BUS_FMT_SBGGR8_1X8,\n+\t\t.pfe_cfg0_bps\t= ISC_PFE_CFG0_BPS_EIGHT,\n+\t\t.cfa_baycfg\t= ISC_BAY_CFG_BGBG,\n+\t},\n+\t{\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_SGBRG8,\n+\t\t.mbus_code\t= MEDIA_BUS_FMT_SGBRG8_1X8,\n+\t\t.pfe_cfg0_bps\t= ISC_PFE_CFG0_BPS_EIGHT,\n+\t\t.cfa_baycfg\t= ISC_BAY_CFG_GBGB,\n+\t},\n+\t{\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_SGRBG8,\n+\t\t.mbus_code\t= MEDIA_BUS_FMT_SGRBG8_1X8,\n+\t\t.pfe_cfg0_bps\t= ISC_PFE_CFG0_BPS_EIGHT,\n+\t\t.cfa_baycfg\t= ISC_BAY_CFG_GRGR,\n+\t},\n+\t{\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_SRGGB8,\n+\t\t.mbus_code\t= MEDIA_BUS_FMT_SRGGB8_1X8,\n+\t\t.pfe_cfg0_bps\t= ISC_PFE_CFG0_BPS_EIGHT,\n+\t\t.cfa_baycfg\t= ISC_BAY_CFG_RGRG,\n+\t},\n+\t{\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_SBGGR10,\n+\t\t.mbus_code\t= MEDIA_BUS_FMT_SBGGR10_1X10,\n+\t\t.pfe_cfg0_bps\t= ISC_PFG_CFG0_BPS_TEN,\n+\t\t.cfa_baycfg\t= ISC_BAY_CFG_RGRG,\n+\t},\n+\t{\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_SGBRG10,\n+\t\t.mbus_code\t= MEDIA_BUS_FMT_SGBRG10_1X10,\n+\t\t.pfe_cfg0_bps\t= ISC_PFG_CFG0_BPS_TEN,\n+\t\t.cfa_baycfg\t= ISC_BAY_CFG_GBGB,\n+\t},\n+\t{\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_SGRBG10,\n+\t\t.mbus_code\t= MEDIA_BUS_FMT_SGRBG10_1X10,\n+\t\t.pfe_cfg0_bps\t= ISC_PFG_CFG0_BPS_TEN,\n+\t\t.cfa_baycfg\t= ISC_BAY_CFG_GRGR,\n+\t},\n+\t{\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_SRGGB10,\n+\t\t.mbus_code\t= MEDIA_BUS_FMT_SRGGB10_1X10,\n+\t\t.pfe_cfg0_bps\t= ISC_PFG_CFG0_BPS_TEN,\n+\t\t.cfa_baycfg\t= ISC_BAY_CFG_RGRG,\n+\t},\n+\t{\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_SBGGR12,\n+\t\t.mbus_code\t= MEDIA_BUS_FMT_SBGGR12_1X12,\n+\t\t.pfe_cfg0_bps\t= ISC_PFG_CFG0_BPS_TWELVE,\n+\t\t.cfa_baycfg\t= ISC_BAY_CFG_BGBG,\n+\t},\n+\t{\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_SGBRG12,\n+\t\t.mbus_code\t= MEDIA_BUS_FMT_SGBRG12_1X12,\n+\t\t.pfe_cfg0_bps\t= ISC_PFG_CFG0_BPS_TWELVE,\n+\t\t.cfa_baycfg\t= ISC_BAY_CFG_GBGB,\n+\t},\n+\t{\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_SGRBG12,\n+\t\t.mbus_code\t= MEDIA_BUS_FMT_SGRBG12_1X12,\n+\t\t.pfe_cfg0_bps\t= ISC_PFG_CFG0_BPS_TWELVE,\n+\t\t.cfa_baycfg\t= ISC_BAY_CFG_GRGR,\n+\t},\n+\t{\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_SRGGB12,\n+\t\t.mbus_code\t= MEDIA_BUS_FMT_SRGGB12_1X12,\n+\t\t.pfe_cfg0_bps\t= ISC_PFG_CFG0_BPS_TWELVE,\n+\t\t.cfa_baycfg\t= ISC_BAY_CFG_RGRG,\n+\t},\n+\t{\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_GREY,\n+\t\t.mbus_code\t= MEDIA_BUS_FMT_Y8_1X8,\n+\t\t.pfe_cfg0_bps\t= ISC_PFE_CFG0_BPS_EIGHT,\n+\t},\n+\t{\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_YUYV,\n+\t\t.mbus_code\t= MEDIA_BUS_FMT_YUYV8_2X8,\n+\t\t.pfe_cfg0_bps\t= ISC_PFE_CFG0_BPS_EIGHT,\n+\t},\n+\t{\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_RGB565,\n+\t\t.mbus_code\t= MEDIA_BUS_FMT_RGB565_2X8_LE,\n+\t\t.pfe_cfg0_bps\t= ISC_PFE_CFG0_BPS_EIGHT,\n+\t},\n+\t{\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_Y10,\n+\t\t.mbus_code\t= MEDIA_BUS_FMT_Y10_1X10,\n+\t\t.pfe_cfg0_bps\t= ISC_PFG_CFG0_BPS_TEN,\n+\t},\n+\n+};\n+\n static void isc_sama5d2_config_csc(struct isc_device *isc)\n {\n \tstruct regmap *regmap = isc->regmap;\n@@ -310,6 +441,11 @@ static int atmel_isc_probe(struct platfo\n \tisc->offsets.version = ISC_SAMA5D2_VERSION_OFFSET;\n \tisc->offsets.his_entry = ISC_SAMA5D2_HIS_ENTRY_OFFSET;\n \n+\tisc->controller_formats = sama5d2_controller_formats;\n+\tisc->controller_formats_size = ARRAY_SIZE(sama5d2_controller_formats);\n+\tisc->formats_list = sama5d2_formats_list;\n+\tisc->formats_list_size = ARRAY_SIZE(sama5d2_formats_list);\n+\n \t/* sama5d2-isc - 8 bits per beat */\n \tisc->dcfg = ISC_DCFG_YMBSIZE_BEATS8 | ISC_DCFG_CMBSIZE_BEATS8;\n \n"
  },
  {
    "path": "target/linux/at91/patches-5.10/181-media-atmel-atmel-isc-create-an-adapt-pipeline-callb.patch",
    "content": "From 8601f1fc0a9a22788bfa6369fbbf83b3828a5b42 Mon Sep 17 00:00:00 2001\nFrom: Eugen Hristev <eugen.hristev@microchip.com>\nDate: Tue, 13 Apr 2021 12:57:23 +0200\nSubject: [PATCH 181/247] media: atmel: atmel-isc: create an adapt pipeline\n callback for product specific\n\nOnce the pipeline is set in the base code, create a callback that will adapt\nthe ISC pipeline to each product.\nCreate the adapt_pipeline callback that will be used in this fashion.\n\n[hverkuil: made isc_sama5d2_adapt_pipeline static]\n\nSigned-off-by: Eugen Hristev <eugen.hristev@microchip.com>\nSigned-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>\nSigned-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>\n---\n drivers/media/platform/atmel/atmel-isc-base.c    |  4 ++++\n drivers/media/platform/atmel/atmel-isc.h         |  5 +++++\n drivers/media/platform/atmel/atmel-sama5d2-isc.c | 11 +++++++++++\n 3 files changed, 20 insertions(+)\n\n--- a/drivers/media/platform/atmel/atmel-isc-base.c\n+++ b/drivers/media/platform/atmel/atmel-isc-base.c\n@@ -1059,6 +1059,10 @@ static int isc_try_configure_pipeline(st\n \tdefault:\n \t\tisc->try_config.bits_pipeline = 0x0;\n \t}\n+\n+\t/* Tune the pipeline to product specific */\n+\tisc->adapt_pipeline(isc);\n+\n \treturn 0;\n }\n \n--- a/drivers/media/platform/atmel/atmel-isc.h\n+++ b/drivers/media/platform/atmel/atmel-isc.h\n@@ -235,6 +235,9 @@ struct isc_reg_offsets {\n  * @config_ctrls:\tpointer to a functoin that initializes product\n  *\t\t\tspecific v4l2 controls.\n  *\n+ * @adapt_pipeline:\tpointer to a function that adapts the pipeline bits\n+ *\t\t\tto the product specific pipeline\n+ *\n  * @offsets:\t\tstruct holding the product specific register offsets\n  * @controller_formats:\tpointer to the array of possible formats that the\n  *\t\t\tcontroller can output\n@@ -320,6 +323,8 @@ struct isc_device {\n \n \t\tvoid (*config_ctrls)(struct isc_device *isc,\n \t\t\t\t     const struct v4l2_ctrl_ops *ops);\n+\n+\t\tvoid (*adapt_pipeline)(struct isc_device *isc);\n \t};\n \n \tstruct isc_reg_offsets\t\toffsets;\n--- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c\n+++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c\n@@ -54,6 +54,10 @@\n \n #define ISC_CLK_MAX_DIV\t\t255\n \n+#define ISC_SAMA5D2_PIPELINE \\\n+\t(WB_ENABLE | CFA_ENABLE | CC_ENABLE | GAM_ENABLES | CSC_ENABLE | \\\n+\tCBC_ENABLE | SUB422_ENABLE | SUB420_ENABLE)\n+\n /* This is a list of the formats that the ISC can *output* */\n static const struct isc_format sama5d2_controller_formats[] = {\n \t{\n@@ -257,6 +261,11 @@ static void isc_sama5d2_config_rlp(struc\n \t\t\t   ISC_RLP_CFG_MODE_MASK, rlp_mode);\n }\n \n+static void isc_sama5d2_adapt_pipeline(struct isc_device *isc)\n+{\n+\tisc->try_config.bits_pipeline &= ISC_SAMA5D2_PIPELINE;\n+}\n+\n /* Gamma table with gamma 1/2.2 */\n static const u32 isc_sama5d2_gamma_table[][GAMMA_ENTRIES] = {\n \t/* 0 --> gamma 1/1.8 */\n@@ -431,6 +440,8 @@ static int atmel_isc_probe(struct platfo\n \tisc->config_rlp = isc_sama5d2_config_rlp;\n \tisc->config_ctrls = isc_sama5d2_config_ctrls;\n \n+\tisc->adapt_pipeline = isc_sama5d2_adapt_pipeline;\n+\n \tisc->offsets.csc = ISC_SAMA5D2_CSC_OFFSET;\n \tisc->offsets.cbc = ISC_SAMA5D2_CBC_OFFSET;\n \tisc->offsets.sub422 = ISC_SAMA5D2_SUB422_OFFSET;\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/182-media-atmel-atmel-isc-regs-add-additional-fields-for.patch",
    "content": "From bf032d1a0105939b90072914d88181fbe6187f43 Mon Sep 17 00:00:00 2001\nFrom: Eugen Hristev <eugen.hristev@microchip.com>\nDate: Tue, 13 Apr 2021 12:57:24 +0200\nSubject: [PATCH 182/247] media: atmel: atmel-isc-regs: add additional fields\n for sama7g5 type pipeline\n\nAdd additional fields for registers present in sama7g5 type pipeline.\nExtend register masks for additional bits in sama7g5 type pipeline registers.\n\nSigned-off-by: Eugen Hristev <eugen.hristev@microchip.com>\nSigned-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>\nSigned-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>\n---\n drivers/media/platform/atmel/atmel-isc-regs.h | 16 ++++++++++++++--\n 1 file changed, 14 insertions(+), 2 deletions(-)\n\n--- a/drivers/media/platform/atmel/atmel-isc-regs.h\n+++ b/drivers/media/platform/atmel/atmel-isc-regs.h\n@@ -289,8 +289,18 @@\n #define ISC_RLP_CFG_MODE_ARGB32         0xa\n #define ISC_RLP_CFG_MODE_YYCC           0xb\n #define ISC_RLP_CFG_MODE_YYCC_LIMITED   0xc\n+#define ISC_RLP_CFG_MODE_YCYC           0xd\n #define ISC_RLP_CFG_MODE_MASK           GENMASK(3, 0)\n \n+#define ISC_RLP_CFG_LSH\t\t\tBIT(5)\n+\n+#define ISC_RLP_CFG_YMODE_YUYV\t\t(3 << 6)\n+#define ISC_RLP_CFG_YMODE_YVYU\t\t(2 << 6)\n+#define ISC_RLP_CFG_YMODE_VYUY\t\t(0 << 6)\n+#define ISC_RLP_CFG_YMODE_UYVY\t\t(1 << 6)\n+\n+#define ISC_RLP_CFG_YMODE_MASK\t\tGENMASK(7, 6)\n+\n /* Offset for HIS register specific to sama5d2 product */\n #define ISC_SAMA5D2_HIS_OFFSET\t0\n /* Histogram Control Register */\n@@ -332,13 +342,15 @@\n #define ISC_DCFG_YMBSIZE_BEATS4         (0x1 << 4)\n #define ISC_DCFG_YMBSIZE_BEATS8         (0x2 << 4)\n #define ISC_DCFG_YMBSIZE_BEATS16        (0x3 << 4)\n-#define ISC_DCFG_YMBSIZE_MASK           GENMASK(5, 4)\n+#define ISC_DCFG_YMBSIZE_BEATS32        (0x4 << 4)\n+#define ISC_DCFG_YMBSIZE_MASK           GENMASK(6, 4)\n \n #define ISC_DCFG_CMBSIZE_SINGLE         (0x0 << 8)\n #define ISC_DCFG_CMBSIZE_BEATS4         (0x1 << 8)\n #define ISC_DCFG_CMBSIZE_BEATS8         (0x2 << 8)\n #define ISC_DCFG_CMBSIZE_BEATS16        (0x3 << 8)\n-#define ISC_DCFG_CMBSIZE_MASK           GENMASK(9, 8)\n+#define ISC_DCFG_CMBSIZE_BEATS32        (0x4 << 8)\n+#define ISC_DCFG_CMBSIZE_MASK           GENMASK(10, 8)\n \n /* DMA Control Register */\n #define ISC_DCTRL       0x000003e4\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/183-media-atmel-atmel-isc-base-add-support-for-more-form.patch",
    "content": "From fa9e6cd8f3ba4a277c06e4c1fb01cd69b3a57234 Mon Sep 17 00:00:00 2001\nFrom: Eugen Hristev <eugen.hristev@microchip.com>\nDate: Tue, 13 Apr 2021 12:57:25 +0200\nSubject: [PATCH 183/247] media: atmel: atmel-isc-base: add support for more\n formats and additional pipeline modules\n\nAdd support for additional formats supported by newer pipelines, and for\nadditional pipeline modules.\n\nSigned-off-by: Eugen Hristev <eugen.hristev@microchip.com>\nSigned-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>\nSigned-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>\n---\n drivers/media/platform/atmel/atmel-isc-base.c | 48 +++++++++++++++----\n 1 file changed, 38 insertions(+), 10 deletions(-)\n\n--- a/drivers/media/platform/atmel/atmel-isc-base.c\n+++ b/drivers/media/platform/atmel/atmel-isc-base.c\n@@ -855,6 +855,8 @@ static int isc_try_validate_formats(stru\n \tcase V4L2_PIX_FMT_YUV420:\n \tcase V4L2_PIX_FMT_YUV422P:\n \tcase V4L2_PIX_FMT_YUYV:\n+\tcase V4L2_PIX_FMT_UYVY:\n+\tcase V4L2_PIX_FMT_VYUY:\n \t\tret = 0;\n \t\tyuv = true;\n \t\tbreak;\n@@ -869,6 +871,7 @@ static int isc_try_validate_formats(stru\n \t\tbreak;\n \tcase V4L2_PIX_FMT_GREY:\n \tcase V4L2_PIX_FMT_Y10:\n+\tcase V4L2_PIX_FMT_Y16:\n \t\tret = 0;\n \t\tgrey = true;\n \t\tbreak;\n@@ -899,6 +902,8 @@ static int isc_try_validate_formats(stru\n  */\n static int isc_try_configure_rlp_dma(struct isc_device *isc, bool direct_dump)\n {\n+\tisc->try_config.rlp_cfg_mode = 0;\n+\n \tswitch (isc->try_config.fourcc) {\n \tcase V4L2_PIX_FMT_SBGGR8:\n \tcase V4L2_PIX_FMT_SGBRG8:\n@@ -965,7 +970,19 @@ static int isc_try_configure_rlp_dma(str\n \t\tisc->try_config.bpp = 16;\n \t\tbreak;\n \tcase V4L2_PIX_FMT_YUYV:\n-\t\tisc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_YYCC;\n+\t\tisc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_YCYC | ISC_RLP_CFG_YMODE_YUYV;\n+\t\tisc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED32;\n+\t\tisc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;\n+\t\tisc->try_config.bpp = 16;\n+\t\tbreak;\n+\tcase V4L2_PIX_FMT_UYVY:\n+\t\tisc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_YCYC | ISC_RLP_CFG_YMODE_UYVY;\n+\t\tisc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED32;\n+\t\tisc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;\n+\t\tisc->try_config.bpp = 16;\n+\t\tbreak;\n+\tcase V4L2_PIX_FMT_VYUY:\n+\t\tisc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_YCYC | ISC_RLP_CFG_YMODE_VYUY;\n \t\tisc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED32;\n \t\tisc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;\n \t\tisc->try_config.bpp = 16;\n@@ -976,8 +993,11 @@ static int isc_try_configure_rlp_dma(str\n \t\tisc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;\n \t\tisc->try_config.bpp = 8;\n \t\tbreak;\n+\tcase V4L2_PIX_FMT_Y16:\n+\t\tisc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DATY10 | ISC_RLP_CFG_LSH;\n+\t\tfallthrough;\n \tcase V4L2_PIX_FMT_Y10:\n-\t\tisc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DATY10;\n+\t\tisc->try_config.rlp_cfg_mode |= ISC_RLP_CFG_MODE_DATY10;\n \t\tisc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED16;\n \t\tisc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;\n \t\tisc->try_config.bpp = 16;\n@@ -1011,7 +1031,8 @@ static int isc_try_configure_pipeline(st\n \t\t/* if sensor format is RAW, we convert inside ISC */\n \t\tif (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) {\n \t\t\tisc->try_config.bits_pipeline = CFA_ENABLE |\n-\t\t\t\tWB_ENABLE | GAM_ENABLES;\n+\t\t\t\tWB_ENABLE | GAM_ENABLES | DPC_BLCENABLE |\n+\t\t\t\tCC_ENABLE;\n \t\t} else {\n \t\t\tisc->try_config.bits_pipeline = 0x0;\n \t\t}\n@@ -1020,8 +1041,9 @@ static int isc_try_configure_pipeline(st\n \t\t/* if sensor format is RAW, we convert inside ISC */\n \t\tif (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) {\n \t\t\tisc->try_config.bits_pipeline = CFA_ENABLE |\n-\t\t\t\tCSC_ENABLE | WB_ENABLE | GAM_ENABLES |\n-\t\t\t\tSUB420_ENABLE | SUB422_ENABLE | CBC_ENABLE;\n+\t\t\t\tCSC_ENABLE | GAM_ENABLES | WB_ENABLE |\n+\t\t\t\tSUB420_ENABLE | SUB422_ENABLE | CBC_ENABLE |\n+\t\t\t\tDPC_BLCENABLE;\n \t\t} else {\n \t\t\tisc->try_config.bits_pipeline = 0x0;\n \t\t}\n@@ -1031,33 +1053,39 @@ static int isc_try_configure_pipeline(st\n \t\tif (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) {\n \t\t\tisc->try_config.bits_pipeline = CFA_ENABLE |\n \t\t\t\tCSC_ENABLE | WB_ENABLE | GAM_ENABLES |\n-\t\t\t\tSUB422_ENABLE | CBC_ENABLE;\n+\t\t\t\tSUB422_ENABLE | CBC_ENABLE | DPC_BLCENABLE;\n \t\t} else {\n \t\t\tisc->try_config.bits_pipeline = 0x0;\n \t\t}\n \t\tbreak;\n \tcase V4L2_PIX_FMT_YUYV:\n+\tcase V4L2_PIX_FMT_UYVY:\n+\tcase V4L2_PIX_FMT_VYUY:\n \t\t/* if sensor format is RAW, we convert inside ISC */\n \t\tif (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) {\n \t\t\tisc->try_config.bits_pipeline = CFA_ENABLE |\n \t\t\t\tCSC_ENABLE | WB_ENABLE | GAM_ENABLES |\n-\t\t\t\tSUB422_ENABLE | CBC_ENABLE;\n+\t\t\t\tSUB422_ENABLE | CBC_ENABLE | DPC_BLCENABLE;\n \t\t} else {\n \t\t\tisc->try_config.bits_pipeline = 0x0;\n \t\t}\n \t\tbreak;\n \tcase V4L2_PIX_FMT_GREY:\n-\t\tif (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) {\n+\tcase V4L2_PIX_FMT_Y16:\n \t\t/* if sensor format is RAW, we convert inside ISC */\n+\t\tif (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) {\n \t\t\tisc->try_config.bits_pipeline = CFA_ENABLE |\n \t\t\t\tCSC_ENABLE | WB_ENABLE | GAM_ENABLES |\n-\t\t\t\tCBC_ENABLE;\n+\t\t\t\tCBC_ENABLE | DPC_BLCENABLE;\n \t\t} else {\n \t\t\tisc->try_config.bits_pipeline = 0x0;\n \t\t}\n \t\tbreak;\n \tdefault:\n-\t\tisc->try_config.bits_pipeline = 0x0;\n+\t\tif (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code))\n+\t\t\tisc->try_config.bits_pipeline = WB_ENABLE | DPC_BLCENABLE;\n+\t\telse\n+\t\t\tisc->try_config.bits_pipeline = 0x0;\n \t}\n \n \t/* Tune the pipeline to product specific */\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/184-media-atmel-atmel-isc-sama5d2-remove-duplicate-defin.patch",
    "content": "From b36d11efc134f9f1e2804270d08b9dbefdee4a0d Mon Sep 17 00:00:00 2001\nFrom: Eugen Hristev <eugen.hristev@microchip.com>\nDate: Tue, 13 Apr 2021 12:57:26 +0200\nSubject: [PATCH 184/247] media: atmel: atmel-isc-sama5d2: remove duplicate\n define\n\nRemove a duplicate definition of clock max divider\n\nSigned-off-by: Eugen Hristev <eugen.hristev@microchip.com>\nSigned-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>\nSigned-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>\n---\n drivers/media/platform/atmel/atmel-sama5d2-isc.c | 2 --\n 1 file changed, 2 deletions(-)\n\n--- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c\n+++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c\n@@ -52,8 +52,6 @@\n #define ISC_SAMA5D2_MAX_SUPPORT_WIDTH   2592\n #define ISC_SAMA5D2_MAX_SUPPORT_HEIGHT  1944\n \n-#define ISC_CLK_MAX_DIV\t\t255\n-\n #define ISC_SAMA5D2_PIPELINE \\\n \t(WB_ENABLE | CFA_ENABLE | CC_ENABLE | GAM_ENABLES | CSC_ENABLE | \\\n \tCBC_ENABLE | SUB422_ENABLE | SUB420_ENABLE)\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/185-media-atmel-atmel-isc-add-microchip-xisc-driver.patch",
    "content": "From 74fd7ea680cb1a3a43b51a7279aea45efdf9ec42 Mon Sep 17 00:00:00 2001\nFrom: Eugen Hristev <eugen.hristev@microchip.com>\nDate: Tue, 13 Apr 2021 12:57:29 +0200\nSubject: [PATCH 185/247] media: atmel: atmel-isc: add microchip-xisc driver\n\nAdd driver for the extended variant of the isc, the microchip XISC\npresent on sama7g5 product.\n\n[hverkuil: drop MODULE_SUPPORTED_DEVICE, no longer exists]\n[hverkuil: made isc_sama7g5_config_csc et al static]\n[hverkuil: made sama7g5_controller_formats et al static]\n\nSigned-off-by: Eugen Hristev <eugen.hristev@microchip.com>\nSigned-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>\nSigned-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>\n---\n drivers/media/platform/Makefile               |   1 +\n drivers/media/platform/atmel/Kconfig          |  11 +\n drivers/media/platform/atmel/Makefile         |   2 +\n drivers/media/platform/atmel/atmel-isc-base.c |   2 +-\n drivers/media/platform/atmel/atmel-isc-regs.h |  26 +\n .../media/platform/atmel/atmel-sama7g5-isc.c  | 630 ++++++++++++++++++\n 6 files changed, 671 insertions(+), 1 deletion(-)\n create mode 100644 drivers/media/platform/atmel/atmel-sama7g5-isc.c\n\n--- a/drivers/media/platform/Makefile\n+++ b/drivers/media/platform/Makefile\n@@ -64,6 +64,7 @@ obj-$(CONFIG_VIDEO_RCAR_VIN)\t\t+= rcar-vi\n \n obj-$(CONFIG_VIDEO_ATMEL_ISC)\t\t+= atmel/\n obj-$(CONFIG_VIDEO_ATMEL_ISI)\t\t+= atmel/\n+obj-$(CONFIG_VIDEO_ATMEL_XISC)\t\t+= atmel/\n \n obj-$(CONFIG_VIDEO_STM32_DCMI)\t\t+= stm32/\n \n--- a/drivers/media/platform/atmel/Kconfig\n+++ b/drivers/media/platform/atmel/Kconfig\n@@ -12,6 +12,17 @@ config VIDEO_ATMEL_ISC\n \t   This module makes the ATMEL Image Sensor Controller available\n \t   as a v4l2 device.\n \n+config VIDEO_ATMEL_XISC\n+\ttristate \"ATMEL eXtended Image Sensor Controller (XISC) support\"\n+\tdepends on VIDEO_V4L2 && COMMON_CLK && VIDEO_V4L2_SUBDEV_API\n+\tdepends on ARCH_AT91 || COMPILE_TEST\n+\tselect VIDEOBUF2_DMA_CONTIG\n+\tselect REGMAP_MMIO\n+\tselect V4L2_FWNODE\n+\thelp\n+\t   This module makes the ATMEL eXtended Image Sensor Controller\n+\t   available as a v4l2 device.\n+\n config VIDEO_ATMEL_ISI\n \ttristate \"ATMEL Image Sensor Interface (ISI) support\"\n \tdepends on VIDEO_V4L2 && OF\n--- a/drivers/media/platform/atmel/Makefile\n+++ b/drivers/media/platform/atmel/Makefile\n@@ -1,5 +1,7 @@\n # SPDX-License-Identifier: GPL-2.0-only\n atmel-isc-objs = atmel-sama5d2-isc.o atmel-isc-base.o\n+atmel-xisc-objs = atmel-sama7g5-isc.o atmel-isc-base.o\n \n obj-$(CONFIG_VIDEO_ATMEL_ISI) += atmel-isi.o\n obj-$(CONFIG_VIDEO_ATMEL_ISC) += atmel-isc.o\n+obj-$(CONFIG_VIDEO_ATMEL_XISC) += atmel-xisc.o\n--- a/drivers/media/platform/atmel/atmel-isc-base.c\n+++ b/drivers/media/platform/atmel/atmel-isc-base.c\n@@ -600,7 +600,7 @@ static int isc_configure(struct isc_devi\n \tmask = ISC_PFE_CFG0_BPS_MASK | ISC_PFE_CFG0_HPOL_LOW |\n \t       ISC_PFE_CFG0_VPOL_LOW | ISC_PFE_CFG0_PPOL_LOW |\n \t       ISC_PFE_CFG0_MODE_MASK | ISC_PFE_CFG0_CCIR_CRC |\n-\t\t   ISC_PFE_CFG0_CCIR656;\n+\t       ISC_PFE_CFG0_CCIR656 | ISC_PFE_CFG0_MIPI;\n \n \tregmap_update_bits(regmap, ISC_PFE_CFG0, mask, pfe_cfg0);\n \n--- a/drivers/media/platform/atmel/atmel-isc-regs.h\n+++ b/drivers/media/platform/atmel/atmel-isc-regs.h\n@@ -26,6 +26,7 @@\n #define ISC_PFE_CFG0_PPOL_LOW   BIT(2)\n #define ISC_PFE_CFG0_CCIR656    BIT(9)\n #define ISC_PFE_CFG0_CCIR_CRC   BIT(10)\n+#define ISC_PFE_CFG0_MIPI\tBIT(14)\n \n #define ISC_PFE_CFG0_MODE_PROGRESSIVE   (0x0 << 4)\n #define ISC_PFE_CFG0_MODE_MASK          GENMASK(6, 4)\n@@ -184,6 +185,8 @@\n /* ISC Gamma Correction Control Register */\n #define ISC_GAM_CTRL    0x00000094\n \n+#define ISC_GAM_CTRL_BIPART\tBIT(4)\n+\n /* ISC_Gamma Correction Blue Entry Register */\n #define ISC_GAM_BENTRY\t0x00000098\n \n@@ -222,6 +225,8 @@\n \n /* Offset for CSC register specific to sama5d2 product */\n #define ISC_SAMA5D2_CSC_OFFSET\t0\n+/* Offset for CSC register specific to sama7g5 product */\n+#define ISC_SAMA7G5_CSC_OFFSET\t0x11c\n \n /* Color Space Conversion Control Register */\n #define ISC_CSC_CTRL    0x00000398\n@@ -246,6 +251,8 @@\n \n /* Offset for CBC register specific to sama5d2 product */\n #define ISC_SAMA5D2_CBC_OFFSET\t0\n+/* Offset for CBC register specific to sama7g5 product */\n+#define ISC_SAMA7G5_CBC_OFFSET\t0x11c\n \n /* Contrast And Brightness Control Register */\n #define ISC_CBC_CTRL    0x000003b4\n@@ -261,18 +268,30 @@\n #define ISC_CBC_CONTRAST\t0x000003c0\n #define ISC_CBC_CONTRAST_MASK\tGENMASK(11, 0)\n \n+/* Hue Register */\n+#define ISC_CBCHS_HUE\t0x4e0\n+/* Saturation Register */\n+#define ISC_CBCHS_SAT\t0x4e4\n+\n /* Offset for SUB422 register specific to sama5d2 product */\n #define ISC_SAMA5D2_SUB422_OFFSET\t0\n+/* Offset for SUB422 register specific to sama7g5 product */\n+#define ISC_SAMA7G5_SUB422_OFFSET\t0x124\n+\n /* Subsampling 4:4:4 to 4:2:2 Control Register */\n #define ISC_SUB422_CTRL 0x000003c4\n \n /* Offset for SUB420 register specific to sama5d2 product */\n #define ISC_SAMA5D2_SUB420_OFFSET\t0\n+/* Offset for SUB420 register specific to sama7g5 product */\n+#define ISC_SAMA7G5_SUB420_OFFSET\t0x124\n /* Subsampling 4:2:2 to 4:2:0 Control Register */\n #define ISC_SUB420_CTRL 0x000003cc\n \n /* Offset for RLP register specific to sama5d2 product */\n #define ISC_SAMA5D2_RLP_OFFSET\t0\n+/* Offset for RLP register specific to sama7g5 product */\n+#define ISC_SAMA7G5_RLP_OFFSET\t0x124\n /* Rounding, Limiting and Packing Configuration Register */\n #define ISC_RLP_CFG     0x000003d0\n \n@@ -303,6 +322,8 @@\n \n /* Offset for HIS register specific to sama5d2 product */\n #define ISC_SAMA5D2_HIS_OFFSET\t0\n+/* Offset for HIS register specific to sama7g5 product */\n+#define ISC_SAMA7G5_HIS_OFFSET\t0x124\n /* Histogram Control Register */\n #define ISC_HIS_CTRL\t0x000003d4\n \n@@ -326,6 +347,8 @@\n \n /* Offset for DMA register specific to sama5d2 product */\n #define ISC_SAMA5D2_DMA_OFFSET\t0\n+/* Offset for DMA register specific to sama7g5 product */\n+#define ISC_SAMA7G5_DMA_OFFSET\t0x13c\n \n /* DMA Configuration Register */\n #define ISC_DCFG        0x000003e0\n@@ -376,11 +399,14 @@\n \n /* Offset for version register specific to sama5d2 product */\n #define ISC_SAMA5D2_VERSION_OFFSET\t0\n+#define ISC_SAMA7G5_VERSION_OFFSET\t0x13c\n /* Version Register */\n #define ISC_VERSION\t0x0000040c\n \n /* Offset for version register specific to sama5d2 product */\n #define ISC_SAMA5D2_HIS_ENTRY_OFFSET\t0\n+/* Offset for version register specific to sama7g5 product */\n+#define ISC_SAMA7G5_HIS_ENTRY_OFFSET\t0x14c\n /* Histogram Entry */\n #define ISC_HIS_ENTRY\t0x00000410\n \n--- /dev/null\n+++ b/drivers/media/platform/atmel/atmel-sama7g5-isc.c\n@@ -0,0 +1,630 @@\n+// SPDX-License-Identifier: GPL-2.0\n+/*\n+ * Microchip eXtended Image Sensor Controller (XISC) driver\n+ *\n+ * Copyright (C) 2019-2021 Microchip Technology, Inc. and its subsidiaries\n+ *\n+ * Author: Eugen Hristev <eugen.hristev@microchip.com>\n+ *\n+ * Sensor-->PFE-->DPC-->WB-->CFA-->CC-->GAM-->VHXS-->CSC-->CBHS-->SUB-->RLP-->DMA-->HIS\n+ *\n+ * ISC video pipeline integrates the following submodules:\n+ * PFE: Parallel Front End to sample the camera sensor input stream\n+ * DPC: Defective Pixel Correction with black offset correction, green disparity\n+ *      correction and defective pixel correction (3 modules total)\n+ *  WB: Programmable white balance in the Bayer domain\n+ * CFA: Color filter array interpolation module\n+ *  CC: Programmable color correction\n+ * GAM: Gamma correction\n+ *VHXS: Vertical and Horizontal Scaler\n+ * CSC: Programmable color space conversion\n+ *CBHS: Contrast Brightness Hue and Saturation control\n+ * SUB: This module performs YCbCr444 to YCbCr420 chrominance subsampling\n+ * RLP: This module performs rounding, range limiting\n+ *      and packing of the incoming data\n+ * DMA: This module performs DMA master accesses to write frames to external RAM\n+ * HIS: Histogram module performs statistic counters on the frames\n+ */\n+\n+#include <linux/clk.h>\n+#include <linux/clkdev.h>\n+#include <linux/clk-provider.h>\n+#include <linux/delay.h>\n+#include <linux/interrupt.h>\n+#include <linux/math64.h>\n+#include <linux/module.h>\n+#include <linux/of.h>\n+#include <linux/of_graph.h>\n+#include <linux/platform_device.h>\n+#include <linux/pm_runtime.h>\n+#include <linux/regmap.h>\n+#include <linux/videodev2.h>\n+\n+#include <media/v4l2-ctrls.h>\n+#include <media/v4l2-device.h>\n+#include <media/v4l2-event.h>\n+#include <media/v4l2-image-sizes.h>\n+#include <media/v4l2-ioctl.h>\n+#include <media/v4l2-fwnode.h>\n+#include <media/v4l2-subdev.h>\n+#include <media/videobuf2-dma-contig.h>\n+\n+#include \"atmel-isc-regs.h\"\n+#include \"atmel-isc.h\"\n+\n+#define ISC_SAMA7G5_MAX_SUPPORT_WIDTH   3264\n+#define ISC_SAMA7G5_MAX_SUPPORT_HEIGHT  2464\n+\n+#define ISC_SAMA7G5_PIPELINE \\\n+\t(WB_ENABLE | CFA_ENABLE | CC_ENABLE | GAM_ENABLES | CSC_ENABLE | \\\n+\tCBC_ENABLE | SUB422_ENABLE | SUB420_ENABLE)\n+\n+/* This is a list of the formats that the ISC can *output* */\n+static const struct isc_format sama7g5_controller_formats[] = {\n+\t{\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_ARGB444,\n+\t},\n+\t{\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_ARGB555,\n+\t},\n+\t{\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_RGB565,\n+\t},\n+\t{\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_ABGR32,\n+\t},\n+\t{\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_XBGR32,\n+\t},\n+\t{\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_YUV420,\n+\t},\n+\t{\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_UYVY,\n+\t},\n+\t{\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_VYUY,\n+\t},\n+\t{\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_YUYV,\n+\t},\n+\t{\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_YUV422P,\n+\t},\n+\t{\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_GREY,\n+\t},\n+\t{\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_Y10,\n+\t},\n+\t{\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_Y16,\n+\t},\n+};\n+\n+/* This is a list of formats that the ISC can receive as *input* */\n+static struct isc_format sama7g5_formats_list[] = {\n+\t{\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_SBGGR8,\n+\t\t.mbus_code\t= MEDIA_BUS_FMT_SBGGR8_1X8,\n+\t\t.pfe_cfg0_bps\t= ISC_PFE_CFG0_BPS_EIGHT,\n+\t\t.cfa_baycfg\t= ISC_BAY_CFG_BGBG,\n+\t},\n+\t{\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_SGBRG8,\n+\t\t.mbus_code\t= MEDIA_BUS_FMT_SGBRG8_1X8,\n+\t\t.pfe_cfg0_bps\t= ISC_PFE_CFG0_BPS_EIGHT,\n+\t\t.cfa_baycfg\t= ISC_BAY_CFG_GBGB,\n+\t},\n+\t{\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_SGRBG8,\n+\t\t.mbus_code\t= MEDIA_BUS_FMT_SGRBG8_1X8,\n+\t\t.pfe_cfg0_bps\t= ISC_PFE_CFG0_BPS_EIGHT,\n+\t\t.cfa_baycfg\t= ISC_BAY_CFG_GRGR,\n+\t},\n+\t{\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_SRGGB8,\n+\t\t.mbus_code\t= MEDIA_BUS_FMT_SRGGB8_1X8,\n+\t\t.pfe_cfg0_bps\t= ISC_PFE_CFG0_BPS_EIGHT,\n+\t\t.cfa_baycfg\t= ISC_BAY_CFG_RGRG,\n+\t},\n+\t{\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_SBGGR10,\n+\t\t.mbus_code\t= MEDIA_BUS_FMT_SBGGR10_1X10,\n+\t\t.pfe_cfg0_bps\t= ISC_PFG_CFG0_BPS_TEN,\n+\t\t.cfa_baycfg\t= ISC_BAY_CFG_RGRG,\n+\t},\n+\t{\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_SGBRG10,\n+\t\t.mbus_code\t= MEDIA_BUS_FMT_SGBRG10_1X10,\n+\t\t.pfe_cfg0_bps\t= ISC_PFG_CFG0_BPS_TEN,\n+\t\t.cfa_baycfg\t= ISC_BAY_CFG_GBGB,\n+\t},\n+\t{\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_SGRBG10,\n+\t\t.mbus_code\t= MEDIA_BUS_FMT_SGRBG10_1X10,\n+\t\t.pfe_cfg0_bps\t= ISC_PFG_CFG0_BPS_TEN,\n+\t\t.cfa_baycfg\t= ISC_BAY_CFG_GRGR,\n+\t},\n+\t{\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_SRGGB10,\n+\t\t.mbus_code\t= MEDIA_BUS_FMT_SRGGB10_1X10,\n+\t\t.pfe_cfg0_bps\t= ISC_PFG_CFG0_BPS_TEN,\n+\t\t.cfa_baycfg\t= ISC_BAY_CFG_RGRG,\n+\t},\n+\t{\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_SBGGR12,\n+\t\t.mbus_code\t= MEDIA_BUS_FMT_SBGGR12_1X12,\n+\t\t.pfe_cfg0_bps\t= ISC_PFG_CFG0_BPS_TWELVE,\n+\t\t.cfa_baycfg\t= ISC_BAY_CFG_BGBG,\n+\t},\n+\t{\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_SGBRG12,\n+\t\t.mbus_code\t= MEDIA_BUS_FMT_SGBRG12_1X12,\n+\t\t.pfe_cfg0_bps\t= ISC_PFG_CFG0_BPS_TWELVE,\n+\t\t.cfa_baycfg\t= ISC_BAY_CFG_GBGB,\n+\t},\n+\t{\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_SGRBG12,\n+\t\t.mbus_code\t= MEDIA_BUS_FMT_SGRBG12_1X12,\n+\t\t.pfe_cfg0_bps\t= ISC_PFG_CFG0_BPS_TWELVE,\n+\t\t.cfa_baycfg\t= ISC_BAY_CFG_GRGR,\n+\t},\n+\t{\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_SRGGB12,\n+\t\t.mbus_code\t= MEDIA_BUS_FMT_SRGGB12_1X12,\n+\t\t.pfe_cfg0_bps\t= ISC_PFG_CFG0_BPS_TWELVE,\n+\t\t.cfa_baycfg\t= ISC_BAY_CFG_RGRG,\n+\t},\n+\t{\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_GREY,\n+\t\t.mbus_code\t= MEDIA_BUS_FMT_Y8_1X8,\n+\t\t.pfe_cfg0_bps\t= ISC_PFE_CFG0_BPS_EIGHT,\n+\t},\n+\t{\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_YUYV,\n+\t\t.mbus_code\t= MEDIA_BUS_FMT_YUYV8_2X8,\n+\t\t.pfe_cfg0_bps\t= ISC_PFE_CFG0_BPS_EIGHT,\n+\t},\n+\t{\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_UYVY,\n+\t\t.mbus_code\t= MEDIA_BUS_FMT_YUYV8_2X8,\n+\t\t.pfe_cfg0_bps\t= ISC_PFE_CFG0_BPS_EIGHT,\n+\t},\n+\t{\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_RGB565,\n+\t\t.mbus_code\t= MEDIA_BUS_FMT_RGB565_2X8_LE,\n+\t\t.pfe_cfg0_bps\t= ISC_PFE_CFG0_BPS_EIGHT,\n+\t},\n+\t{\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_Y10,\n+\t\t.mbus_code\t= MEDIA_BUS_FMT_Y10_1X10,\n+\t\t.pfe_cfg0_bps\t= ISC_PFG_CFG0_BPS_TEN,\n+\t},\n+\n+};\n+\n+static void isc_sama7g5_config_csc(struct isc_device *isc)\n+{\n+\tstruct regmap *regmap = isc->regmap;\n+\n+\t/* Convert RGB to YUV */\n+\tregmap_write(regmap, ISC_CSC_YR_YG + isc->offsets.csc,\n+\t\t     0x42 | (0x81 << 16));\n+\tregmap_write(regmap, ISC_CSC_YB_OY + isc->offsets.csc,\n+\t\t     0x19 | (0x10 << 16));\n+\tregmap_write(regmap, ISC_CSC_CBR_CBG + isc->offsets.csc,\n+\t\t     0xFDA | (0xFB6 << 16));\n+\tregmap_write(regmap, ISC_CSC_CBB_OCB + isc->offsets.csc,\n+\t\t     0x70 | (0x80 << 16));\n+\tregmap_write(regmap, ISC_CSC_CRR_CRG + isc->offsets.csc,\n+\t\t     0x70 | (0xFA2 << 16));\n+\tregmap_write(regmap, ISC_CSC_CRB_OCR + isc->offsets.csc,\n+\t\t     0xFEE | (0x80 << 16));\n+}\n+\n+static void isc_sama7g5_config_cbc(struct isc_device *isc)\n+{\n+\tstruct regmap *regmap = isc->regmap;\n+\n+\t/* Configure what is set via v4l2 ctrls */\n+\tregmap_write(regmap, ISC_CBC_BRIGHT + isc->offsets.cbc, isc->ctrls.brightness);\n+\tregmap_write(regmap, ISC_CBC_CONTRAST + isc->offsets.cbc, isc->ctrls.contrast);\n+\t/* Configure Hue and Saturation as neutral midpoint */\n+\tregmap_write(regmap, ISC_CBCHS_HUE, 0);\n+\tregmap_write(regmap, ISC_CBCHS_SAT, (1 << 4));\n+}\n+\n+static void isc_sama7g5_config_cc(struct isc_device *isc)\n+{\n+\tstruct regmap *regmap = isc->regmap;\n+\n+\t/* Configure each register at the neutral fixed point 1.0 or 0.0 */\n+\tregmap_write(regmap, ISC_CC_RR_RG, (1 << 8));\n+\tregmap_write(regmap, ISC_CC_RB_OR, 0);\n+\tregmap_write(regmap, ISC_CC_GR_GG, (1 << 8) << 16);\n+\tregmap_write(regmap, ISC_CC_GB_OG, 0);\n+\tregmap_write(regmap, ISC_CC_BR_BG, 0);\n+\tregmap_write(regmap, ISC_CC_BB_OB, (1 << 8));\n+}\n+\n+static void isc_sama7g5_config_ctrls(struct isc_device *isc,\n+\t\t\t\t     const struct v4l2_ctrl_ops *ops)\n+{\n+\tstruct isc_ctrls *ctrls = &isc->ctrls;\n+\tstruct v4l2_ctrl_handler *hdl = &ctrls->handler;\n+\n+\tctrls->contrast = 16;\n+\n+\tv4l2_ctrl_new_std(hdl, ops, V4L2_CID_CONTRAST, -2048, 2047, 1, 16);\n+}\n+\n+static void isc_sama7g5_config_dpc(struct isc_device *isc)\n+{\n+\tu32 bay_cfg = isc->config.sd_format->cfa_baycfg;\n+\tstruct regmap *regmap = isc->regmap;\n+\n+\tregmap_update_bits(regmap, ISC_DPC_CFG, ISC_DPC_CFG_BLOFF_MASK,\n+\t\t\t   (64 << ISC_DPC_CFG_BLOFF_SHIFT));\n+\tregmap_update_bits(regmap, ISC_DPC_CFG, ISC_DPC_CFG_BAYCFG_MASK,\n+\t\t\t   (bay_cfg << ISC_DPC_CFG_BAYCFG_SHIFT));\n+}\n+\n+static void isc_sama7g5_config_gam(struct isc_device *isc)\n+{\n+\tstruct regmap *regmap = isc->regmap;\n+\n+\tregmap_update_bits(regmap, ISC_GAM_CTRL, ISC_GAM_CTRL_BIPART,\n+\t\t\t   ISC_GAM_CTRL_BIPART);\n+}\n+\n+static void isc_sama7g5_config_rlp(struct isc_device *isc)\n+{\n+\tstruct regmap *regmap = isc->regmap;\n+\tu32 rlp_mode = isc->config.rlp_cfg_mode;\n+\n+\tregmap_update_bits(regmap, ISC_RLP_CFG + isc->offsets.rlp,\n+\t\t\t   ISC_RLP_CFG_MODE_MASK | ISC_RLP_CFG_LSH |\n+\t\t\t   ISC_RLP_CFG_YMODE_MASK, rlp_mode);\n+}\n+\n+static void isc_sama7g5_adapt_pipeline(struct isc_device *isc)\n+{\n+\tisc->try_config.bits_pipeline &= ISC_SAMA7G5_PIPELINE;\n+}\n+\n+/* Gamma table with gamma 1/2.2 */\n+static const u32 isc_sama7g5_gamma_table[][GAMMA_ENTRIES] = {\n+\t/* index 0 --> gamma bipartite */\n+\t{\n+\t      0x980,  0x4c0320,  0x650260,  0x7801e0,  0x8701a0,  0x940180,\n+\t   0xa00160,  0xab0120,  0xb40120,  0xbd0120,  0xc60100,  0xce0100,\n+\t   0xd600e0,  0xdd00e0,  0xe400e0,  0xeb00c0,  0xf100c0,  0xf700c0,\n+\t   0xfd00c0, 0x10300a0, 0x10800c0, 0x10e00a0, 0x11300a0, 0x11800a0,\n+\t  0x11d00a0, 0x12200a0, 0x12700a0, 0x12c0080, 0x13000a0, 0x1350080,\n+\t  0x13900a0, 0x13e0080, 0x1420076, 0x17d0062, 0x1ae0054, 0x1d8004a,\n+\t  0x1fd0044, 0x21f003e, 0x23e003a, 0x25b0036, 0x2760032, 0x28f0030,\n+\t  0x2a7002e, 0x2be002c, 0x2d4002c, 0x2ea0028, 0x2fe0028, 0x3120026,\n+\t  0x3250024, 0x3370024, 0x3490022, 0x35a0022, 0x36b0020, 0x37b0020,\n+\t  0x38b0020, 0x39b001e, 0x3aa001e, 0x3b9001c, 0x3c7001c, 0x3d5001c,\n+\t  0x3e3001c, 0x3f1001c, 0x3ff001a, 0x40c001a },\n+};\n+\n+static int xisc_parse_dt(struct device *dev, struct isc_device *isc)\n+{\n+\tstruct device_node *np = dev->of_node;\n+\tstruct device_node *epn = NULL;\n+\tstruct isc_subdev_entity *subdev_entity;\n+\tunsigned int flags;\n+\tint ret;\n+\tbool mipi_mode;\n+\n+\tINIT_LIST_HEAD(&isc->subdev_entities);\n+\n+\tmipi_mode = of_property_read_bool(np, \"microchip,mipi-mode\");\n+\n+\twhile (1) {\n+\t\tstruct v4l2_fwnode_endpoint v4l2_epn = { .bus_type = 0 };\n+\n+\t\tepn = of_graph_get_next_endpoint(np, epn);\n+\t\tif (!epn)\n+\t\t\treturn 0;\n+\n+\t\tret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(epn),\n+\t\t\t\t\t\t &v4l2_epn);\n+\t\tif (ret) {\n+\t\t\tret = -EINVAL;\n+\t\t\tdev_err(dev, \"Could not parse the endpoint\\n\");\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\tsubdev_entity = devm_kzalloc(dev, sizeof(*subdev_entity),\n+\t\t\t\t\t     GFP_KERNEL);\n+\t\tif (!subdev_entity) {\n+\t\t\tret = -ENOMEM;\n+\t\t\tbreak;\n+\t\t}\n+\t\tsubdev_entity->epn = epn;\n+\n+\t\tflags = v4l2_epn.bus.parallel.flags;\n+\n+\t\tif (flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)\n+\t\t\tsubdev_entity->pfe_cfg0 = ISC_PFE_CFG0_HPOL_LOW;\n+\n+\t\tif (flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)\n+\t\t\tsubdev_entity->pfe_cfg0 |= ISC_PFE_CFG0_VPOL_LOW;\n+\n+\t\tif (flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)\n+\t\t\tsubdev_entity->pfe_cfg0 |= ISC_PFE_CFG0_PPOL_LOW;\n+\n+\t\tif (v4l2_epn.bus_type == V4L2_MBUS_BT656)\n+\t\t\tsubdev_entity->pfe_cfg0 |= ISC_PFE_CFG0_CCIR_CRC |\n+\t\t\t\t\tISC_PFE_CFG0_CCIR656;\n+\n+\t\tif (mipi_mode)\n+\t\t\tsubdev_entity->pfe_cfg0 |= ISC_PFE_CFG0_MIPI;\n+\n+\t\tlist_add_tail(&subdev_entity->list, &isc->subdev_entities);\n+\t}\n+\tof_node_put(epn);\n+\n+\treturn ret;\n+}\n+\n+static int microchip_xisc_probe(struct platform_device *pdev)\n+{\n+\tstruct device *dev = &pdev->dev;\n+\tstruct isc_device *isc;\n+\tstruct resource *res;\n+\tvoid __iomem *io_base;\n+\tstruct isc_subdev_entity *subdev_entity;\n+\tint irq;\n+\tint ret;\n+\tu32 ver;\n+\n+\tisc = devm_kzalloc(dev, sizeof(*isc), GFP_KERNEL);\n+\tif (!isc)\n+\t\treturn -ENOMEM;\n+\n+\tplatform_set_drvdata(pdev, isc);\n+\tisc->dev = dev;\n+\n+\tres = platform_get_resource(pdev, IORESOURCE_MEM, 0);\n+\tio_base = devm_ioremap_resource(dev, res);\n+\tif (IS_ERR(io_base))\n+\t\treturn PTR_ERR(io_base);\n+\n+\tisc->regmap = devm_regmap_init_mmio(dev, io_base, &isc_regmap_config);\n+\tif (IS_ERR(isc->regmap)) {\n+\t\tret = PTR_ERR(isc->regmap);\n+\t\tdev_err(dev, \"failed to init register map: %d\\n\", ret);\n+\t\treturn ret;\n+\t}\n+\n+\tirq = platform_get_irq(pdev, 0);\n+\tif (irq < 0)\n+\t\treturn irq;\n+\n+\tret = devm_request_irq(dev, irq, isc_interrupt, 0,\n+\t\t\t       \"microchip-sama7g5-xisc\", isc);\n+\tif (ret < 0) {\n+\t\tdev_err(dev, \"can't register ISR for IRQ %u (ret=%i)\\n\",\n+\t\t\tirq, ret);\n+\t\treturn ret;\n+\t}\n+\n+\tisc->gamma_table = isc_sama7g5_gamma_table;\n+\tisc->gamma_max = 0;\n+\n+\tisc->max_width = ISC_SAMA7G5_MAX_SUPPORT_WIDTH;\n+\tisc->max_height = ISC_SAMA7G5_MAX_SUPPORT_HEIGHT;\n+\n+\tisc->config_dpc = isc_sama7g5_config_dpc;\n+\tisc->config_csc = isc_sama7g5_config_csc;\n+\tisc->config_cbc = isc_sama7g5_config_cbc;\n+\tisc->config_cc = isc_sama7g5_config_cc;\n+\tisc->config_gam = isc_sama7g5_config_gam;\n+\tisc->config_rlp = isc_sama7g5_config_rlp;\n+\tisc->config_ctrls = isc_sama7g5_config_ctrls;\n+\n+\tisc->adapt_pipeline = isc_sama7g5_adapt_pipeline;\n+\n+\tisc->offsets.csc = ISC_SAMA7G5_CSC_OFFSET;\n+\tisc->offsets.cbc = ISC_SAMA7G5_CBC_OFFSET;\n+\tisc->offsets.sub422 = ISC_SAMA7G5_SUB422_OFFSET;\n+\tisc->offsets.sub420 = ISC_SAMA7G5_SUB420_OFFSET;\n+\tisc->offsets.rlp = ISC_SAMA7G5_RLP_OFFSET;\n+\tisc->offsets.his = ISC_SAMA7G5_HIS_OFFSET;\n+\tisc->offsets.dma = ISC_SAMA7G5_DMA_OFFSET;\n+\tisc->offsets.version = ISC_SAMA7G5_VERSION_OFFSET;\n+\tisc->offsets.his_entry = ISC_SAMA7G5_HIS_ENTRY_OFFSET;\n+\n+\tisc->controller_formats = sama7g5_controller_formats;\n+\tisc->controller_formats_size = ARRAY_SIZE(sama7g5_controller_formats);\n+\tisc->formats_list = sama7g5_formats_list;\n+\tisc->formats_list_size = ARRAY_SIZE(sama7g5_formats_list);\n+\n+\t/* sama7g5-isc RAM access port is full AXI4 - 32 bits per beat */\n+\tisc->dcfg = ISC_DCFG_YMBSIZE_BEATS32 | ISC_DCFG_CMBSIZE_BEATS32;\n+\n+\tret = isc_pipeline_init(isc);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tisc->hclock = devm_clk_get(dev, \"hclock\");\n+\tif (IS_ERR(isc->hclock)) {\n+\t\tret = PTR_ERR(isc->hclock);\n+\t\tdev_err(dev, \"failed to get hclock: %d\\n\", ret);\n+\t\treturn ret;\n+\t}\n+\n+\tret = clk_prepare_enable(isc->hclock);\n+\tif (ret) {\n+\t\tdev_err(dev, \"failed to enable hclock: %d\\n\", ret);\n+\t\treturn ret;\n+\t}\n+\n+\tret = isc_clk_init(isc);\n+\tif (ret) {\n+\t\tdev_err(dev, \"failed to init isc clock: %d\\n\", ret);\n+\t\tgoto unprepare_hclk;\n+\t}\n+\n+\tisc->ispck = isc->isc_clks[ISC_ISPCK].clk;\n+\n+\tret = clk_prepare_enable(isc->ispck);\n+\tif (ret) {\n+\t\tdev_err(dev, \"failed to enable ispck: %d\\n\", ret);\n+\t\tgoto unprepare_hclk;\n+\t}\n+\n+\t/* ispck should be greater or equal to hclock */\n+\tret = clk_set_rate(isc->ispck, clk_get_rate(isc->hclock));\n+\tif (ret) {\n+\t\tdev_err(dev, \"failed to set ispck rate: %d\\n\", ret);\n+\t\tgoto unprepare_clk;\n+\t}\n+\n+\tret = v4l2_device_register(dev, &isc->v4l2_dev);\n+\tif (ret) {\n+\t\tdev_err(dev, \"unable to register v4l2 device.\\n\");\n+\t\tgoto unprepare_clk;\n+\t}\n+\n+\tret = xisc_parse_dt(dev, isc);\n+\tif (ret) {\n+\t\tdev_err(dev, \"fail to parse device tree\\n\");\n+\t\tgoto unregister_v4l2_device;\n+\t}\n+\n+\tif (list_empty(&isc->subdev_entities)) {\n+\t\tdev_err(dev, \"no subdev found\\n\");\n+\t\tret = -ENODEV;\n+\t\tgoto unregister_v4l2_device;\n+\t}\n+\n+\tlist_for_each_entry(subdev_entity, &isc->subdev_entities, list) {\n+\t\tstruct v4l2_async_subdev *asd;\n+\n+\t\tv4l2_async_notifier_init(&subdev_entity->notifier);\n+\n+\t\tasd = v4l2_async_notifier_add_fwnode_remote_subdev(\n+\t\t\t\t\t&subdev_entity->notifier,\n+\t\t\t\t\tof_fwnode_handle(subdev_entity->epn),\n+\t\t\t\t\tstruct v4l2_async_subdev);\n+\n+\t\tof_node_put(subdev_entity->epn);\n+\t\tsubdev_entity->epn = NULL;\n+\n+\t\tif (IS_ERR(asd)) {\n+\t\t\tret = PTR_ERR(asd);\n+\t\t\tgoto cleanup_subdev;\n+\t\t}\n+\n+\t\tsubdev_entity->notifier.ops = &isc_async_ops;\n+\n+\t\tret = v4l2_async_notifier_register(&isc->v4l2_dev,\n+\t\t\t\t\t\t   &subdev_entity->notifier);\n+\t\tif (ret) {\n+\t\t\tdev_err(dev, \"fail to register async notifier\\n\");\n+\t\t\tgoto cleanup_subdev;\n+\t\t}\n+\n+\t\tif (video_is_registered(&isc->video_dev))\n+\t\t\tbreak;\n+\t}\n+\n+\tpm_runtime_set_active(dev);\n+\tpm_runtime_enable(dev);\n+\tpm_request_idle(dev);\n+\n+\tregmap_read(isc->regmap, ISC_VERSION + isc->offsets.version, &ver);\n+\tdev_info(dev, \"Microchip XISC version %x\\n\", ver);\n+\n+\treturn 0;\n+\n+cleanup_subdev:\n+\tisc_subdev_cleanup(isc);\n+\n+unregister_v4l2_device:\n+\tv4l2_device_unregister(&isc->v4l2_dev);\n+\n+unprepare_clk:\n+\tclk_disable_unprepare(isc->ispck);\n+unprepare_hclk:\n+\tclk_disable_unprepare(isc->hclock);\n+\n+\tisc_clk_cleanup(isc);\n+\n+\treturn ret;\n+}\n+\n+static int microchip_xisc_remove(struct platform_device *pdev)\n+{\n+\tstruct isc_device *isc = platform_get_drvdata(pdev);\n+\n+\tpm_runtime_disable(&pdev->dev);\n+\n+\tisc_subdev_cleanup(isc);\n+\n+\tv4l2_device_unregister(&isc->v4l2_dev);\n+\n+\tclk_disable_unprepare(isc->ispck);\n+\tclk_disable_unprepare(isc->hclock);\n+\n+\tisc_clk_cleanup(isc);\n+\n+\treturn 0;\n+}\n+\n+static int __maybe_unused xisc_runtime_suspend(struct device *dev)\n+{\n+\tstruct isc_device *isc = dev_get_drvdata(dev);\n+\n+\tclk_disable_unprepare(isc->ispck);\n+\tclk_disable_unprepare(isc->hclock);\n+\n+\treturn 0;\n+}\n+\n+static int __maybe_unused xisc_runtime_resume(struct device *dev)\n+{\n+\tstruct isc_device *isc = dev_get_drvdata(dev);\n+\tint ret;\n+\n+\tret = clk_prepare_enable(isc->hclock);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = clk_prepare_enable(isc->ispck);\n+\tif (ret)\n+\t\tclk_disable_unprepare(isc->hclock);\n+\n+\treturn ret;\n+}\n+\n+static const struct dev_pm_ops microchip_xisc_dev_pm_ops = {\n+\tSET_RUNTIME_PM_OPS(xisc_runtime_suspend, xisc_runtime_resume, NULL)\n+};\n+\n+static const struct of_device_id microchip_xisc_of_match[] = {\n+\t{ .compatible = \"microchip,sama7g5-isc\" },\n+\t{ }\n+};\n+MODULE_DEVICE_TABLE(of, microchip_xisc_of_match);\n+\n+static struct platform_driver microchip_xisc_driver = {\n+\t.probe\t= microchip_xisc_probe,\n+\t.remove\t= microchip_xisc_remove,\n+\t.driver\t= {\n+\t\t.name\t\t= \"microchip-sama7g5-xisc\",\n+\t\t.pm\t\t= &microchip_xisc_dev_pm_ops,\n+\t\t.of_match_table = of_match_ptr(microchip_xisc_of_match),\n+\t},\n+};\n+\n+module_platform_driver(microchip_xisc_driver);\n+\n+MODULE_AUTHOR(\"Eugen Hristev <eugen.hristev@microchip.com>\");\n+MODULE_DESCRIPTION(\"The V4L2 driver for Microchip-XISC\");\n+MODULE_LICENSE(\"GPL v2\");\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/186-ASoC-atmel-fix-shadowed-variable.patch",
    "content": "From 1b41c69264d7233a3e9a0aa36333ee22a5a049e9 Mon Sep 17 00:00:00 2001\nFrom: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>\nDate: Fri, 26 Mar 2021 16:59:12 -0500\nSubject: [PATCH 186/247] ASoC: atmel: fix shadowed variable\n\nFix cppcheck warning:\n\nsound/soc/atmel/atmel-classd.c:51:14: style: Local variable 'pwm_type'\nshadows outer variable [shadowVariable]\n const char *pwm_type;\n             ^\nsound/soc/atmel/atmel-classd.c:226:27: note: Shadowed declaration\nstatic const char * const pwm_type[] = {\n                          ^\nsound/soc/atmel/atmel-classd.c:51:14: note: Shadow variable\n const char *pwm_type;\n             ^\n\nSigned-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>\nReviewed-by: Codrin Ciubotariu <codrin.ciubotariu@microchip.com>\nLink: https://lore.kernel.org/r/20210326215927.936377-3-pierre-louis.bossart@linux.intel.com\nSigned-off-by: Mark Brown <broonie@kernel.org>\n---\n sound/soc/atmel/atmel-classd.c | 6 +++---\n 1 file changed, 3 insertions(+), 3 deletions(-)\n\n--- a/sound/soc/atmel/atmel-classd.c\n+++ b/sound/soc/atmel/atmel-classd.c\n@@ -48,7 +48,7 @@ static struct atmel_classd_pdata *atmel_\n {\n \tstruct device_node *np = dev->of_node;\n \tstruct atmel_classd_pdata *pdata;\n-\tconst char *pwm_type;\n+\tconst char *pwm_type_s;\n \tint ret;\n \n \tif (!np) {\n@@ -60,8 +60,8 @@ static struct atmel_classd_pdata *atmel_\n \tif (!pdata)\n \t\treturn ERR_PTR(-ENOMEM);\n \n-\tret = of_property_read_string(np, \"atmel,pwm-type\", &pwm_type);\n-\tif ((ret == 0) && (strcmp(pwm_type, \"diff\") == 0))\n+\tret = of_property_read_string(np, \"atmel,pwm-type\", &pwm_type_s);\n+\tif ((ret == 0) && (strcmp(pwm_type_s, \"diff\") == 0))\n \t\tpdata->pwm_type = CLASSD_MR_PWMTYP_DIFF;\n \telse\n \t\tpdata->pwm_type = CLASSD_MR_PWMTYP_SINGLE;\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/187-ASoC-atmel-atmel-i2s-remove-useless-initialization.patch",
    "content": "From e53725fe0c7e6b52927280272f49fe5f4b4ef317 Mon Sep 17 00:00:00 2001\nFrom: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>\nDate: Fri, 26 Mar 2021 16:59:13 -0500\nSubject: [PATCH 187/247] ASoC: atmel: atmel-i2s: remove useless initialization\n\nCppcheck complains:\n\nsound/soc/atmel/atmel-i2s.c:628:6: style: Redundant initialization for 'err'. The initialized value is overwritten before it is read. [redundantInitialization]\n err = devm_request_irq(&pdev->dev, irq, atmel_i2s_interrupt, 0,\n     ^\nsound/soc/atmel/atmel-i2s.c:598:10: note: err is initialized\n int err = -ENXIO;\n         ^\nsound/soc/atmel/atmel-i2s.c:628:6: note: err is overwritten\n err = devm_request_irq(&pdev->dev, irq, atmel_i2s_interrupt, 0,\n     ^\n\nSigned-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>\nReviewed-by: Codrin Ciubotariu <codrin.ciubotariu@microchip.com>\nLink: https://lore.kernel.org/r/20210326215927.936377-4-pierre-louis.bossart@linux.intel.com\nSigned-off-by: Mark Brown <broonie@kernel.org>\n---\n sound/soc/atmel/atmel-i2s.c | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/sound/soc/atmel/atmel-i2s.c\n+++ b/sound/soc/atmel/atmel-i2s.c\n@@ -613,7 +613,7 @@ static int atmel_i2s_probe(struct platfo\n \tstruct regmap *regmap;\n \tvoid __iomem *base;\n \tint irq;\n-\tint err = -ENXIO;\n+\tint err;\n \tunsigned int pcm_flags = 0;\n \tunsigned int version;\n \n"
  },
  {
    "path": "target/linux/at91/patches-5.10/188-ASoC-atmel-i2s-Set-symmetric-sample-bits.patch",
    "content": "From a6f337fdf68294cfae233724567cbeea0ae5148f Mon Sep 17 00:00:00 2001\nFrom: Codrin Ciubotariu <codrin.ciubotariu@microchip.com>\nDate: Fri, 18 Jun 2021 18:07:40 +0300\nSubject: [PATCH 188/247] ASoC: atmel-i2s: Set symmetric sample bits\n\nThe I2S needs to have the same sample bits for both capture and playback\nstreams.\n\nFixes: b543e467d1a9 (\"ASoC: atmel-i2s: add driver for the new Atmel I2S controller\")\nSigned-off-by: Codrin Ciubotariu <codrin.ciubotariu@microchip.com>\nLink: https://lore.kernel.org/r/20210618150741.401739-1-codrin.ciubotariu@microchip.com\nSigned-off-by: Mark Brown <broonie@kernel.org>\n---\n sound/soc/atmel/atmel-i2s.c | 1 +\n 1 file changed, 1 insertion(+)\n\n--- a/sound/soc/atmel/atmel-i2s.c\n+++ b/sound/soc/atmel/atmel-i2s.c\n@@ -560,6 +560,7 @@ static struct snd_soc_dai_driver atmel_i\n \t},\n \t.ops = &atmel_i2s_dai_ops,\n \t.symmetric_rates = 1,\n+\t.symmetric_samplebits = 1,\n };\n \n static const struct snd_soc_component_driver atmel_i2s_component = {\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/189-watchdog-sama5d4_wdt-add-support-for-sama7g5-wdt.patch",
    "content": "From ff83cc9f95aaba75991210312061b7fe52aaa400 Mon Sep 17 00:00:00 2001\nFrom: Eugen Hristev <eugen.hristev@microchip.com>\nDate: Thu, 27 May 2021 13:01:19 +0300\nSubject: [PATCH 189/247] watchdog: sama5d4_wdt: add support for sama7g5-wdt\n\nAdd support for compatible sama7g5-wdt.\nThe sama7g5 wdt is the same hardware block as on sam9x60.\nAdapt the driver to use the sam9x60/sama7g5 variant if either\nof the two compatibles are selected (sam9x60-wdt/sama7g5-wdt).\n\nSigned-off-by: Eugen Hristev <eugen.hristev@microchip.com>\nAcked-by: Nicolas Ferre <nicolas.ferre@microchip.com>\nReviewed-by: Guenter Roeck <linux@roeck-us.net>\nLink: https://lore.kernel.org/r/20210527100120.266796-2-eugen.hristev@microchip.com\nSigned-off-by: Guenter Roeck <linux@roeck-us.net>\nSigned-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>\n---\n drivers/watchdog/sama5d4_wdt.c | 10 ++++++++--\n 1 file changed, 8 insertions(+), 2 deletions(-)\n\n--- a/drivers/watchdog/sama5d4_wdt.c\n+++ b/drivers/watchdog/sama5d4_wdt.c\n@@ -268,8 +268,10 @@ static int sama5d4_wdt_probe(struct plat\n \twdd->min_timeout = MIN_WDT_TIMEOUT;\n \twdd->max_timeout = MAX_WDT_TIMEOUT;\n \twdt->last_ping = jiffies;\n-\twdt->sam9x60_support = of_device_is_compatible(dev->of_node,\n-\t\t\t\t\t\t       \"microchip,sam9x60-wdt\");\n+\n+\tif (of_device_is_compatible(dev->of_node, \"microchip,sam9x60-wdt\") ||\n+\t    of_device_is_compatible(dev->of_node, \"microchip,sama7g5-wdt\"))\n+\t\twdt->sam9x60_support = true;\n \n \twatchdog_set_drvdata(wdd, wdt);\n \n@@ -329,6 +331,10 @@ static const struct of_device_id sama5d4\n \t{\n \t\t.compatible = \"microchip,sam9x60-wdt\",\n \t},\n+\t{\n+\t\t.compatible = \"microchip,sama7g5-wdt\",\n+\t},\n+\n \t{ }\n };\n MODULE_DEVICE_TABLE(of, sama5d4_wdt_of_match);\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/190-media-atmel-fix-build-when-ISC-m-and-XISC-y.patch",
    "content": "From dfcc0395f5e838c0b5c3fb93c9335b6a8892178a Mon Sep 17 00:00:00 2001\nFrom: Eugen Hristev <eugen.hristev@microchip.com>\nDate: Mon, 5 Jul 2021 14:57:08 +0200\nSubject: [PATCH 190/247] media: atmel: fix build when ISC=m and XISC=y\n\nBuilding VIDEO_ATMEL_ISC as module and VIDEO_ATMEL_XISC as built-in\n(or viceversa) causes build errors:\n\n or1k-linux-ld: drivers/media/platform/atmel/atmel-isc-base.o: in function `isc_async_complete':\n atmel-isc-base.c:(.text+0x40d0): undefined reference to `__this_module'\n or1k-linux-ld: atmel-isc-base.c:(.text+0x40f0): undefined reference to `__this_module'\n or1k-linux-ld: drivers/media/platform/atmel/atmel-isc-base.o:(.rodata+0x390): undefined reference to `__this_module'\n or1k-linux-ld: drivers/media/platform/atmel/atmel-isc-base.o:(__param+0x4): undefined reference to `__this_module'\n or1k-linux-ld: drivers/media/platform/atmel/atmel-isc-base.o:(__param+0x18): undefined reference to `__this_module'\n\nThis is caused by the file atmel-isc-base.c which is common code between\nthe two drivers.\n\nThe solution is to create another Kconfig symbol that is automatically\nselected and generates the module atmel-isc-base.ko. This module can be\nloaded when both drivers are modules, or built-in when at least one of them\nis built-in.\n\nReported-by: kernel test robot <lkp@intel.com>\nFixes: c9aa973884a1 (\"media: atmel: atmel-isc: add microchip-xisc driver\")\nSigned-off-by: Eugen Hristev <eugen.hristev@microchip.com>\nSigned-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>\nSigned-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>\n---\n drivers/media/platform/atmel/Kconfig          |  8 ++++++++\n drivers/media/platform/atmel/Makefile         |  5 +++--\n drivers/media/platform/atmel/atmel-isc-base.c | 11 +++++++++++\n 3 files changed, 22 insertions(+), 2 deletions(-)\n\n--- a/drivers/media/platform/atmel/Kconfig\n+++ b/drivers/media/platform/atmel/Kconfig\n@@ -8,6 +8,7 @@ config VIDEO_ATMEL_ISC\n \tselect VIDEOBUF2_DMA_CONTIG\n \tselect REGMAP_MMIO\n \tselect V4L2_FWNODE\n+\tselect VIDEO_ATMEL_ISC_BASE\n \thelp\n \t   This module makes the ATMEL Image Sensor Controller available\n \t   as a v4l2 device.\n@@ -19,10 +20,17 @@ config VIDEO_ATMEL_XISC\n \tselect VIDEOBUF2_DMA_CONTIG\n \tselect REGMAP_MMIO\n \tselect V4L2_FWNODE\n+\tselect VIDEO_ATMEL_ISC_BASE\n \thelp\n \t   This module makes the ATMEL eXtended Image Sensor Controller\n \t   available as a v4l2 device.\n \n+config VIDEO_ATMEL_ISC_BASE\n+\ttristate\n+\tdefault n\n+\thelp\n+\t  ATMEL ISC and XISC common code base.\n+\n config VIDEO_ATMEL_ISI\n \ttristate \"ATMEL Image Sensor Interface (ISI) support\"\n \tdepends on VIDEO_V4L2 && OF\n--- a/drivers/media/platform/atmel/Makefile\n+++ b/drivers/media/platform/atmel/Makefile\n@@ -1,7 +1,8 @@\n # SPDX-License-Identifier: GPL-2.0-only\n-atmel-isc-objs = atmel-sama5d2-isc.o atmel-isc-base.o\n-atmel-xisc-objs = atmel-sama7g5-isc.o atmel-isc-base.o\n+atmel-isc-objs = atmel-sama5d2-isc.o\n+atmel-xisc-objs = atmel-sama7g5-isc.o\n \n obj-$(CONFIG_VIDEO_ATMEL_ISI) += atmel-isi.o\n+obj-$(CONFIG_VIDEO_ATMEL_ISC_BASE) += atmel-isc-base.o\n obj-$(CONFIG_VIDEO_ATMEL_ISC) += atmel-isc.o\n obj-$(CONFIG_VIDEO_ATMEL_XISC) += atmel-xisc.o\n--- a/drivers/media/platform/atmel/atmel-isc-base.c\n+++ b/drivers/media/platform/atmel/atmel-isc-base.c\n@@ -378,6 +378,7 @@ int isc_clk_init(struct isc_device *isc)\n \n \treturn 0;\n }\n+EXPORT_SYMBOL_GPL(isc_clk_init);\n \n void isc_clk_cleanup(struct isc_device *isc)\n {\n@@ -392,6 +393,7 @@ void isc_clk_cleanup(struct isc_device *\n \t\t\tclk_unregister(isc_clk->clk);\n \t}\n }\n+EXPORT_SYMBOL_GPL(isc_clk_cleanup);\n \n static int isc_queue_setup(struct vb2_queue *vq,\n \t\t\t    unsigned int *nbuffers, unsigned int *nplanes,\n@@ -1575,6 +1577,7 @@ irqreturn_t isc_interrupt(int irq, void\n \n \treturn ret;\n }\n+EXPORT_SYMBOL_GPL(isc_interrupt);\n \n static void isc_hist_count(struct isc_device *isc, u32 *min, u32 *max)\n {\n@@ -2209,6 +2212,7 @@ const struct v4l2_async_notifier_operati\n \t.unbind = isc_async_unbind,\n \t.complete = isc_async_complete,\n };\n+EXPORT_SYMBOL_GPL(isc_async_ops);\n \n void isc_subdev_cleanup(struct isc_device *isc)\n {\n@@ -2221,6 +2225,7 @@ void isc_subdev_cleanup(struct isc_devic\n \n \tINIT_LIST_HEAD(&isc->subdev_entities);\n }\n+EXPORT_SYMBOL_GPL(isc_subdev_cleanup);\n \n int isc_pipeline_init(struct isc_device *isc)\n {\n@@ -2261,6 +2266,7 @@ int isc_pipeline_init(struct isc_device\n \n \treturn 0;\n }\n+EXPORT_SYMBOL_GPL(isc_pipeline_init);\n \n /* regmap configuration */\n #define ATMEL_ISC_REG_MAX    0xd5c\n@@ -2270,4 +2276,9 @@ const struct regmap_config isc_regmap_co\n \t.val_bits       = 32,\n \t.max_register\t= ATMEL_ISC_REG_MAX,\n };\n+EXPORT_SYMBOL_GPL(isc_regmap_config);\n \n+MODULE_AUTHOR(\"Songjun Wu\");\n+MODULE_AUTHOR(\"Eugen Hristev\");\n+MODULE_DESCRIPTION(\"Atmel ISC common code base\");\n+MODULE_LICENSE(\"GPL v2\");\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/191-i2c-at91-remove-define-CONFIG_PM.patch",
    "content": "From 023a6b46536dce41f2c5a7425826fc4da4509b8f Mon Sep 17 00:00:00 2001\nFrom: Claudiu Beznea <claudiu.beznea@microchip.com>\nDate: Mon, 5 Jul 2021 15:15:16 +0300\nSubject: [PATCH 191/247] i2c: at91: remove #define CONFIG_PM\n\nRemove #define CONFIG_PM and use __maybe_unused for PM functions and\npm_ptr() for PM ops.\n\nSigned-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>\nReviewed-by: Codrin Ciubotariu <codrin.ciubotariu@microchip.com>\nSigned-off-by: Wolfram Sang <wsa@kernel.org>\n---\n drivers/i2c/busses/i2c-at91-core.c | 17 +++++------------\n 1 file changed, 5 insertions(+), 12 deletions(-)\n\n--- a/drivers/i2c/busses/i2c-at91-core.c\n+++ b/drivers/i2c/busses/i2c-at91-core.c\n@@ -286,9 +286,7 @@ static int at91_twi_remove(struct platfo\n \treturn 0;\n }\n \n-#ifdef CONFIG_PM\n-\n-static int at91_twi_runtime_suspend(struct device *dev)\n+static int __maybe_unused at91_twi_runtime_suspend(struct device *dev)\n {\n \tstruct at91_twi_dev *twi_dev = dev_get_drvdata(dev);\n \n@@ -299,7 +297,7 @@ static int at91_twi_runtime_suspend(stru\n \treturn 0;\n }\n \n-static int at91_twi_runtime_resume(struct device *dev)\n+static int __maybe_unused at91_twi_runtime_resume(struct device *dev)\n {\n \tstruct at91_twi_dev *twi_dev = dev_get_drvdata(dev);\n \n@@ -308,7 +306,7 @@ static int at91_twi_runtime_resume(struc\n \treturn clk_prepare_enable(twi_dev->clk);\n }\n \n-static int at91_twi_suspend_noirq(struct device *dev)\n+static int __maybe_unused at91_twi_suspend_noirq(struct device *dev)\n {\n \tif (!pm_runtime_status_suspended(dev))\n \t\tat91_twi_runtime_suspend(dev);\n@@ -316,7 +314,7 @@ static int at91_twi_suspend_noirq(struct\n \treturn 0;\n }\n \n-static int at91_twi_resume_noirq(struct device *dev)\n+static int __maybe_unused at91_twi_resume_noirq(struct device *dev)\n {\n \tstruct at91_twi_dev *twi_dev = dev_get_drvdata(dev);\n \tint ret;\n@@ -342,11 +340,6 @@ static const struct dev_pm_ops at91_twi_\n \t.runtime_resume\t\t= at91_twi_runtime_resume,\n };\n \n-#define at91_twi_pm_ops (&at91_twi_pm)\n-#else\n-#define at91_twi_pm_ops NULL\n-#endif\n-\n static struct platform_driver at91_twi_driver = {\n \t.probe\t\t= at91_twi_probe,\n \t.remove\t\t= at91_twi_remove,\n@@ -354,7 +347,7 @@ static struct platform_driver at91_twi_d\n \t.driver\t\t= {\n \t\t.name\t= \"at91_i2c\",\n \t\t.of_match_table = of_match_ptr(atmel_twi_dt_ids),\n-\t\t.pm\t= at91_twi_pm_ops,\n+\t\t.pm\t= pm_ptr(&at91_twi_pm),\n \t},\n };\n \n"
  },
  {
    "path": "target/linux/at91/patches-5.10/192-ASoC-codecs-ad193x-add-support-for-96kHz-and-192kHz-.patch",
    "content": "From 1c906a59a60887e1b997ebab63f19f33a1c69a3e Mon Sep 17 00:00:00 2001\nFrom: Codrin Ciubotariu <codrin.ciubotariu@microchip.com>\nDate: Tue, 3 Aug 2021 13:48:25 +0300\nSubject: [PATCH 192/247] ASoC: codecs: ad193x: add support for 96kHz and\n 192kHz playback rates\n\nad193x devices support 96KHz and 192KHz sampling rates, when PLL/MCLK is\nreferenced to 48kHz.\nTested on ad1934.\n\nSigned-off-by: Codrin Ciubotariu <codrin.ciubotariu@microchip.com>\nLink: https://lore.kernel.org/r/20210803104825.2198335-1-codrin.ciubotariu@microchip.com\nSigned-off-by: Mark Brown <broonie@kernel.org>\n---\n sound/soc/codecs/ad193x.c | 30 ++++++++++++++++++++++++++++--\n sound/soc/codecs/ad193x.h |  4 ++++\n 2 files changed, 32 insertions(+), 2 deletions(-)\n\n--- a/sound/soc/codecs/ad193x.c\n+++ b/sound/soc/codecs/ad193x.c\n@@ -316,6 +316,13 @@ static int ad193x_hw_params(struct snd_p\n \tint word_len = 0, master_rate = 0;\n \tstruct snd_soc_component *component = dai->component;\n \tstruct ad193x_priv *ad193x = snd_soc_component_get_drvdata(component);\n+\tbool is_playback = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;\n+\tu8 dacc0;\n+\n+\tdev_dbg(dai->dev, \"%s() rate=%u format=%#x width=%u channels=%u\\n\",\n+\t\t__func__, params_rate(params), params_format(params),\n+\t\tparams_width(params), params_channels(params));\n+\n \n \t/* bit size */\n \tswitch (params_width(params)) {\n@@ -346,6 +353,25 @@ static int ad193x_hw_params(struct snd_p\n \t\tbreak;\n \t}\n \n+\tif (is_playback) {\n+\t\tswitch (params_rate(params)) {\n+\t\tcase 48000:\n+\t\t\tdacc0 = AD193X_DAC_SR_48;\n+\t\t\tbreak;\n+\t\tcase 96000:\n+\t\t\tdacc0 = AD193X_DAC_SR_96;\n+\t\t\tbreak;\n+\t\tcase 192000:\n+\t\t\tdacc0 = AD193X_DAC_SR_192;\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tdev_err(dai->dev, \"invalid sampling rate: %d\\n\", params_rate(params));\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\n+\t\tregmap_update_bits(ad193x->regmap, AD193X_DAC_CTRL0, AD193X_DAC_SR_MASK, dacc0);\n+\t}\n+\n \tregmap_update_bits(ad193x->regmap, AD193X_PLL_CLK_CTRL0,\n \t\t\t    AD193X_PLL_INPUT_MASK, master_rate);\n \n@@ -385,7 +411,7 @@ static struct snd_soc_dai_driver ad193x_\n \t\t.stream_name = \"Playback\",\n \t\t.channels_min = 2,\n \t\t.channels_max = 8,\n-\t\t.rates = SNDRV_PCM_RATE_48000,\n+\t\t.rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000,\n \t\t.formats = SNDRV_PCM_FMTBIT_S32_LE | SNDRV_PCM_FMTBIT_S16_LE |\n \t\t\tSNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE,\n \t},\n@@ -407,7 +433,7 @@ static struct snd_soc_dai_driver ad193x_\n \t\t.stream_name = \"Playback\",\n \t\t.channels_min = 2,\n \t\t.channels_max = 8,\n-\t\t.rates = SNDRV_PCM_RATE_48000,\n+\t\t.rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000,\n \t\t.formats = SNDRV_PCM_FMTBIT_S32_LE | SNDRV_PCM_FMTBIT_S16_LE |\n \t\t\tSNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE,\n \t},\n--- a/sound/soc/codecs/ad193x.h\n+++ b/sound/soc/codecs/ad193x.h\n@@ -37,6 +37,10 @@ int ad193x_probe(struct device *dev, str\n #define AD193X_PLL_CLK_SRC_MCLK\t(1 << 1)\n #define AD193X_DAC_CTRL0        0x02\n #define AD193X_DAC_POWERDOWN           0x01\n+#define AD193X_DAC_SR_MASK           0x06\n+#define AD193X_DAC_SR_48\t(0 << 1)\n+#define AD193X_DAC_SR_96\t(1 << 1)\n+#define AD193X_DAC_SR_192\t(2 << 1)\n #define AD193X_DAC_SERFMT_MASK\t\t0xC0\n #define AD193X_DAC_SERFMT_STEREO\t(0 << 6)\n #define AD193X_DAC_SERFMT_TDM\t\t(1 << 6)\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/193-media-atmel-atmel-sama5d2-isc-fix-YUYV-format.patch",
    "content": "From 21261e30679118b96ed537d1cdf9e12682fc1b29 Mon Sep 17 00:00:00 2001\nFrom: Eugen Hristev <eugen.hristev@microchip.com>\nDate: Wed, 9 Jun 2021 15:00:28 +0200\nSubject: [PATCH 193/247] media: atmel: atmel-sama5d2-isc: fix YUYV format\n\nSAMA5D2 does not have the YCYC field for the RLP (rounding, limiting,\npackaging) module.\nThe YCYC field is supposed to work with interleaved YUV formats like YUYV.\nIn SAMA5D2, we have to use YYCC field, which is used for both planar\nformats like YUV420 and interleaved formats like YUYV.\nFix the according rlp callback to replace the generic YCYC field (which\nmakes more sense from a logical point of view) with the required YYCC\nfield.\n\nFixes: debfa496871c (\"media: atmel: atmel-isc-base: add support for more formats and additional pipeline modules\")\nSigned-off-by: Eugen Hristev <eugen.hristev@microchip.com>\nSigned-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>\nSigned-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>\n---\n .../media/platform/atmel/atmel-sama5d2-isc.c    | 17 +++++++++++++++++\n 1 file changed, 17 insertions(+)\n\n--- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c\n+++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c\n@@ -255,6 +255,23 @@ static void isc_sama5d2_config_rlp(struc\n \tstruct regmap *regmap = isc->regmap;\n \tu32 rlp_mode = isc->config.rlp_cfg_mode;\n \n+\t/*\n+\t * In sama5d2, the YUV planar modes and the YUYV modes are treated\n+\t * in the same way in RLP register.\n+\t * Normally, YYCC mode should be Luma(n) - Color B(n) - Color R (n)\n+\t * and YCYC should be Luma(n + 1) - Color B (n) - Luma (n) - Color R (n)\n+\t * but in sama5d2, the YCYC mode does not exist, and YYCC must be\n+\t * selected for both planar and interleaved modes, as in fact\n+\t * both modes are supported.\n+\t *\n+\t * Thus, if the YCYC mode is selected, replace it with the\n+\t * sama5d2-compliant mode which is YYCC .\n+\t */\n+\tif ((rlp_mode & ISC_RLP_CFG_MODE_YCYC) == ISC_RLP_CFG_MODE_YCYC) {\n+\t\trlp_mode &= ~ISC_RLP_CFG_MODE_MASK;\n+\t\trlp_mode |= ISC_RLP_CFG_MODE_YYCC;\n+\t}\n+\n \tregmap_update_bits(regmap, ISC_RLP_CFG + isc->offsets.rlp,\n \t\t\t   ISC_RLP_CFG_MODE_MASK, rlp_mode);\n }\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/194-clk-at91-add-register-definition-for-sama7g5-s-maste.patch",
    "content": "From 602f85ff15d45bd313f8f6600d72202a50fd83a9 Mon Sep 17 00:00:00 2001\nFrom: Claudiu Beznea <claudiu.beznea@microchip.com>\nDate: Mon, 19 Jul 2021 11:03:17 +0300\nSubject: [PATCH 194/247] clk: at91: add register definition for sama7g5's\n master clock\n\nAdd register definitions for SAMA7G5's master clock. These would be\nalso used by architecture specific power saving code.\n\nSigned-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>\nSigned-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>\nLink: https://lore.kernel.org/r/20210719080317.1045832-3-claudiu.beznea@microchip.com\n---\n include/linux/clk/at91_pmc.h | 26 ++++++++++++++++++++++++++\n 1 file changed, 26 insertions(+)\n\n--- a/include/linux/clk/at91_pmc.h\n+++ b/include/linux/clk/at91_pmc.h\n@@ -137,6 +137,32 @@\n #define\t\t\tAT91_PMC_PLLADIV2_ON\t\t(1 << 12)\n #define\t\tAT91_PMC_H32MXDIV\tBIT(24)\n \n+#define\tAT91_PMC_MCR_V2\t\t0x30\t\t\t\t/* Master Clock Register [SAMA7G5 only] */\n+#define\t\tAT91_PMC_MCR_V2_ID_MSK\t(0xF)\n+#define\t\t\tAT91_PMC_MCR_V2_ID(_id)\t\t((_id) & AT91_PMC_MCR_V2_ID_MSK)\n+#define\t\tAT91_PMC_MCR_V2_CMD\t(1 << 7)\n+#define\t\tAT91_PMC_MCR_V2_DIV\t(7 << 8)\n+#define\t\t\tAT91_PMC_MCR_V2_DIV1\t\t(0 << 8)\n+#define\t\t\tAT91_PMC_MCR_V2_DIV2\t\t(1 << 8)\n+#define\t\t\tAT91_PMC_MCR_V2_DIV4\t\t(2 << 8)\n+#define\t\t\tAT91_PMC_MCR_V2_DIV8\t\t(3 << 8)\n+#define\t\t\tAT91_PMC_MCR_V2_DIV16\t\t(4 << 8)\n+#define\t\t\tAT91_PMC_MCR_V2_DIV32\t\t(5 << 8)\n+#define\t\t\tAT91_PMC_MCR_V2_DIV64\t\t(6 << 8)\n+#define\t\t\tAT91_PMC_MCR_V2_DIV3\t\t(7 << 8)\n+#define\t\tAT91_PMC_MCR_V2_CSS\t(0x1F << 16)\n+#define\t\t\tAT91_PMC_MCR_V2_CSS_MD_SLCK\t(0 << 16)\n+#define\t\t\tAT91_PMC_MCR_V2_CSS_TD_SLCK\t(1 << 16)\n+#define\t\t\tAT91_PMC_MCR_V2_CSS_MAINCK\t(2 << 16)\n+#define\t\t\tAT91_PMC_MCR_V2_CSS_MCK0\t(3 << 16)\n+#define\t\t\tAT91_PMC_MCR_V2_CSS_SYSPLL\t(5 << 16)\n+#define\t\t\tAT91_PMC_MCR_V2_CSS_DDRPLL\t(6 << 16)\n+#define\t\t\tAT91_PMC_MCR_V2_CSS_IMGPLL\t(7 << 16)\n+#define\t\t\tAT91_PMC_MCR_V2_CSS_BAUDPLL\t(8 << 16)\n+#define\t\t\tAT91_PMC_MCR_V2_CSS_AUDIOPLL\t(9 << 16)\n+#define\t\t\tAT91_PMC_MCR_V2_CSS_ETHPLL\t(10 << 16)\n+#define\t\tAT91_PMC_MCR_V2_EN\t(1 << 28)\n+\n #define AT91_PMC_XTALF\t\t0x34\t\t\t/* Main XTAL Frequency Register [SAMA7G5 only] */\n \n #define\tAT91_PMC_USB\t\t0x38\t\t\t/* USB Clock Register [some SAM9 only] */\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/195-ARM-at91-add-new-SoC-sama7g5.patch",
    "content": "From 32bac6971d0572f67758f9a8c8af7bf4592f1675 Mon Sep 17 00:00:00 2001\nFrom: Eugen Hristev <eugen.hristev@microchip.com>\nDate: Fri, 9 Apr 2021 14:31:15 +0300\nSubject: [PATCH 195/247] ARM: at91: add new SoC sama7g5\n\nAdd new SoC from at91 family : sama7g5\n\nSigned-off-by: Eugen Hristev <eugen.hristev@microchip.com>\n[claudiu.beznea@microchip.com: Select PLL, generic clock and UTMI support, add PM configs]\nSigned-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>\nSigned-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>\nLink: https://lore.kernel.org/r/20210409113116.482199-1-eugen.hristev@microchip.com\nLink: https://lore.kernel.org/r/20210719080317.1045832-2-claudiu.beznea@microchip.com\n---\n arch/arm/mach-at91/Kconfig | 18 ++++++++++++++++++\n 1 file changed, 18 insertions(+)\n\n--- a/arch/arm/mach-at91/Kconfig\n+++ b/arch/arm/mach-at91/Kconfig\n@@ -57,6 +57,16 @@ config SOC_SAMA5D4\n \thelp\n \t  Select this if you are using one of Microchip's SAMA5D4 family SoC.\n \n+config SOC_SAMA7G5\n+\tbool \"SAMA7G5 family\"\n+\tdepends on ARCH_MULTI_V7\n+\tselect HAVE_AT91_GENERATED_CLK\n+\tselect HAVE_AT91_SAM9X60_PLL\n+\tselect HAVE_AT91_UTMI\n+\tselect SOC_SAMA7\n+\thelp\n+\t  Select this if you are using one of Microchip's SAMA7G5 family SoC.\n+\n config SOC_AT91RM9200\n \tbool \"AT91RM9200\"\n \tdepends on ARCH_MULTI_V4T\n@@ -191,4 +201,12 @@ config SOC_SAMA5\n config ATMEL_PM\n \tbool\n \n+config SOC_SAMA7\n+\tbool\n+\tselect ARM_GIC\n+\tselect ATMEL_PM if PM\n+\tselect ATMEL_SDRAMC\n+\tselect MEMORY\n+\tselect SOC_SAM_V7\n+\tselect SRAM if PM\n endif\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/196-ARM-at91-debug-add-sama7g5-low-level-debug-uart.patch",
    "content": "From 3de4879bf59b46a966ea226a67df70b88f43a23e Mon Sep 17 00:00:00 2001\nFrom: Eugen Hristev <eugen.hristev@microchip.com>\nDate: Fri, 9 Apr 2021 14:31:16 +0300\nSubject: [PATCH 196/247] ARM: at91: debug: add sama7g5 low level debug uart\n\nAdd sama7g5 SoC debug uart on Flexcom3. This is the UART that the\nROM bootloader uses.\n\nSigned-off-by: Eugen Hristev <eugen.hristev@microchip.com>\nSigned-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>\nLink: https://lore.kernel.org/r/20210409113116.482199-2-eugen.hristev@microchip.com\n[claudiu.beznea: adapt to v5.10.27]\nSigned-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>\n---\n arch/arm/Kconfig.debug | 10 ++++++++++\n 1 file changed, 10 insertions(+)\n\n--- a/arch/arm/Kconfig.debug\n+++ b/arch/arm/Kconfig.debug\n@@ -191,6 +191,14 @@ choice\n \t\t  their output to the USART1 port on SAMV7 based\n \t\t  machines.\n \n+\tconfig DEBUG_AT91_SAMA7G5_FLEXCOM3\n+\t\tbool \"Kernel low-level debugging on SAMA7G5 FLEXCOM3\"\n+\t\tselect DEBUG_AT91_UART\n+\t\tdepends on SOC_SAMA7G5\n+\t\thelp\n+\t\t  Say Y here if you want kernel low-level debugging support\n+\t\t  on the FLEXCOM3 port of SAMA7G5.\n+\n \tconfig DEBUG_BCM2835\n \t\tbool \"Kernel low-level debugging on BCM2835 PL011 UART\"\n \t\tdepends on ARCH_BCM2835 && ARCH_MULTI_V6\n@@ -1731,6 +1739,7 @@ config DEBUG_UART_PHYS\n \tdefault 0xd4017000 if DEBUG_MMP_UART2\n \tdefault 0xd4018000 if DEBUG_MMP_UART3\n \tdefault 0xe0000000 if DEBUG_SPEAR13XX\n+\tdefault 0xe1824200 if DEBUG_AT91_SAMA7G5_FLEXCOM3\n \tdefault 0xe4007000 if DEBUG_HIP04_UART\n \tdefault 0xe6c40000 if DEBUG_RMOBILE_SCIFA0\n \tdefault 0xe6c50000 if DEBUG_RMOBILE_SCIFA1\n@@ -1791,6 +1800,7 @@ config DEBUG_UART_VIRT\n \tdefault 0xc8912000 if DEBUG_RV1108_UART0\n \tdefault 0xe0010fe0 if ARCH_RPC\n \tdefault 0xf0000be0 if ARCH_EBSA110\n+\tdefault 0xe0824200 if DEBUG_AT91_SAMA7G5_FLEXCOM3\n \tdefault 0xf0010000 if DEBUG_ASM9260_UART\n \tdefault 0xf0100000 if DEBUG_DIGICOLOR_UA0\n \tdefault 0xf01fb000 if DEBUG_NOMADIK_UART\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/197-ARM-at91-pm-move-pm_bu-to-soc_pm-data-structure.patch",
    "content": "From e41d00bdaa31b36fd314e927104082615aa4643a Mon Sep 17 00:00:00 2001\nFrom: Claudiu Beznea <claudiu.beznea@microchip.com>\nDate: Thu, 15 Apr 2021 13:49:47 +0300\nSubject: [PATCH 197/247] ARM: at91: pm: move pm_bu to soc_pm data structure\n\nMove pm_bu to soc_pm data structure.\n\nSigned-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>\nSigned-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>\nLink: https://lore.kernel.org/r/20210415105010.569620-2-claudiu.beznea@microchip.com\n---\n arch/arm/mach-at91/pm.c | 34 +++++++++++++++++++++-------------\n 1 file changed, 21 insertions(+), 13 deletions(-)\n\n--- a/arch/arm/mach-at91/pm.c\n+++ b/arch/arm/mach-at91/pm.c\n@@ -27,10 +27,25 @@\n #include \"generic.h\"\n #include \"pm.h\"\n \n+/**\n+ * struct at91_pm_bu - AT91 power management backup unit data structure\n+ * @suspended: true if suspended to backup mode\n+ * @reserved: reserved\n+ * @canary: canary data for memory checking after exit from backup mode\n+ * @resume: resume API\n+ */\n+struct at91_pm_bu {\n+\tint suspended;\n+\tunsigned long reserved;\n+\tphys_addr_t canary;\n+\tphys_addr_t resume;\n+};\n+\n struct at91_soc_pm {\n \tint (*config_shdwc_ws)(void __iomem *shdwc, u32 *mode, u32 *polarity);\n \tint (*config_pmc_ws)(void __iomem *pmc, u32 mode, u32 polarity);\n \tconst struct of_device_id *ws_ids;\n+\tstruct at91_pm_bu *bu;\n \tstruct at91_pm_data data;\n };\n \n@@ -71,13 +86,6 @@ static int at91_pm_valid_state(suspend_s\n \n static int canary = 0xA5A5A5A5;\n \n-static struct at91_pm_bu {\n-\tint suspended;\n-\tunsigned long reserved;\n-\tphys_addr_t canary;\n-\tphys_addr_t resume;\n-} *pm_bu;\n-\n struct wakeup_source_info {\n \tunsigned int pmc_fsmr_bit;\n \tunsigned int shdwc_mr_bit;\n@@ -288,7 +296,7 @@ static int at91_suspend_finish(unsigned\n static void at91_pm_suspend(suspend_state_t state)\n {\n \tif (soc_pm.data.mode == AT91_PM_BACKUP) {\n-\t\tpm_bu->suspended = 1;\n+\t\tsoc_pm.bu->suspended = 1;\n \n \t\tcpu_suspend(0, at91_suspend_finish);\n \n@@ -672,16 +680,16 @@ static int __init at91_pm_backup_init(vo\n \t\tgoto securam_fail;\n \t}\n \n-\tpm_bu = (void *)gen_pool_alloc(sram_pool, sizeof(struct at91_pm_bu));\n-\tif (!pm_bu) {\n+\tsoc_pm.bu = (void *)gen_pool_alloc(sram_pool, sizeof(struct at91_pm_bu));\n+\tif (!soc_pm.bu) {\n \t\tpr_warn(\"%s: unable to alloc securam!\\n\", __func__);\n \t\tret = -ENOMEM;\n \t\tgoto securam_fail;\n \t}\n \n-\tpm_bu->suspended = 0;\n-\tpm_bu->canary = __pa_symbol(&canary);\n-\tpm_bu->resume = __pa_symbol(cpu_resume);\n+\tsoc_pm.bu->suspended = 0;\n+\tsoc_pm.bu->canary = __pa_symbol(&canary);\n+\tsoc_pm.bu->resume = __pa_symbol(cpu_resume);\n \n \treturn 0;\n \n"
  },
  {
    "path": "target/linux/at91/patches-5.10/198-ARM-at91-pm-move-the-setup-of-soc_pm.bu-suspended.patch",
    "content": "From c8f2a8aaae41fa0a40ad88855ae82696098230d7 Mon Sep 17 00:00:00 2001\nFrom: Claudiu Beznea <claudiu.beznea@microchip.com>\nDate: Thu, 15 Apr 2021 13:49:48 +0300\nSubject: [PATCH 198/247] ARM: at91: pm: move the setup of soc_pm.bu->suspended\n\nMove the setup of soc_pm.bu->suspended in platform_suspend::begin\nfunction so that the PMC code in charge with clocks suspend/resume\nto differentiate b/w standard PM mode and backup mode.\n\nSigned-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>\nReviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com>\nSigned-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>\nLink: https://lore.kernel.org/r/20210415105010.569620-3-claudiu.beznea@microchip.com\n---\n arch/arm/mach-at91/pm.c | 15 ++++++++++++---\n 1 file changed, 12 insertions(+), 3 deletions(-)\n\n--- a/arch/arm/mach-at91/pm.c\n+++ b/arch/arm/mach-at91/pm.c\n@@ -214,6 +214,8 @@ static int at91_sam9x60_config_pmc_ws(vo\n  */\n static int at91_pm_begin(suspend_state_t state)\n {\n+\tint ret;\n+\n \tswitch (state) {\n \tcase PM_SUSPEND_MEM:\n \t\tsoc_pm.data.mode = soc_pm.data.suspend_mode;\n@@ -227,7 +229,16 @@ static int at91_pm_begin(suspend_state_t\n \t\tsoc_pm.data.mode = -1;\n \t}\n \n-\treturn at91_pm_config_ws(soc_pm.data.mode, true);\n+\tret = at91_pm_config_ws(soc_pm.data.mode, true);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tif (soc_pm.data.mode == AT91_PM_BACKUP)\n+\t\tsoc_pm.bu->suspended = 1;\n+\telse if (soc_pm.bu)\n+\t\tsoc_pm.bu->suspended = 0;\n+\n+\treturn 0;\n }\n \n /*\n@@ -296,8 +307,6 @@ static int at91_suspend_finish(unsigned\n static void at91_pm_suspend(suspend_state_t state)\n {\n \tif (soc_pm.data.mode == AT91_PM_BACKUP) {\n-\t\tsoc_pm.bu->suspended = 1;\n-\n \t\tcpu_suspend(0, at91_suspend_finish);\n \n \t\t/* The SRAM is lost between suspend cycles */\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/199-ARM-at91-pm-document-at91_soc_pm-structure.patch",
    "content": "From 59a4b3b9381b727f416d9cc52e60d0bc7d93ecae Mon Sep 17 00:00:00 2001\nFrom: Claudiu Beznea <claudiu.beznea@microchip.com>\nDate: Thu, 15 Apr 2021 13:49:49 +0300\nSubject: [PATCH 199/247] ARM: at91: pm: document at91_soc_pm structure\n\nDocument at91_soc_pm structure.\n\nSigned-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>\nSigned-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>\nLink: https://lore.kernel.org/r/20210415105010.569620-4-claudiu.beznea@microchip.com\n---\n arch/arm/mach-at91/pm.c | 8 ++++++++\n 1 file changed, 8 insertions(+)\n\n--- a/arch/arm/mach-at91/pm.c\n+++ b/arch/arm/mach-at91/pm.c\n@@ -41,6 +41,14 @@ struct at91_pm_bu {\n \tphys_addr_t resume;\n };\n \n+/**\n+ * struct at91_soc_pm - AT91 SoC power management data structure\n+ * @config_shdwc_ws: wakeup sources configuration function for SHDWC\n+ * @config_pmc_ws: wakeup srouces configuration function for PMC\n+ * @ws_ids: wakup sources of_device_id array\n+ * @data: PM data to be used on last phase of suspend\n+ * @bu: backup unit mapped data (for backup mode)\n+ */\n struct at91_soc_pm {\n \tint (*config_shdwc_ws)(void __iomem *shdwc, u32 *mode, u32 *polarity);\n \tint (*config_pmc_ws)(void __iomem *pmc, u32 mode, u32 polarity);\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/200-ARM-at91-pm-check-for-different-controllers-in-at91_.patch",
    "content": "From 0c4cbd38a705bdeab11de4c84ad0ce8c3de8a81d Mon Sep 17 00:00:00 2001\nFrom: Claudiu Beznea <claudiu.beznea@microchip.com>\nDate: Thu, 15 Apr 2021 13:49:50 +0300\nSubject: [PATCH 200/247] ARM: at91: pm: check for different controllers in\n at91_pm_modes_init()\n\nat91_pm_modes_init() checks for proper nodes in device tree and maps\nthem accordingly. Up to SAMA7G5 all AT91 SoCs had the same mapping\nb/w power saving modes and different controllers needed in the\nfinal/first steps of suspend/resume. SAMA7G5 is not aligned with the\nold SoCs thus the code is adapted for this. This patch prepares\nthe field for next commits.\n\nSigned-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>\nSigned-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>\nLink: https://lore.kernel.org/r/20210415105010.569620-5-claudiu.beznea@microchip.com\n---\n arch/arm/mach-at91/pm.c | 143 +++++++++++++++++++++++++---------------\n 1 file changed, 91 insertions(+), 52 deletions(-)\n\n--- a/arch/arm/mach-at91/pm.c\n+++ b/arch/arm/mach-at91/pm.c\n@@ -57,6 +57,18 @@ struct at91_soc_pm {\n \tstruct at91_pm_data data;\n };\n \n+/**\n+ * enum at91_pm_iomaps:\tIOs that needs to be mapped for different PM modes\n+ * @AT91_PM_IOMAP_SHDWC:\tSHDWC controller\n+ * @AT91_PM_IOMAP_SFRBU:\tSFRBU controller\n+ */\n+enum at91_pm_iomaps {\n+\tAT91_PM_IOMAP_SHDWC,\n+\tAT91_PM_IOMAP_SFRBU,\n+};\n+\n+#define AT91_PM_IOMAP(name)\tBIT(AT91_PM_IOMAP_##name)\n+\n static struct at91_soc_pm soc_pm = {\n \t.data = {\n \t\t.standby_mode = AT91_PM_STANDBY,\n@@ -671,24 +683,15 @@ static int __init at91_pm_backup_init(vo\n \tif (!at91_is_pm_mode_active(AT91_PM_BACKUP))\n \t\treturn 0;\n \n-\tnp = of_find_compatible_node(NULL, NULL, \"atmel,sama5d2-sfrbu\");\n-\tif (!np) {\n-\t\tpr_warn(\"%s: failed to find sfrbu!\\n\", __func__);\n-\t\treturn ret;\n-\t}\n-\n-\tsoc_pm.data.sfrbu = of_iomap(np, 0);\n-\tof_node_put(np);\n-\n \tnp = of_find_compatible_node(NULL, NULL, \"atmel,sama5d2-securam\");\n \tif (!np)\n-\t\tgoto securam_fail_no_ref_dev;\n+\t\treturn ret;\n \n \tpdev = of_find_device_by_node(np);\n \tof_node_put(np);\n \tif (!pdev) {\n \t\tpr_warn(\"%s: failed to find securam device!\\n\", __func__);\n-\t\tgoto securam_fail_no_ref_dev;\n+\t\treturn ret;\n \t}\n \n \tsram_pool = gen_pool_get(&pdev->dev, NULL);\n@@ -712,64 +715,92 @@ static int __init at91_pm_backup_init(vo\n \n securam_fail:\n \tput_device(&pdev->dev);\n-securam_fail_no_ref_dev:\n-\tiounmap(soc_pm.data.sfrbu);\n-\tsoc_pm.data.sfrbu = NULL;\n \treturn ret;\n }\n \n-static void __init at91_pm_use_default_mode(int pm_mode)\n-{\n-\tif (pm_mode != AT91_PM_ULP1 && pm_mode != AT91_PM_BACKUP)\n-\t\treturn;\n-\n-\tif (soc_pm.data.standby_mode == pm_mode)\n-\t\tsoc_pm.data.standby_mode = AT91_PM_ULP0;\n-\tif (soc_pm.data.suspend_mode == pm_mode)\n-\t\tsoc_pm.data.suspend_mode = AT91_PM_ULP0;\n-}\n-\n static const struct of_device_id atmel_shdwc_ids[] = {\n \t{ .compatible = \"atmel,sama5d2-shdwc\" },\n \t{ .compatible = \"microchip,sam9x60-shdwc\" },\n \t{ /* sentinel. */ }\n };\n \n-static void __init at91_pm_modes_init(void)\n+static void __init at91_pm_modes_init(const u32 *maps, int len)\n {\n \tstruct device_node *np;\n-\tint ret;\n+\tint ret, mode;\n \n-\tif (!at91_is_pm_mode_active(AT91_PM_BACKUP) &&\n-\t    !at91_is_pm_mode_active(AT91_PM_ULP1))\n-\t\treturn;\n+\tret = at91_pm_backup_init();\n+\tif (ret) {\n+\t\tif (soc_pm.data.standby_mode == AT91_PM_BACKUP)\n+\t\t\tsoc_pm.data.standby_mode = AT91_PM_ULP0;\n+\t\tif (soc_pm.data.suspend_mode == AT91_PM_BACKUP)\n+\t\t\tsoc_pm.data.suspend_mode = AT91_PM_ULP0;\n+\t}\n+\n+\tif (maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SHDWC) ||\n+\t    maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SHDWC)) {\n+\t\tnp = of_find_matching_node(NULL, atmel_shdwc_ids);\n+\t\tif (!np) {\n+\t\t\tpr_warn(\"%s: failed to find shdwc!\\n\", __func__);\n+\n+\t\t\t/* Use ULP0 if it doesn't needs SHDWC.*/\n+\t\t\tif (!(maps[AT91_PM_ULP0] & AT91_PM_IOMAP(SHDWC)))\n+\t\t\t\tmode = AT91_PM_ULP0;\n+\t\t\telse\n+\t\t\t\tmode = AT91_PM_STANDBY;\n+\n+\t\t\tif (maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SHDWC))\n+\t\t\t\tsoc_pm.data.standby_mode = mode;\n+\t\t\tif (maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SHDWC))\n+\t\t\t\tsoc_pm.data.suspend_mode = mode;\n+\t\t} else {\n+\t\t\tsoc_pm.data.shdwc = of_iomap(np, 0);\n+\t\t\tof_node_put(np);\n+\t\t}\n+\t}\n \n-\tnp = of_find_matching_node(NULL, atmel_shdwc_ids);\n-\tif (!np) {\n-\t\tpr_warn(\"%s: failed to find shdwc!\\n\", __func__);\n-\t\tgoto ulp1_default;\n+\tif (maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SFRBU) ||\n+\t    maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SFRBU)) {\n+\t\tnp = of_find_compatible_node(NULL, NULL, \"atmel,sama5d2-sfrbu\");\n+\t\tif (!np) {\n+\t\t\tpr_warn(\"%s: failed to find sfrbu!\\n\", __func__);\n+\n+\t\t\t/*\n+\t\t\t * Use ULP0 if it doesn't need SHDWC or if SHDWC\n+\t\t\t * was already located.\n+\t\t\t */\n+\t\t\tif (!(maps[AT91_PM_ULP0] & AT91_PM_IOMAP(SHDWC)) ||\n+\t\t\t    soc_pm.data.shdwc)\n+\t\t\t\tmode = AT91_PM_ULP0;\n+\t\t\telse\n+\t\t\t\tmode = AT91_PM_STANDBY;\n+\n+\t\t\tif (maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SFRBU))\n+\t\t\t\tsoc_pm.data.standby_mode = mode;\n+\t\t\tif (maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SFRBU))\n+\t\t\t\tsoc_pm.data.suspend_mode = mode;\n+\t\t} else {\n+\t\t\tsoc_pm.data.sfrbu = of_iomap(np, 0);\n+\t\t\tof_node_put(np);\n+\t\t}\n \t}\n \n-\tsoc_pm.data.shdwc = of_iomap(np, 0);\n-\tof_node_put(np);\n+\t/* Unmap all unnecessary. */\n+\tif (soc_pm.data.shdwc &&\n+\t    !(maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SHDWC) ||\n+\t      maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SHDWC))) {\n+\t\tiounmap(soc_pm.data.shdwc);\n+\t\tsoc_pm.data.shdwc = NULL;\n+\t}\n \n-\tret = at91_pm_backup_init();\n-\tif (ret) {\n-\t\tif (!at91_is_pm_mode_active(AT91_PM_ULP1))\n-\t\t\tgoto unmap;\n-\t\telse\n-\t\t\tgoto backup_default;\n+\tif (soc_pm.data.sfrbu &&\n+\t    !(maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SFRBU) ||\n+\t      maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SFRBU))) {\n+\t\tiounmap(soc_pm.data.sfrbu);\n+\t\tsoc_pm.data.sfrbu = NULL;\n \t}\n \n \treturn;\n-\n-unmap:\n-\tiounmap(soc_pm.data.shdwc);\n-\tsoc_pm.data.shdwc = NULL;\n-ulp1_default:\n-\tat91_pm_use_default_mode(AT91_PM_ULP1);\n-backup_default:\n-\tat91_pm_use_default_mode(AT91_PM_BACKUP);\n }\n \n struct pmc_info {\n@@ -936,13 +967,16 @@ void __init sam9x60_pm_init(void)\n \tstatic const int modes[] __initconst = {\n \t\tAT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP0_FAST, AT91_PM_ULP1,\n \t};\n+\tstatic const int iomaps[] __initconst = {\n+\t\t[AT91_PM_ULP1]\t\t= AT91_PM_IOMAP(SHDWC),\n+\t};\n \tint ret;\n \n \tif (!IS_ENABLED(CONFIG_SOC_SAM9X60))\n \t\treturn;\n \n \tat91_pm_modes_validate(modes, ARRAY_SIZE(modes));\n-\tat91_pm_modes_init();\n+\tat91_pm_modes_init(iomaps, ARRAY_SIZE(iomaps));\n \tret = at91_dt_ramc();\n \tif (ret)\n \t\treturn;\n@@ -999,13 +1033,18 @@ void __init sama5d2_pm_init(void)\n \t\tAT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP0_FAST, AT91_PM_ULP1,\n \t\tAT91_PM_BACKUP,\n \t};\n+\tstatic const u32 iomaps[] __initconst = {\n+\t\t[AT91_PM_ULP1]\t\t= AT91_PM_IOMAP(SHDWC),\n+\t\t[AT91_PM_BACKUP]\t= AT91_PM_IOMAP(SHDWC) |\n+\t\t\t\t\t  AT91_PM_IOMAP(SFRBU),\n+\t};\n \tint ret;\n \n \tif (!IS_ENABLED(CONFIG_SOC_SAMA5D2))\n \t\treturn;\n \n \tat91_pm_modes_validate(modes, ARRAY_SIZE(modes));\n-\tat91_pm_modes_init();\n+\tat91_pm_modes_init(iomaps, ARRAY_SIZE(iomaps));\n \tret = at91_dt_ramc();\n \tif (ret)\n \t\treturn;\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/201-ARM-at91-pm-do-not-initialize-pdev.patch",
    "content": "From 31e25503bbad1fffd29fd074a46bd4858b65304f Mon Sep 17 00:00:00 2001\nFrom: Claudiu Beznea <claudiu.beznea@microchip.com>\nDate: Thu, 15 Apr 2021 13:49:51 +0300\nSubject: [PATCH 201/247] ARM: at91: pm: do not initialize pdev\n\nThere is no need to initialize pdev.\n\nSigned-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>\nSigned-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>\nLink: https://lore.kernel.org/r/20210415105010.569620-6-claudiu.beznea@microchip.com\n---\n arch/arm/mach-at91/pm.c | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/arch/arm/mach-at91/pm.c\n+++ b/arch/arm/mach-at91/pm.c\n@@ -674,7 +674,7 @@ static int __init at91_pm_backup_init(vo\n {\n \tstruct gen_pool *sram_pool;\n \tstruct device_node *np;\n-\tstruct platform_device *pdev = NULL;\n+\tstruct platform_device *pdev;\n \tint ret = -ENODEV;\n \n \tif (!IS_ENABLED(CONFIG_SOC_SAMA5D2))\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/202-ARM-at91-pm-use-r7-instead-of-tmp1.patch",
    "content": "From 8a7a4cf3860910e460e2c3ca467b1dabf7ce9827 Mon Sep 17 00:00:00 2001\nFrom: Claudiu Beznea <claudiu.beznea@microchip.com>\nDate: Thu, 15 Apr 2021 13:49:52 +0300\nSubject: [PATCH 202/247] ARM: at91: pm: use r7 instead of tmp1\n\nUse r7 instead of tmp1 in macros. This prepares the filed for\nnext commits.\n\nSigned-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>\nSigned-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>\nLink: https://lore.kernel.org/r/20210415105010.569620-7-claudiu.beznea@microchip.com\n---\n arch/arm/mach-at91/pm_suspend.S | 18 ++++++++++++------\n 1 file changed, 12 insertions(+), 6 deletions(-)\n\n--- a/arch/arm/mach-at91/pm_suspend.S\n+++ b/arch/arm/mach-at91/pm_suspend.S\n@@ -31,30 +31,36 @@ tmp3\t.req\tr6\n \n /*\n  * Wait until master oscillator has stabilized.\n+ *\n+ * Side effects: overwrites r7\n  */\n \t.macro wait_moscrdy\n-1:\tldr\ttmp1, [pmc, #AT91_PMC_SR]\n-\ttst\ttmp1, #AT91_PMC_MOSCS\n+1:\tldr\tr7, [pmc, #AT91_PMC_SR]\n+\ttst\tr7, #AT91_PMC_MOSCS\n \tbeq\t1b\n \t.endm\n \n /*\n  * Wait for main oscillator selection is done\n+ *\n+ * Side effects: overwrites r7\n  */\n \t.macro wait_moscsels\n-1:\tldr\ttmp1, [pmc, #AT91_PMC_SR]\n-\ttst\ttmp1, #AT91_PMC_MOSCSELS\n+1:\tldr\tr7, [pmc, #AT91_PMC_SR]\n+\ttst\tr7, #AT91_PMC_MOSCSELS\n \tbeq\t1b\n \t.endm\n \n /*\n  * Put the processor to enter the idle state\n+ *\n+ * Side effects: overwrites r7\n  */\n \t.macro at91_cpu_idle\n \n #if defined(CONFIG_CPU_V7)\n-\tmov\ttmp1, #AT91_PMC_PCK\n-\tstr\ttmp1, [pmc, #AT91_PMC_SCDR]\n+\tmov\tr7, #AT91_PMC_PCK\n+\tstr\tr7, [pmc, #AT91_PMC_SCDR]\n \n \tdsb\n \n"
  },
  {
    "path": "target/linux/at91/patches-5.10/203-ARM-at91-pm-avoid-push-and-pop-on-stack-while-memory.patch",
    "content": "From 892f6d2fb9c42d4ac451236639599f533c37b507 Mon Sep 17 00:00:00 2001\nFrom: Claudiu Beznea <claudiu.beznea@microchip.com>\nDate: Thu, 15 Apr 2021 13:49:53 +0300\nSubject: [PATCH 203/247] ARM: at91: pm: avoid push and pop on stack while\n memory is in self-refersh\n\nFor the previous AT91 RAM controller and self-refresh procedure this\nhad no side effects. However, for SAMA7G5 the self-refresh procedure\ndoesn't allow this anymore as the RAM controller ports are closed\nbefore switching it to self-refresh. This commits prepares the code\nfor the following ones adding self-refresh and PM support for SAMA7G5.\n\nSigned-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>\nSigned-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>\nLink: https://lore.kernel.org/r/20210415105010.569620-8-claudiu.beznea@microchip.com\n---\n arch/arm/mach-at91/pm_suspend.S | 397 +++++++++++++++++---------------\n 1 file changed, 205 insertions(+), 192 deletions(-)\n\n--- a/arch/arm/mach-at91/pm_suspend.S\n+++ b/arch/arm/mach-at91/pm_suspend.S\n@@ -75,98 +75,147 @@ tmp3\t.req\tr6\n \n \t.arm\n \n-/*\n- * void at91_suspend_sram_fn(struct at91_pm_data*)\n- * @input param:\n- * \t@r0: base address of struct at91_pm_data\n+/**\n+ * Enable self-refresh\n+ *\n+ * register usage:\n+ * \t@r1: memory type\n+ *\t@r2: base address of the sram controller\n+ *\t@r3: temporary\n  */\n-/* at91_pm_suspend_in_sram must be 8-byte aligned per the requirements of fncpy() */\n-\t.align 3\n-ENTRY(at91_pm_suspend_in_sram)\n-\t/* Save registers on stack */\n-\tstmfd\tsp!, {r4 - r12, lr}\n+.macro at91_sramc_self_refresh_ena\n+\tldr\tr1, .memtype\n+\tldr\tr2, .sramc_base\n \n-\t/* Drain write buffer */\n-\tmov\ttmp1, #0\n-\tmcr\tp15, 0, tmp1, c7, c10, 4\n+\tcmp\tr1, #AT91_MEMCTRL_MC\n+\tbne\tsr_ena_ddrc_sf\n \n-\tldr\ttmp1, [r0, #PM_DATA_PMC]\n-\tstr\ttmp1, .pmc_base\n-\tldr\ttmp1, [r0, #PM_DATA_RAMC0]\n-\tstr\ttmp1, .sramc_base\n-\tldr\ttmp1, [r0, #PM_DATA_RAMC1]\n-\tstr\ttmp1, .sramc1_base\n-\tldr\ttmp1, [r0, #PM_DATA_MEMCTRL]\n-\tstr\ttmp1, .memtype\n-\tldr\ttmp1, [r0, #PM_DATA_MODE]\n-\tstr\ttmp1, .pm_mode\n-\tldr\ttmp1, [r0, #PM_DATA_PMC_MCKR_OFFSET]\n-\tstr\ttmp1, .mckr_offset\n-\tldr\ttmp1, [r0, #PM_DATA_PMC_VERSION]\n-\tstr\ttmp1, .pmc_version\n-\t/* Both ldrne below are here to preload their address in the TLB */\n-\tldr\ttmp1, [r0, #PM_DATA_SHDWC]\n-\tstr\ttmp1, .shdwc\n-\tcmp\ttmp1, #0\n-\tldrne\ttmp2, [tmp1, #0]\n-\tldr\ttmp1, [r0, #PM_DATA_SFRBU]\n-\tstr\ttmp1, .sfrbu\n-\tcmp\ttmp1, #0\n-\tldrne\ttmp2, [tmp1, #0x10]\n+\t/* Active SDRAM self-refresh mode */\n+\tmov\tr3, #1\n+\tstr\tr3, [r2, #AT91_MC_SDRAMC_SRR]\n+\tb\tsr_ena_exit\n \n-\t/* Active the self-refresh mode */\n-\tmov\tr0, #SRAMC_SELF_FRESH_ACTIVE\n-\tbl\tat91_sramc_self_refresh\n+sr_ena_ddrc_sf:\n+\tcmp\tr1, #AT91_MEMCTRL_DDRSDR\n+\tbne\tsr_ena_sdramc_sf\n \n-\tldr\tr0, .pm_mode\n-\tcmp\tr0, #AT91_PM_STANDBY\n-\tbeq\tstandby\n-\tcmp\tr0, #AT91_PM_BACKUP\n-\tbeq\tbackup_mode\n+\t/*\n+\t * DDR Memory controller\n+\t */\n \n-\tbl\tat91_ulp_mode\n-\tb\texit_suspend\n+\t/* LPDDR1 --> force DDR2 mode during self-refresh */\n+\tldr\tr3, [r2, #AT91_DDRSDRC_MDR]\n+\tstr\tr3, .saved_sam9_mdr\n+\tbic\tr3, r3, #~AT91_DDRSDRC_MD\n+\tcmp\tr3, #AT91_DDRSDRC_MD_LOW_POWER_DDR\n+\tldreq\tr3, [r2, #AT91_DDRSDRC_MDR]\n+\tbiceq\tr3, r3, #AT91_DDRSDRC_MD\n+\torreq\tr3, r3, #AT91_DDRSDRC_MD_DDR2\n+\tstreq\tr3, [r2, #AT91_DDRSDRC_MDR]\n \n-standby:\n-\t/* Wait for interrupt */\n-\tldr\tpmc, .pmc_base\n-\tat91_cpu_idle\n-\tb\texit_suspend\n+\t/* Active DDRC self-refresh mode */\n+\tldr\tr3, [r2, #AT91_DDRSDRC_LPR]\n+\tstr\tr3, .saved_sam9_lpr\n+\tbic\tr3, r3, #AT91_DDRSDRC_LPCB\n+\torr\tr3, r3, #AT91_DDRSDRC_LPCB_SELF_REFRESH\n+\tstr\tr3, [r2, #AT91_DDRSDRC_LPR]\n \n-backup_mode:\n-\tbl\tat91_backup_mode\n-\tb\texit_suspend\n+\t/* If using the 2nd ddr controller */\n+\tldr\tr2, .sramc1_base\n+\tcmp\tr2, #0\n+\tbeq\tsr_ena_no_2nd_ddrc\n \n-exit_suspend:\n-\t/* Exit the self-refresh mode */\n-\tmov\tr0, #SRAMC_SELF_FRESH_EXIT\n-\tbl\tat91_sramc_self_refresh\n+\tldr\tr3, [r2, #AT91_DDRSDRC_MDR]\n+\tstr\tr3, .saved_sam9_mdr1\n+\tbic\tr3, r3, #~AT91_DDRSDRC_MD\n+\tcmp\tr3, #AT91_DDRSDRC_MD_LOW_POWER_DDR\n+\tldreq\tr3, [r2, #AT91_DDRSDRC_MDR]\n+\tbiceq\tr3, r3, #AT91_DDRSDRC_MD\n+\torreq\tr3, r3, #AT91_DDRSDRC_MD_DDR2\n+\tstreq\tr3, [r2, #AT91_DDRSDRC_MDR]\n \n-\t/* Restore registers, and return */\n-\tldmfd\tsp!, {r4 - r12, pc}\n-ENDPROC(at91_pm_suspend_in_sram)\n+\t/* Active DDRC self-refresh mode */\n+\tldr\tr3, [r2, #AT91_DDRSDRC_LPR]\n+\tstr\tr3, .saved_sam9_lpr1\n+\tbic\tr3, r3, #AT91_DDRSDRC_LPCB\n+\torr\tr3, r3, #AT91_DDRSDRC_LPCB_SELF_REFRESH\n+\tstr\tr3, [r2, #AT91_DDRSDRC_LPR]\n \n-ENTRY(at91_backup_mode)\n-\t/* Switch the master clock source to slow clock. */\n-\tldr\tpmc, .pmc_base\n-\tldr\ttmp2, .mckr_offset\n-\tldr\ttmp1, [pmc, tmp2]\n-\tbic\ttmp1, tmp1, #AT91_PMC_CSS\n-\tstr\ttmp1, [pmc, tmp2]\n+sr_ena_no_2nd_ddrc:\n+\tb\tsr_ena_exit\n \n-\twait_mckrdy\n+\t/*\n+\t * SDRAMC Memory controller\n+\t */\n+sr_ena_sdramc_sf:\n+\t/* Active SDRAMC self-refresh mode */\n+\tldr\tr3, [r2, #AT91_SDRAMC_LPR]\n+\tstr\tr3, .saved_sam9_lpr\n+\tbic\tr3, r3, #AT91_SDRAMC_LPCB\n+\torr\tr3, r3, #AT91_SDRAMC_LPCB_SELF_REFRESH\n+\tstr\tr3, [r2, #AT91_SDRAMC_LPR]\n \n-\t/*BUMEN*/\n-\tldr\tr0, .sfrbu\n-\tmov\ttmp1, #0x1\n-\tstr\ttmp1, [r0, #0x10]\n+\tldr\tr3, .saved_sam9_lpr\n+\tstr\tr3, [r2, #AT91_SDRAMC_LPR]\n \n-\t/* Shutdown */\n-\tldr\tr0, .shdwc\n-\tmov\ttmp1, #0xA5000000\n-\tadd\ttmp1, tmp1, #0x1\n-\tstr\ttmp1, [r0, #0]\n-ENDPROC(at91_backup_mode)\n+sr_ena_exit:\n+.endm\n+\n+/**\n+ * Disable self-refresh\n+ *\n+ * register usage:\n+ * \t@r1: memory type\n+ *\t@r2: base address of the sram controller\n+ *\t@r3: temporary\n+ */\n+.macro at91_sramc_self_refresh_dis\n+\tldr\tr1, .memtype\n+\tldr\tr2, .sramc_base\n+\n+\tcmp\tr1, #AT91_MEMCTRL_MC\n+\tbne\tsr_dis_ddrc_exit_sf\n+\n+\t/*\n+\t * at91rm9200 Memory controller\n+\t */\n+\n+\t /*\n+\t  * For exiting the self-refresh mode, do nothing,\n+\t  * automatically exit the self-refresh mode.\n+\t  */\n+\tb\tsr_dis_exit\n+\n+sr_dis_ddrc_exit_sf:\n+\tcmp\tr1, #AT91_MEMCTRL_DDRSDR\n+\tbne\tsdramc_exit_sf\n+\n+\t/* DDR Memory controller */\n+\n+\t/* Restore MDR in case of LPDDR1 */\n+\tldr\tr3, .saved_sam9_mdr\n+\tstr\tr3, [r2, #AT91_DDRSDRC_MDR]\n+\t/* Restore LPR on AT91 with DDRAM */\n+\tldr\tr3, .saved_sam9_lpr\n+\tstr\tr3, [r2, #AT91_DDRSDRC_LPR]\n+\n+\t/* If using the 2nd ddr controller */\n+\tldr\tr2, .sramc1_base\n+\tcmp\tr2, #0\n+\tldrne\tr3, .saved_sam9_mdr1\n+\tstrne\tr3, [r2, #AT91_DDRSDRC_MDR]\n+\tldrne\tr3, .saved_sam9_lpr1\n+\tstrne\tr3, [r2, #AT91_DDRSDRC_LPR]\n+\n+\tb\tsr_dis_exit\n+\n+sdramc_exit_sf:\n+\t/* SDRAMC Memory controller */\n+\tldr\tr3, .saved_sam9_lpr\n+\tstr\tr3, [r2, #AT91_SDRAMC_LPR]\n+\n+sr_dis_exit:\n+.endm\n \n .macro at91_pm_ulp0_mode\n \tldr\tpmc, .pmc_base\n@@ -503,7 +552,7 @@ ENDPROC(at91_backup_mode)\n 2:\n .endm\n \n-ENTRY(at91_ulp_mode)\n+.macro at91_ulp_mode\n \tldr\tpmc, .pmc_base\n \tldr\ttmp2, .mckr_offset\n \tldr\ttmp3, .pm_mode\n@@ -552,133 +601,97 @@ ulp_exit:\n \n \twait_mckrdy\n \n-\tmov\tpc, lr\n-ENDPROC(at91_ulp_mode)\n-\n-/*\n- * void at91_sramc_self_refresh(unsigned int is_active)\n- *\n- * @input param:\n- *\t@r0: 1 - active self-refresh mode\n- *\t     0 - exit self-refresh mode\n- * register usage:\n- * \t@r1: memory type\n- *\t@r2: base address of the sram controller\n- */\n-\n-ENTRY(at91_sramc_self_refresh)\n-\tldr\tr1, .memtype\n-\tldr\tr2, .sramc_base\n-\n-\tcmp\tr1, #AT91_MEMCTRL_MC\n-\tbne\tddrc_sf\n-\n-\t/*\n-\t * at91rm9200 Memory controller\n-\t */\n-\n-\t /*\n-\t  * For exiting the self-refresh mode, do nothing,\n-\t  * automatically exit the self-refresh mode.\n-\t  */\n-\ttst\tr0, #SRAMC_SELF_FRESH_ACTIVE\n-\tbeq\texit_sramc_sf\n-\n-\t/* Active SDRAM self-refresh mode */\n-\tmov\tr3, #1\n-\tstr\tr3, [r2, #AT91_MC_SDRAMC_SRR]\n-\tb\texit_sramc_sf\n-\n-ddrc_sf:\n-\tcmp\tr1, #AT91_MEMCTRL_DDRSDR\n-\tbne\tsdramc_sf\n+.endm\n \n-\t/*\n-\t * DDR Memory controller\n-\t */\n-\ttst\tr0, #SRAMC_SELF_FRESH_ACTIVE\n-\tbeq\tddrc_exit_sf\n+.macro at91_backup_mode\n+\t/* Switch the master clock source to slow clock. */\n+\tldr\tpmc, .pmc_base\n+\tldr\ttmp2, .mckr_offset\n+\tldr\ttmp1, [pmc, tmp2]\n+\tbic\ttmp1, tmp1, #AT91_PMC_CSS\n+\tstr\ttmp1, [pmc, tmp2]\n \n-\t/* LPDDR1 --> force DDR2 mode during self-refresh */\n-\tldr\tr3, [r2, #AT91_DDRSDRC_MDR]\n-\tstr\tr3, .saved_sam9_mdr\n-\tbic\tr3, r3, #~AT91_DDRSDRC_MD\n-\tcmp\tr3, #AT91_DDRSDRC_MD_LOW_POWER_DDR\n-\tldreq\tr3, [r2, #AT91_DDRSDRC_MDR]\n-\tbiceq\tr3, r3, #AT91_DDRSDRC_MD\n-\torreq\tr3, r3, #AT91_DDRSDRC_MD_DDR2\n-\tstreq\tr3, [r2, #AT91_DDRSDRC_MDR]\n+\twait_mckrdy\n \n-\t/* Active DDRC self-refresh mode */\n-\tldr\tr3, [r2, #AT91_DDRSDRC_LPR]\n-\tstr\tr3, .saved_sam9_lpr\n-\tbic\tr3, r3, #AT91_DDRSDRC_LPCB\n-\torr\tr3, r3, #AT91_DDRSDRC_LPCB_SELF_REFRESH\n-\tstr\tr3, [r2, #AT91_DDRSDRC_LPR]\n+\t/*BUMEN*/\n+\tldr\tr0, .sfrbu\n+\tmov\ttmp1, #0x1\n+\tstr\ttmp1, [r0, #0x10]\n \n-\t/* If using the 2nd ddr controller */\n-\tldr\tr2, .sramc1_base\n-\tcmp\tr2, #0\n-\tbeq\tno_2nd_ddrc\n+\t/* Shutdown */\n+\tldr\tr0, .shdwc\n+\tmov\ttmp1, #0xA5000000\n+\tadd\ttmp1, tmp1, #0x1\n+\tstr\ttmp1, [r0, #0]\n+.endm\n \n-\tldr\tr3, [r2, #AT91_DDRSDRC_MDR]\n-\tstr\tr3, .saved_sam9_mdr1\n-\tbic\tr3, r3, #~AT91_DDRSDRC_MD\n-\tcmp\tr3, #AT91_DDRSDRC_MD_LOW_POWER_DDR\n-\tldreq\tr3, [r2, #AT91_DDRSDRC_MDR]\n-\tbiceq\tr3, r3, #AT91_DDRSDRC_MD\n-\torreq\tr3, r3, #AT91_DDRSDRC_MD_DDR2\n-\tstreq\tr3, [r2, #AT91_DDRSDRC_MDR]\n+/*\n+ * void at91_suspend_sram_fn(struct at91_pm_data*)\n+ * @input param:\n+ * \t@r0: base address of struct at91_pm_data\n+ */\n+/* at91_pm_suspend_in_sram must be 8-byte aligned per the requirements of fncpy() */\n+\t.align 3\n+ENTRY(at91_pm_suspend_in_sram)\n+\t/* Save registers on stack */\n+\tstmfd\tsp!, {r4 - r12, lr}\n \n-\t/* Active DDRC self-refresh mode */\n-\tldr\tr3, [r2, #AT91_DDRSDRC_LPR]\n-\tstr\tr3, .saved_sam9_lpr1\n-\tbic\tr3, r3, #AT91_DDRSDRC_LPCB\n-\torr\tr3, r3, #AT91_DDRSDRC_LPCB_SELF_REFRESH\n-\tstr\tr3, [r2, #AT91_DDRSDRC_LPR]\n+\t/* Drain write buffer */\n+\tmov\ttmp1, #0\n+\tmcr\tp15, 0, tmp1, c7, c10, 4\n \n-no_2nd_ddrc:\n-\tb\texit_sramc_sf\n+\tldr\ttmp1, [r0, #PM_DATA_PMC]\n+\tstr\ttmp1, .pmc_base\n+\tldr\ttmp1, [r0, #PM_DATA_RAMC0]\n+\tstr\ttmp1, .sramc_base\n+\tldr\ttmp1, [r0, #PM_DATA_RAMC1]\n+\tstr\ttmp1, .sramc1_base\n+\tldr\ttmp1, [r0, #PM_DATA_MEMCTRL]\n+\tstr\ttmp1, .memtype\n+\tldr\ttmp1, [r0, #PM_DATA_MODE]\n+\tstr\ttmp1, .pm_mode\n+\tldr\ttmp1, [r0, #PM_DATA_PMC_MCKR_OFFSET]\n+\tstr\ttmp1, .mckr_offset\n+\tldr\ttmp1, [r0, #PM_DATA_PMC_VERSION]\n+\tstr\ttmp1, .pmc_version\n+\t/* Both ldrne below are here to preload their address in the TLB */\n+\tldr\ttmp1, [r0, #PM_DATA_SHDWC]\n+\tstr\ttmp1, .shdwc\n+\tcmp\ttmp1, #0\n+\tldrne\ttmp2, [tmp1, #0]\n+\tldr\ttmp1, [r0, #PM_DATA_SFRBU]\n+\tstr\ttmp1, .sfrbu\n+\tcmp\ttmp1, #0\n+\tldrne\ttmp2, [tmp1, #0x10]\n \n-ddrc_exit_sf:\n-\t/* Restore MDR in case of LPDDR1 */\n-\tldr\tr3, .saved_sam9_mdr\n-\tstr\tr3, [r2, #AT91_DDRSDRC_MDR]\n-\t/* Restore LPR on AT91 with DDRAM */\n-\tldr\tr3, .saved_sam9_lpr\n-\tstr\tr3, [r2, #AT91_DDRSDRC_LPR]\n+\t/* Active the self-refresh mode */\n+\tat91_sramc_self_refresh_ena\n \n-\t/* If using the 2nd ddr controller */\n-\tldr\tr2, .sramc1_base\n-\tcmp\tr2, #0\n-\tldrne\tr3, .saved_sam9_mdr1\n-\tstrne\tr3, [r2, #AT91_DDRSDRC_MDR]\n-\tldrne\tr3, .saved_sam9_lpr1\n-\tstrne\tr3, [r2, #AT91_DDRSDRC_LPR]\n+\tldr\tr0, .pm_mode\n+\tcmp\tr0, #AT91_PM_STANDBY\n+\tbeq\tstandby\n+\tcmp\tr0, #AT91_PM_BACKUP\n+\tbeq\tbackup_mode\n \n-\tb\texit_sramc_sf\n+\tat91_ulp_mode\n+\tb\texit_suspend\n \n-\t/*\n-\t * SDRAMC Memory controller\n-\t */\n-sdramc_sf:\n-\ttst\tr0, #SRAMC_SELF_FRESH_ACTIVE\n-\tbeq\tsdramc_exit_sf\n+standby:\n+\t/* Wait for interrupt */\n+\tldr\tpmc, .pmc_base\n+\tat91_cpu_idle\n+\tb\texit_suspend\n \n-\t/* Active SDRAMC self-refresh mode */\n-\tldr\tr3, [r2, #AT91_SDRAMC_LPR]\n-\tstr\tr3, .saved_sam9_lpr\n-\tbic\tr3, r3, #AT91_SDRAMC_LPCB\n-\torr\tr3, r3, #AT91_SDRAMC_LPCB_SELF_REFRESH\n-\tstr\tr3, [r2, #AT91_SDRAMC_LPR]\n+backup_mode:\n+\tat91_backup_mode\n \n-sdramc_exit_sf:\n-\tldr\tr3, .saved_sam9_lpr\n-\tstr\tr3, [r2, #AT91_SDRAMC_LPR]\n+exit_suspend:\n+\t/* Exit the self-refresh mode */\n+\tat91_sramc_self_refresh_dis\n \n-exit_sramc_sf:\n-\tmov\tpc, lr\n-ENDPROC(at91_sramc_self_refresh)\n+\t/* Restore registers, and return */\n+\tldmfd\tsp!, {r4 - r12, pc}\n+ENDPROC(at91_pm_suspend_in_sram)\n \n .pmc_base:\n \t.word 0\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/204-ARM-at91-pm-s-CONFIG_SOC_SAM9X60-CONFIG_HAVE_AT91_SA.patch",
    "content": "From 673d2519e9028dafb678fac29a990740958bed3c Mon Sep 17 00:00:00 2001\nFrom: Claudiu Beznea <claudiu.beznea@microchip.com>\nDate: Thu, 15 Apr 2021 13:49:54 +0300\nSubject: [PATCH 204/247] ARM: at91: pm:\n s/CONFIG_SOC_SAM9X60/CONFIG_HAVE_AT91_SAM9X60_PLL/g\n\nReplace CONFIG_SOC_SAM9X60 with CONFIG_HAVE_AT91_SAM9X60_PLL as the\nSAM9X60's PLL is also present on SAMA7G5.\n\nSigned-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>\nSigned-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>\nLink: https://lore.kernel.org/r/20210415105010.569620-9-claudiu.beznea@microchip.com\n---\n arch/arm/mach-at91/pm_suspend.S | 4 ++--\n 1 file changed, 2 insertions(+), 2 deletions(-)\n\n--- a/arch/arm/mach-at91/pm_suspend.S\n+++ b/arch/arm/mach-at91/pm_suspend.S\n@@ -422,7 +422,7 @@ sr_dis_exit:\n \tcmp\ttmp1, #AT91_PMC_V1\n \tbeq\t1f\n \n-#ifdef CONFIG_SOC_SAM9X60\n+#ifdef CONFIG_HAVE_AT91_SAM9X60_PLL\n \t/* Save PLLA settings. */\n \tldr\ttmp2, [pmc, #AT91_PMC_PLL_UPDT]\n \tbic\ttmp2, tmp2, #AT91_PMC_PLL_UPDT_ID\n@@ -489,7 +489,7 @@ sr_dis_exit:\n \tcmp\ttmp3, #AT91_PMC_V1\n \tbeq\t4f\n \n-#ifdef CONFIG_SOC_SAM9X60\n+#ifdef CONFIG_HAVE_AT91_SAM9X60_PLL\n \t/* step 1. */\n \tldr\ttmp1, [pmc, #AT91_PMC_PLL_UPDT]\n \tbic\ttmp1, tmp1, #AT91_PMC_PLL_UPDT_ID\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/205-ARM-at91-pm-add-support-for-waiting-MCK1.4.patch",
    "content": "From 67face049c62cb37cf93da26b7fea037228d1d3d Mon Sep 17 00:00:00 2001\nFrom: Claudiu Beznea <claudiu.beznea@microchip.com>\nDate: Thu, 15 Apr 2021 13:49:55 +0300\nSubject: [PATCH 205/247] ARM: at91: pm: add support for waiting MCK1..4\n\nSAMA7G5 has 5 master clocks 0..4. MCK0 is controlled differently than\nMCK 1..4. MCK 1..4 should also be saved/restored in the last phase of\nsuspend/resume. Thus, adapt wait_mckrdy to support also MCK1..4.\n\nSigned-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>\nSigned-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>\nLink: https://lore.kernel.org/r/20210415105010.569620-10-claudiu.beznea@microchip.com\n---\n arch/arm/mach-at91/pm_suspend.S | 48 ++++++++++++++++++++++++---------\n 1 file changed, 35 insertions(+), 13 deletions(-)\n\n--- a/arch/arm/mach-at91/pm_suspend.S\n+++ b/arch/arm/mach-at91/pm_suspend.S\n@@ -22,11 +22,23 @@ tmp3\t.req\tr6\n \n /*\n  * Wait until master clock is ready (after switching master clock source)\n+ *\n+ * @r_mckid:\tregister holding master clock identifier\n+ *\n+ * Side effects: overwrites r7, r8\n  */\n-\t.macro wait_mckrdy\n-1:\tldr\ttmp1, [pmc, #AT91_PMC_SR]\n-\ttst\ttmp1, #AT91_PMC_MCKRDY\n-\tbeq\t1b\n+\t.macro wait_mckrdy r_mckid\n+#ifdef CONFIG_SOC_SAMA7\n+\tcmp\t\\r_mckid, #0\n+\tbeq\t1f\n+\tmov\tr7, #AT91_PMC_MCKXRDY\n+\tb\t2f\n+#endif\n+1:\tmov\tr7, #AT91_PMC_MCKRDY\n+2:\tldr\tr8, [pmc, #AT91_PMC_SR]\n+\tand\tr8, r7\n+\tcmp\tr8, r7\n+\tbne\t2b\n \t.endm\n \n /*\n@@ -231,7 +243,9 @@ sr_dis_exit:\n \tbic\ttmp1, tmp1, #AT91_PMC_PRES\n \torr\ttmp1, tmp1, #AT91_PMC_PRES_64\n \tstr\ttmp1, [pmc, tmp3]\n-\twait_mckrdy\n+\n+\tmov\ttmp3, #0\n+\twait_mckrdy tmp3\n \tb\t1f\n \n 0:\n@@ -267,10 +281,13 @@ sr_dis_exit:\n \tbne\t5f\n \n \t/* Set lowest prescaler for fast resume. */\n+\tldr\ttmp3, .mckr_offset\n \tldr\ttmp1, [pmc, tmp3]\n \tbic\ttmp1, tmp1, #AT91_PMC_PRES\n \tstr\ttmp1, [pmc, tmp3]\n-\twait_mckrdy\n+\n+\tmov\ttmp3, #0\n+\twait_mckrdy tmp3\n \tb\t6f\n \n 5:\t/* Restore RC oscillator state */\n@@ -307,6 +324,7 @@ sr_dis_exit:\n .macro at91_pm_ulp1_mode\n \tldr\tpmc, .pmc_base\n \tldr\ttmp2, .mckr_offset\n+\tmov\ttmp3, #0\n \n \t/* Save RC oscillator state and check if it is enabled. */\n \tldr\ttmp1, [pmc, #AT91_PMC_SR]\n@@ -348,7 +366,7 @@ sr_dis_exit:\n \torr\ttmp1, tmp1, #AT91_PMC_CSS_MAIN\n \tstr\ttmp1, [pmc, tmp2]\n \n-\twait_mckrdy\n+\twait_mckrdy tmp3\n \n \t/* Enter the ULP1 mode by set WAITMODE bit in CKGR_MOR */\n \tldr\ttmp1, [pmc, #AT91_CKGR_MOR]\n@@ -361,7 +379,7 @@ sr_dis_exit:\n \tnop\n \tnop\n \n-\twait_mckrdy\n+\twait_mckrdy tmp3\n \n \t/* Enable the crystal oscillator */\n \tldr\ttmp1, [pmc, #AT91_CKGR_MOR]\n@@ -377,7 +395,7 @@ sr_dis_exit:\n \tbic\ttmp1, tmp1, #AT91_PMC_CSS\n \tstr\ttmp1, [pmc, tmp2]\n \n-\twait_mckrdy\n+\twait_mckrdy tmp3\n \n \t/* Switch main clock source to crystal oscillator */\n \tldr\ttmp1, [pmc, #AT91_CKGR_MOR]\n@@ -394,7 +412,7 @@ sr_dis_exit:\n \torr\ttmp1, tmp1, #AT91_PMC_CSS_MAIN\n \tstr\ttmp1, [pmc, tmp2]\n \n-\twait_mckrdy\n+\twait_mckrdy tmp3\n \n \t/* Restore RC oscillator state */\n \tldr\ttmp1, .saved_osc_status\n@@ -573,10 +591,12 @@ sr_dis_exit:\n save_mck:\n \tstr\ttmp1, [pmc, tmp2]\n \n-\twait_mckrdy\n+\tmov\ttmp3, #0\n+\twait_mckrdy tmp3\n \n \tat91_plla_disable\n \n+\tldr\ttmp3, .pm_mode\n \tcmp\ttmp3, #AT91_PM_ULP1\n \tbeq\tulp1_mode\n \n@@ -599,7 +619,8 @@ ulp_exit:\n \tldr\ttmp2, .saved_mckr\n \tstr\ttmp2, [pmc, tmp1]\n \n-\twait_mckrdy\n+\tmov\ttmp3, #0\n+\twait_mckrdy tmp3\n \n .endm\n \n@@ -611,7 +632,8 @@ ulp_exit:\n \tbic\ttmp1, tmp1, #AT91_PMC_CSS\n \tstr\ttmp1, [pmc, tmp2]\n \n-\twait_mckrdy\n+\tmov\ttmp3, #0\n+\twait_mckrdy tmp3\n \n \t/*BUMEN*/\n \tldr\tr0, .sfrbu\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/206-ARM-at91-sfrbu-add-sfrbu-registers-definitions-for-s.patch",
    "content": "From c6b435625975d9a6daeffd81509a9877ddfb93b5 Mon Sep 17 00:00:00 2001\nFrom: Claudiu Beznea <claudiu.beznea@microchip.com>\nDate: Thu, 15 Apr 2021 13:49:56 +0300\nSubject: [PATCH 206/247] ARM: at91: sfrbu: add sfrbu registers definitions for\n sama7g5\n\nAdd SFRBU registers definitions for SAMA7G5.\n\nSigned-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>\nSigned-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>\nLink: https://lore.kernel.org/r/20210415105010.569620-11-claudiu.beznea@microchip.com\n---\n include/soc/at91/sama7-sfrbu.h | 34 ++++++++++++++++++++++++++++++++++\n 1 file changed, 34 insertions(+)\n create mode 100644 include/soc/at91/sama7-sfrbu.h\n\n--- /dev/null\n+++ b/include/soc/at91/sama7-sfrbu.h\n@@ -0,0 +1,34 @@\n+/* SPDX-License-Identifier: GPL-2.0-only */\n+/*\n+ * Microchip SAMA7 SFRBU registers offsets and bit definitions.\n+ *\n+ * Copyright (C) [2020] Microchip Technology Inc. and its subsidiaries\n+ *\n+ * Author: Claudu Beznea <claudiu.beznea@microchip.com>\n+ */\n+\n+#ifndef __SAMA7_SFRBU_H__\n+#define __SAMA7_SFRBU_H__\n+\n+#ifdef CONFIG_SOC_SAMA7\n+\n+#define AT91_SFRBU_PSWBU\t\t\t(0x00)\t\t/* SFRBU Power Switch BU Control Register */\n+#define\t\tAT91_SFRBU_PSWBU_PSWKEY\t\t(0x4BD20C << 8)\t/* Specific value mandatory to allow writing of other register bits */\n+#define\t\tAT91_SFRBU_PSWBU_STATE\t\t(1 << 2)\t/* Power switch BU state */\n+#define\t\tAT91_SFRBU_PSWBU_SOFTSWITCH\t(1 << 1)\t/* Power switch BU source selection */\n+#define\t\tAT91_SFRBU_PSWBU_CTRL\t\t(1 << 0)\t/* Power switch BU control */\n+\n+#define AT91_SFRBU_25LDOCR\t\t\t(0x0C)\t\t/* SFRBU 2.5V LDO Control Register */\n+#define\t\tAT91_SFRBU_25LDOCR_LDOANAKEY\t(0x3B6E18 << 8)\t/* Specific value mandatory to allow writing of other register bits. */\n+#define\t\tAT91_SFRBU_25LDOCR_STATE\t(1 << 3)\t/* LDOANA Switch On/Off Control */\n+#define\t\tAT91_SFRBU_25LDOCR_LP\t\t(1 << 2)\t/* LDOANA Low-Power Mode Control */\n+#define\t\tAT91_SFRBU_PD_VALUE_MSK\t\t(0x3)\n+#define\t\tAT91_SFRBU_25LDOCR_PD_VALUE(v)\t((v) & AT91_SFRBU_PD_VALUE_MSK)\t/* LDOANA Pull-down value */\n+\n+#define AT91_FRBU_DDRPWR\t\t\t(0x10)\t\t/* SFRBU DDR Power Control Register */\n+#define\t\tAT91_FRBU_DDRPWR_STATE\t\t(1 << 0)\t/* DDR Power Mode State */\n+\n+#endif /* CONFIG_SOC_SAMA7 */\n+\n+#endif /* __SAMA7_SFRBU_H__ */\n+\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/207-ARM-at91-ddr-add-registers-definitions-for-sama7g5-s.patch",
    "content": "From 0005be9abfcddf9a29c6d07afe06caa41560d424 Mon Sep 17 00:00:00 2001\nFrom: Claudiu Beznea <claudiu.beznea@microchip.com>\nDate: Thu, 15 Apr 2021 13:49:57 +0300\nSubject: [PATCH 207/247] ARM: at91: ddr: add registers definitions for\n sama7g5's ddr\n\nAdd registers and bits definitions for SAMA7G5's UDDRC and DDR3PHY.\n\nSigned-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>\nSigned-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>\nLink: https://lore.kernel.org/r/20210415105010.569620-12-claudiu.beznea@microchip.com\n---\n include/soc/at91/sama7-ddr.h | 80 ++++++++++++++++++++++++++++++++++++\n 1 file changed, 80 insertions(+)\n create mode 100644 include/soc/at91/sama7-ddr.h\n\n--- /dev/null\n+++ b/include/soc/at91/sama7-ddr.h\n@@ -0,0 +1,80 @@\n+/* SPDX-License-Identifier: GPL-2.0-only */\n+/*\n+ * Microchip SAMA7 UDDR Controller and DDR3 PHY Controller registers offsets\n+ * and bit definitions.\n+ *\n+ * Copyright (C) [2020] Microchip Technology Inc. and its subsidiaries\n+ *\n+ * Author: Claudu Beznea <claudiu.beznea@microchip.com>\n+ */\n+\n+#ifndef __SAMA7_DDR_H__\n+#define __SAMA7_DDR_H__\n+\n+#ifdef CONFIG_SOC_SAMA7\n+\n+/* DDR3PHY */\n+#define DDR3PHY_PIR\t\t\t\t(0x04)\t\t/* DDR3PHY PHY Initialization Register\t*/\n+#define\tDDR3PHY_PIR_DLLBYP\t\t(1 << 17)\t/* DLL Bypass */\n+#define\t\tDDR3PHY_PIR_ITMSRST\t\t(1 << 4)\t/* Interface Timing Module Soft Reset */\n+#define\tDDR3PHY_PIR_DLLLOCK\t\t(1 << 2)\t/* DLL Lock */\n+#define\t\tDDR3PHY_PIR_DLLSRST\t\t(1 << 1)\t/* DLL Soft Rest */\n+#define\tDDR3PHY_PIR_INIT\t\t(1 << 0)\t/* Initialization Trigger */\n+\n+#define DDR3PHY_PGCR\t\t\t\t(0x08)\t\t/* DDR3PHY PHY General Configuration Register */\n+#define\t\tDDR3PHY_PGCR_CKDV1\t\t(1 << 13)\t/* CK# Disable Value */\n+#define\t\tDDR3PHY_PGCR_CKDV0\t\t(1 << 12)\t/* CK Disable Value */\n+\n+#define\tDDR3PHY_PGSR\t\t\t\t(0x0C)\t\t/* DDR3PHY PHY General Status Register */\n+#define\t\tDDR3PHY_PGSR_IDONE\t\t(1 << 0)\t/* Initialization Done */\n+\n+#define DDR3PHY_ACIOCR\t\t\t\t(0x24)\t\t/*  DDR3PHY AC I/O Configuration Register */\n+#define\t\tDDR3PHY_ACIOCR_CSPDD_CS0\t(1 << 18)\t/* CS#[0] Power Down Driver */\n+#define\t\tDDR3PHY_ACIOCR_CKPDD_CK0\t(1 << 8)\t/* CK[0] Power Down Driver */\n+#define\t\tDDR3PHY_ACIORC_ACPDD\t\t(1 << 3)\t/* AC Power Down Driver */\n+\n+#define DDR3PHY_DXCCR\t\t\t\t(0x28)\t\t/* DDR3PHY DATX8 Common Configuration Register */\n+#define\t\tDDR3PHY_DXCCR_DXPDR\t\t(1 << 3)\t/* Data Power Down Receiver */\n+\n+#define DDR3PHY_DSGCR\t\t\t\t(0x2C)\t\t/* DDR3PHY DDR System General Configuration Register */\n+#define\t\tDDR3PHY_DSGCR_ODTPDD_ODT0\t(1 << 20)\t/* ODT[0] Power Down Driver */\n+\n+#define DDR3PHY_ZQ0SR0\t\t\t\t(0x188)\t\t/* ZQ status register 0 */\n+\n+/* UDDRC */\n+#define UDDRC_STAT\t\t\t\t(0x04)\t\t/* UDDRC Operating Mode Status Register */\n+#define\t\tUDDRC_STAT_SELFREF_TYPE_DIS\t(0x0 << 4)\t/* SDRAM is not in Self-refresh */\n+#define\t\tUDDRC_STAT_SELFREF_TYPE_PHY\t(0x1 << 4)\t/* SDRAM is in Self-refresh, which was caused by PHY Master Request */\n+#define\t\tUDDRC_STAT_SELFREF_TYPE_SW\t(0x2 << 4)\t/* SDRAM is in Self-refresh, which was not caused solely under Automatic Self-refresh control */\n+#define\t\tUDDRC_STAT_SELFREF_TYPE_AUTO\t(0x3 << 4)\t/* SDRAM is in Self-refresh, which was caused by Automatic Self-refresh only */\n+#define\t\tUDDRC_STAT_SELFREF_TYPE_MSK\t(0x3 << 4)\t/* Self-refresh type mask */\n+#define\t\tUDDRC_STAT_OPMODE_INIT\t\t(0x0 << 0)\t/* Init */\n+#define\t\tUDDRC_STAT_OPMODE_NORMAL\t(0x1 << 0)\t/* Normal */\n+#define\t\tUDDRC_STAT_OPMODE_PWRDOWN\t(0x2 << 0)\t/* Power-down */\n+#define\t\tUDDRC_STAT_OPMODE_SELF_REFRESH\t(0x3 << 0)\t/* Self-refresh */\n+#define\t\tUDDRC_STAT_OPMODE_MSK\t\t(0x7 << 0)\t/* Operating mode mask */\n+\n+#define UDDRC_PWRCTL\t\t\t\t(0x30)\t\t/* UDDRC Low Power Control Register */\n+#define\t\tUDDRC_PWRCTRL_SELFREF_SW\t(1 << 5)\t/* Software self-refresh */\n+\n+#define UDDRC_DFIMISC\t\t\t\t(0x1B0)\t\t/* UDDRC DFI Miscellaneous Control Register */\n+#define\t\tUDDRC_DFIMISC_DFI_INIT_COMPLETE_EN (1 << 0)\t/* PHY initialization complete enable signal */\n+\n+#define UDDRC_SWCTRL\t\t\t\t(0x320)\t\t/* UDDRC Software Register Programming Control Enable */\n+#define\t\tUDDRC_SWCTRL_SW_DONE\t\t(1 << 0)\t/* Enable quasi-dynamic register programming outside reset */\n+\n+#define UDDRC_SWSTAT\t\t\t\t(0x324)\t\t/* UDDRC Software Register Programming Control Status */\n+#define\t\tUDDRC_SWSTAT_SW_DONE_ACK\t(1 << 0)\t/* Register programming done */\n+\n+#define UDDRC_PSTAT\t\t\t\t(0x3FC)\t\t/* UDDRC Port Status Register */\n+#define\tUDDRC_PSTAT_ALL_PORTS\t\t(0x1F001F)\t/* Read + writes outstanding transactions on all ports */\n+\n+#define UDDRC_PCTRL_0\t\t\t\t(0x490)\t\t/* UDDRC Port 0 Control Register */\n+#define UDDRC_PCTRL_1\t\t\t\t(0x540)\t\t/* UDDRC Port 1 Control Register */\n+#define UDDRC_PCTRL_2\t\t\t\t(0x5F0)\t\t/* UDDRC Port 2 Control Register */\n+#define UDDRC_PCTRL_3\t\t\t\t(0x6A0)\t\t/* UDDRC Port 3 Control Register */\n+#define UDDRC_PCTRL_4\t\t\t\t(0x750)\t\t/* UDDRC Port 4 Control Register */\n+\n+#endif /* CONFIG_SOC_SAMA7 */\n+\n+#endif /* __SAMA7_DDR_H__ */\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/208-ARM-at91-pm-add-self-refresh-support-for-sama7g5.patch",
    "content": "From 1bfd85d71703f80392a71043caf74f159bec97b8 Mon Sep 17 00:00:00 2001\nFrom: Claudiu Beznea <claudiu.beznea@microchip.com>\nDate: Thu, 15 Apr 2021 13:49:58 +0300\nSubject: [PATCH 208/247] ARM: at91: pm: add self-refresh support for sama7g5\n\nAdd self-refresh support for SAMA7G5.\n\nSigned-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>\nSigned-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>\nLink: https://lore.kernel.org/r/20210415105010.569620-13-claudiu.beznea@microchip.com\n---\n arch/arm/mach-at91/pm.h              |   2 +\n arch/arm/mach-at91/pm_data-offsets.c |   2 +\n arch/arm/mach-at91/pm_suspend.S      | 199 +++++++++++++++++++++++++++\n 3 files changed, 203 insertions(+)\n\n--- a/arch/arm/mach-at91/pm.h\n+++ b/arch/arm/mach-at91/pm.h\n@@ -12,6 +12,7 @@\n #include <linux/mfd/syscon/atmel-mc.h>\n #include <soc/at91/at91sam9_ddrsdr.h>\n #include <soc/at91/at91sam9_sdramc.h>\n+#include <soc/at91/sama7-ddr.h>\n \n #define AT91_MEMCTRL_MC\t\t0\n #define AT91_MEMCTRL_SDRAMC\t1\n@@ -27,6 +28,7 @@\n struct at91_pm_data {\n \tvoid __iomem *pmc;\n \tvoid __iomem *ramc[2];\n+\tvoid __iomem *ramc_phy;\n \tunsigned long uhp_udp_mask;\n \tunsigned int memctrl;\n \tunsigned int mode;\n--- a/arch/arm/mach-at91/pm_data-offsets.c\n+++ b/arch/arm/mach-at91/pm_data-offsets.c\n@@ -8,6 +8,8 @@ int main(void)\n \tDEFINE(PM_DATA_PMC,\t\toffsetof(struct at91_pm_data, pmc));\n \tDEFINE(PM_DATA_RAMC0,\t\toffsetof(struct at91_pm_data, ramc[0]));\n \tDEFINE(PM_DATA_RAMC1,\t\toffsetof(struct at91_pm_data, ramc[1]));\n+\tDEFINE(PM_DATA_RAMC_PHY,\toffsetof(struct at91_pm_data,\n+\t\t\t\t\t\t ramc_phy));\n \tDEFINE(PM_DATA_MEMCTRL,\toffsetof(struct at91_pm_data, memctrl));\n \tDEFINE(PM_DATA_MODE,\t\toffsetof(struct at91_pm_data, mode));\n \tDEFINE(PM_DATA_SHDWC,\t\toffsetof(struct at91_pm_data, shdwc));\n--- a/arch/arm/mach-at91/pm_suspend.S\n+++ b/arch/arm/mach-at91/pm_suspend.S\n@@ -87,6 +87,200 @@ tmp3\t.req\tr6\n \n \t.arm\n \n+#ifdef CONFIG_SOC_SAMA7\n+/**\n+ * Enable self-refresh\n+ *\n+ * Side effects: overwrites r2, r3, tmp1, tmp2, tmp3, r7\n+ */\n+.macro at91_sramc_self_refresh_ena\n+\tldr\tr2, .sramc_base\n+\tldr\tr3, .sramc_phy_base\n+\tldr\tr7, .pm_mode\n+\n+\tdsb\n+\n+\t/* Disable all AXI ports. */\n+\tldr\ttmp1, [r2, #UDDRC_PCTRL_0]\n+\tbic\ttmp1, tmp1, #0x1\n+\tstr\ttmp1, [r2, #UDDRC_PCTRL_0]\n+\n+\tldr\ttmp1, [r2, #UDDRC_PCTRL_1]\n+\tbic\ttmp1, tmp1, #0x1\n+\tstr\ttmp1, [r2, #UDDRC_PCTRL_1]\n+\n+\tldr\ttmp1, [r2, #UDDRC_PCTRL_2]\n+\tbic\ttmp1, tmp1, #0x1\n+\tstr\ttmp1, [r2, #UDDRC_PCTRL_2]\n+\n+\tldr\ttmp1, [r2, #UDDRC_PCTRL_3]\n+\tbic\ttmp1, tmp1, #0x1\n+\tstr\ttmp1, [r2, #UDDRC_PCTRL_3]\n+\n+\tldr\ttmp1, [r2, #UDDRC_PCTRL_4]\n+\tbic\ttmp1, tmp1, #0x1\n+\tstr\ttmp1, [r2, #UDDRC_PCTRL_4]\n+\n+sr_ena_1:\n+\t/* Wait for all ports to disable. */\n+\tldr\ttmp1, [r2, #UDDRC_PSTAT]\n+\tldr\ttmp2, =UDDRC_PSTAT_ALL_PORTS\n+\ttst\ttmp1, tmp2\n+\tbne\tsr_ena_1\n+\n+\t/* Switch to self-refresh. */\n+\tldr\ttmp1, [r2, #UDDRC_PWRCTL]\n+\torr\ttmp1, tmp1, #UDDRC_PWRCTRL_SELFREF_SW\n+\tstr\ttmp1, [r2, #UDDRC_PWRCTL]\n+\n+sr_ena_2:\n+\t/* Wait for self-refresh enter. */\n+\tldr\ttmp1, [r2, #UDDRC_STAT]\n+\tbic\ttmp1, tmp1, #~UDDRC_STAT_SELFREF_TYPE_MSK\n+\tcmp\ttmp1, #UDDRC_STAT_SELFREF_TYPE_SW\n+\tbne\tsr_ena_2\n+\n+\t/* Put DDR PHY's DLL in bypass mode for non-backup modes. */\n+\tcmp\tr7, #AT91_PM_BACKUP\n+\tbeq\tsr_ena_3\n+\tldr\ttmp1, [r3, #DDR3PHY_PIR]\n+\torr\ttmp1, tmp1, #DDR3PHY_PIR_DLLBYP\n+\tstr\ttmp1, [r3, #DDR3PHY_PIR]\n+\n+sr_ena_3:\n+\t/* Power down DDR PHY data receivers. */\n+\tldr\ttmp1, [r3, #DDR3PHY_DXCCR]\n+\torr\ttmp1, tmp1, #DDR3PHY_DXCCR_DXPDR\n+\tstr\ttmp1, [r3, #DDR3PHY_DXCCR]\n+\n+\t/* Power down ADDR/CMD IO. */\n+\tldr\ttmp1, [r3, #DDR3PHY_ACIOCR]\n+\torr\ttmp1, tmp1, #DDR3PHY_ACIORC_ACPDD\n+\torr\ttmp1, tmp1, #DDR3PHY_ACIOCR_CKPDD_CK0\n+\torr\ttmp1, tmp1, #DDR3PHY_ACIOCR_CSPDD_CS0\n+\tstr\ttmp1, [r3, #DDR3PHY_ACIOCR]\n+\n+\t/* Power down ODT. */\n+\tldr\ttmp1, [r3, #DDR3PHY_DSGCR]\n+\torr\ttmp1, tmp1, #DDR3PHY_DSGCR_ODTPDD_ODT0\n+\tstr\ttmp1, [r3, #DDR3PHY_DSGCR]\n+.endm\n+\n+/**\n+ * Disable self-refresh\n+ *\n+ * Side effects: overwrites r2, r3, tmp1, tmp2, tmp3\n+ */\n+.macro at91_sramc_self_refresh_dis\n+\tldr\tr2, .sramc_base\n+\tldr\tr3, .sramc_phy_base\n+\n+\t/* Power up DDR PHY data receivers. */\n+\tldr\ttmp1, [r3, #DDR3PHY_DXCCR]\n+\tbic\ttmp1, tmp1, #DDR3PHY_DXCCR_DXPDR\n+\tstr\ttmp1, [r3, #DDR3PHY_DXCCR]\n+\n+\t/* Power up the output of CK and CS pins. */\n+\tldr\ttmp1, [r3, #DDR3PHY_ACIOCR]\n+\tbic\ttmp1, tmp1, #DDR3PHY_ACIORC_ACPDD\n+\tbic\ttmp1, tmp1, #DDR3PHY_ACIOCR_CKPDD_CK0\n+\tbic\ttmp1, tmp1, #DDR3PHY_ACIOCR_CSPDD_CS0\n+\tstr\ttmp1, [r3, #DDR3PHY_ACIOCR]\n+\n+\t/* Power up ODT. */\n+\tldr\ttmp1, [r3, #DDR3PHY_DSGCR]\n+\tbic\ttmp1, tmp1, #DDR3PHY_DSGCR_ODTPDD_ODT0\n+\tstr\ttmp1, [r3, #DDR3PHY_DSGCR]\n+\n+\t/* Take DDR PHY's DLL out of bypass mode. */\n+\tldr\ttmp1, [r3, #DDR3PHY_PIR]\n+\tbic\ttmp1, tmp1, #DDR3PHY_PIR_DLLBYP\n+\tstr\ttmp1, [r3, #DDR3PHY_PIR]\n+\n+\t/* Enable quasi-dynamic programming. */\n+\tmov\ttmp1, #0\n+\tstr\ttmp1, [r2, #UDDRC_SWCTRL]\n+\n+\t/* De-assert SDRAM initialization. */\n+\tldr\ttmp1, [r2, #UDDRC_DFIMISC]\n+\tbic\ttmp1, tmp1, #UDDRC_DFIMISC_DFI_INIT_COMPLETE_EN\n+\tstr\ttmp1, [r2, #UDDRC_DFIMISC]\n+\n+\t/* Quasi-dynamic programming done. */\n+\tmov\ttmp1, #UDDRC_SWCTRL_SW_DONE\n+\tstr\ttmp1, [r2, #UDDRC_SWCTRL]\n+\n+sr_dis_1:\n+\tldr\ttmp1, [r2, #UDDRC_SWSTAT]\n+\ttst\ttmp1, #UDDRC_SWSTAT_SW_DONE_ACK\n+\tbeq\tsr_dis_1\n+\n+\t/* DLL soft-reset + DLL lock wait + ITM reset */\n+\tmov\ttmp1, #(DDR3PHY_PIR_INIT | DDR3PHY_PIR_DLLSRST | \\\n+\t\t\tDDR3PHY_PIR_DLLLOCK | DDR3PHY_PIR_ITMSRST)\n+\tstr\ttmp1, [r3, #DDR3PHY_PIR]\n+\n+sr_dis_4:\n+\t/* Wait for it. */\n+\tldr\ttmp1, [r3, #DDR3PHY_PGSR]\n+\ttst\ttmp1, #DDR3PHY_PGSR_IDONE\n+\tbeq\tsr_dis_4\n+\n+\t/* Enable quasi-dynamic programming. */\n+\tmov\ttmp1, #0\n+\tstr\ttmp1, [r2, #UDDRC_SWCTRL]\n+\n+\t/* Assert PHY init complete enable signal. */\n+\tldr\ttmp1, [r2, #UDDRC_DFIMISC]\n+\torr\ttmp1, tmp1, #UDDRC_DFIMISC_DFI_INIT_COMPLETE_EN\n+\tstr\ttmp1, [r2, #UDDRC_DFIMISC]\n+\n+\t/* Programming is done. Set sw_done. */\n+\tmov\ttmp1, #UDDRC_SWCTRL_SW_DONE\n+\tstr\ttmp1, [r2, #UDDRC_SWCTRL]\n+\n+sr_dis_5:\n+\t/* Wait for it. */\n+\tldr\ttmp1, [r2, #UDDRC_SWSTAT]\n+\ttst\ttmp1, #UDDRC_SWSTAT_SW_DONE_ACK\n+\tbeq\tsr_dis_5\n+\n+\t/* Trigger self-refresh exit. */\n+\tldr\ttmp1, [r2, #UDDRC_PWRCTL]\n+\tbic\ttmp1, tmp1, #UDDRC_PWRCTRL_SELFREF_SW\n+\tstr\ttmp1, [r2, #UDDRC_PWRCTL]\n+\n+sr_dis_6:\n+\t/* Wait for self-refresh exit done. */\n+\tldr\ttmp1, [r2, #UDDRC_STAT]\n+\tbic\ttmp1, tmp1, #~UDDRC_STAT_OPMODE_MSK\n+\tcmp\ttmp1, #UDDRC_STAT_OPMODE_NORMAL\n+\tbne\tsr_dis_6\n+\n+\t/* Enable all AXI ports. */\n+\tldr\ttmp1, [r2, #UDDRC_PCTRL_0]\n+\torr\ttmp1, tmp1, #0x1\n+\tstr\ttmp1, [r2, #UDDRC_PCTRL_0]\n+\n+\tldr\ttmp1, [r2, #UDDRC_PCTRL_1]\n+\torr\ttmp1, tmp1, #0x1\n+\tstr\ttmp1, [r2, #UDDRC_PCTRL_1]\n+\n+\tldr\ttmp1, [r2, #UDDRC_PCTRL_2]\n+\torr\ttmp1, tmp1, #0x1\n+\tstr\ttmp1, [r2, #UDDRC_PCTRL_2]\n+\n+\tldr\ttmp1, [r2, #UDDRC_PCTRL_3]\n+\torr\ttmp1, tmp1, #0x1\n+\tstr\ttmp1, [r2, #UDDRC_PCTRL_3]\n+\n+\tldr\ttmp1, [r2, #UDDRC_PCTRL_4]\n+\torr\ttmp1, tmp1, #0x1\n+\tstr\ttmp1, [r2, #UDDRC_PCTRL_4]\n+\n+\tdsb\n+.endm\n+#else\n /**\n  * Enable self-refresh\n  *\n@@ -228,6 +422,7 @@ sdramc_exit_sf:\n \n sr_dis_exit:\n .endm\n+#endif\n \n .macro at91_pm_ulp0_mode\n \tldr\tpmc, .pmc_base\n@@ -668,6 +863,8 @@ ENTRY(at91_pm_suspend_in_sram)\n \tstr\ttmp1, .sramc_base\n \tldr\ttmp1, [r0, #PM_DATA_RAMC1]\n \tstr\ttmp1, .sramc1_base\n+\tldr\ttmp1, [r0, #PM_DATA_RAMC_PHY]\n+\tstr\ttmp1, .sramc_phy_base\n \tldr\ttmp1, [r0, #PM_DATA_MEMCTRL]\n \tstr\ttmp1, .memtype\n \tldr\ttmp1, [r0, #PM_DATA_MODE]\n@@ -721,6 +918,8 @@ ENDPROC(at91_pm_suspend_in_sram)\n \t.word 0\n .sramc1_base:\n \t.word 0\n+.sramc_phy_base:\n+\t.word 0\n .shdwc:\n \t.word 0\n .sfrbu:\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/209-ARM-at91-pm-add-support-for-MCK1.4-save-restore-for-.patch",
    "content": "From 9ee7fd7aa956671727752dac6bd131cf511c1137 Mon Sep 17 00:00:00 2001\nFrom: Claudiu Beznea <claudiu.beznea@microchip.com>\nDate: Thu, 15 Apr 2021 13:49:59 +0300\nSubject: [PATCH 209/247] ARM: at91: pm: add support for MCK1..4 save/restore\n for ulp modes\n\nAdd support for MCK1..4 save restore for ULP modes.\n\nSigned-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>\nSigned-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>\nLink: https://lore.kernel.org/r/20210415105010.569620-14-claudiu.beznea@microchip.com\n---\n arch/arm/mach-at91/pm_suspend.S | 126 ++++++++++++++++++++++++++++++++\n 1 file changed, 126 insertions(+)\n\n--- a/arch/arm/mach-at91/pm_suspend.S\n+++ b/arch/arm/mach-at91/pm_suspend.S\n@@ -765,7 +765,122 @@ sr_dis_exit:\n 2:\n .endm\n \n+/**\n+ * at91_mckx_ps_enable:\tsave MCK1..4 settings and switch it to main clock\n+ *\n+ * Side effects: overwrites tmp1, tmp2\n+ */\n+.macro at91_mckx_ps_enable\n+#ifdef CONFIG_SOC_SAMA7\n+\tldr\tpmc, .pmc_base\n+\n+\t/* There are 4 MCKs we need to handle: MCK1..4 */\n+\tmov\ttmp1, #1\n+e_loop:\tcmp\ttmp1, #5\n+\tbeq\te_done\n+\n+\t/* Write MCK ID to retrieve the settings. */\n+\tstr\ttmp1, [pmc, #AT91_PMC_MCR_V2]\n+\tldr\ttmp2, [pmc, #AT91_PMC_MCR_V2]\n+\n+e_save_mck1:\n+\tcmp\ttmp1, #1\n+\tbne\te_save_mck2\n+\tstr\ttmp2, .saved_mck1\n+\tb\te_ps\n+\n+e_save_mck2:\n+\tcmp\ttmp1, #2\n+\tbne\te_save_mck3\n+\tstr\ttmp2, .saved_mck2\n+\tb\te_ps\n+\n+e_save_mck3:\n+\tcmp\ttmp1, #3\n+\tbne\te_save_mck4\n+\tstr\ttmp2, .saved_mck3\n+\tb\te_ps\n+\n+e_save_mck4:\n+\tstr\ttmp2, .saved_mck4\n+\n+e_ps:\n+\t/* Use CSS=MAINCK and DIV=1. */\n+\tbic\ttmp2, tmp2, #AT91_PMC_MCR_V2_CSS\n+\tbic\ttmp2, tmp2, #AT91_PMC_MCR_V2_DIV\n+\torr\ttmp2, tmp2, #AT91_PMC_MCR_V2_CSS_MAINCK\n+\torr\ttmp2, tmp2, #AT91_PMC_MCR_V2_DIV1\n+\tstr\ttmp2, [pmc, #AT91_PMC_MCR_V2]\n+\n+\twait_mckrdy tmp1\n+\n+\tadd\ttmp1, tmp1, #1\n+\tb\te_loop\n+\n+e_done:\n+#endif\n+.endm\n+\n+/**\n+ * at91_mckx_ps_restore: restore MCK1..4 settings\n+ *\n+ * Side effects: overwrites tmp1, tmp2\n+ */\n+.macro at91_mckx_ps_restore\n+#ifdef CONFIG_SOC_SAMA7\n+\tldr\tpmc, .pmc_base\n+\n+\t/* There are 4 MCKs we need to handle: MCK1..4 */\n+\tmov\ttmp1, #1\n+r_loop:\tcmp\ttmp1, #5\n+\tbeq\tr_done\n+\n+r_save_mck1:\n+\tcmp\ttmp1, #1\n+\tbne\tr_save_mck2\n+\tldr\ttmp2, .saved_mck1\n+\tb\tr_ps\n+\n+r_save_mck2:\n+\tcmp\ttmp1, #2\n+\tbne\tr_save_mck3\n+\tldr\ttmp2, .saved_mck2\n+\tb\tr_ps\n+\n+r_save_mck3:\n+\tcmp\ttmp1, #3\n+\tbne\tr_save_mck4\n+\tldr\ttmp2, .saved_mck3\n+\tb\tr_ps\n+\n+r_save_mck4:\n+\tldr\ttmp2, .saved_mck4\n+\n+r_ps:\n+\t/* Write MCK ID to retrieve the settings. */\n+\tstr\ttmp1, [pmc, #AT91_PMC_MCR_V2]\n+\tldr\ttmp3, [pmc, #AT91_PMC_MCR_V2]\n+\n+\t/* We need to restore CSS and DIV. */\n+\tbic\ttmp3, tmp3, #AT91_PMC_MCR_V2_CSS\n+\tbic\ttmp3, tmp3, #AT91_PMC_MCR_V2_DIV\n+\torr\ttmp3, tmp3, tmp2\n+\tbic\ttmp3, tmp3, #AT91_PMC_MCR_V2_ID_MSK\n+\torr\ttmp3, tmp3, tmp1\n+\torr\ttmp3, tmp3, #AT91_PMC_MCR_V2_CMD\n+\tstr\ttmp2, [pmc, #AT91_PMC_MCR_V2]\n+\n+\twait_mckrdy tmp1\n+\n+\tadd\ttmp1, tmp1, #1\n+\tb\tr_loop\n+r_done:\n+#endif\n+.endm\n+\n .macro at91_ulp_mode\n+\tat91_mckx_ps_enable\n+\n \tldr\tpmc, .pmc_base\n \tldr\ttmp2, .mckr_offset\n \tldr\ttmp3, .pm_mode\n@@ -817,6 +932,7 @@ ulp_exit:\n \tmov\ttmp3, #0\n \twait_mckrdy tmp3\n \n+\tat91_mckx_ps_restore\n .endm\n \n .macro at91_backup_mode\n@@ -946,6 +1062,16 @@ ENDPROC(at91_pm_suspend_in_sram)\n \t.word 0\n .saved_osc_status:\n \t.word 0\n+#ifdef CONFIG_SOC_SAMA7\n+.saved_mck1:\n+\t.word 0\n+.saved_mck2:\n+\t.word 0\n+.saved_mck3:\n+\t.word 0\n+.saved_mck4:\n+\t.word 0\n+#endif\n \n ENTRY(at91_pm_suspend_in_sram_sz)\n \t.word .-at91_pm_suspend_in_sram\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/210-ARM-at91-pm-add-support-for-2.5V-LDO-regulator-contr.patch",
    "content": "From b2073cc043612bf95b115bd94103cfb2936f05bf Mon Sep 17 00:00:00 2001\nFrom: Claudiu Beznea <claudiu.beznea@microchip.com>\nDate: Thu, 15 Apr 2021 13:50:00 +0300\nSubject: [PATCH 210/247] ARM: at91: pm: add support for 2.5V LDO regulator\n control\n\nAdd support to disable/enable 2.5V LDO regulator when entering/exiting\nany ULP mode.\n\nSigned-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>\nSigned-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>\nLink: https://lore.kernel.org/r/20210415105010.569620-15-claudiu.beznea@microchip.com\n---\n arch/arm/mach-at91/pm.h         |  1 +\n arch/arm/mach-at91/pm_suspend.S | 29 +++++++++++++++++++++++++++++\n 2 files changed, 30 insertions(+)\n\n--- a/arch/arm/mach-at91/pm.h\n+++ b/arch/arm/mach-at91/pm.h\n@@ -13,6 +13,7 @@\n #include <soc/at91/at91sam9_ddrsdr.h>\n #include <soc/at91/at91sam9_sdramc.h>\n #include <soc/at91/sama7-ddr.h>\n+#include <soc/at91/sama7-sfrbu.h>\n \n #define AT91_MEMCTRL_MC\t\t0\n #define AT91_MEMCTRL_SDRAMC\t1\n--- a/arch/arm/mach-at91/pm_suspend.S\n+++ b/arch/arm/mach-at91/pm_suspend.S\n@@ -83,6 +83,29 @@ tmp3\t.req\tr6\n \n \t.endm\n \n+/**\n+ * Set state for 2.5V low power regulator\n+ * @ena: 0 - disable regulator\n+ *\t 1 - enable regulator\n+ *\n+ * Side effects: overwrites r7, r8, r9, r10\n+ */\n+\t.macro at91_2_5V_reg_set_low_power ena\n+#ifdef CONFIG_SOC_SAMA7\n+\tldr\tr7, .sfrbu\n+\tmov\tr8, #\\ena\n+\tldr\tr9, [r7, #AT91_SFRBU_25LDOCR]\n+\torr\tr9, r9, #AT91_SFRBU_25LDOCR_LP\n+\tcmp\tr8, #1\n+\tbeq\tlp_done_\\ena\n+\tbic\tr9, r9, #AT91_SFRBU_25LDOCR_LP\n+lp_done_\\ena:\n+\tldr\tr10, =AT91_SFRBU_25LDOCR_LDOANAKEY\n+\torr\tr9, r9, r10\n+\tstr\tr9, [r7, #AT91_SFRBU_25LDOCR]\n+#endif\n+\t.endm\n+\n \t.text\n \n \t.arm\n@@ -906,6 +929,9 @@ save_mck:\n \n \tat91_plla_disable\n \n+\t/* Enable low power mode for 2.5V regulator. */\n+\tat91_2_5V_reg_set_low_power 1\n+\n \tldr\ttmp3, .pm_mode\n \tcmp\ttmp3, #AT91_PM_ULP1\n \tbeq\tulp1_mode\n@@ -918,6 +944,9 @@ ulp1_mode:\n \tb\tulp_exit\n \n ulp_exit:\n+\t/* Disable low power mode for 2.5V regulator. */\n+\tat91_2_5V_reg_set_low_power 0\n+\n \tldr\tpmc, .pmc_base\n \n \tat91_plla_enable\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/211-ARM-at91-pm-wait-for-ddr-power-mode-off.patch",
    "content": "From 2b522a22243938dd7613e09c954172b1fa6217f5 Mon Sep 17 00:00:00 2001\nFrom: Claudiu Beznea <claudiu.beznea@microchip.com>\nDate: Thu, 15 Apr 2021 13:50:01 +0300\nSubject: [PATCH 211/247] ARM: at91: pm: wait for ddr power mode off\n\nWait for DDR power mode off before shutting down the core.\n\nSigned-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>\nSigned-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>\nLink: https://lore.kernel.org/r/20210415105010.569620-16-claudiu.beznea@microchip.com\n---\n arch/arm/mach-at91/pm_suspend.S | 5 +++++\n 1 file changed, 5 insertions(+)\n\n--- a/arch/arm/mach-at91/pm_suspend.S\n+++ b/arch/arm/mach-at91/pm_suspend.S\n@@ -980,6 +980,11 @@ ulp_exit:\n \tmov\ttmp1, #0x1\n \tstr\ttmp1, [r0, #0x10]\n \n+\t/* Wait for it. */\n+1:\tldr\ttmp1, [r0, #0x10]\n+\ttst\ttmp1, #0x1\n+\tbeq\t1b\n+\n \t/* Shutdown */\n \tldr\tr0, .shdwc\n \tmov\ttmp1, #0xA5000000\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/212-ARM-at91-pm-add-sama7g5-ddr-controller.patch",
    "content": "From 3f55310c00b8c478da1458704027036c1a414973 Mon Sep 17 00:00:00 2001\nFrom: Claudiu Beznea <claudiu.beznea@microchip.com>\nDate: Thu, 15 Apr 2021 13:50:03 +0300\nSubject: [PATCH 212/247] ARM: at91: pm: add sama7g5 ddr controller\n\nAdd SAMA7G5 DDR controller to the list of DDR controller compatibles.\nAt the moment there is no standby support. Adapt the code for this.\n\nSigned-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>\nSigned-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>\nLink: https://lore.kernel.org/r/20210415105010.569620-18-claudiu.beznea@microchip.com\n---\n arch/arm/mach-at91/pm.c | 9 ++++++---\n 1 file changed, 6 insertions(+), 3 deletions(-)\n\n--- a/arch/arm/mach-at91/pm.c\n+++ b/arch/arm/mach-at91/pm.c\n@@ -548,6 +548,7 @@ static const struct of_device_id ramc_id\n \t{ .compatible = \"atmel,at91sam9260-sdramc\", .data = &ramc_infos[1] },\n \t{ .compatible = \"atmel,at91sam9g45-ddramc\", .data = &ramc_infos[2] },\n \t{ .compatible = \"atmel,sama5d3-ddramc\", .data = &ramc_infos[3] },\n+\t{ .compatible = \"microchip,sama7g5-uddrc\", },\n \t{ /*sentinel*/ }\n };\n \n@@ -569,9 +570,11 @@ static __init int at91_dt_ramc(void)\n \t\t}\n \n \t\tramc = of_id->data;\n-\t\tif (!standby)\n-\t\t\tstandby = ramc->idle;\n-\t\tsoc_pm.data.memctrl = ramc->memctrl;\n+\t\tif (ramc) {\n+\t\t\tif (!standby)\n+\t\t\t\tstandby = ramc->idle;\n+\t\t\tsoc_pm.data.memctrl = ramc->memctrl;\n+\t\t}\n \n \t\tidx++;\n \t}\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/213-ARM-at91-pm-add-sama7g5-ddr-phy-controller.patch",
    "content": "From bbbbf16c44f34a2d563fa7d71de64ffe3b4b82dc Mon Sep 17 00:00:00 2001\nFrom: Claudiu Beznea <claudiu.beznea@microchip.com>\nDate: Thu, 15 Apr 2021 13:50:04 +0300\nSubject: [PATCH 213/247] ARM: at91: pm: add sama7g5 ddr phy controller\n\nSAMA7G5 self-refresh procedure accesses also the DDR PHY registers.\nAdapt the code so that the at91_dt_ramc() to look also for DDR PHYs,\nin case it is mandatory.\n\nSigned-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>\nSigned-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>\nLink: https://lore.kernel.org/r/20210415105010.569620-19-claudiu.beznea@microchip.com\n---\n arch/arm/mach-at91/pm.c | 27 +++++++++++++++++++++------\n 1 file changed, 21 insertions(+), 6 deletions(-)\n\n--- a/arch/arm/mach-at91/pm.c\n+++ b/arch/arm/mach-at91/pm.c\n@@ -552,7 +552,12 @@ static const struct of_device_id ramc_id\n \t{ /*sentinel*/ }\n };\n \n-static __init int at91_dt_ramc(void)\n+static const struct of_device_id ramc_phy_ids[] __initconst = {\n+\t{ .compatible = \"microchip,sama7g5-ddr3phy\", },\n+\t{ /* Sentinel. */ },\n+};\n+\n+static __init void at91_dt_ramc(bool phy_mandatory)\n {\n \tstruct device_node *np;\n \tconst struct of_device_id *of_id;\n@@ -585,6 +590,16 @@ static __init int at91_dt_ramc(void)\n \t\tgoto unmap_ramc;\n \t}\n \n+\t/* Lookup for DDR PHY node, if any. */\n+\tfor_each_matching_node_and_match(np, ramc_phy_ids, &of_id) {\n+\t\tsoc_pm.data.ramc_phy = of_iomap(np, 0);\n+\t\tif (!soc_pm.data.ramc_phy)\n+\t\t\tpanic(pr_fmt(\"unable to map ramc phy cpu registers\\n\"));\n+\t}\n+\n+\tif (phy_mandatory && !soc_pm.data.ramc_phy)\n+\t\tpanic(pr_fmt(\"DDR PHY is mandatory!\\n\"));\n+\n \tif (!standby) {\n \t\tpr_warn(\"ramc no standby function available\\n\");\n \t\treturn 0;\n@@ -953,7 +968,7 @@ void __init at91rm9200_pm_init(void)\n \tsoc_pm.data.standby_mode = AT91_PM_STANDBY;\n \tsoc_pm.data.suspend_mode = AT91_PM_ULP0;\n \n-\tret = at91_dt_ramc();\n+\tret = at91_dt_ramc(false);\n \tif (ret)\n \t\treturn;\n \n@@ -980,7 +995,7 @@ void __init sam9x60_pm_init(void)\n \n \tat91_pm_modes_validate(modes, ARRAY_SIZE(modes));\n \tat91_pm_modes_init(iomaps, ARRAY_SIZE(iomaps));\n-\tret = at91_dt_ramc();\n+\tret = at91_dt_ramc(false);\n \tif (ret)\n \t\treturn;\n \n@@ -1005,7 +1020,7 @@ void __init at91sam9_pm_init(void)\n \tsoc_pm.data.standby_mode = AT91_PM_STANDBY;\n \tsoc_pm.data.suspend_mode = AT91_PM_ULP0;\n \n-\tret = at91_dt_ramc();\n+\tret = at91_dt_ramc(false);\n \tif (ret)\n \t\treturn;\n \n@@ -1023,7 +1038,7 @@ void __init sama5_pm_init(void)\n \t\treturn;\n \n \tat91_pm_modes_validate(modes, ARRAY_SIZE(modes));\n-\tret = at91_dt_ramc();\n+\tret = at91_dt_ramc(false);\n \tif (ret)\n \t\treturn;\n \n@@ -1048,7 +1063,7 @@ void __init sama5d2_pm_init(void)\n \n \tat91_pm_modes_validate(modes, ARRAY_SIZE(modes));\n \tat91_pm_modes_init(iomaps, ARRAY_SIZE(iomaps));\n-\tret = at91_dt_ramc();\n+\tret = at91_dt_ramc(false);\n \tif (ret)\n \t\treturn;\n \n"
  },
  {
    "path": "target/linux/at91/patches-5.10/214-ARM-at91-pm-save-ddr-phy-calibration-data-to-securam.patch",
    "content": "From b355bb98eae3e343969fc5a0203e0dab472a6acd Mon Sep 17 00:00:00 2001\nFrom: Claudiu Beznea <claudiu.beznea@microchip.com>\nDate: Thu, 15 Apr 2021 13:50:05 +0300\nSubject: [PATCH 214/247] ARM: at91: pm: save ddr phy calibration data to\n securam\n\nThe resuming from backup mode is done with the help of bootloader.\nThe bootloader reconfigure the DDR controller and DDR PHY controller.\nTo speed-up the resuming process save the PHY calibration data into\nSECURAM before suspending (securam is powered on backup mode).\nThis data will be later used by bootloader in DDR PHY reconfiguration\nprocess. Also, in the process or recalibration the first 8 words of\nthe memory may get corrupted. To solve this, these 8 words are saved\nin the securam and restored by bootloader in the process of PHY\nconfiguration.\n\nSigned-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>\nSigned-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>\nLink: https://lore.kernel.org/r/20210415105010.569620-20-claudiu.beznea@microchip.com\n---\n arch/arm/mach-at91/pm.c | 60 ++++++++++++++++++++++++++++++++++++++++-\n 1 file changed, 59 insertions(+), 1 deletion(-)\n\n--- a/arch/arm/mach-at91/pm.c\n+++ b/arch/arm/mach-at91/pm.c\n@@ -10,6 +10,7 @@\n #include <linux/io.h>\n #include <linux/of_address.h>\n #include <linux/of.h>\n+#include <linux/of_fdt.h>\n #include <linux/of_platform.h>\n #include <linux/parser.h>\n #include <linux/suspend.h>\n@@ -27,18 +28,23 @@\n #include \"generic.h\"\n #include \"pm.h\"\n \n+#define BACKUP_DDR_PHY_CALIBRATION\t(9)\n+\n /**\n  * struct at91_pm_bu - AT91 power management backup unit data structure\n  * @suspended: true if suspended to backup mode\n  * @reserved: reserved\n  * @canary: canary data for memory checking after exit from backup mode\n  * @resume: resume API\n+ * @ddr_phy_calibration: DDR PHY calibration data: ZQ0CR0, first 8 words\n+ * of the memory\n  */\n struct at91_pm_bu {\n \tint suspended;\n \tunsigned long reserved;\n \tphys_addr_t canary;\n \tphys_addr_t resume;\n+\tunsigned long ddr_phy_calibration[BACKUP_DDR_PHY_CALIBRATION];\n };\n \n /**\n@@ -48,6 +54,7 @@ struct at91_pm_bu {\n  * @ws_ids: wakup sources of_device_id array\n  * @data: PM data to be used on last phase of suspend\n  * @bu: backup unit mapped data (for backup mode)\n+ * @memcs: memory chip select\n  */\n struct at91_soc_pm {\n \tint (*config_shdwc_ws)(void __iomem *shdwc, u32 *mode, u32 *polarity);\n@@ -55,6 +62,7 @@ struct at91_soc_pm {\n \tconst struct of_device_id *ws_ids;\n \tstruct at91_pm_bu *bu;\n \tstruct at91_pm_data data;\n+\tvoid *memcs;\n };\n \n /**\n@@ -316,6 +324,19 @@ extern u32 at91_pm_suspend_in_sram_sz;\n \n static int at91_suspend_finish(unsigned long val)\n {\n+\tint i;\n+\n+\tif (soc_pm.data.mode == AT91_PM_BACKUP && soc_pm.data.ramc_phy) {\n+\t\t/*\n+\t\t * The 1st 8 words of memory might get corrupted in the process\n+\t\t * of DDR PHY recalibration; it is saved here in securam and it\n+\t\t * will be restored later, after recalibration, by bootloader\n+\t\t */\n+\t\tfor (i = 1; i < BACKUP_DDR_PHY_CALIBRATION; i++)\n+\t\t\tsoc_pm.bu->ddr_phy_calibration[i] =\n+\t\t\t\t*((unsigned int *)soc_pm.memcs + (i - 1));\n+\t}\n+\n \tflush_cache_all();\n \touter_disable();\n \n@@ -688,12 +709,40 @@ static bool __init at91_is_pm_mode_activ\n \t\tsoc_pm.data.suspend_mode == pm_mode);\n }\n \n+static int __init at91_pm_backup_scan_memcs(unsigned long node,\n+\t\t\t\t\t    const char *uname, int depth,\n+\t\t\t\t\t    void *data)\n+{\n+\tconst char *type;\n+\tconst __be32 *reg;\n+\tint *located = data;\n+\tint size;\n+\n+\t/* Memory node already located. */\n+\tif (*located)\n+\t\treturn 0;\n+\n+\ttype = of_get_flat_dt_prop(node, \"device_type\", NULL);\n+\n+\t/* We are scanning \"memory\" nodes only. */\n+\tif (!type || strcmp(type, \"memory\"))\n+\t\treturn 0;\n+\n+\treg = of_get_flat_dt_prop(node, \"reg\", &size);\n+\tif (reg) {\n+\t\tsoc_pm.memcs = __va((phys_addr_t)be32_to_cpu(*reg));\n+\t\t*located = 1;\n+\t}\n+\n+\treturn 0;\n+}\n+\n static int __init at91_pm_backup_init(void)\n {\n \tstruct gen_pool *sram_pool;\n \tstruct device_node *np;\n \tstruct platform_device *pdev;\n-\tint ret = -ENODEV;\n+\tint ret = -ENODEV, located = 0;\n \n \tif (!IS_ENABLED(CONFIG_SOC_SAMA5D2))\n \t\treturn -EPERM;\n@@ -728,6 +777,15 @@ static int __init at91_pm_backup_init(vo\n \tsoc_pm.bu->suspended = 0;\n \tsoc_pm.bu->canary = __pa_symbol(&canary);\n \tsoc_pm.bu->resume = __pa_symbol(cpu_resume);\n+\tif (soc_pm.data.ramc_phy) {\n+\t\tof_scan_flat_dt(at91_pm_backup_scan_memcs, &located);\n+\t\tif (!located)\n+\t\t\tgoto securam_fail;\n+\n+\t\t/* DDR3PHY_ZQ0SR0 */\n+\t\tsoc_pm.bu->ddr_phy_calibration[0] = readl(soc_pm.data.ramc_phy +\n+\t\t\t\t\t\t\t  0x188);\n+\t}\n \n \treturn 0;\n \n"
  },
  {
    "path": "target/linux/at91/patches-5.10/215-ARM-at91-pm-add-backup-mode-support-for-SAMA7G5.patch",
    "content": "From 62be32b56ff31b2cd048a53fac40a165c5bc66cd Mon Sep 17 00:00:00 2001\nFrom: Claudiu Beznea <claudiu.beznea@microchip.com>\nDate: Thu, 15 Apr 2021 13:50:06 +0300\nSubject: [PATCH 215/247] ARM: at91: pm: add backup mode support for SAMA7G5\n\nAdapt at91_pm_backup_init() to work for SAMA7G5. Also, set the LPM pin\nto shutdown controller. This will signal to PMIC that it needs to switch\nto the state corresponding to backup mode.\n\nSigned-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>\nSigned-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>\nLink: https://lore.kernel.org/r/20210415105010.569620-21-claudiu.beznea@microchip.com\n---\n arch/arm/mach-at91/pm.c         | 3 ++-\n arch/arm/mach-at91/pm_suspend.S | 7 +++++++\n 2 files changed, 9 insertions(+), 1 deletion(-)\n\n--- a/arch/arm/mach-at91/pm.c\n+++ b/arch/arm/mach-at91/pm.c\n@@ -744,7 +744,8 @@ static int __init at91_pm_backup_init(vo\n \tstruct platform_device *pdev;\n \tint ret = -ENODEV, located = 0;\n \n-\tif (!IS_ENABLED(CONFIG_SOC_SAMA5D2))\n+\tif (!IS_ENABLED(CONFIG_SOC_SAMA5D2) &&\n+\t    !IS_ENABLED(CONFIG_SOC_SAMA7G5))\n \t\treturn -EPERM;\n \n \tif (!at91_is_pm_mode_active(AT91_PM_BACKUP))\n--- a/arch/arm/mach-at91/pm_suspend.S\n+++ b/arch/arm/mach-at91/pm_suspend.S\n@@ -106,6 +106,12 @@ lp_done_\\ena:\n #endif\n \t.endm\n \n+\t.macro at91_backup_set_lpm reg\n+#ifdef CONFIG_SOC_SAMA7\n+\torr\t\\reg, \\reg, #0x200000\n+#endif\n+\t.endm\n+\n \t.text\n \n \t.arm\n@@ -989,6 +995,7 @@ ulp_exit:\n \tldr\tr0, .shdwc\n \tmov\ttmp1, #0xA5000000\n \tadd\ttmp1, tmp1, #0x1\n+\tat91_backup_set_lpm tmp1\n \tstr\ttmp1, [r0, #0]\n .endm\n \n"
  },
  {
    "path": "target/linux/at91/patches-5.10/216-ARM-at91-pm-add-sama7g5-s-pmc.patch",
    "content": "From e9855ac00e8d9a2c41cea42b4f38a2b0b010bef3 Mon Sep 17 00:00:00 2001\nFrom: Claudiu Beznea <claudiu.beznea@microchip.com>\nDate: Thu, 15 Apr 2021 13:50:07 +0300\nSubject: [PATCH 216/247] ARM: at91: pm: add sama7g5's pmc\n\nAdd SAMA7G5's PMC to compatible list.\n\nSigned-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>\nSigned-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>\nLink: https://lore.kernel.org/r/20210415105010.569620-22-claudiu.beznea@microchip.com\n---\n arch/arm/mach-at91/pm.c | 6 ++++++\n 1 file changed, 6 insertions(+)\n\n--- a/arch/arm/mach-at91/pm.c\n+++ b/arch/arm/mach-at91/pm.c\n@@ -912,6 +912,11 @@ static const struct pmc_info pmc_infos[]\n \t\t.mckr = 0x28,\n \t\t.version = AT91_PMC_V2,\n \t},\n+\t{\n+\t\t.mckr = 0x28,\n+\t\t.version = AT91_PMC_V2,\n+\t},\n+\n };\n \n static const struct of_device_id atmel_pmc_ids[] __initconst = {\n@@ -927,6 +932,7 @@ static const struct of_device_id atmel_p\n \t{ .compatible = \"atmel,sama5d4-pmc\", .data = &pmc_infos[1] },\n \t{ .compatible = \"atmel,sama5d2-pmc\", .data = &pmc_infos[1] },\n \t{ .compatible = \"microchip,sam9x60-pmc\", .data = &pmc_infos[4] },\n+\t{ .compatible = \"microchip,sama7g5-pmc\", .data = &pmc_infos[5] },\n \t{ /* sentinel */ },\n };\n \n"
  },
  {
    "path": "target/linux/at91/patches-5.10/217-ARM-at91-sama7-introduce-sama7-SoC-family.patch",
    "content": "From dea645bce478cc72a2bf2413ec873927d1471442 Mon Sep 17 00:00:00 2001\nFrom: Eugen Hristev <eugen.hristev@microchip.com>\nDate: Thu, 15 Apr 2021 13:50:08 +0300\nSubject: [PATCH 217/247] ARM: at91: sama7: introduce sama7 SoC family\n\nIntroduce new family of SoCs, sama7, and first SoC, sama7g5.\n\nSigned-off-by: Eugen Hristev <eugen.hristev@microchip.com>\n[claudiu.beznea@microchip.com: keep only the sama7_dt]\nSigned-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>\nSigned-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>\nLink: https://lore.kernel.org/r/20210415105010.569620-23-claudiu.beznea@microchip.com\n---\n arch/arm/mach-at91/Makefile |  1 +\n arch/arm/mach-at91/sama7.c  | 32 ++++++++++++++++++++++++++++++++\n 2 files changed, 33 insertions(+)\n create mode 100644 arch/arm/mach-at91/sama7.c\n\n--- a/arch/arm/mach-at91/Makefile\n+++ b/arch/arm/mach-at91/Makefile\n@@ -8,6 +8,7 @@ obj-$(CONFIG_SOC_AT91RM9200)\t+= at91rm92\n obj-$(CONFIG_SOC_AT91SAM9)\t+= at91sam9.o\n obj-$(CONFIG_SOC_SAM9X60)\t+= sam9x60.o\n obj-$(CONFIG_SOC_SAMA5)\t\t+= sama5.o\n+obj-$(CONFIG_SOC_SAMA7)\t\t+= sama7.o\n obj-$(CONFIG_SOC_SAMV7)\t\t+= samv7.o\n \n # Power Management\n--- /dev/null\n+++ b/arch/arm/mach-at91/sama7.c\n@@ -0,0 +1,32 @@\n+// SPDX-License-Identifier: GPL-2.0-or-later\n+/*\n+ * Setup code for SAMA7\n+ *\n+ * Copyright (C) 2021 Microchip Technology, Inc. and its subsidiaries\n+ *\n+ */\n+\n+#include <linux/of.h>\n+#include <linux/of_platform.h>\n+\n+#include <asm/mach/arch.h>\n+#include <asm/system_misc.h>\n+\n+#include \"generic.h\"\n+\n+static void __init sama7_dt_device_init(void)\n+{\n+\tof_platform_default_populate(NULL, NULL, NULL);\n+}\n+\n+static const char *const sama7_dt_board_compat[] __initconst = {\n+\t\"microchip,sama7\",\n+\tNULL\n+};\n+\n+DT_MACHINE_START(sama7_dt, \"Microchip SAMA7\")\n+\t/* Maintainer: Microchip */\n+\t.init_machine\t= sama7_dt_device_init,\n+\t.dt_compat\t= sama7_dt_board_compat,\n+MACHINE_END\n+\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/218-ARM-at91-pm-add-pm-support-for-SAMA7G5.patch",
    "content": "From aba3984dc7a405d20b83bff603d23719d0e26bc7 Mon Sep 17 00:00:00 2001\nFrom: Claudiu Beznea <claudiu.beznea@microchip.com>\nDate: Thu, 15 Apr 2021 13:50:09 +0300\nSubject: [PATCH 218/247] ARM: at91: pm: add pm support for SAMA7G5\n\nAdd support for SAMA7G5 power management modes: standby, ulp0, ulp1, backup.\n\nSigned-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>\nSigned-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>\nLink: https://lore.kernel.org/r/20210415105010.569620-24-claudiu.beznea@microchip.com\n---\n arch/arm/mach-at91/generic.h |  2 ++\n arch/arm/mach-at91/pm.c      | 37 ++++++++++++++++++++++++++++++++++++\n arch/arm/mach-at91/sama7.c   |  1 +\n 3 files changed, 40 insertions(+)\n\n--- a/arch/arm/mach-at91/generic.h\n+++ b/arch/arm/mach-at91/generic.h\n@@ -14,12 +14,14 @@ extern void __init at91sam9_pm_init(void\n extern void __init sam9x60_pm_init(void);\n extern void __init sama5_pm_init(void);\n extern void __init sama5d2_pm_init(void);\n+extern void __init sama7_pm_init(void);\n #else\n static inline void __init at91rm9200_pm_init(void) { }\n static inline void __init at91sam9_pm_init(void) { }\n static inline void __init sam9x60_pm_init(void) { }\n static inline void __init sama5_pm_init(void) { }\n static inline void __init sama5d2_pm_init(void) { }\n+static inline void __init sama7_pm_init(void) { }\n #endif\n \n #endif /* _AT91_GENERIC_H */\n--- a/arch/arm/mach-at91/pm.c\n+++ b/arch/arm/mach-at91/pm.c\n@@ -152,6 +152,17 @@ static const struct of_device_id sam9x60\n \t{ /* sentinel */ }\n };\n \n+static const struct of_device_id sama7g5_ws_ids[] = {\n+\t{ .compatible = \"atmel,at91sam9x5-rtc\",\t\t.data = &ws_info[1] },\n+\t{ .compatible = \"microchip,sama7g5-ohci\",\t.data = &ws_info[2] },\n+\t{ .compatible = \"usb-ohci\",\t\t\t.data = &ws_info[2] },\n+\t{ .compatible = \"atmel,at91sam9g45-ehci\",\t.data = &ws_info[2] },\n+\t{ .compatible = \"usb-ehci\",\t\t\t.data = &ws_info[2] },\n+\t{ .compatible = \"microchip,sama7g5-sdhci\",\t.data = &ws_info[3] },\n+\t{ .compatible = \"atmel,at91sam9260-rtt\",\t.data = &ws_info[4] },\n+\t{ /* sentinel */ }\n+};\n+\n static int at91_pm_config_ws(unsigned int pm_mode, bool set)\n {\n \tconst struct wakeup_source_info *wsi;\n@@ -1139,6 +1150,32 @@ void __init sama5d2_pm_init(void)\n \tsoc_pm.config_pmc_ws = at91_sama5d2_config_pmc_ws;\n }\n \n+void __init sama7_pm_init(void)\n+{\n+\tstatic const int modes[] __initconst = {\n+\t\tAT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP1, AT91_PM_BACKUP,\n+\t};\n+\tstatic const u32 iomaps[] __initconst = {\n+\t\t[AT91_PM_ULP0]\t\t= AT91_PM_IOMAP(SFRBU),\n+\t\t[AT91_PM_ULP1]\t\t= AT91_PM_IOMAP(SFRBU) |\n+\t\t\t\t\t  AT91_PM_IOMAP(SHDWC),\n+\t\t[AT91_PM_BACKUP]\t= AT91_PM_IOMAP(SFRBU) |\n+\t\t\t\t\t  AT91_PM_IOMAP(SHDWC),\n+\t};\n+\n+\tif (!IS_ENABLED(CONFIG_SOC_SAMA7))\n+\t\treturn;\n+\n+\tat91_pm_modes_validate(modes, ARRAY_SIZE(modes));\n+\n+\tat91_dt_ramc(true);\n+\tat91_pm_modes_init(iomaps, ARRAY_SIZE(iomaps));\n+\tat91_pm_init(NULL);\n+\n+\tsoc_pm.ws_ids = sama7g5_ws_ids;\n+\tsoc_pm.config_pmc_ws = at91_sam9x60_config_pmc_ws;\n+}\n+\n static int __init at91_pm_modes_select(char *str)\n {\n \tchar *s;\n--- a/arch/arm/mach-at91/sama7.c\n+++ b/arch/arm/mach-at91/sama7.c\n@@ -17,6 +17,7 @@\n static void __init sama7_dt_device_init(void)\n {\n \tof_platform_default_populate(NULL, NULL, NULL);\n+\tsama7_pm_init();\n }\n \n static const char *const sama7_dt_board_compat[] __initconst = {\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/219-ARM-at91-pm-add-sama7g5-shdwc.patch",
    "content": "From 84ff37cc98e6aaefe27d6edd5e3ced2be99d9833 Mon Sep 17 00:00:00 2001\nFrom: Claudiu Beznea <claudiu.beznea@microchip.com>\nDate: Thu, 15 Apr 2021 13:50:10 +0300\nSubject: [PATCH 219/247] ARM: at91: pm: add sama7g5 shdwc\n\nAdd SAMA7G5 SHDWC.\n\nSigned-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>\nSigned-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>\nLink: https://lore.kernel.org/r/20210415105010.569620-25-claudiu.beznea@microchip.com\n---\n arch/arm/mach-at91/pm.c | 1 +\n 1 file changed, 1 insertion(+)\n\n--- a/arch/arm/mach-at91/pm.c\n+++ b/arch/arm/mach-at91/pm.c\n@@ -809,6 +809,7 @@ securam_fail:\n static const struct of_device_id atmel_shdwc_ids[] = {\n \t{ .compatible = \"atmel,sama5d2-shdwc\" },\n \t{ .compatible = \"microchip,sam9x60-shdwc\" },\n+\t{ .compatible = \"microchip,sama7g5-shdwc\" },\n \t{ /* sentinel. */ }\n };\n \n"
  },
  {
    "path": "target/linux/at91/patches-5.10/220-ARM-configs-at91-add-defconfig-for-sama7-family-of-S.patch",
    "content": "From 2223a85aed2d892bd7c13053f27e777c743e5332 Mon Sep 17 00:00:00 2001\nFrom: Eugen Hristev <eugen.hristev@microchip.com>\nDate: Mon, 28 Jun 2021 15:04:51 +0300\nSubject: [PATCH 220/247] ARM: configs: at91: add defconfig for sama7 family of\n SoCs\n\nAdd defconfig for sama7 SoC family.\n\nSigned-off-by: Eugen Hristev <eugen.hristev@microchip.com>\n[claudiu.beznea@microchip.com: add clocks, ethernet, timers, power]\nSigned-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>\n[codrin.ciubotariu@microchip.com: add audio]\nSigned-off-by: Codrin Ciubotariu <codrin.ciubotariu@microchip.com>\n[nicolas.ferre@microchip.com: atags not set, mtd tests, spi gpio]\nSigned-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>\nLink: https://lore.kernel.org/r/20210628120452.74408-3-eugen.hristev@microchip.com\n---\n arch/arm/configs/sama7_defconfig | 209 +++++++++++++++++++++++++++++++\n 1 file changed, 209 insertions(+)\n create mode 100644 arch/arm/configs/sama7_defconfig\n\n--- /dev/null\n+++ b/arch/arm/configs/sama7_defconfig\n@@ -0,0 +1,209 @@\n+# CONFIG_LOCALVERSION_AUTO is not set\n+# CONFIG_SWAP is not set\n+CONFIG_SYSVIPC=y\n+CONFIG_NO_HZ_IDLE=y\n+CONFIG_HIGH_RES_TIMERS=y\n+CONFIG_LOG_BUF_SHIFT=16\n+CONFIG_CGROUPS=y\n+CONFIG_CGROUP_DEBUG=y\n+CONFIG_NAMESPACES=y\n+CONFIG_SYSFS_DEPRECATED=y\n+CONFIG_SYSFS_DEPRECATED_V2=y\n+CONFIG_BLK_DEV_INITRD=y\n+# CONFIG_FHANDLE is not set\n+# CONFIG_IO_URING is not set\n+CONFIG_KALLSYMS_ALL=y\n+CONFIG_EMBEDDED=y\n+# CONFIG_VM_EVENT_COUNTERS is not set\n+CONFIG_SLAB=y\n+CONFIG_ARCH_AT91=y\n+CONFIG_SOC_SAMA7G5=y\n+CONFIG_ATMEL_CLOCKSOURCE_TCB=y\n+# CONFIG_CACHE_L2X0 is not set\n+# CONFIG_ARM_PATCH_IDIV is not set\n+# CONFIG_CPU_SW_DOMAIN_PAN is not set\n+CONFIG_FORCE_MAX_ZONEORDER=15\n+CONFIG_UACCESS_WITH_MEMCPY=y\n+# CONFIG_ATAGS is not set\n+CONFIG_CMDLINE=\"console=ttyS0,115200 earlyprintk ignore_loglevel\"\n+CONFIG_VFP=y\n+CONFIG_NEON=y\n+CONFIG_KERNEL_MODE_NEON=y\n+CONFIG_MODULES=y\n+CONFIG_MODULE_FORCE_LOAD=y\n+CONFIG_MODULE_UNLOAD=y\n+CONFIG_MODULE_FORCE_UNLOAD=y\n+# CONFIG_BLK_DEV_BSG is not set\n+CONFIG_PARTITION_ADVANCED=y\n+# CONFIG_EFI_PARTITION is not set\n+# CONFIG_COREDUMP is not set\n+# CONFIG_COMPACTION is not set\n+CONFIG_CMA=y\n+CONFIG_NET=y\n+CONFIG_PACKET=y\n+CONFIG_UNIX=y\n+CONFIG_INET=y\n+CONFIG_IP_MULTICAST=y\n+CONFIG_IP_PNP=y\n+CONFIG_IP_PNP_DHCP=y\n+# CONFIG_INET_DIAG is not set\n+CONFIG_IPV6_SIT_6RD=y\n+CONFIG_BRIDGE=m\n+CONFIG_BRIDGE_VLAN_FILTERING=y\n+CONFIG_NET_DSA=m\n+CONFIG_VLAN_8021Q=m\n+CONFIG_CAN=y\n+CONFIG_CAN_M_CAN=y\n+CONFIG_CAN_M_CAN_PLATFORM=y\n+CONFIG_BT=y\n+CONFIG_BT_RFCOMM=y\n+CONFIG_BT_RFCOMM_TTY=y\n+CONFIG_BT_BNEP=y\n+CONFIG_BT_BNEP_MC_FILTER=y\n+CONFIG_BT_BNEP_PROTO_FILTER=y\n+CONFIG_BT_HIDP=y\n+CONFIG_BT_HCIBTUSB=y\n+CONFIG_BT_HCIUART=y\n+CONFIG_BT_HCIUART_H4=y\n+CONFIG_BT_HCIVHCI=y\n+CONFIG_CFG80211=m\n+# CONFIG_CFG80211_DEFAULT_PS is not set\n+CONFIG_CFG80211_DEBUGFS=y\n+CONFIG_CFG80211_WEXT=y\n+CONFIG_MAC80211=m\n+CONFIG_MAC80211_LEDS=y\n+CONFIG_RFKILL=y\n+CONFIG_RFKILL_INPUT=y\n+CONFIG_PCCARD=y\n+CONFIG_DEVTMPFS=y\n+CONFIG_DEVTMPFS_MOUNT=y\n+# CONFIG_STANDALONE is not set\n+# CONFIG_PREVENT_FIRMWARE_BUILD is not set\n+# CONFIG_ALLOW_DEV_COREDUMP is not set\n+CONFIG_MTD=y\n+CONFIG_MTD_TESTS=m\n+CONFIG_MTD_CMDLINE_PARTS=y\n+CONFIG_BLK_DEV_LOOP=y\n+CONFIG_BLK_DEV_RAM=y\n+CONFIG_BLK_DEV_RAM_COUNT=1\n+CONFIG_BLK_DEV_RAM_SIZE=8192\n+CONFIG_EEPROM_AT24=y\n+CONFIG_SCSI=y\n+CONFIG_BLK_DEV_SD=y\n+CONFIG_NETDEVICES=y\n+CONFIG_MACB=y\n+CONFIG_MICREL_PHY=y\n+CONFIG_INPUT_EVDEV=y\n+CONFIG_KEYBOARD_GPIO=y\n+# CONFIG_INPUT_MOUSE is not set\n+CONFIG_LEGACY_PTY_COUNT=4\n+CONFIG_SERIAL_ATMEL=y\n+CONFIG_SERIAL_ATMEL_CONSOLE=y\n+CONFIG_HW_RANDOM=y\n+CONFIG_I2C=y\n+CONFIG_I2C_CHARDEV=y\n+CONFIG_I2C_AT91=y\n+CONFIG_SPI=y\n+CONFIG_SPI_MEM=y\n+CONFIG_SPI_ATMEL=y\n+CONFIG_SPI_GPIO=y\n+CONFIG_PINCTRL_AT91=y\n+CONFIG_PINCTRL_AT91PIO4=y\n+CONFIG_GPIO_SYSFS=y\n+CONFIG_POWER_RESET=y\n+CONFIG_POWER_RESET_AT91_RESET=y\n+CONFIG_POWER_RESET_AT91_SAMA5D2_SHDWC=y\n+# CONFIG_HWMON is not set\n+CONFIG_WATCHDOG=y\n+CONFIG_SAMA5D4_WATCHDOG=y\n+CONFIG_MFD_ATMEL_FLEXCOM=y\n+CONFIG_REGULATOR=y\n+CONFIG_REGULATOR_FIXED_VOLTAGE=y\n+CONFIG_REGULATOR_MCP16502=y\n+CONFIG_MEDIA_SUPPORT=y\n+CONFIG_MEDIA_SUPPORT_FILTER=y\n+# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set\n+CONFIG_MEDIA_CAMERA_SUPPORT=y\n+CONFIG_MEDIA_PLATFORM_SUPPORT=y\n+CONFIG_V4L_PLATFORM_DRIVERS=y\n+CONFIG_VIDEO_IMX219=m\n+CONFIG_VIDEO_IMX274=m\n+CONFIG_VIDEO_OV5647=m\n+CONFIG_SOUND=y\n+CONFIG_SND=y\n+CONFIG_SND_SOC=y\n+CONFIG_SND_ATMEL_SOC=y\n+CONFIG_SND_SOC_MIKROE_PROTO=m\n+CONFIG_SND_MCHP_SOC_I2S_MCC=y\n+CONFIG_SND_MCHP_SOC_SPDIFTX=y\n+CONFIG_SND_MCHP_SOC_SPDIFRX=y\n+CONFIG_SND_SOC_PCM5102A=y\n+CONFIG_SND_SOC_SPDIF=y\n+CONFIG_SND_SIMPLE_CARD=y\n+CONFIG_USB=y\n+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y\n+CONFIG_USB_DYNAMIC_MINORS=y\n+CONFIG_USB_EHCI_HCD=y\n+CONFIG_USB_OHCI_HCD=y\n+CONFIG_USB_STORAGE=y\n+CONFIG_USB_UAS=y\n+CONFIG_USB_GADGET=y\n+CONFIG_U_SERIAL_CONSOLE=y\n+CONFIG_USB_ATMEL_USBA=m\n+CONFIG_USB_CONFIGFS=y\n+CONFIG_USB_CONFIGFS_ACM=y\n+CONFIG_USB_CONFIGFS_MASS_STORAGE=y\n+CONFIG_USB_CONFIGFS_F_UVC=y\n+CONFIG_USB_G_SERIAL=m\n+CONFIG_MMC=y\n+CONFIG_MMC_SDHCI=y\n+CONFIG_MMC_SDHCI_PLTFM=y\n+CONFIG_MMC_SDHCI_OF_AT91=y\n+CONFIG_NEW_LEDS=y\n+CONFIG_LEDS_CLASS=y\n+CONFIG_LEDS_GPIO=y\n+CONFIG_LEDS_TRIGGER_HEARTBEAT=y\n+CONFIG_RTC_CLASS=y\n+# CONFIG_RTC_NVMEM is not set\n+CONFIG_RTC_DRV_AT91RM9200=y\n+CONFIG_RTC_DRV_AT91SAM9=y\n+CONFIG_DMADEVICES=y\n+CONFIG_AT_XDMAC=y\n+CONFIG_DMATEST=y\n+CONFIG_STAGING=y\n+CONFIG_MICROCHIP_PIT64B=y\n+# CONFIG_IOMMU_SUPPORT is not set\n+# CONFIG_ATMEL_EBI is not set\n+CONFIG_IIO=y\n+CONFIG_IIO_SW_TRIGGER=y\n+CONFIG_AT91_SAMA5D2_ADC=y\n+CONFIG_PWM=y\n+CONFIG_PWM_ATMEL=y\n+CONFIG_EXT2_FS=y\n+CONFIG_EXT3_FS=y\n+CONFIG_FANOTIFY=y\n+CONFIG_VFAT_FS=y\n+CONFIG_TMPFS=y\n+CONFIG_NFS_FS=y\n+CONFIG_ROOT_NFS=y\n+CONFIG_NLS_CODEPAGE_437=y\n+CONFIG_NLS_CODEPAGE_850=y\n+CONFIG_NLS_ISO8859_1=y\n+CONFIG_NLS_UTF8=y\n+CONFIG_LSM=\"N\"\n+CONFIG_CRYPTO_DEFLATE=y\n+CONFIG_CRYPTO_LZO=y\n+# CONFIG_CRYPTO_HW is not set\n+CONFIG_CRC_CCITT=y\n+CONFIG_CRC_ITU_T=y\n+CONFIG_DMA_CMA=y\n+CONFIG_CMA_SIZE_MBYTES=32\n+CONFIG_CMA_ALIGNMENT=9\n+# CONFIG_SECTION_MISMATCH_WARN_ONLY is not set\n+CONFIG_DEBUG_FS=y\n+# CONFIG_DEBUG_MISC is not set\n+# CONFIG_SCHED_DEBUG is not set\n+CONFIG_STACKTRACE=y\n+# CONFIG_FTRACE is not set\n+CONFIG_DEBUG_USER=y\n+# CONFIG_RUNTIME_TESTING_MENU is not set\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/221-ARM-multi_v7_defconfig-add-sama7g5-SoC.patch",
    "content": "From a62536054548e85da84ed835dc87baa8e5e99b41 Mon Sep 17 00:00:00 2001\nFrom: Eugen Hristev <eugen.hristev@microchip.com>\nDate: Mon, 28 Jun 2021 15:04:52 +0300\nSubject: [PATCH 221/247] ARM: multi_v7_defconfig: add sama7g5 SoC\n\nAdd the Microchip SAMA7G5 ARM v7 Cortex-A7 based SoC to multi_v7_defconfig.\nAlso add it's clock timer, the PIT64B.\n\nSigned-off-by: Eugen Hristev <eugen.hristev@microchip.com>\nSigned-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>\nLink: https://lore.kernel.org/r/20210628120452.74408-4-eugen.hristev@microchip.com\n---\n arch/arm/configs/multi_v7_defconfig | 2 ++\n 1 file changed, 2 insertions(+)\n\n--- a/arch/arm/configs/multi_v7_defconfig\n+++ b/arch/arm/configs/multi_v7_defconfig\n@@ -15,6 +15,7 @@ CONFIG_ARCH_AT91=y\n CONFIG_SOC_SAMA5D2=y\n CONFIG_SOC_SAMA5D3=y\n CONFIG_SOC_SAMA5D4=y\n+CONFIG_SOC_SAMA7G5=y\n CONFIG_ARCH_BCM=y\n CONFIG_ARCH_BCM_CYGNUS=y\n CONFIG_ARCH_BCM_HR2=y\n@@ -967,6 +968,7 @@ CONFIG_APQ_MMCC_8084=y\n CONFIG_MSM_GCC_8660=y\n CONFIG_MSM_MMCC_8960=y\n CONFIG_MSM_MMCC_8974=y\n+CONFIG_MICROCHIP_PIT64B=y\n CONFIG_BCM2835_MBOX=y\n CONFIG_ROCKCHIP_IOMMU=y\n CONFIG_TEGRA_IOMMU_GART=y\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/222-ARM-dts-at91-add-sama7g5-SoC-DT-and-sama7g5-ek.patch",
    "content": "From 969b39d51b7df0869cca9983b06cefb59dae72b0 Mon Sep 17 00:00:00 2001\nFrom: Eugen Hristev <eugen.hristev@microchip.com>\nDate: Mon, 28 Jun 2021 15:04:50 +0300\nSubject: [PATCH 222/247] ARM: dts: at91: add sama7g5 SoC DT and sama7g5-ek\n\nAdd Device Tree for sama7g5 SoC and associated board sama7g5-ek\n\nSigned-off-by: Eugen Hristev <eugen.hristev@microchip.com>\n[claudiu.beznea@microchip.com: add clocks, ethernet, timers, power]\nSigned-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>\n[codrin.ciubotariu@microchip.com: add audio]\nSigned-off-by: Codrin Ciubotariu <codrin.ciubotariu@microchip.com>\n[nicolas.ferre@microchip.com: removed eeproms, reorder i2s dma chans]\nSigned-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>\nLink: https://lore.kernel.org/r/20210628120452.74408-2-eugen.hristev@microchip.com\n[claudiu.beznea: adapt to kernel v5.10]\nSigned-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>\n---\n arch/arm/boot/dts/Makefile           |   2 +\n arch/arm/boot/dts/at91-sama7g5ek.dts | 656 +++++++++++++++++++\n arch/arm/boot/dts/sama7g5-pinfunc.h  | 923 +++++++++++++++++++++++++++\n arch/arm/boot/dts/sama7g5.dtsi       | 528 +++++++++++++++\n 4 files changed, 2109 insertions(+)\n create mode 100644 arch/arm/boot/dts/at91-sama7g5ek.dts\n create mode 100644 arch/arm/boot/dts/sama7g5-pinfunc.h\n create mode 100644 arch/arm/boot/dts/sama7g5.dtsi\n\n--- a/arch/arm/boot/dts/Makefile\n+++ b/arch/arm/boot/dts/Makefile\n@@ -79,6 +79,8 @@ dtb-$(CONFIG_ARCH_ATLAS6) += \\\n \tatlas6-evb.dtb\n dtb-$(CONFIG_ARCH_ATLAS7) += \\\n \tatlas7-evb.dtb\n+dtb-$(CONFIG_SOC_SAMA7G5) += \\\n+\tat91-sama7g5ek.dtb\n dtb-$(CONFIG_ARCH_AXXIA) += \\\n \taxm5516-amarillo.dtb\n dtb-$(CONFIG_ARCH_BCM2835) += \\\n--- /dev/null\n+++ b/arch/arm/boot/dts/at91-sama7g5ek.dts\n@@ -0,0 +1,656 @@\n+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)\n+/*\n+ *  at91-sama7g5ek.dts - Device Tree file for SAMA7G5-EK board\n+ *\n+ *  Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries\n+ *\n+ *  Author: Eugen Hristev <eugen.hristev@microchip.com>\n+ *  Author: Claudiu Beznea <claudiu.beznea@microchip.com>\n+ *\n+ */\n+/dts-v1/;\n+#include \"sama7g5-pinfunc.h\"\n+#include \"sama7g5.dtsi\"\n+#include <dt-bindings/mfd/atmel-flexcom.h>\n+#include <dt-bindings/input/input.h>\n+\n+/ {\n+\tmodel = \"Microchip SAMA7G5-EK\";\n+\tcompatible = \"microchip,sama7g5ek\", \"microchip,sama7g5\", \"microchip,sama7\";\n+\n+\tchosen {\n+\t\tbootargs = \"rw root=/dev/mmcblk1p2 rootfstype=ext4 rootwait\";\n+\t\tstdout-path = \"serial0:115200n8\";\n+\t};\n+\n+\taliases {\n+\t\tserial0 = &uart3;\n+\t\tserial1 = &uart4;\n+\t\tserial2 = &uart7;\n+\t\tserial3 = &uart0;\n+\t\ti2c0 = &i2c1;\n+\t\ti2c1 = &i2c8;\n+\t\ti2c2 = &i2c9;\n+\t};\n+\n+\tclocks {\n+\t\tslow_xtal {\n+\t\t\tclock-frequency = <32768>;\n+\t\t};\n+\n+\t\tmain_xtal {\n+\t\t\tclock-frequency = <24000000>;\n+\t\t};\n+\t};\n+\n+\tgpio_keys {\n+\t\tcompatible = \"gpio-keys\";\n+\n+\t\tpinctrl-names = \"default\";\n+\t\tpinctrl-0 = <&pinctrl_key_gpio_default>;\n+\n+\t\tbp1 {\n+\t\t\tlabel = \"PB_USER\";\n+\t\t\tgpios = <&pioA PIN_PA12 GPIO_ACTIVE_LOW>;\n+\t\t\tlinux,code = <KEY_PROG1>;\n+\t\t\twakeup-source;\n+\t\t};\n+\t};\n+\n+\tleds {\n+\t\tcompatible = \"gpio-leds\";\n+\t\tpinctrl-names = \"default\";\n+\t\tpinctrl-0 = <&pinctrl_led_gpio_default>;\n+\t\tstatus = \"okay\"; /* Conflict with pwm. */\n+\n+\t\tred_led {\n+\t\t\tlabel = \"red\";\n+\t\t\tgpios = <&pioA PIN_PB8 GPIO_ACTIVE_HIGH>;\n+\t\t};\n+\n+\t\tgreen_led {\n+\t\t\tlabel = \"green\";\n+\t\t\tgpios = <&pioA PIN_PA13 GPIO_ACTIVE_HIGH>;\n+\t\t};\n+\n+\t\tblue_led {\n+\t\t\tlabel = \"blue\";\n+\t\t\tgpios = <&pioA PIN_PD20 GPIO_ACTIVE_HIGH>;\n+\t\t\tlinux,default-trigger = \"heartbeat\";\n+\t\t};\n+\t};\n+\n+\t/* 512 M */\n+\tmemory@60000000 {\n+\t\tdevice_type = \"memory\";\n+\t\treg = <0x60000000 0x20000000>;\n+\t};\n+\n+\tsound: sound {\n+\t\tcompatible = \"simple-audio-card\";\n+\t\tsimple-audio-card,name = \"sama7g5ek audio\";\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\tsimple-audio-card,dai-link@0 {\n+\t\t\treg = <0>;\n+\t\t\tcpu {\n+\t\t\t\tsound-dai = <&spdiftx>;\n+\t\t\t};\n+\t\t\tcodec {\n+\t\t\t\tsound-dai = <&spdif_out>;\n+\t\t\t};\n+\t\t};\n+\t\tsimple-audio-card,dai-link@1 {\n+\t\t\treg = <1>;\n+\t\t\tcpu {\n+\t\t\t\tsound-dai = <&spdifrx>;\n+\t\t\t};\n+\t\t\tcodec {\n+\t\t\t\tsound-dai = <&spdif_in>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tspdif_in: spdif-in {\n+\t\t#sound-dai-cells = <0>;\n+\t\tcompatible = \"linux,spdif-dir\";\n+\t};\n+\n+\tspdif_out: spdif-out {\n+\t\t#sound-dai-cells = <0>;\n+\t\tcompatible = \"linux,spdif-dit\";\n+\t};\n+};\n+\n+&cpu0 {\n+\tcpu-supply = <&vddcpu>;\n+};\n+\n+&dma0 {\n+\tstatus = \"okay\";\n+};\n+\n+&dma1 {\n+\tstatus = \"okay\";\n+};\n+\n+&dma2 {\n+\tstatus = \"okay\";\n+};\n+\n+&flx0 {\n+\tatmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_USART>;\n+\tstatus = \"disabled\";\n+\n+\tuart0: serial@200 {\n+\t\tpinctrl-names = \"default\";\n+\t\tpinctrl-0 = <&pinctrl_flx0_default>;\n+\t\tstatus = \"disabled\";\n+\t};\n+};\n+\n+&flx1 {\n+\tatmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>;\n+\tstatus = \"okay\";\n+\n+\ti2c1: i2c@600 {\n+\t\tpinctrl-names = \"default\";\n+\t\tpinctrl-0 = <&pinctrl_i2c1_default>;\n+\t\ti2c-analog-filter;\n+\t\ti2c-digital-filter;\n+\t\ti2c-digital-filter-width-ns = <35>;\n+\t\tstatus = \"okay\";\n+\n+\t\tmcp16502@5b {\n+\t\t\tcompatible = \"microchip,mcp16502\";\n+\t\t\treg = <0x5b>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tregulators {\n+\t\t\t\tvdd_3v3: VDD_IO {\n+\t\t\t\t\tregulator-name = \"VDD_IO\";\n+\t\t\t\t\tregulator-min-microvolt = <1200000>;\n+\t\t\t\t\tregulator-max-microvolt = <3700000>;\n+\t\t\t\t\tregulator-initial-mode = <2>;\n+\t\t\t\t\tregulator-allowed-modes = <2>, <4>;\n+\t\t\t\t\tregulator-always-on;\n+\n+\t\t\t\t\tregulator-state-standby {\n+\t\t\t\t\t\tregulator-on-in-suspend;\n+\t\t\t\t\t\tregulator-mode = <4>;\n+\t\t\t\t\t};\n+\n+\t\t\t\t\tregulator-state-mem {\n+\t\t\t\t\t\tregulator-off-in-suspend;\n+\t\t\t\t\t\tregulator-mode = <4>;\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\n+\t\t\t\tvddioddr: VDD_DDR {\n+\t\t\t\t\tregulator-name = \"VDD_DDR\";\n+\t\t\t\t\tregulator-min-microvolt = <1300000>;\n+\t\t\t\t\tregulator-max-microvolt = <1450000>;\n+\t\t\t\t\tregulator-initial-mode = <2>;\n+\t\t\t\t\tregulator-allowed-modes = <2>, <4>;\n+\t\t\t\t\tregulator-always-on;\n+\n+\t\t\t\t\tregulator-state-standby {\n+\t\t\t\t\t\tregulator-on-in-suspend;\n+\t\t\t\t\t\tregulator-mode = <4>;\n+\t\t\t\t\t};\n+\n+\t\t\t\t\tregulator-state-mem {\n+\t\t\t\t\t\tregulator-on-in-suspend;\n+\t\t\t\t\t\tregulator-mode = <4>;\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\n+\t\t\t\tvddcore: VDD_CORE {\n+\t\t\t\t\tregulator-name = \"VDD_CORE\";\n+\t\t\t\t\tregulator-min-microvolt = <1100000>;\n+\t\t\t\t\tregulator-max-microvolt = <1850000>;\n+\t\t\t\t\tregulator-initial-mode = <2>;\n+\t\t\t\t\tregulator-allowed-modes = <2>, <4>;\n+\t\t\t\t\tregulator-always-on;\n+\n+\t\t\t\t\tregulator-state-standby {\n+\t\t\t\t\t\tregulator-on-in-suspend;\n+\t\t\t\t\t\tregulator-mode = <4>;\n+\t\t\t\t\t};\n+\n+\t\t\t\t\tregulator-state-mem {\n+\t\t\t\t\t\tregulator-off-in-suspend;\n+\t\t\t\t\t\tregulator-mode = <4>;\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\n+\t\t\t\tvddcpu: VDD_OTHER {\n+\t\t\t\t\tregulator-name = \"VDD_OTHER\";\n+\t\t\t\t\tregulator-min-microvolt = <1125000>;\n+\t\t\t\t\tregulator-max-microvolt = <1850000>;\n+\t\t\t\t\tregulator-initial-mode = <2>;\n+\t\t\t\t\tregulator-allowed-modes = <2>, <4>;\n+\t\t\t\t\tregulator-ramp-delay = <3125>;\n+\t\t\t\t\tregulator-always-on;\n+\n+\t\t\t\t\tregulator-state-standby {\n+\t\t\t\t\t\tregulator-on-in-suspend;\n+\t\t\t\t\t\tregulator-mode = <4>;\n+\t\t\t\t\t};\n+\n+\t\t\t\t\tregulator-state-mem {\n+\t\t\t\t\t\tregulator-off-in-suspend;\n+\t\t\t\t\t\tregulator-mode = <4>;\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\n+\t\t\t\tvldo1: LDO1 {\n+\t\t\t\t\tregulator-name = \"LDO1\";\n+\t\t\t\t\tregulator-min-microvolt = <1200000>;\n+\t\t\t\t\tregulator-max-microvolt = <3700000>;\n+\t\t\t\t\tregulator-always-on;\n+\n+\t\t\t\t\tregulator-state-standby {\n+\t\t\t\t\t\tregulator-on-in-suspend;\n+\t\t\t\t\t};\n+\n+\t\t\t\t\tregulator-state-mem {\n+\t\t\t\t\t\tregulator-off-in-suspend;\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\n+\t\t\t\tvldo2: LDO2 {\n+\t\t\t\t\tregulator-name = \"LDO2\";\n+\t\t\t\t\tregulator-min-microvolt = <1200000>;\n+\t\t\t\t\tregulator-max-microvolt = <3700000>;\n+\n+\t\t\t\t\tregulator-state-standby {\n+\t\t\t\t\t\tregulator-on-in-suspend;\n+\t\t\t\t\t};\n+\n+\t\t\t\t\tregulator-state-mem {\n+\t\t\t\t\t\tregulator-off-in-suspend;\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\t\t\t};\n+\t\t};\n+\t};\n+};\n+\n+&flx3 {\n+\tatmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_USART>;\n+\tstatus = \"okay\";\n+\n+\tuart3: serial@200 {\n+\t\tpinctrl-names = \"default\";\n+\t\tpinctrl-0 = <&pinctrl_flx3_default>;\n+\t\tstatus = \"okay\";\n+\t};\n+};\n+\n+&flx4 {\n+\tatmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_USART>;\n+\tstatus = \"okay\";\n+\n+\tuart4: serial@200 {\n+\t\tpinctrl-names = \"default\";\n+\t\tpinctrl-0 = <&pinctrl_flx4_default>;\n+\t\tstatus = \"okay\";\n+\t};\n+};\n+\n+&flx7 {\n+\tatmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_USART>;\n+\tstatus = \"okay\";\n+\n+\tuart7: serial@200 {\n+\t\tpinctrl-names = \"default\";\n+\t\tpinctrl-0 = <&pinctrl_flx7_default>;\n+\t\tstatus = \"okay\";\n+\t};\n+};\n+\n+&flx8 {\n+\tatmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>;\n+\tstatus = \"okay\";\n+\n+\ti2c8: i2c@600 {\n+\t\tpinctrl-names = \"default\";\n+\t\tpinctrl-0 = <&pinctrl_i2c8_default>;\n+\t\ti2c-analog-filter;\n+\t\ti2c-digital-filter;\n+\t\ti2c-digital-filter-width-ns = <35>;\n+\t\tstatus = \"okay\";\n+\t};\n+};\n+\n+&flx9 {\n+\tatmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>;\n+\tstatus = \"okay\";\n+\n+\ti2c9: i2c@600 {\n+\t\tpinctrl-names = \"default\";\n+\t\tpinctrl-0 = <&pinctrl_i2c9_default>;\n+\t\ti2c-analog-filter;\n+\t\ti2c-digital-filter;\n+\t\ti2c-digital-filter-width-ns = <35>;\n+\t\tstatus = \"okay\";\n+\t};\n+};\n+\n+&flx11 {\n+\tatmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_SPI>;\n+\tstatus = \"okay\";\n+\n+\tspi11: spi@400 {\n+\t\tpinctrl-names = \"default\";\n+\t\tpinctrl-0 = <&pinctrl_mikrobus1_spi &pinctrl_mikrobus1_spi_cs>;\n+\t\tstatus = \"okay\";\n+\t};\n+};\n+\n+&gmac0 {\n+\t#address-cells = <1>;\n+\t#size-cells = <0>;\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pinctrl_gmac0_default &pinctrl_gmac0_txck_default &pinctrl_gmac0_phy_irq>;\n+\tphy-mode = \"rgmii-id\";\n+\tstatus = \"okay\";\n+\n+\tethernet-phy@7 {\n+\t\treg = <0x7>;\n+\t\tinterrupt-parent = <&pioA>;\n+\t\tinterrupts = <PIN_PA31 IRQ_TYPE_LEVEL_LOW>;\n+\t};\n+};\n+\n+&gmac1 {\n+\t#address-cells = <1>;\n+\t#size-cells = <0>;\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pinctrl_gmac1_default &pinctrl_gmac1_phy_irq>;\n+\tphy-mode = \"rmii\";\n+\tstatus = \"okay\";\n+\n+\tethernet-phy@0 {\n+\t\treg = <0x0>;\n+\t\tinterrupt-parent = <&pioA>;\n+\t\tinterrupts = <PIN_PA21 IRQ_TYPE_LEVEL_LOW>;\n+\t};\n+};\n+\n+&i2s0 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pinctrl_i2s0_default>;\n+};\n+\n+&pioA {\n+\tpinctrl_flx0_default: flx0_default {\n+\t\tpinmux = <PIN_PE3__FLEXCOM0_IO0>,\n+\t\t\t <PIN_PE4__FLEXCOM0_IO1>,\n+\t\t\t <PIN_PE6__FLEXCOM0_IO3>,\n+\t\t\t <PIN_PE7__FLEXCOM0_IO4>;\n+\t\tbias-disable;\n+\t};\n+\n+\tpinctrl_flx3_default: flx3_default {\n+\t\tpinmux = <PIN_PD16__FLEXCOM3_IO0>,\n+\t\t\t <PIN_PD17__FLEXCOM3_IO1>;\n+\t\tbias-disable;\n+\t};\n+\n+\tpinctrl_flx4_default: flx4_default {\n+\t\tpinmux = <PIN_PD18__FLEXCOM4_IO0>,\n+\t\t\t <PIN_PD19__FLEXCOM4_IO1>;\n+\t\tbias-disable;\n+\t};\n+\n+\tpinctrl_flx7_default: flx7_default {\n+\t\tpinmux = <PIN_PC23__FLEXCOM7_IO0>,\n+\t\t\t <PIN_PC24__FLEXCOM7_IO1>;\n+\t\tbias-disable;\n+\t};\n+\n+\tpinctrl_gmac0_default: gmac0_default {\n+\t\tpinmux = <PIN_PA16__G0_TX0>,\n+\t\t\t <PIN_PA17__G0_TX1>,\n+\t\t\t <PIN_PA26__G0_TX2>,\n+\t\t\t <PIN_PA27__G0_TX3>,\n+\t\t\t <PIN_PA19__G0_RX0>,\n+\t\t\t <PIN_PA20__G0_RX1>,\n+\t\t\t <PIN_PA28__G0_RX2>,\n+\t\t\t <PIN_PA29__G0_RX3>,\n+\t\t\t <PIN_PA15__G0_TXEN>,\n+\t\t\t <PIN_PA30__G0_RXCK>,\n+\t\t\t <PIN_PA18__G0_RXDV>,\n+\t\t\t <PIN_PA22__G0_MDC>,\n+\t\t\t <PIN_PA23__G0_MDIO>,\n+\t\t\t <PIN_PA25__G0_125CK>;\n+\t\tbias-disable;\n+\t};\n+\n+\tpinctrl_gmac0_txck_default: gmac0_txck_default {\n+\t\tpinmux = <PIN_PA24__G0_TXCK>;\n+\t\tbias-pull-up;\n+\t};\n+\n+\tpinctrl_gmac0_phy_irq: gmac0_phy_irq {\n+\t\tpinmux = <PIN_PA31__GPIO>;\n+\t\tbias-disable;\n+\t};\n+\n+\tpinctrl_gmac1_default: gmac1_default {\n+\t\tpinmux = <PIN_PD30__G1_TXCK>,\n+\t\t\t <PIN_PD22__G1_TX0>,\n+\t\t\t <PIN_PD23__G1_TX1>,\n+\t\t\t <PIN_PD21__G1_TXEN>,\n+\t\t\t <PIN_PD25__G1_RX0>,\n+\t\t\t <PIN_PD26__G1_RX1>,\n+\t\t\t <PIN_PD27__G1_RXER>,\n+\t\t\t <PIN_PD24__G1_RXDV>,\n+\t\t\t <PIN_PD28__G1_MDC>,\n+\t\t\t <PIN_PD29__G1_MDIO>;\n+\t\tbias-disable;\n+\t};\n+\n+\tpinctrl_gmac1_phy_irq: gmac1_phy_irq {\n+\t\tpinmux = <PIN_PA21__GPIO>;\n+\t\tbias-disable;\n+\t};\n+\n+\tpinctrl_i2c1_default: i2c1_default {\n+\t\tpinmux = <PIN_PC9__FLEXCOM1_IO0>,\n+\t\t\t <PIN_PC10__FLEXCOM1_IO1>;\n+\t\tbias-disable;\n+\t};\n+\n+\tpinctrl_i2c8_default: i2c8_default {\n+\t\tpinmux = <PIN_PC14__FLEXCOM8_IO0>,\n+\t\t\t <PIN_PC13__FLEXCOM8_IO1>;\n+\t\tbias-disable;\n+\t};\n+\n+\tpinctrl_i2c9_default: i2c9_default {\n+\t\tpinmux = <PIN_PC18__FLEXCOM9_IO0>,\n+\t\t\t <PIN_PC19__FLEXCOM9_IO1>;\n+\t\tbias-disable;\n+\t};\n+\n+\tpinctrl_i2s0_default: i2s0_default {\n+\t\tpinmux = <PIN_PB23__I2SMCC0_CK>,\n+\t\t\t <PIN_PB24__I2SMCC0_WS>,\n+\t\t\t <PIN_PB25__I2SMCC0_DOUT1>,\n+\t\t\t <PIN_PB26__I2SMCC0_DOUT0>,\n+\t\t\t <PIN_PB27__I2SMCC0_MCK>;\n+\t\tbias-disable;\n+\t};\n+\n+\tpinctrl_key_gpio_default: key_gpio_default {\n+\t\tpinmux = <PIN_PA12__GPIO>;\n+\t\tbias-pull-up;\n+\t};\n+\n+\tpinctrl_led_gpio_default: led_gpio_default {\n+\t\tpinmux = <PIN_PA13__GPIO>,\n+\t\t\t <PIN_PB8__GPIO>,\n+\t\t\t <PIN_PD20__GPIO>;\n+\t\tbias-pull-up;\n+\t};\n+\n+\tpinctrl_mikrobus1_an_default: mikrobus1_an_default {\n+\t\tpinmux = <PIN_PD0__GPIO>;\n+\t\tbias-disable;\n+\t};\n+\n+\tpinctrl_mikrobus2_an_default: mikrobus2_an_default {\n+\t\tpinmux = <PIN_PD1__GPIO>;\n+\t\tbias-disable;\n+\t};\n+\n+\tpinctrl_mikrobus1_pwm2_default: mikrobus1_pwm2_default {\n+\t\tpinmux = <PIN_PA13__PWMH2>;\n+\t\tbias-disable;\n+\t};\n+\n+\tpinctrl_mikrobus2_pwm3_default: mikrobus2_pwm3_default {\n+\t\tpinmux = <PIN_PD20__PWMH3>;\n+\t\tbias-disable;\n+\t};\n+\n+\tpinctrl_mikrobus1_spi_cs: mikrobus1_spi_cs {\n+\t\tpinmux = <PIN_PB6__FLEXCOM11_IO3>;\n+\t\tbias-disable;\n+\t};\n+\n+\tpinctrl_mikrobus1_spi: mikrobus1_spi {\n+\t\tpinmux = <PIN_PB3__FLEXCOM11_IO0>,\n+\t\t\t <PIN_PB4__FLEXCOM11_IO1>,\n+\t\t\t <PIN_PB5__FLEXCOM11_IO2>;\n+\t\tbias-disable;\n+\t};\n+\n+\tpinctrl_sdmmc0_default: sdmmc0_default {\n+\t\tcmd_data {\n+\t\t\tpinmux = <PIN_PA1__SDMMC0_CMD>,\n+\t\t\t\t <PIN_PA3__SDMMC0_DAT0>,\n+\t\t\t\t <PIN_PA4__SDMMC0_DAT1>,\n+\t\t\t\t <PIN_PA5__SDMMC0_DAT2>,\n+\t\t\t\t <PIN_PA6__SDMMC0_DAT3>,\n+\t\t\t\t <PIN_PA7__SDMMC0_DAT4>,\n+\t\t\t\t <PIN_PA8__SDMMC0_DAT5>,\n+\t\t\t\t <PIN_PA9__SDMMC0_DAT6>,\n+\t\t\t\t <PIN_PA10__SDMMC0_DAT7>;\n+\t\t\tbias-pull-up;\n+\t\t};\n+\n+\t\tck_cd_rstn_vddsel {\n+\t\t\tpinmux = <PIN_PA0__SDMMC0_CK>,\n+\t\t\t\t <PIN_PA2__SDMMC0_RSTN>,\n+\t\t\t\t <PIN_PA11__SDMMC0_DS>;\n+\t\t\tbias-pull-up;\n+\t\t};\n+\t};\n+\n+\tpinctrl_sdmmc1_default: sdmmc1_default {\n+\t\tcmd_data {\n+\t\t\tpinmux = <PIN_PB29__SDMMC1_CMD>,\n+\t\t\t\t <PIN_PB31__SDMMC1_DAT0>,\n+\t\t\t\t <PIN_PC0__SDMMC1_DAT1>,\n+\t\t\t\t <PIN_PC1__SDMMC1_DAT2>,\n+\t\t\t\t <PIN_PC2__SDMMC1_DAT3>;\n+\t\t\tbias-pull-up;\n+\t\t};\n+\n+\t\tck_cd_rstn_vddsel {\n+\t\t\tpinmux = <PIN_PB30__SDMMC1_CK>,\n+\t\t\t\t <PIN_PB28__SDMMC1_RSTN>,\n+\t\t\t\t <PIN_PC5__SDMMC1_1V8SEL>,\n+\t\t\t\t <PIN_PC4__SDMMC1_CD>;\n+\t\t\tbias-pull-up;\n+\t\t};\n+\t};\n+\n+\tpinctrl_sdmmc2_default: sdmmc2_default {\n+\t\tcmd_data {\n+\t\t\tpinmux = <PIN_PD3__SDMMC2_CMD>,\n+\t\t\t\t <PIN_PD5__SDMMC2_DAT0>,\n+\t\t\t\t <PIN_PD6__SDMMC2_DAT1>,\n+\t\t\t\t <PIN_PD7__SDMMC2_DAT2>,\n+\t\t\t\t <PIN_PD8__SDMMC2_DAT3>;\n+\t\t\tbias-pull-up;\n+\t\t};\n+\n+\t\tck {\n+\t\t\tpinmux = <PIN_PD4__SDMMC2_CK>;\n+\t\t\tbias-pull-up;\n+\t\t};\n+\t};\n+\n+\tpinctrl_spdifrx_default: spdifrx_default {\n+\t\tpinmux = <PIN_PB0__SPDIF_RX>;\n+\t\tbias-disable;\n+\t};\n+\n+\tpinctrl_spdiftx_default: spdiftx_default {\n+\t\tpinmux = <PIN_PB1__SPDIF_TX>;\n+\t\tbias-disable;\n+\t};\n+};\n+\n+&pwm {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pinctrl_mikrobus1_pwm2_default &pinctrl_mikrobus2_pwm3_default>;\n+\tstatus = \"disabled\"; /* Conflict with leds. */\n+};\n+\n+&rtt {\n+\tatmel,rtt-rtc-time-reg = <&gpbr 0x0>;\n+};\n+\n+&sdmmc0 {\n+\tbus-width = <8>;\n+\tnon-removable;\n+\tno-1-8-v;\n+\tsdhci-caps-mask = <0x0 0x00200000>;\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pinctrl_sdmmc0_default>;\n+\tstatus = \"okay\";\n+};\n+\n+&sdmmc1 {\n+\tbus-width = <4>;\n+\tno-1-8-v;\n+\tsdhci-caps-mask = <0x0 0x00200000>;\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pinctrl_sdmmc1_default>;\n+\tstatus = \"okay\";\n+};\n+\n+&sdmmc2 {\n+\tbus-width = <4>;\n+\tno-1-8-v;\n+\tsdhci-caps-mask = <0x0 0x00200000>;\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pinctrl_sdmmc2_default>;\n+};\n+\n+&spdifrx {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pinctrl_spdifrx_default>;\n+\tstatus = \"okay\";\n+};\n+\n+&spdiftx {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pinctrl_spdiftx_default>;\n+\tstatus = \"okay\";\n+};\n+\n+&trng {\n+\tstatus = \"okay\";\n+};\n+\n+&vddout25 {\n+\tvin-supply = <&vdd_3v3>;\n+\tstatus = \"okay\";\n+};\n--- /dev/null\n+++ b/arch/arm/boot/dts/sama7g5-pinfunc.h\n@@ -0,0 +1,923 @@\n+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */\n+#define PINMUX_PIN(no, func, ioset) \\\n+(((no) & 0xffff) | (((func) & 0xf) << 16) | (((ioset) & 0xff) << 20))\n+\n+#define PIN_PA0\t\t\t\t0\n+#define PIN_PA0__GPIO\t\t\tPINMUX_PIN(PIN_PA0, 0, 0)\n+#define PIN_PA0__SDMMC0_CK\t\tPINMUX_PIN(PIN_PA0, 1, 1)\n+#define PIN_PA0__FLEXCOM0_IO0\t\tPINMUX_PIN(PIN_PA0, 2, 1)\n+#define PIN_PA0__CANTX3\t\t\tPINMUX_PIN(PIN_PA0, 3, 1)\n+#define PIN_PA0__PWML0\t\t\tPINMUX_PIN(PIN_PA0, 5, 2)\n+#define PIN_PA1\t\t\t\t1\n+#define PIN_PA1__GPIO\t\t\tPINMUX_PIN(PIN_PA1, 0, 0)\n+#define PIN_PA1__SDMMC0_CMD\t\tPINMUX_PIN(PIN_PA1, 1, 1)\n+#define PIN_PA1__FLEXCOM0_IO1\t\tPINMUX_PIN(PIN_PA1, 2, 1)\n+#define PIN_PA1__CANRX3\t\t\tPINMUX_PIN(PIN_PA1, 3, 1)\n+#define PIN_PA1__D14\t\t\tPINMUX_PIN(PIN_PA1, 4, 1)\n+#define PIN_PA1__PWMH0\t\t\tPINMUX_PIN(PIN_PA1, 5, 3)\n+#define PIN_PA2\t\t\t\t2\n+#define PIN_PA2__GPIO\t\t\tPINMUX_PIN(PIN_PA2, 0, 0)\n+#define PIN_PA2__SDMMC0_RSTN\t\tPINMUX_PIN(PIN_PA2, 1, 1)\n+#define PIN_PA2__FLEXCOM0_IO2\t\tPINMUX_PIN(PIN_PA2, 2, 1)\n+#define PIN_PA2__PDMC1_CLK\t\tPINMUX_PIN(PIN_PA2, 3, 1)\n+#define PIN_PA2__D15\t\t\tPINMUX_PIN(PIN_PA2, 4, 1)\n+#define PIN_PA2__PWMH1\t\t\tPINMUX_PIN(PIN_PA2, 5, 3)\n+#define PIN_PA2__FLEXCOM1_IO0\t\tPINMUX_PIN(PIN_PA2, 6, 3)\n+#define PIN_PA3\t\t\t\t3\n+#define PIN_PA3__GPIO\t\t\tPINMUX_PIN(PIN_PA3, 0, 0)\n+#define PIN_PA3__SDMMC0_DAT0\t\tPINMUX_PIN(PIN_PA3, 1, 1)\n+#define PIN_PA3__FLEXCOM0_IO3\t\tPINMUX_PIN(PIN_PA3, 2, 1)\n+#define PIN_PA3__PDMC1_DS0\t\tPINMUX_PIN(PIN_PA3, 3, 1)\n+#define PIN_PA3__NWR1_NBS1\t\tPINMUX_PIN(PIN_PA3, 4, 1)\n+#define PIN_PA3__PWML3\t\t\tPINMUX_PIN(PIN_PA3, 5, 3)\n+#define PIN_PA3__FLEXCOM1_IO1\t\tPINMUX_PIN(PIN_PA3, 6, 3)\n+#define PIN_PA4\t\t\t\t4\n+#define PIN_PA4__GPIO\t\t\tPINMUX_PIN(PIN_PA4, 0, 0)\n+#define PIN_PA4__SDMMC0_DAT1\t\tPINMUX_PIN(PIN_PA4, 1, 1)\n+#define PIN_PA4__FLEXCOM0_IO4\t\tPINMUX_PIN(PIN_PA4, 2, 1)\n+#define PIN_PA4__PDMC1_DS1\t\tPINMUX_PIN(PIN_PA4, 3, 1)\n+#define PIN_PA4__NCS2\t\t\tPINMUX_PIN(PIN_PA4, 4, 1)\n+#define PIN_PA4__PWMH3\t\t\tPINMUX_PIN(PIN_PA4, 5, 3)\n+#define PIN_PA4__FLEXCOM2_IO0\t\tPINMUX_PIN(PIN_PA4, 6, 3)\n+#define PIN_PA5\t\t\t\t5\n+#define PIN_PA5__GPIO\t\t\tPINMUX_PIN(PIN_PA5, 0, 0)\n+#define PIN_PA5__SDMMC0_DAT2\t\tPINMUX_PIN(PIN_PA5, 1, 1)\n+#define PIN_PA5__FLEXCOM1_IO0\t\tPINMUX_PIN(PIN_PA5, 2, 1)\n+#define PIN_PA5__CANTX2\t\t\tPINMUX_PIN(PIN_PA5, 3, 1)\n+#define PIN_PA5__A23\t\t\tPINMUX_PIN(PIN_PA5, 4, 1)\n+#define PIN_PA5__PWMEXTRG0\t\tPINMUX_PIN(PIN_PA5, 5, 3)\n+#define PIN_PA5__FLEXCOM2_IO1\t\tPINMUX_PIN(PIN_PA5, 6, 3)\n+#define PIN_PA6\t\t\t\t6\n+#define PIN_PA6__GPIO\t\t\tPINMUX_PIN(PIN_PA6, 0, 0)\n+#define PIN_PA6__SDMMC0_DAT3\t\tPINMUX_PIN(PIN_PA6, 1, 1)\n+#define PIN_PA6__FLEXCOM1_IO1\t\tPINMUX_PIN(PIN_PA6, 2, 1)\n+#define PIN_PA6__CANRX2\t\t\tPINMUX_PIN(PIN_PA6, 3, 1)\n+#define PIN_PA6__A24\t\t\tPINMUX_PIN(PIN_PA6, 4, 1)\n+#define PIN_PA6__PWMEXTRG1\t\tPINMUX_PIN(PIN_PA6, 5, 3)\n+#define PIN_PA6__FLEXCOM3_IO0\t\tPINMUX_PIN(PIN_PA6, 6, 3)\n+#define PIN_PA7\t\t\t\t7\n+#define PIN_PA7__GPIO\t\t\tPINMUX_PIN(PIN_PA7, 0, 0)\n+#define PIN_PA7__SDMMC0_DAT4\t\tPINMUX_PIN(PIN_PA7, 1, 1)\n+#define PIN_PA7__FLEXCOM2_IO0\t\tPINMUX_PIN(PIN_PA7, 2, 1)\n+#define PIN_PA7__CANTX1\t\t\tPINMUX_PIN(PIN_PA7, 3, 1)\n+#define PIN_PA7__NWAIT\t\t\tPINMUX_PIN(PIN_PA7, 4, 1)\n+#define PIN_PA7__PWMFI0\t\t\tPINMUX_PIN(PIN_PA7, 5, 3)\n+#define PIN_PA7__FLEXCOM3_IO1\t\tPINMUX_PIN(PIN_PA7, 6, 3)\n+#define PIN_PA8\t\t\t\t8\n+#define PIN_PA8__GPIO\t\t\tPINMUX_PIN(PIN_PA8, 0, 0)\n+#define PIN_PA8__SDMMC0_DAT5\t\tPINMUX_PIN(PIN_PA8, 1, 1)\n+#define PIN_PA8__FLEXCOM2_IO1\t\tPINMUX_PIN(PIN_PA8, 2, 1)\n+#define PIN_PA8__CANRX1\t\t\tPINMUX_PIN(PIN_PA8, 3, 1)\n+#define PIN_PA8__NCS0\t\t\tPINMUX_PIN(PIN_PA8, 4, 1)\n+#define PIN_PA8__PWMIF1\t\t\tPINMUX_PIN(PIN_PA8, 5, 3)\n+#define PIN_PA8__FLEXCOM4_IO0\t\tPINMUX_PIN(PIN_PA8, 6, 3)\n+#define PIN_PA9\t\t\t\t9\n+#define PIN_PA9__GPIO\t\t\tPINMUX_PIN(PIN_PA9, 0, 0)\n+#define PIN_PA9__SDMMC0_DAT6\t\tPINMUX_PIN(PIN_PA9, 1, 1)\n+#define PIN_PA9__FLEXCOM2_IO2\t\tPINMUX_PIN(PIN_PA9, 2, 1)\n+#define PIN_PA9__CANTX0\t\t\tPINMUX_PIN(PIN_PA9, 3, 1)\n+#define PIN_PA9__SMCK\t\t\tPINMUX_PIN(PIN_PA9, 4, 1)\n+#define PIN_PA9__SPDIF_RX\t\tPINMUX_PIN(PIN_PA9, 5, 1)\n+#define PIN_PA9__FLEXCOM4_IO1\t\tPINMUX_PIN(PIN_PA9, 6, 3)\n+#define PIN_PA10\t\t\t10\n+#define PIN_PA10__GPIO\t\t\tPINMUX_PIN(PIN_PA10, 0, 0)\n+#define PIN_PA10__SDMMC0_DAT7\t\tPINMUX_PIN(PIN_PA10, 1, 1)\n+#define PIN_PA10__FLEXCOM2_IO3\t\tPINMUX_PIN(PIN_PA10, 2, 1)\n+#define PIN_PA10__CANRX0\t\tPINMUX_PIN(PIN_PA10, 3, 1)\n+#define PIN_PA10__NCS1\t\t\tPINMUX_PIN(PIN_PA10, 4, 1)\n+#define PIN_PA10__SPDIF_TX\t\tPINMUX_PIN(PIN_PA10, 5, 1)\n+#define PIN_PA10__FLEXCOM5_IO0\t\tPINMUX_PIN(PIN_PA10, 6, 3)\n+#define PIN_PA11\t\t\t11\n+#define PIN_PA11__GPIO\t\t\tPINMUX_PIN(PIN_PA11, 0, 0)\n+#define PIN_PA11__SDMMC0_DS\t\tPINMUX_PIN(PIN_PA11, 1, 1)\n+#define PIN_PA11__FLEXCOM2_IO4\t\tPINMUX_PIN(PIN_PA11, 2, 1)\n+#define PIN_PA11__A0_NBS0\t\tPINMUX_PIN(PIN_PA11, 4, 1)\n+#define PIN_PA11__TIOA0\t\t\tPINMUX_PIN(PIN_PA11, 5, 1)\n+#define PIN_PA11__FLEXCOM5_IO1\t\tPINMUX_PIN(PIN_PA11, 6, 3)\n+#define PIN_PA12\t\t\t12\n+#define PIN_PA12__GPIO\t\t\tPINMUX_PIN(PIN_PA12, 0, 0)\n+#define PIN_PA12__SDMMC0_WP\t\tPINMUX_PIN(PIN_PA12, 1, 1)\n+#define PIN_PA12__FLEXCOM1_IO3\t\tPINMUX_PIN(PIN_PA12, 2, 1)\n+#define PIN_PA12__FLEXCOM3_IO5\t\tPINMUX_PIN(PIN_PA12, 4, 1)\n+#define PIN_PA12__PWML2\t\t\tPINMUX_PIN(PIN_PA12, 5, 3)\n+#define PIN_PA12__FLEXCOM6_IO0\t\tPINMUX_PIN(PIN_PA12, 6, 3)\n+#define PIN_PA13\t\t\t13\n+#define PIN_PA13__GPIO\t\t\tPINMUX_PIN(PIN_PA13, 0, 0)\n+#define PIN_PA13__SDMMC0_1V8SEL\t\tPINMUX_PIN(PIN_PA13, 1, 1)\n+#define PIN_PA13__FLEXCOM1_IO2\t\tPINMUX_PIN(PIN_PA13, 2, 1)\n+#define PIN_PA13__FLEXCOM3_IO6\t\tPINMUX_PIN(PIN_PA13, 4, 1)\n+#define PIN_PA13__PWMH2\t\t\tPINMUX_PIN(PIN_PA13, 5, 3)\n+#define PIN_PA13__FLEXCOM6_IO1\t\tPINMUX_PIN(PIN_PA13, 6, 3)\n+#define PIN_PA14\t\t\t14\n+#define PIN_PA14__GPIO\t\t\tPINMUX_PIN(PIN_PA14, 0, 0)\n+#define PIN_PA14__SDMMC0_CD\t\tPINMUX_PIN(PIN_PA14, 1, 1)\n+#define PIN_PA14__FLEXCOM1_IO4\t\tPINMUX_PIN(PIN_PA14, 2, 1)\n+#define PIN_PA14__A25\t\t\tPINMUX_PIN(PIN_PA14, 4, 1)\n+#define PIN_PA14__PWML1\t\t\tPINMUX_PIN(PIN_PA14, 5, 3)\n+#define PIN_PA15\t\t\t15\n+#define PIN_PA15__GPIO\t\t\tPINMUX_PIN(PIN_PA15, 0, 0)\n+#define PIN_PA15__G0_TXEN\t\tPINMUX_PIN(PIN_PA15, 1, 1)\n+#define PIN_PA15__FLEXCOM3_IO0\t\tPINMUX_PIN(PIN_PA15, 2, 1)\n+#define PIN_PA15__ISC_MCK\t\tPINMUX_PIN(PIN_PA15, 3, 1)\n+#define PIN_PA15__A1\t\t\tPINMUX_PIN(PIN_PA15, 4, 1)\n+#define PIN_PA15__TIOB0\t\t\tPINMUX_PIN(PIN_PA15, 5, 1)\n+#define PIN_PA16\t\t\t16\n+#define PIN_PA16__GPIO\t\t\tPINMUX_PIN(PIN_PA16, 0, 0)\n+#define PIN_PA16__G0_TX0\t\tPINMUX_PIN(PIN_PA16, 1, 1)\n+#define PIN_PA16__FLEXCOM3_IO1\t\tPINMUX_PIN(PIN_PA16, 2, 1)\n+#define PIN_PA16__ISC_D0\t\tPINMUX_PIN(PIN_PA16, 3, 1)\n+#define PIN_PA16__A2\t\t\tPINMUX_PIN(PIN_PA16, 4, 1)\n+#define PIN_PA16__TCLK0\t\t\tPINMUX_PIN(PIN_PA16, 5, 1)\n+#define PIN_PA17\t\t\t17\n+#define PIN_PA17__GPIO\t\t\tPINMUX_PIN(PIN_PA17, 0, 0)\n+#define PIN_PA17__G0_TX1\t\tPINMUX_PIN(PIN_PA17, 1, 1)\n+#define PIN_PA17__FLEXCOM3_IO2\t\tPINMUX_PIN(PIN_PA17, 2, 1)\n+#define PIN_PA17__ISC_D1\t\tPINMUX_PIN(PIN_PA17, 3, 1)\n+#define PIN_PA17__A3\t\t\tPINMUX_PIN(PIN_PA17, 4, 1)\n+#define PIN_PA17__TIOA1\t\t\tPINMUX_PIN(PIN_PA17, 5, 1)\n+#define PIN_PA18\t\t\t18\n+#define PIN_PA18__GPIO\t\t\tPINMUX_PIN(PIN_PA18, 0, 0)\n+#define PIN_PA18__G0_RXDV\t\tPINMUX_PIN(PIN_PA18, 1, 1)\n+#define PIN_PA18__FLEXCOM3_IO3\t\tPINMUX_PIN(PIN_PA18, 2, 1)\n+#define PIN_PA18__ISC_D2\t\tPINMUX_PIN(PIN_PA18, 3, 1)\n+#define PIN_PA18__A4\t\t\tPINMUX_PIN(PIN_PA18, 4, 1)\n+#define PIN_PA18__TIOB1\t\t\tPINMUX_PIN(PIN_PA18, 5, 1)\n+#define PIN_PA19\t\t\t19\n+#define PIN_PA19__GPIO\t\t\tPINMUX_PIN(PIN_PA19, 0, 0)\n+#define PIN_PA19__G0_RX0\t\tPINMUX_PIN(PIN_PA19, 1, 1)\n+#define PIN_PA19__FLEXCOM3_IO4\t\tPINMUX_PIN(PIN_PA19, 2, 1)\n+#define PIN_PA19__ISC_D3\t\tPINMUX_PIN(PIN_PA19, 3, 1)\n+#define PIN_PA19__A5\t\t\tPINMUX_PIN(PIN_PA19, 4, 1)\n+#define PIN_PA19__TCLK1\t\t\tPINMUX_PIN(PIN_PA19, 5, 1)\n+#define PIN_PA20\t\t\t20\n+#define PIN_PA20__GPIO\t\t\tPINMUX_PIN(PIN_PA20, 0, 0)\n+#define PIN_PA20__G0_RX1\t\tPINMUX_PIN(PIN_PA20, 1, 1)\n+#define PIN_PA20__FLEXCOM4_IO0\t\tPINMUX_PIN(PIN_PA20, 2, 1)\n+#define PIN_PA20__ISC_D4\t\tPINMUX_PIN(PIN_PA20, 3, 1)\n+#define PIN_PA20__A6\t\t\tPINMUX_PIN(PIN_PA20, 4, 1)\n+#define PIN_PA20__TIOA2\t\t\tPINMUX_PIN(PIN_PA20, 5, 1)\n+#define PIN_PA21\t\t\t21\n+#define PIN_PA21__GPIO\t\t\tPINMUX_PIN(PIN_PA21, 0, 0)\n+#define PIN_PA21__G0_RXER\t\tPINMUX_PIN(PIN_PA21, 1, 1)\n+#define PIN_PA21__FLEXCOM4_IO1\t\tPINMUX_PIN(PIN_PA21, 2, 1)\n+#define PIN_PA21__ISC_D5\t\tPINMUX_PIN(PIN_PA21, 3, 1)\n+#define PIN_PA21__A7\t\t\tPINMUX_PIN(PIN_PA21, 4, 1)\n+#define PIN_PA21__TIOB2\t\t\tPINMUX_PIN(PIN_PA21, 5, 1)\n+#define PIN_PA22\t\t\t22\n+#define PIN_PA22__GPIO\t\t\tPINMUX_PIN(PIN_PA22, 0, 0)\n+#define PIN_PA22__G0_MDC\t\tPINMUX_PIN(PIN_PA22, 1, 1)\n+#define PIN_PA22__FLEXCOM4_IO2\t\tPINMUX_PIN(PIN_PA22, 2, 1)\n+#define PIN_PA22__ISC_D6\t\tPINMUX_PIN(PIN_PA22, 3, 1)\n+#define PIN_PA22__A8\t\t\tPINMUX_PIN(PIN_PA22, 4, 1)\n+#define PIN_PA22__TCLK2\t\t\tPINMUX_PIN(PIN_PA22, 5, 1)\n+#define PIN_PA23\t\t\t23\n+#define PIN_PA23__GPIO\t\t\tPINMUX_PIN(PIN_PA23, 0, 0)\n+#define PIN_PA23__G0_MDIO\t\tPINMUX_PIN(PIN_PA23, 1, 1)\n+#define PIN_PA23__FLEXCOM4_IO3\t\tPINMUX_PIN(PIN_PA23, 2, 1)\n+#define PIN_PA23__ISC_D7\t\tPINMUX_PIN(PIN_PA23, 3, 1)\n+#define PIN_PA23__A9\t\t\tPINMUX_PIN(PIN_PA23, 4, 1)\n+#define PIN_PA24\t\t\t24\n+#define PIN_PA24__GPIO\t\t\tPINMUX_PIN(PIN_PA24, 0, 0)\n+#define PIN_PA24__G0_TXCK\t\tPINMUX_PIN(PIN_PA24, 1, 1)\n+#define PIN_PA24__FLEXCOM4_IO4\t\tPINMUX_PIN(PIN_PA24, 2, 1)\n+#define PIN_PA24__ISC_HSYNC\t\tPINMUX_PIN(PIN_PA24, 3, 1)\n+#define PIN_PA24__A10\t\t\tPINMUX_PIN(PIN_PA24, 4, 1)\n+#define PIN_PA24__FLEXCOM0_IO5\t\tPINMUX_PIN(PIN_PA24, 5, 1)\n+#define PIN_PA25\t\t\t25\n+#define PIN_PA25__GPIO\t\t\tPINMUX_PIN(PIN_PA25, 0, 0)\n+#define PIN_PA25__G0_125CK\t\tPINMUX_PIN(PIN_PA25, 1, 1)\n+#define PIN_PA25__FLEXCOM5_IO4\t\tPINMUX_PIN(PIN_PA25, 2, 1)\n+#define PIN_PA25__ISC_VSYNC\t\tPINMUX_PIN(PIN_PA25, 3, 1)\n+#define PIN_PA25__A11\t\t\tPINMUX_PIN(PIN_PA25, 4, 1)\n+#define PIN_PA25__FLEXCOM0_IO6\t\tPINMUX_PIN(PIN_PA25, 5, 1)\n+#define PIN_PA25__FLEXCOM7_IO0\t\tPINMUX_PIN(PIN_PA25, 6, 3)\n+#define PIN_PA26\t\t\t26\n+#define PIN_PA26__GPIO\t\t\tPINMUX_PIN(PIN_PA26, 0, 0)\n+#define PIN_PA26__G0_TX2\t\tPINMUX_PIN(PIN_PA26, 1, 1)\n+#define PIN_PA26__FLEXCOM5_IO2\t\tPINMUX_PIN(PIN_PA26, 2, 1)\n+#define PIN_PA26__ISC_FIELD\t\tPINMUX_PIN(PIN_PA26, 3, 1)\n+#define PIN_PA26__A12\t\t\tPINMUX_PIN(PIN_PA26, 4, 1)\n+#define PIN_PA26__TF0\t\t\tPINMUX_PIN(PIN_PA26, 5, 1)\n+#define PIN_PA26__FLEXCOM7_IO1\t\tPINMUX_PIN(PIN_PA26, 6, 3)\n+#define PIN_PA27\t\t\t27\n+#define PIN_PA27__GPIO\t\t\tPINMUX_PIN(PIN_PA27, 0, 0)\n+#define PIN_PA27__G0_TX3\t\tPINMUX_PIN(PIN_PA27, 1, 1)\n+#define PIN_PA27__FLEXCOM5_IO3\t\tPINMUX_PIN(PIN_PA27, 2, 1)\n+#define PIN_PA27__ISC_PCK\t\tPINMUX_PIN(PIN_PA27, 3, 1)\n+#define PIN_PA27__A13\t\t\tPINMUX_PIN(PIN_PA27, 4, 1)\n+#define PIN_PA27__TK0\t\t\tPINMUX_PIN(PIN_PA27, 5, 1)\n+#define PIN_PA27__FLEXCOM8_IO0\t\tPINMUX_PIN(PIN_PA27, 6, 3)\n+#define PIN_PA28\t\t\t28\n+#define PIN_PA28__GPIO\t\t\tPINMUX_PIN(PIN_PA28, 0, 0)\n+#define PIN_PA28__G0_RX2\t\tPINMUX_PIN(PIN_PA28, 1, 1)\n+#define PIN_PA28__FLEXCOM5_IO0\t\tPINMUX_PIN(PIN_PA28, 2, 1)\n+#define PIN_PA28__ISC_D8\t\tPINMUX_PIN(PIN_PA28, 3, 1)\n+#define PIN_PA28__A14\t\t\tPINMUX_PIN(PIN_PA28, 4, 1)\n+#define PIN_PA28__RD0\t\t\tPINMUX_PIN(PIN_PA28, 5, 1)\n+#define PIN_PA28__FLEXCOM8_IO1\t\tPINMUX_PIN(PIN_PA28, 6, 3)\n+#define PIN_PA29\t\t\t29\n+#define PIN_PA29__GPIO\t\t\tPINMUX_PIN(PIN_PA29, 0, 0)\n+#define PIN_PA29__G0_RX3\t\tPINMUX_PIN(PIN_PA29, 1, 1)\n+#define PIN_PA29__FLEXCOM5_IO1\t\tPINMUX_PIN(PIN_PA29, 2, 1)\n+#define PIN_PA29__ISC_D9\t\tPINMUX_PIN(PIN_PA29, 3, 1)\n+#define PIN_PA29__A15\t\t\tPINMUX_PIN(PIN_PA29, 4, 1)\n+#define PIN_PA29__RF0\t\t\tPINMUX_PIN(PIN_PA29, 5, 1)\n+#define PIN_PA29__FLEXCOM9_IO0\t\tPINMUX_PIN(PIN_PA29, 6, 3)\n+#define PIN_PA30\t\t\t30\n+#define PIN_PA30__GPIO\t\t\tPINMUX_PIN(PIN_PA30, 0, 0)\n+#define PIN_PA30__G0_RXCK\t\tPINMUX_PIN(PIN_PA30, 1, 1)\n+#define PIN_PA30__FLEXCOM6_IO4\t\tPINMUX_PIN(PIN_PA30, 2, 1)\n+#define PIN_PA30__ISC_D10\t\tPINMUX_PIN(PIN_PA30, 3, 1)\n+#define PIN_PA30__A16\t\t\tPINMUX_PIN(PIN_PA30, 4, 1)\n+#define PIN_PA30__RK0\t\t\tPINMUX_PIN(PIN_PA30, 5, 1)\n+#define PIN_PA30__FLEXCOM9_IO1\t\tPINMUX_PIN(PIN_PA30, 6, 3)\n+#define PIN_PA31\t\t\t31\n+#define PIN_PA31__GPIO\t\t\tPINMUX_PIN(PIN_PA31, 0, 0)\n+#define PIN_PA31__G0_TXER\t\tPINMUX_PIN(PIN_PA31, 1, 1)\n+#define PIN_PA31__FLEXCOM6_IO2\t\tPINMUX_PIN(PIN_PA31, 2, 1)\n+#define PIN_PA31__ISC_D11\t\tPINMUX_PIN(PIN_PA31, 3, 1)\n+#define PIN_PA31__A17\t\t\tPINMUX_PIN(PIN_PA31, 4, 1)\n+#define PIN_PA31__TD0\t\t\tPINMUX_PIN(PIN_PA31, 5, 1)\n+#define PIN_PA31__FLEXCOM10_IO0\t\tPINMUX_PIN(PIN_PA31, 6, 3)\n+#define PIN_PB0\t\t\t\t32\n+#define PIN_PB0__GPIO\t\t\tPINMUX_PIN(PIN_PB0, 0, 0)\n+#define PIN_PB0__G0_COL\t\t\tPINMUX_PIN(PIN_PB0, 1, 1)\n+#define PIN_PB0__FLEXCOM6_IO3\t\tPINMUX_PIN(PIN_PB0, 2, 2)\n+#define PIN_PB0__EXT_IRQ0\t\tPINMUX_PIN(PIN_PB0, 3, 1)\n+#define PIN_PB0__A18\t\t\tPINMUX_PIN(PIN_PB0, 4, 1)\n+#define PIN_PB0__SPDIF_RX\t\tPINMUX_PIN(PIN_PB0, 5, 2)\n+#define PIN_PB0__FLEXCOM10_IO1\t\tPINMUX_PIN(PIN_PB0, 6, 3)\n+#define PIN_PB1\t\t\t\t33\n+#define PIN_PB1__GPIO\t\t\tPINMUX_PIN(PIN_PB1, 0, 0)\n+#define PIN_PB1__G0_CRS\t\t\tPINMUX_PIN(PIN_PB1, 1, 1)\n+#define PIN_PB1__FLEXCOM6_IO1\t\tPINMUX_PIN(PIN_PB1, 2, 2)\n+#define PIN_PB1__EXT_IRQ1\t\tPINMUX_PIN(PIN_PB1, 3, 1)\n+#define PIN_PB1__A19\t\t\tPINMUX_PIN(PIN_PB1, 4, 1)\n+#define PIN_PB1__SPDIF_TX\t\tPINMUX_PIN(PIN_PB1, 5, 2)\n+#define PIN_PB1__FLEXCOM11_IO0\t\tPINMUX_PIN(PIN_PB1, 6, 3)\n+#define PIN_PB2\t\t\t\t34\n+#define PIN_PB2__GPIO\t\t\tPINMUX_PIN(PIN_PB2, 0, 0)\n+#define PIN_PB2__G0_TSUCOMP\t\tPINMUX_PIN(PIN_PB2, 1, 1)\n+#define PIN_PB2__FLEXCOM6_IO0\t\tPINMUX_PIN(PIN_PB2, 2, 1)\n+#define PIN_PB2__ADTRG\t\t\tPINMUX_PIN(PIN_PB2, 3, 1)\n+#define PIN_PB2__A20\t\t\tPINMUX_PIN(PIN_PB2, 4, 1)\n+#define PIN_PB2__FLEXCOM11_IO0\t\tPINMUX_PIN(PIN_PB2, 6, 3)\n+#define PIN_PB3\t\t\t\t35\n+#define PIN_PB3__GPIO\t\t\tPINMUX_PIN(PIN_PB3, 0, 0)\n+#define PIN_PB3__RF1\t\t\tPINMUX_PIN(PIN_PB3, 1, 1)\n+#define PIN_PB3__FLEXCOM11_IO0\t\tPINMUX_PIN(PIN_PB3, 2, 1)\n+#define PIN_PB3__PCK2\t\t\tPINMUX_PIN(PIN_PB3, 3, 2)\n+#define PIN_PB3__D8\t\t\tPINMUX_PIN(PIN_PB3, 4, 1)\n+#define PIN_PB4\t\t\t\t36\n+#define PIN_PB4__GPIO\t\t\tPINMUX_PIN(PIN_PB4, 0, 0)\n+#define PIN_PB4__TF1\t\t\tPINMUX_PIN(PIN_PB4, 1, 1)\n+#define PIN_PB4__FLEXCOM11_IO1\t\tPINMUX_PIN(PIN_PB4, 2, 1)\n+#define PIN_PB4__PCK3\t\t\tPINMUX_PIN(PIN_PB4, 3, 2)\n+#define PIN_PB4__D9\t\t\tPINMUX_PIN(PIN_PB4, 4, 1)\n+#define PIN_PB5\t\t\t\t37\n+#define PIN_PB5__GPIO\t\t\tPINMUX_PIN(PIN_PB5, 0, 0)\n+#define PIN_PB5__TK1\t\t\tPINMUX_PIN(PIN_PB5, 1, 1)\n+#define PIN_PB5__FLEXCOM11_IO2\t\tPINMUX_PIN(PIN_PB5, 2, 1)\n+#define PIN_PB5__PCK4\t\t\tPINMUX_PIN(PIN_PB5, 3, 2)\n+#define PIN_PB5__D10\t\t\tPINMUX_PIN(PIN_PB5, 4, 1)\n+#define PIN_PB6\t\t\t\t38\n+#define PIN_PB6__GPIO\t\t\tPINMUX_PIN(PIN_PB6, 0, 0)\n+#define PIN_PB6__RK1\t\t\tPINMUX_PIN(PIN_PB6, 1, 1)\n+#define PIN_PB6__FLEXCOM11_IO3\t\tPINMUX_PIN(PIN_PB6, 2, 1)\n+#define PIN_PB6__PCK5\t\t\tPINMUX_PIN(PIN_PB6, 3, 2)\n+#define PIN_PB6__D11\t\t\tPINMUX_PIN(PIN_PB6, 4, 1)\n+#define PIN_PB7\t\t\t\t39\n+#define PIN_PB7__GPIO\t\t\tPINMUX_PIN(PIN_PB7, 0, 0)\n+#define PIN_PB7__TD1\t\t\tPINMUX_PIN(PIN_PB7, 1, 1)\n+#define PIN_PB7__FLEXCOM11_IO4\t\tPINMUX_PIN(PIN_PB7, 2, 1)\n+#define PIN_PB7__FLEXCOM3_IO5\t\tPINMUX_PIN(PIN_PB7, 3, 2)\n+#define PIN_PB7__D12\t\t\tPINMUX_PIN(PIN_PB7, 4, 1)\n+#define PIN_PB8\t\t\t\t40\n+#define PIN_PB8__GPIO\t\t\tPINMUX_PIN(PIN_PB8, 0, 0)\n+#define PIN_PB8__RD1\t\t\tPINMUX_PIN(PIN_PB8, 1, 1)\n+#define PIN_PB8__FLEXCOM8_IO0\t\tPINMUX_PIN(PIN_PB8, 2, 1)\n+#define PIN_PB8__FLEXCOM3_IO6\t\tPINMUX_PIN(PIN_PB8, 3, 2)\n+#define PIN_PB8__D13\t\t\tPINMUX_PIN(PIN_PB8, 4, 1)\n+#define PIN_PB9\t\t\t\t41\n+#define PIN_PB9__GPIO\t\t\tPINMUX_PIN(PIN_PB9, 0, 0)\n+#define PIN_PB9__QSPI0_IO3\t\tPINMUX_PIN(PIN_PB9, 1, 1)\n+#define PIN_PB9__FLEXCOM8_IO1\t\tPINMUX_PIN(PIN_PB9, 2, 1)\n+#define PIN_PB9__PDMC0_CLK\t\tPINMUX_PIN(PIN_PB9, 3, 1)\n+#define PIN_PB9__NCS3_NANDCS\t\tPINMUX_PIN(PIN_PB9, 4, 1)\n+#define PIN_PB9__PWML0\t\t\tPINMUX_PIN(PIN_PB9, 5, 2)\n+#define PIN_PB10\t\t\t42\n+#define PIN_PB10__GPIO\t\t\tPINMUX_PIN(PIN_PB10, 0, 0)\n+#define PIN_PB10__QSPI0_IO2\t\tPINMUX_PIN(PIN_PB10, 1, 1)\n+#define PIN_PB10__FLEXCOM8_IO2\t\tPINMUX_PIN(PIN_PB10, 2, 1)\n+#define PIN_PB10__PDMC0_DS0\t\tPINMUX_PIN(PIN_PB10, 3, 1)\n+#define PIN_PB10__NWE_NWR0_NANDWE\tPINMUX_PIN(PIN_PB10, 4, 1)\n+#define PIN_PB10__PWMH0\t\t\tPINMUX_PIN(PIN_PB10, 5, 2)\n+#define PIN_PB11\t\t\t43\n+#define PIN_PB11__GPIO\t\t\tPINMUX_PIN(PIN_PB11, 0, 0)\n+#define PIN_PB11__QSPI0_IO1\t\tPINMUX_PIN(PIN_PB11, 1, 1)\n+#define PIN_PB11__FLEXCOM8_IO3\t\tPINMUX_PIN(PIN_PB11, 2, 1)\n+#define PIN_PB11__PDMC0_DS1\t\tPINMUX_PIN(PIN_PB11, 3, 1)\n+#define PIN_PB11__NRD_NANDOE\t\tPINMUX_PIN(PIN_PB11, 4, 1)\n+#define PIN_PB11__PWML1\t\t\tPINMUX_PIN(PIN_PB11, 5, 2)\n+#define PIN_PB12\t\t\t44\n+#define PIN_PB12__GPIO\t\t\tPINMUX_PIN(PIN_PB12, 0, 0)\n+#define PIN_PB12__QSPI0_IO0\t\tPINMUX_PIN(PIN_PB12, 1, 1)\n+#define PIN_PB12__FLEXCOM8_IO4\t\tPINMUX_PIN(PIN_PB12, 2, 1)\n+#define PIN_PB12__FLEXCOM6_IO5\t\tPINMUX_PIN(PIN_PB12, 3, 1)\n+#define PIN_PB12__A21_NANDALE\t\tPINMUX_PIN(PIN_PB12, 4, 1)\n+#define PIN_PB12__PWMH1\t\t\tPINMUX_PIN(PIN_PB12, 5, 2)\n+#define PIN_PB13\t\t\t45\n+#define PIN_PB13__GPIO\t\t\tPINMUX_PIN(PIN_PB13, 0, 0)\n+#define PIN_PB13__QSPI0_CS\t\tPINMUX_PIN(PIN_PB13, 1, 1)\n+#define PIN_PB13__FLEXCOM9_IO0\t\tPINMUX_PIN(PIN_PB13, 2, 1)\n+#define PIN_PB13__FLEXCOM6_IO6\t\tPINMUX_PIN(PIN_PB13, 3, 1)\n+#define PIN_PB13__A22_NANDCLE\t\tPINMUX_PIN(PIN_PB13, 4, 1)\n+#define PIN_PB13__PWML2\t\t\tPINMUX_PIN(PIN_PB13, 5, 2)\n+#define PIN_PB14\t\t\t46\n+#define PIN_PB14__GPIO\t\t\tPINMUX_PIN(PIN_PB14, 0, 0)\n+#define PIN_PB14__QSPI0_SCK\t\tPINMUX_PIN(PIN_PB14, 1, 1)\n+#define PIN_PB14__FLEXCOM9_IO1\t\tPINMUX_PIN(PIN_PB14, 2, 1)\n+#define PIN_PB14__D0\t\t\tPINMUX_PIN(PIN_PB14, 4, 1)\n+#define PIN_PB14__PWMH2\t\t\tPINMUX_PIN(PIN_PB14, 5, 2)\n+#define PIN_PB15\t\t\t47\n+#define PIN_PB15__GPIO\t\t\tPINMUX_PIN(PIN_PB15, 0, 0)\n+#define PIN_PB15__QSPI0_SCKN\t\tPINMUX_PIN(PIN_PB15, 1, 1)\n+#define PIN_PB15__FLEXCOM9_IO2\t\tPINMUX_PIN(PIN_PB15, 2, 1)\n+#define PIN_PB15__D1\t\t\tPINMUX_PIN(PIN_PB15, 4, 1)\n+#define PIN_PB15__PWML3\t\t\tPINMUX_PIN(PIN_PB15, 5, 2)\n+#define PIN_PB16\t\t\t48\n+#define PIN_PB16__GPIO\t\t\tPINMUX_PIN(PIN_PB16, 0, 0)\n+#define PIN_PB16__QSPI0_IO4\t\tPINMUX_PIN(PIN_PB16, 1, 1)\n+#define PIN_PB16__FLEXCOM9_IO3\t\tPINMUX_PIN(PIN_PB16, 2, 1)\n+#define PIN_PB16__PCK0\t\t\tPINMUX_PIN(PIN_PB16, 3, 1)\n+#define PIN_PB16__D2\t\t\tPINMUX_PIN(PIN_PB16, 4, 1)\n+#define PIN_PB16__PWMH3\t\t\tPINMUX_PIN(PIN_PB16, 5, 2)\n+#define PIN_PB16__EXT_IRQ0\t\tPINMUX_PIN(PIN_PB16, 6, 2)\n+#define PIN_PB17\t\t\t49\n+#define PIN_PB17__GPIO\t\t\tPINMUX_PIN(PIN_PB17, 0, 0)\n+#define PIN_PB17__QSPI0_IO5\t\tPINMUX_PIN(PIN_PB17, 1, 1)\n+#define PIN_PB17__FLEXCOM9_IO4\t\tPINMUX_PIN(PIN_PB17, 2, 1)\n+#define PIN_PB17__PCK1\t\t\tPINMUX_PIN(PIN_PB17, 3, 1)\n+#define PIN_PB17__D3\t\t\tPINMUX_PIN(PIN_PB17, 4, 1)\n+#define PIN_PB17__PWMEXTRG0\t\tPINMUX_PIN(PIN_PB17, 5, 2)\n+#define PIN_PB17__EXT_IRQ1\t\tPINMUX_PIN(PIN_PB17, 6, 2)\n+#define PIN_PB18\t\t\t50\n+#define PIN_PB18__GPIO\t\t\tPINMUX_PIN(PIN_PB18, 0, 0)\n+#define PIN_PB18__QSPI0_IO6\t\tPINMUX_PIN(PIN_PB18, 1, 1)\n+#define PIN_PB18__FLEXCOM10_IO0\t\tPINMUX_PIN(PIN_PB18, 2, 1)\n+#define PIN_PB18__PCK2\t\t\tPINMUX_PIN(PIN_PB18, 3, 1)\n+#define PIN_PB18__D4\t\t\tPINMUX_PIN(PIN_PB18, 4, 1)\n+#define PIN_PB18__PWMEXTRG1\t\tPINMUX_PIN(PIN_PB18, 5, 2)\n+#define PIN_PB19\t\t\t51\n+#define PIN_PB19__GPIO\t\t\tPINMUX_PIN(PIN_PB19, 0, 0)\n+#define PIN_PB19__QSPI0_IO7\t\tPINMUX_PIN(PIN_PB19, 1, 1)\n+#define PIN_PB19__FLEXCOM10_IO1\t\tPINMUX_PIN(PIN_PB19, 2, 1)\n+#define PIN_PB19__PCK3\t\t\tPINMUX_PIN(PIN_PB19, 3, 1)\n+#define PIN_PB19__D5\t\t\tPINMUX_PIN(PIN_PB19, 4, 1)\n+#define PIN_PB19__PWMFI0\t\tPINMUX_PIN(PIN_PB19, 5, 2)\n+#define PIN_PB20\t\t\t52\n+#define PIN_PB20__GPIO\t\t\tPINMUX_PIN(PIN_PB20, 0, 0)\n+#define PIN_PB20__QSPI0_DQS\t\tPINMUX_PIN(PIN_PB20, 1, 1)\n+#define PIN_PB20__FLEXCOM10_IO2\t\tPINMUX_PIN(PIN_PB20, 2, 1)\n+#define PIN_PB20__D6\t\t\tPINMUX_PIN(PIN_PB20, 4, 1)\n+#define PIN_PB20__PWMFI1\t\tPINMUX_PIN(PIN_PB20, 5, 2)\n+#define PIN_PB21\t\t\t53\n+#define PIN_PB21__GPIO\t\t\tPINMUX_PIN(PIN_PB21, 0, 0)\n+#define PIN_PB21__QSPI0_INT\t\tPINMUX_PIN(PIN_PB21, 1, 1)\n+#define PIN_PB21__FLEXCOM10_IO3\t\tPINMUX_PIN(PIN_PB21, 2, 1)\n+#define PIN_PB21__FLEXCOM9_IO5\t\tPINMUX_PIN(PIN_PB21, 3, 1)\n+#define PIN_PB21__D7\t\t\tPINMUX_PIN(PIN_PB21, 4, 1)\n+#define PIN_PB22\t\t\t54\n+#define PIN_PB22__GPIO\t\t\tPINMUX_PIN(PIN_PB22, 0, 0)\n+#define PIN_PB22__QSPI1_IO3\t\tPINMUX_PIN(PIN_PB22, 1, 1)\n+#define PIN_PB22__FLEXCOM10_IO4\t\tPINMUX_PIN(PIN_PB22, 2, 1)\n+#define PIN_PB22__FLEXCOM9_IO6\t\tPINMUX_PIN(PIN_PB22, 3, 1)\n+#define PIN_PB22__NANDRDY\t\tPINMUX_PIN(PIN_PB22, 4, 1)\n+#define PIN_PB23\t\t\t55\n+#define PIN_PB23__GPIO\t\t\tPINMUX_PIN(PIN_PB23, 0, 0)\n+#define PIN_PB23__QSPI1_IO2\t\tPINMUX_PIN(PIN_PB23, 1, 1)\n+#define PIN_PB23__FLEXCOM7_IO0\t\tPINMUX_PIN(PIN_PB23, 2, 1)\n+#define PIN_PB23__I2SMCC0_CK\t\tPINMUX_PIN(PIN_PB23, 3, 1)\n+#define PIN_PB23__PCK4\t\t\tPINMUX_PIN(PIN_PB23, 6, 1)\n+#define PIN_PB24\t\t\t56\n+#define PIN_PB24__GPIO\t\t\tPINMUX_PIN(PIN_PB24, 0, 0)\n+#define PIN_PB24__QSPI1_IO1\t\tPINMUX_PIN(PIN_PB24, 1, 1)\n+#define PIN_PB24__FLEXCOM7_IO1\t\tPINMUX_PIN(PIN_PB24, 2, 1)\n+#define PIN_PB24__I2SMCC0_WS\t\tPINMUX_PIN(PIN_PB24, 3, 1)\n+#define PIN_PB24__PCK5\t\t\tPINMUX_PIN(PIN_PB24, 6, 1)\n+#define PIN_PB25\t\t\t57\n+#define PIN_PB25__GPIO\t\t\tPINMUX_PIN(PIN_PB25, 0, 0)\n+#define PIN_PB25__QSPI1_IO0\t\tPINMUX_PIN(PIN_PB25, 1, 1)\n+#define PIN_PB25__FLEXCOM7_IO2\t\tPINMUX_PIN(PIN_PB25, 2, 1)\n+#define PIN_PB25__I2SMCC0_DOUT1\t\tPINMUX_PIN(PIN_PB25, 3, 1)\n+#define PIN_PB25__PCK6\t\t\tPINMUX_PIN(PIN_PB25, 6, 1)\n+#define PIN_PB26\t\t\t58\n+#define PIN_PB26__GPIO\t\t\tPINMUX_PIN(PIN_PB26, 0, 0)\n+#define PIN_PB26__QSPI1_CS\t\tPINMUX_PIN(PIN_PB26, 1, 1)\n+#define PIN_PB26__FLEXCOM7_IO3\t\tPINMUX_PIN(PIN_PB26, 2, 1)\n+#define PIN_PB26__I2SMCC0_DOUT0\t\tPINMUX_PIN(PIN_PB26, 3, 1)\n+#define PIN_PB26__PWMEXTRG0\t\tPINMUX_PIN(PIN_PB26, 5, 1)\n+#define PIN_PB26__PCK7\t\t\tPINMUX_PIN(PIN_PB26, 6, 1)\n+#define PIN_PB27\t\t\t59\n+#define PIN_PB27__GPIO\t\t\tPINMUX_PIN(PIN_PB27, 0, 0)\n+#define PIN_PB27__QSPI1_SCK\t\tPINMUX_PIN(PIN_PB27, 1, 1)\n+#define PIN_PB27__FLEXCOM7_IO4\t\tPINMUX_PIN(PIN_PB27, 2, 1)\n+#define PIN_PB27__I2SMCC0_MCK\t\tPINMUX_PIN(PIN_PB27, 3, 1)\n+#define PIN_PB27__PWMEXTRG1\t\tPINMUX_PIN(PIN_PB27, 5, 1)\n+#define PIN_PB28\t\t\t60\n+#define PIN_PB28__GPIO\t\t\tPINMUX_PIN(PIN_PB28, 0, 0)\n+#define PIN_PB28__SDMMC1_RSTN\t\tPINMUX_PIN(PIN_PB28, 1, 1)\n+#define PIN_PB28__ADTRG\t\t\tPINMUX_PIN(PIN_PB28, 2, 2)\n+#define PIN_PB28__PWMFI0\t\tPINMUX_PIN(PIN_PB28, 5, 1)\n+#define PIN_PB28__FLEXCOM7_IO0\t\tPINMUX_PIN(PIN_PB28, 6, 4)\n+#define PIN_PB29\t\t\t61\n+#define PIN_PB29__GPIO\t\t\tPINMUX_PIN(PIN_PB29, 0, 0)\n+#define PIN_PB29__SDMMC1_CMD\t\tPINMUX_PIN(PIN_PB29, 1, 1)\n+#define PIN_PB29__FLEXCOM3_IO2\t\tPINMUX_PIN(PIN_PB29, 2, 2)\n+#define PIN_PB29__FLEXCOM0_IO5\t\tPINMUX_PIN(PIN_PB29, 3, 2)\n+#define PIN_PB29__TIOA3\t\t\tPINMUX_PIN(PIN_PB29, 4, 2)\n+#define PIN_PB29__PWMFI1\t\tPINMUX_PIN(PIN_PB29, 5, 1)\n+#define PIN_PB29__FLEXCOM7_IO1\t\tPINMUX_PIN(PIN_PB29, 6, 4)\n+#define PIN_PB30\t\t\t62\n+#define PIN_PB30__GPIO\t\t\tPINMUX_PIN(PIN_PB30, 0, 0)\n+#define PIN_PB30__SDMMC1_CK\t\tPINMUX_PIN(PIN_PB30, 1, 1)\n+#define PIN_PB30__FLEXCOM3_IO3\t\tPINMUX_PIN(PIN_PB30, 2, 2)\n+#define PIN_PB30__FLEXCOM0_IO6\t\tPINMUX_PIN(PIN_PB30, 3, 2)\n+#define PIN_PB30__TIOB3\t\t\tPINMUX_PIN(PIN_PB30, 4, 1)\n+#define PIN_PB30__PWMH0\t\t\tPINMUX_PIN(PIN_PB30, 5, 1)\n+#define PIN_PB30__FLEXCOM8_IO0\t\tPINMUX_PIN(PIN_PB30, 6, 4)\n+#define PIN_PB31\t\t\t63\n+#define PIN_PB31__GPIO\t\t\tPINMUX_PIN(PIN_PB31, 0, 0)\n+#define PIN_PB31__SDMMC1_DAT0\t\tPINMUX_PIN(PIN_PB31, 1, 1)\n+#define PIN_PB31__FLEXCOM3_IO4\t\tPINMUX_PIN(PIN_PB31, 2, 2)\n+#define PIN_PB31__FLEXCOM9_IO5\t\tPINMUX_PIN(PIN_PB31, 3, 2)\n+#define PIN_PB31__TCLK3\t\t\tPINMUX_PIN(PIN_PB31, 4, 1)\n+#define PIN_PB31__PWML0\t\t\tPINMUX_PIN(PIN_PB31, 5, 1)\n+#define PIN_PB31__FLEXCOM8_IO1\t\tPINMUX_PIN(PIN_PB31, 6, 4)\n+#define PIN_PC0\t\t\t\t64\n+#define PIN_PC0__GPIO\t\t\tPINMUX_PIN(PIN_PC0, 0, 0)\n+#define PIN_PC0__SDMMC1_DAT1\t\tPINMUX_PIN(PIN_PC0, 1, 1)\n+#define PIN_PC0__FLEXCOM3_IO0\t\tPINMUX_PIN(PIN_PC0, 2, 2)\n+#define PIN_PC0__TIOA4\t\t\tPINMUX_PIN(PIN_PC0, 4, 1)\n+#define PIN_PC0__PWML1\t\t\tPINMUX_PIN(PIN_PC0, 5, 1)\n+#define PIN_PC0__FLEXCOM9_IO0\t\tPINMUX_PIN(PIN_PC0, 6, 4)\n+#define PIN_PC1\t\t\t\t65\n+#define PIN_PC1__GPIO\t\t\tPINMUX_PIN(PIN_PC1, 0, 0)\n+#define PIN_PC1__SDMMC1_DAT2\t\tPINMUX_PIN(PIN_PC1, 1, 1)\n+#define PIN_PC1__FLEXCOM3_IO1\t\tPINMUX_PIN(PIN_PC1, 2, 2)\n+#define PIN_PC1__TIOB4\t\t\tPINMUX_PIN(PIN_PC1, 4, 1)\n+#define PIN_PC1__PWMH1\t\t\tPINMUX_PIN(PIN_PC1, 5, 1)\n+#define PIN_PC1__FLEXCOM9_IO1\t\tPINMUX_PIN(PIN_PC1, 6, 4)\n+#define PIN_PC2\t\t\t\t66\n+#define PIN_PC2__GPIO\t\t\tPINMUX_PIN(PIN_PC2, 0, 0)\n+#define PIN_PC2__SDMMC1_DAT3\t\tPINMUX_PIN(PIN_PC2, 1, 1)\n+#define PIN_PC2__FLEXCOM4_IO0\t\tPINMUX_PIN(PIN_PC2, 2, 2)\n+#define PIN_PC2__TCLK4\t\t\tPINMUX_PIN(PIN_PC2, 4, 1)\n+#define PIN_PC2__PWML2\t\t\tPINMUX_PIN(PIN_PC2, 5, 1)\n+#define PIN_PC2__FLEXCOM10_IO0\t\tPINMUX_PIN(PIN_PC2, 6, 4)\n+#define PIN_PC3\t\t\t\t67\n+#define PIN_PC3__GPIO\t\t\tPINMUX_PIN(PIN_PC3, 0, 0)\n+#define PIN_PC3__SDMMC1_WP\t\tPINMUX_PIN(PIN_PC3, 1, 1)\n+#define PIN_PC3__FLEXCOM4_IO1\t\tPINMUX_PIN(PIN_PC3, 2, 2)\n+#define PIN_PC3__TIOA5\t\t\tPINMUX_PIN(PIN_PC3, 4, 1)\n+#define PIN_PC3__PWMH2\t\t\tPINMUX_PIN(PIN_PC3, 5, 1)\n+#define PIN_PC3__FLEXCOM10_IO1\t\tPINMUX_PIN(PIN_PC3, 6, 4)\n+#define PIN_PC4\t\t\t\t68\n+#define PIN_PC4__GPIO\t\t\tPINMUX_PIN(PIN_PC4, 0, 0)\n+#define PIN_PC4__SDMMC1_CD\t\tPINMUX_PIN(PIN_PC4, 1, 1)\n+#define PIN_PC4__FLEXCOM4_IO2\t\tPINMUX_PIN(PIN_PC4, 2, 2)\n+#define PIN_PC4__FLEXCOM9_IO6\t\tPINMUX_PIN(PIN_PC4, 3, 2)\n+#define PIN_PC4__TIOB5\t\t\tPINMUX_PIN(PIN_PC4, 4, 1)\n+#define PIN_PC4__PWML3\t\t\tPINMUX_PIN(PIN_PC4, 5, 1)\n+#define PIN_PC4__FLEXCOM11_IO0\t\tPINMUX_PIN(PIN_PC4, 6, 4)\n+#define PIN_PC5\t\t\t\t69\n+#define PIN_PC5__GPIO\t\t\tPINMUX_PIN(PIN_PC5, 0, 0)\n+#define PIN_PC5__SDMMC1_1V8SEL\t\tPINMUX_PIN(PIN_PC5, 1, 1)\n+#define PIN_PC5__FLEXCOM4_IO3\t\tPINMUX_PIN(PIN_PC5, 2, 2)\n+#define PIN_PC5__FLEXCOM6_IO5\t\tPINMUX_PIN(PIN_PC5, 3, 2)\n+#define PIN_PC5__TCLK5\t\t\tPINMUX_PIN(PIN_PC5, 4, 1)\n+#define PIN_PC5__PWMH3\t\t\tPINMUX_PIN(PIN_PC5, 5, 1)\n+#define PIN_PC5__FLEXCOM11_IO1\t\tPINMUX_PIN(PIN_PC5, 6, 4)\n+#define PIN_PC6\t\t\t\t70\n+#define PIN_PC6__GPIO\t\t\tPINMUX_PIN(PIN_PC6, 0, 0)\n+#define PIN_PC6__FLEXCOM4_IO4\t\tPINMUX_PIN(PIN_PC6, 2, 2)\n+#define PIN_PC6__FLEXCOM6_IO6\t\tPINMUX_PIN(PIN_PC6, 3, 2)\n+#define PIN_PC7\t\t\t\t71\n+#define PIN_PC7__GPIO\t\t\tPINMUX_PIN(PIN_PC7, 0, 0)\n+#define PIN_PC7__I2SMCC0_DIN0\t\tPINMUX_PIN(PIN_PC7, 1, 1)\n+#define PIN_PC7__FLEXCOM7_IO0\t\tPINMUX_PIN(PIN_PC7, 2, 2)\n+#define PIN_PC8\t\t\t\t72\n+#define PIN_PC8__GPIO\t\t\tPINMUX_PIN(PIN_PC8, 0, 0)\n+#define PIN_PC8__I2SMCC0_DIN1\t\tPINMUX_PIN(PIN_PC8, 1, 1)\n+#define PIN_PC8__FLEXCOM7_IO1\t\tPINMUX_PIN(PIN_PC8, 2, 2)\n+#define PIN_PC9\t\t\t\t73\n+#define PIN_PC9__GPIO\t\t\tPINMUX_PIN(PIN_PC9, 0, 0)\n+#define PIN_PC9__I2SMCC0_DOUT3\t\tPINMUX_PIN(PIN_PC9, 1, 1)\n+#define PIN_PC9__FLEXCOM7_IO2\t\tPINMUX_PIN(PIN_PC9, 2, 2)\n+#define PIN_PC9__FLEXCOM1_IO0\t\tPINMUX_PIN(PIN_PC9, 6, 4)\n+#define PIN_PC10\t\t\t74\n+#define PIN_PC10__GPIO\t\t\tPINMUX_PIN(PIN_PC10, 0, 0)\n+#define PIN_PC10__I2SMCC0_DOUT2\t\tPINMUX_PIN(PIN_PC10, 1, 1)\n+#define PIN_PC10__FLEXCOM7_IO3\t\tPINMUX_PIN(PIN_PC10, 2, 2)\n+#define PIN_PC10__FLEXCOM1_IO1\t\tPINMUX_PIN(PIN_PC10, 6, 4)\n+#define PIN_PC11\t\t\t75\n+#define PIN_PC11__GPIO\t\t\tPINMUX_PIN(PIN_PC11, 0, 0)\n+#define PIN_PC11__I2SMCC1_CK\t\tPINMUX_PIN(PIN_PC11, 1, 1)\n+#define PIN_PC11__FLEXCOM7_IO4\t\tPINMUX_PIN(PIN_PC11, 2, 2)\n+#define PIN_PC11__FLEXCOM2_IO0\t\tPINMUX_PIN(PIN_PC11, 6, 4)\n+#define PIN_PC12\t\t\t76\n+#define PIN_PC12__GPIO\t\t\tPINMUX_PIN(PIN_PC12, 0, 0)\n+#define PIN_PC12__I2SMCC1_WS\t\tPINMUX_PIN(PIN_PC12, 1, 1)\n+#define PIN_PC12__FLEXCOM8_IO2\t\tPINMUX_PIN(PIN_PC12, 2, 2)\n+#define PIN_PC12__FLEXCOM2_IO1\t\tPINMUX_PIN(PIN_PC12, 6, 4)\n+#define PIN_PC13\t\t\t77\n+#define PIN_PC13__GPIO\t\t\tPINMUX_PIN(PIN_PC13, 0, 0)\n+#define PIN_PC13__I2SMCC1_MCK\t\tPINMUX_PIN(PIN_PC13, 1, 1)\n+#define PIN_PC13__FLEXCOM8_IO1\t\tPINMUX_PIN(PIN_PC13, 2, 2)\n+#define PIN_PC13__FLEXCOM3_IO0\t\tPINMUX_PIN(PIN_PC13, 6, 4)\n+#define PIN_PC14\t\t\t78\n+#define PIN_PC14__GPIO\t\t\tPINMUX_PIN(PIN_PC14, 0, 0)\n+#define PIN_PC14__I2SMCC1_DOUT0\t\tPINMUX_PIN(PIN_PC14, 1, 1)\n+#define PIN_PC14__FLEXCOM8_IO0\t\tPINMUX_PIN(PIN_PC14, 2, 2)\n+#define PIN_PC14__FLEXCOM3_IO1\t\tPINMUX_PIN(PIN_PC14, 6, 4)\n+#define PIN_PC15\t\t\t79\n+#define PIN_PC15__GPIO\t\t\tPINMUX_PIN(PIN_PC15, 0, 0)\n+#define PIN_PC15__I2SMCC1_DOUT1\t\tPINMUX_PIN(PIN_PC15, 1, 1)\n+#define PIN_PC15__FLEXCOM8_IO3\t\tPINMUX_PIN(PIN_PC15, 2, 2)\n+#define PIN_PC15__FLEXCOM4_IO0\t\tPINMUX_PIN(PIN_PC15, 6, 4)\n+#define PIN_PC16\t\t\t80\n+#define PIN_PC16__GPIO\t\t\tPINMUX_PIN(PIN_PC16, 0, 0)\n+#define PIN_PC16__I2SMCC1_DOUT2\t\tPINMUX_PIN(PIN_PC16, 1, 1)\n+#define PIN_PC16__FLEXCOM8_IO4\t\tPINMUX_PIN(PIN_PC16, 2, 2)\n+#define PIN_PC16__FLEXCOM3_IO1\t\tPINMUX_PIN(PIN_PC16, 6, 4)\n+#define PIN_PC17\t\t\t81\n+#define PIN_PC17__GPIO\t\t\tPINMUX_PIN(PIN_PC17, 0, 0)\n+#define PIN_PC17__I2SMCC1_DOUT3\t\tPINMUX_PIN(PIN_PC17, 1, 1)\n+#define PIN_PC17__EXT_IRQ0\t\tPINMUX_PIN(PIN_PC17, 2, 3)\n+#define PIN_PC17__FLEXCOM5_IO0\t\tPINMUX_PIN(PIN_PC17, 6, 4)\n+#define PIN_PC18\t\t\t82\n+#define PIN_PC18__GPIO\t\t\tPINMUX_PIN(PIN_PC18, 0, 0)\n+#define PIN_PC18__I2SMCC1_DIN0\t\tPINMUX_PIN(PIN_PC18, 1, 1)\n+#define PIN_PC18__FLEXCOM9_IO0\t\tPINMUX_PIN(PIN_PC18, 2, 2)\n+#define PIN_PC18__FLEXCOM5_IO1\t\tPINMUX_PIN(PIN_PC18, 6, 4)\n+#define PIN_PC19\t\t\t83\n+#define PIN_PC19__GPIO\t\t\tPINMUX_PIN(PIN_PC19, 0, 0)\n+#define PIN_PC19__I2SMCC1_DIN1\t\tPINMUX_PIN(PIN_PC19, 1, 1)\n+#define PIN_PC19__FLEXCOM9_IO1\t\tPINMUX_PIN(PIN_PC19, 2, 2)\n+#define PIN_PC19__FLEXCOM6_IO0\t\tPINMUX_PIN(PIN_PC19, 6, 4)\n+#define PIN_PC20\t\t\t84\n+#define PIN_PC20__GPIO\t\t\tPINMUX_PIN(PIN_PC20, 0, 0)\n+#define PIN_PC20__I2SMCC1_DIN2\t\tPINMUX_PIN(PIN_PC20, 1, 1)\n+#define PIN_PC20__FLEXCOM9_IO4\t\tPINMUX_PIN(PIN_PC20, 2, 2)\n+#define PIN_PC20__FLEXCOM6_IO1\t\tPINMUX_PIN(PIN_PC20, 6, 4)\n+#define PIN_PC21\t\t\t85\n+#define PIN_PC21__GPIO\t\t\tPINMUX_PIN(PIN_PC21, 0, 0)\n+#define PIN_PC21__I2SMCC1_DIN3\t\tPINMUX_PIN(PIN_PC21, 1, 1)\n+#define PIN_PC21__FLEXCOM9_IO2\t\tPINMUX_PIN(PIN_PC21, 2, 2)\n+#define PIN_PC21__D3\t\t\tPINMUX_PIN(PIN_PC21, 4, 2)\n+#define PIN_PC21__FLEXCOM6_IO0\t\tPINMUX_PIN(PIN_PC21, 6, 5)\n+#define PIN_PC22\t\t\t86\n+#define PIN_PC22__GPIO\t\t\tPINMUX_PIN(PIN_PC22, 0, 0)\n+#define PIN_PC22__I2SMCC0_DIN2\t\tPINMUX_PIN(PIN_PC22, 1, 1)\n+#define PIN_PC22__FLEXCOM9_IO3\t\tPINMUX_PIN(PIN_PC22, 2, 2)\n+#define PIN_PC22__D4\t\t\tPINMUX_PIN(PIN_PC22, 4, 2)\n+#define PIN_PC22__FLEXCOM6_IO1\t\tPINMUX_PIN(PIN_PC22, 6, 5)\n+#define PIN_PC23\t\t\t87\n+#define PIN_PC23__GPIO\t\t\tPINMUX_PIN(PIN_PC23, 0, 0)\n+#define PIN_PC23__I2SMCC0_DIN3\t\tPINMUX_PIN(PIN_PC23, 1, 1)\n+#define PIN_PC23__FLEXCOM0_IO5\t\tPINMUX_PIN(PIN_PC23, 2, 3)\n+#define PIN_PC23__D5\t\t\tPINMUX_PIN(PIN_PC23, 4, 2)\n+#define PIN_PC23__FLEXCOM7_IO0\t\tPINMUX_PIN(PIN_PC23, 6, 5)\n+#define PIN_PC24\t\t\t88\n+#define PIN_PC24__GPIO\t\t\tPINMUX_PIN(PIN_PC24, 0, 0)\n+#define PIN_PC24__FLEXCOM0_IO6\t\tPINMUX_PIN(PIN_PC24, 2, 3)\n+#define PIN_PC24__EXT_IRQ1\t\tPINMUX_PIN(PIN_PC24, 3, 3)\n+#define PIN_PC24__D6\t\t\tPINMUX_PIN(PIN_PC24, 4, 2)\n+#define PIN_PC24__FLEXCOM7_IO1\t\tPINMUX_PIN(PIN_PC24, 6, 5)\n+#define PIN_PC25\t\t\t89\n+#define PIN_PC25__GPIO\t\t\tPINMUX_PIN(PIN_PC25, 0, 0)\n+#define PIN_PC25__NTRST\t\t\tPINMUX_PIN(PIN_PC25, 1, 1)\n+#define PIN_PC26\t\t\t90\n+#define PIN_PC26__GPIO\t\t\tPINMUX_PIN(PIN_PC26, 0, 0)\n+#define PIN_PC26__TCK_SWCLK\t\tPINMUX_PIN(PIN_PC26, 1, 1)\n+#define PIN_PC27\t\t\t91\n+#define PIN_PC27__GPIO\t\t\tPINMUX_PIN(PIN_PC27, 0, 0)\n+#define PIN_PC27__TMS_SWDIO\t\tPINMUX_PIN(PIN_PC27, 1, 1)\n+#define PIN_PC28\t\t\t92\n+#define PIN_PC28__GPIO\t\t\tPINMUX_PIN(PIN_PC28, 0, 0)\n+#define PIN_PC28__TDI\t\t\tPINMUX_PIN(PIN_PC28, 1, 1)\n+#define PIN_PC29\t\t\t93\n+#define PIN_PC29__GPIO\t\t\tPINMUX_PIN(PIN_PC29, 0, 0)\n+#define PIN_PC29__TDO\t\t\tPINMUX_PIN(PIN_PC29, 1, 1)\n+#define PIN_PC30\t\t\t94\n+#define PIN_PC30__GPIO\t\t\tPINMUX_PIN(PIN_PC30, 0, 0)\n+#define PIN_PC30__FLEXCOM10_IO0\t\tPINMUX_PIN(PIN_PC30, 2, 2)\n+#define PIN_PC31\t\t\t95\n+#define PIN_PC31__GPIO\t\t\tPINMUX_PIN(PIN_PC31, 0, 0)\n+#define PIN_PC31__FLEXCOM10_IO1\t\tPINMUX_PIN(PIN_PC31, 2, 2)\n+#define PIN_PD0\t\t\t\t96\n+#define PIN_PD0__GPIO\t\t\tPINMUX_PIN(PIN_PD0, 0, 0)\n+#define PIN_PD0__FLEXCOM11_IO0\t\tPINMUX_PIN(PIN_PD0, 2, 2)\n+#define PIN_PD1\t\t\t\t97\n+#define PIN_PD1__GPIO\t\t\tPINMUX_PIN(PIN_PD1, 0, 0)\n+#define PIN_PD1__FLEXCOM11_IO1\t\tPINMUX_PIN(PIN_PD1, 2, 2)\n+#define PIN_PD2\t\t\t\t98\n+#define PIN_PD2__GPIO\t\t\tPINMUX_PIN(PIN_PD2, 0, 0)\n+#define PIN_PD2__SDMMC2_RSTN\t\tPINMUX_PIN(PIN_PD2, 1, 1)\n+#define PIN_PD2__PCK0\t\t\tPINMUX_PIN(PIN_PD2, 2, 2)\n+#define PIN_PD2__CANTX4\t\t\tPINMUX_PIN(PIN_PD2, 3, 1)\n+#define PIN_PD2__D7\t\t\tPINMUX_PIN(PIN_PD2, 4, 2)\n+#define PIN_PD2__TIOA0\t\t\tPINMUX_PIN(PIN_PD2, 5, 2)\n+#define PIN_PD2__FLEXCOM8_IO0\t\tPINMUX_PIN(PIN_PD2, 6, 5)\n+#define PIN_PD3\t\t\t\t99\n+#define PIN_PD3__GPIO\t\t\tPINMUX_PIN(PIN_PD3, 0, 0)\n+#define PIN_PD3__SDMMC2_CMD\t\tPINMUX_PIN(PIN_PD3, 1, 1)\n+#define PIN_PD3__FLEXCOM0_IO0\t\tPINMUX_PIN(PIN_PD3, 2, 2)\n+#define PIN_PD3__CANRX4\t\t\tPINMUX_PIN(PIN_PD3, 3, 1)\n+#define PIN_PD3__NANDRDY\t\tPINMUX_PIN(PIN_PD3, 4, 2)\n+#define PIN_PD3__TIOB0\t\t\tPINMUX_PIN(PIN_PD3, 5, 2)\n+#define PIN_PD3__FLEXCOM8_IO1\t\tPINMUX_PIN(PIN_PD3, 6, 5)\n+#define PIN_PD4\t\t\t\t100\n+#define PIN_PD4__GPIO\t\t\tPINMUX_PIN(PIN_PD4, 0, 0)\n+#define PIN_PD4__SDMMC2_CK\t\tPINMUX_PIN(PIN_PD4, 1, 1)\n+#define PIN_PD4__FLEXCOM0_IO1\t\tPINMUX_PIN(PIN_PD4, 2, 2)\n+#define PIN_PD4__CANTX5\t\t\tPINMUX_PIN(PIN_PD4, 3, 1)\n+#define PIN_PD4__NCS3_NANDCS\t\tPINMUX_PIN(PIN_PD4, 4, 2)\n+#define PIN_PD4__TCLK0\t\t\tPINMUX_PIN(PIN_PD4, 5, 2)\n+#define PIN_PD4__FLEXCOM9_IO0\t\tPINMUX_PIN(PIN_PD4, 6, 5)\n+#define PIN_PD5\t\t\t\t101\n+#define PIN_PD5__GPIO\t\t\tPINMUX_PIN(PIN_PD5, 0, 0)\n+#define PIN_PD5__SDMMC2_DAT0\t\tPINMUX_PIN(PIN_PD5, 1, 1)\n+#define PIN_PD5__FLEXCOM0_IO2\t\tPINMUX_PIN(PIN_PD5, 2, 2)\n+#define PIN_PD5__CANRX5\t\t\tPINMUX_PIN(PIN_PD5, 3, 1)\n+#define PIN_PD5__NWE_NWR0_NANDWE\tPINMUX_PIN(PIN_PD5, 4, 2)\n+#define PIN_PD5__TIOA1\t\t\tPINMUX_PIN(PIN_PD5, 5, 2)\n+#define PIN_PD5__FLEXCOM9_IO1\t\tPINMUX_PIN(PIN_PD5, 6, 5)\n+#define PIN_PD6\t\t\t\t102\n+#define PIN_PD6__GPIO\t\t\tPINMUX_PIN(PIN_PD6, 0, 0)\n+#define PIN_PD6__SDMMC2_DAT1\t\tPINMUX_PIN(PIN_PD6, 1, 1)\n+#define PIN_PD6__FLEXCOM0_IO3\t\tPINMUX_PIN(PIN_PD6, 2, 2)\n+#define PIN_PD6__SPDIF_RX\t\tPINMUX_PIN(PIN_PD6, 3, 3)\n+#define PIN_PD6__NRD_NANDOE\t\tPINMUX_PIN(PIN_PD6, 4, 2)\n+#define PIN_PD6__TIOB1\t\t\tPINMUX_PIN(PIN_PD6, 5, 2)\n+#define PIN_PD6__FLEXCOM10_IO0\t\tPINMUX_PIN(PIN_PD6, 6, 5)\n+#define PIN_PD7\t\t\t\t103\n+#define PIN_PD7__GPIO\t\t\tPINMUX_PIN(PIN_PD7, 0, 0)\n+#define PIN_PD7__SDMMC2_DAT2\t\tPINMUX_PIN(PIN_PD7, 1, 1)\n+#define PIN_PD7__FLEXCOM0_IO4\t\tPINMUX_PIN(PIN_PD7, 2, 2)\n+#define PIN_PD7__SPDIF_TX\t\tPINMUX_PIN(PIN_PD7, 2, 2)\n+#define PIN_PD7__A21_NANDALE\t\tPINMUX_PIN(PIN_PD7, 4, 2)\n+#define PIN_PD7__TCLK1\t\t\tPINMUX_PIN(PIN_PD7, 5, 2)\n+#define PIN_PD7__FLEXCOM10_IO1\t\tPINMUX_PIN(PIN_PD7, 6, 5)\n+#define PIN_PD8\t\t\t\t104\n+#define PIN_PD8__GPIO\t\t\tPINMUX_PIN(PIN_PD8, 0, 0)\n+#define PIN_PD8__SDMMC2_DAT3\t\tPINMUX_PIN(PIN_PD8, 1, 1)\n+#define PIN_PD8__I2SMCC0_DIN0\t\tPINMUX_PIN(PIN_PD8, 3, 1)\n+#define PIN_PD8__A11_NANDCLE\t\tPINMUX_PIN(PIN_PD8, 4, 2)\n+#define PIN_PD8__TIOA2\t\t\tPINMUX_PIN(PIN_PD8, 5, 2)\n+#define PIN_PD8__FLEXCOM11_IO0\t\tPINMUX_PIN(PIN_PD8, 6, 5)\n+#define PIN_PD9\t\t\t\t105\n+#define PIN_PD9__GPIO\t\t\tPINMUX_PIN(PIN_PD9, 0, 0)\n+#define PIN_PD9__SDMMC2_WP\t\tPINMUX_PIN(PIN_PD9, 1, 1)\n+#define PIN_PD9__I2SMCC0_DIN1\t\tPINMUX_PIN(PIN_PD9, 3, 2)\n+#define PIN_PD9__D0\t\t\tPINMUX_PIN(PIN_PD9, 4, 2)\n+#define PIN_PD9__TIOB2\t\t\tPINMUX_PIN(PIN_PD9, 5, 2)\n+#define PIN_PD9__FLEXCOM11_IO1\t\tPINMUX_PIN(PIN_PD9, 6, 5)\n+#define PIN_PD10\t\t\t106\n+#define PIN_PD10__GPIO\t\t\tPINMUX_PIN(PIN_PD10, 0, 0)\n+#define PIN_PD10__SDMMC2_CD\t\tPINMUX_PIN(PIN_PD10, 1, 1)\n+#define PIN_PD10__PCK6\t\t\tPINMUX_PIN(PIN_PD10, 2, 2)\n+#define PIN_PD10__I2SMCC0_DIN2\t\tPINMUX_PIN(PIN_PD10, 3, 2)\n+#define PIN_PD10__D1\t\t\tPINMUX_PIN(PIN_PD10, 4, 2)\n+#define PIN_PD10__TCLK2\t\t\tPINMUX_PIN(PIN_PD10, 5, 2)\n+#define PIN_PD10__FLEXCOM0_IO0\t\tPINMUX_PIN(PIN_PD10, 6, 3)\n+#define PIN_PD11\t\t\t107\n+#define PIN_PD11__GPIO\t\t\tPINMUX_PIN(PIN_PD11, 0, 0)\n+#define PIN_PD11__SDMMC2_1V8SEL\t\tPINMUX_PIN(PIN_PD11, 1, 1)\n+#define PIN_PD11__PCK7\t\t\tPINMUX_PIN(PIN_PD11, 2, 2)\n+#define PIN_PD11__I2SMCC0_DIN3\t\tPINMUX_PIN(PIN_PD11, 3, 2)\n+#define PIN_PD11__D2\t\t\tPINMUX_PIN(PIN_PD11, 4, 2)\n+#define PIN_PD11__TIOA3\t\t\tPINMUX_PIN(PIN_PD11, 5, 2)\n+#define PIN_PD11__FLEXCOM0_IO1\t\tPINMUX_PIN(PIN_PD11, 6, 3)\n+#define PIN_PD12\t\t\t108\n+#define PIN_PD12__GPIO\t\t\tPINMUX_PIN(PIN_PD12, 0, 0)\n+#define PIN_PD12__PCK1\t\t\tPINMUX_PIN(PIN_PD12, 1, 2)\n+#define PIN_PD12__FLEXCOM1_IO0\t\tPINMUX_PIN(PIN_PD12, 2, 2)\n+#define PIN_PD12__CANTX0\t\tPINMUX_PIN(PIN_PD12, 4, 2)\n+#define PIN_PD12__TIOB3\t\t\tPINMUX_PIN(PIN_PD12, 5, 2)\n+#define PIN_PD13\t\t\t109\n+#define PIN_PD13__GPIO\t\t\tPINMUX_PIN(PIN_PD13, 0, 0)\n+#define PIN_PD13__I2SMCC0_CK\t\tPINMUX_PIN(PIN_PD13, 1, 2)\n+#define PIN_PD13__FLEXCOM1_IO1\t\tPINMUX_PIN(PIN_PD13, 2, 2)\n+#define PIN_PD13__PWML0\t\t\tPINMUX_PIN(PIN_PD13, 3, 4)\n+#define PIN_PD13__CANRX0\t\tPINMUX_PIN(PIN_PD13, 4, 2)\n+#define PIN_PD13__TCLK3\t\t\tPINMUX_PIN(PIN_PD13, 5, 2)\n+#define PIN_PD14\t\t\t110\n+#define PIN_PD14__GPIO\t\t\tPINMUX_PIN(PIN_PD14, 0, 0)\n+#define PIN_PD14__I2SMCC0_MCK\t\tPINMUX_PIN(PIN_PD14, 1, 2)\n+#define PIN_PD14__FLEXCOM1_IO2\t\tPINMUX_PIN(PIN_PD14, 2, 2)\n+#define PIN_PD14__PWMH0\t\t\tPINMUX_PIN(PIN_PD14, 3, 4)\n+#define PIN_PD14__CANTX1\t\tPINMUX_PIN(PIN_PD14, 4, 2)\n+#define PIN_PD14__TIOA4\t\t\tPINMUX_PIN(PIN_PD14, 5, 2)\n+#define PIN_PD14__FLEXCOM2_IO0\t\tPINMUX_PIN(PIN_PD14, 6, 5)\n+#define PIN_PD15\t\t\t111\n+#define PIN_PD15__GPIO\t\t\tPINMUX_PIN(PIN_PD15, 0, 0)\n+#define PIN_PD15__I2SMCC0_WS\t\tPINMUX_PIN(PIN_PD15, 1, 2)\n+#define PIN_PD15__FLEXCOM1_IO3\t\tPINMUX_PIN(PIN_PD15, 2, 2)\n+#define PIN_PD15__PWML1\t\t\tPINMUX_PIN(PIN_PD15, 3, 4)\n+#define PIN_PD15__CANRX1\t\tPINMUX_PIN(PIN_PD15, 4, 2)\n+#define PIN_PD15__TIOB4\t\t\tPINMUX_PIN(PIN_PD15, 5, 2)\n+#define PIN_PD15__FLEXCOM2_IO1\t\tPINMUX_PIN(PIN_PD15, 6, 5)\n+#define PIN_PD16\t\t\t112\n+#define PIN_PD16__GPIO\t\t\tPINMUX_PIN(PIN_PD16, 0, 0)\n+#define PIN_PD16__I2SMCC0_DOUT0\t\tPINMUX_PIN(PIN_PD16, 1, 2)\n+#define PIN_PD16__FLEXCOM1_IO4\t\tPINMUX_PIN(PIN_PD16, 2, 2)\n+#define PIN_PD16__PWMH1\t\t\tPINMUX_PIN(PIN_PD16, 3, 4)\n+#define PIN_PD16__CANTX2\t\tPINMUX_PIN(PIN_PD16, 4, 2)\n+#define PIN_PD16__TCLK4\t\t\tPINMUX_PIN(PIN_PD16, 5, 2)\n+#define PIN_PD16__FLEXCOM3_IO0\t\tPINMUX_PIN(PIN_PD16, 6, 5)\n+#define PIN_PD17\t\t\t113\n+#define PIN_PD17__GPIO\t\t\tPINMUX_PIN(PIN_PD17, 0, 0)\n+#define PIN_PD17__I2SMCC0_DOUT1\t\tPINMUX_PIN(PIN_PD17, 1, 2)\n+#define PIN_PD17__FLEXCOM2_IO0\t\tPINMUX_PIN(PIN_PD17, 2, 2)\n+#define PIN_PD17__PWML2\t\t\tPINMUX_PIN(PIN_PD17, 3, 4)\n+#define PIN_PD17__CANRX2\t\tPINMUX_PIN(PIN_PD17, 4, 2)\n+#define PIN_PD17__TIOA5\t\t\tPINMUX_PIN(PIN_PD17, 5, 2)\n+#define PIN_PD17__FLEXCOM3_IO1\t\tPINMUX_PIN(PIN_PD17, 6, 5)\n+#define PIN_PD18\t\t\t114\n+#define PIN_PD18__GPIO\t\t\tPINMUX_PIN(PIN_PD18, 0, 0)\n+#define PIN_PD18__I2SMCC0_DOUT2\t\tPINMUX_PIN(PIN_PD18, 1, 2)\n+#define PIN_PD18__FLEXCOM2_IO1\t\tPINMUX_PIN(PIN_PD18, 2, 2)\n+#define PIN_PD18__PWMH2\t\t\tPINMUX_PIN(PIN_PD18, 3, 4)\n+#define PIN_PD18__CANTX3\t\tPINMUX_PIN(PIN_PD18, 4, 2)\n+#define PIN_PD18__TIOB5\t\t\tPINMUX_PIN(PIN_PD18, 5, 2)\n+#define PIN_PD18__FLEXCOM4_IO0\t\tPINMUX_PIN(PIN_PD18, 6, 5)\n+#define PIN_PD19\t\t\t115\n+#define PIN_PD19__GPIO\t\t\tPINMUX_PIN(PIN_PD19, 0, 0)\n+#define PIN_PD19__I2SMCC0_DOUT3\t\tPINMUX_PIN(PIN_PD19, 1, 2)\n+#define PIN_PD19__FLEXCOM2_IO2\t\tPINMUX_PIN(PIN_PD19, 2, 2)\n+#define PIN_PD19__PWML3\t\t\tPINMUX_PIN(PIN_PD19, 3, 4)\n+#define PIN_PD19__CANRX3\t\tPINMUX_PIN(PIN_PD19, 4, 2)\n+#define PIN_PD19__TCLK5\t\t\tPINMUX_PIN(PIN_PD19, 5, 2)\n+#define PIN_PD19__FLEXCOM4_IO1\t\tPINMUX_PIN(PIN_PD19, 6, 5)\n+#define PIN_PD20\t\t\t116\n+#define PIN_PD20__GPIO\t\t\tPINMUX_PIN(PIN_PD20, 0, 0)\n+#define PIN_PD20__PCK0\t\t\tPINMUX_PIN(PIN_PD20, 1, 3)\n+#define PIN_PD20__FLEXCOM2_IO3\t\tPINMUX_PIN(PIN_PD20, 2, 2)\n+#define PIN_PD20__PWMH3\t\t\tPINMUX_PIN(PIN_PD20, 3, 4)\n+#define PIN_PD20__CANTX4\t\tPINMUX_PIN(PIN_PD20, 5, 2)\n+#define PIN_PD20__FLEXCOM5_IO0\t\tPINMUX_PIN(PIN_PD20, 6, 5)\n+#define PIN_PD21\t\t\t117\n+#define PIN_PD21__GPIO\t\t\tPINMUX_PIN(PIN_PD21, 0, 0)\n+#define PIN_PD21__PCK1\t\t\tPINMUX_PIN(PIN_PD21, 1, 3)\n+#define PIN_PD21__FLEXCOM2_IO4\t\tPINMUX_PIN(PIN_PD21, 2, 2)\n+#define PIN_PD21__CANRX4\t\tPINMUX_PIN(PIN_PD21, 4, 2)\n+#define PIN_PD21__FLEXCOM5_IO1\t\tPINMUX_PIN(PIN_PD21, 6, 5)\n+#define PIN_PD21__G1_TXEN\t\tPINMUX_PIN(PIN_PD21, 7, 1)\n+#define PIN_PD22\t\t\t118\n+#define PIN_PD22__GPIO\t\t\tPINMUX_PIN(PIN_PD22, 0, 0)\n+#define PIN_PD22__PDMC0_CLK\t\tPINMUX_PIN(PIN_PD22, 1, 2)\n+#define PIN_PD22__PWMEXTRG0\t\tPINMUX_PIN(PIN_PD22, 3, 4)\n+#define PIN_PD22__RD1\t\t\tPINMUX_PIN(PIN_PD22, 4, 2)\n+#define PIN_PD22__CANTX5\t\tPINMUX_PIN(PIN_PD22, 6, 2)\n+#define PIN_PD22__G1_TX0\t\tPINMUX_PIN(PIN_PD22, 7, 1)\n+#define PIN_PD23\t\t\t119\n+#define PIN_PD23__GPIO\t\t\tPINMUX_PIN(PIN_PD23, 0, 0)\n+#define PIN_PD23__PDMC0_DS0\t\tPINMUX_PIN(PIN_PD23, 1, 2)\n+#define PIN_PD23__PWMEXTRG1\t\tPINMUX_PIN(PIN_PD23, 3, 4)\n+#define PIN_PD23__RF1\t\t\tPINMUX_PIN(PIN_PD23, 4, 2)\n+#define PIN_PD23__ISC_MCK\t\tPINMUX_PIN(PIN_PD23, 5, 2)\n+#define PIN_PD23__CANRX5\t\tPINMUX_PIN(PIN_PD23, 6, 2)\n+#define PIN_PD23__G1_TX1\t\tPINMUX_PIN(PIN_PD23, 7, 1)\n+#define PIN_PD24\t\t\t120\n+#define PIN_PD24__GPIO\t\t\tPINMUX_PIN(PIN_PD24, 0, 0)\n+#define PIN_PD24__PDMC0_DS1\t\tPINMUX_PIN(PIN_PD24, 1, 2)\n+#define PIN_PD24__PWMFI0\t\tPINMUX_PIN(PIN_PD24, 3, 4)\n+#define PIN_PD24__RK1\t\t\tPINMUX_PIN(PIN_PD24, 4, 2)\n+#define PIN_PD24__ISC_D0\t\tPINMUX_PIN(PIN_PD24, 5, 2)\n+#define PIN_PD24__G1_RXDV\t\tPINMUX_PIN(PIN_PD24, 7, 1)\n+#define PIN_PD25\t\t\t121\n+#define PIN_PD25__GPIO\t\t\tPINMUX_PIN(PIN_PD25, 0, 0)\n+#define PIN_PD25__PDMC1_CLK\t\tPINMUX_PIN(PIN_PD25, 1, 2)\n+#define PIN_PD25__FLEXCOM5_IO0\t\tPINMUX_PIN(PIN_PD25, 2, 2)\n+#define PIN_PD25__PWMFI1\t\tPINMUX_PIN(PIN_PD25, 3, 4)\n+#define PIN_PD25__TD1\t\t\tPINMUX_PIN(PIN_PD25, 4, 2)\n+#define PIN_PD25__ISC_D1\t\tPINMUX_PIN(PIN_PD25, 5, 2)\n+#define PIN_PD25__G1_RX0\t\tPINMUX_PIN(PIN_PD25, 7, 1)\n+#define PIN_PD26\t\t\t122\n+#define PIN_PD26__GPIO\t\t\tPINMUX_PIN(PIN_PD26, 0, 0)\n+#define PIN_PD26__PDMC1_DS0\t\tPINMUX_PIN(PIN_PD26, 1, 2)\n+#define PIN_PD26__FLEXCOM5_IO1\t\tPINMUX_PIN(PIN_PD26, 2, 2)\n+#define PIN_PD26__ADTRG\t\t\tPINMUX_PIN(PIN_PD26, 3, 3)\n+#define PIN_PD26__TF1\t\t\tPINMUX_PIN(PIN_PD26, 4, 2)\n+#define PIN_PD26__ISC_D2\t\tPINMUX_PIN(PIN_PD26, 5, 2)\n+#define PIN_PD26__G1_RX1\t\tPINMUX_PIN(PIN_PD26, 7, 1)\n+#define PIN_PD27\t\t\t123\n+#define PIN_PD27__GPIO\t\t\tPINMUX_PIN(PIN_PD27, 0, 0)\n+#define PIN_PD27__PDMC1_DS1\t\tPINMUX_PIN(PIN_PD27, 1, 2)\n+#define PIN_PD27__FLEXCOM5_IO2\t\tPINMUX_PIN(PIN_PD27, 2, 2)\n+#define PIN_PD27__TIOA0\t\t\tPINMUX_PIN(PIN_PD27, 3, 3)\n+#define PIN_PD27__TK1\t\t\tPINMUX_PIN(PIN_PD27, 4, 2)\n+#define PIN_PD27__ISC_D3\t\tPINMUX_PIN(PIN_PD27, 5, 2)\n+#define PIN_PD27__G1_RXER\t\tPINMUX_PIN(PIN_PD27, 7, 1)\n+#define PIN_PD28\t\t\t124\n+#define PIN_PD28__GPIO\t\t\tPINMUX_PIN(PIN_PD28, 0, 0)\n+#define PIN_PD28__RD0\t\t\tPINMUX_PIN(PIN_PD28, 1, 2)\n+#define PIN_PD28__FLEXCOM5_IO3\t\tPINMUX_PIN(PIN_PD28, 2, 2)\n+#define PIN_PD28__TIOB0\t\t\tPINMUX_PIN(PIN_PD28, 3, 3)\n+#define PIN_PD28__I2SMCC1_CK\t\tPINMUX_PIN(PIN_PD28, 4, 2)\n+#define PIN_PD28__ISC_D4\t\tPINMUX_PIN(PIN_PD28, 5, 2)\n+#define PIN_PD28__PWML3\t\t\tPINMUX_PIN(PIN_PD28, 6, 5)\n+#define PIN_PD28__G1_MDC\t\tPINMUX_PIN(PIN_PD28, 7, 1)\n+#define PIN_PD29\t\t\t125\n+#define PIN_PD29__GPIO\t\t\tPINMUX_PIN(PIN_PD29, 0, 0)\n+#define PIN_PD29__RF0\t\t\tPINMUX_PIN(PIN_PD29, 1, 2)\n+#define PIN_PD29__FLEXCOM5_IO4\t\tPINMUX_PIN(PIN_PD29, 2, 2)\n+#define PIN_PD29__TCLK0\t\t\tPINMUX_PIN(PIN_PD29, 3, 3)\n+#define PIN_PD29__I2SMCC1_WS\t\tPINMUX_PIN(PIN_PD29, 4, 2)\n+#define PIN_PD29__ISC_D5\t\tPINMUX_PIN(PIN_PD29, 5, 2)\n+#define PIN_PD29__PWMH3\t\t\tPINMUX_PIN(PIN_PD29, 6, 5)\n+#define PIN_PD29__G1_MDIO\t\tPINMUX_PIN(PIN_PD29, 7, 1)\n+#define PIN_PD30\t\t\t126\n+#define PIN_PD30__GPIO\t\t\tPINMUX_PIN(PIN_PD30, 0, 0)\n+#define PIN_PD30__RK0\t\t\tPINMUX_PIN(PIN_PD30, 1, 2)\n+#define PIN_PD30__FLEXCOM6_IO0\t\tPINMUX_PIN(PIN_PD30, 2, 2)\n+#define PIN_PD30__TIOA1\t\t\tPINMUX_PIN(PIN_PD30, 3, 3)\n+#define PIN_PD30__I2SMCC1_MCK\t\tPINMUX_PIN(PIN_PD30, 4, 2)\n+#define PIN_PD30__ISC_D6\t\tPINMUX_PIN(PIN_PD30, 5, 2)\n+#define PIN_PD30__PWMEXTRG0\t\tPINMUX_PIN(PIN_PD30, 6, 5)\n+#define PIN_PD30__G1_TXCK\t\tPINMUX_PIN(PIN_PD30, 7, 1)\n+#define PIN_PD31\t\t\t127\n+#define PIN_PD31__GPIO\t\t\tPINMUX_PIN(PIN_PD31, 0, 0)\n+#define PIN_PD31__TD0\t\t\tPINMUX_PIN(PIN_PD31, 1, 2)\n+#define PIN_PD31__FLEXCOM6_IO1\t\tPINMUX_PIN(PIN_PD31, 2, 2)\n+#define PIN_PD31__TIOB1\t\t\tPINMUX_PIN(PIN_PD31, 3, 3)\n+#define PIN_PD31__I2SMCC1_DOUT0\t\tPINMUX_PIN(PIN_PD31, 4, 2)\n+#define PIN_PD31__ISC_D7\t\tPINMUX_PIN(PIN_PD31, 5, 2)\n+#define PIN_PD31__PWM_EXTRG1\t\tPINMUX_PIN(PIN_PD31, 6, 5)\n+#define PIN_PD31__G1_TX2\t\tPINMUX_PIN(PIN_PD31, 7, 1)\n+#define PIN_PE0\t\t\t\t128\n+#define PIN_PE0__GPIO\t\t\tPINMUX_PIN(PIN_PE0, 0, 0)\n+#define PIN_PE0__TF0\t\t\tPINMUX_PIN(PIN_PE0, 1, 2)\n+#define PIN_PE0__FLEXCOM6_IO2\t\tPINMUX_PIN(PIN_PE0, 2, 2)\n+#define PIN_PE0__TCLK1\t\t\tPINMUX_PIN(PIN_PE0, 3, 3)\n+#define PIN_PE0__I2SMCC1_DOUT1\t\tPINMUX_PIN(PIN_PE0, 4, 2)\n+#define PIN_PE0__ISC_HSYNC\t\tPINMUX_PIN(PIN_PE0, 5, 2)\n+#define PIN_PE0__PWMFI0\t\t\tPINMUX_PIN(PIN_PE0, 6, 5)\n+#define PIN_PE0__G1_TX3\t\t\tPINMUX_PIN(PIN_PE0, 7, 1)\n+#define PIN_PE1\t\t\t\t129\n+#define PIN_PE1__GPIO\t\t\tPINMUX_PIN(PIN_PE1, 0, 0)\n+#define PIN_PE1__TK0\t\t\tPINMUX_PIN(PIN_PE1, 1, 2)\n+#define PIN_PE1__FLEXCOM6_IO3\t\tPINMUX_PIN(PIN_PE1, 2, 2)\n+#define PIN_PE1__TIOA2\t\t\tPINMUX_PIN(PIN_PE1, 3, 3)\n+#define PIN_PE1__I2SMCC1_DOUT2\t\tPINMUX_PIN(PIN_PE1, 4, 2)\n+#define PIN_PE1__ISC_VSYNC\t\tPINMUX_PIN(PIN_PE1, 5, 2)\n+#define PIN_PE1__PWMFI1\t\t\tPINMUX_PIN(PIN_PE1, 6, 5)\n+#define PIN_PE1__G1_RX2\t\t\tPINMUX_PIN(PIN_PE1, 7, 1)\n+#define PIN_PE2\t\t\t\t130\n+#define PIN_PE2__GPIO\t\t\tPINMUX_PIN(PIN_PE2, 0, 0)\n+#define PIN_PE2__PWML0\t\t\tPINMUX_PIN(PIN_PE2, 1, 5)\n+#define PIN_PE2__FLEXCOM6_IO4\t\tPINMUX_PIN(PIN_PE2, 2, 2)\n+#define PIN_PE2__TIOB2\t\t\tPINMUX_PIN(PIN_PE2, 3, 3)\n+#define PIN_PE2__I2SMCC1_DOUT3\t\tPINMUX_PIN(PIN_PE2, 4, 2)\n+#define PIN_PE2__ISC_FIELD\t\tPINMUX_PIN(PIN_PE2, 5, 2)\n+#define PIN_PE2__G1_RX3\t\t\tPINMUX_PIN(PIN_PE2, 7, 1)\n+#define PIN_PE3\t\t\t\t131\n+#define PIN_PE3__GPIO\t\t\tPINMUX_PIN(PIN_PE3, 0, 0)\n+#define PIN_PE3__PWMH0\t\t\tPINMUX_PIN(PIN_PE3, 1, 5)\n+#define PIN_PE3__FLEXCOM0_IO0\t\tPINMUX_PIN(PIN_PE3, 2, 4)\n+#define PIN_PE3__TCLK2\t\t\tPINMUX_PIN(PIN_PE3, 3, 3)\n+#define PIN_PE3__I2SMCC1_DIN0\t\tPINMUX_PIN(PIN_PE3, 4, 2)\n+#define PIN_PE3__ISC_PCK\t\tPINMUX_PIN(PIN_PE3, 5, 2)\n+#define PIN_PE3__G1_RXCK\t\tPINMUX_PIN(PIN_PE3, 7, 1)\n+#define PIN_PE4\t\t\t\t132\n+#define PIN_PE4__GPIO\t\t\tPINMUX_PIN(PIN_PE4, 0, 0)\n+#define PIN_PE4__PWML1\t\t\tPINMUX_PIN(PIN_PE4, 1, 5)\n+#define PIN_PE4__FLEXCOM0_IO1\t\tPINMUX_PIN(PIN_PE4, 2, 4)\n+#define PIN_PE4__TIOA3\t\t\tPINMUX_PIN(PIN_PE4, 3, 3)\n+#define PIN_PE4__I2SMCC1_DIN1\t\tPINMUX_PIN(PIN_PE4, 4, 2)\n+#define PIN_PE4__ISC_D8\t\t\tPINMUX_PIN(PIN_PE4, 5, 2)\n+#define PIN_PE4__G1_TXER\t\tPINMUX_PIN(PIN_PE4, 7, 1)\n+#define PIN_PE5\t\t\t\t133\n+#define PIN_PE5__GPIO\t\t\tPINMUX_PIN(PIN_PE5, 0, 0)\n+#define PIN_PE5__PWMH1\t\t\tPINMUX_PIN(PIN_PE5, 1, 5)\n+#define PIN_PE5__FLEXCOM0_IO2\t\tPINMUX_PIN(PIN_PE5, 2, 4)\n+#define PIN_PE5__TIOB3\t\t\tPINMUX_PIN(PIN_PE5, 3, 3)\n+#define PIN_PE5__I2SMCC1_DIN2\t\tPINMUX_PIN(PIN_PE5, 4, 2)\n+#define PIN_PE5__ISC_D9\t\t\tPINMUX_PIN(PIN_PE5, 5, 2)\n+#define PIN_PE5__G1_COL\t\t\tPINMUX_PIN(PIN_PE5, 7, 1)\n+#define PIN_PE6\t\t\t\t134\n+#define PIN_PE6__GPIO\t\t\tPINMUX_PIN(PIN_PE6, 0, 0)\n+#define PIN_PE6__PWML2\t\t\tPINMUX_PIN(PIN_PE6, 1, 5)\n+#define PIN_PE6__FLEXCOM0_IO3\t\tPINMUX_PIN(PIN_PE6, 2, 4)\n+#define PIN_PE6__TCLK3\t\t\tPINMUX_PIN(PIN_PE6, 3, 3)\n+#define PIN_PE6__I2SMCC1_DIN3\t\tPINMUX_PIN(PIN_PE6, 4, 2)\n+#define PIN_PE6__ISC_D10\t\tPINMUX_PIN(PIN_PE6, 5, 2)\n+#define PIN_PE6__G1_CRS\t\t\tPINMUX_PIN(PIN_PE6, 7, 1)\n+#define PIN_PE7\t\t\t\t135\n+#define PIN_PE7__GPIO\t\t\tPINMUX_PIN(PIN_PE7, 0, 0)\n+#define PIN_PE7__PWMH2\t\t\tPINMUX_PIN(PIN_PE7, 1, 5)\n+#define PIN_PE7__FLEXCOM0_IO4\t\tPINMUX_PIN(PIN_PE7, 2, 4)\n+#define PIN_PE7__TIOA4\t\t\tPINMUX_PIN(PIN_PE7, 3, 3)\n+#define PIN_PE7__ISC_D11\t\tPINMUX_PIN(PIN_PE7, 5, 2)\n+#define PIN_PE7__G1_TSUCOMP\t\tPINMUX_PIN(PIN_PE7, 7, 1)\n--- /dev/null\n+++ b/arch/arm/boot/dts/sama7g5.dtsi\n@@ -0,0 +1,528 @@\n+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)\n+/*\n+ *  sama7g5.dtsi - Device Tree Include file for SAMA7G5 family SoC\n+ *\n+ *  Copyright (C) 2020 Microchip Technology, Inc. and its subsidiaries\n+ *\n+ *  Author: Eugen Hristev <eugen.hristev@microchip.com>\n+ *  Author: Claudiu Beznea <claudiu.beznea@microchip.com>\n+ *\n+ */\n+\n+#include <dt-bindings/interrupt-controller/irq.h>\n+#include <dt-bindings/interrupt-controller/arm-gic.h>\n+#include <dt-bindings/clock/at91.h>\n+#include <dt-bindings/dma/at91.h>\n+#include <dt-bindings/gpio/gpio.h>\n+\n+/ {\n+\tmodel = \"Microchip SAMA7G5 family SoC\";\n+\tcompatible = \"microchip,sama7g5\";\n+\t#address-cells = <1>;\n+\t#size-cells = <1>;\n+\tinterrupt-parent = <&gic>;\n+\n+\tcpus {\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\n+\t\tcpu0: cpu@0 {\n+\t\t\tdevice_type = \"cpu\";\n+\t\t\tcompatible = \"arm,cortex-a7\";\n+\t\t\treg = <0x0>;\n+\t\t};\n+\t};\n+\n+\tclocks {\n+\t\tslow_xtal: slow_xtal {\n+\t\t\tcompatible = \"fixed-clock\";\n+\t\t\t#clock-cells = <0>;\n+\t\t};\n+\n+\t\tmain_xtal: main_xtal {\n+\t\t\tcompatible = \"fixed-clock\";\n+\t\t\t#clock-cells = <0>;\n+\t\t};\n+\n+\t\tusb_clk: usb_clk {\n+\t\t\tcompatible = \"fixed-clock\";\n+\t\t\t#clock-cells = <0>;\n+\t\t\tclock-frequency = <48000000>;\n+\t\t};\n+\t};\n+\n+\tvddout25: fixed-regulator-vddout25 {\n+\t\tcompatible = \"regulator-fixed\";\n+\n+\t\tregulator-name = \"VDDOUT25\";\n+\t\tregulator-min-microvolt = <2500000>;\n+\t\tregulator-max-microvolt = <2500000>;\n+\t\tregulator-boot-on;\n+\t\tstatus = \"disabled\";\n+\t};\n+\n+\tns_sram: sram@100000 {\n+\t\tcompatible = \"mmio-sram\";\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <1>;\n+\t\treg = <0x100000 0x20000>;\n+\t\tranges;\n+\t};\n+\n+\tsoc {\n+\t\tcompatible = \"simple-bus\";\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <1>;\n+\t\tranges;\n+\n+\t\tsecumod: secumod@e0004000 {\n+\t\t\tcompatible = \"microchip,sama7g5-secumod\", \"atmel,sama5d2-secumod\", \"syscon\";\n+\t\t\treg = <0xe0004000 0x4000>;\n+\t\t\tgpio-controller;\n+\t\t\t#gpio-cells = <2>;\n+\t\t};\n+\n+\t\tsfrbu: sfr@e0008000 {\n+\t\t\tcompatible = \"microchip,sama7g5-sfrbu\", \"atmel,sama5d2-sfrbu\", \"syscon\";\n+\t\t\treg = <0xe0008000 0x20>;\n+\t\t};\n+\n+\t\tpioA: pinctrl@e0014000 {\n+\t\t\tcompatible = \"microchip,sama7g5-pinctrl\";\n+\t\t\treg = <0xe0014000 0x800>;\n+\t\t\tinterrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t\t<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t\t<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t\t<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t\t<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tinterrupt-controller;\n+\t\t\t#interrupt-cells = <2>;\n+\t\t\tgpio-controller;\n+\t\t\t#gpio-cells = <2>;\n+\t\t\tclocks = <&pmc PMC_TYPE_PERIPHERAL 11>;\n+\t\t};\n+\n+\t\tpmc: pmc@e0018000 {\n+\t\t\tcompatible = \"microchip,sama7g5-pmc\", \"syscon\";\n+\t\t\treg = <0xe0018000 0x200>;\n+\t\t\tinterrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\t#clock-cells = <2>;\n+\t\t\tclocks = <&clk32k 1>, <&clk32k 0>, <&main_xtal>;\n+\t\t\tclock-names = \"td_slck\", \"md_slck\", \"main_xtal\";\n+\t\t};\n+\n+\t\trtt: rtt@e001d020 {\n+\t\t\tcompatible = \"microchip,sama7g5-rtt\", \"microchip,sam9x60-rtt\", \"atmel,at91sam9260-rtt\";\n+\t\t\treg = <0xe001d020 0x30>;\n+\t\t\tinterrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tclocks = <&clk32k 0>;\n+\t\t};\n+\n+\t\tclk32k: clock-controller@e001d050 {\n+\t\t\tcompatible = \"microchip,sama7g5-sckc\", \"microchip,sam9x60-sckc\";\n+\t\t\treg = <0xe001d050 0x4>;\n+\t\t\tclocks = <&slow_xtal>;\n+\t\t\t#clock-cells = <1>;\n+\t\t};\n+\n+\t\tgpbr: gpbr@e001d060 {\n+\t\t\tcompatible = \"microchip,sama7g5-gpbr\", \"syscon\";\n+\t\t\treg = <0xe001d060 0x48>;\n+\t\t};\n+\n+\t\tps_wdt: watchdog@e001d180 {\n+\t\t\tcompatible = \"microchip,sama7g5-wdt\";\n+\t\t\treg = <0xe001d180 0x24>;\n+\t\t\tinterrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tclocks = <&clk32k 0>;\n+\t\t};\n+\n+\t\tsdmmc0: mmc@e1204000 {\n+\t\t\tcompatible = \"microchip,sama7g5-sdhci\", \"microchip,sam9x60-sdhci\";\n+\t\t\treg = <0xe1204000 0x4000>;\n+\t\t\tinterrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tclocks = <&pmc PMC_TYPE_PERIPHERAL 80>, <&pmc PMC_TYPE_GCK 80>;\n+\t\t\tclock-names = \"hclock\", \"multclk\";\n+\t\t\tassigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>;\n+\t\t\tassigned-clocks = <&pmc PMC_TYPE_GCK 80>;\n+\t\t\tassigned-clock-rates = <200000000>;\n+\t\t\tmicrochip,sdcal-inverted;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tsdmmc1: mmc@e1208000 {\n+\t\t\tcompatible = \"microchip,sama7g5-sdhci\", \"microchip,sam9x60-sdhci\";\n+\t\t\treg = <0xe1208000 0x4000>;\n+\t\t\tinterrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tclocks = <&pmc PMC_TYPE_PERIPHERAL 81>, <&pmc PMC_TYPE_GCK 81>;\n+\t\t\tclock-names = \"hclock\", \"multclk\";\n+\t\t\tassigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>;\n+\t\t\tassigned-clocks = <&pmc PMC_TYPE_GCK 81>;\n+\t\t\tassigned-clock-rates = <200000000>;\n+\t\t\tmicrochip,sdcal-inverted;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tsdmmc2: mmc@e120c000 {\n+\t\t\tcompatible = \"microchip,sama7g5-sdhci\", \"microchip,sam9x60-sdhci\";\n+\t\t\treg = <0xe120c000 0x4000>;\n+\t\t\tinterrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tclocks = <&pmc PMC_TYPE_PERIPHERAL 82>, <&pmc PMC_TYPE_GCK 82>;\n+\t\t\tclock-names = \"hclock\", \"multclk\";\n+\t\t\tassigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>;\n+\t\t\tassigned-clocks = <&pmc PMC_TYPE_GCK 82>;\n+\t\t\tassigned-clock-rates = <200000000>;\n+\t\t\tmicrochip,sdcal-inverted;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tpwm: pwm@e1604000 {\n+\t\t\tcompatible = \"microchip,sama7g5-pwm\", \"atmel,sama5d2-pwm\";\n+\t\t\treg = <0xe1604000 0x4000>;\n+\t\t\tinterrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\t#pwm-cells = <3>;\n+\t\t\tclocks = <&pmc PMC_TYPE_PERIPHERAL 77>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tspdifrx: spdifrx@e1614000 {\n+\t\t\t#sound-dai-cells = <0>;\n+\t\t\tcompatible = \"microchip,sama7g5-spdifrx\";\n+\t\t\treg = <0xe1614000 0x4000>;\n+\t\t\tinterrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tdmas = <&dma0 AT91_XDMAC_DT_PERID(49)>;\n+\t\t\tdma-names = \"rx\";\n+\t\t\tclocks = <&pmc PMC_TYPE_PERIPHERAL 84>, <&pmc PMC_TYPE_GCK 84>;\n+\t\t\tclock-names = \"pclk\", \"gclk\";\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tspdiftx: spdiftx@e1618000 {\n+\t\t\t#sound-dai-cells = <0>;\n+\t\t\tcompatible = \"microchip,sama7g5-spdiftx\";\n+\t\t\treg = <0xe1618000 0x4000>;\n+\t\t\tinterrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tdmas = <&dma0 AT91_XDMAC_DT_PERID(50)>;\n+\t\t\tdma-names = \"tx\";\n+\t\t\tclocks = <&pmc PMC_TYPE_PERIPHERAL 85>, <&pmc PMC_TYPE_GCK 85>;\n+\t\t\tclock-names = \"pclk\", \"gclk\";\n+\t\t};\n+\n+\t\ti2s0: i2s@e161c000 {\n+\t\t\tcompatible = \"microchip,sama7g5-i2smcc\";\n+\t\t\t#sound-dai-cells = <0>;\n+\t\t\treg = <0xe161c000 0x4000>;\n+\t\t\tinterrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tdmas = <&dma0 AT91_XDMAC_DT_PERID(34)>, <&dma0 AT91_XDMAC_DT_PERID(33)>;\n+\t\t\tdma-names = \"tx\", \"rx\";\n+\t\t\tclocks = <&pmc PMC_TYPE_PERIPHERAL 57>, <&pmc PMC_TYPE_GCK 57>;\n+\t\t\tclock-names = \"pclk\", \"gclk\";\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\ti2s1: i2s@e1620000 {\n+\t\t\tcompatible = \"microchip,sama7g5-i2smcc\";\n+\t\t\t#sound-dai-cells = <0>;\n+\t\t\treg = <0xe1620000 0x4000>;\n+\t\t\tinterrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tdmas = <&dma0 AT91_XDMAC_DT_PERID(36)>, <&dma0 AT91_XDMAC_DT_PERID(35)>;\n+\t\t\tdma-names = \"tx\", \"rx\";\n+\t\t\tclocks = <&pmc PMC_TYPE_PERIPHERAL 58>, <&pmc PMC_TYPE_GCK 58>;\n+\t\t\tclock-names = \"pclk\", \"gclk\";\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tpit64b0: timer@e1800000 {\n+\t\t\tcompatible = \"microchip,sama7g5-pit64b\", \"microchip,sam9x60-pit64b\";\n+\t\t\treg = <0xe1800000 0x4000>;\n+\t\t\tinterrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tclocks = <&pmc PMC_TYPE_PERIPHERAL 70>, <&pmc PMC_TYPE_GCK 70>;\n+\t\t\tclock-names = \"pclk\", \"gclk\";\n+\t\t};\n+\n+\t\tpit64b1: timer@e1804000 {\n+\t\t\tcompatible = \"microchip,sama7g5-pit64b\", \"microchip,sam9x60-pit64b\";\n+\t\t\treg = <0xe1804000 0x4000>;\n+\t\t\tinterrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tclocks = <&pmc PMC_TYPE_PERIPHERAL 71>, <&pmc PMC_TYPE_GCK 71>;\n+\t\t\tclock-names = \"pclk\", \"gclk\";\n+\t\t};\n+\n+\t\tflx0: flexcom@e1818000 {\n+\t\t\tcompatible = \"atmel,sama5d2-flexcom\";\n+\t\t\treg = <0xe1818000 0x200>;\n+\t\t\tclocks = <&pmc PMC_TYPE_PERIPHERAL 38>;\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <1>;\n+\t\t\tranges = <0x0 0xe1818000 0x800>;\n+\t\t\tstatus = \"disabled\";\n+\n+\t\t\tuart0: serial@200 {\n+\t\t\t\tcompatible = \"atmel,at91sam9260-usart\";\n+\t\t\t\treg = <0x200 0x200>;\n+\t\t\t\tinterrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\t\tclocks = <&pmc PMC_TYPE_PERIPHERAL 38>;\n+\t\t\t\tclock-names = \"usart\";\n+\t\t\t\tdmas = <&dma1 AT91_XDMAC_DT_PERID(6)>,\n+\t\t\t\t\t<&dma1 AT91_XDMAC_DT_PERID(5)>;\n+\t\t\t\tdma-names = \"tx\", \"rx\";\n+\t\t\t\tatmel,use-dma-rx;\n+\t\t\t\tatmel,use-dma-tx;\n+\t\t\t\tstatus = \"disabled\";\n+\t\t\t};\n+\t\t};\n+\n+\t\tflx1: flexcom@e181c000 {\n+\t\t\tcompatible = \"atmel,sama5d2-flexcom\";\n+\t\t\treg = <0xe181c000 0x200>;\n+\t\t\tclocks = <&pmc PMC_TYPE_PERIPHERAL 39>;\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <1>;\n+\t\t\tranges = <0x0 0xe181c000 0x800>;\n+\t\t\tstatus = \"disabled\";\n+\n+\t\t\ti2c1: i2c@600 {\n+\t\t\t\tcompatible = \"microchip,sama7g5-i2c\", \"microchip,sam9x60-i2c\";\n+\t\t\t\treg = <0x600 0x200>;\n+\t\t\t\tinterrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\t\t#address-cells = <1>;\n+\t\t\t\t#size-cells = <0>;\n+\t\t\t\tclocks = <&pmc PMC_TYPE_PERIPHERAL 39>;\n+\t\t\t\tatmel,fifo-size = <32>;\n+\t\t\t\tdmas = <&dma0 AT91_XDMAC_DT_PERID(7)>,\n+\t\t\t\t\t<&dma0 AT91_XDMAC_DT_PERID(8)>;\n+\t\t\t\tdma-names = \"rx\", \"tx\";\n+\t\t\t\tatmel,use-dma-rx;\n+\t\t\t\tatmel,use-dma-tx;\n+\t\t\t\tstatus = \"disabled\";\n+\t\t\t};\n+\t\t};\n+\n+\t\tflx3: flexcom@e1824000 {\n+\t\t\tcompatible = \"atmel,sama5d2-flexcom\";\n+\t\t\treg = <0xe1824000 0x200>;\n+\t\t\tclocks = <&pmc PMC_TYPE_PERIPHERAL 41>;\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <1>;\n+\t\t\tranges = <0x0 0xe1824000 0x800>;\n+\t\t\tstatus = \"disabled\";\n+\n+\t\t\tuart3: serial@200 {\n+\t\t\t\tcompatible = \"atmel,at91sam9260-usart\";\n+\t\t\t\treg = <0x200 0x200>;\n+\t\t\t\tinterrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\t\tclocks = <&pmc PMC_TYPE_PERIPHERAL 41>;\n+\t\t\t\tclock-names = \"usart\";\n+\t\t\t\tdmas = <&dma1 AT91_XDMAC_DT_PERID(12)>,\n+\t\t\t\t\t<&dma1 AT91_XDMAC_DT_PERID(11)>;\n+\t\t\t\tdma-names = \"tx\", \"rx\";\n+\t\t\t\tatmel,use-dma-rx;\n+\t\t\t\tatmel,use-dma-tx;\n+\t\t\t\tstatus = \"disabled\";\n+\t\t\t};\n+\t\t};\n+\n+\t\ttrng: rng@e2010000 {\n+\t\t\tcompatible = \"microchip,sama7g5-trng\", \"atmel,at91sam9g45-trng\";\n+\t\t\treg = <0xe2010000 0x100>;\n+\t\t\tinterrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tclocks = <&pmc PMC_TYPE_PERIPHERAL 97>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tflx4: flexcom@e2018000 {\n+\t\t\tcompatible = \"atmel,sama5d2-flexcom\";\n+\t\t\treg = <0xe2018000 0x200>;\n+\t\t\tclocks = <&pmc PMC_TYPE_PERIPHERAL 42>;\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <1>;\n+\t\t\tranges = <0x0 0xe2018000 0x800>;\n+\t\t\tstatus = \"disabled\";\n+\n+\t\t\tuart4: serial@200 {\n+\t\t\t\tcompatible = \"atmel,at91sam9260-usart\";\n+\t\t\t\treg = <0x200 0x200>;\n+\t\t\t\tinterrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\t\tclocks = <&pmc PMC_TYPE_PERIPHERAL 42>;\n+\t\t\t\tclock-names = \"usart\";\n+\t\t\t\tdmas = <&dma1 AT91_XDMAC_DT_PERID(14)>,\n+\t\t\t\t\t<&dma1 AT91_XDMAC_DT_PERID(13)>;\n+\t\t\t\tdma-names = \"tx\", \"rx\";\n+\t\t\t\tatmel,use-dma-rx;\n+\t\t\t\tatmel,use-dma-tx;\n+\t\t\t\tatmel,fifo-size = <16>;\n+\t\t\t\tstatus = \"disabled\";\n+\t\t\t};\n+\t\t};\n+\n+\t\tflx7: flexcom@e2024000 {\n+\t\t\tcompatible = \"atmel,sama5d2-flexcom\";\n+\t\t\treg = <0xe2024000 0x200>;\n+\t\t\tclocks = <&pmc PMC_TYPE_PERIPHERAL 45>;\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <1>;\n+\t\t\tranges = <0x0 0xe2024000 0x800>;\n+\t\t\tstatus = \"disabled\";\n+\n+\t\t\tuart7: serial@200 {\n+\t\t\t\tcompatible = \"atmel,at91sam9260-usart\";\n+\t\t\t\treg = <0x200 0x200>;\n+\t\t\t\tinterrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\t\tclocks = <&pmc PMC_TYPE_PERIPHERAL 45>;\n+\t\t\t\tclock-names = \"usart\";\n+\t\t\t\tdmas = <&dma1 AT91_XDMAC_DT_PERID(20)>,\n+\t\t\t\t\t<&dma1 AT91_XDMAC_DT_PERID(19)>;\n+\t\t\t\tdma-names = \"tx\", \"rx\";\n+\t\t\t\tatmel,use-dma-rx;\n+\t\t\t\tatmel,use-dma-tx;\n+\t\t\t\tatmel,fifo-size = <16>;\n+\t\t\t\tstatus = \"disabled\";\n+\t\t\t};\n+\t\t};\n+\n+\t\tgmac0: ethernet@e2800000 {\n+\t\t\tcompatible = \"microchip,sama7g5-gem\";\n+\t\t\treg = <0xe2800000 0x1000>;\n+\t\t\tinterrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH\n+\t\t\t\t      GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH\n+\t\t\t\t      GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH\n+\t\t\t\t      GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH\n+\t\t\t\t      GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH\n+\t\t\t\t      GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tclocks = <&pmc PMC_TYPE_PERIPHERAL 51>, <&pmc PMC_TYPE_PERIPHERAL 51>, <&pmc PMC_TYPE_GCK 51>, <&pmc PMC_TYPE_GCK 53>;\n+\t\t\tclock-names = \"pclk\", \"hclk\", \"tx_clk\", \"tsu_clk\";\n+\t\t\tassigned-clocks = <&pmc PMC_TYPE_GCK 51>;\n+\t\t\tassigned-clock-rates = <125000000>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tgmac1: ethernet@e2804000 {\n+\t\t\tcompatible = \"microchip,sama7g5-emac\";\n+\t\t\treg = <0xe2804000 0x1000>;\n+\t\t\tinterrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH\n+\t\t\t\t      GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tclocks = <&pmc PMC_TYPE_PERIPHERAL 52>, <&pmc PMC_TYPE_PERIPHERAL 52>;\n+\t\t\tclock-names = \"pclk\", \"hclk\";\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tdma0: dma-controller@e2808000 {\n+\t\t\tcompatible = \"microchip,sama7g5-dma\";\n+\t\t\treg = <0xe2808000 0x1000>;\n+\t\t\tinterrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\t#dma-cells = <1>;\n+\t\t\tclocks = <&pmc PMC_TYPE_PERIPHERAL 22>;\n+\t\t\tclock-names = \"dma_clk\";\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tdma1: dma-controller@e280c000 {\n+\t\t\tcompatible = \"microchip,sama7g5-dma\";\n+\t\t\treg = <0xe280c000 0x1000>;\n+\t\t\tinterrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\t#dma-cells = <1>;\n+\t\t\tclocks = <&pmc PMC_TYPE_PERIPHERAL 23>;\n+\t\t\tclock-names = \"dma_clk\";\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\t/* Place dma2 here despite it's address */\n+\t\tdma2: dma-controller@e1200000 {\n+\t\t\tcompatible = \"microchip,sama7g5-dma\";\n+\t\t\treg = <0xe1200000 0x1000>;\n+\t\t\tinterrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\t#dma-cells = <1>;\n+\t\t\tclocks = <&pmc PMC_TYPE_PERIPHERAL 24>;\n+\t\t\tclock-names = \"dma_clk\";\n+\t\t\tdma-requests = <0>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tflx8: flexcom@e2818000 {\n+\t\t\tcompatible = \"atmel,sama5d2-flexcom\";\n+\t\t\treg = <0xe2818000 0x200>;\n+\t\t\tclocks = <&pmc PMC_TYPE_PERIPHERAL 46>;\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <1>;\n+\t\t\tranges = <0x0 0xe2818000 0x800>;\n+\t\t\tstatus = \"disabled\";\n+\n+\t\t\ti2c8: i2c@600 {\n+\t\t\t\tcompatible = \"microchip,sama7g5-i2c\", \"microchip,sam9x60-i2c\";\n+\t\t\t\treg = <0x600 0x200>;\n+\t\t\t\tinterrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\t\t#address-cells = <1>;\n+\t\t\t\t#size-cells = <0>;\n+\t\t\t\tclocks = <&pmc PMC_TYPE_PERIPHERAL 46>;\n+\t\t\t\tatmel,fifo-size = <32>;\n+\t\t\t\tdmas = <&dma0 AT91_XDMAC_DT_PERID(21)>,\n+\t\t\t\t\t<&dma0 AT91_XDMAC_DT_PERID(22)>;\n+\t\t\t\tdma-names = \"rx\", \"tx\";\n+\t\t\t\tatmel,use-dma-rx;\n+\t\t\t\tatmel,use-dma-tx;\n+\t\t\t\tstatus = \"disabled\";\n+\t\t\t};\n+\t\t};\n+\n+\t\tflx9: flexcom@e281c000 {\n+\t\t\tcompatible = \"atmel,sama5d2-flexcom\";\n+\t\t\treg = <0xe281c000 0x200>;\n+\t\t\tclocks = <&pmc PMC_TYPE_PERIPHERAL 47>;\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <1>;\n+\t\t\tranges = <0x0 0xe281c000 0x800>;\n+\t\t\tstatus = \"disabled\";\n+\n+\t\t\ti2c9: i2c@600 {\n+\t\t\t\tcompatible = \"microchip,sama7g5-i2c\", \"microchip,sam9x60-i2c\";\n+\t\t\t\treg = <0x600 0x200>;\n+\t\t\t\tinterrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\t\t#address-cells = <1>;\n+\t\t\t\t#size-cells = <0>;\n+\t\t\t\tclocks = <&pmc PMC_TYPE_PERIPHERAL 47>;\n+\t\t\t\tatmel,fifo-size = <32>;\n+\t\t\t\tdmas = <&dma0 AT91_XDMAC_DT_PERID(23)>,\n+\t\t\t\t\t<&dma0 AT91_XDMAC_DT_PERID(24)>;\n+\t\t\t\tdma-names = \"rx\", \"tx\";\n+\t\t\t\tatmel,use-dma-rx;\n+\t\t\t\tatmel,use-dma-tx;\n+\t\t\t\tstatus = \"disabled\";\n+\t\t\t};\n+\t\t};\n+\n+\t\tflx11: flexcom@e2824000 {\n+\t\t\tcompatible = \"atmel,sama5d2-flexcom\";\n+\t\t\treg = <0xe2824000 0x200>;\n+\t\t\tclocks = <&pmc PMC_TYPE_PERIPHERAL 49>;\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <1>;\n+\t\t\tranges = <0x0 0xe2824000 0x800>;\n+\t\t\tstatus = \"disabled\";\n+\n+\t\t\tspi11: spi@400 {\n+\t\t\t\tcompatible = \"atmel,at91rm9200-spi\";\n+\t\t\t\treg = <0x400 0x200>;\n+\t\t\t\tinterrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\t\tclocks = <&pmc PMC_TYPE_PERIPHERAL 49>;\n+\t\t\t\tclock-names = \"spi_clk\";\n+\t\t\t\t#address-cells = <1>;\n+\t\t\t\t#size-cells = <0>;\n+\t\t\t\tatmel,fifo-size = <32>;\n+\t\t\t\tdmas = <&dma0 AT91_XDMAC_DT_PERID(27)>,\n+\t\t\t\t\t    <&dma0 AT91_XDMAC_DT_PERID(28)>;\n+\t\t\t\tdma-names = \"rx\", \"tx\";\n+\t\t\t\tstatus = \"disabled\";\n+\t\t\t};\n+\t\t};\n+\n+\t\tgic: interrupt-controller@e8c11000 {\n+\t\t\tcompatible = \"arm,cortex-a7-gic\";\n+\t\t\t#interrupt-cells = <3>;\n+\t\t\t#address-cells = <0>;\n+\t\t\tinterrupt-controller;\n+\t\t\tinterrupt-parent;\n+\t\t\treg = <0xe8c11000 0x1000>,\n+\t\t\t\t<0xe8c12000 0x2000>;\n+\t\t};\n+\t};\n+};\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/223-ARM-at91-pm-do-not-panic-if-ram-controllers-are-not-.patch",
    "content": "From 76dbc56ad65350d78d12bd9b36b00c36fb27addf Mon Sep 17 00:00:00 2001\nFrom: Claudiu Beznea <claudiu.beznea@microchip.com>\nDate: Mon, 23 Aug 2021 16:19:12 +0300\nSubject: [PATCH 223/247] ARM: at91: pm: do not panic if ram controllers are\n not enabled\n\nIn case PM is enabled but there is no RAM controller information\nin DT the code will panic. Avoid such scenarios by not initializing\nplatform specific PM code in case RAM controller is not provided\nvia DT.\n\nReported-by: Eugen Hristev <eugen.hristev@microchip.com>\nFixes: 827de1f123ba0 (\"ARM: at91: remove at91_dt_initialize and machine init_early()\")\nFixes: 892e1f4a3ae58 (\"ARM: at91: pm: add sama7g5 ddr phy controller\")\nSigned-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>\nSigned-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>\nLink: https://lore.kernel.org/r/20210823131915.23857-2-claudiu.beznea@microchip.com\n---\n arch/arm/mach-at91/pm.c | 22 ++++++++++++++++------\n 1 file changed, 16 insertions(+), 6 deletions(-)\n\n--- a/arch/arm/mach-at91/pm.c\n+++ b/arch/arm/mach-at91/pm.c\n@@ -589,7 +589,7 @@ static const struct of_device_id ramc_ph\n \t{ /* Sentinel. */ },\n };\n \n-static __init void at91_dt_ramc(bool phy_mandatory)\n+static __init int at91_dt_ramc(bool phy_mandatory)\n {\n \tstruct device_node *np;\n \tconst struct of_device_id *of_id;\n@@ -625,12 +625,18 @@ static __init void at91_dt_ramc(bool phy\n \t/* Lookup for DDR PHY node, if any. */\n \tfor_each_matching_node_and_match(np, ramc_phy_ids, &of_id) {\n \t\tsoc_pm.data.ramc_phy = of_iomap(np, 0);\n-\t\tif (!soc_pm.data.ramc_phy)\n-\t\t\tpanic(pr_fmt(\"unable to map ramc phy cpu registers\\n\"));\n+\t\tif (!soc_pm.data.ramc_phy) {\n+\t\t\tpr_err(\"unable to map ramc phy cpu registers\\n\");\n+\t\t\tret = -ENOMEM;\n+\t\t\tgoto unmap_ramc;\n+\t\t}\n \t}\n \n-\tif (phy_mandatory && !soc_pm.data.ramc_phy)\n-\t\tpanic(pr_fmt(\"DDR PHY is mandatory!\\n\"));\n+\tif (phy_mandatory && !soc_pm.data.ramc_phy) {\n+\t\tpr_err(\"DDR PHY is mandatory!\\n\");\n+\t\tret = -ENODEV;\n+\t\tgoto unmap_ramc;\n+\t}\n \n \tif (!standby) {\n \t\tpr_warn(\"ramc no standby function available\\n\");\n@@ -1163,13 +1169,17 @@ void __init sama7_pm_init(void)\n \t\t[AT91_PM_BACKUP]\t= AT91_PM_IOMAP(SFRBU) |\n \t\t\t\t\t  AT91_PM_IOMAP(SHDWC),\n \t};\n+\tint ret;\n \n \tif (!IS_ENABLED(CONFIG_SOC_SAMA7))\n \t\treturn;\n \n \tat91_pm_modes_validate(modes, ARRAY_SIZE(modes));\n \n-\tat91_dt_ramc(true);\n+\tret = at91_dt_ramc(true);\n+\tif (ret)\n+\t\treturn;\n+\n \tat91_pm_modes_init(iomaps, ARRAY_SIZE(iomaps));\n \tat91_pm_init(NULL);\n \n"
  },
  {
    "path": "target/linux/at91/patches-5.10/224-ARM-dts-at91-sama7g5-add-ram-controllers.patch",
    "content": "From cf96a88e44f1fde9f1a30ab335329ff9e895e6f8 Mon Sep 17 00:00:00 2001\nFrom: Claudiu Beznea <claudiu.beznea@microchip.com>\nDate: Mon, 23 Aug 2021 16:19:13 +0300\nSubject: [PATCH 224/247] ARM: dts: at91: sama7g5: add ram controllers\n\nAdd RAM and RAMC PHY controllers. These are necessary for platform\nspecific power management code.\n\nSigned-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>\nSigned-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>\nLink: https://lore.kernel.org/r/20210823131915.23857-3-claudiu.beznea@microchip.com\n---\n arch/arm/boot/dts/sama7g5.dtsi | 12 ++++++++++++\n 1 file changed, 12 insertions(+)\n\n--- a/arch/arm/boot/dts/sama7g5.dtsi\n+++ b/arch/arm/boot/dts/sama7g5.dtsi\n@@ -515,6 +515,18 @@\n \t\t\t};\n \t\t};\n \n+\t\tuddrc: uddrc@e3800000 {\n+\t\t\tcompatible = \"microchip,sama7g5-uddrc\";\n+\t\t\treg = <0xe3800000 0x4000>;\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\n+\t\tddr3phy: ddr3phy@e3804000 {\n+\t\t\tcompatible = \"microchip,sama7g5-ddr3phy\";\n+\t\t\treg = <0xe3804000 0x1000>;\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\n \t\tgic: interrupt-controller@e8c11000 {\n \t\t\tcompatible = \"arm,cortex-a7-gic\";\n \t\t\t#interrupt-cells = <3>;\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/225-ARM-dts-at91-sama7g5-add-securam-node.patch",
    "content": "From 1da1aae0b207d6a5ac7c3070b8d7c6ef61a32d71 Mon Sep 17 00:00:00 2001\nFrom: Claudiu Beznea <claudiu.beznea@microchip.com>\nDate: Mon, 23 Aug 2021 16:19:14 +0300\nSubject: [PATCH 225/247] ARM: dts: at91: sama7g5: add securam node\n\nAdd securam node.\n\nSigned-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>\nSigned-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>\nLink: https://lore.kernel.org/r/20210823131915.23857-4-claudiu.beznea@microchip.com\n---\n arch/arm/boot/dts/sama7g5.dtsi | 11 +++++++++++\n 1 file changed, 11 insertions(+)\n\n--- a/arch/arm/boot/dts/sama7g5.dtsi\n+++ b/arch/arm/boot/dts/sama7g5.dtsi\n@@ -75,6 +75,17 @@\n \t\t#size-cells = <1>;\n \t\tranges;\n \n+\t\tsecuram: securam@e0000000 {\n+\t\t\tcompatible = \"microchip,sama7g5-securam\", \"atmel,sama5d2-securam\", \"mmio-sram\";\n+\t\t\treg = <0xe0000000 0x4000>;\n+\t\t\tclocks = <&pmc PMC_TYPE_PERIPHERAL 18>;\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <1>;\n+\t\t\tranges = <0 0xe0000000 0x4000>;\n+\t\t\tno-memory-wc;\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\n \t\tsecumod: secumod@e0004000 {\n \t\t\tcompatible = \"microchip,sama7g5-secumod\", \"atmel,sama5d2-secumod\", \"syscon\";\n \t\t\treg = <0xe0004000 0x4000>;\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/226-ARM-dts-at91-sama7g5-add-shdwc-node.patch",
    "content": "From 372fa27d07f66f97a4bf45621c1b840ce8417a85 Mon Sep 17 00:00:00 2001\nFrom: Claudiu Beznea <claudiu.beznea@microchip.com>\nDate: Mon, 23 Aug 2021 16:19:15 +0300\nSubject: [PATCH 226/247] ARM: dts: at91: sama7g5: add shdwc node\n\nAdd shutdown controller node and enable it.\n\nSigned-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>\nSigned-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>\nLink: https://lore.kernel.org/r/20210823131915.23857-5-claudiu.beznea@microchip.com\n---\n arch/arm/boot/dts/at91-sama7g5ek.dts |  9 +++++++++\n arch/arm/boot/dts/sama7g5.dtsi       | 11 +++++++++++\n 2 files changed, 20 insertions(+)\n\n--- a/arch/arm/boot/dts/at91-sama7g5ek.dts\n+++ b/arch/arm/boot/dts/at91-sama7g5ek.dts\n@@ -634,6 +634,15 @@\n \tpinctrl-0 = <&pinctrl_sdmmc2_default>;\n };\n \n+&shdwc {\n+\tatmel,shdwc-debouncer = <976>;\n+\tstatus = \"okay\";\n+\n+\tinput@0 {\n+\t\treg = <0>;\n+\t};\n+};\n+\n &spdifrx {\n \tpinctrl-names = \"default\";\n \tpinctrl-0 = <&pinctrl_spdifrx_default>;\n--- a/arch/arm/boot/dts/sama7g5.dtsi\n+++ b/arch/arm/boot/dts/sama7g5.dtsi\n@@ -122,6 +122,17 @@\n \t\t\tclock-names = \"td_slck\", \"md_slck\", \"main_xtal\";\n \t\t};\n \n+\t\tshdwc: shdwc@e001d010 {\n+\t\t\tcompatible = \"microchip,sama7g5-shdwc\", \"syscon\";\n+\t\t\treg = <0xe001d010 0x10>;\n+\t\t\tclocks = <&clk32k 0>;\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tatmel,wakeup-rtc-timer;\n+\t\t\tatmel,wakeup-rtt-timer;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n \t\trtt: rtt@e001d020 {\n \t\t\tcompatible = \"microchip,sama7g5-rtt\", \"microchip,sam9x60-rtt\", \"atmel,at91sam9260-rtt\";\n \t\t\treg = <0xe001d020 0x30>;\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/227-ARM-dts-at91-sama7g5-add-chipid.patch",
    "content": "From d216c1ecf978574216ece8140146c8dc0ea400e3 Mon Sep 17 00:00:00 2001\nFrom: Claudiu Beznea <claudiu.beznea@microchip.com>\nDate: Wed, 8 Sep 2021 12:43:29 +0300\nSubject: [PATCH 227/247] ARM: dts: at91: sama7g5: add chipid\n\nAdd chipid node for sama7g5.\n\nSigned-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>\nSigned-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>\nLink: https://lore.kernel.org/r/20210908094329.182477-1-claudiu.beznea@microchip.com\n---\n arch/arm/boot/dts/sama7g5.dtsi | 5 +++++\n 1 file changed, 5 insertions(+)\n\n--- a/arch/arm/boot/dts/sama7g5.dtsi\n+++ b/arch/arm/boot/dts/sama7g5.dtsi\n@@ -159,6 +159,11 @@\n \t\t\tclocks = <&clk32k 0>;\n \t\t};\n \n+\t\tchipid@e0020000 {\n+\t\t\tcompatible = \"microchip,sama7g5-chipid\";\n+\t\t\treg = <0xe0020000 0x8>;\n+\t\t};\n+\n \t\tsdmmc0: mmc@e1204000 {\n \t\t\tcompatible = \"microchip,sama7g5-sdhci\", \"microchip,sam9x60-sdhci\";\n \t\t\treg = <0xe1204000 0x4000>;\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/228-ARM-at91-pm-switch-backup-area-to-vbat-in-backup-mod.patch",
    "content": "From 2cd84ddf0e9623c6bc723b1df368cd8b16a3a8e2 Mon Sep 17 00:00:00 2001\nFrom: Claudiu Beznea <claudiu.beznea@microchip.com>\nDate: Mon, 30 Aug 2021 13:09:27 +0300\nSubject: [PATCH 228/247] ARM: at91: pm: switch backup area to vbat in backup\n mode\n\nBackup area is now switched to VDDIN33 at boot (with the help of\nbootloader). When switching to backup mode we need to switch backup area\nto VBAT as all the other power sources are cut off. The resuming from\nbackup mode is done with the help of bootloader, so there is no need to\ndo something particular in Linux to restore backup area power source.\n\nSigned-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>\nSigned-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>\nLink: https://lore.kernel.org/r/20210830100927.22711-1-claudiu.beznea@microchip.com\n---\n arch/arm/mach-at91/pm.c | 52 +++++++++++++++++++++++++++++++++++++++++\n 1 file changed, 52 insertions(+)\n\n--- a/arch/arm/mach-at91/pm.c\n+++ b/arch/arm/mach-at91/pm.c\n@@ -47,12 +47,26 @@ struct at91_pm_bu {\n \tunsigned long ddr_phy_calibration[BACKUP_DDR_PHY_CALIBRATION];\n };\n \n+/*\n+ * struct at91_pm_sfrbu_offsets: registers mapping for SFRBU\n+ * @pswbu: power switch BU control registers\n+ */\n+struct at91_pm_sfrbu_regs {\n+\tstruct {\n+\t\tu32 key;\n+\t\tu32 ctrl;\n+\t\tu32 state;\n+\t\tu32 softsw;\n+\t} pswbu;\n+};\n+\n /**\n  * struct at91_soc_pm - AT91 SoC power management data structure\n  * @config_shdwc_ws: wakeup sources configuration function for SHDWC\n  * @config_pmc_ws: wakeup srouces configuration function for PMC\n  * @ws_ids: wakup sources of_device_id array\n  * @data: PM data to be used on last phase of suspend\n+ * @sfrbu_regs: SFRBU registers mapping\n  * @bu: backup unit mapped data (for backup mode)\n  * @memcs: memory chip select\n  */\n@@ -62,6 +76,7 @@ struct at91_soc_pm {\n \tconst struct of_device_id *ws_ids;\n \tstruct at91_pm_bu *bu;\n \tstruct at91_pm_data data;\n+\tstruct at91_pm_sfrbu_regs sfrbu_regs;\n \tvoid *memcs;\n };\n \n@@ -356,9 +371,36 @@ static int at91_suspend_finish(unsigned\n \treturn 0;\n }\n \n+static void at91_pm_switch_ba_to_vbat(void)\n+{\n+\tunsigned int offset = offsetof(struct at91_pm_sfrbu_regs, pswbu);\n+\tunsigned int val;\n+\n+\t/* Just for safety. */\n+\tif (!soc_pm.data.sfrbu)\n+\t\treturn;\n+\n+\tval = readl(soc_pm.data.sfrbu + offset);\n+\n+\t/* Already on VBAT. */\n+\tif (!(val & soc_pm.sfrbu_regs.pswbu.state))\n+\t\treturn;\n+\n+\tval &= ~soc_pm.sfrbu_regs.pswbu.softsw;\n+\tval |= soc_pm.sfrbu_regs.pswbu.key | soc_pm.sfrbu_regs.pswbu.ctrl;\n+\twritel(val, soc_pm.data.sfrbu + offset);\n+\n+\t/* Wait for update. */\n+\tval = readl(soc_pm.data.sfrbu + offset);\n+\twhile (val & soc_pm.sfrbu_regs.pswbu.state)\n+\t\tval = readl(soc_pm.data.sfrbu + offset);\n+}\n+\n static void at91_pm_suspend(suspend_state_t state)\n {\n \tif (soc_pm.data.mode == AT91_PM_BACKUP) {\n+\t\tat91_pm_switch_ba_to_vbat();\n+\n \t\tcpu_suspend(0, at91_suspend_finish);\n \n \t\t/* The SRAM is lost between suspend cycles */\n@@ -1155,6 +1197,11 @@ void __init sama5d2_pm_init(void)\n \tsoc_pm.ws_ids = sama5d2_ws_ids;\n \tsoc_pm.config_shdwc_ws = at91_sama5d2_config_shdwc_ws;\n \tsoc_pm.config_pmc_ws = at91_sama5d2_config_pmc_ws;\n+\n+\tsoc_pm.sfrbu_regs.pswbu.key = (0x4BD20C << 8);\n+\tsoc_pm.sfrbu_regs.pswbu.ctrl = BIT(0);\n+\tsoc_pm.sfrbu_regs.pswbu.softsw = BIT(1);\n+\tsoc_pm.sfrbu_regs.pswbu.state = BIT(3);\n }\n \n void __init sama7_pm_init(void)\n@@ -1185,6 +1232,11 @@ void __init sama7_pm_init(void)\n \n \tsoc_pm.ws_ids = sama7g5_ws_ids;\n \tsoc_pm.config_pmc_ws = at91_sam9x60_config_pmc_ws;\n+\n+\tsoc_pm.sfrbu_regs.pswbu.key = (0x4BD20C << 8);\n+\tsoc_pm.sfrbu_regs.pswbu.ctrl = BIT(0);\n+\tsoc_pm.sfrbu_regs.pswbu.softsw = BIT(1);\n+\tsoc_pm.sfrbu_regs.pswbu.state = BIT(2);\n }\n \n static int __init at91_pm_modes_select(char *str)\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/229-ARM-dts-at91-sama7g5ek-add-suspend-voltage-for-ddr3l.patch",
    "content": "From e5f87471392b344b1261d1eaf93fd44710587ea9 Mon Sep 17 00:00:00 2001\nFrom: Claudiu Beznea <claudiu.beznea@microchip.com>\nDate: Thu, 30 Sep 2021 18:42:17 +0300\nSubject: [PATCH 229/247] ARM: dts: at91: sama7g5ek: add suspend voltage for\n ddr3l rail\n\nSAMA7G5-EK board has DDR3L type of memory soldered. This needs 1.35V. The\n1.35V for DDR3L rail at run-time is selected by the proper configuration\non SELV2 pin (for 1.35V it needs to be in high-z state). When suspended\nthe MCP16502 PMIC soldered on SAMA7G5-EK will use different sets of\nconfiguration registers to provide proper voltages on its rail. Run-time\nconfiguration registers could be configured differently than suspend\nconfiguration register for MCP16502 (VSEL2 affects only run-time\nconfiguration). In suspend states the DDR3L memory soldered on SAMA7G5-EK\nswitches to self-refresh. Even on self-refresh it needs to be powered by\na 1.35V rail. Thus, make sure the PMIC is configured properly when system\nis suspended.\n\nFixes: 7540629e2fc7 (ARM: dts: at91: add sama7g5 SoC DT and sama7g5-ek\")\nSigned-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>\nSigned-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>\nLink: https://lore.kernel.org/r/20210930154219.2214051-2-claudiu.beznea@microchip.com\n---\n arch/arm/boot/dts/at91-sama7g5ek.dts | 2 ++\n 1 file changed, 2 insertions(+)\n\n--- a/arch/arm/boot/dts/at91-sama7g5ek.dts\n+++ b/arch/arm/boot/dts/at91-sama7g5ek.dts\n@@ -196,11 +196,13 @@\n \n \t\t\t\t\tregulator-state-standby {\n \t\t\t\t\t\tregulator-on-in-suspend;\n+\t\t\t\t\t\tregulator-suspend-microvolt = <1350000>;\n \t\t\t\t\t\tregulator-mode = <4>;\n \t\t\t\t\t};\n \n \t\t\t\t\tregulator-state-mem {\n \t\t\t\t\t\tregulator-on-in-suspend;\n+\t\t\t\t\t\tregulator-suspend-microvolt = <1350000>;\n \t\t\t\t\t\tregulator-mode = <4>;\n \t\t\t\t\t};\n \t\t\t\t};\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/230-ARM-at91-pm-group-constants-and-addresses-loading.patch",
    "content": "From 12330a9f6b99622e3c21ddcc720b02431b8a6e2d Mon Sep 17 00:00:00 2001\nFrom: Claudiu Beznea <claudiu.beznea@microchip.com>\nDate: Thu, 30 Sep 2021 18:42:18 +0300\nSubject: [PATCH 230/247] ARM: at91: pm: group constants and addresses loading\n\nGroup constants and addresses loading. This commit prepares the field for\nthe next one.\n\nSigned-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>\nSigned-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>\nLink: https://lore.kernel.org/r/20210930154219.2214051-3-claudiu.beznea@microchip.com\n---\n arch/arm/mach-at91/pm_suspend.S | 17 +++++++++--------\n 1 file changed, 9 insertions(+), 8 deletions(-)\n\n--- a/arch/arm/mach-at91/pm_suspend.S\n+++ b/arch/arm/mach-at91/pm_suspend.S\n@@ -1014,6 +1014,15 @@ ENTRY(at91_pm_suspend_in_sram)\n \tmov\ttmp1, #0\n \tmcr\tp15, 0, tmp1, c7, c10, 4\n \n+\tldr\ttmp1, [r0, #PM_DATA_PMC_MCKR_OFFSET]\n+\tstr\ttmp1, .mckr_offset\n+\tldr\ttmp1, [r0, #PM_DATA_PMC_VERSION]\n+\tstr\ttmp1, .pmc_version\n+\tldr\ttmp1, [r0, #PM_DATA_MEMCTRL]\n+\tstr\ttmp1, .memtype\n+\tldr\ttmp1, [r0, #PM_DATA_MODE]\n+\tstr\ttmp1, .pm_mode\n+\n \tldr\ttmp1, [r0, #PM_DATA_PMC]\n \tstr\ttmp1, .pmc_base\n \tldr\ttmp1, [r0, #PM_DATA_RAMC0]\n@@ -1022,14 +1031,6 @@ ENTRY(at91_pm_suspend_in_sram)\n \tstr\ttmp1, .sramc1_base\n \tldr\ttmp1, [r0, #PM_DATA_RAMC_PHY]\n \tstr\ttmp1, .sramc_phy_base\n-\tldr\ttmp1, [r0, #PM_DATA_MEMCTRL]\n-\tstr\ttmp1, .memtype\n-\tldr\ttmp1, [r0, #PM_DATA_MODE]\n-\tstr\ttmp1, .pm_mode\n-\tldr\ttmp1, [r0, #PM_DATA_PMC_MCKR_OFFSET]\n-\tstr\ttmp1, .mckr_offset\n-\tldr\ttmp1, [r0, #PM_DATA_PMC_VERSION]\n-\tstr\ttmp1, .pmc_version\n \t/* Both ldrne below are here to preload their address in the TLB */\n \tldr\ttmp1, [r0, #PM_DATA_SHDWC]\n \tstr\ttmp1, .shdwc\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/231-ARM-at91-pm-preload-base-address-of-controllers-in-t.patch",
    "content": "From 6075bbc75e55258a762d618cd459dbe0dd38aff9 Mon Sep 17 00:00:00 2001\nFrom: Claudiu Beznea <claudiu.beznea@microchip.com>\nDate: Thu, 30 Sep 2021 18:42:19 +0300\nSubject: [PATCH 231/247] ARM: at91: pm: preload base address of controllers in\n tlb\n\nIn suspend/resume procedure for AT91 architecture different controllers\n(PMC, SHDWC, RAM, RAM PHY, SFRBU) are accessed to do the proper settings\nfor power saving. Commit f0bbf17958e8 (\"ARM: at91: pm: add self-refresh\nsupport for sama7g5\") introduced the access to RAMC PHY controller for\nSAMA7G5. The access to this controller is done after RAMC ports are\nclosed, thus any TLB walk necessary for RAMC PHY virtual address will\nfail. In the development branch this was not encountered. However, on\ncurrent kernel the issue is reproducible.\n\nTo solve the issue the previous mechanism of pre-loading the TLB with\nthe RAMC PHY virtual address has been used. However, only the addition\nof this new pre-load breaks the functionality for ARMv5 based\ndevices (SAM9X60). This behavior has been encountered previously\nwhile debugging this code and using the same mechanism for pre-loading\naddress for different controllers (e.g. pin controller, the assumption\nbeing that other requested translations are replaced from TLB).\n\nTo solve this new issue the TLB flush + the extension of pre-loading\nthe rest of controllers to TLB (e.g. PMC, RAMC) has been added. The\nrest of the controllers should have been pre-loaded previously, anyway.\n\nFixes: f0bbf17958e8 (\"ARM: at91: pm: add self-refresh support for sama7g5\")\nDepends-on: e42cbbe5c9a2 (\"ARM: at91: pm: group constants and addresses loading\")\nSigned-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>\nSigned-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>\nLink: https://lore.kernel.org/r/20210930154219.2214051-4-claudiu.beznea@microchip.com\n---\n arch/arm/mach-at91/pm_suspend.S | 25 ++++++++++++++++++++++++-\n 1 file changed, 24 insertions(+), 1 deletion(-)\n\n--- a/arch/arm/mach-at91/pm_suspend.S\n+++ b/arch/arm/mach-at91/pm_suspend.S\n@@ -1014,6 +1014,10 @@ ENTRY(at91_pm_suspend_in_sram)\n \tmov\ttmp1, #0\n \tmcr\tp15, 0, tmp1, c7, c10, 4\n \n+\t/* Flush tlb. */\n+\tmov\tr4, #0\n+\tmcr\tp15, 0, r4, c8, c7, 0\n+\n \tldr\ttmp1, [r0, #PM_DATA_PMC_MCKR_OFFSET]\n \tstr\ttmp1, .mckr_offset\n \tldr\ttmp1, [r0, #PM_DATA_PMC_VERSION]\n@@ -1023,23 +1027,42 @@ ENTRY(at91_pm_suspend_in_sram)\n \tldr\ttmp1, [r0, #PM_DATA_MODE]\n \tstr\ttmp1, .pm_mode\n \n+\t/*\n+\t * ldrne below are here to preload their address in the TLB as access\n+\t * to RAM may be limited while in self-refresh.\n+\t */\n \tldr\ttmp1, [r0, #PM_DATA_PMC]\n \tstr\ttmp1, .pmc_base\n+\tcmp\ttmp1, #0\n+\tldrne\ttmp2, [tmp1, #0]\n+\n \tldr\ttmp1, [r0, #PM_DATA_RAMC0]\n \tstr\ttmp1, .sramc_base\n+\tcmp\ttmp1, #0\n+\tldrne\ttmp2, [tmp1, #0]\n+\n \tldr\ttmp1, [r0, #PM_DATA_RAMC1]\n \tstr\ttmp1, .sramc1_base\n+\tcmp\ttmp1, #0\n+\tldrne\ttmp2, [tmp1, #0]\n+\n+#ifndef CONFIG_SOC_SAM_V4_V5\n+\t/* ldrne below are here to preload their address in the TLB */\n \tldr\ttmp1, [r0, #PM_DATA_RAMC_PHY]\n \tstr\ttmp1, .sramc_phy_base\n-\t/* Both ldrne below are here to preload their address in the TLB */\n+\tcmp\ttmp1, #0\n+\tldrne\ttmp2, [tmp1, #0]\n+\n \tldr\ttmp1, [r0, #PM_DATA_SHDWC]\n \tstr\ttmp1, .shdwc\n \tcmp\ttmp1, #0\n \tldrne\ttmp2, [tmp1, #0]\n+\n \tldr\ttmp1, [r0, #PM_DATA_SFRBU]\n \tstr\ttmp1, .sfrbu\n \tcmp\ttmp1, #0\n \tldrne\ttmp2, [tmp1, #0x10]\n+#endif\n \n \t/* Active the self-refresh mode */\n \tat91_sramc_self_refresh_ena\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/232-ARM-dts-at91-sama7g5ek-use-proper-slew-rate-settings.patch",
    "content": "From 98d2c4ca97dde30616fa78ad5677825b1966cec6 Mon Sep 17 00:00:00 2001\nFrom: Claudiu Beznea <claudiu.beznea@microchip.com>\nDate: Wed, 15 Sep 2021 10:48:35 +0300\nSubject: [PATCH 232/247] ARM: dts: at91: sama7g5ek: use proper slew-rate\n settings for GMACs\n\nDatasheet chapter \"EMAC Timings\" specifies that while in 3.3V domain\nGMAC's MDIO pins should be configured with slew-rate enabled, while the\ndata + signaling pins should be configured with slew-rate disabled when\nGMAC works in RGMII or RMII modes. The pin controller for SAMA7G5 sets\nthe slew-rate as enabled for all pins. Adapt the device tree to comply\nwith these.\n\nFixes: 7540629e2fc7 (\"ARM: dts: at91: add sama7g5 SoC DT and sama7g5-ek\")\nSigned-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>\nSigned-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>\nLink: https://lore.kernel.org/r/20210915074836.6574-2-claudiu.beznea@microchip.com\n---\n arch/arm/boot/dts/at91-sama7g5ek.dts | 28 ++++++++++++++++++++++------\n 1 file changed, 22 insertions(+), 6 deletions(-)\n\n--- a/arch/arm/boot/dts/at91-sama7g5ek.dts\n+++ b/arch/arm/boot/dts/at91-sama7g5ek.dts\n@@ -355,7 +355,10 @@\n \t#address-cells = <1>;\n \t#size-cells = <0>;\n \tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&pinctrl_gmac0_default &pinctrl_gmac0_txck_default &pinctrl_gmac0_phy_irq>;\n+\tpinctrl-0 = <&pinctrl_gmac0_default\n+\t\t     &pinctrl_gmac0_mdio_default\n+\t\t     &pinctrl_gmac0_txck_default\n+\t\t     &pinctrl_gmac0_phy_irq>;\n \tphy-mode = \"rgmii-id\";\n \tstatus = \"okay\";\n \n@@ -370,7 +373,9 @@\n \t#address-cells = <1>;\n \t#size-cells = <0>;\n \tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&pinctrl_gmac1_default &pinctrl_gmac1_phy_irq>;\n+\tpinctrl-0 = <&pinctrl_gmac1_default\n+\t\t     &pinctrl_gmac1_mdio_default\n+\t\t     &pinctrl_gmac1_phy_irq>;\n \tphy-mode = \"rmii\";\n \tstatus = \"okay\";\n \n@@ -425,14 +430,20 @@\n \t\t\t <PIN_PA15__G0_TXEN>,\n \t\t\t <PIN_PA30__G0_RXCK>,\n \t\t\t <PIN_PA18__G0_RXDV>,\n-\t\t\t <PIN_PA22__G0_MDC>,\n-\t\t\t <PIN_PA23__G0_MDIO>,\n \t\t\t <PIN_PA25__G0_125CK>;\n+\t\tslew-rate = <0>;\n+\t\tbias-disable;\n+\t};\n+\n+\tpinctrl_gmac0_mdio_default: gmac0_mdio_default {\n+\t\tpinmux = <PIN_PA22__G0_MDC>,\n+\t\t\t <PIN_PA23__G0_MDIO>;\n \t\tbias-disable;\n \t};\n \n \tpinctrl_gmac0_txck_default: gmac0_txck_default {\n \t\tpinmux = <PIN_PA24__G0_TXCK>;\n+\t\tslew-rate = <0>;\n \t\tbias-pull-up;\n \t};\n \n@@ -449,8 +460,13 @@\n \t\t\t <PIN_PD25__G1_RX0>,\n \t\t\t <PIN_PD26__G1_RX1>,\n \t\t\t <PIN_PD27__G1_RXER>,\n-\t\t\t <PIN_PD24__G1_RXDV>,\n-\t\t\t <PIN_PD28__G1_MDC>,\n+\t\t\t <PIN_PD24__G1_RXDV>;\n+\t\tslew-rate = <0>;\n+\t\tbias-disable;\n+\t};\n+\n+\tpinctrl_gmac1_mdio_default: gmac1_mdio_default {\n+\t\tpinmux = <PIN_PD28__G1_MDC>,\n \t\t\t <PIN_PD29__G1_MDIO>;\n \t\tbias-disable;\n \t};\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/233-ARM-dts-at91-sama7g5ek-to-not-touch-slew-rate-for-SD.patch",
    "content": "From 4c0b77276307d2cba8ae2595cbae4cc916c84c36 Mon Sep 17 00:00:00 2001\nFrom: Claudiu Beznea <claudiu.beznea@microchip.com>\nDate: Wed, 15 Sep 2021 10:48:36 +0300\nSubject: [PATCH 233/247] ARM: dts: at91: sama7g5ek: to not touch slew-rate for\n SDMMC pins\n\nWith commit c709135e576b (\"pinctrl: at91-pio4: add support for slew-rate\")\nand commit cbde6c823bfa (\"pinctrl: at91-pio4: Fix slew rate disablement\")\nthe slew-rate is enabled by default for each configured pin. The datasheet\nspecifies at chapter \"Output Driver AC Characteristics\" that HSIO\ndrivers (use in SDMMCx and QSPI0 peripherals), don't have a slewrate\nsetting but are rather calibrated against an external 1% resistor mounted\non the SDMMCx_CAL or QSPI0_CAL pins. Depending on the target signal\nfrequency and the external load, it is possible to adjust their target\noutput impedance. Thus set slew-rate = <0> for SDMMC (QSPI is not enabled\nat the moment in device tree).\n\nFixes: 7540629e2fc7 (\"ARM: dts: at91: add sama7g5 SoC DT and sama7g5-ek\")\nSigned-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>\nSigned-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>\nLink: https://lore.kernel.org/r/20210915074836.6574-3-claudiu.beznea@microchip.com\n---\n arch/arm/boot/dts/at91-sama7g5ek.dts | 6 ++++++\n 1 file changed, 6 insertions(+)\n\n--- a/arch/arm/boot/dts/at91-sama7g5ek.dts\n+++ b/arch/arm/boot/dts/at91-sama7g5ek.dts\n@@ -558,6 +558,7 @@\n \t\t\t\t <PIN_PA8__SDMMC0_DAT5>,\n \t\t\t\t <PIN_PA9__SDMMC0_DAT6>,\n \t\t\t\t <PIN_PA10__SDMMC0_DAT7>;\n+\t\t\tslew-rate = <0>;\n \t\t\tbias-pull-up;\n \t\t};\n \n@@ -565,6 +566,7 @@\n \t\t\tpinmux = <PIN_PA0__SDMMC0_CK>,\n \t\t\t\t <PIN_PA2__SDMMC0_RSTN>,\n \t\t\t\t <PIN_PA11__SDMMC0_DS>;\n+\t\t\tslew-rate = <0>;\n \t\t\tbias-pull-up;\n \t\t};\n \t};\n@@ -576,6 +578,7 @@\n \t\t\t\t <PIN_PC0__SDMMC1_DAT1>,\n \t\t\t\t <PIN_PC1__SDMMC1_DAT2>,\n \t\t\t\t <PIN_PC2__SDMMC1_DAT3>;\n+\t\t\tslew-rate = <0>;\n \t\t\tbias-pull-up;\n \t\t};\n \n@@ -584,6 +587,7 @@\n \t\t\t\t <PIN_PB28__SDMMC1_RSTN>,\n \t\t\t\t <PIN_PC5__SDMMC1_1V8SEL>,\n \t\t\t\t <PIN_PC4__SDMMC1_CD>;\n+\t\t\tslew-rate = <0>;\n \t\t\tbias-pull-up;\n \t\t};\n \t};\n@@ -595,11 +599,13 @@\n \t\t\t\t <PIN_PD6__SDMMC2_DAT1>,\n \t\t\t\t <PIN_PD7__SDMMC2_DAT2>,\n \t\t\t\t <PIN_PD8__SDMMC2_DAT3>;\n+\t\t\tslew-rate = <0>;\n \t\t\tbias-pull-up;\n \t\t};\n \n \t\tck {\n \t\t\tpinmux = <PIN_PD4__SDMMC2_CK>;\n+\t\t\tslew-rate = <0>;\n \t\t\tbias-pull-up;\n \t\t};\n \t};\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/234-clk-at91-re-factor-clocks-suspend-resume.patch",
    "content": "From 65bb4687b2a5c6f02f44345540c3389d6e7523e7 Mon Sep 17 00:00:00 2001\nFrom: Claudiu Beznea <claudiu.beznea@microchip.com>\nDate: Mon, 11 Oct 2021 14:27:05 +0300\nSubject: [PATCH 234/247] clk: at91: re-factor clocks suspend/resume\n\nSAMA5D2 and SAMA7G5 have a special power saving mode (backup mode) where\nmost of the SoC's components are powered off (including PMC). Resuming\nfrom this mode is done with the help of bootloader. Peripherals are not\naware of the power saving mode thus most of them are disabling clocks in\nproper suspend API and re-enable them in resume API without taking into\naccount the previously setup rate. Moreover some of the peripherals are\nacting as wakeup sources and are not disabling the clocks in this\nscenario, when suspending. Since backup mode cuts the power for\nperipherals, in resume part these clocks needs to be re-configured.\n\nThe initial PMC suspend/resume code was designed only for SAMA5D2's PMC\n(as it was the only one supporting backup mode). SAMA7G supports also\nbackup mode and its PMC is different (few new functionalities, different\nregisters offsets, different offsets in registers for each\nfunctionalities). To address both SAMA5D2 and SAMA7G5 PMC add\n.save_context()/.resume_context() support to each clocks driver and call\nthis from PMC driver.\n\nSigned-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>\nLink: https://lore.kernel.org/r/20211011112719.3951784-2-claudiu.beznea@microchip.com\nAcked-by: Nicolas Ferre <nicolas.ferre@microchip.com>\nSigned-off-by: Stephen Boyd <sboyd@kernel.org>\n---\n drivers/clk/at91/clk-generated.c    |  46 +++++--\n drivers/clk/at91/clk-main.c         |  66 ++++++++++\n drivers/clk/at91/clk-master.c       | 194 ++++++++++++++++++++++++++--\n drivers/clk/at91/clk-peripheral.c   |  40 +++++-\n drivers/clk/at91/clk-pll.c          |  39 ++++++\n drivers/clk/at91/clk-programmable.c |  29 ++++-\n drivers/clk/at91/clk-sam9x60-pll.c  |  68 +++++++++-\n drivers/clk/at91/clk-system.c       |  20 +++\n drivers/clk/at91/clk-usb.c          |  27 ++++\n drivers/clk/at91/clk-utmi.c         |  39 ++++++\n drivers/clk/at91/pmc.c              | 147 +--------------------\n drivers/clk/at91/pmc.h              |  24 ++--\n 12 files changed, 558 insertions(+), 181 deletions(-)\n\n--- a/drivers/clk/at91/clk-generated.c\n+++ b/drivers/clk/at91/clk-generated.c\n@@ -27,6 +27,7 @@ struct clk_generated {\n \tu32 id;\n \tu32 gckdiv;\n \tconst struct clk_pcr_layout *layout;\n+\tstruct at91_clk_pms pms;\n \tu8 parent_id;\n \tint chg_pid;\n };\n@@ -34,25 +35,35 @@ struct clk_generated {\n #define to_clk_generated(hw) \\\n \tcontainer_of(hw, struct clk_generated, hw)\n \n-static int clk_generated_enable(struct clk_hw *hw)\n+static int clk_generated_set(struct clk_generated *gck, int status)\n {\n-\tstruct clk_generated *gck = to_clk_generated(hw);\n \tunsigned long flags;\n-\n-\tpr_debug(\"GCLK: %s, gckdiv = %d, parent id = %d\\n\",\n-\t\t __func__, gck->gckdiv, gck->parent_id);\n+\tunsigned int enable = status ? AT91_PMC_PCR_GCKEN : 0;\n \n \tspin_lock_irqsave(gck->lock, flags);\n \tregmap_write(gck->regmap, gck->layout->offset,\n \t\t     (gck->id & gck->layout->pid_mask));\n \tregmap_update_bits(gck->regmap, gck->layout->offset,\n \t\t\t   AT91_PMC_PCR_GCKDIV_MASK | gck->layout->gckcss_mask |\n-\t\t\t   gck->layout->cmd | AT91_PMC_PCR_GCKEN,\n+\t\t\t   gck->layout->cmd | enable,\n \t\t\t   field_prep(gck->layout->gckcss_mask, gck->parent_id) |\n \t\t\t   gck->layout->cmd |\n \t\t\t   FIELD_PREP(AT91_PMC_PCR_GCKDIV_MASK, gck->gckdiv) |\n-\t\t\t   AT91_PMC_PCR_GCKEN);\n+\t\t\t   enable);\n \tspin_unlock_irqrestore(gck->lock, flags);\n+\n+\treturn 0;\n+}\n+\n+static int clk_generated_enable(struct clk_hw *hw)\n+{\n+\tstruct clk_generated *gck = to_clk_generated(hw);\n+\n+\tpr_debug(\"GCLK: %s, gckdiv = %d, parent id = %d\\n\",\n+\t\t __func__, gck->gckdiv, gck->parent_id);\n+\n+\tclk_generated_set(gck, 1);\n+\n \treturn 0;\n }\n \n@@ -245,6 +256,23 @@ static int clk_generated_set_rate(struct\n \treturn 0;\n }\n \n+static int clk_generated_save_context(struct clk_hw *hw)\n+{\n+\tstruct clk_generated *gck = to_clk_generated(hw);\n+\n+\tgck->pms.status = clk_generated_is_enabled(&gck->hw);\n+\n+\treturn 0;\n+}\n+\n+static void clk_generated_restore_context(struct clk_hw *hw)\n+{\n+\tstruct clk_generated *gck = to_clk_generated(hw);\n+\n+\tif (gck->pms.status)\n+\t\tclk_generated_set(gck, gck->pms.status);\n+}\n+\n static const struct clk_ops generated_ops = {\n \t.enable = clk_generated_enable,\n \t.disable = clk_generated_disable,\n@@ -254,6 +282,8 @@ static const struct clk_ops generated_op\n \t.get_parent = clk_generated_get_parent,\n \t.set_parent = clk_generated_set_parent,\n \t.set_rate = clk_generated_set_rate,\n+\t.save_context = clk_generated_save_context,\n+\t.restore_context = clk_generated_restore_context,\n };\n \n /**\n@@ -320,8 +350,6 @@ at91_clk_register_generated(struct regma\n \tif (ret) {\n \t\tkfree(gck);\n \t\thw = ERR_PTR(ret);\n-\t} else {\n-\t\tpmc_register_id(id);\n \t}\n \n \treturn hw;\n--- a/drivers/clk/at91/clk-main.c\n+++ b/drivers/clk/at91/clk-main.c\n@@ -28,6 +28,7 @@\n struct clk_main_osc {\n \tstruct clk_hw hw;\n \tstruct regmap *regmap;\n+\tstruct at91_clk_pms pms;\n };\n \n #define to_clk_main_osc(hw) container_of(hw, struct clk_main_osc, hw)\n@@ -37,6 +38,7 @@ struct clk_main_rc_osc {\n \tstruct regmap *regmap;\n \tunsigned long frequency;\n \tunsigned long accuracy;\n+\tstruct at91_clk_pms pms;\n };\n \n #define to_clk_main_rc_osc(hw) container_of(hw, struct clk_main_rc_osc, hw)\n@@ -51,6 +53,7 @@ struct clk_rm9200_main {\n struct clk_sam9x5_main {\n \tstruct clk_hw hw;\n \tstruct regmap *regmap;\n+\tstruct at91_clk_pms pms;\n \tu8 parent;\n };\n \n@@ -120,10 +123,29 @@ static int clk_main_osc_is_prepared(stru\n \treturn (status & AT91_PMC_MOSCS) && clk_main_parent_select(tmp);\n }\n \n+static int clk_main_osc_save_context(struct clk_hw *hw)\n+{\n+\tstruct clk_main_osc *osc = to_clk_main_osc(hw);\n+\n+\tosc->pms.status = clk_main_osc_is_prepared(hw);\n+\n+\treturn 0;\n+}\n+\n+static void clk_main_osc_restore_context(struct clk_hw *hw)\n+{\n+\tstruct clk_main_osc *osc = to_clk_main_osc(hw);\n+\n+\tif (osc->pms.status)\n+\t\tclk_main_osc_prepare(hw);\n+}\n+\n static const struct clk_ops main_osc_ops = {\n \t.prepare = clk_main_osc_prepare,\n \t.unprepare = clk_main_osc_unprepare,\n \t.is_prepared = clk_main_osc_is_prepared,\n+\t.save_context = clk_main_osc_save_context,\n+\t.restore_context = clk_main_osc_restore_context,\n };\n \n struct clk_hw * __init\n@@ -240,12 +262,31 @@ static unsigned long clk_main_rc_osc_rec\n \treturn osc->accuracy;\n }\n \n+static int clk_main_rc_osc_save_context(struct clk_hw *hw)\n+{\n+\tstruct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw);\n+\n+\tosc->pms.status = clk_main_rc_osc_is_prepared(hw);\n+\n+\treturn 0;\n+}\n+\n+static void clk_main_rc_osc_restore_context(struct clk_hw *hw)\n+{\n+\tstruct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw);\n+\n+\tif (osc->pms.status)\n+\t\tclk_main_rc_osc_prepare(hw);\n+}\n+\n static const struct clk_ops main_rc_osc_ops = {\n \t.prepare = clk_main_rc_osc_prepare,\n \t.unprepare = clk_main_rc_osc_unprepare,\n \t.is_prepared = clk_main_rc_osc_is_prepared,\n \t.recalc_rate = clk_main_rc_osc_recalc_rate,\n \t.recalc_accuracy = clk_main_rc_osc_recalc_accuracy,\n+\t.save_context = clk_main_rc_osc_save_context,\n+\t.restore_context = clk_main_rc_osc_restore_context,\n };\n \n struct clk_hw * __init\n@@ -465,12 +506,37 @@ static u8 clk_sam9x5_main_get_parent(str\n \treturn clk_main_parent_select(status);\n }\n \n+static int clk_sam9x5_main_save_context(struct clk_hw *hw)\n+{\n+\tstruct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw);\n+\n+\tclkmain->pms.status = clk_main_rc_osc_is_prepared(&clkmain->hw);\n+\tclkmain->pms.parent = clk_sam9x5_main_get_parent(&clkmain->hw);\n+\n+\treturn 0;\n+}\n+\n+static void clk_sam9x5_main_restore_context(struct clk_hw *hw)\n+{\n+\tstruct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw);\n+\tint ret;\n+\n+\tret = clk_sam9x5_main_set_parent(hw, clkmain->pms.parent);\n+\tif (ret)\n+\t\treturn;\n+\n+\tif (clkmain->pms.status)\n+\t\tclk_sam9x5_main_prepare(hw);\n+}\n+\n static const struct clk_ops sam9x5_main_ops = {\n \t.prepare = clk_sam9x5_main_prepare,\n \t.is_prepared = clk_sam9x5_main_is_prepared,\n \t.recalc_rate = clk_sam9x5_main_recalc_rate,\n \t.set_parent = clk_sam9x5_main_set_parent,\n \t.get_parent = clk_sam9x5_main_get_parent,\n+\t.save_context = clk_sam9x5_main_save_context,\n+\t.restore_context = clk_sam9x5_main_restore_context,\n };\n \n struct clk_hw * __init\n--- a/drivers/clk/at91/clk-master.c\n+++ b/drivers/clk/at91/clk-master.c\n@@ -37,6 +37,7 @@ struct clk_master {\n \tspinlock_t *lock;\n \tconst struct clk_master_layout *layout;\n \tconst struct clk_master_characteristics *characteristics;\n+\tstruct at91_clk_pms pms;\n \tu32 *mux_table;\n \tu32 mckr;\n \tint chg_pid;\n@@ -112,10 +113,52 @@ static unsigned long clk_master_div_reca\n \treturn rate;\n }\n \n+static int clk_master_div_save_context(struct clk_hw *hw)\n+{\n+\tstruct clk_master *master = to_clk_master(hw);\n+\tstruct clk_hw *parent_hw = clk_hw_get_parent(hw);\n+\tunsigned long flags;\n+\tunsigned int mckr, div;\n+\n+\tspin_lock_irqsave(master->lock, flags);\n+\tregmap_read(master->regmap, master->layout->offset, &mckr);\n+\tspin_unlock_irqrestore(master->lock, flags);\n+\n+\tmckr &= master->layout->mask;\n+\tdiv = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK;\n+\tdiv = master->characteristics->divisors[div];\n+\n+\tmaster->pms.parent_rate = clk_hw_get_rate(parent_hw);\n+\tmaster->pms.rate = DIV_ROUND_CLOSEST(master->pms.parent_rate, div);\n+\n+\treturn 0;\n+}\n+\n+static void clk_master_div_restore_context(struct clk_hw *hw)\n+{\n+\tstruct clk_master *master = to_clk_master(hw);\n+\tunsigned long flags;\n+\tunsigned int mckr;\n+\tu8 div;\n+\n+\tspin_lock_irqsave(master->lock, flags);\n+\tregmap_read(master->regmap, master->layout->offset, &mckr);\n+\tspin_unlock_irqrestore(master->lock, flags);\n+\n+\tmckr &= master->layout->mask;\n+\tdiv = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK;\n+\tdiv = master->characteristics->divisors[div];\n+\n+\tif (div != DIV_ROUND_CLOSEST(master->pms.parent_rate, master->pms.rate))\n+\t\tpr_warn(\"MCKR DIV not configured properly by firmware!\\n\");\n+}\n+\n static const struct clk_ops master_div_ops = {\n \t.prepare = clk_master_prepare,\n \t.is_prepared = clk_master_is_prepared,\n \t.recalc_rate = clk_master_div_recalc_rate,\n+\t.save_context = clk_master_div_save_context,\n+\t.restore_context = clk_master_div_restore_context,\n };\n \n static int clk_master_div_set_rate(struct clk_hw *hw, unsigned long rate,\n@@ -125,7 +168,9 @@ static int clk_master_div_set_rate(struc\n \tconst struct clk_master_characteristics *characteristics =\n \t\t\t\t\t\tmaster->characteristics;\n \tunsigned long flags;\n+\tunsigned int mckr, tmp;\n \tint div, i;\n+\tint ret;\n \n \tdiv = DIV_ROUND_CLOSEST(parent_rate, rate);\n \tif (div > ARRAY_SIZE(characteristics->divisors))\n@@ -145,11 +190,24 @@ static int clk_master_div_set_rate(struc\n \t\treturn -EINVAL;\n \n \tspin_lock_irqsave(master->lock, flags);\n-\tregmap_update_bits(master->regmap, master->layout->offset,\n-\t\t\t   (MASTER_DIV_MASK << MASTER_DIV_SHIFT),\n-\t\t\t   (div << MASTER_DIV_SHIFT));\n+\tret = regmap_read(master->regmap, master->layout->offset, &mckr);\n+\tif (ret)\n+\t\tgoto unlock;\n+\n+\ttmp = mckr & master->layout->mask;\n+\ttmp = (tmp >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK;\n+\tif (tmp == div)\n+\t\tgoto unlock;\n+\n+\tmckr &= ~(MASTER_DIV_MASK << MASTER_DIV_SHIFT);\n+\tmckr |= (div << MASTER_DIV_SHIFT);\n+\tret = regmap_write(master->regmap, master->layout->offset, mckr);\n+\tif (ret)\n+\t\tgoto unlock;\n+\n \twhile (!clk_master_ready(master))\n \t\tcpu_relax();\n+unlock:\n \tspin_unlock_irqrestore(master->lock, flags);\n \n \treturn 0;\n@@ -197,12 +255,25 @@ static int clk_master_div_determine_rate\n \treturn 0;\n }\n \n+static void clk_master_div_restore_context_chg(struct clk_hw *hw)\n+{\n+\tstruct clk_master *master = to_clk_master(hw);\n+\tint ret;\n+\n+\tret = clk_master_div_set_rate(hw, master->pms.rate,\n+\t\t\t\t      master->pms.parent_rate);\n+\tif (ret)\n+\t\tpr_warn(\"Failed to restore MCK DIV clock\\n\");\n+}\n+\n static const struct clk_ops master_div_ops_chg = {\n \t.prepare = clk_master_prepare,\n \t.is_prepared = clk_master_is_prepared,\n \t.recalc_rate = clk_master_div_recalc_rate,\n \t.determine_rate = clk_master_div_determine_rate,\n \t.set_rate = clk_master_div_set_rate,\n+\t.save_context = clk_master_div_save_context,\n+\t.restore_context = clk_master_div_restore_context_chg,\n };\n \n static void clk_sama7g5_master_best_diff(struct clk_rate_request *req,\n@@ -272,7 +343,8 @@ static int clk_master_pres_set_rate(stru\n {\n \tstruct clk_master *master = to_clk_master(hw);\n \tunsigned long flags;\n-\tunsigned int pres;\n+\tunsigned int pres, mckr, tmp;\n+\tint ret;\n \n \tpres = DIV_ROUND_CLOSEST(parent_rate, rate);\n \tif (pres > MASTER_PRES_MAX)\n@@ -284,15 +356,27 @@ static int clk_master_pres_set_rate(stru\n \t\tpres = ffs(pres) - 1;\n \n \tspin_lock_irqsave(master->lock, flags);\n-\tregmap_update_bits(master->regmap, master->layout->offset,\n-\t\t\t   (MASTER_PRES_MASK << master->layout->pres_shift),\n-\t\t\t   (pres << master->layout->pres_shift));\n+\tret = regmap_read(master->regmap, master->layout->offset, &mckr);\n+\tif (ret)\n+\t\tgoto unlock;\n+\n+\tmckr &= master->layout->mask;\n+\ttmp = (mckr >> master->layout->pres_shift) & MASTER_PRES_MASK;\n+\tif (pres == tmp)\n+\t\tgoto unlock;\n+\n+\tmckr &= ~(MASTER_PRES_MASK << master->layout->pres_shift);\n+\tmckr |= (pres << master->layout->pres_shift);\n+\tret = regmap_write(master->regmap, master->layout->offset, mckr);\n+\tif (ret)\n+\t\tgoto unlock;\n \n \twhile (!clk_master_ready(master))\n \t\tcpu_relax();\n+unlock:\n \tspin_unlock_irqrestore(master->lock, flags);\n \n-\treturn 0;\n+\treturn ret;\n }\n \n static unsigned long clk_master_pres_recalc_rate(struct clk_hw *hw,\n@@ -330,11 +414,68 @@ static u8 clk_master_pres_get_parent(str\n \treturn mckr & AT91_PMC_CSS;\n }\n \n+static int clk_master_pres_save_context(struct clk_hw *hw)\n+{\n+\tstruct clk_master *master = to_clk_master(hw);\n+\tstruct clk_hw *parent_hw = clk_hw_get_parent(hw);\n+\tunsigned long flags;\n+\tunsigned int val, pres;\n+\n+\tspin_lock_irqsave(master->lock, flags);\n+\tregmap_read(master->regmap, master->layout->offset, &val);\n+\tspin_unlock_irqrestore(master->lock, flags);\n+\n+\tval &= master->layout->mask;\n+\tpres = (val >> master->layout->pres_shift) & MASTER_PRES_MASK;\n+\tif (pres == MASTER_PRES_MAX && master->characteristics->have_div3_pres)\n+\t\tpres = 3;\n+\telse\n+\t\tpres = (1 << pres);\n+\n+\tmaster->pms.parent = val & AT91_PMC_CSS;\n+\tmaster->pms.parent_rate = clk_hw_get_rate(parent_hw);\n+\tmaster->pms.rate = DIV_ROUND_CLOSEST_ULL(master->pms.parent_rate, pres);\n+\n+\treturn 0;\n+}\n+\n+static void clk_master_pres_restore_context(struct clk_hw *hw)\n+{\n+\tstruct clk_master *master = to_clk_master(hw);\n+\tunsigned long flags;\n+\tunsigned int val, pres;\n+\n+\tspin_lock_irqsave(master->lock, flags);\n+\tregmap_read(master->regmap, master->layout->offset, &val);\n+\tspin_unlock_irqrestore(master->lock, flags);\n+\n+\tval &= master->layout->mask;\n+\tpres = (val >> master->layout->pres_shift) & MASTER_PRES_MASK;\n+\tif (pres == MASTER_PRES_MAX && master->characteristics->have_div3_pres)\n+\t\tpres = 3;\n+\telse\n+\t\tpres = (1 << pres);\n+\n+\tif (master->pms.rate !=\n+\t    DIV_ROUND_CLOSEST_ULL(master->pms.parent_rate, pres) ||\n+\t    (master->pms.parent != (val & AT91_PMC_CSS)))\n+\t\tpr_warn(\"MCKR PRES was not configured properly by firmware!\\n\");\n+}\n+\n+static void clk_master_pres_restore_context_chg(struct clk_hw *hw)\n+{\n+\tstruct clk_master *master = to_clk_master(hw);\n+\n+\tclk_master_pres_set_rate(hw, master->pms.rate, master->pms.parent_rate);\n+}\n+\n static const struct clk_ops master_pres_ops = {\n \t.prepare = clk_master_prepare,\n \t.is_prepared = clk_master_is_prepared,\n \t.recalc_rate = clk_master_pres_recalc_rate,\n \t.get_parent = clk_master_pres_get_parent,\n+\t.save_context = clk_master_pres_save_context,\n+\t.restore_context = clk_master_pres_restore_context,\n };\n \n static const struct clk_ops master_pres_ops_chg = {\n@@ -344,6 +485,8 @@ static const struct clk_ops master_pres_\n \t.recalc_rate = clk_master_pres_recalc_rate,\n \t.get_parent = clk_master_pres_get_parent,\n \t.set_rate = clk_master_pres_set_rate,\n+\t.save_context = clk_master_pres_save_context,\n+\t.restore_context = clk_master_pres_restore_context_chg,\n };\n \n static struct clk_hw * __init\n@@ -539,20 +682,21 @@ static int clk_sama7g5_master_set_parent\n \treturn 0;\n }\n \n-static int clk_sama7g5_master_enable(struct clk_hw *hw)\n+static void clk_sama7g5_master_set(struct clk_master *master,\n+\t\t\t\t   unsigned int status)\n {\n-\tstruct clk_master *master = to_clk_master(hw);\n \tunsigned long flags;\n \tunsigned int val, cparent;\n+\tunsigned int enable = status ? PMC_MCR_EN : 0;\n \n \tspin_lock_irqsave(master->lock, flags);\n \n \tregmap_write(master->regmap, PMC_MCR, PMC_MCR_ID(master->id));\n \tregmap_read(master->regmap, PMC_MCR, &val);\n \tregmap_update_bits(master->regmap, PMC_MCR,\n-\t\t\t   PMC_MCR_EN | PMC_MCR_CSS | PMC_MCR_DIV |\n+\t\t\t   enable | PMC_MCR_CSS | PMC_MCR_DIV |\n \t\t\t   PMC_MCR_CMD | PMC_MCR_ID_MSK,\n-\t\t\t   PMC_MCR_EN | (master->parent << PMC_MCR_CSS_SHIFT) |\n+\t\t\t   enable | (master->parent << PMC_MCR_CSS_SHIFT) |\n \t\t\t   (master->div << MASTER_DIV_SHIFT) |\n \t\t\t   PMC_MCR_CMD | PMC_MCR_ID(master->id));\n \n@@ -563,6 +707,13 @@ static int clk_sama7g5_master_enable(str\n \t\tcpu_relax();\n \n \tspin_unlock_irqrestore(master->lock, flags);\n+}\n+\n+static int clk_sama7g5_master_enable(struct clk_hw *hw)\n+{\n+\tstruct clk_master *master = to_clk_master(hw);\n+\n+\tclk_sama7g5_master_set(master, 1);\n \n \treturn 0;\n }\n@@ -620,6 +771,23 @@ static int clk_sama7g5_master_set_rate(s\n \treturn 0;\n }\n \n+static int clk_sama7g5_master_save_context(struct clk_hw *hw)\n+{\n+\tstruct clk_master *master = to_clk_master(hw);\n+\n+\tmaster->pms.status = clk_sama7g5_master_is_enabled(hw);\n+\n+\treturn 0;\n+}\n+\n+static void clk_sama7g5_master_restore_context(struct clk_hw *hw)\n+{\n+\tstruct clk_master *master = to_clk_master(hw);\n+\n+\tif (master->pms.status)\n+\t\tclk_sama7g5_master_set(master, master->pms.status);\n+}\n+\n static const struct clk_ops sama7g5_master_ops = {\n \t.enable = clk_sama7g5_master_enable,\n \t.disable = clk_sama7g5_master_disable,\n@@ -629,6 +797,8 @@ static const struct clk_ops sama7g5_mast\n \t.set_rate = clk_sama7g5_master_set_rate,\n \t.get_parent = clk_sama7g5_master_get_parent,\n \t.set_parent = clk_sama7g5_master_set_parent,\n+\t.save_context = clk_sama7g5_master_save_context,\n+\t.restore_context = clk_sama7g5_master_restore_context,\n };\n \n struct clk_hw * __init\n--- a/drivers/clk/at91/clk-peripheral.c\n+++ b/drivers/clk/at91/clk-peripheral.c\n@@ -37,6 +37,7 @@ struct clk_sam9x5_peripheral {\n \tu32 id;\n \tu32 div;\n \tconst struct clk_pcr_layout *layout;\n+\tstruct at91_clk_pms pms;\n \tbool auto_div;\n \tint chg_pid;\n };\n@@ -155,10 +156,11 @@ static void clk_sam9x5_peripheral_autodi\n \tperiph->div = shift;\n }\n \n-static int clk_sam9x5_peripheral_enable(struct clk_hw *hw)\n+static int clk_sam9x5_peripheral_set(struct clk_sam9x5_peripheral *periph,\n+\t\t\t\t     unsigned int status)\n {\n-\tstruct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw);\n \tunsigned long flags;\n+\tunsigned int enable = status ? AT91_PMC_PCR_EN : 0;\n \n \tif (periph->id < PERIPHERAL_ID_MIN)\n \t\treturn 0;\n@@ -168,15 +170,21 @@ static int clk_sam9x5_peripheral_enable(\n \t\t     (periph->id & periph->layout->pid_mask));\n \tregmap_update_bits(periph->regmap, periph->layout->offset,\n \t\t\t   periph->layout->div_mask | periph->layout->cmd |\n-\t\t\t   AT91_PMC_PCR_EN,\n+\t\t\t   enable,\n \t\t\t   field_prep(periph->layout->div_mask, periph->div) |\n-\t\t\t   periph->layout->cmd |\n-\t\t\t   AT91_PMC_PCR_EN);\n+\t\t\t   periph->layout->cmd | enable);\n \tspin_unlock_irqrestore(periph->lock, flags);\n \n \treturn 0;\n }\n \n+static int clk_sam9x5_peripheral_enable(struct clk_hw *hw)\n+{\n+\tstruct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw);\n+\n+\treturn clk_sam9x5_peripheral_set(periph, 1);\n+}\n+\n static void clk_sam9x5_peripheral_disable(struct clk_hw *hw)\n {\n \tstruct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw);\n@@ -393,6 +401,23 @@ static int clk_sam9x5_peripheral_set_rat\n \treturn -EINVAL;\n }\n \n+static int clk_sam9x5_peripheral_save_context(struct clk_hw *hw)\n+{\n+\tstruct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw);\n+\n+\tperiph->pms.status = clk_sam9x5_peripheral_is_enabled(hw);\n+\n+\treturn 0;\n+}\n+\n+static void clk_sam9x5_peripheral_restore_context(struct clk_hw *hw)\n+{\n+\tstruct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw);\n+\n+\tif (periph->pms.status)\n+\t\tclk_sam9x5_peripheral_set(periph, periph->pms.status);\n+}\n+\n static const struct clk_ops sam9x5_peripheral_ops = {\n \t.enable = clk_sam9x5_peripheral_enable,\n \t.disable = clk_sam9x5_peripheral_disable,\n@@ -400,6 +425,8 @@ static const struct clk_ops sam9x5_perip\n \t.recalc_rate = clk_sam9x5_peripheral_recalc_rate,\n \t.round_rate = clk_sam9x5_peripheral_round_rate,\n \t.set_rate = clk_sam9x5_peripheral_set_rate,\n+\t.save_context = clk_sam9x5_peripheral_save_context,\n+\t.restore_context = clk_sam9x5_peripheral_restore_context,\n };\n \n static const struct clk_ops sam9x5_peripheral_chg_ops = {\n@@ -409,6 +436,8 @@ static const struct clk_ops sam9x5_perip\n \t.recalc_rate = clk_sam9x5_peripheral_recalc_rate,\n \t.determine_rate = clk_sam9x5_peripheral_determine_rate,\n \t.set_rate = clk_sam9x5_peripheral_set_rate,\n+\t.save_context = clk_sam9x5_peripheral_save_context,\n+\t.restore_context = clk_sam9x5_peripheral_restore_context,\n };\n \n struct clk_hw * __init\n@@ -460,7 +489,6 @@ at91_clk_register_sam9x5_peripheral(stru\n \t\thw = ERR_PTR(ret);\n \t} else {\n \t\tclk_sam9x5_peripheral_autodiv(periph);\n-\t\tpmc_register_id(id);\n \t}\n \n \treturn hw;\n--- a/drivers/clk/at91/clk-pll.c\n+++ b/drivers/clk/at91/clk-pll.c\n@@ -40,6 +40,7 @@ struct clk_pll {\n \tu16 mul;\n \tconst struct clk_pll_layout *layout;\n \tconst struct clk_pll_characteristics *characteristics;\n+\tstruct at91_clk_pms pms;\n };\n \n static inline bool clk_pll_ready(struct regmap *regmap, int id)\n@@ -260,6 +261,42 @@ static int clk_pll_set_rate(struct clk_h\n \treturn 0;\n }\n \n+static int clk_pll_save_context(struct clk_hw *hw)\n+{\n+\tstruct clk_pll *pll = to_clk_pll(hw);\n+\tstruct clk_hw *parent_hw = clk_hw_get_parent(hw);\n+\n+\tpll->pms.parent_rate = clk_hw_get_rate(parent_hw);\n+\tpll->pms.rate = clk_pll_recalc_rate(&pll->hw, pll->pms.parent_rate);\n+\tpll->pms.status = clk_pll_ready(pll->regmap, PLL_REG(pll->id));\n+\n+\treturn 0;\n+}\n+\n+static void clk_pll_restore_context(struct clk_hw *hw)\n+{\n+\tstruct clk_pll *pll = to_clk_pll(hw);\n+\tunsigned long calc_rate;\n+\tunsigned int pllr, pllr_out, pllr_count;\n+\tu8 out = 0;\n+\n+\tif (pll->characteristics->out)\n+\t\tout = pll->characteristics->out[pll->range];\n+\n+\tregmap_read(pll->regmap, PLL_REG(pll->id), &pllr);\n+\n+\tcalc_rate = (pll->pms.parent_rate / PLL_DIV(pllr)) *\n+\t\t     (PLL_MUL(pllr, pll->layout) + 1);\n+\tpllr_count = (pllr >> PLL_COUNT_SHIFT) & PLL_MAX_COUNT;\n+\tpllr_out = (pllr >> PLL_OUT_SHIFT) & out;\n+\n+\tif (pll->pms.rate != calc_rate ||\n+\t    pll->pms.status != clk_pll_ready(pll->regmap, PLL_REG(pll->id)) ||\n+\t    pllr_count != PLL_MAX_COUNT ||\n+\t    (out && pllr_out != out))\n+\t\tpr_warn(\"PLLAR was not configured properly by firmware\\n\");\n+}\n+\n static const struct clk_ops pll_ops = {\n \t.prepare = clk_pll_prepare,\n \t.unprepare = clk_pll_unprepare,\n@@ -267,6 +304,8 @@ static const struct clk_ops pll_ops = {\n \t.recalc_rate = clk_pll_recalc_rate,\n \t.round_rate = clk_pll_round_rate,\n \t.set_rate = clk_pll_set_rate,\n+\t.save_context = clk_pll_save_context,\n+\t.restore_context = clk_pll_restore_context,\n };\n \n struct clk_hw * __init\n--- a/drivers/clk/at91/clk-programmable.c\n+++ b/drivers/clk/at91/clk-programmable.c\n@@ -24,6 +24,7 @@ struct clk_programmable {\n \tu32 *mux_table;\n \tu8 id;\n \tconst struct clk_programmable_layout *layout;\n+\tstruct at91_clk_pms pms;\n };\n \n #define to_clk_programmable(hw) container_of(hw, struct clk_programmable, hw)\n@@ -177,12 +178,38 @@ static int clk_programmable_set_rate(str\n \treturn 0;\n }\n \n+static int clk_programmable_save_context(struct clk_hw *hw)\n+{\n+\tstruct clk_programmable *prog = to_clk_programmable(hw);\n+\tstruct clk_hw *parent_hw = clk_hw_get_parent(hw);\n+\n+\tprog->pms.parent = clk_programmable_get_parent(hw);\n+\tprog->pms.parent_rate = clk_hw_get_rate(parent_hw);\n+\tprog->pms.rate = clk_programmable_recalc_rate(hw, prog->pms.parent_rate);\n+\n+\treturn 0;\n+}\n+\n+static void clk_programmable_restore_context(struct clk_hw *hw)\n+{\n+\tstruct clk_programmable *prog = to_clk_programmable(hw);\n+\tint ret;\n+\n+\tret = clk_programmable_set_parent(hw, prog->pms.parent);\n+\tif (ret)\n+\t\treturn;\n+\n+\tclk_programmable_set_rate(hw, prog->pms.rate, prog->pms.parent_rate);\n+}\n+\n static const struct clk_ops programmable_ops = {\n \t.recalc_rate = clk_programmable_recalc_rate,\n \t.determine_rate = clk_programmable_determine_rate,\n \t.get_parent = clk_programmable_get_parent,\n \t.set_parent = clk_programmable_set_parent,\n \t.set_rate = clk_programmable_set_rate,\n+\t.save_context = clk_programmable_save_context,\n+\t.restore_context = clk_programmable_restore_context,\n };\n \n struct clk_hw * __init\n@@ -221,8 +248,6 @@ at91_clk_register_programmable(struct re\n \tif (ret) {\n \t\tkfree(prog);\n \t\thw = ERR_PTR(ret);\n-\t} else {\n-\t\tpmc_register_pck(id);\n \t}\n \n \treturn hw;\n--- a/drivers/clk/at91/clk-sam9x60-pll.c\n+++ b/drivers/clk/at91/clk-sam9x60-pll.c\n@@ -38,12 +38,14 @@ struct sam9x60_pll_core {\n \n struct sam9x60_frac {\n \tstruct sam9x60_pll_core core;\n+\tstruct at91_clk_pms pms;\n \tu32 frac;\n \tu16 mul;\n };\n \n struct sam9x60_div {\n \tstruct sam9x60_pll_core core;\n+\tstruct at91_clk_pms pms;\n \tu8 div;\n };\n \n@@ -75,9 +77,8 @@ static unsigned long sam9x60_frac_pll_re\n \t\tDIV_ROUND_CLOSEST_ULL((u64)parent_rate * frac->frac, (1 << 22));\n }\n \n-static int sam9x60_frac_pll_prepare(struct clk_hw *hw)\n+static int sam9x60_frac_pll_set(struct sam9x60_pll_core *core)\n {\n-\tstruct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);\n \tstruct sam9x60_frac *frac = to_sam9x60_frac(core);\n \tstruct regmap *regmap = core->regmap;\n \tunsigned int val, cfrac, cmul;\n@@ -141,6 +142,13 @@ unlock:\n \treturn 0;\n }\n \n+static int sam9x60_frac_pll_prepare(struct clk_hw *hw)\n+{\n+\tstruct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);\n+\n+\treturn sam9x60_frac_pll_set(core);\n+}\n+\n static void sam9x60_frac_pll_unprepare(struct clk_hw *hw)\n {\n \tstruct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);\n@@ -280,6 +288,25 @@ unlock:\n \treturn ret;\n }\n \n+static int sam9x60_frac_pll_save_context(struct clk_hw *hw)\n+{\n+\tstruct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);\n+\tstruct sam9x60_frac *frac = to_sam9x60_frac(core);\n+\n+\tfrac->pms.status = sam9x60_pll_ready(core->regmap, core->id);\n+\n+\treturn 0;\n+}\n+\n+static void sam9x60_frac_pll_restore_context(struct clk_hw *hw)\n+{\n+\tstruct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);\n+\tstruct sam9x60_frac *frac = to_sam9x60_frac(core);\n+\n+\tif (frac->pms.status)\n+\t\tsam9x60_frac_pll_set(core);\n+}\n+\n static const struct clk_ops sam9x60_frac_pll_ops = {\n \t.prepare = sam9x60_frac_pll_prepare,\n \t.unprepare = sam9x60_frac_pll_unprepare,\n@@ -287,6 +314,8 @@ static const struct clk_ops sam9x60_frac\n \t.recalc_rate = sam9x60_frac_pll_recalc_rate,\n \t.round_rate = sam9x60_frac_pll_round_rate,\n \t.set_rate = sam9x60_frac_pll_set_rate,\n+\t.save_context = sam9x60_frac_pll_save_context,\n+\t.restore_context = sam9x60_frac_pll_restore_context,\n };\n \n static const struct clk_ops sam9x60_frac_pll_ops_chg = {\n@@ -296,11 +325,12 @@ static const struct clk_ops sam9x60_frac\n \t.recalc_rate = sam9x60_frac_pll_recalc_rate,\n \t.round_rate = sam9x60_frac_pll_round_rate,\n \t.set_rate = sam9x60_frac_pll_set_rate_chg,\n+\t.save_context = sam9x60_frac_pll_save_context,\n+\t.restore_context = sam9x60_frac_pll_restore_context,\n };\n \n-static int sam9x60_div_pll_prepare(struct clk_hw *hw)\n+static int sam9x60_div_pll_set(struct sam9x60_pll_core *core)\n {\n-\tstruct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);\n \tstruct sam9x60_div *div = to_sam9x60_div(core);\n \tstruct regmap *regmap = core->regmap;\n \tunsigned long flags;\n@@ -334,6 +364,13 @@ unlock:\n \treturn 0;\n }\n \n+static int sam9x60_div_pll_prepare(struct clk_hw *hw)\n+{\n+\tstruct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);\n+\n+\treturn sam9x60_div_pll_set(core);\n+}\n+\n static void sam9x60_div_pll_unprepare(struct clk_hw *hw)\n {\n \tstruct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);\n@@ -482,6 +519,25 @@ unlock:\n \treturn 0;\n }\n \n+static int sam9x60_div_pll_save_context(struct clk_hw *hw)\n+{\n+\tstruct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);\n+\tstruct sam9x60_div *div = to_sam9x60_div(core);\n+\n+\tdiv->pms.status = sam9x60_div_pll_is_prepared(hw);\n+\n+\treturn 0;\n+}\n+\n+static void sam9x60_div_pll_restore_context(struct clk_hw *hw)\n+{\n+\tstruct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);\n+\tstruct sam9x60_div *div = to_sam9x60_div(core);\n+\n+\tif (div->pms.status)\n+\t\tsam9x60_div_pll_set(core);\n+}\n+\n static const struct clk_ops sam9x60_div_pll_ops = {\n \t.prepare = sam9x60_div_pll_prepare,\n \t.unprepare = sam9x60_div_pll_unprepare,\n@@ -489,6 +545,8 @@ static const struct clk_ops sam9x60_div_\n \t.recalc_rate = sam9x60_div_pll_recalc_rate,\n \t.round_rate = sam9x60_div_pll_round_rate,\n \t.set_rate = sam9x60_div_pll_set_rate,\n+\t.save_context = sam9x60_div_pll_save_context,\n+\t.restore_context = sam9x60_div_pll_restore_context,\n };\n \n static const struct clk_ops sam9x60_div_pll_ops_chg = {\n@@ -498,6 +556,8 @@ static const struct clk_ops sam9x60_div_\n \t.recalc_rate = sam9x60_div_pll_recalc_rate,\n \t.round_rate = sam9x60_div_pll_round_rate,\n \t.set_rate = sam9x60_div_pll_set_rate_chg,\n+\t.save_context = sam9x60_div_pll_save_context,\n+\t.restore_context = sam9x60_div_pll_restore_context,\n };\n \n struct clk_hw * __init\n--- a/drivers/clk/at91/clk-system.c\n+++ b/drivers/clk/at91/clk-system.c\n@@ -20,6 +20,7 @@\n struct clk_system {\n \tstruct clk_hw hw;\n \tstruct regmap *regmap;\n+\tstruct at91_clk_pms pms;\n \tu8 id;\n };\n \n@@ -77,10 +78,29 @@ static int clk_system_is_prepared(struct\n \treturn !!(status & (1 << sys->id));\n }\n \n+static int clk_system_save_context(struct clk_hw *hw)\n+{\n+\tstruct clk_system *sys = to_clk_system(hw);\n+\n+\tsys->pms.status = clk_system_is_prepared(hw);\n+\n+\treturn 0;\n+}\n+\n+static void clk_system_restore_context(struct clk_hw *hw)\n+{\n+\tstruct clk_system *sys = to_clk_system(hw);\n+\n+\tif (sys->pms.status)\n+\t\tclk_system_prepare(&sys->hw);\n+}\n+\n static const struct clk_ops system_ops = {\n \t.prepare = clk_system_prepare,\n \t.unprepare = clk_system_unprepare,\n \t.is_prepared = clk_system_is_prepared,\n+\t.save_context = clk_system_save_context,\n+\t.restore_context = clk_system_restore_context,\n };\n \n struct clk_hw * __init\n--- a/drivers/clk/at91/clk-usb.c\n+++ b/drivers/clk/at91/clk-usb.c\n@@ -24,6 +24,7 @@\n struct at91sam9x5_clk_usb {\n \tstruct clk_hw hw;\n \tstruct regmap *regmap;\n+\tstruct at91_clk_pms pms;\n \tu32 usbs_mask;\n \tu8 num_parents;\n };\n@@ -148,12 +149,38 @@ static int at91sam9x5_clk_usb_set_rate(s\n \treturn 0;\n }\n \n+static int at91sam9x5_usb_save_context(struct clk_hw *hw)\n+{\n+\tstruct at91sam9x5_clk_usb *usb = to_at91sam9x5_clk_usb(hw);\n+\tstruct clk_hw *parent_hw = clk_hw_get_parent(hw);\n+\n+\tusb->pms.parent = at91sam9x5_clk_usb_get_parent(hw);\n+\tusb->pms.parent_rate = clk_hw_get_rate(parent_hw);\n+\tusb->pms.rate = at91sam9x5_clk_usb_recalc_rate(hw, usb->pms.parent_rate);\n+\n+\treturn 0;\n+}\n+\n+static void at91sam9x5_usb_restore_context(struct clk_hw *hw)\n+{\n+\tstruct at91sam9x5_clk_usb *usb = to_at91sam9x5_clk_usb(hw);\n+\tint ret;\n+\n+\tret = at91sam9x5_clk_usb_set_parent(hw, usb->pms.parent);\n+\tif (ret)\n+\t\treturn;\n+\n+\tat91sam9x5_clk_usb_set_rate(hw, usb->pms.rate, usb->pms.parent_rate);\n+}\n+\n static const struct clk_ops at91sam9x5_usb_ops = {\n \t.recalc_rate = at91sam9x5_clk_usb_recalc_rate,\n \t.determine_rate = at91sam9x5_clk_usb_determine_rate,\n \t.get_parent = at91sam9x5_clk_usb_get_parent,\n \t.set_parent = at91sam9x5_clk_usb_set_parent,\n \t.set_rate = at91sam9x5_clk_usb_set_rate,\n+\t.save_context = at91sam9x5_usb_save_context,\n+\t.restore_context = at91sam9x5_usb_restore_context,\n };\n \n static int at91sam9n12_clk_usb_enable(struct clk_hw *hw)\n--- a/drivers/clk/at91/clk-utmi.c\n+++ b/drivers/clk/at91/clk-utmi.c\n@@ -23,6 +23,7 @@ struct clk_utmi {\n \tstruct clk_hw hw;\n \tstruct regmap *regmap_pmc;\n \tstruct regmap *regmap_sfr;\n+\tstruct at91_clk_pms pms;\n };\n \n #define to_clk_utmi(hw) container_of(hw, struct clk_utmi, hw)\n@@ -113,11 +114,30 @@ static unsigned long clk_utmi_recalc_rat\n \treturn UTMI_RATE;\n }\n \n+static int clk_utmi_save_context(struct clk_hw *hw)\n+{\n+\tstruct clk_utmi *utmi = to_clk_utmi(hw);\n+\n+\tutmi->pms.status = clk_utmi_is_prepared(hw);\n+\n+\treturn 0;\n+}\n+\n+static void clk_utmi_restore_context(struct clk_hw *hw)\n+{\n+\tstruct clk_utmi *utmi = to_clk_utmi(hw);\n+\n+\tif (utmi->pms.status)\n+\t\tclk_utmi_prepare(hw);\n+}\n+\n static const struct clk_ops utmi_ops = {\n \t.prepare = clk_utmi_prepare,\n \t.unprepare = clk_utmi_unprepare,\n \t.is_prepared = clk_utmi_is_prepared,\n \t.recalc_rate = clk_utmi_recalc_rate,\n+\t.save_context = clk_utmi_save_context,\n+\t.restore_context = clk_utmi_restore_context,\n };\n \n static struct clk_hw * __init\n@@ -232,10 +252,29 @@ static int clk_utmi_sama7g5_is_prepared(\n \treturn 0;\n }\n \n+static int clk_utmi_sama7g5_save_context(struct clk_hw *hw)\n+{\n+\tstruct clk_utmi *utmi = to_clk_utmi(hw);\n+\n+\tutmi->pms.status = clk_utmi_sama7g5_is_prepared(hw);\n+\n+\treturn 0;\n+}\n+\n+static void clk_utmi_sama7g5_restore_context(struct clk_hw *hw)\n+{\n+\tstruct clk_utmi *utmi = to_clk_utmi(hw);\n+\n+\tif (utmi->pms.status)\n+\t\tclk_utmi_sama7g5_prepare(hw);\n+}\n+\n static const struct clk_ops sama7g5_utmi_ops = {\n \t.prepare = clk_utmi_sama7g5_prepare,\n \t.is_prepared = clk_utmi_sama7g5_is_prepared,\n \t.recalc_rate = clk_utmi_recalc_rate,\n+\t.save_context = clk_utmi_sama7g5_save_context,\n+\t.restore_context = clk_utmi_sama7g5_restore_context,\n };\n \n struct clk_hw * __init\n--- a/drivers/clk/at91/pmc.c\n+++ b/drivers/clk/at91/pmc.c\n@@ -3,6 +3,7 @@\n  *  Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>\n  */\n \n+#include <linux/clk.h>\n #include <linux/clk-provider.h>\n #include <linux/clkdev.h>\n #include <linux/clk/at91_pmc.h>\n@@ -14,8 +15,6 @@\n \n #include <asm/proc-fns.h>\n \n-#include <dt-bindings/clock/at91.h>\n-\n #include \"pmc.h\"\n \n #define PMC_MAX_IDS 128\n@@ -111,147 +110,19 @@ struct pmc_data *pmc_data_allocate(unsig\n }\n \n #ifdef CONFIG_PM\n-static struct regmap *pmcreg;\n-\n-static u8 registered_ids[PMC_MAX_IDS];\n-static u8 registered_pcks[PMC_MAX_PCKS];\n-\n-static struct\n-{\n-\tu32 scsr;\n-\tu32 pcsr0;\n-\tu32 uckr;\n-\tu32 mor;\n-\tu32 mcfr;\n-\tu32 pllar;\n-\tu32 mckr;\n-\tu32 usb;\n-\tu32 imr;\n-\tu32 pcsr1;\n-\tu32 pcr[PMC_MAX_IDS];\n-\tu32 audio_pll0;\n-\tu32 audio_pll1;\n-\tu32 pckr[PMC_MAX_PCKS];\n-} pmc_cache;\n-\n-/*\n- * As Peripheral ID 0 is invalid on AT91 chips, the identifier is stored\n- * without alteration in the table, and 0 is for unused clocks.\n- */\n-void pmc_register_id(u8 id)\n+static int at91_pmc_suspend(void)\n {\n-\tint i;\n-\n-\tfor (i = 0; i < PMC_MAX_IDS; i++) {\n-\t\tif (registered_ids[i] == 0) {\n-\t\t\tregistered_ids[i] = id;\n-\t\t\tbreak;\n-\t\t}\n-\t\tif (registered_ids[i] == id)\n-\t\t\tbreak;\n-\t}\n+\treturn clk_save_context();\n }\n \n-/*\n- * As Programmable Clock 0 is valid on AT91 chips, there is an offset\n- * of 1 between the stored value and the real clock ID.\n- */\n-void pmc_register_pck(u8 pck)\n+static void at91_pmc_resume(void)\n {\n-\tint i;\n-\n-\tfor (i = 0; i < PMC_MAX_PCKS; i++) {\n-\t\tif (registered_pcks[i] == 0) {\n-\t\t\tregistered_pcks[i] = pck + 1;\n-\t\t\tbreak;\n-\t\t}\n-\t\tif (registered_pcks[i] == (pck + 1))\n-\t\t\tbreak;\n-\t}\n-}\n-\n-static int pmc_suspend(void)\n-{\n-\tint i;\n-\tu8 num;\n-\n-\tregmap_read(pmcreg, AT91_PMC_SCSR, &pmc_cache.scsr);\n-\tregmap_read(pmcreg, AT91_PMC_PCSR, &pmc_cache.pcsr0);\n-\tregmap_read(pmcreg, AT91_CKGR_UCKR, &pmc_cache.uckr);\n-\tregmap_read(pmcreg, AT91_CKGR_MOR, &pmc_cache.mor);\n-\tregmap_read(pmcreg, AT91_CKGR_MCFR, &pmc_cache.mcfr);\n-\tregmap_read(pmcreg, AT91_CKGR_PLLAR, &pmc_cache.pllar);\n-\tregmap_read(pmcreg, AT91_PMC_MCKR, &pmc_cache.mckr);\n-\tregmap_read(pmcreg, AT91_PMC_USB, &pmc_cache.usb);\n-\tregmap_read(pmcreg, AT91_PMC_IMR, &pmc_cache.imr);\n-\tregmap_read(pmcreg, AT91_PMC_PCSR1, &pmc_cache.pcsr1);\n-\n-\tfor (i = 0; registered_ids[i]; i++) {\n-\t\tregmap_write(pmcreg, AT91_PMC_PCR,\n-\t\t\t     (registered_ids[i] & AT91_PMC_PCR_PID_MASK));\n-\t\tregmap_read(pmcreg, AT91_PMC_PCR,\n-\t\t\t    &pmc_cache.pcr[registered_ids[i]]);\n-\t}\n-\tfor (i = 0; registered_pcks[i]; i++) {\n-\t\tnum = registered_pcks[i] - 1;\n-\t\tregmap_read(pmcreg, AT91_PMC_PCKR(num), &pmc_cache.pckr[num]);\n-\t}\n-\n-\treturn 0;\n-}\n-\n-static bool pmc_ready(unsigned int mask)\n-{\n-\tunsigned int status;\n-\n-\tregmap_read(pmcreg, AT91_PMC_SR, &status);\n-\n-\treturn ((status & mask) == mask) ? 1 : 0;\n-}\n-\n-static void pmc_resume(void)\n-{\n-\tint i;\n-\tu8 num;\n-\tu32 tmp;\n-\tu32 mask = AT91_PMC_MCKRDY | AT91_PMC_LOCKA;\n-\n-\tregmap_read(pmcreg, AT91_PMC_MCKR, &tmp);\n-\tif (pmc_cache.mckr != tmp)\n-\t\tpr_warn(\"MCKR was not configured properly by the firmware\\n\");\n-\tregmap_read(pmcreg, AT91_CKGR_PLLAR, &tmp);\n-\tif (pmc_cache.pllar != tmp)\n-\t\tpr_warn(\"PLLAR was not configured properly by the firmware\\n\");\n-\n-\tregmap_write(pmcreg, AT91_PMC_SCER, pmc_cache.scsr);\n-\tregmap_write(pmcreg, AT91_PMC_PCER, pmc_cache.pcsr0);\n-\tregmap_write(pmcreg, AT91_CKGR_UCKR, pmc_cache.uckr);\n-\tregmap_write(pmcreg, AT91_CKGR_MOR, pmc_cache.mor);\n-\tregmap_write(pmcreg, AT91_CKGR_MCFR, pmc_cache.mcfr);\n-\tregmap_write(pmcreg, AT91_PMC_USB, pmc_cache.usb);\n-\tregmap_write(pmcreg, AT91_PMC_IMR, pmc_cache.imr);\n-\tregmap_write(pmcreg, AT91_PMC_PCER1, pmc_cache.pcsr1);\n-\n-\tfor (i = 0; registered_ids[i]; i++) {\n-\t\tregmap_write(pmcreg, AT91_PMC_PCR,\n-\t\t\t     pmc_cache.pcr[registered_ids[i]] |\n-\t\t\t     AT91_PMC_PCR_CMD);\n-\t}\n-\tfor (i = 0; registered_pcks[i]; i++) {\n-\t\tnum = registered_pcks[i] - 1;\n-\t\tregmap_write(pmcreg, AT91_PMC_PCKR(num), pmc_cache.pckr[num]);\n-\t}\n-\n-\tif (pmc_cache.uckr & AT91_PMC_UPLLEN)\n-\t\tmask |= AT91_PMC_LOCKU;\n-\n-\twhile (!pmc_ready(mask))\n-\t\tcpu_relax();\n+\tclk_restore_context();\n }\n \n static struct syscore_ops pmc_syscore_ops = {\n-\t.suspend = pmc_suspend,\n-\t.resume = pmc_resume,\n+\t.suspend = at91_pmc_suspend,\n+\t.resume = at91_pmc_resume,\n };\n \n static const struct of_device_id sama5d2_pmc_dt_ids[] = {\n@@ -271,11 +142,7 @@ static int __init pmc_register_ops(void)\n \t\tof_node_put(np);\n \t\treturn -ENODEV;\n \t}\n-\n-\tpmcreg = device_node_to_regmap(np);\n \tof_node_put(np);\n-\tif (IS_ERR(pmcreg))\n-\t\treturn PTR_ERR(pmcreg);\n \n \tregister_syscore_ops(&pmc_syscore_ops);\n \n--- a/drivers/clk/at91/pmc.h\n+++ b/drivers/clk/at91/pmc.h\n@@ -13,6 +13,8 @@\n #include <linux/regmap.h>\n #include <linux/spinlock.h>\n \n+#include <dt-bindings/clock/at91.h>\n+\n extern spinlock_t pmc_pcr_lock;\n \n struct pmc_data {\n@@ -98,6 +100,20 @@ struct clk_pcr_layout {\n \tu32 pid_mask;\n };\n \n+/**\n+ * struct at91_clk_pms - Power management state for AT91 clock\n+ * @rate: clock rate\n+ * @parent_rate: clock parent rate\n+ * @status: clock status (enabled or disabled)\n+ * @parent: clock parent index\n+ */\n+struct at91_clk_pms {\n+\tunsigned long rate;\n+\tunsigned long parent_rate;\n+\tunsigned int status;\n+\tunsigned int parent;\n+};\n+\n #define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1))\n #define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask))\n \n@@ -248,12 +264,4 @@ struct clk_hw * __init\n at91_clk_sama7g5_register_utmi(struct regmap *regmap, const char *name,\n \t\t\t       const char *parent_name);\n \n-#ifdef CONFIG_PM\n-void pmc_register_id(u8 id);\n-void pmc_register_pck(u8 pck);\n-#else\n-static inline void pmc_register_id(u8 id) {}\n-static inline void pmc_register_pck(u8 pck) {}\n-#endif\n-\n #endif /* __PMC_H_ */\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/235-clk-at91-pmc-execute-suspend-resume-only-for-backup-.patch",
    "content": "From 63a0c32028148e91ea91cfbf95841c4ecd69d21b Mon Sep 17 00:00:00 2001\nFrom: Claudiu Beznea <claudiu.beznea@microchip.com>\nDate: Mon, 11 Oct 2021 14:27:06 +0300\nSubject: [PATCH 235/247] clk: at91: pmc: execute suspend/resume only for\n backup mode\n\nBefore going to backup mode architecture specific PM code sets the first\nword in securam (file arch/arm/mach-at91/pm.c, function at91_pm_begin()).\nThus take this into account when suspending/resuming clocks. This will\navoid executing unnecessary instructions when suspending to non backup\nmodes.\n\nSigned-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>\nLink: https://lore.kernel.org/r/20211011112719.3951784-3-claudiu.beznea@microchip.com\nAcked-by: Nicolas Ferre <nicolas.ferre@microchip.com>\nSigned-off-by: Stephen Boyd <sboyd@kernel.org>\n---\n drivers/clk/at91/pmc.c | 39 +++++++++++++++++++++++++++++++++++++++\n 1 file changed, 39 insertions(+)\n\n--- a/drivers/clk/at91/pmc.c\n+++ b/drivers/clk/at91/pmc.c\n@@ -8,6 +8,7 @@\n #include <linux/clkdev.h>\n #include <linux/clk/at91_pmc.h>\n #include <linux/of.h>\n+#include <linux/of_address.h>\n #include <linux/mfd/syscon.h>\n #include <linux/platform_device.h>\n #include <linux/regmap.h>\n@@ -110,13 +111,35 @@ struct pmc_data *pmc_data_allocate(unsig\n }\n \n #ifdef CONFIG_PM\n+\n+/* Address in SECURAM that say if we suspend to backup mode. */\n+static void __iomem *at91_pmc_backup_suspend;\n+\n static int at91_pmc_suspend(void)\n {\n+\tunsigned int backup;\n+\n+\tif (!at91_pmc_backup_suspend)\n+\t\treturn 0;\n+\n+\tbackup = readl_relaxed(at91_pmc_backup_suspend);\n+\tif (!backup)\n+\t\treturn 0;\n+\n \treturn clk_save_context();\n }\n \n static void at91_pmc_resume(void)\n {\n+\tunsigned int backup;\n+\n+\tif (!at91_pmc_backup_suspend)\n+\t\treturn;\n+\n+\tbackup = readl_relaxed(at91_pmc_backup_suspend);\n+\tif (!backup)\n+\t\treturn;\n+\n \tclk_restore_context();\n }\n \n@@ -144,6 +167,22 @@ static int __init pmc_register_ops(void)\n \t}\n \tof_node_put(np);\n \n+\tnp = of_find_compatible_node(NULL, NULL, \"atmel,sama5d2-securam\");\n+\tif (!np)\n+\t\treturn -ENODEV;\n+\n+\tif (!of_device_is_available(np)) {\n+\t\tof_node_put(np);\n+\t\treturn -ENODEV;\n+\t}\n+\tof_node_put(np);\n+\n+\tat91_pmc_backup_suspend = of_iomap(np, 0);\n+\tif (!at91_pmc_backup_suspend) {\n+\t\tpr_warn(\"%s(): unable to map securam\\n\", __func__);\n+\t\treturn -ENOMEM;\n+\t}\n+\n \tregister_syscore_ops(&pmc_syscore_ops);\n \n \treturn 0;\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/236-clk-at91-sama7g5-add-securam-s-peripheral-clock.patch",
    "content": "From 50edd53c26177e95995533b7d649801086a52f6c Mon Sep 17 00:00:00 2001\nFrom: Claudiu Beznea <claudiu.beznea@microchip.com>\nDate: Mon, 11 Oct 2021 14:27:07 +0300\nSubject: [PATCH 236/247] clk: at91: sama7g5: add securam's peripheral clock\n\nAdd SECURAM's peripheral clock.\n\nSigned-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>\nAcked-by: Nicolas Ferre <nicolas.ferre@microchip.com>\nLink: https://lore.kernel.org/r/20211011112719.3951784-4-claudiu.beznea@microchip.com\nSigned-off-by: Stephen Boyd <sboyd@kernel.org>\n---\n drivers/clk/at91/sama7g5.c | 1 +\n 1 file changed, 1 insertion(+)\n\n--- a/drivers/clk/at91/sama7g5.c\n+++ b/drivers/clk/at91/sama7g5.c\n@@ -377,6 +377,7 @@ static const struct {\n \tu8 id;\n } sama7g5_periphck[] = {\n \t{ .n = \"pioA_clk\",\t.p = \"mck0\", .id = 11, },\n+\t{ .n = \"securam_clk\",\t.p = \"mck0\", .id = 18, },\n \t{ .n = \"sfr_clk\",\t.p = \"mck1\", .id = 19, },\n \t{ .n = \"hsmc_clk\",\t.p = \"mck1\", .id = 21, },\n \t{ .n = \"xdmac0_clk\",\t.p = \"mck1\", .id = 22, },\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/237-clk-at91-clk-master-add-register-definition-for-sama.patch",
    "content": "From c716562753d1e51a1c53647aa77a332f97187d15 Mon Sep 17 00:00:00 2001\nFrom: Claudiu Beznea <claudiu.beznea@microchip.com>\nDate: Mon, 11 Oct 2021 14:27:08 +0300\nSubject: [PATCH 237/247] clk: at91: clk-master: add register definition for\n sama7g5's master clock\n\nSAMA7G5 has 4 master clocks (MCK1..4) which are controlled though the\nregister at offset 0x30 (relative to PMC). In the last/first phase of\nsuspend/resume procedure (which is architecture specific) the parent\nof master clocks are changed (via assembly code) for more power saving\n(see file arch/arm/mach-at91/pm_suspend.S, macros at91_mckx_ps_enable\nand at91_mckx_ps_restore). Thus the macros corresponding to register\nat offset 0x30 need to be shared b/w clk-master.c and pm_suspend.S.\ncommit ec03f18cc222 (\"clk: at91: add register definition for sama7g5's\nmaster clock\") introduced the proper macros but didn't adapted the\nclk-master.c as well. Thus, this commit adapt the clk-master.c to use\nthe macros introduced in commit ec03f18cc222 (\"clk: at91: add register\ndefinition for sama7g5's master clock\").\n\nSigned-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>\nLink: https://lore.kernel.org/r/20211011112719.3951784-5-claudiu.beznea@microchip.com\nAcked-by: Nicolas Ferre <nicolas.ferre@microchip.com>\nSigned-off-by: Stephen Boyd <sboyd@kernel.org>\n---\n drivers/clk/at91/clk-master.c | 50 ++++++++++++++++-------------------\n 1 file changed, 23 insertions(+), 27 deletions(-)\n\n--- a/drivers/clk/at91/clk-master.c\n+++ b/drivers/clk/at91/clk-master.c\n@@ -17,15 +17,7 @@\n #define MASTER_DIV_SHIFT\t8\n #define MASTER_DIV_MASK\t\t0x7\n \n-#define PMC_MCR\t\t\t0x30\n-#define PMC_MCR_ID_MSK\t\tGENMASK(3, 0)\n-#define PMC_MCR_CMD\t\tBIT(7)\n-#define PMC_MCR_DIV\t\tGENMASK(10, 8)\n-#define PMC_MCR_CSS\t\tGENMASK(20, 16)\n #define PMC_MCR_CSS_SHIFT\t(16)\n-#define PMC_MCR_EN\t\tBIT(28)\n-\n-#define PMC_MCR_ID(x)\t\t((x) & PMC_MCR_ID_MSK)\n \n #define MASTER_MAX_ID\t\t4\n \n@@ -687,20 +679,22 @@ static void clk_sama7g5_master_set(struc\n {\n \tunsigned long flags;\n \tunsigned int val, cparent;\n-\tunsigned int enable = status ? PMC_MCR_EN : 0;\n+\tunsigned int enable = status ? AT91_PMC_MCR_V2_EN : 0;\n \n \tspin_lock_irqsave(master->lock, flags);\n \n-\tregmap_write(master->regmap, PMC_MCR, PMC_MCR_ID(master->id));\n-\tregmap_read(master->regmap, PMC_MCR, &val);\n-\tregmap_update_bits(master->regmap, PMC_MCR,\n-\t\t\t   enable | PMC_MCR_CSS | PMC_MCR_DIV |\n-\t\t\t   PMC_MCR_CMD | PMC_MCR_ID_MSK,\n+\tregmap_write(master->regmap, AT91_PMC_MCR_V2,\n+\t\t     AT91_PMC_MCR_V2_ID(master->id));\n+\tregmap_read(master->regmap, AT91_PMC_MCR_V2, &val);\n+\tregmap_update_bits(master->regmap, AT91_PMC_MCR_V2,\n+\t\t\t   enable | AT91_PMC_MCR_V2_CSS | AT91_PMC_MCR_V2_DIV |\n+\t\t\t   AT91_PMC_MCR_V2_CMD | AT91_PMC_MCR_V2_ID_MSK,\n \t\t\t   enable | (master->parent << PMC_MCR_CSS_SHIFT) |\n \t\t\t   (master->div << MASTER_DIV_SHIFT) |\n-\t\t\t   PMC_MCR_CMD | PMC_MCR_ID(master->id));\n+\t\t\t   AT91_PMC_MCR_V2_CMD |\n+\t\t\t   AT91_PMC_MCR_V2_ID(master->id));\n \n-\tcparent = (val & PMC_MCR_CSS) >> PMC_MCR_CSS_SHIFT;\n+\tcparent = (val & AT91_PMC_MCR_V2_CSS) >> PMC_MCR_CSS_SHIFT;\n \n \t/* Wait here only if parent is being changed. */\n \twhile ((cparent != master->parent) && !clk_master_ready(master))\n@@ -725,10 +719,12 @@ static void clk_sama7g5_master_disable(s\n \n \tspin_lock_irqsave(master->lock, flags);\n \n-\tregmap_write(master->regmap, PMC_MCR, master->id);\n-\tregmap_update_bits(master->regmap, PMC_MCR,\n-\t\t\t   PMC_MCR_EN | PMC_MCR_CMD | PMC_MCR_ID_MSK,\n-\t\t\t   PMC_MCR_CMD | PMC_MCR_ID(master->id));\n+\tregmap_write(master->regmap, AT91_PMC_MCR_V2, master->id);\n+\tregmap_update_bits(master->regmap, AT91_PMC_MCR_V2,\n+\t\t\t   AT91_PMC_MCR_V2_EN | AT91_PMC_MCR_V2_CMD |\n+\t\t\t   AT91_PMC_MCR_V2_ID_MSK,\n+\t\t\t   AT91_PMC_MCR_V2_CMD |\n+\t\t\t   AT91_PMC_MCR_V2_ID(master->id));\n \n \tspin_unlock_irqrestore(master->lock, flags);\n }\n@@ -741,12 +737,12 @@ static int clk_sama7g5_master_is_enabled\n \n \tspin_lock_irqsave(master->lock, flags);\n \n-\tregmap_write(master->regmap, PMC_MCR, master->id);\n-\tregmap_read(master->regmap, PMC_MCR, &val);\n+\tregmap_write(master->regmap, AT91_PMC_MCR_V2, master->id);\n+\tregmap_read(master->regmap, AT91_PMC_MCR_V2, &val);\n \n \tspin_unlock_irqrestore(master->lock, flags);\n \n-\treturn !!(val & PMC_MCR_EN);\n+\treturn !!(val & AT91_PMC_MCR_V2_EN);\n }\n \n static int clk_sama7g5_master_set_rate(struct clk_hw *hw, unsigned long rate,\n@@ -842,10 +838,10 @@ at91_clk_sama7g5_register_master(struct\n \tmaster->mux_table = mux_table;\n \n \tspin_lock_irqsave(master->lock, flags);\n-\tregmap_write(master->regmap, PMC_MCR, master->id);\n-\tregmap_read(master->regmap, PMC_MCR, &val);\n-\tmaster->parent = (val & PMC_MCR_CSS) >> PMC_MCR_CSS_SHIFT;\n-\tmaster->div = (val & PMC_MCR_DIV) >> MASTER_DIV_SHIFT;\n+\tregmap_write(master->regmap, AT91_PMC_MCR_V2, master->id);\n+\tregmap_read(master->regmap, AT91_PMC_MCR_V2, &val);\n+\tmaster->parent = (val & AT91_PMC_MCR_V2_CSS) >> PMC_MCR_CSS_SHIFT;\n+\tmaster->div = (val & AT91_PMC_MCR_V2_DIV) >> MASTER_DIV_SHIFT;\n \tspin_unlock_irqrestore(master->lock, flags);\n \n \thw = &master->hw;\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/238-clk-at91-clk-master-improve-readability-by-using-loc.patch",
    "content": "From 17b53ad1574cb5f41789993289d3d94f7a50f0ce Mon Sep 17 00:00:00 2001\nFrom: Claudiu Beznea <claudiu.beznea@microchip.com>\nDate: Mon, 11 Oct 2021 14:27:09 +0300\nSubject: [PATCH 238/247] clk: at91: clk-master: improve readability by using\n local variables\n\nImprove readability in clk_sama7g5_master_set() by using local\nvariables.\n\nSuggested-by: Nicolas Ferre <nicolas.ferre@microchip.com>\nSigned-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>\nLink: https://lore.kernel.org/r/20211011112719.3951784-6-claudiu.beznea@microchip.com\nAcked-by: Nicolas Ferre <nicolas.ferre@microchip.com>\nSigned-off-by: Stephen Boyd <sboyd@kernel.org>\n---\n drivers/clk/at91/clk-master.c | 6 +++---\n 1 file changed, 3 insertions(+), 3 deletions(-)\n\n--- a/drivers/clk/at91/clk-master.c\n+++ b/drivers/clk/at91/clk-master.c\n@@ -680,6 +680,8 @@ static void clk_sama7g5_master_set(struc\n \tunsigned long flags;\n \tunsigned int val, cparent;\n \tunsigned int enable = status ? AT91_PMC_MCR_V2_EN : 0;\n+\tunsigned int parent = master->parent << PMC_MCR_CSS_SHIFT;\n+\tunsigned int div = master->div << MASTER_DIV_SHIFT;\n \n \tspin_lock_irqsave(master->lock, flags);\n \n@@ -689,9 +691,7 @@ static void clk_sama7g5_master_set(struc\n \tregmap_update_bits(master->regmap, AT91_PMC_MCR_V2,\n \t\t\t   enable | AT91_PMC_MCR_V2_CSS | AT91_PMC_MCR_V2_DIV |\n \t\t\t   AT91_PMC_MCR_V2_CMD | AT91_PMC_MCR_V2_ID_MSK,\n-\t\t\t   enable | (master->parent << PMC_MCR_CSS_SHIFT) |\n-\t\t\t   (master->div << MASTER_DIV_SHIFT) |\n-\t\t\t   AT91_PMC_MCR_V2_CMD |\n+\t\t\t   enable | parent | div | AT91_PMC_MCR_V2_CMD |\n \t\t\t   AT91_PMC_MCR_V2_ID(master->id));\n \n \tcparent = (val & AT91_PMC_MCR_V2_CSS) >> PMC_MCR_CSS_SHIFT;\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/239-clk-at91-pmc-add-sama7g5-to-the-list-of-available-pm.patch",
    "content": "From 8a38e0dda46c9d941a61d8b2e6c14704531b7871 Mon Sep 17 00:00:00 2001\nFrom: Claudiu Beznea <claudiu.beznea@microchip.com>\nDate: Mon, 11 Oct 2021 14:27:10 +0300\nSubject: [PATCH 239/247] clk: at91: pmc: add sama7g5 to the list of available\n pmcs\n\nAdd SAMA7G5 to the list of available PMCs such that the suspend/resume\ncode for clocks to be used on backup mode.\n\nSigned-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>\nLink: https://lore.kernel.org/r/20211011112719.3951784-7-claudiu.beznea@microchip.com\nAcked-by: Nicolas Ferre <nicolas.ferre@microchip.com>\nSigned-off-by: Stephen Boyd <sboyd@kernel.org>\n---\n drivers/clk/at91/pmc.c | 5 +++--\n 1 file changed, 3 insertions(+), 2 deletions(-)\n\n--- a/drivers/clk/at91/pmc.c\n+++ b/drivers/clk/at91/pmc.c\n@@ -148,8 +148,9 @@ static struct syscore_ops pmc_syscore_op\n \t.resume = at91_pmc_resume,\n };\n \n-static const struct of_device_id sama5d2_pmc_dt_ids[] = {\n+static const struct of_device_id pmc_dt_ids[] = {\n \t{ .compatible = \"atmel,sama5d2-pmc\" },\n+\t{ .compatible = \"microchip,sama7g5-pmc\", },\n \t{ /* sentinel */ }\n };\n \n@@ -157,7 +158,7 @@ static int __init pmc_register_ops(void)\n {\n \tstruct device_node *np;\n \n-\tnp = of_find_matching_node(NULL, sama5d2_pmc_dt_ids);\n+\tnp = of_find_matching_node(NULL, pmc_dt_ids);\n \tif (!np)\n \t\treturn -ENODEV;\n \n"
  },
  {
    "path": "target/linux/at91/patches-5.10/240-clk-at91-clk-master-check-if-div-or-pres-is-zero.patch",
    "content": "From bb8e6ca274763fa98613dbe8b0833348a1d8fe4d Mon Sep 17 00:00:00 2001\nFrom: Claudiu Beznea <claudiu.beznea@microchip.com>\nDate: Mon, 11 Oct 2021 14:27:12 +0300\nSubject: [PATCH 240/247] clk: at91: clk-master: check if div or pres is zero\n\nCheck if div or pres is zero before using it as argument for ffs().\nIn case div is zero ffs() will return 0 and thus substracting from\nzero will lead to invalid values to be setup in registers.\n\nFixes: 7a110b9107ed8 (\"clk: at91: clk-master: re-factor master clock\")\nFixes: 75c88143f3b87 (\"clk: at91: clk-master: add master clock support for SAMA7G5\")\nSigned-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>\nLink: https://lore.kernel.org/r/20211011112719.3951784-9-claudiu.beznea@microchip.com\nAcked-by: Nicolas Ferre <nicolas.ferre@microchip.com>\nSigned-off-by: Stephen Boyd <sboyd@kernel.org>\n---\n drivers/clk/at91/clk-master.c | 4 ++--\n 1 file changed, 2 insertions(+), 2 deletions(-)\n\n--- a/drivers/clk/at91/clk-master.c\n+++ b/drivers/clk/at91/clk-master.c\n@@ -344,7 +344,7 @@ static int clk_master_pres_set_rate(stru\n \n \telse if (pres == 3)\n \t\tpres = MASTER_PRES_MAX;\n-\telse\n+\telse if (pres)\n \t\tpres = ffs(pres) - 1;\n \n \tspin_lock_irqsave(master->lock, flags);\n@@ -757,7 +757,7 @@ static int clk_sama7g5_master_set_rate(s\n \n \tif (div == 3)\n \t\tdiv = MASTER_PRES_MAX;\n-\telse\n+\telse if (div)\n \t\tdiv = ffs(div) - 1;\n \n \tspin_lock_irqsave(master->lock, flags);\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/241-clk-at91-clk-master-mask-mckr-against-layout-mask.patch",
    "content": "From 27c11c09346b7b9f67eeb39db1b943f4a9742ff3 Mon Sep 17 00:00:00 2001\nFrom: Claudiu Beznea <claudiu.beznea@microchip.com>\nDate: Mon, 11 Oct 2021 14:27:13 +0300\nSubject: [PATCH 241/247] clk: at91: clk-master: mask mckr against layout->mask\n\nMask values read/written from/to MCKR against layout->mask as this\nmask may be different b/w PMC versions.\n\nSigned-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>\nLink: https://lore.kernel.org/r/20211011112719.3951784-10-claudiu.beznea@microchip.com\nAcked-by: Nicolas Ferre <nicolas.ferre@microchip.com>\nSigned-off-by: Stephen Boyd <sboyd@kernel.org>\n---\n drivers/clk/at91/clk-master.c | 7 +++++--\n 1 file changed, 5 insertions(+), 2 deletions(-)\n\n--- a/drivers/clk/at91/clk-master.c\n+++ b/drivers/clk/at91/clk-master.c\n@@ -186,8 +186,8 @@ static int clk_master_div_set_rate(struc\n \tif (ret)\n \t\tgoto unlock;\n \n-\ttmp = mckr & master->layout->mask;\n-\ttmp = (tmp >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK;\n+\tmckr &= master->layout->mask;\n+\ttmp = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK;\n \tif (tmp == div)\n \t\tgoto unlock;\n \n@@ -384,6 +384,7 @@ static unsigned long clk_master_pres_rec\n \tregmap_read(master->regmap, master->layout->offset, &val);\n \tspin_unlock_irqrestore(master->lock, flags);\n \n+\tval &= master->layout->mask;\n \tpres = (val >> master->layout->pres_shift) & MASTER_PRES_MASK;\n \tif (pres == 3 && characteristics->have_div3_pres)\n \t\tpres = 3;\n@@ -403,6 +404,8 @@ static u8 clk_master_pres_get_parent(str\n \tregmap_read(master->regmap, master->layout->offset, &mckr);\n \tspin_unlock_irqrestore(master->lock, flags);\n \n+\tmckr &= master->layout->mask;\n+\n \treturn mckr & AT91_PMC_CSS;\n }\n \n"
  },
  {
    "path": "target/linux/at91/patches-5.10/242-clk-at91-clk-master-fix-prescaler-logic.patch",
    "content": "From 4375cd63b55860f5e82618dc5f50846b3129842a Mon Sep 17 00:00:00 2001\nFrom: Claudiu Beznea <claudiu.beznea@microchip.com>\nDate: Mon, 11 Oct 2021 14:27:14 +0300\nSubject: [PATCH 242/247] clk: at91: clk-master: fix prescaler logic\n\nWhen prescaler value read from register is MASTER_PRES_MAX it means\nthat the input clock will be divided by 3. Fix the code to reflect\nthis.\n\nFixes: 7a110b9107ed8 (\"clk: at91: clk-master: re-factor master clock\")\nSigned-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>\nLink: https://lore.kernel.org/r/20211011112719.3951784-11-claudiu.beznea@microchip.com\nAcked-by: Nicolas Ferre <nicolas.ferre@microchip.com>\nSigned-off-by: Stephen Boyd <sboyd@kernel.org>\n---\n drivers/clk/at91/clk-master.c | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/drivers/clk/at91/clk-master.c\n+++ b/drivers/clk/at91/clk-master.c\n@@ -386,7 +386,7 @@ static unsigned long clk_master_pres_rec\n \n \tval &= master->layout->mask;\n \tpres = (val >> master->layout->pres_shift) & MASTER_PRES_MASK;\n-\tif (pres == 3 && characteristics->have_div3_pres)\n+\tif (pres == MASTER_PRES_MAX && characteristics->have_div3_pres)\n \t\tpres = 3;\n \telse\n \t\tpres = (1 << pres);\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/243-clk-at91-clk-sam9x60-pll-add-notifier-for-div-part-o.patch",
    "content": "From e76d2af5009f52aa02d3db7ae32d150ad66398f9 Mon Sep 17 00:00:00 2001\nFrom: Claudiu Beznea <claudiu.beznea@microchip.com>\nDate: Mon, 11 Oct 2021 14:27:15 +0300\nSubject: [PATCH 243/247] clk: at91: clk-sam9x60-pll: add notifier for div part\n of PLL\n\nSAM9X60's PLL which is also part of SAMA7G5 is composed of 2 parts:\none fractional part and one divider. On SAMA7G5 the CPU PLL could be\nchanged at run-time to implement DVFS. The hardware clock tree on\nSAMA7G5 for CPU PLL is as follows:\n\n                       +---- div1 ----------------> cpuck\n                       |\nFRAC PLL ---> DIV PLL -+-> prescaler ---> div0 ---> mck0\n\nThe div1 block is not implemented in Linux; on prescaler block it has\nbeen discovered a bug on some scenarios and will be removed from Linux\nin next commits. Thus, the final clock tree that will be used in Linux\nwill be as follows:\n\n                       +-----------> cpuck\n                       |\nFRAC PLL ---> DIV PLL -+-> div0 ---> mck0\n\nIt has been proposed in [1] to not introduce a new CPUFreq driver but\nto overload the proper clock drivers with proper operation such that\ncpufreq-dt to be used. To accomplish this DIV PLL and div0 implement\nclock notifiers which applies safe dividers before FRAC PLL is changed.\nThe current commit treats only the DIV PLL by adding a notifier that\nsets a safe divider on PRE_RATE_CHANGE events. The safe divider is\nprovided by initialization clock code (sama7g5.c). The div0 is treated\nin next commits (to keep the changes as clean as possible).\n\n[1] https://lore.kernel.org/lkml/20210105104426.4tmgc2l3vyicwedd@vireshk-i7/\n\nSigned-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>\nLink: https://lore.kernel.org/r/20211011112719.3951784-12-claudiu.beznea@microchip.com\nAcked-by: Nicolas Ferre <nicolas.ferre@microchip.com>\nSigned-off-by: Stephen Boyd <sboyd@kernel.org>\n---\n drivers/clk/at91/clk-sam9x60-pll.c | 102 ++++++++++++++++++++++-------\n drivers/clk/at91/pmc.h             |   3 +-\n drivers/clk/at91/sam9x60.c         |   6 +-\n drivers/clk/at91/sama7g5.c         |  13 +++-\n 4 files changed, 95 insertions(+), 29 deletions(-)\n\n--- a/drivers/clk/at91/clk-sam9x60-pll.c\n+++ b/drivers/clk/at91/clk-sam9x60-pll.c\n@@ -5,6 +5,7 @@\n  */\n \n #include <linux/bitfield.h>\n+#include <linux/clk.h>\n #include <linux/clk-provider.h>\n #include <linux/clkdev.h>\n #include <linux/clk/at91_pmc.h>\n@@ -47,12 +48,15 @@ struct sam9x60_div {\n \tstruct sam9x60_pll_core core;\n \tstruct at91_clk_pms pms;\n \tu8 div;\n+\tu8 safe_div;\n };\n \n #define to_sam9x60_pll_core(hw)\tcontainer_of(hw, struct sam9x60_pll_core, hw)\n #define to_sam9x60_frac(core)\tcontainer_of(core, struct sam9x60_frac, core)\n #define to_sam9x60_div(core)\tcontainer_of(core, struct sam9x60_div, core)\n \n+static struct sam9x60_div *notifier_div;\n+\n static inline bool sam9x60_pll_ready(struct regmap *regmap, int id)\n {\n \tunsigned int status;\n@@ -329,6 +333,26 @@ static const struct clk_ops sam9x60_frac\n \t.restore_context = sam9x60_frac_pll_restore_context,\n };\n \n+/* This function should be called with spinlock acquired. */\n+static void sam9x60_div_pll_set_div(struct sam9x60_pll_core *core, u32 div,\n+\t\t\t\t    bool enable)\n+{\n+\tstruct regmap *regmap = core->regmap;\n+\tu32 ena_msk = enable ? core->layout->endiv_mask : 0;\n+\tu32 ena_val = enable ? (1 << core->layout->endiv_shift) : 0;\n+\n+\tregmap_update_bits(regmap, AT91_PMC_PLL_CTRL0,\n+\t\t\t   core->layout->div_mask | ena_msk,\n+\t\t\t   (div << core->layout->div_shift) | ena_val);\n+\n+\tregmap_update_bits(regmap, AT91_PMC_PLL_UPDT,\n+\t\t\t   AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,\n+\t\t\t   AT91_PMC_PLL_UPDT_UPDATE | core->id);\n+\n+\twhile (!sam9x60_pll_ready(regmap, core->id))\n+\t\tcpu_relax();\n+}\n+\n static int sam9x60_div_pll_set(struct sam9x60_pll_core *core)\n {\n \tstruct sam9x60_div *div = to_sam9x60_div(core);\n@@ -346,17 +370,7 @@ static int sam9x60_div_pll_set(struct sa\n \tif (!!(val & core->layout->endiv_mask) && cdiv == div->div)\n \t\tgoto unlock;\n \n-\tregmap_update_bits(regmap, AT91_PMC_PLL_CTRL0,\n-\t\t\t   core->layout->div_mask | core->layout->endiv_mask,\n-\t\t\t   (div->div << core->layout->div_shift) |\n-\t\t\t   (1 << core->layout->endiv_shift));\n-\n-\tregmap_update_bits(regmap, AT91_PMC_PLL_UPDT,\n-\t\t\t   AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,\n-\t\t\t   AT91_PMC_PLL_UPDT_UPDATE | core->id);\n-\n-\twhile (!sam9x60_pll_ready(regmap, core->id))\n-\t\tcpu_relax();\n+\tsam9x60_div_pll_set_div(core, div->div, 1);\n \n unlock:\n \tspin_unlock_irqrestore(core->lock, flags);\n@@ -502,16 +516,7 @@ static int sam9x60_div_pll_set_rate_chg(\n \tif (cdiv == div->div)\n \t\tgoto unlock;\n \n-\tregmap_update_bits(regmap, AT91_PMC_PLL_CTRL0,\n-\t\t\t   core->layout->div_mask,\n-\t\t\t   (div->div << core->layout->div_shift));\n-\n-\tregmap_update_bits(regmap, AT91_PMC_PLL_UPDT,\n-\t\t\t   AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,\n-\t\t\t   AT91_PMC_PLL_UPDT_UPDATE | core->id);\n-\n-\twhile (!sam9x60_pll_ready(regmap, core->id))\n-\t\tcpu_relax();\n+\tsam9x60_div_pll_set_div(core, div->div, 0);\n \n unlock:\n \tspin_unlock_irqrestore(core->lock, irqflags);\n@@ -538,6 +543,48 @@ static void sam9x60_div_pll_restore_cont\n \t\tsam9x60_div_pll_set(core);\n }\n \n+static int sam9x60_div_pll_notifier_fn(struct notifier_block *notifier,\n+\t\t\t\t       unsigned long code, void *data)\n+{\n+\tstruct sam9x60_div *div = notifier_div;\n+\tstruct sam9x60_pll_core core = div->core;\n+\tstruct regmap *regmap = core.regmap;\n+\tunsigned long irqflags;\n+\tu32 val, cdiv;\n+\tint ret = NOTIFY_DONE;\n+\n+\tif (code != PRE_RATE_CHANGE)\n+\t\treturn ret;\n+\n+\t/*\n+\t * We switch to safe divider to avoid overclocking of other domains\n+\t * feed by us while the frac PLL (our parent) is changed.\n+\t */\n+\tdiv->div = div->safe_div;\n+\n+\tspin_lock_irqsave(core.lock, irqflags);\n+\tregmap_update_bits(regmap, AT91_PMC_PLL_UPDT, AT91_PMC_PLL_UPDT_ID_MSK,\n+\t\t\t   core.id);\n+\tregmap_read(regmap, AT91_PMC_PLL_CTRL0, &val);\n+\tcdiv = (val & core.layout->div_mask) >> core.layout->div_shift;\n+\n+\t/* Stop if nothing changed. */\n+\tif (cdiv == div->safe_div)\n+\t\tgoto unlock;\n+\n+\tsam9x60_div_pll_set_div(&core, div->div, 0);\n+\tret = NOTIFY_OK;\n+\n+unlock:\n+\tspin_unlock_irqrestore(core.lock, irqflags);\n+\n+\treturn ret;\n+}\n+\n+static struct notifier_block sam9x60_div_pll_notifier = {\n+\t.notifier_call = sam9x60_div_pll_notifier_fn,\n+};\n+\n static const struct clk_ops sam9x60_div_pll_ops = {\n \t.prepare = sam9x60_div_pll_prepare,\n \t.unprepare = sam9x60_div_pll_unprepare,\n@@ -647,7 +694,8 @@ struct clk_hw * __init\n sam9x60_clk_register_div_pll(struct regmap *regmap, spinlock_t *lock,\n \t\t\t     const char *name, const char *parent_name, u8 id,\n \t\t\t     const struct clk_pll_characteristics *characteristics,\n-\t\t\t     const struct clk_pll_layout *layout, u32 flags)\n+\t\t\t     const struct clk_pll_layout *layout, u32 flags,\n+\t\t\t     u32 safe_div)\n {\n \tstruct sam9x60_div *div;\n \tstruct clk_hw *hw;\n@@ -656,9 +704,13 @@ sam9x60_clk_register_div_pll(struct regm\n \tunsigned int val;\n \tint ret;\n \n-\tif (id > PLL_MAX_ID || !lock)\n+\t/* We only support one changeable PLL. */\n+\tif (id > PLL_MAX_ID || !lock || (safe_div && notifier_div))\n \t\treturn ERR_PTR(-EINVAL);\n \n+\tif (safe_div >= PLL_DIV_MAX)\n+\t\tsafe_div = PLL_DIV_MAX - 1;\n+\n \tdiv = kzalloc(sizeof(*div), GFP_KERNEL);\n \tif (!div)\n \t\treturn ERR_PTR(-ENOMEM);\n@@ -678,6 +730,7 @@ sam9x60_clk_register_div_pll(struct regm\n \tdiv->core.layout = layout;\n \tdiv->core.regmap = regmap;\n \tdiv->core.lock = lock;\n+\tdiv->safe_div = safe_div;\n \n \tspin_lock_irqsave(div->core.lock, irqflags);\n \n@@ -693,6 +746,9 @@ sam9x60_clk_register_div_pll(struct regm\n \tif (ret) {\n \t\tkfree(div);\n \t\thw = ERR_PTR(ret);\n+\t} else if (div->safe_div) {\n+\t\tnotifier_div = div;\n+\t\tclk_notifier_register(hw->clk, &sam9x60_div_pll_notifier);\n \t}\n \n \treturn hw;\n--- a/drivers/clk/at91/pmc.h\n+++ b/drivers/clk/at91/pmc.h\n@@ -214,7 +214,8 @@ struct clk_hw * __init\n sam9x60_clk_register_div_pll(struct regmap *regmap, spinlock_t *lock,\n \t\t\t     const char *name, const char *parent_name, u8 id,\n \t\t\t     const struct clk_pll_characteristics *characteristics,\n-\t\t\t     const struct clk_pll_layout *layout, u32 flags);\n+\t\t\t     const struct clk_pll_layout *layout, u32 flags,\n+\t\t\t     u32 safe_div);\n \n struct clk_hw * __init\n sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock,\n--- a/drivers/clk/at91/sam9x60.c\n+++ b/drivers/clk/at91/sam9x60.c\n@@ -242,7 +242,7 @@ static void __init sam9x60_pmc_setup(str\n \t\t\t\t\t    * This feeds CPU. It should not\n \t\t\t\t\t    * be disabled.\n \t\t\t\t\t    */\n-\t\t\t\t\t  CLK_IS_CRITICAL | CLK_SET_RATE_GATE);\n+\t\t\t\t\t  CLK_IS_CRITICAL | CLK_SET_RATE_GATE, 0);\n \tif (IS_ERR(hw))\n \t\tgoto err_free;\n \n@@ -260,7 +260,7 @@ static void __init sam9x60_pmc_setup(str\n \t\t\t\t\t  &pll_div_layout,\n \t\t\t\t\t  CLK_SET_RATE_GATE |\n \t\t\t\t\t  CLK_SET_PARENT_GATE |\n-\t\t\t\t\t  CLK_SET_RATE_PARENT);\n+\t\t\t\t\t  CLK_SET_RATE_PARENT, 0);\n \tif (IS_ERR(hw))\n \t\tgoto err_free;\n \n@@ -279,7 +279,7 @@ static void __init sam9x60_pmc_setup(str\n \thw = at91_clk_register_master_div(regmap, \"masterck_div\",\n \t\t\t\t\t  \"masterck_pres\", &sam9x60_master_layout,\n \t\t\t\t\t  &mck_characteristics, &mck_lock,\n-\t\t\t\t\t  CLK_SET_RATE_GATE);\n+\t\t\t\t\t  CLK_SET_RATE_GATE, 0);\n \tif (IS_ERR(hw))\n \t\tgoto err_free;\n \n--- a/drivers/clk/at91/sama7g5.c\n+++ b/drivers/clk/at91/sama7g5.c\n@@ -127,6 +127,8 @@ static const struct clk_pll_characterist\n  * @t:\t\tclock type\n  * @f:\t\tclock flags\n  * @eid:\texport index in sama7g5->chws[] array\n+ * @safe_div:\tintermediate divider need to be set on PRE_RATE_CHANGE\n+ *\t\tnotification\n  */\n static const struct {\n \tconst char *n;\n@@ -136,6 +138,7 @@ static const struct {\n \tunsigned long f;\n \tu8 t;\n \tu8 eid;\n+\tu8 safe_div;\n } sama7g5_plls[][PLL_ID_MAX] = {\n \t[PLL_ID_CPU] = {\n \t\t{ .n = \"cpupll_fracck\",\n@@ -156,7 +159,12 @@ static const struct {\n \t\t  .t = PLL_TYPE_DIV,\n \t\t   /* This feeds CPU. It should not be disabled. */\n \t\t  .f = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,\n-\t\t  .eid = PMC_CPUPLL, },\n+\t\t  .eid = PMC_CPUPLL,\n+\t\t  /*\n+\t\t   * Safe div=15 should be safe even for switching b/w 1GHz and\n+\t\t   * 90MHz (frac pll might go up to 1.2GHz).\n+\t\t   */\n+\t\t  .safe_div = 15, },\n \t},\n \n \t[PLL_ID_SYS] = {\n@@ -967,7 +975,8 @@ static void __init sama7g5_pmc_setup(str\n \t\t\t\t\tsama7g5_plls[i][j].p, i,\n \t\t\t\t\tsama7g5_plls[i][j].c,\n \t\t\t\t\tsama7g5_plls[i][j].l,\n-\t\t\t\t\tsama7g5_plls[i][j].f);\n+\t\t\t\t\tsama7g5_plls[i][j].f,\n+\t\t\t\t\tsama7g5_plls[i][j].safe_div);\n \t\t\t\tbreak;\n \n \t\t\tdefault:\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/244-clk-at91-clk-master-add-notifier-for-divider.patch",
    "content": "From 75d5d1d584ae73ba0c36d1d7255db6153ca4d3f3 Mon Sep 17 00:00:00 2001\nFrom: Claudiu Beznea <claudiu.beznea@microchip.com>\nDate: Mon, 11 Oct 2021 14:27:16 +0300\nSubject: [PATCH 244/247] clk: at91: clk-master: add notifier for divider\n\nSAMA7G5 supports DVFS by changing cpuck. On SAMA7G5 mck0 shares the same\nparent with cpuck as seen in the following clock tree:\n\n                       +----------> cpuck\n                       |\nFRAC PLL ---> DIV PLL -+-> DIV ---> mck0\n\nmck0 could go b/w 32KHz and 200MHz on SAMA7G5. To avoid mck0 overclocking\nwhile changing FRAC PLL or DIV PLL the commit implements a notifier for\nmck0 which applies a safe divider to register (maximum value of the divider\nwhich is 5) on PRE_RATE_CHANGE events (such that changes on PLL to not\noverclock mck0) and sets the maximum allowed rate on POST_RATE_CHANGE\nevents.\n\nSigned-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>\nLink: https://lore.kernel.org/r/20211011112719.3951784-13-claudiu.beznea@microchip.com\nAcked-by: Nicolas Ferre <nicolas.ferre@microchip.com>\nSigned-off-by: Stephen Boyd <sboyd@kernel.org>\n---\n drivers/clk/at91/at91rm9200.c  |   2 +-\n drivers/clk/at91/at91sam9260.c |   2 +-\n drivers/clk/at91/at91sam9g45.c |   2 +-\n drivers/clk/at91/at91sam9n12.c |   2 +-\n drivers/clk/at91/at91sam9rl.c  |   2 +-\n drivers/clk/at91/at91sam9x5.c  |   2 +-\n drivers/clk/at91/clk-master.c  | 244 +++++++++++++++++++++++----------\n drivers/clk/at91/dt-compat.c   |   2 +-\n drivers/clk/at91/pmc.h         |   2 +-\n drivers/clk/at91/sama5d2.c     |   2 +-\n drivers/clk/at91/sama5d3.c     |   2 +-\n drivers/clk/at91/sama5d4.c     |   2 +-\n drivers/clk/at91/sama7g5.c     |   2 +-\n 13 files changed, 186 insertions(+), 82 deletions(-)\n\n--- a/drivers/clk/at91/at91rm9200.c\n+++ b/drivers/clk/at91/at91rm9200.c\n@@ -152,7 +152,7 @@ static void __init at91rm9200_pmc_setup(\n \t\t\t\t\t  \"masterck_pres\",\n \t\t\t\t\t  &at91rm9200_master_layout,\n \t\t\t\t\t  &rm9200_mck_characteristics,\n-\t\t\t\t\t  &rm9200_mck_lock, CLK_SET_RATE_GATE);\n+\t\t\t\t\t  &rm9200_mck_lock, CLK_SET_RATE_GATE, 0);\n \tif (IS_ERR(hw))\n \t\tgoto err_free;\n \n--- a/drivers/clk/at91/at91sam9260.c\n+++ b/drivers/clk/at91/at91sam9260.c\n@@ -429,7 +429,7 @@ static void __init at91sam926x_pmc_setup\n \t\t\t\t\t  &at91rm9200_master_layout,\n \t\t\t\t\t  data->mck_characteristics,\n \t\t\t\t\t  &at91sam9260_mck_lock,\n-\t\t\t\t\t  CLK_SET_RATE_GATE);\n+\t\t\t\t\t  CLK_SET_RATE_GATE, 0);\n \tif (IS_ERR(hw))\n \t\tgoto err_free;\n \n--- a/drivers/clk/at91/at91sam9g45.c\n+++ b/drivers/clk/at91/at91sam9g45.c\n@@ -164,7 +164,7 @@ static void __init at91sam9g45_pmc_setup\n \t\t\t\t\t  &at91rm9200_master_layout,\n \t\t\t\t\t  &mck_characteristics,\n \t\t\t\t\t  &at91sam9g45_mck_lock,\n-\t\t\t\t\t  CLK_SET_RATE_GATE);\n+\t\t\t\t\t  CLK_SET_RATE_GATE, 0);\n \tif (IS_ERR(hw))\n \t\tgoto err_free;\n \n--- a/drivers/clk/at91/at91sam9n12.c\n+++ b/drivers/clk/at91/at91sam9n12.c\n@@ -191,7 +191,7 @@ static void __init at91sam9n12_pmc_setup\n \t\t\t\t\t  &at91sam9x5_master_layout,\n \t\t\t\t\t  &mck_characteristics,\n \t\t\t\t\t  &at91sam9n12_mck_lock,\n-\t\t\t\t\t  CLK_SET_RATE_GATE);\n+\t\t\t\t\t  CLK_SET_RATE_GATE, 0);\n \tif (IS_ERR(hw))\n \t\tgoto err_free;\n \n--- a/drivers/clk/at91/at91sam9rl.c\n+++ b/drivers/clk/at91/at91sam9rl.c\n@@ -132,7 +132,7 @@ static void __init at91sam9rl_pmc_setup(\n \t\t\t\t\t  \"masterck_pres\",\n \t\t\t\t\t  &at91rm9200_master_layout,\n \t\t\t\t\t  &sam9rl_mck_characteristics,\n-\t\t\t\t\t  &sam9rl_mck_lock, CLK_SET_RATE_GATE);\n+\t\t\t\t\t  &sam9rl_mck_lock, CLK_SET_RATE_GATE, 0);\n \tif (IS_ERR(hw))\n \t\tgoto err_free;\n \n--- a/drivers/clk/at91/at91sam9x5.c\n+++ b/drivers/clk/at91/at91sam9x5.c\n@@ -210,7 +210,7 @@ static void __init at91sam9x5_pmc_setup(\n \t\t\t\t\t  \"masterck_pres\",\n \t\t\t\t\t  &at91sam9x5_master_layout,\n \t\t\t\t\t  &mck_characteristics, &mck_lock,\n-\t\t\t\t\t  CLK_SET_RATE_GATE);\n+\t\t\t\t\t  CLK_SET_RATE_GATE, 0);\n \tif (IS_ERR(hw))\n \t\tgoto err_free;\n \n--- a/drivers/clk/at91/clk-master.c\n+++ b/drivers/clk/at91/clk-master.c\n@@ -5,6 +5,7 @@\n \n #include <linux/clk-provider.h>\n #include <linux/clkdev.h>\n+#include <linux/clk.h>\n #include <linux/clk/at91_pmc.h>\n #include <linux/of.h>\n #include <linux/mfd/syscon.h>\n@@ -36,8 +37,12 @@ struct clk_master {\n \tu8 id;\n \tu8 parent;\n \tu8 div;\n+\tu32 safe_div;\n };\n \n+/* MCK div reference to be used by notifier. */\n+static struct clk_master *master_div;\n+\n static inline bool clk_master_ready(struct clk_master *master)\n {\n \tunsigned int bit = master->id ? AT91_PMC_MCKXRDY : AT91_PMC_MCKRDY;\n@@ -153,107 +158,81 @@ static const struct clk_ops master_div_o\n \t.restore_context = clk_master_div_restore_context,\n };\n \n-static int clk_master_div_set_rate(struct clk_hw *hw, unsigned long rate,\n-\t\t\t\t   unsigned long parent_rate)\n+/* This function must be called with lock acquired. */\n+static int clk_master_div_set(struct clk_master *master,\n+\t\t\t      unsigned long parent_rate, int div)\n {\n-\tstruct clk_master *master = to_clk_master(hw);\n \tconst struct clk_master_characteristics *characteristics =\n \t\t\t\t\t\tmaster->characteristics;\n-\tunsigned long flags;\n-\tunsigned int mckr, tmp;\n-\tint div, i;\n+\tunsigned long rate = parent_rate;\n+\tunsigned int max_div = 0, div_index = 0, max_div_index = 0;\n+\tunsigned int i, mckr, tmp;\n \tint ret;\n \n-\tdiv = DIV_ROUND_CLOSEST(parent_rate, rate);\n-\tif (div > ARRAY_SIZE(characteristics->divisors))\n-\t\treturn -EINVAL;\n-\n \tfor (i = 0; i < ARRAY_SIZE(characteristics->divisors); i++) {\n \t\tif (!characteristics->divisors[i])\n \t\t\tbreak;\n \n-\t\tif (div == characteristics->divisors[i]) {\n-\t\t\tdiv = i;\n-\t\t\tbreak;\n+\t\tif (div == characteristics->divisors[i])\n+\t\t\tdiv_index = i;\n+\n+\t\tif (max_div < characteristics->divisors[i]) {\n+\t\t\tmax_div = characteristics->divisors[i];\n+\t\t\tmax_div_index = i;\n \t\t}\n \t}\n \n-\tif (i == ARRAY_SIZE(characteristics->divisors))\n-\t\treturn -EINVAL;\n+\tif (div > max_div)\n+\t\tdiv_index = max_div_index;\n \n-\tspin_lock_irqsave(master->lock, flags);\n \tret = regmap_read(master->regmap, master->layout->offset, &mckr);\n \tif (ret)\n-\t\tgoto unlock;\n+\t\treturn ret;\n \n \tmckr &= master->layout->mask;\n \ttmp = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK;\n-\tif (tmp == div)\n-\t\tgoto unlock;\n+\tif (tmp == div_index)\n+\t\treturn 0;\n+\n+\trate /= characteristics->divisors[div_index];\n+\tif (rate < characteristics->output.min)\n+\t\tpr_warn(\"master clk div is underclocked\");\n+\telse if (rate > characteristics->output.max)\n+\t\tpr_warn(\"master clk div is overclocked\");\n \n \tmckr &= ~(MASTER_DIV_MASK << MASTER_DIV_SHIFT);\n-\tmckr |= (div << MASTER_DIV_SHIFT);\n+\tmckr |= (div_index << MASTER_DIV_SHIFT);\n \tret = regmap_write(master->regmap, master->layout->offset, mckr);\n \tif (ret)\n-\t\tgoto unlock;\n+\t\treturn ret;\n \n \twhile (!clk_master_ready(master))\n \t\tcpu_relax();\n-unlock:\n-\tspin_unlock_irqrestore(master->lock, flags);\n+\n+\tmaster->div = characteristics->divisors[div_index];\n \n \treturn 0;\n }\n \n-static int clk_master_div_determine_rate(struct clk_hw *hw,\n-\t\t\t\t\t struct clk_rate_request *req)\n+static unsigned long clk_master_div_recalc_rate_chg(struct clk_hw *hw,\n+\t\t\t\t\t\t    unsigned long parent_rate)\n {\n \tstruct clk_master *master = to_clk_master(hw);\n-\tconst struct clk_master_characteristics *characteristics =\n-\t\t\t\t\t\tmaster->characteristics;\n-\tstruct clk_hw *parent;\n-\tunsigned long parent_rate, tmp_rate, best_rate = 0;\n-\tint i, best_diff = INT_MIN, tmp_diff;\n-\n-\tparent = clk_hw_get_parent(hw);\n-\tif (!parent)\n-\t\treturn -EINVAL;\n-\n-\tparent_rate = clk_hw_get_rate(parent);\n-\tif (!parent_rate)\n-\t\treturn -EINVAL;\n \n-\tfor (i = 0; i < ARRAY_SIZE(characteristics->divisors); i++) {\n-\t\tif (!characteristics->divisors[i])\n-\t\t\tbreak;\n-\n-\t\ttmp_rate = DIV_ROUND_CLOSEST_ULL(parent_rate,\n-\t\t\t\t\t\t characteristics->divisors[i]);\n-\t\ttmp_diff = abs(tmp_rate - req->rate);\n-\n-\t\tif (!best_rate || best_diff > tmp_diff) {\n-\t\t\tbest_diff = tmp_diff;\n-\t\t\tbest_rate = tmp_rate;\n-\t\t}\n-\n-\t\tif (!best_diff)\n-\t\t\tbreak;\n-\t}\n-\n-\treq->best_parent_rate = best_rate;\n-\treq->best_parent_hw = parent;\n-\treq->rate = best_rate;\n-\n-\treturn 0;\n+\treturn DIV_ROUND_CLOSEST_ULL(parent_rate, master->div);\n }\n \n static void clk_master_div_restore_context_chg(struct clk_hw *hw)\n {\n \tstruct clk_master *master = to_clk_master(hw);\n+\tunsigned long flags;\n \tint ret;\n \n-\tret = clk_master_div_set_rate(hw, master->pms.rate,\n-\t\t\t\t      master->pms.parent_rate);\n+\tspin_lock_irqsave(master->lock, flags);\n+\tret = clk_master_div_set(master, master->pms.parent_rate,\n+\t\t\t\t DIV_ROUND_CLOSEST(master->pms.parent_rate,\n+\t\t\t\t\t\t   master->pms.rate));\n+\tspin_unlock_irqrestore(master->lock, flags);\n \tif (ret)\n \t\tpr_warn(\"Failed to restore MCK DIV clock\\n\");\n }\n@@ -261,13 +240,116 @@ static void clk_master_div_restore_conte\n static const struct clk_ops master_div_ops_chg = {\n \t.prepare = clk_master_prepare,\n \t.is_prepared = clk_master_is_prepared,\n-\t.recalc_rate = clk_master_div_recalc_rate,\n-\t.determine_rate = clk_master_div_determine_rate,\n-\t.set_rate = clk_master_div_set_rate,\n+\t.recalc_rate = clk_master_div_recalc_rate_chg,\n \t.save_context = clk_master_div_save_context,\n \t.restore_context = clk_master_div_restore_context_chg,\n };\n \n+static int clk_master_div_notifier_fn(struct notifier_block *notifier,\n+\t\t\t\t      unsigned long code, void *data)\n+{\n+\tconst struct clk_master_characteristics *characteristics =\n+\t\t\t\t\t\tmaster_div->characteristics;\n+\tstruct clk_notifier_data *cnd = data;\n+\tunsigned long flags, new_parent_rate, new_rate;\n+\tunsigned int mckr, div, new_div = 0;\n+\tint ret, i;\n+\tlong tmp_diff;\n+\tlong best_diff = -1;\n+\n+\tspin_lock_irqsave(master_div->lock, flags);\n+\tswitch (code) {\n+\tcase PRE_RATE_CHANGE:\n+\t\t/*\n+\t\t * We want to avoid any overclocking of MCK DIV domain. To do\n+\t\t * this we set a safe divider (the underclocking is not of\n+\t\t * interest as we can go as low as 32KHz). The relation\n+\t\t * b/w this clock and its parents are as follows:\n+\t\t *\n+\t\t * FRAC PLL -> DIV PLL -> MCK DIV\n+\t\t *\n+\t\t * With the proper safe divider we should be good even with FRAC\n+\t\t * PLL at its maximum value.\n+\t\t */\n+\t\tret = regmap_read(master_div->regmap, master_div->layout->offset,\n+\t\t\t\t  &mckr);\n+\t\tif (ret) {\n+\t\t\tret = NOTIFY_STOP_MASK;\n+\t\t\tgoto unlock;\n+\t\t}\n+\n+\t\tmckr &= master_div->layout->mask;\n+\t\tdiv = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK;\n+\n+\t\t/* Switch to safe divider. */\n+\t\tclk_master_div_set(master_div,\n+\t\t\t\t   cnd->old_rate * characteristics->divisors[div],\n+\t\t\t\t   master_div->safe_div);\n+\t\tbreak;\n+\n+\tcase POST_RATE_CHANGE:\n+\t\t/*\n+\t\t * At this point we want to restore MCK DIV domain to its maximum\n+\t\t * allowed rate.\n+\t\t */\n+\t\tret = regmap_read(master_div->regmap, master_div->layout->offset,\n+\t\t\t\t  &mckr);\n+\t\tif (ret) {\n+\t\t\tret = NOTIFY_STOP_MASK;\n+\t\t\tgoto unlock;\n+\t\t}\n+\n+\t\tmckr &= master_div->layout->mask;\n+\t\tdiv = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK;\n+\t\tnew_parent_rate = cnd->new_rate * characteristics->divisors[div];\n+\n+\t\tfor (i = 0; i < ARRAY_SIZE(characteristics->divisors); i++) {\n+\t\t\tif (!characteristics->divisors[i])\n+\t\t\t\tbreak;\n+\n+\t\t\tnew_rate = DIV_ROUND_CLOSEST_ULL(new_parent_rate,\n+\t\t\t\t\t\t\t characteristics->divisors[i]);\n+\n+\t\t\ttmp_diff = characteristics->output.max - new_rate;\n+\t\t\tif (tmp_diff < 0)\n+\t\t\t\tcontinue;\n+\n+\t\t\tif (best_diff < 0 || best_diff > tmp_diff) {\n+\t\t\t\tnew_div = characteristics->divisors[i];\n+\t\t\t\tbest_diff = tmp_diff;\n+\t\t\t}\n+\n+\t\t\tif (!tmp_diff)\n+\t\t\t\tbreak;\n+\t\t}\n+\n+\t\tif (!new_div) {\n+\t\t\tret = NOTIFY_STOP_MASK;\n+\t\t\tgoto unlock;\n+\t\t}\n+\n+\t\t/* Update the div to preserve MCK DIV clock rate. */\n+\t\tclk_master_div_set(master_div, new_parent_rate,\n+\t\t\t\t   new_div);\n+\n+\t\tret = NOTIFY_OK;\n+\t\tbreak;\n+\n+\tdefault:\n+\t\tret = NOTIFY_DONE;\n+\t\tbreak;\n+\t}\n+\n+unlock:\n+\tspin_unlock_irqrestore(master_div->lock, flags);\n+\n+\treturn ret;\n+}\n+\n+static struct notifier_block clk_master_div_notifier = {\n+\t.notifier_call = clk_master_div_notifier_fn,\n+};\n+\n static void clk_sama7g5_master_best_diff(struct clk_rate_request *req,\n \t\t\t\t\t struct clk_hw *parent,\n \t\t\t\t\t unsigned long parent_rate,\n@@ -496,6 +578,8 @@ at91_clk_register_master_internal(struct\n \tstruct clk_master *master;\n \tstruct clk_init_data init;\n \tstruct clk_hw *hw;\n+\tunsigned int mckr;\n+\tunsigned long irqflags;\n \tint ret;\n \n \tif (!name || !num_parents || !parent_names || !lock)\n@@ -518,6 +602,16 @@ at91_clk_register_master_internal(struct\n \tmaster->chg_pid = chg_pid;\n \tmaster->lock = lock;\n \n+\tif (ops == &master_div_ops_chg) {\n+\t\tspin_lock_irqsave(master->lock, irqflags);\n+\t\tregmap_read(master->regmap, master->layout->offset, &mckr);\n+\t\tspin_unlock_irqrestore(master->lock, irqflags);\n+\n+\t\tmckr &= layout->mask;\n+\t\tmckr = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK;\n+\t\tmaster->div = characteristics->divisors[mckr];\n+\t}\n+\n \thw = &master->hw;\n \tret = clk_hw_register(NULL, &master->hw);\n \tif (ret) {\n@@ -554,19 +648,29 @@ at91_clk_register_master_div(struct regm\n \t\tconst char *name, const char *parent_name,\n \t\tconst struct clk_master_layout *layout,\n \t\tconst struct clk_master_characteristics *characteristics,\n-\t\tspinlock_t *lock, u32 flags)\n+\t\tspinlock_t *lock, u32 flags, u32 safe_div)\n {\n \tconst struct clk_ops *ops;\n+\tstruct clk_hw *hw;\n \n \tif (flags & CLK_SET_RATE_GATE)\n \t\tops = &master_div_ops;\n \telse\n \t\tops = &master_div_ops_chg;\n \n-\treturn at91_clk_register_master_internal(regmap, name, 1,\n-\t\t\t\t\t\t &parent_name, layout,\n-\t\t\t\t\t\t characteristics, ops,\n-\t\t\t\t\t\t lock, flags, -EINVAL);\n+\thw = at91_clk_register_master_internal(regmap, name, 1,\n+\t\t\t\t\t       &parent_name, layout,\n+\t\t\t\t\t       characteristics, ops,\n+\t\t\t\t\t       lock, flags, -EINVAL);\n+\n+\tif (!IS_ERR(hw) && safe_div) {\n+\t\tmaster_div = to_clk_master(hw);\n+\t\tmaster_div->safe_div = safe_div;\n+\t\tclk_notifier_register(hw->clk,\n+\t\t\t\t      &clk_master_div_notifier);\n+\t}\n+\n+\treturn hw;\n }\n \n static unsigned long\n--- a/drivers/clk/at91/dt-compat.c\n+++ b/drivers/clk/at91/dt-compat.c\n@@ -399,7 +399,7 @@ of_at91_clk_master_setup(struct device_n\n \n \thw = at91_clk_register_master_div(regmap, name, \"masterck_pres\",\n \t\t\t\t\t  layout, characteristics,\n-\t\t\t\t\t  &mck_lock, CLK_SET_RATE_GATE);\n+\t\t\t\t\t  &mck_lock, CLK_SET_RATE_GATE, 0);\n \tif (IS_ERR(hw))\n \t\tgoto out_free_characteristics;\n \n--- a/drivers/clk/at91/pmc.h\n+++ b/drivers/clk/at91/pmc.h\n@@ -182,7 +182,7 @@ at91_clk_register_master_div(struct regm\n \t\t\t     const char *parent_names,\n \t\t\t     const struct clk_master_layout *layout,\n \t\t\t     const struct clk_master_characteristics *characteristics,\n-\t\t\t     spinlock_t *lock, u32 flags);\n+\t\t\t     spinlock_t *lock, u32 flags, u32 safe_div);\n \n struct clk_hw * __init\n at91_clk_sama7g5_register_master(struct regmap *regmap,\n--- a/drivers/clk/at91/sama5d2.c\n+++ b/drivers/clk/at91/sama5d2.c\n@@ -249,7 +249,7 @@ static void __init sama5d2_pmc_setup(str\n \t\t\t\t\t  \"masterck_pres\",\n \t\t\t\t\t  &at91sam9x5_master_layout,\n \t\t\t\t\t  &mck_characteristics, &mck_lock,\n-\t\t\t\t\t  CLK_SET_RATE_GATE);\n+\t\t\t\t\t  CLK_SET_RATE_GATE, 0);\n \tif (IS_ERR(hw))\n \t\tgoto err_free;\n \n--- a/drivers/clk/at91/sama5d3.c\n+++ b/drivers/clk/at91/sama5d3.c\n@@ -184,7 +184,7 @@ static void __init sama5d3_pmc_setup(str\n \t\t\t\t\t  \"masterck_pres\",\n \t\t\t\t\t  &at91sam9x5_master_layout,\n \t\t\t\t\t  &mck_characteristics, &mck_lock,\n-\t\t\t\t\t  CLK_SET_RATE_GATE);\n+\t\t\t\t\t  CLK_SET_RATE_GATE, 0);\n \tif (IS_ERR(hw))\n \t\tgoto err_free;\n \n--- a/drivers/clk/at91/sama5d4.c\n+++ b/drivers/clk/at91/sama5d4.c\n@@ -199,7 +199,7 @@ static void __init sama5d4_pmc_setup(str\n \t\t\t\t\t  \"masterck_pres\",\n \t\t\t\t\t  &at91sam9x5_master_layout,\n \t\t\t\t\t  &mck_characteristics, &mck_lock,\n-\t\t\t\t\t  CLK_SET_RATE_GATE);\n+\t\t\t\t\t  CLK_SET_RATE_GATE, 0);\n \tif (IS_ERR(hw))\n \t\tgoto err_free;\n \n--- a/drivers/clk/at91/sama7g5.c\n+++ b/drivers/clk/at91/sama7g5.c\n@@ -1003,7 +1003,7 @@ static void __init sama7g5_pmc_setup(str\n \n \thw = at91_clk_register_master_div(regmap, \"mck0\", \"cpuck\",\n \t\t\t\t\t  &mck0_layout, &mck0_characteristics,\n-\t\t\t\t\t  &pmc_mck0_lock, 0);\n+\t\t\t\t\t  &pmc_mck0_lock, CLK_GET_RATE_NOCACHE, 5);\n \tif (IS_ERR(hw))\n \t\tgoto err_free;\n \n"
  },
  {
    "path": "target/linux/at91/patches-5.10/245-clk-at91-sama7g5-remove-prescaler-part-of-master-clo.patch",
    "content": "From 91a49481af7332853c4c921d46aded8210572210 Mon Sep 17 00:00:00 2001\nFrom: Claudiu Beznea <claudiu.beznea@microchip.com>\nDate: Mon, 11 Oct 2021 14:27:17 +0300\nSubject: [PATCH 245/247] clk: at91: sama7g5: remove prescaler part of master\n clock\n\nOn SAMA7G5 the prescaler part of master clock has been implemented as a\nchangeable one. Everytime the prescaler is changed the PMC_SR.MCKRDY bit\nmust be polled. Value 1 for PMC_SR.MCKRDY means the prescaler update is\ndone. Driver polls for this bit until it becomes 1. On SAMA7G5 it has\nbeen discovered that in some conditions the PMC_SR.MCKRDY is not rising\nbut the rate it provides it's stable. The workaround is to add a timeout\nwhen polling for PMC_SR.MCKRDY. At the moment, for SAMA7G5, the prescaler\nwill be removed from Linux clock tree as all the frequencies for CPU could\nbe obtained from PLL and also there will be less overhead when changing\nfrequency via DVFS.\n\nSigned-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>\nLink: https://lore.kernel.org/r/20211011112719.3951784-14-claudiu.beznea@microchip.com\nAcked-by: Nicolas Ferre <nicolas.ferre@microchip.com>\nSigned-off-by: Stephen Boyd <sboyd@kernel.org>\n---\n drivers/clk/at91/sama7g5.c | 11 +----------\n 1 file changed, 1 insertion(+), 10 deletions(-)\n\n--- a/drivers/clk/at91/sama7g5.c\n+++ b/drivers/clk/at91/sama7g5.c\n@@ -992,16 +992,7 @@ static void __init sama7g5_pmc_setup(str\n \t}\n \n \tparent_names[0] = \"cpupll_divpmcck\";\n-\thw = at91_clk_register_master_pres(regmap, \"cpuck\", 1, parent_names,\n-\t\t\t\t\t   &mck0_layout, &mck0_characteristics,\n-\t\t\t\t\t   &pmc_mck0_lock,\n-\t\t\t\t\t   CLK_SET_RATE_PARENT, 0);\n-\tif (IS_ERR(hw))\n-\t\tgoto err_free;\n-\n-\tsama7g5_pmc->chws[PMC_CPU] = hw;\n-\n-\thw = at91_clk_register_master_div(regmap, \"mck0\", \"cpuck\",\n+\thw = at91_clk_register_master_div(regmap, \"mck0\", \"cpupll_divpmcck\",\n \t\t\t\t\t  &mck0_layout, &mck0_characteristics,\n \t\t\t\t\t  &pmc_mck0_lock, CLK_GET_RATE_NOCACHE, 5);\n \tif (IS_ERR(hw))\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/246-clk-at91-sama7g5-set-low-limit-for-mck0-at-32KHz.patch",
    "content": "From 9fd5a49f6da9de5da83f4a53eccefad647ab15ed Mon Sep 17 00:00:00 2001\nFrom: Claudiu Beznea <claudiu.beznea@microchip.com>\nDate: Mon, 11 Oct 2021 14:27:18 +0300\nSubject: [PATCH 246/247] clk: at91: sama7g5: set low limit for mck0 at 32KHz\n\nMCK0 could go as low as 32KHz. Set this limit.\n\nSigned-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>\nLink: https://lore.kernel.org/r/20211011112719.3951784-15-claudiu.beznea@microchip.com\nAcked-by: Nicolas Ferre <nicolas.ferre@microchip.com>\nSigned-off-by: Stephen Boyd <sboyd@kernel.org>\n---\n drivers/clk/at91/sama7g5.c | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/drivers/clk/at91/sama7g5.c\n+++ b/drivers/clk/at91/sama7g5.c\n@@ -850,7 +850,7 @@ static const struct {\n \n /* MCK0 characteristics. */\n static const struct clk_master_characteristics mck0_characteristics = {\n-\t.output = { .min = 50000000, .max = 200000000 },\n+\t.output = { .min = 32768, .max = 200000000 },\n \t.divisors = { 1, 2, 4, 3, 5 },\n \t.have_div3_pres = 1,\n };\n"
  },
  {
    "path": "target/linux/at91/patches-5.10/247-clk-use-clk_core_get_rate_recalc-in-clk_rate_get.patch",
    "content": "From fe07791494a78d5a4be1363385e6ba7940740644 Mon Sep 17 00:00:00 2001\nFrom: Claudiu Beznea <claudiu.beznea@microchip.com>\nDate: Mon, 11 Oct 2021 14:27:19 +0300\nSubject: [PATCH 247/247] clk: use clk_core_get_rate_recalc() in clk_rate_get()\n\nIn case clock flags contains CLK_GET_RATE_NOCACHE the clk_rate_get()\nwill return the cached rate. Thus, use clk_core_get_rate_recalc() which\ntakes proper action when clock flags contains CLK_GET_RATE_NOCACHE.\n\nSigned-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>\nLink: https://lore.kernel.org/r/20211011112719.3951784-16-claudiu.beznea@microchip.com\nAcked-by: Nicolas Ferre <nicolas.ferre@microchip.com>\n[sboyd@kernel.org: Grab prepare lock around operation]\nSigned-off-by: Stephen Boyd <sboyd@kernel.org>\n---\n drivers/clk/clk.c | 5 ++++-\n 1 file changed, 4 insertions(+), 1 deletion(-)\n\n--- a/drivers/clk/clk.c\n+++ b/drivers/clk/clk.c\n@@ -3106,7 +3106,10 @@ static int clk_rate_get(void *data, u64\n {\n \tstruct clk_core *core = data;\n \n-\t*val = core->rate;\n+\tclk_prepare_lock();\n+\t*val = clk_core_get_rate_recalc(core);\n+\tclk_prepare_unlock();\n+\n \treturn 0;\n }\n \n"
  },
  {
    "path": "target/linux/at91/patches-5.10/99-scripts-fix-compilation-error.patch",
    "content": "From 6d18eaaaff92f928eab6fad2708b6d28785b4872 Mon Sep 17 00:00:00 2001\nFrom: Claudiu Beznea <claudiu.beznea@microchip.com>\nDate: Wed, 13 Oct 2021 08:32:07 +0300\nSubject: [PATCH] scripts: fix compilation error\n\nSigned-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>\n---\n scripts/Makefile | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/scripts/Makefile\n+++ b/scripts/Makefile\n@@ -21,7 +21,7 @@ HOSTCFLAGS_asn1_compiler.o = -I$(srctree\n HOSTCFLAGS_sign-file.o = $(CRYPTO_CFLAGS)\n HOSTLDLIBS_sign-file = $(CRYPTO_LIBS)\n HOSTCFLAGS_extract-cert.o = $(CRYPTO_CFLAGS)\n-HOSTLDLIBS_extract-cert = $(CRYPTO_LIBS)\n+HOSTLDLIBS_extract-cert = $(CRYPTO_LIBS) -lpthread\n \n ifdef CONFIG_UNWINDER_ORC\n ifeq ($(ARCH),x86_64)\n"
  },
  {
    "path": "target/linux/at91/sam9x/config-default",
    "content": "CONFIG_ALIGNMENT_TRAP=y\nCONFIG_ARCH_32BIT_OFF_T=y\nCONFIG_ARCH_AT91=y\nCONFIG_ARCH_HIBERNATION_POSSIBLE=y\nCONFIG_ARCH_KEEP_MEMBLOCK=y\nCONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y\nCONFIG_ARCH_MULTIPLATFORM=y\n# CONFIG_ARCH_MULTI_V4 is not set\nCONFIG_ARCH_MULTI_V4T=y\nCONFIG_ARCH_MULTI_V4_V5=y\nCONFIG_ARCH_MULTI_V5=y\nCONFIG_ARCH_NR_GPIO=0\nCONFIG_ARCH_OPTIONAL_KERNEL_RWX=y\nCONFIG_ARCH_SELECT_MEMORY_MODEL=y\nCONFIG_ARCH_SPARSEMEM_ENABLE=y\nCONFIG_ARCH_SUSPEND_POSSIBLE=y\nCONFIG_ARM=y\nCONFIG_ARM_CPU_SUSPEND=y\nCONFIG_ARM_HAS_SG_CHAIN=y\nCONFIG_ARM_L1_CACHE_SHIFT=5\nCONFIG_ARM_PATCH_PHYS_VIRT=y\nCONFIG_ARM_THUMB=y\nCONFIG_ARM_UNWIND=y\n# CONFIG_ASN1 is not set\n# CONFIG_AT91RM9200_WATCHDOG is not set\nCONFIG_AT91SAM9X_WATCHDOG=y\n# CONFIG_AT91_ADC is not set\nCONFIG_AT91_SAMA5D2_ADC=y\nCONFIG_AT91_SOC_ID=y\n# CONFIG_AT91_SOC_SFR is not set\nCONFIG_ATMEL_AIC5_IRQ=y\nCONFIG_ATMEL_AIC_IRQ=y\nCONFIG_ATMEL_CLOCKSOURCE_PIT=y\nCONFIG_ATMEL_CLOCKSOURCE_TCB=y\nCONFIG_ATMEL_EBI=y\nCONFIG_ATMEL_PIT=y\nCONFIG_ATMEL_PM=y\nCONFIG_ATMEL_SDRAMC=y\nCONFIG_ATMEL_SSC=y\nCONFIG_ATMEL_ST=y\nCONFIG_ATMEL_TCB_CLKSRC=y\nCONFIG_ATMEL_TCLIB=y\nCONFIG_AT_HDMAC=y\nCONFIG_AT_XDMAC=y\nCONFIG_AUTO_ZRELADDR=y\nCONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y\nCONFIG_BLK_PM=y\nCONFIG_CLKDEV_LOOKUP=y\nCONFIG_CLKSRC_MMIO=y\nCONFIG_CLONE_BACKWARDS=y\nCONFIG_COMMON_CLK=y\nCONFIG_COMMON_CLK_AT91=y\nCONFIG_COMPAT_32BIT_TIME=y\nCONFIG_CONFIGFS_FS=y\nCONFIG_CPU_32v4T=y\nCONFIG_CPU_32v5=y\nCONFIG_CPU_ABRT_EV4T=y\nCONFIG_CPU_ABRT_EV5TJ=y\nCONFIG_CPU_ARM920T=y\nCONFIG_CPU_ARM926T=y\n# CONFIG_CPU_CACHE_ROUND_ROBIN is not set\nCONFIG_CPU_CACHE_V4WT=y\nCONFIG_CPU_CACHE_VIVT=y\nCONFIG_CPU_COPY_V4WB=y\nCONFIG_CPU_CP15=y\nCONFIG_CPU_CP15_MMU=y\n# CONFIG_CPU_DCACHE_WRITETHROUGH is not set\nCONFIG_CPU_NO_EFFICIENT_FFS=y\nCONFIG_CPU_PABRT_LEGACY=y\nCONFIG_CPU_PM=y\nCONFIG_CPU_THUMB_CAPABLE=y\nCONFIG_CPU_TLB_V4WBI=y\nCONFIG_CPU_USE_DOMAINS=y\nCONFIG_CRC16=y\nCONFIG_CRC7=y\nCONFIG_CRC_CCITT=y\nCONFIG_CRC_ITU_T=y\nCONFIG_CRYPTO_CRC32C=y\nCONFIG_CRYPTO_DEFLATE=y\nCONFIG_CRYPTO_HASH_INFO=y\nCONFIG_CRYPTO_LZO=y\nCONFIG_CRYPTO_RNG2=y\nCONFIG_CRYPTO_ZSTD=y\nCONFIG_DEBUG_INFO=y\nCONFIG_DEBUG_LL_INCLUDE=\"mach/debug-macro.S\"\nCONFIG_DMADEVICES=y\nCONFIG_DMA_ENGINE=y\nCONFIG_DMA_OF=y\nCONFIG_DMA_OPS=y\nCONFIG_DMA_REMAP=y\nCONFIG_DTC=y\nCONFIG_EDAC_ATOMIC_SCRUB=y\nCONFIG_EDAC_SUPPORT=y\nCONFIG_EEPROM_AT24=y\nCONFIG_EXT4_FS=y\nCONFIG_FIXED_PHY=y\nCONFIG_FIX_EARLYCON_MEM=y\nCONFIG_FREEZER=y\nCONFIG_FS_IOMAP=y\nCONFIG_FS_MBCACHE=y\nCONFIG_FW_CACHE=y\nCONFIG_FW_LOADER_PAGED_BUF=y\nCONFIG_GENERIC_ALLOCATOR=y\nCONFIG_GENERIC_ATOMIC64=y\nCONFIG_GENERIC_BUG=y\nCONFIG_GENERIC_CLOCKEVENTS=y\nCONFIG_GENERIC_CPU_AUTOPROBE=y\nCONFIG_GENERIC_EARLY_IOREMAP=y\nCONFIG_GENERIC_IDLE_POLL_SETUP=y\nCONFIG_GENERIC_IRQ_CHIP=y\nCONFIG_GENERIC_IRQ_MULTI_HANDLER=y\nCONFIG_GENERIC_IRQ_SHOW=y\nCONFIG_GENERIC_IRQ_SHOW_LEVEL=y\nCONFIG_GENERIC_PCI_IOMAP=y\nCONFIG_GENERIC_PINCONF=y\nCONFIG_GENERIC_PINCTRL_GROUPS=y\nCONFIG_GENERIC_PINMUX_FUNCTIONS=y\nCONFIG_GENERIC_SCHED_CLOCK=y\nCONFIG_GENERIC_SMP_IDLE_THREAD=y\nCONFIG_GENERIC_STRNCPY_FROM_USER=y\nCONFIG_GENERIC_STRNLEN_USER=y\nCONFIG_GLOB=y\nCONFIG_GPIOLIB=y\nCONFIG_GPIOLIB_IRQCHIP=y\nCONFIG_HANDLE_DOMAIN_IRQ=y\nCONFIG_HARDIRQS_SW_RESEND=y\nCONFIG_HAS_DMA=y\nCONFIG_HAS_IOMEM=y\nCONFIG_HAS_IOPORT_MAP=y\nCONFIG_HW_RANDOM=y\nCONFIG_HW_RANDOM_ATMEL=y\nCONFIG_HZ=128\nCONFIG_HZ_FIXED=128\nCONFIG_HZ_PERIODIC=y\nCONFIG_I2C=y\nCONFIG_I2C_ALGOBIT=y\nCONFIG_I2C_AT91=y\n# CONFIG_I2C_AT91_SLAVE_EXPERIMENTAL is not set\nCONFIG_I2C_BOARDINFO=y\nCONFIG_I2C_CHARDEV=y\nCONFIG_I2C_COMPAT=y\nCONFIG_I2C_GPIO=y\nCONFIG_IIO=y\nCONFIG_IIO_BUFFER=y\nCONFIG_IIO_KFIFO_BUF=y\nCONFIG_IIO_TRIGGER=y\nCONFIG_IIO_TRIGGERED_BUFFER=y\nCONFIG_INITRAMFS_SOURCE=\"\"\nCONFIG_INPUT=y\nCONFIG_IRQCHIP=y\nCONFIG_IRQ_DOMAIN=y\nCONFIG_IRQ_FORCED_THREADING=y\nCONFIG_IRQ_WORK=y\nCONFIG_JBD2=y\nCONFIG_LEDS_GPIO=y\nCONFIG_LEDS_PWM=y\nCONFIG_LEDS_TRIGGER_CPU=y\nCONFIG_LEDS_TRIGGER_GPIO=y\nCONFIG_LIBFDT=y\nCONFIG_LOCK_DEBUGGING_SUPPORT=y\nCONFIG_LZO_COMPRESS=y\nCONFIG_LZO_DECOMPRESS=y\nCONFIG_MACB=y\nCONFIG_MDIO_BUS=y\nCONFIG_MDIO_DEVICE=y\nCONFIG_MDIO_DEVRES=y\nCONFIG_MEMFD_CREATE=y\nCONFIG_MEMORY=y\nCONFIG_MFD_AT91_USART=y\nCONFIG_MFD_ATMEL_FLEXCOM=y\nCONFIG_MFD_ATMEL_HLCDC=y\nCONFIG_MFD_ATMEL_SMC=y\nCONFIG_MFD_CORE=y\nCONFIG_MFD_SYSCON=y\nCONFIG_MICREL_PHY=y\nCONFIG_MICROCHIP_PIT64B=y\nCONFIG_MIGRATION=y\nCONFIG_MMC=y\nCONFIG_MMC_ATMELMCI=y\nCONFIG_MMC_BLOCK=y\nCONFIG_MMC_SDHCI=y\nCONFIG_MMC_SDHCI_OF_AT91=y\nCONFIG_MMC_SDHCI_PLTFM=y\nCONFIG_MODULES_USE_ELF_REL=y\nCONFIG_MTD_CMDLINE_PARTS=y\nCONFIG_MTD_DATAFLASH=y\n# CONFIG_MTD_DATAFLASH_OTP is not set\n# CONFIG_MTD_DATAFLASH_WRITE_VERIFY is not set\nCONFIG_MTD_SPI_NOR=y\nCONFIG_MTD_UBI=y\nCONFIG_MTD_UBI_BEB_LIMIT=20\n# CONFIG_MTD_UBI_BLOCK is not set\nCONFIG_MTD_UBI_FASTMAP=y\nCONFIG_MTD_UBI_GLUEBI=y\nCONFIG_MTD_UBI_WL_THRESHOLD=4096\nCONFIG_NEED_DMA_MAP_STATE=y\nCONFIG_NEED_KUSER_HELPERS=y\nCONFIG_NEED_PER_CPU_KM=y\nCONFIG_NLS=y\nCONFIG_NVMEM=y\nCONFIG_NVMEM_SYSFS=y\nCONFIG_OF=y\nCONFIG_OF_ADDRESS=y\nCONFIG_OF_EARLY_FLATTREE=y\nCONFIG_OF_FLATTREE=y\nCONFIG_OF_GPIO=y\nCONFIG_OF_IRQ=y\nCONFIG_OF_KOBJ=y\nCONFIG_OF_MDIO=y\nCONFIG_OF_NET=y\nCONFIG_OLD_SIGACTION=y\nCONFIG_OLD_SIGSUSPEND3=y\nCONFIG_PAGE_OFFSET=0xC0000000\nCONFIG_PERF_USE_VMALLOC=y\nCONFIG_PGTABLE_LEVELS=2\nCONFIG_PHYLIB=y\nCONFIG_PHYLINK=y\nCONFIG_PINCTRL=y\nCONFIG_PINCTRL_AT91=y\n# CONFIG_PINCTRL_AT91PIO4 is not set\nCONFIG_PINCTRL_MCP23S08=y\nCONFIG_PINCTRL_MCP23S08_I2C=y\nCONFIG_PINCTRL_MCP23S08_SPI=y\nCONFIG_PM=y\nCONFIG_PM_CLK=y\nCONFIG_PM_SLEEP=y\nCONFIG_POWER_RESET=y\nCONFIG_POWER_RESET_AT91_POWEROFF=y\nCONFIG_POWER_RESET_AT91_RESET=y\nCONFIG_POWER_RESET_AT91_SAMA5D2_SHDWC=y\nCONFIG_POWER_SUPPLY=y\nCONFIG_PWM=y\nCONFIG_PWM_ATMEL=y\nCONFIG_PWM_ATMEL_HLCDC_PWM=y\nCONFIG_PWM_ATMEL_TCB=y\nCONFIG_PWM_SYSFS=y\nCONFIG_RATIONAL=y\nCONFIG_REGMAP=y\nCONFIG_REGMAP_I2C=y\nCONFIG_REGMAP_MMIO=y\nCONFIG_REGMAP_SPI=y\nCONFIG_REGULATOR=y\nCONFIG_REGULATOR_FIXED_VOLTAGE=y\nCONFIG_RTC_CLASS=y\nCONFIG_RTC_DRV_AT91RM9200=y\nCONFIG_RTC_DRV_AT91SAM9=y\nCONFIG_RTC_I2C_AND_SPI=y\nCONFIG_RTC_MC146818_LIB=y\nCONFIG_SAMA5D4_WATCHDOG=y\n# CONFIG_SERIAL_8250 is not set\nCONFIG_SERIAL_ATMEL=y\nCONFIG_SERIAL_ATMEL_CONSOLE=y\nCONFIG_SERIAL_ATMEL_PDC=y\n# CONFIG_SERIAL_ATMEL_TTYAT is not set\nCONFIG_SERIAL_MCTRL_GPIO=y\nCONFIG_SGL_ALLOC=y\nCONFIG_SOC_AT91RM9200=y\nCONFIG_SOC_AT91SAM9=y\nCONFIG_SOC_BUS=y\nCONFIG_SOC_SAM9X60=y\nCONFIG_SOC_SAM_V4_V5=y\nCONFIG_SPARSE_IRQ=y\nCONFIG_SPI=y\n# CONFIG_SPI_AT91_USART is not set\nCONFIG_SPI_ATMEL=y\nCONFIG_SPI_ATMEL_QUADSPI=y\nCONFIG_SPI_BITBANG=y\nCONFIG_SPI_GPIO=y\nCONFIG_SPI_MASTER=y\nCONFIG_SPI_MEM=y\nCONFIG_SPI_SPIDEV=y\nCONFIG_SPLIT_PTLOCK_CPUS=999999\nCONFIG_SRAM=y\nCONFIG_SRAM_EXEC=y\nCONFIG_SRCU=y\nCONFIG_SUSPEND=y\nCONFIG_SUSPEND_FREEZER=y\nCONFIG_SWPHY=y\nCONFIG_SYS_SUPPORTS_APM_EMULATION=y\nCONFIG_TICK_CPU_ACCOUNTING=y\nCONFIG_TIMER_OF=y\nCONFIG_TIMER_PROBE=y\nCONFIG_TINY_SRCU=y\nCONFIG_UBIFS_FS=y\nCONFIG_UBIFS_FS_ADVANCED_COMPR=y\nCONFIG_UNCOMPRESS_INCLUDE=\"debug/uncompress.h\"\nCONFIG_UNWINDER_ARM=y\nCONFIG_USB=y\nCONFIG_USB_ACM=y\nCONFIG_USB_ANNOUNCE_NEW_DEVICES=y\n# CONFIG_USB_AT91 is not set\n# CONFIG_USB_ATMEL_USBA is not set\nCONFIG_USB_COMMON=y\nCONFIG_USB_EHCI_HCD=y\nCONFIG_USB_EHCI_HCD_AT91=y\n# CONFIG_USB_EHCI_HCD_PLATFORM is not set\nCONFIG_USB_GADGET=y\nCONFIG_USB_OHCI_HCD=y\nCONFIG_USB_OHCI_HCD_AT91=y\nCONFIG_USB_OHCI_HCD_PLATFORM=y\nCONFIG_USB_SERIAL=y\n# CONFIG_USB_SERIAL_CONSOLE is not set\nCONFIG_USB_SERIAL_FTDI_SIO=y\nCONFIG_USB_SERIAL_PL2303=y\nCONFIG_USB_SUPPORT=y\nCONFIG_USE_OF=y\n# CONFIG_VFP is not set\nCONFIG_WATCHDOG_CORE=y\nCONFIG_XXHASH=y\nCONFIG_ZBOOT_ROM_BSS=0x0\nCONFIG_ZBOOT_ROM_TEXT=0x0\nCONFIG_ZLIB_DEFLATE=y\nCONFIG_ZLIB_INFLATE=y\nCONFIG_ZSTD_COMPRESS=y\nCONFIG_ZSTD_DECOMPRESS=y\n"
  },
  {
    "path": "target/linux/at91/sam9x/target.mk",
    "content": "BOARDNAME:= SAM9X Boards (ARMv5)\nCPU_TYPE:=arm926ej-s\n\ndefine Target/Description\n\tBuild generic firmware for Microchip AT91 SAM9x platforms\n\tusing the ARMv5 instruction set.\nendef\n"
  },
  {
    "path": "target/linux/at91/sama5/config-default",
    "content": "CONFIG_ALIGNMENT_TRAP=y\nCONFIG_ARCH_32BIT_OFF_T=y\nCONFIG_ARCH_AT91=y\nCONFIG_ARCH_HIBERNATION_POSSIBLE=y\nCONFIG_ARCH_KEEP_MEMBLOCK=y\nCONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y\nCONFIG_ARCH_MULTIPLATFORM=y\nCONFIG_ARCH_MULTI_V6_V7=y\nCONFIG_ARCH_MULTI_V7=y\nCONFIG_ARCH_NR_GPIO=0\nCONFIG_ARCH_OPTIONAL_KERNEL_RWX=y\nCONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y\nCONFIG_ARCH_SELECT_MEMORY_MODEL=y\nCONFIG_ARCH_SPARSEMEM_ENABLE=y\nCONFIG_ARCH_SUSPEND_POSSIBLE=y\nCONFIG_ARM=y\nCONFIG_ARM_AT91_CPUIDLE=y\nCONFIG_ARM_CPU_SUSPEND=y\nCONFIG_ARM_HAS_SG_CHAIN=y\nCONFIG_ARM_HEAVY_MB=y\nCONFIG_ARM_L1_CACHE_SHIFT=6\nCONFIG_ARM_L1_CACHE_SHIFT_6=y\nCONFIG_ARM_PATCH_IDIV=y\nCONFIG_ARM_PATCH_PHYS_VIRT=y\nCONFIG_ARM_THUMB=y\nCONFIG_ARM_UNWIND=y\nCONFIG_ARM_VIRT_EXT=y\n# CONFIG_ASN1 is not set\nCONFIG_AT91SAM9X_WATCHDOG=y\nCONFIG_AT91_ADC=y\nCONFIG_AT91_SAMA5D2_ADC=y\nCONFIG_AT91_SOC_ID=y\n# CONFIG_AT91_SOC_SFR is not set\nCONFIG_ATMEL_AIC5_IRQ=y\n# CONFIG_ATMEL_CLOCKSOURCE_PIT is not set\nCONFIG_ATMEL_CLOCKSOURCE_TCB=y\nCONFIG_ATMEL_EBI=y\nCONFIG_ATMEL_PM=y\nCONFIG_ATMEL_SDRAMC=y\nCONFIG_ATMEL_SSC=y\nCONFIG_ATMEL_TCB_CLKSRC=y\nCONFIG_ATMEL_TCLIB=y\nCONFIG_AT_HDMAC=y\nCONFIG_AT_XDMAC=y\nCONFIG_AUTO_ZRELADDR=y\nCONFIG_BACKLIGHT_CLASS_DEVICE=y\nCONFIG_BACKLIGHT_PWM=y\nCONFIG_BATTERY_ACT8945A=y\nCONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y\nCONFIG_BLK_DEV_LOOP=y\nCONFIG_BLK_DEV_RAM=y\nCONFIG_BLK_DEV_RAM_COUNT=4\nCONFIG_BLK_DEV_RAM_SIZE=8192\nCONFIG_BLK_DEV_SD=y\nCONFIG_BLK_PM=y\nCONFIG_BLK_SCSI_REQUEST=y\nCONFIG_CACHE_L2X0=y\nCONFIG_CLKDEV_LOOKUP=y\nCONFIG_CLONE_BACKWARDS=y\nCONFIG_CMA=y\nCONFIG_CMA_ALIGNMENT=8\nCONFIG_CMA_AREAS=7\n# CONFIG_CMA_DEBUG is not set\n# CONFIG_CMA_DEBUGFS is not set\nCONFIG_CMA_SIZE_MBYTES=16\n# CONFIG_CMA_SIZE_SEL_MAX is not set\nCONFIG_CMA_SIZE_SEL_MBYTES=y\n# CONFIG_CMA_SIZE_SEL_MIN is not set\n# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set\nCONFIG_CMDLINE=\"console=ttyS0,115200 initrd=0x21100000,25165824 root=/dev/ram0 rw\"\nCONFIG_COMMON_CLK=y\nCONFIG_COMMON_CLK_AT91=y\nCONFIG_COMPAT_32BIT_TIME=y\nCONFIG_CONFIGFS_FS=y\nCONFIG_CONTIG_ALLOC=y\nCONFIG_COREDUMP=y\nCONFIG_CPU_32v6K=y\nCONFIG_CPU_32v7=y\nCONFIG_CPU_ABRT_EV7=y\nCONFIG_CPU_CACHE_V7=y\nCONFIG_CPU_CACHE_VIPT=y\nCONFIG_CPU_COPY_V6=y\nCONFIG_CPU_CP15=y\nCONFIG_CPU_CP15_MMU=y\nCONFIG_CPU_HAS_ASID=y\nCONFIG_CPU_IDLE=y\nCONFIG_CPU_IDLE_GOV_LADDER=y\nCONFIG_CPU_IDLE_GOV_MENU=y\nCONFIG_CPU_PABRT_V7=y\nCONFIG_CPU_PM=y\nCONFIG_CPU_SPECTRE=y\nCONFIG_CPU_THUMB_CAPABLE=y\nCONFIG_CPU_TLB_V7=y\nCONFIG_CPU_V7=y\nCONFIG_CRASH_CORE=y\nCONFIG_CRASH_DUMP=y\nCONFIG_CRC16=y\n# CONFIG_CRC32_SARWATE is not set\nCONFIG_CRC32_SLICEBY8=y\nCONFIG_CROSS_MEMORY_ATTACH=y\nCONFIG_CRYPTO_CRC32C=y\nCONFIG_CRYPTO_DEFLATE=y\nCONFIG_CRYPTO_DRBG=y\nCONFIG_CRYPTO_DRBG_HMAC=y\nCONFIG_CRYPTO_DRBG_MENU=y\nCONFIG_CRYPTO_HASH_INFO=y\nCONFIG_CRYPTO_HMAC=y\nCONFIG_CRYPTO_JITTERENTROPY=y\nCONFIG_CRYPTO_LIB_SHA256=y\nCONFIG_CRYPTO_LZO=y\nCONFIG_CRYPTO_RNG=y\nCONFIG_CRYPTO_RNG2=y\nCONFIG_CRYPTO_RNG_DEFAULT=y\nCONFIG_CRYPTO_SEQIV=y\nCONFIG_CRYPTO_SHA256=y\nCONFIG_CRYPTO_ZSTD=y\nCONFIG_DCACHE_WORD_ACCESS=y\nCONFIG_DEBUG_LL_INCLUDE=\"mach/debug-macro.S\"\nCONFIG_DEBUG_MEMORY_INIT=y\nCONFIG_DEBUG_USER=y\nCONFIG_DMADEVICES=y\nCONFIG_DMA_CMA=y\nCONFIG_DMA_ENGINE=y\nCONFIG_DMA_OF=y\nCONFIG_DMA_OPS=y\nCONFIG_DMA_REMAP=y\nCONFIG_DMA_SHARED_BUFFER=y\nCONFIG_DNOTIFY=y\nCONFIG_DRM=y\nCONFIG_DRM_ATMEL_HLCDC=y\nCONFIG_DRM_BRIDGE=y\nCONFIG_DRM_FBDEV_EMULATION=y\nCONFIG_DRM_FBDEV_OVERALLOC=100\nCONFIG_DRM_GEM_CMA_HELPER=y\nCONFIG_DRM_KMS_CMA_HELPER=y\nCONFIG_DRM_KMS_FB_HELPER=y\nCONFIG_DRM_KMS_HELPER=y\nCONFIG_DRM_PANEL=y\nCONFIG_DRM_PANEL_BRIDGE=y\nCONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y\nCONFIG_DRM_PANEL_SIMPLE=y\nCONFIG_DTC=y\nCONFIG_DVB_CORE=y\nCONFIG_EDAC_ATOMIC_SCRUB=y\nCONFIG_EDAC_SUPPORT=y\nCONFIG_EEPROM_AT24=y\nCONFIG_ELF_CORE=y\nCONFIG_ENABLE_MUST_CHECK=y\nCONFIG_EXT4_FS=y\nCONFIG_FAT_FS=y\nCONFIG_FB=y\nCONFIG_FB_CFB_COPYAREA=y\nCONFIG_FB_CFB_FILLRECT=y\nCONFIG_FB_CFB_IMAGEBLIT=y\nCONFIG_FB_CMDLINE=y\nCONFIG_FB_DEFERRED_IO=y\nCONFIG_FB_SYS_COPYAREA=y\nCONFIG_FB_SYS_FILLRECT=y\nCONFIG_FB_SYS_FOPS=y\nCONFIG_FB_SYS_IMAGEBLIT=y\nCONFIG_FIXED_PHY=y\nCONFIG_FIX_EARLYCON_MEM=y\nCONFIG_FORCE_MAX_ZONEORDER=15\nCONFIG_FREEZER=y\nCONFIG_FS_IOMAP=y\nCONFIG_FS_MBCACHE=y\nCONFIG_FW_CACHE=y\nCONFIG_FW_LOADER_PAGED_BUF=y\nCONFIG_GENERIC_ALLOCATOR=y\nCONFIG_GENERIC_BUG=y\nCONFIG_GENERIC_CLOCKEVENTS=y\nCONFIG_GENERIC_CPU_AUTOPROBE=y\nCONFIG_GENERIC_EARLY_IOREMAP=y\nCONFIG_GENERIC_GETTIMEOFDAY=y\nCONFIG_GENERIC_IDLE_POLL_SETUP=y\nCONFIG_GENERIC_IRQ_CHIP=y\nCONFIG_GENERIC_IRQ_MULTI_HANDLER=y\nCONFIG_GENERIC_IRQ_SHOW=y\nCONFIG_GENERIC_IRQ_SHOW_LEVEL=y\nCONFIG_GENERIC_PCI_IOMAP=y\nCONFIG_GENERIC_PINCONF=y\nCONFIG_GENERIC_SCHED_CLOCK=y\nCONFIG_GENERIC_SMP_IDLE_THREAD=y\nCONFIG_GENERIC_STRNCPY_FROM_USER=y\nCONFIG_GENERIC_STRNLEN_USER=y\nCONFIG_GENERIC_TIME_VSYSCALL=y\nCONFIG_GENERIC_VDSO_32=y\nCONFIG_GLOB=y\nCONFIG_GPIOLIB=y\nCONFIG_GPIOLIB_IRQCHIP=y\nCONFIG_HANDLE_DOMAIN_IRQ=y\nCONFIG_HARDEN_BRANCH_PREDICTOR=y\nCONFIG_HARDIRQS_SW_RESEND=y\nCONFIG_HAS_DMA=y\nCONFIG_HAS_IOMEM=y\nCONFIG_HAS_IOPORT_MAP=y\nCONFIG_HAVE_SMP=y\nCONFIG_HDMI=y\nCONFIG_HID=y\nCONFIG_HID_GENERIC=y\nCONFIG_HW_RANDOM=y\nCONFIG_HW_RANDOM_ATMEL=y\nCONFIG_HZ_FIXED=0\nCONFIG_I2C=y\nCONFIG_I2C_ALGOBIT=y\nCONFIG_I2C_AT91=y\n# CONFIG_I2C_AT91_SLAVE_EXPERIMENTAL is not set\nCONFIG_I2C_BOARDINFO=y\nCONFIG_I2C_CHARDEV=y\nCONFIG_I2C_COMPAT=y\nCONFIG_I2C_GPIO=y\nCONFIG_I2C_HELPER_AUTO=y\nCONFIG_IIO=y\nCONFIG_IIO_BUFFER=y\nCONFIG_IIO_KFIFO_BUF=y\nCONFIG_IIO_TRIGGER=y\nCONFIG_IIO_TRIGGERED_BUFFER=y\nCONFIG_INITRAMFS_SOURCE=\"\"\nCONFIG_INPUT=y\nCONFIG_INPUT_EVDEV=y\nCONFIG_INPUT_KEYBOARD=y\nCONFIG_INPUT_LEDS=y\nCONFIG_INPUT_TOUCHSCREEN=y\nCONFIG_IRQCHIP=y\nCONFIG_IRQ_DOMAIN=y\nCONFIG_IRQ_FORCED_THREADING=y\nCONFIG_IRQ_WORK=y\nCONFIG_JBD2=y\n# CONFIG_JFFS2_FS is not set\nCONFIG_KCMP=y\nCONFIG_KERNEL_GZIP=y\n# CONFIG_KERNEL_XZ is not set\nCONFIG_KEXEC=y\nCONFIG_KEXEC_CORE=y\nCONFIG_KEYBOARD_GPIO=y\nCONFIG_KEYBOARD_QT1070=y\nCONFIG_LEDS_GPIO=y\nCONFIG_LEDS_PWM=y\nCONFIG_LEDS_TRIGGER_CPU=y\nCONFIG_LEDS_TRIGGER_GPIO=y\nCONFIG_LIBFDT=y\nCONFIG_LOCALVERSION_AUTO=y\nCONFIG_LOCK_DEBUGGING_SUPPORT=y\nCONFIG_LOG_BUF_SHIFT=16\nCONFIG_LZO_COMPRESS=y\nCONFIG_LZO_DECOMPRESS=y\nCONFIG_MACB=y\nCONFIG_MAGIC_SYSRQ=y\nCONFIG_MANDATORY_FILE_LOCKING=y\nCONFIG_MDIO_BUS=y\nCONFIG_MDIO_DEVICE=y\nCONFIG_MDIO_DEVRES=y\nCONFIG_MEDIA_ANALOG_TV_SUPPORT=y\nCONFIG_MEDIA_ATTACH=y\nCONFIG_MEDIA_CAMERA_SUPPORT=y\nCONFIG_MEDIA_DIGITAL_TV_SUPPORT=y\nCONFIG_MEDIA_PLATFORM_SUPPORT=y\nCONFIG_MEDIA_RADIO_SUPPORT=y\nCONFIG_MEDIA_SDR_SUPPORT=y\nCONFIG_MEDIA_SUPPORT=y\nCONFIG_MEDIA_TEST_SUPPORT=y\nCONFIG_MEDIA_TUNER=y\nCONFIG_MEDIA_USB_SUPPORT=y\nCONFIG_MEMFD_CREATE=y\nCONFIG_MEMORY=y\nCONFIG_MEMORY_ISOLATION=y\nCONFIG_MFD_ACT8945A=y\nCONFIG_MFD_AT91_USART=y\nCONFIG_MFD_ATMEL_FLEXCOM=y\nCONFIG_MFD_ATMEL_HLCDC=y\nCONFIG_MFD_ATMEL_SMC=y\nCONFIG_MFD_CORE=y\nCONFIG_MFD_SYSCON=y\nCONFIG_MICREL_PHY=y\nCONFIG_MIGHT_HAVE_CACHE_L2X0=y\nCONFIG_MIGRATION=y\nCONFIG_MMC=y\nCONFIG_MMC_ATMELMCI=y\nCONFIG_MMC_BLOCK=y\nCONFIG_MMC_SDHCI=y\nCONFIG_MMC_SDHCI_OF_AT91=y\nCONFIG_MMC_SDHCI_PLTFM=y\nCONFIG_MODULES_USE_ELF_REL=y\n# CONFIG_MTD_CFI_AMDSTD is not set\n# CONFIG_MTD_CFI_INTELEXT is not set\nCONFIG_MTD_CMDLINE_PARTS=y\n# CONFIG_MTD_COMPLEX_MAPPINGS is not set\nCONFIG_MTD_SPI_NOR=y\nCONFIG_MTD_UBI=y\nCONFIG_MTD_UBI_BEB_LIMIT=20\n# CONFIG_MTD_UBI_BLOCK is not set\nCONFIG_MTD_UBI_FASTMAP=y\nCONFIG_MTD_UBI_WL_THRESHOLD=4096\nCONFIG_NEED_DMA_MAP_STATE=y\nCONFIG_NEED_PER_CPU_KM=y\n# CONFIG_NEON is not set\nCONFIG_NLS=y\nCONFIG_NLS_CODEPAGE_437=y\nCONFIG_NLS_CODEPAGE_850=y\nCONFIG_NLS_ISO8859_1=y\nCONFIG_NLS_UTF8=y\nCONFIG_NO_HZ_COMMON=y\nCONFIG_NO_HZ_IDLE=y\nCONFIG_NVMEM=y\nCONFIG_NVMEM_SYSFS=y\nCONFIG_OF=y\nCONFIG_OF_ADDRESS=y\nCONFIG_OF_EARLY_FLATTREE=y\nCONFIG_OF_FLATTREE=y\nCONFIG_OF_GPIO=y\nCONFIG_OF_IRQ=y\nCONFIG_OF_KOBJ=y\nCONFIG_OF_MDIO=y\nCONFIG_OF_NET=y\nCONFIG_OLD_SIGACTION=y\nCONFIG_OLD_SIGSUSPEND3=y\nCONFIG_OUTER_CACHE=y\nCONFIG_OUTER_CACHE_SYNC=y\nCONFIG_PAGE_OFFSET=0xC0000000\n# CONFIG_PARTITION_ADVANCED is not set\nCONFIG_PERF_USE_VMALLOC=y\nCONFIG_PGTABLE_LEVELS=2\nCONFIG_PHYLIB=y\nCONFIG_PHYLINK=y\nCONFIG_PINCTRL=y\nCONFIG_PINCTRL_AT91=y\nCONFIG_PINCTRL_AT91PIO4=y\n# CONFIG_PINCTRL_SINGLE is not set\nCONFIG_PM=y\nCONFIG_PM_CLK=y\nCONFIG_PM_SLEEP=y\nCONFIG_POWER_RESET=y\nCONFIG_POWER_RESET_AT91_POWEROFF=y\nCONFIG_POWER_RESET_AT91_RESET=y\nCONFIG_POWER_RESET_AT91_SAMA5D2_SHDWC=y\nCONFIG_POWER_SUPPLY=y\n# CONFIG_PREVENT_FIRMWARE_BUILD is not set\nCONFIG_PRINTK_TIME=y\nCONFIG_PROC_VMCORE=y\nCONFIG_PWM=y\nCONFIG_PWM_ATMEL=y\nCONFIG_PWM_ATMEL_HLCDC_PWM=y\nCONFIG_PWM_ATMEL_TCB=y\nCONFIG_PWM_SYSFS=y\nCONFIG_RATIONAL=y\nCONFIG_REGMAP=y\nCONFIG_REGMAP_I2C=y\nCONFIG_REGMAP_MMIO=y\nCONFIG_REGMAP_SPI=y\nCONFIG_REGULATOR=y\nCONFIG_REGULATOR_ACT8865=y\nCONFIG_REGULATOR_ACT8945A=y\nCONFIG_REGULATOR_FIXED_VOLTAGE=y\nCONFIG_RTC_CLASS=y\nCONFIG_RTC_DRV_AT91RM9200=y\n# CONFIG_RTC_DRV_AT91SAM9 is not set\n# CONFIG_RTC_DRV_CMOS is not set\nCONFIG_RTC_I2C_AND_SPI=y\nCONFIG_SAMA5D4_WATCHDOG=y\nCONFIG_SCSI=y\n# CONFIG_SCSI_LOWLEVEL is not set\n# CONFIG_SERIAL_8250 is not set\nCONFIG_SERIAL_ATMEL=y\nCONFIG_SERIAL_ATMEL_CONSOLE=y\nCONFIG_SERIAL_ATMEL_PDC=y\n# CONFIG_SERIAL_ATMEL_TTYAT is not set\nCONFIG_SERIAL_MCTRL_GPIO=y\nCONFIG_SGL_ALLOC=y\nCONFIG_SG_POOL=y\nCONFIG_SND=y\nCONFIG_SND_ARM=y\n# CONFIG_SND_AT73C213 is not set\n# CONFIG_SND_AT91_SOC_SAM9G20_WM8731 is not set\n# CONFIG_SND_AT91_SOC_SAM9X5_WM8731 is not set\nCONFIG_SND_ATMEL_SOC=y\nCONFIG_SND_ATMEL_SOC_CLASSD=y\nCONFIG_SND_ATMEL_SOC_DMA=y\nCONFIG_SND_ATMEL_SOC_I2S=y\nCONFIG_SND_ATMEL_SOC_PDC=y\n# CONFIG_SND_ATMEL_SOC_PDMIC is not set\nCONFIG_SND_ATMEL_SOC_SSC=y\nCONFIG_SND_ATMEL_SOC_SSC_DMA=y\n# CONFIG_SND_ATMEL_SOC_SSC_PDC is not set\n# CONFIG_SND_ATMEL_SOC_TSE850_PCM5142 is not set\nCONFIG_SND_ATMEL_SOC_WM8904=y\n# CONFIG_SND_COMPRESS_OFFLOAD is not set\nCONFIG_SND_DMAENGINE_PCM=y\nCONFIG_SND_JACK=y\nCONFIG_SND_JACK_INPUT_DEV=y\n# CONFIG_SND_MCHP_SOC_I2S_MCC is not set\n# CONFIG_SND_MCHP_SOC_SPDIFRX is not set\n# CONFIG_SND_MCHP_SOC_SPDIFTX is not set\nCONFIG_SND_PCM=y\nCONFIG_SND_PCM_TIMER=y\nCONFIG_SND_SOC=y\nCONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y\nCONFIG_SND_SOC_I2C_AND_SPI=y\nCONFIG_SND_SOC_MIKROE_PROTO=y\n# CONFIG_SND_SOC_PCM5102A is not set\nCONFIG_SND_SOC_WM8731=y\nCONFIG_SND_SOC_WM8904=y\nCONFIG_SND_SPI=y\nCONFIG_SND_SUPPORT_OLD_API=y\nCONFIG_SND_TIMER=y\nCONFIG_SOC_BUS=y\nCONFIG_SOC_SAMA5=y\nCONFIG_SOC_SAMA5D2=y\nCONFIG_SOC_SAMA5D3=y\nCONFIG_SOC_SAMA5D4=y\n# CONFIG_SOC_SAMA7G5 is not set\nCONFIG_SOC_SAM_V7=y\nCONFIG_SOUND=y\nCONFIG_SOUND_OSS_CORE=y\nCONFIG_SPARSE_IRQ=y\nCONFIG_SPI=y\n# CONFIG_SPI_AT91_USART is not set\nCONFIG_SPI_ATMEL=y\nCONFIG_SPI_ATMEL_QUADSPI=y\nCONFIG_SPI_BITBANG=y\nCONFIG_SPI_GPIO=y\nCONFIG_SPI_MASTER=y\nCONFIG_SPI_MEM=y\n# CONFIG_SQUASHFS is not set\nCONFIG_SRAM=y\nCONFIG_SRAM_EXEC=y\nCONFIG_SRCU=y\n# CONFIG_STANDALONE is not set\nCONFIG_SUSPEND=y\nCONFIG_SUSPEND_FREEZER=y\nCONFIG_SWPHY=y\n# CONFIG_SWP_EMULATE is not set\nCONFIG_SYNC_FILE=y\nCONFIG_SYS_SUPPORTS_APM_EMULATION=y\nCONFIG_TICK_CPU_ACCOUNTING=y\nCONFIG_TIMER_OF=y\nCONFIG_TIMER_PROBE=y\nCONFIG_TINY_SRCU=y\nCONFIG_TOUCHSCREEN_ATMEL_MXT=y\nCONFIG_TOUCHSCREEN_PROPERTIES=y\nCONFIG_UACCESS_WITH_MEMCPY=y\nCONFIG_UBIFS_FS=y\nCONFIG_UNCOMPRESS_INCLUDE=\"debug/uncompress.h\"\nCONFIG_UNWINDER_ARM=y\nCONFIG_USB=y\nCONFIG_USB_ACM=y\nCONFIG_USB_ANNOUNCE_NEW_DEVICES=y\n# CONFIG_USB_AT91 is not set\n# CONFIG_USB_ATMEL_USBA is not set\n# CONFIG_USB_AUDIO is not set\nCONFIG_USB_COMMON=y\nCONFIG_USB_EHCI_HCD=y\nCONFIG_USB_EHCI_HCD_AT91=y\n# CONFIG_USB_EHCI_HCD_PLATFORM is not set\n# CONFIG_USB_EHCI_ROOT_HUB_TT is not set\nCONFIG_USB_GADGET=y\nCONFIG_USB_HID=y\nCONFIG_USB_OHCI_HCD=y\nCONFIG_USB_OHCI_HCD_AT91=y\nCONFIG_USB_OHCI_HCD_PLATFORM=y\n# CONFIG_USB_PWC is not set\nCONFIG_USB_SERIAL=y\n# CONFIG_USB_SERIAL_CONSOLE is not set\nCONFIG_USB_SERIAL_FTDI_SIO=y\nCONFIG_USB_SERIAL_PL2303=y\nCONFIG_USB_STORAGE=y\nCONFIG_USB_SUPPORT=y\nCONFIG_USE_OF=y\nCONFIG_V4L_PLATFORM_DRIVERS=y\nCONFIG_VFAT_FS=y\nCONFIG_VFP=y\nCONFIG_VFPv3=y\nCONFIG_VIDEOMODE_HELPERS=y\n# CONFIG_VIDEO_CPIA2 is not set\nCONFIG_VIDEO_DEV=y\nCONFIG_VIDEO_V4L2=y\nCONFIG_VIDEO_V4L2_I2C=y\nCONFIG_VM_EVENT_COUNTERS=y\nCONFIG_WATCHDOG_CORE=y\n# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set\nCONFIG_XXHASH=y\nCONFIG_ZBOOT_ROM_BSS=0x0\nCONFIG_ZBOOT_ROM_TEXT=0x0\nCONFIG_ZLIB_DEFLATE=y\nCONFIG_ZLIB_INFLATE=y\nCONFIG_ZSTD_COMPRESS=y\nCONFIG_ZSTD_DECOMPRESS=y\n"
  },
  {
    "path": "target/linux/at91/sama5/target.mk",
    "content": "BOARDNAME:=SAMA5 boards(Cortex-A5)\nCPU_TYPE:=cortex-a5\nCPU_SUBTYPE:=vfpv4\nFEATURES+=fpu\nDEFAULT_PACKAGES += kmod-usb2\n\ndefine Target/Description\n\tBuild generic firmware for Microchip(Atmel AT91) SAMA5D2,\n\tSAMA5D3 and SAMA5D4 MPU's using the ARMv7 instruction set.\nendef\n"
  },
  {
    "path": "target/linux/at91/sama7/config-default",
    "content": "CONFIG_ALIGNMENT_TRAP=y\n# CONFIG_ALLOW_DEV_COREDUMP is not set\nCONFIG_ARCH_32BIT_OFF_T=y\nCONFIG_ARCH_AT91=y\nCONFIG_ARCH_HIBERNATION_POSSIBLE=y\nCONFIG_ARCH_KEEP_MEMBLOCK=y\nCONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y\nCONFIG_ARCH_MULTIPLATFORM=y\nCONFIG_ARCH_MULTI_V6_V7=y\nCONFIG_ARCH_MULTI_V7=y\nCONFIG_ARCH_NR_GPIO=0\nCONFIG_ARCH_OPTIONAL_KERNEL_RWX=y\nCONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y\nCONFIG_ARCH_SELECT_MEMORY_MODEL=y\nCONFIG_ARCH_SPARSEMEM_ENABLE=y\nCONFIG_ARCH_SUSPEND_POSSIBLE=y\nCONFIG_ARM=y\nCONFIG_ARM_GIC=y\nCONFIG_ARM_HAS_SG_CHAIN=y\nCONFIG_ARM_L1_CACHE_SHIFT=6\nCONFIG_ARM_L1_CACHE_SHIFT_6=y\n# CONFIG_ARM_PATCH_IDIV is not set\nCONFIG_ARM_PATCH_PHYS_VIRT=y\nCONFIG_ARM_THUMB=y\nCONFIG_ARM_UNWIND=y\nCONFIG_ARM_VIRT_EXT=y\n# CONFIG_AT91SAM9X_WATCHDOG is not set\n# CONFIG_AT91_ADC is not set\nCONFIG_AT91_SAMA5D2_ADC=y\nCONFIG_AT91_SOC_ID=y\n# CONFIG_AT91_SOC_SFR is not set\nCONFIG_ATMEL_CLOCKSOURCE_TCB=y\n# CONFIG_ATMEL_EBI is not set\nCONFIG_ATMEL_SDRAMC=y\nCONFIG_ATMEL_TCB_CLKSRC=y\n# CONFIG_ATMEL_TCLIB is not set\n# CONFIG_AT_HDMAC is not set\nCONFIG_AT_XDMAC=y\nCONFIG_AUTO_ZRELADDR=y\nCONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y\nCONFIG_BLK_DEV_LOOP=y\nCONFIG_BLK_DEV_RAM=y\nCONFIG_BLK_DEV_RAM_COUNT=1\nCONFIG_BLK_DEV_RAM_SIZE=8192\nCONFIG_BLK_DEV_SD=y\nCONFIG_BLK_SCSI_REQUEST=y\n# CONFIG_CACHE_L2X0 is not set\nCONFIG_CAN=y\nCONFIG_CLKDEV_LOOKUP=y\nCONFIG_CLKSRC_MMIO=y\nCONFIG_CLONE_BACKWARDS=y\nCONFIG_CMA=y\nCONFIG_CMA_ALIGNMENT=9\nCONFIG_CMA_AREAS=7\n# CONFIG_CMA_DEBUG is not set\n# CONFIG_CMA_DEBUGFS is not set\nCONFIG_CMA_SIZE_MBYTES=256\n# CONFIG_CMA_SIZE_SEL_MAX is not set\nCONFIG_CMA_SIZE_SEL_MBYTES=y\n# CONFIG_CMA_SIZE_SEL_MIN is not set\n# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set\nCONFIG_CMDLINE=\"console=ttyS0,115200 earlyprintk nocache ignore_loglevel\"\nCONFIG_COMMON_CLK=y\nCONFIG_COMMON_CLK_AT91=y\n# CONFIG_COMPACTION is not set\nCONFIG_COMPAT_32BIT_TIME=y\nCONFIG_CONFIGFS_FS=y\nCONFIG_CONSOLE_TRANSLATIONS=y\nCONFIG_CONTIG_ALLOC=y\nCONFIG_CPUFREQ_DT=y\nCONFIG_CPUFREQ_DT_PLATDEV=y\nCONFIG_CPU_32v6K=y\nCONFIG_CPU_32v7=y\nCONFIG_CPU_ABRT_EV7=y\nCONFIG_CPU_CACHE_V7=y\nCONFIG_CPU_CACHE_VIPT=y\nCONFIG_CPU_COPY_V6=y\nCONFIG_CPU_CP15=y\nCONFIG_CPU_CP15_MMU=y\nCONFIG_CPU_FREQ=y\nCONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE=y\n# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set\nCONFIG_CPU_FREQ_GOV_ATTR_SET=y\nCONFIG_CPU_FREQ_GOV_COMMON=y\nCONFIG_CPU_FREQ_GOV_CONSERVATIVE=y\nCONFIG_CPU_FREQ_GOV_ONDEMAND=y\nCONFIG_CPU_FREQ_GOV_PERFORMANCE=y\nCONFIG_CPU_FREQ_GOV_POWERSAVE=y\nCONFIG_CPU_FREQ_GOV_USERSPACE=y\nCONFIG_CPU_FREQ_STAT=y\nCONFIG_CPU_HAS_ASID=y\nCONFIG_CPU_PABRT_V7=y\nCONFIG_CPU_SPECTRE=y\n# CONFIG_CPU_SW_DOMAIN_PAN is not set\nCONFIG_CPU_THUMB_CAPABLE=y\nCONFIG_CPU_TLB_V7=y\nCONFIG_CPU_V7=y\nCONFIG_CRC16=y\nCONFIG_CRC_CCITT=y\nCONFIG_CRC_ITU_T=y\nCONFIG_CRYPTO_CMAC=y\nCONFIG_CRYPTO_CRC32C=y\nCONFIG_CRYPTO_DEFLATE=y\nCONFIG_CRYPTO_DRBG=y\nCONFIG_CRYPTO_DRBG_HMAC=y\nCONFIG_CRYPTO_DRBG_MENU=y\nCONFIG_CRYPTO_ECB=y\nCONFIG_CRYPTO_ECC=y\nCONFIG_CRYPTO_ECDH=y\nCONFIG_CRYPTO_HMAC=y\nCONFIG_CRYPTO_JITTERENTROPY=y\nCONFIG_CRYPTO_LIB_SHA256=y\nCONFIG_CRYPTO_LZO=y\nCONFIG_CRYPTO_RNG=y\nCONFIG_CRYPTO_RNG2=y\nCONFIG_CRYPTO_RNG_DEFAULT=y\nCONFIG_CRYPTO_SHA256=y\nCONFIG_DCACHE_WORD_ACCESS=y\nCONFIG_DEBUG_AT91_SAMA7G5_FLEXCOM3=y\nCONFIG_DEBUG_AT91_UART=y\nCONFIG_DEBUG_INFO=y\nCONFIG_DEBUG_LL=y\nCONFIG_DEBUG_LL_INCLUDE=\"debug/at91.S\"\nCONFIG_DEBUG_UART_PHYS=0xe1824200\nCONFIG_DEBUG_UART_VIRT=0xe0824200\n# CONFIG_DEBUG_UNCOMPRESS is not set\nCONFIG_DEBUG_USER=y\nCONFIG_DEVTMPFS=y\nCONFIG_DEVTMPFS_MOUNT=y\nCONFIG_DMADEVICES=y\nCONFIG_DMATEST=y\nCONFIG_DMA_CMA=y\nCONFIG_DMA_ENGINE=y\nCONFIG_DMA_ENGINE_RAID=y\nCONFIG_DMA_OF=y\nCONFIG_DMA_OPS=y\nCONFIG_DMA_REMAP=y\nCONFIG_DTC=y\nCONFIG_DUMMY_CONSOLE=y\nCONFIG_EARLY_PRINTK=y\nCONFIG_EDAC_ATOMIC_SCRUB=y\nCONFIG_EDAC_SUPPORT=y\nCONFIG_EEPROM_AT24=y\n# CONFIG_EFI_PARTITION is not set\nCONFIG_EXT4_FS=y\nCONFIG_FANOTIFY=y\nCONFIG_FAT_FS=y\nCONFIG_FIXED_PHY=y\nCONFIG_FIX_EARLYCON_MEM=y\nCONFIG_FORCE_MAX_ZONEORDER=15\nCONFIG_FS_IOMAP=y\nCONFIG_FS_MBCACHE=y\nCONFIG_FW_LOADER_PAGED_BUF=y\nCONFIG_GENERIC_ALLOCATOR=y\nCONFIG_GENERIC_BUG=y\nCONFIG_GENERIC_CLOCKEVENTS=y\nCONFIG_GENERIC_CPU_AUTOPROBE=y\nCONFIG_GENERIC_CPU_VULNERABILITIES=y\nCONFIG_GENERIC_EARLY_IOREMAP=y\nCONFIG_GENERIC_GETTIMEOFDAY=y\nCONFIG_GENERIC_IDLE_POLL_SETUP=y\nCONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y\nCONFIG_GENERIC_IRQ_MULTI_HANDLER=y\nCONFIG_GENERIC_IRQ_SHOW=y\nCONFIG_GENERIC_IRQ_SHOW_LEVEL=y\nCONFIG_GENERIC_PCI_IOMAP=y\nCONFIG_GENERIC_PINCONF=y\nCONFIG_GENERIC_PINCTRL_GROUPS=y\nCONFIG_GENERIC_PINMUX_FUNCTIONS=y\nCONFIG_GENERIC_SCHED_CLOCK=y\nCONFIG_GENERIC_SMP_IDLE_THREAD=y\nCONFIG_GENERIC_STRNCPY_FROM_USER=y\nCONFIG_GENERIC_STRNLEN_USER=y\nCONFIG_GENERIC_TIME_VSYSCALL=y\nCONFIG_GENERIC_VDSO_32=y\nCONFIG_GLOB=y\nCONFIG_GPIOLIB=y\nCONFIG_GPIOLIB_IRQCHIP=y\nCONFIG_GRACE_PERIOD=y\nCONFIG_HANDLE_DOMAIN_IRQ=y\nCONFIG_HARDEN_BRANCH_PREDICTOR=y\nCONFIG_HARDIRQS_SW_RESEND=y\nCONFIG_HAS_DMA=y\nCONFIG_HAS_IOMEM=y\nCONFIG_HAS_IOPORT_MAP=y\nCONFIG_HAVE_SMP=y\nCONFIG_HW_CONSOLE=y\nCONFIG_HW_RANDOM=y\nCONFIG_HZ_FIXED=0\nCONFIG_I2C=y\nCONFIG_I2C_AT91=y\n# CONFIG_I2C_AT91_SLAVE_EXPERIMENTAL is not set\nCONFIG_I2C_BOARDINFO=y\nCONFIG_I2C_CHARDEV=y\nCONFIG_IIO=y\nCONFIG_IIO_BUFFER=y\nCONFIG_IIO_CONFIGFS=y\n# CONFIG_IIO_HRTIMER_TRIGGER is not set\nCONFIG_IIO_KFIFO_BUF=y\nCONFIG_IIO_SW_TRIGGER=y\n# CONFIG_IIO_TIGHTLOOP_TRIGGER is not set\nCONFIG_IIO_TRIGGER=y\nCONFIG_IIO_TRIGGERED_BUFFER=y\nCONFIG_INITRAMFS_SOURCE=\"\"\nCONFIG_INPUT=y\nCONFIG_IP_PNP=y\n# CONFIG_IP_PNP_BOOTP is not set\nCONFIG_IP_PNP_DHCP=y\n# CONFIG_IP_PNP_RARP is not set\nCONFIG_IRQCHIP=y\nCONFIG_IRQ_DOMAIN=y\nCONFIG_IRQ_DOMAIN_HIERARCHY=y\nCONFIG_IRQ_FORCED_THREADING=y\nCONFIG_IRQ_WORK=y\nCONFIG_JBD2=y\nCONFIG_LEDS_GPIO=y\nCONFIG_LIBFDT=y\nCONFIG_LOCKD=y\nCONFIG_LOCK_DEBUGGING_SUPPORT=y\nCONFIG_LOG_BUF_SHIFT=16\nCONFIG_LSM=\"N\"\nCONFIG_LZO_COMPRESS=y\nCONFIG_LZO_DECOMPRESS=y\nCONFIG_MACB=y\nCONFIG_MDIO_BUS=y\nCONFIG_MDIO_DEVICE=y\nCONFIG_MDIO_DEVRES=y\nCONFIG_MEDIA_CAMERA_SUPPORT=y\nCONFIG_MEDIA_CONTROLLER=y\nCONFIG_MEDIA_PLATFORM_SUPPORT=y\nCONFIG_MEDIA_SUPPORT=y\nCONFIG_MEDIA_SUPPORT_FILTER=y\nCONFIG_MEMFD_CREATE=y\nCONFIG_MEMORY=y\nCONFIG_MEMORY_ISOLATION=y\nCONFIG_MESSAGE_LOGLEVEL_DEFAULT=7\nCONFIG_MFD_AT91_USART=y\nCONFIG_MFD_ATMEL_FLEXCOM=y\nCONFIG_MFD_CORE=y\nCONFIG_MFD_SYSCON=y\nCONFIG_MICREL_PHY=y\nCONFIG_MICROCHIP_PIT64B=y\nCONFIG_MIGHT_HAVE_CACHE_L2X0=y\nCONFIG_MIGRATION=y\nCONFIG_MMC=y\n# CONFIG_MMC_ATMELMCI is not set\nCONFIG_MMC_BLOCK=y\nCONFIG_MMC_SDHCI=y\nCONFIG_MMC_SDHCI_OF_AT91=y\nCONFIG_MMC_SDHCI_PLTFM=y\nCONFIG_MODULES_USE_ELF_REL=y\nCONFIG_MODULE_FORCE_LOAD=y\nCONFIG_MODULE_FORCE_UNLOAD=y\nCONFIG_MTD_CMDLINE_PARTS=y\nCONFIG_NEED_DMA_MAP_STATE=y\nCONFIG_NEED_PER_CPU_KM=y\nCONFIG_NEON=y\nCONFIG_NET_SWITCHDEV=y\nCONFIG_NFS_FS=y\nCONFIG_NLS=y\nCONFIG_NLS_CODEPAGE_437=y\nCONFIG_NLS_CODEPAGE_850=y\nCONFIG_NLS_ISO8859_1=y\nCONFIG_NLS_UTF8=y\nCONFIG_NO_HZ_COMMON=y\nCONFIG_NO_HZ_IDLE=y\nCONFIG_NVMEM=y\nCONFIG_NVMEM_SYSFS=y\nCONFIG_OF=y\nCONFIG_OF_ADDRESS=y\nCONFIG_OF_EARLY_FLATTREE=y\nCONFIG_OF_FLATTREE=y\nCONFIG_OF_GPIO=y\nCONFIG_OF_IRQ=y\nCONFIG_OF_KOBJ=y\nCONFIG_OF_MDIO=y\nCONFIG_OF_NET=y\nCONFIG_OLD_SIGACTION=y\nCONFIG_OLD_SIGSUSPEND3=y\nCONFIG_PAGE_OFFSET=0xC0000000\nCONFIG_PCCARD=y\nCONFIG_PERF_USE_VMALLOC=y\nCONFIG_PGTABLE_LEVELS=2\nCONFIG_PHYLIB=y\nCONFIG_PHYLINK=y\nCONFIG_PINCTRL=y\nCONFIG_PINCTRL_AT91=y\nCONFIG_PINCTRL_AT91PIO4=y\nCONFIG_PM_OPP=y\nCONFIG_POWER_RESET=y\n# CONFIG_POWER_RESET_AT91_POWEROFF is not set\nCONFIG_POWER_RESET_AT91_RESET=y\nCONFIG_POWER_RESET_AT91_SAMA5D2_SHDWC=y\n# CONFIG_PREVENT_FIRMWARE_BUILD is not set\nCONFIG_PRINTK_TIME=y\nCONFIG_PWM=y\nCONFIG_PWM_ATMEL=y\nCONFIG_PWM_SYSFS=y\nCONFIG_RATIONAL=y\nCONFIG_REGMAP=y\nCONFIG_REGMAP_I2C=y\nCONFIG_REGMAP_MMIO=y\nCONFIG_REGMAP_SPI=y\nCONFIG_REGULATOR=y\nCONFIG_REGULATOR_FIXED_VOLTAGE=y\nCONFIG_REGULATOR_MCP16502=y\nCONFIG_ROOT_NFS=y\nCONFIG_RTC_CLASS=y\nCONFIG_RTC_DRV_AT91RM9200=y\nCONFIG_RTC_DRV_AT91SAM9=y\nCONFIG_RTC_I2C_AND_SPI=y\nCONFIG_RTC_MC146818_LIB=y\n# CONFIG_RUNTIME_TESTING_MENU is not set\nCONFIG_SAMA5D4_WATCHDOG=y\nCONFIG_SCSI=y\n# CONFIG_SERIAL_8250 is not set\nCONFIG_SERIAL_ATMEL=y\nCONFIG_SERIAL_ATMEL_CONSOLE=y\nCONFIG_SERIAL_ATMEL_PDC=y\n# CONFIG_SERIAL_ATMEL_TTYAT is not set\nCONFIG_SERIAL_MCTRL_GPIO=y\nCONFIG_SGL_ALLOC=y\nCONFIG_SG_POOL=y\nCONFIG_SND=y\nCONFIG_SND_ATMEL_SOC=y\n# CONFIG_SND_ATMEL_SOC_CLASSD is not set\n# CONFIG_SND_ATMEL_SOC_I2S is not set\n# CONFIG_SND_ATMEL_SOC_PDMIC is not set\n# CONFIG_SND_COMPRESS_OFFLOAD is not set\nCONFIG_SND_DMAENGINE_PCM=y\nCONFIG_SND_JACK=y\nCONFIG_SND_JACK_INPUT_DEV=y\nCONFIG_SND_MCHP_SOC_I2S_MCC=y\nCONFIG_SND_MCHP_SOC_SPDIFRX=y\nCONFIG_SND_MCHP_SOC_SPDIFTX=y\nCONFIG_SND_PCM=y\nCONFIG_SND_SIMPLE_CARD=y\nCONFIG_SND_SIMPLE_CARD_UTILS=y\nCONFIG_SND_SOC=y\nCONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y\nCONFIG_SND_SOC_I2C_AND_SPI=y\n# CONFIG_SND_SOC_MIKROE_PROTO is not set\nCONFIG_SND_SOC_PCM5102A=y\nCONFIG_SND_SOC_SPDIF=y\nCONFIG_SOC_BUS=y\n# CONFIG_SOC_SAMA5D2 is not set\n# CONFIG_SOC_SAMA5D3 is not set\n# CONFIG_SOC_SAMA5D4 is not set\nCONFIG_SOC_SAMA7=y\nCONFIG_SOC_SAMA7G5=y\nCONFIG_SOC_SAM_V7=y\nCONFIG_SOUND=y\nCONFIG_SOUND_OSS_CORE=y\nCONFIG_SPARSE_IRQ=y\nCONFIG_SPI=y\n# CONFIG_SPI_AT91_USART is not set\nCONFIG_SPI_ATMEL=y\n# CONFIG_SPI_ATMEL_QUADSPI is not set\nCONFIG_SPI_MASTER=y\nCONFIG_SPI_MEM=y\nCONFIG_SRCU=y\nCONFIG_STACKTRACE=y\n# CONFIG_STANDALONE is not set\nCONFIG_SUNRPC=y\n# CONFIG_SWAP is not set\nCONFIG_SWPHY=y\n# CONFIG_SWP_EMULATE is not set\nCONFIG_SYSFS_DEPRECATED=y\nCONFIG_SYSFS_DEPRECATED_V2=y\nCONFIG_SYS_SUPPORTS_APM_EMULATION=y\nCONFIG_TICK_CPU_ACCOUNTING=y\nCONFIG_TIMER_OF=y\nCONFIG_TIMER_PROBE=y\nCONFIG_TINY_SRCU=y\nCONFIG_UACCESS_WITH_MEMCPY=y\nCONFIG_UNCOMPRESS_INCLUDE=\"debug/uncompress.h\"\nCONFIG_UNWINDER_ARM=y\nCONFIG_USE_OF=y\nCONFIG_V4L_PLATFORM_DRIVERS=y\nCONFIG_VFAT_FS=y\nCONFIG_VFP=y\nCONFIG_VFPv3=y\n# CONFIG_VIDEO_ATMEL_XISC is not set\nCONFIG_VIDEO_DEV=y\nCONFIG_VIDEO_V4L2=y\nCONFIG_VIDEO_V4L2_I2C=y\nCONFIG_VIDEO_V4L2_SUBDEV_API=y\nCONFIG_VT=y\nCONFIG_VT_CONSOLE=y\n# CONFIG_VT_HW_CONSOLE_BINDING is not set\nCONFIG_WATCHDOG_CORE=y\nCONFIG_ZBOOT_ROM_BSS=0x0\nCONFIG_ZBOOT_ROM_TEXT=0x0\nCONFIG_ZLIB_DEFLATE=y\nCONFIG_ZLIB_INFLATE=y\n"
  },
  {
    "path": "target/linux/at91/sama7/target.mk",
    "content": "BOARDNAME:=SAMA7 boards (Cortex-A7)\nCPU_TYPE:=cortex-a7\nCPU_SUBTYPE:=vfpv4\nFEATURES+=fpu\n\ndefine Target/Description\n\tBuild generic firmware for Microchip SAMA7G5 MPUs using the\n\tARMv7 instruction set.\nendef\n"
  },
  {
    "path": "target/linux/ath25/Makefile",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2006-2013 OpenWrt.org\n\ninclude $(TOPDIR)/rules.mk\n\nARCH:=mips\nBOARD:=ath25\nBOARDNAME:=Atheros AR231x/AR5312\nFEATURES:=squashfs low_mem small_flash\n\nKERNEL_PATCHVER:=5.10\nKERNEL_TESTING_PATCHVER:=5.10\n\ndefine Target/Description\n\tBuild firmware images for Atheros SoC boards\nendef\n\ninclude $(INCLUDE_DIR)/target.mk\n\nDEFAULT_PACKAGES += wpad-basic-wolfssl kmod-ath5k swconfig kmod-gpio-button-hotplug\n\n$(eval $(call BuildTarget))\n"
  },
  {
    "path": "target/linux/ath25/base-files/etc/board.d/01_leds",
    "content": "# Copyright 2012-2015 OpenWrt.org\n#\n\n. /lib/functions/uci-defaults.sh\n\nboard_config_update\n\nucidef_set_led_netdev \"wlan\" \"wlan\" \"wlan\" \"wlan0\"\n\nboard_config_flush\n\nexit 0\n"
  },
  {
    "path": "target/linux/ath25/base-files/etc/board.d/02_network",
    "content": "\n. /lib/functions/uci-defaults.sh\n\nboard_config_update\n\nif [ -e \"/sys/bus/mdio_bus/drivers/IC+ IP175C/0:00\" -o \\\n     -e \"/sys/bus/mdio_bus/drivers/IC+ IP17xx/0:00\" ] && \\\n   [ -x /sbin/swconfig ];\nthen\n\tucidef_add_switch \"eth0\" \\\n\t\t\"0:lan\" \"1:lan\" \"2:lan\" \"3:lan\" \"4:wan\" \"5@eth0\"\n\nelif [ -e \"/sys/bus/mdio_bus/drivers/Infineon ADM6996/0:00\" -o \\\n       -e \"/sys/bus/mdio_bus/drivers/Marvell 88E6060/0:10\" ];\nthen\n\tucidef_set_interfaces_lan_wan \"eth0.1\" \"eth0.2\"\n\nelif [ -d /sys/class/net/eth1 ]; then\n\tucidef_set_interfaces_lan_wan \"eth0\" \"eth1\"\n\nelse\n\tucidef_set_interface_lan \"eth0\"\nfi\n\nboard_config_flush\n\nexit 0\n"
  },
  {
    "path": "target/linux/ath25/base-files/lib/preinit/15_preinit_iface_atheros",
    "content": "preinit_ip() {\n\tif [ -z \"$pi_ifname\" ]; then\n\t\tgrep -q 'Atheros AR231[567]' /proc/cpuinfo && {\n\t\t\tif [ -e \"/sys/bus/mdio_bus/drivers/Infineon ADM6996/0:00\" -o \\\n\t\t\t     -e \"/sys/bus/mdio_bus/drivers/Marvell 88E6060/0:10\" ]; then\n\t\t\t\tip link set eth0 up\n\t\t\t\tip link add link eth0 name eth0.1 type vlan id 1\n\t\t\t\tifname=eth0.1\n\t\t\telse\n\t\t\t\tifname=eth0\n\t\t\tfi\n\t\t\tpi_ifname=$ifname\n\t\t}\n\tfi\n\t[ -n \"$pi_ifname\" ] && grep -q \"$pi_ifname\" /proc/net/dev && {\n\t\tip addr add $pi_ip/$pi_netmask broadcast $pi_broadcast dev $pi_ifname\n\t\tip link set $pi_ifname up\n\t}\n}\n\npreinit_ip_deconfig() {\n\tif [ -e \"/sys/bus/mdio_bus/drivers/Infineon ADM6996/0:00\" -o \\\n\t     -e \"/sys/bus/mdio_bus/drivers/Marvell 88E6060/0:10\" ]; then\n\t\tip link del eth0.1 2>/dev/null\n\t\tip link set $pi_ifname down\n\telif [ -n \"$pi_ifname\" ]; then\n\t\tip -4 addr flush dev $pi_ifname\n\tfi\n}\n"
  },
  {
    "path": "target/linux/ath25/base-files/lib/upgrade/platform.sh",
    "content": "CI_BLKSZ=65536\nCI_LDADR=0x80041000\n\nplatform_find_partitions() {\n\tlocal first dev size erasesize name\n\twhile read dev size erasesize name; do\n\t\tname=${name#'\"'}; name=${name%'\"'}\n\t\tcase \"$name\" in\n\t\t\tvmlinux.bin.l7|kernel|linux|rootfs)\n\t\t\t\tif [ -z \"$first\" ]; then\n\t\t\t\t\tfirst=\"$name\"\n\t\t\t\telse\n\t\t\t\t\techo \"$erasesize:$first:$name\"\n\t\t\t\t\tbreak\n\t\t\t\tfi\n\t\t\t;;\n\t\tesac\n\tdone < /proc/mtd\n}\n\nplatform_find_kernelpart() {\n\tlocal part\n\tfor part in \"${1%:*}\" \"${1#*:}\"; do\n\t\tcase \"$part\" in\n\t\t\tvmlinux.bin.l7|kernel|linux)\n\t\t\t\techo \"$part\"\n\t\t\t\tbreak\n\t\t\t;;\n\t\tesac\n\tdone\n}\n\nplatform_check_image() {\n\t[ \"$#\" -gt 1 ] && return 1\n\n\tcase \"$(get_magic_word \"$1\")\" in\n\t\t# Combined Image\n\t\t4349)\n\t\t\tlocal md5_img=$(dd if=\"$1\" bs=2 skip=9 count=16 2>/dev/null)\n\t\t\tlocal md5_chk=$(dd if=\"$1\" bs=$CI_BLKSZ skip=1 2>/dev/null | md5sum -); md5_chk=\"${md5_chk%% *}\"\n\n\t\t\tif [ -n \"$md5_img\" -a -n \"$md5_chk\" ] && [ \"$md5_img\" = \"$md5_chk\" ]; then\n\t\t\t\treturn 0\n\t\t\telse\n\t\t\t\techo \"Invalid image. Contents do not match checksum (image:$md5_img calculated:$md5_chk)\"\n\t\t\t\treturn 1\n\t\t\tfi\n\t\t;;\n\t\t*)\n\t\t\techo \"Invalid image. Use combined .img files on this platform\"\n\t\t\treturn 1\n\t\t;;\n\tesac\n}\n\nplatform_do_upgrade() {\n\tlocal partitions=$(platform_find_partitions)\n\tlocal kernelpart=$(platform_find_kernelpart \"${partitions#*:}\")\n\tlocal erase_size=$((0x${partitions%%:*})); partitions=\"${partitions#*:}\"\n\tlocal kern_length=0x$(dd if=\"$1\" bs=2 skip=1 count=4 2>/dev/null)\n\tlocal kern_blocks=$(($kern_length / $CI_BLKSZ))\n\tlocal root_blocks=$((0x$(dd if=\"$1\" bs=2 skip=5 count=4 2>/dev/null) / $CI_BLKSZ))\n\n\tif [ -n \"$partitions\" ] && [ -n \"$kernelpart\" ] && \\\n\t   [ ${kern_blocks:-0} -gt 0 ] && \\\n\t   [ ${root_blocks:-0} -gt ${kern_blocks:-0} ] && \\\n\t   [ ${erase_size:-0} -gt 0 ];\n\tthen\n\t\tlocal append=\"\"\n\t\t[ -f \"$UPGRADE_BACKUP\" ] && append=\"-j $UPGRADE_BACKUP\"\n\n\t\t( dd if=\"$1\" bs=$CI_BLKSZ skip=1 count=$kern_blocks 2>/dev/null; \\\n\t\t  dd if=\"$1\" bs=$CI_BLKSZ skip=$((1+$kern_blocks)) count=$root_blocks 2>/dev/null ) | \\\n\t\t\tmtd -r $append -F$kernelpart:$kern_length:$CI_LDADR,rootfs write - $partitions\n\tfi\n}\n"
  },
  {
    "path": "target/linux/ath25/config-5.10",
    "content": "CONFIG_ADM6996_PHY=y\nCONFIG_AR2315_WDT=y\nCONFIG_AR8216_PHY=y\nCONFIG_ARCH_32BIT_OFF_T=y\nCONFIG_ARCH_HIBERNATION_POSSIBLE=y\nCONFIG_ARCH_MMAP_RND_BITS_MAX=15\nCONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15\nCONFIG_ARCH_SUSPEND_POSSIBLE=y\nCONFIG_ATH25=y\nCONFIG_BLK_MQ_PCI=y\nCONFIG_CEVT_R4K=y\nCONFIG_CLONE_BACKWARDS=y\nCONFIG_CMDLINE=\"console=ttyS0,9600 rootfstype=squashfs,jffs2\"\nCONFIG_CMDLINE_BOOL=y\n# CONFIG_CMDLINE_OVERRIDE is not set\n# CONFIG_COMMON_CLK is not set\nCONFIG_COMPAT_32BIT_TIME=y\nCONFIG_CPU_BIG_ENDIAN=y\nCONFIG_CPU_GENERIC_DUMP_TLB=y\nCONFIG_CPU_HAS_PREFETCH=y\nCONFIG_CPU_HAS_SYNC=y\nCONFIG_CPU_MIPS32=y\nCONFIG_CPU_MIPS32_R1=y\nCONFIG_CPU_MIPSR1=y\nCONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y\nCONFIG_CPU_R4K_CACHE_TLB=y\nCONFIG_CPU_SUPPORTS_32BIT_KERNEL=y\nCONFIG_CPU_SUPPORTS_HIGHMEM=y\nCONFIG_CRYPTO_LIB_POLY1305_RSIZE=2\nCONFIG_CRYPTO_RNG2=y\nCONFIG_CSRC_R4K=y\nCONFIG_DMA_NONCOHERENT=y\nCONFIG_EARLY_PRINTK=y\nCONFIG_ETHERNET_PACKET_MANGLE=y\nCONFIG_FORCE_PCI=y\nCONFIG_FW_LOADER_PAGED_BUF=y\nCONFIG_GENERIC_ATOMIC64=y\nCONFIG_GENERIC_CLOCKEVENTS=y\nCONFIG_GENERIC_CMOS_UPDATE=y\nCONFIG_GENERIC_CPU_AUTOPROBE=y\nCONFIG_GENERIC_GETTIMEOFDAY=y\nCONFIG_GENERIC_IOMAP=y\nCONFIG_GENERIC_IRQ_CHIP=y\nCONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y\nCONFIG_GENERIC_IRQ_SHOW=y\nCONFIG_GENERIC_LIB_ASHLDI3=y\nCONFIG_GENERIC_LIB_ASHRDI3=y\nCONFIG_GENERIC_LIB_CMPDI2=y\nCONFIG_GENERIC_LIB_LSHRDI3=y\nCONFIG_GENERIC_LIB_UCMPDI2=y\nCONFIG_GENERIC_PCI_IOMAP=y\nCONFIG_GENERIC_SCHED_CLOCK=y\nCONFIG_GENERIC_SMP_IDLE_THREAD=y\nCONFIG_GENERIC_TIME_VSYSCALL=y\nCONFIG_GPIOLIB=y\nCONFIG_GPIO_AR2315=y\nCONFIG_GPIO_AR5312=y\nCONFIG_HANDLE_DOMAIN_IRQ=y\nCONFIG_HARDWARE_WATCHPOINTS=y\nCONFIG_HAS_DMA=y\nCONFIG_HAS_IOMEM=y\nCONFIG_HAS_IOPORT_MAP=y\nCONFIG_HW_RANDOM=y\nCONFIG_HZ_PERIODIC=y\nCONFIG_INITRAMFS_SOURCE=\"\"\nCONFIG_IP17XX_PHY=y\nCONFIG_IRQ_DOMAIN=y\nCONFIG_IRQ_FORCED_THREADING=y\nCONFIG_IRQ_MIPS_CPU=y\nCONFIG_IRQ_WORK=y\nCONFIG_LEDS_GPIO=y\nCONFIG_LOCK_DEBUGGING_SUPPORT=y\nCONFIG_MDIO_BUS=y\nCONFIG_MDIO_DEVICE=y\nCONFIG_MDIO_DEVRES=y\nCONFIG_MEMFD_CREATE=y\nCONFIG_MIGRATION=y\nCONFIG_MIPS=y\nCONFIG_MIPS_ASID_BITS=8\nCONFIG_MIPS_ASID_SHIFT=0\nCONFIG_MIPS_CLOCK_VSYSCALL=y\n# CONFIG_MIPS_CMDLINE_BUILTIN_EXTEND is not set\nCONFIG_MIPS_CMDLINE_FROM_BOOTLOADER=y\nCONFIG_MIPS_EBPF_JIT=y\nCONFIG_MIPS_L1_CACHE_SHIFT=5\nCONFIG_MIPS_LD_CAN_LINK_VDSO=y\nCONFIG_MODULES_USE_ELF_REL=y\nCONFIG_MTD_AR2315=y\nCONFIG_MTD_CFI_ADV_OPTIONS=y\n# CONFIG_MTD_CFI_GEOMETRY is not set\n# CONFIG_MTD_CFI_INTELEXT is not set\nCONFIG_MTD_MYLOADER_PARTS=y\nCONFIG_MTD_PHYSMAP=y\nCONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-3\nCONFIG_MTD_REDBOOT_PARTS=y\nCONFIG_MVSWITCH_PHY=y\nCONFIG_NEED_DMA_MAP_STATE=y\nCONFIG_NEED_PER_CPU_KM=y\nCONFIG_NET_AR231X=y\nCONFIG_NO_GENERIC_PCI_IOPORT_MAP=y\n# CONFIG_OF is not set\nCONFIG_PCI=y\nCONFIG_PCI_AR2315=y\nCONFIG_PCI_DISABLE_COMMON_QUIRKS=y\nCONFIG_PCI_DOMAINS=y\nCONFIG_PCI_DRIVERS_LEGACY=y\nCONFIG_PERF_USE_VMALLOC=y\nCONFIG_PGTABLE_LEVELS=2\nCONFIG_PHYLIB=y\nCONFIG_SERIAL_8250_NR_UARTS=1\nCONFIG_SERIAL_8250_RUNTIME_UARTS=1\nCONFIG_SERIAL_MCTRL_GPIO=y\nCONFIG_SOC_AR2315=y\nCONFIG_SOC_AR5312=y\nCONFIG_SRCU=y\n# CONFIG_SWAP is not set\nCONFIG_SWCONFIG=y\nCONFIG_SYSCTL_EXCEPTION_TRACE=y\nCONFIG_SYS_HAS_CPU_MIPS32_R1=y\nCONFIG_SYS_HAS_EARLY_PRINTK=y\nCONFIG_SYS_SUPPORTS_32BIT_KERNEL=y\nCONFIG_SYS_SUPPORTS_ARBIT_HZ=y\nCONFIG_SYS_SUPPORTS_BIG_ENDIAN=y\nCONFIG_TARGET_ISA_REV=1\nCONFIG_TICK_CPU_ACCOUNTING=y\nCONFIG_TINY_SRCU=y\nCONFIG_USB_SUPPORT=y\n"
  },
  {
    "path": "target/linux/ath25/files/drivers/net/phy/mvswitch.c",
    "content": "/*\n * Marvell 88E6060 switch driver\n * Copyright (c) 2008 Felix Fietkau <nbd@nbd.name>\n *\n * This program is free software; you can redistribute  it and/or modify it\n * under  the terms of the GNU General Public License v2 as published by the\n * Free Software Foundation\n */\n#include <linux/kernel.h>\n#include <linux/string.h>\n#include <linux/errno.h>\n#include <linux/unistd.h>\n#include <linux/slab.h>\n#include <linux/interrupt.h>\n#include <linux/init.h>\n#include <linux/delay.h>\n#include <linux/netdevice.h>\n#include <linux/etherdevice.h>\n#include <linux/skbuff.h>\n#include <linux/spinlock.h>\n#include <linux/mm.h>\n#include <linux/module.h>\n#include <linux/mii.h>\n#include <linux/ethtool.h>\n#include <linux/phy.h>\n#include <linux/if_vlan.h>\n#include <linux/version.h>\n\n#include <asm/io.h>\n#include <asm/irq.h>\n#include <asm/uaccess.h>\n#include \"mvswitch.h\"\n\n/* Undefine this to use trailer mode instead.\n * I don't know if header mode works with all chips */\n#define HEADER_MODE\t1\n\nMODULE_DESCRIPTION(\"Marvell 88E6060 Switch driver\");\nMODULE_AUTHOR(\"Felix Fietkau\");\nMODULE_LICENSE(\"GPL\");\n\n#define MVSWITCH_MAGIC 0x88E6060\n\nstruct mvswitch_priv {\n\tnetdev_features_t orig_features;\n\tu8 vlans[16];\n};\n\n#define to_mvsw(_phy) ((struct mvswitch_priv *) (_phy)->priv)\n\nstatic inline u16\nr16(struct phy_device *phydev, int addr, int reg)\n{\n\tstruct mii_bus *bus = phydev->mdio.bus;\n\n\treturn bus->read(bus, addr, reg);\n}\n\nstatic inline void\nw16(struct phy_device *phydev, int addr, int reg, u16 val)\n{\n\tstruct mii_bus *bus = phydev->mdio.bus;\n\n\tbus->write(bus, addr, reg, val);\n}\n\n\nstatic struct sk_buff *\nmvswitch_mangle_tx(struct net_device *dev, struct sk_buff *skb)\n{\n\tstruct mvswitch_priv *priv;\n\tchar *buf = NULL;\n\tu16 vid;\n\n\tpriv = dev->phy_ptr;\n\tif (unlikely(!priv))\n\t\tgoto error;\n\n\tif (unlikely(skb->len < 16))\n\t\tgoto error;\n\n#ifdef HEADER_MODE\n\tif (__vlan_hwaccel_get_tag(skb, &vid))\n\t\tgoto error;\n\n\tif (skb_cloned(skb) || (skb->len <= 62) || (skb_headroom(skb) < MV_HEADER_SIZE)) {\n\t\tif (pskb_expand_head(skb, MV_HEADER_SIZE, (skb->len < 62 ? 62 - skb->len : 0), GFP_ATOMIC))\n\t\t\tgoto error_expand;\n\t\tif (skb->len < 62)\n\t\t\tskb->len = 62;\n\t}\n\tbuf = skb_push(skb, MV_HEADER_SIZE);\n#else\n\tif (__vlan_get_tag(skb, &vid))\n\t\tgoto error;\n\n\tif (unlikely((vid > 15 || !priv->vlans[vid])))\n\t\tgoto error;\n\n\tif (skb->len <= 64) {\n\t\tif (pskb_expand_head(skb, 0, 64 + MV_TRAILER_SIZE - skb->len, GFP_ATOMIC))\n\t\t\tgoto error_expand;\n\n\t\tbuf = skb->data + 64;\n\t\tskb->len = 64 + MV_TRAILER_SIZE;\n\t} else {\n\t\tif (skb_cloned(skb) || unlikely(skb_tailroom(skb) < 4)) {\n\t\t\tif (pskb_expand_head(skb, 0, 4, GFP_ATOMIC))\n\t\t\t\tgoto error_expand;\n\t\t}\n\t\tbuf = skb_put(skb, 4);\n\t}\n\n\t/* move the ethernet header 4 bytes forward, overwriting the vlan tag */\n\tmemmove(skb->data + 4, skb->data, 12);\n\tskb->data += 4;\n\tskb->len -= 4;\n\tskb->mac_header += 4;\n#endif\n\n\tif (!buf)\n\t\tgoto error;\n\n\n#ifdef HEADER_MODE\n\t/* prepend the tag */\n\t*((__be16 *) buf) = cpu_to_be16(\n\t\t((vid << MV_HEADER_VLAN_S) & MV_HEADER_VLAN_M) |\n\t\t((priv->vlans[vid] << MV_HEADER_PORTS_S) & MV_HEADER_PORTS_M)\n\t);\n#else\n\t/* append the tag */\n\t*((__be32 *) buf) = cpu_to_be32((\n\t\t(MV_TRAILER_OVERRIDE << MV_TRAILER_FLAGS_S) |\n\t\t((priv->vlans[vid] & MV_TRAILER_PORTS_M) << MV_TRAILER_PORTS_S)\n\t));\n#endif\n\n\treturn skb;\n\nerror_expand:\n\tif (net_ratelimit())\n\t\tprintk(\"%s: failed to expand/update skb for the switch\\n\", dev->name);\n\nerror:\n\t/* any errors? drop the packet! */\n\tdev_kfree_skb_any(skb);\n\treturn NULL;\n}\n\nstatic void\nmvswitch_mangle_rx(struct net_device *dev, struct sk_buff *skb)\n{\n\tstruct mvswitch_priv *priv;\n\tunsigned char *buf;\n\tint vlan = -1;\n\tint i;\n\n\tpriv = dev->phy_ptr;\n\tif (WARN_ON_ONCE(!priv))\n\t\treturn;\n\n#ifdef HEADER_MODE\n\tbuf = skb->data;\n\tskb_pull(skb, MV_HEADER_SIZE);\n#else\n\tbuf = skb->data + skb->len - MV_TRAILER_SIZE;\n\tif (buf[0] != 0x80)\n\t\treturn;\n#endif\n\n\t/* look for the vlan matching the incoming port */\n\tfor (i = 0; i < ARRAY_SIZE(priv->vlans); i++) {\n\t\tif ((1 << buf[1]) & priv->vlans[i])\n\t\t\tvlan = i;\n\t}\n\n\tif (vlan == -1)\n\t\treturn;\n\n\t__vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan);\n}\n\n\nstatic int\nmvswitch_wait_mask(struct phy_device *pdev, int addr, int reg, u16 mask, u16 val)\n{\n\tint i = 100;\n\tu16 r;\n\n\tdo {\n\t\tr = r16(pdev, addr, reg) & mask;\n\t\tif (r == val)\n\t\t\treturn 0;\n\t} while(--i > 0);\n\treturn -ETIMEDOUT;\n}\n\nstatic int\nmvswitch_config_init(struct phy_device *pdev)\n{\n\tstruct mvswitch_priv *priv = to_mvsw(pdev);\n\tstruct net_device *dev = pdev->attached_dev;\n\tu8 vlmap = 0;\n\tint i;\n\n\tif (!dev)\n\t\treturn -EINVAL;\n\n\tprintk(\"%s: Marvell 88E6060 PHY driver attached.\\n\", dev->name);\n\tlinkmode_zero(pdev->supported);\n\tlinkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, pdev->supported);\n\tlinkmode_copy(pdev->advertising, pdev->supported);\n\tdev->phy_ptr = priv;\n\tpdev->irq = PHY_POLL;\n#ifdef HEADER_MODE\n\tdev->flags |= IFF_PROMISC;\n#endif\n\n\t/* initialize default vlans */\n\tfor (i = 0; i < MV_PORTS; i++)\n\t\tpriv->vlans[(i == MV_WANPORT ? 2 : 1)] |= (1 << i);\n\n\t/* before entering reset, disable all ports */\n\tfor (i = 0; i < MV_PORTS; i++)\n\t\tw16(pdev, MV_PORTREG(CONTROL, i), 0x00);\n\n\tmsleep(2); /* wait for the status change to settle in */\n\n\t/* put the ATU in reset */\n\tw16(pdev, MV_SWITCHREG(ATU_CTRL), MV_ATUCTL_RESET);\n\n\ti = mvswitch_wait_mask(pdev, MV_SWITCHREG(ATU_CTRL), MV_ATUCTL_RESET, 0);\n\tif (i < 0) {\n\t\tprintk(\"%s: Timeout waiting for the switch to reset.\\n\", dev->name);\n\t\treturn i;\n\t}\n\n\t/* set the ATU flags */\n\tw16(pdev, MV_SWITCHREG(ATU_CTRL),\n\t\tMV_ATUCTL_NO_LEARN |\n\t\tMV_ATUCTL_ATU_1K |\n\t\tMV_ATUCTL_AGETIME(MV_ATUCTL_AGETIME_MIN) /* minimum without disabling ageing */\n\t);\n\n\t/* initialize the cpu port */\n\tw16(pdev, MV_PORTREG(CONTROL, MV_CPUPORT),\n#ifdef HEADER_MODE\n\t\tMV_PORTCTRL_HEADER |\n#else\n\t\tMV_PORTCTRL_RXTR |\n\t\tMV_PORTCTRL_TXTR |\n#endif\n\t\tMV_PORTCTRL_ENABLED\n\t);\n\t/* wait for the phy change to settle in */\n\tmsleep(2);\n\tfor (i = 0; i < MV_PORTS; i++) {\n\t\tu8 pvid = 0;\n\t\tint j;\n\n\t\tvlmap = 0;\n\n\t\t/* look for the matching vlan */\n\t\tfor (j = 0; j < ARRAY_SIZE(priv->vlans); j++) {\n\t\t\tif (priv->vlans[j] & (1 << i)) {\n\t\t\t\tvlmap = priv->vlans[j];\n\t\t\t\tpvid = j;\n\t\t\t}\n\t\t}\n\t\t/* leave port unconfigured if it's not part of a vlan */\n\t\tif (!vlmap)\n\t\t\tcontinue;\n\n\t\t/* add the cpu port to the allowed destinations list */\n\t\tvlmap |= (1 << MV_CPUPORT);\n\n\t\t/* take port out of its own vlan destination map */\n\t\tvlmap &= ~(1 << i);\n\n\t\t/* apply vlan settings */\n\t\tw16(pdev, MV_PORTREG(VLANMAP, i),\n\t\t\tMV_PORTVLAN_PORTS(vlmap) |\n\t\t\tMV_PORTVLAN_ID(i)\n\t\t);\n\n\t\t/* re-enable port */\n\t\tw16(pdev, MV_PORTREG(CONTROL, i),\n\t\t\tMV_PORTCTRL_ENABLED\n\t\t);\n\t}\n\n\tw16(pdev, MV_PORTREG(VLANMAP, MV_CPUPORT),\n\t\tMV_PORTVLAN_ID(MV_CPUPORT)\n\t);\n\n\t/* set the port association vector */\n\tfor (i = 0; i <= MV_PORTS; i++) {\n\t\tw16(pdev, MV_PORTREG(ASSOC, i),\n\t\t\tMV_PORTASSOC_PORTS(1 << i)\n\t\t);\n\t}\n\n\t/* init switch control */\n\tw16(pdev, MV_SWITCHREG(CTRL),\n\t\tMV_SWITCHCTL_MSIZE |\n\t\tMV_SWITCHCTL_DROP\n\t);\n\n\tdev->eth_mangle_rx = mvswitch_mangle_rx;\n\tdev->eth_mangle_tx = mvswitch_mangle_tx;\n\tpriv->orig_features = dev->features;\n\n#ifdef HEADER_MODE\n#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,15,0)\n\tdev->extra_priv_flags |= IFF_NO_IP_ALIGN;\n#else\n\tdev->priv_flags |= IFF_NO_IP_ALIGN;\n#endif\n\tdev->features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX;\n#else\n\tdev->features |= NETIF_F_HW_VLAN_CTAG_RX;\n#endif\n\n\treturn 0;\n}\n\nstatic int\nmvswitch_read_status(struct phy_device *pdev)\n{\n\tpdev->speed = SPEED_100;\n\tpdev->duplex = DUPLEX_FULL;\n\tpdev->link = 1;\n\n\t/* XXX ugly workaround: we can't force the switch\n\t * to gracefully handle hosts moving from one port to another,\n\t * so we have to regularly clear the ATU database */\n\n\t/* wait for the ATU to become available */\n\tmvswitch_wait_mask(pdev, MV_SWITCHREG(ATU_OP), MV_ATUOP_INPROGRESS, 0);\n\n\t/* flush the ATU */\n\tw16(pdev, MV_SWITCHREG(ATU_OP),\n\t\tMV_ATUOP_INPROGRESS |\n\t\tMV_ATUOP_FLUSH_ALL\n\t);\n\n\t/* wait for operation to complete */\n\tmvswitch_wait_mask(pdev, MV_SWITCHREG(ATU_OP), MV_ATUOP_INPROGRESS, 0);\n\n\treturn 0;\n}\n\nstatic int\nmvswitch_aneg_done(struct phy_device *phydev)\n{\n\treturn 1;\t/* Return any positive value */\n}\n\nstatic int\nmvswitch_config_aneg(struct phy_device *phydev)\n{\n\treturn 0;\n}\n\nstatic void\nmvswitch_detach(struct phy_device *pdev)\n{\n\tstruct mvswitch_priv *priv = to_mvsw(pdev);\n\tstruct net_device *dev = pdev->attached_dev;\n\n\tif (!dev)\n\t\treturn;\n\n\tdev->phy_ptr = NULL;\n\tdev->eth_mangle_rx = NULL;\n\tdev->eth_mangle_tx = NULL;\n\tdev->features = priv->orig_features;\n#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,15,0)\n\tdev->extra_priv_flags &= ~IFF_NO_IP_ALIGN;\n#else\n\tdev->priv_flags &= ~IFF_NO_IP_ALIGN;\n#endif\n}\n\nstatic void\nmvswitch_remove(struct phy_device *pdev)\n{\n\tstruct mvswitch_priv *priv = to_mvsw(pdev);\n\n\tkfree(priv);\n}\n\nstatic int\nmvswitch_probe(struct phy_device *pdev)\n{\n\tstruct mvswitch_priv *priv;\n\n\tpriv = kzalloc(sizeof(struct mvswitch_priv), GFP_KERNEL);\n\tif (priv == NULL)\n\t\treturn -ENOMEM;\n\n\tpdev->priv = priv;\n\n\treturn 0;\n}\n\nstatic int\nmvswitch_fixup(struct phy_device *dev)\n{\n\tstruct mii_bus *bus = dev->mdio.bus;\n\tu16 reg;\n\n\tif (dev->mdio.addr != 0x10)\n\t\treturn 0;\n\n\treg = bus->read(bus, MV_PORTREG(IDENT, 0)) & MV_IDENT_MASK;\n\tif (reg != MV_IDENT_VALUE)\n\t\treturn 0;\n\n\tdev->phy_id = MVSWITCH_MAGIC;\n\treturn 0;\n}\n\n\nstatic struct phy_driver mvswitch_driver = {\n\t.name\t\t= \"Marvell 88E6060\",\n\t.phy_id\t\t= MVSWITCH_MAGIC,\n\t.phy_id_mask\t= 0xffffffff,\n\t.features\t= PHY_BASIC_FEATURES,\n\t.probe\t\t= &mvswitch_probe,\n\t.remove\t\t= &mvswitch_remove,\n\t.detach\t\t= &mvswitch_detach,\n\t.config_init\t= &mvswitch_config_init,\n\t.config_aneg\t= &mvswitch_config_aneg,\n\t.aneg_done\t= &mvswitch_aneg_done,\n\t.read_status\t= &mvswitch_read_status,\n};\n\nstatic int __init\nmvswitch_init(void)\n{\n\tphy_register_fixup_for_id(PHY_ANY_ID, mvswitch_fixup);\n\treturn phy_driver_register(&mvswitch_driver, THIS_MODULE);\n}\n\nstatic void __exit\nmvswitch_exit(void)\n{\n\tphy_driver_unregister(&mvswitch_driver);\n}\n\nmodule_init(mvswitch_init);\nmodule_exit(mvswitch_exit);\n"
  },
  {
    "path": "target/linux/ath25/files/drivers/net/phy/mvswitch.h",
    "content": "/*\n * Marvell 88E6060 switch driver\n * Copyright (c) 2008 Felix Fietkau <nbd@nbd.name>\n *\n * This program is free software; you can redistribute  it and/or modify it\n * under  the terms of the GNU General Public License v2 as published by the\n * Free Software Foundation\n */\n#ifndef __MVSWITCH_H\n#define __MVSWITCH_H\n\n#define MV_HEADER_SIZE\t2\n#define MV_HEADER_PORTS_M\t0x001f\n#define MV_HEADER_PORTS_S\t0\n#define MV_HEADER_VLAN_M\t0xf000\n#define MV_HEADER_VLAN_S\t12\n\n#define MV_TRAILER_SIZE\t4\n#define MV_TRAILER_PORTS_M\t0x1f\n#define MV_TRAILER_PORTS_S\t16\n#define MV_TRAILER_FLAGS_S\t24\n#define MV_TRAILER_OVERRIDE\t0x80\n\n\n#define MV_PORTS\t5\n#define MV_WANPORT\t4\n#define MV_CPUPORT\t5\n\n#define MV_BASE\t\t0x10\n\n#define MV_PHYPORT_BASE\t\t(MV_BASE + 0x0)\n#define MV_PHYPORT(_n)\t\t(MV_PHYPORT_BASE + (_n))\n#define MV_SWITCHPORT_BASE\t(MV_BASE + 0x8)\n#define MV_SWITCHPORT(_n)\t(MV_SWITCHPORT_BASE + (_n))\n#define MV_SWITCHREGS\t\t(MV_BASE + 0xf)\n\nenum {\n\tMV_PHY_CONTROL      = 0x00,\n\tMV_PHY_STATUS       = 0x01,\n\tMV_PHY_IDENT0       = 0x02,\n\tMV_PHY_IDENT1       = 0x03,\n\tMV_PHY_ANEG         = 0x04,\n\tMV_PHY_LINK_ABILITY = 0x05,\n\tMV_PHY_ANEG_EXPAND  = 0x06,\n\tMV_PHY_XMIT_NEXTP   = 0x07,\n\tMV_PHY_LINK_NEXTP   = 0x08,\n\tMV_PHY_CONTROL1     = 0x10,\n\tMV_PHY_STATUS1      = 0x11,\n\tMV_PHY_INTR_EN      = 0x12,\n\tMV_PHY_INTR_STATUS  = 0x13,\n\tMV_PHY_INTR_PORT    = 0x14,\n\tMV_PHY_RECV_COUNTER = 0x16,\n\tMV_PHY_LED_PARALLEL = 0x16,\n\tMV_PHY_LED_STREAM   = 0x17,\n\tMV_PHY_LED_CTRL     = 0x18,\n\tMV_PHY_LED_OVERRIDE = 0x19,\n\tMV_PHY_VCT_CTRL     = 0x1a,\n\tMV_PHY_VCT_STATUS   = 0x1b,\n\tMV_PHY_CONTROL2     = 0x1e\n};\n#define MV_PHYREG(_type, _port) MV_PHYPORT(_port), MV_PHY_##_type\n\nenum {\n\tMV_PORT_STATUS      = 0x00,\n\tMV_PORT_IDENT       = 0x03,\n\tMV_PORT_CONTROL     = 0x04,\n\tMV_PORT_VLANMAP     = 0x06,\n\tMV_PORT_ASSOC       = 0x0b,\n\tMV_PORT_RXCOUNT     = 0x10,\n\tMV_PORT_TXCOUNT     = 0x11,\n};\n#define MV_PORTREG(_type, _port) MV_SWITCHPORT(_port), MV_PORT_##_type\n\nenum {\n\tMV_PORTCTRL_BLOCK   =  (1 << 0),\n\tMV_PORTCTRL_LEARN   =  (2 << 0),\n\tMV_PORTCTRL_ENABLED =  (3 << 0),\n\tMV_PORTCTRL_VLANTUN =  (1 << 7),\t/* Enforce VLANs on packets */\n\tMV_PORTCTRL_RXTR    =  (1 << 8),\t/* Enable Marvell packet trailer for ingress */\n\tMV_PORTCTRL_HEADER\t= (1 << 11),\t/* Enable Marvell packet header mode for port */\n\tMV_PORTCTRL_TXTR    = (1 << 14),\t/* Enable Marvell packet trailer for egress */\n\tMV_PORTCTRL_FORCEFL = (1 << 15),\t/* force flow control */\n};\n\n#define MV_PORTVLAN_ID(_n) (((_n) & 0xf) << 12)\n#define MV_PORTVLAN_PORTS(_n) ((_n) & 0x3f)\n\n#define MV_PORTASSOC_PORTS(_n) ((_n) & 0x1f)\n#define MV_PORTASSOC_MONITOR\t(1 << 15)\n\nenum {\n\tMV_SWITCH_MAC0      = 0x01,\n\tMV_SWITCH_MAC1      = 0x02,\n\tMV_SWITCH_MAC2      = 0x03,\n\tMV_SWITCH_CTRL      = 0x04,\n\tMV_SWITCH_ATU_CTRL  = 0x0a,\n\tMV_SWITCH_ATU_OP    = 0x0b,\n\tMV_SWITCH_ATU_DATA  = 0x0c,\n\tMV_SWITCH_ATU_MAC0  = 0x0d,\n\tMV_SWITCH_ATU_MAC1  = 0x0e,\n\tMV_SWITCH_ATU_MAC2  = 0x0f,\n};\n#define MV_SWITCHREG(_type) MV_SWITCHREGS, MV_SWITCH_##_type\n\nenum {\n\tMV_SWITCHCTL_EEIE   =  (1 << 0),\t/* EEPROM interrupt enable */\n\tMV_SWITCHCTL_PHYIE  =  (1 << 1),\t/* PHY interrupt enable */\n\tMV_SWITCHCTL_ATUDONE=  (1 << 2),\t/* ATU done interrupt enable */\n\tMV_SWITCHCTL_ATUIE  =  (1 << 3),\t/* ATU interrupt enable */\n\tMV_SWITCHCTL_CTRMODE=  (1 << 8),\t/* statistics for rx and tx errors */\n\tMV_SWITCHCTL_RELOAD =  (1 << 9),\t/* reload registers from eeprom */\n\tMV_SWITCHCTL_MSIZE  = (1 << 10),\t/* increase maximum frame size */\n\tMV_SWITCHCTL_DROP   = (1 << 13),\t/* discard frames with excessive collisions */\n};\n\nenum {\n#define MV_ATUCTL_AGETIME_MIN\t16\n#define MV_ATUCTL_AGETIME_MAX\t4080\n#define MV_ATUCTL_AGETIME(_n)\t((((_n) / 16) & 0xff) << 4)\n\tMV_ATUCTL_ATU_256   = (0 << 12),\n\tMV_ATUCTL_ATU_512   = (1 << 12),\n\tMV_ATUCTL_ATU_1K\t= (2 << 12),\n\tMV_ATUCTL_ATUMASK   = (3 << 12),\n\tMV_ATUCTL_NO_LEARN  = (1 << 14),\n\tMV_ATUCTL_RESET     = (1 << 15),\n};\n\nenum {\n#define MV_ATUOP_DBNUM(_n)\t((_n) & 0x0f)\n\n\tMV_ATUOP_NOOP       = (0 << 12),\n\tMV_ATUOP_FLUSH_ALL  = (1 << 12),\n\tMV_ATUOP_FLUSH_U    = (2 << 12),\n\tMV_ATUOP_LOAD_DB    = (3 << 12),\n\tMV_ATUOP_GET_NEXT   = (4 << 12),\n\tMV_ATUOP_FLUSH_DB   = (5 << 12),\n\tMV_ATUOP_FLUSH_DB_UU= (6 << 12),\n\n\tMV_ATUOP_INPROGRESS = (1 << 15),\n};\n\n#define MV_IDENT_MASK\t\t0xfff0\n#define MV_IDENT_VALUE\t\t0x0600\n\n#endif\n"
  },
  {
    "path": "target/linux/ath25/image/Makefile",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2006-2010 OpenWrt.org\n\ninclude $(TOPDIR)/rules.mk\ninclude $(INCLUDE_DIR)/image.mk\n\ndefine Build/mkfwimage\n\t$(STAGING_DIR_HOST)/bin/mkfwimage \\\n\t\t-B $(1).$(VERSION_DIST).$(REVISION) \\\n\t\t-k $(IMAGE_KERNEL) \\\n\t\t-r $(IMAGE_ROOTFS) \\\n\t\t-o $@.new && \\\n\tmv $@.new $@\nendef\n\ndefine Build/combined-image\n\t-sh $(TOPDIR)/scripts/combined-image.sh \\\n\t\t\"$(IMAGE_KERNEL)\" \\\n\t\t\"$(IMAGE_ROOTFS)\" \\\n\t\t\"$@.new\" && \\\n\tmv $@.new $@\nendef\n\ndefine Build/mkmylofw\n\t$(STAGING_DIR_HOST)/bin/mkmylofw -B $(1) \\\n\t\t-p0x020000:0x130000:ah:0x80041000:linux:$(IMAGE_KERNEL) \\\n\t\t-p0x150000:0x2a0000:::rootfs:$(IMAGE_ROOTFS) \\\n\t\t$@.new && \\\n\tmv $@.new $@\nendef\n\ndefine Build/gzip-kernel\n\tgzip -9n -c $@ > $@.gz\n\tdd if=$@.gz of=$@ bs=65536 conv=sync\nendef\n\ndefine Build/lzma-kernel\n\t$(STAGING_DIR_HOST)/bin/lzma e $@ $@.l7\n\tdd if=$@.l7 of=$@ bs=65536 conv=sync\nendef\n\ndefine Build/copy-kernel\n\trm -f $@ $@.elf\n\tcp $< $@\n\tcp $< $@.elf\nendef\n\ndefine Build/elf-kernel\n\tcp $(IMAGE_KERNEL).elf $@\nendef\n\n\ndefine Device/Default\n  PROFILES = Default $$(DEVICE_NAME)\n  KERNEL := copy-kernel | lzma-kernel\n  IMAGES := sysupgrade.bin\n  FILESYSTEMS := squashfs\nendef\n\ndefine Device/generic\n  DEVICE_VENDOR := Atheros\n  DEVICE_MODEL := Generic AR2xxx board\n  IMAGES := kernel.lzma kernel.elf kernel.gz rootfs.bin sysupgrade.bin\n  IMAGE/kernel.gz := elf-kernel | gzip-kernel\n  IMAGE/kernel.elf := elf-kernel\n  IMAGE/kernel.lzma := elf-kernel | lzma-kernel\n  IMAGE/rootfs.bin := append-rootfs | pad-rootfs | pad-to 128k\n  IMAGE/sysupgrade.bin := append-rootfs | pad-rootfs | pad-to 128k | combined-image\n  DEVICE_IMG_NAME = $$(DEVICE_IMG_PREFIX)-$$(if $$(findstring kernel,$$(2)),,$$(1)-)$$(2)\nendef\nTARGET_DEVICES += generic\n\ndefine Device/ubnt_picostation-2\n  DEVICE_VENDOR := Ubiquiti\n  DEVICE_MODEL := Picostation 2 (XS2-8)\n  IMAGE/sysupgrade.bin := append-rootfs | pad-rootfs | pad-to 128k | mkfwimage XS2-8 -v XS2.ar2316\nendef\nTARGET_DEVICES += ubnt_picostation-2\n\ndefine Device/ubnt_nanostation-2\n  DEVICE_VENDOR := Ubiquiti\n  DEVICE_MODEL := Nanostation 2 (XS2)\n  IMAGE/sysupgrade.bin := append-rootfs | pad-rootfs | pad-to 128k | mkfwimage XS2 -v XS2.ar2316\n  DEFAULT := n\nendef\nTARGET_DEVICES += ubnt_nanostation-2\n\ndefine Device/ubnt_nanostation-5\n  DEVICE_VENDOR := Ubiquiti\n  DEVICE_MODEL := Nanostation 5 (XS5)\n  IMAGE/sysupgrade.bin := append-rootfs | pad-rootfs | pad-to 128k | mkfwimage XS5 -v XS5.ar2313\n  DEFAULT := n\nendef\nTARGET_DEVICES += ubnt_nanostation-5\n\ndefine Device/compex_np25g\n  DEVICE_VENDOR := Compex\n  DEVICE_MODEL := NP25G\n  KERNEL := kernel-bin | gzip-kernel\n  IMAGE/sysupgrade.bin := append-rootfs | pad-rootfs | pad-to 128k | mkmylofw np25g\n  BROKEN := y\nendef\nTARGET_DEVICES += compex_np25g\n\ndefine Device/compex_wpe53g\n  DEVICE_VENDOR := Compex\n  DEVICE_MODEL := WPE53G\n  KERNEL := kernel-bin | gzip-kernel\n  IMAGE/sysupgrade.bin := append-rootfs | pad-rootfs | pad-to 128k | mkmylofw wpe53g\n  BROKEN := y\nendef\nTARGET_DEVICES += compex_wpe53g\n\n$(eval $(call BuildImage))\n"
  },
  {
    "path": "target/linux/ath25/patches-5.10/107-ar5312_gpio.patch",
    "content": "--- a/arch/mips/ath25/Kconfig\n+++ b/arch/mips/ath25/Kconfig\n@@ -2,6 +2,7 @@\n config SOC_AR5312\n \tbool \"Atheros AR5312/AR2312+ SoC support\"\n \tdepends on ATH25\n+\tselect GPIO_AR5312\n \tdefault y\n \n config SOC_AR2315\n--- a/arch/mips/ath25/ar5312.c\n+++ b/arch/mips/ath25/ar5312.c\n@@ -23,6 +23,7 @@\n #include <linux/platform_device.h>\n #include <linux/mtd/physmap.h>\n #include <linux/reboot.h>\n+#include <linux/gpio.h>\n #include <asm/bootinfo.h>\n #include <asm/reboot.h>\n #include <asm/time.h>\n@@ -178,6 +179,22 @@ static struct platform_device ar5312_phy\n \t.num_resources = 1,\n };\n \n+static struct resource ar5312_gpio_res[] = {\n+\t{\n+\t\t.name = \"ar5312-gpio\",\n+\t\t.flags = IORESOURCE_MEM,\n+\t\t.start = AR5312_GPIO_BASE,\n+\t\t.end = AR5312_GPIO_BASE + AR5312_GPIO_SIZE - 1,\n+\t},\n+};\n+\n+static struct platform_device ar5312_gpio = {\n+\t.name = \"ar5312-gpio\",\n+\t.id = -1,\n+\t.resource = ar5312_gpio_res,\n+\t.num_resources = ARRAY_SIZE(ar5312_gpio_res),\n+};\n+\n static void __init ar5312_flash_init(void)\n {\n \tvoid __iomem *flashctl_base;\n@@ -245,6 +262,8 @@ void __init ar5312_init_devices(void)\n \n \tplatform_device_register(&ar5312_physmap_flash);\n \n+\tplatform_device_register(&ar5312_gpio);\n+\n \tswitch (ath25_soc) {\n \tcase ATH25_SOC_AR5312:\n \t\tif (!ath25_board.radio)\n--- a/drivers/gpio/Kconfig\n+++ b/drivers/gpio/Kconfig\n@@ -142,6 +142,13 @@ config GPIO_AMDPT\n \t  driver for GPIO functionality on Promontory IOHub\n \t  Require ACPI ASL code to enumerate as a platform device.\n \n+config GPIO_AR5312\n+\tbool \"AR5312 SoC GPIO support\"\n+\tdefault y if SOC_AR5312\n+\tdepends on SOC_AR5312\n+\thelp\n+\t  Say yes here to enable GPIO support for Atheros AR5312/AR2312+ SoCs.\n+\n config GPIO_ASPEED\n \ttristate \"Aspeed GPIO support\"\n \tdepends on (ARCH_ASPEED || COMPILE_TEST) && OF_GPIO\n--- a/drivers/gpio/Makefile\n+++ b/drivers/gpio/Makefile\n@@ -32,6 +32,7 @@ obj-$(CONFIG_GPIO_ALTERA)  \t\t+= gpio-alt\n obj-$(CONFIG_GPIO_AMD8111)\t\t+= gpio-amd8111.o\n obj-$(CONFIG_GPIO_AMD_FCH)\t\t+= gpio-amd-fch.o\n obj-$(CONFIG_GPIO_AMDPT)\t\t+= gpio-amdpt.o\n+obj-$(CONFIG_GPIO_AR5312)\t\t+= gpio-ar5312.o\n obj-$(CONFIG_GPIO_ARIZONA)\t\t+= gpio-arizona.o\n obj-$(CONFIG_GPIO_ASPEED)\t\t+= gpio-aspeed.o\n obj-$(CONFIG_GPIO_ASPEED_SGPIO)\t\t+= gpio-aspeed-sgpio.o\n--- /dev/null\n+++ b/drivers/gpio/gpio-ar5312.c\n@@ -0,0 +1,121 @@\n+/*\n+ * This file is subject to the terms and conditions of the GNU General Public\n+ * License.  See the file \"COPYING\" in the main directory of this archive\n+ * for more details.\n+ *\n+ * Copyright (C) 2003 Atheros Communications, Inc.,  All Rights Reserved.\n+ * Copyright (C) 2006 FON Technology, SL.\n+ * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>\n+ * Copyright (C) 2006-2009 Felix Fietkau <nbd@nbd.name>\n+ * Copyright (C) 2012 Alexandros C. Couloumbis <alex@ozo.com>\n+ */\n+\n+#include <linux/kernel.h>\n+#include <linux/init.h>\n+#include <linux/platform_device.h>\n+#include <linux/gpio.h>\n+\n+#define DRIVER_NAME\t\"ar5312-gpio\"\n+\n+#define AR5312_GPIO_DO\t\t0x00\t\t/* output register */\n+#define AR5312_GPIO_DI\t\t0x04\t\t/* intput register */\n+#define AR5312_GPIO_CR\t\t0x08\t\t/* control register */\n+\n+#define AR5312_GPIO_CR_M(x)\t(1 << (x))\t/* mask for i/o */\n+#define AR5312_GPIO_CR_O(x)\t(0 << (x))\t/* mask for output */\n+#define AR5312_GPIO_CR_I(x)\t(1 << (x))\t/* mask for input */\n+#define AR5312_GPIO_CR_INT(x)\t(1 << ((x)+8))\t/* mask for interrupt */\n+#define AR5312_GPIO_CR_UART(x)\t(1 << ((x)+16))\t/* uart multiplex */\n+\n+#define AR5312_GPIO_NUM\t\t8\n+\n+static void __iomem *ar5312_mem;\n+\n+static inline u32 ar5312_gpio_reg_read(unsigned reg)\n+{\n+\treturn __raw_readl(ar5312_mem + reg);\n+}\n+\n+static inline void ar5312_gpio_reg_write(unsigned reg, u32 val)\n+{\n+\t__raw_writel(val, ar5312_mem + reg);\n+}\n+\n+static inline void ar5312_gpio_reg_mask(unsigned reg, u32 mask, u32 val)\n+{\n+\tar5312_gpio_reg_write(reg, (ar5312_gpio_reg_read(reg) & ~mask) | val);\n+}\n+\n+static int ar5312_gpio_get_val(struct gpio_chip *chip, unsigned gpio)\n+{\n+\treturn (ar5312_gpio_reg_read(AR5312_GPIO_DI) >> gpio) & 1;\n+}\n+\n+static void ar5312_gpio_set_val(struct gpio_chip *chip, unsigned gpio, int val)\n+{\n+\tu32 reg = ar5312_gpio_reg_read(AR5312_GPIO_DO);\n+\n+\treg = val ? reg | (1 << gpio) : reg & ~(1 << gpio);\n+\tar5312_gpio_reg_write(AR5312_GPIO_DO, reg);\n+}\n+\n+static int ar5312_gpio_dir_in(struct gpio_chip *chip, unsigned gpio)\n+{\n+\tar5312_gpio_reg_mask(AR5312_GPIO_CR, 0, 1 << gpio);\n+\treturn 0;\n+}\n+\n+static int ar5312_gpio_dir_out(struct gpio_chip *chip, unsigned gpio, int val)\n+{\n+\tar5312_gpio_reg_mask(AR5312_GPIO_CR, 1 << gpio, 0);\n+\tar5312_gpio_set_val(chip, gpio, val);\n+\treturn 0;\n+}\n+\n+static struct gpio_chip ar5312_gpio_chip = {\n+\t.label\t\t\t= DRIVER_NAME,\n+\t.direction_input\t= ar5312_gpio_dir_in,\n+\t.direction_output\t= ar5312_gpio_dir_out,\n+\t.set\t\t\t= ar5312_gpio_set_val,\n+\t.get\t\t\t= ar5312_gpio_get_val,\n+\t.base\t\t\t= 0,\n+\t.ngpio\t\t\t= AR5312_GPIO_NUM,\n+};\n+\n+static int ar5312_gpio_probe(struct platform_device *pdev)\n+{\n+\tstruct device *dev = &pdev->dev;\n+\tstruct resource *res;\n+\tint ret;\n+\n+\tif (ar5312_mem)\n+\t\treturn -EBUSY;\n+\n+\tres = platform_get_resource(pdev, IORESOURCE_MEM, 0);\n+\tar5312_mem = devm_ioremap_resource(dev, res);\n+\tif (IS_ERR(ar5312_mem))\n+\t\treturn PTR_ERR(ar5312_mem);\n+\n+\tar5312_gpio_chip.parent = dev;\n+\tret = gpiochip_add(&ar5312_gpio_chip);\n+\tif (ret) {\n+\t\tdev_err(dev, \"failed to add gpiochip\\n\");\n+\t\treturn ret;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static struct platform_driver ar5312_gpio_driver = {\n+\t.probe = ar5312_gpio_probe,\n+\t.driver = {\n+\t\t.name = DRIVER_NAME,\n+\t\t.owner = THIS_MODULE,\n+\t}\n+};\n+\n+static int __init ar5312_gpio_init(void)\n+{\n+\treturn platform_driver_register(&ar5312_gpio_driver);\n+}\n+subsys_initcall(ar5312_gpio_init);\n--- a/arch/mips/Kconfig\n+++ b/arch/mips/Kconfig\n@@ -219,6 +219,7 @@ config ATH25\n \tselect CEVT_R4K\n \tselect CSRC_R4K\n \tselect DMA_NONCOHERENT\n+\tselect GPIOLIB\n \tselect IRQ_MIPS_CPU\n \tselect IRQ_DOMAIN\n \tselect SYS_HAS_CPU_MIPS32_R1\n"
  },
  {
    "path": "target/linux/ath25/patches-5.10/108-ar2315_gpio.patch",
    "content": "--- a/arch/mips/ath25/Kconfig\n+++ b/arch/mips/ath25/Kconfig\n@@ -8,6 +8,7 @@ config SOC_AR5312\n config SOC_AR2315\n \tbool \"Atheros AR2315+ SoC support\"\n \tdepends on ATH25\n+\tselect GPIO_AR2315\n \tdefault y\n \n config PCI_AR2315\n--- a/arch/mips/ath25/ar2315.c\n+++ b/arch/mips/ath25/ar2315.c\n@@ -22,6 +22,8 @@\n #include <linux/memblock.h>\n #include <linux/platform_device.h>\n #include <linux/reboot.h>\n+#include <linux/delay.h>\n+#include <linux/gpio.h>\n #include <asm/bootinfo.h>\n #include <asm/reboot.h>\n #include <asm/time.h>\n@@ -165,11 +167,42 @@ void __init ar2315_arch_init_irq(void)\n \tar2315_misc_irq_domain = domain;\n }\n \n+static struct resource ar2315_gpio_res[] = {\n+\t{\n+\t\t.name = \"ar2315-gpio\",\n+\t\t.flags = IORESOURCE_MEM,\n+\t\t.start = AR2315_RST_BASE + AR2315_GPIO,\n+\t\t.end = AR2315_RST_BASE + AR2315_GPIO + 0x10 - 1,\n+\t},\n+\t{\n+\t\t.name = \"ar2315-gpio\",\n+\t\t.flags = IORESOURCE_IRQ,\n+\t},\n+\t{\n+\t\t.name = \"ar2315-gpio-irq-base\",\n+\t\t.flags = IORESOURCE_IRQ,\n+\t\t.start = AR231X_GPIO_IRQ_BASE,\n+\t\t.end = AR231X_GPIO_IRQ_BASE,\n+\t}\n+};\n+\n+static struct platform_device ar2315_gpio = {\n+\t.id = -1,\n+\t.name = \"ar2315-gpio\",\n+\t.resource = ar2315_gpio_res,\n+\t.num_resources = ARRAY_SIZE(ar2315_gpio_res)\n+};\n+\n void __init ar2315_init_devices(void)\n {\n \t/* Find board configuration */\n \tath25_find_config(AR2315_SPI_READ_BASE, AR2315_SPI_READ_SIZE);\n \n+\tar2315_gpio_res[1].start = irq_create_mapping(ar2315_misc_irq_domain,\n+\t\t\t\t\t\t      AR2315_MISC_IRQ_GPIO);\n+\tar2315_gpio_res[1].end = ar2315_gpio_res[1].start;\n+\tplatform_device_register(&ar2315_gpio);\n+\n \tath25_add_wmac(0, AR2315_WLAN0_BASE, AR2315_IRQ_WLAN0);\n }\n \n@@ -185,8 +218,8 @@ static void ar2315_restart(char *command\n \t/* Cold reset does not work on the AR2315/6, use the GPIO reset bits\n \t * a workaround. Give it some time to attempt a gpio based hardware\n \t * reset (atheros reference design workaround) */\n-\n-\t/* TODO: implement the GPIO reset workaround */\n+\tgpio_request_one(AR2315_RESET_GPIO, GPIOF_OUT_INIT_LOW, \"Reset\");\n+\tmdelay(100);\n \n \t/* Some boards (e.g. Senao EOC-2610) don't implement the reset logic\n \t * workaround. Attempt to jump to the mips reset location -\n--- a/drivers/gpio/Kconfig\n+++ b/drivers/gpio/Kconfig\n@@ -142,6 +142,13 @@ config GPIO_AMDPT\n \t  driver for GPIO functionality on Promontory IOHub\n \t  Require ACPI ASL code to enumerate as a platform device.\n \n+config GPIO_AR2315\n+\tbool \"AR2315 SoC GPIO support\"\n+\tdefault y if SOC_AR2315\n+\tdepends on SOC_AR2315\n+\thelp\n+\t  Say yes here to enable GPIO support for Atheros AR2315+ SoCs.\n+\n config GPIO_AR5312\n \tbool \"AR5312 SoC GPIO support\"\n \tdefault y if SOC_AR5312\n--- a/drivers/gpio/Makefile\n+++ b/drivers/gpio/Makefile\n@@ -32,6 +32,7 @@ obj-$(CONFIG_GPIO_ALTERA)  \t\t+= gpio-alt\n obj-$(CONFIG_GPIO_AMD8111)\t\t+= gpio-amd8111.o\n obj-$(CONFIG_GPIO_AMD_FCH)\t\t+= gpio-amd-fch.o\n obj-$(CONFIG_GPIO_AMDPT)\t\t+= gpio-amdpt.o\n+obj-$(CONFIG_GPIO_AR2315)\t\t+= gpio-ar2315.o\n obj-$(CONFIG_GPIO_AR5312)\t\t+= gpio-ar5312.o\n obj-$(CONFIG_GPIO_ARIZONA)\t\t+= gpio-arizona.o\n obj-$(CONFIG_GPIO_ASPEED)\t\t+= gpio-aspeed.o\n--- /dev/null\n+++ b/drivers/gpio/gpio-ar2315.c\n@@ -0,0 +1,233 @@\n+/*\n+ * This file is subject to the terms and conditions of the GNU General Public\n+ * License.  See the file \"COPYING\" in the main directory of this archive\n+ * for more details.\n+ *\n+ * Copyright (C) 2003 Atheros Communications, Inc.,  All Rights Reserved.\n+ * Copyright (C) 2006 FON Technology, SL.\n+ * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>\n+ * Copyright (C) 2006 Felix Fietkau <nbd@nbd.name>\n+ * Copyright (C) 2012 Alexandros C. Couloumbis <alex@ozo.com>\n+ */\n+\n+#include <linux/kernel.h>\n+#include <linux/init.h>\n+#include <linux/platform_device.h>\n+#include <linux/gpio.h>\n+#include <linux/irq.h>\n+\n+#define DRIVER_NAME\t\"ar2315-gpio\"\n+\n+#define AR2315_GPIO_DI\t\t\t0x0000\n+#define AR2315_GPIO_DO\t\t\t0x0008\n+#define AR2315_GPIO_DIR\t\t\t0x0010\n+#define AR2315_GPIO_INT\t\t\t0x0018\n+\n+#define AR2315_GPIO_DIR_M(x)\t\t(1 << (x))\t/* mask for i/o */\n+#define AR2315_GPIO_DIR_O(x)\t\t(1 << (x))\t/* output */\n+#define AR2315_GPIO_DIR_I(x)\t\t(0)\t\t/* input */\n+\n+#define AR2315_GPIO_INT_NUM_M\t\t0x3F\t\t/* mask for GPIO num */\n+#define AR2315_GPIO_INT_TRIG(x)\t\t((x) << 6)\t/* interrupt trigger */\n+#define AR2315_GPIO_INT_TRIG_M\t\t(0x3 << 6)\t/* mask for int trig */\n+\n+#define AR2315_GPIO_INT_TRIG_OFF\t0\t/* Triggerring off */\n+#define AR2315_GPIO_INT_TRIG_LOW\t1\t/* Low Level Triggered */\n+#define AR2315_GPIO_INT_TRIG_HIGH\t2\t/* High Level Triggered */\n+#define AR2315_GPIO_INT_TRIG_EDGE\t3\t/* Edge Triggered */\n+\n+#define AR2315_GPIO_NUM\t\t22\n+\n+static u32 ar2315_gpio_intmask;\n+static u32 ar2315_gpio_intval;\n+static unsigned ar2315_gpio_irq_base;\n+static void __iomem *ar2315_mem;\n+\n+static inline u32 ar2315_gpio_reg_read(unsigned reg)\n+{\n+\treturn __raw_readl(ar2315_mem + reg);\n+}\n+\n+static inline void ar2315_gpio_reg_write(unsigned reg, u32 val)\n+{\n+\t__raw_writel(val, ar2315_mem + reg);\n+}\n+\n+static inline void ar2315_gpio_reg_mask(unsigned reg, u32 mask, u32 val)\n+{\n+\tar2315_gpio_reg_write(reg, (ar2315_gpio_reg_read(reg) & ~mask) | val);\n+}\n+\n+static void ar2315_gpio_irq_handler(struct irq_desc *desc)\n+{\n+\tu32 pend;\n+\tint bit = -1;\n+\n+\t/* only do one gpio interrupt at a time */\n+\tpend = ar2315_gpio_reg_read(AR2315_GPIO_DI);\n+\tpend ^= ar2315_gpio_intval;\n+\tpend &= ar2315_gpio_intmask;\n+\n+\tif (pend) {\n+\t\tbit = fls(pend) - 1;\n+\t\tpend &= ~(1 << bit);\n+\t\tar2315_gpio_intval ^= (1 << bit);\n+\t}\n+\n+\t/* Enable interrupt with edge detection */\n+\tif ((ar2315_gpio_reg_read(AR2315_GPIO_DIR) & AR2315_GPIO_DIR_M(bit)) !=\n+\t    AR2315_GPIO_DIR_I(bit))\n+\t\treturn;\n+\n+\tif (bit >= 0)\n+\t\tgeneric_handle_irq(ar2315_gpio_irq_base + bit);\n+}\n+\n+static void ar2315_gpio_int_setup(unsigned gpio, int trig)\n+{\n+\tu32 reg = ar2315_gpio_reg_read(AR2315_GPIO_INT);\n+\n+\treg &= ~(AR2315_GPIO_INT_NUM_M | AR2315_GPIO_INT_TRIG_M);\n+\treg |= gpio | AR2315_GPIO_INT_TRIG(trig);\n+\tar2315_gpio_reg_write(AR2315_GPIO_INT, reg);\n+}\n+\n+static void ar2315_gpio_irq_unmask(struct irq_data *d)\n+{\n+\tunsigned gpio = d->irq - ar2315_gpio_irq_base;\n+\tu32 dir = ar2315_gpio_reg_read(AR2315_GPIO_DIR);\n+\n+\t/* Enable interrupt with edge detection */\n+\tif ((dir & AR2315_GPIO_DIR_M(gpio)) != AR2315_GPIO_DIR_I(gpio))\n+\t\treturn;\n+\n+\tar2315_gpio_intmask |= (1 << gpio);\n+\tar2315_gpio_int_setup(gpio, AR2315_GPIO_INT_TRIG_EDGE);\n+}\n+\n+static void ar2315_gpio_irq_mask(struct irq_data *d)\n+{\n+\tunsigned gpio = d->irq - ar2315_gpio_irq_base;\n+\n+\t/* Disable interrupt */\n+\tar2315_gpio_intmask &= ~(1 << gpio);\n+\tar2315_gpio_int_setup(gpio, AR2315_GPIO_INT_TRIG_OFF);\n+}\n+\n+static struct irq_chip ar2315_gpio_irq_chip = {\n+\t.name\t\t= DRIVER_NAME,\n+\t.irq_unmask\t= ar2315_gpio_irq_unmask,\n+\t.irq_mask\t= ar2315_gpio_irq_mask,\n+};\n+\n+static void ar2315_gpio_irq_init(unsigned irq)\n+{\n+\tunsigned i;\n+\n+\tar2315_gpio_intval = ar2315_gpio_reg_read(AR2315_GPIO_DI);\n+\tfor (i = 0; i < AR2315_GPIO_NUM; i++) {\n+\t\tunsigned _irq = ar2315_gpio_irq_base + i;\n+\n+\t\tirq_set_chip_and_handler(_irq, &ar2315_gpio_irq_chip,\n+\t\t\t\t\t handle_level_irq);\n+\t}\n+\tirq_set_chained_handler(irq, ar2315_gpio_irq_handler);\n+}\n+\n+static int ar2315_gpio_get_val(struct gpio_chip *chip, unsigned gpio)\n+{\n+\treturn (ar2315_gpio_reg_read(AR2315_GPIO_DI) >> gpio) & 1;\n+}\n+\n+static void ar2315_gpio_set_val(struct gpio_chip *chip, unsigned gpio, int val)\n+{\n+\tu32 reg = ar2315_gpio_reg_read(AR2315_GPIO_DO);\n+\n+\treg = val ? reg | (1 << gpio) : reg & ~(1 << gpio);\n+\tar2315_gpio_reg_write(AR2315_GPIO_DO, reg);\n+}\n+\n+static int ar2315_gpio_dir_in(struct gpio_chip *chip, unsigned gpio)\n+{\n+\tar2315_gpio_reg_mask(AR2315_GPIO_DIR, 1 << gpio, 0);\n+\treturn 0;\n+}\n+\n+static int ar2315_gpio_dir_out(struct gpio_chip *chip, unsigned gpio, int val)\n+{\n+\tar2315_gpio_reg_mask(AR2315_GPIO_DIR, 0, 1 << gpio);\n+\tar2315_gpio_set_val(chip, gpio, val);\n+\treturn 0;\n+}\n+\n+static int ar2315_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)\n+{\n+\treturn ar2315_gpio_irq_base + gpio;\n+}\n+\n+static struct gpio_chip ar2315_gpio_chip = {\n+\t.label\t\t\t= DRIVER_NAME,\n+\t.direction_input\t= ar2315_gpio_dir_in,\n+\t.direction_output\t= ar2315_gpio_dir_out,\n+\t.set\t\t\t= ar2315_gpio_set_val,\n+\t.get\t\t\t= ar2315_gpio_get_val,\n+\t.to_irq\t\t\t= ar2315_gpio_to_irq,\n+\t.base\t\t\t= 0,\n+\t.ngpio\t\t\t= AR2315_GPIO_NUM,\n+};\n+\n+static int ar2315_gpio_probe(struct platform_device *pdev)\n+{\n+\tstruct device *dev = &pdev->dev;\n+\tstruct resource *res;\n+\tunsigned irq;\n+\tint ret;\n+\n+\tif (ar2315_mem)\n+\t\treturn -EBUSY;\n+\n+\tres = platform_get_resource_byname(pdev, IORESOURCE_IRQ,\n+\t\t\t\t\t   \"ar2315-gpio-irq-base\");\n+\tif (!res) {\n+\t\tdev_err(dev, \"not found GPIO IRQ base\\n\");\n+\t\treturn -ENXIO;\n+\t}\n+\tar2315_gpio_irq_base = res->start;\n+\n+\tres = platform_get_resource_byname(pdev, IORESOURCE_IRQ, DRIVER_NAME);\n+\tif (!res) {\n+\t\tdev_err(dev, \"not found IRQ number\\n\");\n+\t\treturn -ENXIO;\n+\t}\n+\tirq = res->start;\n+\n+\tres = platform_get_resource_byname(pdev, IORESOURCE_MEM, DRIVER_NAME);\n+\tar2315_mem = devm_ioremap_resource(dev, res);\n+\tif (IS_ERR(ar2315_mem))\n+\t\treturn PTR_ERR(ar2315_mem);\n+\n+\tar2315_gpio_chip.parent = dev;\n+\tret = gpiochip_add(&ar2315_gpio_chip);\n+\tif (ret) {\n+\t\tdev_err(dev, \"failed to add gpiochip\\n\");\n+\t\treturn ret;\n+\t}\n+\n+\tar2315_gpio_irq_init(irq);\n+\n+\treturn 0;\n+}\n+\n+static struct platform_driver ar2315_gpio_driver = {\n+\t.probe = ar2315_gpio_probe,\n+\t.driver = {\n+\t\t.name = DRIVER_NAME,\n+\t\t.owner = THIS_MODULE,\n+\t}\n+};\n+\n+static int __init ar2315_gpio_init(void)\n+{\n+\treturn platform_driver_register(&ar2315_gpio_driver);\n+}\n+subsys_initcall(ar2315_gpio_init);\n--- a/arch/mips/ath25/devices.h\n+++ b/arch/mips/ath25/devices.h\n@@ -4,6 +4,11 @@\n \n #include <linux/cpu.h>\n \n+#define AR231X_GPIO_IRQ_BASE\t\t0x30\n+\n+/* GPIO number for AR2315/16 reset issue workaround */\n+#define AR2315_RESET_GPIO\t\t5\n+\n #define ATH25_REG_MS(_val, _field)\t(((_val) & _field##_M) >> _field##_S)\n \n #define ATH25_IRQ_CPU_CLOCK\t(MIPS_CPU_IRQ_BASE + 7)\t/* C0_CAUSE: 0x8000 */\n--- a/arch/mips/ath25/ar2315_regs.h\n+++ b/arch/mips/ath25/ar2315_regs.h\n@@ -315,6 +315,9 @@\n #define AR2315_MEM_CFG_BANKADDR_BITS_M\t0x00000018\n #define AR2315_MEM_CFG_BANKADDR_BITS_S\t3\n \n+/* GPIO MMR base address */\n+#define AR2315_GPIO\t\t\t0x0088\n+\n /*\n  * Local Bus Interface Registers\n  */\n"
  },
  {
    "path": "target/linux/ath25/patches-5.10/110-ar2313_ethernet.patch",
    "content": "--- a/drivers/net/ethernet/atheros/Makefile\n+++ b/drivers/net/ethernet/atheros/Makefile\n@@ -9,3 +9,4 @@ obj-$(CONFIG_ATL2) += atlx/\n obj-$(CONFIG_ATL1E) += atl1e/\n obj-$(CONFIG_ATL1C) += atl1c/\n obj-$(CONFIG_ALX) += alx/\n+obj-$(CONFIG_NET_AR231X) += ar231x/\n--- a/drivers/net/ethernet/atheros/Kconfig\n+++ b/drivers/net/ethernet/atheros/Kconfig\n@@ -6,7 +6,7 @@\n config NET_VENDOR_ATHEROS\n \tbool \"Atheros devices\"\n \tdefault y\n-\tdepends on (PCI || ATH79)\n+\tdepends on (PCI || ATH25 || ATH79)\n \thelp\n \t  If you have a network (Ethernet) card belonging to this class, say Y.\n \n@@ -87,4 +87,10 @@ config ALX\n \t  To compile this driver as a module, choose M here.  The module\n \t  will be called alx.\n \n+config NET_AR231X\n+\ttristate \"Atheros AR231X built-in Ethernet support\"\n+\tdepends on ATH25\n+\thelp\n+\t  Support for the AR231x/531x ethernet controller\n+\n endif # NET_VENDOR_ATHEROS\n--- /dev/null\n+++ b/drivers/net/ethernet/atheros/ar231x/Makefile\n@@ -0,0 +1 @@\n+obj-$(CONFIG_NET_AR231X) += ar231x.o\n--- /dev/null\n+++ b/drivers/net/ethernet/atheros/ar231x/ar231x.c\n@@ -0,0 +1,1119 @@\n+/*\n+ * ar231x.c: Linux driver for the Atheros AR231x Ethernet device.\n+ *\n+ * Copyright (C) 2004 by Sameer Dekate <sdekate@arubanetworks.com>\n+ * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>\n+ * Copyright (C) 2006-2009 Felix Fietkau <nbd@nbd.name>\n+ *\n+ * Thanks to Atheros for providing hardware and documentation\n+ * enabling me to write this driver.\n+ *\n+ * This program is free software; you can redistribute it and/or modify\n+ * it under the terms of the GNU General Public License as published by\n+ * the Free Software Foundation; either version 2 of the License, or\n+ * (at your option) any later version.\n+ *\n+ * Additional credits:\n+ * This code is taken from John Taylor's Sibyte driver and then\n+ * modified for the AR2313.\n+ */\n+\n+#include <linux/module.h>\n+#include <linux/types.h>\n+#include <linux/errno.h>\n+#include <linux/ioport.h>\n+#include <linux/netdevice.h>\n+#include <linux/etherdevice.h>\n+#include <linux/interrupt.h>\n+#include <linux/skbuff.h>\n+#include <linux/init.h>\n+#include <linux/delay.h>\n+#include <linux/mm.h>\n+#include <linux/mii.h>\n+#include <linux/phy.h>\n+#include <linux/platform_device.h>\n+#include <linux/io.h>\n+\n+#define AR2313_MTU                     1692\n+#define AR2313_PRIOS                   1\n+#define AR2313_QUEUES                  (2*AR2313_PRIOS)\n+#define AR2313_DESCR_ENTRIES           64\n+\n+#ifndef min\n+#define min(a, b)\t(((a) < (b)) ? (a) : (b))\n+#endif\n+\n+#ifndef SMP_CACHE_BYTES\n+#define SMP_CACHE_BYTES\tL1_CACHE_BYTES\n+#endif\n+\n+#define AR2313_MBOX_SET_BIT  0x8\n+\n+#include \"ar231x.h\"\n+\n+/**\n+ * New interrupt handler strategy:\n+ *\n+ * An old interrupt handler worked using the traditional method of\n+ * replacing an skbuff with a new one when a packet arrives. However\n+ * the rx rings do not need to contain a static number of buffer\n+ * descriptors, thus it makes sense to move the memory allocation out\n+ * of the main interrupt handler and do it in a bottom half handler\n+ * and only allocate new buffers when the number of buffers in the\n+ * ring is below a certain threshold. In order to avoid starving the\n+ * NIC under heavy load it is however necessary to force allocation\n+ * when hitting a minimum threshold. The strategy for alloction is as\n+ * follows:\n+ *\n+ *     RX_LOW_BUF_THRES    - allocate buffers in the bottom half\n+ *     RX_PANIC_LOW_THRES  - we are very low on buffers, allocate\n+ *                           the buffers in the interrupt handler\n+ *     RX_RING_THRES       - maximum number of buffers in the rx ring\n+ *\n+ * One advantagous side effect of this allocation approach is that the\n+ * entire rx processing can be done without holding any spin lock\n+ * since the rx rings and registers are totally independent of the tx\n+ * ring and its registers.  This of course includes the kmalloc's of\n+ * new skb's. Thus start_xmit can run in parallel with rx processing\n+ * and the memory allocation on SMP systems.\n+ *\n+ * Note that running the skb reallocation in a bottom half opens up\n+ * another can of races which needs to be handled properly. In\n+ * particular it can happen that the interrupt handler tries to run\n+ * the reallocation while the bottom half is either running on another\n+ * CPU or was interrupted on the same CPU. To get around this the\n+ * driver uses bitops to prevent the reallocation routines from being\n+ * reentered.\n+ *\n+ * TX handling can also be done without holding any spin lock, wheee\n+ * this is fun! since tx_csm is only written to by the interrupt\n+ * handler.\n+ */\n+\n+/**\n+ * Threshold values for RX buffer allocation - the low water marks for\n+ * when to start refilling the rings are set to 75% of the ring\n+ * sizes. It seems to make sense to refill the rings entirely from the\n+ * intrrupt handler once it gets below the panic threshold, that way\n+ * we don't risk that the refilling is moved to another CPU when the\n+ * one running the interrupt handler just got the slab code hot in its\n+ * cache.\n+ */\n+#define RX_RING_SIZE\t\tAR2313_DESCR_ENTRIES\n+#define RX_PANIC_THRES\t        (RX_RING_SIZE/4)\n+#define RX_LOW_THRES\t        ((3*RX_RING_SIZE)/4)\n+#define CRC_LEN                 4\n+#define RX_OFFSET               2\n+\n+#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)\n+#define VLAN_HDR                4\n+#else\n+#define VLAN_HDR                0\n+#endif\n+\n+#define AR2313_BUFSIZE\t\t(AR2313_MTU + VLAN_HDR + ETH_HLEN + CRC_LEN + \\\n+\t\t\t\t RX_OFFSET)\n+\n+#ifdef MODULE\n+MODULE_LICENSE(\"GPL\");\n+MODULE_AUTHOR(\"Sameer Dekate <sdekate@arubanetworks.com>, Imre Kaloz <kaloz@openwrt.org>, Felix Fietkau <nbd@nbd.name>\");\n+MODULE_DESCRIPTION(\"AR231x Ethernet driver\");\n+#endif\n+\n+#define virt_to_phys(x) ((u32)(x) & 0x1fffffff)\n+\n+/* prototypes */\n+static void ar231x_halt(struct net_device *dev);\n+static void rx_tasklet_func(unsigned long data);\n+static void rx_tasklet_cleanup(struct net_device *dev);\n+static void ar231x_multicast_list(struct net_device *dev);\n+static void ar231x_tx_timeout(struct net_device *dev, unsigned int txqueue);\n+\n+static int ar231x_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum);\n+static int ar231x_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum,\n+\t\t\t\tu16 value);\n+static int ar231x_mdiobus_reset(struct mii_bus *bus);\n+static int ar231x_mdiobus_probe(struct net_device *dev);\n+static void ar231x_adjust_link(struct net_device *dev);\n+\n+#ifndef ERR\n+#define ERR(fmt, args...) printk(\"%s: \" fmt, __func__, ##args)\n+#endif\n+\n+#ifdef CONFIG_NET_POLL_CONTROLLER\n+static void\n+ar231x_netpoll(struct net_device *dev)\n+{\n+\tunsigned long flags;\n+\n+\tlocal_irq_save(flags);\n+\tar231x_interrupt(dev->irq, dev);\n+\tlocal_irq_restore(flags);\n+}\n+#endif\n+\n+static const struct net_device_ops ar231x_ops = {\n+\t.ndo_open\t\t= ar231x_open,\n+\t.ndo_stop\t\t= ar231x_close,\n+\t.ndo_start_xmit\t\t= ar231x_start_xmit,\n+\t.ndo_set_rx_mode\t= ar231x_multicast_list,\n+\t.ndo_do_ioctl\t\t= ar231x_ioctl,\n+\t.ndo_validate_addr\t= eth_validate_addr,\n+\t.ndo_set_mac_address\t= eth_mac_addr,\n+\t.ndo_tx_timeout\t\t= ar231x_tx_timeout,\n+#ifdef CONFIG_NET_POLL_CONTROLLER\n+\t.ndo_poll_controller\t= ar231x_netpoll,\n+#endif\n+};\n+\n+static int ar231x_probe(struct platform_device *pdev)\n+{\n+\tstruct net_device *dev;\n+\tstruct ar231x_private *sp;\n+\tstruct resource *res;\n+\tunsigned long ar_eth_base;\n+\tchar buf[64];\n+\n+\tdev = alloc_etherdev(sizeof(struct ar231x_private));\n+\n+\tif (dev == NULL) {\n+\t\tprintk(KERN_ERR\n+\t\t\t   \"ar231x: Unable to allocate net_device structure!\\n\");\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\tplatform_set_drvdata(pdev, dev);\n+\n+\tSET_NETDEV_DEV(dev, &pdev->dev);\n+\n+\tsp = netdev_priv(dev);\n+\tsp->dev = dev;\n+\tsp->pdev = pdev;\n+\tsp->cfg = pdev->dev.platform_data;\n+\n+\tsprintf(buf, \"eth%d_membase\", pdev->id);\n+\tres = platform_get_resource_byname(pdev, IORESOURCE_MEM, buf);\n+\tif (!res)\n+\t\treturn -ENODEV;\n+\n+\tsp->link = 0;\n+\tar_eth_base = res->start;\n+\n+\tsprintf(buf, \"eth%d_irq\", pdev->id);\n+\tdev->irq = platform_get_irq_byname(pdev, buf);\n+\n+\tspin_lock_init(&sp->lock);\n+\n+\tdev->features |= NETIF_F_HIGHDMA;\n+\tdev->netdev_ops = &ar231x_ops;\n+\n+\ttasklet_init(&sp->rx_tasklet, rx_tasklet_func, (unsigned long)dev);\n+\ttasklet_disable(&sp->rx_tasklet);\n+\n+\tsp->eth_regs = ioremap(ar_eth_base, sizeof(*sp->eth_regs));\n+\tif (!sp->eth_regs) {\n+\t\tprintk(\"Can't remap eth registers\\n\");\n+\t\treturn -ENXIO;\n+\t}\n+\n+\t/**\n+\t * When there's only one MAC, PHY regs are typically on ENET0,\n+\t * even though the MAC might be on ENET1.\n+\t * So remap PHY regs separately.\n+\t */\n+\tres = platform_get_resource_byname(pdev, IORESOURCE_MEM, \"eth0_mii\");\n+\tif (!res) {\n+\t\tres = platform_get_resource_byname(pdev, IORESOURCE_MEM,\n+\t\t\t\t\t\t   \"eth1_mii\");\n+\t\tif (!res)\n+\t\t\treturn -ENODEV;\n+\t}\n+\tsp->phy_regs = ioremap(res->start, resource_size(res));\n+\tif (!sp->phy_regs) {\n+\t\tprintk(\"Can't remap phy registers\\n\");\n+\t\treturn -ENXIO;\n+\t}\n+\n+\tsp->dma_regs = ioremap(ar_eth_base + 0x1000,\n+\t\t\t       sizeof(*sp->dma_regs));\n+\tif (!sp->dma_regs) {\n+\t\tprintk(\"Can't remap DMA registers\\n\");\n+\t\treturn -ENXIO;\n+\t}\n+\tdev->base_addr = ar_eth_base + 0x1000;\n+\n+\tstrncpy(sp->name, \"Atheros AR231x\", sizeof(sp->name) - 1);\n+\tsp->name[sizeof(sp->name) - 1] = '\\0';\n+\tmemcpy(dev->dev_addr, sp->cfg->macaddr, 6);\n+\n+\tif (ar231x_init(dev)) {\n+\t\t/* ar231x_init() calls ar231x_init_cleanup() on error */\n+\t\tkfree(dev);\n+\t\treturn -ENODEV;\n+\t}\n+\n+\tif (register_netdev(dev)) {\n+\t\tprintk(\"%s: register_netdev failed\\n\", __func__);\n+\t\treturn -1;\n+\t}\n+\n+\tprintk(\"%s: %s: %pM, irq %d\\n\", dev->name, sp->name, dev->dev_addr,\n+\t       dev->irq);\n+\n+\tsp->mii_bus = mdiobus_alloc();\n+\tif (sp->mii_bus == NULL)\n+\t\treturn -1;\n+\n+\tsp->mii_bus->priv = dev;\n+\tsp->mii_bus->read = ar231x_mdiobus_read;\n+\tsp->mii_bus->write = ar231x_mdiobus_write;\n+\tsp->mii_bus->reset = ar231x_mdiobus_reset;\n+\tsp->mii_bus->name = \"ar231x_eth_mii\";\n+\tsnprintf(sp->mii_bus->id, MII_BUS_ID_SIZE, \"%d\", pdev->id);\n+\n+\tmdiobus_register(sp->mii_bus);\n+\n+\tif (ar231x_mdiobus_probe(dev) != 0) {\n+\t\tprintk(KERN_ERR \"%s: mdiobus_probe failed\\n\", dev->name);\n+\t\trx_tasklet_cleanup(dev);\n+\t\tar231x_init_cleanup(dev);\n+\t\tunregister_netdev(dev);\n+\t\tkfree(dev);\n+\t\treturn -ENODEV;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static void ar231x_multicast_list(struct net_device *dev)\n+{\n+\tstruct ar231x_private *sp = netdev_priv(dev);\n+\tunsigned int filter;\n+\n+\tfilter = sp->eth_regs->mac_control;\n+\n+\tif (dev->flags & IFF_PROMISC)\n+\t\tfilter |= MAC_CONTROL_PR;\n+\telse\n+\t\tfilter &= ~MAC_CONTROL_PR;\n+\tif ((dev->flags & IFF_ALLMULTI) || (netdev_mc_count(dev) > 0))\n+\t\tfilter |= MAC_CONTROL_PM;\n+\telse\n+\t\tfilter &= ~MAC_CONTROL_PM;\n+\n+\tsp->eth_regs->mac_control = filter;\n+}\n+\n+static void rx_tasklet_cleanup(struct net_device *dev)\n+{\n+\tstruct ar231x_private *sp = netdev_priv(dev);\n+\n+\t/**\n+\t * Tasklet may be scheduled. Need to get it removed from the list\n+\t * since we're about to free the struct.\n+\t */\n+\n+\tsp->unloading = 1;\n+\ttasklet_enable(&sp->rx_tasklet);\n+\ttasklet_kill(&sp->rx_tasklet);\n+}\n+\n+static int ar231x_remove(struct platform_device *pdev)\n+{\n+\tstruct net_device *dev = platform_get_drvdata(pdev);\n+\tstruct ar231x_private *sp = netdev_priv(dev);\n+\n+\trx_tasklet_cleanup(dev);\n+\tar231x_init_cleanup(dev);\n+\tunregister_netdev(dev);\n+\tmdiobus_unregister(sp->mii_bus);\n+\tmdiobus_free(sp->mii_bus);\n+\tkfree(dev);\n+\treturn 0;\n+}\n+\n+/**\n+ * Restart the AR2313 ethernet controller.\n+ */\n+static int ar231x_restart(struct net_device *dev)\n+{\n+\t/* disable interrupts */\n+\tdisable_irq(dev->irq);\n+\n+\t/* stop mac */\n+\tar231x_halt(dev);\n+\n+\t/* initialize */\n+\tar231x_init(dev);\n+\n+\t/* enable interrupts */\n+\tenable_irq(dev->irq);\n+\n+\treturn 0;\n+}\n+\n+static struct platform_driver ar231x_driver = {\n+\t.driver.name = \"ar231x-eth\",\n+\t.probe = ar231x_probe,\n+\t.remove = ar231x_remove,\n+};\n+\n+module_platform_driver(ar231x_driver);\n+\n+static void ar231x_free_descriptors(struct net_device *dev)\n+{\n+\tstruct ar231x_private *sp = netdev_priv(dev);\n+\n+\tif (sp->rx_ring != NULL) {\n+\t\tkfree((void *)KSEG0ADDR(sp->rx_ring));\n+\t\tsp->rx_ring = NULL;\n+\t\tsp->tx_ring = NULL;\n+\t}\n+}\n+\n+static int ar231x_allocate_descriptors(struct net_device *dev)\n+{\n+\tstruct ar231x_private *sp = netdev_priv(dev);\n+\tint size;\n+\tint j;\n+\tar231x_descr_t *space;\n+\n+\tif (sp->rx_ring != NULL) {\n+\t\tprintk(\"%s: already done.\\n\", __func__);\n+\t\treturn 0;\n+\t}\n+\n+\tsize = sizeof(ar231x_descr_t) * (AR2313_DESCR_ENTRIES * AR2313_QUEUES);\n+\tspace = kmalloc(size, GFP_KERNEL);\n+\tif (space == NULL)\n+\t\treturn 1;\n+\n+\t/* invalidate caches */\n+\tdma_cache_inv((unsigned int)space, size);\n+\n+\t/* now convert pointer to KSEG1 */\n+\tspace = (ar231x_descr_t *)KSEG1ADDR(space);\n+\n+\tmemset((void *)space, 0, size);\n+\n+\tsp->rx_ring = space;\n+\tspace += AR2313_DESCR_ENTRIES;\n+\n+\tsp->tx_ring = space;\n+\tspace += AR2313_DESCR_ENTRIES;\n+\n+\t/* Initialize the transmit Descriptors */\n+\tfor (j = 0; j < AR2313_DESCR_ENTRIES; j++) {\n+\t\tar231x_descr_t *td = &sp->tx_ring[j];\n+\n+\t\ttd->status = 0;\n+\t\ttd->devcs = DMA_TX1_CHAINED;\n+\t\ttd->addr = 0;\n+\t\ttd->descr = virt_to_phys(&sp->tx_ring[DSC_NEXT(j)]);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+/**\n+ * Generic cleanup handling data allocated during init. Used when the\n+ * module is unloaded or if an error occurs during initialization\n+ */\n+static void ar231x_init_cleanup(struct net_device *dev)\n+{\n+\tstruct ar231x_private *sp = netdev_priv(dev);\n+\tstruct sk_buff *skb;\n+\tint j;\n+\n+\tar231x_free_descriptors(dev);\n+\n+\tif (sp->eth_regs)\n+\t\tiounmap((void *)sp->eth_regs);\n+\tif (sp->dma_regs)\n+\t\tiounmap((void *)sp->dma_regs);\n+\tif (sp->phy_regs)\n+\t\tiounmap((void *)sp->phy_regs);\n+\n+\tif (sp->rx_skb) {\n+\t\tfor (j = 0; j < AR2313_DESCR_ENTRIES; j++) {\n+\t\t\tskb = sp->rx_skb[j];\n+\t\t\tif (skb) {\n+\t\t\t\tsp->rx_skb[j] = NULL;\n+\t\t\t\tdev_kfree_skb(skb);\n+\t\t\t}\n+\t\t}\n+\t\tkfree(sp->rx_skb);\n+\t\tsp->rx_skb = NULL;\n+\t}\n+\n+\tif (sp->tx_skb) {\n+\t\tfor (j = 0; j < AR2313_DESCR_ENTRIES; j++) {\n+\t\t\tskb = sp->tx_skb[j];\n+\t\t\tif (skb) {\n+\t\t\t\tsp->tx_skb[j] = NULL;\n+\t\t\t\tdev_kfree_skb(skb);\n+\t\t\t}\n+\t\t}\n+\t\tkfree(sp->tx_skb);\n+\t\tsp->tx_skb = NULL;\n+\t}\n+}\n+\n+static int ar231x_reset_reg(struct net_device *dev)\n+{\n+\tstruct ar231x_private *sp = netdev_priv(dev);\n+\tunsigned int ethsal, ethsah;\n+\tunsigned int flags;\n+\n+\tsp->cfg->reset_set(sp->cfg->reset_mac);\n+\tmdelay(10);\n+\tsp->cfg->reset_clear(sp->cfg->reset_mac);\n+\tmdelay(10);\n+\tsp->cfg->reset_set(sp->cfg->reset_phy);\n+\tmdelay(10);\n+\tsp->cfg->reset_clear(sp->cfg->reset_phy);\n+\tmdelay(10);\n+\n+\tsp->dma_regs->bus_mode = (DMA_BUS_MODE_SWR);\n+\tmdelay(10);\n+\tsp->dma_regs->bus_mode =\n+\t\t((32 << DMA_BUS_MODE_PBL_SHIFT) | DMA_BUS_MODE_BLE);\n+\n+\t/* enable interrupts */\n+\tsp->dma_regs->intr_ena = DMA_STATUS_AIS | DMA_STATUS_NIS |\n+\t\t\t\t DMA_STATUS_RI | DMA_STATUS_TI |\n+\t\t\t\t DMA_STATUS_FBE;\n+\tsp->dma_regs->xmt_base = virt_to_phys(sp->tx_ring);\n+\tsp->dma_regs->rcv_base = virt_to_phys(sp->rx_ring);\n+\tsp->dma_regs->control =\n+\t\t(DMA_CONTROL_SR | DMA_CONTROL_ST | DMA_CONTROL_SF);\n+\n+\tsp->eth_regs->flow_control = (FLOW_CONTROL_FCE);\n+\tsp->eth_regs->vlan_tag = (0x8100);\n+\n+\t/* Enable Ethernet Interface */\n+\tflags = (MAC_CONTROL_TE |\t/* transmit enable */\n+\t\t\t MAC_CONTROL_PM |\t/* pass mcast */\n+\t\t\t MAC_CONTROL_F |\t/* full duplex */\n+\t\t\t MAC_CONTROL_HBD);\t/* heart beat disabled */\n+\n+\tif (dev->flags & IFF_PROMISC) {\t/* set promiscuous mode */\n+\t\tflags |= MAC_CONTROL_PR;\n+\t}\n+\tsp->eth_regs->mac_control = flags;\n+\n+\t/* Set all Ethernet station address registers to their initial values */\n+\tethsah = (((u_int) (dev->dev_addr[5]) << 8) & (u_int) 0x0000FF00) |\n+\t\t (((u_int) (dev->dev_addr[4]) << 0) & (u_int) 0x000000FF);\n+\n+\tethsal = (((u_int) (dev->dev_addr[3]) << 24) & (u_int) 0xFF000000) |\n+\t\t (((u_int) (dev->dev_addr[2]) << 16) & (u_int) 0x00FF0000) |\n+\t\t (((u_int) (dev->dev_addr[1]) << 8) & (u_int) 0x0000FF00) |\n+\t\t (((u_int) (dev->dev_addr[0]) << 0) & (u_int) 0x000000FF);\n+\n+\tsp->eth_regs->mac_addr[0] = ethsah;\n+\tsp->eth_regs->mac_addr[1] = ethsal;\n+\n+\tmdelay(10);\n+\n+\treturn 0;\n+}\n+\n+static int ar231x_init(struct net_device *dev)\n+{\n+\tstruct ar231x_private *sp = netdev_priv(dev);\n+\tint ecode = 0;\n+\n+\t/* Allocate descriptors */\n+\tif (ar231x_allocate_descriptors(dev)) {\n+\t\tprintk(\"%s: %s: ar231x_allocate_descriptors failed\\n\",\n+\t\t       dev->name, __func__);\n+\t\tecode = -EAGAIN;\n+\t\tgoto init_error;\n+\t}\n+\n+\t/* Get the memory for the skb rings */\n+\tif (sp->rx_skb == NULL) {\n+\t\tsp->rx_skb =\n+\t\t\tkmalloc(sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES,\n+\t\t\t\tGFP_KERNEL);\n+\t\tif (!(sp->rx_skb)) {\n+\t\t\tprintk(\"%s: %s: rx_skb kmalloc failed\\n\",\n+\t\t\t       dev->name, __func__);\n+\t\t\tecode = -EAGAIN;\n+\t\t\tgoto init_error;\n+\t\t}\n+\t}\n+\tmemset(sp->rx_skb, 0, sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES);\n+\n+\tif (sp->tx_skb == NULL) {\n+\t\tsp->tx_skb =\n+\t\t\tkmalloc(sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES,\n+\t\t\t\tGFP_KERNEL);\n+\t\tif (!(sp->tx_skb)) {\n+\t\t\tprintk(\"%s: %s: tx_skb kmalloc failed\\n\",\n+\t\t\t       dev->name, __func__);\n+\t\t\tecode = -EAGAIN;\n+\t\t\tgoto init_error;\n+\t\t}\n+\t}\n+\tmemset(sp->tx_skb, 0, sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES);\n+\n+\t/**\n+\t * Set tx_csm before we start receiving interrupts, otherwise\n+\t * the interrupt handler might think it is supposed to process\n+\t * tx ints before we are up and running, which may cause a null\n+\t * pointer access in the int handler.\n+\t */\n+\tsp->rx_skbprd = 0;\n+\tsp->cur_rx = 0;\n+\tsp->tx_prd = 0;\n+\tsp->tx_csm = 0;\n+\n+\t/* Zero the stats before starting the interface */\n+\tmemset(&dev->stats, 0, sizeof(dev->stats));\n+\n+\t/**\n+\t * We load the ring here as there seem to be no way to tell the\n+\t * firmware to wipe the ring without re-initializing it.\n+\t */\n+\tar231x_load_rx_ring(dev, RX_RING_SIZE);\n+\n+\t/* Init hardware */\n+\tar231x_reset_reg(dev);\n+\n+\t/* Get the IRQ */\n+\tecode = request_irq(dev->irq, &ar231x_interrupt, 0,\n+\t\t\t    dev->name, dev);\n+\tif (ecode) {\n+\t\tprintk(KERN_WARNING \"%s: %s: Requested IRQ %d is busy\\n\",\n+\t\t       dev->name, __func__, dev->irq);\n+\t\tgoto init_error;\n+\t}\n+\n+\ttasklet_enable(&sp->rx_tasklet);\n+\n+\treturn 0;\n+\n+init_error:\n+\tar231x_init_cleanup(dev);\n+\treturn ecode;\n+}\n+\n+/**\n+ * Load the rx ring.\n+ *\n+ * Loading rings is safe without holding the spin lock since this is\n+ * done only before the device is enabled, thus no interrupts are\n+ * generated and by the interrupt handler/tasklet handler.\n+ */\n+static void ar231x_load_rx_ring(struct net_device *dev, int nr_bufs)\n+{\n+\tstruct ar231x_private *sp = netdev_priv(dev);\n+\tshort i, idx;\n+\n+\tidx = sp->rx_skbprd;\n+\n+\tfor (i = 0; i < nr_bufs; i++) {\n+\t\tstruct sk_buff *skb;\n+\t\tar231x_descr_t *rd;\n+\n+\t\tif (sp->rx_skb[idx])\n+\t\t\tbreak;\n+\n+\t\tskb = netdev_alloc_skb_ip_align(dev, AR2313_BUFSIZE);\n+\t\tif (!skb) {\n+\t\t\tprintk(\"\\n\\n\\n\\n %s: No memory in system\\n\\n\\n\\n\",\n+\t\t\t       __func__);\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\t/* Make sure IP header starts on a fresh cache line */\n+\t\tskb->dev = dev;\n+\t\tsp->rx_skb[idx] = skb;\n+\n+\t\trd = (ar231x_descr_t *)&sp->rx_ring[idx];\n+\n+\t\t/* initialize dma descriptor */\n+\t\trd->devcs = ((AR2313_BUFSIZE << DMA_RX1_BSIZE_SHIFT) |\n+\t\t\t\t\t DMA_RX1_CHAINED);\n+\t\trd->addr = virt_to_phys(skb->data);\n+\t\trd->descr = virt_to_phys(&sp->rx_ring[DSC_NEXT(idx)]);\n+\t\trd->status = DMA_RX_OWN;\n+\n+\t\tidx = DSC_NEXT(idx);\n+\t}\n+\n+\tif (i)\n+\t\tsp->rx_skbprd = idx;\n+}\n+\n+#define AR2313_MAX_PKTS_PER_CALL        64\n+\n+static int ar231x_rx_int(struct net_device *dev)\n+{\n+\tstruct ar231x_private *sp = netdev_priv(dev);\n+\tstruct sk_buff *skb, *skb_new;\n+\tar231x_descr_t *rxdesc;\n+\tunsigned int status;\n+\tu32 idx;\n+\tint pkts = 0;\n+\tint rval;\n+\n+\tidx = sp->cur_rx;\n+\n+\t/* process at most the entire ring and then wait for another int */\n+\twhile (1) {\n+\t\trxdesc = &sp->rx_ring[idx];\n+\t\tstatus = rxdesc->status;\n+\n+\t\tif (status & DMA_RX_OWN) {\n+\t\t\t/* SiByte owns descriptor or descr not yet filled in */\n+\t\t\trval = 0;\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\tif (++pkts > AR2313_MAX_PKTS_PER_CALL) {\n+\t\t\trval = 1;\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\tif ((status & DMA_RX_ERROR) && !(status & DMA_RX_LONG)) {\n+\t\t\tdev->stats.rx_errors++;\n+\t\t\tdev->stats.rx_dropped++;\n+\n+\t\t\t/* add statistics counters */\n+\t\t\tif (status & DMA_RX_ERR_CRC)\n+\t\t\t\tdev->stats.rx_crc_errors++;\n+\t\t\tif (status & DMA_RX_ERR_COL)\n+\t\t\t\tdev->stats.rx_over_errors++;\n+\t\t\tif (status & DMA_RX_ERR_LENGTH)\n+\t\t\t\tdev->stats.rx_length_errors++;\n+\t\t\tif (status & DMA_RX_ERR_RUNT)\n+\t\t\t\tdev->stats.rx_over_errors++;\n+\t\t\tif (status & DMA_RX_ERR_DESC)\n+\t\t\t\tdev->stats.rx_over_errors++;\n+\n+\t\t} else {\n+\t\t\t/* alloc new buffer. */\n+\t\t\tskb_new = netdev_alloc_skb_ip_align(dev,\n+\t\t\t\t\t\t\t    AR2313_BUFSIZE);\n+\t\t\tif (skb_new != NULL) {\n+\t\t\t\tskb = sp->rx_skb[idx];\n+\t\t\t\t/* set skb */\n+\t\t\t\tskb_put(skb, ((status >> DMA_RX_LEN_SHIFT) &\n+\t\t\t\t\t0x3fff) - CRC_LEN);\n+\n+\t\t\t\tdev->stats.rx_bytes += skb->len;\n+\t\t\t\tskb->protocol = eth_type_trans(skb, dev);\n+\t\t\t\t/* pass the packet to upper layers */\n+\t\t\t\tnetif_rx(skb);\n+\n+\t\t\t\tskb_new->dev = dev;\n+\t\t\t\t/* reset descriptor's curr_addr */\n+\t\t\t\trxdesc->addr = virt_to_phys(skb_new->data);\n+\n+\t\t\t\tdev->stats.rx_packets++;\n+\t\t\t\tsp->rx_skb[idx] = skb_new;\n+\t\t\t} else {\n+\t\t\t\tdev->stats.rx_dropped++;\n+\t\t\t}\n+\t\t}\n+\n+\t\trxdesc->devcs = ((AR2313_BUFSIZE << DMA_RX1_BSIZE_SHIFT) |\n+\t\t\t\t\t\t DMA_RX1_CHAINED);\n+\t\trxdesc->status = DMA_RX_OWN;\n+\n+\t\tidx = DSC_NEXT(idx);\n+\t}\n+\n+\tsp->cur_rx = idx;\n+\n+\treturn rval;\n+}\n+\n+static void ar231x_tx_int(struct net_device *dev)\n+{\n+\tstruct ar231x_private *sp = netdev_priv(dev);\n+\tu32 idx;\n+\tstruct sk_buff *skb;\n+\tar231x_descr_t *txdesc;\n+\tunsigned int status = 0;\n+\n+\tidx = sp->tx_csm;\n+\n+\twhile (idx != sp->tx_prd) {\n+\t\ttxdesc = &sp->tx_ring[idx];\n+\t\tstatus = txdesc->status;\n+\n+\t\tif (status & DMA_TX_OWN) {\n+\t\t\t/* ar231x dma still owns descr */\n+\t\t\tbreak;\n+\t\t}\n+\t\t/* done with this descriptor */\n+\t\tdma_unmap_single(&sp->pdev->dev, txdesc->addr,\n+\t\t\t\t txdesc->devcs & DMA_TX1_BSIZE_MASK,\n+\t\t\t\t DMA_TO_DEVICE);\n+\t\ttxdesc->status = 0;\n+\n+\t\tif (status & DMA_TX_ERROR) {\n+\t\t\tdev->stats.tx_errors++;\n+\t\t\tdev->stats.tx_dropped++;\n+\t\t\tif (status & DMA_TX_ERR_UNDER)\n+\t\t\t\tdev->stats.tx_fifo_errors++;\n+\t\t\tif (status & DMA_TX_ERR_HB)\n+\t\t\t\tdev->stats.tx_heartbeat_errors++;\n+\t\t\tif (status & (DMA_TX_ERR_LOSS | DMA_TX_ERR_LINK))\n+\t\t\t\tdev->stats.tx_carrier_errors++;\n+\t\t\tif (status & (DMA_TX_ERR_LATE | DMA_TX_ERR_COL |\n+\t\t\t    DMA_TX_ERR_JABBER | DMA_TX_ERR_DEFER))\n+\t\t\t\tdev->stats.tx_aborted_errors++;\n+\t\t} else {\n+\t\t\t/* transmit OK */\n+\t\t\tdev->stats.tx_packets++;\n+\t\t}\n+\n+\t\tskb = sp->tx_skb[idx];\n+\t\tsp->tx_skb[idx] = NULL;\n+\t\tidx = DSC_NEXT(idx);\n+\t\tdev->stats.tx_bytes += skb->len;\n+\t\tdev_kfree_skb_irq(skb);\n+\t}\n+\n+\tsp->tx_csm = idx;\n+}\n+\n+static void rx_tasklet_func(unsigned long data)\n+{\n+\tstruct net_device *dev = (struct net_device *)data;\n+\tstruct ar231x_private *sp = netdev_priv(dev);\n+\n+\tif (sp->unloading)\n+\t\treturn;\n+\n+\tif (ar231x_rx_int(dev)) {\n+\t\ttasklet_hi_schedule(&sp->rx_tasklet);\n+\t} else {\n+\t\tunsigned long flags;\n+\n+\t\tspin_lock_irqsave(&sp->lock, flags);\n+\t\tsp->dma_regs->intr_ena |= DMA_STATUS_RI;\n+\t\tspin_unlock_irqrestore(&sp->lock, flags);\n+\t}\n+}\n+\n+static void rx_schedule(struct net_device *dev)\n+{\n+\tstruct ar231x_private *sp = netdev_priv(dev);\n+\n+\tsp->dma_regs->intr_ena &= ~DMA_STATUS_RI;\n+\n+\ttasklet_hi_schedule(&sp->rx_tasklet);\n+}\n+\n+static irqreturn_t ar231x_interrupt(int irq, void *dev_id)\n+{\n+\tstruct net_device *dev = (struct net_device *)dev_id;\n+\tstruct ar231x_private *sp = netdev_priv(dev);\n+\tunsigned int status, enabled;\n+\n+\t/* clear interrupt */\n+\t/* Don't clear RI bit if currently disabled */\n+\tstatus = sp->dma_regs->status;\n+\tenabled = sp->dma_regs->intr_ena;\n+\tsp->dma_regs->status = status & enabled;\n+\n+\tif (status & DMA_STATUS_NIS) {\n+\t\t/* normal status */\n+\t\t/**\n+\t\t * Don't schedule rx processing if interrupt\n+\t\t * is already disabled.\n+\t\t */\n+\t\tif (status & enabled & DMA_STATUS_RI) {\n+\t\t\t/* receive interrupt */\n+\t\t\trx_schedule(dev);\n+\t\t}\n+\t\tif (status & DMA_STATUS_TI) {\n+\t\t\t/* transmit interrupt */\n+\t\t\tar231x_tx_int(dev);\n+\t\t}\n+\t}\n+\n+\t/* abnormal status */\n+\tif (status & (DMA_STATUS_FBE | DMA_STATUS_TPS))\n+\t\tar231x_restart(dev);\n+\n+\treturn IRQ_HANDLED;\n+}\n+\n+static int ar231x_open(struct net_device *dev)\n+{\n+\tstruct ar231x_private *sp = netdev_priv(dev);\n+\tunsigned int ethsal, ethsah;\n+\n+\t/* reset the hardware, in case the MAC address changed */\n+\tethsah = (((u_int) (dev->dev_addr[5]) << 8) & (u_int) 0x0000FF00) |\n+\t\t (((u_int) (dev->dev_addr[4]) << 0) & (u_int) 0x000000FF);\n+\n+\tethsal = (((u_int) (dev->dev_addr[3]) << 24) & (u_int) 0xFF000000) |\n+\t\t (((u_int) (dev->dev_addr[2]) << 16) & (u_int) 0x00FF0000) |\n+\t\t (((u_int) (dev->dev_addr[1]) << 8) & (u_int) 0x0000FF00) |\n+\t\t (((u_int) (dev->dev_addr[0]) << 0) & (u_int) 0x000000FF);\n+\n+\tsp->eth_regs->mac_addr[0] = ethsah;\n+\tsp->eth_regs->mac_addr[1] = ethsal;\n+\n+\tmdelay(10);\n+\n+\tdev->mtu = 1500;\n+\tnetif_start_queue(dev);\n+\n+\tsp->eth_regs->mac_control |= MAC_CONTROL_RE;\n+\n+\tphy_start(sp->phy_dev);\n+\n+\treturn 0;\n+}\n+\n+static void ar231x_tx_timeout(struct net_device *dev, unsigned int txqueue)\n+{\n+\tstruct ar231x_private *sp = netdev_priv(dev);\n+\tunsigned long flags;\n+\n+\tspin_lock_irqsave(&sp->lock, flags);\n+\tar231x_restart(dev);\n+\tspin_unlock_irqrestore(&sp->lock, flags);\n+}\n+\n+static void ar231x_halt(struct net_device *dev)\n+{\n+\tstruct ar231x_private *sp = netdev_priv(dev);\n+\tint j;\n+\n+\ttasklet_disable(&sp->rx_tasklet);\n+\n+\t/* kill the MAC */\n+\tsp->eth_regs->mac_control &= ~(MAC_CONTROL_RE |\t/* disable Receives */\n+\t\t\t\t       MAC_CONTROL_TE);\t/* disable Transmits */\n+\t/* stop dma */\n+\tsp->dma_regs->control = 0;\n+\tsp->dma_regs->bus_mode = DMA_BUS_MODE_SWR;\n+\n+\t/* place phy and MAC in reset */\n+\tsp->cfg->reset_set(sp->cfg->reset_mac);\n+\tsp->cfg->reset_set(sp->cfg->reset_phy);\n+\n+\t/* free buffers on tx ring */\n+\tfor (j = 0; j < AR2313_DESCR_ENTRIES; j++) {\n+\t\tstruct sk_buff *skb;\n+\t\tar231x_descr_t *txdesc;\n+\n+\t\ttxdesc = &sp->tx_ring[j];\n+\t\ttxdesc->descr = 0;\n+\n+\t\tskb = sp->tx_skb[j];\n+\t\tif (skb) {\n+\t\t\tdev_kfree_skb(skb);\n+\t\t\tsp->tx_skb[j] = NULL;\n+\t\t}\n+\t}\n+}\n+\n+/**\n+ * close should do nothing. Here's why. It's called when\n+ * 'ifconfig bond0 down' is run. If it calls free_irq then\n+ * the irq is gone forever ! When bond0 is made 'up' again,\n+ * the ar231x_open () does not call request_irq (). Worse,\n+ * the call to ar231x_halt() generates a WDOG reset due to\n+ * the write to reset register and the box reboots.\n+ * Commenting this out is good since it allows the\n+ * system to resume when bond0 is made up again.\n+ */\n+static int ar231x_close(struct net_device *dev)\n+{\n+\tstruct ar231x_private *sp = netdev_priv(dev);\n+#if 0\n+\t/* Disable interrupts */\n+\tdisable_irq(dev->irq);\n+\n+\t/**\n+\t * Without (or before) releasing irq and stopping hardware, this\n+\t * is an absolute non-sense, by the way. It will be reset instantly\n+\t * by the first irq.\n+\t */\n+\tnetif_stop_queue(dev);\n+\n+\t/* stop the MAC and DMA engines */\n+\tar231x_halt(dev);\n+\n+\t/* release the interrupt */\n+\tfree_irq(dev->irq, dev);\n+\n+#endif\n+\n+\tphy_stop(sp->phy_dev);\n+\n+\treturn 0;\n+}\n+\n+static int ar231x_start_xmit(struct sk_buff *skb, struct net_device *dev)\n+{\n+\tstruct ar231x_private *sp = netdev_priv(dev);\n+\tar231x_descr_t *td;\n+\tu32 idx;\n+\n+\tidx = sp->tx_prd;\n+\ttd = &sp->tx_ring[idx];\n+\n+\tif (td->status & DMA_TX_OWN) {\n+\t\t/* free skbuf and lie to the caller that we sent it out */\n+\t\tdev->stats.tx_dropped++;\n+\t\tdev_kfree_skb(skb);\n+\n+\t\t/* restart transmitter in case locked */\n+\t\tsp->dma_regs->xmt_poll = 0;\n+\t\treturn 0;\n+\t}\n+\n+\t/* Setup the transmit descriptor. */\n+\ttd->devcs = ((skb->len << DMA_TX1_BSIZE_SHIFT) |\n+\t\t\t\t (DMA_TX1_LS | DMA_TX1_IC | DMA_TX1_CHAINED));\n+\ttd->addr = dma_map_single(&sp->pdev->dev, skb->data, skb->len, DMA_TO_DEVICE);\n+\ttd->status = DMA_TX_OWN;\n+\n+\t/* kick transmitter last */\n+\tsp->dma_regs->xmt_poll = 0;\n+\n+\tsp->tx_skb[idx] = skb;\n+\tidx = DSC_NEXT(idx);\n+\tsp->tx_prd = idx;\n+\n+\treturn 0;\n+}\n+\n+static int ar231x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)\n+{\n+\tstruct ar231x_private *sp = netdev_priv(dev);\n+\n+\tswitch (cmd) {\n+\tcase SIOCGMIIPHY:\n+\tcase SIOCGMIIREG:\n+\tcase SIOCSMIIREG:\n+\t\treturn phy_mii_ioctl(sp->phy_dev, ifr, cmd);\n+\n+\tdefault:\n+\t\tbreak;\n+\t}\n+\n+\treturn -EOPNOTSUPP;\n+}\n+\n+static void ar231x_adjust_link(struct net_device *dev)\n+{\n+\tstruct ar231x_private *sp = netdev_priv(dev);\n+\tstruct phy_device *phydev = sp->phy_dev;\n+\tu32 mc;\n+\n+\tif (!phydev->link) {\n+\t\tif (sp->link) {\n+\t\t\tpr_info(\"%s: link down\\n\", dev->name);\n+\t\t\tsp->link = 0;\n+\t\t}\n+\t\treturn;\n+\t}\n+\tsp->link = 1;\n+\n+\tpr_info(\"%s: link up (%uMbps/%s duplex)\\n\", dev->name,\n+\t\tphydev->speed, phydev->duplex ? \"full\" : \"half\");\n+\n+\tmc = sp->eth_regs->mac_control;\n+\tif (phydev->duplex)\n+\t\tmc = (mc | MAC_CONTROL_F) & ~MAC_CONTROL_DRO;\n+\telse\n+\t\tmc = (mc | MAC_CONTROL_DRO) & ~MAC_CONTROL_F;\n+\tsp->eth_regs->mac_control = mc;\n+\tsp->duplex = phydev->duplex;\n+}\n+\n+#define MII_ADDR(phy, reg) \\\n+\t((reg << MII_ADDR_REG_SHIFT) | (phy << MII_ADDR_PHY_SHIFT))\n+\n+static int\n+ar231x_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum)\n+{\n+\tstruct net_device *const dev = bus->priv;\n+\tstruct ar231x_private *sp = netdev_priv(dev);\n+\tvolatile MII *ethernet = sp->phy_regs;\n+\n+\tethernet->mii_addr = MII_ADDR(phy_addr, regnum);\n+\twhile (ethernet->mii_addr & MII_ADDR_BUSY)\n+\t\t;\n+\treturn ethernet->mii_data >> MII_DATA_SHIFT;\n+}\n+\n+static int\n+ar231x_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum, u16 value)\n+{\n+\tstruct net_device *const dev = bus->priv;\n+\tstruct ar231x_private *sp = netdev_priv(dev);\n+\tvolatile MII *ethernet = sp->phy_regs;\n+\n+\twhile (ethernet->mii_addr & MII_ADDR_BUSY)\n+\t\t;\n+\tethernet->mii_data = value << MII_DATA_SHIFT;\n+\tethernet->mii_addr = MII_ADDR(phy_addr, regnum) | MII_ADDR_WRITE;\n+\n+\treturn 0;\n+}\n+\n+static int ar231x_mdiobus_reset(struct mii_bus *bus)\n+{\n+\tstruct net_device *const dev = bus->priv;\n+\n+\tar231x_reset_reg(dev);\n+\n+\treturn 0;\n+}\n+\n+static int ar231x_mdiobus_probe(struct net_device *dev)\n+{\n+\t__ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };\n+\tstruct ar231x_private *const sp = netdev_priv(dev);\n+\tstruct phy_device *phydev = NULL;\n+\n+\t/* find the first (lowest address) PHY on the current MAC's MII bus */\n+\tphydev = phy_find_first(sp->mii_bus);\n+\tif (!phydev) {\n+\t\tprintk(KERN_ERR \"ar231x: %s: no PHY found\\n\", dev->name);\n+\t\treturn -1;\n+\t}\n+\n+\t/* now we are supposed to have a proper phydev, to attach to... */\n+\tBUG_ON(phydev->attached_dev);\n+\n+\tphydev = phy_connect(dev, phydev_name(phydev), &ar231x_adjust_link,\n+\t\t\t     PHY_INTERFACE_MODE_MII);\n+\tif (IS_ERR(phydev)) {\n+\t\tprintk(KERN_ERR \"%s: Could not attach to PHY\\n\", dev->name);\n+\t\treturn PTR_ERR(phydev);\n+\t}\n+\n+\t/* mask with MAC supported features */\n+\tlinkmode_set_bit_array(phy_10_100_features_array,\n+\t\t\t       ARRAY_SIZE(phy_10_100_features_array),\n+\t\t\t       mask);\n+\tlinkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, mask);\n+\tlinkmode_set_bit(ETHTOOL_LINK_MODE_MII_BIT, mask);\n+\tlinkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT, mask);\n+\n+\tlinkmode_and(phydev->supported, phydev->supported, mask);\n+\tlinkmode_copy(phydev->advertising, phydev->supported);\n+\n+\tsp->phy_dev = phydev;\n+\n+\tprintk(KERN_INFO \"%s: attached PHY driver [%s] (mii_bus:phy_addr=%s)\\n\",\n+\t       dev->name, phydev->drv->name, phydev_name(phydev));\n+\n+\treturn 0;\n+}\n+\n--- /dev/null\n+++ b/drivers/net/ethernet/atheros/ar231x/ar231x.h\n@@ -0,0 +1,282 @@\n+/*\n+ * ar231x.h: Linux driver for the Atheros AR231x Ethernet device.\n+ *\n+ * Copyright (C) 2004 by Sameer Dekate <sdekate@arubanetworks.com>\n+ * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>\n+ * Copyright (C) 2006-2009 Felix Fietkau <nbd@nbd.name>\n+ *\n+ * Thanks to Atheros for providing hardware and documentation\n+ * enabling me to write this driver.\n+ *\n+ * This program is free software; you can redistribute it and/or modify\n+ * it under the terms of the GNU General Public License as published by\n+ * the Free Software Foundation; either version 2 of the License, or\n+ * (at your option) any later version.\n+ */\n+\n+#ifndef _AR2313_H_\n+#define _AR2313_H_\n+\n+#include <linux/interrupt.h>\n+#include <generated/autoconf.h>\n+#include <linux/bitops.h>\n+#include <ath25_platform.h>\n+\n+/* probe link timer - 5 secs */\n+#define LINK_TIMER    (5*HZ)\n+\n+#define IS_DMA_TX_INT(X)   (((X) & (DMA_STATUS_TI)) != 0)\n+#define IS_DMA_RX_INT(X)   (((X) & (DMA_STATUS_RI)) != 0)\n+#define IS_DRIVER_OWNED(X) (((X) & (DMA_TX_OWN))    == 0)\n+\n+#define AR2313_TX_TIMEOUT (HZ/4)\n+\n+/* Rings */\n+#define DSC_RING_ENTRIES_SIZE\t(AR2313_DESCR_ENTRIES * sizeof(struct desc))\n+#define DSC_NEXT(idx)\t        ((idx + 1) & (AR2313_DESCR_ENTRIES - 1))\n+\n+#define AR2313_MBGET\t\t2\n+#define AR2313_MBSET\t\t3\n+#define AR2313_PCI_RECONFIG\t4\n+#define AR2313_PCI_DUMP\t\t5\n+#define AR2313_TEST_PANIC\t6\n+#define AR2313_TEST_NULLPTR\t7\n+#define AR2313_READ_DATA\t8\n+#define AR2313_WRITE_DATA\t9\n+#define AR2313_GET_VERSION\t10\n+#define AR2313_TEST_HANG\t11\n+#define AR2313_SYNC\t\t12\n+\n+#define DMA_RX_ERR_CRC\t\tBIT(1)\n+#define DMA_RX_ERR_DRIB\t\tBIT(2)\n+#define DMA_RX_ERR_MII\t\tBIT(3)\n+#define DMA_RX_EV2\t\tBIT(5)\n+#define DMA_RX_ERR_COL\t\tBIT(6)\n+#define DMA_RX_LONG\t\tBIT(7)\n+#define DMA_RX_LS\t\tBIT(8)\t/* last descriptor */\n+#define DMA_RX_FS\t\tBIT(9)\t/* first descriptor */\n+#define DMA_RX_MF\t\tBIT(10)\t/* multicast frame */\n+#define DMA_RX_ERR_RUNT\t\tBIT(11)\t/* runt frame */\n+#define DMA_RX_ERR_LENGTH\tBIT(12)\t/* length error */\n+#define DMA_RX_ERR_DESC\t\tBIT(14)\t/* descriptor error */\n+#define DMA_RX_ERROR\t\tBIT(15)\t/* error summary */\n+#define DMA_RX_LEN_MASK\t\t0x3fff0000\n+#define DMA_RX_LEN_SHIFT\t16\n+#define DMA_RX_FILT\t\tBIT(30)\n+#define DMA_RX_OWN\t\tBIT(31)\t/* desc owned by DMA controller */\n+\n+#define DMA_RX1_BSIZE_MASK\t0x000007ff\n+#define DMA_RX1_BSIZE_SHIFT\t0\n+#define DMA_RX1_CHAINED\t\tBIT(24)\n+#define DMA_RX1_RER\t\tBIT(25)\n+\n+#define DMA_TX_ERR_UNDER\tBIT(1)\t/* underflow error */\n+#define DMA_TX_ERR_DEFER\tBIT(2)\t/* excessive deferral */\n+#define DMA_TX_COL_MASK\t\t0x78\n+#define DMA_TX_COL_SHIFT\t3\n+#define DMA_TX_ERR_HB\t\tBIT(7)\t/* hearbeat failure */\n+#define DMA_TX_ERR_COL\t\tBIT(8)\t/* excessive collisions */\n+#define DMA_TX_ERR_LATE\t\tBIT(9)\t/* late collision */\n+#define DMA_TX_ERR_LINK\t\tBIT(10)\t/* no carrier */\n+#define DMA_TX_ERR_LOSS\t\tBIT(11)\t/* loss of carrier */\n+#define DMA_TX_ERR_JABBER\tBIT(14)\t/* transmit jabber timeout */\n+#define DMA_TX_ERROR\t\tBIT(15)\t/* frame aborted */\n+#define DMA_TX_OWN\t\tBIT(31)\t/* descr owned by DMA controller */\n+\n+#define DMA_TX1_BSIZE_MASK\t0x000007ff\n+#define DMA_TX1_BSIZE_SHIFT\t0\n+#define DMA_TX1_CHAINED\t\tBIT(24)\t/* chained descriptors */\n+#define DMA_TX1_TER\t\tBIT(25)\t/* transmit end of ring */\n+#define DMA_TX1_FS\t\tBIT(29)\t/* first segment */\n+#define DMA_TX1_LS\t\tBIT(30)\t/* last segment */\n+#define DMA_TX1_IC\t\tBIT(31)\t/* interrupt on completion */\n+\n+#define RCVPKT_LENGTH(X)\t(X  >> 16)\t/* Received pkt Length */\n+\n+#define MAC_CONTROL_RE\t\tBIT(2)\t/* receive enable */\n+#define MAC_CONTROL_TE\t\tBIT(3)\t/* transmit enable */\n+#define MAC_CONTROL_DC\t\tBIT(5)\t/* Deferral check */\n+#define MAC_CONTROL_ASTP\tBIT(8)\t/* Auto pad strip */\n+#define MAC_CONTROL_DRTY\tBIT(10)\t/* Disable retry */\n+#define MAC_CONTROL_DBF\t\tBIT(11)\t/* Disable bcast frames */\n+#define MAC_CONTROL_LCC\t\tBIT(12)\t/* late collision ctrl */\n+#define MAC_CONTROL_HP\t\tBIT(13)\t/* Hash Perfect filtering */\n+#define MAC_CONTROL_HASH\tBIT(14)\t/* Unicast hash filtering */\n+#define MAC_CONTROL_HO\t\tBIT(15)\t/* Hash only filtering */\n+#define MAC_CONTROL_PB\t\tBIT(16)\t/* Pass Bad frames */\n+#define MAC_CONTROL_IF\t\tBIT(17)\t/* Inverse filtering */\n+#define MAC_CONTROL_PR\t\tBIT(18)\t/* promis mode (valid frames only) */\n+#define MAC_CONTROL_PM\t\tBIT(19)\t/* pass multicast */\n+#define MAC_CONTROL_F\t\tBIT(20)\t/* full-duplex */\n+#define MAC_CONTROL_DRO\t\tBIT(23)\t/* Disable Receive Own */\n+#define MAC_CONTROL_HBD\t\tBIT(28)\t/* heart-beat disabled (MUST BE SET) */\n+#define MAC_CONTROL_BLE\t\tBIT(30)\t/* big endian mode */\n+#define MAC_CONTROL_RA\t\tBIT(31)\t/* rcv all (valid and invalid frames) */\n+\n+#define MII_ADDR_BUSY\t\tBIT(0)\n+#define MII_ADDR_WRITE\t\tBIT(1)\n+#define MII_ADDR_REG_SHIFT\t6\n+#define MII_ADDR_PHY_SHIFT\t11\n+#define MII_DATA_SHIFT\t\t0\n+\n+#define FLOW_CONTROL_FCE\tBIT(1)\n+\n+#define DMA_BUS_MODE_SWR\tBIT(0)\t/* software reset */\n+#define DMA_BUS_MODE_BLE\tBIT(7)\t/* big endian mode */\n+#define DMA_BUS_MODE_PBL_SHIFT\t8\t/* programmable burst length 32 */\n+#define DMA_BUS_MODE_DBO\tBIT(20)\t/* big-endian descriptors */\n+\n+#define DMA_STATUS_TI\t\tBIT(0)\t/* transmit interrupt */\n+#define DMA_STATUS_TPS\t\tBIT(1)\t/* transmit process stopped */\n+#define DMA_STATUS_TU\t\tBIT(2)\t/* transmit buffer unavailable */\n+#define DMA_STATUS_TJT\t\tBIT(3)\t/* transmit buffer timeout */\n+#define DMA_STATUS_UNF\t\tBIT(5)\t/* transmit underflow */\n+#define DMA_STATUS_RI\t\tBIT(6)\t/* receive interrupt */\n+#define DMA_STATUS_RU\t\tBIT(7)\t/* receive buffer unavailable */\n+#define DMA_STATUS_RPS\t\tBIT(8)\t/* receive process stopped */\n+#define DMA_STATUS_ETI\t\tBIT(10)\t/* early transmit interrupt */\n+#define DMA_STATUS_FBE\t\tBIT(13)\t/* fatal bus interrupt */\n+#define DMA_STATUS_ERI\t\tBIT(14)\t/* early receive interrupt */\n+#define DMA_STATUS_AIS\t\tBIT(15)\t/* abnormal interrupt summary */\n+#define DMA_STATUS_NIS\t\tBIT(16)\t/* normal interrupt summary */\n+#define DMA_STATUS_RS_SHIFT\t17\t/* receive process state */\n+#define DMA_STATUS_TS_SHIFT\t20\t/* transmit process state */\n+#define DMA_STATUS_EB_SHIFT\t23\t/* error bits */\n+\n+#define DMA_CONTROL_SR\t\tBIT(1)\t/* start receive */\n+#define DMA_CONTROL_ST\t\tBIT(13)\t/* start transmit */\n+#define DMA_CONTROL_SF\t\tBIT(21)\t/* store and forward */\n+\n+typedef struct {\n+\tvolatile unsigned int status;\t/* OWN, Device control and status. */\n+\tvolatile unsigned int devcs;\t/* pkt Control bits + Length */\n+\tvolatile unsigned int addr;\t/* Current Address. */\n+\tvolatile unsigned int descr;\t/* Next descriptor in chain. */\n+} ar231x_descr_t;\n+\n+/**\n+ * New Combo structure for Both Eth0 AND eth1\n+ *\n+ * Don't directly access MII related regs since phy chip could be actually\n+ * connected to another ethernet block.\n+ */\n+typedef struct {\n+\tvolatile unsigned int mac_control;\t/* 0x00 */\n+\tvolatile unsigned int mac_addr[2];\t/* 0x04 - 0x08 */\n+\tvolatile unsigned int mcast_table[2];\t/* 0x0c - 0x10 */\n+\tvolatile unsigned int __mii_addr;\t/* 0x14 */\n+\tvolatile unsigned int __mii_data;\t/* 0x18 */\n+\tvolatile unsigned int flow_control;\t/* 0x1c */\n+\tvolatile unsigned int vlan_tag;\t/* 0x20 */\n+\tvolatile unsigned int pad[7];\t/* 0x24 - 0x3c */\n+\tvolatile unsigned int ucast_table[8];\t/* 0x40-0x5c */\n+} ETHERNET_STRUCT;\n+\n+typedef struct {\n+\tvolatile unsigned int mii_addr;\n+\tvolatile unsigned int mii_data;\n+} MII;\n+\n+/********************************************************************\n+ * Interrupt controller\n+ ********************************************************************/\n+\n+typedef struct {\n+\tvolatile unsigned int wdog_control;\t/* 0x08 */\n+\tvolatile unsigned int wdog_timer;\t/* 0x0c */\n+\tvolatile unsigned int misc_status;\t/* 0x10 */\n+\tvolatile unsigned int misc_mask;\t/* 0x14 */\n+\tvolatile unsigned int global_status;\t/* 0x18 */\n+\tvolatile unsigned int reserved;\t/* 0x1c */\n+\tvolatile unsigned int reset_control;\t/* 0x20 */\n+} INTERRUPT;\n+\n+/********************************************************************\n+ * DMA controller\n+ ********************************************************************/\n+typedef struct {\n+\tvolatile unsigned int bus_mode;\t/* 0x00 (CSR0) */\n+\tvolatile unsigned int xmt_poll;\t/* 0x04 (CSR1) */\n+\tvolatile unsigned int rcv_poll;\t/* 0x08 (CSR2) */\n+\tvolatile unsigned int rcv_base;\t/* 0x0c (CSR3) */\n+\tvolatile unsigned int xmt_base;\t/* 0x10 (CSR4) */\n+\tvolatile unsigned int status;\t/* 0x14 (CSR5) */\n+\tvolatile unsigned int control;\t/* 0x18 (CSR6) */\n+\tvolatile unsigned int intr_ena;\t/* 0x1c (CSR7) */\n+\tvolatile unsigned int rcv_missed;\t/* 0x20 (CSR8) */\n+\tvolatile unsigned int reserved[11];\t/* 0x24-0x4c (CSR9-19) */\n+\tvolatile unsigned int cur_tx_buf_addr;\t/* 0x50 (CSR20) */\n+\tvolatile unsigned int cur_rx_buf_addr;\t/* 0x50 (CSR21) */\n+} DMA;\n+\n+/**\n+ * Struct private for the Sibyte.\n+ *\n+ * Elements are grouped so variables used by the tx handling goes\n+ * together, and will go into the same cache lines etc. in order to\n+ * avoid cache line contention between the rx and tx handling on SMP.\n+ *\n+ * Frequently accessed variables are put at the beginning of the\n+ * struct to help the compiler generate better/shorter code.\n+ */\n+struct ar231x_private {\n+\tstruct net_device *dev;\n+\tstruct platform_device *pdev;\n+\tint version;\n+\tu32 mb[2];\n+\n+\tvolatile MII *phy_regs;\n+\tvolatile ETHERNET_STRUCT *eth_regs;\n+\tvolatile DMA *dma_regs;\n+\tstruct ar231x_eth *cfg;\n+\n+\tspinlock_t lock;\t\t\t/* Serialise access to device */\n+\n+\t/* RX and TX descriptors, must be adjacent */\n+\tar231x_descr_t *rx_ring;\n+\tar231x_descr_t *tx_ring;\n+\n+\tstruct sk_buff **rx_skb;\n+\tstruct sk_buff **tx_skb;\n+\n+\t/* RX elements */\n+\tu32 rx_skbprd;\n+\tu32 cur_rx;\n+\n+\t/* TX elements */\n+\tu32 tx_prd;\n+\tu32 tx_csm;\n+\n+\t/* Misc elements */\n+\tchar name[48];\n+\tstruct {\n+\t\tu32 address;\n+\t\tu32 length;\n+\t\tchar *mapping;\n+\t} desc;\n+\n+\tunsigned short link;\t\t/* 0 - link down, 1 - link up */\n+\tunsigned short duplex;\t\t/* 0 - half, 1 - full */\n+\n+\tstruct tasklet_struct rx_tasklet;\n+\tint unloading;\n+\n+\tstruct phy_device *phy_dev;\n+\tstruct mii_bus *mii_bus;\n+};\n+\n+/* Prototypes */\n+static int ar231x_init(struct net_device *dev);\n+#ifdef TX_TIMEOUT\n+static void ar231x_tx_timeout(struct net_device *dev);\n+#endif\n+static int ar231x_restart(struct net_device *dev);\n+static void ar231x_load_rx_ring(struct net_device *dev, int bufs);\n+static irqreturn_t ar231x_interrupt(int irq, void *dev_id);\n+static int ar231x_open(struct net_device *dev);\n+static int ar231x_start_xmit(struct sk_buff *skb, struct net_device *dev);\n+static int ar231x_close(struct net_device *dev);\n+static int ar231x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd);\n+static void ar231x_init_cleanup(struct net_device *dev);\n+\n+#endif\t/* _AR2313_H_ */\n--- a/arch/mips/ath25/ar2315_regs.h\n+++ b/arch/mips/ath25/ar2315_regs.h\n@@ -57,6 +57,9 @@\n #define AR2315_PCI_EXT_BASE\t0x80000000\t/* PCI external */\n #define AR2315_PCI_EXT_SIZE\t0x40000000\n \n+/* MII registers offset inside Ethernet MMR region */\n+#define AR2315_ENET0_MII_BASE\t(AR2315_ENET0_BASE + 0x14)\n+\n /*\n  * Configuration registers\n  */\n--- a/arch/mips/ath25/ar5312_regs.h\n+++ b/arch/mips/ath25/ar5312_regs.h\n@@ -64,6 +64,10 @@\n #define AR5312_AR5312_REV7\t0x0057\t\t/* AR5312 WMAC (AP30-040) */\n #define AR5312_AR2313_REV8\t0x0058\t\t/* AR2313 WMAC (AP43-030) */\n \n+/* MII registers offset inside Ethernet MMR region */\n+#define AR5312_ENET0_MII_BASE\t(AR5312_ENET0_BASE + 0x14)\n+#define AR5312_ENET1_MII_BASE\t(AR5312_ENET1_BASE + 0x14)\n+\n /* Reset/Timer Block Address Map */\n #define AR5312_TIMER\t\t0x0000 /* countdown timer */\n #define AR5312_RELOAD\t\t0x0004 /* timer reload value */\n--- a/arch/mips/ath25/ar2315.c\n+++ b/arch/mips/ath25/ar2315.c\n@@ -132,6 +132,8 @@ static void ar2315_irq_dispatch(void)\n \n \tif (pending & CAUSEF_IP3)\n \t\tdo_IRQ(AR2315_IRQ_WLAN0);\n+\telse if (pending & CAUSEF_IP4)\n+\t\tdo_IRQ(AR2315_IRQ_ENET0);\n #ifdef CONFIG_PCI_AR2315\n \telse if (pending & CAUSEF_IP5)\n \t\tdo_IRQ(AR2315_IRQ_LCBUS_PCI);\n@@ -167,6 +169,29 @@ void __init ar2315_arch_init_irq(void)\n \tar2315_misc_irq_domain = domain;\n }\n \n+static void ar2315_device_reset_set(u32 mask)\n+{\n+\tu32 val;\n+\n+\tval = ar2315_rst_reg_read(AR2315_RESET);\n+\tar2315_rst_reg_write(AR2315_RESET, val | mask);\n+}\n+\n+static void ar2315_device_reset_clear(u32 mask)\n+{\n+\tu32 val;\n+\n+\tval = ar2315_rst_reg_read(AR2315_RESET);\n+\tar2315_rst_reg_write(AR2315_RESET, val & ~mask);\n+}\n+\n+static struct ar231x_eth ar2315_eth_data = {\n+\t.reset_set = ar2315_device_reset_set,\n+\t.reset_clear = ar2315_device_reset_clear,\n+\t.reset_mac = AR2315_RESET_ENET0,\n+\t.reset_phy = AR2315_RESET_EPHY0,\n+};\n+\n static struct resource ar2315_gpio_res[] = {\n \t{\n \t\t.name = \"ar2315-gpio\",\n@@ -203,6 +228,11 @@ void __init ar2315_init_devices(void)\n \tar2315_gpio_res[1].end = ar2315_gpio_res[1].start;\n \tplatform_device_register(&ar2315_gpio);\n \n+\tar2315_eth_data.macaddr = ath25_board.config->enet0_mac;\n+\tath25_add_ethernet(0, AR2315_ENET0_BASE, \"eth0_mii\",\n+\t\t\t   AR2315_ENET0_MII_BASE, AR2315_IRQ_ENET0,\n+\t\t\t   &ar2315_eth_data);\n+\n \tath25_add_wmac(0, AR2315_WLAN0_BASE, AR2315_IRQ_WLAN0);\n }\n \n--- a/arch/mips/ath25/ar5312.c\n+++ b/arch/mips/ath25/ar5312.c\n@@ -128,6 +128,10 @@ static void ar5312_irq_dispatch(void)\n \n \tif (pending & CAUSEF_IP2)\n \t\tdo_IRQ(AR5312_IRQ_WLAN0);\n+\telse if (pending & CAUSEF_IP3)\n+\t\tdo_IRQ(AR5312_IRQ_ENET0);\n+\telse if (pending & CAUSEF_IP4)\n+\t\tdo_IRQ(AR5312_IRQ_ENET1);\n \telse if (pending & CAUSEF_IP5)\n \t\tdo_IRQ(AR5312_IRQ_WLAN1);\n \telse if (pending & CAUSEF_IP6)\n@@ -161,6 +165,36 @@ void __init ar5312_arch_init_irq(void)\n \tar5312_misc_irq_domain = domain;\n }\n \n+static void ar5312_device_reset_set(u32 mask)\n+{\n+\tu32 val;\n+\n+\tval = ar5312_rst_reg_read(AR5312_RESET);\n+\tar5312_rst_reg_write(AR5312_RESET, val | mask);\n+}\n+\n+static void ar5312_device_reset_clear(u32 mask)\n+{\n+\tu32 val;\n+\n+\tval = ar5312_rst_reg_read(AR5312_RESET);\n+\tar5312_rst_reg_write(AR5312_RESET, val & ~mask);\n+}\n+\n+static struct ar231x_eth ar5312_eth0_data = {\n+\t.reset_set = ar5312_device_reset_set,\n+\t.reset_clear = ar5312_device_reset_clear,\n+\t.reset_mac = AR5312_RESET_ENET0,\n+\t.reset_phy = AR5312_RESET_EPHY0,\n+};\n+\n+static struct ar231x_eth ar5312_eth1_data = {\n+\t.reset_set = ar5312_device_reset_set,\n+\t.reset_clear = ar5312_device_reset_clear,\n+\t.reset_mac = AR5312_RESET_ENET1,\n+\t.reset_phy = AR5312_RESET_EPHY1,\n+};\n+\n static struct physmap_flash_data ar5312_flash_data = {\n \t.width = 2,\n };\n@@ -241,6 +275,7 @@ static void __init ar5312_flash_init(voi\n void __init ar5312_init_devices(void)\n {\n \tstruct ath25_boarddata *config;\n+\tu8 *c;\n \n \tar5312_flash_init();\n \n@@ -264,8 +299,30 @@ void __init ar5312_init_devices(void)\n \n \tplatform_device_register(&ar5312_gpio);\n \n+\t/* Fix up MAC addresses if necessary */\n+\tif (is_broadcast_ether_addr(config->enet0_mac))\n+\t\tether_addr_copy(config->enet0_mac, config->enet1_mac);\n+\n+\t/* If ENET0 and ENET1 have the same mac address,\n+\t * increment the one from ENET1 */\n+\tif (ether_addr_equal(config->enet0_mac, config->enet1_mac)) {\n+\t\tc = config->enet1_mac + 5;\n+\t\twhile ((c >= config->enet1_mac) && !(++(*c)))\n+\t\t\tc--;\n+\t}\n+\n \tswitch (ath25_soc) {\n \tcase ATH25_SOC_AR5312:\n+\t\tar5312_eth0_data.macaddr = config->enet0_mac;\n+\t\tath25_add_ethernet(0, AR5312_ENET0_BASE, \"eth0_mii\",\n+\t\t\t\t   AR5312_ENET0_MII_BASE, AR5312_IRQ_ENET0,\n+\t\t\t\t   &ar5312_eth0_data);\n+\n+\t\tar5312_eth1_data.macaddr = config->enet1_mac;\n+\t\tath25_add_ethernet(1, AR5312_ENET1_BASE, \"eth1_mii\",\n+\t\t\t\t   AR5312_ENET1_MII_BASE, AR5312_IRQ_ENET1,\n+\t\t\t\t   &ar5312_eth1_data);\n+\n \t\tif (!ath25_board.radio)\n \t\t\treturn;\n \n@@ -274,8 +331,18 @@ void __init ar5312_init_devices(void)\n \n \t\tath25_add_wmac(0, AR5312_WLAN0_BASE, AR5312_IRQ_WLAN0);\n \t\tbreak;\n+\t/*\n+\t * AR2312/3 ethernet uses the PHY of ENET0, but the MAC\n+\t * of ENET1. Atheros calls it 'twisted' for a reason :)\n+\t */\n \tcase ATH25_SOC_AR2312:\n \tcase ATH25_SOC_AR2313:\n+\t\tar5312_eth1_data.reset_phy = ar5312_eth0_data.reset_phy;\n+\t\tar5312_eth1_data.macaddr = config->enet0_mac;\n+\t\tath25_add_ethernet(1, AR5312_ENET1_BASE, \"eth0_mii\",\n+\t\t\t\t   AR5312_ENET0_MII_BASE, AR5312_IRQ_ENET1,\n+\t\t\t\t   &ar5312_eth1_data);\n+\n \t\tif (!ath25_board.radio)\n \t\t\treturn;\n \t\tbreak;\n--- a/arch/mips/ath25/devices.h\n+++ b/arch/mips/ath25/devices.h\n@@ -33,6 +33,8 @@ extern struct ar231x_board_config ath25_\n extern void (*ath25_irq_dispatch)(void);\n \n int ath25_find_config(phys_addr_t offset, unsigned long size);\n+int ath25_add_ethernet(int nr, u32 base, const char *mii_name, u32 mii_base,\n+\t\t       int irq, void *pdata);\n void ath25_serial_setup(u32 mapbase, int irq, unsigned int uartclk);\n int ath25_add_wmac(int nr, u32 base, int irq);\n \n--- a/arch/mips/ath25/devices.c\n+++ b/arch/mips/ath25/devices.c\n@@ -13,6 +13,51 @@\n struct ar231x_board_config ath25_board;\n enum ath25_soc_type ath25_soc = ATH25_SOC_UNKNOWN;\n \n+static struct resource ath25_eth0_res[] = {\n+\t{\n+\t\t.name = \"eth0_membase\",\n+\t\t.flags = IORESOURCE_MEM,\n+\t},\n+\t{\n+\t\t.name = \"eth0_mii\",\n+\t\t.flags = IORESOURCE_MEM,\n+\t},\n+\t{\n+\t\t.name = \"eth0_irq\",\n+\t\t.flags = IORESOURCE_IRQ,\n+\t}\n+};\n+\n+static struct resource ath25_eth1_res[] = {\n+\t{\n+\t\t.name = \"eth1_membase\",\n+\t\t.flags = IORESOURCE_MEM,\n+\t},\n+\t{\n+\t\t.name = \"eth1_mii\",\n+\t\t.flags = IORESOURCE_MEM,\n+\t},\n+\t{\n+\t\t.name = \"eth1_irq\",\n+\t\t.flags = IORESOURCE_IRQ,\n+\t}\n+};\n+\n+static struct platform_device ath25_eth[] = {\n+\t{\n+\t\t.id = 0,\n+\t\t.name = \"ar231x-eth\",\n+\t\t.resource = ath25_eth0_res,\n+\t\t.num_resources = ARRAY_SIZE(ath25_eth0_res)\n+\t},\n+\t{\n+\t\t.id = 1,\n+\t\t.name = \"ar231x-eth\",\n+\t\t.resource = ath25_eth1_res,\n+\t\t.num_resources = ARRAY_SIZE(ath25_eth1_res)\n+\t}\n+};\n+\n static struct resource ath25_wmac0_res[] = {\n \t{\n \t\t.name = \"wmac0_membase\",\n@@ -71,6 +116,25 @@ const char *get_system_type(void)\n \treturn soc_type_strings[ath25_soc];\n }\n \n+int __init ath25_add_ethernet(int nr, u32 base, const char *mii_name,\n+\t\t\t      u32 mii_base, int irq, void *pdata)\n+{\n+\tstruct resource *res;\n+\n+\tath25_eth[nr].dev.platform_data = pdata;\n+\tres = &ath25_eth[nr].resource[0];\n+\tres->start = base;\n+\tres->end = base + 0x2000 - 1;\n+\tres++;\n+\tres->name = mii_name;\n+\tres->start = mii_base;\n+\tres->end = mii_base + 8 - 1;\n+\tres++;\n+\tres->start = irq;\n+\tres->end = irq;\n+\treturn platform_device_register(&ath25_eth[nr]);\n+}\n+\n void __init ath25_serial_setup(u32 mapbase, int irq, unsigned int uartclk)\n {\n #ifdef CONFIG_SERIAL_8250_CONSOLE\n--- a/arch/mips/include/asm/mach-ath25/ath25_platform.h\n+++ b/arch/mips/include/asm/mach-ath25/ath25_platform.h\n@@ -71,4 +71,15 @@ struct ar231x_board_config {\n \tconst char *radio;\n };\n \n+/*\n+ * Platform device information for the Ethernet MAC\n+ */\n+struct ar231x_eth {\n+\tvoid (*reset_set)(u32);\n+\tvoid (*reset_clear)(u32);\n+\tu32 reset_mac;\n+\tu32 reset_phy;\n+\tchar *macaddr;\n+};\n+\n #endif /* __ASM_MACH_ATH25_PLATFORM_H */\n"
  },
  {
    "path": "target/linux/ath25/patches-5.10/120-spiflash.patch",
    "content": "--- a/drivers/mtd/devices/Kconfig\n+++ b/drivers/mtd/devices/Kconfig\n@@ -114,6 +114,10 @@ config MTD_BCM47XXSFLASH\n \t  registered by bcma as platform devices. This enables driver for\n \t  serial flash memories.\n \n+config MTD_AR2315\n+\ttristate \"Atheros AR2315+ SPI Flash support\"\n+\tdepends on SOC_AR2315\n+\n config MTD_SLRAM\n \ttristate \"Uncached system RAM\"\n \thelp\n--- a/drivers/mtd/devices/Makefile\n+++ b/drivers/mtd/devices/Makefile\n@@ -15,6 +15,7 @@ obj-$(CONFIG_MTD_DATAFLASH)\t+= mtd_dataf\n obj-$(CONFIG_MTD_MCHP23K256)\t+= mchp23k256.o\n obj-$(CONFIG_MTD_SPEAR_SMI)\t+= spear_smi.o\n obj-$(CONFIG_MTD_SST25L)\t+= sst25l.o\n+obj-$(CONFIG_MTD_AR2315)\t+= ar2315.o\n obj-$(CONFIG_MTD_BCM47XXSFLASH)\t+= bcm47xxsflash.o\n obj-$(CONFIG_MTD_ST_SPI_FSM)    += st_spi_fsm.o\n obj-$(CONFIG_MTD_POWERNV_FLASH)\t+= powernv_flash.o\n--- /dev/null\n+++ b/drivers/mtd/devices/ar2315.c\n@@ -0,0 +1,456 @@\n+\n+/*\n+ * MTD driver for the SPI Flash Memory support on Atheros AR2315\n+ *\n+ * Copyright (c) 2005-2006 Atheros Communications Inc.\n+ * Copyright (C) 2006-2007 FON Technology, SL.\n+ * Copyright (C) 2006-2007 Imre Kaloz <kaloz@openwrt.org>\n+ * Copyright (C) 2006-2009 Felix Fietkau <nbd@nbd.name>\n+ * Copyright (C) 2012 Alexandros C. Couloumbis <alex@ozo.com>\n+ *\n+ * This code is free software; you can redistribute it and/or modify\n+ * it under the terms of the GNU General Public License version 2 as\n+ * published by the Free Software Foundation.\n+ *\n+ */\n+\n+#include <linux/kernel.h>\n+#include <linux/module.h>\n+#include <linux/types.h>\n+#include <linux/errno.h>\n+#include <linux/slab.h>\n+#include <linux/mtd/mtd.h>\n+#include <linux/mtd/partitions.h>\n+#include <linux/platform_device.h>\n+#include <linux/sched.h>\n+#include <linux/delay.h>\n+#include <linux/io.h>\n+#include <linux/mutex.h>\n+\n+#include \"ar2315_spiflash.h\"\n+\n+#define DRIVER_NAME \"ar2315-spiflash\"\n+\n+#define busy_wait(_priv, _condition, _wait) do { \\\n+\twhile (_condition) { \\\n+\t\tif (_wait > 1) \\\n+\t\t\tmsleep(_wait); \\\n+\t\telse if ((_wait == 1) && need_resched()) \\\n+\t\t\tschedule(); \\\n+\t\telse \\\n+\t\t\tudelay(1); \\\n+\t} \\\n+} while (0)\n+\n+enum {\n+\tFLASH_NONE,\n+\tFLASH_1MB,\n+\tFLASH_2MB,\n+\tFLASH_4MB,\n+\tFLASH_8MB,\n+\tFLASH_16MB,\n+};\n+\n+/* Flash configuration table */\n+struct flashconfig {\n+\tu32 byte_cnt;\n+\tu32 sector_cnt;\n+\tu32 sector_size;\n+};\n+\n+static const struct flashconfig flashconfig_tbl[] = {\n+\t[FLASH_NONE] = { 0, 0, 0},\n+\t[FLASH_1MB]  = { STM_1MB_BYTE_COUNT, STM_1MB_SECTOR_COUNT,\n+\t\t\t STM_1MB_SECTOR_SIZE},\n+\t[FLASH_2MB]  = { STM_2MB_BYTE_COUNT, STM_2MB_SECTOR_COUNT,\n+\t\t\t STM_2MB_SECTOR_SIZE},\n+\t[FLASH_4MB]  = { STM_4MB_BYTE_COUNT, STM_4MB_SECTOR_COUNT,\n+\t\t\t STM_4MB_SECTOR_SIZE},\n+\t[FLASH_8MB]  = { STM_8MB_BYTE_COUNT, STM_8MB_SECTOR_COUNT,\n+\t\t\t STM_8MB_SECTOR_SIZE},\n+\t[FLASH_16MB] = { STM_16MB_BYTE_COUNT, STM_16MB_SECTOR_COUNT,\n+\t\t\t STM_16MB_SECTOR_SIZE}\n+};\n+\n+/* Mapping of generic opcodes to STM serial flash opcodes */\n+enum {\n+\tSPI_WRITE_ENABLE,\n+\tSPI_WRITE_DISABLE,\n+\tSPI_RD_STATUS,\n+\tSPI_WR_STATUS,\n+\tSPI_RD_DATA,\n+\tSPI_FAST_RD_DATA,\n+\tSPI_PAGE_PROGRAM,\n+\tSPI_SECTOR_ERASE,\n+\tSPI_BULK_ERASE,\n+\tSPI_DEEP_PWRDOWN,\n+\tSPI_RD_SIG,\n+};\n+\n+struct opcodes {\n+\t__u16 code;\n+\t__s8 tx_cnt;\n+\t__s8 rx_cnt;\n+};\n+\n+static const struct opcodes stm_opcodes[] = {\n+\t[SPI_WRITE_ENABLE] = {STM_OP_WR_ENABLE, 1, 0},\n+\t[SPI_WRITE_DISABLE] = {STM_OP_WR_DISABLE, 1, 0},\n+\t[SPI_RD_STATUS] = {STM_OP_RD_STATUS, 1, 1},\n+\t[SPI_WR_STATUS] = {STM_OP_WR_STATUS, 1, 0},\n+\t[SPI_RD_DATA] = {STM_OP_RD_DATA, 4, 4},\n+\t[SPI_FAST_RD_DATA] = {STM_OP_FAST_RD_DATA, 5, 0},\n+\t[SPI_PAGE_PROGRAM] = {STM_OP_PAGE_PGRM, 8, 0},\n+\t[SPI_SECTOR_ERASE] = {STM_OP_SECTOR_ERASE, 4, 0},\n+\t[SPI_BULK_ERASE] = {STM_OP_BULK_ERASE, 1, 0},\n+\t[SPI_DEEP_PWRDOWN] = {STM_OP_DEEP_PWRDOWN, 1, 0},\n+\t[SPI_RD_SIG] = {STM_OP_RD_SIG, 4, 1},\n+};\n+\n+/* Driver private data structure */\n+struct spiflash_priv {\n+\tstruct mtd_info mtd;\n+\tvoid __iomem *readaddr; /* memory mapped data for read  */\n+\tvoid __iomem *mmraddr;  /* memory mapped register space */\n+\tstruct mutex lock;\t/* serialize registers access */\n+};\n+\n+#define to_spiflash(_mtd) container_of(_mtd, struct spiflash_priv, mtd)\n+\n+enum {\n+\tFL_READY,\n+\tFL_READING,\n+\tFL_ERASING,\n+\tFL_WRITING\n+};\n+\n+/*****************************************************************************/\n+\n+static u32\n+spiflash_read_reg(struct spiflash_priv *priv, int reg)\n+{\n+\treturn ioread32(priv->mmraddr + reg);\n+}\n+\n+static void\n+spiflash_write_reg(struct spiflash_priv *priv, int reg, u32 data)\n+{\n+\tiowrite32(data, priv->mmraddr + reg);\n+}\n+\n+static u32\n+spiflash_wait_busy(struct spiflash_priv *priv)\n+{\n+\tu32 reg;\n+\n+\tbusy_wait(priv, (reg = spiflash_read_reg(priv, SPI_FLASH_CTL)) &\n+\t\tSPI_CTL_BUSY, 0);\n+\treturn reg;\n+}\n+\n+static u32\n+spiflash_sendcmd(struct spiflash_priv *priv, int opcode, u32 addr)\n+{\n+\tconst struct opcodes *op;\n+\tu32 reg, mask;\n+\n+\top = &stm_opcodes[opcode];\n+\treg = spiflash_wait_busy(priv);\n+\tspiflash_write_reg(priv, SPI_FLASH_OPCODE,\n+\t\t\t   ((u32)op->code) | (addr << 8));\n+\n+\treg &= ~SPI_CTL_TX_RX_CNT_MASK;\n+\treg |= SPI_CTL_START | op->tx_cnt | (op->rx_cnt << 4);\n+\n+\tspiflash_write_reg(priv, SPI_FLASH_CTL, reg);\n+\tspiflash_wait_busy(priv);\n+\n+\tif (!op->rx_cnt)\n+\t\treturn 0;\n+\n+\treg = spiflash_read_reg(priv, SPI_FLASH_DATA);\n+\n+\tswitch (op->rx_cnt) {\n+\tcase 1:\n+\t\tmask = 0x000000ff;\n+\t\tbreak;\n+\tcase 2:\n+\t\tmask = 0x0000ffff;\n+\t\tbreak;\n+\tcase 3:\n+\t\tmask = 0x00ffffff;\n+\t\tbreak;\n+\tdefault:\n+\t\tmask = 0xffffffff;\n+\t\tbreak;\n+\t}\n+\treg &= mask;\n+\n+\treturn reg;\n+}\n+\n+/*\n+ * Probe SPI flash device\n+ * Function returns 0 for failure.\n+ * and flashconfig_tbl array index for success.\n+ */\n+static int\n+spiflash_probe_chip(struct platform_device *pdev, struct spiflash_priv *priv)\n+{\n+\tu32 sig = spiflash_sendcmd(priv, SPI_RD_SIG, 0);\n+\tint flash_size;\n+\n+\tswitch (sig) {\n+\tcase STM_8MBIT_SIGNATURE:\n+\t\tflash_size = FLASH_1MB;\n+\t\tbreak;\n+\tcase STM_16MBIT_SIGNATURE:\n+\t\tflash_size = FLASH_2MB;\n+\t\tbreak;\n+\tcase STM_32MBIT_SIGNATURE:\n+\t\tflash_size = FLASH_4MB;\n+\t\tbreak;\n+\tcase STM_64MBIT_SIGNATURE:\n+\t\tflash_size = FLASH_8MB;\n+\t\tbreak;\n+\tcase STM_128MBIT_SIGNATURE:\n+\t\tflash_size = FLASH_16MB;\n+\t\tbreak;\n+\tdefault:\n+\t\tdev_warn(&pdev->dev, \"read of flash device signature failed!\\n\");\n+\t\treturn 0;\n+\t}\n+\n+\treturn flash_size;\n+}\n+\n+static void\n+spiflash_wait_complete(struct spiflash_priv *priv, unsigned int timeout)\n+{\n+\tbusy_wait(priv, spiflash_sendcmd(priv, SPI_RD_STATUS, 0) &\n+\t\tSPI_STATUS_WIP, timeout);\n+}\n+\n+static int\n+spiflash_erase(struct mtd_info *mtd, struct erase_info *instr)\n+{\n+\tstruct spiflash_priv *priv = to_spiflash(mtd);\n+\tconst struct opcodes *op;\n+\tu32 temp, reg;\n+\n+\tif (instr->addr + instr->len > mtd->size)\n+\t\treturn -EINVAL;\n+\n+\tmutex_lock(&priv->lock);\n+\n+\tspiflash_sendcmd(priv, SPI_WRITE_ENABLE, 0);\n+\treg = spiflash_wait_busy(priv);\n+\n+\top = &stm_opcodes[SPI_SECTOR_ERASE];\n+\ttemp = ((u32)instr->addr << 8) | (u32)(op->code);\n+\tspiflash_write_reg(priv, SPI_FLASH_OPCODE, temp);\n+\n+\treg &= ~SPI_CTL_TX_RX_CNT_MASK;\n+\treg |= op->tx_cnt | SPI_CTL_START;\n+\tspiflash_write_reg(priv, SPI_FLASH_CTL, reg);\n+\n+\tspiflash_wait_complete(priv, 20);\n+\n+\tmutex_unlock(&priv->lock);\n+\n+\treturn 0;\n+}\n+\n+static int\n+spiflash_read(struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen,\n+\t      u_char *buf)\n+{\n+\tstruct spiflash_priv *priv = to_spiflash(mtd);\n+\n+\tif (!len)\n+\t\treturn 0;\n+\n+\tif (from + len > mtd->size)\n+\t\treturn -EINVAL;\n+\n+\t*retlen = len;\n+\n+\tmutex_lock(&priv->lock);\n+\n+\tmemcpy_fromio(buf, priv->readaddr + from, len);\n+\n+\tmutex_unlock(&priv->lock);\n+\n+\treturn 0;\n+}\n+\n+static int\n+spiflash_write(struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen,\n+\t       const u8 *buf)\n+{\n+\tstruct spiflash_priv *priv = to_spiflash(mtd);\n+\tu32 opcode, bytes_left;\n+\n+\t*retlen = 0;\n+\n+\tif (!len)\n+\t\treturn 0;\n+\n+\tif (to + len > mtd->size)\n+\t\treturn -EINVAL;\n+\n+\tbytes_left = len;\n+\n+\tdo {\n+\t\tu32 read_len, reg, page_offset, spi_data = 0;\n+\n+\t\tread_len = min(bytes_left, sizeof(u32));\n+\n+\t\t/* 32-bit writes cannot span across a page boundary\n+\t\t * (256 bytes). This types of writes require two page\n+\t\t * program operations to handle it correctly. The STM part\n+\t\t * will write the overflow data to the beginning of the\n+\t\t * current page as opposed to the subsequent page.\n+\t\t */\n+\t\tpage_offset = (to & (STM_PAGE_SIZE - 1)) + read_len;\n+\n+\t\tif (page_offset > STM_PAGE_SIZE)\n+\t\t\tread_len -= (page_offset - STM_PAGE_SIZE);\n+\n+\t\tmutex_lock(&priv->lock);\n+\n+\t\tspiflash_sendcmd(priv, SPI_WRITE_ENABLE, 0);\n+\t\tspi_data = 0;\n+\t\tswitch (read_len) {\n+\t\tcase 4:\n+\t\t\tspi_data |= buf[3] << 24;\n+\t\t\t/* fall through */\n+\t\tcase 3:\n+\t\t\tspi_data |= buf[2] << 16;\n+\t\t\t/* fall through */\n+\t\tcase 2:\n+\t\t\tspi_data |= buf[1] << 8;\n+\t\t\t/* fall through */\n+\t\tcase 1:\n+\t\t\tspi_data |= buf[0] & 0xff;\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\tspiflash_write_reg(priv, SPI_FLASH_DATA, spi_data);\n+\t\topcode = stm_opcodes[SPI_PAGE_PROGRAM].code |\n+\t\t\t(to & 0x00ffffff) << 8;\n+\t\tspiflash_write_reg(priv, SPI_FLASH_OPCODE, opcode);\n+\n+\t\treg = spiflash_read_reg(priv, SPI_FLASH_CTL);\n+\t\treg &= ~SPI_CTL_TX_RX_CNT_MASK;\n+\t\treg |= (read_len + 4) | SPI_CTL_START;\n+\t\tspiflash_write_reg(priv, SPI_FLASH_CTL, reg);\n+\n+\t\tspiflash_wait_complete(priv, 1);\n+\n+\t\tmutex_unlock(&priv->lock);\n+\n+\t\tbytes_left -= read_len;\n+\t\tto += read_len;\n+\t\tbuf += read_len;\n+\n+\t\t*retlen += read_len;\n+\t} while (bytes_left != 0);\n+\n+\treturn 0;\n+}\n+\n+#if defined CONFIG_MTD_REDBOOT_PARTS || CONFIG_MTD_MYLOADER_PARTS\n+static const char * const part_probe_types[] = {\n+\t\"cmdlinepart\", \"RedBoot\", \"MyLoader\", NULL\n+};\n+#endif\n+\n+static int\n+spiflash_probe(struct platform_device *pdev)\n+{\n+\tstruct spiflash_priv *priv;\n+\tstruct mtd_info *mtd;\n+\tstruct resource *res;\n+\tint index;\n+\tint result = 0;\n+\n+\tpriv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);\n+\tif (!priv)\n+\t\treturn -ENOMEM;\n+\n+\tmutex_init(&priv->lock);\n+\tmtd = &priv->mtd;\n+\n+\tres = platform_get_resource(pdev, IORESOURCE_MEM, 1);\n+\tpriv->mmraddr = devm_ioremap_resource(&pdev->dev, res);\n+\tif (IS_ERR(priv->mmraddr)) {\n+\t\tdev_warn(&pdev->dev, \"failed to map flash MMR\\n\");\n+\t\treturn PTR_ERR(priv->mmraddr);\n+\t}\n+\n+\tindex = spiflash_probe_chip(pdev, priv);\n+\tif (!index) {\n+\t\tdev_warn(&pdev->dev, \"found no flash device\\n\");\n+\t\treturn -ENODEV;\n+\t}\n+\n+\tres = platform_get_resource(pdev, IORESOURCE_MEM, 0);\n+\tpriv->readaddr = devm_ioremap_resource(&pdev->dev, res);\n+\tif (IS_ERR(priv->readaddr)) {\n+\t\tdev_warn(&pdev->dev, \"failed to map flash read mem\\n\");\n+\t\treturn PTR_ERR(priv->readaddr);\n+\t}\n+\n+\tplatform_set_drvdata(pdev, priv);\n+\tmtd->name = \"spiflash\";\n+\tmtd->type = MTD_NORFLASH;\n+\tmtd->flags = (MTD_CAP_NORFLASH|MTD_WRITEABLE);\n+\tmtd->size = flashconfig_tbl[index].byte_cnt;\n+\tmtd->erasesize = flashconfig_tbl[index].sector_size;\n+\tmtd->writesize = 1;\n+\tmtd->numeraseregions = 0;\n+\tmtd->eraseregions = NULL;\n+\tmtd->_erase = spiflash_erase;\n+\tmtd->_read = spiflash_read;\n+\tmtd->_write = spiflash_write;\n+\tmtd->owner = THIS_MODULE;\n+\n+\tdev_info(&pdev->dev, \"%lld Kbytes flash detected\\n\", mtd->size >> 10);\n+\n+#if defined CONFIG_MTD_REDBOOT_PARTS || CONFIG_MTD_MYLOADER_PARTS\n+\t/* parse redboot partitions */\n+\n+\tresult = mtd_device_parse_register(mtd, part_probe_types,\n+\t\t\t\t\t   NULL, NULL, 0);\n+#endif\n+\n+\treturn result;\n+}\n+\n+static int\n+spiflash_remove(struct platform_device *pdev)\n+{\n+\tstruct spiflash_priv *priv = platform_get_drvdata(pdev);\n+\n+\tmtd_device_unregister(&priv->mtd);\n+\n+\treturn 0;\n+}\n+\n+static struct platform_driver spiflash_driver = {\n+\t.driver.name = DRIVER_NAME,\n+\t.probe = spiflash_probe,\n+\t.remove = spiflash_remove,\n+};\n+\n+module_platform_driver(spiflash_driver);\n+\n+MODULE_LICENSE(\"GPL\");\n+MODULE_AUTHOR(\"OpenWrt.org\");\n+MODULE_AUTHOR(\"Atheros Communications Inc\");\n+MODULE_DESCRIPTION(\"MTD driver for SPI Flash on Atheros AR2315+ SOC\");\n+MODULE_ALIAS(\"platform:\" DRIVER_NAME);\n+\n--- /dev/null\n+++ b/drivers/mtd/devices/ar2315_spiflash.h\n@@ -0,0 +1,106 @@\n+/*\n+ * Atheros AR2315 SPI Flash Memory support header file.\n+ *\n+ * Copyright (c) 2005, Atheros Communications Inc.\n+ * Copyright (C) 2006 FON Technology, SL.\n+ * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>\n+ * Copyright (C) 2006-2009 Felix Fietkau <nbd@nbd.name>\n+ *\n+ * This code is free software; you can redistribute it and/or modify\n+ * it under the terms of the GNU General Public License version 2 as\n+ * published by the Free Software Foundation.\n+ *\n+ */\n+#ifndef __AR2315_SPIFLASH_H\n+#define __AR2315_SPIFLASH_H\n+\n+#define STM_PAGE_SIZE           256\n+\n+#define SFI_WRITE_BUFFER_SIZE   4\n+#define SFI_FLASH_ADDR_MASK     0x00ffffff\n+\n+#define STM_8MBIT_SIGNATURE     0x13\n+#define STM_M25P80_BYTE_COUNT   1048576\n+#define STM_M25P80_SECTOR_COUNT 16\n+#define STM_M25P80_SECTOR_SIZE  0x10000\n+\n+#define STM_16MBIT_SIGNATURE    0x14\n+#define STM_M25P16_BYTE_COUNT   2097152\n+#define STM_M25P16_SECTOR_COUNT 32\n+#define STM_M25P16_SECTOR_SIZE  0x10000\n+\n+#define STM_32MBIT_SIGNATURE    0x15\n+#define STM_M25P32_BYTE_COUNT   4194304\n+#define STM_M25P32_SECTOR_COUNT 64\n+#define STM_M25P32_SECTOR_SIZE  0x10000\n+\n+#define STM_64MBIT_SIGNATURE    0x16\n+#define STM_M25P64_BYTE_COUNT   8388608\n+#define STM_M25P64_SECTOR_COUNT 128\n+#define STM_M25P64_SECTOR_SIZE  0x10000\n+\n+#define STM_128MBIT_SIGNATURE   0x17\n+#define STM_M25P128_BYTE_COUNT   16777216\n+#define STM_M25P128_SECTOR_COUNT 256\n+#define STM_M25P128_SECTOR_SIZE  0x10000\n+\n+#define STM_1MB_BYTE_COUNT   STM_M25P80_BYTE_COUNT\n+#define STM_1MB_SECTOR_COUNT STM_M25P80_SECTOR_COUNT\n+#define STM_1MB_SECTOR_SIZE  STM_M25P80_SECTOR_SIZE\n+#define STM_2MB_BYTE_COUNT   STM_M25P16_BYTE_COUNT\n+#define STM_2MB_SECTOR_COUNT STM_M25P16_SECTOR_COUNT\n+#define STM_2MB_SECTOR_SIZE  STM_M25P16_SECTOR_SIZE\n+#define STM_4MB_BYTE_COUNT   STM_M25P32_BYTE_COUNT\n+#define STM_4MB_SECTOR_COUNT STM_M25P32_SECTOR_COUNT\n+#define STM_4MB_SECTOR_SIZE  STM_M25P32_SECTOR_SIZE\n+#define STM_8MB_BYTE_COUNT   STM_M25P64_BYTE_COUNT\n+#define STM_8MB_SECTOR_COUNT STM_M25P64_SECTOR_COUNT\n+#define STM_8MB_SECTOR_SIZE  STM_M25P64_SECTOR_SIZE\n+#define STM_16MB_BYTE_COUNT   STM_M25P128_BYTE_COUNT\n+#define STM_16MB_SECTOR_COUNT STM_M25P128_SECTOR_COUNT\n+#define STM_16MB_SECTOR_SIZE  STM_M25P128_SECTOR_SIZE\n+\n+/*\n+ * ST Microelectronics Opcodes for Serial Flash\n+ */\n+\n+#define STM_OP_WR_ENABLE       0x06     /* Write Enable */\n+#define STM_OP_WR_DISABLE      0x04     /* Write Disable */\n+#define STM_OP_RD_STATUS       0x05     /* Read Status */\n+#define STM_OP_WR_STATUS       0x01     /* Write Status */\n+#define STM_OP_RD_DATA         0x03     /* Read Data */\n+#define STM_OP_FAST_RD_DATA    0x0b     /* Fast Read Data */\n+#define STM_OP_PAGE_PGRM       0x02     /* Page Program */\n+#define STM_OP_SECTOR_ERASE    0xd8     /* Sector Erase */\n+#define STM_OP_BULK_ERASE      0xc7     /* Bulk Erase */\n+#define STM_OP_DEEP_PWRDOWN    0xb9     /* Deep Power-Down Mode */\n+#define STM_OP_RD_SIG          0xab     /* Read Electronic Signature */\n+\n+#define STM_STATUS_WIP       0x01       /* Write-In-Progress */\n+#define STM_STATUS_WEL       0x02       /* Write Enable Latch */\n+#define STM_STATUS_BP0       0x04       /* Block Protect 0 */\n+#define STM_STATUS_BP1       0x08       /* Block Protect 1 */\n+#define STM_STATUS_BP2       0x10       /* Block Protect 2 */\n+#define STM_STATUS_SRWD      0x80       /* Status Register Write Disable */\n+\n+/*\n+ * SPI Flash Interface Registers\n+ */\n+\n+#define SPI_FLASH_CTL           0x00\n+#define SPI_FLASH_OPCODE        0x04\n+#define SPI_FLASH_DATA          0x08\n+\n+#define SPI_CTL_START           0x00000100\n+#define SPI_CTL_BUSY            0x00010000\n+#define SPI_CTL_TXCNT_MASK      0x0000000f\n+#define SPI_CTL_RXCNT_MASK      0x000000f0\n+#define SPI_CTL_TX_RX_CNT_MASK  0x000000ff\n+#define SPI_CTL_SIZE_MASK       0x00060000\n+\n+#define SPI_CTL_CLK_SEL_MASK    0x03000000\n+#define SPI_OPCODE_MASK         0x000000ff\n+\n+#define SPI_STATUS_WIP\t\tSTM_STATUS_WIP\n+\n+#endif\n--- a/arch/mips/ath25/ar2315.c\n+++ b/arch/mips/ath25/ar2315.c\n@@ -218,6 +218,28 @@ static struct platform_device ar2315_gpi\n \t.num_resources = ARRAY_SIZE(ar2315_gpio_res)\n };\n \n+static struct resource ar2315_spiflash_res[] = {\n+\t{\n+\t\t.name = \"spiflash_read\",\n+\t\t.flags = IORESOURCE_MEM,\n+\t\t.start = AR2315_SPI_READ_BASE,\n+\t\t.end = AR2315_SPI_READ_BASE + AR2315_SPI_READ_SIZE - 1,\n+\t},\n+\t{\n+\t\t.name = \"spiflash_mmr\",\n+\t\t.flags = IORESOURCE_MEM,\n+\t\t.start = AR2315_SPI_MMR_BASE,\n+\t\t.end = AR2315_SPI_MMR_BASE + AR2315_SPI_MMR_SIZE - 1,\n+\t},\n+};\n+\n+static struct platform_device ar2315_spiflash = {\n+\t.id = 0,\n+\t.name = \"ar2315-spiflash\",\n+\t.resource = ar2315_spiflash_res,\n+\t.num_resources = ARRAY_SIZE(ar2315_spiflash_res)\n+};\n+\n void __init ar2315_init_devices(void)\n {\n \t/* Find board configuration */\n@@ -228,6 +250,8 @@ void __init ar2315_init_devices(void)\n \tar2315_gpio_res[1].end = ar2315_gpio_res[1].start;\n \tplatform_device_register(&ar2315_gpio);\n \n+\tplatform_device_register(&ar2315_spiflash);\n+\n \tar2315_eth_data.macaddr = ath25_board.config->enet0_mac;\n \tath25_add_ethernet(0, AR2315_ENET0_BASE, \"eth0_mii\",\n \t\t\t   AR2315_ENET0_MII_BASE, AR2315_IRQ_ENET0,\n"
  },
  {
    "path": "target/linux/ath25/patches-5.10/130-watchdog.patch",
    "content": "--- /dev/null\n+++ b/drivers/watchdog/ar2315-wtd.c\n@@ -0,0 +1,209 @@\n+/*\n+ * This program is free software; you can redistribute it and/or modify\n+ * it under the terms of the GNU General Public License as published by\n+ * the Free Software Foundation; either version 2 of the License, or\n+ * (at your option) any later version.\n+ *\n+ * This program is distributed in the hope that it will be useful,\n+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\n+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n+ * GNU General Public License for more details.\n+ *\n+ * You should have received a copy of the GNU General Public License\n+ * along with this program; if not, see <http://www.gnu.org/licenses/>.\n+ *\n+ * Copyright (C) 2008 John Crispin <blogic@openwrt.org>\n+ * Based on EP93xx and ifxmips wdt driver\n+ */\n+\n+#include <linux/interrupt.h>\n+#include <linux/module.h>\n+#include <linux/moduleparam.h>\n+#include <linux/types.h>\n+#include <linux/miscdevice.h>\n+#include <linux/watchdog.h>\n+#include <linux/fs.h>\n+#include <linux/ioport.h>\n+#include <linux/notifier.h>\n+#include <linux/reboot.h>\n+#include <linux/init.h>\n+#include <linux/platform_device.h>\n+#include <linux/io.h>\n+#include <linux/uaccess.h>\n+\n+#define DRIVER_NAME\t\"ar2315-wdt\"\n+\n+#define CLOCK_RATE 40000000\n+#define HEARTBEAT(x) (x < 1 || x > 90 ? 20 : x)\n+\n+#define WDT_REG_TIMER\t\t0x00\n+#define WDT_REG_CTRL\t\t0x04\n+\n+#define WDT_CTRL_ACT_NONE\t0x00000000\t/* No action */\n+#define WDT_CTRL_ACT_NMI\t0x00000001\t/* NMI on watchdog */\n+#define WDT_CTRL_ACT_RESET\t0x00000002\t/* reset on watchdog */\n+\n+static int wdt_timeout = 20;\n+static int started;\n+static int in_use;\n+static void __iomem *wdt_base;\n+\n+static inline void ar2315_wdt_wr(unsigned reg, u32 val)\n+{\n+\tiowrite32(val, wdt_base + reg);\n+}\n+\n+static void\n+ar2315_wdt_enable(void)\n+{\n+\tar2315_wdt_wr(WDT_REG_TIMER, wdt_timeout * CLOCK_RATE);\n+}\n+\n+static ssize_t\n+ar2315_wdt_write(struct file *file, const char __user *data, size_t len,\n+\t\t loff_t *ppos)\n+{\n+\tif (len)\n+\t\tar2315_wdt_enable();\n+\treturn len;\n+}\n+\n+static int\n+ar2315_wdt_open(struct inode *inode, struct file *file)\n+{\n+\tif (in_use)\n+\t\treturn -EBUSY;\n+\tar2315_wdt_enable();\n+\tin_use = 1;\n+\tstarted = 1;\n+\treturn nonseekable_open(inode, file);\n+}\n+\n+static int\n+ar2315_wdt_release(struct inode *inode, struct file *file)\n+{\n+\tin_use = 0;\n+\treturn 0;\n+}\n+\n+static irqreturn_t\n+ar2315_wdt_interrupt(int irq, void *dev)\n+{\n+\tstruct platform_device *pdev = (struct platform_device *)dev;\n+\n+\tif (started) {\n+\t\tdev_crit(&pdev->dev, \"watchdog expired, rebooting system\\n\");\n+\t\temergency_restart();\n+\t} else {\n+\t\tar2315_wdt_wr(WDT_REG_CTRL, 0);\n+\t\tar2315_wdt_wr(WDT_REG_TIMER, 0);\n+\t}\n+\treturn IRQ_HANDLED;\n+}\n+\n+static struct watchdog_info ident = {\n+\t.options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING,\n+\t.identity = \"ar2315 Watchdog\",\n+};\n+\n+static long\n+ar2315_wdt_ioctl(struct file *file, unsigned int cmd, unsigned long arg)\n+{\n+\tint new_wdt_timeout;\n+\tint ret = -ENOIOCTLCMD;\n+\n+\tswitch (cmd) {\n+\tcase WDIOC_GETSUPPORT:\n+\t\tret = copy_to_user((void __user *)arg, &ident, sizeof(ident)) ?\n+\t\t      -EFAULT : 0;\n+\t\tbreak;\n+\tcase WDIOC_KEEPALIVE:\n+\t\tar2315_wdt_enable();\n+\t\tret = 0;\n+\t\tbreak;\n+\tcase WDIOC_SETTIMEOUT:\n+\t\tret = get_user(new_wdt_timeout, (int __user *)arg);\n+\t\tif (ret)\n+\t\t\tbreak;\n+\t\twdt_timeout = HEARTBEAT(new_wdt_timeout);\n+\t\tar2315_wdt_enable();\n+\t\tbreak;\n+\tcase WDIOC_GETTIMEOUT:\n+\t\tret = put_user(wdt_timeout, (int __user *)arg);\n+\t\tbreak;\n+\t}\n+\treturn ret;\n+}\n+\n+static const struct file_operations ar2315_wdt_fops = {\n+\t.owner\t\t= THIS_MODULE,\n+\t.llseek\t\t= no_llseek,\n+\t.write\t\t= ar2315_wdt_write,\n+\t.unlocked_ioctl\t= ar2315_wdt_ioctl,\n+\t.open\t\t= ar2315_wdt_open,\n+\t.release\t= ar2315_wdt_release,\n+};\n+\n+static struct miscdevice ar2315_wdt_miscdev = {\n+\t.minor\t= WATCHDOG_MINOR,\n+\t.name\t= \"watchdog\",\n+\t.fops\t= &ar2315_wdt_fops,\n+};\n+\n+static int\n+ar2315_wdt_probe(struct platform_device *dev)\n+{\n+\tstruct resource *mem_res, *irq_res;\n+\tint ret = 0;\n+\n+\tif (wdt_base)\n+\t\treturn -EBUSY;\n+\n+\tirq_res = platform_get_resource(dev, IORESOURCE_IRQ, 0);\n+\tif (!irq_res) {\n+\t\tdev_err(&dev->dev, \"no IRQ resource\\n\");\n+\t\treturn -ENOENT;\n+\t}\n+\n+\tmem_res = platform_get_resource(dev, IORESOURCE_MEM, 0);\n+\twdt_base = devm_ioremap_resource(&dev->dev, mem_res);\n+\tif (IS_ERR(wdt_base))\n+\t\treturn PTR_ERR(wdt_base);\n+\n+\tret = devm_request_irq(&dev->dev, irq_res->start, ar2315_wdt_interrupt,\n+\t\t\t       0, DRIVER_NAME, dev);\n+\tif (ret) {\n+\t\tdev_err(&dev->dev, \"failed to register inetrrupt\\n\");\n+\t\tgoto out;\n+\t}\n+\n+\tret = misc_register(&ar2315_wdt_miscdev);\n+\tif (ret)\n+\t\tdev_err(&dev->dev, \"failed to register miscdev\\n\");\n+\n+out:\n+\treturn ret;\n+}\n+\n+static int\n+ar2315_wdt_remove(struct platform_device *dev)\n+{\n+\tmisc_deregister(&ar2315_wdt_miscdev);\n+\treturn 0;\n+}\n+\n+static struct platform_driver ar2315_wdt_driver = {\n+\t.probe = ar2315_wdt_probe,\n+\t.remove = ar2315_wdt_remove,\n+\t.driver = {\n+\t\t.name = DRIVER_NAME,\n+\t\t.owner = THIS_MODULE,\n+\t},\n+};\n+\n+module_platform_driver(ar2315_wdt_driver);\n+\n+MODULE_DESCRIPTION(\"Atheros AR2315 hardware watchdog driver\");\n+MODULE_AUTHOR(\"John Crispin <blogic@openwrt.org>\");\n+MODULE_LICENSE(\"GPL\");\n+MODULE_ALIAS(\"platform:\" DRIVER_NAME);\n--- a/drivers/watchdog/Kconfig\n+++ b/drivers/watchdog/Kconfig\n@@ -1873,6 +1873,13 @@ config PIC32_DMT\n \t  To compile this driver as a loadable module, choose M here.\n \t  The module will be called pic32-dmt.\n \n+config AR2315_WDT\n+\ttristate \"Atheros AR2315+ WiSoCs Watchdog Timer\"\n+\tdepends on ATH25\n+\thelp\n+\t  Hardware driver for the built-in watchdog timer on the Atheros\n+\t  AR2315/AR2316 WiSoCs.\n+\n # PARISC Architecture\n \n # POWERPC Architecture\n--- a/drivers/watchdog/Makefile\n+++ b/drivers/watchdog/Makefile\n@@ -164,6 +164,7 @@ obj-$(CONFIG_WDT_MTX1) += mtx-1_wdt.o\n obj-$(CONFIG_PNX833X_WDT) += pnx833x_wdt.o\n obj-$(CONFIG_SIBYTE_WDOG) += sb_wdog.o\n obj-$(CONFIG_AR7_WDT) += ar7_wdt.o\n+obj-$(CONFIG_AR2315_WDT) += ar2315-wtd.o\n obj-$(CONFIG_TXX9_WDT) += txx9wdt.o\n obj-$(CONFIG_OCTEON_WDT) += octeon-wdt.o\n octeon-wdt-y := octeon-wdt-main.o octeon-wdt-nmi.o\n--- a/arch/mips/ath25/ar2315.c\n+++ b/arch/mips/ath25/ar2315.c\n@@ -218,6 +218,24 @@ static struct platform_device ar2315_gpi\n \t.num_resources = ARRAY_SIZE(ar2315_gpio_res)\n };\n \n+static struct resource ar2315_wdt_res[] = {\n+\t{\n+\t\t.flags = IORESOURCE_MEM,\n+\t\t.start = AR2315_RST_BASE + AR2315_WDT_TIMER,\n+\t\t.end = AR2315_RST_BASE + AR2315_WDT_TIMER + 8 - 1,\n+\t},\n+\t{\n+\t\t.flags = IORESOURCE_IRQ,\n+\t}\n+};\n+\n+static struct platform_device ar2315_wdt = {\n+\t.id = 0,\n+\t.name = \"ar2315-wdt\",\n+\t.resource = ar2315_wdt_res,\n+\t.num_resources = ARRAY_SIZE(ar2315_wdt_res)\n+};\n+\n static struct resource ar2315_spiflash_res[] = {\n \t{\n \t\t.name = \"spiflash_read\",\n@@ -250,6 +268,11 @@ void __init ar2315_init_devices(void)\n \tar2315_gpio_res[1].end = ar2315_gpio_res[1].start;\n \tplatform_device_register(&ar2315_gpio);\n \n+\tar2315_wdt_res[1].start = irq_create_mapping(ar2315_misc_irq_domain,\n+\t\t\t\t\t\t     AR2315_MISC_IRQ_WATCHDOG);\n+\tar2315_wdt_res[1].end = ar2315_wdt_res[1].start;\n+\tplatform_device_register(&ar2315_wdt);\n+\n \tplatform_device_register(&ar2315_spiflash);\n \n \tar2315_eth_data.macaddr = ath25_board.config->enet0_mac;\n"
  },
  {
    "path": "target/linux/ath25/patches-5.10/140-redboot_boardconfig.patch",
    "content": "--- a/drivers/mtd/parsers/redboot.c\n+++ b/drivers/mtd/parsers/redboot.c\n@@ -16,6 +16,8 @@\n #include <linux/mtd/partitions.h>\n #include <linux/module.h>\n \n+#define BOARD_CONFIG_PART\t\t\"boardconfig\"\n+\n struct fis_image_desc {\n     unsigned char name[16];      // Null terminated name\n     uint32_t\t  flash_base;    // Address within FLASH of image\n@@ -72,6 +74,7 @@ static int parse_redboot_partitions(stru\n \t\t\t\t    const struct mtd_partition **pparts,\n \t\t\t\t    struct mtd_part_parser_data *data)\n {\n+\tunsigned long max_offset = 0;\n \tint nrparts = 0;\n \tstruct fis_image_desc *buf;\n \tstruct mtd_partition *parts;\n@@ -239,14 +242,15 @@ static int parse_redboot_partitions(stru\n \t\t}\n \t}\n #endif\n-\tparts = kzalloc(sizeof(*parts)*nrparts + nulllen + namelen, GFP_KERNEL);\n+\tparts = kzalloc(sizeof(*parts) * (nrparts + 1) + nulllen + namelen +\n+\t\t\tsizeof(BOARD_CONFIG_PART), GFP_KERNEL);\n \n \tif (!parts) {\n \t\tret = -ENOMEM;\n \t\tgoto out;\n \t}\n \n-\tnullname = (char *)&parts[nrparts];\n+\tnullname = (char *)&parts[nrparts + 1];\n #ifdef CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED\n \tif (nulllen > 0) {\n \t\tstrcpy(nullname, nullstring);\n@@ -265,6 +269,8 @@ static int parse_redboot_partitions(stru\n \t}\n #endif\n \tfor ( ; i<nrparts; i++) {\n+\t\tif (max_offset < buf[i].flash_base + buf[i].size)\n+\t\t\tmax_offset = buf[i].flash_base + buf[i].size;\n \t\tparts[i].size = fl->img->size;\n \t\tparts[i].offset = fl->img->flash_base;\n \t\tparts[i].name = names;\n@@ -298,6 +304,13 @@ static int parse_redboot_partitions(stru\n \t\tfl = fl->next;\n \t\tkfree(tmp_fl);\n \t}\n+\tif (master->size - max_offset >= master->erasesize) {\n+\t\tparts[nrparts].size = master->size - max_offset;\n+\t\tparts[nrparts].offset = max_offset;\n+\t\tparts[nrparts].name = names;\n+\t\tstrcpy(names, BOARD_CONFIG_PART);\n+\t\tnrparts++;\n+\t}\n \tret = nrparts;\n \t*pparts = parts;\n  out:\n"
  },
  {
    "path": "target/linux/ath25/patches-5.10/141-redboot_partition_scan.patch",
    "content": "--- a/drivers/mtd/parsers/redboot.c\n+++ b/drivers/mtd/parsers/redboot.c\n@@ -93,12 +93,18 @@ static int parse_redboot_partitions(stru\n \n \tparse_redboot_of(master);\n \n+\tbuf = vmalloc(master->erasesize);\n+\tif (!buf)\n+\t\treturn -ENOMEM;\n+\n+ restart:\n \tif ( directory < 0 ) {\n \t\toffset = master->size + directory * master->erasesize;\n \t\twhile (mtd_block_isbad(master, offset)) {\n \t\t\tif (!offset) {\n \t\t\tnogood:\n \t\t\t\tprintk(KERN_NOTICE \"Failed to find a non-bad block to check for RedBoot partition table\\n\");\n+\t\t\t\tvfree(buf);\n \t\t\t\treturn -EIO;\n \t\t\t}\n \t\t\toffset -= master->erasesize;\n@@ -111,10 +117,6 @@ static int parse_redboot_partitions(stru\n \t\t\t\tgoto nogood;\n \t\t}\n \t}\n-\tbuf = vmalloc(master->erasesize);\n-\n-\tif (!buf)\n-\t\treturn -ENOMEM;\n \n \tprintk(KERN_NOTICE \"Searching for RedBoot partition table in %s at offset 0x%lx\\n\",\n \t       master->name, offset);\n@@ -187,6 +189,11 @@ static int parse_redboot_partitions(stru\n \t}\n \tif (i == numslots) {\n \t\t/* Didn't find it */\n+\t\tif (offset + master->erasesize < master->size) {\n+\t\t\t/* not at the end of the flash yet, maybe next block */\n+\t\t\tdirectory++;\n+\t\t\tgoto restart;\n+\t\t}\n \t\tprintk(KERN_NOTICE \"No RedBoot partition table detected in %s\\n\",\n \t\t       master->name);\n \t\tret = 0;\n"
  },
  {
    "path": "target/linux/ath25/patches-5.10/142-redboot_various_erase_size_fix.patch",
    "content": "--- a/drivers/mtd/parsers/redboot.c\n+++ b/drivers/mtd/parsers/redboot.c\n@@ -70,6 +70,22 @@ static void parse_redboot_of(struct mtd_\n \tdirectory = dirblock;\n }\n \n+static uint32_t mtd_get_offset_erasesize(struct mtd_info *mtd, uint64_t offset)\n+{\n+\tstruct mtd_erase_region_info *regions = mtd->eraseregions;\n+\tint i;\n+\n+\tfor (i = 0; i < mtd->numeraseregions; i++) {\n+\t\tif (regions[i].offset +\n+\t\t    regions[i].numblocks * regions[i].erasesize <= offset)\n+\t\t\tcontinue;\n+\n+\t\treturn regions[i].erasesize;\n+\t}\n+\n+\treturn mtd->erasesize;\n+}\n+\n static int parse_redboot_partitions(struct mtd_info *master,\n \t\t\t\t    const struct mtd_partition **pparts,\n \t\t\t\t    struct mtd_part_parser_data *data)\n@@ -86,6 +102,7 @@ static int parse_redboot_partitions(stru\n \tint namelen = 0;\n \tint nulllen = 0;\n \tint numslots;\n+\tint first_slot;\n \tunsigned long offset;\n #ifdef CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED\n \tstatic char nullstring[] = \"unallocated\";\n@@ -200,7 +217,10 @@ static int parse_redboot_partitions(stru\n \t\tgoto out;\n \t}\n \n-\tfor (i = 0; i < numslots; i++) {\n+\tfirst_slot = (buf[i].flash_base & (master->erasesize - 1)) /\n+\t\t     sizeof(struct fis_image_desc);\n+\n+\tfor (i = first_slot; i < first_slot + numslots; i++) {\n \t\tstruct fis_list *new_fl, **prev;\n \n \t\tif (buf[i].name[0] == 0xff) {\n@@ -276,12 +296,13 @@ static int parse_redboot_partitions(stru\n \t}\n #endif\n \tfor ( ; i<nrparts; i++) {\n-\t\tif (max_offset < buf[i].flash_base + buf[i].size)\n-\t\t\tmax_offset = buf[i].flash_base + buf[i].size;\n \t\tparts[i].size = fl->img->size;\n \t\tparts[i].offset = fl->img->flash_base;\n \t\tparts[i].name = names;\n \n+\t\tif (max_offset < parts[i].offset + parts[i].size)\n+\t\t\tmax_offset = parts[i].offset + parts[i].size;\n+\n \t\tstrcpy(names, fl->img->name);\n #ifdef CONFIG_MTD_REDBOOT_PARTS_READONLY\n \t\tif (!memcmp(names, \"RedBoot\", 8) ||\n@@ -311,7 +332,9 @@ static int parse_redboot_partitions(stru\n \t\tfl = fl->next;\n \t\tkfree(tmp_fl);\n \t}\n-\tif (master->size - max_offset >= master->erasesize) {\n+\n+\tif (master->size - max_offset >=\n+\t    mtd_get_offset_erasesize(master, max_offset)) {\n \t\tparts[nrparts].size = master->size - max_offset;\n \t\tparts[nrparts].offset = max_offset;\n \t\tparts[nrparts].name = names;\n"
  },
  {
    "path": "target/linux/ath25/patches-5.10/210-reset_button.patch",
    "content": "--- a/arch/mips/ath25/Makefile\n+++ b/arch/mips/ath25/Makefile\n@@ -8,7 +8,7 @@\n # Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>\n #\n \n-obj-y += board.o prom.o devices.o\n+obj-y += board.o prom.o devices.o reset.o\n \n obj-$(CONFIG_EARLY_PRINTK) += early_printk.o\n \n--- /dev/null\n+++ b/arch/mips/ath25/reset.c\n@@ -0,0 +1,57 @@\n+#include <linux/init.h>\n+#include <linux/slab.h>\n+#include <linux/platform_device.h>\n+#include <linux/gpio_keys.h>\n+#include <linux/input.h>\n+#include <ath25_platform.h>\n+#include \"devices.h\"\n+\n+static int __init\n+ar231x_init_reset(void)\n+{\n+\tstruct platform_device *pdev;\n+\tstruct gpio_keys_platform_data pdata;\n+\tstruct gpio_keys_button *p;\n+\tint err;\n+\n+\tif (ath25_board.config->reset_config_gpio == 0xffff)\n+\t\treturn -ENODEV;\n+\n+\tp = kzalloc(sizeof(*p), GFP_KERNEL);\n+\tif (!p)\n+\t\tgoto err;\n+\n+\tp->desc = \"reset\";\n+\tp->type = EV_KEY;\n+\tp->code = KEY_RESTART;\n+\tp->debounce_interval = 60;\n+\tp->gpio = ath25_board.config->reset_config_gpio;\n+\n+\tmemset(&pdata, 0, sizeof(pdata));\n+\tpdata.poll_interval = 20;\n+\tpdata.buttons = p;\n+\tpdata.nbuttons = 1;\n+\n+\tpdev = platform_device_alloc(\"gpio-keys-polled\", 0);\n+\tif (!pdev)\n+\t\tgoto err_free;\n+\n+\terr = platform_device_add_data(pdev, &pdata, sizeof(pdata));\n+\tif (err)\n+\t\tgoto err_put_pdev;\n+\n+\terr = platform_device_add(pdev);\n+\tif (err)\n+\t\tgoto err_put_pdev;\n+\n+\treturn 0;\n+\n+err_put_pdev:\n+\tplatform_device_put(pdev);\n+err_free:\n+\tkfree(p);\n+err:\n+\treturn -ENOMEM;\n+}\n+\n+device_initcall(ar231x_init_reset);\n"
  },
  {
    "path": "target/linux/ath25/patches-5.10/220-enet_micrel_workaround.patch",
    "content": "--- a/drivers/net/ethernet/atheros/ar231x/ar231x.c\n+++ b/drivers/net/ethernet/atheros/ar231x/ar231x.c\n@@ -135,6 +135,7 @@ static int ar231x_mdiobus_write(struct m\n static int ar231x_mdiobus_reset(struct mii_bus *bus);\n static int ar231x_mdiobus_probe(struct net_device *dev);\n static void ar231x_adjust_link(struct net_device *dev);\n+static bool no_phy;\n \n #ifndef ERR\n #define ERR(fmt, args...) printk(\"%s: \" fmt, __func__, ##args)\n@@ -166,6 +167,32 @@ static const struct net_device_ops ar231\n #endif\n };\n \n+static int get_phy_id(struct mii_bus *bus, int addr, u32 *phy_id)\n+{\n+\tint phy_reg;\n+\n+\t/**\n+\t * Grab the bits from PHYIR1, and put them\n+\t * in the upper half.\n+\t */\n+\tphy_reg = mdiobus_read(bus, addr, MII_PHYSID1);\n+\n+\tif (phy_reg < 0)\n+\t\treturn -EIO;\n+\n+\t*phy_id = (phy_reg & 0xffff) << 16;\n+\n+\t/* Grab the bits from PHYIR2, and put them in the lower half */\n+\tphy_reg = mdiobus_read(bus, addr, MII_PHYSID2);\n+\n+\tif (phy_reg < 0)\n+\t\treturn -EIO;\n+\n+\t*phy_id |= (phy_reg & 0xffff);\n+\n+\treturn 0;\n+}\n+\n static int ar231x_probe(struct platform_device *pdev)\n {\n \tstruct net_device *dev;\n@@ -273,6 +300,24 @@ static int ar231x_probe(struct platform_\n \n \tmdiobus_register(sp->mii_bus);\n \n+\t/**\n+\t * Workaround for Micrel switch, which is only available on\n+\t * one PHY and cannot be configured through MDIO.\n+\t */\n+\tif (!no_phy) {\n+\t\tu32 phy_id = 0;\n+\n+\t\tget_phy_id(sp->mii_bus, 1, &phy_id);\n+\t\tif (phy_id == 0x00221450)\n+\t\t\tno_phy = true;\n+\t}\n+\tif (no_phy) {\n+\t\tsp->link = 1;\n+\t\tnetif_carrier_on(dev);\n+\t\treturn 0;\n+\t}\n+\tno_phy = true;\n+\n \tif (ar231x_mdiobus_probe(dev) != 0) {\n \t\tprintk(KERN_ERR \"%s: mdiobus_probe failed\\n\", dev->name);\n \t\trx_tasklet_cleanup(dev);\n@@ -326,8 +371,10 @@ static int ar231x_remove(struct platform\n \trx_tasklet_cleanup(dev);\n \tar231x_init_cleanup(dev);\n \tunregister_netdev(dev);\n-\tmdiobus_unregister(sp->mii_bus);\n-\tmdiobus_free(sp->mii_bus);\n+\tif (sp->mii_bus) {\n+\t\tmdiobus_unregister(sp->mii_bus);\n+\t\tmdiobus_free(sp->mii_bus);\n+\t}\n \tkfree(dev);\n \treturn 0;\n }\n@@ -870,7 +917,8 @@ static int ar231x_open(struct net_device\n \n \tsp->eth_regs->mac_control |= MAC_CONTROL_RE;\n \n-\tphy_start(sp->phy_dev);\n+\tif (sp->phy_dev)\n+\t\tphy_start(sp->phy_dev);\n \n \treturn 0;\n }\n@@ -951,7 +999,8 @@ static int ar231x_close(struct net_devic\n \n #endif\n \n-\tphy_stop(sp->phy_dev);\n+\tif (sp->phy_dev)\n+\t\tphy_stop(sp->phy_dev);\n \n \treturn 0;\n }\n@@ -995,6 +1044,9 @@ static int ar231x_ioctl(struct net_devic\n {\n \tstruct ar231x_private *sp = netdev_priv(dev);\n \n+\tif (!sp->phy_dev)\n+\t\treturn -ENODEV;\n+\n \tswitch (cmd) {\n \tcase SIOCGMIIPHY:\n \tcase SIOCGMIIREG:\n"
  },
  {
    "path": "target/linux/ath25/patches-5.10/330-board_leds.patch",
    "content": "--- a/arch/mips/ath25/ar2315.c\n+++ b/arch/mips/ath25/ar2315.c\n@@ -24,6 +24,7 @@\n #include <linux/reboot.h>\n #include <linux/delay.h>\n #include <linux/gpio.h>\n+#include <linux/leds.h>\n #include <asm/bootinfo.h>\n #include <asm/reboot.h>\n #include <asm/time.h>\n@@ -258,6 +259,50 @@ static struct platform_device ar2315_spi\n \t.num_resources = ARRAY_SIZE(ar2315_spiflash_res)\n };\n \n+#ifdef CONFIG_LEDS_GPIO\n+static struct gpio_led ar2315_leds[6];\n+static struct gpio_led_platform_data ar2315_led_data = {\n+\t.leds = (void *)ar2315_leds,\n+};\n+\n+static struct platform_device ar2315_gpio_leds = {\n+\t.name = \"leds-gpio\",\n+\t.id = -1,\n+\t.dev = {\n+\t\t.platform_data = (void *)&ar2315_led_data,\n+\t}\n+};\n+\n+static void __init ar2315_init_gpio_leds(void)\n+{\n+\tstatic char led_names[6][6];\n+\tint i, led = 0;\n+\n+\tar2315_led_data.num_leds = 0;\n+\tfor (i = 1; i < 8; i++) {\n+\t\tif ((i == AR2315_RESET_GPIO) ||\n+\t\t    (i == ath25_board.config->reset_config_gpio))\n+\t\t\tcontinue;\n+\n+\t\tif (i == ath25_board.config->sys_led_gpio)\n+\t\t\tstrcpy(led_names[led], \"wlan\");\n+\t\telse\n+\t\t\tsprintf(led_names[led], \"gpio%d\", i);\n+\n+\t\tar2315_leds[led].name = led_names[led];\n+\t\tar2315_leds[led].gpio = i;\n+\t\tar2315_leds[led].active_low = 0;\n+\t\tled++;\n+\t}\n+\tar2315_led_data.num_leds = led;\n+\tplatform_device_register(&ar2315_gpio_leds);\n+}\n+#else\n+static inline void ar2315_init_gpio_leds(void)\n+{\n+}\n+#endif\n+\n void __init ar2315_init_devices(void)\n {\n \t/* Find board configuration */\n@@ -268,6 +313,8 @@ void __init ar2315_init_devices(void)\n \tar2315_gpio_res[1].end = ar2315_gpio_res[1].start;\n \tplatform_device_register(&ar2315_gpio);\n \n+\tar2315_init_gpio_leds();\n+\n \tar2315_wdt_res[1].start = irq_create_mapping(ar2315_misc_irq_domain,\n \t\t\t\t\t\t     AR2315_MISC_IRQ_WATCHDOG);\n \tar2315_wdt_res[1].end = ar2315_wdt_res[1].start;\n--- a/arch/mips/ath25/ar5312.c\n+++ b/arch/mips/ath25/ar5312.c\n@@ -24,6 +24,7 @@\n #include <linux/mtd/physmap.h>\n #include <linux/reboot.h>\n #include <linux/gpio.h>\n+#include <linux/leds.h>\n #include <asm/bootinfo.h>\n #include <asm/reboot.h>\n #include <asm/time.h>\n@@ -229,6 +230,23 @@ static struct platform_device ar5312_gpi\n \t.num_resources = ARRAY_SIZE(ar5312_gpio_res),\n };\n \n+#ifdef CONFIG_LEDS_GPIO\n+static struct gpio_led ar5312_leds[] = {\n+\t{ .name = \"wlan\", .gpio = 0, .active_low = 1, },\n+};\n+\n+static const struct gpio_led_platform_data ar5312_led_data = {\n+\t.num_leds = ARRAY_SIZE(ar5312_leds),\n+\t.leds = (void *)ar5312_leds,\n+};\n+\n+static struct platform_device ar5312_gpio_leds = {\n+\t.name = \"leds-gpio\",\n+\t.id = -1,\n+\t.dev.platform_data = (void *)&ar5312_led_data,\n+};\n+#endif\n+\n static void __init ar5312_flash_init(void)\n {\n \tvoid __iomem *flashctl_base;\n@@ -299,6 +317,11 @@ void __init ar5312_init_devices(void)\n \n \tplatform_device_register(&ar5312_gpio);\n \n+#ifdef CONFIG_LEDS_GPIO\n+\tar5312_leds[0].gpio = config->sys_led_gpio;\n+\tplatform_device_register(&ar5312_gpio_leds);\n+#endif\n+\n \t/* Fix up MAC addresses if necessary */\n \tif (is_broadcast_ether_addr(config->enet0_mac))\n \t\tether_addr_copy(config->enet0_mac, config->enet1_mac);\n"
  },
  {
    "path": "target/linux/ath25/patches-5.10/700-swconfig_mvswitch.patch",
    "content": "--- a/drivers/net/phy/Kconfig\n+++ b/drivers/net/phy/Kconfig\n@@ -95,6 +95,10 @@ config IP17XX_PHY\n \ttristate \"Driver for IC+ IP17xx switches\"\n \tselect SWCONFIG\n \n+config MVSWITCH_PHY\n+\ttristate \"Driver for Marvell 88E6060 switches\"\n+\tselect ETHERNET_PACKET_MANGLE\n+\n config PSB6970_PHY\n \ttristate \"Lantiq XWAY Tantos (PSB6970) Ethernet switch\"\n \tselect SWCONFIG\n--- a/drivers/net/phy/Makefile\n+++ b/drivers/net/phy/Makefile\n@@ -29,6 +29,7 @@ obj-$(CONFIG_ADM6996_PHY)\t+= adm6996.o\n obj-$(CONFIG_AR8216_PHY)\t+= ar8216.o ar8327.o\n obj-$(CONFIG_SWCONFIG_B53)\t+= b53/\n obj-$(CONFIG_IP17XX_PHY)\t+= ip17xx.o\n+obj-$(CONFIG_MVSWITCH_PHY)\t+= mvswitch.o\n obj-$(CONFIG_PSB6970_PHY)\t+= psb6970.o\n obj-$(CONFIG_RTL8306_PHY)\t+= rtl8306.o\n obj-$(CONFIG_RTL8366_SMI)\t+= rtl8366_smi.o\n"
  },
  {
    "path": "target/linux/ath25/profiles/00-default.mk",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2011 OpenWrt.org\n\ndefine Profile/Default\n\tNAME:=Default Profile\n\tPRIORITY:=1\nendef\n\ndefine Profile/Default/Description\n\tDefault package set compatible with most boards.\nendef\n$(eval $(call Profile,Default))\n"
  },
  {
    "path": "target/linux/ath79/Makefile",
    "content": "include $(TOPDIR)/rules.mk\n\nARCH:=mips\nBOARD:=ath79\nBOARDNAME:=Atheros ATH79\nCPU_TYPE:=24kc\nSUBTARGETS:=generic mikrotik nand tiny\n\nFEATURES:=ramdisk squashfs usbgadget\n\nKERNEL_PATCHVER:=5.10\n\ninclude $(INCLUDE_DIR)/target.mk\n\nDEFAULT_PACKAGES += \\\n\tkmod-gpio-button-hotplug swconfig \\\n\tkmod-ath9k uboot-envtools\n\n$(eval $(call BuildTarget))\n"
  },
  {
    "path": "target/linux/ath79/base-files/etc/hotplug.d/ieee80211/00-wifi-migration",
    "content": "#!/bin/sh\n\nWIFI_PATH_CHANGED=0\n\n. /lib/functions.sh\n\nmigrate_wifi_path() {\n\tlocal section=\"$1\"\n\tlocal path\n\n\tconfig_get path ${section} path\n\tcase ${path} in\n\t\t\"pci0000:01/0000:01:00.0\")\n\t\t\tboard=$(board_name)\n\n\t\t\tcase \"$board\" in\n\t\t\t\ttplink,archer-c5-v1|\\\n\t\t\t\ttplink,archer-c7-v1|\\\n\t\t\t\ttplink,archer-c7-v2|\\\n\t\t\t\tzyxel,emg2926-q10a|\\\n\t\t\t\tzyxel,nbg6716)\n\t\t\t\t\tpath=\"pci0000:00/0000:00:00.0\"\n\t\t\t\t\tWIFI_PATH_CHANGED=1\n\t\t\t\t;;\n\t\t\t\t*)\n\t\t\t\t\treturn 0\n\t\t\t\t;;\n\t\t\tesac\n\t\t;;\n\t\t\"platform/ahb/ahb:apb/18100000.wmac\"|\\\n\t\t\"platform/ar933x_wmac\"|\\\n\t\t\"platform/ar934x_wmac\"|\\\n\t\t\"platform/qca953x_wmac\"|\\\n\t\t\"platform/qca955x_wmac\"|\\\n\t\t\"platform/qca956x_wmac\")\n\t\t\tpath=\"platform/ahb/18100000.wmac\"\n\t\t\tWIFI_PATH_CHANGED=1\n\t\t;;\n\t\t\"platform/ath9k\")\n\t\t\tpath=\"platform/ahb/180c0000.wmac\"\n\t\t\tWIFI_PATH_CHANGED=1\n\t\t;;\n\t\t*)\n\t\t\treturn 0\n\t\t;;\n\tesac\n\n\tuci set wireless.${section}.path=${path}\n}\n\n[ \"${ACTION}\" = \"add\" ] && {\n\t[ ! -e /etc/config/wireless ] && return 0\n\n\tconfig_load wireless\n\tconfig_foreach migrate_wifi_path wifi-device\n\n\t[ \"${WIFI_PATH_CHANGED}\" = \"1\" ] && uci commit wireless\n}\n"
  },
  {
    "path": "target/linux/ath79/config-5.10",
    "content": "CONFIG_AG71XX=y\n# CONFIG_AG71XX_DEBUG is not set\nCONFIG_AG71XX_DEBUG_FS=y\nCONFIG_AR8216_PHY=y\nCONFIG_AR8216_PHY_LEDS=y\nCONFIG_ARCH_32BIT_OFF_T=y\nCONFIG_ARCH_HIBERNATION_POSSIBLE=y\nCONFIG_ARCH_MMAP_RND_BITS_MAX=15\nCONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15\nCONFIG_ARCH_SUSPEND_POSSIBLE=y\nCONFIG_AT803X_PHY=y\nCONFIG_ATH79=y\nCONFIG_ATH79_WDT=y\nCONFIG_BLK_MQ_PCI=y\nCONFIG_CEVT_R4K=y\nCONFIG_CLKDEV_LOOKUP=y\nCONFIG_CLONE_BACKWARDS=y\nCONFIG_CMDLINE=\"rootfstype=squashfs,jffs2\"\nCONFIG_CMDLINE_BOOL=y\n# CONFIG_CMDLINE_OVERRIDE is not set\nCONFIG_COMMON_CLK=y\n# CONFIG_COMMON_CLK_BOSTON is not set\nCONFIG_COMPAT_32BIT_TIME=y\nCONFIG_CPU_BIG_ENDIAN=y\nCONFIG_CPU_GENERIC_DUMP_TLB=y\nCONFIG_CPU_HAS_DIEI=y\nCONFIG_CPU_HAS_PREFETCH=y\nCONFIG_CPU_HAS_RIXI=y\nCONFIG_CPU_HAS_SYNC=y\nCONFIG_CPU_MIPS32=y\nCONFIG_CPU_MIPS32_R2=y\nCONFIG_CPU_MIPSR2=y\nCONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y\nCONFIG_CPU_R4K_CACHE_TLB=y\nCONFIG_CPU_SUPPORTS_32BIT_KERNEL=y\nCONFIG_CPU_SUPPORTS_HIGHMEM=y\nCONFIG_CPU_SUPPORTS_MSA=y\n# CONFIG_CRYPTO_CHACHA_MIPS is not set\nCONFIG_CRYPTO_LIB_POLY1305_RSIZE=2\n# CONFIG_CRYPTO_POLY1305_MIPS is not set\nCONFIG_CRYPTO_RNG2=y\nCONFIG_CSRC_R4K=y\nCONFIG_DMA_NONCOHERENT=y\nCONFIG_DTC=y\nCONFIG_EARLY_PRINTK=y\nCONFIG_ETHERNET_PACKET_MANGLE=y\nCONFIG_FIXED_PHY=y\nCONFIG_FW_LOADER_PAGED_BUF=y\nCONFIG_GENERIC_ATOMIC64=y\nCONFIG_GENERIC_CLOCKEVENTS=y\nCONFIG_GENERIC_CMOS_UPDATE=y\nCONFIG_GENERIC_CPU_AUTOPROBE=y\nCONFIG_GENERIC_GETTIMEOFDAY=y\nCONFIG_GENERIC_IOMAP=y\nCONFIG_GENERIC_IRQ_CHIP=y\nCONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y\nCONFIG_GENERIC_IRQ_SHOW=y\nCONFIG_GENERIC_LIB_ASHLDI3=y\nCONFIG_GENERIC_LIB_ASHRDI3=y\nCONFIG_GENERIC_LIB_CMPDI2=y\nCONFIG_GENERIC_LIB_LSHRDI3=y\nCONFIG_GENERIC_LIB_UCMPDI2=y\nCONFIG_GENERIC_PCI_IOMAP=y\nCONFIG_GENERIC_PHY=y\nCONFIG_GENERIC_PINCONF=y\nCONFIG_GENERIC_PINCTRL_GROUPS=y\nCONFIG_GENERIC_PINMUX_FUNCTIONS=y\nCONFIG_GENERIC_SCHED_CLOCK=y\nCONFIG_GENERIC_SMP_IDLE_THREAD=y\nCONFIG_GENERIC_TIME_VSYSCALL=y\nCONFIG_GPIOLIB=y\nCONFIG_GPIOLIB_IRQCHIP=y\nCONFIG_GPIO_74X164=y\nCONFIG_GPIO_ATH79=y\nCONFIG_GPIO_GENERIC=y\n# CONFIG_GPIO_LATCH is not set\n# CONFIG_GPIO_RB91X_KEY is not set\nCONFIG_HANDLE_DOMAIN_IRQ=y\nCONFIG_HARDWARE_WATCHPOINTS=y\nCONFIG_HAS_DMA=y\nCONFIG_HAS_IOMEM=y\nCONFIG_HAS_IOPORT_MAP=y\nCONFIG_HZ_PERIODIC=y\nCONFIG_IMAGE_CMDLINE_HACK=y\nCONFIG_INITRAMFS_SOURCE=\"\"\nCONFIG_IRQCHIP=y\nCONFIG_IRQ_DOMAIN=y\nCONFIG_IRQ_FORCED_THREADING=y\nCONFIG_IRQ_MIPS_CPU=y\nCONFIG_IRQ_WORK=y\n# CONFIG_KERNEL_ZSTD is not set\nCONFIG_LEDS_GPIO=y\n# CONFIG_LEDS_RESET is not set\nCONFIG_LIBFDT=y\nCONFIG_LOCK_DEBUGGING_SUPPORT=y\nCONFIG_MDIO_BITBANG=y\nCONFIG_MDIO_BUS=y\nCONFIG_MDIO_DEVICE=y\nCONFIG_MDIO_GPIO=y\nCONFIG_MEMFD_CREATE=y\n# CONFIG_MFD_RB4XX_CPLD is not set\nCONFIG_MFD_SYSCON=y\nCONFIG_MIGRATION=y\nCONFIG_MIPS=y\nCONFIG_MIPS_ASID_BITS=8\nCONFIG_MIPS_ASID_SHIFT=0\nCONFIG_MIPS_CBPF_JIT=y\nCONFIG_MIPS_CLOCK_VSYSCALL=y\n# CONFIG_MIPS_CMDLINE_BUILTIN_EXTEND is not set\n# CONFIG_MIPS_CMDLINE_DTB_EXTEND is not set\n# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set\nCONFIG_MIPS_CMDLINE_FROM_DTB=y\n# CONFIG_MIPS_ELF_APPENDED_DTB is not set\n# CONFIG_MIPS_GENERIC_KERNEL is not set\nCONFIG_MIPS_L1_CACHE_SHIFT=5\nCONFIG_MIPS_LD_CAN_LINK_VDSO=y\n# CONFIG_MIPS_NO_APPENDED_DTB is not set\nCONFIG_MIPS_RAW_APPENDED_DTB=y\nCONFIG_MIPS_SPRAM=y\nCONFIG_MODULES_USE_ELF_REL=y\nCONFIG_MTD_CFI_ADV_OPTIONS=y\nCONFIG_MTD_CFI_GEOMETRY=y\n# CONFIG_MTD_CFI_I2 is not set\n# CONFIG_MTD_CFI_INTELEXT is not set\nCONFIG_MTD_CMDLINE_PARTS=y\n# CONFIG_MTD_MAP_BANK_WIDTH_1 is not set\n# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set\nCONFIG_MTD_PARSER_CYBERTAN=y\nCONFIG_MTD_PHYSMAP=y\nCONFIG_MTD_SPI_NOR=y\nCONFIG_MTD_SPLIT_ELF_FW=y\nCONFIG_MTD_SPLIT_LZMA_FW=y\nCONFIG_MTD_SPLIT_SEAMA_FW=y\nCONFIG_MTD_SPLIT_TPLINK_FW=y\nCONFIG_MTD_SPLIT_UIMAGE_FW=y\nCONFIG_MTD_SPLIT_WRGG_FW=y\nCONFIG_MTD_VIRT_CONCAT=y\nCONFIG_NEED_DMA_MAP_STATE=y\nCONFIG_NEED_PER_CPU_KM=y\nCONFIG_NO_GENERIC_PCI_IOPORT_MAP=y\nCONFIG_NVMEM=y\nCONFIG_OF=y\nCONFIG_OF_ADDRESS=y\nCONFIG_OF_EARLY_FLATTREE=y\nCONFIG_OF_FLATTREE=y\nCONFIG_OF_GPIO=y\nCONFIG_OF_IRQ=y\nCONFIG_OF_KOBJ=y\nCONFIG_OF_MDIO=y\nCONFIG_OF_NET=y\nCONFIG_PCI=y\nCONFIG_PCI_AR71XX=y\nCONFIG_PCI_AR724X=y\nCONFIG_PCI_DISABLE_COMMON_QUIRKS=y\nCONFIG_PCI_DOMAINS=y\nCONFIG_PCI_DRIVERS_LEGACY=y\nCONFIG_PERF_USE_VMALLOC=y\nCONFIG_PGTABLE_LEVELS=2\nCONFIG_PHYLIB=y\n# CONFIG_PHY_AR7100_USB is not set\n# CONFIG_PHY_AR7200_USB is not set\n# CONFIG_PHY_ATH79_USB is not set\nCONFIG_PINCTRL=y\nCONFIG_RATIONAL=y\nCONFIG_REGMAP=y\nCONFIG_REGMAP_MMIO=y\nCONFIG_REGULATOR=y\nCONFIG_RESET_ATH79=y\nCONFIG_RESET_CONTROLLER=y\nCONFIG_SERIAL_8250_NR_UARTS=1\nCONFIG_SERIAL_8250_RUNTIME_UARTS=1\nCONFIG_SERIAL_AR933X=y\nCONFIG_SERIAL_AR933X_CONSOLE=y\nCONFIG_SERIAL_AR933X_NR_UARTS=2\nCONFIG_SERIAL_MCTRL_GPIO=y\nCONFIG_SERIAL_OF_PLATFORM=y\nCONFIG_SPI=y\nCONFIG_SPI_AR934X=y\nCONFIG_SPI_ATH79=y\nCONFIG_SPI_BITBANG=y\nCONFIG_SPI_GPIO=y\nCONFIG_SPI_MASTER=y\nCONFIG_SPI_MEM=y\n# CONFIG_SPI_RB4XX is not set\nCONFIG_SRCU=y\nCONFIG_SWCONFIG=y\nCONFIG_SWCONFIG_LEDS=y\nCONFIG_SWPHY=y\nCONFIG_SYSCTL_EXCEPTION_TRACE=y\nCONFIG_SYS_HAS_CPU_MIPS32_R2=y\nCONFIG_SYS_HAS_EARLY_PRINTK=y\nCONFIG_SYS_SUPPORTS_32BIT_KERNEL=y\nCONFIG_SYS_SUPPORTS_ARBIT_HZ=y\nCONFIG_SYS_SUPPORTS_BIG_ENDIAN=y\nCONFIG_SYS_SUPPORTS_MIPS16=y\nCONFIG_SYS_SUPPORTS_ZBOOT=y\nCONFIG_SYS_SUPPORTS_ZBOOT_UART_PROM=y\nCONFIG_TARGET_ISA_REV=2\nCONFIG_TICK_CPU_ACCOUNTING=y\nCONFIG_TINY_SRCU=y\nCONFIG_USB_SUPPORT=y\nCONFIG_USE_OF=y\n"
  },
  {
    "path": "target/linux/ath79/config-5.15",
    "content": "CONFIG_AG71XX=y\n# CONFIG_AG71XX_DEBUG is not set\nCONFIG_AG71XX_DEBUG_FS=y\nCONFIG_AR8216_PHY=y\nCONFIG_AR8216_PHY_LEDS=y\nCONFIG_ARCH_32BIT_OFF_T=y\nCONFIG_ARCH_HIBERNATION_POSSIBLE=y\nCONFIG_ARCH_KEEP_MEMBLOCK=y\nCONFIG_ARCH_MMAP_RND_BITS_MAX=15\nCONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15\nCONFIG_ARCH_SUSPEND_POSSIBLE=y\nCONFIG_AT803X_PHY=y\nCONFIG_ATH79=y\nCONFIG_ATH79_WDT=y\nCONFIG_BLK_MQ_PCI=y\nCONFIG_CEVT_R4K=y\nCONFIG_CLONE_BACKWARDS=y\nCONFIG_CMDLINE=\"rootfstype=squashfs,jffs2\"\nCONFIG_CMDLINE_BOOL=y\n# CONFIG_CMDLINE_OVERRIDE is not set\nCONFIG_COMMON_CLK=y\nCONFIG_COMPAT_32BIT_TIME=y\nCONFIG_CPU_BIG_ENDIAN=y\nCONFIG_CPU_GENERIC_DUMP_TLB=y\nCONFIG_CPU_HAS_DIEI=y\nCONFIG_CPU_HAS_PREFETCH=y\nCONFIG_CPU_HAS_RIXI=y\nCONFIG_CPU_HAS_SYNC=y\nCONFIG_CPU_MIPS32=y\nCONFIG_CPU_MIPS32_R2=y\nCONFIG_CPU_MIPSR2=y\nCONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y\nCONFIG_CPU_R4K_CACHE_TLB=y\nCONFIG_CPU_SUPPORTS_32BIT_KERNEL=y\nCONFIG_CPU_SUPPORTS_HIGHMEM=y\nCONFIG_CPU_SUPPORTS_MSA=y\nCONFIG_CRYPTO_LIB_POLY1305_RSIZE=2\nCONFIG_CRYPTO_RNG2=y\nCONFIG_CSRC_R4K=y\nCONFIG_DMA_NONCOHERENT=y\nCONFIG_DTC=y\nCONFIG_EARLY_PRINTK=y\nCONFIG_FIXED_PHY=y\nCONFIG_FWNODE_MDIO=y\nCONFIG_FW_LOADER_PAGED_BUF=y\nCONFIG_GENERIC_ATOMIC64=y\nCONFIG_GENERIC_CLOCKEVENTS=y\nCONFIG_GENERIC_CMOS_UPDATE=y\nCONFIG_GENERIC_CPU_AUTOPROBE=y\nCONFIG_GENERIC_FIND_FIRST_BIT=y\nCONFIG_GENERIC_GETTIMEOFDAY=y\nCONFIG_GENERIC_IOMAP=y\nCONFIG_GENERIC_IRQ_CHIP=y\nCONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y\nCONFIG_GENERIC_IRQ_SHOW=y\nCONFIG_GENERIC_LIB_ASHLDI3=y\nCONFIG_GENERIC_LIB_ASHRDI3=y\nCONFIG_GENERIC_LIB_CMPDI2=y\nCONFIG_GENERIC_LIB_LSHRDI3=y\nCONFIG_GENERIC_LIB_UCMPDI2=y\nCONFIG_GENERIC_PCI_IOMAP=y\nCONFIG_GENERIC_PHY=y\nCONFIG_GENERIC_PINCONF=y\nCONFIG_GENERIC_PINCTRL_GROUPS=y\nCONFIG_GENERIC_PINMUX_FUNCTIONS=y\nCONFIG_GENERIC_SCHED_CLOCK=y\nCONFIG_GENERIC_SMP_IDLE_THREAD=y\nCONFIG_GENERIC_TIME_VSYSCALL=y\nCONFIG_GPIOLIB=y\nCONFIG_GPIOLIB_IRQCHIP=y\nCONFIG_GPIO_74X164=y\nCONFIG_GPIO_ATH79=y\nCONFIG_GPIO_CDEV=y\nCONFIG_GPIO_GENERIC=y\n# CONFIG_GPIO_LATCH is not set\n# CONFIG_GPIO_RB91X_KEY is not set\nCONFIG_HANDLE_DOMAIN_IRQ=y\nCONFIG_HARDWARE_WATCHPOINTS=y\nCONFIG_HAS_DMA=y\nCONFIG_HAS_IOMEM=y\nCONFIG_HAS_IOPORT_MAP=y\nCONFIG_HZ_PERIODIC=y\nCONFIG_IMAGE_CMDLINE_HACK=y\nCONFIG_INITRAMFS_SOURCE=\"\"\nCONFIG_IRQCHIP=y\nCONFIG_IRQ_DOMAIN=y\nCONFIG_IRQ_FORCED_THREADING=y\nCONFIG_IRQ_MIPS_CPU=y\nCONFIG_IRQ_WORK=y\nCONFIG_LEDS_GPIO=y\n# CONFIG_LEDS_RESET is not set\nCONFIG_LIBFDT=y\nCONFIG_LOCK_DEBUGGING_SUPPORT=y\nCONFIG_MDIO_BITBANG=y\nCONFIG_MDIO_BUS=y\nCONFIG_MDIO_DEVICE=y\nCONFIG_MDIO_DEVRES=y\nCONFIG_MDIO_GPIO=y\nCONFIG_MEMFD_CREATE=y\n# CONFIG_MFD_RB4XX_CPLD is not set\nCONFIG_MFD_SYSCON=y\nCONFIG_MIGRATION=y\nCONFIG_MIPS=y\nCONFIG_MIPS_ASID_BITS=8\nCONFIG_MIPS_ASID_SHIFT=0\nCONFIG_MIPS_CLOCK_VSYSCALL=y\n# CONFIG_MIPS_CMDLINE_BUILTIN_EXTEND is not set\n# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set\nCONFIG_MIPS_CMDLINE_FROM_DTB=y\nCONFIG_MIPS_EBPF_JIT=y\nCONFIG_MIPS_L1_CACHE_SHIFT=5\nCONFIG_MIPS_LD_CAN_LINK_VDSO=y\n# CONFIG_MIPS_NO_APPENDED_DTB is not set\nCONFIG_MIPS_RAW_APPENDED_DTB=y\nCONFIG_MIPS_SPRAM=y\nCONFIG_MODULES_USE_ELF_REL=y\nCONFIG_MTD_CFI_ADV_OPTIONS=y\nCONFIG_MTD_CFI_GEOMETRY=y\n# CONFIG_MTD_CFI_I2 is not set\n# CONFIG_MTD_CFI_INTELEXT is not set\nCONFIG_MTD_CMDLINE_PARTS=y\n# CONFIG_MTD_MAP_BANK_WIDTH_1 is not set\n# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set\nCONFIG_MTD_PARSER_CYBERTAN=y\nCONFIG_MTD_PHYSMAP=y\nCONFIG_MTD_SPI_NOR=y\nCONFIG_MTD_SPLIT_ELF_FW=y\nCONFIG_MTD_SPLIT_LZMA_FW=y\nCONFIG_MTD_SPLIT_SEAMA_FW=y\nCONFIG_MTD_SPLIT_TPLINK_FW=y\nCONFIG_MTD_SPLIT_UIMAGE_FW=y\nCONFIG_MTD_SPLIT_WRGG_FW=y\nCONFIG_MTD_VIRT_CONCAT=y\nCONFIG_NEED_DMA_MAP_STATE=y\nCONFIG_NEED_PER_CPU_KM=y\nCONFIG_NET_SELFTESTS=y\nCONFIG_NO_GENERIC_PCI_IOPORT_MAP=y\nCONFIG_NVMEM=y\nCONFIG_OF=y\nCONFIG_OF_ADDRESS=y\nCONFIG_OF_EARLY_FLATTREE=y\nCONFIG_OF_FLATTREE=y\nCONFIG_OF_GPIO=y\nCONFIG_OF_IRQ=y\nCONFIG_OF_KOBJ=y\nCONFIG_OF_MDIO=y\nCONFIG_PCI=y\nCONFIG_PCI_AR71XX=y\nCONFIG_PCI_AR724X=y\nCONFIG_PCI_DISABLE_COMMON_QUIRKS=y\nCONFIG_PCI_DOMAINS=y\nCONFIG_PCI_DRIVERS_LEGACY=y\nCONFIG_PERF_USE_VMALLOC=y\nCONFIG_PGTABLE_LEVELS=2\nCONFIG_PHYLIB=y\n# CONFIG_PHY_AR7100_USB is not set\n# CONFIG_PHY_AR7200_USB is not set\n# CONFIG_PHY_ATH79_USB is not set\nCONFIG_PINCTRL=y\n# CONFIG_PINCTRL_PISTACHIO is not set\nCONFIG_PTP_1588_CLOCK_OPTIONAL=y\nCONFIG_RATIONAL=y\nCONFIG_REGMAP=y\nCONFIG_REGMAP_MMIO=y\nCONFIG_REGULATOR=y\nCONFIG_RESET_ATH79=y\nCONFIG_RESET_CONTROLLER=y\nCONFIG_SERIAL_8250_NR_UARTS=1\nCONFIG_SERIAL_8250_RUNTIME_UARTS=1\nCONFIG_SERIAL_AR933X=y\nCONFIG_SERIAL_AR933X_CONSOLE=y\nCONFIG_SERIAL_AR933X_NR_UARTS=2\nCONFIG_SERIAL_MCTRL_GPIO=y\nCONFIG_SERIAL_OF_PLATFORM=y\nCONFIG_SPI=y\nCONFIG_SPI_AR934X=y\nCONFIG_SPI_ATH79=y\nCONFIG_SPI_BITBANG=y\nCONFIG_SPI_GPIO=y\nCONFIG_SPI_MASTER=y\nCONFIG_SPI_MEM=y\n# CONFIG_SPI_RB4XX is not set\nCONFIG_SRCU=y\nCONFIG_SWCONFIG=y\nCONFIG_SWCONFIG_LEDS=y\nCONFIG_SWPHY=y\nCONFIG_SYSCTL_EXCEPTION_TRACE=y\nCONFIG_SYS_HAS_CPU_MIPS32_R2=y\nCONFIG_SYS_HAS_EARLY_PRINTK=y\nCONFIG_SYS_SUPPORTS_32BIT_KERNEL=y\nCONFIG_SYS_SUPPORTS_ARBIT_HZ=y\nCONFIG_SYS_SUPPORTS_BIG_ENDIAN=y\nCONFIG_SYS_SUPPORTS_MIPS16=y\nCONFIG_SYS_SUPPORTS_ZBOOT=y\nCONFIG_SYS_SUPPORTS_ZBOOT_UART_PROM=y\nCONFIG_TARGET_ISA_REV=2\nCONFIG_TICK_CPU_ACCOUNTING=y\nCONFIG_TINY_SRCU=y\nCONFIG_USB_SUPPORT=y\nCONFIG_USE_OF=y\n"
  },
  {
    "path": "target/linux/ath79/dts/ar1022_iodata_wn-ag300dgr.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9344.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"iodata,wn-ag300dgr\", \"qca,ar9344\";\n\tmodel = \"I-O DATA WN-AG300DGR\";\n\n\taliases {\n\t\tled-boot = &led_router;\n\t\tled-failsafe = &led_router;\n\t\tled-running = &led_router;\n\t\tled-upgrade = &led_router;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_router: router {\n\t\t\tlabel = \"green:router\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\tchildren {\n\t\t\tlabel = \"green:children\";\n\t\t\tgpios = <&gpio 2 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\teco {\n\t\t\tlabel = \"green:eco\";\n\t\t\tgpios = <&gpio 3 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tnotification {\n\t\t\tlabel = \"amber:notification\";\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan2g {\n\t\t\tlabel = \"green:wlan2g\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\twlan5g {\n\t\t\tlabel = \"green:wlan5g\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\teco {\n\t\t\tlabel = \"eco\";\n\t\t\tgpios = <&gpio 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_1>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\trouter {\n\t\t\tlabel = \"router\";\n\t\t\tgpios = <&gpio 1 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_0>;\n\t\t\tlinux,input-type = <EV_SW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\tauto {\n\t\t\tlabel = \"auto\";\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_0>;\n\t\t\tlinux,input-type = <EV_SW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\tchildren {\n\t\t\tlabel = \"children\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_1>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n};\n\n&ref {\n\tclock-frequency = <25000000>;\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x030000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x030000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x040000 0xf10000>;\n\t\t\t};\n\n\t\t\tpartition@f50000 {\n\t\t\t\tlabel = \"manufacture\";\n\t\t\t\treg = <0xf50000 0x40000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@f90000 {\n\t\t\t\tlabel = \"backup\";\n\t\t\t\treg = <0xf90000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@fa0000 {\n\t\t\t\tlabel = \"storage\";\n\t\t\t\treg = <0xfa0000 0x50000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@ff0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0xff0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t\tphy-mode = \"rgmii\";\n\n\t\tqca,ar8327-initvals = <\n\t\t\t0x04 0x07a00000 /* PORT0 PAD MODE CTRL */\n\t\t\t0x7c 0x000000fe /* PORT0_STATUS */\n\t\t>;\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tpll-data = <0x06000000 0x00000101 0x00001616>;\n\n\tphy-mode = \"rgmii\";\n\tphy-handle = <&phy0>;\n\n\tgmac-config {\n\t\tdevice = <&gmac>;\n\t\trgmii-gmac0 = <1>;\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&usb {\n\tstatus = \"okay\";\n};\n\n&usb_phy {\n\tstatus = \"okay\";\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tqca,no-eeprom;\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar1022_sitecom_wlr-7100.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9344.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"Sitecom WLR-7100 (X7 AC1200)\";\n\tcompatible = \"sitecom,wlr-7100\", \"qca,ar9344\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\twlan2g {\n\t\t\tlabel = \"2.4GHz\";\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twlan5g {\n\t\t\tlabel = \"5GHz\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tops {\n\t\t\tlabel = \"white:ops\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_power: power {\n\t\t\tlabel = \"amber:power\";\n\t\t\tgpios = <&gpio 2 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\twlan2g {\n\t\t\tlabel = \"blue:wlan2g\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tpll-data = <0x06000000 0x00000101 0x00001616>;\n\n\tphy-mode = \"rgmii\";\n\tphy-handle = <&phy0>;\n\n\tgmac-config {\n\t\tdevice = <&gmac>;\n\t\trgmii-gmac0 = <1>;\n\t};\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t\tphy-mode = \"rgmii\";\n\n\t\tqca,ar8327-initvals = <\n\t\t\t0x04 0x87a00000 /* PORT0 PAD Mode */\n\t\t\t0x0c 0x01000000 /* PORT6 PAD Mode */\n\t\t\t0x10 0x80000000 /* PWS_REG_VALUE */\n\t\t\t0x7c 0x000000fe /* PORT0_STATUS */\n\t\t\t0x94 0x000000fe /* PORT6_STATUS */\n\t\t>;\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n\n\twifi@0,0 {\n\t\tcompatible = \"qcom,ath10k\";\n\t\treg = <0x0000 0 0 0 0>;\n\t};\n};\n\n&ref {\n\tclock-frequency = <25000000>;\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x030000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tuenv: partition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x030000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x040000 0x750000>;\n\t\t\t};\n\n\t\t\tpartition@790000 {\n\t\t\t\tlabel = \"backup\";\n\t\t\t\treg = <0x790000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@7a0000 {\n\t\t\t\tlabel = \"storage\";\n\t\t\t\treg = <0x7a0000 0x050000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tart: partition@7f0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0x7f0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&usb {\n\tstatus = \"okay\";\n};\n\n&usb_phy {\n\tstatus = \"okay\";\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tqca,no-eeprom;\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar7100.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ath79.dtsi\"\n\n/ {\n\tcompatible = \"qca,ar7100\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200\";\n\t};\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu@0 {\n\t\t\tdevice_type = \"cpu\";\n\t\t\tcompatible = \"mips,mips24Kc\";\n\t\t\tclocks = <&pll ATH79_CLK_CPU>;\n\t\t\treg = <0>;\n\t\t};\n\t};\n\n\tahb {\n\t\tapb {\n\t\t\tddr_ctrl: memory-controller@18000000 {\n\t\t\t\tcompatible = \"qca,ar7100-ddr-controller\";\n\t\t\t\treg = <0x18000000 0x100>;\n\n\t\t\t\t#qca,ddr-wb-channel-cells = <1>;\n\t\t\t};\n\n\t\t\tuart: uart@18020000 {\n\t\t\t\tcompatible = \"ns16550a\";\n\t\t\t\treg = <0x18020000 0x20>;\n\t\t\t\tinterrupts = <3>;\n\n\t\t\t\tclocks = <&pll ATH79_CLK_AHB>;\n\t\t\t\tclock-names = \"uart\";\n\n\t\t\t\treg-io-width = <4>;\n\t\t\t\treg-shift = <2>;\n\t\t\t\tno-loopback-test;\n\t\t\t};\n\n\t\t\tusb_phy: usb-phy@18030000 {\n\t\t\t\tcompatible = \"qca,ar7100-usb-phy\";\n\t\t\t\treg = <0x18030000 0x10>;\n\n\t\t\t\treset-names = \"usb-phy\", \"usb-host\", \"usb-ohci-dll\";\n\t\t\t\tresets = <&rst 4>, <&rst 5>, <&rst 6>;\n\n\t\t\t\t#phy-cells = <0>;\n\n\t\t\t\tstatus = \"disabled\";\n\t\t\t};\n\n\t\t\tgpio: gpio@18040000 {\n\t\t\t\tcompatible = \"qca,ar7100-gpio\";\n\t\t\t\treg = <0x18040000 0x28>;\n\t\t\t\tinterrupts = <2>;\n\n\t\t\t\tngpios = <16>;\n\n\t\t\t\tgpio-controller;\n\t\t\t\t#gpio-cells = <2>;\n\n\t\t\t\tinterrupt-controller;\n\t\t\t\t#interrupt-cells = <2>;\n\t\t\t};\n\n\t\t\tpll: pll-controller@18050000 {\n\t\t\t\tcompatible = \"qca,ar7100-pll\", \"syscon\";\n\t\t\t\treg = <0x18050000 0x20>;\n\n\t\t\t\tclock-names = \"ref\";\n\t\t\t\t/* The board must provides the ref clock */\n\n\t\t\t\t#clock-cells = <1>;\n\t\t\t\tclock-output-names = \"cpu\", \"ddr\", \"ahb\";\n\t\t\t};\n\n\t\t\twdt: wdt@18060008 {\n\t\t\t\tcompatible = \"qca,ar7130-wdt\";\n\t\t\t\treg = <0x18060008 0x8>;\n\n\t\t\t\tinterrupts = <4>;\n\n\t\t\t\tclocks = <&pll ATH79_CLK_AHB>;\n\t\t\t\tclock-names = \"wdt\";\n\t\t\t};\n\n\t\t\tpci_intc: interrupt-controller@18060018 {\n\t\t\t\tcompatible = \"qca,ar7100-misc-intc\";\n\t\t\t\treg = <0x18060018 0x4>;\n\t\t\t\tinterrupt-parent = <&cpuintc>;\n\t\t\t\tinterrupts = <2>;\n\t\t\t\tinterrupt-controller;\n\t\t\t\t#interrupt-cells = <1>;\n\t\t\t};\n\n\t\t\trst: reset-controller@18060024 {\n\t\t\t\tcompatible = \"qca,ar7100-reset\";\n\t\t\t\treg = <0x18060024 0x4>;\n\n\t\t\t\t#reset-cells = <1>;\n\t\t\t};\n\n\t\t\tpcie0: pcie-controller@17010000 {\n\t\t\t\tcompatible = \"qca,ar7100-pci\";\n\t\t\t\t#address-cells = <3>;\n\t\t\t\t#size-cells = <2>;\n\t\t\t\tbus-range = <0x0 0x0>;\n\t\t\t\treg = <0x17010000 0x100>;\n\t\t\t\treg-names = \"cfg_base\";\n\t\t\t\tranges = <0x2000000 0 0x10000000 0x10000000 0 0x07000000\t/* pci memory */\n\t\t\t\t\t  0x1000000 0 0x00000000 0x0000000 0 0x000001>;\t\t/* io space */\n\n\t\t\t\tdevice_type = \"pci\";\n\n\t\t\t\tinterrupt-parent = <&pci_intc>;\n\t\t\t\tinterrupts = <4>;\n\n\t\t\t\t#interrupt-cells = <1>;\n\n\t\t\t\tinterrupt-map-mask = <0xf800 0 0 0>;\n\t\t\t\tinterrupt-map = <0x8800 0 0 0 &pci_intc 0\n\t\t\t\t\t\t 0x9000 0 0 0 &pci_intc 1\n\t\t\t\t\t\t 0x9800 0 0 0 &pci_intc 2>;\n\n\t\t\t\tstatus = \"disabled\";\n\t\t\t};\n\t\t};\n\t};\n\n\tusb2: usb@1b000000 {\n\t\tcompatible = \"generic-ehci\";\n\t\treg = <0x1b000000 0x1000>;\n\n\t\tinterrupt-parent = <&cpuintc>;\n\t\tinterrupts = <3>;\n\n\t\tphy-names = \"usb-phy\";\n\t\tphys = <&usb_phy>;\n\n\t\thas-synopsys-hc-bug;\n\n\t\tstatus = \"disabled\";\n\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t};\n\n\tusb1: usb@1c000000 {\n\t\tcompatible = \"generic-ohci\";\n\t\treg = <0x1c000000 0x1000>;\n\n\t\tinterrupt-parent = <&miscintc>;\n\t\tinterrupts = <6>;\n\n\t\tphy-names = \"usb-phy\";\n\t\tphys = <&usb_phy>;\n\n\t\tstatus = \"disabled\";\n\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t};\n\n\tspi: spi@1f000000 {\n\t\tcompatible = \"qca,ar7100-spi\";\n\t\treg = <0x1f000000 0x10>;\n\n\t\tclocks = <&pll ATH79_CLK_AHB>;\n\t\tclock-names = \"ahb\";\n\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tstatus = \"disabled\";\n\t};\n};\n\n&cpuintc {\n\tqca,ddr-wb-channel-interrupts = <2>, <3>, <4>, <5>;\n\tqca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>,\n\t\t\t\t<&ddr_ctrl 0>, <&ddr_ctrl 1>;\n};\n\n&miscintc {\n\tcompatible = \"qca,ar7100-misc-intc\";\n};\n\n&eth0 {\n\tcompatible = \"qca,ar7100-eth\", \"syscon\";\n\treg = <0x19000000 0x200\n\t\t0x18070000 0x4>;\n\n\tpll-data = <0x00110000 0x00001099 0x00991099>;\n\tpll-reg = <0x4 0x10 17>;\n\tpll-handle = <&pll>;\n\tphy-mode = \"rgmii\";\n\n\tresets = <&rst 9>;\n\treset-names = \"mac\";\n\tqca,mac-idx = <0>;\n};\n\n&mdio1 {\n\tbuiltin-switch;\n};\n\n&eth1 {\n\tcompatible = \"qca,ar7100-eth\", \"syscon\";\n\treg = <0x1a000000 0x200\n\t\t0x18070004 0x4>;\n\n\tpll-data = <0x00110000 0x00001099 0x00991099>;\n\tpll-reg = <0x4 0x14 19>;\n\tpll-handle = <&pll>;\n\n\tphy-mode = \"rgmii\";\n\n\tresets = <&rst 13>;\n\treset-names = \"mac\";\n\tqca,mac-idx = <1>;\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar7100_mikrotik_routerboard-4xx.dtsi",
    "content": "// SPDX-License-Identifier: GPL-1.0-or-later OR MIT\n\n#include \"ar7100.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\taliases {\n\t\tled-boot = &led_user;\n\t\tled-failsafe = &led_user;\n\t\tled-running = &led_user;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_user: user {\n\t\t\tlabel = \"yellow:user\";\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\tled1 {\n\t\t\tlabel = \"green:led1\";\n\t\t\tgpios = <&cpld_gpio 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled2 {\n\t\t\tlabel = \"green:led2\";\n\t\t\tgpios = <&cpld_gpio 2 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled3 {\n\t\t\tlabel = \"green:led3\";\n\t\t\tgpios = <&cpld_gpio 1 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled4 {\n\t\t\tlabel = \"green:led4\";\n\t\t\tgpios = <&cpld_gpio 3 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled5 {\n\t\t\tlabel = \"green:led5\";\n\t\t\tgpios = <&cpld_gpio 8 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&gpio {\n\tngpios = <31>;\n\tgpio-line-names =\n\t\t\"\",     \"\", \"\", \"\", \"LED\", \"RDY\",  \"\",  \"MDC\",\n\t\t\"MDIO\", \"\", \"\", \"\", \"\",    \"\",     \"\",  \"\",\n\t\t\"\",     \"\", \"\", \"\", \"\",    \"\",     \"\",  \"\",\n\t\t\"\",     \"\", \"\", \"\", \"\",    \"\",     \"\",  \"\";\n};\n\n&pcie0 {\n\tstatus = \"okay\";\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tcompatible = \"mikrotik,rb4xx-spi\";\n\n\tflash@0 {\n\t\tcompatible = \"pm25lv512\", \"jedec,spi-nor\";\n\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"mikrotik,routerboot-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"routerboot1\";\n\t\t\t\treg = <0x0 0x0>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\thard_config {\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tbios {\n\t\t\t\tsize = <0x1000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\trouterboot2 {\n\t\t\t\tlabel = \"routerboot2\";\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tsoft_config {\n\t\t\t};\n\t\t};\n\t};\n\n\tcpld@1 {\n\t\tcompatible = \"mikrotik,rb4xx-cpld\";\n\n\t\treg = <1>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tcpld_gpio: gpio {\n\t\t\tcompatible = \"mikrotik,rb4xx-gpio\";\n\n\t\t\tbase = <32>;\n\n\t\t\tgpio-controller;\n\t\t\t#gpio-cells = <2>;\n\t\t\tgpio-line-names =\n\t\t\t\t\"LED1\", \"LED2\", \"LED3\", \"LED4\",\n\t\t\t\t\"FAN\",  \"ALE\",  \"CLE\",  \"nCE\",\n\t\t\t\t\"LED5\";\n\t\t};\n\n\t\tnand {\n\t\t\tcompatible = \"mikrotik,rb4xx-nand\";\n\n\t\t\tgpios = <&cpld_gpio 5 GPIO_ACTIVE_HIGH>, // ALE\n\t\t\t\t<&cpld_gpio 6 GPIO_ACTIVE_HIGH>, // CLE\n\t\t\t\t<&cpld_gpio 7 GPIO_ACTIVE_HIGH>, // nCE\n\t\t\t\t<&gpio      5 GPIO_ACTIVE_HIGH>; // RDY\n\n\t\t\tpartitions {\n\t\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\n\t\t\t\tpartition@0 {\n\t\t\t\t\tlabel = \"booter\";\n\t\t\t\t\treg = <0x0000000 0x0040000>;\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\tpartition@40000 {\n\t\t\t\t\tlabel = \"kernel\";\n\t\t\t\t\treg = <0x0040000 0x0800000>;\n\t\t\t\t};\n\n\t\t\t\tpartition@840000 {\n\t\t\t\t\tlabel = \"ubi\";\n\t\t\t\t\treg = <0x0840000 0x77c0000>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tphy-handle = <&phy0>;\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar7161_adtran_bsap1800-v2.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar7161_adtran_bsap1880.dtsi\"\n\n/ {\n\tmodel = \"Adtran/Bluesocket BSAP-1800 v2\";\n\tcompatible = \"adtran,bsap1800-v2\", \"qca,ar7161\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar7161_adtran_bsap1840.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar7161_adtran_bsap1880.dtsi\"\n\n/ {\n\tmodel = \"Adtran/Bluesocket BSAP-1840\";\n\tcompatible = \"adtran,bsap1840\", \"qca,ar7161\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar7161_adtran_bsap1880.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar7100.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200n8\";\n\t};\n\n\taliases {\n\t\tled-boot = &led_status_green;\n\t\tled-failsafe = &led_status_yellow;\n\t\tled-running = &led_status_green;\n\t\tled-upgrade = &led_status_yellow;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twlan5g {\n\t\t\tlabel = \"green:wifi5g\";\n\t\t\tgpios = <&gpio 8 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\n\t\twlan2g {\n\t\t\tlabel = \"green:wifi2g\";\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\tled_status_green: status_green {\n\t\t\tlabel = \"green:status\";\n\t\t\tgpios = <&gpio 5 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_status_yellow: status_yellow {\n\t\t\tlabel = \"yellow:status\";\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 6 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy-mask = <0x1>;\n\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tphy-mode = \"rgmii-id\";\n\tphy-handle = <&phy0>;\n};\n\n&pcie0 {\n\tstatus = \"okay\";\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\t\t\tcompatible = \"ecoscentric,redboot-fis-partitions\";\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar7161_aruba_ap-105.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar7100.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"aruba,ap-105\", \"qca,ar7161\";\n\tmodel = \"Aruba AP-105\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,9600\";\n\t};\n\n\taliases {\n\t\tled-boot = &led_power_green;\n\t\tled-failsafe = &led_power_red;\n\t\tled-running = &led_power_green;\n\t\tled-upgrade = &led_power_green;\n\t\tlabel-mac-device = &eth0;\n\t};\n\n\textosc: ref {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-output-names = \"ref\";\n\t\tclock-frequency = <40000000>;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power_green: power_green {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 3 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_power_red: power_red {\n\t\t\tlabel = \"red:power\";\n\t\t\tgpios = <&gpio 2 GPIO_ACTIVE_LOW>;\n\t\t\tpanic-indicator;\n\t\t};\n\n\t\twifi_2g_red {\n\t\t\tlabel = \"red:wlan2g\";\n\t\t\tgpios = <&gpio 8 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twifi_5g_red {\n\t\t\tlabel = \"red:wlan5g\";\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tath9k-leds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twifi_2g_green {\n\t\t\tlabel = \"green:wlan2g\";\n\t\t\tgpios = <&ath9k0 5 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\twifi_5g_green {\n\t\t\tlabel = \"green:wlan5g\";\n\t\t\tgpios = <&ath9k1 5 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 6 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\ti2c {\n\t\tcompatible = \"i2c-gpio\";\n\n\t\tsda-gpios = <&gpio 5 GPIO_ACTIVE_LOW>;\n\t\tscl-gpios = <&gpio 4 GPIO_ACTIVE_LOW>;\n\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\ttpm@29 {\n\t\t\tcompatible = \"atmel,at97sc3203s\";\n\t\t\treg = <0x29>;\n\n\t\t\t/* triggering it, will also kill system */\n\t\t\treset-gpios = <&gpio 7 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&pcie0 {\n\tstatus = \"okay\";\n\n\tath9k0: wifi@0,11 { /* 2.4 GHz */\n\t\tcompatible = \"pci168c,0029\";\n\t\tnvmem-cells = <&macaddr_hwinfo_1c>;\n\t\tnvmem-cell-names = \"mac-address\";\n\t\tmac-address-increment = <1>;\n\t\treg = <0x8800 0 0 0 0>;\n\t\t#gpio-cells = <2>;\n\t\tgpio-controller;\n\t};\n\n\tath9k1: wifi@0,12 { /* 5 GHz */\n\t\tcompatible = \"pci168c,0029\";\n\t\tnvmem-cells = <&macaddr_hwinfo_1c>;\n\t\tnvmem-cell-names = \"mac-address\";\n\t\tmac-address-increment = <2>;\n\t\treg = <0x9000 0 0 0 0>;\n\t\t#gpio-cells = <2>;\n\t\tgpio-controller;\n\t};\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy-mask = <0x1>;\n\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\tnvmem-cells = <&macaddr_hwinfo_1c>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tpll-data = <0x00110000 0x00001099 0x00991099>;\n\n\tphy-mode = \"rgmii\";\n\tphy-handle = <&phy0>;\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x40000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x40000 0xfa0000>;\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t};\n\n\t\t\thwinfo: partition@fe0000 {\n\t\t\t\tlabel = \"hwinfo\";\n\t\t\t\treg = <0xfe0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@ff0000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0xff0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&hwinfo {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_hwinfo_1c: macaddr@1c {\n\t\treg = <0x1c 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar7161_buffalo_wzr-600dhp.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar7161_buffalo_wzr-hp-ag300h.dtsi\"\n\n/ {\n\tcompatible = \"buffalo,wzr-600dhp\", \"qca,ar7161\";\n\tmodel = \"Buffalo WZR-600DHP\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar7161_buffalo_wzr-hp-ag300h.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar7161_buffalo_wzr-hp-ag300h.dtsi\"\n\n/ {\n\tcompatible = \"buffalo,wzr-hp-ag300h\", \"qca,ar7161\";\n\tmodel = \"Buffalo WZR-HP-AG300H\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar7161_buffalo_wzr-hp-ag300h.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar7100.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\taliases {\n\t\tled-boot = &led_diag;\n\t\tled-failsafe = &led_diag;\n\t\tled-upgrade = &led_diag;\n\t};\n\n\textosc: ref {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-output-names = \"ref\";\n\t\tclock-frequency = <40000000>;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_diag: diag {\n\t\t\tlabel = \"red:diag\";\n\t\t\tgpios = <&gpio 1 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tath9k-leds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tband2g_a {\n\t\t\tlabel = \"amber:band2g\";\n\t\t\tgpios = <&ath9k0 1 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tusb {\n\t\t\tlabel = \"green:usb\";\n\t\t\tgpios = <&ath9k0 3 GPIO_ACTIVE_LOW>;\n\t\t\ttrigger-sources = <&usb_ohci_port>, <&usb_ehci_port>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\n\t\tband2g_g {\n\t\t\tlabel = \"green:band2g\";\n\t\t\tgpios = <&ath9k0 5 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\tband5g_g {\n\t\t\tlabel = \"green:band5g\";\n\t\t\tgpios = <&ath9k1 1 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\n\t\trouter {\n\t\t\tlabel = \"green:router\";\n\t\t\tgpios = <&ath9k1 3 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tmovie_engine {\n\t\t\tlabel = \"blue:movie_engine\";\n\t\t\tgpios = <&ath9k1 4 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tband5g_a {\n\t\t\tlabel = \"amber:band5g\";\n\t\t\tgpios = <&ath9k1 5 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\tusb {\n\t\t\tlabel = \"usb\";\n\t\t\tlinux,code = <BTN_2>;\n\t\t\tgpios = <&gpio 3 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\taoss {\n\t\t\tlabel = \"aoss\";\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tgpios = <&gpio 5 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\trouter_auto {\n\t\t\tlabel = \"router_auto\";\n\t\t\tlinux,code = <BTN_6>;\n\t\t\tlinux,input-type = <EV_SW>;\n\t\t\tgpios = <&gpio 6 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\trouter_off {\n\t\t\tlabel = \"router_off\";\n\t\t\tlinux,code = <BTN_5>;\n\t\t\tlinux,input-type = <EV_SW>;\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\tmovie_engine {\n\t\t\tlabel = \"movie_engine\";\n\t\t\tlinux,code = <BTN_7>;\n\t\t\tlinux,input-type = <EV_SW>;\n\t\t\tgpios = <&gpio 8 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tgpio-export {\n\t\tcompatible = \"gpio-export\";\n\n\t\tgpio_usb_power {\n\t\t\tgpio-export,name = \"buffalo:power:usb\";\n\t\t\tgpio-export,output = <1>;\n\t\t\tgpios = <&gpio 2 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n\n\tflash {\n\t\tcompatible = \"mtd-concat\";\n\n\t\tdevices = <&flash0 &flash1>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0000000 0x0040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x0040000 0x0010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tart: partition@50000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0x0050000 0x0010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@60000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x0060000 0x1f90000>;\n\t\t\t};\n\n\t\t\tpartition@1ff0000 {\n\t\t\t\tlabel = \"user_property\";\n\t\t\t\treg = <0x1ff0000 0x0010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&usb_phy {\n\tstatus = \"okay\";\n};\n\n&usb1 {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\tstatus = \"okay\";\n\n\tusb_ohci_port: port@1 {\n\t\treg = <1>;\n\t\t#trigger-source-cells = <0>;\n\t};\n};\n\n&usb2 {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\tstatus = \"okay\";\n\n\tusb_ehci_port: port@1 {\n\t\treg = <1>;\n\t\t#trigger-source-cells = <0>;\n\t};\n};\n\n&pcie0 {\n\tstatus = \"okay\";\n\n\tath9k0: wifi@0,11 {\n\t\tcompatible = \"pci168c,0029\";\n\t\treg = <0x8800 0 0 0 0>;\n\t\tqca,no-eeprom;\n\t\t#gpio-cells = <2>;\n\t\tgpio-controller;\n\t};\n\n\tath9k1: wifi@0,12 {\n\t\tcompatible = \"pci168c,0029\";\n\t\treg = <0x9000 0 0 0 0>;\n\t\tqca,no-eeprom;\n\t\t#gpio-cells = <2>;\n\t\tgpio-controller;\n\t};\n};\n\n&pll {\n\tclocks = <&extosc>;\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\n\tflash0: flash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <50000000>;\n\t\tm25p,fast-read;\n\t};\n\n\tflash1: flash@1 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <1>;\n\t\tspi-max-frequency = <50000000>;\n\t\tm25p,fast-read;\n\t};\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy4: ethernet-phy@4 {\n\t\treg = <4>;\n\t\tphy-mode = \"rgmii\";\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tnvmem-cells = <&macaddr_art_120c>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tfixed-link {\n\t\tspeed = <1000>;\n\t\tfull-duplex;\n\t};\n};\n\n&eth1 {\n\tstatus = \"okay\";\n\n\tnvmem-cells = <&macaddr_art_520c>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <1>;\n\n\tphy-handle = <&phy4>;\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_120c: macaddr@120c {\n\t\treg = <0x120c 0x6>;\n\t};\n\n\tmacaddr_art_520c: macaddr@520c {\n\t\treg = <0x520c 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar7161_dlink_dir-825-b1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar7100.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"dlink,dir-825-b1\", \"qca,ar7161\";\n\tmodel = \"D-Link DIR825B1\";\n\n\taliases {\n\t\tled-boot = &led_power_orange;\n\t\tled-failsafe = &led_power_orange;\n\t\tled-running = &led_power_blue;\n\t\tled-upgrade = &led_power_orange;\n\t};\n\n\textosc: ref {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-output-names = \"ref\";\n\t\tclock-frequency = <40000000>;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tusb {\n\t\t\tlabel = \"blue:usb\";\n\t\t\tgpios = <&gpio 0 GPIO_ACTIVE_LOW>;\n\t\t\ttrigger-sources = <&usb_ohci_port>, <&usb_ehci_port>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\n\t\tled_power_orange: power_orange {\n\t\t\tlabel = \"orange:power\";\n\t\t\tgpios = <&gpio 1 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\tled_power_blue: power_blue {\n\t\t\tlabel = \"blue:power\";\n\t\t\tgpios = <&gpio 2 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"blue:wps\";\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tplanet_orange {\n\t\t\tlabel = \"orange:planet\";\n\t\t\tgpios = <&gpio 6 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tplanet_blue {\n\t\t\tlabel = \"blue:planet\";\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tath9k-leds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twlan2g {\n\t\t\tlabel = \"blue:wlan2g\";\n\t\t\tgpios = <&ath9k0 5 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\twlan5g {\n\t\t\tlabel = \"blue:wlan5g\";\n\t\t\tgpios = <&ath9k1 5 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 3 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tgpios = <&gpio 8 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\trtl8366s {\n\t\tcompatible = \"realtek,rtl8366s\";\n\t\tgpio-sda = <&gpio 5 GPIO_ACTIVE_HIGH>;\n\t\tgpio-sck = <&gpio 7 GPIO_ACTIVE_HIGH>;\n\t\trealtek,initvals = <0x06 0x0108>;\n\n\t\tmdio-bus {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tstatus = \"okay\";\n\n\t\t\tphy-mask = <0x10>;\n\n\t\t\tphy4: ethernet-phy@4 {\n\t\t\t\treg = <4>;\n\t\t\t\tphy-mode = \"rgmii\";\n\t\t\t};\n\t\t};\n\t};\n};\n\n&usb1 {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\tstatus = \"okay\";\n\n\tusb_ohci_port: port@1 {\n\t\treg = <1>;\n\t\t#trigger-source-cells = <0>;\n\t};\n};\n\n&usb2 {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\tstatus = \"okay\";\n\n\tusb_ehci_port: port@1 {\n\t\treg = <1>;\n\t\t#trigger-source-cells = <0>;\n\t};\n};\n\n&usb_phy {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\tstatus = \"okay\";\n\n\tath9k0: wifi@0,11 {\n\t\tcompatible = \"pci168c,0029\";\n\t\treg = <0x8800 0 0 0 0>;\n\t\tqca,no-eeprom;\n\t\t#gpio-cells = <2>;\n\t\tgpio-controller;\n\t};\n\n\tath9k1: wifi@0,12 {\n\t\tcompatible = \"pci168c,0029\";\n\t\treg = <0x9000 0 0 0 0>;\n\t\tqca,no-eeprom;\n\t\t#gpio-cells = <2>;\n\t\tgpio-controller;\n\t};\n};\n\n&pll {\n\tclocks = <&extosc>;\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"config\";\n\t\t\t\treg = <0x040000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x050000 0x610000>;\n\t\t\t};\n\n\t\t\tpartition@660000 {\n\t\t\t\tlabel = \"caldata\";\n\t\t\t\treg = <0x660000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@670000 {\n\t\t\t\tlabel = \"unknown\";\n\t\t\t\treg = <0x670000 0x190000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tpll-data = <0x11110000 0x00001099 0x00991099>;\n\n\tfixed-link {\n\t\tspeed = <1000>;\n\t\tfull-duplex;\n\t};\n};\n\n&eth1 {\n\tstatus = \"okay\";\n\n\tpll-data = <0x11110000 0x00001099 0x00991099>;\n\n\tphy-handle = <&phy4>;\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar7161_jjplus_ja76pf2.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar7100.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"jjPlus JA76PF2\";\n\tcompatible = \"jjplus,ja76pf2\", \"qca,ar7161\";\n\n\tmemory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x0 0x4000000>;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200n8\";\n\t};\n\n\taliases {\n\t\tled-boot = &led_d2;\n\t\tled-failsafe = &led_d2;\n\t\tled-running = &led_d2;\n\t\tled-upgrade = &led_d2;\n\t};\n\n\textosc: ref {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-output-names = \"ref\";\n\t\tclock-frequency = <40000000>;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_d2: d2 {\n\t\t\tlabel = \"green:d2\";\n\t\t\tgpios = <&gpio 5 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\td3 {\n\t\t\tlabel = \"green:d3\";\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\td4 {\n\t\t\tlabel = \"green:d4\";\n\t\t\tgpios = <&gpio 3 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\tsw1 {\n\t\t\tlabel = \"sw1\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\tsw2 {\n\t\t\tlabel = \"sw2\";\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tgpios = <&gpio 8 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy-mask = <0x1>;\n\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t\tphy-mode = \"rgmii\";\n\t};\n\n\tphy4: ethernet-phy@4 {\n\t\treg = <4>;\n\t\tphy-mode = \"rgmii\";\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tphy-handle = <&phy0>;\n};\n\n&eth1 {\n\tstatus = \"okay\";\n\n\tphy-handle = <&phy4>;\n};\n\n&pcie0 {\n\tstatus = \"okay\";\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\t\t\tcompatible = \"ecoscentric,redboot-fis-partitions\";\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar7161_meraki_mr16.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar7100.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"meraki,mr16\", \"qca,ar7161\";\n\tmodel = \"Meraki MR16\";\n\n\taliases {\n\t\tled-boot = &led_power_orange;\n\t\tled-failsafe = &led_power_orange;\n\t\tled-running = &led_power_green;\n\t\tled-upgrade = &led_power_orange;\n\t};\n\n\textosc: ref {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-output-names = \"ref\";\n\t\tclock-frequency = <40000000>;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twifi1 {\n\t\t\tlabel = \"green:wifi1\";\n\t\t\tgpios = <&gpio 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twifi2 {\n\t\t\tlabel = \"green:wifi2\";\n\t\t\tgpios = <&gpio 1 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twifi3 {\n\t\t\tlabel = \"green:wifi3\";\n\t\t\tgpios = <&gpio 2 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twifi4 {\n\t\t\tlabel = \"green:wifi4\";\n\t\t\tgpios = <&gpio 3 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twan {\n\t\t\tlabel = \"green:wan\";\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_power_orange: power_orange {\n\t\t\tlabel = \"orange:power\";\n\t\t\tgpios = <&gpio 5 GPIO_ACTIVE_LOW>;\n\t\t\tpanic-indicator;\n\t\t};\n\n\t\tled_power_green: power_green {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 6 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&pcie0 {\n\tstatus = \"okay\";\n\n\tath9k0: wifi@0,11 { /* 2.4 GHz */\n\t\tcompatible = \"pci168c,0029\";\n\t\treg = <0x8800 0 0 0 0>;\n\t\tqca,no-eeprom;\n\t\tnvmem-cells = <&macaddr_config_66>;\n\t\tnvmem-cell-names = \"mac-address\";\n\t\tmac-address-increment = <1>;\n\t\t#gpio-cells = <2>;\n\t\tgpio-controller;\n\t};\n\n\tath9k1: wifi@0,12 { /* 5 GHz */\n\t\tcompatible = \"pci168c,0029\";\n\t\treg = <0x9000 0 0 0 0>;\n\t\tqca,no-eeprom;\n\t\tnvmem-cells = <&macaddr_config_66>;\n\t\tnvmem-cell-names = \"mac-address\";\n\t\tmac-address-increment = <2>;\n\t\t#gpio-cells = <2>;\n\t\tgpio-controller;\n\t};\n};\n\n&pll {\n\tclocks = <&extosc>;\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy-mask = <0x1>;\n\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\tnvmem-cells = <&macaddr_config_66>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tpll-data = <0x00110000 0x00001099 0x00991099>;\n\n\tphy-mode = \"rgmii\";\n\tphy-handle = <&phy0>;\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x40000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x40000 0x40000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tconfig: partition@80000 {\n\t\t\t\tlabel = \"config\";\n\t\t\t\treg = <0x80000 0x20000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@a0000 {\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0xa0000 0xf40000>;\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t};\n\n\t\t\tpartition@fe0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0xfe0000 0x20000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&config {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_config_66: macaddr@66 {\n\t\treg = <0x66 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar7161_mikrotik_routerboard-493g.dts",
    "content": "// SPDX-License-Identifier: GPL-1.0-or-later OR MIT\n\n#include \"ar7100_mikrotik_routerboard-4xx.dtsi\"\n\n/ {\n\tcompatible = \"mikrotik,routerboard-493g\", \"qca,ar7161\";\n\tmodel = \"MikroTik RouterBOARD 493G\";\n\n\taliases {\n\t\tmdio-gpio0 = &mdio_gpio0;\n\t};\n};\n\n&spi {\n\tsdcard: mmc-slot@2 {\n\t\tcompatible = \"mmc-spi-slot\";\n\n\t\treg = <2>;\n\t\tspi-max-frequency = <25000000>;\n\t};\n};\n\n&eth1 {\n\tstatus = \"okay\";\n\n\tphy-handle = <&gpio_phy0>;\n\n\tmdio_gpio0: mdio-gpio {\n\t\tcompatible = \"virtual,mdio-gpio\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tgpios = <&gpio 7 GPIO_ACTIVE_HIGH>, // MDC\n\t\t\t<&gpio 8 GPIO_ACTIVE_HIGH>; // MDIO\n\n\t\tgpio_phy0: ethernet-phy@0 {\n\t\t\treg = <0>;\n\t\t};\n\t};\n};\n\n&usb_phy {\n\tstatus = \"okay\";\n};\n\n&usb2 {\n\tstatus = \"okay\";\n};\n\n&usb1 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar7161_netgear_wndap360.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar7100.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"netgear,wndap360\", \"qca,ar7161\";\n\tmodel = \"Netgear WNDAP360\";\n\n\taliases {\n\t\tled-boot = &led_power_orange;\n\t\tled-failsafe = &led_power_orange;\n\t\tled-running = &led_power_orange;\n\t\tled-upgrade = &led_power_orange;\n\t};\n\n\textosc: ref {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-output-names = \"ref\";\n\t\tclock-frequency = <40000000>;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power_orange: power_orange {\n\t\t\tlabel = \"orange:power\";\n\t\t\tgpios = <&gpio 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tath9k-leds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twifi_2g_green {\n\t\t\tlabel = \"green:wlan2g\";\n\t\t\tgpios = <&ath9k0 5 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\twifi_5g_green {\n\t\t\tlabel = \"green:wlan5g\";\n\t\t\tgpios = <&ath9k1 5 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 8 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy-mask = <0x0f>;\n\tphy1: ethernet-phy@1 {\n\t\treg = <0x1>;\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tphy-mode = \"rgmii\";\n\tphy-handle = <&phy1>;\n\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <50000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x40000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x790000>;\n\t\t\t};\n\n\t\t\tpartition@7e0000 {\n\t\t\t\tlabel = \"nvram\";\n\t\t\t\treg = <0x7e0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tart: partition@7f0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0x7f0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pcie0 {\n\tstatus = \"okay\";\n\n\tath9k0: wifi@0,11 {\n\t\tcompatible = \"pci168c,0029\";\n\t\treg = <0x8800 0 0 0 0>;\n\t\tqca,no-eeprom;\n\t\tnvmem-cells = <&macaddr_art_120c>;\n\t\tnvmem-cell-names = \"mac-address\";\n\t\t#gpio-cells = <2>;\n\t\tgpio-controller;\n\t};\n\n\tath9k1: wifi@0,12 {\n\t\tcompatible = \"pci168c,0029\";\n\t\treg = <0x9000 0 0 0 0>;\n\t\tqca,no-eeprom;\n\t\tnvmem-cells = <&macaddr_art_520c>;\n\t\tnvmem-cell-names = \"mac-address\";\n\t\tmac-address-increment = <1>;\n\t\t#gpio-cells = <2>;\n\t\tgpio-controller;\n\t};\n};\n\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n\n\tmacaddr_art_120c: macaddr@120c {\n\t\treg = <0x120c 0x6>;\n\t};\n\n\tmacaddr_art_520c: macaddr@520c {\n\t\treg = <0x520c 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar7161_netgear_wndr.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar7100.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/mtd/partitions/uimage.h>\n\n/ {\n\taliases {\n\t\tled-boot = &led_power_orange;\n\t\tled-failsafe = &led_power_orange;\n\t\tled-running = &led_power_green;\n\t\tled-upgrade = &led_power_orange;\n\t};\n\n\textosc: ref {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-output-names = \"ref\";\n\t\tclock-frequency = <40000000>;\n\t};\n\n\treset-leds {\n\t\tcompatible = \"reset-leds\";\n\n\t\tusb_led {\n\t\t\tlabel = \"green:usb\";\n\t\t\tresets = <&rst 12>;\n\t\t\ttrigger-sources = <&usb_ohci_port>, <&usb_ehci_port>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twps {\n\t\t\tlabel = \"orange:wps\";\n\t\t\tgpios = <&gpio 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_power_green: power_green {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 2 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_power_orange: power_orange {\n\t\t\tlabel = \"orange:power\";\n\t\t\tgpios = <&gpio 1 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\twps_green {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twan_green {\n\t\t\tlabel = \"green:wan\";\n\t\t\tgpios = <&gpio 6 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tath9k-leds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twlan2g {\n\t\t\tlabel = \"green:wlan2g\";\n\t\t\tgpios = <&ath9k0 5 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\t\twlan5g {\n\t\t\tlabel = \"blue:wlan5g\";\n\t\t\tgpios = <&ath9k1 5 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tgpios = <&gpio 3 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 8 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\trfkill {\n\t\t\tlabel = \"rfkill\";\n\t\t\tlinux,code = <KEY_RFKILL>;\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\trtl8366s {\n\t\tcompatible = \"realtek,rtl8366s\";\n\n\t\tgpio-sda = <&gpio 5 GPIO_ACTIVE_HIGH>;\n\t\tgpio-sck = <&gpio 7 GPIO_ACTIVE_HIGH>;\n\n\t\tmdio-bus {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tstatus = \"okay\";\n\n\t\t\tphy-mask = <0x10>;\n\n\t\t\tphy4: ethernet-phy@4 {\n\t\t\t\treg = <4>;\n\t\t\t\tphy-mode = \"rgmii\";\n\t\t\t};\n\t\t};\n\t};\n};\n\n&usb_phy {\n\tstatus = \"okay\";\n};\n\n&usb1 {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\tstatus = \"okay\";\n\n\tusb_ohci_port: port@1 {\n\t\treg = <1>;\n\t\t#trigger-source-cells = <0>;\n\t};\n};\n\n&usb2 {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\tstatus = \"okay\";\n\n\tusb_ehci_port: port@1 {\n\t\treg = <1>;\n\t\t#trigger-source-cells = <0>;\n\t};\n};\n\n&pcie0 {\n\tstatus = \"okay\";\n\n\tath9k0: wifi@0,11 {\n\t\tcompatible = \"pci168c,0029\";\n\t\treg = <0x8800 0 0 0 0>;\n\n\t\t#gpio-cells = <2>;\n\t\tgpio-controller;\n\n\t\t/* all WNDR3700 variants have four antennae dedicated\n\t\t * to the 2.4GHz radio. Two antennae are available for\n\t\t * each chain. The following configuration is the\n\t\t * default setting which taken from the vendor's wifi\n\t\t * code for that radio.\n\t\t *\n\t\t * All possible options [GPIO6,GPIO7,GPIO8,GPIO9]:\n\t\t *\t[0,1,0,1], [0,1,1,0], [1,0,0,1], [1,0,1,0]\n\t\t */\n\t\tantenna-demux {\n\t\t\tgpio-hog;\n\t\t\tline-name = \"fixed antenna group 1\";\n\t\t\tgpios = <6 GPIO_ACTIVE_LOW>,\n\t\t\t\t<7 GPIO_ACTIVE_HIGH>,\n\t\t\t\t<8 GPIO_ACTIVE_LOW>,\n\t\t\t\t<9 GPIO_ACTIVE_HIGH>;\n\t\t\toutput-high;\n\t\t};\n\t};\n\n\tath9k1: wifi@0,12 {\n\t\tcompatible = \"pci168c,0029\";\n\t\treg = <0x9000 0 0 0 0>;\n\n\t\t#gpio-cells = <2>;\n\t\tgpio-controller;\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions: partitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\t\t};\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tpll-data = <0x11110000 0x00001099 0x00991099>;\n\n\tfixed-link {\n\t\tspeed = <1000>;\n\t\tfull-duplex;\n\t};\n};\n\n&eth1 {\n\tstatus = \"okay\";\n\n\tpll-data = <0x11110000 0x00001099 0x00991099>;\n\n\tphy-handle = <&phy4>;\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar7161_netgear_wndr3700-v2.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar7161_netgear_wndr.dtsi\"\n\n/ {\n\tcompatible = \"netgear,wndr3700-v2\", \"qca,ar7161\";\n\tmodel = \"Netgear WNDR3700 v2\";\n\n\taliases {\n\t\tlabel-mac-device = &eth0;\n\t};\n};\n\n&partitions {\n\tpartition@0 {\n\t\tlabel = \"u-boot\";\n\t\treg = <0x000000 0x050000>;\n\t\tread-only;\n\t};\n\n\tpartition@50000 {\n\t\tlabel = \"u-boot-env\";\n\t\treg = <0x050000 0x020000>;\n\t};\n\n\tpartition@70000 {\n\t\tlabel = \"firmware\";\n\t\treg = <0x070000 0xf80000>;\n\t\tcompatible = \"openwrt,uimage\", \"denx,uimage\";\n\t\topenwrt,ih-magic = <0x33373031>;\n\t\topenwrt,ih-type = <IH_TYPE_FILESYSTEM>;\n\t};\n\n\tart: partition@ff0000 {\n\t\tlabel = \"art\";\n\t\treg = <0xff0000 0x010000>;\n\t\tread-only;\n\t};\n};\n\n&ath9k0 {\n\tnvmem-cells = <&macaddr_art_c>, <&cal_art_1000>;\n\tnvmem-cell-names = \"mac-address\", \"calibration\";\n};\n\n&ath9k1 {\n\tnvmem-cells = <&macaddr_art_0>, <&cal_art_5000>;\n\tnvmem-cell-names = \"mac-address\", \"calibration\";\n};\n\n&eth0 {\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&eth1 {\n\tnvmem-cells = <&macaddr_art_6>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n\n\tmacaddr_art_6: macaddr@6 {\n\t\treg = <0x6 0x6>;\n\t};\n\n\tmacaddr_art_c: macaddr@c {\n\t\treg = <0xc 0x6>;\n\t};\n\n\tcal_art_1000: cal@1000 {\n\t\treg = <0x1000 0xeb8>;\n\t};\n\n\tcal_art_5000: cal@5000 {\n\t\treg = <0x5000 0xeb8>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar7161_netgear_wndr3700.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar7161_netgear_wndr.dtsi\"\n\n/ {\n\tcompatible = \"netgear,wndr3700\", \"qca,ar7161\";\n\tmodel = \"Netgear WNDR3700\";\n\n\taliases {\n\t\tlabel-mac-device = &eth0;\n\t};\n};\n\n&partitions {\n\tpartition@0 {\n\t\tlabel = \"u-boot\";\n\t\treg = <0x000000 0x050000>;\n\t\tread-only;\n\t};\n\n\tpartition@50000 {\n\t\tlabel = \"u-boot-env\";\n\t\treg = <0x050000 0x020000>;\n\t};\n\n\tpartition@70000 {\n\t\tlabel = \"firmware\";\n\t\treg = <0x070000 0x780000>;\n\t\tcompatible = \"openwrt,uimage\", \"denx,uimage\";\n\t\topenwrt,ih-magic = <0x33373030>;\n\t\topenwrt,ih-type = <IH_TYPE_FILESYSTEM>;\n\t};\n\n\tart: partition@7f0000 {\n\t\tlabel = \"art\";\n\t\treg = <0x7f0000 0x010000>;\n\t\tread-only;\n\t};\n};\n\n&ath9k0 {\n\tnvmem-cells = <&macaddr_art_c>, <&cal_art_1000>;\n\tnvmem-cell-names = \"mac-address\", \"calibration\";\n};\n\n&ath9k1 {\n\tnvmem-cells = <&macaddr_art_0>, <&cal_art_5000>;\n\tnvmem-cell-names = \"mac-address\", \"calibration\";\n\n\t/* The original WNDR3700(v1) variant have four antennae dedicated\n\t * to the 5GHz radio as well. Again, two antennae are available for\n\t * each chain to switch between. The following configuration is the\n\t * default setting which taken from the vendor's wifi\n\t * code for that radio.\n\t *\n\t * All possible options [GPIO6,GPIO7,GPIO8,GPIO9]:\n\t *\t[0,1,0,1], [0,1,1,0], [1,0,0,1], [1,0,1,0]\n\t */\n\tantenna-demux {\n\t\tgpio-hog;\n\t\tline-name = \"fixed antenna group 2\";\n\t\tgpios = <6 GPIO_ACTIVE_LOW>,\n\t\t\t<7 GPIO_ACTIVE_HIGH>,\n\t\t\t<8 GPIO_ACTIVE_HIGH>,\n\t\t\t<9 GPIO_ACTIVE_LOW>;\n\t\toutput-high;\n\t};\n};\n\n&eth0 {\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&eth1 {\n\tnvmem-cells = <&macaddr_art_6>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n\n\tmacaddr_art_6: macaddr@6 {\n\t\treg = <0x6 0x6>;\n\t};\n\n\tmacaddr_art_c: macaddr@c {\n\t\treg = <0xc 0x6>;\n\t};\n\n\tcal_art_1000: cal@1000 {\n\t\treg = <0x1000 0xeb8>;\n\t};\n\n\tcal_art_5000: cal@5000 {\n\t\treg = <0x5000 0xeb8>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar7161_netgear_wndr3800.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar7161_netgear_wndr.dtsi\"\n\n/ {\n\tcompatible = \"netgear,wndr3800\", \"qca,ar7161\";\n\tmodel = \"Netgear WNDR3800\";\n\n\taliases {\n\t\tlabel-mac-device = &eth0;\n\t};\n};\n\n&partitions {\n\tpartition@0 {\n\t\tlabel = \"u-boot\";\n\t\treg = <0x000000 0x050000>;\n\t\tread-only;\n\t};\n\n\tpartition@50000 {\n\t\tlabel = \"u-boot-env\";\n\t\treg = <0x050000 0x020000>;\n\t\tread-only;\n\t};\n\n\tpartition@70000 {\n\t\tlabel = \"firmware\";\n\t\treg = <0x070000 0xf80000>;\n\t\tcompatible = \"openwrt,uimage\", \"denx,uimage\";\n\t\topenwrt,ih-magic = <0x33373031>;\n\t\topenwrt,ih-type = <IH_TYPE_FILESYSTEM>;\n\t};\n\n\tart: partition@ff0000 {\n\t\tlabel = \"art\";\n\t\treg = <0xff0000 0x010000>;\n\t\tread-only;\n\t};\n};\n\n&ath9k0 {\n\tnvmem-cells = <&macaddr_art_c>, <&cal_art_1000>;\n\tnvmem-cell-names = \"mac-address\", \"calibration\";\n};\n\n&ath9k1 {\n\tnvmem-cells = <&macaddr_art_0>, <&cal_art_5000>;\n\tnvmem-cell-names = \"mac-address\", \"calibration\";\n};\n\n&eth0 {\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&eth1 {\n\tnvmem-cells = <&macaddr_art_6>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n\n\tmacaddr_art_6: macaddr@6 {\n\t\treg = <0x6 0x6>;\n\t};\n\n\tmacaddr_art_c: macaddr@c {\n\t\treg = <0xc 0x6>;\n\t};\n\n\tcal_art_1000: cal@1000 {\n\t\treg = <0x1000 0xeb8>;\n\t};\n\n\tcal_art_5000: cal@5000 {\n\t\treg = <0x5000 0xeb8>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar7161_netgear_wndr3800ch.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar7161_netgear_wndr.dtsi\"\n\n/ {\n\tcompatible = \"netgear,wndr3800ch\", \"qca,ar7161\";\n\tmodel = \"Netgear WNDR3800CH\";\n\n\taliases {\n\t\tlabel-mac-device = &eth0;\n\t};\n};\n\n&partitions {\n\tpartition@0 {\n\t\tlabel = \"u-boot\";\n\t\treg = <0x000000 0x050000>;\n\t\tread-only;\n\t};\n\n\tpartition@50000 {\n\t\tlabel = \"u-boot-env\";\n\t\treg = <0x050000 0x020000>;\n\t\tread-only;\n\t};\n\n\tpartition@70000 {\n\t\tlabel = \"firmware\";\n\t\treg = <0x070000 0xf80000>;\n\t\tcompatible = \"openwrt,uimage\", \"denx,uimage\";\n\t\topenwrt,ih-magic = <0x33373031>;\n\t\topenwrt,ih-type = <IH_TYPE_FILESYSTEM>;\n\t};\n\n\tart: partition@ff0000 {\n\t\tlabel = \"art\";\n\t\treg = <0xff0000 0x010000>;\n\t\tread-only;\n\t};\n};\n\n&ath9k0 {\n\tnvmem-cells = <&macaddr_art_c>, <&cal_art_1000>;\n\tnvmem-cell-names = \"mac-address\", \"calibration\";\n};\n\n&ath9k1 {\n\tnvmem-cells = <&macaddr_art_0>, <&cal_art_5000>;\n\tnvmem-cell-names = \"mac-address\", \"calibration\";\n};\n\n&eth0 {\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&eth1 {\n\tnvmem-cells = <&macaddr_art_6>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n\n\tmacaddr_art_6: macaddr@6 {\n\t\treg = <0x6 0x6>;\n\t};\n\n\tmacaddr_art_c: macaddr@c {\n\t\treg = <0xc 0x6>;\n\t};\n\n\tcal_art_1000: cal@1000 {\n\t\treg = <0x1000 0xeb8>;\n\t};\n\n\tcal_art_5000: cal@5000 {\n\t\treg = <0x5000 0xeb8>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar7161_netgear_wndrmac-v1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar7161_netgear_wndr.dtsi\"\n\n/ {\n\tcompatible = \"netgear,wndrmac-v1\", \"qca,ar7161\";\n\tmodel = \"Netgear WNDRMAC v1\";\n\n\taliases {\n\t\tlabel-mac-device = &eth0;\n\t};\n};\n\n&partitions {\n\tpartition@0 {\n\t\tlabel = \"u-boot\";\n\t\treg = <0x000000 0x050000>;\n\t\tread-only;\n\t};\n\n\tpartition@50000 {\n\t\tlabel = \"u-boot-env\";\n\t\treg = <0x050000 0x020000>;\n\t};\n\n\tpartition@70000 {\n\t\tlabel = \"firmware\";\n\t\treg = <0x070000 0xf80000>;\n\t\tcompatible = \"openwrt,uimage\", \"denx,uimage\";\n\t\topenwrt,ih-magic = <0x33373031>;\n\t\topenwrt,ih-type = <IH_TYPE_FILESYSTEM>;\n\t};\n\n\tart: partition@ff0000 {\n\t\tlabel = \"art\";\n\t\treg = <0xff0000 0x010000>;\n\t\tread-only;\n\t};\n};\n\n&ath9k0 {\n\tnvmem-cells = <&macaddr_art_c>, <&cal_art_1000>;\n\tnvmem-cell-names = \"mac-address\", \"calibration\";\n};\n\n&ath9k1 {\n\tnvmem-cells = <&macaddr_art_0>, <&cal_art_5000>;\n\tnvmem-cell-names = \"mac-address\", \"calibration\";\n};\n\n&eth0 {\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&eth1 {\n\tnvmem-cells = <&macaddr_art_6>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n\n\tmacaddr_art_6: macaddr@6 {\n\t\treg = <0x6 0x6>;\n\t};\n\n\tmacaddr_art_c: macaddr@c {\n\t\treg = <0xc 0x6>;\n\t};\n\n\tcal_art_1000: cal@1000 {\n\t\treg = <0x1000 0xeb8>;\n\t};\n\n\tcal_art_5000: cal@5000 {\n\t\treg = <0x5000 0xeb8>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar7161_netgear_wndrmac-v2.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar7161_netgear_wndr.dtsi\"\n\n/ {\n\tcompatible = \"netgear,wndrmac-v2\", \"qca,ar7161\";\n\tmodel = \"Netgear WNDRMAC v2\";\n\n\taliases {\n\t\tlabel-mac-device = &eth0;\n\t};\n};\n\n&partitions {\n\tpartition@0 {\n\t\tlabel = \"u-boot\";\n\t\treg = <0x000000 0x050000>;\n\t\tread-only;\n\t};\n\n\tpartition@50000 {\n\t\tlabel = \"u-boot-env\";\n\t\treg = <0x050000 0x020000>;\n\t\tread-only;\n\t};\n\n\tpartition@70000 {\n\t\tlabel = \"firmware\";\n\t\treg = <0x070000 0xf80000>;\n\t\tcompatible = \"openwrt,uimage\", \"denx,uimage\";\n\t\topenwrt,ih-magic = <0x33373031>;\n\t\topenwrt,ih-type = <IH_TYPE_FILESYSTEM>;\n\t};\n\n\tart: partition@ff0000 {\n\t\tlabel = \"art\";\n\t\treg = <0xff0000 0x010000>;\n\t\tread-only;\n\t};\n};\n\n&ath9k0 {\n\tnvmem-cells = <&macaddr_art_c>, <&cal_art_1000>;\n\tnvmem-cell-names = \"mac-address\", \"calibration\";\n};\n\n&ath9k1 {\n\tnvmem-cells = <&macaddr_art_0>, <&cal_art_5000>;\n\tnvmem-cell-names = \"mac-address\", \"calibration\";\n};\n\n&eth0 {\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&eth1 {\n\tnvmem-cells = <&macaddr_art_6>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n\n\tmacaddr_art_6: macaddr@6 {\n\t\treg = <0x6 0x6>;\n\t};\n\n\tmacaddr_art_c: macaddr@c {\n\t\treg = <0xc 0x6>;\n\t};\n\n\tcal_art_1000: cal@1000 {\n\t\treg = <0x1000 0xeb8>;\n\t};\n\n\tcal_art_5000: cal@5000 {\n\t\treg = <0x5000 0xeb8>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar7161_siemens_ws-ap3610.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar7100.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"siemens,ws-ap3610\", \"qca,ar7161\";\n\tmodel = \"Siemens WS-AP3610\";\n\n\taliases {\n\t\tled-boot = &led_power_green;\n\t\tled-failsafe = &led_power_red;\n\t\tled-running = &led_power_green;\n\t\tled-upgrade = &led_power_red;\n\t\tlabel-mac-device = &eth0;\n\t};\n\n\textosc: ref {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-output-names = \"ref\";\n\t\tclock-frequency = <40000000>;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power_green: led_power_green {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_power_red: led_power_red {\n\t\t\tlabel = \"red:power\";\n\t\t\tgpios = <&gpio 8 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_wlan5_blue {\n\t\t\tlabel = \"blue:wlan5\";\n\t\t\tgpios = <&gpio 2 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\tled_wlan5_green {\n\t\t\tlabel = \"green:wlan5\";\n\t\t\tgpios = <&gpio 3 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_wlan2_blue {\n\t\t\tlabel = \"blue:wlan2\";\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\n\t\tled_wlan2_green {\n\t\t\tlabel = \"green:wlan2\";\n\t\t\tgpios = <&gpio 5 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&pcie0 {\n\tstatus = \"okay\";\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy0: ethernet-phy@0 {\n\t\t/*\n\t\t * When the compatible-is missing, PHY autodetection\n\t\t * is performed, but the PHY-ID reads all 0xff.\n\t\t *\n\t\t * Linux does not create the device in this case,\n\t\t * and the reset is never even de-asserted.\n\t\t */\n\t\tcompatible = \"ethernet-phy-id0143.bca2\",\n\t\t\t\t\"ethernet-phy-ieee802.3-c22\";\n\t\treg = <0>;\n\n\t\tresets = <&rst 8>;\n\t\treset-names = \"phy\";\n\t\treset-assert-us = <10000>;\n\t\treset-deassert-us = <10000>;\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tphy-mode = \"rgmii-id\";\n\tphy-handle = <&phy0>;\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <50000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x40000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"u-boot-bak\";\n\t\t\t\treg = <0x40000 0x40000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@80000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x80000 0xe00000>;\n\t\t\t};\n\n\t\t\tpartition@e80000 {\n\t\t\t\tlabel = \"cfg1\";\n\t\t\t\treg = <0xe80000 0x40000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@ec0000 {\n\t\t\t\tlabel = \"cfg2\";\n\t\t\t\treg = <0xec0000 0x40000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@f00000 {\n\t\t\t\tlabel = \"nvram1\";\n\t\t\t\treg = <0xf00000 0x40000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@f40000 {\n\t\t\t\tlabel = \"nvram2\";\n\t\t\t\treg = <0xf40000 0x40000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@f80000 {\n\t\t\t\tlabel = \"rsvd1\";\n\t\t\t\treg = <0xf80000 0x40000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@fc0000 {\n\t\t\t\tlabel = \"rsvd2\";\n\t\t\t\treg = <0xfc0000 0x40000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar7161_ubnt_routerstation-pro.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar7161_ubnt_routerstation.dtsi\"\n\n/ {\n\tcompatible = \"ubnt,routerstation-pro\", \"qca,ar7161\";\n\tmodel = \"Ubiquiti RouterStation Pro\";\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t};\n\n\tphy4: ethernet-phy@4 {\n\t\treg = <4>;\n\t};\n};\n\n&eth0 {\n\tphy-mode = \"rgmii\";\n\tphy-handle = <&phy4>;\n};\n\n&eth1 {\n\tphy-mode = \"rgmii\";\n\tphy-handle = <&phy0>;\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar7161_ubnt_routerstation.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar7161_ubnt_routerstation.dtsi\"\n\n/ {\n\tcompatible = \"ubnt,routerstation\", \"qca,ar7161\";\n\tmodel = \"Ubiquiti RouterStation\";\n};\n\n&eth0 {\n\tphy-mode = \"mii\";\n\n\tfixed-link {\n\t\tspeed = <100>;\n\t\tfull-duplex;\n\t};\n};\n\n&eth1 {\n\tphy-mode = \"rmii\";\n\n\tfixed-link {\n\t\tspeed = <100>;\n\t\tfull-duplex;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar7161_ubnt_routerstation.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar7100.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\taliases {\n\t\tled-boot = &led_rf;\n\t\tled-failsafe = &led_rf;\n\t\tled-running = &led_rf;\n\t\tled-upgrade = &led_rf;\n\t};\n\n\textosc: ref {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-output-names = \"ref\";\n\t\tclock-frequency = <40000000>;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_rf: rf_green {\n\t\t\tlabel = \"green:rf\";\n\t\t\tgpios = <&gpio 2 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\twps {\n\t\t\tlabel = \"sw4\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 8 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n};\n\n&eth1 {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\tstatus = \"okay\";\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"ecoscentric,redboot-fis-partitions\";\n\t\t};\n\t};\n};\n\n&usb_phy {\n\tstatus = \"okay\";\n};\n\n&usb1 {\n\tstatus = \"okay\";\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\n\tusb_ohci_port: port@1 {\n\t\treg = <1>;\n\t\t#trigger-source-cells = <0>;\n\t};\n};\n\n&usb2 {\n\tstatus = \"okay\";\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\n\tusb_ehci_port: port@1 {\n\t\treg = <1>;\n\t\t#trigger-source-cells = <0>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar7240.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar724x.dtsi\"\n\n/ {\n\tusb_phy: usb-phy {\n\t\tcompatible = \"qca,ar7200-usb-phy\";\n\n\t\treset-names = \"usb-phy\", \"usb-ohci-dll\";\n\t\tresets = <&rst 4>, <&rst 3>;\n\n\t\t#phy-cells = <0>;\n\n\t\tstatus = \"disabled\";\n\t};\n};\n\n&ahb {\n\tusb: usb@1b000000 {\n\t\tcompatible = \"generic-ohci\";\n\t\treg = <0x1b000000 0x1000>;\n\n\t\tinterrupts = <3>;\n\n\t\tresets = <&rst 5>;\n\t\treset-names = \"usb-host\";\n\n\t\tphy-names = \"usb-phy\";\n\t\tphys = <&usb_phy>;\n\n\t\tstatus = \"disabled\";\n\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t};\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tcompatible = \"qca,ar7240-mdio\";\n\tbuiltin-switch;\n\n\tbuiltin_switch: switch0@1f {\n\t\tcompatible = \"qca,ar7240sw\";\n\n\t\treg = <0x1f>;\n\t\tresets = <&rst 8>;\n\t\treset-names = \"switch\";\n\t\tqca,mib-poll-interval = <500>;\n\n\t\tmdio-bus {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\n\t\t\tswphy4: ethernet-phy@4 {\n\t\t\t\treg = <4>;\n\t\t\t\tphy-mode = \"mii\";\n\t\t\t};\n\t\t};\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tcompatible = \"qca,ar7240-eth\", \"syscon\";\n\n\tpll-data = <0x00110000 0x00001099 0x00991099>;\n\n\tresets = <&rst 9>;\n\treset-names = \"mac\";\n\tphy-handle = <&swphy4>;\n};\n\n&eth1 {\n\tcompatible = \"qca,ar7240-eth\", \"syscon\";\n\n\tpll-data = <0x00110000 0x00001099 0x00991099>;\n\n\tresets = <&rst 13>;\n\treset-names = \"mac\";\n\n\tphy-mode = \"gmii\";\n\n\tfixed-link {\n\t\tspeed = <1000>;\n\t\tfull-duplex;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar7240_buffalo_whr-g301n.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar7240.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"buffalo,whr-g301n\", \"qca,ar7240\";\n\tmodel = \"Buffalo WHR-G301N\";\n\n\taliases {\n\t\tled-boot = &led_diag;\n\t\tled-failsafe = &led_diag;\n\t\tled-upgrade = &led_diag;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\trouter_on {\n\t\t\tlabel = \"router_on\";\n\t\t\tlinux,code = <BTN_2>;\n\t\t\tlinux,input-type = <EV_SW>;\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\trouter_off {\n\t\t\tlabel = \"router_off\";\n\t\t\tlinux,code = <BTN_3>;\n\t\t\tlinux,input-type = <EV_SW>;\n\t\t\tgpios = <&gpio 8 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tpinctrl-names = \"default\";\n\t\tpinctrl-0 = <&switch_led_pins>;\n\n\t\tsecurity {\n\t\t\tlabel = \"orange:security\";\n\t\t\tgpios = <&gpio 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_diag: diag {\n\t\t\tlabel = \"red:diag\";\n\t\t\tgpios = <&gpio 1 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\trouter {\n\t\t\tlabel = \"green:router\";\n\t\t\tgpios = <&gpio 6 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan1 {\n\t\t\tlabel = \"green:lan1\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan2 {\n\t\t\tlabel = \"green:lan2\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan3 {\n\t\t\tlabel = \"green:lan3\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan4 {\n\t\t\tlabel = \"green:lan4\";\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twan {\n\t\t\tlabel = \"green:wan\";\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tath9k-leds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twlan {\n\t\t\tlabel = \"green:wlan\";\n\t\t\tgpios = <&ath9k 1 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\treg = <0x0 0x3e000>;\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@3e000 {\n\t\t\t\treg = <0x3e000 0x2000>;\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\treg = <0x40000 0x3a0000>;\n\t\t\t\tlabel = \"firmware\";\n\t\t\t};\n\n\t\t\tpartition@3e0000 {\n\t\t\t\treg = <0x3e0000 0x10000>;\n\t\t\t\tlabel = \"user_property\";\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tart: partition@3f0000 {\n\t\t\t\treg = <0x3f0000 0x10000>;\n\t\t\t\tlabel = \"art\";\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&eth0 {\n\tnvmem-cells = <&macaddr_art_120c>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&eth1 {\n\tstatus = \"okay\";\n\n\tnvmem-cells = <&macaddr_art_120c>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <1>;\n};\n\n&pcie {\n\tstatus = \"okay\";\n\n\tath9k: wifi@0,0 {\n\t\tcompatible = \"pci168c,002a\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tqca,no-eeprom;\n\t\tnvmem-cells = <&macaddr_art_120c>;\n\t\tnvmem-cell-names = \"mac-address\";\n\t\t#gpio-cells = <2>;\n\t\tgpio-controller;\n\t};\n};\n\n&pinmux {\n\tswitch_led_pins: switch_led_pins {\n\t\tpinctrl-single,bits = <0x0 0x0 0xf8>;\n\t};\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_120c: macaddr@120c {\n\t\treg = <0x120c 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar7240_dlink_dir-615-e4.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar7240.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"D-Link DIR-615 E4\";\n\tcompatible = \"dlink,dir-615-e4\", \"qca,ar7240\";\n\n\taliases {\n\t\tled-boot = &led_power_amber;\n\t\tled-failsafe = &led_power_amber;\n\t\tled-running = &led_power_green;\n\t\tled-upgrade = &led_power_amber;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 8 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tpinctrl-names = \"default\";\n\t\tpinctrl-0 = <&switch_led_pins>;\n\n\t\tled_power_green: power_green {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 6 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tled_power_amber: power_amber {\n\t\t\tlabel = \"amber:power\";\n\t\t\tgpios = <&gpio 1 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"blue:wps\";\n\t\t\tgpios = <&gpio 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan1 {\n\t\t\tlabel = \"green:lan1\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan2 {\n\t\t\tlabel = \"green:lan2\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan3 {\n\t\t\tlabel = \"green:lan3\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan4 {\n\t\t\tlabel = \"green:lan4\";\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twan_amber {\n\t\t\tlabel = \"amber:wan\";\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\twan_green {\n\t\t\tlabel = \"green:wan\";\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tath9k-leds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twlan {\n\t\t\tlabel = \"green:wlan\";\n\t\t\tgpios = <&ath9k 1 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <33000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tlabel = \"nvram\";\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\treg = <0x40000 0x3b0000>;\n\t\t\t\tlabel = \"firmware\";\n\t\t\t};\n\n\t\t\tpartition@3f0000 {\n\t\t\t\treg = <0x3f0000 0x10000>;\n\t\t\t\tlabel = \"art\";\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&eth1 {\n\tstatus = \"okay\";\n};\n\n&pcie {\n\tstatus = \"okay\";\n\n\tath9k: wifi@0,0 {\n\t\tcompatible = \"pci168c,002b\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tqca,no-eeprom;\n\t\t#gpio-cells = <2>;\n\t\tgpio-controller;\n\t};\n};\n\n&pinmux {\n\tswitch_led_pins: pinmux_switch_led_pins {\n\t\tpinctrl-single,bits = <0x0 0x0 0xf8>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar7240_engenius_enh202-v1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar7240.dtsi\"\n#include \"ar724x_senao_loader-64k.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"engenius,enh202-v1\", \"qca,ar7240\";\n\tmodel = \"EnGenius ENH202 v1\";\n\n\taliases {\n\t\tled-boot = &led_rssihigh;\n\t\tled-failsafe = &led_rssihigh;\n\t\tled-running = &led_rssihigh;\n\t\tled-upgrade = &led_rssihigh;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 1 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tpinctrl-names = \"default\";\n\t\tpinctrl-0 = <&jtag_disable_pins &switch_led_disable_pins &clks_disable_pins>;\n\n\t\trssilow {\n\t\t\tlabel = \"red:rssilow\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\trssimedium {\n\t\t\tlabel = \"amber:rssimedium\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_rssihigh: rssihigh {\n\t\t\tlabel = \"green:rssihigh\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan {\n\t\t\tlabel = \"amber:lan\";\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twan {\n\t\t\tlabel = \"green:wan\";\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tath9k-leds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twlan {\n\t\t\tlabel = \"green:wlan\";\n\t\t\tgpios = <&ath9k 1 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\t};\n};\n\n&eth0 {\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&eth1 {\n\tstatus = \"okay\";\n\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&pcie {\n\tstatus = \"okay\";\n\n\tath9k: wifi@0,0 {\n\t\tcompatible = \"pci168c,002a\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tqca,no-eeprom;\n\t\t#gpio-cells = <2>;\n\t\tgpio-controller;\n\t};\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar7240_netgear_wnr1000-v2.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar7240.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/mtd/partitions/uimage.h>\n\n/ {\n\tcompatible = \"netgear,wnr1000-v2\", \"qca,ar7240\";\n\tmodel = \"Netgear WNR1000 v2\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200n8\";\n\t};\n\n\taliases {\n\t\tled-boot = &led_power_amber;\n\t\tled-failsafe = &led_power_amber;\n\t\tled-running = &led_power_green;\n\t\tled-upgrade = &led_power_amber;\n\t\tlabel-mac-device = &eth1;\n\t};\n\n\tath9k-keys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <20>;\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tgpios = <&ath9k 6 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&ath9k 7 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\trfkill {\n\t\t\tlabel = \"rfkill\";\n\t\t\tlinux,code = <KEY_RFKILL>;\n\t\t\tgpios = <&ath9k 8 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tpinctrl-names = \"default\";\n\t\tpinctrl-0 = <&jtag_disable_pins &switch_led_disable_pins &clks_disable_pins>;\n\n\t\tled_power_green: power_green {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_power_amber: power_amber {\n\t\t\tlabel = \"amber:power\";\n\t\t\tgpios = <&gpio 1 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"keep\";\n\t\t};\n\n\t\twan_green {\n\t\t\tlabel = \"green:wan\";\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twan_amber {\n\t\t\tlabel = \"amber:wan\";\n\t\t\tgpios = <&gpio 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan1_green {\n\t\t\tlabel = \"green:lan1\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan1_amber {\n\t\t\tlabel = \"amber:lan1\";\n\t\t\tgpios = <&gpio 6 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan2_green {\n\t\t\tlabel = \"green:lan2\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan2_amber {\n\t\t\tlabel = \"amber:lan2\";\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan3_green {\n\t\t\tlabel = \"green:lan3\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan3_amber {\n\t\t\tlabel = \"amber:lan3\";\n\t\t\tgpios = <&gpio 8 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan4_green {\n\t\t\tlabel = \"green:lan4\";\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan4_amber {\n\t\t\tlabel = \"amber:lan4\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tath9k-leds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twps_green {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&ath9k 5 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan_blue {\n\t\t\tlabel = \"blue:wlan\";\n\t\t\tgpios = <&ath9k 1 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x40000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x3a0000>;\n\t\t\t\tcompatible = \"openwrt,uimage\", \"denx,uimage\";\n\t\t\t\topenwrt,ih-magic = <0x31303031>;\n\t\t\t\topenwrt,ih-type = <IH_TYPE_FILESYSTEM>;\n\t\t\t};\n\n\t\t\tart: partition@3f0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0x3f0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&eth0 {\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&eth1 {\n\tstatus = \"okay\";\n\n\tnvmem-cells = <&macaddr_art_6>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&pcie {\n\tstatus = \"okay\";\n\n\tath9k: wifi@0,0 {\n\t\tcompatible = \"pci168c,002b\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tnvmem-cells = <&macaddr_art_0>;\n\t\tnvmem-cell-names = \"mac-address\";\n\t\tmac-address-increment = <1>;\n\t\tqca,no-eeprom;\n\t\t#gpio-cells = <2>;\n\t\tgpio-controller;\n\t};\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n\n\tmacaddr_art_6: macaddr@6 {\n\t\treg = <0x6 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar7240_netgear_wnr612-v2.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar7240_netgear_wnr612-v2.dtsi\"\n\n/ {\n\tcompatible = \"netgear,wnr612-v2\", \"qca,ar7240\";\n\tmodel = \"Netgear WNR612 v2\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar7240_netgear_wnr612-v2.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar7240.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/mtd/partitions/uimage.h>\n\n/ {\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t\tlabel-mac-device = &eth1;\n\t};\n\n\tath9k-keys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&ath9k 7 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tpinctrl-names = \"default\";\n\t\tpinctrl-0 = <&jtag_disable_pins &switch_led_disable_pins &clks_disable_pins>;\n\n\t\tled_power: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan1 {\n\t\t\tlabel = \"green:lan1\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan2 {\n\t\t\tlabel = \"green:lan2\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twan {\n\t\t\tlabel = \"green:wan\";\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tath9k-leds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twlan {\n\t\t\tlabel = \"green:wlan\";\n\t\t\tgpios = <&ath9k 1 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\treg = <0x0 0x40000>;\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"openwrt,uimage\", \"denx,uimage\";\n\t\t\t\topenwrt,ih-magic = <0x32303631>;\n\t\t\t\topenwrt,ih-type = <IH_TYPE_FILESYSTEM>;\n\t\t\t\treg = <0x50000 0x3a0000>;\n\t\t\t\tlabel = \"firmware\";\n\t\t\t};\n\n\t\t\tart: partition@3f0000 {\n\t\t\t\treg = <0x3f0000 0x10000>;\n\t\t\t\tlabel = \"art\";\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&eth0 {\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&eth1 {\n\tstatus = \"okay\";\n\n\tnvmem-cells = <&macaddr_art_6>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&pcie {\n\tstatus = \"okay\";\n\n\tath9k: wifi@0,0 {\n\t\tcompatible = \"pci168c,002b\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tnvmem-cells = <&macaddr_art_0>;\n\t\tnvmem-cell-names = \"mac-address\";\n\t\tmac-address-increment = <1>;\n\t\tqca,no-eeprom;\n\t\t#gpio-cells = <2>;\n\t\tgpio-controller;\n\t};\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n\n\tmacaddr_art_6: macaddr@6 {\n\t\treg = <0x6 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar7240_on_n150r.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar7240_netgear_wnr612-v2.dtsi\"\n\n/ {\n\tcompatible = \"on,n150r\", \"qca,ar7240\";\n\tmodel = \"ON Network N150R\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar7240_openmesh_om2p-v1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar7240.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"openmesh,om2p-v1\", \"qca,ar7240\";\n\tmodel = \"OpenMesh OM2P v1\";\n\n\tchosen {\n\t\t/delete-property/ bootargs;\n\t};\n\n\taliases {\n\t\tled-boot = &led_power_blue;\n\t\tled-failsafe = &led_power_blue;\n\t\tled-running = &led_power_blue;\n\t\tled-upgrade = &led_power_blue;\n\t\tlabel-mac-device = &eth0;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 1 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tpinctrl-names = \"default\";\n\t\tpinctrl-0 = <&switch_led_disable_pins>;\n\n\t\tled_power_blue: power_blue {\n\t\t\tlabel = \"blue:power\";\n\t\t\tgpios = <&gpio 0 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\twifi_green {\n\t\t\tlabel = \"green:wifi\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\twifi_red {\n\t\t\tlabel = \"red:wifi\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twifi_yellow {\n\t\t\tlabel = \"yellow:wifi\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan_blue {\n\t\t\tlabel = \"blue:lan\";\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twan_blue {\n\t\t\tlabel = \"blue:wan\";\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\twatchdog {\n\t\tcompatible = \"linux,wdt-gpio\";\n\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\thw_algo = \"toggle\";\n\t\t/* hw_margin_ms is actually 300s but driver limits it to 60s */\n\t\thw_margin_ms = <60000>;\n\t\talways-running;\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <40000000>;\n\t\tlinux,mtd-name = \"ar7240-nor0\";\n\n\t\t/* partitions are passed via bootloader */\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x040000 0x040000>;\n\t\t\t};\n\n\t\t\tpartition@80000 {\n\t\t\t\tlabel = \"custom\";\n\t\t\t\treg = <0x080000 0x140000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@1c0000 {\n\t\t\t\tlabel = \"inactive\";\n\t\t\t\treg = <0x1c0000 0x700000>;\n\t\t\t};\n\n\t\t\tpartition@8c0000 {\n\t\t\t\tlabel = \"inactive2\";\n\t\t\t\treg = <0x8c0000 0x700000>;\n\t\t\t};\n\n\t\t\tart: partition@fc0000 {\n\t\t\t\tlabel = \"ART\";\n\t\t\t\treg = <0xfc0000 0x040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&eth0 {\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&eth1 {\n\tstatus = \"okay\";\n\n\tnvmem-cells = <&macaddr_art_6>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&pcie {\n\tstatus = \"okay\";\n\n\twifi@0,0 {\n\t\tcompatible = \"pci168c,002a\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tqca,no-eeprom;\n\t\t#gpio-cells = <2>;\n\t\tgpio-controller;\n\t};\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n\n\tmacaddr_art_6: macaddr@6 {\n\t\treg = <0x6 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar7240_tplink.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar7240.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\taliases {\n\t\tled-boot = &led_system;\n\t\tled-failsafe = &led_system;\n\t\tled-running = &led_system;\n\t\tled-upgrade = &led_system;\n\t\tlabel-mac-device = &ath9k;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds: leds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tpinctrl-names = \"default\";\n\t\tpinctrl-0 = <&pinmux_switch_led_pins>;\n\n\t\tled_system: system {\n\t\t\tlabel = \"green:system\";\n\t\t\tgpios = <&gpio 1 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tqss {\n\t\t\tlabel = \"green:qss\";\n\t\t\tgpios = <&gpio 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tath9k-leds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twlan {\n\t\t\tlabel = \"green:wlan\";\n\t\t\tgpios = <&ath9k 1 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tuboot: partition@0 {\n\t\t\t\treg = <0x0 0x20000>;\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tcompatible = \"tplink,firmware\";\n\t\t\t\treg = <0x20000 0x3d0000>;\n\t\t\t\tlabel = \"firmware\";\n\t\t\t};\n\n\t\t\tart: partition@3f0000 {\n\t\t\t\treg = <0x3f0000 0x10000>;\n\t\t\t\tlabel = \"art\";\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&eth1 {\n\tstatus = \"okay\";\n};\n\n&pcie {\n\tstatus = \"okay\";\n\n\tath9k: wifi@0,0 {\n\t\treg = <0x0000 0 0 0 0>;\n\t\tqca,no-eeprom;\n\t\tnvmem-cells = <&macaddr_uboot_1fc00>;\n\t\tnvmem-cell-names = \"mac-address\";\n\t\t#gpio-cells = <2>;\n\t\tgpio-controller;\n\t};\n};\n\n&pinmux {\n\tpinmux_switch_led_pins: switch_led_pins {\n\t\tpinctrl-single,bits = <0x0 0x0 0xf8>;\n\t};\n};\n\n&uboot {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_uboot_1fc00: macaddr@1fc00 {\n\t\treg = <0x1fc00 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar7240_tplink_tl-wa.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar7240_tplink.dtsi\"\n\n&leds {\n\tlan {\n\t\tlabel = \"green:lan\";\n\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t};\n};\n\n&eth0 {\n\tcompatible = \"syscon\", \"simple-mfd\";\n};\n\n&eth1 {\n\tnvmem-cells = <&macaddr_uboot_1fc00>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&ath9k {\n\tcompatible = \"pci168c,002a\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar7240_tplink_tl-wa701nd-v1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar7240_tplink_tl-wa.dtsi\"\n\n/ {\n\tmodel = \"TP-Link TL-WA701ND v1\";\n\tcompatible = \"tplink,tl-wa701nd-v1\", \"qca,ar7240\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar7240_tplink_tl-wa730re-v1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar7240_tplink_tl-wa.dtsi\"\n\n/ {\n\tmodel = \"TP-Link TL-WA730RE v1\";\n\tcompatible = \"tplink,tl-wa730re-v1\", \"qca,ar7240\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar7240_tplink_tl-wa801nd-v1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar7240_tplink_tl-wa.dtsi\"\n\n/ {\n\tmodel = \"TP-Link TL-WA801ND v1\";\n\tcompatible = \"tplink,tl-wa801nd-v1\", \"qca,ar7240\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar7240_tplink_tl-wa830re-v1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar7240_tplink_tl-wa.dtsi\"\n\n/ {\n\tmodel = \"TP-Link TL-WA830RE v1\";\n\tcompatible = \"tplink,tl-wa830re-v1\", \"qca,ar7240\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar7240_tplink_tl-wa901nd-v1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar7240_tplink_tl-wa.dtsi\"\n\n/ {\n\tmodel = \"TP-Link TL-WA901ND v1\";\n\tcompatible = \"tplink,tl-wa901nd-v1\", \"qca,ar7240\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar7240_tplink_tl-wr.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar7240_tplink.dtsi\"\n\n&leds {\n\tlan1 {\n\t\tlabel = \"green:lan1\";\n\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t};\n\n\tlan2 {\n\t\tlabel = \"green:lan2\";\n\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t};\n\n\tlan3 {\n\t\tlabel = \"green:lan3\";\n\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t};\n\n\tlan4 {\n\t\tlabel = \"green:lan4\";\n\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t};\n\n\twan {\n\t\tlabel = \"green:wan\";\n\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t};\n};\n\n&eth0 {\n\tnvmem-cells = <&macaddr_uboot_1fc00>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <(-1)>;\n};\n\n&eth1 {\n\tnvmem-cells = <&macaddr_uboot_1fc00>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <1>;\n};\n\n&ath9k {\n\tcompatible = \"pci168c,002b\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar7240_tplink_tl-wr740n-v1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar7240_tplink_tl-wr.dtsi\"\n\n/ {\n\tmodel = \"TP-Link TL-WR740N v1/v2\";\n\tcompatible = \"tplink,tl-wr740n-v1\", \"qca,ar7240\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar7240_tplink_tl-wr740n-v3.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar7240_tplink_tl-wr.dtsi\"\n\n/ {\n\tmodel = \"TP-Link TL-WR740N v3\";\n\tcompatible = \"tplink,tl-wr740n-v3\", \"qca,ar7240\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar7240_tplink_tl-wr741-v1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar7240_tplink_tl-wr.dtsi\"\n\n/ {\n\tmodel = \"TP-Link TL-WR741N/ND v1/v2\";\n\tcompatible = \"tplink,tl-wr741-v1\", \"qca,ar7240\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar7240_tplink_tl-wr743nd-v1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar7240_tplink_tl-wr.dtsi\"\n\n/ {\n\tmodel = \"TP-Link TL-WR743ND v1\";\n\tcompatible = \"tplink,tl-wr743nd-v1\", \"qca,ar7240\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar7240_tplink_tl-wr841-v5.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar7240_tplink_tl-wr.dtsi\"\n\n/ {\n\tmodel = \"TP-Link TL-WR841N/ND v5/v6\";\n\tcompatible = \"tplink,tl-wr841-v5\", \"qca,ar7240\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar7240_tplink_tl-wr941-v4.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar7240_tplink_tl-wr.dtsi\"\n\n/ {\n\tmodel = \"TP-Link TL-WR941N/ND v4\";\n\tcompatible = \"tplink,tl-wr941-v4\", \"qca,ar7240\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar7240_ubnt_bullet-m-ar7240.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar7240.dtsi\"\n#include \"ar724x_ubnt_xm.dtsi\"\n#include \"ar724x_ubnt_xm_outdoor.dtsi\"\n\n/ {\n\tcompatible = \"ubnt,bullet-m-ar7240\", \"ubnt,xm\", \"qca,ar7240\";\n\tmodel = \"Ubiquiti Bullet M (XM AR7240)\";\n};\n\n&eth0 {\n\tfixed-link {\n\t\tspeed = <100>;\n\t\tfull-duplex;\n\t};\n};\n\n&eth1 {\n\tcompatible = \"syscon\", \"simple-mfd\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar7241.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar724x.dtsi\"\n\n/ {\n\tusb_phy: usb-phy {\n\t\tcompatible = \"qca,ar7200-usb-phy\";\n\n\t\treset-names = \"usb-phy\", \"usb-suspend-override\";\n\t\tresets = <&rst 4>, <&rst 3>;\n\n\t\t#phy-cells = <0>;\n\n\t\tstatus = \"disabled\";\n\t};\n};\n\n&gpio {\n\tngpios = <20>;\n};\n\n&ahb {\n\tusb: usb@1b000000 {\n\t\tcompatible = \"generic-ehci\";\n\t\treg = <0x1b000000 0x1000>;\n\n\t\tinterrupts = <3>;\n\n\t\tresets = <&rst 5>;\n\t\treset-names = \"usb-host\";\n\n\t\thas-transaction-translator;\n\t\tcaps-offset = <0x100>;\n\n\t\tphy-names = \"usb-phy\";\n\t\tphys = <&usb_phy>;\n\n\t\tstatus = \"disabled\";\n\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t};\n};\n\n&eth0 {\n\tcompatible = \"qca,ar7241-eth\", \"syscon\";\n\n\tpll-data = <0x00110000 0x00001099 0x00991099>;\n\n\tresets = <&rst 9>;\n\treset-names = \"mac\";\n\tphy-handle = <&swphy4>;\n};\n\n&mdio1 {\n\tstatus = \"okay\";\n\n\tresets = <&rst 23>;\n\treset-names = \"mdio\";\n\tbuiltin-switch;\n\n\tbuiltin_switch: switch0@1f {\n\t\tcompatible = \"qca,ar7240sw\";\n\n\t\treg = <0x1f>;\n\t\tresets = <&rst 8>;\n\t\treset-names = \"switch\";\n\t\tqca,mib-poll-interval = <500>;\n\n\t\tmdio-bus {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\n\t\t\tswphy4: ethernet-phy@4 {\n\t\t\t\treg = <4>;\n\t\t\t\tphy-mode = \"mii\";\n\t\t\t};\n\t\t};\n\t};\n};\n\n&eth1 {\n\tstatus = \"okay\";\n\n\tcompatible = \"qca,ar7241-eth\", \"syscon\";\n\n\tpll-data = <0x00110000 0x00001099 0x00991099>;\n\n\tresets = <&rst 13>;\n\treset-names = \"mac\";\n\n\tphy-mode = \"gmii\";\n\n\tfixed-link {\n\t\tspeed = <1000>;\n\t\tfull-duplex;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar7241_netgear_wnr2000-v3.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar7241.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/mtd/partitions/uimage.h>\n\n/ {\n\tcompatible = \"netgear,wnr2000-v3\", \"qca,ar7241\";\n\tmodel = \"Netgear WNR2000 v3\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200n8\";\n\t};\n\n\taliases {\n\t\tled-boot = &led_power_amber;\n\t\tled-failsafe = &led_power_amber;\n\t\tled-running = &led_power_green;\n\t\tled-upgrade = &led_power_amber;\n\t\tlabel-mac-device = &eth1;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tath9k-keys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&ath9k 8 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\trfkill {\n\t\t\tlabel = \"rfkill\";\n\t\t\tlinux,code = <KEY_RFKILL>;\n\t\t\tgpios = <&ath9k 9 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tpinctrl-names = \"default\";\n\t\tpinctrl-0 = <&jtag_disable_pins &switch_led_disable_pins &clks_disable_pins>;\n\n\t\twan_green {\n\t\t\tlabel = \"green:wan\";\n\t\t\tgpios = <&gpio 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twan_amber {\n\t\t\tlabel = \"amber:wan\";\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan1_green {\n\t\t\tlabel = \"green:lan1\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan1_amber {\n\t\t\tlabel = \"amber:lan1\";\n\t\t\tgpios = <&gpio 1 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan2_green {\n\t\t\tlabel = \"green:lan2\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan2_amber {\n\t\t\tlabel = \"amber:lan2\";\n\t\t\tgpios = <&gpio 6 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan3_green {\n\t\t\tlabel = \"green:lan3\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan3_amber {\n\t\t\tlabel = \"amber:lan3\";\n\t\t\tgpios = <&gpio 8 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan4_green {\n\t\t\tlabel = \"green:lan4\";\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan4_amber {\n\t\t\tlabel = \"amber:lan4\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twps_green {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tath9k-leds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power_green: power_green {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&ath9k 3 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_power_amber: power_amber {\n\t\t\tlabel = \"amber:power\";\n\t\t\tgpios = <&ath9k 2 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"keep\";\n\t\t};\n\n\t\twlan_blue {\n\t\t\tlabel = \"blue:wlan\";\n\t\t\tgpios = <&ath9k 1 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x40000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x3a0000>;\n\t\t\t\tcompatible = \"openwrt,uimage\", \"denx,uimage\";\n\t\t\t\topenwrt,ih-magic = <0x32303033>;\n\t\t\t\topenwrt,ih-type = <IH_TYPE_FILESYSTEM>;\n\t\t\t};\n\n\t\t\tart: partition@3f0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0x3f0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&eth1 {\n\tcompatible = \"qca,ar7241-eth\", \"syscon\", \"simple-mfd\";\n\n\tnvmem-cells = <&macaddr_art_6>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&pcie {\n\tstatus = \"okay\";\n\n\tath9k: wifi@0,0 {\n\t\tcompatible = \"pci168c,002e\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tnvmem-cells = <&macaddr_art_0>;\n\t\tnvmem-cell-names = \"mac-address\";\n\t\tmac-address-increment = <1>;\n\t\tqca,no-eeprom;\n\t\t#gpio-cells = <2>;\n\t\tgpio-controller;\n\t};\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n\n\tmacaddr_art_6: macaddr@6 {\n\t\treg = <0x6 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar7241_netgear_wnr2200-16m.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar7241_netgear_wnr2200.dtsi\"\n\n/ {\n\tcompatible = \"netgear,wnr2200-16m\", \"qca,ar7241\";\n\tmodel = \"Netgear WNR2200 (16M)\";\n\n\taliases {\n\t\tlabel-mac-device = &eth1;\n\t};\n};\n\n&partitions {\n\tpartition@0 {\n\t\tlabel = \"u-boot\";\n\t\treg = <0x0 0x40000>;\n\t\tread-only;\n\t};\n\n\tpartition@40000 {\n\t\tlabel = \"u-boot-env\";\n\t\treg = <0x40000 0x10000>;\n\t};\n\n\tpartition@50000 {\n\t\tlabel = \"firmware\";\n\t\treg = <0x50000 0xfa0000>;\n\t\tcompatible = \"openwrt,uimage\", \"denx,uimage\";\n\t\topenwrt,ih-magic = <0x32323030>;\n\t\topenwrt,ih-type = <IH_TYPE_FILESYSTEM>;\n\t};\n\n\tart: partition@ff0000 {\n\t\tlabel = \"art\";\n\t\treg = <0xff0000 0x10000>;\n\t\tread-only;\n\t};\n};\n\n&eth0 {\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&eth1 {\n\tnvmem-cells = <&macaddr_art_6>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&ath9k {\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <1>;\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n\n\tmacaddr_art_6: macaddr@6 {\n\t\treg = <0x6 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar7241_netgear_wnr2200-8m.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar7241_netgear_wnr2200.dtsi\"\n\n/ {\n\tcompatible = \"netgear,wnr2200-8m\", \"qca,ar7241\";\n\tmodel = \"Netgear WNR2200 (8M)\";\n\n\taliases {\n\t\tlabel-mac-device = &eth1;\n\t};\n};\n\n&partitions {\n\tpartition@0 {\n\t\tlabel = \"u-boot\";\n\t\treg = <0x0 0x40000>;\n\t\tread-only;\n\t};\n\n\tpartition@40000 {\n\t\tlabel = \"u-boot-env\";\n\t\treg = <0x40000 0x10000>;\n\t};\n\n\tpartition@50000 {\n\t\tlabel = \"firmware\";\n\t\treg = <0x50000 0x7a0000>;\n\t\tcompatible = \"openwrt,uimage\", \"denx,uimage\";\n\t\topenwrt,ih-magic = <0x32323030>;\n\t\topenwrt,ih-type = <IH_TYPE_FILESYSTEM>;\n\t};\n\n\tart: partition@7f0000 {\n\t\tlabel = \"art\";\n\t\treg = <0x7f0000 0x10000>;\n\t\tread-only;\n\t};\n};\n\n&eth0 {\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&eth1 {\n\tnvmem-cells = <&macaddr_art_6>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&ath9k {\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <1>;\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n\n\tmacaddr_art_6: macaddr@6 {\n\t\treg = <0x6 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar7241_netgear_wnr2200.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar7241.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/mtd/partitions/uimage.h>\n\n/ {\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200n8\";\n\t};\n\n\taliases {\n\t\tled-boot = &led_power_amber;\n\t\tled-failsafe = &led_power_amber;\n\t\tled-running = &led_power_green;\n\t\tled-upgrade = &led_power_amber;\n\t};\n\n\tath9k-keys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <20>;\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tgpios = <&ath9k 5 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&ath9k 6 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\trfkill {\n\t\t\tlabel = \"rfkill\";\n\t\t\tlinux,code = <KEY_RFKILL>;\n\t\t\tgpios = <&ath9k 3 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tpinctrl-names = \"default\";\n\t\tpinctrl-0 = <&jtag_disable_pins &switch_led_disable_pins &clks_disable_pins>;\n\n\t\twan_green {\n\t\t\tlabel = \"green:wan\";\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twan_amber {\n\t\t\tlabel = \"amber:wan\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan1_green {\n\t\t\tlabel = \"green:lan1\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan1_amber {\n\t\t\tlabel = \"amber:lan1\";\n\t\t\tgpios = <&gpio 6 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan2_green {\n\t\t\tlabel = \"green:lan2\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan2_amber {\n\t\t\tlabel = \"amber:lan2\";\n\t\t\tgpios = <&gpio 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan3_green {\n\t\t\tlabel = \"green:lan3\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan3_amber {\n\t\t\tlabel = \"amber:lan3\";\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan4_green {\n\t\t\tlabel = \"green:lan4\";\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan4_amber {\n\t\t\tlabel = \"amber:lan4\";\n\t\t\tgpios = <&gpio 1 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twps_green {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tusb_green {\n\t\t\tlabel = \"green:usb\";\n\t\t\tgpios = <&gpio 8 GPIO_ACTIVE_LOW>;\n\t\t\ttrigger-sources = <&hub_port>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\t};\n\n\tath9k-leds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power_green: power_green {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&ath9k 2 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_power_amber: power_amber {\n\t\t\tlabel = \"amber:power\";\n\t\t\tgpios = <&ath9k 1 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"keep\";\n\t\t};\n\n\t\twlan_blue {\n\t\t\tlabel = \"blue:wlan\";\n\t\t\tgpios = <&ath9k 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions: partitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\t\t};\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n};\n\n&eth1 {\n\tcompatible = \"qca,ar7241-eth\", \"syscon\", \"simple-mfd\";\n};\n\n&pcie {\n\tstatus = \"okay\";\n\n\tath9k: wifi@0,0 {\n\t\tcompatible = \"pci168c,002e\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tqca,no-eeprom;\n\t\t#gpio-cells = <2>;\n\t\tgpio-controller;\n\n\t\tusb_power {\n\t\t\tgpio-hog;\n\t\t\tline-name = \"netgear:power:usb\";\n\t\t\tgpios = <4 GPIO_ACTIVE_HIGH>;\n\t\t\toutput-high;\n\t\t};\n\t};\n};\n\n&usb_phy {\n\tstatus = \"okay\";\n};\n\n&usb {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\tstatus = \"okay\";\n\n\thub_port: port@1 {\n\t\treg = <1>;\n\t\t#trigger-source-cells = <0>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar7241_tplink.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar7241.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\taliases {\n\t\tled-boot = &led_system;\n\t\tled-failsafe = &led_system;\n\t\tled-running = &led_system;\n\t\tled-upgrade = &led_system;\n\t\tlabel-mac-device = &ath9k;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\tqss {\n\t\t\tlabel = \"qss\";\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds: leds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_system: system {\n\t\t\tlabel = \"green:system\";\n\t\t\tgpios = <&gpio 1 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tqss {\n\t\t\tlabel = \"green:qss\";\n\t\t\tgpios = <&gpio 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tuboot: partition@0 {\n\t\t\t\treg = <0x0 0x20000>;\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tcompatible = \"tplink,firmware\";\n\t\t\t\treg = <0x20000 0x3d0000>;\n\t\t\t\tlabel = \"firmware\";\n\t\t\t};\n\n\t\t\tpartition@3f0000 {\n\t\t\t\treg = <0x3f0000 0x10000>;\n\t\t\t\tlabel = \"art\";\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n\n\tath9k: wifi@0,0 {\n\t\treg = <0x0000 0 0 0 0>;\n\t\t#gpio-cells = <2>;\n\t\tgpio-controller;\n\t\tqca,no-eeprom;\n\t\tnvmem-cells = <&macaddr_uboot_1fc00>;\n\t\tnvmem-cell-names = \"mac-address\";\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tnvmem-cells = <&macaddr_uboot_1fc00>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <(-1)>;\n};\n\n&eth1 {\n\tnvmem-cells = <&macaddr_uboot_1fc00>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <1>;\n};\n\n&uboot {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_uboot_1fc00: macaddr@1fc00 {\n\t\treg = <0x1fc00 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar7241_tplink_tl-mr3220-v1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar7241_tplink_tl-mr3x20.dtsi\"\n\n/ {\n\tcompatible = \"tplink,tl-mr3220-v1\", \"qca,ar7241\";\n\tmodel = \"TP-Link TL-MR3220 v1\";\n\n\tath9k-leds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twlan {\n\t\t\tlabel = \"green:wlan\";\n\t\t\tgpios = <&ath9k 1 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar7241_tplink_tl-mr3420-v1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar7241_tplink_tl-mr3x20.dtsi\"\n\n/ {\n\tcompatible = \"tplink,tl-mr3420-v1\", \"qca,ar7241\";\n\tmodel = \"TP-Link TL-MR3420 v1\";\n\n\tath9k-leds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twlan {\n\t\t\tlabel = \"green:wlan\";\n\t\t\tgpios = <&ath9k 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar7241_tplink_tl-mr3x20.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar7241_tplink.dtsi\"\n\n/ {\n\tgpio-export {\n\t\tcompatible = \"gpio-export\";\n\t\t#size-cells = <0>;\n\n\t\tgpio_usb_power {\n\t\t\tgpio-export,name = \"tp-link:power:usb\";\n\t\t\tgpio-export,output = <1>;\n\t\t\tgpios = <&gpio 6 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&leds {\n\tled3g {\n\t\tlabel = \"green:3g\";\n\t\tgpios = <&gpio 8 GPIO_ACTIVE_LOW>;\n\t\ttrigger-sources = <&hub_port>;\n\t\tlinux,default-trigger = \"usbport\";\n\t};\n};\n\n&usb {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\tstatus = \"okay\";\n\n\thub_port: port@1 {\n\t\treg = <1>;\n\t\t#trigger-source-cells = <0>;\n\t};\n};\n\n&usb_phy {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar7241_tplink_tl-wr841-v7.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar7241_tplink.dtsi\"\n\n/ {\n\tcompatible = \"tplink,tl-wr841-v7\", \"qca,ar7241\";\n\tmodel = \"TP-Link TL-WR841N/ND v7\";\n\n\tath9k-leds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twlan {\n\t\t\tlabel = \"green:wlan\";\n\t\t\tgpios = <&ath9k 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar7241_tplink_tl-wr842n-v1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar7241.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"tplink,tl-wr842n-v1\", \"qca,ar7241\";\n\tmodel = \"TP-Link TL-WR842N/ND v1\";\n\n\taliases {\n\t\tled-boot = &led_system;\n\t\tled-failsafe = &led_system;\n\t\tled-running = &led_system;\n\t\tled-upgrade = &led_system;\n\t\tlabel-mac-device = &ath9k;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\trfkill {\n\t\t\tlabel = \"rfkill\";\n\t\t\tlinux,code = <KEY_RFKILL>;\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_system: system {\n\t\t\tlabel = \"green:system\";\n\t\t\tgpios = <&gpio 1 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tqss {\n\t\t\tlabel = \"green:qss\";\n\t\t\tgpios = <&gpio 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled3g {\n\t\t\tlabel = \"green:3g\";\n\t\t\tgpios = <&gpio 8 GPIO_ACTIVE_LOW>;\n\t\t\ttrigger-sources = <&hub_port>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\t};\n\n\tath9k-leds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twlan {\n\t\t\tlabel = \"green:wlan\";\n\t\t\tgpios = <&ath9k 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\t};\n\n\tgpio-export {\n\t\tcompatible = \"gpio-export\";\n\n\t\tgpio_usb_power {\n\t\t\tgpio-export,name = \"tp-link:power:usb\";\n\t\t\tgpio-export,output = <1>;\n\t\t\tgpios = <&gpio 6 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&usb {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\tstatus = \"okay\";\n\n\thub_port: port@1 {\n\t\treg = <1>;\n\t\t#trigger-source-cells = <0>;\n\t};\n};\n\n&usb_phy {\n\tstatus = \"okay\";\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tuboot: partition@0 {\n\t\t\t\treg = <0x0 0x20000>;\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tcompatible = \"tplink,firmware\";\n\t\t\t\treg = <0x20000 0x7d0000>;\n\t\t\t\tlabel = \"firmware\";\n\t\t\t};\n\n\t\t\tpartition@7f0000 {\n\t\t\t\treg = <0x7f0000 0x10000>;\n\t\t\t\tlabel = \"art\";\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n\n\tath9k: wifi@0,0 {\n\t\tcompatible = \"pci168c,002e\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\t#gpio-cells = <2>;\n\t\tgpio-controller;\n\t\tqca,no-eeprom;\n\t\tnvmem-cells = <&macaddr_uboot_1fc00>;\n\t\tnvmem-cell-names = \"mac-address\";\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tnvmem-cells = <&macaddr_uboot_1fc00>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <(-1)>;\n};\n\n&eth1 {\n\tnvmem-cells = <&macaddr_uboot_1fc00>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <1>;\n};\n\n&uboot {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_uboot_1fc00: macaddr@1fc00 {\n\t\treg = <0x1fc00 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar7241_ubnt_airrouter.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar7241.dtsi\"\n#include \"ar724x_ubnt_xm.dtsi\"\n\n/ {\n\tcompatible = \"ubnt,airrouter\", \"ubnt,xm\", \"qca,ar7241\";\n\tmodel = \"Ubiquiti AirRouter (XM)\";\n\n\taliases {\n\t\tled-boot = &led_globe;\n\t\tled-failsafe = &led_globe;\n\t\tled-running = &led_globe;\n\t\tled-upgrade = &led_globe;\n\t\tlabel-mac-device = &wifi;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_globe: globe {\n\t\t\tlabel = \"green:globe\";\n\t\t\tgpios = <&gpio 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tpower {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&usb_phy {\n\tstatus = \"okay\";\n};\n\n&usb {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar7241_ubnt_bullet-m-ar7241.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar7241.dtsi\"\n#include \"ar724x_ubnt_xm.dtsi\"\n#include \"ar724x_ubnt_xm_outdoor.dtsi\"\n\n/ {\n\tcompatible = \"ubnt,bullet-m-ar7241\", \"ubnt,xm\", \"qca,ar7241\";\n\tmodel = \"Ubiquiti Bullet M (XM AR7241)\";\n};\n\n&eth1 {\n\tcompatible = \"syscon\", \"simple-mfd\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar7241_ubnt_nanobridge-m.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar7241.dtsi\"\n#include \"ar724x_ubnt_xm.dtsi\"\n#include \"ar724x_ubnt_xm_outdoor.dtsi\"\n\n/ {\n\tcompatible = \"ubnt,nanobridge-m\", \"ubnt,xm\", \"qca,ar7241\";\n\tmodel = \"Ubiquiti NanoBridge M (XM)\";\n};\n\n&eth1 {\n\tcompatible = \"syscon\", \"simple-mfd\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar7241_ubnt_nanostation-loco-m.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar7241.dtsi\"\n#include \"ar724x_ubnt_xm.dtsi\"\n#include \"ar724x_ubnt_xm_outdoor.dtsi\"\n\n/ {\n\tcompatible = \"ubnt,nanostation-loco-m\", \"ubnt,xm\", \"qca,ar7241\";\n\tmodel = \"Ubiquiti Nanostation Loco M (XM)\";\n};\n\n&eth1 {\n\tcompatible = \"syscon\", \"simple-mfd\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar7241_ubnt_nanostation-m.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar7241.dtsi\"\n#include \"ar724x_ubnt_xm.dtsi\"\n#include \"ar724x_ubnt_xm_outdoor.dtsi\"\n\n/ {\n\tcompatible = \"ubnt,nanostation-m\", \"ubnt,xm\", \"qca,ar7241\";\n\tmodel = \"Ubiquiti Nanostation M (XM)\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar7241_ubnt_picostation-m.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar7241.dtsi\"\n#include \"ar724x_ubnt_xm.dtsi\"\n#include \"ar724x_ubnt_xm_outdoor.dtsi\"\n\n/ {\n\tcompatible = \"ubnt,picostation-m\", \"ubnt,xm\", \"qca,ar7241\";\n\tmodel = \"Ubiquiti Picostation M (XM)\";\n};\n\n&eth1 {\n\tcompatible = \"syscon\", \"simple-mfd\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar7241_ubnt_powerbridge-m.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar7241.dtsi\"\n#include \"ar724x_ubnt_xm.dtsi\"\n#include \"ar724x_ubnt_xm_outdoor.dtsi\"\n\n/ {\n\tcompatible = \"ubnt,powerbridge-m\", \"ubnt,xm\", \"qca,ar7241\";\n\tmodel = \"Ubiquiti PowerBridge M (XM)\";\n};\n\n&eth1 {\n\tcompatible = \"syscon\", \"simple-mfd\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar7241_ubnt_rocket-m.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar7241.dtsi\"\n#include \"ar724x_ubnt_xm.dtsi\"\n#include \"ar724x_ubnt_xm_outdoor.dtsi\"\n\n/ {\n\tcompatible = \"ubnt,rocket-m\", \"ubnt,xm\", \"qca,ar7241\";\n\tmodel = \"Ubiquiti Rocket M (XM)\";\n};\n\n&eth1 {\n\tcompatible = \"syscon\", \"simple-mfd\";\n};\n\n&usb_phy {\n\tstatus = \"okay\";\n};\n\n&usb {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar7241_ubnt_unifi-ap-outdoor-plus.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar7241_ubnt_unifi.dtsi\"\n\n/ {\n\tcompatible = \"ubnt,unifi-ap-outdoor-plus\", \"qca,ar7241\";\n\tmodel = \"Ubiquiti UniFi AP Outdoor+\";\n\n\taliases {\n\t\tled-boot = &led_white;\n\t\tled-failsafe = &led_white;\n\t\tled-running = &led_blue;\n\t\tled-upgrade = &led_blue;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_blue: blue {\n\t\t\tlabel = \"blue\";\n\t\t\tgpios = <&gpio 0 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tled_white: white {\n\t\t\tlabel = \"white\";\n\t\t\tgpios = <&gpio 1 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <50000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tuboot: partition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x40000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0xf60000>;\n\n\t\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\n\t\t\t\tpartition@0 {\n\t\t\t\t\tlabel = \"kernel\";\n\t\t\t\t\treg = <0x0 0x300000>;\n\t\t\t\t\t/* Can be resized w/o issues.\n\t\t\t\t\t * U-Boot can load kernel from the\n\t\t\t\t\t * entirety of the \"firmware\" partition space.\n\t\t\t\t\t */\n\t\t\t\t};\n\n\t\t\t\tpartition@300000 {\n\t\t\t\t\tlabel = \"rootfs\";\n\t\t\t\t\treg = <0x300000 0xc60000>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tpartition@fb0000 {\n\t\t\t\tlabel = \"cfg\";\n\t\t\t\treg = <0xfb0000 0x40000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tart: partition@ff0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0xff0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&eth0 {\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&eth1 {\n\tstatus = \"okay\";\n\n\tnvmem-cells = <&macaddr_art_6>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wifi {\n\tubnt,hsr;\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n\n\tmacaddr_art_6: macaddr@6 {\n\t\treg = <0x6 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar7241_ubnt_unifi.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar7241_ubnt_unifi.dtsi\"\n\n/ {\n\tcompatible = \"ubnt,unifi\", \"qca,ar7241\";\n\tmodel = \"Ubiquiti UniFi AP\";\n\n\taliases {\n\t\tled-boot = &led_dome_green;\n\t\tled-failsafe = &led_dome_green;\n\t\tled-running = &led_dome_green;\n\t\tled-upgrade = &led_dome_green;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_dome_green: dome_green {\n\t\t\tlabel = \"green:dome\";\n\t\t\tgpios = <&gpio 0 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tdome_orange {\n\t\t\tlabel = \"orange:dome\";\n\t\t\tgpios = <&gpio 1 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x040000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x050000 0x750000>;\n\t\t\t};\n\n\t\t\tpartition@7a0000 {\n\t\t\t\tlabel = \"board_config\";\n\t\t\t\treg = <0x7a0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@7b0000 {\n\t\t\t\tlabel = \"cfg\";\n\t\t\t\treg = <0x7b0000 0x040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tart: partition@7f0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0x7f0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&eth0 {\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&eth1 {\n\tcompatible = \"syscon\", \"simple-mfd\";\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar7241_ubnt_unifi.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar7241.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\taliases {\n\t\tlabel-mac-device = &eth0;\n\t};\n\n\textosc: ref {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <40000000>;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n};\n\n&pll {\n\tclocks = <&extosc>;\n};\n\n&pcie {\n\tstatus = \"okay\";\n\n\twifi: wifi@0,0 {\n\t\treg = <0x0000 0 0 0 0>;\n\t\tqca,no-eeprom;\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar7242.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar724x.dtsi\"\n\n/ {\n\tusb_phy: usb-phy {\n\t\tcompatible = \"qca,ar7200-usb-phy\";\n\n\t\treset-names = \"usb-phy\", \"usb-suspend-override\";\n\t\tresets = <&rst 4>, <&rst 3>;\n\n\t\t#phy-cells = <0>;\n\n\t\tstatus = \"disabled\";\n\t};\n};\n\n&gpio {\n\tngpios = <20>;\n};\n\n&ahb {\n\tusb: usb@1b000000 {\n\t\tcompatible = \"generic-ehci\";\n\t\treg = <0x1b000000 0x1000>;\n\n\t\tinterrupts = <3>;\n\n\t\tresets = <&rst 5>;\n\t\treset-names = \"usb-host\";\n\n\t\thas-transaction-translator;\n\t\tcaps-offset = <0x100>;\n\n\t\tphy-names = \"usb-phy\";\n\t\tphys = <&usb_phy>;\n\n\t\tstatus = \"disabled\";\n\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t};\n};\n\n&mdio0 {\n\tresets = <&rst 22>;\n\treset-names = \"mdio\";\n};\n\n&eth0 {\n\tcompatible = \"qca,ar7242-eth\", \"syscon\";\n\n\tpll-data = <0x16000000 0x00000101 0x00001616>;\n\tpll-reg = <0x4 0x2c 17>;\n\tpll-handle = <&pll>;\n\n\tresets = <&rst 9>;\n\treset-names = \"mac\";\n};\n\n&mdio1 {\n\tresets = <&rst 23>;\n\treset-names = \"mdio\";\n\tbuiltin-switch;\n\n\tbuiltin_switch: switch0@1f {\n\t\tcompatible = \"qca,ar7240sw\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x1f>;\n\t\tresets = <&rst 8>;\n\t\treset-names = \"switch\";\n\t\tqca,mib-poll-interval = <500>;\n\t};\n};\n\n&eth1 {\n\tcompatible = \"qca,ar7242-eth\", \"syscon\";\n\n\tresets = <&rst 13>;\n\treset-names = \"mac\";\n\n\tphy-mode = \"gmii\";\n\n\tfixed-link {\n\t\tspeed = <1000>;\n\t\tfull-duplex;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar7242_avm_fritz300e.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar7242.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"avm,fritz300e\", \"qca,ar7242\";\n\tmodel = \"AVM FRITZ!WLAN Repeater 300E\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t\tlabel-mac-device = &ath9k;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\tlan {\n\t\t\tlabel = \"green:lan\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan {\n\t\t\tlabel = \"green:wlan\";\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\t};\n\n\tath9k-leds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\trssi0 {\n\t\t\tlabel = \"green:rssi0\";\n\t\t\tgpios = <&ath9k 10 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\trssi1 {\n\t\t\tlabel = \"green:rssi1\";\n\t\t\tgpios = <&ath9k 4 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\trssi2 {\n\t\t\tlabel = \"green:rssi2\";\n\t\t\tgpios = <&ath9k 6 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\trssi3 {\n\t\t\tlabel = \"green:rssi3\";\n\t\t\tgpios = <&ath9k 7 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\trssi4 {\n\t\t\tlabel = \"green:rssi4\";\n\t\t\tgpios = <&ath9k 5 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\teth-phy-reset {\n\t\tcompatible = \"regulator-fixed\";\n\n\t\tregulator-name = \"eth-phy-reset\";\n\t\tregulator-min-microvolt = <3300000>;\n\t\tregulator-max-microvolt = <3300000>;\n\n\t\tgpio = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\tstartup-delay-us = <300000>;\n\t\tenable-active-high;\n\n\t\tregulator-always-on;\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\treg = <0x0 0x20000>;\n\t\t\t\tlabel = \"urloader\";\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tcompatible = \"avm,eva-firmware\";\n\t\t\t\treg = <0x20000 0xee0000>;\n\t\t\t\tlabel = \"firmware\";\n\t\t\t};\n\n\t\t\tpartition@f00000 {\n\t\t\t\treg = <0xf00000 0x80000>;\n\t\t\t\tlabel = \"tffs (1)\";\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@f80000 {\n\t\t\t\treg = <0xf80000 0x80000>;\n\t\t\t\tlabel = \"tffs (2)\";\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n\n\tath9k: wifi@0,0 {\n\t\treg = <0x0000 0 0 0 0>;\n\t\t#gpio-cells = <2>;\n\t\tgpio-controller;\n\t\tqca,no-eeprom;\n\t};\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t\tphy-mode = \"rgmii\";\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tphy-mode = \"rgmii\";\n\tphy-handle = <&phy0>;\n\n\tpll-data = <0x16000000 0x00000101 0x00001313>;\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar7242_buffalo_bhr-4grv.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar7242_buffalo_wzr-bhr.dtsi\"\n\n/ {\n\tcompatible = \"buffalo,bhr-4grv\", \"qca,ar7242\";\n\tmodel = \"Buffalo BHR-4GRV\";\n};\n\n&leds {\n\tsec_vpn {\n\t\tlabel = \"orange:vpn\";\n\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t};\n};\n\n&eth0 {\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar7242_buffalo_wzr-bhr.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar7242.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\taliases {\n\t\tled-boot = &led_diag;\n\t\tled-failsafe = &led_diag;\n\t\tled-upgrade = &led_diag;\n\t};\n\n\textosc: ref {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <40000000>;\n\t};\n\n\tkeys: keys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\tusb {\n\t\t\tlabel = \"usb\";\n\t\t\tlinux,code = <BTN_2>;\n\t\t\tgpios = <&gpio 1 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 6 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds: leds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_diag: diag {\n\t\t\tlabel = \"red:diag\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tusb {\n\t\t\tlabel = \"green:usb\";\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t\ttrigger-sources = <&hub_port>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\t};\n\n\tgpio-export {\n\t\tcompatible = \"gpio-export\";\n\t\t#size-cells = <0>;\n\n\t\tgpio_usb_power {\n\t\t\tgpio-export,name = \"buffalo:usb-power\";\n\t\t\tgpio-export,output = <1>;\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n\n\tvirtual_flash {\n\t\tcompatible = \"mtd-concat\";\n\t\tdevices = <&flash0 &flash1>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\treg = <0x0 0x40000>;\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t};\n\n\t\t\tart: partition@50000 {\n\t\t\t\treg = <0x50000 0x10000>;\n\t\t\t\tlabel = \"art\";\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@60000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\treg = <0x60000 0x1f80000>;\n\t\t\t\tlabel = \"firmware\";\n\t\t\t};\n\n\t\t\tpartition@1fe0000 {\n\t\t\t\treg = <0x1fe0000 0x20000>;\n\t\t\t\tlabel = \"user_property\";\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash0: flash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\t};\n\n\tflash1: flash@1 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <1>;\n\t\tspi-max-frequency = <25000000>;\n\t};\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy-mask = <0x1>;\n\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t\tphy-mode = \"rgmii\";\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tphy-mode = \"rgmii\";\n\tphy-handle = <&phy0>;\n};\n\n&pll {\n\tclocks = <&extosc>;\n};\n\n&usb_phy {\n\tstatus = \"okay\";\n};\n\n&usb {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\tstatus = \"okay\";\n\n\thub_port: port@1 {\n\t\treg = <1>;\n\t\t#trigger-source-cells = <0>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar7242_buffalo_wzr-hp-g302h-a1a0.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar7242.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"buffalo,wzr-hp-g302h-a1a0\", \"qca,ar7242\";\n\tmodel = \"Buffalo WZR-HP-G302H A1A0\";\n\n\taliases {\n\t\tled-boot = &led_diag;\n\t\tled-failsafe = &led_diag;\n\t\tled-upgrade = &led_diag;\n\t};\n\n\textosc: ref {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <40000000>;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 1 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\tusb {\n\t\t\tlabel = \"usb\";\n\t\t\tlinux,code = <BTN_2>;\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\trouter_on {\n\t\t\tlabel = \"router_on\";\n\t\t\tlinux,code = <BTN_5>;\n\t\t\tlinux,input-type = <EV_SW>;\n\t\t\tgpios = <&gpio 8 GPIO_ACTIVE_HIGH>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\tmovie_engine {\n\t\t\tlabel = \"movie_engine\";\n\t\t\tlinux,code = <BTN_3>;\n\t\t\tlinux,input-type = <EV_SW>;\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_HIGH>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_diag: diag {\n\t\t\tlabel = \"red:diag\";\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tath9k-leds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tusb {\n\t\t\tlabel = \"blue:usb\";\n\t\t\tgpios = <&ath9k 4 GPIO_ACTIVE_LOW>;\n\t\t\ttrigger-sources = <&hub_port>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\n\t\twireless {\n\t\t\tlabel = \"green:wireless\";\n\t\t\tgpios = <&ath9k 5 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\tsecurity {\n\t\t\tlabel = \"orange:security\";\n\t\t\tgpios = <&ath9k 6 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\trouter {\n\t\t\tlabel = \"green:router\";\n\t\t\tgpios = <&ath9k 7 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tmovie_engine_on {\n\t\t\tlabel = \"blue:movie_engine_on\";\n\t\t\tgpios = <&ath9k 8 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tmovie_engine_off {\n\t\t\tlabel = \"blue:movie_engine_off\";\n\t\t\tgpios = <&ath9k 9 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tgpio-export {\n\t\tcompatible = \"gpio-export\";\n\t\t#size-cells = <0>;\n\n\t\tgpio_usb_power {\n\t\t\tgpio-export,name = \"buffalo:usb-power\";\n\t\t\tgpio-export,output = <1>;\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n\n\tvirtual_flash {\n\t\tcompatible = \"mtd-concat\";\n\t\tdevices = <&flash0 &flash1>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\treg = <0x0 0x40000>;\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t};\n\n\t\t\tart: partition@50000 {\n\t\t\t\treg = <0x50000 0x10000>;\n\t\t\t\tlabel = \"art\";\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@60000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\treg = <0x60000 0x1f60000>;\n\t\t\t\tlabel = \"firmware\";\n\t\t\t};\n\n\t\t\tpartition@1fc0000 {\n\t\t\t\treg = <0x1fc0000 0x40000>;\n\t\t\t\tlabel = \"user_property\";\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash0: flash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\t};\n\n\tflash1: flash@1 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <1>;\n\t\tspi-max-frequency = <25000000>;\n\t};\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy-mask = <0x1>;\n\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t\tphy-mode = \"rgmii\";\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tpll-data = <0x1c000000 0x00000101 0x00001616>;\n\n\tnvmem-cells = <&macaddr_art_120c>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tphy-mode = \"rgmii\";\n\tphy-handle = <&phy0>;\n};\n\n&pcie {\n\tstatus = \"okay\";\n\n\tath9k: wifi@0,0 {\n\t\tcompatible = \"pci168c,002a\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tnvmem-cells = <&macaddr_art_120c>;\n\t\tnvmem-cell-names = \"mac-address\";\n\t\tqca,no-eeprom;\n\t\t#gpio-cells = <2>;\n\t\tgpio-controller;\n\t};\n};\n\n&pll {\n\tclocks = <&extosc>;\n};\n\n&usb_phy {\n\tstatus = \"okay\";\n};\n\n&usb {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\tstatus = \"okay\";\n\n\thub_port: port@1 {\n\t\treg = <1>;\n\t\t#trigger-source-cells = <0>;\n\t};\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_120c: macaddr@120c {\n\t\treg = <0x120c 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar7242_buffalo_wzr-hp-g450h.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar7242_buffalo_wzr-bhr.dtsi\"\n\n/ {\n\tcompatible = \"buffalo,wzr-hp-g450h\", \"qca,ar7242\";\n\tmodel = \"Buffalo WZR-HP-G450H/WZR-450HP\";\n\n\taliases {\n\t\tlabel-mac-device = &eth0;\n\t};\n\n\tath9k-leds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_movie_engine {\n\t\t\tlabel = \"blue:movie_engine\";\n\t\t\tgpios = <&ath9k 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\trouter {\n\t\t\tlabel = \"green:router\";\n\t\t\tgpios = <&ath9k 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twireless {\n\t\t\tlabel = \"green:wireless\";\n\t\t\tgpios = <&ath9k 15 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\t};\n};\n\n&keys {\n\tmovie_engine {\n\t\tlabel = \"movie_engine\";\n\t\tlinux,code = <BTN_6>;\n\t\tlinux,input-type = <EV_SW>;\n\t\tgpios = <&gpio 7 GPIO_ACTIVE_HIGH>;\n\t\tdebounce-interval = <60>;\n\t};\n\n\taoss {\n\t\tlabel = \"aoss\";\n\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\tgpios = <&gpio 8 GPIO_ACTIVE_LOW>;\n\t\tdebounce-interval = <60>;\n\t};\n\n\trouter_off {\n\t\tlabel = \"router_off\";\n\t\tlinux,code = <BTN_5>;\n\t\tlinux,input-type = <EV_SW>;\n\t\tgpios = <&gpio 12 GPIO_ACTIVE_HIGH>;\n\t\tdebounce-interval = <60>;\n\t};\n};\n\n&leds {\n\tsec_vpn {\n\t\tlabel = \"orange:security\";\n\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t};\n};\n\n&eth0 {\n\tnvmem-cells = <&macaddr_art_1002>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&pcie {\n\tstatus = \"okay\";\n\n\tath9k: wifi@0,0 {\n\t\tcompatible = \"pci168c,0030\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tnvmem-cells = <&macaddr_art_1002>;\n\t\tnvmem-cell-names = \"mac-address\";\n\t\tqca,no-eeprom;\n\t\t#gpio-cells = <2>;\n\t\tgpio-controller;\n\t};\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_1002: macaddr@1002 {\n\t\treg = <0x1002 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar7242_engenius_eap350-v1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar7242.dtsi\"\n#include \"ar724x_senao_loader-4k.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"engenius,eap350-v1\", \"qca,ar7242\";\n\tmodel = \"EnGenius EAP350 v1\";\n\n\taliases {\n\t\tlabel-mac-device = &eth0;\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 0 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"blue:power\";\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\tath9k-leds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twlan {\n\t\t\tlabel = \"blue:wlan\";\n\t\t\tgpios = <&ath9k 1 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\t};\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy4: ethernet-phy@4 {\n\t\treg = <4>;\n\t\teee-broken-100tx;\n\t\teee-broken-1000t;\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tphy-handle = <&phy4>;\n\tphy-mode = \"rgmii-id\";\n\n\tpll-data = <0x02000000 0x00000101 0x00001313>;\n};\n\n&pcie {\n\tstatus = \"okay\";\n\n\tath9k: wifi@0,0,0 {\n\t\tcompatible = \"pci168c,002a\";\n\t\treg = <0x0 0 0 0 0>;\n\t\tnvmem-cells = <&macaddr_art_0>;\n\t\tnvmem-cell-names = \"mac-address\";\n\t\tmac-address-increment = <1>;\n\t\tqca,no-eeprom;\n\t\t#gpio-cells = <2>;\n\t\tgpio-controller;\n\t};\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar7242_engenius_ecb350-v1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar7242.dtsi\"\n#include \"ar724x_senao_loader-4k.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"engenius,ecb350-v1\", \"qca,ar7242\";\n\tmodel = \"EnGenius ECB350 v1\";\n\n\taliases {\n\t\tlabel-mac-device = &ath9k;\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 0 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\tath9k-leds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twlan {\n\t\t\tlabel = \"green:wlan\";\n\t\t\tgpios = <&ath9k 1 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\t};\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy4: ethernet-phy@4 {\n\t\treg = <4>;\n\t\teee-broken-100tx;\n\t\teee-broken-1000t;\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tphy-handle = <&phy4>;\n\tphy-mode = \"rgmii-id\";\n\n\tpll-data = <0x02000000 0x00000101 0x00001313>;\n};\n\n&pcie {\n\tstatus = \"okay\";\n\n\tath9k: wifi@0,0,0 {\n\t\tcompatible = \"pci168c,002a\";\n\t\treg = <0x0 0 0 0 0>;\n\t\tnvmem-cells = <&macaddr_art_0>;\n\t\tnvmem-cell-names = \"mac-address\";\n\t\tmac-address-increment = <(-1)>;\n\t\tqca,no-eeprom;\n\t\t#gpio-cells = <2>;\n\t\tgpio-controller;\n\t};\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar7242_meraki_mr12.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar7242.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"meraki,mr12\", \"qca,ar7242\";\n\tmodel = \"Meraki MR12\";\n\n\taliases {\n\t\tled-boot = &led_power_orange;\n\t\tled-failsafe = &led_power_orange;\n\t\tled-running = &led_power_green;\n\t\tled-upgrade = &led_power_orange;\n\t};\n\n\textosc: ref {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-output-names = \"ref\";\n\t\tclock-frequency = <40000000>;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tlink1 {\n\t\t\tlabel = \"green:link1\";\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlink2 {\n\t\t\tlabel = \"green:link2\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlink3 {\n\t\t\tlabel = \"green:link3\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlink4 {\n\t\t\tlabel = \"green:link4\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan {\n\t\t\tlabel = \"green:lan\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_power_orange: power_orange {\n\t\t\tlabel = \"orange:power\";\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t\tpanic-indicator;\n\t\t};\n\n\t\tled_power_green: power_green {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 8 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n\n\twifi@0,0,0 {\n\t\tcompatible = \"pci168c,002a\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tqca,no-eeprom;\n\t\tnvmem-cells = <&macaddr_config_66>;\n\t\tnvmem-cell-names = \"mac-address\";\n\t\tmac-address-increment = <1>;\n\t};\n};\n\n&pll {\n\tclocks = <&extosc>;\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy4: ethernet-phy@4 {\n\t\treg = <4>;\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tnvmem-cells = <&macaddr_config_66>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tpll-data = <0x02000000 0x00000101 0x00001313>;\n\n\tphy-mode = \"rgmii-id\";\n\tphy-handle = <&phy4>;\n};\n\n&mdio1 {\n\tstatus = \"okay\";\n};\n\n&eth1 {\n\tstatus = \"okay\";\n\n\tnvmem-cells = <&macaddr_config_66>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <50000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x40000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x40000 0x40000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tconfig: partition@80000 {\n\t\t\t\tlabel = \"config\";\n\t\t\t\treg = <0x80000 0x20000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@a0000 {\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0xa0000 0xf40000>;\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t};\n\n\t\t\tpartition@fe0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0xfe0000 0x20000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&config {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_config_66: macaddr@66 {\n\t\treg = <0x66 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar7242_tplink_tl-wr2543-v1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar7242.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"tplink,tl-wr2543-v1\", \"qca,ar7242\";\n\tmodel = \"TP-Link TL-WR2543N/ND\";\n\n\taliases {\n\t\tled-boot = &led_wps;\n\t\tled-failsafe = &led_wps;\n\t\tled-running = &led_wps;\n\t\tled-upgrade = &led_wps;\n\t\tlabel-mac-device = &eth0;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200n8\";\n\t};\n\n\textosc: ref {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <40000000>;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_wps: wps {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&gpio 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tusb {\n\t\t\tlabel = \"green:usb\";\n\t\t\tgpios = <&gpio 8 GPIO_ACTIVE_LOW>;\n\t\t\ttrigger-sources = <&hub_port>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\t};\n\n\tath9k-leds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twlan2g {\n\t\t\tlabel = \"green:wlan2g\";\n\t\t\tgpios = <&ath9k 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\twlan5g {\n\t\t\tlabel = \"green:wlan5g\";\n\t\t\tgpios = <&ath9k 1 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\t};\n\n\trtl8367 {\n\t\tcompatible = \"realtek,rtl8367\";\n\t\tgpio-sda = <&gpio 1 GPIO_ACTIVE_HIGH>;\n\t\tgpio-sck = <&gpio 6 GPIO_ACTIVE_HIGH>;\n\t\trealtek,extif0 = <1 0 1 1 1 1 1 1 2>;\n\n\t\tmdio-bus {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tstatus = \"okay\";\n\n\t\t\tphy0: ethernet-phy@0 {\n\t\t\t\treg = <0>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pll {\n\tclocks = <&extosc>;\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\t\tm25p,fast-read;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tuboot: partition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x020000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tcompatible = \"tplink,firmware\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x020000 0x7d0000>;\n\t\t\t};\n\n\t\t\tpartition@7f0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0x7f0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&usb {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\tstatus = \"okay\";\n\n\thub_port: port@1 {\n\t\treg = <1>;\n\t\t#trigger-source-cells = <0>;\n\t};\n};\n\n&usb_phy {\n\tstatus = \"okay\";\n};\n\n&pcie {\n\tstatus = \"okay\";\n\n\tath9k: wifi@0,0 {\n\t\treg = <0x0000 0 0 0 0>;\n\t\t#gpio-cells = <2>;\n\t\tgpio-controller;\n\t\tqca,no-eeprom;\n\t\tnvmem-cells = <&macaddr_uboot_1fc00>;\n\t\tnvmem-cell-names = \"mac-address\";\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tphy-mode = \"rgmii\";\n\tnvmem-cells = <&macaddr_uboot_1fc00>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tphy-handle = <&phy0>;\n\tfixed-link {\n\t\tspeed = <1000>;\n\t\tfull-duplex;\n\t};\n};\n\n&uboot {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_uboot_1fc00: macaddr@1fc00 {\n\t\treg = <0x1fc00 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar7242_ubnt_edgeswitch-5xp.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar7242_ubnt_sw.dtsi\"\n\n/ {\n\tcompatible = \"ubnt,edgeswitch-5xp\", \"qca,ar7242\";\n\tmodel = \"Ubiquiti EdgeSwitch 5XP\";\n\n\tgpio-export {\n\t\tcompatible = \"gpio-export\";\n\n\t\tpoe_24v_port1 {\n\t\t\tgpio-export,name = \"ubnt:24v-poe:port1\";\n\t\t\tgpio-export,output = <0>;\n\t\t\tgpios = <&gpio_hc595 1 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tpoe_24v_port2 {\n\t\t\tgpio-export,name = \"ubnt:24v-poe:port2\";\n\t\t\tgpio-export,output = <0>;\n\t\t\tgpios = <&gpio_hc595 3 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tpoe_24v_port3 {\n\t\t\tgpio-export,name = \"ubnt:24v-poe:port3\";\n\t\t\tgpio-export,output = <0>;\n\t\t\tgpios = <&gpio_hc595 5 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tpoe_24v_port4 {\n\t\t\tgpio-export,name = \"ubnt:24v-poe:port4\";\n\t\t\tgpio-export,output = <0>;\n\t\t\tgpios = <&gpio_hc595 7 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tpoe_24v_port5 {\n\t\t\tgpio-export,name = \"ubnt:24v-poe:port5\";\n\t\t\tgpio-export,output = <0>;\n\t\t\tgpios = <&gpio_hc595 9 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy0: ethernet-switch@0 {\n\t\tcompatible = \"qca,ar8327\";\n\t\treg = <0x0>;\n\n\t\tqca,ar8327-initvals = <\n\t\t\t0x04 0x05100000 /* PORT0 PAD MODE CTRL */\n\t\t\t0x0c 0x05100000 /* PORT6 PAD MODE CTRL */\n\t\t\t0x50 0x40004000 /* LED_CTRL0 */\n\t\t\t0x54 0x40004000 /* LED_CTRL1 */\n\t\t\t0x58 0x40004000 /* LED_CTRL2 */\n\t\t\t0x5c 0x03ffff00 /* LED_CTRL3 */\n\t\t\t0x7c 0x0000007e /* PORT0_STATUS */\n\t\t\t0x94 0x0000007e /* PORT6_STATUS */\n\t\t>;\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii\";\n\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tfixed-link {\n\t\tspeed = <1000>;\n\t\tfull-duplex;\n\t};\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar7242_ubnt_edgeswitch-8xp.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar7242_ubnt_sw.dtsi\"\n\n/ {\n\tcompatible = \"ubnt,edgeswitch-8xp\", \"qca,ar7242\";\n\tmodel = \"Ubiquiti EdgeSwitch 8XP\";\n\n\tgpio-export {\n\t\tcompatible = \"gpio-export\";\n\n\t\tpoe_24v_port1 {\n\t\t\tgpio-export,name = \"ubnt:24v-poe:port1\";\n\t\t\tgpio-export,output = <0>;\n\t\t\tgpios = <&gpio_hc595 1 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tpoe_48v_port1 {\n\t\t\tgpio-export,name = \"ubnt:48v-poe:port1\";\n\t\t\tgpio-export,output = <0>;\n\t\t\tgpios = <&gpio_hc595 0 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tpoe_24v_port2 {\n\t\t\tgpio-export,name = \"ubnt:24v-poe:port2\";\n\t\t\tgpio-export,output = <0>;\n\t\t\tgpios = <&gpio_hc595 3 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tpoe_48v_port2 {\n\t\t\tgpio-export,name = \"ubnt:48v-poe:port2\";\n\t\t\tgpio-export,output = <0>;\n\t\t\tgpios = <&gpio_hc595 2 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tpoe_24v_port3 {\n\t\t\tgpio-export,name = \"ubnt:24v-poe:port3\";\n\t\t\tgpio-export,output = <0>;\n\t\t\tgpios = <&gpio_hc595 5 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tpoe_48v_port3 {\n\t\t\tgpio-export,name = \"ubnt:48v-poe:port3\";\n\t\t\tgpio-export,output = <0>;\n\t\t\tgpios = <&gpio_hc595 4 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tpoe_24v_port4 {\n\t\t\tgpio-export,name = \"ubnt:24v-poe:port4\";\n\t\t\tgpio-export,output = <0>;\n\t\t\tgpios = <&gpio_hc595 7 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tpoe_48v_port4 {\n\t\t\tgpio-export,name = \"ubnt:48v-poe:port4\";\n\t\t\tgpio-export,output = <0>;\n\t\t\tgpios = <&gpio_hc595 6 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tpoe_24v_port5 {\n\t\t\tgpio-export,name = \"ubnt:24v-poe:port5\";\n\t\t\tgpio-export,output = <0>;\n\t\t\tgpios = <&gpio_hc595 9 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tpoe_48v_port5 {\n\t\t\tgpio-export,name = \"ubnt:48v-poe:port5\";\n\t\t\tgpio-export,output = <0>;\n\t\t\tgpios = <&gpio_hc595 8 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tpoe_24v_port6 {\n\t\t\tgpio-export,name = \"ubnt:24v-poe:port6\";\n\t\t\tgpio-export,output = <0>;\n\t\t\tgpios = <&gpio_hc595 11 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tpoe_48v_port6 {\n\t\t\tgpio-export,name = \"ubnt:48v-poe:port6\";\n\t\t\tgpio-export,output = <0>;\n\t\t\tgpios = <&gpio_hc595 10 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tpoe_24v_port7 {\n\t\t\tgpio-export,name = \"ubnt:24v-poe:port7\";\n\t\t\tgpio-export,output = <0>;\n\t\t\tgpios = <&gpio_hc595 13 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tpoe_48v_port7 {\n\t\t\tgpio-export,name = \"ubnt:48v-poe:port7\";\n\t\t\tgpio-export,output = <0>;\n\t\t\tgpios = <&gpio_hc595 12 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tpoe_24v_port8 {\n\t\t\tgpio-export,name = \"ubnt:24v-poe:port8\";\n\t\t\tgpio-export,output = <0>;\n\t\t\tgpios = <&gpio_hc595 15 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tpoe_48v_port8 {\n\t\t\tgpio-export,name = \"ubnt:48v-poe:port8\";\n\t\t\tgpio-export,output = <0>;\n\t\t\tgpios = <&gpio_hc595 14 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy-mask = <0x10>;\n\n\tethernet-switch@1e {\n\t\tcompatible = \"brcm,bcm53128\";\n\t\treg = <0x1e>;\n\n\t\tports {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\n\t\t\tport0@0 {\n\t\t\t\treg = <0>;\n\t\t\t\tlabel = \"lan1\";\n\t\t\t};\n\n\t\t\tport1@1 {\n\t\t\t\treg = <1>;\n\t\t\t\tlabel = \"lan2\";\n\t\t\t};\n\n\t\t\tport2@2 {\n\t\t\t\treg = <2>;\n\t\t\t\tlabel = \"lan3\";\n\t\t\t};\n\n\t\t\tport3@3 {\n\t\t\t\treg = <3>;\n\t\t\t\tlabel = \"lan4\";\n\t\t\t};\n\n\t\t\tport4@4 {\n\t\t\t\treg = <4>;\n\t\t\t\tlabel = \"lan5\";\n\t\t\t};\n\n\t\t\tport5@5 {\n\t\t\t\treg = <5>;\n\t\t\t\tlabel = \"lan6\";\n\t\t\t};\n\n\t\t\tport6@6 {\n\t\t\t\treg = <6>;\n\t\t\t\tlabel = \"lan7\";\n\t\t\t};\n\n\t\t\tport7@7 {\n\t\t\t\treg = <7>;\n\t\t\t\tlabel = \"lan8\";\n\t\t\t};\n\n\t\t\tphy0: port8@8 {\n\t\t\t\treg = <8>;\n\t\t\t\tlabel = \"cpu\";\n\t\t\t\tethernet = <&eth0>;\n\n\t\t\t\tfixed-link {\n\t\t\t\t\tspeed = <1000>;\n\t\t\t\t\tfull-duplex;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-rxid\";\n\tpll-data = <0x16000000 0x00000101 0x00001313>;\n\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tfixed-link {\n\t\tspeed = <1000>;\n\t\tfull-duplex;\n\t};\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar7242_ubnt_sw.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar7242.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"qca,ar7242\";\n\tmodel = \"Ubiquiti Networks SW board\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200n8\";\n\t};\n\n\taliases {\n\t\tled-boot = &led_usr;\n\t\tled-failsafe = &led_usr;\n\t\tled-running = &led_usr;\n\t\tled-upgrade = &led_usr;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_usr: usr {\n\t\t\tlabel = \"yellow:usr\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tgpio_spi {\n\t\tcompatible = \"spi-gpio\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tsck-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\t\tmosi-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;\n\t\tcs-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;\n\t\tnum-chipselects = <1>;\n\n\t\tgpio_hc595: gpio_spi@0 {\n\t\t\tcompatible = \"fairchild,74hc595\";\n\t\t\treg = <0>;\n\t\t\tregisters-number = <2>;\n\t\t\tspi-max-frequency = <100000>;\n\t\t\tenable-gpios = <&gpio 7 GPIO_ACTIVE_HIGH>;\n\n\t\t\tgpio-controller;\n\t\t\t#gpio-cells = <2>;\n\n\t\t};\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\treg = <0x000000 0x040000>;\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\treg = <0x040000 0x010000>;\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\treg = <0x050000 0x760000>;\n\t\t\t\tlabel = \"firmware\";\n\t\t\t};\n\n\t\t\tpartition@7b0000 {\n\t\t\t\treg = <0x7b0000 0x040000>;\n\t\t\t\tlabel = \"cfg\";\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tart: partition@7f0000 {\n\t\t\t\treg = <0x7f0000 0x010000>;\n\t\t\t\tlabel = \"art\";\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&usb_phy {\n\tstatus = \"okay\";\n};\n\n&usb {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\tstatus = \"okay\";\n\n\thub_port: port@1 {\n\t\treg = <1>;\n\t\t#trigger-source-cells = <0>;\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&eth1 {\n\tstatus = \"okay\";\n\n\tnvmem-cells = <&macaddr_art_6>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_6: macaddr@6 {\n\t\treg = <0x6 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar724x.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ath79.dtsi\"\n\n/ {\n\tcompatible = \"qca,ar7240\";\n\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200\";\n\t};\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu@0 {\n\t\t\tdevice_type = \"cpu\";\n\t\t\tcompatible = \"mips,mips24Kc\";\n\t\t\tclocks = <&pll ATH79_CLK_CPU>;\n\t\t\treg = <0>;\n\t\t};\n\t};\n\n\tahb: ahb {\n\t\tapb {\n\t\t\tddr_ctrl: memory-controller@18000000 {\n\t\t\t\tcompatible = \"qca,ar9132-ddr-controller\",\n\t\t\t\t\t\t\"qca,ar7240-ddr-controller\";\n\t\t\t\treg = <0x18000000 0x100>;\n\n\t\t\t\t#qca,ddr-wb-channel-cells = <1>;\n\t\t\t};\n\n\t\t\tuart: uart@18020000 {\n\t\t\t\tcompatible = \"ns16550a\";\n\t\t\t\treg = <0x18020000 0x20>;\n\t\t\t\tinterrupts = <3>;\n\n\t\t\t\tclocks = <&pll ATH79_CLK_AHB>;\n\t\t\t\tclock-names = \"uart\";\n\n\t\t\t\treg-io-width = <4>;\n\t\t\t\treg-shift = <2>;\n\t\t\t\tno-loopback-test;\n\t\t\t};\n\n\t\t\tgpio: gpio@18040000 {\n\t\t\t\tcompatible = \"qca,ar7240-gpio\",\n\t\t\t\t\t\t\"qca,ar7100-gpio\";\n\t\t\t\treg = <0x18040000 0x28>;\n\t\t\t\tinterrupts = <2>;\n\n\t\t\t\tngpios = <18>;\n\n\t\t\t\tgpio-controller;\n\t\t\t\t#gpio-cells = <2>;\n\n\t\t\t\tinterrupt-controller;\n\t\t\t\t#interrupt-cells = <2>;\n\t\t\t};\n\n\t\t\tpinmux: pinmux@18040028 {\n\t\t\t\tcompatible = \"pinctrl-single\";\n\n\t\t\t\treg = <0x18040028 0x8>;\n\n\t\t\t\tpinctrl-single,bit-per-mux;\n\t\t\t\tpinctrl-single,register-width = <32>;\n\t\t\t\tpinctrl-single,function-mask = <0x1>;\n\t\t\t\t#pinctrl-cells = <2>;\n\n\t\t\t\tjtag_disable_pins: pinmux_jtag_disable_pins {\n\t\t\t\t\tpinctrl-single,bits = <0x0 0x1 0x1>;\n\t\t\t\t};\n\n\t\t\t\tswitch_led_disable_pins: pinmux_switch_led_disable_pins {\n\t\t\t\t\tpinctrl-single,bits = <0x0 0x0 0xf8>;\n\t\t\t\t};\n\n\t\t\t\tclks_disable_pins: pinmux_clks_disable_pins {\n\t\t\t\t\tpinctrl-single,bits = <0x0 0x0 0x81f00>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tpll: pll-controller@18050000 {\n\t\t\t\tcompatible = \"qca,ar7240-pll\", \"syscon\";\n\t\t\t\treg = <0x18050000 0x3c>;\n\n\t\t\t\tclock-names = \"ref\";\n\t\t\t\t/* The board must provides the ref clock */\n\n\t\t\t\t#clock-cells = <1>;\n\t\t\t\tclock-output-names = \"cpu\", \"ddr\", \"ahb\";\n\t\t\t};\n\n\t\t\twdt: wdt@18060008 {\n\t\t\t\tcompatible = \"qca,ar7130-wdt\";\n\t\t\t\treg = <0x18060008 0x8>;\n\n\t\t\t\tinterrupts = <4>;\n\n\t\t\t\tclocks = <&pll ATH79_CLK_AHB>;\n\t\t\t\tclock-names = \"wdt\";\n\t\t\t};\n\n\t\t\trst: reset-controller@1806001c {\n\t\t\t\tcompatible = \"qca,ar7240-reset\",\n\t\t\t\t\t\t\"qca,ar7100-reset\";\n\t\t\t\treg = <0x1806001c 0x4>;\n\n\t\t\t\t#reset-cells = <1>;\n\t\t\t};\n\n\t\t\tpcie: pcie-controller@180c0000 {\n\t\t\t\tcompatible = \"qcom,ar7240-pci\";\n\t\t\t\t#address-cells = <3>;\n\t\t\t\t#size-cells = <2>;\n\t\t\t\tbus-range = <0x0 0x0>;\n\t\t\t\treg = <0x180c0000 0x1000>, /* CRP */\n\t\t\t\t      <0x180f0000 0x100>,  /* CTRL */\n\t\t\t\t      <0x14000000 0x1000>; /* CFG */\n\t\t\t\treg-names = \"crp_base\", \"ctrl_base\", \"cfg_base\";\n\t\t\t\tranges = <0x2000000 0 0x10000000 0x10000000 0 0x04000000\t/* pci memory */\n\t\t\t\t\t  0x1000000 0 0x00000000 0x0000000 0 0x000001>;\t\t/* io space */\n\t\t\t\tinterrupt-parent = <&cpuintc>;\n\t\t\t\tinterrupts = <2>;\n\n\t\t\t\tresets = <&rst 6>, <&rst 7>;\n\t\t\t\treset-names = \"hc\", \"phy\";\n\n\t\t\t\tdevice_type = \"pci\";\n\n\t\t\t\tinterrupt-controller;\n\t\t\t\t#interrupt-cells = <1>;\n\n\t\t\t\tinterrupt-map-mask = <0 0 0 1>;\n\t\t\t\tinterrupt-map = <0 0 0 0 &pcie 0>;\n\t\t\t\tstatus = \"disabled\";\n\t\t\t};\n\t\t};\n\n\t\tspi: spi@1f000000 {\n\t\t\tcompatible = \"qca,ar7240-spi\",\n\t\t\t\t\t\"qca,ar7100-spi\";\n\t\t\treg = <0x1f000000 0x10>;\n\n\t\t\tclocks = <&pll ATH79_CLK_AHB>;\n\t\t\tclock-names = \"ahb\";\n\n\t\t\tstatus = \"disabled\";\n\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\t};\n};\n\n&cpuintc {\n\tqca,ddr-wb-channel-interrupts = <2>, <3>, <4>, <5>;\n\tqca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>,\n\t\t\t\t<&ddr_ctrl 0>, <&ddr_ctrl 1>;\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar724x_senao_loader-4k.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include <dt-bindings/mtd/partitions/uimage.h>\n\n/ {\n\tvirtual_flash {\n\t\tcompatible = \"mtd-concat\";\n\n\t\tdevices = <&fwconcat0 &fwconcat1>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tcompatible = \"openwrt,uimage\", \"denx,uimage\";\n\t\t\t\topenwrt,ih-magic = <0x73714f4b>;\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x0 0x0>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <20000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x40000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tlabel = \"custom\";\n\t\t\t\treg = <0x50000 0x50000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@a0000 {\n\t\t\t\tlabel = \"loader\";\n\t\t\t\treg = <0xa0000 0x1000>;\n\t\t\t};\n\n\t\t\tfwconcat1: partition@a1000 {\n\t\t\t\tlabel = \"fwconcat1\";\n\t\t\t\treg = <0xa1000 0xff000>;\n\t\t\t};\n\n\t\t\tfwconcat0: partition@1a0000 {\n\t\t\t\tlabel = \"fwconcat0\";\n\t\t\t\treg = <0x1a0000 0x4d0000>;\n\t\t\t};\n\n\t\t\tpartition@670000 {\n\t\t\t\tlabel = \"failsafe\";\n\t\t\t\treg = <0x670000 0x180000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tart: partition@7f0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0x7f0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar724x_senao_loader-64k.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include <dt-bindings/mtd/partitions/uimage.h>\n\n/ {\n\tvirtual_flash {\n\t\tcompatible = \"mtd-concat\";\n\n\t\tdevices = <&fwconcat0 &fwconcat1>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tcompatible = \"openwrt,uimage\", \"denx,uimage\";\n\t\t\t\topenwrt,ih-magic = <0x73714f4b>;\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x0 0x0>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <20000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x40000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tlabel = \"custom\";\n\t\t\t\treg = <0x50000 0x50000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@a0000 {\n\t\t\t\tlabel = \"loader\";\n\t\t\t\treg = <0xa0000 0x10000>;\n\t\t\t};\n\n\t\t\tfwconcat1: partition@b0000 {\n\t\t\t\tlabel = \"fwconcat1\";\n\t\t\t\treg = <0xb0000 0xf0000>;\n\t\t\t};\n\n\t\t\tfwconcat0: partition@1a0000 {\n\t\t\t\tlabel = \"fwconcat0\";\n\t\t\t\treg = <0x1a0000 0x4d0000>;\n\t\t\t};\n\n\t\t\tpartition@670000 {\n\t\t\t\tlabel = \"failsafe\";\n\t\t\t\treg = <0x670000 0x180000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tart: partition@7f0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0x7f0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar724x_ubnt_xm.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x040000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x050000 0x750000>;\n\t\t\t};\n\n\t\t\tpartition@7a0000 {\n\t\t\t\tlabel = \"board_config\";\n\t\t\t\treg = <0x7a0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@7b0000 {\n\t\t\t\tlabel = \"cfg\";\n\t\t\t\treg = <0x7b0000 0x040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tart: partition@7f0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0x7f0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n\n\twifi: wifi@0,0 {\n\t\treg = <0x0000 0 0 0 0>;\n\t\tqca,no-eeprom;\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&eth1 {\n\tstatus = \"okay\";\n\n\tnvmem-cells = <&macaddr_art_6>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n\n\tmacaddr_art_6: macaddr@6 {\n\t\treg = <0x6 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar724x_ubnt_xm_outdoor.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n/ {\n\taliases {\n\t\tled-boot = &led_link4;\n\t\tled-failsafe = &led_link4;\n\t\tlabel-mac-device = &wifi;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tlink1 {\n\t\t\tlabel = \"red:link1\";\n\t\t\tgpios = <&gpio 0 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tlink2 {\n\t\t\tlabel = \"orange:link2\";\n\t\t\tgpios = <&gpio 1 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tlink3 {\n\t\t\tlabel = \"green:link3\";\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tled_link4: link4 {\n\t\t\tlabel = \"green:link4\";\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9132.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-only\n\n#include \"ath79.dtsi\"\n\n/ {\n\tcompatible = \"qca,ar9132\";\n\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200\";\n\t};\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu@0 {\n\t\t\tdevice_type = \"cpu\";\n\t\t\tcompatible = \"mips,mips24Kc\";\n\t\t\tclocks = <&pll ATH79_CLK_CPU>;\n\t\t\treg = <0>;\n\t\t};\n\t};\n\n\tcpuintc: interrupt-controller {\n\t\tcompatible = \"qca,ar9132-cpu-intc\", \"qca,ar7100-cpu-intc\";\n\n\t\tinterrupt-controller;\n\t\t#interrupt-cells = <1>;\n\n\t\tqca,ddr-wb-channel-interrupts = <2>, <3>, <4>, <5>;\n\t\tqca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>,\n\t\t\t\t\t<&ddr_ctrl 0>, <&ddr_ctrl 1>;\n\t};\n\n\tahb {\n\t\tcompatible = \"simple-bus\";\n\t\tranges;\n\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tinterrupt-parent = <&cpuintc>;\n\n\t\tapb {\n\t\t\tcompatible = \"simple-bus\";\n\t\t\tranges;\n\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tinterrupt-parent = <&miscintc>;\n\n\t\t\tddr_ctrl: memory-controller@18000000 {\n\t\t\t\tcompatible = \"qca,ar9132-ddr-controller\",\n\t\t\t\t\t\t\"qca,ar7240-ddr-controller\";\n\t\t\t\treg = <0x18000000 0x100>;\n\n\t\t\t\t#qca,ddr-wb-channel-cells = <1>;\n\t\t\t};\n\n\t\t\tuart: uart@18020000 {\n\t\t\t\tcompatible = \"ns8250\";\n\t\t\t\treg = <0x18020000 0x20>;\n\t\t\t\tinterrupts = <3>;\n\n\t\t\t\tclocks = <&pll ATH79_CLK_AHB>;\n\t\t\t\tclock-names = \"uart\";\n\n\t\t\t\treg-io-width = <4>;\n\t\t\t\treg-shift = <2>;\n\t\t\t\tno-loopback-test;\n\t\t\t};\n\n\t\t\tgpio: gpio@18040000 {\n\t\t\t\tcompatible = \"qca,ar9132-gpio\",\n\t\t\t\t\t\t\"qca,ar7100-gpio\";\n\t\t\t\treg = <0x18040000 0x28>;\n\t\t\t\tinterrupts = <2>;\n\n\t\t\t\tngpios = <22>;\n\n\t\t\t\tgpio-controller;\n\t\t\t\t#gpio-cells = <2>;\n\n\t\t\t\tinterrupt-controller;\n\t\t\t\t#interrupt-cells = <2>;\n\t\t\t};\n\n\t\t\tpll: pll-controller@18050000 {\n\t\t\t\tcompatible = \"qca,ar9132-pll\",\n\t\t\t\t\t\t\"qca,ar9130-pll\", \"syscon\";\n\t\t\t\treg = <0x18050000 0x20>;\n\n\t\t\t\tclock-names = \"ref\";\n\t\t\t\t/* The board must provides the ref clock */\n\n\t\t\t\t#clock-cells = <1>;\n\t\t\t\tclock-output-names = \"cpu\", \"ddr\", \"ahb\";\n\t\t\t};\n\n\t\t\twdt: wdt@18060008 {\n\t\t\t\tcompatible = \"qca,ar7130-wdt\";\n\t\t\t\treg = <0x18060008 0x8>;\n\n\t\t\t\tinterrupts = <4>;\n\n\t\t\t\tclocks = <&pll ATH79_CLK_AHB>;\n\t\t\t\tclock-names = \"wdt\";\n\t\t\t};\n\n\t\t\tmiscintc: interrupt-controller@18060010 {\n\t\t\t\tcompatible = \"qca,ar9132-misc-intc\",\n\t\t\t\t\t   \"qca,ar7100-misc-intc\";\n\t\t\t\treg = <0x18060010 0x8>;\n\n\t\t\t\tinterrupt-parent = <&cpuintc>;\n\t\t\t\tinterrupts = <6>;\n\n\t\t\t\tinterrupt-controller;\n\t\t\t\t#interrupt-cells = <1>;\n\t\t\t};\n\n\t\t\trst: reset-controller@1806001c {\n\t\t\t\tcompatible = \"qca,ar9132-reset\",\n\t\t\t\t\t\t\"qca,ar7100-reset\";\n\t\t\t\treg = <0x1806001c 0x4>;\n\n\t\t\t\t#reset-cells = <1>;\n\t\t\t};\n\t\t};\n\n\t\tusb: usb@1b000100 {\n\t\t\tcompatible = \"qca,ar7100-ehci\", \"generic-ehci\";\n\t\t\treg = <0x1b000100 0x100>;\n\n\t\t\tinterrupts = <3>;\n\t\t\tresets = <&rst 5>;\n\n\t\t\thas-transaction-translator;\n\n\t\t\tphy-names = \"usb\";\n\t\t\tphys = <&usb_phy>;\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tspi: spi@1f000000 {\n\t\t\tcompatible = \"qca,ar9132-spi\", \"qca,ar7100-spi\";\n\t\t\treg = <0x1f000000 0x10>;\n\n\t\t\tclocks = <&pll ATH79_CLK_AHB>;\n\t\t\tclock-names = \"ahb\";\n\n\t\t\tstatus = \"disabled\";\n\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\twmac: wmac@180c0000 {\n\t\t\tcompatible = \"qca,ar9130-wmac\";\n\t\t\treg = <0x180c0000 0x230000>;\n\n\t\t\tinterrupts = <2>;\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\t};\n\n\tusb_phy: usb-phy {\n\t\tcompatible = \"qca,ar7200-usb-phy\";\n\n\t\treset-names = \"usb-phy\", \"usb-suspend-override\";\n\t\tresets = <&rst 4>, <&rst 3>;\n\n\t\t#phy-cells = <0>;\n\n\t\tstatus = \"disabled\";\n\t};\n};\n\n&eth0 {\n\tcompatible = \"qca,ar9130-eth\", \"syscon\";\n\treg = <0x19000000 0x200\n\t\t0x18070000 0x4>;\n\tpll-data = <0x1a000000 0x13000a44 0x00441099>;\n\tpll-reg = <0x4 0x14 20>;\n\tpll-handle = <&pll>;\n\tresets = <&rst 9>;\n\treset-names = \"mac\";\n\tqca,mac-idx = <0>;\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9132_buffalo_wzr-hp-g300nh-rb.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9132_buffalo_wzr-hp-g300nh.dtsi\"\n\n/ {\n\tcompatible = \"buffalo,wzr-hp-g300nh-rb\", \"qca,ar9132\";\n\tmodel = \"Buffalo WZR-HP-G300NH (rtl8366rb)\";\n};\n\n&switch {\n\tstatus = \"okay\";\n\n\tcompatible = \"realtek,rtl8366rb\";\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tpll-data = <0x1f000000 0x13000a44 0x00441099>;\n};\n\n&eth1 {\n\tstatus = \"okay\";\n\n\tpll-data = <0x100 0x13000a44 0x00441099>;\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9132_buffalo_wzr-hp-g300nh-s.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9132_buffalo_wzr-hp-g300nh.dtsi\"\n\n/ {\n\tcompatible = \"buffalo,wzr-hp-g300nh-s\", \"qca,ar9132\";\n\tmodel = \"Buffalo WZR-HP-G300NH (rtl8366s)\";\n};\n\n&switch {\n\tstatus = \"okay\";\n\n\tcompatible = \"realtek,rtl8366s\";\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tpll-data = <0x1e000100 0x13000a44 0x00441099>;\n};\n\n&eth1 {\n\tstatus = \"okay\";\n\n\tpll-data = <0x1e000100 0x13000a44 0x00441099>;\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9132_buffalo_wzr-hp-g300nh.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9132.dtsi\"\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\taliases {\n\t\tled-boot = &led_diag;\n\t\tled-failsafe = &led_security;\n\t\tled-upgrade = &led_diag;\n\t};\n\n\tclock40mhz: ref {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <40000000>;\n\t};\n\n\t/* There is a GPIO driven NXP 74HC153 dual 4-way multiplexer on board\n\t * used for buttons that are on top of the the device.\n         */\n\tmux: mux-controller {\n\t\tcompatible = \"gpio-mux\";\n\t\t#mux-control-cells = <0>;\n\n\t\tmux-gpios = <&gpio 9 GPIO_ACTIVE_HIGH>,\t\t/* s0 */\n\t\t\t    <&gpio 11 GPIO_ACTIVE_HIGH>;\t/* s1 */\n\t};\n\n\tgpio2: key-mux1 {\n\t\tcompatible = \"gpio-cascade\";\n\t\tmux-controls = <&mux>;\n\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\n\t\t// GPIOs used by this node, the mux pin\n\t\tupstream-gpios = <&gpio 12 GPIO_ACTIVE_HIGH>; /* 1y */\n\t};\n\n\tgpio3: key-mux2 {\n\t\tcompatible = \"gpio-cascade\";\n\t\tmux-controls = <&mux>;\n\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\n\t\t// GPIOs used by this node, the mux pin\n\t\tupstream-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; /* 2y */\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <20>;\n\n\t\taoss {\n\t\t\tlabel = \"aoss\";\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tgpios = <&gpio2 0 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio2 1 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\trouter_on {\n\t\t\tlabel = \"router_on\";\n\t\t\tlinux,code = <BTN_5>;\n\t\t\tgpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\tmovie_off {\n\t\t\tlabel = \"movie_off\";\n\t\t\tlinux,code = <BTN_3>;\n\t\t\tgpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\tusb {\n\t\t\tlabel = \"usb\";\n\t\t\tlinux,code = <BTN_2>;\n\t\t\tgpios = <&gpio3 1 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\trouter_auto {\n\t\t\tlabel = \"router_auto\";\n\t\t\tlinux,code = <BTN_6>;\n\t\t\tgpios = <&gpio3 2 GPIO_ACTIVE_HIGH>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\tmovie_on {\n\t\t\tlabel = \"movie_on\";\n\t\t\tlinux,code = <BTN_4>;\n\t\t\tgpios = <&gpio3 3 GPIO_ACTIVE_HIGH>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tflash@1e000000 {\n\t\tcompatible = \"cfi-flash\";\n\t\treg = <0x1e000000 0x2000000>;\n\t\tbank-width = <2>;\n\t\tdevice-width = <2>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0000000 0x0040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x0040000 0x0020000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@60000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x0060000 0x1f60000>;\n\t\t\t};\n\n\t\t\tpartition@1fc0000 {\n\t\t\t\tlabel = \"user_property\";\n\t\t\t\treg = <0x1fc0000 0x0020000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tart: partition@1fe0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0x1fe0000 0x020000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tusb {\n\t\t\tlabel = \"blue:usb\";\n\t\t\tgpios = <&gpio 0 GPIO_ACTIVE_LOW>;\n\t\t\ttrigger-sources = <&hub_port>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\n\t\tled_diag: diag {\n\t\t\tlabel = \"red:diag\";\n\t\t\tgpios = <&gpio 1 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twireless {\n\t\t\tlabel = \"green:wireless\";\n\t\t\tgpios = <&gpio 6 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\tled_security: security {\n\t\t\tlabel = \"amber:security\";\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\trouter {\n\t\t\tlabel = \"green:router\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tswitch: switch {\n\t\tstatus = \"disabled\";\n\n\t\tgpio-sda = <&gpio 19 GPIO_ACTIVE_HIGH>;\n\t\tgpio-sck = <&gpio 20 GPIO_ACTIVE_HIGH>;\n\t\tmii-bus = <&mdio0>;\n\n\t\tmdio-bus {\n\t\t\tstatus = \"okay\";\n\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tphy-mask = <0x10>;\n\n\t\t\tphy4: ethernet-phy@4 {\n\t\t\t\treg = <4>;\n\t\t\t\tphy-mode = \"rgmii\";\n\t\t\t};\n\t\t};\n\t};\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n};\n\n&eth0 {\n\tstatus = \"disabled\";\n\n\tphy-mode = \"rgmii\";\n\tnvmem-cells = <&macaddr_art_1120c>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tfixed-link {\n\t\tspeed = <1000>;\n\t\tfull-duplex;\n\t};\n};\n\n&mdio1 {\n\tstatus = \"okay\";\n};\n\n&eth1 {\n\tstatus = \"disabled\";\n\n\tcompatible = \"qca,ar9130-eth\", \"syscon\";\n\treg = <0x1a000000 0x200\n\t\t0x18070004 0x4>;\n\n\tpll-reg = <0x4 0x18 22>;\n\tpll-handle = <&pll>;\n\n\tphy-mode = \"rgmii\";\n\tphy-handle = <&phy4>;\n\tresets = <&rst 13>;\n\treset-names = \"mac\";\n\tqca,mac-idx = <1>;\n\tnvmem-cells = <&macaddr_art_1120c>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x11000>;\n};\n\n&uart {\n\tstatus = \"okay\";\n};\n\n&pll {\n\tclocks = <&clock40mhz>;\n};\n\n&usb {\n\tstatus = \"okay\";\n\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\n\thub_port: port@1 {\n\t\treg = <1>;\n\t\t#trigger-source-cells = <0>;\n\t};\n};\n\n&usb_phy {\n\tstatus = \"okay\";\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_1120c: macaddr@1120c {\n\t\treg = <0x1120c 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9132_tplink_tl-wa901nd-v2.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-only\n\n#include \"ar9132.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"tplink,tl-wa901nd-v2\", \"qca,ar9132\";\n\tmodel = \"TP-Link TL-WA901ND v2\";\n\n\taliases {\n\t\tled-boot = &led_system;\n\t\tled-failsafe = &led_system;\n\t\tled-running = &led_system;\n\t\tled-upgrade = &led_system;\n\t\tlabel-mac-device = &eth0;\n\t};\n\n\textosc: ref {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <40000000>;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 3 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\tqss {\n\t\t\tlabel = \"qss\";\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_system: system {\n\t\t\tlabel = \"green:system\";\n\t\t\tgpios = <&gpio 2 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tqss {\n\t\t\tlabel = \"green:qss\";\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\twlan {\n\t\t\tlabel = \"green:wlan\";\n\t\t\tgpios = <&gpio 9 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\t};\n};\n\n&pll {\n\tclocks = <&extosc>;\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tuboot: partition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x020000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@1 {\n\t\t\t\tcompatible = \"tplink,firmware\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x020000 0x3D0000>;\n\t\t\t};\n\n\t\t\tart: partition@2 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0x3F0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy12: ethernet-phy@c {\n\t\treg = <0xc>;\n\t\tphy-mode = \"mii\";\n\n\t\tresets = <&rst 8>;\n\t\treset-names = \"phy\";\n\n\t\treset-assert-us = <10000>;\n\t\treset-deassert-us = <10000>;\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tnvmem-cells = <&macaddr_uboot_1fc00>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tphy-handle = <&phy12>;\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n\tnvmem-cells = <&macaddr_uboot_1fc00>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&uboot {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_uboot_1fc00: macaddr@1fc00 {\n\t\treg = <0x1fc00 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9132_tplink_tl-wr1043nd-v1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-only\n\n#include \"ar9132.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"tplink,tl-wr1043nd-v1\", \"qca,ar9132\";\n\tmodel = \"TP-Link TL-WR1043ND v1\";\n\n\taliases {\n\t\tled-boot = &led_system;\n\t\tled-failsafe = &led_system;\n\t\tled-running = &led_system;\n\t\tled-upgrade = &led_system;\n\t\tlabel-mac-device = &eth0;\n\t};\n\n\textosc: ref {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <40000000>;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 3 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\tqss {\n\t\t\tlabel = \"qss\";\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tusb {\n\t\t\tlabel = \"green:usb\";\n\t\t\tgpios = <&gpio 1 GPIO_ACTIVE_LOW>;\n\t\t\ttrigger-sources = <&hub_port>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\n\t\tled_system: system {\n\t\t\tlabel = \"green:system\";\n\t\t\tgpios = <&gpio 2 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\n\t\tqss {\n\t\t\tlabel = \"green:qss\";\n\t\t\tgpios = <&gpio 5 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\twlan {\n\t\t\tlabel = \"green:wlan\";\n\t\t\tgpios = <&gpio 9 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\t};\n\n\trtl8366rb {\n\t\tcompatible = \"realtek,rtl8366rb\";\n\t\tgpio-sda = <&gpio 18 GPIO_ACTIVE_HIGH>;\n\t\tgpio-sck = <&gpio 19 GPIO_ACTIVE_HIGH>;\n\n\t\tresets = <&rst 8>;\n\t\treset-names = \"switch\";\n\t};\n};\n\n&pll {\n\tclocks = <&extosc>;\n};\n\n&usb {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\tstatus = \"okay\";\n\n\thub_port: port@1 {\n\t\treg = <1>;\n\t\t#trigger-source-cells = <0>;\n\t};\n};\n\n&usb_phy {\n\tstatus = \"okay\";\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\t\tm25p,fast-read;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tuboot: partition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x020000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tcompatible = \"tplink,firmware\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x020000 0x7D0000>;\n\t\t\t};\n\n\t\t\tart: partition@7F0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0x7F0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tphy-mode = \"rgmii\";\n\tnvmem-cells = <&macaddr_uboot_1fc00>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tfixed-link {\n\t\tspeed = <1000>;\n\t\tfull-duplex;\n\t};\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n\tnvmem-cells = <&macaddr_uboot_1fc00>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&uboot {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_uboot_1fc00: macaddr@1fc00 {\n\t\treg = <0x1fc00 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9132_tplink_tl-wr941-v2.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-only\n\n#include \"ar9132.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"tplink,tl-wr941-v2\", \"qca,ar9132\";\n\tmodel = \"TP-Link TL-WR941N/ND v2/v3\";\n\n\taliases {\n\t\tled-boot = &led_system;\n\t\tled-failsafe = &led_system;\n\t\tled-running = &led_system;\n\t\tled-upgrade = &led_system;\n\t\tlabel-mac-device = &eth0;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 3 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\tqss {\n\t\t\tlabel = \"qss\";\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_system: system {\n\t\t\tlabel = \"green:system\";\n\t\t\tgpios = <&gpio 2 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tqss_r {\n\t\t\tlabel = \"red:qss\";\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tqss_g {\n\t\t\tlabel = \"green:qss\";\n\t\t\tgpios = <&gpio 5 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\twlan {\n\t\t\tlabel = \"green:wlan\";\n\t\t\tgpios = <&gpio 9 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\t};\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tswitch@0 {\n\t\tcompatible = \"marvell,mv88e6060\";\n\t\treg = <0>;\n\n\t\tports {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\n\t\t\tport@0 {\n\t\t\t\treg = <0>;\n\t\t\t\tlabel = \"wan\";\n\t\t\t};\n\n\t\t\tport@1 {\n\t\t\t\treg = <1>;\n\t\t\t\tlabel = \"lan1\";\n\t\t\t};\n\n\t\t\tport@2 {\n\t\t\t\treg = <2>;\n\t\t\t\tlabel = \"lan2\";\n\t\t\t};\n\n\t\t\tport@3 {\n\t\t\t\treg = <3>;\n\t\t\t\tlabel = \"lan3\";\n\t\t\t};\n\n\t\t\tport@4 {\n\t\t\t\treg = <4>;\n\t\t\t\tlabel = \"lan4\";\n\t\t\t};\n\n\t\t\tport@5 {\n\t\t\t\treg = <5>;\n\t\t\t\tlabel = \"cpu\";\n\t\t\t\tethernet = <&eth0>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tuboot: partition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x20000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tcompatible = \"tplink,firmware\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x020000 0x3d0000>;\n\t\t\t};\n\n\t\t\tart: partition@3f0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0x3f0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tphy-mode = \"rmii\";\n\tnvmem-cells = <&macaddr_uboot_1fc00>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tfixed-link {\n\t\tspeed = <100>;\n\t\tfull-duplex;\n\t};\n};\n\n&wmac {\n\tstatus = \"okay\";\n\tmtd-cal-data = <&art 0x1000>;\n\tnvmem-cells = <&macaddr_uboot_1fc00>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&uboot {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_uboot_1fc00: macaddr@1fc00 {\n\t\treg = <0x1fc00 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9330.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ath79.dtsi\"\n\n/ {\n\tcompatible = \"qca,ar9330\";\n\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\taliases {\n\t\tserial0 = &uart;\n\t};\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu@0 {\n\t\t\tdevice_type = \"cpu\";\n\t\t\tcompatible = \"mips,mips24Kc\";\n\t\t\tclocks = <&pll ATH79_CLK_CPU>;\n\t\t\treg = <0>;\n\t\t};\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyATH0,115200\";\n\t};\n\n\tahb {\n\t\tapb {\n\t\t\tddr_ctrl: memory-controller@18000000 {\n\t\t\t\tcompatible = \"qca,ar7240-ddr-controller\";\n\t\t\t\treg = <0x18000000 0x100>;\n\n\t\t\t\t#qca,ddr-wb-channel-cells = <1>;\n\t\t\t};\n\n\t\t\tuart: uart@18020000 {\n\t\t\t\tcompatible = \"qca,ar9330-uart\";\n\t\t\t\treg = <0x18020000 0x14>;\n\n\t\t\t\tinterrupts = <3>;\n\n\t\t\t\tclocks = <&pll ATH79_CLK_REF>;\n\t\t\t\tclock-names = \"uart\";\n\t\t\t};\n\n\t\t\tgpio: gpio@18040000 {\n\t\t\t\tcompatible = \"qca,ar7100-gpio\";\n\t\t\t\treg = <0x18040000 0x28>;\n\t\t\t\tinterrupts = <2>;\n\n\t\t\t\tngpios = <30>;\n\n\t\t\t\tgpio-controller;\n\t\t\t\t#gpio-cells = <2>;\n\n\t\t\t\tinterrupt-controller;\n\t\t\t\t#interrupt-cells = <2>;\n\t\t\t};\n\n\t\t\tpinmux: pinmux@18040028 {\n\t\t\t\tcompatible = \"pinctrl-single\";\n\t\t\t\treg = <0x18040028 0x8>;\n\n\t\t\t\tpinctrl-single,bit-per-mux;\n\t\t\t\tpinctrl-single,register-width = <32>;\n\t\t\t\tpinctrl-single,function-mask = <0x1>;\n\t\t\t\t#pinctrl-cells = <2>;\n\n\t\t\t\tjtag_disable_pins: pinmux_jtag_disable_pins {\n\t\t\t\t\tpinctrl-single,bits = <0x0 0x1 0x1>;\n\t\t\t\t};\n\n\t\t\t\tswitch_led_disable_pins: pinmux_switch_led_disable_pins {\n\t\t\t\t\tpinctrl-single,bits = <0x0 0x0 0xf8>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tpll: pll-controller@18050000 {\n\t\t\t\tcompatible = \"qca,ar9330-pll\";\n\t\t\t\treg = <0x18050000 0x100>;\n\n\t\t\t\t#clock-cells = <1>;\n\t\t\t};\n\n\t\t\twdt: wdt@18060008 {\n\t\t\t\tcompatible = \"qca,ar7130-wdt\";\n\t\t\t\treg = <0x18060008 0x8>;\n\n\t\t\t\tinterrupts = <4>;\n\n\t\t\t\tclocks = <&pll ATH79_CLK_AHB>;\n\t\t\t\tclock-names = \"wdt\";\n\t\t\t};\n\n\t\t\trst: reset-controller@1806001c {\n\t\t\t\tcompatible = \"qca,ar7100-reset\";\n\t\t\t\treg = <0x1806001c 0x4>;\n\n\t\t\t\t#reset-cells = <1>;\n\t\t\t};\n\t\t};\n\n\t\tusb: usb@1b000000 {\n\t\t\tcompatible = \"chipidea,usb2\";\n\t\t\treg = <0x1b000000 0x200>;\n\n\t\t\tinterrupts = <3>;\n\t\t\tresets = <&rst 5>;\n\t\t\treset-names = \"usb-host\";\n\n\t\t\tphy-names = \"usb-phy\";\n\t\t\tphys = <&usb_phy>;\n\n\t\t\tstatus = \"disabled\";\n\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tspi: spi@1f000000 {\n\t\t\tcompatible = \"qca,ar934x-spi\";\n\t\t\treg = <0x1f000000 0x1c>;\n\n\t\t\tclocks = <&pll ATH79_CLK_AHB>;\n\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tgmac: gmac@18070000 {\n\t\t\tcompatible = \"qca,ar9330-gmac\";\n\t\t\treg = <0x18070000 0x4>;\n\t\t};\n\n\t\twmac: wmac@18100000 {\n\t\t\tcompatible = \"qca,ar9330-wmac\";\n\t\t\treg = <0x18100000 0x20000>;\n\n\t\t\tinterrupts = <2>;\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\t};\n\n\tusb_phy: usb-phy {\n\t\tcompatible = \"qca,ar7200-usb-phy\";\n\n\t\treset-names = \"usb-phy\", \"usb-suspend-override\";\n\t\tresets = <&rst 4>, <&rst 3>;\n\n\t\t#phy-cells = <0>;\n\n\t\tstatus = \"disabled\";\n\t};\n};\n\n&cpuintc {\n\tqca,ddr-wb-channel-interrupts = <2>, <3>;\n\tqca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>;\n};\n\n&eth0 {\n\tcompatible = \"qca,ar9330-eth\", \"syscon\";\n\n\tpll-data = <0x00110000 0x00001099 0x00991099>;\n\n\tresets = <&rst 9>;\n\treset-names = \"mac\";\n\tphy-handle = <&swphy4>;\n};\n\n&mdio1 {\n\tstatus = \"okay\";\n\tcompatible = \"qca,ar9330-mdio\";\n\n\tresets = <&rst 23>;\n\treset-names = \"mdio\";\n\tbuiltin-switch;\n\n\tbuiltin_switch: switch0@1f {\n\t\tcompatible = \"qca,ar7240sw\";\n\t\treg = <0x1f>;\n\t\tresets = <&rst 8>;\n\t\treset-names = \"switch\";\n\t\tqca,mib-poll-interval = <500>;\n\n\t\tmdio-bus {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\n\t\t\tswphy4: ethernet-phy@4 {\n\t\t\t\treg = <4>;\n\t\t\t\tphy-mode = \"mii\";\n\t\t\t};\n\t\t};\n\t};\n};\n\n&eth1 {\n\tcompatible = \"qca,ar9330-eth\", \"syscon\";\n\n\tpll-data = <0x00110000 0x00001099 0x00991099>;\n\tphy-mode = \"gmii\";\n\n\tresets = <&rst 13>;\n\treset-names = \"mac\";\n\n\tfixed-link {\n\t\tspeed = <1000>;\n\t\tfull-duplex;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9330_dlink_dir-505.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9330.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"D-Link DIR-505\";\n\tcompatible = \"dlink,dir-505\", \"qca,ar9330\";\n\n\taliases {\n\t\tled-boot = &led_power_green;\n\t\tled-failsafe = &led_status_red;\n\t\tled-running = &led_power_green;\n\t\tled-upgrade = &led_status_red;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\twps {\n\t\t\tlabel = \"WPS button\";\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"Reset button\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tpinctrl-names = \"default\";\n\t\tpinctrl-0 = <&jtag_disable_pins>;\n\n\t\tled_power_green: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 27 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_status_red: status {\n\t\t\tlabel = \"red:status\";\n\t\t\tgpios = <&gpio 26 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&gpio {\n\tled_enable {\n\t\tgpio-hog;\n\t\toutput-low;\n\t\tgpios = <1 GPIO_ACTIVE_LOW>;\n\t\tline-name = \"d-link:power:led\";\n\t};\n};\n\n&usb {\n\tdr_mode = \"host\";\n\tstatus = \"okay\";\n};\n\n&usb_phy {\n\tstatus = \"okay\";\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tgmac-config {\n\t\tdevice = <&gmac>;\n\t\tswitch-phy-addr-swap = <0>;\n\t\tswitch-phy-swap = <0>;\n\t};\n};\n\n&eth1 {\n\tcompatible = \"syscon\", \"simple-mfd\";\n\tstatus = \"okay\";\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\tspi-max-frequency = <50000000>;\n\t\treg = <0>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tart: partition@10000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0x10000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tmac: partition@20000 {\n\t\t\t\tlabel = \"mac\";\n\t\t\t\treg = <0x20000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"nvram\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"language\";\n\t\t\t\treg = <0x40000 0x40000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@80000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x80000 0x780000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&wmac {\n\tstatus = \"okay\";\n\tqca,no-eeprom;\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9330_glinet_gl-ar150.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9330.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"GL.iNet GL-AR150\";\n\tcompatible = \"glinet,gl-ar150\", \"qca,ar9330\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t\tlabel-mac-device = &eth0;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twlan {\n\t\t\tlabel = \"orange:wlan\";\n\t\t\tgpios = <&gpio 0 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\tconfigurable {\n\t\t\tlabel = \"green:configurable\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tled_power: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\tmanual {\n\t\t\tlabel = \"manual\";\n\t\t\tlinux,code = <BTN_7>;\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tauto {\n\t\t\tlabel = \"auto\";\n\t\t\tlinux,code = <BTN_8>;\n\t\t\tgpios = <&gpio 8 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&usb {\n\tdr_mode = \"host\";\n\tstatus = \"okay\";\n};\n\n&usb_phy {\n\tstatus = \"okay\";\n\tgpios = <&gpio 6 GPIO_ACTIVE_HIGH>;\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\tspi-max-frequency = <50000000>;\n\t\treg = <0>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@1 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x040000 0x010000>;\n\t\t\t};\n\n\t\t\tpartition@2 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x050000 0xfa0000>;\n\t\t\t};\n\n\t\t\tart: partition@3 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0xff0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&eth1 {\n\tstatus = \"okay\";\n\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tgmac-config {\n\t\tdevice = <&gmac>;\n\n\t\tswitch-phy-addr-swap = <0>;\n\t\tswitch-phy-swap = <0>;\n\t};\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9330_openmesh_om2p-lc.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9330_openmesh_om2p.dtsi\"\n\n/ {\n\tcompatible = \"openmesh,om2p-lc\", \"qca,ar9330\";\n\tmodel = \"OpenMesh OM2P-LC\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9330_openmesh_om2p-v2.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9330_openmesh_om2p.dtsi\"\n\n/ {\n\tcompatible = \"openmesh,om2p-v2\", \"qca,ar9330\";\n\tmodel = \"OpenMesh OM2P v2\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9330_openmesh_om2p.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9330.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tchosen {\n\t\t/delete-property/ bootargs;\n\t};\n\n\taliases {\n\t\tled-boot = &led_power_blue;\n\t\tled-failsafe = &led_power_blue;\n\t\tled-running = &led_power_blue;\n\t\tled-upgrade = &led_power_blue;\n\t\tlabel-mac-device = &eth1;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tpinctrl-names = \"default\";\n\t\tpinctrl-0 = <&switch_led_disable_pins>;\n\n\t\twifi_yellow {\n\t\t\tlabel = \"yellow:wifi\";\n\t\t\tgpios = <&gpio 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_power_blue: power_blue {\n\t\t\tlabel = \"blue:power\";\n\t\t\tgpios = <&gpio 1 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\tlan_blue {\n\t\t\tlabel = \"blue:lan\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twifi_green {\n\t\t\tlabel = \"green:wifi\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\twifi_red {\n\t\t\tlabel = \"red:wifi\";\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twan_blue {\n\t\t\tlabel = \"blue:wan\";\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\twatchdog {\n\t\tcompatible = \"linux,wdt-gpio\";\n\t\tgpios = <&gpio 26 GPIO_ACTIVE_LOW>;\n\t\thw_algo = \"toggle\";\n\t\t/* hw_margin_ms is actually 300s but driver limits it to 60s */\n\t\thw_margin_ms = <60000>;\n\t\talways-running;\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\t/* partitions are passed via bootloader */\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x040000 0x040000>;\n\t\t\t};\n\n\t\t\tpartition@80000 {\n\t\t\t\tlabel = \"custom\";\n\t\t\t\treg = <0x080000 0x140000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@1c0000 {\n\t\t\t\tlabel = \"inactive\";\n\t\t\t\treg = <0x1c0000 0x700000>;\n\t\t\t};\n\n\t\t\tpartition@8c0000 {\n\t\t\t\tlabel = \"inactive2\";\n\t\t\t\treg = <0x8c0000 0x700000>;\n\t\t\t};\n\n\t\t\tart: partition@fc0000 {\n\t\t\t\tlabel = \"ART\";\n\t\t\t\treg = <0xfc0000 0x040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tnvmem-cells = <&macaddr_art_6>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&eth1 {\n\tstatus = \"okay\";\n\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n\n\tmacaddr_art_6: macaddr@6 {\n\t\treg = <0x6 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9330_pqi_air-pen.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9330.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"PQI Air-Pen\";\n\tcompatible = \"pqi,air-pen\", \"qca,ar9330\";\n\n\taliases {\n\t\tled-boot = &led_wlan;\n\t\tled-failsafe = &led_wlan;\n\t\tled-upgrade = &led_wlan;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_wlan: wlan {\n\t\t\tlabel = \"blue:wlan\";\n\t\t\tgpios = <&gpio 0 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"blue:wps\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_HIGH>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n};\n\n&usb {\n\tdr_mode = \"host\";\n\tstatus = \"okay\";\n};\n\n&usb_phy {\n\tstatus = \"okay\";\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\tspi-max-frequency = <50000000>;\n\t\treg = <0>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x040000 0x010000>;\n\t\t\t};\n\n\t\t\tart: partition@50000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0x050000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@60000 {\n\t\t\t\tlabel = \"NVRAM\";\n\t\t\t\treg = <0x060000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@70000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x070000 0x780000>;\n\t\t\t};\n\n\t\t\tpartition@7f0000 {\n\t\t\t\tlabel = \"CONF\";\n\t\t\t\treg = <0x7f0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tnvmem-cells = <&macaddr_art_1002>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tgmac-config {\n\t\tdevice = <&gmac>;\n\n\t\tswitch-phy-addr-swap = <0>;\n\t\tswitch-phy-swap = <0>;\n\t};\n};\n\n&eth1 {\n\tstatus = \"okay\";\n\n\tcompatible = \"syscon\", \"simple-mfd\";\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n\tnvmem-cells = <&macaddr_art_2>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_2: macaddr@2 {\n\t\treg = <0x2 0x6>;\n\t};\n\n\tmacaddr_art_1002: macaddr@1002 {\n\t\treg = <0x1002 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9330_ziking_cpe46b.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9330.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"ZiKing CPE46B\";\n\tcompatible = \"ziking,cpe46b\", \"qca,ar9330\";\n\n\taliases {\n\t\tlabel-mac-device = &eth0;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twlan {\n\t\t\tlabel = \"green:wlan\";\n\t\t\tgpios = <&gpio 0 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\trssi1 {\n\t\t\tlabel = \"green:rssi1\";\n\t\t\tgpios = <&gpio 20 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\trssi2 {\n\t\t\tlabel = \"green:rssi2\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\tspi-max-frequency = <50000000>;\n\t\treg = <0>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@10000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x010000 0x010000>;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x020000 0x7d0000>;\n\t\t\t};\n\n\t\t\tart: partition@7f0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0x7f0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&eth1 {\n\tstatus = \"okay\";\n\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <2>;\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9331.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9330.dtsi\"\n\n/ {\n\tcompatible = \"qca,ar9331\";\n\n\tref: ref {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9331_8dev_carambola2.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9331.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"8devices Carambola2\";\n\tcompatible = \"8dev,carambola2\", \"qca,ar9331\";\n\n\taliases {\n\t\tlabel-mac-device = &wmac;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twlan {\n\t\t\tlabel = \"green:wlan\";\n\t\t\tgpios = <&gpio 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\teth0 {\n\t\t\tlabel = \"orange:eth0\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\teth1 {\n\t\t\tlabel = \"orange:eth1\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&ref {\n\tclock-frequency = <40000000>;\n};\n\n&usb {\n\tdr_mode = \"host\";\n\tstatus = \"okay\";\n};\n\n&usb_phy {\n\tstatus = \"okay\";\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\tspi-max-frequency = <50000000>;\n\t\treg = <0>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tuboot: partition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x040000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0xfa0000>;\n\t\t\t};\n\n\t\t\tart: partition@ff0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0xff0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tgmac-config {\n\t\tdevice = <&gmac>;\n\n\t\tswitch-phy-addr-swap = <1>;\n\t\tswitch-phy-swap = <1>;\n\t};\n};\n\n&eth1 {\n\tstatus = \"okay\";\n\tnvmem-cells = <&macaddr_art_6>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wmac {\n\tstatus = \"okay\";\n\tmtd-cal-data = <&art 0x1000>;\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n\n\tmacaddr_art_6: macaddr@6 {\n\t\treg = <0x6 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9331_alfa-network_ap121f.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9331_alfa-network_ap121f.dtsi\"\n\n/ {\n\tmodel = \"ALFA Network AP121F\";\n\tcompatible = \"alfa-network,ap121f\", \"qca,ar9331\";\n};\n\n&usb {\n\tdr_mode = \"host\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9331_alfa-network_ap121f.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9331.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\taliases {\n\t\tlabel-mac-device = &wmac;\n\t\tled-boot = &led_vpn;\n\t\tled-failsafe = &led_vpn;\n\t\tled-upgrade = &led_vpn;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\tswitch {\n\t\t\tlabel = \"switch\";\n\t\t\tlinux,code = <BTN_0>;\n\t\t\tgpios = <&gpio 21 GPIO_ACTIVE_HIGH>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tlan {\n\t\t\tlabel = \"green:lan\";\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_vpn: vpn {\n\t\t\tlabel = \"green:vpn\";\n\t\t\tgpios = <&gpio 27 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan {\n\t\t\tlabel = \"green:wlan\";\n\t\t\tgpios = <&gpio 0 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tgmac-config {\n\t\tdevice = <&gmac>;\n\t\tswitch-phy-addr-swap = <0>;\n\t\tswitch-phy-swap = <0>;\n\t};\n};\n\n&eth1 {\n\tstatus = \"okay\";\n\n\tcompatible = \"syscon\", \"simple-mfd\";\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <50000000>;\n\t\tm25p,fast-read;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x030000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x030000 0x010000>;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0x040000 0x010000>;\n\t\t\t\tread-only;\n\n\t\t\t\tcompatible = \"nvmem-cells\";\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\n\t\t\t\tcal_art_1000: cal@1000 {\n\t\t\t\t\treg = <0x1000 0x440>;\n\t\t\t\t};\n\n\t\t\t\tmacaddr_art_0: macaddr@0 {\n\t\t\t\t\treg = <0x0 0x6>;\n\t\t\t\t};\n\n\t\t\t\tmacaddr_art_1002: macaddr@1002 {\n\t\t\t\t\treg = <0x1002 0x6>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x050000 0xfb0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&usb {\n\tstatus = \"okay\";\n};\n\n&usb_phy {\n\tstatus = \"okay\";\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tnvmem-cells = <&cal_art_1000>, <&macaddr_art_1002>;\n\tnvmem-cell-names = \"calibration\", \"mac-address\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9331_alfa-network_ap121fe.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9331_alfa-network_ap121f.dtsi\"\n\n/ {\n\tmodel = \"ALFA Network AP121FE\";\n\tcompatible = \"alfa-network,ap121fe\", \"qca,ar9331\";\n};\n\n&usb {\n\tdr_mode = \"peripheral\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9331_arduino_yun.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9331.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"Arduino Yun\";\n\tcompatible = \"arduino,yun\", \"qca,ar9331\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyATH0,250000\";\n\t};\n\n\tahb {\n\t\tapb {\n\t\t\tpinmux_extended: pinmux@18040030 {\n\t\t\t\tcompatible = \"pinctrl-single\";\n\t\t\t\treg = <0x18040030 0x4>;\n\n\t\t\t\tpinctrl-single,bit-per-mux;\n\t\t\t\tpinctrl-single,register-width = <32>;\n\t\t\t\tpinctrl-single,function-mask = <0x1>;\n\t\t\t\t#pinctrl-cells = <2>;\n\n\t\t\t\tenable_gpio11: pinmux_enable_gpio11 {\n\t\t\t\t\tpinctrl-single,bits = <0x0 0x200 0x200>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tpinmux_bootstrap: pinmux@180600ac {\n\t\t\t\tcompatible = \"pinctrl-single\";\n\t\t\t\treg = <0x180600ac 0x4>;\n\n\t\t\t\tpinctrl-single,bit-per-mux;\n\t\t\t\tpinctrl-single,register-width = <32>;\n\t\t\t\tpinctrl-single,function-mask = <0x1>;\n\t\t\t\t#pinctrl-cells = <2>;\n\n\t\t\t\tenable_gpio26_gpio27: pinmux_enable_gpio26_gpio27 {\n\t\t\t\t\tpinctrl-single,bits = <0x0 0x40000 0x40000>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twlan {\n\t\t\tlabel = \"blue:wlan\";\n\t\t\tgpios = <&gpio 0 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\tusb {\n\t\t\tlabel = \"white:usb\";\n\t\t\tgpios = <&gpio 1 GPIO_ACTIVE_HIGH>;\n\t\t\ttrigger-sources = <&hub_port1>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\tconfig {\n\t\t\tlabel = \"config\";\n\t\t\tlinux,code = <BTN_0>;\n\t\t\tgpios = <&gpio 20 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tgpio-export {\n\t\tcompatible = \"gpio-export\";\n\n\t\tgpio_spi_enable {\n\t\t\tgpio-export,name = \"yun:oe:spi\";\n\t\t\tgpio-export,output = <0>;\n\t\t\tgpios = <&gpio 21 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tgpio_handshake_enable {\n\t\t\tgpio-export,name = \"yun:oe:hs\";\n\t\t\tgpio-export,output = <0>;\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tgpio_uart_enable {\n\t\t\tgpio-export,name = \"yun:oe:uart\";\n\t\t\tgpio-export,output = <0>;\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\treg_usb_vbus: reg_usb_vbus {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"usb_vbus\";\n\t\tregulator-min-microvolt = <5000000>;\n\t\tregulator-max-microvolt = <5000000>;\n\t\tenable-active-high;\n\t};\n};\n\n&pinmux {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&jtag_disable_pins &switch_led_disable_pins>;\n};\n\n&switch_led_disable_pins {\n\tpinctrl-single,bits = <0x0 0x80 0xf8>;\n};\n\n&pinmux_extended {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&enable_gpio11>;\n};\n\n&pinmux_bootstrap {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&enable_gpio26_gpio27>;\n};\n\n&usb {\n\tstatus = \"okay\";\n\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\tdr_mode = \"host\";\n\tvbus-supply = <&reg_usb_vbus>;\n\n\tport@1 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <1>;\n\t\t#trigger-source-cells = <0>;\n\n\t\thub_port1: port@1 {\n\t\t\treg = <1>;\n\t\t\t#trigger-source-cells = <0>;\n\t\t};\n\t};\n};\n\n&usb_phy {\n\tstatus = \"okay\";\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <50000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x40000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0xf90000>;\n\t\t\t};\n\n\t\t\tpartition@fe0000 {\n\t\t\t\tlabel = \"nvram\";\n\t\t\t\treg = <0xfe0000 0x10000>;\n\t\t\t};\n\n\t\t\tart: partition@ff0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0xff0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n};\n\n&eth1 {\n\tstatus = \"okay\";\n\n\tcompatible = \"syscon\", \"simple-mfd\";\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9331_embeddedwireless_dorin.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9331.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"Embedded Wireless Dorin\";\n\tcompatible = \"embeddedwireless,dorin\", \"qca,ar9331\";\n\n\taliases {\n\t\tled-boot = &led_status;\n\t\tled-failsafe = &led_status;\n\t\tled-running = &led_status;\n\t\tled-upgrade = &led_status;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_status: status {\n\t\t\tlabel = \"green:status\";\n\t\t\tgpios = <&gpio 21 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 6 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&usb {\n\tdr_mode = \"host\";\n\tstatus = \"okay\";\n};\n\n&usb_phy {\n\tstatus = \"okay\";\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\tspi-max-frequency = <50000000>;\n\t\treg = <0>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@1 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x040000 0x010000>;\n\t\t\t};\n\n\t\t\tpartition@2 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x050000 0xfa0000>;\n\t\t\t};\n\n\t\t\tart: partition@3 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0xff0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&eth1 {\n\tstatus = \"okay\";\n\n\tnvmem-cells = <&macaddr_art_1002>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment-byte = <3>;\n\tmac-address-increment = <0x40>;\n};\n\n&mdio1 {\n\tstatus = \"okay\";\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_1002: macaddr@1002 {\n\t\treg = <0x1002 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9331_etactica_eg200.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9331.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"eTactica EG200\";\n\tcompatible = \"etactica,eg200\", \"qca,ar9331\";\n\n\taliases {\n\t\tled-boot = &led_etactica;\n\t\tled-failsafe = &led_etactica;\n\t\tled-upgrade = &led_etactica;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\trestore {\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tpinctrl-names = \"default\";\n\t\tpinctrl-0 = <&switch_led_disable_pins>;\n\n\t\tmodbus {\n\t\t\tlabel = \"red:modbus\";\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tled_etactica: etactica {\n\t\t\tlabel = \"red:etactica\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\teth0 {\n\t\t\tlabel = \"red:eth0\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan {\n\t\t\tlabel = \"red:wlan\";\n\t\t\tgpios = <&gpio 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\t};\n};\n\n&usb {\n\tdr_mode = \"host\";\n\tstatus = \"okay\";\n};\n\n&usb_phy {\n\tstatus = \"okay\";\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tgmac-config {\n\t\tdevice = <&gmac>;\n\t\tswitch-phy-addr-swap = <1>;\n\t\tswitch-phy-swap = <1>;\n\t};\n};\n\n&eth1 {\n\tstatus = \"okay\";\n\tcompatible = \"syscon\", \"simple-mfd\";\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\tspi-max-frequency = <50000000>;\n\t\treg = <0>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tuboot@0 {\n\t\t\t\treg = <0x0 0x40000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tuboot-env@40000 {\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfirmware@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\treg = <0x50000 0xfa0000>;\n\t\t\t};\n\n\t\t\tart: art@ff0000 {\n\t\t\t\treg = <0xff0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&wmac {\n\tstatus = \"okay\";\n\tmtd-cal-data = <&art 0x1000>;\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9331_glinet_6408.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9331_glinet_64xx.dtsi\"\n\n/ {\n\tmodel = \"GL.iNet 6408\";\n\tcompatible = \"glinet,6408\", \"qca,ar9331\";\n\n\taliases {\n\t\tlabel-mac-device = &wmac;\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tuboot: partition@0 {\n\t\t\t\treg = <0x0 0x20000>;\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tcompatible = \"tplink,firmware\";\n\t\t\t\treg = <0x20000 0x7d0000>;\n\t\t\t\tlabel = \"firmware\";\n\t\t\t};\n\n\t\t\tart: partition@7f0000 {\n\t\t\t\treg = <0x7f0000 0x10000>;\n\t\t\t\tlabel = \"art\";\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&eth0 {\n\tnvmem-cells = <&macaddr_uboot_1fc00>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&eth1 {\n\tnvmem-cells = <&macaddr_uboot_1fc00>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wmac {\n\tmtd-cal-data = <&art 0x1000>;\n\n\tnvmem-cells = <&macaddr_uboot_1fc00>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&uboot {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_uboot_1fc00: macaddr@1fc00 {\n\t\treg = <0x1fc00 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9331_glinet_6416.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9331_glinet_64xx.dtsi\"\n\n/ {\n\tmodel = \"GL.iNet 6416\";\n\tcompatible = \"glinet,6416\", \"qca,ar9331\";\n\n\taliases {\n\t\tlabel-mac-device = &wmac;\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tuboot: partition@0 {\n\t\t\t\treg = <0x0 0x20000>;\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tcompatible = \"tplink,firmware\";\n\t\t\t\treg = <0x20000 0xfd0000>;\n\t\t\t\tlabel = \"firmware\";\n\t\t\t};\n\n\t\t\tart: partition@ff0000 {\n\t\t\t\treg = <0xff0000 0x10000>;\n\t\t\t\tlabel = \"art\";\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&eth0 {\n\tnvmem-cells = <&macaddr_uboot_1fc00>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&eth1 {\n\tnvmem-cells = <&macaddr_uboot_1fc00>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wmac {\n\tmtd-cal-data = <&art 0x1000>;\n\n\tnvmem-cells = <&macaddr_uboot_1fc00>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&uboot {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_uboot_1fc00: macaddr@1fc00 {\n\t\treg = <0x1fc00 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9331_glinet_64xx.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9331.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_HIGH>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twlan {\n\t\t\tlabel = \"red:wlan\";\n\t\t\tgpios = <&gpio 0 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\tlan {\n\t\t\tlabel = \"green:lan\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n\n\treg_usb_vbus: reg_usb_vbus {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"usb_vbus\";\n\t\tregulator-min-microvolt = <5000000>;\n\t\tregulator-max-microvolt = <5000000>;\n\t\tenable-active-high;\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tgmac-config {\n\t\tdevice = <&gmac>;\n\n\t\tswitch-phy-addr-swap = <0>;\n\t\tswitch-phy-swap = <0>;\n\t};\n};\n\n&eth1 {\n\tstatus = \"okay\";\n};\n\n&usb {\n\tdr_mode = \"host\";\n\tvbus-supply = <&reg_usb_vbus>;\n\tstatus = \"okay\";\n};\n\n&usb_phy {\n\tstatus = \"okay\";\n};\n\n&wmac {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9331_glinet_gl-mifi.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9331.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"glinet,gl-mifi\", \"qca,ar9331\";\n\tmodel = \"GL.iNet GL-MiFi\";\n\n\taliases {\n\t\tlabel-mac-device = &eth0;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twlan {\n\t\t\tlabel = \"green:wlan\";\n\t\t\tgpios = <&gpio 1 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\tlan {\n\t\t\tlabel = \"green:lan\";\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\twan {\n\t\t\tlabel = \"green:wan\";\n\t\t\tgpios = <&gpio 27 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\t3g4g {\n\t\t\tlabel = \"green:3g4g\";\n\t\t\tgpios = <&gpio 0 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_HIGH>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\treg_usb_vbus: reg_usb_vbus {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"usb_vbus\";\n\t\tregulator-min-microvolt = <5000000>;\n\t\tregulator-max-microvolt = <5000000>;\n\t\tgpio = <&gpio 6 GPIO_ACTIVE_LOW>;\n\t};\n\n\tgpio-export {\n\t\tcompatible = \"gpio-export\";\n\n\t\tminipcie {\n\t\t\tgpio-export,name = \"minipcie\";\n\t\t\tgpio-export,output = <0>;\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&usb {\n\tstatus = \"okay\";\n\n\tdr_mode = \"host\";\n\tvbus-supply = <&reg_usb_vbus>;\n};\n\n&usb_phy {\n\tstatus = \"okay\";\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\tspi-max-frequency = <33000000>;\n\t\treg = <0>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x040000 0x010000>;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x050000 0xfa0000>;\n\t\t\t};\n\n\t\t\tart: partition@ff0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0xff0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tgmac-config {\n\t\tdevice = <&gmac>;\n\n\t\tswitch-phy-addr-swap = <0>;\n\t\tswitch-phy-swap = <0>;\n\t};\n};\n\n&eth1 {\n\tstatus = \"okay\";\n\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9331_glinet_gl-usb150.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9331.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"glinet,gl-usb150\", \"qca,ar9331\";\n\tmodel = \"GL.iNet GL-USB150\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t\tlabel-mac-device = &eth0;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twlan {\n\t\t\tlabel = \"green:wlan\";\n\t\t\tgpios = <&gpio 0 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\tled_power: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_HIGH>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tgpio-export {\n\t\tcompatible = \"gpio-export\";\n\n\t\tgpio_lan_reset {\n\t\t\tgpio-export,name = \"lan:reset\";\n\t\t\tgpio-export,output = <0>;\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tgmac-config {\n\t\tdevice = <&gmac>;\n\t\tswitch-phy-addr-swap = <0>;\n\t\tswitch-phy-swap = <0>;\n\t};\n};\n\n&eth1 {\n\tstatus = \"okay\";\n\n\tcompatible = \"syscon\", \"simple-mfd\";\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\tspi-max-frequency = <33000000>;\n\t\treg = <0>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x040000 0x010000>;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x050000 0xfa0000>;\n\t\t\t};\n\n\t\t\tart: partition@ff0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0xff0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9331_hak5_lan-turtle.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9331_hak5_lan-turtle.dtsi\"\n\n/ {\n\tmodel = \"Hak5 LAN Turtle\";\n\tcompatible = \"hak5,lan-turtle\", \"qca,ar9331\";\n\n\taliases {\n\t\tled-boot = &led_system;\n\t\tled-failsafe = &led_system;\n\t\tled-upgrade = &led_system;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tpinctrl-names = \"default\";\n\t\tpinctrl-0 = <&switch_led_disable_pins>;\n\n\t\tled_system: system {\n\t\t\tlabel = \"orange:system\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9331_hak5_lan-turtle.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9331.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tkeys: keys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\tpinctrl-names = \"default\";\n\t\tpinctrl-0 = <&enable_gpio11>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tnvmem-cells = <&macaddr_uboot_1fc00>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <(-1)>;\n\n\tgmac-config {\n\t\tdevice = <&gmac>;\n\n\t\tswitch-phy-addr-swap = <1>;\n\t\tswitch-phy-swap = <1>;\n\t};\n};\n\n&eth1 {\n\tstatus = \"okay\";\n\n\tnvmem-cells = <&macaddr_uboot_1fc00>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <1>;\n};\n\n&pinmux {\n\tenable_gpio11: pinmux_enable_gpio11 {\n\t\tpinctrl-single,bits = <0x0 0x0 0x4>;\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <50000000>;\n\t\tm25p,fast-read;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tuboot: partition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x020000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x020000 0xfd0000>;\n\t\t\t\tcompatible = \"tplink,firmware\";\n\t\t\t};\n\n\t\t\tpartition@ff0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0xff0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&usb {\n\tstatus = \"okay\";\n};\n\n&usb_phy {\n\tstatus = \"okay\";\n};\n\n&uboot {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_uboot_1fc00: macaddr@1fc00 {\n\t\treg = <0x1fc00 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9331_hak5_packet-squirrel.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9331_hak5_lan-turtle.dtsi\"\n\n/ {\n\tmodel = \"Hak5 Packet Squirrel\";\n\tcompatible = \"hak5,packet-squirrel\", \"qca,ar9331\";\n\n\taliases {\n\t\tled-boot = &led_system_green;\n\t\tled-failsafe = &led_system_green;\n\t\tled-running = &led_system_green;\n\t\tled-upgrade = &led_system_green;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_system_green: system-green {\n\t\t\tlabel = \"green:system\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tsystem-blue {\n\t\t\tlabel = \"blue:system\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tsystem-red {\n\t\t\tlabel = \"red:system\";\n\t\t\tgpios = <&gpio 19 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&keys {\n\tsw1 {\n\t\tlabel = \"sw1\";\n\t\tlinux,code = <BTN_0>;\n\t\tgpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t\tdebounce-interval = <60>;\n\t};\n\n\tsw2 {\n\t\tlabel = \"sw2\";\n\t\tlinux,code = <BTN_1>;\n\t\tgpios = <&gpio 20 GPIO_ACTIVE_LOW>;\n\t\tdebounce-interval = <60>;\n\t};\n\n\tsw3 {\n\t\tlabel = \"sw3\";\n\t\tlinux,code = <BTN_2>;\n\t\tgpios = <&gpio 21 GPIO_ACTIVE_LOW>;\n\t\tdebounce-interval = <60>;\n\t};\n\n\tsw4 {\n\t\tlabel = \"sw4\";\n\t\tlinux,code = <BTN_3>;\n\t\tgpios = <&gpio 24 GPIO_ACTIVE_LOW>;\n\t\tdebounce-interval = <60>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9331_hak5_wifi-pineapple-nano.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9331.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"Hak5 WiFi Pineapple NANO\";\n\tcompatible = \"hak5,wifi-pineapple-nano\", \"qca,ar9331\";\n\n\taliases {\n\t\tlabel-mac-device = &wmac;\n\t\tled-boot = &led_system;\n\t\tled-failsafe = &led_system;\n\t\tled-upgrade = &led_system;\n\t};\n\n\tgpio-export {\n\t\tcompatible = \"gpio-export\";\n\t\t#size-cells = <0>;\n\n\t\tmicrosd-detect {\n\t\t\tgpio-export,name = \"microsd-detect\";\n\t\t\tgpios = <&gpio 19 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tusb-alarm {\n\t\t\tgpio-export,name = \"usb-alarm\";\n\t\t\tgpios = <&gpio 20 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tusb-power {\n\t\t\tgpio-export,name = \"usb-power\";\n\t\t\tgpio-export,output = <0>;\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_system: system {\n\t\t\tlabel = \"blue:system\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tnvmem-cells = <&macaddr_art_6>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&eth1 {\n\tstatus = \"okay\";\n\n\tcompatible = \"syscon\", \"simple-mfd\";\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <50000000>;\n\t\tm25p,fast-read;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x020000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x020000 0xfd0000>;\n\t\t\t\tcompatible = \"tplink,firmware\";\n\t\t\t};\n\n\t\t\tart: partition@ff0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0xff0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&usb {\n\tstatus = \"okay\";\n};\n\n&usb_phy {\n\tstatus = \"okay\";\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_6: macaddr@6 {\n\t\treg = <0x6 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9331_hiwifi_hc6361.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9331.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"HiWiFi HC6361\";\n\tcompatible = \"hiwifi,hc6361\", \"qca,ar9331\";\n\n\taliases {\n\t\tserial0 = &uart;\n\t\tled-boot = &led_system;\n\t\tled-failsafe = &led_system;\n\t\tled-running = &led_system;\n\t\tled-upgrade = &led_system;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_system: system {\n\t\t\tlabel = \"blue:system\";\n\t\t\tgpios = <&gpio 1 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t\twlan {\n\t\t\tlabel = \"blue:wlan\";\n\t\t\tgpios = <&gpio 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\twan {\n\t\t\tlabel = \"blue:wan\";\n\t\t\tgpios = <&gpio 27 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\treg_usb_vbus: regulator {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"usb_vbus\";\n\t\tregulator-min-microvolt = <5000000>;\n\t\tregulator-max-microvolt = <5000000>;\n\t\tenable-active-high;\n\t\tgpio = <&gpio 20 GPIO_ACTIVE_HIGH>;\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\tnum-cs = <1>;\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tuboot: partition@0 {\n\t\t\t\treg = <0x0 0x10000>;\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tbdinfo: partition@10000 {\n\t\t\t\treg = <0x10000 0x10000>;\n\t\t\t\tlabel = \"bdinfo\";\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfirmware: partition@20000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\treg = <0x20000 0xfc0000>;\n\t\t\t\tlabel = \"firmware\";\n\t\t\t};\n\n\t\t\tbackup: partition@fe0000 {\n\t\t\t\treg = <0xfe0000 0x10000>;\n\t\t\t\tlabel = \"backup\";\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tart: partition@ff0000 {\n\t\t\t\treg = <0xff0000 0x10000>;\n\t\t\t\tlabel = \"art\";\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&gpio {\n\tstatus = \"okay\";\n};\n\n&uart {\n\tstatus = \"okay\";\n};\n\n&usb {\n\tstatus = \"okay\";\n\tdr_mode = \"host\";\n\tvbus-supply = <&reg_usb_vbus>;\n};\n\n&usb_phy {\n\tstatus = \"okay\";\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tnvmem-cells = <&macaddr_bdinfo_18a>;\n\tnvmem-cell-names = \"mac-address-ascii\";\n\tmac-address-increment = <1>;\n};\n\n&eth1 {\n\tstatus = \"okay\";\n\n\tnvmem-cells = <&macaddr_bdinfo_18a>;\n\tnvmem-cell-names = \"mac-address-ascii\";\n};\n\n&wmac {\n\tstatus = \"okay\";\n\tmtd-cal-data = <&art 0x1000>;\n\n\tnvmem-cells = <&macaddr_bdinfo_18a>;\n\tnvmem-cell-names = \"mac-address-ascii\";\n\tmac-address-increment = <2>;\n};\n\n&bdinfo {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_bdinfo_18a: macaddr@18a {\n\t\treg = <0x18a 0x11>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9331_onion_omega.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9331.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"Onion Omega\";\n\tcompatible = \"onion,omega\", \"qca,ar9331\";\n\n\taliases {\n\t\tserial0 = &uart;\n\t\tlabel-mac-device = &wmac;\n\t\tled-boot = &led_system;\n\t\tled-failsafe = &led_system;\n\t\tled-running = &led_system;\n\t\tled-upgrade = &led_system;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_system: system {\n\t\t\tlabel = \"amber:system\";\n\t\t\tgpios = <&gpio 27 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_HIGH>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\treg_usb_vbus: reg_usb_vbus {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"usb_vbus\";\n\t\tregulator-min-microvolt = <5000000>;\n\t\tregulator-max-microvolt = <5000000>;\n\t\tgpio = <&gpio 8 GPIO_ACTIVE_HIGH>;\n\t\tenable-active-high;\n\t};\n};\n\n&ref {\n\tclock-frequency = <25000000>;\n};\n\n&usb {\n\tstatus = \"okay\";\n\n\tvbus-supply = <&reg_usb_vbus>;\n\tdr_mode = \"host\";\n};\n\n&usb_phy {\n\tstatus = \"okay\";\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tcompatible = \"syscon\", \"simple-mfd\";\n};\n\n&eth1 {\n\tstatus = \"okay\";\n\n\tnvmem-cells = <&macaddr_uboot_1fc00>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <(-1)>;\n\n\tgmac-config {\n\t\tdevice = <&gmac>;\n\t\tswitch-phy-addr-swap = <4>;\n\t\tswitch-phy-swap = <4>;\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\tspi-max-frequency = <25000000>;\n\t\treg = <0>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tuboot: partition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x020000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tcompatible = \"tplink,firmware\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x020000 0xfd0000>;\n\t\t\t};\n\n\t\t\tart: partition@ff0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0xff0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n\n\tnvmem-cells = <&macaddr_uboot_1fc00>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&uboot {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_uboot_1fc00: macaddr@1fc00 {\n\t\treg = <0x1fc00 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9331_pisen_ts-d084.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9331.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"Pisen TS-D084\";\n\tcompatible = \"pisen,ts-d084\", \"qca,ar9331\";\n\n\taliases {\n\t\tled-boot = &led_system;\n\t\tled-failsafe = &led_system;\n\t\tled-running = &led_system;\n\t\tled-upgrade = &led_system;\n\t\tlabel-mac-device = &wmac;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_system: system {\n\t\t\tlabel = \"blue:system\";\n\t\t\tgpios = <&gpio 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tuboot: partition@0 {\n\t\t\t\treg = <0x0 0x20000>;\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfirmware: partition@20000 {\n\t\t\t\tcompatible = \"tplink,firmware\";\n\t\t\t\treg = <0x20000 0x7d0000>;\n\t\t\t\tlabel = \"firmware\";\n\t\t\t};\n\n\t\t\tart: partition@7f0000 {\n\t\t\t\treg = <0x7f0000 0x10000>;\n\t\t\t\tlabel = \"art\";\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tnvmem-cells = <&macaddr_uboot_1fc00>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tgmac-config {\n\t\tdevice = <&gmac>;\n\n\t\tswitch-phy-addr-swap = <0>;\n\t\tswitch-phy-swap = <0>;\n\t};\n};\n\n&eth1 {\n\tstatus = \"okay\";\n\tcompatible = \"syscon\", \"simple-mfd\";\n};\n\n&usb {\n\tdr_mode = \"host\";\n\tstatus = \"okay\";\n};\n\n&usb_phy {\n\tstatus = \"okay\";\n};\n\n&wmac {\n\tstatus = \"okay\";\n\tmtd-cal-data = <&art 0x1000>;\n\tnvmem-cells = <&macaddr_uboot_1fc00>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&uboot {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_uboot_1fc00: macaddr@1fc00 {\n\t\treg = <0x1fc00 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9331_pisen_wmm003n.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9331.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"Pisen WMM003N\";\n\tcompatible = \"pisen,wmm003n\", \"qca,ar9331\";\n\n\taliases {\n\t\tled-boot = &led_system;\n\t\tled-failsafe = &led_system;\n\t\tled-running = &led_system;\n\t\tled-upgrade = &led_system;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_system: system {\n\t\t\tlabel = \"blue:system\";\n\t\t\tgpios = <&gpio 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\treg_usb_vbus: reg_usb_vbus {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"usb_vbus\";\n\t\tregulator-min-microvolt = <5000000>;\n\t\tregulator-max-microvolt = <5000000>;\n\t\tgpio = <&gpio 8 GPIO_ACTIVE_HIGH>;\n\t\tenable-active-high;\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tuboot: partition@0 {\n\t\t\t\treg = <0x0 0x20000>;\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfirmware: partition@20000 {\n\t\t\t\tcompatible = \"tplink,firmware\";\n\t\t\t\treg = <0x20000 0x7d0000>;\n\t\t\t\tlabel = \"firmware\";\n\t\t\t};\n\n\t\t\tart: partition@7f0000 {\n\t\t\t\treg = <0x7f0000 0x10000>;\n\t\t\t\tlabel = \"art\";\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tnvmem-cells = <&macaddr_uboot_1fc00>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tgmac-config {\n\t\tdevice = <&gmac>;\n\n\t\tswitch-phy-addr-swap = <0>;\n\t\tswitch-phy-swap = <0>;\n\t};\n};\n\n&eth1 {\n\tstatus = \"okay\";\n\tcompatible = \"syscon\", \"simple-mfd\";\n};\n\n&usb {\n\tdr_mode = \"host\";\n\tvbus-supply = <&reg_usb_vbus>;\n\tstatus = \"okay\";\n};\n\n&usb_phy {\n\tstatus = \"okay\";\n};\n\n&wmac {\n\tstatus = \"okay\";\n\tmtd-cal-data = <&art 0x1000>;\n\tnvmem-cells = <&macaddr_uboot_1fc00>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&uboot {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_uboot_1fc00: macaddr@1fc00 {\n\t\treg = <0x1fc00 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9331_teltonika_rut230-v1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9331.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"Teltonika RUT230 v1\";\n\tcompatible = \"teltonika,rut230-v1\", \"qca,ar9331\";\n\n\taliases {\n\t\tlabel-mac-device = &wmac;\n\t\tled-boot = &led_ss0;\n\t\tled-failsafe = &led_ss0;\n\t\tled-upgrade = &led_ss0;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\tinput {\n\t\t\tlabel = \"input\";\n\t\t\tlinux,code = <BTN_0>;\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\tsim-tray {\n\t\t\tlabel = \"sim-tray\";\n\t\t\tlinux,code = <BTN_1>;\n\t\t\tgpios = <&gpio 20 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tpinctrl-names = \"default\";\n\t\tpinctrl-0 = <&switch_led_disable_pins>;\n\n\t\tled_ss0: signal-strength-0 {\n\t\t\tlabel = \"green:signal-strength-0\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tsignal-strength-1 {\n\t\t\tlabel = \"green:signal-strength-1\";\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tsignal-strength-2 {\n\t\t\tlabel = \"green:signal-strength-2\";\n\t\t\tgpios = <&gpio 6 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tsignal-strength-3 {\n\t\t\tlabel = \"green:signal-strength-3\";\n\t\t\tgpios = <&gpio 26 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tsignal-strength-4 {\n\t\t\tlabel = \"green:signal-strength4\";\n\t\t\tgpios = <&gpio 27 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\t2g {\n\t\t\tlabel = \"green:2g\";\n\t\t\tgpios = <&gpio 8 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\t3g {\n\t\t\tlabel = \"green:3g\";\n\t\t\tgpios = <&gpio 24 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tlan {\n\t\t\tlabel = \"green:lan\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t\t/* GPIO 13 - ACTIVE HIGH for hwrev 0 */\n\t\t};\n\n\t\twan {\n\t\t\tlabel = \"green:wan\";\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t\t/* GPIO 14 - ACTIVE HIGH for hwrev 0 */\n\t\t};\n\n\t\t/* 4G LED - GPIO21 ACTIVE_HIGH for RUT240 */\n\t};\n\n\treg_usb_vbus: reg_usb_vbus {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"usb_vbus\";\n\t\tregulator-min-microvolt = <5000000>;\n\t\tregulator-max-microvolt = <5000000>;\n\t\tgpio = <&gpio 19 GPIO_ACTIVE_HIGH>;\n\t\tenable-active-high;\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tnvmem-cells = <&macaddr_config_0>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&eth1 {\n\tstatus = \"okay\";\n\n\tnvmem-cells = <&macaddr_config_0>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <1>;\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <30000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x20000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tconfig: partition@20000 {\n\t\t\t\tlabel = \"config\";\n\t\t\t\treg = <0x20000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tart: partition@30000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tcompatible = \"tplink,firmware\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x40000 0xf30000>;\n\t\t\t};\n\n\t\t\tpartition@f70000 {\n\t\t\t\tlabel = \"event-log\";\n\t\t\t\treg = <0xf70000 0x90000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&usb {\n\tdr_mode = \"host\";\n\tvbus-supply = <&reg_usb_vbus>;\n\tstatus = \"okay\";\n};\n\n&gpio {\n\tmodem-power {\n\t\tgpio-hog;\n\t\toutput-low;\n\t\tgpios = <18 GPIO_ACTIVE_HIGH>;\n\t\tline-name = \"modem-power\";\n\t};\n};\n\n&usb_phy {\n\tstatus = \"okay\";\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n\tnvmem-cells = <&macaddr_config_0>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <2>;\n};\n\n&config {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_config_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9331_tplink_tl-mr10u.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9331_tplink_tl-wr703n_tl-mr10u.dtsi\"\n\n/ {\n\tmodel = \"TP-Link TL-MR10U\";\n\tcompatible = \"tplink,tl-mr10u\", \"qca,ar9331\";\n};\n\n&reg_usb_vbus {\n\tgpio = <&gpio 18 GPIO_ACTIVE_HIGH>;\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9331_tplink_tl-mr3020-v1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-only\n\n#include \"ar9331.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"TP-Link TL-MR3020 V1\";\n\tcompatible = \"tplink,tl-mr3020-v1\", \"qca,ar9331\";\n\n\taliases {\n\t\tled-boot = &led_wps;\n\t\tled-failsafe = &led_wps;\n\t\tled-running = &led_wps;\n\t\tled-upgrade = &led_wps;\n\t\tlabel-mac-device = &eth0;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twlan {\n\t\t\tlabel = \"green:wlan\";\n\t\t\tgpios = <&gpio 0 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\tlan {\n\t\t\tlabel = \"green:lan\";\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_wps: wps {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&gpio 26 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled3g {\n\t\t\tlabel = \"green:3g\";\n\t\t\tgpios = <&gpio 27 GPIO_ACTIVE_LOW>;\n\t\t\ttrigger-sources = <&hub_port>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_HIGH>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\tsw1 {\n\t\t\tlabel = \"sw1\";\n\t\t\tlinux,input-type = <EV_SW>;\n\t\t\tlinux,code = <BTN_0>;\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_HIGH>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\tsw2 {\n\t\t\tlabel = \"sw2\";\n\t\t\tlinux,input-type = <EV_SW>;\n\t\t\tlinux,code = <BTN_1>;\n\t\t\tgpios = <&gpio 20 GPIO_ACTIVE_HIGH>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\treg_usb_vbus: reg_usb_vbus {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"usb_vbus\";\n\t\tregulator-min-microvolt = <5000000>;\n\t\tregulator-max-microvolt = <5000000>;\n\t\tgpio = <&gpio 8 GPIO_ACTIVE_HIGH>;\n\t\tenable-active-high;\n\t};\n};\n\n&ref {\n\tclock-frequency = <25000000>;\n};\n\n&usb {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\tdr_mode = \"host\";\n\tvbus-supply = <&reg_usb_vbus>;\n\tstatus = \"okay\";\n\n\thub_port: port@1 {\n\t\treg = <1>;\n\t\t#trigger-source-cells = <0>;\n\t};\n};\n\n&usb_phy {\n\tstatus = \"okay\";\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\t/* Spansion S25FL032PIF SPI flash */\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\tspi-max-frequency = <50000000>;\n\t\treg = <0>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tuboot: partition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x020000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tcompatible = \"tplink,firmware\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x020000 0x3c0000>;\n\t\t\t};\n\n\t\t\tpartition@3e0000 {\n\t\t\t\tlabel = \"config\";\n\t\t\t\treg = <0x3e0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tart: partition@3f0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0x3f0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tnvmem-cells = <&macaddr_uboot_1fc00>;\n\tnvmem-cell-names = \"mac-address\";\n\tgmac-config {\n\t\tdevice = <&gmac>;\n\n\t\tswitch-phy-addr-swap = <0>;\n\t\tswitch-phy-swap = <0>;\n\t};\n};\n\n&eth1 {\n\tstatus = \"okay\";\n\n\tcompatible = \"syscon\", \"simple-mfd\";\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n\tnvmem-cells = <&macaddr_uboot_1fc00>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&uboot {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_uboot_1fc00: macaddr@1fc00 {\n\t\treg = <0x1fc00 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9331_tplink_tl-mr3040-v2.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-only\n\n#include \"ar9331.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"TP-Link TL-MR3040 V2\";\n\tcompatible = \"tplink,tl-mr3040-v2\", \"qca,ar9331\";\n\n\taliases {\n\t\tled-boot = &led_lan;\n\t\tled-failsafe = &led_lan;\n\t\tlabel-mac-device = &eth0;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tpinctrl-names = \"default\";\n\t\tpinctrl-0 = <&switch_led_disable_pins>;\n\n\t\twlan {\n\t\t\tlabel = \"green:wlan\";\n\t\t\tgpios = <&gpio 26 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\tled_lan: lan {\n\t\t\tlabel = \"green:lan\";\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled3g {\n\t\t\tlabel = \"green:3g\";\n\t\t\tgpios = <&gpio 27 GPIO_ACTIVE_LOW>;\n\t\t\ttrigger-sources = <&hub_port>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_HIGH>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\tsw1 {\n\t\t\tlabel = \"sw1\";\n\t\t\tlinux,input-type = <EV_SW>;\n\t\t\tlinux,code = <BTN_0>;\n\t\t\tgpios = <&gpio 19 GPIO_ACTIVE_HIGH>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\tsw2 {\n\t\t\tlabel = \"sw2\";\n\t\t\tlinux,input-type = <EV_SW>;\n\t\t\tlinux,code = <BTN_1>;\n\t\t\tgpios = <&gpio 20 GPIO_ACTIVE_HIGH>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\treg_usb_vbus: reg_usb_vbus {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"usb_vbus\";\n\t\tregulator-min-microvolt = <5000000>;\n\t\tregulator-max-microvolt = <5000000>;\n\t\tgpio = <&gpio 18 GPIO_ACTIVE_HIGH>;\n\t\tenable-active-high;\n\t};\n};\n\n&ref {\n\tclock-frequency = <25000000>;\n};\n\n&usb {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\tdr_mode = \"host\";\n\tvbus-supply = <&reg_usb_vbus>;\n\tstatus = \"okay\";\n\n\thub_port: port@1 {\n\t\treg = <1>;\n\t\t#trigger-source-cells = <0>;\n\t};\n};\n\n&usb_phy {\n\tstatus = \"okay\";\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\tspi-max-frequency = <50000000>;\n\t\treg = <0>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tuboot: partition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x020000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tcompatible = \"tplink,firmware\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x020000 0x3d0000>;\n\t\t\t};\n\n\t\t\tart: partition@3f0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0x3f0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tnvmem-cells = <&macaddr_uboot_1fc00>;\n\tnvmem-cell-names = \"mac-address\";\n\tgmac-config {\n\t\tdevice = <&gmac>;\n\n\t\tswitch-phy-addr-swap = <0>;\n\t\tswitch-phy-swap = <0>;\n\t};\n};\n\n&eth1 {\n\tstatus = \"okay\";\n\n\tcompatible = \"syscon\", \"simple-mfd\";\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n\tnvmem-cells = <&macaddr_uboot_1fc00>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&uboot {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_uboot_1fc00: macaddr@1fc00 {\n\t\treg = <0x1fc00 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9331_tplink_tl-wr703n.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9331_tplink_tl-wr703n_tl-mr10u.dtsi\"\n\n/ {\n\tmodel = \"TP-Link TL-WR703N\";\n\tcompatible = \"tplink,tl-wr703n\", \"qca,ar9331\";\n};\n\n&reg_usb_vbus {\n\tgpio = <&gpio 8 GPIO_ACTIVE_HIGH>;\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9331_tplink_tl-wr703n_tl-mr10u.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9331.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\taliases {\n\t\tled-boot = &led_system;\n\t\tled-failsafe = &led_system;\n\t\tled-running = &led_system;\n\t\tled-upgrade = &led_system;\n\t\tlabel-mac-device = &eth0;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_system: system {\n\t\t\tlabel = \"blue:system\";\n\t\t\tgpios = <&gpio 27 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\treg_usb_vbus: reg_usb_vbus {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"usb_vbus\";\n\t\tregulator-min-microvolt = <5000000>;\n\t\tregulator-max-microvolt = <5000000>;\n\t\tenable-active-high;\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tuboot: partition@0 {\n\t\t\t\treg = <0x0 0x20000>;\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tcompatible = \"tplink,firmware\";\n\t\t\t\treg = <0x20000 0x3d0000>;\n\t\t\t\tlabel = \"firmware\";\n\t\t\t};\n\n\t\t\tart: partition@3f0000 {\n\t\t\t\treg = <0x3f0000 0x10000>;\n\t\t\t\tlabel = \"art\";\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tnvmem-cells = <&macaddr_uboot_1fc00>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tgmac-config {\n\t\tdevice = <&gmac>;\n\n\t\tswitch-phy-addr-swap = <0>;\n\t\tswitch-phy-swap = <0>;\n\t};\n};\n\n&eth1 {\n\tstatus = \"okay\";\n\n\tcompatible = \"syscon\", \"simple-mfd\";\n};\n\n&usb {\n\tdr_mode = \"host\";\n\tvbus-supply = <&reg_usb_vbus>;\n\tstatus = \"okay\";\n};\n\n&usb_phy {\n\tstatus = \"okay\";\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n\tnvmem-cells = <&macaddr_uboot_1fc00>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&uboot {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_uboot_1fc00: macaddr@1fc00 {\n\t\treg = <0x1fc00 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9331_tplink_tl-wr710n-8m.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9331_tplink_tl-wr710n.dtsi\"\n\n/ {\n\taliases {\n\t\tlabel-mac-device = &eth0;\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tuboot: partition@0 {\n\t\t\t\treg = <0x0 0x20000>;\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tcompatible = \"tplink,firmware\";\n\t\t\t\treg = <0x20000 0x7d0000>;\n\t\t\t\tlabel = \"firmware\";\n\t\t\t};\n\n\t\t\tart: partition@7f0000 {\n\t\t\t\treg = <0x7f0000 0x10000>;\n\t\t\t\tlabel = \"art\";\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&eth0 {\n\tnvmem-cells = <&macaddr_uboot_1fc00>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&eth1 {\n\tnvmem-cells = <&macaddr_uboot_1fc00>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <(-1)>;\n};\n\n&wmac {\n\tmtd-cal-data = <&art 0x1000>;\n\n\tnvmem-cells = <&macaddr_uboot_1fc00>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&uboot {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_uboot_1fc00: macaddr@1fc00 {\n\t\treg = <0x1fc00 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9331_tplink_tl-wr710n-v1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9331_tplink_tl-wr710n-8m.dtsi\"\n\n/ {\n\tmodel = \"TP-Link TL-WR710N v1\";\n\tcompatible = \"tplink,tl-wr710n-v1\", \"qca,ar9331\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9331_tplink_tl-wr710n-v2.1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9331_tplink_tl-wr710n-8m.dtsi\"\n\n/ {\n\tmodel = \"TP-Link TL-WR710N v2.1\";\n\tcompatible = \"tplink,tl-wr710n-v2.1\", \"qca,ar9331\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9331_tplink_tl-wr710n.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9331.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\taliases {\n\t\tled-boot = &led_system;\n\t\tled-failsafe = &led_system;\n\t\tled-running = &led_system;\n\t\tled-upgrade = &led_system;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_system: system {\n\t\t\tlabel = \"green:system\";\n\t\t\tgpios = <&gpio 27 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\treg_usb_vbus: regulator {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"usb_vbus\";\n\t\tregulator-min-microvolt = <5000000>;\n\t\tregulator-max-microvolt = <5000000>;\n\t\tgpio = <&gpio 8 GPIO_ACTIVE_HIGH>;\n\t\tenable-active-high;\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tgmac-config {\n\t\tdevice = <&gmac>;\n\n\t\tswitch-phy-addr-swap = <0>;\n\t\tswitch-phy-swap = <0>;\n\t};\n};\n\n&eth1 {\n\tstatus = \"okay\";\n};\n\n&usb {\n\tstatus = \"okay\";\n\n\tdr_mode = \"host\";\n\tvbus-supply = <&reg_usb_vbus>;\n};\n\n&usb_phy {\n\tstatus = \"okay\";\n};\n\n&wmac {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9331_tplink_tl-wr740n-v4.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9331_tplink_tl-wr741nd-v4.dtsi\"\n\n/ {\n\tmodel = \"TP-Link TL-WR740N v4\";\n\tcompatible = \"tplink,tl-wr740n-v4\", \"qca,ar9331\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9331_tplink_tl-wr740n-v5.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9331_tplink_tl-wr741nd-v4.dtsi\"\n\n/ {\n\tmodel = \"TP-Link TL-WR740N v5\";\n\tcompatible = \"tplink,tl-wr740n-v5\", \"qca,ar9331\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9331_tplink_tl-wr741nd-v4.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9331_tplink_tl-wr741nd-v4.dtsi\"\n\n/ {\n\tmodel = \"TP-Link TL-WR741N/ND v4\";\n\tcompatible = \"tplink,tl-wr741nd-v4\", \"qca,ar9331\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9331_tplink_tl-wr741nd-v4.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9331.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"tplink,tl-wr741n-v4\", \"qca,ar9331\";\n\tmodel = \"TP-Link TL-WR741N/ND v4\";\n\n\taliases {\n\t\tled-boot = &led_system;\n\t\tled-failsafe = &led_system;\n\t\tled-running = &led_system;\n\t\tled-upgrade = &led_system;\n\t\tlabel-mac-device = &wmac;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_HIGH>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tgpios = <&gpio 26 GPIO_ACTIVE_HIGH>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tpinctrl-names = \"default\";\n\t\tpinctrl-0 = <&switch_led_disable_pins>;\n\n\t\tlan1 {\n\t\t\tlabel = \"green:lan1\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tlan2 {\n\t\t\tlabel = \"green:lan2\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tlan3 {\n\t\t\tlabel = \"green:lan3\";\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tlan4 {\n\t\t\tlabel = \"green:lan4\";\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tqss {\n\t\t\tlabel = \"green:qss\";\n\t\t\tgpios = <&gpio 1 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tled_system: system {\n\t\t\tlabel = \"green:system\";\n\t\t\tgpios = <&gpio 27 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twan {\n\t\t\tlabel = \"green:wan\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\twlan {\n\t\t\tlabel = \"green:wlan\";\n\t\t\tgpios = <&gpio 0 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tuboot: partition@0 {\n\t\t\t\treg = <0x0 0x20000>;\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfirmware: partition@20000 {\n\t\t\t\tcompatible = \"tplink,firmware\";\n\t\t\t\treg = <0x20000 0x3d0000>;\n\t\t\t\tlabel = \"firmware\";\n\t\t\t};\n\n\t\t\tart: partition@3f0000 {\n\t\t\t\treg = <0x3f0000 0x10000>;\n\t\t\t\tlabel = \"art\";\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tnvmem-cells = <&macaddr_uboot_1fc00>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <1>;\n\n\tgmac-config {\n\t\tdevice = <&gmac>;\n\n\t\tswitch-phy-addr-swap = <1>;\n\t\tswitch-phy-swap = <1>;\n\t};\n};\n\n&eth1 {\n\tstatus = \"okay\";\n\n\tnvmem-cells = <&macaddr_uboot_1fc00>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <(-1)>;\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n\tnvmem-cells = <&macaddr_uboot_1fc00>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&uboot {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_uboot_1fc00: macaddr@1fc00 {\n\t\treg = <0x1fc00 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9341.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar934x.dtsi\"\n\n/ {\n\tcompatible = \"qca,ar9341\";\n};\n\n&cpuintc {\n\tqca,ddr-wb-channel-interrupts = <2>, <3>, <4>, <5>;\n\tqca,ddr-wb-channels = <&ddr_ctrl 4>, <&ddr_ctrl 2>,\n\t\t\t\t<&ddr_ctrl 0>, <&ddr_ctrl 1>;\n};\n\n&wmac {\n\tinterrupt-parent = <&cpuintc>;\n\tinterrupts = <2>;\n};\n\n&eth1 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9341_engenius_eap300-v2.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9341.dtsi\"\n#include \"ar934x_senao_loader.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"Engenius EAP300 v2\";\n\tcompatible = \"engenius,eap300-v2\", \"qca,ar9341\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 1 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"blue:power\";\n\t\t\tgpios = <&gpio 0 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\twlan {\n\t\t\tlabel = \"blue:wlan\";\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\t};\n};\n\n&eth1 {\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9341_engenius_ens202ext-v1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9341.dtsi\"\n#include \"ar934x_senao_loader.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"Engenius ENS202EXT v1\";\n\tcompatible = \"engenius,ens202ext-v1\", \"qca,ar9341\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"Reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 1 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"amber:power\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\twlan {\n\t\t\tlabel = \"amber:wlan\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\trssilow {\n\t\t\tlabel = \"red:rssilow\";\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\trssimedium {\n\t\t\tlabel = \"amber:rssimedium\";\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\trssihigh {\n\t\t\tlabel = \"green:rssihigh\";\n\t\t\tgpios = <&gpio 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tphy-handle = <&swphy0>;\n\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&eth1 {\n\tstatus = \"okay\";\n\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tgmac-config {\n\t\tdevice = <&gmac>;\n\t\tswitch-phy-swap = <1>;\n\t};\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9341_openmesh_om2p-hs-v1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9341_openmesh_om2p-hs.dtsi\"\n\n/ {\n\tcompatible = \"openmesh,om2p-hs-v1\", \"qca,ar9341\";\n\tmodel = \"OpenMesh OM2P-HS v1\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9341_openmesh_om2p-hs-v2.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9341_openmesh_om2p-hs.dtsi\"\n\n/ {\n\tcompatible = \"openmesh,om2p-hs-v2\", \"qca,ar9341\";\n\tmodel = \"OpenMesh OM2P-HS v2\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9341_openmesh_om2p-hs-v3.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9341_openmesh_om2p-hs.dtsi\"\n\n/ {\n\tcompatible = \"openmesh,om2p-hs-v3\", \"qca,ar9341\";\n\tmodel = \"OpenMesh OM2P-HS v3\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9341_openmesh_om2p-hs.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9341.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tchosen {\n\t\t/delete-property/ bootargs;\n\t};\n\n\taliases {\n\t\tled-boot = &led_power_blue;\n\t\tled-failsafe = &led_power_blue;\n\t\tled-running = &led_power_blue;\n\t\tled-upgrade = &led_power_blue;\n\t\tlabel-mac-device = &eth1;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\tpinctrl-names = \"default\";\n\t\tpinctrl-0 = <&jtag_disable_pins &led_lan_wan_blue_pin>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 1 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power_blue: power_blue {\n\t\t\tlabel = \"blue:power\";\n\t\t\tgpios = <&gpio 0 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\twifi_green {\n\t\t\tlabel = \"green:wifi\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\twifi_red {\n\t\t\tlabel = \"red:wifi\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twifi_yellow {\n\t\t\tlabel = \"yellow:wifi\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan_blue {\n\t\t\tlabel = \"blue:lan\";\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twan_blue {\n\t\t\tlabel = \"blue:wan\";\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\twatchdog {\n\t\tcompatible = \"linux,wdt-gpio\";\n\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\thw_algo = \"toggle\";\n\t\t/* hw_margin_ms is actually 300s but driver limits it to 60s */\n\t\thw_margin_ms = <60000>;\n\t\talways-running;\n\t};\n};\n\n&ref {\n\tclock-frequency = <40000000>;\n};\n\n&pinmux {\n\tled_lan_wan_blue_pin: pinmux_lan_wan_blue_pin {\n\t\tpinctrl-single,bits = <0x10 0x0 0x0000ffff>;\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <40000000>;\n\n\t\t/* partitions are passed via bootloader */\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x040000 0x040000>;\n\t\t\t};\n\n\t\t\tpartition@80000 {\n\t\t\t\tlabel = \"custom\";\n\t\t\t\treg = <0x080000 0x140000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@1c0000 {\n\t\t\t\tlabel = \"inactive\";\n\t\t\t\treg = <0x1c0000 0x700000>;\n\t\t\t};\n\n\t\t\tpartition@8c0000 {\n\t\t\t\tlabel = \"inactive2\";\n\t\t\t\treg = <0x8c0000 0x700000>;\n\t\t\t};\n\n\t\t\tart: partition@fc0000 {\n\t\t\t\tlabel = \"ART\";\n\t\t\t\treg = <0xfc0000 0x040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tphy-handle = <&swphy4>;\n\n\tnvmem-cells = <&macaddr_art_6>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&eth1 {\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n\n\tmacaddr_art_6: macaddr@6 {\n\t\treg = <0x6 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9341_pcs_cr3000.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9341.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"PowerCloud Systems CR3000\";\n\tcompatible = \"pcs,cr3000\", \"qca,ar9341\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\tpinctrl-names = \"default\";\n\t\tpinctrl-0 = <&jtag_disable_pins>;\n\n\t\treset {\n\t\t\tlabel = \"Reset button\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"WPS button\";\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"amber:power\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\twlan2g {\n\t\t\tlabel = \"blue:wlan\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\twan {\n\t\t\tlabel = \"blue:wan\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan1 {\n\t\t\tlabel = \"blue:lan1\";\n\t\t\tgpios = <&gpio 19 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan2 {\n\t\t\tlabel = \"blue:lan2\";\n\t\t\tgpios = <&gpio 20 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan3 {\n\t\t\tlabel = \"blue:lan3\";\n\t\t\tgpios = <&gpio 21 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan4 {\n\t\t\tlabel = \"blue:lan4\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&ref {\n\tclock-frequency = <25000000>;\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tuboot: partition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x040000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x050000 0x07a0000>;\n\t\t\t};\n\n\t\t\tart: partition@7f0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0x7f0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tphy-handle = <&swphy0>;\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <1>;\n};\n\n&eth1 {\n\tphy-handle = <&swphy4>;\n\tpll-data = <0x06000000 0x00000101 0x00001616>;\n\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tgmac-config {\n\t\tdevice = <&gmac>;\n\t\tswitch-phy-swap = <1>;\n\t};\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9341_pisen_wmb001n.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9341.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/mtd/partitions/uimage.h>\n\n/ {\n\tmodel = \"PISEN WMB001N\";\n\tcompatible = \"pisen,wmb001n\", \"qca,ar9341\";\n\n\taliases {\n\t\tled-boot = &led_wifi;\n\t\tled-failsafe = &led_wifi;\n\t\tled-running = &led_wifi;\n\t\tled-upgrade = &led_wifi;\n\t};\n\n\ti2c {\n\t\tcompatible = \"i2c-gpio\";\n\t\tpinctrl-names = \"default\";\n\t\tpinctrl-0 = <&pmx_i2c_gpio &pmx_i2s_spdif>;\n\n\t\tsda-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;\n\t\tscl-gpios = <&gpio 20 GPIO_ACTIVE_HIGH>;\n\t\t/*\n\t\t * Pull-up resistor for scl is missing on this board.\n\t\t * Following settings trick i2c-gpio to use output mode\n\t\t * instead of open-drain for scl.\n\t\t */\n\t\ti2c-gpio,scl-output-only;\n\t\ti2c-gpio,scl-open-drain;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\tvol_down {\n\t\t\tlabel = \"volume down\";\n\t\t\tlinux,code = <KEY_VOLUMEDOWN>;\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\tvol_up {\n\t\t\tlabel = \"volume up\";\n\t\t\tlinux,code = <KEY_VOLUMEUP>;\n\t\t\tgpios = <&gpio 19 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tpinctrl-names = \"default\";\n\t\tpinctrl-0 = <&jtag_disable_pins>;\n\n\t\tvolume1 {\n\t\t\tlabel = \"blue:volume1\";\n\t\t\tgpios = <&gpio 0 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tvolume2 {\n\t\t\tlabel = \"blue:volume2\";\n\t\t\tgpios = <&gpio 1 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tvolume3 {\n\t\t\tlabel = \"blue:volume3\";\n\t\t\tgpios = <&gpio 2 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tvolume4 {\n\t\t\tlabel = \"blue:volume4\";\n\t\t\tgpios = <&gpio 3 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tvolume5 {\n\t\t\tlabel = \"blue:volume5\";\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tled_wifi: wifi {\n\t\t\tlabel = \"blue:wifi\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n\n\tvirtual_flash {\n\t\tcompatible = \"mtd-concat\";\n\t\tdevices = <&fwconcat0 &fwconcat1>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\treg = <0x0 0x0>;\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\tcompatible = \"openwrt,uimage\", \"denx,uimage\";\n\t\t\t\topenwrt,ih-magic = <IH_MAGIC_OKLI>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pinmux {\n\tpmx_i2c_gpio: pinmux_i2c_gpio {\n\t\tpinctrl-single,bits = <0x10 0x0 0xff>,\n\t\t\t\t      <0x14 0x0 0xff>;\n\t};\n\n\tpmx_i2s_spdif: pinmux_i2s_spdif {\n\t\tpinctrl-single,bits = <0x8 0x0e000000 0xff000000>,\n\t\t\t\t      <0xc 0x0f0c0d 0xffffff>,\n\t\t\t\t      <0x14 0x1900 0xff00>;\n\t};\n};\n\n&ref {\n\tclock-frequency = <25000000>;\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tuboot: partition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@10000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x10000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfwconcat0: partition@20000 {\n\t\t\t\tlabel = \"fwconcat0\";\n\t\t\t\treg = <0x20000 0xdc0000>;\n\t\t\t};\n\n\t\t\tpartition@de0000 {\n\t\t\t\tlabel = \"loader\";\n\t\t\t\treg = <0xde0000 0x10000>;\n\t\t\t};\n\n\t\t\tfwconcat1: partition@df0000 {\n\t\t\t\tlabel = \"fwconcat1\";\n\t\t\t\treg = <0xdf0000 0x1f0000>;\n\t\t\t};\n\n\t\t\tpartition@fe0000 {\n\t\t\t\tlabel = \"mib0\";\n\t\t\t\treg = <0xfe0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tart: partition@ff0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0xff0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\tphy-handle = <&swphy4>;\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&eth1 {\n\tcompatible = \"syscon\", \"simple-mfd\";\n\tstatus = \"okay\";\n\n\tgmac-config {\n\t\tdevice = <&gmac>;\n\t\tswitch-phy-swap = <0>;\n\t};\n};\n\n&usb {\n\tstatus = \"okay\";\n};\n\n&usb_phy {\n\tstatus = \"okay\";\n};\n\n&wmac {\n\tstatus = \"okay\";\n\tmtd-cal-data = <&art 0x1000>;\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9341_tplink.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9341.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tleds: leds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\twlan {\n\t\t\tlabel = \"green:wlan\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\tqss {\n\t\t\tlabel = \"green:qss\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twan {\n\t\t\tlabel = \"green:wan\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan1 {\n\t\t\tlabel = \"green:lan1\";\n\t\t\tgpios = <&gpio 19 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan2 {\n\t\t\tlabel = \"green:lan2\";\n\t\t\tgpios = <&gpio 20 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan3 {\n\t\t\tlabel = \"green:lan3\";\n\t\t\tgpios = <&gpio 21 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan4 {\n\t\t\tlabel = \"green:lan4\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&ref {\n\tclock-frequency = <25000000>;\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&jtag_disable_pins &pmx_usb_power>;\n};\n\n&pinmux {\n\tpmx_usb_power: usb_power {\n\t\tpinctrl-single,bits = <0x4 0x0 0xff>;\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tphy-handle = <&swphy0>;\n};\n\n&eth1 {\n\tgmac-config {\n\t\tdevice = <&gmac>;\n\t\tswitch-phy-swap = <1>;\n\t};\n};\n\n&wmac {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9341_tplink_tl-mr3420-v2.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9341_tplink.dtsi\"\n\n/ {\n\tmodel = \"TP-Link TL-MR3420 v2\";\n\tcompatible = \"tplink,tl-mr3420-v2\", \"qca,ar9341\";\n\n\taliases {\n\t\tlabel-mac-device = &wmac;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\trfkill {\n\t\t\tlabel = \"WiFi\";\n\t\t\tlinux,code = <KEY_RFKILL>;\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"Reset/WPS\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n};\n\n&leds {\n\tusb {\n\t\tlabel = \"green:usb\";\n\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\ttrigger-sources = <&hub_port>;\n\t\tlinux,default-trigger = \"usbport\";\n\t};\n};\n\n&gpio {\n\tusb_power {\n\t\tgpio-hog;\n\t\tgpios = <4 GPIO_ACTIVE_HIGH>;\n\t\toutput-high;\n\t\tline-name = \"tp-link:power:usb\";\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tuboot: partition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x020000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tcompatible = \"tplink,firmware\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x020000 0x3d0000>;\n\t\t\t};\n\n\t\t\tart: partition@3f0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0x3f0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&usb {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\tstatus = \"okay\";\n\n\thub_port: port@1 {\n\t\treg = <1>;\n\t\t#trigger-source-cells = <0>;\n\t};\n};\n\n&usb_phy {\n\tstatus = \"okay\";\n};\n\n&eth0 {\n\tnvmem-cells = <&macaddr_uboot_1fc00>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <(-1)>;\n};\n\n&eth1 {\n\tnvmem-cells = <&macaddr_uboot_1fc00>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wmac {\n\tmtd-cal-data = <&art 0x1000>;\n\n\tnvmem-cells = <&macaddr_uboot_1fc00>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&uboot {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_uboot_1fc00: macaddr@1fc00 {\n\t\treg = <0x1fc00 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9341_tplink_tl-wa.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9341.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\taliases {\n\t\tlabel-mac-device = &wmac;\n\t};\n};\n\n&ref {\n\tclock-frequency = <25000000>;\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tuboot: partition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x020000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tcompatible = \"tplink,firmware\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x020000 0x3d0000>;\n\t\t\t};\n\n\t\t\tart: partition@3f0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0x3f0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tphy-handle = <&swphy0>;\n\n\tnvmem-cells = <&macaddr_uboot_1fc00>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tgmac-config {\n\t\tdevice = <&gmac>;\n\n\t\tswitch-phy-swap = <1>;\n\t};\n};\n\n&eth1 {\n\tcompatible = \"syscon\", \"simple-mfd\";\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n\tnvmem-cells = <&macaddr_uboot_1fc00>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&uboot {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_uboot_1fc00: macaddr@1fc00 {\n\t\treg = <0x1fc00 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9341_tplink_tl-wa850re-v1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9341_tplink_tl-wa.dtsi\"\n\n/ {\n\tmodel = \"TP-Link TL-WA850RE v1\";\n\tcompatible = \"tplink,tl-wa850re-v1\", \"qca,ar9341\";\n\n\taliases {\n\t\tled-boot = &led_re;\n\t\tled-failsafe = &led_re;\n\t\tled-running = &led_re;\n\t\tled-upgrade = &led_re;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"Reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"WPS\";\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tlan {\n\t\t\tlabel = \"blue:lan\";\n\t\t\tgpios = <&gpio 20 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan {\n\t\t\tlabel = \"blue:wlan\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\tled_re: re {\n\t\t\tlabel = \"blue:re\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tsignal1 {\n\t\t\tlabel = \"blue:signal1\";\n\t\t\tgpios = <&gpio 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tsignal2 {\n\t\t\tlabel = \"blue:signal2\";\n\t\t\tgpios = <&gpio 1 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tsignal3 {\n\t\t\tlabel = \"blue:signal3\";\n\t\t\tgpios = <&gpio 2 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tsignal4 {\n\t\t\tlabel = \"blue:signal4\";\n\t\t\tgpios = <&gpio 3 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tsignal5 {\n\t\t\tlabel = \"blue:signal5\";\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9341_tplink_tl-wa860re-v1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9341_tplink_tl-wa.dtsi\"\n\n/ {\n\tmodel = \"TP-Link TL-WA860RE v1\";\n\tcompatible = \"tplink,tl-wa860re-v1\", \"qca,ar9341\";\n\n\taliases {\n\t\tled-boot = &led_power_green;\n\t\tled-failsafe = &led_power_orange;\n\t\tled-running = &led_power_green;\n\t\tled-upgrade = &led_power_orange;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"Reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"WPS\";\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\tonoff {\n\t\t\tlabel = \"ONOFF\";\n\t\t\tlinux,code = <BTN_1>;\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tlan {\n\t\t\tlabel = \"green:lan\";\n\t\t\tgpios = <&gpio 20 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_power_green: power_green {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\tled_power_orange: power_orange {\n\t\t\tlabel = \"orange:power\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan_green {\n\t\t\tlabel = \"green:wlan\";\n\t\t\tgpios = <&gpio 2 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\twlan_orange {\n\t\t\tlabel = \"orange:wlan\";\n\t\t\tgpios = <&gpio 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9341_tplink_tl-wa901nd-v3.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9341_tplink_tl-wa.dtsi\"\n\n/ {\n\tmodel = \"TP-Link TL-WA901ND v3\";\n\tcompatible = \"tplink,tl-wa901nd-v3\", \"qca,ar9341\";\n\n\taliases {\n\t\tled-boot = &led_system;\n\t\tled-failsafe = &led_system;\n\t\tled-running = &led_system;\n\t\tled-upgrade = &led_system;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"Reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tlan {\n\t\t\tlabel = \"green:lan\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan {\n\t\t\tlabel = \"green:wlan\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\tqss {\n\t\t\tlabel = \"green:qss\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_system: system {\n\t\t\tlabel = \"green:system\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9341_tplink_tl-wr841-v8.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9341_tplink.dtsi\"\n\n/ {\n\tmodel = \"TP-Link TL-WR841N/ND v8\";\n\tcompatible = \"tplink,tl-wr841-v8\", \"qca,ar9341\";\n\n\taliases {\n\t\tlabel-mac-device = &wmac;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\trfkill {\n\t\t\tlabel = \"WiFi\";\n\t\t\tlinux,code = <KEY_RFKILL>;\n\t\t\tlinux,input-type = <EV_SW>;\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"Reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tuboot: partition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x020000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tcompatible = \"tplink,firmware\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x020000 0x3d0000>;\n\t\t\t};\n\n\t\t\tart: partition@3f0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0x3f0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&eth0 {\n\tnvmem-cells = <&macaddr_uboot_1fc00>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <(-1)>;\n};\n\n&eth1 {\n\tnvmem-cells = <&macaddr_uboot_1fc00>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wmac {\n\tmtd-cal-data = <&art 0x1000>;\n\n\tnvmem-cells = <&macaddr_uboot_1fc00>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&uboot {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_uboot_1fc00: macaddr@1fc00 {\n\t\treg = <0x1fc00 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9341_tplink_tl-wr842n-v2.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9341_tplink.dtsi\"\n\n/ {\n\tmodel = \"TP-Link TL-WR842N/ND v2\";\n\tcompatible = \"tplink,tl-wr842n-v2\", \"qca,ar9341\";\n\n\taliases {\n\t\tlabel-mac-device = &wmac;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\trfkill {\n\t\t\tlabel = \"WiFi\";\n\t\t\tlinux,code = <KEY_RFKILL>;\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"Reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tgpio-export {\n\t\tcompatible = \"gpio-export\";\n\n\t\tgpio_usb_power {\n\t\t\tgpio-export,name = \"tp-link:power:usb\";\n\t\t\tgpio-export,output = <1>;\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&leds {\n\tusb {\n\t\tlabel = \"green:usb\";\n\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\ttrigger-sources = <&hub_port>;\n\t\tlinux,default-trigger = \"usbport\";\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tuboot: partition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x020000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tcompatible = \"tplink,firmware\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x020000 0x7d0000>;\n\t\t\t};\n\n\t\t\tart: partition@7f0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0x7f0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&usb {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\tstatus = \"okay\";\n\n\thub_port: port@1 {\n\t\treg = <1>;\n\t\t#trigger-source-cells = <0>;\n\t};\n};\n\n&usb_phy {\n\tstatus = \"okay\";\n};\n\n&eth0 {\n\tnvmem-cells = <&macaddr_uboot_1fc00>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <(-1)>;\n};\n\n&eth1 {\n\tphy-handle = <&swphy4>;\n\n\tnvmem-cells = <&macaddr_uboot_1fc00>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wmac {\n\tmtd-cal-data = <&art 0x1000>;\n\n\tnvmem-cells = <&macaddr_uboot_1fc00>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&uboot {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_uboot_1fc00: macaddr@1fc00 {\n\t\treg = <0x1fc00 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9342_iodata_etg3-r.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9344.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"iodata,etg3-r\", \"qca,ar9344\";\n\tmodel = \"I-O DATA ETG3-R\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\tnotification {\n\t\t\tlabel = \"green:notification\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n};\n\n&ref {\n\tclock-frequency = <40000000>;\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x040000 0x010000>;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x050000 0x780000>;\n\t\t\t};\n\n\t\t\tpartition@7d0000 {\n\t\t\t\tlabel = \"Config\";\n\t\t\t\treg = <0x07d0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@7e0000 {\n\t\t\t\tlabel = \"Rsv\";\n\t\t\t\treg = <0x07e0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@7f0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0x7f0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t\tphy-mode = \"rgmii\";\n\n\t\tqca,ar8327-initvals = <\n\t\t\t0x04 0x07600000 /* PORT0 PAD MODE CTRL */\n\t\t\t0x50 0xffb7ffb7 /* LED_CTRL0 */\n\t\t\t0x54 0xffb7ffb7 /* LED_CTRL1 */\n\t\t\t0x58 0xffb7ffb7 /* LED_CTRL2 */\n\t\t\t0x5c 0x03ffff00 /* LED_CTRL3 */\n\t\t\t0x7c 0x0000007e /* PORT0_STATUS */\n\t\t>;\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tpll-data = <0x0e000000 0x00000101 0x00001616>;\n\n\tphy-mode = \"rgmii\";\n\tphy-handle = <&phy0>;\n\n\tgmac-config {\n\t\tdevice = <&gmac>;\n\n\t\trgmii-gmac0 = <1>;\n\t\trxd-delay = <3>;\n\t\trxdv-delay = <3>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9342_mikrotik_routerboard-912uag-2hpnd.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later\n\n#include \"ar9344.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"mikrotik,routerboard-912uag-2hpnd\", \"qca,ar9342\";\n\tmodel = \"MikroTik RouterBOARD 912UAG-2HPnD\";\n\n\taliases {\n                led-boot = &led_power;\n                led-failsafe = &led_power;\n                led-running = &led_power;\n                led-upgrade = &led_power;\n        };\n\n\tgpio_key: gpio_key {\n\t\tcompatible = \"mikrotik,gpio-rb91x-key\";\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\tgpio = <&gpio 15 GPIO_ACTIVE_HIGH>;\n\t};\n\n\tgpio_latch: gpio_latch {\n\t\tcompatible = \"gpio-latch\";\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\tgpios = <&gpio 0 GPIO_ACTIVE_HIGH>,\n\t\t\t<&gpio 1 GPIO_ACTIVE_HIGH>,\n\t\t\t<&gpio 2 GPIO_ACTIVE_HIGH>,\n\t\t\t<&gpio 3 GPIO_ACTIVE_HIGH>,\n\t\t\t<0>, /* Not connected */\n\t\t\t<&gpio 13 GPIO_ACTIVE_HIGH>,\n\t\t\t<&gpio 14 GPIO_ACTIVE_HIGH>,\n\t\t\t<&gpio_key 0 GPIO_ACTIVE_HIGH>,\n\t\t\t<&gpio 11 GPIO_ACTIVE_LOW>; /* Latch Enable */\n\t};\n\n\tnand_gpio {\n\t\tcompatible = \"mikrotik,rb91x-nand\";\n\n\t\tgpios = <&gpio_latch 3 GPIO_ACTIVE_HIGH>, /* Read */\n\t\t\t<&gpio 4 GPIO_ACTIVE_HIGH>,       /* Ready (RDY) */\n\t\t\t<&gpio_latch 5 GPIO_ACTIVE_LOW>,  /* Chip Enable (nCE) */\n\t\t\t<&gpio_latch 6 GPIO_ACTIVE_HIGH>, /* Command Latch Enable (CLE) */\n\t\t\t<&gpio_latch 7 GPIO_ACTIVE_HIGH>, /* Address Latch Enable (ALE) */\n\t\t\t<&gpio 12 GPIO_ACTIVE_LOW>,       /* Read/Write Enable (nRW) */\n\t\t\t<&gpio_latch 8 GPIO_ACTIVE_LOW>,  /* Latch Enable (nLE) */\n\t\t\t<&gpio_key 2 GPIO_ACTIVE_HIGH>;   /* Key poll disable */\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"booter\";\n\t\t\t\treg = <0x0 0x0040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"kernel\";\n\t\t\t\treg = <0x0040000 0x03c0000>;\n\t\t\t};\n\n\t\t\tpartition@400000 {\n\t\t\t\tlabel = \"ubi\";\n\t\t\t\treg = <0x0400000 0x7c00000>;\n\t\t\t};\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <20>;\n\n\t\tbutton@0 {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio_key 1 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio_latch 1 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\tuser {\n\t\t\tlabel = \"green:user\";\n\t\t\tgpios = <&gpio_latch 2 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tled1 {\n\t\t\tlabel = \"green:led1\";\n\t\t\tgpios = <&ssr 0 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tled2 {\n\t\t\tlabel = \"green:led2\";\n\t\t\tgpios = <&ssr 1 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tled3 {\n\t\t\tlabel = \"green:led3\";\n\t\t\tgpios = <&ssr 2 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tled4 {\n\t\t\tlabel = \"green:led4\";\n\t\t\tgpios = <&ssr 3 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tled5 {\n\t\t\tlabel = \"green:led5\";\n\t\t\tgpios = <&ssr 4 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n\n\tgpio-export {\n\t\tcompatible = \"gpio-export\";\n\n\t\tbeeper {\n\t\t\tgpio-export,name = \"beeper\";\n\t\t\tgpio-export,output = <1>;\t/* Must be 1 to avoid EMI induced clicking noise */\n\t\t\tgpios = <&ssr 5 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tusb_power {\n\t\t\tgpio-export,name = \"power-usb\";\n\t\t\tgpio-export,output = <1>;\n\t\t\tgpios = <&ssr 6 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tpcie_power {\n\t\t\tgpio-export,name = \"power-pcie\";\n\t\t\tgpio-export,output = <0>;\n\t\t\tgpios = <&ssr 7 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&ref {\n\tclock-frequency = <25000000>;\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tcompatible = \"qca,ar7100-spi\";\n\n\tcs-gpios = <0>, <&gpio_latch 0 GPIO_ACTIVE_LOW>;\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <50000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"mikrotik,routerboot-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"routerboot\";\n\t\t\t\treg = <0x0 0x0>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\thard_config {\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tbios {\n\t\t\t\tsize = <0x1000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tsoft_config {\n\t\t\t};\n\t\t};\n\t};\n\n\tssr: ssr@1 {\n\t\tcompatible = \"fairchild,74hc595\";\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\tregisters-number = <1>;\n\t\treg = <1>;\n\t\tspi-max-frequency = <50000000>;\n\t};\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy-mask = <0>;\n\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tphy-mode = \"rgmii-id\";\n\tphy-handle = <&phy0>;\n\tpll-data = <0x02000000 0x00000101 0x00001313>;\n\n\tgmac-config {\n\t\tdevice = <&gmac>;\n\t\trgmii-gmac0 = <1>;\n\t\trxd-delay = <1>;\n\t\ttxd-delay = <1>;\n\t};\n};\n\n&wmac {\n\tstatus = \"okay\";\n\tqca,no-eeprom;\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&usb {\n\tstatus = \"okay\";\n};\n\n&usb_phy {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9342_ubnt_aircube-ac.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9344.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"ubnt,aircube-ac\", \"qca,ar9342\";\n\tmodel = \"Ubiquiti airCube AC\";\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x040000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x050000 0xf60000>;\n\t\t\t};\n\n\t\t\tpartition@fb0000 {\n\t\t\t\tlabel = \"cfg\";\n\t\t\t\treg = <0xfb0000 0x040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tart: partition@ff0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0xff0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&ref {\n\tclock-frequency = <40000000>;\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy-mask = <4>;\n\tphy0: ethernet-phy@0 {\n\t\tphy-mode = \"rgmii\";\n\t\treg = <0>;\n\n\t\tqca,ar8327-initvals = <\n\t\t\t0x04 0x07600000 /* PORT0 PAD MODE CTRL */\n\t\t\t0x7c 0x0000007e /* PORT0_STATUS */\n\t\t>;\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\t/* default for ar934x, except for 1000M and 10M */\n\tpll-data = <0x06000000 0x00000101 0x00001313>;\n\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tphy-mode = \"rgmii\";\n\tphy-handle = <&phy0>;\n\n\tgmac-config {\n\t\tdevice = <&gmac>;\n\t};\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9342_ubnt_bullet-ac.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-only\n\n#include \"ar9342_ubnt_wa_1port.dtsi\"\n\n/ {\n\tcompatible = \"ubnt,bullet-ac\", \"ubnt,wa\", \"qca,ar9342\";\n\tmodel = \"Ubiquiti Bullet AC (2WA)\";\n\n\taliases {\n\t\tled-boot = &led_rssi3;\n\t\tled-failsafe = &led_rssi3;\n\t\tled-upgrade = &led_rssi3;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\trssi0 {\n\t\t\tlabel = \"blue:rssi0\";\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\trssi1 {\n\t\t\tlabel = \"blue:rssi1\";\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\trssi2 {\n\t\t\tlabel = \"blue:rssi2\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_rssi3: rssi3 {\n\t\t\tlabel = \"blue:rssi3\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9342_ubnt_bullet-m-xw.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9342_ubnt_xw.dtsi\"\n\n/ {\n\tcompatible = \"ubnt,bullet-m-xw\", \"ubnt,xw\", \"qca,ar9342\";\n\tmodel = \"Ubiquiti Bullet M (XW)\";\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy-mask = <4>;\n\tphy4: ethernet-phy@4 {\n\t\tphy-mode = \"rgmii\";\n\t\treg = <4>;\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tphy-mode = \"rgmii\";\n\tphy-handle = <&phy4>;\n\n\tgmac-config {\n\t\tdevice = <&gmac>;\n\t\trxd-delay = <3>;\n\t\trxdv-delay = <3>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9342_ubnt_lap-120.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-only\n\n#include \"ar9342_ubnt_wa_1port.dtsi\"\n\n/ {\n\tcompatible = \"ubnt,lap-120\", \"ubnt,wa\", \"qca,ar9342\";\n\tmodel = \"Ubiquiti LiteAP ac (LAP-120)\";\n};\n\n&wmac {\n\tstatus = \"disabled\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9342_ubnt_litebeam-ac-gen2.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-only\n\n#include \"ar9342_ubnt_wa_1port.dtsi\"\n\n/ {\n\tcompatible = \"ubnt,litebeam-ac-gen2\", \"ubnt,wa\", \"qca,ar9342\";\n\tmodel = \"Ubiquiti LiteBeam AC Gen2\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9342_ubnt_nanobeam-ac-gen2.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later\n\n#include \"ar9342_ubnt_wa_2port.dtsi\"\n\n/ {\n\tcompatible = \"ubnt,nanobeam-ac-gen2\", \"ubnt,wa\", \"qca,ar9342\";\n\tmodel = \"Ubiquiti NanoBeam AC Gen2 (WA)\";\n\n\taliases {\n\t\tled-boot = &led_rssi3;\n\t\tled-failsafe = &led_rssi3;\n\t\tled-upgrade = &led_rssi3;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\trssi0 {\n\t\t\tlabel = \"blue:rssi0\";\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\trssi1 {\n\t\t\tlabel = \"blue:rssi1\";\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\trssi2 {\n\t\t\tlabel = \"blue:rssi2\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_rssi3: rssi3 {\n\t\t\tlabel = \"blue:rssi3\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9342_ubnt_nanobeam-ac.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-only\n\n#include \"ar9342_ubnt_wa_1port.dtsi\"\n\n/ {\n\tcompatible = \"ubnt,nanobeam-ac\", \"ubnt,wa\", \"qca,ar9342\";\n\tmodel = \"Ubiquiti NanoBeam AC Gen1 (WA)\";\n\n\taliases {\n\t\tled-boot = &led_rssi3;\n\t\tled-failsafe = &led_rssi3;\n\t\tled-upgrade = &led_rssi3;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\trssi0 {\n\t\t\tlabel = \"blue:rssi0\";\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\trssi1 {\n\t\t\tlabel = \"blue:rssi1\";\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\trssi2 {\n\t\t\tlabel = \"blue:rssi2\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_rssi3: rssi3 {\n\t\t\tlabel = \"blue:rssi3\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9342_ubnt_nanostation-ac-loco.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-only\n\n#include \"ar9342_ubnt_wa_1port.dtsi\"\n\n/ {\n\tcompatible = \"ubnt,nanostation-ac-loco\", \"ubnt,wa\", \"qca,ar9342\";\n\tmodel = \"Ubiquiti Nanostation AC loco (WA)\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9342_ubnt_nanostation-ac.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-only\n\n#include \"ar9342_ubnt_wa_2port.dtsi\"\n\n/ {\n\tcompatible = \"ubnt,nanostation-ac\",\"ubnt,wa\", \"qca,ar9342\";\n\tmodel = \"Ubiquiti Nanostation AC (WA)\";\n\n\taliases {\n\t\tled-boot = &led_rssi3;\n\t\tled-failsafe = &led_rssi3;\n\t\tled-upgrade = &led_rssi3;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\trssi0 {\n\t\t\tlabel = \"blue:rssi0\";\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\trssi1 {\n\t\t\tlabel = \"blue:rssi1\";\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\trssi2 {\n\t\t\tlabel = \"blue:rssi2\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_rssi3: rssi3 {\n\t\t\tlabel = \"blue:rssi3\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9342_ubnt_nanostation-loco-m-xw.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9342_ubnt_xw.dtsi\"\n\n/ {\n\tcompatible = \"ubnt,nanostation-loco-m-xw\", \"ubnt,xw\", \"qca,ar9342\";\n\tmodel = \"Ubiquiti Nanostation Loco M (XW)\";\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy-mask = <0x1>;\n\n\tphy1: ethernet-phy@1 {\n\t\treg = <1>;\n\t\tphy-mode = \"mii\";\n\t\treset-gpios = <&gpio 0 GPIO_ACTIVE_LOW>;\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tphy-handle = <&phy1>;\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9342_ubnt_nanostation-m-xw.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9342_ubnt_xw.dtsi\"\n\n/ {\n\tcompatible = \"ubnt,nanostation-m-xw\", \"ubnt,xw\", \"qca,ar9342\";\n\tmodel = \"Ubiquiti Nanostation M (XW)\";\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy4-mii-enable;\n\tphy-mask = <0x23>;\n\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t\tphy-mode = \"mii\";\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tphy-handle = <&phy0>;\n\n\tgmac-config {\n\t\tdevice = <&gmac>;\n\t\tmii-gmac0 = <1>;\n\t\tmii-gmac0-slave = <1>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9342_ubnt_powerbeam-5ac-gen2.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-only\n\n#include \"ar9342_ubnt_wa_1port.dtsi\"\n\n/ {\n\tcompatible = \"ubnt,powerbeam-5ac-gen2\", \"ubnt,wa\", \"qca,ar9342\";\n\tmodel = \"Ubiquiti PowerBeam 5AC Gen2\";\n\n\taliases {\n\t\tled-boot = &led_rssi3;\n\t\tled-failsafe = &led_rssi3;\n\t\tled-upgrade = &led_rssi3;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\trssi0 {\n\t\t\tlabel = \"blue:rssi0\";\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\trssi1 {\n\t\t\tlabel = \"blue:rssi1\";\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\trssi2 {\n\t\t\tlabel = \"blue:rssi2\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_rssi3: rssi3 {\n\t\t\tlabel = \"blue:rssi3\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9342_ubnt_powerbeam-m2-xw.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9342_ubnt_xw.dtsi\"\n\n/ {\n\tcompatible = \"ubnt,powerbeam-m2-xw\", \"ubnt,xw\", \"qca,ar9342\";\n\tmodel = \"Ubiquiti PowerBeam M2 (XW)\";\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy-mask = <4>;\n\n\tphy1: ethernet-phy@1 {\n\t\treg = <1>;\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\t/* default for ar934x, except for 1000M and 10M */\n\tpll-data = <0x02000000 0x00000101 0x00001313>;\n\n\tphy-mode = \"rgmii-id\";\n\tphy-handle = <&phy1>;\n\n\tgmac-config {\n\t\tdevice = <&gmac>;\n\t\trxd-delay = <3>;\n\t\trxdv-delay = <3>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9342_ubnt_powerbeam-m5-xw.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9342_ubnt_xw.dtsi\"\n\n/ {\n\tcompatible = \"ubnt,powerbeam-m5-xw\", \"ubnt,xw\", \"qca,ar9342\";\n\tmodel = \"Ubiquiti PowerBeam M5 (XW)\";\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy-mask = <4>;\n\n\tphy4: ethernet-phy@4 {\n\t\treg = <4>;\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\t/* default for ar934x, except for 1000M and 10M */\n\tpll-data = <0x02000000 0x00000101 0x00001313>;\n\n\tphy-mode = \"rgmii-id\";\n\tphy-handle = <&phy4>;\n\n\tgmac-config {\n\t\tdevice = <&gmac>;\n\t\trxd-delay = <3>;\n\t\trxdv-delay = <3>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9342_ubnt_wa.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-only\n\n#include \"ar9344.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"ubnt,wa\", \"qca,ar9342\";\n\tmodel = \"Ubiquiti Networks WA board\";\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"Reset button\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n};\n\n&ref {\n\tclock-frequency = <40000000>;\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x040000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x050000 0xf60000>;\n\t\t\t};\n\n\t\t\tpartition@fb0000 {\n\t\t\t\tlabel = \"cfg\";\n\t\t\t\treg = <0xfb0000 0x040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tart: partition@ff0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0xff0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tieee80211-freq-limit = <2402000 2482000>;\n\tmtd-cal-data = <&art 0x1000>;\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9342_ubnt_wa_1port.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-only\n\n#include \"ar9342_ubnt_wa.dtsi\"\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy-mask = <4>;\n\n\tphy4: ethernet-phy@4 {\n\t\treg = <4>;\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\t/* default for ar934x, except for 1000M and 10M */\n\tpll-data = <0x02000000 0x00000101 0x00001313>;\n\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tphy-mode = \"rgmii-id\";\n\tphy-handle = <&phy4>;\n\n\tgmac-config {\n\t\tdevice = <&gmac>;\n\t\trxd-delay = <3>;\n\t\trxdv-delay = <3>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9342_ubnt_wa_2port.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-only\n\n#include \"ar9342_ubnt_wa.dtsi\"\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy-mask = <4>;\n\n\tphy0: ethernet-phy@0 {\n\t\tphy-mode = \"rgmii\";\n\t\treg = <0>;\n\n\t\tqca,ar8327-initvals = <\n\t\t\t0x04 0x07600000 /* PORT0 PAD MODE CTRL */\n\t\t\t0x58 0xffb7ffb7 /* LED_CTRL2 */\n\t\t\t0x5c 0x03ffff00 /* LED_CTRL3 */\n\t\t\t0x7c 0x0000007e /* PORT0_STATUS */\n\t\t>;\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\t/* default for ar934x, except for 1000M and 10M */\n\tpll-data = <0x06000000 0x00000101 0x00001313>;\n\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tphy-mode = \"rgmii\";\n\tphy-handle = <&phy0>;\n\n\tgmac-config {\n\t\tdevice = <&gmac>;\n\t\trxd-delay = <2>;\n\t\trxdv-delay = <2>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9342_ubnt_xw.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9344.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"ubnt,xw\", \"qca,ar9342\";\n\tmodel = \"Ubiquiti Networks XW board\";\n\n\taliases {\n\t\tled-boot = &led_link4;\n\t\tled-running = &led_link4;\n\t\tled-upgrade = &led_link4;\n\t\tled-failsafe = &led_link4;\n\t\tlabel-mac-device = &wmac;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tlink1 {\n\t\t\tlabel = \"red:link1\";\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlink2 {\n\t\t\tlabel = \"orange:link2\";\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlink3 {\n\t\t\tlabel = \"green:link3\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_link4: link4 {\n\t\t\tlabel = \"green:link4\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"Reset button\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n};\n\n&ref {\n\tclock-frequency = <40000000>;\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x040000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x050000 0x760000>;\n\t\t\t};\n\n\t\t\tpartition@7b0000 {\n\t\t\t\tlabel = \"cfg\";\n\t\t\t\treg = <0x7b0000 0x040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tart: partition@7f0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0x7f0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n};\n\n&eth0 {\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9344.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar934x.dtsi\"\n\n/ {\n\tcompatible = \"qca,ar9344\";\n};\n\n&cpuintc {\n\tqca,ddr-wb-channel-interrupts = <3>, <4>, <5>;\n\tqca,ddr-wb-channels = <&ddr_ctrl 2>, <&ddr_ctrl 0>,\n\t\t\t<&ddr_ctrl 1>;\n};\n\n&rst {\n\tintc2: interrupt-controller {\n\t\tcompatible = \"qca,ar9340-intc\";\n\n\t\tinterrupt-parent = <&cpuintc>;\n\t\tinterrupts = <2>;\n\n\t\tinterrupt-controller;\n\t\t#interrupt-cells = <1>;\n\n\t\tqca,int-status-addr = <0xac>;\n\t\tqca,pending-bits = <0xf>,\t/* wmac */\n\t\t\t\t<0x1f0>;\t/* pcie rc1 */\n\n\t\tqca,ddr-wb-channel-interrupts = <0>, <1>;\n\t\tqca,ddr-wb-channels = <&ddr_ctrl 4>, <&ddr_ctrl 3>;\n\t};\n};\n\n&ahb {\n\tpcie: pcie-controller@180c0000 {\n\t\tcompatible = \"qcom,ar9340-pci\", \"qcom,ar7240-pci\";\n\t\t#address-cells = <3>;\n\t\t#size-cells = <2>;\n\t\tbus-range = <0x0 0x0>;\n\t\treg = <0x180c0000 0x1000>, /* CRP */\n\t\t\t\t<0x180f0000 0x100>, /* CTRL */\n\t\t\t\t<0x14000000 0x1000>; /* CFG */\n\t\treg-names = \"crp_base\", \"ctrl_base\", \"cfg_base\";\n\t\tranges = <0x2000000 0 0x10000000 0x10000000 0 0x04000000 /* pci memory */\n\t\t\t\t0x1000000 0 0x00000000 0x0000000 0 0x000001>; /* io space */\n\t\tinterrupt-parent = <&intc2>;\n\t\tinterrupts = <1>;\n\n\t\tdevice_type = \"pci\";\n\n\t\tresets = <&rst 6>, <&rst 7>;\n\t\treset-names = \"hc\", \"phy\";\n\n\t\tinterrupt-controller;\n\t\t#interrupt-cells = <1>;\n\n\t\tinterrupt-map-mask = <0 0 0 1>;\n\t\tinterrupt-map = <0 0 0 0 &pcie 0>;\n\n\t\tstatus = \"disabled\";\n\t};\n};\n\n&wmac {\n\tinterrupt-parent = <&intc2>;\n\tinterrupts = <0>;\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9344_aerohive_hiveap-121.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-only\n\n#include \"ar9344.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"aerohive,hiveap-121\", \"qca,ar9344\";\n\tmodel = \"Aerohive HiveAP 121\";\n\n\taliases {\n\t\tled-boot = &led_power_white;\n\t\tled-failsafe = &led_power_orange;\n\t\tled-running = &led_power_white;\n\t\tled-upgrade = &led_power_orange;\n\t\tlabel-mac-device = &eth0;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,9600\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"Reset button\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power_orange: power_orange {\n\t\t\tlabel = \"orange:power\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_power_white: power_white {\n\t\t\tlabel = \"white:power\";\n\t\t\tgpios = <&gpio 21 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\ti2c {\n\t\tcompatible = \"i2c-gpio\";\n\t\tgpios = <&gpio 13 GPIO_ACTIVE_HIGH /* sda */\n\t\t\t &gpio 12 GPIO_ACTIVE_HIGH /* scl */\n\t\t\t>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\ttpm@29 {\n\t\t\tcompatible = \"atmel,at97sc3204t\";\n\t\t\treg = <0x29>;\n\t\t};\n\t};\n};\n\n&ref {\n\tclock-frequency = <40000000>;\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&jtag_disable_pins>;\n\n\tgpio_ext_lna0 {\n\t\tgpio-hog;\n\t\tgpios = <20 0>;\n\t\toutput-low;\n\t\tline-name = \"hiveap-121:ext:lna0\";\n\t};\n\n\tgpio_ext_lna1 {\n\t\tgpio-hog;\n\t\tgpios = <19 0>;\n\t\toutput-low;\n\t\tline-name = \"hiveap-121:ext:lna1\";\n\t};\n\n\tgpio_usb_power {\n\t\tgpio-hog;\n\t\tgpios = <15 0>;\n\t\toutput-high;\n\t\tline-name = \"hiveap-121:power:usb\";\n\t};\n};\n\n&usb {\n\tstatus = \"okay\";\n};\n\n&usb_phy {\n\tstatus = \"okay\";\n};\n\n&pcie {\n\tstatus = \"okay\";\n\n\twifi@0,0 {\n\t\tcompatible = \"pci168c,0030\";\n\t\treg = <0x0000 0 0 0 0>;\n\n\t\tnvmem-cells = <&macaddr_hw_info_0>;\n\t\tnvmem-cell-names = \"mac-address\";\n\t\tmac-address-increment = <2>;\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x80000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@80000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x80000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\thw_info: partition@90000 {\n\t\t\t\tlabel = \"hw-info\";\n\t\t\t\treg = <0x90000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@a0000 {\n\t\t\t\tlabel = \"boot-info\";\n\t\t\t\treg = <0xa0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@b0000 {\n\t\t\t\tlabel = \"boot-sinfo\";\n\t\t\t\treg = <0xb0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tnvmem-cells = <&macaddr_hw_info_0>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <1>;\n};\n\n&nand {\n\tstatus = \"okay\";\n\n\tpartitions {\n\t\tcompatible = \"fixed-partitions\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"u-boot1\";\n\t\t\treg = <0x0 0x400000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@400000 {\n\t\t\tlabel = \"u-boot-env1\";\n\t\t\treg = <0x400000 0x400000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@800000 {\n\t\t\tlabel = \"kernel\";\n\t\t\treg = <0x800000 0x500000>;\n\t\t};\n\n\t\tpartition@d00000 {\n\t\t\tlabel = \"ubi\";\n\t\t\treg = <0xd00000 0x6f00000>;\n\t\t};\n\n\t\tpartition@2e00000 {\n\t\t\tlabel = \"wifi-info\";\n\t\t\treg = <0x7c00000 0x400000>;\n\t\t\tread-only;\n\t\t};\n\t};\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tpll-data = <0x06000000 0x00000101 0x00001313>;\n\n\tnvmem-cells = <&macaddr_hw_info_0>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tphy-mode = \"rgmii-id\";\n\tphy-handle = <&phy0>;\n\n\tgmac-config {\n\t\tdevice = <&gmac>;\n\t\trgmii-gmac0 = <1>;\n\t\trxd-delay = <1>;\n\t\trxdv-delay = <1>;\n\t};\n};\n\n&hw_info {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_hw_info_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9344_alfa-network_n5q.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9344.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"ALFA Network N5Q\";\n\tcompatible = \"alfa-network,n5q\", \"qca,ar9344\";\n\n\taliases {\n\t\tlabel-mac-device = &wmac;\n\t\tled-boot = &led_signal4;\n\t\tled-failsafe = &led_signal4;\n\t\tled-upgrade = &led_signal4;\n\t};\n\n\tgpio-export {\n\t\tcompatible = \"gpio-export\";\n\t\t#size-cells = <0>;\n\n\t\twatchdog-enable {\n\t\t\tgpio-export,name = \"watchdog-enable\";\n\t\t\tgpio-export,output = <1>;\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tlan1 {\n\t\t\tlabel = \"green:lan1\";\n\t\t\tgpios = <&gpio 19 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan2 {\n\t\t\tlabel = \"green:lan2\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_signal4: signal4 {\n\t\t\tlabel = \"green:signal4\";\n\t\t\tgpios = <&gpio 3 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tsignal1 {\n\t\t\tlabel = \"red:signal1\";\n\t\t\tgpios = <&gpio 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tsignal2 {\n\t\t\tlabel = \"orange:signal2\";\n\t\t\tgpios = <&gpio 1 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tsignal3 {\n\t\t\tlabel = \"green:signal3\";\n\t\t\tgpios = <&gpio 2 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan {\n\t\t\tlabel = \"green:wlan\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\t};\n\n\twatchdog {\n\t\tcompatible = \"linux,wdt-gpio\";\n\t\tgpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\t\thw_algo = \"toggle\";\n\t\thw_margin_ms = <25000>;\n\t\talways-running;\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n\tphy-handle = <&swphy4>;\n};\n\n&eth1 {\n\tstatus = \"okay\";\n\n\tnvmem-cells = <&macaddr_art_6>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&ref {\n\tclock-frequency = <40000000>;\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <50000000>;\n\t\tm25p,fast-read;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x060000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@60000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x060000 0x010000>;\n\t\t\t};\n\n\t\t\tpartition@70000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0x070000 0x010000>;\n\t\t\t\tread-only;\n\n\t\t\t\tcompatible = \"nvmem-cells\";\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\n\t\t\t\tcal_art_1000: cal@1000 {\n\t\t\t\t\treg = <0x1000 0x440>;\n\t\t\t\t};\n\n\t\t\t\tmacaddr_art_0: macaddr@0 {\n\t\t\t\t\treg = <0x0 0x6>;\n\t\t\t\t};\n\n\t\t\t\tmacaddr_art_6: macaddr@6 {\n\t\t\t\t\treg = <0x6 0x6>;\n\t\t\t\t};\n\n\t\t\t\tmacaddr_art_1002: macaddr@1002 {\n\t\t\t\t\treg = <0x1002 0x6>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tpartition@80000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x080000 0xf80000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tnvmem-cells = <&cal_art_1000>, <&macaddr_art_1002>;\n\tnvmem-cell-names = \"calibration\", \"mac-address\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9344_araknis_an-300-ap-i-n.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9344.dtsi\"\n#include \"ar934x_senao_loader.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"araknis,an-300-ap-i-n\", \"qca,ar9344\";\n\tmodel = \"Araknis AN-300-AP-I-N\";\n\n\taliases {\n\t\tlabel-mac-device = &eth0;\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"amber:power\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\twifi5g {\n\t\t\tlabel = \"blue:wifi5g\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"blue:wps\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tath9k-leds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twifi2g {\n\t\t\tlabel = \"blue:wifi2g\";\n\t\t\tgpios = <&ath9k 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\t};\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t\teee-broken-100tx;\n\t\teee-broken-1000t;\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-txid\";\n\n\tpll-data = <0x02000000 0x00000101 0x00001313>;\n};\n\n&pcie {\n\tstatus = \"okay\";\n\n\tath9k: wifi@0,0,0 {\n\t\tcompatible = \"pci168c,0030\";\n\t\treg = <0x0 0 0 0 0>;\n\t\tnvmem-cells = <&macaddr_art_0>;\n\t\tnvmem-cell-names = \"mac-address\";\n\t\tmac-address-increment = <1>;\n\t\tqca,disable-5ghz;\n\t\tqca,no-eeprom;\n\t\t#gpio-cells = <2>;\n\t\tgpio-controller;\n\t};\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tqca,disable-2ghz;\n\n\tmtd-cal-data = <&art 0x1000>;\n\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <2>;\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9344_atheros_db120.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9344.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/mtd/partitions/uimage.h>\n\n/ {\n\tmodel = \"Atheros DB120 reference board\";\n\tcompatible = \"atheros,db120\", \"qca,ar9344\";\n\n\taliases {\n\t\tled-boot = &led_system;\n\t\tled-failsafe = &led_system;\n\t\tled-running = &led_system;\n\t\tled-upgrade = &led_system;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twlan2g {\n\t\t\tlabel = \"green:wlan2g\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\twlan5g {\n\t\t\tlabel = \"green:wlan5g\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\n\t\tled_system: system {\n\t\t\tlabel = \"green:system\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\tusb {\n\t\t\tlabel = \"green:usb\";\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\t\ttrigger-sources = <&hub_port1>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\t};\n\n\tleds-ath9k {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twlan5g-ath {\n\t\t\tlabel = \"green:wlan5g-ath\";\n\t\t\tgpios = <&ath9k 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\twps {\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tlabel = \"WPS button\";\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tvirtual_flash {\n\t\tcompatible = \"mtd-concat\";\n\t\tdevices = <&fwconcat0 &fwconcat1>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\treg = <0x0 0x0>;\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\tcompatible = \"openwrt,uimage\", \"denx,uimage\";\n\t\t\t\topenwrt,ih-magic = <IH_MAGIC_OKLI>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&ref {\n\tclock-frequency = <40000000>;\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tuboot: partition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x040000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfwconcat0: partition@50000 {\n\t\t\t\tlabel = \"fwconcat0\";\n\t\t\t\treg = <0x050000 0x630000>;\n\t\t\t};\n\n\t\t\tpartition@680000 {\n\t\t\t\tlabel = \"loader\";\n\t\t\t\treg = <0x680000 0x010000>;\n\t\t\t};\n\n\t\t\tfwconcat1: partition@690000 {\n\t\t\t\tlabel = \"fwconcat1\";\n\t\t\t\treg = <0x690000 0x150000>;\n\t\t\t};\n\n\t\t\tpartition@7e0000 {\n\t\t\t\tlabel = \"nvram\";\n\t\t\t\treg = <0x7e0000 0x010000>;\n\t\t\t};\n\n\t\t\tart: partition@7f0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0x7f0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tpll-data = <0x06000000 0x00000101 0x00001616>;\n\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tphy-mode = \"rgmii\";\n\tphy-handle = <&phy0>;\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy-mask = <0>;\n\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\n\t\tqca,ar8327-initvals = <\n\t\t\t0x04 0x07600000 /* PORT0 PAD MODE CTRL */\n\t\t\t0x10 0xc1000000 /* POWER_ON_STRAP */\n\t\t\t0x7c 0x0000007e /* PORT0_STATUS */\n\t\t\t0x94 0x0000007e /* PORT6_STATUS */\n\t\t\t>;\n\t};\n};\n\n&pinmux {\n\tpmx_led_wan_lan: pinmux_led_wan_lan {\n\t\tpinctrl-single,bits = <0x10 0x2c2d0000 0xffff0000>,\n\t\t\t <0x14 0x292a2b 0xffffff>;\n\t};\n};\n\n&builtin_switch {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pmx_led_wan_lan>;\n\n\t/delete-property/qca,phy4-mii-enable;\n};\n\n&eth1 {\n\tstatus = \"okay\";\n\n\tnvmem-cells = <&macaddr_art_6>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tgmac-config {\n\t\tdevice = <&gmac>;\n\t\tswitch-phy-swap = <0>;\n\t\tswitch-only-mode = <1>;\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n\n\tath9k: wifi@0,0 {\n\t\tcompatible = \"pci168c,0030\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tqca,no-eeprom;\n\t\tieee80211-freq-limit = <4900000 5990000>;\n\t\t#gpio-cells = <2>;\n\t\tgpio-controller;\n\t};\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n};\n\n&usb {\n\tstatus = \"okay\";\n\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\n\thub_port1: port@1 {\n\t\treg = <1>;\n\t\t#trigger-source-cells = <0>;\n\t};\n};\n\n&usb_phy {\n\tstatus = \"okay\";\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n\n\tmacaddr_art_6: macaddr@6 {\n\t\treg = <0x6 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9344_comfast_cf-e120a-v3.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9344.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"comfast,cf-e120a-v3\", \"qca,ar9344\";\n\tmodel = \"COMFAST CF-E120A v3\";\n\n\taliases {\n\t\tled-boot = &led_rssihigh;\n\t\tled-failsafe = &led_rssihigh;\n\t\tled-upgrade = &led_rssihigh;\n\t\tlabel-mac-device = &eth0;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tpinctrl-names = \"default\";\n\t\tpinctrl-0 = <&led_rssimediumhigh_pin>;\n\n\t\twan {\n\t\t\tlabel = \"green:wan\";\n\t\t\tgpios = <&gpio 3 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan {\n\t\t\tlabel = \"green:lan\";\n\t\t\tgpios = <&gpio 2 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan {\n\t\t\tlabel = \"green:wlan\";\n\t\t\tgpios = <&gpio 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\trssilow {\n\t\t\tlabel = \"red:rssilow\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\trssimediumlow {\n\t\t\tlabel = \"red:rssimediumlow\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\trssimediumhigh {\n\t\t\tlabel = \"green:rssimediumhigh\";\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_rssihigh: rssihigh {\n\t\t\tlabel = \"green:rssihigh\";\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n};\n\n&pinmux {\n\tled_rssimediumhigh_pin: pinmux_rssimediumhigh_pin {\n\t\tpinctrl-single,bits = <0x10 0x0 0xff>;\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tart: partition@10000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0x010000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x020000 0x7d0000>;\n\t\t\t};\n\n\t\t\tpartition@7f0000 {\n\t\t\t\tlabel = \"nvram\";\n\t\t\t\treg = <0x7f0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\tphy-handle = <&swphy0>;\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tgmac-config {\n\t\tdevice = <&gmac>;\n\t\tswitch-phy-swap = <1>;\n\t};\n};\n\n&eth1 {\n\tstatus = \"okay\";\n\tnvmem-cells = <&macaddr_art_6>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wmac {\n\tstatus = \"okay\";\n\tmtd-cal-data = <&art 0x1000>;\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n\n\tmacaddr_art_6: macaddr@6 {\n\t\treg = <0x6 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9344_compex_wpj344-16m.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9344.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"compex,wpj344-16m\", \"qca,ar9344\";\n\tmodel = \"Compex WPJ344 (16MB flash)\";\n\n\taliases {\n\t\tlabel-mac-device = &eth0;\n\t\tled-boot = &led_status;\n\t\tled-failsafe = &led_status;\n\t\tled-running = &led_status;\n\t\tled-upgrade = &led_status;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_status: status {\n\t\t\tlabel = \"green:status\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tsig1 {\n\t\t\tlabel = \"red:sig1\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tsig2 {\n\t\t\tlabel = \"yellow:sig2\";\n\t\t\tgpios = <&gpio 20 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tsig3 {\n\t\t\tlabel = \"green:sig3\";\n\t\t\tgpios = <&gpio 21 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tsig4 {\n\t\t\tlabel = \"green:sig4\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n};\n\n&ref {\n\tclock-frequency = <40000000>;\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tuboot: partition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x030000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x030000 0xfc0000>;\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t};\n\n\t\t\tart: partition@ff0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0xff0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&usb {\n\tstatus = \"okay\";\n};\n\n&usb_phy {\n\tstatus = \"okay\";\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy-mask = <0>;\n\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t\tphy-mode = \"rgmii\";\n\n\t\tqca,ar8327-initvals = <\n\t\t\t0x04 0x07600000 /* PORT0 PAD MODE CTRL */\n\t\t\t0x10 0x80000080 /* POWER_ON_STRAP */\n\t\t\t0x50 0x00000000 /* LED_CTRL0 */\n\t\t\t0x54 0xc737c737 /* LED_CTRL1 */\n\t\t\t0x58 0x00000000 /* LED_CTRL2 */\n\t\t\t0x5c 0x00c30c00 /* LED_CTRL3 */\n\t\t\t0x7c 0x0000007e /* PORT0_STATUS */\n\t\t\t>;\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tpll-data = <0x06000000 0x00000101 0x00001616>;\n\n\tnvmem-cells = <&macaddr_uboot_2e010>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tphy-mode = \"rgmii\";\n\tphy-handle = <&phy0>;\n};\n\n&uboot {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_uboot_2e010: macaddr@2e010 {\n\t\treg = <0x2e010 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9344_devolo_dlan-pro-1200plus-ac.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9344_devolo_dlan_wifi.dtsi\"\n\n/ {\n\tmodel = \"Devolo dLAN pro 1200+ WiFi ac\";\n\tcompatible = \"devolo,dlan-pro-1200plus-ac\", \"qca,ar9344\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9344_devolo_dlan_wifi.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9344.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\taliases {\n\t\tled-boot = &led_dlan_red;\n\t\tled-failsafe = &led_dlan_red;\n\t\tled-running = &led_dlan_white;\n\t\tled-upgrade = &led_dlan_red;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twlan {\n\t\t\tlabel = \"white:wlan\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\n\t\tled_dlan_white: dlan_white {\n\t\t\tlabel = \"white:dlan\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_dlan_red: dlan_red {\n\t\t\tlabel = \"red:dlan\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_HIGH>;\n\t\t\tpanic-indicator;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"Reset button\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\twifi {\n\t\t\tlabel = \"WIFI button\";\n\t\t\tlinux,code = <KEY_RFKILL>;\n\t\t\tgpios = <&gpio 20 GPIO_ACTIVE_HIGH>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\tdlan {\n\t\t\tlabel = \"DLAN button\";\n\t\t\tlinux,code = <BTN_0>;\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n};\n\n&gpio {\n\twlan_power {\n\t\tgpio-hog;\n\t\tline-name = \"WLAN power\";\n\t\tgpios = <&gpio 21 GPIO_ACTIVE_HIGH>;\n\t\toutput-high;\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tuboot: partition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x40000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tlabel = \"Config1\";\n\t\t\t\treg = <0x50000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@60000 {\n\t\t\t\tlabel = \"Config2\";\n\t\t\t\treg = <0x60000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@70000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x70000 0xf80000>;\n\t\t\t};\n\n\t\t\tart: partition@ff0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0xff0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&ref {\n\tclock-frequency = <40000000>;\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tpll-data = <0x02000000 0x00000101 0x00001616>;\n\n\tnvmem-cells = <&macaddr_art_1002>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <2>;\n\n\tphy-mode = \"rgmii\";\n\tphy-handle = <&phy0>;\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n};\n\n&pcie {\n\tstatus = \"okay\";\n\n\twifi@0,0 {\n\t\tcompatible = \"qcom,ath10k\";\n\t\treg = <0 0 0 0 0>;\n\t};\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t\tphy-mode = \"rgmii\";\n\n\t\tqca,ar8327-initvals = <\n\t\t\t/* PORT0: RGMII, MAC0/6 exchange, tx_delay 01, No rx_delay */\n\t\t\t0x04 0x06400000\n\t\t\t0x08 0x00000000 /* PORT5 PAD MODE CTRL */\n\t\t\t0x0c 0x00000000 /* PORT6 PAD MODE CTRL */\n\t\t\t0x7c 0x0000007e /* PORT0_STATUS */\n\t\t>;\n\t};\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_1002: macaddr@1002 {\n\t\treg = <0x1002 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9344_devolo_magic-2-wifi.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9344_devolo_dlan_wifi.dtsi\"\n\n/ {\n\tmodel = \"Devolo Magic 2 Wifi\";\n\tcompatible = \"devolo,magic-2-wifi\", \"qca,ar9344\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9344_dlink_dir-825-c1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9344_dlink_dir-8x5.dtsi\"\n\n/ {\n\tmodel = \"D-LINK DIR-825 C1\";\n\tcompatible = \"dlink,dir-825-c1\", \"qca,ar9344\";\n\n\taliases {\n\t\tled-boot = &led_power_orange;\n\t\tled-failsafe = &led_power_orange;\n\t\tled-running = &led_power_blue;\n\t\tled-upgrade = &led_power_orange;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tpinctrl-names = \"default\";\n\t\tpinctrl-0 = <&enable_gpio_11>;\n\n\t\tled_power_blue: power_blue {\n\t\t\tlabel = \"blue:power\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tusb {\n\t\t\tlabel = \"blue:usb\";\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t\ttrigger-sources = <&hub_port1>;\n\t\t};\n\n\t\twan_blue {\n\t\t\tlabel = \"blue:wan\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan2g {\n\t\t\tlabel = \"blue:wlan2g\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"blue:wps\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_power_orange: power_orange {\n\t\t\tlabel = \"orange:power\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twan_orange {\n\t\t\tlabel = \"orange:wan\";\n\t\t\tgpios = <&gpio 19 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tleds-ath9k {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twlan5g {\n\t\t\tlabel = \"blue:wlan5g\";\n\t\t\tgpios = <&ath9k 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\t};\n};\n\n&pinmux {\n\tenable_gpio_11: pinmux_enable_gpio_11 {\n\t\tpinctrl-single,bits = <0x8 0x0 0xff000000>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9344_dlink_dir-835-a1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9344_dlink_dir-8x5.dtsi\"\n\n/ {\n\tmodel = \"D-LINK DIR-835 A1\";\n\tcompatible = \"dlink,dir-835-a1\", \"qca,ar9344\";\n\n\taliases {\n\t\tled-boot = &led_power_orange;\n\t\tled-failsafe = &led_power_orange;\n\t\tled-running = &led_power_green;\n\t\tled-upgrade = &led_power_orange;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power_green: power_green {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twan_green {\n\t\t\tlabel = \"green:wan\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_power_orange: power_orange {\n\t\t\tlabel = \"orange:power\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twan_orange {\n\t\t\tlabel = \"orange:wan\";\n\t\t\tgpios = <&gpio 19 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9344_dlink_dir-8x5.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9344.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\twps {\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\t/* default for ar934x, except for 1000M */\n\tpll-data = <0x06000000 0x00000101 0x00001616>;\n\n\tphy-mode = \"rgmii\";\n\tphy-handle = <&phy0>;\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy-mask = <0>;\n\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t\tqca,ar8327-initvals = <\n\t\t\t/* GPL code drop (bsp.h & athrs17_phy.c) */\n\t\t\t0x10 0xc1000000 /* PWS_REG_VALUE */\n\t\t\t0x04 0x07600000 /* PORT0 PAD Mode */\n\t\t\t0x0c 0x01000000 /* PORT6 PAD Mode */\n\t\t\t0x7c 0x0000007e /* PORT0_STATUS */\n\t\t\t0x94 0x0000007e /* PORT6_STATUS */\n\t\t>;\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n\n\tath9k: wifi@0,0 {\n\t\tcompatible = \"pci168c,0030\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tqca,no-eeprom;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t};\n};\n\n&ref {\n\tclock-frequency = <40000000>;\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"uboot\";\n\t\t\t\treg = <0x000000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@10000 {\n\t\t\t\tlabel = \"nvram\";\n\t\t\t\treg = <0x010000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x020000 0xF90000>;\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t};\n\n\t\t\tpartition@fb0000 {\n\t\t\t\tlabel = \"lang\";\n\t\t\t\treg = <0xfb0000 0x030000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@fe0000 {\n\t\t\t\tlabel = \"mac\";\n\t\t\t\treg = <0xfe0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@ff0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0xff0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&usb {\n\tstatus = \"okay\";\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\n\thub_port1: port@1 {\n\t\treg = <1>;\n\t\t#trigger-source-cells = <0>;\n\t};\n};\n\n&usb_phy {\n\tstatus = \"okay\";\n};\n\n&wmac {\n\tstatus = \"okay\";\n\tqca,no-eeprom;\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9344_embeddedwireless_balin.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9344.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/leds/common.h>\n\n/ {\n\tmodel = \"Embedded Wireless Balin\";\n\tcompatible = \"embeddedwireless,balin\", \"qca,ar9344\";\n\n\tchosen {\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\taliases {\n\t\tled-boot = &led_system;\n\t\tled-failsafe = &led_system;\n\t\tled-running = &led_system;\n\t\tled-upgrade = &led_system;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_system: led-0 {\n\t\t\tlabel = \"green:system\";\n\t\t\tcolor = <LED_COLOR_ID_GREEN>;\n\t\t\tfunction = LED_FUNCTION_POWER;\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_HIGH>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n};\n\n&ref {\n\tclock-frequency = <40000000>;\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <50000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x040000 0x010000>;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x050000 0xfa0000>;\n\t\t\t};\n\n\t\t\tpartition@ff0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0xff0000 0x010000>;\n\t\t\t\tread-only;\n\n\t\t\t\tcompatible = \"nvmem-cells\";\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\n\t\t\t\tcalibration_art_1000: calibration_data@1000 {\n\t\t\t\t\treg = <0x1000 0x440>;\n\t\t\t\t};\n\n\t\t\t\tmacaddr_art_1002: macaddr@1002 {\n\t\t\t\t\treg = <0x1002 0x6>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t};\n};\n\n&builtin_switch {\n\t/delete-property/qca,phy4-mii-enable;\n};\n\n&eth1 {\n\tstatus = \"okay\";\n\n\tnvmem-cells = <&macaddr_art_1002>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment-byte = <3>;\n\tmac-address-increment = <0x40>;\n\n\tgmac-config {\n\t\tdevice = <&gmac>;\n\t\tswitch-phy-swap = <0>;\n\t\tswitch-only-mode = <1>;\n\t};\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tnvmem-cells = <&macaddr_art_1002>, <&calibration_art_1000>;\n\tnvmem-cell-names = \"mac-address\", \"calibration\";\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9344_engenius_eap600.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9344_engenius_exx600.dtsi\"\n\n/ {\n\tmodel = \"EnGenius EAP600\";\n\tcompatible = \"engenius,eap600\", \"qca,ar9344\";\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"amber:power\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"blue:wps\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twifi5g {\n\t\t\tlabel = \"green:wifi5g\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\t};\n};\n\n&eth0 {\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <(-2)>;\n};\n\n&pcie {\n\twifi@0,0,0 {\n\t\tnvmem-cells = <&macaddr_art_0>;\n\t\tnvmem-cell-names = \"mac-address\";\n\t};\n};\n\n&wmac {\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <(-1)>;\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9344_engenius_ecb600.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9344_engenius_exx600.dtsi\"\n\n/ {\n\tmodel = \"EnGenius ECB600\";\n\tcompatible = \"engenius,ecb600\", \"qca,ar9344\";\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"amber:power\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\twifi5g {\n\t\t\tlabel = \"blue:wifi5g\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\t};\n};\n\n&eth0 {\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&pcie {\n\twifi@0,0,0 {\n\t\tnvmem-cells = <&macaddr_art_0>;\n\t\tnvmem-cell-names = \"mac-address\";\n\t\tmac-address-increment = <(-2)>;\n\t};\n};\n\n&wmac {\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <(-1)>;\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9344_engenius_exx600.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9344.dtsi\"\n#include \"ar934x_senao_loader.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\taliases {\n\t\tlabel-mac-device = &eth0;\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tath9k-leds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twifi2g {\n\t\t\tlabel = \"blue:wifi2g\";\n\t\t\tgpios = <&ath9k 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\t};\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t\teee-broken-100tx;\n\t\teee-broken-1000t;\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii-id\";\n\n\tpll-data = <0x02000000 0x00000101 0x00001313>;\n\n\tgmac-config {\n\t\tdevice = <&gmac>;\n\t\trgmii-gmac0 = <1>;\n\t\trxdv-delay = <3>;\n\t\trxd-delay = <3>;\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n\n\tath9k: wifi@0,0,0 {\n\t\tcompatible = \"pci168c,0030\";\n\t\treg = <0x0 0 0 0 0>;\n\t\tieee80211-freq-limit = <2402000 2482000>;\n\t\tqca,no-eeprom;\n\t\t#gpio-cells = <2>;\n\t\tgpio-controller;\n\t};\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tieee80211-freq-limit = <4900000 5990000>;\n\n\tmtd-cal-data = <&art 0x1000>;\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9344_enterasys_ws-ap3705i.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9344.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"enterasys,ws-ap3705i\", \"qca,ar9344\";\n\tmodel = \"Enterasys WS-AP3705i\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200n8\";\n\t};\n\n\taliases {\n\t\tled-boot = &led_power_green;\n\t\tled-failsafe = &led_power_red;\n\t\tled-running = &led_power_green;\n\t\tled-upgrade = &led_power_red;\n\t\tlabel-mac-device = &eth0;\n\t};\n\n\tmtd-concat {\n\t\tcompatible = \"mtd-concat\";\n\t\tdevices = <&fwconcat0 &fwconcat1>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x0 0x1dd0000>;\n\t\t\t};\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tpinctrl-names = \"default\";\n\t\tpinctrl-0 = <&enable_gpio_11 &enable_gpio_16>;\n\n\t\tled_power_green: power_green {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_power_red: power_red {\n\t\t\tlabel = \"red:power\";\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan_blue {\n\t\t\tlabel = \"blue:lan\";\n\t\t\tgpios = <&gpio 19 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tlan_green {\n\t\t\tlabel = \"green:lan\";\n\t\t\tgpios = <&gpio 20 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tradio2 {\n\t\t\tlabel = \"green:radio2\";\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\t};\n\n\tath9k-leds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tradio1 {\n\t\t\tlabel = \"green:radio1\";\n\t\t\tgpios = <&ath9k 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"Reset button\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&ref {\n\tclock-frequency = <40000000>;\n};\n\n&pinmux {\n\tenable_gpio_16: pinmux_enable_gpio_16 {\n\t\tpinctrl-single,bits = <0x10 0x0 0x000000ff>;\n\t};\n\n\tenable_gpio_11: pinmux_enable_gpio_11 {\n\t\tpinctrl-single,bits = <0x8 0x0 0xff000000>;\n\t};\n};\n\n&wmac {\n\tstatus = \"okay\";\n\tqca,no-eeprom;\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot-bak\";\n\t\t\t\treg = <0x0 0x80000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@80000 {\n\t\t\t\tlabel = \"u-boot-env0\";\n\t\t\t\treg = <0x80000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@90000 {\n\t\t\t\tlabel = \"u-boot-env1\";\n\t\t\t\treg = <0x90000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@a0000 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0xa0000 0x80000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@120000 {\n\t\t\t\tlabel = \"calibrate\";\n\t\t\t\treg = <0x120000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@130000 {\n\t\t\t\tlabel = \"nvram\";\n\t\t\t\treg = <0x130000 0x100000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfwconcat0: partition@230000 {\n\t\t\t\tlabel = \"fwconcat0\";\n\t\t\t\treg = <0x230000 0xdd0000>;\n\t\t\t};\n\t\t};\n\t};\n\n\tflash@1 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <1>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tfwconcat1: partition@0 {\n\t\t\t\tlabel = \"fwconcat1\";\n\t\t\t\treg = <0x0 0x1000000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n\n\tath9k: wifi@0,0 {\n\t\tcompatible = \"pci168c,0033\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tqca,no-eeprom;\n\t\t#gpio-cells = <2>;\n\t\tgpio-controller;\n\t};\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tpll-data = <0x1e000000 0x08000101 0x08001313>;\n\n\tphy-mode = \"rgmii\";\n\tphy-handle = <&phy0>;\n\n\tgmac-config {\n\t\tdevice = <&gmac>;\n\t\trgmii-gmac0 = <1>;\n\t\trxd-delay = <0>;\n\t\trxdv-delay = <0>;\n\t\ttxen-delay = <0>;\n\t\ttxd-delay = <0>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9344_mercury_mw4530r-v1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9344_tplink_tl-wdr4300.dtsi\"\n\n/ {\n\tmodel = \"Mercury MW4530R v1\";\n\tcompatible = \"mercury,mw4530r-v1\", \"qca,ar9344\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9344_mikrotik_routerboard-16m-nor.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9344.dtsi\"\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <40000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"RouterBoot\";\n\t\t\t\treg = <0x0 0x20000>;\n\t\t\t\tread-only;\n\t\t\t\tcompatible = \"mikrotik,routerboot-partitions\";\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\n\t\t\t\tpartition@0 {\n\t\t\t\t\tlabel = \"bootloader1\";\n\t\t\t\t\treg = <0x0 0x0>;\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\thard_config {\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\tbios {\n\t\t\t\t\tsize = <0x1000>;\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\tpartition@10000 {\n\t\t\t\t\tlabel = \"bootloader2\";\n\t\t\t\t\treg = <0x10000 0x0>;\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\tsoft_config {\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tcompatible = \"mikrotik,minor\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x020000 0xfe0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tqca,no-eeprom;\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9344_mikrotik_routerboard-lhg-5nd.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9344_mikrotik_routerboard-16m-nor.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"mikrotik,routerboard-lhg-5nd\", \"qca,ar9344\";\n\tmodel = \"MikroTik RouterBOARD LHG 5nD\";\n\n\taliases {\n\t\tled-boot = &led_user;\n\t\tled-failsafe = &led_user;\n\t\tled-running = &led_user;\n\t\tled-upgrade = &led_user;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tpower {\n\t\t\tlabel = \"blue:power\";\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\trssilow {\n\t\t\tlabel = \"green:rssilow\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\trssimediumlow {\n\t\t\tlabel = \"green:rssimediumlow\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\trssimedium {\n\t\t\tlabel = \"green:rssimedium\";\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\trssimediumhigh {\n\t\t\tlabel = \"green:rssimediumhigh\";\n\t\t\tgpios = <&gpio 21 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\trssihigh {\n\t\t\tlabel = \"green:rssihigh\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_user: user {\n\t\t\tlabel = \"white:user\";\n\t\t\tgpios = <&gpio 20 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan {\n\t\t\tlabel = \"green:lan\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tphy-handle = <&swphy0>;\n\n\tgmac-config {\n\t\tdevice = <&gmac>;\n\t\tswitch-phy-swap = <1>;\n\t};\n};\n\n&eth1 {\n\tstatus = \"okay\";\n\n\tcompatible = \"syscon\", \"simple-mfd\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9344_mikrotik_routerboard-sxt-5n.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9344.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"mikrotik,routerboard-sxt-5n\", \"qca,ar9344\";\n\tmodel = \"MikroTik SXT 5N platform\";\n\n\taliases {\n\t\tled-boot = &led_user;\n\t\tled-failsafe = &led_user;\n\t\tled-running = &led_user;\n\t\tled-upgrade = &led_user;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tpower {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\trssilow {\n\t\t\tlabel = \"green:rssilow\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\trssimediumlow {\n\t\t\tlabel = \"green:rssimediumlow\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\trssimedium {\n\t\t\tlabel = \"green:rssimedium\";\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\trssimediumhigh {\n\t\t\tlabel = \"green:rssimediumhigh\";\n\t\t\tgpios = <&gpio 21 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\trssihigh {\n\t\t\tlabel = \"green:rssihigh\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_user: user {\n\t\t\tlabel = \"green:user\";\n\t\t\tgpios = <&gpio 3 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tgpio-export {\n\t\tcompatible = \"gpio-export\";\n\n\t\tgpio_nand_power {\n\t\t\tgpio-export,name = \"sxt5n:power:nand\";\n\t\t\tgpio-export,output = <0>;\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tbeeper {\n\t\tcompatible = \"gpio-beeper\";\n\t\tgpios = <&gpio 19 GPIO_ACTIVE_HIGH>;\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <40000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"RouterBoot\";\n\t\t\t\treg = <0x0 0x20000>;\n\t\t\t\tcompatible = \"mikrotik,routerboot-partitions\";\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\n\t\t\t\tpartition@0 {\n\t\t\t\t\tlabel = \"bootloader1\";\n\t\t\t\t\treg = <0x0 0x0>;\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\thard_config {\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\tbios {\n\t\t\t\t\tsize = <0x1000>;\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\tsoft_config {\n\t\t\t\t};\n\n\t\t\t\tpartition@10000 {\n\t\t\t\t\tlabel = \"bootloader2\";\n\t\t\t\t\treg = <0x10000 0x10000>;\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t};\n};\n\n&nand {\n\tstatus = \"okay\";\n\n\tnand-ecc-mode = \"soft\";\n\tqca,nand-swap-dma;\n\tqca,nand-scan-fixup;\n\n\tpartitions {\n\t\tcompatible = \"fixed-partitions\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"booter\";\n\t\t\treg = <0x0000000 0x0040000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@40000 {\n\t\t\tlabel = \"kernel\";\n\t\t\treg = <0x0040000 0x03c0000>;\n\t\t};\n\n\t\tpartition@400000 {\n\t\t\tlabel = \"ubi\";\n\t\t\treg = <0x0400000 0x7c00000>;\n\t\t};\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tphy-handle = <&swphy0>;\n\n\tgmac-config {\n\t\tdevice = <&gmac>;\n\t\tswitch-phy-swap = <1>;\n\t};\n};\n\n&eth1 {\n\tstatus = \"okay\";\n\n\tcompatible = \"syscon\", \"simple-mfd\";\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tqca,no-eeprom;\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9344_mikrotik_routerboard-sxt-5nd-r2.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9344_mikrotik_routerboard-sxt-5n.dtsi\"\n\n/ {\n\tcompatible = \"mikrotik,routerboard-sxt-5nd-r2\", \"qca,ar9344\";\n\tmodel = \"MikroTik RouterBOARD SXT 5nD r2 (SXT Lite5)\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9344_netgear_r6100.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9344.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"Netgear R6100\";\n\tcompatible = \"netgear,r6100\", \"qca,ar9344\";\n\n\taliases {\n\t\tlabel-mac-device = &eth0;\n\t\tled-boot = &led_power_green;\n\t\tled-failsafe = &led_power_amber;\n\t\tled-running = &led_power_green;\n\t\tled-upgrade = &led_power_green;\n\t};\n\n\tgpio-export {\n\t\tcompatible = \"gpio-export\";\n\t\t#size-cells = <0>;\n\n\t\tusb-power {\n\t\t\tgpio-export,name = \"usb-power\";\n\t\t\tgpio-export,output = <1>;\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\trfkill {\n\t\t\tlabel = \"rfkill\";\n\t\t\tlinux,code = <KEY_RFKILL>;\n\t\t\tgpios = <&gpio 1 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tgpios = <&gpio 3 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power_amber: power_amber {\n\t\t\tlabel = \"amber:power\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_power_green: power_green {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tusb {\n\t\t\tlabel = \"blue:usb\";\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\t\ttrigger-sources = <&hub_port>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\n\t\twan_amber {\n\t\t\tlabel = \"amber:wan\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twan_green {\n\t\t\tlabel = \"green:wan\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan {\n\t\t\tlabel = \"blue:wlan\";\n\t\t\tgpios = <&gpio 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tphy-handle = <&swphy0>;\n\n\tnvmem-cells = <&macaddr_caldata_6>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tgmac-config {\n\t\tdevice = <&gmac>;\n\t\tswitch-phy-swap = <1>;\n\t};\n};\n\n&eth1 {\n\tstatus = \"okay\";\n\n\tnvmem-cells = <&macaddr_caldata_0>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&nand {\n\tstatus = \"okay\";\n\n\tpartitions {\n\t\tcompatible = \"fixed-partitions\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"u-boot\";\n\t\t\treg = <0x0000000 0x0020000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tcaldata: partition@20000 {\n\t\t\tlabel = \"caldata\";\n\t\t\treg = <0x0020000 0x0040000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@60000 {\n\t\t\tlabel = \"caldata-backup\";\n\t\t\treg = <0x0060000 0x0040000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@a0000 {\n\t\t\tlabel = \"config\";\n\t\t\treg = <0x00a0000 0x0080000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@120000 {\n\t\t\tlabel = \"pot\";\n\t\t\treg = <0x0120000 0x0080000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@1a0000 {\n\t\t\tlabel = \"kernel\";\n\t\t\treg = <0x01a0000 0x0400000>;\n\t\t};\n\n\t\tpartition@5a0000 {\n\t\t\tlabel = \"ubi\";\n\t\t\treg = <0x05a0000 0x7560000>;\n\t\t};\n\n\t\tpartition@7b00000 {\n\t\t\tlabel = \"language\";\n\t\t\treg = <0x7b00000 0x0200000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@7d00000 {\n\t\t\tlabel = \"traffic_meter\";\n\t\t\treg = <0x7d00000 0x0300000>;\n\t\t\tread-only;\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n\n\twifi@0,0,0 {\n\t\tcompatible = \"qcom,ath10k\";\n\t\treg = <0x0000 0 0 0 0>;\n\n\t\tnvmem-cells = <&macaddr_caldata_c>;\n\t\tnvmem-cell-names = \"mac-address\";\n\t};\n};\n\n&ref {\n\tclock-frequency = <40000000>;\n};\n\n&usb {\n\tstatus = \"okay\";\n\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\n\thub_port: port@1 {\n\t\treg = <1>;\n\t\t#trigger-source-cells = <0>;\n\t};\n};\n\n&usb_phy {\n\tstatus = \"okay\";\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&caldata 0x1000>;\n};\n\n&caldata {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_caldata_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n\n\tmacaddr_caldata_6: macaddr@6 {\n\t\treg = <0x6 0x6>;\n\t};\n\n\tmacaddr_caldata_c: macaddr@c {\n\t\treg = <0xc 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9344_netgear_wndr.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9344.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/mtd/partitions/uimage.h>\n\n/ {\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200n8\";\n\t};\n\n\taliases {\n\t\tled-boot = &led_power_amber;\n\t\tled-failsafe = &led_power_amber;\n\t\tled-running = &led_power_green;\n\t\tled-upgrade = &led_power_amber;\n\t\tlabel-mac-device = &eth0;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 21 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\trfkill {\n\t\t\tlabel = \"rfkill\";\n\t\t\tlinux,code = <KEY_RFKILL>;\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tleds: leds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tpinctrl-names = \"default\";\n\t\tpinctrl-0 = <&enable_gpio_11>;\n\n\t\tled_power_green: power_green {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_power_amber: power_amber {\n\t\t\tlabel = \"amber:power\";\n\t\t\tgpios = <&gpio 2 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"keep\";\n\t\t};\n\n\t\twlan2g_green {\n\t\t\tlabel = \"green:wlan2g\";\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\twlan5g_blue {\n\t\t\tlabel = \"blue:wlan5g\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\n\t\twps_green {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twps_amber {\n\t\t\tlabel = \"amber:wps\";\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tubi-concat {\n\t\tcompatible = \"mtd-concat\";\n\t\tdevices = <&ubiconcat0 &ubiconcat1>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tubi@ac0000 {\n\t\t\t\tlabel = \"ubi\";\n\t\t\t\treg = <0x0 0x7500000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pinmux {\n\tenable_gpio_11: pinmux_enable_gpio_11 {\n\t\tpinctrl-single,bits = <0x8 0x0 0xff000000>;\n\t};\n};\n\n&nand {\n\tstatus = \"okay\";\n\n\tpartitions {\n\t\tcompatible = \"fixed-partitions\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"u-boot\";\n\t\t\treg = <0x0 0x40000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@40000 {\n\t\t\tlabel = \"u-boot-env\";\n\t\t\treg = <0x40000 0x40000>;\n\t\t};\n\n\t\tcaldata: partition@80000 {\n\t\t\tlabel = \"caldata\";\n\t\t\treg = <0x80000 0x40000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@c0000 {\n\t\t\tlabel = \"pot\";\n\t\t\treg = <0xc0000 0x80000>;\n\t\t};\n\n\t\tpartition@140000 {\n\t\t\tlabel = \"language\";\n\t\t\treg = <0x140000 0x200000>;\n\t\t};\n\n\t\tpartition@340000 {\n\t\t\tlabel = \"config\";\n\t\t\treg = <0x340000 0x80000>;\n\t\t};\n\n\t\tpartition@3c0000 {\n\t\t\tlabel = \"traffic_meter\";\n\t\t\treg = <0x3c0000 0x300000>;\n\t\t};\n\n\t\tkernel@6c0000 {\n\t\t\tlabel = \"kernel\";\n\t\t\treg = <0x6c0000 0x400000>;\n\t\t};\n\n\t\tubiconcat0: partition@ac0000 {\n\t\t\tlabel = \"ubiconcat0\";\n\t\t\treg = <0xac0000 0x1500000>;\n\t\t};\n\n\t\tpartition@6c0000 {\n\t\t\tlabel = \"firmware\";\n\t\t\treg = <0x6c0000 0x1900000>;\n\t\t\tcompatible = \"openwrt,uimage\", \"denx,uimage\";\n\t\t\topenwrt,ih-magic = <0x33373033>;\n\t\t\topenwrt,ih-type = <IH_TYPE_FILESYSTEM>;\n\t\t};\n\n\t\tpartition@1fc0000 {\n\t\t\tlabel = \"caldata_backup\";\n\t\t\treg = <0x1fc0000 0x40000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tubiconcat1: partition@2000000 {\n\t\t\tlabel = \"ubiconcat1\";\n\t\t\treg = <0x2000000 0x6000000>;\n\t\t};\n\t};\n};\n\n&ref {\n\tclock-frequency = <40000000>;\n};\n\n&builtin_switch {\n\tresets = <&rst 8>, <&rst 12>;\n\treset-names = \"switch\", \"switch-analog\";\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy-mask = <0>;\n\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t\tphy-mode = \"rgmii\";\n\t\tqca,mib-poll-interval = <500>;\n\n\t\tqca,ar8327-initvals = <\n\t\t\t0x04 0x07600000\n\t\t\t0x0c 0x01000000\n\t\t\t0x10 0xc1000000\n\t\t\t0x50 0xcc35cc35\n\t\t\t0x54 0xcb37cb37\n\t\t\t0x58 0x00000000\n\t\t\t0x5c 0x00f3cf00\n\t\t\t0x7c 0x0000007e\n\t\t\t0x94 0x0000007e\n\t\t\t>;\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\t/* default for ar934x, except for 1000M */\n\tpll-data = <0x06000000 0x00000101 0x00001616>;\n\n\tnvmem-cells = <&macaddr_caldata_0>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tphy-mode = \"rgmii\";\n\tphy-handle = <&phy0>;\n};\n\n&gpio {\n\tlna0 {\n\t\tgpio-hog;\n\t\tline-name = \"netgear:ext:lna0\";\n\t\tgpios = <18 GPIO_ACTIVE_HIGH>;\n\t\toutput-high;\n\t};\n\n\tlna1 {\n\t\tgpio-hog;\n\t\tline-name = \"netgear:ext:lna1\";\n\t\tgpios = <19 GPIO_ACTIVE_HIGH>;\n\t\toutput-high;\n\t};\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tnvmem-cells = <&macaddr_caldata_0>;\n\tnvmem-cell-names = \"mac-address\";\n\tqca,no-eeprom;\n};\n\n&pcie {\n\tstatus = \"okay\";\n\n\tath9k: wifi@0,0 {\n\t\tcompatible = \"pci168c,0033\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tnvmem-cells = <&macaddr_caldata_c>;\n\t\tnvmem-cell-names = \"mac-address\";\n\t\tqca,no-eeprom;\n\t\t#gpio-cells = <2>;\n\t\tgpio-controller;\n\t};\n};\n\n&caldata {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_caldata_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n\n\tmacaddr_caldata_c: macaddr@c {\n\t\treg = <0xc 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9344_netgear_wndr3700-v4.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9344_netgear_wndr.dtsi\"\n#include \"ar9344_netgear_wndr_wan.dtsi\"\n#include \"ar9344_netgear_wndr_usb.dtsi\"\n\n/ {\n\tcompatible = \"netgear,wndr3700-v4\", \"qca,ar9344\";\n\tmodel = \"Netgear WNDR3700 v4\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9344_netgear_wndr4300.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9344_netgear_wndr.dtsi\"\n#include \"ar9344_netgear_wndr_wan.dtsi\"\n#include \"ar9344_netgear_wndr_usb.dtsi\"\n\n/ {\n\tcompatible = \"netgear,wndr4300\", \"qca,ar9344\";\n\tmodel = \"Netgear WNDR4300\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9344_netgear_wndr4300sw.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9344_netgear_wndr.dtsi\"\n#include \"ar9344_netgear_wndr_wan.dtsi\"\n#include \"ar9344_netgear_wndr_usb.dtsi\"\n\n/ {\n\tcompatible = \"netgear,wndr4300sw\", \"qca,ar9344\";\n\tmodel = \"Netgear WNDR4300SW\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9344_netgear_wndr4300tn.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9344_netgear_wndr.dtsi\"\n\n/ {\n\tcompatible = \"netgear,wndr4300tn\", \"qca,ar9344\";\n\tmodel = \"Netgear WNDR4300TN\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9344_netgear_wndr_usb.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n&leds {\n\tusb_green {\n\t\tlabel = \"green:usb\";\n\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\ttrigger-sources = <&hub_port>;\n\t\tlinux,default-trigger = \"usbport\";\n\t};\n};\n\n&ath9k {\n\tusb_power {\n\t\tgpio-hog;\n\t\tline-name = \"netgear:power:usb\";\n\t\tgpios = <0 GPIO_ACTIVE_HIGH>;\n\t\toutput-high;\n\t};\n};\n\n&usb_phy {\n\tstatus = \"okay\";\n};\n\n&usb {\n\tstatus = \"okay\";\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\n\thub_port: port@1 {\n\t\treg = <1>;\n\t\t#trigger-source-cells = <0>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9344_netgear_wndr_wan.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n&leds {\n\twan_green {\n\t\tlabel = \"green:wan\";\n\t\tgpios = <&gpio 1 GPIO_ACTIVE_LOW>;\n\t};\n\n\twan_amber {\n\t\tlabel = \"amber:wan\";\n\t\tgpios = <&gpio 3 GPIO_ACTIVE_LOW>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9344_ocedo_raccoon.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9344.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"OCEDO Raccoon\";\n\tcompatible = \"ocedo,raccoon\", \"qca,ar9344\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200n8\";\n\t};\n\n\taliases {\n\t\tled-boot = &led_system;\n\t\tled-failsafe = &led_system;\n\t\tled-running = &led_system;\n\t\tled-upgrade = &led_system;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tpower {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\twlan2g {\n\t\t\tlabel = \"yellow:wlan24\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\tled_system: system {\n\t\t\tlabel = \"blue:sys\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tath9k-leds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twlan5g {\n\t\t\tlabel = \"red:wlan5\";\n\t\t\tgpios = <&ath9k 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n};\n\n&ref {\n\tclock-frequency = <40000000>;\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <50000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tuboot: partition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x040000 0x010000>;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x050000 0x740000>;\n\t\t\t};\n\n\t\t\tpartition@790000 {\n\t\t\t\tlabel = \"vendor\";\n\t\t\t\treg = <0x790000 0x740000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@ed0000 {\n\t\t\t\tlabel = \"data\";\n\t\t\t\treg = <0xed0000 0x110000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@fe0000 {\n\t\t\t\tlabel = \"id\";\n\t\t\t\treg = <0xfe0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tart: partition@ff0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0xff0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n\n\tath9k: wifi@0,0 {\n\t\tcompatible = \"pci168c,0030\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tnvmem-cells = <&macaddr_art_c>;\n\t\tnvmem-cell-names = \"mac-address\";\n\t\tqca,no-eeprom;\n\t\t#gpio-cells = <2>;\n\t\tgpio-controller;\n\t};\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n\tnvmem-cells = <&macaddr_art_6>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy-mask = <0>;\n\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t\teee-broken-100tx;\n\t\teee-broken-1000t;\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tpll-data = <0x02000000 0x00000101 0x00001313>;\n\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tphy-mode = \"rgmii-id\";\n\tphy-handle = <&phy0>;\n\n\tgmac-config {\n\t\tdevice = <&gmac>;\n\t\trgmii-gmac0 = <1>;\n\t\trxdv-delay = <3>;\n\t\trxd-delay = <3>;\n\t\ttxen-delay = <0>;\n\t\ttxd-delay = <0>;\n\t};\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n\n\tmacaddr_art_6: macaddr@6 {\n\t\treg = <0x6 0x6>;\n\t};\n\n\tmacaddr_art_c: macaddr@c {\n\t\treg = <0xc 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9344_openmesh_mr600-v1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9344_openmesh_mr600.dtsi\"\n\n/ {\n\tcompatible = \"openmesh,mr600-v1\", \"qca,ar9344\";\n\tmodel = \"OpenMesh MR600 v1\";\n\n\taliases {\n\t\tled-boot = &led_power_orange;\n\t\tled-failsafe = &led_power_orange;\n\t\tled-running = &led_power_orange;\n\t\tled-upgrade = &led_power_orange;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twifi5g_green {\n\t\t\tlabel = \"green:wifi5g\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\twps_blue {\n\t\t\tlabel = \"blue:wps\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_power_orange: power_orange {\n\t\t\tlabel = \"orange:power\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\tleds-ath9k {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twifi2g {\n\t\t\tlabel = \"blue:wifi2g\";\n\t\t\tgpios = <&ath9k 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9344_openmesh_mr600-v2.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9344_openmesh_mr600.dtsi\"\n\n/ {\n\tcompatible = \"openmesh,mr600-v2\", \"qca,ar9344\";\n\tmodel = \"OpenMesh MR600 v2\";\n\n\taliases {\n\t\tled-boot = &led_power_blue;\n\t\tled-failsafe = &led_power_blue;\n\t\tled-running = &led_power_blue;\n\t\tled-upgrade = &led_power_blue;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twifi5g_red {\n\t\t\tlabel = \"red:wifi5g\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twps_blue {\n\t\t\tlabel = \"blue:wps\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_power_blue: power_blue {\n\t\t\tlabel = \"blue:power\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\twifi2g_green {\n\t\t\tlabel = \"green:wifi2g\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\n\t\twifi2g_yellow {\n\t\t\tlabel = \"yellow:wifi2g\";\n\t\t\tgpios = <&gpio 19 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twifi2g_red {\n\t\t\tlabel = \"red:wifi2g\";\n\t\t\tgpios = <&gpio 20 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twifi5g_green {\n\t\t\tlabel = \"green:wifi5g\";\n\t\t\tgpios = <&gpio 21 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\twifi5g_yellow {\n\t\t\tlabel = \"yellow:wifi5g\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\twatchdog {\n\t\tcompatible = \"linux,wdt-gpio\";\n\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\thw_algo = \"toggle\";\n\t\t/* hw_margin_ms is actually 300s but driver limits it to 60s */\n\t\thw_margin_ms = <60000>;\n\t\talways-running;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9344_openmesh_mr600.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9344.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tchosen {\n\t\t/delete-property/ bootargs;\n\t};\n\n\taliases {\n\t\tlabel-mac-device = &eth0;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&ref {\n\tclock-frequency = <40000000>;\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <40000000>;\n\n\t\t/* partitions are passed via bootloader */\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x040000 0x010000>;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tlabel = \"custom\";\n\t\t\t\treg = <0x050000 0x060000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@b0000 {\n\t\t\t\tlabel = \"inactive\";\n\t\t\t\treg = <0x0b0000 0x7a0000>;\n\t\t\t};\n\n\t\t\tpartition@850000 {\n\t\t\t\tlabel = \"inactive2\";\n\t\t\t\treg = <0x850000 0x7a0000>;\n\t\t\t};\n\n\t\t\tart: partition@ff0000 {\n\t\t\t\tlabel = \"ART\";\n\t\t\t\treg = <0xff0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy-mask = <0x1>;\n\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t\teee-broken-100tx;\n\t\teee-broken-1000t;\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tpll-data = <0x02000000 0x00000101 0x00001313>;\n\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tphy-mode = \"rgmii-id\";\n\tphy-handle = <&phy0>;\n\n\tgmac-config {\n\t\tdevice = <&gmac>;\n\t\trgmii-gmac0 = <1>;\n\t\trxdv-delay = <3>;\n\t\trxd-delay = <3>;\n\t};\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <1>;\n};\n\n&pcie {\n\tstatus = \"okay\";\n\n\tath9k: wifi@0,0 {\n\t\tcompatible = \"pci168c,0030\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tqca,no-eeprom;\n\t\tnvmem-cells = <&macaddr_art_0>;\n\t\tnvmem-cell-names = \"mac-address\";\n\t\tmac-address-increment = <8>;\n\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t};\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9344_openmesh_om5p-an.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9344.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"openmesh,om5p-an\", \"qca,ar9344\";\n\tmodel = \"OpenMesh OM5P-AN\";\n\n\tchosen {\n\t\t/delete-property/ bootargs;\n\t};\n\n\taliases {\n\t\tled-boot = &led_power_blue;\n\t\tled-failsafe = &led_power_blue;\n\t\tled-running = &led_power_blue;\n\t\tled-upgrade = &led_power_blue;\n\t\tlabel-mac-device = &eth0;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tpinctrl-names = \"default\";\n\t\tpinctrl-0 = <&led_lan_wan_blue_pin>;\n\n\t\tled_power_blue: power_blue {\n\t\t\tlabel = \"blue:power\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\twan_blue {\n\t\t\tlabel = \"blue:wan\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan_blue {\n\t\t\tlabel = \"blue:lan\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twifi_green {\n\t\t\tlabel = \"green:wifi\";\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\twifi_yellow {\n\t\t\tlabel = \"yellow:wifi\";\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twifi_red {\n\t\t\tlabel = \"red:wifi\";\n\t\t\tgpios = <&gpio 19 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\ti2c {\n\t\tcompatible = \"i2c-gpio\";\n\t\tgpios = <&gpio 21 GPIO_ACTIVE_HIGH /* sda */\n\t\t\t &gpio 20 GPIO_ACTIVE_HIGH /* scl */\n\t\t\t>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\ti2c-gpio,scl-open-drain;\n\t\ti2c-gpio,sda-open-drain;\n\n\t\ttmp423a@4c {\n\t\t\tcompatible = \"ti,tmp423\";\n\t\t\treg = <0x4c>;\n\t\t};\n\t};\n\n\twatchdog {\n\t\tcompatible = \"linux,wdt-gpio\";\n\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\thw_algo = \"toggle\";\n\t\t/* hw_margin_ms is actually 300s but driver limits it to 60s */\n\t\thw_margin_ms = <60000>;\n\t\talways-running;\n\t};\n};\n\n&ref {\n\tclock-frequency = <40000000>;\n};\n\n&pinmux {\n\tled_lan_wan_blue_pin: pinmux_lan_wan_blue_pin {\n\t\tpinctrl-single,bits = <0xc 0x0 0xffff0000>;\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <40000000>;\n\n\t\t/* partitions are passed via bootloader */\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x040000 0x010000>;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tlabel = \"custom\";\n\t\t\t\treg = <0x050000 0x060000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@b0000 {\n\t\t\t\tlabel = \"inactive\";\n\t\t\t\treg = <0x0b0000 0x7a0000>;\n\t\t\t};\n\n\t\t\tpartition@850000 {\n\t\t\t\tlabel = \"inactive2\";\n\t\t\t\treg = <0x850000 0x7a0000>;\n\t\t\t};\n\n\t\t\tart: partition@ff0000 {\n\t\t\t\tlabel = \"ART\";\n\t\t\t\treg = <0xff0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy-mask = <0x80>;\n\n\tphy7: ethernet-phy@7 {\n\t\treg = <7>;\n\t\teee-broken-100tx;\n\t\teee-broken-1000t;\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tpll-data = <0x02000000 0x00000101 0x00001313>;\n\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tphy-mode = \"rgmii-id\";\n\tphy-handle = <&phy7>;\n\n\tgmac-config {\n\t\tdevice = <&gmac>;\n\t\trgmii-gmac0 = <1>;\n\t\trxd-delay = <2>;\n\t\trxdv-delay = <2>;\n\t\tswitch-phy-swap = <1>;\n\t};\n};\n\n&eth1 {\n\tstatus = \"okay\";\n\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <1>;\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <2>;\n};\n\n&pcie {\n\tstatus = \"okay\";\n\n\twifi@0,0 {\n\t\tcompatible = \"pci168c,0030\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tqca,no-eeprom;\n\t\tnvmem-cells = <&macaddr_art_0>;\n\t\tnvmem-cell-names = \"mac-address\";\n\t\tmac-address-increment = <16>;\n\t};\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9344_openmesh_om5p.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9344.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"openmesh,om5p\", \"qca,ar9344\";\n\tmodel = \"OpenMesh OM5P\";\n\n\tchosen {\n\t\t/delete-property/ bootargs;\n\t};\n\n\taliases {\n\t\tled-boot = &led_power_blue;\n\t\tled-failsafe = &led_power_blue;\n\t\tled-running = &led_power_blue;\n\t\tled-upgrade = &led_power_blue;\n\t\tlabel-mac-device = &eth1;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tpinctrl-names = \"default\";\n\t\tpinctrl-0 = <&led_lan_wan_blue_pin>;\n\n\t\tled_power_blue: power_blue {\n\t\t\tlabel = \"blue:power\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\twan_blue {\n\t\t\tlabel = \"blue:wan\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan_blue {\n\t\t\tlabel = \"blue:lan\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twifi_green {\n\t\t\tlabel = \"green:wifi\";\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\twifi_yellow {\n\t\t\tlabel = \"yellow:wifi\";\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twifi_red {\n\t\t\tlabel = \"red:wifi\";\n\t\t\tgpios = <&gpio 19 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\twatchdog {\n\t\tcompatible = \"linux,wdt-gpio\";\n\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\thw_algo = \"toggle\";\n\t\t/* hw_margin_ms is actually 300s but driver limits it to 60s */\n\t\thw_margin_ms = <60000>;\n\t\talways-running;\n\t};\n};\n\n&ref {\n\tclock-frequency = <40000000>;\n};\n\n&pinmux {\n\tled_lan_wan_blue_pin: pinmux_lan_wan_blue_pin {\n\t\tpinctrl-single,bits = <0xc 0x0 0xffff0000>;\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <40000000>;\n\n\t\t/* partitions are passed via bootloader */\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x040000 0x010000>;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tlabel = \"custom\";\n\t\t\t\treg = <0x050000 0x060000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@b0000 {\n\t\t\t\tlabel = \"inactive\";\n\t\t\t\treg = <0x0b0000 0x7a0000>;\n\t\t\t};\n\n\t\t\tpartition@850000 {\n\t\t\t\tlabel = \"inactive2\";\n\t\t\t\treg = <0x850000 0x7a0000>;\n\t\t\t};\n\n\t\t\tart: partition@ff0000 {\n\t\t\t\tlabel = \"ART\";\n\t\t\t\treg = <0xff0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tphy-handle = <&swphy4>;\n\n\tnvmem-cells = <&macaddr_art_6>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&eth1 {\n\tstatus = \"okay\";\n\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n\n\tmacaddr_art_6: macaddr@6 {\n\t\treg = <0x6 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9344_pcs_cap324.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9344.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"PowerCloud Systems CAP324\";\n\tcompatible = \"pcs,cap324\", \"qca,ar9344\";\n\n\taliases {\n\t\tled-boot = &led_power_amber;\n\t\tled-failsafe = &led_power_amber;\n\t\tled-running = &led_power_green;\n\t\tled-upgrade = &led_power_amber;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\tpinctrl-names = \"default\";\n\t\tpinctrl-0 = <&jtag_disable_pins>;\n\n\t\treset {\n\t\t\tlabel = \"Reset button\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power_amber: power_amber {\n\t\t\tlabel = \"amber:power\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_power_green: power_green {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\twlan_amber {\n\t\t\tlabel = \"amber:wlan\";\n\t\t\tgpios = <&gpio 19 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\n\t\twlan_green {\n\t\t\tlabel = \"green:wlan\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\tlan_amber {\n\t\t\tlabel = \"amber:lan\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan_green {\n\t\t\tlabel = \"green:lan\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&ref {\n\tclock-frequency = <25000000>;\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tuboot: partition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x040000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x050000 0x0fa0000>;\n\t\t\t};\n\n\t\t\tart: partition@7f0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0xff0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n\n\tath9k: wifi@0,0 {\n\t\tcompatible = \"168c,0030\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tnvmem-cells = <&macaddr_art_0>;\n\t\tnvmem-cell-names = \"mac-address\";\n\t\tmac-address-increment = <(-2)>;\n\t\tmtd-cal-data = <&art 0x5000>;\n\t\tqca,no-eeprom;\n\t\tieee80211-freq-limit = <2402000 2482000>;\n\t\t#gpio-cells = <2>;\n\t\tgpio-controller;\n\t};\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tieee80211-freq-limit = <4900000 5990000>;\n\tmtd-cal-data = <&art 0x1000>;\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <(-1)>;\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy-mask = <0>;\n\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t\tphy-mode = \"rgmii\";\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\t/* default for ar934x, except for 1000M */\n\tpll-data = <0x06000000 0x00000101 0x00001616>;\n\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tphy-mode = \"rgmii\";\n\tphy-handle = <&phy0>;\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9344_pcs_cr5000.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9344.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"PowerCloud Systems CR5000\";\n\tcompatible = \"pcs,cr5000\", \"qca,ar9344\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\tpinctrl-names = \"default\";\n\t\tpinctrl-0 = <&jtag_disable_pins>;\n\n\t\treset {\n\t\t\tlabel = \"Reset button\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"WPS button\";\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"amber:power\";\n\t\t\tgpios = <&gpio 2 GPIO_ACTIVE_LOW>,\n\t\t\t\t<&gpio 4 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\twlan2g {\n\t\t\tlabel = \"blue:wlan\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\twps_white {\n\t\t\tlabel = \"white:wps\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&ref {\n\tclock-frequency = <25000000>;\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tuboot: partition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x040000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x050000 0x07a0000>;\n\t\t\t};\n\n\t\t\tart: partition@7f0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0x7f0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&usb {\n\tstatus = \"okay\";\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\n\thub_port1: port@1 {\n\t\treg = <1>;\n\t\t#trigger-source-cells = <0>;\n\t};\n};\n\n&usb_phy {\n\tstatus = \"okay\";\n};\n\n&pcie {\n\tstatus = \"okay\";\n\n\tath9k: wifi@0,0 {\n\t\tcompatible = \"pci168c,0030\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tnvmem-cells = <&macaddr_art_5002>;\n\t\tnvmem-cell-names = \"mac-address\";\n\t\t#gpio-cells = <2>;\n\t\tgpio-controller;\n\t};\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy-mask = <0>;\n\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t\tphy-mode = \"rgmii\";\n\t\tqca,ar8327-initvals = <\n\t\t\t0x04 0x07600000 /* PORT0 PAD MODE CTRL */\n\t\t\t0x10 0x81000080 /* POWER_ON_STRAP */\n\t\t\t0x50 0xcc35cc35 /* LED_CTRL0 */\n\t\t\t0x54 0xca35ca35 /* LED_CTRL1 */\n\t\t\t0x58 0xc935c935 /* LED_CTRL2 */\n\t\t\t0x5c 0x03ffff00 /* LED_CTRL3 */\n\t\t\t0x7c 0x0000007e /* PORT0_STATUS */\n\t\t>;\n\t};\n};\n\n&eth0 {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\tstatus = \"okay\";\n\n\t/* default for ar934x, except for 1000M */\n\tpll-data = <0x06000000 0x00000101 0x00001616>;\n\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tphy-mode = \"rgmii\";\n\tphy-handle = <&phy0>;\n\n\taliases {\n\t\tag0 = &eth1;\n\t};\n\n\tport@0 {\n\t\tcompatible = \"swconfig,port\";\n\t\treg = <0>;\n\t\tswconfig,segment = \"lan\";\n\t\tswconfig,portmap = <1 1>;\n\t};\n\n\tport@1 {\n\t\tcompatible = \"swconfig,port\";\n\t\treg = <1>;\n\t\tswconfig,segment = \"lan\";\n\t\tswconfig,portmap = <2 2>;\n\t};\n\n\tport@2 {\n\t\tcompatible = \"swconfig,port\";\n\t\treg = <2>;\n\t\tswconfig,segment = \"lan\";\n\t\tswconfig,portmap = <3 3>;\n\t};\n\n\tport@3 {\n\t\tcompatible = \"swconfig,port\";\n\t\treg = <3>;\n\t\tswconfig,segment = \"lan\";\n\t\tswconfig,portmap = <4 4>;\n\t};\n\n\tport@4 {\n\t\tcompatible = \"swconfig,port\";\n\t\treg = <4>;\n\t\tswconfig,segment = \"wan\";\n\t\tswconfig,portmap = <5 5>;\n\t};\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n\n\tmacaddr_art_5002: macaddr@5002 {\n\t\treg = <0x5002 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9344_qihoo_c301.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9344.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"Qihoo 360 C301\";\n\tcompatible = \"qihoo,c301\";\n\n\taliases {\n\t\tled-boot = &led_wlan_g;\n\t\tled-failsafe = &led_wlan_o;\n\t\tled-upgrade = &led_wlan_o;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tpinctrl-names = \"default\";\n\t\tpinctrl-0 = <&jtag_disable_pins>;\n\n\t\tled_wlan_g: wlan_g {\n\t\t\tlabel = \"green:wlan\";\n\t\t\tgpios = <&gpio 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_wlan_o: wlan_o {\n\t\t\tlabel = \"orange:wlan\";\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\treg_eth_led_vbus {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"eth_led_vbus\";\n\t\tregulator-min-microvolt = <3300000>;\n\t\tregulator-max-microvolt = <3300000>;\n\t\tregulator-always-on;\n\t\tgpio = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t};\n\n\tusb_vbus: reg_usb_vbus {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"usb_vbus\";\n\t\tregulator-min-microvolt = <5000000>;\n\t\tregulator-max-microvolt = <5000000>;\n\t\tenable-active-high;\n\t\tgpio = <&gpio 19 GPIO_ACTIVE_HIGH>;\n\t};\n};\n\n&pinmux {\n\tpmx_spi_cs1: pinmux_spi_cs1 {\n\t\tpinctrl-single,bits = <0xc 0x07 0xff>;\n\t};\n\n\tpmx_led_switch: pinmux_led_switch {\n\t\tpinctrl-single,bits = <0x0 0x2b2a2d00 0xffffff00>;\n\t};\n};\n\n&ref {\n\tclock-frequency = <40000000>;\n};\n\n&gpio {\n\tgpio_ext_lna0 {\n\t\tgpio-hog;\n\t\tgpios = <14 0>;\n\t\toutput-high;\n\t\tline-name = \"c301:ext:lna0\";\n\t};\n\n\tgpio_ext_lna1 {\n\t\tgpio-hog;\n\t\tgpios = <15 0>;\n\t\toutput-high;\n\t\tline-name = \"c301:ext:lna1\";\n\t};\n};\n\n&builtin_switch {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pmx_led_switch>;\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pmx_spi_cs1>;\n\n\tflash@0 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tuboot: partition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x40000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tlabel = \"devdata\";\n\t\t\t\treg = <0x50000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@60000 {\n\t\t\t\tlabel = \"devconf\";\n\t\t\t\treg = <0x60000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@70000 {\n\t\t\t\tcompatible = \"seama\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x70000 0xf60000>;\n\t\t\t};\n\n\t\t\tpartition@fd0000 {\n\t\t\t\tlabel = \"warm_start\";\n\t\t\t\treg = <0xfd0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@fe0000 {\n\t\t\t\tlabel = \"action_image_config\";\n\t\t\t\treg = <0xfe0000 0x10000>;\n\t\t\t};\n\n\t\t\tpartition@ff0000 {\n\t\t\t\tlabel = \"radiocfg\";\n\t\t\t\treg = <0xff0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n\n\tflash@1 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <1>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"firmware2\";\n\t\t\t\treg = <0x0 0xf00000>;\n\t\t\t};\n\n\t\t\tpartition@f00000 {\n\t\t\t\tlabel = \"privatedata\";\n\t\t\t\treg = <0xf00000 0x100000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&usb {\n\tstatus = \"okay\";\n};\n\n&usb_phy {\n\tstatus = \"okay\";\n\tphy-supply = <&usb_vbus>;\n};\n\n&pcie {\n\tstatus = \"okay\";\n\n\twifi@0,0 {\n\t\tcompatible = \"qcom,ath10k\";\n\t\treg = <0 0 0 0 0>;\n\t};\n};\n\n&wmac {\n\tstatus = \"okay\";\n\tqca,no-eeprom;\n};\n\n&eth1 {\n\tstatus = \"okay\";\n\tgmac-config {\n\t\tdevice = <&gmac>;\n\t\tswitch-phy-swap = <1>;\n\t\tswitch-only-mode = <1>;\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\tphy-handle = <&swphy0>;\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9344_qxwlan_e750a-v4-16m.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9344_qxwlan_e750x.dtsi\"\n\n/ {\n\tmodel = \"Qxwlan E750A v4 16M\";\n\tcompatible = \"qxwlan,e750a-v4-16m\", \"qca,ar9344\";\n};\n\n&leds {\n\tlan {\n\t\tlabel = \"green:lan\";\n\t\tgpios = <&gpio 19 GPIO_ACTIVE_LOW>;\n\t};\n\n\twan {\n\t\tlabel = \"green:wan\";\n\t\tgpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tphy-handle = <&swphy4>;\n\n\tnvmem-cells = <&macaddr_pridata_400>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <1>;\n};\n\n&eth1 {\n\tstatus = \"okay\";\n\n\tnvmem-cells = <&macaddr_pridata_400>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tgmac-config {\n\t\tdevice = <&gmac>;\n\t\tswitch-phy-swap = <0>;\n\t\tswitch-only-mode = <1>;\n\t};\n};\n\n&partitions {\n\tpartition@70000 {\n\t\tcompatible = \"denx,uimage\";\n\t\tlabel = \"firmware\";\n\t\treg = <0x070000 0xf90000>;\n\t};\n};\n\n&pridata {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_pridata_400: macaddr@400 {\n\t\treg = <0x400 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9344_qxwlan_e750a-v4-8m.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9344_qxwlan_e750x.dtsi\"\n\n/ {\n\tmodel = \"Qxwlan E750A v4 8M\";\n\tcompatible = \"qxwlan,e750a-v4-8m\", \"qca,ar9344\";\n};\n\n&leds {\n\tlan {\n\t\tlabel = \"green:lan\";\n\t\tgpios = <&gpio 19 GPIO_ACTIVE_LOW>;\n\t};\n\n\twan {\n\t\tlabel = \"green:wan\";\n\t\tgpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tphy-handle = <&swphy4>;\n\n\tnvmem-cells = <&macaddr_pridata_400>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <1>;\n};\n\n&eth1 {\n\tstatus = \"okay\";\n\n\tnvmem-cells = <&macaddr_pridata_400>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tgmac-config {\n\t\tdevice = <&gmac>;\n\t\tswitch-phy-swap = <0>;\n\t\tswitch-only-mode = <1>;\n\t};\n};\n\n&partitions {\n\tpartition@70000 {\n\t\tcompatible = \"denx,uimage\";\n\t\tlabel = \"firmware\";\n\t\treg = <0x070000 0x790000>;\n\t};\n};\n\n&pridata {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_pridata_400: macaddr@400 {\n\t\treg = <0x400 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9344_qxwlan_e750g-v8-16m.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9344_qxwlan_e750x.dtsi\"\n\n/ {\n\tmodel = \"Qxwlan E750G v8 16M\";\n\tcompatible = \"qxwlan,e750g-v8-16m\", \"qca,ar9344\";\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy-mask = <0>;\n\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t\tphy-mode = \"rgmii\";\n\n\t\tqca,ar8327-initvals = <\n\t\t\t0x04 0x07600000 /* PORT0 PAD MODE CTRL */\n\t\t\t0x10 0x81000080 /* POWER_ON_STRAP */\n\t\t\t0x50 0xcc35cc35 /* LED_CTRL0 */\n\t\t\t0x54 0xca35ca35 /* LED_CTRL1 */\n\t\t\t0x58 0xc935c935 /* LED_CTRL2 */\n\t\t\t0x5c 0x03ffff00 /* LED_CTRL3 */\n\t\t\t0x7c 0x0000007e /* PORT0_STATUS */\n\t\t\t>;\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tpll-data = <0x06000000 0x00000101 0x00001616>;\n\n\tnvmem-cells = <&macaddr_pridata_400>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tphy-mode = \"rgmii\";\n\tphy-handle = <&phy0>;\n};\n\n&partitions {\n\tpartition@70000 {\n\t\tcompatible = \"denx,uimage\";\n\t\tlabel = \"firmware\";\n\t\treg = <0x070000 0xf90000>;\n\t};\n};\n\n&pridata {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_pridata_400: macaddr@400 {\n\t\treg = <0x400 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9344_qxwlan_e750g-v8-8m.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9344_qxwlan_e750x.dtsi\"\n\n/ {\n\tmodel = \"Qxwlan E750G v8 8M\";\n\tcompatible = \"qxwlan,e750g-v8-8m\", \"qca,ar9344\";\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy-mask = <0>;\n\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t\tphy-mode = \"rgmii\";\n\n\t\tqca,ar8327-initvals = <\n\t\t\t0x04 0x07600000 /* PORT0 PAD MODE CTRL */\n\t\t\t0x10 0x81000080 /* POWER_ON_STRAP */\n\t\t\t0x50 0xcc35cc35 /* LED_CTRL0 */\n\t\t\t0x54 0xca35ca35 /* LED_CTRL1 */\n\t\t\t0x58 0xc935c935 /* LED_CTRL2 */\n\t\t\t0x5c 0x03ffff00 /* LED_CTRL3 */\n\t\t\t0x7c 0x0000007e /* PORT0_STATUS */\n\t\t\t>;\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tpll-data = <0x06000000 0x00000101 0x00001616>;\n\n\tnvmem-cells = <&macaddr_pridata_400>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tphy-mode = \"rgmii\";\n\tphy-handle = <&phy0>;\n};\n\n&partitions {\n\tpartition@70000 {\n\t\tcompatible = \"denx,uimage\";\n\t\tlabel = \"firmware\";\n\t\treg = <0x070000 0x790000>;\n\t};\n};\n\n&pridata {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_pridata_400: macaddr@400 {\n\t\treg = <0x400 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9344_qxwlan_e750x.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9344.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\taliases {\n\t\tlabel-mac-device = &eth0;\n\t\tled-boot = &led_system;\n\t\tled-failsafe = &led_system;\n\t\tled-running = &led_system;\n\t\tled-upgrade = &led_system;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds: leds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_system: system {\n\t\t\tlabel = \"green:system\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\tsig1 {\n\t\t\tlabel = \"green:sig1\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tsig2 {\n\t\t\tlabel = \"green:sig2\";\n\t\t\tgpios = <&gpio 20 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan {\n\t\t\tlabel = \"green:wlan\";\n\t\t\tgpios = <&gpio 21 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions: partitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x040000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpridata: partition@50000 {\n\t\t\t\tlabel = \"pri-data\";\n\t\t\t\treg = <0x050000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tart: partition@60000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0x060000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&ref {\n\tclock-frequency = <40000000>;\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9344_samsung_wam250.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9344.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"Samsung WAM250\";\n\tcompatible = \"samsung,wam250\", \"qca,ar9344\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tgpios = <&gpio 1 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tlan {\n\t\t\tlabel = \"white:lan\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_power: power {\n\t\t\tlabel = \"white:power\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"keep\";\n\t\t};\n\n\t\trepeater {\n\t\t\tlabel = \"white:repeater\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan {\n\t\t\tlabel = \"white:wlan\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tphy-handle = <&swphy0>;\n\n\tnvmem-cells = <&macaddr_art_1002>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <1>;\n\n\tgmac-config {\n\t\tdevice = <&gmac>;\n\t\tswitch-phy-swap = <1>;\n\t};\n};\n\n&eth1 {\n\tstatus = \"okay\";\n\n\tnvmem-cells = <&macaddr_art_1002>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&gpio {\n\tlna0 {\n\t\tline-name = \"wam250:ext:lna0\";\n\t\tgpios = <19 GPIO_ACTIVE_HIGH>;\n\t\toutput-high;\n\t\tgpio-hog;\n\t};\n};\n\n&ref {\n\tclock-frequency = <40000000>;\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <50000000>;\n\t\tm25p,fast-read;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x040000 0x010000>;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tlabel = \"nvram\";\n\t\t\t\treg = <0x050000 0x020000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@70000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x070000 0xf80000>;\n\t\t\t};\n\n\t\t\tart: partition@ff0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0xff0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&usb {\n\tstatus = \"okay\";\n};\n\n&usb_phy {\n\tstatus = \"okay\";\n};\n\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_1002: macaddr@1002 {\n\t\treg = <0x1002 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9344_teltonika_rut955-h7v3c0.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9344_teltonika_rut9xx.dtsi\"\n#include <dt-bindings/interrupt-controller/irq.h>\n\n/ {\n\tmodel = \"Teltonika RUT955 H7V3C0\";\n\tcompatible = \"teltonika,rut955-h7v3c0\", \"teltonika,rut9xx\", \"qca,ar9344\";\n\n\taliases {\n\t\tled-boot = &led_system_green;\n\t\tled-failsafe = &led_system_red;\n\t\tled-running = &led_system_green;\n\t\tled-upgrade = &led_system_red;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tsignal0 {\n\t\t\tlabel = \"green:signal0\";\n\t\t\tgpios = <&gpio_ext 0 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tsignal1 {\n\t\t\tlabel = \"green:signal1\";\n\t\t\tgpios = <&gpio_ext 1 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tsignal2 {\n\t\t\tlabel = \"green:signal2\";\n\t\t\tgpios = <&gpio_ext 2 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tsignal3 {\n\t\t\tlabel = \"green:signal3\";\n\t\t\tgpios = <&gpio_ext 3 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tsignal4 {\n\t\t\tlabel = \"green:signal4\";\n\t\t\tgpios = <&gpio_ext 4 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tled_system_red: system_red {\n\t\t\tlabel = \"red:system\";\n\t\t\tgpios = <&gpio_ext 5 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tled_system_green: system_green {\n\t\t\tlabel = \"green:system\";\n\t\t\tgpios = <&gpio_ext 6 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&jtag_disable_pins>;\n\n\tgpio-line-names = \"RS485_D\", \"led_wan\", \"wmac_lna\", \"mmc_cs\",\n\t\t\"EXT_INT\", \"\", \"\", \"\",\n\t\t\"\", \"\", \"\", \"\",\n\t\t\"\", \"led_lan2\", \"led_lan1\", \"\",\n\t\t\"i2c_scl\", \"i2c_sda\", \"\", \"\",\n\t\t\"\", \"\", \"led_lan3\", \"\",\n\t\t\"\", \"\", \"\", \"\",\n\t\t\"\", \"\", \"\", \"\";\n\n\text_lna {\n\t\tgpio-hog;\n\t\tgpios = <2 GPIO_ACTIVE_HIGH>;\n\t\toutput-high;\n\t\tline-name = \"rut955:wmac:ext_lna\";\n\t};\n\n\tmmc_cs {\n\t\tgpio-hog;\n\t\tgpios = <3 GPIO_ACTIVE_HIGH>;\n\t\toutput-high;\n\t\tline-name = \"rut955:mmc:cs\";\n\t};\n\n\text_int {\n\t\tgpio-hog;\n\t\tgpios = <4 GPIO_ACTIVE_LOW>;\n\t\tinput;\n\t\tline-name = \"rut955:ext:int\";\n\t};\n\n\tuart1_td {\n\t\tgpio-hog;\n\t\tgpios = <18 GPIO_ACTIVE_HIGH>;\n\t\toutput-high;\n\t\tline-name = \"rut955:uart1:td\";\n\t};\n\n\tuart1_rd {\n\t\tgpio-hog;\n\t\tgpios = <11 GPIO_ACTIVE_LOW>;\n\t\tinput;\n\t\tline-name = \"rut955:uart1:rd\";\n\t};\n\n\tled_wan {\n\t\tgpio-hog;\n\t\tgpios = <1 GPIO_ACTIVE_HIGH>;\n\t\toutput-high;\n\t\tline-name = \"rut955:led:wan\";\n\t};\n\n\tled_lan2 {\n\t\tgpio-hog;\n\t\tgpios = <13 GPIO_ACTIVE_HIGH>;\n\t\toutput-high;\n\t\tline-name = \"rut955:led:lan2\";\n\t};\n\n\tled_lan1 {\n\t\tgpio-hog;\n\t\tgpios = <14 GPIO_ACTIVE_HIGH>;\n\t\toutput-high;\n\t\tline-name = \"rut955:led:lan1\";\n\t};\n\n\tled_lan3 {\n\t\tgpio-hog;\n\t\tgpios = <22 GPIO_ACTIVE_HIGH>;\n\t\toutput-high;\n\t\tline-name = \"rut955:led:lan3\";\n\t};\n};\n\n&i2c0 {\n\tgpio_ext: gpio_ext@74 {\n\t\tstatus = \"okay\";\n\n\t\tcompatible = \"nxp,pca9539\";\n\t\treg = <0x74>;\n\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\n\t\treset-gpios = <&gpio 21 GPIO_ACTIVE_HIGH>;\n\n\t\tinterrupt-parent = <&gpio>;\n\t\tinterrupts = <4 IRQ_TYPE_EDGE_FALLING>;\n\t\tinterrupt-controller;\n\t\t#interrupt-cells = <2>;\n\n\t\tgpio-line-names = \"signal_bar0\", \"signal_bar1\", \"signal_bar2\", \"signal_bar3\",\n\t\t\t\"signal_bar4\", \"status_red\", \"status_green\", \"sim_sel\",\n\t\t\t\"DOUT1\", \"DOUT2\", \"DIN2\", \"DIN1\",\n\t\t\t\"MON\", \"MRST\", \"SDCD\", \"RS485_R\";\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tphy-handle = <&swphy4>;\n\n\tnvmem-cells = <&macaddr_config_0>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <1>;\n};\n\n&eth1 {\n\tstatus = \"okay\";\n\n\tnvmem-cells = <&macaddr_config_0>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&builtin_switch {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pmx_leds_switch>;\n};\n\n&wmac {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pmx_ext_lna>;\n};\n\n&pinmux {\n\tpmx_ext_lna: ext_lna {\n\t\t// EXT_LNA0 on GPIO 2\n\t\tpinctrl-single,bits = <0x0 0x002e0000 0x00ff0000>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9344_teltonika_rut955.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9344_teltonika_rut9xx.dtsi\"\n\n/ {\n\tmodel = \"Teltonika RUT955\";\n\tcompatible = \"teltonika,rut955\", \"teltonika,rut9xx\", \"qca,ar9344\";\n\n\taliases {\n\t\tled-boot = &led_system_green;\n\t\tled-failsafe = &led_system_red;\n\t\tled-running = &led_system_green;\n\t\tled-upgrade = &led_system_red;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tsignal0 {\n\t\t\tlabel = \"green:signal0\";\n\t\t\tgpios = <&gpio_ext 0 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tsignal1 {\n\t\t\tlabel = \"green:signal1\";\n\t\t\tgpios = <&gpio_ext 1 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tsignal2 {\n\t\t\tlabel = \"green:signal2\";\n\t\t\tgpios = <&gpio_ext 2 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tsignal3 {\n\t\t\tlabel = \"green:signal3\";\n\t\t\tgpios = <&gpio_ext 3 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tsignal4 {\n\t\t\tlabel = \"green:signal4\";\n\t\t\tgpios = <&gpio_ext 4 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tled_system_red: system_red {\n\t\t\tlabel = \"red:system\";\n\t\t\tgpios = <&gpio_ext 5 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tled_system_green: system_green {\n\t\t\tlabel = \"green:system\";\n\t\t\tgpios = <&gpio_ext 6 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&jtag_disable_pins>;\n\n\tgpio-line-names = \"RS485_D\", \"led_wan\", \"DIN3\", \"mmc_cs\",\n\t\t\"ext_sck\", \"\", \"\", \"\",\n\t\t\"\", \"\", \"\", \"\",\n\t\t\"ext_mosi\", \"led_lan2\", \"led_lan1\", \"\",\n\t\t\"i2c_scl\", \"i2c_sda\", \"\", \"DIN2\",\n\t\t\"ext_cs\", \"DIN1\", \"led_lan3\", \"\",\n\t\t\"\", \"\", \"\", \"\",\n\t\t\"\", \"\", \"\", \"\";\n\n\text_sck {\n\t\tgpio-hog;\n\t\tgpios = <4 GPIO_ACTIVE_HIGH>;\n\t\toutput-high;\n\t\tline-name = \"rut955:ext:sck\";\n\t};\n\n\text_mosi {\n\t\tgpio-hog;\n\t\tgpios = <12 GPIO_ACTIVE_HIGH>;\n\t\toutput-high;\n\t\tline-name = \"rut955:ext:mosi\";\n\t};\n\n\text_cs {\n\t\tgpio-hog;\n\t\tgpios = <20 GPIO_ACTIVE_HIGH>;\n\t\toutput-low;\n\t\tline-name = \"rut955:ext:cs\";\n\t};\n\n\tmmc_cs {\n\t\tgpio-hog;\n\t\tgpios = <3 GPIO_ACTIVE_HIGH>;\n\t\toutput-high;\n\t\tline-name = \"rut955:mmc:cs\";\n\t};\n\n\tuart1_td {\n\t\tgpio-hog;\n\t\tgpios = <18 GPIO_ACTIVE_HIGH>;\n\t\toutput-high;\n\t\tline-name = \"rut955:uart1:td\";\n\t};\n\n\tuart1_rd {\n\t\tgpio-hog;\n\t\tgpios = <11 GPIO_ACTIVE_LOW>;\n\t\tinput;\n\t\tline-name = \"rut955:uart1:rd\";\n\t};\n\n\tled_wan {\n\t\tgpio-hog;\n\t\tgpios = <1 GPIO_ACTIVE_HIGH>;\n\t\toutput-high;\n\t\tline-name = \"rut955:led:wan\";\n\t};\n\n\tled_lan2 {\n\t\tgpio-hog;\n\t\tgpios = <13 GPIO_ACTIVE_HIGH>;\n\t\toutput-high;\n\t\tline-name = \"rut955:led:lan2\";\n\t};\n\n\tled_lan1 {\n\t\tgpio-hog;\n\t\tgpios = <14 GPIO_ACTIVE_HIGH>;\n\t\toutput-high;\n\t\tline-name = \"rut955:led:lan1\";\n\t};\n\n\tled_lan3 {\n\t\tgpio-hog;\n\t\tgpios = <22 GPIO_ACTIVE_HIGH>;\n\t\toutput-high;\n\t\tline-name = \"rut955:led:lan3\";\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pmx_spi>, <&pmx_spi_ext>;\n\n\tgpio_ext: gpio_ext@2 {\n\t\tcompatible = \"fairchild,74hc595\";\n\t\treg = <2>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\tregisters-number = <2>;\n\t\tspi-max-frequency = <10000000>;\n\t\tgpio-line-names = \"signal_bar0\", \"signal_bar1\", \"signal_bar2\", \"signal_bar3\",\n\t\t\t\"signal_bar4\", \"status_red\", \"status_green\", \"sim_sel\",\n\t\t\t\"DOUT1\", \"DOUT2\", \"modem_vbus\", \"modem_rst\",\n\t\t\t\"DOUT3\", \"RS485_R\", \"SDCS\", \"HWRST\";\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tphy-handle = <&swphy4>;\n\n\tnvmem-cells = <&macaddr_config_0>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <1>;\n};\n\n&eth1 {\n\tstatus = \"okay\";\n\n\tnvmem-cells = <&macaddr_config_0>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&builtin_switch {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pmx_leds_switch>;\n};\n\n&pinmux {\n\tpmx_spi_ext: spi_ext {\n\t\t// 2nd SCK on GPIO 4, 2nd MOSI on GPIO 12, SPI_CS2 on GPIO 20\n\t\tpinctrl-single,bits = <0x4 0x0a 0xff>,\n\t\t\t\t\t<0xc 0x0b 0xff>,\n\t\t\t\t\t<0x14 0x08 0xff>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9344_teltonika_rut9xx.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9344.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"teltonika,rut9xx\", \"qca,ar9344\";\n\n\taliases {\n\t\tserial1 = &hs_uart;\n\t\tlabel-mac-device = &eth1;\n\t};\n\n\ti2c0: i2c {\n\t\tcompatible = \"i2c-gpio\";\n\t\tscl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;\n\t\tsda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\thwmon@4d {\n\t\t\tcompatible = \"microchip,mcp3221\";\n\t\t\treg = <0x4d>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n};\n\n&ref {\n\tclock-frequency = <40000000>;\n};\n\n&hs_uart {\n\tstatus = \"okay\";\n\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pmx_uart2>;\n\n\trts-gpios = <&gpio 0 GPIO_ACTIVE_HIGH>;\n\trs485-rts-active-low;\n\tlinux,rs485-enabled-at-boot-time;\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pmx_spi>;\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x20000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tconfig: partition@20000 {\n\t\t\t\tlabel = \"config\";\n\t\t\t\treg = <0x20000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tart: partition@30000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x40000 0xf30000>;\n\t\t\t\tcompatible = \"tplink,firmware\";\n\t\t\t};\n\n\t\t\tpartition@f70000 {\n\t\t\t\tlabel = \"event-log\";\n\t\t\t\treg = <0xf70000 0x90000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n\n\tmicrosd@1 {\n\t\tstatus = \"disabled\";\n\n\t\tcompatible = \"mmc-spi-slot\";\n\t\tspi-max-frequency = <25000000>;\n\t\treg = <1>;\n\t\tvoltage-ranges = <3200 3400>;\n\t\tbroken-cd;\n\t};\n};\n\n&usb {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\tstatus = \"okay\";\n\n\tport@1 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <1>;\n\n\t\tport@1 {\n\t\t\tcompatible = \"usb-a-connector\";\n\t\t\treg = <1>;\n\t\t};\n\n\t\tport@3 {\n\t\t\tlabel = \"RS-232 serial adapter\";\n\t\t\treg = <3>;\n\t\t};\n\n\t\tport@4 {\n\t\t\tlabel = \"internal wwan modem\";\n\t\t\treg = <4>;\n\t\t};\n\t};\n};\n\n&usb_phy {\n\tstatus = \"okay\";\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n\tnvmem-cells = <&macaddr_config_0>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <2>;\n};\n\n&pinmux {\n\tpmx_spi: spi {\n\t\t// SPI_CS1 on GPIO 3\n\t\tpinctrl-single,bits =\t<0x0 0x07000000 0xff000000>;\n\t};\n\n\tpmx_leds_switch: leds_switch {\n\t\t// switch port LEDs on GPIO 1, GPIO 13, GPIO 14 and GPIO 22\n\t\tpinctrl-single,bits =\t<0x00 0x00002d00 0x0000ff00>,\n\t\t\t\t\t<0x0c 0x002c2b00 0x00ffff00>,\n\t\t\t\t\t<0x14 0x002a0000 0x00ff0000>;\n\t};\n\n\tpmx_uart2: uart2 {\n\t\t// UART1_DTR on GPIO 0, UART1_RD on GPIO 11, UART1_TD on GPIO 18\n\t\tpinctrl-single,bits =\t<0x00 0x00000000 0x000000ff>,\n\t\t\t\t\t<0x10 0x004f0000 0x00ff0000>,\n\t\t\t\t\t<0x3c 0x000b0000 0x00ff0000>;\n\t};\n};\n\n&config {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_config_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9344_tplink_cpe.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9344.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/mtd/partitions/uimage.h>\n\n/ {\n\taliases {\n\t\tlabel-mac-device = &wmac;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n};\n\n&ref {\n\tclock-frequency = <40000000>;\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tuboot: partition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x020000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tlabel = \"partition-table\";\n\t\t\t\treg = <0x020000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tinfo: partition@30000 {\n\t\t\t\tlabel = \"info\";\n\t\t\t\treg = <0x030000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x040000 0x780000>;\n\t\t\t\tcompatible = \"openwrt,uimage\", \"denx,uimage\";\n\t\t\t\topenwrt,ih-magic = <IH_MAGIC_OKLI>;\n\t\t\t\topenwrt,offset = <0x3000>;\n\t\t\t};\n\n\t\t\tpartition@7c0000 {\n\t\t\t\tlabel = \"config\";\n\t\t\t\treg = <0x7c0000 0x030000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tart: partition@7f0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0x7f0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n\tnvmem-cells = <&macaddr_info_8>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tphy-handle = <&swphy4>;\n\n\tnvmem-cells = <&macaddr_info_8>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&eth1 {\n\tstatus = \"okay\";\n};\n\n&gpio {\n\tgpio_ext_lna0 {\n\t\tgpio-hog;\n\t\tgpios = <18 GPIO_ACTIVE_HIGH>;\n\t\toutput-high;\n\t\tline-name = \"tp-link:ext:lna0\";\n\t};\n\n\tgpio_ext_lna1 {\n\t\tgpio-hog;\n\t\tgpios = <19 GPIO_ACTIVE_HIGH>;\n\t\toutput-high;\n\t\tline-name = \"tp-link:ext:lna1\";\n\t};\n};\n\n&info {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_info_8: macaddr@8 {\n\t\treg = <0x8 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9344_tplink_cpe210-v1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9344_tplink_cpe_2port.dtsi\"\n\n/ {\n\tcompatible = \"tplink,cpe210-v1\", \"qca,ar9344\";\n\tmodel = \"TP-Link CPE210 v1\";\n};\n\n&led_link4 {\n\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9344_tplink_cpe220-v2.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9344_tplink_cpe_2port.dtsi\"\n\n/ {\n\tcompatible = \"tplink,cpe220-v2\", \"qca,ar9344\";\n\tmodel = \"TP-Link CPE220 v2\";\n};\n\n&led_link4 {\n\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9344_tplink_cpe510-v1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9344_tplink_cpe_2port.dtsi\"\n\n/ {\n\tcompatible = \"tplink,cpe510-v1\", \"qca,ar9344\";\n\tmodel = \"TP-Link CPE510 v1\";\n};\n\n&led_link4 {\n\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9344_tplink_cpe510-v2.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9344_tplink_cpe_1port.dtsi\"\n\n/ {\n\tcompatible = \"tplink,cpe510-v2\", \"qca,ar9344\";\n\tmodel = \"TP-Link CPE510 v2\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9344_tplink_cpe510-v3.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9344_tplink_cpe_1port.dtsi\"\n\n/ {\n\tcompatible = \"tplink,cpe510-v3\", \"qca,ar9344\";\n\tmodel = \"TP-Link CPE510 v3\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9344_tplink_cpe610-v1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9344_tplink_cpe.dtsi\"\n\n/ {\n\tmodel = \"TP-Link CPE610 v1\";\n\tcompatible = \"tplink,cpe610-v1\", \"qca,ar9344\";\n\n\taliases {\n\t\tled-boot = &led_lan;\n\t\tled-failsafe = &led_lan;\n\t\tled-upgrade = &led_lan;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_lan: lan {\n\t\t\tlabel = \"green:lan\";\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan5g {\n\t\t\tlabel = \"green:wlan5g\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\t};\n};\n\n&eth1 {\n\tcompatible = \"syscon\", \"simple-mfd\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9344_tplink_cpe610-v2.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9344_tplink_cpe.dtsi\"\n\n/ {\n\tmodel = \"TP-Link CPE610 v2\";\n\tcompatible = \"tplink,cpe610-v2\", \"qca,ar9344\";\n\n\taliases {\n\t\tled-boot = &led_lan;\n\t\tled-failsafe = &led_lan;\n\t\tled-upgrade = &led_lan;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_lan: lan {\n\t\t\tlabel = \"green:lan\";\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan5g {\n\t\t\tlabel = \"green:wlan5g\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\t};\n};\n\n&eth1 {\n\tcompatible = \"syscon\", \"simple-mfd\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9344_tplink_cpe_1port.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9344_tplink_cpe.dtsi\"\n\n/ {\n\taliases {\n\t\tled-boot = &led_system;\n\t\tled-failsafe = &led_system;\n\t\tled-running = &led_system;\n\t\tled-upgrade = &led_system;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tlan {\n\t\t\tlabel = \"green:lan\";\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlink1 {\n\t\t\tlabel = \"green:link1\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlink2 {\n\t\t\tlabel = \"green:link2\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlink3 {\n\t\t\tlabel = \"green:link3\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_system: link4 {\n\t\t\tlabel = \"green:link4\";\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&eth1 {\n\tcompatible = \"syscon\", \"simple-mfd\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9344_tplink_cpe_2port.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9344_tplink_cpe.dtsi\"\n\n/ {\n\taliases {\n\t\tled-boot = &led_link4;\n\t\tled-failsafe = &led_link4;\n\t\tled-running = &led_link4;\n\t\tled-upgrade = &led_link4;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tlan0 {\n\t\t\tlabel = \"green:lan0\";\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan1 {\n\t\t\tlabel = \"green:lan1\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlink1 {\n\t\t\tlabel = \"green:link1\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlink2 {\n\t\t\tlabel = \"green:link2\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlink3 {\n\t\t\tlabel = \"green:link3\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_link4: link4 {\n\t\t\tlabel = \"green:link4\";\n\t\t};\n\t};\n};\n\n&eth1 {\n\tnvmem-cells = <&macaddr_info_8>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tgmac-config {\n\t\tdevice = <&gmac>;\n\t\tswitch-phy-swap = <0>;\n\t\tswitch-only-mode = <1>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9344_tplink_tl-wdr3500-v1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9344_tplink_tl-wdrxxxx.dtsi\"\n\n/ {\n\tmodel = \"TP-Link TL-WDR3500 v1\";\n\tcompatible = \"tplink,tl-wdr3500-v1\", \"qca,ar9344\";\n\n\taliases {\n\t\tlabel-mac-device = &wmac;\n\t};\n};\n\n&leds {\n\tusb {\n\t\tlabel = \"green:usb\";\n\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\tlinux,default-trigger = \"usbport\";\n\t\ttrigger-sources = <&hub_port>;\n\t};\n};\n\n&gpio {\n\tusb_power {\n\t\tgpio-hog;\n\t\tgpios = <12 GPIO_ACTIVE_HIGH>;\n\t\toutput-high;\n\t\tline-name = \"tp-link:power:usb\";\n\t};\n};\n\n&pinmux {\n\tpmx_led_wan_lan: pinmux_led_wan_lan {\n\t\tpinctrl-single,bits = <0x10 0x2c2d0000 0xffff0000>,\n\t\t\t<0x14 0x292a2b 0xffffff>;\n\t};\n};\n\n&builtin_switch {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pmx_led_wan_lan>;\n};\n\n&usb {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\tstatus = \"okay\";\n\n\thub_port: port@1 {\n\t\treg = <1>;\n\t\t#trigger-source-cells = <0>;\n\t};\n};\n\n&usb_phy {\n\tstatus = \"okay\";\n};\n\n&ath9k {\n\tnvmem-cells = <&macaddr_uboot_1fc00>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <1>;\n};\n\n&wmac {\n\tnvmem-cells = <&macaddr_uboot_1fc00>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&eth1 {\n\tstatus = \"okay\";\n\n\tnvmem-cells = <&macaddr_uboot_1fc00>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <(-1)>;\n\n\tgmac-config {\n\t\tdevice = <&gmac>;\n\t\tswitch-phy-swap = <0>;\n\t\tswitch-only-mode = <1>;\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tphy-handle = <&swphy4>;\n\n\tnvmem-cells = <&macaddr_uboot_1fc00>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <2>;\n};\n\n&uboot {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_uboot_1fc00: macaddr@1fc00 {\n\t\treg = <0x1fc00 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9344_tplink_tl-wdr3600-v1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9344_tplink_tl-wdr4300.dtsi\"\n\n/ {\n\tmodel = \"TP-Link TL-WDR3600 v1\";\n\tcompatible = \"tplink,tl-wdr3600-v1\", \"qca,ar9344\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9344_tplink_tl-wdr4300-v1-il.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9344_tplink_tl-wdr4300.dtsi\"\n\n/ {\n\tmodel = \"TP-Link TL-WDR4300 v1 (IL)\";\n\tcompatible = \"tplink,tl-wdr4300-v1-il\", \"qca,ar9344\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9344_tplink_tl-wdr4300-v1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9344_tplink_tl-wdr4300.dtsi\"\n\n/ {\n\tmodel = \"TP-Link TL-WDR4300 v1\";\n\tcompatible = \"tplink,tl-wdr4300-v1\", \"qca,ar9344\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9344_tplink_tl-wdr4300.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9344_tplink_tl-wdrxxxx.dtsi\"\n\n/ {\n\taliases {\n\t\tlabel-mac-device = &ath9k;\n\t};\n\n\tgpio-export {\n\t\tcompatible = \"gpio-export\";\n\n\t\tgpio_usb1_power {\n\t\t\tgpio-export,name = \"tp-link:power:usb1\";\n\t\t\tgpio-export,output = <1>;\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tgpio_usb2_power {\n\t\t\tgpio-export,name = \"tp-link:power:usb2\";\n\t\t\tgpio-export,output = <1>;\n\t\t\tgpios = <&gpio 21 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tgpio_ext_lna0 {\n\t\t\tgpio-export,name = \"tp-link:ext:lna0\";\n\t\t\tgpio-export,output = <1>;\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tgpio_ext_lna1 {\n\t\t\tgpio-export,name = \"tp-link:ext:lna1\";\n\t\t\tgpio-export,output = <1>;\n\t\t\tgpios = <&gpio 19 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&leds {\n\tusb1 {\n\t\tlabel = \"green:usb1\";\n\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\ttrigger-sources = <&hub_port1>;\n\t\tlinux,default-trigger = \"usbport\";\n\t};\n\n\tusb2 {\n\t\tlabel = \"green:usb2\";\n\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\ttrigger-sources = <&hub_port2>;\n\t\tlinux,default-trigger = \"usbport\";\n\t};\n};\n\n&usb {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\tstatus = \"okay\";\n\n\tport@1 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <1>;\n\t\t#trigger-source-cells = <0>;\n\n\t\thub_port1: port@1 {\n\t\t\treg = <1>;\n\t\t\t#trigger-source-cells = <0>;\n\t\t};\n\n\t\thub_port2: port@2 {\n\t\t\treg = <2>;\n\t\t\t#trigger-source-cells = <0>;\n\t\t};\n\t};\n};\n\n&usb_phy {\n\tstatus = \"okay\";\n};\n\n&ath9k {\n\tnvmem-cells = <&macaddr_uboot_1fc00>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wmac {\n\tnvmem-cells = <&macaddr_uboot_1fc00>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <(-1)>;\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy-mask = <0>;\n\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t\tphy-mode = \"rgmii\";\n\n\t\tqca,ar8327-initvals = <\n\t\t\t0x04 0x07600000 /* PORT0 PAD MODE CTRL */\n\t\t\t0x10 0x80000080 /* POWER_ON_STRAP */\n\t\t\t0x50 0xc737c737 /* LED_CTRL0 */\n\t\t\t0x54 0x00000000 /* LED_CTRL1 */\n\t\t\t0x58 0x00000000 /* LED_CTRL2 */\n\t\t\t0x5c 0x0030c300 /* LED_CTRL3 */\n\t\t\t0x7c 0x0000007e /* PORT0_STATUS */\n\t\t\t>;\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\t/* default for ar934x, except for 1000M */\n\tpll-data = <0x06000000 0x00000101 0x00001616>;\n\n\tnvmem-cells = <&macaddr_uboot_1fc00>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tphy-mode = \"rgmii\";\n\tphy-handle = <&phy0>;\n};\n\n&uboot {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_uboot_1fc00: macaddr@1fc00 {\n\t\treg = <0x1fc00 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9344_tplink_tl-wdr4310-v1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9344_tplink_tl-wdr4300.dtsi\"\n\n/ {\n\tmodel = \"TP-Link TL-WDR4310 v1\";\n\tcompatible = \"tplink,tl-wdr4310-v1\", \"qca,ar9344\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9344_tplink_tl-wdrxxxx.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9344.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\taliases {\n\t\tled-boot = &led_system;\n\t\tled-failsafe = &led_system;\n\t\tled-running = &led_system;\n\t\tled-upgrade = &led_system;\n\t};\n\n\tleds: leds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twlan2g {\n\t\t\tlabel = \"green:wlan2g\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\tled_system: system {\n\t\t\tlabel = \"green:system\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\tqss {\n\t\t\tlabel = \"green:qss\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tath9k-leds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twlan5g {\n\t\t\tlabel = \"green:wlan5g\";\n\t\t\tgpios = <&ath9k 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\twifi {\n\t\t\tlinux,code = <KEY_RFKILL>;\n\t\t\tlinux,input-type = <EV_SW>;\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n};\n\n&ref {\n\tclock-frequency = <40000000>;\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <33000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tuboot: partition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x020000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tcompatible = \"tplink,firmware\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x020000 0x7d0000>;\n\t\t\t};\n\n\t\t\tart: partition@7f0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0x7f0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n\n\tath9k: wifi@0,0 {\n\t\tcompatible = \"pci168c,0033\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tqca,no-eeprom;\n\t\t#gpio-cells = <2>;\n\t\tgpio-controller;\n\t};\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9344_tplink_tl-wr841hp-v2.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9344.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"TP-Link TL-WR841HP v2\";\n\tcompatible = \"tplink,tl-wr841hp-v2\", \"qca,ar9344\";\n\n\taliases {\n\t\tled-boot = &led_system;\n\t\tled-failsafe = &led_system;\n\t\tled-running = &led_system;\n\t\tled-upgrade = &led_system;\n\t\tlabel-mac-device = &wmac;\n\t};\n\t\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_HIGH>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\t\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twan {\n\t\t\tlabel = \"green:wan\";\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan1 {\n\t\t\tlabel = \"green:lan1\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan2 {\n\t\t\tlabel = \"green:lan2\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan3 {\n\t\t\tlabel = \"green:lan3\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan4 {\n\t\t\tlabel = \"green:lan4\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\t\n\t\twps {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\t\n\t\twlan {\n\t\t\tlabel = \"green:wlan\";\n\t\t\tgpios = <&gpio 21 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\tled_system: system {\n\t\t\tlabel = \"green:system\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n};\n\n&ref {\n\tclock-frequency = <40000000>;\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tuboot: partition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x020000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tcompatible = \"tplink,firmware\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x020000 0x7d0000>;\n\t\t\t};\n\n\t\t\tart: partition@7f0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0x7f0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&gpio {\n\tgpio_ext_lna0 {\n\t\tgpio-hog;\n\t\tgpios = <18 GPIO_ACTIVE_HIGH>;\n\t\toutput-high;\n\t\tline-name = \"tp-link:ext:lna0\";\n\t};\n\n\tgpio_ext_lna1 {\n\t\tgpio-hog;\n\t\tgpios = <19 GPIO_ACTIVE_HIGH>;\n\t\toutput-high;\n\t\tline-name = \"tp-link:ext:lna1\";\n\t};\n};\n\n&wmac {\n\tstatus = \"okay\";\n\t\n\tmtd-cal-data = <&art 0x1000>;\n\t\n\tnvmem-cells = <&macaddr_uboot_1fc00>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\t\n\tphy-handle = <&swphy0>;\n\n\tnvmem-cells = <&macaddr_uboot_1fc00>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <1>;\n};\n\n&eth1 {\n\tstatus = \"okay\";\n\n\tnvmem-cells = <&macaddr_uboot_1fc00>;\n\tnvmem-cell-names = \"mac-address\";\n\t\n\tgmac-config {\n\t\tdevice = <&gmac>;\n\t\tswitch-phy-swap = <1>;\n\t};\n};\n\n&uboot {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_uboot_1fc00: macaddr@1fc00 {\n\t\treg = <0x1fc00 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9344_tplink_wbs210-v1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9344_tplink_cpe_2port.dtsi\"\n\n/ {\n\tcompatible = \"tplink,wbs210-v1\", \"qca,ar9344\";\n\tmodel = \"TP-Link WBS210 v1\";\n};\n\n&led_link4 {\n\tgpios = <&gpio 2 GPIO_ACTIVE_LOW>;\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9344_tplink_wbs210-v2.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9344_tplink_cpe_2port.dtsi\"\n\n/ {\n\tcompatible = \"tplink,wbs210-v2\", \"qca,ar9344\";\n\tmodel = \"TP-Link WBS210 v2\";\n};\n\n&led_link4 {\n\tgpios = <&gpio 2 GPIO_ACTIVE_LOW>;\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9344_tplink_wbs510-v1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9344_tplink_cpe_2port.dtsi\"\n\n/ {\n\tcompatible = \"tplink,wbs510-v1\", \"qca,ar9344\";\n\tmodel = \"TP-Link WBS510 v1\";\n};\n\n&led_link4 {\n\tgpios = <&gpio 2 GPIO_ACTIVE_LOW>;\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9344_tplink_wbs510-v2.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9344_tplink_cpe_2port.dtsi\"\n\n/ {\n\tcompatible = \"tplink,wbs510-v2\", \"qca,ar9344\";\n\tmodel = \"TP-Link WBS510 v2\";\n};\n\n&led_link4 {\n\tgpios = <&gpio 2 GPIO_ACTIVE_LOW>;\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9344_ubnt_unifi-ap-pro.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9344.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"Ubiquiti UniFi AP Pro\";\n\tcompatible = \"ubnt,unifi-ap-pro\";\n\n\taliases {\n\t\tled-boot = &led_white;\n\t\tled-failsafe = &led_white;\n\t\tled-running = &led_blue;\n\t\tled-upgrade = &led_blue;\n\t\tlabel-mac-device = &eth0;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_white: led-white {\n\t\t\tlabel = \"white:dome\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tled_blue: led-blue {\n\t\t\tlabel = \"blue:dome\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n};\n\n&ref {\n\tclock-frequency = <40000000>;\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <50000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tuboot: partition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x40000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0xf60000>;\n\n\t\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\n\t\t\t\tpartition@0 {\n\t\t\t\t\tlabel = \"kernel\";\n\t\t\t\t\treg = <0x0 0x300000>;\n\t\t\t\t\t/* Can be resized w/o issues.\n\t\t\t\t\t * U-Boot can load kernel from the\n\t\t\t\t\t * entirety of the \"firmware\" partition space.\n\t\t\t\t\t */\n\t\t\t\t};\n\n\t\t\t\tpartition@300000 {\n\t\t\t\t\tlabel = \"rootfs\";\n\t\t\t\t\treg = <0x300000 0xc60000>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tpartition@fb0000 {\n\t\t\t\tlabel = \"cfg\";\n\t\t\t\treg = <0xfb0000 0x40000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tart: partition@ff0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0xff0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n\n\twifi@0,0 {\n\t\tcompatible = \"pci168c,0033\";\n\t\treg = <0 0 0 0 0>;\n\t\tqca,no-eeprom;\n\t};\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\n\t\tqca,ar8327-initvals = <\n\t\t\t0x4 0x7600000 /* PORT0 PAD MODE CTRL */\n\t\t\t0x10 0x80000080 /* POWER_ON_STRAP */\n\t\t\t0x7c 0x7e /* PORT0_STATUS */\n\t\t\t>;\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tpll-data = <0x6000000 0x101 0x1616>;\n\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tphy-mode = \"rgmii\";\n\tphy-handle = <&phy0>;\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9344_wd_mynet-n600.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9344_wd_mynet-nxxx.dtsi\"\n#include <dt-bindings/leds/common.h>\n\n/ {\n\tmodel = \"Western Digital My Net N600\";\n\tcompatible = \"wd,mynet-n600\", \"qca,ar9344\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled-0 {\n                        color = <LED_COLOR_ID_BLUE>;\n                        function = LED_FUNCTION_WLAN;\n\t\t\tgpios = <&gpio 0 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tled_power: led-1 {\n\t\t\tlabel = \"blue:power\";\n                        color = <LED_COLOR_ID_BLUE>;\n                        function = LED_FUNCTION_POWER;\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tled-2 {\n                        color = <LED_COLOR_ID_BLUE>;\n                        function = LED_FUNCTION_WAN;\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tled-3 {\n                        color = <LED_COLOR_ID_BLUE>;\n                        function = LED_FUNCTION_WPS;\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twps {\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&gpio {\n\tgpio_ext_lna0 {\n\t\tgpio-hog;\n\t\tgpios = <14 0>;\n\t\toutput-high;\n\t\tline-name = \"ext:lna0\";\n\t};\n\n\tgpio_ext_lna1 {\n\t\tgpio-hog;\n\t\tgpios = <15 0>;\n\t\toutput-high;\n\t\tline-name = \"ext:lna1\";\n\t};\n};\n\n&pinmux {\n\tpmx_led_switch: pinmux_led_switch {\n\t\tpinctrl-single,bits =\n\t\t\t<0x0 0x2c2b2a00 0xffffff00>, /* GPIO1-3 default to PHY2-4 */\n\t\t\t<0x4 0x00000029 0x000000ff>; /* GPIO4 default to PHY1 */\n\t};\n};\n\n&builtin_switch {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pmx_led_switch>;\n};\n\n&usb {\n\tstatus = \"okay\";\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tphy-handle = <&swphy0>;\n\n\tgmac-config {\n\t\tdevice = <&gmac>;\n\t\tswitch-phy-swap = <1>;\n\t\tswitch-only-mode = <1>;\n\t};\n};\n\n&eth1 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9344_wd_mynet-n750.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9344_wd_mynet-nxxx.dtsi\"\n\n/ {\n\tmodel = \"Western Digital My Net N750\";\n\tcompatible = \"wd,mynet-n750\", \"qca,ar9344\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twifi {\n\t\t\tlabel = \"blue:wireless\";\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tinternet {\n\t\t\tlabel = \"blue:internet\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"blue:wps\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tled_power: power {\n\t\t\tlabel = \"blue:power\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twps {\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tgpios = <&gpio 19 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&gpio {\n\tgpio_ext_lna0 {\n\t\tgpio-hog;\n\t\tgpios = <15 0>;\n\t\toutput-high;\n\t\tline-name = \"ext:lna0\";\n\t};\n\n\tgpio_ext_lna1 {\n\t\tgpio-hog;\n\t\tgpios = <18 0>;\n\t\toutput-high;\n\t\tline-name = \"ext:lna1\";\n\t};\n};\n\n&usb {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\tstatus = \"okay\";\n\n\tport@1 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <1>;\n\t\t#trigger-source-cells = <0>;\n\n\t\thub_port1: port@1 {\n\t\t\treg = <1>;\n\t\t\t#trigger-source-cells = <0>;\n\t\t};\n\n\t\thub_port2: port@2 {\n\t\t\treg = <2>;\n\t\t\t#trigger-source-cells = <0>;\n\t\t};\n\t};\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy-mask = <0>;\n\n\tswitch0@1f {\n\t\tcompatible = \"qca,ar8327\";\n\t\treg = <0x1f>;\n\n\t\tqca,ar8327-initvals = <\n\t\t\t0x04 0x07600000 /* PORT0 PAD MODE CTRL */\n\t\t\t0x10 0x80000080 /* POWER_ON_STRAP */\n\t\t\t0x50 0xc737c737 /* LED_CTRL0 */\n\t\t\t0x54 0x00000000 /* LED_CTRL1 */\n\t\t\t0x58 0x00000000 /* LED_CTRL2 */\n\t\t\t0x5c 0x0030c300 /* LED_CTRL3 */\n\t\t\t0x7c 0x0000007e /* PORT0_STATUS */\n\t\t\t>;\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\t/* default for ar934x, except for 1000M */\n\tpll-data = <0x06000000 0x00000101 0x00001616>;\n\n\tphy-mode = \"rgmii\";\n\tfixed-link {\n\t\tspeed = <1000>;\n\t\tfull-duplex;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9344_wd_mynet-nxxx.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9344.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200n8\";\n\t};\n};\n\n&ref {\n\tclock-frequency = <40000000>;\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"bootloader\";\n\t\t\t\treg = <0x000000 0x040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"bdcfg\";\n\t\t\t\treg = <0x040000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tlabel = \"devdata\";\n\t\t\t\treg = <0x050000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@60000 {\n\t\t\t\tlabel = \"devconf\";\n\t\t\t\treg = <0x060000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@70000 {\n\t\t\t\tcompatible = \"seama\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x070000 0xf80000>;\n\t\t\t};\n\n\t\t\tart: partition@ff0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0xff0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&usb_phy {\n\tstatus = \"okay\";\n};\n\n&pcie {\n\tstatus = \"okay\";\n\n\twifi@0,0 {\n\t\tcompatible = \"pci168c,0033\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tqca,no-eeprom;\n\t};\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tqca,no-eeprom;\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9344_wd_mynet-wifi-rangeextender.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9344.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"Western Digital My Net Wi-Fi Range Extender\";\n\tcompatible = \"wd,mynet-wifi-rangeextender\", \"qca,ar9344\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200n8\";\n\t};\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"blue:power\";\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_HIGH>;\n\t\t\t/* LED has no off state. It's either on or it blinks */\n\t\t};\n\n\t\tlan {\n\t\t\tlabel = \"green:lan\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twifi {\n\t\t\tlabel = \"blue:wifi\";\n\t\t\tgpios = <&gpio 19 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\twifi-rssi-low {\n\t\t\tlabel = \"blue:rssi-low\";\n\t\t\tgpios = <&gpio 20 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twifi-rssi-med {\n\t\t\tlabel = \"blue:rssi-med\";\n\t\t\tgpios = <&gpio 21 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twifi-rssi-max {\n\t\t\tlabel = \"blue:rssi-max\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tband-switch {\n\t\t\tlinux,code = <BTN_1>;\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,input-type = <EV_SW>;\n\t\t};\n\n\t\twps {\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&ref {\n\tclock-frequency = <25000000>;\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = /* \"s25fl064k\", */ \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tuboot: partition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x40000 0x7a0000>;\n\t\t\t\tcompatible = \"cybertan,trx\";\n\t\t\t};\n\n\t\t\tnvram: partition@7e0000 {\n\t\t\t\tlabel = \"nvram\";\n\t\t\t\treg = <0x7e0000 0x10000>;\n\t\t\t};\n\n\t\t\tart: partition@7f0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0x7f0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n\n\tath9k: wifi@0,0 {\n\t\tcompatible = \"pci168c,0030\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tqca,no-eeprom;\n\t\t/* wifi MAC is stored in nvram */\n\t};\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy-mask = <0x10>;\n\n\tphy4: ethernet-phy@4 {\n\t\treg = <4>;\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tpll-data = <0x02000000 0x00000101 0x00001313>;\n\n\t/* ethernet MAC is stored in nvram */\n\tphy-mode = \"rgmii-id\";\n\tphy-handle = <&phy4>;\n\n\tgmac-config {\n\t\tdevice = <&gmac>;\n\t\trgmii-gmac0 = <1>;\n\t\trxd-delay = <3>;\n\t\trxdv-delay = <3>;\n\t};\n};\n\n&mdio1 {\n\tstatus = \"disabled\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9344_winchannel_wb2000.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9344.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"Winchannel WB2000\";\n\tcompatible = \"winchannel,wb2000\", \"qca,ar9344\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200n8\";\n\t};\n\n\taliases {\n\t\tled-boot = &led_system;\n\t\tled-failsafe = &led_system;\n\t\tled-running = &led_system;\n\t\tled-upgrade = &led_system;\n\t};\n\n\ti2c {\n\t\tcompatible = \"i2c-gpio\";\n\t\tgpios = <&gpio 17 GPIO_ACTIVE_HIGH\n\t\t\t &gpio 16 GPIO_ACTIVE_HIGH\n\t\t\t>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\trtc@68 {\n\t\t\tcompatible = \"dallas,ds1339\";\n\t\t\treg = <0x68>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twlan2g {\n\t\t\tlabel = \"green:2g\";\n\t\t\tgpios = <&gpio 20 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\tusb {\n\t\t\tlabel = \"green:usb\";\n\t\t\tgpios = <&gpio 21 GPIO_ACTIVE_HIGH>;\n\t\t\ttrigger-sources = <&hub_port1>, <&hub_port2>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\n\t\tled_system: system {\n\t\t\tlabel = \"green:system\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 3 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tath9k-leds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twlan {\n\t\t\tlabel = \"green:5g\";\n\t\t\tgpios = <&ath9k 6 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\t};\n};\n\n&ref {\n\tclock-frequency = <40000000>;\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x40000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0xf80000>;\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t};\n\n\t\t\tpartition@fd0000 {\n\t\t\t\tlabel = \"nvram\";\n\t\t\t\treg = <0xfd0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tart: partition@fe0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0xfe0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\taddr: partition@ff0000 {\n\t\t\t\tlabel = \"addr\";\n\t\t\t\treg = <0xff0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n\n\tath9k: wifi@0,0 {\n\t\tcompatible = \"pci168c,0030\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tqca,no-eeprom;\n\t\tnvmem-cells = <&macaddr_addr_0>;\n\t\tnvmem-cell-names = \"mac-address\";\n\t\tmac-address-increment = <0x10>;\n\t\t#gpio-cells = <2>;\n\t\tgpio-controller;\n\t};\n};\n\n&usb {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\tstatus = \"okay\";\n\n\tport@1 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <1>;\n\t\t#trigger-source-cells = <0>;\n\n\t\thub_port1: port@1 {\n\t\t\treg = <1>;\n\t\t\t#trigger-source-cells = <0>;\n\t\t};\n\n\t\thub_port2: port@2 {\n\t\t\treg = <2>;\n\t\t\t#trigger-source-cells = <0>;\n\t\t};\n\t};\n};\n\n&usb_phy {\n\tstatus = \"okay\";\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n\tnvmem-cells = <&macaddr_addr_0>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy-mask = <0x10>;\n\n\tphy4: ethernet-phy@4 {\n\t\treg = <4>;\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tpll-data = <0xe000000 0x04000101 0x04001313>;\n\n\tnvmem-cells = <&macaddr_addr_0>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <0x21>;\n\n\tphy-mode = \"rgmii-rxid\";\n\tphy-handle = <&phy4>;\n\n\tgmac-config {\n\t\tdevice = <&gmac>;\n\t\trgmii-gmac0 = <1>;\n\t\trxd-delay = <1>;\n\t\trxdv-delay = <1>;\n\t};\n};\n\n&addr {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_addr_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar9344_zbtlink_zbt-wd323.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ar9344.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"ZBT WD323\";\n\tcompatible = \"zbtlink,zbt-wd323\", \"qca,ar9344\";\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\ti2c {\n\t\tcompatible = \"i2c-gpio\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tpinctrl-names = \"default\";\n\t\tpinctrl-0 = <&enable_gpio15 &enable_gpio19>;\n\n\t\tsda-gpios = <&gpio 19 GPIO_ACTIVE_LOW>;\n\t\tscl-gpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\n\t\tpcf8563: pcf8563@51 {\n\t\t\tcompatible = \"nxp,pcf8563\";\n\t\t\treg = <0x51>;\n\t\t\t#clock-cells = <0>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tpinctrl-names = \"default\";\n\t\tpinctrl-0 = <&enable_gpio20_gpio22>;\n\n\t\twifi {\n\t\t\tlabel = \"green:wifi\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\tlan1 {\n\t\t\tlabel = \"orange:lan1\";\n\t\t\tgpios = <&gpio 20 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan2 {\n\t\t\tlabel = \"orange:lan2\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&wdt {\n\tstatus = \"okay\";\n\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&enable_gpio21>;\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&jtag_disable_pins>;\n};\n\n&usb {\n\tstatus = \"okay\";\n};\n\n&usb_phy {\n\tstatus = \"okay\";\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\tphy-handle = <&swphy4>;\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&eth1 {\n\tstatus = \"okay\";\n\tnvmem-cells = <&macaddr_art_6>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\tspi-max-frequency = <22000000>;\n\t\treg = <0>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tuboot@0 {\n\t\t\t\treg = <0x0 0x40000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tuboot-env@40000 {\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfirmware@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\treg = <0x50000 0xfa0000>;\n\t\t\t};\n\n\t\t\tart: art@ff0000 {\n\t\t\t\treg = <0xff0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&wmac {\n\tstatus = \"okay\";\n\tmtd-cal-data = <&art 0x1000>;\n};\n\n&pinmux {\n\tenable_gpio15: pinmux_enable_gpio15 {\n\t\tpinctrl-single,bits = <0xc 0x0 0xff000000>;\n\t};\n\n\tenable_gpio19: pinmux_enable_gpio19 {\n\t\tpinctrl-single,bits = <0x10 0x0 0xff000000>;\n\t};\n\n\tenable_gpio20_gpio22: pinmux_enable_gpio20_gpio22 {\n\t\tpinctrl-single,bits = <0x14 0x0 0xff00ff>;\n\t};\n\n\tenable_gpio21: pinmux_enable_gpio21 {\n\t\tpinctrl-single,bits = <0x14 0x0 0xff00>;\n\t};\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n\n\tmacaddr_art_6: macaddr@6 {\n\t\treg = <0x6 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar934x.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ath79.dtsi\"\n\n/ {\n\tcompatible = \"qca,ar9340\";\n\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\taliases {\n\t\tserial0 = &uart;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200\";\n\t};\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu@0 {\n\t\t\tdevice_type = \"cpu\";\n\t\t\tcompatible = \"mips,mips74Kc\";\n\t\t\tclocks = <&pll ATH79_CLK_CPU>;\n\t\t\treg = <0>;\n\t\t};\n\t};\n\n\tclocks {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tranges;\n\n\t\tref: ref {\n\t\t\t#clock-cells = <0>;\n\t\t\tcompatible = \"fixed-clock\";\n\t\t\tclock-output-names = \"ref\";\n\t\t};\n\t};\n\n\tahb: ahb {\n\t\tcompatible = \"simple-bus\";\n\t\tranges;\n\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tapb: apb {\n\t\t\tcompatible = \"simple-bus\";\n\t\t\tranges;\n\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tddr_ctrl: memory-controller@18000000 {\n\t\t\t\tcompatible = \"qca,ar9340-ddr-controller\",\n\t\t\t\t\t\t\"qca,ar7240-ddr-controller\";\n\t\t\t\treg = <0x18000000 0x12c>;\n\n\t\t\t\t#qca,ddr-wb-channel-cells = <1>;\n\t\t\t};\n\n\t\t\tuart: uart@18020000 {\n\t\t\t\tcompatible = \"ns16550a\";\n\t\t\t\treg = <0x18020000 0x2c>;\n\n\t\t\t\tinterrupts = <3>;\n\n\t\t\t\tclocks = <&pll ATH79_CLK_REF>;\n\t\t\t\tclock-names = \"uart\";\n\n\t\t\t\treg-io-width = <4>;\n\t\t\t\treg-shift = <2>;\n\t\t\t\tno-loopback-test;\n\t\t\t};\n\n\t\t\tgpio: gpio@18040000 {\n\t\t\t\tcompatible = \"qca,ar9340-gpio\";\n\t\t\t\treg = <0x18040000 0x28>;\n\n\t\t\t\tinterrupts = <2>;\n\t\t\t\tngpios = <23>;\n\n\t\t\t\tgpio-controller;\n\t\t\t\t#gpio-cells = <2>;\n\n\t\t\t\tinterrupt-controller;\n\t\t\t\t#interrupt-cells = <2>;\n\t\t\t};\n\n\t\t\tpinmux: pinmux@1804002c {\n\t\t\t\tcompatible = \"pinctrl-single\";\n\n\t\t\t\treg = <0x1804002c 0x44>;\n\n\t\t\t\t#size-cells = <0>;\n\n\t\t\t\tpinctrl-single,bit-per-mux;\n\t\t\t\tpinctrl-single,register-width = <32>;\n\t\t\t\tpinctrl-single,function-mask = <0x1>;\n\t\t\t\t#pinctrl-cells = <2>;\n\n\t\t\t\tjtag_disable_pins: pinmux_jtag_disable_pins {\n\t\t\t\t\tpinctrl-single,bits = <0x40 0x2 0x2>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tpll: pll-controller@18050000 {\n\t\t\t\tcompatible = \"qca,ar9340-pll\", \"syscon\";\n\t\t\t\treg = <0x18050000 0x4c>;\n\n\t\t\t\t#clock-cells = <1>;\n\t\t\t\tclocks = <&ref>;\n\t\t\t\tclock-names = \"ref\";\n\t\t\t\tclock-output-names = \"cpu\", \"ddr\", \"ahb\";\n\t\t\t};\n\n\t\t\twdt: wdt@18060008 {\n\t\t\t\tcompatible = \"qca,ar9340-wdt\", \"qca,ar7130-wdt\";\n\t\t\t\treg = <0x18060008 0x8>;\n\n\t\t\t\tinterrupts = <4>;\n\n\t\t\t\tclocks = <&pll ATH79_CLK_AHB>;\n\t\t\t\tclock-names = \"wdt\";\n\t\t\t};\n\n\t\t\trst: reset-controller@1806001c {\n\t\t\t\tcompatible = \"qca,ar9340-reset\", \"qca,ar7100-reset\";\n\t\t\t\treg = <0x1806001c 0x4>;\n\n\t\t\t\t#reset-cells = <1>;\n\t\t\t};\n\n\t\t\ths_uart: uart@18500000 {\n\t\t\t\tcompatible = \"qca,ar9330-uart\";\n\t\t\t\treg = <0x18500000 0x14>;\n\n\t\t\t\tinterrupts = <6>;\n\t\t\t\tinterrupt-parent = <&miscintc>;\n\n\t\t\t\tclocks = <&pll ATH79_CLK_UART1>;\n\t\t\t\tclock-names = \"uart\";\n\n\t\t\t\tstatus = \"disabled\";\n\t\t\t};\n\t\t};\n\n\t\tgmac: gmac@18070000 {\n\t\t\tcompatible = \"qca,ar9340-gmac\";\n\t\t\treg = <0x18070000 0x14>;\n\t\t};\n\n\t\twmac: wmac@18100000 {\n\t\t\tcompatible = \"qca,ar9340-wmac\";\n\t\t\treg = <0x18100000 0x20000>;\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tusb: usb@1b000000 {\n\t\t\tcompatible = \"generic-ehci\";\n\t\t\treg = <0x1b000000 0x1d8>;\n\n\t\t\tinterrupts = <3>;\n\t\t\tresets = <&rst 5>;\n\t\t\treset-names = \"usb-host\";\n\n\t\t\thas-transaction-translator;\n\t\t\tcaps-offset = <0x100>;\n\n\t\t\tphy-names = \"usb-phy\";\n\t\t\tphys = <&usb_phy>;\n\n\t\t\tstatus = \"disabled\";\n\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tnand: nand@1b000200 {\n\t\t\tcompatible = \"qca,ar934x-nand\";\n\t\t\treg = <0x1b000200 0xb8>;\n\n\t\t\tinterrupts = <21>;\n\t\t\tinterrupt-parent = <&miscintc>;\n\n\t\t\tresets = <&rst 14>;\n\t\t\treset-names = \"nand\";\n\n\t\t\tnand-ecc-mode = \"hw\";\n\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tspi: spi@1f000000 {\n\t\t\tcompatible = \"qca,ar934x-spi\";\n\t\t\treg = <0x1f000000 0x1c>;\n\n\t\t\tclocks = <&pll ATH79_CLK_AHB>;\n\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\t};\n\n\tusb_phy: usb-phy {\n\t\tcompatible = \"qca,ar9340-usb-phy\", \"qca,ar7200-usb-phy\";\n\n\t\treset-names = \"usb-phy-analog\", \"usb-phy\", \"usb-suspend-override\";\n\t\tresets = <&rst 11>, <&rst 4>, <&rst 3>;\n\n\t\t#phy-cells = <0>;\n\n\t\tstatus = \"disabled\";\n\t};\n};\n\n&mdio0 {\n\tcompatible = \"qca,ar9340-mdio\";\n};\n\n&eth0 {\n\tcompatible = \"qca,ar9340-eth\", \"syscon\";\n\n\tpll-data = <0x16000000 0x00000101 0x00001616>;\n\tpll-reg = <0x4 0x2c 17>;\n\tpll-handle = <&pll>;\n\tresets = <&rst 9>, <&rst 22>;\n\treset-names = \"mac\", \"mdio\";\n\tclocks = <&pll ATH79_CLK_AHB>, <&pll ATH79_CLK_AHB>;\n\tclock-names = \"eth\", \"mdio\";\n};\n\n&mdio1 {\n\tstatus = \"okay\";\n\n\tcompatible = \"qca,ar9340-mdio\";\n\tresets = <&rst 23>;\n\treset-names = \"mdio\";\n\tbuiltin-switch;\n\n\tbuiltin_switch: switch0@1f {\n\t\tcompatible = \"qca,ar8229\";\n\n\t\treg = <0x1f>;\n\t\tresets = <&rst 8>;\n\t\treset-names = \"switch\";\n\t\tphy-mode = \"gmii\";\n\t\tqca,mib-poll-interval = <500>;\n\t\tqca,phy4-mii-enable;\n\n\t\tmdio-bus {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\n\t\t\tswphy0: ethernet-phy@0 {\n\t\t\t\treg = <0>;\n\t\t\t\tphy-mode = \"mii\";\n\t\t\t};\n\n\t\t\tswphy4: ethernet-phy@4 {\n\t\t\t\treg = <4>;\n\t\t\t\tphy-mode = \"mii\";\n\t\t\t};\n\t\t};\n\t};\n};\n\n&eth1 {\n\tcompatible = \"qca,ar9340-eth\", \"syscon\";\n\n\tresets = <&rst 13>;\n\treset-names = \"mac\";\n\tclocks = <&pll ATH79_CLK_AHB>, <&pll ATH79_CLK_AHB>;\n\tclock-names = \"eth\", \"mdio\";\n\tphy-mode = \"gmii\";\n\n\tfixed-link {\n\t\tspeed = <1000>;\n\t\tfull-duplex;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ar934x_senao_loader.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include <dt-bindings/mtd/partitions/uimage.h>\n\n/ {\n\tvirtual_flash {\n\t\tcompatible = \"mtd-concat\";\n\n\t\tdevices = <&fwconcat0 &fwconcat1>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tcompatible = \"openwrt,uimage\", \"denx,uimage\";\n\t\t\t\topenwrt,ih-magic = <0x73714f4b>;\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x0 0x0>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&ref {\n\tclock-frequency = <40000000>;\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <40000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x040000 0x010000>;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tlabel = \"custom\";\n\t\t\t\treg = <0x050000 0x050000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@a0000 {\n\t\t\t\tlabel = \"loader\";\n\t\t\t\treg = <0x0a0000 0x010000>;\n\t\t\t};\n\n\t\t\tfwconcat1: partition@b0000 {\n\t\t\t\tlabel = \"fwconcat1\";\n\t\t\t\treg = <0x0b0000 0x170000>;\n\t\t\t};\n\n\t\t\tfwconcat0: partition@220000 {\n\t\t\t\tlabel = \"fwconcat0\";\n\t\t\t\treg = <0x220000 0xbd0000>;\n\t\t\t};\n\n\t\t\tpartition@df0000 {\n\t\t\t\tlabel = \"failsafe\";\n\t\t\t\treg = <0xdf0000 0x200000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tart: partition@ff0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0xff0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/ath79.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n/dts-v1/;\n\n#include <dt-bindings/clock/ath79-clk.h>\n\n/ {\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tcpuintc: interrupt-controller {\n\t\tcompatible = \"qca,ar7100-cpu-intc\";\n\n\t\tinterrupt-controller;\n\t\t#interrupt-cells = <1>;\n\t};\n\n\tahb {\n\t\tcompatible = \"simple-bus\";\n\t\tranges;\n\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tinterrupt-parent = <&cpuintc>;\n\n\t\tapb {\n\t\t\tcompatible = \"simple-bus\";\n\t\t\tranges;\n\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tinterrupt-parent = <&miscintc>;\n\n\t\t\tmiscintc: interrupt-controller@18060010 {\n\t\t\t\tcompatible = \"qca,ar7240-misc-intc\";\n\t\t\t\treg = <0x18060010 0x4>;\n\n\t\t\t\tinterrupt-parent = <&cpuintc>;\n\t\t\t\tinterrupts = <6>;\n\n\t\t\t\tinterrupt-controller;\n\t\t\t\t#interrupt-cells = <1>;\n\t\t\t};\n\t\t};\n\n\t\teth0: eth@19000000 {\n\t\t\tstatus = \"disabled\";\n\n\t\t\tcompatible = \"qca,ath79-eth\", \"syscon\";\n\t\t\treg = <0x19000000 0x200>;\n\n\t\t\tinterrupts = <4>;\n\t\t\tphy-mode = \"mii\";\n\n\t\t\tmdio0: mdio {\n\t\t\t\tstatus = \"disabled\";\n\n\t\t\t\tcompatible = \"qca,ath79-mdio\";\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\n\t\t\t\tregmap = <&eth0>;\n\n\t\t\t\tclocks = <&pll ATH79_CLK_MDIO>;\n\t\t\t\tclock-names = \"ref\";\n\t\t\t};\n\t\t};\n\n\t\teth1: eth@1a000000 {\n\t\t\tstatus = \"disabled\";\n\n\t\t\tcompatible = \"qca,ath79-eth\", \"syscon\";\n\t\t\treg = <0x1a000000 0x200>;\n\n\t\t\tinterrupts = <5>;\n\t\t\tphy-mode = \"mii\";\n\n\t\t\tmdio1: mdio {\n\t\t\t\tstatus = \"disabled\";\n\n\t\t\t\tcompatible = \"qca,ath79-mdio\";\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\n\t\t\t\tregmap = <&eth1>;\n\n\t\t\t\tclocks = <&pll ATH79_CLK_MDIO>;\n\t\t\t\tclock-names = \"ref\";\n\t\t\t};\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9531_8dev_lima.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca953x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"8dev,lima\", \"qca,qca9531\";\n\tmodel = \"8devices Lima\";\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&pcie0 {\n\tstatus = \"okay\";\n};\n\n&usb0 {\n\tstatus = \"okay\";\n\n\tdr_mode = \"host\";\n};\n\n&usb_phy {\n\tstatus = \"okay\";\n};\n\n&wdt {\n\tstatus = \"okay\";\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\t/* Winbond W25Q256 SPI flash */\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <45000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x040000 0x040000>;\n\t\t\t};\n\n\t\t\tart: partition@80000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0x080000 0x040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@c0000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x0c0000 0xf40000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tphy-handle = <&swphy0>;\n\n\tnvmem-cells = <&macaddr_art_6>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tgmac-config {\n\t\tdevice = <&gmac>;\n\n\t\tswitch-phy-addr-swap = <1>;\n\t\tswitch-phy-swap = <1>;\n\t};\n};\n\n&eth1 {\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n\n\tmacaddr_art_6: macaddr@6 {\n\t\treg = <0x6 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9531_alfa-network_n2q.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9531_alfa-network_r36a.dtsi\"\n\n/ {\n\tmodel = \"ALFA Network N2Q\";\n\tcompatible = \"alfa-network,n2q\", \"qca,qca9531\";\n\n\taliases {\n\t\tled-boot = &led_usb;\n\t\tled-failsafe = &led_usb;\n\t\tled-upgrade = &led_usb;\n\t};\n\n\tgpio-export-pcf8574 {\n\t\tcompatible = \"gpio-export\";\n\t\t#size-cells = <0>;\n\n\t\tpoe-passthrough {\n\t\t\tgpio-export,name = \"poe-passthrough\";\n\t\t\tgpio-export,output = <1>;\n\t\t\tgpios = <&pcf8574 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tusb-power {\n\t\t\tgpio-export,name = \"usb-power\";\n\t\t\tgpio-export,output = <0>;\n\t\t\tgpios = <&pcf8574 2 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\ti2c {\n\t\tcompatible = \"i2c-gpio\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tsda-gpios = <&gpio 11 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\t\tscl-gpios = <&gpio  3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\n\t\tpcf8574: pcf8574@20 {\n\t\t\tcompatible = \"nxp,pcf8574\";\n\t\t\treg = <0x20>;\n\t\t\tgpio-controller;\n\t\t\t#gpio-cells = <2>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tpinctrl-names = \"default\";\n\t\tpinctrl-0 = <&enable_gpio4 &enable_gpio16>;\n\n\t\tlan1 {\n\t\t\tlabel = \"orange:lan1\";\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan2 {\n\t\t\tlabel = \"orange:lan2\";\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_usb: usb {\n\t\t\tlabel = \"green:usb\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t\ttrigger-sources = <&hub_port0>;\n\t\t};\n\n\t\tminipcie {\n\t\t\tlabel = \"green:minipcie\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan {\n\t\t\tlabel = \"green:wlan\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\t};\n\n\tleds-pcf8574 {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tpoe-passthrough {\n\t\t\tlabel = \"green:poe-passthrough\";\n\t\t\tgpios = <&pcf8574 1 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tsignal1 {\n\t\t\tlabel = \"red:signal1\";\n\t\t\tgpios = <&pcf8574 3 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tsignal2 {\n\t\t\tlabel = \"orange:signal2\";\n\t\t\tgpios = <&pcf8574 4 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tsignal3 {\n\t\t\tlabel = \"green:signal3\";\n\t\t\tgpios = <&pcf8574 5 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&eth0 {\n\tnvmem-cells = <&macaddr_art_1002>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <(-2)>;\n};\n\n&eth1 {\n\tnvmem-cells = <&macaddr_art_1002>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <(-1)>;\n};\n\n&pcie0 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9531_alfa-network_pi-wifi4.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9531_alfa-network_r36a.dtsi\"\n\n/ {\n\tmodel = \"ALFA Network Pi-WiFi4\";\n\tcompatible = \"alfa-network,pi-wifi4\", \"qca,qca9531\";\n\n\taliases {\n\t\tled-boot = &led_usb;\n\t\tled-failsafe = &led_usb;\n\t\tled-upgrade = &led_usb;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tpinctrl-names = \"default\";\n\t\tpinctrl-0 = <&enable_gpio4 &enable_gpio16>;\n\n\t\tlan_data {\n\t\t\tlabel = \"orange:lan_data\";\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan_link {\n\t\t\tlabel = \"green:lan_link\";\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_usb: usb {\n\t\t\tlabel = \"green:usb\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t\ttrigger-sources = <&gl850g_port1>, <&gl850g_port2>,\n\t\t\t\t\t  <&gl850g_port3>, <&gl850g_port4>;\n\t\t};\n\n\t\twlan {\n\t\t\tlabel = \"blue:wlan\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\t};\n};\n\n&eth0 {\n\tnvmem-cells = <&macaddr_art_1002>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <(-1)>;\n};\n\n&eth1 {\n\tcompatible = \"syscon\", \"simple-mfd\";\n};\n\n&gpio_export {\n\tusb-power {\n\t\tgpio-export,name = \"usb-power\";\n\t\tgpio-export,output = <1>;\n\t\tgpios = <&gpio 3 GPIO_ACTIVE_HIGH>;\n\t};\n};\n\n&hub_port0 {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\n\tgl850g_port1: port@1 {\n\t\treg = <1>;\n\t\t#trigger-source-cells = <0>;\n\t};\n\n\tgl850g_port2: port@2 {\n\t\treg = <2>;\n\t\t#trigger-source-cells = <0>;\n\t};\n\n\tgl850g_port3: port@3 {\n\t\treg = <3>;\n\t\t#trigger-source-cells = <0>;\n\t};\n\n\tgl850g_port4: port@4 {\n\t\treg = <4>;\n\t\t#trigger-source-cells = <0>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9531_alfa-network_r36a.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9531_alfa-network_r36a.dtsi\"\n\n/ {\n\tmodel = \"ALFA Network R36A\";\n\tcompatible = \"alfa-network,r36a\", \"qca,qca9531\";\n\n\taliases {\n\t\tled-boot = &led_status;\n\t\tled-failsafe = &led_status;\n\t\tled-running = &led_status;\n\t\tled-upgrade = &led_status;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tpinctrl-names = \"default\";\n\t\tpinctrl-0 = <&enable_gpio4 &enable_gpio16>;\n\n\t\tlan {\n\t\t\tlabel = \"blue:lan\";\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_status: status {\n\t\t\tlabel = \"blue:status\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tusb {\n\t\t\tlabel = \"blue:usb\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t\ttrigger-sources = <&hub_port0>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\n\t\twan {\n\t\t\tlabel = \"blue:wan\";\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan {\n\t\t\tlabel = \"blue:wlan\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\t};\n};\n\n&eth0 {\n\tnvmem-cells = <&macaddr_art_1002>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <(-2)>;\n};\n\n&eth1 {\n\t/* Workaround: keep the Ethernet interfaces order/mapping correct\n\t * (GMAC0 -> eth0, GMAC1 -> eth1, same as in old ar71xx target) */\n\tcompatible = \"qca,qca9530-eth\", \"syscon\", \"simple-mfd\";\n\n\tnvmem-cells = <&macaddr_art_1002>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <(-1)>;\n};\n\n&gpio_export {\n\tusb-power {\n\t\tgpio-export,name = \"usb-power\";\n\t\tgpio-export,output = <1>;\n\t\tgpios = <&gpio 3 GPIO_ACTIVE_HIGH>;\n\t};\n};\n\n&keys {\n\trfkill {\n\t\tlabel = \"rfkill\";\n\t\tlinux,code = <KEY_RFKILL>;\n\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\tdebounce-interval = <60>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9531_alfa-network_r36a.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca953x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\taliases {\n\t\tlabel-mac-device = &wmac;\n\t};\n\n\tgpio_export: gpio-export {\n\t\tcompatible = \"gpio-export\";\n\t\t#size-cells = <0>;\n\n\t\twatchdog-enable {\n\t\t\tgpio-export,name = \"watchdog-enable\";\n\t\t\tgpio-export,output = <1>;\n\t\t\tgpios = <&gpio 1 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n\n\tkeys: keys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 2 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\twatchdog {\n\t\tcompatible = \"linux,wdt-gpio\";\n\t\tgpios = <&gpio 0 GPIO_ACTIVE_HIGH>;\n\t\thw_algo = \"toggle\";\n\t\thw_margin_ms = <25000>;\n\t\talways-running;\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tphy-handle = <&swphy4>;\n};\n\n&pinmux {\n\tenable_gpio4: pinmux_enable_gpio4 {\n\t\tpinctrl-single,bits = <0x04 0x0 0xff>;\n\t};\n\n\tenable_gpio16: pinmux_enable_gpio16 {\n\t\tpinctrl-single,bits = <0x10 0x0 0xff>;\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <50000000>;\n\t\tm25p,fast-read;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x060000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@60000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x060000 0x010000>;\n\t\t\t};\n\n\t\t\tpartition@70000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0x070000 0x010000>;\n\t\t\t\tread-only;\n\n\t\t\t\tcompatible = \"nvmem-cells\";\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\n\t\t\t\tcal_art_1000: cal@1000 {\n\t\t\t\t\treg = <0x1000 0x440>;\n\t\t\t\t};\n\n\t\t\t\tmacaddr_art_1002: macaddr@1002 {\n\t\t\t\t\treg = <0x1002 0x6>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tpartition@80000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x080000 0xf80000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&usb0 {\n\tstatus = \"okay\";\n\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\n\thub_port0: port@1 {\n\t\treg = <1>;\n\t\t#trigger-source-cells = <0>;\n\t};\n};\n\n&usb_phy {\n\tstatus = \"okay\";\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tnvmem-cells = <&cal_art_1000>, <&macaddr_art_1002>;\n\tnvmem-cell-names = \"calibration\", \"mac-address\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9531_alfa-network_tube-2hq.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9531_alfa-network_r36a.dtsi\"\n\n/ {\n\tmodel = \"ALFA Network Tube-2HQ\";\n\tcompatible = \"alfa-network,tube-2hq\", \"qca,qca9531\";\n\n\taliases {\n\t\tled-boot = &led_signal4;\n\t\tled-failsafe = &led_signal4;\n\t\tled-upgrade = &led_signal4;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tpinctrl-names = \"default\";\n\t\tpinctrl-0 = <&enable_gpio4 &enable_gpio16>;\n\n\t\tlan {\n\t\t\tlabel = \"blue:lan\";\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_signal4: signal4 {\n\t\t\tlabel = \"green:signal4\";\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tsignal1 {\n\t\t\tlabel = \"red:signal1\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tsignal2 {\n\t\t\tlabel = \"orange:signal2\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tsignal3 {\n\t\t\tlabel = \"green:signal3\";\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&eth0 {\n\tnvmem-cells = <&macaddr_art_1002>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tmac-address-increment = <(-1)>;\n};\n\n&eth1 {\n\tcompatible = \"syscon\", \"simple-mfd\";\n};\n\n&usb0 {\n\tstatus = \"disabled\";\n};\n\n&usb_phy {\n\tstatus = \"disabled\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9531_comfast_cf-e130n-v2.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca953x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"comfast,cf-e130n-v2\", \"qca,qca9531\";\n\tmodel = \"COMFAST CF-E130N v2\";\n\n\taliases {\n\t\tserial0 = &uart;\n\t\tled-boot = &led_rssihigh;\n\t\tled-failsafe = &led_rssihigh;\n\t\tled-upgrade = &led_rssihigh;\n\t\tlabel-mac-device = &eth1;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tpinctrl-names = \"default\";\n\n\t\twlan {\n\t\t\tlabel = \"green:wlan\";\n\t\t\tgpios = <&gpio 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\tlan {\n\t\t\tlabel = \"green:lan\";\n\t\t\tgpios = <&gpio 2 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tunused {\n\t\t\tlabel = \"green:unused\";\n\t\t\tgpios = <&gpio 3 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\trssilow {\n\t\t\tlabel = \"red:rssilow\";\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\trssimediumlow {\n\t\t\tlabel = \"red:rssimediumlow\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\trssimediumhigh {\n\t\t\tlabel = \"green:rssimediumhigh\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_rssihigh: rssihigh {\n\t\t\tlabel = \"green:rssihigh\";\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tart: partition@10000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0x010000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x020000 0x7c0000>;\n\t\t\t};\n\n\t\t\tpartition@7e0000 {\n\t\t\t\tlabel = \"configs\";\n\t\t\t\treg = <0x7e0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@7f0000 {\n\t\t\t\tlabel = \"nvram\";\n\t\t\t\treg = <0x7f0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&eth1 {\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tgmac-config {\n\t\tdevice = <&gmac>;\n\t\tswitch-phy-swap = <1>;\n\t};\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n\tmtd-cal-data = <&art 0x1000>;\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9531_comfast_cf-e313ac.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca953x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"comfast,cf-e313ac\", \"qca,qca9531\";\n\tmodel = \"COMFAST CF-E313AC\";\n\n\taliases {\n\t\tserial0 = &uart;\n\t\tled-boot = &led_rssihigh;\n\t\tled-failsafe = &led_rssihigh;\n\t\tled-upgrade = &led_rssihigh;\n\t\tlabel-mac-device = &eth1;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tpinctrl-names = \"default\";\n\n\t\twlan {\n\t\t\tlabel = \"green:wlan\";\n\t\t\tgpios = <&gpio 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\tlan {\n\t\t\tlabel = \"green:lan\";\n\t\t\tgpios = <&gpio 2 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twan {\n\t\t\tlabel = \"green:wan\";\n\t\t\tgpios = <&gpio 3 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\trssilow {\n\t\t\tlabel = \"red:rssilow\";\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\trssimediumlow {\n\t\t\tlabel = \"red:rssimediumlow\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\trssimediumhigh {\n\t\t\tlabel = \"green:rssimediumhigh\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_rssihigh: rssihigh {\n\t\t\tlabel = \"green:rssihigh\";\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tart: partition@10000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0x010000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x020000 0x7c0000>;\n\t\t\t};\n\n\t\t\tpartition@7e0000 {\n\t\t\t\tlabel = \"config\";\n\t\t\t\treg = <0x7e0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@7f0000 {\n\t\t\t\tlabel = \"nvram\";\n\t\t\t\treg = <0x7f0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tphy-handle = <&swphy0>;\n\n\tnvmem-cells = <&macaddr_art_1002>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tgmac-config {\n\t\tdevice = <&gmac>;\n\t\tswitch-phy-swap = <1>;\n\t};\n};\n\n&eth1 {\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&pcie0 {\n\tstatus = \"okay\";\n\n\twifi@0,0 {\n\t\tcompatible = \"qcom,ath10k\";\n\t\treg = <0 0 0 0 0>;\n\t};\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n\n\tmacaddr_art_1002: macaddr@1002 {\n\t\treg = <0x1002 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9531_comfast_cf-e314n-v2.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca953x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"comfast,cf-e314n-v2\", \"qca,qca9531\";\n\tmodel = \"COMFAST CF-E314N v2\";\n\n\taliases {\n\t\tserial0 = &uart;\n\t\tled-boot = &led_rssihigh;\n\t\tled-failsafe = &led_rssihigh;\n\t\tled-upgrade = &led_rssihigh;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tpinctrl-names = \"default\";\n\t\tpinctrl-0 = <&jtag_disable_pins &led_rssilow_pin &led_rssimediumhigh_pin &led_rssihigh_pin>;\n\n\t\twan {\n\t\t\tlabel = \"green:wan\";\n\t\t\tgpios = <&gpio 3 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan {\n\t\t\tlabel = \"green:lan\";\n\t\t\tgpios = <&gpio 2 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\trssilow {\n\t\t\tlabel = \"red:signal1\";\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\trssimediumlow {\n\t\t\tlabel = \"red:signal2\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\trssimediumhigh {\n\t\t\tlabel = \"green:signal3\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_rssihigh: rssihigh {\n\t\t\tlabel = \"green:signal4\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan {\n\t\t\tlabel = \"green:wlan\";\n\t\t\tgpios = <&gpio 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n};\n\n&pinmux {\n\tled_rssilow_pin: pinmux_rssilow_pin {\n\t\tpinctrl-single,bits = <0x8 0x0 0xff000000>;\n\t};\n\n\tled_rssimediumhigh_pin: pinmux_rssimediumhigh_pin {\n\t\tpinctrl-single,bits = <0xc 0x0 0x00ff0000>;\n\t};\n\n\tled_rssihigh_pin: pinmux_rssihigh_pin {\n\t\tpinctrl-single,bits = <0x10 0x0 0x000000ff>;\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tart: partition@10000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0x010000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x020000 0x7c0000>;\n\t\t\t};\n\n\t\t\tpartition@7e0000 {\n\t\t\t\tlabel = \"configs\";\n\t\t\t\treg = <0x7e0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@7f0000 {\n\t\t\t\tlabel = \"nvram\";\n\t\t\t\treg = <0x7f0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tphy-handle = <&swphy4>;\n\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&eth1 {\n\tnvmem-cells = <&macaddr_art_6>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wmac {\n\tstatus = \"okay\";\n\tmtd-cal-data = <&art 0x1000>;\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n\n\tmacaddr_art_6: macaddr@6 {\n\t\treg = <0x6 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9531_comfast_cf-e5.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca953x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"comfast,cf-e5\", \"qca,qca9531\";\n\tmodel = \"COMFAST CF-E5/E7\";\n\n\taliases {\n\t\tlabel-mac-device = &eth0;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tpinctrl-names = \"default\";\n\t\tpinctrl-0 = <&jtag_disable_pins &led_wan_pin>;\n\n\t\twan {\n\t\t\tlabel = \"blue:wan\";\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan {\n\t\t\tlabel = \"blue:lan\";\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan {\n\t\t\tlabel = \"blue:wlan\";\n\t\t\tgpios = <&gpio 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\trssi0 {\n\t\t\tlabel = \"blue:rssi0\";\n\t\t\tgpios = <&gpio 2 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\trssi1 {\n\t\t\tlabel = \"blue:rssi1\";\n\t\t\tgpios = <&gpio 3 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\trssi2 {\n\t\t\tlabel = \"blue:rssi2\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&usb0 {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\tstatus = \"okay\";\n\n\thub_port: port@1 {\n\t\treg = <1>;\n\t\t#trigger-source-cells = <0>;\n\t};\n};\n\n&usb_phy {\n\tstatus = \"okay\";\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tart: partition@10000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0x010000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x020000 0xfd0000>;\n\t\t\t};\n\n\t\t\tpartition@ff0000 {\n\t\t\t\tlabel = \"art-backup\";\n\t\t\t\treg = <0xff0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tphy-handle = <&swphy4>;\n\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&eth1 {\n\tnvmem-cells = <&macaddr_art_6>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n};\n\n&pinmux {\n\tled_wan_pin: pinmux_led_wan_pin {\n\t\tpinctrl-single,bits = <0x4 0x0 0xff>;\n\t};\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n\n\tmacaddr_art_6: macaddr@6 {\n\t\treg = <0x6 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9531_comfast_cf-e560ac.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca953x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"comfast,cf-e560ac\", \"qca,qca9531\";\n\tmodel = \"COMFAST CF-E560AC\";\n\n\taliases {\n\t\tserial0 = &uart;\n\t\tlabel-mac-device = &eth1;\n\t\tled-boot = &led_system;\n\t\tled-failsafe = &led_system;\n\t\tled-upgrade = &led_system;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tpinctrl-names = \"default\";\n\t\tpinctrl-0 = <&jtag_disable_pins>;\n\n\t\tlan1 {\n\t\t\tlabel = \"blue:lan1\";\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan2 {\n\t\t\tlabel = \"blue:lan2\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan3 {\n\t\t\tlabel = \"blue:lan3\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan4 {\n\t\t\tlabel = \"blue:lan4\";\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_system: system {\n\t\t\tlabel = \"blue:system\";\n\t\t\tgpios = <&gpio 3 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twan {\n\t\t\tlabel = \"blue:wan\";\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan {\n\t\t\tlabel = \"blue:wlan\";\n\t\t\tgpios = <&gpio 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\t};\n\n\twatchdog {\n\t\tcompatible = \"linux,wdt-gpio\";\n\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\thw_algo = \"toggle\";\n\t\thw_margin_ms = <1200>;\n\t\talways-running;\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tart: partition@10000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0x010000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x020000 0xfc0000>;\n\t\t\t};\n\n\t\t\tpartition@fe0000 {\n\t\t\t\tlabel = \"configs\";\n\t\t\t\treg = <0xfe0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@ff0000 {\n\t\t\t\tlabel = \"nvram\";\n\t\t\t\treg = <0xff0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pcie0 {\n\tstatus = \"okay\";\n};\n\n&usb_phy {\n\tstatus = \"okay\";\n};\n\n&usb0 {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\tstatus = \"okay\";\n\n\tport@1 {\n\t\treg = <1>;\n\t\t#trigger-source-cells = <0>;\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tphy-handle = <&swphy4>;\n\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <1>;\n};\n\n&eth1 {\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <10>;\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9531_comfast_cf-ew72.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca953x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"comfast,cf-ew72\", \"qca,qca9531\";\n\tmodel = \"COMFAST CF-EW72\";\n\n\taliases {\n\t\tserial0 = &uart;\n\t\tled-boot = &led_wan;\n\t\tled-failsafe = &led_wan;\n\t\tled-upgrade = &led_wan;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tpinctrl-names = \"default\";\n\t\tpinctrl-0 = <&jtag_disable_pins>;\n\n\t\tlan {\n\t\t\tlabel = \"blue:lan\";\n\t\t\tgpios = <&gpio 2 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_wan: wan {\n\t\t\tlabel = \"blue:wan\";\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan {\n\t\t\tlabel = \"blue:wlan\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\twatchdog {\n\t\tcompatible = \"linux,wdt-gpio\";\n\n\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\thw_algo = \"toggle\";\n\t\thw_margin_ms = <1200>;\n\t\talways-running;\n\t};\n};\n\n&pcie0 {\n\tstatus = \"okay\";\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"winbond,w25q128\", \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tart: partition@10000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0x010000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x020000 0xfd0000>;\n\t\t\t};\n\n\t\t\tpartition@ff0000 {\n\t\t\t\tlabel = \"nvram\";\n\t\t\t\treg = <0xff0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tphy-handle = <&swphy4>;\n\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <1>;\n};\n\n&eth1 {\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <3>;\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9531_comfast_cf-wr752ac-v1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca953x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"comfast,cf-wr752ac-v1\", \"qca,qca9531\";\n\tmodel = \"COMFAST CF-WR752AC v1\";\n\n\taliases {\n\t\tserial0 = &uart;\n\t\tled-boot = &led_lan;\n\t\tled-failsafe = &led_lan;\n\t\tled-upgrade = &led_lan;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tpinctrl-names = \"default\";\n\t\tpinctrl-0 = <&jtag_disable_pins &pinmux_led_rssihigh &pinmux_led_rssilow>;\n\n\t\tled_lan: lan {\n\t\t\tlabel = \"blue:lan\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\trssihigh {\n\t\t\tlabel = \"green:rssihigh\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\trssilow {\n\t\t\tlabel = \"red:rssilow\";\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\tbutton {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n};\n\n&pinmux {\n\tpinmux_led_rssihigh: pinmux_led_rssihigh {\n\t\tpinctrl-single,bits = <0xc 0x0 0xff000000>;\n\t};\n\n\tpinmux_led_rssilow: pinmux_led_rssilow {\n\t\tpinctrl-single,bits = <0x8 0x0 0xff000000>;\n\t};\n};\n\n&pcie0 {\n\tstatus = \"okay\";\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tart: partition@10000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0x010000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x020000 0xfd0000>;\n\t\t\t};\n\n\t\t\tpartition@ff0000 {\n\t\t\t\tlabel = \"nvram\";\n\t\t\t\treg = <0xff0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tphy-handle = <&swphy4>;\n\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&eth1 {\n\tcompatible = \"syscon\", \"simple-mfd\";\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <10>;\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9531_compex_wpj531-16m.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca953x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"compex,wpj531-16m\", \"qca,qca9531\";\n\tmodel = \"Compex WPJ531 (16MB flash)\";\n\n\taliases {\n\t\tlabel-mac-device = &eth0;\n\t\tled-boot = &led_sig4;\n\t\tled-failsafe = &led_sig4;\n\t\tled-running = &led_sig4;\n\t\tled-upgrade = &led_sig4;\n\t};\n\n\tbeeper {\n\t\tcompatible = \"gpio-beeper\";\n\t\tgpios = <&gpio 4 GPIO_ACTIVE_HIGH>;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tpinctrl-names = \"default\";\n\t\tpinctrl-0 = <&pinmux_led_eth_pins>;\n\n\t\tsig1 {\n\t\t\tlabel = \"red:sig1\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tsig2 {\n\t\t\tlabel = \"yellow:sig2\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tsig3 {\n\t\t\tlabel = \"green:sig3\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_sig4: sig4 {\n\t\t\tlabel = \"green:sig4\";\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&pinmux {\n\tpinmux_led_eth_pins: pinmux_led_eth_pins {\n\t\tpinctrl-single,bits = <0x8 0x2b000000 0xff000000>, <0xc 0x00002d00 0x0000ff00>;\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tuboot: partition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x030000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x030000 0xfc0000>;\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t};\n\n\t\t\tart: partition@ff0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0xff0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tphy-handle = <&swphy4>;\n\n\tnvmem-cells = <&macaddr_uboot_2e010>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&eth1 {\n\tnvmem-cells = <&macaddr_uboot_2e018>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n};\n\n&pcie0 {\n\tstatus = \"okay\";\n\n\twifi@0,0 {\n\t\tcompatible = \"pci168c,003c\";\n\t\treg = <0x0000 0 0 0 0>;\n\t};\n};\n\n&usb_phy {\n\tstatus = \"okay\";\n};\n\n&usb0 {\n\tstatus = \"okay\";\n};\n\n&uboot {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_uboot_2e010: macaddr@2e010 {\n\t\treg = <0x2e010 0x6>;\n\t};\n\n\tmacaddr_uboot_2e018: macaddr@2e018 {\n\t\treg = <0x2e018 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9531_dlink_dch-g020-a1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca953x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"dlink,dch-g020-a1\", \"qca,qca9531\";\n\tmodel = \"D-Link DCH-G020 A1\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\ti2c {\n\t\tcompatible = \"i2c-gpio\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tsda-gpios = <&gpio 0 GPIO_ACTIVE_HIGH>;\n\t\tscl-gpios = <&gpio 1 GPIO_ACTIVE_HIGH>;\n\n\t\tgpio_ext: gpio_ext@38 {\n\t\t\tcompatible = \"nxp,pca9554\";\n\t\t\treg = <0x38 0x1>;\n\n\t\t\tgpio-controller;\n\t\t\t#gpio-cells = <2>;\n\t\t};\n\n\t\trtc@30 {\n\t\t\tcompatible = \"pericom,pt7c43390\";\n\t\t\treg = <0x30 0x8>;\n\t\t};\n\t};\n\n\tgpio-export {\n\t\tcompatible = \"gpio-export\";\n\n\t\tusb_power {\n\t\t\tlabel = \"power:usb\";\n\t\t\tgpio-export,name = \"d-link:power:usb\";\n\t\t\tgpio-export,output = <0>;\n\t\t\tgpios = <&gpio_ext 3 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tzwave_power {\n\t\t\tlabel = \"power:zwave\";\n\t\t\tgpio-export,name = \"d-link:power:zwave\";\n\t\t\tgpio-export,output = <0>;\n\t\t\tgpios = <&gpio_ext 1 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tgpios = <&gpio 3 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tstatus {\n\t\t\tlabel = \"red:status\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <50000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tart: partition@10000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0x10000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tlabel = \"mp\";\n\t\t\t\treg = <0x20000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"config\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"bootarg\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0xe70000>;\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t};\n\n\t\t\tpartition@ec0000 {\n\t\t\t\tlabel = \"dlink\";\n\t\t\t\treg = <0xec0000 0x140000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&usb0 {\n\tstatus = \"okay\";\n};\n\n&usb_phy {\n\tstatus = \"okay\";\n};\n\n&eth0 {\n\tstatus = \"okay\";\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9531_engenius_ews511ap.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca953x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"engenius,ews511ap\", \"qca,qca9531\";\n\tmodel = \"EnGenius EWS511AP\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\tpinctrl-names = \"default\";\n\t\tpinctrl-0 = <&jtag_disable_pins>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 1 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"amber:power\";\n\t\t\tgpios = <&gpio 0 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\tlan1 {\n\t\t\tlabel = \"blue:lan1\";\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan2 {\n\t\t\tlabel = \"blue:lan2\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan2g {\n\t\t\tlabel = \"green:wlan2g\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\twlan5g {\n\t\t\tlabel = \"green:wlan5g\";\n\t\t\tgpios = <&gpio 3 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\t};\n\n\twatchdog {\n\t\tcompatible = \"linux,wdt-gpio\";\n\n\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\thw_algo = \"toggle\";\n\t\t/* hw_margin_ms is actually 300s but driver limits it to 60s */\n\t\thw_margin_ms = <60000>;\n\t\talways-running;\n\t};\n};\n\n&wdt {\n\tstatus = \"okay\";\n};\n\n&rst {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\tstatus = \"okay\";\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tubootenv: partition@40000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x040000 0x010000>;\n\t\t\t};\n\n\t\t\tart: partition@50000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0x050000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@60000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x060000 0xfa0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tphy-handle = <&swphy4>;\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9531_glinet_gl-ar300m-lite.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9531_glinet_gl-ar300m.dtsi\"\n\n/ {\n\tcompatible = \"glinet,gl-ar300m-lite\", \"qca,qca9531\";\n\tmodel = \"GL.iNet GL-AR300M-Lite\";\n};\n\n/delete-node/ &reg_usb_vbus;\n\n/delete-node/ &nand_flash;\n\n&nor_firmware {\n\tcompatible = \"denx,uimage\";\n\tlabel = \"firmware\";\n};\n\n// \"Disable\" unpopulated GMAC1\n\n&eth1 {\n\tcompatible = \"syscon\", \"simple-mfd\";\n};\n\n&led_status {\n\tlabel = \"red:status\";\n};\n\n&led_wlan {\n\tlabel = \"green:wlan\";\n};\n\n&usb0 {\n\t/delete-property/ vbus-supply;\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9531_glinet_gl-ar300m-nand.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9531_glinet_gl-ar300m.dtsi\"\n\n/ {\n\tcompatible = \"glinet,gl-ar300m-nand\", \"qca,qca9531\";\n\tmodel = \"GL.iNet GL-AR300M (NAND)\";\n};\n\n&nand_kernel {\n\tlabel = \"kernel\";\n};\n\n&nand_ubi {\n\tlabel = \"ubi\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9531_glinet_gl-ar300m-nor.dts",
    "content": "#include \"qca9531_glinet_gl-ar300m.dtsi\"\n\n/ {\n\tcompatible = \"glinet,gl-ar300m-nor\", \"qca,qca9531\";\n\tmodel = \"GL.iNet GL-AR300M (NOR)\";\n};\n\n&nor_firmware {\n\tcompatible = \"denx,uimage\";\n\tlabel = \"firmware\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9531_glinet_gl-ar300m.dtsi",
    "content": "#include \"qca953x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\taliases {\n\t\tled-boot = &led_status;\n\t\tled-failsafe = &led_status;\n\t\tled-running = &led_status;\n\t\tled-upgrade = &led_status;\n\t\tlabel-mac-device = &eth0;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\tpinctrl-names = \"default\";\n\t\tpinctrl-0 = <&jtag_disable_pins>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 3 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tright {\n\t\t\tlabel = \"button right\";\n\t\t\tlinux,code = <BTN_0>;\n\t\t\tgpios = <&gpio 0 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tleft {\n\t\t\tlabel = \"button left\";\n\t\t\tlinux,code = <BTN_1>;\n\t\t\tgpios = <&gpio 1 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n\n\treg_usb_vbus: reg_usb_vbus {\n\t\tcompatible = \"regulator-fixed\";\n\n\t\tregulator-name = \"usb_vbus\";\n\t\tregulator-min-microvolt = <5000000>;\n\t\tregulator-max-microvolt = <5000000>;\n\t\tgpio = <&gpio 2 GPIO_ACTIVE_HIGH>;\n\t\tenable-active-high;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\t// Colors for non-Lite versions\n\n\t\tled_status: status {\n\t\t\tlabel = \"green:status\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan {\n\t\t\tlabel = \"green:lan\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_wlan: wlan {\n\t\t\tlabel = \"red:wlan\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\t};\n\n\ti2c: i2c {\n\t\tcompatible = \"i2c-gpio\";\n\n\t\tpinctrl-names = \"default\";\n\t\tpinctrl-0 = <&enable_gpio17>;\n\n\t\tsda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;\n\t\tscl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;\n\t};\n};\n\n&pcie0 {\n\tstatus = \"okay\";\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x040000 0x010000>;\n\t\t\t};\n\n\t\t\tnor_firmware: partition@50000 {\n\t\t\t\tlabel = \"nor_firmware\";\n\t\t\t\treg = <0x050000 0xfa0000>;\n\t\t\t};\n\n\t\t\tart: partition@ff0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0xff0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n\n\tnand_flash: flash@1 {\n\t\tcompatible = \"spi-nand\";\n\t\treg = <1>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tnand_kernel: partition@0 {\n\t\t\t\tlabel = \"nand_kernel\";\n\t\t\t\treg = <0x000000 0x400000>;\n\t\t\t};\n\n\t\t\tnand_ubi: partition@400000 {\n\t\t\t\tlabel = \"nand_ubi\";\n\t\t\t\treg = <0x400000 0x7c00000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&usb0 {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\tvbus-supply = <&reg_usb_vbus>;\n\tstatus = \"okay\";\n};\n\n&usb_phy {\n\tstatus = \"okay\";\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tphy-handle = <&swphy4>;\n\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&eth1 {\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <1>;\n};\n\n&wmac {\n\tstatus = \"okay\";\n\tmtd-cal-data = <&art 0x1000>;\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n};\n\n&pinmux {\n\tenable_gpio17: pinmux_enable_gpio17 {\n\t\tpinctrl-single,bits = <0x10 0x0000 0xff00>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9531_glinet_gl-ar300m16.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9531_glinet_gl-ar300m.dtsi\"\n\n/ {\n\tcompatible = \"glinet,gl-ar300m16\", \"qca,qca9531\";\n\tmodel = \"GL.iNet GL-AR300M16\";\n};\n\n/delete-node/ &nand_flash;\n\n&nor_firmware {\n\tcompatible = \"denx,uimage\";\n\tlabel = \"firmware\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9531_glinet_gl-ar750.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca953x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"glinet,gl-ar750\", \"qca,qca9531\";\n\tmodel = \"GL.iNet GL-AR750\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t\tlabel-mac-device = &eth0;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\tpinctrl-names = \"default\";\n\t\tpinctrl-0 = <&jtag_disable_pins>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 3 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tmode {\n\t\t\tlabel = \"mode\";\n\t\t\tlinux,code = <BTN_0>;\n\t\t\tgpios = <&gpio 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"white:power\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\twlan2g {\n\t\t\tlabel = \"white:wlan2g\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\n\t\twlan5g {\n\t\t\tlabel = \"white:wlan5g\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\t};\n\n\ti2c {\n\t\tcompatible = \"i2c-gpio\";\n\n\t\tsda-gpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\tscl-gpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t};\n};\n\n&pcie0 {\n\tstatus = \"okay\";\n\n\twifi@0,0 {\n\t\tcompatible = \"qcom,ath10k\";\n\t\treg = <0 0 0 0 0>;\n\t\tdevice_type = \"pci\";\n\t};\n};\n\n&usb0 {\n\tstatus = \"okay\";\n};\n\n&usb_phy {\n\tstatus = \"okay\";\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x040000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tart: partition@50000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0x050000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@60000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x060000 0xfa0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tphy-handle = <&swphy4>;\n\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&eth1 {\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <1>;\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9531_glinet_gl-e750.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca953x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"glinet,gl-e750\", \"qca,qca9531\";\n\tmodel = \"GL.iNet GL-E750\";\n\n\taliases {\n\t\tlabel-mac-device = &eth0;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\tpinctrl-names = \"default\";\n\t\tpinctrl-0 = <&jtag_disable_pins>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 3 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tswitch {\n\t\t\tlabel = \"switch\";\n\t\t\tlinux,code = <BTN_0>;\n\t\t\tgpios = <&gpio 1 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tgpio-export {\n\t\tcompatible = \"gpio-export\";\n\n\t\tgpio_lte_power {\n\t\t\tgpio-export,name = \"lte_power\";\n\t\t\tgpio-export,output = <1>;\n\t\t\tgpios = <&gpio 0 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t };\n};\n\n&pcie0 {\n\tstatus = \"okay\";\n};\n\n&usb0 {\n\tstatus = \"okay\";\n};\n\n&usb_phy {\n\tstatus = \"okay\";\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x40000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t};\n\n\t\t\tart: partition@50000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0x50000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@60000 {\n\t\t\t\tlabel = \"kernel\";\n\t\t\t\treg = <0x60000 0x400000>;\n\t\t\t};\n\n\t\t\tpartition@460000 {\n\t\t\t\tlabel = \"reserved\";\n\t\t\t\treg = <0x460000 0xba0000>;\n\t\t\t};\n\t\t};\n\t};\n\n\tflash@1 {\n\t\tcompatible = \"spi-nand\";\n\t\treg = <1>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"ubi\";\n\t\t\t\treg = <0x0 0x8000000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tphy-handle = <&swphy4>;\n\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&eth1 {\n\tcompatible = \"syscon\", \"simple-mfd\";\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9531_glinet_gl-x300b.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca953x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"glinet,gl-x300b\", \"qca,qca9531\";\n\tmodel = \"GL.iNet GL-X300B\";\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\tpinctrl-names = \"default\";\n\t\tpinctrl-0 = <&jtag_disable_pins>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 3 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twlan2g {\n\t\t\tlabel = \"green:wlan2g\";\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\twan {\n\t\t\tlabel = \"green:wan\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlte {\n\t\t\tlabel = \"green:lte\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tgpio-export {\n\t\tcompatible = \"gpio-export\";\n\n\t\tminipcie {\n\t\t\tgpio-export,name = \"minipcie\";\n\t\t\tgpio-export,output = <0>;\n\t\t\tgpios = <&gpio 0 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\trs485tx_en {\n\t\t\tgpio-export,name = \"rs485tx_en\";\n\t\t\tgpio-export,output = <0>;\n\t\t\tgpios = <&gpio 1 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tble_rst {\n\t\t\tgpio-export,name = \"ble_rst\";\n\t\t\tgpio-export,output = <0>;\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n\n\twatchdog {\n\t\tcompatible = \"hw_wdt\";\n\t\tdog_en_gpio = <12>;\n\t\tfeed_dog_gpio = <2>;\n\t\tfeed_dog_interval = <100000000>;\n\t};\n};\n\n&usb0 {\n\tstatus = \"okay\";\n};\n\n&usb_phy {\n\tstatus = \"okay\";\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x040000 0x010000>;\n\t\t\t};\n\n\t\t\tart: partition@50000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0x050000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@60000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x060000 0xfa0000>;\n\t\t\t};\n\n\t\t};\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tphy-handle = <&swphy4>;\n};\n\n&eth1 {\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <1>;\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9531_glinet_gl-x750.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca953x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"glinet,gl-x750\", \"qca,qca9531\";\n\tmodel = \"GL.iNet GL-X750\";\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\tpinctrl-names = \"default\";\n\t\tpinctrl-0 = <&jtag_disable_pins>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 3 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tpower {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\twlan2g {\n\t\t\tlabel = \"green:wlan2g\";\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\n\t\twlan5g {\n\t\t\tlabel = \"green:wlan5g\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\twan {\n\t\t\tlabel = \"green:wan\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\t4g {\n\t\t\tlabel = \"green:4g\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&pcie0 {\n\tstatus = \"okay\";\n};\n\n&usb0 {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\tstatus = \"okay\";\n\n\thub_port: port@1 {\n\t\treg = <1>;\n\t\t#trigger-source-cells = <0>;\n\t};\n};\n\n&usb_phy {\n\tstatus = \"okay\";\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x040000 0x010000>;\n\t\t\t};\n\n\t\t\tart: partition@50000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0x050000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@60000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x060000 0xfa0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tphy-handle = <&swphy4>;\n\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&eth1 {\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <1>;\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9531_glinet_gl-xe300.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca953x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"glinet,gl-xe300\", \"qca,qca9531\";\n\tmodel = \"GL.iNet GL-XE300\";\n\n\tgpio-export {\n\t\tcompatible = \"gpio-export\";\n\n\t\tgpio_lte_power {\n\t\t\tgpios = <&gpio 0 GPIO_ACTIVE_HIGH>;\n\t\t\tgpio-export,name = \"lte_power\";\n\t\t\tgpio-export,output = <1>;\n\t\t};\n\n\t\tgpio_sd_detect {\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t\tgpio-export,name = \"sd_detect\";\n\t\t\tgpio-export,output = <0>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\tpinctrl-names = \"default\";\n\t\tpinctrl-0 = <&jtag_disable_pins>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 3 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tlan {\n\t\t\tgpios = <&gpio 10 GPIO_ACTIVE_LOW>;\n\t\t\tlabel = \"green:lan\";\n\t\t};\n\n\t\twan {\n\t\t\tgpios = <&gpio 1 GPIO_ACTIVE_LOW>;\n\t\t\tlabel = \"green:wan\";\n\t\t};\n\n\t\twlan {\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t\tlabel = \"green:wlan\";\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\tlte {\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t\tlabel = \"green:lte\";\n\t\t};\n\t};\n};\n\n&pcie0 {\n\tstatus = \"okay\";\n};\n\n&usb0 {\n\tstatus = \"okay\";\n};\n\n&usb_phy {\n\tstatus = \"okay\";\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x40000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t};\n\n\t\t\tart: partition@50000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0x50000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@60000 {\n\t\t\t\tlabel = \"kernel\";\n\t\t\t\treg = <0x60000 0x400000>;\n\t\t\t};\n\n\t\t\tpartition@460000 {\n\t\t\t\tlabel = \"nor_reserved\";\n\t\t\t\treg = <0x460000 0xba0000>;\n\t\t\t};\n\t\t};\n\t};\n\n\tflash@1 {\n\t\tcompatible = \"spi-nand\";\n\t\treg = <1>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"ubi\";\n\t\t\t\treg = <0x0 0x8000000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tphy-handle = <&swphy4>;\n\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&eth1 {\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <1>;\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9531_joyit_jt-or750i.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca953x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"joyit,jt-or750i\", \"qca,qca9531\";\n\tmodel = \"Joy-IT JT-OR750i\";\n\n\taliases {\n\t\tled-boot = &led_status_green;\n\t\tled-failsafe = &led_status_red;\n\t\tled-running = &led_status_green;\n\t\tled-upgrade = &led_status_red;\n\t\tlabel-mac-device = &eth0;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tpinctrl-names = \"default\";\n\t\tpinctrl-0 = <&jtag_disable_pins &pinmux_led_eth_pins>;\n\n\t\tled_status_green: status_green {\n\t\t\tlabel = \"green:status\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\tled_status_red: status_red {\n\t\t\tlabel = \"red:status\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&pinmux {\n\tpinmux_led_eth_pins: pinmux_led_eth_pins {\n\t\tpinctrl-single,bits = \\\n\t\t\t/* GPIO 4: LED_LINK_5 (WAN) */     \\\n\t\t\t<0x04 0x0000002d 0x000000ff>,      \\\n\t\t\t/* GPIO 14: LED_LINK_2 (LAN 3) */  \\\n\t\t\t/* GPIO 15: LED_LINK_3 (LAN 2) */  \\\n\t\t\t<0x0c 0x2b2a0000 0xffff0000>,      \\\n\t\t\t/* GPIO 16: LED_LINK_4 (LAN 1) */  \\\n\t\t\t<0x10 0x0000002c 0x000000ff>;\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <50000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x40000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0xfa0000>;\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t};\n\n\t\t\tart: partition@ff0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0xff0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tphy-handle = <&swphy4>;\n\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&eth1 {\n\tnvmem-cells = <&macaddr_art_6>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&pcie0 {\n\tstatus = \"okay\";\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n\n\tmacaddr_art_6: macaddr@6 {\n\t\treg = <0x6 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9531_letv_lba-047-ch.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca953x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/mtd/partitions/uimage.h>\n\n/ {\n\tmodel = \"Letv LBA-047-CH\";\n\tcompatible = \"letv,lba-047-ch\", \"qca,qca9531\";\n\n\taliases {\n\t\tled-boot = &led_status_red;\n\t\tled-failsafe = &led_status_red;\n\t\tled-running = &led_status_blue;\n\t\tled-upgrade = &led_status_red;\n\t\tlabel-mac-device = &eth0;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tpinctrl-names = \"default\";\n\t\tpinctrl-0 = <&led_wan_pin>;\n\n\t\tled_status_blue: status_blue {\n\t\t\tlabel = \"blue:status\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_status_red: status_red {\n\t\t\tlabel = \"red:status\";\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tvirtual_flash {\n\t\tcompatible = \"mtd-concat\";\n\t\tdevices = <&fwconcat0 &fwconcat1>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\treg = <0x0 0x0>;\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\tcompatible = \"openwrt,uimage\", \"denx,uimage\";\n\t\t\t\topenwrt,ih-magic = <IH_MAGIC_OKLI>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pinmux {\n\t/* GPIO 4: LED_LINK_5 (WAN) */\n\tled_wan_pin: pinmux_led_wan_pin {\n\t\tpinctrl-single,bits = <0x04 0x0000002d 0x000000ff>;\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <50000000>;\n\t\tm25p,fast-read;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x40000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfwconcat0: partition@50000 {\n\t\t\t\tlabel = \"fwconcat0\";\n\t\t\t\treg = <0x50000 0xe30000>;\n\t\t\t};\n\n\t\t\tpartition@e80000 {\n\t\t\t\tlabel = \"loader\";\n\t\t\t\treg = <0xe80000 0x10000>;\n\t\t\t};\n\n\t\t\tfwconcat1: partition@e90000 {\n\t\t\t\tlabel = \"fwconcat1\";\n\t\t\t\treg = <0xe90000 0x160000>;\n\t\t\t};\n\n\t\t\tart: partition@ff0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0xff0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tphy-handle = <&swphy4>;\n\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&eth1 {\n\tcompatible = \"qca,qca9530-eth\", \"syscon\", \"simple-mfd\";\n\n\tnvmem-cells = <&macaddr_art_6>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n\n\tmacaddr_art_6: macaddr@6 {\n\t\treg = <0x6 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9531_qxwlan_e600g-v2-16m.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9531_qxwlan_e600g.dtsi\"\n\n/ {\n\tmodel = \"Qxwlan E600G v2 16M\";\n\tcompatible = \"qxwlan,e600g-v2-16m\", \"qca,qca9531\";\n};\n\n&leds {\n\twlan {\n\t\tlabel = \"blue:wlan\";\n\t\tgpios = <&gpio 4 GPIO_ACTIVE_LOW>;\n\t\tlinux,default-trigger = \"phy0tpt\";\n\t};\n};\n\n&partitions {\n\tpartition@70000 {\n\t\tcompatible = \"denx,uimage\";\n\t\tlabel = \"firmware\";\n\t\treg = <0x070000 0xf90000>;\n\t};\n};\n\n&usb_phy {\n\tstatus = \"okay\";\n};\n\n&usb0 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9531_qxwlan_e600g-v2-8m.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9531_qxwlan_e600g.dtsi\"\n\n/ {\n\tmodel = \"Qxwlan E600G v2 8M\";\n\tcompatible = \"qxwlan,e600g-v2-8m\", \"qca,qca9531\";\n};\n\n&leds {\n\twlan {\n\t\tlabel = \"blue:wlan\";\n\t\tgpios = <&gpio 4 GPIO_ACTIVE_LOW>;\n\t\tlinux,default-trigger = \"phy0tpt\";\n\t};\n};\n\n&partitions {\n\tpartition@70000 {\n\t\tcompatible = \"denx,uimage\";\n\t\tlabel = \"firmware\";\n\t\treg = <0x070000 0x790000>;\n\t};\n};\n\n&usb_phy {\n\tstatus = \"okay\";\n};\n\n&usb0 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9531_qxwlan_e600g.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca953x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\taliases {\n\t\tlabel-mac-device = &eth0;\n\t\tled-boot = &led_system;\n\t\tled-failsafe = &led_system;\n\t\tled-running = &led_system;\n\t\tled-upgrade = &led_system;\n\t};\n\n\tkeys: keys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds: leds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_system: system {\n\t\t\tlabel = \"blue:system\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\twan {\n\t\t\tlabel = \"green:wan\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan {\n\t\t\tlabel = \"green:lan\";\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&pcie0 {\n\tstatus = \"okay\";\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions: partitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x040000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpridata: partition@50000 {\n\t\t\t\tlabel = \"pri-data\";\n\t\t\t\treg = <0x050000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tart: partition@60000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0x060000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tphy-handle = <&swphy4>;\n\n\tnvmem-cells = <&macaddr_pridata_400>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <1>;\n};\n\n&eth1 {\n\tnvmem-cells = <&macaddr_pridata_400>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n};\n\n&pridata {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_pridata_400: macaddr@400 {\n\t\treg = <0x400 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9531_qxwlan_e600gac-v2-16m.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9531_qxwlan_e600g.dtsi\"\n\n/ {\n\tmodel = \"Qxwlan E600GAC v2 16M\";\n\tcompatible = \"qxwlan,e600gac-v2-16m\", \"qca,qca9531\";\n};\n\n&keys {\n\twps {\n\t\tlabel = \"wps\";\n\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\tgpios = <&gpio 1 GPIO_ACTIVE_LOW>;\n\t\tdebounce-interval = <60>;\n\t};\n};\n\n&leds {\n\twlan2g {\n\t\tlabel = \"orange:wlan2g\";\n\t\tgpios = <&gpio 4 GPIO_ACTIVE_LOW>;\n\t\tlinux,default-trigger = \"phy1tpt\";\n\t};\n\n\tcontrol1 {\n\t\tlabel = \"green:control\";\n\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t};\n\n\tcontrol2 {\n\t\tlabel = \"red:control\";\n\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t};\n\n\tcontrol3 {\n\t\tlabel = \"blue:control\";\n\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t};\n};\n\n&partitions {\n\tpartition@70000 {\n\t\tcompatible = \"denx,uimage\";\n\t\tlabel = \"firmware\";\n\t\treg = <0x070000 0xf90000>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9531_qxwlan_e600gac-v2-8m.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9531_qxwlan_e600g.dtsi\"\n\n/ {\n\tmodel = \"Qxwlan E600GAC v2 8M\";\n\tcompatible = \"qxwlan,e600gac-v2-8m\", \"qca,qca9531\";\n};\n\n&keys {\n\twps {\n\t\tlabel = \"wps\";\n\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\tgpios = <&gpio 1 GPIO_ACTIVE_LOW>;\n\t\tdebounce-interval = <60>;\n\t};\n};\n\n&leds {\n\twlan2g {\n\t\tlabel = \"orange:wlan2g\";\n\t\tgpios = <&gpio 4 GPIO_ACTIVE_LOW>;\n\t\tlinux,default-trigger = \"phy1tpt\";\n\t};\n\n\tcontrol1 {\n\t\tlabel = \"green:control\";\n\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t};\n\n\tcontrol2 {\n\t\tlabel = \"red:control\";\n\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t};\n\n\tcontrol3 {\n\t\tlabel = \"blue:control\";\n\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t};\n};\n\n&partitions {\n\tpartition@70000 {\n\t\tcompatible = \"denx,uimage\";\n\t\tlabel = \"firmware\";\n\t\treg = <0x070000 0x790000>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9531_telco_t1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca953x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"telco,t1\", \"qca,qca9531\";\n\tmodel = \"Telco T1\";\n\n\taliases {\n\t\tlabel-mac-device = &eth0;\n\t\tled-boot = &led_rssi0;\n\t\tled-failsafe = &led_rssi0;\n\t\tled-running = &led_rssi0;\n\t\tled-upgrade = &led_rssi0;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tpinctrl-names = \"default\";\n\t\tpinctrl-0 = <&jtag_disable_pins &pinmux_led_wan_pin>;\n\n\t\twan {\n\t\t\tlabel = \"blue:wan\";\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan {\n\t\t\tlabel = \"blue:lan\";\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan {\n\t\t\tlabel = \"blue:wlan\";\n\t\t\tgpios = <&gpio 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\tled_rssi0: rssi0 {\n\t\t\tlabel = \"blue:rssi0\";\n\t\t\tgpios = <&gpio 2 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\trssi1 {\n\t\t\tlabel = \"blue:rssi1\";\n\t\t\tgpios = <&gpio 3 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\trssi2 {\n\t\t\tlabel = \"blue:rssi2\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&usb0 {\n\tstatus = \"okay\";\n};\n\n&usb_phy {\n\tstatus = \"okay\";\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tart: partition@10000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0x010000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x020000 0xfd0000>;\n\t\t\t};\n\n\t\t\tpartition@ff0000 {\n\t\t\t\tlabel = \"art-backup\";\n\t\t\t\treg = <0xff0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tphy-handle = <&swphy4>;\n\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&eth1 {\n\tnvmem-cells = <&macaddr_art_6>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n};\n\n&pinmux {\n\tpinmux_led_wan_pin: led_wan_pin {\n\t\tpinctrl-single,bits = <0x4 0x0 0xff>;\n\t};\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n\n\tmacaddr_art_6: macaddr@6 {\n\t\treg = <0x6 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9531_tplink_archer-d50-v1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca953x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"tplink,archer-d50-v1\", \"qca,qca9531\";\n\tmodel = \"TP-Link Archer D50 v1\";\n\n\taliases {\n\t\tled-boot = &led_system;\n\t\tled-failsafe = &led_system;\n\t\tled-running = &led_system;\n\t\tled-upgrade = &led_system;\n\t\tlabel-mac-device = &wmac;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twlan2g {\n\t\t\tlabel = \"white:wlan2g\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\twlan5g {\n\t\t\tlabel = \"white:wlan5g\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\n\t\tqss {\n\t\t\tlabel = \"white:qss\";\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twan {\n\t\t\tlabel = \"white:wan\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan {\n\t\t\tlabel = \"white:lan\";\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tusb {\n\t\t\tlabel = \"white:usb\";\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_LOW>;\n\t\t\ttrigger-sources = <&hub_port0>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\n\t\tinternet {\n\t\t\tlabel = \"white:internet\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_system: system {\n\t\t\tlabel = \"white:system\";\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"Reset button\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\trfkill {\n\t\t\tlabel = \"RFKILL button\";\n\t\t\tlinux,code = <KEY_RFKILL>;\n\t\t\tgpios = <&gpio 3 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"WPS button\";\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tgpios = <&gpio 2 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x020000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tcompatible = \"tplink,firmware\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x020000 0x7a0000>;\n\t\t\t};\n\n\t\t\tpartition@7c0000 {\n\t\t\t\tlabel = \"config\";\n\t\t\t\treg = <0x7c0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tromfile: partition@7d0000 {\n\t\t\t\tlabel = \"romfile\";\n\t\t\t\treg = <0x7d0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@7e0000 {\n\t\t\t\tlabel = \"rom\";\n\t\t\t\treg = <0x7e0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tart: partition@7f0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0x7f0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tphy-handle = <&swphy4>;\n\n\tnvmem-cells = <&macaddr_romfile_f100>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <1>;\n};\n\n&eth1 {\n\tnvmem-cells = <&macaddr_romfile_f100>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n\tnvmem-cells = <&macaddr_romfile_f100>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&pcie0 {\n\tstatus = \"okay\";\n\n\twifi@0,0 {\n\t\tcompatible = \"pci168c,003c\";\n\t\treg = <0x0000 0 0 0 0>;\n\t};\n};\n\n&usb_phy {\n\tstatus = \"okay\";\n};\n\n&usb0 {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\tstatus = \"okay\";\n\n\thub_port0: port@1 {\n\t\treg = <1>;\n\t\t#trigger-source-cells = <0>;\n\t};\n};\n\n&romfile {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_romfile_f100: macaddr@f100 {\n\t\treg = <0xf100 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9531_tplink_tl-mr3420-v3.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca953x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"tplink,tl-mr3420-v3\", \"qca,qca9531\";\n\tmodel = \"TP-Link TL-MR3420 v3\";\n\n\taliases {\n\t\tled-boot = &led_system;\n\t\tled-failsafe = &led_system;\n\t\tled-running = &led_system;\n\t\tled-upgrade = &led_system;\n\t\tlabel-mac-device = &wmac;\n\n\t};\n\n\tled_spi {\n\t\tcompatible = \"spi-gpio\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tsck-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;\n\t\tmosi-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\t\tcs-gpios = <&gpio 13 GPIO_ACTIVE_HIGH>;\n\t\tnum-chipselects = <1>;\n\n\t\tled_gpio: led_gpio@0 {\n\t\t\tcompatible = \"fairchild,74hc595\";\n\t\t\treg = <0>;\n\t\t\tgpio-controller;\n\t\t\t#gpio-cells = <2>;\n\t\t\tregisters-number = <1>;\n\t\t\tspi-max-frequency = <10000000>;\n\t\t};\n\t};\n\n\tgpio-export {\n\t\tcompatible = \"gpio-export\";\n\n\t\tgpio_shift_register_oe {\n\t\t\tgpio-export,name = \"tp-link:oe:sr\";\n\t\t\tgpio-export,output = <0>;\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tgpio_shift_register_reset {\n\t\t\tgpio-export,name = \"tp-link:reset:sr\";\n\t\t\tgpio-export,output = <1>;\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_system: system {\n\t\t\tlabel = \"green:system\";\n\t\t\tgpios = <&gpio 1 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\tlan4 {\n\t\t\tlabel = \"green:lan4\";\n\t\t\tgpios = <&led_gpio 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan3 {\n\t\t\tlabel = \"green:lan3\";\n\t\t\tgpios = <&led_gpio 1 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan2 {\n\t\t\tlabel = \"green:lan2\";\n\t\t\tgpios = <&led_gpio 2 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan1 {\n\t\t\tlabel = \"green:lan1\";\n\t\t\tgpios = <&led_gpio 3 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twan {\n\t\t\tlabel = \"green:wan\";\n\t\t\tgpios = <&led_gpio 4 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twan_fail {\n\t\t\tlabel = \"orange:wan\";\n\t\t\tgpios = <&led_gpio 5 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan {\n\t\t\tlabel = \"green:wlan\";\n\t\t\tgpios = <&led_gpio 6 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\tusb {\n\t\t\tlabel = \"green:usb\";\n\t\t\tgpios = <&led_gpio 7 GPIO_ACTIVE_LOW>;\n\t\t\ttrigger-sources = <&hub_port>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\n\t\tqss {\n\t\t\tlabel = \"green:qss\";\n\t\t\tgpios = <&gpio 3 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"Reset button\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\trfkill {\n\t\t\tlabel = \"RF kill button\";\n\t\t\tlinux,code = <KEY_RFKILL>;\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tuboot: partition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x020000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tcompatible = \"tplink,firmware\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x020000 0x3d0000>;\n\t\t\t};\n\n\t\t\tart: partition@3f0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0x3f0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tphy-handle = <&swphy4>;\n\n\tnvmem-cells = <&macaddr_uboot_1fc00>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <1>;\n};\n\n&eth1 {\n\tnvmem-cells = <&macaddr_uboot_1fc00>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n\tnvmem-cells = <&macaddr_uboot_1fc00>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&usb0 {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\tstatus = \"okay\";\n\n\thub_port: port@1 {\n\t\treg = <1>;\n\t\t#trigger-source-cells = <0>;\n\t};\n};\n\n&usb_phy {\n\tstatus = \"okay\";\n};\n\n&uboot {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_uboot_1fc00: macaddr@1fc00 {\n\t\treg = <0x1fc00 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9531_tplink_tl-mr6400-v1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later\n\n#include \"qca953x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"tplink,tl-mr6400-v1\", \"qca,qca9531\";\n\tmodel = \"TP-Link TL-MR6400 v1\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t\tlabel-mac-device = &wmac;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\t/* D12 */\n\t\twan {\n\t\t\tlabel = \"white:wan\";\n\t\t\tgpios = <&gpio 0 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\t/* D11 */\n\t\t4g {\n\t\t\tlabel = \"white:4g\";\n\t\t\tgpios = <&gpio 1 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\t/* D5 */\n\t\twps {\n\t\t\tlabel = \"white:wps\";\n\t\t\tgpios = <&gpio 3 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\t/* D3 */\n\t\twlan {\n\t\t\tlabel = \"white:wlan\";\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\t/* D2 */\n\t\tled_power: power {\n\t\t\tlabel = \"white:power\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\t/* D4 */\n\t\tlan {\n\t\t\tlabel = \"white:lan\";\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\t/* SW2 */\n\t\treset {\n\t\t\tlabel = \"Reset button\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\t/* SW3 */\n\t\trfkill {\n\t\t\tlabel = \"RF kill button\";\n\t\t\tlinux,code = <KEY_RFKILL>;\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tgpio-export {\n\t\tcompatible = \"gpio-export\";\n\n\t\tgpio_usb_power {\n\t\t\tgpio-export,name = \"tp-link:power:lte\";\n\t\t\tgpio-export,output = <0>;\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tuboot: partition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x020000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tcompatible = \"tplink,firmware\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x020000 0x7d0000>;\n\t\t\t};\n\n\t\t\tart: partition@7f0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0x7f0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tphy-handle = <&swphy0>;\n\n\tnvmem-cells = <&macaddr_uboot_1fc00>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <1>;\n};\n\n&eth1 {\n\tnvmem-cells = <&macaddr_uboot_1fc00>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <(-1)>;\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n\tnvmem-cells = <&macaddr_uboot_1fc00>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&usb0 {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\tstatus = \"okay\";\n\n\thub_port: port@1 {\n\t\treg = <1>;\n\t\t#trigger-source-cells = <0>;\n\t};\n};\n\n&usb_phy {\n\tstatus = \"okay\";\n};\n\n&uboot {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_uboot_1fc00: macaddr@1fc00 {\n\t\treg = <0x1fc00 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9531_tplink_tl-wr810n-v1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca953x_tplink_tl-wr810n.dtsi\"\n\n/ {\n\tcompatible = \"tplink,tl-wr810n-v1\", \"qca,qca9531\";\n\tmodel = \"TP-Link TL-WR810N v1\";\n\n\treg_usb_vbus: reg_usb_vbus {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"usb_vbus\";\n\t\tregulator-min-microvolt = <5000000>;\n\t\tregulator-max-microvolt = <5000000>;\n\t\tgpio = <&gpio 11 GPIO_ACTIVE_HIGH>;\n\t\tenable-active-high;\n\t\tregulator-always-on;\n\t};\n};\n\n&usb0 {\n\tstatus = \"okay\";\n\n\tvbus-supply = <&reg_usb_vbus>;\n};\n\n&usb_phy {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9531_tplink_tl-wr902ac-v1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca953x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"tplink,tl-wr902ac-v1\", \"qca,qca9531\";\n\tmodel = \"TP-Link TL-WR902AC v1\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t\tlabel-mac-device = &wmac;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\tinternet {\n\t\t\tlabel = \"green:internet\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan2g {\n\t\t\tlabel = \"green:wlan2g\";\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\tusb {\n\t\t\tlabel = \"green:usb\";\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_HIGH>;\n\t\t\ttrigger-sources = <&hub_port0>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&gpio 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan {\n\t\t\tlabel = \"green:lan\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"Reset button\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 3 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"WPS button\";\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tgpios = <&gpio 2 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tsw1 {\n\t\t\tlabel = \"Mode switch 1\";\n\t\t\tlinux,input-type = <EV_SW>;\n\t\t\tlinux,code = <BTN_0>;\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tsw2 {\n\t\t\tlabel = \"Mode switch 2\";\n\t\t\tlinux,input-type = <EV_SW>;\n\t\t\tlinux,code = <BTN_1>;\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tgpio-export {\n\t\tcompatible = \"gpio-export\";\n\n\t\tgpio_usb_power {\n\t\t\tgpio-export,name = \"tp-link:power:usb\";\n\t\t\tgpio-export,output = <1>;\n\t\t\tgpios = <&gpio 1 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x020000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tcompatible = \"tplink,firmware\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x020000 0x730000>;\n\t\t\t};\n\n\t\t\tinfo: partition@750000 {\n\t\t\t\tlabel = \"info\";\n\t\t\t\treg = <0x750000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@760000 {\n\t\t\t\tlabel = \"tplink\";\n\t\t\t\treg = <0x760000 0x090000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tart: partition@7f0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0x7f0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tphy-handle = <&swphy4>;\n\n\tnvmem-cells = <&macaddr_info_8>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <1>;\n};\n\n&eth1 {\n\tcompatible = \"syscon\", \"simple-mfd\";\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n\tnvmem-cells = <&macaddr_info_8>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&pcie0 {\n\tstatus = \"okay\";\n\n\twifi@0,0 {\n\t\tcompatible = \"pci168c,0050\";\n\t\treg = <0x0000 0 0 0 0>;\n\t};\n};\n\n&usb_phy {\n\tstatus = \"okay\";\n};\n\n&usb0 {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\tstatus = \"okay\";\n\n\thub_port0: port@1 {\n\t\treg = <1>;\n\t\t#trigger-source-cells = <0>;\n\t};\n};\n\n&info {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_info_8: macaddr@8 {\n\t\treg = <0x8 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9531_wallys_dr531.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca953x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"Wallys DR531\";\n\tcompatible = \"wallys,dr531\", \"qca,qca9531\";\n\n\taliases {\n\t\tlabel-mac-device = &eth1;\n\t\tled-boot = &led_sig4;\n\t\tled-failsafe = &led_sig4;\n\t\tled-upgrade = &led_sig4;\n\t};\n\n\tgpio-export {\n\t\tcompatible = \"gpio-export\";\n\n\t\tbuzzer {\n\t\t\tgpio-export,name = \"buzzer\";\n\t\t\tgpio-export,output = <0>;\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tlan {\n\t\t\tlabel = \"green:lan\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_sig4: sig4 {\n\t\t\tlabel = \"green:sig4\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tsig1 {\n\t\t\tlabel = \"green:sig1\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tsig2 {\n\t\t\tlabel = \"green:sig2\";\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tsig3 {\n\t\t\tlabel = \"green:sig3\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twan {\n\t\t\tlabel = \"green:wan\";\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tphy-handle = <&swphy4>;\n\tnvmem-cells = <&macaddr_env_f818>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&eth1 {\n\t/* Workaround: keep the Ethernet interfaces order/mapping correct\n\t * (GMAC0 -> eth0, GMAC1 -> eth1, same as in old ar71xx target) */\n\tcompatible = \"qca,qca9530-eth\", \"syscon\", \"simple-mfd\";\n\n\tnvmem-cells = <&macaddr_env_f810>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&pcie0 {\n\tstatus = \"okay\";\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <50000000>;\n\t\tm25p,fast-read;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x030000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tenv: partition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x030000 0x010000>;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"partition-table\";\n\t\t\t\treg = <0x040000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x050000 0x7a0000>;\n\t\t\t};\n\n\t\t\tart: partition@7f0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0x7f0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&usb0 {\n\tstatus = \"okay\";\n};\n\n&usb_phy {\n\tstatus = \"okay\";\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n};\n\n&env {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_env_f810: macaddr@f810 {\n\t\treg = <0xf810 0x6>;\n\t};\n\n\tmacaddr_env_f818: macaddr@f818 {\n\t\treg = <0xf818 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9531_yuncore_a770.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca953x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"YunCore A770\";\n\tcompatible = \"yuncore,a770\", \"qca,qca9531\";\n\n\taliases {\n\t\tled-boot = &led_status;\n\t\tled-failsafe = &led_status;\n\t\tled-running = &led_status;\n\t\tled-upgrade = &led_status;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tlan {\n\t\t\tlabel = \"green:lan\";\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_status: status {\n\t\t\tlabel = \"green:status\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"keep\";\n\t\t};\n\n\t\twan {\n\t\t\tlabel = \"green:wan\";\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan2g {\n\t\t\tlabel = \"red:wlan2g\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x040000 0x010000>;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x050000 0xfa0000>;\n\t\t\t};\n\n\t\t\tart: partition@ff0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0xff0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tphy-handle = <&swphy4>;\n\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&eth1 {\n\tnvmem-cells = <&macaddr_art_6>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&pcie0 {\n\tstatus = \"okay\";\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n\n\tmacaddr_art_6: macaddr@6 {\n\t\treg = <0x6 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9533_comfast_cf-e110n-v2.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca953x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"comfast,cf-e110n-v2\", \"qca,qca9533\";\n\tmodel = \"COMFAST CF-E110N v2\";\n\n\taliases {\n\t\tserial0 = &uart;\n\t\tled-boot = &led_rssihigh;\n\t\tled-failsafe = &led_rssihigh;\n\t\tled-upgrade = &led_rssihigh;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tpinctrl-names = \"default\";\n\t\tpinctrl-0 = <&jtag_disable_pins &led_rssilow_pin &led_rssimediumhigh_pin &led_rssihigh_pin>;\n\n\t\twan {\n\t\t\tlabel = \"green:wan\";\n\t\t\tgpios = <&gpio 3 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan {\n\t\t\tlabel = \"green:lan\";\n\t\t\tgpios = <&gpio 2 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\trssilow {\n\t\t\tlabel = \"red:rssilow\";\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\trssimediumlow {\n\t\t\tlabel = \"red:rssimediumlow\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\trssimediumhigh {\n\t\t\tlabel = \"green:rssimediumhigh\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_rssihigh: rssihigh {\n\t\t\tlabel = \"green:rssihigh\";\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tath9k-leds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twlan {\n\t\t\tlabel = \"green:wlan\";\n\t\t\tgpios = <&gpio 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n};\n\n&pinmux {\n\tled_rssilow_pin: pinmux_rssilow_pin {\n\t\tpinctrl-single,bits = <0x8 0x0 0xff000000>;\n\t};\n\n\tled_rssimediumhigh_pin: pinmux_rssimediumhigh_pin {\n\t\tpinctrl-single,bits = <0xc 0x0 0x00ff0000>;\n\t};\n\n\tled_rssihigh_pin: pinmux_rssihigh_pin {\n\t\tpinctrl-single,bits = <0x10 0x0 0x000000ff>;\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"winbond,w25q128\", \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tart: partition@10000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0x010000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x020000 0xfd0000>;\n\t\t\t};\n\n\t\t\tpartition@ff0000 {\n\t\t\t\tlabel = \"nvram\";\n\t\t\t\treg = <0xff0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tphy-handle = <&swphy4>;\n\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&eth1 {\n\tnvmem-cells = <&macaddr_art_1002>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tgmac-config {\n\t\tdevice = <&gmac>;\n\t};\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n\tnvmem-cells = <&macaddr_art_6>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n\n\tmacaddr_art_6: macaddr@6 {\n\t\treg = <0x6 0x6>;\n\t};\n\n\tmacaddr_art_1002: macaddr@1002 {\n\t\treg = <0x1002 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9533_dlink_dap-1330-a1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9533_dlink_dap-13xx.dtsi\"\n\n/ {\n\tcompatible = \"dlink,dap-1330-a1\", \"qca,qca9533\";\n\tmodel = \"D-Link DAP-1330 A1\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9533_dlink_dap-1365-a1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9533_dlink_dap-13xx.dtsi\"\n\n/ {\n\tcompatible = \"dlink,dap-1365-a1\", \"qca,qca9533\";\n\tmodel = \"D-Link DAP-1365 A1\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9533_dlink_dap-13xx.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca953x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_status;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_status;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tgpios = <&gpio 2 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_status: status {\n\t\t\tlabel = \"red:status\";\n\t\t\tgpios = <&gpio 3 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\trssilow {\n\t\t\tlabel = \"red:rssilow\";\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\trssimediumlow {\n\t\t\tlabel = \"green:rssimediumlow\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\trssimediumhigh {\n\t\t\tlabel = \"green:rssimediumhigh\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\trssihigh {\n\t\t\tlabel = \"green:rssihigh\";\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <50000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tart: partition@10000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0x10000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tlabel = \"mp\";\n\t\t\t\treg = <0x20000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"config\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x40000 0x7c0000>;\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t};\n\t\t};\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9533_dlink_dap-2230-a1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca953x_dlink_dap-2xxx.dtsi\"\n\n/ {\n\tcompatible = \"dlink,dap-2230-a1\", \"qca,qca9533\";\n\tmodel = \"D-Link DAP-2230 A1\";\n\n\taliases {\n\t\tled-boot = &led_power_green;\n\t\tled-failsafe = &led_power_green;\n\t\tled-running = &led_power_green;\n\t\tled-upgrade = &led_power_green;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power_green: power_green {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n};\n\n&partitions {\n\tpartition@70000 {\n\t\tlabel = \"firmware\";\n\t\treg = <0x70000 0xee0000>;\n\t\tcompatible = \"wrg\";\n\t};\n\n\tpartition@f50000 {\n\t\tlabel = \"dlink\";\n\t\treg = <0xf50000 0xa0000>;\n\t\tread-only;\n\t};\n\n\tart: partition@ff0000 {\n\t\tlabel = \"art\";\n\t\treg = <0xff0000 0x10000>;\n\t\tread-only;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9533_dlink_dap-3320-a1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca953x_dlink_dap-2xxx.dtsi\"\n\n/ {\n\tcompatible = \"dlink,dap-3320-a1\", \"qca,qca9533\";\n\tmodel = \"D-Link DAP-3320 A1\";\n\n\taliases {\n\t\tled-boot = &led_power_green;\n\t\tled-failsafe = &led_power_green;\n\t\tled-running = &led_power_green;\n\t\tled-upgrade = &led_power_green;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power_green: power_green {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n};\n\n&partitions {\n\tpartition@70000 {\n\t\tlabel = \"firmware\";\n\t\treg = <0x70000 0xef0000>;\n\t\tcompatible = \"wrg\";\n\t};\n\n\tpartition@f60000 {\n\t\tlabel = \"dlink\";\n\t\treg = <0xf60000 0x90000>;\n\t\tread-only;\n\t};\n\n\tart: partition@ff0000 {\n\t\tlabel = \"art\";\n\t\treg = <0xff0000 0x10000>;\n\t\tread-only;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9533_mikrotik_routerboard-16m.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca953x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\taliases {\n\t\tserial0 = &uart;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <40000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"RouterBoot\";\n\t\t\t\treg = <0x0 0x20000>;\n\t\t\t\tcompatible = \"mikrotik,routerboot-partitions\";\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\n\t\t\t\tpartition@0 {\n\t\t\t\t\tlabel = \"bootloader1\";\n\t\t\t\t\treg = <0x0 0x0>;\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\thard_config {\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\tbios {\n\t\t\t\t\tsize = <0x1000>;\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\tpartition@10000 {\n\t\t\t\t\tlabel = \"bootloader2\";\n\t\t\t\t\treg = <0x10000 0x0>;\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\tsoft_config {\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tcompatible = \"mikrotik,minor\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x020000 0xfe0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tqca,no-eeprom;\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9533_mikrotik_routerboard-lhg-2nd.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9533_mikrotik_routerboard-lhg-hb.dtsi\"\n\n/ {\n\tcompatible = \"mikrotik,routerboard-lhg-2nd\", \"qca,qca9533\";\n\tmodel = \"MikroTik RouterBOARD LHG 2nD\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9533_mikrotik_routerboard-lhg-hb.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9533_mikrotik_routerboard-16m.dtsi\"\n\n/ {\n\tcompatible = \"mikrotik,routerboard-lhg-hb\", \"qca,qca9533\";\n\tmodel = \"MikroTik RouterBOARD LHG-HB platform\";\n\n\taliases {\n\t\tled-boot = &led_user;\n\t\tled-failsafe = &led_user;\n\t\tled-upgrade = &led_user;\n\t\tled-running = &led_user;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tpinctrl-names = \"default\";\n\t\tpinctrl-0 = <&led_wan_pin>;\n\n\t\tpower {\n\t\t\tlabel = \"blue:power\";\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\tled_user: user {\n\t\t\tlabel = \"green:user\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan {\n\t\t\tlabel = \"green:lan\";\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan {\n\t\t\tlabel = \"green:wlan\";\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\trssilow {\n\t\t\tlabel = \"green:rssilow\";\n\t\t\tgpios = <&gpio 9 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\trssimediumlow {\n\t\t\tlabel = \"green:rssimediumlow\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\trssimediumhigh {\n\t\t\tlabel = \"green:rssimediumhigh\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\t/* The rssihigh LED GPIO 16 is shared with the reset button, so it remains\n\t\tunregistered here to avoid conflict.\n\n\t\trssihigh {\n\t\t\tlabel = \"green:rssihigh\";\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\t*/\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tphy-handle = <&swphy0>;\n\n\tgmac-config {\n\t\tdevice = <&gmac>;\n\t\tswitch-phy-swap = <1>;\n\t};\n};\n\n&eth1 {\n\tcompatible = \"syscon\", \"simple-mfd\";\n};\n\n&pinmux {\n\tled_wan_pin: pinmux_led_wan_pin {\n\t\tpinctrl-single,bits = <0x4 0x0 0xff>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9533_mikrotik_routerboard-mapl-2nd.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9533_mikrotik_routerboard-16m.dtsi\"\n\n/ {\n\tcompatible = \"mikrotik,routerboard-mapl-2nd\", \"qca,qca9533\";\n\tmodel = \"MikroTik RouterBOARD mAPL-2nD (mAP lite)\";\n\n\taliases {\n\t\tled-boot = &led_user;\n\t\tled-failsafe = &led_user;\n\t\tled-running = &led_user;\n\t\tled-upgrade = &led_user;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tpinctrl-names = \"default\";\n\t\tpinctrl-0 = <&led_power_pin &led_lan_pin>;\n\n\t\tpower {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\tlan {\n\t\t\tlabel = \"green:lan\";\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\twlan {\n\t\t\tlabel = \"green:wlan\";\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\tled_user: user {\n\t\t\tlabel = \"green:user\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tphy-handle = <&swphy0>;\n\n\tgmac-config {\n\t\tdevice = <&gmac>;\n\t\tswitch-phy-swap = <1>;\n\t};\n};\n\n&eth1 {\n\tcompatible = \"syscon\", \"simple-mfd\";\n};\n\n&pinmux {\n\tled_lan_pin: pinmux_led_lan_pin {\n\t\tpinctrl-single,bits = <0x4 0x0 0xff>;\n\t};\n\n\tled_power_pin: pinmux_led_power_pin {\n\t\tpinctrl-single,bits = <0x10 0x0 0xff00>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9533_mikrotik_routerboard-wap-2nd.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9533_mikrotik_routerboard-16m.dtsi\"\n\n/ {\n\tcompatible = \"mikrotik,routerboard-wap-2nd\", \"qca,qca9533\";\n\tmodel = \"MikroTik RouterBOARD wAP-2nD (wAP)\";\n\n\taliases {\n\t\tled-boot = &led_user;\n\t\tled-failsafe = &led_user;\n\t\tled-running = &led_user;\n\t\tled-upgrade = &led_user;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tpinctrl-names = \"default\";\n\t\tpinctrl-0 = <&led_lan_pin>;\n\n\t\tlan {\n\t\t\tlabel = \"green:lan\";\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan {\n\t\t\tlabel = \"green:wlan\";\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\tled_user: user {\n\t\t\tlabel = \"green:user\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tphy-handle = <&swphy0>;\n\n\tgmac-config {\n\t\tdevice = <&gmac>;\n\t\tswitch-phy-swap = <1>;\n\t};\n};\n\n&eth1 {\n\tcompatible = \"syscon\", \"simple-mfd\";\n};\n\n&pinmux {\n\tled_lan_pin: pinmux_led_lan_pin {\n\t\tpinctrl-single,bits = <0x4 0x0 0xff>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9533_mikrotik_routerboard-wapr-2nd.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9533_mikrotik_routerboard-16m.dtsi\"\n\n/ {\n\tcompatible = \"mikrotik,routerboard-wapr-2nd\", \"qca,qca9533\";\n\tmodel = \"MikroTik RouterBOARD wAPR-2nD (wAP R)\";\n\n\taliases {\n\t\tled-boot = &led_rssilow;\n\t\tled-failsafe = &led_rssilow;\n\t\tled-upgrade = &led_rssilow;\n\t\tled-running = &led_rssilow;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tpinctrl-names = \"default\";\n\n\t\tled_rssilow: rssilow {\n\t\t\tlabel = \"green:rssilow\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\trssimedium {\n\t\t\tlabel = \"green:rssimedium\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\trssihigh {\n\t\t\tlabel = \"green:rssihigh\";\n\t\t\tgpios = <&gpio 3 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\twlan {\n\t\t\tlabel = \"green:wlan\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\t};\n\n\tgpio-export {\n\t\tcompatible = \"gpio-export\";\n\n\t\tminipcie {\n\t\t\tgpio-export,name = \"minipcie\";\n\t\t\tgpio-export,output = <1>;\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tphy-handle = <&swphy0>;\n\n\tgmac-config {\n\t\tdevice = <&gmac>;\n\t\tswitch-phy-swap = <1>;\n\t};\n};\n\n&eth1 {\n\tcompatible = \"syscon\", \"simple-mfd\";\n};\n\n&pcie0 {\n\tstatus = \"okay\";\n};\n\n&usb0 {\n\tstatus = \"okay\";\n};\n\n&usb_phy {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9533_openmesh_om2p-hs-v4.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9533_openmesh_om2p-v4.dtsi\"\n\n/ {\n\tcompatible = \"openmesh,om2p-hs-v4\", \"qca,qca9533\";\n\tmodel = \"OpenMesh OM2P-HS v4\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9533_openmesh_om2p-v4.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9533_openmesh_om2p-v4.dtsi\"\n\n/ {\n\tcompatible = \"openmesh,om2p-v4\", \"qca,qca9533\";\n\tmodel = \"OpenMesh OM2P v4\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9533_openmesh_om2p-v4.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca953x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tchosen {\n\t\t/delete-property/ bootargs;\n\t};\n\n\taliases {\n\t\tled-boot = &led_power_blue;\n\t\tled-failsafe = &led_power_blue;\n\t\tled-running = &led_power_blue;\n\t\tled-upgrade = &led_power_blue;\n\t\tlabel-mac-device = &eth0;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\tpinctrl-names = \"default\";\n\t\tpinctrl-0 = <&jtag_disable_pins>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 1 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power_blue: power_blue {\n\t\t\tlabel = \"blue:power\";\n\t\t\tgpios = <&gpio 0 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\twifi_green {\n\t\t\tlabel = \"green:wifi\";\n\t\t\tgpios = <&gpio 2 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\twifi_yellow {\n\t\t\tlabel = \"yellow:wifi\";\n\t\t\tgpios = <&gpio 3 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twifi_red {\n\t\t\tlabel = \"red:wifi\";\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twan_blue {\n\t\t\tlabel = \"blue:wan\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan_blue {\n\t\t\tlabel = \"blue:lan\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\twatchdog {\n\t\tcompatible = \"linux,wdt-gpio\";\n\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\thw_algo = \"toggle\";\n\t\t/* hw_margin_ms is actually 300s but driver limits it to 60s */\n\t\thw_margin_ms = <60000>;\n\t\talways-running;\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\t/* partitions are passed via bootloader */\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x040000 0x040000>;\n\t\t\t};\n\n\t\t\tpartition@80000 {\n\t\t\t\tlabel = \"custom\";\n\t\t\t\treg = <0x080000 0x140000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@1c0000 {\n\t\t\t\tlabel = \"inactive\";\n\t\t\t\treg = <0x1c0000 0x700000>;\n\t\t\t};\n\n\t\t\tpartition@8c0000 {\n\t\t\t\tlabel = \"inactive2\";\n\t\t\t\treg = <0x8c0000 0x700000>;\n\t\t\t};\n\n\t\t\tart: partition@fc0000 {\n\t\t\t\tlabel = \"ART\";\n\t\t\t\treg = <0xfc0000 0x040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tphy-handle = <&swphy4>;\n\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&eth1 {\n\t/* Workaround: keep the Ethernet interfaces order/mapping correct\n\t * (GMAC0 -> eth0, GMAC1 -> eth1, same as in old ar71xx target)\n\t */\n\tcompatible = \"qca,qca9530-eth\", \"syscon\", \"simple-mfd\";\n\n\tnvmem-cells = <&macaddr_art_6>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <2>;\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n\n\tmacaddr_art_6: macaddr@6 {\n\t\treg = <0x6 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9533_plasmacloud_pa300.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9533_plasmacloud_pa300.dtsi\"\n\n/ {\n\tcompatible = \"plasmacloud,pa300\", \"qca,qca9533\";\n\tmodel = \"Plasma Cloud PA300\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9533_plasmacloud_pa300.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca953x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tchosen {\n\t\t/delete-property/ bootargs;\n\t};\n\n\taliases {\n\t\tled-boot = &led_status_green;\n\t\tled-failsafe = &led_status_green;\n\t\tled-running = &led_status_green;\n\t\tled-upgrade = &led_status_green;\n\t\tlabel-mac-device = &eth0;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\tpinctrl-names = \"default\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 1 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tstatus_red {\n\t\t\tlabel = \"red:status\";\n\t\t\tgpios = <&gpio 0 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tled_status_green: status_green {\n\t\t\tlabel = \"green:status\";\n\t\t\tgpios = <&gpio 2 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tstatus_blue {\n\t\t\tlabel = \"blue:status\";\n\t\t\tgpios = <&gpio 3 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n\n\twatchdog {\n\t\tcompatible = \"linux,wdt-gpio\";\n\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\thw_algo = \"toggle\";\n\t\t/* hw_margin_ms is actually 300s but driver limits it to 60s */\n\t\thw_margin_ms = <60000>;\n\t\talways-running;\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\t/* partitions are passed via bootloader */\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x040000 0x040000>;\n\t\t\t};\n\n\t\t\tpartition@80000 {\n\t\t\t\tlabel = \"custom\";\n\t\t\t\treg = <0x080000 0x140000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@1c0000 {\n\t\t\t\tlabel = \"inactive\";\n\t\t\t\treg = <0x1c0000 0x700000>;\n\t\t\t};\n\n\t\t\tpartition@8c0000 {\n\t\t\t\tlabel = \"inactive2\";\n\t\t\t\treg = <0x8c0000 0x700000>;\n\t\t\t};\n\n\t\t\tart: partition@fc0000 {\n\t\t\t\tlabel = \"ART\";\n\t\t\t\treg = <0xfc0000 0x040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tphy-handle = <&swphy4>;\n\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&eth1 {\n\t/* Workaround: keep the Ethernet interfaces order/mapping correct\n\t * (GMAC0 -> eth0, GMAC1 -> eth1, same as in old ar71xx target)\n\t */\n\tcompatible = \"qca,qca9530-eth\", \"syscon\", \"simple-mfd\";\n\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <1>;\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <2>;\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9533_plasmacloud_pa300e.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9533_plasmacloud_pa300.dtsi\"\n\n/ {\n\tcompatible = \"plasmacloud,pa300e\", \"qca,qca9533\";\n\tmodel = \"Plasma Cloud PA300E\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9533_qca_ap143-16m.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9533_qca_ap143.dtsi\"\n\n/ {\n\tmodel = \"Qualcomm Atheros AP143 (16M) reference board\";\n\tcompatible = \"qca,ap143-16m\", \"qca,qca9533\";\n\n\tvirtual_flash {\n\t\tcompatible = \"mtd-concat\";\n\t\tdevices = <&fwconcat0 &fwconcat1>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\treg = <0x0 0x0>;\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\tcompatible = \"openwrt,uimage\", \"denx,uimage\";\n\t\t\t\topenwrt,ih-magic = <IH_MAGIC_OKLI>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&partitions {\n\tfwconcat0: partition@50000 {\n\t\tlabel = \"fwconcat0\";\n\t\treg = <0x050000 0xe30000>;\n\t};\n\n\tpartition@e80000 {\n\t\tlabel = \"loader\";\n\t\treg = <0xe80000 0x10000>;\n\t};\n\n\tfwconcat1: partition@e90000 {\n\t\tlabel = \"fwconcat1\";\n\t\treg = <0xe90000 0x160000>;\n\t};\n\n\tart: partition@ff0000 {\n\t\tlabel = \"art\";\n\t\treg = <0xff0000 0x010000>;\n\t\tread-only;\n\t};\n};\n\n&eth0 {\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&eth1 {\n\tnvmem-cells = <&macaddr_art_6>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wmac {\n\tmtd-cal-data = <&art 0x1000>;\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n\n\tmacaddr_art_6: macaddr@6 {\n\t\treg = <0x6 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9533_qca_ap143-8m.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9533_qca_ap143.dtsi\"\n\n/ {\n\tmodel = \"Qualcomm Atheros AP143 (8M) reference board\";\n\tcompatible = \"qca,ap143-8m\", \"qca,qca9533\";\n\n\tvirtual_flash {\n\t\tcompatible = \"mtd-concat\";\n\t\tdevices = <&fwconcat0 &fwconcat1>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\treg = <0x0 0x0>;\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\tcompatible = \"openwrt,uimage\", \"denx,uimage\";\n\t\t\t\topenwrt,ih-magic = <IH_MAGIC_OKLI>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&partitions {\n\tfwconcat0: partition@50000 {\n\t\tlabel = \"fwconcat0\";\n\t\treg = <0x050000 0x630000>;\n\t};\n\n\tpartition@680000 {\n\t\tlabel = \"loader\";\n\t\treg = <0x680000 0x10000>;\n\t};\n\n\tfwconcat1: partition@690000 {\n\t\tlabel = \"fwconcat1\";\n\t\treg = <0x690000 0x160000>;\n\t};\n\n\tart: partition@7f0000 {\n\t\tlabel = \"art\";\n\t\treg = <0x7f0000 0x010000>;\n\t\tread-only;\n\t};\n};\n\n&eth0 {\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&eth1 {\n\tnvmem-cells = <&macaddr_art_6>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wmac {\n\tmtd-cal-data = <&art 0x1000>;\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n\n\tmacaddr_art_6: macaddr@6 {\n\t\treg = <0x6 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9533_qca_ap143.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca953x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/mtd/partitions/uimage.h>\n\n/ {\n\taliases {\n\t\tled-boot = &led_wps;\n\t\tled-failsafe = &led_wps;\n\t\tled-running = &led_wps;\n\t\tled-upgrade = &led_wps;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twan {\n\t\t\tlabel = \"green:wan\";\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan {\n\t\t\tlabel = \"green:wlan\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\tlan1 {\n\t\t\tlabel = \"green:lan1\";\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan2 {\n\t\t\tlabel = \"green:lan2\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan3 {\n\t\t\tlabel = \"green:lan3\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan4 {\n\t\t\tlabel = \"green:lan4\";\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_wps: wps {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\twps {\n\t\t\tlabel = \"WPS button\";\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions: partitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x040000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tphy-handle = <&swphy4>;\n};\n\n&eth1 {\n\tgmac-config {\n\t\tdevice = <&gmac>;\n\t};\n};\n\n&wmac {\n\tstatus = \"okay\";\n};\n\n&usb0 {\n\tstatus = \"okay\";\n};\n\n&usb_phy {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9533_tplink_cpe210-v2.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9533_tplink_cpe210.dtsi\"\n\n/ {\n\tcompatible = \"tplink,cpe210-v2\", \"qca,qca9533\";\n\tmodel = \"TP-Link CPE210 v2\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9533_tplink_cpe210-v3.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9533_tplink_cpe210.dtsi\"\n\n/ {\n\tcompatible = \"tplink,cpe210-v3\", \"qca,qca9533\";\n\tmodel = \"TP-Link CPE210 v3\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9533_tplink_cpe210.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9533_tplink_cpexxx.dtsi\"\n\n&leds {\n\tlan {\n\t\tlabel = \"green:lan\";\n\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t};\n};\n\n&eth1 {\n\tcompatible = \"syscon\", \"simple-mfd\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9533_tplink_cpe220-v3.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9533_tplink_cpexxx.dtsi\"\n\n/ {\n\tcompatible = \"tplink,cpe220-v3\", \"qca,qca9533\";\n\tmodel = \"TP-Link CPE220 v3\";\n};\n\n&leds {\n\tlan0 {\n\t\tlabel = \"green:lan0\";\n\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t};\n\n\tlan1 {\n\t\tlabel = \"green:lan1\";\n\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t};\n};\n\n&eth1 {\n\tnvmem-cells = <&macaddr_info_8>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tgmac-config {\n\t\tdevice = <&gmac>;\n\t\tswitch-phy-swap = <0>;\n\t\tswitch-only-mode = <1>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9533_tplink_cpexxx.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca953x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\taliases {\n\t\tled-boot = &led_link4;\n\t\tled-failsafe = &led_link4;\n\t\tled-running = &led_link4;\n\t\tled-upgrade = &led_link4;\n\t\tlabel-mac-device = &wmac;\n\t};\n\n\tleds: leds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tlink1 {\n\t\t\tlabel = \"green:link1\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlink2 {\n\t\t\tlabel = \"green:link2\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlink3 {\n\t\t\tlabel = \"green:link3\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_link4: link4 {\n\t\t\tlabel = \"green:link4\";\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"Reset button\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tuboot: partition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x020000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tlabel = \"partition-table\";\n\t\t\t\treg = <0x020000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tinfo: partition@30000 {\n\t\t\t\tlabel = \"info\";\n\t\t\t\treg = <0x030000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x040000 0x780000>;\n\t\t\t\tcompatible = \"tplink,firmware\";\n\t\t\t};\n\n\t\t\tconfig: partition@7c0000 {\n\t\t\t\tlabel = \"config\";\n\t\t\t\treg = <0x7c0000 0x030000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tart: partition@7f0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0x7f0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tphy-handle = <&swphy4>;\n\n\tnvmem-cells = <&macaddr_info_8>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n\tnvmem-cells = <&macaddr_info_8>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&info {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_info_8: macaddr@8 {\n\t\treg = <0x8 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9533_tplink_tl-wa801nd-v3.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9533_tplink_tl-wa801nd.dtsi\"\n\n/ {\n\tcompatible = \"tplink,tl-wa801nd-v3\", \"qca,qca9533\";\n\tmodel = \"TP-Link TL-WA801ND v3\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9533_tplink_tl-wa801nd-v4.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9533_tplink_tl-wa801nd.dtsi\"\n\n/ {\n\tcompatible = \"tplink,tl-wa801nd-v4\", \"qca,qca9533\";\n\tmodel = \"TP-Link TL-WA801ND v4\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9533_tplink_tl-wa801nd.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca953x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\taliases {\n\t\tlabel-mac-device = &wmac;\n\t\tled-boot = &led_system;\n\t\tled-failsafe = &led_system;\n\t\tled-running = &led_system;\n\t\tled-upgrade = &led_system;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tlan {\n\t\t\tlabel = \"green:lan\";\n\t\t\tgpios = <&gpio 3 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tsecurity_red {\n\t\t\tlabel = \"red:security\";\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\twlan {\n\t\t\tlabel = \"green:wlan\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\tled_system: system {\n\t\t\tlabel = \"green:system\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tsecurity_green {\n\t\t\tlabel = \"green:security\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"Reset button\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 2 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"WPS button\";\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tgpios = <&gpio 1 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tuboot: partition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x020000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tcompatible = \"tplink,firmware\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x020000 0x3d0000>;\n\t\t\t};\n\n\t\t\tart: partition@3f0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0x3f0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tphy-handle = <&swphy4>;\n\n\tnvmem-cells = <&macaddr_uboot_1fc00>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&eth1 {\n\tcompatible = \"syscon\", \"simple-mfd\";\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n\tnvmem-cells = <&macaddr_uboot_1fc00>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&uboot {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_uboot_1fc00: macaddr@1fc00 {\n\t\treg = <0x1fc00 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9533_tplink_tl-wa850re-v2.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca953x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"tplink,tl-wa850re-v2\", \"qca,qca9533\";\n\tmodel = \"TP-Link TL-WA850RE v2\";\n\n\taliases {\n\t\tled-boot = &led_re;\n\t\tled-failsafe = &led_re;\n\t\tled-running = &led_re;\n\t\tled-upgrade = &led_re;\n\t\tlabel-mac-device = &wmac;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tpinctrl-names = \"default\";\n\t\tpinctrl-0 = <&jtag_disable_pins>;\n\n\t\tlan {\n\t\t\tlabel = \"blue:lan\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_re: re {\n\t\t\tlabel = \"blue:re\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tsignal1 {\n\t\t\tlabel = \"blue:signal1\";\n\t\t\tgpios = <&gpio 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tsignal2 {\n\t\t\tlabel = \"blue:signal2\";\n\t\t\tgpios = <&gpio 1 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tsignal3 {\n\t\t\tlabel = \"blue:signal3\";\n\t\t\tgpios = <&gpio 2 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tsignal4 {\n\t\t\tlabel = \"blue:signal4\";\n\t\t\tgpios = <&gpio 3 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_signal5: signal5 {\n\t\t\tlabel = \"blue:signal5\";\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan {\n\t\t\tlabel = \"blue:wlan\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"Reset button\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"WPS button\";\n\t\t\tlinux,code = <KEY_RFKILL>;\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&gpio {\n\tled_enable {\n\t\tgpio-hog;\n\t\tgpios = <15 GPIO_ACTIVE_HIGH>;\n\t\tline-name = \"tp-link:power:led\";\n\t\toutput-high;\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x020000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x020000 0x390000>;\n\t\t\t\tcompatible = \"tplink,firmware\";\n\t\t\t};\n\n\t\t\tpartition@3b0000 {\n\t\t\t\tlabel = \"partition-table\";\n\t\t\t\treg = <0x3b0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tinfo: partition@3c0000 {\n\t\t\t\tlabel = \"info\";\n\t\t\t\treg = <0x3c0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@3d0000 {\n\t\t\t\tlabel = \"config\";\n\t\t\t\treg = <0x3d0000 0x020000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tart: partition@3f0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0x3f0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tphy-handle = <&swphy4>;\n\n\tnvmem-cells = <&macaddr_info_8>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&eth1 {\n\tcompatible = \"syscon\", \"simple-mfd\";\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n\tnvmem-cells = <&macaddr_info_8>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&info {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_info_8: macaddr@8 {\n\t\treg = <0x8 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9533_tplink_tl-wr802n-v1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9533_tplink_tl-wr802n.dtsi\"\n\n/ {\n\tmodel = \"TP-Link TL-WR802N v1\";\n\tcompatible = \"tplink,tl-wr802n-v1\", \"qca,qca9533\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9533_tplink_tl-wr802n-v2.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9533_tplink_tl-wr802n.dtsi\"\n\n/ {\n\tmodel = \"TP-Link TL-WR802N v2\";\n\tcompatible = \"tplink,tl-wr802n-v2\", \"qca,qca9533\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9533_tplink_tl-wr802n.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca953x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\taliases {\n\t\tled-boot = &led_system;\n\t\tled-failsafe = &led_system;\n\t\tled-running = &led_system;\n\t\tled-upgrade = &led_system;\n\t\tlabel-mac-device = &wmac;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_system: system {\n\t\t\tlabel = \"green:system\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"Reset button\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <50000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tuboot: partition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x020000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x020000 0x3d0000>;\n\t\t\t\tcompatible = \"tplink,firmware\";\n\t\t\t};\n\n\t\t\tart: partition@3f0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0x3f0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tphy-handle = <&swphy4>;\n\n\tnvmem-cells = <&macaddr_uboot_1fc00>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <1>;\n};\n\n&eth1 {\n\tcompatible = \"syscon\", \"simple-mfd\";\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n\tnvmem-cells = <&macaddr_uboot_1fc00>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&uboot {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_uboot_1fc00: macaddr@1fc00 {\n\t\treg = <0x1fc00 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9533_tplink_tl-wr810n-v2.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca953x_tplink_tl-wr810n.dtsi\"\n\n/ {\n\tcompatible = \"tplink,tl-wr810n-v2\", \"qca,qca9533\";\n\tmodel = \"TP-Link TL-WR810N v2\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9533_tplink_tl-wr841-v10.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9533_tplink_tl-wr841.dtsi\"\n\n/ {\n\tcompatible = \"tplink,tl-wr841-v10\", \"qca,qca9533\";\n\tmodel = \"TP-Link TL-WR841N/ND v10\";\n\n\taliases {\n\t\tled-boot = &led_qss;\n\t\tled-failsafe = &led_qss;\n\t\tled-running = &led_qss;\n\t\tled-upgrade = &led_qss;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9533_tplink_tl-wr841-v11.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9533_tplink_tl-wr841-v11.dtsi\"\n\n/ {\n\tcompatible = \"tplink,tl-wr841-v11\", \"qca,qca9533\";\n\tmodel = \"TP-Link TL-WR841N/ND v11\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9533_tplink_tl-wr841-v11.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9533_tplink_tl-wr841.dtsi\"\n\n/ {\n\taliases {\n\t\tled-boot = &led_system;\n\t\tled-failsafe = &led_system;\n\t\tled-running = &led_system;\n\t\tled-upgrade = &led_system;\n\t};\n};\n\n&leds {\n\tled_system: system {\n\t\tlabel = \"green:system\";\n\t\tgpios = <&gpio 1 GPIO_ACTIVE_LOW>;\n\t};\n\n\twan_orange {\n\t\tlabel = \"orange:wan\";\n\t\tgpios = <&gpio 2 GPIO_ACTIVE_LOW>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9533_tplink_tl-wr841-v12.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9533_tplink_tl-wr841-v11.dtsi\"\n\n/ {\n\tcompatible = \"tplink,tl-wr841-v12\", \"qca,qca9533\";\n\tmodel = \"TP-Link TL-WR841N/ND v12\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9533_tplink_tl-wr841-v9.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9533_tplink_tl-wr841.dtsi\"\n\n/ {\n\tcompatible = \"tplink,tl-wr841-v9\", \"qca,qca9533\";\n\tmodel = \"TP-Link TL-WR841N/ND v9\";\n\n\taliases {\n\t\tled-boot = &led_qss;\n\t\tled-failsafe = &led_qss;\n\t\tled-running = &led_qss;\n\t\tled-upgrade = &led_qss;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9533_tplink_tl-wr841.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca953x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\taliases {\n\t\tlabel-mac-device = &wmac;\n\t};\n\n\tleds: leds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twifi {\n\t\t\tlabel = \"green:wlan\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\tled_qss: qss {\n\t\t\tlabel = \"green:qss\";\n\t\t\tgpios = <&gpio 3 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twan {\n\t\t\tlabel = \"green:wan\";\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan1 {\n\t\t\tlabel = \"green:lan1\";\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan2 {\n\t\t\tlabel = \"green:lan2\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan3 {\n\t\t\tlabel = \"green:lan3\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan4 {\n\t\t\tlabel = \"green:lan4\";\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"Reset button\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\trfkill {\n\t\t\tlabel = \"RFKILL button\";\n\t\t\tlinux,code = <KEY_RFKILL>;\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tuboot: partition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x020000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tcompatible = \"tplink,firmware\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x020000 0x3d0000>;\n\t\t\t};\n\n\t\t\tart: partition@3f0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0x3f0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tphy-handle = <&swphy4>;\n\n\tnvmem-cells = <&macaddr_uboot_1fc00>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <1>;\n};\n\n&eth1 {\n\tnvmem-cells = <&macaddr_uboot_1fc00>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n\tnvmem-cells = <&macaddr_uboot_1fc00>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&uboot {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_uboot_1fc00: macaddr@1fc00 {\n\t\treg = <0x1fc00 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9533_tplink_tl-wr841hp-v3.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca953x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"tplink,tl-wr841hp-v3\", \"qca,qca9533\";\n\tmodel = \"TP-Link TL-WR841HP v3\";\n\n\taliases {\n\t\tlabel-mac-device = &wmac;\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twifi {\n\t\t\tlabel = \"green:wifi\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\tled_power: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\twan_green {\n\t\t\tlabel = \"green:wan\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twan_amber {\n\t\t\tlabel = \"amber:wan\";\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan {\n\t\t\tlabel = \"green:lan\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tre {\n\t\t\tlabel = \"green:re\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"Reset button\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 1 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\twifi {\n\t\t\tlabel = \"WiFi button\";\n\t\t\tlinux,code = <KEY_RFKILL>;\n\t\t\tgpios = <&gpio 0 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"WPS button\";\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tgpios = <&gpio 2 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\tre {\n\t\t\tlabel = \"RE button\";\n\t\t\tlinux,code = <BTN_0>;\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tuboot: partition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x020000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tcompatible = \"tplink,firmware\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x020000 0x7d0000>;\n\t\t\t};\n\n\t\t\tart: partition@7f0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0x7f0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tphy-handle = <&swphy4>;\n\n\tnvmem-cells = <&macaddr_uboot_1fc00>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <1>;\n};\n\n&eth1 {\n\tnvmem-cells = <&macaddr_uboot_1fc00>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n\tnvmem-cells = <&macaddr_uboot_1fc00>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&uboot {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_uboot_1fc00: macaddr@1fc00 {\n\t\treg = <0x1fc00 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9533_tplink_tl-wr842n-v3.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca953x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"tplink,tl-wr842n-v3\", \"qca,qca9533\";\n\tmodel = \"TP-Link TL-WR842N v3\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t\tlabel-mac-device = &eth1;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 2 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\twifi {\n\t\t\tlabel = \"green:wlan\";\n\t\t\tgpios = <&gpio 3 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\tqss {\n\t\t\tlabel = \"green:qss\";\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twan_green {\n\t\t\tlabel = \"green:wan\";\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twan_red {\n\t\t\tlabel = \"red:wan\";\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan1 {\n\t\t\tlabel = \"green:lan1\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan2 {\n\t\t\tlabel = \"green:lan2\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan3 {\n\t\t\tlabel = \"green:lan3\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan4 {\n\t\t\tlabel = \"green:lan4\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tusb {\n\t\t\tlabel = \"green:usb\";\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t\ttrigger-sources = <&hub_port>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"Reset button\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 1 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\trfkill {\n\t\t\tlabel = \"RFKILL button\";\n\t\t\tlinux,code = <KEY_RFKILL>;\n\t\t\tgpios = <&gpio 0 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n};\n\n&usb0 {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\tstatus = \"okay\";\n\n\thub_port: port@1 {\n\t\treg = <1>;\n\t\t#trigger-source-cells = <0>;\n\t};\n};\n\n&usb_phy {\n\tstatus = \"okay\";\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tuboot: partition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x020000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tcompatible = \"tplink,firmware\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x020000 0xfd0000>;\n\t\t\t};\n\n\t\t\tart: partition@ff0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0xff0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tphy-handle = <&swphy4>;\n\n\tnvmem-cells = <&macaddr_uboot_1fc00>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <1>;\n};\n\n&eth1 {\n\tnvmem-cells = <&macaddr_uboot_1fc00>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n\tnvmem-cells = <&macaddr_uboot_1fc00>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&uboot {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_uboot_1fc00: macaddr@1fc00 {\n\t\treg = <0x1fc00 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9533_ubnt_aircube-isp.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca953x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"ubnt,aircube-isp\", \"qca,qca9533\";\n\tmodel = \"Ubiquiti airCube ISP\";\n\n\taliases {\n\t\tlabel-mac-device = &wmac;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x040000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x050000 0xf60000>;\n\t\t\t};\n\n\t\t\tpartition@fb0000 {\n\t\t\t\tlabel = \"cfg\";\n\t\t\t\treg = <0xfb0000 0x040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tart: partition@ff0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0xff0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tphy-handle = <&swphy4>;\n\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&eth1 {\n\tnvmem-cells = <&macaddr_art_6>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tgmac-config {\n\t\tdevice = <&gmac>;\n\t};\n};\n\n&wmac {\n\tstatus = \"okay\";\n\tmtd-cal-data = <&art 0x1000>;\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n\n\tmacaddr_art_6: macaddr@6 {\n\t\treg = <0x6 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9533_yuncore_a930.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca953x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"yuncore,a930\", \"qca,qca9533\";\n\tmodel = \"YunCore A930\";\n\n\taliases {\n\t\tlabel-mac-device = &eth1;\n\t\tled-boot = &led_system;\n\t\tled-failsafe = &led_system;\n\t\tled-running = &led_system;\n\t\tled-upgrade = &led_system;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_system: system {\n\t\t\tlabel = \"green:system\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"keep\";\n\t\t};\n\n\t\twlan2g {\n\t\t\tlabel = \"blue:wlan2g\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x040000 0x010000>;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x050000 0xfa0000>;\n\t\t\t};\n\n\t\t\tart: partition@ff0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0xff0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tphy-handle = <&swphy4>;\n\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&eth1 {\n\tnvmem-cells = <&macaddr_art_6>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wmac {\n\tstatus = \"okay\";\n\tmtd-cal-data = <&art 0x1000>;\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n\n\tmacaddr_art_6: macaddr@6 {\n\t\treg = <0x6 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca953x.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ath79.dtsi\"\n\n/ {\n\tcompatible = \"qca,qca9530\";\n\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200n8\";\n\t};\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu@0 {\n\t\t\tdevice_type = \"cpu\";\n\t\t\tcompatible = \"mips,mips24Kc\";\n\t\t\tclocks = <&pll ATH79_CLK_CPU>;\n\t\t\treg = <0>;\n\t\t};\n\t};\n\n\textosc: ref {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-output-names = \"ref\";\n\t\tclock-frequency = <25000000>;\n\t};\n\n\tahb {\n\t\tapb {\n\t\t\tddr_ctrl: memory-controller@18000000 {\n\t\t\t\tcompatible = \"qca,qca9530-ddr-controller\",\n\t\t\t\t\t\t\"qca,ar7240-ddr-controller\";\n\t\t\t\treg = <0x18000000 0x128>;\n\n\t\t\t\t#qca,ddr-wb-channel-cells = <1>;\n\t\t\t};\n\n\t\t\tuart: uart@18020000 {\n\t\t\t\tcompatible = \"ns16550a\";\n\t\t\t\treg = <0x18020000 0x20>;\n\n\t\t\t\tinterrupts = <3>;\n\n\t\t\t\tclocks = <&pll ATH79_CLK_REF>;\n\t\t\t\tclock-names = \"uart\";\n\n\t\t\t\treg-io-width = <4>;\n\t\t\t\treg-shift = <2>;\n\t\t\t\tno-loopback-test;\n\t\t\t};\n\n\t\t\tusb_phy: usb-phy@18030000 {\n\t\t\t\tcompatible = \"qca,ar7200-usb-phy\";\n\t\t\t\treg = <0x18030000 0x100>;\n\t\t\t\t#phy-cells = <0>;\n\n\t\t\t\treset-names = \"usb-phy-analog\", \"usb-phy\", \"usb-suspend-override\";\n\t\t\t\tresets = <&rst 11>, <&rst 4>, <&rst 3>;\n\n\t\t\t\tstatus = \"disabled\";\n\t\t\t};\n\n\t\t\tgpio: gpio@18040000 {\n\t\t\t\tcompatible = \"qca,qca9530-gpio\",\n\t\t\t\t\t\t\"qca,ar9340-gpio\";\n\t\t\t\treg = <0x18040000 0x28>;\n\n\t\t\t\tinterrupts = <2>;\n\t\t\t\tngpios = <20>;\n\n\t\t\t\tgpio-controller;\n\t\t\t\t#gpio-cells = <2>;\n\n\t\t\t\tinterrupt-controller;\n\t\t\t\t#interrupt-cells = <2>;\n\t\t\t};\n\n\t\t\tpinmux: pinmux@1804002c {\n\t\t\t\tcompatible = \"pinctrl-single\";\n\n\t\t\t\treg = <0x1804002c 0x48>;\n\n\t\t\t\t#size-cells = <0>;\n\n\t\t\t\tpinctrl-single,bit-per-mux;\n\t\t\t\tpinctrl-single,register-width = <32>;\n\t\t\t\tpinctrl-single,function-mask = <0x1>;\n\t\t\t\t#pinctrl-cells = <2>;\n\n\t\t\t\tjtag_disable_pins: pinmux_jtag_disable_pins {\n\t\t\t\t\tpinctrl-single,bits = <0x40 0x2 0x2>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tpll: pll-controller@18050000 {\n\t\t\t\tcompatible = \"qca,qca9530-pll\", \"syscon\";\n\t\t\t\treg = <0x18050000 0x48>;\n\n\t\t\t\t#clock-cells = <1>;\n\t\t\t\tclock-output-names = \"cpu\", \"ddr\", \"ahb\";\n\t\t\t\tclocks = <&extosc>;\n\t\t\t};\n\n\t\t\twdt: wdt@18060008 {\n\t\t\t\tcompatible = \"qca,qca9530-wdt\", \"qca,ar7130-wdt\";\n\t\t\t\treg = <0x18060008 0x8>;\n\n\t\t\t\tinterrupts = <4>;\n\n\t\t\t\tclocks = <&pll ATH79_CLK_AHB>;\n\t\t\t\tclock-names = \"wdt\";\n\t\t\t};\n\n\t\t\trst: reset-controller@1806001c {\n\t\t\t\tcompatible = \"qca,qca9530-reset\",\n\t\t\t\t\t\t\"qca,ar7100-reset\";\n\t\t\t\treg = <0x1806001c 0xac>;\n\n\t\t\t\t#reset-cells = <1>;\n\n\t\t\t\tintc2: interrupt-controller {\n\t\t\t\t\tcompatible = \"qca,ar9340-intc\";\n\n\t\t\t\t\tinterrupt-parent = <&cpuintc>;\n\t\t\t\t\tinterrupts = <2>;\n\n\t\t\t\t\tinterrupt-controller;\n\t\t\t\t\t#interrupt-cells = <1>;\n\n\t\t\t\t\tqca,int-status-addr = <0xac>;\n\t\t\t\t\tqca,pending-bits = <0xf>,       /* wmac */\n\t\t\t\t\t\t\t<0x1f0>;        /* pcie rc1 */\n\n\t\t\t\t\tqca,ddr-wb-channel-interrupts = <0>, <1>;\n\t\t\t\t\tqca,ddr-wb-channels = <&ddr_ctrl 4>, <&ddr_ctrl 3>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tgmac: gmac@18070000 {\n\t\t\tcompatible = \"qca,ar9330-gmac\";\n\t\t\treg = <0x18070000 0x4>;\n\t\t};\n\n\t\tpcie0: pcie-controller@180c0000 {\n\t\t\tcompatible = \"qcom,ar7240-pci\";\n\t\t\t#address-cells = <3>;\n\t\t\t#size-cells = <2>;\n\t\t\tbus-range = <0x0 0x0>;\n\t\t\treg = <0x180c0000 0x1000>, /* CRP */\n\t\t\t      <0x180f0000 0x100>,  /* CTRL */\n\t\t\t      <0x14000000 0x1000>; /* CFG */\n\t\t\treg-names = \"crp_base\", \"ctrl_base\", \"cfg_base\";\n\t\t\tranges = <0x2000000 0 0x10000000 0x10000000 0 0x04000000\t/* pci memory */\n\t\t\t\t  0x1000000 0 0x00000000 0x0000000 0 0x000001>;\t\t/* io space */\n\t\t\tinterrupt-parent = <&intc2>;\n\t\t\tinterrupts = <1>;\n\n\t\t\tdevice_type = \"pci\";\n\n\t\t\tresets = <&rst 6>, <&rst 7>;\n\t\t\treset-names = \"hc\", \"phy\";\n\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <1>;\n\n\t\t\tinterrupt-map-mask = <0 0 0 1>;\n\t\t\tinterrupt-map = <0 0 0 0 &pcie0 0>;\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\twmac: wmac@18100000 {\n\t\t\tcompatible = \"qca,qca9530-wmac\";\n\t\t\treg = <0x18100000 0x20000>;\n\n\t\t\tinterrupt-parent = <&intc2>;\n\t\t\tinterrupts = <0>;\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tusb0: usb@1b000000 {\n\t\t\tcompatible = \"generic-ehci\";\n\t\t\treg = <0x1b000000 0x1000>;\n\n\t\t\tinterrupts = <3>;\n\t\t\tresets = <&rst 5>;\n\t\t\treset-names = \"usb-host\";\n\t\t\tdr_mode = \"host\";\n\n\t\t\thas-transaction-translator;\n\t\t\tcaps-offset = <0x100>;\n\n\t\t\tphy-names = \"usb-phy\";\n\t\t\tphys = <&usb_phy>;\n\n\t\t\tstatus = \"disabled\";\n\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tspi: spi@1f000000 {\n\t\t\tcompatible = \"qca,ar934x-spi\";\n\t\t\treg = <0x1f000000 0x1c>;\n\n\t\t\tclocks = <&pll ATH79_CLK_AHB>;\n\n\t\t\tstatus = \"disabled\";\n\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\t};\n};\n\n&cpuintc {\n\tqca,ddr-wb-channel-interrupts = <3>, <4>, <5>;\n\tqca,ddr-wb-channels = <&ddr_ctrl 2>, <&ddr_ctrl 0>,\n\t\t\t\t\t\t<&ddr_ctrl 1>;\n};\n\n&eth0 {\n\tcompatible = \"qca,qca9530-eth\", \"syscon\";\n\tpll-data = <0x82000101 0x80000101 0x80001313>;\n\treg = <0x19000000 0x200\n\t\t0x18070000 0x4>;\n\tpll-reg = <0x4 0x2c 17>;\n\tpll-handle = <&pll>;\n\n\treset-names = \"mac\";\n\tresets = <&rst 9>;\n};\n\n&mdio1 {\n\tstatus = \"okay\";\n\tresets = <&rst 23>;\n\treset-names = \"mdio\";\n\tbuiltin-switch;\n\n\tbuiltin_switch: switch0@1f {\n\t\tcompatible = \"qca,ar8229\";\n\n\t\treg = <0x1f>;\n\t\tresets = <&rst 8>;\n\t\treset-names = \"switch\";\n\t\tphy-mode = \"gmii\";\n\t\tqca,phy4-mii-enable;\n\t\tqca,mib-poll-interval = <500>;\n\n\t\tmdio-bus {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\n\t\t\tswphy0: ethernet-phy@0 {\n\t\t\t\treg = <0>;\n\t\t\t\tphy-mode = \"mii\";\n\t\t\t};\n\n\t\t\tswphy4: ethernet-phy@4 {\n\t\t\t\treg = <4>;\n\t\t\t\tphy-mode = \"mii\";\n\t\t\t};\n\t\t};\n\t};\n};\n\n&eth1 {\n\tstatus = \"okay\";\n\n\tcompatible = \"qca,qca9530-eth\", \"syscon\";\n\tresets = <&rst 13>;\n\treset-names = \"mac\";\n\n\tphy-mode = \"gmii\";\n\n\tfixed-link {\n\t\tspeed = <1000>;\n\t\tfull-duplex;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca953x_dlink_dap-2xxx.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca953x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <50000000>;\n\n\t\tpartitions: partitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x40000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"bdcfg\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tlabel = \"rgdb\";\n\t\t\t\treg = <0x50000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@60000 {\n\t\t\t\tlabel = \"unused\";\n\t\t\t\treg = <0x60000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca953x_tplink_tl-wr810n.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca953x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\taliases {\n\t\tled-boot = &led_system;\n\t\tled-failsafe = &led_system;\n\t\tled-running = &led_system;\n\t\tled-upgrade = &led_system;\n\t\tlabel-mac-device = &eth1;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_system: system {\n\t\t\tlabel = \"blue:system\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"Reset button\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\tswitch_b0 {\n\t\t\tlabel = \"switch_b0\";\n\t\t\tlinux,input-type = <EV_SW>;\n\t\t\tlinux,code = <BTN_0>;\n\t\t\tgpios = <&gpio 1 GPIO_ACTIVE_HIGH>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\tswitch_b1 {\n\t\t\tlabel = \"switch_b1\";\n\t\t\tlinux,input-type = <EV_SW>;\n\t\t\tlinux,code = <BTN_1>;\n\t\t\tgpios = <&gpio 0 GPIO_ACTIVE_HIGH>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tuboot: partition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x020000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tcompatible = \"tplink,firmware\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x020000 0x7d0000>;\n\t\t\t};\n\n\t\t\tart: partition@7f0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0x7f0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tphy-handle = <&swphy4>;\n\n\tnvmem-cells = <&macaddr_uboot_1fc00>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <1>;\n};\n\n&eth1 {\n\tnvmem-cells = <&macaddr_uboot_1fc00>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n\tnvmem-cells = <&macaddr_uboot_1fc00>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&uboot {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_uboot_1fc00: macaddr@1fc00 {\n\t\treg = <0x1fc00 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9550_airtight_c-75.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca955x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/leds/common.h>\n\n/ {\n\tmodel = \"AirTight Networks C-75\";\n\tcompatible = \"airtight,c-75\", \"qca,qca9550\", \"qca,qca9558\";\n\n\taliases {\n\t\tlabel-mac-device = &eth0;\n\t\tled-boot = &led_power_amber;\n\t\tled-running = &led_power_green;\n\t\tled-failsafe = &led_power_amber;\n\t\tled-upgrade = &led_power_amber;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power_amber: power-amber {\n\t\t\tlabel = \"amber:power\";\n\t\t\tcolor = <LED_COLOR_ID_AMBER>;\n\t\t\tfunction = LED_FUNCTION_POWER;\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_power_green: power-green {\n\t\t\tlabel = \"green:power\";\n\t\t\tcolor = <LED_COLOR_ID_GREEN>;\n\t\t\tfunction = LED_FUNCTION_POWER;\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan2g {\n\t\t\tlabel = \"green:wlan2g\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\t};\n\n\tvirtual_flash {\n\t\tcompatible = \"mtd-concat\";\n\t\tdevices = <&fwconcat0 &fwconcat1>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x0 0x1f90000>;\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t};\n\t\t};\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n\tphy-handle = <&phy0>;\n\tpll-data = <0xa6000000 0x00000101 0x00001616>;\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t\tqca,ar8327-initvals = <\n\t\t\t0x04 0x07600000 /* PORT0 PAD MODE CTRL */\n\t\t\t0x0c 0x00080080 /* PORT6 PAD MODE CTRL */\n\t\t\t0x58 0xc935c935 /* LED2 CTRL */\n\t\t\t0x5c 0x03ffff00 /* LED3 CTRL */\n\t\t\t0x7c 0x0000007e /* PORT0_STATUS */\n\t\t\t0x94 0x0000007e /* PORT6_STATUS */\n\t\t>;\n\t};\n};\n\n&eth1 {\n\tstatus = \"okay\";\n\n\tnvmem-cells = <&macaddr_art_6>;\n\tnvmem-cell-names = \"mac-address\";\n\tpll-data = <0x03000101 0x00000101 0x00001616>;\n\n\tfixed-link {\n\t\tspeed = <1000>;\n\t\tfull-duplex;\n\t};\n};\n\n&pcie0 {\n\tstatus = \"okay\";\n\n\twifi@0,0 {\n\t\tcompatible = \"qcom,ath10k\";\n\t\treg = <0x0000 0 0 0 0>;\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x040000 0x010000>;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tlabel = \"wlandrv\";\n\t\t\t\treg = <0x050000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfwconcat0: partition@60000 {\n\t\t\t\tlabel = \"fwconcat0\";\n\t\t\t\treg = <0x060000 0xf90000>;\n\t\t\t};\n\n\t\t\tart: partition@ff0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0xff0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n\n\tflash@1 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <1>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tfwconcat1: partition@0 {\n\t\t\t\tlabel = \"fwconcat1\";\n\t\t\t\treg = <0x0 0x1000000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&usb_phy0 {\n\tstatus = \"okay\";\n};\n\n&usb0 {\n\tstatus = \"okay\";\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n\n\tmacaddr_art_6: macaddr@6 {\n\t\treg = <0x6 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9556_avm_fritz-repeater.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca955x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"urlader\";\n\t\t\t\treg = <0x0 0x20000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tcompatible = \"avm,eva-firmware\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x20000 0xee0000>;\n\t\t\t};\n\n\t\t\tpartition@f00000 {\n\t\t\t\tlabel = \"tffs (1)\";\n\t\t\t\treg = <0xf00000 0x80000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@f80000 {\n\t\t\t\tlabel = \"tffs (2)\";\n\t\t\t\treg = <0xf80000 0x80000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&wmac {\n\tstatus = \"okay\";\n\tqca,no-eeprom;\n};\n\n&eth1 {\n\tstatus = \"okay\";\n\n\tphy-handle = <&phy0>;\n\tpll-data = <0x3000000 0x101 0x1313>;\n\n\tqca955x-sgmii-fixup;\n\n\tgmac-config {\n\t\tdevice = <&gmac>;\n\t\tge0-sgmii = <0>;\n\t};\n};\n\n&mdio1 {\n\tstatus = \"okay\";\n\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t\tat803x-override-sgmii-link-check;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9556_avm_fritz1750e.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9556_avm_fritz-repeater.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n\n/ {\n\tcompatible = \"avm,fritz1750e\", \"qca,qca9556\";\n\tmodel = \"AVM FRITZ!WLAN Repeater 1750E\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tled_spi {\n\t\tcompatible = \"spi-gpio\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tsck-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;\n\t\tmosi-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;\n\t\tnum-chipselects = <0>;\n\n\t\tspi_gpio: led_gpio@0 {\n\t\t\tcompatible = \"fairchild,74hc595\";\n\t\t\treg = <0>;\n\t\t\tgpio-controller;\n\t\t\t#gpio-cells = <2>;\n\t\t\tregisters-number = <1>;\n\t\t\tspi-max-frequency = <10000000>;\n\n\t\t\tgpio_latch_bit {\n\t\t\t\tgpio-hog;\n\t\t\t\tgpios = <7 GPIO_ACTIVE_HIGH>;\n\t\t\t\toutput-high;\n\t\t\t\tline-name = \"gpio-latch-bit\";\n\t\t\t};\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&spi_gpio 6 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\twlan {\n\t\t\tlabel = \"green:wlan\";\n\t\t\tgpios = <&spi_gpio 5 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\n\t\tlan {\n\t\t\tlabel = \"green:lan\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\trssi0 {\n\t\t\tlabel = \"green:rssi0\";\n\t\t\tgpios = <&spi_gpio 0 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\trssi1 {\n\t\t\tlabel = \"green:rssi1\";\n\t\t\tgpios = <&spi_gpio 1 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\trssi2 {\n\t\t\tlabel = \"green:rssi2\";\n\t\t\tgpios = <&spi_gpio 2 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\trssi3 {\n\t\t\tlabel = \"green:rssi3\";\n\t\t\tgpios = <&spi_gpio 3 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\trssi4 {\n\t\t\tlabel = \"green:rssi4\";\n\t\t\tgpios = <&spi_gpio 4 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&pcie0 {\n\tstatus = \"okay\";\n};\n\n&phy0 {\n\treset-gpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n};\n\n&gpio {\n\treset-pcie-ep {\n\t\tgpio-hog;\n\t\tgpios = <17 GPIO_ACTIVE_HIGH>;\n\t\toutput-high;\n\t\tline-name = \"PCIE EP reset\";\n\t};\n\n\treset-pcie {\n\t\tgpio-hog;\n\t\tgpios = <18 GPIO_ACTIVE_HIGH>;\n\t\toutput-high;\n\t\tline-name = \"PCIE Bus reset\";\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9556_avm_fritz450e.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9556_avm_fritz-repeater.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n\n/ {\n\tcompatible = \"avm,fritz450e\", \"qca,qca9556\";\n\tmodel = \"AVM FRITZ!WLAN Repeater 450E\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\twlan {\n\t\t\tlabel = \"green:wlan\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\tlan {\n\t\t\tlabel = \"green:lan\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\trssi2 {\n\t\t\tlabel = \"green:rssi2\";\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\trssi3 {\n\t\t\tlabel = \"green:rssi3\";\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\trssi4 {\n\t\t\tlabel = \"green:rssi4\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&gpio {\n\t/*\n\t * Wondered why rssi0 and rssi1 are missing?\n\t *\n\t * AVM seems to have run low on usable GPIO pins, so\n\t * instead of adding a shift register like they did for\n\t * the 1750E they figured out \"Why not use the LEDs on\n\t * the AR8033?\".\n\t *\n\t * EVA configures the PHY in a way it does not display\n\t * the link-state using it's LEDs. When we reset the PHY\n\t * using the reset-mechanism of the PHY subsystem, this\n\t * setting is cleared.\n\t *\n\t * We avoid this by keeping the reset line high.\n\t */\n\tphy-reset {\n\t\tgpio-hog;\n\t\tgpios = <11 GPIO_ACTIVE_HIGH>;\n\t\toutput-high;\n\t\tline-name = \"phy-reset\";\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9556_avm_fritzdvbc.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9556_avm_fritz-repeater.dtsi\"\n\n/ {\n\tcompatible = \"avm,fritzdvbc\", \"qca,qca9556\";\n\tmodel = \"AVM FRITZ!WLAN Repeater DVB-C\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tled_spi {\n\t\tcompatible = \"spi-gpio\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tsck-gpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\tmosi-gpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\tnum-chipselects = <0>;\n\n\t\tspi_gpio: led_gpio@0 {\n\t\t\tcompatible = \"fairchild,74hc595\";\n\t\t\treg = <0>;\n\t\t\tgpio-controller;\n\t\t\t#gpio-cells = <2>;\n\t\t\tregisters-number = <2>;\n\t\t\tspi-max-frequency = <10000000>;\n\n\t\t\tgpio_latch_bit {\n\t\t\t\tgpio-hog;\n\t\t\t\tgpios = <16 GPIO_ACTIVE_HIGH>;\n\t\t\t\toutput-high;\n\t\t\t\tline-name = \"gpio-latch-bit\";\n\t\t\t};\n\t\t};\n\t};\n\n\t/*\n\t * GPIO pins 100 or greater in the vendor GPL dump are redirected\n\t * to the shift register.\n\t * So OEM source pin 100 becomes 0 on the SR and so forth.\n\t */\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&spi_gpio 6 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan {\n\t\t\tlabel = \"green:wlan\";\n\t\t\tgpios = <&spi_gpio 7 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\n\t\ttv {\n\t\t\tlabel = \"green:tv\";\n\t\t\tgpios = <&spi_gpio 5 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\trssihigh {\n\t\t\tlabel = \"green:rssihigh\";\n\t\t\tgpios = <&spi_gpio 1 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\trssimediumhigh {\n\t\t\tlabel = \"green:rssimediumhigh\";\n\t\t\tgpios = <&spi_gpio 2 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\trssimedium {\n\t\t\tlabel = \"green:rssimedium\";\n\t\t\tgpios = <&spi_gpio 3 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\trssimediumlow {\n\t\t\tlabel = \"green:rssimediumlow\";\n\t\t\tgpios = <&spi_gpio 4 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\trssilow {\n\t\t\tlabel = \"green:rssilow\";\n\t\t\tgpios = <&spi_gpio 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&pcie0 {\n\tstatus = \"okay\";\n};\n\n&gpio {\n\treset-pcie-ep {\n\t\tgpio-hog;\n\t\tgpios = <109 GPIO_ACTIVE_HIGH>;\n\t\toutput-high;\n\t\tline-name = \"PCIE EP reset\";\n\t};\n\n\treset-pcie-bus {\n\t\tgpio-hog;\n\t\tgpios = <110 GPIO_ACTIVE_HIGH>;\n\t\toutput-high;\n\t\tline-name = \"PCIE Bus reset\";\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9556_mikrotik_routerboard-wap-g-5hact2hnd.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca955x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"mikrotik,routerboard-wap-g-5hact2hnd\", \"qca,qca9556\";\n\tmodel = \"MikroTik RouterBOARD wAP G-5HacT2HnD\";\n\n\taliases {\n\t\tmdio-gpio1 = &mdio2;\n\t\tserial0 = &uart;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 1 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tmdio2: mdio {\n\t\tcompatible = \"virtual,mdio-gpio\";\n\n\t\tgpios = <&gpio 12 GPIO_ACTIVE_HIGH>, /* MDC */\n\t\t\t<&gpio 11 GPIO_ACTIVE_HIGH>; /* MDIO */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tphy0: ethernet-phy@0 {\n\t\t\treg = <0>;\n\t\t\tdevice_type = \"ethernet-phy\";\n\n\t\t\tphy-mode = \"sgmii\";\n\n\t\t\tat803x-override-sgmii-link-check;\n\t\t};\n\t};\n};\n\n&eth1 {\n\tstatus = \"okay\";\n\n\tpll-data = <0x03000101 0x80000101 0x80001313>;\n\tphy-handle = <&phy0>;\n\n\tqca955x-sgmii-fixup;\n\n\tgmac-config {\n\t\tdevice = <&gmac>;\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <40000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"RouterBoot\";\n\t\t\t\treg = <0x0 0x20000>;\n\t\t\t\tcompatible = \"mikrotik,routerboot-partitions\";\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\n\t\t\t\tpartition@0 {\n\t\t\t\t\tlabel = \"bootloader1\";\n\t\t\t\t\treg = <0x0 0x0>;\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\thard_config {\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\tbios {\n\t\t\t\t\tsize = <0x1000>;\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\tpartition@10000 {\n\t\t\t\t\tlabel = \"bootloader2\";\n\t\t\t\t\treg = <0x10000 0x0>;\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\tsoft_config {\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tcompatible = \"mikrotik,minor\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x020000 0xfe0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tqca,no-eeprom;\n};\n\n&pcie0 {\n\tstatus = \"okay\";\n\n\twifi@0,0 {\n\t\tcompatible = \"qcom,ath10k\";\n\t\treg = <0 0 0 0 0>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9557_8dev_rambutan.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca955x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"8dev,rambutan\", \"qca,qca9557\";\n\tmodel = \"8devices Rambutan\";\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n};\n\n&nand {\n\tstatus = \"okay\";\n\n\tpartitions {\n\t\tcompatible = \"fixed-partitions\";\n\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"u-boot\";\n\t\t\treg = <0x0 0x300000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@300000 {\n\t\t\tlabel = \"u-boot-env\";\n\t\t\treg = <0x300000 0x200000>;\n\t\t};\n\n\t\tart: partition@500000 {\n\t\t\tlabel = \"art\";\n\t\t\treg = <0x500000 0x100000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@600000 {\n\t\t\tlabel = \"ubi\";\n\t\t\treg = <0x600000 0x7a00000>;\n\t\t};\n\t};\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t\treset-gpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t};\n};\n\n&mdio1 {\n\tstatus = \"okay\";\n\n\tphy1: ethernet-phy@0 {\n\t\treg = <0>;\n\t\treset-gpios = <&gpio 23 GPIO_ACTIVE_LOW>;\n\t\tphy-mode = \"sgmii\";\n\t\tat803x-override-sgmii-link-check;\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n\tphy-mode = \"mii\";\n\tphy-handle = <&phy0>;\n};\n\n&eth1 {\n\tstatus = \"okay\";\n\n\tpll-data = <0x17000000 0x101 0x1313>;\n\tphy-handle = <&phy1>;\n\tqca955x-sgmii-fixup;\n\tnvmem-cells = <&macaddr_art_6>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tgpio-controller;\n\tmtd-cal-data = <&art 0x1000>;\n};\n\n&pcie0 {\n\tstatus = \"okay\";\n};\n\n&usb_phy0 {\n\tstatus = \"okay\";\n};\n\n&usb0 {\n\tstatus = \"okay\";\n\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n};\n\n&usb_phy1 {\n\tstatus = \"okay\";\n};\n\n&usb1 {\n\tstatus = \"okay\";\n\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n\n\tmacaddr_art_6: macaddr@6 {\n\t\treg = <0x6 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9557_araknis_an-500-ap-i-ac.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca955x_senao_loader.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"araknis,an-500-ap-i-ac\", \"qca,qca9557\";\n\tmodel = \"Araknis AN-500-AP-I-AC\";\n\n\taliases {\n\t\tlabel-mac-device = &eth0;\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"amber:power\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\twifi2g {\n\t\t\tlabel = \"blue:wifi2g\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\n\t\twifi5g {\n\t\t\tlabel = \"blue:wifi5g\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"blue:wps\";\n\t\t\tgpios = <&gpio 19 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&partitions {\n\tart: partition@ff0000 {\n\t\tlabel = \"art\";\n\t\treg = <0xff0000 0x010000>;\n\t\tread-only;\n\t};\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy5: ethernet-phy@5 {\n\t\treg = <5>;\n\t\teee-broken-100tx;\n\t\teee-broken-1000t;\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tphy-handle = <&phy5>;\n\tphy-mode = \"rgmii-id\";\n\n\tpll-data = <0x82000000 0x80000101 0x80001313>;\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <1>;\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9557_buffalo_bhr-4grv2.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca955x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"buffalo,bhr-4grv2\", \"qca,qca9557\";\n\tmodel = \"Buffalo BHR-4GRV2\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 19 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\tdiag {\n\t\t\tlabel = \"orange:diag\";\n\t\t\tgpios = <&gpio 20 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tvpn_orange {\n\t\t\tlabel = \"orange:vpn\";\n\t\t\tgpios = <&gpio 3 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tvpn_green {\n\t\t\tlabel = \"green:vpn\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\teco {\n\t\t\tlabel = \"eco\";\n\t\t\tgpios = <&gpio 21 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_0>;\n\t\t\tlinux,input-type = <EV_SW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x040000 0x010000>;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x050000 0xfa0000>;\n\t\t\t};\n\n\t\t\tart: partition@ff0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0xff0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\n\t\tqca,ar8327-initvals = <\n\t\t    0x04 0x80080080 /* PORT0 PAD MODE CTRL */\n\t\t    0x0c 0x07600000 /* PORT6 PAD MODE CTRL */\n\t\t    0x7c 0x0000007e /* PORT0_STATUS */\n\t\t    0x94 0x0000007e /* PORT6 STATUS */\n\t\t>;\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n\tphy-handle = <&phy0>;\n\tpll-data = <0x56000000 0x00000101 0x00001616>;\n};\n\n&eth1 {\n\tstatus = \"okay\";\n\n\tnvmem-cells = <&macaddr_art_6>;\n\tnvmem-cell-names = \"mac-address\";\n\tpll-data = <0x03000101 0x00000101 0x00001616>;\n\n\tfixed-link {\n\t\tspeed = <1000>;\n\t\tfull-duplex;\n\t};\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n\n\tmacaddr_art_6: macaddr@6 {\n\t\treg = <0x6 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9557_dlink_dap-2660-a1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca955x_dlink_dap-2xxx.dtsi\"\n\n/ {\n\tcompatible = \"dlink,dap-2660-a1\", \"qca,qca9557\";\n\tmodel = \"D-Link DAP-2660 A1\";\n\n\taliases {\n\t\tled-boot = &led_power_green;\n\t\tled-failsafe = &led_power_red;\n\t\tled-running = &led_power_green;\n\t\tled-upgrade = &led_power_red;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power_red: power_red {\n\t\t\tlabel = \"red:power\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_power_green: power_green {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n};\n\n&partitions {\n\tpartition@70000 {\n\t\tlabel = \"firmware\";\n\t\treg = <0x70000 0xee0000>;\n\t\tcompatible = \"wrg\";\n\t};\n\n\tpartition@f50000 {\n\t\tlabel = \"dlink\";\n\t\treg = <0xf50000 0xa0000>;\n\t\tread-only;\n\t};\n\n\tart: partition@ff0000 {\n\t\tlabel = \"art\";\n\t\treg = <0xff0000 0x10000>;\n\t\tread-only;\n\t};\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy4: ethernet-phy@4 {\n\t\treg = <4>;\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tpll-data = <0x82000000 0x80000101 0x80001313>;\n\n\tphy-handle = <&phy4>;\n\tphy-mode = \"rgmii-id\";\n\n\tgmac-config {\n\t\tdevice = <&gmac>;\n\t\trgmii-enabled = <1>;\n\t\trxd-delay = <3>;\n\t\trxdv-delay = <3>;\n\t};\n};\n\n&pcie0 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9557_dongwon_dw02-412h-128m.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9557_dongwon_dw02-412h.dtsi\"\n\n/ {\n\tmodel = \"Dongwon T&I DW02-412H (128M)\";\n\tcompatible = \"dongwon,dw02-412h-128m\", \"qca,qca9557\";\n};\n\n&ubi {\n\treg = <0x1800000 0x6800000>;\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9557_dongwon_dw02-412h-64m.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9557_dongwon_dw02-412h.dtsi\"\n\n/ {\n\tmodel = \"Dongwon T&I DW02-412H (64M)\";\n\tcompatible = \"dongwon,dw02-412h-64m\", \"qca,qca9557\";\n};\n\n&ubi {\n\treg = <0x1800000 0x2800000>;\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9557_dongwon_dw02-412h.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca955x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\taliases {\n\t\tled-boot = &led_wan;\n\t\tled-failsafe = &led_wan;\n\t\tled-upgrade = &led_wan;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\twps {\n\t\t\tlabel = \"WPS button\";\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"Reset button\";\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_wan: wan {\n\t\t\tlabel = \"green:wan\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan {\n\t\t\tlabel = \"green:wlan\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <50000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x040000 0x010000>;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tlabel = \"log\";\n\t\t\t\treg = <0x050000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@60000 {\n\t\t\t\tlabel = \"recoverk\";\n\t\t\t\treg = <0x060000 0x0e0000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@140000 {\n\t\t\t\tlabel = \"recoverr\";\n\t\t\t\treg = <0x140000 0x090000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@1d0000 {\n\t\t\t\tlabel = \"nvram\";\n\t\t\t\treg = <0x1d0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@1e0000 {\n\t\t\t\tlabel = \"nvbackup\";\n\t\t\t\treg = <0x1e0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@1f0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0x1f0000 0x010000>;\n\t\t\t\tread-only;\n\n\t\t\t\tcompatible = \"nvmem-cells\";\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\n\t\t\t\tmacaddr_art_0: macaddr@0 {\n\t\t\t\t\treg = <0x0 0x6>;\n\t\t\t\t};\n\n\t\t\t\tcal_art_1000: cal@1000 {\n\t\t\t\t\treg = <0x1000 0x440>;\n\t\t\t\t};\n\n\t\t\t\tcal_art_5000: cal@5000 {\n\t\t\t\t\treg = <0x5000 0x844>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t};\n};\n\n&nand {\n\tstatus = \"okay\";\n\n\tpartitions {\n\t\tcompatible = \"fixed-partitions\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"current\";\n\t\t\treg = <0x0 0x1000000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@1000000 {\n\t\t\tlabel = \"kernel\";\n\t\t\treg = <0x1000000 0x800000>;\n\t\t};\n\n\t\tubi: partition@1800000 {\n\t\t\tlabel = \"ubi\";\n\t\t};\n\t};\n};\n\n&pcie0 {\n\tstatus = \"okay\";\n\n\twifi@0,0 {\n\t\tcompatible = \"qcom,ath10k\";\n\t\treg = <0 0 0 0 0>;\n\n\t\tnvmem-cells = <&macaddr_art_0>, <&cal_art_5000>;\n\t\tnvmem-cell-names = \"mac-address\", \"calibration\";\n\t\tmac-address-increment = <4>;\n\t};\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tnvmem-cells = <&macaddr_art_0>, <&cal_art_1000>;\n\tnvmem-cell-names = \"mac-address\", \"calibration\";\n\tmac-address-increment = <3>;\n};\n\n&usb_phy0 {\n\tstatus = \"okay\";\n};\n\n&usb0 {\n\tstatus = \"okay\";\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\n\t\tqca,ar8327-initvals = <\n\t\t\t0x04 0x07600000 /* PORT0 PAD MODE CTRL */\n\t\t\t0x50 0xcf37cf37 /* LED Control Register 0 */\n\t\t\t0x54 0x00000000 /* LED Control Register 1 */\n\t\t\t0x58 0x00000000 /* LED Control Register 2 */\n\t\t\t0x5c 0x0030c300 /* LED Control Register 3 */\n\t\t\t0x7c 0x0000007e /* PORT0_STATUS */\n\t\t>;\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <1>;\n\tphy-handle = <&phy0>;\n\tpll-data = <0xa6000000 0x00000101 0x00001616>;\n\n\tgmac-config {\n\t\tdevice = <&gmac>;\n\t\trgmii-enabled = <1>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9557_engenius_eap1200h.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca955x_senao_loader.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"engenius,eap1200h\", \"qca,qca9557\";\n\tmodel = \"EnGenius EAP1200H\";\n\n\taliases {\n\t\tlabel-mac-device = &eth0;\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"amber:power\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\twifi2g {\n\t\t\tlabel = \"blue:wifi2g\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\n\t\twifi5g {\n\t\t\tlabel = \"green:wifi5g\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"blue:wps\";\n\t\t\tgpios = <&gpio 19 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&partitions {\n\tart: partition@ff0000 {\n\t\tlabel = \"art\";\n\t\treg = <0xff0000 0x010000>;\n\t\tread-only;\n\t};\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy5: ethernet-phy@5 {\n\t\treg = <5>;\n\t\teee-broken-100tx;\n\t\teee-broken-1000t;\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tphy-handle = <&phy5>;\n\tphy-mode = \"rgmii-id\";\n\n\tpll-data = <0x82000000 0x80000101 0x80001313>;\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <1>;\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9557_engenius_ecb1200.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca955x_engenius_ecb1xxx.dtsi\"\n\n/ {\n\tcompatible = \"engenius,ecb1200\", \"qca,qca9557\";\n\tmodel = \"EnGenius ECB1200\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9557_engenius_enstationac-v1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca955x_senao_loader.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"engenius,enstationac-v1\", \"qca,qca9557\";\n\tmodel = \"EnGenius EnStationAC v1\";\n\n\taliases {\n\t\tlabel-mac-device = &eth0;\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"amber:power\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\twlan {\n\t\t\tlabel = \"green:wlan\";\n\t\t\tgpios = <&gpio 21 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\trssilow {\n\t\t\tlabel = \"red:rssilow\";\n\t\t\tgpios = <&gpio 19 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\trssimedium {\n\t\t\tlabel = \"amber:rssimedium\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\trssihigh {\n\t\t\tlabel = \"green:rssihigh\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&partitions {\n\tart: partition@ff0000 {\n\t\tlabel = \"art\";\n\t\treg = <0xff0000 0x010000>;\n\t\tread-only;\n\t};\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy1: ethernet-phy@1 {\n\t\treg = <1>;\n\t\teee-broken-100tx;\n\t\teee-broken-1000t;\n\t};\n\n\tphy2: ethernet-phy@2 {\n\t\treg = <2>;\n\t\teee-broken-100tx;\n\t\teee-broken-1000t;\n\t\tat803x-override-sgmii-link-check;\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tphy-handle = <&phy1>;\n\tphy-mode = \"rgmii-id\";\n\n\tpll-data = <0x82000000 0x80000101 0x80001313>;\n};\n\n&eth1 {\n\tstatus = \"okay\";\n\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <1>;\n\n\tphy-handle = <&phy2>;\n\n\tpll-data = <0x03000000 0x00000101 0x00001313>;\n\n\tqca955x-sgmii-fixup;\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9557_iodata_wn-ac-dgr.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca955x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tleds: leds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\teco {\n\t\t\tlabel = \"green:eco\";\n\t\t\tgpios = <&gpio 3 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan5g {\n\t\t\tlabel = \"green:wlan5g\";\n\t\t\tgpios = <&gpio 21 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\twlan2g {\n\t\t\tlabel = \"green:wlan2g\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\n\t\tnotification {\n\t\t\tlabel = \"amber:notification\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys: keys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\teco {\n\t\t\tlabel = \"eco\";\n\t\t\tgpios = <&gpio 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_1>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\tauto {\n\t\t\tlabel = \"auto\";\n\t\t\tgpios = <&gpio 1 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_0>;\n\t\t\tlinux,input-type = <EV_SW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\trouter {\n\t\t\tlabel = \"router\";\n\t\t\tgpios = <&gpio 19 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_0>;\n\t\t\tlinux,input-type = <EV_SW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x030000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x030000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x040000 0xe50000>;\n\t\t\t};\n\n\t\t\tpartition@e90000 {\n\t\t\t\tlabel = \"manufacture\";\n\t\t\t\treg = <0xe90000 0x100000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@f90000 {\n\t\t\t\tlabel = \"backup\";\n\t\t\t\treg = <0xf90000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@fa0000 {\n\t\t\t\tlabel = \"storage\";\n\t\t\t\treg = <0xfa0000 0x050000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tart: partition@ff0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0xff0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\n\t\tqca,ar8327-initvals = <\n\t\t\t0x04 0x87600000 /* PORT0 PAD MODE CTRL */\n\t\t\t0x7c 0x0000007e /* PORT0_STATUS */\n\t\t>;\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tpll-data = <0xa6000000 0x00000101 0x00001616>;\n\tphy-handle = <&phy0>;\n};\n\n&pcie1 {\n\tstatus = \"okay\";\n\n\twifi@0,0 {\n\t\tcompatible = \"pci168c,003c\";\n\t\treg = <0x0000 0 0 0 0>;\n\t};\n};\n\n&usb_phy0 {\n\tstatus = \"okay\";\n};\n\n&usb0 {\n\tstatus = \"okay\";\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tqca,no-eeprom;\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9557_iodata_wn-ac1167dgr.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9557_iodata_wn-ac-dgr.dtsi\"\n\n/ {\n\tcompatible = \"iodata,wn-ac1167dgr\", \"qca,qca9557\";\n\tmodel = \"I-O DATA WN-AC1167DGR\";\n};\n\n&leds {\n\tcopy {\n\t\tlabel = \"green:copy\";\n\t\tgpios = <&gpio 2 GPIO_ACTIVE_LOW>;\n\t};\n};\n\n&keys {\n\tcopy {\n\t\tlabel = \"copy\";\n\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\tlinux,code = <BTN_1>;\n\t\tdebounce-interval = <60>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9557_iodata_wn-ac1600dgr.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9557_iodata_wn-ac-dgr.dtsi\"\n\n/ {\n\tcompatible = \"iodata,wn-ac1600dgr\", \"qca,qca9557\";\n\tmodel = \"I-O DATA WN-AC1600DGR\";\n};\n\n&leds {\n\tfunction {\n\t\tlabel = \"green:function\";\n\t\tgpios = <&gpio 2 GPIO_ACTIVE_LOW>;\n\t};\n};\n\n&keys {\n\tfunction {\n\t\tlabel = \"function\";\n\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\tlinux,code = <BTN_1>;\n\t\tdebounce-interval = <60>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9557_iodata_wn-ac1600dgr2.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9557_iodata_wn-ac-dgr.dtsi\"\n\n/ {\n\tcompatible = \"iodata,wn-ac1600dgr2\", \"iodata,wn-ac1600dgr3\", \"qca,qca9557\";\n\tmodel = \"I-O DATA WN-AC1600DGR2/DGR3\";\n};\n\n&leds {\n\tcopy {\n\t\tlabel = \"green:copy\";\n\t\tgpios = <&gpio 2 GPIO_ACTIVE_LOW>;\n\t};\n};\n\n&keys {\n\tcopy {\n\t\tlabel = \"copy\";\n\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\tlinux,code = <BTN_1>;\n\t\tdebounce-interval = <60>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9557_zyxel_nbg6616.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca955x_zyxel_nbg6x16.dtsi\"\n\n/ {\n\tcompatible = \"zyxel,nbg6616\", \"qca,qca9557\";\n\tmodel = \"ZyXEL NBG6616\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tusb1 {\n\t\t\tlabel = \"green:usb1\";\n\t\t\tgpios = <&gpio 21 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t\ttrigger-sources = <&hub_port0>;\n\t\t};\n\n\t\tusb2 {\n\t\t\tlabel = \"green:usb2\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t\ttrigger-sources = <&hub_port1>;\n\t\t};\n\n\t\twifi2g {\n\t\t\tlabel = \"green:wifi2g\";\n\t\t\tgpios = <&gpio 19 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\n\t\twifi5g {\n\t\t\tlabel = \"green:wifi5g\";\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&gpio 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&gpio_usb_power {\n\tline-name = \"nbg6616:power:usb\";\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x030000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x030000 0x010000>;\n\t\t\t};\n\n\t\t\tart: partition@40000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0x040000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tlabel = \"zyxel_rfsd\";\n\t\t\t\treg = <0x050000 0x060000>;\n\t\t\t};\n\n\t\t\tpartition@b0000 {\n\t\t\t\tlabel = \"romd\";\n\t\t\t\treg = <0x0b0000 0x060000>;\n\t\t\t};\n\n\t\t\tpartition@110000 {\n\t\t\t\tlabel = \"header\";\n\t\t\t\treg = <0x110000 0x010000>;\n\t\t\t};\n\n\t\t\tpartition@120000 {\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x120000 0xee0000>;\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pcie1 {\n\tstatus = \"okay\";\n\n\twifi@0,0 {\n\t\tcompatible = \"qcom,ath10k\";\n\t\treg = <0 0 0 0 0>;\n\t\tqca,no-eeprom;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9558_allnet_all-wap02860ac.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca955x_senao_loader.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"allnet,all-wap02860ac\", \"qca,qca9558\";\n\tmodel = \"ALLNET ALL-WAP02860AC\";\n\n\taliases {\n\t\tlabel-mac-device = &eth0;\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"amber:power\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\twlan2g {\n\t\t\tlabel = \"blue:wlan2g\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\n\t\twlan5g {\n\t\t\tlabel = \"green:wlan5g\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"blue:wps\";\n\t\t\tgpios = <&gpio 19 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tphy-handle = <&phy5>;\n\tphy-mode = \"rgmii-id\";\n\n\tpll-data = <0x82000000 0x80000101 0x80001313>;\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy5: ethernet-phy@5 {\n\t\treg = <5>;\n\t\teee-broken-100tx;\n\t\teee-broken-1000t;\n\t};\n};\n\n&partitions {\n\tart: partition@ff0000 {\n\t\tlabel = \"art\";\n\t\treg = <0xff0000 0x010000>;\n\t\tread-only;\n\t};\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <1>;\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9558_araknis_an-700-ap-i-ac.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca955x_senao_loader.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"araknis,an-700-ap-i-ac\", \"qca,qca9558\";\n\tmodel = \"Araknis AN-700-AP-I-AC\";\n\n\taliases {\n\t\tlabel-mac-device = &eth0;\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"amber:power\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\twifi2g {\n\t\t\tlabel = \"blue:wifi2g\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\n\t\twifi5g {\n\t\t\tlabel = \"blue:wifi5g\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"blue:wps\";\n\t\t\tgpios = <&gpio 19 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&partitions {\n\tart: partition@ff0000 {\n\t\tlabel = \"art\";\n\t\treg = <0xff0000 0x010000>;\n\t\tread-only;\n\t};\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy5: ethernet-phy@5 {\n\t\treg = <5>;\n\t\teee-broken-100tx;\n\t\teee-broken-1000t;\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tphy-handle = <&phy5>;\n\tphy-mode = \"rgmii-id\";\n\n\tpll-data = <0x82000000 0x80000101 0x80001313>;\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <1>;\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9558_belkin_f9j1108-v2.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9558_belkin_f9x-v2.dtsi\"\n\n/ {\n\tmodel = \"Belkin F9J1108 v2 (AC1750 DB Wi-Fi)\";\n\tcompatible = \"belkin,f9j1108-v2\", \"qca,qca9558\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9558_belkin_f9k1115-v2.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9558_belkin_f9x-v2.dtsi\"\n\n/ {\n\tmodel = \"Belkin F9K1115 v2 (AC 1750 DB)\";\n\tcompatible = \"belkin,f9k1115-v2\", \"qca,qca9558\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9558_belkin_f9x-v2.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca955x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/mtd/partitions/uimage.h>\n\n/ {\n\taliases {\n\t\tled-boot = &led_system;\n\t\tled-failsafe = &led_system;\n\t\tled-running = &led_system;\n\t\tled-upgrade = &led_system;\n\t\tlabel-mac-device = &eth1;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tusb {\n\t\t\tlabel = \"green:usb2\";\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_LOW>;\n\t\t\ttrigger-sources = <&hub_port0>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\n\t\tstatus {\n\t\t\tlabel = \"amber:status\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twps-amber {\n\t\t\tlabel = \"amber:wps\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twps-blue {\n\t\t\tlabel = \"blue:wps\";\n\t\t\tgpios = <&gpio 19 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_system: system {\n\t\t\tlabel = \"blue:system\";\n\t\t\tgpios = <&gpio 20 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tgpio-export {\n\t\tcompatible = \"gpio-export\";\n\t\t#size-cells = <0>;\n\n\t\tusb2_power {\n\t\t\tgpio-export,name = \"usb2:power\";\n\t\t\tgpio-export,output = <1>;\n\t\t\tgpios = <&gpio 21 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\twps {\n\t\t\tlabel = \"WPS button\";\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"Reset button\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tvirtual_flash {\n\t\tcompatible = \"mtd-concat\";\n\n\t\tdevices = <&fwconcat0 &fwconcat1>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tcompatible = \"openwrt,uimage\", \"denx,uimage\";\n\t\t\t\topenwrt,ih-magic = <IH_MAGIC_OKLI>;\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x0 0x0>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pcie1 {\n\tstatus = \"okay\";\n};\n\n&usb_phy0 {\n\tstatus = \"okay\";\n};\n\n&usb0 {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\tstatus = \"okay\";\n\n\thub_port0: port@1 {\n\t\treg = <1>;\n\t\t#trigger-source-cells = <0>;\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <80000000>;\n\t\tm25p,fast-read;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tuboot: partition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x040000 0x010000>;\n\t\t\t};\n\n\t\t\tfwconcat0: partition@50000 {\n\t\t\t\tlabel = \"fwconcat0\";\n\t\t\t\treg = <0x050000 0xe20000>;\n\t\t\t};\n\n\t\t\tpartition@e70000 {\n\t\t\t\tlabel = \"loader\";\n\t\t\t\treg = <0xe70000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfwconcat1: partition@e80000 {\n\t\t\t\tlabel = \"fwconcat1\";\n\t\t\t\treg = <0xe80000 0x170000>;\n\t\t\t};\n\n\t\t\tart: partition@ff0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0xff0000 0x010000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\n\t\tqca,ar8327-initvals = <\n\t\t\t0x04 0x00080080 /* PORT0 PAD MODE CTRL */\n\t\t\t0x0c 0x07600000 /* PORT6 PAD MODE CTRL */\n\t\t\t0x50 0xc737c737 /* LED_CTRL0 */\n\t\t\t0x54 0x00000000 /* LED_CTRL1 */\n\t\t\t0x58 0x00000000 /* LED_CTRL2 */\n\t\t\t0x5c 0x0030c300 /* LED_CTRL3 */\n\t\t\t0x7c 0x0000007e /* PORT0_STATUS */\n\t\t\t0x94 0x0000007e /* PORT6 STATUS */\n\t\t\t>;\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n\tphy-handle = <&phy0>;\n\tpll-data = <0xa6000000 0x00000101 0x00001616>;\n\n\tgmac-config {\n\t\tdevice = <&gmac>;\n\t\trgmii-enabled = <1>;\n\t};\n};\n\n&eth1 {\n\tstatus = \"okay\";\n\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <(-1)>;\n\tpll-data = <0x03000101 0x00000101 0x00001616>;\n\n\tfixed-link {\n\t\tspeed = <1000>;\n\t\tfull-duplex;\n\t};\n};\n\n&pcie0 {\n\tstatus = \"okay\";\n\n\twifi@0,0 {\n\t\tcompatible = \"qcom,ath10k\";\n\t\treg = <0 0 0 0 0>;\n\t};\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9558_comfast_cf-wr650ac-v1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9558_comfast_cf-wr650ac.dtsi\"\n\n/ {\n\tcompatible = \"comfast,cf-wr650ac-v1\", \"qca,qca9558\";\n\tmodel = \"Comfast CF-WR650AC v1\";\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x020000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tart: partition@20000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0x020000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\treg = <0x030000 0xfc0000>;\n\t\t\t};\n\n\t\t\tpartition@ff0000 {\n\t\t\t\tlabel = \"nvram\";\n\t\t\t\treg = <0xff0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&eth0 {\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&eth1 {\n\tnvmem-cells = <&macaddr_art_6>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wmac {\n\tmtd-cal-data = <&art 0x1000>;\n\n\tnvmem-cells = <&macaddr_art_18>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n\n\tmacaddr_art_6: macaddr@6 {\n\t\treg = <0x6 0x6>;\n\t};\n\n\tmacaddr_art_18: macaddr@18 {\n\t\treg = <0x18 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9558_comfast_cf-wr650ac-v2.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9558_comfast_cf-wr650ac.dtsi\"\n\n/ {\n\tcompatible = \"comfast,cf-wr650ac-v2\", \"qca,qca9558\";\n\tmodel = \"Comfast CF-WR650AC v2\";\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tart: partition@40000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0x040000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\treg = <0x050000 0xfa0000>;\n\t\t\t};\n\n\t\t\tpartition@ff0000 {\n\t\t\t\tlabel = \"nvram\";\n\t\t\t\treg = <0xff0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&eth0 {\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&eth1 {\n\tnvmem-cells = <&macaddr_art_6>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wmac {\n\tmtd-cal-data = <&art 0x1000>;\n\n\tnvmem-cells = <&macaddr_art_18>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n\n\tmacaddr_art_6: macaddr@6 {\n\t\treg = <0x6 0x6>;\n\t};\n\n\tmacaddr_art_18: macaddr@18 {\n\t\treg = <0x18 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9558_comfast_cf-wr650ac.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca955x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 19 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twps {\n\t\t\tlabel = \"blue:wps\";\n\t\t\tgpios = <&gpio 20 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tnetwork {\n\t\t\tlabel = \"blue:network\";\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan2g {\n\t\t\tlabel = \"blue:wlan2\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\n\t\twlan5g {\n\t\t\tlabel = \"blue:wlan5\";\n\t\t\tgpios = <&gpio 2 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\t};\n\n\twatchdog {\n\t\tcompatible = \"linux,wdt-gpio\";\n\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\thw_algo = \"toggle\";\n\t\thw_margin_ms = <500>;\n\t\talways-running;\n\t};\n};\n\n&pcie0 {\n\tstatus = \"okay\";\n};\n\n&usb_phy0 {\n\tstatus = \"okay\";\n};\n\n&usb0 {\n\tstatus = \"okay\";\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tswitch0@1f {\n\t\tcompatible = \"qca,ar8327\";\n\t\treg = <0x1f>;\n\t\tqca,ar8327-initvals = <\n\t\t\t0x04 0x87600000 /* PORT0 PAD MODE CTRL */\n\t\t\t0x0c 0x00080080 /* PORT6 PAD MODE CTRL */\n\t\t\t0x10 0x81000080 /* POWER_ON_STRAP */\n\t\t\t0x7c 0x0000007e /* PORT0_STATUS */\n\t\t\t0x94 0x0000007e /* PORT6 STATUS */\n\t\t\t>;\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tpll-data = <0xa6000000 0x00000101 0x00001616>;\n\n\tfixed-link {\n\t\tspeed = <1000>;\n\t\tfull-duplex;\n\t};\n};\n\n&eth1 {\n\tstatus = \"okay\";\n\n\tpll-data = <0x03000101 0x00000101 0x00001616>;\n\n\tfixed-link {\n\t\tspeed = <1000>;\n\t\tfull-duplex;\n\t};\n};\n\n&wmac {\n\tstatus = \"okay\";\n};\n\n// This node is required for the Ethernet ports to work correctly.\n&gpio {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9558_compex_wpj558-16m.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later\n\n#include \"qca955x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"compex,wpj558-16m\", \"qca,qca9558\";\n\tmodel = \"Compex WPJ558 (16MB flash)\";\n\n\taliases {\n\t\tlabel-mac-device = &eth0;\n\t\tled-boot = &led_sig4;\n\t\tled-failsafe = &led_sig4;\n\t\tled-running = &led_sig4;\n\t\tled-upgrade = &led_sig4;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tsig1 {\n\t\t\tlabel = \"red:sig1\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tsig2 {\n\t\t\tlabel = \"yellow:sig2\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tsig3 {\n\t\t\tlabel = \"green:sig3\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_sig4: sig4 {\n\t\t\tlabel = \"green:sig4\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"Reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tbeeper {\n\t\tcompatible = \"gpio-beeper\";\n\t\tgpios = <&gpio 4 GPIO_ACTIVE_HIGH>;\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <50000000>;\n\t\tm25p,fast-read;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tuboot: partition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x030000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfirmware@30000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x030000 0xfc0000>;\n\t\t\t};\n\n\t\t\tart: partition@ff0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0xff0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\n\t\tqca,ar8327-initvals = <\n\t\t\t0x04 0x00080080 /* PORT0 PAD MODE CTRL */\n\t\t\t0x0c 0x07600000 /* PORT6 PAD MODE CTRL */\n\t\t\t0x50 0xcc35cc35 /* LED_CTRL0 */\n\t\t\t0x54 0x00000000 /* LED_CTRL1 */\n\t\t\t0x58 0x00000000 /* LED_CTRL2 */\n\t\t\t0x5c 0x03ffff00 /* LED_CTRL3 */\n\t\t\t0x7c 0x0000007e /* PORT0_STATUS */\n\t\t\t0x94 0x0000007e /* PORT6 STATUS */\n\t\t>;\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tpll-data = <0x56000000 0x00000101 0x00001616>;\n\tphy-handle = <&phy0>;\n\n\tnvmem-cells = <&macaddr_uboot_2e010>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n};\n\n&pcie0 {\n\tstatus = \"okay\";\n};\n\n&uboot {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_uboot_2e010: macaddr@2e010 {\n\t\treg = <0x2e010 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9558_devolo_dvl1200e.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9558_devolo_dvl1xxx.dtsi\"\n\n/ {\n\tcompatible = \"devolo,dvl1200e\", \"qca,qca9558\";\n\tmodel = \"devolo WiFi pro 1200e\";\n\n\taliases {\n\t\tled-boot = &led_status_blue;\n\t\tled-failsafe = &led_status_red;\n\t\tled-running = &led_status_blue;\n\t\tled-upgrade = &led_status_red;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_status_blue: status_blue {\n\t\t\tlabel = \"blue:status\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\tled_status_red: status_red {\n\t\t\tlabel = \"red:status\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tbeeper {\n\t\tcompatible = \"gpio-beeper\";\n\t\tgpios = <&gpio 4 GPIO_ACTIVE_HIGH>;\n\t};\n};\n\n&eth0 {\n\tpll-data = <0xae000000 0x80000101 0x80001313>;\n\tphy-mode = \"rgmii-rxid\";\n};\n\n&gmac_config {\n\trxdv-delay = <3>;\n\trxd-delay = <3>;\n\ttxen-delay = <0>;\n\ttxd-delay = <0>;\n};\n\n&mdio1 {\n\tstatus = \"okay\";\n\n\tphy1: ethernet-phy@1 {\n\t\treg = <1>;\n\t\tat803x-override-sgmii-link-check;\n\t};\n};\n\n&eth1 {\n\tstatus = \"okay\";\n\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <1>;\n\n\tphy-handle = <&phy1>;\n\tpll-data = <0x03000101 0x00000101 0x00001313>;\n\n\tqca955x-sgmii-fixup;\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9558_devolo_dvl1200i.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9558_devolo_dvl1xxx.dtsi\"\n\n/ {\n\tcompatible = \"devolo,dvl1200i\", \"qca,qca9558\";\n\tmodel = \"devolo WiFi pro 1200i\";\n\n\taliases {\n\t\tled-boot = &led_status_blue;\n\t\tled-failsafe = &led_status_red;\n\t\tled-running = &led_status_blue;\n\t\tled-upgrade = &led_status_red;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_status_blue: status_blue {\n\t\t\tlabel = \"blue:status\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\tled_status_red: status_red {\n\t\t\tlabel = \"red:status\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tbeeper {\n\t\tcompatible = \"gpio-beeper\";\n\t\tgpios = <&gpio 4 GPIO_ACTIVE_HIGH>;\n\t};\n};\n\n&eth0 {\n\tpll-data = <0xbe000000 0x80000101 0x80001313>;\n\tphy-mode = \"rgmii-id\";\n};\n\n&gmac_config {\n\trxdv-delay = <3>;\n\trxd-delay = <3>;\n\ttxen-delay = <3>;\n\ttxd-delay = <3>;\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9558_devolo_dvl1750c.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9558_devolo_dvl1xxx.dtsi\"\n\n/ {\n\tcompatible = \"devolo,dvl1750c\", \"qca,qca9558\";\n\tmodel = \"devolo WiFi pro 1750c\";\n\n\taliases {\n\t\tled-boot = &led_status_blue;\n\t\tled-failsafe = &led_status_red;\n\t\tled-running = &led_status_blue;\n\t\tled-upgrade = &led_status_red;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_status_blue: status_blue {\n\t\t\tlabel = \"blue:status\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\tled_status_red: status_red {\n\t\t\tlabel = \"red:status\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tbeeper {\n\t\tcompatible = \"gpio-beeper\";\n\t\tgpios = <&gpio 21 GPIO_ACTIVE_HIGH>;\n\t};\n};\n\n&eth0 {\n\tpll-data = <0xae000000 0x80000101 0x80001313>;\n\tphy-mode = \"rgmii-id\";\n};\n\n&gmac_config {\n\trxdv-delay = <3>;\n\trxd-delay = <3>;\n\ttxen-delay = <3>;\n\ttxd-delay = <3>;\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9558_devolo_dvl1750e.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9558_devolo_dvl1xxx.dtsi\"\n\n/ {\n\tcompatible = \"devolo,dvl1750e\", \"qca,qca9558\";\n\tmodel = \"devolo WiFi pro 1750e\";\n\n\taliases {\n\t\tled-boot = &led_status_blue;\n\t\tled-failsafe = &led_status_red;\n\t\tled-running = &led_status_blue;\n\t\tled-upgrade = &led_status_red;\n\t};\n\n\tkeys {\n\t\twps {\n\t\t\tlabel = \"WPS Button\";\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\tusb_eject {\n\t\t\tlabel = \"USB Eject Button\";\n\t\t\tlinux,code = <BTN_0>;\n\t\t\tlinux,input-type = <EV_SW>;\n\t\t\tgpios = <&gpio 19 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_status_blue: status_blue {\n\t\t\tlabel = \"blue:status\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\tled_status_red: status_red {\n\t\t\tlabel = \"red:status\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tbeeper {\n\t\tcompatible = \"gpio-beeper\";\n\t\tgpios = <&gpio 4 GPIO_ACTIVE_HIGH>;\n\t};\n\n\tgpio_export {\n\t\tcompatible = \"gpio-export\";\n\n\t\tgpio_usb_power {\n\t\t\tgpio-export,name = \"devolo:power:usb\";\n\t\t\tgpio-export,output = <1>;\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&usb_phy0 {\n\tstatus = \"okay\";\n};\n\n&usb0 {\n\tstatus = \"okay\";\n};\n\n&eth0 {\n\tpll-data = <0xae000000 0x80000101 0x80001313>;\n\tphy-mode = \"rgmii-rxid\";\n};\n\n&gmac_config {\n\trxdv-delay = <3>;\n\trxd-delay = <3>;\n\ttxen-delay = <0>;\n\ttxd-delay = <0>;\n};\n\n&mdio1 {\n\tstatus = \"okay\";\n\n\tphy1: ethernet-phy@1 {\n\t\treg = <1>;\n\t\tat803x-override-sgmii-link-check;\n\t};\n};\n\n&eth1 {\n\tstatus = \"okay\";\n\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <1>;\n\n\tphy-handle = <&phy1>;\n\tpll-data = <0x03000101 0x00000101 0x00001313>;\n\n\tqca955x-sgmii-fixup;\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9558_devolo_dvl1750i.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9558_devolo_dvl1xxx.dtsi\"\n\n/ {\n\tcompatible = \"devolo,dvl1750i\", \"qca,qca9558\";\n\tmodel = \"devolo WiFi pro 1750i\";\n\n\taliases {\n\t\tled-boot = &led_status_blue;\n\t\tled-failsafe = &led_status_red;\n\t\tled-running = &led_status_blue;\n\t\tled-upgrade = &led_status_red;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_status_blue: status_blue {\n\t\t\tlabel = \"blue:status\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\tled_status_red: status_red {\n\t\t\tlabel = \"red:status\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tbeeper {\n\t\tcompatible = \"gpio-beeper\";\n\t\tgpios = <&gpio 4 GPIO_ACTIVE_HIGH>;\n\t};\n};\n\n&eth0 {\n\tpll-data = <0xbe000000 0x80000101 0x80001313>;\n\tphy-mode = \"rgmii-id\";\n};\n\n&gmac_config {\n\trxdv-delay = <3>;\n\trxd-delay = <3>;\n\ttxen-delay = <3>;\n\ttxd-delay = <3>;\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9558_devolo_dvl1750x.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9558_devolo_dvl1xxx.dtsi\"\n\n/ {\n\tcompatible = \"devolo,dvl1750x\", \"qca,qca9558\";\n\tmodel = \"devolo WiFi pro 1750x\";\n\n\taliases {\n\t\tled-boot = &led_status_red;\n\t\tled-failsafe = &led_status_red;\n\t\tled-running = &led_status_red;\n\t\tled-upgrade = &led_status_red;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_status_red: status_red {\n\t\t\t/* This LED is not visible on the external casing. */\n\t\t\tlabel = \"red:status\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan {\n\t\t\tlabel = \"green:wlan\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\t};\n\n\tbeeper {\n\t\tcompatible = \"gpio-beeper\";\n\t\tgpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\t};\n};\n\n&eth0 {\n\tpll-data = <0xbe000000 0x80000101 0x80001313>;\n\tphy-mode = \"rgmii-id\";\n};\n\n&gmac_config {\n\trxdv-delay = <3>;\n\trxd-delay = <3>;\n\ttxen-delay = <3>;\n\ttxd-delay = <3>;\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9558_devolo_dvl1xxx.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n/*\n * The hardware of this board family is most likely shared with other devices\n * from other manufacturers.\n * Devolo seems to use hardware from Edimax, namely the Edimax WAP1750.\n *\n * The base board is identical but the single models differ in number of\n * buttons, ethernet ports, external console, USB, external / internal\n * antennas and number of spatial streams.\n */\n\n#include \"qca955x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"Reset button\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\twatchdog {\n\t\tcompatible = \"linux,wdt-gpio\";\n\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\thw_algo = \"toggle\";\n\t\thw_margin_ms = <300>;\n\t\talways-running;\n\t};\n};\n\n&pcie0 {\n\tstatus = \"okay\";\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x040000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tart: partition@50000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0x050000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@60000 {\n\t\t\t\tlabel = \"art_bak\";\n\t\t\t\treg = <0x060000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@70000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x070000 0xf90000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy4: ethernet-phy@4 {\n\t\treg = <4>;\n\t\teee-broken-100tx;\n\t\teee-broken-1000t;\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n\tphy-handle = <&phy4>;\n\n\tgmac_config: gmac-config {\n\t\tdevice = <&gmac>;\n\n\t\trgmii-enabled = <1>;\n\t};\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <(-2)>;\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9558_dlink_dap-2680-a1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca955x_dlink_dap-2xxx.dtsi\"\n\n/ {\n\tcompatible = \"dlink,dap-2680-a1\", \"qca,qca9558\";\n\tmodel = \"D-Link DAP-2680 A1\";\n\n\taliases {\n\t\tled-boot = &led_power_green;\n\t\tled-failsafe = &led_power_red;\n\t\tled-running = &led_power_green;\n\t\tled-upgrade = &led_power_red;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power_red: power_red {\n\t\t\tlabel = \"red:power\";\n\t\t\tgpios = <&gpio 20 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_power_green: power_green {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 19 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n};\n\n&partitions {\n\tpartition@70000 {\n\t\tlabel = \"firmware\";\n\t\treg = <0x70000 0xee0000>;\n\t\tcompatible = \"wrg\";\n\t};\n\n\tpartition@f50000 {\n\t\tlabel = \"dlink\";\n\t\treg = <0xf50000 0xa0000>;\n\t\tread-only;\n\t};\n\n\tart: partition@ff0000 {\n\t\tlabel = \"art\";\n\t\treg = <0xff0000 0x10000>;\n\t\tread-only;\n\t};\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy4: ethernet-phy@4 {\n\t\treg = <4>;\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tpll-data = <0x82000000 0x80000101 0x80001313>;\n\n\tphy-handle = <&phy4>;\n\tphy-mode = \"rgmii-id\";\n\n\tgmac-config {\n\t\tdevice = <&gmac>;\n\t\trgmii-enabled = <1>;\n\t\trxd-delay = <3>;\n\t\trxdv-delay = <3>;\n\t};\n};\n\n&pcie0 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9558_dlink_dap-2695-a1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca955x_dlink_dap-2xxx.dtsi\"\n\n/ {\n\tcompatible = \"dlink,dap-2695-a1\", \"qca,qca9558\";\n\tmodel = \"D-link DAP-2695-A1\";\n\n\taliases {\n\t\tled-boot = &led_power_red;\n\t\tled-failsafe = &led_power_red;\n\t\tled-running = &led_power_green;\n\t\tled-upgrade = &led_power_red;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power_green: power_green {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\tled_power_red: power_red {\n\t\t\tlabel = \"red:power\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twifi2g {\n\t\t\tlabel = \"green:wifi2g\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&partitions {\n\tpartition@70000 {\n\t\tlabel = \"firmware\";\n\t\treg = <0x070000 0xf00000>;\n\t\tcompatible = \"wrg\";\n\t};\n\n\tpartition@f70000 {\n\t\tlabel = \"captival\";\n\t\treg = <0xf70000 0x070000>;\n\t\tread-only;\n\t};\n\n\tpartition@fe0000 {\n\t\tlabel = \"certificate\";\n\t\treg = <0xfe0000 0x010000>;\n\t\tread-only;\n\t};\n\n\tart: partition@ff0000 {\n\t\tlabel = \"art\";\n\t\treg = <0xff0000 0x010000>;\n\t\tread-only;\n\t};\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\n\t\tqca,ar8327-initvals = <\n\t\t\t0x04 0x07600000 /* PORT0_PAD_CTRL */\n\t\t\t0x0c 0x00080080 /* PORT6_PAD_CTRL */\n\t\t\t0x7c 0x0000007e /* PORT0_STATUS */\n\t\t\t0x94 0x0000007e /* PORT6_STATUS */\n\t\t>;\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tphy-handle = <&phy0>;\n\tpll-data = <0x56000000 0x00000101 0x00001616>;\n\n\tfixed-link {\n\t\tspeed = <1000>;\n\t\tfull-duplex;\n\t};\n};\n\n&eth1 {\n\tstatus = \"okay\";\n\n\tphy-mask = <0>;\n\tpll-data = <0x03000101 0x00000101 0x00001616>;\n\n\tfixed-link {\n\t\tspeed = <1000>;\n\t\tfull-duplex;\n\t};\n};\n\n&pcie0 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9558_dlink_dap-3662-a1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca955x_dlink_dap-2xxx.dtsi\"\n\n/ {\n\tcompatible = \"dlink,dap-3662-a1\", \"qca,qca9558\";\n\tmodel = \"D-Link DAP-3662 A1\";\n\n\taliases {\n\t\tled-boot = &led_power_green;\n\t\tled-failsafe = &led_power_red;\n\t\tled-running = &led_power_green;\n\t\tled-upgrade = &led_power_red;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power_red: power_red {\n\t\t\tlabel = \"red:power\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_power_green: power_green {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n};\n\n&partitions {\n\tpartition@70000 {\n\t\tlabel = \"firmware\";\n\t\treg = <0x70000 0xef0000>;\n\t\tcompatible = \"wrg\";\n\t};\n\n\tpartition@f60000 {\n\t\tlabel = \"dlink\";\n\t\treg = <0xf60000 0x90000>;\n\t\tread-only;\n\t};\n\n\tart: partition@ff0000 {\n\t\tlabel = \"art\";\n\t\treg = <0xff0000 0x10000>;\n\t\tread-only;\n\t};\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\n\t\tqca,ar8327-initvals = <\n\t\t\t0x04 0x07600000 /* PORT0_PAD_CTRL */\n\t\t\t0x0c 0x00080080 /* PORT6_PAD_CTRL */\n\t\t\t0x7c 0x0000007e /* PORT0_STATUS */\n\t\t\t0x94 0x0000007e /* PORT6_STATUS */\n\t\t>;\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tphy-handle = <&phy0>;\n\tpll-data = <0x56000000 0x00000101 0x00001616>;\n\n\tfixed-link {\n\t\tspeed = <1000>;\n\t\tfull-duplex;\n\t};\n};\n\n&eth1 {\n\tstatus = \"okay\";\n\n\tpll-data = <0x03000101 0x00000101 0x00001616>;\n\n\tfixed-link {\n\t\tspeed = <1000>;\n\t\tfull-duplex;\n\t};\n};\n\n&pcie0 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9558_domywifi_dw33d.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca955x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"domywifi,dw33d\", \"qca,qca9558\";\n\tmodel = \"DomyWifi DW33D\";\n\n\taliases {\n\t\tled-boot = &led_system;\n\t\tled-failsafe = &led_system;\n\t\tled-running = &led_system;\n\t\tled-upgrade = &led_system;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_system: system {\n\t\t\tlabel = \"blue:system\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tmmc {\n\t\t\tlabel = \"blue:mmc\";\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_LOW>;\n\t\t\ttrigger-sources = <&hub_port0>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\n\t\tusb {\n\t\t\tlabel = \"blue:usb\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t\ttrigger-sources = <&hub_port1>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\n\t\twlan2g {\n\t\t\tlabel = \"blue:wlan2g\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\n\t\tinternet {\n\t\t\tlabel = \"blue:internet\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"Reset button\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n};\n\n&pcie0 {\n\tstatus = \"okay\";\n\n\twifi@0,0 {\n\t\tcompatible = \"qcom,ath10k\";\n\t\treg = <0 0 0 0 0>;\n\t};\n};\n\n&usb_phy0 {\n\tstatus = \"okay\";\n};\n\n&usb0 {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\tstatus = \"okay\";\n\n\thub_port0: port@1 {\n\t\treg = <1>;\n\t\t#trigger-source-cells = <0>;\n\t};\n};\n\n&usb_phy1 {\n\tstatus = \"okay\";\n};\n\n&usb1 {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\tstatus = \"okay\";\n\n\thub_port1: port@1 {\n\t\treg = <1>;\n\t\t#trigger-source-cells = <0>;\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x40000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tlabel = \"oem-firmware\";\n\t\t\t\treg = <0x50000 0xfa0000>;\n\t\t\t};\n\n\t\t\tart: partition@ff0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0xff0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&nand {\n\tstatus = \"okay\";\n\n\tpartitions {\n\t\tcompatible = \"fixed-partitions\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"kernel\";\n\t\t\treg = <0x0 0x500000>;\n\t\t};\n\n\t\tpartition@500000 {\n\t\t\tlabel = \"ubi\";\n\t\t\treg = <0x500000 0x5b00000>;\n\t\t};\n\n\t\tpartition@6000000 {\n\t\t\tlabel = \"oem-backup\";\n\t\t\treg = <0x6000000 0x2000000>;\n\t\t};\n\t};\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\n\t\tqca,ar8327-initvals = <\n\t\t\t0x04 0x87600000 /* PORT0 PAD MODE CTRL */\n\t\t\t0x0c 0x00080080 /* PORT6 PAD MODE CTRL */\n\t\t\t0x7c 0x0000007e /* PORT0_STATUS */\n\t\t\t0x94 0x0000007e /* PORT6 STATUS */\n\t\t\t>;\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n\tpll-data = <0x56000000 0x00000101 0x00001616>;\n\tphy-handle = <&phy0>;\n};\n\n&eth1 {\n\tstatus = \"okay\";\n\n\tnvmem-cells = <&macaddr_art_6>;\n\tnvmem-cell-names = \"mac-address\";\n\tpll-data = <0x03000101 0x00000101 0x00001616>;\n\tfixed-link {\n\t\tspeed = <1000>;\n\t\tfull-duplex;\n\t};\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n\tnvmem-cells = <&macaddr_art_c>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n\n\tmacaddr_art_6: macaddr@6 {\n\t\treg = <0x6 0x6>;\n\t};\n\n\tmacaddr_art_c: macaddr@c {\n\t\treg = <0xc 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9558_engenius_ecb1750.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca955x_engenius_ecb1xxx.dtsi\"\n\n/ {\n\tcompatible = \"engenius,ecb1750\", \"qca,qca9558\";\n\tmodel = \"EnGenius ECB1750\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9558_engenius_epg5000.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca955x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"EnGenius EPG5000\";\n\tcompatible = \"engenius,epg5000\", \"qca,qca9558\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"amber:power\";\n\t\t\tgpios = <&gpio 2 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\twlan2g {\n\t\t\tlabel = \"blue:wlan2g\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\n\t\twlan5g {\n\t\t\tlabel = \"blue:wlan5g\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\twps_amber {\n\t\t\tlabel = \"amber:wps\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twps_blue {\n\t\t\tlabel = \"blue:wps\";\n\t\t\tgpios = <&gpio 19 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tphy-handle = <&phy0>;\n\tpll-data = <0xa6000000 0x00000101 0x00001616>;\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\n\t\tqca,ar8327-initvals = <\n\t\t\t0x04 0x87600000 /* PORT0 PAD MODE CTRL */\n\t\t\t0x7c 0x0000007e /* PORT0_STATUS */\n\t\t\t>;\n\t};\n};\n\n&pcie0 {\n\tstatus = \"okay\";\n\n\twifi@0,0 {\n\t\tcompatible = \"pci168c,003c\";\n\t\treg = <0x0000 0 0 0 0>;\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x030000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x030000 0x010000>;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x040000 0xe50000>;\n\t\t\t};\n\n\t\t\tpartition@790000 {\n\t\t\t\tlabel = \"manufacture\";\n\t\t\t\treg = <0xe90000 0x100000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@ed0000 {\n\t\t\t\tlabel = \"backup\";\n\t\t\t\treg = <0xf90000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@fe0000 {\n\t\t\t\tlabel = \"storage\";\n\t\t\t\treg = <0xfa0000 0x050000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@ff0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0xff0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&usb_phy1 {\n\tstatus = \"okay\";\n};\n\n&usb1 {\n\tstatus = \"okay\";\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tqca,no-eeprom;\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9558_jjplus_jwap230.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca955x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/leds/common.h>\n\n/ {\n\tmodel = \"jjPlus JWAP230\";\n\tcompatible = \"jjplus,jwap230\", \"qca,qca9558\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: led-0 {\n\t\t\tlabel = \"green:power\";\n\t\t\tcolor = <LED_COLOR_ID_GREEN>;\n\t\t\tfunction = LED_FUNCTION_POWER;\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled-1 {\n\t\t\tcolor = <LED_COLOR_ID_GREEN>;\n\t\t\tfunction-enumerator = <0>;\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled-2 {\n\t\t\tcolor = <LED_COLOR_ID_GREEN>;\n\t\t\tfunction-enumerator = <1>;\n\t\t\tgpios = <&gpio 21 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&pcie0 {\n\tstatus = \"okay\";\n};\n\n&pcie1 {\n\tstatus = \"okay\";\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x040000 0x010000>;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x050000 0xfa0000>;\n\t\t\t};\n\n\t\t\tart: partition@ff0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0xff0000 0x010000>;\n\t\t\t\tread-only;\n\n\t\t\t\tcompatible = \"nvmem-cells\";\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\n\t\t\t\tmacaddr_art_lan: macaddr@0 {\n\t\t\t\t\treg = <0x0 0x6>;\n\t\t\t\t};\n\n\t\t\t\tmacaddr_art_wan: macaddr@6 {\n\t\t\t\t\treg = <0x6 0x6>;\n\t\t\t\t};\n\n\t\t\t\tcalibration_art_wlan: calibration@1000 {\n\t\t\t\t\treg = <0x1000 0x440>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t};\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tswitch {\n\t\tcompatible = \"qca,ar8327\";\n\t\treg = <0>;\n\n\t\tqca,ar8327-initvals = <\n\t\t\t0x04 0x07600000 /* PORT0 PAD MODE CTRL */\n\t\t\t0x58 0xffb7ffb7 /* LED_CTRL2 */\n\t\t\t0x5c 0x03ffff00 /* LED_CTRL3 */\n\t\t\t0x7c 0x0000007e /* PORT0_STATUS */\n\t\t\t0x0c 0x00080080 /* PORT6 PAD MODE CTRL */\n\t\t\t0x94 0x0000007e /* PORT6_STATUS */\n\t\t>;\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tnvmem-cells = <&macaddr_art_wan>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tpll-data = <0xae000000 0x80000101 0x80001313>;\n\n\tfixed-link {\n\t\tspeed = <1000>;\n\t\tfull-duplex;\n\t};\n\n\tgmac_config: gmac-config {\n\t\tdevice = <&gmac>;\n\n\t\trxdv-delay = <3>;\n\t\trxd-delay = <3>;\n\t\ttxen-delay = <0>;\n\t\ttxd-delay = <0>;\n\t\trgmii-enabled = <1>;\n\t};\n};\n\n&eth1 {\n\tstatus = \"okay\";\n\n\tnvmem-cells = <&macaddr_art_lan>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tpll-data = <0x03000101 0x00000101 0x00001313>;\n\n\tfixed-link {\n\t\tspeed = <1000>;\n\t\tfull-duplex;\n\t};\n};\n\n&wmac {\n\tstatus = \"okay\";\n\tnvmem-cells = <&calibration_art_wlan>;\n\tnvmem-cell-names = \"calibration\";\n};\n\n&usb_phy0 {\n\tstatus = \"okay\";\n};\n\n&usb0 {\n\tstatus = \"okay\";\n};\n\n&usb_phy1 {\n\tstatus = \"okay\";\n};\n\n&usb1 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9558_librerouter_librerouter-v1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca955x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"librerouter,librerouter-v1\", \"qca,qca9558\";\n\tmodel = \"LibreRouter v1\";\n\n\taliases {\n\t\tled-boot = &led_system;\n\t\tled-failsafe = &led_system;\n\t\tled-running = &led_system;\n\t\tled-upgrade = &led_system;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_system: system {\n\t\t\tlabel = \"green:system\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\twifi_green {\n\t\t\tlabel = \"green:wlan2g\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\tstatus_blue {\n\t\t\tlabel = \"blue:status\";\n\t\t\tgpios = <&gpio 20 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"Reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\twatchdog {\n\t\tcompatible = \"linux,wdt-gpio\";\n\t\tgpios = <&gpio 2 GPIO_ACTIVE_LOW>;\n\t\thw_algo = \"toggle\";\n\t\thw_margin_ms = <1000>;\n\t\talways-running;\n\t};\n};\n\n&pcie0 {\n\tstatus = \"okay\";\n\n\twifi@0,0 {\n\t\tcompatible = \"pci168c,0033\";\n\t\treg = <0x0000 0 0 0 0>;\n\t};\n};\n\n&pcie1 {\n\tstatus = \"okay\";\n\n\twifi@0,0 {\n\t\tcompatible = \"pci168c,0033\";\n\t\treg = <0x0000 0 0 0 0>;\n\t};\n};\n\n&usb_phy0 {\n\tstatus = \"okay\";\n};\n\n&usb0 {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\tstatus = \"okay\";\n};\n\n&usb_phy1 {\n\tstatus = \"okay\";\n};\n\n&usb1 {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\tstatus = \"okay\";\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x040000 0x010000>;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x050000 0x7c0000>;\n\t\t\t};\n\n\t\t\tpartition@810000 {\n\t\t\t\tlabel = \"fw2\";\n\t\t\t\treg = <0x810000 0x7d0000>;\n\t\t\t};\n\n\t\t\tpartition@fd0000 {\n\t\t\t\tlabel = \"res\";\n\t\t\t\treg = <0xfd0000 0x20000>;\n\t\t\t};\n\n\t\t\tart: partition@ff0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0xff0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t\tqca,ar8327-initvals = <\n\t\t\t0x04 0x87600000 /* PORT0: RGMII, MAC0/6 exchage, tx_delay 01, rx_delay 10 */\n\t\t\t0x0c 0x00000080 /* PORT6: SGMII */\n\t\t\t0x10 0x81000080 /* POWER_ON_STRAP: LED open drain, SerDes auto-neg disabled */\n\t\t\t0x50 0xcf37cf37 /* LED_CTRL0 */\n\t\t\t0x54 0xcf37cf37 /* LED_CTRL1 */\n\t\t\t0x58 0xcf37cf37 /* LED_CTRL2 */\n\t\t\t0x5c 0x0        /* LED_CTRL3 */\n\t\t\t0x7c 0x0000007e /* PORT0_STATUS */\n\t\t\t0x94 0x0000007e /* PORT6 STATUS */\n\t\t>;\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tpll-data = <0xa6000000 0x00000101 0x00001616>;\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tphy-handle = <&phy0>;\n};\n\n&eth1 {\n\tstatus = \"okay\";\n\n\tpll-data = <0x03000101 0x00000101 0x00001616>;\n\tnvmem-cells = <&macaddr_art_6>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tfixed-link {\n\t\tspeed = <1000>;\n\t\tfull-duplex;\n\t};\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n\tnvmem-cells = <&macaddr_art_c>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n\n\tmacaddr_art_6: macaddr@6 {\n\t\treg = <0x6 0x6>;\n\t};\n\n\tmacaddr_art_c: macaddr@c {\n\t\treg = <0xc 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9558_mikrotik_routerboard-921gs-5hpacd-15s.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9558_mikrotik_routerboard-92x.dtsi\"\n\n/ {\n\tcompatible = \"mikrotik,routerboard-921gs-5hpacd-15s\", \"qca,qca9558\";\n\tmodel = \"MikroTik RouterBOARD 921GS-5HPacD-15s\";\n\n\tath10k-leds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twlan5g {\n\t\t\tlabel = \"green:wlan5g\";\n\t\t\tgpios = <&ath10k 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\t};\n};\n\n&pcie1 {\n\tstatus = \"okay\";\n\n\tath10k: wifi@0,0 {\n\t\tcompatible = \"qcom,ath10k\";\n\t\treg = <0 0 0 0 0>;\n\t\t#gpio-cells = <2>;\n\t\tgpio-controller;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9558_mikrotik_routerboard-922uags-5hpacd.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9558_mikrotik_routerboard-92x.dtsi\"\n\n/ {\n\tcompatible = \"mikrotik,routerboard-922uags-5hpacd\", \"qca,qca9558\";\n\tmodel = \"MikroTik RouterBOARD 922UAGS-5HPacD\";\n\n\tath10k-leds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twlan5g {\n\t\t\tlabel = \"green:wlan5g\";\n\t\t\tgpios = <&ath10k 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\t};\n\n\tgpio-export {\n\t\tgpio_usb_power {\n\t\t\tgpio-export,name = \"mikrotik:power:usb\";\n\t\t\tgpio-export,output = <0>;\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&pcie0 {\n\tstatus = \"okay\";\n\n\tath10k: wifi@0,0 {\n\t\tcompatible = \"qcom,ath10k\";\n\t\treg = <0 0 0 0 0>;\n\t\t#gpio-cells = <2>;\n\t\tgpio-controller;\n\t};\n};\n\n&pcie1 {\n\tstatus = \"okay\";\n};\n\n&usb0 {\n\tstatus = \"okay\";\n};\n\n&usb_phy0 {\n\tstatus = \"okay\";\n};\n\n&usb1 {\n\tstatus = \"okay\";\n};\n\n&usb_phy1 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9558_mikrotik_routerboard-92x.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca955x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\taliases {\n\t\tled-boot = &led_user;\n\t\tled-failsafe = &led_user;\n\t\tled-upgrade = &led_user;\n\t\tserial0 = &uart;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_user: user {\n\t\t\tlabel = \"green:user\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 20 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tgpio-export {\n\t\tcompatible = \"gpio-export\";\n\n\t\tgpio_nand_power {\n\t\t\tgpio-export,name = \"mikrotik:power:nand\";\n\t\t\tgpio-export,output = <0>;\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\ti2c: i2c {\n\t\tcompatible = \"i2c-gpio\";\n\n\t\tsda-gpios = <&gpio 18 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;\n\t\tscl-gpios = <&gpio 19 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;\n\t\ti2c-gpio,delay-us = <5>;\n\t\ti2c-gpio,timeout-ms = <1>;\n\t};\n\n\tsfp1: sfp {\n\t\tcompatible = \"sff,sfp\";\n\n\t\ti2c-bus = <&i2c>;\n\t\tmaximum-power-milliwatt = <1000>;\n\t\tlos-gpios = <&gpio 21 GPIO_ACTIVE_HIGH>;\n\t\tmod-def0-gpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\ttx-disable-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\t\t// Toggling GPIO16 actually enables/disables the transmitter,\n\t\t// but the SFP driver does not seem to be using it.\n\t};\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy4: ethernet-phy@4 {\n\t\treg = <4>;\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tphy-handle = <&phy4>;\n\tpll-data = <0x8f000000 0xa0000101 0xa0001313>;\n\n\tgmac-config {\n\t\tdevice = <&gmac>;\n\t\trgmii-enabled = <1>;\n\t};\n};\n\n&mdio1 {\n\tstatus = \"okay\";\n\n\tphy_sfp: ethernet-phy@0 {\n\t\treg = <0>;\n\t\tphy-mode = \"sgmii\";\n\t\tsfp = <&sfp1>;\n\t};\n};\n\n&eth1 {\n\tstatus = \"okay\";\n\n\tphy-handle = <&phy_sfp>;\n\tpll-data = <0x03000000 0x00000101 0x00001616>;\n\tqca955x-sgmii-fixup;\n\n\tgmac-config {\n\t\tdevice = <&gmac>;\n\t};\n\n\tfixed-link {\n\t\tspeed = <1000>;\n\t\tfull-duplex;\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"mikrotik,routerboot-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"routerboot\";\n\t\t\t\treg = <0x0 0x0>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\thard_config {\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tbios {\n\t\t\t\tsize = <0x1000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tsoft_config {\n\t\t\t};\n\t\t};\n\t};\n};\n\n&nand {\n\tstatus = \"okay\";\n\n\tnand-ecc-mode = \"soft\";\n\tqca,nand-swap-dma;\n\tqca,nand-scan-fixup;\n\n\tpartitions {\n\t\tcompatible = \"fixed-partitions\";\n\t\t#size-cells = <1>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"booter\";\n\t\t\treg = <0x0000000 0x0040000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@40000 {\n\t\t\tlabel = \"kernel\";\n\t\t\treg = <0x0040000 0x03c0000>;\n\t\t};\n\n\t\tpartition@400000 {\n\t\t\tlabel = \"ubi\";\n\t\t\treg = <0x0400000 0x7c00000>;\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9558_mikrotik_routerboard-962uigs-5hact2hnt.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9558_mikrotik_routerboard-96x.dtsi\"\n\n/ {\n\tcompatible = \"mikrotik,routerboard-962uigs-5hact2hnt\", \"qca,qca9558\";\n\tmodel = \"MikroTik RouterBOARD 962UiGS-5HacT2HnT (hAP ac)\";\n\n\tgpio-export {\n\t\tcompatible = \"gpio-export\";\n\n\t\tport5_poe {\n\t\t\tgpio-export,name = \"port5-poe\";\n\t\t\tgpio-export,output = <1>;\n\t\t\tgpios = <&gpio 3 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&gpio {\n\tinput-poe-out-compat {\n\t\tgpio-hog;\n\t\tgpios = <2 GPIO_ACTIVE_HIGH>;\n\t\tinput;\n\t\tline-name = \"PoE out compat\";\n\t};\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tqca,no-eeprom;\n};\n\n&pcie1 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9558_mikrotik_routerboard-96x.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca955x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\taliases {\n\t\tled-boot = &led_user;\n\t\tled-failsafe = &led_user;\n\t\tled-upgrade = &led_user;\n\t\tserial0 = &uart;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_user: user {\n\t\t\tlabel = \"green:user\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 20 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tgpio-export {\n\t\tcompatible = \"gpio-export\";\n\n\t\tbuzzer {\n\t\t\t/* Beeper requires PWM for frequency selection */\n\t\t\tgpio-export,name = \"buzzer\";\n\t\t\tgpio-export,output = <0>;\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tusb_power {\n\t\t\tgpio-export,name = \"usb-power\";\n\t\t\tgpio-export,output = <0>;\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n\n\ti2c: i2c {\n\t\tcompatible = \"i2c-gpio\";\n\n\t\tsda-gpios = <&gpio 18 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;\n\t\tscl-gpios = <&gpio 19 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;\n\t\ti2c-gpio,delay-us = <5>;\n\t\ti2c-gpio,timeout-ms = <1>;\n\t};\n\n\tsfp1: sfp {\n\t\tcompatible = \"sff,sfp\";\n\n\t\ti2c-bus = <&i2c>;\n\t\tmaximum-power-milliwatt = <1000>;\n\t\tlos-gpios = <&gpio 21 GPIO_ACTIVE_HIGH>;\n\t\tmod-def0-gpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\ttx-disable-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\t\t// Toggling GPIO16 actually enables/disables the transmitter,\n\t\t// but the SFP driver does not seem to be using it.\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <40000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"RouterBoot\";\n\t\t\t\treg = <0x0 0x20000>;\n\t\t\t\tread-only;\n\t\t\t\tcompatible = \"mikrotik,routerboot-partitions\";\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\n\t\t\t\tpartition@0 {\n\t\t\t\t\tlabel = \"bootloader1\";\n\t\t\t\t\treg = <0x0 0x0>;\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\thard_config {\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\tbios {\n\t\t\t\t\tsize = <0x1000>;\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\tpartition@10000 {\n\t\t\t\t\tlabel = \"bootloader2\";\n\t\t\t\t\treg = <0x10000 0x0>;\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\tsoft_config {\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tcompatible = \"mikrotik,minor\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x020000 0xfe0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\n\t\tqca,ar8327-initvals = <\n\t\t\t/* PAD0_MODE from vendor firmware\n\t\t\t * RGMII_EN, TX/RXCLK_DELAY_EN, TXCLK_DELAY_SEL=1\n\t\t\t */\n\t\t\t0x04 0x07400000 /* PAD0_MODE */\n\t\t\t0x50 0xc737c737 /* LED_CTRL0 */\n\t\t\t0x54 0x00000000 /* LED_CTRL1 */\n\t\t\t0x58 0x00000000 /* LED_CTRL2 */\n\t\t\t0x5c 0x0030c300 /* LED_CTRL3 */\n\t\t\t0x7c 0x0000007e /* PORT0_STATUS */\n\t\t\t>;\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tphy-handle = <&phy0>;\n\t/* gigabit pll-data from vendor firmware\n\t * TX_INVERT, TX_DELAY=3, GIGE, OFFSET_PHASE\n\t */\n\tpll-data = <0x8f000000 0x00000101 0x00001616>;\n\n\tgmac-config {\n\t\tdevice = <&gmac>;\n\t\trgmii-enabled = <1>;\n\t};\n};\n\n&mdio1 {\n\tstatus = \"okay\";\n\n\tphy_sfp: ethernet-phy@0 {\n\t\treg = <0>;\n\t\tphy-mode = \"sgmii\";\n\t\tsfp = <&sfp1>;\n\t};\n};\n\n&eth1 {\n\tstatus = \"okay\";\n\n\tphy-handle = <&phy_sfp>;\n\tpll-data = <0x03000000 0x00000101 0x00001616>;\n\tqca955x-sgmii-fixup;\n\n\tgmac-config {\n\t\tdevice = <&gmac>;\n\t};\n\n\tfixed-link {\n\t\tspeed = <1000>;\n\t\tfull-duplex;\n\t};\n};\n\n&usb0 {\n\tstatus = \"okay\";\n};\n\n&usb_phy0 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9558_netgear_ex6400.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9558_netgear_ex7300.dtsi\"\n\n/ {\n\tmodel = \"Netgear EX6400\";\n\tcompatible = \"netgear,ex6400\", \"qca,qca9558\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9558_netgear_ex7300.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9558_netgear_ex7300.dtsi\"\n\n/ {\n\tmodel = \"Netgear EX7300\";\n\tcompatible = \"netgear,ex7300\", \"qca,qca9558\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9558_netgear_ex7300.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca955x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\taliases {\n\t\tled-boot = &led_power_green;\n\t\tled-failsafe = &led_power_amber;\n\t\tled-running = &led_power_green;\n\t\tled-upgrade = &led_power_amber;\n\t\tlabel-mac-device = &eth0;\n\t};\n\n\tled_spi {\n\t\tcompatible = \"spi-gpio\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tsck-gpios = <&gpio 18 GPIO_ACTIVE_HIGH>;\n\t\tmosi-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;\n\t\tnum-chipselects = <0>;\n\n\t\tled_gpio: led_gpio@0 {\n\t\t\tcompatible = \"nxp,74lvc594\";\n\t\t\treg = <0>;\n\t\t\tgpio-controller;\n\t\t\t#gpio-cells = <2>;\n\t\t\tregisters-number = <1>;\n\t\t\tspi-max-frequency = <500000>;\n\n\t\t\tgpio_latch_bit {\n\t\t\t\tgpio-hog;\n\t\t\t\tgpios = <4 GPIO_ACTIVE_HIGH>;\n\t\t\t\toutput-high;\n\t\t\t\tline-name = \"gpio-latch-bit\";\n\t\t\t};\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power_green: power_green {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 19 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_power_amber: power_amber {\n\t\t\tlabel = \"amber:power\";\n\t\t\tgpios = <&gpio 20 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tleft_blue {\n\t\t\tlabel = \"blue:left\";\n\t\t\tgpios = <&led_gpio 7 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tright_blue {\n\t\t\tlabel = \"blue:right\";\n\t\t\tgpios = <&led_gpio 6 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twps_green {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&led_gpio 5 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tclient_red {\n\t\t\tlabel = \"red:client\";\n\t\t\tgpios = <&led_gpio 3 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tclient_green {\n\t\t\tlabel = \"green:client\";\n\t\t\tgpios = <&led_gpio 2 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\trouter_red {\n\t\t\tlabel = \"red:router\";\n\t\t\tgpios = <&led_gpio 1 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\trouter_green {\n\t\t\tlabel = \"green:router\";\n\t\t\tgpios = <&led_gpio 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"Reset button\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"WPS button\";\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\textender_apmode {\n\t\t\tlabel = \"EXTENDER/APMODE switch\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_0>;\n\t\t\tlinux,input-type = <EV_SW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n};\n\n&pcie0 {\n\tstatus = \"okay\";\n};\n\n&pll {\n\tclocks = <&extosc>;\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tuboot: partition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x040000 0x010000>;\n\t\t\t};\n\n\t\t\tcaldata: partition@50000 {\n\t\t\t\tlabel = \"caldata\";\n\t\t\t\treg = <0x050000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@60000 {\n\t\t\t\tlabel = \"caldata-backup\";\n\t\t\t\treg = <0x060000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@70000 {\n\t\t\t\tlabel = \"config\";\n\t\t\t\treg = <0x070000 0x010000>;\n\t\t\t};\n\n\t\t\tpartition@80000 {\n\t\t\t\tlabel = \"pot\";\n\t\t\t\treg = <0x080000 0x010000>;\n\t\t\t};\n\n\t\t\tpartition@90000 {\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x090000 0xf30000>;\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t};\n\n\t\t\tpartition@fc0000 {\n\t\t\t\tlabel = \"language\";\n\t\t\t\treg = <0xfc0000 0x040000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&caldata 0x1000>;\n\tnvmem-cells = <&macaddr_caldata_6>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy4: ethernet-phy@4 {\n\t\treg = <4>;\n\t\tphy-mode = \"rgmii\";\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tnvmem-cells = <&macaddr_caldata_0>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tphy-handle = <&phy4>;\n\tphy-mode = \"rgmii-rxid\";\n\n\tpll-data = <0x86000000 0x80000101 0x80001313>;\n};\n\n&caldata {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_caldata_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n\n\tmacaddr_caldata_6: macaddr@6 {\n\t\treg = <0x6 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9558_ocedo_koala.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca955x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"ocedo,koala\", \"qca,qca9558\";\n\tmodel = \"OCEDO Koala\";\n\n\taliases {\n\t\tled-boot = &led_system;\n\t\tled-failsafe = &led_system;\n\t\tled-running = &led_system;\n\t\tled-upgrade = &led_system;\n\t\tlabel-mac-device = &eth0;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tpower {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\twifi2 {\n\t\t\tlabel = \"yellow:wlan2\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\n\t\twifi5 {\n\t\t\tlabel = \"red:wlan58\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\tled_system: system {\n\t\t\tlabel = \"blue:sys\";\n\t\t\tgpios = <&gpio 19 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&pcie0 {\n\tstatus = \"okay\";\n};\n\n&pll {\n\tclocks = <&extosc>;\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <50000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tuboot: partition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x040000 0x010000>;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x050000 0x740000>;\n\t\t\t};\n\n\t\t\tpartition@790000 {\n\t\t\t\tlabel = \"vendor\";\n\t\t\t\treg = <0x790000 0x740000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@ed0000 {\n\t\t\t\tlabel = \"data\";\n\t\t\t\treg = <0xed0000 0x110000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@fe0000 {\n\t\t\t\tlabel = \"id\";\n\t\t\t\treg = <0xfe0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tart: partition@ff0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0xff0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n\tnvmem-cells = <&macaddr_art_6>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy5: ethernet-phy@5 {\n\t\treg = <5>;\n\t\teee-broken-100tx;\n\t\teee-broken-1000t;\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tphy-handle = <&phy5>;\n\tphy-mode = \"rgmii-rxid\";\n\n\tpll-data = <0x8e000000 0x80000101 0x80001313>;\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n\n\tmacaddr_art_6: macaddr@6 {\n\t\treg = <0x6 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9558_ocedo_ursus.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca955x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"ocedo,ursus\", \"qca,qca9558\";\n\tmodel = \"OCEDO Ursus\";\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twifi2 {\n\t\t\tlabel = \"green:wlan2g\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\n\t\twifi5 {\n\t\t\tlabel = \"green:wlan5g\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\t};\n};\n\n&pcie1 {\n\tstatus = \"okay\";\n};\n\n&pll {\n\tclocks = <&extosc>;\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <50000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tuboot: partition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x040000 0x010000>;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x050000 0x740000>;\n\t\t\t};\n\n\t\t\tpartition@790000 {\n\t\t\t\tlabel = \"vendor\";\n\t\t\t\treg = <0x790000 0x740000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@ed0000 {\n\t\t\t\tlabel = \"data\";\n\t\t\t\treg = <0xed0000 0x110000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@fe0000 {\n\t\t\t\tlabel = \"id\";\n\t\t\t\treg = <0xfe0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tart: partition@ff0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0xff0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n\tnvmem-cells = <&macaddr_art_6>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy1: ethernet-phy@1 {\n\t\treg = <1>;\n\t};\n\n\tphy2: ethernet-phy@2 {\n\t\treg = <2>;\n\t\tat803x-override-sgmii-link-check;\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tphy-mode = \"rgmii-rxid\";\n\tphy-handle = <&phy1>;\n\tpll-data = <0x8e000000 0x80000101 0x80001313>;\n\n\tgmac_config: gmac-config {\n\t\tdevice = <&gmac>;\n\n\t\trxdv-delay = <3>;\n\t\trxd-delay = <3>;\n\t\ttxen-delay = <0>;\n\t\ttxd-delay = <0>;\n\t\trgmii-enabled = <1>;\n\t};\n};\n\n&eth1 {\n\tstatus = \"okay\";\n\tnvmem-cells = <&macaddr_art_12>;\n\tnvmem-cell-names = \"mac-address\";\n\tphy-handle = <&phy2>;\n\tpll-data = <0x3000101 0x101 0x1313>;\n\tqca955x-sgmii-fixup;\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n\n\tmacaddr_art_6: macaddr@6 {\n\t\treg = <0x6 0x6>;\n\t};\n\n\tmacaddr_art_12: macaddr@12 {\n\t\treg = <0x12 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9558_openmesh_a40.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9558_openmesh_a60.dtsi\"\n\n/ {\n\tcompatible = \"openmesh,a40\", \"qca,qca9558\";\n\tmodel = \"OpenMesh A40\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9558_openmesh_a60.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9558_openmesh_a60.dtsi\"\n\n/ {\n\tcompatible = \"openmesh,a60\", \"qca,qca9558\";\n\tmodel = \"OpenMesh A60\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9558_openmesh_a60.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca955x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tchosen {\n\t\t/delete-property/ bootargs;\n\t};\n\n\taliases {\n\t\tserial0 = &uart;\n\t\tled-boot = &led_status_green;\n\t\tled-failsafe = &led_status_green;\n\t\tled-running = &led_status_green;\n\t\tled-upgrade = &led_status_green;\n\t\tlabel-mac-device = &eth0;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tstatus_blue {\n\t\t\tlabel = \"blue:status\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tstatus_red {\n\t\t\tlabel = \"red:status\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tled_status_green: status_green {\n\t\t\tlabel = \"green:status\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n\n\twatchdog {\n\t\tcompatible = \"linux,wdt-gpio\";\n\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\thw_algo = \"toggle\";\n\t\t/* hw_margin_ms is actually 300s but driver limits it to 60s */\n\t\thw_margin_ms = <60000>;\n\t\talways-running;\n\t};\n};\n\n&usb_phy1 {\n\tstatus = \"okay\";\n};\n\n&usb1 {\n\tstatus = \"okay\";\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <40000000>;\n\n\t\t/* partitions are passed via bootloader */\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x040000 0x010000>;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tlabel = \"custom\";\n\t\t\t\treg = <0x050000 0x060000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@b0000 {\n\t\t\t\tlabel = \"inactive\";\n\t\t\t\treg = <0x0b0000 0x7a0000>;\n\t\t\t};\n\n\t\t\tpartition@850000 {\n\t\t\t\tlabel = \"inactive2\";\n\t\t\t\treg = <0x850000 0x7a0000>;\n\t\t\t};\n\n\t\t\tart: partition@ff0000 {\n\t\t\t\tlabel = \"ART\";\n\t\t\t\treg = <0xff0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy-mask = <0x6>;\n\n\tphy1: ethernet-phy@1 {\n\t\treg = <1>;\n\t\teee-broken-100tx;\n\t\teee-broken-1000t;\n\t};\n\n\tphy2: ethernet-phy@2 {\n\t\treg = <2>;\n\t\teee-broken-100tx;\n\t\teee-broken-1000t;\n\t\tat803x-override-sgmii-link-check;\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tpll-data = <0x82000101 0x80000101 0x80001313>;\n\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tphy-mode = \"rgmii-id\";\n\tphy-handle = <&phy1>;\n\n\tgmac-config {\n\t\tdevice = <&gmac>;\n\t\trgmii-enabled = <1>;\n\t\trxd-delay = <3>;\n\t\trxdv-delay = <3>;\n\t\ttxd-delay = <0>;\n\t\ttxen-delay = <0>;\n\t};\n};\n\n&eth1 {\n\tstatus = \"okay\";\n\n\tpll-data = <0x03000101 0x80000101 0x80001313>;\n\n\tnvmem-cells = <&macaddr_art_6>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tqca955x-sgmii-fixup;\n\n\tphy-handle = <&phy2>;\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <2>;\n};\n\n&pcie0 {\n\tstatus = \"okay\";\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n\n\tmacaddr_art_6: macaddr@6 {\n\t\treg = <0x6 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9558_openmesh_mr.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca955x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tchosen {\n\t\t/delete-property/ bootargs;\n\t};\n\n\taliases {\n\t\tserial0 = &uart;\n\t\tled-boot = &led_power_blue;\n\t\tled-failsafe = &led_power_blue;\n\t\tled-running = &led_power_blue;\n\t\tled-upgrade = &led_power_blue;\n\t\tlabel-mac-device = &eth0;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tlan_blue {\n\t\t\tlabel = \"blue:lan\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_wifi2g: wifi2g {\n\t\t\tlabel = \"blue:wifi2g\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tstatus_green {\n\t\t\tlabel = \"green:status\";\n\t\t\tgpios = <&gpio 19 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tstatus_red {\n\t\t\tlabel = \"red:status\";\n\t\t\tgpios = <&gpio 21 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_power_blue: power_blue {\n\t\t\tlabel = \"blue:power\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\tled_wifi5g: wifi5g {\n\t\t\tlabel = \"blue:wifi5g\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\twatchdog {\n\t\tcompatible = \"linux,wdt-gpio\";\n\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\thw_algo = \"toggle\";\n\t\t/* hw_margin_ms is actually 300s but driver limits it to 60s */\n\t\thw_margin_ms = <60000>;\n\t\talways-running;\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <40000000>;\n\n\t\t/* partitions are passed via bootloader */\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x040000 0x010000>;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tlabel = \"custom\";\n\t\t\t\treg = <0x050000 0x060000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@b0000 {\n\t\t\t\tlabel = \"inactive\";\n\t\t\t\treg = <0x0b0000 0x7a0000>;\n\t\t\t};\n\n\t\t\tpartition@850000 {\n\t\t\t\tlabel = \"inactive2\";\n\t\t\t\treg = <0x850000 0x7a0000>;\n\t\t\t};\n\n\t\t\tart: partition@ff0000 {\n\t\t\t\tlabel = \"ART\";\n\t\t\t\treg = <0xff0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy-mask = <0x20>;\n\n\tphy5: ethernet-phy@5 {\n\t\treg = <5>;\n\t\teee-broken-100tx;\n\t\teee-broken-1000t;\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tpll-data = <0x82000000 0x80000101 0x80001313>;\n\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tphy-mode = \"rgmii-id\";\n\tphy-handle = <&phy5>;\n\n\tgmac-config {\n\t\tdevice = <&gmac>;\n\t\trgmii-enabled = <1>;\n\t};\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <1>;\n};\n\n&pcie0 {\n\tstatus = \"okay\";\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9558_openmesh_mr1750-v1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9558_openmesh_mr.dtsi\"\n\n/ {\n\tcompatible = \"openmesh,mr1750-v1\", \"qca,qca9558\";\n\tmodel = \"OpenMesh MR1750 v1\";\n};\n\n&led_wifi2g {\n\tlinux,default-trigger = \"phy1tpt\";\n};\n\n&led_wifi5g {\n\tlinux,default-trigger = \"phy0tpt\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9558_openmesh_mr1750-v2.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9558_openmesh_mr.dtsi\"\n\n/ {\n\tcompatible = \"openmesh,mr1750-v2\", \"qca,qca9558\";\n\tmodel = \"OpenMesh MR1750 v2\";\n};\n\n&led_wifi2g {\n\tlinux,default-trigger = \"phy1tpt\";\n};\n\n&led_wifi5g {\n\tlinux,default-trigger = \"phy0tpt\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9558_openmesh_mr900-v1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9558_openmesh_mr.dtsi\"\n\n/ {\n\tcompatible = \"openmesh,mr900-v1\", \"qca,qca9558\";\n\tmodel = \"OpenMesh MR900 v1\";\n};\n\n&led_wifi2g {\n\tlinux,default-trigger = \"phy0tpt\";\n};\n\n&led_wifi5g {\n\tlinux,default-trigger = \"phy1tpt\";\n};\n\n&pcie0 {\n\twifi@0,0 {\n\t\tcompatible = \"pci168c,0033\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tnvmem-cells = <&macaddr_art_0>;\n\t\tnvmem-cell-names = \"mac-address\";\n\t\tmac-address-increment = <16>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9558_openmesh_mr900-v2.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9558_openmesh_mr.dtsi\"\n\n/ {\n\tcompatible = \"openmesh,mr900-v2\", \"qca,qca9558\";\n\tmodel = \"OpenMesh MR900 v2\";\n};\n\n&led_wifi2g {\n\tlinux,default-trigger = \"phy0tpt\";\n};\n\n&led_wifi5g {\n\tlinux,default-trigger = \"phy1tpt\";\n};\n\n&pcie0 {\n\twifi@0,0 {\n\t\tcompatible = \"pci168c,0033\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tnvmem-cells = <&macaddr_art_0>;\n\t\tnvmem-cell-names = \"mac-address\";\n\t\tmac-address-increment = <16>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9558_openmesh_om5p-ac-v1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca955x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"openmesh,om5p-ac-v1\", \"qca,qca9558\";\n\tmodel = \"OpenMesh OM5P-AC v1\";\n\n\tchosen {\n\t\t/delete-property/ bootargs;\n\t};\n\n\taliases {\n\t\tserial0 = &uart;\n\t\tled-boot = &led_power_blue;\n\t\tled-failsafe = &led_power_blue;\n\t\tled-running = &led_power_blue;\n\t\tled-upgrade = &led_power_blue;\n\t\tlabel-mac-device = &eth0;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power_blue: power_blue {\n\t\t\tlabel = \"blue:power\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\twan_blue {\n\t\t\tlabel = \"blue:wan\";\n\t\t\tgpios = <&gpio 19 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan_blue {\n\t\t\tlabel = \"blue:lan\";\n\t\t\tgpios = <&gpio 20 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twifi_green {\n\t\t\tlabel = \"green:wifi\";\n\t\t\tgpios = <&gpio 21 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\twifi_yellow {\n\t\t\tlabel = \"yellow:wifi\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twifi_red {\n\t\t\tlabel = \"red:wifi\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\ti2c {\n\t\tcompatible = \"i2c-gpio\";\n\t\tgpios = <&gpio 11 GPIO_ACTIVE_HIGH /* sda */\n\t\t\t &gpio 12 GPIO_ACTIVE_HIGH /* scl */\n\t\t\t>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\ti2c-gpio,scl-open-drain;\n\t\ti2c-gpio,sda-open-drain;\n\n\t\ttmp423a@4c {\n\t\t\tcompatible = \"ti,tmp423\";\n\t\t\treg = <0x4c>;\n\t\t};\n\t};\n\n\twatchdog {\n\t\tcompatible = \"linux,wdt-gpio\";\n\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\thw_algo = \"toggle\";\n\t\t/* hw_margin_ms is actually 300s but driver limits it to 60s */\n\t\thw_margin_ms = <60000>;\n\t\talways-running;\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <40000000>;\n\n\t\t/* partitions are passed via bootloader */\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x040000 0x010000>;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tlabel = \"custom\";\n\t\t\t\treg = <0x050000 0x060000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@b0000 {\n\t\t\t\tlabel = \"inactive\";\n\t\t\t\treg = <0x0b0000 0x7a0000>;\n\t\t\t};\n\n\t\t\tpartition@850000 {\n\t\t\t\tlabel = \"inactive2\";\n\t\t\t\treg = <0x850000 0x7a0000>;\n\t\t\t};\n\n\t\t\tart: partition@ff0000 {\n\t\t\t\tlabel = \"ART\";\n\t\t\t\treg = <0xff0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy-mask = <0x6>;\n\n\tphy1: ethernet-phy@1 {\n\t\treg = <1>;\n\t\teee-broken-100tx;\n\t\teee-broken-1000t;\n\t};\n\n\tphy2: ethernet-phy@2 {\n\t\treg = <2>;\n\t\teee-broken-100tx;\n\t\teee-broken-1000t;\n\t\tat803x-override-sgmii-link-check;\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tpll-data = <0x82000101 0x80000101 0x80001313>;\n\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tphy-mode = \"rgmii-id\";\n\tphy-handle = <&phy1>;\n\n\tgmac-config {\n\t\tdevice = <&gmac>;\n\t\trgmii-enabled = <1>;\n\t\trxd-delay = <3>;\n\t\trxdv-delay = <3>;\n\t\ttxd-delay = <0>;\n\t\ttxen-delay = <0>;\n\t};\n};\n\n&eth1 {\n\tstatus = \"okay\";\n\n\tpll-data = <0x03000101 0x80000101 0x80001313>;\n\n\tnvmem-cells = <&macaddr_art_6>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tqca955x-sgmii-fixup;\n\n\tphy-handle = <&phy2>;\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <2>;\n};\n\n&pcie1 {\n\tstatus = \"okay\";\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n\n\tmacaddr_art_6: macaddr@6 {\n\t\treg = <0x6 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9558_openmesh_om5p-ac-v2.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca955x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"openmesh,om5p-ac-v2\", \"qca,qca9558\";\n\tmodel = \"OpenMesh OM5P-AC v2\";\n\n\tchosen {\n\t\t/delete-property/ bootargs;\n\t};\n\n\taliases {\n\t\tserial0 = &uart;\n\t\tled-boot = &led_power_blue;\n\t\tled-failsafe = &led_power_blue;\n\t\tled-running = &led_power_blue;\n\t\tled-upgrade = &led_power_blue;\n\t\tlabel-mac-device = &eth0;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twifi_green {\n\t\t\tlabel = \"green:wifi\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\tled_power_blue: power_blue {\n\t\t\tlabel = \"blue:power\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\twifi_yellow {\n\t\t\tlabel = \"yellow:wifi\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twifi_red {\n\t\t\tlabel = \"red:wifi\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 1 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\ti2c {\n\t\tcompatible = \"i2c-gpio\";\n\t\tgpios = <&gpio 19 GPIO_ACTIVE_HIGH /* sda */\n\t\t\t &gpio 18 GPIO_ACTIVE_HIGH /* scl */\n\t\t\t>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\ti2c-gpio,scl-open-drain;\n\t\ti2c-gpio,sda-open-drain;\n\n\t\ttmp423a@4e {\n\t\t\tcompatible = \"ti,tmp423\";\n\t\t\treg = <0x4e>;\n\t\t};\n\t};\n\n\twatchdog {\n\t\tcompatible = \"linux,wdt-gpio\";\n\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\thw_algo = \"toggle\";\n\t\t/* hw_margin_ms is actually 300s but driver limits it to 60s */\n\t\thw_margin_ms = <60000>;\n\t\talways-running;\n\t};\n\n\tgpio-export {\n\t\tcompatible = \"gpio-export\";\n\t\t#size-cells = <0>;\n\n\t\tgpio_pa_dcdc {\n\t\t\tgpio-export,name = \"om5pac:pa_dcdc\";\n\t\t\tgpio-export,output = <1>;\n\t\t\tgpios = <&gpio 2 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t\tgpio_pa_high {\n\t\t\tgpio-export,name = \"om5pac:pa_high\";\n\t\t\tgpio-export,output = <1>;\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&pinmux {\n\tpinmux_pa_dcdc_pins {\n\t\tpinctrl-single,bits = <0x0 0x0 0xff0000>;\n\t};\n\n\tpinmux_pa_high_pins {\n\t\tpinctrl-single,bits = <0x10 0x0 0xff>;\n\t};\n};\n\n&pcie0 {\n\tstatus = \"okay\";\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\t/* partitions are passed via bootloader */\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x040000 0x010000>;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tlabel = \"custom\";\n\t\t\t\treg = <0x050000 0x060000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@b0000 {\n\t\t\t\tlabel = \"inactive\";\n\t\t\t\treg = <0x0b0000 0x7a0000>;\n\t\t\t};\n\n\t\t\tpartition@850000 {\n\t\t\t\tlabel = \"inactive2\";\n\t\t\t\treg = <0x850000 0x7a0000>;\n\t\t\t};\n\n\t\t\tart: partition@ff0000 {\n\t\t\t\tlabel = \"ART\";\n\t\t\t\treg = <0xff0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy-mask = <0x10>;\n\n\tphy4: ethernet-phy@4 {\n\t\treg = <4>;\n\t\teee-broken-100tx;\n\t\teee-broken-1000t;\n\t};\n};\n\n&mdio1 {\n\tstatus = \"okay\";\n\n\tphy-mask = <0x2>;\n\n\tphy1: ethernet-phy@1 {\n\t\treg = <1>;\n\t\teee-broken-100tx;\n\t\teee-broken-1000t;\n\t\tat803x-override-sgmii-link-check;\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tpll-data = <0x82000101 0x80000101 0x80001313>;\n\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tphy-mode = \"rgmii-id\";\n\tphy-handle = <&phy4>;\n\n\tgmac-config {\n\t\tdevice = <&gmac>;\n\t\trgmii-enabled = <1>;\n\t\trxd-delay = <2>;\n\t\trxdv-delay = <2>;\n\t\ttxd-delay = <0>;\n\t\ttxen-delay = <0>;\n\t};\n};\n\n&eth1 {\n\tstatus = \"okay\";\n\n\tpll-data = <0x03000101 0x80000101 0x80001313>;\n\n\tnvmem-cells = <&macaddr_art_6>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tqca955x-sgmii-fixup;\n\n\tphy-handle = <&phy1>;\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <2>;\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n\n\tmacaddr_art_6: macaddr@6 {\n\t\treg = <0x6 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9558_qxwlan_e558-v2-16m.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9558_qxwlan_e558.dtsi\"\n\n/ {\n\tmodel = \"Qxwlan E558 v2 16M\";\n\tcompatible = \"qxwlan,e558-v2-16m\", \"qca,qca9558\";\n};\n\n&partitions {\n\tpartition@70000 {\n\t\tcompatible = \"denx,uimage\";\n\t\tlabel = \"firmware\";\n\t\treg = <0x070000 0xf90000>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9558_qxwlan_e558-v2-8m.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9558_qxwlan_e558.dtsi\"\n\n/ {\n\tmodel = \"Qxwlan E558 v2 8M\";\n\tcompatible = \"qxwlan,e558-v2-8m\", \"qca,qca9558\";\n};\n\n&partitions {\n\tpartition@70000 {\n\t\tcompatible = \"denx,uimage\";\n\t\tlabel = \"firmware\";\n\t\treg = <0x070000 0x790000>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9558_qxwlan_e558.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca955x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\taliases {\n\t\tled-boot = &led_system;\n\t\tled-failsafe = &led_system;\n\t\tled-running = &led_system;\n\t\tled-upgrade = &led_system;\n\t\tlabel-mac-device = &eth0;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"Reset button\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twlan {\n\t\t\tlabel = \"green:wlan\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\tled_system: system {\n\t\t\tlabel = \"green:system\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\tsig1 {\n\t\t\tlabel = \"green:sig1\";\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tsig2 {\n\t\t\tlabel = \"green:sig2\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&pcie0 {\n\tstatus = \"okay\";\n};\n\n&pcie1 {\n\tstatus = \"okay\";\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions: partitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x040000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpridata: partition@50000 {\n\t\t\t\tlabel = \"pri-data\";\n\t\t\t\treg = <0x050000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tart: partition@60000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0x060000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\n\t\tqca,ar8327-initvals = <\n\t\t\t0x04 0x00080080 /* PORT0 PAD MODE CTRL */\n\t\t\t0x0c 0x07600000 /* PORT6 PAD MODE CTRL */\n\t\t\t0x10 0x81000080 /* POWER_ON_STRAP */\n\t\t\t0x50 0xcc35cc35 /* LED_CTRL0 */\n\t\t\t0x54 0xca35ca35 /* LED_CTRL1 */\n\t\t\t0x58 0xc935c935 /* LED_CTRL2 */\n\t\t\t0x5c 0x03ffff00 /* LED_CTRL3 */\n\t\t\t0x7c 0x0000007e /* PORT0_STATUS */\n\t\t\t0x94 0x0000007e /* PORT6 STATUS */\n\t\t>;\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tpll-data = <0x56000000 0x00000101 0x00001616>;\n\n\tphy-handle = <&phy0>;\n\n\tnvmem-cells = <&macaddr_pridata_400>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <1>;\n};\n\n&eth1 {\n\tstatus = \"okay\";\n\n\tpll-data = <0x03000101 0x00000101 0x00001616>;\n\n\tnvmem-cells = <&macaddr_pridata_400>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tfixed-link {\n\t\tspeed = <1000>;\n\t\tfull-duplex;\n\t};\n};\n\n&usb_phy0 {\n\tstatus = \"okay\";\n};\n\n&usb0 {\n\tstatus = \"okay\";\n};\n\n&usb_phy1 {\n\tstatus = \"okay\";\n};\n\n&usb1 {\n\tstatus = \"okay\";\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n};\n\n&pridata {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_pridata_400: macaddr@400 {\n\t\treg = <0x400 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9558_sitecom_wlr-8100.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca955x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"Sitecom WLR-8100 (X8 AC1750)\";\n\tcompatible = \"sitecom,wlr-8100\", \"qca,qca9558\";\n\n\taliases {\n\t\tled-boot = &led_status_amber;\n\t\tled-failsafe = &led_status_amber;\n\t\tled-running = &led_status_amber;\n\t\tled-upgrade = &led_status_amber;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\twifi2g_rfkill {\n\t\t\tlabel = \"2.4GHz - RFKILL\";\n\t\t\tgpios = <&gpio 21 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RFKILL>;\n\t\t};\n\n\t\twifi5g_restart {\n\t\t\tlabel = \"5GHz - RESTART\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_status_amber: status_amber {\n\t\t\tlabel = \"amber:status\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\tops {\n\t\t\tlabel = \"white:ops\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twifi2g {\n\t\t\tlabel = \"blue:wifi2g\";\n\t\t\tgpios = <&gpio 19 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\n\t\twifi5g {\n\t\t\tlabel = \"blue:wifi5g\";\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tuboot: partition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x030000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x030000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x040000 0xf10000>;\n\t\t\t};\n\n\t\t\tpartition@f50000 {\n\t\t\t\tlabel = \"manufacture\";\n\t\t\t\treg = <0xf50000 0x040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@f90000 {\n\t\t\t\tlabel = \"backup\";\n\t\t\t\treg = <0xf90000  0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@fa0000 {\n\t\t\t\tlabel = \"storage\";\n\t\t\t\treg = <0xfa0000 0x050000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tart: partition@ff0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0xff0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pcie0 {\n\tstatus = \"okay\";\n};\n\n&pcie1 {\n\tstatus = \"okay\";\n\n\twifi@0,0 {\n\t\tcompatible = \"qcom,ath10k\";\n\t\treg = <0 0 0 0 0>;\n\t};\n};\n\n&usb_phy0 {\n\tstatus = \"okay\";\n};\n\n&usb0 {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\tstatus = \"okay\";\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\n\t\tqca,ar8327-initvals = <\n\t\t\t0x04 0x87600000 /* PORT0 PAD MODE CTRL */\n\t\t\t0x50 0xcf37cf37 /* LED Control Register 0 */\n\t\t\t0x54 0x00000000 /* LED Control Register 1 */\n\t\t\t0x58 0x00000000 /* LED Control Register 2 */\n\t\t\t0x5c 0x0030c300 /* LED Control Register 3 */\n\t\t\t0x7c 0x0000007e /* PORT0_STATUS */\n\t\t\t>;\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\tphy-handle = <&phy0>;\n\tpll-data = <0xa6000000 0x00000101 0x00001616>;\n\n\tgmac-config {\n\t\tdevice = <&gmac>;\n\t\trgmii-enabled = <1>;\n\t};\n};\n\n&wmac {\n\tstatus = \"okay\";\n\tqca,no-eeprom;\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9558_sophos_ap.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n/*\n * The hardware of this board family is most likely shared with other devices\n * from other manufacturers. Edimax appear to be the actual OEM.\n *\n * Sophos use the same exact board for the AP55C/AP100C, and AP55/AP100.\n * Yes, this means your AP55C is a 3x3 AP with a software lock, and your\n * AP55 is an AP100 with one missing antenna pigtail.\n *\n * AP55 and AP55C boards have different physical layouts, but are logically\n * almost identical. AP55/100 have an empty micro-USB OTG port footprint,\n * which may be possible to retrofit with some work.\n */\n\n#include \"qca955x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\taliases {\n\t\tled-boot = &led_status_green;\n\t\tled-failsafe = &led_status_red;\n\t\tled-running = &led_status_green;\n\t\tled-upgrade = &led_status_red;\n\t\tlabel-mac-device = &eth0;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200n8\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_status_green: status_green {\n\t\t\tlabel = \"green:status\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\tled_status_red: status_red {\n\t\t\tlabel = \"red:status\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\treg_usb_vbus: reg_usb_vbus {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"usb_vbus\";\n\t\tregulator-min-microvolt = <5000000>;\n\t\tregulator-max-microvolt = <5000000>;\n\t\tgpio = <&gpio 11 GPIO_ACTIVE_HIGH>;\n\t\tenable-active-high;\n\t\tregulator-boot-on;\n\t\tstatus = \"disabled\";\n\t};\n};\n\n&pcie0 {\n\tstatus = \"okay\";\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x040000 0x010000>;\n\t\t\t};\n\n\t\t\tart: partition@50000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0x050000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tconfig: partition@60000 {\n\t\t\t\tlabel = \"config\";\n\t\t\t\treg = <0x060000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@70000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x070000 0xf90000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy-mask = <0x10>;\n\n\tphy4: ethernet-phy@4 {\n\t\treg = <4>;\n\t\teee-broken-100tx;\n\t\teee-broken-1000t;\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tpll-data = <0xa6000000 0xa0000101 0xa0001313>;\n\n\tnvmem-cells = <&macaddr_config_201a>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tphy-mode = \"rgmii-id\";\n\tphy-handle = <&phy4>;\n\n\tgmac_config: gmac-config {\n\t\tdevice = <&gmac>;\n\n\t\trgmii-enabled = <1>;\n\n\t\trxdv-delay = <3>;\n\t\trxd-delay = <3>;\n\t\ttxen-delay = <3>;\n\t\ttxd-delay = <3>;\n\t};\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n};\n\n&config {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_config_201a: macaddr@201a {\n\t\treg = <0x201a 0x6>;\n\t};\n};\n\n&usb0 {\n\tvbus-supply = <&reg_usb_vbus>;\n\n\thub_port0: port@1 {\n\t\treg = <1>;\n\t\t#trigger-source-cells = <0>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9558_sophos_ap100.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9558_sophos_ap.dtsi\"\n\n/ {\n\tcompatible = \"sophos,ap100\", \"qca,qca9558\";\n\tmodel = \"Sophos AP100\";\n};\n\n&reg_usb_vbus {\n\tstatus = \"okay\";\n};\n\n&usb_phy0 {\n\tstatus = \"okay\";\n};\n\n&usb0 {\n\tstatus = \"okay\";\n\tdr_mode = \"host\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9558_sophos_ap100c.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9558_sophos_ap.dtsi\"\n\n/ {\n\tcompatible = \"sophos,ap100c\", \"qca,qca9558\";\n\tmodel = \"Sophos AP100C\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9558_sophos_ap55.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9558_sophos_ap.dtsi\"\n\n/ {\n\tcompatible = \"sophos,ap55\", \"qca,qca9558\";\n\tmodel = \"Sophos AP55\";\n};\n\n&reg_usb_vbus {\n\tstatus = \"okay\";\n};\n\n&usb_phy0 {\n\tstatus = \"okay\";\n};\n\n&usb0 {\n\tstatus = \"okay\";\n\tdr_mode = \"host\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9558_sophos_ap55c.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9558_sophos_ap.dtsi\"\n\n/ {\n\tcompatible = \"sophos,ap55c\", \"qca,qca9558\";\n\tmodel = \"Sophos AP55C\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9558_tplink_archer-c.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca955x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\taliases {\n\t\tled-boot = &led_system;\n\t\tled-failsafe = &led_system;\n\t\tled-running = &led_system;\n\t\tled-upgrade = &led_system;\n\t};\n\n\tleds: leds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_system: system {\n\t\t\tlabel = \"green:system\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\tusb1 {\n\t\t\tlabel = \"green:usb1\";\n\t\t\tgpios = <&gpio 19 GPIO_ACTIVE_LOW>;\n\t\t\ttrigger-sources = <&hub_port1>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\n\t\tusb2 {\n\t\t\tlabel = \"green:usb2\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t\t\ttrigger-sources = <&hub_port0>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\n\t\twlan2g {\n\t\t\tlabel = \"green:wlan2g\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\n\t\tqss {\n\t\t\tlabel = \"green:qss\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys: keys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"Reset button\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tgpio-export {\n\t\tcompatible = \"gpio-export\";\n\n\t\tgpio_usb1_power {\n\t\t\tgpio-export,name = \"tp-link:power:usb1\";\n\t\t\tgpio-export,output = <1>;\n\t\t\tgpios = <&gpio 21 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tgpio_usb2_power {\n\t\t\tgpio-export,name = \"tp-link:power:usb2\";\n\t\t\tgpio-export,output = <1>;\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&pcie1 {\n\tstatus = \"okay\";\n};\n\n&usb_phy0 {\n\tstatus = \"okay\";\n};\n\n&usb0 {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\tstatus = \"okay\";\n\n\thub_port0: port@1 {\n\t\treg = <1>;\n\t\t#trigger-source-cells = <0>;\n\t};\n};\n\n&usb_phy1 {\n\tstatus = \"okay\";\n};\n\n&usb1 {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\tstatus = \"okay\";\n\n\thub_port1: port@1 {\n\t\treg = <1>;\n\t\t#trigger-source-cells = <0>;\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tmtdparts: partitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\t\t};\n\t};\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\n\t\tqca,ar8327-initvals = <\n\t\t\t0x04 0x00080080 /* PORT0 PAD MODE CTRL */\n\t\t\t0x0c 0x07600000 /* PORT6 PAD MODE CTRL */\n\t\t\t0x50 0xc737c737 /* LED_CTRL0 */\n\t\t\t0x54 0x00000000 /* LED_CTRL1 */\n\t\t\t0x58 0x00000000 /* LED_CTRL2 */\n\t\t\t0x5c 0x0030c300 /* LED_CTRL3 */\n\t\t\t0x7c 0x0000007e /* PORT0_STATUS */\n\t\t\t0x94 0x0000007e /* PORT6 STATUS */\n\t\t\t>;\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tphy-handle = <&phy0>;\n\tpll-data = <0x56000000 0x00000101 0x00001616>;\n\n\tgmac-config {\n\t\tdevice = <&gmac>;\n\t\trgmii-enabled = <1>;\n\t};\n};\n\n&eth1 {\n\tstatus = \"okay\";\n\n\tpll-data = <0x03000101 0x00000101 0x00001616>;\n\n\tfixed-link {\n\t\tspeed = <1000>;\n\t\tfull-duplex;\n\t};\n};\n\n&wmac {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9558_tplink_archer-c5-v1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9558_tplink_archer-c.dtsi\"\n\n/ {\n\tcompatible = \"tplink,archer-c5-v1\", \"qca,qca9558\";\n\tmodel = \"TP-Link Archer C5 v1\";\n\n\taliases {\n\t\tlabel-mac-device = &eth1;\n\t};\n};\n\n&keys {\n\trfkill {\n\t\tgpios = <&gpio 23 GPIO_ACTIVE_LOW>;\n\t\tlinux,code = <KEY_RFKILL>;\n\t\tlinux,input-type = <EV_SW>;\n\t\tdebounce-interval = <60>;\n\t};\n};\n\n&leds {\n\twlan5g {\n\t\tlabel = \"green:wlan5g\";\n\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\tlinux,default-trigger = \"phy0tpt\";\n\t};\n};\n\n&mtdparts {\n\tuboot: partition@0 {\n\t\tlabel = \"u-boot\";\n\t\treg = <0x000000 0x020000>;\n\t\tread-only;\n\t};\n\n\tpartition@20000 {\n\t\tlabel = \"firmware\";\n\t\treg = <0x020000 0xfd0000>;\n\t\tcompatible = \"tplink,firmware\";\n\t};\n\n\tart: partition@ff0000 {\n\t\tlabel = \"art\";\n\t\treg = <0xff0000 0x010000>;\n\t\tread-only;\n\t};\n};\n\n&eth0 {\n\tnvmem-cells = <&macaddr_uboot_1fc00>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <1>;\n};\n\n&eth1 {\n\tnvmem-cells = <&macaddr_uboot_1fc00>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wmac {\n\tmtd-cal-data = <&art 0x1000>;\n\n\tnvmem-cells = <&macaddr_uboot_1fc00>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&uboot {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_uboot_1fc00: macaddr@1fc00 {\n\t\treg = <0x1fc00 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9558_tplink_archer-c7-v1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9558_tplink_archer-c.dtsi\"\n\n/ {\n\tcompatible = \"tplink,archer-c7-v1\", \"qca,qca9558\";\n\tmodel = \"TP-Link Archer C7 v1\";\n\n\taliases {\n\t\tlabel-mac-device = &eth1;\n\t};\n};\n\n&keys {\n\trfkill {\n\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\tlinux,code = <KEY_RFKILL>;\n\t\tlinux,input-type = <EV_SW>;\n\t\tdebounce-interval = <60>;\n\t};\n};\n\n&leds {\n\twlan5g {\n\t\tlabel = \"green:wlan5g\";\n\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\tlinux,default-trigger = \"phy0tpt\";\n\t};\n};\n\n&mtdparts {\n\tuboot: partition@0 {\n\t\tlabel = \"u-boot\";\n\t\treg = <0x000000 0x020000>;\n\t\tread-only;\n\t};\n\n\tpartition@20000 {\n\t\tlabel = \"firmware\";\n\t\tcompatible = \"tplink,firmware\";\n\t\treg = <0x020000 0x7d0000>;\n\t};\n\n\tpartition@7f0000 {\n\t\tlabel = \"art\";\n\t\treg = <0x7f0000 0x010000>;\n\t\tread-only;\n\n\t\tcompatible = \"nvmem-cells\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tcalibration_art_1000: calibration@1000 {\n\t\t\treg = <0x1000 0x440>;\n\t\t};\n\t};\n};\n\n&eth0 {\n\tnvmem-cells = <&macaddr_uboot_1fc00>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <1>;\n};\n\n&eth1 {\n\tnvmem-cells = <&macaddr_uboot_1fc00>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wmac {\n\tnvmem-cells = <&macaddr_uboot_1fc00>, <&calibration_art_1000>;\n\tnvmem-cell-names = \"mac-address\", \"calibration\";\n};\n\n&uboot {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_uboot_1fc00: macaddr@1fc00 {\n\t\treg = <0x1fc00 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9558_tplink_archer-c7-v2.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9558_tplink_archer-c.dtsi\"\n\n/ {\n\tcompatible = \"tplink,archer-c7-v2\", \"qca,qca9558\";\n\tmodel = \"TP-Link Archer C7 v2\";\n\n\taliases {\n\t\tlabel-mac-device = &eth1;\n\t};\n};\n\n&keys {\n\trfkill {\n\t\tgpios = <&gpio 23 GPIO_ACTIVE_LOW>;\n\t\tlinux,code = <KEY_RFKILL>;\n\t\tlinux,input-type = <EV_SW>;\n\t\tdebounce-interval = <60>;\n\t};\n};\n\n&leds {\n\twlan5g {\n\t\tlabel = \"green:wlan5g\";\n\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\tlinux,default-trigger = \"phy0tpt\";\n\t};\n};\n\n&mtdparts {\n\tuboot: partition@0 {\n\t\tlabel = \"u-boot\";\n\t\treg = <0x000000 0x020000>;\n\t\tread-only;\n\t};\n\n\tpartition@20000 {\n\t\tlabel = \"firmware\";\n\t\treg = <0x020000 0xfd0000>;\n\t\tcompatible = \"tplink,firmware\";\n\t};\n\n\tart: partition@ff0000 {\n\t\tlabel = \"art\";\n\t\treg = <0xff0000 0x010000>;\n\t\tread-only;\n\n\t\tcompatible = \"nvmem-cells\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tcalibration_art_1000: calibration@1000 {\n\t\t\treg = <0x1000 0x440>;\n\t\t};\n\n\t\tcalibration_art_5000: calibration@5000 {\n\t\t\treg = <0x5000 0x844>;\n\t\t};\n\t};\n};\n\n&eth0 {\n\tnvmem-cells = <&macaddr_uboot_1fc00>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <1>;\n};\n\n&eth1 {\n\tnvmem-cells = <&macaddr_uboot_1fc00>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&pcie1 {\n\tstatus = \"okay\";\n\n\twifi@0,0 {\n\t\tcompatible = \"qcom,ath10k\";\n\t\treg = <0 0 0 0 0>;\n\n\t\tmac-address-increment = <(-1)>;\n\t\tnvmem-cells = <&macaddr_uboot_1fc00>, <&calibration_art_5000>;\n\t\tnvmem-cell-names = \"mac-address\", \"calibration\";\n\t};\n};\n\n&wmac {\n\tnvmem-cells = <&macaddr_uboot_1fc00>, <&calibration_art_1000>;\n\tnvmem-cell-names = \"mac-address\", \"calibration\";\n};\n\n&uboot {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_uboot_1fc00: macaddr@1fc00 {\n\t\treg = <0x1fc00 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9558_tplink_archer-d7-v1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9558_tplink_archer-d7.dtsi\"\n\n/ {\n\tcompatible = \"tplink,archer-d7-v1\", \"qca,qca9558\";\n\tmodel = \"TP-Link Archer D7 v1\";\n\n\taliases {\n\t\tlabel-mac-device = &wmac;\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x020000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tcompatible = \"tplink,firmware\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x020000 0xf90000>;\n\t\t\t};\n\n\t\t\tpartition@fb0000 {\n\t\t\t\tlabel = \"radioDECT\";\n\t\t\t\treg = <0xfb0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@fc0000 {\n\t\t\t\tlabel = \"config\";\n\t\t\t\treg = <0xfc0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tromfs: partition@fd0000 {\n\t\t\t\tlabel = \"romfs\";\n\t\t\t\treg = <0xfd0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@fe0000 {\n\t\t\t\tlabel = \"rom\";\n\t\t\t\treg = <0xfe0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tart: partition@ff0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0xff0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&eth0 {\n\tnvmem-cells = <&macaddr_romfs_f100>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <1>;\n};\n\n&eth1 {\n\tnvmem-cells = <&macaddr_romfs_f100>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wmac {\n\tmtd-cal-data = <&art 0x1000>;\n\tnvmem-cells = <&macaddr_romfs_f100>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&romfs {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_romfs_f100: macaddr@f100 {\n\t\treg = <0xf100 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9558_tplink_archer-d7.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca955x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\taliases {\n\t\tled-boot = &led_system;\n\t\tled-failsafe = &led_system;\n\t\tled-running = &led_system;\n\t\tled-upgrade = &led_system;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_system: system {\n\t\t\tlabel = \"white:system\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\twlan {\n\t\t\tlabel = \"white:wlan\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan {\n\t\t\tlabel = \"white:lan\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tusb {\n\t\t\tlabel = \"white:usb\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t\t\ttrigger-sources = <&hub_port1>, <&hub_port0>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\n\t\tqss {\n\t\t\tlabel = \"white:qss\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\twifi {\n\t\t\tlabel = \"WiFi button\";\n\t\t\tlinux,code = <KEY_RFKILL>;\n\t\t\tgpios = <&gpio 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"WPS button\";\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tgpios = <&gpio 1 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"Reset button\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\treg_usb0_vbus: regulator {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"usb_vbus\";\n\t\tregulator-min-microvolt = <5000000>;\n\t\tregulator-max-microvolt = <5000000>;\n\t\tgpio = <&gpio 21 GPIO_ACTIVE_HIGH>;\n\t\tenable-active-high;\n\t};\n\n\treg_usb1_vbus: regulator {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"usb_vbus\";\n\t\tregulator-min-microvolt = <5000000>;\n\t\tregulator-max-microvolt = <5000000>;\n\t\tgpio = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\tenable-active-high;\n\t};\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\n\t\tqca,ar8327-initvals = <\n\t\t\t0x04 0x00080080 /* PORT0 PAD MODE CTRL */\n\t\t\t0x0c 0x07600000 /* PORT6 PAD MODE CTRL */\n\t\t\t0x50 0xc737c737 /* LED_CTRL0 */\n\t\t\t0x54 0x00000000 /* LED_CTRL1 */\n\t\t\t0x58 0x00000000 /* LED_CTRL2 */\n\t\t\t0x5c 0x0030c300 /* LED_CTRL3 */\n\t\t\t0x7c 0x0000007e /* PORT0_STATUS */\n\t\t\t0x94 0x0000007e /* PORT6 STATUS */\n\t\t\t>;\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tphy-handle = <&phy0>;\n\tpll-data = <0x56000000 0x00000101 0x00001616>;\n\n\tgmac-config {\n\t\tdevice = <&gmac>;\n\t\trgmii-enabled = <1>;\n\t};\n};\n\n&eth1 {\n\tstatus = \"okay\";\n\n\tpll-data = <0x03000101 0x00000101 0x00001616>;\n\n\tfixed-link {\n\t\tspeed = <1000>;\n\t\tfull-duplex;\n\t};\n};\n\n&wmac {\n\tstatus = \"okay\";\n};\n\n&pcie1 {\n\tstatus = \"okay\";\n};\n\n&usb_phy0 {\n\tstatus = \"okay\";\n};\n\n&usb0 {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\tdr_mode = \"host\";\n\tvbus-supply = <&reg_usb0_vbus>;\n\tstatus = \"okay\";\n\n\thub_port0: port@1 {\n\t\treg = <1>;\n\t\t#trigger-source-cells = <0>;\n\t};\n};\n\n&usb_phy1 {\n\tstatus = \"okay\";\n};\n\n&usb1 {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\tdr_mode = \"host\";\n\tvbus-supply = <&reg_usb1_vbus>;\n\tstatus = \"okay\";\n\n\thub_port1: port@1 {\n\t\treg = <1>;\n\t\t#trigger-source-cells = <0>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9558_tplink_archer-d7b-v1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9558_tplink_archer-d7.dtsi\"\n\n/ {\n\tcompatible = \"tplink,archer-d7b-v1\", \"qca,qca9558\";\n\tmodel = \"TP-Link Archer D7b v1\";\n\n\taliases {\n\t\tlabel-mac-device = &wmac;\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x020000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tcompatible = \"tplink,firmware\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x020000 0xfa0000>;\n\t\t\t};\n\n\t\t\tpartition@fc0000 {\n\t\t\t\tlabel = \"config\";\n\t\t\t\treg = <0xfc0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tromfs: partition@fd0000 {\n\t\t\t\tlabel = \"romfs\";\n\t\t\t\treg = <0xfd0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@fe0000 {\n\t\t\t\tlabel = \"reserve\";\n\t\t\t\treg = <0xfe0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tart: partition@ff0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0xff0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&eth0 {\n\tnvmem-cells = <&macaddr_romfs_f100>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <1>;\n};\n\n&eth1 {\n\tnvmem-cells = <&macaddr_romfs_f100>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wmac {\n\tmtd-cal-data = <&art 0x1000>;\n\tnvmem-cells = <&macaddr_romfs_f100>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&romfs {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_romfs_f100: macaddr@f100 {\n\t\treg = <0xf100 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9558_tplink_re350k-v1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca955x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"TP-Link RE350K v1\";\n\tcompatible = \"tplink,re350k-v1\", \"qca,qca9558\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t\tmdio-gpio0 = &mdio2;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\tapp-config {\n\t\t\tlabel = \"app-config\";\n\t\t\tlinux,code = <BTN_0>;\n\t\t\tgpios = <&gpio 20 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\tled {\n\t\t\tlabel = \"led\";\n\t\t\tlinux,code = <BTN_1>;\n\t\t\tgpios = <&gpio 19 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\twlan2g_green {\n\t\t\tlabel = \"green:wlan2g\";\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\n\t\twlan2g_red {\n\t\t\tlabel = \"red:wlan2g\";\n\t\t\tgpios = <&gpio 21 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan5g_green {\n\t\t\tlabel = \"green:wlan5g\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\twlan5g_red {\n\t\t\tlabel = \"red:wlan5g\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tmdio2: mdio {\n\t\tcompatible = \"virtual,mdio-gpio\";\n\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>,\n\t\t\t<&gpio 18 GPIO_ACTIVE_HIGH>;\n\n\t\tphy4: ethernet-phy@4 {\n\t\t\treg = <4>;\n\n\t\t\tphy-mode = \"rgmii-rxid\";\n\t\t\teee-broken-100tx;\n\t\t\teee-broken-1000t;\n\t\t};\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tphy-handle = <&phy4>;\n\tpll-data = <0x9e000000 0x80000101 0x80001313>;\n\n\tnvmem-cells = <&macaddr_info_8>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tgmac-config {\n\t\tdevice = <&gmac>;\n\n\t\trxdv-delay = <2>;\n\t\trxd-delay = <2>;\n\t\ttxen-delay = <0>;\n\t\ttxd-delay = <0>;\n\t\trgmii-enabled = <1>;\n\t};\n};\n\n&pcie0 {\n\tstatus = \"okay\";\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x020000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tcompatible = \"tplink,firmware\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x020000 0xd70000>;\n\t\t\t};\n\n\t\t\tpartition@d90000 {\n\t\t\t\tlabel = \"partition-table\";\n\t\t\t\treg = <0xd90000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tinfo: partition@da0000 {\n\t\t\t\tlabel = \"info\";\n\t\t\t\treg = <0xda0000 0x020000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@dc0000 {\n\t\t\t\tlabel = \"config\";\n\t\t\t\treg = <0xdc0000 0x230000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tart: partition@ff0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0xff0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n\tnvmem-cells = <&macaddr_info_8>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&info {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_info_8: macaddr@8 {\n\t\treg = <0x8 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9558_tplink_re355-v1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9558_tplink_rex5x.dtsi\"\n\n/ {\n\tcompatible = \"tplink,re355-v1\", \"qca,qca9558\";\n\tmodel = \"TP-Link RE355 v1\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9558_tplink_re450-v1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9558_tplink_rex5x.dtsi\"\n\n/ {\n\tcompatible = \"tplink,re450-v1\", \"qca,qca9558\";\n\tmodel = \"TP-Link RE450 v1\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9558_tplink_rex5x.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca955x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t\tmdio-gpio0 = &mdio2;\n\t\tlabel-mac-device = &eth0;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"blue:power\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan2g {\n\t\t\tlabel = \"blue:wlan2g\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\n\t\twlan5g {\n\t\t\tlabel = \"blue:wlan5g\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\tlan_link {\n\t\t\tlabel = \"green:lan_link\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan_data {\n\t\t\tlabel = \"green:lan_data\";\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twps_blue {\n\t\t\tlabel = \"blue:wps\";\n\t\t\tgpios = <&gpio 21 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\twps_red {\n\t\t\tlabel = \"red:wps\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"Reset button\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\tleds {\n\t\t\tlabel = \"LED control button\";\n\t\t\tlinux,code = <BTN_0>;\n\t\t\tgpios = <&gpio 19 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"WPS button\";\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tgpios = <&gpio 20 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tmdio2: mdio {\n\t\tcompatible = \"virtual,mdio-gpio\";\n\n\t\tgpios = <&gpio 3 GPIO_ACTIVE_HIGH>, /* MDC */\n\t\t\t<&gpio 1 GPIO_ACTIVE_HIGH>; /* MDIO */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tphy4: ethernet-phy@4 {\n\t\t\treg = <4>;\n\t\t\treset-gpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&pcie0 {\n\tstatus = \"okay\";\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x020000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tcompatible = \"tplink,firmware\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x020000 0x5e0000>;\n\t\t\t};\n\n\t\t\tpartition@600000 {\n\t\t\t\tlabel = \"partition-table\";\n\t\t\t\treg = <0x600000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tinfo: partition@610000 {\n\t\t\t\tlabel = \"info\";\n\t\t\t\treg = <0x610000 0x020000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@630000 {\n\t\t\t\tlabel = \"config\";\n\t\t\t\treg = <0x630000 0x1c0000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tart: partition@7f0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0x7f0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tphy-handle = <&phy4>;\n\tpll-data = <0xa6000000 0x00000101 0x00001616>;\n\n\tnvmem-cells = <&macaddr_info_8>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n\tnvmem-cells = <&macaddr_info_8>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <(-1)>;\n};\n\n&info {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_info_8: macaddr@8 {\n\t\treg = <0x8 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9558_tplink_tl-wdr4900-v2.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca955x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"tplink,tl-wdr4900-v2\", \"qca,qca9558\";\n\tmodel = \"TP-Link TL-WDR4900 v2\";\n\n\taliases {\n\t\tled-boot = &led_system;\n\t\tled-failsafe = &led_system;\n\t\tled-running = &led_system;\n\t\tled-upgrade = &led_system;\n\t\tlabel-mac-device = &eth1;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_system: system {\n\t\t\tlabel = \"blue:system\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\tusb1 {\n\t\t\tlabel = \"green:usb1\";\n\t\t\tgpios = <&gpio 19 GPIO_ACTIVE_LOW>;\n\t\t\ttrigger-sources = <&hub_port1>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\n\t\tusb2 {\n\t\t\tlabel = \"green:usb2\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t\t\ttrigger-sources = <&hub_port0>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\n\t\twlan2g {\n\t\t\tlabel = \"blue:wlan2g\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\tqss {\n\t\t\tlabel = \"blue:qss\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tath9k-leds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twlan5g {\n\t\t\tlabel = \"blue:wlan5g\";\n\t\t\tgpios = <&ath9k 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"Reset button\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tgpio-export {\n\t\tcompatible = \"gpio-export\";\n\n\t\tgpio_usb1_power {\n\t\t\tgpio-export,name = \"tp-link:power:usb1\";\n\t\t\tgpio-export,output = <1>;\n\t\t\tgpios = <&gpio 21 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tgpio_usb2_power {\n\t\t\tgpio-export,name = \"tp-link:power:usb2\";\n\t\t\tgpio-export,output = <1>;\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&pcie1 {\n\tstatus = \"okay\";\n\n\tath9k: wifi@0,0 {\n\t\tcompatible = \"pci168c,0033\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tnvmem-cells = <&macaddr_uboot_1fc00>;\n\t\tnvmem-cell-names = \"mac-address\";\n\t\tmac-address-increment = <(-2)>;\n\t\tqca,no-eeprom;\n\t\t#gpio-cells = <2>;\n\t\tgpio-controller;\n\t};\n};\n\n&usb_phy0 {\n\tstatus = \"okay\";\n};\n\n&usb0 {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\tstatus = \"okay\";\n\n\thub_port0: port@1 {\n\t\treg = <1>;\n\t\t#trigger-source-cells = <0>;\n\t};\n};\n\n&usb_phy1 {\n\tstatus = \"okay\";\n};\n\n&usb1 {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\tstatus = \"okay\";\n\n\thub_port1: port@1 {\n\t\treg = <1>;\n\t\t#trigger-source-cells = <0>;\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tuboot: partition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x020000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tcompatible = \"tplink,firmware\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x020000 0x7d0000>;\n\t\t\t};\n\n\t\t\tart: partition@7f0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0x7f0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\n\t\tqca,ar8327-initvals = <\n\t\t\t0x04 0x00080080 /* PORT0 PAD MODE CTRL */\n\t\t\t0x0c 0x07600000 /* PORT6 PAD MODE CTRL */\n\t\t\t0x50 0xc737c737 /* LED_CTRL0 */\n\t\t\t0x54 0x00000000 /* LED_CTRL1 */\n\t\t\t0x58 0x00000000 /* LED_CTRL2 */\n\t\t\t0x5c 0x0030c300 /* LED_CTRL3 */\n\t\t\t0x7c 0x0000007e /* PORT0_STATUS */\n\t\t\t0x94 0x0000007e /* PORT6 STATUS */\n\t\t>;\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tnvmem-cells = <&macaddr_uboot_1fc00>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <1>;\n\tphy-handle = <&phy0>;\n\tpll-data = <0x56000000 0x00000101 0x00001616>;\n\n\tgmac-config {\n\t\tdevice = <&gmac>;\n\t\trgmii-enabled = <1>;\n\t};\n};\n\n&eth1 {\n\tstatus = \"okay\";\n\n\tnvmem-cells = <&macaddr_uboot_1fc00>;\n\tnvmem-cell-names = \"mac-address\";\n\tpll-data = <0x03000101 0x00000101 0x00001616>;\n\n\tfixed-link {\n\t\tspeed = <1000>;\n\t\tfull-duplex;\n\t};\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n\tnvmem-cells = <&macaddr_uboot_1fc00>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <(-1)>;\n};\n\n&uboot {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_uboot_1fc00: macaddr@1fc00 {\n\t\treg = <0x1fc00 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9558_tplink_tl-wdr7500-v3.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9558_tplink_archer-c.dtsi\"\n\n/ {\n\tcompatible = \"tplink,tl-wdr7500-v3\", \"qca,qca9558\";\n\tmodel = \"TP-Link TL-WDR7500 v3\";\n\n\taliases {\n\t\tlabel-mac-device = &eth1;\n\t};\n};\n\n&keys {\n\trfkill {\n\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\tlinux,code = <KEY_RFKILL>;\n\t\tlinux,input-type = <EV_SW>;\n\t\tdebounce-interval = <60>;\n\t};\n};\n\n&leds {\n\twlan5g {\n\t\tlabel = \"green:wlan5g\";\n\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\tlinux,default-trigger = \"phy0tpt\";\n\t};\n};\n\n&mtdparts {\n\tuboot: partition@0 {\n\t\tlabel = \"u-boot\";\n\t\treg = <0x000000 0x020000>;\n\t\tread-only;\n\t};\n\n\tpartition@20000 {\n\t\tlabel = \"firmware\";\n\t\tcompatible = \"tplink,firmware\";\n\t\treg = <0x020000 0x7d0000>;\n\t};\n\n\tart: partition@7f0000 {\n\t\tlabel = \"art\";\n\t\treg = <0x7f0000 0x010000>;\n\t\tread-only;\n\t};\n};\n\n&eth0 {\n\tnvmem-cells = <&macaddr_uboot_1fc00>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <1>;\n};\n\n&eth1 {\n\tnvmem-cells = <&macaddr_uboot_1fc00>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wmac {\n\tmtd-cal-data = <&art 0x1000>;\n\n\tnvmem-cells = <&macaddr_uboot_1fc00>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&uboot {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_uboot_1fc00: macaddr@1fc00 {\n\t\treg = <0x1fc00 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9558_tplink_tl-wr1043nd-v2.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9558_tplink_tl-wr1043nd.dtsi\"\n\n/ {\n\tcompatible = \"tplink,tl-wr1043nd-v2\", \"qca,qca9558\";\n\tmodel = \"TP-Link TL-WR1043ND v2\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9558_tplink_tl-wr1043nd-v3.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9558_tplink_tl-wr1043nd.dtsi\"\n\n/ {\n\tcompatible = \"tplink,tl-wr1043nd-v3\", \"qca,qca9558\";\n\tmodel = \"TP-Link TL-WR1043ND v3\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9558_tplink_tl-wr1043nd.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca955x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\taliases {\n\t\tled-boot = &led_system;\n\t\tled-failsafe = &led_system;\n\t\tled-running = &led_system;\n\t\tled-upgrade = &led_system;\n\t\tlabel-mac-device = &wmac;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_system: system {\n\t\t\tlabel = \"green:system\";\n\t\t\tgpios = <&gpio 19 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\n\t\tusb {\n\t\t\tlabel = \"green:usb\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t\ttrigger-sources = <&hub_port0>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\n\t\twifi_green {\n\t\t\tlabel = \"green:wlan\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\twifi_wps {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"Reset button\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\twifi {\n\t\t\tlabel = \"RFKILL button\";\n\t\t\tlinux,code = <KEY_RFKILL>;\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tgpio-export {\n\t\tcompatible = \"gpio-export\";\n\t\t#size-cells = <0>;\n\n\t\tgpio_usb_power {\n\t\t\tgpio-export,name = \"tp-link:power:usb\";\n\t\t\tgpio-export,output = <1>;\n\t\t\tgpios = <&gpio 21 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&usb_phy0 {\n\tstatus = \"okay\";\n};\n\n&usb0 {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\tstatus = \"okay\";\n\n\thub_port0: port@1 {\n\t\treg = <1>;\n\t\t#trigger-source-cells = <0>;\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <33400000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tuboot: partition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x020000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tcompatible = \"tplink,firmware\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x020000 0x7d0000>;\n\t\t\t};\n\n\t\t\tart: partition@7f0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0x7f0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t\tqca,ar8327-initvals = <\n\t\t\t0x04 0x00080080 /* PORT0 PAD MODE CTRL */\n\t\t\t0x0c 0x07600000 /* PORT6 PAD MODE CTRL */\n\t\t\t0x10 0x81000080 /* POWER_ON_STRAP */\n\t\t\t0x50 0xcc35cc35 /* LED_CTRL0 */\n\t\t\t0x54 0xca35ca35 /* LED_CTRL1 */\n\t\t\t0x58 0xc935c935 /* LED_CTRL2 */\n\t\t\t0x5c 0x03ffff00 /* LED_CTRL3 */\n\t\t\t0x7c 0x0000007e /* PORT0_STATUS */\n\t\t\t0x94 0x0000007e /* PORT6 STATUS */\n\t\t>;\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tpll-data = <0x56000000 0x00000101 0x00001616>;\n\n\tnvmem-cells = <&macaddr_uboot_1fc00>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <1>;\n\tphy-handle = <&phy0>;\n};\n\n&eth1 {\n\tstatus = \"okay\";\n\n\tpll-data = <0x03000101 0x00000101 0x00001616>;\n\n\tnvmem-cells = <&macaddr_uboot_1fc00>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tfixed-link {\n\t\tspeed = <1000>;\n\t\tfull-duplex;\n\t};\n};\n\n&wmac {\n\tstatus = \"okay\";\n\tmtd-cal-data = <&art 0x1000>;\n\tnvmem-cells = <&macaddr_uboot_1fc00>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&uboot {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_uboot_1fc00: macaddr@1fc00 {\n\t\treg = <0x1fc00 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9558_tplink_tl-wr1045nd-v2.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9558_tplink_tl-wr1043nd.dtsi\"\n\n/ {\n\tcompatible = \"tplink,tl-wr1045nd-v2\", \"qca,qca9558\";\n\tmodel = \"TP-Link TL-WR1045ND v2\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9558_tplink_tl-wr941n-v7-cn.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca955x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"tplink,tl-wr941n-v7-cn\", \"qca,qca9558\";\n\tmodel = \"TP-Link TL-WR941N v7 (CN)\";\n\n\taliases {\n\t\tled-boot = &led_system;\n\t\tled-failsafe = &led_system;\n\t\tled-running = &led_system;\n\t\tled-upgrade = &led_system;\n\t\tlabel-mac-device = &eth0;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_system: system {\n\t\t\tlabel = \"green:system\";\n\t\t\tgpios = <&gpio 19 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\twlan {\n\t\t\tlabel = \"green:wlan\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\tqss {\n\t\t\tlabel = \"green:qss\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"qss\";\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tuboot: partition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x020000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tcompatible = \"tplink,firmware\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x020000 0x3d0000>;\n\t\t\t};\n\n\t\t\tart: partition@7f0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0x3f0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tswitch0@1f {\n\t\tcompatible = \"qca,ar8236\";\n\t\treg = <0x1f>;\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\tphy-mode = \"mii\";\n\tnvmem-cells = <&macaddr_uboot_1fc00>;\n\tnvmem-cell-names = \"mac-address\";\n\tfixed-link {\n\t\tspeed = <100>;\n\t\tfull-duplex;\n\t};\n};\n\n&wmac {\n\tstatus = \"okay\";\n\tmtd-cal-data = <&art 0x1000>;\n\tnvmem-cells = <&macaddr_uboot_1fc00>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&uboot {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_uboot_1fc00: macaddr@1fc00 {\n\t\treg = <0x1fc00 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9558_trendnet_tew-823dru.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca955x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"trendnet,tew-823dru\", \"qca,qca9558\";\n\tmodel = \"TRENDNET TEW-823DRU\";\n\n\taliases {\n\t\tled-boot = &led_power_green;\n\t\tled-failsafe = &led_power_green;\n\t\tled-running = &led_power_green;\n\t\tled-upgrade = &led_power_green;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tpower_orange {\n\t\t\tlabel = \"orange:power\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_power_green: power_green {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 19 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tplanet_green {\n\t\t\tlabel = \"green:planet\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tplanet_orange {\n\t\t\tlabel = \"orange:planet\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"Reset button\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"WPS button\";\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n};\n\n&pcie0 {\n\tstatus = \"okay\";\n};\n\n&pcie1 {\n\tstatus = \"okay\";\n};\n\n&usb_phy0 {\n\tstatus = \"okay\";\n};\n\n&usb0 {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\tstatus = \"okay\";\n\n\thub_port0: port@1 {\n\t\treg = <1>;\n\t\t#trigger-source-cells = <0>;\n\t};\n};\n\n&usb_phy1 {\n\tstatus = \"okay\";\n};\n\n&usb1 {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\tstatus = \"okay\";\n\n\thub_port1: port@1 {\n\t\treg = <1>;\n\t\t#trigger-source-cells = <0>;\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x030000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"nvram\";\n\t\t\t\treg = <0x030000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x040000 0xef0000>;\n\t\t\t};\n\n\t\t\tpartition@f30000 {\n\t\t\t\tlabel = \"lang\";\n\t\t\t\treg = <0xf30000 0x030000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@f60000 {\n\t\t\t\tlabel = \"my-dlink\";\n\t\t\t\treg = <0xf60000 0x080000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@fe0000 {\n\t\t\t\tlabel = \"mac\";\n\t\t\t\treg = <0xfe0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tart: partition@ff0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0xff0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t\tqca,ar8327-initvals = <\n\t\t\t0x04 0x00080080 /* PORT0 PAD MODE CTRL */\n\t\t\t0x0c 0x07600000 /* PORT6 PAD MODE CTRL */\n\t\t\t0x10 0x81000080 /* POWER_ON_STRAP */\n\t\t\t0x7c 0x0000007e /* PORT0_STATUS */\n\t\t\t0x94 0x0000007e /* PORT6 STATUS */\n\t\t>;\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tphy-handle = <&phy0>;\n\tpll-data = <0x56000000 0x00000101 0x00001616>;\n\n\tgmac-config {\n\t\tdevice = <&gmac>;\n\t\trgmii-enabled = <1>;\n\t};\n};\n\n&eth1 {\n\tstatus = \"okay\";\n\n\tpll-data = <0x03000101 0x00000101 0x00001616>;\n\n\tfixed-link {\n\t\tspeed = <1000>;\n\t\tfull-duplex;\n\t};\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9558_ubnt_nanobeam-ac-xc.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-only\n/*\n * Device Tree file for Ubiquiti Nanobeam NBE-5AC-19 (XC)\n *\n * Copyright (C) 2022 Daniel González Cabanelas <dgcbueu@gmail.com>\n * based on device tree from qca9558_ubnt_powerbeam-5ac-500.dts\n */\n \n#include \"qca955x_ubnt_xc.dtsi\"\n\n/ {\n\tcompatible = \"ubnt,nanobeam-ac-xc\", \"ubnt,xc\", \"qca,qca9558\";\n\tmodel = \"Ubiquiti NanoBeam AC Gen1 (XC)\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"Reset button\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 19 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tled_spi {\n\t\tcompatible = \"spi-gpio\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tsck-gpios  = <&gpio 0 GPIO_ACTIVE_HIGH>;\n\t\tmosi-gpios = <&gpio 1 GPIO_ACTIVE_HIGH>;\n\t\tcs-gpios   = <&gpio 3 GPIO_ACTIVE_HIGH>;\n\t\tnum-chipselects = <1>;\n\n\t\tled_gpio: led_gpio@0 {\n\t\t\tcompatible = \"fairchild,74hc595\";\n\t\t\treg = <0>;\n\t\t\tgpio-controller;\n\t\t\t#gpio-cells = <2>;\n\t\t\tregisters-number = <1>;\n\t\t\tspi-max-frequency = <10000000>;\n\t\t\tenable-gpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\trssi0 {\n\t\t\tlabel = \"blue:rssi0\";\n\t\t\tgpios = <&led_gpio 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\trssi1 {\n\t\t\tlabel = \"blue:rssi1\";\n\t\t\tgpios = <&led_gpio 1 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\trssi2 {\n\t\t\tlabel = \"blue:rssi2\";\n\t\t\tgpios = <&led_gpio 2 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\trssi3 {\n\t\t\tlabel = \"blue:rssi3\";\n\t\t\tgpios = <&led_gpio 3 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tled_power: power {\n\t\t\tlabel = \"blue:power\";\n\t\t\tgpios = <&led_gpio 4 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy-mask = <4>;\n\tphy4: ethernet-phy@4 {\n\t\tphy-mode = \"sgmii\";\n\t\treg = <4>;\n\t\tat803x-override-sgmii-link-check;\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tpll-reg = <0 0x48 0>;\n\tpll-data = <0x03000000 0x00000101 0x00001313>;\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n\tphy-mode = \"sgmii\";\n\tphy-handle = <&phy4>;\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9558_ubnt_powerbeam-5ac-500.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-only\n\n#include \"qca955x_ubnt_xc.dtsi\"\n\n/ {\n\tcompatible = \"ubnt,powerbeam-5ac-500\", \"ubnt,xc\", \"qca,qca9558\";\n\tmodel = \"Ubiquiti PowerBeam 5AC 500\";\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"Reset button\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 19 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy-mask = <4>;\n\tphy4: ethernet-phy@4 {\n\t\tphy-mode = \"sgmii\";\n\t\treg = <4>;\n\t\tat803x-override-sgmii-link-check;\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n\tphy-mode = \"sgmii\";\n\tphy-handle = <&phy4>;\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9558_ubnt_rocket-5ac-lite.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-only\n\n#include \"qca955x_ubnt_xc.dtsi\"\n\n/ {\n\tcompatible = \"ubnt,rocket-5ac-lite\", \"ubnt,xc\", \"qca,qca9558\";\n\tmodel = \"Ubiquiti Rocket 5AC Lite\";\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"Reset button\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 19 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy-mask = <4>;\n\tphy4: ethernet-phy@4 {\n\t\tphy-mode = \"sgmii\";\n\t\treg = <4>;\n\t\tat803x-override-sgmii-link-check;\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n\tphy-mode = \"sgmii\";\n\tphy-handle = <&phy4>;\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9558_zyxel_emg2926_q10a.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9558_zyxel_nbg6716.dts\"\n\n/ {\n\tcompatible = \"zyxel,emg2926-q10a\", \"zyxel,nbg6716\", \"qca,qca9558\";\n\tmodel = \"ZyXEL EMG2926-Q10A\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9558_zyxel_nbg6716.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca955x_zyxel_nbg6x16.dtsi\"\n\n/ {\n\tcompatible = \"zyxel,nbg6716\", \"qca,qca9558\";\n\tmodel = \"ZyXEL NBG6716\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"white:power\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tinternet {\n\t\t\tlabel = \"white:internet\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tusb1 {\n\t\t\tlabel = \"white:usb1\";\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t\ttrigger-sources = <&hub_port1>;\n\t\t};\n\n\t\tusb2 {\n\t\t\tlabel = \"white:usb2\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t\ttrigger-sources = <&hub_port0>;\n\t\t};\n\n\t\twifi2g {\n\t\t\tlabel = \"white:wifi2g\";\n\t\t\tgpios = <&gpio 19 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\n\t\twifi5g {\n\t\t\tlabel = \"white:wifi5g\";\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"white:wps\";\n\t\t\tgpios = <&gpio 21 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&keys {\n\tusb1 {\n\t\tlabel = \"USB1 eject button\";\n\t\tlinux,code = <BTN_1>;\n\t\tgpios = <&gpio 0 GPIO_ACTIVE_LOW>;\n\t\tdebounce-interval = <60>;\n\t};\n\n\tusb2 {\n\t\tlabel = \"USB2 eject button\";\n\t\tlinux,code = <BTN_2>;\n\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\tdebounce-interval = <60>;\n\t};\n};\n\n&gpio_usb_power {\n\tline-name = \"nbg6716:power:usb\";\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tuboot: partition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tuboot_env: partition@40000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x040000 0x010000>;\n\t\t\t};\n\n\t\t\tart: partition@50000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0x050000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@60000 {\n\t\t\t\tlabel = \"nbu\";\n\t\t\t\treg = <0x060000 0xfa0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&nand {\n\tstatus = \"okay\";\n\n\tpartitions {\n\t\tcompatible = \"fixed-partitions\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"zyxel_rfsd\";\n\t\t\treg = <0x0 0x200000>;\n\t\t};\n\n\t\tpartition@200000 {\n\t\t\tlabel = \"romd\";\n\t\t\treg = <0x200000 0x200000>;\n\t\t};\n\n\t\tpartition@400000 {\n\t\t\tlabel = \"header\";\n\t\t\treg = <0x400000 0x100000>;\n\t\t};\n\n\t\tfirmware@500000 {\n\t\t\tlabel = \"firmware\";\n\t\t\treg = <0x500000 0x7b00000>;\n\t\t};\n\n\t\tpartition@500000 {\n\t\t\tlabel = \"kernel\";\n\t\t\treg = <0x500000 0x400000>;\n\t\t};\n\n\t\tpartition@900000 {\n\t\t\tlabel = \"ubi\";\n\t\t\treg = <0x900000 0x7700000>;\n\t\t};\n\t};\n};\n\n&pcie1 {\n\tstatus = \"okay\";\n\n\twifi@0,0 {\n\t\tcompatible = \"qcom,ath10k\";\n\t\treg = <0 0 0 0 0>;\n\t\tqcom,ath10k-calibration-variant = \"ZyXEL-NBG6716\";\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca955x.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ath79.dtsi\"\n\n/ {\n\tcompatible = \"qca,qca9550\";\n\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200n8\";\n\t};\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu@0 {\n\t\t\tdevice_type = \"cpu\";\n\t\t\tcompatible = \"mips,mips74Kc\";\n\t\t\tclocks = <&pll ATH79_CLK_CPU>;\n\t\t\treg = <0>;\n\t\t};\n\t};\n\n\textosc: ref {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-output-names = \"ref\";\n\t\tclock-frequency = <40000000>;\n\t};\n\n\tahb {\n\t\tapb {\n\t\t\tddr_ctrl: memory-controller@18000000 {\n\t\t\t\tcompatible = \"qca,qca9550-ddr-controller\",\n\t\t\t\t\t\t\"qca,ar7240-ddr-controller\";\n\t\t\t\treg = <0x18000000 0x100>;\n\n\t\t\t\t#qca,ddr-wb-channel-cells = <1>;\n\t\t\t};\n\n\t\t\tuart: uart@18020000 {\n\t\t\t\tcompatible = \"ns16550a\";\n\t\t\t\treg = <0x18020000 0x20>;\n\n\t\t\t\tinterrupts = <3>;\n\n\t\t\t\tclocks = <&pll ATH79_CLK_REF>;\n\t\t\t\tclock-names = \"uart\";\n\n\t\t\t\treg-io-width = <4>;\n\t\t\t\treg-shift = <2>;\n\t\t\t\tno-loopback-test;\n\t\t\t};\n\n\t\t\tusb_phy0: usb-phy0@18030000 {\n\t\t\t\tcompatible =\"qca,qca9550-usb-phy\", \"qca,ar7200-usb-phy\";\n\t\t\t\treg = <0x18030000 4>, <0x18030004 4>;\n\n\t\t\t\treset-names = \"usb-phy\", \"usb-suspend-override\";\n\t\t\t\tresets = <&rst 4>, <&rst 3>;\n\n\t\t\t\t#phy-cells = <0>;\n\n\t\t\t\tstatus = \"disabled\";\n\t\t\t};\n\n\t\t\tusb_phy1: usb-phy1@18030010 {\n\t\t\t\tcompatible = \"qca,qca9550-usb-phy\", \"qca,ar7200-usb-phy\";\n\t\t\t\treg = <0x18030010 4>, <0x18030014 4>;\n\n\t\t\t\treset-names = \"usb-phy\", \"usb-suspend-override\";\n\t\t\t\tresets = <&rst2 4>, <&rst2 3>;\n\n\t\t\t\t#phy-cells = <0>;\n\n\t\t\t\tstatus = \"disabled\";\n\t\t\t};\n\n\t\t\tgpio: gpio@18040000 {\n\t\t\t\tcompatible = \"qca,qca9550-gpio\",\n\t\t\t\t\t\t\"qca,ar9340-gpio\";\n\t\t\t\treg = <0x18040000 0x28>;\n\n\t\t\t\tinterrupts = <2>;\n\t\t\t\tngpios = <24>;\n\n\t\t\t\tgpio-controller;\n\t\t\t\t#gpio-cells = <2>;\n\n\t\t\t\tinterrupt-controller;\n\t\t\t\t#interrupt-cells = <2>;\n\t\t\t};\n\n\t\t\tpinmux: pinmux@1804002c {\n\t\t\t\tcompatible = \"pinctrl-single\";\n\n\t\t\t\treg = <0x1804002c 0x44>;\n\n\t\t\t\t#size-cells = <0>;\n\n\t\t\t\tpinctrl-single,bit-per-mux;\n\t\t\t\tpinctrl-single,register-width = <32>;\n\t\t\t\tpinctrl-single,function-mask = <0x1>;\n\t\t\t\t#pinctrl-cells = <2>;\n\n\t\t\t\tjtag_disable_pins: pinmux_jtag_disable_pins {\n\t\t\t\t\tpinctrl-single,bits = <0x40 0x2  0x2>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tpll: pll-controller@18050000 {\n\t\t\t\tcompatible = \"qca,qca9550-pll\", \"syscon\";\n\t\t\t\treg = <0x18050000 0x50>;\n\n\t\t\t\t#clock-cells = <1>;\n\t\t\t\tclock-output-names = \"cpu\", \"ddr\", \"ahb\";\n\n\t\t\t\tclocks = <&extosc>;\n\t\t\t};\n\n\t\t\twdt: wdt@18060008 {\n\t\t\t\tcompatible = \"qca,ar7130-wdt\";\n\t\t\t\treg = <0x18060008 0x8>;\n\n\t\t\t\tinterrupts = <4>;\n\n\t\t\t\tclocks = <&pll ATH79_CLK_AHB>;\n\t\t\t\tclock-names = \"wdt\";\n\t\t\t};\n\n\t\t\trst: reset-controller@1806001c {\n\t\t\t\tcompatible = \"qca,qca9550-reset\",\n\t\t\t\t\t\t\"qca,ar7100-reset\";\n\t\t\t\treg = <0x1806001c 0x4>;\n\n\t\t\t\t#reset-cells = <1>;\n\t\t\t\tinterrupt-parent = <&cpuintc>;\n\n\t\t\t\tintc2: interrupt-controller2 {\n\t\t\t\t\tcompatible = \"qca,ar9340-intc\";\n\n\t\t\t\t\tinterrupt-parent = <&cpuintc>;\n\t\t\t\t\tinterrupts = <2>;\n\n\t\t\t\t\tinterrupt-controller;\n\t\t\t\t\t#interrupt-cells = <1>;\n\n\t\t\t\t\tqca,int-status-addr = <0xac>;\n\t\t\t\t\tqca,pending-bits = <0xf>,\t/* wmac */\n\t\t\t\t\t\t\t<0x1f0>;\t/* pcie rc 0 */\n\t\t\t\t};\n\n\t\t\t\tintc3: interrupt-controller3 {\n\t\t\t\t\tcompatible = \"qca,ar9340-intc\";\n\n\t\t\t\t\tinterrupt-parent = <&cpuintc>;\n\t\t\t\t\tinterrupts = <3>;\n\n\t\t\t\t\tinterrupt-controller;\n\t\t\t\t\t#interrupt-cells = <1>;\n\n\t\t\t\t\tqca,int-status-addr = <0xac>;\n\t\t\t\t\tqca,pending-bits = <0x1f000>,\t\t/* pcie rc 1 */\n\t\t\t\t\t\t\t    <0x1000000>,\t/* usb1 */\n\t\t\t\t\t\t\t    <0x10000000>;\t/* usb2 */\n\t\t\t\t};\n\t\t\t};\n\n\t\t\trst2: reset-controller@180600c0 {\n\t\t\t\tcompatible = \"qca,qca9550-reset\",\n\t\t\t\t\t\t\"qca,ar7100-reset\",\n\t\t\t\t\t\t \"simple-bus\";\n\t\t\t\treg = <0x180600c0 0x4>;\n\n\t\t\t\t#reset-cells = <1>;\n\t\t\t};\n\t\t};\n\n\t\tgmac: gmac@18070000 {\n\t\t\tcompatible = \"qca,qca9550-gmac\";\n\t\t\treg = <0x18070000 0x58>;\n\t\t};\n\n\t\tpcie0: pcie-controller@180c0000 {\n\t\t\tcompatible = \"qcom,qca9550-pci\", \"qcom,ar7240-pci\";\n\t\t\t#address-cells = <3>;\n\t\t\t#size-cells = <2>;\n\t\t\tbus-range = <0x0 0x0>;\n\t\t\treg = <0x180c0000 0x1000>, /* CRP */\n\t\t\t      <0x180f0000 0x100>,  /* CTRL */\n\t\t\t      <0x14000000 0x1000>; /* CFG */\n\t\t\treg-names = \"crp_base\", \"ctrl_base\", \"cfg_base\";\n\t\t\tranges = <0x2000000 0 0x10000000 0x10000000 0 0x02000000\t/* pci memory */\n\t\t\t\t  0x1000000 0 0x00000000 0x0000000 0 0x000001>;\t\t/* io space */\n\t\t\tinterrupt-parent = <&intc2>;\n\t\t\tinterrupts = <1>;\n\n\t\t\tdevice_type = \"pci\";\n\n\t\t\tresets = <&rst 6>, <&rst 7>;\n\t\t\treset-names = \"hc\", \"phy\";\n\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <1>;\n\n\t\t\tinterrupt-map-mask = <0 0 0 1>;\n\t\t\tinterrupt-map = <0 0 0 0 &pcie0 0>;\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\twmac: wmac@18100000 {\n\t\t\tcompatible = \"qca,qca9550-wmac\";\n\t\t\treg = <0x18100000 0x10000>;\n\n\t\t\tinterrupt-parent = <&intc2>;\n\t\t\tinterrupts = <0>;\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tpcie1: pcie-controller@18250000 {\n\t\t\tcompatible = \"qcom,qca9550-pci\", \"qcom,ar7240-pci\";\n\t\t\t#address-cells = <3>;\n\t\t\t#size-cells = <2>;\n\t\t\tbus-range = <0x0 0x0>;\n\t\t\treg = <0x18250000 0x1000>, /* CRP */\n\t\t\t      <0x18280000 0x100>,  /* CTRL */\n\t\t\t      <0x16000000 0x1000>; /* CFG */\n\t\t\treg-names = \"crp_base\", \"ctrl_base\", \"cfg_base\";\n\t\t\tranges = <0x2000000 0 0x12000000 0x12000000 0 0x02000000\t/* pci memory */\n\t\t\t\t  0x1000000 0 0x00000000 0x0000001 0 0x000001>;\t\t/* io space */\n\t\t\tinterrupt-parent = <&intc3>;\n\t\t\tinterrupts = <0>;\n\n\t\t\tdevice_type = \"pci\";\n\n\t\t\tresets = <&rst2 6>, <&rst2 7>;\n\t\t\treset-names = \"hc\", \"phy\";\n\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <1>;\n\n\t\t\tinterrupt-map-mask = <0 0 0 1>;\n\t\t\tinterrupt-map = <0 0 0 0 &pcie1 0>;\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tusb0: usb@1b000000 {\n\t\t\tcompatible = \"generic-ehci\";\n\t\t\treg = <0x1b000000 0x1fc>;\n\n\t\t\tinterrupt-parent = <&intc3>;\n\t\t\tinterrupts = <1>;\n\t\t\tresets = <&rst 5>;\n\t\t\treset-names = \"usb-host\";\n\n\t\t\thas-transaction-translator;\n\t\t\tcaps-offset = <0x100>;\n\n\t\t\tphy-names = \"usb-phy0\";\n\t\t\tphys = <&usb_phy0>;\n\n\t\t\tstatus = \"disabled\";\n\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tusb1: usb@1b400000 {\n\t\t\tcompatible = \"generic-ehci\";\n\t\t\treg = <0x1b400000 0x1fc>;\n\n\t\t\tinterrupt-parent = <&intc3>;\n\t\t\tinterrupts = <2>;\n\t\t\tresets = <&rst2 5>;\n\t\t\treset-names = \"usb-host\";\n\n\t\t\thas-transaction-translator;\n\t\t\tcaps-offset = <0x100>;\n\n\t\t\tphy-names = \"usb-phy1\";\n\t\t\tphys = <&usb_phy1>;\n\n\t\t\tstatus = \"disabled\";\n\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tnand: nand@1b800200 {\n\t\t\tcompatible = \"qca,ar934x-nand\";\n\t\t\treg = <0x1b800200 0xb8>;\n\n\t\t\tinterrupts = <21>;\n\t\t\tinterrupt-parent = <&miscintc>;\n\n\t\t\tresets = <&rst 14>;\n\t\t\treset-names = \"nand\";\n\n\t\t\tnand-ecc-mode = \"hw\";\n\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tspi: spi@1f000000 {\n\t\t\tcompatible = \"qca,ar934x-spi\";\n\t\t\treg = <0x1f000000 0x1c>;\n\n\t\t\tclocks = <&pll ATH79_CLK_AHB>;\n\n\t\t\tstatus = \"disabled\";\n\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\t};\n};\n\n&mdio0 {\n\tcompatible = \"qca,ar9340-mdio\";\n};\n\n&eth0 {\n\tcompatible = \"qca,qca9550-eth\", \"syscon\";\n\n\tpll-reg = <0 0x28 0>;\n\tpll-handle = <&pll>;\n\n\tpll-data = <0x16000000 0x00000101 0x00001616>;\n\tphy-mode = \"rgmii\";\n\n\tresets = <&rst 9>, <&rst 22>;\n\treset-names = \"mac\", \"mdio\";\n};\n\n&mdio1 {\n\tcompatible = \"qca,ar9340-mdio\";\n};\n\n&eth1 {\n\tcompatible = \"qca,qca9550-eth\", \"syscon\";\n\n\tpll-reg = <0 0x48 0>;\n\tpll-handle = <&pll>;\n\n\tpll-data = <0x16000000 0x00000101 0x00001616>;\n\tphy-mode = \"sgmii\";\n\n\tresets = <&rst 13>, <&rst 23>;\n\treset-names = \"mac\", \"mdio\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca955x_dlink_dap-2xxx.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca955x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <50000000>;\n\n\t\tpartitions: partitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x40000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"bdcfg\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tlabel = \"rgdb\";\n\t\t\t\treg = <0x50000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@60000 {\n\t\t\t\tlabel = \"unused\";\n\t\t\t\treg = <0x60000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca955x_engenius_ecb1xxx.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca955x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tdebounce-interval = <60>;\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"amber:power\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\twifi2g {\n\t\t\tlabel = \"blue:wifi2g\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\n\t\twifi5g {\n\t\t\tlabel = \"blue:wifi5g\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <40000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x040000 0x010000>;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x050000 0xf50000>;\n\t\t\t};\n\n\t\t\tpartition@fa0000 {\n\t\t\t\tlabel = \"userconfig\";\n\t\t\t\treg = <0xfa0000 0x050000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@ff0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0xff0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy5: ethernet-phy@5 {\n\t\treg = <5>;\n\t\teee-broken-100tx;\n\t\teee-broken-1000t;\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tphy-handle = <&phy5>;\n\tphy-mode = \"rgmii-id\";\n\n\tpll-data = <0x82000000 0x80000101 0x80001313>;\n\n\tgmac-config {\n\t\tdevice = <&gmac>;\n\t\trgmii-enabled = <1>;\n\t};\n};\n\n&pcie0 {\n\tstatus = \"okay\";\n\n\twifi@0,0,0 {\n\t\tcompatible = \"qcom,ath10k\";\n\t\treg = <0x0 0 0 0 0>;\n\t\tqca,no-eeprom;\n\t};\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tqca,no-eeprom;\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca955x_senao_loader.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca955x.dtsi\"\n\n#include <dt-bindings/mtd/partitions/uimage.h>\n\n/ {\n\tvirtual_flash {\n\t\tcompatible = \"mtd-concat\";\n\n\t\tdevices = <&fwconcat0 &fwconcat1>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tcompatible = \"openwrt,uimage\", \"denx,uimage\";\n\t\t\t\topenwrt,ih-magic = <0x73714f4b>;\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x0 0x0>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pcie0 {\n\tstatus = \"okay\";\n\n\twifi@0,0,0 {\n\t\tcompatible = \"qcom,ath10k\";\n\t\treg = <0x0 0 0 0 0>;\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <40000000>;\n\n\t\tpartitions: partitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x040000 0x010000>;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tlabel = \"custom\";\n\t\t\t\treg = <0x050000 0x050000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@a0000 {\n\t\t\t\tlabel = \"loader\";\n\t\t\t\treg = <0x0a0000 0x010000>;\n\t\t\t};\n\n\t\t\tfwconcat1: partition@b0000 {\n\t\t\t\tlabel = \"fwconcat1\";\n\t\t\t\treg = <0x0b0000 0x170000>;\n\t\t\t};\n\n\t\t\tfwconcat0: partition@220000 {\n\t\t\t\tlabel = \"fwconcat0\";\n\t\t\t\treg = <0x220000 0xb50000>;\n\t\t\t};\n\n\t\t\tpartition@d70000 {\n\t\t\t\tlabel = \"failsafe\";\n\t\t\t\treg = <0xd70000 0x280000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\t/* additional partitions in device DTS files */\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca955x_ubnt_xc.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-only\n\n#include \"qca955x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n&pcie0 {\n\tstatus = \"okay\";\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x040000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x050000 0xf60000>;\n\t\t\t};\n\n\t\t\tpartition@fb0000 {\n\t\t\t\tlabel = \"cfg\";\n\t\t\t\treg = <0xfb0000 0x040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tart: partition@ff0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0xff0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca955x_zyxel_nbg6x16.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca955x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tkeys: keys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\twifi {\n\t\t\tlabel = \"WiFi on/off button\";\n\t\t\tlinux,code = <KEY_RFKILL>;\n\t\t\tlinux,input-type = <EV_SW>;\n\t\t\tgpios = <&gpio 1 GPIO_ACTIVE_HIGH>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"WPS button\";\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"Reset button\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n};\n\n&gpio {\n\tgpio_usb_power: usb_power {\n\t\tgpio-hog;\n\t\tgpios = <16 0>;\n\t\toutput-high;\n\t};\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy17: ethernet-phy@11 {\n\t\treg = <0x11>;\n\t\tphy-mode = \"rgmii-id\";\n\t};\n\n\tswitch0@1f {\n\t\tcompatible = \"qca,ar8327\";\n\t\treg = <0x1f>;\n\t\tqca,ar8327-initvals = <\n\t\t\t0x04 0x87600000 /* PORT0 PAD MODE CTRL */\n\t\t\t0x0c 0x00080080 /* PORT6 PAD MODE CTRL */\n\t\t\t0x10 0x81000080 /* POWER_ON_STRAP */\n\t\t\t0x50 0xffb7ffb7 /* LED_CTRL0 */\n\t\t\t0x54 0xffb7ffb7 /* LED_CTRL1 */\n\t\t\t0x58 0xffb7ffb7 /* LED_CTRL2 */\n\t\t\t0x5c 0x03ffff00 /* LED_CTRL3 */\n\t\t\t0x7c 0x0000007e /* PORT0_STATUS */\n\t\t\t0x94 0x0000007e /* PORT6 STATUS */\n\t\t\t>;\n\t};\n};\n\n&mdio1 {\n\tstatus = \"okay\";\n\n\tphy1: ethernet-phy@1 {\n\t\treg = <1>;\n\t\tphy-mode = \"sgmii\";\n\t};\n};\n\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tpll-data = <0xa6000000 0x00000101 0x00001616>;\n\tphy-handle = <&phy17>;\n\n\tfixed-link {\n\t\tspeed = <1000>;\n\t\tfull-duplex;\n\t};\n};\n\n&eth1 {\n\tstatus = \"okay\";\n\n\tpll-data = <0x03000101 0x00000101 0x00001616>;\n\tphy-handle = <&phy1>;\n\n\tfixed-link {\n\t\tspeed = <1000>;\n\t\tfull-duplex;\n\t};\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n};\n\n&usb_phy0 {\n\tstatus = \"okay\";\n};\n\n&usb_phy1 {\n\tstatus = \"okay\";\n};\n\n&usb0 {\n\tstatus = \"okay\";\n\n\thub_port0: port@1 {\n\t\treg = <1>;\n\t\t#trigger-source-cells = <0>;\n\t};\n\n};\n\n&usb1 {\n\tstatus = \"okay\";\n\n\thub_port1: port@1 {\n\t\treg = <1>;\n\t\t#trigger-source-cells = <0>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9561_avm_fritz4020.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca956x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"avm,fritz4020\", \"qca,qca9560\";\n\tmodel = \"AVM FRITZ!Box 4020\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_info_red;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_info_red;\n\t};\n\n\tled_spi {\n\t\tcompatible = \"spi-gpio\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tsck-gpios = <&gpio 20 GPIO_ACTIVE_HIGH>;\n\t\tmosi-gpios = <&gpio 19 GPIO_ACTIVE_HIGH>;\n\t\tnum-chipselects = <0>;\n\n\t\tled_gpio: led_gpio@0 {\n\t\t\tcompatible = \"fairchild,74hc595\";\n\t\t\treg = <0>;\n\t\t\tgpio-controller;\n\t\t\t#gpio-cells = <2>;\n\t\t\tregisters-number = <1>;\n\t\t\tspi-max-frequency = <10000000>;\n\n\t\t\tgpio_latch_bit {\n\t\t\t\tgpio-hog;\n\t\t\t\tgpios = <7 GPIO_ACTIVE_HIGH>;\n\t\t\t\toutput-high;\n\t\t\t\tline-name = \"gpio-latch-bit\";\n\t\t\t};\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&led_gpio 2 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\twlan {\n\t\t\tlabel = \"green:wlan\";\n\t\t\tgpios = <&led_gpio 3 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\tlan {\n\t\t\tlabel = \"green:lan\";\n\t\t\tgpios = <&led_gpio 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twan {\n\t\t\tlabel = \"green:wan\";\n\t\t\tgpios = <&led_gpio 4 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tinfo {\n\t\t\tlabel = \"green:info\";\n\t\t\tgpios = <&led_gpio 6 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_info_red: info_red {\n\t\t\tlabel = \"red:info\";\n\t\t\tgpios = <&led_gpio 1 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\twps {\n\t\t\tlabel = \"WPS button\";\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tgpios = <&gpio 2 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan {\n\t\t\tlabel = \"WLAN button\";\n\t\t\tlinux,code = <KEY_RFKILL>;\n\t\t\tgpios = <&gpio 21 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"urlader\";\n\t\t\t\treg = <0x000000 0x020000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@1 {\n\t\t\t\tcompatible = \"avm,eva-firmware\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x020000 0xee0000>;\n\t\t\t};\n\n\t\t\tpartition@2 {\n\t\t\t\tlabel = \"tffs (1)\";\n\t\t\t\treg = <0xf00000 0x080000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@3 {\n\t\t\t\tlabel = \"tffs (2)\";\n\t\t\t\treg = <0xf80000 0x080000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tphy-handle = <&swphy0>;\n\n\tgmac-config {\n\t\tdevice = <&gmac>;\n\n\t\tswitch-phy-addr-swap = <1>;\n\t\tswitch-phy-swap = <1>;\n\t};\n};\n\n&eth1 {\n\tstatus = \"okay\";\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tqca,no-eeprom;\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9561_nec_wf1200cr.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca956x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"NEC Aterm WF1200CR\";\n\tcompatible = \"nec,wf1200cr\", \"qca,qca9561\";\n\n\taliases {\n\t\tled-boot = &led_power_green;\n\t\tled-failsafe = &led_power_red;\n\t\tled-running = &led_power_green;\n\t\tled-upgrade = &led_power_green;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\t/* other LEDs are connected to ath10k (QCA9888) gpiochip */\n\n\t\tled_power_green: power_green {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_power_red: power_red {\n\t\t\tlabel = \"red:power\";\n\t\t\tgpios = <&gpio 21 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 1 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\trouter {\n\t\t\tlabel = \"rt\";\n\t\t\tgpios = <&gpio 2 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_0>;\n\t\t\tlinux,input-type = <EV_SW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"devdata\";\n\t\t\t\treg = <0x040000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tlabel = \"devconf\";\n\t\t\t\treg = <0x050000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@60000 {\n\t\t\t\tlabel = \"misc\";\n\t\t\t\treg = <0x060000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@70000 {\n\t\t\t\tcompatible = \"seama\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x070000 0x780000>;\n\t\t\t};\n\n\t\t\tpartition@7f0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0x7f0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tpll-data = <0x03000101 0x00000101 0x00001919>;\n\n\tphy-handle = <&swphy0>;\n\n\tgmac-config {\n\t\tdevice = <&gmac>;\n\n\t\tswitch-phy-swap = <1>;\n\t\tswitch-phy-addr-swap = <0>;\n\t};\n};\n\n&eth1 {\n\tstatus = \"okay\";\n\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinmux_swled_enable_pins>;\n};\n\n&gpio {\n\tswitch_leds {\n\t\tgpio-hog;\n\t\tgpios = <14 GPIO_ACTIVE_HIGH>,\t/* WAN */\n\t\t\t<19 GPIO_ACTIVE_HIGH>;\t/* LAN */\n\t\toutput-high;\n\t\tline-name = \"led:wan-lan\";\n\t};\n};\n\n&pinmux {\n\tpinmux_swled_enable_pins: swled_enable_pins {\n\t\tpinctrl-single,bits =\n\t\t\t<0xc 0x240000 0xff0000>,\t/* WAN */\n\t\t\t<0x10 0x10000000 0xff000000>;\t/* LAN */\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n\n\twifi@0,0 {\n\t\tcompatible = \"qcom,ath10k\";\n\t\treg = <0x0000 0 0 0 0>;\n\t};\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tqca,no-eeprom;\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9561_tplink_archer-c25-v1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca956x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"tplink,archer-c25-v1\", \"qca,qca9561\";\n\tmodel = \"TP-Link Archer C25 v1\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t\tlabel-mac-device = &eth0;\n\t};\n\n\tled_spi {\n\t\tcompatible = \"spi-gpio\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tsck-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;\n\t\tmosi-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;\n\t\tcs-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\t\tnum-chipselects = <1>;\n\n\t\tled_gpio: led_gpio@0 {\n\t\t\tcompatible = \"fairchild,74hc595\";\n\t\t\treg = <0>;\n\t\t\tgpio-controller;\n\t\t\t#gpio-cells = <2>;\n\t\t\tregisters-number = <1>;\n\t\t\tspi-max-frequency = <10000000>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\twifi {\n\t\t\tlabel = \"WiFi button\";\n\t\t\tlinux,code = <KEY_RFKILL>;\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"Reset button\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 1 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&gpio 2 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan2g {\n\t\t\tlabel = \"green:wlan2g\";\n\t\t\tgpios = <&led_gpio 6 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\n\t\twlan5g {\n\t\t\tlabel = \"green:wlan5g\";\n\t\t\tgpios = <&led_gpio 7 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\twan_green {\n\t\t\tlabel = \"green:wan\";\n\t\t\tgpios = <&led_gpio 5 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twan_amber {\n\t\t\tlabel = \"amber:wan\";\n\t\t\tgpios = <&led_gpio 4 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan1 {\n\t\t\tlabel = \"green:lan1\";\n\t\t\tgpios = <&led_gpio 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan2 {\n\t\t\tlabel = \"green:lan2\";\n\t\t\tgpios = <&led_gpio 1 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan3 {\n\t\t\tlabel = \"green:lan3\";\n\t\t\tgpios = <&led_gpio 2 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan4 {\n\t\t\tlabel = \"green:lan4\";\n\t\t\tgpios = <&led_gpio 3 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"factory-boot\";\n\t\t\t\treg = <0x000000 0x020000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x020000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x030000 0x7a0000>;\n\t\t\t};\n\n\t\t\tconfig: partition@7d0000 {\n\t\t\t\tlabel = \"config\";\n\t\t\t\treg = <0x7d0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tinfo: partition@7e0000 {\n\t\t\t\tlabel = \"info\";\n\t\t\t\treg = <0x7e0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tart: partition@7f0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0x7f0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tphy-handle = <&swphy4>;\n\n\tnvmem-cells = <&macaddr_info_8>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&eth1 {\n\tstatus = \"okay\";\n\n\tnvmem-cells = <&macaddr_info_8>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <1>;\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n\tnvmem-cells = <&macaddr_info_8>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&info {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_info_8: macaddr@8 {\n\t\treg = <0x8 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9561_tplink_archer-c58-v1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9561_tplink_archer-c5x.dtsi\"\n\n/ {\n\tcompatible = \"tplink,archer-c58-v1\", \"qca,qca9560\";\n\tmodel = \"TP-Link Archer C58 v1\";\n\n\taliases {\n\t\tlabel-mac-device = &eth1;\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tinfo: partition@10000 {\n\t\t\t\tlabel = \"info\";\n\t\t\t\treg = <0x010000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x020000 0x7c0000>;\n\t\t\t};\n\n\t\t\tpartition@7e0000 {\n\t\t\t\tlabel = \"tplink\";\n\t\t\t\treg = <0x7e0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tart: partition@7f0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0x7f0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&eth0 {\n\tnvmem-cells = <&macaddr_info_8>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <1>;\n};\n\n&eth1 {\n\tnvmem-cells = <&macaddr_info_8>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wmac {\n\tmtd-cal-data = <&art 0x1000>;\n\n\tnvmem-cells = <&macaddr_info_8>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&info {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_info_8: macaddr@8 {\n\t\treg = <0x8 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9561_tplink_archer-c59-v1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9561_tplink_archer-c5x.dtsi\"\n\n/ {\n\tcompatible = \"tplink,archer-c59-v1\", \"qca,qca9560\";\n\tmodel = \"TP-Link Archer C59 v1\";\n\n\taliases {\n\t\tlabel-mac-device = &eth1;\n\t};\n};\n\n&leds {\n\tusb {\n\t\tlabel = \"green:usb\";\n\t\tgpios = <&led_gpio 7 GPIO_ACTIVE_LOW>;\n\t\tlinux,default-trigger = \"usbport\";\n\t\ttrigger-sources = <&hub_port>;\n\t};\n};\n\n&usb0 {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\tstatus = \"okay\";\n\n\thub_port: port@1 {\n\t\treg = <1>;\n\t\t#trigger-source-cells = <0>;\n\t};\n};\n\n&usb_phy0 {\n\tstatus = \"okay\";\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tinfo: partition@10000 {\n\t\t\t\tlabel = \"info\";\n\t\t\t\treg = <0x010000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x020000 0xe30000>;\n\t\t\t};\n\n\t\t\tpartition@e50000 {\n\t\t\t\tlabel = \"tplink\";\n\t\t\t\treg = <0xe50000 0x1a0000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tart: partition@ff0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0xff0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&eth0 {\n\tnvmem-cells = <&macaddr_info_8>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <1>;\n};\n\n&eth1 {\n\tnvmem-cells = <&macaddr_info_8>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wmac {\n\tmtd-cal-data = <&art 0x1000>;\n\n\tnvmem-cells = <&macaddr_info_8>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&info {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_info_8: macaddr@8 {\n\t\treg = <0x8 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9561_tplink_archer-c59-v2.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9561_tplink_archer-c5x.dtsi\"\n\n/ {\n\tcompatible = \"tplink,archer-c59-v2\", \"qca,qca9560\";\n\tmodel = \"TP-Link Archer C59 v2\";\n\n\taliases {\n\t\tlabel-mac-device = &eth1;\n\t};\n};\n\n&leds {\n\tusb\t{\n\t\tlabel =\t\"green:usb\";\n\t\tgpios =\t<&led_gpio 7 GPIO_ACTIVE_LOW>;\n\t\tlinux,default-trigger =\t\"usbport\";\n\t\ttrigger-sources\t= <&hub_port>;\n\t};\n};\n\n&usb0 {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\tstatus = \"okay\";\n\n\thub_port: port@1 {\n\t\treg = <1>;\n\t\t#trigger-source-cells = <0>;\n\t};\n};\n\n&usb_phy0 {\n\tstatus = \"okay\";\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"factory-boot\";\n\t\t\t\treg = <0x000000 0x020000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x020000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tinfo: partition@30000 {\n\t\t\t\tlabel = \"info\";\n\t\t\t\treg = <0x030000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x040000 0xe10000>;\n\t\t\t};\n\n\t\t\tpartition@e50000 {\n\t\t\t\tlabel = \"tplink\";\n\t\t\t\treg = <0xe50000 0x1a0000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tart: partition@ff0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0xff0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&eth0 {\n\tnvmem-cells = <&macaddr_info_8>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <1>;\n};\n\n&eth1 {\n\tnvmem-cells = <&macaddr_info_8>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wmac {\n\tmtd-cal-data = <&art 0x1000>;\n\n\tnvmem-cells = <&macaddr_info_8>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&info {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_info_8: macaddr@8 {\n\t\treg = <0x8 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9561_tplink_archer-c5x.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca956x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"tplink,archer-c5x\", \"qca,qca9560\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tled_spi {\n\t\tcompatible = \"spi-gpio\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tsck-gpios = <&gpio 18 GPIO_ACTIVE_HIGH>;\n\t\tmosi-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\t\tcs-gpios = <&gpio 20 GPIO_ACTIVE_HIGH>;\n\t\tnum-chipselects = <1>;\n\n\t\tled_gpio: led_gpio@0 {\n\t\t\tcompatible = \"fairchild,74hc595\";\n\t\t\treg = <0>;\n\t\t\tgpio-controller;\n\t\t\t#gpio-cells = <2>;\n\t\t\tregisters-number = <1>;\n\t\t\tspi-max-frequency = <10000000>;\n\t\t};\n\t};\n\n\tleds: leds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&led_gpio 0 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\twlan2g {\n\t\t\tlabel = \"green:wlan2g\";\n\t\t\tgpios = <&led_gpio 1 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\n\t\twlan5g {\n\t\t\tlabel = \"green:wlan5g\";\n\t\t\tgpios = <&led_gpio 2 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\twan_green {\n\t\t\tlabel = \"green:wan\";\n\t\t\tgpios = <&led_gpio 4 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twan_amber {\n\t\t\tlabel = \"amber:wan\";\n\t\t\tgpios = <&led_gpio 5 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan {\n\t\t\tlabel = \"green:lan\";\n\t\t\tgpios = <&led_gpio 3 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&led_gpio 6 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\twps {\n\t\t\tlabel = \"WPS button\";\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tgpios = <&gpio 1 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twifi {\n\t\t\tlabel = \"WiFi button\";\n\t\t\tlinux,code = <KEY_RFKILL>;\n\t\t\tgpios = <&gpio 2 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"Reset button\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 21 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tgpio-export {\n\t\tcompatible = \"gpio-export\";\n\n\t\tgpio_shift_register_oe {\n\t\t\tgpio-export,name = \"tp-link:oe:sr\";\n\t\t\tgpio-export,output = <0>;\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tgpio_shift_register_reset {\n\t\t\tgpio-export,name = \"tp-link:reset:sr\";\n\t\t\tgpio-export,output = <1>;\n\t\t\tgpios = <&gpio 19 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tphy-handle = <&swphy0>;\n\n\tgmac-config {\n\t\tdevice = <&gmac>;\n\n\t\tswitch-phy-addr-swap = <1>;\n\t\tswitch-phy-swap = <1>;\n\t};\n};\n\n&eth1 {\n\tstatus = \"okay\";\n};\n\n&wmac {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9561_tplink_archer-c60-v1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9561_tplink_archer-c6x.dtsi\"\n\n/ {\n\tcompatible = \"tplink,archer-c60-v1\", \"qca,qca9561\";\n\tmodel = \"TP-Link Archer C60 v1\";\n\n\taliases {\n\t\tlabel-mac-device = &eth1;\n\t};\n};\n\n&leds {\n\twan_amber {\n\t\tlabel = \"amber:wan\";\n\t\tgpios = <&gpio 22 GPIO_ACTIVE_LOW>;\n\t};\n\n\twps {\n\t\tlabel = \"green:wps\";\n\t\tgpios = <&gpio 19 GPIO_ACTIVE_LOW>;\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tinfo: partition@10000 {\n\t\t\t\tlabel = \"info\";\n\t\t\t\treg = <0x010000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x020000 0x7c0000>;\n\t\t\t};\n\n\t\t\tpartition@7e0000 {\n\t\t\t\tlabel = \"tplink\";\n\t\t\t\treg = <0x7e0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tart: partition@7f0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0x7f0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&eth0 {\n\tnvmem-cells = <&macaddr_info_8>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <1>;\n};\n\n&eth1 {\n\tnvmem-cells = <&macaddr_info_8>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wmac {\n\tmtd-cal-data = <&art 0x1000>;\n\n\tnvmem-cells = <&macaddr_info_8>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&info {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_info_8: macaddr@8 {\n\t\treg = <0x8 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9561_tplink_archer-c60-v2.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9561_tplink_archer-c6x.dtsi\"\n\n/ {\n\tcompatible = \"tplink,archer-c60-v2\", \"qca,qca9561\";\n\tmodel = \"TP-Link Archer C60 v2\";\n\n\taliases {\n\t\tlabel-mac-device = &eth1;\n\t};\n};\n\n&leds {\n\twan_amber {\n\t\tlabel = \"amber:wan\";\n\t\tgpios = <&gpio 22 GPIO_ACTIVE_LOW>;\n\t};\n\n\twps {\n\t\tlabel = \"green:wps\";\n\t\tgpios = <&gpio 19 GPIO_ACTIVE_LOW>;\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"factory-boot\";\n\t\t\t\treg = <0x000000 0x01fb00>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tinfo: partition@1fb00 {\n\t\t\t\tlabel = \"info\";\n\t\t\t\treg = <0x01fb00 0x000500>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x020000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x030000 0x7a0000>;\n\t\t\t};\n\n\t\t\tpartition@7d0000 {\n\t\t\t\tlabel = \"tplink\";\n\t\t\t\treg = <0x7d0000 0x020000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tart: partition@7f0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0x7f0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&eth0 {\n\tnvmem-cells = <&macaddr_info_8>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <1>;\n};\n\n&eth1 {\n\tnvmem-cells = <&macaddr_info_8>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wmac {\n\tmtd-cal-data = <&art 0x1000>;\n\n\tnvmem-cells = <&macaddr_info_8>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&info {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_info_8: macaddr@8 {\n\t\treg = <0x8 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9561_tplink_archer-c60-v3.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9561_tplink_archer-c6x.dtsi\"\n\n/ {\n\tcompatible = \"tplink,archer-c60-v3\", \"qca,qca9561\";\n\tmodel = \"TP-Link Archer C60 v3\";\n\n\taliases {\n\t\tlabel-mac-device = &eth1;\n\t};\n};\n\n&leds {\n\twan_amber {\n\t\tlabel = \"amber:wan\";\n\t\tgpios = <&gpio 19 GPIO_ACTIVE_LOW>;\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"factory-boot\";\n\t\t\t\treg = <0x000000 0x01fb00>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tinfo: partition@1fb00 {\n\t\t\t\tlabel = \"info\";\n\t\t\t\treg = <0x01fb00 0x000500>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x020000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x030000 0x7a0000>;\n\t\t\t};\n\n\t\t\tpartition@7d0000 {\n\t\t\t\tlabel = \"tplink\";\n\t\t\t\treg = <0x7d0000 0x020000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tart: partition@7f0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0x7f0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&eth0 {\n\tnvmem-cells = <&macaddr_info_8>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <1>;\n};\n\n&eth1 {\n\tnvmem-cells = <&macaddr_info_8>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wmac {\n\tmtd-cal-data = <&art 0x1000>;\n\n\tnvmem-cells = <&macaddr_info_8>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&info {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_info_8: macaddr@8 {\n\t\treg = <0x8 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9561_tplink_archer-c6x.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca956x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\twifi {\n\t\t\tlabel = \"WiFi button\";\n\t\t\tlinux,code = <KEY_RFKILL>;\n\t\t\tgpios = <&gpio 1 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"Reset button\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 21 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tleds: leds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\twlan2g {\n\t\t\tlabel = \"green:wlan2g\";\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\n\t\twlan5g {\n\t\t\tlabel = \"green:wlan5g\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\twan_green {\n\t\t\tlabel = \"green:wan\";\n\t\t\tgpios = <&gpio 20 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan {\n\t\t\tlabel = \"green:lan\";\n\t\t\tgpios = <&gpio 2 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tphy-handle = <&swphy4>;\n};\n\n&eth1 {\n\tstatus = \"okay\";\n};\n\n&wmac {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9561_tplink_eap225-wall-v2.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca956x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"tplink,eap225-wall-v2\", \"qca,qca9561\";\n\tmodel = \"TP-Link EAP225-Wall v2\";\n\n\taliases {\n\t\tlabel-mac-device = &eth1;\n\t\tled-boot = &led_status;\n\t\tled-failsafe = &led_status;\n\t\tled-running = &led_status;\n\t\tled-upgrade = &led_status;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"Reset button\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\tled {\n\t\t\tlabel = \"LED button\";\n\t\t\tlinux,code = <KEY_LIGHTS_TOGGLE>;\n\t\t\tgpios = <&gpio 21 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_status: status {\n\t\t\tlabel = \"white:status\";\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\tgpio-export {\n\t\tcompatible = \"gpio-export\";\n\n\t\tpoe_passthrough {\n\t\t\tgpio-export,name = \"tp-link:poe-passthrough:enable\";\n\t\t\tgpio-export,output = <0>;\n\t\t\tgpios = <&gpio 20 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x020000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tlabel = \"partition-table\";\n\t\t\t\treg = <0x020000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tinfo: partition@30000 {\n\t\t\t\tlabel = \"info\";\n\t\t\t\treg = <0x030000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tcompatible = \"openwrt,elf\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x040000 0xd80000>;\n\t\t\t};\n\n\t\t\tpartition@dc0000 {\n\t\t\t\tlabel = \"config\";\n\t\t\t\treg = <0xdc0000 0x030000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\t/* df0000-f30000 undefined in vendor firmware */\n\n\t\t\tpartition@f30000 {\n\t\t\t\tlabel = \"mutil-log\";\n\t\t\t\treg = <0xf30000 0x080000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@fb0000 {\n\t\t\t\tlabel = \"oops\";\n\t\t\t\treg = <0xfb0000 0x040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tart: partition@ff0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0xff0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&eth1 {\n\tstatus = \"okay\";\n\n\tnvmem-cells = <&macaddr_info_8>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n\tnvmem-cells = <&macaddr_info_8>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&info {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_info_8: macaddr@8 {\n\t\treg = <0x8 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9561_xiaomi_mi-router-4q.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca956x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"xiaomi,mi-router-4q\", \"qca,qca9560\";\n\tmodel = \"Xiaomi Mi Router 4Q\";\n\n\taliases {\n\t\tled-boot = &led_yellow;\n\t\tled-failsafe = &led_red;\n\t\tled-running = &led_blue;\n\t\tled-upgrade = &led_red;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"Reset button\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 21 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"WPS/MI button\";\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tgpios = <&gpio 19 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_red: led_red {\n\t\t\tlabel = \"red:led\";\n\t\t\tgpios = <&gpio 1 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_yellow: led_yellow {\n\t\t\tlabel = \"yellow:led\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_blue: led_blue {\n\t\t\tlabel = \"blue:led\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"nvram\";\n\t\t\t\treg = <0x030000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"boarddata\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tlabel = \"crash\";\n\t\t\t\treg = <0x50000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tart: partition@60000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0x60000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@70000 {\n\t\t\t\tlabel = \"cfg_bak\";\n\t\t\t\treg = <0x70000 0x20000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@90000 {\n\t\t\t\tlabel = \"overlay\";\n\t\t\t\treg = <0x90000 0x170000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@200000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x200000 0xe00000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tphy-handle = <&swphy4>;\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&eth1 {\n\tstatus = \"okay\";\n\n\tnvmem-cells = <&macaddr_art_6>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <1>;\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n\n\tmacaddr_art_6: macaddr@6 {\n\t\treg = <0x6 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9563_asus_rp-ac66.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca956x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/leds/common.h>\n\n/ {\n\tmodel = \"ASUS RP-AC66\";\n\tcompatible = \"asus,rp-ac66\", \"qca,qca9563\";\n\n\taliases {\n\t\tled-boot = &led_orange;\n\t\tled-failsafe = &led_orange;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_orange;\n\t\tlabel-mac-device = &eth0;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 6 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tled_orange: wps {\n\t\t\tlabel = \"orange:wps\";\n\t\t\tgpios = <&gpio 1 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\trssilow-wlan0 {\n\t\t\tlabel = \"blue:rssilow-wlan0\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\trssimedium-wlan0 {\n\t\t\tlabel = \"red:rssimedium-wlan0\";\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\trssihigh-wlan0 {\n\t\t\tlabel = \"green:rssihigh-wlan0\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\trssilow-wlan1 {\n\t\t\tlabel = \"blue:rssilow-wlan1\";\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\trssimedium-wlan1 {\n\t\t\tlabel = \"red:rssimedium-wlan1\";\n\t\t\tgpios = <&gpio 9 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\trssihigh-wlan1 {\n\t\t\tlabel = \"green:rssihigh-wlan1\";\n\t\t\tgpios = <&gpio 8 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\twps {\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tgpios = <&gpio 5 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\treset {\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 2 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <50000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x40000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x040000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tart: partition@50000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0x050000 0x10000>;\n\t\t\t\tread-only;\n\n\t\t\t\tcompatible = \"nvmem-cells\";\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\n\t\t\t\tmacaddr_art_1002: macaddr@1002 {\n\t\t\t\t\treg = <0x1002 0x6>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tpartition@60000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x060000 0xfa0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy-mask = <0>;\n\n\tphy0: ethernet-phy@3 {\n\t\treg = <0x3>;\n\t\tphy-mode = \"sgmii\";\n\t\tqca,mib-poll-interval = <500>;\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tphy-mode = \"sgmii\";\n\tnvmem-cells = <&macaddr_art_1002>;\n\tnvmem-cell-names = \"mac-address\";\n\tphy-handle = <&phy0>;\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tqca,no-eeprom;\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9563_comfast_cf-e375ac.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca956x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"COMFAST CF-E375AC\";\n\tcompatible = \"comfast,cf-e375ac\", \"qca,qca9563\";\n\n\taliases {\n\t\tlabel-mac-device = &eth0;\n\t\tled-boot = &led_lan;\n\t\tled-failsafe = &led_lan;\n\t\tled-running = &led_lan;\n\t\tled-upgrade = &led_lan;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_lan: lan {\n\t\t\tlabel = \"green:lan\";\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\twan {\n\t\t\tlabel = \"red:wan\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\twlan2g {\n\t\t\tlabel = \"blue:wlan2g\";\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 2 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\twatchdog {\n\t\tcompatible = \"linux,wdt-gpio\";\n\n\t\tgpios = <&gpio 6 GPIO_ACTIVE_HIGH>;\n\t\thw_algo = \"toggle\";\n\t\thw_margin_ms = <500>;\n\t\talways-running;\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tart: partition@40000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0x040000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x050000 0xfa0000>;\n\t\t\t};\n\n\t\t\tpartition@ff0000 {\n\t\t\t\tlabel = \"art-backup\";\n\t\t\t\treg = <0xff0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy-mask = <0>;\n\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t\tphy-mode = \"sgmii\";\n\t\tqca,mib-poll-interval = <500>;\n\n\t\tqca,ar8327-initvals = <\n\t\t\t0x04 0x00080080 /* PORT0 PAD MODE CTRL */\n\t\t\t0x7c 0x0000007e /* PORT0_STATUS */\n\t\t>;\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tpll-data = <0x03000101 0x00000101 0x00001919>;\n\n\tphy-mode = \"sgmii\";\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n\tphy-handle = <&phy0>;\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <10>;\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9563_compex_wpj563.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca956x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"Compex WPJ563\";\n\tcompatible = \"compex,wpj563\", \"qca,qca9563\";\n\n\taliases {\n\t\tlabel-mac-device = &eth0;\n\t\tled-boot = &led_sig4;\n\t\tled-failsafe = &led_sig4;\n\t\tled-running = &led_sig4;\n\t\tled-upgrade = &led_sig4;\n\t};\n\n\tbeeper {\n\t\tcompatible = \"gpio-beeper\";\n\t\tgpios = <&gpio 19 GPIO_ACTIVE_HIGH>;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 2 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tsig1 {\n\t\t\tlabel = \"green:sig1\";\n\t\t\tgpios = <&gpio 1 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tsig2 {\n\t\t\tlabel = \"green:sig2\";\n\t\t\tgpios = <&gpio 5 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tsig3 {\n\t\t\tlabel = \"green:sig4\";\n\t\t\tgpios = <&gpio 6 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_sig4: sig4 {\n\t\t\tlabel = \"green:sig4\";\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tuboot: partition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x030000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x030000 0xfc0000>;\n\t\t\t};\n\n\t\t\tart: partition@ff0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0xff0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy-mask = <0>;\n\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t\tphy-mode = \"sgmii\";\n\t\tqca,mib-poll-interval = <500>;\n\n\t\tqca,ar8327-initvals = <\n\t\t\t0x04 0x00080080 /* PORT0 PAD MODE CTRL */\n\t\t\t0x7c 0x0000007e /* PORT0_STATUS */\n\t\t>;\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tpll-data = <0x03000101 0x00000101 0x00001919>;\n\n\tnvmem-cells = <&macaddr_uboot_2e010>;\n\tnvmem-cell-names = \"mac-address\";\n\tphy-mode = \"sgmii\";\n\tphy-handle = <&phy0>;\n};\n\n&usb_phy0 {\n\tstatus = \"okay\";\n};\n\n&usb0 {\n\tstatus = \"okay\";\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n};\n\n&uboot {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_uboot_2e010: macaddr@2e010 {\n\t\treg = <0x2e010 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9563_dlink_dir-842-c.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca956x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\twps {\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tgpios = <&gpio 1 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\treset {\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 2 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 5 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&gpio 8 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan {\n\t\t\tlabel = \"green:wlan\";\n\t\t\tgpios = <&gpio 19 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <50000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x40000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x040000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tlabel = \"devdata\";\n\t\t\t\treg = <0x050000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@60000 {\n\t\t\t\tlabel = \"devconf\";\n\t\t\t\treg = <0x060000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@70000 {\n\t\t\t\tlabel = \"misc\";\n\t\t\t\treg = <0x070000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@80000 {\n\t\t\t\tcompatible = \"seama\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x080000 0xf50000>;\n\t\t\t};\n\n\t\t\tart: partition@fd0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0xfd0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@fe0000 {\n\t\t\t\tlabel = \"reserved\";\n\t\t\t\treg = <0xfe0000 0x20000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy-mask = <0>;\n\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t\tqca,mib-poll-interval = <500>;\n\t\treset-gpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\n\t\tqca,ar8327-initvals = <\n\t\t\t0x04 0x00080080 /* PORT0 PAD MODE CTRL */\n\t\t\t0x10 0x81000080 /* POWER_ON_STRAP */\n\t\t\t0x50 0xcc35cc35 /* LED_CTRL0 */\n\t\t\t0x54 0xcb37cb37 /* LED_CTRL1 */\n\t\t\t0x58 0x00000000 /* LED_CTRL2 */\n\t\t\t0x5c 0x00f3cf00 /* LED_CTRL3 */\n\t\t\t0x7c 0x0000007e /* PORT0_STATUS */\n\t\t\t>;\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tpll-data = <0x03000101 0x00000101 0x00001919>;\n\n\tphy-mode = \"sgmii\";\n\tphy-handle = <&phy0>;\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tqca,no-eeprom;\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9563_dlink_dir-842-c1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9563_dlink_dir-842-c.dtsi\"\n\n/ {\n\tcompatible = \"dlink,dir-842-c1\", \"qca,qca9563\";\n\tmodel = \"D-Link DIR-842 C1\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9563_dlink_dir-842-c2.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9563_dlink_dir-842-c.dtsi\"\n\n/ {\n\tcompatible = \"dlink,dir-842-c2\", \"qca,qca9563\";\n\tmodel = \"D-Link DIR-842 C2\";\n};\n\n&usb_phy0 {\n\tstatus = \"okay\";\n};\n\n&usb0 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9563_dlink_dir-842-c3.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9563_dlink_dir-842-c.dtsi\"\n\n/ {\n\tcompatible = \"dlink,dir-842-c3\", \"qca,qca9563\";\n\tmodel = \"D-Link DIR-842 C3\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9563_dlink_dir-859-a1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca956x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"D-Link DIR-859 A1\";\n\tcompatible = \"dlink,dir-859-a1\", \"qca,qca9563\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twps {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&gpio 8 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_power: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tinternet {\n\t\t\tlabel = \"green:internet\";\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan {\n\t\t\tlabel = \"green:wlan\";\n\t\t\tgpios = <&gpio 19 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\twps {\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tgpios = <&gpio 1 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\treset {\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 2 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tgpio-export {\n\t\tcompatible = \"gpio-export\";\n\t\t#size-cells = <0>;\n\n\t\tgpio_switch_reset {\n\t\t\tgpio-export,name = \"dir-859-a1:reset:switch\";\n\t\t\tgpio-export,output = <1>;\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <50000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"bootloader\";\n\t\t\t\treg = <0x000000 0x40000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"bdcfg\";\n\t\t\t\treg = <0x040000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tlabel = \"devdata\";\n\t\t\t\treg = <0x050000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@60000 {\n\t\t\t\tlabel = \"devconf\";\n\t\t\t\treg = <0x060000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@70000 {\n\t\t\t\tcompatible = \"seama\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x070000 0xf80000>;\n\t\t\t};\n\n\t\t\tart: partition@ff0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0xff0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy-mask = <0>;\n\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t\tphy-mode = \"sgmii\";\n\t\tqca,mib-poll-interval = <500>;\n\n\t\tqca,ar8327-initvals = <\n\t\t\t0x04 0x00080080 /* PORT0 PAD MODE CTRL */\n\t\t\t0x10 0x81000080 /* POWER_ON_STRAP */\n\t\t\t0x50 0xcc35cc35 /* LED_CTRL0 */\n\t\t\t0x54 0xcb37cb37 /* LED_CTRL1 */\n\t\t\t0x58 0x00000000 /* LED_CTRL2 */\n\t\t\t0x5c 0x00f3cf00 /* LED_CTRL3 */\n\t\t\t0x7c 0x0000007e /* PORT0_STATUS */\n\t\t\t>;\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tpll-data = <0x03000101 0x00000101 0x00001919>;\n\n\tphy-mode = \"sgmii\";\n\tphy-handle = <&phy0>;\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tqca,no-eeprom;\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9563_elecom_wrc-1750ghbk2-i.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9563_elecom_wrc-ghbk2-i.dtsi\"\n\n/ {\n\tmodel = \"ELECOM WRC-1750GHBK2-I/C\";\n\tcompatible = \"elecom,wrc-1750ghbk2-i\", \"qca,qca9563\";\n};\n\n&leds {\n\tled_power: power {\n\t\tlabel = \"blue:power\";\n\t\tgpios = <&gpio 1 GPIO_ACTIVE_HIGH>;\n\t\tdefault-state = \"on\";\n\t};\n\n\twlan2g {\n\t\tlabel = \"blue:wlan2g\";\n\t\tgpios = <&gpio 7 GPIO_ACTIVE_HIGH>;\n\t\tlinux,default-trigger = \"phy1tpt\";\n\t};\n\n\twlan5g {\n\t\tlabel = \"blue:wlan5g\";\n\t\tgpios = <&gpio 8 GPIO_ACTIVE_HIGH>;\n\t\tlinux,default-trigger = \"phy0tpt\";\n\t};\n};\n\n&partitions {\n\tpartition@70000 {\n\t\tcompatible = \"denx,uimage\";\n\t\tlabel = \"firmware\";\n\t\treg = <0x070000 0xf70000>;\n\t};\n\n\tpartition@fe0000 {\n\t\tlabel = \"hwconfig\";\n\t\treg = <0xfe0000 0x010000>;\n\t\tread-only;\n\t};\n\n\tart: partition@ff0000 {\n\t\tlabel = \"art\";\n\t\treg = <0xff0000 0x010000>;\n\t\tread-only;\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&eth0 {\n\tnvmem-cells = <&macaddr_art_1002>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <(-1)>;\n};\n\n&wmac {\n\tmtd-cal-data = <&art 0x1000>;\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_1002: macaddr@1002 {\n\t\treg = <0x1002 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9563_elecom_wrc-300ghbk2-i.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9563_elecom_wrc-ghbk2-i.dtsi\"\n\n/ {\n\tmodel = \"ELECOM WRC-300GHBK2-I\";\n\tcompatible = \"elecom,wrc-300ghbk2-i\", \"qca,qca9563\";\n};\n\n&leds {\n\tled_power: power {\n\t\tlabel = \"white:power\";\n\t\tgpios = <&gpio 1 GPIO_ACTIVE_HIGH>;\n\t\tdefault-state = \"on\";\n\t};\n\n\twlan2g {\n\t\tlabel = \"white:wlan2g\";\n\t\tgpios = <&gpio 7 GPIO_ACTIVE_HIGH>;\n\t\tlinux,default-trigger = \"phy0tpt\";\n\t};\n};\n\n&partitions {\n\tpartition@70000 {\n\t\tcompatible = \"denx,uimage\";\n\t\tlabel = \"firmware\";\n\t\treg = <0x070000 0x770000>;\n\t};\n\n\tpartition@7e0000 {\n\t\tlabel = \"hwconfig\";\n\t\treg = <0x7e0000 0x010000>;\n\t\tread-only;\n\t};\n\n\tart: partition@7f0000 {\n\t\tlabel = \"art\";\n\t\treg = <0x7f0000 0x010000>;\n\t\tread-only;\n\t};\n};\n\n&eth0 {\n\tnvmem-cells = <&macaddr_art_1002>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <(-1)>;\n};\n\n&wmac {\n\tmtd-cal-data = <&art 0x1000>;\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_1002: macaddr@1002 {\n\t\treg = <0x1002 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9563_elecom_wrc-ghbk2-i.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca956x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tleds: leds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twps {\n\t\t\tlabel = \"red:wps\";\n\t\t\tgpios = <&gpio 9 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 2 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio 5 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\tap {\n\t\t\tlabel = \"ap\";\n\t\t\tgpios = <&gpio 6 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_0>;\n\t\t\tlinux,input-type = <EV_SW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions: partitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x040000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tlabel = \"nvram\";\n\t\t\t\treg = <0x050000 0x020000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\n\t\tqca,ar8327-initvals = <\n\t\t\t0x04 0x00000080 /* PORT0 PAD MODE CTRL */\n\t\t\t0x50 0xcf37cf37 /* LED_CTRL0 */\n\t\t\t0x54 0x00000000 /* LED_CTRL1 */\n\t\t\t0x58 0x00000000 /* LED_CTRL2 */\n\t\t\t0x5c 0x03ffff00 /* LED_CTRL3 */\n\t\t\t0x7c 0x0000007e /* PORT0_STATUS */\n\t\t>;\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tpll-data = <0x03000101 0x00000101 0x00001919>;\n\n\tphy-mode = \"sgmii\";\n\tphy-handle = <&phy0>;\n};\n\n&wmac {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9563_glinet_gl-ar750s-nor-nand.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9563_glinet_gl-ar750s.dtsi\"\n\n/ {\n\tcompatible = \"glinet,gl-ar750s-nor-nand\", \"qca,qca9563\";\n\tmodel = \"GL.iNet GL-AR750S (NOR/NAND)\";\n};\n\n&nor_partitions {\n\tpartition@60000 {\n\t\tlabel = \"kernel\";\n\t\treg = <0x060000 0x400000>;\n\n\t\t/*\n\t\t * U-Boot bootcmd is \"bootm 0x9f060000\".\n\t\t * So this might be possible to resize in the future.\n\t\t */\n\t};\n\n\tpartition@460000 {\n\t\tlabel = \"nor_reserved\";\n\t\treg = <0x460000 0xba0000>;\n\t};\n};\n\n&nand_ubi {\n\tlabel = \"ubi\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9563_glinet_gl-ar750s-nor.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9563_glinet_gl-ar750s.dtsi\"\n\n/ {\n\tcompatible = \"glinet,gl-ar750s-nor\", \"qca,qca9563\";\n\tmodel = \"GL.iNet GL-AR750S (NOR)\";\n};\n\n&nor_partitions {\n\tpartition@60000 {\n\t\tcompatible = \"denx,uimage\";\n\t\tlabel = \"firmware\";\n\t\treg = <0x060000 0xfa0000>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9563_glinet_gl-ar750s.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca956x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"glinet,gl-ar750s\", \"qca,qca9563\";\n\tmodel = \"GL.iNet GL-AR750S\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t\tlabel-mac-device = &eth0;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\tpinctrl-names = \"default\";\n\t\tpinctrl-0 = <&jtag_disable_pins>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 2 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tmode {\n\t\t\tlabel = \"mode\";\n\t\t\tlinux,code = <BTN_0>;\n\t\t\tlinux,input-type = <EV_SW>;\n\t\t\tgpios = <&gpio 8 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 1 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"keep\";\n\t\t};\n\n\t\tled_wlan2g: wlan2g {\n\t\t\tlabel = \"green:wlan2g\";\n\t\t\tgpios = <&gpio 19 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\n\t\tled_wlan5g: wlan5g {\n\t\t\tlabel = \"green:wlan5g\";\n\t\t\tgpios = <&gpio 20 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\t};\n\n\ti2c: i2c {\n\t\tcompatible = \"i2c-gpio\";\n\n\t\tsda-gpios = <&gpio  5 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;\n\t\tscl-gpios = <&gpio 21 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash_nor: flash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tnor_partitions: partitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x040000 0x010000>;\n\t\t\t};\n\n\t\t\tart: partition@50000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0x050000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\t/* Firmware / Kernel flash type specific */\n\t\t};\n\t};\n\n\tflash_nand: flash@1 {\n\t\tcompatible = \"spi-nand\";\n\t\treg = <1>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tnand_partitions: partitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tnand_ubi: partition@0 {\n\t\t\t\tlabel = \"nand_ubi\";\n\t\t\t\treg = <0x000000 0x8000000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tphy-handle = <&phy0>;\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&gpio {\n\tusb_vbus {\n\t\tgpio-hog;\n\t\tgpios = <7 GPIO_ACTIVE_HIGH>;\n\t\toutput-high;\n\t\tline-name = \"usb-vbus\";\n\t};\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy-mask = <0>;\n\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t\tphy-mode = \"sgmii\";\n\t\tqca,ar8327-initvals = <\n\t\t\t0x04 0x00080080 /* PORT0 PAD MODE CTRL */\n\t\t\t0x7c 0x0000007e /* PORT0_STATUS */\n\t\t>;\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&usb0 {\n\tstatus = \"okay\";\n};\n\n&usb1 {\n\tstatus = \"okay\";\n};\n\n&usb_phy0 {\n\tstatus = \"okay\";\n};\n\n&usb_phy1 {\n\tstatus = \"okay\";\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9563_nec_wg1200cr.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca956x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"NEC Aterm WG1200CR\";\n\tcompatible = \"nec,wg1200cr\", \"qca,qca9563\";\n\n\taliases {\n\t\tled-boot = &led_power_green;\n\t\tled-failsafe = &led_power_red;\n\t\tled-running = &led_power_green;\n\t\tled-upgrade = &led_power_green;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\t/* other LEDs are connected to ath10k (QCA9888) gpiochip */\n\n\t\tled_power_green: power_green {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 5 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\tled_power_red: power_red {\n\t\t\tlabel = \"red:power\";\n\t\t\tgpios = <&gpio 6 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 1 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio 2 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\tbridge {\n\t\t\tlabel = \"br\";\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_0>;\n\t\t\tlinux,input-type = <EV_SW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\tconverter {\n\t\t\tlabel = \"cnv\";\n\t\t\tgpios = <&gpio 8 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_0>;\n\t\t\tlinux,input-type = <EV_SW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"devdata\";\n\t\t\t\treg = <0x040000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tlabel = \"devconf\";\n\t\t\t\treg = <0x050000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@60000 {\n\t\t\t\tlabel = \"misc\";\n\t\t\t\treg = <0x060000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@70000 {\n\t\t\t\tlabel = \"wifimngdata\";\n\t\t\t\treg = <0x070000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@80000 {\n\t\t\t\tcompatible = \"seama\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x080000 0x770000>;\n\t\t\t};\n\n\t\t\tpartition@7f0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0x7f0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\n\t\tqca,ar8327-initvals = <\n\t\t\t0x04 0x00000080 /* PORT0 PAD MODE CTRL */\n\t\t\t0x50 0xcc35cc35 /* LED_CTRL0 */\n\t\t\t0x54 0xca35ca35 /* LED_CTRL1 */\n\t\t\t0x58 0xc935c935 /* LED_CTRL2 */\n\t\t\t0x5c 0x03ffff00 /* LED_CTRL3 */\n\t\t\t0x7c 0x0000007e /* PORT0_STATUS */\n\t\t>;\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tpll-data = <0x03000101 0x00000101 0x00001919>;\n\n\tphy-mode = \"sgmii\";\n\tphy-handle = <&phy0>;\n};\n\n&pcie {\n\tstatus = \"okay\";\n\n\twifi@0,0 {\n\t\tcompatible = \"pci168c,0056\";\n\t\treg = <0x0000 0 0 0 0>;\n\t};\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tqca,no-eeprom;\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9563_nec_wg800hp.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca956x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"NEC Aterm WG800HP\";\n\tcompatible = \"nec,wg800hp\", \"qca,qca9563\";\n\n\taliases {\n\t\tled-boot = &led_power_green;\n\t\tled-failsafe = &led_power_red;\n\t\tled-running = &led_power_green;\n\t\tled-upgrade = &led_power_green;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tpinctrl-names = \"default\";\n\t\tpinctrl-0 = <&jtag_disable_pins>;\n\n\t\twlan2g_red {\n\t\t\tlabel = \"red:wlan2g\";\n\t\t\tgpios = <&gpio 6 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tactive_red {\n\t\t\tlabel = \"red:active\";\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tactive_green {\n\t\t\tlabel = \"green:active\";\n\t\t\tgpios = <&gpio 8 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_power_red: power_red {\n\t\t\tlabel = \"red:power\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_power_green: power_green {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\twlan5g_red {\n\t\t\tlabel = \"red:wlan5g\";\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\twlan5g_green {\n\t\t\tlabel = \"green:wlan5g\";\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\twlan2g_green {\n\t\t\tlabel = \"green:wlan2g\";\n\t\t\tgpios = <&gpio 19 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\tbr {\n\t\t\tlabel = \"br\";\n\t\t\tgpios = <&gpio 1 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_0>;\n\t\t\tlinux,input-type = <EV_SW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 2 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio 5 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x040000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x050000 0x6f0000>;\n\t\t\t};\n\n\t\t\tpartition@740000 {\n\t\t\t\tlabel = \"user_data\";\n\t\t\t\treg = <0x740000 0x0a0000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@7e0000 {\n\t\t\t\tlabel = \"board_data\";\n\t\t\t\treg = <0x7e0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tart: partition@7f0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0x7f0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\n\t\tqca,ar8327-initvals = <\n\t\t\t0x04 0x00000080 /* PORT0 PAD MODE CTRL */\n\t\t\t0x50 0xcc35cc35 /* LED_CTRL0 */\n\t\t\t0x54 0xca35ca35 /* LED_CTRL1 */\n\t\t\t0x58 0xc935c935 /* LED_CTRL2 */\n\t\t\t0x5c 0x03ffff00 /* LED_CTRL3 */\n\t\t\t0x7c 0x0000007e /* PORT0_STATUS */\n\t\t>;\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tphy-mode = \"sgmii\";\n\tphy-handle = <&phy0>;\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&wmac {\n\tstatus = \"okay\";\n\tqca,no-eeprom;\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9563_netgear_wndr.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca956x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\taliases {\n\t\tled-boot = &led_power_amber;\n\t\tled-failsafe = &led_power_amber;\n\t\tled-running = &led_power_green;\n\t\tled-upgrade = &led_power_amber;\n\t\tlabel-mac-device = &eth0;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tgpios = <&gpio 1 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 2 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tath9k-keys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <20>;\n\n\t\trfkill {\n\t\t\tlabel = \"rfkill\";\n\t\t\tlinux,code = <KEY_RFKILL>;\n\t\t\tgpios = <&ath9k 9 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds: leds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tpinctrl-names = \"default\";\n\t\tpinctrl-0 = <&jtag_disable_pins>;\n\n\t\tled_power_green: power_green {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 5 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_power_amber: power_amber {\n\t\t\tlabel = \"amber:power\";\n\t\t\tgpios = <&gpio 6 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"keep\";\n\t\t};\n\n\t\twan_green {\n\t\t\tlabel = \"green:wan\";\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twan_amber {\n\t\t\tlabel = \"amber:wan\";\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan2g_green {\n\t\t\tlabel = \"green:wlan2g\";\n\t\t\tgpios = <&gpio 19 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\twps_green {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tath9k-leds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twlan5g_blue {\n\t\t\tlabel = \"blue:wlan5g\";\n\t\t\tgpios = <&ath9k 7 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x40000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tlabel = \"caldata_backup\";\n\t\t\t\treg = <0x50000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@60000 {\n\t\t\t\tlabel = \"config\";\n\t\t\t\treg = <0x60000 0x10000>;\n\t\t\t};\n\n\t\t\tpartition@70000 {\n\t\t\t\tlabel = \"traffic_meter\";\n\t\t\t\treg = <0x70000 0x10000>;\n\t\t\t};\n\n\t\t\tpartition@80000 {\n\t\t\t\tlabel = \"pot\";\n\t\t\t\treg = <0x80000 0x10000>;\n\t\t\t};\n\n\t\t\tpartition@90000 {\n\t\t\t\tlabel = \"reserved\";\n\t\t\t\treg = <0x90000 0x160000>;\n\t\t\t};\n\n\t\t\tcaldata: partition@1f0000 {\n\t\t\t\tlabel = \"caldata\";\n\t\t\t\treg = <0x1f0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n\n\tflash@1 {\n\t\tcompatible = \"spi-nand\";\n\t\treg = <1>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"kernel\";\n\t\t\t\treg = <0x0 0x400000>;\n\t\t\t};\n\n\t\t\tpartition@400000 {\n\t\t\t\tlabel = \"ubi\";\n\t\t\t\treg = <0x400000 0x7c00000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy-mask = <0>;\n\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t\tphy-mode = \"sgmii\";\n\t\tqca,mib-poll-interval = <500>;\n\n\t\tqca,ar8327-initvals = <\n\t\t\t0x04 0x00000080\t/* PORT0 PAD MODE CTRL */\n\t\t\t0x10 0x81000080\t/* POWER_ON_STRAP */\n\t\t\t0x50 0xcc35cc35\t/* LED_CTRL0 */\n\t\t\t0x54 0xcb37cb37\t/* LED_CTRL1 */\n\t\t\t0x58 0x00000000\t/* LED_CTRL2 */\n\t\t\t0x5c 0x00f3cf00\t/* LED_CTRL3 */\n\t\t\t0x7c 0x0000007e\t/* PORT0_STATUS */\n\t\t\t0x94 0x00000200 /* PORT6_STATUS */\n\t\t\t>;\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tpll-data = <0x03000101 0x00000101 0x00001919>;\n\n\tnvmem-cells = <&macaddr_caldata_0>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tphy-mode = \"sgmii\";\n\tphy-handle = <&phy0>;\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tnvmem-cells = <&macaddr_caldata_0>;\n\tnvmem-cell-names = \"mac-address\";\n\tqca,no-eeprom;\n};\n\n&pcie {\n\tstatus = \"okay\";\n\n\tath9k: wifi@0,0 {\n\t\t/* chip is AR9580, override bogus PCI ID 168c:abcd */\n\t\tcompatible = \"pci168c,0033\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tnvmem-cells = <&macaddr_caldata_c>;\n\t\tnvmem-cell-names = \"mac-address\";\n\t\tqca,no-eeprom;\n\t\tqca,gpio-mask=<0xf6ff>;\t/* unmask pin 9 for RFKILL button */\n\t\t#gpio-cells = <2>;\n\t\tgpio-controller;\n\t};\n};\n\n&usb_phy0 {\n\tstatus = \"okay\";\n};\n\n&usb0 {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\tstatus = \"okay\";\n\n\thub_port0: port@1 {\n\t\treg = <1>;\n\t\t#trigger-source-cells = <0>;\n\t};\n};\n\n&caldata {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_caldata_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n\n\tmacaddr_caldata_c: macaddr@c {\n\t\treg = <0xc 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9563_netgear_wndr4300-v2.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9563_netgear_wndr.dtsi\"\n\n/ {\n\tcompatible = \"netgear,wndr4300-v2\", \"qca,qca9563\";\n\tmodel = \"Netgear WNDR4300 v2\";\n};\n\n&leds {\n\tusb_green {\n\t\tlabel = \"green:usb\";\n\t\tgpios = <&gpio 7 GPIO_ACTIVE_LOW>;\n\t\ttrigger-sources = <&hub_port0>;\n\t\tlinux,default-trigger = \"usbport\";\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9563_netgear_wndr4500-v3.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9563_netgear_wndr.dtsi\"\n\n/ {\n\tcompatible = \"netgear,wndr4500-v3\", \"qca,qca9563\";\n\tmodel = \"Netgear WNDR4500 v3\";\n};\n\n&leds {\n\tusb1_green {\n\t\tlabel = \"green:usb1\";\n\t\tgpios = <&gpio 7 GPIO_ACTIVE_LOW>;\n\t\ttrigger-sources = <&hub_port0>;\n\t\tlinux,default-trigger = \"usbport\";\n\t};\n\n\tusb2_green {\n\t\tlabel = \"green:usb2\";\n\t\tgpios = <&gpio 8 GPIO_ACTIVE_LOW>;\n\t\ttrigger-sources = <&hub_port1>;\n\t\tlinux,default-trigger = \"usbport\";\n\t};\n};\n\n&usb_phy1 {\n\tstatus = \"okay\";\n};\n\n&usb1 {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\tstatus = \"okay\";\n\n\thub_port1: port@1 {\n\t\treg = <1>;\n\t\t#trigger-source-cells = <0>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9563_phicomm_k2t.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca956x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"Phicomm K2T\";\n\tcompatible = \"phicomm,k2t\", \"qca,qca9563\";\n\n\taliases {\n\t\tled-boot = &led_status_red;\n\t\tled-failsafe = &led_status_red;\n\t\tled-running = &led_status_red;\n\t\tled-upgrade = &led_status_red;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tstatus_blue {\n\t\t\tlabel = \"blue:status\";\n\t\t\tgpios = <&gpio 6 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_status_red: status_red {\n\t\t\tlabel = \"red:status\";\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tstatus_yellow {\n\t\t\tlabel = \"yellow:status\";\n\t\t\tgpios = <&gpio 8 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 2 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"config\";\n\t\t\t\treg = <0x030000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"permanent\";\n\t\t\t\treg = <0x040000 0x50000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@90000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x090000 0xf60000>;\n\t\t\t};\n\n\t\t\tart: partition@ff0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0xff0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy-mask = <0>;\n\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t\tphy-mode = \"sgmii\";\n\n\t\tqca,ar8327-initvals = <\n\t\t\t0x04 0x00080080 /* PORT0 PAD MODE CTRL */\n\t\t\t0x10 0x81000080 /* POWER_ON_STRAP */\n\t\t\t0x50 0xcc35cc35 /* LED_CTRL0 */\n\t\t\t0x54 0xcb37cb37 /* LED_CTRL1 */\n\t\t\t0x58 0x00000000 /* LED_CTRL2 */\n\t\t\t0x5c 0x00f3cf00 /* LED_CTRL3 */\n\t\t\t0x7c 0x0000007e /* PORT0_STATUS */\n\t\t\t>;\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tpll-data = <0x03000101 0x00000101 0x00001919>;\n\n\tphy-mode = \"sgmii\";\n\tphy-handle = <&phy0>;\n};\n\n&wmac {\n\tstatus = \"okay\";\n\tmtd-cal-data = <&art 0x1000>;\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9563_qxwlan_e1700ac-v2-16m.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9563_qxwlan_e1700ac.dtsi\"\n\n/ {\n\tmodel = \"Qxwlan E1700AC v2 16M\";\n\tcompatible = \"qxwlan,e1700ac-v2-16m\", \"qca,qca9563\";\n};\n\n&partitions {\n\tpartition@70000 {\n\t\tcompatible = \"denx,uimage\";\n\t\tlabel = \"firmware\";\n\t\treg = <0x070000 0xf90000>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9563_qxwlan_e1700ac-v2-8m.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9563_qxwlan_e1700ac.dtsi\"\n\n/ {\n\tmodel = \"Qxwlan E1700AC v2 8M\";\n\tcompatible = \"qxwlan,e1700ac-v2-8m\", \"qca,qca9563\";\n};\n\n&partitions {\n\tpartition@70000 {\n\t\tcompatible = \"denx,uimage\";\n\t\tlabel = \"firmware\";\n\t\treg = <0x070000 0x790000>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9563_qxwlan_e1700ac.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca956x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\taliases {\n\t\tlabel-mac-device = &eth0;\n\t\tled-boot = &led_system;\n\t\tled-failsafe = &led_system;\n\t\tled-running = &led_system;\n\t\tled-upgrade = &led_system;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 2 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_system: system {\n\t\t\tlabel = \"green:system\";\n\t\t\tgpios = <&gpio 1 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\tusb {\n\t\t\tlabel = \"green:usb\";\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_LOW>;\n\t\t\ttrigger-sources = <&hub_port0>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\n\t\twlan2g {\n\t\t\tlabel = \"green:wlan2g\";\n\t\t\tgpios = <&gpio 19 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions: partitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x040000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpridata: partition@50000 {\n\t\t\t\tlabel = \"pri-data\";\n\t\t\t\treg = <0x050000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tart: partition@60000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0x060000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy-mask = <0>;\n\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t\tphy-mode = \"sgmii\";\n\t\tqca,mib-poll-interval = <500>;\n\n\t\tqca,ar8327-initvals = <\n\t\t\t0x04 0x00080080 /* PORT0 PAD MODE CTRL */\n\t\t\t0x7c 0x0000007e /* PORT0_STATUS */\n\t\t>;\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tpll-data = <0x03000101 0x00000101 0x00001919>;\n\n\tphy-mode = \"sgmii\";\n\tphy-handle = <&phy0>;\n\n\tnvmem-cells = <&macaddr_pridata_400>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&usb_phy0 {\n\tstatus = \"okay\";\n};\n\n&usb0 {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\tstatus = \"okay\";\n\n\thub_port0: port@1 {\n\t\treg = <1>;\n\t\t#trigger-source-cells = <0>;\n\t};\n};\n\n&usb_phy1 {\n\tstatus = \"okay\";\n};\n\n&usb1 {\n\tstatus = \"okay\";\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n};\n\n&pridata {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_pridata_400: macaddr@400 {\n\t\treg = <0x400 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9563_rosinson_wr818.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca956x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"ROSINSON WR818\";\n\tcompatible = \"rosinson,wr818\", \"qca,qca9563\";\n\n\taliases {\n\t\tled-boot = &led_system;\n\t\tled-failsafe = &led_system;\n\t\tled-running = &led_system;\n\t\tled-upgrade = &led_system;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_system: system {\n\t\t\tlabel = \"red:system\";\n\t\t\tgpios = <&gpio 1 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twifi_2g {\n\t\t\tlabel = \"red:wifi2g\";\n\t\t\tgpios = <&gpio 19 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 2 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x040000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tinfo: partition@50000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x050000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@60000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x060000 0xf80000>;\n\t\t\t};\n\n\t\t\tart: partition@ff0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0xff0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy-mask = <0>;\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t\tphy-mode = \"sgmii\";\n\n\t\tqca,ar8327-initvals = <\n\t\t\t0x04 0x00080080 /* PORT0 PAD MODE CTRL */\n\t\t\t0x7c 0x0000007e /* PORT0_STATUS */\n\t\t>;\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tnvmem-cells = <&macaddr_info_0>;\n\tnvmem-cell-names = \"mac-address\";\n\tphy-mode = \"sgmii\";\n\tphy-handle = <&phy0>;\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n};\n\n&usb_phy0 {\n\tstatus = \"okay\";\n};\n\n&usb0 {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\tstatus = \"okay\";\n\n\tport@1 {\n\t\treg = <1>;\n\t\t#trigger-source-cells = <0>;\n\t};\n};\n\n&usb_phy1 {\n\tstatus = \"okay\";\n};\n\n&usb1 {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\tstatus = \"okay\";\n\n\tport@2 {\n\t\treg = <2>;\n\t\t#trigger-source-cells = <0>;\n\t};\n};\n\n&info {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_info_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9563_tplink_archer-a7-v5.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9563_tplink_archer-x7-v5.dtsi\"\n\n/ {\n\tcompatible = \"tplink,archer-a7-v5\", \"qca,qca9563\";\n\tmodel = \"TP-Link Archer A7 v5\";\n\n\taliases {\n\t\tlabel-mac-device = &eth0;\n\t};\n};\n\n&keys {\n\treset {\n\t\tlabel = \"Reset button\";\n\t\tlinux,code = <KEY_RESTART>;\n\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\tdebounce-interval = <60>;\n\t};\n};\n\n&mtdparts {\n\tpartition@0 {\n\t\tlabel = \"factory-uboot\";\n\t\treg = <0x000000 0x020000>;\n\t\tread-only;\n\t};\n\n\tuboot: partition@20000 {\n\t\tlabel = \"u-boot\";\n\t\treg = <0x020000 0x020000>;\n\t\tread-only;\n\t};\n\n\tpartition@40000 {\n\t\tlabel = \"firmware\";\n\t\treg = <0x040000 0xec0000>;\n\t\tcompatible = \"denx,uimage\";\n\t};\n\n\tinfo: partition@f40000 {\n\t\tlabel = \"info\";\n\t\treg = <0xf40000 0x020000>;\n\t\tread-only;\n\t};\n\n\tconfig: partition@f60000 {\n\t\tlabel = \"config\";\n\t\treg = <0xf60000 0x050000>;\n\t\tread-only;\n\t};\n\n\tpartition@fc0000 {\n\t\tlabel = \"partition-table\";\n\t\treg = <0xfc0000 0x010000>;\n\t\tread-only;\n\t};\n\n\tart: partition@ff0000 {\n\t\tlabel = \"art\";\n\t\treg = <0xff0000 0x010000>;\n\t\tread-only;\n\t};\n};\n\n&eth0 {\n\tnvmem-cells = <&macaddr_info_8>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wmac {\n\tmtd-cal-data = <&art 0x1000>;\n\n\tnvmem-cells = <&macaddr_info_8>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&info {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_info_8: macaddr@8 {\n\t\treg = <0x8 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9563_tplink_archer-c2-v3.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca956x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"tplink,archer-c2-v3\", \"qca,qca9563\";\n\tmodel = \"TP-Link Archer C2 v3\";\n\n\taliases {\n\t\tled-boot = &led_system;\n\t\tled-failsafe = &led_system;\n\t\tled-running = &led_system;\n\t\tled-upgrade = &led_system;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_system: system {\n\t\t\tlabel = \"green:system\";\n\t\t\tgpios = <&gpio 6 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\twifi2g {\n\t\t\tlabel = \"green:wifi2g\";\n\t\t\tgpios = <&gpio 8 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\n\t\twifi5g {\n\t\t\tlabel = \"green:wifi5g\";\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\twifi_wps {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&gpio 1 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twan {\n\t\t\tlabel = \"green:wan\";\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twan_fail {\n\t\t\tlabel = \"orange:wan\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan1 {\n\t\t\tlabel = \"green:lan1\";\n\t\t\tgpios = <&gpio 9 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan2 {\n\t\t\tlabel = \"green:lan2\";\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan3 {\n\t\t\tlabel = \"green:lan3\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan4 {\n\t\t\tlabel = \"green:lan4\";\n\t\t\tgpios = <&gpio 21 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"Reset button\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 2 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"WPS button\";\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tgpios = <&gpio 5 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"factory-uboot\";\n\t\t\t\treg = <0x000000 0x020000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tlabel = \"uboot\";\n\t\t\t\treg = <0x020000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x030000 0x7A0000>;\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t};\n\n\t\t\tinfo: partition@7e0000 {\n\t\t\t\tlabel = \"info\";\n\t\t\t\treg = <0x7e0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tart: partition@7f0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0x7f0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy-mask = <0>;\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t\tphy-mode = \"sgmii\";\n\t\tqca,mib-poll-interval = <500>;\n\n\t\tqca,ar8327-initvals = <\n\t\t\t0x04 0x00080080 /* PORT0 PAD MODE CTRL */\n\t\t\t0x7c 0x0000007e /* PORT0_STATUS */\n\t\t>;\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tnvmem-cells = <&macaddr_info_8>;\n\tnvmem-cell-names = \"mac-address\";\n\tphy-mode = \"sgmii\";\n\tphy-handle = <&phy0>;\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n\tnvmem-cells = <&macaddr_info_8>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&info {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_info_8: macaddr@8 {\n\t\treg = <0x8 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9563_tplink_archer-c6-v2-us.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9563_tplink_archer-x6-v2.dtsi\"\n\n/ {\n\tcompatible = \"tplink,archer-c6-v2-us\", \"qca,qca9563\";\n\tmodel = \"TP-Link Archer C6 v2 (US) / A6 v2 (US/TW)\";\n\n\taliases {\n\t\tlabel-mac-device = &eth0;\n\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 6 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\twlan2g {\n\t\t\tlabel = \"green:wlan2g\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\n\t\twlan5g {\n\t\t\tlabel = \"green:wlan5g\";\n\t\t\tgpios = <&gpio 9 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\tlan {\n\t\t\tlabel = \"green:lan\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twan {\n\t\t\tlabel = \"green:wan\";\n\t\t\tgpios = <&gpio 8 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twan_fail {\n\t\t\tlabel = \"amber:wan\";\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&gpio 1 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"Reset button\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 5 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"WPS button\";\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tgpios = <&gpio 2 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"factory-boot\";\n\t\t\t\treg = <0x000000 0x020000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tinfo: partition@20000 {\n\t\t\t\tlabel = \"info\";\n\t\t\t\treg = <0x020000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x030000 0x020000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x050000 0xf80000>;\n\t\t\t};\n\n\t\t\tpartition@fd0000 {\n\t\t\t\tlabel = \"tplink\";\n\t\t\t\treg = <0xfd0000 0x020000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tart: partition@ff0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0xff0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&eth0 {\n\tnvmem-cells = <&macaddr_info_8>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wmac {\n\tmtd-cal-data = <&art 0x1000>;\n\n\tnvmem-cells = <&macaddr_info_8>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&info {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_info_8: macaddr@8 {\n\t\treg = <0x8 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9563_tplink_archer-c6-v2.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9563_tplink_archer-x6-v2.dtsi\"\n\n/ {\n\tcompatible = \"tplink,archer-c6-v2\", \"qca,qca9563\";\n\tmodel = \"TP-Link Archer C6 v2 (EU/RU/JP)\";\n\n\taliases {\n\t\tlabel-mac-device = &eth0;\n\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\twlan2g {\n\t\t\tlabel = \"green:wlan2g\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\n\t\twlan5g {\n\t\t\tlabel = \"green:wlan5g\";\n\t\t\tgpios = <&gpio 19 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\tlan {\n\t\t\tlabel = \"green:lan\";\n\t\t\tgpios = <&gpio 20 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twan {\n\t\t\tlabel = \"green:wan\";\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twan_fail {\n\t\t\tlabel = \"amber:wan\";\n\t\t\tgpios = <&gpio 8 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&gpio 9 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"Reset button\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 5 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"WPS button\";\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tgpios = <&gpio 6 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x020000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tinfo: partition@20000 {\n\t\t\t\tlabel = \"info\";\n\t\t\t\treg = <0x020000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x030000 0x7a0000>;\n\t\t\t};\n\n\t\t\tpartition@7d0000 {\n\t\t\t\tlabel = \"tplink\";\n\t\t\t\treg = <0x7d0000 0x020000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tart: partition@7f0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0x7f0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&eth0 {\n\tnvmem-cells = <&macaddr_info_8>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wmac {\n\tmtd-cal-data = <&art 0x1000>;\n\n\tnvmem-cells = <&macaddr_info_8>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&info {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_info_8: macaddr@8 {\n\t\treg = <0x8 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9563_tplink_archer-c7-v4.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca956x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"tplink,archer-c7-v4\", \"qca,qca9563\";\n\tmodel = \"TP-Link Archer C7 v4\";\n\n\taliases {\n\t\tled-boot = &led_system;\n\t\tled-failsafe = &led_system;\n\t\tled-running = &led_system;\n\t\tled-upgrade = &led_system;\n\t\tlabel-mac-device = &eth0;\n\t};\n\n\tled_spi {\n\t\tcompatible = \"spi-gpio\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tsck-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;\t// 74HC595 SRCLK (Serial Clock)\n\t\tmosi-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;\t// 74HC595 SER (Serial)\n\t\tcs-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\t\t// 74HC595 RCLK (Register Clock)\n\t\tnum-chipselects = <1>;\n\n\t\tled_gpio: led_gpio@0 {\n\t\t\tcompatible = \"fairchild,74hc595\";\n\t\t\treg = <0>;\n\t\t\tgpio-controller;\n\t\t\t#gpio-cells = <2>;\n\t\t\tregisters-number = <1>;\n\t\t\tspi-max-frequency = <10000000>;\n\t\t};\n\t};\n\n\tgpio-export {\n\t\tcompatible = \"gpio-export\";\n\n\t\tgpio_shift_register_oe {\n\t\t\tgpio-export,name = \"tp-link:oe:sr\";\n\t\t\tgpio-export,output = <0>;\n\t\t\tgpios = <&gpio 1 GPIO_ACTIVE_LOW>;\t// 74HC595 /OE (Output Enable)\n\t\t};\n\n\t\tgpio_shift_register_reset {\n\t\t\tgpio-export,name = \"tp-link:reset:sr\";\n\t\t\tgpio-export,output = <1>;\n\t\t\tgpios = <&gpio 21 GPIO_ACTIVE_LOW>;\t// 74HC595 /SRCLR (Serial Clear)\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_system: system {\n\t\t\tlabel = \"green:system\";\n\t\t\tgpios = <&gpio 6 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\tusb1 {\n\t\t\tlabel = \"green:usb1\";\n\t\t\tgpios = <&gpio 8 GPIO_ACTIVE_LOW>;\n\t\t\ttrigger-sources = <&hub_port1>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\n\t\tusb2 {\n\t\t\tlabel = \"green:usb2\";\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_LOW>;\n\t\t\ttrigger-sources = <&hub_port0>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\n\t\twlan5g {\n\t\t\tlabel = \"green:wlan5g\";\n\t\t\tgpios = <&gpio 9 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\twlan2g {\n\t\t\tlabel = \"green:wlan2g\";\n\t\t\tgpios = <&led_gpio 7 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\n\t\twan {\n\t\t\tlabel = \"green:wan\";\n\t\t\tgpios = <&led_gpio 5 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twan_fail {\n\t\t\tlabel = \"orange:wan\";\n\t\t\tgpios = <&led_gpio 6 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan1 {\n\t\t\tlabel = \"green:lan1\";\n\t\t\tgpios = <&led_gpio 4 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan2 {\n\t\t\tlabel = \"green:lan2\";\n\t\t\tgpios = <&led_gpio 3 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan3 {\n\t\t\tlabel = \"green:lan3\";\n\t\t\tgpios = <&led_gpio 2 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan4 {\n\t\t\tlabel = \"green:lan4\";\n\t\t\tgpios = <&led_gpio 1 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&led_gpio 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"Reset button\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 5 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"WPS button\";\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tgpios = <&gpio 2 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&usb_phy0 {\n\tstatus = \"okay\";\n};\n\n&usb0 {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\tstatus = \"okay\";\n\n\thub_port0: port@1 {\n\t\treg = <1>;\n\t\t#trigger-source-cells = <0>;\n\t};\n};\n\n&usb_phy1 {\n\tstatus = \"okay\";\n};\n\n&usb1 {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\tstatus = \"okay\";\n\n\thub_port1: port@1 {\n\t\treg = <1>;\n\t\t#trigger-source-cells = <0>;\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"factory-uboot\";\n\t\t\t\treg = <0x000000 0x020000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x020000 0x020000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x040000 0xec0000>;\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t};\n\n\t\t\tinfo: partition@f00000 {\n\t\t\t\tlabel = \"info\";\n\t\t\t\treg = <0xf00000 0x0f0000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tart: partition@ff0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0xff0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy-mask = <0>;\n\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t\tphy-mode = \"sgmii\";\n\t\tqca,mib-poll-interval = <500>;\n\n\t\tqca,ar8327-initvals = <\n\t\t\t0x04 0x80080080 /* PORT0 PAD MODE CTRL */\n\t\t\t0x7c 0x0000007e /* PORT0_STATUS */\n\t\t\t0x94 0x00000200 /* PORT6_STATUS */\n\t\t\t>;\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tpll-data = <0x03000101 0x00000101 0x00001919>;\n\n\tphy-mode = \"sgmii\";\n\tnvmem-cells = <&macaddr_info_8>;\n\tnvmem-cell-names = \"mac-address\";\n\tphy-handle = <&phy0>;\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n\tnvmem-cells = <&macaddr_info_8>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&info {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_info_8: macaddr@8 {\n\t\treg = <0x8 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9563_tplink_archer-c7-v5.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9563_tplink_archer-x7-v5.dtsi\"\n\n/ {\n\tcompatible = \"tplink,archer-c7-v5\", \"qca,qca9563\";\n\tmodel = \"TP-Link Archer C7 v5\";\n\n\taliases {\n\t\tlabel-mac-device = &eth0;\n\t};\n};\n\n&keys {\n\treset {\n\t\tlabel = \"Reset button\";\n\t\tlinux,code = <KEY_RESTART>;\n\t\tgpios = <&gpio 5 GPIO_ACTIVE_LOW>;\n\t\tdebounce-interval = <60>;\n\t};\n};\n\n&mtdparts {\n\tpartition@0 {\n\t\tlabel = \"factory-uboot\";\n\t\treg = <0x000000 0x020000>;\n\t\tread-only;\n\t};\n\n\tpartition@20000 {\n\t\tlabel = \"u-boot\";\n\t\treg = <0x020000 0x020000>;\n\t\tread-only;\n\t};\n\n\tpartition@40000 {\n\t\tlabel = \"partition-table\";\n\t\treg = <0x040000 0x010000>;\n\t\tread-only;\n\t};\n\n\tart: partition@50000 {\n\t\tlabel = \"art\";\n\t\treg = <0x050000 0x010000>;\n\t\tread-only;\n\t};\n\n\tinfo: partition@60000 {\n\t\tlabel = \"info\";\n\t\treg = <0x060000 0x020000>;\n\t\tread-only;\n\t};\n\n\tpartition@80000 {\n\t\tlabel = \"user-config\";\n\t\treg = <0x080000 0x040000>;\n\t\tread-only;\n\t};\n\n\tpartition@c0000 {\n\t\tlabel = \"firmware\";\n\t\treg = <0x0c0000 0xf00000>;\n\t\tcompatible = \"denx,uimage\";\n\t};\n\n\tpartition@ff0000 {\n\t\tlabel = \"default-config\";\n\t\treg = <0xff0000 0x010000>;\n\t\tread-only;\n\t};\n};\n\n&eth0 {\n\tnvmem-cells = <&macaddr_info_8>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wmac {\n\tmtd-cal-data = <&art 0x1000>;\n\n\tnvmem-cells = <&macaddr_info_8>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&info {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_info_8: macaddr@8 {\n\t\treg = <0x8 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9563_tplink_archer-x6-v2.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca956x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy-mask = <0>;\n\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t\tphy-mode = \"sgmii\";\n\t\tqca,mib-poll-interval = <500>;\n\n\t\tqca,ar8327-initvals = <\n\t\t\t0x04 0x00080080 /* PORT0 PAD MODE CTRL */\n\t\t\t0x7c 0x0000007e /* PORT0_STATUS */\n\t\t\t>;\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tphy-mode = \"sgmii\";\n\tphy-handle = <&phy0>;\n};\n\n&wmac {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9563_tplink_archer-x7-v5.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca956x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\taliases {\n\t\tled-boot = &led_system;\n\t\tled-failsafe = &led_system;\n\t\tled-running = &led_system;\n\t\tled-upgrade = &led_system;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_system: system {\n\t\t\tlabel = \"green:system\";\n\t\t\tgpios = <&gpio 6 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\tusb {\n\t\t\tlabel = \"green:usb\";\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_LOW>;\n\t\t\ttrigger-sources = <&hub_port0>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\n\t\twlan5g {\n\t\t\tlabel = \"green:wlan5g\";\n\t\t\tgpios = <&gpio 9 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\twlan2g {\n\t\t\tlabel = \"green:wlan2g\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\n\t\twan {\n\t\t\tlabel = \"green:wan\";\n\t\t\tgpios = <&gpio 21 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twan_fail {\n\t\t\tlabel = \"orange:wan\";\n\t\t\tgpios = <&gpio 20 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan1 {\n\t\t\tlabel = \"green:lan1\";\n\t\t\tgpios = <&gpio 8 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan2 {\n\t\t\tlabel = \"green:lan2\";\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan3 {\n\t\t\tlabel = \"green:lan3\";\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan4 {\n\t\t\tlabel = \"green:lan4\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&gpio 1 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys: keys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\twps {\n\t\t\tlabel = \"WPS button\";\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tgpios = <&gpio 2 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tgpio-export {\n\t\tcompatible = \"gpio-export\";\n\n\t\tgpio_usb_power {\n\t\t\tgpio-export,name = \"tp-link:power:usb\";\n\t\t\tgpio-export,output = <1>;\n\t\t\tgpios = <&gpio 19 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&usb_phy0 {\n\tstatus = \"okay\";\n};\n\n&usb0 {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\tstatus = \"okay\";\n\n\thub_port0: port@1 {\n\t\treg = <1>;\n\t\t#trigger-source-cells = <0>;\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tmtdparts: partitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\t\t};\n\t};\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy-mask = <0>;\n\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t\tphy-mode = \"sgmii\";\n\t\tqca,mib-poll-interval = <500>;\n\n\t\tqca,ar8327-initvals = <\n\t\t\t0x04 0x80080080 /* PORT0 PAD MODE CTRL */\n\t\t\t0x08 0x00000000 /* PORT5 PAD MODE CTRL */\n\t\t\t0x0c 0x00000000 /* PORT6 PAD MODE CTRL */\n\t\t\t0x10 0x00000080 /* POWER_ON_STRAP */\n\t\t\t0x7c 0x0000007e /* PORT0_STATUS */\n\t\t\t0x94 0x00000200 /* PORT6_STATUS */\n\t\t\t>;\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tpll-data = <0x03000101 0x00000101 0x00001919>;\n\n\tphy-mode = \"sgmii\";\n\tphy-handle = <&phy0>;\n};\n\n&wmac {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9563_tplink_cpe710-v1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca956x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"TP-Link CPE710 v1\";\n\tcompatible = \"tplink,cpe710-v1\", \"qca,qca9563\";\n\n\taliases {\n\t\tlabel-mac-device = &eth0;\n\t\tled-boot = &led_lan;\n\t\tled-failsafe = &led_lan;\n\t\tled-upgrade = &led_lan;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_lan: lan {\n\t\t\tlabel = \"blue:lan\";\n\t\t\tgpios = <&gpio 5 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan5g {\n\t\t\tlabel = \"blue:wlan5g\";\n\t\t\tgpios = <&gpio 1 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"Reset button\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 2 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <40000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x040000 0x010000>;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tlabel = \"partition-table\";\n\t\t\t\treg = <0x050000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tinfo: partition@60000 {\n\t\t\t\tlabel = \"info\";\n\t\t\t\treg = <0x060000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@70000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x070000 0xf50000>;\n\t\t\t};\n\n\t\t\tpartition@fc0000 {\n\t\t\t\tlabel = \"config\";\n\t\t\t\treg = <0xfc0000 0x030000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tart: partition@ff0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0xff0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pinmux {\n\tmdio_pins: mdio_pins {\n\t\t/* GPIO 10 as MDIO(0x20), GPIO 8 as MDC(0x21) */\n\t\tpinctrl-single,bits = <0x8 0x00200021 0x00ff00ff>;\n\t};\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&mdio_pins>;\n\n\tphy-mask = <0x10>;\n\n\tphy4: ethernet-phy@4 {\n\t\treg = <4>;\n\t\treset-gpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tphy-handle = <&phy4>;\n\tphy-mode = \"sgmii\";\n\n\tnvmem-cells = <&macaddr_info_8>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tqca956x-serdes-fixup;\n\n\tgmac-config {\n\t\tdevice = <&gmac>;\n\t};\n};\n\n&info {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_info_8: macaddr@8 {\n\t\treg = <0x8 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9563_tplink_deco-m4r-v1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n#include \"qca956x.dtsi\"\n\n/ {\n\tcompatible = \"tplink,deco-m4r-v1\", \"qca,qca9563\";\n\tmodel = \"TP-Link Deco M4R v1\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twlan2g {\n\t\t\tlabel = \"red:wlan2g\";\n\t\t\tgpios = <&gpio 1 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\t\t\n\t\tled_power: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\twlan5g {\n\t\t\tlabel = \"blue:wlan5g\";\n\t\t\tgpios = <&gpio 9 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\t};\n\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\t\t\n\t\treset {\n\t\t\tlabel = \"Reset button\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 2 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\tphy-mask = <0>;\n\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t\tphy-mode = \"sgmii\";\n\t\tqca,mib-poll-interval = <500>;\n\n\t\tqca,ar8327-initvals = <\n\t\t\t0x04 0x00080080 /* PORT0 PAD MODE CTRL */\n\t\t\t0x7c 0x0000007e /* PORT0_STATUS */\n\t\t\t>;\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\tnum-cs = <1>;\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\t\t\t\n\t\t\tuboot: partition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x080000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\t\n\t\t\tpartition@80000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x080000 0xe00000>;\n\t\t\t};\n\t\t\t\n\t\t\tpartition@e80000 {\n\t\t\t\tlabel = \"product-info\";\n\t\t\t\treg = <0xe80000 0x05000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tconfig: partition@e85000 {\n\t\t\t\tlabel = \"config\";\n\t\t\t\treg = <0xe85000 0x16b000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\t\n\t\t\tart: partition@ff0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0xff0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tphy-mode = \"sgmii\";\n\tphy-handle = <&phy0>;\n\t\n\tnvmem-cells = <&macaddr_config_8>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n\tnvmem-cells = <&macaddr_config_8>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&config {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_config_8: macaddr@8 {\n\t\treg = <0x8 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9563_tplink_eap225-outdoor-v1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9563_tplink_eap2x5-1port.dtsi\"\n\n/ {\n\tcompatible = \"tplink,eap225-outdoor-v1\", \"qca,qca9563\";\n\tmodel = \"TP-Link EAP225-Outdoor v1\";\n\n\taliases {\n\t\tled-boot = &led_status_green;\n\t\tled-failsafe = &led_status_amber;\n\t\tled-running = &led_status_green;\n\t\tled-upgrade = &led_status_amber;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_status_green: status_green {\n\t\t\tlabel = \"green:status\";\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\tled_status_amber: status_amber {\n\t\t\tlabel = \"amber:status\";\n\t\t\tgpios = <&gpio 9 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9563_tplink_eap225-v1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include <dt-bindings/leds/common.h>\n#include \"qca9563_tplink_eap2x5-1port.dtsi\"\n\n/ {\n\tcompatible = \"tplink,eap225-v1\", \"qca,qca9563\";\n\tmodel = \"TP-Link EAP225 v1\";\n\n\taliases {\n\t\tled-boot = &led_status_green;\n\t\tled-failsafe = &led_status_amber;\n\t\tled-running = &led_status_green;\n\t\tled-upgrade = &led_status_amber;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_status_green: led-0 {\n\t\t\tlabel = \"green:status\";\n\t\t\tcolor = <LED_COLOR_ID_GREEN>;\n\t\t\tfunction = LED_FUNCTION_STATUS;\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\tled_status_amber: led-1 {\n\t\t\tlabel = \"amber:status\";\n\t\t\tcolor = <LED_COLOR_ID_AMBER>;\n\t\t\tfunction = LED_FUNCTION_STATUS;\n\t\t\tgpios = <&gpio 9 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tled_status_red: led-2 {\n\t\t\tlabel = \"red:status\";\n\t\t\tcolor = <LED_COLOR_ID_RED>;\n\t\t\tfunction = LED_FUNCTION_STATUS;\n\t\t\tgpios = <&gpio 1 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n\n\tgpio-export {\n\t\tcompatible = \"gpio-export\";\n\t\tled_enable {\n\t\t\tgpio-export,name = \"leds:enable\";\n\t\t\tgpio-export,output = <1>;\n\t\t\tgpios = <&gpio 5 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9563_tplink_eap225-v3.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9563_tplink_eap2x5-1port.dtsi\"\n\n/ {\n\tcompatible = \"tplink,eap225-v3\", \"qca,qca9563\";\n\tmodel = \"TP-Link EAP225 v3\";\n\n\taliases {\n\t\tled-boot = &led_status_green;\n\t\tled-failsafe = &led_status_amber;\n\t\tled-running = &led_status_green;\n\t\tled-upgrade = &led_status_amber;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_status_green: status_green {\n\t\t\tlabel = \"green:status\";\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\tled_status_amber: status_amber {\n\t\t\tlabel = \"amber:status\";\n\t\t\tgpios = <&gpio 9 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9563_tplink_eap245-v1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9563_tplink_eap2x5-1port.dtsi\"\n\n/ {\n\tcompatible = \"tplink,eap245-v1\", \"qca,qca9563\";\n\tmodel = \"TP-Link EAP245 v1\";\n\n\taliases {\n\t\tled-boot = &led_status_green;\n\t\tled-failsafe = &led_status_amber;\n\t\tled-running = &led_status_green;\n\t\tled-upgrade = &led_status_amber;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_status_green: status_green {\n\t\t\tlabel = \"green:status\";\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\tled_status_amber: status_amber {\n\t\t\tlabel = \"amber:status\";\n\t\t\tgpios = <&gpio 9 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tled_status_red: status_red {\n\t\t\tlabel = \"red:status\";\n\t\t\tgpios = <&gpio 1 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n\n\tgpio-export {\n\t\tcompatible = \"gpio-export\";\n\t\tled_enable {\n\t\t\tgpio-export,name = \"leds:enable\";\n\t\t\tgpio-export,output = <1>;\n\t\t\tgpios = <&gpio 5 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9563_tplink_eap245-v3.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca956x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"tplink,eap245-v3\", \"qca,qca9563\";\n\tmodel = \"TP-Link EAP245 v3 / EAP265 HD v1\";\n\n\taliases {\n\t\tled-boot = &led_status_green;\n\t\tled-failsafe = &led_status_amber;\n\t\tled-running = &led_status_green;\n\t\tled-upgrade = &led_status_amber;\n\t\tlabel-mac-device = &eth0;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_status_green: status_green {\n\t\t\tlabel = \"green:status\";\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\tled_status_amber: status_amber {\n\t\t\tlabel = \"amber:status\";\n\t\t\tgpios = <&gpio 9 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"Reset button\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 2 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"factory-boot\";\n\t\t\t\treg = <0x000000 0x040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x040000 0x040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@80000 {\n\t\t\t\tlabel = \"partition-table\";\n\t\t\t\treg = <0x080000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tinfo: partition@90000 {\n\t\t\t\tlabel = \"info\";\n\t\t\t\treg = <0x090000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tart: partition@a0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0x0a0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@b0000 {\n\t\t\t\tlabel = \"extra-para\";\n\t\t\t\treg = <0x0b0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@c0000 {\n\t\t\t\tcompatible = \"openwrt,elf\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x0c0000 0xe40000>;\n\t\t\t};\n\n\t\t\tpartition@f00000 {\n\t\t\t\tlabel = \"config\";\n\t\t\t\treg = <0xf00000 0x030000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@f30000 {\n\t\t\t\tlabel = \"mutil-log\";\n\t\t\t\treg = <0xf30000 0x080000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@fb0000 {\n\t\t\t\tlabel = \"oops\";\n\t\t\t\treg = <0xfb0000 0x040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy-mask = <0x1>;\n\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t\tphy-mode = \"sgmii\";\n\t\tqca,ar8327-initvals = <\n\t\t\t0x04 0x00080080 /* PAD0 */\n\t\t\t0x7c 0x0000007e /* PORT0_STATUS */\n\t\t\t0xe0 0xc74164de /* SGMII_CTRL */\n\t\t\t>;\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\";\n\n\tnvmem-cells = <&macaddr_info_8>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n\tnvmem-cells = <&macaddr_info_8>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&info {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_info_8: macaddr@8 {\n\t\treg = <0x8 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9563_tplink_eap2x5-1port.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca956x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\taliases {\n\t\tlabel-mac-device = &eth0;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"Reset button\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 2 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x020000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tlabel = \"partition-table\";\n\t\t\t\treg = <0x020000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tinfo: partition@30000 {\n\t\t\t\tlabel = \"info\";\n\t\t\t\treg = <0x030000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tcompatible = \"openwrt,elf\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x040000 0xd80000>;\n\t\t\t};\n\n\t\t\tpartition@dc0000 {\n\t\t\t\tlabel = \"config\";\n\t\t\t\treg = <0xdc0000 0x030000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\t/* df0000-f30000 undefined in vendor firmware */\n\n\t\t\tpartition@f30000 {\n\t\t\t\tlabel = \"log\";\n\t\t\t\treg = <0xf30000 0x0c0000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tart: partition@ff0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0xff0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pinmux {\n\tmdio_pins: mdio_pins {\n\t\t/* GPIO 10 as MDIO(0x20), GPIO 8 as MDC(0x21) */\n\t\tpinctrl-single,bits = <0x8 0x00200021 0x00ff00ff>;\n\t};\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&mdio_pins>;\n\n\tphy-mask = <0x10>;\n\n\tphy4: ethernet-phy@4 {\n\t\treg = <4>;\n\t\treset-gpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tphy-handle = <&phy4>;\n\tphy-mode = \"sgmii\";\n\tpll-data = <0x03000000 0x00000101 0x00001313>;\n\n\tnvmem-cells = <&macaddr_info_8>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tqca956x-serdes-fixup;\n\n\tgmac-config {\n\t\tdevice = <&gmac>;\n\t};\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n\tnvmem-cells = <&macaddr_info_8>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&info {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_info_8: macaddr@8 {\n\t\treg = <0x8 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9563_tplink_re450-v2.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9563_tplink_re450.dtsi\"\n\n/ {\n\tcompatible = \"tplink,re450-v2\", \"qca,qca9563\";\n\tmodel = \"TP-Link RE450 v2\";\n\n\taliases {\n\t\tlabel-mac-device = &eth0;\n\t};\n};\n\n&partitions {\n\tpartition@0 {\n\t\tlabel = \"u-boot\";\n\t\treg = <0x000000 0x020000>;\n\t\tread-only;\n\t};\n\n\tpartition@20000 {\n\t\tcompatible = \"tplink,firmware\";\n\t\tlabel = \"firmware\";\n\t\treg = <0x020000 0x5e0000>;\n\t};\n\n\tpartition@600000 {\n\t\tlabel = \"partition-table\";\n\t\treg = <0x600000 0x010000>;\n\t\tread-only;\n\t};\n\n\tinfo: partition@610000 {\n\t\tlabel = \"info\";\n\t\treg = <0x610000 0x020000>;\n\t\tread-only;\n\t};\n\n\tpartition@630000 {\n\t\tlabel = \"config\";\n\t\treg = <0x630000 0x020000>;\n\t\tread-only;\n\t};\n\n\tart: partition@7f0000 {\n\t\tlabel = \"art\";\n\t\treg = <0x7f0000 0x010000>;\n\t\tread-only;\n\t};\n};\n\n&eth0 {\n\tnvmem-cells = <&macaddr_info_8>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wmac {\n\tmtd-cal-data = <&art 0x1000>;\n\n\tnvmem-cells = <&macaddr_info_8>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&info {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_info_8: macaddr@8 {\n\t\treg = <0x8 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9563_tplink_re450-v3.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9563_tplink_re450.dtsi\"\n\n/ {\n\tcompatible = \"tplink,re450-v3\", \"qca,qca9563\";\n\tmodel = \"TP-Link RE450 v3\";\n\n\taliases {\n\t\tlabel-mac-device = &eth0;\n\t};\n};\n\n&partitions {\n\tpartition@0 {\n\t\tlabel = \"u-boot\";\n\t\treg = <0x000000 0x020000>;\n\t\tread-only;\n\t};\n\n\tinfo: partition@20000 {\n\t\tlabel = \"info\";\n\t\treg = <0x020000 0x002000>;\n\t\tread-only;\n\t};\n\n\tpartition@22000 {\n\t\tlabel = \"partition-table\";\n\t\treg = <0x022000 0x002000>;\n\t\tread-only;\n\t};\n\n\tpartition@24000 {\n\t\tlabel = \"info2\";\n\t\treg = <0x024000 0x00a000>;\n\t\tread-only;\n\t};\n\n\tpartition@2e000 {\n\t\tlabel = \"config\";\n\t\treg = <0x02e000 0x022000>;\n\t\tread-only;\n\t};\n\n\tpartition@50000 {\n\t\tcompatible = \"tplink,firmware\";\n\t\tlabel = \"firmware\";\n\t\treg = <0x050000 0x7a0000>;\n\t};\n\n\tart: partition@7f0000 {\n\t\tlabel = \"art\";\n\t\treg = <0x7f0000 0x010000>;\n\t\tread-only;\n\t};\n};\n\n&eth0 {\n\tnvmem-cells = <&macaddr_info_8>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wmac {\n\tmtd-cal-data = <&art 0x1000>;\n\n\tnvmem-cells = <&macaddr_info_8>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&info {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_info_8: macaddr@8 {\n\t\treg = <0x8 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9563_tplink_re450.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca956x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t\tmdio-gpio0 = &mdio2;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"blue:power\";\n\t\t\tgpios = <&gpio 1 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan2g {\n\t\t\tlabel = \"blue:wlan2g\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\n\t\twlan5g {\n\t\t\tlabel = \"blue:wlan5g\";\n\t\t\tgpios = <&gpio 5 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\tlan_link {\n\t\t\tlabel = \"green:lan_link\";\n\t\t\tgpios = <&gpio 8 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan_data {\n\t\t\tlabel = \"green:lan_data\";\n\t\t\tgpios = <&gpio 9 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twps_blue {\n\t\t\tlabel = \"blue:wps\";\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\twps_red {\n\t\t\tlabel = \"red:wps\";\n\t\t\tgpios = <&gpio 20 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"Reset button\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 6 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\tpower {\n\t\t\tlabel = \"Power button\";\n\t\t\tlinux,code = <KEY_POWER>;\n\t\t\tgpios = <&gpio 2 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\tleds {\n\t\t\tlabel = \"LED control button\";\n\t\t\tlinux,code = <BTN_0>;\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"WPS button\";\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tgpios = <&gpio 19 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tmdio2: mdio {\n\t\tcompatible = \"virtual,mdio-gpio\";\n\n\t\tgpios = <&gpio 3 GPIO_ACTIVE_HIGH>, /* MDC */\n\t\t\t<&gpio 4 GPIO_ACTIVE_HIGH>; /* MDIO */\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tphy4: ethernet-phy@4 {\n\t\t\treg = <4>;\n\t\t\tdevice_type = \"ethernet-phy\";\n\t\t\treset-gpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions: partitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\t\t};\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tphy-mode = \"sgmii\";\n\tphy-handle = <&phy4>;\n};\n\n&wmac {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9563_tplink_re455-v1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9563_tplink_re450.dtsi\"\n\n/ {\n\tcompatible = \"tplink,re455-v1\", \"qca,qca9563\";\n\tmodel = \"TP-Link RE455 v1\";\n\n\taliases {\n\t\tlabel-mac-device = &eth0;\n\t};\n};\n\n&partitions {\n\tpartition@0 {\n\t\tlabel = \"u-boot\";\n\t\treg = <0x000000 0x020000>;\n\t\tread-only;\n\t};\n\n\tinfo: partition@20000 {\n\t\tlabel = \"info\";\n\t\treg = <0x020000 0x002000>;\n\t\tread-only;\n\t};\n\n\tpartition@22000 {\n\t\tlabel = \"partition-table\";\n\t\treg = <0x022000 0x002000>;\n\t\tread-only;\n\t};\n\n\tpartition@24000 {\n\t\tlabel = \"info2\";\n\t\treg = <0x024000 0x00a000>;\n\t\tread-only;\n\t};\n\n\tpartition@2e000 {\n\t\tlabel = \"config\";\n\t\treg = <0x02e000 0x022000>;\n\t\tread-only;\n\t};\n\n\tpartition@50000 {\n\t\tcompatible = \"tplink,firmware\";\n\t\tlabel = \"firmware\";\n\t\treg = <0x050000 0x7a0000>;\n\t};\n\n\tart: partition@7f0000 {\n\t\tlabel = \"art\";\n\t\treg = <0x7f0000 0x010000>;\n\t\tread-only;\n\t};\n};\n\n&eth0 {\n\tnvmem-cells = <&macaddr_info_8>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wmac {\n\tmtd-cal-data = <&art 0x1000>;\n\n\tnvmem-cells = <&macaddr_info_8>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&info {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_info_8: macaddr@8 {\n\t\treg = <0x8 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9563_tplink_tl-wa1201-v2.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca956x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"tplink,tl-wa1201-v2\", \"qca,qca9563\";\n\tmodel = \"TP-Link TL-WA1201 v2\";\n\n\taliases {\n\t\tlabel-mac-device = &eth0;\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t\tmdio-gpio0 = &mdio2;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\twlan2g {\n\t\t\tlabel = \"green:wlan2g\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\n\t\twlan5g {\n\t\t\tlabel = \"green:wlan5g\";\n\t\t\tgpios = <&gpio 19 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\tlan {\n\t\t\tlabel = \"green:lan\";\n\t\t\tgpios = <&gpio 20 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"Reset button\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 5 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"WPS button\";\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tgpios = <&gpio 6 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tmdio2: mdio {\n\t\tcompatible = \"virtual,mdio-gpio\";\n\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tgpios = <&gpio 3 GPIO_ACTIVE_HIGH>, /* MDC */\n\t\t\t<&gpio 4 GPIO_ACTIVE_HIGH>; /* MDIO */\n\n\t\tphy4: ethernet-phy@4 {\n\t\t\treg = <4>;\n\n\t\t\teee-broken-100tx;\n\t\t\teee-broken-1000t;\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tphy-mode = \"sgmii\";\n\tphy-handle = <&phy4>;\n\n\tnvmem-cells = <&macaddr_info_8>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n\n\tnvmem-cells = <&macaddr_info_8>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x020000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tinfo: partition@20000 {\n\t\t\t\tlabel = \"info\";\n\t\t\t\treg = <0x020000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x030000 0xce0000>;\n\t\t\t};\n\n\t\t\tpartition@d10000 {\n\t\t\t\tlabel = \"tplink\";\n\t\t\t\treg = <0xd10000 0x2e0000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tart: partition@ff0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0xff0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&info {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_info_8: macaddr@8 {\n\t\treg = <0x8 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9563_tplink_tl-wpa8630-v1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9563_tplink_tl-wpa8630.dtsi\"\n\n/ {\n\tcompatible = \"tplink,tl-wpa8630-v1\", \"qca,qca9563\";\n\tmodel = \"TP-Link TL-WPA8630 v1\";\n\n\taliases {\n\t\tlabel-mac-device = &eth0;\n\t};\n};\n\n&partitions {\n\tuboot: partition@0 {\n\t\tlabel = \"u-boot\";\n\t\treg = <0x000000 0x010000>;\n\t\tread-only;\n\t};\n\n\tpartition@10000 {\n\t\tcompatible = \"tplink,firmware\";\n\t\tlabel = \"firmware\";\n\t\treg = <0x010000 0x7d0000>;\n\t};\n\n\tpartition@7e0000 {\n\t\tlabel = \"mib0\";\n\t\treg = <0x7e0000 0x010000>;\n\t\tread-only;\n\t};\n\n\tart: partition@7f0000 {\n\t\tlabel = \"art\";\n\t\treg = <0x7f0000 0x010000>;\n\t\tread-only;\n\t};\n};\n\n&eth0 {\n\tnvmem-cells = <&macaddr_uboot_fc00>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wmac {\n\tmtd-cal-data = <&art 0x1000>;\n\n\tnvmem-cells = <&macaddr_uboot_fc00>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&uboot {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_uboot_fc00: macaddr@fc00 {\n\t\treg = <0xfc00 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9563_tplink_tl-wpa8630.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca956x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"Reset button\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 2 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\tleds {\n\t\t\tlabel = \"LED control button\";\n\t\t\tlinux,code = <KEY_LIGHTS_TOGGLE>;\n\t\t\tgpios = <&gpio 6 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\tpair {\n\t\t\tlabel = \"Pair button\";\n\t\t\tlinux,code = <BTN_1>;\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\twifi {\n\t\t\tlabel = \"WiFi button\";\n\t\t\tlinux,code = <KEY_RFKILL>;\n\t\t\tgpios = <&gpio 8 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 1 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan {\n\t\t\tlabel = \"green:lan\";\n\t\t\tgpios = <&gpio 5 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twifi2g {\n\t\t\tlabel = \"green:wifi2g\";\n\t\t\tgpios = <&gpio 19 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\n\t\twifi5g {\n\t\t\tlabel = \"green:wifi5g\";\n\t\t\tgpios = <&gpio 21 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\t};\n\n\tgpio-export {\n\t\tcompatible = \"gpio-export\";\n\n\t\tled_control {\n\t\t\tgpio-export,name = \"tp-link:led:control\";\n\t\t\tgpio-export,output = <0>;\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions: partitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy-mask = <0>;\n\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t\tphy-mode = \"sgmii\";\n\t\tqca,mib-poll-interval = <500>;\n\n\t\tqca,ar8327-initvals = <\n\t\t\t0x04 0x00080080 /* PORT0 PAD MODE CTRL */\n\t\t\t0x7c 0x0000007e /* PORT0_STATUS */\n\t\t>;\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tphy-handle = <&phy0>;\n\tphy-mode = \"sgmii\";\n};\n\n&wmac {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9563_tplink_tl-wpa8630p-v2-int.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9563_tplink_tl-wpa8630.dtsi\"\n\n/ {\n\tcompatible = \"tplink,tl-wpa8630p-v2-int\", \"qca,qca9563\";\n\tmodel = \"TP-Link WPA8630P v2 (Int.)\";\n\n\taliases {\n\t\tlabel-mac-device = &eth0;\n\t};\n};\n\n&partitions {\n\tpartition@0 {\n\t\tlabel = \"factory-uboot\";\n\t\treg = <0x000000 0x020000>;\n\t\tread-only;\n\t};\n\n\tpartition@20000 {\n\t\tlabel = \"u-boot\";\n\t\treg = <0x020000 0x020000>;\n\t\tread-only;\n\t};\n\n\tpartition@40000 {\n\t\tcompatible = \"tplink,firmware\";\n\t\tlabel = \"firmware\";\n\t\treg = <0x040000 0x5e0000>;\n\t};\n\n\tpartition@620000 {\n\t\tlabel = \"partition-table\";\n\t\treg = <0x620000 0x010000>;\n\t\tread-only;\n\t};\n\n\tpartition@630000 {\n\t\tlabel = \"tplink\";\n\t\treg = <0x630000 0x1b0000>;\n\t\tread-only;\n\t};\n\n\tinfo: partition@7e0000 {\n\t\tlabel = \"info\";\n\t\treg = <0x7e0000 0x010000>;\n\t\tread-only;\n\t};\n\n\tart: partition@7f0000 {\n\t\tlabel = \"art\";\n\t\treg = <0x7f0000 0x010000>;\n\t\tread-only;\n\t};\n};\n\n&eth0 {\n\tnvmem-cells = <&macaddr_info_8>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wmac {\n\tmtd-cal-data = <&art 0x1000>;\n\n\tnvmem-cells = <&macaddr_info_8>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&info {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_info_8: macaddr@8 {\n\t\treg = <0x8 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9563_tplink_tl-wpa8630p-v2.0-eu.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9563_tplink_tl-wpa8630.dtsi\"\n\n/ {\n\tcompatible = \"tplink,tl-wpa8630p-v2.0-eu\", \"qca,qca9563\";\n\tmodel = \"TP-Link WPA8630P v2.0 (EU)\";\n\n\taliases {\n\t\tlabel-mac-device = &eth0;\n\t};\n};\n\n&partitions {\n\tpartition@0 {\n\t\tlabel = \"factory-uboot\";\n\t\treg = <0x000000 0x020000>;\n\t\tread-only;\n\t};\n\n\tpartition@20000 {\n\t\tlabel = \"u-boot\";\n\t\treg = <0x020000 0x020000>;\n\t\tread-only;\n\t};\n\n\tpartition@40000 {\n\t\tcompatible = \"tplink,firmware\";\n\t\tlabel = \"firmware\";\n\t\treg = <0x040000 0x5e0000>;\n\t};\n\n\tpartition@620000 {\n\t\tlabel = \"partition-table\";\n\t\treg = <0x620000 0x010000>;\n\t\tread-only;\n\t};\n\n\tinfo: partition@630000 {\n\t\tlabel = \"info\";\n\t\treg = <0x630000 0x010000>;\n\t\tread-only;\n\t};\n\n\tpartition@640000 {\n\t\tlabel = \"tplink\";\n\t\treg = <0x640000 0x1b0000>;\n\t\tread-only;\n\t};\n\n\tart: partition@7f0000 {\n\t\tlabel = \"art\";\n\t\treg = <0x7f0000 0x010000>;\n\t\tread-only;\n\t};\n};\n\n&eth0 {\n\tnvmem-cells = <&macaddr_info_8>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wmac {\n\tmtd-cal-data = <&art 0x1000>;\n\n\tnvmem-cells = <&macaddr_info_8>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&info {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_info_8: macaddr@8 {\n\t\treg = <0x8 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9563_tplink_tl-wpa8630p-v2.1-eu.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9563_tplink_tl-wpa8630.dtsi\"\n\n/ {\n\tcompatible = \"tplink,tl-wpa8630p-v2.1-eu\", \"qca,qca9563\";\n\tmodel = \"TP-Link WPA8630P v2.1 (EU)\";\n\n\taliases {\n\t\tlabel-mac-device = &eth0;\n\t};\n};\n\n&partitions {\n\tpartition@0 {\n\t\tlabel = \"factory-uboot\";\n\t\treg = <0x000000 0x020000>;\n\t\tread-only;\n\t};\n\n\tpartition@20000 {\n\t\tlabel = \"u-boot\";\n\t\treg = <0x020000 0x020000>;\n\t\tread-only;\n\t};\n\n\tpartition@40000 {\n\t\tcompatible = \"tplink,firmware\";\n\t\tlabel = \"firmware\";\n\t\treg = <0x040000 0x5e0000>;\n\t};\n\n\t/* 0x620000 to 0x680000 is empty in OEM partitioning */\n\n\tpartition@680000 {\n\t\tlabel = \"tplink\";\n\t\treg = <0x680000 0x160000>;\n\t\tread-only;\n\t};\n\n\tinfo: partition@7e0000 {\n\t\tlabel = \"info\";\n\t\treg = <0x7e0000 0x010000>;\n\t\tread-only;\n\t};\n\n\tart: partition@7f0000 {\n\t\tlabel = \"art\";\n\t\treg = <0x7f0000 0x010000>;\n\t\tread-only;\n\t};\n};\n\n&eth0 {\n\tnvmem-cells = <&macaddr_info_8>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wmac {\n\tmtd-cal-data = <&art 0x1000>;\n\n\tnvmem-cells = <&macaddr_info_8>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&info {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_info_8: macaddr@8 {\n\t\treg = <0x8 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9563_tplink_tl-wr1043n-v5.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9563_tplink_tl-wr1043n.dtsi\"\n\n/ {\n\tcompatible = \"tplink,tl-wr1043n-v5\", \"qca,qca9563\";\n\tmodel = \"TP-Link TL-WR1043N v5\";\n\n\taliases {\n\t\tlabel-mac-device = &wmac;\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"factory-uboot\";\n\t\t\t\treg = <0x000000 0x020000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x020000 0x020000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x040000 0xec0000>;\n\t\t\t};\n\n\t\t\tinfo: partition@f00000 {\n\t\t\t\tlabel = \"info\";\n\t\t\t\treg = <0xf00000 0x020000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@f20000 {\n\t\t\t\tlabel = \"config\";\n\t\t\t\treg = <0xf20000 0x0a0000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@fc0000 {\n\t\t\t\tlabel = \"partition-table\";\n\t\t\t\treg = <0xfc0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@fd0000 {\n\t\t\t\tlabel = \"logs\";\n\t\t\t\treg = <0xfd0000 0x020000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tart: partition@ff0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0xff0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&eth0 {\n\tnvmem-cells = <&macaddr_info_8>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wmac {\n\tmtd-cal-data = <&art 0x1000>;\n\n\tnvmem-cells = <&macaddr_info_8>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&info {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_info_8: macaddr@8 {\n\t\treg = <0x8 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9563_tplink_tl-wr1043n.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca956x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\taliases {\n\t\tled-boot = &led_system;\n\t\tled-failsafe = &led_system;\n\t\tled-running = &led_system;\n\t\tled-upgrade = &led_system;\n\t};\n\n\tleds: leds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_system: system {\n\t\t\tlabel = \"green:system\";\n\t\t\tgpios = <&gpio 6 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"heartbeat\";\n\t\t};\n\n\t\twifi_green {\n\t\t\tlabel = \"green:wlan\";\n\t\t\tgpios = <&gpio 19 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\twifi_wps {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&gpio 1 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twan {\n\t\t\tlabel = \"green:wan\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twan_fail {\n\t\t\tlabel = \"orange:wan\";\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan1 {\n\t\t\tlabel = \"green:lan1\";\n\t\t\tgpios = <&gpio 9 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan2 {\n\t\t\tlabel = \"green:lan2\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan3 {\n\t\t\tlabel = \"green:lan3\";\n\t\t\tgpios = <&gpio 21 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan4 {\n\t\t\tlabel = \"green:lan4\";\n\t\t\tgpios = <&gpio 20 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"Reset button\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 2 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\twifi {\n\t\t\tlabel = \"RFKILL button\";\n\t\t\tlinux,code = <KEY_RFKILL>;\n\t\t\tgpios = <&gpio 5 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy-mask = <0>;\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t\tphy-mode = \"sgmii\";\n\t\tqca,mib-poll-interval = <500>;\n\n\t\tqca,ar8327-initvals = <\n\t\t\t0x04 0x00080080 /* PORT0 PAD MODE CTRL */\n\t\t\t0x7c 0x0000007e /* PORT0_STATUS */\n\t\t>;\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tphy-mode = \"sgmii\";\n\tphy-handle = <&phy0>;\n};\n\n&wmac {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9563_tplink_tl-wr1043nd-v4.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9563_tplink_tl-wr1043n.dtsi\"\n\n/ {\n\tcompatible = \"tplink,tl-wr1043nd-v4\", \"qca,qca9563\";\n\tmodel = \"TP-Link TL-WR1043ND v4\";\n\n\taliases {\n\t\tlabel-mac-device = &wmac;\n\t};\n\n\tgpio-export {\n\t\tcompatible = \"gpio-export\";\n\t\t#size-cells = <0>;\n\n\t\tgpio_usb_power {\n\t\t\tgpio-export,name = \"tp-link:power:usb\";\n\t\t\tgpio-export,output = <1>;\n\t\t\tgpios = <&gpio 8 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x020000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tcompatible = \"tplink,firmware\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x020000 0xf30000>;\n\t\t\t};\n\n\t\t\tinfo: partition@f50000 {\n\t\t\t\tlabel = \"info\";\n\t\t\t\treg = <0xf50000 0x020000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@f70000 {\n\t\t\t\tlabel = \"config\";\n\t\t\t\treg = <0xf70000 0x050000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@fc0000 {\n\t\t\t\tlabel = \"partition-table\";\n\t\t\t\treg = <0xfc0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@fd0000 {\n\t\t\t\tlabel = \"logs\";\n\t\t\t\treg = <0xfd0000 0x020000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tart: partition@ff0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0xff0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&leds {\n\tusb {\n\t\tlabel = \"green:usb\";\n\t\tgpios = <&gpio 7 GPIO_ACTIVE_LOW>;\n\t\ttrigger-sources = <&hub_port0>;\n\t\tlinux,default-trigger = \"usbport\";\n\t};\n};\n\n&usb_phy0 {\n\tstatus = \"okay\";\n};\n\n&usb0 {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\tstatus = \"okay\";\n\n\thub_port0: port@1 {\n\t\treg = <1>;\n\t\t#trigger-source-cells = <0>;\n\t};\n};\n\n&eth0 {\n\tnvmem-cells = <&macaddr_info_8>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wmac {\n\tmtd-cal-data = <&art 0x1000>;\n\n\tnvmem-cells = <&macaddr_info_8>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&info {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_info_8: macaddr@8 {\n\t\treg = <0x8 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9563_ubnt_unifiac-lite.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9563_ubnt_unifiac-lite.dtsi\"\n\n/ {\n\tcompatible = \"ubnt,unifiac-lite\", \"qca,qca9563\";\n\tmodel = \"Ubiquiti UniFi AC Lite\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9563_ubnt_unifiac-lite.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9563_ubnt_unifiac.dtsi\"\n\n/ {\n\taliases {\n\t\tlabel-mac-device = &eth0;\n\t};\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy-mask = <4>;\n\tphy4: ethernet-phy@4 {\n\t\tphy-mode = \"sgmii\";\n\t\treg = <4>;\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n\tphy-mode = \"sgmii\";\n\tphy-handle = <&phy4>;\n\n\tpll-data = <0x03000000 0x00000101 0x00001313>;\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9563_ubnt_unifiac-lr.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9563_ubnt_unifiac-lite.dtsi\"\n\n/ {\n\tcompatible = \"ubnt,unifiac-lr\", \"qca,qca9563\";\n\tmodel = \"Ubiquiti UniFi AC LR\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9563_ubnt_unifiac-mesh-pro.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9563_ubnt_unifiac-pro.dtsi\"\n\n/ {\n\tcompatible = \"ubnt,unifiac-mesh-pro\", \"qca,qca9563\";\n\tmodel = \"Ubiquiti UniFi AC Mesh Pro\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9563_ubnt_unifiac-mesh.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9563_ubnt_unifiac-lite.dtsi\"\n\n/ {\n\tcompatible = \"ubnt,unifiac-mesh\", \"qca,qca9563\";\n\tmodel = \"Ubiquiti UniFi AC Mesh\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9563_ubnt_unifiac-pro.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9563_ubnt_unifiac-pro.dtsi\"\n\n/ {\n\tcompatible = \"ubnt,unifiac-pro\", \"qca,qca9563\";\n\tmodel = \"Ubiquiti UniFi AC Pro\";\n};\n\n&usb_phy0 {\n\tstatus = \"okay\";\n};\n\n&usb0 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9563_ubnt_unifiac-pro.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9563_ubnt_unifiac.dtsi\"\n\n/ {\n\taliases {\n\t\tlabel-mac-device = &eth0;\n\t};\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\tphy-mask = <0>;\n\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t\tphy-mode = \"sgmii\";\n\t\tqca,ar8327-initvals = <\n\t\t\t0x04 0x00080080 /* PORT0 PAD MODE CTRL */\n\t\t\t0x7c 0x0000007e /* PORT0_STATUS */\n\t\t>;\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n\tphy-handle = <&phy0>;\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9563_ubnt_unifiac.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca956x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\taliases {\n\t\tled-boot = &led_white;\n\t\tled-failsafe = &led_white;\n\t\tled-running = &led_blue;\n\t\tled-upgrade = &led_blue;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_white: led_white {\n\t\t\tlabel = \"white:dome\";\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tled_blue: led_blue {\n\t\t\tlabel = \"blue:dome\";\n\t\t\tgpios = <&gpio 8 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"Reset button\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 2 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x060000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@60000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x060000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@70000 {\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x070000 0x790000>;\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t};\n\n\t\t\tpartition@800000 {\n\t\t\t\tlabel = \"kernel1\";\n\t\t\t\treg = <0x800000 0x790000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@f90000 {\n\t\t\t\tlabel = \"bs\";\n\t\t\t\treg = <0xf90000 0x020000>;\n\t\t\t};\n\n\t\t\tpartition@fb0000 {\n\t\t\t\tlabel = \"cfg\";\n\t\t\t\treg = <0xfb0000 0x040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tart: partition@ff0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0xff0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9563_xiaomi_aiot-ac2350.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca956x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"Xiaomi AIoT AC2350\";\n\tcompatible = \"xiaomi,aiot-ac2350\", \"qca,qca9563\";\n\n\taliases {\n\t\tlabel-mac-device = &eth0;\n\n\t\tled-boot = &led_system_orange;\n\t\tled-failsafe = &led_system_orange;\n\t\tled-running = &led_system_blue;\n\t\tled-upgrade = &led_system_orange;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 2 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_system_blue: system_blue {\n\t\t\tlabel = \"blue:system\";\n\t\t\tgpios = <&gpio 5 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_system_orange: system_orange {\n\t\t\tlabel = \"orange:system\";\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twan_blue {\n\t\t\tlabel = \"blue:wan\";\n\t\t\tgpios = <&gpio 8 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twan_orange {\n\t\t\tlabel = \"orange:wan\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tgpio-export {\n\t\tcompatible = \"gpio-export\";\n\n\t\twps {\n\t\t\tgpio-export,name = \"wps\";\n\t\t\tgpio-export,output = <0>;\n\t\t\tgpios = <&gpio 1 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tusb-reset {\n\t\t\tgpio-export,name = \"usb-reset\";\n\t\t\tgpio-export,output = <0>;\n\t\t\tgpios = <&gpio 19 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <50000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"Bootloader\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"Nvram\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"Bdata\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tlabel = \"crash\";\n\t\t\t\treg = <0x50000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tart: partition@60000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0x60000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@70000 {\n\t\t\t\tlabel = \"cfg_bak\";\n\t\t\t\treg = <0x70000 0x20000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@90000 {\n\t\t\t\tlabel = \"overlay\";\n\t\t\t\treg = <0x90000 0x170000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@200000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x200000 0xe00000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy-mask = <0x1>;\n\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t\tphy-mode = \"sgmii\";\n\n\t\tqca,ar8327-initvals = <\n\t\t\t0x04 0x00000080 /* PORT0 PAD MODE CTRL */\n\t\t\t0x08 0x01000000 /* PORT5 PAD MODE CTRL */\n\t\t\t0x0c 0x00000000 /* PORT6 PAD MODE CTRL */\n\t\t\t0x10 0x602613a0 /* POWER_ON_STRAP */\n\t\t\t0x50 0xcf35cf35 /* LED_CTRL0 */\n\t\t\t0x54 0xca35ca35 /* LED_CTRL1 */\n\t\t\t0x58 0xc935c935 /* LED_CTRL2 */\n\t\t\t0x5c 0x03ffff00 /* LED_CTRL3 */\n\t\t\t0x7c 0x000000fe /* PORT0_STATUS */\n\t\t\t0x94 0x000010c2 /* PORT6_STATUS */\n\t\t\t0xe0 0xc74164de /* SGMII_CTRL */\n\t\t>;\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tphy-mode = \"sgmii\";\n\tphy-handle = <&phy0>;\n\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9563_yuncore_a782.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9563_yuncore_xd4200.dtsi\"\n\n/ {\n\tcompatible = \"yuncore,a782\", \"qca,qca9563\";\n\tmodel = \"YunCore A782\";\n\n\taliases {\n\t\tled-boot = &led_system;\n\t\tled-failsafe = &led_system;\n\t\tled-running = &led_system;\n\t\tled-upgrade = &led_system;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_system: system {\n\t\t\tlabel = \"red:system\";\n\t\t\tgpios = <&gpio 1 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"keep\";\n\t\t};\n\n\t\twlan2g {\n\t\t\tlabel = \"green:wlan2g\";\n\t\t\tgpios = <&gpio 19 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9563_yuncore_xd3200.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9563_yuncore_xd4200.dtsi\"\n\n/ {\n\tcompatible = \"yuncore,xd3200\", \"qca,qca9563\";\n\tmodel = \"YunCore XD3200\";\n\n\taliases {\n\t\tlabel-mac-device = &eth0;\n\t\tled-boot = &led_system;\n\t\tled-failsafe = &led_system;\n\t\tled-running = &led_system;\n\t\tled-upgrade = &led_system;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_system: system {\n\t\t\tlabel = \"green:system\";\n\t\t\tgpios = <&gpio 1 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"keep\";\n\t\t};\n\n\t\twlan2g {\n\t\t\tlabel = \"blue:wlan2g\";\n\t\t\tgpios = <&gpio 19 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9563_yuncore_xd4200.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca9563_yuncore_xd4200.dtsi\"\n\n/ {\n\tcompatible = \"yuncore,xd4200\", \"qca,qca9563\";\n\tmodel = \"YunCore XD4200\";\n\n\taliases {\n\t\tled-boot = &led_system;\n\t\tled-failsafe = &led_system;\n\t\tled-running = &led_system;\n\t\tled-upgrade = &led_system;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_system: system {\n\t\t\tlabel = \"blue:system\";\n\t\t\tgpios = <&gpio 1 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"keep\";\n\t\t};\n\n\t\twlan2g {\n\t\t\tlabel = \"blue:wlan2g\";\n\t\t\tgpios = <&gpio 19 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9563_yuncore_xd4200.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca956x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\taliases {\n\t\tlabel-mac-device = &eth0;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 2 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tpll-data = <0x03000101 0x00000101 0x00001919>;\n\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n\tphy-mode = \"sgmii\";\n\tphy-handle = <&phy0>;\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy-mask = <0>;\n\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t\tphy-mode = \"sgmii\";\n\n\t\tqca,ar8327-initvals = <\n\t\t\t0x04 0x00080080 /* PORT0 PAD MODE CTRL */\n\t\t\t0x10 0x81000080 /* POWER_ON_STRAP */\n\t\t\t0x50 0xcf37cf37 /* LED_CTRL0 */\n\t\t\t0x54 0xcf37cf37 /* LED_CTRL1 */\n\t\t\t0x58 0xcf37cf37 /* LED_CTRL2 */\n\t\t\t0x5c 0x0000c300 /* LED_CTRL3 */\n\t\t\t0x7c 0x0000007e /* PORT0_STATUS */\n\t\t>;\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n\n\twifi@0,0 {\n\t\tcompatible = \"pci168c,0056\";\n\t\treg = <0x0000 0 0 0 0>;\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x040000 0x010000>;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x050000 0xfa0000>;\n\t\t\t};\n\n\t\t\tart: partition@ff0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0xff0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9563_zte_mf286.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n// Copyright (c) 2021 Cezary Jackiewicz\n// Copyright (c) 2021, 2022 Lech Perczak\n#include \"qca9563_zte_mf286.dtsi\"\n\n/ {\n\tmodel = \"ZTE MF286\";\n\tcompatible = \"zte,mf286\", \"qca,qca9563\";\n\n\tubi-concat {\n\t\tcompatible = \"mtd-concat\";\n\t\tdevices = <&ubiconcat0 &ubiconcat1>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\treg = <0x0 0x7840000>;\n\t\t\t\tlabel = \"ubi\";\n\t\t\t};\n\t\t};\n\t};\n};\n\n&led_debug {\n\t/* Hidden green SMD LED below signal strength LEDs\n\t * Visible through slits underside of the case,\n\t * and slightly through the case below signal state LEDs\n\t */\n\tcolor = <LED_COLOR_ID_GREEN>;\n\tlabel = \"green:debug\";\n};\n\n&boot_flash {\n\tpartitions {\n\t\tpartition@0 {\n\t\t\tlabel = \"u-boot\";\n\t\t\treg = <0x000000 0x080000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@80000 {\n\t\t\tlabel = \"u-boot-env\";\n\t\t\treg = <0x080000 0x020000>;\n\t\t\tread-only;\n\t\t};\n\t};\n};\n\n&system_flash {\n\tpartitions {\n\t\tpartition@0 {\n\t\t\tlabel = \"fota-flag\";\n\t\t\treg = <0x000000 0x140000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@140000 {\n\t\t\tlabel = \"caldata\";\n\t\t\treg = <0x140000 0x140000>;\n\t\t\tread-only;\n\n\t\t\tcompatible = \"nvmem-cells\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tcal_caldata_1000: cal@1000 {\n\t\t\t\treg = <0x1000 0x440>;\n\t\t\t};\n\n\t\t\tcal_caldata_5000: cal@5000 {\n\t\t\t\treg = <0x5000 0x844>;\n\t\t\t};\n\t\t};\n\n\t\tpartition@280000 {\n\t\t\tlabel = \"mac\";\n\t\t\treg = <0x280000 0x140000>;\n\t\t\tread-only;\n\n\t\t\tcompatible = \"nvmem-cells\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tmacaddr_mac_0: macaddr@0 {\n\t\t\t\treg = <0x0 0x6>;\n\t\t\t};\n\t\t};\n\n\t\t/* This encompasses stock cfg-param, oops, web partitions,\n\t\t * which can be overwritten safely\n\t\t */\n\t\tubiconcat0: partition@3c0000 {\n\t\t\tlabel = \"ubiconcat0\";\n\t\t\treg = <0x3c0000 0xf40000>;\n\t\t};\n\n\t\t/* Kernel MTD size is increased to 4MB from stock 3MB */\n\t\tpartition@1300000 {\n\t\t\tlabel = \"kernel\";\n\t\t\treg = <0x1300000 0x400000>;\n\t\t};\n\n\t\t/* This encompasses stock rootfs, data, fota partitions,\n\t\t * which can be overwritten safely\n\t\t */\n\t\tubiconcat1: partition@1600000 {\n\t\t\tlabel = \"ubiconcat1\";\n\t\t\treg = <0x1700000 0x6900000>;\n\t\t};\n\t};\n};\n\n&eth0 {\n\tnvmem-cells = <&macaddr_mac_0>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wifi_ath10k {\n\tnvmem-cells = <&macaddr_mac_0>, <&cal_caldata_5000>;\n\tnvmem-cell-names = \"mac-address\", \"calibration\";\n\tmac-address-increment = <1>;\n};\n\n&wmac {\n\tnvmem-cells = <&macaddr_mac_0>, <&cal_caldata_1000>;\n\tnvmem-cell-names = \"mac-address\", \"calibration\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9563_zte_mf286.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n// Copyright (c) 2021 Cezary Jackiewicz\n// Copyright (c) 2021, 2022 Lech Perczak\n#include \"qca956x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/leds/common.h>\n\n/ {\n\taliases {\n\t\tled-boot = &led_debug;\n\t\tled-failsafe = &led_debug;\n\t\tled-running = &led_debug;\n\t\tled-upgrade = &led_debug;\n\t\tlabel-mac-device = &eth0;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\t/* Hidden SMD LED below signal strength LEDs.\n\t\t * Visible through slits underside of the case,\n\t\t * and slightly through the case below signal state LEDs\n\t\t */\n\t\tled_debug: led-0 {\n\t\t\tfunction = LED_FUNCTION_DEBUG;\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 2 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tgpios = <&gpio 1 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\twifi {\n\t\t\tlabel = \"wifi\";\n\t\t\tlinux,code = <KEY_RFKILL>;\n\t\t\tgpios = <&gpio 8 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\t/* This GPIO is used to reset whole board _including_ the modem */\n\tgpio-restart {\n\t\tcompatible = \"gpio-restart\";\n\t\tgpios = <&gpio 5 GPIO_ACTIVE_HIGH>;\n\t\tactive-delay = <3000>;\n\t\tinactive-delay = <1000>;\n\t};\n};\n\n&gpio {\n\t/* GPIO19 is used as a mask to enable WLAN LED\n\t * in stock firmware, which is controlled directly\n\t * by 5GHz Wi-Fi chip, which currently is inactive\n\t * in OpenWrt\n\t */\n\tled-wlan {\n\t\tgpio-hog;\n\t\tgpios = <19 GPIO_ACTIVE_LOW>;\n\t\toutput-high;\n\t\tline-name = \"led:wlan\";\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tboot_flash: flash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\t\t};\n\t};\n\n\tsystem_flash: flash@1 {\n\t\tcompatible = \"spi-nand\";\n\t\treg = <1>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\t\t};\n\t};\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy-mask = <0>;\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t\tphy-mode = \"sgmii\";\n\n\t\tqca,ar8327-initvals = <\n\t\t\t0x04 0x00080080 /* PORT0 PAD MODE CTRL */\n\t\t\t0x7c 0x0000007e /* PORT0_STATUS */\n\t\t>;\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tphy-mode = \"sgmii\";\n\tphy-handle = <&phy0>;\n};\n\n&pcie {\n\tstatus = \"okay\";\n\n\twifi_ath10k: wifi@0,0 {\n\t\tcompatible = \"qcom,ath10k\";\n\t\treg = <0x0 0 0 0 0>;\n\t};\n};\n\n&wmac {\n\tstatus = \"okay\";\n};\n\n&usb_phy0 {\n\tstatus = \"okay\";\n};\n\n&usb0 {\n\tstatus = \"okay\";\n};\n\n&usb_phy1 {\n\tstatus = \"okay\";\n};\n\n&usb1 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9563_zte_mf286a.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n// Copyright (c) 2021 Cezary Jackiewicz\n// Copyright (c) 2021, 2022 Lech Perczak\n#include \"qca9563_zte_mf286ar.dtsi\"\n\n/ {\n\tmodel = \"ZTE MF286A\";\n\tcompatible = \"zte,mf286a\", \"qca,qca9563\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9563_zte_mf286ar.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n// Copyright (c) 2021 Cezary Jackiewicz\n// Copyright (c) 2021, 2022 Lech Perczak\n#include \"qca9563_zte_mf286.dtsi\"\n\n/ {\n\tubi-concat {\n\t\tcompatible = \"mtd-concat\";\n\t\tdevices = <&ubiconcat0 &ubiconcat1>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\treg = <0x0 0x7a60000>;\n\t\t\t\tlabel = \"ubi\";\n\t\t\t};\n\t\t};\n\t};\n};\n\n&led_debug {\n\t/* Hidden blue SMD LED below signal strength LEDs\n\t * Visible through slits underside of the case,\n\t * and slightly through the case below signal state LEDs\n\t */\n\tcolor = <LED_COLOR_ID_BLUE>;\n\tlabel = \"blue:debug\";\n};\n\n&boot_flash {\n\tpartitions {\n\t\tpartition@0 {\n\t\t\tlabel = \"u-boot\";\n\t\t\treg = <0x000000 0x0a0000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@a0000 {\n\t\t\tlabel = \"u-boot-env\";\n\t\t\treg = <0x0a0000 0x020000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@c0000 {\n\t\t\tlabel = \"reserved1\";\n\t\t\treg = <0x0c0000 0x140000>;\n\t\t\tread-only;\n\t\t};\n\t};\n};\n\n&system_flash {\n\tpartitions {\n\t\tpartition@0 {\n\t\t\tlabel = \"fota-flag\";\n\t\t\treg = <0x00000 0xa0000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@a0000 {\n\t\t\tlabel = \"art\";\n\t\t\treg = <0xa0000 0x80000>;\n\t\t\tread-only;\n\n\t\t\tcompatible = \"nvmem-cells\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tcal_art_1000: cal@1000 {\n\t\t\t\treg = <0x1000 0x440>;\n\t\t\t};\n\n\t\t\tprecal_art_5000: precal@5000 {\n\t\t\t\treg = <0x5000 0x2f20>;\n\t\t\t};\n\t\t};\n\n\t\tpartition@120000 {\n\t\t\tlabel = \"mac\";\n\t\t\treg = <0x120000 0x80000>;\n\t\t\tread-only;\n\n\t\t\tcompatible = \"nvmem-cells\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tmacaddr_mac_0: mac-address@0 {\n\t\t\t\treg = <0x0 0x6>;\n\t\t\t};\n\t\t};\n\n\t\t/* This encompasses stock reserved2, cfg-param, log, oops,\n\t\t * reserved3, web partitions,\n\t\t * which can be overwritten safely\n\t\t */\n\t\tubiconcat0: partition@1a0000 {\n\t\t\tlabel = \"ubiconcat0\";\n\t\t\treg = <0x1a0000 0x1660000>;\n\t\t};\n\n\t\t/* Kernel MTD size is increased to 4MB from stock 3MB */\n\t\tpartition@1800000 {\n\t\t\tlabel = \"kernel\";\n\t\t\treg = <0x1800000 0x400000>;\n\t\t};\n\n\t\t/* This encompasses stock rootfs, data, fota partitions,\n\t\t * which can be overwritten safely\n\t\t */\n\t\tubiconcat1: partition@1c00000 {\n\t\t\tlabel = \"ubiconcat1\";\n\t\t\treg = <0x1c00000 0x6400000>;\n\t\t};\n\t};\n};\n\n&eth0 {\n\tnvmem-cells = <&macaddr_mac_0>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wifi_ath10k {\n\tnvmem-cells = <&macaddr_mac_0>, <&precal_art_5000>;\n\tnvmem-cell-names = \"mac-address\", \"pre-calibration\";\n\tmac-address-increment = <0x20000>;\n};\n\n&wmac {\n\tnvmem-cells = <&macaddr_mac_0>, <&cal_art_1000>;\n\tnvmem-cell-names = \"mac-address\", \"calibration\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca9563_zte_mf286r.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n// Copyright (c) 2021 Cezary Jackiewicz\n// Copyright (c) 2021, 2022 Lech Perczak\n#include \"qca9563_zte_mf286ar.dtsi\"\n\n/ {\n\tmodel = \"ZTE MF286R\";\n\tcompatible = \"zte,mf286r\", \"qca,qca9563\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qca956x.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"ath79.dtsi\"\n\n/ {\n\tcompatible = \"qca,qca9560\";\n\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200n8\";\n\t};\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu@0 {\n\t\t\tdevice_type = \"cpu\";\n\t\t\tcompatible = \"mips,mips74Kc\";\n\t\t\tclocks = <&pll ATH79_CLK_CPU>;\n\t\t\treg = <0>;\n\t\t};\n\t};\n\n\textosc: ref {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-output-names = \"ref\";\n\t\tclock-frequency = <25000000>;\n\t};\n\n\tahb {\n\t\tapb {\n\t\t\tddr_ctrl: memory-controller@18000000 {\n\t\t\t\tcompatible = \"qca,qca9560-ddr-controller\",\n\t\t\t\t\t\t\"qca,ar7240-ddr-controller\";\n\t\t\t\treg = <0x18000000 0x100>;\n\n\t\t\t\t#qca,ddr-wb-channel-cells = <1>;\n\t\t\t};\n\n\t\t\tuart: uart@18020000 {\n\t\t\t\tcompatible = \"ns16550a\";\n\t\t\t\treg = <0x18020000 0x20>;\n\n\t\t\t\tinterrupts = <3>;\n\n\t\t\t\tclocks = <&pll ATH79_CLK_REF>;\n\t\t\t\tclock-names = \"uart\";\n\n\t\t\t\treg-io-width = <4>;\n\t\t\t\treg-shift = <2>;\n\t\t\t\tno-loopback-test;\n\t\t\t};\n\n\t\t\tgpio: gpio@18040000 {\n\t\t\t\tcompatible = \"qca,qca9560-gpio\",\n\t\t\t\t\t\t\"qca,ar9340-gpio\";\n\t\t\t\treg = <0x18040000 0x28>;\n\n\t\t\t\tinterrupts = <2>;\n\t\t\t\tngpios = <24>;\n\n\t\t\t\tgpio-controller;\n\t\t\t\t#gpio-cells = <2>;\n\n\t\t\t\tinterrupt-controller;\n\t\t\t\t#interrupt-cells = <2>;\n\t\t\t};\n\n\t\t\tpinmux: pinmux@1804002c {\n\t\t\t\tcompatible = \"pinctrl-single\";\n\n\t\t\t\treg = <0x1804002c 0x44>;\n\n\t\t\t\t#size-cells = <0>;\n\n\t\t\t\tpinctrl-single,bit-per-mux;\n\t\t\t\tpinctrl-single,register-width = <32>;\n\t\t\t\tpinctrl-single,function-mask = <0x1>;\n\t\t\t\t#pinctrl-cells = <2>;\n\n\t\t\t\tjtag_disable_pins: pinmux_jtag_disable_pins {\n\t\t\t\t\tpinctrl-single,bits = <0x40 0x2 0x2>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tpll: pll-controller@18050000 {\n\t\t\t\tcompatible = \"qca,qca9560-pll\", \"syscon\";\n\t\t\t\treg = <0x18050000 0x50>;\n\n\t\t\t\t#clock-cells = <1>;\n\t\t\t\tclock-output-names = \"cpu\", \"ddr\", \"ahb\";\n\n\t\t\t\tclocks = <&extosc>;\n\t\t\t};\n\n\t\t\twdt: wdt@18060008 {\n\t\t\t\tcompatible = \"qca,ar7130-wdt\";\n\t\t\t\treg = <0x18060008 0x8>;\n\n\t\t\t\tinterrupts = <4>;\n\n\t\t\t\tclocks = <&pll ATH79_CLK_AHB>;\n\t\t\t\tclock-names = \"wdt\";\n\t\t\t};\n\n\t\t\trst: reset-controller@1806001c {\n\t\t\t\tcompatible = \"qca,qca9560-reset\",\n\t\t\t\t\t\t\"qca,ar7100-reset\";\n\t\t\t\treg = <0x1806001c 0x4>;\n\n\t\t\t\t#reset-cells = <1>;\n\t\t\t\tinterrupt-parent = <&cpuintc>;\n\n\t\t\t\tintc3: interrupt-controller {\n\t\t\t\t\tcompatible = \"qca,ar9340-intc\";\n\n\t\t\t\t\tinterrupt-parent = <&cpuintc>;\n\t\t\t\t\tinterrupts = <3>;\n\n\t\t\t\t\tinterrupt-controller;\n\t\t\t\t\t#interrupt-cells = <1>;\n\n\t\t\t\t\tqca,int-status-addr = <0xac>;\n\t\t\t\t\tqca,pending-bits = <0x1f000>,\t\t/* pcie rc */\n\t\t\t\t\t\t\t    <0x1000000>,\t/* usb1 */\n\t\t\t\t\t\t\t    <0x10000000>;\t/* usb2 */\n\t\t\t\t};\n\t\t\t};\n\n\t\t\trst2: reset-controller@180600c0 {\n\t\t\t\tcompatible = \"qca,qca9560-reset\",\n\t\t\t\t\t\t\"qca,ar7100-reset\",\n\t\t\t\t\t\t \"simple-bus\";\n\t\t\t\treg = <0x180600c0 0x4>;\n\n\t\t\t\t#reset-cells = <1>;\n\t\t\t};\n\t\t};\n\n\t\tgmac: gmac@18070000 {\n\t\t\tcompatible = \"qca,qca9560-gmac\";\n\t\t\treg = <0x18070000 0x64>;\n\t\t};\n\n\t\twmac: wmac@18100000 {\n\t\t\tcompatible = \"qca,qca9560-wmac\";\n\t\t\treg = <0x18100000 0x10000>;\n\n\t\t\tinterrupt-parent = <&cpuintc>;\n\t\t\tinterrupts = <2>;\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tpcie: pcie-controller@18250000 {\n\t\t\tcompatible = \"qcom,ar7240-pci\";\n\t\t\t#address-cells = <3>;\n\t\t\t#size-cells = <2>;\n\t\t\tbus-range = <0x0 0x0>;\n\t\t\treg = <0x18250000 0x1000>, /* CRP */\n\t\t\t      <0x18280000 0x100>,  /* CTRL */\n\t\t\t      <0x16000000 0x1000>; /* CFG */\n\t\t\treg-names = \"crp_base\", \"ctrl_base\", \"cfg_base\";\n\t\t\tranges = <0x2000000 0 0x12000000 0x12000000 0 0x02000000\t/* pci memory */\n\t\t\t\t  0x1000000 0 0x00000000 0x0000000 0 0x000001>;\t\t/* io space */\n\t\t\tinterrupt-parent = <&intc3>;\n\t\t\tinterrupts = <0>;\n\n\t\t\tdevice_type = \"pci\";\n\n\t\t\tresets = <&rst 6>, <&rst 7>;\n\t\t\treset-names = \"hc\", \"phy\";\n\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <1>;\n\n\t\t\tinterrupt-map-mask = <0 0 0 1>;\n\t\t\tinterrupt-map = <0 0 0 0 &pcie 0>;\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tusb0: usb@1b000000 {\n\t\t\tcompatible = \"generic-ehci\";\n\t\t\treg = <0x1b000000 0x1d8>;\n\n\t\t\tinterrupt-parent = <&intc3>;\n\t\t\tinterrupts = <1>;\n\n\t\t\tresets = <&rst 5>;\n\t\t\treset-names = \"usb-host\";\n\n\t\t\thas-transaction-translator;\n\t\t\tcaps-offset = <0x100>;\n\n\t\t\tphy-names = \"usb-phy0\";\n\t\t\tphys = <&usb_phy0>;\n\n\t\t\tstatus = \"disabled\";\n\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tusb1: usb@1b400000 {\n\t\t\tcompatible = \"generic-ehci\";\n\t\t\treg = <0x1b400000 0x1d8>;\n\n\t\t\tinterrupt-parent = <&intc3>;\n\t\t\tinterrupts = <2>;\n\n\t\t\tresets = <&rst2 5>;\n\t\t\treset-names = \"usb-host\";\n\n\t\t\thas-transaction-translator;\n\t\t\tcaps-offset = <0x100>;\n\n\t\t\tphy-names = \"usb-phy1\";\n\t\t\tphys = <&usb_phy1>;\n\n\t\t\tstatus = \"disabled\";\n\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tspi: spi@1f000000 {\n\t\t\tcompatible = \"qca,ar934x-spi\";\n\t\t\treg = <0x1f000000 0x1c>;\n\n\t\t\tclocks = <&pll ATH79_CLK_AHB>;\n\n\t\t\tstatus = \"disabled\";\n\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\t};\n\n\tusb_phy0: usb-phy {\n\t\tcompatible = \"qca,qca9560-usb-phy\", \"qca,ar7200-usb-phy\";\n\n\t\treset-names = \"usb-phy\", \"usb-suspend-override\";\n\t\tresets = <&rst 4>, <&rst 3>;\n\n\t\t#phy-cells = <0>;\n\n\t\tstatus = \"disabled\";\n\t};\n\n\tusb_phy1: usb-phy {\n\t\tcompatible = \"qca,qca9560-usb-phy\", \"qca,ar7200-usb-phy\";\n\n\t\treset-names = \"usb-phy\", \"usb-suspend-override\";\n\t\tresets = <&rst2 4>, <&rst2 3>;\n\n\t\t#phy-cells = <0>;\n\n\t\tstatus = \"disabled\";\n\t};\n};\n\n&mdio0 {\n\tresets = <&rst 22>;\n\treset-names = \"mdio\";\n};\n\n&eth0 {\n\tcompatible = \"qca,qca9560-eth\", \"syscon\";\n\n\tpll-data = <0x03000000 0x00000101 0x00001919>;\n\tpll-reg = <0 0x48 0>;\n\tpll-handle = <&pll>;\n\n\tresets = <&rst 9>;\n\treset-names = \"mac\";\n};\n\n&mdio1 {\n\tstatus = \"okay\";\n\tresets = <&rst 23>;\n\treset-names = \"mdio\";\n\tbuiltin-switch;\n\n\tbuiltin_switch: switch0@1f {\n\t\tcompatible = \"qca,ar8229\";\n\t\treg = <0x1f>;\n\t\tresets = <&rst 8>;\n\t\treset-names = \"switch\";\n\t\tphy-mode = \"gmii\";\n\t\tqca,phy4-mii-enable;\n\t\tqca,mib-poll-interval = <500>;\n\n\t\tmdio-bus {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\n\t\t\tswphy0: ethernet-phy@0 {\n\t\t\t\treg = <0>;\n\t\t\t\tphy-mode = \"mii\";\n\t\t\t};\n\n\t\t\tswphy4: ethernet-phy@4 {\n\t\t\t\treg = <4>;\n\t\t\t\tphy-mode = \"mii\";\n\t\t\t};\n\t\t};\n\t};\n};\n\n&eth1 {\n\tcompatible = \"qca,qca9560-eth\", \"syscon\";\n\n\tphy-mode = \"gmii\";\n\n\tresets = <&rst 13>;\n\treset-names = \"mac\";\n\n\tfixed-link {\n\t\tspeed = <1000>;\n\t\tfull-duplex;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qcn5502_netgear_ex7300-v2.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca956x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"Netgear EX7300 v2\";\n\tcompatible = \"netgear,ex7300-v2\", \"qca,qcn5500\", \"qca,qca9560\";\n\n\taliases {\n\t\tled-boot = &led_power_green;\n\t\tled-failsafe = &led_power_amber;\n\t\tled-running = &led_power_green;\n\t\tled-upgrade = &led_power_amber;\n\t\tlabel-mac-device = &eth0;\n\t};\n\n\tled_spi {\n\t\tcompatible = \"spi-gpio\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tsck-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;\n\t\tmosi-gpios = <&gpio 0 GPIO_ACTIVE_HIGH>;\n\t\tnum-chipselects = <0>;\n\n\t\tled_gpio: led_gpio@0 {\n\t\t\tcompatible = \"fairchild,74hc595\";\n\t\t\treg = <0>;\n\t\t\tgpio-controller;\n\t\t\t#gpio-cells = <2>;\n\t\t\tregisters-number = <1>;\n\t\t\tspi-max-frequency = <500000>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power_green: power_green {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_power_amber: power_amber {\n\t\t\tlabel = \"amber:power\";\n\t\t\tgpios = <&led_gpio 7 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twps_green {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&led_gpio 6 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\trouter_red {\n\t\t\tlabel = \"red:router\";\n\t\t\tgpios = <&led_gpio 5 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\trouter_green {\n\t\t\tlabel = \"green:router\";\n\t\t\tgpios = <&led_gpio 4 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tclient_red {\n\t\t\tlabel = \"red:client\";\n\t\t\tgpios = <&led_gpio 3 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tclient_green {\n\t\t\tlabel = \"green:client\";\n\t\t\tgpios = <&led_gpio 2 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tleft_blue {\n\t\t\tlabel = \"blue:left\";\n\t\t\tgpios = <&led_gpio 1 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tright_blue {\n\t\t\tlabel = \"blue:right\";\n\t\t\tgpios = <&led_gpio 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"Reset button\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 3 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"WPS button\";\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tgpios = <&gpio 1 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\textender_apmode {\n\t\t\tlabel = \"EXTENDER/APMODE switch\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_0>;\n\t\t\tlinux,input-type = <EV_SW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n\n\twifi@0,0 {\n\t\tcompatible = \"qcom,ath10k\";\n\t\treg = <0 0 0 0 0>;\n\n\t\tnvmem-cells = <&macaddr_artmtd_c>, <&precal_art_5000>;\n\t\tnvmem-cell-names = \"mac-address\", \"pre-calibration\";\n\t};\n};\n\n&pll {\n\tclocks = <&extosc>;\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x040000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tlabel = \"config\";\n\t\t\t\treg = <0x050000 0x010000>;\n\t\t\t};\n\n\t\t\tpartition@60000 {\n\t\t\t\tlabel = \"pot\";\n\t\t\t\treg = <0x060000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@70000 {\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x70000 0xe30000>;\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t};\n\n\t\t\tpartition@ea0000 {\n\t\t\t\tlabel = \"rae\";\n\t\t\t\treg = <0xea0000 0x100000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@fa0000 {\n\t\t\t\tlabel = \"oopsdump\";\n\t\t\t\treg = <0xfa0000 0x40000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@fe0000 {\n\t\t\t\tlabel = \"artmtd\";\n\t\t\t\treg = <0xfe0000 0x10000>;\n\n\t\t\t\tcompatible = \"nvmem-cells\";\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\n\t\t\t\tmacaddr_artmtd_0: macaddr@0 {\n\t\t\t\t\treg = <0x0 0x6>;\n\t\t\t\t};\n\n\t\t\t\tmacaddr_artmtd_6: macaddr@6 {\n\t\t\t\t\treg = <0x6 0x6>;\n\t\t\t\t};\n\n\t\t\t\tmacaddr_artmtd_c: macaddr@c {\n\t\t\t\t\treg = <0xc 0x6>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tpartition@ff0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0xff0000 0x10000>;\n\t\t\t\tread-only;\n\n\t\t\t\tcompatible = \"nvmem-cells\";\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\n\t\t\t\tcal_art_1000: cal@1000 {\n\t\t\t\t\treg = <0x1000 0x440>;\n\t\t\t\t};\n\n\t\t\t\tprecal_art_5000: precal@5000 {\n\t\t\t\t\treg = <0x5000 0x2f20>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t};\n};\n\n\n&wmac {\n\t/* Does not work due to lack of QCN5502 support in ath9k. */\n\tstatus = \"disabled\";\n\n\tnvmem-cells = <&macaddr_artmtd_6>, <&cal_art_1000>;\n\tnvmem-cell-names = \"mac-address\", \"calibration\";\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy5: ethernet-phy@5 {\n\t\treg = <5>;\n\t\tphy-mode = \"sgmii\";\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tnvmem-cells = <&macaddr_artmtd_0>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tphy-handle = <&phy5>;\n\tphy-mode = \"sgmii\";\n\n\tpll-data = <0x03000000 0x00000101 0x00001313>;\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/qcn5502_tplink_archer-a9-v6.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca956x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"TP-Link Archer A9 v6\";\n\tcompatible = \"tplink,archer-a9-v6\", \"qca,qcn5500\", \"qca,qca9560\";\n\n\taliases {\n\t\tlabel-mac-device = &eth0;\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\tusb {\n\t\t\tlabel = \"green:usb\";\n\t\t\tgpios = <&gpio 0 GPIO_ACTIVE_HIGH>;\n\t\t\ttrigger-sources = <&hub_port0>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\n\t\twan {\n\t\t\tlabel = \"green:wan\";\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twan_orange {\n\t\t\tlabel = \"orange:wan\";\n\t\t\tgpios = <&gpio 3 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan2g {\n\t\t\tlabel = \"green:wlan2g\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\n\t\twlan5g {\n\t\t\tlabel = \"green:wlan5g\";\n\t\t\tgpios = <&gpio 20 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&gpio 1 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tpll-data = <0x03000101 0x00000101 0x00001919>;\n\n\tphy-mode = \"sgmii\";\n\tphy-handle = <&phy0>;\n\n\tnvmem-cells = <&macaddr_info_8>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tphy-mask = <0>;\n\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t\tphy-mode = \"sgmii\";\n\t\tqca,mib-poll-interval = <500>;\n\n\t\tqca,ar8327-initvals = <\n\t\t\t0x04 0x80080080 /* PORT0 PAD MODE CTRL */\n\t\t\t0x08 0x00000000 /* PORT5 PAD MODE CTRL */\n\t\t\t0x0c 0x00000000 /* PORT6 PAD MODE CTRL */\n\t\t\t0x10 0x00000080 /* POWER_ON_STRAP */\n\t\t\t0x7c 0x0000007e /* PORT0_STATUS */\n\t\t\t0x94 0x00000200 /* PORT6_STATUS */\n\t\t\t>;\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n\n\twifi@0,0 {\n\t\tcompatible = \"pci168c,0046\";\n\t\treg = <0 0 0 0 0>;\n\n\t\tnvmem-cells = <&macaddr_info_8>, <&precal_art_5000>;\n\t\tnvmem-cell-names = \"mac-address\", \"pre-calibration\";\n\n\t\tmac-address-increment = <(-1)>;\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\t\tm25p,fast-read;\n\n\t\tmtdparts: partitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"factory-uboot\";\n\t\t\t\treg = <0x000000 0x020000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x020000 0x020000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"partition-table\";\n\t\t\t\treg = <0x040000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0x050000 0x010000>;\n\t\t\t\tread-only;\n\n\t\t\t\tcompatible = \"nvmem-cells\";\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\n\t\t\t\tcal_art_1000: cal@1000 {\n\t\t\t\t\treg = <0x1000 0x440>;\n\t\t\t\t};\n\n\t\t\t\tprecal_art_5000: precal@5000 {\n\t\t\t\t\treg = <0x5000 0x2f20>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tpartition@60000 {\n\t\t\t\tlabel = \"info\";\n\t\t\t\treg = <0x060000 0x020000>;\n\t\t\t\tread-only;\n\n\t\t\t\tcompatible = \"nvmem-cells\";\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\n\t\t\t\tmacaddr_info_8: macaddr@8 {\n\t\t\t\t\treg = <0x8 0x6>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tpartition@80000 {\n\t\t\t\tlabel = \"user-config\";\n\t\t\t\treg = <0x080000 0x040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@c0000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x0c0000 0xf00000>;\n\t\t\t};\n\n\t\t\tpartition@fc0000 {\n\t\t\t\tlabel = \"log\";\n\t\t\t\treg = <0xfc0000 0x020000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@fe0000 {\n\t\t\t\tlabel = \"certificate\";\n\t\t\t\treg = <0xfe0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@ff0000 {\n\t\t\t\tlabel = \"default-config\";\n\t\t\t\treg = <0xff0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&usb_phy0 {\n\tstatus = \"okay\";\n};\n\n&usb0 {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\tstatus = \"okay\";\n\n\thub_port0: port@1 {\n\t\treg = <1>;\n\t\t#trigger-source-cells = <0>;\n\t};\n};\n\n&wmac {\n\t/* TODO: missing support in ath9k */\n\tstatus = \"disabled\";\n\n\tnvmem-cells = <&cal_art_1000>, <&macaddr_info_8>;\n\tnvmem-cell-names = \"calibration\", \"mac-address\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/tp9343_tplink_tl-wa901nd-v4.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"tp9343_tplink_tl-wa901nd.dtsi\"\n\n/ {\n\tcompatible = \"tplink,tl-wa901nd-v4\", \"qca,tp9343\";\n\tmodel = \"TP-Link TL-WA901ND v4\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/tp9343_tplink_tl-wa901nd-v5.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"tp9343_tplink_tl-wa901nd.dtsi\"\n\n/ {\n\tcompatible = \"tplink,tl-wa901nd-v5\", \"qca,tp9343\";\n\tmodel = \"TP-Link TL-WA901ND v5\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/tp9343_tplink_tl-wa901nd.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"tp9343_tplink_tl-wx.dtsi\"\n\n/ {\n\taliases {\n\t\tled-boot = &led_system;\n\t\tled-failsafe = &led_system;\n\t\tled-running = &led_system;\n\t\tled-upgrade = &led_system;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"Reset button\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 1 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_system: system {\n\t\t\tlabel = \"green:system\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\tqss {\n\t\t\tlabel = \"green:qss\";\n\t\t\tgpios = <&gpio 3 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan {\n\t\t\tlabel = \"green:lan\";\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan {\n\t\t\tlabel = \"green:wlan\";\n\t\t\tgpios = <&gpio 8 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\t};\n};\n\n&eth1 {\n\tcompatible = \"syscon\", \"simple-mfd\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/tp9343_tplink_tl-wr940n-v3.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"tp9343_tplink_tl-wr940n-v3.dtsi\"\n\n/ {\n\tcompatible = \"tplink,tl-wr940n-v3\", \"qca,tp9343\";\n\tmodel = \"TP-Link TL-WR940N v3\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/tp9343_tplink_tl-wr940n-v3.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"tp9343_tplink_tl-wr94x.dtsi\"\n\n/ {\n\taliases {\n\t\tled-boot = &led_system;\n\t\tled-failsafe = &led_system;\n\t\tled-running = &led_system;\n\t\tled-upgrade = &led_system;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_system: system {\n\t\t\tlabel = \"blue:system\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\tqss {\n\t\t\tlabel = \"blue:qss\";\n\t\t\tgpios = <&gpio 3 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan {\n\t\t\tlabel = \"blue:wlan\";\n\t\t\tgpios = <&gpio 8 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\twan_blue {\n\t\t\tlabel = \"blue:wan\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twan_red {\n\t\t\tlabel = \"red:wan\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tlan1 {\n\t\t\tlabel = \"blue:lan1\";\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan2 {\n\t\t\tlabel = \"blue:lan2\";\n\t\t\tgpios = <&gpio 6 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan3 {\n\t\t\tlabel = \"blue:lan3\";\n\t\t\tgpios = <&gpio 5 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan4 {\n\t\t\tlabel = \"blue:lan4\";\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&eth1 {\n\tnvmem-cells = <&macaddr_uboot_1fc00>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <(-1)>;\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/tp9343_tplink_tl-wr940n-v4.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"tp9343_tplink_tl-wr94x.dtsi\"\n\n/ {\n\tcompatible = \"tplink,tl-wr940n-v4\", \"qca,tp9343\";\n\tmodel = \"TP-Link TL-WR940N v4\";\n\n\taliases {\n\t\tled-boot = &led_system;\n\t\tled-failsafe = &led_system;\n\t\tled-running = &led_system;\n\t\tled-upgrade = &led_system;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_system: system {\n\t\t\tlabel = \"blue:system\";\n\t\t\tgpios = <&gpio 5 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\tqss {\n\t\t\tlabel = \"blue:qss\";\n\t\t\tgpios = <&gpio 3 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan {\n\t\t\tlabel = \"blue:wlan\";\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\twan_blue {\n\t\t\tlabel = \"blue:wan\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twan_red {\n\t\t\tlabel = \"red:wan\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tlan1 {\n\t\t\tlabel = \"blue:lan1\";\n\t\t\tgpios = <&gpio 8 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan2 {\n\t\t\tlabel = \"blue:lan2\";\n\t\t\tgpios = <&gpio 6 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan3 {\n\t\t\tlabel = \"blue:lan3\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan4 {\n\t\t\tlabel = \"blue:lan4\";\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&eth1 {\n\tnvmem-cells = <&macaddr_uboot_1fc00>;\n\tnvmem-cell-names = \"mac-address\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/tp9343_tplink_tl-wr940n-v6.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"tp9343_tplink_tl-wr94x.dtsi\"\n\n/ {\n\tcompatible = \"tplink,tl-wr940n-v6\", \"qca,tp9343\";\n\tmodel = \"TP-Link TL-WR940N v6\";\n\n\taliases {\n\t\tled-boot = &led_diag_orange;\n\t\tled-failsafe = &led_diag_orange;\n\t\tled-running = &led_diag_orange;\n\t\tled-upgrade = &led_diag_orange;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twan_blue {\n\t\t\tlabel = \"blue:wan\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_diag_orange: diag_orange {\n\t\t\tlabel = \"orange:diag\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n};\n\n&eth1 {\n\tnvmem-cells = <&macaddr_uboot_1fc00>;\n\tnvmem-cell-names = \"mac-address\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/tp9343_tplink_tl-wr941hp-v1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca956x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"tplink,tl-wr941hp-v1\", \"qca,tp9343\";\n\tmodel = \"TP-Link TL-WR941HP v1\";\n\n\taliases {\n\t\tlabel-mac-device = &wmac;\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tre {\n\t\t\tlabel = \"blue:re\";\n\t\t\tgpios = <&gpio 6 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twifi {\n\t\t\tlabel = \"blue:wifi\";\n\t\t\tgpios = <&gpio 8 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\tled_power: power {\n\t\t\tlabel = \"blue:power\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\twan_blue {\n\t\t\tlabel = \"blue:wan\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twan_red {\n\t\t\tlabel = \"red:wan\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan {\n\t\t\tlabel = \"blue:lan\";\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"blue:wps\";\n\t\t\tgpios = <&gpio 3 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\tre {\n\t\t\tlabel = \"range extender button\";\n\t\t\tlinux,code = <BTN_0>;\n\t\t\tgpios = <&gpio 5 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\twifi {\n\t\t\tlabel = \"wifi button\";\n\t\t\tlinux,code = <KEY_RFKILL>;\n\t\t\tgpios = <&gpio 2 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset button\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 1 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps button\";\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tuboot: partition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x020000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tcompatible = \"tplink,firmware\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x020000 0x730000>;\n\t\t\t};\n\n\t\t\tconfig: partition@750000 {\n\t\t\t\tlabel = \"config\";\n\t\t\t\treg = <0x750000 0x0a0000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tart: partition@7f0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0x7f0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tphy-handle = <&swphy0>;\n\n\tnvmem-cells = <&macaddr_config_8>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <1>;\n};\n\n&eth1 {\n\tstatus = \"okay\";\n\n\tnvmem-cells = <&macaddr_config_8>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n\tnvmem-cells = <&macaddr_config_8>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&config {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_config_8: macaddr@8 {\n\t\treg = <0x8 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/tp9343_tplink_tl-wr941nd-v6.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"tp9343_tplink_tl-wr940n-v3.dtsi\"\n\n/ {\n\tcompatible = \"tplink,tl-wr941nd-v6\", \"qca,tp9343\";\n\tmodel = \"TP-Link TL-WR941ND v6\";\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/tp9343_tplink_tl-wr94x.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"tp9343_tplink_tl-wx.dtsi\"\n\n/ {\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\twifi {\n\t\t\tlabel = \"WiFi button\";\n\t\t\tlinux,code = <KEY_RFKILL>;\n\t\t\tgpios = <&gpio 2 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"Reset button\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 1 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/dts/tp9343_tplink_tl-wx.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qca956x.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\taliases {\n\t\tlabel-mac-device = &wmac;\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tuboot: partition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x020000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tcompatible = \"tplink,firmware\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x020000 0x3d0000>;\n\t\t\t};\n\n\t\t\tart: partition@3f0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0x3f0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tphy-handle = <&swphy4>;\n\n\tnvmem-cells = <&macaddr_uboot_1fc00>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <1>;\n};\n\n&eth1 {\n\tstatus = \"okay\";\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmtd-cal-data = <&art 0x1000>;\n\tnvmem-cells = <&macaddr_uboot_1fc00>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&uboot {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_uboot_1fc00: macaddr@1fc00 {\n\t\treg = <0x1fc00 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ath79/files/arch/mips/include/asm/fw/myloader/myloader.h",
    "content": "/*\n *  Compex's MyLoader specific definitions\n *\n *  Copyright (C) 2006-2008 Gabor Juhos <juhosg@openwrt.org>\n *\n *  This program is free software; you can redistribute it and/or modify it\n *  under the terms of the GNU General Public License version 2 as published\n *  by the Free Software Foundation.\n *\n */\n\n#ifndef _ASM_MIPS_FW_MYLOADER_H\n#define _ASM_MIPS_FW_MYLOADER_H\n\n#include <linux/myloader.h>\n\nstruct myloader_info {\n\tuint32_t\tvid;\n\tuint32_t\tdid;\n\tuint32_t\tsvid;\n\tuint32_t\tsdid;\n\tuint8_t\t\tmacs[MYLO_ETHADDR_COUNT][6];\n};\n\n#ifdef CONFIG_MYLOADER\nextern struct myloader_info *myloader_get_info(void) __init;\n#else\nstatic inline struct myloader_info *myloader_get_info(void)\n{\n\treturn NULL;\n}\n#endif /* CONFIG_MYLOADER */\n\n#endif /* _ASM_MIPS_FW_MYLOADER_H */\n"
  },
  {
    "path": "target/linux/ath79/files/drivers/gpio/gpio-latch.c",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later\n/*\n *  GPIO latch driver\n *\n *  Copyright (C) 2014 Gabor Juhos <juhosg@openwrt.org>\n */\n\n#include <linux/kernel.h>\n#include <linux/init.h>\n#include <linux/module.h>\n#include <linux/types.h>\n#include <linux/gpio/consumer.h>\n#include <linux/gpio/driver.h>\n#include <linux/platform_device.h>\n#include <linux/of_platform.h>\n#include <linux/of_gpio.h>\n\n#define GPIO_LATCH_DRIVER_NAME  \"gpio-latch\"\n#define GPIO_LATCH_LINES 9\n\nstruct gpio_latch_chip {\n\tstruct gpio_chip gc;\n\tstruct mutex mutex;\n\tstruct mutex latch_mutex;\n\tbool latch_enabled;\n\tint le_gpio;\n\tbool le_active_low;\n\tstruct gpio_desc *gpios[GPIO_LATCH_LINES];\n};\n\nstatic inline struct gpio_latch_chip *to_gpio_latch_chip(struct gpio_chip *gc)\n{\n\treturn container_of(gc, struct gpio_latch_chip, gc);\n}\n\nstatic void gpio_latch_lock(struct gpio_latch_chip *glc, bool enable)\n{\n\tmutex_lock(&glc->mutex);\n\n\tif (enable)\n\t\tglc->latch_enabled = true;\n\n\tif (glc->latch_enabled)\n\t\tmutex_lock(&glc->latch_mutex);\n}\n\nstatic void gpio_latch_unlock(struct gpio_latch_chip *glc, bool disable)\n{\n\tif (glc->latch_enabled)\n\t\tmutex_unlock(&glc->latch_mutex);\n\n\tif (disable)\n\t\tglc->latch_enabled = true;\n\n\tmutex_unlock(&glc->mutex);\n}\n\nstatic int\ngpio_latch_get(struct gpio_chip *gc, unsigned offset)\n{\n\tstruct gpio_latch_chip *glc = to_gpio_latch_chip(gc);\n\tint ret;\n\n\tgpio_latch_lock(glc, false);\n\tret = gpiod_get_raw_value_cansleep(glc->gpios[offset]);\n\tgpio_latch_unlock(glc, false);\n\n\treturn ret;\n}\n\nstatic void\ngpio_latch_set(struct gpio_chip *gc, unsigned offset, int value)\n{\n\tstruct gpio_latch_chip *glc = to_gpio_latch_chip(gc);\n\tbool enable_latch = false;\n\tbool disable_latch = false;\n\n\tif (offset == glc->le_gpio) {\n\t\tenable_latch = value ^ glc->le_active_low;\n\t\tdisable_latch = !enable_latch;\n\t}\n\n\tgpio_latch_lock(glc, enable_latch);\n\tgpiod_set_raw_value_cansleep(glc->gpios[offset], value);\n\tgpio_latch_unlock(glc, disable_latch);\n}\n\nstatic int\ngpio_latch_direction_output(struct gpio_chip *gc, unsigned offset, int value)\n{\n\tstruct gpio_latch_chip *glc = to_gpio_latch_chip(gc);\n\tbool enable_latch = false;\n\tbool disable_latch = false;\n\tint ret;\n\n\tif (offset == glc->le_gpio) {\n\t\tenable_latch = value ^ glc->le_active_low;\n\t\tdisable_latch = !enable_latch;\n\t}\n\n\tgpio_latch_lock(glc, enable_latch);\n\tret = gpiod_direction_output_raw(glc->gpios[offset], value);\n\tgpio_latch_unlock(glc, disable_latch);\n\n\treturn ret;\n}\n\nstatic int gpio_latch_probe(struct platform_device *pdev)\n{\n\tstruct gpio_latch_chip *glc;\n\tstruct gpio_chip *gc;\n\tstruct device *dev = &pdev->dev;\n\tstruct device_node *of_node = dev->of_node;\n\tint i, n;\n\n\tglc = devm_kzalloc(dev, sizeof(*glc), GFP_KERNEL);\n\tif (!glc)\n\t\treturn -ENOMEM;\n\n\tmutex_init(&glc->mutex);\n\tmutex_init(&glc->latch_mutex);\n\n\tn = gpiod_count(dev, NULL);\n\tif (n <= 0) {\n\t\tdev_err(dev, \"failed to get gpios: %d\\n\", n);\n\t\treturn n;\n\t} else if (n != GPIO_LATCH_LINES) {\n\t\tdev_err(dev, \"expected %d gpios\\n\", GPIO_LATCH_LINES);\n\t\treturn -EINVAL;\n\t}\n\n\tfor (i = 0; i < n; i++) {\n\t\tglc->gpios[i] = devm_gpiod_get_index_optional(dev, NULL, i,\n\t\t\tGPIOD_OUT_LOW);\n\t\tif (IS_ERR(glc->gpios[i])) {\n\t\t\tif (PTR_ERR(glc->gpios[i]) != -EPROBE_DEFER) {\n\t\t\t\tdev_err(dev, \"failed to get gpio %d: %d\\n\", i,\n\t\t\t\t\tPTR_ERR(glc->gpios[i]));\n\t\t\t}\n\t\t\treturn PTR_ERR(glc->gpios[i]);\n\t\t}\n\t}\n\n\tglc->le_gpio = 8;\n\tglc->le_active_low = gpiod_is_active_low(glc->gpios[glc->le_gpio]);\n\n\tif (!glc->gpios[glc->le_gpio]) {\n\t\tdev_err(dev, \"missing required latch-enable gpio %d\\n\",\n\t\t\tglc->le_gpio);\n\t\treturn -EINVAL;\n\t}\n\n\tgc = &glc->gc;\n\tgc->label = GPIO_LATCH_DRIVER_NAME;\n\tgc->can_sleep = true;\n\tgc->base = -1;\n\tgc->ngpio = GPIO_LATCH_LINES;\n\tgc->get = gpio_latch_get;\n\tgc->set = gpio_latch_set;\n\tgc->direction_output = gpio_latch_direction_output;\n\tgc->of_node = of_node;\n\n\tplatform_set_drvdata(pdev, glc);\n\n\ti = gpiochip_add(&glc->gc);\n\tif (i) {\n\t\tdev_err(dev, \"gpiochip_add() failed: %d\\n\", i);\n\t\treturn i;\n\t}\n\n\treturn 0;\n}\n\nstatic int gpio_latch_remove(struct platform_device *pdev)\n{\n\tstruct gpio_latch_chip *glc = platform_get_drvdata(pdev);\n\n\tgpiochip_remove(&glc->gc);\n\treturn 0;\n}\n\nstatic const struct of_device_id gpio_latch_match[] = {\n\t{ .compatible = GPIO_LATCH_DRIVER_NAME },\n\t{},\n};\n\nMODULE_DEVICE_TABLE(of, gpio_latch_match);\n\nstatic struct platform_driver gpio_latch_driver = {\n\t.probe = gpio_latch_probe,\n\t.remove = gpio_latch_remove,\n\t.driver = {\n\t\t.name = GPIO_LATCH_DRIVER_NAME,\n\t\t.owner = THIS_MODULE,\n\t\t.of_match_table = gpio_latch_match,\n\t},\n};\n\nmodule_platform_driver(gpio_latch_driver);\n\nMODULE_DESCRIPTION(\"GPIO latch driver\");\nMODULE_AUTHOR(\"Gabor Juhos <juhosg@openwrt.org>\");\nMODULE_AUTHOR(\"Denis Kalashnikov <denis281089@gmail.com>\");\nMODULE_LICENSE(\"GPL v2\");\nMODULE_ALIAS(\"platform:\" GPIO_LATCH_DRIVER_NAME);\n"
  },
  {
    "path": "target/linux/ath79/files/drivers/gpio/gpio-rb4xx.c",
    "content": "// SPDX-License-Identifier: GPL-2.0-only\n/*\n * GPIO driver for the MikroTik RouterBoard 4xx series\n *\n * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>\n * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>\n * Copyright (C) 2015 Bert Vermeulen <bert@biot.com>\n * Copyright (C) 2020 Christopher Hill <ch6574@gmail.com>\n *\n * This file was based on the driver for Linux 2.6.22 published by\n * MikroTik for their RouterBoard 4xx series devices.\n *\n * N.B. driver probe reports \"DMA mask not set\" warnings which are\n * an artifact of using a platform_driver as an MFD device child.\n * See conversation here https://lkml.org/lkml/2020/4/28/675\n */\n#include <linux/platform_device.h>\n#include <linux/gpio/driver.h>\n#include <linux/module.h>\n#include <linux/of_device.h>\n\n#include <mfd/rb4xx-cpld.h>\n\nstruct rb4xx_gpio {\n\tstruct rb4xx_cpld *cpld;\n\tstruct device *dev;\n\n\tstruct gpio_chip chip;\n\tstruct mutex lock;\n\tu16 values;\t\t/* bitfield of GPIO 0-8 current values */\n};\n\nstatic int rb4xx_gpio_cpld_set(struct rb4xx_gpio *gpio, unsigned int offset,\n\t\t\t       int value)\n{\n\tstruct rb4xx_cpld *cpld = gpio->cpld;\n\tu16 values;\n\tint ret;\n\n\tmutex_lock(&gpio->lock);\n\tvalues = gpio->values;\n\n\tif (value)\n\t\tvalues |= BIT(offset);\n\telse\n\t\tvalues &= ~(BIT(offset));\n\n\tif (values == gpio->values) {\n\t\tret = 0;\n\t\tgoto unlock;\n\t}\n\n\tif (offset < 8) {\n\t\tret = cpld->gpio_set_0_7(cpld, values & 0xff);\n\t} else if (offset == 8) {\n\t\tret = cpld->gpio_set_8(cpld, values >> 8);\n\t}\n\n\tif(likely(!ret))\n\t\tgpio->values = values;\n\nunlock:\n\tmutex_unlock(&gpio->lock);\n\treturn ret;\n}\n\nstatic int rb4xx_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)\n{\n\treturn 0; /* All 9 GPIOs are out */\n}\n\nstatic int rb4xx_gpio_direction_input(struct gpio_chip *chip,\n\t\t\t\t      unsigned int offset)\n{\n\treturn -EOPNOTSUPP;\n}\n\nstatic int rb4xx_gpio_direction_output(struct gpio_chip *chip,\n\t\t\t\t       unsigned int offset, int value)\n{\n\treturn rb4xx_gpio_cpld_set(gpiochip_get_data(chip), offset, value);\n}\n\nstatic int rb4xx_gpio_get(struct gpio_chip *chip, unsigned int offset)\n{\n\tstruct rb4xx_gpio *gpio = gpiochip_get_data(chip);\n\tint ret;\n\n\tmutex_lock(&gpio->lock);\n\tret = (gpio->values >> offset) & 0x1;\n\tmutex_unlock(&gpio->lock);\n\n\treturn ret;\n}\n\nstatic void rb4xx_gpio_set(struct gpio_chip *chip, unsigned int offset,\n\t\t\t   int value)\n{\n\trb4xx_gpio_cpld_set(gpiochip_get_data(chip), offset, value);\n}\n\nstatic int rb4xx_gpio_probe(struct platform_device *pdev)\n{\n\tstruct device *dev = &pdev->dev;\n\tstruct device *parent = dev->parent;\n\tstruct rb4xx_gpio *gpio;\n\tu32 val;\n\n\tif (!parent)\n\t\treturn -ENODEV;\n\n\tgpio = devm_kzalloc(dev, sizeof(*gpio), GFP_KERNEL);\n\tif (!gpio)\n\t\treturn -ENOMEM;\n\n\tplatform_set_drvdata(pdev, gpio);\n\tgpio->cpld\t= dev_get_drvdata(parent);\n\tgpio->dev\t= dev;\n\tgpio->values\t= 0;\n\tmutex_init(&gpio->lock);\n\n\tgpio->chip.label\t\t= \"rb4xx-gpio\";\n\tgpio->chip.parent\t\t= dev;\n\tgpio->chip.owner\t\t= THIS_MODULE;\n\tgpio->chip.get_direction\t= rb4xx_gpio_get_direction;\n\tgpio->chip.direction_input\t= rb4xx_gpio_direction_input;\n\tgpio->chip.direction_output\t= rb4xx_gpio_direction_output;\n\tgpio->chip.get\t\t\t= rb4xx_gpio_get;\n\tgpio->chip.set\t\t\t= rb4xx_gpio_set;\n\tgpio->chip.ngpio\t\t= 9;\n\tgpio->chip.base\t\t\t= -1;\n\tgpio->chip.can_sleep\t\t= 1;\n\n\tif (!of_property_read_u32(dev->of_node, \"base\", &val))\n\t\tgpio->chip.base = val;\n\n\treturn gpiochip_add_data(&gpio->chip, gpio);\n}\n\nstatic int rb4xx_gpio_remove(struct platform_device *pdev)\n{\n\tstruct rb4xx_gpio *gpio = platform_get_drvdata(pdev);\n\n\tgpiochip_remove(&gpio->chip);\n\tmutex_destroy(&gpio->lock);\n\n\treturn 0;\n}\n\nstatic const struct platform_device_id rb4xx_gpio_id_table[] = {\n\t{ \"mikrotik,rb4xx-gpio\", },\n\t{ },\n};\nMODULE_DEVICE_TABLE(platform, rb4xx_gpio_id_table);\n\nstatic struct platform_driver rb4xx_gpio_driver = {\n\t.probe = rb4xx_gpio_probe,\n\t.remove = rb4xx_gpio_remove,\n\t.id_table = rb4xx_gpio_id_table,\n\t.driver = {\n\t\t.name = \"rb4xx-gpio\",\n\t},\n};\n\nmodule_platform_driver(rb4xx_gpio_driver);\n\nMODULE_DESCRIPTION(\"Mikrotik RB4xx GPIO driver\");\nMODULE_AUTHOR(\"Gabor Juhos <juhosg@openwrt.org>\");\nMODULE_AUTHOR(\"Imre Kaloz <kaloz@openwrt.org>\");\nMODULE_AUTHOR(\"Bert Vermeulen <bert@biot.com>\");\nMODULE_AUTHOR(\"Christopher Hill <ch6574@gmail.com\");\nMODULE_LICENSE(\"GPL v2\");\n"
  },
  {
    "path": "target/linux/ath79/files/drivers/gpio/gpio-rb91x-key.c",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later\n/*\n * Driver for reset key gpio line on MikroTik RB91x board series.\n * This line is shared between NAND ALE (goes through a latch),\n * NAND IO7 and reset key. We make 3 virtual gpio lines from the\n * single physical one:\n *   1) Capable output one for NAND,\n *   2) Capable input one for reset key,\n *   3) And capable output one, aka \"key-poll-disable\",\n *      for NAND -- to syncronise NAND operation and key polling.\n *\n * Copyright (C) 2021 Denis Kalashnikov <denis281089@gmail.com>\n */\n\n#include <linux/kernel.h>\n#include <linux/init.h>\n#include <linux/module.h>\n#include <linux/types.h>\n#include <linux/gpio/consumer.h>\n#include <linux/gpio/driver.h>\n#include <linux/platform_device.h>\n#include <linux/of_platform.h>\n#include <linux/of_gpio.h>\n#include <linux/delay.h>\n\n#define GPIO_RB91X_KEY_DRIVER_NAME  \"gpio-rb91x-key\"\n\nenum gpio_rb91x_key_gpios {\n\tGPIO_RB91X_KEY_NAND,\n\tGPIO_RB91X_KEY_POLL,\n\tGPIO_RB91X_KEY_PDIS,\n\n\tGPIO_RB91X_KEY_NGPIOS,\n};\n\nstruct gpio_rb91x_key {\n\tstruct gpio_chip gc;\n\tstruct mutex mutex;\n\tstruct mutex poll_mutex;\n\tint polling_disabled;\n\tstruct gpio_desc *gpio;\n};\n\nstatic inline struct gpio_rb91x_key *to_gpio_rb91x_key(struct gpio_chip *gc)\n{\n\treturn container_of(gc, struct gpio_rb91x_key, gc);\n}\n\nstatic int gpio_rb91x_key_get(struct gpio_chip *gc, unsigned offset)\n{\n\tstruct gpio_rb91x_key *drvdata = to_gpio_rb91x_key(gc);\n\tstruct gpio_desc *gpio = drvdata->gpio;\n\tint val, bak_val;\n\n\tswitch (offset) {\n\tcase GPIO_RB91X_KEY_NAND:\n\t\tmutex_lock(&drvdata->mutex);\n\t\tval = gpiod_get_value_cansleep(gpio);\n\t\tmutex_unlock(&drvdata->mutex);\n\t\tbreak;\n\tcase GPIO_RB91X_KEY_PDIS:\n\t\tmutex_lock(&drvdata->mutex);\n\t\tval = drvdata->polling_disabled;\n\t\tmutex_unlock(&drvdata->mutex);\n\t\tbreak;\n\tcase GPIO_RB91X_KEY_POLL:\n\t\tmutex_lock(&drvdata->poll_mutex);\n\t\tmutex_lock(&drvdata->mutex);\n\t\tbak_val = gpiod_get_raw_value_cansleep(gpio);\n\t\tgpiod_direction_input(gpio);\n\t\t/*\n\t\t * Without this delay nothing works. Get it\n\t\t * from mikrotik RouterOS linux kernel patches.\n\t\t */\n\t\tudelay(200);\n\t\tval = gpiod_get_raw_value_cansleep(gpio);\n\t\tgpiod_direction_output_raw(gpio, bak_val);\n\t\tmutex_unlock(&drvdata->mutex);\n\t\tmutex_unlock(&drvdata->poll_mutex);\n\t\tbreak;\n\tdefault:\n\t\treturn -EINVAL;\n\t}\n\n\treturn val;\n}\n\nstatic int gpio_rb91x_key_direction_input(struct gpio_chip *gc, unsigned offset)\n{\n\tswitch (offset) {\n\tcase GPIO_RB91X_KEY_POLL:\n\t\treturn 0;\n\tdefault:\n\t\treturn -EINVAL;\n\t}\n}\n\nstatic void gpio_rb91x_key_set(struct gpio_chip *gc, unsigned offset, int value)\n{\n\tstruct gpio_rb91x_key *drvdata = to_gpio_rb91x_key(gc);\n\tstruct gpio_desc *gpio = drvdata->gpio;\n\n\tmutex_lock(&drvdata->mutex);\n\n\tswitch (offset) {\n\tcase GPIO_RB91X_KEY_NAND:\n\t\tgpiod_set_raw_value_cansleep(gpio, value);\n\t\tbreak;\n\tcase GPIO_RB91X_KEY_PDIS:\n\t\tif (value) {\n\t\t\tif (!drvdata->polling_disabled) {\n\t\t\t\tmutex_lock(&drvdata->poll_mutex);\n\t\t\t\tdrvdata->polling_disabled = 1;\n\t\t\t}\n\t\t} else {\n\t\t\tif (drvdata->polling_disabled) {\n\t\t\t\tmutex_unlock(&drvdata->poll_mutex);\n\t\t\t\tdrvdata->polling_disabled = 0;\n\t\t\t}\n\t\t}\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\n\tmutex_unlock(&drvdata->mutex);\n}\n\nstatic int gpio_rb91x_key_direction_output(struct gpio_chip *gc, unsigned offset,\n\t\t\t\t\t   int value)\n{\n\tswitch (offset) {\n\tcase GPIO_RB91X_KEY_NAND:\n\tcase GPIO_RB91X_KEY_PDIS:\n\t\tgpio_rb91x_key_set(gc, offset, value);\n\t\treturn 0;\n\tdefault:\n\t\treturn -EINVAL;\n\t}\n}\n\nstatic int gpio_rb91x_key_probe(struct platform_device *pdev)\n{\n\tstruct gpio_rb91x_key *drvdata;\n\tstruct gpio_chip *gc;\n\tstruct device *dev = &pdev->dev;\n\tstruct device_node *of_node = dev->of_node;\n\tint r;\n\n\tdrvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);\n\tif (!drvdata)\n\t\treturn -ENOMEM;\n\n\tmutex_init(&drvdata->mutex);\n\tmutex_init(&drvdata->poll_mutex);\n\n\tdrvdata->gpio = devm_gpiod_get(dev, NULL, GPIOD_OUT_LOW);\n\tif (IS_ERR(drvdata->gpio)) {\n\t\tif (PTR_ERR(drvdata->gpio) != -EPROBE_DEFER) {\n\t\t\tdev_err(dev, \"failed to get gpio: %ld\\n\",\n\t\t\t\tPTR_ERR(drvdata->gpio));\n\t\t}\n\t\treturn PTR_ERR(drvdata->gpio);\n\t}\n\n\tgc = &drvdata->gc;\n\tgc->label = GPIO_RB91X_KEY_DRIVER_NAME;\n\tgc->can_sleep = 1;\n\tgc->base = -1;\n\tgc->ngpio = GPIO_RB91X_KEY_NGPIOS;\n\tgc->get = gpio_rb91x_key_get;\n\tgc->set = gpio_rb91x_key_set;\n\tgc->direction_output = gpio_rb91x_key_direction_output;\n\tgc->direction_input = gpio_rb91x_key_direction_input;\n\tgc->of_node = of_node;\n\n\tplatform_set_drvdata(pdev, drvdata);\n\n\tr = gpiochip_add(&drvdata->gc);\n\tif (r) {\n\t\tdev_err(dev, \"gpiochip_add() failed: %d\\n\", r);\n\t\treturn r;\n\t}\n\n\treturn 0;\n}\n\nstatic int gpio_rb91x_key_remove(struct platform_device *pdev)\n{\n\tstruct gpio_rb91x_key *drvdata = platform_get_drvdata(pdev);\n\n\tgpiochip_remove(&drvdata->gc);\n\treturn 0;\n}\n\nstatic const struct of_device_id gpio_rb91x_key_match[] = {\n\t{ .compatible = \"mikrotik,\"GPIO_RB91X_KEY_DRIVER_NAME },\n\t{},\n};\n\nMODULE_DEVICE_TABLE(of, gpio_rb91x_key_match);\n\nstatic struct platform_driver gpio_rb91x_key_driver = {\n\t.probe = gpio_rb91x_key_probe,\n\t.remove = gpio_rb91x_key_remove,\n\t.driver = {\n\t\t.name = GPIO_RB91X_KEY_DRIVER_NAME,\n\t\t.owner = THIS_MODULE,\n\t\t.of_match_table = gpio_rb91x_key_match,\n\t},\n};\n\nmodule_platform_driver(gpio_rb91x_key_driver);\n\nMODULE_DESCRIPTION(\"Driver for reset key gpio line shared with NAND for MikroTik RB91x board series.\");\nMODULE_AUTHOR(\"Denis Kalashnikov <denis281089@gmail.com>\");\nMODULE_LICENSE(\"GPL v2\");\nMODULE_ALIAS(\"platform:\" GPIO_RB91X_KEY_DRIVER_NAME);\n"
  },
  {
    "path": "target/linux/ath79/files/drivers/mfd/rb4xx-cpld.c",
    "content": "// SPDX-License-Identifier: GPL-2.0-only\n/*\n * CPLD driver for the MikroTik RouterBoard 4xx series\n *\n * This driver provides access to a CPLD that interfaces between the SoC SPI bus\n * and other devices. Behind the CPLD there is a NAND flash chip and five LEDs.\n *\n * The CPLD supports SPI two-wire mode, in which two bits are transferred per\n * SPI clock cycle. The second bit is transmitted with the SoC's CS2 pin.\n *\n * The CPLD also acts as a GPIO expander.\n *\n * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>\n * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>\n * Copyright (C) 2015 Bert Vermeulen <bert@biot.com>\n * Copyright (C) 2020 Christopher Hill <ch6574@gmail.com>\n *\n * This file was based on the driver for Linux 2.6.22 published by\n * MikroTik for their RouterBoard 4xx series devices.\n*/\n#include <linux/mfd/core.h>\n#include <linux/spi/spi.h>\n#include <linux/module.h>\n#include <linux/of_platform.h>\n\n#include <mfd/rb4xx-cpld.h>\n\n/* CPLD commands */\n#define CPLD_CMD_WRITE_NAND\t0x08 /* send cmd, n x send data, send idle */\n#define CPLD_CMD_WRITE_CFG\t0x09 /* send cmd, n x send cfg */\n#define CPLD_CMD_READ_NAND\t0x0a /* send cmd, send idle, n x read data */\n#define CPLD_CMD_READ_FAST\t0x0b /* send cmd, 4 x idle, n x read data */\n#define CPLD_CMD_GPIO8_HIGH\t0x0c /* send cmd */\n#define CPLD_CMD_GPIO8_LOW\t0x0d /* send cmd */\n\nstatic int rb4xx_cpld_write_nand(struct rb4xx_cpld *cpld, const void *tx_buf,\n\t\t\t\t unsigned int len)\n{\n\tstruct spi_message m;\n\tstatic const u8 cmd = CPLD_CMD_WRITE_NAND;\n\tstruct spi_transfer t[3] = {\n\t\t{\n\t\t\t.tx_buf = &cmd,\n\t\t\t.len = sizeof(cmd),\n\t\t}, {\n\t\t\t.tx_buf = tx_buf,\n\t\t\t.len = len,\n\t\t\t.tx_nbits = SPI_NBITS_DUAL,\n\t\t}, {\n\t\t\t.len = 1,\n\t\t\t.tx_nbits = SPI_NBITS_DUAL,\n\t\t},\n\t};\n\n\tspi_message_init(&m);\n\tspi_message_add_tail(&t[0], &m);\n\tspi_message_add_tail(&t[1], &m);\n\tspi_message_add_tail(&t[2], &m);\n\treturn spi_sync(cpld->spi, &m);\n}\n\nstatic int rb4xx_cpld_read_nand(struct rb4xx_cpld *cpld, void *rx_buf,\n\t\t\t\tunsigned int len)\n{\n\tstruct spi_message m;\n\tstatic const u8 cmd[2] = {\n\t\tCPLD_CMD_READ_NAND, 0\n\t};\n\tstruct spi_transfer t[2] = {\n\t\t{\n\t\t\t.tx_buf = &cmd,\n\t\t\t.len = sizeof(cmd),\n\t\t}, {\n\t\t\t.rx_buf = rx_buf,\n\t\t\t.len = len,\n\t\t},\n\t};\n\n\tspi_message_init(&m);\n\tspi_message_add_tail(&t[0], &m);\n\tspi_message_add_tail(&t[1], &m);\n\treturn spi_sync(cpld->spi, &m);\n}\n\nstatic int rb4xx_cpld_cmd(struct rb4xx_cpld *cpld, const void *tx_buf,\n\t\t\t  unsigned int len)\n{\n\tstruct spi_message m;\n\tstruct spi_transfer t = {\n\t\t.tx_buf = tx_buf,\n\t\t.len = len,\n\t};\n\n\tspi_message_init(&m);\n\tspi_message_add_tail(&t, &m);\n\treturn spi_sync(cpld->spi, &m);\n}\n\nstatic int rb4xx_cpld_gpio_set_0_7(struct rb4xx_cpld *cpld, u8 values)\n{\n\t/* GPIO 0-7 change can be sent via command + bitfield */\n\tu8 cmd[2] = {\n\t\tCPLD_CMD_WRITE_CFG, values\n\t};\n\treturn rb4xx_cpld_cmd(cpld, &cmd, 2);\n}\n\nstatic int rb4xx_cpld_gpio_set_8(struct rb4xx_cpld *cpld, u8 value)\n{\n\t/* GPIO 8 uses dedicated high/low commands */\n\tu8 cmd = CPLD_CMD_GPIO8_HIGH | !!(value);\n\treturn rb4xx_cpld_cmd(cpld, &cmd, 1);\n}\n\nstatic const struct mfd_cell rb4xx_cpld_cells[] = {\n\t{\n\t\t.name = \"mikrotik,rb4xx-gpio\",\n\t\t.of_compatible = \"mikrotik,rb4xx-gpio\",\n\t}, {\n\t\t.name = \"mikrotik,rb4xx-nand\",\n\t\t.of_compatible = \"mikrotik,rb4xx-nand\",\n\t},\n};\n\nstatic int rb4xx_cpld_probe(struct spi_device *spi)\n{\n\tstruct device *dev = &spi->dev;\n\tstruct rb4xx_cpld *cpld;\n\tint ret;\n\n\tcpld = devm_kzalloc(dev, sizeof(*cpld), GFP_KERNEL);\n\tif (!cpld)\n\t\treturn -ENOMEM;\n\n\tdev_set_drvdata(dev, cpld);\n\n\tcpld->spi\t\t= spi;\n\tcpld->write_nand\t= rb4xx_cpld_write_nand;\n\tcpld->read_nand\t\t= rb4xx_cpld_read_nand;\n\tcpld->gpio_set_0_7\t= rb4xx_cpld_gpio_set_0_7;\n\tcpld->gpio_set_8\t= rb4xx_cpld_gpio_set_8;\n\n\tspi->mode = SPI_MODE_0 | SPI_TX_DUAL;\n\tret = spi_setup(spi);\n\tif (ret)\n\t\treturn ret;\n\n\treturn devm_mfd_add_devices(dev, PLATFORM_DEVID_NONE,\n\t\t\t\t    rb4xx_cpld_cells,\n\t\t\t\t    ARRAY_SIZE(rb4xx_cpld_cells),\n\t\t\t\t    NULL, 0, NULL);\n}\n\nstatic int rb4xx_cpld_remove(struct spi_device *spi)\n{\n\treturn 0;\n}\n\nstatic const struct of_device_id rb4xx_cpld_dt_match[] = {\n\t{ .compatible = \"mikrotik,rb4xx-cpld\", },\n\t{ },\n};\nMODULE_DEVICE_TABLE(of, rb4xx_cpld_dt_match);\n\nstatic struct spi_driver rb4xx_cpld_driver = {\n\t.probe = rb4xx_cpld_probe,\n\t.remove = rb4xx_cpld_remove,\n\t.driver = {\n\t\t.name = \"rb4xx-cpld\",\n\t\t.bus = &spi_bus_type,\n\t\t.of_match_table = of_match_ptr(rb4xx_cpld_dt_match),\n\t},\n};\n\nmodule_spi_driver(rb4xx_cpld_driver);\n\nMODULE_DESCRIPTION(\"Mikrotik RB4xx CPLD driver\");\nMODULE_AUTHOR(\"Gabor Juhos <juhosg@openwrt.org>\");\nMODULE_AUTHOR(\"Imre Kaloz <kaloz@openwrt.org>\");\nMODULE_AUTHOR(\"Bert Vermeulen <bert@biot.com>\");\nMODULE_AUTHOR(\"Christopher Hill <ch6574@gmail.com\");\nMODULE_LICENSE(\"GPL v2\");\n"
  },
  {
    "path": "target/linux/ath79/files/drivers/mtd/nand/raw/ar934x_nand.c",
    "content": "/*\n * Driver for the built-in NAND controller of the Atheros AR934x SoCs\n *\n * Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of the GNU General Public License version 2 as published\n * by the Free Software Foundation.\n */\n\n#include <linux/version.h>\n#include <linux/init.h>\n#include <linux/interrupt.h>\n#include <linux/module.h>\n#include <linux/dma-mapping.h>\n#include <linux/mtd/mtd.h>\n#include <linux/mtd/nand.h>\n#include <linux/mtd/rawnand.h>\n#include <linux/mtd/partitions.h>\n#include <linux/platform_device.h>\n#include <linux/delay.h>\n#include <linux/slab.h>\n#include <linux/of.h>\n#include <linux/of_device.h>\n#include <linux/reset.h>\n\n#define AR934X_NFC_DRIVER_NAME\t\t\"ar934x-nand\"\n\n#define AR934X_NFC_REG_CMD\t\t0x00\n#define AR934X_NFC_REG_CTRL\t\t0x04\n#define AR934X_NFC_REG_STATUS\t\t0x08\n#define AR934X_NFC_REG_INT_MASK\t\t0x0c\n#define AR934X_NFC_REG_INT_STATUS\t0x10\n#define AR934X_NFC_REG_ECC_CTRL\t\t0x14\n#define AR934X_NFC_REG_ECC_OFFSET\t0x18\n#define AR934X_NFC_REG_ADDR0_0\t\t0x1c\n#define AR934X_NFC_REG_ADDR0_1\t\t0x24\n#define AR934X_NFC_REG_ADDR1_0\t\t0x20\n#define AR934X_NFC_REG_ADDR1_1\t\t0x28\n#define AR934X_NFC_REG_SPARE_SIZE\t0x30\n#define AR934X_NFC_REG_PROTECT\t\t0x38\n#define AR934X_NFC_REG_LOOKUP_EN\t0x40\n#define AR934X_NFC_REG_LOOKUP(_x)\t(0x44 + (_i) * 4)\n#define AR934X_NFC_REG_DMA_ADDR\t\t0x64\n#define AR934X_NFC_REG_DMA_COUNT\t0x68\n#define AR934X_NFC_REG_DMA_CTRL\t\t0x6c\n#define AR934X_NFC_REG_MEM_CTRL\t\t0x80\n#define AR934X_NFC_REG_DATA_SIZE\t0x84\n#define AR934X_NFC_REG_READ_STATUS\t0x88\n#define AR934X_NFC_REG_TIME_SEQ\t\t0x8c\n#define AR934X_NFC_REG_TIMINGS_ASYN\t0x90\n#define AR934X_NFC_REG_TIMINGS_SYN\t0x94\n#define AR934X_NFC_REG_FIFO_DATA\t0x98\n#define AR934X_NFC_REG_TIME_MODE\t0x9c\n#define AR934X_NFC_REG_DMA_ADDR_OFFS\t0xa0\n#define AR934X_NFC_REG_FIFO_INIT\t0xb0\n#define AR934X_NFC_REG_GEN_SEQ_CTRL\t0xb4\n\n#define AR934X_NFC_CMD_CMD_SEQ_S\t\t0\n#define AR934X_NFC_CMD_CMD_SEQ_M\t\t0x3f\n#define   AR934X_NFC_CMD_SEQ_1C\t\t\t0x00\n#define   AR934X_NFC_CMD_SEQ_ERASE\t\t0x0e\n#define   AR934X_NFC_CMD_SEQ_12\t\t\t0x0c\n#define   AR934X_NFC_CMD_SEQ_1C1AXR\t\t0x21\n#define   AR934X_NFC_CMD_SEQ_S\t\t\t0x24\n#define   AR934X_NFC_CMD_SEQ_1C3AXR\t\t0x27\n#define   AR934X_NFC_CMD_SEQ_1C5A1CXR\t\t0x2a\n#define   AR934X_NFC_CMD_SEQ_18\t\t\t0x32\n#define AR934X_NFC_CMD_INPUT_SEL_SIU\t\t0\n#define AR934X_NFC_CMD_INPUT_SEL_DMA\t\tBIT(6)\n#define AR934X_NFC_CMD_ADDR_SEL_0\t\t0\n#define AR934X_NFC_CMD_ADDR_SEL_1\t\tBIT(7)\n#define AR934X_NFC_CMD_CMD0_S\t\t\t8\n#define AR934X_NFC_CMD_CMD0_M\t\t\t0xff\n#define AR934X_NFC_CMD_CMD1_S\t\t\t16\n#define AR934X_NFC_CMD_CMD1_M\t\t\t0xff\n#define AR934X_NFC_CMD_CMD2_S\t\t\t24\n#define AR934X_NFC_CMD_CMD2_M\t\t\t0xff\n\n#define AR934X_NFC_CTRL_ADDR_CYCLE0_M\t\t0x7\n#define AR934X_NFC_CTRL_ADDR_CYCLE0_S\t\t0\n#define AR934X_NFC_CTRL_SPARE_EN\t\tBIT(3)\n#define AR934X_NFC_CTRL_INT_EN\t\t\tBIT(4)\n#define AR934X_NFC_CTRL_ECC_EN\t\t\tBIT(5)\n#define AR934X_NFC_CTRL_BLOCK_SIZE_S\t\t6\n#define AR934X_NFC_CTRL_BLOCK_SIZE_M\t\t0x3\n#define   AR934X_NFC_CTRL_BLOCK_SIZE_32\t\t0\n#define   AR934X_NFC_CTRL_BLOCK_SIZE_64\t\t1\n#define   AR934X_NFC_CTRL_BLOCK_SIZE_128\t2\n#define   AR934X_NFC_CTRL_BLOCK_SIZE_256\t3\n#define AR934X_NFC_CTRL_PAGE_SIZE_S\t\t8\n#define AR934X_NFC_CTRL_PAGE_SIZE_M\t\t0x7\n#define   AR934X_NFC_CTRL_PAGE_SIZE_256\t\t0\n#define   AR934X_NFC_CTRL_PAGE_SIZE_512\t\t1\n#define   AR934X_NFC_CTRL_PAGE_SIZE_1024\t2\n#define   AR934X_NFC_CTRL_PAGE_SIZE_2048\t3\n#define   AR934X_NFC_CTRL_PAGE_SIZE_4096\t4\n#define   AR934X_NFC_CTRL_PAGE_SIZE_8192\t5\n#define   AR934X_NFC_CTRL_PAGE_SIZE_16384\t6\n#define AR934X_NFC_CTRL_CUSTOM_SIZE_EN\t\tBIT(11)\n#define AR934X_NFC_CTRL_IO_WIDTH_8BITS\t\t0\n#define AR934X_NFC_CTRL_IO_WIDTH_16BITS\t\tBIT(12)\n#define AR934X_NFC_CTRL_LOOKUP_EN\t\tBIT(13)\n#define AR934X_NFC_CTRL_PROT_EN\t\t\tBIT(14)\n#define AR934X_NFC_CTRL_WORK_MODE_ASYNC\t\t0\n#define AR934X_NFC_CTRL_WORK_MODE_SYNC\t\tBIT(15)\n#define AR934X_NFC_CTRL_ADDR0_AUTO_INC\t\tBIT(16)\n#define AR934X_NFC_CTRL_ADDR1_AUTO_INC\t\tBIT(17)\n#define AR934X_NFC_CTRL_ADDR_CYCLE1_M\t\t0x7\n#define AR934X_NFC_CTRL_ADDR_CYCLE1_S\t\t18\n#define AR934X_NFC_CTRL_SMALL_PAGE\t\tBIT(21)\n\n#define AR934X_NFC_DMA_CTRL_DMA_START\t\tBIT(7)\n#define AR934X_NFC_DMA_CTRL_DMA_DIR_WRITE\t0\n#define AR934X_NFC_DMA_CTRL_DMA_DIR_READ\tBIT(6)\n#define AR934X_NFC_DMA_CTRL_DMA_MODE_SG\t\tBIT(5)\n#define AR934X_NFC_DMA_CTRL_DMA_BURST_S\t\t2\n#define AR934X_NFC_DMA_CTRL_DMA_BURST_0\t\t0\n#define AR934X_NFC_DMA_CTRL_DMA_BURST_1\t\t1\n#define AR934X_NFC_DMA_CTRL_DMA_BURST_2\t\t2\n#define AR934X_NFC_DMA_CTRL_DMA_BURST_3\t\t3\n#define AR934X_NFC_DMA_CTRL_DMA_BURST_4\t\t4\n#define AR934X_NFC_DMA_CTRL_DMA_BURST_5\t\t5\n#define AR934X_NFC_DMA_CTRL_ERR_FLAG\t\tBIT(1)\n#define AR934X_NFC_DMA_CTRL_DMA_READY\t\tBIT(0)\n\n#define AR934X_NFC_INT_DEV_RDY(_x)\t\tBIT(4 + (_x))\n#define AR934X_NFC_INT_CMD_END\t\t\tBIT(1)\n\n#define AR934X_NFC_ECC_CTRL_ERR_THRES_S\t\t8\n#define AR934X_NFC_ECC_CTRL_ERR_THRES_M\t\t0x1f\n#define AR934X_NFC_ECC_CTRL_ECC_CAP_S\t\t5\n#define AR934X_NFC_ECC_CTRL_ECC_CAP_M\t\t0x7\n#define AR934X_NFC_ECC_CTRL_ECC_CAP_2\t\t0\n#define AR934X_NFC_ECC_CTRL_ECC_CAP_4\t\t1\n#define AR934X_NFC_ECC_CTRL_ECC_CAP_6\t\t2\n#define AR934X_NFC_ECC_CTRL_ECC_CAP_8\t\t3\n#define AR934X_NFC_ECC_CTRL_ECC_CAP_10\t\t4\n#define AR934X_NFC_ECC_CTRL_ECC_CAP_12\t\t5\n#define AR934X_NFC_ECC_CTRL_ECC_CAP_14\t\t6\n#define AR934X_NFC_ECC_CTRL_ECC_CAP_16\t\t7\n#define AR934X_NFC_ECC_CTRL_ERR_OVER\t\tBIT(2)\n#define AR934X_NFC_ECC_CTRL_ERR_UNCORRECT\tBIT(1)\n#define AR934X_NFC_ECC_CTRL_ERR_CORRECT\t\tBIT(0)\n\n#define AR934X_NFC_ECC_OFFS_OFSET_M\t\t0xffff\n\n/* default timing values */\n#define AR934X_NFC_TIME_SEQ_DEFAULT\t0x7fff\n#define AR934X_NFC_TIMINGS_ASYN_DEFAULT\t0x22\n#define AR934X_NFC_TIMINGS_SYN_DEFAULT\t0xf\n\n#define AR934X_NFC_ID_BUF_SIZE\t\t8\n#define AR934X_NFC_DEV_READY_TIMEOUT\t25 /* msecs */\n#define AR934X_NFC_DMA_READY_TIMEOUT\t25 /* msecs */\n#define AR934X_NFC_DONE_TIMEOUT\t\t1000\n#define AR934X_NFC_DMA_RETRIES\t\t20\n\n#define AR934X_NFC_USE_IRQ\t\ttrue\n#define AR934X_NFC_IRQ_MASK\t\tAR934X_NFC_INT_DEV_RDY(0)\n\n#define  AR934X_NFC_GENSEQ_SMALL_PAGE_READ\t0x30043\n\n#undef AR934X_NFC_DEBUG_DATA\n#undef AR934X_NFC_DEBUG\n\nstruct mtd_info;\nstruct mtd_partition;\nstruct ar934x_nfc;\n\nstruct ar934x_nfc {\n\tstruct nand_chip nand_chip;\n\tstruct device *parent;\n\tvoid __iomem *base;\n\tbool swap_dma;\n\tint irq;\n\twait_queue_head_t irq_waitq;\n\n\tbool spurious_irq_expected;\n\tu32 irq_status;\n\n\tu32 ctrl_reg;\n\tu32 ecc_ctrl_reg;\n\tu32 ecc_offset_reg;\n\tu32 ecc_thres;\n\tu32 ecc_oob_pos;\n\n\tbool small_page;\n\tunsigned int addr_count0;\n\tunsigned int addr_count1;\n\n\tu8 *buf;\n\tdma_addr_t buf_dma;\n\tunsigned int buf_size;\n\tint buf_index;\n\n\tbool read_id;\n\n\tint erase1_page_addr;\n\n\tint rndout_page_addr;\n\tint rndout_read_cmd;\n\n\tint seqin_page_addr;\n\tint seqin_column;\n\tint seqin_read_cmd;\n\n\tstruct reset_control *rst;\n};\n\nstatic inline __printf(2, 3)\nvoid _nfc_dbg(struct ar934x_nfc *nfc, const char *fmt, ...)\n{\n}\n\n#ifdef AR934X_NFC_DEBUG\n#define nfc_dbg(_nfc, fmt, ...) \\\n\tdev_info((_nfc)->parent, fmt, ##__VA_ARGS__)\n#else\n#define nfc_dbg(_nfc, fmt, ...) \\\n\t_nfc_dbg((_nfc), fmt, ##__VA_ARGS__)\n#endif /* AR934X_NFC_DEBUG */\n\n#ifdef AR934X_NFC_DEBUG_DATA\nstatic void nfc_debug_data(const char *label, void *data, int len)\n{\n\tprint_hex_dump(KERN_WARNING, label, DUMP_PREFIX_OFFSET, 16, 1,\n\t\t       data, len, 0);\n}\n#else\nstatic inline void nfc_debug_data(const char *label, void *data, int len) {}\n#endif /* AR934X_NFC_DEBUG_DATA */\n\nstatic void ar934x_nfc_restart(struct ar934x_nfc *nfc);\n\nstatic inline bool is_all_ff(u8 *buf, int len)\n{\n\twhile (len--)\n\t\tif (buf[len] != 0xff)\n\t\t\treturn false;\n\n\treturn true;\n}\n\nstatic inline void ar934x_nfc_wr(struct ar934x_nfc *nfc, unsigned reg, u32 val)\n{\n\t__raw_writel(val, nfc->base + reg);\n}\n\nstatic inline u32 ar934x_nfc_rr(struct ar934x_nfc *nfc, unsigned reg)\n{\n\treturn __raw_readl(nfc->base + reg);\n}\n\nstatic inline struct ar934x_nfc *mtd_to_ar934x_nfc(struct mtd_info *mtd)\n{\n\tstruct nand_chip *chip = mtd_to_nand(mtd);\n\n\treturn container_of(chip, struct ar934x_nfc, nand_chip);\n}\n\nstatic struct mtd_info *ar934x_nfc_to_mtd(struct ar934x_nfc *nfc)\n{\n\treturn nand_to_mtd(&nfc->nand_chip);\n}\n\nstatic inline bool ar934x_nfc_use_irq(struct ar934x_nfc *nfc)\n{\n\treturn AR934X_NFC_USE_IRQ;\n}\n\nstatic inline void ar934x_nfc_write_cmd_reg(struct ar934x_nfc *nfc, u32 cmd_reg)\n{\n\twmb();\n\n\tar934x_nfc_wr(nfc, AR934X_NFC_REG_CMD, cmd_reg);\n\t/* flush write */\n\tar934x_nfc_rr(nfc, AR934X_NFC_REG_CMD);\n}\n\nstatic bool __ar934x_nfc_dev_ready(struct ar934x_nfc *nfc)\n{\n\tu32 status;\n\n\tstatus = ar934x_nfc_rr(nfc, AR934X_NFC_REG_STATUS);\n\treturn (status & 0xff) == 0xff;\n}\n\nstatic inline bool __ar934x_nfc_is_dma_ready(struct ar934x_nfc *nfc)\n{\n\tu32 status;\n\n\tstatus = ar934x_nfc_rr(nfc, AR934X_NFC_REG_DMA_CTRL);\n\treturn (status & AR934X_NFC_DMA_CTRL_DMA_READY) != 0;\n}\n\nstatic int ar934x_nfc_wait_dev_ready(struct ar934x_nfc *nfc)\n{\n\tunsigned long timeout;\n\n\ttimeout = jiffies + msecs_to_jiffies(AR934X_NFC_DEV_READY_TIMEOUT);\n\tdo {\n\t\tif (__ar934x_nfc_dev_ready(nfc))\n\t\t\treturn 0;\n\t} while time_before(jiffies, timeout);\n\n\tnfc_dbg(nfc, \"timeout waiting for device ready, status:%08x int:%08x\\n\",\n\t\tar934x_nfc_rr(nfc, AR934X_NFC_REG_STATUS),\n\t\tar934x_nfc_rr(nfc, AR934X_NFC_REG_INT_STATUS));\n\treturn -ETIMEDOUT;\n}\n\nstatic int ar934x_nfc_wait_dma_ready(struct ar934x_nfc *nfc)\n{\n\tunsigned long timeout;\n\n\ttimeout = jiffies + msecs_to_jiffies(AR934X_NFC_DMA_READY_TIMEOUT);\n\tdo {\n\t\tif (__ar934x_nfc_is_dma_ready(nfc))\n\t\t\treturn 0;\n\t} while time_before(jiffies, timeout);\n\n\tnfc_dbg(nfc, \"timeout waiting for DMA ready, dma_ctrl:%08x\\n\",\n\t\tar934x_nfc_rr(nfc, AR934X_NFC_REG_DMA_CTRL));\n\treturn -ETIMEDOUT;\n}\n\nstatic int ar934x_nfc_wait_irq(struct ar934x_nfc *nfc)\n{\n\tlong timeout;\n\tint ret;\n\n\ttimeout = wait_event_timeout(nfc->irq_waitq,\n\t\t\t\t(nfc->irq_status & AR934X_NFC_IRQ_MASK) != 0,\n\t\t\t\tmsecs_to_jiffies(AR934X_NFC_DEV_READY_TIMEOUT));\n\n\tret = 0;\n\tif (!timeout) {\n\t\tar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_MASK, 0);\n\t\tar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_STATUS, 0);\n\t\t/* flush write */\n\t\tar934x_nfc_rr(nfc, AR934X_NFC_REG_INT_STATUS);\n\n\t\tnfc_dbg(nfc,\n\t\t\t\"timeout waiting for interrupt, status:%08x\\n\",\n\t\t\tnfc->irq_status);\n\t\tret = -ETIMEDOUT;\n\t}\n\n\tnfc->irq_status = 0;\n\treturn ret;\n}\n\nstatic int ar934x_nfc_wait_done(struct ar934x_nfc *nfc)\n{\n\tint ret;\n\n\tif (ar934x_nfc_use_irq(nfc))\n\t\tret = ar934x_nfc_wait_irq(nfc);\n\telse\n\t\tret = ar934x_nfc_wait_dev_ready(nfc);\n\n\tif (ret)\n\t\treturn ret;\n\n\treturn ar934x_nfc_wait_dma_ready(nfc);\n}\n\nstatic int ar934x_nfc_alloc_buf(struct ar934x_nfc *nfc, unsigned size)\n{\n\tnfc->buf = dma_alloc_coherent(nfc->parent, size,\n\t\t\t\t      &nfc->buf_dma, GFP_KERNEL);\n\tif (nfc->buf == NULL) {\n\t\tdev_err(nfc->parent, \"no memory for DMA buffer\\n\");\n\t\treturn -ENOMEM;\n\t}\n\n\tnfc->buf_size = size;\n\tnfc_dbg(nfc, \"buf:%p size:%u\\n\", nfc->buf, nfc->buf_size);\n\n\treturn 0;\n}\n\nstatic void ar934x_nfc_free_buf(struct ar934x_nfc *nfc)\n{\n\tdma_free_coherent(nfc->parent, nfc->buf_size, nfc->buf, nfc->buf_dma);\n}\n\nstatic void ar934x_nfc_get_addr(struct ar934x_nfc *nfc, int column,\n\t\t\t\tint page_addr, u32 *addr0, u32 *addr1)\n{\n\tu32 a0, a1;\n\n\ta0 = 0;\n\ta1 = 0;\n\n\tif (column == -1) {\n\t\t/* ERASE1 */\n\t\ta0 = (page_addr & 0xffff) << 16;\n\t\ta1 = (page_addr >> 16) & 0xf;\n\t} else if (page_addr != -1) {\n\t\t/* SEQIN, READ0, etc.. */\n\n\t\t/* TODO: handle 16bit bus width */\n\t\tif (nfc->small_page) {\n\t\t\ta0 = column & 0xff;\n\t\t\ta0 |= (page_addr & 0xff) << 8;\n\t\t\ta0 |= ((page_addr >> 8) & 0xff) << 16;\n\t\t\ta0 |= ((page_addr >> 16) & 0xff) << 24;\n\t\t} else {\n\t\t\ta0 = column & 0x0FFF;\n\t\t\ta0 |= (page_addr & 0xffff) << 16;\n\n\t\t\tif (nfc->addr_count0 > 4)\n\t\t\t\ta1 = (page_addr >> 16) & 0xf;\n\t\t}\n\t}\n\n\t*addr0 = a0;\n\t*addr1 = a1;\n}\n\nstatic void ar934x_nfc_send_cmd(struct ar934x_nfc *nfc, unsigned command)\n{\n\tu32 cmd_reg;\n\n\tcmd_reg = AR934X_NFC_CMD_INPUT_SEL_SIU | AR934X_NFC_CMD_ADDR_SEL_0 |\n\t\t  AR934X_NFC_CMD_SEQ_1C;\n\tcmd_reg |= (command & AR934X_NFC_CMD_CMD0_M) << AR934X_NFC_CMD_CMD0_S;\n\n\tar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_STATUS, 0);\n\tar934x_nfc_wr(nfc, AR934X_NFC_REG_CTRL, nfc->ctrl_reg);\n\n\tar934x_nfc_write_cmd_reg(nfc, cmd_reg);\n\tar934x_nfc_wait_dev_ready(nfc);\n}\n\nstatic int ar934x_nfc_do_rw_command(struct ar934x_nfc *nfc, int column,\n\t\t\t\t    int page_addr, int len, u32 cmd_reg,\n\t\t\t\t    u32 ctrl_reg, bool write)\n{\n\tu32 addr0, addr1;\n\tu32 dma_ctrl;\n\tint dir;\n\tint err;\n\tint retries = 0;\n\n\tWARN_ON(len & 3);\n\n\tif (WARN_ON(len > nfc->buf_size))\n\t\tdev_err(nfc->parent, \"len=%d > buf_size=%d\", len,\n\t\t\tnfc->buf_size);\n\n\tif (write) {\n\t\tdma_ctrl = AR934X_NFC_DMA_CTRL_DMA_DIR_WRITE;\n\t\tdir = DMA_TO_DEVICE;\n\t} else {\n\t\tdma_ctrl = AR934X_NFC_DMA_CTRL_DMA_DIR_READ;\n\t\tdir = DMA_FROM_DEVICE;\n\t}\n\n\tar934x_nfc_get_addr(nfc, column, page_addr, &addr0, &addr1);\n\n\tdma_ctrl |= AR934X_NFC_DMA_CTRL_DMA_START |\n\t\t    (AR934X_NFC_DMA_CTRL_DMA_BURST_3 <<\n\t\t     AR934X_NFC_DMA_CTRL_DMA_BURST_S);\n\n\tcmd_reg |= AR934X_NFC_CMD_INPUT_SEL_DMA | AR934X_NFC_CMD_ADDR_SEL_0;\n\tctrl_reg |= AR934X_NFC_CTRL_INT_EN;\n\n\tnfc_dbg(nfc, \"%s a0:%08x a1:%08x len:%x cmd:%08x dma:%08x ctrl:%08x\\n\",\n\t\t(write) ? \"write\" : \"read\",\n\t\taddr0, addr1, len, cmd_reg, dma_ctrl, ctrl_reg);\n\nretry:\n\tar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_STATUS, 0);\n\tar934x_nfc_wr(nfc, AR934X_NFC_REG_ADDR0_0, addr0);\n\tar934x_nfc_wr(nfc, AR934X_NFC_REG_ADDR0_1, addr1);\n\tar934x_nfc_wr(nfc, AR934X_NFC_REG_DMA_ADDR, nfc->buf_dma);\n\tar934x_nfc_wr(nfc, AR934X_NFC_REG_DMA_COUNT, len);\n\tar934x_nfc_wr(nfc, AR934X_NFC_REG_DATA_SIZE, len);\n\tar934x_nfc_wr(nfc, AR934X_NFC_REG_CTRL, ctrl_reg);\n\tar934x_nfc_wr(nfc, AR934X_NFC_REG_DMA_CTRL, dma_ctrl);\n\tar934x_nfc_wr(nfc, AR934X_NFC_REG_ECC_CTRL, nfc->ecc_ctrl_reg);\n\tar934x_nfc_wr(nfc, AR934X_NFC_REG_ECC_OFFSET, nfc->ecc_offset_reg);\n\n\tif (ar934x_nfc_use_irq(nfc)) {\n\t\tar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_MASK,\n\t\t\t      AR934X_NFC_IRQ_MASK);\n\t\t/* flush write */\n\t\tar934x_nfc_rr(nfc, AR934X_NFC_REG_INT_MASK);\n\t}\n\n\tar934x_nfc_write_cmd_reg(nfc, cmd_reg);\n\terr = ar934x_nfc_wait_done(nfc);\n\tif (err) {\n\t\tdev_dbg(nfc->parent, \"%s operation stuck at page %d\\n\",\n\t\t\t(write) ? \"write\" : \"read\", page_addr);\n\n\t\tar934x_nfc_restart(nfc);\n\t\tif (retries++ < AR934X_NFC_DMA_RETRIES)\n\t\t\tgoto retry;\n\n\t\tdev_err(nfc->parent, \"%s operation failed on page %d\\n\",\n\t\t\t(write) ? \"write\" : \"read\", page_addr);\n\t}\n\n\treturn err;\n}\n\nstatic int ar934x_nfc_send_readid(struct ar934x_nfc *nfc, unsigned command)\n{\n\tu32 cmd_reg;\n\tint err;\n\n\tnfc_dbg(nfc, \"readid, cmd:%02x\\n\", command);\n\n\tcmd_reg = AR934X_NFC_CMD_SEQ_1C1AXR;\n\tcmd_reg |= (command & AR934X_NFC_CMD_CMD0_M) << AR934X_NFC_CMD_CMD0_S;\n\n\terr = ar934x_nfc_do_rw_command(nfc, -1, -1, AR934X_NFC_ID_BUF_SIZE,\n\t\t\t\t       cmd_reg, nfc->ctrl_reg, false);\n\n\tnfc_debug_data(\"[id] \", nfc->buf, AR934X_NFC_ID_BUF_SIZE);\n\n\treturn err;\n}\n\nstatic int ar934x_nfc_send_read(struct ar934x_nfc *nfc, unsigned command,\n\t\t\t\tint column, int page_addr, int len)\n{\n\tu32 cmd_reg;\n\tint err;\n\n\tnfc_dbg(nfc, \"read, column=%d page=%d len=%d\\n\",\n\t\tcolumn, page_addr, len);\n\n\tcmd_reg = (command & AR934X_NFC_CMD_CMD0_M) << AR934X_NFC_CMD_CMD0_S;\n\n\tif (nfc->small_page) {\n\t\tcmd_reg |= AR934X_NFC_CMD_SEQ_18;\n\t} else {\n\t\tcmd_reg |= NAND_CMD_READSTART << AR934X_NFC_CMD_CMD1_S;\n\t\tcmd_reg |= AR934X_NFC_CMD_SEQ_1C5A1CXR;\n\t}\n\n\terr = ar934x_nfc_do_rw_command(nfc, column, page_addr, len,\n\t\t\t\t       cmd_reg, nfc->ctrl_reg, false);\n\n\tnfc_debug_data(\"[data] \", nfc->buf, len);\n\n\treturn err;\n}\n\nstatic void ar934x_nfc_send_erase(struct ar934x_nfc *nfc, unsigned command,\n\t\t\t\t  int column, int page_addr)\n{\n\tu32 addr0, addr1;\n\tu32 ctrl_reg;\n\tu32 cmd_reg;\n\n\tar934x_nfc_get_addr(nfc, column, page_addr, &addr0, &addr1);\n\n\tctrl_reg = nfc->ctrl_reg;\n\tif (nfc->small_page) {\n\t\t/* override number of address cycles for the erase command */\n\t\tctrl_reg &= ~(AR934X_NFC_CTRL_ADDR_CYCLE0_M <<\n\t\t\t      AR934X_NFC_CTRL_ADDR_CYCLE0_S);\n\t\tctrl_reg &= ~(AR934X_NFC_CTRL_ADDR_CYCLE1_M <<\n\t\t\t      AR934X_NFC_CTRL_ADDR_CYCLE1_S);\n\t\tctrl_reg &= ~(AR934X_NFC_CTRL_SMALL_PAGE);\n\t\tctrl_reg |= (nfc->addr_count0 + 1) <<\n\t\t\t    AR934X_NFC_CTRL_ADDR_CYCLE0_S;\n\t}\n\n\tcmd_reg = NAND_CMD_ERASE1 << AR934X_NFC_CMD_CMD0_S;\n\tcmd_reg |= command << AR934X_NFC_CMD_CMD1_S;\n\tcmd_reg |= AR934X_NFC_CMD_SEQ_ERASE;\n\n\tnfc_dbg(nfc, \"erase page %d, a0:%08x a1:%08x cmd:%08x ctrl:%08x\\n\",\n\t\tpage_addr, addr0, addr1, cmd_reg, ctrl_reg);\n\n\tar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_STATUS, 0);\n\tar934x_nfc_wr(nfc, AR934X_NFC_REG_CTRL, ctrl_reg);\n\tar934x_nfc_wr(nfc, AR934X_NFC_REG_ADDR0_0, addr0);\n\tar934x_nfc_wr(nfc, AR934X_NFC_REG_ADDR0_1, addr1);\n\n\tar934x_nfc_write_cmd_reg(nfc, cmd_reg);\n\tar934x_nfc_wait_dev_ready(nfc);\n}\n\nstatic int ar934x_nfc_send_write(struct ar934x_nfc *nfc, unsigned command,\n\t\t\t\t int column, int page_addr, int len)\n{\n\tu32 cmd_reg;\n\n\tnfc_dbg(nfc, \"write, column=%d page=%d len=%d\\n\",\n\t\tcolumn, page_addr, len);\n\n\tnfc_debug_data(\"[data] \", nfc->buf, len);\n\n\tcmd_reg = NAND_CMD_SEQIN << AR934X_NFC_CMD_CMD0_S;\n\tcmd_reg |= command << AR934X_NFC_CMD_CMD1_S;\n\tcmd_reg |= AR934X_NFC_CMD_SEQ_12;\n\n\treturn ar934x_nfc_do_rw_command(nfc, column, page_addr, len,\n\t\t\t\t\tcmd_reg, nfc->ctrl_reg, true);\n}\n\nstatic void ar934x_nfc_read_status(struct ar934x_nfc *nfc)\n{\n\tu32 cmd_reg;\n\tu32 status;\n\n\tcmd_reg = NAND_CMD_STATUS << AR934X_NFC_CMD_CMD0_S;\n\tcmd_reg |= AR934X_NFC_CMD_SEQ_S;\n\n\tar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_STATUS, 0);\n\tar934x_nfc_wr(nfc, AR934X_NFC_REG_CTRL, nfc->ctrl_reg);\n\n\tar934x_nfc_write_cmd_reg(nfc, cmd_reg);\n\tar934x_nfc_wait_dev_ready(nfc);\n\n\tstatus = ar934x_nfc_rr(nfc, AR934X_NFC_REG_READ_STATUS);\n\n\tnfc_dbg(nfc, \"read status, cmd:%08x status:%02x\\n\",\n\t\tcmd_reg, (status & 0xff));\n\n\tif (nfc->swap_dma)\n\t\tnfc->buf[0 ^ 3] = status;\n\telse\n\t\tnfc->buf[0] = status;\n}\n\nstatic void ar934x_nfc_cmdfunc(struct nand_chip *nand, unsigned int command,\n\t\t\t       int column, int page_addr)\n{\n\tstruct mtd_info *mtd = nand_to_mtd(nand);\n\tstruct ar934x_nfc *nfc = nand->priv;\n\n\tnfc->read_id = false;\n\tif (command != NAND_CMD_PAGEPROG)\n\t\tnfc->buf_index = 0;\n\n\tswitch (command) {\n\tcase NAND_CMD_RESET:\n\t\tar934x_nfc_send_cmd(nfc, command);\n\t\tbreak;\n\n\tcase NAND_CMD_READID:\n\t\tnfc->read_id = true;\n\t\tar934x_nfc_send_readid(nfc, command);\n\t\tbreak;\n\n\tcase NAND_CMD_READ0:\n\tcase NAND_CMD_READ1:\n\t\tif (nfc->small_page) {\n\t\t\tar934x_nfc_send_read(nfc, command, column, page_addr,\n\t\t\t\t\t     mtd->writesize + mtd->oobsize);\n\t\t} else {\n\t\t\tar934x_nfc_send_read(nfc, command, 0, page_addr,\n\t\t\t\t\t     mtd->writesize + mtd->oobsize);\n\t\t\tnfc->buf_index = column;\n\t\t\tnfc->rndout_page_addr = page_addr;\n\t\t\tnfc->rndout_read_cmd = command;\n\t\t}\n\t\tbreak;\n\n\tcase NAND_CMD_READOOB:\n\t\tif (nfc->small_page)\n\t\t\tar934x_nfc_send_read(nfc, NAND_CMD_READOOB,\n\t\t\t\t\t     column, page_addr,\n\t\t\t\t\t     mtd->oobsize);\n\t\telse\n\t\t\tar934x_nfc_send_read(nfc, NAND_CMD_READ0,\n\t\t\t\t\t     mtd->writesize, page_addr,\n\t\t\t\t\t     mtd->oobsize);\n\t\tbreak;\n\n\tcase NAND_CMD_RNDOUT:\n\t\tif (WARN_ON(nfc->small_page))\n\t\t\tbreak;\n\n\t\t/* emulate subpage read */\n\t\tar934x_nfc_send_read(nfc, nfc->rndout_read_cmd, 0,\n\t\t\t\t     nfc->rndout_page_addr,\n\t\t\t\t     mtd->writesize + mtd->oobsize);\n\t\tnfc->buf_index = column;\n\t\tbreak;\n\n\tcase NAND_CMD_ERASE1:\n\t\tnfc->erase1_page_addr = page_addr;\n\t\tbreak;\n\n\tcase NAND_CMD_ERASE2:\n\t\tar934x_nfc_send_erase(nfc, command, -1, nfc->erase1_page_addr);\n\t\tbreak;\n\n\tcase NAND_CMD_STATUS:\n\t\tar934x_nfc_read_status(nfc);\n\t\tbreak;\n\n\tcase NAND_CMD_SEQIN:\n\t\tif (nfc->small_page) {\n\t\t\t/* output read command */\n\t\t\tif (column >= mtd->writesize) {\n\t\t\t\tcolumn -= mtd->writesize;\n\t\t\t\tnfc->seqin_read_cmd = NAND_CMD_READOOB;\n\t\t\t} else if (column < 256) {\n\t\t\t\tnfc->seqin_read_cmd = NAND_CMD_READ0;\n\t\t\t} else {\n\t\t\t\tcolumn -= 256;\n\t\t\t\tnfc->seqin_read_cmd = NAND_CMD_READ1;\n\t\t\t}\n\t\t} else {\n\t\t\tnfc->seqin_read_cmd = NAND_CMD_READ0;\n\t\t}\n\t\tnfc->seqin_column = column;\n\t\tnfc->seqin_page_addr = page_addr;\n\t\tbreak;\n\n\tcase NAND_CMD_PAGEPROG:\n\t\tif (nand->ecc.engine_type == NAND_ECC_ENGINE_TYPE_ON_HOST) {\n\t\t\t/* the data is already written */\n\t\t\tbreak;\n\t\t}\n\n\t\tif (nfc->small_page)\n\t\t\tar934x_nfc_send_cmd(nfc, nfc->seqin_read_cmd);\n\n\t\tar934x_nfc_send_write(nfc, command, nfc->seqin_column,\n\t\t\t\t      nfc->seqin_page_addr,\n\t\t\t\t      nfc->buf_index);\n\t\tbreak;\n\n\tdefault:\n\t\tdev_err(nfc->parent,\n\t\t\t\"unsupported command: %x, column:%d page_addr=%d\\n\",\n\t\t\tcommand, column, page_addr);\n\t\tbreak;\n\t}\n}\n\nstatic int ar934x_nfc_dev_ready(struct nand_chip *chip)\n{\n\tstruct ar934x_nfc *nfc = chip->priv;\n\n\treturn __ar934x_nfc_dev_ready(nfc);\n}\n\nstatic u8 ar934x_nfc_read_byte(struct nand_chip *chip)\n{\n\tstruct ar934x_nfc *nfc = chip->priv;\n\tu8 data;\n\n\tWARN_ON(nfc->buf_index >= nfc->buf_size);\n\n\tif (nfc->swap_dma || nfc->read_id)\n\t\tdata = nfc->buf[nfc->buf_index ^ 3];\n\telse\n\t\tdata = nfc->buf[nfc->buf_index];\n\n\tnfc->buf_index++;\n\n\treturn data;\n}\n\nstatic void ar934x_nfc_write_buf(struct nand_chip *chip, const u8 *buf, int len)\n{\n\tstruct ar934x_nfc *nfc = chip->priv;\n\tint i;\n\n\tWARN_ON(nfc->buf_index + len > nfc->buf_size);\n\n\tif (nfc->swap_dma) {\n\t\tfor (i = 0; i < len; i++) {\n\t\t\tnfc->buf[nfc->buf_index ^ 3] = buf[i];\n\t\t\tnfc->buf_index++;\n\t\t}\n\t} else {\n\t\tfor (i = 0; i < len; i++) {\n\t\t\tnfc->buf[nfc->buf_index] = buf[i];\n\t\t\tnfc->buf_index++;\n\t\t}\n\t}\n}\n\nstatic void ar934x_nfc_read_buf(struct nand_chip *chip, u8 *buf, int len)\n{\n\tstruct ar934x_nfc *nfc = chip->priv;\n\tint buf_index;\n\tint i;\n\n\tWARN_ON(nfc->buf_index + len > nfc->buf_size);\n\n\tbuf_index = nfc->buf_index;\n\n\tif (nfc->swap_dma || nfc->read_id) {\n\t\tfor (i = 0; i < len; i++) {\n\t\t\tbuf[i] = nfc->buf[buf_index ^ 3];\n\t\t\tbuf_index++;\n\t\t}\n\t} else {\n\t\tfor (i = 0; i < len; i++) {\n\t\t\tbuf[i] = nfc->buf[buf_index];\n\t\t\tbuf_index++;\n\t\t}\n\t}\n\n\tnfc->buf_index = buf_index;\n}\n\nstatic inline void ar934x_nfc_enable_hwecc(struct ar934x_nfc *nfc)\n{\n\tnfc->ctrl_reg |= AR934X_NFC_CTRL_ECC_EN;\n\tnfc->ctrl_reg &= ~AR934X_NFC_CTRL_CUSTOM_SIZE_EN;\n}\n\nstatic inline void ar934x_nfc_disable_hwecc(struct ar934x_nfc *nfc)\n{\n\tnfc->ctrl_reg &= ~AR934X_NFC_CTRL_ECC_EN;\n\tnfc->ctrl_reg |= AR934X_NFC_CTRL_CUSTOM_SIZE_EN;\n}\n\nstatic int ar934x_nfc_read_oob(struct nand_chip *chip,\n\t\t\t       int page)\n{\n\tstruct ar934x_nfc *nfc = chip->priv;\n\tstruct mtd_info *mtd = ar934x_nfc_to_mtd(nfc);\n\tint err;\n\n\tnfc_dbg(nfc, \"read_oob: page:%d\\n\", page);\n\n\terr = ar934x_nfc_send_read(nfc, NAND_CMD_READ0, mtd->writesize, page,\n\t\t\t\t   mtd->oobsize);\n\tif (err)\n\t\treturn err;\n\n\tmemcpy(chip->oob_poi, nfc->buf, mtd->oobsize);\n\n\treturn 0;\n}\n\nstatic int ar934x_nfc_write_oob(struct nand_chip *chip,\n\t\t\t\tint page)\n{\n\tstruct ar934x_nfc *nfc = chip->priv;\n\tstruct mtd_info *mtd = ar934x_nfc_to_mtd(nfc);\n\tnfc_dbg(nfc, \"write_oob: page:%d\\n\", page);\n\n\tmemcpy(nfc->buf, chip->oob_poi, mtd->oobsize);\n\n\treturn ar934x_nfc_send_write(nfc, NAND_CMD_PAGEPROG, mtd->writesize,\n\t\t\t\t     page, mtd->oobsize);\n}\n\nstatic int ar934x_nfc_read_page_raw(\n\t\t\t\t    struct nand_chip *chip, u8 *buf,\n\t\t\t\t    int oob_required, int page)\n{\n\tstruct ar934x_nfc *nfc = chip->priv;\n\tstruct mtd_info *mtd = ar934x_nfc_to_mtd(nfc);\n\tint len;\n\tint err;\n\n\tnfc_dbg(nfc, \"read_page_raw: page:%d oob:%d\\n\", page, oob_required);\n\n\tlen = mtd->writesize;\n\tif (oob_required)\n\t\tlen += mtd->oobsize;\n\n\terr = ar934x_nfc_send_read(nfc, NAND_CMD_READ0, 0, page, len);\n\tif (err)\n\t\treturn err;\n\n\tmemcpy(buf, nfc->buf, mtd->writesize);\n\n\tif (oob_required)\n\t\tmemcpy(chip->oob_poi, &nfc->buf[mtd->writesize], mtd->oobsize);\n\n\treturn 0;\n}\n\nstatic int ar934x_nfc_read_page(struct nand_chip *chip,\n\t\t\t\tu8 *buf, int oob_required, int page)\n{\n\tstruct ar934x_nfc *nfc = chip->priv;\n\tstruct mtd_info *mtd = ar934x_nfc_to_mtd(nfc);\n\tu32 ecc_ctrl;\n\tint max_bitflips = 0;\n\tbool ecc_failed;\n\tbool ecc_corrected;\n\tint err;\n\n\tnfc_dbg(nfc, \"read_page: page:%d oob:%d\\n\", page, oob_required);\n\n\tar934x_nfc_enable_hwecc(nfc);\n\terr = ar934x_nfc_send_read(nfc, NAND_CMD_READ0, 0, page,\n\t\t\t\t   mtd->writesize);\n\tar934x_nfc_disable_hwecc(nfc);\n\n\tif (err)\n\t\treturn err;\n\n\t/* TODO: optimize to avoid memcpy */\n\tmemcpy(buf, nfc->buf, mtd->writesize);\n\n\t/* read the ECC status */\n\tecc_ctrl = ar934x_nfc_rr(nfc, AR934X_NFC_REG_ECC_CTRL);\n\tecc_failed = ecc_ctrl & AR934X_NFC_ECC_CTRL_ERR_UNCORRECT;\n\tecc_corrected = ecc_ctrl & AR934X_NFC_ECC_CTRL_ERR_CORRECT;\n\n\tif (oob_required || ecc_failed) {\n\t\terr = ar934x_nfc_send_read(nfc, NAND_CMD_READ0, mtd->writesize,\n\t\t\t\t\t   page, mtd->oobsize);\n\t\tif (err)\n\t\t\treturn err;\n\n\t\tif (oob_required)\n\t\t\tmemcpy(chip->oob_poi, nfc->buf, mtd->oobsize);\n\t}\n\n\tif (ecc_failed) {\n\t\t/*\n\t\t * The hardware ECC engine reports uncorrectable errors\n\t\t * on empty pages. Check the ECC bytes and the data. If\n\t\t * both contains 0xff bytes only, dont report a failure.\n\t\t *\n\t\t * TODO: prebuild a buffer with 0xff bytes and use memcmp\n\t\t * for better performance?\n\t\t */\n\t\tif (!is_all_ff(&nfc->buf[nfc->ecc_oob_pos], chip->ecc.total) ||\n\t\t    !is_all_ff(buf, mtd->writesize))\n\t\t\t\tmtd->ecc_stats.failed++;\n\t} else if (ecc_corrected) {\n\t\t/*\n\t\t * The hardware does not report the exact count of the\n\t\t * corrected bitflips, use assumptions based on the\n\t\t * threshold.\n\t\t */\n\t\tif (ecc_ctrl & AR934X_NFC_ECC_CTRL_ERR_OVER) {\n\t\t\t/*\n\t\t\t * The number of corrected bitflips exceeds the\n\t\t\t * threshold. Assume the maximum.\n\t\t\t */\n\t\t\tmax_bitflips = chip->ecc.strength * chip->ecc.steps;\n\t\t} else {\n\t\t\tmax_bitflips = nfc->ecc_thres * chip->ecc.steps;\n\t\t}\n\n\t\tmtd->ecc_stats.corrected += max_bitflips;\n\t}\n\n\treturn max_bitflips;\n}\n\nstatic int ar934x_nfc_write_page_raw(\n\t\t\t\t     struct nand_chip *chip, const u8 *buf,\n\t\t\t\t     int oob_required, int page)\n{\n\tstruct ar934x_nfc *nfc = chip->priv;\n\tstruct mtd_info *mtd = ar934x_nfc_to_mtd(nfc);\n\tint len;\n\n\tnfc_dbg(nfc, \"write_page_raw: page:%d oob:%d\\n\", page, oob_required);\n\n\tmemcpy(nfc->buf, buf, mtd->writesize);\n\tlen = mtd->writesize;\n\n\tif (oob_required) {\n\t\tmemcpy(&nfc->buf[mtd->writesize], chip->oob_poi, mtd->oobsize);\n\t\tlen += mtd->oobsize;\n\t}\n\n\treturn ar934x_nfc_send_write(nfc, NAND_CMD_PAGEPROG, 0, page, len);\n}\n\nstatic int ar934x_nfc_write_page(struct nand_chip *chip,\n\t\t\t\t const u8 *buf, int oob_required, int page)\n{\n\tstruct ar934x_nfc *nfc = chip->priv;\n\tstruct mtd_info *mtd = ar934x_nfc_to_mtd(nfc);\n\tint err;\n\n\tnfc_dbg(nfc, \"write_page: page:%d oob:%d\\n\", page, oob_required);\n\n\t/* write OOB first */\n\tif (oob_required &&\n\t    !is_all_ff(chip->oob_poi, mtd->oobsize)) {\n\t\terr = ar934x_nfc_write_oob(chip, page);\n\t\tif (err)\n\t\t\treturn err;\n\t}\n\n\t/* TODO: optimize to avoid memcopy */\n\tmemcpy(nfc->buf, buf, mtd->writesize);\n\n\tar934x_nfc_enable_hwecc(nfc);\n\terr = ar934x_nfc_send_write(nfc, NAND_CMD_PAGEPROG, 0, page,\n\t\t\t\t    mtd->writesize);\n\tar934x_nfc_disable_hwecc(nfc);\n\n\treturn err;\n}\n\nstatic int ar934x_nfc_hw_reset_assert(struct ar934x_nfc *nfc)\n{\n\tint err;\n\n\terr = reset_control_assert(nfc->rst);\n\tudelay(250);\n\treturn err;\n}\n\nstatic int ar934x_nfc_hw_reset_deassert(struct ar934x_nfc *nfc)\n{\n\tint err;\n\n\terr = reset_control_deassert(nfc->rst);\n\tudelay(250);\n\treturn err;\n}\n\nstatic int ar934x_nfc_hw_init(struct ar934x_nfc *nfc)\n{\n\tar934x_nfc_hw_reset_assert(nfc);\n\tar934x_nfc_hw_reset_deassert(nfc);\n\t/*\n\t * setup timings\n\t * TODO: make it configurable via platform data or DT\n\t */\n\tar934x_nfc_wr(nfc, AR934X_NFC_REG_TIME_SEQ,\n\t\t      AR934X_NFC_TIME_SEQ_DEFAULT);\n\tar934x_nfc_wr(nfc, AR934X_NFC_REG_TIMINGS_ASYN,\n\t\t      AR934X_NFC_TIMINGS_ASYN_DEFAULT);\n\tar934x_nfc_wr(nfc, AR934X_NFC_REG_TIMINGS_SYN,\n\t\t      AR934X_NFC_TIMINGS_SYN_DEFAULT);\n\n\t/* disable WP on all chips, and select chip 0 */\n\tar934x_nfc_wr(nfc, AR934X_NFC_REG_MEM_CTRL, 0xff00);\n\n\tar934x_nfc_wr(nfc, AR934X_NFC_REG_DMA_ADDR_OFFS, 0);\n\n\t/* initialize Control register */\n\tnfc->ctrl_reg = AR934X_NFC_CTRL_CUSTOM_SIZE_EN;\n\tar934x_nfc_wr(nfc, AR934X_NFC_REG_CTRL, nfc->ctrl_reg);\n\n\tif (nfc->small_page) {\n\t\t/*  Setup generic sequence register for small page reads. */\n\t\tar934x_nfc_wr(nfc, AR934X_NFC_REG_GEN_SEQ_CTRL,\n\t\t\t      AR934X_NFC_GENSEQ_SMALL_PAGE_READ);\n\t}\n\n\treturn 0;\n}\n\nstatic void ar934x_nfc_restart(struct ar934x_nfc *nfc)\n{\n\tu32 ctrl_reg;\n\n\tctrl_reg = nfc->ctrl_reg;\n\tar934x_nfc_hw_init(nfc);\n\tnfc->ctrl_reg = ctrl_reg;\n\n\tar934x_nfc_send_cmd(nfc, NAND_CMD_RESET);\n}\n\nstatic irqreturn_t ar934x_nfc_irq_handler(int irq, void *data)\n{\n\tstruct ar934x_nfc *nfc = data;\n\tu32 status;\n\n\tstatus = ar934x_nfc_rr(nfc, AR934X_NFC_REG_INT_STATUS);\n\n\tar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_STATUS, 0);\n\t/* flush write */\n\tar934x_nfc_rr(nfc, AR934X_NFC_REG_INT_STATUS);\n\n\tstatus &= ar934x_nfc_rr(nfc, AR934X_NFC_REG_INT_MASK);\n\tif (status) {\n\t\tnfc_dbg(nfc, \"got IRQ, status:%08x\\n\", status);\n\n\t\tnfc->irq_status = status;\n\t\tnfc->spurious_irq_expected = true;\n\t\twake_up(&nfc->irq_waitq);\n\t} else {\n\t\tif (nfc->spurious_irq_expected)\n\t\t\tnfc->spurious_irq_expected = false;\n\t\telse\n\t\t\tdev_warn(nfc->parent, \"spurious interrupt\\n\");\n\t}\n\n\treturn IRQ_HANDLED;\n}\n\nstatic int ar934x_nfc_init_tail(struct mtd_info *mtd)\n{\n\tstruct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd);\n\tstruct nand_chip *chip = &nfc->nand_chip;\n\tu64 chipsize = nanddev_target_size(&chip->base);\n\tu32 ctrl;\n\tu32 t;\n\tint err;\n\n\tswitch (mtd->oobsize) {\n\tcase 16:\n\tcase 64:\n\tcase 128:\n\t\tar934x_nfc_wr(nfc, AR934X_NFC_REG_SPARE_SIZE, mtd->oobsize);\n\t\tbreak;\n\n\tdefault:\n\t\tdev_err(nfc->parent, \"unsupported OOB size: %d bytes\\n\",\n\t\t\tmtd->oobsize);\n\t\treturn -ENXIO;\n\t}\n\n\tctrl = AR934X_NFC_CTRL_CUSTOM_SIZE_EN;\n\n\tswitch (mtd->erasesize / mtd->writesize) {\n\tcase 32:\n\t\tt = AR934X_NFC_CTRL_BLOCK_SIZE_32;\n\t\tbreak;\n\n\tcase 64:\n\t\tt = AR934X_NFC_CTRL_BLOCK_SIZE_64;\n\t\tbreak;\n\n\tcase 128:\n\t\tt = AR934X_NFC_CTRL_BLOCK_SIZE_128;\n\t\tbreak;\n\n\tcase 256:\n\t\tt = AR934X_NFC_CTRL_BLOCK_SIZE_256;\n\t\tbreak;\n\n\tdefault:\n\t\tdev_err(nfc->parent, \"unsupported block size: %u\\n\",\n\t\t\tmtd->erasesize / mtd->writesize);\n\t\treturn -ENXIO;\n\t}\n\n\tctrl |= t << AR934X_NFC_CTRL_BLOCK_SIZE_S;\n\n\tswitch (mtd->writesize) {\n\tcase 256:\n\t\tnfc->small_page = 1;\n\t\tt = AR934X_NFC_CTRL_PAGE_SIZE_256;\n\t\tbreak;\n\n\tcase 512:\n\t\tnfc->small_page = 1;\n\t\tt = AR934X_NFC_CTRL_PAGE_SIZE_512;\n\t\tbreak;\n\n\tcase 1024:\n\t\tt = AR934X_NFC_CTRL_PAGE_SIZE_1024;\n\t\tbreak;\n\n\tcase 2048:\n\t\tt = AR934X_NFC_CTRL_PAGE_SIZE_2048;\n\t\tbreak;\n\n\tcase 4096:\n\t\tt = AR934X_NFC_CTRL_PAGE_SIZE_4096;\n\t\tbreak;\n\n\tcase 8192:\n\t\tt = AR934X_NFC_CTRL_PAGE_SIZE_8192;\n\t\tbreak;\n\n\tcase 16384:\n\t\tt = AR934X_NFC_CTRL_PAGE_SIZE_16384;\n\t\tbreak;\n\n\tdefault:\n\t\tdev_err(nfc->parent, \"unsupported write size: %d bytes\\n\",\n\t\t\tmtd->writesize);\n\t\treturn -ENXIO;\n\t}\n\n\tctrl |= t << AR934X_NFC_CTRL_PAGE_SIZE_S;\n\n\tif (nfc->small_page) {\n\t\tctrl |= AR934X_NFC_CTRL_SMALL_PAGE;\n\n\t\tif (chipsize > (32 << 20)) {\n\t\t\tnfc->addr_count0 = 4;\n\t\t\tnfc->addr_count1 = 3;\n\t\t} else if (chipsize > (2 << 16)) {\n\t\t\tnfc->addr_count0 = 3;\n\t\t\tnfc->addr_count1 = 2;\n\t\t} else {\n\t\t\tnfc->addr_count0 = 2;\n\t\t\tnfc->addr_count1 = 1;\n\t\t}\n\t} else {\n\t\tif (chipsize > (128 << 20)) {\n\t\t\tnfc->addr_count0 = 5;\n\t\t\tnfc->addr_count1 = 3;\n\t\t} else if (chipsize > (8 << 16)) {\n\t\t\tnfc->addr_count0 = 4;\n\t\t\tnfc->addr_count1 = 2;\n\t\t} else {\n\t\t\tnfc->addr_count0 = 3;\n\t\t\tnfc->addr_count1 = 1;\n\t\t}\n\t}\n\n\tctrl |= nfc->addr_count0 << AR934X_NFC_CTRL_ADDR_CYCLE0_S;\n\tctrl |= nfc->addr_count1 << AR934X_NFC_CTRL_ADDR_CYCLE1_S;\n\n\tnfc->ctrl_reg = ctrl;\n\tar934x_nfc_wr(nfc, AR934X_NFC_REG_CTRL, nfc->ctrl_reg);\n\n\tar934x_nfc_free_buf(nfc);\n\terr = ar934x_nfc_alloc_buf(nfc, mtd->writesize + mtd->oobsize);\n\n\treturn err;\n}\n\nstatic int ar934x_nfc_ooblayout_ecc(struct mtd_info *mtd, int section,\n\t\t\t\t    struct mtd_oob_region *oobregion)\n{\n\tif (section)\n\t\treturn -ERANGE;\n\n\toobregion->offset = 20;\n\toobregion->length = 28;\n\n\treturn 0;\n}\n\nstatic int ar934x_nfc_ooblayout_free(struct mtd_info *mtd, int section,\n\t\t\t\t     struct mtd_oob_region *oobregion)\n{\n\tswitch (section) {\n\tcase 0:\n\t\toobregion->offset = 4;\n\t\toobregion->length = 16;\n\t\treturn 0;\n\tcase 1:\n\t\toobregion->offset = 48;\n\t\toobregion->length = 16;\n\t\treturn 0;\n\tdefault:\n\t\treturn -ERANGE;\n\t}\n}\n\nstatic const struct mtd_ooblayout_ops ar934x_nfc_ecclayout_ops = {\n\t.ecc = ar934x_nfc_ooblayout_ecc,\n\t.free = ar934x_nfc_ooblayout_free,\n};\n\nstatic int ar934x_nfc_setup_hwecc(struct ar934x_nfc *nfc)\n{\n\tstruct nand_chip *nand = &nfc->nand_chip;\n\tstruct mtd_info *mtd = nand_to_mtd(nand);\n\tu32 ecc_cap;\n\tu32 ecc_thres;\n\tstruct mtd_oob_region oobregion;\n\n\tswitch (mtd->writesize) {\n\tcase 2048:\n\t\t/*\n\t\t * Writing a subpage separately is not supported, because\n\t\t * the controller only does ECC on full-page accesses.\n\t\t */\n\n\t\tnand->ecc.size = 512;\n\t\tnand->ecc.bytes = 7;\n\t\tnand->ecc.strength = 4;\n\t\tmtd_set_ooblayout(mtd, &ar934x_nfc_ecclayout_ops);\n\t\tbreak;\n\n\tdefault:\n\t\tdev_err(nfc->parent,\n\t\t\t\"hardware ECC is not available for %d byte pages\\n\",\n\t\t\tmtd->writesize);\n\t\treturn -EINVAL;\n\t}\n\n\tBUG_ON(!mtd->ooblayout->ecc);\n\n\tswitch (nand->ecc.strength) {\n\tcase 4:\n\t\tecc_cap = AR934X_NFC_ECC_CTRL_ECC_CAP_4;\n\t\tecc_thres = 4;\n\t\tbreak;\n\n\tdefault:\n\t\tdev_err(nfc->parent, \"unsupported ECC strength %u\\n\",\n\t\t\tnand->ecc.strength);\n\t\treturn -EINVAL;\n\t}\n\n\tnfc->ecc_thres = ecc_thres;\n\tmtd->ooblayout->ecc(mtd, 0, &oobregion);\n\tnfc->ecc_oob_pos = oobregion.offset;\n\n\tnfc->ecc_ctrl_reg = ecc_cap << AR934X_NFC_ECC_CTRL_ECC_CAP_S;\n\tnfc->ecc_ctrl_reg |= ecc_thres << AR934X_NFC_ECC_CTRL_ERR_THRES_S;\n\n\tnfc->ecc_offset_reg = mtd->writesize + nfc->ecc_oob_pos;\n\n\tnand->ecc.read_page = ar934x_nfc_read_page;\n\tnand->ecc.read_page_raw = ar934x_nfc_read_page_raw;\n\tnand->ecc.write_page = ar934x_nfc_write_page;\n\tnand->ecc.write_page_raw = ar934x_nfc_write_page_raw;\n\tnand->ecc.read_oob = ar934x_nfc_read_oob;\n\tnand->ecc.write_oob = ar934x_nfc_write_oob;\n\n\treturn 0;\n}\n\nstatic int ar934x_nfc_attach_chip(struct nand_chip *nand)\n{\n\tstruct mtd_info *mtd = nand_to_mtd(nand);\n\tstruct ar934x_nfc *nfc = nand_get_controller_data(nand);\n\tstruct device *dev = mtd->dev.parent;\n\tint ret;\n\n\tret = ar934x_nfc_init_tail(mtd);\n\tif (ret)\n\t\treturn ret;\n\n\tif (mtd->writesize == 2048)\n\t\tnand->options |= NAND_NO_SUBPAGE_WRITE;\n\n\tif (nand->ecc.engine_type == NAND_ECC_ENGINE_TYPE_ON_HOST) {\n\t\tret = ar934x_nfc_setup_hwecc(nfc);\n\t\tif (ret)\n\t\t\treturn ret;\n\t} else if (nand->ecc.engine_type != NAND_ECC_ENGINE_TYPE_SOFT) {\n\t\tdev_err(dev, \"unknown ECC mode %d\\n\", nand->ecc.engine_type);\n\t\treturn -EINVAL;\n\t} else if ((nand->ecc.algo != NAND_ECC_ALGO_BCH) &&\n\t\t   (nand->ecc.algo != NAND_ECC_ALGO_HAMMING)) {\n\t\tdev_err(dev, \"unknown software ECC algo %d\\n\", nand->ecc.algo);\n\t\treturn -EINVAL;\n\t}\n\n\treturn 0;\n}\n\nstatic u64 ar934x_nfc_dma_mask = DMA_BIT_MASK(32);\n\nstatic void ar934x_nfc_cmd_ctrl(struct nand_chip *chip, int dat,\n\t\t\t\tunsigned int ctrl)\n{\n\tWARN_ON(dat != NAND_CMD_NONE);\n}\n\nstatic const struct nand_controller_ops ar934x_nfc_controller_ops = {\n\t.attach_chip = ar934x_nfc_attach_chip,\n};\n\nstatic int ar934x_nfc_probe(struct platform_device *pdev)\n{\n\tstruct ar934x_nfc *nfc;\n\tstruct resource *res;\n\tstruct mtd_info *mtd;\n\tstruct nand_chip *nand;\n\tint ret;\n\n\tpdev->dev.dma_mask = &ar934x_nfc_dma_mask;\n\tpdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);\n\n\tres = platform_get_resource(pdev, IORESOURCE_MEM, 0);\n\tif (!res) {\n\t\tdev_err(&pdev->dev, \"failed to get I/O memory\\n\");\n\t\treturn -EINVAL;\n\t}\n\n\tnfc = devm_kzalloc(&pdev->dev, sizeof(struct ar934x_nfc), GFP_KERNEL);\n\tif (!nfc) {\n\t\tdev_err(&pdev->dev, \"failed to allocate driver data\\n\");\n\t\treturn -ENOMEM;\n\t}\n\n\tnfc->base = devm_ioremap_resource(&pdev->dev, res);\n\tif (IS_ERR(nfc->base)) {\n\t\tdev_err(&pdev->dev, \"failed to remap I/O memory\\n\");\n\t\treturn PTR_ERR(nfc->base);\n\t}\n\n\tnfc->irq = platform_get_irq(pdev, 0);\n\tif (nfc->irq < 0) {\n\t\tdev_err(&pdev->dev, \"no IRQ resource specified\\n\");\n\t\treturn -EINVAL;\n\t}\n\n\tinit_waitqueue_head(&nfc->irq_waitq);\n\tret = devm_request_irq(&pdev->dev, nfc->irq, ar934x_nfc_irq_handler,\n\t\t\t       0, AR934X_NFC_DRIVER_NAME, nfc);\n\tif (ret) {\n\t\tdev_err(&pdev->dev, \"devm_request_irq failed, err:%d\\n\", ret);\n\t\treturn ret;\n\t}\n\n\tnfc->rst = devm_reset_control_get(&pdev->dev, \"nand\");\n\tif (IS_ERR(nfc->rst)) {\n\t\tdev_err(&pdev->dev, \"Failed to get reset\\n\");\n\t\treturn PTR_ERR(nfc->rst);\n\t}\n\n\tnfc->parent = &pdev->dev;\n\tnfc->swap_dma = of_property_read_bool(pdev->dev.of_node,\n\t\t\t\t\t      \"qca,nand-swap-dma\");\n\n\tnand = &nfc->nand_chip;\n\tmtd = nand_to_mtd(nand);\n\n\tmtd->owner = THIS_MODULE;\n\tmtd->dev.parent = &pdev->dev;\n\tmtd->name = AR934X_NFC_DRIVER_NAME;\n\n\tnand_set_controller_data(nand, nfc);\n\tnand_set_flash_node(nand, pdev->dev.of_node);\n\tnand->legacy.chip_delay = 25;\n\tnand->legacy.dev_ready = ar934x_nfc_dev_ready;\n\tnand->legacy.cmdfunc = ar934x_nfc_cmdfunc;\n\tnand->legacy.cmd_ctrl = ar934x_nfc_cmd_ctrl;\t/* dummy */\n\tnand->legacy.read_byte = ar934x_nfc_read_byte;\n\tnand->legacy.write_buf = ar934x_nfc_write_buf;\n\tnand->legacy.read_buf = ar934x_nfc_read_buf;\n\tnand->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;\t/* default */\n\tnand->priv = nfc;\n\tplatform_set_drvdata(pdev, nfc);\n\n\tret = ar934x_nfc_alloc_buf(nfc, AR934X_NFC_ID_BUF_SIZE);\n\tif (ret)\n\t\treturn ret;\n\n\tret = ar934x_nfc_hw_init(nfc);\n\tif (ret) {\n\t\tdev_err(&pdev->dev, \"hardware init failed, err:%d\\n\", ret);\n\t\tgoto err_free_buf;\n\t}\n\n\tnand->legacy.dummy_controller.ops = &ar934x_nfc_controller_ops;\n\tret = nand_scan(nand, 1);\n\tif (ret) {\n\t\tdev_err(&pdev->dev, \"nand_scan failed, err:%d\\n\", ret);\n\t\tgoto err_free_buf;\n\t}\n\n\tret = mtd_device_register(mtd, NULL, 0);\n\tif (ret) {\n\t\tdev_err(&pdev->dev, \"unable to register mtd, err:%d\\n\", ret);\n\t\tgoto err_free_buf;\n\t}\n\n\treturn 0;\n\nerr_free_buf:\n\tar934x_nfc_free_buf(nfc);\n\treturn ret;\n}\n\nstatic int ar934x_nfc_remove(struct platform_device *pdev)\n{\n\tstruct ar934x_nfc *nfc;\n\n\tnfc = platform_get_drvdata(pdev);\n\tif (nfc) {\n\t\tmtd_device_unregister(nand_to_mtd(&nfc->nand_chip));\n\t\tnand_cleanup(&nfc->nand_chip);\n\t\tar934x_nfc_free_buf(nfc);\n\t}\n\n\treturn 0;\n}\n\nstatic const struct of_device_id ar934x_nfc_match[] = {\n\t{ .compatible = \"qca,\" AR934X_NFC_DRIVER_NAME },\n\t{},\n};\n\nMODULE_DEVICE_TABLE(of, ar934x_nfc_match);\n\nstatic struct platform_driver ar934x_nfc_driver = {\n\t.probe\t\t= ar934x_nfc_probe,\n\t.remove\t\t= ar934x_nfc_remove,\n\t.driver = {\n\t\t.name\t= AR934X_NFC_DRIVER_NAME,\n\t\t.owner\t= THIS_MODULE,\n\t\t.of_match_table = ar934x_nfc_match,\n\t},\n};\n\nmodule_platform_driver(ar934x_nfc_driver);\n\nMODULE_LICENSE(\"GPL v2\");\nMODULE_AUTHOR(\"Gabor Juhos <juhosg@openwrt.org>\");\nMODULE_DESCRIPTION(\"Atheros AR934x NAND Flash Controller driver\");\nMODULE_ALIAS(\"platform:\" AR934X_NFC_DRIVER_NAME);\n"
  },
  {
    "path": "target/linux/ath79/files/drivers/mtd/nand/raw/nand_rb4xx.c",
    "content": "// SPDX-License-Identifier: GPL-2.0-only\n/*\n * NAND driver for the MikroTik RouterBoard 4xx series\n *\n * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>\n * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>\n * Copyright (C) 2015 Bert Vermeulen <bert@biot.com>\n * Copyright (C) 2020 Christopher Hill <ch6574@gmail.com>\n *\n * This file was based on the driver for Linux 2.6.22 published by\n * MikroTik for their RouterBoard 4xx series devices.\n *\n * N.B. driver probe reports \"DMA mask not set\" warnings which are\n * an artifact of using a platform_driver as an MFD device child.\n * See conversation here https://lkml.org/lkml/2020/4/28/675\n */\n#include <linux/platform_device.h>\n#include <linux/mtd/rawnand.h>\n#include <linux/gpio/consumer.h>\n#include <linux/module.h>\n#include <linux/of_device.h>\n#include <linux/version.h>\n\n#include <mfd/rb4xx-cpld.h>\n\nstruct rb4xx_nand {\n\tstruct rb4xx_cpld *cpld;\n\tstruct device *dev;\n\n\tstruct nand_chip chip;\n\tstruct gpio_desc *ale;\n\tstruct gpio_desc *cle;\n\tstruct gpio_desc *nce;\n\tstruct gpio_desc *rdy;\n};\n\nstatic int rb4xx_ooblayout_ecc(struct mtd_info *mtd, int section,\n\t\t\t       struct mtd_oob_region *oobregion)\n{\n\tswitch (section) {\n\tcase 0:\n\t\toobregion->offset = 8;\n\t\toobregion->length = 3;\n\t\treturn 0;\n\tcase 1:\n\t\toobregion->offset = 13;\n\t\toobregion->length = 3;\n\t\treturn 0;\n\tdefault:\n\t\treturn -ERANGE;\n\t}\n}\n\nstatic int rb4xx_ooblayout_free(struct mtd_info *mtd, int section,\n\t\t\t\tstruct mtd_oob_region *oobregion)\n{\n\tswitch (section) {\n\tcase 0:\n\t\toobregion->offset = 0;\n\t\toobregion->length = 4;\n\t\treturn 0;\n\tcase 1:\n\t\toobregion->offset = 4;\n\t\toobregion->length = 1;\n\t\treturn 0;\n\tcase 2:\n\t\toobregion->offset = 6;\n\t\toobregion->length = 2;\n\t\treturn 0;\n\tcase 3:\n\t\toobregion->offset = 11;\n\t\toobregion->length = 2;\n\t\treturn 0;\n\tdefault:\n\t\treturn -ERANGE;\n\t}\n}\n\nstatic const struct mtd_ooblayout_ops rb4xx_nand_ecclayout_ops = {\n\t.ecc = rb4xx_ooblayout_ecc,\n\t.free = rb4xx_ooblayout_free,\n};\n\nstatic u8 rb4xx_nand_read_byte(struct nand_chip *chip)\n{\n\tstruct rb4xx_nand *nand = chip->priv;\n\tstruct rb4xx_cpld *cpld = nand->cpld;\n\tu8 data;\n\tint ret;\n\n\tret = cpld->read_nand(cpld, &data, 1);\n\tif (unlikely(ret))\n\t\treturn 0xff;\n\n\treturn data;\n}\n\nstatic void rb4xx_nand_write_buf(struct nand_chip *chip, const u8 *buf, int len)\n{\n\tstruct rb4xx_nand *nand = chip->priv;\n\tstruct rb4xx_cpld *cpld = nand->cpld;\n\n\tcpld->write_nand(cpld, buf, len);\n}\n\nstatic void rb4xx_nand_read_buf(struct nand_chip *chip, u8 *buf, int len)\n{\n\tstruct rb4xx_nand *nand = chip->priv;\n\tstruct rb4xx_cpld *cpld = nand->cpld;\n\n\tcpld->read_nand(cpld, buf, len);\n}\n\nstatic void rb4xx_nand_cmd_ctrl(struct nand_chip *chip, int dat,\n\t\t\t\tunsigned int ctrl)\n{\n\tstruct rb4xx_nand *nand = chip->priv;\n\tstruct rb4xx_cpld *cpld = nand->cpld;\n\tu8 data = dat;\n\n\tif (ctrl & NAND_CTRL_CHANGE) {\n\t\tgpiod_set_value_cansleep(nand->cle, !!(ctrl & NAND_CLE));\n\t\tgpiod_set_value_cansleep(nand->ale, !!(ctrl & NAND_ALE));\n\t\tgpiod_set_value_cansleep(nand->nce,  !(ctrl & NAND_NCE));\n\t}\n\n\tif (dat != NAND_CMD_NONE)\n\t\tcpld->write_nand(cpld, &data, 1);\n}\n\nstatic int rb4xx_nand_dev_ready(struct nand_chip *chip)\n{\n\tstruct rb4xx_nand *nand = chip->priv;\n\n\treturn gpiod_get_value_cansleep(nand->rdy);\n}\n\nstatic int rb4xx_nand_probe(struct platform_device *pdev)\n{\n\tstruct device *dev = &pdev->dev;\n\tstruct device *parent = dev->parent;\n\tstruct rb4xx_nand *nand;\n\tstruct mtd_info *mtd;\n\tint ret;\n\n\tif (!parent)\n\t\treturn -ENODEV;\n\n\tnand = devm_kzalloc(dev, sizeof(*nand), GFP_KERNEL);\n\tif (!nand)\n\t\treturn -ENOMEM;\n\n\tplatform_set_drvdata(pdev, nand);\n\tnand->cpld\t= dev_get_drvdata(parent);\n\tnand->dev\t= dev;\n\n\tnand->ale = devm_gpiod_get_index(dev, NULL, 0, GPIOD_OUT_LOW);\n\tif (IS_ERR(nand->ale))\n\t\tdev_err(dev, \"missing gpio ALE: %ld\\n\", PTR_ERR(nand->ale));\n\n\tnand->cle = devm_gpiod_get_index(dev, NULL, 1, GPIOD_OUT_LOW);\n\tif (IS_ERR(nand->cle))\n\t\tdev_err(dev, \"missing gpio CLE: %ld\\n\", PTR_ERR(nand->cle));\n\n\tnand->nce = devm_gpiod_get_index(dev, NULL, 2, GPIOD_OUT_LOW);\n\tif (IS_ERR(nand->nce))\n\t\tdev_err(dev, \"missing gpio nCE: %ld\\n\", PTR_ERR(nand->nce));\n\n\tnand->rdy = devm_gpiod_get_index(dev, NULL, 3, GPIOD_IN);\n\tif (IS_ERR(nand->rdy))\n\t\tdev_err(dev, \"missing gpio RDY: %ld\\n\", PTR_ERR(nand->rdy));\n\n\tif (IS_ERR(nand->ale) || IS_ERR(nand->cle) ||\n\t    IS_ERR(nand->nce) || IS_ERR(nand->rdy))\n\t\treturn -ENOENT;\n\n\tgpiod_set_consumer_name(nand->ale, \"mikrotik:nand:ALE\");\n\tgpiod_set_consumer_name(nand->cle, \"mikrotik:nand:CLE\");\n\tgpiod_set_consumer_name(nand->nce, \"mikrotik:nand:nCE\");\n\tgpiod_set_consumer_name(nand->rdy, \"mikrotik:nand:RDY\");\n\n\tmtd = nand_to_mtd(&nand->chip);\n\tmtd->priv\t= nand;\n\tmtd->owner\t= THIS_MODULE;\n\tmtd->dev.parent\t= dev;\n\tmtd_set_of_node(mtd, dev->of_node);\n\n\tif (mtd->writesize == 512)\n\t\tmtd_set_ooblayout(mtd, &rb4xx_nand_ecclayout_ops);\n\n\tnand->chip.ecc.engine_type\t= NAND_ECC_ENGINE_TYPE_SOFT;\n\tnand->chip.ecc.algo\t\t= NAND_ECC_ALGO_HAMMING;\n\tnand->chip.options\t\t= NAND_NO_SUBPAGE_WRITE;\n\tnand->chip.priv\t\t\t= nand;\n\n\tnand->chip.legacy.read_byte\t= rb4xx_nand_read_byte;\n\tnand->chip.legacy.write_buf\t= rb4xx_nand_write_buf;\n\tnand->chip.legacy.read_buf\t= rb4xx_nand_read_buf;\n\tnand->chip.legacy.cmd_ctrl\t= rb4xx_nand_cmd_ctrl;\n\tnand->chip.legacy.dev_ready\t= rb4xx_nand_dev_ready;\n\tnand->chip.legacy.chip_delay\t= 25;\n\n\tret = nand_scan(&nand->chip, 1);\n\tif (ret)\n\t\treturn -ENXIO;\n\n\tret = mtd_device_register(mtd, NULL, 0);\n\tif (ret) {\n\t\tmtd_device_unregister(nand_to_mtd(&nand->chip));\n\t\tnand_cleanup(&nand->chip);\n\t\treturn ret;\n\t}\n\n\treturn 0;\n}\n\nstatic int rb4xx_nand_remove(struct platform_device *pdev)\n{\n\tstruct rb4xx_nand *nand = platform_get_drvdata(pdev);\n\n\tmtd_device_unregister(nand_to_mtd(&nand->chip));\n\tnand_cleanup(&nand->chip);\n\n\treturn 0;\n}\n\nstatic const struct platform_device_id rb4xx_nand_id_table[] = {\n\t{ \"mikrotik,rb4xx-nand\", },\n\t{ },\n};\nMODULE_DEVICE_TABLE(platform, rb4xx_nand_id_table);\n\nstatic struct platform_driver rb4xx_nand_driver = {\n\t.probe = rb4xx_nand_probe,\n\t.remove = rb4xx_nand_remove,\n\t.id_table = rb4xx_nand_id_table,\n\t.driver = {\n\t\t.name = \"rb4xx-nand\",\n\t},\n};\n\nmodule_platform_driver(rb4xx_nand_driver);\n\nMODULE_DESCRIPTION(\"Mikrotik RB4xx NAND driver\");\nMODULE_AUTHOR(\"Gabor Juhos <juhosg@openwrt.org>\");\nMODULE_AUTHOR(\"Imre Kaloz <kaloz@openwrt.org>\");\nMODULE_AUTHOR(\"Bert Vermeulen <bert@biot.com>\");\nMODULE_AUTHOR(\"Christopher Hill <ch6574@gmail.com\");\nMODULE_LICENSE(\"GPL v2\");\n"
  },
  {
    "path": "target/linux/ath79/files/drivers/mtd/nand/raw/rb91x_nand.c",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later\n/*\n *  MikroTik RB91x NAND flash driver\n *\n *  Main part is copied from original driver written by Gabor Juhos.\n *\n *  Copyright (C) 2013-2014 Gabor Juhos <juhosg@openwrt.org>\n */\n\n/*\n * WARNING: to speed up NAND reading/writing we are working with SoC GPIO\n * controller registers directly -- not through standard GPIO API.\n */\n\n#include <linux/kernel.h>\n#include <linux/module.h>\n#include <linux/mtd/rawnand.h>\n#include <linux/mtd/mtd.h>\n#include <linux/mtd/partitions.h>\n#include <linux/platform_device.h>\n#include <linux/gpio/consumer.h>\n#include <linux/version.h>\n#include <linux/of_platform.h>\n\n#include <asm/mach-ath79/ar71xx_regs.h>\n\n/* Bit masks for NAND data lines in ath79 gpio 32-bit register */\n#define RB91X_NAND_NRW_BIT BIT(12)\n#define RB91X_NAND_DATA_BITS (BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) \\\n\t\t\t    | BIT(13) | BIT(14) | BIT(15))\n#define RB91X_NAND_LOW_DATA_MASK\t0x1f\n#define RB91X_NAND_HIGH_DATA_MASK\t0xe0\n#define RB91X_NAND_HIGH_DATA_SHIFT\t8\n\nenum rb91x_nand_gpios {\n\tRB91X_NAND_READ,/* Read */\n\tRB91X_NAND_RDY, /* NAND Ready */\n\tRB91X_NAND_NCE, /* Chip Enable. Active low */\n\tRB91X_NAND_CLE, /* Command Latch Enable */\n\tRB91X_NAND_ALE, /* Address Latch Enable */\n\tRB91X_NAND_NRW, /* Read/Write. Active low */\n\tRB91X_NAND_NLE, /* Latch Enable. Active low */\n\tRB91X_NAND_PDIS, /* Reset Key Poll Disable. Active high */\n\n\tRB91X_NAND_GPIOS,\n};\n\nstruct rb91x_nand_drvdata {\n\tstruct nand_chip chip;\n\tstruct device *dev;\n\tstruct gpio_desc **gpio;\n\tvoid __iomem *ath79_gpio_base;\n};\n\nstatic inline void rb91x_nand_latch_lock(struct rb91x_nand_drvdata *drvdata,\n\t\t\t\t\t int lock)\n{\n\tgpiod_set_value_cansleep(drvdata->gpio[RB91X_NAND_NLE], lock);\n}\n\nstatic inline void rb91x_nand_rst_key_poll_disable(struct rb91x_nand_drvdata *drvdata,\n\t\t\t\t\t\t   int disable)\n{\n\tgpiod_set_value_cansleep(drvdata->gpio[RB91X_NAND_PDIS], disable);\n}\n\nstatic int rb91x_ooblayout_ecc(struct mtd_info *mtd, int section,\n\t\t\t       struct mtd_oob_region *oobregion)\n{\n\tswitch (section) {\n\tcase 0:\n\t\toobregion->offset = 8;\n\t\toobregion->length = 3;\n\t\treturn 0;\n\tcase 1:\n\t\toobregion->offset = 13;\n\t\toobregion->length = 3;\n\t\treturn 0;\n\tdefault:\n\t\treturn -ERANGE;\n\t}\n}\n\nstatic int rb91x_ooblayout_free(struct mtd_info *mtd, int section,\n\t\t\t\tstruct mtd_oob_region *oobregion)\n{\n\tswitch (section) {\n\tcase 0:\n\t\toobregion->offset = 0;\n\t\toobregion->length = 4;\n\t\treturn 0;\n\tcase 1:\n\t\toobregion->offset = 4;\n\t\toobregion->length = 1;\n\t\treturn 0;\n\tcase 2:\n\t\toobregion->offset = 6;\n\t\toobregion->length = 2;\n\t\treturn 0;\n\tcase 3:\n\t\toobregion->offset = 11;\n\t\toobregion->length = 2;\n\t\treturn 0;\n\tdefault:\n\t\treturn -ERANGE;\n\t}\n}\n\nstatic const struct mtd_ooblayout_ops rb91x_nand_ecclayout_ops = {\n\t.ecc = rb91x_ooblayout_ecc,\n\t.free = rb91x_ooblayout_free,\n};\n\nstatic void rb91x_nand_write(struct rb91x_nand_drvdata *drvdata,\n\t\t\t     const u8 *buf,\n\t\t\t     unsigned len)\n{\n\tvoid __iomem *base = drvdata->ath79_gpio_base;\n\tu32 oe_reg;\n\tu32 out_reg;\n\tu32 out;\n\tunsigned i;\n\n\trb91x_nand_latch_lock(drvdata, 1);\n\trb91x_nand_rst_key_poll_disable(drvdata, 1);\n\n\toe_reg = __raw_readl(base + AR71XX_GPIO_REG_OE);\n\tout_reg = __raw_readl(base + AR71XX_GPIO_REG_OUT);\n\n\t/* Set data lines to output mode */\n\t__raw_writel(oe_reg & ~(RB91X_NAND_DATA_BITS | RB91X_NAND_NRW_BIT),\n\t\t     base + AR71XX_GPIO_REG_OE);\n\n\tout = out_reg & ~(RB91X_NAND_DATA_BITS | RB91X_NAND_NRW_BIT);\n\tfor (i = 0; i != len; i++) {\n\t\tu32 data;\n\n\t\tdata = (buf[i] & RB91X_NAND_HIGH_DATA_MASK) <<\n\t\t\tRB91X_NAND_HIGH_DATA_SHIFT;\n\t\tdata |= buf[i] & RB91X_NAND_LOW_DATA_MASK;\n\t\tdata |= out;\n\t\t__raw_writel(data, base + AR71XX_GPIO_REG_OUT);\n\n\t\t/* Deactivate WE line */\n\t\tdata |= RB91X_NAND_NRW_BIT;\n\t\t__raw_writel(data, base + AR71XX_GPIO_REG_OUT);\n\t\t/* Flush write */\n\t\t__raw_readl(base + AR71XX_GPIO_REG_OUT);\n\t}\n\n\t/* Restore registers */\n\t__raw_writel(out_reg, base + AR71XX_GPIO_REG_OUT);\n\t__raw_writel(oe_reg, base + AR71XX_GPIO_REG_OE);\n\t/* Flush write */\n\t__raw_readl(base + AR71XX_GPIO_REG_OUT);\n\n\trb91x_nand_rst_key_poll_disable(drvdata, 0);\n\trb91x_nand_latch_lock(drvdata, 0);\n}\n\nstatic void rb91x_nand_read(struct rb91x_nand_drvdata *drvdata,\n\t\t\t    u8 *read_buf,\n\t\t\t    unsigned len)\n{\n\tvoid __iomem *base = drvdata->ath79_gpio_base;\n\tu32 oe_reg;\n\tu32 out_reg;\n\tunsigned i;\n\n\t/* Enable read mode */\n\tgpiod_set_value_cansleep(drvdata->gpio[RB91X_NAND_READ], 1);\n\n\trb91x_nand_latch_lock(drvdata, 1);\n\trb91x_nand_rst_key_poll_disable(drvdata, 1);\n\n\t/* Save registers */\n\toe_reg = __raw_readl(base + AR71XX_GPIO_REG_OE);\n\tout_reg = __raw_readl(base + AR71XX_GPIO_REG_OUT);\n\n\t/* Set data lines to input mode */\n\t__raw_writel(oe_reg | RB91X_NAND_DATA_BITS,\n\t\t     base + AR71XX_GPIO_REG_OE);\n\n\tfor (i = 0; i < len; i++) {\n\t\tu32 in;\n\t\tu8 data;\n\n\t\t/* Activate RE line */\n\t\t__raw_writel(RB91X_NAND_NRW_BIT, base + AR71XX_GPIO_REG_CLEAR);\n\t\t/* Flush write */\n\t\t__raw_readl(base + AR71XX_GPIO_REG_CLEAR);\n\n\t\t/* Read input lines */\n\t\tin = __raw_readl(base + AR71XX_GPIO_REG_IN);\n\n\t\t/* Deactivate RE line */\n\t\t__raw_writel(RB91X_NAND_NRW_BIT, base + AR71XX_GPIO_REG_SET);\n\n\t\tdata = (in & RB91X_NAND_LOW_DATA_MASK);\n\t\tdata |= (in >> RB91X_NAND_HIGH_DATA_SHIFT) &\n\t\t\tRB91X_NAND_HIGH_DATA_MASK;\n\n\t\tread_buf[i] = data;\n\t}\n\n\t/* Restore  registers */\n\t__raw_writel(out_reg, base + AR71XX_GPIO_REG_OUT);\n\t__raw_writel(oe_reg, base + AR71XX_GPIO_REG_OE);\n\t/* Flush write */\n\t__raw_readl(base + AR71XX_GPIO_REG_OUT);\n\n\trb91x_nand_rst_key_poll_disable(drvdata, 0);\n\trb91x_nand_latch_lock(drvdata, 0);\n\n\t/* Disable read mode */\n\tgpiod_set_value_cansleep(drvdata->gpio[RB91X_NAND_READ], 0);\n}\n\nstatic int rb91x_nand_dev_ready(struct nand_chip *chip)\n{\n\tstruct rb91x_nand_drvdata *drvdata = (struct rb91x_nand_drvdata *)(chip->priv);\n\n\treturn gpiod_get_value_cansleep(drvdata->gpio[RB91X_NAND_RDY]);\n}\n\nstatic void rb91x_nand_cmd_ctrl(struct nand_chip *chip, int cmd,\n\t\t\t\tunsigned int ctrl)\n{\n\tstruct rb91x_nand_drvdata *drvdata = chip->priv;\n\n\tif (ctrl & NAND_CTRL_CHANGE) {\n\t\tgpiod_set_value_cansleep(drvdata->gpio[RB91X_NAND_CLE],\n\t\t\t\t\t(ctrl & NAND_CLE) ? 1 : 0);\n\t\tgpiod_set_value_cansleep(drvdata->gpio[RB91X_NAND_ALE],\n\t\t\t\t\t(ctrl & NAND_ALE) ? 1 : 0);\n\t\tgpiod_set_value_cansleep(drvdata->gpio[RB91X_NAND_NCE],\n\t\t\t\t\t(ctrl & NAND_NCE) ? 1 : 0);\n\t}\n\n\tif (cmd != NAND_CMD_NONE) {\n\t\tu8 t = cmd;\n\n\t\trb91x_nand_write(drvdata, &t, 1);\n\t}\n}\n\nstatic u8 rb91x_nand_read_byte(struct nand_chip *chip)\n{\n\tu8 data = 0xff;\n\n\trb91x_nand_read(chip->priv, &data, 1);\n\n\treturn data;\n}\n\nstatic void rb91x_nand_read_buf(struct nand_chip *chip, u8 *buf, int len)\n{\n\trb91x_nand_read(chip->priv, buf, len);\n}\n\nstatic void rb91x_nand_write_buf(struct nand_chip *chip, const u8 *buf, int len)\n{\n\trb91x_nand_write(chip->priv, buf, len);\n}\n\nstatic void rb91x_nand_release(struct rb91x_nand_drvdata *drvdata)\n{\n\tmtd_device_unregister(nand_to_mtd(&drvdata->chip));\n\tnand_cleanup(&drvdata->chip);\n}\n\nstatic int rb91x_nand_probe(struct platform_device *pdev)\n{\n\tstruct rb91x_nand_drvdata *drvdata;\n\tstruct mtd_info *mtd;\n\tint r;\n\tstruct device *dev = &pdev->dev;\n\tstruct gpio_descs *gpios;\n\n\tdrvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);\n\tif (!drvdata)\n\t\treturn -ENOMEM;\n\n\tplatform_set_drvdata(pdev, drvdata);\n\n\tgpios = gpiod_get_array(dev, NULL, GPIOD_OUT_LOW);\n\tif (IS_ERR(gpios)) {\n\t\tif (PTR_ERR(gpios) != -EPROBE_DEFER) {\n\t\t\tdev_err(dev, \"failed to get gpios: %d\\n\",\n\t\t\t\tPTR_ERR(gpios));\n\t\t}\n\t\treturn PTR_ERR(gpios);\n\t}\n\n\tif (gpios->ndescs != RB91X_NAND_GPIOS) {\n\t\tdev_err(dev, \"expected %d gpios\\n\", RB91X_NAND_GPIOS);\n\t\treturn -EINVAL;\n\t}\n\n\tdrvdata->gpio = gpios->desc;\n\n\tgpiod_direction_input(drvdata->gpio[RB91X_NAND_RDY]);\n\n\tdrvdata->ath79_gpio_base = ioremap(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE);\n\n\tdrvdata->dev = dev;\n\n\tdrvdata->chip.priv = drvdata;\n\n\tdrvdata->chip.legacy.cmd_ctrl = rb91x_nand_cmd_ctrl;\n\tdrvdata->chip.legacy.dev_ready = rb91x_nand_dev_ready;\n\tdrvdata->chip.legacy.read_byte = rb91x_nand_read_byte;\n\tdrvdata->chip.legacy.write_buf = rb91x_nand_write_buf;\n\tdrvdata->chip.legacy.read_buf = rb91x_nand_read_buf;\n\n\tdrvdata->chip.legacy.chip_delay = 25;\n\tdrvdata->chip.ecc.engine_type      = NAND_ECC_ENGINE_TYPE_SOFT;\n\tdrvdata->chip.ecc.algo             = NAND_ECC_ALGO_HAMMING;\n\tdrvdata->chip.options = NAND_NO_SUBPAGE_WRITE;\n\n\tr = nand_scan(&drvdata->chip, 1);\n\tif (r) {\n\t\tdev_err(dev, \"nand_scan() failed: %d\\n\", r);\n\t\treturn r;\n\t}\n\n\tmtd = nand_to_mtd(&drvdata->chip);\n\tmtd->dev.parent = dev;\n\tmtd_set_of_node(mtd, dev->of_node);\n\tmtd->owner = THIS_MODULE;\n\tif (mtd->writesize == 512)\n\t\tmtd_set_ooblayout(mtd, &rb91x_nand_ecclayout_ops);\n\n\tr = mtd_device_register(mtd, NULL, 0);\n\tif (r) {\n\t\tdev_err(dev, \"mtd_device_register() failed: %d\\n\",\n\t\t\tr);\n\t\tgoto err_release_nand;\n\t}\n\n\treturn 0;\n\nerr_release_nand:\n\trb91x_nand_release(drvdata);\n\treturn r;\n}\n\nstatic int rb91x_nand_remove(struct platform_device *pdev)\n{\n\tstruct rb91x_nand_drvdata *drvdata = platform_get_drvdata(pdev);\n\n\trb91x_nand_release(drvdata);\n\n\treturn 0;\n}\n\nstatic const struct of_device_id rb91x_nand_match[] = {\n\t{ .compatible = \"mikrotik,rb91x-nand\" },\n\t{},\n};\n\nMODULE_DEVICE_TABLE(of, rb91x_nand_match);\n\nstatic struct platform_driver rb91x_nand_driver = {\n\t.probe\t= rb91x_nand_probe,\n\t.remove\t= rb91x_nand_remove,\n\t.driver\t= {\n\t\t.name\t= \"rb91x-nand\",\n\t\t.owner\t= THIS_MODULE,\n\t\t.of_match_table = rb91x_nand_match,\n\t},\n};\n\nmodule_platform_driver(rb91x_nand_driver);\n\nMODULE_DESCRIPTION(\"MikrotTik RB91x NAND flash driver\");\nMODULE_VERSION(DRV_VERSION);\nMODULE_AUTHOR(\"Gabor Juhos <juhosg@openwrt.org>\");\nMODULE_AUTHOR(\"Denis Kalashnikov <denis281089@gmail.com>\");\nMODULE_LICENSE(\"GPL v2\");\n"
  },
  {
    "path": "target/linux/ath79/files/drivers/mtd/parsers/parser_cybertan.c",
    "content": "/*\n * Copyright (C) 2009 Christian Daniel <cd@maintech.de>\n * Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>\n *\n * This program is free software; you can redistribute it and/or modify\n * it under the terms of the GNU General Public License as published by\n * the Free Software Foundation; either version 2 of the License, or\n * (at your option) any later version.\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n * GNU General Public License for more details.\n *\n * You should have received a copy of the GNU General Public License\n * along with this program; if not, write to the Free Software\n * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA\n *\n * TRX flash partition table.\n * Based on ar7 map by Felix Fietkau <nbd@nbd.name>\n *\n */\n\n#include <linux/kernel.h>\n#include <linux/module.h>\n#include <linux/slab.h>\n#include <linux/vmalloc.h>\n\n#include <linux/mtd/mtd.h>\n#include <linux/mtd/partitions.h>\n#include <linux/version.h>\n\nstruct cybertan_header {\n\tchar\tmagic[4];\n\tu8\tres1[4];\n\tchar\tfw_date[3];\n\tchar\tfw_ver[3];\n\tchar\tid[4];\n\tchar\thw_ver;\n\tchar\tunused;\n\tu8\tflags[2];\n\tu8\tres2[10];\n} __packed;\n\n#define TRX_PARTS\t3\n#define TRX_MAGIC\t0x30524448\n#define TRX_MAX_OFFSET\t3\n\nstruct trx_header {\n\t__le32 magic;           /* \"HDR0\" */\n\t__le32 len;             /* Length of file including header */\n\t__le32 crc32;           /* 32-bit CRC from flag_version to end of file */\n\t__le32 flag_version;    /* 0:15 flags, 16:31 version */\n\t__le32 offsets[TRX_MAX_OFFSET]; /* Offsets of partitions from start of header */\n} __packed;\n\n#define IH_MAGIC\t0x27051956\t/* Image Magic Number */\n#define IH_NMLEN\t32\t\t/* Image Name Length */\n\nstruct uimage_header {\n\t__be32\tih_magic;\t/* Image Header Magic Number */\n\t__be32\tih_hcrc;\t/* Image Header CRC Checksum */\n\t__be32\tih_time;\t/* Image Creation Timestamp */\n\t__be32\tih_size;\t/* Image Data Size */\n\t__be32\tih_load;\t/* Data» Load  Address */\n\t__be32\tih_ep;\t\t/* Entry Point Address */\n\t__be32\tih_dcrc;\t/* Image Data CRC Checksum */\n\tuint8_t\tih_os;\t\t/* Operating System */\n\tuint8_t\tih_arch;\t/* CPU architecture */\n\tuint8_t\tih_type;\t/* Image Type */\n\tuint8_t\tih_comp;\t/* Compression Type */\n\tuint8_t\tih_name[IH_NMLEN];\t/* Image Name */\n} __packed;\n\nstruct firmware_header {\n\tstruct cybertan_header\tcybertan;\n\tstruct trx_header\ttrx;\n\tstruct uimage_header\tuimage;\n} __packed;\n\nstatic int cybertan_parse_partitions(struct mtd_info *master,\n\t\t\t\t     const struct mtd_partition **pparts,\n\t\t\t\t     struct mtd_part_parser_data *data)\n{\n\tstruct firmware_header header;\n\tstruct trx_header *theader;\n\tstruct uimage_header *uheader;\n\tstruct mtd_partition *trx_parts;\n\tsize_t retlen;\n\tunsigned int kernel_len;\n\tint ret;\n\n\ttrx_parts = kcalloc(TRX_PARTS, sizeof(struct mtd_partition),\n\t\t\t    GFP_KERNEL);\n\tif (!trx_parts) {\n\t\tret = -ENOMEM;\n\t\tgoto out;\n\t}\n\n\tret = mtd_read(master, 0, sizeof(header),\n\t\t       &retlen, (uint8_t *)&header);\n\tif (ret)\n\t\tgoto free_parts;\n\n\tif (retlen != sizeof(header)) {\n\t\tret = -EIO;\n\t\tgoto free_parts;\n\t}\n\n\ttheader = &header.trx;\n\tif (theader->magic != cpu_to_le32(TRX_MAGIC)) {\n\t\tprintk(KERN_NOTICE \"%s: no TRX header found\\n\", master->name);\n\t\tgoto free_parts;\n\t}\n\n\tuheader = &header.uimage;\n\tif (uheader->ih_magic != cpu_to_be32(IH_MAGIC)) {\n\t\tprintk(KERN_NOTICE \"%s: no uImage found\\n\", master->name);\n\t\tgoto free_parts;\n\t}\n\n\tkernel_len = le32_to_cpu(theader->offsets[1]) +\n\t\tsizeof(struct cybertan_header);\n\n\ttrx_parts[0].name = \"header\";\n\ttrx_parts[0].offset = 0;\n\ttrx_parts[0].size = offsetof(struct firmware_header, uimage);\n\ttrx_parts[0].mask_flags = 0;\n\n\ttrx_parts[1].name = \"kernel\";\n\ttrx_parts[1].offset = trx_parts[0].offset + trx_parts[0].size;\n\ttrx_parts[1].size = kernel_len - trx_parts[0].size;\n\ttrx_parts[1].mask_flags = 0;\n\n\ttrx_parts[2].name = \"rootfs\";\n\ttrx_parts[2].offset = trx_parts[1].offset + trx_parts[1].size;\n\ttrx_parts[2].size = master->size - trx_parts[1].size - trx_parts[0].size;\n\ttrx_parts[2].mask_flags = 0;\n\n\t*pparts = trx_parts;\n\treturn TRX_PARTS;\n\nfree_parts:\n\tkfree(trx_parts);\nout:\n\treturn ret;\n}\n\nstatic const struct of_device_id mtd_parser_cybertan_of_match_table[] = {\n\t{ .compatible = \"cybertan,trx\" },\n\t{},\n};\nMODULE_DEVICE_TABLE(of, mtd_parser_cybertan_of_match_table);\n\nstatic struct mtd_part_parser mtd_parser_cybertan = {\n\t.parse_fn = cybertan_parse_partitions,\n\t.name = \"cybertan-trx\",\n\t.of_match_table = mtd_parser_cybertan_of_match_table,\n};\nmodule_mtd_part_parser(mtd_parser_cybertan);\n\nMODULE_LICENSE(\"GPL\");\nMODULE_AUTHOR(\"Christian Daniel <cd@maintech.de>\");\n"
  },
  {
    "path": "target/linux/ath79/files/drivers/net/ethernet/atheros/ag71xx/Kconfig",
    "content": "config AG71XX\n\ttristate \"Atheros AR7XXX/AR9XXX built-in ethernet mac support\"\n\tdepends on ATH79\n\tselect PHYLIB\n\thelp\n\t  If you wish to compile a kernel for AR7XXX/91XXX and enable\n\t  ethernet support, then you should always answer Y to this.\n\nif AG71XX\n\nconfig AG71XX_DEBUG\n\tbool \"Atheros AR71xx built-in ethernet driver debugging\"\n\tdefault n\n\thelp\n\t  Atheros AR71xx built-in ethernet driver debugging messages.\n\nconfig AG71XX_DEBUG_FS\n\tbool \"Atheros AR71xx built-in ethernet driver debugfs support\"\n\tdepends on DEBUG_FS\n\tdefault n\n\thelp\n\t  Say Y, if you need access to various statistics provided by\n\t  the ag71xx driver.\n\nendif\n"
  },
  {
    "path": "target/linux/ath79/files/drivers/net/ethernet/atheros/ag71xx/Makefile",
    "content": "#\n# Makefile for the Atheros AR71xx built-in ethernet macs\n#\n\nag71xx-y\t+= ag71xx_main.o\nag71xx-y\t+= ag71xx_gmac.o\nag71xx-y\t+= ag71xx_ethtool.o\nag71xx-y\t+= ag71xx_phy.o\n\nag71xx-$(CONFIG_AG71XX_DEBUG_FS)\t+= ag71xx_debugfs.o\n\nobj-$(CONFIG_AG71XX)\t+= ag71xx_mdio.o\nobj-$(CONFIG_AG71XX)\t+= ag71xx.o\n"
  },
  {
    "path": "target/linux/ath79/files/drivers/net/ethernet/atheros/ag71xx/ag71xx.h",
    "content": "/*\n *  Atheros AR71xx built-in ethernet mac driver\n *\n *  Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>\n *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>\n *\n *  Based on Atheros' AG7100 driver\n *\n *  This program is free software; you can redistribute it and/or modify it\n *  under the terms of the GNU General Public License version 2 as published\n *  by the Free Software Foundation.\n */\n\n#ifndef __AG71XX_H\n#define __AG71XX_H\n\n#include <linux/kernel.h>\n#include <linux/version.h>\n#include <linux/module.h>\n#include <linux/init.h>\n#include <linux/types.h>\n#include <linux/random.h>\n#include <linux/spinlock.h>\n#include <linux/interrupt.h>\n#include <linux/platform_device.h>\n#include <linux/ethtool.h>\n#include <linux/etherdevice.h>\n#include <linux/if_vlan.h>\n#include <linux/phy.h>\n#include <linux/skbuff.h>\n#include <linux/dma-mapping.h>\n#include <linux/workqueue.h>\n#include <linux/reset.h>\n#include <linux/of.h>\n#include <linux/mfd/syscon.h>\n#include <linux/regmap.h>\n\n#include <linux/bitops.h>\n\n#include <asm/mach-ath79/ar71xx_regs.h>\n#include <asm/mach-ath79/ath79.h>\n\n#define AG71XX_DRV_NAME\t\t\"ag71xx\"\n\n/*\n * For our NAPI weight bigger does *NOT* mean better - it means more\n * D-cache misses and lots more wasted cycles than we'll ever\n * possibly gain from saving instructions.\n */\n#define AG71XX_NAPI_WEIGHT\t32\n#define AG71XX_OOM_REFILL\t(1 + HZ/10)\n\n#define AG71XX_INT_ERR\t(AG71XX_INT_RX_BE | AG71XX_INT_TX_BE)\n#define AG71XX_INT_TX\t(AG71XX_INT_TX_PS)\n#define AG71XX_INT_RX\t(AG71XX_INT_RX_PR | AG71XX_INT_RX_OF)\n\n#define AG71XX_INT_POLL\t(AG71XX_INT_RX | AG71XX_INT_TX)\n#define AG71XX_INT_INIT\t(AG71XX_INT_ERR | AG71XX_INT_POLL)\n\n#define AG71XX_TX_MTU_LEN\t1540\n\n#define AG71XX_TX_RING_SPLIT\t\t512\n#define AG71XX_TX_RING_DS_PER_PKT\tDIV_ROUND_UP(AG71XX_TX_MTU_LEN, \\\n\t\t\t\t\t\t     AG71XX_TX_RING_SPLIT)\n#define AG71XX_TX_RING_SIZE_DEFAULT\t128\n#define AG71XX_RX_RING_SIZE_DEFAULT\t256\n\n#define AG71XX_TX_RING_SIZE_MAX\t\t128\n#define AG71XX_RX_RING_SIZE_MAX\t\t256\n\n#ifdef CONFIG_AG71XX_DEBUG\n#define DBG(fmt, args...)\tpr_debug(fmt, ## args)\n#else\n#define DBG(fmt, args...)\tdo {} while (0)\n#endif\n\n#define ag71xx_assert(_cond)\t\t\t\t\t\t\\\ndo {\t\t\t\t\t\t\t\t\t\\\n\tif (_cond)\t\t\t\t\t\t\t\\\n\t\tbreak;\t\t\t\t\t\t\t\\\n\tprintk(\"%s,%d: assertion failed\\n\", __FILE__, __LINE__);\t\\\n\tBUG();\t\t\t\t\t\t\t\t\\\n} while (0)\n\nstruct ag71xx_desc {\n\tu32\tdata;\n\tu32\tctrl;\n#define DESC_EMPTY\tBIT(31)\n#define DESC_MORE\tBIT(24)\n#define DESC_PKTLEN_M\t0xfff\n\tu32\tnext;\n\tu32\tpad;\n} __attribute__((aligned(4)));\n\n#define AG71XX_DESC_SIZE\troundup(sizeof(struct ag71xx_desc), \\\n\t\t\t\t\tL1_CACHE_BYTES)\n\nstruct ag71xx_buf {\n\tunion {\n\t\tstruct sk_buff\t*skb;\n\t\tvoid\t\t*rx_buf;\n\t};\n\tunion {\n\t\tdma_addr_t\tdma_addr;\n\t\tunsigned int\t\tlen;\n\t};\n};\n\nstruct ag71xx_ring {\n\tstruct ag71xx_buf\t*buf;\n\tu8\t\t\t*descs_cpu;\n\tdma_addr_t\t\tdescs_dma;\n\tu16\t\t\tdesc_split;\n\tu16\t\t\torder;\n\tunsigned int\t\tcurr;\n\tunsigned int\t\tdirty;\n};\n\nstruct ag71xx_int_stats {\n\tunsigned long\t\trx_pr;\n\tunsigned long\t\trx_be;\n\tunsigned long\t\trx_of;\n\tunsigned long\t\ttx_ps;\n\tunsigned long\t\ttx_be;\n\tunsigned long\t\ttx_ur;\n\tunsigned long\t\ttotal;\n};\n\nstruct ag71xx_napi_stats {\n\tunsigned long\t\tnapi_calls;\n\tunsigned long\t\trx_count;\n\tunsigned long\t\trx_packets;\n\tunsigned long\t\trx_packets_max;\n\tunsigned long\t\ttx_count;\n\tunsigned long\t\ttx_packets;\n\tunsigned long\t\ttx_packets_max;\n\n\tunsigned long\t\trx[AG71XX_NAPI_WEIGHT + 1];\n\tunsigned long\t\ttx[AG71XX_NAPI_WEIGHT + 1];\n};\n\nstruct ag71xx_debug {\n\tstruct dentry\t\t*debugfs_dir;\n\n\tstruct ag71xx_int_stats int_stats;\n\tstruct ag71xx_napi_stats napi_stats;\n};\n\nstruct ag71xx {\n\t/*\n\t * Critical data related to the per-packet data path are clustered\n\t * early in this structure to help improve the D-cache footprint.\n\t */\n\tstruct ag71xx_ring\trx_ring ____cacheline_aligned;\n\tstruct ag71xx_ring\ttx_ring ____cacheline_aligned;\n\n\tint\t\t\tmac_idx;\n\n\tu16\t\t\tdesc_pktlen_mask;\n\tu16\t\t\trx_buf_size;\n\tu8\t\t\trx_buf_offset;\n\tu8\t\t\ttx_hang_workaround:1;\n\n\tstruct net_device\t*dev;\n\tstruct platform_device  *pdev;\n\tspinlock_t\t\tlock;\n\tstruct napi_struct\tnapi;\n\tu32\t\t\tmsg_enable;\n\n\t/*\n\t * From this point onwards we're not looking at per-packet fields.\n\t */\n\tvoid __iomem\t\t*mac_base;\n\tvoid __iomem\t\t*mii_base;\n\n\tstruct ag71xx_desc\t*stop_desc;\n\tdma_addr_t\t\tstop_desc_dma;\n\n\tstruct phy_device\t*phy_dev;\n\tvoid\t\t\t*phy_priv;\n\tphy_interface_t\t\tphy_if_mode;\n\n\tunsigned int\t\tlink;\n\tunsigned int\t\tspeed;\n\tint\t\t\tduplex;\n\n\tstruct delayed_work\trestart_work;\n\tstruct timer_list\toom_timer;\n\n\tstruct reset_control *mac_reset;\n\tstruct reset_control *mdio_reset;\n\n\tu32\t\t\tfifodata[3];\n\tu32\t\t\tplldata[3];\n\tu32\t\t\tpllreg[3];\n\tstruct regmap\t\t*pllregmap;\n\n#ifdef CONFIG_AG71XX_DEBUG_FS\n\tstruct ag71xx_debug\tdebug;\n#endif\n};\n\nstruct ag71xx_mdio {\n\tstruct reset_control *mdio_reset;\n\tstruct mii_bus\t\t*mii_bus;\n\tstruct regmap\t\t*mii_regmap;\n};\n\nextern struct ethtool_ops ag71xx_ethtool_ops;\nvoid ag71xx_link_adjust(struct ag71xx *ag);\n\nint ag71xx_phy_connect(struct ag71xx *ag);\nvoid ag71xx_phy_disconnect(struct ag71xx *ag);\n\nstatic inline int ag71xx_desc_empty(struct ag71xx_desc *desc)\n{\n\treturn (desc->ctrl & DESC_EMPTY) != 0;\n}\n\nstatic inline struct ag71xx_desc *\nag71xx_ring_desc(struct ag71xx_ring *ring, int idx)\n{\n\treturn (struct ag71xx_desc *) &ring->descs_cpu[idx * AG71XX_DESC_SIZE];\n}\n\nstatic inline int\nag71xx_ring_size_order(int size)\n{\n\treturn fls(size - 1);\n}\n\n/* Register offsets */\n#define AG71XX_REG_MAC_CFG1\t0x0000\n#define AG71XX_REG_MAC_CFG2\t0x0004\n#define AG71XX_REG_MAC_IPG\t0x0008\n#define AG71XX_REG_MAC_HDX\t0x000c\n#define AG71XX_REG_MAC_MFL\t0x0010\n#define AG71XX_REG_MII_CFG\t0x0020\n#define AG71XX_REG_MII_CMD\t0x0024\n#define AG71XX_REG_MII_ADDR\t0x0028\n#define AG71XX_REG_MII_CTRL\t0x002c\n#define AG71XX_REG_MII_STATUS\t0x0030\n#define AG71XX_REG_MII_IND\t0x0034\n#define AG71XX_REG_MAC_IFCTL\t0x0038\n#define AG71XX_REG_MAC_ADDR1\t0x0040\n#define AG71XX_REG_MAC_ADDR2\t0x0044\n#define AG71XX_REG_FIFO_CFG0\t0x0048\n#define AG71XX_REG_FIFO_CFG1\t0x004c\n#define AG71XX_REG_FIFO_CFG2\t0x0050\n#define AG71XX_REG_FIFO_CFG3\t0x0054\n#define AG71XX_REG_FIFO_CFG4\t0x0058\n#define AG71XX_REG_FIFO_CFG5\t0x005c\n#define AG71XX_REG_FIFO_RAM0\t0x0060\n#define AG71XX_REG_FIFO_RAM1\t0x0064\n#define AG71XX_REG_FIFO_RAM2\t0x0068\n#define AG71XX_REG_FIFO_RAM3\t0x006c\n#define AG71XX_REG_FIFO_RAM4\t0x0070\n#define AG71XX_REG_FIFO_RAM5\t0x0074\n#define AG71XX_REG_FIFO_RAM6\t0x0078\n#define AG71XX_REG_FIFO_RAM7\t0x007c\n\n#define AG71XX_REG_TX_CTRL\t0x0180\n#define AG71XX_REG_TX_DESC\t0x0184\n#define AG71XX_REG_TX_STATUS\t0x0188\n#define AG71XX_REG_RX_CTRL\t0x018c\n#define AG71XX_REG_RX_DESC\t0x0190\n#define AG71XX_REG_RX_STATUS\t0x0194\n#define AG71XX_REG_INT_ENABLE\t0x0198\n#define AG71XX_REG_INT_STATUS\t0x019c\n\n#define AG71XX_REG_FIFO_DEPTH\t0x01a8\n#define AG71XX_REG_RX_SM\t0x01b0\n#define AG71XX_REG_TX_SM\t0x01b4\n\n#define MAC_CFG1_TXE\t\tBIT(0)\t/* Tx Enable */\n#define MAC_CFG1_STX\t\tBIT(1)\t/* Synchronize Tx Enable */\n#define MAC_CFG1_RXE\t\tBIT(2)\t/* Rx Enable */\n#define MAC_CFG1_SRX\t\tBIT(3)\t/* Synchronize Rx Enable */\n#define MAC_CFG1_TFC\t\tBIT(4)\t/* Tx Flow Control Enable */\n#define MAC_CFG1_RFC\t\tBIT(5)\t/* Rx Flow Control Enable */\n#define MAC_CFG1_LB\t\tBIT(8)\t/* Loopback mode */\n#define MAC_CFG1_SR\t\tBIT(31)\t/* Soft Reset */\n\n#define MAC_CFG2_FDX\t\tBIT(0)\n#define MAC_CFG2_CRC_EN\t\tBIT(1)\n#define MAC_CFG2_PAD_CRC_EN\tBIT(2)\n#define MAC_CFG2_LEN_CHECK\tBIT(4)\n#define MAC_CFG2_HUGE_FRAME_EN\tBIT(5)\n#define MAC_CFG2_IF_1000\tBIT(9)\n#define MAC_CFG2_IF_10_100\tBIT(8)\n\n#define FIFO_CFG0_WTM\t\tBIT(0)\t/* Watermark Module */\n#define FIFO_CFG0_RXS\t\tBIT(1)\t/* Rx System Module */\n#define FIFO_CFG0_RXF\t\tBIT(2)\t/* Rx Fabric Module */\n#define FIFO_CFG0_TXS\t\tBIT(3)\t/* Tx System Module */\n#define FIFO_CFG0_TXF\t\tBIT(4)\t/* Tx Fabric Module */\n#define FIFO_CFG0_ALL\t(FIFO_CFG0_WTM | FIFO_CFG0_RXS | FIFO_CFG0_RXF \\\n\t\t\t| FIFO_CFG0_TXS | FIFO_CFG0_TXF)\n\n#define FIFO_CFG0_ENABLE_SHIFT\t8\n\n#define FIFO_CFG4_DE\t\tBIT(0)\t/* Drop Event */\n#define FIFO_CFG4_DV\t\tBIT(1)\t/* RX_DV Event */\n#define FIFO_CFG4_FC\t\tBIT(2)\t/* False Carrier */\n#define FIFO_CFG4_CE\t\tBIT(3)\t/* Code Error */\n#define FIFO_CFG4_CR\t\tBIT(4)\t/* CRC error */\n#define FIFO_CFG4_LM\t\tBIT(5)\t/* Length Mismatch */\n#define FIFO_CFG4_LO\t\tBIT(6)\t/* Length out of range */\n#define FIFO_CFG4_OK\t\tBIT(7)\t/* Packet is OK */\n#define FIFO_CFG4_MC\t\tBIT(8)\t/* Multicast Packet */\n#define FIFO_CFG4_BC\t\tBIT(9)\t/* Broadcast Packet */\n#define FIFO_CFG4_DR\t\tBIT(10)\t/* Dribble */\n#define FIFO_CFG4_LE\t\tBIT(11)\t/* Long Event */\n#define FIFO_CFG4_CF\t\tBIT(12)\t/* Control Frame */\n#define FIFO_CFG4_PF\t\tBIT(13)\t/* Pause Frame */\n#define FIFO_CFG4_UO\t\tBIT(14)\t/* Unsupported Opcode */\n#define FIFO_CFG4_VT\t\tBIT(15)\t/* VLAN tag detected */\n#define FIFO_CFG4_FT\t\tBIT(16)\t/* Frame Truncated */\n#define FIFO_CFG4_UC\t\tBIT(17)\t/* Unicast Packet */\n\n#define FIFO_CFG5_DE\t\tBIT(0)\t/* Drop Event */\n#define FIFO_CFG5_DV\t\tBIT(1)\t/* RX_DV Event */\n#define FIFO_CFG5_FC\t\tBIT(2)\t/* False Carrier */\n#define FIFO_CFG5_CE\t\tBIT(3)\t/* Code Error */\n#define FIFO_CFG5_LM\t\tBIT(4)\t/* Length Mismatch */\n#define FIFO_CFG5_LO\t\tBIT(5)\t/* Length Out of Range */\n#define FIFO_CFG5_OK\t\tBIT(6)\t/* Packet is OK */\n#define FIFO_CFG5_MC\t\tBIT(7)\t/* Multicast Packet */\n#define FIFO_CFG5_BC\t\tBIT(8)\t/* Broadcast Packet */\n#define FIFO_CFG5_DR\t\tBIT(9)\t/* Dribble */\n#define FIFO_CFG5_CF\t\tBIT(10)\t/* Control Frame */\n#define FIFO_CFG5_PF\t\tBIT(11)\t/* Pause Frame */\n#define FIFO_CFG5_UO\t\tBIT(12)\t/* Unsupported Opcode */\n#define FIFO_CFG5_VT\t\tBIT(13)\t/* VLAN tag detected */\n#define FIFO_CFG5_LE\t\tBIT(14)\t/* Long Event */\n#define FIFO_CFG5_FT\t\tBIT(15)\t/* Frame Truncated */\n#define FIFO_CFG5_16\t\tBIT(16)\t/* unknown */\n#define FIFO_CFG5_17\t\tBIT(17)\t/* unknown */\n#define FIFO_CFG5_SF\t\tBIT(18)\t/* Short Frame */\n#define FIFO_CFG5_BM\t\tBIT(19)\t/* Byte Mode */\n\n#define AG71XX_INT_TX_PS\tBIT(0)\n#define AG71XX_INT_TX_UR\tBIT(1)\n#define AG71XX_INT_TX_BE\tBIT(3)\n#define AG71XX_INT_RX_PR\tBIT(4)\n#define AG71XX_INT_RX_OF\tBIT(6)\n#define AG71XX_INT_RX_BE\tBIT(7)\n\n#define MAC_IFCTL_SPEED\t\tBIT(16)\n\n#define MII_CFG_CLK_DIV_4\t0\n#define MII_CFG_CLK_DIV_6\t2\n#define MII_CFG_CLK_DIV_8\t3\n#define MII_CFG_CLK_DIV_10\t4\n#define MII_CFG_CLK_DIV_14\t5\n#define MII_CFG_CLK_DIV_20\t6\n#define MII_CFG_CLK_DIV_28\t7\n#define MII_CFG_CLK_DIV_34\t8\n#define MII_CFG_CLK_DIV_42\t9\n#define MII_CFG_CLK_DIV_50\t10\n#define MII_CFG_CLK_DIV_58\t11\n#define MII_CFG_CLK_DIV_66\t12\n#define MII_CFG_CLK_DIV_74\t13\n#define MII_CFG_CLK_DIV_82\t14\n#define MII_CFG_CLK_DIV_98\t15\n#define MII_CFG_RESET\t\tBIT(31)\n\n#define MII_CMD_WRITE\t\t0x0\n#define MII_CMD_READ\t\t0x1\n#define MII_ADDR_SHIFT\t\t8\n#define MII_IND_BUSY\t\tBIT(0)\n#define MII_IND_INVALID\t\tBIT(2)\n\n#define TX_CTRL_TXE\t\tBIT(0)\t/* Tx Enable */\n\n#define TX_STATUS_PS\t\tBIT(0)\t/* Packet Sent */\n#define TX_STATUS_UR\t\tBIT(1)\t/* Tx Underrun */\n#define TX_STATUS_BE\t\tBIT(3)\t/* Bus Error */\n\n#define RX_CTRL_RXE\t\tBIT(0)\t/* Rx Enable */\n\n#define RX_STATUS_PR\t\tBIT(0)\t/* Packet Received */\n#define RX_STATUS_OF\t\tBIT(2)\t/* Rx Overflow */\n#define RX_STATUS_BE\t\tBIT(3)\t/* Bus Error */\n\nstatic inline void ag71xx_wr(struct ag71xx *ag, unsigned reg, u32 value)\n{\n\t__raw_writel(value, ag->mac_base + reg);\n\t/* flush write */\n\t(void) __raw_readl(ag->mac_base + reg);\n}\n\nstatic inline u32 ag71xx_rr(struct ag71xx *ag, unsigned reg)\n{\n\treturn __raw_readl(ag->mac_base + reg);\n}\n\nstatic inline void ag71xx_sb(struct ag71xx *ag, unsigned reg, u32 mask)\n{\n\tvoid __iomem *r;\n\n\tr = ag->mac_base + reg;\n\t__raw_writel(__raw_readl(r) | mask, r);\n\t/* flush write */\n\t(void) __raw_readl(r);\n}\n\nstatic inline void ag71xx_cb(struct ag71xx *ag, unsigned reg, u32 mask)\n{\n\tvoid __iomem *r;\n\n\tr = ag->mac_base + reg;\n\t__raw_writel(__raw_readl(r) & ~mask, r);\n\t/* flush write */\n\t(void) __raw_readl(r);\n}\n\nstatic inline void ag71xx_int_enable(struct ag71xx *ag, u32 ints)\n{\n\tag71xx_sb(ag, AG71XX_REG_INT_ENABLE, ints);\n}\n\nstatic inline void ag71xx_int_disable(struct ag71xx *ag, u32 ints)\n{\n\tag71xx_cb(ag, AG71XX_REG_INT_ENABLE, ints);\n}\n\n#ifdef CONFIG_AG71XX_DEBUG_FS\nint ag71xx_debugfs_root_init(void);\nvoid ag71xx_debugfs_root_exit(void);\nint ag71xx_debugfs_init(struct ag71xx *ag);\nvoid ag71xx_debugfs_exit(struct ag71xx *ag);\nvoid ag71xx_debugfs_update_int_stats(struct ag71xx *ag, u32 status);\nvoid ag71xx_debugfs_update_napi_stats(struct ag71xx *ag, int rx, int tx);\n#else\nstatic inline int ag71xx_debugfs_root_init(void) { return 0; }\nstatic inline void ag71xx_debugfs_root_exit(void) {}\nstatic inline int ag71xx_debugfs_init(struct ag71xx *ag) { return 0; }\nstatic inline void ag71xx_debugfs_exit(struct ag71xx *ag) {}\nstatic inline void ag71xx_debugfs_update_int_stats(struct ag71xx *ag,\n\t\t\t\t\t\t   u32 status) {}\nstatic inline void ag71xx_debugfs_update_napi_stats(struct ag71xx *ag,\n\t\t\t\t\t\t    int rx, int tx) {}\n#endif /* CONFIG_AG71XX_DEBUG_FS */\n\nint ag71xx_ar7240_init(struct ag71xx *ag, struct device_node *np);\nvoid ag71xx_ar7240_cleanup(struct ag71xx *ag);\n\nint ag71xx_setup_gmac(struct device_node *np);\n\nint ar7240sw_phy_read(struct mii_bus *mii, int addr, int reg);\nint ar7240sw_phy_write(struct mii_bus *mii, int addr, int reg, u16 val);\n\n#endif /* _AG71XX_H */\n"
  },
  {
    "path": "target/linux/ath79/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_debugfs.c",
    "content": "/*\n *  Atheros AR71xx built-in ethernet mac driver\n *\n *  Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>\n *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>\n *\n *  Based on Atheros' AG7100 driver\n *\n *  This program is free software; you can redistribute it and/or modify it\n *  under the terms of the GNU General Public License version 2 as published\n *  by the Free Software Foundation.\n */\n\n#include <linux/debugfs.h>\n\n#include \"ag71xx.h\"\n\nstatic struct dentry *ag71xx_debugfs_root;\n\nstatic int ag71xx_debugfs_generic_open(struct inode *inode, struct file *file)\n{\n\tfile->private_data = inode->i_private;\n\treturn 0;\n}\n\nvoid ag71xx_debugfs_update_int_stats(struct ag71xx *ag, u32 status)\n{\n\tif (status)\n\t\tag->debug.int_stats.total++;\n\tif (status & AG71XX_INT_TX_PS)\n\t\tag->debug.int_stats.tx_ps++;\n\tif (status & AG71XX_INT_TX_UR)\n\t\tag->debug.int_stats.tx_ur++;\n\tif (status & AG71XX_INT_TX_BE)\n\t\tag->debug.int_stats.tx_be++;\n\tif (status & AG71XX_INT_RX_PR)\n\t\tag->debug.int_stats.rx_pr++;\n\tif (status & AG71XX_INT_RX_OF)\n\t\tag->debug.int_stats.rx_of++;\n\tif (status & AG71XX_INT_RX_BE)\n\t\tag->debug.int_stats.rx_be++;\n}\n\nstatic ssize_t read_file_int_stats(struct file *file, char __user *user_buf,\n\t\t\t\t   size_t count, loff_t *ppos)\n{\n#define PR_INT_STAT(_label, _field)\t\t\t\t\t\\\n\tlen += snprintf(buf + len, sizeof(buf) - len,\t\t\t\\\n\t\t\"%20s: %10lu\\n\", _label, ag->debug.int_stats._field);\n\n\tstruct ag71xx *ag = file->private_data;\n\tchar buf[256];\n\tunsigned int len = 0;\n\n\tPR_INT_STAT(\"TX Packet Sent\", tx_ps);\n\tPR_INT_STAT(\"TX Underrun\", tx_ur);\n\tPR_INT_STAT(\"TX Bus Error\", tx_be);\n\tPR_INT_STAT(\"RX Packet Received\", rx_pr);\n\tPR_INT_STAT(\"RX Overflow\", rx_of);\n\tPR_INT_STAT(\"RX Bus Error\", rx_be);\n\tlen += snprintf(buf + len, sizeof(buf) - len, \"\\n\");\n\tPR_INT_STAT(\"Total\", total);\n\n\treturn simple_read_from_buffer(user_buf, count, ppos, buf, len);\n#undef PR_INT_STAT\n}\n\nstatic const struct file_operations ag71xx_fops_int_stats = {\n\t.open\t= ag71xx_debugfs_generic_open,\n\t.read\t= read_file_int_stats,\n\t.owner\t= THIS_MODULE\n};\n\nvoid ag71xx_debugfs_update_napi_stats(struct ag71xx *ag, int rx, int tx)\n{\n\tstruct ag71xx_napi_stats *stats = &ag->debug.napi_stats;\n\n\tif (rx) {\n\t\tstats->rx_count++;\n\t\tstats->rx_packets += rx;\n\t\tif (rx <= AG71XX_NAPI_WEIGHT)\n\t\t\tstats->rx[rx]++;\n\t\tif (rx > stats->rx_packets_max)\n\t\t\tstats->rx_packets_max = rx;\n\t}\n\n\tif (tx) {\n\t\tstats->tx_count++;\n\t\tstats->tx_packets += tx;\n\t\tif (tx <= AG71XX_NAPI_WEIGHT)\n\t\t\tstats->tx[tx]++;\n\t\tif (tx > stats->tx_packets_max)\n\t\t\tstats->tx_packets_max = tx;\n\t}\n}\n\nstatic ssize_t read_file_napi_stats(struct file *file, char __user *user_buf,\n\t\t\t\t    size_t count, loff_t *ppos)\n{\n\tstruct ag71xx *ag = file->private_data;\n\tstruct ag71xx_napi_stats *stats = &ag->debug.napi_stats;\n\tchar *buf;\n\tunsigned int buflen;\n\tunsigned int len = 0;\n\tunsigned long rx_avg = 0;\n\tunsigned long tx_avg = 0;\n\tint ret;\n\tint i;\n\n\tbuflen = 2048;\n\tbuf = kmalloc(buflen, GFP_KERNEL);\n\tif (!buf)\n\t\treturn -ENOMEM;\n\n\tif (stats->rx_count)\n\t\trx_avg = stats->rx_packets / stats->rx_count;\n\n\tif (stats->tx_count)\n\t\ttx_avg = stats->tx_packets / stats->tx_count;\n\n\tlen += snprintf(buf + len, buflen - len, \"%3s  %10s %10s\\n\",\n\t\t\t\"len\", \"rx\", \"tx\");\n\n\tfor (i = 1; i <= AG71XX_NAPI_WEIGHT; i++)\n\t\tlen += snprintf(buf + len, buflen - len,\n\t\t\t\t\"%3d: %10lu %10lu\\n\",\n\t\t\t\ti, stats->rx[i], stats->tx[i]);\n\n\tlen += snprintf(buf + len, buflen - len, \"\\n\");\n\n\tlen += snprintf(buf + len, buflen - len, \"%3s: %10lu %10lu\\n\",\n\t\t\t\"sum\", stats->rx_count, stats->tx_count);\n\tlen += snprintf(buf + len, buflen - len, \"%3s: %10lu %10lu\\n\",\n\t\t\t\"avg\", rx_avg, tx_avg);\n\tlen += snprintf(buf + len, buflen - len, \"%3s: %10lu %10lu\\n\",\n\t\t\t\"max\", stats->rx_packets_max, stats->tx_packets_max);\n\tlen += snprintf(buf + len, buflen - len, \"%3s: %10lu %10lu\\n\",\n\t\t\t\"pkt\", stats->rx_packets, stats->tx_packets);\n\n\tret = simple_read_from_buffer(user_buf, count, ppos, buf, len);\n\tkfree(buf);\n\n\treturn ret;\n}\n\nstatic const struct file_operations ag71xx_fops_napi_stats = {\n\t.open\t= ag71xx_debugfs_generic_open,\n\t.read\t= read_file_napi_stats,\n\t.owner\t= THIS_MODULE\n};\n\n#define DESC_PRINT_LEN\t64\n\nstatic ssize_t read_file_ring(struct file *file, char __user *user_buf,\n\t\t\t      size_t count, loff_t *ppos,\n\t\t\t      struct ag71xx *ag,\n\t\t\t      struct ag71xx_ring *ring,\n\t\t\t      unsigned desc_reg)\n{\n\tint ring_size = BIT(ring->order);\n\tint ring_mask = ring_size - 1;\n\tchar *buf;\n\tunsigned int buflen;\n\tunsigned int len = 0;\n\tunsigned long flags;\n\tssize_t ret;\n\tint curr;\n\tint dirty;\n\tu32 desc_hw;\n\tint i;\n\n\tbuflen = (ring_size * DESC_PRINT_LEN);\n\tbuf = kmalloc(buflen, GFP_KERNEL);\n\tif (!buf)\n\t\treturn -ENOMEM;\n\n\tlen += snprintf(buf + len, buflen - len,\n\t\t\t\"Idx ... %-8s %-8s %-8s %-8s .\\n\",\n\t\t\t\"desc\", \"next\", \"data\", \"ctrl\");\n\n\tspin_lock_irqsave(&ag->lock, flags);\n\n\tcurr = (ring->curr & ring_mask);\n\tdirty = (ring->dirty & ring_mask);\n\tdesc_hw = ag71xx_rr(ag, desc_reg);\n\tfor (i = 0; i < ring_size; i++) {\n\t\tstruct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);\n\t\tu32 desc_dma = ((u32) ring->descs_dma) + i * AG71XX_DESC_SIZE;\n\n\t\tlen += snprintf(buf + len, buflen - len,\n\t\t\t\"%3d %c%c%c %08x %08x %08x %08x %c\\n\",\n\t\t\ti,\n\t\t\t(i == curr) ? 'C' : ' ',\n\t\t\t(i == dirty) ? 'D' : ' ',\n\t\t\t(desc_hw == desc_dma) ? 'H' : ' ',\n\t\t\tdesc_dma,\n\t\t\tdesc->next,\n\t\t\tdesc->data,\n\t\t\tdesc->ctrl,\n\t\t\t(desc->ctrl & DESC_EMPTY) ? 'E' : '*');\n\t}\n\n\tspin_unlock_irqrestore(&ag->lock, flags);\n\n\tret = simple_read_from_buffer(user_buf, count, ppos, buf, len);\n\tkfree(buf);\n\n\treturn ret;\n}\n\nstatic ssize_t read_file_tx_ring(struct file *file, char __user *user_buf,\n\t\t\t\t size_t count, loff_t *ppos)\n{\n\tstruct ag71xx *ag = file->private_data;\n\n\treturn read_file_ring(file, user_buf, count, ppos, ag, &ag->tx_ring,\n\t\t\t      AG71XX_REG_TX_DESC);\n}\n\nstatic const struct file_operations ag71xx_fops_tx_ring = {\n\t.open\t= ag71xx_debugfs_generic_open,\n\t.read\t= read_file_tx_ring,\n\t.owner\t= THIS_MODULE\n};\n\nstatic ssize_t read_file_rx_ring(struct file *file, char __user *user_buf,\n\t\t\t\t size_t count, loff_t *ppos)\n{\n\tstruct ag71xx *ag = file->private_data;\n\n\treturn read_file_ring(file, user_buf, count, ppos, ag, &ag->rx_ring,\n\t\t\t      AG71XX_REG_RX_DESC);\n}\n\nstatic const struct file_operations ag71xx_fops_rx_ring = {\n\t.open\t= ag71xx_debugfs_generic_open,\n\t.read\t= read_file_rx_ring,\n\t.owner\t= THIS_MODULE\n};\n\nvoid ag71xx_debugfs_exit(struct ag71xx *ag)\n{\n\tdebugfs_remove_recursive(ag->debug.debugfs_dir);\n}\n\nint ag71xx_debugfs_init(struct ag71xx *ag)\n{\n\tstruct device *dev = &ag->pdev->dev;\n\n\tag->debug.debugfs_dir = debugfs_create_dir(dev_name(dev),\n\t\t\t\t\t\t   ag71xx_debugfs_root);\n\tif (!ag->debug.debugfs_dir) {\n\t\tdev_err(dev, \"unable to create debugfs directory\\n\");\n\t\treturn -ENOENT;\n\t}\n\n\tdebugfs_create_file(\"int_stats\", S_IRUGO, ag->debug.debugfs_dir,\n\t\t\t    ag, &ag71xx_fops_int_stats);\n\tdebugfs_create_file(\"napi_stats\", S_IRUGO, ag->debug.debugfs_dir,\n\t\t\t    ag, &ag71xx_fops_napi_stats);\n\tdebugfs_create_file(\"tx_ring\", S_IRUGO, ag->debug.debugfs_dir,\n\t\t\t    ag, &ag71xx_fops_tx_ring);\n\tdebugfs_create_file(\"rx_ring\", S_IRUGO, ag->debug.debugfs_dir,\n\t\t\t    ag, &ag71xx_fops_rx_ring);\n\n\treturn 0;\n}\n\nint ag71xx_debugfs_root_init(void)\n{\n\tif (ag71xx_debugfs_root)\n\t\treturn -EBUSY;\n\n\tag71xx_debugfs_root = debugfs_create_dir(KBUILD_MODNAME, NULL);\n\tif (!ag71xx_debugfs_root)\n\t\treturn -ENOENT;\n\n\treturn 0;\n}\n\nvoid ag71xx_debugfs_root_exit(void)\n{\n\tdebugfs_remove(ag71xx_debugfs_root);\n\tag71xx_debugfs_root = NULL;\n}\n"
  },
  {
    "path": "target/linux/ath79/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_ethtool.c",
    "content": "/*\n *  Atheros AR71xx built-in ethernet mac driver\n *\n *  Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>\n *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>\n *\n *  Based on Atheros' AG7100 driver\n *\n *  This program is free software; you can redistribute it and/or modify it\n *  under the terms of the GNU General Public License version 2 as published\n *  by the Free Software Foundation.\n */\n\n#include \"ag71xx.h\"\n\nstruct ag71xx_statistic {\n\tunsigned short offset;\n\tu32 mask;\n\tconst char name[ETH_GSTRING_LEN];\n};\n\nstatic const struct ag71xx_statistic ag71xx_statistics[] = {\n\t{ 0x0080, GENMASK(17, 0), \"Tx/Rx 64 Byte\", },\n\t{ 0x0084, GENMASK(17, 0), \"Tx/Rx 65-127 Byte\", },\n\t{ 0x0088, GENMASK(17, 0), \"Tx/Rx 128-255 Byte\", },\n\t{ 0x008C, GENMASK(17, 0), \"Tx/Rx 256-511 Byte\", },\n\t{ 0x0090, GENMASK(17, 0), \"Tx/Rx 512-1023 Byte\", },\n\t{ 0x0094, GENMASK(17, 0), \"Tx/Rx 1024-1518 Byte\", },\n\t{ 0x0098, GENMASK(17, 0), \"Tx/Rx 1519-1522 Byte VLAN\", },\n\t{ 0x009C, GENMASK(23, 0), \"Rx Byte\", },\n\t{ 0x00A0, GENMASK(17, 0), \"Rx Packet\", },\n\t{ 0x00A4, GENMASK(11, 0), \"Rx FCS Error\", },\n\t{ 0x00A8, GENMASK(17, 0), \"Rx Multicast Packet\", },\n\t{ 0x00AC, GENMASK(21, 0), \"Rx Broadcast Packet\", },\n\t{ 0x00B0, GENMASK(17, 0), \"Rx Control Frame Packet\", },\n\t{ 0x00B4, GENMASK(11, 0), \"Rx Pause Frame Packet\", },\n\t{ 0x00B8, GENMASK(11, 0), \"Rx Unknown OPCode Packet\", },\n\t{ 0x00BC, GENMASK(11, 0), \"Rx Alignment Error\", },\n\t{ 0x00C0, GENMASK(15, 0), \"Rx Frame Length Error\", },\n\t{ 0x00C4, GENMASK(11, 0), \"Rx Code Error\", },\n\t{ 0x00C8, GENMASK(11, 0), \"Rx Carrier Sense Error\", },\n\t{ 0x00CC, GENMASK(11, 0), \"Rx Undersize Packet\", },\n\t{ 0x00D0, GENMASK(11, 0), \"Rx Oversize Packet\", },\n\t{ 0x00D4, GENMASK(11, 0), \"Rx Fragments\", },\n\t{ 0x00D8, GENMASK(11, 0), \"Rx Jabber\", },\n\t{ 0x00DC, GENMASK(11, 0), \"Rx Dropped Packet\", },\n\t{ 0x00E0, GENMASK(23, 0), \"Tx Byte\", },\n\t{ 0x00E4, GENMASK(17, 0), \"Tx Packet\", },\n\t{ 0x00E8, GENMASK(17, 0), \"Tx Multicast Packet\", },\n\t{ 0x00EC, GENMASK(17, 0), \"Tx Broadcast Packet\", },\n\t{ 0x00F0, GENMASK(11, 0), \"Tx Pause Control Frame\", },\n\t{ 0x00F4, GENMASK(11, 0), \"Tx Deferral Packet\", },\n\t{ 0x00F8, GENMASK(11, 0), \"Tx Excessive Deferral Packet\", },\n\t{ 0x00FC, GENMASK(11, 0), \"Tx Single Collision Packet\", },\n\t{ 0x0100, GENMASK(11, 0), \"Tx Multiple Collision\", },\n\t{ 0x0104, GENMASK(11, 0), \"Tx Late Collision Packet\", },\n\t{ 0x0108, GENMASK(11, 0), \"Tx Excessive Collision Packet\", },\n\t{ 0x010C, GENMASK(12, 0), \"Tx Total Collision\", },\n\t{ 0x0110, GENMASK(11, 0), \"Tx Pause Frames Honored\", },\n\t{ 0x0114, GENMASK(11, 0), \"Tx Drop Frame\", },\n\t{ 0x0118, GENMASK(11, 0), \"Tx Jabber Frame\", },\n\t{ 0x011C, GENMASK(11, 0), \"Tx FCS Error\", },\n\t{ 0x0120, GENMASK(11, 0), \"Tx Control Frame\", },\n\t{ 0x0124, GENMASK(11, 0), \"Tx Oversize Frame\", },\n\t{ 0x0128, GENMASK(11, 0), \"Tx Undersize Frame\", },\n\t{ 0x012C, GENMASK(11, 0), \"Tx Fragment\", },\n};\n\nstatic u32 ag71xx_ethtool_get_msglevel(struct net_device *dev)\n{\n\tstruct ag71xx *ag = netdev_priv(dev);\n\n\treturn ag->msg_enable;\n}\n\nstatic void ag71xx_ethtool_set_msglevel(struct net_device *dev, u32 msg_level)\n{\n\tstruct ag71xx *ag = netdev_priv(dev);\n\n\tag->msg_enable = msg_level;\n}\n\nstatic void ag71xx_ethtool_get_ringparam(struct net_device *dev,\n\t\t\t\t\t struct ethtool_ringparam *er)\n{\n\tstruct ag71xx *ag = netdev_priv(dev);\n\n\ter->tx_max_pending = AG71XX_TX_RING_SIZE_MAX;\n\ter->rx_max_pending = AG71XX_RX_RING_SIZE_MAX;\n\ter->rx_mini_max_pending = 0;\n\ter->rx_jumbo_max_pending = 0;\n\n\ter->tx_pending = BIT(ag->tx_ring.order);\n\ter->rx_pending = BIT(ag->rx_ring.order);\n\ter->rx_mini_pending = 0;\n\ter->rx_jumbo_pending = 0;\n\n\tif (ag->tx_ring.desc_split)\n\t\ter->tx_pending /= AG71XX_TX_RING_DS_PER_PKT;\n}\n\nstatic int ag71xx_ethtool_set_ringparam(struct net_device *dev,\n\t\t\t\t\tstruct ethtool_ringparam *er)\n{\n\tstruct ag71xx *ag = netdev_priv(dev);\n\tunsigned tx_size;\n\tunsigned rx_size;\n\tint err = 0;\n\n\tif (er->rx_mini_pending != 0||\n\t    er->rx_jumbo_pending != 0 ||\n\t    er->rx_pending == 0 ||\n\t    er->tx_pending == 0)\n\t\treturn -EINVAL;\n\n\ttx_size = er->tx_pending < AG71XX_TX_RING_SIZE_MAX ?\n\t\t  er->tx_pending : AG71XX_TX_RING_SIZE_MAX;\n\n\trx_size = er->rx_pending < AG71XX_RX_RING_SIZE_MAX ?\n\t\t  er->rx_pending : AG71XX_RX_RING_SIZE_MAX;\n\n\tif (netif_running(dev)) {\n\t\terr = dev->netdev_ops->ndo_stop(dev);\n\t\tif (err)\n\t\t\treturn err;\n\t}\n\n\tif (ag->tx_ring.desc_split)\n\t\ttx_size *= AG71XX_TX_RING_DS_PER_PKT;\n\n\tag->tx_ring.order = ag71xx_ring_size_order(tx_size);\n\tag->rx_ring.order = ag71xx_ring_size_order(rx_size);\n\n\tif (netif_running(dev))\n\t\terr = dev->netdev_ops->ndo_open(dev);\n\n\treturn err;\n}\n\nstatic int ag71xx_ethtool_nway_reset(struct net_device *dev)\n{\n\tstruct ag71xx *ag = netdev_priv(dev);\n\tstruct phy_device *phydev = ag->phy_dev;\n\n\tif (!phydev)\n\t\treturn -ENODEV;\n\n\treturn genphy_restart_aneg(phydev);\n}\n\nstatic void ag71xx_ethtool_get_strings(struct net_device *netdev, u32 sset,\n\t\t\t\t       u8 *data)\n{\n\tif (sset == ETH_SS_STATS) {\n\t\tint i;\n\n\t\tfor (i = 0; i < ARRAY_SIZE(ag71xx_statistics); i++)\n\t\t\tmemcpy(data + i * ETH_GSTRING_LEN,\n\t\t\t       ag71xx_statistics[i].name, ETH_GSTRING_LEN);\n\t}\n}\n\nstatic void ag71xx_ethtool_get_stats(struct net_device *ndev,\n\t\t\t\t     struct ethtool_stats *stats, u64 *data)\n{\n\tstruct ag71xx *ag = netdev_priv(ndev);\n\tint i;\n\n\tfor (i = 0; i < ARRAY_SIZE(ag71xx_statistics); i++)\n\t\t*data++ = ag71xx_rr(ag, ag71xx_statistics[i].offset)\n\t\t\t\t& ag71xx_statistics[i].mask;\n}\n\nstatic int ag71xx_ethtool_get_sset_count(struct net_device *ndev, int sset)\n{\n\tif (sset == ETH_SS_STATS)\n\t\treturn ARRAY_SIZE(ag71xx_statistics);\n\treturn -EOPNOTSUPP;\n}\n\nstruct ethtool_ops ag71xx_ethtool_ops = {\n\t.get_msglevel\t= ag71xx_ethtool_get_msglevel,\n\t.set_msglevel\t= ag71xx_ethtool_set_msglevel,\n\t.get_ringparam\t= ag71xx_ethtool_get_ringparam,\n\t.set_ringparam\t= ag71xx_ethtool_set_ringparam,\n\t.get_link_ksettings = phy_ethtool_get_link_ksettings,\n\t.set_link_ksettings = phy_ethtool_set_link_ksettings,\n\t.get_link\t= ethtool_op_get_link,\n\t.get_ts_info\t= ethtool_op_get_ts_info,\n\t.nway_reset\t= ag71xx_ethtool_nway_reset,\n\t.get_strings\t\t= ag71xx_ethtool_get_strings,\n\t.get_ethtool_stats\t= ag71xx_ethtool_get_stats,\n\t.get_sset_count\t\t= ag71xx_ethtool_get_sset_count,\n};\n"
  },
  {
    "path": "target/linux/ath79/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_gmac.c",
    "content": "/*\n *  Atheros AR71xx built-in ethernet mac driver\n *\n *  This program is free software; you can redistribute it and/or modify it\n *  under the terms of the GNU General Public License version 2 as published\n *  by the Free Software Foundation.\n */\n\n#include <linux/sizes.h>\n#include <linux/of_address.h>\n#include \"ag71xx.h\"\n\nstatic void ag71xx_of_set(struct device_node *np, const char *prop,\n\t\t\t  u32 *reg, u32 shift, u32 mask)\n{\n\tu32 val;\n\n\tif (of_property_read_u32(np, prop, &val))\n\t\treturn;\n\n\t*reg &= ~(mask << shift);\n\t*reg |= ((val & mask) << shift);\n}\n\nstatic void ag71xx_of_bit(struct device_node *np, const char *prop,\n\t\t\t  u32 *reg, u32 mask)\n{\n\tu32 val;\n\n\tif (of_property_read_u32(np, prop, &val))\n\t\treturn;\n\n\tif (val)\n\t\t*reg |= mask;\n\telse\n\t\t*reg &= ~mask;\n}\n\nstatic void ag71xx_setup_gmac_933x(struct device_node *np, void __iomem *base)\n{\n\tu32 val = __raw_readl(base + AR933X_GMAC_REG_ETH_CFG);\n\n\tag71xx_of_bit(np, \"switch-phy-swap\", &val, AR933X_ETH_CFG_SW_PHY_SWAP);\n\tag71xx_of_bit(np, \"switch-phy-addr-swap\", &val,\n\t\tAR933X_ETH_CFG_SW_PHY_ADDR_SWAP);\n\n\t__raw_writel(val, base + AR933X_GMAC_REG_ETH_CFG);\n}\n\nstatic void ag71xx_setup_gmac_934x(struct device_node *np, void __iomem *base)\n{\n\tu32 val = __raw_readl(base + AR934X_GMAC_REG_ETH_CFG);\n\n\tag71xx_of_bit(np, \"rgmii-gmac0\", &val, AR934X_ETH_CFG_RGMII_GMAC0);\n\tag71xx_of_bit(np, \"mii-gmac0\", &val, AR934X_ETH_CFG_MII_GMAC0);\n\tag71xx_of_bit(np, \"mii-gmac0-slave\", &val, AR934X_ETH_CFG_MII_GMAC0_SLAVE);\n\tag71xx_of_bit(np, \"gmii-gmac0\", &val, AR934X_ETH_CFG_GMII_GMAC0);\n\tag71xx_of_bit(np, \"switch-phy-swap\", &val, AR934X_ETH_CFG_SW_PHY_SWAP);\n\tag71xx_of_bit(np, \"switch-only-mode\", &val,\n\t\tAR934X_ETH_CFG_SW_ONLY_MODE);\n\tag71xx_of_set(np, \"rxdv-delay\", &val,\n\t\t      AR934X_ETH_CFG_RDV_DELAY_SHIFT, 0x3);\n\tag71xx_of_set(np, \"rxd-delay\", &val,\n\t\t      AR934X_ETH_CFG_RXD_DELAY_SHIFT, 0x3);\n\tag71xx_of_set(np, \"txd-delay\", &val,\n\t\t      AR934X_ETH_CFG_TXD_DELAY_SHIFT, 0x3);\n\tag71xx_of_set(np, \"txen-delay\", &val,\n\t\t      AR934X_ETH_CFG_TXE_DELAY_SHIFT, 0x3);\n\n\t__raw_writel(val, base + AR934X_GMAC_REG_ETH_CFG);\n}\n\nstatic void ag71xx_setup_gmac_955x(struct device_node *np, void __iomem *base)\n{\n\tu32 val = __raw_readl(base + QCA955X_GMAC_REG_ETH_CFG);\n\n\tag71xx_of_bit(np, \"rgmii-enabled\", &val, QCA955X_ETH_CFG_RGMII_EN);\n\tag71xx_of_bit(np, \"ge0-sgmii\", &val, QCA955X_ETH_CFG_GE0_SGMII);\n\tag71xx_of_set(np, \"txen-delay\", &val, QCA955X_ETH_CFG_TXE_DELAY_SHIFT, 0x3);\n\tag71xx_of_set(np, \"txd-delay\", &val, QCA955X_ETH_CFG_TXD_DELAY_SHIFT, 0x3);\n\tag71xx_of_set(np, \"rxdv-delay\", &val, QCA955X_ETH_CFG_RDV_DELAY_SHIFT, 0x3);\n\tag71xx_of_set(np, \"rxd-delay\", &val, QCA955X_ETH_CFG_RXD_DELAY_SHIFT, 0x3);\n\n\t__raw_writel(val, base + QCA955X_GMAC_REG_ETH_CFG);\n}\n\nstatic void ag71xx_setup_gmac_956x(struct device_node *np, void __iomem *base)\n{\n\tu32 val = __raw_readl(base + QCA956X_GMAC_REG_ETH_CFG);\n\n\tag71xx_of_bit(np, \"switch-phy-swap\", &val, QCA956X_ETH_CFG_SW_PHY_SWAP);\n\tag71xx_of_bit(np, \"switch-phy-addr-swap\", &val,\n\t\tQCA956X_ETH_CFG_SW_PHY_ADDR_SWAP);\n\n\t__raw_writel(val, base + QCA956X_GMAC_REG_ETH_CFG);\n}\n\nint ag71xx_setup_gmac(struct device_node *np)\n{\n\tstruct device_node *np_dev;\n\tvoid __iomem *base;\n\tint err = 0;\n\n\tnp = of_get_child_by_name(np, \"gmac-config\");\n\tif (!np)\n\t\treturn 0;\n\n\tnp_dev = of_parse_phandle(np, \"device\", 0);\n\tif (!np_dev)\n\t\tgoto out;\n\n\tbase = of_iomap(np_dev, 0);\n\tif (!base) {\n\t\tpr_err(\"%pOF: can't map GMAC registers\\n\", np_dev);\n\t\terr = -ENOMEM;\n\t\tgoto err_iomap;\n\t}\n\n\tif (of_device_is_compatible(np_dev, \"qca,ar9330-gmac\"))\n\t\tag71xx_setup_gmac_933x(np, base);\n\telse if (of_device_is_compatible(np_dev, \"qca,ar9340-gmac\"))\n\t\tag71xx_setup_gmac_934x(np, base);\n\telse if (of_device_is_compatible(np_dev, \"qca,qca9550-gmac\"))\n\t\tag71xx_setup_gmac_955x(np, base);\n\telse if (of_device_is_compatible(np_dev, \"qca,qca9560-gmac\"))\n\t\tag71xx_setup_gmac_956x(np, base);\n\n\tiounmap(base);\n\nerr_iomap:\n\tof_node_put(np_dev);\nout:\n\tof_node_put(np);\n\treturn err;\n}\n"
  },
  {
    "path": "target/linux/ath79/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_main.c",
    "content": "/*\n *  Atheros AR71xx built-in ethernet mac driver\n *\n *  Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>\n *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>\n *\n *  Based on Atheros' AG7100 driver\n *\n *  This program is free software; you can redistribute it and/or modify it\n *  under the terms of the GNU General Public License version 2 as published\n *  by the Free Software Foundation.\n */\n\n#include <linux/sizes.h>\n#include <linux/of_net.h>\n#include <linux/of_address.h>\n#include <linux/of_platform.h>\n#include \"ag71xx.h\"\n\n#define AG71XX_DEFAULT_MSG_ENABLE\t\\\n\t(NETIF_MSG_DRV\t\t\t\\\n\t| NETIF_MSG_PROBE\t\t\\\n\t| NETIF_MSG_LINK\t\t\\\n\t| NETIF_MSG_TIMER\t\t\\\n\t| NETIF_MSG_IFDOWN\t\t\\\n\t| NETIF_MSG_IFUP\t\t\\\n\t| NETIF_MSG_RX_ERR\t\t\\\n\t| NETIF_MSG_TX_ERR)\n\nstatic int ag71xx_msg_level = -1;\n\nmodule_param_named(msg_level, ag71xx_msg_level, int, 0);\nMODULE_PARM_DESC(msg_level, \"Message level (-1=defaults,0=none,...,16=all)\");\n\n#define ETH_SWITCH_HEADER_LEN\t2\n\nstatic int ag71xx_tx_packets(struct ag71xx *ag, bool flush);\n\nstatic inline unsigned int ag71xx_max_frame_len(unsigned int mtu)\n{\n\treturn ETH_SWITCH_HEADER_LEN + ETH_HLEN + VLAN_HLEN + mtu + ETH_FCS_LEN;\n}\n\nstatic void ag71xx_dump_dma_regs(struct ag71xx *ag)\n{\n\tDBG(\"%s: dma_tx_ctrl=%08x, dma_tx_desc=%08x, dma_tx_status=%08x\\n\",\n\t\tag->dev->name,\n\t\tag71xx_rr(ag, AG71XX_REG_TX_CTRL),\n\t\tag71xx_rr(ag, AG71XX_REG_TX_DESC),\n\t\tag71xx_rr(ag, AG71XX_REG_TX_STATUS));\n\n\tDBG(\"%s: dma_rx_ctrl=%08x, dma_rx_desc=%08x, dma_rx_status=%08x\\n\",\n\t\tag->dev->name,\n\t\tag71xx_rr(ag, AG71XX_REG_RX_CTRL),\n\t\tag71xx_rr(ag, AG71XX_REG_RX_DESC),\n\t\tag71xx_rr(ag, AG71XX_REG_RX_STATUS));\n}\n\nstatic void ag71xx_dump_regs(struct ag71xx *ag)\n{\n\tDBG(\"%s: mac_cfg1=%08x, mac_cfg2=%08x, ipg=%08x, hdx=%08x, mfl=%08x\\n\",\n\t\tag->dev->name,\n\t\tag71xx_rr(ag, AG71XX_REG_MAC_CFG1),\n\t\tag71xx_rr(ag, AG71XX_REG_MAC_CFG2),\n\t\tag71xx_rr(ag, AG71XX_REG_MAC_IPG),\n\t\tag71xx_rr(ag, AG71XX_REG_MAC_HDX),\n\t\tag71xx_rr(ag, AG71XX_REG_MAC_MFL));\n\tDBG(\"%s: mac_ifctl=%08x, mac_addr1=%08x, mac_addr2=%08x\\n\",\n\t\tag->dev->name,\n\t\tag71xx_rr(ag, AG71XX_REG_MAC_IFCTL),\n\t\tag71xx_rr(ag, AG71XX_REG_MAC_ADDR1),\n\t\tag71xx_rr(ag, AG71XX_REG_MAC_ADDR2));\n\tDBG(\"%s: fifo_cfg0=%08x, fifo_cfg1=%08x, fifo_cfg2=%08x\\n\",\n\t\tag->dev->name,\n\t\tag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),\n\t\tag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),\n\t\tag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));\n\tDBG(\"%s: fifo_cfg3=%08x, fifo_cfg4=%08x, fifo_cfg5=%08x\\n\",\n\t\tag->dev->name,\n\t\tag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),\n\t\tag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),\n\t\tag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));\n}\n\nstatic inline void ag71xx_dump_intr(struct ag71xx *ag, char *label, u32 intr)\n{\n\tDBG(\"%s: %s intr=%08x %s%s%s%s%s%s\\n\",\n\t\tag->dev->name, label, intr,\n\t\t(intr & AG71XX_INT_TX_PS) ? \"TXPS \" : \"\",\n\t\t(intr & AG71XX_INT_TX_UR) ? \"TXUR \" : \"\",\n\t\t(intr & AG71XX_INT_TX_BE) ? \"TXBE \" : \"\",\n\t\t(intr & AG71XX_INT_RX_PR) ? \"RXPR \" : \"\",\n\t\t(intr & AG71XX_INT_RX_OF) ? \"RXOF \" : \"\",\n\t\t(intr & AG71XX_INT_RX_BE) ? \"RXBE \" : \"\");\n}\n\nstatic void ag71xx_ring_tx_clean(struct ag71xx *ag)\n{\n\tstruct ag71xx_ring *ring = &ag->tx_ring;\n\tstruct net_device *dev = ag->dev;\n\tint ring_mask = BIT(ring->order) - 1;\n\tu32 bytes_compl = 0, pkts_compl = 0;\n\n\twhile (ring->curr != ring->dirty) {\n\t\tstruct ag71xx_desc *desc;\n\t\tu32 i = ring->dirty & ring_mask;\n\n\t\tdesc = ag71xx_ring_desc(ring, i);\n\t\tif (!ag71xx_desc_empty(desc)) {\n\t\t\tdesc->ctrl = 0;\n\t\t\tdev->stats.tx_errors++;\n\t\t}\n\n\t\tif (ring->buf[i].skb) {\n\t\t\tbytes_compl += ring->buf[i].len;\n\t\t\tpkts_compl++;\n\t\t\tdev_kfree_skb_any(ring->buf[i].skb);\n\t\t}\n\t\tring->buf[i].skb = NULL;\n\t\tring->dirty++;\n\t}\n\n\t/* flush descriptors */\n\twmb();\n\n\tnetdev_completed_queue(dev, pkts_compl, bytes_compl);\n}\n\nstatic void ag71xx_ring_tx_init(struct ag71xx *ag)\n{\n\tstruct ag71xx_ring *ring = &ag->tx_ring;\n\tint ring_size = BIT(ring->order);\n\tint ring_mask = BIT(ring->order) - 1;\n\tint i;\n\n\tfor (i = 0; i < ring_size; i++) {\n\t\tstruct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);\n\n\t\tdesc->next = (u32) (ring->descs_dma +\n\t\t\tAG71XX_DESC_SIZE * ((i + 1) & ring_mask));\n\n\t\tdesc->ctrl = DESC_EMPTY;\n\t\tring->buf[i].skb = NULL;\n\t}\n\n\t/* flush descriptors */\n\twmb();\n\n\tring->curr = 0;\n\tring->dirty = 0;\n\tnetdev_reset_queue(ag->dev);\n}\n\nstatic void ag71xx_ring_rx_clean(struct ag71xx *ag)\n{\n\tstruct ag71xx_ring *ring = &ag->rx_ring;\n\tint ring_size = BIT(ring->order);\n\tint i;\n\n\tif (!ring->buf)\n\t\treturn;\n\n\tfor (i = 0; i < ring_size; i++)\n\t\tif (ring->buf[i].rx_buf) {\n\t\t\tdma_unmap_single(&ag->pdev->dev, ring->buf[i].dma_addr,\n\t\t\t\t\t ag->rx_buf_size, DMA_FROM_DEVICE);\n\t\t\tskb_free_frag(ring->buf[i].rx_buf);\n\t\t}\n}\n\nstatic int ag71xx_buffer_size(struct ag71xx *ag)\n{\n\treturn ag->rx_buf_size +\n\t       SKB_DATA_ALIGN(sizeof(struct skb_shared_info));\n}\n\nstatic bool ag71xx_fill_rx_buf(struct ag71xx *ag, struct ag71xx_buf *buf,\n\t\t\t       int offset,\n\t\t\t       void *(*alloc)(unsigned int size))\n{\n\tstruct ag71xx_ring *ring = &ag->rx_ring;\n\tstruct ag71xx_desc *desc = ag71xx_ring_desc(ring, buf - &ring->buf[0]);\n\tvoid *data;\n\n\tdata = alloc(ag71xx_buffer_size(ag));\n\tif (!data)\n\t\treturn false;\n\n\tbuf->rx_buf = data;\n\tbuf->dma_addr = dma_map_single(&ag->pdev->dev, data, ag->rx_buf_size,\n\t\t\t\t       DMA_FROM_DEVICE);\n\tdesc->data = (u32) buf->dma_addr + offset;\n\treturn true;\n}\n\nstatic int ag71xx_ring_rx_init(struct ag71xx *ag)\n{\n\tstruct ag71xx_ring *ring = &ag->rx_ring;\n\tint ring_size = BIT(ring->order);\n\tint ring_mask = BIT(ring->order) - 1;\n\tunsigned int i;\n\tint ret;\n\n\tret = 0;\n\tfor (i = 0; i < ring_size; i++) {\n\t\tstruct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);\n\n\t\tdesc->next = (u32) (ring->descs_dma +\n\t\t\tAG71XX_DESC_SIZE * ((i + 1) & ring_mask));\n\n\t\tDBG(\"ag71xx: RX desc at %p, next is %08x\\n\",\n\t\t\tdesc, desc->next);\n\t}\n\n\tfor (i = 0; i < ring_size; i++) {\n\t\tstruct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);\n\n\t\tif (!ag71xx_fill_rx_buf(ag, &ring->buf[i], ag->rx_buf_offset,\n\t\t\t\t\tnetdev_alloc_frag)) {\n\t\t\tret = -ENOMEM;\n\t\t\tbreak;\n\t\t}\n\n\t\tdesc->ctrl = DESC_EMPTY;\n\t}\n\n\t/* flush descriptors */\n\twmb();\n\n\tring->curr = 0;\n\tring->dirty = 0;\n\n\treturn ret;\n}\n\nstatic int ag71xx_ring_rx_refill(struct ag71xx *ag)\n{\n\tstruct ag71xx_ring *ring = &ag->rx_ring;\n\tint ring_mask = BIT(ring->order) - 1;\n\tunsigned int count;\n\tint offset = ag->rx_buf_offset;\n\n\tcount = 0;\n\tfor (; ring->curr - ring->dirty > 0; ring->dirty++) {\n\t\tstruct ag71xx_desc *desc;\n\t\tunsigned int i;\n\n\t\ti = ring->dirty & ring_mask;\n\t\tdesc = ag71xx_ring_desc(ring, i);\n\n\t\tif (!ring->buf[i].rx_buf &&\n\t\t    !ag71xx_fill_rx_buf(ag, &ring->buf[i], offset,\n\t\t\t\t\tnapi_alloc_frag))\n\t\t\tbreak;\n\n\t\tdesc->ctrl = DESC_EMPTY;\n\t\tcount++;\n\t}\n\n\t/* flush descriptors */\n\twmb();\n\n\tDBG(\"%s: %u rx descriptors refilled\\n\", ag->dev->name, count);\n\n\treturn count;\n}\n\nstatic int ag71xx_rings_init(struct ag71xx *ag)\n{\n\tstruct ag71xx_ring *tx = &ag->tx_ring;\n\tstruct ag71xx_ring *rx = &ag->rx_ring;\n\tint ring_size = BIT(tx->order) + BIT(rx->order);\n\tint tx_size = BIT(tx->order);\n\n\ttx->buf = kzalloc(ring_size * sizeof(*tx->buf), GFP_KERNEL);\n\tif (!tx->buf)\n\t\treturn -ENOMEM;\n\n\ttx->descs_cpu = dma_alloc_coherent(&ag->pdev->dev, ring_size * AG71XX_DESC_SIZE,\n\t\t\t\t\t   &tx->descs_dma, GFP_KERNEL);\n\tif (!tx->descs_cpu) {\n\t\tkfree(tx->buf);\n\t\ttx->buf = NULL;\n\t\treturn -ENOMEM;\n\t}\n\n\trx->buf = &tx->buf[tx_size];\n\trx->descs_cpu = ((void *)tx->descs_cpu) + tx_size * AG71XX_DESC_SIZE;\n\trx->descs_dma = tx->descs_dma + tx_size * AG71XX_DESC_SIZE;\n\n\tag71xx_ring_tx_init(ag);\n\treturn ag71xx_ring_rx_init(ag);\n}\n\nstatic void ag71xx_rings_free(struct ag71xx *ag)\n{\n\tstruct ag71xx_ring *tx = &ag->tx_ring;\n\tstruct ag71xx_ring *rx = &ag->rx_ring;\n\tint ring_size = BIT(tx->order) + BIT(rx->order);\n\n\tif (tx->descs_cpu)\n\t\tdma_free_coherent(&ag->pdev->dev, ring_size * AG71XX_DESC_SIZE,\n\t\t\t\t  tx->descs_cpu, tx->descs_dma);\n\n\tkfree(tx->buf);\n\n\ttx->descs_cpu = NULL;\n\trx->descs_cpu = NULL;\n\ttx->buf = NULL;\n\trx->buf = NULL;\n}\n\nstatic void ag71xx_rings_cleanup(struct ag71xx *ag)\n{\n\tag71xx_ring_rx_clean(ag);\n\tag71xx_ring_tx_clean(ag);\n\tag71xx_rings_free(ag);\n\n\tnetdev_reset_queue(ag->dev);\n}\n\nstatic unsigned char *ag71xx_speed_str(struct ag71xx *ag)\n{\n\tswitch (ag->speed) {\n\tcase SPEED_1000:\n\t\treturn \"1000\";\n\tcase SPEED_100:\n\t\treturn \"100\";\n\tcase SPEED_10:\n\t\treturn \"10\";\n\t}\n\n\treturn \"?\";\n}\n\nstatic void ag71xx_hw_set_macaddr(struct ag71xx *ag, unsigned char *mac)\n{\n\tu32 t;\n\n\tt = (((u32) mac[5]) << 24) | (((u32) mac[4]) << 16)\n\t  | (((u32) mac[3]) << 8) | ((u32) mac[2]);\n\n\tag71xx_wr(ag, AG71XX_REG_MAC_ADDR1, t);\n\n\tt = (((u32) mac[1]) << 24) | (((u32) mac[0]) << 16);\n\tag71xx_wr(ag, AG71XX_REG_MAC_ADDR2, t);\n}\n\nstatic void ag71xx_dma_reset(struct ag71xx *ag)\n{\n\tu32 val;\n\tint i;\n\n\tag71xx_dump_dma_regs(ag);\n\n\t/* stop RX and TX */\n\tag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);\n\tag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);\n\n\t/*\n\t * give the hardware some time to really stop all rx/tx activity\n\t * clearing the descriptors too early causes random memory corruption\n\t */\n\tmdelay(1);\n\n\t/* clear descriptor addresses */\n\tag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->stop_desc_dma);\n\tag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->stop_desc_dma);\n\n\t/* clear pending RX/TX interrupts */\n\tfor (i = 0; i < 256; i++) {\n\t\tag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);\n\t\tag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);\n\t}\n\n\t/* clear pending errors */\n\tag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE | RX_STATUS_OF);\n\tag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE | TX_STATUS_UR);\n\n\tval = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);\n\tif (val)\n\t\tpr_alert(\"%s: unable to clear DMA Rx status: %08x\\n\",\n\t\t\t ag->dev->name, val);\n\n\tval = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);\n\n\t/* mask out reserved bits */\n\tval &= ~0xff000000;\n\n\tif (val)\n\t\tpr_alert(\"%s: unable to clear DMA Tx status: %08x\\n\",\n\t\t\t ag->dev->name, val);\n\n\tag71xx_dump_dma_regs(ag);\n}\n\n#define MAC_CFG1_INIT\t(MAC_CFG1_RXE | MAC_CFG1_TXE | \\\n\t\t\t MAC_CFG1_SRX | MAC_CFG1_STX)\n\n#define FIFO_CFG0_INIT\t(FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT)\n\n#define FIFO_CFG4_INIT\t(FIFO_CFG4_DE | FIFO_CFG4_DV | FIFO_CFG4_FC | \\\n\t\t\t FIFO_CFG4_CE | FIFO_CFG4_CR | FIFO_CFG4_LM | \\\n\t\t\t FIFO_CFG4_LO | FIFO_CFG4_OK | FIFO_CFG4_MC | \\\n\t\t\t FIFO_CFG4_BC | FIFO_CFG4_DR | FIFO_CFG4_LE | \\\n\t\t\t FIFO_CFG4_CF | FIFO_CFG4_PF | FIFO_CFG4_UO | \\\n\t\t\t FIFO_CFG4_VT)\n\n#define FIFO_CFG5_INIT\t(FIFO_CFG5_DE | FIFO_CFG5_DV | FIFO_CFG5_FC | \\\n\t\t\t FIFO_CFG5_CE | FIFO_CFG5_LO | FIFO_CFG5_OK | \\\n\t\t\t FIFO_CFG5_MC | FIFO_CFG5_BC | FIFO_CFG5_DR | \\\n\t\t\t FIFO_CFG5_CF | FIFO_CFG5_PF | FIFO_CFG5_VT | \\\n\t\t\t FIFO_CFG5_LE | FIFO_CFG5_FT | FIFO_CFG5_16 | \\\n\t\t\t FIFO_CFG5_17 | FIFO_CFG5_SF)\n\nstatic void ag71xx_hw_stop(struct ag71xx *ag)\n{\n\t/* disable all interrupts and stop the rx/tx engine */\n\tag71xx_wr(ag, AG71XX_REG_INT_ENABLE, 0);\n\tag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);\n\tag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);\n}\n\nstatic void ag71xx_hw_setup(struct ag71xx *ag)\n{\n\tstruct device_node *np = ag->pdev->dev.of_node;\n\tu32 init = MAC_CFG1_INIT;\n\n\t/* setup MAC configuration registers */\n\tif (of_property_read_bool(np, \"flow-control\"))\n\t\tinit |= MAC_CFG1_TFC | MAC_CFG1_RFC;\n\tag71xx_wr(ag, AG71XX_REG_MAC_CFG1, init);\n\n\tag71xx_sb(ag, AG71XX_REG_MAC_CFG2,\n\t\t  MAC_CFG2_PAD_CRC_EN | MAC_CFG2_LEN_CHECK);\n\n\t/* setup max frame length to zero */\n\tag71xx_wr(ag, AG71XX_REG_MAC_MFL, 0);\n\n\t/* setup FIFO configuration registers */\n\tag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, FIFO_CFG0_INIT);\n\tag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, ag->fifodata[0]);\n\tag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, ag->fifodata[1]);\n\tag71xx_wr(ag, AG71XX_REG_FIFO_CFG4, FIFO_CFG4_INIT);\n\tag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, FIFO_CFG5_INIT);\n}\n\nstatic void ag71xx_hw_init(struct ag71xx *ag)\n{\n\tag71xx_hw_stop(ag);\n\n\tag71xx_sb(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_SR);\n\tudelay(20);\n\n\treset_control_assert(ag->mac_reset);\n\tif (ag->mdio_reset)\n\t\treset_control_assert(ag->mdio_reset);\n\tmsleep(100);\n\treset_control_deassert(ag->mac_reset);\n\tif (ag->mdio_reset)\n\t\treset_control_deassert(ag->mdio_reset);\n\tmsleep(200);\n\n\tag71xx_hw_setup(ag);\n\n\tag71xx_dma_reset(ag);\n}\n\nstatic void ag71xx_fast_reset(struct ag71xx *ag)\n{\n\tstruct net_device *dev = ag->dev;\n\tu32 rx_ds;\n\tu32 mii_reg;\n\n\tag71xx_hw_stop(ag);\n\twmb();\n\n\tmii_reg = ag71xx_rr(ag, AG71XX_REG_MII_CFG);\n\trx_ds = ag71xx_rr(ag, AG71XX_REG_RX_DESC);\n\n\tag71xx_tx_packets(ag, true);\n\n\treset_control_assert(ag->mac_reset);\n\tudelay(10);\n\treset_control_deassert(ag->mac_reset);\n\tudelay(10);\n\n\tag71xx_dma_reset(ag);\n\tag71xx_hw_setup(ag);\n\tag->tx_ring.curr = 0;\n\tag->tx_ring.dirty = 0;\n\tnetdev_reset_queue(ag->dev);\n\n\t/* setup max frame length */\n\tag71xx_wr(ag, AG71XX_REG_MAC_MFL,\n\t\t  ag71xx_max_frame_len(ag->dev->mtu));\n\n\tag71xx_wr(ag, AG71XX_REG_RX_DESC, rx_ds);\n\tag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma);\n\tag71xx_wr(ag, AG71XX_REG_MII_CFG, mii_reg);\n\n\tag71xx_hw_set_macaddr(ag, dev->dev_addr);\n}\n\nstatic void ag71xx_hw_start(struct ag71xx *ag)\n{\n\t/* start RX engine */\n\tag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);\n\n\t/* enable interrupts */\n\tag71xx_wr(ag, AG71XX_REG_INT_ENABLE, AG71XX_INT_INIT);\n\n\tnetif_wake_queue(ag->dev);\n}\n\nstatic void ath79_set_pllval(struct ag71xx *ag)\n{\n\tu32 pll_reg = ag->pllreg[1];\n\tu32 pll_val;\n\n\tif (!ag->pllregmap)\n\t\treturn;\n\n\tswitch (ag->speed) {\n\tcase SPEED_10:\n\t\tpll_val = ag->plldata[2];\n\t\tbreak;\n\tcase SPEED_100:\n\t\tpll_val = ag->plldata[1];\n\t\tbreak;\n\tcase SPEED_1000:\n\t\tpll_val = ag->plldata[0];\n\t\tbreak;\n\tdefault:\n\t\tBUG();\n\t}\n\n\tif (pll_val)\n\t\tregmap_write(ag->pllregmap, pll_reg, pll_val);\n}\n\nstatic void ath79_set_pll(struct ag71xx *ag)\n{\n\tu32 pll_cfg = ag->pllreg[0];\n\tu32 pll_shift = ag->pllreg[2];\n\n\tif (!ag->pllregmap)\n\t\treturn;\n\n\tregmap_update_bits(ag->pllregmap, pll_cfg, 3 << pll_shift, 2 << pll_shift);\n\tudelay(100);\n\n\tath79_set_pllval(ag);\n\n\tregmap_update_bits(ag->pllregmap, pll_cfg, 3 << pll_shift, 3 << pll_shift);\n\tudelay(100);\n\n\tregmap_update_bits(ag->pllregmap, pll_cfg, 3 << pll_shift, 0);\n\tudelay(100);\n}\n\nstatic void ag71xx_bit_set(void __iomem *reg, u32 bit)\n{\n\tu32 val;\n\n\tval = __raw_readl(reg) | bit;\n\t__raw_writel(val, reg);\n\t__raw_readl(reg);\n}\n\nstatic void ag71xx_bit_clear(void __iomem *reg, u32 bit)\n{\n\tu32 val;\n\n\tval = __raw_readl(reg) & ~bit;\n\t__raw_writel(val, reg);\n\t__raw_readl(reg);\n}\n\nstatic void ag71xx_sgmii_serdes_init_qca956x(struct device_node *np)\n{\n\tstruct device_node *np_dev;\n\tvoid __iomem *gmac_base;\n\tu32 serdes_cal;\n\tu32 t;\n\n\tnp = of_get_child_by_name(np, \"gmac-config\");\n\tif (!np)\n\t\treturn;\n\n\tif (of_property_read_u32(np, \"serdes-cal\", &serdes_cal))\n\t\t/* By default, use middle value for resistor calibration */\n\t\tserdes_cal = 0x7;\n\n\tnp_dev = of_parse_phandle(np, \"device\", 0);\n\tif (!np_dev)\n\t\tgoto out;\n\n\tgmac_base = of_iomap(np_dev, 0);\n\tif (!gmac_base) {\n\t\tpr_err(\"%pOF: can't map GMAC registers\\n\", np_dev);\n\t\tgoto err_iomap;\n\t}\n\n\tt = __raw_readl(gmac_base + QCA956X_GMAC_REG_SGMII_CONFIG);\n\tt &= ~(QCA956X_SGMII_CONFIG_MODE_CTRL_MASK << QCA956X_SGMII_CONFIG_MODE_CTRL_SHIFT);\n\tt |= QCA956X_SGMII_CONFIG_MODE_CTRL_SGMII_MAC;\n\t__raw_writel(t, gmac_base + QCA956X_GMAC_REG_SGMII_CONFIG);\n\n\tpr_debug(\"%pOF: fixup SERDES calibration to value %i\\n\",\n\t\tnp_dev, serdes_cal);\n\tt = __raw_readl(gmac_base + QCA956X_GMAC_REG_SGMII_SERDES);\n\tt &= ~(QCA956X_SGMII_SERDES_RES_CALIBRATION_MASK\n\t\t\t<< QCA956X_SGMII_SERDES_RES_CALIBRATION_SHIFT);\n\tt |= (serdes_cal & QCA956X_SGMII_SERDES_RES_CALIBRATION_MASK)\n\t\t\t<< QCA956X_SGMII_SERDES_RES_CALIBRATION_SHIFT;\n\t__raw_writel(t, gmac_base + QCA956X_GMAC_REG_SGMII_SERDES);\n\n\tath79_pll_wr(QCA956X_PLL_ETH_SGMII_SERDES_REG,\n\t\t\tQCA956X_PLL_ETH_SGMII_SERDES_LOCK_DETECT\n\t\t\t\t\t| QCA956X_PLL_ETH_SGMII_SERDES_EN_PLL);\n\n\tt = __raw_readl(gmac_base + QCA956X_GMAC_REG_SGMII_SERDES);\n\n\t/* missing in QCA u-boot code, clear before setting */\n\tt &= ~(QCA956X_SGMII_SERDES_CDR_BW_MASK\n\t\t\t<< QCA956X_SGMII_SERDES_CDR_BW_SHIFT |\n\t\tQCA956X_SGMII_SERDES_TX_DR_CTRL_MASK\n\t\t\t<< QCA956X_SGMII_SERDES_TX_DR_CTRL_SHIFT |\n\t\tQCA956X_SGMII_SERDES_VCO_REG_MASK\n\t\t\t<< QCA956X_SGMII_SERDES_VCO_REG_SHIFT);\n\n\tt |= (3 << QCA956X_SGMII_SERDES_CDR_BW_SHIFT) |\n\t\t(1 << QCA956X_SGMII_SERDES_TX_DR_CTRL_SHIFT) |\n\t\tQCA956X_SGMII_SERDES_PLL_BW |\n\t\tQCA956X_SGMII_SERDES_EN_SIGNAL_DETECT |\n\t\tQCA956X_SGMII_SERDES_FIBER_SDO |\n\t\t(3 << QCA956X_SGMII_SERDES_VCO_REG_SHIFT);\n\n\t__raw_writel(t, gmac_base + QCA956X_GMAC_REG_SGMII_SERDES);\n\n\tath79_device_reset_clear(QCA956X_RESET_SGMII_ANALOG);\n\tath79_device_reset_clear(QCA956X_RESET_SGMII);\n\n\twhile (!(__raw_readl(gmac_base + QCA956X_GMAC_REG_SGMII_SERDES)\n\t\t\t& QCA956X_SGMII_SERDES_LOCK_DETECT_STATUS))\n\t\t;\n\n\tiounmap(gmac_base);\nerr_iomap:\n\tof_node_put(np_dev);\nout:\n\tof_node_put(np);\n}\n\nstatic void ag71xx_sgmii_init_qca955x(struct device_node *np)\n{\n\tstruct device_node *np_dev;\n\tvoid __iomem *gmac_base;\n\tu32 mr_an_status;\n\tu32 sgmii_status;\n\tu8 tries = 0;\n\tint err = 0;\n\n\tnp = of_get_child_by_name(np, \"gmac-config\");\n\tif (!np)\n\t\treturn;\n\n\tnp_dev = of_parse_phandle(np, \"device\", 0);\n\tif (!np_dev)\n\t\tgoto out;\n\n\tgmac_base = of_iomap(np_dev, 0);\n\tif (!gmac_base) {\n\t\tpr_err(\"%pOF: can't map GMAC registers\\n\", np_dev);\n\t\terr = -ENOMEM;\n\t\tgoto err_iomap;\n\t}\n\n\tmr_an_status = __raw_readl(gmac_base + QCA955X_GMAC_REG_MR_AN_STATUS);\n\tif (!(mr_an_status & QCA955X_MR_AN_STATUS_AN_ABILITY))\n\t\tgoto sgmii_out;\n\n\t/* SGMII reset sequence */\n\t__raw_writel(QCA955X_SGMII_RESET_RX_CLK_N_RESET,\n\t\t     gmac_base + QCA955X_GMAC_REG_SGMII_RESET);\n\t__raw_readl(gmac_base + QCA955X_GMAC_REG_SGMII_RESET);\n\tudelay(10);\n\n\tag71xx_bit_set(gmac_base + QCA955X_GMAC_REG_SGMII_RESET,\n\t\t       QCA955X_SGMII_RESET_HW_RX_125M_N);\n\tudelay(10);\n\n\tag71xx_bit_set(gmac_base + QCA955X_GMAC_REG_SGMII_RESET,\n\t\t       QCA955X_SGMII_RESET_RX_125M_N);\n\tudelay(10);\n\n\tag71xx_bit_set(gmac_base + QCA955X_GMAC_REG_SGMII_RESET,\n\t\t       QCA955X_SGMII_RESET_TX_125M_N);\n\tudelay(10);\n\n\tag71xx_bit_set(gmac_base + QCA955X_GMAC_REG_SGMII_RESET,\n\t\t       QCA955X_SGMII_RESET_RX_CLK_N);\n\tudelay(10);\n\n\tag71xx_bit_set(gmac_base + QCA955X_GMAC_REG_SGMII_RESET,\n\t\t       QCA955X_SGMII_RESET_TX_CLK_N);\n\tudelay(10);\n\n\t/*\n\t * The following is what QCA has to say about what happens here:\n\t *\n\t * Across resets SGMII link status goes to weird state.\n\t * If SGMII_DEBUG register reads other than 0x1f or 0x10,\n\t * we are for sure in a bad  state.\n\t *\n\t * Issue a PHY reset in MR_AN_CONTROL to keep going.\n\t */\n\tdo {\n\t\tag71xx_bit_set(gmac_base + QCA955X_GMAC_REG_MR_AN_CONTROL,\n\t\t\t       QCA955X_MR_AN_CONTROL_PHY_RESET |\n\t\t\t       QCA955X_MR_AN_CONTROL_AN_ENABLE);\n\t\tudelay(200);\n\t\tag71xx_bit_clear(gmac_base + QCA955X_GMAC_REG_MR_AN_CONTROL,\n\t\t\t\t QCA955X_MR_AN_CONTROL_PHY_RESET);\n\t\tmdelay(300);\n\t\tsgmii_status = __raw_readl(gmac_base + QCA955X_GMAC_REG_SGMII_DEBUG) &\n\t\t\t\t\t   QCA955X_SGMII_DEBUG_TX_STATE_MASK;\n\n\t\tif (tries++ >= 20) {\n\t\t\tpr_err(\"ag71xx: max retries for SGMII fixup exceeded\\n\");\n\t\t\tbreak;\n\t\t}\n\t} while (!(sgmii_status == 0xf || sgmii_status == 0x10));\n\nsgmii_out:\n\tiounmap(gmac_base);\nerr_iomap:\n\tof_node_put(np_dev);\nout:\n\tof_node_put(np);\n}\n\nstatic void ag71xx_mux_select_sgmii_qca956x(struct device_node *np)\n{\n\tstruct device_node *np_dev;\n\tvoid __iomem *gmac_base;\n\tu32 t;\n\n\tnp = of_get_child_by_name(np, \"gmac-config\");\n\tif (!np)\n\t\treturn;\n\n\tnp_dev = of_parse_phandle(np, \"device\", 0);\n\tif (!np_dev)\n\t\tgoto out;\n\n\tgmac_base = of_iomap(np_dev, 0);\n\tif (!gmac_base) {\n\t\tpr_err(\"%pOF: can't map GMAC registers\\n\", np_dev);\n\t\tgoto err_iomap;\n\t}\n\n\tt = __raw_readl(gmac_base + QCA956X_GMAC_REG_ETH_CFG);\n\tt |= QCA956X_ETH_CFG_GE0_SGMII;\n\t__raw_writel(t, gmac_base + QCA956X_GMAC_REG_ETH_CFG);\n\n\tiounmap(gmac_base);\nerr_iomap:\n\tof_node_put(np_dev);\nout:\n\tof_node_put(np);\n}\n\nstatic void ath79_mii_ctrl_set_if(struct ag71xx *ag, unsigned int mii_if)\n{\n\tu32 t;\n\n\tt = __raw_readl(ag->mii_base);\n\tt &= ~(AR71XX_MII_CTRL_IF_MASK);\n\tt |= (mii_if & AR71XX_MII_CTRL_IF_MASK);\n\t__raw_writel(t, ag->mii_base);\n}\n\nstatic void ath79_mii0_ctrl_set_if(struct ag71xx *ag)\n{\n\tunsigned int mii_if;\n\n\tswitch (ag->phy_if_mode) {\n\tcase PHY_INTERFACE_MODE_MII:\n\t\tmii_if = AR71XX_MII0_CTRL_IF_MII;\n\t\tbreak;\n\tcase PHY_INTERFACE_MODE_GMII:\n\t\tmii_if = AR71XX_MII0_CTRL_IF_GMII;\n\t\tbreak;\n\tcase PHY_INTERFACE_MODE_RGMII:\n\tcase PHY_INTERFACE_MODE_RGMII_ID:\n\tcase PHY_INTERFACE_MODE_RGMII_RXID:\n\tcase PHY_INTERFACE_MODE_RGMII_TXID:\n\t\tmii_if = AR71XX_MII0_CTRL_IF_RGMII;\n\t\tbreak;\n\tcase PHY_INTERFACE_MODE_RMII:\n\t\tmii_if = AR71XX_MII0_CTRL_IF_RMII;\n\t\tbreak;\n\tdefault:\n\t\tWARN(1, \"Impossible PHY mode defined.\\n\");\n\t\treturn;\n\t}\n\n\tath79_mii_ctrl_set_if(ag, mii_if);\n}\n\nstatic void ath79_mii1_ctrl_set_if(struct ag71xx *ag)\n{\n\tunsigned int mii_if;\n\n\tswitch (ag->phy_if_mode) {\n\tcase PHY_INTERFACE_MODE_RMII:\n\t\tmii_if = AR71XX_MII1_CTRL_IF_RMII;\n\t\tbreak;\n\tcase PHY_INTERFACE_MODE_RGMII:\n\tcase PHY_INTERFACE_MODE_RGMII_ID:\n\tcase PHY_INTERFACE_MODE_RGMII_RXID:\n\tcase PHY_INTERFACE_MODE_RGMII_TXID:\n\t\tmii_if = AR71XX_MII1_CTRL_IF_RGMII;\n\t\tbreak;\n\tdefault:\n\t\tWARN(1, \"Impossible PHY mode defined.\\n\");\n\t\treturn;\n\t}\n\n\tath79_mii_ctrl_set_if(ag, mii_if);\n}\n\nstatic void ath79_mii_ctrl_set_speed(struct ag71xx *ag)\n{\n\tunsigned int mii_speed;\n\tu32 t;\n\n\tif (!ag->mii_base)\n\t\treturn;\n\n\tswitch (ag->speed) {\n\tcase SPEED_10:\n\t\tmii_speed =  AR71XX_MII_CTRL_SPEED_10;\n\t\tbreak;\n\tcase SPEED_100:\n\t\tmii_speed =  AR71XX_MII_CTRL_SPEED_100;\n\t\tbreak;\n\tcase SPEED_1000:\n\t\tmii_speed =  AR71XX_MII_CTRL_SPEED_1000;\n\t\tbreak;\n\tdefault:\n\t\tBUG();\n\t}\n\n\tt = __raw_readl(ag->mii_base);\n\tt &= ~(AR71XX_MII_CTRL_SPEED_MASK << AR71XX_MII_CTRL_SPEED_SHIFT);\n\tt |= mii_speed << AR71XX_MII_CTRL_SPEED_SHIFT;\n\t__raw_writel(t, ag->mii_base);\n}\n\nstatic void\n__ag71xx_link_adjust(struct ag71xx *ag, bool update)\n{\n\tstruct device_node *np = ag->pdev->dev.of_node;\n\tu32 cfg2;\n\tu32 ifctl;\n\tu32 fifo5;\n\n\tif (!ag->link && update) {\n\t\tag71xx_hw_stop(ag);\n\t\tnetif_carrier_off(ag->dev);\n\t\tif (netif_msg_link(ag))\n\t\t\tpr_info(\"%s: link down\\n\", ag->dev->name);\n\t\treturn;\n\t}\n\n\tif (!of_device_is_compatible(np, \"qca,ar9130-eth\") &&\n\t    !of_device_is_compatible(np, \"qca,ar7100-eth\"))\n\t\tag71xx_fast_reset(ag);\n\n\tcfg2 = ag71xx_rr(ag, AG71XX_REG_MAC_CFG2);\n\tcfg2 &= ~(MAC_CFG2_IF_1000 | MAC_CFG2_IF_10_100 | MAC_CFG2_FDX);\n\tcfg2 |= (ag->duplex) ? MAC_CFG2_FDX : 0;\n\n\tifctl = ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL);\n\tifctl &= ~(MAC_IFCTL_SPEED);\n\n\tfifo5 = ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5);\n\tfifo5 &= ~FIFO_CFG5_BM;\n\n\tswitch (ag->speed) {\n\tcase SPEED_1000:\n\t\tcfg2 |= MAC_CFG2_IF_1000;\n\t\tfifo5 |= FIFO_CFG5_BM;\n\t\tbreak;\n\tcase SPEED_100:\n\t\tcfg2 |= MAC_CFG2_IF_10_100;\n\t\tifctl |= MAC_IFCTL_SPEED;\n\t\tbreak;\n\tcase SPEED_10:\n\t\tcfg2 |= MAC_CFG2_IF_10_100;\n\t\tbreak;\n\tdefault:\n\t\tBUG();\n\t\treturn;\n\t}\n\n\tif (ag->tx_ring.desc_split) {\n\t\tag->fifodata[2] &= 0xffff;\n\t\tag->fifodata[2] |= ((2048 - ag->tx_ring.desc_split) / 4) << 16;\n\t}\n\n\tag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, ag->fifodata[2]);\n\n\tif (update) {\n\t\tif (of_device_is_compatible(np, \"qca,ar7100-eth\") ||\n\t\t    of_device_is_compatible(np, \"qca,ar9130-eth\")) {\n\t\t\tath79_set_pll(ag);\n\t\t\tath79_mii_ctrl_set_speed(ag);\n\t\t} else if (of_device_is_compatible(np, \"qca,ar7242-eth\") ||\n\t\t\t   of_device_is_compatible(np, \"qca,ar9340-eth\") ||\n\t\t\t   of_device_is_compatible(np, \"qca,qca9550-eth\") ||\n\t\t\t   of_device_is_compatible(np, \"qca,qca9560-eth\")) {\n\t\t\tath79_set_pllval(ag);\n\t\t\tif (of_property_read_bool(np, \"qca955x-sgmii-fixup\"))\n\t\t\t\tag71xx_sgmii_init_qca955x(np);\n\t\t}\n\t}\n\n\tag71xx_wr(ag, AG71XX_REG_MAC_CFG2, cfg2);\n\tag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, fifo5);\n\tag71xx_wr(ag, AG71XX_REG_MAC_IFCTL, ifctl);\n\n\tif (of_device_is_compatible(np, \"qca,qca9530-eth\") ||\n\t    of_device_is_compatible(np, \"qca,qca9560-eth\")) {\n\t\t/*\n\t\t * The rx ring buffer can stall on small packets on QCA953x and\n\t\t * QCA956x. Disabling the inline checksum engine fixes the stall.\n\t\t * The wr, rr functions cannot be used since this hidden register\n\t\t * is outside of the normal ag71xx register block.\n\t\t */\n\t\tvoid __iomem *dam = ioremap(0xb90001bc, 0x4);\n\t\tif (dam) {\n\t\t\t__raw_writel(__raw_readl(dam) & ~BIT(27), dam);\n\t\t\t(void)__raw_readl(dam);\n\t\t\tiounmap(dam);\n\t\t}\n\t}\n\n\tag71xx_hw_start(ag);\n\n\tnetif_carrier_on(ag->dev);\n\tif (update && netif_msg_link(ag))\n\t\tpr_info(\"%s: link up (%sMbps/%s duplex)\\n\",\n\t\t\tag->dev->name,\n\t\t\tag71xx_speed_str(ag),\n\t\t\t(DUPLEX_FULL == ag->duplex) ? \"Full\" : \"Half\");\n\n\tag71xx_dump_regs(ag);\n}\n\nvoid ag71xx_link_adjust(struct ag71xx *ag)\n{\n\t__ag71xx_link_adjust(ag, true);\n}\n\nstatic int ag71xx_hw_enable(struct ag71xx *ag)\n{\n\tint ret;\n\n\tret = ag71xx_rings_init(ag);\n\tif (ret)\n\t\treturn ret;\n\n\tnapi_enable(&ag->napi);\n\tag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma);\n\tag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->rx_ring.descs_dma);\n\tnetif_start_queue(ag->dev);\n\n\treturn 0;\n}\n\nstatic void ag71xx_hw_disable(struct ag71xx *ag)\n{\n\tnetif_stop_queue(ag->dev);\n\n\tag71xx_hw_stop(ag);\n\tag71xx_dma_reset(ag);\n\n\tnapi_disable(&ag->napi);\n\tdel_timer_sync(&ag->oom_timer);\n\n\tag71xx_rings_cleanup(ag);\n}\n\nstatic int ag71xx_open(struct net_device *dev)\n{\n\tstruct ag71xx *ag = netdev_priv(dev);\n\tunsigned int max_frame_len;\n\tint ret;\n\n\tnetif_carrier_off(dev);\n\tmax_frame_len = ag71xx_max_frame_len(dev->mtu);\n\tag->rx_buf_size = SKB_DATA_ALIGN(max_frame_len + NET_SKB_PAD + NET_IP_ALIGN);\n\n\t/* setup max frame length */\n\tag71xx_wr(ag, AG71XX_REG_MAC_MFL, max_frame_len);\n\tag71xx_hw_set_macaddr(ag, dev->dev_addr);\n\n\tret = ag71xx_hw_enable(ag);\n\tif (ret)\n\t\tgoto err;\n\n\tphy_start(ag->phy_dev);\n\n\treturn 0;\n\nerr:\n\tag71xx_rings_cleanup(ag);\n\treturn ret;\n}\n\nstatic int ag71xx_stop(struct net_device *dev)\n{\n\tunsigned long flags;\n\tstruct ag71xx *ag = netdev_priv(dev);\n\n\tnetif_carrier_off(dev);\n\tphy_stop(ag->phy_dev);\n\n\tspin_lock_irqsave(&ag->lock, flags);\n\tif (ag->link) {\n\t\tag->link = 0;\n\t\tag71xx_link_adjust(ag);\n\t}\n\tspin_unlock_irqrestore(&ag->lock, flags);\n\n\tag71xx_hw_disable(ag);\n\n\treturn 0;\n}\n\nstatic int ag71xx_fill_dma_desc(struct ag71xx_ring *ring, u32 addr, int len)\n{\n\tint i;\n\tstruct ag71xx_desc *desc;\n\tint ring_mask = BIT(ring->order) - 1;\n\tint ndesc = 0;\n\tint split = ring->desc_split;\n\n\tif (!split)\n\t\tsplit = len;\n\n\twhile (len > 0) {\n\t\tunsigned int cur_len = len;\n\n\t\ti = (ring->curr + ndesc) & ring_mask;\n\t\tdesc = ag71xx_ring_desc(ring, i);\n\n\t\tif (!ag71xx_desc_empty(desc))\n\t\t\treturn -1;\n\n\t\tif (cur_len > split) {\n\t\t\tcur_len = split;\n\n\t\t\t/*\n\t\t\t * TX will hang if DMA transfers <= 4 bytes,\n\t\t\t * make sure next segment is more than 4 bytes long.\n\t\t\t */\n\t\t\tif (len <= split + 4)\n\t\t\t\tcur_len -= 4;\n\t\t}\n\n\t\tdesc->data = addr;\n\t\taddr += cur_len;\n\t\tlen -= cur_len;\n\n\t\tif (len > 0)\n\t\t\tcur_len |= DESC_MORE;\n\n\t\t/* prevent early tx attempt of this descriptor */\n\t\tif (!ndesc)\n\t\t\tcur_len |= DESC_EMPTY;\n\n\t\tdesc->ctrl = cur_len;\n\t\tndesc++;\n\t}\n\n\treturn ndesc;\n}\n\nstatic netdev_tx_t ag71xx_hard_start_xmit(struct sk_buff *skb,\n\t\t\t\t\t  struct net_device *dev)\n{\n\tstruct ag71xx *ag = netdev_priv(dev);\n\tstruct ag71xx_ring *ring = &ag->tx_ring;\n\tint ring_mask = BIT(ring->order) - 1;\n\tint ring_size = BIT(ring->order);\n\tstruct ag71xx_desc *desc;\n\tdma_addr_t dma_addr;\n\tint i, n, ring_min;\n\n\tif (skb->len <= 4) {\n\t\tDBG(\"%s: packet len is too small\\n\", ag->dev->name);\n\t\tgoto err_drop;\n\t}\n\n\tdma_addr = dma_map_single(&ag->pdev->dev, skb->data, skb->len,\n\t\t\t\t  DMA_TO_DEVICE);\n\n\ti = ring->curr & ring_mask;\n\tdesc = ag71xx_ring_desc(ring, i);\n\n\t/* setup descriptor fields */\n\tn = ag71xx_fill_dma_desc(ring, (u32) dma_addr, skb->len & ag->desc_pktlen_mask);\n\tif (n < 0)\n\t\tgoto err_drop_unmap;\n\n\ti = (ring->curr + n - 1) & ring_mask;\n\tring->buf[i].len = skb->len;\n\tring->buf[i].skb = skb;\n\n\tnetdev_sent_queue(dev, skb->len);\n\n\tskb_tx_timestamp(skb);\n\n\tdesc->ctrl &= ~DESC_EMPTY;\n\tring->curr += n;\n\n\t/* flush descriptor */\n\twmb();\n\n\tring_min = 2;\n\tif (ring->desc_split)\n\t    ring_min *= AG71XX_TX_RING_DS_PER_PKT;\n\n\tif (ring->curr - ring->dirty >= ring_size - ring_min) {\n\t\tDBG(\"%s: tx queue full\\n\", dev->name);\n\t\tnetif_stop_queue(dev);\n\t}\n\n\tDBG(\"%s: packet injected into TX queue\\n\", ag->dev->name);\n\n\t/* enable TX engine */\n\tag71xx_wr(ag, AG71XX_REG_TX_CTRL, TX_CTRL_TXE);\n\n\treturn NETDEV_TX_OK;\n\nerr_drop_unmap:\n\tdma_unmap_single(&ag->pdev->dev, dma_addr, skb->len, DMA_TO_DEVICE);\n\nerr_drop:\n\tdev->stats.tx_dropped++;\n\n\tdev_kfree_skb(skb);\n\treturn NETDEV_TX_OK;\n}\n\nstatic int ag71xx_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)\n{\n\tstruct ag71xx *ag = netdev_priv(dev);\n\n\n\tswitch (cmd) {\n\tcase SIOCSIFHWADDR:\n\t\tif (copy_from_user\n\t\t\t(dev->dev_addr, ifr->ifr_data, sizeof(dev->dev_addr)))\n\t\t\treturn -EFAULT;\n\t\treturn 0;\n\n\tcase SIOCGIFHWADDR:\n\t\tif (copy_to_user\n\t\t\t(ifr->ifr_data, dev->dev_addr, sizeof(dev->dev_addr)))\n\t\t\treturn -EFAULT;\n\t\treturn 0;\n\n\tcase SIOCGMIIPHY:\n\tcase SIOCGMIIREG:\n\tcase SIOCSMIIREG:\n\t\tif (ag->phy_dev == NULL)\n\t\t\tbreak;\n\n\t\treturn phy_mii_ioctl(ag->phy_dev, ifr, cmd);\n\n\tdefault:\n\t\tbreak;\n\t}\n\n\treturn -EOPNOTSUPP;\n}\n\nstatic void ag71xx_oom_timer_handler(struct timer_list *t)\n{\n\tstruct ag71xx *ag = from_timer(ag, t, oom_timer);\n\n\tnapi_schedule(&ag->napi);\n}\n\nstatic void ag71xx_tx_timeout(struct net_device *dev, unsigned int txqueue)\n{\n\tstruct ag71xx *ag = netdev_priv(dev);\n\n\tif (netif_msg_tx_err(ag))\n\t\tpr_info(\"%s: tx timeout\\n\", ag->dev->name);\n\n\tschedule_delayed_work(&ag->restart_work, 1);\n}\n\nstatic void ag71xx_restart_work_func(struct work_struct *work)\n{\n\tstruct ag71xx *ag = container_of(work, struct ag71xx, restart_work.work);\n\n\trtnl_lock();\n\tag71xx_hw_disable(ag);\n\tag71xx_hw_enable(ag);\n\tif (ag->link)\n\t\t__ag71xx_link_adjust(ag, false);\n\trtnl_unlock();\n}\n\nstatic bool ag71xx_check_dma_stuck(struct ag71xx *ag)\n{\n\tunsigned long timestamp;\n\tu32 rx_sm, tx_sm, rx_fd;\n\n\ttimestamp = netdev_get_tx_queue(ag->dev, 0)->trans_start;\n\tif (likely(time_before(jiffies, timestamp + HZ/10)))\n\t\treturn false;\n\n\tif (!netif_carrier_ok(ag->dev))\n\t\treturn false;\n\n\trx_sm = ag71xx_rr(ag, AG71XX_REG_RX_SM);\n\tif ((rx_sm & 0x7) == 0x3 && ((rx_sm >> 4) & 0x7) == 0x6)\n\t\treturn true;\n\n\ttx_sm = ag71xx_rr(ag, AG71XX_REG_TX_SM);\n\trx_fd = ag71xx_rr(ag, AG71XX_REG_FIFO_DEPTH);\n\tif (((tx_sm >> 4) & 0x7) == 0 && ((rx_sm & 0x7) == 0) &&\n\t    ((rx_sm >> 4) & 0x7) == 0 && rx_fd == 0)\n\t\treturn true;\n\n\treturn false;\n}\n\nstatic int ag71xx_tx_packets(struct ag71xx *ag, bool flush)\n{\n\tstruct ag71xx_ring *ring = &ag->tx_ring;\n\tbool dma_stuck = false;\n\tint ring_mask = BIT(ring->order) - 1;\n\tint ring_size = BIT(ring->order);\n\tint sent = 0;\n\tint bytes_compl = 0;\n\tint n = 0;\n\n\tDBG(\"%s: processing TX ring\\n\", ag->dev->name);\n\n\twhile (ring->dirty + n != ring->curr) {\n\t\tunsigned int i = (ring->dirty + n) & ring_mask;\n\t\tstruct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);\n\t\tstruct sk_buff *skb = ring->buf[i].skb;\n\n\t\tif (!flush && !ag71xx_desc_empty(desc)) {\n\t\t\tif (ag->tx_hang_workaround &&\n\t\t\t    ag71xx_check_dma_stuck(ag)) {\n\t\t\t\tschedule_delayed_work(&ag->restart_work, HZ / 2);\n\t\t\t\tdma_stuck = true;\n\t\t\t}\n\t\t\tbreak;\n\t\t}\n\n\t\tif (flush)\n\t\t\tdesc->ctrl |= DESC_EMPTY;\n\n\t\tn++;\n\t\tif (!skb)\n\t\t\tcontinue;\n\n\t\tdev_kfree_skb_any(skb);\n\t\tring->buf[i].skb = NULL;\n\n\t\tbytes_compl += ring->buf[i].len;\n\n\t\tsent++;\n\t\tring->dirty += n;\n\n\t\twhile (n > 0) {\n\t\t\tag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);\n\t\t\tn--;\n\t\t}\n\t}\n\n\tDBG(\"%s: %d packets sent out\\n\", ag->dev->name, sent);\n\n\tif (!sent)\n\t\treturn 0;\n\n\tag->dev->stats.tx_bytes += bytes_compl;\n\tag->dev->stats.tx_packets += sent;\n\n\tnetdev_completed_queue(ag->dev, sent, bytes_compl);\n\tif ((ring->curr - ring->dirty) < (ring_size * 3) / 4)\n\t\tnetif_wake_queue(ag->dev);\n\n\tif (!dma_stuck)\n\t\tcancel_delayed_work(&ag->restart_work);\n\n\treturn sent;\n}\n\nstatic int ag71xx_rx_packets(struct ag71xx *ag, int limit)\n{\n\tstruct net_device *dev = ag->dev;\n\tstruct ag71xx_ring *ring = &ag->rx_ring;\n\tunsigned int pktlen_mask = ag->desc_pktlen_mask;\n\tunsigned int offset = ag->rx_buf_offset;\n\tint ring_mask = BIT(ring->order) - 1;\n\tint ring_size = BIT(ring->order);\n\tstruct list_head rx_list;\n\tstruct sk_buff *next;\n\tstruct sk_buff *skb;\n\tint done = 0;\n\n\tDBG(\"%s: rx packets, limit=%d, curr=%u, dirty=%u\\n\",\n\t\t\tdev->name, limit, ring->curr, ring->dirty);\n\tINIT_LIST_HEAD(&rx_list);\n\n\twhile (done < limit) {\n\t\tunsigned int i = ring->curr & ring_mask;\n\t\tstruct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);\n\t\tint pktlen;\n\t\tint err = 0;\n\n\t\tif (ag71xx_desc_empty(desc))\n\t\t\tbreak;\n\n\t\tif ((ring->dirty + ring_size) == ring->curr) {\n\t\t\tag71xx_assert(0);\n\t\t\tbreak;\n\t\t}\n\n\t\tag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);\n\n\t\tpktlen = desc->ctrl & pktlen_mask;\n\t\tpktlen -= ETH_FCS_LEN;\n\n\t\tdma_unmap_single(&ag->pdev->dev, ring->buf[i].dma_addr,\n\t\t\t\t ag->rx_buf_size, DMA_FROM_DEVICE);\n\n\t\tdev->stats.rx_packets++;\n\t\tdev->stats.rx_bytes += pktlen;\n\n\t\tskb = build_skb(ring->buf[i].rx_buf, ag71xx_buffer_size(ag));\n\t\tif (!skb) {\n\t\t\tskb_free_frag(ring->buf[i].rx_buf);\n\t\t\tgoto next;\n\t\t}\n\n\t\tskb_reserve(skb, offset);\n\t\tskb_put(skb, pktlen);\n\n\t\tif (err) {\n\t\t\tdev->stats.rx_dropped++;\n\t\t\tkfree_skb(skb);\n\t\t} else {\n\t\t\tskb->dev = dev;\n\t\t\tskb->ip_summed = CHECKSUM_NONE;\n\t\t\tlist_add_tail(&skb->list, &rx_list);\n\t\t}\n\nnext:\n\t\tring->buf[i].rx_buf = NULL;\n\t\tdone++;\n\n\t\tring->curr++;\n\t}\n\n\tag71xx_ring_rx_refill(ag);\n\n\tlist_for_each_entry_safe(skb, next, &rx_list, list)\n\t\tskb->protocol = eth_type_trans(skb, dev);\n\tnetif_receive_skb_list(&rx_list);\n\n\tDBG(\"%s: rx finish, curr=%u, dirty=%u, done=%d\\n\",\n\t\tdev->name, ring->curr, ring->dirty, done);\n\n\treturn done;\n}\n\nstatic int ag71xx_poll(struct napi_struct *napi, int limit)\n{\n\tstruct ag71xx *ag = container_of(napi, struct ag71xx, napi);\n\tstruct net_device *dev = ag->dev;\n\tstruct ag71xx_ring *rx_ring = &ag->rx_ring;\n\tint rx_ring_size = BIT(rx_ring->order);\n\tunsigned long flags;\n\tu32 status;\n\tint tx_done;\n\tint rx_done;\n\n\ttx_done = ag71xx_tx_packets(ag, false);\n\n\tDBG(\"%s: processing RX ring\\n\", dev->name);\n\trx_done = ag71xx_rx_packets(ag, limit);\n\n\tag71xx_debugfs_update_napi_stats(ag, rx_done, tx_done);\n\n\tif (rx_ring->buf[rx_ring->dirty % rx_ring_size].rx_buf == NULL)\n\t\tgoto oom;\n\n\tstatus = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);\n\tif (unlikely(status & RX_STATUS_OF)) {\n\t\tag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_OF);\n\t\tdev->stats.rx_fifo_errors++;\n\n\t\t/* restart RX */\n\t\tag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);\n\t}\n\n\tif (rx_done < limit) {\n\t\tif (status & RX_STATUS_PR)\n\t\t\tgoto more;\n\n\t\tstatus = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);\n\t\tif (status & TX_STATUS_PS)\n\t\t\tgoto more;\n\n\t\tDBG(\"%s: disable polling mode, rx=%d, tx=%d,limit=%d\\n\",\n\t\t\tdev->name, rx_done, tx_done, limit);\n\n\t\tnapi_complete(napi);\n\n\t\t/* enable interrupts */\n\t\tspin_lock_irqsave(&ag->lock, flags);\n\t\tag71xx_int_enable(ag, AG71XX_INT_POLL);\n\t\tspin_unlock_irqrestore(&ag->lock, flags);\n\t\treturn rx_done;\n\t}\n\nmore:\n\tDBG(\"%s: stay in polling mode, rx=%d, tx=%d, limit=%d\\n\",\n\t\t\tdev->name, rx_done, tx_done, limit);\n\treturn limit;\n\noom:\n\tif (netif_msg_rx_err(ag))\n\t\tpr_info(\"%s: out of memory\\n\", dev->name);\n\n\tmod_timer(&ag->oom_timer, jiffies + AG71XX_OOM_REFILL);\n\tnapi_complete(napi);\n\treturn 0;\n}\n\nstatic irqreturn_t ag71xx_interrupt(int irq, void *dev_id)\n{\n\tstruct net_device *dev = dev_id;\n\tstruct ag71xx *ag = netdev_priv(dev);\n\tu32 status;\n\n\tstatus = ag71xx_rr(ag, AG71XX_REG_INT_STATUS);\n\tag71xx_dump_intr(ag, \"raw\", status);\n\n\tif (unlikely(!status))\n\t\treturn IRQ_NONE;\n\n\tif (unlikely(status & AG71XX_INT_ERR)) {\n\t\tif (status & AG71XX_INT_TX_BE) {\n\t\t\tag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE);\n\t\t\tdev_err(&dev->dev, \"TX BUS error\\n\");\n\t\t}\n\t\tif (status & AG71XX_INT_RX_BE) {\n\t\t\tag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE);\n\t\t\tdev_err(&dev->dev, \"RX BUS error\\n\");\n\t\t}\n\t}\n\n\tif (likely(status & AG71XX_INT_POLL)) {\n\t\tag71xx_int_disable(ag, AG71XX_INT_POLL);\n\t\tDBG(\"%s: enable polling mode\\n\", dev->name);\n\t\tnapi_schedule(&ag->napi);\n\t}\n\n\tag71xx_debugfs_update_int_stats(ag, status);\n\n\treturn IRQ_HANDLED;\n}\n\nstatic int ag71xx_change_mtu(struct net_device *dev, int new_mtu)\n{\n\tstruct ag71xx *ag = netdev_priv(dev);\n\n\tdev->mtu = new_mtu;\n\tag71xx_wr(ag, AG71XX_REG_MAC_MFL,\n\t\t  ag71xx_max_frame_len(dev->mtu));\n\n\treturn 0;\n}\n\nstatic const struct net_device_ops ag71xx_netdev_ops = {\n\t.ndo_open\t\t= ag71xx_open,\n\t.ndo_stop\t\t= ag71xx_stop,\n\t.ndo_start_xmit\t\t= ag71xx_hard_start_xmit,\n\t.ndo_do_ioctl\t\t= ag71xx_do_ioctl,\n\t.ndo_tx_timeout\t\t= ag71xx_tx_timeout,\n\t.ndo_change_mtu\t\t= ag71xx_change_mtu,\n\t.ndo_set_mac_address\t= eth_mac_addr,\n\t.ndo_validate_addr\t= eth_validate_addr,\n};\n\nstatic int ag71xx_probe(struct platform_device *pdev)\n{\n\tstruct device_node *np = pdev->dev.of_node;\n\tstruct net_device *dev;\n\tstruct resource *res;\n\tstruct ag71xx *ag;\n\tu32 max_frame_len;\n\tint tx_size, err;\n\n\tif (!np)\n\t\treturn -ENODEV;\n\n\tdev = devm_alloc_etherdev(&pdev->dev, sizeof(*ag));\n\tif (!dev)\n\t\treturn -ENOMEM;\n\n\tres = platform_get_resource(pdev, IORESOURCE_MEM, 0);\n\tif (!res)\n\t\treturn -EINVAL;\n\n\tif (of_property_read_bool(np, \"qca956x-serdes-fixup\")) {\n\t\tag71xx_sgmii_serdes_init_qca956x(np);\n\t\tag71xx_sgmii_init_qca955x(np);\n\t}\n\n\terr = ag71xx_setup_gmac(np);\n\tif (err)\n\t\treturn err;\n\n\tSET_NETDEV_DEV(dev, &pdev->dev);\n\n\tag = netdev_priv(dev);\n\tag->pdev = pdev;\n\tag->dev = dev;\n\tag->msg_enable = netif_msg_init(ag71xx_msg_level,\n\t\t\t\t\tAG71XX_DEFAULT_MSG_ENABLE);\n\tspin_lock_init(&ag->lock);\n\n\tag->mac_reset = devm_reset_control_get_exclusive(&pdev->dev, \"mac\");\n\tif (IS_ERR(ag->mac_reset)) {\n\t\tdev_err(&pdev->dev, \"missing mac reset\\n\");\n\t\treturn PTR_ERR(ag->mac_reset);\n\t}\n\n\tag->mdio_reset = devm_reset_control_get_optional_exclusive(&pdev->dev, \"mdio\");\n\n\tif (of_property_read_u32_array(np, \"fifo-data\", ag->fifodata, 3)) {\n\t\tif (of_device_is_compatible(np, \"qca,ar9130-eth\") ||\n\t\t    of_device_is_compatible(np, \"qca,ar7100-eth\")) {\n\t\t\tag->fifodata[0] = 0x0fff0000;\n\t\t\tag->fifodata[1] = 0x00001fff;\n\t\t} else {\n\t\t\tag->fifodata[0] = 0x0010ffff;\n\t\t\tag->fifodata[1] = 0x015500aa;\n\t\t\tag->fifodata[2] = 0x01f00140;\n\t\t}\n\t\tif (of_device_is_compatible(np, \"qca,ar9130-eth\"))\n\t\t\tag->fifodata[2] = 0x00780fff;\n\t\telse if (of_device_is_compatible(np, \"qca,ar7100-eth\"))\n\t\t\tag->fifodata[2] = 0x008001ff;\n\t}\n\n\tif (of_property_read_u32_array(np, \"pll-data\", ag->plldata, 3))\n\t\tdev_dbg(&pdev->dev, \"failed to read pll-data property\\n\");\n\n\tif (of_property_read_u32_array(np, \"pll-reg\", ag->pllreg, 3))\n\t\tdev_dbg(&pdev->dev, \"failed to read pll-reg property\\n\");\n\n\tag->pllregmap = syscon_regmap_lookup_by_phandle(np, \"pll-handle\");\n\tif (IS_ERR(ag->pllregmap)) {\n\t\tdev_dbg(&pdev->dev, \"failed to read pll-handle property\\n\");\n\t\tag->pllregmap = NULL;\n\t}\n\n\tag->mac_base = devm_ioremap(&pdev->dev, res->start,\n\t\t\t\t    res->end - res->start + 1);\n\tif (!ag->mac_base)\n\t\treturn -ENOMEM;\n\n\tres = platform_get_resource(pdev, IORESOURCE_MEM, 1);\n\tif (res) {\n\t\tag->mii_base = devm_ioremap(&pdev->dev, res->start,\n\t\t\t\t\t    res->end - res->start + 1);\n\t\tif (!ag->mii_base)\n\t\t\treturn -ENOMEM;\n\t}\n\n\t/* ensure that HW is in manual polling mode before interrupts are\n\t * activated. Otherwise ag71xx_interrupt might call napi_schedule\n\t * before it is initialized by netif_napi_add.\n\t */\n\tag71xx_int_disable(ag, AG71XX_INT_POLL);\n\n\tdev->irq = platform_get_irq(pdev, 0);\n\terr = devm_request_irq(&pdev->dev, dev->irq, ag71xx_interrupt,\n\t\t\t       0x0, dev_name(&pdev->dev), dev);\n\tif (err) {\n\t\tdev_err(&pdev->dev, \"unable to request IRQ %d\\n\", dev->irq);\n\t\treturn err;\n\t}\n\n\tdev->netdev_ops = &ag71xx_netdev_ops;\n\tdev->ethtool_ops = &ag71xx_ethtool_ops;\n\n\tINIT_DELAYED_WORK(&ag->restart_work, ag71xx_restart_work_func);\n\n\ttimer_setup(&ag->oom_timer, ag71xx_oom_timer_handler, 0);\n\n\ttx_size = AG71XX_TX_RING_SIZE_DEFAULT;\n\tag->rx_ring.order = ag71xx_ring_size_order(AG71XX_RX_RING_SIZE_DEFAULT);\n\n\tif (of_device_is_compatible(np, \"qca,ar9340-eth\") ||\n\t    of_device_is_compatible(np, \"qca,qca9530-eth\") ||\n\t    of_device_is_compatible(np, \"qca,qca9550-eth\") ||\n\t    of_device_is_compatible(np, \"qca,qca9560-eth\"))\n\t\tag->desc_pktlen_mask = SZ_16K - 1;\n\telse\n\t\tag->desc_pktlen_mask = SZ_4K - 1;\n\n\tif (ag->desc_pktlen_mask == SZ_16K - 1 &&\n\t    !of_device_is_compatible(np, \"qca,qca9550-eth\") &&\n\t    !of_device_is_compatible(np, \"qca,qca9560-eth\"))\n\t\tmax_frame_len = ag->desc_pktlen_mask;\n\telse\n\t\tmax_frame_len = 1540;\n\n\tdev->min_mtu = 68;\n\tdev->max_mtu = max_frame_len - ag71xx_max_frame_len(0);\n\n\tif (of_device_is_compatible(np, \"qca,ar7240-eth\") ||\n\t    of_device_is_compatible(np, \"qca,ar7241-eth\") ||\n\t    of_device_is_compatible(np, \"qca,ar7242-eth\") ||\n\t    of_device_is_compatible(np, \"qca,ar9330-eth\") ||\n\t    of_device_is_compatible(np, \"qca,ar9340-eth\") ||\n\t    of_device_is_compatible(np, \"qca,qca9530-eth\") ||\n\t    of_device_is_compatible(np, \"qca,qca9550-eth\") ||\n\t    of_device_is_compatible(np, \"qca,qca9560-eth\"))\n\t\tag->tx_hang_workaround = 1;\n\n\tag->rx_buf_offset = NET_SKB_PAD;\n\tif (!of_device_is_compatible(np, \"qca,ar7100-eth\") &&\n\t    !of_device_is_compatible(np, \"qca,ar9130-eth\"))\n\t\tag->rx_buf_offset += NET_IP_ALIGN;\n\n\tif (of_device_is_compatible(np, \"qca,ar7100-eth\")) {\n\t\tag->tx_ring.desc_split = AG71XX_TX_RING_SPLIT;\n\t\ttx_size *= AG71XX_TX_RING_DS_PER_PKT;\n\t}\n\tag->tx_ring.order = ag71xx_ring_size_order(tx_size);\n\n\tag->stop_desc = dmam_alloc_coherent(&pdev->dev,\n\t\t\t\t\t    sizeof(struct ag71xx_desc),\n\t\t\t\t\t    &ag->stop_desc_dma, GFP_KERNEL);\n\tif (!ag->stop_desc)\n\t\treturn -ENOMEM;\n\n\tag->stop_desc->data = 0;\n\tag->stop_desc->ctrl = 0;\n\tag->stop_desc->next = (u32) ag->stop_desc_dma;\n\n\tof_get_mac_address(np, dev->dev_addr);\n\tif (!is_valid_ether_addr(dev->dev_addr)) {\n\t\tdev_err(&pdev->dev, \"invalid MAC address, using random address\\n\");\n\t\teth_random_addr(dev->dev_addr);\n\t}\n\n\terr = of_get_phy_mode(np, &ag->phy_if_mode);\n\tif (err < 0) {\n\t\tdev_err(&pdev->dev, \"missing phy-mode property in DT\\n\");\n\t\treturn ag->phy_if_mode;\n\t}\n\n\tif (of_device_is_compatible(np, \"qca,qca9560-eth\") &&\n\t    ag->phy_if_mode == PHY_INTERFACE_MODE_SGMII)\n\t\tag71xx_mux_select_sgmii_qca956x(np);\n\n\tif (of_property_read_u32(np, \"qca,mac-idx\", &ag->mac_idx))\n\t\tag->mac_idx = -1;\n\tif (ag->mii_base)\n\t\tswitch (ag->mac_idx) {\n\t\tcase 0:\n\t\t\tath79_mii0_ctrl_set_if(ag);\n\t\t\tbreak;\n\t\tcase 1:\n\t\t\tath79_mii1_ctrl_set_if(ag);\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tbreak;\n\t\t}\n\n\tnetif_napi_add(dev, &ag->napi, ag71xx_poll, AG71XX_NAPI_WEIGHT);\n\n\tag71xx_dump_regs(ag);\n\n\tag71xx_wr(ag, AG71XX_REG_MAC_CFG1, 0);\n\n\tag71xx_hw_init(ag);\n\n\tag71xx_dump_regs(ag);\n\n\t/*\n\t * populate current node to register mdio-bus as a subdevice.\n\t * the mdio bus works independently on ar7241 and later chips\n\t * and we need to load mdio1 before gmac0, which can be done\n\t * by adding a \"simple-mfd\" compatible to gmac node. The\n\t * following code checks OF_POPULATED_BUS flag before populating\n\t * to avoid duplicated population.\n\t */\n\tif (!of_node_check_flag(np, OF_POPULATED_BUS)) {\n\t\terr = of_platform_populate(np, NULL, NULL, &pdev->dev);\n\t\tif (err)\n\t\t\treturn err;\n\t}\n\n\terr = ag71xx_phy_connect(ag);\n\tif (err)\n\t\treturn err;\n\n\terr = ag71xx_debugfs_init(ag);\n\tif (err)\n\t\tgoto err_phy_disconnect;\n\n\tplatform_set_drvdata(pdev, dev);\n\n\terr = register_netdev(dev);\n\tif (err) {\n\t\tdev_err(&pdev->dev, \"unable to register net device\\n\");\n\t\tplatform_set_drvdata(pdev, NULL);\n\t\tag71xx_debugfs_exit(ag);\n\t\tgoto err_phy_disconnect;\n\t}\n\n\tpr_info(\"%s: Atheros AG71xx at 0x%08lx, irq %d, mode: %s\\n\",\n\t\tdev->name, (unsigned long) ag->mac_base, dev->irq,\n\t\tphy_modes(ag->phy_if_mode));\n\n\treturn 0;\n\nerr_phy_disconnect:\n\tag71xx_phy_disconnect(ag);\n\treturn err;\n}\n\nstatic int ag71xx_remove(struct platform_device *pdev)\n{\n\tstruct net_device *dev = platform_get_drvdata(pdev);\n\tstruct ag71xx *ag;\n\n\tif (!dev)\n\t\treturn 0;\n\n\tag = netdev_priv(dev);\n\tag71xx_debugfs_exit(ag);\n\tag71xx_phy_disconnect(ag);\n\tunregister_netdev(dev);\n\tplatform_set_drvdata(pdev, NULL);\n\treturn 0;\n}\n\nstatic const struct of_device_id ag71xx_match[] = {\n\t{ .compatible = \"qca,ar7100-eth\" },\n\t{ .compatible = \"qca,ar7240-eth\" },\n\t{ .compatible = \"qca,ar7241-eth\" },\n\t{ .compatible = \"qca,ar7242-eth\" },\n\t{ .compatible = \"qca,ar9130-eth\" },\n\t{ .compatible = \"qca,ar9330-eth\" },\n\t{ .compatible = \"qca,ar9340-eth\" },\n\t{ .compatible = \"qca,qca9530-eth\" },\n\t{ .compatible = \"qca,qca9550-eth\" },\n\t{ .compatible = \"qca,qca9560-eth\" },\n\t{}\n};\n\nstatic struct platform_driver ag71xx_driver = {\n\t.probe\t\t= ag71xx_probe,\n\t.remove\t\t= ag71xx_remove,\n\t.driver = {\n\t\t.name\t= AG71XX_DRV_NAME,\n\t\t.of_match_table = ag71xx_match,\n\t}\n};\n\nstatic int __init ag71xx_module_init(void)\n{\n\tint ret;\n\n\tret = ag71xx_debugfs_root_init();\n\tif (ret)\n\t\tgoto err_out;\n\n\tret = platform_driver_register(&ag71xx_driver);\n\tif (ret)\n\t\tgoto err_debugfs_exit;\n\n\treturn 0;\n\nerr_debugfs_exit:\n\tag71xx_debugfs_root_exit();\nerr_out:\n\treturn ret;\n}\n\nstatic void __exit ag71xx_module_exit(void)\n{\n\tplatform_driver_unregister(&ag71xx_driver);\n\tag71xx_debugfs_root_exit();\n}\n\nmodule_init(ag71xx_module_init);\nmodule_exit(ag71xx_module_exit);\n\nMODULE_AUTHOR(\"Gabor Juhos <juhosg@openwrt.org>\");\nMODULE_AUTHOR(\"Imre Kaloz <kaloz@openwrt.org>\");\nMODULE_AUTHOR(\"Felix Fietkau <nbd@nbd.name>\");\nMODULE_LICENSE(\"GPL v2\");\nMODULE_ALIAS(\"platform:\" AG71XX_DRV_NAME);\n"
  },
  {
    "path": "target/linux/ath79/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_mdio.c",
    "content": "/*\n *  Atheros AR71xx built-in ethernet mac driver\n *\n *  Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>\n *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>\n *\n *  Based on Atheros' AG7100 driver\n *\n *  This program is free software; you can redistribute it and/or modify it\n *  under the terms of the GNU General Public License version 2 as published\n *  by the Free Software Foundation.\n */\n\n#include <linux/clk.h>\n#include <linux/of_mdio.h>\n#include \"ag71xx.h\"\n\n#define AG71XX_MDIO_RETRY\t1000\n#define AG71XX_MDIO_DELAY\t5\n\nstatic int bus_count;\n\nstatic int ag71xx_mdio_wait_busy(struct ag71xx_mdio *am)\n{\n\tint i;\n\n\tfor (i = 0; i < AG71XX_MDIO_RETRY; i++) {\n\t\tu32 busy;\n\n\t\tudelay(AG71XX_MDIO_DELAY);\n\n\t\tregmap_read(am->mii_regmap, AG71XX_REG_MII_IND, &busy);\n\t\tif (!busy)\n\t\t\treturn 0;\n\n\t\tudelay(AG71XX_MDIO_DELAY);\n\t}\n\n\tpr_err(\"%s: MDIO operation timed out\\n\", am->mii_bus->name);\n\n\treturn -ETIMEDOUT;\n}\n\nstatic int ag71xx_mdio_mii_read(struct mii_bus *bus, int addr, int reg)\n{\n\tstruct ag71xx_mdio *am = bus->priv;\n\tint err;\n\tint ret;\n\n\terr = ag71xx_mdio_wait_busy(am);\n\tif (err)\n\t\treturn 0xffff;\n\n\tregmap_write(am->mii_regmap, AG71XX_REG_MII_CMD, MII_CMD_WRITE);\n\tregmap_write(am->mii_regmap, AG71XX_REG_MII_ADDR,\n\t\t\t((addr & 0xff) << MII_ADDR_SHIFT) | (reg & 0xff));\n\tregmap_write(am->mii_regmap, AG71XX_REG_MII_CMD, MII_CMD_READ);\n\n\terr = ag71xx_mdio_wait_busy(am);\n\tif (err)\n\t\treturn 0xffff;\n\n\tregmap_read(am->mii_regmap, AG71XX_REG_MII_STATUS, &ret);\n\tret &= 0xffff;\n\tregmap_write(am->mii_regmap, AG71XX_REG_MII_CMD, MII_CMD_WRITE);\n\n\tDBG(\"mii_read: addr=%04x, reg=%04x, value=%04x\\n\", addr, reg, ret);\n\n\treturn ret;\n}\n\nstatic int ag71xx_mdio_mii_write(struct mii_bus *bus, int addr, int reg, u16 val)\n{\n\tstruct ag71xx_mdio *am = bus->priv;\n\n\tDBG(\"mii_write: addr=%04x, reg=%04x, value=%04x\\n\", addr, reg, val);\n\n\tregmap_write(am->mii_regmap, AG71XX_REG_MII_ADDR,\n\t\t\t((addr & 0xff) << MII_ADDR_SHIFT) | (reg & 0xff));\n\tregmap_write(am->mii_regmap, AG71XX_REG_MII_CTRL, val);\n\n\tag71xx_mdio_wait_busy(am);\n\n\treturn 0;\n}\n\nstatic const u32 ar71xx_mdio_div_table[] = {\n\t4, 4, 6, 8, 10, 14, 20, 28,\n};\n\nstatic const u32 ar7240_mdio_div_table[] = {\n\t2, 2, 4, 6, 8, 12, 18, 26, 32, 40, 48, 56, 62, 70, 78, 96,\n};\n\nstatic const u32 ar933x_mdio_div_table[] = {\n\t4, 4, 6, 8, 10, 14, 20, 28, 34, 42, 50, 58, 66, 74, 82, 98,\n};\n\nstatic int ag71xx_mdio_get_divider(struct device_node *np, u32 *div)\n{\n\tstruct clk *ref_clk = of_clk_get(np, 0);\n\tunsigned long ref_clock;\n\tu32 mdio_clock;\n\tconst u32 *table;\n\tint ndivs, i;\n\n\tif (IS_ERR(ref_clk))\n\t\treturn -EINVAL;\n\n\tref_clock = clk_get_rate(ref_clk);\n\tclk_put(ref_clk);\n\n\tif(of_property_read_u32(np, \"qca,mdio-max-frequency\", &mdio_clock)) {\n\t\tif (of_property_read_bool(np, \"builtin-switch\"))\n\t\t\tmdio_clock = 5000000;\n\t\telse\n\t\t\tmdio_clock = 2000000;\n\t}\n\n\tif (of_device_is_compatible(np, \"qca,ar9330-mdio\") ||\n\t\tof_device_is_compatible(np, \"qca,ar9340-mdio\")) {\n\t\ttable = ar933x_mdio_div_table;\n\t\tndivs = ARRAY_SIZE(ar933x_mdio_div_table);\n\t} else if (of_device_is_compatible(np, \"qca,ar7240-mdio\")) {\n\t\ttable = ar7240_mdio_div_table;\n\t\tndivs = ARRAY_SIZE(ar7240_mdio_div_table);\n\t} else {\n\t\ttable = ar71xx_mdio_div_table;\n\t\tndivs = ARRAY_SIZE(ar71xx_mdio_div_table);\n\t}\n\n\tfor (i = 0; i < ndivs; i++) {\n\t\tunsigned long t;\n\n\t\tt = ref_clock / table[i];\n\t\tif (t <= mdio_clock) {\n\t\t\t*div = i;\n\t\t\treturn 0;\n\t\t}\n\t}\n\n\treturn -ENOENT;\n}\n\nstatic int ag71xx_mdio_reset(struct mii_bus *bus)\n{\n\tstruct device_node *np = bus->dev.of_node;\n\tstruct ag71xx_mdio *am = bus->priv;\n\tbool builtin_switch;\n\tu32 t;\n\n\tbuiltin_switch = of_property_read_bool(np, \"builtin-switch\");\n\n\tif (ag71xx_mdio_get_divider(np, &t)) {\n\t\tif (of_device_is_compatible(np, \"qca,ar9340-mdio\"))\n\t\t\tt = MII_CFG_CLK_DIV_58;\n\t\telse if (builtin_switch)\n\t\t\tt = MII_CFG_CLK_DIV_10;\n\t\telse\n\t\t\tt = MII_CFG_CLK_DIV_28;\n\t}\n\n\tregmap_write(am->mii_regmap, AG71XX_REG_MII_CFG, t | MII_CFG_RESET);\n\tudelay(100);\n\n\tregmap_write(am->mii_regmap, AG71XX_REG_MII_CFG, t);\n\tudelay(100);\n\n\treturn 0;\n}\n\nstatic int ag71xx_mdio_probe(struct platform_device *pdev)\n{\n\tstruct device *amdev = &pdev->dev;\n\tstruct device_node *np = pdev->dev.of_node;\n\tstruct ag71xx_mdio *am;\n\tstruct mii_bus *mii_bus;\n\tbool builtin_switch;\n\tint i, err;\n\n\tam = devm_kzalloc(amdev, sizeof(*am), GFP_KERNEL);\n\tif (!am)\n\t\treturn -ENOMEM;\n\n\tam->mii_regmap = syscon_regmap_lookup_by_phandle(np, \"regmap\");\n\tif (IS_ERR(am->mii_regmap))\n\t\treturn PTR_ERR(am->mii_regmap);\n\n\tmii_bus = devm_mdiobus_alloc(amdev);\n\tif (!mii_bus)\n\t\treturn -ENOMEM;\n\n\tam->mdio_reset = devm_reset_control_get_exclusive(amdev, \"mdio\");\n\tbuiltin_switch = of_property_read_bool(np, \"builtin-switch\");\n\n\tmii_bus->name = \"ag71xx_mdio\";\n\tmii_bus->read = ag71xx_mdio_mii_read;\n\tmii_bus->write = ag71xx_mdio_mii_write;\n\tmii_bus->reset = ag71xx_mdio_reset;\n\tmii_bus->priv = am;\n\tmii_bus->parent = amdev;\n\tsnprintf(mii_bus->id, MII_BUS_ID_SIZE, \"%s.%d\", np->name, bus_count++);\n\n\tif (!builtin_switch &&\n\t    of_property_read_u32(np, \"phy-mask\", &mii_bus->phy_mask))\n\t\tmii_bus->phy_mask = 0;\n\n\tfor (i = 0; i < PHY_MAX_ADDR; i++)\n\t\tmii_bus->irq[i] = PHY_POLL;\n\n\tif (!IS_ERR(am->mdio_reset)) {\n\t\treset_control_assert(am->mdio_reset);\n\t\tmsleep(100);\n\t\treset_control_deassert(am->mdio_reset);\n\t\tmsleep(200);\n\t}\n\n\terr = of_mdiobus_register(mii_bus, np);\n\tif (err)\n\t\treturn err;\n\n\tam->mii_bus = mii_bus;\n\tplatform_set_drvdata(pdev, am);\n\n\treturn 0;\n}\n\nstatic int ag71xx_mdio_remove(struct platform_device *pdev)\n{\n\tstruct ag71xx_mdio *am = platform_get_drvdata(pdev);\n\n\tmdiobus_unregister(am->mii_bus);\n\treturn 0;\n}\n\nstatic const struct of_device_id ag71xx_mdio_match[] = {\n\t{ .compatible = \"qca,ar7240-mdio\" },\n\t{ .compatible = \"qca,ar9330-mdio\" },\n\t{ .compatible = \"qca,ar9340-mdio\" },\n\t{ .compatible = \"qca,ath79-mdio\" },\n\t{}\n};\n\nstatic struct platform_driver ag71xx_mdio_driver = {\n\t.probe\t\t= ag71xx_mdio_probe,\n\t.remove\t\t= ag71xx_mdio_remove,\n\t.driver = {\n\t\t.name\t = \"ag71xx-mdio\",\n\t\t.of_match_table = ag71xx_mdio_match,\n\t}\n};\n\nmodule_platform_driver(ag71xx_mdio_driver);\nMODULE_LICENSE(\"GPL\");\n"
  },
  {
    "path": "target/linux/ath79/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_phy.c",
    "content": "/*\n *  Atheros AR71xx built-in ethernet mac driver\n *\n *  Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>\n *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>\n *\n *  Based on Atheros' AG7100 driver\n *\n *  This program is free software; you can redistribute it and/or modify it\n *  under the terms of the GNU General Public License version 2 as published\n *  by the Free Software Foundation.\n */\n\n#include <linux/of_mdio.h>\n#include \"ag71xx.h\"\n\nstatic void ag71xx_phy_link_adjust(struct net_device *dev)\n{\n\tstruct ag71xx *ag = netdev_priv(dev);\n\tstruct phy_device *phydev = ag->phy_dev;\n\tunsigned long flags;\n\tint status_change = 0;\n\n\tspin_lock_irqsave(&ag->lock, flags);\n\n\tif (phydev->link) {\n\t\tif (ag->duplex != phydev->duplex\n\t\t    || ag->speed != phydev->speed) {\n\t\t\tstatus_change = 1;\n\t\t}\n\t}\n\n\tif (phydev->link != ag->link)\n\t\tstatus_change = 1;\n\n\tag->link = phydev->link;\n\tag->duplex = phydev->duplex;\n\tag->speed = phydev->speed;\n\n\tif (status_change)\n\t\tag71xx_link_adjust(ag);\n\n\tspin_unlock_irqrestore(&ag->lock, flags);\n}\n\nint ag71xx_phy_connect(struct ag71xx *ag)\n{\n\tstruct device_node *np = ag->pdev->dev.of_node;\n\tstruct device_node *phy_node;\n\tint ret;\n\n\tif (of_phy_is_fixed_link(np)) {\n\t\tret = of_phy_register_fixed_link(np);\n\t\tif (ret < 0) {\n\t\t\tdev_err(&ag->pdev->dev,\n\t\t\t\t\"Failed to register fixed PHY link: %d\\n\", ret);\n\t\t\treturn ret;\n\t\t}\n\n\t\tphy_node = of_node_get(np);\n\t} else {\n\t\tphy_node = of_parse_phandle(np, \"phy-handle\", 0);\n\t}\n\n\tif (!phy_node) {\n\t\tdev_err(&ag->pdev->dev,\n\t\t\t\"Could not find valid phy node\\n\");\n\t\treturn -ENODEV;\n\t}\n\n\tag->phy_dev = of_phy_connect(ag->dev, phy_node, ag71xx_phy_link_adjust,\n\t\t\t\t     0, ag->phy_if_mode);\n\n\tof_node_put(phy_node);\n\n\tif (!ag->phy_dev) {\n\t\tdev_err(&ag->pdev->dev,\n\t\t\t\"Could not connect to PHY device. Deferring probe.\\n\");\n\t\treturn -EPROBE_DEFER;\n\t}\n\n\tdev_info(&ag->pdev->dev, \"connected to PHY at %s [uid=%08x, driver=%s]\\n\",\n\t\t    phydev_name(ag->phy_dev),\n\t\t    ag->phy_dev->phy_id, ag->phy_dev->drv->name);\n\n\treturn 0;\n}\n\nvoid ag71xx_phy_disconnect(struct ag71xx *ag)\n{\n\tphy_disconnect(ag->phy_dev);\n}\n"
  },
  {
    "path": "target/linux/ath79/files/include/mfd/rb4xx-cpld.h",
    "content": "// SPDX-License-Identifier: GPL-2.0-only\n/*\n * CPLD driver for the MikroTik RouterBoard 4xx series\n *\n * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>\n * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>\n * Copyright (C) 2015 Bert Vermeulen <bert@biot.com>\n * Copyright (C) 2020 Christopher Hill <ch6574@gmail.com>\n *\n * This file was based on the driver for Linux 2.6.22 published by\n * MikroTik for their RouterBoard 4xx series devices.\n */\n#include <linux/spi/spi.h>\n\nstruct rb4xx_cpld {\n\tstruct spi_device *spi;\n\n\tint (*write_nand)(struct rb4xx_cpld *self, const void *tx_buf,\n\t\t\t  unsigned int len);\n\tint (*read_nand)(struct rb4xx_cpld *self, void *rx_buf,\n\t\t\t unsigned int len);\n\n\tint (*gpio_set_0_7)(struct rb4xx_cpld *self, u8 values);\n\tint (*gpio_set_8)(struct rb4xx_cpld *self, u8 value);\n};\n"
  },
  {
    "path": "target/linux/ath79/generic/base-files/etc/board.d/01_leds",
    "content": "\n. /lib/functions/uci-defaults.sh\n\nboard_config_update\n\nboard=$(board_name)\n\ncase \"$board\" in\n8dev,carambola2)\n\tucidef_set_led_netdev \"lan\" \"LAN\" \"orange:eth0\" \"eth0\"\n\tucidef_set_led_switch \"wan\" \"WAN\" \"orange:eth1\" \"switch0\" \"0x04\"\n\t;;\nalfa-network,ap121f|\\\nalfa-network,ap121fe|\\\navm,fritz450e|\\\nglinet,6408|\\\nglinet,6416|\\\nglinet,gl-ar300m-lite|\\\nglinet,gl-ar300m16|\\\npcs,cap324|\\\ntplink,cpe610-v1|\\\ntplink,cpe610-v2|\\\ntplink,tl-wa1201-v2)\n\tucidef_set_led_netdev \"lan\" \"LAN\" \"green:lan\" \"eth0\"\n\t;;\nalfa-network,n2q)\n\tucidef_set_led_netdev \"lan2\" \"LAN2\" \"orange:lan2\" \"eth1\"\n\tucidef_set_led_switch \"lan1\" \"LAN1\" \"orange:lan1\" \"switch0\" \"0x10\"\n\tucidef_set_rssimon \"wlan0\" \"200000\" \"1\"\n\tucidef_set_led_rssi \"signal1\" \"SIGNAL1\" \"red:signal1\" \"wlan0\" \"1\" \"100\"\n\tucidef_set_led_rssi \"signal2\" \"SIGNAL2\" \"orange:signal2\" \"wlan0\" \"33\" \"100\"\n\tucidef_set_led_rssi \"signal3\" \"SIGNAL3\" \"green:signal3\" \"wlan0\" \"66\" \"100\"\n\t;;\nalfa-network,n5q)\n\tucidef_set_led_netdev \"lan2\" \"LAN2\" \"green:lan2\" \"eth1\"\n\tucidef_set_led_switch \"lan1\" \"LAN1\" \"green:lan1\" \"switch0\" \"0x10\"\n\tucidef_set_rssimon \"wlan0\" \"200000\" \"1\"\n\tucidef_set_led_rssi \"signal1\" \"SIGNAL1\" \"red:signal1\" \"wlan0\" \"1\" \"100\"\n\tucidef_set_led_rssi \"signal2\" \"SIGNAL2\" \"orange:signal2\" \"wlan0\" \"25\" \"100\"\n\tucidef_set_led_rssi \"signal3\" \"SIGNAL3\" \"green:signal3\" \"wlan0\" \"50\" \"100\"\n\tucidef_set_led_rssi \"signal4\" \"SIGNAL4\" \"green:signal4\" \"wlan0\" \"75\" \"100\"\n\t;;\nalfa-network,pi-wifi4)\n\tucidef_set_led_netdev \"lan_data\" \"LAN_DATA\" \"orange:lan_data\" \"eth0\" \"tx rx\"\n\tucidef_set_led_netdev \"lan_link\" \"LAN_LINK\" \"green:lan_link\" \"eth0\" \"link\"\n\t;;\nalfa-network,r36a)\n\tucidef_set_led_netdev \"lan\" \"LAN\" \"blue:lan\" \"eth0\"\n\tucidef_set_led_switch \"wan\" \"WAN\" \"blue:wan\" \"switch0\" \"0x10\"\n\t;;\nalfa-network,tube-2hq)\n\tucidef_set_led_netdev \"lan\" \"LAN\" \"blue:lan\" \"eth0\"\n\tucidef_set_rssimon \"wlan0\" \"200000\" \"1\"\n\tucidef_set_led_rssi \"signal1\" \"SIGNAL1\" \"red:signal1\" \"wlan0\" \"1\" \"100\"\n\tucidef_set_led_rssi \"signal2\" \"SIGNAL2\" \"orange:signal2\" \"wlan0\" \"25\" \"100\"\n\tucidef_set_led_rssi \"signal3\" \"SIGNAL3\" \"green:signal3\" \"wlan0\" \"50\" \"100\"\n\tucidef_set_led_rssi \"signal4\" \"SIGNAL4\" \"green:signal4\" \"wlan0\" \"75\" \"100\"\n\t;;\nasus,rp-ac66)\n\tucidef_set_rssimon \"wlan0\" \"200000\" \"1\"\n\tucidef_set_rssimon \"wlan1\" \"200000\" \"1\"\n\tucidef_set_led_rssi \"rssilow-wlan0\" \"RSSILOW\" \"blue:rssilow-wlan0\" \"wlan0\" \"1\" \"1\"\n\tucidef_set_led_rssi \"rssimedium-wlan0\" \"RSSIMEDIUM\" \"red:rssimedium-wlan0\" \"wlan0\" \"1\" \"79\"\n\tucidef_set_led_rssi \"rssihigh-wlan0\" \"RSSIHIGH\" \"green:rssihigh-wlan0\" \"wlan0\" \"70\" \"100\"\n\tucidef_set_led_rssi \"rssilow-wlan1\" \"RSSILOW\" \"blue:rssilow-wlan1\" \"wlan1\" \"1\" \"1\"\n\tucidef_set_led_rssi \"rssimedium-wlan1\" \"RSSIMEDIUM\" \"red:rssimedium-wlan1\" \"wlan1\" \"1\" \"79\"\n\tucidef_set_led_rssi \"rssihigh-wlan1\" \"RSSIHIGH\" \"green:rssihigh-wlan1\" \"wlan1\" \"70\" \"100\"\n\t;;\navm,fritz1750e)\n\tucidef_set_led_netdev \"lan\" \"LAN\" \"green:lan\" \"eth0\"\n\tucidef_set_rssimon \"wlan1\" \"200000\" \"1\"\n\tucidef_set_led_rssi \"rssilow\" \"RSSILOW\" \"green:rssi0\" \"wlan1\" \"1\" \"100\"\n\tucidef_set_led_rssi \"rssimediumlow\" \"RSSIMEDIUMLOW\" \"green:rssi1\" \"wlan1\" \"20\" \"100\"\n\tucidef_set_led_rssi \"rssimedium\" \"RSSIMEDIUM\" \"green:rssi2\" \"wlan1\" \"40\" \"100\"\n\tucidef_set_led_rssi \"rssimediumhigh\" \"RSSIMEDIUMHIGH\" \"green:rssi3\" \"wlan1\" \"60\" \"100\"\n\tucidef_set_led_rssi \"rssihigh\" \"RSSIHIGH\" \"green:rssi4\" \"wlan1\" \"80\" \"100\"\n\t;;\navm,fritz300e)\n\tucidef_set_led_netdev \"lan\" \"LAN\" \"green:lan\" \"eth0\"\n\tucidef_set_rssimon \"wlan0\" \"200000\" \"1\"\n\tucidef_set_led_rssi \"rssilow\" \"RSSILOW\" \"green:rssi0\" \"wlan0\" \"1\" \"100\"\n\tucidef_set_led_rssi \"rssimediumlow\" \"RSSIMEDIUMLOW\" \"green:rssi1\" \"wlan0\" \"20\" \"100\"\n\tucidef_set_led_rssi \"rssimedium\" \"RSSIMEDIUM\" \"green:rssi2\" \"wlan0\" \"40\" \"100\"\n\tucidef_set_led_rssi \"rssimediumhigh\" \"RSSIMEDIUMHIGH\" \"green:rssi3\" \"wlan0\" \"60\" \"100\"\n\tucidef_set_led_rssi \"rssihigh\" \"RSSIHIGH\" \"green:rssi4\" \"wlan0\" \"80\" \"100\"\n\t;;\navm,fritz4020|\\\ntplink,archer-c58-v1|\\\ntplink,archer-c59-v1|\\\ntplink,archer-c59-v2|\\\ntplink,archer-c60-v1|\\\ntplink,archer-c60-v2|\\\ntplink,archer-c60-v3|\\\ntplink,tl-wr841hp-v3)\n\tucidef_set_led_switch \"lan\" \"LAN\" \"green:lan\" \"switch0\" \"0x1e\"\n\tucidef_set_led_netdev \"wan\" \"WAN\" \"green:wan\" \"eth1\"\n\t;;\navm,fritzdvbc)\n\tucidef_set_rssimon \"wlan1\" \"200000\" \"1\"\n\tucidef_set_led_rssi \"rssilow\" \"RSSILOW\" \"green:rssilow\" \"wlan1\" \"1\" \"100\"\n\tucidef_set_led_rssi \"rssimediumlow\" \"RSSIMEDIUMLOW\" \"green:rssimediumlow\" \"wlan1\" \"20\" \"100\"\n\tucidef_set_led_rssi \"rssimedium\" \"RSSIMEDIUM\" \"green:rssimedium\" \"wlan1\" \"40\" \"100\"\n\tucidef_set_led_rssi \"rssimediumhigh\" \"RSSIMEDIUMHIGH\" \"green:rssimediumhigh\" \"wlan1\" \"60\" \"100\"\n\tucidef_set_led_rssi \"rssihigh\" \"RSSIHIGH\" \"green:rssihigh\" \"wlan1\" \"80\" \"100\"\n\t;;\nbuffalo,wzr-hp-g300nh-rb|\\\nbuffalo,wzr-hp-g300nh-s)\n\tucidef_set_led_netdev \"router\" \"Router\" \"green:router\" \"eth1\"\n\t;;\ncomfast,cf-e110n-v2)\n\tucidef_set_led_netdev \"lan\" \"LAN\" \"green:lan\" \"eth1\"\n\tucidef_set_led_switch \"wan\" \"WAN\" \"green:wan\" \"switch0\" \"0x02\"\n\tucidef_set_led_wlan \"wlan\" \"WLAN\" \"green:wlan\" \"phy0tpt\"\n\tucidef_set_rssimon \"wlan0\" \"200000\" \"1\"\n\tucidef_set_led_rssi \"rssilow\" \"RSSILOW\" \"red:rssilow\" \"wlan0\" \"1\" \"100\"\n\tucidef_set_led_rssi \"rssimediumlow\" \"RSSIMEDIUMLOW\" \"red:rssimediumlow\" \"wlan0\" \"26\" \"100\"\n\tucidef_set_led_rssi \"rssimediumhigh\" \"RSSIMEDIUMHIGH\" \"green:rssimediumhigh\" \"wlan0\" \"51\" \"100\"\n\tucidef_set_led_rssi \"rssihigh\" \"RSSIHIGH\" \"green:rssihigh\" \"wlan0\" \"76\" \"100\"\n\t;;\ncomfast,cf-e120a-v3)\n\tucidef_set_led_netdev \"lan\" \"LAN\" \"green:lan\" \"eth1\"\n\tucidef_set_led_switch \"wan\" \"WAN\" \"green:wan\" \"switch0\" \"0x04\"\n\tucidef_set_rssimon \"wlan0\" \"200000\" \"1\"\n\tucidef_set_led_rssi \"rssilow\" \"RSSILOW\" \"red:rssilow\" \"wlan0\" \"1\" \"100\"\n\tucidef_set_led_rssi \"rssimediumlow\" \"RSSIMEDIUMLOW\" \"red:rssimediumlow\" \"wlan0\" \"26\" \"100\"\n\tucidef_set_led_rssi \"rssimediumhigh\" \"RSSIMEDIUMHIGH\" \"green:rssimediumhigh\" \"wlan0\" \"51\" \"100\"\n\tucidef_set_led_rssi \"rssihigh\" \"RSSIHIGH\" \"green:rssihigh\" \"wlan0\" \"76\" \"100\"\n\t;;\ncomfast,cf-e130n-v2)\n\tucidef_set_led_netdev \"lan\" \"LAN\" \"green:lan\" \"eth0\"\n\tucidef_set_rssimon \"wlan0\" \"200000\" \"1\"\n\tucidef_set_led_rssi \"rssilow\" \"RSSILOW\" \"red:rssilow\" \"wlan0\" \"1\" \"100\"\n\tucidef_set_led_rssi \"rssimediumlow\" \"RSSIMEDIUMLOW\" \"red:rssimediumlow\" \"wlan0\" \"26\" \"100\"\n\tucidef_set_led_rssi \"rssimediumhigh\" \"RSSIMEDIUMHIGH\" \"green:rssimediumhigh\" \"wlan0\" \"51\" \"100\"\n\tucidef_set_led_rssi \"rssihigh\" \"RSSIHIGH\" \"green:rssihigh\" \"wlan0\" \"76\" \"100\"\n\t;;\ncomfast,cf-e313ac)\n\tucidef_set_led_switch \"lan\" \"LAN\" \"green:lan\" \"switch0\" \"0x02\"\n\tucidef_set_led_netdev \"wan\" \"WAN\" \"green:wan\" \"eth1\"\n\tucidef_set_rssimon \"wlan0\" \"200000\" \"1\"\n\tucidef_set_led_rssi \"rssilow\" \"RSSILOW\" \"red:rssilow\" \"wlan0\" \"1\" \"100\"\n\tucidef_set_led_rssi \"rssimediumlow\" \"RSSIMEDIUMLOW\" \"red:rssimediumlow\" \"wlan0\" \"26\" \"100\"\n\tucidef_set_led_rssi \"rssimediumhigh\" \"RSSIMEDIUMHIGH\" \"green:rssimediumhigh\" \"wlan0\" \"51\" \"100\"\n\tucidef_set_led_rssi \"rssihigh\" \"RSSIHIGH\" \"green:rssihigh\" \"wlan0\" \"76\" \"100\"\n\t;;\ncomfast,cf-e314n-v2)\n\tucidef_set_led_netdev \"wan\" \"WAN\" \"green:wan\" \"eth0\"\n\tucidef_set_led_netdev \"lan\" \"LAN\" \"green:lan\" \"eth1\"\n\tucidef_set_rssimon \"wlan0\" \"200000\" \"1\"\n\tucidef_set_led_rssi \"rssilow\" \"RSSILOW\" \"red:rssilow\" \"wlan0\" \"1\" \"100\"\n\tucidef_set_led_rssi \"rssimediumlow\" \"RSSIMEDIUMLOW\" \"red:rssimediumlow\" \"wlan0\" \"26\" \"100\"\n\tucidef_set_led_rssi \"rssimediumhigh\" \"RSSIMEDIUMHIGH\" \"green:rssimediumhigh\" \"wlan0\" \"51\" \"100\"\n\tucidef_set_led_rssi \"rssihigh\" \"RSSIHIGH\" \"green:rssihigh\" \"wlan0\" \"76\" \"100\"\n\t;;\ncomfast,cf-e375ac)\n\tucidef_set_led_switch \"lan\" \"LAN\" \"green:lan\" \"switch0\" \"0x04\"\n\tucidef_set_led_switch \"wan\" \"WAN\" \"red:wan\" \"switch0\" \"0x02\"\n\t;;\ncomfast,cf-e5)\n\tucidef_set_led_switch \"lan\" \"LAN\" \"blue:lan\" \"switch0\" \"0x02\"\n\tucidef_set_led_netdev \"wan\" \"WAN\" \"blue:wan\" \"eth1\"\n\tucidef_set_rssimon \"wlan0\" \"200000\" \"1\"\n\tucidef_set_led_rssi \"rssilow\" \"RSSILOW\" \"blue:rssi0\" \"wlan0\" \"1\" \"100\"\n\tucidef_set_led_rssi \"rssimedium\" \"RSSIMEDIUM\" \"blue:rssi1\" \"wlan0\" \"33\" \"100\"\n\tucidef_set_led_rssi \"rssihigh\" \"RSSIHIGH\" \"blue:rssi2\" \"wlan0\" \"66\" \"100\"\n\t;;\ncomfast,cf-e560ac)\n\tucidef_set_led_netdev \"wan\" \"WAN\" \"blue:wan\" \"eth1\"\n\tucidef_set_led_switch \"lan1\" \"LAN1\" \"blue:lan1\" \"switch0\" \"0x02\"\n\tucidef_set_led_switch \"lan2\" \"LAN2\" \"blue:lan2\" \"switch0\" \"0x04\"\n\tucidef_set_led_switch \"lan3\" \"LAN3\" \"blue:lan3\" \"switch0\" \"0x08\"\n\tucidef_set_led_switch \"lan4\" \"LAN4\" \"blue:lan4\" \"switch0\" \"0x10\"\n\t;;\ncomfast,cf-ew72|\\\nopenmesh,om2p-v2|\\\nopenmesh,om2p-hs-v1|\\\nopenmesh,om2p-hs-v2|\\\nopenmesh,om2p-hs-v3|\\\nopenmesh,om2p-lc|\\\nopenmesh,om5p|\\\ntelco,t1)\n\tucidef_set_led_switch \"lan\" \"LAN\" \"blue:lan\" \"switch0\" \"0x02\"\n\tucidef_set_led_netdev \"wan\" \"WAN\" \"blue:wan\" \"eth1\"\n\t;;\ncomfast,cf-wr752ac-v1|\\\nenterasys,ws-ap3705i|\\\nopenmesh,mr900-v1|\\\nopenmesh,mr900-v2|\\\nopenmesh,mr1750-v1|\\\nopenmesh,mr1750-v2|\\\ntplink,cpe710-v1)\n\tucidef_set_led_netdev \"lan\" \"LAN\" \"blue:lan\" \"eth0\"\n\t;;\ncompex,wpj344-16m|\\\ncompex,wpj531-16m)\n\tucidef_set_rssimon \"wlan0\" \"200000\" \"1\"\n\tucidef_set_led_rssi \"sig1\" \"SIG1\" \"red:sig1\" \"wlan0\" \"85\" \"100\"\n\tucidef_set_led_rssi \"sig2\" \"SIG2\" \"yellow:sig2\" \"wlan0\" \"75\" \"100\"\n\tucidef_set_led_rssi \"sig3\" \"SIG3\" \"green:sig3\" \"wlan0\" \"65\" \"100\"\n\tucidef_set_led_rssi \"sig4\" \"SIG4\" \"green:sig4\" \"wlan0\" \"50\" \"100\"\n\t;;\ndevolo,dlan-pro-1200plus-ac|\\\ndevolo,magic-2-wifi)\n\tucidef_set_led_netdev \"plcw\" \"dLAN\" \"white:dlan\" \"eth0.1\" \"rx\"\n\t;;\ndlink,dap-1330-a1|\\\ndlink,dap-1365-a1)\n\tucidef_set_rssimon \"wlan0\" \"200000\" \"1\"\n\tucidef_set_led_rssi \"rssilow\" \"RSSILOW\" \"red:rssilow\" \"wlan0\" \"1\" \"25\"\n\tucidef_set_led_rssi \"rssimediumlow\" \"RSSIMEDIUMLOW\" \"green:rssimediumlow\" \"wlan0\" \"1\" \"100\"\n\tucidef_set_led_rssi \"rssimediumhigh\" \"RSSIMEDIUMHIGH\" \"green:rssimediumhigh\" \"wlan0\" \"51\" \"100\"\n\tucidef_set_led_rssi \"rssihigh\" \"RSSIHIGH\" \"green:rssihigh\" \"wlan0\" \"76\" \"100\"\n\t;;\ndlink,dir-859-a1)\n\tucidef_set_led_switch \"internet\" \"WAN\" \"green:internet\" \"switch0\" \"0x20\"\n\t;;\nengenius,ens202ext-v1|\\\nengenius,enstationac-v1)\n\tucidef_set_rssimon \"wlan0\" \"200000\" \"1\"\n\tucidef_set_led_rssi \"rssilow\" \"RSSILOW\" \"red:rssilow\" \"wlan0\" \"1\"  \"100\"\n\tucidef_set_led_rssi \"rssimedium\" \"RSSIMEDIUM\" \"amber:rssimedium\" \"wlan0\" \"33\" \"100\"\n\tucidef_set_led_rssi \"rssihigh\" \"RSSIHIGH\" \"green:rssihigh\" \"wlan0\" \"67\" \"100\"\n\t;;\nengenius,ews511ap)\n\tucidef_set_led_netdev \"lan1\" \"LAN1\" \"blue:lan1\" \"eth1\"\n\tucidef_set_led_netdev \"lan2\" \"LAN2\" \"blue:lan2\" \"eth0\"\n\t;;\netactica,eg200)\n\tucidef_set_led_netdev \"lan\" \"LAN\" \"red:eth0\" \"eth0\"\n\tucidef_set_led_oneshot \"modbus\" \"Modbus\" \"red:modbus\" \"100\" \"33\"\n\t;;\nglinet,gl-mifi|\\\nqxwlan,e600g-v2-8m|\\\nqxwlan,e600g-v2-16m|\\\nqxwlan,e600gac-v2-8m|\\\nqxwlan,e600gac-v2-16m|\\\nqxwlan,e750a-v4-8m|\\\nqxwlan,e750a-v4-16m)\n\tucidef_set_led_switch \"lan\" \"LAN\" \"green:lan\" \"switch0\" \"0x02\"\n\tucidef_set_led_netdev \"wan\" \"WAN\" \"green:wan\" \"eth1\"\n\t;;\nglinet,gl-x300b|\\\nglinet,gl-x750)\n\tucidef_set_led_netdev \"wan\" \"WAN\" \"green:wan\" \"eth1\"\n\t;;\nhak5,lan-turtle)\n\tucidef_set_led_netdev \"wan\" \"WAN\" \"orange:system\" \"eth1\"\n\t;;\njoyit,jt-or750i|\\\nyuncore,xd3200)\n\tucidef_set_led_default \"ath10k\" \"ath10k-disable\" \"ath10k-phy0\" \"0\"\n\t;;\nhiwifi,hc6361)\n\tucidef_set_led_netdev \"wan\" \"WAN\" \"blue:wan\" \"eth1\"\n\tucidef_set_led_wlan \"wlan\" \"WLAN\" \"blue:wlan\" \"phy0tpt\"\n\t;;\nmeraki,mr12|\\\ntplink,cpe210-v2|\\\ntplink,cpe210-v3)\n\tucidef_set_led_netdev \"lan\" \"LAN\" \"green:lan\" \"eth0\"\n\tucidef_set_rssimon \"wlan0\" \"200000\" \"1\"\n\tucidef_set_led_rssi \"rssilow\" \"RSSILOW\" \"green:link1\" \"wlan0\" \"1\" \"100\"\n\tucidef_set_led_rssi \"rssimediumlow\" \"RSSIMEDIUMLOW\" \"green:link2\" \"wlan0\" \"30\" \"100\"\n\tucidef_set_led_rssi \"rssimediumhigh\" \"RSSIMEDIUMHIGH\" \"green:link3\" \"wlan0\" \"60\" \"100\"\n\tucidef_set_led_rssi \"rssihigh\" \"RSSIHIGH\" \"green:link4\" \"wlan0\" \"80\" \"100\"\n\t;;\nmeraki,mr16)\n\tucidef_set_led_netdev \"wan\" \"WAN\" \"green:wan\" \"eth0\"\n\t;;\nnetgear,wnr2200-8m|\\\nnetgear,wnr2200-16m)\n\tucidef_set_led_netdev \"wan-amber\" \"WAN (amber)\" \"amber:wan\" \"eth0\"\n\tucidef_set_led_switch \"lan1green\" \"LAN1 (green)\" \"green:lan1\" \"switch0\" \"0x02\" \"0x04\"\n\tucidef_set_led_switch \"lan2green\" \"LAN2 (green)\" \"green:lan2\" \"switch0\" \"0x04\" \"0x04\"\n\tucidef_set_led_switch \"lan3green\" \"LAN3 (green)\" \"green:lan3\" \"switch0\" \"0x08\" \"0x04\"\n\tucidef_set_led_switch \"lan4green\" \"LAN4 (green)\" \"green:lan4\" \"switch0\" \"0x10\" \"0x04\"\n\tucidef_set_led_switch \"lan1amber\" \"LAN1 (amber)\" \"amber:lan1\" \"switch0\" \"0x02\" \"0x02\"\n\tucidef_set_led_switch \"lan2amber\" \"LAN2 (amber)\" \"amber:lan2\" \"switch0\" \"0x04\" \"0x02\"\n\tucidef_set_led_switch \"lan3amber\" \"LAN3 (amber)\" \"amber:lan3\" \"switch0\" \"0x08\" \"0x02\"\n\tucidef_set_led_switch \"lan4amber\" \"LAN4 (amber)\" \"amber:lan4\" \"switch0\" \"0x10\" \"0x02\"\n\t;;\nopenmesh,om2p-v4|\\\nopenmesh,om2p-hs-v4)\n\tucidef_set_led_netdev \"wan\" \"WAN\" \"blue:wan\" \"eth0\"\n\tucidef_set_led_switch \"lan\" \"LAN\" \"blue:lan\" \"switch0\" \"0x02\"\n\t;;\nopenmesh,om2p-v1)\n\tucidef_set_led_netdev \"wan\" \"WAN\" \"blue:wan\" \"eth0\"\n\tucidef_set_led_switch \"lan\" \"LAN\" \"blue:lan\" \"switch0\" \"0x10\"\n\t;;\nopenmesh,om5p-ac-v1)\n\tucidef_set_led_netdev \"lan\" \"LAN\" \"blue:lan\" \"eth0\"\n\tucidef_set_led_netdev \"wan\" \"WAN\" \"blue:wan\" \"eth1\"\n\t;;\nopenmesh,om5p-an)\n\tucidef_set_led_netdev \"lan\" \"LAN\" \"blue:lan\" \"eth0\"\n\tucidef_set_led_switch \"wan\" \"WAN\" \"blue:wan\" \"switch0\" \"0x02\"\n\t;;\npcs,cr3000)\n\tucidef_set_led_netdev \"wan\" \"WAN\" \"blue:wan\" \"eth1\"\n\tucidef_set_led_switch \"lan1\" \"LAN1\" \"blue:lan1\" \"switch0\" \"0x04\"\n\tucidef_set_led_switch \"lan2\" \"LAN2\" \"blue:lan2\" \"switch0\" \"0x08\"\n\tucidef_set_led_switch \"lan3\" \"LAN3\" \"blue:lan3\" \"switch0\" \"0x10\"\n\tucidef_set_led_switch \"lan4\" \"LAN4\" \"blue:lan4\" \"switch0\" \"0x02\"\n\t;;\nqca,ap143-8m|\\\nqca,ap143-16m)\n\tucidef_set_led_netdev \"wan\" \"WAN\" \"green:wan\" \"eth1\"\n\tucidef_set_led_switch \"lan1\" \"LAN1\" \"green:lan1\" \"switch0\" \"0x02\"\n\tucidef_set_led_switch \"lan2\" \"LAN2\" \"green:lan2\" \"switch0\" \"0x04\"\n\tucidef_set_led_switch \"lan3\" \"LAN3\" \"green:lan3\" \"switch0\" \"0x08\"\n\tucidef_set_led_switch \"lan4\" \"LAN4\" \"green:lan4\" \"switch0\" \"0x10\"\n\t;;\nqihoo,c301)\n\tucidef_set_led_wlan \"wlan\" \"WLAN\" \"green:wlan\" \"phy0tpt\"\n\t;;\nsamsung,wam250)\n\tucidef_set_led_netdev \"lan\" \"LAN\" \"white:lan\" \"eth0\"\n\t;;\nteltonika,rut230-v1)\n\tucidef_set_led_netdev \"wan\" \"WAN\" \"green:wan\" \"eth1\"\n\tucidef_set_led_switch \"lan\" \"LAN\" \"green:lan\" \"switch0\" \"0x04\"\n\t;;\ntplink,archer-a7-v5|\\\ntplink,archer-c7-v4|\\\ntplink,archer-c7-v5)\n\tucidef_set_led_switch \"wan\" \"WAN\" \"green:wan\" \"switch0\" \"0x02\"\n\tucidef_set_led_switch \"lan1\" \"LAN1\" \"green:lan1\" \"switch0\" \"0x04\"\n\tucidef_set_led_switch \"lan2\" \"LAN2\" \"green:lan2\" \"switch0\" \"0x08\"\n\tucidef_set_led_switch \"lan3\" \"LAN3\" \"green:lan3\" \"switch0\" \"0x10\"\n\tucidef_set_led_switch \"lan4\" \"LAN4\" \"green:lan4\" \"switch0\" \"0x20\"\n\t;;\ntplink,archer-a9-v6)\n\tucidef_set_led_switch \"wan\" \"WAN\" \"green:wan\" \"switch0\" \"0x02\"\n\t;;\ntplink,archer-c2-v3|\\\ntplink,tl-wr1043nd-v4|\\\ntplink,tl-wr1043n-v5)\n\tucidef_set_led_switch \"wan\" \"WAN\" \"green:wan\" \"switch0\" \"0x20\"\n\tucidef_set_led_switch \"lan1\" \"LAN1\" \"green:lan1\" \"switch0\" \"0x10\"\n\tucidef_set_led_switch \"lan2\" \"LAN2\" \"green:lan2\" \"switch0\" \"0x08\"\n\tucidef_set_led_switch \"lan3\" \"LAN3\" \"green:lan3\" \"switch0\" \"0x04\"\n\tucidef_set_led_switch \"lan4\" \"LAN4\" \"green:lan4\" \"switch0\" \"0x02\"\n\t;;\ntplink,archer-c6-v2|\\\ntplink,archer-c6-v2-us)\n\tucidef_set_led_switch \"lan\" \"LAN\" \"green:lan\" \"switch0\" \"0x3c\"\n\tucidef_set_led_switch \"wan\" \"WAN\" \"green:wan\" \"switch0\" \"0x02\"\n\t;;\ntplink,archer-c25-v1|\\\ntplink,tl-wr842n-v3)\n\tucidef_set_led_netdev \"wan\" \"WAN\" \"green:wan\" \"eth1\"\n\tucidef_set_led_switch \"lan1\" \"LAN1\" \"green:lan1\" \"switch0\" \"0x10\"\n\tucidef_set_led_switch \"lan2\" \"LAN2\" \"green:lan2\" \"switch0\" \"0x08\"\n\tucidef_set_led_switch \"lan3\" \"LAN3\" \"green:lan3\" \"switch0\" \"0x04\"\n\tucidef_set_led_switch \"lan4\" \"LAN4\" \"green:lan4\" \"switch0\" \"0x02\"\n\t;;\ntplink,archer-d50-v1)\n\tucidef_set_led_switch \"lan\" \"LAN\" \"white:lan\" \"switch0\" \"0x1c\"\n\tucidef_set_led_switch \"wan_data\" \"WAN Data\" \"white:internet\" \"switch0\" \"0x02\" \"\" \"tx rx\"\n\tucidef_set_led_switch \"wan_link\" \"WAN Link\" \"white:wan\" \"switch0\" \"0x02\" \"\" \"link\"\n\t;;\ntplink,archer-d7-v1|\\\ntplink,archer-d7b-v1)\n\tucidef_set_led_switch \"lan\" \"LAN\" \"white:lan\" \"switch0\" \"0x3c\"\n\t;;\ntplink,cpe210-v1|\\\ntplink,cpe220-v2|\\\ntplink,cpe220-v3|\\\ntplink,cpe510-v1|\\\ntplink,wbs210-v1|\\\ntplink,wbs210-v2|\\\ntplink,wbs510-v1|\\\ntplink,wbs510-v2)\n\tucidef_set_led_netdev \"lan0\" \"LAN0\" \"green:lan0\" \"eth1\"\n\tucidef_set_led_switch \"lan1\" \"LAN1\" \"green:lan1\" \"switch0\" \"0x10\"\n\tucidef_set_rssimon \"wlan0\" \"200000\" \"1\"\n\tucidef_set_led_rssi \"rssilow\" \"RSSILOW\" \"green:link1\" \"wlan0\" \"1\" \"100\"\n\tucidef_set_led_rssi \"rssimediumlow\" \"RSSIMEDIUMLOW\" \"green:link2\" \"wlan0\" \"30\" \"100\"\n\tucidef_set_led_rssi \"rssimediumhigh\" \"RSSIMEDIUMHIGH\" \"green:link3\" \"wlan0\" \"60\" \"100\"\n\tucidef_set_led_rssi \"rssihigh\" \"RSSIHIGH\" \"green:link4\" \"wlan0\" \"80\" \"100\"\n\t;;\ntplink,cpe510-v2|\\\ntplink,cpe510-v3)\n\tucidef_set_led_netdev \"lan\" \"LAN\" \"green:lan\" \"eth0\"\n\tucidef_set_rssimon \"wlan0\" \"200000\" \"1\"\n\tucidef_set_led_rssi \"rssilow\" \"RSSILOW\" \"green:link1\" \"wlan0\" \"1\" \"100\" \"0\" \"13\"\n\tucidef_set_led_rssi \"rssimediumlow\" \"RSSIMEDIUMLOW\" \"green:link2\" \"wlan0\" \"26\" \"100\" \"-25\" \"13\"\n\tucidef_set_led_rssi \"rssimediumhigh\" \"RSSIMEDIUMHIGH\" \"green:link3\" \"wlan0\" \"51\" \"100\" \"-50\" \"13\"\n\tucidef_set_led_rssi \"rssihigh\" \"RSSIHIGH\" \"green:link4\" \"wlan0\" \"76\" \"100\" \"-75\" \"13\"\n\t;;\ntplink,tl-wr902ac-v1)\n\tucidef_set_led_netdev \"lan\" \"LAN\" \"green:lan\" \"eth0\"\n\tucidef_set_led_netdev \"internet\" \"Internet\" \"green:internet\" \"eth0\"\n\t;;\ntplink,re355-v1|\\\ntplink,re450-v1|\\\ntplink,re450-v2|\\\ntplink,re450-v3|\\\ntplink,re455-v1)\n\tucidef_set_led_netdev \"lan_data\" \"LAN Data\" \"green:lan_data\" \"eth0\" \"tx rx\"\n\tucidef_set_led_netdev \"lan_link\" \"LAN Link\" \"green:lan_link\" \"eth0\" \"link\"\n\t;;\ntplink,tl-mr6400-v1)\n\tucidef_set_led_switch \"lan\" \"LAN\" \"white:lan\" \"switch0\" \"0x0e\"\n\tucidef_set_led_netdev \"wan\" \"WAN\" \"white:wan\" \"eth1\"\n\tucidef_set_led_netdev \"4g\" \"4G\" \"white:4g\" \"usb0\"\n\t;;\ntplink,tl-wpa8630-v1)\n\tucidef_set_led_switch \"lan\" \"LAN\" \"green:lan\" \"switch0\" \"0x3c\"\n\t;;\ntplink,tl-wr841hp-v2|\\\ntplink,tl-wr842n-v2)\n\tucidef_set_led_netdev \"wan\" \"WAN\" \"green:wan\" \"eth1\"\n\tucidef_set_led_switch \"lan1\" \"LAN1\" \"green:lan1\" \"switch0\" \"0x04\"\n\tucidef_set_led_switch \"lan2\" \"LAN2\" \"green:lan2\" \"switch0\" \"0x08\"\n\tucidef_set_led_switch \"lan3\" \"LAN3\" \"green:lan3\" \"switch0\" \"0x10\"\n\tucidef_set_led_switch \"lan4\" \"LAN4\" \"green:lan4\" \"switch0\" \"0x02\"\n\t;;\ntplink,tl-wr941hp-v1)\n\tucidef_set_led_netdev \"wan\" \"WAN\" \"blue:wan\" \"eth1\" \"link tx rx\"\n\tucidef_set_led_switch \"lan\" \"LAN\" \"blue:lan\" \"switch0\" \"0x1e\"\n\t;;\ntrendnet,tew-823dru)\n\tucidef_set_led_netdev \"wan\" \"WAN\" \"green:planet\" \"eth0\"\n\t;;\nubnt,bullet-ac|\\\nubnt,nanobeam-ac|\\\nubnt,nanobeam-ac-gen2|\\\nubnt,nanobeam-ac-xc|\\\nubnt,nanostation-ac|\\\nubnt,powerbeam-5ac-gen2)\n\tucidef_set_rssimon \"wlan0\" \"200000\" \"1\"\n\tucidef_set_led_rssi \"rssilow\" \"RSSILOW\" \"blue:rssi0\" \"wlan0\" \"1\" \"100\"\n\tucidef_set_led_rssi \"rssimediumlow\" \"RSSIMEDIUMLOW\" \"blue:rssi1\" \"wlan0\" \"26\" \"100\"\n\tucidef_set_led_rssi \"rssimediumhigh\" \"RSSIMEDIUMHIGH\" \"blue:rssi2\" \"wlan0\" \"51\" \"100\"\n\tucidef_set_led_rssi \"rssihigh\" \"RSSIHIGH\" \"blue:rssi3\" \"wlan0\" \"76\" \"100\"\n\t;;\nubnt,bullet-m-ar7240|\\\nubnt,bullet-m-ar7241|\\\nubnt,bullet-m-xw|\\\nubnt,nanobridge-m|\\\nubnt,nanostation-loco-m|\\\nubnt,nanostation-loco-m-xw|\\\nubnt,nanostation-m|\\\nubnt,nanostation-m-xw|\\\nubnt,picostation-m|\\\nubnt,powerbeam-m2-xw|\\\nubnt,powerbeam-m5-xw|\\\nubnt,powerbridge-m|\\\nubnt,rocket-m)\n\tucidef_set_rssimon \"wlan0\" \"200000\" \"1\"\n\tucidef_set_led_rssi \"rssilow\" \"RSSILOW\" \"red:link1\" \"wlan0\" \"1\" \"100\"\n\tucidef_set_led_rssi \"rssimediumlow\" \"RSSIMEDIUMLOW\" \"orange:link2\" \"wlan0\" \"26\" \"100\"\n\tucidef_set_led_rssi \"rssimediumhigh\" \"RSSIMEDIUMHIGH\" \"green:link3\" \"wlan0\" \"51\" \"100\"\n\tucidef_set_led_rssi \"rssihigh\" \"RSSIHIGH\" \"green:link4\" \"wlan0\" \"76\" \"100\"\n\t;;\nwallys,dr531)\n\tucidef_set_led_netdev \"lan\" \"LAN\" \"green:lan\" \"eth0\"\n\tucidef_set_led_switch \"wan\" \"WAN\" \"green:wan\" \"switch0\" \"0x2\"\n\tucidef_set_rssimon \"wlan0\" \"200000\" \"1\"\n\tucidef_set_led_rssi \"sig1\" \"SIG1\" \"green:sig1\" \"wlan0\" \"1\" \"100\"\n\tucidef_set_led_rssi \"sig2\" \"SIG2\" \"green:sig2\" \"wlan0\" \"25\" \"100\"\n\tucidef_set_led_rssi \"sig3\" \"SIG3\" \"green:sig3\" \"wlan0\" \"50\" \"100\"\n\tucidef_set_led_rssi \"sig4\" \"SIG4\" \"green:sig4\" \"wlan0\" \"75\" \"100\"\n\t;;\nwd,mynet-wifi-rangeextender)\n\tucidef_set_led_netdev \"lan\" \"LAN\" \"green:lan\" \"eth0\"\n\tucidef_set_rssimon \"wlan0\" \"200000\" \"1\"\n\tucidef_set_led_rssi \"rssilow\" \"RSSILOW\" \"blue:rssi-low\" \"wlan0\" \"1\" \"100\"\n\tucidef_set_led_rssi \"rssimedium\" \"RSSIMED\" \"blue:rssi-med\" \"wlan0\" \"33\" \"100\"\n\tucidef_set_led_rssi \"rssihigh\" \"RSSIMAX\" \"blue:rssi-max\" \"wlan0\" \"66\" \"100\"\n\t;;\nxiaomi,aiot-ac2350)\n\tucidef_set_led_switch \"wan\" \"WAN\" \"blue:wan\" \"switch0\" \"0x02\"\n\t;;\nyuncore,a770)\n\tucidef_set_led_netdev \"wan\" \"WAN\" \"green:wan\" \"eth1\"\n\tucidef_set_led_switch \"lan\" \"LAN\" \"green:lan\" \"switch0\" \"0x10\"\n\t;;\nzbtlink,zbt-wd323)\n\tucidef_set_led_switch \"lan1\" \"LAN1\" \"orange:lan1\" \"switch0\" \"0x10\"\n\tucidef_set_led_switch \"lan2\" \"LAN2\" \"orange:lan2\" \"switch0\" \"0x08\"\n\t;;\nesac\n\nboard_config_flush\n\nexit 0\n"
  },
  {
    "path": "target/linux/ath79/generic/base-files/etc/board.d/02_network",
    "content": "\n. /lib/functions/system.sh\n. /lib/functions/uci-defaults.sh\n. /lib/functions/k2t.sh\n\nath79_setup_interfaces()\n{\n\tlocal board=\"$1\"\n\n\tcase \"$board\" in\n\tadtran,bsap1800-v2|\\\n\tadtran,bsap1840|\\\n\tallnet,all-wap02860ac|\\\n\talfa-network,ap121f|\\\n\talfa-network,pi-wifi4|\\\n\talfa-network,tube-2hq|\\\n\taraknis,an-300-ap-i-n|\\\n\taraknis,an-500-ap-i-ac|\\\n\taraknis,an-700-ap-i-ac|\\\n\tarduino,yun|\\\n\taruba,ap-105|\\\n\tasus,rp-ac66|\\\n\tavm,fritz1750e|\\\n\tavm,fritz300e|\\\n\tavm,fritzdvbc|\\\n\tcomfast,cf-wr752ac-v1|\\\n\tcomfast,cf-e130n-v2|\\\n\tdevolo,dvl1200i|\\\n\tdevolo,dvl1750c|\\\n\tdevolo,dvl1750i|\\\n\tdevolo,dvl1750x|\\\n\tdlink,dap-1330-a1|\\\n\tdlink,dap-1365-a1|\\\n\tdlink,dap-2230-a1|\\\n\tdlink,dap-2660-a1|\\\n\tdlink,dap-2680-a1|\\\n\tdlink,dap-3320-a1|\\\n\tdlink,dir-505|\\\n\tengenius,eap1200h|\\\n\tengenius,eap600|\\\n\tengenius,ecb1200|\\\n\tengenius,ecb1750|\\\n\tengenius,ecb600|\\\n\tenterasys,ws-ap3705i|\\\n\tglinet,gl-ar300m-lite|\\\n\tglinet,gl-usb150|\\\n\thak5,wifi-pineapple-nano|\\\n\tmeraki,mr16|\\\n\tnetgear,ex6400|\\\n\tnetgear,ex7300|\\\n\tnetgear,ex7300-v2|\\\n\tnetgear,wndap360|\\\n\tocedo,koala|\\\n\tocedo,raccoon|\\\n\tonion,omega|\\\n\topenmesh,mr600-v1|\\\n\topenmesh,mr600-v2|\\\n\topenmesh,mr900-v1|\\\n\topenmesh,mr900-v2|\\\n\topenmesh,mr1750-v1|\\\n\topenmesh,mr1750-v2|\\\n\tpcs,cap324|\\\n\tpisen,ts-d084|\\\n\tpisen,wmb001n|\\\n\tpisen,wmm003n|\\\n\tsiemens,ws-ap3610|\\\n\tsophos,ap55|\\\n\tsophos,ap55c|\\\n\tsophos,ap100|\\\n\tsophos,ap100c|\\\n\ttplink,cpe210-v2|\\\n\ttplink,cpe210-v3|\\\n\ttplink,cpe510-v2|\\\n\ttplink,cpe510-v3|\\\n\ttplink,cpe610-v1|\\\n\ttplink,cpe610-v2|\\\n\ttplink,cpe710-v1|\\\n\ttplink,eap225-outdoor-v1|\\\n\ttplink,eap225-v1|\\\n\ttplink,eap225-v3|\\\n\ttplink,eap245-v1|\\\n\ttplink,re350k-v1|\\\n\ttplink,re355-v1|\\\n\ttplink,re450-v1|\\\n\ttplink,re450-v2|\\\n\ttplink,re450-v3|\\\n\ttplink,re455-v1|\\\n\ttplink,tl-wa1201-v2|\\\n\ttplink,tl-wr902ac-v1|\\\n\tubnt,bullet-ac|\\\n\tubnt,bullet-m-ar7240|\\\n\tubnt,bullet-m-ar7241|\\\n\tubnt,bullet-m-xw|\\\n\tubnt,lap-120|\\\n\tubnt,litebeam-ac-gen2|\\\n\tubnt,nanobeam-ac|\\\n\tubnt,nanobeam-ac-xc|\\\n\tubnt,nanobridge-m|\\\n\tubnt,nanostation-ac-loco|\\\n\tubnt,nanostation-loco-m|\\\n\tubnt,nanostation-loco-m-xw|\\\n\tubnt,picostation-m|\\\n\tubnt,powerbeam-5ac-500|\\\n\tubnt,powerbeam-5ac-gen2|\\\n\tubnt,powerbeam-m2-xw|\\\n\tubnt,powerbeam-m5-xw|\\\n\tubnt,powerbridge-m|\\\n\tubnt,rocket-5ac-lite|\\\n\tubnt,rocket-m|\\\n\tubnt,unifiac-lite|\\\n\tubnt,unifiac-lr|\\\n\tubnt,unifiac-mesh|\\\n\tubnt,unifi|\\\n\twd,mynet-wifi-rangeextender|\\\n\twinchannel,wb2000)\n\t\tucidef_set_interface_lan \"eth0\"\n\t\t;;\n\tairtight,c-75)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0@eth0\" \"2:wan\" \"3:lan\" \"6@eth1\"\n\t\t;;\n\talfa-network,ap121fe)\n\t\tucidef_set_interface_lan \"eth0 usb0\"\n\t\t;;\n\talfa-network,n2q|\\\n\talfa-network,n5q|\\\n\tdevolo,dvl1200e|\\\n\tdevolo,dvl1750e|\\\n\tengenius,enstationac-v1|\\\n\tengenius,ews511ap|\\\n\tocedo,ursus|\\\n\tubnt,unifi-ap-outdoor-plus)\n\t\tucidef_set_interface_lan \"eth0 eth1\"\n\t\t;;\n\tatheros,db120)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0@eth0\" \"2:lan\" \"3:lan\" \"4:lan\" \"5:lan\" \"1:wan\"\n\t\tucidef_add_switch \"switch1\" \\\n\t\t\t\"0@eth1\" \"1:lan\" \"2:lan\" \"3:lan\" \"4:lan\" \"5:lan\"\n\t\t;;\n\tavm,fritz4020|\\\n\tpcs,cr3000|\\\n\ttplink,archer-c58-v1|\\\n\ttplink,archer-c59-v1|\\\n\ttplink,archer-c59-v2|\\\n\twd,mynet-n600)\n\t\tucidef_set_interface_wan \"eth1\"\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0@eth0\" \"1:lan:1\" \"2:lan:4\" \"3:lan:3\" \"4:lan:2\"\n\t\t;;\n\tbelkin,f9j1108-v2|\\\n\tbelkin,f9k1115-v2|\\\n\ttplink,archer-c5-v1|\\\n\ttplink,archer-c7-v1|\\\n\ttplink,archer-c7-v2|\\\n\ttplink,tl-wdr4900-v2|\\\n\ttplink,tl-wdr7500-v3)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0@eth1\" \"2:lan\" \"3:lan\" \"4:lan\" \"5:lan\" \"6@eth0\" \"1:wan\"\n\t\t;;\n\tbuffalo,bhr-4grv|\\\n\tbuffalo,wzr-hp-g450h)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0@eth0\" \"2:lan\" \"3:lan\" \"4:lan\" \"5:lan\" \"1:wan\"\n\t\t;;\n\tbuffalo,bhr-4grv2|\\\n\ttrendnet,tew-823dru)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0@eth1\" \"1:lan\" \"2:lan\" \"3:lan\" \"4:lan\" \"5:wan\" \"6@eth0\"\n\t\t;;\n\tbuffalo,wzr-600dhp|\\\n\tbuffalo,wzr-hp-ag300h|\\\n\ttplink,archer-c25-v1|\\\n\ttplink,archer-c60-v1|\\\n\ttplink,archer-c60-v2|\\\n\ttplink,archer-c60-v3|\\\n\ttplink,tl-wdr3500-v1|\\\n\ttplink,tl-wr842n-v1|\\\n\ttplink,tl-wr842n-v3|\\\n\tubnt,airrouter)\n\t\tucidef_set_interface_wan \"eth1\"\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0@eth0\" \"1:lan:4\" \"2:lan:3\" \"3:lan:2\" \"4:lan:1\"\n\t\t;;\n\tbuffalo,wzr-hp-g300nh-rb|\\\n\tbuffalo,wzr-hp-g300nh-s|\\\n\tdlink,dir-825-b1)\n\t\tucidef_set_interface_wan \"eth1\"\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0:lan\" \"1:lan\" \"2:lan\" \"3:lan\" \"5@eth0\"\n\t\t;;\n\tbuffalo,wzr-hp-g302h-a1a0)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0@eth0\" \"1:lan:1\" \"3:lan:4\" \"4:lan:3\" \"5:lan:2\" \"2:wan\"\n\t\t;;\n\tcomfast,cf-e110n-v2|\\\n\tcomfast,cf-e120a-v3|\\\n\tcomfast,cf-e314n-v2|\\\n\tcompex,wpj531-16m|\\\n\topenmesh,a40|\\\n\topenmesh,a60|\\\n\topenmesh,om2p-v1|\\\n\topenmesh,om2p-v4|\\\n\topenmesh,om2p-hs-v4|\\\n\tplasmacloud,pa300|\\\n\tplasmacloud,pa300e|\\\n\ttplink,cpe210-v1|\\\n\ttplink,cpe220-v2|\\\n\ttplink,cpe220-v3|\\\n\ttplink,cpe510-v1|\\\n\ttplink,wbs210-v1|\\\n\ttplink,wbs210-v2|\\\n\ttplink,wbs510-v1|\\\n\ttplink,wbs510-v2|\\\n\tubnt,nanostation-m|\\\n\tubnt,routerstation)\n\t\tucidef_set_interfaces_lan_wan \"eth1\" \"eth0\"\n\t\t;;\n\tcomfast,cf-e375ac)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0@eth0\" \"1:wan\" \"2:lan\"\n\t\t;;\n\tcomfast,cf-e560ac|\\\n\tqca,ap143-8m|\\\n\tqca,ap143-16m|\\\n\ttplink,tl-wr841hp-v3)\n\t\tucidef_set_interface_wan \"eth1\"\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0@eth0\" \"1:lan\" \"2:lan\" \"3:lan\" \"4:lan\"\n\t\t;;\n\tcomfast,cf-wr650ac-v1|\\\n\tcomfast,cf-wr650ac-v2|\\\n\tzyxel,nbg6616)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0@eth0\" \"1:lan\" \"2:lan\" \"3:lan\" \"4:lan\" \"5:wan\" \"6@eth1\"\n\t\t;;\n\tcompex,wpj344-16m|\\\n\tcompex,wpj563)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0@eth0\" \"3:lan\" \"2:wan\"\n\t\t;;\n\tcompex,wpj558-16m)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"1:wan\" \"5:lan\" \"6@eth0\"\n\t\t;;\n\tdevolo,dlan-pro-1200plus-ac|\\\n\tdevolo,magic-2-wifi)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0@eth0\" \"2:wan\" \"3:lan\" \"4:lan\"\n\t\t;;\n\tdlink,dap-2695-a1)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0@eth0\" \"2:lan\" \"3:wan\" \"6@eth1\"\n\t\t;;\n\tdlink,dap-3662-a1)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0@eth0\" \"1:lan:2\" \"2:lan:1\" \"6@eth1\"\n\t\t;;\n\tdlink,dch-g020-a1)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0@eth0\" \"1:lan:2\" \"2:lan:1\"\n\t\t;;\n\tdlink,dir-825-c1|\\\n\tdlink,dir-835-a1|\\\n\tdlink,dir-842-c1|\\\n\tdlink,dir-842-c2|\\\n\tdlink,dir-842-c3|\\\n\tdlink,dir-859-a1|\\\n\tengenius,epg5000|\\\n\tsitecom,wlr-7100|\\\n\ttplink,archer-c2-v3|\\\n\ttplink,tl-wr1043nd-v4|\\\n\ttplink,tl-wr1043n-v5)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0@eth0\" \"1:lan:4\" \"2:lan:3\" \"3:lan:2\" \"4:lan:1\" \"5:wan\"\n\t\t;;\n\telecom,wrc-1750ghbk2-i|\\\n\telecom,wrc-300ghbk2-i|\\\n\tsitecom,wlr-8100)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0@eth0\" \"2:lan:4\" \"3:lan:3\" \"4:lan:2\" \"5:lan:1\" \"1:wan\"\n\t\t;;\n\tembeddedwireless,balin)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0@eth0\" \"5:lan:1\" \"4:lan:2\" \"3:wan\"\n\t\t;;\n\tembeddedwireless,dorin)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0@eth0\" \"1:wan\" \"2:lan:3\" \"3:lan:2\"\n\t\t;;\n\tengenius,eap300-v2)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0@eth0\" \"1:lan\"\n\t\t;;\n\tengenius,ens202ext-v1)\n\t\tucidef_set_interface_lan \"eth1\"\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0@eth0\" \"1:lan\"\n\t\t;;\n\tetactica,eg200)\n\t\tucidef_set_interface_lan \"eth0\" \"dhcp\"\n\t\t;;\n\tglinet,gl-ar750)\n\t\tucidef_set_interface_wan \"eth1\"\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0@eth0\" \"1:lan\" \"2:lan\"\n\t\t;;\n\tglinet,gl-x300b)\n\t\tucidef_set_interface_wan \"eth1\"\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0@eth0\" \"4:lan\"\n\t\t;;\n\tiodata,etg3-r|\\\n\tiodata,wn-ac1167dgr|\\\n\tiodata,wn-ac1600dgr|\\\n\tiodata,wn-ac1600dgr2|\\\n\tiodata,wn-ag300dgr|\\\n\tpcs,cr5000|\\\n\twd,mynet-n750)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0@eth0\" \"1:lan\" \"2:lan\" \"3:lan\" \"4:lan\" \"5:wan\"\n\t\t;;\n\tjjplus,jwap230)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0@eth0\" \"5:wan:1\" \"1:lan:2\" \"6@eth1\"\n\t\t;;\n\tjoyit,jt-or750i)\n\t\tucidef_set_interface_wan \"eth1\"\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0@eth0\" \"2:lan:3\" \"3:lan:2\" \"4:lan:1\"\n\t\t;;\n\tletv,lba-047-ch)\n\t\tucidef_set_interface_wan \"eth0\"\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0@eth1\" \"3:lan:2\" \"4:lan:1\"\n\t\t;;\n\tlibrerouter,librerouter-v1)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0@eth0\" \"5:wan\" \"6@eth1\" \"4:lan\"\n\t\t;;\n\tmeraki,mr12)\n\t\tucidef_set_interface_lan \"eth0\"\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0@eth1\" \"1:lan\"\n\t\t;;\n\tmercury,mw4530r-v1|\\\n\ttplink,archer-a7-v5|\\\n\ttplink,archer-a9-v6|\\\n\ttplink,archer-c6-v2|\\\n\ttplink,archer-c6-v2-us|\\\n\ttplink,archer-c7-v4|\\\n\ttplink,archer-c7-v5|\\\n\ttplink,tl-wdr3600-v1|\\\n\ttplink,tl-wdr4300-v1|\\\n\ttplink,tl-wdr4300-v1-il|\\\n\ttplink,tl-wdr4310-v1)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0@eth0\" \"2:lan:1\" \"3:lan:2\" \"4:lan:3\" \"5:lan:4\" \"1:wan\"\n\t\t;;\n\tnec,wf1200cr)\n\t\tucidef_set_interface_wan \"eth1\"\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0@eth0\" \"1:lan\"\n\t\t;;\n\tnec,wg1200cr|\\\n\tqxwlan,e1700ac-v2-8m|\\\n\tqxwlan,e1700ac-v2-16m|\\\n\tqxwlan,e750g-v8-8m|\\\n\tqxwlan,e750g-v8-16m|\\\n\tubnt,nanobeam-ac-gen2|\\\n\tubnt,nanostation-ac|\\\n\tyuncore,a782|\\\n\tyuncore,xd3200|\\\n\tyuncore,xd4200)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0@eth0\" \"2:lan\" \"3:wan\"\n\t\t;;\n\tnec,wg800hp|\\\n\txiaomi,aiot-ac2350)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0@eth0\" \"2:lan\" \"3:lan\" \"4:lan\" \"1:wan\"\n\t\t;;\n\tnetgear,wndr3700|\\\n\tnetgear,wndr3700-v2|\\\n\tnetgear,wndr3800|\\\n\tnetgear,wndr3800ch|\\\n\tnetgear,wndrmac-v1|\\\n\tnetgear,wndrmac-v2)\n\t\tucidef_set_interface_wan \"eth1\"\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0:lan:4\" \"1:lan:3\" \"2:lan:2\" \"3:lan:1\" \"5u@eth0\"\n\t\tucidef_add_switch_attr \"switch0\" \"blinkrate\" 2\n\t\tucidef_add_switch_port_attr \"switch0\" 1 led 6\n\t\tucidef_add_switch_port_attr \"switch0\" 2 led 9\n\t\tucidef_add_switch_port_attr \"switch0\" 5 led 2\n\t\t;;\n\tnetgear,wnr2200-8m|\\\n\tnetgear,wnr2200-16m)\n\t\tucidef_set_interface_wan \"eth0\"\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0@eth1\" \"1:lan\" \"2:lan\" \"3:lan\" \"4:lan\"\n\t\t;;\n\tphicomm,k2t)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0@eth0\" \"3:lan:1\" \"5:lan:2\" \"4:wan\"\n\t\t;;\n\tqihoo,c301)\n\t\tucidef_set_interface_wan \"eth1\"\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0@eth0\" \"2:lan\" \"3:lan\"\n\t\t;;\n\tqxwlan,e558-v2-8m|\\\n\tqxwlan,e558-v2-16m)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0@eth1\" \"4:lan\" \"5:lan\" \"6@eth0\" \"3:wan\"\n\t\t;;\n\trosinson,wr818)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0@eth0\" \"1:lan\" \"2:lan\" \"3:wan\"\n\t\t;;\n\tteltonika,rut955|\\\n\tteltonika,rut955-h7v3c0)\n\t\tucidef_set_interface_wan \"eth1\"\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0@eth0\" \"2:lan:3\" \"3:lan:2\" \"4:lan:1\"\n\t\t;;\n\ttplink,archer-d50-v1)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0@eth0\" \"2:lan:3\" \"3:lan:2\" \"4:lan:1\" \"1:wan\"\n\t\t;;\n\ttplink,archer-d7-v1|\\\n\ttplink,archer-d7b-v1)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0@eth1\" \"3:lan:3\" \"4:lan:2\" \"5:lan:1\" \"6@eth0\" \"2:wan:4\" \"1:wan:5\"\n\t\t;;\n\ttplink,eap225-wall-v2)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0@eth0\" \"1:lan\" \"2:lan\" \"3:lan\" \"4:lan\"\n\t\t;;\n\ttplink,eap245-v3)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0@eth0\" \"2:lan:1\" \"5:lan:2\"\n\t\t;;\n\ttplink,tl-mr6400-v1)\n\t\tucidef_set_interfaces_lan_wan \"eth0.1 eth1\" \"usb0\"\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0@eth0\" \"1:lan:1\" \"2:lan:3\" \"3:lan:2\"\n\t\t;;\n\ttplink,tl-wpa8630-v1)\n\t\t# port 5 (internal) is the power-line port\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0@eth0\" \"2:lan:3\" \"3:lan:2\" \"4:lan:1\" \"5:lan:4\"\n\t\t;;\n\ttplink,tl-wr841hp-v2|\\\n\ttplink,tl-wr842n-v2|\\\n\ttplink,tl-wr941hp-v1)\n\t\tucidef_set_interface_wan \"eth1\"\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0@eth0\" \"1:lan:4\" \"2:lan:1\" \"3:lan:2\" \"4:lan:3\"\n\t\t;;\n\ttplink,tl-wr1043nd-v1)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"1:lan\" \"2:lan\" \"3:lan\" \"4:lan\" \"0:wan\" \"5@eth0\"\n\t\t;;\n\ttplink,tl-wr1043nd-v2|\\\n\ttplink,tl-wr1043nd-v3|\\\n\ttplink,tl-wr1045nd-v2)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0@eth1\" \"1:lan:4\" \"2:lan:3\" \"3:lan:2\" \"4:lan:1\" \"5:wan\" \"6@eth0\"\n\t\t;;\n\ttplink,tl-wr2543-v1)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"1:lan\" \"2:lan\" \"3:lan\" \"4:lan\" \"0:wan\" \"9@eth0\"\n\t\t;;\n\tubnt,aircube-ac)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0@eth0\" \"2:lan:1\" \"3:lan:2\" \"5:lan:3\" \"4:wan\"\n\t\t;;\n\tubnt,aircube-isp)\n\t\tucidef_set_interface_wan \"eth1\"\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0@eth0\" \"2:lan:1\" \"3:lan:3\" \"4:lan:2\"\n\t\t;;\n\tubnt,edgeswitch-5xp)\n\t\tucidef_set_interface_wan \"eth1\"\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0@eth0\" \"1:lan\" \"2:lan\" \"3:lan\" \"4:lan\" \"5:lan\"\n\t\t;;\n\tubnt,edgeswitch-8xp)\n\t\tucidef_set_interface_wan \"eth1\"\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0:lan:1\" \"1:lan:2\" \"2:lan:3\" \"3:lan:4\" \"4:lan:5\" \"5:lan:6\" \"6:lan:7\" \"7:lan:8\"  \"8@eth0\"\n\t\t;;\n\tubnt,routerstation-pro)\n\t\tucidef_set_interface_wan \"eth0\"\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0@eth1\" \"2:lan:3\" \"3:lan:2\" \"4:lan:1\"\n\t\t;;\n\tubnt,nanostation-m-xw)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0@eth0\" \"5:lan\" \"1:wan\"\n\t\t;;\n\tubnt,unifiac-mesh-pro|\\\n\tubnt,unifiac-pro)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0@eth0\" \"2:lan:1\" \"3:lan:2\"\n\t\t;;\n\tubnt,unifi-ap-pro)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0@eth0\" \"1:lan\" \"2:lan\"\n\t\t;;\n\ttplink,deco-m4r-v1)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0@eth0\" \"3:lan:1\" \"5:lan:2\"\n\t\t;;\n\thiwifi,hc6361|\\\n\txiaomi,mi-router-4q|\\\n\tzbtlink,zbt-wd323)\n\t\tucidef_set_interface_wan \"eth1\"\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0@eth0\" \"3:lan:1\" \"4:lan:2\"\n\t\t;;\n\t*)\n\t\tucidef_set_interfaces_lan_wan \"eth0\" \"eth1\"\n\t\t;;\n\tesac\n}\n\nath79_setup_macs()\n{\n\tlocal board=\"$1\"\n\n\tcase \"$board\" in\n\tadtran,bsap1800-v2|\\\n\tadtran,bsap1840)\n\t\tlan_mac=$(mtd_get_mac_binary \"Board data\" 2)\n\t\tlabel_mac=$lan_mac\n\t\t;;\n\talfa-network,ap121f|\\\n\talfa-network,ap121fe|\\\n\talfa-network,n2q|\\\n\talfa-network,n5q|\\\n\talfa-network,pi-wifi4|\\\n\talfa-network,r36a|\\\n\talfa-network,tube-2hq|\\\n\tengenius,eap300-v2|\\\n\tengenius,ens202ext-v1)\n\t\tlabel_mac=$(mtd_get_mac_binary art 0x1002)\n\t\t;;\n\tarduino,yun)\n\t\tbase_mac=$(mtd_get_mac_binary art 0x1002)\n\t\tlan_mac=$(macaddr_setbit $base_mac 29)\n\t\t[ $lan_mac = $base_mac ] && lan_mac=$(macaddr_unsetbit $base_mac 29)\n\t\t;;\n\tavm,fritz1750e|\\\n\tavm,fritz450e|\\\n\tavm,fritzdvbc)\n\t\tlabel_mac=$(fritz_tffs -n macwlan -i $(find_mtd_part \"tffs (1)\"))\n\t\t;;\n\tavm,fritz300e)\n\t\tlan_mac=$(fritz_tffs -n maca -i $(find_mtd_part \"tffs (1)\"))\n\t\tlabel_mac=$(fritz_tffs -n macwlan -i $(find_mtd_part \"tffs (1)\"))\n\t\t;;\n\tavm,fritz4020)\n\t\tlan_mac=$(fritz_tffs -n maca -i $(find_mtd_part \"tffs (1)\"))\n\t\twan_mac=$(fritz_tffs -n macb -i $(find_mtd_part \"tffs (1)\"))\n\t\t;;\n\tcomfast,cf-e375ac)\n\t\twan_mac=$(macaddr_add $(mtd_get_mac_binary art 0x0) 1)\n\t\t;;\n\tcompex,wpj344-16m|\\\n\tcompex,wpj558-16m|\\\n\tcompex,wpj563)\n\t\twan_mac=$(mtd_get_mac_binary u-boot 0x2e018)\n\t\t;;\n\tdevolo,dlan-pro-1200plus-ac|\\\n\tdevolo,magic-2-wifi)\n\t\tlabel_mac=$(macaddr_add \"$(mtd_get_mac_binary art 0x1002)\" 3)\n\t\t;;\n\tdlink,dap-1330-a1|\\\n\tdlink,dap-1365-a1|\\\n\tdlink,dch-g020-a1)\n\t\tlan_mac=$(mtd_get_mac_text \"mp\" 0x1)\n\t\tlabel_mac=$lan_mac\n\t\t;;\n\tdlink,dap-2230-a1|\\\n\tdlink,dap-2660-a1|\\\n\tdlink,dap-2680-a1|\\\n\tdlink,dap-3320-a1)\n\t\tlan_mac=$(mtd_get_mac_ascii bdcfg \"lanmac\")\n\t\tlabel_mac=$lan_mac\n\t\t;;\n\tdlink,dap-2695-a1|\\\n\tdlink,dap-3662-a1)\n\t\tlabel_mac=$(mtd_get_mac_ascii bdcfg \"wlanmac\")\n\t\t;;\n\tdlink,dir-825-b1)\n\t\tlan_mac=$(mtd_get_mac_text \"caldata\" 0xffa0)\n\t\twan_mac=$(mtd_get_mac_text \"caldata\" 0xffb4)\n\t\t;;\n\tdlink,dir-505)\n\t\tlan_mac=$(mtd_get_mac_text \"mac\" 0x4)\n\t\t;;\n\tdlink,dir-825-c1|\\\n\tdlink,dir-835-a1)\n\t\tlan_mac=$(mtd_get_mac_text \"mac\" 0x4)\n\t\twan_mac=$(mtd_get_mac_text \"mac\" 0x18)\n\t\t;;\n\tdlink,dir-842-c1|\\\n\tdlink,dir-842-c2|\\\n\tdlink,dir-842-c3)\n\t\tlan_mac=$(mtd_get_mac_ascii devdata \"lanmac\")\n\t\twan_mac=$(mtd_get_mac_ascii devdata \"wanmac\")\n\t\tlabel_mac=$lan_mac\n\t\t;;\n\tdlink,dir-859-a1|\\\n\tqihoo,c301|\\\n\twd,mynet-n600|\\\n\twd,mynet-n750)\n\t\tlan_mac=$(mtd_get_mac_ascii devdata \"lanmac\")\n\t\twan_mac=$(mtd_get_mac_ascii devdata \"wanmac\")\n\t\t;;\n\telecom,wrc-1750ghbk2-i|\\\n\telecom,wrc-300ghbk2-i)\n\t\twan_mac=$(macaddr_add \"$(mtd_get_mac_binary art 0x1002)\" -2)\n\t\t;;\n\tengenius,ecb1200|\\\n\tengenius,ecb1750)\n\t\tlan_mac=$(mtd_get_mac_ascii u-boot-env ethaddr)\n\t\tlabel_mac=$lan_mac\n\t\t;;\n\tengenius,epg5000)\n\t\tlan_mac=$(mtd_get_mac_ascii u-boot-env ethaddr)\n\t\twan_mac=$(mtd_get_mac_ascii u-boot-env wanaddr)\n\t\t;;\n\tengenius,ews511ap)\n\t\tlan_mac=$(mtd_get_mac_text \"u-boot-env\" 0xe9)\n\t\teth1_mac=$(macaddr_add \"$lan_mac\" 1)\n\t\tucidef_set_interface \"eth0\" ifname \"eth0\" protocol \"none\" macaddr \"$lan_mac\"\n\t\tucidef_set_interface \"eth1\" ifname \"eth1\" protocol \"none\" macaddr \"$eth1_mac\"\n\t\t;;\n\tenterasys,ws-ap3705i)\n\t\tlabel_mac=$(mtd_get_mac_ascii u-boot-env0 ethaddr)\n\t\t;;\n\thak5,lan-turtle|\\\n\thak5,packet-squirrel)\n\t\tlabel_mac=$(mtd_get_mac_binary u-boot 0x1fc00)\n\t\t;;\n\tiodata,etg3-r)\n\t\tlan_mac=$(mtd_get_mac_ascii u-boot-env ethaddr)\n\t\twan_mac=$(macaddr_add \"$lan_mac\" -1)\n\t\tlabel_mac=$wan_mac\n\t\t;;\n\tiodata,wn-ac1167dgr|\\\n\tiodata,wn-ac1600dgr|\\\n\tiodata,wn-ac1600dgr2|\\\n\tiodata,wn-ag300dgr)\n\t\tlan_mac=$(mtd_get_mac_ascii u-boot-env ethaddr)\n\t\twan_mac=$(mtd_get_mac_ascii u-boot-env wanaddr)\n\t\tlabel_mac=$wan_mac\n\t\t;;\n\tjjplus,ja76pf2)\n\t\twan_mac=$(fconfig -s -r -d $(find_mtd_part \"RedBoot config\") -n alias/ethaddr)\n\t\tlan_mac=$(macaddr_add \"$wan_mac\" 1)\n\t\t;;\n\tmercury,mw4530r-v1|\\\n\ttplink,tl-wdr3600-v1|\\\n\ttplink,tl-wdr4300-v1|\\\n\ttplink,tl-wdr4300-v1-il)\n\t\tbase_mac=$(mtd_get_mac_binary u-boot 0x1fc00)\n\t\twan_mac=$(macaddr_add \"$base_mac\" 1)\n\t\t;;\n\tnec,wf1200cr|\\\n\tnec,wg1200cr)\n\t\tlan_mac=$(mtd_get_mac_ascii devdata \"lanmac\")\n\t\twan_mac=$(mtd_get_mac_ascii devdata \"wanmac\")\n\t\tlabel_mac=$wan_mac\n\t\t;;\n\tnec,wg800hp)\n\t\tlan_mac=$(mtd_get_mac_text board_data 0x280)\n\t\twan_mac=$(mtd_get_mac_text board_data 0x480)\n\t\tlabel_mac=$wan_mac\n\t\t;;\n\tnetgear,wndr3700|\\\n\tnetgear,wndr3700-v2|\\\n\tnetgear,wndr3800|\\\n\tnetgear,wndrmac-v1|\\\n\tnetgear,wndrmac-v2)\n\t\tlan_mac=$(macaddr_setbit_la \"$(mtd_get_mac_binary art 0x0)\")\n\t\t;;\n\tphicomm,k2t)\n\t\tlan_mac=$(k2t_get_mac \"lan_mac\")\n\t\twan_mac=$(k2t_get_mac \"wan_mac\")\n\t\t;;\n\trosinson,wr818)\n\t\twan_mac=$(mtd_get_mac_binary factory 0x0)\n\t\tlan_mac=$(macaddr_setbit_la \"$wan_mac\")\n\t\t;;\n\tsitecom,wlr-7100|\\\n\tsitecom,wlr-8100)\n\t\tlan_mac=$(mtd_get_mac_ascii u-boot-env ethaddr)\n\t\twan_mac=$(mtd_get_mac_ascii u-boot-env wanaddr)\n\t\tlabel_mac=$lan_mac\n\t\t;;\n\ttplink,archer-a7-v5|\\\n\ttplink,archer-a9-v6|\\\n\ttplink,archer-c7-v4|\\\n\ttplink,archer-c7-v5|\\\n\ttplink,tl-wr1043nd-v4|\\\n\ttplink,tl-wr1043n-v5)\n\t\tbase_mac=$(mtd_get_mac_binary info 0x8)\n\t\twan_mac=$(macaddr_add \"$base_mac\" 1)\n\t\t;;\n\ttrendnet,tew-823dru)\n\t\tlan_mac=$(mtd_get_mac_text mac 0x4)\n\t\twan_mac=$(mtd_get_mac_text mac 0x18)\n\t\tlabel_mac=$wan_mac\n\t\t;;\n\tubnt,airrouter|\\\n\tubnt,bullet-m-ar7240|\\\n\tubnt,bullet-m-ar7241|\\\n\tubnt,nanobridge-m|\\\n\tubnt,nanostation-loco-m|\\\n\tubnt,nanostation-m|\\\n\tubnt,picostation-m|\\\n\tubnt,powerbridge-m|\\\n\tubnt,rocket-m|\\\n\tubnt,unifi)\n\t\tlabel_mac=$(cat /sys/class/ieee80211/phy0/macaddress)\n\t\t;;\n\tubnt,litebeam-ac-gen2|\\\n\tubnt,nanobeam-ac-gen2|\\\n\tubnt,nanobeam-ac-xc|\\\n\tubnt,powerbeam-5ac-500|\\\n\tubnt,powerbeam-5ac-gen2)\n\t\tlabel_mac=$(mtd_get_mac_binary art 0x5006)\n\t\t;;\n\tubnt,routerstation|\\\n\tubnt,routerstation-pro)\n\t\twan_mac=$(fconfig -s -r -d $(find_mtd_part \"RedBoot config\") -n ar7100_esa)\n\t\tlan_mac=$(macaddr_add \"$wan_mac\" 1)\n\t\t;;\n\twd,mynet-wifi-rangeextender)\n\t\tlan_mac=$(nvram get et0macaddr)\n\t\t;;\n\txiaomi,aiot-ac2350)\n\t\tlan_mac=$(mtd_get_mac_binary art 0x1002)\n\t\t;;\n\tzyxel,nbg6616)\n\t\tlabel_mac=$(mtd_get_mac_ascii u-boot-env ethaddr)\n\t\t;;\n\tesac\n\n\t[ -n \"$lan_mac\" ] && ucidef_set_interface_macaddr \"lan\" $lan_mac\n\t[ -n \"$wan_mac\" ] && ucidef_set_interface_macaddr \"wan\" $wan_mac\n\t[ -n \"$label_mac\" ] && ucidef_set_label_macaddr $label_mac\n}\n\nboard_config_update\nboard=$(board_name)\nath79_setup_interfaces $board\nath79_setup_macs $board\nboard_config_flush\n\nexit 0\n"
  },
  {
    "path": "target/linux/ath79/generic/base-files/etc/board.d/03_gpio_switches",
    "content": "#\n# Copyright (C) 2018 OpenWrt.org\n#\n\n. /lib/functions/uci-defaults.sh\n\nboard_config_update\n\nboard=$(board_name)\n\ncase \"$board\" in\nadtran,bsap1800-v2|\\\nadtran,bsap1840)\n\tucidef_add_gpio_switch \"wifi1_ext_a\" \"5GHz External Antenna A\" \"489\" \"1\"\n\tucidef_add_gpio_switch \"wifi1_int_a\" \"5GHz Internal Antenna A\" \"493\"\n\tucidef_add_gpio_switch \"wifi1_ext_b\" \"5GHz External Antenna B\" \"494\" \"1\"\n\tucidef_add_gpio_switch \"wifi1_int_b\" \"5GHz Internal Antenna B\" \"495\"\n\tucidef_add_gpio_switch \"wifi1_ext_c\" \"5GHz External Antenna C\" \"496\" \"1\"\n\tucidef_add_gpio_switch \"wifi1_int_c\" \"5GHz Internal Antenna C\" \"497\"\n\tucidef_add_gpio_switch \"wifi0_ext_a\" \"2.4GHz External Antenna A\" \"505\" \"1\"\n\tucidef_add_gpio_switch \"wifi0_int_a\" \"2.4GHz Internal Antenna A\" \"506\"\n\tucidef_add_gpio_switch \"wifi0_ext_b\" \"2.4GHz External Antenna B\" \"507\" \"1\"\n\tucidef_add_gpio_switch \"wifi0_int_b\" \"2.4GHz Internal Antenna B\" \"508\"\n\tucidef_add_gpio_switch \"wifi0_ext_c\" \"2.4GHz External Antenna C\" \"509\" \"1\"\n\tucidef_add_gpio_switch \"wifi0_int_c\" \"2.4GHz Internal Antenna C\" \"510\"\n\t;;\ncomfast,cf-e5|\\\ntelco,t1)\n\tucidef_add_gpio_switch \"lte_power\" \"LTE Power\" \"14\" \"1\"\n\tucidef_add_gpio_switch \"lte_wakeup\" \"LTE Wakeup\" \"11\" \"1\"\n\tucidef_add_gpio_switch \"lte_poweroff\" \"LTE Poweroff\" \"1\" \"1\"\n\tucidef_add_gpio_switch \"lte_reset\" \"LTE Reset\" \"12\" \"1\"\n\t;;\ndevolo,dlan-pro-1200plus-ac)\n\tucidef_add_gpio_switch \"plc_enable\" \"PLC enable\" \"13\" \"0\"\n\t;;\ndevolo,magic-2-wifi)\n\tucidef_add_gpio_switch \"plc_pairing\" \"PLC pairing\" \"11\" \"1\"\n\tucidef_add_gpio_switch \"plc_enable\" \"PLC enable\" \"13\" \"1\"\n\t;;\ndlink,dir-825-c1|\\\ndlink,dir-835-a1)\n\tucidef_add_gpio_switch \"wan_led_auto\" \"WAN LED Auto\" \"20\" \"0\"\n\t;;\nlibrerouter,librerouter-v1)\n\tucidef_add_gpio_switch \"poe_passthrough\" \"PoE Passthrough\" \"1\" \"0\"\n\t;;\nteltonika,rut955)\n\tucidef_add_gpio_switch \"sim_sel\" \"SIM select\" \"503\" \"1\"\n\tucidef_add_gpio_switch \"DOUT1\" \"DOUT1 (OC)\" \"504\" \"0\"\n\tucidef_add_gpio_switch \"DOUT2\" \"DOUT2 (Relay)\" \"505\" \"0\"\n\tucidef_add_gpio_switch \"modem_vbus\" \"Modem enable\" \"506\" \"1\"\n\tucidef_add_gpio_switch \"modem_rst\" \"Modem reset\" \"507\" \"0\"\n\tucidef_add_gpio_switch \"DOUT3\" \"DOUT3\" \"508\" \"0\"\n\t;;\nteltonika,rut955-h7v3c0)\n\tucidef_add_gpio_switch \"sim_sel\" \"SIM select\" \"503\" \"1\"\n\tucidef_add_gpio_switch \"DOUT1\" \"DOUT1 (OC)\" \"504\" \"0\"\n\tucidef_add_gpio_switch \"DOUT2\" \"DOUT2 (Relay)\" \"505\" \"0\"\n\tucidef_add_gpio_switch \"modem_vbus\" \"Modem enable\" \"508\" \"1\"\n\tucidef_add_gpio_switch \"modem_rst\" \"Modem reset\" \"509\" \"0\"\n\t;;\n\ntplink,archer-c25-v1)\n\tucidef_add_gpio_switch \"led_control\" \"LED control\" \"21\" \"0\"\n\tucidef_add_gpio_switch \"led_reset\" \"LED reset\" \"19\" \"1\"\n\t;;\ntplink,cpe210-v1|\\\ntplink,cpe220-v2|\\\ntplink,cpe220-v3|\\\ntplink,cpe510-v1|\\\ntplink,wbs210-v1|\\\ntplink,wbs210-v2|\\\ntplink,wbs510-v1|\\\ntplink,wbs510-v2)\n\tucidef_add_gpio_switch \"poe_passthrough\" \"PoE Passthrough\" \"20\"\n\t;;\nubnt,aircube-ac|\\\nubnt,nanobeam-ac-gen2|\\\nubnt,nanostation-ac)\n\tucidef_add_gpio_switch \"poe_passthrough\" \"PoE Passthrough\" \"3\"\n\t;;\nubnt,aircube-isp)\n\tucidef_add_gpio_switch \"poe_passthrough\" \"PoE Passthrough\" \"11\"\n\t;;\nubnt,nanostation-m)\n\tucidef_add_gpio_switch \"poe_passthrough\" \"PoE Passthrough\" \"8\"\n\t;;\nubnt,nanostation-m-xw)\n\tucidef_add_gpio_switch \"poe_passthrough\" \"PoE Passthrough\" \"2\"\n\t;;\nzbtlink,zbt-wd323)\n\tucidef_add_gpio_switch \"io0\" \"IO#0\" \"0\"\n\tucidef_add_gpio_switch \"io1\" \"IO#1\" \"1\"\n\tucidef_add_gpio_switch \"io2\" \"IO#2\" \"2\"\n\tucidef_add_gpio_switch \"io14\" \"IO#14\" \"14\"\n\t;;\nesac\n\nboard_config_flush\n\nexit 0\n"
  },
  {
    "path": "target/linux/ath79/generic/base-files/etc/hotplug.d/firmware/10-ath9k-eeprom",
    "content": "#!/bin/sh\n\n[ -e /lib/firmware/$FIRMWARE ] && exit 0\n\n. /lib/functions/caldata.sh\n\nboard=$(board_name)\n\ncase \"$FIRMWARE\" in\n\"ath9k-eeprom-ahb-18100000.wmac.bin\")\n\tcase $board in\n\t8dev,lima)\n\t\tcaldata_extract \"art\" 0x1000 0x800\n\t\t;;\n\tasus,rp-ac66)\n\t\tcaldata_extract \"art\" 0x1000 0x440\n\t\t;;\n\tavm,fritz1750e|\\\n\tavm,fritz4020|\\\n\tavm,fritz450e|\\\n\tavm,fritzdvbc)\n\t\tcaldata_extract_reverse \"urlader\" 0x1541 0x440\n\t\t;;\n\tdlink,dir-505|\\\n\tdlink,dir-825-c1|\\\n\tdlink,dir-835-a1)\n\t\tcaldata_extract \"art\" 0x1000 0x440\n\t\tath9k_patch_mac $(mtd_get_mac_text \"mac\" 0x4)\n\t\t;;\n\tdlink,dir-842-c1|\\\n\tdlink,dir-842-c2|\\\n\tdlink,dir-842-c3|\\\n\tdlink,dir-859-a1|\\\n\tnec,wf1200cr|\\\n\tnec,wg1200cr|\\\n\twd,mynet-n600|\\\n\twd,mynet-n750)\n\t\tcaldata_extract \"art\" 0x1000 0x440\n\t\tath9k_patch_mac $(mtd_get_mac_ascii devdata \"wlan24mac\")\n\t\t;;\n\tengenius,ecb1200|\\\n\tengenius,ecb1750)\n\t\tcaldata_extract \"art\" 0x1000 0x440\n\t\tath9k_patch_mac $(macaddr_add $(mtd_get_mac_ascii u-boot-env athaddr) 1)\n\t\t;;\n\tengenius,epg5000|\\\n\tiodata,wn-ac1167dgr|\\\n\tiodata,wn-ac1600dgr|\\\n\tiodata,wn-ac1600dgr2|\\\n\tiodata,wn-ag300dgr|\\\n\tsitecom,wlr-7100|\\\n\tsitecom,wlr-8100)\n\t\tcaldata_extract \"art\" 0x1000 0x440\n\t\tath9k_patch_mac $(mtd_get_mac_ascii u-boot-env ethaddr)\n\t\t;;\n\tenterasys,ws-ap3705i)\n\t\tcaldata_extract \"calibrate\" 0x1000 0x440\n\t\tath9k_patch_mac $(mtd_get_mac_ascii u-boot-env0 RADIOADDR1)\n\t\t;;\n\tnec,wg800hp)\n\t\tcaldata_extract \"art\" 0x1000 0x440\n\t\tath9k_patch_mac $(mtd_get_mac_text board_data 0x680)\n\t\t;;\n\tqihoo,c301)\n\t\tcaldata_extract \"radiocfg\" 0x1000 0x440\n\t\tath9k_patch_mac $(mtd_get_mac_ascii devdata \"wlan24mac\")\n\t\t;;\n\t*)\n\t\tcaldata_die \"board $board is not supported yet\"\n\t\t;;\n\tesac\n\t;;\n\"ath9k-eeprom-pci-0000:00:00.0.bin\")\n\tcase $board in\n\taraknis,an-300-ap-i-n|\\\n\tatheros,db120|\\\n\tengenius,eap600|\\\n\tengenius,ecb600|\\\n\tmercury,mw4530r-v1|\\\n\tocedo,raccoon|\\\n\ttplink,tl-wdr3500-v1|\\\n\ttplink,tl-wdr3600-v1|\\\n\ttplink,tl-wdr4300-v1|\\\n\ttplink,tl-wdr4300-v1-il|\\\n\ttplink,tl-wdr4310-v1|\\\n\ttplink,tl-wdr4900-v2|\\\n\tubnt,unifi-ap-pro|\\\n\twinchannel,wb2000)\n\t\tcaldata_extract \"art\" 0x5000 0x440\n\t\t;;\n\tavm,fritz300e)\n\t\tcaldata_extract_reverse \"urloader\" 0x1541 0x440\n\t\t;;\n\tbuffalo,wzr-hp-g302h-a1a0|\\\n\tubnt,unifi-ap-outdoor-plus)\n\t\tcaldata_extract \"art\" 0x1000 0xeb8\n\t\t;;\n\tbuffalo,wzr-hp-g450h|\\\n\tubnt,unifi)\n\t\tcaldata_extract \"art\" 0x1000 0x440\n\t\t;;\n\tdlink,dir-825-c1|\\\n\tdlink,dir-835-a1)\n\t\tcaldata_extract \"art\" 0x5000 0x440\n\t\tath9k_patch_mac $(macaddr_add $(mtd_get_mac_text \"mac\" 0x18) 1)\n\t\t;;\n\tenterasys,ws-ap3705i)\n\t\tcaldata_extract \"calibrate\" 0x5000 0x440\n\t\tath9k_patch_mac $(mtd_get_mac_ascii u-boot-env0 RADIOADDR0)\n\t\t;;\n\tmeraki,mr12)\n\t\tcaldata_extract \"art\" 0x11000 0xeb8\n\t\t;;\n\tnetgear,wnr2200-8m|\\\n\tnetgear,wnr2200-16m|\\\n\tpcs,cap324|\\\n\ttplink,tl-wr2543-v1|\\\n\ttplink,tl-wr842n-v1|\\\n\tubnt,airrouter|\\\n\tubnt,bullet-m-ar7240|\\\n\tubnt,bullet-m-ar7241|\\\n\tubnt,nanobridge-m|\\\n\tubnt,nanostation-loco-m|\\\n\tubnt,nanostation-m|\\\n\tubnt,picostation-m|\\\n\tubnt,powerbridge-m|\\\n\tubnt,rocket-m)\n\t\tcaldata_extract \"art\" 0x1000 0x1000\n\t\t;;\n\topenmesh,mr600-v1|\\\n\topenmesh,mr600-v2|\\\n\topenmesh,om5p-an)\n\t\tcaldata_extract \"ART\" 0x5000 0x440\n\t\t;;\n\topenmesh,om2p-v1)\n\t\tcaldata_extract \"ART\" 0x1000 0x440\n\t\t;;\n\twd,mynet-n600|\\\n\twd,mynet-n750)\n\t\tcaldata_extract \"art\" 0x5000 0x440\n\t\tath9k_patch_mac $(mtd_get_mac_ascii devdata \"wlan5mac\")\n\t\t;;\n\twd,mynet-wifi-rangeextender)\n\t\tcaldata_extract \"art\" 0x1000 0x1000\n\t\tath9k_patch_mac $(nvram get wl0_hwaddr)\n\t\t;;\n\t*)\n\t\tcaldata_die \"board $board is not supported yet\"\n\t\t;;\n\tesac\n\t;;\n\"ath9k-eeprom-pci-0000:00:11.0.bin\")\n\tcase $board in\n\tbuffalo,wzr-600dhp|\\\n\tbuffalo,wzr-hp-ag300h|\\\n\tnetgear,wndap360)\n\t\tcaldata_extract \"art\" 0x1000 0xeb8\n\t\t;;\n\tdlink,dir-825-b1)\n\t\tcaldata_extract \"caldata\" 0x1000 0xeb8\n\t\tath9k_patch_mac_crc $(mtd_get_mac_text \"caldata\" 0xffa0) 0x20c\n\t\t;;\n\tmeraki,mr16)\n\t\tcaldata_extract \"art\" 0x11000 0xeb8\n\t\t;;\n\t*)\n\t\tcaldata_die \"board $board is not supported yet\"\n\t\t;;\n\tesac\n\t;;\n\"ath9k-eeprom-pci-0000:00:12.0.bin\")\n\tcase $board in\n\tbuffalo,wzr-600dhp|\\\n\tbuffalo,wzr-hp-ag300h|\\\n\tnetgear,wndap360)\n\t\tcaldata_extract \"art\" 0x5000 0xeb8\n\t\t;;\n\tdlink,dir-825-b1)\n\t\tcaldata_extract \"caldata\" 0x5000 0xeb8\n\t\tath9k_patch_mac_crc $(macaddr_add $(mtd_get_mac_text \"caldata\" 0xffb4) 1) 0x20c\n\t\t;;\n\tmeraki,mr16)\n\t\tcaldata_extract \"art\" 0x15000 0xeb8\n\t\t;;\n\t*)\n\t\tcaldata_die \"board $board is not supported yet\"\n\t\t;;\n\tesac\n\t;;\nesac\n"
  },
  {
    "path": "target/linux/ath79/generic/base-files/etc/hotplug.d/firmware/11-ath10k-caldata",
    "content": "#!/bin/sh\n\n[ -e /lib/firmware/$FIRMWARE ] && exit 0\n\n. /lib/functions/caldata.sh\n. /lib/functions/k2t.sh\n\nboard=$(board_name)\n\ncase \"$FIRMWARE\" in\n\"ath10k/cal-pci-0000:00:00.0.bin\")\n\tcase $board in\n\tallnet,all-wap02860ac|\\\n\taraknis,an-500-ap-i-ac|\\\n\taraknis,an-700-ap-i-ac|\\\n\tengenius,eap1200h|\\\n\tengenius,enstationac-v1|\\\n\tglinet,gl-x750)\n\t\tcaldata_extract \"art\" 0x5000 0x844\n\t\tath10k_patch_mac $(macaddr_add $(mtd_get_mac_binary art 0x0) 2)\n\t\t;;\n\tasus,rp-ac66|\\\n\tcomfast,cf-wr650ac-v1|\\\n\tcomfast,cf-wr650ac-v2|\\\n\tdevolo,dlan-pro-1200plus-ac|\\\n\tdevolo,magic-2-wifi|\\\n\tjoyit,jt-or750i|\\\n\tqxwlan,e1700ac-v2-8m|\\\n\tqxwlan,e1700ac-v2-16m|\\\n\tqxwlan,e600gac-v2-8m|\\\n\tqxwlan,e600gac-v2-16m|\\\n\tsophos,ap55|\\\n\tsophos,ap55c|\\\n\tsophos,ap100|\\\n\tsophos,ap100c|\\\n\tubnt,aircube-ac|\\\n\tubnt,bullet-ac|\\\n\tubnt,unifiac-lite|\\\n\tubnt,unifiac-lr|\\\n\tubnt,unifiac-mesh|\\\n\tubnt,unifiac-mesh-pro|\\\n\tubnt,lap-120|\\\n\tubnt,litebeam-ac-gen2|\\\n\tubnt,nanobeam-ac|\\\n\tubnt,nanobeam-ac-gen2|\\\n\tubnt,nanobeam-ac-xc|\\\n\tubnt,nanostation-ac|\\\n\tubnt,nanostation-ac-loco|\\\n\tubnt,powerbeam-5ac-500|\\\n\tubnt,powerbeam-5ac-gen2|\\\n\tubnt,rocket-5ac-lite|\\\n\tubnt,unifiac-pro|\\\n\tyuncore,a770|\\\n\tyuncore,xd3200)\n\t\tcaldata_extract \"art\" 0x5000 0x844\n\t\t;;\n\tavm,fritz1750e|\\\n\tavm,fritzdvbc)\n\t\tcaldata_extract \"urlader\" 0x198a 0x844\n\t\t;;\n\tdevolo,dvl1200e|\\\n\tdevolo,dvl1200i|\\\n\tdevolo,dvl1750c|\\\n\tdevolo,dvl1750e|\\\n\tdevolo,dvl1750i|\\\n\tdevolo,dvl1750x)\n\t\tcaldata_extract \"art\" 0x5000 0x844\n\t\tath10k_patch_mac $(macaddr_add $(mtd_get_mac_binary art 0x0) -1)\n\t\t;;\n\tdlink,dap-2660-a1|\\\n\tdlink,dap-2695-a1|\\\n\tdlink,dap-3662-a1)\n\t\tcaldata_extract \"art\" 0x5000 0x844\n\t\tath10k_patch_mac $(mtd_get_mac_ascii bdcfg wlanmac_a)\n\t\t;;\n\tdlink,dir-859-a1)\n\t\tcaldata_extract \"art\" 0x5000 0x844\n\t\tath10k_patch_mac $(mtd_get_mac_ascii devdata \"wlan5mac\")\n\t\t;;\n\telecom,wrc-1750ghbk2-i)\n\t\tcaldata_extract \"art\" 0x5000 0x844\n\t\t;;\n\tengenius,ecb1200|\\\n\tengenius,ecb1750)\n\t\tcaldata_extract \"art\" 0x5000 0x844\n\t\tath10k_patch_mac $(mtd_get_mac_ascii u-boot-env athaddr)\n\t\t;;\n\tengenius,epg5000|\\\n\tiodata,wn-ac1167dgr|\\\n\tiodata,wn-ac1600dgr2|\\\n\tsitecom,wlr-7100|\\\n\tzyxel,nbg6616)\n\t\tcaldata_extract \"art\" 0x5000 0x844\n\t\tath10k_patch_mac $(macaddr_add $(mtd_get_mac_ascii u-boot-env ethaddr) 1)\n\t\t;;\n\tengenius,ews511ap)\n\t\tcaldata_extract \"art\" 0x5000 0x844\n\t\tath10k_patch_mac $(macaddr_add $(cat /sys/class/net/eth0/address) 1)\n\t\t;;\n\tglinet,gl-ar750)\n\t\tcaldata_extract \"art\" 0x5000 0x844\n\t\tath10k_patch_mac $(macaddr_add $(mtd_get_mac_binary art 0x0) 1)\n\t\t;;\n\tnec,wg800hp)\n\t\tcaldata_extract \"art\" 0x5000 0x844\n\t\tath10k_patch_mac $(mtd_get_mac_text board_data 0x880)\n\t\t;;\n\tocedo,koala|\\\n\tocedo,ursus)\n\t\tcaldata_extract \"art\" 0x5000 0x844\n\t\tath10k_patch_mac $(mtd_get_mac_binary art 0xc)\n\t\t;;\n\topenmesh,a40|\\\n\topenmesh,a60|\\\n\topenmesh,mr1750-v1|\\\n\topenmesh,mr1750-v2|\\\n\topenmesh,om5p-ac-v2)\n\t\tcaldata_extract \"ART\" 0x5000 0x844\n\t\tath10k_patch_mac $(macaddr_add $(cat /sys/class/net/eth0/address) 16)\n\t\t;;\n\tqihoo,c301)\n\t\tcaldata_extract \"radiocfg\" 0x5000 0x844\n\t\tath10k_patch_mac $(mtd_get_mac_ascii devdata wlan5mac)\n\t\t;;\n\ttplink,archer-a7-v5|\\\n\ttplink,archer-c2-v3|\\\n\ttplink,archer-c7-v4|\\\n\ttplink,archer-c7-v5|\\\n\ttplink,archer-c25-v1|\\\n\ttplink,tl-wr902ac-v1)\n\t\tcaldata_extract \"art\" 0x5000 0x844\n\t\tath10k_patch_mac $(macaddr_add $(mtd_get_mac_binary info 0x8) -1)\n\t\t;;\n\ttplink,archer-c5-v1|\\\n\ttplink,tl-wdr7500-v3)\n\t\tcaldata_extract \"art\" 0x5000 0x844\n\t\tath10k_patch_mac $(macaddr_add $(mtd_get_mac_binary u-boot 0x1fc00) -1)\n\t\t;;\n\ttplink,archer-d50-v1)\n\t\tcaldata_extract \"art\" 0x5000 0x844\n\t\tath10k_patch_mac $(macaddr_add $(mtd_get_mac_binary romfile 0xf100) 2)\n\t\t;;\n\ttplink,archer-d7-v1|\\\n\ttplink,archer-d7b-v1)\n\t\tcaldata_extract \"art\" 0x5000 0x844\n\t\tath10k_patch_mac $(macaddr_add $(mtd_get_mac_binary romfs 0xf100) 2)\n\t\t;;\n\ttplink,eap225-v1|\\\n\ttplink,eap245-v1|\\\n\ttplink,re450-v2|\\\n\ttplink,re450-v3|\\\n\ttplink,re455-v1)\n\t\tcaldata_extract \"art\" 0x5000 0x844\n\t\tath10k_patch_mac $(macaddr_add $(mtd_get_mac_binary info 0x8) 1)\n\t\t;;\n\ttplink,re350k-v1)\n\t\tcaldata_extract \"art\" 0x5000 0x844\n\t\tath10k_patch_mac $(macaddr_add $(mtd_get_mac_binary info 0x8) 2)\n\t\t;;\n\ttplink,re355-v1|\\\n\ttplink,re450-v1)\n\t\tcaldata_extract \"art\" 0x5000 0x844\n\t\tath10k_patch_mac $(macaddr_add $(cat /sys/class/net/eth0/address) -2)\n\t\t;;\n\ttplink,tl-wpa8630-v1)\n\t\tcaldata_extract \"art\" 0x5000 0x844\n\t\tath10k_patch_mac $(macaddr_add $(mtd_get_mac_binary u-boot 0x0fc00) 1)\n\t\t;;\n\tesac\n\t;;\n\"ath10k/cal-pci-0000:01:00.0.bin\")\n\tcase $board in\n\topenmesh,om5p-ac-v1)\n\t\tcaldata_extract \"ART\" 0x5000 0x844\n\t\tath10k_patch_mac $(macaddr_add $(cat /sys/class/net/eth0/address) +16)\n\t\t;;\n\tsitecom,wlr-8100)\n\t\tcaldata_extract \"art\" 0x5000 0x844\n\t\tath10k_patch_mac $(macaddr_add $(mtd_get_mac_ascii u-boot-env ethaddr) 1)\n\t\t;;\n\tesac\n\t;;\n\"ath10k/pre-cal-pci-0000:00:00.0.bin\")\n\tcase $board in\n\tcomfast,cf-e313ac)\n\t\tcaldata_extract \"art\" 0x5000 0x2f20\n\t\tath10k_patch_mac $(mtd_get_mac_binary art 0x6)\n\t\tln -sf /lib/firmware/ath10k/pre-cal-pci-0000\\:00\\:00.0.bin \\\n\t\t\t/lib/firmware/ath10k/QCA9888/hw2.0/board.bin\n\t\trm /lib/firmware/ath10k/QCA9888/hw2.0/board-2.bin\n\t\t;;\n\tcomfast,cf-e375ac|\\\n\tcomfast,cf-e560ac|\\\n\tcomfast,cf-ew72|\\\n\tcomfast,cf-wr752ac-v1)\n\t\tcaldata_extract \"art\" 0x5000 0x2f20\n\t\tath10k_patch_mac $(macaddr_add $(mtd_get_mac_binary art 0x0) 2)\n\t\tln -sf /lib/firmware/ath10k/pre-cal-pci-0000\\:00\\:00.0.bin \\\n\t\t\t/lib/firmware/ath10k/QCA9888/hw2.0/board.bin\n\t\trm /lib/firmware/ath10k/QCA9888/hw2.0/board-2.bin\n\t\t;;\n\tdlink,dap-2680-a1)\n\t\tcaldata_extract \"art\" 0x5000 0x2f20\n\t\tath10k_patch_mac $(mtd_get_mac_ascii bdcfg wlanmac_a)\n\t\tln -sf /lib/firmware/ath10k/pre-cal-pci-0000\\:00\\:00.0.bin \\\n\t\t\t/lib/firmware/ath10k/QCA9888/hw2.0/board.bin\n\t\t;;\n\tdlink,dir-842-c1|\\\n\tdlink,dir-842-c2|\\\n\tdlink,dir-842-c3)\n\t\tcaldata_extract \"art\" 0x5000 0x2f20\n\t\tcaldata_valid \"202f\" || caldata_extract \"reserved\" 0x15000 0x2f20\n\t\tath10k_patch_mac $(mtd_get_mac_ascii devdata wlan5mac)\n\t\tln -sf /lib/firmware/ath10k/pre-cal-pci-0000\\:00\\:00.0.bin \\\n\t\t\t/lib/firmware/ath10k/QCA9888/hw2.0/board.bin\n\t\t;;\n\tnec,wf1200cr|\\\n\tnec,wg1200cr)\n\t\tcaldata_extract \"art\" 0x5000 0x2f20\n\t\tath10k_patch_mac $(mtd_get_mac_ascii devdata wlan5mac)\n\t\tln -sf /lib/firmware/ath10k/pre-cal-pci-0000\\:00\\:00.0.bin \\\n\t\t\t/lib/firmware/ath10k/QCA9888/hw2.0/board.bin\n\t\t;;\n\tnetgear,ex6400|\\\n\tnetgear,ex7300)\n\t\tcaldata_extract \"caldata\" 0x5000 0x2f20\n\t\tath10k_patch_mac $(mtd_get_mac_binary caldata 0xc)\n\t\t;;\n\tphicomm,k2t)\n\t\tcaldata_extract \"art\" 0x5000 0x2f20\n\t\tath10k_patch_mac $(k2t_get_mac \"5g_mac\")\n\t\tln -sf /lib/firmware/ath10k/pre-cal-pci-0000\\:00\\:00.0.bin \\\n\t\t\t/lib/firmware/ath10k/QCA9888/hw2.0/board.bin\n\t\t;;\n\ttplink,archer-c58-v1|\\\n\ttplink,archer-c59-v1|\\\n\ttplink,archer-c59-v2|\\\n\ttplink,archer-c60-v1|\\\n\ttplink,archer-c60-v2|\\\n\ttplink,archer-c60-v3|\\\n\ttplink,archer-c6-v2|\\\n\ttplink,archer-c6-v2-us|\\\n\ttplink,tl-wa1201-v2)\n\t\tcaldata_extract \"art\" 0x5000 0x2f20\n\t\tath10k_patch_mac $(macaddr_add $(mtd_get_mac_binary info 0x8) -1)\n\t\tln -sf /lib/firmware/ath10k/pre-cal-pci-0000\\:00\\:00.0.bin \\\n\t\t\t/lib/firmware/ath10k/QCA9888/hw2.0/board.bin\n\t\t;;\n\ttplink,cpe710-v1)\n\t\tcaldata_extract \"art\" 0x5000 0x2f20\n\t\tath10k_patch_mac $(mtd_get_mac_binary info 0x8)\n\t\tln -sf /lib/firmware/ath10k/pre-cal-pci-0000\\:00\\:00.0.bin \\\n\t\t\t/lib/firmware/ath10k/QCA9888/hw2.0/board.bin\n\t\t;;\n\ttplink,eap225-outdoor-v1|\\\n\ttplink,eap225-v3|\\\n\ttplink,eap225-wall-v2)\n\t\tcaldata_extract \"art\" 0x5000 0x2f20\n\t\tath10k_patch_mac $(macaddr_add $(mtd_get_mac_binary info 0x8) 1)\n\t\tln -sf /lib/firmware/ath10k/pre-cal-pci-0000\\:00\\:00.0.bin \\\n\t\t\t/lib/firmware/ath10k/QCA9888/hw2.0/board.bin\n\t\t;;\n\ttplink,eap245-v3)\n\t\tcaldata_extract \"art\" 0x5000 0x2f20\n\t\tath10k_patch_mac $(macaddr_add $(mtd_get_mac_binary info 0x8) 1)\n\t\t;;\n\txiaomi,aiot-ac2350)\n\t\tcaldata_extract \"art\" 0x5000 0x2f20\n\t\tln -sf /lib/firmware/ath10k/pre-cal-pci-0000\\:00\\:00.0.bin \\\n\t\t\t/lib/firmware/ath10k/QCA9984/hw1.0/board.bin\n\t\t;;\n\ttplink,deco-m4r-v1)\n\t\tcaldata_extract \"art\" 0x5000 0x2f20\n\t\tath10k_patch_mac $(macaddr_add $(mtd_get_mac_binary config 0x8) -1)\n\t\tln -sf /lib/firmware/ath10k/pre-cal-pci-0000\\:00\\:00.0.bin \\\n\t\t\t/lib/firmware/ath10k/QCA9888/hw2.0/board.bin\n\t\t;;\n\tyuncore,a782|\\\n\tyuncore,xd4200)\n\t\tcaldata_extract \"art\" 0x5000 0x2f20\n\t\tln -sf /lib/firmware/ath10k/pre-cal-pci-0000\\:00\\:00.0.bin \\\n\t\t\t/lib/firmware/ath10k/QCA9888/hw2.0/board.bin\n\t\t;;\n\tesac\n\t;;\n*)\n\texit 1\n\t;;\nesac\n"
  },
  {
    "path": "target/linux/ath79/generic/base-files/etc/hotplug.d/ieee80211/10_fix_wifi_mac",
    "content": "#!/bin/ash\n\n[ \"$ACTION\" = \"add\" ] || exit 0\n\nPHYNBR=${DEVPATH##*/phy}\n\n[ -n $PHYNBR ] || exit 0\n\n. /lib/functions.sh\n. /lib/functions/system.sh\n. /lib/functions/k2t.sh\n\nboard=$(board_name)\n\ncase \"$board\" in\n\tadtran,bsap1800-v2|\\\n\tadtran,bsap1840)\n\t\tmacaddr_add \"$(mtd_get_mac_binary 'Board data' 2)\" $(($PHYNBR * 8 + 1)) > /sys${DEVPATH}/macaddress\n\t\t;;\n\tdlink,dap-1330-a1|\\\n\tdlink,dap-1365-a1|\\\n\tdlink,dch-g020-a1)\n\t\tmtd_get_mac_text \"mp\" 0x13 > /sys${DEVPATH}/macaddress\n\t\t;;\n\tdlink,dap-2230-a1|\\\n\tdlink,dap-3320-a1)\n\t\tmtd_get_mac_ascii bdcfg \"wlanmac\" > /sys${DEVPATH}/macaddress\n\t\t;;\n\tdlink,dap-2660-a1|\\\n\tdlink,dap-2680-a1|\\\n\tdlink,dap-2695-a1|\\\n\tdlink,dap-3662-a1)\n\t\t[ \"$PHYNBR\" -eq 1 ] && \\\n\t\t\tmtd_get_mac_ascii bdcfg \"wlanmac\" > /sys${DEVPATH}/macaddress\n\t\t;;\n\tiodata,wn-ac1600dgr)\n\t\t# There is no eeprom data for 5 GHz wlan in \"art\" partition\n\t\t# which would allow to patch the macaddress\n\t\t[ \"$PHYNBR\" -eq 0 ] && \\\n\t\t\tmacaddr_add \"$(mtd_get_mac_ascii u-boot-env ethaddr)\" 1 > /sys${DEVPATH}/macaddress\n\t\t;;\n\tiodata,wn-ag300dgr)\n\t\t# There is no eeprom data for 5 GHz wlan in \"art\" partition\n\t\t# which would allow to patch the macaddress\n\t\t[ \"$PHYNBR\" -eq 1 ] && \\\n\t\t\tmacaddr_add \"$(mtd_get_mac_ascii u-boot-env ethaddr)\" 1 > /sys${DEVPATH}/macaddress\n\t\t;;\n\tphicomm,k2t)\n\t\t# The K2T factory firmware does use LAN mac address as the 2.4G wifi mac address\n\t\t[ \"$PHYNBR\" -eq 1 ] && \\\n\t\t\tk2t_get_mac \"lan_mac\" > /sys${DEVPATH}/macaddress\n\t\t;;\n\tsiemens,ws-ap3610)\n\t\tmtd_get_mac_ascii cfg1 RADIOADDR${PHYNBR} > /sys${DEVPATH}/macaddress\n\t\t;;\n\ttrendnet,tew-823dru)\n\t\t# set the 2.4G interface mac address to LAN MAC\n\t\t[ \"$PHYNBR\" -eq 1 ] && \\\n\t\t\tmtd_get_mac_text mac 4 > /sys${DEVPATH}/macaddress\n\t\t# set the 5G interface mac address to WAN MAC + 1\n\t\t[ \"$PHYNBR\" -eq 0 ] && \\\n\t\t\tmacaddr_add \"$(mtd_get_mac_text mac 0x18)\" 1 > /sys${DEVPATH}/macaddress\n\t\t;;\n\tzyxel,nbg6616)\n\t\t# Set mac address for 2.4g device\n\t\t[ \"$PHYNBR\" -eq 1 ] && \\\n\t\t\tmtd_get_mac_ascii u-boot-env ethaddr > /sys${DEVPATH}/macaddress\n\t\t;;\nesac\n"
  },
  {
    "path": "target/linux/ath79/generic/base-files/etc/init.d/bootcount",
    "content": "#!/bin/sh /etc/rc.common\n\nSTART=99\n\nboot() {\n\tcase $(board_name) in\n\tadtran,bsap1800-v2|\\\n\tadtran,bsap1840)\n\t\tfconfig -s -w -d $(find_mtd_part \"RedBoot config\") -n boot_cntb -x 0\n\t\t;;\n\tqihoo,c301)\n\t\tlocal n=$(fw_printenv activeregion | cut -d = -f 2)\n\t\tfw_setenv \"image${n}trynum\" 0\n\t\t;;\n\tesac\n}\n"
  },
  {
    "path": "target/linux/ath79/generic/base-files/etc/uci-defaults/04_led_migration",
    "content": ". /lib/functions.sh\n. /lib/functions/migrations.sh\n\nboard=$(board_name)\n\ncase \"$board\" in\ndlink,dap-1330-a1)\n\tmigrate_leds \"red:power=red:status\" \\\n\t\t\"red:wifi=red:rssilow\" \\\n\t\t\"green:wifi=green:rssimediumlow\" \\\n\t\t\"green:signal1=green:rssimediumhigh\" \\\n\t\t\"green:signal2=green:rssihigh\"\n\t;;\nengenius,epg5000)\n\tmigrate_leds \":wlan-2g=:wlan2g\" \":wlan-5g=:wlan5g\"\n\t;;\nglinet,gl-mifi)\n\tmigrate_leds \":net=:3g4g\"\n\t;;\nmeraki,mr12)\n\tmigrate_leds \":wifi=:link\" \":wan=:lan\"\n\t;;\nopenmesh,mr600-v1)\n\tmigrate_leds \":wlan58=:wifi5g\"\n\t;;\nopenmesh,mr600-v2)\n\tmigrate_leds \":wlan24=:wifi2g\" \":wlan58=:wifi5g\"\n\t;;\nopenmesh,mr900-v1|\\\nopenmesh,mr900-v2|\\\nopenmesh,mr1750-v1|\\\nopenmesh,mr1750-v2)\n\tmigrate_leds \":wlan24=:wifi2g\" \":wlan58=:wifi5g\" \":wan=:lan\"\n\t;;\npcs,cap324)\n\tmigrate_leds \"lan:amber=amber:lan\" \"lan:green=green:lan\"\n\t;;\nqxwlan,e558-v2-16m|\\\nqxwlan,e558-v2-8m)\n\tmigrate_leds \":qss=:sig2\"\n\t;;\nqxwlan,e600g-v2-16m|\\\nqxwlan,e600g-v2-8m)\n\tmigrate_leds \"blue:wan=blue:wlan\"\n\t;;\nqxwlan,e600gac-v2-16m|\\\nqxwlan,e600gac-v2-8m)\n\tmigrate_leds \"orange:wan=orange:wlan2g\" \"green:system=blue:system\"\n\t;;\nqxwlan,e750a-v4-16m|\\\nqxwlan,e750a-v4-8m|\\\nqxwlan,e750g-v8-16m|\\\nqxwlan,e750g-v8-8m)\n\tmigrate_leds \":ds10=:sig1\" \":ds20=:sig2\"\n\t;;\nmercury,mw4530r-v1|\\\ntplink,archer-c7-v2|\\\ntplink,tl-wdr3600-v1|\\\ntplink,tl-wdr4300-v1|\\\ntplink,tl-wdr4300-v1-il|\\\ntplink,tl-wdr4310-v1)\n\tmigrate_leds \"blue:=green:\"\n\t;;\ntplink,tl-wpa8630-v1)\n\tmigrate_leds ':wlan$=:wifi2g' ':wlan5$=:wifi5g'\n\t;;\nesac\n\nremove_devicename_leds\n\nmigrations_apply system\n\nexit 0\n"
  },
  {
    "path": "target/linux/ath79/generic/base-files/etc/uci-defaults/05_fix-compat-version",
    "content": ". /lib/functions.sh\n\ncase \"$(board_name)\" in\n\tmeraki,mr12|\\\n\tmeraki,mr16)\n\t\tuci set system.@system[0].compat_version=\"2.0\"\n\t\tuci commit system\n\t\t;;\nesac\n\nexit 0\n"
  },
  {
    "path": "target/linux/ath79/generic/base-files/etc/uci-defaults/09_fix-checksum",
    "content": ". /lib/functions.sh\n\nfix_seama_header() {\n\tlocal kernel_size=$(sed -n 's/mtd[0-9]*: \\([0-9a-f]*\\).*\"kernel\".*/\\1/p' /proc/mtd)\n\t[ \"$kernel_size\" ] && mtd -c 0x$kernel_size fixseama firmware\n}\n\nfixwrgg() {\n\tlocal kernel_size=$(sed -n 's/mtd[0-9]*: \\([0-9a-f]*\\).*\"kernel\".*/\\1/p' /proc/mtd)\n\t[ \"$kernel_size\" ] && mtd -c 0x$kernel_size fixwrgg firmware\n}\n\nboard=$(board_name)\n\ncase \"$board\" in\ndlink,dap-2230-a1|\\\ndlink,dap-2660-a1|\\\ndlink,dap-2680-a1|\\\ndlink,dap-2695-a1|\\\ndlink,dap-3320-a1|\\\ndlink,dap-3662-a1)\n\tfixwrgg\n\t;;\nqihoo,c301)\n\tfix_seama_header\n\t;;\nesac\n"
  },
  {
    "path": "target/linux/ath79/generic/base-files/lib/functions/k2t.sh",
    "content": "#\n# Copyright (C) 2018 Weijie Gao <hackpascal@gmail.com>\n#\n# Helper function to extract mac addresses from mtd part for Phicomm K2T\n#\n\n. /lib/functions.sh\n. /lib/functions/system.sh\n. /usr/share/libubox/jshn.sh\n\nk2t_config_load() {\n\tlocal mtd_blk=$(find_mtd_part config)\n\n\tif [ -z \"$mtd_blk\" ]; then\n\t\techo \"k2t_config_load: no mtd part named config\" >&2\n\t\texit 1\n\tfi\n\n\tlocal json_size=$(dd if=$mtd_blk bs=1 count=8 2>/dev/null)\n\n\tjson_size=\"0x$json_size\"\n\tjson_size=$((json_size))\n\n\tif [ \"$?\" -ne 0 ]; then\n\t\techo \"k2t_config_load: invalid json data size\" >&2\n\t\texit 2\n\tfi\n\n\tif [ \"$json_size\" -eq 0 ]; then\n\t\techo \"k2t_config_load: empty json data\" >&2\n\t\texit 3\n\tfi\n\n\tlocal json_data=$(dd if=$mtd_blk bs=1 skip=8 count=$json_size 2>/dev/null)\n\n\tjson_load \"$json_data\"\n}\n\nk2t_get_mac() {\n\tlocal old_ns\n\n\tjson_set_namespace \"k2t\" old_ns\n\n\tif k2t_config_load; then\n\t\tjson_select \"this_dev_info\"\n\t\tjson_get_var val \"$1\"\n\t\tjson_select ..\n\tfi\n\n\tjson_set_namespace old_ns\n\n\techo $val\n}\n\n"
  },
  {
    "path": "target/linux/ath79/generic/base-files/lib/preinit/10_fix_eth_mac.sh",
    "content": ". /lib/functions.sh\n\npreinit_set_mac_address() {\n\tcase $(board_name) in\n\tavm,fritz1750e|\\\n\tavm,fritz450e|\\\n\tavm,fritzdvbc)\n\t\tip link set dev eth0 address $(fritz_tffs -n maca -i $(find_mtd_part \"tffs (1)\"))\n\t\t;;\n\tdlink,dap-2695-a1|\\\n\tdlink,dap-3662-a1)\n\t\tip link set dev eth0 address $(mtd_get_mac_ascii bdcfg \"lanmac\")\n\t\tip link set dev eth1 address $(mtd_get_mac_ascii bdcfg \"wanmac\")\n\t\t;;\n\tenterasys,ws-ap3705i)\n\t\tip link set dev eth0 address $(mtd_get_mac_ascii u-boot-env0 ethaddr)\n\t\t;;\n\tsiemens,ws-ap3610)\n\t\tip link set dev eth0 address $(mtd_get_mac_ascii cfg1 ethaddr)\n\t\t;;\n\tzyxel,nbg6616)\n\t\tethaddr=$(mtd_get_mac_ascii u-boot-env ethaddr)\n\t\tip link set dev eth0 address $(macaddr_add $ethaddr 2)\n\t\tip link set dev eth1 address $(macaddr_add $ethaddr 3)\n\t\t;;\n\tesac\n}\n\nboot_hook_add preinit_main preinit_set_mac_address\n"
  },
  {
    "path": "target/linux/ath79/generic/base-files/lib/upgrade/dualboot_datachk.sh",
    "content": "# The U-Boot loader with the datachk patchset for dualbooting requires image\n# sizes and checksums to be provided in the U-Boot environment.\n# The devices come with 2 main partitions - while one is active\n# sysupgrade will flash the other. The boot order is changed to boot the\n# newly flashed partition. If the new partition can't be booted due to\n# upgrade failures the previously used partition is loaded.\n\nplatform_do_upgrade_dualboot_datachk() {\n\tlocal tar_file=\"$1\"\n\tlocal restore_backup\n\tlocal primary_kernel_mtd\n\n\tlocal setenv_script=\"/tmp/fw_env_upgrade\"\n\n\tlocal inactive_mtd=\"$(find_mtd_index $PART_NAME)\"\n\tlocal inactive_offset=\"$(cat /sys/class/mtd/mtd${inactive_mtd}/offset)\"\n\tlocal total_size=\"$(cat /sys/class/mtd/mtd${inactive_mtd}/size)\"\n\tlocal flash_start_mem=0x9f000000\n\n\t# detect to which flash region the new image is written to.\n\t#\n\t# 1. check what is the mtd index for the first flash region on this\n\t#    device\n\t# 2. check if the target partition (\"inactive\") has the mtd index of\n\t#    the first flash region\n\t#\n\t#    - when it is: the new bootseq will be 1,2 and the first region is\n\t#      modified\n\t#    - when it isnt: bootseq will be 2,1 and the second region is\n\t#      modified\n\t#\n\t# The detection has to be done via the hardcoded mtd partition because\n\t# the current boot might be done with the fallback region. Let us\n\t# assume that the current bootseq is 1,2. The bootloader detected that\n\t# the image in flash region 1 is corrupt and thus switches to flash\n\t# region 2. The bootseq in the u-boot-env is now still the same and\n\t# the sysupgrade code can now only rely on the actual mtd indexes and\n\t# not the bootseq variable to detect the currently booted flash\n\t# region/image.\n\t#\n\t# In the above example, an implementation which uses bootseq (\"1,2\") to\n\t# detect the currently booted image would assume that region 1 is booted\n\t# and then overwrite the variables for the wrong flash region (aka the\n\t# one which isn't modified). This could result in a device which doesn't\n\t# boot anymore to Linux until it was reflashed with ap51-flash.\n\tlocal next_boot_part=\"1\"\n\tcase \"$(board_name)\" in\n\tplasmacloud,pa300|\\\n\tplasmacloud,pa300e)\n\t\tprimary_kernel_mtd=3\n\t\t;;\n\t*)\n\t\techo \"failed to detect primary kernel mtd partition for board\"\n\t\treturn 1\n\t\t;;\n\tesac\n\t[ \"$inactive_mtd\" = \"$primary_kernel_mtd\" ] || next_boot_part=\"2\"\n\n\tlocal board_dir=$(tar tf $tar_file | grep -m 1 '^sysupgrade-.*/$')\n\tboard_dir=${board_dir%/}\n\n\tlocal kernel_length=$(tar xf $tar_file ${board_dir}/kernel -O | wc -c)\n\tlocal rootfs_length=$(tar xf $tar_file ${board_dir}/root -O | wc -c)\n\t# rootfs without EOF marker\n\trootfs_length=$((rootfs_length-4))\n\n\tlocal kernel_md5=$(tar xf $tar_file ${board_dir}/kernel -O | md5sum); kernel_md5=\"${kernel_md5%% *}\"\n\t# md5 checksum of rootfs with EOF marker\n\tlocal rootfs_md5=$(tar xf $tar_file ${board_dir}/root -O | dd bs=1 count=$rootfs_length | md5sum); rootfs_md5=\"${rootfs_md5%% *}\"\n\n\t#\n\t# add tar support to get_image() to use default_do_upgrade() instead?\n\t#\n\n\t# take care of restoring a saved config\n\t[ -n \"$UPGRADE_BACKUP\" ] && restore_backup=\"${MTD_CONFIG_ARGS} -j ${UPGRADE_BACKUP}\"\n\n\tmtd -q erase inactive\n\ttar xf $tar_file ${board_dir}/root -O | mtd -n -p $kernel_length $restore_backup write - $PART_NAME\n\ttar xf $tar_file ${board_dir}/kernel -O | mtd -n write - $PART_NAME\n\n\t# prepare new u-boot env\n\tif [ \"$next_boot_part\" = \"1\" ]; then\n\t\techo \"bootseq 1,2\" > $setenv_script\n\telse\n\t\techo \"bootseq 2,1\" > $setenv_script\n\tfi\n\n\tprintf \"kernel_size_%i %i\\n\" $next_boot_part $((kernel_length / 1024)) >> $setenv_script\n\tprintf \"vmlinux_start_addr 0x%08x\\n\" $((flash_start_mem + inactive_offset)) >> $setenv_script\n\tprintf \"vmlinux_size 0x%08x\\n\" ${kernel_length} >> $setenv_script\n\tprintf \"vmlinux_checksum %s\\n\" ${kernel_md5} >> $setenv_script\n\n\tprintf \"rootfs_size_%i %i\\n\" $next_boot_part $(((total_size-kernel_length) / 1024)) >> $setenv_script\n\tprintf \"rootfs_start_addr 0x%08x\\n\" $((flash_start_mem+inactive_offset+kernel_length)) >> $setenv_script\n\tprintf \"rootfs_size 0x%08x\\n\" ${rootfs_length} >> $setenv_script\n\tprintf \"rootfs_checksum %s\\n\" ${rootfs_md5} >> $setenv_script\n\n\t# store u-boot env changes\n\tmkdir -p /var/lock\n\tfw_setenv -s $setenv_script || {\n\t\techo \"failed to update U-Boot environment\"\n\t\treturn 1\n\t}\n}\n"
  },
  {
    "path": "target/linux/ath79/generic/base-files/lib/upgrade/failsafe_datachk.sh",
    "content": "# U-Boot with the datachk patchset requires image sizes, offsets,\n# and checksums to be provided in the U-Boot environment.\n# This script is based on the dualboot version for devices that come with 2 OS partitions.\n# For Senao boards with a \"failsafe\" partition image, the process is almost the same.\n# Instead of booting a secondary instalation on checksum failure,\n# the failsafe image is booted instead.\n# These boards also use the OKLI lzma kernel loader and mtd-concat\n# So the kernel check is for the loader, the rootfs check is for kernel + rootfs\n\nplatform_do_upgrade_failsafe_datachk() {\n\tlocal setenv_script=\"/tmp/fw_env_upgrade\"\n\n\tlocal flash_base=0x9f000000\n\n\tlocal kernel_mtd=$(find_mtd_index ${KERNEL_PART:-kernel})\n\tlocal rootfs_mtd=$(find_mtd_index ${ROOTFS_PART:-rootfs})\n\n\tlocal kernel_offset=$(cat /sys/class/mtd/mtd${kernel_mtd}/offset)\n\tlocal rootfs_offset=$(cat /sys/class/mtd/mtd${rootfs_mtd}/offset)\n\n\tif [ -n \"$IMAGE_LIST\" ]; then\n\t\tKERNEL_FILE=$($IMAGE_LIST | grep $KERNEL_FILE)\n\t\tROOTFS_FILE=$($IMAGE_LIST | grep $ROOTFS_FILE)\n\tfi\n\n\tlocal kernel_size=$($IMAGE_CMD $KERNEL_FILE | wc -c)\n\tlocal rootfs_size=$($IMAGE_CMD $ROOTFS_FILE | wc -c)\n\n\t# rootfs without JFFS2\n\tlocal rootfs_blocks=$((rootfs_size / 4096))\n\trootfs_size=$((rootfs_blocks * 4096))\n\n\tlocal kernel_md5=$($IMAGE_CMD $KERNEL_FILE | md5sum | cut -d ' ' -f1)\n\tlocal rootfs_md5=$($IMAGE_CMD $ROOTFS_FILE | dd bs=4k count=$rootfs_blocks iflag=fullblock | md5sum | cut -d ' ' -f1)\n\n\t# prepare new u-boot-env vars\n\tprintf \"vmlinux_start_addr 0x%08x\\n\" $((flash_base + kernel_offset)) >> $setenv_script\n\tprintf \"vmlinux_size 0x%08x\\n\" ${kernel_size} >> $setenv_script\n\tprintf \"vmlinux_checksum %s\\n\" ${kernel_md5} >> $setenv_script\n\n\tprintf \"rootfs_start_addr 0x%08x\\n\" $((flash_base + rootfs_offset)) >> $setenv_script\n\tprintf \"rootfs_size 0x%08x\\n\" ${rootfs_size} >> $setenv_script\n\tprintf \"rootfs_checksum %s\\n\" ${rootfs_md5} >> $setenv_script\n\n\t# store u-boot-env\n\tmkdir -p /var/lock\n\tfw_setenv -s $setenv_script || {\n\t\techo 'failed to update U-Boot environment'\n\t\texit 1\n\t}\n\n\t# sysupgrade\n\tsleep 2\n\tsync\n\techo 3 > /proc/sys/vm/drop_caches\n\t$IMAGE_CMD $KERNEL_FILE | mtd $MTD_ARGS write - ${KERNEL_PART:-kernel}\n\tsleep 2\n\tsync\n\tif [ -n \"$UPGRADE_BACKUP\" ]; then\n\t\t$IMAGE_CMD $ROOTFS_FILE | mtd $MTD_ARGS $MTD_CONFIG_ARGS -j $UPGRADE_BACKUP write - ${ROOTFS_PART:-rootfs}\n\telse\n\t\t$IMAGE_CMD $ROOTFS_FILE | mtd $MTD_ARGS write - ${ROOTFS_PART:-rootfs}\n\tfi\n}\n"
  },
  {
    "path": "target/linux/ath79/generic/base-files/lib/upgrade/openmesh.sh",
    "content": "# The U-Boot loader of the OpenMesh devices requires image sizes and\n# checksums to be provided in the U-Boot environment.\n# The OpenMesh devices come with 2 main partitions - while one is active\n# sysupgrade will flash the other. The boot order is changed to boot the\n# newly flashed partition. If the new partition can't be booted due to\n# upgrade failures the previously used partition is loaded.\n\ncfg_value_get()\n{\n\tlocal cfg=$1 cfg_opt\n\tlocal section=$2 our_section=0\n\tlocal param=$3 our_param=\n\n\tfor cfg_opt in $cfg; do\n\t\t[ \"$cfg_opt\" = \"[$section]\" ] && our_section=1 && continue\n\t\t[ \"$our_section\" = \"1\" ] || continue\n\n\t\tour_param=${cfg_opt%%=*}\n\t\t[ \"$param\" = \"$our_param\" ] && echo ${cfg_opt##*=} && break\n\tdone\n}\n\nplatform_do_upgrade_openmesh()\n{\n\tlocal img_path=\"$1\"\n\tlocal restore_backup\n\n\tlocal setenv_script=\"/tmp/fw_env_upgrade\"\n\n\tlocal inactive_mtd=\"$(find_mtd_index $PART_NAME)\"\n\tlocal inactive_offset=\"$(cat /sys/class/mtd/mtd${inactive_mtd}/offset)\"\n\tlocal total_size=\"$(cat /sys/class/mtd/mtd${inactive_mtd}/size)\"\n\tlocal total_kbs=$((total_size / 1024))\n\tlocal flash_start_mem=0x9f000000\n\tlocal data_offset=$((64 * 1024))\n\n\t# detect to which flash region the new image is written to.\n\t#\n\t# 1. check what is the mtd index for the first flash region on this\n\t#    device\n\t# 2. check if the target partition (\"inactive\") has the mtd index of\n\t#    the first flash region\n\t#\n\t#    - when it is: the new bootseq will be 1,2 and the first region is\n\t#      modified\n\t#    - when it isn't: bootseq will be 2,1 and the second region is\n\t#      modified\n\t#\n\t# The detection has to be done via the hardcoded mtd partition because\n\t# the current boot might be done with the fallback region. Let us\n\t# assume that the current bootseq is 1,2. The bootloader detected that\n\t# the image in flash region 1 is corrupt and thus switches to flash\n\t# region 2. The bootseq in the u-boot-env is now still the same and\n\t# the sysupgrade code can now only rely on the actual mtd indexes and\n\t# not the bootseq variable to detect the currently booted flash\n\t# region/image.\n\t#\n\t# In the above example, an implementation which uses bootseq (\"1,2\") to\n\t# detect the currently booted image would assume that region 1 is booted\n\t# and then overwrite the variables for the wrong flash region (aka the\n\t# one which isn't modified). This could result in a device which doesn't\n\t# boot anymore to Linux until it was reflashed with ap51-flash.\n\tlocal next_boot_part=\"1\"\n\tlocal primary_kernel_mtd=\"3\"\n\t[ \"$inactive_mtd\" = \"$primary_kernel_mtd\" ] || next_boot_part=\"2\"\n\n\tlocal cfg_size=$(dd if=\"$img_path\" bs=8 skip=70 count=1 iflag=skip_bytes 2>/dev/null)\n\tlocal cfg_length=$((0x$cfg_size))\n\tlocal cfg_content=$(dd if=\"$img_path\" bs=$cfg_length skip=$data_offset count=1 iflag=skip_bytes 2>/dev/null)\n\n\tlocal kernel_size=$(dd if=\"$img_path\" bs=8 skip=142 count=1 iflag=skip_bytes 2>/dev/null)\n\tlocal kernel_length=$((0x$kernel_size))\n\tlocal kernel_kbs=$((kernel_length / 1024))\n\tlocal kernel_md5=$(cfg_value_get \"$cfg_content\" \"vmlinux\" \"md5sum\")\n\n\tlocal rootfs_size=$(dd if=\"$img_path\" bs=8 skip=214 count=1 iflag=skip_bytes 2>/dev/null)\n\tlocal rootfs_length=$((0x$rootfs_size))\n\tlocal rootfs_md5=$(cfg_value_get \"$cfg_content\" \"rootfs\" \"md5sum\")\n\tlocal rootfs_checksize=$(cfg_value_get \"$cfg_content\" \"rootfs\" \"checksize\")\n\n\t# take care of restoring a saved config\n\t[ -n \"$UPGRADE_BACKUP\" ] && restore_backup=\"${MTD_CONFIG_ARGS} -j ${UPGRADE_BACKUP}\"\n\n\t# write image parts\n\tmtd -q erase inactive\n\tdd if=\"$img_path\" bs=1 skip=$((data_offset + cfg_length + kernel_length)) count=$rootfs_length 2>&- | \\\n\t\tmtd -n -p $kernel_length $restore_backup write - $PART_NAME\n\tdd if=\"$img_path\" bs=1024 skip=$((data_offset + cfg_length)) count=$kernel_kbs iflag=skip_bytes 2>&- | \\\n\t\tmtd -n write - $PART_NAME\n\n\t# prepare new u-boot env\n\tif [ \"$next_boot_part\" = \"1\" ]; then\n\t\techo \"bootseq 1,2\" > $setenv_script\n\telse\n\t\techo \"bootseq 2,1\" > $setenv_script\n\tfi\n\n\tprintf \"kernel_size_%i %i\\n\" $next_boot_part $kernel_kbs >> $setenv_script\n\tprintf \"vmlinux_start_addr 0x%08x\\n\" $((flash_start_mem + inactive_offset)) >> $setenv_script\n\tprintf \"vmlinux_size 0x%08x\\n\" ${kernel_length} >> $setenv_script\n\tprintf \"vmlinux_checksum %s\\n\" ${kernel_md5} >> $setenv_script\n\n\tprintf \"rootfs_size_%i %i\\n\" $next_boot_part $((total_kbs - kernel_kbs)) >> $setenv_script\n\tprintf \"rootfs_start_addr 0x%08x\\n\" $((flash_start_mem+inactive_offset+kernel_length)) >> $setenv_script\n\tprintf \"rootfs_size %s\\n\" $rootfs_checksize >> $setenv_script\n\tprintf \"rootfs_checksum %s\\n\" ${rootfs_md5} >> $setenv_script\n\n\t# store u-boot env changes\n\tmkdir -p /var/lock\n\tfw_setenv -s $setenv_script || {\n\t\techo \"failed to update U-Boot environment\"\n\t\treturn 1\n\t}\n}\n"
  },
  {
    "path": "target/linux/ath79/generic/base-files/lib/upgrade/platform.sh",
    "content": "#\n# Copyright (C) 2011 OpenWrt.org\n#\n\nPART_NAME=firmware\nREQUIRE_IMAGE_METADATA=1\n\nRAMFS_COPY_BIN='fw_printenv fw_setenv'\nRAMFS_COPY_DATA='/etc/fw_env.config /var/lock/fw_printenv.lock'\n\nredboot_fis_do_upgrade() {\n\tlocal append\n\tlocal sysup_file=\"$1\"\n\tlocal kern_part=\"$2\"\n\tlocal magic=$(get_magic_word \"$sysup_file\")\n\n\tif [ \"$magic\" = \"4349\" ]; then\n\t\tlocal kern_length=0x$(dd if=\"$sysup_file\" bs=2 skip=1 count=4 2>/dev/null)\n\n\t\t[ -f \"$UPGRADE_BACKUP\" ] && append=\"-j $UPGRADE_BACKUP\"\n\t\tdd if=\"$sysup_file\" bs=64k skip=1 2>/dev/null | \\\n\t\t\tmtd -r $append -F$kern_part:$kern_length:0x80060000,rootfs write - $kern_part:rootfs\n\n\telif [ \"$magic\" = \"7379\" ]; then\n\t\tlocal board_dir=$(tar tf $sysup_file | grep -m 1 '^sysupgrade-.*/$')\n\t\tlocal kern_length=$(tar xf $sysup_file ${board_dir}kernel -O | wc -c)\n\n\t\t[ -f \"$UPGRADE_BACKUP\" ] && append=\"-j $UPGRADE_BACKUP\"\n\t\ttar xf $sysup_file ${board_dir}kernel ${board_dir}root -O | \\\n\t\t\tmtd -r $append -F$kern_part:$kern_length:0x80060000,rootfs write - $kern_part:rootfs\n\n\telse\n\t\techo \"Unknown image, aborting!\"\n\t\treturn 1\n\tfi\n}\n\nplatform_check_image() {\n\treturn 0\n}\n\nplatform_do_upgrade() {\n\tlocal board=$(board_name)\n\n\tcase \"$board\" in\n\tadtran,bsap1800-v2|\\\n\tadtran,bsap1840)\n\t\tredboot_fis_do_upgrade \"$1\" vmlinux_2\n\t\t;;\n\tallnet,all-wap02860ac|\\\n\taraknis,an-300-ap-i-n|\\\n\taraknis,an-500-ap-i-ac|\\\n\taraknis,an-700-ap-i-ac|\\\n\tengenius,eap1200h|\\\n\tengenius,eap300-v2|\\\n\tengenius,eap600|\\\n\tengenius,ecb600|\\\n\tengenius,ens202ext-v1|\\\n\tengenius,enstationac-v1)\n\t\tIMAGE_LIST=\"tar tzf $1\"\n\t\tIMAGE_CMD=\"tar xzOf $1\"\n\t\tKERNEL_PART=\"loader\"\n\t\tROOTFS_PART=\"fwconcat0\"\n\t\tKERNEL_FILE=\"uImage-lzma.bin\"\n\t\tROOTFS_FILE=\"root.squashfs\"\n\t\tplatform_do_upgrade_failsafe_datachk \"$1\"\n\t\t;;\n\tjjplus,ja76pf2)\n\t\tredboot_fis_do_upgrade \"$1\" linux\n\t\t;;\n\topenmesh,a40|\\\n\topenmesh,a60|\\\n\topenmesh,mr600-v1|\\\n\topenmesh,mr600-v2|\\\n\topenmesh,mr900-v1|\\\n\topenmesh,mr900-v2|\\\n\topenmesh,mr1750-v1|\\\n\topenmesh,mr1750-v2|\\\n\topenmesh,om2p-v1|\\\n\topenmesh,om2p-v2|\\\n\topenmesh,om2p-v4|\\\n\topenmesh,om2p-hs-v1|\\\n\topenmesh,om2p-hs-v2|\\\n\topenmesh,om2p-hs-v3|\\\n\topenmesh,om2p-hs-v4|\\\n\topenmesh,om2p-lc|\\\n\topenmesh,om5p|\\\n\topenmesh,om5p-ac-v1|\\\n\topenmesh,om5p-ac-v2|\\\n\topenmesh,om5p-an)\n\t\tPART_NAME=\"inactive\"\n\t\tplatform_do_upgrade_openmesh \"$1\"\n\t\t;;\n\tplasmacloud,pa300|\\\n\tplasmacloud,pa300e)\n\t\tPART_NAME=\"inactive\"\n\t\tplatform_do_upgrade_dualboot_datachk \"$1\"\n\t\t;;\n\tubnt,routerstation|\\\n\tubnt,routerstation-pro)\n\t\tredboot_fis_do_upgrade \"$1\" kernel\n\t\t;;\n\t*)\n\t\tdefault_do_upgrade \"$1\"\n\t\t;;\n\tesac\n}\n"
  },
  {
    "path": "target/linux/ath79/generic/config-default",
    "content": "CONFIG_BCM_NET_PHYLIB=y\nCONFIG_BROADCOM_PHY=y\nCONFIG_GPIO_PCA953X=y\nCONFIG_GPIO_PCA953X_IRQ=y\nCONFIG_GPIO_WATCHDOG=y\nCONFIG_GPIO_WATCHDOG_ARCH_INITCALL=y\nCONFIG_I2C=y\nCONFIG_I2C_ALGOBIT=y\nCONFIG_I2C_CHARDEV=y\nCONFIG_I2C_GPIO=y\nCONFIG_INTEL_XWAY_PHY=y\nCONFIG_IP17XX_PHY=y\nCONFIG_LEDS_RESET=y\nCONFIG_MARVELL_PHY=y\nCONFIG_MICREL_PHY=y\nCONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-3\nCONFIG_MTD_REDBOOT_PARTS=y\nCONFIG_MTD_SPLIT_EVA_FW=y\nCONFIG_PHY_AR7100_USB=y\nCONFIG_PHY_AR7200_USB=y\nCONFIG_REGULATOR_FIXED_VOLTAGE=y\nCONFIG_RTL8366RB_PHY=y\nCONFIG_RTL8366S_PHY=y\nCONFIG_RTL8366_SMI=y\nCONFIG_RTL8367_PHY=y\nCONFIG_VITESSE_PHY=y\nCONFIG_WATCHDOG_CORE=y\n"
  },
  {
    "path": "target/linux/ath79/generic/target.mk",
    "content": "BOARDNAME:=Generic\n\nDEFAULT_PACKAGES += wpad-basic-wolfssl\n\nKERNEL_TESTING_PATCHVER:=5.15\n\ndefine Target/Description\n\tBuild firmware images for generic Atheros AR71xx/AR913x/AR934x based boards.\nendef\n"
  },
  {
    "path": "target/linux/ath79/image/Makefile",
    "content": "include $(TOPDIR)/rules.mk\ninclude $(INCLUDE_DIR)/image.mk\n\nKERNEL_LOADADDR = 0x80060000\n\nDEVICE_VARS += LOADER_FLASH_OFFS LOADER_TYPE\nDEVICE_VARS += LOADER_FLASH_MAX LOADER_KERNEL_MAGIC\nDEVICE_VARS += NETGEAR_BOARD_ID NETGEAR_HW_ID\nDEVICE_VARS += RAS_BOARD RAS_ROOTFS_SIZE RAS_VERSION\n\ndefine Build/combined-image\n\tsh $(TOPDIR)/scripts/combined-image.sh \\\n\t\t\"$(IMAGE_KERNEL)\" \\\n\t\t\"$@\" \\\n\t\t\"$@.new\"\n\t@mv $@.new $@\nendef\n\ndefine Build/loader-common\n\trm -rf $@.src\n\t$(MAKE) -C lzma-loader \\\n\t\tPKG_BUILD_DIR=\"$@.src\" \\\n\t\tTARGET_DIR=\"$(dir $@)\" LOADER_NAME=\"$(notdir $@)\" \\\n\t\t$(1) compile loader.$(LOADER_TYPE)\n\tmv \"$@.$(LOADER_TYPE)\" \"$@\"\n\trm -rf $@.src\nendef\n\ndefine Build/loader-kernel\n\t$(call Build/loader-common, \\\n\t\tLOADER_DATA=\"$@\" \\\n\t\tBOARD=\"$(DEVICE_NAME)\" )\nendef\n\ndefine Build/loader-okli-compile\n\t$(call Build/loader-common, \\\n\t\tFLASH_OFFS=$(LOADER_FLASH_OFFS) \\\n\t\tFLASH_MAX=$(LOADER_FLASH_MAX) \\\n\t\tKERNEL_MAGIC=$(LOADER_KERNEL_MAGIC) \\\n\t\tBOARD=\"$(DEVICE_NAME)\" )\nendef\n\n# Arguments: <output name> <kernel offset>\ndefine Build/loader-okli\n\tdd if=$(KDIR)/loader-$(word 1,$(1)).$(LOADER_TYPE) bs=$(word 2,$(1)) conv=sync of=\"$@.new\"\n\tcat \"$@\" >> \"$@.new\"\n\tmv \"$@.new\" \"$@\"\nendef\n\ndefine Build/append-loader-okli\n\tcat \"$(KDIR)/loader-$(word 1,$(1)).$(LOADER_TYPE)\" >> \"$@\"\nendef\n\ndefine Build/append-loader-okli-uimage\n\tcat \"$(KDIR)/loader-$(word 1,$(1)).uImage\" >> \"$@\"\nendef\n\ndefine Build/relocate-kernel\n\trm -rf $@.relocate\n\t$(CP) ../../generic/image/relocate $@.relocate\n\t$(MAKE) -j1 -C $@.relocate KERNEL_ADDR=$(KERNEL_LOADADDR) CROSS_COMPILE=$(TARGET_CROSS)\n\t( \\\n\t\tdd if=$@.relocate/loader.bin bs=32 conv=sync && \\\n\t\tperl -e '@s = stat(\"$@\"); print pack(\"N\", @s[7])' && \\\n\t\tcat \"$@\" \\\n\t) > \"$@.new\"\n\tmv \"$@.new\" \"$@\"\n\trm -rf $@.relocate\nendef\n\n\ndefine Device/Default\n  DEVICE_DTS_DIR := ../dts\n  DEVICE_DTS = $$(SOC)_$(1)\n  PROFILES = Default\n  MTDPARTS :=\n  BLOCKSIZE := 64k\n  KERNEL := kernel-bin | append-dtb | lzma | uImage lzma\n  KERNEL_INITRAMFS := kernel-bin | append-dtb | lzma | uImage lzma\n  LOADER_KERNEL_MAGIC :=\n  LOADER_FLASH_MAX :=\n  LOADER_FLASH_OFFS :=\n  LOADER_TYPE :=\n  COMPILE :=\n  IMAGES := sysupgrade.bin\n  IMAGE/sysupgrade.bin = append-kernel | pad-to $$$$(BLOCKSIZE) | \\\n\tappend-rootfs | pad-rootfs | check-size | append-metadata\nendef\n\ndefine Device/loader-okli-uimage\n  LOADER_TYPE := bin\n  COMPILE := loader-$(1).bin loader-$(1).uImage\n  COMPILE/loader-$(1).bin := loader-okli-compile\n  COMPILE/loader-$(1).uImage := append-loader-okli $(1) | pad-to 64k | \\\n\tlzma | uImage lzma\nendef\n\ninclude $(SUBTARGET).mk\n\nifeq ($(SUBTARGET),generic)\ninclude generic-tp-link.mk\ninclude generic-ubnt.mk\nendif\n\nifeq ($(SUBTARGET),tiny)\ninclude tiny-netgear.mk\ninclude tiny-tp-link.mk\nendif\n\n$(eval $(call BuildImage))\n"
  },
  {
    "path": "target/linux/ath79/image/common-buffalo.mk",
    "content": "DEVICE_VARS += BUFFALO_PRODUCT BUFFALO_HWVER\n\ndefine Build/buffalo-tag\n\t$(eval product=$(word 1,$(1)))\n\t$(eval hwver=$(word 2,$(1)))\n\t$(STAGING_DIR_HOST)/bin/buffalo-tag \\\n\t\t-c 0x80041000 -d 0x801e8000 -w $(hwver) \\\n\t\t-a ath -v 1.99 -m 1.01 -f 1 \\\n\t\t-b $(product) -p $(product) \\\n\t\t-r M_ -l mlang8 \\\n\t\t-i $@ -o $@.new\n\tmv $@.new $@\nendef\n\ndefine Build/buffalo-tftp-header\n\t( \\\n\t\techo -n -e \"# Airstation Public Fmt1\" | dd bs=32 count=1 conv=sync; \\\n\t\tdd if=$@; \\\n\t) > $@.new\n\tmv $@.new $@\nendef\n\n\ndefine Device/buffalo_common\n  DEVICE_VENDOR := Buffalo\n  BUFFALO_PRODUCT :=\n  BUFFALO_HWVER := 3\n  IMAGES += factory.bin tftp.bin\n  IMAGE/default := append-kernel | pad-to $$$$(BLOCKSIZE) | append-rootfs | \\\n\tpad-rootfs | check-size\n  IMAGE/factory.bin := $$(IMAGE/default) | buffalo-enc $$$$(BUFFALO_PRODUCT) 1.99 | \\\n\tbuffalo-tag $$$$(BUFFALO_PRODUCT) $$$$(BUFFALO_HWVER)\n  IMAGE/tftp.bin := $$(IMAGE/default) | buffalo-tftp-header\nendef\n"
  },
  {
    "path": "target/linux/ath79/image/common-mikrotik.mk",
    "content": "define Device/mikrotik\n\tDEVICE_VENDOR := MikroTik\n\tKERNEL_NAME := vmlinuz\n\tKERNEL := kernel-bin | append-dtb-elf\n\tKERNEL_INITRAMFS := kernel-bin | append-dtb-elf\nendef\n\ndefine Device/mikrotik_nor\n  $(Device/mikrotik)\n  IMAGE/sysupgrade.bin := append-kernel | kernel2minor -s 1024 -e | \\\n\tpad-to $$$$(BLOCKSIZE) | append-rootfs | pad-rootfs | \\\n\tcheck-size | append-metadata\nendef\n\ndefine Device/mikrotik_nand\n  $(Device/mikrotik)\n  IMAGE/sysupgrade.bin = append-kernel | kernel2minor -s 2048 -e -c | \\\n\tsysupgrade-tar kernel=$$$$@ | append-metadata\n  DEVICE_PACKAGES := nand-utils\n  DEFAULT := n\nendef\n"
  },
  {
    "path": "target/linux/ath79/image/common-netgear.mk",
    "content": "define Build/netgear-rootfs\n\tmkimage \\\n\t\t-A mips -O linux -T filesystem -C none \\\n\t\t$(if $(UIMAGE_MAGIC),-M $(UIMAGE_MAGIC)) \\\n\t\t-n '$(VERSION_DIST) filesystem' \\\n\t\t-d $(IMAGE_ROOTFS) $@.fs\n\tcat $@.fs >> $@\n\trm -rf $@.fs\nendef\n\ndefine Build/netgear-squashfs\n\trm -rf $@.fs $@.squashfs\n\tmkdir -p $@.fs/image\n\tcp $@ $@.fs/image/uImage\n\t$(STAGING_DIR_HOST)/bin/mksquashfs-lzma  \\\n\t\t$@.fs $@.squashfs -be \\\n\t\t-noappend -root-owned -b 65536 \\\n\t\t$(if $(SOURCE_DATE_EPOCH),-fixed-time $(SOURCE_DATE_EPOCH))\n\n\tdd if=/dev/zero bs=1k count=1 >> $@.squashfs\n\tmkimage \\\n\t\t-A mips -O linux -T filesystem -C none \\\n\t\t$(if $(UIMAGE_MAGIC),-M $(UIMAGE_MAGIC)) \\\n\t\t-a 0xbf070000 -e 0xbf070000 \\\n\t\t-n 'MIPS $(VERSION_DIST) Linux-$(LINUX_VERSION)' \\\n\t\t-d $@.squashfs $@\n\trm -rf $@.squashfs $@.fs\nendef\n\ndefine Device/netgear_generic\n  DEVICE_VENDOR := NETGEAR\n  KERNEL := kernel-bin | append-dtb | lzma -d20 | uImage lzma\n  KERNEL_INITRAMFS := kernel-bin | append-dtb | lzma -d20 | uImage lzma\n  IMAGES += factory.img\n  IMAGE/default := append-kernel | pad-to $$$$(BLOCKSIZE) | \\\n\tnetgear-squashfs | append-rootfs | pad-rootfs\n  IMAGE/sysupgrade.bin := $$(IMAGE/default) | check-size | append-metadata\n  IMAGE/factory.img := $$(IMAGE/default) | netgear-dni | check-size\nendef\n"
  },
  {
    "path": "target/linux/ath79/image/common-senao.mk",
    "content": "DEVICE_VARS += SENAO_IMGNAME\n\n# This needs to make OEM config archive 'sysupgrade.tgz' an empty file prior to OEM\n# sysupgrade, as otherwise it will implant the old configuration from\n# OEM firmware when writing rootfs from factory.bin\n# rootfs size and checksum is taken from a squashfs header\n# the header does not exist, therefore, supply the size and md5\ndefine Build/senao-tar-gz\n\t-[ -f \"$@\" ] && \\\n\tmkdir -p $@.tmp && \\\n\ttouch $@.tmp/failsafe.bin && \\\n\ttouch $@.tmp/FWINFO-$(word 1,$(1))-$(REVISION) && \\\n\techo '#!/bin/sh' > $@.tmp/before-upgrade.sh && \\\n\techo ': > /tmp/sysupgrade.tgz' >> $@.tmp/before-upgrade.sh && \\\n\techo ': > /tmp/_sys/sysupgrade.tgz' >> $@.tmp/before-upgrade.sh && \\\n\techo -n $$(( $$(cat $@ | wc -c) / 4096 * 4096 )) > $@.len && \\\n\tdd if=$@ bs=$$(cat $@.len) count=1 | md5sum - | cut -d ' ' -f 1 > $@.md5 && \\\n\techo '#!/bin/sh' > $@.tmp/after-upgrade.sh && \\\n\tprintf 'fw_setenv rootfs_size 0x%08x\\n' $$(cat $@.len) >> $@.tmp/after-upgrade.sh && \\\n\tprintf 'fw_setenv rootfs_checksum %s\\n' $$(cat $@.md5) >> $@.tmp/after-upgrade.sh && \\\n\t$(CP) $(KDIR)/loader-$(DEVICE_NAME).uImage \\\n\t\t$@.tmp/openwrt-$(word 1,$(1))-uImage-lzma.bin && \\\n\t$(CP) $@ $@.tmp/openwrt-$(word 1,$(1))-root.squashfs && \\\n\t$(TAR) -cp --numeric-owner --owner=0 --group=0 --mode=a-s --sort=name \\\n\t\t$(if $(SOURCE_DATE_EPOCH),--mtime=\"@$(SOURCE_DATE_EPOCH)\") \\\n\t\t-C $@.tmp . | gzip -9n > $@ && \\\n\trm -rf $@.tmp $@.len $@.md5\nendef\n\ndefine Device/senao_loader_okli\n  $(Device/loader-okli-uimage)\n  KERNEL := kernel-bin | append-dtb | lzma | uImage lzma -M 0x73714f4b\n  LOADER_KERNEL_MAGIC := 0x73714f4b\n  IMAGES += factory.bin\n  IMAGE/factory.bin := append-kernel | pad-to $$$$(BLOCKSIZE) | append-rootfs | pad-rootfs | \\\n\tcheck-size | senao-tar-gz $$$$(SENAO_IMGNAME)\n  IMAGE/sysupgrade.bin := $$(IMAGE/factory.bin) | append-metadata\nendef\n"
  },
  {
    "path": "target/linux/ath79/image/common-tp-link.mk",
    "content": "DEVICE_VARS += TPLINK_HWID TPLINK_HWREV TPLINK_FLASHLAYOUT TPLINK_HEADER_VERSION\nDEVICE_VARS += TPLINK_BOARD_ID TPLINK_HWREVADD TPLINK_HVERSION\n\ndefine Device/tplink-v1\n  DEVICE_VENDOR := TP-Link\n  TPLINK_HWID := 0x0\n  TPLINK_HWREV := 0x1\n  TPLINK_HEADER_VERSION := 1\n  LOADER_TYPE := gz\n  KERNEL := kernel-bin | append-dtb | lzma\n  KERNEL_INITRAMFS := kernel-bin | append-dtb | lzma | tplink-v1-header\n  IMAGES += factory.bin\n  IMAGE/sysupgrade.bin := tplink-v1-image sysupgrade | append-metadata\n  IMAGE/factory.bin := tplink-v1-image factory\nendef\n\ndefine Device/tplink-v2\n  DEVICE_VENDOR := TP-Link\n  TPLINK_HWID := 0x0\n  TPLINK_HWREV := 0x1\n  TPLINK_HWREVADD := 0x0\n  TPLINK_HVERSION := 3\n  KERNEL := kernel-bin | append-dtb | lzma\n  KERNEL_INITRAMFS := kernel-bin | append-dtb | lzma | tplink-v2-header\n  IMAGE/sysupgrade.bin := tplink-v2-image -s | check-size | append-metadata\nendef\n\ndefine Device/tplink-nolzma\n  $(Device/tplink-v1)\n  LOADER_FLASH_OFFS := 0x22000\n  COMPILE := loader-$(1).gz\n  COMPILE/loader-$(1).gz := loader-okli-compile\n  KERNEL := kernel-bin | append-dtb | lzma | uImage lzma -M 0x4f4b4c49 | \\\n\tloader-okli $(1) 7680\n  KERNEL_INITRAMFS := kernel-bin | append-dtb | gzip | tplink-v1-header\nendef\n\ndefine Device/tplink-4m\n  $(Device/tplink-nolzma)\n  TPLINK_FLASHLAYOUT := 4M\n  IMAGE_SIZE := 3904k\n  DEFAULT := n\nendef\n\ndefine Device/tplink-4mlzma\n  $(Device/tplink-v1)\n  TPLINK_FLASHLAYOUT := 4Mlzma\n  IMAGE_SIZE := 3904k\n  DEFAULT := n\nendef\n\ndefine Device/tplink-8m\n  $(Device/tplink-nolzma)\n  TPLINK_FLASHLAYOUT := 8M\n  IMAGE_SIZE := 8000k\nendef\n\ndefine Device/tplink-8mlzma\n  $(Device/tplink-v1)\n  TPLINK_FLASHLAYOUT := 8Mlzma\n  IMAGE_SIZE := 8000k\nendef\n\ndefine Device/tplink-16mlzma\n  $(Device/tplink-v1)\n  TPLINK_FLASHLAYOUT := 16Mlzma\n  IMAGE_SIZE := 16192k\nendef\n\ndefine Device/tplink-safeloader\n  $(Device/tplink-v1)\n  TPLINK_HWREV := 0x0\n  KERNEL := kernel-bin | append-dtb | lzma | tplink-v1-header -O\n  KERNEL_INITRAMFS := $$(KERNEL)\n  IMAGE/sysupgrade.bin := append-rootfs | tplink-safeloader sysupgrade | \\\n\tcheck-size | append-metadata\n  IMAGE/factory.bin := append-rootfs | tplink-safeloader factory\nendef\n\ndefine Device/tplink-safeloader-uimage\n  $(Device/tplink-safeloader)\n  KERNEL := kernel-bin | append-dtb | lzma | uImage lzma\n  KERNEL_INITRAMFS := $$(KERNEL)\nendef\n\ndefine Device/tplink-safeloader-okli\n  $(Device/tplink-safeloader)\n  LOADER_TYPE := elf\n  LOADER_FLASH_OFFS := 0x43000\n  COMPILE := loader-$(1).elf\n  COMPILE/loader-$(1).elf := loader-okli-compile\n  KERNEL := kernel-bin | append-dtb | lzma | uImage lzma -M 0x4f4b4c49 | \\\n\tloader-okli $(1) 12288\n  KERNEL_INITRAMFS := $$(KERNEL)\nendef\n"
  },
  {
    "path": "target/linux/ath79/image/common-yuncore.mk",
    "content": "define Build/yuncore-tftp-header-16m\n\t( \\\n\t\techo -n -e \\\n\t\t\t\"YUNCOREsetenv bootcmd \\\"bootm 0x9f050000 || bootm 0x9fe80000\\\"\" \\\n\t\t\t\"&& saveenv\" \\\n\t\t\t\"&& erase 0x9f050000 +0xfa0000\" \\\n\t\t\t\"&& cp.b 0x800600c0 0x9f050000 0xfa0000\" |\\\n\t\tdd bs=192 count=1 conv=sync; \\\n\t\tdd if=$@; \\\n\t) > $@.new\n\tmv $@.new $@\nendef\n"
  },
  {
    "path": "target/linux/ath79/image/generic-tp-link.mk",
    "content": "include ./common-tp-link.mk\n\ndefine Device/tplink_archer-a7-v5\n  $(Device/tplink-safeloader-uimage)\n  SOC := qca9563\n  IMAGE_SIZE := 15104k\n  DEVICE_MODEL := Archer A7\n  DEVICE_VARIANT := v5\n  DEVICE_PACKAGES := kmod-usb2 kmod-usb-ledtrig-usbport kmod-ath10k-ct \\\n\tath10k-firmware-qca988x-ct\n  TPLINK_BOARD_ID := ARCHER-A7-V5\nendef\nTARGET_DEVICES += tplink_archer-a7-v5\n\ndefine Device/tplink_archer-a9-v6\n  $(Device/tplink-safeloader-uimage)\n  SOC := qcn5502\n  IMAGE_SIZE := 15360k\n  DEVICE_MODEL := Archer A9\n  DEVICE_VARIANT := v6\n  DEVICE_PACKAGES := kmod-usb2 kmod-usb-ledtrig-usbport kmod-ath10k-ct \\\n\tath10k-firmware-qca9984-ct\n  TPLINK_BOARD_ID := ARCHER-A9-V6\nendef\nTARGET_DEVICES += tplink_archer-a9-v6\n\ndefine Device/tplink_archer-c2-v3\n  $(Device/tplink-safeloader-uimage)\n  SOC := qca9563\n  IMAGE_SIZE := 7808k\n  DEVICE_MODEL := Archer C2\n  DEVICE_VARIANT := v3\n  DEVICE_PACKAGES := kmod-ath10k-ct-smallbuffers ath10k-firmware-qca9887-ct\n  TPLINK_BOARD_ID := ARCHER-C2-V3\nendef\nTARGET_DEVICES += tplink_archer-c2-v3\n\ndefine Device/tplink_archer-c25-v1\n  $(Device/tplink-safeloader-uimage)\n  SOC := qca9561\n  IMAGE_SIZE := 7808k\n  DEVICE_MODEL := Archer C25\n  DEVICE_VARIANT := v1\n  TPLINK_BOARD_ID := ARCHER-C25-V1\n  DEVICE_PACKAGES := kmod-ath10k-ct-smallbuffers ath10k-firmware-qca9887-ct\n  SUPPORTED_DEVICES += archer-c25-v1\nendef\nTARGET_DEVICES += tplink_archer-c25-v1\n\ndefine Device/tplink_archer-c5-v1\n  $(Device/tplink-16mlzma)\n  SOC := qca9558\n  DEVICE_MODEL := Archer C5\n  DEVICE_VARIANT := v1\n  DEVICE_PACKAGES := kmod-usb2 kmod-usb-ledtrig-usbport kmod-ath10k-ct \\\n\tath10k-firmware-qca988x-ct\n  TPLINK_HWID := 0xc5000001\n  SUPPORTED_DEVICES += archer-c5\nendef\nTARGET_DEVICES += tplink_archer-c5-v1\n\ndefine Device/tplink_archer-c58-v1\n  $(Device/tplink-safeloader-uimage)\n  SOC := qca9561\n  IMAGE_SIZE := 7936k\n  DEVICE_MODEL := Archer C58\n  DEVICE_VARIANT := v1\n  TPLINK_BOARD_ID := ARCHER-C58-V1\n  DEVICE_PACKAGES := kmod-ath10k-ct-smallbuffers ath10k-firmware-qca9888-ct\n  SUPPORTED_DEVICES += archer-c58-v1\nendef\nTARGET_DEVICES += tplink_archer-c58-v1\n\ndefine Device/tplink_archer-c59-v1\n  $(Device/tplink-safeloader-uimage)\n  SOC := qca9561\n  IMAGE_SIZE := 14528k\n  DEVICE_MODEL := Archer C59\n  DEVICE_VARIANT := v1\n  TPLINK_BOARD_ID := ARCHER-C59-V1\n  DEVICE_PACKAGES := kmod-usb2 kmod-usb-ledtrig-usbport kmod-ath10k-ct \\\n\tath10k-firmware-qca9888-ct\n  SUPPORTED_DEVICES += archer-c59-v1\nendef\nTARGET_DEVICES += tplink_archer-c59-v1\n\ndefine Device/tplink_archer-c59-v2\n  $(Device/tplink-safeloader-uimage)\n  SOC := qca9561\n  IMAGE_SIZE := 14400k\n  DEVICE_MODEL := Archer C59\n  DEVICE_VARIANT := v2\n  TPLINK_BOARD_ID := ARCHER-C59-V2\n  DEVICE_PACKAGES := kmod-usb2 kmod-usb-ledtrig-usbport kmod-ath10k-ct \\\n\tath10k-firmware-qca9888-ct\n  SUPPORTED_DEVICES += archer-c59-v2\nendef\nTARGET_DEVICES += tplink_archer-c59-v2\n\ndefine Device/tplink_archer-c6-v2\n  $(Device/tplink-safeloader-uimage)\n  SOC := qca9563\n  IMAGE_SIZE := 7808k\n  DEVICE_MODEL := Archer C6\n  DEVICE_VARIANT := v2 (EU/RU/JP)\n  TPLINK_BOARD_ID := ARCHER-C6-V2\n  DEVICE_PACKAGES := kmod-ath10k-ct ath10k-firmware-qca9888-ct\nendef\nTARGET_DEVICES += tplink_archer-c6-v2\n\ndefine Device/tplink_archer-c6-v2-us\n  $(Device/tplink-safeloader-uimage)\n  SOC := qca9563\n  IMAGE_SIZE := 15872k\n  DEVICE_MODEL := Archer C6\n  DEVICE_VARIANT := v2 (US)\n  DEVICE_ALT0_VENDOR := TP-Link\n  DEVICE_ALT0_MODEL := Archer A6\n  DEVICE_ALT0_VARIANT := v2 (US/TW)\n  TPLINK_BOARD_ID := ARCHER-C6-V2-US\n  DEVICE_PACKAGES := kmod-ath10k-ct ath10k-firmware-qca9888-ct\nendef\nTARGET_DEVICES += tplink_archer-c6-v2-us\n\ndefine Device/tplink_archer-c60-v1\n  $(Device/tplink-safeloader-uimage)\n  SOC := qca9561\n  IMAGE_SIZE := 7936k\n  DEVICE_MODEL := Archer C60\n  DEVICE_VARIANT := v1\n  TPLINK_BOARD_ID := ARCHER-C60-V1\n  DEVICE_PACKAGES := kmod-ath10k-ct-smallbuffers ath10k-firmware-qca9888-ct\n  SUPPORTED_DEVICES += archer-c60-v1\nendef\nTARGET_DEVICES += tplink_archer-c60-v1\n\ndefine Device/tplink_archer-c60-v2\n  $(Device/tplink-safeloader-uimage)\n  SOC := qca9561\n  IMAGE_SIZE := 7808k\n  DEVICE_MODEL := Archer C60\n  DEVICE_VARIANT := v2\n  TPLINK_BOARD_ID := ARCHER-C60-V2\n  DEVICE_PACKAGES := kmod-ath10k-ct-smallbuffers ath10k-firmware-qca9888-ct\n  SUPPORTED_DEVICES += archer-c60-v2\nendef\nTARGET_DEVICES += tplink_archer-c60-v2\n\ndefine Device/tplink_archer-c60-v3\n  $(Device/tplink-safeloader-uimage)\n  SOC := qca9561\n  IMAGE_SIZE := 7808k\n  DEVICE_MODEL := Archer C60\n  DEVICE_VARIANT := v3\n  TPLINK_BOARD_ID := ARCHER-C60-V3\n  DEVICE_PACKAGES := kmod-ath10k-ct-smallbuffers ath10k-firmware-qca9888-ct\nendef\nTARGET_DEVICES += tplink_archer-c60-v3\n\ndefine Device/tplink_archer-c7-v1\n  $(Device/tplink-8mlzma)\n  SOC := qca9558\n  DEVICE_MODEL := Archer C7\n  DEVICE_VARIANT := v1\n  DEVICE_PACKAGES := kmod-usb2 kmod-usb-ledtrig-usbport\n  TPLINK_HWID := 0x75000001\n  SUPPORTED_DEVICES += archer-c7\nendef\nTARGET_DEVICES += tplink_archer-c7-v1\n\ndefine Device/tplink_archer-c7-v2\n  $(Device/tplink-16mlzma)\n  SOC := qca9558\n  DEVICE_MODEL := Archer C7\n  DEVICE_VARIANT := v2\n  DEVICE_PACKAGES := kmod-usb2 kmod-usb-ledtrig-usbport kmod-ath10k-ct \\\n\tath10k-firmware-qca988x-ct\n  TPLINK_HWID := 0xc7000002\n  SUPPORTED_DEVICES += archer-c7\n  IMAGES += factory-us.bin factory-eu.bin\n  IMAGE/factory-us.bin := tplink-v1-image factory -C US\n  IMAGE/factory-eu.bin := tplink-v1-image factory -C EU\nendef\nTARGET_DEVICES += tplink_archer-c7-v2\n\ndefine Device/tplink_archer-c7-v4\n  $(Device/tplink-safeloader-uimage)\n  SOC := qca9563\n  IMAGE_SIZE := 15104k\n  DEVICE_MODEL := Archer C7\n  DEVICE_VARIANT := v4\n  DEVICE_PACKAGES := kmod-usb2 kmod-usb-ledtrig-usbport kmod-ath10k-ct \\\n\tath10k-firmware-qca988x-ct\n  TPLINK_BOARD_ID := ARCHER-C7-V4\n  SUPPORTED_DEVICES += archer-c7-v4\nendef\nTARGET_DEVICES += tplink_archer-c7-v4\n\ndefine Device/tplink_archer-c7-v5\n  $(Device/tplink-safeloader-uimage)\n  SOC := qca9563\n  IMAGE_SIZE := 15360k\n  DEVICE_MODEL := Archer C7\n  DEVICE_VARIANT := v5\n  DEVICE_PACKAGES := kmod-usb2 kmod-usb-ledtrig-usbport kmod-ath10k-ct \\\n\tath10k-firmware-qca988x-ct\n  TPLINK_BOARD_ID := ARCHER-C7-V5\n  SUPPORTED_DEVICES += archer-c7-v5\nendef\nTARGET_DEVICES += tplink_archer-c7-v5\n\ndefine Device/tplink_archer-d50-v1\n  $(Device/tplink-v2)\n  SOC := qca9531\n  DEVICE_MODEL := Archer D50\n  DEVICE_VARIANT := v1\n  DEVICE_PACKAGES := kmod-usb2 kmod-usb-ledtrig-usbport \\\n\tkmod-ath10k-ct-smallbuffers ath10k-firmware-qca988x-ct\n  IMAGE_SIZE := 7808k\n  TPLINK_HWID := 0xC1200001\n  TPLINK_HWREV := 0x00000046\n  TPLINK_FLASHLAYOUT := 8Mqca\n  KERNEL_INITRAMFS := kernel-bin | append-dtb | lzma | \\\n\ttplink-v2-header -s -V \"ver. 1.0\"\nendef\nTARGET_DEVICES += tplink_archer-d50-v1\n\ndefine Device/tplink_archer-d7-v1\n  $(Device/tplink-v2)\n  SOC := qca9558\n  DEVICE_MODEL := Archer D7\n  DEVICE_VARIANT := v1\n  DEVICE_PACKAGES := kmod-usb2 kmod-usb-ledtrig-usbport \\\n\tkmod-ath10k-ct ath10k-firmware-qca988x-ct\n  IMAGE_SIZE := 15936k\n  TPLINK_HWID := 0x89300001\n  TPLINK_HWREV := 0x0000002D\n  TPLINK_FLASHLAYOUT := 16Mqca\n  TPLINK_HWREVADD := 0x00000002\nendef\nTARGET_DEVICES += tplink_archer-d7-v1\n\ndefine Device/tplink_archer-d7b-v1\n  $(Device/tplink-v2)\n  SOC := qca9558\n  DEVICE_MODEL := Archer D7b\n  DEVICE_VARIANT := v1\n  DEVICE_PACKAGES := kmod-usb2 kmod-usb-ledtrig-usbport \\\n\tkmod-ath10k-ct ath10k-firmware-qca988x-ct\n  IMAGE_SIZE := 16000k\n  TPLINK_HWID := 0x89300001\n  TPLINK_HWREV := 0x0000003D\n  TPLINK_FLASHLAYOUT := 16Mqca\nendef\nTARGET_DEVICES += tplink_archer-d7b-v1\n\ndefine Device/tplink_cpe210-v1\n  $(Device/tplink-safeloader-okli)\n  SOC := ar9344\n  IMAGE_SIZE := 7680k\n  DEVICE_MODEL := CPE210\n  DEVICE_VARIANT := v1\n  DEVICE_PACKAGES := rssileds\n  TPLINK_BOARD_ID := CPE210\n  SUPPORTED_DEVICES += cpe210\nendef\nTARGET_DEVICES += tplink_cpe210-v1\n\ndefine Device/tplink_cpe210-v2\n  $(Device/tplink-safeloader)\n  SOC := qca9533\n  IMAGE_SIZE := 7680k\n  DEVICE_MODEL := CPE210\n  DEVICE_VARIANT := v2\n  TPLINK_BOARD_ID := CPE210V2\n  DEVICE_PACKAGES := rssileds\n  LOADER_TYPE := elf\n  SUPPORTED_DEVICES += cpe210-v2\nendef\nTARGET_DEVICES += tplink_cpe210-v2\n\ndefine Device/tplink_cpe210-v3\n  $(Device/tplink-safeloader)\n  SOC := qca9533\n  IMAGE_SIZE := 7680k\n  DEVICE_MODEL := CPE210\n  DEVICE_VARIANT := v3\n  DEVICE_PACKAGES := rssileds\n  TPLINK_BOARD_ID := CPE210V3\n  LOADER_TYPE := elf\n  SUPPORTED_DEVICES += cpe210-v3\nendef\nTARGET_DEVICES += tplink_cpe210-v3\n\ndefine Device/tplink_cpe220-v2\n  $(Device/tplink-safeloader-okli)\n  SOC := ar9344\n  IMAGE_SIZE := 7680k\n  DEVICE_MODEL := CPE220\n  DEVICE_VARIANT := v2\n  DEVICE_PACKAGES := rssileds\n  TPLINK_BOARD_ID := CPE220V2\nendef\nTARGET_DEVICES += tplink_cpe220-v2\n\ndefine Device/tplink_cpe220-v3\n  $(Device/tplink-safeloader)\n  SOC := qca9533\n  IMAGE_SIZE := 7680k\n  DEVICE_MODEL := CPE220\n  DEVICE_VARIANT := v3\n  DEVICE_PACKAGES := rssileds\n  TPLINK_BOARD_ID := CPE220V3\n  LOADER_TYPE := elf\nendef\nTARGET_DEVICES += tplink_cpe220-v3\n\ndefine Device/tplink_cpe510-v1\n  $(Device/tplink-safeloader-okli)\n  SOC := ar9344\n  IMAGE_SIZE := 7680k\n  DEVICE_MODEL := CPE510\n  DEVICE_VARIANT := v1\n  DEVICE_PACKAGES := rssileds\n  TPLINK_BOARD_ID := CPE510\n  SUPPORTED_DEVICES += cpe510\nendef\nTARGET_DEVICES += tplink_cpe510-v1\n\ndefine Device/tplink_cpe510-v2\n  $(Device/tplink-safeloader-okli)\n  SOC := ar9344\n  IMAGE_SIZE := 7680k\n  DEVICE_MODEL := CPE510\n  DEVICE_VARIANT := v2\n  DEVICE_PACKAGES := rssileds\n  TPLINK_BOARD_ID := CPE510V2\n  SUPPORTED_DEVICES += cpe510-v2\nendef\nTARGET_DEVICES += tplink_cpe510-v2\n\ndefine Device/tplink_cpe510-v3\n  $(Device/tplink-safeloader-okli)\n  SOC := ar9344\n  IMAGE_SIZE := 7680k\n  DEVICE_MODEL := CPE510\n  DEVICE_VARIANT := v3\n  DEVICE_PACKAGES := rssileds\n  TPLINK_BOARD_ID := CPE510V3\nendef\nTARGET_DEVICES += tplink_cpe510-v3\n\ndefine Device/tplink_cpe610-v1\n  $(Device/tplink-safeloader-okli)\n  SOC := ar9344\n  IMAGE_SIZE := 7680k\n  DEVICE_MODEL := CPE610\n  DEVICE_VARIANT := v1\n  TPLINK_BOARD_ID := CPE610V1\nendef\nTARGET_DEVICES += tplink_cpe610-v1\n\ndefine Device/tplink_cpe610-v2\n  $(Device/tplink-safeloader-okli)\n  SOC := ar9344\n  IMAGE_SIZE := 7680k\n  DEVICE_MODEL := CPE610\n  DEVICE_VARIANT := v2\n  TPLINK_BOARD_ID := CPE610V2\nendef\nTARGET_DEVICES += tplink_cpe610-v2\n\ndefine Device/tplink_cpe710-v1\n  $(Device/tplink-safeloader-uimage)\n  SOC := qca9563\n  IMAGE_SIZE := 15680k\n  DEVICE_MODEL := CPE710\n  DEVICE_VARIANT := v1\n  DEVICE_PACKAGES := kmod-ath10k-ct ath10k-firmware-qca9888-ct\n  TPLINK_BOARD_ID := CPE710V1\nendef\nTARGET_DEVICES += tplink_cpe710-v1\n\ndefine Device/tplink-eap2x5\n  $(Device/tplink-safeloader)\n  LOADER_TYPE := elf\n  KERNEL := kernel-bin | append-dtb | lzma | loader-kernel\n  KERNEL_INITRAMFS := $$(KERNEL)\n  IMAGE/factory.bin := append-rootfs | tplink-safeloader factory | \\\n\tpad-extra 128\nendef\n\ndefine Device/tplink_eap225-outdoor-v1\n  $(Device/tplink-eap2x5)\n  SOC := qca9563\n  IMAGE_SIZE := 13824k\n  DEVICE_MODEL := EAP225-Outdoor\n  DEVICE_VARIANT := v1\n  DEVICE_PACKAGES := kmod-ath10k-ct ath10k-firmware-qca9888-ct\n  TPLINK_BOARD_ID := EAP225-OUTDOOR-V1\nendef\nTARGET_DEVICES += tplink_eap225-outdoor-v1\n\ndefine Device/tplink_eap225-v1\n  $(Device/tplink-eap2x5)\n  SOC := qca9563\n  IMAGE_SIZE := 13824k\n  DEVICE_MODEL := EAP225\n  DEVICE_VARIANT := v1\n  DEVICE_PACKAGES := kmod-ath10k-ct ath10k-firmware-qca988x-ct\n  TPLINK_BOARD_ID := EAP225-V1\nendef\nTARGET_DEVICES += tplink_eap225-v1\n\ndefine Device/tplink_eap225-v3\n  $(Device/tplink-eap2x5)\n  SOC := qca9563\n  IMAGE_SIZE := 13824k\n  DEVICE_MODEL := EAP225\n  DEVICE_VARIANT := v3\n  DEVICE_PACKAGES := kmod-ath10k-ct ath10k-firmware-qca9888-ct\n  TPLINK_BOARD_ID := EAP225-V3\nendef\nTARGET_DEVICES += tplink_eap225-v3\n\ndefine Device/tplink_eap225-wall-v2\n  $(Device/tplink-eap2x5)\n  SOC := qca9561\n  IMAGE_SIZE := 13824k\n  DEVICE_MODEL := EAP225-Wall\n  DEVICE_VARIANT := v2\n  DEVICE_PACKAGES := kmod-ath10k-ct ath10k-firmware-qca9888-ct\n  TPLINK_BOARD_ID := EAP225-WALL-V2\nendef\nTARGET_DEVICES += tplink_eap225-wall-v2\n\ndefine Device/tplink_eap245-v1\n  $(Device/tplink-eap2x5)\n  SOC := qca9563\n  IMAGE_SIZE := 13824k\n  DEVICE_MODEL := EAP245\n  DEVICE_VARIANT := v1\n  DEVICE_PACKAGES := kmod-ath10k-ct ath10k-firmware-qca988x-ct\n  TPLINK_BOARD_ID := EAP245-V1\nendef\nTARGET_DEVICES += tplink_eap245-v1\n\ndefine Device/tplink_eap245-v3\n  $(Device/tplink-eap2x5)\n  SOC := qca9563\n  IMAGE_SIZE := 14592k\n  DEVICE_MODEL := EAP245\n  DEVICE_VARIANT := v3\n  DEVICE_ALT0_VENDOR := $$(DEVICE_VENDOR)\n  DEVICE_ALT0_MODEL := EAP265 HD\n  DEVICE_ALT0_VARIANT := v1\n  DEVICE_PACKAGES := kmod-ath10k-ct ath10k-firmware-qca99x0-ct\n  TPLINK_BOARD_ID := EAP245-V3\nendef\nTARGET_DEVICES += tplink_eap245-v3\n\ndefine Device/tplink_deco-m4r-v1\n  $(Device/tplink-safeloader-uimage)\n  SOC := qca9563\n  IMAGE_SIZE := 13824k\n  DEVICE_MODEL := Deco M4R\n  DEVICE_VARIANT := v1\n  DEVICE_PACKAGES := kmod-ath10k-ct ath10k-firmware-qca9888-ct\n  SUPPORTED_DEVICES += deco-m4r-v1\n  TPLINK_BOARD_ID := DECO-M4R-V1\nendef\nTARGET_DEVICES += tplink_deco-m4r-v1\n\ndefine Device/tplink_re350k-v1\n  $(Device/tplink-safeloader)\n  SOC := qca9558\n  IMAGE_SIZE := 13760k\n  DEVICE_MODEL := RE350K\n  DEVICE_VARIANT := v1\n  DEVICE_PACKAGES := kmod-ath10k-ct ath10k-firmware-qca988x-ct\n  TPLINK_BOARD_ID := RE350K-V1\nendef\nTARGET_DEVICES += tplink_re350k-v1\n\ndefine Device/tplink_rex5x-v1\n  $(Device/tplink-safeloader)\n  SOC := qca9558\n  IMAGE_SIZE := 6016k\n  DEVICE_PACKAGES := kmod-ath10k-ct-smallbuffers ath10k-firmware-qca988x-ct\nendef\n\ndefine Device/tplink_re355-v1\n  $(Device/tplink_rex5x-v1)\n  DEVICE_MODEL := RE355\n  DEVICE_VARIANT := v1\n  TPLINK_BOARD_ID := RE355\n  SUPPORTED_DEVICES += re355\nendef\nTARGET_DEVICES += tplink_re355-v1\n\ndefine Device/tplink_re450-v1\n  $(Device/tplink_rex5x-v1)\n  DEVICE_MODEL := RE450\n  DEVICE_VARIANT := v1\n  TPLINK_BOARD_ID := RE450\n  SUPPORTED_DEVICES += re450\nendef\nTARGET_DEVICES += tplink_re450-v1\n\ndefine Device/tplink_re450-v2\n  $(Device/tplink-safeloader)\n  SOC := qca9563\n  IMAGE_SIZE := 6016k\n  DEVICE_MODEL := RE450\n  DEVICE_VARIANT := v2\n  DEVICE_PACKAGES := kmod-ath10k-ct-smallbuffers ath10k-firmware-qca988x-ct\n  TPLINK_BOARD_ID := RE450-V2\n  LOADER_TYPE := elf\nendef\nTARGET_DEVICES += tplink_re450-v2\n\ndefine Device/tplink_re450-v3\n  $(Device/tplink-safeloader)\n  SOC := qca9563\n  IMAGE_SIZE := 7808k\n  DEVICE_MODEL := RE450\n  DEVICE_VARIANT := v3\n  DEVICE_PACKAGES := kmod-ath10k-ct-smallbuffers ath10k-firmware-qca988x-ct\n  TPLINK_BOARD_ID := RE450-V3\n  LOADER_TYPE := elf\nendef\nTARGET_DEVICES += tplink_re450-v3\n\ndefine Device/tplink_re455-v1\n  $(Device/tplink-safeloader)\n  SOC := qca9563\n  IMAGE_SIZE := 7808k\n  DEVICE_MODEL := RE455\n  DEVICE_VARIANT := v1\n  DEVICE_PACKAGES := kmod-ath10k-ct-smallbuffers ath10k-firmware-qca988x-ct\n  TPLINK_BOARD_ID := RE455-V1\n  LOADER_TYPE := elf\nendef\nTARGET_DEVICES += tplink_re455-v1\n\ndefine Device/tplink_tl-mr6400-v1\n  $(Device/tplink-8mlzma)\n  SOC := qca9531\n  DEVICE_MODEL := TL-MR6400\n  DEVICE_VARIANT := v1\n  TPLINK_HWID := 0x64000001\n  DEVICE_PACKAGES := kmod-usb2 kmod-usb-net-rndis \\\n\tkmod-usb-serial-option adb-enablemodem\n  SUPPORTED_DEVICES += tl-mr6400\nendef\nTARGET_DEVICES += tplink_tl-mr6400-v1\n\ndefine Device/tplink_tl-wa1201-v2\n  $(Device/tplink-safeloader-uimage)\n  SOC := qca9563\n  IMAGE_SIZE := 13184k\n  DEVICE_MODEL := TL-WA1201\n  DEVICE_VARIANT := v2\n  TPLINK_BOARD_ID := TL-WA1201-V2\n  DEVICE_PACKAGES := kmod-ath10k-ct ath10k-firmware-qca9888-ct\nendef\nTARGET_DEVICES += tplink_tl-wa1201-v2\n\ndefine Device/tplink_tl-wdr3500-v1\n  $(Device/tplink-8mlzma)\n  SOC := ar9344\n  DEVICE_MODEL := TL-WDR3500\n  DEVICE_VARIANT := v1\n  DEVICE_PACKAGES := kmod-usb2 kmod-usb-ledtrig-usbport\n  TPLINK_HWID := 0x35000001\n  SUPPORTED_DEVICES += tl-wdr3500\nendef\nTARGET_DEVICES += tplink_tl-wdr3500-v1\n\ndefine Device/tplink_tl-wdr3600-v1\n  $(Device/tplink-8mlzma)\n  SOC := ar9344\n  DEVICE_MODEL := TL-WDR3600\n  DEVICE_VARIANT := v1\n  DEVICE_PACKAGES := kmod-usb2 kmod-usb-ledtrig-usbport\n  TPLINK_HWID := 0x36000001\n  SUPPORTED_DEVICES += tl-wdr4300\nendef\nTARGET_DEVICES += tplink_tl-wdr3600-v1\n\ndefine Device/tplink_tl-wdr4300-v1\n  $(Device/tplink-8mlzma)\n  SOC := ar9344\n  DEVICE_MODEL := TL-WDR4300\n  DEVICE_VARIANT := v1\n  DEVICE_PACKAGES := kmod-usb2 kmod-usb-ledtrig-usbport\n  TPLINK_HWID := 0x43000001\n  SUPPORTED_DEVICES += tl-wdr4300\nendef\nTARGET_DEVICES += tplink_tl-wdr4300-v1\n\ndefine Device/tplink_tl-wdr4300-v1-il\n  $(Device/tplink-8mlzma)\n  SOC := ar9344\n  DEVICE_MODEL := TL-WDR4300\n  DEVICE_VARIANT := v1 (IL)\n  DEVICE_PACKAGES := kmod-usb2 kmod-usb-ledtrig-usbport\n  TPLINK_HWID := 0x43008001\n  SUPPORTED_DEVICES += tl-wdr4300\nendef\nTARGET_DEVICES += tplink_tl-wdr4300-v1-il\n\ndefine Device/tplink_tl-wdr4310-v1\n  $(Device/tplink-8mlzma)\n  SOC := ar9344\n  DEVICE_MODEL := TL-WDR4310\n  DEVICE_VARIANT := v1\n  DEVICE_PACKAGES := kmod-usb2 kmod-usb-ledtrig-usbport\n  TPLINK_HWID := 0x43100001\n  SUPPORTED_DEVICES += tl-wdr4300\nendef\nTARGET_DEVICES += tplink_tl-wdr4310-v1\n\ndefine Device/tplink_tl-wdr4900-v2\n  $(Device/tplink-8mlzma)\n  SOC := qca9558\n  DEVICE_MODEL := TL-WDR4900\n  DEVICE_VARIANT := v2\n  DEVICE_PACKAGES := kmod-usb2 kmod-usb-ledtrig-usbport\n  TPLINK_HWID := 0x49000002\n  SUPPORTED_DEVICES += tl-wdr4900-v2\nendef\nTARGET_DEVICES += tplink_tl-wdr4900-v2\n\ndefine Device/tplink_tl-wdr7500-v3\n  $(Device/tplink-8mlzma)\n  SOC := qca9558\n  DEVICE_MODEL := TL-WDR7500\n  DEVICE_VARIANT := v3\n  DEVICE_PACKAGES := kmod-usb2 kmod-usb-ledtrig-usbport kmod-ath10k-ct \\\n\tath10k-firmware-qca988x-ct\n  TPLINK_HWID := 0x75000003\n  SUPPORTED_DEVICES += archer-c7\nendef\nTARGET_DEVICES += tplink_tl-wdr7500-v3\n\ndefine Device/tplink_tl-wpa8630-v1\n  $(Device/tplink-8mlzma)\n  SOC := qca9563\n  DEVICE_MODEL := TL-WPA8630\n  DEVICE_VARIANT := v1\n  DEVICE_PACKAGES := kmod-ath10k-ct ath10k-firmware-qca988x-ct\n  TPLINK_HWID := 0x86300001\n  SUPPORTED_DEVICES += tl-wpa8630\nendef\nTARGET_DEVICES += tplink_tl-wpa8630-v1\n\ndefine Device/tplink_tl-wr1043nd-v1\n  $(Device/tplink-8m)\n  SOC := ar9132\n  DEVICE_MODEL := TL-WR1043N/ND\n  DEVICE_VARIANT := v1\n  DEVICE_PACKAGES := kmod-usb2 kmod-usb-ledtrig-usbport\n  TPLINK_HWID := 0x10430001\n  SUPPORTED_DEVICES += tl-wr1043nd\nendef\nTARGET_DEVICES += tplink_tl-wr1043nd-v1\n\ndefine Device/tplink_tl-wr1043nd-v2\n  $(Device/tplink-8mlzma)\n  SOC := qca9558\n  DEVICE_MODEL := TL-WR1043N/ND\n  DEVICE_VARIANT := v2\n  DEVICE_PACKAGES := kmod-usb2 kmod-usb-ledtrig-usbport\n  TPLINK_HWID := 0x10430002\n  SUPPORTED_DEVICES += tl-wr1043nd-v2\nendef\nTARGET_DEVICES += tplink_tl-wr1043nd-v2\n\ndefine Device/tplink_tl-wr1043nd-v3\n  $(Device/tplink-8mlzma)\n  SOC := qca9558\n  DEVICE_MODEL := TL-WR1043N/ND\n  DEVICE_VARIANT := v3\n  DEVICE_PACKAGES := kmod-usb2 kmod-usb-ledtrig-usbport\n  TPLINK_HWID := 0x10430003\n  SUPPORTED_DEVICES += tl-wr1043nd-v2\nendef\nTARGET_DEVICES += tplink_tl-wr1043nd-v3\n\ndefine Device/tplink_tl-wr1043nd-v4\n  $(Device/tplink-safeloader)\n  SOC := qca9563\n  IMAGE_SIZE := 15552k\n  DEVICE_MODEL := TL-WR1043N/ND\n  DEVICE_VARIANT := v4\n  DEVICE_PACKAGES := kmod-usb2 kmod-usb-ledtrig-usbport\n  TPLINK_HWID := 0x10430004\n  TPLINK_HWREV := 0x1\n  TPLINK_BOARD_ID := TLWR1043NDV4\n  SUPPORTED_DEVICES += tl-wr1043nd-v4\nendef\nTARGET_DEVICES += tplink_tl-wr1043nd-v4\n\ndefine Device/tplink_tl-wr1043n-v5\n  $(Device/tplink-safeloader-uimage)\n  SOC := qca9563\n  IMAGE_SIZE := 15104k\n  DEVICE_MODEL := TL-WR1043N\n  DEVICE_VARIANT := v5\n  TPLINK_BOARD_ID := TLWR1043NV5\n  SUPPORTED_DEVICES += tl-wr1043n-v5\nendef\nTARGET_DEVICES += tplink_tl-wr1043n-v5\n\ndefine Device/tplink_tl-wr1045nd-v2\n  $(Device/tplink-8mlzma)\n  SOC := qca9558\n  DEVICE_MODEL := TL-WR1045ND\n  DEVICE_VARIANT := v2\n  DEVICE_PACKAGES := kmod-usb2 kmod-usb-ledtrig-usbport\n  TPLINK_HWID := 0x10450002\nendef\nTARGET_DEVICES += tplink_tl-wr1045nd-v2\n\ndefine Device/tplink_tl-wr2543-v1\n  $(Device/tplink-8mlzma)\n  SOC := ar7242\n  DEVICE_MODEL := TL-WR2543N/ND\n  DEVICE_VARIANT := v1\n  DEVICE_PACKAGES := kmod-usb2 kmod-usb-ledtrig-usbport\n  TPLINK_HWID := 0x25430001\n  IMAGE/sysupgrade.bin := tplink-v1-image sysupgrade -v 3.13.99 | \\\n\tcheck-size | append-metadata\n  IMAGE/factory.bin := tplink-v1-image factory -v 3.13.99\n  SUPPORTED_DEVICES += tl-wr2543n\nendef\nTARGET_DEVICES += tplink_tl-wr2543-v1\n\ndefine Device/tplink_tl-wr710n-v1\n  $(Device/tplink-8mlzma)\n  SOC := ar9331\n  DEVICE_MODEL := TL-WR710N\n  DEVICE_VARIANT := v1\n  DEVICE_PACKAGES := kmod-usb-chipidea2 kmod-usb-ledtrig-usbport\n  TPLINK_HWID := 0x07100001\n  SUPPORTED_DEVICES += tl-wr710n\nendef\nTARGET_DEVICES += tplink_tl-wr710n-v1\n\ndefine Device/tplink_tl-wr710n-v2.1\n  $(Device/tplink-8mlzma)\n  SOC := ar9331\n  DEVICE_MODEL := TL-WR710N\n  DEVICE_VARIANT := v2.1\n  DEVICE_PACKAGES := kmod-usb-chipidea2 kmod-usb-ledtrig-usbport\n  TPLINK_HWID := 0x07100002\n  TPLINK_HWREV := 0x2\n  SUPPORTED_DEVICES += tl-wr710n\nendef\nTARGET_DEVICES += tplink_tl-wr710n-v2.1\n\ndefine Device/tplink_tl-wr810n-v1\n  $(Device/tplink-8mlzma)\n  SOC := qca9531\n  DEVICE_MODEL := TL-WR810N\n  DEVICE_VARIANT := v1\n  TPLINK_HWID := 0x8100001\n  DEVICE_PACKAGES := kmod-usb2 kmod-usb-ledtrig-usbport\n  SUPPORTED_DEVICES += tl-wr810n\nendef\nTARGET_DEVICES += tplink_tl-wr810n-v1\n\ndefine Device/tplink_tl-wr810n-v2\n  $(Device/tplink-8mlzma)\n  SOC := qca9533\n  DEVICE_MODEL := TL-WR810N\n  DEVICE_VARIANT := v2\n  TPLINK_HWID := 0x8100002\n  SUPPORTED_DEVICES += tl-wr810n-v2\nendef\nTARGET_DEVICES += tplink_tl-wr810n-v2\n\ndefine Device/tplink_tl-wr841hp-v2\n  $(Device/tplink-8mlzma)\n  SOC := ar9344\n  DEVICE_MODEL := TL-WR841HP\n  DEVICE_VARIANT := v2\n  TPLINK_HWID := 0x08411002\nendef\nTARGET_DEVICES += tplink_tl-wr841hp-v2\n\ndefine Device/tplink_tl-wr841hp-v3\n  $(Device/tplink-8mlzma)\n  SOC := qca9533\n  DEVICE_MODEL := TL-WR841HP\n  DEVICE_VARIANT := v3\n  TPLINK_HWID := 0x08411003\nendef\nTARGET_DEVICES += tplink_tl-wr841hp-v3\n\ndefine Device/tplink_tl-wr842n-v1\n  $(Device/tplink-8m)\n  SOC := ar7241\n  DEVICE_MODEL := TL-WR842N/ND\n  DEVICE_VARIANT := v1\n  DEVICE_PACKAGES := kmod-usb2 kmod-usb-ledtrig-usbport\n  TPLINK_HWID := 0x8420001\n  SUPPORTED_DEVICES += tl-mr3420\nendef\nTARGET_DEVICES += tplink_tl-wr842n-v1\n\ndefine Device/tplink_tl-wr842n-v2\n  $(Device/tplink-8mlzma)\n  SOC := ar9341\n  DEVICE_MODEL := TL-WR842N/ND\n  DEVICE_VARIANT := v2\n  DEVICE_PACKAGES := kmod-usb2 kmod-usb-ledtrig-usbport\n  TPLINK_HWID := 0x8420002\n  SUPPORTED_DEVICES += tl-wr842n-v2\nendef\nTARGET_DEVICES += tplink_tl-wr842n-v2\n\ndefine Device/tplink_tl-wr842n-v3\n  $(Device/tplink-16mlzma)\n  SOC := qca9533\n  DEVICE_MODEL := TL-WR842N\n  DEVICE_VARIANT := v3\n  DEVICE_PACKAGES := kmod-usb2 kmod-usb-ledtrig-usbport\n  TPLINK_HWID := 0x8420003\n  SUPPORTED_DEVICES += tl-wr842n-v3\nendef\nTARGET_DEVICES += tplink_tl-wr842n-v3\n\ndefine Device/tplink_tl-wr902ac-v1\n  $(Device/tplink-safeloader)\n  SOC := qca9531\n  DEVICE_MODEL := TL-WR902AC\n  DEVICE_VARIANT := v1\n  DEVICE_PACKAGES := kmod-usb2 kmod-usb-ledtrig-usbport \\\n\tkmod-ath10k-ct-smallbuffers ath10k-firmware-qca9887-ct \\\n\t-swconfig -uboot-envtools\n  TPLINK_BOARD_ID := TL-WR902AC-V1\n  IMAGE_SIZE := 7360k\n  SUPPORTED_DEVICES += tl-wr902ac-v1\nendef\nTARGET_DEVICES += tplink_tl-wr902ac-v1\n\ndefine Device/tplink_tl-wr941hp-v1\n  $(Device/tplink-safeloader)\n  SOC := tp9343\n  DEVICE_MODEL := TL-WR941HP\n  DEVICE_VARIANT := v1\n  TPLINK_BOARD_ID := TL-WR941HP-V1\n  IMAGE_SIZE := 7360k\nendef\nTARGET_DEVICES += tplink_tl-wr941hp-v1\n\ndefine Device/tplink_wbs210-v1\n  $(Device/tplink-safeloader-okli)\n  SOC := ar9344\n  IMAGE_SIZE := 7680k\n  DEVICE_MODEL := WBS210\n  DEVICE_VARIANT := v1\n  DEVICE_PACKAGES := rssileds\n  TPLINK_BOARD_ID := WBS210\n  SUPPORTED_DEVICES += wbs210\nendef\nTARGET_DEVICES += tplink_wbs210-v1\n\ndefine Device/tplink_wbs210-v2\n  $(Device/tplink-safeloader-okli)\n  SOC := ar9344\n  IMAGE_SIZE := 7680k\n  DEVICE_MODEL := WBS210\n  DEVICE_VARIANT := v2\n  DEVICE_PACKAGES := rssileds\n  TPLINK_BOARD_ID := WBS210V2\nendef\nTARGET_DEVICES += tplink_wbs210-v2\n\ndefine Device/tplink_wbs510-v1\n  $(Device/tplink-safeloader-okli)\n  SOC := ar9344\n  IMAGE_SIZE := 7680k\n  DEVICE_MODEL := WBS510\n  DEVICE_VARIANT := v1\n  DEVICE_PACKAGES := rssileds\n  TPLINK_BOARD_ID := WBS510\n  SUPPORTED_DEVICES += wbs510\nendef\nTARGET_DEVICES += tplink_wbs510-v1\n\ndefine Device/tplink_wbs510-v2\n  $(Device/tplink-safeloader-okli)\n  SOC := ar9344\n  IMAGE_SIZE := 7680k\n  DEVICE_MODEL := WBS510\n  DEVICE_VARIANT := v2\n  DEVICE_PACKAGES := rssileds\n  TPLINK_BOARD_ID := WBS510V2\nendef\nTARGET_DEVICES += tplink_wbs510-v2\n"
  },
  {
    "path": "target/linux/ath79/image/generic-ubnt.mk",
    "content": "DEVICE_VARS += UBNT_BOARD UBNT_CHIP UBNT_TYPE UBNT_VERSION UBNT_REVISION\n\n# On M (XW) devices the U-Boot as of version 1.1.4-s1039 doesn't like\n# VERSION_DIST being on the place of major(?) version number, so we need to\n# use some number.\nUBNT_REVISION := $(VERSION_DIST)-$(REVISION)\n\n# mkubntimage is using the kernel image direct\n# routerboard creates partitions out of the ubnt header\ndefine Build/mkubntimage\n\t-$(STAGING_DIR_HOST)/bin/mkfwimage -B $(UBNT_BOARD) \\\n\t\t-v $(UBNT_TYPE).$(UBNT_CHIP).v6.0.0-$(VERSION_DIST)-$(REVISION) \\\n\t\t-k $(IMAGE_KERNEL) -r $@ -o $@\nendef\n\ndefine Build/mkubntimage2\n\t-$(STAGING_DIR_HOST)/bin/mkfwimage2 -f 0x9f000000 \\\n\t\t-v $(UBNT_TYPE).$(UBNT_CHIP).v6.0.0-$(VERSION_DIST)-$(REVISION) \\\n\t\t-p jffs2:0x50000:0xf60000:0:0:$@ \\\n\t\t-o $@.new\n\t@mv $@.new $@\nendef\n\n# all UBNT XM/WA devices expect the kernel image to have 1024k while flash, when\n# booting the image, the size doesn't matter.\ndefine Build/mkubntimage-split\n\t-[ -f $@ ] && ( \\\n\tdd if=$@ of=$@.old1 bs=1024k count=1; \\\n\tdd if=$@ of=$@.old2 bs=1024k skip=1; \\\n\t$(STAGING_DIR_HOST)/bin/mkfwimage -B $(UBNT_BOARD) \\\n\t\t-v $(UBNT_TYPE).$(UBNT_CHIP).v$(UBNT_VERSION)-$(UBNT_REVISION) \\\n\t\t-k $@.old1 -r $@.old2 -o $@; \\\n\trm $@.old1 $@.old2 )\nendef\n\n# UBNT_BOARD e.g. one of (XS2, XS5, RS, XM)\n# UBNT_TYPE e.g. one of (BZ, XM, XW)\n# UBNT_CHIP e.g. one of (ar7240, ar933x, ar934x)\n# UBNT_VERSION e.g. one of (6.0.0, 8.5.3)\ndefine Device/ubnt\n  DEVICE_VENDOR := Ubiquiti\n  DEVICE_PACKAGES := kmod-usb2\n  IMAGES += factory.bin\n  IMAGE/factory.bin := append-kernel | pad-to $$$$(BLOCKSIZE) | \\\n\tappend-rootfs | pad-rootfs | check-size | mkubntimage-split\nendef\n\ndefine Device/ubnt-bz\n  $(Device/ubnt)\n  SOC := ar7241\n  IMAGE_SIZE := 7448k\n  UBNT_BOARD := XM\n  UBNT_CHIP := ar7240\n  UBNT_TYPE := BZ\n  UBNT_VERSION := 6.0.0\nendef\n\ndefine Device/ubnt-sw\n  $(Device/ubnt)\n  SOC := ar7242\n  DEVICE_PACKAGES += kmod-usb-ohci\n  IMAGE_SIZE := 7552k\n  UBNT_BOARD := SW\n  UBNT_CHIP := ar7240\n  UBNT_TYPE := SW\n  UBNT_VERSION := 1.4.1\n  KERNEL := kernel-bin | append-dtb | relocate-kernel | lzma | uImage lzma\nendef\n\ndefine Device/ubnt-2wa\n  $(Device/ubnt)\n  SOC := ar9342\n  IMAGE_SIZE := 15744k\n  UBNT_BOARD := WA\n  UBNT_CHIP := ar934x\n  UBNT_TYPE := 2WA\n  UBNT_VERSION := 8.5.3\nendef\n\ndefine Device/ubnt-wa\n  $(Device/ubnt)\n  SOC := ar9342\n  IMAGE_SIZE := 15744k\n  UBNT_BOARD := WA\n  UBNT_CHIP := ar934x\n  UBNT_TYPE := WA\n  UBNT_VERSION := 8.5.3\nendef\n\ndefine Device/ubnt-xc\n  $(Device/ubnt)\n  IMAGE_SIZE := 15744k\n  UBNT_BOARD := XC\n  UBNT_CHIP := qca955x\n  UBNT_TYPE := XC\n  UBNT_VERSION := 8.5.3\nendef\n\ndefine Device/ubnt-xm\n  $(Device/ubnt)\n  DEVICE_VARIANT := XM\n  DEVICE_PACKAGES += kmod-usb-ohci\n  IMAGE_SIZE := 7448k\n  UBNT_BOARD := XM\n  UBNT_CHIP := ar7240\n  UBNT_REVISION := 42.$(UBNT_REVISION)\n  UBNT_TYPE := XM\n  UBNT_VERSION := 6.0.0\n  KERNEL := kernel-bin | append-dtb | relocate-kernel | lzma | uImage lzma\nendef\n\ndefine Device/ubnt-xw\n  $(Device/ubnt)\n  SOC := ar9342\n  DEVICE_VARIANT := XW\n  IMAGE_SIZE := 7552k\n  UBNT_BOARD := XM\n  UBNT_CHIP := ar934x\n  UBNT_REVISION := 42.$(UBNT_REVISION)\n  UBNT_TYPE := XW\n  UBNT_VERSION := 6.0.4\nendef\n\ndefine Device/ubnt-unifi-jffs2\n  $(Device/ubnt)\n  KERNEL_SIZE := 3072k\n  IMAGE_SIZE := 15744k\n  UBNT_TYPE := BZ\n  KERNEL := kernel-bin | append-dtb | lzma | uImage lzma | jffs2 kernel0\n  IMAGES := sysupgrade.bin factory.bin\n  IMAGE/sysupgrade.bin := append-kernel | pad-to $$$$(KERNEL_SIZE) | append-rootfs |\\\n\tpad-rootfs | check-size | append-metadata\n  IMAGE/factory.bin := $$(IMAGE/sysupgrade.bin) | mkubntimage2\nendef\n\ndefine Device/ubnt-acb\n  $(Device/ubnt)\n  IMAGE_SIZE := 15744k\n  UBNT_BOARD := ACB\n  UBNT_TYPE := ACB\n  UBNT_VERSION := 2.5.0\nendef\n\ndefine Device/ubnt_aircube-ac\n  $(Device/ubnt-acb)\n  SOC := ar9342\n  DEVICE_MODEL := airCube AC\n  UBNT_CHIP := ar9342\n  DEVICE_PACKAGES += kmod-ath10k-ct-smallbuffers ath10k-firmware-qca988x-ct\nendef\nTARGET_DEVICES += ubnt_aircube-ac\n\ndefine Device/ubnt_aircube-isp\n  $(Device/ubnt-acb)\n  SOC := qca9533\n  DEVICE_MODEL := airCube ISP\n  UBNT_CHIP := qca9533\n  SUPPORTED_DEVICES += ubnt,acb-isp\nendef\nTARGET_DEVICES += ubnt_aircube-isp\n\ndefine Device/ubnt_airrouter\n  $(Device/ubnt-xm)\n  SOC := ar7241\n  DEVICE_MODEL := AirRouter\n  SUPPORTED_DEVICES += airrouter\nendef\nTARGET_DEVICES += ubnt_airrouter\n\ndefine Device/ubnt_bullet-ac\n  $(Device/ubnt-2wa)\n  DEVICE_MODEL := Bullet AC\n  DEVICE_PACKAGES += kmod-ath10k-ct-smallbuffers ath10k-firmware-qca988x-ct rssileds\nendef\nTARGET_DEVICES += ubnt_bullet-ac\n\ndefine Device/ubnt_bullet-m-ar7240\n  $(Device/ubnt-xm)\n  SOC := ar7240\n  DEVICE_MODEL := Bullet M\n  DEVICE_VARIANT := XM (AR7240)\n  DEVICE_PACKAGES += rssileds\n  SUPPORTED_DEVICES += bullet-m\nendef\nTARGET_DEVICES += ubnt_bullet-m-ar7240\n\ndefine Device/ubnt_bullet-m-ar7241\n  $(Device/ubnt-xm)\n  SOC := ar7241\n  DEVICE_MODEL := Bullet M\n  DEVICE_VARIANT := XM (AR7241)\n  DEVICE_PACKAGES += rssileds\n  SUPPORTED_DEVICES += bullet-m ubnt,bullet-m\nendef\nTARGET_DEVICES += ubnt_bullet-m-ar7241\n\ndefine Device/ubnt_bullet-m-xw\n  $(Device/ubnt-xw)\n  DEVICE_MODEL := Bullet M\n  DEVICE_PACKAGES += rssileds\n  SUPPORTED_DEVICES += bullet-m-xw\nendef\nTARGET_DEVICES += ubnt_bullet-m-xw\n\ndefine Device/ubnt_edgeswitch-5xp\n  $(Device/ubnt-sw)\n  DEVICE_MODEL := EdgeSwitch 5XP\nendef\nTARGET_DEVICES += ubnt_edgeswitch-5xp\n\ndefine Device/ubnt_edgeswitch-8xp\n  $(Device/ubnt-sw)\n  DEVICE_MODEL := EdgeSwitch 8XP\n  DEVICE_PACKAGES += kmod-switch-bcm53xx-mdio\nendef\nTARGET_DEVICES += ubnt_edgeswitch-8xp\n\ndefine Device/ubnt_lap-120\n  $(Device/ubnt-wa)\n  DEVICE_MODEL := LiteAP ac (LAP-120)\n  DEVICE_PACKAGES += kmod-ath10k-ct-smallbuffers ath10k-firmware-qca988x-ct\nendef\nTARGET_DEVICES += ubnt_lap-120\n\ndefine Device/ubnt_litebeam-ac-gen2\n  $(Device/ubnt-wa)\n  DEVICE_MODEL := LiteBeam AC\n  DEVICE_VARIANT := Gen2\n  DEVICE_PACKAGES := kmod-ath10k-ct-smallbuffers ath10k-firmware-qca988x-ct\nendef\nTARGET_DEVICES += ubnt_litebeam-ac-gen2\n\ndefine Device/ubnt_nanobeam-ac\n  $(Device/ubnt-wa)\n  DEVICE_MODEL := NanoBeam AC\n  DEVICE_VARIANT := Gen1\n  DEVICE_PACKAGES += kmod-ath10k-ct-smallbuffers ath10k-firmware-qca988x-ct rssileds\nendef\nTARGET_DEVICES += ubnt_nanobeam-ac\n\ndefine Device/ubnt_nanobeam-ac-gen2\n  $(Device/ubnt-wa)\n  DEVICE_MODEL := NanoBeam AC\n  DEVICE_VARIANT := Gen2\n  DEVICE_PACKAGES += kmod-ath10k-ct-smallbuffers ath10k-firmware-qca988x-ct rssileds\nendef\nTARGET_DEVICES += ubnt_nanobeam-ac-gen2\n\ndefine Device/ubnt_nanobeam-ac-xc\n  $(Device/ubnt-xc)\n  SOC := qca9558\n  DEVICE_MODEL := NanoBeam AC\n  DEVICE_VARIANT := Gen1 (XC)\n  DEVICE_PACKAGES += kmod-ath10k-ct ath10k-firmware-qca988x-ct rssileds\nendef\nTARGET_DEVICES += ubnt_nanobeam-ac-xc\n\ndefine Device/ubnt_nanobridge-m\n  $(Device/ubnt-xm)\n  SOC := ar7241\n  DEVICE_MODEL := NanoBridge M\n  DEVICE_PACKAGES += rssileds\n  SUPPORTED_DEVICES += bullet-m\nendef\nTARGET_DEVICES += ubnt_nanobridge-m\n\ndefine Device/ubnt_nanostation-ac\n  $(Device/ubnt-wa)\n  DEVICE_MODEL := Nanostation AC\n  DEVICE_PACKAGES += kmod-ath10k-ct-smallbuffers ath10k-firmware-qca988x-ct rssileds\nendef\nTARGET_DEVICES += ubnt_nanostation-ac\n\ndefine Device/ubnt_nanostation-ac-loco\n  $(Device/ubnt-wa)\n  DEVICE_MODEL := Nanostation AC loco\n  DEVICE_PACKAGES += kmod-ath10k-ct-smallbuffers ath10k-firmware-qca988x-ct\nendef\nTARGET_DEVICES += ubnt_nanostation-ac-loco\n\ndefine Device/ubnt_nanostation-loco-m\n  $(Device/ubnt-xm)\n  SOC := ar7241\n  DEVICE_MODEL := Nanostation Loco M\n  DEVICE_PACKAGES += rssileds\n  SUPPORTED_DEVICES += bullet-m\nendef\nTARGET_DEVICES += ubnt_nanostation-loco-m\n\ndefine Device/ubnt_nanostation-loco-m-xw\n  $(Device/ubnt-xw)\n  DEVICE_MODEL := Nanostation Loco M\n  DEVICE_PACKAGES += rssileds\n  SUPPORTED_DEVICES += loco-m-xw\nendef\nTARGET_DEVICES += ubnt_nanostation-loco-m-xw\n\ndefine Device/ubnt_nanostation-m\n  $(Device/ubnt-xm)\n  SOC := ar7241\n  DEVICE_MODEL := Nanostation M\n  DEVICE_PACKAGES += rssileds\n  SUPPORTED_DEVICES += nanostation-m\nendef\nTARGET_DEVICES += ubnt_nanostation-m\n\ndefine Device/ubnt_nanostation-m-xw\n  $(Device/ubnt-xw)\n  DEVICE_MODEL := Nanostation M\n  DEVICE_PACKAGES += rssileds\n  SUPPORTED_DEVICES += nanostation-m-xw\nendef\nTARGET_DEVICES += ubnt_nanostation-m-xw\n\ndefine Device/ubnt_picostation-m\n  $(Device/ubnt-xm)\n  SOC := ar7241\n  DEVICE_MODEL := Picostation M\n  DEVICE_PACKAGES += rssileds\n  SUPPORTED_DEVICES += bullet-m\nendef\nTARGET_DEVICES += ubnt_picostation-m\n\ndefine Device/ubnt_powerbeam-5ac-500\n  $(Device/ubnt-xc)\n  SOC := qca9558\n  DEVICE_MODEL := PowerBeam 5AC\n  DEVICE_VARIANT := 500\n  DEVICE_PACKAGES := kmod-ath10k-ct ath10k-firmware-qca988x-ct\nendef\nTARGET_DEVICES += ubnt_powerbeam-5ac-500\n\ndefine Device/ubnt_powerbeam-5ac-gen2\n  $(Device/ubnt-wa)\n  DEVICE_MODEL := PowerBeam 5AC\n  DEVICE_VARIANT := Gen2\n  DEVICE_PACKAGES := kmod-ath10k-ct-smallbuffers ath10k-firmware-qca988x-ct rssileds\nendef\nTARGET_DEVICES += ubnt_powerbeam-5ac-gen2\n\ndefine Device/ubnt_powerbeam-m2-xw\n  $(Device/ubnt-xw)\n  DEVICE_MODEL := PowerBeam M2\n  DEVICE_PACKAGES += rssileds\n  SUPPORTED_DEVICES += loco-m-xw\nendef\nTARGET_DEVICES += ubnt_powerbeam-m2-xw\n\ndefine Device/ubnt_powerbeam-m5-xw\n  $(Device/ubnt-xw)\n  DEVICE_MODEL := PowerBeam M5\n  DEVICE_PACKAGES += rssileds\n  SUPPORTED_DEVICES += loco-m-xw\nendef\nTARGET_DEVICES += ubnt_powerbeam-m5-xw\n\ndefine Device/ubnt_powerbridge-m\n  $(Device/ubnt-xm)\n  SOC := ar7241\n  DEVICE_MODEL := PowerBridge M\n  DEVICE_PACKAGES += rssileds\n  SUPPORTED_DEVICES += bullet-m\nendef\nTARGET_DEVICES += ubnt_powerbridge-m\n\ndefine Device/ubnt_rocket-5ac-lite\n  $(Device/ubnt-xc)\n  SOC := qca9558\n  DEVICE_MODEL := Rocket 5AC\n  DEVICE_VARIANT := Lite\n  DEVICE_PACKAGES := kmod-ath10k-ct ath10k-firmware-qca988x-ct\nendef\nTARGET_DEVICES += ubnt_rocket-5ac-lite\n\ndefine Device/ubnt_rocket-m\n  $(Device/ubnt-xm)\n  SOC := ar7241\n  DEVICE_MODEL := Rocket M\n  DEVICE_PACKAGES += rssileds\n  SUPPORTED_DEVICES += rocket-m\nendef\nTARGET_DEVICES += ubnt_rocket-m\n\ndefine Device/ubnt_routerstation_common\n  DEVICE_PACKAGES := -kmod-ath9k -wpad-basic-wolfssl -uboot-envtools kmod-usb-ohci \\\n\tkmod-usb2 fconfig\n  DEVICE_VENDOR := Ubiquiti\n  SOC := ar7161\n  IMAGE_SIZE := 16128k\n  IMAGES += factory.bin\n  IMAGE/factory.bin := append-rootfs | pad-rootfs | mkubntimage | \\\n\tcheck-size\n  IMAGE/sysupgrade.bin := append-rootfs | pad-rootfs | combined-image | \\\n\tcheck-size | append-metadata\n  KERNEL := kernel-bin | append-dtb | lzma | pad-to $$(BLOCKSIZE)\n  KERNEL_INITRAMFS := kernel-bin | append-dtb\nendef\n\ndefine Device/ubnt_routerstation\n  $(Device/ubnt_routerstation_common)\n  DEVICE_MODEL := RouterStation\n  UBNT_BOARD := RS\n  UBNT_TYPE := RSx\n  UBNT_CHIP := ar7100\n  DEVICE_PACKAGES += -swconfig\n  SUPPORTED_DEVICES += routerstation\nendef\nTARGET_DEVICES += ubnt_routerstation\n\ndefine Device/ubnt_routerstation-pro\n  $(Device/ubnt_routerstation_common)\n  DEVICE_MODEL := RouterStation Pro\n  UBNT_BOARD := RSPRO\n  UBNT_TYPE := RSPRO\n  UBNT_CHIP := ar7100pro\n  SUPPORTED_DEVICES += routerstation-pro\nendef\nTARGET_DEVICES += ubnt_routerstation-pro\n\ndefine Device/ubnt_unifi\n  $(Device/ubnt-bz)\n  DEVICE_MODEL := UniFi AP\n  SUPPORTED_DEVICES += unifi\nendef\nTARGET_DEVICES += ubnt_unifi\n\ndefine Device/ubnt_unifiac\n  DEVICE_VENDOR := Ubiquiti\n  SOC := qca9563\n  IMAGE_SIZE := 7744k\n  DEVICE_PACKAGES := kmod-ath10k-ct ath10k-firmware-qca988x-ct\nendef\n\ndefine Device/ubnt_unifiac-lite\n  $(Device/ubnt_unifiac)\n  DEVICE_MODEL := UniFi AC Lite\n  DEVICE_PACKAGES += -swconfig\n  SUPPORTED_DEVICES += unifiac-lite\nendef\nTARGET_DEVICES += ubnt_unifiac-lite\n\ndefine Device/ubnt_unifiac-lr\n  $(Device/ubnt_unifiac)\n  DEVICE_MODEL := UniFi AC LR\n  DEVICE_PACKAGES += -swconfig\n  SUPPORTED_DEVICES += unifiac-lite ubnt,unifiac-lite\nendef\nTARGET_DEVICES += ubnt_unifiac-lr\n\ndefine Device/ubnt_unifiac-mesh\n  $(Device/ubnt_unifiac)\n  DEVICE_MODEL := UniFi AC Mesh\n  DEVICE_PACKAGES += -swconfig\n  SUPPORTED_DEVICES += unifiac-lite\nendef\nTARGET_DEVICES += ubnt_unifiac-mesh\n\ndefine Device/ubnt_unifiac-mesh-pro\n  $(Device/ubnt_unifiac)\n  DEVICE_MODEL := UniFi AC Mesh Pro\n  SUPPORTED_DEVICES += unifiac-pro\nendef\nTARGET_DEVICES += ubnt_unifiac-mesh-pro\n\ndefine Device/ubnt_unifiac-pro\n  $(Device/ubnt_unifiac)\n  DEVICE_MODEL := UniFi AC Pro\n  DEVICE_PACKAGES += kmod-usb2\n  SUPPORTED_DEVICES += unifiac-pro\nendef\nTARGET_DEVICES += ubnt_unifiac-pro\n\ndefine Device/ubnt_unifi-ap-outdoor-plus\n  $(Device/ubnt-bz)\n  $(Device/ubnt-unifi-jffs2)\n  DEVICE_MODEL := UniFi AP Outdoor+\n  SUPPORTED_DEVICES += unifi-outdoor-plus\nendef\nTARGET_DEVICES += ubnt_unifi-ap-outdoor-plus\n\ndefine Device/ubnt_unifi-ap-pro\n  $(Device/ubnt-unifi-jffs2)\n  SOC := ar9344\n  DEVICE_MODEL := UniFi AP Pro\n  UBNT_CHIP := ar934x\n  SUPPORTED_DEVICES += uap-pro\nendef\nTARGET_DEVICES += ubnt_unifi-ap-pro\n"
  },
  {
    "path": "target/linux/ath79/image/generic.mk",
    "content": "include ./common-buffalo.mk\ninclude ./common-netgear.mk\ninclude ./common-senao.mk\ninclude ./common-tp-link.mk\ninclude ./common-yuncore.mk\n\nDEVICE_VARS += ADDPATTERN_ID ADDPATTERN_VERSION\nDEVICE_VARS += SEAMA_SIGNATURE SEAMA_MTDBLOCK\nDEVICE_VARS += KERNEL_INITRAMFS_PREFIX DAP_SIGNATURE\nDEVICE_VARS += EDIMAX_HEADER_MAGIC EDIMAX_HEADER_MODEL\nDEVICE_VARS += OPENMESH_CE_TYPE\n\ndefine Build/add-elecom-factory-initramfs\n  $(eval edimax_model=$(word 1,$(1)))\n  $(eval product=$(word 2,$(1)))\n\n  $(STAGING_DIR_HOST)/bin/mkedimaximg \\\n\t-b -s CSYS -m $(edimax_model) \\\n\t-f 0x70000 -S 0x01100000 \\\n\t-i $@ -o $@.factory\n\n  $(call Build/elecom-product-header,$(product) $@.factory)\n\n  if [ \"$$(stat -c%s $@.factory)\" -le $$(($(subst k,* 1024,$(subst m, * 1024k,$(IMAGE_SIZE))))) ]; then \\\n\tmv $@.factory $(BIN_DIR)/$(KERNEL_INITRAMFS_PREFIX)-factory.bin; \\\n  else \\\n\techo \"WARNING: initramfs kernel image too big, cannot generate factory image\" >&2; \\\n  fi\nendef\n\ndefine Build/addpattern\n\t-$(STAGING_DIR_HOST)/bin/addpattern -B $(ADDPATTERN_ID) \\\n\t\t-v v$(ADDPATTERN_VERSION) -i $@ -o $@.new\n\t-mv \"$@.new\" \"$@\"\nendef\n\ndefine Build/append-md5sum-bin\n\t$(MKHASH) md5 $@ | sed 's/../\\\\\\\\x&/g' |\\\n\t\txargs echo -ne >> $@\nendef\n\ndefine Build/cybertan-trx\n\t@echo -n '' > $@-empty.bin\n\t-$(STAGING_DIR_HOST)/bin/trx -o $@.new \\\n\t\t-f $(IMAGE_KERNEL) -F $@-empty.bin \\\n\t\t-x 32 -a 0x10000 -x -32 -f $@\n\t-mv \"$@.new\" \"$@\"\n\t-rm $@-empty.bin\nendef\n\ndefine Build/edimax-headers\n\t$(eval edimax_magic=$(word 1,$(1)))\n\t$(eval edimax_model=$(word 2,$(1)))\n\n\t$(STAGING_DIR_HOST)/bin/edimax_fw_header -M $(edimax_magic) -m $(edimax_model)\\\n\t\t-v $(VERSION_DIST)$(firstword $(subst +, , $(firstword $(subst -, ,$(REVISION))))) \\\n\t\t-n \"uImage\" \\\n\t\t-i $(KDIR)/loader-$(DEVICE_NAME).uImage \\\n\t\t-o $@.uImage\n\t$(STAGING_DIR_HOST)/bin/edimax_fw_header -M $(edimax_magic) -m $(edimax_model)\\\n\t\t-v $(VERSION_DIST)$(firstword $(subst +, , $(firstword $(subst -, ,$(REVISION))))) \\\n\t\t-n \"rootfs\" \\\n\t\t-i $@ \\\n\t\t-o $@.rootfs\n\tcat $@.uImage $@.rootfs > $@\n\trm -rf $@.uImage $@.rootfs\nendef\n\ndefine Build/mkdapimg2\n\t$(STAGING_DIR_HOST)/bin/mkdapimg2 \\\n\t\t-i $@ -o $@.new \\\n\t\t-s $(DAP_SIGNATURE) \\\n\t\t-v $(VERSION_DIST)-$(firstword $(subst +, , \\\n\t\t\t$(firstword $(subst -, ,$(REVISION))))) \\\n\t\t-r Default \\\n\t\t$(if $(1),-k $(1))\n\tmv $@.new $@\nendef\n\ndefine Build/mkmylofw_16m\n\t$(eval device_id=$(word 1,$(1)))\n\t$(eval revision=$(word 2,$(1)))\n\n\t# On WPJ344, WPJ531, and WPJ563, the default boot command tries 0x9f680000\n\t# first and fails if the remains of the stock image are sill there\n\t# - resulting in an infinite boot loop.\n\t# The size parameter is grown to have that block deleted if the firmware\n\t# isn't big enough by itself.\n\n\tlet \\\n\t\tsize=\"$$(stat -c%s $@)\" \\\n\t\tpad=\"$(subst k,* 1024,$(BLOCKSIZE))\" \\\n\t\tpad=\"(pad - (size % pad)) % pad\" \\\n\t\tnewsize='size + pad' ; \\\n\t\t[ $$newsize -lt $$((0x660000)) ] && newsize=0x660000 ; \\\n\t\t$(STAGING_DIR_HOST)/bin/mkmylofw \\\n\t\t\t-B WPE72 -i 0x11f6:$(device_id):0x11f6:$(device_id) -r $(revision) \\\n\t\t\t-s 0x1000000 -p0x30000:$$newsize:al:0x80060000:\"OpenWRT\":$@ \\\n\t\t\t$@.new\n\t\t@mv $@.new $@\nendef\n\ndefine Build/mkwrggimg\n\t$(STAGING_DIR_HOST)/bin/mkwrggimg -b \\\n\t\t-i $@ -o $@.imghdr -d /dev/mtdblock/1 \\\n\t\t-m $(DEVICE_MODEL)-$(DEVICE_VARIANT) -s $(DAP_SIGNATURE) \\\n\t\t-v $(VERSION_DIST) -B $(REVISION)\n\tmv $@.imghdr $@\nendef\n\ndefine Build/nec-enc\n  $(STAGING_DIR_HOST)/bin/nec-enc \\\n    -i $@ -o $@.new -k $(1)\n  mv $@.new $@\nendef\n\ndefine Build/nec-fw\n  ( stat -c%s $@ | tr -d \"\\n\" | dd bs=16 count=1 conv=sync; ) >> $@\n  ( \\\n    echo -n -e \"$(1)\" | dd bs=16 count=1 conv=sync; \\\n    echo -n \"0.0.00\" | dd bs=16 count=1 conv=sync; \\\n    dd if=$@; \\\n  ) > $@.new\n  mv $@.new $@\nendef\n\ndefine Build/pisen_wmb001n-factory\n  -[ -f \"$@\" ] && \\\n  mkdir -p \"$@.tmp\" && \\\n  cp \"$(KDIR)/loader-$(word 1,$(1)).uImage\" \"$@.tmp/uImage\" && \\\n  mv \"$@\" \"$@.tmp/rootfs\" && \\\n  cp \"bin/pisen_wmb001n_factory-header.bin\" \"$@\" && \\\n  $(TAR) -cp --numeric-owner --owner=0 --group=0 --mode=a-s --sort=name \\\n    $(if $(SOURCE_DATE_EPOCH),--mtime=\"@$(SOURCE_DATE_EPOCH)\") \\\n    -C \"$@.tmp\" . | gzip -9n >> \"$@\" && \\\n  rm -rf \"$@.tmp\"\nendef\n\ndefine Build/teltonika-fw-fake-checksum\n\t# Teltonika U-Boot web based firmware upgrade/recovery routine compares\n\t# 16 bytes from md5sum1[16] field in TP-Link v1 header (offset: 76 bytes\n\t# from begin of the firmware file) with 16 bytes stored just before\n\t# 0xdeadc0de marker. Values are only compared, MD5 sum is not verified.\n\tlet \\\n\t\toffs=\"$$(stat -c%s $@) - $(1)\"; \\\n\t\tdd if=$@ bs=1 count=16 skip=76 |\\\n\t\tdd of=$@ bs=1 count=16 seek=$$offs conv=notrunc\nendef\n\ndefine Build/teltonika-v1-header\n\t$(STAGING_DIR_HOST)/bin/mktplinkfw \\\n\t\t-c -H $(TPLINK_HWID) -W $(TPLINK_HWREV) -L $(KERNEL_LOADADDR) \\\n\t\t-E $(if $(KERNEL_ENTRY),$(KERNEL_ENTRY),$(KERNEL_LOADADDR)) \\\n\t\t-m $(TPLINK_HEADER_VERSION) -N \"$(VERSION_DIST)\" -V \"RUT2xx      \" \\\n\t\t-k $@ -o $@.new $(1)\n\t@mv $@.new $@\nendef\n\ndefine Build/wrgg-pad-rootfs\n\t$(STAGING_DIR_HOST)/bin/padjffs2 $(IMAGE_ROOTFS) -c 64 >>$@\nendef\n\n\ndefine Device/seama\n  KERNEL := kernel-bin | append-dtb | relocate-kernel | lzma\n  KERNEL_INITRAMFS := $$(KERNEL) | seama\n  IMAGES += factory.bin\n  SEAMA_MTDBLOCK := 1\n\n  # 64 bytes offset:\n  # - 28 bytes seama_header\n  # - 36 bytes of META data (4-bytes aligned)\n  IMAGE/default := append-kernel | pad-offset $$$$(BLOCKSIZE) 64 | append-rootfs\n  IMAGE/sysupgrade.bin := $$(IMAGE/default) | seama | pad-rootfs | \\\n\tcheck-size | append-metadata\n  IMAGE/factory.bin := $$(IMAGE/default) | pad-rootfs -x 64 | seama | \\\n\tseama-seal | check-size\n  SEAMA_SIGNATURE :=\nendef\n\n\ndefine Device/8dev_carambola2\n  SOC := ar9331\n  DEVICE_VENDOR := 8devices\n  DEVICE_MODEL := Carambola2\n  DEVICE_PACKAGES := kmod-usb-chipidea2\n  IMAGE_SIZE := 16000k\n  SUPPORTED_DEVICES += carambola2\nendef\nTARGET_DEVICES += 8dev_carambola2\n\ndefine Device/8dev_lima\n  SOC := qca9531\n  DEVICE_VENDOR := 8devices\n  DEVICE_MODEL := Lima\n  DEVICE_PACKAGES := kmod-usb2\n  IMAGE_SIZE := 15616k\n  SUPPORTED_DEVICES += lima\nendef\nTARGET_DEVICES += 8dev_lima\n\ndefine Device/adtran_bsap1880\n  SOC := ar7161\n  DEVICE_VENDOR := Adtran/Bluesocket\n  DEVICE_PACKAGES += -swconfig -uboot-envtools fconfig\n  KERNEL := kernel-bin | append-dtb | lzma | pad-to $$(BLOCKSIZE)\n  KERNEL_INITRAMFS := kernel-bin | append-dtb\n  IMAGE_SIZE := 11200k\n  IMAGES += kernel.bin rootfs.bin\n  IMAGE/kernel.bin := append-kernel\n  IMAGE/rootfs.bin := append-rootfs | pad-rootfs\n  IMAGE/sysupgrade.bin := append-rootfs | pad-rootfs | \\\n\tcheck-size | sysupgrade-tar rootfs=$$$$@ | append-metadata\nendef\n\ndefine Device/adtran_bsap1800-v2\n  $(Device/adtran_bsap1880)\n  DEVICE_MODEL := BSAP-1800\n  DEVICE_VARIANT := v2\nendef\nTARGET_DEVICES += adtran_bsap1800-v2\n\ndefine Device/adtran_bsap1840\n  $(Device/adtran_bsap1880)\n  DEVICE_MODEL := BSAP-1840\nendef\nTARGET_DEVICES += adtran_bsap1840\n\ndefine Device/airtight_c-75\n  SOC := qca9550\n  DEVICE_VENDOR := AirTight Networks\n  DEVICE_MODEL := C-75\n  DEVICE_ALT0_VENDOR := Mojo Networks\n  DEVICE_ALT0_MODEL := C-75\n  DEVICE_ALT1_VENDOR := WatchGuard\n  DEVICE_ALT1_MODEL := AP320\n  DEVICE_PACKAGES := ath10k-firmware-qca988x-ct kmod-ath10k-ct kmod-usb2\n  IMAGE_SIZE := 32320k\n  KERNEL_SIZE := 15936k\nendef\nTARGET_DEVICES += airtight_c-75\n\ndefine Device/alfa-network_ap121f\n  SOC := ar9331\n  DEVICE_VENDOR := ALFA Network\n  DEVICE_MODEL := AP121F\n  DEVICE_PACKAGES := kmod-usb-chipidea2 kmod-usb-storage -swconfig\n  IMAGE_SIZE := 16064k\n  SUPPORTED_DEVICES += ap121f\nendef\nTARGET_DEVICES += alfa-network_ap121f\n\ndefine Device/alfa-network_ap121fe\n  SOC := ar9331\n  DEVICE_VENDOR := ALFA Network\n  DEVICE_MODEL := AP121FE\n  DEVICE_PACKAGES := kmod-usb-chipidea2 kmod-usb-gadget-eth -swconfig\n  IMAGE_SIZE := 16064k\nendef\nTARGET_DEVICES += alfa-network_ap121fe\n\ndefine Device/alfa-network_n2q\n  SOC := qca9531\n  DEVICE_VENDOR := ALFA Network\n  DEVICE_MODEL := N2Q\n  DEVICE_PACKAGES := kmod-i2c-gpio kmod-gpio-pcf857x kmod-usb2 \\\n\tkmod-usb-ledtrig-usbport rssileds\n  IMAGE_SIZE := 15872k\nendef\nTARGET_DEVICES += alfa-network_n2q\n\ndefine Device/alfa-network_n5q\n  SOC := ar9344\n  DEVICE_VENDOR := ALFA Network\n  DEVICE_MODEL := N5Q\n  DEVICE_PACKAGES := rssileds\n  IMAGE_SIZE := 15872k\n  SUPPORTED_DEVICES += n5q\nendef\nTARGET_DEVICES += alfa-network_n5q\n\ndefine Device/alfa-network_pi-wifi4\n  SOC := qca9531\n  DEVICE_VENDOR := ALFA Network\n  DEVICE_MODEL := Pi-WiFi4\n  DEVICE_PACKAGES := kmod-usb2 kmod-usb-ledtrig-usbport -swconfig\n  IMAGE_SIZE := 15872k\nendef\nTARGET_DEVICES += alfa-network_pi-wifi4\n\ndefine Device/alfa-network_r36a\n  SOC := qca9531\n  DEVICE_VENDOR := ALFA Network\n  DEVICE_MODEL := R36A\n  DEVICE_PACKAGES := kmod-usb2 kmod-usb-ledtrig-usbport\n  IMAGE_SIZE := 15872k\n  SUPPORTED_DEVICES += r36a\nendef\nTARGET_DEVICES += alfa-network_r36a\n\ndefine Device/alfa-network_tube-2hq\n  SOC := qca9531\n  DEVICE_VENDOR := ALFA Network\n  DEVICE_MODEL := Tube-2HQ\n  DEVICE_PACKAGES := rssileds -swconfig\n  IMAGE_SIZE := 15872k\n  SUPPORTED_DEVICES += tube-2hq\nendef\nTARGET_DEVICES += alfa-network_tube-2hq\n\ndefine Device/allnet_all-wap02860ac\n  $(Device/senao_loader_okli)\n  SOC := qca9558\n  DEVICE_VENDOR := ALLNET\n  DEVICE_MODEL := ALL-WAP02860AC\n  DEVICE_PACKAGES := ath10k-firmware-qca988x-ct kmod-ath10k-ct\n  IMAGE_SIZE := 11584k\n  LOADER_FLASH_OFFS := 0x220000\n  SENAO_IMGNAME := senao-allwap02860ac\nendef\nTARGET_DEVICES += allnet_all-wap02860ac\n\ndefine Device/araknis_an-300-ap-i-n\n  $(Device/senao_loader_okli)\n  SOC := ar9344\n  DEVICE_VENDOR := Araknis\n  DEVICE_MODEL := AN-300-AP-I-N\n  IMAGE_SIZE := 12096k\n  LOADER_FLASH_OFFS := 0x220000\n  SENAO_IMGNAME := senao-an300\nendef\nTARGET_DEVICES += araknis_an-300-ap-i-n\n\ndefine Device/araknis_an-500-ap-i-ac\n  $(Device/senao_loader_okli)\n  SOC := qca9557\n  DEVICE_VENDOR := Araknis\n  DEVICE_MODEL := AN-500-AP-I-AC\n  DEVICE_PACKAGES := ath10k-firmware-qca988x-ct kmod-ath10k-ct\n  IMAGE_SIZE := 11584k\n  LOADER_FLASH_OFFS := 0x220000\n  SENAO_IMGNAME := senao-generic-v1-an500\nendef\nTARGET_DEVICES += araknis_an-500-ap-i-ac\n\ndefine Device/araknis_an-700-ap-i-ac\n  $(Device/senao_loader_okli)\n  SOC := qca9558\n  DEVICE_VENDOR := Araknis\n  DEVICE_MODEL := AN-700-AP-I-AC\n  DEVICE_PACKAGES := ath10k-firmware-qca988x-ct kmod-ath10k-ct\n  IMAGE_SIZE := 11584k\n  LOADER_FLASH_OFFS := 0x220000\n  SENAO_IMGNAME := senao-generic-v1-an700\nendef\nTARGET_DEVICES += araknis_an-700-ap-i-ac\n\ndefine Device/arduino_yun\n  SOC := ar9331\n  DEVICE_VENDOR := Arduino\n  DEVICE_MODEL := Yun\n  DEVICE_PACKAGES := kmod-usb-chipidea2 kmod-usb-ledtrig-usbport \\\n\tkmod-usb-storage block-mount -swconfig\n  IMAGE_SIZE := 15936k\n  SUPPORTED_DEVICES += arduino-yun\nendef\nTARGET_DEVICES += arduino_yun\n\ndefine Device/aruba_ap-105\n  SOC := ar7161\n  DEVICE_VENDOR := Aruba\n  DEVICE_MODEL := AP-105\n  IMAGE_SIZE := 16000k\n  DEVICE_PACKAGES := kmod-i2c-gpio kmod-tpm-i2c-atmel\nendef\nTARGET_DEVICES += aruba_ap-105\n\ndefine Device/asus_rp-ac66\n  SOC := qca9563\n  DEVICE_VENDOR := ASUS\n  DEVICE_MODEL := RP-AC66\n  IMAGE_SIZE := 16000k\n  IMAGES += factory.bin\n  IMAGE/factory.bin := append-kernel | pad-to $$$$(BLOCKSIZE) | \\\n\tappend-rootfs | pad-rootfs\n  DEVICE_PACKAGES := kmod-ath10k-ct-smallbuffers ath10k-firmware-qca988x-ct \\\n\trssileds -swconfig\nendef\nTARGET_DEVICES += asus_rp-ac66\n\ndefine Device/atheros_db120\n  $(Device/loader-okli-uimage)\n  SOC := ar9344\n  DEVICE_VENDOR := Atheros\n  DEVICE_MODEL := DB120\n  DEVICE_PACKAGES := kmod-usb2\n  IMAGE_SIZE := 7808k\n  SUPPORTED_DEVICES += db120\n  LOADER_FLASH_OFFS := 0x50000\n  KERNEL := kernel-bin | append-dtb | lzma | uImage lzma -M 0x4f4b4c49\n  IMAGES += factory.bin\n  IMAGE/factory.bin := append-kernel | pad-to $$$$(BLOCKSIZE) | \\\n\tappend-rootfs | pad-rootfs | check-size | pad-to 6336k | \\\n\tappend-loader-okli-uimage $(1) | pad-to 64k\nendef\nTARGET_DEVICES += atheros_db120\n\ndefine Device/avm\n  DEVICE_VENDOR := AVM\n  KERNEL := kernel-bin | append-dtb | lzma | eva-image\n  KERNEL_INITRAMFS := $$(KERNEL)\n  IMAGE/sysupgrade.bin := append-kernel | pad-to 64k | \\\n\tappend-squashfs-fakeroot-be | pad-to 256 | append-rootfs | pad-rootfs | \\\n\tcheck-size | append-metadata\n  DEVICE_PACKAGES := fritz-tffs\nendef\n\ndefine Device/avm_fritz1750e\n  $(Device/avm)\n  SOC := qca9556\n  IMAGE_SIZE := 15232k\n  DEVICE_MODEL := FRITZ!WLAN Repeater 1750E\n  DEVICE_PACKAGES += rssileds kmod-ath10k-ct-smallbuffers \\\n\tath10k-firmware-qca988x-ct -swconfig\nendef\nTARGET_DEVICES += avm_fritz1750e\n\ndefine Device/avm_fritz300e\n  $(Device/avm)\n  SOC := ar7242\n  IMAGE_SIZE := 15232k\n  DEVICE_MODEL := FRITZ!WLAN Repeater 300E\n  DEVICE_PACKAGES += rssileds -swconfig\n  SUPPORTED_DEVICES += fritz300e\nendef\nTARGET_DEVICES += avm_fritz300e\n\ndefine Device/avm_fritz4020\n  $(Device/avm)\n  SOC := qca9561\n  IMAGE_SIZE := 15232k\n  DEVICE_MODEL := FRITZ!Box 4020\n  SUPPORTED_DEVICES += fritz4020\nendef\nTARGET_DEVICES += avm_fritz4020\n\ndefine Device/avm_fritz450e\n  $(Device/avm)\n  SOC := qca9556\n  IMAGE_SIZE := 15232k\n  DEVICE_MODEL := FRITZ!WLAN Repeater 450E\n  SUPPORTED_DEVICES += fritz450e\nendef\nTARGET_DEVICES += avm_fritz450e\n\ndefine Device/avm_fritzdvbc\n  $(Device/avm)\n  SOC := qca9556\n  IMAGE_SIZE := 15232k\n  DEVICE_MODEL := FRITZ!WLAN Repeater DVB-C\n  DEVICE_PACKAGES += rssileds kmod-ath10k-ct-smallbuffers \\\n\tath10k-firmware-qca988x-ct -swconfig\nendef\nTARGET_DEVICES += avm_fritzdvbc\n\ndefine Device/belkin_f9x-v2\n  $(Device/loader-okli-uimage)\n  SOC := qca9558\n  DEVICE_VENDOR := Belkin\n  IMAGE_SIZE := 14464k\n  DEVICE_PACKAGES += kmod-ath10k-ct ath10k-firmware-qca988x-ct kmod-usb2 \\\n\tkmod-usb3 kmod-usb-ledtrig-usbport\n  LOADER_FLASH_OFFS := 0x50000\n  KERNEL := kernel-bin | append-dtb | lzma | uImage lzma -M 0x4f4b4c49\n  IMAGES += factory.bin\n  IMAGE/factory.bin := append-kernel | pad-to $$$$(BLOCKSIZE) | \\\n\tappend-rootfs | pad-rootfs | check-size | \\\n\tedimax-headers $$$$(EDIMAX_HEADER_MAGIC) $$$$(EDIMAX_HEADER_MODEL) | \\\n\tpad-to $$$$(BLOCKSIZE)\nendef\n\ndefine Device/belkin_f9j1108-v2\n  $(Device/belkin_f9x-v2)\n  DEVICE_MODEL := F9J1108 v2 (AC1750 DB Wi-Fi)\n  EDIMAX_HEADER_MAGIC := F9J1108v1\n  EDIMAX_HEADER_MODEL := BR-6679BAC\nendef\nTARGET_DEVICES += belkin_f9j1108-v2\n\ndefine Device/belkin_f9k1115-v2\n  $(Device/belkin_f9x-v2)\n  DEVICE_MODEL := F9K1115 v2 (AC1750 DB Wi-Fi)\n  EDIMAX_HEADER_MAGIC := eDiMaX\n  EDIMAX_HEADER_MODEL := F9K1115V2\nendef\nTARGET_DEVICES += belkin_f9k1115-v2\n\ndefine Device/buffalo_bhr-4grv\n  $(Device/buffalo_common)\n  SOC := ar7242\n  DEVICE_MODEL := BHR-4GRV\n  BUFFALO_PRODUCT := BHR-4GRV\n  DEVICE_PACKAGES := kmod-usb2 kmod-usb-ledtrig-usbport\n  IMAGE_SIZE := 32256k\n  SUPPORTED_DEVICES += wzr-hp-g450h\nendef\nTARGET_DEVICES += buffalo_bhr-4grv\n\ndefine Device/buffalo_bhr-4grv2\n  SOC := qca9557\n  DEVICE_VENDOR := Buffalo\n  DEVICE_MODEL := BHR-4GRV2\n  IMAGE_SIZE := 16000k\nendef\nTARGET_DEVICES += buffalo_bhr-4grv2\n\ndefine Device/buffalo_wzr_ar7161\n  $(Device/buffalo_common)\n  SOC := ar7161\n  BUFFALO_PRODUCT := WZR-HP-AG300H\n  DEVICE_PACKAGES := kmod-usb-ohci kmod-usb2 kmod-usb-ledtrig-usbport \\\n\tkmod-leds-reset kmod-owl-loader\n  IMAGE_SIZE := 32320k\n  SUPPORTED_DEVICES += wzr-hp-ag300h\nendef\n\ndefine Device/buffalo_wzr-600dhp\n  $(Device/buffalo_wzr_ar7161)\n  DEVICE_MODEL := WZR-600DHP\nendef\nTARGET_DEVICES += buffalo_wzr-600dhp\n\ndefine Device/buffalo_wzr-hp-ag300h\n  $(Device/buffalo_wzr_ar7161)\n  DEVICE_MODEL := WZR-HP-AG300H\nendef\nTARGET_DEVICES += buffalo_wzr-hp-ag300h\n\ndefine Device/buffalo_wzr-hp-g300nh\n  $(Device/buffalo_common)\n  SOC := ar9132\n  BUFFALO_PRODUCT := WZR-HP-G300NH\n  BUFFALO_HWVER := 1\n  DEVICE_PACKAGES := kmod-gpio-cascade kmod-mux-gpio kmod-usb2 kmod-usb-ledtrig-usbport\n  BLOCKSIZE := 128k\n  IMAGE_SIZE := 32128k\n  SUPPORTED_DEVICES += wzr-hp-g300nh\nendef\n\ndefine Device/buffalo_wzr-hp-g300nh-rb\n  $(Device/buffalo_wzr-hp-g300nh)\n  DEVICE_MODEL := WZR-HP-G300NH (RTL8366RB switch)\nendef\nTARGET_DEVICES += buffalo_wzr-hp-g300nh-rb\n\ndefine Device/buffalo_wzr-hp-g300nh-s\n  $(Device/buffalo_wzr-hp-g300nh)\n  DEVICE_MODEL := WZR-HP-G300NH (RTL8366S switch)\nendef\nTARGET_DEVICES += buffalo_wzr-hp-g300nh-s\n\ndefine Device/buffalo_wzr-hp-g302h-a1a0\n  $(Device/buffalo_common)\n  SOC := ar7242\n  DEVICE_MODEL := WZR-HP-G302H\n  DEVICE_VARIANT := A1A0\n  BUFFALO_PRODUCT := WZR-HP-G302H\n  BUFFALO_HWVER := 4\n  DEVICE_PACKAGES := kmod-usb2 kmod-usb-ledtrig-usbport\n  IMAGE_SIZE := 32128k\n  SUPPORTED_DEVICES += wzr-hp-g300nh2\nendef\nTARGET_DEVICES += buffalo_wzr-hp-g302h-a1a0\n\ndefine Device/buffalo_wzr-hp-g450h\n  $(Device/buffalo_common)\n  SOC := ar7242\n  DEVICE_MODEL := WZR-HP-G450H/WZR-450HP\n  BUFFALO_PRODUCT := WZR-HP-G450H\n  DEVICE_PACKAGES := kmod-usb2 kmod-usb-ledtrig-usbport\n  IMAGE_SIZE := 32256k\n  SUPPORTED_DEVICES += wzr-hp-g450h\nendef\nTARGET_DEVICES += buffalo_wzr-hp-g450h\n\ndefine Device/comfast_cf-e110n-v2\n  SOC := qca9533\n  DEVICE_VENDOR := COMFAST\n  DEVICE_MODEL := CF-E110N\n  DEVICE_VARIANT := v2\n  DEVICE_PACKAGES := rssileds -swconfig -uboot-envtools\n  IMAGE_SIZE := 16192k\nendef\nTARGET_DEVICES += comfast_cf-e110n-v2\n\ndefine Device/comfast_cf-e120a-v3\n  SOC := ar9344\n  DEVICE_VENDOR := COMFAST\n  DEVICE_MODEL := CF-E120A\n  DEVICE_VARIANT := v3\n  DEVICE_PACKAGES := rssileds -uboot-envtools\n  IMAGE_SIZE := 8000k\nendef\nTARGET_DEVICES += comfast_cf-e120a-v3\n\ndefine Device/comfast_cf-e130n-v2\n  SOC := qca9531\n  DEVICE_VENDOR := COMFAST\n  DEVICE_MODEL := CF-E130N\n  DEVICE_VARIANT := v2\n  DEVICE_PACKAGES := rssileds -swconfig -uboot-envtools\n  IMAGE_SIZE := 7936k\nendef\nTARGET_DEVICES += comfast_cf-e130n-v2\n\ndefine Device/comfast_cf-e313ac\n  SOC := qca9531\n  DEVICE_VENDOR := COMFAST\n  DEVICE_MODEL := CF-E313AC\n  DEVICE_PACKAGES := rssileds kmod-ath10k-ct-smallbuffers \\\n\tath10k-firmware-qca9888-ct -swconfig -uboot-envtools\n  IMAGE_SIZE := 7936k\nendef\nTARGET_DEVICES += comfast_cf-e313ac\n\ndefine Device/comfast_cf-e314n-v2\n  SOC := qca9531\n  DEVICE_VENDOR := COMFAST\n  DEVICE_MODEL := CF-E314N\n  DEVICE_VARIANT := v2\n  DEVICE_PACKAGES := rssileds\n  IMAGE_SIZE := 7936k\nendef\nTARGET_DEVICES += comfast_cf-e314n-v2\n\ndefine Device/comfast_cf-e375ac\n  SOC := qca9563\n  DEVICE_VENDOR := COMFAST\n  DEVICE_MODEL := CF-E375AC\n  DEVICE_PACKAGES := kmod-ath10k-ct \\\n\tath10k-firmware-qca9888-ct -uboot-envtools\n  IMAGE_SIZE := 16000k\nendef\nTARGET_DEVICES += comfast_cf-e375ac\n\ndefine Device/comfast_cf-e5\n  SOC := qca9531\n  DEVICE_VENDOR := COMFAST\n  DEVICE_MODEL := CF-E5/E7\n  DEVICE_PACKAGES := rssileds kmod-usb2 kmod-usb-net-qmi-wwan -swconfig \\\n\t-uboot-envtools\n  IMAGE_SIZE := 16192k\nendef\nTARGET_DEVICES += comfast_cf-e5\n\ndefine Device/comfast_cf-e560ac\n  SOC := qca9531\n  DEVICE_VENDOR := COMFAST\n  DEVICE_MODEL := CF-E560AC\n  DEVICE_PACKAGES := kmod-usb2 kmod-ath10k-ct ath10k-firmware-qca9888-ct\n  IMAGE_SIZE := 16128k\nendef\nTARGET_DEVICES += comfast_cf-e560ac\n\ndefine Device/comfast_cf-ew72\n  SOC := qca9531\n  DEVICE_VENDOR := COMFAST\n  DEVICE_MODEL := CF-EW72\n  DEVICE_PACKAGES := kmod-usb2 kmod-ath10k-ct ath10k-firmware-qca9888-ct \\\n\t-uboot-envtools -swconfig\n  IMAGE_SIZE := 16192k\nendef\nTARGET_DEVICES += comfast_cf-ew72\n\ndefine Device/comfast_cf-wr650ac-v1\n  SOC := qca9558\n  DEVICE_VENDOR := COMFAST\n  DEVICE_MODEL := CF-WR650AC\n  DEVICE_VARIANT := v1\n  DEVICE_PACKAGES := kmod-ath10k-ct ath10k-firmware-qca988x-ct\n  IMAGE_SIZE := 16128k\nendef\nTARGET_DEVICES += comfast_cf-wr650ac-v1\n\ndefine Device/comfast_cf-wr650ac-v2\n  SOC := qca9558\n  DEVICE_VENDOR := COMFAST\n  DEVICE_MODEL := CF-WR650AC\n  DEVICE_VARIANT := v2\n  DEVICE_PACKAGES := kmod-ath10k-ct ath10k-firmware-qca988x-ct\n  IMAGE_SIZE := 16000k\nendef\nTARGET_DEVICES += comfast_cf-wr650ac-v2\n\ndefine Device/comfast_cf-wr752ac-v1\n  SOC := qca9531\n  DEVICE_VENDOR := COMFAST\n  DEVICE_MODEL := CF-WR752AC\n  DEVICE_VARIANT := v1\n  DEVICE_PACKAGES := kmod-usb2 kmod-ath10k-ct ath10k-firmware-qca9888-ct \\\n\t-uboot-envtools\n  IMAGE_SIZE := 16192k\nendef\nTARGET_DEVICES += comfast_cf-wr752ac-v1\n\ndefine Device/compex_wpj344-16m\n  SOC := ar9344\n  DEVICE_PACKAGES := kmod-usb2\n  IMAGE_SIZE := 16128k\n  DEVICE_VENDOR := Compex\n  DEVICE_MODEL := WPJ344\n  DEVICE_VARIANT := 16M\n  SUPPORTED_DEVICES += wpj344\n  IMAGES += cpximg-6a08.bin\n  IMAGE/cpximg-6a08.bin := append-kernel | pad-to $$$$(BLOCKSIZE) | append-rootfs | pad-rootfs | mkmylofw_16m 0x690 3\nendef\nTARGET_DEVICES += compex_wpj344-16m\n\ndefine Device/compex_wpj531-16m\n  SOC := qca9531\n  DEVICE_PACKAGES := kmod-usb2\n  IMAGE_SIZE := 16128k\n  DEVICE_VENDOR := Compex\n  DEVICE_MODEL := WPJ531\n  DEVICE_VARIANT := 16M\n  SUPPORTED_DEVICES += wpj531\n  IMAGES += cpximg-7a03.bin cpximg-7a04.bin cpximg-7a06.bin cpximg-7a07.bin\n  IMAGE/cpximg-7a03.bin := append-kernel | pad-to $$$$(BLOCKSIZE) | append-rootfs | pad-rootfs | mkmylofw_16m 0x68a 2\n  IMAGE/cpximg-7a04.bin := append-kernel | pad-to $$$$(BLOCKSIZE) | append-rootfs | pad-rootfs | mkmylofw_16m 0x693 3\n  IMAGE/cpximg-7a06.bin := append-kernel | pad-to $$$$(BLOCKSIZE) | append-rootfs | pad-rootfs | mkmylofw_16m 0x693 3\n  IMAGE/cpximg-7a07.bin := append-kernel | pad-to $$$$(BLOCKSIZE) | append-rootfs | pad-rootfs | mkmylofw_16m 0x693 3\nendef\nTARGET_DEVICES += compex_wpj531-16m\n\ndefine Device/compex_wpj558-16m\n  SOC := qca9558\n  IMAGE_SIZE := 16128k\n  DEVICE_VENDOR := Compex\n  DEVICE_MODEL := WPJ558\n  DEVICE_VARIANT := 16M\n  SUPPORTED_DEVICES += wpj558\n  IMAGES += cpximg-6a07.bin\n  IMAGE/cpximg-6a07.bin := append-kernel | pad-to $$$$(BLOCKSIZE) | \\\n\tappend-rootfs | pad-rootfs | mkmylofw_16m 0x691 3\n  DEVICE_PACKAGES := kmod-gpio-beeper\nendef\nTARGET_DEVICES += compex_wpj558-16m\n\ndefine Device/compex_wpj563\n  SOC := qca9563\n  DEVICE_PACKAGES := kmod-usb2 kmod-usb3\n  IMAGE_SIZE := 16128k\n  DEVICE_VENDOR := Compex\n  DEVICE_MODEL := WPJ563\n  SUPPORTED_DEVICES += wpj563\n  IMAGES += cpximg-7a02.bin\n  IMAGE/cpximg-7a02.bin := append-kernel | pad-to $$$$(BLOCKSIZE) | append-rootfs | pad-rootfs | mkmylofw_16m 0x694 2\nendef\nTARGET_DEVICES += compex_wpj563\n\ndefine Device/devolo_dlan-pro-1200plus-ac\n  SOC := ar9344\n  DEVICE_VENDOR := Devolo\n  DEVICE_MODEL := dLAN pro 1200+ WiFi ac\n  DEVICE_PACKAGES := kmod-ath10k-ct ath10k-firmware-qca988x-ct\n  IMAGE_SIZE := 15872k\nendef\nTARGET_DEVICES += devolo_dlan-pro-1200plus-ac\n\ndefine Device/devolo_dvl1200e\n  SOC := qca9558\n  DEVICE_VENDOR := devolo\n  DEVICE_MODEL := WiFi pro 1200e\n  DEVICE_PACKAGES := kmod-ath10k-ct ath10k-firmware-qca988x-ct\n  IMAGE_SIZE := 15936k\nendef\nTARGET_DEVICES += devolo_dvl1200e\n\ndefine Device/devolo_dvl1200i\n  SOC := qca9558\n  DEVICE_VENDOR := devolo\n  DEVICE_MODEL := WiFi pro 1200i\n  DEVICE_PACKAGES := kmod-ath10k-ct ath10k-firmware-qca988x-ct\n  IMAGE_SIZE := 15936k\nendef\nTARGET_DEVICES += devolo_dvl1200i\n\ndefine Device/devolo_dvl1750c\n  SOC := qca9558\n  DEVICE_VENDOR := devolo\n  DEVICE_MODEL := WiFi pro 1750c\n  DEVICE_PACKAGES := kmod-ath10k-ct ath10k-firmware-qca988x-ct\n  IMAGE_SIZE := 15936k\nendef\nTARGET_DEVICES += devolo_dvl1750c\n\ndefine Device/devolo_dvl1750e\n  SOC := qca9558\n  DEVICE_VENDOR := devolo\n  DEVICE_MODEL := WiFi pro 1750e\n  DEVICE_PACKAGES := kmod-usb2 kmod-ath10k-ct ath10k-firmware-qca988x-ct\n  IMAGE_SIZE := 15936k\nendef\nTARGET_DEVICES += devolo_dvl1750e\n\ndefine Device/devolo_dvl1750i\n  SOC := qca9558\n  DEVICE_VENDOR := devolo\n  DEVICE_MODEL := WiFi pro 1750i\n  DEVICE_PACKAGES := kmod-ath10k-ct ath10k-firmware-qca988x-ct\n  IMAGE_SIZE := 15936k\nendef\nTARGET_DEVICES += devolo_dvl1750i\n\ndefine Device/devolo_dvl1750x\n  SOC := qca9558\n  DEVICE_VENDOR := devolo\n  DEVICE_MODEL := WiFi pro 1750x\n  DEVICE_PACKAGES := kmod-ath10k-ct ath10k-firmware-qca988x-ct\n  IMAGE_SIZE := 15936k\nendef\nTARGET_DEVICES += devolo_dvl1750x\n\ndefine Device/devolo_magic-2-wifi\n  SOC := ar9344\n  DEVICE_VENDOR := Devolo\n  DEVICE_MODEL := Magic 2 WiFi\n  DEVICE_PACKAGES := kmod-ath10k-ct ath10k-firmware-qca988x-ct\n  IMAGE_SIZE := 15872k\nendef\nTARGET_DEVICES += devolo_magic-2-wifi\n\ndefine Device/dlink_dap-13xx\n  SOC := qca9533\n  DEVICE_VENDOR := D-Link\n  DEVICE_PACKAGES += rssileds\n  IMAGE_SIZE := 7936k\n  IMAGES += factory.bin\n  IMAGE/factory.bin := append-kernel | pad-to $$$$(BLOCKSIZE) | \\\n\tappend-rootfs | pad-rootfs | check-size | mkdapimg2 0xE0000\nendef\n\ndefine Device/dlink_dap-1330-a1\n  $(Device/dlink_dap-13xx)\n  DEVICE_MODEL := DAP-1330\n  DEVICE_VARIANT := A1\n  DAP_SIGNATURE := HONEYBEE-FIRMWARE-DAP-1330\n  SUPPORTED_DEVICES += dap-1330-a1\nendef\nTARGET_DEVICES += dlink_dap-1330-a1\n\ndefine Device/dlink_dap-1365-a1\n  $(Device/dlink_dap-13xx)\n  DEVICE_MODEL := DAP-1365\n  DEVICE_VARIANT := A1\n  DAP_SIGNATURE := HONEYBEE-FIRMWARE-DAP-1365\nendef\nTARGET_DEVICES += dlink_dap-1365-a1\n\ndefine Device/dlink_dap-2xxx\n  IMAGES += factory.img\n  IMAGE/factory.img := append-kernel | pad-offset 6144k 160 | \\\n\tappend-rootfs | wrgg-pad-rootfs | mkwrggimg | check-size\n  IMAGE/sysupgrade.bin := append-kernel | mkwrggimg | \\\n\tpad-to $$$$(BLOCKSIZE) | append-rootfs | check-size | append-metadata\n  KERNEL := kernel-bin | append-dtb | relocate-kernel | lzma\n  KERNEL_INITRAMFS := $$(KERNEL) | mkwrggimg\nendef\n\ndefine Device/dlink_dap-2230-a1\n  $(Device/dlink_dap-2xxx)\n  SOC := qca9533\n  DEVICE_VENDOR := D-Link\n  DEVICE_MODEL := DAP-2230\n  DEVICE_VARIANT := A1\n  IMAGE_SIZE := 15232k\n  DAP_SIGNATURE := wapn31_dkbs_dap2230\nendef\nTARGET_DEVICES += dlink_dap-2230-a1\n\ndefine Device/dlink_dap-2660-a1\n  $(Device/dlink_dap-2xxx)\n  SOC := qca9557\n  DEVICE_VENDOR := D-Link\n  DEVICE_MODEL := DAP-2660\n  DEVICE_VARIANT := A1\n  DEVICE_PACKAGES := ath10k-firmware-qca988x-ct kmod-ath10k-ct\n  IMAGE_SIZE := 15232k\n  DAP_SIGNATURE := wapac09_dkbs_dap2660\nendef\nTARGET_DEVICES += dlink_dap-2660-a1\n\ndefine Device/dlink_dap-2680-a1\n  $(Device/dlink_dap-2xxx)\n  SOC := qca9558\n  DEVICE_VENDOR := D-Link\n  DEVICE_MODEL := DAP-2680\n  DEVICE_VARIANT := A1\n  DEVICE_PACKAGES := ath10k-firmware-qca99x0-ct kmod-ath10k-ct\n  IMAGE_SIZE := 15232k\n  DAP_SIGNATURE := wapac36_dkbs_dap2680\nendef\nTARGET_DEVICES += dlink_dap-2680-a1\n\ndefine Device/dlink_dap-2695-a1\n  $(Device/dlink_dap-2xxx)\n  SOC := qca9558\n  DEVICE_VENDOR := D-Link\n  DEVICE_MODEL := DAP-2695\n  DEVICE_VARIANT := A1\n  DEVICE_PACKAGES := ath10k-firmware-qca988x-ct kmod-ath10k-ct\n  IMAGE_SIZE := 15360k\n  DAP_SIGNATURE := wapac02_dkbs_dap2695\n  SUPPORTED_DEVICES += dap-2695-a1\nendef\nTARGET_DEVICES += dlink_dap-2695-a1\n\ndefine Device/dlink_dap-3320-a1\n  $(Device/dlink_dap-2xxx)\n  SOC := qca9533\n  DEVICE_VENDOR := D-Link\n  DEVICE_MODEL := DAP-3320\n  DEVICE_VARIANT := A1\n  IMAGE_SIZE := 15296k\n  DAP_SIGNATURE := wapn29_dkbs_dap3320\nendef\nTARGET_DEVICES += dlink_dap-3320-a1\n\ndefine Device/dlink_dap-3662-a1\n  $(Device/dlink_dap-2xxx)\n  SOC := qca9558\n  DEVICE_VENDOR := D-Link\n  DEVICE_MODEL := DAP-3662\n  DEVICE_VARIANT := A1\n  DEVICE_PACKAGES := ath10k-firmware-qca988x-ct kmod-ath10k-ct\n  IMAGE_SIZE := 15296k\n  DAP_SIGNATURE := wapac11_dkbs_dap3662\nendef\nTARGET_DEVICES += dlink_dap-3662-a1\n\ndefine Device/dlink_dch-g020-a1\n  SOC := qca9531\n  DEVICE_VENDOR := D-Link\n  DEVICE_MODEL := DCH-G020\n  DEVICE_VARIANT := A1\n  DEVICE_PACKAGES := kmod-gpio-pca953x kmod-i2c-gpio kmod-usb2 kmod-usb-acm\n  IMAGES += factory.bin\n  IMAGE_SIZE := 14784k\n  IMAGE/factory.bin := append-kernel | pad-to $$$$(BLOCKSIZE) | \\\n\tappend-rootfs | pad-rootfs | check-size | mkdapimg2 0x20000\n  DAP_SIGNATURE := HONEYBEE-FIRMWARE-DCH-G020\nendef\nTARGET_DEVICES += dlink_dch-g020-a1\n\ndefine Device/dlink_dir-505\n  SOC := ar9330\n  DEVICE_VENDOR := D-Link\n  DEVICE_MODEL := DIR-505\n  IMAGE_SIZE := 7680k\n  DEVICE_PACKAGES := kmod-usb-chipidea2\n  SUPPORTED_DEVICES += dir-505-a1\nendef\nTARGET_DEVICES += dlink_dir-505\n\ndefine Device/dlink_dir-825-b1\n  SOC := ar7161\n  DEVICE_VENDOR := D-Link\n  DEVICE_MODEL := DIR-825\n  DEVICE_VARIANT := B1\n  IMAGE_SIZE := 6208k\n  IMAGE/sysupgrade.bin := append-kernel | append-rootfs | pad-rootfs | \\\n\tcheck-size | append-metadata\n  DEVICE_PACKAGES := kmod-usb-ohci kmod-usb2 kmod-usb-ledtrig-usbport \\\n\tkmod-leds-reset kmod-owl-loader\n  SUPPORTED_DEVICES += dir-825-b1\nendef\nTARGET_DEVICES += dlink_dir-825-b1\n\ndefine Device/dlink_dir-825-c1\n  SOC := ar9344\n  DEVICE_VENDOR := D-Link\n  DEVICE_MODEL := DIR-825\n  DEVICE_VARIANT := C1\n  DEVICE_PACKAGES := kmod-usb2 kmod-usb-ledtrig-usbport kmod-leds-reset \\\n\tkmod-owl-loader\n  SUPPORTED_DEVICES += dir-825-c1\n  IMAGE_SIZE := 15936k\n  IMAGES := factory.bin sysupgrade.bin\n  IMAGE/default := append-kernel | pad-to $$$$(BLOCKSIZE) | append-rootfs | \\\n\tpad-rootfs\n  IMAGE/factory.bin := $$(IMAGE/default) | pad-offset $$$$(IMAGE_SIZE) 26 | \\\n\tappend-string 00DB120AR9344-RT-101214-00 | check-size\n  IMAGE/sysupgrade.bin := $$(IMAGE/default) | check-size | append-metadata\nendef\nTARGET_DEVICES += dlink_dir-825-c1\n\ndefine Device/dlink_dir-835-a1\n  SOC := ar9344\n  DEVICE_VENDOR := D-Link\n  DEVICE_MODEL := DIR-835\n  DEVICE_VARIANT := A1\n  DEVICE_PACKAGES := kmod-usb2 kmod-leds-reset kmod-owl-loader\n  SUPPORTED_DEVICES += dir-835-a1\n  IMAGE_SIZE := 15936k\n  IMAGES := factory.bin sysupgrade.bin\n  IMAGE/default := append-kernel | pad-to $$$$(BLOCKSIZE) | append-rootfs | \\\n\tpad-rootfs\n  IMAGE/factory.bin := $$(IMAGE/default) | pad-offset $$$$(IMAGE_SIZE) 26 | \\\n\tappend-string 00DB120AR9344-RT-101214-00 | check-size\n  IMAGE/sysupgrade.bin := $$(IMAGE/default) | check-size | append-metadata\nendef\nTARGET_DEVICES += dlink_dir-835-a1\n\ndefine Device/dlink_dir-842-c\n  SOC := qca9563\n  DEVICE_VENDOR := D-Link\n  DEVICE_MODEL := DIR-842\n  KERNEL := kernel-bin | append-dtb | relocate-kernel | lzma\n  KERNEL_INITRAMFS := $$(KERNEL) | seama\n  IMAGES += factory.bin\n  SEAMA_MTDBLOCK := 5\n  SEAMA_SIGNATURE := wrgac65_dlink.2015_dir842\n  # 64 bytes offset:\n  # - 28 bytes seama_header\n  # - 36 bytes of META data (4-bytes aligned)\n  IMAGE/default := append-kernel | uImage lzma | \\\n\tpad-offset $$$$(BLOCKSIZE) 64 | append-rootfs\n  IMAGE/sysupgrade.bin := $$(IMAGE/default) | seama | pad-rootfs | \\\n\tcheck-size | append-metadata\n  IMAGE/factory.bin := $$(IMAGE/default) | pad-rootfs -x 64 | seama | \\\n\tseama-seal | check-size\n  IMAGE_SIZE := 15680k\nendef\n\ndefine Device/dlink_dir-842-c1\n  $(Device/dlink_dir-842-c)\n  DEVICE_VARIANT := C1\n  DEVICE_PACKAGES := kmod-ath10k-ct ath10k-firmware-qca9888-ct\nendef\nTARGET_DEVICES += dlink_dir-842-c1\n\ndefine Device/dlink_dir-842-c2\n  $(Device/dlink_dir-842-c)\n  DEVICE_VARIANT := C2\n  DEVICE_PACKAGES := kmod-usb2 kmod-ath10k-ct ath10k-firmware-qca9888-ct\nendef\nTARGET_DEVICES += dlink_dir-842-c2\n\ndefine Device/dlink_dir-842-c3\n  $(Device/dlink_dir-842-c)\n  DEVICE_VARIANT := C3\n  DEVICE_PACKAGES := kmod-ath10k-ct ath10k-firmware-qca9888-ct\nendef\nTARGET_DEVICES += dlink_dir-842-c3\n\ndefine Device/dlink_dir-859-a1\n  $(Device/seama)\n  SOC := qca9563\n  DEVICE_VENDOR := D-Link\n  DEVICE_MODEL := DIR-859\n  DEVICE_VARIANT := A1\n  IMAGE_SIZE := 15872k\n  DEVICE_PACKAGES :=  kmod-usb2 kmod-ath10k-ct-smallbuffers ath10k-firmware-qca988x-ct\n  SEAMA_SIGNATURE := wrgac37_dlink.2013gui_dir859\nendef\nTARGET_DEVICES += dlink_dir-859-a1\n\ndefine Device/elecom_wrc-1750ghbk2-i\n  SOC := qca9563\n  DEVICE_VENDOR := ELECOM\n  DEVICE_MODEL := WRC-1750GHBK2-I/C\n  IMAGE_SIZE := 15808k\n  KERNEL_INITRAMFS := $$(KERNEL) | pad-to 2 | \\\n\tadd-elecom-factory-initramfs RN68 WRC-1750GHBK2\n  DEVICE_PACKAGES := kmod-ath10k-ct ath10k-firmware-qca988x-ct\nendef\nTARGET_DEVICES += elecom_wrc-1750ghbk2-i\n\ndefine Device/elecom_wrc-300ghbk2-i\n  SOC := qca9563\n  DEVICE_VENDOR := ELECOM\n  DEVICE_MODEL := WRC-300GHBK2-I\n  IMAGE_SIZE := 7616k\n  KERNEL_INITRAMFS := $$(KERNEL) | pad-to 2 | \\\n\tadd-elecom-factory-initramfs RN51 WRC-300GHBK2-I\nendef\nTARGET_DEVICES += elecom_wrc-300ghbk2-i\n\ndefine Device/embeddedwireless_balin\n  SOC := ar9344\n  DEVICE_VENDOR := Embedded Wireless\n  DEVICE_MODEL := Balin\n  DEVICE_PACKAGES := kmod-usb-chipidea2\n  IMAGE_SIZE := 16000k\nendef\nTARGET_DEVICES += embeddedwireless_balin\n\ndefine Device/embeddedwireless_dorin\n  SOC := ar9331\n  DEVICE_VENDOR := Embedded Wireless\n  DEVICE_MODEL := Dorin\n  DEVICE_PACKAGES := kmod-usb-chipidea2\n  IMAGE_SIZE := 16000k\nendef\nTARGET_DEVICES += embeddedwireless_dorin\n\ndefine Device/engenius_eap1200h\n  $(Device/senao_loader_okli)\n  SOC := qca9557\n  DEVICE_VENDOR := EnGenius\n  DEVICE_MODEL := EAP1200H\n  DEVICE_PACKAGES := ath10k-firmware-qca988x-ct kmod-ath10k-ct\n  IMAGE_SIZE := 11584k\n  LOADER_FLASH_OFFS := 0x220000\n  SENAO_IMGNAME := ar71xx-generic-eap1200h\nendef\nTARGET_DEVICES += engenius_eap1200h\n\ndefine Device/engenius_eap300-v2\n  $(Device/senao_loader_okli)\n  SOC := ar9341\n  DEVICE_VENDOR := EnGenius\n  DEVICE_MODEL := EAP300\n  DEVICE_VARIANT := v2\n  IMAGE_SIZE := 12096k\n  LOADER_FLASH_OFFS := 0x220000\n  SENAO_IMGNAME := senao-eap300v2\nendef\nTARGET_DEVICES += engenius_eap300-v2\n\ndefine Device/engenius_eap600\n  $(Device/senao_loader_okli)\n  SOC := ar9344\n  DEVICE_VENDOR := EnGenius\n  DEVICE_MODEL := EAP600\n  IMAGE_SIZE := 12096k\n  LOADER_FLASH_OFFS := 0x220000\n  SENAO_IMGNAME := senao-eap600\nendef\nTARGET_DEVICES += engenius_eap600\n\ndefine Device/engenius_ecb1200\n  SOC := qca9557\n  DEVICE_VENDOR := EnGenius\n  DEVICE_MODEL := ECB1200\n  DEVICE_PACKAGES := ath10k-firmware-qca988x-ct kmod-ath10k-ct\n  IMAGE_SIZE := 15680k\n  IMAGES += factory.bin\n  IMAGE/factory.bin := append-kernel | pad-to $$$$(BLOCKSIZE) | \\\n\tappend-rootfs | pad-rootfs | check-size | \\\n\tsenao-header -r 0x101 -p 0x6e -t 2\nendef\nTARGET_DEVICES += engenius_ecb1200\n\ndefine Device/engenius_ecb1750\n  SOC := qca9558\n  DEVICE_VENDOR := EnGenius\n  DEVICE_MODEL := ECB1750\n  DEVICE_PACKAGES := ath10k-firmware-qca988x-ct kmod-ath10k-ct\n  IMAGE_SIZE := 15680k\n  IMAGES += factory.bin\n  IMAGE/factory.bin := append-kernel | pad-to $$$$(BLOCKSIZE) | \\\n\tappend-rootfs | pad-rootfs | check-size | \\\n\tsenao-header -r 0x101 -p 0x6d -t 2\nendef\nTARGET_DEVICES += engenius_ecb1750\n\ndefine Device/engenius_ecb600\n  $(Device/senao_loader_okli)\n  SOC := ar9344\n  DEVICE_VENDOR := EnGenius\n  DEVICE_MODEL := ECB600\n  IMAGE_SIZE := 12096k\n  LOADER_FLASH_OFFS := 0x220000\n  SENAO_IMGNAME := senao-ecb600\nendef\nTARGET_DEVICES += engenius_ecb600\n\ndefine Device/engenius_ens202ext-v1\n  $(Device/senao_loader_okli)\n  SOC := ar9341\n  DEVICE_VENDOR := EnGenius\n  DEVICE_MODEL := ENS202EXT\n  DEVICE_VARIANT := v1\n  DEVICE_PACKAGES := rssileds\n  IMAGE_SIZE := 12096k\n  LOADER_FLASH_OFFS := 0x220000\n  SENAO_IMGNAME := senao-ens202ext\nendef\nTARGET_DEVICES += engenius_ens202ext-v1\n\ndefine Device/engenius_enstationac-v1\n  $(Device/senao_loader_okli)\n  SOC := qca9557\n  DEVICE_VENDOR := EnGenius\n  DEVICE_MODEL := EnStationAC\n  DEVICE_VARIANT := v1\n  DEVICE_PACKAGES := ath10k-firmware-qca988x-ct kmod-ath10k-ct rssileds\n  IMAGE_SIZE := 11584k\n  LOADER_FLASH_OFFS := 0x220000\n  SENAO_IMGNAME := ar71xx-generic-enstationac\nendef\nTARGET_DEVICES += engenius_enstationac-v1\n\ndefine Device/engenius_epg5000\n  SOC := qca9558\n  DEVICE_VENDOR := EnGenius\n  DEVICE_MODEL := EPG5000\n  DEVICE_PACKAGES := ath10k-firmware-qca988x-ct kmod-ath10k-ct kmod-usb2\n  IMAGE_SIZE := 14656k\n  IMAGES += factory.dlf\n  IMAGE/factory.dlf := append-kernel | pad-to $$$$(BLOCKSIZE) | \\\n\tappend-rootfs | pad-rootfs | check-size | \\\n\tsenao-header -r 0x101 -p 0x71 -t 2\n  SUPPORTED_DEVICES += epg5000\nendef\nTARGET_DEVICES += engenius_epg5000\n\ndefine Device/engenius_ews511ap\n  SOC := qca9531\n  DEVICE_VENDOR := EnGenius\n  DEVICE_MODEL := EWS511AP\n  DEVICE_PACKAGES := kmod-ath10k-ct ath10k-firmware-qca9887-ct\n  IMAGE_SIZE := 16000k\nendef\nTARGET_DEVICES += engenius_ews511ap\n\ndefine Device/enterasys_ws-ap3705i\n  SOC := ar9344\n  DEVICE_VENDOR := Enterasys\n  DEVICE_MODEL := WS-AP3705i\n  IMAGE_SIZE := 30528k\nendef\nTARGET_DEVICES += enterasys_ws-ap3705i\n\ndefine Device/etactica_eg200\n  SOC := ar9331\n  DEVICE_VENDOR := eTactica\n  DEVICE_MODEL := EG200\n  DEVICE_PACKAGES := kmod-usb-chipidea2 kmod-ledtrig-oneshot \\\n\tkmod-usb-serial-ftdi kmod-usb-storage kmod-fs-ext4\n  IMAGE_SIZE := 16000k\n  SUPPORTED_DEVICES += rme-eg200\nendef\nTARGET_DEVICES += etactica_eg200\n\ndefine Device/glinet_6408\n  $(Device/tplink-8mlzma)\n  SOC := ar9331\n  DEVICE_VENDOR := GL.iNet\n  DEVICE_MODEL := 6408\n  DEVICE_PACKAGES := kmod-usb-chipidea2\n  IMAGE_SIZE := 8000k\n  TPLINK_HWID := 0x08000001\n  IMAGES := sysupgrade.bin\n  SUPPORTED_DEVICES += gl-inet\nendef\nTARGET_DEVICES += glinet_6408\n\ndefine Device/glinet_6416\n  $(Device/tplink-16mlzma)\n  SOC := ar9331\n  DEVICE_VENDOR := GL.iNet\n  DEVICE_MODEL := 6416\n  DEVICE_PACKAGES := kmod-usb-chipidea2\n  IMAGE_SIZE := 16192k\n  TPLINK_HWID := 0x08000001\n  IMAGES := sysupgrade.bin\n  SUPPORTED_DEVICES += gl-inet\nendef\nTARGET_DEVICES += glinet_6416\n\ndefine Device/glinet_gl-ar150\n  SOC := ar9330\n  DEVICE_VENDOR := GL.iNet\n  DEVICE_MODEL := GL-AR150\n  DEVICE_PACKAGES := kmod-usb-chipidea2\n  IMAGE_SIZE := 16000k\n  SUPPORTED_DEVICES += gl-ar150\nendef\nTARGET_DEVICES += glinet_gl-ar150\n\ndefine Device/glinet_gl-ar300m-common-nor\n  SOC := qca9531\n  DEVICE_VENDOR := GL.iNet\n  DEVICE_PACKAGES := kmod-usb2\n  IMAGE_SIZE := 16000k\n  SUPPORTED_DEVICES += gl-ar300m\nendef\n\ndefine Device/glinet_gl-ar300m-lite\n  $(Device/glinet_gl-ar300m-common-nor)\n  DEVICE_MODEL := GL-AR300M\n  DEVICE_VARIANT := Lite\nendef\nTARGET_DEVICES += glinet_gl-ar300m-lite\n\ndefine Device/glinet_gl-ar300m16\n  $(Device/glinet_gl-ar300m-common-nor)\n  DEVICE_MODEL := GL-AR300M16\nendef\nTARGET_DEVICES += glinet_gl-ar300m16\n\ndefine Device/glinet_gl-ar750\n  SOC := qca9531\n  DEVICE_VENDOR := GL.iNet\n  DEVICE_MODEL := GL-AR750\n  DEVICE_PACKAGES := kmod-usb2 kmod-ath10k-ct ath10k-firmware-qca9887-ct\n  IMAGE_SIZE := 16000k\n  SUPPORTED_DEVICES += gl-ar750\nendef\nTARGET_DEVICES += glinet_gl-ar750\n\ndefine Device/glinet_gl-mifi\n  SOC := ar9331\n  DEVICE_VENDOR := GL.iNET\n  DEVICE_MODEL := GL-MiFi\n  DEVICE_PACKAGES := kmod-usb-chipidea2\n  IMAGE_SIZE := 16000k\n  SUPPORTED_DEVICES += gl-mifi\nendef\nTARGET_DEVICES += glinet_gl-mifi\n\ndefine Device/glinet_gl-usb150\n  SOC := ar9331\n  DEVICE_VENDOR := GL.iNET\n  DEVICE_MODEL := GL-USB150\n  IMAGE_SIZE := 16000k\n  SUPPORTED_DEVICES += gl-usb150\nendef\nTARGET_DEVICES += glinet_gl-usb150\n\ndefine Device/glinet_gl-x300b\n  SOC := qca9531\n  DEVICE_VENDOR := GL.iNet\n  DEVICE_MODEL := GL-X300B\n  DEVICE_PACKAGES := kmod-usb2\n  IMAGE_SIZE := 16000k\nendef\nTARGET_DEVICES += glinet_gl-x300b\n\ndefine Device/glinet_gl-x750\n  SOC := qca9531\n  DEVICE_VENDOR := GL.iNet\n  DEVICE_MODEL := GL-X750\n  DEVICE_PACKAGES := kmod-usb2 kmod-ath10k-ct ath10k-firmware-qca9887-ct\n  IMAGE_SIZE := 16000k\nendef\nTARGET_DEVICES += glinet_gl-x750\n\ndefine Device/hak5_lan-turtle\n  $(Device/tplink-16mlzma)\n  SOC := ar9331\n  DEVICE_VENDOR := Hak5\n  DEVICE_MODEL := LAN Turtle\n  TPLINK_HWID := 0x5348334c\n  IMAGES := sysupgrade.bin\n  DEVICE_PACKAGES := kmod-usb-chipidea2 -iwinfo -kmod-ath9k -swconfig \\\n\t-uboot-envtools -wpad-basic-wolfssl\n  SUPPORTED_DEVICES += lan-turtle\nendef\nTARGET_DEVICES += hak5_lan-turtle\n\ndefine Device/hak5_packet-squirrel\n  $(Device/tplink-16mlzma)\n  SOC := ar9331\n  DEVICE_VENDOR := Hak5\n  DEVICE_MODEL := Packet Squirrel\n  TPLINK_HWID := 0x5351524c\n  IMAGES := sysupgrade.bin\n  DEVICE_PACKAGES := kmod-usb-chipidea2 -iwinfo -kmod-ath9k -swconfig \\\n\t-uboot-envtools -wpad-basic-wolfssl\n  SUPPORTED_DEVICES += packet-squirrel\nendef\nTARGET_DEVICES += hak5_packet-squirrel\n\ndefine Device/hak5_wifi-pineapple-nano\n  $(Device/tplink-16mlzma)\n  SOC := ar9331\n  DEVICE_VENDOR := Hak5\n  DEVICE_MODEL := WiFi Pineapple NANO\n  TPLINK_HWID := 0x4e414e4f\n  IMAGES := sysupgrade.bin\n  DEVICE_PACKAGES := kmod-ath9k-htc kmod-usb-chipidea2 kmod-usb-storage \\\n\t-swconfig -uboot-envtools\n  SUPPORTED_DEVICES += wifi-pineapple-nano\nendef\nTARGET_DEVICES += hak5_wifi-pineapple-nano\n\ndefine Device/hiwifi_hc6361\n  SOC := ar9331\n  DEVICE_VENDOR := HiWiFi\n  DEVICE_MODEL := HC6361\n  DEVICE_PACKAGES := kmod-usb-core kmod-usb2 kmod-usb-chipidea2 kmod-usb-storage \\\n\tkmod-fs-ext4 kmod-nls-iso8859-1 e2fsprogs\n  BOARDNAME := HiWiFi-HC6361\n  KERNEL := kernel-bin | append-dtb | lzma | uImage lzma | pad-to $$(BLOCKSIZE)\n  IMAGE_SIZE := 16128k\nendef\nTARGET_DEVICES += hiwifi_hc6361\n\ndefine Device/iodata_etg3-r\n  SOC := ar9342\n  DEVICE_VENDOR := I-O DATA\n  DEVICE_MODEL := ETG3-R\n  IMAGE_SIZE := 7680k\n  DEVICE_PACKAGES := -iwinfo -kmod-ath9k -wpad-basic-wolfssl\nendef\nTARGET_DEVICES += iodata_etg3-r\n\ndefine Device/iodata_wn-ac1167dgr\n  SOC := qca9557\n  DEVICE_VENDOR := I-O DATA\n  DEVICE_MODEL := WN-AC1167DGR\n  IMAGE_SIZE := 14656k\n  IMAGES += factory.bin\n  IMAGE/factory.bin := append-kernel | pad-to $$$$(BLOCKSIZE) | \\\n\tappend-rootfs | pad-rootfs | check-size | \\\n\tsenao-header -r 0x30a -p 0x61 -t 2\n  DEVICE_PACKAGES := kmod-usb2 kmod-ath10k-ct ath10k-firmware-qca988x-ct\nendef\nTARGET_DEVICES += iodata_wn-ac1167dgr\n\ndefine Device/iodata_wn-ac1600dgr\n  SOC := qca9557\n  DEVICE_VENDOR := I-O DATA\n  DEVICE_MODEL := WN-AC1600DGR\n  IMAGE_SIZE := 14656k\n  IMAGES += factory.bin\n  IMAGE/factory.bin := append-kernel | pad-to $$$$(BLOCKSIZE) | \\\n\tappend-rootfs | pad-rootfs | check-size | \\\n\tsenao-header -r 0x30a -p 0x60 -t 2 -v 200\n  DEVICE_PACKAGES := kmod-usb2 kmod-ath10k-ct ath10k-firmware-qca988x-ct\nendef\nTARGET_DEVICES += iodata_wn-ac1600dgr\n\ndefine Device/iodata_wn-ac1600dgr2\n  SOC := qca9557\n  DEVICE_VENDOR := I-O DATA\n  DEVICE_MODEL := WN-AC1600DGR2/DGR3\n  IMAGE_SIZE := 14656k\n  IMAGES += dgr2-dgr3-factory.bin\n  IMAGE/dgr2-dgr3-factory.bin := append-kernel | pad-to $$$$(BLOCKSIZE) | \\\n\tappend-rootfs | pad-rootfs | check-size | \\\n\tsenao-header -r 0x30a -p 0x60 -t 2 -v 200\n  DEVICE_PACKAGES := kmod-usb2 kmod-ath10k-ct ath10k-firmware-qca988x-ct\nendef\nTARGET_DEVICES += iodata_wn-ac1600dgr2\n\ndefine Device/iodata_wn-ag300dgr\n  SOC := ar1022\n  DEVICE_VENDOR := I-O DATA\n  DEVICE_MODEL := WN-AG300DGR\n  IMAGE_SIZE := 15424k\n  IMAGES += factory.bin\n  IMAGE/factory.bin := append-kernel | pad-to $$$$(BLOCKSIZE) | \\\n\tappend-rootfs | pad-rootfs | check-size | \\\n\tsenao-header -r 0x30a -p 0x47 -t 2\n  DEVICE_PACKAGES := kmod-usb2\nendef\nTARGET_DEVICES += iodata_wn-ag300dgr\n\ndefine Device/jjplus_ja76pf2\n  SOC := ar7161\n  DEVICE_VENDOR := jjPlus\n  DEVICE_MODEL := JA76PF2\n  DEVICE_PACKAGES += -kmod-ath9k -swconfig -wpad-basic-wolfssl -uboot-envtools fconfig\n  IMAGES += kernel.bin rootfs.bin\n  IMAGE/kernel.bin := append-kernel\n  IMAGE/rootfs.bin := append-rootfs | pad-rootfs\n  IMAGE/sysupgrade.bin := append-rootfs | pad-rootfs | combined-image | \\\n\tcheck-size | append-metadata\n  KERNEL := kernel-bin | append-dtb | lzma | pad-to $$(BLOCKSIZE)\n  KERNEL_INITRAMFS := kernel-bin | append-dtb\n  IMAGE_SIZE := 16000k\n  SUPPORTED_DEVICES += ja76pf2\nendef\nTARGET_DEVICES += jjplus_ja76pf2\n\ndefine Device/jjplus_jwap230\n  SOC := qca9558\n  DEVICE_VENDOR := jjPlus\n  DEVICE_MODEL := JWAP230\n  IMAGE_SIZE := 16000k\nendef\nTARGET_DEVICES += jjplus_jwap230\n\ndefine Device/joyit_jt-or750i\n  SOC := qca9531\n  DEVICE_VENDOR := Joy-IT\n  DEVICE_MODEL := JT-OR750i\n  DEVICE_PACKAGES := kmod-ath10k-ct ath10k-firmware-qca9887-ct\n  IMAGE_SIZE := 16000k\nendef\nTARGET_DEVICES += joyit_jt-or750i\n\ndefine Device/letv_lba-047-ch\n  $(Device/loader-okli-uimage)\n  SOC := qca9531\n  DEVICE_VENDOR := Letv\n  DEVICE_MODEL := LBA-047-CH\n  IMAGE_SIZE := 15936k\n  LOADER_FLASH_OFFS := 0x50000\n  KERNEL := kernel-bin | append-dtb | lzma | uImage lzma -M 0x4f4b4c49\n  IMAGES += factory.bin\n  IMAGE/factory.bin := append-kernel | pad-to $$$$(BLOCKSIZE) | \\\n\tappend-rootfs | pad-rootfs | check-size | pad-to 14528k | \\\n\tappend-loader-okli-uimage $(1) | pad-to 64k\nendef\nTARGET_DEVICES += letv_lba-047-ch\n\ndefine Device/librerouter_librerouter-v1\n  SOC := qca9558\n  DEVICE_VENDOR := Librerouter\n  DEVICE_MODEL := LibreRouter\n  DEVICE_VARIANT := v1\n  IMAGE_SIZE := 7936k\n  DEVICE_PACKAGES := kmod-usb2\nendef\nTARGET_DEVICES += librerouter_librerouter-v1\n\ndefine Device/meraki_mr12\n  SOC := ar7242\n  DEVICE_VENDOR := Meraki\n  DEVICE_MODEL := MR12\n  IMAGE_SIZE := 15616k\n  DEVICE_PACKAGES := kmod-owl-loader rssileds\n  SUPPORTED_DEVICES += mr12\n  DEVICE_COMPAT_VERSION := 2.0\n  DEVICE_COMPAT_MESSAGE := Partitions differ from ar71xx version of MR12. Image format is incompatible. \\\n\tTo use sysupgrade, you must change /lib/update/common.sh::get_image to prepend 128K zeroes to this image, \\\n\tand change the bootcmd in u-boot to \"bootm 0xbf0a0000\". After that, you can use \"sysupgrade -F -n\". \\\n\tMake sure you do not keep your old config, as ethernet setup is not compatible either. \\\n\tFor more details, see the OpenWrt Wiki: https://openwrt.org/toh/meraki/MR12, \\\n\tor the commit message of the MR12 ath79 port on git.openwrt.org.\nendef\nTARGET_DEVICES += meraki_mr12\n\ndefine Device/meraki_mr16\n  SOC := ar7161\n  DEVICE_VENDOR := Meraki\n  DEVICE_MODEL := MR16\n  IMAGE_SIZE := 15616k\n  DEVICE_PACKAGES := kmod-owl-loader\n  SUPPORTED_DEVICES += mr16\n  DEVICE_COMPAT_VERSION := 2.0\n  DEVICE_COMPAT_MESSAGE := Partitions differ from ar71xx version of MR16. Image format is incompatible. \\\n\tTo use sysupgrade, you must change /lib/update/common.sh::get_image to prepend 128K zeroes to this image, \\\n\tand change the bootcmd in u-boot to \"bootm 0xbf0a0000\". After that, you can use \"sysupgrade -F\". \\\n\tFor more details, see the OpenWrt Wiki: https://openwrt.org/toh/meraki/mr16, \\\n\tor the commit message of the MR16 ath79 port on git.openwrt.org.\nendef\nTARGET_DEVICES += meraki_mr16\n\ndefine Device/mercury_mw4530r-v1\n  $(Device/tplink-8mlzma)\n  SOC := ar9344\n  DEVICE_VENDOR := Mercury\n  DEVICE_MODEL := MW4530R\n  DEVICE_VARIANT := v1\n  DEVICE_PACKAGES := kmod-usb2 kmod-usb-ledtrig-usbport\n  TPLINK_HWID := 0x45300001\n  SUPPORTED_DEVICES += tl-wdr4300\nendef\nTARGET_DEVICES += mercury_mw4530r-v1\n\ndefine Device/nec_wx1200cr\n  DEVICE_VENDOR := NEC\n  IMAGE/default := append-kernel | pad-offset $$$$(BLOCKSIZE) 64 | append-rootfs\n  IMAGE/sysupgrade.bin := $$(IMAGE/default) | seama | pad-rootfs | \\\n\tcheck-size | append-metadata\n  DEVICE_PACKAGES := kmod-ath10k-ct ath10k-firmware-qca9888-ct\nendef\n\ndefine Device/nec_wf1200cr\n  $(Device/nec_wx1200cr)\n  SOC := qca9561\n  DEVICE_MODEL := Aterm WF1200CR\n  IMAGE_SIZE := 7680k\n  SEAMA_MTDBLOCK := 5\n  SEAMA_SIGNATURE := wrgac62_necpf.2016gui_wf1200cr\n  IMAGES += factory.bin\n  IMAGE/factory.bin := $$(IMAGE/default) | pad-rootfs -x 64 | seama | \\\n\tseama-seal | nec-enc ryztfyutcrqqo69d | check-size\nendef\nTARGET_DEVICES += nec_wf1200cr\n\ndefine Device/nec_wg1200cr\n  $(Device/nec_wx1200cr)\n  SOC := qca9563\n  DEVICE_MODEL := Aterm WG1200CR\n  IMAGE_SIZE := 7616k\n  SEAMA_MTDBLOCK := 6\n  SEAMA_SIGNATURE := wrgac72_necpf.2016gui_wg1200cr\n  IMAGES += factory.bin\n  IMAGE/factory.bin := $$(IMAGE/default) | pad-rootfs -x 64 | seama | \\\n\tseama-seal | nec-enc 9gsiy9nzep452pad | check-size\nendef\nTARGET_DEVICES += nec_wg1200cr\n\ndefine Device/nec_wg800hp\n  SOC := qca9563\n  DEVICE_VENDOR := NEC\n  DEVICE_MODEL := Aterm WG800HP\n  IMAGE_SIZE := 7104k\n  IMAGES += factory.bin\n  IMAGE/factory.bin := append-kernel | pad-to $$$$(BLOCKSIZE) | \\\n\tappend-rootfs | pad-rootfs | check-size | \\\n\txor-image -p 6A57190601121E4C004C1E1201061957 -x | nec-fw LASER_ATERM\n  DEVICE_PACKAGES := kmod-ath10k-ct-smallbuffers ath10k-firmware-qca9887-ct-full-htt\nendef\nTARGET_DEVICES += nec_wg800hp\n\ndefine Device/netgear_ex6400_ex7300\n  $(Device/netgear_generic)\n  SOC := qca9558\n  UIMAGE_MAGIC := 0x27051956\n  NETGEAR_BOARD_ID := EX7300series\n  NETGEAR_HW_ID := 29765104+16+0+128\n  IMAGE_SIZE := 15552k\n  IMAGE/default := append-kernel | pad-offset $$$$(BLOCKSIZE) 64 | \\\n\tnetgear-rootfs | pad-rootfs\n  IMAGE/sysupgrade.bin := $$(IMAGE/default) | check-size | append-metadata\n  IMAGE/factory.img := $$(IMAGE/default) | netgear-dni | check-size\n  DEVICE_PACKAGES := kmod-ath10k-ct ath10k-firmware-qca99x0-ct\nendef\n\ndefine Device/netgear_ex6400\n  $(Device/netgear_ex6400_ex7300)\n  DEVICE_MODEL := EX6400\nendef\nTARGET_DEVICES += netgear_ex6400\n\ndefine Device/netgear_ex7300\n  $(Device/netgear_ex6400_ex7300)\n  DEVICE_MODEL := EX7300\nendef\nTARGET_DEVICES += netgear_ex7300\n\ndefine Device/netgear_ex7300-v2\n  $(Device/netgear_generic)\n  SOC := qcn5502\n  DEVICE_MODEL := EX7300\n  DEVICE_VARIANT := v2\n  UIMAGE_MAGIC := 0x27051956\n  NETGEAR_BOARD_ID := EX7300v2series\n  NETGEAR_HW_ID := 29765907+16+0+128\n  IMAGE_SIZE := 14528k\n  IMAGE/default := append-kernel | pad-offset $$$$(BLOCKSIZE) 64 | \\\n\tnetgear-rootfs | pad-rootfs\n  IMAGE/sysupgrade.bin := $$(IMAGE/default) | check-size | append-metadata\n  IMAGE/factory.img := $$(IMAGE/default) | check-size | netgear-dni\n  DEVICE_PACKAGES := kmod-ath10k-ct ath10k-firmware-qca9984-ct\nendef\nTARGET_DEVICES += netgear_ex7300-v2\n\ndefine Device/netgear_wndap360\n  $(Device/netgear_generic)\n  SOC := ar7161\n  DEVICE_MODEL := WNDAP360\n  DEVICE_PACKAGES := kmod-leds-reset kmod-owl-loader\n  IMAGE_SIZE := 7744k\n  BLOCKSIZE := 256k\n  KERNEL := kernel-bin | append-dtb | gzip | uImage gzip\n  KERNEL_INITRAMFS := kernel-bin | append-dtb | uImage none\n  IMAGES := sysupgrade.bin\n  IMAGE/sysupgrade.bin := append-kernel | pad-to 64k | append-rootfs | pad-rootfs | \\\n\tcheck-size | append-metadata\nendef\nTARGET_DEVICES += netgear_wndap360\n\ndefine Device/netgear_wndr3x00\n  $(Device/netgear_generic)\n  SOC := ar7161\n  DEVICE_PACKAGES := kmod-usb-ohci kmod-usb2 kmod-usb-ledtrig-usbport \\\n\tkmod-leds-reset kmod-owl-loader\nendef\n\ndefine Device/netgear_wndr3700\n  $(Device/netgear_wndr3x00)\n  DEVICE_MODEL := WNDR3700\n  DEVICE_VARIANT := v1\n  UIMAGE_MAGIC := 0x33373030\n  NETGEAR_BOARD_ID := WNDR3700\n  IMAGE_SIZE := 7680k\n  IMAGES += factory-NA.img\n  IMAGE/factory-NA.img := $$(IMAGE/default) | netgear-dni NA | \\\n\tcheck-size\n  SUPPORTED_DEVICES += wndr3700\nendef\nTARGET_DEVICES += netgear_wndr3700\n\ndefine Device/netgear_wndr3700-v2\n  $(Device/netgear_wndr3x00)\n  DEVICE_MODEL := WNDR3700\n  DEVICE_VARIANT := v2\n  UIMAGE_MAGIC := 0x33373031\n  NETGEAR_BOARD_ID := WNDR3700v2\n  NETGEAR_HW_ID := 29763654+16+64\n  IMAGE_SIZE := 15872k\n  SUPPORTED_DEVICES += wndr3700 netgear,wndr3700v2\nendef\nTARGET_DEVICES += netgear_wndr3700-v2\n\ndefine Device/netgear_wndr3800\n  $(Device/netgear_wndr3x00)\n  DEVICE_MODEL := WNDR3800\n  UIMAGE_MAGIC := 0x33373031\n  NETGEAR_BOARD_ID := WNDR3800\n  NETGEAR_HW_ID := 29763654+16+128\n  IMAGE_SIZE := 15872k\n  SUPPORTED_DEVICES += wndr3700\nendef\nTARGET_DEVICES += netgear_wndr3800\n\ndefine Device/netgear_wndr3800ch\n  $(Device/netgear_wndr3x00)\n  DEVICE_MODEL := WNDR3800CH\n  UIMAGE_MAGIC := 0x33373031\n  NETGEAR_BOARD_ID := WNDR3800CH\n  NETGEAR_HW_ID := 29763654+16+128\n  IMAGE_SIZE := 15872k\n  SUPPORTED_DEVICES += wndr3700\nendef\nTARGET_DEVICES += netgear_wndr3800ch\n\ndefine Device/netgear_wndrmac-v1\n  $(Device/netgear_wndr3x00)\n  DEVICE_MODEL := WNDRMAC\n  DEVICE_VARIANT := v1\n  UIMAGE_MAGIC := 0x33373031\n  NETGEAR_BOARD_ID := WNDRMAC\n  NETGEAR_HW_ID := 29763654+16+64\n  IMAGE_SIZE := 15872k\n  SUPPORTED_DEVICES += wndr3700\nendef\nTARGET_DEVICES += netgear_wndrmac-v1\n\ndefine Device/netgear_wndrmac-v2\n  $(Device/netgear_wndr3x00)\n  DEVICE_MODEL := WNDRMAC\n  DEVICE_VARIANT := v2\n  UIMAGE_MAGIC := 0x33373031\n  NETGEAR_BOARD_ID := WNDRMACv2\n  NETGEAR_HW_ID := 29763654+16+128\n  IMAGE_SIZE := 15872k\n  SUPPORTED_DEVICES += wndr3700\nendef\nTARGET_DEVICES += netgear_wndrmac-v2\n\ndefine Device/netgear_wnr2200_common\n  $(Device/netgear_generic)\n  SOC := ar7241\n  DEVICE_MODEL := WNR2200\n  DEVICE_PACKAGES := kmod-usb2 kmod-usb-ledtrig-usbport\n  UIMAGE_MAGIC := 0x32323030\n  NETGEAR_BOARD_ID := wnr2200\nendef\n\ndefine Device/netgear_wnr2200-8m\n  $(Device/netgear_wnr2200_common)\n  DEVICE_VARIANT := 8M\n  NETGEAR_HW_ID := 29763600+08+64\n  IMAGE_SIZE := 7808k\n  IMAGES += factory-NA.img\n  IMAGE/factory-NA.img := $$(IMAGE/default) | netgear-dni NA | \\\n\tcheck-size\n  SUPPORTED_DEVICES += wnr2200\nendef\nTARGET_DEVICES += netgear_wnr2200-8m\n\ndefine Device/netgear_wnr2200-16m\n  $(Device/netgear_wnr2200_common)\n  DEVICE_VARIANT := 16M\n  DEVICE_ALT0_VENDOR := NETGEAR\n  DEVICE_ALT0_MODEL := WNR2200\n  DEVICE_ALT0_VARIANT := CN/RU\n  NETGEAR_HW_ID :=\n  IMAGE_SIZE := 16000k\nendef\nTARGET_DEVICES += netgear_wnr2200-16m\n\ndefine Device/ocedo_koala\n  SOC := qca9558\n  DEVICE_VENDOR := Ocedo\n  DEVICE_MODEL := Koala\n  DEVICE_PACKAGES := kmod-ath10k-ct ath10k-firmware-qca988x-ct\n  SUPPORTED_DEVICES += koala\n  IMAGE_SIZE := 7424k\nendef\nTARGET_DEVICES += ocedo_koala\n\ndefine Device/ocedo_raccoon\n  SOC := ar9344\n  DEVICE_VENDOR := Ocedo\n  DEVICE_MODEL := Raccoon\n  IMAGE_SIZE := 7424k\nendef\nTARGET_DEVICES += ocedo_raccoon\n\ndefine Device/ocedo_ursus\n  SOC := qca9558\n  DEVICE_VENDOR := Ocedo\n  DEVICE_MODEL := Ursus\n  DEVICE_PACKAGES := kmod-ath10k-ct ath10k-firmware-qca988x-ct\n  IMAGE_SIZE := 7424k\nendef\nTARGET_DEVICES += ocedo_ursus\n\ndefine Device/onion_omega\n  $(Device/tplink-16mlzma)\n  SOC := ar9331\n  DEVICE_VENDOR := Onion\n  DEVICE_MODEL := Omega\n  DEVICE_PACKAGES := kmod-usb-chipidea2\n  SUPPORTED_DEVICES += onion-omega\n  KERNEL_INITRAMFS := kernel-bin | append-dtb | lzma | uImage lzma\n  IMAGE_SIZE := 16192k\n  TPLINK_HWID := 0x04700001\nendef\nTARGET_DEVICES += onion_omega\n\ndefine Device/openmesh_common_64k\n  DEVICE_VENDOR := OpenMesh\n  DEVICE_PACKAGES := uboot-envtools\n  IMAGE_SIZE := 7808k\n  OPENMESH_CE_TYPE :=\n  KERNEL := kernel-bin | append-dtb | lzma | uImage lzma | \\\n\tpad-to $$(BLOCKSIZE)\n  IMAGE/sysupgrade.bin := append-rootfs | pad-rootfs | \\\n\topenmesh-image ce_type=$$$$(OPENMESH_CE_TYPE) | append-metadata\nendef\n\ndefine Device/openmesh_common_256k\n  DEVICE_VENDOR := OpenMesh\n  DEVICE_PACKAGES := uboot-envtools\n  IMAGE_SIZE := 7168k\n  BLOCKSIZE := 256k\n  OPENMESH_CE_TYPE :=\n  KERNEL := kernel-bin | append-dtb | lzma | uImage lzma | \\\n\tpad-to $$(BLOCKSIZE)\n  IMAGE/sysupgrade.bin := append-rootfs | pad-rootfs | \\\n\topenmesh-image ce_type=$$$$(OPENMESH_CE_TYPE) | append-metadata\nendef\n\ndefine Device/openmesh_a40\n  $(Device/openmesh_common_64k)\n  SOC := qca9558\n  DEVICE_MODEL := A40\n  DEVICE_PACKAGES += kmod-ath10k-ct ath10k-firmware-qca988x-ct kmod-usb2\n  OPENMESH_CE_TYPE := A60\n  SUPPORTED_DEVICES += a40\nendef\nTARGET_DEVICES += openmesh_a40\n\ndefine Device/openmesh_a60\n  $(Device/openmesh_common_64k)\n  SOC := qca9558\n  DEVICE_MODEL := A60\n  DEVICE_PACKAGES += kmod-ath10k-ct ath10k-firmware-qca988x-ct kmod-usb2\n  OPENMESH_CE_TYPE := A60\n  SUPPORTED_DEVICES += a60\nendef\nTARGET_DEVICES += openmesh_a60\n\ndefine Device/openmesh_mr600-v1\n  $(Device/openmesh_common_64k)\n  SOC := ar9344\n  DEVICE_MODEL := MR600\n  DEVICE_VARIANT := v1\n  OPENMESH_CE_TYPE := MR600\n  SUPPORTED_DEVICES += mr600\nendef\nTARGET_DEVICES += openmesh_mr600-v1\n\ndefine Device/openmesh_mr600-v2\n  $(Device/openmesh_common_64k)\n  SOC := ar9344\n  DEVICE_MODEL := MR600\n  DEVICE_VARIANT := v2\n  OPENMESH_CE_TYPE := MR600\n  SUPPORTED_DEVICES += mr600v2\nendef\nTARGET_DEVICES += openmesh_mr600-v2\n\ndefine Device/openmesh_mr900-v1\n  $(Device/openmesh_common_64k)\n  SOC := qca9558\n  DEVICE_MODEL := MR900\n  DEVICE_VARIANT := v1\n  OPENMESH_CE_TYPE := MR900\n  SUPPORTED_DEVICES += mr900\nendef\nTARGET_DEVICES += openmesh_mr900-v1\n\ndefine Device/openmesh_mr900-v2\n  $(Device/openmesh_common_64k)\n  SOC := qca9558\n  DEVICE_MODEL := MR900\n  DEVICE_VARIANT := v2\n  OPENMESH_CE_TYPE := MR900\n  SUPPORTED_DEVICES += mr900v2\nendef\nTARGET_DEVICES += openmesh_mr900-v2\n\ndefine Device/openmesh_mr1750-v1\n  $(Device/openmesh_common_64k)\n  SOC := qca9558\n  DEVICE_MODEL := MR1750\n  DEVICE_VARIANT := v1\n  DEVICE_PACKAGES += kmod-ath10k-ct ath10k-firmware-qca988x-ct\n  OPENMESH_CE_TYPE := MR1750\n  SUPPORTED_DEVICES += mr1750\nendef\nTARGET_DEVICES += openmesh_mr1750-v1\n\ndefine Device/openmesh_mr1750-v2\n  $(Device/openmesh_common_64k)\n  SOC := qca9558\n  DEVICE_MODEL := MR1750\n  DEVICE_VARIANT := v2\n  DEVICE_PACKAGES += kmod-ath10k-ct ath10k-firmware-qca988x-ct\n  OPENMESH_CE_TYPE := MR1750\n  SUPPORTED_DEVICES += mr1750v2\nendef\nTARGET_DEVICES += openmesh_mr1750-v2\n\ndefine Device/openmesh_om2p-v1\n  $(Device/openmesh_common_256k)\n  SOC := ar7240\n  DEVICE_MODEL := OM2P\n  DEVICE_VARIANT := v1\n  OPENMESH_CE_TYPE := OM2P\n  SUPPORTED_DEVICES += om2p\nendef\nTARGET_DEVICES += openmesh_om2p-v1\n\ndefine Device/openmesh_om2p-v2\n  $(Device/openmesh_common_256k)\n  SOC := ar9330\n  DEVICE_MODEL := OM2P\n  DEVICE_VARIANT := v2\n  OPENMESH_CE_TYPE := OM2P\n  SUPPORTED_DEVICES += om2pv2\nendef\nTARGET_DEVICES += openmesh_om2p-v2\n\ndefine Device/openmesh_om2p-v4\n  $(Device/openmesh_common_256k)\n  SOC := qca9533\n  DEVICE_MODEL := OM2P\n  DEVICE_VARIANT := v4\n  OPENMESH_CE_TYPE := OM2P\n  SUPPORTED_DEVICES += om2pv4\nendef\nTARGET_DEVICES += openmesh_om2p-v4\n\ndefine Device/openmesh_om2p-hs-v1\n  $(Device/openmesh_common_256k)\n  SOC := ar9341\n  DEVICE_MODEL := OM2P-HS\n  DEVICE_VARIANT := v1\n  OPENMESH_CE_TYPE := OM2P\n  SUPPORTED_DEVICES += om2p-hs\nendef\nTARGET_DEVICES += openmesh_om2p-hs-v1\n\ndefine Device/openmesh_om2p-hs-v2\n  $(Device/openmesh_common_256k)\n  SOC := ar9341\n  DEVICE_MODEL := OM2P-HS\n  DEVICE_VARIANT := v2\n  OPENMESH_CE_TYPE := OM2P\n  SUPPORTED_DEVICES += om2p-hsv2\nendef\nTARGET_DEVICES += openmesh_om2p-hs-v2\n\ndefine Device/openmesh_om2p-hs-v3\n  $(Device/openmesh_common_256k)\n  SOC := ar9341\n  DEVICE_MODEL := OM2P-HS\n  DEVICE_VARIANT := v3\n  OPENMESH_CE_TYPE := OM2P\n  SUPPORTED_DEVICES += om2p-hsv3\nendef\nTARGET_DEVICES += openmesh_om2p-hs-v3\n\ndefine Device/openmesh_om2p-hs-v4\n  $(Device/openmesh_common_256k)\n  SOC := qca9533\n  DEVICE_MODEL := OM2P-HS\n  DEVICE_VARIANT := v4\n  OPENMESH_CE_TYPE := OM2P\n  SUPPORTED_DEVICES += om2p-hsv4\nendef\nTARGET_DEVICES += openmesh_om2p-hs-v4\n\ndefine Device/openmesh_om2p-lc\n  $(Device/openmesh_common_256k)\n  SOC := ar9330\n  DEVICE_MODEL := OM2P-LC\n  OPENMESH_CE_TYPE := OM2P\n  SUPPORTED_DEVICES += om2p-lc\nendef\nTARGET_DEVICES += openmesh_om2p-lc\n\ndefine Device/openmesh_om5p\n  $(Device/openmesh_common_64k)\n  SOC := ar9344\n  DEVICE_MODEL := OM5P\n  OPENMESH_CE_TYPE := OM5P\n  SUPPORTED_DEVICES += om5p\nendef\nTARGET_DEVICES += openmesh_om5p\n\ndefine Device/openmesh_om5p-ac-v1\n  $(Device/openmesh_common_64k)\n  SOC := qca9558\n  DEVICE_MODEL := OM5P-AC\n  DEVICE_VARIANT := v1\n  DEVICE_PACKAGES += kmod-ath10k-ct ath10k-firmware-qca988x-ct\n  OPENMESH_CE_TYPE := OM5PAC\n  SUPPORTED_DEVICES += om5p-ac\nendef\nTARGET_DEVICES += openmesh_om5p-ac-v1\n\ndefine Device/openmesh_om5p-ac-v2\n  $(Device/openmesh_common_64k)\n  SOC := qca9558\n  DEVICE_MODEL := OM5P-AC\n  DEVICE_VARIANT := v2\n  DEVICE_PACKAGES += kmod-ath10k-ct ath10k-firmware-qca988x-ct\n  OPENMESH_CE_TYPE := OM5PAC\n  SUPPORTED_DEVICES += om5p-acv2\nendef\nTARGET_DEVICES += openmesh_om5p-ac-v2\n\ndefine Device/openmesh_om5p-an\n  $(Device/openmesh_common_64k)\n  SOC := ar9344\n  DEVICE_MODEL := OM5P-AN\n  OPENMESH_CE_TYPE := OM5P\n  SUPPORTED_DEVICES += om5p-an\nendef\nTARGET_DEVICES += openmesh_om5p-an\n\ndefine Device/pcs_cap324\n  SOC := ar9344\n  DEVICE_VENDOR := PowerCloud Systems\n  DEVICE_MODEL := CAP324\n  IMAGE_SIZE := 16000k\n  SUPPORTED_DEVICES += cap324\nendef\nTARGET_DEVICES += pcs_cap324\n\ndefine Device/pcs_cr3000\n  SOC := ar9341\n  DEVICE_VENDOR := PowerCloud Systems\n  DEVICE_MODEL := CR3000\n  IMAGE_SIZE := 7808k\n  SUPPORTED_DEVICES += cr3000\nendef\nTARGET_DEVICES += pcs_cr3000\n\ndefine Device/pcs_cr5000\n  SOC := ar9344\n  DEVICE_VENDOR := PowerCloud Systems\n  DEVICE_MODEL := CR5000\n  DEVICE_PACKAGES := kmod-usb2\n  IMAGE_SIZE := 7808k\n  SUPPORTED_DEVICES += cr5000\nendef\nTARGET_DEVICES += pcs_cr5000\n\ndefine Device/phicomm_k2t\n  SOC := qca9563\n  DEVICE_VENDOR := Phicomm\n  DEVICE_MODEL := K2T\n  IMAGE_SIZE := 15744k\n  IMAGE/sysupgrade.bin := append-kernel | append-rootfs | pad-rootfs | \\\n\tcheck-size | append-metadata\n  DEVICE_PACKAGES := kmod-leds-reset kmod-ath10k-ct-smallbuffers ath10k-firmware-qca9888-ct\nendef\nTARGET_DEVICES += phicomm_k2t\n\ndefine Device/pisen_ts-d084\n  $(Device/tplink-8mlzma)\n  SOC := ar9331\n  DEVICE_VENDOR := PISEN\n  DEVICE_MODEL := TS-D084\n  DEVICE_PACKAGES := kmod-usb-chipidea2\n  TPLINK_HWID := 0x07030101\nendef\nTARGET_DEVICES += pisen_ts-d084\n\ndefine Device/pisen_wmb001n\n  $(Device/loader-okli-uimage)\n  SOC := ar9341\n  DEVICE_VENDOR := PISEN\n  DEVICE_MODEL := WMB001N\n  IMAGE_SIZE := 14080k\n  DEVICE_PACKAGES := kmod-i2c-gpio kmod-usb2\n  LOADER_FLASH_OFFS := 0x20000\n  KERNEL := kernel-bin | append-dtb | lzma | uImage lzma -M 0x4f4b4c49\n  IMAGES += factory.bin\n  IMAGE/factory.bin := $$(IMAGE/sysupgrade.bin) | pisen_wmb001n-factory $(1)\nendef\nTARGET_DEVICES += pisen_wmb001n\n\ndefine Device/pisen_wmm003n\n  $(Device/tplink-8mlzma)\n  SOC := ar9331\n  DEVICE_VENDOR := PISEN\n  DEVICE_MODEL := Cloud Easy Power (WMM003N)\n  DEVICE_PACKAGES := kmod-usb-chipidea2\n  TPLINK_HWID := 0x07030101\nendef\nTARGET_DEVICES += pisen_wmm003n\n\ndefine Device/plasmacloud_pa300-common\n  SOC := qca9533\n  DEVICE_VENDOR := Plasma Cloud\n  DEVICE_PACKAGES := uboot-envtools\n  IMAGE_SIZE := 7168k\n  IMAGES += factory.bin\n  KERNEL := kernel-bin | append-dtb | lzma | uImage lzma | pad-to $$(BLOCKSIZE)\n  IMAGE/factory.bin := append-rootfs | pad-rootfs | openmesh-image ce_type=PA300\n  IMAGE/sysupgrade.bin := append-rootfs | pad-rootfs | sysupgrade-tar rootfs=$$$$@ | append-metadata\nendef\n\ndefine Device/plasmacloud_pa300\n  $(Device/plasmacloud_pa300-common)\n  DEVICE_MODEL := PA300\nendef\nTARGET_DEVICES += plasmacloud_pa300\n\ndefine Device/plasmacloud_pa300e\n  $(Device/plasmacloud_pa300-common)\n  DEVICE_MODEL := PA300E\nendef\nTARGET_DEVICES += plasmacloud_pa300e\n\ndefine Device/qca_ap143\n  $(Device/loader-okli-uimage)\n  SOC := qca9533\n  DEVICE_VENDOR := Qualcomm Atheros\n  DEVICE_MODEL := AP143\n  DEVICE_PACKAGES := kmod-usb2\n  SUPPORTED_DEVICES += ap143\n  LOADER_FLASH_OFFS := 0x50000\n  KERNEL := kernel-bin | append-dtb | lzma | uImage lzma -M 0x4f4b4c49\nendef\n\ndefine Device/qca_ap143-8m\n  $(Device/qca_ap143)\n  DEVICE_VARIANT := (8M)\n  IMAGE_SIZE := 7744k\n  IMAGES += factory.bin\n  IMAGE/factory.bin := append-kernel | pad-to $$$$(BLOCKSIZE) | \\\n\tappend-rootfs | pad-rootfs | check-size | pad-to 6336k | \\\n\tappend-loader-okli-uimage $(1) | pad-to 64k\nendef\nTARGET_DEVICES += qca_ap143-8m\n\ndefine Device/qca_ap143-16m\n  $(Device/qca_ap143)\n  DEVICE_VARIANT := (16M)\n  IMAGE_SIZE := 15936k\n  IMAGES += factory.bin\n  IMAGE/factory.bin := append-kernel | pad-to $$$$(BLOCKSIZE) | \\\n\tappend-rootfs | pad-rootfs | check-size | pad-to 14528k | \\\n\tappend-loader-okli-uimage $(1) | pad-to 64k\nendef\nTARGET_DEVICES += qca_ap143-16m\n\ndefine Device/qihoo_c301\n  $(Device/seama)\n  SOC := ar9344\n  DEVICE_VENDOR := Qihoo\n  DEVICE_MODEL := C301\n  DEVICE_PACKAGES := kmod-usb2 kmod-ath10k-ct ath10k-firmware-qca988x-ct \\\n\tuboot-envtools\n  IMAGE_SIZE := 15744k\n  SEAMA_SIGNATURE := wrgac26_qihoo360_360rg\n  SUPPORTED_DEVICES += qihoo-c301\nendef\nTARGET_DEVICES += qihoo_c301\n\ndefine Device/qxwlan_e1700ac-v2\n  SOC := qca9563\n  DEVICE_VENDOR := Qxwlan\n  DEVICE_MODEL := E1700AC\n  DEVICE_PACKAGES := kmod-usb2 kmod-ath10k-ct ath10k-firmware-qca988x-ct\n  SUPPORTED_DEVICES += e1700ac-v2\nendef\n\ndefine Device/qxwlan_e1700ac-v2-16m\n  $(Device/qxwlan_e1700ac-v2)\n  DEVICE_VARIANT := v2 (16M)\n  IMAGE_SIZE := 15936k\nendef\nTARGET_DEVICES += qxwlan_e1700ac-v2-16m\n\ndefine Device/qxwlan_e1700ac-v2-8m\n  $(Device/qxwlan_e1700ac-v2)\n  DEVICE_VARIANT := v2 (8M)\n  IMAGE_SIZE := 7744k\nendef\nTARGET_DEVICES += qxwlan_e1700ac-v2-8m\n\ndefine Device/qxwlan_e558-v2\n  SOC := qca9558\n  DEVICE_VENDOR := Qxwlan\n  DEVICE_MODEL := E558\n  DEVICE_PACKAGES := kmod-usb2\n  SUPPORTED_DEVICES += e558-v2\nendef\n\ndefine Device/qxwlan_e558-v2-16m\n  $(Device/qxwlan_e558-v2)\n  DEVICE_VARIANT := v2 (16M)\n  IMAGE_SIZE := 15936k\nendef\nTARGET_DEVICES += qxwlan_e558-v2-16m\n\ndefine Device/qxwlan_e558-v2-8m\n  $(Device/qxwlan_e558-v2)\n  DEVICE_VARIANT := v2 (8M)\n  IMAGE_SIZE := 7744k\nendef\nTARGET_DEVICES += qxwlan_e558-v2-8m\n\ndefine Device/qxwlan_e600g-v2\n  SOC := qca9531\n  DEVICE_VENDOR := Qxwlan\n  DEVICE_MODEL := E600G\n  DEVICE_PACKAGES := kmod-usb2\n  SUPPORTED_DEVICES += e600g-v2\nendef\n\ndefine Device/qxwlan_e600g-v2-16m\n  $(Device/qxwlan_e600g-v2)\n  DEVICE_VARIANT := v2 (16M)\n  IMAGE_SIZE := 15936k\nendef\nTARGET_DEVICES += qxwlan_e600g-v2-16m\n\ndefine Device/qxwlan_e600g-v2-8m\n  $(Device/qxwlan_e600g-v2)\n  DEVICE_VARIANT := v2 (8M)\n  IMAGE_SIZE := 7744k\nendef\nTARGET_DEVICES += qxwlan_e600g-v2-8m\n\ndefine Device/qxwlan_e600gac-v2\n  SOC := qca9531\n  DEVICE_VENDOR := Qxwlan\n  DEVICE_MODEL := E600GAC\n  DEVICE_PACKAGES := kmod-ath10k-ct ath10k-firmware-qca9887-ct\n  SUPPORTED_DEVICES += e600gac-v2\nendef\n\ndefine Device/qxwlan_e600gac-v2-16m\n  $(Device/qxwlan_e600gac-v2)\n  DEVICE_VARIANT := v2 (16M)\n  IMAGE_SIZE := 15936k\nendef\nTARGET_DEVICES += qxwlan_e600gac-v2-16m\n\ndefine Device/qxwlan_e600gac-v2-8m\n  $(Device/qxwlan_e600gac-v2)\n  DEVICE_VARIANT := v2 (8M)\n  IMAGE_SIZE := 7744k\nendef\nTARGET_DEVICES += qxwlan_e600gac-v2-8m\n\ndefine Device/qxwlan_e750a-v4\n  SOC := ar9344\n  DEVICE_VENDOR := Qxwlan\n  DEVICE_MODEL := E750A\n  DEVICE_PACKAGES := kmod-usb2\n  SUPPORTED_DEVICES += e750a-v4\nendef\n\ndefine Device/qxwlan_e750a-v4-16m\n  $(Device/qxwlan_e750a-v4)\n  DEVICE_VARIANT := v4 (16M)\n  IMAGE_SIZE := 15936k\nendef\nTARGET_DEVICES += qxwlan_e750a-v4-16m\n\ndefine Device/qxwlan_e750a-v4-8m\n  $(Device/qxwlan_e750a-v4)\n  DEVICE_VARIANT := v4 (8M)\n  IMAGE_SIZE := 7744k\nendef\nTARGET_DEVICES += qxwlan_e750a-v4-8m\n\ndefine Device/qxwlan_e750g-v8\n  SOC := ar9344\n  DEVICE_VENDOR := Qxwlan\n  DEVICE_MODEL := E750G\n  DEVICE_PACKAGES := kmod-usb2\n  SUPPORTED_DEVICES += e750g-v8\nendef\n\ndefine Device/qxwlan_e750g-v8-16m\n  $(Device/qxwlan_e750g-v8)\n  DEVICE_VARIANT := v8 (16M)\n  IMAGE_SIZE := 15936k\nendef\nTARGET_DEVICES += qxwlan_e750g-v8-16m\n\ndefine Device/qxwlan_e750g-v8-8m\n  $(Device/qxwlan_e750g-v8)\n  DEVICE_VARIANT := v8 (8M)\n  IMAGE_SIZE := 7744k\nendef\nTARGET_DEVICES += qxwlan_e750g-v8-8m\n\ndefine Device/rosinson_wr818\n  SOC := qca9563\n  DEVICE_VENDOR := Rosinson\n  DEVICE_MODEL := WR818\n  IMAGE_SIZE := 15872k\n  DEVICE_PACKAGES := kmod-usb2 kmod-usb-ledtrig-usbport\nendef\nTARGET_DEVICES += rosinson_wr818\n\ndefine Device/samsung_wam250\n  SOC := ar9344\n  DEVICE_VENDOR := Samsung\n  DEVICE_MODEL := WAM250\n  IMAGE_SIZE := 15872k\n  DEVICE_PACKAGES := kmod-usb2\n  SUPPORTED_DEVICES += wam250\nendef\nTARGET_DEVICES += samsung_wam250\n\ndefine Device/siemens_ws-ap3610\n  SOC := ar7161\n  DEVICE_VENDOR := Siemens\n  DEVICE_MODEL := WS-AP3610\n  IMAGE_SIZE := 14336k\n  BLOCKSIZE := 256k\n  LOADER_TYPE := bin\n  LOADER_FLASH_OFFS := 0x82000\n  COMPILE := loader-$(1).bin\n  COMPILE/loader-$(1).bin := loader-okli-compile\n  KERNEL := kernel-bin | append-dtb | lzma | uImage lzma -M 0x4f4b4c49 | loader-okli $(1) 8128 | uImage none\n  KERNEL_INITRAMFS := kernel-bin | append-dtb | uImage none\nendef\nTARGET_DEVICES += siemens_ws-ap3610\n\ndefine Device/sitecom_wlr-7100\n  SOC := ar1022\n  DEVICE_VENDOR := Sitecom\n  DEVICE_MODEL := WLR-7100\n  DEVICE_PACKAGES := ath10k-firmware-qca988x-ct kmod-ath10k-ct-smallbuffers kmod-usb2\n  IMAGES += factory.dlf\n  IMAGE/factory.dlf := append-kernel | pad-to $$$$(BLOCKSIZE) | \\\n\tappend-rootfs | pad-rootfs | check-size | \\\n\tsenao-header -r 0x222 -p 0x53 -t 2\n  IMAGE_SIZE := 7488k\nendef\nTARGET_DEVICES += sitecom_wlr-7100\n\ndefine Device/sitecom_wlr-8100\n  SOC := qca9558\n  DEVICE_VENDOR := Sitecom\n  DEVICE_MODEL := WLR-8100\n  DEVICE_ALT0_VENDOR := Sitecom\n  DEVICE_ALT0_MODEL := X8 AC1750\n  DEVICE_PACKAGES := ath10k-firmware-qca988x-ct kmod-ath10k-ct kmod-usb2 kmod-usb3\n  SUPPORTED_DEVICES += wlr8100\n  IMAGES += factory.dlf\n  IMAGE/factory.dlf := append-kernel | pad-to $$$$(BLOCKSIZE) | \\\n\tappend-rootfs | pad-rootfs | check-size | \\\n\tsenao-header -r 0x222 -p 0x56 -t 2\n  IMAGE_SIZE := 15424k\nendef\nTARGET_DEVICES += sitecom_wlr-8100\n\ndefine Device/sophos_ap55\n  SOC := qca9558\n  DEVICE_VENDOR := Sophos\n  DEVICE_MODEL := AP55\n  DEVICE_PACKAGES := kmod-ath10k-ct ath10k-firmware-qca988x-ct kmod-usb2\n  IMAGE_SIZE := 15936k\nendef\nTARGET_DEVICES += sophos_ap55\n\ndefine Device/sophos_ap55c\n  SOC := qca9558\n  DEVICE_VENDOR := Sophos\n  DEVICE_MODEL := AP55C\n  DEVICE_PACKAGES := kmod-ath10k-ct ath10k-firmware-qca988x-ct\n  IMAGE_SIZE := 15936k\nendef\nTARGET_DEVICES += sophos_ap55c\n\ndefine Device/sophos_ap100\n  SOC := qca9558\n  DEVICE_VENDOR := Sophos\n  DEVICE_MODEL := AP100\n  DEVICE_PACKAGES := kmod-ath10k-ct ath10k-firmware-qca988x-ct kmod-usb2\n  IMAGE_SIZE := 15936k\nendef\nTARGET_DEVICES += sophos_ap100\n\ndefine Device/sophos_ap100c\n  SOC := qca9558\n  DEVICE_VENDOR := Sophos\n  DEVICE_MODEL := AP100C\n  DEVICE_PACKAGES := kmod-ath10k-ct ath10k-firmware-qca988x-ct\n  IMAGE_SIZE := 15936k\nendef\nTARGET_DEVICES += sophos_ap100c\n\ndefine Device/telco_t1\n  SOC := qca9531\n  DEVICE_VENDOR := Telco\n  DEVICE_MODEL := T1\n  DEVICE_PACKAGES := kmod-usb2 kmod-usb-net-qmi-wwan \\\n\tkmod-usb-serial-option uqmi -swconfig -uboot-envtools\n  IMAGE_SIZE := 16192k\n  SUPPORTED_DEVICES += telco_electronics,tel-t1\nendef\nTARGET_DEVICES += telco_t1\n\ndefine Device/teltonika_rut230-v1\n  SOC := ar9331\n  DEVICE_VENDOR := Teltonika\n  DEVICE_MODEL := RUT230\n  DEVICE_VARIANT := v1\n  DEVICE_PACKAGES := kmod-usb-chipidea2 kmod-usb-acm kmod-usb-net-qmi-wwan \\\n\tuqmi -uboot-envtools\n  IMAGE_SIZE := 15552k\n  TPLINK_HWID := 0x32200002\n  TPLINK_HWREV := 0x1\n  TPLINK_HEADER_VERSION := 1\n  KERNEL := kernel-bin | append-dtb | lzma | teltonika-v1-header\n  KERNEL_INITRAMFS := kernel-bin | append-dtb | lzma | uImage lzma\n  IMAGES += factory.bin\n  IMAGE/factory.bin := append-kernel | pad-to $$$$(BLOCKSIZE) | append-rootfs |\\\n\tpad-rootfs | pad-extra 64 | teltonika-fw-fake-checksum 54 | check-size\n  IMAGE/sysupgrade.bin := append-kernel | pad-to $$$$(BLOCKSIZE) |\\\n\tappend-rootfs | pad-rootfs | append-metadata |\\\n\tcheck-size\nendef\nTARGET_DEVICES += teltonika_rut230-v1\n\ndefine Device/teltonika_rut955\n  SOC := ar9344\n  DEVICE_VENDOR := Teltonika\n  DEVICE_MODEL := RUT955\n  DEVICE_PACKAGES := kmod-usb2 kmod-usb-acm kmod-usb-net-qmi-wwan \\\n\tkmod-usb-serial-option kmod-hwmon-mcp3021 uqmi -uboot-envtools\n  IMAGE_SIZE := 15552k\n  TPLINK_HWID := 0x35000001\n  TPLINK_HWREV := 0x1\n  TPLINK_HEADER_VERSION := 1\n  KERNEL := kernel-bin | append-dtb | lzma | tplink-v1-header\n  KERNEL_INITRAMFS := kernel-bin | append-dtb | lzma | uImage lzma\n  IMAGES += factory.bin\n  IMAGE/factory.bin := append-kernel | pad-to $$$$(BLOCKSIZE) | append-rootfs |\\\n\tpad-rootfs | teltonika-fw-fake-checksum 20 | append-string master |\\\n\tappend-md5sum-bin | check-size\n  IMAGE/sysupgrade.bin := append-kernel | pad-to $$$$(BLOCKSIZE) |\\\n\tappend-rootfs | pad-rootfs | check-size | append-metadata\nendef\nTARGET_DEVICES += teltonika_rut955\n\ndefine Device/teltonika_rut955-h7v3c0\n  $(Device/teltonika_rut955)\n  DEVICE_VARIANT := H7V3C0\nendef\nTARGET_DEVICES += teltonika_rut955-h7v3c0\n\ndefine Device/trendnet_tew-823dru\n  SOC := qca9558\n  DEVICE_VENDOR := Trendnet\n  DEVICE_MODEL := TEW-823DRU\n  DEVICE_VARIANT := v1.0R\n  DEVICE_PACKAGES := kmod-usb2 kmod-ath10k-ct ath10k-firmware-qca988x-ct\n  SUPPORTED_DEVICES += tew-823dru\n  IMAGE_SIZE := 15296k\n  IMAGES := factory.bin sysupgrade.bin\n  IMAGE/default := append-kernel | pad-to $$$$(BLOCKSIZE) | append-rootfs | \\\n\tpad-rootfs\n  IMAGE/factory.bin := $$(IMAGE/default) | pad-offset $$$$(IMAGE_SIZE) 26 | \\\n\tappend-string 00AP135AR9558-RT-131129-00 | check-size\n  IMAGE/sysupgrade.bin := $$(IMAGE/default) | check-size | append-metadata\nendef\nTARGET_DEVICES += trendnet_tew-823dru\n\ndefine Device/wallys_dr531\n  SOC := qca9531\n  DEVICE_VENDOR := Wallys\n  DEVICE_MODEL := DR531\n  DEVICE_PACKAGES := kmod-usb2 rssileds\n  IMAGE_SIZE := 7808k\n  SUPPORTED_DEVICES += dr531\nendef\nTARGET_DEVICES += wallys_dr531\n\ndefine Device/wd_mynet-n600\n  $(Device/seama)\n  SOC := ar9344\n  DEVICE_VENDOR := Western Digital\n  DEVICE_MODEL := My Net N600\n  IMAGE_SIZE := 15872k\n  DEVICE_PACKAGES := kmod-usb2\n  SEAMA_SIGNATURE := wrgnd16_wd_db600\n  SUPPORTED_DEVICES += mynet-n600\nendef\nTARGET_DEVICES += wd_mynet-n600\n\ndefine Device/wd_mynet-n750\n  $(Device/seama)\n  SOC := ar9344\n  DEVICE_VENDOR := Western Digital\n  DEVICE_MODEL := My Net N750\n  IMAGE_SIZE := 15872k\n  DEVICE_PACKAGES := kmod-usb2\n  SEAMA_SIGNATURE := wrgnd13_wd_av\n  SUPPORTED_DEVICES += mynet-n750\nendef\nTARGET_DEVICES += wd_mynet-n750\n\ndefine Device/wd_mynet-wifi-rangeextender\n  SOC := ar9344\n  DEVICE_VENDOR := Western Digital\n  DEVICE_MODEL := My Net Wi-Fi Range Extender\n  DEVICE_PACKAGES := rssileds nvram -swconfig\n  IMAGE_SIZE := 7808k\n  ADDPATTERN_ID := mynet-rext\n  ADDPATTERN_VERSION := 1.00.01\n  IMAGE/sysupgrade.bin := append-rootfs | pad-rootfs | cybertan-trx | \\\n\taddpattern | append-metadata\n  SUPPORTED_DEVICES += mynet-rext\nendef\nTARGET_DEVICES += wd_mynet-wifi-rangeextender\n\ndefine Device/winchannel_wb2000\n  SOC := ar9344\n  DEVICE_VENDOR := Winchannel\n  DEVICE_MODEL := WB2000\n  IMAGE_SIZE := 15872k\n  DEVICE_PACKAGES := kmod-i2c-gpio kmod-rtc-ds1307 kmod-usb2 \\\n\tkmod-usb-ledtrig-usbport\nendef\nTARGET_DEVICES += winchannel_wb2000\n\ndefine Device/xiaomi_aiot-ac2350\n  SOC := qca9563\n  DEVICE_VENDOR := Xiaomi\n  DEVICE_MODEL := AIoT AC2350\n  DEVICE_PACKAGES := kmod-ath10k-ct ath10k-firmware-qca9984-ct\n  IMAGE_SIZE := 14336k\nendef\nTARGET_DEVICES += xiaomi_aiot-ac2350\n\ndefine Device/xiaomi_mi-router-4q\n  SOC := qca9561\n  DEVICE_VENDOR := Xiaomi\n  DEVICE_MODEL := Mi Router 4Q\n  IMAGE_SIZE := 14336k\nendef\nTARGET_DEVICES += xiaomi_mi-router-4q\n\ndefine Device/yuncore_a770\n  SOC := qca9531\n  DEVICE_VENDOR := YunCore\n  DEVICE_MODEL := A770\n  DEVICE_PACKAGES := kmod-ath10k-ct ath10k-firmware-qca9887-ct\n  IMAGE_SIZE := 16000k\n  IMAGES += tftp.bin\n  IMAGE/tftp.bin := $$(IMAGE/sysupgrade.bin) | yuncore-tftp-header-16m\nendef\nTARGET_DEVICES += yuncore_a770\n\ndefine Device/yuncore_a782\n  SOC := qca9563\n  DEVICE_VENDOR := YunCore\n  DEVICE_MODEL := A782\n  DEVICE_PACKAGES := kmod-ath10k-ct ath10k-firmware-qca9888-ct\n  IMAGE_SIZE := 16000k\n  IMAGES += tftp.bin\n  IMAGE/tftp.bin := $$(IMAGE/sysupgrade.bin) | yuncore-tftp-header-16m\nendef\nTARGET_DEVICES += yuncore_a782\n\ndefine Device/yuncore_a930\n  SOC := qca9533\n  DEVICE_VENDOR := YunCore\n  DEVICE_MODEL := A930\n  IMAGE_SIZE := 16000k\n  IMAGES += tftp.bin\n  IMAGE/tftp.bin := $$(IMAGE/sysupgrade.bin) | yuncore-tftp-header-16m\nendef\nTARGET_DEVICES += yuncore_a930\n\ndefine Device/yuncore_xd3200\n  SOC := qca9563\n  DEVICE_VENDOR := YunCore\n  DEVICE_MODEL := XD3200\n  DEVICE_PACKAGES := kmod-ath10k-ct ath10k-firmware-qca988x-ct\n  IMAGE_SIZE := 16000k\n  IMAGES += tftp.bin\n  IMAGE/tftp.bin := $$(IMAGE/sysupgrade.bin) | yuncore-tftp-header-16m\nendef\nTARGET_DEVICES += yuncore_xd3200\n\ndefine Device/yuncore_xd4200\n  SOC := qca9563\n  DEVICE_VENDOR := YunCore\n  DEVICE_MODEL := XD4200\n  DEVICE_PACKAGES := kmod-ath10k-ct ath10k-firmware-qca9888-ct\n  IMAGE_SIZE := 16000k\n  IMAGES += tftp.bin\n  IMAGE/tftp.bin := $$(IMAGE/sysupgrade.bin) | yuncore-tftp-header-16m\nendef\nTARGET_DEVICES += yuncore_xd4200\n\ndefine Device/ziking_cpe46b\n  SOC := ar9330\n  DEVICE_VENDOR := ZiKing\n  DEVICE_MODEL := CPE46B\n  IMAGE_SIZE := 8000k\n  DEVICE_PACKAGES := kmod-i2c-gpio\nendef\nTARGET_DEVICES += ziking_cpe46b\n\ndefine Device/zbtlink_zbt-wd323\n  SOC := ar9344\n  DEVICE_VENDOR := ZBT\n  DEVICE_MODEL := WD323\n  IMAGE_SIZE := 16000k\n  DEVICE_PACKAGES := kmod-usb2 kmod-i2c-gpio kmod-rtc-pcf8563 \\\n\tkmod-usb-serial-cp210x uqmi\nendef\nTARGET_DEVICES += zbtlink_zbt-wd323\n\ndefine Device/zyxel_nbg6616\n  SOC := qca9557\n  DEVICE_VENDOR := ZyXEL\n  DEVICE_MODEL := NBG6616\n  DEVICE_PACKAGES := kmod-usb2 kmod-usb-ledtrig-usbport kmod-rtc-pcf8563 \\\n\tkmod-ath10k-ct ath10k-firmware-qca988x-ct\n  IMAGE_SIZE := 15232k\n  RAS_BOARD := NBG6616\n  RAS_ROOTFS_SIZE := 14464k\n  RAS_VERSION := \"OpenWrt Linux-$(LINUX_VERSION)\"\n  IMAGES += factory.bin\n  IMAGE/factory.bin := append-kernel | pad-to $$$$(BLOCKSIZE) | \\\n\tappend-rootfs | pad-rootfs | pad-to 64k | check-size | zyxel-ras-image\n  SUPPORTED_DEVICES += nbg6616\nendef\nTARGET_DEVICES += zyxel_nbg6616\n"
  },
  {
    "path": "target/linux/ath79/image/lzma-loader/Makefile",
    "content": "#\n# Copyright (C) 2011 OpenWrt.org\n# Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nLZMA_TEXT_START\t:= 0x81800000\nLOADADDR\t:= 0x80060000\nLOADER\t\t:= loader.bin\nLOADER_NAME\t:= $(basename $(notdir $(LOADER)))\nLOADER_DATA\t:=\nKERNEL_MAGIC\t:=\nTARGET_DIR\t:=\nFLASH_OFFS\t:=\nFLASH_MAX\t:=\nBOARD\t\t:=\n\nifeq ($(TARGET_DIR),)\nTARGET_DIR\t:= $(KDIR)\nendif\n\nLOADER_BIN\t:= $(TARGET_DIR)/$(LOADER_NAME).bin\nLOADER_GZ\t:= $(TARGET_DIR)/$(LOADER_NAME).gz\nLOADER_ELF\t:= $(TARGET_DIR)/$(LOADER_NAME).elf\n\nPKG_NAME := lzma-loader\nPKG_BUILD_DIR := $(KDIR)/$(PKG_NAME)\n\n.PHONY : loader-compile loader.bin loader.elf loader.gz\n\n$(PKG_BUILD_DIR)/.prepared:\n\tmkdir $(PKG_BUILD_DIR)\n\t$(CP) ./src/* $(PKG_BUILD_DIR)/\n\ttouch $@\n\nloader-compile: $(PKG_BUILD_DIR)/.prepared\n\t$(MAKE) -C $(PKG_BUILD_DIR) CROSS_COMPILE=\"$(TARGET_CROSS)\" \\\n\t\tLZMA_TEXT_START=$(LZMA_TEXT_START) \\\n\t\tLOADADDR=$(LOADADDR) \\\n\t\tLOADER_DATA=$(LOADER_DATA) \\\n\t\tKERNEL_MAGIC=$(KERNEL_MAGIC) \\\n\t\tFLASH_OFFS=$(FLASH_OFFS) \\\n\t\tFLASH_MAX=$(FLASH_MAX) \\\n\t\tBOARD=\"$(BOARD)\" \\\n\t\tclean all\n\nloader.gz: $(PKG_BUILD_DIR)/loader.bin\n\t# Workaround for buggy bootloaders: Some devices\n\t# (TP-Link TL-WR1043ND v1) don't work correctly when\n\t# the uncompressed loader is too small (probably a cache\n\t# invalidation issue)\n\tdd if=$< bs=512K conv=sync | gzip -nc9 > $(LOADER_GZ)\n\nloader.elf: $(PKG_BUILD_DIR)/loader.elf\n\t$(CP) $< $(LOADER_ELF)\n\nloader.bin: $(PKG_BUILD_DIR)/loader.bin\n\t$(CP) $< $(LOADER_BIN)\n\ndownload:\nprepare: $(PKG_BUILD_DIR)/.prepared\ncompile: loader-compile\n\ninstall:\n\nclean:\n\trm -rf $(PKG_BUILD_DIR)\n\n"
  },
  {
    "path": "target/linux/ath79/image/lzma-loader/src/LzmaDecode.c",
    "content": "/*\n  LzmaDecode.c\n  LZMA Decoder (optimized for Speed version)\n  \n  LZMA SDK 4.40 Copyright (c) 1999-2006 Igor Pavlov (2006-05-01)\n  http://www.7-zip.org/\n\n  LZMA SDK is licensed under two licenses:\n  1) GNU Lesser General Public License (GNU LGPL)\n  2) Common Public License (CPL)\n  It means that you can select one of these two licenses and \n  follow rules of that license.\n\n  SPECIAL EXCEPTION:\n  Igor Pavlov, as the author of this Code, expressly permits you to \n  statically or dynamically link your Code (or bind by name) to the \n  interfaces of this file without subjecting your linked Code to the \n  terms of the CPL or GNU LGPL. Any modifications or additions \n  to this file, however, are subject to the LGPL or CPL terms.\n*/\n\n#include \"LzmaDecode.h\"\n\n#define kNumTopBits 24\n#define kTopValue ((UInt32)1 << kNumTopBits)\n\n#define kNumBitModelTotalBits 11\n#define kBitModelTotal (1 << kNumBitModelTotalBits)\n#define kNumMoveBits 5\n\n#define RC_READ_BYTE (*Buffer++)\n\n#define RC_INIT2 Code = 0; Range = 0xFFFFFFFF; \\\n  { int i; for(i = 0; i < 5; i++) { RC_TEST; Code = (Code << 8) | RC_READ_BYTE; }}\n\n#ifdef _LZMA_IN_CB\n\n#define RC_TEST { if (Buffer == BufferLim) \\\n  { SizeT size; int result = InCallback->Read(InCallback, &Buffer, &size); if (result != LZMA_RESULT_OK) return result; \\\n  BufferLim = Buffer + size; if (size == 0) return LZMA_RESULT_DATA_ERROR; }}\n\n#define RC_INIT Buffer = BufferLim = 0; RC_INIT2\n\n#else\n\n#define RC_TEST { if (Buffer == BufferLim) return LZMA_RESULT_DATA_ERROR; }\n\n#define RC_INIT(buffer, bufferSize) Buffer = buffer; BufferLim = buffer + bufferSize; RC_INIT2\n \n#endif\n\n#define RC_NORMALIZE if (Range < kTopValue) { RC_TEST; Range <<= 8; Code = (Code << 8) | RC_READ_BYTE; }\n\n#define IfBit0(p) RC_NORMALIZE; bound = (Range >> kNumBitModelTotalBits) * *(p); if (Code < bound)\n#define UpdateBit0(p) Range = bound; *(p) += (kBitModelTotal - *(p)) >> kNumMoveBits;\n#define UpdateBit1(p) Range -= bound; Code -= bound; *(p) -= (*(p)) >> kNumMoveBits;\n\n#define RC_GET_BIT2(p, mi, A0, A1) IfBit0(p) \\\n  { UpdateBit0(p); mi <<= 1; A0; } else \\\n  { UpdateBit1(p); mi = (mi + mi) + 1; A1; } \n  \n#define RC_GET_BIT(p, mi) RC_GET_BIT2(p, mi, ; , ;)               \n\n#define RangeDecoderBitTreeDecode(probs, numLevels, res) \\\n  { int i = numLevels; res = 1; \\\n  do { CProb *p = probs + res; RC_GET_BIT(p, res) } while(--i != 0); \\\n  res -= (1 << numLevels); }\n\n\n#define kNumPosBitsMax 4\n#define kNumPosStatesMax (1 << kNumPosBitsMax)\n\n#define kLenNumLowBits 3\n#define kLenNumLowSymbols (1 << kLenNumLowBits)\n#define kLenNumMidBits 3\n#define kLenNumMidSymbols (1 << kLenNumMidBits)\n#define kLenNumHighBits 8\n#define kLenNumHighSymbols (1 << kLenNumHighBits)\n\n#define LenChoice 0\n#define LenChoice2 (LenChoice + 1)\n#define LenLow (LenChoice2 + 1)\n#define LenMid (LenLow + (kNumPosStatesMax << kLenNumLowBits))\n#define LenHigh (LenMid + (kNumPosStatesMax << kLenNumMidBits))\n#define kNumLenProbs (LenHigh + kLenNumHighSymbols) \n\n\n#define kNumStates 12\n#define kNumLitStates 7\n\n#define kStartPosModelIndex 4\n#define kEndPosModelIndex 14\n#define kNumFullDistances (1 << (kEndPosModelIndex >> 1))\n\n#define kNumPosSlotBits 6\n#define kNumLenToPosStates 4\n\n#define kNumAlignBits 4\n#define kAlignTableSize (1 << kNumAlignBits)\n\n#define kMatchMinLen 2\n\n#define IsMatch 0\n#define IsRep (IsMatch + (kNumStates << kNumPosBitsMax))\n#define IsRepG0 (IsRep + kNumStates)\n#define IsRepG1 (IsRepG0 + kNumStates)\n#define IsRepG2 (IsRepG1 + kNumStates)\n#define IsRep0Long (IsRepG2 + kNumStates)\n#define PosSlot (IsRep0Long + (kNumStates << kNumPosBitsMax))\n#define SpecPos (PosSlot + (kNumLenToPosStates << kNumPosSlotBits))\n#define Align (SpecPos + kNumFullDistances - kEndPosModelIndex)\n#define LenCoder (Align + kAlignTableSize)\n#define RepLenCoder (LenCoder + kNumLenProbs)\n#define Literal (RepLenCoder + kNumLenProbs)\n\n#if Literal != LZMA_BASE_SIZE\nStopCompilingDueBUG\n#endif\n\nint LzmaDecodeProperties(CLzmaProperties *propsRes, const unsigned char *propsData, int size)\n{\n  unsigned char prop0;\n  if (size < LZMA_PROPERTIES_SIZE)\n    return LZMA_RESULT_DATA_ERROR;\n  prop0 = propsData[0];\n  if (prop0 >= (9 * 5 * 5))\n    return LZMA_RESULT_DATA_ERROR;\n  {\n    for (propsRes->pb = 0; prop0 >= (9 * 5); propsRes->pb++, prop0 -= (9 * 5));\n    for (propsRes->lp = 0; prop0 >= 9; propsRes->lp++, prop0 -= 9);\n    propsRes->lc = prop0;\n    /*\n    unsigned char remainder = (unsigned char)(prop0 / 9);\n    propsRes->lc = prop0 % 9;\n    propsRes->pb = remainder / 5;\n    propsRes->lp = remainder % 5;\n    */\n  }\n\n  #ifdef _LZMA_OUT_READ\n  {\n    int i;\n    propsRes->DictionarySize = 0;\n    for (i = 0; i < 4; i++)\n      propsRes->DictionarySize += (UInt32)(propsData[1 + i]) << (i * 8);\n    if (propsRes->DictionarySize == 0)\n      propsRes->DictionarySize = 1;\n  }\n  #endif\n  return LZMA_RESULT_OK;\n}\n\n#define kLzmaStreamWasFinishedId (-1)\n\nint LzmaDecode(CLzmaDecoderState *vs,\n    #ifdef _LZMA_IN_CB\n    ILzmaInCallback *InCallback,\n    #else\n    const unsigned char *inStream, SizeT inSize, SizeT *inSizeProcessed,\n    #endif\n    unsigned char *outStream, SizeT outSize, SizeT *outSizeProcessed)\n{\n  CProb *p = vs->Probs;\n  SizeT nowPos = 0;\n  Byte previousByte = 0;\n  UInt32 posStateMask = (1 << (vs->Properties.pb)) - 1;\n  UInt32 literalPosMask = (1 << (vs->Properties.lp)) - 1;\n  int lc = vs->Properties.lc;\n\n  #ifdef _LZMA_OUT_READ\n  \n  UInt32 Range = vs->Range;\n  UInt32 Code = vs->Code;\n  #ifdef _LZMA_IN_CB\n  const Byte *Buffer = vs->Buffer;\n  const Byte *BufferLim = vs->BufferLim;\n  #else\n  const Byte *Buffer = inStream;\n  const Byte *BufferLim = inStream + inSize;\n  #endif\n  int state = vs->State;\n  UInt32 rep0 = vs->Reps[0], rep1 = vs->Reps[1], rep2 = vs->Reps[2], rep3 = vs->Reps[3];\n  int len = vs->RemainLen;\n  UInt32 globalPos = vs->GlobalPos;\n  UInt32 distanceLimit = vs->DistanceLimit;\n\n  Byte *dictionary = vs->Dictionary;\n  UInt32 dictionarySize = vs->Properties.DictionarySize;\n  UInt32 dictionaryPos = vs->DictionaryPos;\n\n  Byte tempDictionary[4];\n\n  #ifndef _LZMA_IN_CB\n  *inSizeProcessed = 0;\n  #endif\n  *outSizeProcessed = 0;\n  if (len == kLzmaStreamWasFinishedId)\n    return LZMA_RESULT_OK;\n\n  if (dictionarySize == 0)\n  {\n    dictionary = tempDictionary;\n    dictionarySize = 1;\n    tempDictionary[0] = vs->TempDictionary[0];\n  }\n\n  if (len == kLzmaNeedInitId)\n  {\n    {\n      UInt32 numProbs = Literal + ((UInt32)LZMA_LIT_SIZE << (lc + vs->Properties.lp));\n      UInt32 i;\n      for (i = 0; i < numProbs; i++)\n        p[i] = kBitModelTotal >> 1; \n      rep0 = rep1 = rep2 = rep3 = 1;\n      state = 0;\n      globalPos = 0;\n      distanceLimit = 0;\n      dictionaryPos = 0;\n      dictionary[dictionarySize - 1] = 0;\n      #ifdef _LZMA_IN_CB\n      RC_INIT;\n      #else\n      RC_INIT(inStream, inSize);\n      #endif\n    }\n    len = 0;\n  }\n  while(len != 0 && nowPos < outSize)\n  {\n    UInt32 pos = dictionaryPos - rep0;\n    if (pos >= dictionarySize)\n      pos += dictionarySize;\n    outStream[nowPos++] = dictionary[dictionaryPos] = dictionary[pos];\n    if (++dictionaryPos == dictionarySize)\n      dictionaryPos = 0;\n    len--;\n  }\n  if (dictionaryPos == 0)\n    previousByte = dictionary[dictionarySize - 1];\n  else\n    previousByte = dictionary[dictionaryPos - 1];\n\n  #else /* if !_LZMA_OUT_READ */\n\n  int state = 0;\n  UInt32 rep0 = 1, rep1 = 1, rep2 = 1, rep3 = 1;\n  int len = 0;\n  const Byte *Buffer;\n  const Byte *BufferLim;\n  UInt32 Range;\n  UInt32 Code;\n\n  #ifndef _LZMA_IN_CB\n  *inSizeProcessed = 0;\n  #endif\n  *outSizeProcessed = 0;\n\n  {\n    UInt32 i;\n    UInt32 numProbs = Literal + ((UInt32)LZMA_LIT_SIZE << (lc + vs->Properties.lp));\n    for (i = 0; i < numProbs; i++)\n      p[i] = kBitModelTotal >> 1;\n  }\n  \n  #ifdef _LZMA_IN_CB\n  RC_INIT;\n  #else\n  RC_INIT(inStream, inSize);\n  #endif\n\n  #endif /* _LZMA_OUT_READ */\n\n  while(nowPos < outSize)\n  {\n    CProb *prob;\n    UInt32 bound;\n    int posState = (int)(\n        (nowPos \n        #ifdef _LZMA_OUT_READ\n        + globalPos\n        #endif\n        )\n        & posStateMask);\n\n    prob = p + IsMatch + (state << kNumPosBitsMax) + posState;\n    IfBit0(prob)\n    {\n      int symbol = 1;\n      UpdateBit0(prob)\n      prob = p + Literal + (LZMA_LIT_SIZE * \n        (((\n        (nowPos \n        #ifdef _LZMA_OUT_READ\n        + globalPos\n        #endif\n        )\n        & literalPosMask) << lc) + (previousByte >> (8 - lc))));\n\n      if (state >= kNumLitStates)\n      {\n        int matchByte;\n        #ifdef _LZMA_OUT_READ\n        UInt32 pos = dictionaryPos - rep0;\n        if (pos >= dictionarySize)\n          pos += dictionarySize;\n        matchByte = dictionary[pos];\n        #else\n        matchByte = outStream[nowPos - rep0];\n        #endif\n        do\n        {\n          int bit;\n          CProb *probLit;\n          matchByte <<= 1;\n          bit = (matchByte & 0x100);\n          probLit = prob + 0x100 + bit + symbol;\n          RC_GET_BIT2(probLit, symbol, if (bit != 0) break, if (bit == 0) break)\n        }\n        while (symbol < 0x100);\n      }\n      while (symbol < 0x100)\n      {\n        CProb *probLit = prob + symbol;\n        RC_GET_BIT(probLit, symbol)\n      }\n      previousByte = (Byte)symbol;\n\n      outStream[nowPos++] = previousByte;\n      #ifdef _LZMA_OUT_READ\n      if (distanceLimit < dictionarySize)\n        distanceLimit++;\n\n      dictionary[dictionaryPos] = previousByte;\n      if (++dictionaryPos == dictionarySize)\n        dictionaryPos = 0;\n      #endif\n      if (state < 4) state = 0;\n      else if (state < 10) state -= 3;\n      else state -= 6;\n    }\n    else             \n    {\n      UpdateBit1(prob);\n      prob = p + IsRep + state;\n      IfBit0(prob)\n      {\n        UpdateBit0(prob);\n        rep3 = rep2;\n        rep2 = rep1;\n        rep1 = rep0;\n        state = state < kNumLitStates ? 0 : 3;\n        prob = p + LenCoder;\n      }\n      else\n      {\n        UpdateBit1(prob);\n        prob = p + IsRepG0 + state;\n        IfBit0(prob)\n        {\n          UpdateBit0(prob);\n          prob = p + IsRep0Long + (state << kNumPosBitsMax) + posState;\n          IfBit0(prob)\n          {\n            #ifdef _LZMA_OUT_READ\n            UInt32 pos;\n            #endif\n            UpdateBit0(prob);\n            \n            #ifdef _LZMA_OUT_READ\n            if (distanceLimit == 0)\n            #else\n            if (nowPos == 0)\n            #endif\n              return LZMA_RESULT_DATA_ERROR;\n            \n            state = state < kNumLitStates ? 9 : 11;\n            #ifdef _LZMA_OUT_READ\n            pos = dictionaryPos - rep0;\n            if (pos >= dictionarySize)\n              pos += dictionarySize;\n            previousByte = dictionary[pos];\n            dictionary[dictionaryPos] = previousByte;\n            if (++dictionaryPos == dictionarySize)\n              dictionaryPos = 0;\n            #else\n            previousByte = outStream[nowPos - rep0];\n            #endif\n            outStream[nowPos++] = previousByte;\n            #ifdef _LZMA_OUT_READ\n            if (distanceLimit < dictionarySize)\n              distanceLimit++;\n            #endif\n\n            continue;\n          }\n          else\n          {\n            UpdateBit1(prob);\n          }\n        }\n        else\n        {\n          UInt32 distance;\n          UpdateBit1(prob);\n          prob = p + IsRepG1 + state;\n          IfBit0(prob)\n          {\n            UpdateBit0(prob);\n            distance = rep1;\n          }\n          else \n          {\n            UpdateBit1(prob);\n            prob = p + IsRepG2 + state;\n            IfBit0(prob)\n            {\n              UpdateBit0(prob);\n              distance = rep2;\n            }\n            else\n            {\n              UpdateBit1(prob);\n              distance = rep3;\n              rep3 = rep2;\n            }\n            rep2 = rep1;\n          }\n          rep1 = rep0;\n          rep0 = distance;\n        }\n        state = state < kNumLitStates ? 8 : 11;\n        prob = p + RepLenCoder;\n      }\n      {\n        int numBits, offset;\n        CProb *probLen = prob + LenChoice;\n        IfBit0(probLen)\n        {\n          UpdateBit0(probLen);\n          probLen = prob + LenLow + (posState << kLenNumLowBits);\n          offset = 0;\n          numBits = kLenNumLowBits;\n        }\n        else\n        {\n          UpdateBit1(probLen);\n          probLen = prob + LenChoice2;\n          IfBit0(probLen)\n          {\n            UpdateBit0(probLen);\n            probLen = prob + LenMid + (posState << kLenNumMidBits);\n            offset = kLenNumLowSymbols;\n            numBits = kLenNumMidBits;\n          }\n          else\n          {\n            UpdateBit1(probLen);\n            probLen = prob + LenHigh;\n            offset = kLenNumLowSymbols + kLenNumMidSymbols;\n            numBits = kLenNumHighBits;\n          }\n        }\n        RangeDecoderBitTreeDecode(probLen, numBits, len);\n        len += offset;\n      }\n\n      if (state < 4)\n      {\n        int posSlot;\n        state += kNumLitStates;\n        prob = p + PosSlot +\n            ((len < kNumLenToPosStates ? len : kNumLenToPosStates - 1) << \n            kNumPosSlotBits);\n        RangeDecoderBitTreeDecode(prob, kNumPosSlotBits, posSlot);\n        if (posSlot >= kStartPosModelIndex)\n        {\n          int numDirectBits = ((posSlot >> 1) - 1);\n          rep0 = (2 | ((UInt32)posSlot & 1));\n          if (posSlot < kEndPosModelIndex)\n          {\n            rep0 <<= numDirectBits;\n            prob = p + SpecPos + rep0 - posSlot - 1;\n          }\n          else\n          {\n            numDirectBits -= kNumAlignBits;\n            do\n            {\n              RC_NORMALIZE\n              Range >>= 1;\n              rep0 <<= 1;\n              if (Code >= Range)\n              {\n                Code -= Range;\n                rep0 |= 1;\n              }\n            }\n            while (--numDirectBits != 0);\n            prob = p + Align;\n            rep0 <<= kNumAlignBits;\n            numDirectBits = kNumAlignBits;\n          }\n          {\n            int i = 1;\n            int mi = 1;\n            do\n            {\n              CProb *prob3 = prob + mi;\n              RC_GET_BIT2(prob3, mi, ; , rep0 |= i);\n              i <<= 1;\n            }\n            while(--numDirectBits != 0);\n          }\n        }\n        else\n          rep0 = posSlot;\n        if (++rep0 == (UInt32)(0))\n        {\n          /* it's for stream version */\n          len = kLzmaStreamWasFinishedId;\n          break;\n        }\n      }\n\n      len += kMatchMinLen;\n      #ifdef _LZMA_OUT_READ\n      if (rep0 > distanceLimit) \n      #else\n      if (rep0 > nowPos)\n      #endif\n        return LZMA_RESULT_DATA_ERROR;\n\n      #ifdef _LZMA_OUT_READ\n      if (dictionarySize - distanceLimit > (UInt32)len)\n        distanceLimit += len;\n      else\n        distanceLimit = dictionarySize;\n      #endif\n\n      do\n      {\n        #ifdef _LZMA_OUT_READ\n        UInt32 pos = dictionaryPos - rep0;\n        if (pos >= dictionarySize)\n          pos += dictionarySize;\n        previousByte = dictionary[pos];\n        dictionary[dictionaryPos] = previousByte;\n        if (++dictionaryPos == dictionarySize)\n          dictionaryPos = 0;\n        #else\n        previousByte = outStream[nowPos - rep0];\n        #endif\n        len--;\n        outStream[nowPos++] = previousByte;\n      }\n      while(len != 0 && nowPos < outSize);\n    }\n  }\n  RC_NORMALIZE;\n\n  #ifdef _LZMA_OUT_READ\n  vs->Range = Range;\n  vs->Code = Code;\n  vs->DictionaryPos = dictionaryPos;\n  vs->GlobalPos = globalPos + (UInt32)nowPos;\n  vs->DistanceLimit = distanceLimit;\n  vs->Reps[0] = rep0;\n  vs->Reps[1] = rep1;\n  vs->Reps[2] = rep2;\n  vs->Reps[3] = rep3;\n  vs->State = state;\n  vs->RemainLen = len;\n  vs->TempDictionary[0] = tempDictionary[0];\n  #endif\n\n  #ifdef _LZMA_IN_CB\n  vs->Buffer = Buffer;\n  vs->BufferLim = BufferLim;\n  #else\n  *inSizeProcessed = (SizeT)(Buffer - inStream);\n  #endif\n  *outSizeProcessed = nowPos;\n  return LZMA_RESULT_OK;\n}\n"
  },
  {
    "path": "target/linux/ath79/image/lzma-loader/src/LzmaDecode.h",
    "content": "/* \n  LzmaDecode.h\n  LZMA Decoder interface\n\n  LZMA SDK 4.40 Copyright (c) 1999-2006 Igor Pavlov (2006-05-01)\n  http://www.7-zip.org/\n\n  LZMA SDK is licensed under two licenses:\n  1) GNU Lesser General Public License (GNU LGPL)\n  2) Common Public License (CPL)\n  It means that you can select one of these two licenses and \n  follow rules of that license.\n\n  SPECIAL EXCEPTION:\n  Igor Pavlov, as the author of this code, expressly permits you to \n  statically or dynamically link your code (or bind by name) to the \n  interfaces of this file without subjecting your linked code to the \n  terms of the CPL or GNU LGPL. Any modifications or additions \n  to this file, however, are subject to the LGPL or CPL terms.\n*/\n\n#ifndef __LZMADECODE_H\n#define __LZMADECODE_H\n\n#include \"LzmaTypes.h\"\n\n/* #define _LZMA_IN_CB */\n/* Use callback for input data */\n\n/* #define _LZMA_OUT_READ */\n/* Use read function for output data */\n\n/* #define _LZMA_PROB32 */\n/* It can increase speed on some 32-bit CPUs, \n   but memory usage will be doubled in that case */\n\n/* #define _LZMA_LOC_OPT */\n/* Enable local speed optimizations inside code */\n\n#ifdef _LZMA_PROB32\n#define CProb UInt32\n#else\n#define CProb UInt16\n#endif\n\n#define LZMA_RESULT_OK 0\n#define LZMA_RESULT_DATA_ERROR 1\n\n#ifdef _LZMA_IN_CB\ntypedef struct _ILzmaInCallback\n{\n  int (*Read)(void *object, const unsigned char **buffer, SizeT *bufferSize);\n} ILzmaInCallback;\n#endif\n\n#define LZMA_BASE_SIZE 1846\n#define LZMA_LIT_SIZE 768\n\n#define LZMA_PROPERTIES_SIZE 5\n\ntypedef struct _CLzmaProperties\n{\n  int lc;\n  int lp;\n  int pb;\n  #ifdef _LZMA_OUT_READ\n  UInt32 DictionarySize;\n  #endif\n}CLzmaProperties;\n\nint LzmaDecodeProperties(CLzmaProperties *propsRes, const unsigned char *propsData, int size);\n\n#define LzmaGetNumProbs(Properties) (LZMA_BASE_SIZE + (LZMA_LIT_SIZE << ((Properties)->lc + (Properties)->lp)))\n\n#define kLzmaNeedInitId (-2)\n\ntypedef struct _CLzmaDecoderState\n{\n  CLzmaProperties Properties;\n  CProb *Probs;\n\n  #ifdef _LZMA_IN_CB\n  const unsigned char *Buffer;\n  const unsigned char *BufferLim;\n  #endif\n\n  #ifdef _LZMA_OUT_READ\n  unsigned char *Dictionary;\n  UInt32 Range;\n  UInt32 Code;\n  UInt32 DictionaryPos;\n  UInt32 GlobalPos;\n  UInt32 DistanceLimit;\n  UInt32 Reps[4];\n  int State;\n  int RemainLen;\n  unsigned char TempDictionary[4];\n  #endif\n} CLzmaDecoderState;\n\n#ifdef _LZMA_OUT_READ\n#define LzmaDecoderInit(vs) { (vs)->RemainLen = kLzmaNeedInitId; }\n#endif\n\nint LzmaDecode(CLzmaDecoderState *vs,\n    #ifdef _LZMA_IN_CB\n    ILzmaInCallback *inCallback,\n    #else\n    const unsigned char *inStream, SizeT inSize, SizeT *inSizeProcessed,\n    #endif\n    unsigned char *outStream, SizeT outSize, SizeT *outSizeProcessed);\n\n#endif\n"
  },
  {
    "path": "target/linux/ath79/image/lzma-loader/src/LzmaTypes.h",
    "content": "/* \nLzmaTypes.h \n\nTypes for LZMA Decoder\n\nThis file written and distributed to public domain by Igor Pavlov.\nThis file is part of LZMA SDK 4.40 (2006-05-01)\n*/\n\n#ifndef __LZMATYPES_H\n#define __LZMATYPES_H\n\n#ifndef _7ZIP_BYTE_DEFINED\n#define _7ZIP_BYTE_DEFINED\ntypedef unsigned char Byte;\n#endif \n\n#ifndef _7ZIP_UINT16_DEFINED\n#define _7ZIP_UINT16_DEFINED\ntypedef unsigned short UInt16;\n#endif \n\n#ifndef _7ZIP_UINT32_DEFINED\n#define _7ZIP_UINT32_DEFINED\n#ifdef _LZMA_UINT32_IS_ULONG\ntypedef unsigned long UInt32;\n#else\ntypedef unsigned int UInt32;\n#endif\n#endif \n\n/* #define _LZMA_NO_SYSTEM_SIZE_T */\n/* You can use it, if you don't want <stddef.h> */\n\n#ifndef _7ZIP_SIZET_DEFINED\n#define _7ZIP_SIZET_DEFINED\n#ifdef _LZMA_NO_SYSTEM_SIZE_T\ntypedef UInt32 SizeT;\n#else\n#include <stddef.h>\ntypedef size_t SizeT;\n#endif\n#endif\n\n#endif\n"
  },
  {
    "path": "target/linux/ath79/image/lzma-loader/src/Makefile",
    "content": "#\n# Makefile for the LZMA compressed kernel loader for\n# Atheros AR7XXX/AR9XXX based boards\n#\n# Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>\n#\n# Some parts of this file was based on the OpenWrt specific lzma-loader\n# for the BCM47xx and ADM5120 based boards:\n#\tCopyright (C) 2004 Manuel Novoa III (mjn3@codepoet.org)\n#\tCopyright (C) 2005 Mineharu Takahara <mtakahar@yahoo.com>\n#\tCopyright (C) 2005 by Oleg I. Vdovikin <oleg@cs.msu.su>\n#\n# This program is free software; you can redistribute it and/or modify it\n# under the terms of the GNU General Public License version 2 as published\n# by the Free Software Foundation.\n#\n\nLOADADDR\t:=\nLZMA_TEXT_START\t:= 0x80a00000\nLOADER_DATA\t:=\nKERNEL_MAGIC\t:=\nBOARD\t\t:=\nFLASH_OFFS\t:=\nFLASH_MAX\t:=\n\nCC\t\t:= $(CROSS_COMPILE)gcc\nLD\t\t:= $(CROSS_COMPILE)ld\nOBJCOPY\t\t:= $(CROSS_COMPILE)objcopy\nOBJDUMP\t\t:= $(CROSS_COMPILE)objdump\n\nBIN_FLAGS\t:= -O binary -R .reginfo -R .note -R .comment -R .mdebug \\\n\t\t   -R .MIPS.abiflags -S\n\nCFLAGS\t\t= -D__KERNEL__ -Wall -Wstrict-prototypes -Wno-trigraphs -Os \\\n\t\t  -fno-strict-aliasing -fno-common -fomit-frame-pointer -G 0 \\\n\t\t  -mno-abicalls -fno-pic -ffunction-sections -pipe -mlong-calls \\\n\t\t  -fno-common -ffreestanding -fhonour-copts -nostartfiles \\\n\t\t  -mabi=32 -march=mips32r2 \\\n\t\t  -Wa,-32 -Wa,-march=mips32r2 -Wa,-mips32r2 -Wa,--trap\nCFLAGS\t\t+= -D_LZMA_PROB32\nCFLAGS\t\t+= -flto\n\nASFLAGS\t\t= $(CFLAGS) -D__ASSEMBLY__\n\nLDFLAGS\t\t= -static -Wl,--gc-sections -Wl,-no-warn-mismatch\nLDFLAGS\t\t+= -Wl,-e,startup -T loader.lds -Wl,-Ttext,$(LZMA_TEXT_START)\nLDFLAGS\t\t+= -flto -fwhole-program\n\nO_FORMAT \t= $(shell $(OBJDUMP) -i | head -2 | grep elf32)\n\nOBJECTS\t\t:= head.o loader.o cache.o board.o printf.o LzmaDecode.o\n\nifneq ($(strip $(LOADER_DATA)),)\nOBJECTS\t\t+= data.o\nCFLAGS\t\t+= -DLZMA_WRAPPER=1 -DLOADADDR=$(LOADADDR)\nendif\n\nifneq ($(strip $(KERNEL_MAGIC)),)\nCFLAGS\t\t+= -DCONFIG_KERNEL_MAGIC=$(KERNEL_MAGIC)\nendif\n\nifneq ($(strip $(KERNEL_CMDLINE)),)\nCFLAGS\t\t+= -DCONFIG_KERNEL_CMDLINE='\"$(KERNEL_CMDLINE)\"'\nendif\n\nifneq ($(strip $(FLASH_OFFS)),)\nCFLAGS\t\t+= -DCONFIG_FLASH_OFFS=$(FLASH_OFFS)\nendif\n\nifneq ($(strip $(FLASH_MAX)),)\nCFLAGS\t\t+= -DCONFIG_FLASH_MAX=$(FLASH_MAX)\nendif\n\nBOARD_DEF := $(shell echo $(strip $(BOARD)) | tr a-z A-Z | tr - _)\nifneq ($(BOARD_DEF),)\nCFLAGS\t\t+= -DCONFIG_BOARD_$(BOARD_DEF)\nendif\n\nall: loader.elf\n\n# Don't build dependencies, this may die if $(CC) isn't gcc\ndep:\n\ninstall:\n\n%.o : %.c\n\t$(CC) $(CFLAGS) -c -o $@ $<\n\n%.o : %.S\n\t$(CC) $(ASFLAGS) -c -o $@ $<\n\ndata.o: $(LOADER_DATA)\n\t$(LD) -r -b binary --oformat $(O_FORMAT) -T lzma-data.lds -o $@ $<\n\nloader: $(OBJECTS)\n\t$(CC) $(CFLAGS) $(LDFLAGS) -o $@ $(OBJECTS)\n\nloader.bin: loader\n\t$(OBJCOPY) $(BIN_FLAGS) $< $@\n\nloader2.o: loader.bin\n\t$(LD) -r -b binary --oformat $(O_FORMAT) -o $@ $<\n\nloader.elf: loader2.o\n\t$(LD) -z max-page-size=0x1000 -e startup -T loader2.lds -Ttext $(LOADADDR) -o $@ $<\n\nmrproper: clean\n\nclean:\n\trm -f loader *.elf *.bin *.o\n\n\n\n"
  },
  {
    "path": "target/linux/ath79/image/lzma-loader/src/ar71xx_regs.h",
    "content": "/*\n *  Atheros AR71XX/AR724X/AR913X SoC register definitions\n *\n *  Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>\n *  Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>\n *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>\n *\n *  Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP\n *\n *  This program is free software; you can redistribute it and/or modify it\n *  under the terms of the GNU General Public License version 2 as published\n *  by the Free Software Foundation.\n */\n\n#ifndef __ASM_MACH_AR71XX_REGS_H\n#define __ASM_MACH_AR71XX_REGS_H\n\n#define BIT(_x)\t\t\t(1UL << (_x))\n\n#define AR71XX_APB_BASE\t\t0x18000000\n#define AR71XX_GE0_BASE\t\t0x19000000\n#define AR71XX_GE0_SIZE\t\t0x10000\n#define AR71XX_GE1_BASE\t\t0x1a000000\n#define AR71XX_GE1_SIZE\t\t0x10000\n#define AR71XX_EHCI_BASE\t0x1b000000\n#define AR71XX_EHCI_SIZE\t0x1000\n#define AR71XX_OHCI_BASE\t0x1c000000\n#define AR71XX_OHCI_SIZE\t0x1000\n#define AR71XX_SPI_BASE\t\t0x1f000000\n#define AR71XX_SPI_SIZE\t\t0x01000000\n\n#define AR71XX_DDR_CTRL_BASE\t(AR71XX_APB_BASE + 0x00000000)\n#define AR71XX_DDR_CTRL_SIZE\t0x100\n#define AR71XX_UART_BASE\t(AR71XX_APB_BASE + 0x00020000)\n#define AR71XX_UART_SIZE\t0x100\n#define AR71XX_USB_CTRL_BASE\t(AR71XX_APB_BASE + 0x00030000)\n#define AR71XX_USB_CTRL_SIZE\t0x100\n#define AR71XX_GPIO_BASE        (AR71XX_APB_BASE + 0x00040000)\n#define AR71XX_GPIO_SIZE        0x100\n#define AR71XX_PLL_BASE\t\t(AR71XX_APB_BASE + 0x00050000)\n#define AR71XX_PLL_SIZE\t\t0x100\n#define AR71XX_RESET_BASE\t(AR71XX_APB_BASE + 0x00060000)\n#define AR71XX_RESET_SIZE\t0x100\n#define AR71XX_MII_BASE\t\t(AR71XX_APB_BASE + 0x00070000)\n#define AR71XX_MII_SIZE\t\t0x100\n\n#define AR71XX_PCI_MEM_BASE\t0x10000000\n#define AR71XX_PCI_MEM_SIZE\t0x07000000\n\n#define AR71XX_PCI_WIN0_OFFS\t0x10000000\n#define AR71XX_PCI_WIN1_OFFS\t0x11000000\n#define AR71XX_PCI_WIN2_OFFS\t0x12000000\n#define AR71XX_PCI_WIN3_OFFS\t0x13000000\n#define AR71XX_PCI_WIN4_OFFS\t0x14000000\n#define AR71XX_PCI_WIN5_OFFS\t0x15000000\n#define AR71XX_PCI_WIN6_OFFS\t0x16000000\n#define AR71XX_PCI_WIN7_OFFS\t0x07000000\n\n#define AR71XX_PCI_CFG_BASE\t\\\n\t(AR71XX_PCI_MEM_BASE + AR71XX_PCI_WIN7_OFFS + 0x10000)\n#define AR71XX_PCI_CFG_SIZE\t0x100\n\n#define AR7240_USB_CTRL_BASE\t(AR71XX_APB_BASE + 0x00030000)\n#define AR7240_USB_CTRL_SIZE\t0x100\n#define AR7240_OHCI_BASE\t0x1b000000\n#define AR7240_OHCI_SIZE\t0x1000\n\n#define AR724X_PCI_MEM_BASE\t0x10000000\n#define AR724X_PCI_MEM_SIZE\t0x04000000\n\n#define AR724X_PCI_CFG_BASE\t0x14000000\n#define AR724X_PCI_CFG_SIZE\t0x1000\n#define AR724X_PCI_CRP_BASE\t(AR71XX_APB_BASE + 0x000c0000)\n#define AR724X_PCI_CRP_SIZE\t0x1000\n#define AR724X_PCI_CTRL_BASE\t(AR71XX_APB_BASE + 0x000f0000)\n#define AR724X_PCI_CTRL_SIZE\t0x100\n\n#define AR724X_EHCI_BASE\t0x1b000000\n#define AR724X_EHCI_SIZE\t0x1000\n\n#define AR913X_EHCI_BASE\t0x1b000000\n#define AR913X_EHCI_SIZE\t0x1000\n#define AR913X_WMAC_BASE\t(AR71XX_APB_BASE + 0x000C0000)\n#define AR913X_WMAC_SIZE\t0x30000\n\n#define AR933X_UART_BASE\t(AR71XX_APB_BASE + 0x00020000)\n#define AR933X_UART_SIZE\t0x14\n#define AR933X_GMAC_BASE\t(AR71XX_APB_BASE + 0x00070000)\n#define AR933X_GMAC_SIZE\t0x04\n#define AR933X_WMAC_BASE\t(AR71XX_APB_BASE + 0x00100000)\n#define AR933X_WMAC_SIZE\t0x20000\n#define AR933X_EHCI_BASE\t0x1b000000\n#define AR933X_EHCI_SIZE\t0x1000\n\n#define AR934X_GMAC_BASE\t(AR71XX_APB_BASE + 0x00070000)\n#define AR934X_GMAC_SIZE\t0x14\n#define AR934X_WMAC_BASE\t(AR71XX_APB_BASE + 0x00100000)\n#define AR934X_WMAC_SIZE\t0x20000\n#define AR934X_EHCI_BASE\t0x1b000000\n#define AR934X_EHCI_SIZE\t0x200\n\n#define QCA955X_PCI_MEM_BASE0\t0x10000000\n#define QCA955X_PCI_MEM_BASE1\t0x12000000\n#define QCA955X_PCI_MEM_SIZE\t0x02000000\n#define QCA955X_PCI_CFG_BASE0\t0x14000000\n#define QCA955X_PCI_CFG_BASE1\t0x16000000\n#define QCA955X_PCI_CFG_SIZE\t0x1000\n#define QCA955X_PCI_CRP_BASE0\t(AR71XX_APB_BASE + 0x000c0000)\n#define QCA955X_PCI_CRP_BASE1\t(AR71XX_APB_BASE + 0x00250000)\n#define QCA955X_PCI_CRP_SIZE\t0x1000\n#define QCA955X_PCI_CTRL_BASE0\t(AR71XX_APB_BASE + 0x000f0000)\n#define QCA955X_PCI_CTRL_BASE1\t(AR71XX_APB_BASE + 0x00280000)\n#define QCA955X_PCI_CTRL_SIZE\t0x100\n\n#define QCA955X_WMAC_BASE\t(AR71XX_APB_BASE + 0x00100000)\n#define QCA955X_WMAC_SIZE\t0x20000\n#define QCA955X_EHCI0_BASE\t0x1b000000\n#define QCA955X_EHCI1_BASE\t0x1b400000\n#define QCA955X_EHCI_SIZE\t0x1000\n#define QCA955X_GMAC_BASE\t(AR71XX_APB_BASE + 0x00070000)\n#define QCA955X_GMAC_SIZE\t0x40\n\n#define AR9300_OTP_BASE\t\t0x14000\n#define AR9300_OTP_STATUS\t0x15f18\n#define AR9300_OTP_STATUS_TYPE\t\t0x7\n#define AR9300_OTP_STATUS_VALID\t\t0x4\n#define AR9300_OTP_STATUS_ACCESS_BUSY\t0x2\n#define AR9300_OTP_STATUS_SM_BUSY\t0x1\n#define AR9300_OTP_READ_DATA\t0x15f1c\n\n/*\n * DDR_CTRL block\n */\n#define AR71XX_DDR_REG_PCI_WIN0\t\t0x7c\n#define AR71XX_DDR_REG_PCI_WIN1\t\t0x80\n#define AR71XX_DDR_REG_PCI_WIN2\t\t0x84\n#define AR71XX_DDR_REG_PCI_WIN3\t\t0x88\n#define AR71XX_DDR_REG_PCI_WIN4\t\t0x8c\n#define AR71XX_DDR_REG_PCI_WIN5\t\t0x90\n#define AR71XX_DDR_REG_PCI_WIN6\t\t0x94\n#define AR71XX_DDR_REG_PCI_WIN7\t\t0x98\n#define AR71XX_DDR_REG_FLUSH_GE0\t0x9c\n#define AR71XX_DDR_REG_FLUSH_GE1\t0xa0\n#define AR71XX_DDR_REG_FLUSH_USB\t0xa4\n#define AR71XX_DDR_REG_FLUSH_PCI\t0xa8\n\n#define AR724X_DDR_REG_FLUSH_GE0\t0x7c\n#define AR724X_DDR_REG_FLUSH_GE1\t0x80\n#define AR724X_DDR_REG_FLUSH_USB\t0x84\n#define AR724X_DDR_REG_FLUSH_PCIE\t0x88\n\n#define AR913X_DDR_REG_FLUSH_GE0\t0x7c\n#define AR913X_DDR_REG_FLUSH_GE1\t0x80\n#define AR913X_DDR_REG_FLUSH_USB\t0x84\n#define AR913X_DDR_REG_FLUSH_WMAC\t0x88\n\n#define AR933X_DDR_REG_FLUSH_GE0\t0x7c\n#define AR933X_DDR_REG_FLUSH_GE1\t0x80\n#define AR933X_DDR_REG_FLUSH_USB\t0x84\n#define AR933X_DDR_REG_FLUSH_WMAC\t0x88\n\n#define AR934X_DDR_REG_FLUSH_GE0\t0x9c\n#define AR934X_DDR_REG_FLUSH_GE1\t0xa0\n#define AR934X_DDR_REG_FLUSH_USB\t0xa4\n#define AR934X_DDR_REG_FLUSH_PCIE\t0xa8\n#define AR934X_DDR_REG_FLUSH_WMAC\t0xac\n\n/*\n * PLL block\n */\n#define AR71XX_PLL_REG_CPU_CONFIG\t0x00\n#define AR71XX_PLL_REG_SEC_CONFIG\t0x04\n#define AR71XX_PLL_REG_ETH0_INT_CLOCK\t0x10\n#define AR71XX_PLL_REG_ETH1_INT_CLOCK\t0x14\n\n#define AR71XX_PLL_DIV_SHIFT\t\t3\n#define AR71XX_PLL_DIV_MASK\t\t0x1f\n#define AR71XX_CPU_DIV_SHIFT\t\t16\n#define AR71XX_CPU_DIV_MASK\t\t0x3\n#define AR71XX_DDR_DIV_SHIFT\t\t18\n#define AR71XX_DDR_DIV_MASK\t\t0x3\n#define AR71XX_AHB_DIV_SHIFT\t\t20\n#define AR71XX_AHB_DIV_MASK\t\t0x7\n\n#define AR71XX_ETH0_PLL_SHIFT\t\t17\n#define AR71XX_ETH1_PLL_SHIFT\t\t19\n\n#define AR724X_PLL_REG_CPU_CONFIG\t0x00\n#define AR724X_PLL_REG_PCIE_CONFIG\t0x18\n\n#define AR724X_PLL_DIV_SHIFT\t\t0\n#define AR724X_PLL_DIV_MASK\t\t0x3ff\n#define AR724X_PLL_REF_DIV_SHIFT\t10\n#define AR724X_PLL_REF_DIV_MASK\t\t0xf\n#define AR724X_AHB_DIV_SHIFT\t\t19\n#define AR724X_AHB_DIV_MASK\t\t0x1\n#define AR724X_DDR_DIV_SHIFT\t\t22\n#define AR724X_DDR_DIV_MASK\t\t0x3\n\n#define AR7242_PLL_REG_ETH0_INT_CLOCK\t0x2c\n\n#define AR913X_PLL_REG_CPU_CONFIG\t0x00\n#define AR913X_PLL_REG_ETH_CONFIG\t0x04\n#define AR913X_PLL_REG_ETH0_INT_CLOCK\t0x14\n#define AR913X_PLL_REG_ETH1_INT_CLOCK\t0x18\n\n#define AR913X_PLL_DIV_SHIFT\t\t0\n#define AR913X_PLL_DIV_MASK\t\t0x3ff\n#define AR913X_DDR_DIV_SHIFT\t\t22\n#define AR913X_DDR_DIV_MASK\t\t0x3\n#define AR913X_AHB_DIV_SHIFT\t\t19\n#define AR913X_AHB_DIV_MASK\t\t0x1\n\n#define AR913X_ETH0_PLL_SHIFT\t\t20\n#define AR913X_ETH1_PLL_SHIFT\t\t22\n\n#define AR933X_PLL_CPU_CONFIG_REG\t0x00\n#define AR933X_PLL_CLOCK_CTRL_REG\t0x08\n\n#define AR933X_PLL_CPU_CONFIG_NINT_SHIFT\t10\n#define AR933X_PLL_CPU_CONFIG_NINT_MASK\t\t0x3f\n#define AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT\t16\n#define AR933X_PLL_CPU_CONFIG_REFDIV_MASK\t0x1f\n#define AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT\t23\n#define AR933X_PLL_CPU_CONFIG_OUTDIV_MASK\t0x7\n\n#define AR933X_PLL_CLOCK_CTRL_BYPASS\t\tBIT(2)\n#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT\t5\n#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK\t0x3\n#define AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT\t10\n#define AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK\t0x3\n#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT\t15\n#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK\t0x7\n\n#define AR934X_PLL_CPU_CONFIG_REG\t\t0x00\n#define AR934X_PLL_DDR_CONFIG_REG\t\t0x04\n#define AR934X_PLL_CPU_DDR_CLK_CTRL_REG\t\t0x08\n#define AR934X_PLL_ETH_XMII_CONTROL_REG\t\t0x2c\n\n#define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT\t0\n#define AR934X_PLL_CPU_CONFIG_NFRAC_MASK\t0x3f\n#define AR934X_PLL_CPU_CONFIG_NINT_SHIFT\t6\n#define AR934X_PLL_CPU_CONFIG_NINT_MASK\t\t0x3f\n#define AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT\t12\n#define AR934X_PLL_CPU_CONFIG_REFDIV_MASK\t0x1f\n#define AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT\t19\n#define AR934X_PLL_CPU_CONFIG_OUTDIV_MASK\t0x3\n\n#define AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT\t0\n#define AR934X_PLL_DDR_CONFIG_NFRAC_MASK\t0x3ff\n#define AR934X_PLL_DDR_CONFIG_NINT_SHIFT\t10\n#define AR934X_PLL_DDR_CONFIG_NINT_MASK\t\t0x3f\n#define AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT\t16\n#define AR934X_PLL_DDR_CONFIG_REFDIV_MASK\t0x1f\n#define AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT\t23\n#define AR934X_PLL_DDR_CONFIG_OUTDIV_MASK\t0x7\n\n#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS\tBIT(2)\n#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS\tBIT(3)\n#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS\tBIT(4)\n#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT\t5\n#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK\t0x1f\n#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT\t10\n#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK\t0x1f\n#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT\t15\n#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK\t0x1f\n#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL\tBIT(20)\n#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL\tBIT(21)\n#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL\tBIT(24)\n\n#define QCA955X_PLL_CPU_CONFIG_REG\t\t0x00\n#define QCA955X_PLL_DDR_CONFIG_REG\t\t0x04\n#define QCA955X_PLL_CLK_CTRL_REG\t\t0x08\n\n#define QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT\t0\n#define QCA955X_PLL_CPU_CONFIG_NFRAC_MASK\t0x3f\n#define QCA955X_PLL_CPU_CONFIG_NINT_SHIFT\t6\n#define QCA955X_PLL_CPU_CONFIG_NINT_MASK\t0x3f\n#define QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT\t12\n#define QCA955X_PLL_CPU_CONFIG_REFDIV_MASK\t0x1f\n#define QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT\t19\n#define QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK\t0x3\n\n#define QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT\t0\n#define QCA955X_PLL_DDR_CONFIG_NFRAC_MASK\t0x3ff\n#define QCA955X_PLL_DDR_CONFIG_NINT_SHIFT\t10\n#define QCA955X_PLL_DDR_CONFIG_NINT_MASK\t0x3f\n#define QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT\t16\n#define QCA955X_PLL_DDR_CONFIG_REFDIV_MASK\t0x1f\n#define QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT\t23\n#define QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK\t0x7\n\n#define QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS\t\tBIT(2)\n#define QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS\t\tBIT(3)\n#define QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS\t\tBIT(4)\n#define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT\t\t5\n#define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK\t\t0x1f\n#define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT\t\t10\n#define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_MASK\t\t0x1f\n#define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT\t\t15\n#define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_MASK\t\t0x1f\n#define QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL\t\tBIT(20)\n#define QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL\t\tBIT(21)\n#define QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL\t\tBIT(24)\n\n/*\n * USB_CONFIG block\n */\n#define AR71XX_USB_CTRL_REG_FLADJ\t0x00\n#define AR71XX_USB_CTRL_REG_CONFIG\t0x04\n\n/*\n * RESET block\n */\n#define AR71XX_RESET_REG_TIMER\t\t\t0x00\n#define AR71XX_RESET_REG_TIMER_RELOAD\t\t0x04\n#define AR71XX_RESET_REG_WDOG_CTRL\t\t0x08\n#define AR71XX_RESET_REG_WDOG\t\t\t0x0c\n#define AR71XX_RESET_REG_MISC_INT_STATUS\t0x10\n#define AR71XX_RESET_REG_MISC_INT_ENABLE\t0x14\n#define AR71XX_RESET_REG_PCI_INT_STATUS\t\t0x18\n#define AR71XX_RESET_REG_PCI_INT_ENABLE\t\t0x1c\n#define AR71XX_RESET_REG_GLOBAL_INT_STATUS\t0x20\n#define AR71XX_RESET_REG_RESET_MODULE\t\t0x24\n#define AR71XX_RESET_REG_PERFC_CTRL\t\t0x2c\n#define AR71XX_RESET_REG_PERFC0\t\t\t0x30\n#define AR71XX_RESET_REG_PERFC1\t\t\t0x34\n#define AR71XX_RESET_REG_REV_ID\t\t\t0x90\n\n#define AR913X_RESET_REG_GLOBAL_INT_STATUS\t0x18\n#define AR913X_RESET_REG_RESET_MODULE\t\t0x1c\n#define AR913X_RESET_REG_PERF_CTRL\t\t0x20\n#define AR913X_RESET_REG_PERFC0\t\t\t0x24\n#define AR913X_RESET_REG_PERFC1\t\t\t0x28\n\n#define AR724X_RESET_REG_RESET_MODULE\t\t0x1c\n\n#define AR933X_RESET_REG_RESET_MODULE\t\t0x1c\n#define AR933X_RESET_REG_BOOTSTRAP\t\t0xac\n\n#define AR934X_RESET_REG_RESET_MODULE\t\t0x1c\n#define AR934X_RESET_REG_BOOTSTRAP\t\t0xb0\n#define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS\t0xac\n\n#define QCA955X_RESET_REG_BOOTSTRAP\t\t0xb0\n#define QCA955X_RESET_REG_EXT_INT_STATUS\t0xac\n\n#define MISC_INT_ETHSW\t\t\tBIT(12)\n#define MISC_INT_TIMER4\t\t\tBIT(10)\n#define MISC_INT_TIMER3\t\t\tBIT(9)\n#define MISC_INT_TIMER2\t\t\tBIT(8)\n#define MISC_INT_DMA\t\t\tBIT(7)\n#define MISC_INT_OHCI\t\t\tBIT(6)\n#define MISC_INT_PERFC\t\t\tBIT(5)\n#define MISC_INT_WDOG\t\t\tBIT(4)\n#define MISC_INT_UART\t\t\tBIT(3)\n#define MISC_INT_GPIO\t\t\tBIT(2)\n#define MISC_INT_ERROR\t\t\tBIT(1)\n#define MISC_INT_TIMER\t\t\tBIT(0)\n\n#define AR71XX_RESET_EXTERNAL\t\tBIT(28)\n#define AR71XX_RESET_FULL_CHIP\t\tBIT(24)\n#define AR71XX_RESET_CPU_NMI\t\tBIT(21)\n#define AR71XX_RESET_CPU_COLD\t\tBIT(20)\n#define AR71XX_RESET_DMA\t\tBIT(19)\n#define AR71XX_RESET_SLIC\t\tBIT(18)\n#define AR71XX_RESET_STEREO\t\tBIT(17)\n#define AR71XX_RESET_DDR\t\tBIT(16)\n#define AR71XX_RESET_GE1_MAC\t\tBIT(13)\n#define AR71XX_RESET_GE1_PHY\t\tBIT(12)\n#define AR71XX_RESET_USBSUS_OVERRIDE\tBIT(10)\n#define AR71XX_RESET_GE0_MAC\t\tBIT(9)\n#define AR71XX_RESET_GE0_PHY\t\tBIT(8)\n#define AR71XX_RESET_USB_OHCI_DLL\tBIT(6)\n#define AR71XX_RESET_USB_HOST\t\tBIT(5)\n#define AR71XX_RESET_USB_PHY\t\tBIT(4)\n#define AR71XX_RESET_PCI_BUS\t\tBIT(1)\n#define AR71XX_RESET_PCI_CORE\t\tBIT(0)\n\n#define AR7240_RESET_USB_HOST\t\tBIT(5)\n#define AR7240_RESET_OHCI_DLL\t\tBIT(3)\n\n#define AR724X_RESET_GE1_MDIO\t\tBIT(23)\n#define AR724X_RESET_GE0_MDIO\t\tBIT(22)\n#define AR724X_RESET_PCIE_PHY_SERIAL\tBIT(10)\n#define AR724X_RESET_PCIE_PHY\t\tBIT(7)\n#define AR724X_RESET_PCIE\t\tBIT(6)\n#define AR724X_RESET_USB_HOST\t\tBIT(5)\n#define AR724X_RESET_USB_PHY\t\tBIT(4)\n#define AR724X_RESET_USBSUS_OVERRIDE\tBIT(3)\n\n#define AR913X_RESET_AMBA2WMAC\t\tBIT(22)\n#define AR913X_RESET_USBSUS_OVERRIDE\tBIT(10)\n#define AR913X_RESET_USB_HOST\t\tBIT(5)\n#define AR913X_RESET_USB_PHY\t\tBIT(4)\n\n#define AR933X_RESET_GE1_MDIO\t\tBIT(23)\n#define AR933X_RESET_GE0_MDIO\t\tBIT(22)\n#define AR933X_RESET_GE1_MAC\t\tBIT(13)\n#define AR933X_RESET_WMAC\t\tBIT(11)\n#define AR933X_RESET_GE0_MAC\t\tBIT(9)\n#define AR933X_RESET_USB_HOST\t\tBIT(5)\n#define AR933X_RESET_USB_PHY\t\tBIT(4)\n#define AR933X_RESET_USBSUS_OVERRIDE\tBIT(3)\n\n#define AR934X_RESET_HOST\t\tBIT(31)\n#define AR934X_RESET_SLIC\t\tBIT(30)\n#define AR934X_RESET_HDMA\t\tBIT(29)\n#define AR934X_RESET_EXTERNAL\t\tBIT(28)\n#define AR934X_RESET_RTC\t\tBIT(27)\n#define AR934X_RESET_PCIE_EP_INT\tBIT(26)\n#define AR934X_RESET_CHKSUM_ACC\t\tBIT(25)\n#define AR934X_RESET_FULL_CHIP\t\tBIT(24)\n#define AR934X_RESET_GE1_MDIO\t\tBIT(23)\n#define AR934X_RESET_GE0_MDIO\t\tBIT(22)\n#define AR934X_RESET_CPU_NMI\t\tBIT(21)\n#define AR934X_RESET_CPU_COLD\t\tBIT(20)\n#define AR934X_RESET_HOST_RESET_INT\tBIT(19)\n#define AR934X_RESET_PCIE_EP\t\tBIT(18)\n#define AR934X_RESET_UART1\t\tBIT(17)\n#define AR934X_RESET_DDR\t\tBIT(16)\n#define AR934X_RESET_USB_PHY_PLL_PWD_EXT BIT(15)\n#define AR934X_RESET_NANDF\t\tBIT(14)\n#define AR934X_RESET_GE1_MAC\t\tBIT(13)\n#define AR934X_RESET_ETH_SWITCH_ANALOG\tBIT(12)\n#define AR934X_RESET_USB_PHY_ANALOG\tBIT(11)\n#define AR934X_RESET_HOST_DMA_INT\tBIT(10)\n#define AR934X_RESET_GE0_MAC\t\tBIT(9)\n#define AR934X_RESET_ETH_SWITCH\t\tBIT(8)\n#define AR934X_RESET_PCIE_PHY\t\tBIT(7)\n#define AR934X_RESET_PCIE\t\tBIT(6)\n#define AR934X_RESET_USB_HOST\t\tBIT(5)\n#define AR934X_RESET_USB_PHY\t\tBIT(4)\n#define AR934X_RESET_USBSUS_OVERRIDE\tBIT(3)\n#define AR934X_RESET_LUT\t\tBIT(2)\n#define AR934X_RESET_MBOX\t\tBIT(1)\n#define AR934X_RESET_I2S\t\tBIT(0)\n\n#define AR933X_BOOTSTRAP_MDIO_GPIO_EN\tBIT(18)\n#define AR933X_BOOTSTRAP_EEPBUSY\tBIT(4)\n#define AR933X_BOOTSTRAP_REF_CLK_40\tBIT(0)\n\n#define AR934X_BOOTSTRAP_SW_OPTION8\tBIT(23)\n#define AR934X_BOOTSTRAP_SW_OPTION7\tBIT(22)\n#define AR934X_BOOTSTRAP_SW_OPTION6\tBIT(21)\n#define AR934X_BOOTSTRAP_SW_OPTION5\tBIT(20)\n#define AR934X_BOOTSTRAP_SW_OPTION4\tBIT(19)\n#define AR934X_BOOTSTRAP_SW_OPTION3\tBIT(18)\n#define AR934X_BOOTSTRAP_SW_OPTION2\tBIT(17)\n#define AR934X_BOOTSTRAP_SW_OPTION1\tBIT(16)\n#define AR934X_BOOTSTRAP_USB_MODE_DEVICE BIT(7)\n#define AR934X_BOOTSTRAP_PCIE_RC\tBIT(6)\n#define AR934X_BOOTSTRAP_EJTAG_MODE\tBIT(5)\n#define AR934X_BOOTSTRAP_REF_CLK_40\tBIT(4)\n#define AR934X_BOOTSTRAP_BOOT_FROM_SPI\tBIT(2)\n#define AR934X_BOOTSTRAP_SDRAM_DISABLED\tBIT(1)\n#define AR934X_BOOTSTRAP_DDR1\t\tBIT(0)\n\n#define QCA955X_BOOTSTRAP_REF_CLK_40\tBIT(4)\n\n#define AR934X_PCIE_WMAC_INT_WMAC_MISC\t\tBIT(0)\n#define AR934X_PCIE_WMAC_INT_WMAC_TX\t\tBIT(1)\n#define AR934X_PCIE_WMAC_INT_WMAC_RXLP\t\tBIT(2)\n#define AR934X_PCIE_WMAC_INT_WMAC_RXHP\t\tBIT(3)\n#define AR934X_PCIE_WMAC_INT_PCIE_RC\t\tBIT(4)\n#define AR934X_PCIE_WMAC_INT_PCIE_RC0\t\tBIT(5)\n#define AR934X_PCIE_WMAC_INT_PCIE_RC1\t\tBIT(6)\n#define AR934X_PCIE_WMAC_INT_PCIE_RC2\t\tBIT(7)\n#define AR934X_PCIE_WMAC_INT_PCIE_RC3\t\tBIT(8)\n#define AR934X_PCIE_WMAC_INT_WMAC_ALL \\\n\t(AR934X_PCIE_WMAC_INT_WMAC_MISC | AR934X_PCIE_WMAC_INT_WMAC_TX | \\\n\t AR934X_PCIE_WMAC_INT_WMAC_RXLP | AR934X_PCIE_WMAC_INT_WMAC_RXHP)\n\n#define AR934X_PCIE_WMAC_INT_PCIE_ALL \\\n\t(AR934X_PCIE_WMAC_INT_PCIE_RC | AR934X_PCIE_WMAC_INT_PCIE_RC0 | \\\n\t AR934X_PCIE_WMAC_INT_PCIE_RC1 | AR934X_PCIE_WMAC_INT_PCIE_RC2 | \\\n\t AR934X_PCIE_WMAC_INT_PCIE_RC3)\n\n#define QCA955X_EXT_INT_WMAC_MISC\t\tBIT(0)\n#define QCA955X_EXT_INT_WMAC_TX\t\t\tBIT(1)\n#define QCA955X_EXT_INT_WMAC_RXLP\t\tBIT(2)\n#define QCA955X_EXT_INT_WMAC_RXHP\t\tBIT(3)\n#define QCA955X_EXT_INT_PCIE_RC1\t\tBIT(4)\n#define QCA955X_EXT_INT_PCIE_RC1_INT0\t\tBIT(5)\n#define QCA955X_EXT_INT_PCIE_RC1_INT1\t\tBIT(6)\n#define QCA955X_EXT_INT_PCIE_RC1_INT2\t\tBIT(7)\n#define QCA955X_EXT_INT_PCIE_RC1_INT3\t\tBIT(8)\n#define QCA955X_EXT_INT_PCIE_RC2\t\tBIT(12)\n#define QCA955X_EXT_INT_PCIE_RC2_INT0\t\tBIT(13)\n#define QCA955X_EXT_INT_PCIE_RC2_INT1\t\tBIT(14)\n#define QCA955X_EXT_INT_PCIE_RC2_INT2\t\tBIT(15)\n#define QCA955X_EXT_INT_PCIE_RC2_INT3\t\tBIT(16)\n#define QCA955X_EXT_INT_USB1\t\t\tBIT(24)\n#define QCA955X_EXT_INT_USB2\t\t\tBIT(28)\n\n#define QCA955X_EXT_INT_WMAC_ALL \\\n\t(QCA955X_EXT_INT_WMAC_MISC | QCA955X_EXT_INT_WMAC_TX | \\\n\t QCA955X_EXT_INT_WMAC_RXLP | QCA955X_EXT_INT_WMAC_RXHP)\n\n#define QCA955X_EXT_INT_PCIE_RC1_ALL \\\n\t(QCA955X_EXT_INT_PCIE_RC1 | QCA955X_EXT_INT_PCIE_RC1_INT0 | \\\n\t QCA955X_EXT_INT_PCIE_RC1_INT1 | QCA955X_EXT_INT_PCIE_RC1_INT2 | \\\n\t QCA955X_EXT_INT_PCIE_RC1_INT3)\n\n#define QCA955X_EXT_INT_PCIE_RC2_ALL \\\n\t(QCA955X_EXT_INT_PCIE_RC2 | QCA955X_EXT_INT_PCIE_RC2_INT0 | \\\n\t QCA955X_EXT_INT_PCIE_RC2_INT1 | QCA955X_EXT_INT_PCIE_RC2_INT2 | \\\n\t QCA955X_EXT_INT_PCIE_RC2_INT3)\n\n#define REV_ID_MAJOR_MASK\t\t0xfff0\n#define REV_ID_MAJOR_AR71XX\t\t0x00a0\n#define REV_ID_MAJOR_AR913X\t\t0x00b0\n#define REV_ID_MAJOR_AR7240\t\t0x00c0\n#define REV_ID_MAJOR_AR7241\t\t0x0100\n#define REV_ID_MAJOR_AR7242\t\t0x1100\n#define REV_ID_MAJOR_AR9330\t\t0x0110\n#define REV_ID_MAJOR_AR9331\t\t0x1110\n#define REV_ID_MAJOR_AR9341\t\t0x0120\n#define REV_ID_MAJOR_AR9342\t\t0x1120\n#define REV_ID_MAJOR_AR9344\t\t0x2120\n#define REV_ID_MAJOR_QCA9558\t\t0x1130\n\n#define AR71XX_REV_ID_MINOR_MASK\t0x3\n#define AR71XX_REV_ID_MINOR_AR7130\t0x0\n#define AR71XX_REV_ID_MINOR_AR7141\t0x1\n#define AR71XX_REV_ID_MINOR_AR7161\t0x2\n#define AR71XX_REV_ID_REVISION_MASK\t0x3\n#define AR71XX_REV_ID_REVISION_SHIFT\t2\n\n#define AR913X_REV_ID_MINOR_MASK\t0x3\n#define AR913X_REV_ID_MINOR_AR9130\t0x0\n#define AR913X_REV_ID_MINOR_AR9132\t0x1\n#define AR913X_REV_ID_REVISION_MASK\t0x3\n#define AR913X_REV_ID_REVISION_SHIFT\t2\n\n#define AR933X_REV_ID_REVISION_MASK\t0x3\n\n#define AR724X_REV_ID_REVISION_MASK\t0x3\n\n#define AR934X_REV_ID_REVISION_MASK     0xf\n\n#define AR944X_REV_ID_REVISION_MASK\t0xf\n\n/*\n * SPI block\n */\n#define AR71XX_SPI_REG_FS\t0x00\t/* Function Select */\n#define AR71XX_SPI_REG_CTRL\t0x04\t/* SPI Control */\n#define AR71XX_SPI_REG_IOC\t0x08\t/* SPI I/O Control */\n#define AR71XX_SPI_REG_RDS\t0x0c\t/* Read Data Shift */\n\n#define AR71XX_SPI_FS_GPIO\tBIT(0)\t/* Enable GPIO mode */\n\n#define AR71XX_SPI_CTRL_RD\tBIT(6)\t/* Remap Disable */\n#define AR71XX_SPI_CTRL_DIV_MASK 0x3f\n\n#define AR71XX_SPI_IOC_DO\tBIT(0)\t/* Data Out pin */\n#define AR71XX_SPI_IOC_CLK\tBIT(8)\t/* CLK pin */\n#define AR71XX_SPI_IOC_CS(n)\tBIT(16 + (n))\n#define AR71XX_SPI_IOC_CS0\tAR71XX_SPI_IOC_CS(0)\n#define AR71XX_SPI_IOC_CS1\tAR71XX_SPI_IOC_CS(1)\n#define AR71XX_SPI_IOC_CS2\tAR71XX_SPI_IOC_CS(2)\n#define AR71XX_SPI_IOC_CS_ALL\t(AR71XX_SPI_IOC_CS0 | AR71XX_SPI_IOC_CS1 | \\\n\t\t\t\t AR71XX_SPI_IOC_CS2)\n\n/*\n * GPIO block\n */\n#define AR71XX_GPIO_REG_OE\t\t0x00\n#define AR71XX_GPIO_REG_IN\t\t0x04\n#define AR71XX_GPIO_REG_OUT\t\t0x08\n#define AR71XX_GPIO_REG_SET\t\t0x0c\n#define AR71XX_GPIO_REG_CLEAR\t\t0x10\n#define AR71XX_GPIO_REG_INT_MODE\t0x14\n#define AR71XX_GPIO_REG_INT_TYPE\t0x18\n#define AR71XX_GPIO_REG_INT_POLARITY\t0x1c\n#define AR71XX_GPIO_REG_INT_PENDING\t0x20\n#define AR71XX_GPIO_REG_INT_ENABLE\t0x24\n#define AR71XX_GPIO_REG_FUNC\t\t0x28\n\n#define AR934X_GPIO_REG_OUT_FUNC0\t0x2c\n#define AR934X_GPIO_REG_OUT_FUNC1\t0x30\n#define AR934X_GPIO_REG_OUT_FUNC2\t0x34\n#define AR934X_GPIO_REG_OUT_FUNC3\t0x38\n#define AR934X_GPIO_REG_OUT_FUNC4\t0x3c\n#define AR934X_GPIO_REG_OUT_FUNC5\t0x40\n#define AR934X_GPIO_REG_FUNC\t\t0x6c\n\n#define AR71XX_GPIO_COUNT\t\t16\n#define AR724X_GPIO_COUNT\t\t18\n#define AR913X_GPIO_COUNT\t\t22\n#define AR933X_GPIO_COUNT\t\t30\n#define AR934X_GPIO_COUNT\t\t23\n#define QCA955X_GPIO_COUNT\t\t24\n\n#define AR71XX_GPIO_FUNC_STEREO_EN\t\tBIT(17)\n#define AR71XX_GPIO_FUNC_SLIC_EN\t\tBIT(16)\n#define AR71XX_GPIO_FUNC_SPI_CS2_EN\t\tBIT(13)\n#define AR71XX_GPIO_FUNC_SPI_CS1_EN\t\tBIT(12)\n#define AR71XX_GPIO_FUNC_UART_EN\t\tBIT(8)\n#define AR71XX_GPIO_FUNC_USB_OC_EN\t\tBIT(4)\n#define AR71XX_GPIO_FUNC_USB_CLK_EN\t\tBIT(0)\n\n#define AR724X_GPIO_FUNC_GE0_MII_CLK_EN\t\tBIT(19)\n#define AR724X_GPIO_FUNC_SPI_EN\t\t\tBIT(18)\n#define AR724X_GPIO_FUNC_SPI_CS_EN2\t\tBIT(14)\n#define AR724X_GPIO_FUNC_SPI_CS_EN1\t\tBIT(13)\n#define AR724X_GPIO_FUNC_CLK_OBS5_EN\t\tBIT(12)\n#define AR724X_GPIO_FUNC_CLK_OBS4_EN\t\tBIT(11)\n#define AR724X_GPIO_FUNC_CLK_OBS3_EN\t\tBIT(10)\n#define AR724X_GPIO_FUNC_CLK_OBS2_EN\t\tBIT(9)\n#define AR724X_GPIO_FUNC_CLK_OBS1_EN\t\tBIT(8)\n#define AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN\tBIT(7)\n#define AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN\tBIT(6)\n#define AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN\tBIT(5)\n#define AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN\tBIT(4)\n#define AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN\tBIT(3)\n#define AR724X_GPIO_FUNC_UART_RTS_CTS_EN\tBIT(2)\n#define AR724X_GPIO_FUNC_UART_EN\t\tBIT(1)\n#define AR724X_GPIO_FUNC_JTAG_DISABLE\t\tBIT(0)\n\n#define AR913X_GPIO_FUNC_WMAC_LED_EN\t\tBIT(22)\n#define AR913X_GPIO_FUNC_EXP_PORT_CS_EN\t\tBIT(21)\n#define AR913X_GPIO_FUNC_I2S_REFCLKEN\t\tBIT(20)\n#define AR913X_GPIO_FUNC_I2S_MCKEN\t\tBIT(19)\n#define AR913X_GPIO_FUNC_I2S1_EN\t\tBIT(18)\n#define AR913X_GPIO_FUNC_I2S0_EN\t\tBIT(17)\n#define AR913X_GPIO_FUNC_SLIC_EN\t\tBIT(16)\n#define AR913X_GPIO_FUNC_UART_RTSCTS_EN\t\tBIT(9)\n#define AR913X_GPIO_FUNC_UART_EN\t\tBIT(8)\n#define AR913X_GPIO_FUNC_USB_CLK_EN\t\tBIT(4)\n\n#define AR933X_GPIO_FUNC_SPDIF2TCK\t\tBIT(31)\n#define AR933X_GPIO_FUNC_SPDIF_EN\t\tBIT(30)\n#define AR933X_GPIO_FUNC_I2SO_22_18_EN\t\tBIT(29)\n#define AR933X_GPIO_FUNC_I2S_MCK_EN\t\tBIT(27)\n#define AR933X_GPIO_FUNC_I2SO_EN\t\tBIT(26)\n#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_DUPL\tBIT(25)\n#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_COLL\tBIT(24)\n#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_ACT\tBIT(23)\n#define AR933X_GPIO_FUNC_SPI_EN\t\t\tBIT(18)\n#define AR933X_GPIO_FUNC_SPI_CS_EN2\t\tBIT(14)\n#define AR933X_GPIO_FUNC_SPI_CS_EN1\t\tBIT(13)\n#define AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN\tBIT(7)\n#define AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN\tBIT(6)\n#define AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN\tBIT(5)\n#define AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN\tBIT(4)\n#define AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN\tBIT(3)\n#define AR933X_GPIO_FUNC_UART_RTS_CTS_EN\tBIT(2)\n#define AR933X_GPIO_FUNC_UART_EN\t\tBIT(1)\n#define AR933X_GPIO_FUNC_JTAG_DISABLE\t\tBIT(0)\n\n#define AR934X_GPIO_FUNC_DDR_DQOE_EN\tBIT(17)\n#define AR934X_GPIO_FUNC_SPI_CS_1_EN\tBIT(14)\n#define AR934X_GPIO_FUNC_SPI_CS_0_EN\tBIT(13)\n\n#define AR934X_GPIO_OUT_GPIO\t\t0x00\n\n/*\n * MII_CTRL block\n */\n#define AR71XX_MII_REG_MII0_CTRL\t0x00\n#define AR71XX_MII_REG_MII1_CTRL\t0x04\n\n#define AR71XX_MII_CTRL_IF_MASK\t\t3\n#define AR71XX_MII_CTRL_SPEED_SHIFT\t4\n#define AR71XX_MII_CTRL_SPEED_MASK\t3\n#define AR71XX_MII_CTRL_SPEED_10\t0\n#define AR71XX_MII_CTRL_SPEED_100\t1\n#define AR71XX_MII_CTRL_SPEED_1000\t2\n\n#define AR71XX_MII0_CTRL_IF_GMII\t0\n#define AR71XX_MII0_CTRL_IF_MII\t\t1\n#define AR71XX_MII0_CTRL_IF_RGMII\t2\n#define AR71XX_MII0_CTRL_IF_RMII\t3\n\n#define AR71XX_MII1_CTRL_IF_RGMII\t0\n#define AR71XX_MII1_CTRL_IF_RMII\t1\n\n/*\n * AR933X GMAC interface\n */\n#define AR933X_GMAC_REG_ETH_CFG\t\t0x00\n\n#define AR933X_ETH_CFG_RGMII_GE0\tBIT(0)\n#define AR933X_ETH_CFG_MII_GE0\t\tBIT(1)\n#define AR933X_ETH_CFG_GMII_GE0\t\tBIT(2)\n#define AR933X_ETH_CFG_MII_GE0_MASTER\tBIT(3)\n#define AR933X_ETH_CFG_MII_GE0_SLAVE\tBIT(4)\n#define AR933X_ETH_CFG_MII_GE0_ERR_EN\tBIT(5)\n#define AR933X_ETH_CFG_SW_PHY_SWAP\tBIT(7)\n#define AR933X_ETH_CFG_SW_PHY_ADDR_SWAP\tBIT(8)\n#define AR933X_ETH_CFG_RMII_GE0\t\tBIT(9)\n#define AR933X_ETH_CFG_RMII_GE0_SPD_10\t0\n#define AR933X_ETH_CFG_RMII_GE0_SPD_100\tBIT(10)\n\n/*\n * AR934X GMAC Interface\n */\n#define AR934X_GMAC_REG_ETH_CFG\t\t0x00\n\n#define AR934X_ETH_CFG_RGMII_GMAC0\tBIT(0)\n#define AR934X_ETH_CFG_MII_GMAC0\tBIT(1)\n#define AR934X_ETH_CFG_GMII_GMAC0\tBIT(2)\n#define AR934X_ETH_CFG_MII_GMAC0_MASTER\tBIT(3)\n#define AR934X_ETH_CFG_MII_GMAC0_SLAVE\tBIT(4)\n#define AR934X_ETH_CFG_MII_GMAC0_ERR_EN\tBIT(5)\n#define AR934X_ETH_CFG_SW_ONLY_MODE\tBIT(6)\n#define AR934X_ETH_CFG_SW_PHY_SWAP\tBIT(7)\n#define AR934X_ETH_CFG_SW_APB_ACCESS\tBIT(9)\n#define AR934X_ETH_CFG_RMII_GMAC0\tBIT(10)\n#define AR933X_ETH_CFG_MII_CNTL_SPEED\tBIT(11)\n#define AR934X_ETH_CFG_RMII_GMAC0_MASTER BIT(12)\n#define AR933X_ETH_CFG_SW_ACC_MSB_FIRST\tBIT(13)\n\n/*\n * QCA955X GMAC Interface\n */\n\n#define QCA955X_GMAC_REG_ETH_CFG\t0x00\n\n#define QCA955X_ETH_CFG_RGMII_GMAC0\tBIT(0)\n#define QCA955X_ETH_CFG_SGMII_GMAC0\tBIT(6)\n\n#endif /* __ASM_MACH_AR71XX_REGS_H */\n"
  },
  {
    "path": "target/linux/ath79/image/lzma-loader/src/board.c",
    "content": "/*\n * LZMA compressed kernel loader for Atheros AR7XXX/AR9XXX based boards\n *\n * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of the GNU General Public License version 2 as published\n * by the Free Software Foundation.\n */\n\n#include <stddef.h>\n#include \"config.h\"\n#include \"ar71xx_regs.h\"\n\n#define READREG(r)\t*(volatile unsigned int *)(r)\n#define WRITEREG(r,v)\t*(volatile unsigned int *)(r) = v\n\n#define KSEG1ADDR(_x)\t(((_x) & 0x1fffffff) | 0xa0000000)\n\n#define UART_BASE\t0xb8020000\n\n#define UART_TX\t\t0\n#define UART_LSR\t5\n\n#define UART_LSR_THRE   0x20\n\n#define UART_READ(r)\t\tREADREG(UART_BASE + 4 * (r))\n#define UART_WRITE(r,v)\t\tWRITEREG(UART_BASE + 4 * (r), (v))\n\nvoid board_putc(int ch)\n{\n\twhile (((UART_READ(UART_LSR)) & UART_LSR_THRE) == 0);\n\tUART_WRITE(UART_TX, ch);\n\twhile (((UART_READ(UART_LSR)) & UART_LSR_THRE) == 0);\n}\n\n#ifdef CONFIG_BOARD_TL_WR1043ND_V1\nstatic void tlwr1043nd_init(void)\n{\n\tunsigned int reg = KSEG1ADDR(AR71XX_RESET_BASE);\n\tunsigned int t;\n\n\tt = READREG(reg + AR913X_RESET_REG_RESET_MODULE);\n\tt |= AR71XX_RESET_GE0_PHY;\n\tWRITEREG(reg + AR913X_RESET_REG_RESET_MODULE, t);\n\t/* flush write */\n\tt = READREG(reg + AR913X_RESET_REG_RESET_MODULE);\n}\n#else\nstatic inline void tlwr1043nd_init(void) {}\n#endif\n\nvoid board_init(void)\n{\n\ttlwr1043nd_init();\n}\n"
  },
  {
    "path": "target/linux/ath79/image/lzma-loader/src/cache.c",
    "content": "/*\n * LZMA compressed kernel loader for Atheros AR7XXX/AR9XXX based boards\n *\n * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>\n *\n * The cache manipulation routine has been taken from the U-Boot project.\n *\t(C) Copyright 2003\n *\tWolfgang Denk, DENX Software Engineering, <wd@denx.de>\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of the GNU General Public License version 2 as published\n * by the Free Software Foundation.\n *\n */\n\n#include \"cache.h\"\n#include \"cacheops.h\"\n#include \"config.h\"\n\n#define cache_op(op,addr)\t\t\t\t\t\t\\\n\t__asm__ __volatile__(\t\t\t\t\t\t\\\n\t\"\t.set\tpush\t\t\t\t\t\\n\"\t\\\n\t\"\t.set\tnoreorder\t\t\t\t\\n\"\t\\\n\t\"\t.set\tmips3\\n\\t\t\t\t\t\\n\"\t\\\n\t\"\tcache\t%0, %1\t\t\t\t\t\\n\"\t\\\n\t\"\t.set\tpop\t\t\t\t\t\\n\"\t\\\n\t:\t\t\t\t\t\t\t\t\\\n\t: \"i\" (op), \"R\" (*(unsigned char *)(addr)))\n\nvoid flush_cache(unsigned long start_addr, unsigned long size)\n{\n\tunsigned long lsize = CONFIG_CACHELINE_SIZE;\n\tunsigned long addr = start_addr & ~(lsize - 1);\n\tunsigned long aend = (start_addr + size - 1) & ~(lsize - 1);\n\n\twhile (1) {\n\t\tcache_op(Hit_Writeback_Inv_D, addr);\n\t\tcache_op(Hit_Invalidate_I, addr);\n\t\tif (addr == aend)\n\t\t\tbreak;\n\t\taddr += lsize;\n\t}\n}\n"
  },
  {
    "path": "target/linux/ath79/image/lzma-loader/src/cache.h",
    "content": "/*\n * LZMA compressed kernel loader for Atheros AR7XXX/AR9XXX based boards\n *\n * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of the GNU General Public License version 2 as published\n * by the Free Software Foundation.\n *\n */\n\n#ifndef __CACHE_H\n#define __CACHE_H\n\nvoid flush_cache(unsigned long start_addr, unsigned long size);\n\n#endif /* __CACHE_H */\n"
  },
  {
    "path": "target/linux/ath79/image/lzma-loader/src/cacheops.h",
    "content": "/*\n * Cache operations for the cache instruction.\n *\n * This file is subject to the terms and conditions of the GNU General Public\n * License.  See the file \"COPYING\" in the main directory of this archive\n * for more details.\n *\n * (C) Copyright 1996, 97, 99, 2002, 03 Ralf Baechle\n * (C) Copyright 1999 Silicon Graphics, Inc.\n */\n#ifndef\t__ASM_CACHEOPS_H\n#define\t__ASM_CACHEOPS_H\n\n/*\n * Cache Operations available on all MIPS processors with R4000-style caches\n */\n#define Index_Invalidate_I      0x00\n#define Index_Writeback_Inv_D   0x01\n#define Index_Load_Tag_I\t0x04\n#define Index_Load_Tag_D\t0x05\n#define Index_Store_Tag_I\t0x08\n#define Index_Store_Tag_D\t0x09\n#if defined(CONFIG_CPU_LOONGSON2)\n#define Hit_Invalidate_I\t0x00\n#else\n#define Hit_Invalidate_I\t0x10\n#endif\n#define Hit_Invalidate_D\t0x11\n#define Hit_Writeback_Inv_D\t0x15\n\n/*\n * R4000-specific cacheops\n */\n#define Create_Dirty_Excl_D\t0x0d\n#define Fill\t\t\t0x14\n#define Hit_Writeback_I\t\t0x18\n#define Hit_Writeback_D\t\t0x19\n\n/*\n * R4000SC and R4400SC-specific cacheops\n */\n#define Index_Invalidate_SI     0x02\n#define Index_Writeback_Inv_SD  0x03\n#define Index_Load_Tag_SI\t0x06\n#define Index_Load_Tag_SD\t0x07\n#define Index_Store_Tag_SI\t0x0A\n#define Index_Store_Tag_SD\t0x0B\n#define Create_Dirty_Excl_SD\t0x0f\n#define Hit_Invalidate_SI\t0x12\n#define Hit_Invalidate_SD\t0x13\n#define Hit_Writeback_Inv_SD\t0x17\n#define Hit_Writeback_SD\t0x1b\n#define Hit_Set_Virtual_SI\t0x1e\n#define Hit_Set_Virtual_SD\t0x1f\n\n/*\n * R5000-specific cacheops\n */\n#define R5K_Page_Invalidate_S\t0x17\n\n/*\n * RM7000-specific cacheops\n */\n#define Page_Invalidate_T\t0x16\n\n/*\n * R10000-specific cacheops\n *\n * Cacheops 0x02, 0x06, 0x0a, 0x0c-0x0e, 0x16, 0x1a and 0x1e are unused.\n * Most of the _S cacheops are identical to the R4000SC _SD cacheops.\n */\n#define Index_Writeback_Inv_S\t0x03\n#define Index_Load_Tag_S\t0x07\n#define Index_Store_Tag_S\t0x0B\n#define Hit_Invalidate_S\t0x13\n#define Cache_Barrier\t\t0x14\n#define Hit_Writeback_Inv_S\t0x17\n#define Index_Load_Data_I\t0x18\n#define Index_Load_Data_D\t0x19\n#define Index_Load_Data_S\t0x1b\n#define Index_Store_Data_I\t0x1c\n#define Index_Store_Data_D\t0x1d\n#define Index_Store_Data_S\t0x1f\n\n#endif\t/* __ASM_CACHEOPS_H */\n"
  },
  {
    "path": "target/linux/ath79/image/lzma-loader/src/config.h",
    "content": "/*\n * LZMA compressed kernel loader for Atheros AR7XXX/AR9XXX based boards\n *\n * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of the GNU General Public License version 2 as published\n * by the Free Software Foundation.\n *\n */\n\n#ifndef _CONFIG_H_\n#define _CONFIG_H_\n\n#define CONFIG_ICACHE_SIZE\t(32 * 1024)\n#define CONFIG_DCACHE_SIZE\t(64 * 1024)\n#define CONFIG_CACHELINE_SIZE\t32\n\n#ifndef CONFIG_FLASH_OFFS\n#define CONFIG_FLASH_OFFS\t0\n#endif\n\n#ifndef CONFIG_FLASH_MAX\n#define CONFIG_FLASH_MAX\t0\n#endif\n\n#ifndef CONFIG_FLASH_STEP\n#define CONFIG_FLASH_STEP\t0x1000\n#endif\n\n#endif /* _CONFIG_H_ */\n"
  },
  {
    "path": "target/linux/ath79/image/lzma-loader/src/cp0regdef.h",
    "content": "/*\n * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle\n *\n * Copyright (C) 2001, Monta Vista Software\n * Author: jsun@mvista.com or jsun@junsun.net\n */\n#ifndef _cp0regdef_h_\n#define _cp0regdef_h_\n\n#define CP0_INDEX $0\n#define CP0_RANDOM $1\n#define CP0_ENTRYLO0 $2\n#define CP0_ENTRYLO1 $3\n#define CP0_CONTEXT $4\n#define CP0_PAGEMASK $5\n#define CP0_WIRED $6\n#define CP0_BADVADDR $8\n#define CP0_COUNT $9\n#define CP0_ENTRYHI $10\n#define CP0_COMPARE $11\n#define CP0_STATUS $12\n#define CP0_CAUSE $13\n#define CP0_EPC $14\n#define CP0_PRID $15\n#define CP0_CONFIG $16\n#define CP0_LLADDR $17\n#define CP0_WATCHLO $18\n#define CP0_WATCHHI $19\n#define CP0_XCONTEXT $20\n#define CP0_FRAMEMASK $21\n#define CP0_DIAGNOSTIC $22\n#define CP0_PERFORMANCE $25\n#define CP0_ECC $26\n#define CP0_CACHEERR $27\n#define CP0_TAGLO $28\n#define CP0_TAGHI $29\n#define CP0_ERROREPC $30\n\n#endif\n"
  },
  {
    "path": "target/linux/ath79/image/lzma-loader/src/head.S",
    "content": "/*\n * LZMA compressed kernel loader for Atheros AR7XXX/AR9XXX based boards\n *\n * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>\n *\n * Some parts of this code was based on the OpenWrt specific lzma-loader\n * for the BCM47xx and ADM5120 based boards:\n *\tCopyright (C) 2004 Manuel Novoa III (mjn3@codepoet.org)\n *\tCopyright (C) 2005 by Oleg I. Vdovikin <oleg@cs.msu.su>\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of the GNU General Public License version 2 as published\n * by the Free Software Foundation.\n */\n\n#include <asm/asm.h>\n#include <asm/regdef.h>\n#include \"cp0regdef.h\"\n#include \"cacheops.h\"\n#include \"config.h\"\n\n#define KSEG0\t\t0x80000000\n\n\t.macro\tehb\n\tsll     zero, 3\n\t.endm\n\n\t.text\n\nLEAF(startup)\n\t.set noreorder\n\t.set mips32\n\n\tmtc0\tzero, CP0_WATCHLO\t# clear watch registers\n\tmtc0\tzero, CP0_WATCHHI\n\tmtc0\tzero, CP0_CAUSE\t\t# clear before writing status register\n\n\tmfc0\tt0, CP0_STATUS\n\tli\tt1, 0x1000001f\n\tor\tt0, t1\n\txori\tt0, 0x1f\n\tmtc0\tt0, CP0_STATUS\n\tehb\n\n\t/*\n\t * Some bootloaders set the 'Kseg0 coherency algorithm' to\n\t * 'Cacheable, noncoherent, write-through, no write allocate'\n\t * and this cause performance issues. Let's go and change it to\n\t * 'Cacheable, noncoherent, write-back, write allocate'\n\t */\n\tmfc0\tt0, CP0_CONFIG\n\tli\tt1, ~7\t\t\t#~CONF_CM_CMASK\n\tand\tt0, t1\n\tori\tt0, 3\t\t\t#CONF_CM_CACHABLE_NONCOHERENT\n\tmtc0\tt0, CP0_CONFIG\n\tnop\n\n\tmtc0\tzero, CP0_COUNT\n\tmtc0\tzero, CP0_COMPARE\n\tehb\n\n\tla\tt0, __reloc_label\t# get linked address of label\n\tbal\t__reloc_label\t\t# branch and link to label to\n\tnop\t\t\t\t# get actual address\n__reloc_label:\n\tsubu\tt0, ra, t0\t\t# get reloc_delta\n\n\tbeqz\tt0, __reloc_done         # if delta is 0 we are in the right place\n\tnop\n\n\t/* Copy our code to the right place */\n\tla\tt1, _code_start\t\t# get linked address of _code_start\n\tla\tt2, _code_end\t\t# get linked address of _code_end\n\taddu\tt0, t0, t1\t\t# calculate actual address of _code_start\n\n__reloc_copy:\n\tlw\tt3, 0(t0)\n\tsw\tt3, 0(t1)\n\tadd\tt1, 4\n\tblt\tt1, t2, __reloc_copy\n\tadd\tt0, 4\n\n\t/* flush cache */\n\tla\tt0, _code_start\n\tla\tt1, _code_end\n\n\tli\tt2, ~(CONFIG_CACHELINE_SIZE - 1)\n\tand\tt0, t2\n\tand\tt1, t2\n\tli\tt2, CONFIG_CACHELINE_SIZE\n\n\tb\t__flush_check\n\tnop\n\n__flush_line:\n\tcache\tHit_Writeback_Inv_D, 0(t0)\n\tcache\tHit_Invalidate_I, 0(t0)\n\tadd\tt0, t2\n\n__flush_check:\n\tbne\tt0, t1, __flush_line\n\tnop\n\n\tsync\n\n__reloc_done:\n\n\t/* clear bss */\n\tla\tt0, _bss_start\n\tla\tt1, _bss_end\n\tb\t__bss_check\n\tnop\n\n__bss_fill:\n\tsw\tzero, 0(t0)\n\taddi\tt0, 4\n\n__bss_check:\n\tbne\tt0, t1, __bss_fill\n\tnop\n\n\t/* Setup new \"C\" stack */\n\tla\tsp, _stack\n\n\t/* reserve stack space for a0-a3 registers */\n\tsubu\tsp, 16\n\n\t/* jump to the decompressor routine */\n\tla\tt0, loader_main\n\tjr\tt0\n\tnop\n\n\t.set reorder\nEND(startup)\n"
  },
  {
    "path": "target/linux/ath79/image/lzma-loader/src/loader.c",
    "content": "/*\n * LZMA compressed kernel loader for Atheros AR7XXX/AR9XXX based boards\n *\n * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>\n *\n * Some parts of this code was based on the OpenWrt specific lzma-loader\n * for the BCM47xx and ADM5120 based boards:\n *\tCopyright (C) 2004 Manuel Novoa III (mjn3@codepoet.org)\n *\tCopyright (C) 2005 Mineharu Takahara <mtakahar@yahoo.com>\n *\tCopyright (C) 2005 by Oleg I. Vdovikin <oleg@cs.msu.su>\n *\n * The image_header structure has been taken from the U-Boot project.\n *\t(C) Copyright 2008 Semihalf\n *\t(C) Copyright 2000-2005\n *\tWolfgang Denk, DENX Software Engineering, wd@denx.de.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of the GNU General Public License version 2 as published\n * by the Free Software Foundation.\n */\n\n#include <stddef.h>\n#include <stdint.h>\n\n#include \"config.h\"\n#include \"cache.h\"\n#include \"printf.h\"\n#include \"LzmaDecode.h\"\n\n#define AR71XX_FLASH_START\t0x1f000000\n#define AR71XX_FLASH_END\t0x1fe00000\n\n#define KSEG0\t\t\t0x80000000\n#define KSEG1\t\t\t0xa0000000\n\n#define KSEG1ADDR(a)\t\t((((unsigned)(a)) & 0x1fffffffU) | KSEG1)\n\n#undef LZMA_DEBUG\n\n#ifdef LZMA_DEBUG\n#  define DBG(f, a...)\tprintf(f, ## a)\n#else\n#  define DBG(f, a...)\tdo {} while (0)\n#endif\n\n#define IH_MAGIC_OKLI\t\t0x4f4b4c49\t/* 'OKLI' */\n\n#define IH_NMLEN\t\t32\t/* Image Name Length\t\t*/\n\ntypedef struct image_header {\n\tuint32_t\tih_magic;\t/* Image Header Magic Number\t*/\n\tuint32_t\tih_hcrc;\t/* Image Header CRC Checksum\t*/\n\tuint32_t\tih_time;\t/* Image Creation Timestamp\t*/\n\tuint32_t\tih_size;\t/* Image Data Size\t\t*/\n\tuint32_t\tih_load;\t/* Data\t Load  Address\t\t*/\n\tuint32_t\tih_ep;\t\t/* Entry Point Address\t\t*/\n\tuint32_t\tih_dcrc;\t/* Image Data CRC Checksum\t*/\n\tuint8_t\t\tih_os;\t\t/* Operating System\t\t*/\n\tuint8_t\t\tih_arch;\t/* CPU architecture\t\t*/\n\tuint8_t\t\tih_type;\t/* Image Type\t\t\t*/\n\tuint8_t\t\tih_comp;\t/* Compression Type\t\t*/\n\tuint8_t\t\tih_name[IH_NMLEN];\t/* Image Name\t\t*/\n} image_header_t;\n\n/* beyond the image end, size not known in advance */\nextern unsigned char workspace[];\nextern void board_init(void);\n\nstatic CLzmaDecoderState lzma_state;\nstatic unsigned char *lzma_data;\nstatic unsigned long lzma_datasize;\nstatic unsigned long lzma_outsize;\nstatic unsigned long kernel_la;\n\n#ifdef CONFIG_KERNEL_CMDLINE\n#define kernel_argc\t2\nstatic const char kernel_cmdline[] = CONFIG_KERNEL_CMDLINE;\nstatic const char *const kernel_argv[] = {\n\tNULL,\n\tkernel_cmdline,\n\tNULL,\n};\n#endif /* CONFIG_KERNEL_CMDLINE */\n\nstatic void halt(void)\n{\n\tprintf(\"\\nSystem halted!\\n\");\n\tfor(;;);\n}\n\nstatic __inline__ unsigned long get_be32(void *buf)\n{\n\tunsigned char *p = buf;\n\n\treturn (((unsigned long) p[0] << 24) +\n\t        ((unsigned long) p[1] << 16) +\n\t        ((unsigned long) p[2] << 8) +\n\t        (unsigned long) p[3]);\n}\n\nstatic __inline__ unsigned char lzma_get_byte(void)\n{\n\tunsigned char c;\n\n\tlzma_datasize--;\n\tc = *lzma_data++;\n\n\treturn c;\n}\n\nstatic int lzma_init_props(void)\n{\n\tunsigned char props[LZMA_PROPERTIES_SIZE];\n\tint res;\n\tint i;\n\n\t/* read lzma properties */\n\tfor (i = 0; i < LZMA_PROPERTIES_SIZE; i++)\n\t\tprops[i] = lzma_get_byte();\n\n\t/* read the lower half of uncompressed size in the header */\n\tlzma_outsize = ((SizeT) lzma_get_byte()) +\n\t\t       ((SizeT) lzma_get_byte() << 8) +\n\t\t       ((SizeT) lzma_get_byte() << 16) +\n\t\t       ((SizeT) lzma_get_byte() << 24);\n\n\t/* skip rest of the header (upper half of uncompressed size) */\n\tfor (i = 0; i < 4; i++)\n\t\tlzma_get_byte();\n\n\tres = LzmaDecodeProperties(&lzma_state.Properties, props,\n\t\t\t\t\tLZMA_PROPERTIES_SIZE);\n\treturn res;\n}\n\nstatic int lzma_decompress(unsigned char *outStream)\n{\n\tSizeT ip, op;\n\tint ret;\n\n\tlzma_state.Probs = (CProb *) workspace;\n\n\tret = LzmaDecode(&lzma_state, lzma_data, lzma_datasize, &ip, outStream,\n\t\t\t lzma_outsize, &op);\n\n\tif (ret != LZMA_RESULT_OK) {\n\t\tint i;\n\n\t\tDBG(\"LzmaDecode error %d at %08x, osize:%d ip:%d op:%d\\n\",\n\t\t    ret, lzma_data + ip, lzma_outsize, ip, op);\n\n\t\tfor (i = 0; i < 16; i++)\n\t\t\tDBG(\"%02x \", lzma_data[ip + i]);\n\n\t\tDBG(\"\\n\");\n\t}\n\n\treturn ret;\n}\n\n#if (LZMA_WRAPPER)\nstatic void lzma_init_data(void)\n{\n\textern unsigned char _lzma_data_start[];\n\textern unsigned char _lzma_data_end[];\n\n\tkernel_la = LOADADDR;\n\tlzma_data = _lzma_data_start;\n\tlzma_datasize = _lzma_data_end - _lzma_data_start;\n}\n#else\nstatic void lzma_init_data(void)\n{\n\tstruct image_header *hdr = NULL;\n\tunsigned char *flash_base;\n\tunsigned long flash_ofs;\n\tunsigned long kernel_ofs;\n\tunsigned long kernel_size;\n\n\tflash_base = (unsigned char *) KSEG1ADDR(AR71XX_FLASH_START);\n\n\tprintf(\"Looking for OpenWrt image... \");\n\n\tfor (flash_ofs = CONFIG_FLASH_OFFS;\n\t     flash_ofs <= (CONFIG_FLASH_OFFS + CONFIG_FLASH_MAX);\n\t     flash_ofs += CONFIG_FLASH_STEP) {\n\t\tunsigned long magic;\n\t\tunsigned char *p;\n\n\t\tp = flash_base + flash_ofs;\n\t\tmagic = get_be32(p);\n#ifdef CONFIG_KERNEL_MAGIC\n\t\tif (magic == CONFIG_KERNEL_MAGIC) {\n#else\n\t\tif (magic == IH_MAGIC_OKLI) {\n#endif\n\t\t\thdr = (struct image_header *) p;\n\t\t\tbreak;\n\t\t}\n\t}\n\n\tif (hdr == NULL) {\n\t\tprintf(\"not found!\\n\");\n\t\thalt();\n\t}\n\n\tprintf(\"found at 0x%08x\\n\", flash_base + flash_ofs);\n\n\tkernel_ofs = sizeof(struct image_header);\n\tkernel_size = get_be32(&hdr->ih_size);\n\tkernel_la = get_be32(&hdr->ih_load);\n\n\tlzma_data = flash_base + flash_ofs + kernel_ofs;\n\tlzma_datasize = kernel_size;\n}\n#endif /* (LZMA_WRAPPER) */\n\nvoid loader_main(unsigned long reg_a0, unsigned long reg_a1,\n\t\t unsigned long reg_a2, unsigned long reg_a3)\n{\n\tvoid (*kernel_entry) (unsigned long, unsigned long, unsigned long,\n\t\t\t      unsigned long);\n\tint res;\n\n\tboard_init();\n\n\tprintf(\"\\n\\nOpenWrt kernel loader for AR7XXX/AR9XXX\\n\");\n\tprintf(\"Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>\\n\");\n\n\tlzma_init_data();\n\n\tres = lzma_init_props();\n\tif (res != LZMA_RESULT_OK) {\n\t\tprintf(\"Incorrect LZMA stream properties!\\n\");\n\t\thalt();\n\t}\n\n\tprintf(\"Decompressing kernel... \");\n\n\tres = lzma_decompress((unsigned char *) kernel_la);\n\tif (res != LZMA_RESULT_OK) {\n\t\tprintf(\"failed, \");\n\t\tswitch (res) {\n\t\tcase LZMA_RESULT_DATA_ERROR:\n\t\t\tprintf(\"data error!\\n\");\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tprintf(\"unknown error %d!\\n\", res);\n\t\t}\n\t\thalt();\n\t} else {\n\t\tprintf(\"done!\\n\");\n\t}\n\n\tflush_cache(kernel_la, lzma_outsize);\n\n\tprintf(\"Starting kernel at %08x...\\n\\n\", kernel_la);\n\n#ifdef CONFIG_KERNEL_CMDLINE\n\treg_a0 = kernel_argc;\n\treg_a1 = (unsigned long) kernel_argv;\n\treg_a2 = 0;\n\treg_a3 = 0;\n#endif\n\n\tkernel_entry = (void *) kernel_la;\n\tkernel_entry(reg_a0, reg_a1, reg_a2, reg_a3);\n}\n"
  },
  {
    "path": "target/linux/ath79/image/lzma-loader/src/loader.lds",
    "content": "OUTPUT_ARCH(mips)\nSECTIONS {\n\t.text : {\n\t\t_code_start = .;\n\t\t*(.text)\n\t\t*(.text.*)\n\t\t*(.rodata)\n\t\t*(.rodata.*)\n\t\t*(.data.lzma)\n\t}\n\n\t. = ALIGN(32);\n\t.data : {\n\t\t*(.data)\n\t\t*(.data.*)\n\t}\n\n\t. = ALIGN(32);\n\t_code_end = .;\n\n\t_bss_start = .;\n\t.bss : {\n\t\t*(.bss)\n\t\t*(.bss.*)\n\t}\n\n\t. = ALIGN(32);\n\t_bss_end = .;\n\n\t. = . + 8192;\n\t_stack = .;\n\n\tworkspace = .;\n}\n"
  },
  {
    "path": "target/linux/ath79/image/lzma-loader/src/loader2.lds",
    "content": "OUTPUT_ARCH(mips)\nSECTIONS {\n\t.text : {\n\t\tstartup = .;\n\t\t*(.text)\n\t\t*(.text.*)\n\t\t*(.data)\n\t\t*(.data.*)\n\t}\n}\n"
  },
  {
    "path": "target/linux/ath79/image/lzma-loader/src/lzma-data.lds",
    "content": "OUTPUT_ARCH(mips)\nSECTIONS {\n\t.data.lzma : {\n\t\t_lzma_data_start = .;\n\t\t*(.data)\n\t\t_lzma_data_end = .;\n\t}\n}\n"
  },
  {
    "path": "target/linux/ath79/image/lzma-loader/src/printf.c",
    "content": "/*\n * Copyright (C) 2001 MontaVista Software Inc.\n * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net\n *\n * This program is free software; you can redistribute  it and/or modify it\n * under  the terms of  the GNU General  Public License as published by the\n * Free Software Foundation;  either version 2 of the  License, or (at your\n * option) any later version.\n *\n */\n\n#include\t\"printf.h\"\n\nextern void board_putc(int ch);\n\n/* this is the maximum width for a variable */\n#define\t\tLP_MAX_BUF\t256\n\n/* macros */\n#define\t\tIsDigit(x)\t( ((x) >= '0') && ((x) <= '9') )\n#define\t\tCtod(x)\t\t( (x) - '0')\n\n/* forward declaration */\nstatic int PrintChar(char *, char, int, int);\nstatic int PrintString(char *, char *, int, int);\nstatic int PrintNum(char *, unsigned long, int, int, int, int, char, int);\n\n/* private variable */\nstatic const char theFatalMsg[] = \"fatal error in lp_Print!\";\n\n/* -*-\n * A low level printf() function.\n */\nstatic void\nlp_Print(void (*output)(void *, char *, int),\n\t void * arg,\n\t char *fmt,\n\t va_list ap)\n{\n\n#define \tOUTPUT(arg, s, l)  \\\n  { if (((l) < 0) || ((l) > LP_MAX_BUF)) { \\\n       (*output)(arg, (char*)theFatalMsg, sizeof(theFatalMsg)-1); for(;;); \\\n    } else { \\\n      (*output)(arg, s, l); \\\n    } \\\n  }\n\n    char buf[LP_MAX_BUF];\n\n    char c;\n    char *s;\n    long int num;\n\n    int longFlag;\n    int negFlag;\n    int width;\n    int prec;\n    int ladjust;\n    char padc;\n\n    int length;\n\n    for(;;) {\n\t{\n\t    /* scan for the next '%' */\n\t    char *fmtStart = fmt;\n\t    while ( (*fmt != '\\0') && (*fmt != '%')) {\n\t\tfmt ++;\n\t    }\n\n\t    /* flush the string found so far */\n\t    OUTPUT(arg, fmtStart, fmt-fmtStart);\n\n\t    /* are we hitting the end? */\n\t    if (*fmt == '\\0') break;\n\t}\n\n\t/* we found a '%' */\n\tfmt ++;\n\n\t/* check for long */\n\tif (*fmt == 'l') {\n\t    longFlag = 1;\n\t    fmt ++;\n\t} else {\n\t    longFlag = 0;\n\t}\n\n\t/* check for other prefixes */\n\twidth = 0;\n\tprec = -1;\n\tladjust = 0;\n\tpadc = ' ';\n\n\tif (*fmt == '-') {\n\t    ladjust = 1;\n\t    fmt ++;\n\t}\n\n\tif (*fmt == '0') {\n\t    padc = '0';\n\t    fmt++;\n\t}\n\n\tif (IsDigit(*fmt)) {\n\t    while (IsDigit(*fmt)) {\n\t\twidth = 10 * width + Ctod(*fmt++);\n\t    }\n\t}\n\n\tif (*fmt == '.') {\n\t    fmt ++;\n\t    if (IsDigit(*fmt)) {\n\t\tprec = 0;\n\t\twhile (IsDigit(*fmt)) {\n\t\t    prec = prec*10 + Ctod(*fmt++);\n\t\t}\n\t    }\n\t}\n\n\n\t/* check format flag */\n\tnegFlag = 0;\n\tswitch (*fmt) {\n\t case 'b':\n\t    if (longFlag) {\n\t\tnum = va_arg(ap, long int);\n\t    } else {\n\t\tnum = va_arg(ap, int);\n\t    }\n\t    length = PrintNum(buf, num, 2, 0, width, ladjust, padc, 0);\n\t    OUTPUT(arg, buf, length);\n\t    break;\n\n\t case 'd':\n\t case 'D':\n\t    if (longFlag) {\n\t\tnum = va_arg(ap, long int);\n\t    } else {\n\t\tnum = va_arg(ap, int);\n\t    }\n\t    if (num < 0) {\n\t\tnum = - num;\n\t\tnegFlag = 1;\n\t    }\n\t    length = PrintNum(buf, num, 10, negFlag, width, ladjust, padc, 0);\n\t    OUTPUT(arg, buf, length);\n\t    break;\n\n\t case 'o':\n\t case 'O':\n\t    if (longFlag) {\n\t\tnum = va_arg(ap, long int);\n\t    } else {\n\t\tnum = va_arg(ap, int);\n\t    }\n\t    length = PrintNum(buf, num, 8, 0, width, ladjust, padc, 0);\n\t    OUTPUT(arg, buf, length);\n\t    break;\n\n\t case 'u':\n\t case 'U':\n\t    if (longFlag) {\n\t\tnum = va_arg(ap, long int);\n\t    } else {\n\t\tnum = va_arg(ap, int);\n\t    }\n\t    length = PrintNum(buf, num, 10, 0, width, ladjust, padc, 0);\n\t    OUTPUT(arg, buf, length);\n\t    break;\n\n\t case 'x':\n\t    if (longFlag) {\n\t\tnum = va_arg(ap, long int);\n\t    } else {\n\t\tnum = va_arg(ap, int);\n\t    }\n\t    length = PrintNum(buf, num, 16, 0, width, ladjust, padc, 0);\n\t    OUTPUT(arg, buf, length);\n\t    break;\n\n\t case 'X':\n\t    if (longFlag) {\n\t\tnum = va_arg(ap, long int);\n\t    } else {\n\t\tnum = va_arg(ap, int);\n\t    }\n\t    length = PrintNum(buf, num, 16, 0, width, ladjust, padc, 1);\n\t    OUTPUT(arg, buf, length);\n\t    break;\n\n\t case 'c':\n\t    c = (char)va_arg(ap, int);\n\t    length = PrintChar(buf, c, width, ladjust);\n\t    OUTPUT(arg, buf, length);\n\t    break;\n\n\t case 's':\n\t    s = (char*)va_arg(ap, char *);\n\t    length = PrintString(buf, s, width, ladjust);\n\t    OUTPUT(arg, buf, length);\n\t    break;\n\n\t case '\\0':\n\t    fmt --;\n\t    break;\n\n\t default:\n\t    /* output this char as it is */\n\t    OUTPUT(arg, fmt, 1);\n\t}\t/* switch (*fmt) */\n\n\tfmt ++;\n    }\t\t/* for(;;) */\n\n    /* special termination call */\n    OUTPUT(arg, \"\\0\", 1);\n}\n\n\n/* --------------- local help functions --------------------- */\nstatic int\nPrintChar(char * buf, char c, int length, int ladjust)\n{\n    int i;\n\n    if (length < 1) length = 1;\n    if (ladjust) {\n\t*buf = c;\n\tfor (i=1; i< length; i++) buf[i] = ' ';\n    } else {\n\tfor (i=0; i< length-1; i++) buf[i] = ' ';\n\tbuf[length - 1] = c;\n    }\n    return length;\n}\n\nstatic int\nPrintString(char * buf, char* s, int length, int ladjust)\n{\n    int i;\n    int len=0;\n    char* s1 = s;\n    while (*s1++) len++;\n    if (length < len) length = len;\n\n    if (ladjust) {\n\tfor (i=0; i< len; i++) buf[i] = s[i];\n\tfor (i=len; i< length; i++) buf[i] = ' ';\n    } else {\n\tfor (i=0; i< length-len; i++) buf[i] = ' ';\n\tfor (i=length-len; i < length; i++) buf[i] = s[i-length+len];\n    }\n    return length;\n}\n\nstatic int\nPrintNum(char * buf, unsigned long u, int base, int negFlag,\n\t int length, int ladjust, char padc, int upcase)\n{\n    /* algorithm :\n     *  1. prints the number from left to right in reverse form.\n     *  2. fill the remaining spaces with padc if length is longer than\n     *     the actual length\n     *     TRICKY : if left adjusted, no \"0\" padding.\n     *\t\t    if negtive, insert  \"0\" padding between \"0\" and number.\n     *  3. if (!ladjust) we reverse the whole string including paddings\n     *  4. otherwise we only reverse the actual string representing the num.\n     */\n\n    int actualLength =0;\n    char *p = buf;\n    int i;\n\n    do {\n\tint tmp = u %base;\n\tif (tmp <= 9) {\n\t    *p++ = '0' + tmp;\n\t} else if (upcase) {\n\t    *p++ = 'A' + tmp - 10;\n\t} else {\n\t    *p++ = 'a' + tmp - 10;\n\t}\n\tu /= base;\n    } while (u != 0);\n\n    if (negFlag) {\n\t*p++ = '-';\n    }\n\n    /* figure out actual length and adjust the maximum length */\n    actualLength = p - buf;\n    if (length < actualLength) length = actualLength;\n\n    /* add padding */\n    if (ladjust) {\n\tpadc = ' ';\n    }\n    if (negFlag && !ladjust && (padc == '0')) {\n\tfor (i = actualLength-1; i< length-1; i++) buf[i] = padc;\n\tbuf[length -1] = '-';\n    } else {\n\tfor (i = actualLength; i< length; i++) buf[i] = padc;\n    }\n\n\n    /* prepare to reverse the string */\n    {\n\tint begin = 0;\n\tint end;\n\tif (ladjust) {\n\t    end = actualLength - 1;\n\t} else {\n\t    end = length -1;\n\t}\n\n\twhile (end > begin) {\n\t    char tmp = buf[begin];\n\t    buf[begin] = buf[end];\n\t    buf[end] = tmp;\n\t    begin ++;\n\t    end --;\n\t}\n    }\n\n    /* adjust the string pointer */\n    return length;\n}\n\nstatic void printf_output(void *arg, char *s, int l)\n{\n    int i;\n\n    // special termination call\n    if ((l==1) && (s[0] == '\\0')) return;\n\n    for (i=0; i< l; i++) {\n\tboard_putc(s[i]);\n\tif (s[i] == '\\n') board_putc('\\r');\n    }\n}\n\nvoid printf(char *fmt, ...)\n{\n    va_list ap;\n    va_start(ap, fmt);\n    lp_Print(printf_output, 0, fmt, ap);\n    va_end(ap);\n}\n"
  },
  {
    "path": "target/linux/ath79/image/lzma-loader/src/printf.h",
    "content": "/*\n * Copyright (C) 2001 MontaVista Software Inc.\n * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net\n *\n * This program is free software; you can redistribute  it and/or modify it\n * under  the terms of  the GNU General  Public License as published by the\n * Free Software Foundation;  either version 2 of the  License, or (at your\n * option) any later version.\n *\n */\n\n#ifndef _printf_h_\n#define _printf_h_\n\n#include <stdarg.h>\nvoid printf(char *fmt, ...);\n\n#endif /* _printf_h_ */\n"
  },
  {
    "path": "target/linux/ath79/image/mikrotik.mk",
    "content": "include ./common-mikrotik.mk\n\ndefine Device/mikrotik_routerboard-493g\n  $(Device/mikrotik_nand)\n  SOC := ar7161\n  DEVICE_MODEL := RouterBOARD 493G\n  DEVICE_PACKAGES += kmod-usb-ohci kmod-usb2\n  SUPPORTED_DEVICES += rb-493g\nendef\nTARGET_DEVICES += mikrotik_routerboard-493g\n\ndefine Device/mikrotik_routerboard-912uag-2hpnd\n  $(Device/mikrotik_nand)\n  SOC := ar9342\n  DEVICE_MODEL := RouterBOARD 912UAG-2HPnD\n  DEVICE_PACKAGES += kmod-usb-ehci kmod-usb2\n  SUPPORTED_DEVICES += rb-912uag-2hpnd\nendef\nTARGET_DEVICES += mikrotik_routerboard-912uag-2hpnd\n\ndefine Device/mikrotik_routerboard-921gs-5hpacd-15s\n  $(Device/mikrotik_nand)\n  SOC := qca9558\n  DEVICE_MODEL := RouterBOARD 921GS-5HPacD-15s (mANTBox 15s)\n  DEVICE_PACKAGES += kmod-ath10k-ct ath10k-firmware-qca988x-ct kmod-i2c-gpio \\\n\tkmod-sfp\n  SUPPORTED_DEVICES += rb-921gs-5hpacd-r2\nendef\nTARGET_DEVICES += mikrotik_routerboard-921gs-5hpacd-15s\n\ndefine Device/mikrotik_routerboard-922uags-5hpacd\n  $(Device/mikrotik_nand)\n  SOC := qca9558\n  DEVICE_MODEL := RouterBOARD 922UAGS-5HPacD\n  DEVICE_PACKAGES += kmod-ath10k-ct ath10k-firmware-qca988x-ct kmod-usb2 \\\n\tkmod-i2c-gpio kmod-sfp\n  SUPPORTED_DEVICES += rb-922uags-5hpacd\nendef\nTARGET_DEVICES += mikrotik_routerboard-922uags-5hpacd\n\ndefine Device/mikrotik_routerboard-962uigs-5hact2hnt\n  $(Device/mikrotik_nor)\n  SOC := qca9558\n  DEVICE_MODEL := RouterBOARD 962UiGS-5HacT2HnT (hAP ac)\n  DEVICE_PACKAGES += kmod-ath10k-ct ath10k-firmware-qca988x-ct kmod-usb2 \\\n\tkmod-i2c-gpio kmod-sfp\n  IMAGE_SIZE := 16256k\n  SUPPORTED_DEVICES += rb-962uigs-5hact2hnt\nendef\nTARGET_DEVICES += mikrotik_routerboard-962uigs-5hact2hnt\n\ndefine Device/mikrotik_routerboard-lhg-2nd\n  $(Device/mikrotik_nor)\n  SOC := qca9533\n  DEVICE_MODEL := RouterBOARD LHG 2nD (LHG 2)\n  IMAGE_SIZE := 16256k\nendef\nTARGET_DEVICES += mikrotik_routerboard-lhg-2nd\n\ndefine Device/mikrotik_routerboard-lhg-5nd\n  $(Device/mikrotik_nor)\n  SOC := ar9344\n  DEVICE_MODEL := RouterBOARD LHG 5nD (LHG 5)\n  DEVICE_PACKAGES += rssileds\n  IMAGE_SIZE := 16256k\nendef\nTARGET_DEVICES += mikrotik_routerboard-lhg-5nd\n\ndefine Device/mikrotik_routerboard-mapl-2nd\n  $(Device/mikrotik_nor)\n  SOC := qca9533\n  DEVICE_MODEL := RouterBOARD mAPL-2nD (mAP lite)\n  IMAGE_SIZE := 16256k\nendef\nTARGET_DEVICES += mikrotik_routerboard-mapl-2nd\n\ndefine Device/mikrotik_routerboard-sxt-5nd-r2\n  $(Device/mikrotik_nand)\n  SOC := ar9344\n  DEVICE_MODEL := RouterBOARD SXT 5nD r2 (SXT Lite5)\n  DEVICE_PACKAGES += rssileds kmod-gpio-beeper\n  SUPPORTED_DEVICES += rb-sxt5n\nendef\nTARGET_DEVICES += mikrotik_routerboard-sxt-5nd-r2\n\ndefine Device/mikrotik_routerboard-wap-g-5hact2hnd\n  $(Device/mikrotik_nor)\n  SOC := qca9556\n  DEVICE_MODEL := RouterBOARD wAP G-5HacT2HnD (wAP AC)\n  IMAGE_SIZE := 16256k\n  DEVICE_PACKAGES += kmod-ath10k-ct-smallbuffers ath10k-firmware-qca988x-ct\n  SUPPORTED_DEVICES += rb-wapg-5hact2hnd\nendef\nTARGET_DEVICES += mikrotik_routerboard-wap-g-5hact2hnd\n\ndefine Device/mikrotik_routerboard-wapr-2nd\n  $(Device/mikrotik_nor)\n  SOC := qca9533\n  DEVICE_MODEL := RouterBOARD wAPR-2nD (wAP R)\n  DEVICE_PACKAGES += kmod-usb2 rssileds\n  IMAGE_SIZE := 16256k\nendef\nTARGET_DEVICES += mikrotik_routerboard-wapr-2nd\n\ndefine Device/mikrotik_routerboard-wap-2nd\n  $(Device/mikrotik_nor)\n  SOC := qca9533\n  DEVICE_MODEL := RouterBOARD wAP-2nD (wAP)\n  IMAGE_SIZE := 16256k\nendef\nTARGET_DEVICES += mikrotik_routerboard-wap-2nd\n"
  },
  {
    "path": "target/linux/ath79/image/nand.mk",
    "content": "define Build/dongwon-header\n\thead -c 4 $@ > $@.tmp\n\thead -c 8 /dev/zero >> $@.tmp\n\ttail -c +9 $@ >> $@.tmp\n\t( \\\n\t\theader_crc=\"$$(head -c 68 $@.tmp | gzip -c | \\\n\t\t\ttail -c 8 | od -An -N4 -tx4 --endian little | tr -d ' \\n')\"; \\\n\t\tprintf \"$$(echo $$header_crc | sed 's/../\\\\x&/g')\" | \\\n\t\t\tdd of=$@.tmp bs=4 count=1 seek=1 conv=notrunc \\\n\t)\n\tmv $@.tmp $@\nendef\n\n# attention: only zlib compression is allowed for the boot fs\ndefine Build/zyxel-buildkerneljffs\n\tmkdir -p $@.tmp/boot\n\tcp $@ $@.tmp/boot/vmlinux.lzma.uImage\n\t$(STAGING_DIR_HOST)/bin/mkfs.jffs2 \\\n\t\t--big-endian --squash-uids -v -e 128KiB -q -f -n -x lzma -x rtime \\\n\t\t-o $@ \\\n\t\t-d $@.tmp\n\trm -rf $@.tmp\nendef\n\ndefine Build/zyxel-factory\n\tlet \\\n\t\tmaxsize=\"$(subst k,* 1024,$(RAS_ROOTFS_SIZE))\"; \\\n\t\tlet size=\"$$(stat -c%s $@)\"; \\\n\t\tif [ $$size -lt $$maxsize ]; then \\\n\t\t\t$(STAGING_DIR_HOST)/bin/mkrasimage \\\n\t\t\t\t-b $(RAS_BOARD) \\\n\t\t\t\t-v $(RAS_VERSION) \\\n\t\t\t\t-r $@ \\\n\t\t\t\t-s $$maxsize \\\n\t\t\t\t-o $@.new \\\n\t\t\t\t-l 131072 \\\n\t\t\t&& mv $@.new $@ ; \\\n\t\tfi\nendef\n\ndefine Device/8dev_rambutan\n  SOC := qca9557\n  DEVICE_VENDOR := 8devices\n  DEVICE_MODEL := Rambutan\n  DEVICE_PACKAGES := kmod-usb2\n  BLOCKSIZE := 128k\n  PAGESIZE := 2048\n  KERNEL_SIZE := 4096k\n  KERNEL_IN_UBI := 1\n  IMAGES := factory.bin sysupgrade.tar\n  IMAGE/sysupgrade.tar := sysupgrade-tar | append-metadata\n  IMAGE/factory.bin := append-ubi\nendef\nTARGET_DEVICES += 8dev_rambutan\n\ndefine Device/aerohive_hiveap-121\n  SOC := ar9344\n  DEVICE_VENDOR := Aerohive\n  DEVICE_MODEL := HiveAP 121\n  DEVICE_PACKAGES := kmod-usb2\n  BLOCKSIZE := 128k\n  PAGESIZE := 2048\n  IMAGE_SIZE := 116m\n  KERNEL_SIZE := 5120k\n  UBINIZE_OPTS := -E 5\n  SUPPORTED_DEVICES += hiveap-121\n  IMAGES += factory.bin\n  IMAGE/factory.bin := append-kernel | pad-to $$$$(KERNEL_SIZE) | append-ubi | \\\n\tcheck-size\n  IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata\nendef\nTARGET_DEVICES += aerohive_hiveap-121\n\ndefine Device/domywifi_dw33d\n  SOC := qca9558\n  DEVICE_VENDOR := DomyWifi\n  DEVICE_MODEL := DW33D\n  DEVICE_PACKAGES := kmod-usb2 kmod-usb-storage kmod-usb-ledtrig-usbport \\\n\tkmod-ath10k-ct ath10k-firmware-qca988x-ct\n  KERNEL_SIZE := 5120k\n  IMAGE_SIZE := 98304k\n  BLOCKSIZE := 128k\n  PAGESIZE := 2048\n  UBINIZE_OPTS := -E 5\n  IMAGES += factory.bin\n  IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata\n  IMAGE/factory.bin := append-kernel | pad-to $$$$(KERNEL_SIZE) | append-ubi | \\\n\tcheck-size\nendef\nTARGET_DEVICES += domywifi_dw33d\n\ndefine Device/dongwon_dw02-412h\n  SOC := qca9557\n  DEVICE_VENDOR := Dongwon T&I\n  DEVICE_MODEL := DW02-412H\n  DEVICE_ALT0_VENDOR := KT\n  DEVICE_ALT0_MODEL := GiGA WiFi home\n  DEVICE_PACKAGES := kmod-usb2 kmod-ath10k-ct ath10k-firmware-qca988x-ct\n  KERNEL_SIZE := 8192k\n  BLOCKSIZE := 128k\n  PAGESIZE := 2048\n  KERNEL := $$(KERNEL) | dongwon-header\n  KERNEL_INITRAMFS := $$(KERNEL)\n  UBINIZE_OPTS := -E 5\n  IMAGES += factory.img\n  IMAGE/factory.img := append-kernel | pad-to $$$$(KERNEL_SIZE) | append-ubi | \\\n\tcheck-size\n  IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata\nendef\n\ndefine Device/dongwon_dw02-412h-64m\n  $(Device/dongwon_dw02-412h)\n  DEVICE_VARIANT := (64M)\n  DEVICE_ALT0_VARIANT := (64M)\n  IMAGE_SIZE := 49152k\nendef\nTARGET_DEVICES += dongwon_dw02-412h-64m\n\ndefine Device/dongwon_dw02-412h-128m\n  $(Device/dongwon_dw02-412h)\n  DEVICE_VARIANT := (128M)\n  DEVICE_ALT0_VARIANT := (128M)\n  IMAGE_SIZE := 114688k\nendef\nTARGET_DEVICES += dongwon_dw02-412h-128m\n\ndefine Device/glinet_gl-ar300m-common-nand\n  SOC := qca9531\n  DEVICE_VENDOR := GL.iNet\n  DEVICE_MODEL := GL-AR300M\n  DEVICE_PACKAGES := kmod-usb2\n  KERNEL_SIZE := 4096k\n  IMAGE_SIZE := 16000k\n  PAGESIZE := 2048\n  VID_HDR_OFFSET := 2048\nendef\n\ndefine Device/glinet_gl-ar300m-nand\n  $(Device/glinet_gl-ar300m-common-nand)\n  DEVICE_VARIANT := NAND\n  BLOCKSIZE := 128k\n  IMAGES += factory.img\n  IMAGE/factory.img := append-kernel | pad-to $$$$(KERNEL_SIZE) | append-ubi\n  IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata\n  SUPPORTED_DEVICES += glinet,gl-ar300m-nor\nendef\nTARGET_DEVICES += glinet_gl-ar300m-nand\n\ndefine Device/glinet_gl-ar300m-nor\n  $(Device/glinet_gl-ar300m-common-nand)\n  DEVICE_VARIANT := NOR\n  SUPPORTED_DEVICES += glinet,gl-ar300m-nand gl-ar300m\nendef\nTARGET_DEVICES += glinet_gl-ar300m-nor\n\ndefine Device/glinet_gl-ar750s-common\n  SOC := qca9563\n  DEVICE_VENDOR := GL.iNet\n  DEVICE_MODEL := GL-AR750S\n  DEVICE_PACKAGES := kmod-ath10k-ct ath10k-firmware-qca9887-ct kmod-usb2 \\\n\tkmod-usb-storage block-mount\n  IMAGE_SIZE := 16000k\nendef\n\ndefine Device/glinet_gl-ar750s-nor-nand\n  $(Device/glinet_gl-ar750s-common)\n  DEVICE_VARIANT := NOR/NAND\n  KERNEL_SIZE := 4096k\n  IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata\n  SUPPORTED_DEVICES += glinet,gl-ar750s-nor\nendef\nTARGET_DEVICES += glinet_gl-ar750s-nor-nand\n\ndefine Device/glinet_gl-ar750s-nor\n  $(Device/glinet_gl-ar750s-common)\n  DEVICE_VARIANT := NOR\n  SUPPORTED_DEVICES += gl-ar750s glinet,gl-ar750s glinet,gl-ar750s-nor-nand\nendef\nTARGET_DEVICES += glinet_gl-ar750s-nor\n\ndefine Device/glinet_gl-e750\n  SOC := qca9531\n  DEVICE_VENDOR := GL.iNet\n  DEVICE_MODEL := GL-E750\n  DEVICE_PACKAGES := kmod-ath10k-ct ath10k-firmware-qca9887-ct kmod-usb2\n  SUPPORTED_DEVICES += gl-e750\n  KERNEL_SIZE := 4096k\n  IMAGE_SIZE := 131072k\n  PAGESIZE := 2048\n  VID_HDR_OFFSET := 2048\n  BLOCKSIZE := 128k\n  IMAGES += factory.img\n  IMAGE/factory.img := append-kernel | pad-to $$$$(KERNEL_SIZE) | append-ubi\n  IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata\nendef\nTARGET_DEVICES += glinet_gl-e750\n\ndefine Device/glinet_gl-xe300\n  SOC := qca9531\n  DEVICE_VENDOR := GL.iNet\n  DEVICE_MODEL := GL-XE300\n  DEVICE_PACKAGES := kmod-usb2 block-mount kmod-usb-serial-ch341\n  KERNEL_SIZE := 4096k\n  IMAGE_SIZE := 131072k\n  PAGESIZE := 2048\n  VID_HDR_OFFSET := 2048\n  BLOCKSIZE := 128k\n  IMAGES += factory.img\n  IMAGE/factory.img := append-kernel | pad-to $$$$(KERNEL_SIZE) | append-ubi\n  IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata\nendef\nTARGET_DEVICES += glinet_gl-xe300\n\n# fake rootfs is mandatory, pad-offset 129 equals (2 * uimage_header + 0xff)\ndefine Device/netgear_ath79_nand\n  DEVICE_VENDOR := NETGEAR\n  DEVICE_PACKAGES := kmod-usb2 kmod-usb-ledtrig-usbport\n  KERNEL_SIZE := 4096k\n  BLOCKSIZE := 128k\n  PAGESIZE := 2048\n  IMAGE_SIZE := 25600k\n  KERNEL := kernel-bin | append-dtb | lzma -d20 | \\\n\tpad-offset $$(KERNEL_SIZE) 129 | uImage lzma | \\\n\tappend-string -e '\\xff' | \\\n\tappend-uImage-fakehdr filesystem $$(UIMAGE_MAGIC)\n  KERNEL_INITRAMFS := kernel-bin | append-dtb | lzma -d20 | uImage lzma\n  IMAGES := sysupgrade.bin factory.img\n  IMAGE/factory.img := append-kernel | append-ubi | netgear-dni | \\\n\tcheck-size\n  IMAGE/sysupgrade.bin := sysupgrade-tar | check-size | append-metadata\n  UBINIZE_OPTS := -E 5\nendef\n\ndefine Device/netgear_r6100\n  SOC := ar9344\n  DEVICE_MODEL := R6100\n  UIMAGE_MAGIC := 0x36303030\n  NETGEAR_BOARD_ID := R6100\n  NETGEAR_HW_ID := 29764434+0+128+128+2x2+2x2\n  $(Device/netgear_ath79_nand)\n  DEVICE_PACKAGES += kmod-ath10k-ct ath10k-firmware-qca988x-ct\nendef\nTARGET_DEVICES += netgear_r6100\n\ndefine Device/netgear_wndr3700-v4\n  SOC := ar9344\n  DEVICE_MODEL := WNDR3700\n  DEVICE_VARIANT := v4\n  UIMAGE_MAGIC := 0x33373033\n  NETGEAR_BOARD_ID := WNDR3700v4\n  NETGEAR_HW_ID := 29763948+128+128\n  $(Device/netgear_ath79_nand)\nendef\nTARGET_DEVICES += netgear_wndr3700-v4\n\ndefine Device/netgear_wndr4300\n  SOC := ar9344\n  DEVICE_MODEL := WNDR4300\n  UIMAGE_MAGIC := 0x33373033\n  NETGEAR_BOARD_ID := WNDR4300\n  NETGEAR_HW_ID := 29763948+0+128+128+2x2+3x3\n  $(Device/netgear_ath79_nand)\nendef\nTARGET_DEVICES += netgear_wndr4300\n\ndefine Device/netgear_wndr4300sw\n  SOC := ar9344\n  DEVICE_MODEL := WNDR4300SW\n  UIMAGE_MAGIC := 0x33373033\n  NETGEAR_BOARD_ID := WNDR4300SW\n  NETGEAR_HW_ID := 29763948+0+128+128+2x2+3x3\n  $(Device/netgear_ath79_nand)\nendef\nTARGET_DEVICES += netgear_wndr4300sw\n\ndefine Device/netgear_wndr4300tn\n  SOC := ar9344\n  DEVICE_MODEL := WNDR4300TN\n  UIMAGE_MAGIC := 0x33373033\n  NETGEAR_BOARD_ID := WNDR4300TN\n  NETGEAR_HW_ID := 29763948+0+128+128+2x2+3x3\n  $(Device/netgear_ath79_nand)\nendef\nTARGET_DEVICES += netgear_wndr4300tn\n\ndefine Device/netgear_wndr4300-v2\n  SOC := qca9563\n  DEVICE_MODEL := WNDR4300\n  DEVICE_VARIANT := v2\n  UIMAGE_MAGIC := 0x27051956\n  NETGEAR_BOARD_ID := WNDR4500series\n  NETGEAR_HW_ID := 29764821+2+128+128+3x3+3x3+5508012175\n  $(Device/netgear_ath79_nand)\nendef\nTARGET_DEVICES += netgear_wndr4300-v2\n\ndefine Device/netgear_wndr4500-v3\n  SOC := qca9563\n  DEVICE_MODEL := WNDR4500\n  DEVICE_VARIANT := v3\n  UIMAGE_MAGIC := 0x27051956\n  NETGEAR_BOARD_ID := WNDR4500series\n  NETGEAR_HW_ID := 29764821+2+128+128+3x3+3x3+5508012173\n  $(Device/netgear_ath79_nand)\nendef\nTARGET_DEVICES += netgear_wndr4500-v3\n\ndefine Device/zte_mf286_common\n  SOC := qca9563\n  DEVICE_VENDOR := ZTE\n  DEVICE_PACKAGES := kmod-usb2 kmod-ath10k-ct\n  BLOCKSIZE := 128k\n  PAGESIZE := 2048\n  KERNEL_SIZE := 4096k\n  IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata\nendef\n\ndefine Device/zte_mf286\n  $(Device/zte_mf286_common)\n  DEVICE_MODEL := MF286\n  DEVICE_PACKAGES += ath10k-firmware-qca988x-ct kmod-usb-net-qmi-wwan \\\n\tkmod-usb-serial-option uqmi\nendef\nTARGET_DEVICES += zte_mf286\n\ndefine Device/zte_mf286a\n  $(Device/zte_mf286_common)\n  DEVICE_MODEL := MF286A\n  DEVICE_PACKAGES += ath10k-firmware-qca9888-ct kmod-usb-net-qmi-wwan \\\n\tkmod-usb-serial-option uqmi\nendef\nTARGET_DEVICES += zte_mf286a\n\ndefine Device/zte_mf286r\n  $(Device/zte_mf286_common)\n  DEVICE_MODEL := MF286R\n  DEVICE_PACKAGES += ath10k-firmware-qca9888-ct kmod-usb-net-rndis kmod-usb-acm \\\n\tcomgt-ncm\nendef\nTARGET_DEVICES += zte_mf286r\n\ndefine Device/zyxel_nbg6716\n  SOC := qca9558\n  DEVICE_VENDOR := ZyXEL\n  DEVICE_MODEL := NBG6716\n  DEVICE_PACKAGES := kmod-usb2 kmod-usb-ledtrig-usbport kmod-ath10k-ct \\\n\tath10k-firmware-qca988x-ct\n  RAS_BOARD := NBG6716\n  RAS_ROOTFS_SIZE := 29696k\n  RAS_VERSION := \"OpenWrt Linux-$(LINUX_VERSION)\"\n  KERNEL_SIZE := 4096k\n  BLOCKSIZE := 128k\n  PAGESIZE := 2048\n  LOADER_TYPE := bin\n  KERNEL := kernel-bin | append-dtb | lzma | loader-kernel | uImage none | \\\n\tzyxel-buildkerneljffs | check-size 4096k\n  IMAGES := sysupgrade.tar sysupgrade-4M-Kernel.bin factory.bin\n  IMAGE/sysupgrade.tar/squashfs := append-rootfs | pad-to $$$$(BLOCKSIZE) | \\\n\tsysupgrade-tar rootfs=$$$$@ | append-metadata\n  IMAGE/sysupgrade-4M-Kernel.bin/squashfs := append-kernel | \\\n\tpad-to $$$$(KERNEL_SIZE) | append-ubi | pad-to 263192576 | gzip\n  IMAGE/factory.bin := append-kernel | pad-to $$$$(KERNEL_SIZE) | append-ubi | \\\n\tzyxel-factory\n  UBINIZE_OPTS := -E 5\nendef\nTARGET_DEVICES += zyxel_nbg6716\n\ndefine Device/zyxel_emg2926_q10a\n  $(Device/zyxel_nbg6716)\n  DEVICE_MODEL := EMG2926-Q10A\n  RAS_BOARD := AAVK-EMG2926Q10A\nendef\nTARGET_DEVICES += zyxel_emg2926_q10a\n"
  },
  {
    "path": "target/linux/ath79/image/tiny-netgear.mk",
    "content": "include ./common-netgear.mk\n\ndefine Device/netgear_wnr612-v2\n  $(Device/netgear_generic)\n  SOC := ar7240\n  DEVICE_MODEL := WNR612\n  DEVICE_VARIANT := v2\n  DEVICE_DTS := ar7240_netgear_wnr612-v2\n  UIMAGE_MAGIC := 0x32303631\n  NETGEAR_BOARD_ID := REALWNR612V2\n  IMAGE_SIZE := 3712k\n  SUPPORTED_DEVICES += wnr612-v2\n  DEFAULT := n\nendef\nTARGET_DEVICES += netgear_wnr612-v2\n\ndefine Device/on_n150r\n  $(Device/netgear_generic)\n  SOC := ar7240\n  DEVICE_VENDOR := On Networks\n  DEVICE_MODEL := N150R\n  UIMAGE_MAGIC := 0x32303631\n  NETGEAR_BOARD_ID := N150R\n  IMAGE_SIZE := 3712k\n  SUPPORTED_DEVICES += n150r\n  DEFAULT := n\nendef\nTARGET_DEVICES += on_n150r\n\ndefine Device/netgear_wnr1000-v2\n  $(Device/netgear_generic)\n  SOC := ar7240\n  DEVICE_MODEL := WNR1000\n  DEVICE_VARIANT := v2\n  UIMAGE_MAGIC := 0x31303031\n  NETGEAR_BOARD_ID := WNR1000V2\n  NETGEAR_HW_ID := 29763331+4+32\n  IMAGE_SIZE := 3712k\n  SUPPORTED_DEVICES += wnr1000-v2\n  DEFAULT := n\nendef\nTARGET_DEVICES += netgear_wnr1000-v2\n\ndefine Device/netgear_wnr2000-v3\n  $(Device/netgear_generic)\n  SOC := ar7241\n  DEVICE_MODEL := WNR2000\n  DEVICE_VARIANT := v3\n  UIMAGE_MAGIC := 0x32303033\n  NETGEAR_BOARD_ID := WNR2000V3\n  NETGEAR_HW_ID := 29763551+04+32\n  IMAGE_SIZE := 3712k\n  IMAGES += factory-NA.img\n  IMAGE/factory-NA.img := $$(IMAGE/default) | netgear-dni NA | \\\n\tcheck-size\n  SUPPORTED_DEVICES += wnr2000-v3\n  DEFAULT := n\nendef\nTARGET_DEVICES += netgear_wnr2000-v3\n"
  },
  {
    "path": "target/linux/ath79/image/tiny-tp-link.mk",
    "content": "include ./common-tp-link.mk\n\ndefine Device/tplink_tl-mr10u\n  $(Device/tplink-4mlzma)\n  SOC := ar9331\n  DEVICE_MODEL := TL-MR10U\n  DEVICE_PACKAGES := kmod-usb-chipidea2\n  TPLINK_HWID := 0x00100101\n  SUPPORTED_DEVICES += tl-mr10u\nendef\nTARGET_DEVICES += tplink_tl-mr10u\n\ndefine Device/tplink_tl-mr3020-v1\n  $(Device/tplink-4mlzma)\n  IMAGE_SIZE := 3840k\n  SOC := ar9331\n  DEVICE_MODEL := TL-MR3020\n  DEVICE_VARIANT := v1\n  DEVICE_PACKAGES := kmod-usb-chipidea2 kmod-usb-ledtrig-usbport\n  TPLINK_HWID := 0x30200001\n  SUPPORTED_DEVICES += tl-mr3020\nendef\nTARGET_DEVICES += tplink_tl-mr3020-v1\n\ndefine Device/tplink_tl-mr3040-v2\n  $(Device/tplink-4mlzma)\n  SOC := ar9331\n  DEVICE_MODEL := TL-MR3040\n  DEVICE_VARIANT := v2\n  DEVICE_PACKAGES := kmod-usb-chipidea2 kmod-usb-ledtrig-usbport\n  TPLINK_HWID := 0x30400002\n  SUPPORTED_DEVICES += tl-mr3040-v2\nendef\nTARGET_DEVICES += tplink_tl-mr3040-v2\n\ndefine Device/tplink_tl-mr3220-v1\n  $(Device/tplink-4m)\n  SOC := ar7241\n  DEVICE_MODEL := TL-MR3220\n  DEVICE_VARIANT := v1\n  TPLINK_HWID := 0x32200001\n  DEVICE_PACKAGES := kmod-usb2 kmod-usb-ledtrig-usbport\n  SUPPORTED_DEVICES += tl-mr3220\nendef\nTARGET_DEVICES += tplink_tl-mr3220-v1\n\ndefine Device/tplink_tl-mr3420-v1\n  $(Device/tplink-4m)\n  SOC := ar7241\n  DEVICE_MODEL := TL-MR3420\n  DEVICE_VARIANT := v1\n  TPLINK_HWID := 0x34200001\n  DEVICE_PACKAGES := kmod-usb2 kmod-usb-ledtrig-usbport\n  SUPPORTED_DEVICES += tl-mr3420\nendef\nTARGET_DEVICES += tplink_tl-mr3420-v1\n\ndefine Device/tplink_tl-mr3420-v2\n  $(Device/tplink-4mlzma)\n  SOC := ar9341\n  DEVICE_MODEL := TL-MR3420\n  DEVICE_VARIANT := v2\n  TPLINK_HWID := 0x34200002\n  DEVICE_PACKAGES := kmod-usb2 kmod-usb-ledtrig-usbport\n  SUPPORTED_DEVICES += tl-mr3420-v2\nendef\nTARGET_DEVICES += tplink_tl-mr3420-v2\n\ndefine Device/tplink_tl-mr3420-v3\n  $(Device/tplink-4mlzma)\n  SOC := qca9531\n  DEVICE_MODEL := TL-MR3420\n  DEVICE_VARIANT := v3\n  TPLINK_HWID := 0x34200003\n  DEVICE_PACKAGES := kmod-usb2 kmod-usb-ledtrig-usbport\nendef\nTARGET_DEVICES += tplink_tl-mr3420-v3\n\ndefine Device/tplink_tl-wa701nd-v1\n  $(Device/tplink-4m)\n  SOC := ar7240\n  DEVICE_MODEL := TL-WA701ND\n  DEVICE_VARIANT := v1\n  TPLINK_HWID := 0x07010001\n  SUPPORTED_DEVICES += tl-wa901nd\nendef\nTARGET_DEVICES += tplink_tl-wa701nd-v1\n\ndefine Device/tplink_tl-wa730re-v1\n  $(Device/tplink-4m)\n  SOC := ar7240\n  DEVICE_MODEL := TL-WA730RE\n  DEVICE_VARIANT := v1\n  TPLINK_HWID := 0x07300001\n  SUPPORTED_DEVICES += tl-wa901nd\nendef\nTARGET_DEVICES += tplink_tl-wa730re-v1\n\ndefine Device/tplink_tl-wa801nd-v1\n  $(Device/tplink-4m)\n  SOC := ar7240\n  DEVICE_MODEL := TL-WA801ND\n  DEVICE_VARIANT := v1\n  TPLINK_HWID := 0x08010001\n  SUPPORTED_DEVICES += tl-wa901nd\nendef\nTARGET_DEVICES += tplink_tl-wa801nd-v1\n\ndefine Device/tplink_tl-wa801nd-v3\n  $(Device/tplink-4mlzma)\n  SOC := qca9533\n  DEVICE_MODEL := TL-WA801ND\n  DEVICE_VARIANT := v3\n  TPLINK_HWID := 0x08010003\n  SUPPORTED_DEVICES += tl-wa801nd-v3\nendef\nTARGET_DEVICES += tplink_tl-wa801nd-v3\n\ndefine Device/tplink_tl-wa801nd-v4\n  $(Device/tplink-4mlzma)\n  SOC := qca9533\n  DEVICE_MODEL := TL-WA801ND\n  DEVICE_VARIANT := v4\n  TPLINK_HWID := 0x08010004\n  SUPPORTED_DEVICES += tl-wa801nd-v3\nendef\nTARGET_DEVICES += tplink_tl-wa801nd-v4\n\ndefine Device/tplink_tl-wa830re-v1\n  $(Device/tplink-4m)\n  SOC := ar7240\n  DEVICE_MODEL := TL-WA830RE\n  DEVICE_VARIANT := v1\n  TPLINK_HWID := 0x08300010\n  SUPPORTED_DEVICES += tl-wa901nd\nendef\nTARGET_DEVICES += tplink_tl-wa830re-v1\n\ndefine Device/tplink_tl-wa850re-v1\n  $(Device/tplink-4mlzma)\n  SOC := ar9341\n  DEVICE_MODEL := TL-WA850RE\n  DEVICE_VARIANT := v1\n  TPLINK_HWID := 0x08500001\n  DEVICE_PACKAGES := rssileds\n  SUPPORTED_DEVICES += tl-wa850re\nendef\nTARGET_DEVICES += tplink_tl-wa850re-v1\n\ndefine Device/tplink_tl-wa850re-v2\n  $(Device/tplink-safeloader)\n  SOC := qca9533\n  IMAGE_SIZE := 3648k\n  DEVICE_MODEL := TL-WA850RE\n  DEVICE_VARIANT := v2\n  TPLINK_BOARD_ID := TLWA850REV2\n  TPLINK_HWID := 0x08500002\n  DEVICE_PACKAGES := rssileds\n  SUPPORTED_DEVICES += tl-wa850re-v2\n  DEFAULT := n\nendef\nTARGET_DEVICES += tplink_tl-wa850re-v2\n\ndefine Device/tplink_tl-wa860re-v1\n  $(Device/tplink-4mlzma)\n  SOC := ar9341\n  DEVICE_MODEL := TL-WA860RE\n  DEVICE_VARIANT := v1\n  TPLINK_HWID := 0x08600001\n  SUPPORTED_DEVICES += tl-wa860re\nendef\nTARGET_DEVICES += tplink_tl-wa860re-v1\n\ndefine Device/tplink_tl-wa901nd-v1\n  $(Device/tplink-4m)\n  SOC := ar7240\n  DEVICE_MODEL := TL-WA901ND\n  DEVICE_VARIANT := v1\n  TPLINK_HWID := 0x09010001\n  SUPPORTED_DEVICES += tl-wa901nd\nendef\nTARGET_DEVICES += tplink_tl-wa901nd-v1\n\ndefine Device/tplink_tl-wa901nd-v2\n  $(Device/tplink-4m)\n  SOC := ar9132\n  DEVICE_MODEL := TL-WA901ND\n  DEVICE_VARIANT := v2\n  TPLINK_HWID := 0x09010002\n  SUPPORTED_DEVICES += tl-wa901nd-v2\nendef\nTARGET_DEVICES += tplink_tl-wa901nd-v2\n\ndefine Device/tplink_tl-wa901nd-v3\n  $(Device/tplink-4mlzma)\n  SOC := ar9341\n  DEVICE_MODEL := TL-WA901ND\n  DEVICE_VARIANT := v3\n  TPLINK_HWID := 0x09010003\n  SUPPORTED_DEVICES += tl-wa901nd-v3\nendef\nTARGET_DEVICES += tplink_tl-wa901nd-v3\n\ndefine Device/tplink_tl-wa901nd-v4\n  $(Device/tplink-4mlzma)\n  SOC := tp9343\n  DEVICE_MODEL := TL-WA901ND\n  DEVICE_VARIANT := v4\n  TPLINK_HWID := 0x09010004\n  SUPPORTED_DEVICES += tl-wa901nd-v4\n  IMAGE/factory.bin := tplink-v1-image factory -C EU\nendef\nTARGET_DEVICES += tplink_tl-wa901nd-v4\n\ndefine Device/tplink_tl-wa901nd-v5\n  $(Device/tplink-4mlzma)\n  SOC := tp9343\n  DEVICE_MODEL := TL-WA901ND\n  DEVICE_VARIANT := v5\n  TPLINK_HWID := 0x09010005\n  SUPPORTED_DEVICES += tl-wa901nd-v5\n  IMAGE/factory.bin := tplink-v1-image factory -C EU\nendef\nTARGET_DEVICES += tplink_tl-wa901nd-v5\n\ndefine Device/tplink_tl-wpa8630p-v2\n  $(Device/tplink-safeloader)\n  SOC := qca9563\n  DEVICE_MODEL := TL-WPA8630P\n  IMAGE_SIZE := 6016k\n  DEVICE_PACKAGES := kmod-ath10k-ct ath10k-firmware-qca9888-ct\n  DEVICE_COMPAT_VERSION := 2.0\n  DEVICE_COMPAT_MESSAGE := The flash erase blocksize has changed to 4k from the 64k in previous versions, \\\n    so the JFFS2 settings partition MUST be reformatted to avoid data corruption. \\\n    Backup your settings before upgrading, then during sysupgrade, \\\n    de-select \"Keep settings\" and select \"Force\" to continue (equivilant to \"sysupgrade -n -F\").\nendef\n\ndefine Device/tplink_tl-wpa8630p-v2-int\n  $(Device/tplink_tl-wpa8630p-v2)\n  DEVICE_VARIANT := v2 (Int.)\n  TPLINK_BOARD_ID := TL-WPA8630P-V2-INT\nendef\nTARGET_DEVICES += tplink_tl-wpa8630p-v2-int\n\ndefine Device/tplink_tl-wpa8630p-v2.0-eu\n  $(Device/tplink_tl-wpa8630p-v2)\n  DEVICE_VARIANT := v2.0 (EU)\n  TPLINK_BOARD_ID := TL-WPA8630P-V2.0-EU\n  SUPPORTED_DEVICES += tplink,tl-wpa8630p-v2-eu\nendef\nTARGET_DEVICES += tplink_tl-wpa8630p-v2.0-eu\n\ndefine Device/tplink_tl-wpa8630p-v2.1-eu\n  $(Device/tplink_tl-wpa8630p-v2)\n  DEVICE_VARIANT := v2.1 (EU)\n  TPLINK_BOARD_ID := TL-WPA8630P-V2.1-EU\nendef\nTARGET_DEVICES += tplink_tl-wpa8630p-v2.1-eu\n\ndefine Device/tplink_tl-wr703n\n  $(Device/tplink-4mlzma)\n  SOC := ar9331\n  DEVICE_MODEL := TL-WR703N\n  DEVICE_PACKAGES := kmod-usb-chipidea2\n  TPLINK_HWID := 0x07030101\n  SUPPORTED_DEVICES += tl-wr703n\nendef\nTARGET_DEVICES += tplink_tl-wr703n\n\ndefine Device/tplink_tl-wr740n-v1\n  $(Device/tplink-4m)\n  SOC := ar7240\n  DEVICE_MODEL := TL-WR740N\n  DEVICE_VARIANT := v1/v2\n  TPLINK_HWID := 0x07400001\n  SUPPORTED_DEVICES += tl-wr741nd\nendef\nTARGET_DEVICES += tplink_tl-wr740n-v1\n\ndefine Device/tplink_tl-wr740n-v3\n  $(Device/tplink-4m)\n  SOC := ar7240\n  DEVICE_MODEL := TL-WR740N\n  DEVICE_VARIANT := v3\n  TPLINK_HWID := 0x07400003\n  SUPPORTED_DEVICES += tl-wr741nd\nendef\nTARGET_DEVICES += tplink_tl-wr740n-v3\n\ndefine Device/tplink_tl-wr740n-v4\n  $(Device/tplink-4mlzma)\n  SOC := ar9331\n  DEVICE_MODEL := TL-WR740N\n  DEVICE_VARIANT := v4\n  TPLINK_HWID := 0x07400004\n  SUPPORTED_DEVICES += tl-wr741nd-v4\nendef\nTARGET_DEVICES += tplink_tl-wr740n-v4\n\ndefine Device/tplink_tl-wr740n-v5\n  $(Device/tplink-4mlzma)\n  SOC := ar9331\n  DEVICE_MODEL := TL-WR740N\n  DEVICE_VARIANT := v5\n  TPLINK_HWID := 0x07400005\n  SUPPORTED_DEVICES += tl-wr741nd-v4\nendef\nTARGET_DEVICES += tplink_tl-wr740n-v5\n\ndefine Device/tplink_tl-wr741-v1\n  $(Device/tplink-4m)\n  SOC := ar7240\n  DEVICE_MODEL := TL-WR741N/ND\n  DEVICE_VARIANT := v1/v2\n  TPLINK_HWID := 0x07410001\n  SUPPORTED_DEVICES += tl-wr741nd\nendef\nTARGET_DEVICES += tplink_tl-wr741-v1\n\ndefine Device/tplink_tl-wr741nd-v4\n  $(Device/tplink-4mlzma)\n  SOC := ar9331\n  DEVICE_MODEL := TL-WR741N/ND\n  DEVICE_VARIANT := v4\n  TPLINK_HWID := 0x07410004\n  SUPPORTED_DEVICES += tl-wr741nd-v4\nendef\nTARGET_DEVICES += tplink_tl-wr741nd-v4\n\ndefine Device/tplink_tl-wr743nd-v1\n  $(Device/tplink-4m)\n  SOC := ar7240\n  DEVICE_MODEL := TL-WR743ND\n  DEVICE_VARIANT := v1\n  TPLINK_HWID := 0x07430001\n  SUPPORTED_DEVICES += tl-wr741nd\nendef\nTARGET_DEVICES += tplink_tl-wr743nd-v1\n\ndefine Device/tplink_tl-wr802n-v1\n  $(Device/tplink-4mlzma)\n  SOC := qca9533\n  DEVICE_MODEL := TL-WR802N\n  DEVICE_VARIANT := v1\n  TPLINK_HWID := 0x08020001\n  SUPPORTED_DEVICES += tl-wr802n-v1\nendef\nTARGET_DEVICES += tplink_tl-wr802n-v1\n\ndefine Device/tplink_tl-wr802n-v2\n  $(Device/tplink-4mlzma)\n  SOC := qca9533\n  DEVICE_MODEL := TL-WR802N\n  DEVICE_VARIANT := v2\n  TPLINK_HWID := 0x08020002\n  TPLINK_HWREV := 2\n  SUPPORTED_DEVICES += tl-wr802n-v2\n  IMAGES += factory-us.bin factory-eu.bin\n  IMAGE/factory-us.bin := tplink-v1-image factory -C US\n  IMAGE/factory-eu.bin := tplink-v1-image factory -C EU\nendef\nTARGET_DEVICES += tplink_tl-wr802n-v2\n\ndefine Device/tplink_tl-wr841-v5\n  $(Device/tplink-4m)\n  SOC := ar7240\n  DEVICE_MODEL := TL-WR841N/ND\n  DEVICE_VARIANT := v5/v6\n  TPLINK_HWID := 0x08410005\n  SUPPORTED_DEVICES += tl-wr741nd\nendef\nTARGET_DEVICES += tplink_tl-wr841-v5\n\ndefine Device/tplink_tl-wr841-v7\n  $(Device/tplink-4m)\n  SOC := ar7241\n  DEVICE_MODEL := TL-WR841N/ND\n  DEVICE_VARIANT := v7\n  TPLINK_HWID := 0x08410007\n  SUPPORTED_DEVICES += tl-wr841n-v7\nendef\nTARGET_DEVICES += tplink_tl-wr841-v7\n\ndefine Device/tplink_tl-wr841-v8\n  $(Device/tplink-4mlzma)\n  SOC := ar9341\n  DEVICE_MODEL := TL-WR841N/ND\n  DEVICE_VARIANT := v8\n  TPLINK_HWID := 0x08410008\n  SUPPORTED_DEVICES += tl-wr841n-v8\nendef\nTARGET_DEVICES += tplink_tl-wr841-v8\n\ndefine Device/tplink_tl-wr841-v9\n  $(Device/tplink-4mlzma)\n  SOC := qca9533\n  DEVICE_MODEL := TL-WR841N/ND\n  DEVICE_VARIANT := v9\n  TPLINK_HWID := 0x08410009\n  SUPPORTED_DEVICES += tl-wr841n-v9\nendef\nTARGET_DEVICES += tplink_tl-wr841-v9\n\ndefine Device/tplink_tl-wr841-v10\n  $(Device/tplink-4mlzma)\n  SOC := qca9533\n  DEVICE_MODEL := TL-WR841N/ND\n  DEVICE_VARIANT := v10\n  TPLINK_HWID := 0x08410010\n  SUPPORTED_DEVICES += tl-wr841n-v9\nendef\nTARGET_DEVICES += tplink_tl-wr841-v10\n\ndefine Device/tplink_tl-wr841-v11\n  $(Device/tplink-4mlzma)\n  SOC := qca9533\n  DEVICE_MODEL := TL-WR841N/ND\n  DEVICE_VARIANT := v11\n  TPLINK_HWID := 0x08410011\n  SUPPORTED_DEVICES += tl-wr841n-v11\n  IMAGES += factory-us.bin factory-eu.bin\n  IMAGE/factory-us.bin := tplink-v1-image factory -C US\n  IMAGE/factory-eu.bin := tplink-v1-image factory -C EU\nendef\nTARGET_DEVICES += tplink_tl-wr841-v11\n\ndefine Device/tplink_tl-wr841-v12\n  $(Device/tplink-4mlzma)\n  SOC := qca9533\n  DEVICE_MODEL := TL-WR841N/ND\n  DEVICE_VARIANT := v12\n  TPLINK_HWID := 0x08410012\n  SUPPORTED_DEVICES += tl-wr841n-v11\n  IMAGES += factory-us.bin factory-eu.bin\n  IMAGE/factory-us.bin := tplink-v1-image factory -C US\n  IMAGE/factory-eu.bin := tplink-v1-image factory -C EU\nendef\nTARGET_DEVICES += tplink_tl-wr841-v12\n\ndefine Device/tplink_tl-wr940n-v3\n  $(Device/tplink-4mlzma)\n  SOC := tp9343\n  DEVICE_MODEL := TL-WR940N\n  DEVICE_VARIANT := v3\n  TPLINK_HWID := 0x09410006\n  SUPPORTED_DEVICES += tl-wr941nd-v6\nendef\nTARGET_DEVICES += tplink_tl-wr940n-v3\n\ndefine Device/tplink_tl-wr940n-v4\n  $(Device/tplink-4mlzma)\n  SOC := tp9343\n  DEVICE_MODEL := TL-WR940N\n  DEVICE_VARIANT := v4\n  TPLINK_HWID := 0x09400004\n  SUPPORTED_DEVICES += tl-wr940n-v4\n  IMAGES += factory-us.bin factory-eu.bin factory-br.bin\n  IMAGE/factory-us.bin := tplink-v1-image factory -C US\n  IMAGE/factory-eu.bin := tplink-v1-image factory -C EU\n  IMAGE/factory-br.bin := tplink-v1-image factory -C BR\nendef\nTARGET_DEVICES += tplink_tl-wr940n-v4\n\ndefine Device/tplink_tl-wr940n-v6\n  $(Device/tplink-4mlzma)\n  SOC := tp9343\n  DEVICE_MODEL := TL-WR940N\n  DEVICE_VARIANT := v6\n  TPLINK_HWID := 0x09400006\n  SUPPORTED_DEVICES += tl-wr940n-v6\n  IMAGES += factory-us.bin factory-eu.bin factory-br.bin\n  IMAGE/factory-us.bin := tplink-v1-image factory -C US\n  IMAGE/factory-eu.bin := tplink-v1-image factory -C EU\n  IMAGE/factory-br.bin := tplink-v1-image factory -C BR\nendef\nTARGET_DEVICES += tplink_tl-wr940n-v6\n\ndefine Device/tplink_tl-wr941-v2\n  $(Device/tplink-4m)\n  SOC := ar9132\n  DEVICE_MODEL := TL-WR941ND\n  DEVICE_VARIANT := v2/v3\n  DEVICE_ALT0_VENDOR := TP-Link\n  DEVICE_ALT0_MODEL := TL-WR941N\n  DEVICE_ALT0_VARIANT := v2/v3\n  TPLINK_HWID := 0x09410002\n  TPLINK_HWREV := 2\n  SUPPORTED_DEVICES += tl-wr941nd\nendef\nTARGET_DEVICES += tplink_tl-wr941-v2\n\ndefine Device/tplink_tl-wr941-v4\n  $(Device/tplink-4m)\n  SOC := ar7240\n  DEVICE_MODEL := TL-WR941ND\n  DEVICE_VARIANT := v4\n  DEVICE_ALT0_VENDOR := TP-Link\n  DEVICE_ALT0_MODEL := TL-WR941N\n  DEVICE_ALT0_VARIANT := v4\n  TPLINK_HWID := 0x09410004\n  SUPPORTED_DEVICES += tl-wr741nd\nendef\nTARGET_DEVICES += tplink_tl-wr941-v4\n\ndefine Device/tplink_tl-wr941nd-v6\n  $(Device/tplink-4mlzma)\n  SOC := tp9343\n  DEVICE_MODEL := TL-WR941ND\n  DEVICE_VARIANT := v6\n  TPLINK_HWID := 0x09410006\n  SUPPORTED_DEVICES += tl-wr941nd-v6\nendef\nTARGET_DEVICES += tplink_tl-wr941nd-v6\n\ndefine Device/tplink_tl-wr941n-v7-cn\n  $(Device/tplink-4mlzma)\n  SOC := qca9558\n  DEVICE_MODEL := TL-WR941N\n  DEVICE_VARIANT := v7 (CN)\n  TPLINK_HWID := 0x09410007\nendef\nTARGET_DEVICES += tplink_tl-wr941n-v7-cn\n"
  },
  {
    "path": "target/linux/ath79/image/tiny.mk",
    "content": "include ./common-buffalo.mk\ninclude ./common-senao.mk\n\ndefine Device/buffalo_whr-g301n\n  $(Device/buffalo_common)\n  SOC := ar7240\n  DEVICE_MODEL := WHR-G301N\n  BUFFALO_PRODUCT := WHR-G301N\n  IMAGE_SIZE := 3712k\n  SUPPORTED_DEVICES += whr-g301n\n  DEFAULT := n\nendef\nTARGET_DEVICES += buffalo_whr-g301n\n\ndefine Device/dlink_dir-615-e4\n  SOC := ar7240\n  DEVICE_VENDOR := D-Link\n  DEVICE_MODEL := DIR-615\n  DEVICE_VARIANT := E4\n  IMAGE_SIZE := 3776k\n  FACTORY_IMAGE_SIZE := 3456k\n  IMAGES += factory.bin\n  IMAGE/default := append-kernel | append-rootfs | pad-rootfs\n  IMAGE/sysupgrade.bin := $$(IMAGE/default) | check-size | append-metadata\n  IMAGE/factory.bin := $$(IMAGE/default) | \\\n\tcheck-size $$$$(FACTORY_IMAGE_SIZE) | pad-to $$$$(FACTORY_IMAGE_SIZE) | \\\n\tappend-string \"AP99-AR7240-RT-091105-05\"\n  SUPPORTED_DEVICES += dir-615-e4\n  DEFAULT := n\nendef\nTARGET_DEVICES += dlink_dir-615-e4\n\ndefine Device/engenius_eap350-v1\n  $(Device/senao_loader_okli)\n  BLOCKSIZE := 4k\n  SOC := ar7242\n  DEVICE_VENDOR := EnGenius\n  DEVICE_MODEL := EAP350\n  DEVICE_VARIANT := v1\n  IMAGE_SIZE := 4928k\n  LOADER_FLASH_OFFS := 0x1a0000\n  SENAO_IMGNAME := senao-eap350\nendef\nTARGET_DEVICES += engenius_eap350-v1\n\ndefine Device/engenius_ecb350-v1\n  $(Device/senao_loader_okli)\n  BLOCKSIZE := 4k\n  SOC := ar7242\n  DEVICE_VENDOR := EnGenius\n  DEVICE_MODEL := ECB350\n  DEVICE_VARIANT := v1\n  IMAGE_SIZE := 4928k\n  LOADER_FLASH_OFFS := 0x1a0000\n  SENAO_IMGNAME := senao-ecb350\nendef\nTARGET_DEVICES += engenius_ecb350-v1\n\ndefine Device/engenius_enh202-v1\n  $(Device/senao_loader_okli)\n  SOC := ar7240\n  DEVICE_VENDOR := EnGenius\n  DEVICE_MODEL := ENH202\n  DEVICE_VARIANT := v1\n  DEVICE_PACKAGES := rssileds\n  IMAGE_SIZE := 4928k\n  LOADER_FLASH_OFFS := 0x1a0000\n  SENAO_IMGNAME := senao-enh202\nendef\nTARGET_DEVICES += engenius_enh202-v1\n\ndefine Device/pqi_air-pen\n  SOC := ar9330\n  DEVICE_VENDOR := PQI\n  DEVICE_MODEL := Air-Pen\n  DEVICE_PACKAGES := kmod-usb-chipidea2\n  IMAGE_SIZE := 7680k\n  SUPPORTED_DEVICES += pqi-air-pen\nendef\nTARGET_DEVICES += pqi_air-pen\n"
  },
  {
    "path": "target/linux/ath79/mikrotik/base-files/etc/board.d/01_leds",
    "content": "\n. /lib/functions/uci-defaults.sh\n\nboard_config_update\n\nboard=$(board_name)\n\ncase \"$board\" in\nmikrotik,routerboard-lhg-2nd|\\\nmikrotik,routerboard-mapl-2nd|\\\nmikrotik,routerboard-wap-2nd)\n\tucidef_set_led_netdev \"lan\" \"lan\" \"green:lan\" \"eth0\"\n\t;;\nmikrotik,routerboard-lhg-5nd)\n\tucidef_set_led_netdev \"lan\" \"lan\" \"green:lan\" \"eth0\"\n\tucidef_set_rssimon \"wlan0\" \"200000\" \"1\"\n\tucidef_set_led_rssi \"rssilow\" \"rssilow\" \"green:rssilow\" \"wlan0\" \"1\" \"100\"\n\tucidef_set_led_rssi \"rssimediumlow\" \"rssimediumlow\" \"green:rssimediumlow\" \"wlan0\" \"20\" \"100\"\n\tucidef_set_led_rssi \"rssimedium\" \"rssimedium\" \"green:rssimedium\" \"wlan0\" \"40\" \"100\"\n\tucidef_set_led_rssi \"rssimediumhigh\" \"rssimediumhigh\" \"green:rssimediumhigh\" \"wlan0\" \"60\" \"100\"\n\tucidef_set_led_rssi \"rssihigh\" \"rssihigh\" \"green:rssihigh\" \"wlan0\" \"80\" \"100\"\n\t;;\nmikrotik,routerboard-wapr-2nd)\n\tucidef_set_rssimon \"wlan0\" \"200000\" \"1\"\n\tucidef_set_led_rssi \"rssilow\" \"rssilow\" \"green:rssilow\" \"wlan0\" \"1\" \"100\"\n\tucidef_set_led_rssi \"rssimedium\" \"rssimedium\" \"green:rssimedium\" \"wlan0\" \"33\" \"100\"\n\tucidef_set_led_rssi \"rssihigh\" \"rssihigh\" \"green:rssihigh\" \"wlan0\" \"66\" \"100\"\n\t;;\nmikrotik,routerboard-sxt-5nd-r2)\n\tucidef_set_rssimon \"wlan0\" \"200000\" \"1\"\n\tucidef_set_led_rssi \"rssilow\" \"rssilow\" \"green:rssilow\" \"wlan0\" \"1\" \"100\"\n\tucidef_set_led_rssi \"rssimediumlow\" \"rssimediumlow\" \"green:rssimediumlow\" \"wlan0\" \"20\" \"100\"\n\tucidef_set_led_rssi \"rssimedium\" \"rssimedium\" \"green:rssimedium\" \"wlan0\" \"40\" \"100\"\n\tucidef_set_led_rssi \"rssimediumhigh\" \"rssimediumhigh\" \"green:rssimediumhigh\" \"wlan0\" \"60\" \"100\"\n\tucidef_set_led_rssi \"rssihigh\" \"rssihigh\" \"green:rssihigh\" \"wlan0\" \"80\" \"100\"\n\t;;\nesac\n\nboard_config_flush\n\nexit 0\n"
  },
  {
    "path": "target/linux/ath79/mikrotik/base-files/etc/board.d/02_network",
    "content": "\n. /lib/functions/system.sh\n. /lib/functions/uci-defaults.sh\n\nath79_setup_interfaces()\n{\n\tlocal board=\"$1\"\n\n\tcase \"$board\" in\n\tmikrotik,routerboard-493g)\n\t\tucidef_set_interfaces_lan_wan \"eth0.1 eth1.1\" \"eth0.2\"\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0@eth0\" \"1:lan:4\" \"2:lan:1\" \"3:lan:3\" \"4:lan:2\" \"5:wan\"\n\t\tucidef_add_switch \"switch1\" \\\n\t\t\t\"0@eth1\" \"1:lan:4\" \"2:lan:1\" \"3:lan:2\" \"4:lan:3\"\n\t\t;;\n\tmikrotik,routerboard-912uag-2hpnd|\\\n\tmikrotik,routerboard-lhg-2nd|\\\n\tmikrotik,routerboard-lhg-5nd|\\\n\tmikrotik,routerboard-mapl-2nd|\\\n\tmikrotik,routerboard-sxt-5nd-r2|\\\n\tmikrotik,routerboard-wap-2nd|\\\n\tmikrotik,routerboard-wap-g-5hact2hnd|\\\n\tmikrotik,routerboard-wapr-2nd)\n\t\tucidef_set_interface_lan \"eth0\"\n\t\t;;\n\tmikrotik,routerboard-962uigs-5hact2hnt)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0@eth0\" \"2:lan\" \"3:lan\" \"4:lan\" \"5:lan\" \"1:wan\"\n\t\t;;\n\t*)\n\t\tucidef_set_interfaces_lan_wan \"eth0\" \"eth1\"\n\t\t;;\n\tesac\n}\n\nath79_setup_macs()\n{\n\tlocal board=\"$1\"\n\tlocal lan_mac=\"\"\n\tlocal wan_mac=\"\"\n\tlocal label_mac=\"\"\n\tlocal mac_base=\"$(cat /sys/firmware/mikrotik/hard_config/mac_base)\"\n\n\tcase \"$board\" in\n\tmikrotik,routerboard-912uag-2hpnd|\\\n\tmikrotik,routerboard-lhg-2nd|\\\n\tmikrotik,routerboard-lhg-5nd|\\\n\tmikrotik,routerboard-mapl-2nd|\\\n\tmikrotik,routerboard-sxt-5nd-r2|\\\n\tmikrotik,routerboard-wap-2nd|\\\n\tmikrotik,routerboard-wap-g-5hact2hnd|\\\n\tmikrotik,routerboard-wapr-2nd)\n\t\tlabel_mac=\"$mac_base\"\n\t\tlan_mac=\"$mac_base\"\n\t\t;;\n\tmikrotik,routerboard-921gs-5hpacd-15s|\\\n\tmikrotik,routerboard-922uags-5hpacd)\n\t\tlabel_mac=\"$mac_base\"\n\t\tlan_mac=\"$mac_base\"\n\t\twan_mac=$(macaddr_add $mac_base 1)\n\t\t;;\n\t*)\n\t\tlabel_mac=\"$mac_base\"\n\t\twan_mac=\"$mac_base\"\n\t\tlan_mac=$(macaddr_add $mac_base 1)\n\t\t;;\n\tesac\n\n\t[ -n \"$lan_mac\" ] && ucidef_set_interface_macaddr \"lan\" $lan_mac\n\t[ -n \"$wan_mac\" ] && ucidef_set_interface_macaddr \"wan\" $wan_mac\n\t[ -n \"$label_mac\" ] && ucidef_set_label_macaddr $label_mac\n}\n\nboard_config_update\nboard=$(board_name)\nath79_setup_interfaces $board\nath79_setup_macs $board\nboard_config_flush\n\nexit 0\n"
  },
  {
    "path": "target/linux/ath79/mikrotik/base-files/etc/hotplug.d/firmware/10-ath9k-eeprom",
    "content": "#!/bin/sh\n\n[ -e /lib/firmware/$FIRMWARE ] && exit 0\n\n. /lib/functions/caldata.sh\n\ncaldata_mikrotik_ath9k() {\n\tlocal offset=$(($1))\n\tlocal count=$(($2))\n\tlocal macaddr=$3\n\n\tcaldata_from_file $wlan_data $offset $count /tmp/$FIRMWARE\n\tath9k_patch_mac \"$macaddr\" /tmp/$FIRMWARE\n\tcaldata_sysfsload_from_file /tmp/$FIRMWARE 0x0 $count\n\trm -f /tmp/$FIRMWARE\n}\n\nwlan_data=\"/sys/firmware/mikrotik/hard_config/wlan_data\"\nmac_base=\"$(cat /sys/firmware/mikrotik/hard_config/mac_base)\"\n\nboard=$(board_name)\n\ncase \"$FIRMWARE\" in\n\"ath9k-eeprom-ahb-18100000.wmac.bin\")\n\tcase $board in\n\tmikrotik,routerboard-912uag-2hpnd|\\\n\tmikrotik,routerboard-lhg-2nd|\\\n\tmikrotik,routerboard-lhg-5nd|\\\n\tmikrotik,routerboard-sxt-5nd-r2|\\\n\tmikrotik,routerboard-wap-2nd|\\\n\tmikrotik,routerboard-wapr-2nd)\n\t\tcaldata_mikrotik_ath9k 0x1000 0x440 $(macaddr_add \"$mac_base\" 1)\n\t\t;;\n\tmikrotik,routerboard-mapl-2nd|\\\n\tmikrotik,routerboard-wap-g-5hact2hnd)\n\t\tcaldata_mikrotik_ath9k 0x1000 0x440 $(macaddr_add \"$mac_base\" 2)\n\t\t;;\n\tmikrotik,routerboard-962uigs-5hact2hnt)\n\t\tcaldata_mikrotik_ath9k 0x1000 0x440 $(macaddr_add \"$mac_base\" 7)\n\t\t;;\n\t*)\n\t\tcaldata_die \"board $board is not supported yet\"\n\t\t;;\n\tesac\n\t;;\nesac\n"
  },
  {
    "path": "target/linux/ath79/mikrotik/base-files/etc/hotplug.d/firmware/11-ath10k-caldata",
    "content": "#!/bin/sh\n\n[ -e /lib/firmware/$FIRMWARE ] && exit 0\n\n. /lib/functions/caldata.sh\n\nwlan_data=\"/sys/firmware/mikrotik/hard_config/wlan_data\"\n\nboard=$(board_name)\n\ncase \"$FIRMWARE\" in\n\"ath10k/cal-pci-0000:00:00.0.bin\")\n\tcase $board in\n\tmikrotik,routerboard-921gs-5hpacd-15s|\\\n\tmikrotik,routerboard-962uigs-5hact2hnt|\\\n\tmikrotik,routerboard-wap-g-5hact2hnd)\n\t\tcaldata_sysfsload_from_file $wlan_data 0x5000 0x844\n\t\t;;\n\tesac\n\t;;\n\"ath10k/cal-pci-0000:01:00.0.bin\")\n\tcase $board in\n\tmikrotik,routerboard-922uags-5hpacd)\n\t\tcaldata_sysfsload_from_file $wlan_data 0x5000 0x844\n\t\t;;\n\tesac\n\t;;\n*)\n\texit 1\n\t;;\nesac\n"
  },
  {
    "path": "target/linux/ath79/mikrotik/base-files/etc/uci-defaults/04_led_migration",
    "content": ". /lib/functions.sh\n. /lib/functions/migrations.sh\n\nboard=$(board_name)\n\ncase \"$board\" in\nesac\n\nremove_devicename_leds\n\nmigrations_apply system\n\nexit 0\n"
  },
  {
    "path": "target/linux/ath79/mikrotik/base-files/lib/upgrade/platform.sh",
    "content": "# Copyright (C) 2011 OpenWrt.org\n\nPART_NAME=firmware\n\nREQUIRE_IMAGE_METADATA=1\nplatform_check_image() {\n\treturn 0\n}\n\nRAMFS_COPY_BIN='fw_printenv fw_setenv nandwrite'\nRAMFS_COPY_DATA='/etc/fw_env.config /var/lock/fw_printenv.lock'\n\nplatform_do_upgrade_mikrotik_nand() {\n\tCI_KERNPART=none\n\n\tlocal fw_mtd=$(find_mtd_part kernel)\n\tfw_mtd=\"${fw_mtd/block/}\"\n\t[ -n \"$fw_mtd\" ] || return\n\n\tlocal board_dir=$(tar tf \"$1\" | grep -m 1 '^sysupgrade-.*/$')\n\tboard_dir=${board_dir%/}\n\t[ -n \"$board_dir\" ] || return\n\n\tmtd erase kernel\n\ttar xf \"$1\" ${board_dir}/kernel -O | nandwrite -o \"$fw_mtd\" -\n\n\tnand_do_upgrade \"$1\"\n}\n\nplatform_do_upgrade() {\n\tlocal board=$(board_name)\n\n\tcase \"$board\" in\n\tmikrotik,routerboard-493g|\\\n\tmikrotik,routerboard-912uag-2hpnd|\\\n\tmikrotik,routerboard-921gs-5hpacd-15s|\\\n\tmikrotik,routerboard-922uags-5hpacd|\\\n\tmikrotik,routerboard-sxt-5nd-r2)\n\t\tplatform_do_upgrade_mikrotik_nand \"$1\"\n\t\t;;\n\t*)\n\t\t# NOR devices: erase firmware if booted from initramfs\n\t\t[ \"$(rootfs_type)\" = \"tmpfs\" ] && mtd erase firmware\n\n\t\tdefault_do_upgrade \"$1\"\n\t\t;;\n\tesac\n}\n"
  },
  {
    "path": "target/linux/ath79/mikrotik/config-default",
    "content": "CONFIG_CRC16=y\nCONFIG_CRYPTO_DEFLATE=y\nCONFIG_GPIO_LATCH=y\nCONFIG_GPIO_RB91X_KEY=y\nCONFIG_GPIO_RB4XX=y\nCONFIG_GPIO_WATCHDOG=y\nCONFIG_GPIO_WATCHDOG_ARCH_INITCALL=y\nCONFIG_LEDS_RESET=y\nCONFIG_LZO_DECOMPRESS=y\nCONFIG_MDIO_GPIO=y\nCONFIG_MFD_RB4XX_CPLD=y\nCONFIG_MIKROTIK=y\nCONFIG_MIKROTIK_RB_SYSFS=y\nCONFIG_MTD_NAND=y\nCONFIG_MTD_NAND_AR934X=y\nCONFIG_MTD_NAND_CORE=y\nCONFIG_MTD_NAND_ECC=y\nCONFIG_MTD_NAND_ECC_SW_HAMMING=y\nCONFIG_MTD_NAND_RB4XX=y\nCONFIG_MTD_NAND_RB91X=y\nCONFIG_MTD_RAW_NAND=y\nCONFIG_MTD_ROUTERBOOT_PARTS=y\nCONFIG_MTD_SPI_NAND=y\nCONFIG_MTD_SPI_NOR_USE_VARIABLE_ERASE=y\nCONFIG_MTD_SPLIT_MINOR_FW=y\nCONFIG_MTD_UBI=y\nCONFIG_MTD_UBI_BLOCK=y\nCONFIG_MTD_UBI_WL_THRESHOLD=4096\nCONFIG_MTD_UBI_BEB_LIMIT=20\nCONFIG_NET_DSA=y\nCONFIG_NET_SWITCHDEV=y\nCONFIG_PCI_AR71XX=y\nCONFIG_PHY_AR7100_USB=y\nCONFIG_PHY_AR7200_USB=y\nCONFIG_REGULATOR_FIXED_VOLTAGE=y\nCONFIG_SPI_RB4XX=y\nCONFIG_UBIFS_FS=y\nCONFIG_WATCHDOG_CORE=y\nCONFIG_ZLIB_DEFLATE=y\nCONFIG_ZLIB_INFLATE=y\n"
  },
  {
    "path": "target/linux/ath79/mikrotik/target.mk",
    "content": "BOARDNAME := MikroTik devices\nFEATURES += minor nand\nKERNELNAME := vmlinux vmlinuz\nIMAGES_DIR := ../../..\n\nDEFAULT_PACKAGES += wpad-basic-wolfssl\n\nKERNEL_TESTING_PATCHVER:=5.15\n\ndefine Target/Description\n\tBuild firmware images for MikroTik devices based on Qualcomm Atheros\n\tMIPS SoCs (AR71xx, AR72xx, AR91xx, AR93xx, QCA95xx).\nendef\n"
  },
  {
    "path": "target/linux/ath79/modules.mk",
    "content": "LEDS_MENU:=LED modules\n\ndefine KernelPackage/leds-reset\n  SUBMENU:=$(LEDS_MENU)\n  TITLE:=reset controller LED support\n  DEPENDS:= @TARGET_ath79\n  KCONFIG:=CONFIG_LEDS_RESET=m\n  FILES:=$(LINUX_DIR)/drivers/leds/leds-reset.ko\n  AUTOLOAD:=$(call AutoLoad,60,leds-reset,1)\nendef\n\ndefine KernelPackage/leds-reset/description\n Kernel module for LEDs on reset lines\nendef\n\n$(eval $(call KernelPackage,leds-reset))\n"
  },
  {
    "path": "target/linux/ath79/nand/base-files/etc/board.d/01_leds",
    "content": "\n. /lib/functions/uci-defaults.sh\n\nboard_config_update\n\nboard=$(board_name)\n\ncase \"$board\" in\ndongwon,dw02-412h-64m|\\\ndongwon,dw02-412h-128m)\n\tucidef_set_led_switch \"wan\" \"WAN\" \"green:wan\" \"switch0\" \"0x02\"\n\t;;\nglinet,gl-ar300m-nand|\\\nglinet,gl-ar300m-nor)\n\tucidef_set_led_netdev \"lan\" \"LAN\" \"green:lan\" \"eth0\"\n\t;;\nglinet,gl-xe300)\n\tucidef_set_led_netdev \"wan\" \"WAN\" \"green:wan\" \"eth1\"\n\tucidef_set_led_switch \"lan\" \"LAN\" \"green:lan\" \"switch0\" \"0x10\"\n\t;;\nnetgear,r6100)\n\tucidef_set_led_netdev \"wan-green\" \"WAN (green)\" \"green:wan\" \"eth1\"\n\t;;\nnetgear,wndr3700-v4|\\\nnetgear,wndr4300|\\\nnetgear,wndr4300sw|\\\nnetgear,wndr4300-v2|\\\nnetgear,wndr4500-v3)\n\tucidef_set_led_switch \"wan-amber\" \"WAN (amber)\" \"amber:wan\" \"switch0\" \"0x20\"\n\t;;\nesac\n\nboard_config_flush\n\nexit 0\n"
  },
  {
    "path": "target/linux/ath79/nand/base-files/etc/board.d/02_network",
    "content": "\n. /lib/functions/system.sh\n. /lib/functions/uci-defaults.sh\n\nath79_setup_interfaces()\n{\n\tlocal board=\"$1\"\n\n\tcase \"$board\" in\n\taerohive,hiveap-121|\\\n\tglinet,gl-e750)\n\t\tucidef_set_interface_lan \"eth0\"\n\t\t;;\n\tdomywifi,dw33d)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0@eth0\" \"1:wan\" \"2:lan\" \"3:lan\" \"4:lan\" \"5:lan\" \"6@eth1\"\n\t\t;;\n\tdongwon,dw02-412h-64m|\\\n\tdongwon,dw02-412h-128m)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0@eth0\" \"2:lan:4\" \"3:lan:3\" \"4:lan:2\" \"5:lan:1\" \"1:wan\"\n\t\t;;\n\tglinet,gl-ar750s-nor|\\\n\tglinet,gl-ar750s-nor-nand)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0@eth0\" \"2:lan:2\" \"3:lan:1\" \"1:wan\"\n\t\t;;\n\tglinet,gl-xe300)\n\t\tucidef_set_interface_wan \"eth1\"\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0@eth0\" \"4:lan\"\n\t\t;;\n\tnetgear,r6100)\n\t\tucidef_set_interface_wan \"eth1\"\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0@eth0\" \"1:lan:4\" \"2:lan:1\" \"3:lan:2\" \"4:lan:3\"\n\t\t;;\n\tnetgear,wndr3700-v4|\\\n\tnetgear,wndr4300|\\\n\tnetgear,wndr4300sw|\\\n\tnetgear,wndr4300-v2)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0@eth0\" \"1:lan:4\" \"2:lan:3\" \"3:lan:2\" \"4:lan:1\" \"5:wan\"\n\t\t;;\n\tnetgear,wndr4500-v3)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0@eth0\" \"1:lan\" \"2:lan\" \"3:lan\" \"4:lan\" \"5:wan\"\n\t\t;;\n\tnetgear,wndr4300tn)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0@eth0\" \"1:lan:4\" \"2:lan:3\" \"3:lan:2\" \"4:lan:1\"\n\t\t;;\n\tzte,mf286|\\\n\tzte,mf286a|\\\n\tzte,mf286r)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0@eth0\" \"1:lan:4\" \"2:lan:3\" \"3:lan:2\" \"5:lan:1\"\n\t\t;;\n\tzyxel,emg2926-q10a|\\\n\tzyxel,nbg6716)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0@eth0\" \"1:lan\" \"2:lan\" \"3:lan\" \"4:lan\" \"5:wan\" \"6@eth1\"\n\t\t;;\n\t*)\n\t\tucidef_set_interfaces_lan_wan \"eth0\" \"eth1\"\n\t\t;;\n\tesac\n}\n\nath79_setup_macs()\n{\n\tlocal board=\"$1\"\n\n\tcase \"$board\" in\n\tdongwon,dw02-412h-64m|\\\n\tdongwon,dw02-412h-128m)\n\t\twan_mac=$(mtd_get_mac_binary art 0x0)\n\t\tlabel_mac=$wan_mac\n\t\t;;\n\tnetgear,wndr3700-v4|\\\n\tnetgear,wndr4300|\\\n\tnetgear,wndr4300sw|\\\n\tnetgear,wndr4300-v2|\\\n\tnetgear,wndr4500-v3)\n\t\twan_mac=$(mtd_get_mac_binary caldata 0x6)\n\t\t;;\n\tesac\n\n\t[ -n \"$lan_mac\" ] && ucidef_set_interface_macaddr \"lan\" $lan_mac\n\t[ -n \"$wan_mac\" ] && ucidef_set_interface_macaddr \"wan\" $wan_mac\n\t[ -n \"$label_mac\" ] && ucidef_set_label_macaddr $label_mac\n}\n\nboard_config_update\nboard=$(board_name)\nath79_setup_interfaces $board\nath79_setup_macs $board\nboard_config_flush\n\nexit 0\n"
  },
  {
    "path": "target/linux/ath79/nand/base-files/etc/board.d/03_gpio_switches",
    "content": "#\n# Copyright (C) 2022 OpenWrt.org\n#\n\n. /lib/functions/uci-defaults.sh\n\nboard_config_update\n\nboard=$(board_name)\n\ncase \"$board\" in\nzte,mf286a|\\\nzte,mf286r)\n\tucidef_add_gpio_switch \"power_btn_block\" \"Power button blocker\" \"20\" \"0\"\n\t;;\nesac\n\nboard_config_flush\n\nexit 0\n"
  },
  {
    "path": "target/linux/ath79/nand/base-files/etc/hotplug.d/firmware/10-ath9k-eeprom",
    "content": "#!/bin/sh\n\n[ -e /lib/firmware/$FIRMWARE ] && exit 0\n\n. /lib/functions/caldata.sh\n\nboard=$(board_name)\n\ncase \"$FIRMWARE\" in\n\"ath9k-eeprom-ahb-18100000.wmac.bin\")\n\tcase $board in\n\t8dev,rambutan)\n\t\tcaldata_extract \"caldata\" 0x1000 0x800\n\t\t;;\n\tnetgear,wndr3700-v4|\\\n\tnetgear,wndr4300|\\\n\tnetgear,wndr4300sw|\\\n\tnetgear,wndr4300tn|\\\n\tnetgear,wndr4300-v2|\\\n\tnetgear,wndr4500-v3)\n\t\tcaldata_extract \"caldata\" 0x1000 0x440\n\t\t;;\n\t*)\n\t\tcaldata_die \"board $board is not supported yet\"\n\t\t;;\n\tesac\n\t;;\n\"ath9k-eeprom-pci-0000:00:00.0.bin\")\n\tcase $board in\n\tnetgear,wndr3700-v4|\\\n\tnetgear,wndr4300|\\\n\tnetgear,wndr4300sw|\\\n\tnetgear,wndr4300tn|\\\n\tnetgear,wndr4300-v2|\\\n\tnetgear,wndr4500-v3)\n\t\tcaldata_extract \"caldata\" 0x5000 0x440\n\t\t;;\n\t*)\n\t\tcaldata_die \"board $board is not supported yet\"\n\t\t;;\n\tesac\n\t;;\nesac\n"
  },
  {
    "path": "target/linux/ath79/nand/base-files/etc/hotplug.d/firmware/11-ath10k-caldata",
    "content": "#!/bin/sh\n\n[ -e /lib/firmware/$FIRMWARE ] && exit 0\n\n. /lib/functions/caldata.sh\n\nboard=$(board_name)\n\ncase \"$FIRMWARE\" in\n\"ath10k/cal-pci-0000:00:00.0.bin\")\n\tcase $board in\n\tdomywifi,dw33d)\n\t\tcaldata_extract \"art\" 0x5000 0x844\n\t\tath10k_patch_mac $(mtd_get_mac_binary art 0x12)\n\t\t;;\n\tglinet,gl-ar750s-nor|\\\n\tglinet,gl-ar750s-nor-nand)\n\t\tcaldata_extract \"art\" 0x5000 0x844\n\t\tath10k_patch_mac $(macaddr_add $(mtd_get_mac_binary art 0x0) 1)\n\t\t;;\n\tnetgear,r6100)\n\t\tcaldata_extract \"caldata\" 0x5000 0x844\n\t\t;;\n\tzyxel,emg2926-q10a|\\\n\tzyxel,nbg6716)\n\t\tcaldata_extract \"art\" 0x5000 0x844\n\t\tath10k_patch_mac $(macaddr_add $(mtd_get_mac_ascii u-boot-env ethaddr) 1)\n\t\t;;\n\tesac\n\t;;\n*)\n\texit 1\n\t;;\nesac\n"
  },
  {
    "path": "target/linux/ath79/nand/base-files/etc/hotplug.d/ieee80211/10-fix-wifi-mac",
    "content": "[ \"$ACTION\" = \"add\" ] || exit 0\n\nPHYNBR=${DEVPATH##*/phy}\n\n[ -n $PHYNBR ] || exit 0\n\n. /lib/functions.sh\n. /lib/functions/system.sh\n\nboard=$(board_name)\n\ncase $board in\n\tglinet,gl-e750)\n\t\t# Set mac address for 5g device\n\t\t[ \"$PHYNBR\" -eq 0 ] && \\\n\t\t\tmacaddr_add $(mtd_get_mac_binary art 0x0) 2 > /sys${DEVPATH}/macaddress\n\t\t;;\n\tzyxel,emg2926-q10a|\\\n\tzyxel,nbg6716)\n\t\t# Set mac address for 2.4g device\n\t\t[ \"$PHYNBR\" -eq 1 ] && \\\n\t\t\tmtd_get_mac_ascii u-boot-env ethaddr > /sys${DEVPATH}/macaddress\n\t\t;;\nesac\n"
  },
  {
    "path": "target/linux/ath79/nand/base-files/etc/init.d/bootcount",
    "content": "#!/bin/sh /etc/rc.common\n# SPDX-License-Identifier: GPL-2.0-only\n\nSTART=99\n\nboot() {\n\tcase $(board_name) in\n\tglinet,gl-ar300m-nand)\n\t\tfw_setenv bootcount 0\n\t\t;;\n\tesac\n}\n"
  },
  {
    "path": "target/linux/ath79/nand/base-files/etc/uci-defaults/04_led_migration",
    "content": ". /lib/functions.sh\n. /lib/functions/migrations.sh\n\nboard=$(board_name)\n\ncase \"$board\" in\nesac\n\nremove_devicename_leds\n\nmigrations_apply system\n\nexit 0\n"
  },
  {
    "path": "target/linux/ath79/nand/base-files/lib/preinit/10_fix_eth_mac.sh",
    "content": ". /lib/functions.sh\n. /lib/functions/system.sh\n\npreinit_set_mac_address() {\n\tcase $(board_name) in\n\tzyxel,emg2926-q10a|\\\n\tzyxel,nbg6716)\n\t\tethaddr=$(mtd_get_mac_ascii u-boot-env ethaddr)\n\t\tip link set dev eth0 address $(macaddr_add $ethaddr 2)\n\t\tip link set dev eth1 address $(macaddr_add $ethaddr 3)\n\t\t;;\n\tesac\n}\n\nboot_hook_add preinit_main preinit_set_mac_address\n"
  },
  {
    "path": "target/linux/ath79/nand/base-files/lib/upgrade/glinet.sh",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2019 Jeff Kletsky\n#\n\nglinet_using_boot_dev_switch() {\n\tif [ \"$(fw_printenv -n boot_dev 2>/dev/null)\" = \"on\" ] ; then\n\t\t>&2 echo \"NOTE: boot_dev=on; use switch to control boot partition\"\n\t\ttrue\n\telse\n\t\tfalse\n\tfi\n}\n\nglinet_set_next_boot_nand() {\n\tmkdir -p /var/lock\n\t! glinet_using_boot_dev_switch && \\\n\t\tfw_setenv bootcount 0 &&  \\\n\t\t>&2 echo \"Next boot set for NAND\"\n}\n\nglinet_set_next_boot_nor() {\n\tmkdir -p /var/lock\n\t! glinet_using_boot_dev_switch && \\\n\t\tfw_setenv bootcount 3 &&  \\\n\t\t>&2 echo \"Next boot set for NOR\"\n}\n\nglinet_nand_nor_do_upgrade() {\n\tset_next_boot_nand() { glinet_set_next_boot_nand; }\n\tset_next_boot_nor() { glinet_set_next_boot_nor; }\n\tnand_nor_do_upgrade \"$1\"\n}\n\nnand_nor_do_upgrade() {\n\tlocal upgrade_file=\"$1\"\n\n\tlocal pn\n\tlocal found=\"\"\n\tlocal err\n\n\tcase \"$(get_magic_long \"$upgrade_file\")\" in\n\n\t\"27051956\")\t# U-Boot Image Magic\n\n\t\tfor pn in \"nor_${PART_NAME}\" \"$PART_NAME\" ; do\t\t# firmware\n\t\t\tif [ \"$(find_mtd_index \"$pn\")\" ] ; then\n\t\t\t\tPART_NAME=\"$pn\"\n\t\t\t\tfound=\"yes\"\n\t\t\t\tbreak\n\t\t\tfi\n\t\tdone\n\t\tif [ \"$found\" = \"yes\" ] ; then\n\t\t\t>&2 echo \"Running NOR upgrade\"\n\t\t\tdefault_do_upgrade \"$upgrade_file\"\n\t\t\t# At this time, default_do_upgrade() exits on error\n\t\t\ttype set_next_boot_nor >/dev/null && set_next_boot_nor\n\t\telse\n\t\t\t>&2 echo \"ERROR: UPGRADE FAILED: Unable to locate '$PART_NAME' or 'nor_${PART_NAME}'\"\n\t\t\texit 1\n\t\tfi\n\t\t;;\n\n\t*)\t# otherwise a file that nand_do_upgrade can process\n\n\t\tfor pn in \"nand_${CI_KERNPART}\" \"$CI_KERNPART\" ; do\t# kernel\n\t\t\tif [ \"$(find_mtd_index \"$pn\")\" ] ; then\n\t\t\t\tCI_KERNPART=\"$pn\"\n\t\t\t\tbreak\n\t\t\tfi\n\t\tdone\n\t\tfor pn in \"nand_${CI_UBIPART}\" \"$CI_UBIPART\" ; do\t# ubi\n\t\t\tif [ \"$(find_mtd_index \"$pn\")\" ] ; then\n\t\t\t\tCI_UBIPART=\"$pn\"\n\t\t\t\tbreak\n\t\t\tfi\n\t\tdone\n\t\tfor pn in \"nand_${CI_ROOTPART}\" \"$CI_ROOTPART\" ; do\t#rootfs\n\t\t\tif [ \"$(find_mtd_index \"$pn\")\" ] ; then\n\t\t\t\tCI_ROOTPART=\"$pn\"\n\t\t\t\tbreak\n\t\t\tfi\n\t\tdone\n\t\t>&2 echo \"Running NAND upgrade\"\n\t\t# TODO: change order when NAND upgrade offers return\n\t\ttype set_next_boot_nand >/dev/null && set_next_boot_nand\n\t\tnand_do_upgrade \"$upgrade_file\"\n\t\t;;\n\tesac\n}\n"
  },
  {
    "path": "target/linux/ath79/nand/base-files/lib/upgrade/platform.sh",
    "content": "# Copyright (C) 2011 OpenWrt.org\n\nPART_NAME=firmware\n\nREQUIRE_IMAGE_METADATA=1\nplatform_check_image() {\n\treturn 0\n}\n\nRAMFS_COPY_BIN='fw_printenv fw_setenv nandwrite'\nRAMFS_COPY_DATA='/etc/fw_env.config /var/lock/fw_printenv.lock'\n\nplatform_do_upgrade() {\n\tlocal board=$(board_name)\n\n\tcase \"$board\" in\n\tglinet,gl-ar300m-nand|\\\n\tglinet,gl-ar300m-nor)\n\t\tglinet_nand_nor_do_upgrade \"$1\"\n\t\t;;\n\tglinet,gl-ar750s-nor|\\\n\tglinet,gl-ar750s-nor-nand)\n\t\tnand_nor_do_upgrade \"$1\"\n\t\t;;\n\t*)\n\t\tnand_do_upgrade \"$1\"\n\t\t;;\n\tesac\n}\n"
  },
  {
    "path": "target/linux/ath79/nand/config-default",
    "content": "CONFIG_CRC16=y\nCONFIG_CRYPTO_ACOMP2=y\nCONFIG_CRYPTO_DEFLATE=y\nCONFIG_CRYPTO_HASH_INFO=y\nCONFIG_CRYPTO_LZO=y\nCONFIG_LZO_COMPRESS=y\nCONFIG_LZO_DECOMPRESS=y\nCONFIG_MTD_NAND=y\nCONFIG_MTD_NAND_AR934X=y\nCONFIG_MTD_NAND_CORE=y\nCONFIG_MTD_RAW_NAND=y\nCONFIG_MTD_SPI_NAND=y\nCONFIG_MTD_UBI=y\nCONFIG_MTD_UBI_BEB_LIMIT=20\nCONFIG_MTD_UBI_BLOCK=y\nCONFIG_MTD_UBI_WL_THRESHOLD=4096\n# CONFIG_PCI_AR71XX is not set\nCONFIG_PHY_AR7200_USB=y\nCONFIG_POWER_RESET=y\nCONFIG_POWER_RESET_GPIO_RESTART=y\nCONFIG_SGL_ALLOC=y\nCONFIG_UBIFS_FS=y\nCONFIG_ZLIB_DEFLATE=y\nCONFIG_ZLIB_INFLATE=y\n"
  },
  {
    "path": "target/linux/ath79/nand/target.mk",
    "content": "BOARDNAME := Generic devices with NAND flash\n\nFEATURES += nand\n\nDEFAULT_PACKAGES += wpad-basic-wolfssl\n\nKERNEL_TESTING_PATCHVER:=5.15\n\ndefine Target/Description\n\tFirmware for boards using Qualcomm Atheros, MIPS-based SoCs\n\tin the ar72xx and subsequent series, with support for NAND flash\nendef\n"
  },
  {
    "path": "target/linux/ath79/patches-5.10/0003-leds-add-reset-controller-based-driver.patch",
    "content": "From ecbd9c87f073f097d9fe56390353e64e963e866a Mon Sep 17 00:00:00 2001\nFrom: John Crispin <john@phrozen.org>\nDate: Tue, 6 Mar 2018 10:03:03 +0100\nSubject: [PATCH 03/27] leds: add reset-controller based driver\n\nSigned-off-by: John Crispin <john@phrozen.org>\n---\n drivers/leds/Kconfig      |  11 ++++\n drivers/leds/Makefile     |   1 +\n drivers/leds/leds-reset.c | 137 ++++++++++++++++++++++++++++++++++++++++++++++\n 3 files changed, 149 insertions(+)\n create mode 100644 drivers/leds/leds-reset.c\n\n--- a/drivers/leds/Kconfig\n+++ b/drivers/leds/Kconfig\n@@ -929,6 +929,17 @@ config LEDS_ACER_A500\n \t  This option enables support for the Power Button LED of\n \t  Acer Iconia Tab A500.\n \n+config LEDS_RESET\n+\ttristate \"LED support for reset-controller API\"\n+\tdepends on LEDS_CLASS\n+\tdepends on RESET_CONTROLLER\n+\thelp\n+\t  This option enables support for LEDs connected to pins driven by reset\n+\t  controllers. Yes, DNI actual built HW like that.\n+\n+\t  To compile this driver as a module, choose M here: the module\n+\t  will be called leds-reset.\n+\n comment \"LED Triggers\"\n source \"drivers/leds/trigger/Kconfig\"\n \n--- /dev/null\n+++ b/drivers/leds/leds-reset.c\n@@ -0,0 +1,140 @@\n+/*\n+ * Copyright (C) 2018 John Crispin <john@phrozen.org>\n+ *\n+ * This program is free software; you can redistribute it and/or modify\n+ * it under the terms of the GNU General Public License version 2 as\n+ * published by the Free Software Foundation.\n+ *\n+ */\n+#include <linux/err.h>\n+#include <linux/reset.h>\n+#include <linux/kernel.h>\n+#include <linux/leds.h>\n+#include <linux/module.h>\n+#include <linux/of.h>\n+#include <linux/platform_device.h>\n+#include <linux/reset.h>\n+\n+struct reset_led_data {\n+\tstruct led_classdev cdev;\n+\tstruct reset_control *rst;\n+};\n+\n+static inline struct reset_led_data *\n+\t\t\tcdev_to_reset_led_data(struct led_classdev *led_cdev)\n+{\n+\treturn container_of(led_cdev, struct reset_led_data, cdev);\n+}\n+\n+static void reset_led_set(struct led_classdev *led_cdev,\n+\tenum led_brightness value)\n+{\n+\tstruct reset_led_data *led_dat = cdev_to_reset_led_data(led_cdev);\n+\n+\tif (value == LED_OFF)\n+\t\treset_control_assert(led_dat->rst);\n+\telse\n+\t\treset_control_deassert(led_dat->rst);\n+}\n+\n+struct reset_leds_priv {\n+\tint num_leds;\n+\tstruct reset_led_data leds[];\n+};\n+\n+static inline int sizeof_reset_leds_priv(int num_leds)\n+{\n+\treturn sizeof(struct reset_leds_priv) +\n+\t\t(sizeof(struct reset_led_data) * num_leds);\n+}\n+\n+static struct reset_leds_priv *reset_leds_create(struct platform_device *pdev)\n+{\n+\tstruct device *dev = &pdev->dev;\n+\tstruct fwnode_handle *child;\n+\tstruct reset_leds_priv *priv;\n+\tint count, ret;\n+\n+\tcount = device_get_child_node_count(dev);\n+\tif (!count)\n+\t\treturn ERR_PTR(-ENODEV);\n+\n+\tpriv = devm_kzalloc(dev, sizeof_reset_leds_priv(count), GFP_KERNEL);\n+\tif (!priv)\n+\t\treturn ERR_PTR(-ENOMEM);\n+\n+\tdevice_for_each_child_node(dev, child) {\n+\t\tstruct reset_led_data *led = &priv->leds[priv->num_leds];\n+\t\tstruct device_node *np = to_of_node(child);\n+\n+\t\tret = fwnode_property_read_string(child, \"label\", &led->cdev.name);\n+\t\tif (!led->cdev.name) {\n+\t\t\tfwnode_handle_put(child);\n+\t\t\treturn ERR_PTR(-EINVAL);\n+\t\t}\n+\t\tled->rst = __of_reset_control_get(np, NULL, 0, 0, 0, true);\n+\t\tif (IS_ERR(led->rst))\n+\t\t\treturn ERR_PTR(-EINVAL);\n+\n+\t\tfwnode_property_read_string(child, \"linux,default-trigger\",\n+\t\t\t\t\t\t&led->cdev.default_trigger);\n+\n+\t\tled->cdev.brightness_set = reset_led_set;\n+\t\tret = devm_led_classdev_register(&pdev->dev, &led->cdev);\n+\t\tif (ret < 0)\n+\t\t\treturn ERR_PTR(ret);\n+\t\tled->cdev.dev->of_node = np;\n+\t\tpriv->num_leds++;\n+\t}\n+\n+\treturn priv;\n+}\n+\n+static const struct of_device_id of_reset_leds_match[] = {\n+\t{ .compatible = \"reset-leds\", },\n+\t{},\n+};\n+\n+MODULE_DEVICE_TABLE(of, of_reset_leds_match);\n+\n+static int reset_led_probe(struct platform_device *pdev)\n+{\n+\tstruct reset_leds_priv *priv;\n+\n+\tpriv = reset_leds_create(pdev);\n+\tif (IS_ERR(priv))\n+\t\treturn PTR_ERR(priv);\n+\n+\tplatform_set_drvdata(pdev, priv);\n+\n+\treturn 0;\n+}\n+\n+static void reset_led_shutdown(struct platform_device *pdev)\n+{\n+\tstruct reset_leds_priv *priv = platform_get_drvdata(pdev);\n+\tint i;\n+\n+\tfor (i = 0; i < priv->num_leds; i++) {\n+\t\tstruct reset_led_data *led = &priv->leds[i];\n+\n+\t\tif (!(led->cdev.flags & LED_RETAIN_AT_SHUTDOWN))\n+\t\t\treset_led_set(&led->cdev, LED_OFF);\n+\t}\n+}\n+\n+static struct platform_driver reset_led_driver = {\n+\t.probe\t\t= reset_led_probe,\n+\t.shutdown\t= reset_led_shutdown,\n+\t.driver\t\t= {\n+\t\t.name\t= \"leds-reset\",\n+\t\t.of_match_table = of_reset_leds_match,\n+\t},\n+};\n+\n+module_platform_driver(reset_led_driver);\n+\n+MODULE_AUTHOR(\"John Crispin <john@phrozen.org>\");\n+MODULE_DESCRIPTION(\"reset controller LED driver\");\n+MODULE_LICENSE(\"GPL\");\n+MODULE_ALIAS(\"platform:leds-reset\");\n--- a/drivers/leds/Makefile\n+++ b/drivers/leds/Makefile\n@@ -93,6 +93,7 @@ obj-$(CONFIG_LEDS_TURRIS_OMNIA)\t\t+= leds\n obj-$(CONFIG_LEDS_WM831X_STATUS)\t+= leds-wm831x-status.o\n obj-$(CONFIG_LEDS_WM8350)\t\t+= leds-wm8350.o\n obj-$(CONFIG_LEDS_WRAP)\t\t\t+= leds-wrap.o\n+obj-$(CONFIG_LEDS_RESET)\t\t+= leds-reset.o\n \n # LED SPI Drivers\n obj-$(CONFIG_LEDS_CR0014114)\t\t+= leds-cr0014114.o\n"
  },
  {
    "path": "target/linux/ath79/patches-5.10/0004-phy-add-ath79-usb-phys.patch",
    "content": "From 08c9d6ceef01893678a5d2e8a15517c745417f21 Mon Sep 17 00:00:00 2001\nFrom: John Crispin <john@phrozen.org>\nDate: Tue, 6 Mar 2018 10:04:05 +0100\nSubject: [PATCH 04/27] phy: add ath79 usb phys\n\nSigned-off-by: John Crispin <john@phrozen.org>\n---\n drivers/phy/Kconfig          |  16 ++++++\n drivers/phy/Makefile         |   2 +\n drivers/phy/phy-ar7100-usb.c | 124 +++++++++++++++++++++++++++++++++++++++++++\n drivers/phy/phy-ar7200-usb.c | 108 +++++++++++++++++++++++++++++++++++++\n 4 files changed, 250 insertions(+)\n create mode 100644 drivers/phy/phy-ar7100-usb.c\n create mode 100644 drivers/phy/phy-ar7200-usb.c\n\n--- a/drivers/phy/Kconfig\n+++ b/drivers/phy/Kconfig\n@@ -24,6 +24,22 @@ config GENERIC_PHY_MIPI_DPHY\n \t  Provides a number of helpers a core functions for MIPI D-PHY\n \t  drivers to us.\n \n+config PHY_AR7100_USB\n+\ttristate \"Atheros AR7100 USB PHY driver\"\n+\tdepends on ATH79 || COMPILE_TEST\n+\tdefault y if USB_EHCI_HCD_PLATFORM\n+\tselect GENERIC_PHY\n+\thelp\n+\t  Enable this to support the USB PHY on Atheros AR7100 SoCs.\n+\n+config PHY_AR7200_USB\n+\ttristate \"Atheros AR7200 USB PHY driver\"\n+\tdepends on ATH79 || COMPILE_TEST\n+\tdefault y if USB_EHCI_HCD_PLATFORM\n+\tselect GENERIC_PHY\n+\thelp\n+\t  Enable this to support the USB PHY on Atheros AR7200 SoCs.\n+\n config PHY_LPC18XX_USB_OTG\n \ttristate \"NXP LPC18xx/43xx SoC USB OTG PHY driver\"\n \tdepends on OF && (ARCH_LPC18XX || COMPILE_TEST)\n--- a/drivers/phy/Makefile\n+++ b/drivers/phy/Makefile\n@@ -4,6 +4,8 @@\n #\n \n obj-$(CONFIG_GENERIC_PHY)\t\t+= phy-core.o\n+obj-$(CONFIG_PHY_AR7100_USB)\t\t+= phy-ar7100-usb.o\n+obj-$(CONFIG_PHY_AR7200_USB)\t\t+= phy-ar7200-usb.o\n obj-$(CONFIG_GENERIC_PHY_MIPI_DPHY)\t+= phy-core-mipi-dphy.o\n obj-$(CONFIG_PHY_LPC18XX_USB_OTG)\t+= phy-lpc18xx-usb-otg.o\n obj-$(CONFIG_PHY_XGENE)\t\t\t+= phy-xgene.o\n--- /dev/null\n+++ b/drivers/phy/phy-ar7100-usb.c\n@@ -0,0 +1,140 @@\n+/*\n+ * Copyright (C) 2018 John Crispin <john@phrozen.org>\n+ *\n+ * This program is free software; you can redistribute it and/or modify\n+ * it under the terms of the GNU General Public License as published by\n+ * the Free Software Foundation; either version 2 of the License, or\n+ * (at your option) any later version.\n+ */\n+\n+#include <linux/module.h>\n+#include <linux/platform_device.h>\n+#include <linux/phy/phy.h>\n+#include <linux/delay.h>\n+#include <linux/reset.h>\n+#include <linux/of_gpio.h>\n+\n+#include <asm/mach-ath79/ath79.h>\n+#include <asm/mach-ath79/ar71xx_regs.h>\n+\n+struct ar7100_usb_phy {\n+\tstruct reset_control\t*rst_phy;\n+\tstruct reset_control\t*rst_host;\n+\tstruct reset_control\t*rst_ohci_dll;\n+\tvoid __iomem\t\t*io_base;\n+\tstruct phy\t\t*phy;\n+\tint\t\t\tgpio;\n+};\n+\n+static int ar7100_usb_phy_power_off(struct phy *phy)\n+{\n+\tstruct ar7100_usb_phy *priv = phy_get_drvdata(phy);\n+\tint err = 0;\n+\n+\terr |= reset_control_assert(priv->rst_host);\n+\terr |= reset_control_assert(priv->rst_phy);\n+\terr |= reset_control_assert(priv->rst_ohci_dll);\n+\n+\treturn err;\n+}\n+\n+static int ar7100_usb_phy_power_on(struct phy *phy)\n+{\n+\tstruct ar7100_usb_phy *priv = phy_get_drvdata(phy);\n+\tint err = 0;\n+\n+\terr |= ar7100_usb_phy_power_off(phy);\n+\tmdelay(100);\n+\terr |= reset_control_deassert(priv->rst_ohci_dll);\n+\terr |= reset_control_deassert(priv->rst_phy);\n+\terr |= reset_control_deassert(priv->rst_host);\n+\tmdelay(500);\n+\tiowrite32(0xf0000, priv->io_base + AR71XX_USB_CTRL_REG_CONFIG);\n+\tiowrite32(0x20c00, priv->io_base + AR71XX_USB_CTRL_REG_FLADJ);\n+\n+\treturn err;\n+}\n+\n+static const struct phy_ops ar7100_usb_phy_ops = {\n+\t.power_on\t= ar7100_usb_phy_power_on,\n+\t.power_off\t= ar7100_usb_phy_power_off,\n+\t.owner\t\t= THIS_MODULE,\n+};\n+\n+static int ar7100_usb_phy_probe(struct platform_device *pdev)\n+{\n+\tstruct phy_provider *phy_provider;\n+\tstruct resource *res;\n+\tstruct ar7100_usb_phy *priv;\n+\n+\tpriv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);\n+\tif (!priv)\n+\t\treturn -ENOMEM;\n+\n+\tres = platform_get_resource(pdev, IORESOURCE_MEM, 0);\n+\tpriv->io_base = devm_ioremap_resource(&pdev->dev, res);\n+\tif (IS_ERR(priv->io_base))\n+\t\treturn PTR_ERR(priv->io_base);\n+\n+\tpriv->rst_phy = devm_reset_control_get(&pdev->dev, \"usb-phy\");\n+\tif (IS_ERR(priv->rst_phy)) {\n+\t\tdev_err(&pdev->dev, \"phy reset is missing\\n\");\n+\t\treturn PTR_ERR(priv->rst_phy);\n+\t}\n+\n+\tpriv->rst_host = devm_reset_control_get(&pdev->dev, \"usb-host\");\n+\tif (IS_ERR(priv->rst_host)) {\n+\t\tdev_err(&pdev->dev, \"host reset is missing\\n\");\n+\t\treturn PTR_ERR(priv->rst_host);\n+\t}\n+\n+\tpriv->rst_ohci_dll = devm_reset_control_get(&pdev->dev, \"usb-ohci-dll\");\n+\tif (IS_ERR(priv->rst_ohci_dll)) {\n+\t\tdev_err(&pdev->dev, \"ohci-dll reset is missing\\n\");\n+\t\treturn PTR_ERR(priv->rst_host);\n+\t}\n+\n+\tpriv->phy = devm_phy_create(&pdev->dev, NULL, &ar7100_usb_phy_ops);\n+\tif (IS_ERR(priv->phy)) {\n+\t\tdev_err(&pdev->dev, \"failed to create PHY\\n\");\n+\t\treturn PTR_ERR(priv->phy);\n+\t}\n+\n+\tpriv->gpio = of_get_gpio(pdev->dev.of_node, 0);\n+\tif (priv->gpio >= 0) {\n+\t\tint ret = devm_gpio_request(&pdev->dev, priv->gpio, dev_name(&pdev->dev));\n+\n+\t\tif (ret) {\n+\t\t\tdev_err(&pdev->dev, \"failed to request gpio\\n\");\n+\t\t\treturn ret;\n+\t\t}\n+\t\tgpio_export_with_name(priv->gpio, 0, dev_name(&pdev->dev));\n+\t\tgpio_set_value(priv->gpio, 1);\n+\t}\n+\n+\tphy_set_drvdata(priv->phy, priv);\n+\n+\tphy_provider = devm_of_phy_provider_register(&pdev->dev, of_phy_simple_xlate);\n+\n+\n+\treturn PTR_ERR_OR_ZERO(phy_provider);\n+}\n+\n+static const struct of_device_id ar7100_usb_phy_of_match[] = {\n+\t{ .compatible = \"qca,ar7100-usb-phy\" },\n+\t{}\n+};\n+MODULE_DEVICE_TABLE(of, ar7100_usb_phy_of_match);\n+\n+static struct platform_driver ar7100_usb_phy_driver = {\n+\t.probe\t= ar7100_usb_phy_probe,\n+\t.driver = {\n+\t\t.of_match_table\t= ar7100_usb_phy_of_match,\n+\t\t.name\t\t= \"ar7100-usb-phy\",\n+\t}\n+};\n+module_platform_driver(ar7100_usb_phy_driver);\n+\n+MODULE_DESCRIPTION(\"ATH79 USB PHY driver\");\n+MODULE_AUTHOR(\"Alban Bedel <albeu@free.fr>\");\n+MODULE_LICENSE(\"GPL\");\n--- /dev/null\n+++ b/drivers/phy/phy-ar7200-usb.c\n@@ -0,0 +1,136 @@\n+/*\n+ * Copyright (C) 2015 Alban Bedel <albeu@free.fr>\n+ *\n+ * This program is free software; you can redistribute it and/or modify\n+ * it under the terms of the GNU General Public License as published by\n+ * the Free Software Foundation; either version 2 of the License, or\n+ * (at your option) any later version.\n+ */\n+\n+#include <linux/module.h>\n+#include <linux/platform_device.h>\n+#include <linux/phy/phy.h>\n+#include <linux/reset.h>\n+#include <linux/of_gpio.h>\n+\n+struct ar7200_usb_phy {\n+\tstruct reset_control\t*rst_phy;\n+\tstruct reset_control\t*rst_phy_analog;\n+\tstruct reset_control\t*suspend_override;\n+\tstruct phy\t\t*phy;\n+\tint\t\t\tgpio;\n+};\n+\n+static int ar7200_usb_phy_power_on(struct phy *phy)\n+{\n+\tstruct ar7200_usb_phy *priv = phy_get_drvdata(phy);\n+\tint err = 0;\n+\n+\tif (priv->suspend_override)\n+\t\terr = reset_control_assert(priv->suspend_override);\n+\tif (priv->rst_phy)\n+\t\terr |= reset_control_deassert(priv->rst_phy);\n+\tif (priv->rst_phy_analog)\n+\t\terr |= reset_control_deassert(priv->rst_phy_analog);\n+\n+\treturn err;\n+}\n+\n+static int ar7200_usb_phy_power_off(struct phy *phy)\n+{\n+\tstruct ar7200_usb_phy *priv = phy_get_drvdata(phy);\n+\tint err = 0;\n+\n+\tif (priv->suspend_override)\n+\t\terr = reset_control_deassert(priv->suspend_override);\n+\tif (priv->rst_phy)\n+\t\terr |= reset_control_assert(priv->rst_phy);\n+\tif (priv->rst_phy_analog)\n+\t\terr |= reset_control_assert(priv->rst_phy_analog);\n+\n+\treturn err;\n+}\n+\n+static const struct phy_ops ar7200_usb_phy_ops = {\n+\t.power_on\t= ar7200_usb_phy_power_on,\n+\t.power_off\t= ar7200_usb_phy_power_off,\n+\t.owner\t\t= THIS_MODULE,\n+};\n+\n+static int ar7200_usb_phy_probe(struct platform_device *pdev)\n+{\n+\tstruct phy_provider *phy_provider;\n+\tstruct ar7200_usb_phy *priv;\n+\n+\tpriv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);\n+\tif (!priv)\n+\t\treturn -ENOMEM;\n+\n+\tpriv->rst_phy = devm_reset_control_get(&pdev->dev, \"usb-phy\");\n+\tif (IS_ERR(priv->rst_phy)) {\n+\t\tif (PTR_ERR(priv->rst_phy) != -EPROBE_DEFER)\n+\t\t\tdev_err(&pdev->dev, \"phy reset is missing\\n\");\n+\t\treturn PTR_ERR(priv->rst_phy);\n+\t}\n+\n+\tpriv->rst_phy_analog = devm_reset_control_get_optional(\n+\t\t&pdev->dev, \"usb-phy-analog\");\n+\tif (IS_ERR(priv->rst_phy_analog)) {\n+\t\tif (PTR_ERR(priv->rst_phy_analog) == -ENOENT)\n+\t\t\tpriv->rst_phy_analog = NULL;\n+\t\telse\n+\t\t\treturn PTR_ERR(priv->rst_phy_analog);\n+\t}\n+\n+\tpriv->suspend_override = devm_reset_control_get_optional(\n+\t\t&pdev->dev, \"usb-suspend-override\");\n+\tif (IS_ERR(priv->suspend_override)) {\n+\t\tif (PTR_ERR(priv->suspend_override) == -ENOENT)\n+\t\t\tpriv->suspend_override = NULL;\n+\t\telse\n+\t\t\treturn PTR_ERR(priv->suspend_override);\n+\t}\n+\n+\tpriv->phy = devm_phy_create(&pdev->dev, NULL, &ar7200_usb_phy_ops);\n+\tif (IS_ERR(priv->phy)) {\n+\t\tdev_err(&pdev->dev, \"failed to create PHY\\n\");\n+\t\treturn PTR_ERR(priv->phy);\n+\t}\n+\n+\tpriv->gpio = of_get_gpio(pdev->dev.of_node, 0);\n+\tif (priv->gpio >= 0) {\n+\t\tint ret = devm_gpio_request(&pdev->dev, priv->gpio, dev_name(&pdev->dev));\n+\n+\t\tif (ret) {\n+\t\t\tdev_err(&pdev->dev, \"failed to request gpio\\n\");\n+\t\t\treturn ret;\n+\t\t}\n+\t\tgpio_export_with_name(priv->gpio, 0, dev_name(&pdev->dev));\n+\t\tgpio_set_value(priv->gpio, 1);\n+\t}\n+\n+\tphy_set_drvdata(priv->phy, priv);\n+\n+\tphy_provider = devm_of_phy_provider_register(&pdev->dev, of_phy_simple_xlate);\n+\n+\treturn PTR_ERR_OR_ZERO(phy_provider);\n+}\n+\n+static const struct of_device_id ar7200_usb_phy_of_match[] = {\n+\t{ .compatible = \"qca,ar7200-usb-phy\" },\n+\t{}\n+};\n+MODULE_DEVICE_TABLE(of, ar7200_usb_phy_of_match);\n+\n+static struct platform_driver ar7200_usb_phy_driver = {\n+\t.probe\t= ar7200_usb_phy_probe,\n+\t.driver = {\n+\t\t.of_match_table\t= ar7200_usb_phy_of_match,\n+\t\t.name\t\t= \"ar7200-usb-phy\",\n+\t}\n+};\n+module_platform_driver(ar7200_usb_phy_driver);\n+\n+MODULE_DESCRIPTION(\"ATH79 USB PHY driver\");\n+MODULE_AUTHOR(\"Alban Bedel <albeu@free.fr>\");\n+MODULE_LICENSE(\"GPL\");\n"
  },
  {
    "path": "target/linux/ath79/patches-5.10/0005-usb-add-more-OF-quirk-properties.patch",
    "content": "From 2201818e5bd33f389beceb3943fdfcf5a698fc5b Mon Sep 17 00:00:00 2001\nFrom: John Crispin <john@phrozen.org>\nDate: Tue, 6 Mar 2018 10:01:43 +0100\nSubject: [PATCH 05/27] usb: add more OF/quirk properties\n\nSigned-off-by: John Crispin <john@phrozen.org>\n---\n drivers/usb/host/ehci-platform.c | 5 +++++\n 1 file changed, 5 insertions(+)\n\n--- a/drivers/usb/host/ehci-platform.c\n+++ b/drivers/usb/host/ehci-platform.c\n@@ -277,6 +277,11 @@ static int ehci_platform_probe(struct pl\n \tehci = hcd_to_ehci(hcd);\n \n \tif (pdata == &ehci_platform_defaults && dev->dev.of_node) {\n+\t\tof_property_read_u32(dev->dev.of_node, \"caps-offset\", &pdata->caps_offset);\n+\n+\t\tif (of_property_read_bool(dev->dev.of_node, \"has-synopsys-hc-bug\"))\n+\t\t\tpdata->has_synopsys_hc_bug = 1;\n+\n \t\tif (of_property_read_bool(dev->dev.of_node, \"big-endian-regs\"))\n \t\t\tehci->big_endian_mmio = 1;\n \n"
  },
  {
    "path": "target/linux/ath79/patches-5.10/0007-irqchip-irq-ath79-intc-add-irq-cascade-driver-for-QC.patch",
    "content": "From f3eacff2310a60348a755c50a8da6fc251fc8587 Mon Sep 17 00:00:00 2001\nFrom: John Crispin <john@phrozen.org>\nDate: Tue, 6 Mar 2018 09:55:13 +0100\nSubject: [PATCH 07/33] irqchip/irq-ath79-intc: add irq cascade driver for\n QCA9556 SoCs\n\nSigned-off-by: John Crispin <john@phrozen.org>\n---\n drivers/irqchip/Makefile         |   1 +\n drivers/irqchip/irq-ath79-intc.c | 142 +++++++++++++++++++++++++++++++++++++++\n 2 files changed, 143 insertions(+)\n create mode 100644 drivers/irqchip/irq-ath79-intc.c\n\n--- a/drivers/irqchip/Makefile\n+++ b/drivers/irqchip/Makefile\n@@ -4,6 +4,7 @@ obj-$(CONFIG_IRQCHIP)\t\t\t+= irqchip.o\n obj-$(CONFIG_AL_FIC)\t\t\t+= irq-al-fic.o\n obj-$(CONFIG_ALPINE_MSI)\t\t+= irq-alpine-msi.o\n obj-$(CONFIG_ATH79)\t\t\t+= irq-ath79-cpu.o\n+obj-$(CONFIG_ATH79)\t\t\t+= irq-ath79-intc.o\n obj-$(CONFIG_ATH79)\t\t\t+= irq-ath79-misc.o\n obj-$(CONFIG_ARCH_BCM2835)\t\t+= irq-bcm2835.o\n obj-$(CONFIG_ARCH_BCM2835)\t\t+= irq-bcm2836.o\n--- /dev/null\n+++ b/drivers/irqchip/irq-ath79-intc.c\n@@ -0,0 +1,142 @@\n+/*\n+ *  Atheros AR71xx/AR724x/AR913x specific interrupt handling\n+ *\n+ *  Copyright (C) 2018 John Crispin <john@phrozen.org>\n+ *\n+ *  This program is free software; you can redistribute it and/or modify it\n+ *  under the terms of the GNU General Public License version 2 as published\n+ *  by the Free Software Foundation.\n+ */\n+\n+#include <linux/interrupt.h>\n+#include <linux/irqchip.h>\n+#include <linux/of.h>\n+#include <linux/of_irq.h>\n+#include <linux/irqdomain.h>\n+\n+#include <asm/irq_cpu.h>\n+#include <asm/mach-ath79/ath79.h>\n+#include <asm/mach-ath79/ar71xx_regs.h>\n+\n+#define ATH79_MAX_INTC_CASCADE\t3\n+\n+struct ath79_intc {\n+\tstruct irq_chip chip;\n+\tu32 irq;\n+\tu32 pending_mask;\n+\tu32 int_status;\n+\tu32 irq_mask[ATH79_MAX_INTC_CASCADE];\n+\tu32 irq_wb_chan[ATH79_MAX_INTC_CASCADE];\n+};\n+\n+static void ath79_intc_irq_handler(struct irq_desc *desc)\n+{\n+\tstruct irq_domain *domain = irq_desc_get_handler_data(desc);\n+\tstruct ath79_intc *intc = domain->host_data;\n+\tu32 pending;\n+\n+\tpending = ath79_reset_rr(intc->int_status);\n+\tpending &= intc->pending_mask;\n+\n+\tif (pending) {\n+\t\tint i;\n+\n+\t\tfor (i = 0; i < domain->hwirq_max; i++)\n+\t\t\tif (pending & intc->irq_mask[i]) {\n+\t\t\t\tif (intc->irq_wb_chan[i] != 0xffffffff)\n+\t\t\t\t\tath79_ddr_wb_flush(intc->irq_wb_chan[i]);\n+\t\t\t\tgeneric_handle_irq(irq_find_mapping(domain, i));\n+\t\t\t}\n+\t} else {\n+\t\tspurious_interrupt();\n+\t}\n+}\n+\n+static void ath79_intc_irq_enable(struct irq_data *d)\n+{\n+\tstruct ath79_intc *intc = d->domain->host_data;\n+\tenable_irq(intc->irq);\n+}\n+\n+static void ath79_intc_irq_disable(struct irq_data *d)\n+{\n+\tstruct ath79_intc *intc = d->domain->host_data;\n+\tdisable_irq(intc->irq);\n+}\n+\n+static int ath79_intc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)\n+{\n+\tstruct ath79_intc *intc = d->host_data;\n+\n+\tirq_set_chip_and_handler(irq, &intc->chip, handle_level_irq);\n+\n+\treturn 0;\n+}\n+\n+static const struct irq_domain_ops ath79_irq_domain_ops = {\n+\t.xlate = irq_domain_xlate_onecell,\n+\t.map = ath79_intc_map,\n+};\n+\n+static int __init ath79_intc_of_init(\n+\tstruct device_node *node, struct device_node *parent)\n+{\n+\tstruct irq_domain *domain;\n+\tstruct ath79_intc *intc;\n+\tint cnt, cntwb, i, err;\n+\n+\tcnt = of_property_count_u32_elems(node, \"qca,pending-bits\");\n+\tif (cnt > ATH79_MAX_INTC_CASCADE)\n+\t\tpanic(\"Too many INTC pending bits\\n\");\n+\n+\tintc = kzalloc(sizeof(*intc), GFP_KERNEL);\n+\tif (!intc)\n+\t\tpanic(\"Failed to allocate INTC memory\\n\");\n+\tintc->chip = dummy_irq_chip;\n+\tintc->chip.name = \"INTC\";\n+\tintc->chip.irq_disable = ath79_intc_irq_disable;\n+\tintc->chip.irq_enable = ath79_intc_irq_enable;\n+\n+\tif (of_property_read_u32(node, \"qca,int-status-addr\", &intc->int_status) < 0) {\n+\t\tpanic(\"Missing address of interrupt status register\\n\");\n+\t}\n+\n+\tof_property_read_u32_array(node, \"qca,pending-bits\", intc->irq_mask, cnt);\n+\tfor (i = 0; i < cnt; i++) {\n+\t\tintc->pending_mask |= intc->irq_mask[i];\n+\t\tintc->irq_wb_chan[i] = 0xffffffff;\n+\t}\n+\n+\tcntwb = of_count_phandle_with_args(\n+\t\tnode, \"qca,ddr-wb-channels\", \"#qca,ddr-wb-channel-cells\");\n+\n+\tfor (i = 0; i < cntwb; i++) {\n+\t\tstruct of_phandle_args args;\n+\t\tu32 irq = i;\n+\n+\t\tof_property_read_u32_index(\n+\t\t\tnode, \"qca,ddr-wb-channel-interrupts\", i, &irq);\n+\t\tif (irq >= ATH79_MAX_INTC_CASCADE)\n+\t\t\tcontinue;\n+\n+\t\terr = of_parse_phandle_with_args(\n+\t\t\tnode, \"qca,ddr-wb-channels\",\n+\t\t\t\"#qca,ddr-wb-channel-cells\",\n+\t\t\ti, &args);\n+\t\tif (err)\n+\t\t\treturn err;\n+\n+\t\tintc->irq_wb_chan[irq] = args.args[0];\n+\t}\n+\n+\tintc->irq = irq_of_parse_and_map(node, 0);\n+\tif (!intc->irq)\n+\t\tpanic(\"Failed to get INTC IRQ\");\n+\n+\tdomain = irq_domain_add_linear(node, cnt, &ath79_irq_domain_ops, intc);\n+\tirq_set_chained_handler_and_data(intc->irq, ath79_intc_irq_handler, domain);\n+\n+\treturn 0;\n+}\n+IRQCHIP_DECLARE(ath79_intc, \"qca,ar9340-intc\",\n+\t\tath79_intc_of_init);\n"
  },
  {
    "path": "target/linux/ath79/patches-5.10/0008-irqchip-irq-ath79-cpu-drop-OF-init-helper.patch",
    "content": "From e029f998594f151008ecbfa024e2957edd2a5189 Mon Sep 17 00:00:00 2001\nFrom: John Crispin <john@phrozen.org>\nDate: Tue, 6 Mar 2018 09:58:19 +0100\nSubject: [PATCH 08/33] irqchip/irq-ath79-cpu: drop !OF init helper\n\nSigned-off-by: John Crispin <john@phrozen.org>\n---\n drivers/irqchip/irq-ath79-cpu.c | 7 -------\n 1 file changed, 7 deletions(-)\n\n--- a/drivers/irqchip/irq-ath79-cpu.c\n+++ b/drivers/irqchip/irq-ath79-cpu.c\n@@ -85,10 +85,3 @@ static int __init ar79_cpu_intc_of_init(\n }\n IRQCHIP_DECLARE(ar79_cpu_intc, \"qca,ar7100-cpu-intc\",\n \t\tar79_cpu_intc_of_init);\n-\n-void __init ath79_cpu_irq_init(unsigned irq_wb_chan2, unsigned irq_wb_chan3)\n-{\n-\tirq_wb_chan[2] = irq_wb_chan2;\n-\tirq_wb_chan[3] = irq_wb_chan3;\n-\tmips_cpu_irq_init();\n-}\n"
  },
  {
    "path": "target/linux/ath79/patches-5.10/0017-dt-bindings-PCI-qcom-ar7100-adds-binding-doc.patch",
    "content": "From 4a4f869ec58ed8910b9b2e68d0eee50957e9bb20 Mon Sep 17 00:00:00 2001\nFrom: John Crispin <john@phrozen.org>\nDate: Mon, 25 Jun 2018 15:52:10 +0200\nSubject: [PATCH 17/33] dt-bindings: PCI: qcom,ar7100: adds binding doc\n\nWith the driver being converted from platform_data to pure OF, we need to\nalso add some docs.\n\nCc: Rob Herring <robh+dt@kernel.org>\nCc: devicetree@vger.kernel.org\nSigned-off-by: John Crispin <john@phrozen.org>\n---\n .../devicetree/bindings/pci/qcom,ar7100-pci.txt    | 38 ++++++++++++++++++++++\n 1 file changed, 38 insertions(+)\n create mode 100644 Documentation/devicetree/bindings/pci/qcom,ar7100-pci.txt\n\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/pci/qcom,ar7100-pci.txt\n@@ -0,0 +1,38 @@\n+* Qualcomm Atheros AR7100 PCI express root complex\n+\n+Required properties:\n+- compatible: should contain \"qcom,ar7100-pci\" to identify the core.\n+- reg: Should contain the register ranges as listed in the reg-names property.\n+- reg-names: Definition: Must include the following entries\n+\t- \"cfg_base\"\tIO Memory\n+- #address-cells: set to <3>\n+- #size-cells: set to <2>\n+- ranges: ranges for the PCI memory and I/O regions\n+- interrupt-map-mask and interrupt-map: standard PCI\n+\tproperties to define the mapping of the PCIe interface to interrupt\n+\tnumbers.\n+- #interrupt-cells: set to <1>\n+- interrupt-controller: define to enable the builtin IRQ cascade.\n+\n+Optional properties:\n+- interrupt-parent: phandle to the MIPS IRQ controller\n+\n+* Example for ar7100\n+\tpcie-controller@180c0000 {\n+\t\tcompatible = \"qca,ar7100-pci\";\n+\t\t#address-cells = <3>;\n+\t\t#size-cells = <2>;\n+\t\tbus-range = <0x0 0x0>;\n+\t\treg = <0x17010000 0x100>;\n+\t\treg-names = \"cfg_base\";\n+\t\tranges = <0x2000000 0 0x10000000 0x10000000 0 0x07000000\n+\t\t\t  0x1000000 0 0x00000000 0x00000000 0 0x00000001>;\n+\t\tinterrupt-parent = <&cpuintc>;\n+\t\tinterrupts = <2>;\n+\n+\t\tinterrupt-controller;\n+\t\t#interrupt-cells = <1>;\n+\n+\t\tinterrupt-map-mask = <0 0 0 1>;\n+\t\tinterrupt-map = <0 0 0 0 &pcie0 0>;\n+\t};\n"
  },
  {
    "path": "target/linux/ath79/patches-5.10/0018-MIPS-pci-ar71xx-convert-to-OF.patch",
    "content": "From 1855ab6b1d27f5b38a648baf57ff6a534afec26d Mon Sep 17 00:00:00 2001\nFrom: John Crispin <john@phrozen.org>\nDate: Sat, 23 Jun 2018 15:07:23 +0200\nSubject: [PATCH 18/33] MIPS: pci-ar71xx: convert to OF\n\nWith the ath79 target getting converted to pure OF, we can drop all the\nplatform data code and add the missing OF bits to the driver. We also add\na irq domain for the PCI/e controllers cascade, thus making it usable from\ndts files.\n\nSigned-off-by: John Crispin <john@phrozen.org>\n---\n arch/mips/pci/pci-ar71xx.c | 82 +++++++++++++++++++++++-----------------------\n 1 file changed, 41 insertions(+), 41 deletions(-)\n\n--- a/arch/mips/pci/pci-ar71xx.c\n+++ b/arch/mips/pci/pci-ar71xx.c\n@@ -15,8 +15,11 @@\n #include <linux/pci.h>\n #include <linux/pci_regs.h>\n #include <linux/interrupt.h>\n+#include <linux/irqchip/chained_irq.h>\n #include <linux/init.h>\n #include <linux/platform_device.h>\n+#include <linux/of_irq.h>\n+#include <linux/of_pci.h>\n \n #include <asm/mach-ath79/ar71xx_regs.h>\n #include <asm/mach-ath79/ath79.h>\n@@ -46,12 +49,13 @@\n #define AR71XX_PCI_IRQ_COUNT\t\t5\n \n struct ar71xx_pci_controller {\n+\tstruct device_node *np;\n \tvoid __iomem *cfg_base;\n \tint irq;\n-\tint irq_base;\n \tstruct pci_controller pci_ctrl;\n \tstruct resource io_res;\n \tstruct resource mem_res;\n+\tstruct irq_domain *domain;\n };\n \n /* Byte lane enable bits */\n@@ -225,29 +229,30 @@ static struct pci_ops ar71xx_pci_ops = {\n \n static void ar71xx_pci_irq_handler(struct irq_desc *desc)\n {\n-\tstruct ar71xx_pci_controller *apc;\n \tvoid __iomem *base = ath79_reset_base;\n+\tstruct irq_chip *chip = irq_desc_get_chip(desc);\n+\tstruct ar71xx_pci_controller *apc = irq_desc_get_handler_data(desc);\n \tu32 pending;\n \n-\tapc = irq_desc_get_handler_data(desc);\n-\n+\tchained_irq_enter(chip, desc);\n \tpending = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_STATUS) &\n \t\t  __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);\n \n \tif (pending & AR71XX_PCI_INT_DEV0)\n-\t\tgeneric_handle_irq(apc->irq_base + 0);\n+\t\tgeneric_handle_irq(irq_linear_revmap(apc->domain, 1));\n \n \telse if (pending & AR71XX_PCI_INT_DEV1)\n-\t\tgeneric_handle_irq(apc->irq_base + 1);\n+\t\tgeneric_handle_irq(irq_linear_revmap(apc->domain, 2));\n \n \telse if (pending & AR71XX_PCI_INT_DEV2)\n-\t\tgeneric_handle_irq(apc->irq_base + 2);\n+\t\tgeneric_handle_irq(irq_linear_revmap(apc->domain, 3));\n \n \telse if (pending & AR71XX_PCI_INT_CORE)\n-\t\tgeneric_handle_irq(apc->irq_base + 4);\n+\t\tgeneric_handle_irq(irq_linear_revmap(apc->domain, 4));\n \n \telse\n \t\tspurious_interrupt();\n+\tchained_irq_exit(chip, desc);\n }\n \n static void ar71xx_pci_irq_unmask(struct irq_data *d)\n@@ -258,7 +263,7 @@ static void ar71xx_pci_irq_unmask(struct\n \tu32 t;\n \n \tapc = irq_data_get_irq_chip_data(d);\n-\tirq = d->irq - apc->irq_base;\n+\tirq = irq_linear_revmap(apc->domain, d->irq);\n \n \tt = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);\n \t__raw_writel(t | (1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE);\n@@ -275,7 +280,7 @@ static void ar71xx_pci_irq_mask(struct i\n \tu32 t;\n \n \tapc = irq_data_get_irq_chip_data(d);\n-\tirq = d->irq - apc->irq_base;\n+\tirq = irq_linear_revmap(apc->domain, d->irq);\n \n \tt = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);\n \t__raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE);\n@@ -291,24 +296,31 @@ static struct irq_chip ar71xx_pci_irq_ch\n \t.irq_mask_ack\t= ar71xx_pci_irq_mask,\n };\n \n+static int ar71xx_pci_irq_map(struct irq_domain *d,\n+\t\t\t      unsigned int irq, irq_hw_number_t hw)\n+{\n+\tstruct ar71xx_pci_controller *apc = d->host_data;\n+\n+\tirq_set_chip_and_handler(irq, &ar71xx_pci_irq_chip, handle_level_irq);\n+\tirq_set_chip_data(irq, apc);\n+\n+\treturn 0;\n+}\n+\n+static const struct irq_domain_ops ar71xx_pci_domain_ops = {\n+\t.xlate = irq_domain_xlate_onecell,\n+\t.map = ar71xx_pci_irq_map,\n+};\n+\n static void ar71xx_pci_irq_init(struct ar71xx_pci_controller *apc)\n {\n \tvoid __iomem *base = ath79_reset_base;\n-\tint i;\n \n \t__raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_ENABLE);\n \t__raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_STATUS);\n \n-\tBUILD_BUG_ON(ATH79_PCI_IRQ_COUNT < AR71XX_PCI_IRQ_COUNT);\n-\n-\tapc->irq_base = ATH79_PCI_IRQ_BASE;\n-\tfor (i = apc->irq_base;\n-\t     i < apc->irq_base + AR71XX_PCI_IRQ_COUNT; i++) {\n-\t\tirq_set_chip_and_handler(i, &ar71xx_pci_irq_chip,\n-\t\t\t\t\t handle_level_irq);\n-\t\tirq_set_chip_data(i, apc);\n-\t}\n-\n+\tapc->domain = irq_domain_add_linear(apc->np, AR71XX_PCI_IRQ_COUNT,\n+\t\t\t\t\t    &ar71xx_pci_domain_ops, apc);\n \tirq_set_chained_handler_and_data(apc->irq, ar71xx_pci_irq_handler,\n \t\t\t\t\t apc);\n }\n@@ -325,6 +337,11 @@ static void ar71xx_pci_reset(void)\n \tmdelay(100);\n }\n \n+static const struct of_device_id ar71xx_pci_ids[] = {\n+\t{ .compatible = \"qca,ar7100-pci\" },\n+\t{},\n+};\n+\n static int ar71xx_pci_probe(struct platform_device *pdev)\n {\n \tstruct ar71xx_pci_controller *apc;\n@@ -345,26 +362,6 @@ static int ar71xx_pci_probe(struct platf\n \tif (apc->irq < 0)\n \t\treturn -EINVAL;\n \n-\tres = platform_get_resource_byname(pdev, IORESOURCE_IO, \"io_base\");\n-\tif (!res)\n-\t\treturn -EINVAL;\n-\n-\tapc->io_res.parent = res;\n-\tapc->io_res.name = \"PCI IO space\";\n-\tapc->io_res.start = res->start;\n-\tapc->io_res.end = res->end;\n-\tapc->io_res.flags = IORESOURCE_IO;\n-\n-\tres = platform_get_resource_byname(pdev, IORESOURCE_MEM, \"mem_base\");\n-\tif (!res)\n-\t\treturn -EINVAL;\n-\n-\tapc->mem_res.parent = res;\n-\tapc->mem_res.name = \"PCI memory space\";\n-\tapc->mem_res.start = res->start;\n-\tapc->mem_res.end = res->end;\n-\tapc->mem_res.flags = IORESOURCE_MEM;\n-\n \tar71xx_pci_reset();\n \n \t/* setup COMMAND register */\n@@ -377,9 +374,11 @@ static int ar71xx_pci_probe(struct platf\n \n \tar71xx_pci_irq_init(apc);\n \n+\tapc->np = pdev->dev.of_node;\n \tapc->pci_ctrl.pci_ops = &ar71xx_pci_ops;\n \tapc->pci_ctrl.mem_resource = &apc->mem_res;\n \tapc->pci_ctrl.io_resource = &apc->io_res;\n+\tpci_load_of_ranges(&apc->pci_ctrl, pdev->dev.of_node);\n \n \tregister_pci_controller(&apc->pci_ctrl);\n \n@@ -390,6 +389,7 @@ static struct platform_driver ar71xx_pci\n \t.probe = ar71xx_pci_probe,\n \t.driver = {\n \t\t.name = \"ar71xx-pci\",\n+\t\t.of_match_table = of_match_ptr(ar71xx_pci_ids),\n \t},\n };\n \n"
  },
  {
    "path": "target/linux/ath79/patches-5.10/0019-dt-bindings-PCI-qcom-ar7240-adds-binding-doc.patch",
    "content": "From ea27764bc3ef2a05decf3ae05edffc289cd0d93c Mon Sep 17 00:00:00 2001\nFrom: John Crispin <john@phrozen.org>\nDate: Mon, 25 Jun 2018 15:52:02 +0200\nSubject: [PATCH 19/33] dt-bindings: PCI: qcom,ar7240: adds binding doc\n\nWith the driver being converted from platform_data to pure OF, we need to\nalso add some docs.\n\nCc: Rob Herring <robh+dt@kernel.org>\nCc: devicetree@vger.kernel.org\nSigned-off-by: John Crispin <john@phrozen.org>\n---\n .../devicetree/bindings/pci/qcom,ar7240-pci.txt    | 42 ++++++++++++++++++++++\n 1 file changed, 42 insertions(+)\n create mode 100644 Documentation/devicetree/bindings/pci/qcom,ar7240-pci.txt\n\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/pci/qcom,ar7240-pci.txt\n@@ -0,0 +1,42 @@\n+* Qualcomm Atheros AR724X PCI express root complex\n+\n+Required properties:\n+- compatible: should contain \"qcom,ar7240-pci\" to identify the core.\n+- reg: Should contain the register ranges as listed in the reg-names property.\n+- reg-names: Definition: Must include the following entries\n+\t- \"crp_base\"\tConfiguration registers\n+\t- \"ctrl_base\"\tControl registers\n+\t- \"cfg_base\"\tIO Memory\n+- #address-cells: set to <3>\n+- #size-cells: set to <2>\n+- ranges: ranges for the PCI memory and I/O regions\n+- interrupt-map-mask and interrupt-map: standard PCI\n+\tproperties to define the mapping of the PCIe interface to interrupt\n+\tnumbers.\n+- #interrupt-cells: set to <1>\n+- interrupt-parent: phandle to the MIPS IRQ controller\n+\n+Optional properties:\n+- interrupt-controller: define to enable the builtin IRQ cascade.\n+\n+* Example for qca9557\n+\tpcie-controller@180c0000 {\n+\t\tcompatible = \"qcom,ar7240-pci\";\n+\t\t#address-cells = <3>;\n+\t\t#size-cells = <2>;\n+\t\tbus-range = <0x0 0x0>;\n+\t\treg = <0x180c0000 0x1000>,\n+\t\t      <0x180f0000 0x100>,\n+\t\t      <0x14000000 0x1000>;\n+\t\treg-names = \"crp_base\", \"ctrl_base\", \"cfg_base\";\n+\t\tranges = <0x2000000 0 0x10000000 0x10000000 0 0x04000000\n+\t\t\t  0x1000000 0 0x00000000 0x00000000 0 0x00000001>;\n+\t\tinterrupt-parent = <&intc2>;\n+\t\tinterrupts = <1>;\n+\n+\t\tinterrupt-controller;\n+\t\t#interrupt-cells = <1>;\n+\n+\t\tinterrupt-map-mask = <0 0 0 1>;\n+\t\tinterrupt-map = <0 0 0 0 &pcie0 0>;\n+\t};\n"
  },
  {
    "path": "target/linux/ath79/patches-5.10/0020-MIPS-pci-ar724x-convert-to-OF.patch",
    "content": "From a522ee0199d5d3ea114ca2e211f6ac398d3e8e0b Mon Sep 17 00:00:00 2001\nFrom: John Crispin <john@phrozen.org>\nDate: Sat, 23 Jun 2018 15:07:37 +0200\nSubject: [PATCH 20/33] MIPS: pci-ar724x: convert to OF\n\nWith the ath79 target getting converted to pure OF, we can drop all the\nplatform data code and add the missing OF bits to the driver. We also add\na irq domain for the PCI/e controllers cascade, thus making it usable from\ndts files.\n\nSigned-off-by: John Crispin <john@phrozen.org>\n---\n arch/mips/pci/pci-ar724x.c | 88 ++++++++++++++++++++++------------------------\n 1 file changed, 42 insertions(+), 46 deletions(-)\n\n--- a/arch/mips/pci/pci-ar724x.c\n+++ b/arch/mips/pci/pci-ar724x.c\n@@ -11,8 +11,11 @@\n #include <linux/init.h>\n #include <linux/delay.h>\n #include <linux/platform_device.h>\n+#include <linux/irqchip/chained_irq.h>\n #include <asm/mach-ath79/ath79.h>\n #include <asm/mach-ath79/ar71xx_regs.h>\n+#include <linux/of_irq.h>\n+#include <linux/of_pci.h>\n \n #define AR724X_PCI_REG_APP\t\t0x00\n #define AR724X_PCI_REG_RESET\t\t0x18\n@@ -42,17 +45,20 @@ struct ar724x_pci_controller {\n \tvoid __iomem *crp_base;\n \n \tint irq;\n-\tint irq_base;\n \n \tbool link_up;\n \tbool bar0_is_cached;\n \tu32  bar0_value;\n \n+\tstruct device_node *np;\n \tstruct pci_controller pci_controller;\n+\tstruct irq_domain *domain;\n \tstruct resource io_res;\n \tstruct resource mem_res;\n };\n \n+static struct irq_chip ar724x_pci_irq_chip;\n+\n static inline bool ar724x_pci_check_link(struct ar724x_pci_controller *apc)\n {\n \tu32 reset;\n@@ -228,35 +234,31 @@ static struct pci_ops ar724x_pci_ops = {\n \n static void ar724x_pci_irq_handler(struct irq_desc *desc)\n {\n-\tstruct ar724x_pci_controller *apc;\n-\tvoid __iomem *base;\n+\tstruct irq_chip *chip = irq_desc_get_chip(desc);\n+\tstruct ar724x_pci_controller *apc = irq_desc_get_handler_data(desc);\n \tu32 pending;\n \n-\tapc = irq_desc_get_handler_data(desc);\n-\tbase = apc->ctrl_base;\n-\n-\tpending = __raw_readl(base + AR724X_PCI_REG_INT_STATUS) &\n-\t\t  __raw_readl(base + AR724X_PCI_REG_INT_MASK);\n+\tchained_irq_enter(chip, desc);\n+\tpending = __raw_readl(apc->ctrl_base + AR724X_PCI_REG_INT_STATUS) &\n+\t\t  __raw_readl(apc->ctrl_base + AR724X_PCI_REG_INT_MASK);\n \n \tif (pending & AR724X_PCI_INT_DEV0)\n-\t\tgeneric_handle_irq(apc->irq_base + 0);\n-\n+\t\tgeneric_handle_irq(irq_linear_revmap(apc->domain, 1));\n \telse\n \t\tspurious_interrupt();\n+\tchained_irq_exit(chip, desc);\n }\n \n static void ar724x_pci_irq_unmask(struct irq_data *d)\n {\n \tstruct ar724x_pci_controller *apc;\n \tvoid __iomem *base;\n-\tint offset;\n \tu32 t;\n \n \tapc = irq_data_get_irq_chip_data(d);\n \tbase = apc->ctrl_base;\n-\toffset = apc->irq_base - d->irq;\n \n-\tswitch (offset) {\n+\tswitch (irq_linear_revmap(apc->domain, d->irq)) {\n \tcase 0:\n \t\tt = __raw_readl(base + AR724X_PCI_REG_INT_MASK);\n \t\t__raw_writel(t | AR724X_PCI_INT_DEV0,\n@@ -270,14 +272,12 @@ static void ar724x_pci_irq_mask(struct i\n {\n \tstruct ar724x_pci_controller *apc;\n \tvoid __iomem *base;\n-\tint offset;\n \tu32 t;\n \n \tapc = irq_data_get_irq_chip_data(d);\n \tbase = apc->ctrl_base;\n-\toffset = apc->irq_base - d->irq;\n \n-\tswitch (offset) {\n+\tswitch (irq_linear_revmap(apc->domain, d->irq)) {\n \tcase 0:\n \t\tt = __raw_readl(base + AR724X_PCI_REG_INT_MASK);\n \t\t__raw_writel(t & ~AR724X_PCI_INT_DEV0,\n@@ -302,26 +302,34 @@ static struct irq_chip ar724x_pci_irq_ch\n \t.irq_mask_ack\t= ar724x_pci_irq_mask,\n };\n \n+static int ar724x_pci_irq_map(struct irq_domain *d,\n+\t\t\t      unsigned int irq, irq_hw_number_t hw)\n+{\n+\tstruct ar724x_pci_controller *apc = d->host_data;\n+\n+\tirq_set_chip_and_handler(irq, &ar724x_pci_irq_chip, handle_level_irq);\n+\tirq_set_chip_data(irq, apc);\n+\n+\treturn 0;\n+}\n+\n+static const struct irq_domain_ops ar724x_pci_domain_ops = {\n+\t.xlate = irq_domain_xlate_onecell,\n+\t.map = ar724x_pci_irq_map,\n+};\n+\n static void ar724x_pci_irq_init(struct ar724x_pci_controller *apc,\n \t\t\t\tint id)\n {\n \tvoid __iomem *base;\n-\tint i;\n \n \tbase = apc->ctrl_base;\n \n \t__raw_writel(0, base + AR724X_PCI_REG_INT_MASK);\n \t__raw_writel(0, base + AR724X_PCI_REG_INT_STATUS);\n \n-\tapc->irq_base = ATH79_PCI_IRQ_BASE + (id * AR724X_PCI_IRQ_COUNT);\n-\n-\tfor (i = apc->irq_base;\n-\t     i < apc->irq_base + AR724X_PCI_IRQ_COUNT; i++) {\n-\t\tirq_set_chip_and_handler(i, &ar724x_pci_irq_chip,\n-\t\t\t\t\t handle_level_irq);\n-\t\tirq_set_chip_data(i, apc);\n-\t}\n-\n+\tapc->domain = irq_domain_add_linear(apc->np, 2,\n+\t\t\t\t\t    &ar724x_pci_domain_ops, apc);\n \tirq_set_chained_handler_and_data(apc->irq, ar724x_pci_irq_handler,\n \t\t\t\t\t apc);\n }\n@@ -388,29 +396,11 @@ static int ar724x_pci_probe(struct platf\n \tif (apc->irq < 0)\n \t\treturn -EINVAL;\n \n-\tres = platform_get_resource_byname(pdev, IORESOURCE_IO, \"io_base\");\n-\tif (!res)\n-\t\treturn -EINVAL;\n-\n-\tapc->io_res.parent = res;\n-\tapc->io_res.name = \"PCI IO space\";\n-\tapc->io_res.start = res->start;\n-\tapc->io_res.end = res->end;\n-\tapc->io_res.flags = IORESOURCE_IO;\n-\n-\tres = platform_get_resource_byname(pdev, IORESOURCE_MEM, \"mem_base\");\n-\tif (!res)\n-\t\treturn -EINVAL;\n-\n-\tapc->mem_res.parent = res;\n-\tapc->mem_res.name = \"PCI memory space\";\n-\tapc->mem_res.start = res->start;\n-\tapc->mem_res.end = res->end;\n-\tapc->mem_res.flags = IORESOURCE_MEM;\n-\n+\tapc->np = pdev->dev.of_node;\n \tapc->pci_controller.pci_ops = &ar724x_pci_ops;\n \tapc->pci_controller.io_resource = &apc->io_res;\n \tapc->pci_controller.mem_resource = &apc->mem_res;\n+\tpci_load_of_ranges(&apc->pci_controller, pdev->dev.of_node);\n \n \t/*\n \t * Do the full PCIE Root Complex Initialization Sequence if the PCIe\n@@ -432,10 +422,16 @@ static int ar724x_pci_probe(struct platf\n \treturn 0;\n }\n \n+static const struct of_device_id ar724x_pci_ids[] = {\n+\t{ .compatible = \"qcom,ar7240-pci\" },\n+\t{},\n+};\n+\n static struct platform_driver ar724x_pci_driver = {\n \t.probe = ar724x_pci_probe,\n \t.driver = {\n \t\t.name = \"ar724x-pci\",\n+\t\t.of_match_table = of_match_ptr(ar724x_pci_ids),\n \t},\n };\n \n"
  },
  {
    "path": "target/linux/ath79/patches-5.10/0032-MIPS-ath79-sanitize-symbols.patch",
    "content": "From 3fc8585cf76022dba7496627074d42af88c30718 Mon Sep 17 00:00:00 2001\nFrom: John Crispin <john@phrozen.org>\nDate: Sat, 23 Jun 2018 15:16:55 +0200\nSubject: [PATCH 32/33] MIPS: ath79: sanitize symbols\n\nWe no longer need to select which SoCs are supported as the whole arch\ncode is always built. So lets drop all the SoC symbols\n\nSigned-off-by: John Crispin <john@phrozen.org>\n---\n arch/mips/Kconfig       |  2 ++\n arch/mips/ath79/Kconfig | 44 +++++---------------------------------------\n arch/mips/pci/Makefile  |  2 +-\n 3 files changed, 8 insertions(+), 40 deletions(-)\n\n--- a/arch/mips/Kconfig\n+++ b/arch/mips/Kconfig\n@@ -245,6 +245,8 @@ config ATH79\n \tselect SYS_SUPPORTS_BIG_ENDIAN\n \tselect SYS_SUPPORTS_MIPS16\n \tselect SYS_SUPPORTS_ZBOOT_UART_PROM\n+\tselect HAVE_PCI\n+\tselect USB_ARCH_HAS_EHCI\n \tselect USE_OF\n \tselect USB_EHCI_ROOT_HUB_TT if USB_EHCI_HCD_PLATFORM\n \thelp\n--- a/arch/mips/ath79/Kconfig\n+++ b/arch/mips/ath79/Kconfig\n@@ -1,48 +1,14 @@\n # SPDX-License-Identifier: GPL-2.0\n if ATH79\n \n-config SOC_AR71XX\n-\tselect HAVE_PCI\n-\tdef_bool n\n-\n-config SOC_AR724X\n-\tselect HAVE_PCI\n-\tselect PCI_AR724X if PCI\n-\tdef_bool n\n-\n-config SOC_AR913X\n-\tdef_bool n\n-\n-config SOC_AR933X\n-\tdef_bool n\n-\n-config SOC_AR934X\n-\tselect HAVE_PCI\n-\tselect PCI_AR724X if PCI\n-\tdef_bool n\n-\n-config SOC_QCA955X\n-\tselect HAVE_PCI\n-\tselect PCI_AR724X if PCI\n+config PCI_AR71XX\n+\tbool \"PCI support for AR7100 type SoCs\"\n+\tdepends on PCI\n \tdef_bool n\n \n config PCI_AR724X\n-\tdef_bool n\n-\n-config ATH79_DEV_GPIO_BUTTONS\n-\tdef_bool n\n-\n-config ATH79_DEV_LEDS_GPIO\n-\tdef_bool n\n-\n-config ATH79_DEV_SPI\n-\tdef_bool n\n-\n-config ATH79_DEV_USB\n-\tdef_bool n\n-\n-config ATH79_DEV_WMAC\n-\tdepends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA955X)\n+\tbool \"PCI support for AR724x type SoCs\"\n+\tdepends on PCI\n \tdef_bool n\n \n endif\n--- a/arch/mips/pci/Makefile\n+++ b/arch/mips/pci/Makefile\n@@ -21,7 +21,7 @@ obj-$(CONFIG_BCM63XX)\t\t+= pci-bcm63xx.o\n \t\t\t\t\tops-bcm63xx.o\n obj-$(CONFIG_MIPS_ALCHEMY)\t+= pci-alchemy.o\n obj-$(CONFIG_PCI_AR2315)\t+= pci-ar2315.o\n-obj-$(CONFIG_SOC_AR71XX)\t+= pci-ar71xx.o\n+obj-$(CONFIG_PCI_AR71XX)\t+= pci-ar71xx.o\n obj-$(CONFIG_PCI_AR724X)\t+= pci-ar724x.o\n obj-$(CONFIG_PCI_XTALK_BRIDGE)\t+= pci-xtalk-bridge.o\n #\n"
  },
  {
    "path": "target/linux/ath79/patches-5.10/0033-spi-ath79-drop-pdata-support.patch",
    "content": "From c4e197bbcecc7233aa9e553e7047fa50e4e1fe77 Mon Sep 17 00:00:00 2001\nFrom: John Crispin <john@phrozen.org>\nDate: Mon, 25 Jun 2018 15:52:34 +0200\nSubject: [PATCH 33/33] spi: ath79: drop pdata support\n\nThe target is being converted to pure OF. We can therefore drop all of the\nplatform data code from the driver.\n\nCc: linux-spi@vger.kernel.org\nAcked-by: Mark Brown <broonie@kernel.org>\nSigned-off-by: John Crispin <john@phrozen.org>\n---\n include/linux/platform_data/spi-ath79.h | 16 -------------------\n drivers/spi/spi-ath79.c                               |  8 --------\n 2 files changed, 27 deletions(-)\n delete mode 100644 arch/mips/include/asm/mach-ath79/ath79_spi_platform.h\n\n--- a/include/linux/platform_data/spi-ath79.h\n+++ /dev/null\n@@ -1,16 +0,0 @@\n-/* SPDX-License-Identifier: GPL-2.0-only */\n-/*\n- *  Platform data definition for Atheros AR71XX/AR724X/AR913X SPI controller\n- *\n- *  Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>\n- */\n-\n-#ifndef _ATH79_SPI_PLATFORM_H\n-#define _ATH79_SPI_PLATFORM_H\n-\n-struct ath79_spi_platform_data {\n-\tunsigned\tbus_num;\n-\tunsigned\tnum_chipselect;\n-};\n-\n-#endif /* _ATH79_SPI_PLATFORM_H */\n--- a/drivers/spi/spi-ath79.c\n+++ b/drivers/spi/spi-ath79.c\n@@ -19,7 +19,6 @@\n #include <linux/bitops.h>\n #include <linux/clk.h>\n #include <linux/err.h>\n-#include <linux/platform_data/spi-ath79.h>\n \n #define DRV_NAME\t\"ath79-spi\"\n \n@@ -138,7 +137,6 @@ static int ath79_spi_probe(struct platfo\n {\n \tstruct spi_master *master;\n \tstruct ath79_spi *sp;\n-\tstruct ath79_spi_platform_data *pdata;\n \tunsigned long rate;\n \tint ret;\n \n@@ -152,15 +150,9 @@ static int ath79_spi_probe(struct platfo\n \tmaster->dev.of_node = pdev->dev.of_node;\n \tplatform_set_drvdata(pdev, sp);\n \n-\tpdata = dev_get_platdata(&pdev->dev);\n-\n \tmaster->use_gpio_descriptors = true;\n \tmaster->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32);\n \tmaster->flags = SPI_MASTER_GPIO_SS;\n-\tif (pdata) {\n-\t\tmaster->bus_num = pdata->bus_num;\n-\t\tmaster->num_chipselect = pdata->num_chipselect;\n-\t}\n \n \tsp->bitbang.master = master;\n \tsp->bitbang.chipselect = ath79_spi_chipselect;\n"
  },
  {
    "path": "target/linux/ath79/patches-5.10/0034-MIPS-ath79-ath9k-exports.patch",
    "content": "--- a/arch/mips/ath79/common.c\n+++ b/arch/mips/ath79/common.c\n@@ -31,11 +31,13 @@ EXPORT_SYMBOL_GPL(ath79_ddr_freq);\n \n enum ath79_soc_type ath79_soc;\n unsigned int ath79_soc_rev;\n+EXPORT_SYMBOL_GPL(ath79_soc_rev);\n \n void __iomem *ath79_pll_base;\n void __iomem *ath79_reset_base;\n EXPORT_SYMBOL_GPL(ath79_reset_base);\n-static void __iomem *ath79_ddr_base;\n+void __iomem *ath79_ddr_base;\n+EXPORT_SYMBOL_GPL(ath79_ddr_base);\n static void __iomem *ath79_ddr_wb_flush_base;\n static void __iomem *ath79_ddr_pci_win_base;\n \n--- a/arch/mips/include/asm/mach-ath79/ath79.h\n+++ b/arch/mips/include/asm/mach-ath79/ath79.h\n@@ -149,6 +149,7 @@ void ath79_ddr_wb_flush(unsigned int reg\n void ath79_ddr_set_pci_windows(void);\n \n extern void __iomem *ath79_pll_base;\n+extern void __iomem *ath79_ddr_base;\n extern void __iomem *ath79_reset_base;\n \n static inline void ath79_pll_wr(unsigned reg, u32 val)\n"
  },
  {
    "path": "target/linux/ath79/patches-5.10/0036-MIPS-ath79-remove-irq-code-from-pci.patch",
    "content": "--- a/arch/mips/pci/pci-ar71xx.c\n+++ b/arch/mips/pci/pci-ar71xx.c\n@@ -51,11 +51,9 @@\n struct ar71xx_pci_controller {\n \tstruct device_node *np;\n \tvoid __iomem *cfg_base;\n-\tint irq;\n \tstruct pci_controller pci_ctrl;\n \tstruct resource io_res;\n \tstruct resource mem_res;\n-\tstruct irq_domain *domain;\n };\n \n /* Byte lane enable bits */\n@@ -227,104 +225,6 @@ static struct pci_ops ar71xx_pci_ops = {\n \t.write\t= ar71xx_pci_write_config,\n };\n \n-static void ar71xx_pci_irq_handler(struct irq_desc *desc)\n-{\n-\tvoid __iomem *base = ath79_reset_base;\n-\tstruct irq_chip *chip = irq_desc_get_chip(desc);\n-\tstruct ar71xx_pci_controller *apc = irq_desc_get_handler_data(desc);\n-\tu32 pending;\n-\n-\tchained_irq_enter(chip, desc);\n-\tpending = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_STATUS) &\n-\t\t  __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);\n-\n-\tif (pending & AR71XX_PCI_INT_DEV0)\n-\t\tgeneric_handle_irq(irq_linear_revmap(apc->domain, 1));\n-\n-\telse if (pending & AR71XX_PCI_INT_DEV1)\n-\t\tgeneric_handle_irq(irq_linear_revmap(apc->domain, 2));\n-\n-\telse if (pending & AR71XX_PCI_INT_DEV2)\n-\t\tgeneric_handle_irq(irq_linear_revmap(apc->domain, 3));\n-\n-\telse if (pending & AR71XX_PCI_INT_CORE)\n-\t\tgeneric_handle_irq(irq_linear_revmap(apc->domain, 4));\n-\n-\telse\n-\t\tspurious_interrupt();\n-\tchained_irq_exit(chip, desc);\n-}\n-\n-static void ar71xx_pci_irq_unmask(struct irq_data *d)\n-{\n-\tstruct ar71xx_pci_controller *apc;\n-\tunsigned int irq;\n-\tvoid __iomem *base = ath79_reset_base;\n-\tu32 t;\n-\n-\tapc = irq_data_get_irq_chip_data(d);\n-\tirq = irq_linear_revmap(apc->domain, d->irq);\n-\n-\tt = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);\n-\t__raw_writel(t | (1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE);\n-\n-\t/* flush write */\n-\t__raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);\n-}\n-\n-static void ar71xx_pci_irq_mask(struct irq_data *d)\n-{\n-\tstruct ar71xx_pci_controller *apc;\n-\tunsigned int irq;\n-\tvoid __iomem *base = ath79_reset_base;\n-\tu32 t;\n-\n-\tapc = irq_data_get_irq_chip_data(d);\n-\tirq = irq_linear_revmap(apc->domain, d->irq);\n-\n-\tt = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);\n-\t__raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE);\n-\n-\t/* flush write */\n-\t__raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);\n-}\n-\n-static struct irq_chip ar71xx_pci_irq_chip = {\n-\t.name\t\t= \"AR71XX PCI\",\n-\t.irq_mask\t= ar71xx_pci_irq_mask,\n-\t.irq_unmask\t= ar71xx_pci_irq_unmask,\n-\t.irq_mask_ack\t= ar71xx_pci_irq_mask,\n-};\n-\n-static int ar71xx_pci_irq_map(struct irq_domain *d,\n-\t\t\t      unsigned int irq, irq_hw_number_t hw)\n-{\n-\tstruct ar71xx_pci_controller *apc = d->host_data;\n-\n-\tirq_set_chip_and_handler(irq, &ar71xx_pci_irq_chip, handle_level_irq);\n-\tirq_set_chip_data(irq, apc);\n-\n-\treturn 0;\n-}\n-\n-static const struct irq_domain_ops ar71xx_pci_domain_ops = {\n-\t.xlate = irq_domain_xlate_onecell,\n-\t.map = ar71xx_pci_irq_map,\n-};\n-\n-static void ar71xx_pci_irq_init(struct ar71xx_pci_controller *apc)\n-{\n-\tvoid __iomem *base = ath79_reset_base;\n-\n-\t__raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_ENABLE);\n-\t__raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_STATUS);\n-\n-\tapc->domain = irq_domain_add_linear(apc->np, AR71XX_PCI_IRQ_COUNT,\n-\t\t\t\t\t    &ar71xx_pci_domain_ops, apc);\n-\tirq_set_chained_handler_and_data(apc->irq, ar71xx_pci_irq_handler,\n-\t\t\t\t\t apc);\n-}\n-\n static void ar71xx_pci_reset(void)\n {\n \tath79_device_reset_set(AR71XX_RESET_PCI_BUS | AR71XX_RESET_PCI_CORE);\n@@ -358,10 +258,6 @@ static int ar71xx_pci_probe(struct platf\n \tif (IS_ERR(apc->cfg_base))\n \t\treturn PTR_ERR(apc->cfg_base);\n \n-\tapc->irq = platform_get_irq(pdev, 0);\n-\tif (apc->irq < 0)\n-\t\treturn -EINVAL;\n-\n \tar71xx_pci_reset();\n \n \t/* setup COMMAND register */\n@@ -372,8 +268,6 @@ static int ar71xx_pci_probe(struct platf\n \t/* clear bus errors */\n \tar71xx_pci_check_error(apc, 1);\n \n-\tar71xx_pci_irq_init(apc);\n-\n \tapc->np = pdev->dev.of_node;\n \tapc->pci_ctrl.pci_ops = &ar71xx_pci_ops;\n \tapc->pci_ctrl.mem_resource = &apc->mem_res;\n"
  },
  {
    "path": "target/linux/ath79/patches-5.10/0037-missing-registers.patch",
    "content": "commit f3ffac90bc7266b7d917616f3233f58e8c08a196\nAuthor: Christian Lamparter <chunkeey@gmail.com>\nDate:   Fri Aug 10 23:24:47 2018 +0200\n\n    ath79: gmac: add parsers for rxd(v)- and tx(d|en)-delay for AR9344\n\n    Signed-off-by: Christian Lamparter <chunkeey@gmail.com>\n\n--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h\n+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h\n@@ -1226,6 +1226,10 @@\n #define AR934X_ETH_CFG_RDV_DELAY        BIT(16)\n #define AR934X_ETH_CFG_RDV_DELAY_MASK   0x3\n #define AR934X_ETH_CFG_RDV_DELAY_SHIFT  16\n+#define AR934X_ETH_CFG_TXD_DELAY_MASK   0x3\n+#define AR934X_ETH_CFG_TXD_DELAY_SHIFT  18\n+#define AR934X_ETH_CFG_TXE_DELAY_MASK   0x3\n+#define AR934X_ETH_CFG_TXE_DELAY_SHIFT  20\n \n /*\n  * QCA953X GMAC Interface\n"
  },
  {
    "path": "target/linux/ath79/patches-5.10/0038-MIPS-ath79-add-missing-QCA955x-GMAC-registers.patch",
    "content": "From 60efe35257b063ce584968f9f80b437030ce6ba6 Mon Sep 17 00:00:00 2001\nFrom: David Bauer <mail@david-bauer.net>\nDate: Mon, 18 Mar 2019 00:54:06 +0100\nSubject: [PATCH] MIPS: ath79: add missing QCA955x GMAC registers\n\nThis adds missing GMAC register definitions for the Qualcomm Atheros\nQCA955X series MIPS SoCs.\n\nThey originate from the platforms U-Boot code and the AVM FRITZ!WLAN\nRepeater 450E's GPL tarball.\n\nSigned-off-by: David Bauer <mail@david-bauer.net>\n---\n .../mips/include/asm/mach-ath79/ar71xx_regs.h | 54 +++++++++++++++++++\n 1 file changed, 54 insertions(+)\n\n--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h\n+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h\n@@ -1246,7 +1246,12 @@\n  */\n \n #define QCA955X_GMAC_REG_ETH_CFG\t0x00\n+#define QCA955X_GMAC_REG_SGMII_RESET\t0x14\n #define QCA955X_GMAC_REG_SGMII_SERDES\t0x18\n+#define QCA955X_GMAC_REG_MR_AN_CONTROL\t0x1c\n+#define QCA955X_GMAC_REG_MR_AN_STATUS\t0x20\n+#define QCA955X_GMAC_REG_SGMII_CONFIG\t0x34\n+#define QCA955X_GMAC_REG_SGMII_DEBUG\t0x58\n \n #define QCA955X_ETH_CFG_RGMII_EN\tBIT(0)\n #define QCA955X_ETH_CFG_MII_GE0\t\tBIT(1)\n@@ -1268,9 +1273,58 @@\n #define QCA955X_ETH_CFG_TXE_DELAY_MASK\t0x3\n #define QCA955X_ETH_CFG_TXE_DELAY_SHIFT\t20\n \n+#define QCA955X_SGMII_RESET_RX_CLK_N_RESET\t0\n+#define QCA955X_SGMII_RESET_RX_CLK_N\t\tBIT(0)\n+#define QCA955X_SGMII_RESET_TX_CLK_N\t\tBIT(1)\n+#define QCA955X_SGMII_RESET_RX_125M_N\t\tBIT(2)\n+#define QCA955X_SGMII_RESET_TX_125M_N\t\tBIT(3)\n+#define QCA955X_SGMII_RESET_HW_RX_125M_N\tBIT(4)\n+\n #define QCA955X_SGMII_SERDES_LOCK_DETECT_STATUS\tBIT(15)\n #define QCA955X_SGMII_SERDES_RES_CALIBRATION_SHIFT 23\n #define QCA955X_SGMII_SERDES_RES_CALIBRATION_MASK 0xf\n+\n+#define QCA955X_MR_AN_CONTROL_SPEED_SEL1\tBIT(6)\n+#define QCA955X_MR_AN_CONTROL_DUPLEX_MODE\tBIT(8)\n+#define QCA955X_MR_AN_CONTROL_RESTART_AN\tBIT(9)\n+#define QCA955X_MR_AN_CONTROL_POWER_DOWN\tBIT(11)\n+#define QCA955X_MR_AN_CONTROL_AN_ENABLE\t\tBIT(12)\n+#define QCA955X_MR_AN_CONTROL_SPEED_SEL0\tBIT(13)\n+#define QCA955X_MR_AN_CONTROL_LOOPBACK\t\tBIT(14)\n+#define QCA955X_MR_AN_CONTROL_PHY_RESET\t\tBIT(15)\n+\n+#define QCA955X_MR_AN_STATUS_EXT_CAP\t\tBIT(0)\n+#define QCA955X_MR_AN_STATUS_LINK_UP\t\tBIT(2)\n+#define QCA955X_MR_AN_STATUS_AN_ABILITY\t\tBIT(3)\n+#define QCA955X_MR_AN_STATUS_REMOTE_FAULT\tBIT(4)\n+#define QCA955X_MR_AN_STATUS_AN_COMPLETE\tBIT(5)\n+#define QCA955X_MR_AN_STATUS_NO_PREAMBLE\tBIT(6)\n+#define QCA955X_MR_AN_STATUS_BASE_PAGE\t\tBIT(7)\n+\n+#define QCA955X_SGMII_CONFIG_MODE_CTRL_SHIFT\t\t0\n+#define QCA955X_SGMII_CONFIG_MODE_CTRL_MASK\t\t0x7\n+#define QCA955X_SGMII_CONFIG_ENABLE_SGMII_TX_PAUSE\tBIT(3)\n+#define QCA955X_SGMII_CONFIG_MR_REG4_CHANGED\t\tBIT(4)\n+#define QCA955X_SGMII_CONFIG_FORCE_SPEED\t\tBIT(5)\n+#define QCA955X_SGMII_CONFIG_SPEED_SHIFT\t\t6\n+#define QCA955X_SGMII_CONFIG_SPEED_MASK\t\t\t0xc0\n+#define QCA955X_SGMII_CONFIG_REMOTE_PHY_LOOPBACK\tBIT(8)\n+#define QCA955X_SGMII_CONFIG_NEXT_PAGE_LOADED\t\tBIT(9)\n+#define QCA955X_SGMII_CONFIG_MDIO_ENABLE\t\tBIT(10)\n+#define QCA955X_SGMII_CONFIG_MDIO_PULSE\t\t\tBIT(11)\n+#define QCA955X_SGMII_CONFIG_MDIO_COMPLETE\t\tBIT(12)\n+#define QCA955X_SGMII_CONFIG_PRBS_ENABLE\t\tBIT(13)\n+#define QCA955X_SGMII_CONFIG_BERT_ENABLE\t\tBIT(14)\n+\n+#define QCA955X_SGMII_DEBUG_TX_STATE_MASK\t0xff\n+#define QCA955X_SGMII_DEBUG_TX_STATE_SHIFT\t0\n+#define QCA955X_SGMII_DEBUG_RX_STATE_MASK\t0xff00\n+#define QCA955X_SGMII_DEBUG_RX_STATE_SHIFT\t8\n+#define QCA955X_SGMII_DEBUG_RX_SYNC_STATE_MASK\t0xff0000\n+#define QCA955X_SGMII_DEBUG_RX_SYNC_STATE_SHIFT\t16\n+#define QCA955X_SGMII_DEBUG_ARB_STATE_MASK\t0xf000000\n+#define QCA955X_SGMII_DEBUG_ARB_STATE_SHIFT\t24\n+\n /*\n  * QCA956X GMAC Interface\n  */\n"
  },
  {
    "path": "target/linux/ath79/patches-5.10/0039-MIPS-ath79-export-UART1-reference-clock.patch",
    "content": "--- a/arch/mips/ath79/clock.c\n+++ b/arch/mips/ath79/clock.c\n@@ -40,6 +40,7 @@ static const char * const clk_names[ATH7\n \t[ATH79_CLK_AHB] = \"ahb\",\n \t[ATH79_CLK_REF] = \"ref\",\n \t[ATH79_CLK_MDIO] = \"mdio\",\n+\t[ATH79_CLK_UART1] = \"uart1\",\n };\n \n static const char * __init ath79_clk_name(int type)\n@@ -344,6 +345,9 @@ static void __init ar934x_clocks_init(vo\n \tif (clk_ctrl & AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL)\n \t\tath79_set_clk(ATH79_CLK_MDIO, 100 * 1000 * 1000);\n \n+\tif (clk_ctrl & AR934X_PLL_SWITCH_CLOCK_CONTROL_UART1_CLK_SEL)\n+\t\tath79_set_clk(ATH79_CLK_UART1, 100 * 1000 * 1000);\n+\n \tiounmap(dpll_base);\n }\n \n@@ -649,6 +653,9 @@ static void __init ath79_clocks_init_dt(\n \tif (!clks[ATH79_CLK_MDIO])\n \t\tclks[ATH79_CLK_MDIO] = clks[ATH79_CLK_REF];\n \n+\tif (!clks[ATH79_CLK_UART1])\n+\t\tclks[ATH79_CLK_UART1] = clks[ATH79_CLK_REF];\n+\n \tif (of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data)) {\n \t\tpr_err(\"%pOF: could not register clk provider\\n\", np);\n \t\tgoto err_iounmap;\n--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h\n+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h\n@@ -348,6 +348,7 @@\n #define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL\tBIT(24)\n \n #define AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL\tBIT(6)\n+#define AR934X_PLL_SWITCH_CLOCK_CONTROL_UART1_CLK_SEL\tBIT(7)\n \n #define QCA953X_PLL_CPU_CONFIG_REG\t\t0x00\n #define QCA953X_PLL_DDR_CONFIG_REG\t\t0x04\n--- a/include/dt-bindings/clock/ath79-clk.h\n+++ b/include/dt-bindings/clock/ath79-clk.h\n@@ -11,7 +11,8 @@\n #define ATH79_CLK_AHB\t\t2\n #define ATH79_CLK_REF\t\t3\n #define ATH79_CLK_MDIO\t\t4\n+#define ATH79_CLK_UART1\t\t5\n \n-#define ATH79_CLK_END\t\t5\n+#define ATH79_CLK_END\t\t6\n \n #endif /* __DT_BINDINGS_ATH79_CLK_H */\n"
  },
  {
    "path": "target/linux/ath79/patches-5.10/004-register_gpio_driver_earlier.patch",
    "content": "HACK: register the GPIO driver earlier to ensure that gpio_request calls\nfrom mach files succeed.\n\n--- a/drivers/gpio/gpio-ath79.c\n+++ b/drivers/gpio/gpio-ath79.c\n@@ -306,7 +306,11 @@ static struct platform_driver ath79_gpio\n \t.probe = ath79_gpio_probe,\n };\n \n-module_platform_driver(ath79_gpio_driver);\n+static int __init ath79_gpio_init(void)\n+{\n+\treturn platform_driver_register(&ath79_gpio_driver);\n+}\n+postcore_initcall(ath79_gpio_init);\n \n MODULE_DESCRIPTION(\"Atheros AR71XX/AR724X/AR913X GPIO API support\");\n MODULE_LICENSE(\"GPL v2\");\n"
  },
  {
    "path": "target/linux/ath79/patches-5.10/0040-ath79-sgmii-config.patch",
    "content": "--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h\n+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h\n@@ -1376,5 +1376,6 @@\n \n #define QCA956X_SGMII_CONFIG_MODE_CTRL_SHIFT\t0\n #define QCA956X_SGMII_CONFIG_MODE_CTRL_MASK\t0x7\n+#define QCA956X_SGMII_CONFIG_MODE_CTRL_SGMII_MAC\t0x2\n \n #endif /* __ASM_MACH_AR71XX_REGS_H */\n"
  },
  {
    "path": "target/linux/ath79/patches-5.10/0052-mtd-spi-nor-use-4-bit-locking-for-MX25L12805D.patch",
    "content": "From a449cd03db4d0e1d292b3734f7676634cfd94f53 Mon Sep 17 00:00:00 2001\nFrom: David Bauer <mail@david-bauer.net>\nDate: Sun, 25 Oct 2020 01:14:22 +0200\nSubject: [PATCH] mtd: spi-nor: use 4 bit locking for MX25L12805D\n\nMacronix MX25L12805D supports locking with 4 block\nprotection bits in its status register. Add the corresponding\nflag in order to clear these bits when unloking the flash.\n\nOtherwise, the flash might not be writable depending on the state\nleft by the bootloader.\n\nTested-on: Ubiquiti UniFi AC Lite (ath79)\n\nFixes commit 62593cf40b23 (\"mtd: spi-nor: refactor block protection functions\")\n\nSigned-off-by: David Bauer <mail@david-bauer.net>\n---\n drivers/mtd/spi-nor/macronix.c | 3 ++-\n 1 file changed, 2 insertions(+), 1 deletion(-)\n\n--- a/drivers/mtd/spi-nor/macronix.c\n+++ b/drivers/mtd/spi-nor/macronix.c\n@@ -51,7 +51,8 @@ static const struct flash_info macronix_\n \t{ \"mx25u4035\",   INFO(0xc22533, 0, 64 * 1024,   8, SECT_4K) },\n \t{ \"mx25u8035\",   INFO(0xc22534, 0, 64 * 1024,  16, SECT_4K) },\n \t{ \"mx25u6435f\",  INFO(0xc22537, 0, 64 * 1024, 128, SECT_4K) },\n-\t{ \"mx25l12805d\", INFO(0xc22018, 0, 64 * 1024, 256, SECT_4K) },\n+\t{ \"mx25l12805d\", INFO(0xc22018, 0, 64 * 1024, 256, SECT_4K |\n+\t\t\t      SPI_NOR_HAS_LOCK | SPI_NOR_4BIT_BP) },\n \t{ \"mx25l12855e\", INFO(0xc22618, 0, 64 * 1024, 256, 0) },\n \t{ \"mx25r1635f\",  INFO(0xc22815, 0, 64 * 1024,  32,\n \t\t\t      SECT_4K | SPI_NOR_DUAL_READ |\n"
  },
  {
    "path": "target/linux/ath79/patches-5.10/0062-MIPS-pci-ar724x-add-QCA9550-reset-sequence.patch",
    "content": "From: David Bauer <mail@david-bauer.net>\nDate: Sat, 11 Apr 2020 14:03:12 +0200\nSubject: MIPS: pci-ar724x: add QCA9550 reset sequence\n\nThe QCA9550 family of SoCs have a slightly different reset\nsequence compared to older chips.\n\nNormally the bootloader performs this sequence, however\nsome bootloader implementation expect the operating system\nto clear the reset.\n\nAlso get the resets from OF to support handling of the second\nPCIe root-complex on the QCA9558.\n\nSigned-off-by: David Bauer <mail@david-bauer.net>\n\n--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h\n+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h\n@@ -391,6 +391,7 @@\n #define QCA955X_PLL_CPU_CONFIG_REG\t\t0x00\n #define QCA955X_PLL_DDR_CONFIG_REG\t\t0x04\n #define QCA955X_PLL_CLK_CTRL_REG\t\t0x08\n+#define QCA955X_PLL_PCIE_CONFIG_REG\t\t0x0c\n #define QCA955X_PLL_ETH_XMII_CONTROL_REG\t0x28\n #define QCA955X_PLL_ETH_SGMII_CONTROL_REG\t0x48\n #define QCA955X_PLL_ETH_SGMII_SERDES_REG\t0x4c\n@@ -476,6 +477,9 @@\n #define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_CPUPLL\tBIT(21)\n #define QCA956X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL\t\tBIT(24)\n \n+#define QCA955X_PLL_PCIE_CONFIG_PLL_PWD\t\t\tBIT(30)\n+#define QCA955X_PLL_PCIE_CONFIG_PLL_BYPASS\t\tBIT(16)\n+\n #define QCA956X_PLL_SWITCH_CLOCK_SPARE_I2C_CLK_SELB\t\tBIT(5)\n #define QCA956X_PLL_SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_1\t\tBIT(6)\n #define QCA956X_PLL_SWITCH_CLOCK_SPARE_UART1_CLK_SEL\t\tBIT(7)\n--- a/arch/mips/pci/pci-ar724x.c\n+++ b/arch/mips/pci/pci-ar724x.c\n@@ -8,6 +8,7 @@\n \n #include <linux/irq.h>\n #include <linux/pci.h>\n+#include <linux/reset.h>\n #include <linux/init.h>\n #include <linux/delay.h>\n #include <linux/platform_device.h>\n@@ -55,6 +56,9 @@ struct ar724x_pci_controller {\n \tstruct irq_domain *domain;\n \tstruct resource io_res;\n \tstruct resource mem_res;\n+\n+\tstruct reset_control *hc_reset;\n+\tstruct reset_control *phy_reset;\n };\n \n static struct irq_chip ar724x_pci_irq_chip;\n@@ -340,18 +344,30 @@ static void ar724x_pci_hw_init(struct ar\n \tint wait = 0;\n \n \t/* deassert PCIe host controller and PCIe PHY reset */\n-\tath79_device_reset_clear(AR724X_RESET_PCIE);\n-\tath79_device_reset_clear(AR724X_RESET_PCIE_PHY);\n+\treset_control_deassert(apc->hc_reset);\n+\treset_control_deassert(apc->phy_reset);\n \n-\t/* remove the reset of the PCIE PLL */\n-\tppl = ath79_pll_rr(AR724X_PLL_REG_PCIE_CONFIG);\n-\tppl &= ~AR724X_PLL_REG_PCIE_CONFIG_PPL_RESET;\n-\tath79_pll_wr(AR724X_PLL_REG_PCIE_CONFIG, ppl);\n-\n-\t/* deassert bypass for the PCIE PLL */\n-\tppl = ath79_pll_rr(AR724X_PLL_REG_PCIE_CONFIG);\n-\tppl &= ~AR724X_PLL_REG_PCIE_CONFIG_PPL_BYPASS;\n-\tath79_pll_wr(AR724X_PLL_REG_PCIE_CONFIG, ppl);\n+\tif (of_device_is_compatible(apc->np, \"qcom,qca9550-pci\")) {\n+\t\t/* remove the reset of the PCIE PLL */\n+\t\tppl = ath79_pll_rr(QCA955X_PLL_PCIE_CONFIG_REG);\n+\t\tppl &= ~QCA955X_PLL_PCIE_CONFIG_PLL_PWD;\n+\t\tath79_pll_wr(QCA955X_PLL_PCIE_CONFIG_REG, ppl);\n+\n+\t\t/* deassert bypass for the PCIE PLL */\n+\t\tppl = ath79_pll_rr(QCA955X_PLL_PCIE_CONFIG_REG);\n+\t\tppl &= ~QCA955X_PLL_PCIE_CONFIG_PLL_BYPASS;\n+\t\tath79_pll_wr(QCA955X_PLL_PCIE_CONFIG_REG, ppl);\n+\t} else {\n+\t\t/* remove the reset of the PCIE PLL */\n+\t\tppl = ath79_pll_rr(AR724X_PLL_REG_PCIE_CONFIG);\n+\t\tppl &= ~AR724X_PLL_REG_PCIE_CONFIG_PPL_RESET;\n+\t\tath79_pll_wr(AR724X_PLL_REG_PCIE_CONFIG, ppl);\n+\n+\t\t/* deassert bypass for the PCIE PLL */\n+\t\tppl = ath79_pll_rr(AR724X_PLL_REG_PCIE_CONFIG);\n+\t\tppl &= ~AR724X_PLL_REG_PCIE_CONFIG_PPL_BYPASS;\n+\t\tath79_pll_wr(AR724X_PLL_REG_PCIE_CONFIG, ppl);\n+\t}\n \n \t/* set PCIE Application Control to ready */\n \tapp = __raw_readl(apc->ctrl_base + AR724X_PCI_REG_APP);\n@@ -396,6 +412,14 @@ static int ar724x_pci_probe(struct platf\n \tif (apc->irq < 0)\n \t\treturn -EINVAL;\n \n+\tapc->hc_reset = devm_reset_control_get_exclusive(&pdev->dev, \"hc\");\n+\tif (IS_ERR(apc->hc_reset))\n+\t\treturn PTR_ERR(apc->hc_reset);\n+\n+\tapc->phy_reset = devm_reset_control_get_exclusive(&pdev->dev, \"phy\");\n+\tif (IS_ERR(apc->phy_reset))\n+\t\treturn PTR_ERR(apc->phy_reset);\n+\n \tapc->np = pdev->dev.of_node;\n \tapc->pci_controller.pci_ops = &ar724x_pci_ops;\n \tapc->pci_controller.io_resource = &apc->io_res;\n@@ -406,7 +430,7 @@ static int ar724x_pci_probe(struct platf\n \t * Do the full PCIE Root Complex Initialization Sequence if the PCIe\n \t * host controller is in reset.\n \t */\n-\tif (ath79_reset_rr(AR724X_RESET_REG_RESET_MODULE) & AR724X_RESET_PCIE)\n+\tif (reset_control_status(apc->hc_reset))\n \t\tar724x_pci_hw_init(apc);\n \n \tapc->link_up = ar724x_pci_check_link(apc);\n@@ -424,6 +448,7 @@ static int ar724x_pci_probe(struct platf\n \n static const struct of_device_id ar724x_pci_ids[] = {\n \t{ .compatible = \"qcom,ar7240-pci\" },\n+\t{ .compatible = \"qcom,qca9550-pci\" },\n \t{},\n };\n \n"
  },
  {
    "path": "target/linux/ath79/patches-5.10/401-mtd-nor-support-mtd-name-from-device-tree.patch",
    "content": "From f32bc2aa01edcba2f2ed5db151cf183eac9ef919 Mon Sep 17 00:00:00 2001\nFrom: Abhimanyu Vishwakarma <Abhimanyu.Vishwakarma@imgtec.com>\nDate: Sat, 25 Feb 2017 16:42:50 +0000\nSubject: mtd: nor: support mtd name from device tree\n\nSigned-off-by: Abhimanyu Vishwakarma <Abhimanyu.Vishwakarma@imgtec.com>\n---\n drivers/mtd/spi-nor/spi-nor.c | 8 +++++++-\n 1 file changed, 7 insertions(+), 1 deletion(-)\n\n--- a/drivers/mtd/spi-nor/core.c\n+++ b/drivers/mtd/spi-nor/core.c\n@@ -3147,6 +3147,7 @@ int spi_nor_scan(struct spi_nor *nor, co\n \tstruct device *dev = nor->dev;\n \tstruct mtd_info *mtd = &nor->mtd;\n \tstruct device_node *np = spi_nor_get_flash_node(nor);\n+\tconst char __maybe_unused *of_mtd_name = NULL;\n \tint ret;\n \tint i;\n \n@@ -3201,7 +3202,12 @@ int spi_nor_scan(struct spi_nor *nor, co\n \tif (ret)\n \t\treturn ret;\n \n-\tif (!mtd->name)\n+#ifdef CONFIG_MTD_OF_PARTS\n+\tof_property_read_string(np, \"linux,mtd-name\", &of_mtd_name);\n+#endif\n+\tif (of_mtd_name)\n+\t\tmtd->name = of_mtd_name;\n+\telse if (!mtd->name)\n \t\tmtd->name = dev_name(dev);\n \tmtd->priv = nor;\n \tmtd->type = MTD_NORFLASH;\n--- a/drivers/mtd/mtdcore.c\n+++ b/drivers/mtd/mtdcore.c\n@@ -778,6 +778,17 @@ out_error:\n  */\n static void mtd_set_dev_defaults(struct mtd_info *mtd)\n {\n+#ifdef CONFIG_MTD_OF_PARTS\n+\tconst char __maybe_unused *of_mtd_name = NULL;\n+\tstruct device_node *np;\n+\n+\tnp = mtd_get_of_node(mtd);\n+\tif (np && !mtd->name) {\n+\t\tof_property_read_string(np, \"linux,mtd-name\", &of_mtd_name);\n+\t\tif (of_mtd_name)\n+\t\t\tmtd->name = of_mtd_name;\n+\t} else\n+#endif\n \tif (mtd->dev.parent) {\n \t\tif (!mtd->owner && mtd->dev.parent->driver)\n \t\t\tmtd->owner = mtd->dev.parent->driver->owner;\n"
  },
  {
    "path": "target/linux/ath79/patches-5.10/402-v5.17-spi-ar934x-fix-transfer-and-word-delays.patch",
    "content": "From c70282457c380db7deb57c81a6894debc8f88efa Mon Sep 17 00:00:00 2001\nFrom: Oskari Lemmela <oskari@lemmela.net>\nDate: Wed, 22 Dec 2021 07:59:58 +0200\nSubject: [PATCH] spi: ar934x: fix transfer and word delays\n\nAdd missing delay between transferred messages and words.\n\nSigned-off-by: Oskari Lemmela <oskari@lemmela.net>\nLink: https://lore.kernel.org/r/20211222055958.1383233-3-oskari@lemmela.net\nSigned-off-by: Mark Brown <broonie@kernel.org>\n---\n drivers/spi/spi-ar934x.c | 2 ++\n 1 file changed, 2 insertions(+)\n\n--- a/drivers/spi/spi-ar934x.c\n+++ b/drivers/spi/spi-ar934x.c\n@@ -137,8 +137,10 @@ static int ar934x_spi_transfer_one_messa\n \t\t\t\t\treg >>= 8;\n \t\t\t\t}\n \t\t\t}\n+\t\t\tspi_delay_exec(&t->word_delay, t);\n \t\t}\n \t\tm->actual_length += t->len;\n+\t\tspi_transfer_delay_exec(t);\n \t}\n \n msg_done:\n"
  },
  {
    "path": "target/linux/ath79/patches-5.10/403-v5.17-spi-ar934x-fix-transfer-size.patch",
    "content": "From ebe33e5a98dcf14a9630845f3f10c193584ac054 Mon Sep 17 00:00:00 2001\nFrom: Oskari Lemmela <oskari@lemmela.net>\nDate: Wed, 22 Dec 2021 07:59:57 +0200\nSubject: [PATCH] spi: ar934x: fix transfer size\n\nIf bits_per_word is configured, transfer only word amount\nof data per iteration.\n\nSigned-off-by: Oskari Lemmela <oskari@lemmela.net>\nLink: https://lore.kernel.org/r/20211222055958.1383233-2-oskari@lemmela.net\nSigned-off-by: Mark Brown <broonie@kernel.org>\n---\n drivers/spi/spi-ar934x.c | 16 +++++++++++-----\n 1 file changed, 11 insertions(+), 5 deletions(-)\n\n--- a/drivers/spi/spi-ar934x.c\n+++ b/drivers/spi/spi-ar934x.c\n@@ -82,7 +82,7 @@ static int ar934x_spi_transfer_one_messa\n \tstruct spi_device *spi = m->spi;\n \tunsigned long trx_done, trx_cur;\n \tint stat = 0;\n-\tu8 term = 0;\n+\tu8 bpw, term = 0;\n \tint div, i;\n \tu32 reg;\n \tconst u8 *tx_buf;\n@@ -90,6 +90,11 @@ static int ar934x_spi_transfer_one_messa\n \n \tm->actual_length = 0;\n \tlist_for_each_entry(t, &m->transfers, transfer_list) {\n+\t\tif (t->bits_per_word >= 8 && t->bits_per_word < 32)\n+\t\t\tbpw = t->bits_per_word >> 3;\n+\t\telse\n+\t\t\tbpw = 4;\n+\n \t\tif (t->speed_hz)\n \t\t\tdiv = ar934x_spi_clk_div(sp, t->speed_hz);\n \t\telse\n@@ -105,10 +110,10 @@ static int ar934x_spi_transfer_one_messa\n \t\tiowrite32(reg, sp->base + AR934X_SPI_REG_CTRL);\n \t\tiowrite32(0, sp->base + AR934X_SPI_DATAOUT);\n \n-\t\tfor (trx_done = 0; trx_done < t->len; trx_done += 4) {\n+\t\tfor (trx_done = 0; trx_done < t->len; trx_done += bpw) {\n \t\t\ttrx_cur = t->len - trx_done;\n-\t\t\tif (trx_cur > 4)\n-\t\t\t\ttrx_cur = 4;\n+\t\t\tif (trx_cur > bpw)\n+\t\t\t\ttrx_cur = bpw;\n \t\t\telse if (list_is_last(&t->transfer_list, &m->transfers))\n \t\t\t\tterm = 1;\n \n@@ -193,7 +198,8 @@ static int ar934x_spi_probe(struct platf\n \tctlr->mode_bits = SPI_LSB_FIRST;\n \tctlr->setup = ar934x_spi_setup;\n \tctlr->transfer_one_message = ar934x_spi_transfer_one_message;\n-\tctlr->bits_per_word_mask = SPI_BPW_MASK(8);\n+\tctlr->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(24) |\n+\t\t\t\t   SPI_BPW_MASK(16) | SPI_BPW_MASK(8);\n \tctlr->dev.of_node = pdev->dev.of_node;\n \tctlr->num_chipselect = 3;\n \n"
  },
  {
    "path": "target/linux/ath79/patches-5.10/404-mtd-cybertan-trx-parser.patch",
    "content": "--- a/drivers/mtd/parsers/Makefile\n+++ b/drivers/mtd/parsers/Makefile\n@@ -8,6 +8,7 @@ obj-$(CONFIG_MTD_OF_PARTS)\t\t+= ofpart.o\n ofpart-y\t\t\t\t+= ofpart_core.o\n ofpart-$(CONFIG_MTD_OF_PARTS_BCM4908)\t+= ofpart_bcm4908.o\n ofpart-$(CONFIG_MTD_OF_PARTS_LINKSYS_NS)+= ofpart_linksys_ns.o\n+obj-$(CONFIG_MTD_PARSER_CYBERTAN)\t+= parser_cybertan.o\n obj-$(CONFIG_MTD_PARSER_IMAGETAG)\t+= parser_imagetag.o\n obj-$(CONFIG_MTD_AFS_PARTS)\t\t+= afs.o\n obj-$(CONFIG_MTD_PARSER_TRX)\t\t+= parser_trx.o\n--- a/drivers/mtd/parsers/Kconfig\n+++ b/drivers/mtd/parsers/Kconfig\n@@ -102,6 +102,14 @@ config MTD_OF_PARTS_LINKSYS_NS\n \t  two \"firmware\" partitions. Currently used firmware has to be detected\n \t  using CFE environment variable.\n \n+config MTD_PARSER_CYBERTAN\n+\ttristate \"Parser for Cybertan format partitions\"\n+\tdepends on MTD && (ATH79 || COMPILE_TEST)\n+\thelp\n+\t  Cybertan has a proprietory header than encompasses a Broadcom trx\n+\t  header. This driver will parse the header and take care of the\n+\t  special offsets that result in the extra headers.\n+\n config MTD_PARSER_IMAGETAG\n \ttristate \"Parser for BCM963XX Image Tag format partitions\"\n \tdepends on BCM63XX || BMIPS_GENERIC || COMPILE_TEST\n"
  },
  {
    "path": "target/linux/ath79/patches-5.10/408-mtd-redboot_partition_scan.patch",
    "content": "--- a/drivers/mtd/parsers/redboot.c\n+++ b/drivers/mtd/parsers/redboot.c\n@@ -90,12 +90,18 @@ static int parse_redboot_partitions(stru\n \n \tparse_redboot_of(master);\n \n+\tbuf = vmalloc(master->erasesize);\n+\tif (!buf)\n+\t\treturn -ENOMEM;\n+\n+ restart:\n \tif ( directory < 0 ) {\n \t\toffset = master->size + directory * master->erasesize;\n \t\twhile (mtd_block_isbad(master, offset)) {\n \t\t\tif (!offset) {\n \t\t\tnogood:\n \t\t\t\tprintk(KERN_NOTICE \"Failed to find a non-bad block to check for RedBoot partition table\\n\");\n+\t\t\t\tvfree(buf);\n \t\t\t\treturn -EIO;\n \t\t\t}\n \t\t\toffset -= master->erasesize;\n@@ -108,10 +114,6 @@ static int parse_redboot_partitions(stru\n \t\t\t\tgoto nogood;\n \t\t}\n \t}\n-\tbuf = vmalloc(master->erasesize);\n-\n-\tif (!buf)\n-\t\treturn -ENOMEM;\n \n \tprintk(KERN_NOTICE \"Searching for RedBoot partition table in %s at offset 0x%lx\\n\",\n \t       master->name, offset);\n@@ -184,6 +186,11 @@ static int parse_redboot_partitions(stru\n \t}\n \tif (i == numslots) {\n \t\t/* Didn't find it */\n+\t\tif (offset + master->erasesize < master->size) {\n+\t\t\t/* not at the end of the flash yet, maybe next block :) */\n+\t\t\tdirectory++;\n+\t\t\tgoto restart;\n+\t\t}\n \t\tprintk(KERN_NOTICE \"No RedBoot partition table detected in %s\\n\",\n \t\t       master->name);\n \t\tret = 0;\n"
  },
  {
    "path": "target/linux/ath79/patches-5.10/410-spi-ath79-Implement-the-spi_mem-interface.patch",
    "content": "From 8d8cdb4a6ccee5b62cc0dc64651c3946364514dc Mon Sep 17 00:00:00 2001\nFrom: Luiz Angelo Daros de Luca <luizluca@gmail.com>\nDate: Mon, 10 Feb 2020 16:11:27 -0300\nSubject: [PATCH] spi: ath79: Implement the spi_mem interface\n\nSigned-off-by: Luiz Angelo Daros de Luca <luizluca@gmail.com>\n---\n drivers/spi/spi-ath79.c | 35 +++++++++++++++++++++++++++++++++++\n 1 file changed, 35 insertions(+)\n\n--- a/drivers/spi/spi-ath79.c\n+++ b/drivers/spi/spi-ath79.c\n@@ -15,6 +15,7 @@\n #include <linux/platform_device.h>\n #include <linux/io.h>\n #include <linux/spi/spi.h>\n+#include <linux/spi/spi-mem.h>\n #include <linux/spi/spi_bitbang.h>\n #include <linux/bitops.h>\n #include <linux/clk.h>\n@@ -133,6 +134,39 @@ static u32 ath79_spi_txrx_mode0(struct s\n \treturn ath79_spi_rr(sp, AR71XX_SPI_REG_RDS);\n }\n \n+static int ath79_exec_mem_op(struct spi_mem *mem,\n+                              const struct spi_mem_op *op)\n+{\n+\tstruct ath79_spi *sp = ath79_spidev_to_sp(mem->spi);\n+\n+\t/* Ensures that reading is performed on device connected\n+\t   to hardware cs0 */\n+\tif (mem->spi->chip_select || mem->spi->cs_gpiod)\n+\t\treturn -ENOTSUPP;\n+\n+\t/* Only use for fast-read op. */\n+\tif (op->cmd.opcode != 0x0b || op->data.dir != SPI_MEM_DATA_IN ||\n+\t    op->addr.nbytes != 3 || op->dummy.nbytes != 1)\n+\t\treturn -ENOTSUPP;\n+\n+\t/* disable GPIO mode */\n+\tath79_spi_wr(sp, AR71XX_SPI_REG_FS, 0);\n+\n+\tmemcpy_fromio(op->data.buf.in, sp->base + op->addr.val, op->data.nbytes);\n+\n+\t/* enable GPIO mode */\n+\tath79_spi_wr(sp, AR71XX_SPI_REG_FS, AR71XX_SPI_FS_GPIO);\n+\n+\t/* restore IOC register */\n+\tath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);\n+\n+\treturn 0;\n+}\n+\n+static const struct spi_controller_mem_ops ath79_mem_ops = {\n+\t.exec_op = ath79_exec_mem_op,\n+};\n+\n static int ath79_spi_probe(struct platform_device *pdev)\n {\n \tstruct spi_master *master;\n@@ -164,6 +198,7 @@ static int ath79_spi_probe(struct platfo\n \t\tret = PTR_ERR(sp->base);\n \t\tgoto err_put_master;\n \t}\n+\tmaster->mem_ops = &ath79_mem_ops;\n \n \tsp->clk = devm_clk_get(&pdev->dev, \"ahb\");\n \tif (IS_ERR(sp->clk)) {\n"
  },
  {
    "path": "target/linux/ath79/patches-5.10/412-spi-ath79-set-number-of-chipselect-lines.patch",
    "content": "From e2e9f6d9f9bd7449ff113c157b639ce1a24b9d3f Mon Sep 17 00:00:00 2001\nFrom: David Bauer <mail@david-bauer.net>\nDate: Sat, 24 Apr 2021 16:14:48 +0200\nSubject: [PATCH 2/2] spi: ath79: set number of chipselect lines\n\nAll chipsets from AR7100 up to QCA9563 have three dedicated chipselect\nlines for the integrated SPI controller. Remove the number of\nchipselects from the platform data, as there is no need to manually set\nthis to a different value.\n\nSigned-off-by: David Bauer <mail@david-bauer.net>\n---\n drivers/spi/spi-ath79.c                 | 2 +-\n include/linux/platform_data/spi-ath79.h | 1 -\n 2 files changed, 1 insertion(+), 2 deletions(-)\n\n--- a/drivers/spi/spi-ath79.c\n+++ b/drivers/spi/spi-ath79.c\n@@ -187,6 +187,7 @@ static int ath79_spi_probe(struct platfo\n \tmaster->use_gpio_descriptors = true;\n \tmaster->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32);\n \tmaster->flags = SPI_MASTER_GPIO_SS;\n+\tmaster->num_chipselect = 3;\n \n \tsp->bitbang.master = master;\n \tsp->bitbang.chipselect = ath79_spi_chipselect;\n"
  },
  {
    "path": "target/linux/ath79/patches-5.10/420-net-use-downstream-ag71xx.patch",
    "content": "--- a/drivers/net/ethernet/atheros/Kconfig\n+++ b/drivers/net/ethernet/atheros/Kconfig\n@@ -17,13 +17,7 @@ config NET_VENDOR_ATHEROS\n \n if NET_VENDOR_ATHEROS\n \n-config AG71XX\n-\ttristate \"Atheros AR7XXX/AR9XXX built-in ethernet mac support\"\n-\tdepends on ATH79\n-\tselect PHYLINK\n-\thelp\n-\t  If you wish to compile a kernel for AR7XXX/91XXX and enable\n-\t  ethernet support, then you should always answer Y to this.\n+source \"drivers/net/ethernet/atheros/ag71xx/Kconfig\"\n \n config ATL2\n \ttristate \"Atheros L2 Fast Ethernet support\"\n--- a/drivers/net/ethernet/atheros/Makefile\n+++ b/drivers/net/ethernet/atheros/Makefile\n@@ -3,7 +3,7 @@\n # Makefile for the Atheros network device drivers.\n #\n \n-obj-$(CONFIG_AG71XX) += ag71xx.o\n+obj-$(CONFIG_AG71XX) += ag71xx/\n obj-$(CONFIG_ATL1) += atlx/\n obj-$(CONFIG_ATL2) += atlx/\n obj-$(CONFIG_ATL1E) += atl1e/\n"
  },
  {
    "path": "target/linux/ath79/patches-5.10/425-at803x-allow-sgmii-aneg-override.patch",
    "content": "--- a/drivers/net/phy/at803x.c\n+++ b/drivers/net/phy/at803x.c\n@@ -830,6 +830,13 @@ static int at803x_aneg_done(struct phy_d\n \tif (!(phy_read(phydev, AT803X_PSSR) & AT803X_PSSR_MR_AN_COMPLETE)) {\n \t\tphydev_warn(phydev, \"803x_aneg_done: SGMII link is not ok\\n\");\n \t\taneg_done = 0;\n+#ifdef CONFIG_OF_MDIO\n+\t\tif (phydev->mdio.dev.of_node &&\n+\t\t\t\tof_property_read_bool(phydev->mdio.dev.of_node,\n+\t\t\t\t\"at803x-override-sgmii-link-check\")) {\n+\t\t\taneg_done = 1;\n+\t\t}\n+#endif\n \t}\n \t/* switch back to copper page */\n \tphy_write(phydev, AT803X_REG_CHIP_CONFIG, ccr | AT803X_BT_BX_REG_SEL);\n"
  },
  {
    "path": "target/linux/ath79/patches-5.10/430-drivers-link-spi-before-mtd.patch",
    "content": "--- a/drivers/Makefile\n+++ b/drivers/Makefile\n@@ -81,8 +81,8 @@ obj-y\t\t\t\t+= scsi/\n obj-y\t\t\t\t+= nvme/\n obj-$(CONFIG_ATA)\t\t+= ata/\n obj-$(CONFIG_TARGET_CORE)\t+= target/\n-obj-$(CONFIG_MTD)\t\t+= mtd/\n obj-$(CONFIG_SPI)\t\t+= spi/\n+obj-$(CONFIG_MTD)\t\t+= mtd/\n obj-$(CONFIG_SPMI)\t\t+= spmi/\n obj-$(CONFIG_HSI)\t\t+= hsi/\n obj-$(CONFIG_SLIMBUS)\t\t+= slimbus/\n"
  },
  {
    "path": "target/linux/ath79/patches-5.10/440-mtd-ar934x-nand-driver.patch",
    "content": "--- a/drivers/mtd/nand/raw/Kconfig\n+++ b/drivers/mtd/nand/raw/Kconfig\n@@ -556,4 +556,12 @@ config MTD_NAND_DISKONCHIP_BBTWRITE\n \t  load time (assuming you build diskonchip as a module) with the module\n \t  parameter \"inftl_bbt_write=1\".\n \n+config MTD_NAND_AR934X\n+\ttristate \"Support for NAND controller on Qualcomm Atheros AR934x/QCA955x SoCs\"\n+\tdepends on ATH79 || COMPILE_TEST\n+\tdepends on HAS_IOMEM\n+\thelp\n+\t  Enables support for NAND controller on Qualcomm Atheros SoCs.\n+\t  This controller is found on AR934x and QCA955x SoCs.\n+\n endif # MTD_RAW_NAND\n--- a/drivers/mtd/nand/raw/Makefile\n+++ b/drivers/mtd/nand/raw/Makefile\n@@ -58,6 +58,7 @@ obj-$(CONFIG_MTD_NAND_STM32_FMC2)\t+= stm\n obj-$(CONFIG_MTD_NAND_MESON)\t\t+= meson_nand.o\n obj-$(CONFIG_MTD_NAND_CADENCE)\t\t+= cadence-nand-controller.o\n obj-$(CONFIG_MTD_NAND_ARASAN)\t\t+= arasan-nand-controller.o\n+obj-$(CONFIG_MTD_NAND_AR934X)\t\t+= ar934x_nand.o\n \n nand-objs := nand_base.o nand_legacy.o nand_bbt.o nand_timings.o nand_ids.o\n nand-objs += nand_onfi.o\n"
  },
  {
    "path": "target/linux/ath79/patches-5.10/470-MIPS-ath79-swizzle-pci-address-for-ar71xx.patch",
    "content": "--- /dev/null\n+++ b/arch/mips/include/asm/mach-ath79/mangle-port.h\n@@ -0,0 +1,37 @@\n+/*\n+ *  Copyright (C) 2012 Gabor Juhos <juhosg@openwrt.org>\n+ *\n+ *  This file was derived from: inlude/asm-mips/mach-generic/mangle-port.h\n+ *      Copyright (C) 2003, 2004 Ralf Baechle\n+ *\n+ *  This program is free software; you can redistribute it and/or modify it\n+ *  under the terms of the GNU General Public License version 2 as published\n+ *  by the Free Software Foundation.\n+ */\n+\n+#ifndef __ASM_MACH_ATH79_MANGLE_PORT_H\n+#define __ASM_MACH_ATH79_MANGLE_PORT_H\n+\n+#ifdef CONFIG_PCI_AR71XX\n+extern unsigned long (ath79_pci_swizzle_b)(unsigned long port);\n+extern unsigned long (ath79_pci_swizzle_w)(unsigned long port);\n+#else\n+#define ath79_pci_swizzle_b(port) (port)\n+#define ath79_pci_swizzle_w(port) (port)\n+#endif\n+\n+#define __swizzle_addr_b(port)\tath79_pci_swizzle_b(port)\n+#define __swizzle_addr_w(port)\tath79_pci_swizzle_w(port)\n+#define __swizzle_addr_l(port)\t(port)\n+#define __swizzle_addr_q(port)\t(port)\n+\n+# define ioswabb(a, x)           (x)\n+# define __mem_ioswabb(a, x)     (x)\n+# define ioswabw(a, x)           (x)\n+# define __mem_ioswabw(a, x)     cpu_to_le16(x)\n+# define ioswabl(a, x)           (x)\n+# define __mem_ioswabl(a, x)     cpu_to_le32(x)\n+# define ioswabq(a, x)           (x)\n+# define __mem_ioswabq(a, x)     cpu_to_le64(x)\n+\n+#endif /* __ASM_MACH_ATH79_MANGLE_PORT_H */\n--- a/arch/mips/pci/pci-ar71xx.c\n+++ b/arch/mips/pci/pci-ar71xx.c\n@@ -68,6 +68,45 @@ static const u32 ar71xx_pci_read_mask[8]\n \t0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0\n };\n \n+static unsigned long (*__ath79_pci_swizzle_b)(unsigned long port);\n+static unsigned long (*__ath79_pci_swizzle_w)(unsigned long port);\n+\n+static inline bool ar71xx_is_pci_addr(unsigned long port)\n+{\n+\tunsigned long phys = CPHYSADDR(port);\n+\n+\treturn (phys >= AR71XX_PCI_MEM_BASE &&\n+\t\tphys < AR71XX_PCI_MEM_BASE + AR71XX_PCI_MEM_SIZE);\n+}\n+\n+static unsigned long ar71xx_pci_swizzle_b(unsigned long port)\n+{\n+\treturn ar71xx_is_pci_addr(port) ? port ^ 3 : port;\n+}\n+\n+static unsigned long ar71xx_pci_swizzle_w(unsigned long port)\n+{\n+\treturn ar71xx_is_pci_addr(port) ? port ^ 2 : port;\n+}\n+\n+unsigned long ath79_pci_swizzle_b(unsigned long port)\n+{\n+\tif (__ath79_pci_swizzle_b)\n+\t\treturn __ath79_pci_swizzle_b(port);\n+\n+\treturn port;\n+}\n+EXPORT_SYMBOL(ath79_pci_swizzle_b);\n+\n+unsigned long ath79_pci_swizzle_w(unsigned long port)\n+{\n+\tif (__ath79_pci_swizzle_w)\n+\t\treturn __ath79_pci_swizzle_w(port);\n+\n+\treturn port;\n+}\n+EXPORT_SYMBOL(ath79_pci_swizzle_w);\n+\n static inline u32 ar71xx_pci_get_ble(int where, int size, int local)\n {\n \tu32 t;\n@@ -276,6 +315,9 @@ static int ar71xx_pci_probe(struct platf\n \n \tregister_pci_controller(&apc->pci_ctrl);\n \n+\t__ath79_pci_swizzle_b = ar71xx_pci_swizzle_b;\n+\t__ath79_pci_swizzle_w = ar71xx_pci_swizzle_w;\n+\n \treturn 0;\n }\n \n"
  },
  {
    "path": "target/linux/ath79/patches-5.10/600-of_net-add-mac-address-ascii-support.patch",
    "content": "--- a/net/ethernet/eth.c\n+++ b/net/ethernet/eth.c\n@@ -545,6 +545,63 @@ int eth_platform_get_mac_address(struct\n }\n EXPORT_SYMBOL(eth_platform_get_mac_address);\n \n+static void *nvmem_cell_get_mac_address(struct nvmem_cell *cell)\n+{\n+\tsize_t len;\n+\tvoid *mac;\n+\n+\tmac = nvmem_cell_read(cell, &len);\n+\tif (IS_ERR(mac))\n+\t\treturn PTR_ERR(mac);\n+\tif (len != ETH_ALEN) {\n+\t\tkfree(mac);\n+\t\treturn ERR_PTR(-EINVAL);\n+\t}\n+\treturn mac;\n+}\n+\n+static void *nvmem_cell_get_mac_address_ascii(struct nvmem_cell *cell)\n+{\n+\tsize_t len;\n+\tint ret;\n+\tvoid *mac_ascii;\n+\tu8 *mac;\n+\n+\tmac_ascii = nvmem_cell_read(cell, &len);\n+\tif (IS_ERR(mac_ascii))\n+\t\treturn PTR_ERR(mac_ascii);\n+\tif (len != ETH_ALEN*2+5) {\n+\t\tkfree(mac_ascii);\n+\t\treturn ERR_PTR(-EINVAL);\n+\t}\n+\tmac = kmalloc(ETH_ALEN, GFP_KERNEL);\n+\tif (!mac) {\n+\t\tkfree(mac_ascii);\n+\t\treturn ERR_PTR(-ENOMEM);\n+\t}\n+\tret = sscanf(mac_ascii, \"%2hhx:%2hhx:%2hhx:%2hhx:%2hhx:%2hhx\",\n+\t\t\t\t&mac[0], &mac[1], &mac[2],\n+\t\t\t\t&mac[3], &mac[4], &mac[5]);\n+\tkfree(mac_ascii);\n+\tif (ret == ETH_ALEN)\n+\t\treturn mac;\n+\tkfree(mac);\n+\treturn ERR_PTR(-EINVAL);\n+}\n+\n+static struct nvmem_cell_mac_address_property {\n+\tchar *name;\n+\tvoid *(*read)(struct nvmem_cell *);\n+} nvmem_cell_mac_address_properties[] = {\n+\t{\n+\t\t.name = \"mac-address\",\n+\t\t.read = nvmem_cell_get_mac_address,\n+\t}, {\n+\t\t.name = \"mac-address-ascii\",\n+\t\t.read = nvmem_cell_get_mac_address_ascii,\n+\t},\n+};\n+\n /**\n  * Obtain the MAC address from an nvmem cell named 'mac-address' associated\n  * with given device.\n@@ -558,19 +615,23 @@ int nvmem_get_mac_address(struct device\n {\n \tstruct nvmem_cell *cell;\n \tconst void *mac;\n-\tsize_t len;\n+\tstruct nvmem_cell_mac_address_property *property;\n+\tint i;\n \n-\tcell = nvmem_cell_get(dev, \"mac-address\");\n-\tif (IS_ERR(cell))\n-\t\treturn PTR_ERR(cell);\n-\n-\tmac = nvmem_cell_read(cell, &len);\n-\tnvmem_cell_put(cell);\n-\n-\tif (IS_ERR(mac))\n-\t\treturn PTR_ERR(mac);\n+\tfor (i = 0; i < ARRAY_SIZE(nvmem_cell_mac_address_properties); i++) {\n+\t\tproperty = &nvmem_cell_mac_address_properties[i];\n+\t\tcell = nvmem_cell_get(dev, property->name);\n+\t\tif (IS_ERR(cell)) {\n+\t\t\tif (i == ARRAY_SIZE(nvmem_cell_mac_address_properties) - 1)\n+\t\t\t\treturn PTR_ERR(cell);\n+\t\t\tcontinue;\n+\t\t}\n+\t\tmac = property->read(cell);\n+\t\tnvmem_cell_put(cell);\n+\t\tbreak;\n+\t}\n \n-\tif (len != ETH_ALEN || !is_valid_ether_addr(mac)) {\n+\tif (!is_valid_ether_addr(mac)) {\n \t\tkfree(mac);\n \t\treturn -EINVAL;\n \t}\n"
  },
  {
    "path": "target/linux/ath79/patches-5.10/900-mdio_bitbang_ignore_ta_value.patch",
    "content": "--- a/drivers/net/mdio/mdio-bitbang.c\n+++ b/drivers/net/mdio/mdio-bitbang.c\n@@ -152,7 +152,7 @@ static int mdiobb_cmd_addr(struct mdiobb\n static int mdiobb_read(struct mii_bus *bus, int phy, int reg)\n {\n \tstruct mdiobb_ctrl *ctrl = bus->priv;\n-\tint ret, i;\n+\tint ret;\n \n \tif (reg & MII_ADDR_C45) {\n \t\treg = mdiobb_cmd_addr(ctrl, phy, reg);\n@@ -162,19 +162,7 @@ static int mdiobb_read(struct mii_bus *b\n \n \tctrl->ops->set_mdio_dir(ctrl, 0);\n \n-\t/* check the turnaround bit: the PHY should be driving it to zero, if this\n-\t * PHY is listed in phy_ignore_ta_mask as having broken TA, skip that\n-\t */\n-\tif (mdiobb_get_bit(ctrl) != 0 &&\n-\t    !(bus->phy_ignore_ta_mask & (1 << phy))) {\n-\t\t/* PHY didn't drive TA low -- flush any bits it\n-\t\t * may be trying to send.\n-\t\t */\n-\t\tfor (i = 0; i < 32; i++)\n-\t\t\tmdiobb_get_bit(ctrl);\n-\n-\t\treturn 0xffff;\n-\t}\n+\tmdiobb_get_bit(ctrl);\n \n \tret = mdiobb_get_num(ctrl, 16);\n \tmdiobb_get_bit(ctrl);\n"
  },
  {
    "path": "target/linux/ath79/patches-5.10/901-phy-mdio-bitbang-prevent-rescheduling-during-command.patch",
    "content": "From 66e584435ac0de6e0abeb6d7166fe4fe25d6bb73 Mon Sep 17 00:00:00 2001\nFrom: Jonas Gorski <jogo@openwrt.org>\nDate: Tue, 16 Jun 2015 13:15:08 +0200\nSubject: [PATCH] phy/mdio-bitbang: prevent rescheduling during command\n\nIt seems some phys have some maximum timings for accessing the MDIO line,\nresulting in bit errors under cpu stress. Prevent this from happening by\ndisabling interrupts when sending commands.\n\nSigned-off-by: Jonas Gorski <jogo@openwrt.org>\n---\n drivers/net/mdio/mdio-bitbang.c | 9 +++++++++\n 1 file changed, 9 insertions(+)\n\n--- a/drivers/net/mdio/mdio-bitbang.c\n+++ b/drivers/net/mdio/mdio-bitbang.c\n@@ -15,6 +15,7 @@\n  */\n \n #include <linux/delay.h>\n+#include <linux/irqflags.h>\n #include <linux/mdio-bitbang.h>\n #include <linux/module.h>\n #include <linux/types.h>\n@@ -153,7 +154,9 @@ static int mdiobb_read(struct mii_bus *b\n {\n \tstruct mdiobb_ctrl *ctrl = bus->priv;\n \tint ret;\n+\tunsigned long flags;\n \n+\tlocal_irq_save(flags);\n \tif (reg & MII_ADDR_C45) {\n \t\treg = mdiobb_cmd_addr(ctrl, phy, reg);\n \t\tmdiobb_cmd(ctrl, MDIO_C45_READ, phy, reg);\n@@ -166,13 +169,17 @@ static int mdiobb_read(struct mii_bus *b\n \n \tret = mdiobb_get_num(ctrl, 16);\n \tmdiobb_get_bit(ctrl);\n+\tlocal_irq_restore(flags);\n+\n \treturn ret;\n }\n \n static int mdiobb_write(struct mii_bus *bus, int phy, int reg, u16 val)\n {\n \tstruct mdiobb_ctrl *ctrl = bus->priv;\n+\tunsigned long flags;\n \n+\tlocal_irq_save(flags);\n \tif (reg & MII_ADDR_C45) {\n \t\treg = mdiobb_cmd_addr(ctrl, phy, reg);\n \t\tmdiobb_cmd(ctrl, MDIO_C45_WRITE, phy, reg);\n@@ -187,6 +194,8 @@ static int mdiobb_write(struct mii_bus *\n \n \tctrl->ops->set_mdio_dir(ctrl, 0);\n \tmdiobb_get_bit(ctrl);\n+\tlocal_irq_restore(flags);\n+\n \treturn 0;\n }\n \n"
  },
  {
    "path": "target/linux/ath79/patches-5.10/910-unaligned_access_hacks.patch",
    "content": "--- a/arch/mips/include/asm/checksum.h\n+++ b/arch/mips/include/asm/checksum.h\n@@ -100,26 +100,30 @@ static inline __sum16 ip_fast_csum(const\n \tconst unsigned int *stop = word + ihl;\n \tunsigned int csum;\n \tint carry;\n+\tunsigned int w;\n \n-\tcsum = word[0];\n-\tcsum += word[1];\n-\tcarry = (csum < word[1]);\n+\tcsum = net_hdr_word(word++);\n+\n+\tw = net_hdr_word(word++);\n+\tcsum += w;\n+\tcarry = (csum < w);\n \tcsum += carry;\n \n-\tcsum += word[2];\n-\tcarry = (csum < word[2]);\n+\tw = net_hdr_word(word++);\n+\tcsum += w;\n+\tcarry = (csum < w);\n \tcsum += carry;\n \n-\tcsum += word[3];\n-\tcarry = (csum < word[3]);\n+\tw = net_hdr_word(word++);\n+\tcsum += w;\n+\tcarry = (csum < w);\n \tcsum += carry;\n \n-\tword += 4;\n \tdo {\n-\t\tcsum += *word;\n-\t\tcarry = (csum < *word);\n+\t\tw = net_hdr_word(word++);\n+\t\tcsum += w;\n+\t\tcarry = (csum < w);\n \t\tcsum += carry;\n-\t\tword++;\n \t} while (word != stop);\n \n \treturn csum_fold(csum);\n@@ -180,73 +184,6 @@ static inline __sum16 ip_compute_csum(co\n \treturn csum_fold(csum_partial(buff, len, 0));\n }\n \n-#define _HAVE_ARCH_IPV6_CSUM\n-static __inline__ __sum16 csum_ipv6_magic(const struct in6_addr *saddr,\n-\t\t\t\t\t  const struct in6_addr *daddr,\n-\t\t\t\t\t  __u32 len, __u8 proto,\n-\t\t\t\t\t  __wsum sum)\n-{\n-\t__wsum tmp;\n-\n-\t__asm__(\n-\t\"\t.set\tpush\t\t# csum_ipv6_magic\\n\"\n-\t\"\t.set\tnoreorder\t\\n\"\n-\t\"\t.set\tnoat\t\t\\n\"\n-\t\"\taddu\t%0, %5\t\t# proto (long in network byte order)\\n\"\n-\t\"\tsltu\t$1, %0, %5\t\\n\"\n-\t\"\taddu\t%0, $1\t\t\\n\"\n-\n-\t\"\taddu\t%0, %6\t\t# csum\\n\"\n-\t\"\tsltu\t$1, %0, %6\t\\n\"\n-\t\"\tlw\t%1, 0(%2)\t# four words source address\\n\"\n-\t\"\taddu\t%0, $1\t\t\\n\"\n-\t\"\taddu\t%0, %1\t\t\\n\"\n-\t\"\tsltu\t$1, %0, %1\t\\n\"\n-\n-\t\"\tlw\t%1, 4(%2)\t\\n\"\n-\t\"\taddu\t%0, $1\t\t\\n\"\n-\t\"\taddu\t%0, %1\t\t\\n\"\n-\t\"\tsltu\t$1, %0, %1\t\\n\"\n-\n-\t\"\tlw\t%1, 8(%2)\t\\n\"\n-\t\"\taddu\t%0, $1\t\t\\n\"\n-\t\"\taddu\t%0, %1\t\t\\n\"\n-\t\"\tsltu\t$1, %0, %1\t\\n\"\n-\n-\t\"\tlw\t%1, 12(%2)\t\\n\"\n-\t\"\taddu\t%0, $1\t\t\\n\"\n-\t\"\taddu\t%0, %1\t\t\\n\"\n-\t\"\tsltu\t$1, %0, %1\t\\n\"\n-\n-\t\"\tlw\t%1, 0(%3)\t\\n\"\n-\t\"\taddu\t%0, $1\t\t\\n\"\n-\t\"\taddu\t%0, %1\t\t\\n\"\n-\t\"\tsltu\t$1, %0, %1\t\\n\"\n-\n-\t\"\tlw\t%1, 4(%3)\t\\n\"\n-\t\"\taddu\t%0, $1\t\t\\n\"\n-\t\"\taddu\t%0, %1\t\t\\n\"\n-\t\"\tsltu\t$1, %0, %1\t\\n\"\n-\n-\t\"\tlw\t%1, 8(%3)\t\\n\"\n-\t\"\taddu\t%0, $1\t\t\\n\"\n-\t\"\taddu\t%0, %1\t\t\\n\"\n-\t\"\tsltu\t$1, %0, %1\t\\n\"\n-\n-\t\"\tlw\t%1, 12(%3)\t\\n\"\n-\t\"\taddu\t%0, $1\t\t\\n\"\n-\t\"\taddu\t%0, %1\t\t\\n\"\n-\t\"\tsltu\t$1, %0, %1\t\\n\"\n-\n-\t\"\taddu\t%0, $1\t\t# Add final carry\\n\"\n-\t\"\t.set\tpop\"\n-\t: \"=&r\" (sum), \"=&r\" (tmp)\n-\t: \"r\" (saddr), \"r\" (daddr),\n-\t  \"0\" (htonl(len)), \"r\" (htonl(proto)), \"r\" (sum));\n-\n-\treturn csum_fold(sum);\n-}\n-\n #include <asm-generic/checksum.h>\n #endif /* CONFIG_GENERIC_CSUM */\n \n--- a/include/uapi/linux/ip.h\n+++ b/include/uapi/linux/ip.h\n@@ -103,7 +103,7 @@ struct iphdr {\n \t__be32\tsaddr;\n \t__be32\tdaddr;\n \t/*The options start here. */\n-};\n+} __attribute__((packed, aligned(2)));\n \n \n struct ip_auth_hdr {\n--- a/include/uapi/linux/ipv6.h\n+++ b/include/uapi/linux/ipv6.h\n@@ -132,7 +132,7 @@ struct ipv6hdr {\n \n \tstruct\tin6_addr\tsaddr;\n \tstruct\tin6_addr\tdaddr;\n-};\n+} __attribute__((packed, aligned(2)));\n \n \n /* index values for the variables in ipv6_devconf */\n--- a/include/uapi/linux/tcp.h\n+++ b/include/uapi/linux/tcp.h\n@@ -55,7 +55,7 @@ struct tcphdr {\n \t__be16\twindow;\n \t__sum16\tcheck;\n \t__be16\turg_ptr;\n-};\n+} __attribute__((packed, aligned(2)));\n \n /*\n  *\tThe union cast uses a gcc extension to avoid aliasing problems\n@@ -65,7 +65,7 @@ struct tcphdr {\n union tcp_word_hdr { \n \tstruct tcphdr hdr;\n \t__be32 \t\t  words[5];\n-}; \n+} __attribute__((packed, aligned(2)));\n \n #define tcp_flag_word(tp) ( ((union tcp_word_hdr *)(tp))->words [3]) \n \n--- a/include/uapi/linux/udp.h\n+++ b/include/uapi/linux/udp.h\n@@ -25,7 +25,7 @@ struct udphdr {\n \t__be16\tdest;\n \t__be16\tlen;\n \t__sum16\tcheck;\n-};\n+} __attribute__((packed, aligned(2)));\n \n /* UDP socket options */\n #define UDP_CORK\t1\t/* Never send partially complete segments */\n--- a/net/netfilter/nf_conntrack_core.c\n+++ b/net/netfilter/nf_conntrack_core.c\n@@ -271,8 +271,8 @@ nf_ct_get_tuple(const struct sk_buff *sk\n \n \tswitch (l3num) {\n \tcase NFPROTO_IPV4:\n-\t\ttuple->src.u3.ip = ap[0];\n-\t\ttuple->dst.u3.ip = ap[1];\n+\t\ttuple->src.u3.ip = net_hdr_word(ap++);\n+\t\ttuple->dst.u3.ip = net_hdr_word(ap);\n \t\tbreak;\n \tcase NFPROTO_IPV6:\n \t\tmemcpy(tuple->src.u3.ip6, ap, sizeof(tuple->src.u3.ip6));\n--- a/include/uapi/linux/icmp.h\n+++ b/include/uapi/linux/icmp.h\n@@ -83,7 +83,7 @@ struct icmphdr {\n \t} frag;\n \t__u8\treserved[4];\n   } un;\n-};\n+} __attribute__((packed, aligned(2)));\n \n \n /*\n--- a/include/uapi/linux/in6.h\n+++ b/include/uapi/linux/in6.h\n@@ -43,7 +43,7 @@ struct in6_addr {\n #define s6_addr16\t\tin6_u.u6_addr16\n #define s6_addr32\t\tin6_u.u6_addr32\n #endif\n-};\n+} __attribute__((packed, aligned(2)));\n #endif /* __UAPI_DEF_IN6_ADDR */\n \n #if __UAPI_DEF_SOCKADDR_IN6\n--- a/net/ipv6/tcp_ipv6.c\n+++ b/net/ipv6/tcp_ipv6.c\n@@ -35,6 +35,7 @@\n #include <linux/ipsec.h>\n #include <linux/times.h>\n #include <linux/slab.h>\n+#include <asm/unaligned.h>\n #include <linux/uaccess.h>\n #include <linux/ipv6.h>\n #include <linux/icmpv6.h>\n@@ -924,10 +925,10 @@ static void tcp_v6_send_response(const s\n \ttopt = (__be32 *)(t1 + 1);\n \n \tif (tsecr) {\n-\t\t*topt++ = htonl((TCPOPT_NOP << 24) | (TCPOPT_NOP << 16) |\n-\t\t\t\t(TCPOPT_TIMESTAMP << 8) | TCPOLEN_TIMESTAMP);\n-\t\t*topt++ = htonl(tsval);\n-\t\t*topt++ = htonl(tsecr);\n+\t\tput_unaligned_be32((TCPOPT_NOP << 24) | (TCPOPT_NOP << 16) |\n+\t\t\t\t(TCPOPT_TIMESTAMP << 8) | TCPOLEN_TIMESTAMP, topt++);\n+\t\tput_unaligned_be32(tsval, topt++);\n+\t\tput_unaligned_be32(tsecr, topt++);\n \t}\n \n #ifdef CONFIG_TCP_MD5SIG\n--- a/include/linux/ipv6.h\n+++ b/include/linux/ipv6.h\n@@ -6,6 +6,7 @@\n \n #define ipv6_optlen(p)  (((p)->hdrlen+1) << 3)\n #define ipv6_authlen(p) (((p)->hdrlen+2) << 2)\n+\n /*\n  * This structure contains configuration options per IPv6 link.\n  */\n--- a/net/ipv6/datagram.c\n+++ b/net/ipv6/datagram.c\n@@ -492,7 +492,7 @@ int ipv6_recv_error(struct sock *sk, str\n \t\t\t\tipv6_iface_scope_id(&sin->sin6_addr,\n \t\t\t\t\t\t    IP6CB(skb)->iif);\n \t\t} else {\n-\t\t\tipv6_addr_set_v4mapped(*(__be32 *)(nh + serr->addr_offset),\n+\t\t\tipv6_addr_set_v4mapped(net_hdr_word(nh + serr->addr_offset),\n \t\t\t\t\t       &sin->sin6_addr);\n \t\t\tsin->sin6_scope_id = 0;\n \t\t}\n@@ -846,12 +846,12 @@ int ip6_datagram_send_ctl(struct net *ne\n \t\t\t}\n \n \t\t\tif (fl6->flowlabel&IPV6_FLOWINFO_MASK) {\n-\t\t\t\tif ((fl6->flowlabel^*(__be32 *)CMSG_DATA(cmsg))&~IPV6_FLOWINFO_MASK) {\n+\t\t\t\tif ((fl6->flowlabel^net_hdr_word(CMSG_DATA(cmsg)))&~IPV6_FLOWINFO_MASK) {\n \t\t\t\t\terr = -EINVAL;\n \t\t\t\t\tgoto exit_f;\n \t\t\t\t}\n \t\t\t}\n-\t\t\tfl6->flowlabel = IPV6_FLOWINFO_MASK & *(__be32 *)CMSG_DATA(cmsg);\n+\t\t\tfl6->flowlabel = IPV6_FLOWINFO_MASK & net_hdr_word(CMSG_DATA(cmsg));\n \t\t\tbreak;\n \n \t\tcase IPV6_2292HOPOPTS:\n--- a/net/ipv6/exthdrs.c\n+++ b/net/ipv6/exthdrs.c\n@@ -948,7 +948,7 @@ static bool ipv6_hop_jumbo(struct sk_buf\n \t\tgoto drop;\n \t}\n \n-\tpkt_len = ntohl(*(__be32 *)(nh + optoff + 2));\n+\tpkt_len = ntohl(net_hdr_word(nh + optoff + 2));\n \tif (pkt_len <= IPV6_MAXPLEN) {\n \t\t__IP6_INC_STATS(net, idev, IPSTATS_MIB_INHDRERRORS);\n \t\ticmpv6_param_prob(skb, ICMPV6_HDR_FIELD, optoff+2);\n--- a/include/linux/types.h\n+++ b/include/linux/types.h\n@@ -227,5 +227,11 @@ typedef void (*swap_func_t)(void *a, voi\n typedef int (*cmp_r_func_t)(const void *a, const void *b, const void *priv);\n typedef int (*cmp_func_t)(const void *a, const void *b);\n \n+struct net_hdr_word {\n+       u32 words[1];\n+} __attribute__((packed, aligned(2)));\n+\n+#define net_hdr_word(_p) (((struct net_hdr_word *) (_p))->words[0])\n+\n #endif /*  __ASSEMBLY__ */\n #endif /* _LINUX_TYPES_H */\n--- a/net/ipv4/af_inet.c\n+++ b/net/ipv4/af_inet.c\n@@ -1470,8 +1470,8 @@ struct sk_buff *inet_gro_receive(struct\n \tif (unlikely(ip_fast_csum((u8 *)iph, 5)))\n \t\tgoto out_unlock;\n \n-\tid = ntohl(*(__be32 *)&iph->id);\n-\tflush = (u16)((ntohl(*(__be32 *)iph) ^ skb_gro_len(skb)) | (id & ~IP_DF));\n+\tid = ntohl(net_hdr_word(&iph->id));\n+\tflush = (u16)((ntohl(net_hdr_word(iph)) ^ skb_gro_len(skb)) | (id & ~IP_DF));\n \tid >>= 16;\n \n \tlist_for_each_entry(p, head, list) {\n--- a/net/ipv4/tcp_output.c\n+++ b/net/ipv4/tcp_output.c\n@@ -611,48 +611,53 @@ static void tcp_options_write(__be32 *pt\n \tu16 options = opts->options;\t/* mungable copy */\n \n \tif (unlikely(OPTION_MD5 & options)) {\n-\t\t*ptr++ = htonl((TCPOPT_NOP << 24) | (TCPOPT_NOP << 16) |\n-\t\t\t       (TCPOPT_MD5SIG << 8) | TCPOLEN_MD5SIG);\n+\t\tnet_hdr_word(ptr++) =\n+\t\t\thtonl((TCPOPT_NOP << 24) | (TCPOPT_NOP << 16) |\n+\t\t\t      (TCPOPT_MD5SIG << 8) | TCPOLEN_MD5SIG);\n \t\t/* overload cookie hash location */\n \t\topts->hash_location = (__u8 *)ptr;\n \t\tptr += 4;\n \t}\n \n \tif (unlikely(opts->mss)) {\n-\t\t*ptr++ = htonl((TCPOPT_MSS << 24) |\n-\t\t\t       (TCPOLEN_MSS << 16) |\n-\t\t\t       opts->mss);\n+\t\tnet_hdr_word(ptr++) =\n+\t\t\thtonl((TCPOPT_MSS << 24) | (TCPOLEN_MSS << 16) |\n+\t\t\t      opts->mss);\n \t}\n \n \tif (likely(OPTION_TS & options)) {\n \t\tif (unlikely(OPTION_SACK_ADVERTISE & options)) {\n-\t\t\t*ptr++ = htonl((TCPOPT_SACK_PERM << 24) |\n-\t\t\t\t       (TCPOLEN_SACK_PERM << 16) |\n-\t\t\t\t       (TCPOPT_TIMESTAMP << 8) |\n-\t\t\t\t       TCPOLEN_TIMESTAMP);\n+\t\t\tnet_hdr_word(ptr++) =\n+\t\t\t\thtonl((TCPOPT_SACK_PERM << 24) |\n+\t\t\t\t      (TCPOLEN_SACK_PERM << 16) |\n+\t\t\t\t      (TCPOPT_TIMESTAMP << 8) |\n+\t\t\t\t      TCPOLEN_TIMESTAMP);\n \t\t\toptions &= ~OPTION_SACK_ADVERTISE;\n \t\t} else {\n-\t\t\t*ptr++ = htonl((TCPOPT_NOP << 24) |\n-\t\t\t\t       (TCPOPT_NOP << 16) |\n-\t\t\t\t       (TCPOPT_TIMESTAMP << 8) |\n-\t\t\t\t       TCPOLEN_TIMESTAMP);\n+\t\t\tnet_hdr_word(ptr++) =\n+\t\t\t\thtonl((TCPOPT_NOP << 24) |\n+\t\t\t\t      (TCPOPT_NOP << 16) |\n+\t\t\t\t      (TCPOPT_TIMESTAMP << 8) |\n+\t\t\t\t      TCPOLEN_TIMESTAMP);\n \t\t}\n-\t\t*ptr++ = htonl(opts->tsval);\n-\t\t*ptr++ = htonl(opts->tsecr);\n+\t\tnet_hdr_word(ptr++) = htonl(opts->tsval);\n+\t\tnet_hdr_word(ptr++) = htonl(opts->tsecr);\n \t}\n \n \tif (unlikely(OPTION_SACK_ADVERTISE & options)) {\n-\t\t*ptr++ = htonl((TCPOPT_NOP << 24) |\n-\t\t\t       (TCPOPT_NOP << 16) |\n-\t\t\t       (TCPOPT_SACK_PERM << 8) |\n-\t\t\t       TCPOLEN_SACK_PERM);\n+\t\tnet_hdr_word(ptr++) =\n+\t\t\thtonl((TCPOPT_NOP << 24) |\n+\t\t\t      (TCPOPT_NOP << 16) |\n+\t\t\t      (TCPOPT_SACK_PERM << 8) |\n+\t\t\t      TCPOLEN_SACK_PERM);\n \t}\n \n \tif (unlikely(OPTION_WSCALE & options)) {\n-\t\t*ptr++ = htonl((TCPOPT_NOP << 24) |\n-\t\t\t       (TCPOPT_WINDOW << 16) |\n-\t\t\t       (TCPOLEN_WINDOW << 8) |\n-\t\t\t       opts->ws);\n+\t\tnet_hdr_word(ptr++) =\n+\t\t\thtonl((TCPOPT_NOP << 24) |\n+\t\t\t      (TCPOPT_WINDOW << 16) |\n+\t\t\t      (TCPOLEN_WINDOW << 8) |\n+\t\t\t      opts->ws);\n \t}\n \n \tif (unlikely(opts->num_sack_blocks)) {\n@@ -660,16 +665,17 @@ static void tcp_options_write(__be32 *pt\n \t\t\ttp->duplicate_sack : tp->selective_acks;\n \t\tint this_sack;\n \n-\t\t*ptr++ = htonl((TCPOPT_NOP  << 24) |\n-\t\t\t       (TCPOPT_NOP  << 16) |\n-\t\t\t       (TCPOPT_SACK <<  8) |\n-\t\t\t       (TCPOLEN_SACK_BASE + (opts->num_sack_blocks *\n+\t\tnet_hdr_word(ptr++) =\n+\t\t\thtonl((TCPOPT_NOP << 24) |\n+\t\t\t      (TCPOPT_NOP << 16) |\n+\t\t\t      (TCPOPT_SACK << 8) |\n+\t\t\t      (TCPOLEN_SACK_BASE + (opts->num_sack_blocks *\n \t\t\t\t\t\t     TCPOLEN_SACK_PERBLOCK)));\n \n \t\tfor (this_sack = 0; this_sack < opts->num_sack_blocks;\n \t\t     ++this_sack) {\n-\t\t\t*ptr++ = htonl(sp[this_sack].start_seq);\n-\t\t\t*ptr++ = htonl(sp[this_sack].end_seq);\n+\t\t\tnet_hdr_word(ptr++) = htonl(sp[this_sack].start_seq);\n+\t\t\tnet_hdr_word(ptr++) = htonl(sp[this_sack].end_seq);\n \t\t}\n \n \t\ttp->rx_opt.dsack = 0;\n@@ -682,13 +688,14 @@ static void tcp_options_write(__be32 *pt\n \n \t\tif (foc->exp) {\n \t\t\tlen = TCPOLEN_EXP_FASTOPEN_BASE + foc->len;\n-\t\t\t*ptr = htonl((TCPOPT_EXP << 24) | (len << 16) |\n+\t\t\tnet_hdr_word(ptr) =\n+\t\t\t\thtonl((TCPOPT_EXP << 24) | (len << 16) |\n \t\t\t\t     TCPOPT_FASTOPEN_MAGIC);\n \t\t\tp += TCPOLEN_EXP_FASTOPEN_BASE;\n \t\t} else {\n \t\t\tlen = TCPOLEN_FASTOPEN_BASE + foc->len;\n-\t\t\t*p++ = TCPOPT_FASTOPEN;\n-\t\t\t*p++ = len;\n+\t\t\tnet_hdr_word(p++) = TCPOPT_FASTOPEN;\n+\t\t\tnet_hdr_word(p++) = len;\n \t\t}\n \n \t\tmemcpy(p, foc->val, foc->len);\n--- a/include/uapi/linux/igmp.h\n+++ b/include/uapi/linux/igmp.h\n@@ -33,7 +33,7 @@ struct igmphdr {\n \t__u8 code;\t\t/* For newer IGMP */\n \t__sum16 csum;\n \t__be32 group;\n-};\n+} __attribute__((packed, aligned(2)));\n \n /* V3 group record types [grec_type] */\n #define IGMPV3_MODE_IS_INCLUDE\t\t1\n@@ -49,7 +49,7 @@ struct igmpv3_grec {\n \t__be16\tgrec_nsrcs;\n \t__be32\tgrec_mca;\n \t__be32\tgrec_src[0];\n-};\n+} __attribute__((packed, aligned(2)));\n \n struct igmpv3_report {\n \t__u8 type;\n@@ -58,7 +58,7 @@ struct igmpv3_report {\n \t__be16 resv2;\n \t__be16 ngrec;\n \tstruct igmpv3_grec grec[0];\n-};\n+} __attribute__((packed, aligned(2)));\n \n struct igmpv3_query {\n \t__u8 type;\n@@ -79,7 +79,7 @@ struct igmpv3_query {\n \t__u8 qqic;\n \t__be16 nsrcs;\n \t__be32 srcs[0];\n-};\n+} __attribute__((packed, aligned(2)));\n \n #define IGMP_HOST_MEMBERSHIP_QUERY\t0x11\t/* From RFC1112 */\n #define IGMP_HOST_MEMBERSHIP_REPORT\t0x12\t/* Ditto */\n--- a/net/core/flow_dissector.c\n+++ b/net/core/flow_dissector.c\n@@ -128,7 +128,7 @@ __be32 __skb_flow_get_ports(const struct\n \t\tports = __skb_header_pointer(skb, thoff + poff,\n \t\t\t\t\t     sizeof(_ports), data, hlen, &_ports);\n \t\tif (ports)\n-\t\t\treturn *ports;\n+\t\t\treturn (__be32)net_hdr_word(ports);\n \t}\n \n \treturn 0;\n--- a/include/uapi/linux/icmpv6.h\n+++ b/include/uapi/linux/icmpv6.h\n@@ -78,7 +78,7 @@ struct icmp6hdr {\n #define icmp6_addrconf_other\ticmp6_dataun.u_nd_ra.other\n #define icmp6_rt_lifetime\ticmp6_dataun.u_nd_ra.rt_lifetime\n #define icmp6_router_pref\ticmp6_dataun.u_nd_ra.router_pref\n-};\n+} __attribute__((packed, aligned(2)));\n \n \n #define ICMPV6_ROUTER_PREF_LOW\t\t0x3\n--- a/include/net/ndisc.h\n+++ b/include/net/ndisc.h\n@@ -93,7 +93,7 @@ struct ra_msg {\n         struct icmp6hdr\t\ticmph;\n \t__be32\t\t\treachable_time;\n \t__be32\t\t\tretrans_timer;\n-};\n+} __attribute__((packed, aligned(2)));\n \n struct rd_msg {\n \tstruct icmp6hdr icmph;\n@@ -372,10 +372,10 @@ static inline u32 ndisc_hashfn(const voi\n {\n \tconst u32 *p32 = pkey;\n \n-\treturn (((p32[0] ^ hash32_ptr(dev)) * hash_rnd[0]) +\n-\t\t(p32[1] * hash_rnd[1]) +\n-\t\t(p32[2] * hash_rnd[2]) +\n-\t\t(p32[3] * hash_rnd[3]));\n+\treturn (((net_hdr_word(&p32[0]) ^ hash32_ptr(dev)) * hash_rnd[0]) +\n+\t\t(net_hdr_word(&p32[1]) * hash_rnd[1]) +\n+\t\t(net_hdr_word(&p32[2]) * hash_rnd[2]) +\n+\t\t(net_hdr_word(&p32[3]) * hash_rnd[3]));\n }\n \n static inline struct neighbour *__ipv6_neigh_lookup_noref(struct net_device *dev, const void *pkey)\n--- a/net/sched/cls_u32.c\n+++ b/net/sched/cls_u32.c\n@@ -155,7 +155,7 @@ next_knode:\n \t\t\tdata = skb_header_pointer(skb, toff, 4, &hdata);\n \t\t\tif (!data)\n \t\t\t\tgoto out;\n-\t\t\tif ((*data ^ key->val) & key->mask) {\n+\t\t\tif ((net_hdr_word(data) ^ key->val) & key->mask) {\n \t\t\t\tn = rcu_dereference_bh(n->next);\n \t\t\t\tgoto next_knode;\n \t\t\t}\n@@ -206,8 +206,8 @@ check_terminal:\n \t\t\t\t\t\t  &hdata);\n \t\t\tif (!data)\n \t\t\t\tgoto out;\n-\t\t\tsel = ht->divisor & u32_hash_fold(*data, &n->sel,\n-\t\t\t\t\t\t\t  n->fshift);\n+\t\t\tsel = ht->divisor & u32_hash_fold(net_hdr_word(data),\n+\t\t\t\t\t\t\t  &n->sel, n->fshift);\n \t\t}\n \t\tif (!(n->sel.flags & (TC_U32_VAROFFSET | TC_U32_OFFSET | TC_U32_EAT)))\n \t\t\tgoto next_ht;\n--- a/net/ipv6/ip6_offload.c\n+++ b/net/ipv6/ip6_offload.c\n@@ -240,7 +240,7 @@ INDIRECT_CALLABLE_SCOPE struct sk_buff *\n \t\t\tcontinue;\n \n \t\tiph2 = (struct ipv6hdr *)(p->data + off);\n-\t\tfirst_word = *(__be32 *)iph ^ *(__be32 *)iph2;\n+\t\tfirst_word = net_hdr_word(iph) ^ net_hdr_word(iph2);\n \n \t\t/* All fields must match except length and Traffic Class.\n \t\t * XXX skbs on the gro_list have all been parsed and pulled\n--- a/include/net/addrconf.h\n+++ b/include/net/addrconf.h\n@@ -47,7 +47,7 @@ struct prefix_info {\n \t__be32\t\t\treserved2;\n \n \tstruct in6_addr\t\tprefix;\n-};\n+} __attribute__((packed, aligned(2)));\n \n #include <linux/ipv6.h>\n #include <linux/netdevice.h>\n--- a/include/net/inet_ecn.h\n+++ b/include/net/inet_ecn.h\n@@ -140,9 +140,9 @@ static inline int IP6_ECN_set_ce(struct\n \tif (INET_ECN_is_not_ect(ipv6_get_dsfield(iph)))\n \t\treturn 0;\n \n-\tfrom = *(__be32 *)iph;\n+\tfrom = net_hdr_word(iph);\n \tto = from | htonl(INET_ECN_CE << 20);\n-\t*(__be32 *)iph = to;\n+\tnet_hdr_word(iph) = to;\n \tif (skb->ip_summed == CHECKSUM_COMPLETE)\n \t\tskb->csum = csum_add(csum_sub(skb->csum, (__force __wsum)from),\n \t\t\t\t     (__force __wsum)to);\n--- a/include/net/ipv6.h\n+++ b/include/net/ipv6.h\n@@ -146,7 +146,7 @@ struct frag_hdr {\n \t__u8\treserved;\n \t__be16\tfrag_off;\n \t__be32\tidentification;\n-};\n+} __attribute__((packed, aligned(2)));\n \n #define\tIP6_MF\t\t0x0001\n #define\tIP6_OFFSET\t0xFFF8\n@@ -560,8 +560,8 @@ static inline void __ipv6_addr_set_half(\n \t}\n #endif\n #endif\n-\taddr[0] = wh;\n-\taddr[1] = wl;\n+\tnet_hdr_word(&addr[0]) = wh;\n+\tnet_hdr_word(&addr[1]) = wl;\n }\n \n static inline void ipv6_addr_set(struct in6_addr *addr,\n@@ -620,6 +620,8 @@ static inline bool ipv6_prefix_equal(con\n \tconst __be32 *a1 = addr1->s6_addr32;\n \tconst __be32 *a2 = addr2->s6_addr32;\n \tunsigned int pdw, pbi;\n+\t/* Used for last <32-bit fraction of prefix */\n+\tu32 pbia1, pbia2;\n \n \t/* check complete u32 in prefix */\n \tpdw = prefixlen >> 5;\n@@ -628,7 +630,9 @@ static inline bool ipv6_prefix_equal(con\n \n \t/* check incomplete u32 in prefix */\n \tpbi = prefixlen & 0x1f;\n-\tif (pbi && ((a1[pdw] ^ a2[pdw]) & htonl((0xffffffff) << (32 - pbi))))\n+\tpbia1 = net_hdr_word(&a1[pdw]);\n+\tpbia2 = net_hdr_word(&a2[pdw]);\n+\tif (pbi && ((pbia1 ^ pbia2) & htonl((0xffffffff) << (32 - pbi))))\n \t\treturn false;\n \n \treturn true;\n@@ -749,13 +753,13 @@ static inline void ipv6_addr_set_v4mappe\n  */\n static inline int __ipv6_addr_diff32(const void *token1, const void *token2, int addrlen)\n {\n-\tconst __be32 *a1 = token1, *a2 = token2;\n+\tconst struct in6_addr *a1 = token1, *a2 = token2;\n \tint i;\n \n \taddrlen >>= 2;\n \n \tfor (i = 0; i < addrlen; i++) {\n-\t\t__be32 xb = a1[i] ^ a2[i];\n+\t\t__be32 xb = a1->s6_addr32[i] ^ a2->s6_addr32[i];\n \t\tif (xb)\n \t\t\treturn i * 32 + 31 - __fls(ntohl(xb));\n \t}\n@@ -941,17 +945,18 @@ static inline int ip6_multipath_hash_pol\n static inline void ip6_flow_hdr(struct ipv6hdr *hdr, unsigned int tclass,\n \t\t\t\t__be32 flowlabel)\n {\n-\t*(__be32 *)hdr = htonl(0x60000000 | (tclass << 20)) | flowlabel;\n+\tnet_hdr_word((__be32 *)hdr) =\n+\t\thtonl(0x60000000 | (tclass << 20)) | flowlabel;\n }\n \n static inline __be32 ip6_flowinfo(const struct ipv6hdr *hdr)\n {\n-\treturn *(__be32 *)hdr & IPV6_FLOWINFO_MASK;\n+\treturn net_hdr_word((__be32 *)hdr) & IPV6_FLOWINFO_MASK;\n }\n \n static inline __be32 ip6_flowlabel(const struct ipv6hdr *hdr)\n {\n-\treturn *(__be32 *)hdr & IPV6_FLOWLABEL_MASK;\n+\treturn net_hdr_word((__be32 *)hdr) & IPV6_FLOWLABEL_MASK;\n }\n \n static inline u8 ip6_tclass(__be32 flowinfo)\n--- a/include/net/secure_seq.h\n+++ b/include/net/secure_seq.h\n@@ -3,6 +3,7 @@\n #define _NET_SECURE_SEQ\n \n #include <linux/types.h>\n+#include <linux/in6.h>\n \n u32 secure_ipv4_port_ephemeral(__be32 saddr, __be32 daddr, __be16 dport);\n u32 secure_ipv6_port_ephemeral(const __be32 *saddr, const __be32 *daddr,\n--- a/include/uapi/linux/in.h\n+++ b/include/uapi/linux/in.h\n@@ -88,7 +88,7 @@ enum {\n /* Internet address. */\n struct in_addr {\n \t__be32\ts_addr;\n-};\n+} __attribute__((packed, aligned(2)));\n #endif\n \n #define IP_TOS\t\t1\n--- a/net/ipv6/ip6_fib.c\n+++ b/net/ipv6/ip6_fib.c\n@@ -140,7 +140,7 @@ static __be32 addr_bit_set(const void *t\n \t * See include/asm-generic/bitops/le.h.\n \t */\n \treturn (__force __be32)(1 << ((~fn_bit ^ BITOP_BE32_SWIZZLE) & 0x1f)) &\n-\t       addr[fn_bit >> 5];\n+\t       net_hdr_word(&addr[fn_bit >> 5]);\n }\n \n struct fib6_info *fib6_info_alloc(gfp_t gfp_flags, bool with_fib6_nh)\n--- a/net/netfilter/nf_conntrack_proto_tcp.c\n+++ b/net/netfilter/nf_conntrack_proto_tcp.c\n@@ -415,7 +415,7 @@ static void tcp_sack(const struct sk_buf\n \n \t/* Fast path for timestamp-only option */\n \tif (length == TCPOLEN_TSTAMP_ALIGNED\n-\t    && *(__be32 *)ptr == htonl((TCPOPT_NOP << 24)\n+\t    && net_hdr_word(ptr) == htonl((TCPOPT_NOP << 24)\n \t\t\t\t       | (TCPOPT_NOP << 16)\n \t\t\t\t       | (TCPOPT_TIMESTAMP << 8)\n \t\t\t\t       | TCPOLEN_TIMESTAMP))\n--- a/net/xfrm/xfrm_input.c\n+++ b/net/xfrm/xfrm_input.c\n@@ -165,8 +165,8 @@ int xfrm_parse_spi(struct sk_buff *skb,\n \tif (!pskb_may_pull(skb, hlen))\n \t\treturn -EINVAL;\n \n-\t*spi = *(__be32 *)(skb_transport_header(skb) + offset);\n-\t*seq = *(__be32 *)(skb_transport_header(skb) + offset_seq);\n+\t*spi = net_hdr_word(skb_transport_header(skb) + offset);\n+\t*seq = net_hdr_word(skb_transport_header(skb) + offset_seq);\n \treturn 0;\n }\n EXPORT_SYMBOL(xfrm_parse_spi);\n--- a/net/ipv4/tcp_input.c\n+++ b/net/ipv4/tcp_input.c\n@@ -4083,14 +4083,16 @@ static bool tcp_parse_aligned_timestamp(\n {\n \tconst __be32 *ptr = (const __be32 *)(th + 1);\n \n-\tif (*ptr == htonl((TCPOPT_NOP << 24) | (TCPOPT_NOP << 16)\n-\t\t\t  | (TCPOPT_TIMESTAMP << 8) | TCPOLEN_TIMESTAMP)) {\n+\tif (net_hdr_word(ptr) ==\n+\t    htonl((TCPOPT_NOP << 24) | (TCPOPT_NOP << 16) |\n+\t\t  (TCPOPT_TIMESTAMP << 8) | TCPOLEN_TIMESTAMP)) {\n \t\ttp->rx_opt.saw_tstamp = 1;\n \t\t++ptr;\n-\t\ttp->rx_opt.rcv_tsval = ntohl(*ptr);\n+\t\ttp->rx_opt.rcv_tsval = get_unaligned_be32(ptr);\n \t\t++ptr;\n-\t\tif (*ptr)\n-\t\t\ttp->rx_opt.rcv_tsecr = ntohl(*ptr) - tp->tsoffset;\n+\t\tif (net_hdr_word(ptr))\n+\t\t\ttp->rx_opt.rcv_tsecr = get_unaligned_be32(ptr) -\n+\t\t\t\t\t       tp->tsoffset;\n \t\telse\n \t\t\ttp->rx_opt.rcv_tsecr = 0;\n \t\treturn true;\n--- a/include/uapi/linux/if_pppox.h\n+++ b/include/uapi/linux/if_pppox.h\n@@ -51,6 +51,7 @@ struct pppoe_addr {\n  */\n struct pptp_addr {\n \t__u16\t\tcall_id;\n+\t__u16\t\tpad;\n \tstruct in_addr\tsin_addr;\n };\n \n--- a/net/ipv6/netfilter/nf_log_ipv6.c\n+++ b/net/ipv6/netfilter/nf_log_ipv6.c\n@@ -63,9 +63,9 @@ static void dump_ipv6_packet(struct net\n \t/* Max length: 44 \"LEN=65535 TC=255 HOPLIMIT=255 FLOWLBL=FFFFF \" */\n \tnf_log_buf_add(m, \"LEN=%zu TC=%u HOPLIMIT=%u FLOWLBL=%u \",\n \t       ntohs(ih->payload_len) + sizeof(struct ipv6hdr),\n-\t       (ntohl(*(__be32 *)ih) & 0x0ff00000) >> 20,\n+\t       (ntohl(net_hdr_word(ih)) & 0x0ff00000) >> 20,\n \t       ih->hop_limit,\n-\t       (ntohl(*(__be32 *)ih) & 0x000fffff));\n+\t       (ntohl(net_hdr_word(ih)) & 0x000fffff));\n \n \tfragment = 0;\n \tptr = ip6hoff + sizeof(struct ipv6hdr);\n--- a/include/net/neighbour.h\n+++ b/include/net/neighbour.h\n@@ -275,8 +275,10 @@ static inline bool neigh_key_eq128(const\n \tconst u32 *n32 = (const u32 *)n->primary_key;\n \tconst u32 *p32 = pkey;\n \n-\treturn ((n32[0] ^ p32[0]) | (n32[1] ^ p32[1]) |\n-\t\t(n32[2] ^ p32[2]) | (n32[3] ^ p32[3])) == 0;\n+\treturn ((n32[0] ^ net_hdr_word(&p32[0])) |\n+\t\t(n32[1] ^ net_hdr_word(&p32[1])) |\n+\t\t(n32[2] ^ net_hdr_word(&p32[2])) |\n+\t\t(n32[3] ^ net_hdr_word(&p32[3]))) == 0;\n }\n \n static inline struct neighbour *___neigh_lookup_noref(\n--- a/include/uapi/linux/netfilter_arp/arp_tables.h\n+++ b/include/uapi/linux/netfilter_arp/arp_tables.h\n@@ -70,7 +70,7 @@ struct arpt_arp {\n \t__u8 flags;\n \t/* Inverse flags */\n \t__u16 invflags;\n-};\n+} __attribute__((aligned(4)));\n \n /* Values for \"flag\" field in struct arpt_ip (general arp structure).\n  * No flags defined yet.\n--- a/net/core/utils.c\n+++ b/net/core/utils.c\n@@ -460,8 +460,14 @@ void inet_proto_csum_replace16(__sum16 *\n \t\t\t       bool pseudohdr)\n {\n \t__be32 diff[] = {\n-\t\t~from[0], ~from[1], ~from[2], ~from[3],\n-\t\tto[0], to[1], to[2], to[3],\n+\t\t~net_hdr_word(&from[0]),\n+\t\t~net_hdr_word(&from[1]),\n+\t\t~net_hdr_word(&from[2]),\n+\t\t~net_hdr_word(&from[3]),\n+\t\tnet_hdr_word(&to[0]),\n+\t\tnet_hdr_word(&to[1]),\n+\t\tnet_hdr_word(&to[2]),\n+\t\tnet_hdr_word(&to[3]),\n \t};\n \tif (skb->ip_summed != CHECKSUM_PARTIAL) {\n \t\t*sum = csum_fold(csum_partial(diff, sizeof(diff),\n--- a/include/linux/etherdevice.h\n+++ b/include/linux/etherdevice.h\n@@ -499,7 +499,7 @@ static inline bool is_etherdev_addr(cons\n  * @b: Pointer to Ethernet header\n  *\n  * Compare two Ethernet headers, returns 0 if equal.\n- * This assumes that the network header (i.e., IP header) is 4-byte\n+ * This assumes that the network header (i.e., IP header) is 2-byte\n  * aligned OR the platform can handle unaligned access.  This is the\n  * case for all packets coming into netif_receive_skb or similar\n  * entry points.\n@@ -522,11 +522,12 @@ static inline unsigned long compare_ethe\n \tfold |= *(unsigned long *)(a + 6) ^ *(unsigned long *)(b + 6);\n \treturn fold;\n #else\n-\tu32 *a32 = (u32 *)((u8 *)a + 2);\n-\tu32 *b32 = (u32 *)((u8 *)b + 2);\n+\tconst u16 *a16 = a;\n+\tconst u16 *b16 = b;\n \n-\treturn (*(u16 *)a ^ *(u16 *)b) | (a32[0] ^ b32[0]) |\n-\t       (a32[1] ^ b32[1]) | (a32[2] ^ b32[2]);\n+\treturn (a16[0] ^ b16[0]) | (a16[1] ^ b16[1]) | (a16[2] ^ b16[2]) |\n+\t       (a16[3] ^ b16[3]) | (a16[4] ^ b16[4]) | (a16[5] ^ b16[5]) |\n+\t       (a16[6] ^ b16[6]);\n #endif\n }\n \n--- a/net/ipv4/tcp_offload.c\n+++ b/net/ipv4/tcp_offload.c\n@@ -223,7 +223,7 @@ struct sk_buff *tcp_gro_receive(struct l\n \n \t\tth2 = tcp_hdr(p);\n \n-\t\tif (*(u32 *)&th->source ^ *(u32 *)&th2->source) {\n+\t\tif (net_hdr_word(&th->source) ^ net_hdr_word(&th2->source)) {\n \t\t\tNAPI_GRO_CB(p)->same_flow = 0;\n \t\t\tcontinue;\n \t\t}\n@@ -241,8 +241,8 @@ found:\n \t\t  ~(TCP_FLAG_CWR | TCP_FLAG_FIN | TCP_FLAG_PSH));\n \tflush |= (__force int)(th->ack_seq ^ th2->ack_seq);\n \tfor (i = sizeof(*th); i < thlen; i += 4)\n-\t\tflush |= *(u32 *)((u8 *)th + i) ^\n-\t\t\t *(u32 *)((u8 *)th2 + i);\n+\t\tflush |= net_hdr_word((u8 *)th + i) ^\n+\t\t\t net_hdr_word((u8 *)th2 + i);\n \n \t/* When we receive our second frame we can made a decision on if we\n \t * continue this flow as an atomic flow with a fixed ID or if we use\n--- a/net/ipv6/netfilter/ip6table_mangle.c\n+++ b/net/ipv6/netfilter/ip6table_mangle.c\n@@ -47,7 +47,7 @@ ip6t_mangle_out(struct sk_buff *skb, con\n \thop_limit = ipv6_hdr(skb)->hop_limit;\n \n \t/* flowlabel and prio (includes version, which shouldn't change either */\n-\tflowlabel = *((u_int32_t *)ipv6_hdr(skb));\n+\tflowlabel = net_hdr_word(ipv6_hdr(skb));\n \n \tret = ip6t_do_table(skb, state, state->net->ipv6.ip6table_mangle);\n \n@@ -56,7 +56,7 @@ ip6t_mangle_out(struct sk_buff *skb, con\n \t     !ipv6_addr_equal(&ipv6_hdr(skb)->daddr, &daddr) ||\n \t     skb->mark != mark ||\n \t     ipv6_hdr(skb)->hop_limit != hop_limit ||\n-\t     flowlabel != *((u_int32_t *)ipv6_hdr(skb)))) {\n+\t     flowlabel != net_hdr_word(ipv6_hdr(skb)))) {\n \t\terr = ip6_route_me_harder(state->net, state->sk, skb);\n \t\tif (err < 0)\n \t\t\tret = NF_DROP_ERR(err);\n"
  },
  {
    "path": "target/linux/ath79/patches-5.10/920-mikrotik-rb4xx.patch",
    "content": "--- a/drivers/mfd/Kconfig\n+++ b/drivers/mfd/Kconfig\n@@ -2142,6 +2142,14 @@ config RAVE_SP_CORE\n \t  Select this to get support for the Supervisory Processor\n \t  device found on several devices in RAVE line of hardware.\n \n+config MFD_RB4XX_CPLD\n+\ttristate \"CPLD driver for Mikrotik RB4xx series boards\"\n+\tselect MFD_CORE\n+\tdepends on ATH79 || COMPILE_TEST\n+\thelp\n+\t  Enables support for the CPLD chip (NAND & GPIO) on Mikrotik\n+\t  Routerboard RB4xx series.\n+\n config SGI_MFD_IOC3\n \ttristate \"SGI IOC3 core driver\"\n \tdepends on PCI && MIPS && 64BIT\n--- a/drivers/mfd/Makefile\n+++ b/drivers/mfd/Makefile\n@@ -264,6 +264,7 @@ obj-$(CONFIG_MFD_ROHM_BD718XX)\t+= rohm-b\n obj-$(CONFIG_MFD_STMFX) \t+= stmfx.o\n obj-$(CONFIG_MFD_KHADAS_MCU) \t+= khadas-mcu.o\n \n+obj-$(CONFIG_MFD_RB4XX_CPLD)\t+= rb4xx-cpld.o\n obj-$(CONFIG_SGI_MFD_IOC3)\t+= ioc3.o\n obj-$(CONFIG_MFD_SIMPLE_MFD_I2C)\t+= simple-mfd-i2c.o\n obj-$(CONFIG_MFD_INTEL_M10_BMC)   += intel-m10-bmc.o\n--- a/drivers/gpio/Kconfig\n+++ b/drivers/gpio/Kconfig\n@@ -1520,6 +1520,12 @@ config GPIO_SODAVILLE\n \thelp\n \t  Say Y here to support Intel Sodaville GPIO.\n \n+config GPIO_RB4XX\n+\ttristate \"GPIO expander for Mikrotik RB4xx series boards\"\n+\tdepends on MFD_RB4XX_CPLD\n+\thelp\n+\t  GPIO driver for Mikrotik Routerboard RB4xx series.\n+\n endmenu\n \n menu \"SPI GPIO expanders\"\n--- a/drivers/gpio/Makefile\n+++ b/drivers/gpio/Makefile\n@@ -121,6 +121,7 @@ obj-$(CONFIG_GPIO_PL061)\t\t+= gpio-pl061.\n obj-$(CONFIG_GPIO_PMIC_EIC_SPRD)\t+= gpio-pmic-eic-sprd.o\n obj-$(CONFIG_GPIO_PXA)\t\t\t+= gpio-pxa.o\n obj-$(CONFIG_GPIO_RASPBERRYPI_EXP)\t+= gpio-raspberrypi-exp.o\n+obj-$(CONFIG_GPIO_RB4XX)\t\t+= gpio-rb4xx.o\n obj-$(CONFIG_GPIO_RC5T583)\t\t+= gpio-rc5t583.o\n obj-$(CONFIG_GPIO_RCAR)\t\t\t+= gpio-rcar.o\n obj-$(CONFIG_GPIO_RDA)\t\t\t+= gpio-rda.o\n--- a/drivers/mtd/nand/raw/Kconfig\n+++ b/drivers/mtd/nand/raw/Kconfig\n@@ -564,4 +564,11 @@ config MTD_NAND_AR934X\n \t  Enables support for NAND controller on Qualcomm Atheros SoCs.\n \t  This controller is found on AR934x and QCA955x SoCs.\n \n+config MTD_NAND_RB4XX\n+\ttristate \"Support for NAND driver for Mikrotik RB4xx series boards\"\n+\tdepends on MFD_RB4XX_CPLD\n+\thelp\n+\t  Enables support for the NAND flash chip on Mikrotik Routerboard\n+\t  RB4xx series.\n+\n endif # MTD_RAW_NAND\n--- a/drivers/mtd/nand/raw/Makefile\n+++ b/drivers/mtd/nand/raw/Makefile\n@@ -59,6 +59,7 @@ obj-$(CONFIG_MTD_NAND_MESON)\t\t+= meson_n\n obj-$(CONFIG_MTD_NAND_CADENCE)\t\t+= cadence-nand-controller.o\n obj-$(CONFIG_MTD_NAND_ARASAN)\t\t+= arasan-nand-controller.o\n obj-$(CONFIG_MTD_NAND_AR934X)\t\t+= ar934x_nand.o\n+obj-$(CONFIG_MTD_NAND_RB4XX)\t\t+= nand_rb4xx.o\n \n nand-objs := nand_base.o nand_legacy.o nand_bbt.o nand_timings.o nand_ids.o\n nand-objs += nand_onfi.o\n"
  },
  {
    "path": "target/linux/ath79/patches-5.10/930-ar8216-make-reg-access-atomic.patch",
    "content": "From b3797d1a92afe97c173b00fdb7824cedba24eef0 Mon Sep 17 00:00:00 2001\nFrom: Chuanhong Guo <gch981213@gmail.com>\nDate: Sun, 20 Sep 2020 01:00:45 +0800\nSubject: [PATCH] ath79: ar8216: make switch register access atomic\n\ndue to some unknown reason these register accesses sometimes fail\non the integrated switch without this patch.\n\nTHIS ONLY WORKS ON ATH79 AND MAY BREAK THE DRIVER ON OTHER PLATFORMS!\nThe mdio bus on ath79 works in polling mode and doesn't rely on\nany interrupt. This patch breaks the driver on any mdio master\nwith interrupts used.\n\n---\n--- a/drivers/net/phy/ar8216.c\n+++ b/drivers/net/phy/ar8216.c\n@@ -252,6 +252,7 @@ ar8xxx_mii_write32(struct ar8xxx_priv *p\n u32\n ar8xxx_read(struct ar8xxx_priv *priv, int reg)\n {\n+\tunsigned long flags;\n \tstruct mii_bus *bus = priv->mii_bus;\n \tu16 r1, r2, page;\n \tu32 val;\n@@ -259,11 +260,13 @@ ar8xxx_read(struct ar8xxx_priv *priv, in\n \tsplit_addr((u32) reg, &r1, &r2, &page);\n \n \tmutex_lock(&bus->mdio_lock);\n+\tlocal_irq_save(flags);\n \n \tbus->write(bus, 0x18, 0, page);\n \twait_for_page_switch();\n \tval = ar8xxx_mii_read32(priv, 0x10 | r2, r1);\n \n+\tlocal_irq_restore(flags);\n \tmutex_unlock(&bus->mdio_lock);\n \n \treturn val;\n@@ -272,17 +275,20 @@ ar8xxx_read(struct ar8xxx_priv *priv, in\n void\n ar8xxx_write(struct ar8xxx_priv *priv, int reg, u32 val)\n {\n+\tunsigned long flags;\n \tstruct mii_bus *bus = priv->mii_bus;\n \tu16 r1, r2, page;\n \n \tsplit_addr((u32) reg, &r1, &r2, &page);\n \n \tmutex_lock(&bus->mdio_lock);\n+\tlocal_irq_save(flags);\n \n \tbus->write(bus, 0x18, 0, page);\n \twait_for_page_switch();\n \tar8xxx_mii_write32(priv, 0x10 | r2, r1, val);\n \n+\tlocal_irq_restore(flags);\n \tmutex_unlock(&bus->mdio_lock);\n }\n \n"
  },
  {
    "path": "target/linux/ath79/patches-5.10/939-mikrotik-rb91x.patch",
    "content": "--- a/drivers/gpio/Kconfig\n+++ b/drivers/gpio/Kconfig\n@@ -341,6 +341,13 @@ config GPIO_IXP4XX\n \t  IXP4xx series of chips.\n \n \t  If unsure, say N.\n+\n+config GPIO_LATCH\n+\ttristate \"MikroTik RouterBOARD GPIO latch support\"\n+\tdepends on ATH79\n+\thelp\n+\t  GPIO driver for latch on some MikroTik RouterBOARDs.\n+\n config GPIO_LOGICVC\n \ttristate \"Xylon LogiCVC GPIO support\"\n \tdepends on MFD_SYSCON && OF\n@@ -495,6 +502,10 @@ config GPIO_REG\n \t  A 32-bit single register GPIO fixed in/out implementation.  This\n \t  can be used to represent any register as a set of GPIO signals.\n \n+config GPIO_RB91X_KEY\n+\ttristate \"MikroTik RB91x board series reset key support\"\n+\tdepends on ATH79\n+\n config GPIO_SAMA5D2_PIOBU\n \ttristate \"SAMA5D2 PIOBU GPIO support\"\n \tdepends on MFD_SYSCON\n--- a/drivers/gpio/Makefile\n+++ b/drivers/gpio/Makefile\n@@ -73,6 +73,7 @@ obj-$(CONFIG_GPIO_IT87)\t\t\t+= gpio-it87.o\n obj-$(CONFIG_GPIO_IXP4XX)\t\t+= gpio-ixp4xx.o\n obj-$(CONFIG_GPIO_JANZ_TTL)\t\t+= gpio-janz-ttl.o\n obj-$(CONFIG_GPIO_KEMPLD)\t\t+= gpio-kempld.o\n+obj-$(CONFIG_GPIO_LATCH)\t\t+= gpio-latch.o\n obj-$(CONFIG_GPIO_LOGICVC)\t\t+= gpio-logicvc.o\n obj-$(CONFIG_GPIO_LOONGSON1)\t\t+= gpio-loongson1.o\n obj-$(CONFIG_GPIO_LOONGSON)\t\t+= gpio-loongson.o\n@@ -122,6 +123,7 @@ obj-$(CONFIG_GPIO_PMIC_EIC_SPRD)\t+= gpio\n obj-$(CONFIG_GPIO_PXA)\t\t\t+= gpio-pxa.o\n obj-$(CONFIG_GPIO_RASPBERRYPI_EXP)\t+= gpio-raspberrypi-exp.o\n obj-$(CONFIG_GPIO_RB4XX)\t\t+= gpio-rb4xx.o\n+obj-$(CONFIG_GPIO_RB91X_KEY)\t\t+= gpio-rb91x-key.o\n obj-$(CONFIG_GPIO_RC5T583)\t\t+= gpio-rc5t583.o\n obj-$(CONFIG_GPIO_RCAR)\t\t\t+= gpio-rcar.o\n obj-$(CONFIG_GPIO_RDA)\t\t\t+= gpio-rda.o\n--- a/drivers/mtd/nand/raw/Kconfig\n+++ b/drivers/mtd/nand/raw/Kconfig\n@@ -571,4 +571,10 @@ config MTD_NAND_RB4XX\n \t  Enables support for the NAND flash chip on Mikrotik Routerboard\n \t  RB4xx series.\n \n+config MTD_NAND_RB91X\n+\ttristate \"MikroTik RB91x NAND driver support\"\n+\tdepends on ATH79 && MTD_RAW_NAND\n+\thelp\n+\t  Enables support for the NAND flash chip on MikroTik RB91x series.\n+\n endif # MTD_RAW_NAND\n--- a/drivers/mtd/nand/raw/Makefile\n+++ b/drivers/mtd/nand/raw/Makefile\n@@ -60,6 +60,7 @@ obj-$(CONFIG_MTD_NAND_CADENCE)\t\t+= caden\n obj-$(CONFIG_MTD_NAND_ARASAN)\t\t+= arasan-nand-controller.o\n obj-$(CONFIG_MTD_NAND_AR934X)\t\t+= ar934x_nand.o\n obj-$(CONFIG_MTD_NAND_RB4XX)\t\t+= nand_rb4xx.o\n+obj-$(CONFIG_MTD_NAND_RB91X)\t\t+= rb91x_nand.o\n \n nand-objs := nand_base.o nand_legacy.o nand_bbt.o nand_timings.o nand_ids.o\n nand-objs += nand_onfi.o\n"
  },
  {
    "path": "target/linux/ath79/patches-5.10/940-ath79-add-support-for-booting-QCN550x.patch",
    "content": "From: Wenli Looi <wlooi@ucalgary.ca>\nDate: Sun, 20 Jun 2021 23:32:28 -0700\nSubject: [PATCH] ath79: add support for booting QCN550x\n\nBased on wikidevi, QCN550x is a \"Dragonfly\" like QCA9561 and QCA9563.\nTreating it as QCA956x seems to work.\nTested on Netgear EX7300v2 which boots successfully with\nthe same CPU clock as the stock firmware.\n\nLink: https://wikidevi.wi-cat.ru/Qualcomm#bgn\nLink: https://wikidevi.wi-cat.ru/Qualcomm_Atheros#.28a.29bgn_2\nSigned-off-by: Wenli Looi <wlooi@ucalgary.ca>\n\n--- a/arch/mips/ath79/early_printk.c\n+++ b/arch/mips/ath79/early_printk.c\n@@ -121,6 +121,7 @@ static void prom_putchar_init(void)\n \tcase REV_ID_MAJOR_QCA9558:\n \tcase REV_ID_MAJOR_TP9343:\n \tcase REV_ID_MAJOR_QCA956X:\n+\tcase REV_ID_MAJOR_QCN550X:\n \t\t_prom_putchar = prom_putchar_ar71xx;\n \t\tbreak;\n \n--- a/arch/mips/ath79/setup.c\n+++ b/arch/mips/ath79/setup.c\n@@ -168,6 +168,12 @@ static void __init ath79_detect_sys_type\n \t\trev = id & QCA956X_REV_ID_REVISION_MASK;\n \t\tbreak;\n \n+\tcase REV_ID_MAJOR_QCN550X:\n+\t\tath79_soc = ATH79_SOC_QCA956X;\n+\t\tchip = \"550X\";\n+\t\trev = id & QCA956X_REV_ID_REVISION_MASK;\n+\t\tbreak;\n+\n \tcase REV_ID_MAJOR_TP9343:\n \t\tath79_soc = ATH79_SOC_TP9343;\n \t\tchip = \"9343\";\n--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h\n+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h\n@@ -867,6 +867,7 @@\n #define REV_ID_MAJOR_QCA9558\t\t0x1130\n #define REV_ID_MAJOR_TP9343\t\t0x0150\n #define REV_ID_MAJOR_QCA956X\t\t0x1150\n+#define REV_ID_MAJOR_QCN550X\t\t0x2170\n \n #define AR71XX_REV_ID_MINOR_MASK\t0x3\n #define AR71XX_REV_ID_MINOR_AR7130\t0x0\n"
  },
  {
    "path": "target/linux/ath79/patches-5.15/0003-leds-add-reset-controller-based-driver.patch",
    "content": "From ecbd9c87f073f097d9fe56390353e64e963e866a Mon Sep 17 00:00:00 2001\nFrom: John Crispin <john@phrozen.org>\nDate: Tue, 6 Mar 2018 10:03:03 +0100\nSubject: [PATCH 03/27] leds: add reset-controller based driver\n\nSigned-off-by: John Crispin <john@phrozen.org>\n---\n drivers/leds/Kconfig      |  11 ++++\n drivers/leds/Makefile     |   1 +\n drivers/leds/leds-reset.c | 137 ++++++++++++++++++++++++++++++++++++++++++++++\n 3 files changed, 149 insertions(+)\n create mode 100644 drivers/leds/leds-reset.c\n\n--- a/drivers/leds/Kconfig\n+++ b/drivers/leds/Kconfig\n@@ -876,6 +876,17 @@ source \"drivers/leds/blink/Kconfig\"\n comment \"Flash and Torch LED drivers\"\n source \"drivers/leds/flash/Kconfig\"\n \n+config LEDS_RESET\n+\ttristate \"LED support for reset-controller API\"\n+\tdepends on LEDS_CLASS\n+\tdepends on RESET_CONTROLLER\n+\thelp\n+\t  This option enables support for LEDs connected to pins driven by reset\n+\t  controllers. Yes, DNI actual built HW like that.\n+\n+\t  To compile this driver as a module, choose M here: the module\n+\t  will be called leds-reset.\n+\n comment \"LED Triggers\"\n source \"drivers/leds/trigger/Kconfig\"\n \n--- /dev/null\n+++ b/drivers/leds/leds-reset.c\n@@ -0,0 +1,140 @@\n+/*\n+ * Copyright (C) 2018 John Crispin <john@phrozen.org>\n+ *\n+ * This program is free software; you can redistribute it and/or modify\n+ * it under the terms of the GNU General Public License version 2 as\n+ * published by the Free Software Foundation.\n+ *\n+ */\n+#include <linux/err.h>\n+#include <linux/reset.h>\n+#include <linux/kernel.h>\n+#include <linux/leds.h>\n+#include <linux/module.h>\n+#include <linux/of.h>\n+#include <linux/platform_device.h>\n+#include <linux/reset.h>\n+\n+struct reset_led_data {\n+\tstruct led_classdev cdev;\n+\tstruct reset_control *rst;\n+};\n+\n+static inline struct reset_led_data *\n+\t\t\tcdev_to_reset_led_data(struct led_classdev *led_cdev)\n+{\n+\treturn container_of(led_cdev, struct reset_led_data, cdev);\n+}\n+\n+static void reset_led_set(struct led_classdev *led_cdev,\n+\tenum led_brightness value)\n+{\n+\tstruct reset_led_data *led_dat = cdev_to_reset_led_data(led_cdev);\n+\n+\tif (value == LED_OFF)\n+\t\treset_control_assert(led_dat->rst);\n+\telse\n+\t\treset_control_deassert(led_dat->rst);\n+}\n+\n+struct reset_leds_priv {\n+\tint num_leds;\n+\tstruct reset_led_data leds[];\n+};\n+\n+static inline int sizeof_reset_leds_priv(int num_leds)\n+{\n+\treturn sizeof(struct reset_leds_priv) +\n+\t\t(sizeof(struct reset_led_data) * num_leds);\n+}\n+\n+static struct reset_leds_priv *reset_leds_create(struct platform_device *pdev)\n+{\n+\tstruct device *dev = &pdev->dev;\n+\tstruct fwnode_handle *child;\n+\tstruct reset_leds_priv *priv;\n+\tint count, ret;\n+\n+\tcount = device_get_child_node_count(dev);\n+\tif (!count)\n+\t\treturn ERR_PTR(-ENODEV);\n+\n+\tpriv = devm_kzalloc(dev, sizeof_reset_leds_priv(count), GFP_KERNEL);\n+\tif (!priv)\n+\t\treturn ERR_PTR(-ENOMEM);\n+\n+\tdevice_for_each_child_node(dev, child) {\n+\t\tstruct reset_led_data *led = &priv->leds[priv->num_leds];\n+\t\tstruct device_node *np = to_of_node(child);\n+\n+\t\tret = fwnode_property_read_string(child, \"label\", &led->cdev.name);\n+\t\tif (!led->cdev.name) {\n+\t\t\tfwnode_handle_put(child);\n+\t\t\treturn ERR_PTR(-EINVAL);\n+\t\t}\n+\t\tled->rst = __of_reset_control_get(np, NULL, 0, 0, 0, true);\n+\t\tif (IS_ERR(led->rst))\n+\t\t\treturn ERR_PTR(-EINVAL);\n+\n+\t\tfwnode_property_read_string(child, \"linux,default-trigger\",\n+\t\t\t\t\t\t&led->cdev.default_trigger);\n+\n+\t\tled->cdev.brightness_set = reset_led_set;\n+\t\tret = devm_led_classdev_register(&pdev->dev, &led->cdev);\n+\t\tif (ret < 0)\n+\t\t\treturn ERR_PTR(ret);\n+\t\tled->cdev.dev->of_node = np;\n+\t\tpriv->num_leds++;\n+\t}\n+\n+\treturn priv;\n+}\n+\n+static const struct of_device_id of_reset_leds_match[] = {\n+\t{ .compatible = \"reset-leds\", },\n+\t{},\n+};\n+\n+MODULE_DEVICE_TABLE(of, of_reset_leds_match);\n+\n+static int reset_led_probe(struct platform_device *pdev)\n+{\n+\tstruct reset_leds_priv *priv;\n+\n+\tpriv = reset_leds_create(pdev);\n+\tif (IS_ERR(priv))\n+\t\treturn PTR_ERR(priv);\n+\n+\tplatform_set_drvdata(pdev, priv);\n+\n+\treturn 0;\n+}\n+\n+static void reset_led_shutdown(struct platform_device *pdev)\n+{\n+\tstruct reset_leds_priv *priv = platform_get_drvdata(pdev);\n+\tint i;\n+\n+\tfor (i = 0; i < priv->num_leds; i++) {\n+\t\tstruct reset_led_data *led = &priv->leds[i];\n+\n+\t\tif (!(led->cdev.flags & LED_RETAIN_AT_SHUTDOWN))\n+\t\t\treset_led_set(&led->cdev, LED_OFF);\n+\t}\n+}\n+\n+static struct platform_driver reset_led_driver = {\n+\t.probe\t\t= reset_led_probe,\n+\t.shutdown\t= reset_led_shutdown,\n+\t.driver\t\t= {\n+\t\t.name\t= \"leds-reset\",\n+\t\t.of_match_table = of_reset_leds_match,\n+\t},\n+};\n+\n+module_platform_driver(reset_led_driver);\n+\n+MODULE_AUTHOR(\"John Crispin <john@phrozen.org>\");\n+MODULE_DESCRIPTION(\"reset controller LED driver\");\n+MODULE_LICENSE(\"GPL\");\n+MODULE_ALIAS(\"platform:leds-reset\");\n--- a/drivers/leds/Makefile\n+++ b/drivers/leds/Makefile\n@@ -87,6 +87,7 @@ obj-$(CONFIG_LEDS_TURRIS_OMNIA)\t\t+= leds\n obj-$(CONFIG_LEDS_WM831X_STATUS)\t+= leds-wm831x-status.o\n obj-$(CONFIG_LEDS_WM8350)\t\t+= leds-wm8350.o\n obj-$(CONFIG_LEDS_WRAP)\t\t\t+= leds-wrap.o\n+obj-$(CONFIG_LEDS_RESET)\t\t+= leds-reset.o\n \n # LED SPI Drivers\n obj-$(CONFIG_LEDS_CR0014114)\t\t+= leds-cr0014114.o\n"
  },
  {
    "path": "target/linux/ath79/patches-5.15/0004-phy-add-ath79-usb-phys.patch",
    "content": "From 08c9d6ceef01893678a5d2e8a15517c745417f21 Mon Sep 17 00:00:00 2001\nFrom: John Crispin <john@phrozen.org>\nDate: Tue, 6 Mar 2018 10:04:05 +0100\nSubject: [PATCH 04/27] phy: add ath79 usb phys\n\nSigned-off-by: John Crispin <john@phrozen.org>\n---\n drivers/phy/Kconfig          |  16 ++++++\n drivers/phy/Makefile         |   2 +\n drivers/phy/phy-ar7100-usb.c | 124 +++++++++++++++++++++++++++++++++++++++++++\n drivers/phy/phy-ar7200-usb.c | 108 +++++++++++++++++++++++++++++++++++++\n 4 files changed, 250 insertions(+)\n create mode 100644 drivers/phy/phy-ar7100-usb.c\n create mode 100644 drivers/phy/phy-ar7200-usb.c\n\n--- a/drivers/phy/Kconfig\n+++ b/drivers/phy/Kconfig\n@@ -24,6 +24,22 @@ config GENERIC_PHY_MIPI_DPHY\n \t  Provides a number of helpers a core functions for MIPI D-PHY\n \t  drivers to us.\n \n+config PHY_AR7100_USB\n+\ttristate \"Atheros AR7100 USB PHY driver\"\n+\tdepends on ATH79 || COMPILE_TEST\n+\tdefault y if USB_EHCI_HCD_PLATFORM\n+\tselect GENERIC_PHY\n+\thelp\n+\t  Enable this to support the USB PHY on Atheros AR7100 SoCs.\n+\n+config PHY_AR7200_USB\n+\ttristate \"Atheros AR7200 USB PHY driver\"\n+\tdepends on ATH79 || COMPILE_TEST\n+\tdefault y if USB_EHCI_HCD_PLATFORM\n+\tselect GENERIC_PHY\n+\thelp\n+\t  Enable this to support the USB PHY on Atheros AR7200 SoCs.\n+\n config PHY_LPC18XX_USB_OTG\n \ttristate \"NXP LPC18xx/43xx SoC USB OTG PHY driver\"\n \tdepends on OF && (ARCH_LPC18XX || COMPILE_TEST)\n--- a/drivers/phy/Makefile\n+++ b/drivers/phy/Makefile\n@@ -4,6 +4,8 @@\n #\n \n obj-$(CONFIG_GENERIC_PHY)\t\t+= phy-core.o\n+obj-$(CONFIG_PHY_AR7100_USB)\t\t+= phy-ar7100-usb.o\n+obj-$(CONFIG_PHY_AR7200_USB)\t\t+= phy-ar7200-usb.o\n obj-$(CONFIG_GENERIC_PHY_MIPI_DPHY)\t+= phy-core-mipi-dphy.o\n obj-$(CONFIG_PHY_CAN_TRANSCEIVER)\t+= phy-can-transceiver.o\n obj-$(CONFIG_PHY_LPC18XX_USB_OTG)\t+= phy-lpc18xx-usb-otg.o\n--- /dev/null\n+++ b/drivers/phy/phy-ar7100-usb.c\n@@ -0,0 +1,140 @@\n+/*\n+ * Copyright (C) 2018 John Crispin <john@phrozen.org>\n+ *\n+ * This program is free software; you can redistribute it and/or modify\n+ * it under the terms of the GNU General Public License as published by\n+ * the Free Software Foundation; either version 2 of the License, or\n+ * (at your option) any later version.\n+ */\n+\n+#include <linux/module.h>\n+#include <linux/platform_device.h>\n+#include <linux/phy/phy.h>\n+#include <linux/delay.h>\n+#include <linux/reset.h>\n+#include <linux/of_gpio.h>\n+\n+#include <asm/mach-ath79/ath79.h>\n+#include <asm/mach-ath79/ar71xx_regs.h>\n+\n+struct ar7100_usb_phy {\n+\tstruct reset_control\t*rst_phy;\n+\tstruct reset_control\t*rst_host;\n+\tstruct reset_control\t*rst_ohci_dll;\n+\tvoid __iomem\t\t*io_base;\n+\tstruct phy\t\t*phy;\n+\tint\t\t\tgpio;\n+};\n+\n+static int ar7100_usb_phy_power_off(struct phy *phy)\n+{\n+\tstruct ar7100_usb_phy *priv = phy_get_drvdata(phy);\n+\tint err = 0;\n+\n+\terr |= reset_control_assert(priv->rst_host);\n+\terr |= reset_control_assert(priv->rst_phy);\n+\terr |= reset_control_assert(priv->rst_ohci_dll);\n+\n+\treturn err;\n+}\n+\n+static int ar7100_usb_phy_power_on(struct phy *phy)\n+{\n+\tstruct ar7100_usb_phy *priv = phy_get_drvdata(phy);\n+\tint err = 0;\n+\n+\terr |= ar7100_usb_phy_power_off(phy);\n+\tmdelay(100);\n+\terr |= reset_control_deassert(priv->rst_ohci_dll);\n+\terr |= reset_control_deassert(priv->rst_phy);\n+\terr |= reset_control_deassert(priv->rst_host);\n+\tmdelay(500);\n+\tiowrite32(0xf0000, priv->io_base + AR71XX_USB_CTRL_REG_CONFIG);\n+\tiowrite32(0x20c00, priv->io_base + AR71XX_USB_CTRL_REG_FLADJ);\n+\n+\treturn err;\n+}\n+\n+static const struct phy_ops ar7100_usb_phy_ops = {\n+\t.power_on\t= ar7100_usb_phy_power_on,\n+\t.power_off\t= ar7100_usb_phy_power_off,\n+\t.owner\t\t= THIS_MODULE,\n+};\n+\n+static int ar7100_usb_phy_probe(struct platform_device *pdev)\n+{\n+\tstruct phy_provider *phy_provider;\n+\tstruct resource *res;\n+\tstruct ar7100_usb_phy *priv;\n+\n+\tpriv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);\n+\tif (!priv)\n+\t\treturn -ENOMEM;\n+\n+\tres = platform_get_resource(pdev, IORESOURCE_MEM, 0);\n+\tpriv->io_base = devm_ioremap_resource(&pdev->dev, res);\n+\tif (IS_ERR(priv->io_base))\n+\t\treturn PTR_ERR(priv->io_base);\n+\n+\tpriv->rst_phy = devm_reset_control_get(&pdev->dev, \"usb-phy\");\n+\tif (IS_ERR(priv->rst_phy)) {\n+\t\tdev_err(&pdev->dev, \"phy reset is missing\\n\");\n+\t\treturn PTR_ERR(priv->rst_phy);\n+\t}\n+\n+\tpriv->rst_host = devm_reset_control_get(&pdev->dev, \"usb-host\");\n+\tif (IS_ERR(priv->rst_host)) {\n+\t\tdev_err(&pdev->dev, \"host reset is missing\\n\");\n+\t\treturn PTR_ERR(priv->rst_host);\n+\t}\n+\n+\tpriv->rst_ohci_dll = devm_reset_control_get(&pdev->dev, \"usb-ohci-dll\");\n+\tif (IS_ERR(priv->rst_ohci_dll)) {\n+\t\tdev_err(&pdev->dev, \"ohci-dll reset is missing\\n\");\n+\t\treturn PTR_ERR(priv->rst_host);\n+\t}\n+\n+\tpriv->phy = devm_phy_create(&pdev->dev, NULL, &ar7100_usb_phy_ops);\n+\tif (IS_ERR(priv->phy)) {\n+\t\tdev_err(&pdev->dev, \"failed to create PHY\\n\");\n+\t\treturn PTR_ERR(priv->phy);\n+\t}\n+\n+\tpriv->gpio = of_get_gpio(pdev->dev.of_node, 0);\n+\tif (priv->gpio >= 0) {\n+\t\tint ret = devm_gpio_request(&pdev->dev, priv->gpio, dev_name(&pdev->dev));\n+\n+\t\tif (ret) {\n+\t\t\tdev_err(&pdev->dev, \"failed to request gpio\\n\");\n+\t\t\treturn ret;\n+\t\t}\n+\t\tgpio_export_with_name(priv->gpio, 0, dev_name(&pdev->dev));\n+\t\tgpio_set_value(priv->gpio, 1);\n+\t}\n+\n+\tphy_set_drvdata(priv->phy, priv);\n+\n+\tphy_provider = devm_of_phy_provider_register(&pdev->dev, of_phy_simple_xlate);\n+\n+\n+\treturn PTR_ERR_OR_ZERO(phy_provider);\n+}\n+\n+static const struct of_device_id ar7100_usb_phy_of_match[] = {\n+\t{ .compatible = \"qca,ar7100-usb-phy\" },\n+\t{}\n+};\n+MODULE_DEVICE_TABLE(of, ar7100_usb_phy_of_match);\n+\n+static struct platform_driver ar7100_usb_phy_driver = {\n+\t.probe\t= ar7100_usb_phy_probe,\n+\t.driver = {\n+\t\t.of_match_table\t= ar7100_usb_phy_of_match,\n+\t\t.name\t\t= \"ar7100-usb-phy\",\n+\t}\n+};\n+module_platform_driver(ar7100_usb_phy_driver);\n+\n+MODULE_DESCRIPTION(\"ATH79 USB PHY driver\");\n+MODULE_AUTHOR(\"Alban Bedel <albeu@free.fr>\");\n+MODULE_LICENSE(\"GPL\");\n--- /dev/null\n+++ b/drivers/phy/phy-ar7200-usb.c\n@@ -0,0 +1,136 @@\n+/*\n+ * Copyright (C) 2015 Alban Bedel <albeu@free.fr>\n+ *\n+ * This program is free software; you can redistribute it and/or modify\n+ * it under the terms of the GNU General Public License as published by\n+ * the Free Software Foundation; either version 2 of the License, or\n+ * (at your option) any later version.\n+ */\n+\n+#include <linux/module.h>\n+#include <linux/platform_device.h>\n+#include <linux/phy/phy.h>\n+#include <linux/reset.h>\n+#include <linux/of_gpio.h>\n+\n+struct ar7200_usb_phy {\n+\tstruct reset_control\t*rst_phy;\n+\tstruct reset_control\t*rst_phy_analog;\n+\tstruct reset_control\t*suspend_override;\n+\tstruct phy\t\t*phy;\n+\tint\t\t\tgpio;\n+};\n+\n+static int ar7200_usb_phy_power_on(struct phy *phy)\n+{\n+\tstruct ar7200_usb_phy *priv = phy_get_drvdata(phy);\n+\tint err = 0;\n+\n+\tif (priv->suspend_override)\n+\t\terr = reset_control_assert(priv->suspend_override);\n+\tif (priv->rst_phy)\n+\t\terr |= reset_control_deassert(priv->rst_phy);\n+\tif (priv->rst_phy_analog)\n+\t\terr |= reset_control_deassert(priv->rst_phy_analog);\n+\n+\treturn err;\n+}\n+\n+static int ar7200_usb_phy_power_off(struct phy *phy)\n+{\n+\tstruct ar7200_usb_phy *priv = phy_get_drvdata(phy);\n+\tint err = 0;\n+\n+\tif (priv->suspend_override)\n+\t\terr = reset_control_deassert(priv->suspend_override);\n+\tif (priv->rst_phy)\n+\t\terr |= reset_control_assert(priv->rst_phy);\n+\tif (priv->rst_phy_analog)\n+\t\terr |= reset_control_assert(priv->rst_phy_analog);\n+\n+\treturn err;\n+}\n+\n+static const struct phy_ops ar7200_usb_phy_ops = {\n+\t.power_on\t= ar7200_usb_phy_power_on,\n+\t.power_off\t= ar7200_usb_phy_power_off,\n+\t.owner\t\t= THIS_MODULE,\n+};\n+\n+static int ar7200_usb_phy_probe(struct platform_device *pdev)\n+{\n+\tstruct phy_provider *phy_provider;\n+\tstruct ar7200_usb_phy *priv;\n+\n+\tpriv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);\n+\tif (!priv)\n+\t\treturn -ENOMEM;\n+\n+\tpriv->rst_phy = devm_reset_control_get(&pdev->dev, \"usb-phy\");\n+\tif (IS_ERR(priv->rst_phy)) {\n+\t\tif (PTR_ERR(priv->rst_phy) != -EPROBE_DEFER)\n+\t\t\tdev_err(&pdev->dev, \"phy reset is missing\\n\");\n+\t\treturn PTR_ERR(priv->rst_phy);\n+\t}\n+\n+\tpriv->rst_phy_analog = devm_reset_control_get_optional(\n+\t\t&pdev->dev, \"usb-phy-analog\");\n+\tif (IS_ERR(priv->rst_phy_analog)) {\n+\t\tif (PTR_ERR(priv->rst_phy_analog) == -ENOENT)\n+\t\t\tpriv->rst_phy_analog = NULL;\n+\t\telse\n+\t\t\treturn PTR_ERR(priv->rst_phy_analog);\n+\t}\n+\n+\tpriv->suspend_override = devm_reset_control_get_optional(\n+\t\t&pdev->dev, \"usb-suspend-override\");\n+\tif (IS_ERR(priv->suspend_override)) {\n+\t\tif (PTR_ERR(priv->suspend_override) == -ENOENT)\n+\t\t\tpriv->suspend_override = NULL;\n+\t\telse\n+\t\t\treturn PTR_ERR(priv->suspend_override);\n+\t}\n+\n+\tpriv->phy = devm_phy_create(&pdev->dev, NULL, &ar7200_usb_phy_ops);\n+\tif (IS_ERR(priv->phy)) {\n+\t\tdev_err(&pdev->dev, \"failed to create PHY\\n\");\n+\t\treturn PTR_ERR(priv->phy);\n+\t}\n+\n+\tpriv->gpio = of_get_gpio(pdev->dev.of_node, 0);\n+\tif (priv->gpio >= 0) {\n+\t\tint ret = devm_gpio_request(&pdev->dev, priv->gpio, dev_name(&pdev->dev));\n+\n+\t\tif (ret) {\n+\t\t\tdev_err(&pdev->dev, \"failed to request gpio\\n\");\n+\t\t\treturn ret;\n+\t\t}\n+\t\tgpio_export_with_name(priv->gpio, 0, dev_name(&pdev->dev));\n+\t\tgpio_set_value(priv->gpio, 1);\n+\t}\n+\n+\tphy_set_drvdata(priv->phy, priv);\n+\n+\tphy_provider = devm_of_phy_provider_register(&pdev->dev, of_phy_simple_xlate);\n+\n+\treturn PTR_ERR_OR_ZERO(phy_provider);\n+}\n+\n+static const struct of_device_id ar7200_usb_phy_of_match[] = {\n+\t{ .compatible = \"qca,ar7200-usb-phy\" },\n+\t{}\n+};\n+MODULE_DEVICE_TABLE(of, ar7200_usb_phy_of_match);\n+\n+static struct platform_driver ar7200_usb_phy_driver = {\n+\t.probe\t= ar7200_usb_phy_probe,\n+\t.driver = {\n+\t\t.of_match_table\t= ar7200_usb_phy_of_match,\n+\t\t.name\t\t= \"ar7200-usb-phy\",\n+\t}\n+};\n+module_platform_driver(ar7200_usb_phy_driver);\n+\n+MODULE_DESCRIPTION(\"ATH79 USB PHY driver\");\n+MODULE_AUTHOR(\"Alban Bedel <albeu@free.fr>\");\n+MODULE_LICENSE(\"GPL\");\n"
  },
  {
    "path": "target/linux/ath79/patches-5.15/0005-usb-add-more-OF-quirk-properties.patch",
    "content": "From 2201818e5bd33f389beceb3943fdfcf5a698fc5b Mon Sep 17 00:00:00 2001\nFrom: John Crispin <john@phrozen.org>\nDate: Tue, 6 Mar 2018 10:01:43 +0100\nSubject: [PATCH 05/27] usb: add more OF/quirk properties\n\nSigned-off-by: John Crispin <john@phrozen.org>\n---\n drivers/usb/host/ehci-platform.c | 5 +++++\n 1 file changed, 5 insertions(+)\n\n--- a/drivers/usb/host/ehci-platform.c\n+++ b/drivers/usb/host/ehci-platform.c\n@@ -277,6 +277,11 @@ static int ehci_platform_probe(struct pl\n \tehci = hcd_to_ehci(hcd);\n \n \tif (pdata == &ehci_platform_defaults && dev->dev.of_node) {\n+\t\tof_property_read_u32(dev->dev.of_node, \"caps-offset\", &pdata->caps_offset);\n+\n+\t\tif (of_property_read_bool(dev->dev.of_node, \"has-synopsys-hc-bug\"))\n+\t\t\tpdata->has_synopsys_hc_bug = 1;\n+\n \t\tif (of_property_read_bool(dev->dev.of_node, \"big-endian-regs\"))\n \t\t\tehci->big_endian_mmio = 1;\n \n"
  },
  {
    "path": "target/linux/ath79/patches-5.15/0007-irqchip-irq-ath79-intc-add-irq-cascade-driver-for-QC.patch",
    "content": "From f3eacff2310a60348a755c50a8da6fc251fc8587 Mon Sep 17 00:00:00 2001\nFrom: John Crispin <john@phrozen.org>\nDate: Tue, 6 Mar 2018 09:55:13 +0100\nSubject: [PATCH 07/33] irqchip/irq-ath79-intc: add irq cascade driver for\n QCA9556 SoCs\n\nSigned-off-by: John Crispin <john@phrozen.org>\n---\n drivers/irqchip/Makefile         |   1 +\n drivers/irqchip/irq-ath79-intc.c | 142 +++++++++++++++++++++++++++++++++++++++\n 2 files changed, 143 insertions(+)\n create mode 100644 drivers/irqchip/irq-ath79-intc.c\n\n--- a/drivers/irqchip/Makefile\n+++ b/drivers/irqchip/Makefile\n@@ -4,6 +4,7 @@ obj-$(CONFIG_IRQCHIP)\t\t\t+= irqchip.o\n obj-$(CONFIG_AL_FIC)\t\t\t+= irq-al-fic.o\n obj-$(CONFIG_ALPINE_MSI)\t\t+= irq-alpine-msi.o\n obj-$(CONFIG_ATH79)\t\t\t+= irq-ath79-cpu.o\n+obj-$(CONFIG_ATH79)\t\t\t+= irq-ath79-intc.o\n obj-$(CONFIG_ATH79)\t\t\t+= irq-ath79-misc.o\n obj-$(CONFIG_ARCH_BCM2835)\t\t+= irq-bcm2835.o\n obj-$(CONFIG_ARCH_BCM2835)\t\t+= irq-bcm2836.o\n--- /dev/null\n+++ b/drivers/irqchip/irq-ath79-intc.c\n@@ -0,0 +1,142 @@\n+/*\n+ *  Atheros AR71xx/AR724x/AR913x specific interrupt handling\n+ *\n+ *  Copyright (C) 2018 John Crispin <john@phrozen.org>\n+ *\n+ *  This program is free software; you can redistribute it and/or modify it\n+ *  under the terms of the GNU General Public License version 2 as published\n+ *  by the Free Software Foundation.\n+ */\n+\n+#include <linux/interrupt.h>\n+#include <linux/irqchip.h>\n+#include <linux/of.h>\n+#include <linux/of_irq.h>\n+#include <linux/irqdomain.h>\n+\n+#include <asm/irq_cpu.h>\n+#include <asm/mach-ath79/ath79.h>\n+#include <asm/mach-ath79/ar71xx_regs.h>\n+\n+#define ATH79_MAX_INTC_CASCADE\t3\n+\n+struct ath79_intc {\n+\tstruct irq_chip chip;\n+\tu32 irq;\n+\tu32 pending_mask;\n+\tu32 int_status;\n+\tu32 irq_mask[ATH79_MAX_INTC_CASCADE];\n+\tu32 irq_wb_chan[ATH79_MAX_INTC_CASCADE];\n+};\n+\n+static void ath79_intc_irq_handler(struct irq_desc *desc)\n+{\n+\tstruct irq_domain *domain = irq_desc_get_handler_data(desc);\n+\tstruct ath79_intc *intc = domain->host_data;\n+\tu32 pending;\n+\n+\tpending = ath79_reset_rr(intc->int_status);\n+\tpending &= intc->pending_mask;\n+\n+\tif (pending) {\n+\t\tint i;\n+\n+\t\tfor (i = 0; i < domain->hwirq_max; i++)\n+\t\t\tif (pending & intc->irq_mask[i]) {\n+\t\t\t\tif (intc->irq_wb_chan[i] != 0xffffffff)\n+\t\t\t\t\tath79_ddr_wb_flush(intc->irq_wb_chan[i]);\n+\t\t\t\tgeneric_handle_irq(irq_find_mapping(domain, i));\n+\t\t\t}\n+\t} else {\n+\t\tspurious_interrupt();\n+\t}\n+}\n+\n+static void ath79_intc_irq_enable(struct irq_data *d)\n+{\n+\tstruct ath79_intc *intc = d->domain->host_data;\n+\tenable_irq(intc->irq);\n+}\n+\n+static void ath79_intc_irq_disable(struct irq_data *d)\n+{\n+\tstruct ath79_intc *intc = d->domain->host_data;\n+\tdisable_irq(intc->irq);\n+}\n+\n+static int ath79_intc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)\n+{\n+\tstruct ath79_intc *intc = d->host_data;\n+\n+\tirq_set_chip_and_handler(irq, &intc->chip, handle_level_irq);\n+\n+\treturn 0;\n+}\n+\n+static const struct irq_domain_ops ath79_irq_domain_ops = {\n+\t.xlate = irq_domain_xlate_onecell,\n+\t.map = ath79_intc_map,\n+};\n+\n+static int __init ath79_intc_of_init(\n+\tstruct device_node *node, struct device_node *parent)\n+{\n+\tstruct irq_domain *domain;\n+\tstruct ath79_intc *intc;\n+\tint cnt, cntwb, i, err;\n+\n+\tcnt = of_property_count_u32_elems(node, \"qca,pending-bits\");\n+\tif (cnt > ATH79_MAX_INTC_CASCADE)\n+\t\tpanic(\"Too many INTC pending bits\\n\");\n+\n+\tintc = kzalloc(sizeof(*intc), GFP_KERNEL);\n+\tif (!intc)\n+\t\tpanic(\"Failed to allocate INTC memory\\n\");\n+\tintc->chip = dummy_irq_chip;\n+\tintc->chip.name = \"INTC\";\n+\tintc->chip.irq_disable = ath79_intc_irq_disable;\n+\tintc->chip.irq_enable = ath79_intc_irq_enable;\n+\n+\tif (of_property_read_u32(node, \"qca,int-status-addr\", &intc->int_status) < 0) {\n+\t\tpanic(\"Missing address of interrupt status register\\n\");\n+\t}\n+\n+\tof_property_read_u32_array(node, \"qca,pending-bits\", intc->irq_mask, cnt);\n+\tfor (i = 0; i < cnt; i++) {\n+\t\tintc->pending_mask |= intc->irq_mask[i];\n+\t\tintc->irq_wb_chan[i] = 0xffffffff;\n+\t}\n+\n+\tcntwb = of_count_phandle_with_args(\n+\t\tnode, \"qca,ddr-wb-channels\", \"#qca,ddr-wb-channel-cells\");\n+\n+\tfor (i = 0; i < cntwb; i++) {\n+\t\tstruct of_phandle_args args;\n+\t\tu32 irq = i;\n+\n+\t\tof_property_read_u32_index(\n+\t\t\tnode, \"qca,ddr-wb-channel-interrupts\", i, &irq);\n+\t\tif (irq >= ATH79_MAX_INTC_CASCADE)\n+\t\t\tcontinue;\n+\n+\t\terr = of_parse_phandle_with_args(\n+\t\t\tnode, \"qca,ddr-wb-channels\",\n+\t\t\t\"#qca,ddr-wb-channel-cells\",\n+\t\t\ti, &args);\n+\t\tif (err)\n+\t\t\treturn err;\n+\n+\t\tintc->irq_wb_chan[irq] = args.args[0];\n+\t}\n+\n+\tintc->irq = irq_of_parse_and_map(node, 0);\n+\tif (!intc->irq)\n+\t\tpanic(\"Failed to get INTC IRQ\");\n+\n+\tdomain = irq_domain_add_linear(node, cnt, &ath79_irq_domain_ops, intc);\n+\tirq_set_chained_handler_and_data(intc->irq, ath79_intc_irq_handler, domain);\n+\n+\treturn 0;\n+}\n+IRQCHIP_DECLARE(ath79_intc, \"qca,ar9340-intc\",\n+\t\tath79_intc_of_init);\n"
  },
  {
    "path": "target/linux/ath79/patches-5.15/0008-irqchip-irq-ath79-cpu-drop-OF-init-helper.patch",
    "content": "From e029f998594f151008ecbfa024e2957edd2a5189 Mon Sep 17 00:00:00 2001\nFrom: John Crispin <john@phrozen.org>\nDate: Tue, 6 Mar 2018 09:58:19 +0100\nSubject: [PATCH 08/33] irqchip/irq-ath79-cpu: drop !OF init helper\n\nSigned-off-by: John Crispin <john@phrozen.org>\n---\n drivers/irqchip/irq-ath79-cpu.c | 7 -------\n 1 file changed, 7 deletions(-)\n\n--- a/drivers/irqchip/irq-ath79-cpu.c\n+++ b/drivers/irqchip/irq-ath79-cpu.c\n@@ -85,10 +85,3 @@ static int __init ar79_cpu_intc_of_init(\n }\n IRQCHIP_DECLARE(ar79_cpu_intc, \"qca,ar7100-cpu-intc\",\n \t\tar79_cpu_intc_of_init);\n-\n-void __init ath79_cpu_irq_init(unsigned irq_wb_chan2, unsigned irq_wb_chan3)\n-{\n-\tirq_wb_chan[2] = irq_wb_chan2;\n-\tirq_wb_chan[3] = irq_wb_chan3;\n-\tmips_cpu_irq_init();\n-}\n"
  },
  {
    "path": "target/linux/ath79/patches-5.15/0017-dt-bindings-PCI-qcom-ar7100-adds-binding-doc.patch",
    "content": "From 4a4f869ec58ed8910b9b2e68d0eee50957e9bb20 Mon Sep 17 00:00:00 2001\nFrom: John Crispin <john@phrozen.org>\nDate: Mon, 25 Jun 2018 15:52:10 +0200\nSubject: [PATCH 17/33] dt-bindings: PCI: qcom,ar7100: adds binding doc\n\nWith the driver being converted from platform_data to pure OF, we need to\nalso add some docs.\n\nCc: Rob Herring <robh+dt@kernel.org>\nCc: devicetree@vger.kernel.org\nSigned-off-by: John Crispin <john@phrozen.org>\n---\n .../devicetree/bindings/pci/qcom,ar7100-pci.txt    | 38 ++++++++++++++++++++++\n 1 file changed, 38 insertions(+)\n create mode 100644 Documentation/devicetree/bindings/pci/qcom,ar7100-pci.txt\n\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/pci/qcom,ar7100-pci.txt\n@@ -0,0 +1,38 @@\n+* Qualcomm Atheros AR7100 PCI express root complex\n+\n+Required properties:\n+- compatible: should contain \"qcom,ar7100-pci\" to identify the core.\n+- reg: Should contain the register ranges as listed in the reg-names property.\n+- reg-names: Definition: Must include the following entries\n+\t- \"cfg_base\"\tIO Memory\n+- #address-cells: set to <3>\n+- #size-cells: set to <2>\n+- ranges: ranges for the PCI memory and I/O regions\n+- interrupt-map-mask and interrupt-map: standard PCI\n+\tproperties to define the mapping of the PCIe interface to interrupt\n+\tnumbers.\n+- #interrupt-cells: set to <1>\n+- interrupt-controller: define to enable the builtin IRQ cascade.\n+\n+Optional properties:\n+- interrupt-parent: phandle to the MIPS IRQ controller\n+\n+* Example for ar7100\n+\tpcie-controller@180c0000 {\n+\t\tcompatible = \"qca,ar7100-pci\";\n+\t\t#address-cells = <3>;\n+\t\t#size-cells = <2>;\n+\t\tbus-range = <0x0 0x0>;\n+\t\treg = <0x17010000 0x100>;\n+\t\treg-names = \"cfg_base\";\n+\t\tranges = <0x2000000 0 0x10000000 0x10000000 0 0x07000000\n+\t\t\t  0x1000000 0 0x00000000 0x00000000 0 0x00000001>;\n+\t\tinterrupt-parent = <&cpuintc>;\n+\t\tinterrupts = <2>;\n+\n+\t\tinterrupt-controller;\n+\t\t#interrupt-cells = <1>;\n+\n+\t\tinterrupt-map-mask = <0 0 0 1>;\n+\t\tinterrupt-map = <0 0 0 0 &pcie0 0>;\n+\t};\n"
  },
  {
    "path": "target/linux/ath79/patches-5.15/0018-MIPS-pci-ar71xx-convert-to-OF.patch",
    "content": "From 1855ab6b1d27f5b38a648baf57ff6a534afec26d Mon Sep 17 00:00:00 2001\nFrom: John Crispin <john@phrozen.org>\nDate: Sat, 23 Jun 2018 15:07:23 +0200\nSubject: [PATCH 18/33] MIPS: pci-ar71xx: convert to OF\n\nWith the ath79 target getting converted to pure OF, we can drop all the\nplatform data code and add the missing OF bits to the driver. We also add\na irq domain for the PCI/e controllers cascade, thus making it usable from\ndts files.\n\nSigned-off-by: John Crispin <john@phrozen.org>\n---\n arch/mips/pci/pci-ar71xx.c | 82 +++++++++++++++++++++++-----------------------\n 1 file changed, 41 insertions(+), 41 deletions(-)\n\n--- a/arch/mips/pci/pci-ar71xx.c\n+++ b/arch/mips/pci/pci-ar71xx.c\n@@ -15,8 +15,11 @@\n #include <linux/pci.h>\n #include <linux/pci_regs.h>\n #include <linux/interrupt.h>\n+#include <linux/irqchip/chained_irq.h>\n #include <linux/init.h>\n #include <linux/platform_device.h>\n+#include <linux/of_irq.h>\n+#include <linux/of_pci.h>\n \n #include <asm/mach-ath79/ar71xx_regs.h>\n #include <asm/mach-ath79/ath79.h>\n@@ -46,12 +49,13 @@\n #define AR71XX_PCI_IRQ_COUNT\t\t5\n \n struct ar71xx_pci_controller {\n+\tstruct device_node *np;\n \tvoid __iomem *cfg_base;\n \tint irq;\n-\tint irq_base;\n \tstruct pci_controller pci_ctrl;\n \tstruct resource io_res;\n \tstruct resource mem_res;\n+\tstruct irq_domain *domain;\n };\n \n /* Byte lane enable bits */\n@@ -225,29 +229,30 @@ static struct pci_ops ar71xx_pci_ops = {\n \n static void ar71xx_pci_irq_handler(struct irq_desc *desc)\n {\n-\tstruct ar71xx_pci_controller *apc;\n \tvoid __iomem *base = ath79_reset_base;\n+\tstruct irq_chip *chip = irq_desc_get_chip(desc);\n+\tstruct ar71xx_pci_controller *apc = irq_desc_get_handler_data(desc);\n \tu32 pending;\n \n-\tapc = irq_desc_get_handler_data(desc);\n-\n+\tchained_irq_enter(chip, desc);\n \tpending = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_STATUS) &\n \t\t  __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);\n \n \tif (pending & AR71XX_PCI_INT_DEV0)\n-\t\tgeneric_handle_irq(apc->irq_base + 0);\n+\t\tgeneric_handle_irq(irq_linear_revmap(apc->domain, 1));\n \n \telse if (pending & AR71XX_PCI_INT_DEV1)\n-\t\tgeneric_handle_irq(apc->irq_base + 1);\n+\t\tgeneric_handle_irq(irq_linear_revmap(apc->domain, 2));\n \n \telse if (pending & AR71XX_PCI_INT_DEV2)\n-\t\tgeneric_handle_irq(apc->irq_base + 2);\n+\t\tgeneric_handle_irq(irq_linear_revmap(apc->domain, 3));\n \n \telse if (pending & AR71XX_PCI_INT_CORE)\n-\t\tgeneric_handle_irq(apc->irq_base + 4);\n+\t\tgeneric_handle_irq(irq_linear_revmap(apc->domain, 4));\n \n \telse\n \t\tspurious_interrupt();\n+\tchained_irq_exit(chip, desc);\n }\n \n static void ar71xx_pci_irq_unmask(struct irq_data *d)\n@@ -258,7 +263,7 @@ static void ar71xx_pci_irq_unmask(struct\n \tu32 t;\n \n \tapc = irq_data_get_irq_chip_data(d);\n-\tirq = d->irq - apc->irq_base;\n+\tirq = irq_linear_revmap(apc->domain, d->irq);\n \n \tt = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);\n \t__raw_writel(t | (1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE);\n@@ -275,7 +280,7 @@ static void ar71xx_pci_irq_mask(struct i\n \tu32 t;\n \n \tapc = irq_data_get_irq_chip_data(d);\n-\tirq = d->irq - apc->irq_base;\n+\tirq = irq_linear_revmap(apc->domain, d->irq);\n \n \tt = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);\n \t__raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE);\n@@ -291,24 +296,31 @@ static struct irq_chip ar71xx_pci_irq_ch\n \t.irq_mask_ack\t= ar71xx_pci_irq_mask,\n };\n \n+static int ar71xx_pci_irq_map(struct irq_domain *d,\n+\t\t\t      unsigned int irq, irq_hw_number_t hw)\n+{\n+\tstruct ar71xx_pci_controller *apc = d->host_data;\n+\n+\tirq_set_chip_and_handler(irq, &ar71xx_pci_irq_chip, handle_level_irq);\n+\tirq_set_chip_data(irq, apc);\n+\n+\treturn 0;\n+}\n+\n+static const struct irq_domain_ops ar71xx_pci_domain_ops = {\n+\t.xlate = irq_domain_xlate_onecell,\n+\t.map = ar71xx_pci_irq_map,\n+};\n+\n static void ar71xx_pci_irq_init(struct ar71xx_pci_controller *apc)\n {\n \tvoid __iomem *base = ath79_reset_base;\n-\tint i;\n \n \t__raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_ENABLE);\n \t__raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_STATUS);\n \n-\tBUILD_BUG_ON(ATH79_PCI_IRQ_COUNT < AR71XX_PCI_IRQ_COUNT);\n-\n-\tapc->irq_base = ATH79_PCI_IRQ_BASE;\n-\tfor (i = apc->irq_base;\n-\t     i < apc->irq_base + AR71XX_PCI_IRQ_COUNT; i++) {\n-\t\tirq_set_chip_and_handler(i, &ar71xx_pci_irq_chip,\n-\t\t\t\t\t handle_level_irq);\n-\t\tirq_set_chip_data(i, apc);\n-\t}\n-\n+\tapc->domain = irq_domain_add_linear(apc->np, AR71XX_PCI_IRQ_COUNT,\n+\t\t\t\t\t    &ar71xx_pci_domain_ops, apc);\n \tirq_set_chained_handler_and_data(apc->irq, ar71xx_pci_irq_handler,\n \t\t\t\t\t apc);\n }\n@@ -325,6 +337,11 @@ static void ar71xx_pci_reset(void)\n \tmdelay(100);\n }\n \n+static const struct of_device_id ar71xx_pci_ids[] = {\n+\t{ .compatible = \"qca,ar7100-pci\" },\n+\t{},\n+};\n+\n static int ar71xx_pci_probe(struct platform_device *pdev)\n {\n \tstruct ar71xx_pci_controller *apc;\n@@ -345,26 +362,6 @@ static int ar71xx_pci_probe(struct platf\n \tif (apc->irq < 0)\n \t\treturn -EINVAL;\n \n-\tres = platform_get_resource_byname(pdev, IORESOURCE_IO, \"io_base\");\n-\tif (!res)\n-\t\treturn -EINVAL;\n-\n-\tapc->io_res.parent = res;\n-\tapc->io_res.name = \"PCI IO space\";\n-\tapc->io_res.start = res->start;\n-\tapc->io_res.end = res->end;\n-\tapc->io_res.flags = IORESOURCE_IO;\n-\n-\tres = platform_get_resource_byname(pdev, IORESOURCE_MEM, \"mem_base\");\n-\tif (!res)\n-\t\treturn -EINVAL;\n-\n-\tapc->mem_res.parent = res;\n-\tapc->mem_res.name = \"PCI memory space\";\n-\tapc->mem_res.start = res->start;\n-\tapc->mem_res.end = res->end;\n-\tapc->mem_res.flags = IORESOURCE_MEM;\n-\n \tar71xx_pci_reset();\n \n \t/* setup COMMAND register */\n@@ -377,9 +374,11 @@ static int ar71xx_pci_probe(struct platf\n \n \tar71xx_pci_irq_init(apc);\n \n+\tapc->np = pdev->dev.of_node;\n \tapc->pci_ctrl.pci_ops = &ar71xx_pci_ops;\n \tapc->pci_ctrl.mem_resource = &apc->mem_res;\n \tapc->pci_ctrl.io_resource = &apc->io_res;\n+\tpci_load_of_ranges(&apc->pci_ctrl, pdev->dev.of_node);\n \n \tregister_pci_controller(&apc->pci_ctrl);\n \n@@ -390,6 +389,7 @@ static struct platform_driver ar71xx_pci\n \t.probe = ar71xx_pci_probe,\n \t.driver = {\n \t\t.name = \"ar71xx-pci\",\n+\t\t.of_match_table = of_match_ptr(ar71xx_pci_ids),\n \t},\n };\n \n"
  },
  {
    "path": "target/linux/ath79/patches-5.15/0019-dt-bindings-PCI-qcom-ar7240-adds-binding-doc.patch",
    "content": "From ea27764bc3ef2a05decf3ae05edffc289cd0d93c Mon Sep 17 00:00:00 2001\nFrom: John Crispin <john@phrozen.org>\nDate: Mon, 25 Jun 2018 15:52:02 +0200\nSubject: [PATCH 19/33] dt-bindings: PCI: qcom,ar7240: adds binding doc\n\nWith the driver being converted from platform_data to pure OF, we need to\nalso add some docs.\n\nCc: Rob Herring <robh+dt@kernel.org>\nCc: devicetree@vger.kernel.org\nSigned-off-by: John Crispin <john@phrozen.org>\n---\n .../devicetree/bindings/pci/qcom,ar7240-pci.txt    | 42 ++++++++++++++++++++++\n 1 file changed, 42 insertions(+)\n create mode 100644 Documentation/devicetree/bindings/pci/qcom,ar7240-pci.txt\n\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/pci/qcom,ar7240-pci.txt\n@@ -0,0 +1,42 @@\n+* Qualcomm Atheros AR724X PCI express root complex\n+\n+Required properties:\n+- compatible: should contain \"qcom,ar7240-pci\" to identify the core.\n+- reg: Should contain the register ranges as listed in the reg-names property.\n+- reg-names: Definition: Must include the following entries\n+\t- \"crp_base\"\tConfiguration registers\n+\t- \"ctrl_base\"\tControl registers\n+\t- \"cfg_base\"\tIO Memory\n+- #address-cells: set to <3>\n+- #size-cells: set to <2>\n+- ranges: ranges for the PCI memory and I/O regions\n+- interrupt-map-mask and interrupt-map: standard PCI\n+\tproperties to define the mapping of the PCIe interface to interrupt\n+\tnumbers.\n+- #interrupt-cells: set to <1>\n+- interrupt-parent: phandle to the MIPS IRQ controller\n+\n+Optional properties:\n+- interrupt-controller: define to enable the builtin IRQ cascade.\n+\n+* Example for qca9557\n+\tpcie-controller@180c0000 {\n+\t\tcompatible = \"qcom,ar7240-pci\";\n+\t\t#address-cells = <3>;\n+\t\t#size-cells = <2>;\n+\t\tbus-range = <0x0 0x0>;\n+\t\treg = <0x180c0000 0x1000>,\n+\t\t      <0x180f0000 0x100>,\n+\t\t      <0x14000000 0x1000>;\n+\t\treg-names = \"crp_base\", \"ctrl_base\", \"cfg_base\";\n+\t\tranges = <0x2000000 0 0x10000000 0x10000000 0 0x04000000\n+\t\t\t  0x1000000 0 0x00000000 0x00000000 0 0x00000001>;\n+\t\tinterrupt-parent = <&intc2>;\n+\t\tinterrupts = <1>;\n+\n+\t\tinterrupt-controller;\n+\t\t#interrupt-cells = <1>;\n+\n+\t\tinterrupt-map-mask = <0 0 0 1>;\n+\t\tinterrupt-map = <0 0 0 0 &pcie0 0>;\n+\t};\n"
  },
  {
    "path": "target/linux/ath79/patches-5.15/0020-MIPS-pci-ar724x-convert-to-OF.patch",
    "content": "From a522ee0199d5d3ea114ca2e211f6ac398d3e8e0b Mon Sep 17 00:00:00 2001\nFrom: John Crispin <john@phrozen.org>\nDate: Sat, 23 Jun 2018 15:07:37 +0200\nSubject: [PATCH 20/33] MIPS: pci-ar724x: convert to OF\n\nWith the ath79 target getting converted to pure OF, we can drop all the\nplatform data code and add the missing OF bits to the driver. We also add\na irq domain for the PCI/e controllers cascade, thus making it usable from\ndts files.\n\nSigned-off-by: John Crispin <john@phrozen.org>\n---\n arch/mips/pci/pci-ar724x.c | 88 ++++++++++++++++++++++------------------------\n 1 file changed, 42 insertions(+), 46 deletions(-)\n\n--- a/arch/mips/pci/pci-ar724x.c\n+++ b/arch/mips/pci/pci-ar724x.c\n@@ -11,8 +11,11 @@\n #include <linux/init.h>\n #include <linux/delay.h>\n #include <linux/platform_device.h>\n+#include <linux/irqchip/chained_irq.h>\n #include <asm/mach-ath79/ath79.h>\n #include <asm/mach-ath79/ar71xx_regs.h>\n+#include <linux/of_irq.h>\n+#include <linux/of_pci.h>\n \n #define AR724X_PCI_REG_APP\t\t0x00\n #define AR724X_PCI_REG_RESET\t\t0x18\n@@ -42,17 +45,20 @@ struct ar724x_pci_controller {\n \tvoid __iomem *crp_base;\n \n \tint irq;\n-\tint irq_base;\n \n \tbool link_up;\n \tbool bar0_is_cached;\n \tu32  bar0_value;\n \n+\tstruct device_node *np;\n \tstruct pci_controller pci_controller;\n+\tstruct irq_domain *domain;\n \tstruct resource io_res;\n \tstruct resource mem_res;\n };\n \n+static struct irq_chip ar724x_pci_irq_chip;\n+\n static inline bool ar724x_pci_check_link(struct ar724x_pci_controller *apc)\n {\n \tu32 reset;\n@@ -228,35 +234,31 @@ static struct pci_ops ar724x_pci_ops = {\n \n static void ar724x_pci_irq_handler(struct irq_desc *desc)\n {\n-\tstruct ar724x_pci_controller *apc;\n-\tvoid __iomem *base;\n+\tstruct irq_chip *chip = irq_desc_get_chip(desc);\n+\tstruct ar724x_pci_controller *apc = irq_desc_get_handler_data(desc);\n \tu32 pending;\n \n-\tapc = irq_desc_get_handler_data(desc);\n-\tbase = apc->ctrl_base;\n-\n-\tpending = __raw_readl(base + AR724X_PCI_REG_INT_STATUS) &\n-\t\t  __raw_readl(base + AR724X_PCI_REG_INT_MASK);\n+\tchained_irq_enter(chip, desc);\n+\tpending = __raw_readl(apc->ctrl_base + AR724X_PCI_REG_INT_STATUS) &\n+\t\t  __raw_readl(apc->ctrl_base + AR724X_PCI_REG_INT_MASK);\n \n \tif (pending & AR724X_PCI_INT_DEV0)\n-\t\tgeneric_handle_irq(apc->irq_base + 0);\n-\n+\t\tgeneric_handle_irq(irq_linear_revmap(apc->domain, 1));\n \telse\n \t\tspurious_interrupt();\n+\tchained_irq_exit(chip, desc);\n }\n \n static void ar724x_pci_irq_unmask(struct irq_data *d)\n {\n \tstruct ar724x_pci_controller *apc;\n \tvoid __iomem *base;\n-\tint offset;\n \tu32 t;\n \n \tapc = irq_data_get_irq_chip_data(d);\n \tbase = apc->ctrl_base;\n-\toffset = apc->irq_base - d->irq;\n \n-\tswitch (offset) {\n+\tswitch (irq_linear_revmap(apc->domain, d->irq)) {\n \tcase 0:\n \t\tt = __raw_readl(base + AR724X_PCI_REG_INT_MASK);\n \t\t__raw_writel(t | AR724X_PCI_INT_DEV0,\n@@ -270,14 +272,12 @@ static void ar724x_pci_irq_mask(struct i\n {\n \tstruct ar724x_pci_controller *apc;\n \tvoid __iomem *base;\n-\tint offset;\n \tu32 t;\n \n \tapc = irq_data_get_irq_chip_data(d);\n \tbase = apc->ctrl_base;\n-\toffset = apc->irq_base - d->irq;\n \n-\tswitch (offset) {\n+\tswitch (irq_linear_revmap(apc->domain, d->irq)) {\n \tcase 0:\n \t\tt = __raw_readl(base + AR724X_PCI_REG_INT_MASK);\n \t\t__raw_writel(t & ~AR724X_PCI_INT_DEV0,\n@@ -302,26 +302,34 @@ static struct irq_chip ar724x_pci_irq_ch\n \t.irq_mask_ack\t= ar724x_pci_irq_mask,\n };\n \n+static int ar724x_pci_irq_map(struct irq_domain *d,\n+\t\t\t      unsigned int irq, irq_hw_number_t hw)\n+{\n+\tstruct ar724x_pci_controller *apc = d->host_data;\n+\n+\tirq_set_chip_and_handler(irq, &ar724x_pci_irq_chip, handle_level_irq);\n+\tirq_set_chip_data(irq, apc);\n+\n+\treturn 0;\n+}\n+\n+static const struct irq_domain_ops ar724x_pci_domain_ops = {\n+\t.xlate = irq_domain_xlate_onecell,\n+\t.map = ar724x_pci_irq_map,\n+};\n+\n static void ar724x_pci_irq_init(struct ar724x_pci_controller *apc,\n \t\t\t\tint id)\n {\n \tvoid __iomem *base;\n-\tint i;\n \n \tbase = apc->ctrl_base;\n \n \t__raw_writel(0, base + AR724X_PCI_REG_INT_MASK);\n \t__raw_writel(0, base + AR724X_PCI_REG_INT_STATUS);\n \n-\tapc->irq_base = ATH79_PCI_IRQ_BASE + (id * AR724X_PCI_IRQ_COUNT);\n-\n-\tfor (i = apc->irq_base;\n-\t     i < apc->irq_base + AR724X_PCI_IRQ_COUNT; i++) {\n-\t\tirq_set_chip_and_handler(i, &ar724x_pci_irq_chip,\n-\t\t\t\t\t handle_level_irq);\n-\t\tirq_set_chip_data(i, apc);\n-\t}\n-\n+\tapc->domain = irq_domain_add_linear(apc->np, 2,\n+\t\t\t\t\t    &ar724x_pci_domain_ops, apc);\n \tirq_set_chained_handler_and_data(apc->irq, ar724x_pci_irq_handler,\n \t\t\t\t\t apc);\n }\n@@ -388,29 +396,11 @@ static int ar724x_pci_probe(struct platf\n \tif (apc->irq < 0)\n \t\treturn -EINVAL;\n \n-\tres = platform_get_resource_byname(pdev, IORESOURCE_IO, \"io_base\");\n-\tif (!res)\n-\t\treturn -EINVAL;\n-\n-\tapc->io_res.parent = res;\n-\tapc->io_res.name = \"PCI IO space\";\n-\tapc->io_res.start = res->start;\n-\tapc->io_res.end = res->end;\n-\tapc->io_res.flags = IORESOURCE_IO;\n-\n-\tres = platform_get_resource_byname(pdev, IORESOURCE_MEM, \"mem_base\");\n-\tif (!res)\n-\t\treturn -EINVAL;\n-\n-\tapc->mem_res.parent = res;\n-\tapc->mem_res.name = \"PCI memory space\";\n-\tapc->mem_res.start = res->start;\n-\tapc->mem_res.end = res->end;\n-\tapc->mem_res.flags = IORESOURCE_MEM;\n-\n+\tapc->np = pdev->dev.of_node;\n \tapc->pci_controller.pci_ops = &ar724x_pci_ops;\n \tapc->pci_controller.io_resource = &apc->io_res;\n \tapc->pci_controller.mem_resource = &apc->mem_res;\n+\tpci_load_of_ranges(&apc->pci_controller, pdev->dev.of_node);\n \n \t/*\n \t * Do the full PCIE Root Complex Initialization Sequence if the PCIe\n@@ -432,10 +422,16 @@ static int ar724x_pci_probe(struct platf\n \treturn 0;\n }\n \n+static const struct of_device_id ar724x_pci_ids[] = {\n+\t{ .compatible = \"qcom,ar7240-pci\" },\n+\t{},\n+};\n+\n static struct platform_driver ar724x_pci_driver = {\n \t.probe = ar724x_pci_probe,\n \t.driver = {\n \t\t.name = \"ar724x-pci\",\n+\t\t.of_match_table = of_match_ptr(ar724x_pci_ids),\n \t},\n };\n \n"
  },
  {
    "path": "target/linux/ath79/patches-5.15/0032-MIPS-ath79-sanitize-symbols.patch",
    "content": "From 3fc8585cf76022dba7496627074d42af88c30718 Mon Sep 17 00:00:00 2001\nFrom: John Crispin <john@phrozen.org>\nDate: Sat, 23 Jun 2018 15:16:55 +0200\nSubject: [PATCH 32/33] MIPS: ath79: sanitize symbols\n\nWe no longer need to select which SoCs are supported as the whole arch\ncode is always built. So lets drop all the SoC symbols\n\nSigned-off-by: John Crispin <john@phrozen.org>\n---\n arch/mips/Kconfig       |  2 ++\n arch/mips/ath79/Kconfig | 44 +++++---------------------------------------\n arch/mips/pci/Makefile  |  2 +-\n 3 files changed, 8 insertions(+), 40 deletions(-)\n\n--- a/arch/mips/Kconfig\n+++ b/arch/mips/Kconfig\n@@ -256,6 +256,8 @@ config ATH79\n \tselect SYS_SUPPORTS_BIG_ENDIAN\n \tselect SYS_SUPPORTS_MIPS16\n \tselect SYS_SUPPORTS_ZBOOT_UART_PROM\n+\tselect HAVE_PCI\n+\tselect USB_ARCH_HAS_EHCI\n \tselect USE_OF\n \tselect USB_EHCI_ROOT_HUB_TT if USB_EHCI_HCD_PLATFORM\n \thelp\n--- a/arch/mips/ath79/Kconfig\n+++ b/arch/mips/ath79/Kconfig\n@@ -1,48 +1,14 @@\n # SPDX-License-Identifier: GPL-2.0\n if ATH79\n \n-config SOC_AR71XX\n-\tselect HAVE_PCI\n-\tdef_bool n\n-\n-config SOC_AR724X\n-\tselect HAVE_PCI\n-\tselect PCI_AR724X if PCI\n-\tdef_bool n\n-\n-config SOC_AR913X\n-\tdef_bool n\n-\n-config SOC_AR933X\n-\tdef_bool n\n-\n-config SOC_AR934X\n-\tselect HAVE_PCI\n-\tselect PCI_AR724X if PCI\n-\tdef_bool n\n-\n-config SOC_QCA955X\n-\tselect HAVE_PCI\n-\tselect PCI_AR724X if PCI\n+config PCI_AR71XX\n+\tbool \"PCI support for AR7100 type SoCs\"\n+\tdepends on PCI\n \tdef_bool n\n \n config PCI_AR724X\n-\tdef_bool n\n-\n-config ATH79_DEV_GPIO_BUTTONS\n-\tdef_bool n\n-\n-config ATH79_DEV_LEDS_GPIO\n-\tdef_bool n\n-\n-config ATH79_DEV_SPI\n-\tdef_bool n\n-\n-config ATH79_DEV_USB\n-\tdef_bool n\n-\n-config ATH79_DEV_WMAC\n-\tdepends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA955X)\n+\tbool \"PCI support for AR724x type SoCs\"\n+\tdepends on PCI\n \tdef_bool n\n \n endif\n--- a/arch/mips/pci/Makefile\n+++ b/arch/mips/pci/Makefile\n@@ -21,7 +21,7 @@ obj-$(CONFIG_BCM63XX)\t\t+= pci-bcm63xx.o\n \t\t\t\t\tops-bcm63xx.o\n obj-$(CONFIG_MIPS_ALCHEMY)\t+= pci-alchemy.o\n obj-$(CONFIG_PCI_AR2315)\t+= pci-ar2315.o\n-obj-$(CONFIG_SOC_AR71XX)\t+= pci-ar71xx.o\n+obj-$(CONFIG_PCI_AR71XX)\t+= pci-ar71xx.o\n obj-$(CONFIG_PCI_AR724X)\t+= pci-ar724x.o\n obj-$(CONFIG_PCI_XTALK_BRIDGE)\t+= pci-xtalk-bridge.o\n #\n"
  },
  {
    "path": "target/linux/ath79/patches-5.15/0034-MIPS-ath79-ath9k-exports.patch",
    "content": "--- a/arch/mips/ath79/common.c\n+++ b/arch/mips/ath79/common.c\n@@ -31,11 +31,13 @@ EXPORT_SYMBOL_GPL(ath79_ddr_freq);\n \n enum ath79_soc_type ath79_soc;\n unsigned int ath79_soc_rev;\n+EXPORT_SYMBOL_GPL(ath79_soc_rev);\n \n void __iomem *ath79_pll_base;\n void __iomem *ath79_reset_base;\n EXPORT_SYMBOL_GPL(ath79_reset_base);\n-static void __iomem *ath79_ddr_base;\n+void __iomem *ath79_ddr_base;\n+EXPORT_SYMBOL_GPL(ath79_ddr_base);\n static void __iomem *ath79_ddr_wb_flush_base;\n static void __iomem *ath79_ddr_pci_win_base;\n \n--- a/arch/mips/include/asm/mach-ath79/ath79.h\n+++ b/arch/mips/include/asm/mach-ath79/ath79.h\n@@ -149,6 +149,7 @@ void ath79_ddr_wb_flush(unsigned int reg\n void ath79_ddr_set_pci_windows(void);\n \n extern void __iomem *ath79_pll_base;\n+extern void __iomem *ath79_ddr_base;\n extern void __iomem *ath79_reset_base;\n \n static inline void ath79_pll_wr(unsigned reg, u32 val)\n"
  },
  {
    "path": "target/linux/ath79/patches-5.15/0036-MIPS-ath79-remove-irq-code-from-pci.patch",
    "content": "--- a/arch/mips/pci/pci-ar71xx.c\n+++ b/arch/mips/pci/pci-ar71xx.c\n@@ -51,11 +51,9 @@\n struct ar71xx_pci_controller {\n \tstruct device_node *np;\n \tvoid __iomem *cfg_base;\n-\tint irq;\n \tstruct pci_controller pci_ctrl;\n \tstruct resource io_res;\n \tstruct resource mem_res;\n-\tstruct irq_domain *domain;\n };\n \n /* Byte lane enable bits */\n@@ -227,104 +225,6 @@ static struct pci_ops ar71xx_pci_ops = {\n \t.write\t= ar71xx_pci_write_config,\n };\n \n-static void ar71xx_pci_irq_handler(struct irq_desc *desc)\n-{\n-\tvoid __iomem *base = ath79_reset_base;\n-\tstruct irq_chip *chip = irq_desc_get_chip(desc);\n-\tstruct ar71xx_pci_controller *apc = irq_desc_get_handler_data(desc);\n-\tu32 pending;\n-\n-\tchained_irq_enter(chip, desc);\n-\tpending = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_STATUS) &\n-\t\t  __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);\n-\n-\tif (pending & AR71XX_PCI_INT_DEV0)\n-\t\tgeneric_handle_irq(irq_linear_revmap(apc->domain, 1));\n-\n-\telse if (pending & AR71XX_PCI_INT_DEV1)\n-\t\tgeneric_handle_irq(irq_linear_revmap(apc->domain, 2));\n-\n-\telse if (pending & AR71XX_PCI_INT_DEV2)\n-\t\tgeneric_handle_irq(irq_linear_revmap(apc->domain, 3));\n-\n-\telse if (pending & AR71XX_PCI_INT_CORE)\n-\t\tgeneric_handle_irq(irq_linear_revmap(apc->domain, 4));\n-\n-\telse\n-\t\tspurious_interrupt();\n-\tchained_irq_exit(chip, desc);\n-}\n-\n-static void ar71xx_pci_irq_unmask(struct irq_data *d)\n-{\n-\tstruct ar71xx_pci_controller *apc;\n-\tunsigned int irq;\n-\tvoid __iomem *base = ath79_reset_base;\n-\tu32 t;\n-\n-\tapc = irq_data_get_irq_chip_data(d);\n-\tirq = irq_linear_revmap(apc->domain, d->irq);\n-\n-\tt = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);\n-\t__raw_writel(t | (1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE);\n-\n-\t/* flush write */\n-\t__raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);\n-}\n-\n-static void ar71xx_pci_irq_mask(struct irq_data *d)\n-{\n-\tstruct ar71xx_pci_controller *apc;\n-\tunsigned int irq;\n-\tvoid __iomem *base = ath79_reset_base;\n-\tu32 t;\n-\n-\tapc = irq_data_get_irq_chip_data(d);\n-\tirq = irq_linear_revmap(apc->domain, d->irq);\n-\n-\tt = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);\n-\t__raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE);\n-\n-\t/* flush write */\n-\t__raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);\n-}\n-\n-static struct irq_chip ar71xx_pci_irq_chip = {\n-\t.name\t\t= \"AR71XX PCI\",\n-\t.irq_mask\t= ar71xx_pci_irq_mask,\n-\t.irq_unmask\t= ar71xx_pci_irq_unmask,\n-\t.irq_mask_ack\t= ar71xx_pci_irq_mask,\n-};\n-\n-static int ar71xx_pci_irq_map(struct irq_domain *d,\n-\t\t\t      unsigned int irq, irq_hw_number_t hw)\n-{\n-\tstruct ar71xx_pci_controller *apc = d->host_data;\n-\n-\tirq_set_chip_and_handler(irq, &ar71xx_pci_irq_chip, handle_level_irq);\n-\tirq_set_chip_data(irq, apc);\n-\n-\treturn 0;\n-}\n-\n-static const struct irq_domain_ops ar71xx_pci_domain_ops = {\n-\t.xlate = irq_domain_xlate_onecell,\n-\t.map = ar71xx_pci_irq_map,\n-};\n-\n-static void ar71xx_pci_irq_init(struct ar71xx_pci_controller *apc)\n-{\n-\tvoid __iomem *base = ath79_reset_base;\n-\n-\t__raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_ENABLE);\n-\t__raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_STATUS);\n-\n-\tapc->domain = irq_domain_add_linear(apc->np, AR71XX_PCI_IRQ_COUNT,\n-\t\t\t\t\t    &ar71xx_pci_domain_ops, apc);\n-\tirq_set_chained_handler_and_data(apc->irq, ar71xx_pci_irq_handler,\n-\t\t\t\t\t apc);\n-}\n-\n static void ar71xx_pci_reset(void)\n {\n \tath79_device_reset_set(AR71XX_RESET_PCI_BUS | AR71XX_RESET_PCI_CORE);\n@@ -358,10 +258,6 @@ static int ar71xx_pci_probe(struct platf\n \tif (IS_ERR(apc->cfg_base))\n \t\treturn PTR_ERR(apc->cfg_base);\n \n-\tapc->irq = platform_get_irq(pdev, 0);\n-\tif (apc->irq < 0)\n-\t\treturn -EINVAL;\n-\n \tar71xx_pci_reset();\n \n \t/* setup COMMAND register */\n@@ -372,8 +268,6 @@ static int ar71xx_pci_probe(struct platf\n \t/* clear bus errors */\n \tar71xx_pci_check_error(apc, 1);\n \n-\tar71xx_pci_irq_init(apc);\n-\n \tapc->np = pdev->dev.of_node;\n \tapc->pci_ctrl.pci_ops = &ar71xx_pci_ops;\n \tapc->pci_ctrl.mem_resource = &apc->mem_res;\n"
  },
  {
    "path": "target/linux/ath79/patches-5.15/0037-missing-registers.patch",
    "content": "commit f3ffac90bc7266b7d917616f3233f58e8c08a196\nAuthor: Christian Lamparter <chunkeey@gmail.com>\nDate:   Fri Aug 10 23:24:47 2018 +0200\n\n    ath79: gmac: add parsers for rxd(v)- and tx(d|en)-delay for AR9344\n\n    Signed-off-by: Christian Lamparter <chunkeey@gmail.com>\n\n--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h\n+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h\n@@ -1226,6 +1226,10 @@\n #define AR934X_ETH_CFG_RDV_DELAY        BIT(16)\n #define AR934X_ETH_CFG_RDV_DELAY_MASK   0x3\n #define AR934X_ETH_CFG_RDV_DELAY_SHIFT  16\n+#define AR934X_ETH_CFG_TXD_DELAY_MASK   0x3\n+#define AR934X_ETH_CFG_TXD_DELAY_SHIFT  18\n+#define AR934X_ETH_CFG_TXE_DELAY_MASK   0x3\n+#define AR934X_ETH_CFG_TXE_DELAY_SHIFT  20\n \n /*\n  * QCA953X GMAC Interface\n"
  },
  {
    "path": "target/linux/ath79/patches-5.15/0038-MIPS-ath79-add-missing-QCA955x-GMAC-registers.patch",
    "content": "From 60efe35257b063ce584968f9f80b437030ce6ba6 Mon Sep 17 00:00:00 2001\nFrom: David Bauer <mail@david-bauer.net>\nDate: Mon, 18 Mar 2019 00:54:06 +0100\nSubject: [PATCH] MIPS: ath79: add missing QCA955x GMAC registers\n\nThis adds missing GMAC register definitions for the Qualcomm Atheros\nQCA955X series MIPS SoCs.\n\nThey originate from the platforms U-Boot code and the AVM FRITZ!WLAN\nRepeater 450E's GPL tarball.\n\nSigned-off-by: David Bauer <mail@david-bauer.net>\n---\n .../mips/include/asm/mach-ath79/ar71xx_regs.h | 54 +++++++++++++++++++\n 1 file changed, 54 insertions(+)\n\n--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h\n+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h\n@@ -1246,7 +1246,12 @@\n  */\n \n #define QCA955X_GMAC_REG_ETH_CFG\t0x00\n+#define QCA955X_GMAC_REG_SGMII_RESET\t0x14\n #define QCA955X_GMAC_REG_SGMII_SERDES\t0x18\n+#define QCA955X_GMAC_REG_MR_AN_CONTROL\t0x1c\n+#define QCA955X_GMAC_REG_MR_AN_STATUS\t0x20\n+#define QCA955X_GMAC_REG_SGMII_CONFIG\t0x34\n+#define QCA955X_GMAC_REG_SGMII_DEBUG\t0x58\n \n #define QCA955X_ETH_CFG_RGMII_EN\tBIT(0)\n #define QCA955X_ETH_CFG_MII_GE0\t\tBIT(1)\n@@ -1268,9 +1273,58 @@\n #define QCA955X_ETH_CFG_TXE_DELAY_MASK\t0x3\n #define QCA955X_ETH_CFG_TXE_DELAY_SHIFT\t20\n \n+#define QCA955X_SGMII_RESET_RX_CLK_N_RESET\t0\n+#define QCA955X_SGMII_RESET_RX_CLK_N\t\tBIT(0)\n+#define QCA955X_SGMII_RESET_TX_CLK_N\t\tBIT(1)\n+#define QCA955X_SGMII_RESET_RX_125M_N\t\tBIT(2)\n+#define QCA955X_SGMII_RESET_TX_125M_N\t\tBIT(3)\n+#define QCA955X_SGMII_RESET_HW_RX_125M_N\tBIT(4)\n+\n #define QCA955X_SGMII_SERDES_LOCK_DETECT_STATUS\tBIT(15)\n #define QCA955X_SGMII_SERDES_RES_CALIBRATION_SHIFT 23\n #define QCA955X_SGMII_SERDES_RES_CALIBRATION_MASK 0xf\n+\n+#define QCA955X_MR_AN_CONTROL_SPEED_SEL1\tBIT(6)\n+#define QCA955X_MR_AN_CONTROL_DUPLEX_MODE\tBIT(8)\n+#define QCA955X_MR_AN_CONTROL_RESTART_AN\tBIT(9)\n+#define QCA955X_MR_AN_CONTROL_POWER_DOWN\tBIT(11)\n+#define QCA955X_MR_AN_CONTROL_AN_ENABLE\t\tBIT(12)\n+#define QCA955X_MR_AN_CONTROL_SPEED_SEL0\tBIT(13)\n+#define QCA955X_MR_AN_CONTROL_LOOPBACK\t\tBIT(14)\n+#define QCA955X_MR_AN_CONTROL_PHY_RESET\t\tBIT(15)\n+\n+#define QCA955X_MR_AN_STATUS_EXT_CAP\t\tBIT(0)\n+#define QCA955X_MR_AN_STATUS_LINK_UP\t\tBIT(2)\n+#define QCA955X_MR_AN_STATUS_AN_ABILITY\t\tBIT(3)\n+#define QCA955X_MR_AN_STATUS_REMOTE_FAULT\tBIT(4)\n+#define QCA955X_MR_AN_STATUS_AN_COMPLETE\tBIT(5)\n+#define QCA955X_MR_AN_STATUS_NO_PREAMBLE\tBIT(6)\n+#define QCA955X_MR_AN_STATUS_BASE_PAGE\t\tBIT(7)\n+\n+#define QCA955X_SGMII_CONFIG_MODE_CTRL_SHIFT\t\t0\n+#define QCA955X_SGMII_CONFIG_MODE_CTRL_MASK\t\t0x7\n+#define QCA955X_SGMII_CONFIG_ENABLE_SGMII_TX_PAUSE\tBIT(3)\n+#define QCA955X_SGMII_CONFIG_MR_REG4_CHANGED\t\tBIT(4)\n+#define QCA955X_SGMII_CONFIG_FORCE_SPEED\t\tBIT(5)\n+#define QCA955X_SGMII_CONFIG_SPEED_SHIFT\t\t6\n+#define QCA955X_SGMII_CONFIG_SPEED_MASK\t\t\t0xc0\n+#define QCA955X_SGMII_CONFIG_REMOTE_PHY_LOOPBACK\tBIT(8)\n+#define QCA955X_SGMII_CONFIG_NEXT_PAGE_LOADED\t\tBIT(9)\n+#define QCA955X_SGMII_CONFIG_MDIO_ENABLE\t\tBIT(10)\n+#define QCA955X_SGMII_CONFIG_MDIO_PULSE\t\t\tBIT(11)\n+#define QCA955X_SGMII_CONFIG_MDIO_COMPLETE\t\tBIT(12)\n+#define QCA955X_SGMII_CONFIG_PRBS_ENABLE\t\tBIT(13)\n+#define QCA955X_SGMII_CONFIG_BERT_ENABLE\t\tBIT(14)\n+\n+#define QCA955X_SGMII_DEBUG_TX_STATE_MASK\t0xff\n+#define QCA955X_SGMII_DEBUG_TX_STATE_SHIFT\t0\n+#define QCA955X_SGMII_DEBUG_RX_STATE_MASK\t0xff00\n+#define QCA955X_SGMII_DEBUG_RX_STATE_SHIFT\t8\n+#define QCA955X_SGMII_DEBUG_RX_SYNC_STATE_MASK\t0xff0000\n+#define QCA955X_SGMII_DEBUG_RX_SYNC_STATE_SHIFT\t16\n+#define QCA955X_SGMII_DEBUG_ARB_STATE_MASK\t0xf000000\n+#define QCA955X_SGMII_DEBUG_ARB_STATE_SHIFT\t24\n+\n /*\n  * QCA956X GMAC Interface\n  */\n"
  },
  {
    "path": "target/linux/ath79/patches-5.15/0039-MIPS-ath79-export-UART1-reference-clock.patch",
    "content": "--- a/arch/mips/ath79/clock.c\n+++ b/arch/mips/ath79/clock.c\n@@ -40,6 +40,7 @@ static const char * const clk_names[ATH7\n \t[ATH79_CLK_AHB] = \"ahb\",\n \t[ATH79_CLK_REF] = \"ref\",\n \t[ATH79_CLK_MDIO] = \"mdio\",\n+\t[ATH79_CLK_UART1] = \"uart1\",\n };\n \n static const char * __init ath79_clk_name(int type)\n@@ -344,6 +345,9 @@ static void __init ar934x_clocks_init(vo\n \tif (clk_ctrl & AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL)\n \t\tath79_set_clk(ATH79_CLK_MDIO, 100 * 1000 * 1000);\n \n+\tif (clk_ctrl & AR934X_PLL_SWITCH_CLOCK_CONTROL_UART1_CLK_SEL)\n+\t\tath79_set_clk(ATH79_CLK_UART1, 100 * 1000 * 1000);\n+\n \tiounmap(dpll_base);\n }\n \n@@ -649,6 +653,9 @@ static void __init ath79_clocks_init_dt(\n \tif (!clks[ATH79_CLK_MDIO])\n \t\tclks[ATH79_CLK_MDIO] = clks[ATH79_CLK_REF];\n \n+\tif (!clks[ATH79_CLK_UART1])\n+\t\tclks[ATH79_CLK_UART1] = clks[ATH79_CLK_REF];\n+\n \tif (of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data)) {\n \t\tpr_err(\"%pOF: could not register clk provider\\n\", np);\n \t\tgoto err_iounmap;\n--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h\n+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h\n@@ -348,6 +348,7 @@\n #define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL\tBIT(24)\n \n #define AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL\tBIT(6)\n+#define AR934X_PLL_SWITCH_CLOCK_CONTROL_UART1_CLK_SEL\tBIT(7)\n \n #define QCA953X_PLL_CPU_CONFIG_REG\t\t0x00\n #define QCA953X_PLL_DDR_CONFIG_REG\t\t0x04\n--- a/include/dt-bindings/clock/ath79-clk.h\n+++ b/include/dt-bindings/clock/ath79-clk.h\n@@ -11,7 +11,8 @@\n #define ATH79_CLK_AHB\t\t2\n #define ATH79_CLK_REF\t\t3\n #define ATH79_CLK_MDIO\t\t4\n+#define ATH79_CLK_UART1\t\t5\n \n-#define ATH79_CLK_END\t\t5\n+#define ATH79_CLK_END\t\t6\n \n #endif /* __DT_BINDINGS_ATH79_CLK_H */\n"
  },
  {
    "path": "target/linux/ath79/patches-5.15/004-register_gpio_driver_earlier.patch",
    "content": "HACK: register the GPIO driver earlier to ensure that gpio_request calls\nfrom mach files succeed.\n\n--- a/drivers/gpio/gpio-ath79.c\n+++ b/drivers/gpio/gpio-ath79.c\n@@ -297,7 +297,11 @@ static struct platform_driver ath79_gpio\n \t.probe = ath79_gpio_probe,\n };\n \n-module_platform_driver(ath79_gpio_driver);\n+static int __init ath79_gpio_init(void)\n+{\n+\treturn platform_driver_register(&ath79_gpio_driver);\n+}\n+postcore_initcall(ath79_gpio_init);\n \n MODULE_DESCRIPTION(\"Atheros AR71XX/AR724X/AR913X GPIO API support\");\n MODULE_LICENSE(\"GPL v2\");\n"
  },
  {
    "path": "target/linux/ath79/patches-5.15/0040-ath79-sgmii-config.patch",
    "content": "--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h\n+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h\n@@ -1376,5 +1376,6 @@\n \n #define QCA956X_SGMII_CONFIG_MODE_CTRL_SHIFT\t0\n #define QCA956X_SGMII_CONFIG_MODE_CTRL_MASK\t0x7\n+#define QCA956X_SGMII_CONFIG_MODE_CTRL_SGMII_MAC\t0x2\n \n #endif /* __ASM_MACH_AR71XX_REGS_H */\n"
  },
  {
    "path": "target/linux/ath79/patches-5.15/0062-MIPS-pci-ar724x-add-QCA9550-reset-sequence.patch",
    "content": "From: David Bauer <mail@david-bauer.net>\nDate: Sat, 11 Apr 2020 14:03:12 +0200\nSubject: MIPS: pci-ar724x: add QCA9550 reset sequence\n\nThe QCA9550 family of SoCs have a slightly different reset\nsequence compared to older chips.\n\nNormally the bootloader performs this sequence, however\nsome bootloader implementation expect the operating system\nto clear the reset.\n\nAlso get the resets from OF to support handling of the second\nPCIe root-complex on the QCA9558.\n\nSigned-off-by: David Bauer <mail@david-bauer.net>\n\n--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h\n+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h\n@@ -391,6 +391,7 @@\n #define QCA955X_PLL_CPU_CONFIG_REG\t\t0x00\n #define QCA955X_PLL_DDR_CONFIG_REG\t\t0x04\n #define QCA955X_PLL_CLK_CTRL_REG\t\t0x08\n+#define QCA955X_PLL_PCIE_CONFIG_REG\t\t0x0c\n #define QCA955X_PLL_ETH_XMII_CONTROL_REG\t0x28\n #define QCA955X_PLL_ETH_SGMII_CONTROL_REG\t0x48\n #define QCA955X_PLL_ETH_SGMII_SERDES_REG\t0x4c\n@@ -476,6 +477,9 @@\n #define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_CPUPLL\tBIT(21)\n #define QCA956X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL\t\tBIT(24)\n \n+#define QCA955X_PLL_PCIE_CONFIG_PLL_PWD\t\t\tBIT(30)\n+#define QCA955X_PLL_PCIE_CONFIG_PLL_BYPASS\t\tBIT(16)\n+\n #define QCA956X_PLL_SWITCH_CLOCK_SPARE_I2C_CLK_SELB\t\tBIT(5)\n #define QCA956X_PLL_SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_1\t\tBIT(6)\n #define QCA956X_PLL_SWITCH_CLOCK_SPARE_UART1_CLK_SEL\t\tBIT(7)\n--- a/arch/mips/pci/pci-ar724x.c\n+++ b/arch/mips/pci/pci-ar724x.c\n@@ -8,6 +8,7 @@\n \n #include <linux/irq.h>\n #include <linux/pci.h>\n+#include <linux/reset.h>\n #include <linux/init.h>\n #include <linux/delay.h>\n #include <linux/platform_device.h>\n@@ -55,6 +56,9 @@ struct ar724x_pci_controller {\n \tstruct irq_domain *domain;\n \tstruct resource io_res;\n \tstruct resource mem_res;\n+\n+\tstruct reset_control *hc_reset;\n+\tstruct reset_control *phy_reset;\n };\n \n static struct irq_chip ar724x_pci_irq_chip;\n@@ -340,18 +344,30 @@ static void ar724x_pci_hw_init(struct ar\n \tint wait = 0;\n \n \t/* deassert PCIe host controller and PCIe PHY reset */\n-\tath79_device_reset_clear(AR724X_RESET_PCIE);\n-\tath79_device_reset_clear(AR724X_RESET_PCIE_PHY);\n+\treset_control_deassert(apc->hc_reset);\n+\treset_control_deassert(apc->phy_reset);\n \n-\t/* remove the reset of the PCIE PLL */\n-\tppl = ath79_pll_rr(AR724X_PLL_REG_PCIE_CONFIG);\n-\tppl &= ~AR724X_PLL_REG_PCIE_CONFIG_PPL_RESET;\n-\tath79_pll_wr(AR724X_PLL_REG_PCIE_CONFIG, ppl);\n-\n-\t/* deassert bypass for the PCIE PLL */\n-\tppl = ath79_pll_rr(AR724X_PLL_REG_PCIE_CONFIG);\n-\tppl &= ~AR724X_PLL_REG_PCIE_CONFIG_PPL_BYPASS;\n-\tath79_pll_wr(AR724X_PLL_REG_PCIE_CONFIG, ppl);\n+\tif (of_device_is_compatible(apc->np, \"qcom,qca9550-pci\")) {\n+\t\t/* remove the reset of the PCIE PLL */\n+\t\tppl = ath79_pll_rr(QCA955X_PLL_PCIE_CONFIG_REG);\n+\t\tppl &= ~QCA955X_PLL_PCIE_CONFIG_PLL_PWD;\n+\t\tath79_pll_wr(QCA955X_PLL_PCIE_CONFIG_REG, ppl);\n+\n+\t\t/* deassert bypass for the PCIE PLL */\n+\t\tppl = ath79_pll_rr(QCA955X_PLL_PCIE_CONFIG_REG);\n+\t\tppl &= ~QCA955X_PLL_PCIE_CONFIG_PLL_BYPASS;\n+\t\tath79_pll_wr(QCA955X_PLL_PCIE_CONFIG_REG, ppl);\n+\t} else {\n+\t\t/* remove the reset of the PCIE PLL */\n+\t\tppl = ath79_pll_rr(AR724X_PLL_REG_PCIE_CONFIG);\n+\t\tppl &= ~AR724X_PLL_REG_PCIE_CONFIG_PPL_RESET;\n+\t\tath79_pll_wr(AR724X_PLL_REG_PCIE_CONFIG, ppl);\n+\n+\t\t/* deassert bypass for the PCIE PLL */\n+\t\tppl = ath79_pll_rr(AR724X_PLL_REG_PCIE_CONFIG);\n+\t\tppl &= ~AR724X_PLL_REG_PCIE_CONFIG_PPL_BYPASS;\n+\t\tath79_pll_wr(AR724X_PLL_REG_PCIE_CONFIG, ppl);\n+\t}\n \n \t/* set PCIE Application Control to ready */\n \tapp = __raw_readl(apc->ctrl_base + AR724X_PCI_REG_APP);\n@@ -396,6 +412,14 @@ static int ar724x_pci_probe(struct platf\n \tif (apc->irq < 0)\n \t\treturn -EINVAL;\n \n+\tapc->hc_reset = devm_reset_control_get_exclusive(&pdev->dev, \"hc\");\n+\tif (IS_ERR(apc->hc_reset))\n+\t\treturn PTR_ERR(apc->hc_reset);\n+\n+\tapc->phy_reset = devm_reset_control_get_exclusive(&pdev->dev, \"phy\");\n+\tif (IS_ERR(apc->phy_reset))\n+\t\treturn PTR_ERR(apc->phy_reset);\n+\n \tapc->np = pdev->dev.of_node;\n \tapc->pci_controller.pci_ops = &ar724x_pci_ops;\n \tapc->pci_controller.io_resource = &apc->io_res;\n@@ -406,7 +430,7 @@ static int ar724x_pci_probe(struct platf\n \t * Do the full PCIE Root Complex Initialization Sequence if the PCIe\n \t * host controller is in reset.\n \t */\n-\tif (ath79_reset_rr(AR724X_RESET_REG_RESET_MODULE) & AR724X_RESET_PCIE)\n+\tif (reset_control_status(apc->hc_reset))\n \t\tar724x_pci_hw_init(apc);\n \n \tapc->link_up = ar724x_pci_check_link(apc);\n@@ -424,6 +448,7 @@ static int ar724x_pci_probe(struct platf\n \n static const struct of_device_id ar724x_pci_ids[] = {\n \t{ .compatible = \"qcom,ar7240-pci\" },\n+\t{ .compatible = \"qcom,qca9550-pci\" },\n \t{},\n };\n \n"
  },
  {
    "path": "target/linux/ath79/patches-5.15/401-mtd-nor-support-mtd-name-from-device-tree.patch",
    "content": "From f32bc2aa01edcba2f2ed5db151cf183eac9ef919 Mon Sep 17 00:00:00 2001\nFrom: Abhimanyu Vishwakarma <Abhimanyu.Vishwakarma@imgtec.com>\nDate: Sat, 25 Feb 2017 16:42:50 +0000\nSubject: mtd: nor: support mtd name from device tree\n\nSigned-off-by: Abhimanyu Vishwakarma <Abhimanyu.Vishwakarma@imgtec.com>\n---\n drivers/mtd/spi-nor/spi-nor.c | 8 +++++++-\n 1 file changed, 7 insertions(+), 1 deletion(-)\n\n--- a/drivers/mtd/spi-nor/core.c\n+++ b/drivers/mtd/spi-nor/core.c\n@@ -3101,6 +3101,7 @@ int spi_nor_scan(struct spi_nor *nor, co\n \tstruct device *dev = nor->dev;\n \tstruct mtd_info *mtd = &nor->mtd;\n \tstruct device_node *np = spi_nor_get_flash_node(nor);\n+\tconst char __maybe_unused *of_mtd_name = NULL;\n \tint ret;\n \tint i;\n \n@@ -3155,7 +3156,12 @@ int spi_nor_scan(struct spi_nor *nor, co\n \tif (ret)\n \t\treturn ret;\n \n-\tif (!mtd->name)\n+#ifdef CONFIG_MTD_OF_PARTS\n+\tof_property_read_string(np, \"linux,mtd-name\", &of_mtd_name);\n+#endif\n+\tif (of_mtd_name)\n+\t\tmtd->name = of_mtd_name;\n+\telse if (!mtd->name)\n \t\tmtd->name = dev_name(dev);\n \tmtd->priv = nor;\n \tmtd->type = MTD_NORFLASH;\n--- a/drivers/mtd/mtdcore.c\n+++ b/drivers/mtd/mtdcore.c\n@@ -778,6 +778,17 @@ out_error:\n  */\n static void mtd_set_dev_defaults(struct mtd_info *mtd)\n {\n+#ifdef CONFIG_MTD_OF_PARTS\n+\tconst char __maybe_unused *of_mtd_name = NULL;\n+\tstruct device_node *np;\n+\n+\tnp = mtd_get_of_node(mtd);\n+\tif (np && !mtd->name) {\n+\t\tof_property_read_string(np, \"linux,mtd-name\", &of_mtd_name);\n+\t\tif (of_mtd_name)\n+\t\t\tmtd->name = of_mtd_name;\n+\t} else\n+#endif\n \tif (mtd->dev.parent) {\n \t\tif (!mtd->owner && mtd->dev.parent->driver)\n \t\t\tmtd->owner = mtd->dev.parent->driver->owner;\n"
  },
  {
    "path": "target/linux/ath79/patches-5.15/402-v5.17-spi-ar934x-fix-transfer-and-word-delays.patch",
    "content": "From c70282457c380db7deb57c81a6894debc8f88efa Mon Sep 17 00:00:00 2001\nFrom: Oskari Lemmela <oskari@lemmela.net>\nDate: Wed, 22 Dec 2021 07:59:58 +0200\nSubject: [PATCH] spi: ar934x: fix transfer and word delays\n\nAdd missing delay between transferred messages and words.\n\nSigned-off-by: Oskari Lemmela <oskari@lemmela.net>\nLink: https://lore.kernel.org/r/20211222055958.1383233-3-oskari@lemmela.net\nSigned-off-by: Mark Brown <broonie@kernel.org>\n---\n drivers/spi/spi-ar934x.c | 2 ++\n 1 file changed, 2 insertions(+)\n\n--- a/drivers/spi/spi-ar934x.c\n+++ b/drivers/spi/spi-ar934x.c\n@@ -137,8 +137,10 @@ static int ar934x_spi_transfer_one_messa\n \t\t\t\t\treg >>= 8;\n \t\t\t\t}\n \t\t\t}\n+\t\t\tspi_delay_exec(&t->word_delay, t);\n \t\t}\n \t\tm->actual_length += t->len;\n+\t\tspi_transfer_delay_exec(t);\n \t}\n \n msg_done:\n"
  },
  {
    "path": "target/linux/ath79/patches-5.15/403-v5.17-spi-ar934x-fix-transfer-size.patch",
    "content": "From ebe33e5a98dcf14a9630845f3f10c193584ac054 Mon Sep 17 00:00:00 2001\nFrom: Oskari Lemmela <oskari@lemmela.net>\nDate: Wed, 22 Dec 2021 07:59:57 +0200\nSubject: [PATCH] spi: ar934x: fix transfer size\n\nIf bits_per_word is configured, transfer only word amount\nof data per iteration.\n\nSigned-off-by: Oskari Lemmela <oskari@lemmela.net>\nLink: https://lore.kernel.org/r/20211222055958.1383233-2-oskari@lemmela.net\nSigned-off-by: Mark Brown <broonie@kernel.org>\n---\n drivers/spi/spi-ar934x.c | 16 +++++++++++-----\n 1 file changed, 11 insertions(+), 5 deletions(-)\n\n--- a/drivers/spi/spi-ar934x.c\n+++ b/drivers/spi/spi-ar934x.c\n@@ -82,7 +82,7 @@ static int ar934x_spi_transfer_one_messa\n \tstruct spi_device *spi = m->spi;\n \tunsigned long trx_done, trx_cur;\n \tint stat = 0;\n-\tu8 term = 0;\n+\tu8 bpw, term = 0;\n \tint div, i;\n \tu32 reg;\n \tconst u8 *tx_buf;\n@@ -90,6 +90,11 @@ static int ar934x_spi_transfer_one_messa\n \n \tm->actual_length = 0;\n \tlist_for_each_entry(t, &m->transfers, transfer_list) {\n+\t\tif (t->bits_per_word >= 8 && t->bits_per_word < 32)\n+\t\t\tbpw = t->bits_per_word >> 3;\n+\t\telse\n+\t\t\tbpw = 4;\n+\n \t\tif (t->speed_hz)\n \t\t\tdiv = ar934x_spi_clk_div(sp, t->speed_hz);\n \t\telse\n@@ -105,10 +110,10 @@ static int ar934x_spi_transfer_one_messa\n \t\tiowrite32(reg, sp->base + AR934X_SPI_REG_CTRL);\n \t\tiowrite32(0, sp->base + AR934X_SPI_DATAOUT);\n \n-\t\tfor (trx_done = 0; trx_done < t->len; trx_done += 4) {\n+\t\tfor (trx_done = 0; trx_done < t->len; trx_done += bpw) {\n \t\t\ttrx_cur = t->len - trx_done;\n-\t\t\tif (trx_cur > 4)\n-\t\t\t\ttrx_cur = 4;\n+\t\t\tif (trx_cur > bpw)\n+\t\t\t\ttrx_cur = bpw;\n \t\t\telse if (list_is_last(&t->transfer_list, &m->transfers))\n \t\t\t\tterm = 1;\n \n@@ -193,7 +198,8 @@ static int ar934x_spi_probe(struct platf\n \tctlr->mode_bits = SPI_LSB_FIRST;\n \tctlr->setup = ar934x_spi_setup;\n \tctlr->transfer_one_message = ar934x_spi_transfer_one_message;\n-\tctlr->bits_per_word_mask = SPI_BPW_MASK(8);\n+\tctlr->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(24) |\n+\t\t\t\t   SPI_BPW_MASK(16) | SPI_BPW_MASK(8);\n \tctlr->dev.of_node = pdev->dev.of_node;\n \tctlr->num_chipselect = 3;\n \n"
  },
  {
    "path": "target/linux/ath79/patches-5.15/404-mtd-cybertan-trx-parser.patch",
    "content": "--- a/drivers/mtd/parsers/Makefile\n+++ b/drivers/mtd/parsers/Makefile\n@@ -8,6 +8,7 @@ obj-$(CONFIG_MTD_OF_PARTS)\t\t+= ofpart.o\n ofpart-y\t\t\t\t+= ofpart_core.o\n ofpart-$(CONFIG_MTD_OF_PARTS_BCM4908)\t+= ofpart_bcm4908.o\n ofpart-$(CONFIG_MTD_OF_PARTS_LINKSYS_NS)+= ofpart_linksys_ns.o\n+obj-$(CONFIG_MTD_PARSER_CYBERTAN)\t+= parser_cybertan.o\n obj-$(CONFIG_MTD_PARSER_IMAGETAG)\t+= parser_imagetag.o\n obj-$(CONFIG_MTD_AFS_PARTS)\t\t+= afs.o\n obj-$(CONFIG_MTD_PARSER_TRX)\t\t+= parser_trx.o\n--- a/drivers/mtd/parsers/Kconfig\n+++ b/drivers/mtd/parsers/Kconfig\n@@ -102,6 +102,14 @@ config MTD_OF_PARTS_LINKSYS_NS\n \t  two \"firmware\" partitions. Currently used firmware has to be detected\n \t  using CFE environment variable.\n \n+config MTD_PARSER_CYBERTAN\n+\ttristate \"Parser for Cybertan format partitions\"\n+\tdepends on MTD && (ATH79 || COMPILE_TEST)\n+\thelp\n+\t  Cybertan has a proprietory header than encompasses a Broadcom trx\n+\t  header. This driver will parse the header and take care of the\n+\t  special offsets that result in the extra headers.\n+\n config MTD_PARSER_IMAGETAG\n \ttristate \"Parser for BCM963XX Image Tag format partitions\"\n \tdepends on BCM63XX || BMIPS_GENERIC || COMPILE_TEST\n"
  },
  {
    "path": "target/linux/ath79/patches-5.15/408-mtd-redboot_partition_scan.patch",
    "content": "--- a/drivers/mtd/parsers/redboot.c\n+++ b/drivers/mtd/parsers/redboot.c\n@@ -90,12 +90,18 @@ static int parse_redboot_partitions(stru\n \n \tparse_redboot_of(master);\n \n+\tbuf = vmalloc(master->erasesize);\n+\tif (!buf)\n+\t\treturn -ENOMEM;\n+\n+ restart:\n \tif (directory < 0) {\n \t\toffset = master->size + directory * master->erasesize;\n \t\twhile (mtd_block_isbad(master, offset)) {\n \t\t\tif (!offset) {\n nogood:\n \t\t\t\tpr_notice(\"Failed to find a non-bad block to check for RedBoot partition table\\n\");\n+\t\t\t\tvfree(buf);\n \t\t\t\treturn -EIO;\n \t\t\t}\n \t\t\toffset -= master->erasesize;\n@@ -108,10 +114,6 @@ nogood:\n \t\t\t\tgoto nogood;\n \t\t}\n \t}\n-\tbuf = vmalloc(master->erasesize);\n-\n-\tif (!buf)\n-\t\treturn -ENOMEM;\n \n \tpr_notice(\"Searching for RedBoot partition table in %s at offset 0x%lx\\n\",\n \t\t  master->name, offset);\n@@ -183,6 +185,12 @@ nogood:\n \t}\n \tif (i == numslots) {\n \t\t/* Didn't find it */\n+\t\tif (offset + master->erasesize < master->size) {\n+\t\t\t/* not at the end of the flash yet, maybe next block :) */\n+\t\t\tdirectory++;\n+\t\t\tgoto restart;\n+\t\t}\n+\n \t\tpr_notice(\"No RedBoot partition table detected in %s\\n\",\n \t\t\t  master->name);\n \t\tret = 0;\n"
  },
  {
    "path": "target/linux/ath79/patches-5.15/410-spi-ath79-Implement-the-spi_mem-interface.patch",
    "content": "From 8d8cdb4a6ccee5b62cc0dc64651c3946364514dc Mon Sep 17 00:00:00 2001\nFrom: Luiz Angelo Daros de Luca <luizluca@gmail.com>\nDate: Mon, 10 Feb 2020 16:11:27 -0300\nSubject: [PATCH] spi: ath79: Implement the spi_mem interface\n\nSigned-off-by: Luiz Angelo Daros de Luca <luizluca@gmail.com>\n---\n drivers/spi/spi-ath79.c | 35 +++++++++++++++++++++++++++++++++++\n 1 file changed, 35 insertions(+)\n\n--- a/drivers/spi/spi-ath79.c\n+++ b/drivers/spi/spi-ath79.c\n@@ -15,6 +15,7 @@\n #include <linux/platform_device.h>\n #include <linux/io.h>\n #include <linux/spi/spi.h>\n+#include <linux/spi/spi-mem.h>\n #include <linux/spi/spi_bitbang.h>\n #include <linux/bitops.h>\n #include <linux/clk.h>\n@@ -133,6 +134,39 @@ static u32 ath79_spi_txrx_mode0(struct s\n \treturn ath79_spi_rr(sp, AR71XX_SPI_REG_RDS);\n }\n \n+static int ath79_exec_mem_op(struct spi_mem *mem,\n+                              const struct spi_mem_op *op)\n+{\n+\tstruct ath79_spi *sp = ath79_spidev_to_sp(mem->spi);\n+\n+\t/* Ensures that reading is performed on device connected\n+\t   to hardware cs0 */\n+\tif (mem->spi->chip_select || mem->spi->cs_gpiod)\n+\t\treturn -ENOTSUPP;\n+\n+\t/* Only use for fast-read op. */\n+\tif (op->cmd.opcode != 0x0b || op->data.dir != SPI_MEM_DATA_IN ||\n+\t    op->addr.nbytes != 3 || op->dummy.nbytes != 1)\n+\t\treturn -ENOTSUPP;\n+\n+\t/* disable GPIO mode */\n+\tath79_spi_wr(sp, AR71XX_SPI_REG_FS, 0);\n+\n+\tmemcpy_fromio(op->data.buf.in, sp->base + op->addr.val, op->data.nbytes);\n+\n+\t/* enable GPIO mode */\n+\tath79_spi_wr(sp, AR71XX_SPI_REG_FS, AR71XX_SPI_FS_GPIO);\n+\n+\t/* restore IOC register */\n+\tath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);\n+\n+\treturn 0;\n+}\n+\n+static const struct spi_controller_mem_ops ath79_mem_ops = {\n+\t.exec_op = ath79_exec_mem_op,\n+};\n+\n static int ath79_spi_probe(struct platform_device *pdev)\n {\n \tstruct spi_master *master;\n@@ -165,6 +199,7 @@ static int ath79_spi_probe(struct platfo\n \t\tret = PTR_ERR(sp->base);\n \t\tgoto err_put_master;\n \t}\n+\tmaster->mem_ops = &ath79_mem_ops;\n \n \tsp->clk = devm_clk_get(&pdev->dev, \"ahb\");\n \tif (IS_ERR(sp->clk)) {\n"
  },
  {
    "path": "target/linux/ath79/patches-5.15/420-net-use-downstream-ag71xx.patch",
    "content": "--- a/drivers/net/ethernet/atheros/Kconfig\n+++ b/drivers/net/ethernet/atheros/Kconfig\n@@ -17,14 +17,7 @@ config NET_VENDOR_ATHEROS\n \n if NET_VENDOR_ATHEROS\n \n-config AG71XX\n-\ttristate \"Atheros AR7XXX/AR9XXX built-in ethernet mac support\"\n-\tdepends on ATH79\n-\tselect PHYLINK\n-\timply NET_SELFTESTS\n-\thelp\n-\t  If you wish to compile a kernel for AR7XXX/91XXX and enable\n-\t  ethernet support, then you should always answer Y to this.\n+source \"drivers/net/ethernet/atheros/ag71xx/Kconfig\"\n \n config ATL2\n \ttristate \"Atheros L2 Fast Ethernet support\"\n--- a/drivers/net/ethernet/atheros/Makefile\n+++ b/drivers/net/ethernet/atheros/Makefile\n@@ -3,7 +3,7 @@\n # Makefile for the Atheros network device drivers.\n #\n \n-obj-$(CONFIG_AG71XX) += ag71xx.o\n+obj-$(CONFIG_AG71XX) += ag71xx/\n obj-$(CONFIG_ATL1) += atlx/\n obj-$(CONFIG_ATL2) += atlx/\n obj-$(CONFIG_ATL1E) += atl1e/\n"
  },
  {
    "path": "target/linux/ath79/patches-5.15/430-drivers-link-spi-before-mtd.patch",
    "content": "--- a/drivers/Makefile\n+++ b/drivers/Makefile\n@@ -80,8 +80,8 @@ obj-y\t\t\t\t+= scsi/\n obj-y\t\t\t\t+= nvme/\n obj-$(CONFIG_ATA)\t\t+= ata/\n obj-$(CONFIG_TARGET_CORE)\t+= target/\n-obj-$(CONFIG_MTD)\t\t+= mtd/\n obj-$(CONFIG_SPI)\t\t+= spi/\n+obj-$(CONFIG_MTD)\t\t+= mtd/\n obj-$(CONFIG_SPMI)\t\t+= spmi/\n obj-$(CONFIG_HSI)\t\t+= hsi/\n obj-$(CONFIG_SLIMBUS)\t\t+= slimbus/\n"
  },
  {
    "path": "target/linux/ath79/patches-5.15/440-mtd-ar934x-nand-driver.patch",
    "content": "--- a/drivers/mtd/nand/raw/Kconfig\n+++ b/drivers/mtd/nand/raw/Kconfig\n@@ -555,4 +555,12 @@ config MTD_NAND_DISKONCHIP_BBTWRITE\n \t  load time (assuming you build diskonchip as a module) with the module\n \t  parameter \"inftl_bbt_write=1\".\n \n+config MTD_NAND_AR934X\n+\ttristate \"Support for NAND controller on Qualcomm Atheros AR934x/QCA955x SoCs\"\n+\tdepends on ATH79 || COMPILE_TEST\n+\tdepends on HAS_IOMEM\n+\thelp\n+\t  Enables support for NAND controller on Qualcomm Atheros SoCs.\n+\t  This controller is found on AR934x and QCA955x SoCs.\n+\n endif # MTD_RAW_NAND\n--- a/drivers/mtd/nand/raw/Makefile\n+++ b/drivers/mtd/nand/raw/Makefile\n@@ -58,6 +58,7 @@ obj-$(CONFIG_MTD_NAND_ARASAN)\t\t+= arasan\n obj-$(CONFIG_MTD_NAND_INTEL_LGM)\t+= intel-nand-controller.o\n obj-$(CONFIG_MTD_NAND_ROCKCHIP)\t\t+= rockchip-nand-controller.o\n obj-$(CONFIG_MTD_NAND_PL35X)\t\t+= pl35x-nand-controller.o\n+obj-$(CONFIG_MTD_NAND_AR934X)\t\t+= ar934x_nand.o\n \n nand-objs := nand_base.o nand_legacy.o nand_bbt.o nand_timings.o nand_ids.o\n nand-objs += nand_onfi.o\n"
  },
  {
    "path": "target/linux/ath79/patches-5.15/470-MIPS-ath79-swizzle-pci-address-for-ar71xx.patch",
    "content": "--- /dev/null\n+++ b/arch/mips/include/asm/mach-ath79/mangle-port.h\n@@ -0,0 +1,37 @@\n+/*\n+ *  Copyright (C) 2012 Gabor Juhos <juhosg@openwrt.org>\n+ *\n+ *  This file was derived from: inlude/asm-mips/mach-generic/mangle-port.h\n+ *      Copyright (C) 2003, 2004 Ralf Baechle\n+ *\n+ *  This program is free software; you can redistribute it and/or modify it\n+ *  under the terms of the GNU General Public License version 2 as published\n+ *  by the Free Software Foundation.\n+ */\n+\n+#ifndef __ASM_MACH_ATH79_MANGLE_PORT_H\n+#define __ASM_MACH_ATH79_MANGLE_PORT_H\n+\n+#ifdef CONFIG_PCI_AR71XX\n+extern unsigned long (ath79_pci_swizzle_b)(unsigned long port);\n+extern unsigned long (ath79_pci_swizzle_w)(unsigned long port);\n+#else\n+#define ath79_pci_swizzle_b(port) (port)\n+#define ath79_pci_swizzle_w(port) (port)\n+#endif\n+\n+#define __swizzle_addr_b(port)\tath79_pci_swizzle_b(port)\n+#define __swizzle_addr_w(port)\tath79_pci_swizzle_w(port)\n+#define __swizzle_addr_l(port)\t(port)\n+#define __swizzle_addr_q(port)\t(port)\n+\n+# define ioswabb(a, x)           (x)\n+# define __mem_ioswabb(a, x)     (x)\n+# define ioswabw(a, x)           (x)\n+# define __mem_ioswabw(a, x)     cpu_to_le16(x)\n+# define ioswabl(a, x)           (x)\n+# define __mem_ioswabl(a, x)     cpu_to_le32(x)\n+# define ioswabq(a, x)           (x)\n+# define __mem_ioswabq(a, x)     cpu_to_le64(x)\n+\n+#endif /* __ASM_MACH_ATH79_MANGLE_PORT_H */\n--- a/arch/mips/pci/pci-ar71xx.c\n+++ b/arch/mips/pci/pci-ar71xx.c\n@@ -68,6 +68,45 @@ static const u32 ar71xx_pci_read_mask[8]\n \t0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0\n };\n \n+static unsigned long (*__ath79_pci_swizzle_b)(unsigned long port);\n+static unsigned long (*__ath79_pci_swizzle_w)(unsigned long port);\n+\n+static inline bool ar71xx_is_pci_addr(unsigned long port)\n+{\n+\tunsigned long phys = CPHYSADDR(port);\n+\n+\treturn (phys >= AR71XX_PCI_MEM_BASE &&\n+\t\tphys < AR71XX_PCI_MEM_BASE + AR71XX_PCI_MEM_SIZE);\n+}\n+\n+static unsigned long ar71xx_pci_swizzle_b(unsigned long port)\n+{\n+\treturn ar71xx_is_pci_addr(port) ? port ^ 3 : port;\n+}\n+\n+static unsigned long ar71xx_pci_swizzle_w(unsigned long port)\n+{\n+\treturn ar71xx_is_pci_addr(port) ? port ^ 2 : port;\n+}\n+\n+unsigned long ath79_pci_swizzle_b(unsigned long port)\n+{\n+\tif (__ath79_pci_swizzle_b)\n+\t\treturn __ath79_pci_swizzle_b(port);\n+\n+\treturn port;\n+}\n+EXPORT_SYMBOL(ath79_pci_swizzle_b);\n+\n+unsigned long ath79_pci_swizzle_w(unsigned long port)\n+{\n+\tif (__ath79_pci_swizzle_w)\n+\t\treturn __ath79_pci_swizzle_w(port);\n+\n+\treturn port;\n+}\n+EXPORT_SYMBOL(ath79_pci_swizzle_w);\n+\n static inline u32 ar71xx_pci_get_ble(int where, int size, int local)\n {\n \tu32 t;\n@@ -276,6 +315,9 @@ static int ar71xx_pci_probe(struct platf\n \n \tregister_pci_controller(&apc->pci_ctrl);\n \n+\t__ath79_pci_swizzle_b = ar71xx_pci_swizzle_b;\n+\t__ath79_pci_swizzle_w = ar71xx_pci_swizzle_w;\n+\n \treturn 0;\n }\n \n"
  },
  {
    "path": "target/linux/ath79/patches-5.15/600-of_net-add-mac-address-ascii-support.patch",
    "content": "--- a/net/ethernet/eth.c\n+++ b/net/ethernet/eth.c\n@@ -544,6 +544,63 @@ int eth_platform_get_mac_address(struct\n }\n EXPORT_SYMBOL(eth_platform_get_mac_address);\n \n+static void *nvmem_cell_get_mac_address(struct nvmem_cell *cell)\n+{\n+\tsize_t len;\n+\tvoid *mac;\n+\n+\tmac = nvmem_cell_read(cell, &len);\n+\tif (IS_ERR(mac))\n+\t\treturn PTR_ERR(mac);\n+\tif (len != ETH_ALEN) {\n+\t\tkfree(mac);\n+\t\treturn ERR_PTR(-EINVAL);\n+\t}\n+\treturn mac;\n+}\n+\n+static void *nvmem_cell_get_mac_address_ascii(struct nvmem_cell *cell)\n+{\n+\tsize_t len;\n+\tint ret;\n+\tvoid *mac_ascii;\n+\tu8 *mac;\n+\n+\tmac_ascii = nvmem_cell_read(cell, &len);\n+\tif (IS_ERR(mac_ascii))\n+\t\treturn PTR_ERR(mac_ascii);\n+\tif (len != ETH_ALEN*2+5) {\n+\t\tkfree(mac_ascii);\n+\t\treturn ERR_PTR(-EINVAL);\n+\t}\n+\tmac = kmalloc(ETH_ALEN, GFP_KERNEL);\n+\tif (!mac) {\n+\t\tkfree(mac_ascii);\n+\t\treturn ERR_PTR(-ENOMEM);\n+\t}\n+\tret = sscanf(mac_ascii, \"%2hhx:%2hhx:%2hhx:%2hhx:%2hhx:%2hhx\",\n+\t\t\t\t&mac[0], &mac[1], &mac[2],\n+\t\t\t\t&mac[3], &mac[4], &mac[5]);\n+\tkfree(mac_ascii);\n+\tif (ret == ETH_ALEN)\n+\t\treturn mac;\n+\tkfree(mac);\n+\treturn ERR_PTR(-EINVAL);\n+}\n+\n+static struct nvmem_cell_mac_address_property {\n+\tchar *name;\n+\tvoid *(*read)(struct nvmem_cell *);\n+} nvmem_cell_mac_address_properties[] = {\n+\t{\n+\t\t.name = \"mac-address\",\n+\t\t.read = nvmem_cell_get_mac_address,\n+\t}, {\n+\t\t.name = \"mac-address-ascii\",\n+\t\t.read = nvmem_cell_get_mac_address_ascii,\n+\t},\n+};\n+\n /**\n  * nvmem_get_mac_address - Obtain the MAC address from an nvmem cell named\n  * 'mac-address' associated with given device.\n@@ -557,19 +614,23 @@ int nvmem_get_mac_address(struct device\n {\n \tstruct nvmem_cell *cell;\n \tconst void *mac;\n-\tsize_t len;\n+\tstruct nvmem_cell_mac_address_property *property;\n+\tint i;\n \n-\tcell = nvmem_cell_get(dev, \"mac-address\");\n-\tif (IS_ERR(cell))\n-\t\treturn PTR_ERR(cell);\n-\n-\tmac = nvmem_cell_read(cell, &len);\n-\tnvmem_cell_put(cell);\n-\n-\tif (IS_ERR(mac))\n-\t\treturn PTR_ERR(mac);\n+\tfor (i = 0; i < ARRAY_SIZE(nvmem_cell_mac_address_properties); i++) {\n+\t\tproperty = &nvmem_cell_mac_address_properties[i];\n+\t\tcell = nvmem_cell_get(dev, property->name);\n+\t\tif (IS_ERR(cell)) {\n+\t\t\tif (i == ARRAY_SIZE(nvmem_cell_mac_address_properties) - 1)\n+\t\t\t\treturn PTR_ERR(cell);\n+\t\t\tcontinue;\n+\t\t}\n+\t\tmac = property->read(cell);\n+\t\tnvmem_cell_put(cell);\n+\t\tbreak;\n+\t}\n \n-\tif (len != ETH_ALEN || !is_valid_ether_addr(mac)) {\n+\tif (!is_valid_ether_addr(mac)) {\n \t\tkfree(mac);\n \t\treturn -EINVAL;\n \t}\n"
  },
  {
    "path": "target/linux/ath79/patches-5.15/900-mdio_bitbang_ignore_ta_value.patch",
    "content": "--- a/drivers/net/mdio/mdio-bitbang.c\n+++ b/drivers/net/mdio/mdio-bitbang.c\n@@ -152,7 +152,7 @@ static int mdiobb_cmd_addr(struct mdiobb\n int mdiobb_read(struct mii_bus *bus, int phy, int reg)\n {\n \tstruct mdiobb_ctrl *ctrl = bus->priv;\n-\tint ret, i;\n+\tint ret;\n \n \tif (reg & MII_ADDR_C45) {\n \t\treg = mdiobb_cmd_addr(ctrl, phy, reg);\n@@ -162,19 +162,7 @@ int mdiobb_read(struct mii_bus *bus, int\n \n \tctrl->ops->set_mdio_dir(ctrl, 0);\n \n-\t/* check the turnaround bit: the PHY should be driving it to zero, if this\n-\t * PHY is listed in phy_ignore_ta_mask as having broken TA, skip that\n-\t */\n-\tif (mdiobb_get_bit(ctrl) != 0 &&\n-\t    !(bus->phy_ignore_ta_mask & (1 << phy))) {\n-\t\t/* PHY didn't drive TA low -- flush any bits it\n-\t\t * may be trying to send.\n-\t\t */\n-\t\tfor (i = 0; i < 32; i++)\n-\t\t\tmdiobb_get_bit(ctrl);\n-\n-\t\treturn 0xffff;\n-\t}\n+\tmdiobb_get_bit(ctrl);\n \n \tret = mdiobb_get_num(ctrl, 16);\n \tmdiobb_get_bit(ctrl);\n"
  },
  {
    "path": "target/linux/ath79/patches-5.15/901-phy-mdio-bitbang-prevent-rescheduling-during-command.patch",
    "content": "From 66e584435ac0de6e0abeb6d7166fe4fe25d6bb73 Mon Sep 17 00:00:00 2001\nFrom: Jonas Gorski <jogo@openwrt.org>\nDate: Tue, 16 Jun 2015 13:15:08 +0200\nSubject: [PATCH] phy/mdio-bitbang: prevent rescheduling during command\n\nIt seems some phys have some maximum timings for accessing the MDIO line,\nresulting in bit errors under cpu stress. Prevent this from happening by\ndisabling interrupts when sending commands.\n\nSigned-off-by: Jonas Gorski <jogo@openwrt.org>\n---\n drivers/net/mdio/mdio-bitbang.c | 9 +++++++++\n 1 file changed, 9 insertions(+)\n\n--- a/drivers/net/mdio/mdio-bitbang.c\n+++ b/drivers/net/mdio/mdio-bitbang.c\n@@ -14,6 +14,7 @@\n  * Vitaly Bordug <vbordug@ru.mvista.com>\n  */\n \n+#include <linux/irqflags.h>\n #include <linux/delay.h>\n #include <linux/mdio-bitbang.h>\n #include <linux/module.h>\n@@ -153,7 +154,9 @@ int mdiobb_read(struct mii_bus *bus, int\n {\n \tstruct mdiobb_ctrl *ctrl = bus->priv;\n \tint ret;\n+\tunsigned long flags;\n \n+\tlocal_irq_save(flags);\n \tif (reg & MII_ADDR_C45) {\n \t\treg = mdiobb_cmd_addr(ctrl, phy, reg);\n \t\tmdiobb_cmd(ctrl, MDIO_C45_READ, phy, reg);\n@@ -166,6 +169,7 @@ int mdiobb_read(struct mii_bus *bus, int\n \n \tret = mdiobb_get_num(ctrl, 16);\n \tmdiobb_get_bit(ctrl);\n+\tlocal_irq_restore(flags);\n \treturn ret;\n }\n EXPORT_SYMBOL(mdiobb_read);\n@@ -173,7 +177,9 @@ EXPORT_SYMBOL(mdiobb_read);\n int mdiobb_write(struct mii_bus *bus, int phy, int reg, u16 val)\n {\n \tstruct mdiobb_ctrl *ctrl = bus->priv;\n+\tunsigned long flags;\n \n+\tlocal_irq_save(flags);\n \tif (reg & MII_ADDR_C45) {\n \t\treg = mdiobb_cmd_addr(ctrl, phy, reg);\n \t\tmdiobb_cmd(ctrl, MDIO_C45_WRITE, phy, reg);\n@@ -188,6 +194,8 @@ int mdiobb_write(struct mii_bus *bus, in\n \n \tctrl->ops->set_mdio_dir(ctrl, 0);\n \tmdiobb_get_bit(ctrl);\n+\tlocal_irq_restore(flags);\n+\n \treturn 0;\n }\n EXPORT_SYMBOL(mdiobb_write);\n"
  },
  {
    "path": "target/linux/ath79/patches-5.15/910-unaligned_access_hacks.patch",
    "content": "--- a/arch/mips/include/asm/checksum.h\n+++ b/arch/mips/include/asm/checksum.h\n@@ -100,26 +100,30 @@ static inline __sum16 ip_fast_csum(const\n \tconst unsigned int *stop = word + ihl;\n \tunsigned int csum;\n \tint carry;\n+\tunsigned int w;\n \n-\tcsum = word[0];\n-\tcsum += word[1];\n-\tcarry = (csum < word[1]);\n+\tcsum = net_hdr_word(word++);\n+\n+\tw = net_hdr_word(word++);\n+\tcsum += w;\n+\tcarry = (csum < w);\n \tcsum += carry;\n \n-\tcsum += word[2];\n-\tcarry = (csum < word[2]);\n+\tw = net_hdr_word(word++);\n+\tcsum += w;\n+\tcarry = (csum < w);\n \tcsum += carry;\n \n-\tcsum += word[3];\n-\tcarry = (csum < word[3]);\n+\tw = net_hdr_word(word++);\n+\tcsum += w;\n+\tcarry = (csum < w);\n \tcsum += carry;\n \n-\tword += 4;\n \tdo {\n-\t\tcsum += *word;\n-\t\tcarry = (csum < *word);\n+\t\tw = net_hdr_word(word++);\n+\t\tcsum += w;\n+\t\tcarry = (csum < w);\n \t\tcsum += carry;\n-\t\tword++;\n \t} while (word != stop);\n \n \treturn csum_fold(csum);\n@@ -182,73 +186,6 @@ static inline __sum16 ip_compute_csum(co\n \treturn csum_fold(csum_partial(buff, len, 0));\n }\n \n-#define _HAVE_ARCH_IPV6_CSUM\n-static __inline__ __sum16 csum_ipv6_magic(const struct in6_addr *saddr,\n-\t\t\t\t\t  const struct in6_addr *daddr,\n-\t\t\t\t\t  __u32 len, __u8 proto,\n-\t\t\t\t\t  __wsum sum)\n-{\n-\t__wsum tmp;\n-\n-\t__asm__(\n-\t\"\t.set\tpush\t\t# csum_ipv6_magic\\n\"\n-\t\"\t.set\tnoreorder\t\\n\"\n-\t\"\t.set\tnoat\t\t\\n\"\n-\t\"\taddu\t%0, %5\t\t# proto (long in network byte order)\\n\"\n-\t\"\tsltu\t$1, %0, %5\t\\n\"\n-\t\"\taddu\t%0, $1\t\t\\n\"\n-\n-\t\"\taddu\t%0, %6\t\t# csum\\n\"\n-\t\"\tsltu\t$1, %0, %6\t\\n\"\n-\t\"\tlw\t%1, 0(%2)\t# four words source address\\n\"\n-\t\"\taddu\t%0, $1\t\t\\n\"\n-\t\"\taddu\t%0, %1\t\t\\n\"\n-\t\"\tsltu\t$1, %0, %1\t\\n\"\n-\n-\t\"\tlw\t%1, 4(%2)\t\\n\"\n-\t\"\taddu\t%0, $1\t\t\\n\"\n-\t\"\taddu\t%0, %1\t\t\\n\"\n-\t\"\tsltu\t$1, %0, %1\t\\n\"\n-\n-\t\"\tlw\t%1, 8(%2)\t\\n\"\n-\t\"\taddu\t%0, $1\t\t\\n\"\n-\t\"\taddu\t%0, %1\t\t\\n\"\n-\t\"\tsltu\t$1, %0, %1\t\\n\"\n-\n-\t\"\tlw\t%1, 12(%2)\t\\n\"\n-\t\"\taddu\t%0, $1\t\t\\n\"\n-\t\"\taddu\t%0, %1\t\t\\n\"\n-\t\"\tsltu\t$1, %0, %1\t\\n\"\n-\n-\t\"\tlw\t%1, 0(%3)\t\\n\"\n-\t\"\taddu\t%0, $1\t\t\\n\"\n-\t\"\taddu\t%0, %1\t\t\\n\"\n-\t\"\tsltu\t$1, %0, %1\t\\n\"\n-\n-\t\"\tlw\t%1, 4(%3)\t\\n\"\n-\t\"\taddu\t%0, $1\t\t\\n\"\n-\t\"\taddu\t%0, %1\t\t\\n\"\n-\t\"\tsltu\t$1, %0, %1\t\\n\"\n-\n-\t\"\tlw\t%1, 8(%3)\t\\n\"\n-\t\"\taddu\t%0, $1\t\t\\n\"\n-\t\"\taddu\t%0, %1\t\t\\n\"\n-\t\"\tsltu\t$1, %0, %1\t\\n\"\n-\n-\t\"\tlw\t%1, 12(%3)\t\\n\"\n-\t\"\taddu\t%0, $1\t\t\\n\"\n-\t\"\taddu\t%0, %1\t\t\\n\"\n-\t\"\tsltu\t$1, %0, %1\t\\n\"\n-\n-\t\"\taddu\t%0, $1\t\t# Add final carry\\n\"\n-\t\"\t.set\tpop\"\n-\t: \"=&r\" (sum), \"=&r\" (tmp)\n-\t: \"r\" (saddr), \"r\" (daddr),\n-\t  \"0\" (htonl(len)), \"r\" (htonl(proto)), \"r\" (sum));\n-\n-\treturn csum_fold(sum);\n-}\n-\n #include <asm-generic/checksum.h>\n #endif /* CONFIG_GENERIC_CSUM */\n \n--- a/include/uapi/linux/ip.h\n+++ b/include/uapi/linux/ip.h\n@@ -103,7 +103,7 @@ struct iphdr {\n \t__be32\tsaddr;\n \t__be32\tdaddr;\n \t/*The options start here. */\n-};\n+} __attribute__((packed, aligned(2)));\n \n \n struct ip_auth_hdr {\n--- a/include/uapi/linux/ipv6.h\n+++ b/include/uapi/linux/ipv6.h\n@@ -132,7 +132,7 @@ struct ipv6hdr {\n \n \tstruct\tin6_addr\tsaddr;\n \tstruct\tin6_addr\tdaddr;\n-};\n+} __attribute__((packed, aligned(2)));\n \n \n /* index values for the variables in ipv6_devconf */\n--- a/include/uapi/linux/tcp.h\n+++ b/include/uapi/linux/tcp.h\n@@ -55,7 +55,7 @@ struct tcphdr {\n \t__be16\twindow;\n \t__sum16\tcheck;\n \t__be16\turg_ptr;\n-};\n+} __attribute__((packed, aligned(2)));\n \n /*\n  *\tThe union cast uses a gcc extension to avoid aliasing problems\n@@ -65,7 +65,7 @@ struct tcphdr {\n union tcp_word_hdr {\n \tstruct tcphdr hdr;\n \t__be32        words[5];\n-};\n+} __attribute__((packed, aligned(2)));\n \n #define tcp_flag_word(tp) (((union tcp_word_hdr *)(tp))->words[3])\n \n--- a/include/uapi/linux/udp.h\n+++ b/include/uapi/linux/udp.h\n@@ -25,7 +25,7 @@ struct udphdr {\n \t__be16\tdest;\n \t__be16\tlen;\n \t__sum16\tcheck;\n-};\n+} __attribute__((packed, aligned(2)));\n \n /* UDP socket options */\n #define UDP_CORK\t1\t/* Never send partially complete segments */\n--- a/net/netfilter/nf_conntrack_core.c\n+++ b/net/netfilter/nf_conntrack_core.c\n@@ -305,8 +305,8 @@ nf_ct_get_tuple(const struct sk_buff *sk\n \n \tswitch (l3num) {\n \tcase NFPROTO_IPV4:\n-\t\ttuple->src.u3.ip = ap[0];\n-\t\ttuple->dst.u3.ip = ap[1];\n+\t\ttuple->src.u3.ip = net_hdr_word(ap++);\n+\t\ttuple->dst.u3.ip = net_hdr_word(ap);\n \t\tbreak;\n \tcase NFPROTO_IPV6:\n \t\tmemcpy(tuple->src.u3.ip6, ap, sizeof(tuple->src.u3.ip6));\n--- a/include/uapi/linux/icmp.h\n+++ b/include/uapi/linux/icmp.h\n@@ -102,7 +102,7 @@ struct icmphdr {\n \t} frag;\n \t__u8\treserved[4];\n   } un;\n-};\n+} __attribute__((packed, aligned(2)));\n \n \n /*\n--- a/include/uapi/linux/in6.h\n+++ b/include/uapi/linux/in6.h\n@@ -43,7 +43,7 @@ struct in6_addr {\n #define s6_addr16\t\tin6_u.u6_addr16\n #define s6_addr32\t\tin6_u.u6_addr32\n #endif\n-};\n+} __attribute__((packed, aligned(2)));\n #endif /* __UAPI_DEF_IN6_ADDR */\n \n #if __UAPI_DEF_SOCKADDR_IN6\n--- a/net/ipv6/tcp_ipv6.c\n+++ b/net/ipv6/tcp_ipv6.c\n@@ -35,6 +35,7 @@\n #include <linux/ipsec.h>\n #include <linux/times.h>\n #include <linux/slab.h>\n+#include <asm/unaligned.h>\n #include <linux/uaccess.h>\n #include <linux/ipv6.h>\n #include <linux/icmpv6.h>\n@@ -941,10 +942,10 @@ static void tcp_v6_send_response(const s\n \ttopt = (__be32 *)(t1 + 1);\n \n \tif (tsecr) {\n-\t\t*topt++ = htonl((TCPOPT_NOP << 24) | (TCPOPT_NOP << 16) |\n-\t\t\t\t(TCPOPT_TIMESTAMP << 8) | TCPOLEN_TIMESTAMP);\n-\t\t*topt++ = htonl(tsval);\n-\t\t*topt++ = htonl(tsecr);\n+\t\tput_unaligned_be32((TCPOPT_NOP << 24) | (TCPOPT_NOP << 16) |\n+\t\t\t\t(TCPOPT_TIMESTAMP << 8) | TCPOLEN_TIMESTAMP, topt++);\n+\t\tput_unaligned_be32(tsval, topt++);\n+\t\tput_unaligned_be32(tsecr, topt++);\n \t}\n \n \tif (mrst)\n--- a/include/linux/ipv6.h\n+++ b/include/linux/ipv6.h\n@@ -6,6 +6,7 @@\n \n #define ipv6_optlen(p)  (((p)->hdrlen+1) << 3)\n #define ipv6_authlen(p) (((p)->hdrlen+2) << 2)\n+\n /*\n  * This structure contains configuration options per IPv6 link.\n  */\n--- a/net/ipv6/datagram.c\n+++ b/net/ipv6/datagram.c\n@@ -492,7 +492,7 @@ int ipv6_recv_error(struct sock *sk, str\n \t\t\t\tipv6_iface_scope_id(&sin->sin6_addr,\n \t\t\t\t\t\t    IP6CB(skb)->iif);\n \t\t} else {\n-\t\t\tipv6_addr_set_v4mapped(*(__be32 *)(nh + serr->addr_offset),\n+\t\t\tipv6_addr_set_v4mapped(net_hdr_word(nh + serr->addr_offset),\n \t\t\t\t\t       &sin->sin6_addr);\n \t\t\tsin->sin6_scope_id = 0;\n \t\t}\n@@ -846,12 +846,12 @@ int ip6_datagram_send_ctl(struct net *ne\n \t\t\t}\n \n \t\t\tif (fl6->flowlabel&IPV6_FLOWINFO_MASK) {\n-\t\t\t\tif ((fl6->flowlabel^*(__be32 *)CMSG_DATA(cmsg))&~IPV6_FLOWINFO_MASK) {\n+\t\t\t\tif ((fl6->flowlabel^net_hdr_word(CMSG_DATA(cmsg)))&~IPV6_FLOWINFO_MASK) {\n \t\t\t\t\terr = -EINVAL;\n \t\t\t\t\tgoto exit_f;\n \t\t\t\t}\n \t\t\t}\n-\t\t\tfl6->flowlabel = IPV6_FLOWINFO_MASK & *(__be32 *)CMSG_DATA(cmsg);\n+\t\t\tfl6->flowlabel = IPV6_FLOWINFO_MASK & net_hdr_word(CMSG_DATA(cmsg));\n \t\t\tbreak;\n \n \t\tcase IPV6_2292HOPOPTS:\n--- a/net/ipv6/exthdrs.c\n+++ b/net/ipv6/exthdrs.c\n@@ -1009,7 +1009,7 @@ static bool ipv6_hop_jumbo(struct sk_buf\n \t\tgoto drop;\n \t}\n \n-\tpkt_len = ntohl(*(__be32 *)(nh + optoff + 2));\n+\tpkt_len = ntohl(net_hdr_word(nh + optoff + 2));\n \tif (pkt_len <= IPV6_MAXPLEN) {\n \t\t__IP6_INC_STATS(net, idev, IPSTATS_MIB_INHDRERRORS);\n \t\ticmpv6_param_prob(skb, ICMPV6_HDR_FIELD, optoff+2);\n--- a/include/linux/types.h\n+++ b/include/linux/types.h\n@@ -231,5 +231,11 @@ typedef void (*swap_func_t)(void *a, voi\n typedef int (*cmp_r_func_t)(const void *a, const void *b, const void *priv);\n typedef int (*cmp_func_t)(const void *a, const void *b);\n \n+struct net_hdr_word {\n+       u32 words[1];\n+} __attribute__((packed, aligned(2)));\n+\n+#define net_hdr_word(_p) (((struct net_hdr_word *) (_p))->words[0])\n+\n #endif /*  __ASSEMBLY__ */\n #endif /* _LINUX_TYPES_H */\n--- a/net/ipv4/af_inet.c\n+++ b/net/ipv4/af_inet.c\n@@ -1475,8 +1475,8 @@ struct sk_buff *inet_gro_receive(struct\n \tif (unlikely(ip_fast_csum((u8 *)iph, 5)))\n \t\tgoto out_unlock;\n \n-\tid = ntohl(*(__be32 *)&iph->id);\n-\tflush = (u16)((ntohl(*(__be32 *)iph) ^ skb_gro_len(skb)) | (id & ~IP_DF));\n+\tid = ntohl(net_hdr_word(&iph->id));\n+\tflush = (u16)((ntohl(net_hdr_word(iph)) ^ skb_gro_len(skb)) | (id & ~IP_DF));\n \tid >>= 16;\n \n \tlist_for_each_entry(p, head, list) {\n--- a/net/ipv4/tcp_output.c\n+++ b/net/ipv4/tcp_output.c\n@@ -613,48 +613,53 @@ static void tcp_options_write(__be32 *pt\n \tu16 options = opts->options;\t/* mungable copy */\n \n \tif (unlikely(OPTION_MD5 & options)) {\n-\t\t*ptr++ = htonl((TCPOPT_NOP << 24) | (TCPOPT_NOP << 16) |\n-\t\t\t       (TCPOPT_MD5SIG << 8) | TCPOLEN_MD5SIG);\n+\t\tnet_hdr_word(ptr++) =\n+\t\t\thtonl((TCPOPT_NOP << 24) | (TCPOPT_NOP << 16) |\n+\t\t\t      (TCPOPT_MD5SIG << 8) | TCPOLEN_MD5SIG);\n \t\t/* overload cookie hash location */\n \t\topts->hash_location = (__u8 *)ptr;\n \t\tptr += 4;\n \t}\n \n \tif (unlikely(opts->mss)) {\n-\t\t*ptr++ = htonl((TCPOPT_MSS << 24) |\n-\t\t\t       (TCPOLEN_MSS << 16) |\n-\t\t\t       opts->mss);\n+\t\tnet_hdr_word(ptr++) =\n+\t\t\thtonl((TCPOPT_MSS << 24) | (TCPOLEN_MSS << 16) |\n+\t\t\t      opts->mss);\n \t}\n \n \tif (likely(OPTION_TS & options)) {\n \t\tif (unlikely(OPTION_SACK_ADVERTISE & options)) {\n-\t\t\t*ptr++ = htonl((TCPOPT_SACK_PERM << 24) |\n-\t\t\t\t       (TCPOLEN_SACK_PERM << 16) |\n-\t\t\t\t       (TCPOPT_TIMESTAMP << 8) |\n-\t\t\t\t       TCPOLEN_TIMESTAMP);\n+\t\t\tnet_hdr_word(ptr++) =\n+\t\t\t\thtonl((TCPOPT_SACK_PERM << 24) |\n+\t\t\t\t      (TCPOLEN_SACK_PERM << 16) |\n+\t\t\t\t      (TCPOPT_TIMESTAMP << 8) |\n+\t\t\t\t      TCPOLEN_TIMESTAMP);\n \t\t\toptions &= ~OPTION_SACK_ADVERTISE;\n \t\t} else {\n-\t\t\t*ptr++ = htonl((TCPOPT_NOP << 24) |\n-\t\t\t\t       (TCPOPT_NOP << 16) |\n-\t\t\t\t       (TCPOPT_TIMESTAMP << 8) |\n-\t\t\t\t       TCPOLEN_TIMESTAMP);\n+\t\t\tnet_hdr_word(ptr++) =\n+\t\t\t\thtonl((TCPOPT_NOP << 24) |\n+\t\t\t\t      (TCPOPT_NOP << 16) |\n+\t\t\t\t      (TCPOPT_TIMESTAMP << 8) |\n+\t\t\t\t      TCPOLEN_TIMESTAMP);\n \t\t}\n-\t\t*ptr++ = htonl(opts->tsval);\n-\t\t*ptr++ = htonl(opts->tsecr);\n+\t\tnet_hdr_word(ptr++) = htonl(opts->tsval);\n+\t\tnet_hdr_word(ptr++) = htonl(opts->tsecr);\n \t}\n \n \tif (unlikely(OPTION_SACK_ADVERTISE & options)) {\n-\t\t*ptr++ = htonl((TCPOPT_NOP << 24) |\n-\t\t\t       (TCPOPT_NOP << 16) |\n-\t\t\t       (TCPOPT_SACK_PERM << 8) |\n-\t\t\t       TCPOLEN_SACK_PERM);\n+\t\tnet_hdr_word(ptr++) =\n+\t\t\thtonl((TCPOPT_NOP << 24) |\n+\t\t\t      (TCPOPT_NOP << 16) |\n+\t\t\t      (TCPOPT_SACK_PERM << 8) |\n+\t\t\t      TCPOLEN_SACK_PERM);\n \t}\n \n \tif (unlikely(OPTION_WSCALE & options)) {\n-\t\t*ptr++ = htonl((TCPOPT_NOP << 24) |\n-\t\t\t       (TCPOPT_WINDOW << 16) |\n-\t\t\t       (TCPOLEN_WINDOW << 8) |\n-\t\t\t       opts->ws);\n+\t\tnet_hdr_word(ptr++) =\n+\t\t\thtonl((TCPOPT_NOP << 24) |\n+\t\t\t      (TCPOPT_WINDOW << 16) |\n+\t\t\t      (TCPOLEN_WINDOW << 8) |\n+\t\t\t      opts->ws);\n \t}\n \n \tif (unlikely(opts->num_sack_blocks)) {\n@@ -662,16 +667,17 @@ static void tcp_options_write(__be32 *pt\n \t\t\ttp->duplicate_sack : tp->selective_acks;\n \t\tint this_sack;\n \n-\t\t*ptr++ = htonl((TCPOPT_NOP  << 24) |\n-\t\t\t       (TCPOPT_NOP  << 16) |\n-\t\t\t       (TCPOPT_SACK <<  8) |\n-\t\t\t       (TCPOLEN_SACK_BASE + (opts->num_sack_blocks *\n+\t\tnet_hdr_word(ptr++) =\n+\t\t\thtonl((TCPOPT_NOP << 24) |\n+\t\t\t      (TCPOPT_NOP << 16) |\n+\t\t\t      (TCPOPT_SACK << 8) |\n+\t\t\t      (TCPOLEN_SACK_BASE + (opts->num_sack_blocks *\n \t\t\t\t\t\t     TCPOLEN_SACK_PERBLOCK)));\n \n \t\tfor (this_sack = 0; this_sack < opts->num_sack_blocks;\n \t\t     ++this_sack) {\n-\t\t\t*ptr++ = htonl(sp[this_sack].start_seq);\n-\t\t\t*ptr++ = htonl(sp[this_sack].end_seq);\n+\t\t\tnet_hdr_word(ptr++) = htonl(sp[this_sack].start_seq);\n+\t\t\tnet_hdr_word(ptr++) = htonl(sp[this_sack].end_seq);\n \t\t}\n \n \t\ttp->rx_opt.dsack = 0;\n@@ -684,13 +690,14 @@ static void tcp_options_write(__be32 *pt\n \n \t\tif (foc->exp) {\n \t\t\tlen = TCPOLEN_EXP_FASTOPEN_BASE + foc->len;\n-\t\t\t*ptr = htonl((TCPOPT_EXP << 24) | (len << 16) |\n+\t\t\tnet_hdr_word(ptr) =\n+\t\t\t\thtonl((TCPOPT_EXP << 24) | (len << 16) |\n \t\t\t\t     TCPOPT_FASTOPEN_MAGIC);\n \t\t\tp += TCPOLEN_EXP_FASTOPEN_BASE;\n \t\t} else {\n \t\t\tlen = TCPOLEN_FASTOPEN_BASE + foc->len;\n-\t\t\t*p++ = TCPOPT_FASTOPEN;\n-\t\t\t*p++ = len;\n+\t\t\tnet_hdr_word(p++) = TCPOPT_FASTOPEN;\n+\t\t\tnet_hdr_word(p++) = len;\n \t\t}\n \n \t\tmemcpy(p, foc->val, foc->len);\n--- a/include/uapi/linux/igmp.h\n+++ b/include/uapi/linux/igmp.h\n@@ -33,7 +33,7 @@ struct igmphdr {\n \t__u8 code;\t\t/* For newer IGMP */\n \t__sum16 csum;\n \t__be32 group;\n-};\n+} __attribute__((packed, aligned(2)));\n \n /* V3 group record types [grec_type] */\n #define IGMPV3_MODE_IS_INCLUDE\t\t1\n@@ -49,7 +49,7 @@ struct igmpv3_grec {\n \t__be16\tgrec_nsrcs;\n \t__be32\tgrec_mca;\n \t__be32\tgrec_src[0];\n-};\n+} __attribute__((packed, aligned(2)));\n \n struct igmpv3_report {\n \t__u8 type;\n@@ -58,7 +58,7 @@ struct igmpv3_report {\n \t__be16 resv2;\n \t__be16 ngrec;\n \tstruct igmpv3_grec grec[0];\n-};\n+} __attribute__((packed, aligned(2)));\n \n struct igmpv3_query {\n \t__u8 type;\n@@ -79,7 +79,7 @@ struct igmpv3_query {\n \t__u8 qqic;\n \t__be16 nsrcs;\n \t__be32 srcs[0];\n-};\n+} __attribute__((packed, aligned(2)));\n \n #define IGMP_HOST_MEMBERSHIP_QUERY\t0x11\t/* From RFC1112 */\n #define IGMP_HOST_MEMBERSHIP_REPORT\t0x12\t/* Ditto */\n--- a/net/core/flow_dissector.c\n+++ b/net/core/flow_dissector.c\n@@ -129,7 +129,7 @@ __be32 __skb_flow_get_ports(const struct\n \t\tports = __skb_header_pointer(skb, thoff + poff,\n \t\t\t\t\t     sizeof(_ports), data, hlen, &_ports);\n \t\tif (ports)\n-\t\t\treturn *ports;\n+\t\t\treturn (__be32)net_hdr_word(ports);\n \t}\n \n \treturn 0;\n--- a/include/uapi/linux/icmpv6.h\n+++ b/include/uapi/linux/icmpv6.h\n@@ -78,7 +78,7 @@ struct icmp6hdr {\n #define icmp6_addrconf_other\ticmp6_dataun.u_nd_ra.other\n #define icmp6_rt_lifetime\ticmp6_dataun.u_nd_ra.rt_lifetime\n #define icmp6_router_pref\ticmp6_dataun.u_nd_ra.router_pref\n-};\n+} __attribute__((packed, aligned(2)));\n \n \n #define ICMPV6_ROUTER_PREF_LOW\t\t0x3\n--- a/include/net/ndisc.h\n+++ b/include/net/ndisc.h\n@@ -93,7 +93,7 @@ struct ra_msg {\n         struct icmp6hdr\t\ticmph;\n \t__be32\t\t\treachable_time;\n \t__be32\t\t\tretrans_timer;\n-};\n+} __attribute__((packed, aligned(2)));\n \n struct rd_msg {\n \tstruct icmp6hdr icmph;\n@@ -372,10 +372,10 @@ static inline u32 ndisc_hashfn(const voi\n {\n \tconst u32 *p32 = pkey;\n \n-\treturn (((p32[0] ^ hash32_ptr(dev)) * hash_rnd[0]) +\n-\t\t(p32[1] * hash_rnd[1]) +\n-\t\t(p32[2] * hash_rnd[2]) +\n-\t\t(p32[3] * hash_rnd[3]));\n+\treturn (((net_hdr_word(&p32[0]) ^ hash32_ptr(dev)) * hash_rnd[0]) +\n+\t\t(net_hdr_word(&p32[1]) * hash_rnd[1]) +\n+\t\t(net_hdr_word(&p32[2]) * hash_rnd[2]) +\n+\t\t(net_hdr_word(&p32[3]) * hash_rnd[3]));\n }\n \n static inline struct neighbour *__ipv6_neigh_lookup_noref(struct net_device *dev, const void *pkey)\n--- a/net/sched/cls_u32.c\n+++ b/net/sched/cls_u32.c\n@@ -155,7 +155,7 @@ next_knode:\n \t\t\tdata = skb_header_pointer(skb, toff, 4, &hdata);\n \t\t\tif (!data)\n \t\t\t\tgoto out;\n-\t\t\tif ((*data ^ key->val) & key->mask) {\n+\t\t\tif ((net_hdr_word(data) ^ key->val) & key->mask) {\n \t\t\t\tn = rcu_dereference_bh(n->next);\n \t\t\t\tgoto next_knode;\n \t\t\t}\n@@ -206,8 +206,8 @@ check_terminal:\n \t\t\t\t\t\t  &hdata);\n \t\t\tif (!data)\n \t\t\t\tgoto out;\n-\t\t\tsel = ht->divisor & u32_hash_fold(*data, &n->sel,\n-\t\t\t\t\t\t\t  n->fshift);\n+\t\t\tsel = ht->divisor & u32_hash_fold(net_hdr_word(data),\n+\t\t\t\t\t\t\t  &n->sel, n->fshift);\n \t\t}\n \t\tif (!(n->sel.flags & (TC_U32_VAROFFSET | TC_U32_OFFSET | TC_U32_EAT)))\n \t\t\tgoto next_ht;\n--- a/net/ipv6/ip6_offload.c\n+++ b/net/ipv6/ip6_offload.c\n@@ -241,7 +241,7 @@ INDIRECT_CALLABLE_SCOPE struct sk_buff *\n \t\t\tcontinue;\n \n \t\tiph2 = (struct ipv6hdr *)(p->data + off);\n-\t\tfirst_word = *(__be32 *)iph ^ *(__be32 *)iph2;\n+\t\tfirst_word = net_hdr_word(iph) ^ net_hdr_word(iph2);\n \n \t\t/* All fields must match except length and Traffic Class.\n \t\t * XXX skbs on the gro_list have all been parsed and pulled\n--- a/include/net/addrconf.h\n+++ b/include/net/addrconf.h\n@@ -47,7 +47,7 @@ struct prefix_info {\n \t__be32\t\t\treserved2;\n \n \tstruct in6_addr\t\tprefix;\n-};\n+} __attribute__((packed, aligned(2)));\n \n #include <linux/ipv6.h>\n #include <linux/netdevice.h>\n--- a/include/net/inet_ecn.h\n+++ b/include/net/inet_ecn.h\n@@ -138,9 +138,9 @@ static inline int IP6_ECN_set_ce(struct\n \tif (INET_ECN_is_not_ect(ipv6_get_dsfield(iph)))\n \t\treturn 0;\n \n-\tfrom = *(__be32 *)iph;\n+\tfrom = net_hdr_word(iph);\n \tto = from | htonl(INET_ECN_CE << 20);\n-\t*(__be32 *)iph = to;\n+\tnet_hdr_word(iph) = to;\n \tif (skb->ip_summed == CHECKSUM_COMPLETE)\n \t\tskb->csum = csum_add(csum_sub(skb->csum, (__force __wsum)from),\n \t\t\t\t     (__force __wsum)to);\n--- a/include/net/ipv6.h\n+++ b/include/net/ipv6.h\n@@ -147,7 +147,7 @@ struct frag_hdr {\n \t__u8\treserved;\n \t__be16\tfrag_off;\n \t__be32\tidentification;\n-};\n+} __attribute__((packed, aligned(2)));\n \n #define\tIP6_MF\t\t0x0001\n #define\tIP6_OFFSET\t0xFFF8\n@@ -561,8 +561,8 @@ static inline void __ipv6_addr_set_half(\n \t}\n #endif\n #endif\n-\taddr[0] = wh;\n-\taddr[1] = wl;\n+\tnet_hdr_word(&addr[0]) = wh;\n+\tnet_hdr_word(&addr[1]) = wl;\n }\n \n static inline void ipv6_addr_set(struct in6_addr *addr,\n@@ -621,6 +621,8 @@ static inline bool ipv6_prefix_equal(con\n \tconst __be32 *a1 = addr1->s6_addr32;\n \tconst __be32 *a2 = addr2->s6_addr32;\n \tunsigned int pdw, pbi;\n+\t/* Used for last <32-bit fraction of prefix */\n+\tu32 pbia1, pbia2;\n \n \t/* check complete u32 in prefix */\n \tpdw = prefixlen >> 5;\n@@ -629,7 +631,9 @@ static inline bool ipv6_prefix_equal(con\n \n \t/* check incomplete u32 in prefix */\n \tpbi = prefixlen & 0x1f;\n-\tif (pbi && ((a1[pdw] ^ a2[pdw]) & htonl((0xffffffff) << (32 - pbi))))\n+\tpbia1 = net_hdr_word(&a1[pdw]);\n+\tpbia2 = net_hdr_word(&a2[pdw]);\n+\tif (pbi && ((pbia1 ^ pbia2) & htonl((0xffffffff) << (32 - pbi))))\n \t\treturn false;\n \n \treturn true;\n@@ -750,13 +754,13 @@ static inline void ipv6_addr_set_v4mappe\n  */\n static inline int __ipv6_addr_diff32(const void *token1, const void *token2, int addrlen)\n {\n-\tconst __be32 *a1 = token1, *a2 = token2;\n+\tconst struct in6_addr *a1 = token1, *a2 = token2;\n \tint i;\n \n \taddrlen >>= 2;\n \n \tfor (i = 0; i < addrlen; i++) {\n-\t\t__be32 xb = a1[i] ^ a2[i];\n+\t\t__be32 xb = a1->s6_addr32[i] ^ a2->s6_addr32[i];\n \t\tif (xb)\n \t\t\treturn i * 32 + 31 - __fls(ntohl(xb));\n \t}\n@@ -950,17 +954,18 @@ static inline u32 ip6_multipath_hash_fie\n static inline void ip6_flow_hdr(struct ipv6hdr *hdr, unsigned int tclass,\n \t\t\t\t__be32 flowlabel)\n {\n-\t*(__be32 *)hdr = htonl(0x60000000 | (tclass << 20)) | flowlabel;\n+\tnet_hdr_word((__be32 *)hdr) =\n+\t\thtonl(0x60000000 | (tclass << 20)) | flowlabel;\n }\n \n static inline __be32 ip6_flowinfo(const struct ipv6hdr *hdr)\n {\n-\treturn *(__be32 *)hdr & IPV6_FLOWINFO_MASK;\n+\treturn net_hdr_word((__be32 *)hdr) & IPV6_FLOWINFO_MASK;\n }\n \n static inline __be32 ip6_flowlabel(const struct ipv6hdr *hdr)\n {\n-\treturn *(__be32 *)hdr & IPV6_FLOWLABEL_MASK;\n+\treturn net_hdr_word((__be32 *)hdr) & IPV6_FLOWLABEL_MASK;\n }\n \n static inline u8 ip6_tclass(__be32 flowinfo)\n--- a/include/net/secure_seq.h\n+++ b/include/net/secure_seq.h\n@@ -3,6 +3,7 @@\n #define _NET_SECURE_SEQ\n \n #include <linux/types.h>\n+#include <linux/in6.h>\n \n u32 secure_ipv4_port_ephemeral(__be32 saddr, __be32 daddr, __be16 dport);\n u32 secure_ipv6_port_ephemeral(const __be32 *saddr, const __be32 *daddr,\n--- a/include/uapi/linux/in.h\n+++ b/include/uapi/linux/in.h\n@@ -88,7 +88,7 @@ enum {\n /* Internet address. */\n struct in_addr {\n \t__be32\ts_addr;\n-};\n+} __attribute__((packed, aligned(2)));\n #endif\n \n #define IP_TOS\t\t1\n--- a/net/ipv6/ip6_fib.c\n+++ b/net/ipv6/ip6_fib.c\n@@ -141,7 +141,7 @@ static __be32 addr_bit_set(const void *t\n \t * See include/asm-generic/bitops/le.h.\n \t */\n \treturn (__force __be32)(1 << ((~fn_bit ^ BITOP_BE32_SWIZZLE) & 0x1f)) &\n-\t       addr[fn_bit >> 5];\n+\t       net_hdr_word(&addr[fn_bit >> 5]);\n }\n \n struct fib6_info *fib6_info_alloc(gfp_t gfp_flags, bool with_fib6_nh)\n--- a/net/netfilter/nf_conntrack_proto_tcp.c\n+++ b/net/netfilter/nf_conntrack_proto_tcp.c\n@@ -400,7 +400,7 @@ static void tcp_sack(const struct sk_buf\n \n \t/* Fast path for timestamp-only option */\n \tif (length == TCPOLEN_TSTAMP_ALIGNED\n-\t    && *(__be32 *)ptr == htonl((TCPOPT_NOP << 24)\n+\t    && net_hdr_word(ptr) == htonl((TCPOPT_NOP << 24)\n \t\t\t\t       | (TCPOPT_NOP << 16)\n \t\t\t\t       | (TCPOPT_TIMESTAMP << 8)\n \t\t\t\t       | TCPOLEN_TIMESTAMP))\n--- a/net/xfrm/xfrm_input.c\n+++ b/net/xfrm/xfrm_input.c\n@@ -165,8 +165,8 @@ int xfrm_parse_spi(struct sk_buff *skb,\n \tif (!pskb_may_pull(skb, hlen))\n \t\treturn -EINVAL;\n \n-\t*spi = *(__be32 *)(skb_transport_header(skb) + offset);\n-\t*seq = *(__be32 *)(skb_transport_header(skb) + offset_seq);\n+\t*spi = net_hdr_word(skb_transport_header(skb) + offset);\n+\t*seq = net_hdr_word(skb_transport_header(skb) + offset_seq);\n \treturn 0;\n }\n EXPORT_SYMBOL(xfrm_parse_spi);\n--- a/net/ipv4/tcp_input.c\n+++ b/net/ipv4/tcp_input.c\n@@ -4130,14 +4130,16 @@ static bool tcp_parse_aligned_timestamp(\n {\n \tconst __be32 *ptr = (const __be32 *)(th + 1);\n \n-\tif (*ptr == htonl((TCPOPT_NOP << 24) | (TCPOPT_NOP << 16)\n-\t\t\t  | (TCPOPT_TIMESTAMP << 8) | TCPOLEN_TIMESTAMP)) {\n+\tif (net_hdr_word(ptr) ==\n+\t    htonl((TCPOPT_NOP << 24) | (TCPOPT_NOP << 16) |\n+\t\t  (TCPOPT_TIMESTAMP << 8) | TCPOLEN_TIMESTAMP)) {\n \t\ttp->rx_opt.saw_tstamp = 1;\n \t\t++ptr;\n-\t\ttp->rx_opt.rcv_tsval = ntohl(*ptr);\n+\t\ttp->rx_opt.rcv_tsval = get_unaligned_be32(ptr);\n \t\t++ptr;\n-\t\tif (*ptr)\n-\t\t\ttp->rx_opt.rcv_tsecr = ntohl(*ptr) - tp->tsoffset;\n+\t\tif (net_hdr_word(ptr))\n+\t\t\ttp->rx_opt.rcv_tsecr = get_unaligned_be32(ptr) -\n+\t\t\t\t\t       tp->tsoffset;\n \t\telse\n \t\t\ttp->rx_opt.rcv_tsecr = 0;\n \t\treturn true;\n--- a/include/uapi/linux/if_pppox.h\n+++ b/include/uapi/linux/if_pppox.h\n@@ -51,6 +51,7 @@ struct pppoe_addr {\n  */\n struct pptp_addr {\n \t__u16\t\tcall_id;\n+\t__u16\t\tpad;\n \tstruct in_addr\tsin_addr;\n };\n \n--- a/include/net/neighbour.h\n+++ b/include/net/neighbour.h\n@@ -275,8 +275,10 @@ static inline bool neigh_key_eq128(const\n \tconst u32 *n32 = (const u32 *)n->primary_key;\n \tconst u32 *p32 = pkey;\n \n-\treturn ((n32[0] ^ p32[0]) | (n32[1] ^ p32[1]) |\n-\t\t(n32[2] ^ p32[2]) | (n32[3] ^ p32[3])) == 0;\n+\treturn ((n32[0] ^ net_hdr_word(&p32[0])) |\n+\t\t(n32[1] ^ net_hdr_word(&p32[1])) |\n+\t\t(n32[2] ^ net_hdr_word(&p32[2])) |\n+\t\t(n32[3] ^ net_hdr_word(&p32[3]))) == 0;\n }\n \n static inline struct neighbour *___neigh_lookup_noref(\n--- a/include/uapi/linux/netfilter_arp/arp_tables.h\n+++ b/include/uapi/linux/netfilter_arp/arp_tables.h\n@@ -70,7 +70,7 @@ struct arpt_arp {\n \t__u8 flags;\n \t/* Inverse flags */\n \t__u16 invflags;\n-};\n+} __attribute__((aligned(4)));\n \n /* Values for \"flag\" field in struct arpt_ip (general arp structure).\n  * No flags defined yet.\n--- a/net/core/utils.c\n+++ b/net/core/utils.c\n@@ -460,8 +460,14 @@ void inet_proto_csum_replace16(__sum16 *\n \t\t\t       bool pseudohdr)\n {\n \t__be32 diff[] = {\n-\t\t~from[0], ~from[1], ~from[2], ~from[3],\n-\t\tto[0], to[1], to[2], to[3],\n+\t\t~net_hdr_word(&from[0]),\n+\t\t~net_hdr_word(&from[1]),\n+\t\t~net_hdr_word(&from[2]),\n+\t\t~net_hdr_word(&from[3]),\n+\t\tnet_hdr_word(&to[0]),\n+\t\tnet_hdr_word(&to[1]),\n+\t\tnet_hdr_word(&to[2]),\n+\t\tnet_hdr_word(&to[3]),\n \t};\n \tif (skb->ip_summed != CHECKSUM_PARTIAL) {\n \t\t*sum = csum_fold(csum_partial(diff, sizeof(diff),\n--- a/include/linux/etherdevice.h\n+++ b/include/linux/etherdevice.h\n@@ -511,7 +511,7 @@ static inline bool is_etherdev_addr(cons\n  * @b: Pointer to Ethernet header\n  *\n  * Compare two Ethernet headers, returns 0 if equal.\n- * This assumes that the network header (i.e., IP header) is 4-byte\n+ * This assumes that the network header (i.e., IP header) is 2-byte\n  * aligned OR the platform can handle unaligned access.  This is the\n  * case for all packets coming into netif_receive_skb or similar\n  * entry points.\n@@ -534,11 +534,12 @@ static inline unsigned long compare_ethe\n \tfold |= *(unsigned long *)(a + 6) ^ *(unsigned long *)(b + 6);\n \treturn fold;\n #else\n-\tu32 *a32 = (u32 *)((u8 *)a + 2);\n-\tu32 *b32 = (u32 *)((u8 *)b + 2);\n+\tconst u16 *a16 = a;\n+\tconst u16 *b16 = b;\n \n-\treturn (*(u16 *)a ^ *(u16 *)b) | (a32[0] ^ b32[0]) |\n-\t       (a32[1] ^ b32[1]) | (a32[2] ^ b32[2]);\n+\treturn (a16[0] ^ b16[0]) | (a16[1] ^ b16[1]) | (a16[2] ^ b16[2]) |\n+\t       (a16[3] ^ b16[3]) | (a16[4] ^ b16[4]) | (a16[5] ^ b16[5]) |\n+\t       (a16[6] ^ b16[6]);\n #endif\n }\n \n--- a/net/ipv4/tcp_offload.c\n+++ b/net/ipv4/tcp_offload.c\n@@ -223,7 +223,7 @@ struct sk_buff *tcp_gro_receive(struct l\n \n \t\tth2 = tcp_hdr(p);\n \n-\t\tif (*(u32 *)&th->source ^ *(u32 *)&th2->source) {\n+\t\tif (net_hdr_word(&th->source) ^ net_hdr_word(&th2->source)) {\n \t\t\tNAPI_GRO_CB(p)->same_flow = 0;\n \t\t\tcontinue;\n \t\t}\n@@ -241,8 +241,8 @@ found:\n \t\t  ~(TCP_FLAG_CWR | TCP_FLAG_FIN | TCP_FLAG_PSH));\n \tflush |= (__force int)(th->ack_seq ^ th2->ack_seq);\n \tfor (i = sizeof(*th); i < thlen; i += 4)\n-\t\tflush |= *(u32 *)((u8 *)th + i) ^\n-\t\t\t *(u32 *)((u8 *)th2 + i);\n+\t\tflush |= net_hdr_word((u8 *)th + i) ^\n+\t\t\t net_hdr_word((u8 *)th2 + i);\n \n \t/* When we receive our second frame we can made a decision on if we\n \t * continue this flow as an atomic flow with a fixed ID or if we use\n--- a/net/ipv6/netfilter/ip6table_mangle.c\n+++ b/net/ipv6/netfilter/ip6table_mangle.c\n@@ -44,7 +44,7 @@ ip6t_mangle_out(struct sk_buff *skb, con\n \thop_limit = ipv6_hdr(skb)->hop_limit;\n \n \t/* flowlabel and prio (includes version, which shouldn't change either */\n-\tflowlabel = *((u_int32_t *)ipv6_hdr(skb));\n+\tflowlabel = net_hdr_word(ipv6_hdr(skb));\n \n \tret = ip6t_do_table(skb, state, priv);\n \n@@ -53,7 +53,7 @@ ip6t_mangle_out(struct sk_buff *skb, con\n \t     !ipv6_addr_equal(&ipv6_hdr(skb)->daddr, &daddr) ||\n \t     skb->mark != mark ||\n \t     ipv6_hdr(skb)->hop_limit != hop_limit ||\n-\t     flowlabel != *((u_int32_t *)ipv6_hdr(skb)))) {\n+\t     flowlabel != net_hdr_word(ipv6_hdr(skb)))) {\n \t\terr = ip6_route_me_harder(state->net, state->sk, skb);\n \t\tif (err < 0)\n \t\t\tret = NF_DROP_ERR(err);\n"
  },
  {
    "path": "target/linux/ath79/patches-5.15/920-mikrotik-rb4xx.patch",
    "content": "--- a/drivers/mfd/Kconfig\n+++ b/drivers/mfd/Kconfig\n@@ -2174,6 +2174,14 @@ config RAVE_SP_CORE\n \t  Select this to get support for the Supervisory Processor\n \t  device found on several devices in RAVE line of hardware.\n \n+config MFD_RB4XX_CPLD\n+\ttristate \"CPLD driver for Mikrotik RB4xx series boards\"\n+\tselect MFD_CORE\n+\tdepends on ATH79 || COMPILE_TEST\n+\thelp\n+\t  Enables support for the CPLD chip (NAND & GPIO) on Mikrotik\n+\t  Routerboard RB4xx series.\n+\n config SGI_MFD_IOC3\n \tbool \"SGI IOC3 core driver\"\n \tdepends on PCI && MIPS && 64BIT\n--- a/drivers/mfd/Makefile\n+++ b/drivers/mfd/Makefile\n@@ -267,6 +267,7 @@ obj-$(CONFIG_MFD_KHADAS_MCU) \t+= khadas-\n obj-$(CONFIG_MFD_ACER_A500_EC)\t+= acer-ec-a500.o\n obj-$(CONFIG_MFD_QCOM_PM8008)\t+= qcom-pm8008.o\n \n+obj-$(CONFIG_MFD_RB4XX_CPLD)\t+= rb4xx-cpld.o\n obj-$(CONFIG_SGI_MFD_IOC3)\t+= ioc3.o\n obj-$(CONFIG_MFD_SIMPLE_MFD_I2C)\t+= simple-mfd-i2c.o\n obj-$(CONFIG_MFD_INTEL_M10_BMC)   += intel-m10-bmc.o\n--- a/drivers/gpio/Kconfig\n+++ b/drivers/gpio/Kconfig\n@@ -1574,6 +1574,12 @@ config GPIO_SODAVILLE\n \thelp\n \t  Say Y here to support Intel Sodaville GPIO.\n \n+config GPIO_RB4XX\n+\ttristate \"GPIO expander for Mikrotik RB4xx series boards\"\n+\tdepends on MFD_RB4XX_CPLD\n+\thelp\n+\t  GPIO driver for Mikrotik Routerboard RB4xx series.\n+\n endmenu\n \n menu \"SPI GPIO expanders\"\n--- a/drivers/gpio/Makefile\n+++ b/drivers/gpio/Makefile\n@@ -122,6 +122,7 @@ obj-$(CONFIG_GPIO_PL061)\t\t+= gpio-pl061.\n obj-$(CONFIG_GPIO_PMIC_EIC_SPRD)\t+= gpio-pmic-eic-sprd.o\n obj-$(CONFIG_GPIO_PXA)\t\t\t+= gpio-pxa.o\n obj-$(CONFIG_GPIO_RASPBERRYPI_EXP)\t+= gpio-raspberrypi-exp.o\n+obj-$(CONFIG_GPIO_RB4XX)\t\t+= gpio-rb4xx.o\n obj-$(CONFIG_GPIO_RC5T583)\t\t+= gpio-rc5t583.o\n obj-$(CONFIG_GPIO_RCAR)\t\t\t+= gpio-rcar.o\n obj-$(CONFIG_GPIO_RDA)\t\t\t+= gpio-rda.o\n--- a/drivers/mtd/nand/raw/Kconfig\n+++ b/drivers/mtd/nand/raw/Kconfig\n@@ -563,4 +563,11 @@ config MTD_NAND_AR934X\n \t  Enables support for NAND controller on Qualcomm Atheros SoCs.\n \t  This controller is found on AR934x and QCA955x SoCs.\n \n+config MTD_NAND_RB4XX\n+\ttristate \"Support for NAND driver for Mikrotik RB4xx series boards\"\n+\tdepends on MFD_RB4XX_CPLD\n+\thelp\n+\t  Enables support for the NAND flash chip on Mikrotik Routerboard\n+\t  RB4xx series.\n+\n endif # MTD_RAW_NAND\n--- a/drivers/mtd/nand/raw/Makefile\n+++ b/drivers/mtd/nand/raw/Makefile\n@@ -59,6 +59,7 @@ obj-$(CONFIG_MTD_NAND_INTEL_LGM)\t+= inte\n obj-$(CONFIG_MTD_NAND_ROCKCHIP)\t\t+= rockchip-nand-controller.o\n obj-$(CONFIG_MTD_NAND_PL35X)\t\t+= pl35x-nand-controller.o\n obj-$(CONFIG_MTD_NAND_AR934X)\t\t+= ar934x_nand.o\n+obj-$(CONFIG_MTD_NAND_RB4XX)\t\t+= nand_rb4xx.o\n \n nand-objs := nand_base.o nand_legacy.o nand_bbt.o nand_timings.o nand_ids.o\n nand-objs += nand_onfi.o\n"
  },
  {
    "path": "target/linux/ath79/patches-5.15/930-ar8216-make-reg-access-atomic.patch",
    "content": "From b3797d1a92afe97c173b00fdb7824cedba24eef0 Mon Sep 17 00:00:00 2001\nFrom: Chuanhong Guo <gch981213@gmail.com>\nDate: Sun, 20 Sep 2020 01:00:45 +0800\nSubject: [PATCH] ath79: ar8216: make switch register access atomic\n\ndue to some unknown reason these register accesses sometimes fail\non the integrated switch without this patch.\n\nTHIS ONLY WORKS ON ATH79 AND MAY BREAK THE DRIVER ON OTHER PLATFORMS!\nThe mdio bus on ath79 works in polling mode and doesn't rely on\nany interrupt. This patch breaks the driver on any mdio master\nwith interrupts used.\n\n---\n--- a/drivers/net/phy/ar8216.c\n+++ b/drivers/net/phy/ar8216.c\n@@ -252,6 +252,7 @@ ar8xxx_mii_write32(struct ar8xxx_priv *p\n u32\n ar8xxx_read(struct ar8xxx_priv *priv, int reg)\n {\n+\tunsigned long flags;\n \tstruct mii_bus *bus = priv->mii_bus;\n \tu16 r1, r2, page;\n \tu32 val;\n@@ -259,11 +260,13 @@ ar8xxx_read(struct ar8xxx_priv *priv, in\n \tsplit_addr((u32) reg, &r1, &r2, &page);\n \n \tmutex_lock(&bus->mdio_lock);\n+\tlocal_irq_save(flags);\n \n \tbus->write(bus, 0x18, 0, page);\n \twait_for_page_switch();\n \tval = ar8xxx_mii_read32(priv, 0x10 | r2, r1);\n \n+\tlocal_irq_restore(flags);\n \tmutex_unlock(&bus->mdio_lock);\n \n \treturn val;\n@@ -272,17 +275,20 @@ ar8xxx_read(struct ar8xxx_priv *priv, in\n void\n ar8xxx_write(struct ar8xxx_priv *priv, int reg, u32 val)\n {\n+\tunsigned long flags;\n \tstruct mii_bus *bus = priv->mii_bus;\n \tu16 r1, r2, page;\n \n \tsplit_addr((u32) reg, &r1, &r2, &page);\n \n \tmutex_lock(&bus->mdio_lock);\n+\tlocal_irq_save(flags);\n \n \tbus->write(bus, 0x18, 0, page);\n \twait_for_page_switch();\n \tar8xxx_mii_write32(priv, 0x10 | r2, r1, val);\n \n+\tlocal_irq_restore(flags);\n \tmutex_unlock(&bus->mdio_lock);\n }\n \n"
  },
  {
    "path": "target/linux/ath79/patches-5.15/939-mikrotik-rb91x.patch",
    "content": "--- a/drivers/gpio/Kconfig\n+++ b/drivers/gpio/Kconfig\n@@ -353,6 +353,13 @@ config GPIO_IXP4XX\n \t  IXP4xx series of chips.\n \n \t  If unsure, say N.\n+\n+config GPIO_LATCH\n+\ttristate \"MikroTik RouterBOARD GPIO latch support\"\n+\tdepends on ATH79\n+\thelp\n+\t  GPIO driver for latch on some MikroTik RouterBOARDs.\n+\n config GPIO_LOGICVC\n \ttristate \"Xylon LogiCVC GPIO support\"\n \tdepends on MFD_SYSCON && OF\n@@ -529,6 +536,10 @@ config GPIO_ROCKCHIP\n \thelp\n \t  Say yes here to support GPIO on Rockchip SoCs.\n \n+config GPIO_RB91X_KEY\n+\ttristate \"MikroTik RB91x board series reset key support\"\n+\tdepends on ATH79\n+\n config GPIO_SAMA5D2_PIOBU\n \ttristate \"SAMA5D2 PIOBU GPIO support\"\n \tdepends on MFD_SYSCON\n--- a/drivers/gpio/Makefile\n+++ b/drivers/gpio/Makefile\n@@ -75,6 +75,7 @@ obj-$(CONFIG_GPIO_IT87)\t\t\t+= gpio-it87.o\n obj-$(CONFIG_GPIO_IXP4XX)\t\t+= gpio-ixp4xx.o\n obj-$(CONFIG_GPIO_JANZ_TTL)\t\t+= gpio-janz-ttl.o\n obj-$(CONFIG_GPIO_KEMPLD)\t\t+= gpio-kempld.o\n+obj-$(CONFIG_GPIO_LATCH)\t\t+= gpio-latch.o\n obj-$(CONFIG_GPIO_LOGICVC)\t\t+= gpio-logicvc.o\n obj-$(CONFIG_GPIO_LOONGSON1)\t\t+= gpio-loongson1.o\n obj-$(CONFIG_GPIO_LOONGSON)\t\t+= gpio-loongson.o\n@@ -123,6 +124,7 @@ obj-$(CONFIG_GPIO_PMIC_EIC_SPRD)\t+= gpio\n obj-$(CONFIG_GPIO_PXA)\t\t\t+= gpio-pxa.o\n obj-$(CONFIG_GPIO_RASPBERRYPI_EXP)\t+= gpio-raspberrypi-exp.o\n obj-$(CONFIG_GPIO_RB4XX)\t\t+= gpio-rb4xx.o\n+obj-$(CONFIG_GPIO_RB91X_KEY)\t\t+= gpio-rb91x-key.o\n obj-$(CONFIG_GPIO_RC5T583)\t\t+= gpio-rc5t583.o\n obj-$(CONFIG_GPIO_RCAR)\t\t\t+= gpio-rcar.o\n obj-$(CONFIG_GPIO_RDA)\t\t\t+= gpio-rda.o\n--- a/drivers/mtd/nand/raw/Kconfig\n+++ b/drivers/mtd/nand/raw/Kconfig\n@@ -570,4 +570,10 @@ config MTD_NAND_RB4XX\n \t  Enables support for the NAND flash chip on Mikrotik Routerboard\n \t  RB4xx series.\n \n+config MTD_NAND_RB91X\n+\ttristate \"MikroTik RB91x NAND driver support\"\n+\tdepends on ATH79 && MTD_RAW_NAND\n+\thelp\n+\t  Enables support for the NAND flash chip on MikroTik RB91x series.\n+\n endif # MTD_RAW_NAND\n--- a/drivers/mtd/nand/raw/Makefile\n+++ b/drivers/mtd/nand/raw/Makefile\n@@ -60,6 +60,7 @@ obj-$(CONFIG_MTD_NAND_ROCKCHIP)\t\t+= rock\n obj-$(CONFIG_MTD_NAND_PL35X)\t\t+= pl35x-nand-controller.o\n obj-$(CONFIG_MTD_NAND_AR934X)\t\t+= ar934x_nand.o\n obj-$(CONFIG_MTD_NAND_RB4XX)\t\t+= nand_rb4xx.o\n+obj-$(CONFIG_MTD_NAND_RB91X)\t\t+= rb91x_nand.o\n \n nand-objs := nand_base.o nand_legacy.o nand_bbt.o nand_timings.o nand_ids.o\n nand-objs += nand_onfi.o\n"
  },
  {
    "path": "target/linux/ath79/patches-5.15/940-ath79-add-support-for-booting-QCN550x.patch",
    "content": "From: Wenli Looi <wlooi@ucalgary.ca>\nDate: Sun, 20 Jun 2021 23:32:28 -0700\nSubject: [PATCH] ath79: add support for booting QCN550x\n\nBased on wikidevi, QCN550x is a \"Dragonfly\" like QCA9561 and QCA9563.\nTreating it as QCA956x seems to work.\nTested on Netgear EX7300v2 which boots successfully with\nthe same CPU clock as the stock firmware.\n\nLink: https://wikidevi.wi-cat.ru/Qualcomm#bgn\nLink: https://wikidevi.wi-cat.ru/Qualcomm_Atheros#.28a.29bgn_2\nSigned-off-by: Wenli Looi <wlooi@ucalgary.ca>\n\n--- a/arch/mips/ath79/early_printk.c\n+++ b/arch/mips/ath79/early_printk.c\n@@ -121,6 +121,7 @@ static void prom_putchar_init(void)\n \tcase REV_ID_MAJOR_QCA9558:\n \tcase REV_ID_MAJOR_TP9343:\n \tcase REV_ID_MAJOR_QCA956X:\n+\tcase REV_ID_MAJOR_QCN550X:\n \t\t_prom_putchar = prom_putchar_ar71xx;\n \t\tbreak;\n \n--- a/arch/mips/ath79/setup.c\n+++ b/arch/mips/ath79/setup.c\n@@ -168,6 +168,12 @@ static void __init ath79_detect_sys_type\n \t\trev = id & QCA956X_REV_ID_REVISION_MASK;\n \t\tbreak;\n \n+\tcase REV_ID_MAJOR_QCN550X:\n+\t\tath79_soc = ATH79_SOC_QCA956X;\n+\t\tchip = \"550X\";\n+\t\trev = id & QCA956X_REV_ID_REVISION_MASK;\n+\t\tbreak;\n+\n \tcase REV_ID_MAJOR_TP9343:\n \t\tath79_soc = ATH79_SOC_TP9343;\n \t\tchip = \"9343\";\n--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h\n+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h\n@@ -867,6 +867,7 @@\n #define REV_ID_MAJOR_QCA9558\t\t0x1130\n #define REV_ID_MAJOR_TP9343\t\t0x0150\n #define REV_ID_MAJOR_QCA956X\t\t0x1150\n+#define REV_ID_MAJOR_QCN550X\t\t0x2170\n \n #define AR71XX_REV_ID_MINOR_MASK\t0x3\n #define AR71XX_REV_ID_MINOR_AR7130\t0x0\n"
  },
  {
    "path": "target/linux/ath79/tiny/base-files/etc/board.d/01_leds",
    "content": "\n. /lib/functions/uci-defaults.sh\n\nboard_config_update\n\nboard=$(board_name)\n\ncase \"$board\" in\nbuffalo,whr-g301n|\\\ndlink,dir-615-e4|\\\ntplink,tl-wr740n-v1|\\\ntplink,tl-wr740n-v3|\\\ntplink,tl-wr741-v1|\\\ntplink,tl-wr743nd-v1|\\\ntplink,tl-wr841-v5|\\\ntplink,tl-wr941-v4)\n\tucidef_set_led_netdev \"wan\" \"WAN\" \"green:wan\" \"eth0\"\n\tucidef_set_led_switch \"lan1\" \"LAN1\" \"green:lan1\" \"switch0\" \"0x02\"\n\tucidef_set_led_switch \"lan2\" \"LAN2\" \"green:lan2\" \"switch0\" \"0x04\"\n\tucidef_set_led_switch \"lan3\" \"LAN3\" \"green:lan3\" \"switch0\" \"0x08\"\n\tucidef_set_led_switch \"lan4\" \"LAN4\" \"green:lan4\" \"switch0\" \"0x10\"\n\t;;\nengenius,enh202-v1)\n\tucidef_set_led_switch \"lan\" \"LAN\" \"amber:lan\" \"switch0\" \"0x10\"\n\tucidef_set_led_netdev \"wan\" \"WAN\" \"green:wan\" \"eth0\"\n\tucidef_set_rssimon \"wlan0\" \"200000\" \"1\"\n\tucidef_set_led_rssi \"rssilow\" \"RSSILOW\" \"red:rssilow\" \"wlan0\" \"1\"  \"100\"\n\tucidef_set_led_rssi \"rssimedium\" \"RSSIMEDIUM\" \"amber:rssimedium\" \"wlan0\" \"33\" \"100\"\n\tucidef_set_led_rssi \"rssihigh\" \"RSSIHIGH\" \"green:rssihigh\" \"wlan0\" \"67\" \"100\"\n\t;;\nnetgear,wnr1000-v2|\\\nnetgear,wnr2000-v3)\n\tucidef_set_led_netdev \"wan-amber\" \"WAN (amber)\" \"amber:wan\" \"eth0\"\n\tucidef_set_led_switch \"lan1green\" \"LAN1 (green)\" \"green:lan1\" \"switch0\" \"0x02\" \"0x04\"\n\tucidef_set_led_switch \"lan2green\" \"LAN2 (green)\" \"green:lan2\" \"switch0\" \"0x04\" \"0x04\"\n\tucidef_set_led_switch \"lan3green\" \"LAN3 (green)\" \"green:lan3\" \"switch0\" \"0x08\" \"0x04\"\n\tucidef_set_led_switch \"lan4green\" \"LAN4 (green)\" \"green:lan4\" \"switch0\" \"0x10\" \"0x04\"\n\tucidef_set_led_switch \"lan1amber\" \"LAN1 (amber)\" \"amber:lan1\" \"switch0\" \"0x02\" \"0x02\"\n\tucidef_set_led_switch \"lan2amber\" \"LAN2 (amber)\" \"amber:lan2\" \"switch0\" \"0x04\" \"0x02\"\n\tucidef_set_led_switch \"lan3amber\" \"LAN3 (amber)\" \"amber:lan3\" \"switch0\" \"0x08\" \"0x02\"\n\tucidef_set_led_switch \"lan4amber\" \"LAN4 (amber)\" \"amber:lan4\" \"switch0\" \"0x10\" \"0x02\"\n\t;;\nnetgear,wnr612-v2|\\\non,n150r)\n\tucidef_set_led_netdev \"wan\" \"WAN\" \"green:wan\" \"eth0\"\n\tucidef_set_led_switch \"lan1\" \"LAN1\" \"green:lan1\" \"switch0\" \"0x02\" \"0x0f\"\n\tucidef_set_led_switch \"lan2\" \"LAN2\" \"green:lan2\" \"switch0\" \"0x04\" \"0x0f\"\n\t;;\ntplink,tl-mr3020-v1|\\\ntplink,tl-mr3040-v2|\\\ntplink,tl-wa701nd-v1|\\\ntplink,tl-wa730re-v1|\\\ntplink,tl-wa801nd-v1|\\\ntplink,tl-wa801nd-v3|\\\ntplink,tl-wa801nd-v4|\\\ntplink,tl-wa830re-v1|\\\ntplink,tl-wa860re-v1|\\\ntplink,tl-wa901nd-v1|\\\ntplink,tl-wa901nd-v3|\\\ntplink,tl-wa901nd-v4|\\\ntplink,tl-wa901nd-v5)\n\tucidef_set_led_netdev \"lan\" \"LAN\" \"green:lan\" \"eth0\"\n\t;;\ntplink,tl-mr3420-v2|\\\ntplink,tl-wr740n-v4|\\\ntplink,tl-wr740n-v5|\\\ntplink,tl-wr741nd-v4|\\\ntplink,tl-wr841-v8)\n\tucidef_set_led_netdev \"wan\" \"WAN\" \"green:wan\" \"eth1\"\n\tucidef_set_led_switch \"lan1\" \"LAN1\" \"green:lan1\" \"switch0\" \"0x04\"\n\tucidef_set_led_switch \"lan2\" \"LAN2\" \"green:lan2\" \"switch0\" \"0x08\"\n\tucidef_set_led_switch \"lan3\" \"LAN3\" \"green:lan3\" \"switch0\" \"0x10\"\n\tucidef_set_led_switch \"lan4\" \"LAN4\" \"green:lan4\" \"switch0\" \"0x02\"\n\t;;\ntplink,tl-mr3420-v3|\\\ntplink,tl-wr841-v9|\\\ntplink,tl-wr841-v10|\\\ntplink,tl-wr841-v11|\\\ntplink,tl-wr841-v12)\n\tucidef_set_led_netdev \"wan\" \"WAN\" \"green:wan\" \"eth1\"\n\tucidef_set_led_switch \"lan1\" \"LAN1\" \"green:lan1\" \"switch0\" \"0x10\"\n\tucidef_set_led_switch \"lan2\" \"LAN2\" \"green:lan2\" \"switch0\" \"0x08\"\n\tucidef_set_led_switch \"lan3\" \"LAN3\" \"green:lan3\" \"switch0\" \"0x04\"\n\tucidef_set_led_switch \"lan4\" \"LAN4\" \"green:lan4\" \"switch0\" \"0x02\"\n\t;;\ntplink,tl-wa850re-v1|\\\ntplink,tl-wa850re-v2)\n\tucidef_set_led_netdev \"lan\" \"LAN\" \"blue:lan\" \"eth0\"\n\tucidef_set_rssimon \"wlan0\" \"200000\" \"1\"\n\tucidef_set_led_rssi \"rssilow\" \"RSSILOW\" \"blue:signal1\" \"wlan0\" \"1\" \"100\"\n\tucidef_set_led_rssi \"rssimediumlow\" \"RSSIMEDIUMLOW\" \"blue:signal2\" \"wlan0\" \"20\" \"100\"\n\tucidef_set_led_rssi \"rssimedium\" \"RSSIMEDIUM\" \"blue:signal3\" \"wlan0\" \"40\" \"100\"\n\tucidef_set_led_rssi \"rssimediumhigh\" \"RSSIMEDIUMHIGH\" \"blue:signal4\" \"wlan0\" \"60\" \"100\"\n\tucidef_set_led_rssi \"rssihigh\" \"RSSIHIGH\" \"blue:signal5\" \"wlan0\" \"80\" \"100\"\n\t;;\ntplink,tl-wpa8630p-v2-int|\\\ntplink,tl-wpa8630p-v2.0-eu|\\\ntplink,tl-wpa8630p-v2.1-eu)\n\tucidef_set_led_switch \"lan\" \"LAN\" \"green:lan\" \"switch0\" \"0x3c\"\n\t;;\ntplink,tl-wr940n-v3|\\\ntplink,tl-wr940n-v4|\\\ntplink,tl-wr941nd-v6)\n\tucidef_set_led_netdev \"wan\" \"WAN\" \"blue:wan\" \"eth1\"\n\tucidef_set_led_switch \"lan1\" \"LAN1\" \"blue:lan1\" \"switch0\" \"0x10\"\n\tucidef_set_led_switch \"lan2\" \"LAN2\" \"blue:lan2\" \"switch0\" \"0x08\"\n\tucidef_set_led_switch \"lan3\" \"LAN3\" \"blue:lan3\" \"switch0\" \"0x04\"\n\tucidef_set_led_switch \"lan4\" \"LAN4\" \"blue:lan4\" \"switch0\" \"0x02\"\n\t;;\ntplink,tl-wr940n-v6)\n\tucidef_set_led_netdev \"wan\" \"WAN\" \"blue:wan\" \"eth1\"\n\t;;\nesac\n\nboard_config_flush\n\nexit 0\n"
  },
  {
    "path": "target/linux/ath79/tiny/base-files/etc/board.d/02_network",
    "content": "\n. /lib/functions/system.sh\n. /lib/functions/uci-defaults.sh\n\nath79_setup_interfaces()\n{\n\tlocal board=\"$1\"\n\n\tcase \"$board\" in\n\tbuffalo,whr-g301n)\n\t\tucidef_set_interface_wan \"eth0\"\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0@eth1\" \"1:lan:4\" \"2:lan:3\" \"3:lan:2\" \"4:lan:1\"\n\t\t;;\n\tdlink,dir-615-e4|\\\n\tnetgear,wnr1000-v2|\\\n\tnetgear,wnr2000-v3|\\\n\tnetgear,wnr612-v2|\\\n\ton,n150r|\\\n\ttplink,tl-wr740n-v1|\\\n\ttplink,tl-wr740n-v3|\\\n\ttplink,tl-wr741-v1|\\\n\ttplink,tl-wr743nd-v1|\\\n\ttplink,tl-wr841-v5|\\\n\ttplink,tl-wr941-v4)\n\t\tucidef_set_interface_wan \"eth0\"\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0@eth1\" \"1:lan\" \"2:lan\" \"3:lan\" \"4:lan\"\n\t\t;;\n\tengenius,eap350-v1|\\\n\tengenius,ecb350-v1|\\\n\tpqi,air-pen|\\\n\ttplink,tl-mr10u|\\\n\ttplink,tl-mr3020-v1|\\\n\ttplink,tl-mr3040-v2|\\\n\ttplink,tl-wa701nd-v1|\\\n\ttplink,tl-wa730re-v1|\\\n\ttplink,tl-wa801nd-v1|\\\n\ttplink,tl-wa801nd-v3|\\\n\ttplink,tl-wa801nd-v4|\\\n\ttplink,tl-wa830re-v1|\\\n\ttplink,tl-wa850re-v1|\\\n\ttplink,tl-wa850re-v2|\\\n\ttplink,tl-wa860re-v1|\\\n\ttplink,tl-wa901nd-v1|\\\n\ttplink,tl-wa901nd-v2|\\\n\ttplink,tl-wa901nd-v3|\\\n\ttplink,tl-wa901nd-v4|\\\n\ttplink,tl-wa901nd-v5|\\\n\ttplink,tl-wr703n|\\\n\ttplink,tl-wr802n-v1|\\\n\ttplink,tl-wr802n-v2)\n\t\tucidef_set_interface_lan \"eth0\"\n\t\t;;\n\tengenius,enh202-v1)\n\t\tucidef_set_interface_lan \"eth0\"\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0@eth1\" \"4:lan:1\"\n\t\t;;\n\ttplink,tl-mr3220-v1|\\\n\ttplink,tl-mr3420-v1|\\\n\ttplink,tl-mr3420-v3|\\\n\ttplink,tl-wr841-v7|\\\n\ttplink,tl-wr841-v9|\\\n\ttplink,tl-wr841-v10|\\\n\ttplink,tl-wr841-v11|\\\n\ttplink,tl-wr841-v12|\\\n\ttplink,tl-wr940n-v3|\\\n\ttplink,tl-wr940n-v4|\\\n\ttplink,tl-wr940n-v6|\\\n\ttplink,tl-wr941nd-v6)\n\t\tucidef_set_interface_wan \"eth1\"\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0@eth0\" \"1:lan:4\" \"2:lan:3\" \"3:lan:2\" \"4:lan:1\"\n\t\t;;\n\ttplink,tl-mr3420-v2|\\\n\ttplink,tl-wr740n-v4|\\\n\ttplink,tl-wr740n-v5|\\\n\ttplink,tl-wr741nd-v4|\\\n\ttplink,tl-wr841-v8)\n\t\tucidef_set_interface_wan \"eth1\"\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0@eth0\" \"1:lan:4\" \"2:lan:1\" \"3:lan:2\" \"4:lan:3\"\n\t\t;;\n\ttplink,tl-wpa8630p-v2-int|\\\n\ttplink,tl-wpa8630p-v2.0-eu|\\\n\ttplink,tl-wpa8630p-v2.1-eu)\n\t\t# port 5 (internal) is the power-line port\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0@eth0\" \"2:lan:3\" \"3:lan:2\" \"4:lan:1\" \"5:lan:4\"\n\t\t;;\n\ttplink,tl-wr941-v2)\n\t\tucidef_set_interfaces_lan_wan \"lan1 lan2 lan3 lan4\" \"wan\"\n\t\t;;\n\ttplink,tl-wr941n-v7-cn)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0@eth0\" \"2:lan:1\" \"3:lan:2\" \"4:lan:3\" \"5:lan:4\" \"1:wan\"\n\t\t;;\n\t*)\n\t\tucidef_set_interfaces_lan_wan \"eth0\" \"eth1\"\n\t\t;;\n\tesac\n}\n\nath79_setup_macs()\n{\n\tlocal board=\"$1\"\n\n\tcase \"$board\" in\n\tdlink,dir-615-e4)\n\t\tlan_mac=$(mtd_get_mac_ascii \"nvram\" \"lan_mac\")\n\t\twan_mac=$(mtd_get_mac_ascii \"nvram\" \"wan_mac\")\n\t\tlabel_mac=$wan_mac\n\t\t;;\n\tengenius,enh202-v1)\n\t\tlabel_mac=$(cat /sys/class/ieee80211/phy0/macaddress)\n\t\t;;\n\ttplink,tl-wr941-v2|\\\n\ttplink,tl-wr941n-v7-cn)\n\t\tbase_mac=$(mtd_get_mac_binary u-boot 0x1fc00)\n\t\twan_mac=$(macaddr_add \"$base_mac\" 1)\n\t\t;;\n\tesac\n\n\t[ -n \"$lan_mac\" ] && ucidef_set_interface_macaddr \"lan\" $lan_mac\n\t[ -n \"$wan_mac\" ] && ucidef_set_interface_macaddr \"wan\" $wan_mac\n\t[ -n \"$label_mac\" ] && ucidef_set_label_macaddr $label_mac\n}\n\nboard_config_update\nboard=$(board_name)\nath79_setup_interfaces $board\nath79_setup_macs $board\nboard_config_flush\n\nexit 0\n"
  },
  {
    "path": "target/linux/ath79/tiny/base-files/etc/board.d/05_compat-version",
    "content": "#\n# Copyright (C) 2020 OpenWrt.org\n#\n\n. /lib/functions.sh\n. /lib/functions/uci-defaults.sh\n\nboard_config_update\n\ncase \"$(board_name)\" in\n\ttplink,tl-wpa8630p-v2-int|\\\n\ttplink,tl-wpa8630p-v2.0-eu|\\\n\ttplink,tl-wpa8630p-v2.1-eu)\n\t\tucidef_set_compat_version \"2.0\"\n\t\t;;\nesac\n\nboard_config_flush\n\nexit 0\n"
  },
  {
    "path": "target/linux/ath79/tiny/base-files/etc/hotplug.d/firmware/10-ath9k-eeprom",
    "content": "#!/bin/sh\n\n[ -e /lib/firmware/$FIRMWARE ] && exit 0\n\n. /lib/functions/caldata.sh\n\nboard=$(board_name)\n\ncase \"$FIRMWARE\" in\n\"ath9k-eeprom-pci-0000:00:00.0.bin\")\n\tcase $board in\n\tbuffalo,whr-g301n|\\\n\tengenius,eap350-v1|\\\n\tengenius,ecb350-v1|\\\n\tengenius,enh202-v1|\\\n\ttplink,tl-wa701nd-v1|\\\n\ttplink,tl-wa730re-v1|\\\n\ttplink,tl-wa801nd-v1|\\\n\ttplink,tl-wa830re-v1|\\\n\ttplink,tl-wa901nd-v1|\\\n\ttplink,tl-wr841-v5|\\\n\ttplink,tl-wr941-v4)\n\t\tcaldata_extract \"art\" 0x1000 0xeb8\n\t\t;;\n\tdlink,dir-615-e4)\n\t\tcaldata_extract \"art\" 0x1000 0x1000\n\t\tath9k_patch_mac_crc $(mtd_get_mac_ascii \"nvram\" \"lan_mac\") 0x10c\n\t\t;;\n\tnetgear,wnr1000-v2|\\\n\tnetgear,wnr2000-v3|\\\n\tnetgear,wnr612-v2|\\\n\ton,n150r|\\\n\ttplink,tl-mr3220-v1|\\\n\ttplink,tl-mr3420-v1|\\\n\ttplink,tl-wr740n-v1|\\\n\ttplink,tl-wr740n-v3|\\\n\ttplink,tl-wr741-v1|\\\n\ttplink,tl-wr743nd-v1|\\\n\ttplink,tl-wr841-v7)\n\t\tcaldata_extract \"art\" 0x1000 0x1000\n\t\t;;\n\tpqi,air-pen)\n\t\tcaldata_extract \"art\" 0x1000 0x7d2\n\t\t;;\n\t*)\n\t\tcaldata_die \"board $board is not supported yet\"\n\t\t;;\n\tesac\n\t;;\nesac\n"
  },
  {
    "path": "target/linux/ath79/tiny/base-files/etc/hotplug.d/firmware/11-ath10k-caldata",
    "content": "#!/bin/sh\n\n[ -e /lib/firmware/$FIRMWARE ] && exit 0\n\n. /lib/functions/caldata.sh\n\nboard=$(board_name)\n\ncase \"$FIRMWARE\" in\n\"ath10k/pre-cal-pci-0000:00:00.0.bin\")\n\tcase $board in\n\ttplink,tl-wpa8630p-v2-int|\\\n\ttplink,tl-wpa8630p-v2.0-eu|\\\n\ttplink,tl-wpa8630p-v2.1-eu)\n\t\tcaldata_extract \"art\" 0x5000 0x2f20\n\t\tath10k_patch_mac $(macaddr_add $(mtd_get_mac_binary info 0x8) 1)\n\t\tln -sf /lib/firmware/ath10k/pre-cal-pci-0000\\:00\\:00.0.bin \\\n\t\t\t/lib/firmware/ath10k/QCA9888/hw2.0/board.bin\n\t\t;;\n\tesac\n\t;;\n*)\n\texit 1\n\t;;\nesac\n"
  },
  {
    "path": "target/linux/ath79/tiny/base-files/etc/uci-defaults/04_led_migration",
    "content": ". /lib/functions.sh\n. /lib/functions/migrations.sh\n\nboard=$(board_name)\n\ncase \"$board\" in\ntplink,tl-wr802n-v1)\n\tmigrate_leds \"blue:=green:\"\n\t;;\nesac\n\nremove_devicename_leds\n\nmigrations_apply system\n\nexit 0\n"
  },
  {
    "path": "target/linux/ath79/tiny/base-files/lib/upgrade/failsafe_datachk.sh",
    "content": "# U-Boot with the datachk patchset requires image sizes, offsets,\n# and checksums to be provided in the U-Boot environment.\n# This script is based on the dualboot version for devices that come with 2 OS partitions.\n# For Senao boards with a \"failsafe\" partition image, the process is almost the same.\n# Instead of booting a secondary instalation on checksum failure,\n# the failsafe image is booted instead.\n# These boards also use the OKLI lzma kernel loader and mtd-concat\n# So the kernel check is for the loader, the rootfs check is for kernel + rootfs\n\nplatform_do_upgrade_failsafe_datachk() {\n\tlocal setenv_script=\"/tmp/fw_env_upgrade\"\n\n\tlocal flash_base=0x9f000000\n\n\tlocal kernel_mtd=$(find_mtd_index ${KERNEL_PART:-kernel})\n\tlocal rootfs_mtd=$(find_mtd_index ${ROOTFS_PART:-rootfs})\n\n\tlocal kernel_offset=$(cat /sys/class/mtd/mtd${kernel_mtd}/offset)\n\tlocal rootfs_offset=$(cat /sys/class/mtd/mtd${rootfs_mtd}/offset)\n\n\tif [ -n \"$IMAGE_LIST\" ]; then\n\t\tKERNEL_FILE=$($IMAGE_LIST | grep $KERNEL_FILE)\n\t\tROOTFS_FILE=$($IMAGE_LIST | grep $ROOTFS_FILE)\n\tfi\n\n\tlocal kernel_size=$($IMAGE_CMD $KERNEL_FILE | wc -c)\n\tlocal rootfs_size=$($IMAGE_CMD $ROOTFS_FILE | wc -c)\n\n\t# rootfs without JFFS2\n\tlocal rootfs_blocks=$((rootfs_size / 4096))\n\trootfs_size=$((rootfs_blocks * 4096))\n\n\tlocal kernel_md5=$($IMAGE_CMD $KERNEL_FILE | md5sum | cut -d ' ' -f1)\n\tlocal rootfs_md5=$($IMAGE_CMD $ROOTFS_FILE | dd bs=4k count=$rootfs_blocks iflag=fullblock | md5sum | cut -d ' ' -f1)\n\n\t# prepare new u-boot-env vars\n\tprintf \"vmlinux_start_addr 0x%08x\\n\" $((flash_base + kernel_offset)) >> $setenv_script\n\tprintf \"vmlinux_size 0x%08x\\n\" ${kernel_size} >> $setenv_script\n\tprintf \"vmlinux_checksum %s\\n\" ${kernel_md5} >> $setenv_script\n\n\tprintf \"rootfs_start_addr 0x%08x\\n\" $((flash_base + rootfs_offset)) >> $setenv_script\n\tprintf \"rootfs_size 0x%08x\\n\" ${rootfs_size} >> $setenv_script\n\tprintf \"rootfs_checksum %s\\n\" ${rootfs_md5} >> $setenv_script\n\n\t# store u-boot-env\n\tmkdir -p /var/lock\n\tfw_setenv -s $setenv_script || {\n\t\techo 'failed to update U-Boot environment'\n\t\texit 1\n\t}\n\n\t# sysupgrade\n\tsleep 2\n\tsync\n\techo 3 > /proc/sys/vm/drop_caches\n\t$IMAGE_CMD $KERNEL_FILE | mtd $MTD_ARGS write - ${KERNEL_PART:-kernel}\n\tsleep 2\n\tsync\n\tif [ -n \"$UPGRADE_BACKUP\" ]; then\n\t\t$IMAGE_CMD $ROOTFS_FILE | mtd $MTD_ARGS $MTD_CONFIG_ARGS -j $UPGRADE_BACKUP write - ${ROOTFS_PART:-rootfs}\n\telse\n\t\t$IMAGE_CMD $ROOTFS_FILE | mtd $MTD_ARGS write - ${ROOTFS_PART:-rootfs}\n\tfi\n}\n"
  },
  {
    "path": "target/linux/ath79/tiny/base-files/lib/upgrade/platform.sh",
    "content": "#\n# Copyright (C) 2011 OpenWrt.org\n#\n\nPART_NAME=firmware\nREQUIRE_IMAGE_METADATA=1\n\nRAMFS_COPY_BIN='fw_setenv'\nRAMFS_COPY_DATA='/etc/fw_env.config'\n\nplatform_check_image() {\n\treturn 0\n}\n\nplatform_do_upgrade() {\n\tlocal board=$(board_name)\n\n\tcase \"$board\" in\n\tengenius,eap350-v1|\\\n\tengenius,ecb350-v1|\\\n\tengenius,enh202-v1)\n\t\tIMAGE_LIST=\"tar tzf $1\"\n\t\tIMAGE_CMD=\"tar xzOf $1\"\n\t\tKERNEL_PART=\"loader\"\n\t\tROOTFS_PART=\"fwconcat0\"\n\t\tKERNEL_FILE=\"uImage-lzma.bin\"\n\t\tROOTFS_FILE=\"root.squashfs\"\n\t\tplatform_do_upgrade_failsafe_datachk \"$1\"\n\t\t;;\n\t*)\n\t\tdefault_do_upgrade \"$1\"\n\t\t;;\n\tesac\n}\n"
  },
  {
    "path": "target/linux/ath79/tiny/config-default",
    "content": "CONFIG_LEDS_RESET=y\nCONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y\nCONFIG_NET_DEVLINK=y\nCONFIG_NET_DSA=y\nCONFIG_NET_DSA_MV88E6060=y\n# CONFIG_NET_DSA_TAG_QCA is not set\nCONFIG_NET_DSA_TAG_TRAILER=y\nCONFIG_NET_SWITCHDEV=y\nCONFIG_PHYLINK=y\nCONFIG_PHY_AR7100_USB=y\nCONFIG_PHY_AR7200_USB=y\nCONFIG_REGULATOR_FIXED_VOLTAGE=y\n"
  },
  {
    "path": "target/linux/ath79/tiny/target.mk",
    "content": "BOARDNAME:=Devices with small flash\nFEATURES += small_flash\n\nDEFAULT_PACKAGES += wpad-basic-wolfssl\n\ndefine Target/Description\n\tBuild firmware images for Atheros AR71xx/AR913x/AR934x based boards with small flash\nendef\n"
  },
  {
    "path": "target/linux/bcm27xx/Makefile",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2012-2020 OpenWrt.org\n# Copyright (C) 2017 LEDE project\n\ninclude $(TOPDIR)/rules.mk\n\nARCH:=arm\nBOARD:=bcm27xx\nBOARDNAME:=Broadcom BCM27xx\nFEATURES:=audio boot-part display ext4 fpu gpio rootfs-part rtc squashfs usb usbgadget\nSUBTARGETS:=bcm2708 bcm2709 bcm2710 bcm2711\n\nKERNEL_PATCHVER=5.10\n\ndefine Target/Description\n\tBuild firmware image for Broadcom BCM27xx SoC devices.\n\tCurrently produces SD Card image for Raspberry Pi.\nendef\n\ninclude $(INCLUDE_DIR)/target.mk\n\nDEFAULT_PACKAGES := $(filter-out urngd,$(DEFAULT_PACKAGES))\nDEFAULT_PACKAGES += \\\n\tbcm27xx-gpu-fw \\\n\tkmod-usb-hid \\\n\tkmod-sound-core kmod-sound-arm-bcm2835 \\\n\tkmod-fs-vfat kmod-nls-cp437 kmod-nls-iso8859-1 \\\n\tpartx-utils mkf2fs e2fsprogs\n\nKERNELNAME:=Image dtbs\n\n$(eval $(call BuildTarget))\n"
  },
  {
    "path": "target/linux/bcm27xx/base-files/etc/board.d/02_network",
    "content": "# Copyright (C) 2014-2016 OpenWrt.org\n# Copyright (C) 2017 LEDE project\n\n. /lib/functions/uci-defaults.sh\n. /lib/functions.sh\n. /lib/functions/system.sh\n\nboard_config_update\n\nboard=$(board_name)\n\ncase \"$board\" in\nraspberrypi,model-b |\\\nraspberrypi,model-b-plus |\\\nraspberrypi,model-b-rev2 |\\\nraspberrypi,2-model-b |\\\nraspberrypi,2-model-b-rev2 |\\\nraspberrypi,3-model-b |\\\nraspberrypi,3-model-b-plus |\\\nraspberrypi,400 |\\\nraspberrypi,4-compute-module |\\\nraspberrypi,4-model-b)\n\tucidef_set_interface_lan \"eth0\"\n\t;;\n\nraspberrypi,model-zero-w)\n\tucidef_set_interface_lan \"wlan0\"\n\t;;\nesac\n\nboard_config_flush\n\nexit 0\n"
  },
  {
    "path": "target/linux/bcm27xx/base-files/etc/diag.sh",
    "content": "#!/bin/sh\n# Copyright (C) 2015-2016 OpenWrt.org\n# Copyright (C) 2017 LEDE project\n\n. /lib/functions.sh\n. /lib/functions/leds.sh\n\nset_state() {\n\tcase \"$(board_name)\" in\n\traspberrypi,2-model-b |\\\n\traspberrypi,2-model-b-rev2 |\\\n\traspberrypi,3-model-b |\\\n\traspberrypi,3-model-b-plus |\\\n\traspberrypi,400 |\\\n\traspberrypi,4-compute-module |\\\n\traspberrypi,4-model-b |\\\n\traspberrypi,model-b-plus)\n\t\tstatus_led=\"led1\"\n\t\t;;\n\traspberrypi,3-compute-module |\\\n\traspberrypi,model-b |\\\n\traspberrypi,model-zero |\\\n\traspberrypi,model-zero-w)\n\t\tstatus_led=\"led0\"\n\t\t;;\n\tesac\n\n\tcase \"$1\" in\n\tpreinit)\n\t\tstatus_led_blink_preinit\n\t\t;;\n\tfailsafe)\n\t\tstatus_led_blink_failsafe\n\t\t;;\n\tpreinit_regular)\n\t\tstatus_led_blink_preinit_regular\n\t\t;;\n\tdone)\n\t\tstatus_led_on\n\t\t;;\n\tesac\n}\n"
  },
  {
    "path": "target/linux/bcm27xx/base-files/etc/inittab",
    "content": "::sysinit:/etc/init.d/rcS S boot\n::shutdown:/etc/init.d/rcS K shutdown\n::askconsole:/usr/libexec/login.sh\ntty1::askfirst:/usr/libexec/login.sh\n"
  },
  {
    "path": "target/linux/bcm27xx/base-files/lib/preinit/05_set_preinit_iface_brcm2708",
    "content": "# Copyright (C) 2015-2016 OpenWrt.org\n# Copyright (C) 2017 LEDE project\n\nset_preinit_iface() {\n\t. /lib/functions.sh\n\n\tcase \"$(board_name)\" in\n\traspberrypi,2-model-b |\\\n\traspberrypi,2-model-b-rev2 |\\\n\traspberrypi,3-model-b |\\\n\traspberrypi,3-model-b-plus |\\\n\traspberrypi,4-model-b |\\\n\traspberrypi,model-b |\\\n\traspberrypi,model-b-plus |\\\n\traspberrypi,model-b-rev2)\n\t\tifname=eth0\n\t\t;;\n\tesac\n}\n\nboot_hook_add preinit_main set_preinit_iface\n"
  },
  {
    "path": "target/linux/bcm27xx/base-files/lib/preinit/79_move_config",
    "content": "# Copyright (C) 2015 OpenWrt.org\n\n. /lib/upgrade/common.sh\n\nBOOTPART=/dev/mmcblk0p1\n\nmove_config() {\n\tif [ -b $BOOTPART ]; then\n\t\tinsmod nls_cp437\n\t\tinsmod nls_iso8859-1\n\t\tinsmod fat\n\t\tinsmod vfat\n\t\tmkdir -p /boot\n\t\tmount -t vfat -o rw,noatime $BOOTPART /boot\n\t\t[ -f \"/boot/$BACKUP_FILE\" ] && mv -f \"/boot/$BACKUP_FILE\" /\n\tfi\n}\n\nboot_hook_add preinit_mount_root move_config\n"
  },
  {
    "path": "target/linux/bcm27xx/base-files/lib/upgrade/keep.d/platform",
    "content": "/boot/cmdline.txt\n/boot/config.txt\n"
  },
  {
    "path": "target/linux/bcm27xx/base-files/lib/upgrade/platform.sh",
    "content": ". /lib/functions.sh\n\nREQUIRE_IMAGE_METADATA=1\n\n# copied from x86's platform.sh\n\nplatform_check_image() {\n\tlocal diskdev partdev diff\n\n\t[ \"$#\" -gt 1 ] && return 1\n\n\texport_bootdevice && export_partdevice diskdev 0 || {\n\t\techo \"Unable to determine upgrade device\"\n\t\treturn 1\n\t}\n\n\tget_partitions \"/dev/$diskdev\" bootdisk\n\n\t#extract the boot sector from the image\n\tget_image \"$@\" | dd of=/tmp/image.bs count=1 bs=512b 2>/dev/null\n\n\tget_partitions /tmp/image.bs image\n\n\t#compare tables\n\tdiff=\"$(grep -F -x -v -f /tmp/partmap.bootdisk /tmp/partmap.image)\"\n\n\trm -f /tmp/image.bs /tmp/partmap.bootdisk /tmp/partmap.image\n\n\tif [ -n \"$diff\" ]; then\n\t\techo \"Partition layout has changed. Full image will be written.\"\n\t\task_bool 0 \"Abort\" && exit 1\n\t\treturn 0\n\tfi\n\n\treturn 0;\n}\n\nplatform_do_upgrade() {\n\tlocal diskdev partdev diff\n\n\texport_bootdevice && export_partdevice diskdev 0 || {\n\t\techo \"Unable to determine upgrade device\"\n\t\treturn 1\n\t}\n\n\tsync\n\n\tif [ \"$UPGRADE_OPT_SAVE_PARTITIONS\" = \"1\" ]; then\n\t\tget_partitions \"/dev/$diskdev\" bootdisk\n\n\t\t#extract the boot sector from the image\n\t\tget_image \"$@\" | dd of=/tmp/image.bs count=1 bs=512b\n\n\t\tget_partitions /tmp/image.bs image\n\n\t\t#compare tables\n\t\tdiff=\"$(grep -F -x -v -f /tmp/partmap.bootdisk /tmp/partmap.image)\"\n\telse\n\t\tdiff=1\n\tfi\n\n\tif [ -n \"$diff\" ]; then\n\t\tget_image \"$@\" | dd of=\"/dev/$diskdev\" bs=2M conv=fsync\n\n\t\t# Separate removal and addtion is necessary; otherwise, partition 1\n\t\t# will be missing if it overlaps with the old partition 2\n\t\tpartx -d - \"/dev/$diskdev\"\n\t\tpartx -a - \"/dev/$diskdev\"\n\n\t\treturn 0\n\tfi\n\n\t#iterate over each partition from the image and write it to the boot disk\n\twhile read part start size; do\n\t\tif export_partdevice partdev $part; then\n\t\t\techo \"Writing image to /dev/$partdev...\"\n\t\t\tget_image \"$@\" | dd of=\"/dev/$partdev\" ibs=\"512\" obs=1M skip=\"$start\" count=\"$size\" conv=fsync\n\t\telse\n\t\t\techo \"Unable to find partition $part device, skipped.\"\n\tfi\n\tdone < /tmp/partmap.image\n\n\t#copy partition uuid\n\techo \"Writing new UUID to /dev/$diskdev...\"\n\tget_image \"$@\" | dd of=\"/dev/$diskdev\" bs=1 skip=440 count=4 seek=440 conv=fsync\n}\n\nplatform_copy_config() {\n\tlocal partdev\n\n\tif export_partdevice partdev 1; then\n\t\tmkdir -p /boot\n\t\t[ -f /boot/kernel.img ] || mount -t vfat -o rw,noatime \"/dev/$partdev\" /boot\n\t\tcp -af \"$UPGRADE_BACKUP\" \"/boot/$BACKUP_FILE\"\n\t\ttar -C / -zxvf \"$UPGRADE_BACKUP\" boot/cmdline.txt boot/config.txt\n\t\tsync\n\t\tumount /boot\n\tfi\n}\n"
  },
  {
    "path": "target/linux/bcm27xx/bcm2708/config-5.10",
    "content": "# CONFIG_AIO is not set\nCONFIG_ALIGNMENT_TRAP=y\nCONFIG_ARCH_32BIT_OFF_T=y\nCONFIG_ARCH_BCM=y\nCONFIG_ARCH_BCM2835=y\nCONFIG_ARCH_HIBERNATION_POSSIBLE=y\nCONFIG_ARCH_KEEP_MEMBLOCK=y\nCONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y\nCONFIG_ARCH_MULTIPLATFORM=y\nCONFIG_ARCH_MULTI_V6=y\nCONFIG_ARCH_MULTI_V6_V7=y\nCONFIG_ARCH_NR_GPIO=0\nCONFIG_ARCH_OPTIONAL_KERNEL_RWX=y\nCONFIG_ARCH_SELECT_MEMORY_MODEL=y\nCONFIG_ARCH_SPARSEMEM_ENABLE=y\nCONFIG_ARCH_SUSPEND_POSSIBLE=y\nCONFIG_ARM=y\nCONFIG_ARM_AMBA=y\nCONFIG_ARM_CPU_SUSPEND=y\nCONFIG_ARM_ERRATA_411920=y\nCONFIG_ARM_HAS_SG_CHAIN=y\nCONFIG_ARM_L1_CACHE_SHIFT=5\nCONFIG_ARM_PATCH_PHYS_VIRT=y\nCONFIG_ARM_RASPBERRYPI_CPUFREQ=y\nCONFIG_ARM_THUMB=y\nCONFIG_ARM_TIMER_SP804=y\nCONFIG_ARM_UNWIND=y\nCONFIG_AUTO_ZRELADDR=y\nCONFIG_BCM2708_VCMEM=y\n# CONFIG_BCM2711_THERMAL is not set\nCONFIG_BCM2835_DEVGPIOMEM=y\nCONFIG_BCM2835_FAST_MEMCPY=y\nCONFIG_BCM2835_MBOX=y\nCONFIG_BCM2835_POWER=y\n# CONFIG_BCM2835_SMI is not set\nCONFIG_BCM2835_THERMAL=y\nCONFIG_BCM2835_TIMER=y\nCONFIG_BCM2835_VCHIQ=y\n# CONFIG_BCM2835_VCHIQ_MMAL is not set\nCONFIG_BCM2835_WDT=y\nCONFIG_BCM_VCIO=y\n# CONFIG_BCM_VC_SM_CMA is not set\nCONFIG_BCM_VIDEOCORE=y\nCONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y\n# CONFIG_BLK_DEV_INITRD is not set\nCONFIG_BLK_DEV_LOOP=y\nCONFIG_BLK_DEV_RAM=y\nCONFIG_BLK_DEV_RAM_COUNT=16\nCONFIG_BLK_DEV_RAM_SIZE=4096\nCONFIG_BLK_DEV_SD=y\nCONFIG_BLK_PM=y\nCONFIG_BLK_SCSI_REQUEST=y\nCONFIG_BRCMSTB_L2_IRQ=y\nCONFIG_BRCM_CHAR_DRIVERS=y\n# CONFIG_CACHE_L2X0 is not set\nCONFIG_CLKDEV_LOOKUP=y\nCONFIG_CLKSRC_MMIO=y\nCONFIG_CLK_BCM2711_DVP=y\nCONFIG_CLK_BCM2835=y\nCONFIG_CLK_RASPBERRYPI=y\nCONFIG_CLONE_BACKWARDS=y\nCONFIG_CMA=y\nCONFIG_CMA_ALIGNMENT=8\nCONFIG_CMA_AREAS=7\n# CONFIG_CMA_DEBUG is not set\n# CONFIG_CMA_DEBUGFS is not set\nCONFIG_CMA_SIZE_MBYTES=5\n# CONFIG_CMA_SIZE_SEL_MAX is not set\nCONFIG_CMA_SIZE_SEL_MBYTES=y\n# CONFIG_CMA_SIZE_SEL_MIN is not set\n# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set\nCONFIG_COMMON_CLK=y\nCONFIG_COMPAT_32BIT_TIME=y\nCONFIG_CONFIGFS_FS=y\nCONFIG_CONSOLE_TRANSLATIONS=y\nCONFIG_CONTIG_ALLOC=y\nCONFIG_CPUFREQ_DT=y\nCONFIG_CPUFREQ_DT_PLATDEV=y\nCONFIG_CPU_32v6=y\nCONFIG_CPU_32v6K=y\nCONFIG_CPU_ABRT_EV6=y\nCONFIG_CPU_CACHE_V6=y\nCONFIG_CPU_CACHE_VIPT=y\nCONFIG_CPU_COPY_V6=y\nCONFIG_CPU_CP15=y\nCONFIG_CPU_CP15_MMU=y\nCONFIG_CPU_FREQ=y\nCONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y\n# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set\nCONFIG_CPU_FREQ_GOV_ATTR_SET=y\nCONFIG_CPU_FREQ_GOV_COMMON=y\nCONFIG_CPU_FREQ_GOV_CONSERVATIVE=y\nCONFIG_CPU_FREQ_GOV_ONDEMAND=y\nCONFIG_CPU_FREQ_GOV_PERFORMANCE=y\nCONFIG_CPU_FREQ_GOV_POWERSAVE=y\nCONFIG_CPU_FREQ_GOV_USERSPACE=y\nCONFIG_CPU_FREQ_STAT=y\nCONFIG_CPU_HAS_ASID=y\nCONFIG_CPU_IDLE=y\nCONFIG_CPU_IDLE_GOV_LADDER=y\nCONFIG_CPU_IDLE_GOV_MENU=y\nCONFIG_CPU_PABRT_V6=y\nCONFIG_CPU_PM=y\nCONFIG_CPU_THUMB_CAPABLE=y\nCONFIG_CPU_TLB_V6=y\nCONFIG_CPU_V6K=y\nCONFIG_CRC16=y\nCONFIG_CRYPTO_CRC32=y\nCONFIG_CRYPTO_CRC32C=y\nCONFIG_CRYPTO_RNG2=y\nCONFIG_DCACHE_WORD_ACCESS=y\nCONFIG_DEBUG_BUGVERBOSE=y\nCONFIG_DEBUG_INFO=y\nCONFIG_DEBUG_LL_INCLUDE=\"mach/debug-macro.S\"\nCONFIG_DMABUF_HEAPS=y\nCONFIG_DMABUF_HEAPS_CMA=y\nCONFIG_DMABUF_HEAPS_SYSTEM=y\nCONFIG_DMADEVICES=y\nCONFIG_DMA_BCM2708=y\nCONFIG_DMA_BCM2835=y\nCONFIG_DMA_CMA=y\nCONFIG_DMA_ENGINE=y\nCONFIG_DMA_OF=y\nCONFIG_DMA_OPS=y\nCONFIG_DMA_REMAP=y\nCONFIG_DMA_SHARED_BUFFER=y\nCONFIG_DMA_VIRTUAL_CHANNELS=y\nCONFIG_DNOTIFY=y\nCONFIG_DTC=y\nCONFIG_DUMMY_CONSOLE=y\nCONFIG_EDAC_ATOMIC_SCRUB=y\nCONFIG_EDAC_SUPPORT=y\nCONFIG_ENABLE_MUST_CHECK=y\nCONFIG_EXT4_FS=y\nCONFIG_EXT4_FS_POSIX_ACL=y\nCONFIG_EXT4_FS_SECURITY=y\nCONFIG_F2FS_FS=y\nCONFIG_FB=y\nCONFIG_FB_BCM2708=y\nCONFIG_FB_CFB_COPYAREA=y\nCONFIG_FB_CFB_FILLRECT=y\nCONFIG_FB_CFB_IMAGEBLIT=y\nCONFIG_FB_CMDLINE=y\n# CONFIG_FB_RPISENSE is not set\nCONFIG_FB_SIMPLE=y\nCONFIG_FIQ=y\nCONFIG_FIXED_PHY=y\nCONFIG_FIX_EARLYCON_MEM=y\nCONFIG_FONT_8x16=y\nCONFIG_FONT_8x8=y\nCONFIG_FONT_SUPPORT=y\n# CONFIG_FPE_FASTFPE is not set\n# CONFIG_FPE_NWFPE is not set\nCONFIG_FRAMEBUFFER_CONSOLE=y\n# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set\nCONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y\nCONFIG_FREEZER=y\nCONFIG_FS_IOMAP=y\nCONFIG_FS_MBCACHE=y\nCONFIG_FS_POSIX_ACL=y\nCONFIG_FW_CACHE=y\nCONFIG_FW_LOADER_PAGED_BUF=y\nCONFIG_GENERIC_ALLOCATOR=y\nCONFIG_GENERIC_BUG=y\nCONFIG_GENERIC_CLOCKEVENTS=y\nCONFIG_GENERIC_CPU_AUTOPROBE=y\nCONFIG_GENERIC_EARLY_IOREMAP=y\nCONFIG_GENERIC_IDLE_POLL_SETUP=y\nCONFIG_GENERIC_IRQ_CHIP=y\nCONFIG_GENERIC_IRQ_MULTI_HANDLER=y\nCONFIG_GENERIC_IRQ_SHOW=y\nCONFIG_GENERIC_IRQ_SHOW_LEVEL=y\nCONFIG_GENERIC_PCI_IOMAP=y\nCONFIG_GENERIC_PINCONF=y\nCONFIG_GENERIC_PINCTRL_GROUPS=y\nCONFIG_GENERIC_PINMUX_FUNCTIONS=y\nCONFIG_GENERIC_SCHED_CLOCK=y\nCONFIG_GENERIC_SMP_IDLE_THREAD=y\nCONFIG_GENERIC_STRNCPY_FROM_USER=y\nCONFIG_GENERIC_STRNLEN_USER=y\nCONFIG_GPIOLIB=y\nCONFIG_GPIOLIB_IRQCHIP=y\n# CONFIG_GPIO_BCM_VIRT is not set\n# CONFIG_GPIO_FSM is not set\nCONFIG_GPIO_RASPBERRYPI_EXP=y\nCONFIG_HANDLE_DOMAIN_IRQ=y\nCONFIG_HARDIRQS_SW_RESEND=y\nCONFIG_HAS_DMA=y\nCONFIG_HAS_IOMEM=y\nCONFIG_HAS_IOPORT_MAP=y\nCONFIG_HW_CONSOLE=y\nCONFIG_HW_RANDOM=y\nCONFIG_HW_RANDOM_BCM2835=y\nCONFIG_HZ_FIXED=0\nCONFIG_I2C=y\n# CONFIG_I2C_BCM2708 is not set\nCONFIG_I2C_BOARDINFO=y\n# CONFIG_I2C_BRCMSTB is not set\nCONFIG_IKCONFIG=y\nCONFIG_IKCONFIG_PROC=y\nCONFIG_INPUT=y\nCONFIG_INPUT_MOUSEDEV=y\n# CONFIG_INPUT_MOUSEDEV_PSAUX is not set\nCONFIG_INPUT_MOUSEDEV_SCREEN_X=1024\nCONFIG_INPUT_MOUSEDEV_SCREEN_Y=768\nCONFIG_IRQCHIP=y\nCONFIG_IRQ_DOMAIN=y\nCONFIG_IRQ_FORCED_THREADING=y\nCONFIG_IRQ_WORK=y\nCONFIG_JBD2=y\nCONFIG_KERNEL_GZIP=y\n# CONFIG_KERNEL_XZ is not set\nCONFIG_LEDS_GPIO=y\nCONFIG_LEDS_TRIGGER_ACTPWR=y\nCONFIG_LEDS_TRIGGER_INPUT=y\nCONFIG_LIBFDT=y\nCONFIG_LOCK_DEBUGGING_SUPPORT=y\nCONFIG_LOGO=y\nCONFIG_LOGO_LINUX_CLUT224=y\n# CONFIG_LOGO_LINUX_MONO is not set\n# CONFIG_LOGO_LINUX_VGA16 is not set\nCONFIG_MAC_PARTITION=y\nCONFIG_MAGIC_SYSRQ=y\nCONFIG_MAILBOX=y\n# CONFIG_MAILBOX_TEST is not set\nCONFIG_MAX_RAW_DEVS=256\nCONFIG_MDIO_BUS=y\nCONFIG_MDIO_DEVICE=y\nCONFIG_MDIO_DEVRES=y\nCONFIG_MEMFD_CREATE=y\nCONFIG_MEMORY_ISOLATION=y\nCONFIG_MFD_CORE=y\n# CONFIG_MFD_RPISENSE_CORE is not set\nCONFIG_MFD_SYSCON=y\nCONFIG_MIGHT_HAVE_CACHE_L2X0=y\nCONFIG_MIGRATION=y\nCONFIG_MMC=y\nCONFIG_MMC_BCM2835=y\nCONFIG_MMC_BCM2835_DMA=y\nCONFIG_MMC_BCM2835_MMC=y\nCONFIG_MMC_BCM2835_PIO_DMA_BARRIER=2\nCONFIG_MMC_BCM2835_SDHOST=y\nCONFIG_MMC_BLOCK=y\nCONFIG_MMC_BLOCK_MINORS=32\nCONFIG_MMC_SDHCI=y\nCONFIG_MMC_SDHCI_PLTFM=y\nCONFIG_MODULES_USE_ELF_REL=y\n# CONFIG_MTD is not set\nCONFIG_NEED_DMA_MAP_STATE=y\nCONFIG_NEED_PER_CPU_KM=y\nCONFIG_NLS=y\nCONFIG_NLS_ASCII=y\nCONFIG_NO_HZ=y\nCONFIG_NO_HZ_COMMON=y\nCONFIG_NO_HZ_IDLE=y\nCONFIG_NVMEM=y\n# CONFIG_NVMEM_RMEM is not set\nCONFIG_OABI_COMPAT=y\nCONFIG_OF=y\nCONFIG_OF_ADDRESS=y\nCONFIG_OF_CONFIGFS=y\nCONFIG_OF_DYNAMIC=y\nCONFIG_OF_EARLY_FLATTREE=y\nCONFIG_OF_FLATTREE=y\nCONFIG_OF_GPIO=y\nCONFIG_OF_IRQ=y\nCONFIG_OF_KOBJ=y\nCONFIG_OF_MDIO=y\nCONFIG_OF_NET=y\nCONFIG_OF_OVERLAY=y\nCONFIG_OF_RESOLVE=y\nCONFIG_OLD_SIGACTION=y\nCONFIG_OLD_SIGSUSPEND3=y\nCONFIG_PAGE_OFFSET=0xC0000000\nCONFIG_PERF_USE_VMALLOC=y\nCONFIG_PGTABLE_LEVELS=2\nCONFIG_PHYLIB=y\nCONFIG_PINCTRL=y\nCONFIG_PINCTRL_BCM2835=y\nCONFIG_PM=y\nCONFIG_PM_CLK=y\nCONFIG_PM_GENERIC_DOMAINS=y\nCONFIG_PM_GENERIC_DOMAINS_OF=y\nCONFIG_PM_GENERIC_DOMAINS_SLEEP=y\nCONFIG_PM_OPP=y\nCONFIG_PM_SLEEP=y\nCONFIG_POWER_SUPPLY=y\nCONFIG_PRINTK_TIME=y\nCONFIG_RASPBERRYPI_FIRMWARE=y\nCONFIG_RASPBERRYPI_POWER=y\nCONFIG_RATIONAL=y\n# CONFIG_RAVE_SP_CORE is not set\nCONFIG_RAW_DRIVER=y\nCONFIG_REGMAP=y\nCONFIG_REGMAP_MMIO=y\nCONFIG_REGULATOR=y\nCONFIG_REGULATOR_FIXED_VOLTAGE=y\nCONFIG_RESET_CONTROLLER=y\n# CONFIG_RESET_RASPBERRYPI is not set\nCONFIG_RESET_SIMPLE=y\n# CONFIG_RPIVID_MEM is not set\n# CONFIG_RPI_AXIPERF is not set\n# CONFIG_RPI_POE_POWER is not set\nCONFIG_SCSI=y\n# CONFIG_SCSI_LOWLEVEL is not set\n# CONFIG_SCSI_PROC_FS is not set\nCONFIG_SERIAL_8250_BCM2835AUX=y\n# CONFIG_SERIAL_8250_DMA is not set\nCONFIG_SERIAL_8250_EXTENDED=y\nCONFIG_SERIAL_8250_FSL=y\nCONFIG_SERIAL_8250_NR_UARTS=1\nCONFIG_SERIAL_8250_RUNTIME_UARTS=0\nCONFIG_SERIAL_8250_SHARE_IRQ=y\nCONFIG_SERIAL_AMBA_PL011=y\nCONFIG_SERIAL_AMBA_PL011_CONSOLE=y\nCONFIG_SERIAL_DEV_BUS=y\n# CONFIG_SERIAL_DEV_CTRL_TTYPORT is not set\nCONFIG_SERIAL_MCTRL_GPIO=y\nCONFIG_SERIAL_OF_PLATFORM=y\nCONFIG_SG_POOL=y\nCONFIG_SMSC_PHY=y\n# CONFIG_SND_SOC_AD193X_I2C is not set\n# CONFIG_SND_SOC_AD193X_SPI is not set\nCONFIG_SPARSE_IRQ=y\nCONFIG_SRCU=y\n# CONFIG_STRIP_ASM_SYMS is not set\nCONFIG_SUSPEND=y\nCONFIG_SUSPEND_FREEZER=y\nCONFIG_SWPHY=y\nCONFIG_SYS_SUPPORTS_APM_EMULATION=y\n# CONFIG_TEXTSEARCH is not set\nCONFIG_THERMAL=y\nCONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y\nCONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0\nCONFIG_THERMAL_GOV_STEP_WISE=y\nCONFIG_THERMAL_OF=y\nCONFIG_TICK_CPU_ACCOUNTING=y\nCONFIG_TIMER_OF=y\nCONFIG_TIMER_PROBE=y\nCONFIG_TINY_SRCU=y\nCONFIG_TMPFS_POSIX_ACL=y\nCONFIG_UEVENT_HELPER_PATH=\"\"\n# CONFIG_UID16 is not set\nCONFIG_UNCOMPRESS_INCLUDE=\"debug/uncompress.h\"\nCONFIG_UNWINDER_ARM=y\nCONFIG_USB=y\nCONFIG_USB_ANNOUNCE_NEW_DEVICES=y\nCONFIG_USB_COMMON=y\nCONFIG_USB_DWCOTG=y\nCONFIG_USB_NET_DRIVERS=y\nCONFIG_USB_NET_SMSC95XX=y\nCONFIG_USB_STORAGE=y\nCONFIG_USB_SUPPORT=y\nCONFIG_USB_UAS=y\nCONFIG_USB_USBNET=y\nCONFIG_USE_OF=y\nCONFIG_VFP=y\nCONFIG_VT=y\nCONFIG_VT_CONSOLE=y\nCONFIG_VT_CONSOLE_SLEEP=y\nCONFIG_VT_HW_CONSOLE_BINDING=y\nCONFIG_WATCHDOG_CORE=y\nCONFIG_XZ_DEC_ARM=y\nCONFIG_XZ_DEC_BCJ=y\nCONFIG_ZBOOT_ROM_BSS=0x0\nCONFIG_ZBOOT_ROM_TEXT=0x0\n"
  },
  {
    "path": "target/linux/bcm27xx/bcm2708/target.mk",
    "content": "#\n# Copyright (C) 2015-2019 OpenWrt.org\n#\n\nSUBTARGET:=bcm2708\nBOARDNAME:=BCM2708 boards (32 bit)\nCPU_TYPE:=arm1176jzf-s\nCPU_SUBTYPE:=vfp\n\ndefine Target/Description\n\tBuild firmware image for BCM2708 devices.\n\tThis firmware features a 32 bit kernel.\nendef\n"
  },
  {
    "path": "target/linux/bcm27xx/bcm2709/config-5.10",
    "content": "# CONFIG_AIO is not set\nCONFIG_ALIGNMENT_TRAP=y\nCONFIG_ARCH_32BIT_OFF_T=y\nCONFIG_ARCH_BCM=y\nCONFIG_ARCH_BCM2835=y\n# CONFIG_ARCH_BCM_HR2 is not set\nCONFIG_ARCH_DMA_ADDR_T_64BIT=y\nCONFIG_ARCH_HIBERNATION_POSSIBLE=y\nCONFIG_ARCH_KEEP_MEMBLOCK=y\nCONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y\nCONFIG_ARCH_MULTIPLATFORM=y\nCONFIG_ARCH_MULTI_V6_V7=y\nCONFIG_ARCH_MULTI_V7=y\nCONFIG_ARCH_NR_GPIO=0\nCONFIG_ARCH_OPTIONAL_KERNEL_RWX=y\nCONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y\nCONFIG_ARCH_SELECT_MEMORY_MODEL=y\nCONFIG_ARCH_SPARSEMEM_ENABLE=y\nCONFIG_ARCH_SUSPEND_POSSIBLE=y\nCONFIG_ARM=y\nCONFIG_ARM_AMBA=y\nCONFIG_ARM_ARCH_TIMER=y\nCONFIG_ARM_ARCH_TIMER_EVTSTREAM=y\nCONFIG_ARM_CPU_SUSPEND=y\nCONFIG_ARM_GIC=y\nCONFIG_ARM_HAS_SG_CHAIN=y\nCONFIG_ARM_L1_CACHE_SHIFT=6\nCONFIG_ARM_L1_CACHE_SHIFT_6=y\nCONFIG_ARM_LPAE=y\nCONFIG_ARM_PATCH_IDIV=y\nCONFIG_ARM_PATCH_PHYS_VIRT=y\nCONFIG_ARM_RASPBERRYPI_CPUFREQ=y\nCONFIG_ARM_THUMB=y\nCONFIG_ARM_TIMER_SP804=y\nCONFIG_ARM_UNWIND=y\nCONFIG_ARM_VIRT_EXT=y\nCONFIG_ASSOCIATIVE_ARRAY=y\nCONFIG_AUTO_ZRELADDR=y\nCONFIG_BCM2708_VCMEM=y\nCONFIG_BCM2711_THERMAL=y\nCONFIG_BCM2835_DEVGPIOMEM=y\nCONFIG_BCM2835_MBOX=y\nCONFIG_BCM2835_POWER=y\n# CONFIG_BCM2835_SMI is not set\nCONFIG_BCM2835_THERMAL=y\nCONFIG_BCM2835_TIMER=y\nCONFIG_BCM2835_VCHIQ=y\n# CONFIG_BCM2835_VCHIQ_MMAL is not set\nCONFIG_BCM2835_WDT=y\nCONFIG_BCM7XXX_PHY=y\nCONFIG_BCMGENET=y\nCONFIG_BCM_NET_PHYLIB=y\nCONFIG_BCM_VCIO=y\n# CONFIG_BCM_VC_SM_CMA is not set\nCONFIG_BCM_VIDEOCORE=y\nCONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y\n# CONFIG_BLK_DEV_INITRD is not set\nCONFIG_BLK_DEV_LOOP=y\nCONFIG_BLK_DEV_RAM=y\nCONFIG_BLK_DEV_RAM_COUNT=16\nCONFIG_BLK_DEV_RAM_SIZE=4096\nCONFIG_BLK_DEV_SD=y\nCONFIG_BLK_MQ_PCI=y\nCONFIG_BLK_PM=y\nCONFIG_BLK_SCSI_REQUEST=y\nCONFIG_BOUNCE=y\nCONFIG_BRCMSTB_L2_IRQ=y\nCONFIG_BRCM_CHAR_DRIVERS=y\nCONFIG_BROADCOM_PHY=y\n# CONFIG_CACHE_L2X0 is not set\nCONFIG_CLKDEV_LOOKUP=y\nCONFIG_CLKSRC_MMIO=y\nCONFIG_CLK_BCM2711_DVP=y\nCONFIG_CLK_BCM2835=y\nCONFIG_CLK_RASPBERRYPI=y\nCONFIG_CLONE_BACKWARDS=y\nCONFIG_CMA=y\nCONFIG_CMA_ALIGNMENT=8\nCONFIG_CMA_AREAS=7\n# CONFIG_CMA_DEBUG is not set\n# CONFIG_CMA_DEBUGFS is not set\nCONFIG_CMA_SIZE_MBYTES=5\n# CONFIG_CMA_SIZE_SEL_MAX is not set\nCONFIG_CMA_SIZE_SEL_MBYTES=y\n# CONFIG_CMA_SIZE_SEL_MIN is not set\n# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set\nCONFIG_COMMON_CLK=y\nCONFIG_COMPAT_32BIT_TIME=y\nCONFIG_CONFIGFS_FS=y\nCONFIG_CONSOLE_TRANSLATIONS=y\nCONFIG_CONTIG_ALLOC=y\nCONFIG_CPUFREQ_DT=y\nCONFIG_CPUFREQ_DT_PLATDEV=y\nCONFIG_CPU_32v6K=y\nCONFIG_CPU_32v7=y\nCONFIG_CPU_ABRT_EV7=y\nCONFIG_CPU_CACHE_V7=y\nCONFIG_CPU_CACHE_VIPT=y\nCONFIG_CPU_COPY_V6=y\nCONFIG_CPU_CP15=y\nCONFIG_CPU_CP15_MMU=y\nCONFIG_CPU_FREQ=y\nCONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y\n# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set\nCONFIG_CPU_FREQ_GOV_ATTR_SET=y\nCONFIG_CPU_FREQ_GOV_COMMON=y\nCONFIG_CPU_FREQ_GOV_CONSERVATIVE=y\nCONFIG_CPU_FREQ_GOV_ONDEMAND=y\nCONFIG_CPU_FREQ_GOV_PERFORMANCE=y\nCONFIG_CPU_FREQ_GOV_POWERSAVE=y\nCONFIG_CPU_FREQ_GOV_USERSPACE=y\nCONFIG_CPU_FREQ_STAT=y\nCONFIG_CPU_HAS_ASID=y\nCONFIG_CPU_IDLE=y\nCONFIG_CPU_IDLE_GOV_LADDER=y\nCONFIG_CPU_IDLE_GOV_MENU=y\nCONFIG_CPU_PABRT_V7=y\nCONFIG_CPU_PM=y\nCONFIG_CPU_RMAP=y\nCONFIG_CPU_SPECTRE=y\nCONFIG_CPU_THUMB_CAPABLE=y\nCONFIG_CPU_TLB_V7=y\nCONFIG_CPU_V7=y\nCONFIG_CRC16=y\nCONFIG_CRYPTO_CBC=y\nCONFIG_CRYPTO_CRC32=y\nCONFIG_CRYPTO_CRC32C=y\nCONFIG_CRYPTO_CTS=y\nCONFIG_CRYPTO_DRBG=y\nCONFIG_CRYPTO_DRBG_HMAC=y\nCONFIG_CRYPTO_DRBG_MENU=y\nCONFIG_CRYPTO_ECB=y\nCONFIG_CRYPTO_HMAC=y\nCONFIG_CRYPTO_JITTERENTROPY=y\nCONFIG_CRYPTO_LIB_SHA256=y\nCONFIG_CRYPTO_RNG=y\nCONFIG_CRYPTO_RNG2=y\nCONFIG_CRYPTO_RNG_DEFAULT=y\nCONFIG_CRYPTO_SEQIV=y\nCONFIG_CRYPTO_SHA256=y\nCONFIG_CRYPTO_SHA512=y\nCONFIG_CRYPTO_XTS=y\nCONFIG_DCACHE_WORD_ACCESS=y\nCONFIG_DEBUG_BUGVERBOSE=y\nCONFIG_DEBUG_INFO=y\nCONFIG_DEBUG_LL_INCLUDE=\"mach/debug-macro.S\"\nCONFIG_DIMLIB=y\nCONFIG_DMABUF_HEAPS=y\nCONFIG_DMABUF_HEAPS_CMA=y\nCONFIG_DMABUF_HEAPS_SYSTEM=y\nCONFIG_DMADEVICES=y\nCONFIG_DMA_BCM2708=y\nCONFIG_DMA_BCM2835=y\nCONFIG_DMA_CMA=y\nCONFIG_DMA_ENGINE=y\nCONFIG_DMA_OF=y\nCONFIG_DMA_OPS=y\nCONFIG_DMA_REMAP=y\nCONFIG_DMA_SHARED_BUFFER=y\nCONFIG_DMA_VIRTUAL_CHANNELS=y\nCONFIG_DNOTIFY=y\nCONFIG_DTC=y\nCONFIG_DUMMY_CONSOLE=y\nCONFIG_EDAC_ATOMIC_SCRUB=y\nCONFIG_EDAC_SUPPORT=y\nCONFIG_ENABLE_MUST_CHECK=y\nCONFIG_EXT4_FS=y\nCONFIG_EXT4_FS_POSIX_ACL=y\nCONFIG_EXT4_FS_SECURITY=y\nCONFIG_EXTCON=y\nCONFIG_F2FS_FS=y\nCONFIG_FB=y\nCONFIG_FB_BCM2708=y\nCONFIG_FB_CFB_COPYAREA=y\nCONFIG_FB_CFB_FILLRECT=y\nCONFIG_FB_CFB_IMAGEBLIT=y\nCONFIG_FB_CMDLINE=y\n# CONFIG_FB_RPISENSE is not set\nCONFIG_FB_SIMPLE=y\nCONFIG_FIQ=y\nCONFIG_FIXED_PHY=y\nCONFIG_FIX_EARLYCON_MEM=y\nCONFIG_FONT_8x16=y\nCONFIG_FONT_8x8=y\nCONFIG_FONT_SUPPORT=y\n# CONFIG_FPE_FASTFPE is not set\n# CONFIG_FPE_NWFPE is not set\nCONFIG_FRAMEBUFFER_CONSOLE=y\n# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set\nCONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y\nCONFIG_FREEZER=y\nCONFIG_FS_ENCRYPTION=y\nCONFIG_FS_ENCRYPTION_ALGS=y\nCONFIG_FS_IOMAP=y\nCONFIG_FS_MBCACHE=y\nCONFIG_FS_POSIX_ACL=y\nCONFIG_FW_CACHE=y\nCONFIG_FW_LOADER_PAGED_BUF=y\nCONFIG_GENERIC_ALLOCATOR=y\nCONFIG_GENERIC_ARCH_TOPOLOGY=y\nCONFIG_GENERIC_BUG=y\nCONFIG_GENERIC_CLOCKEVENTS=y\nCONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y\nCONFIG_GENERIC_CPU_AUTOPROBE=y\nCONFIG_GENERIC_EARLY_IOREMAP=y\nCONFIG_GENERIC_GETTIMEOFDAY=y\nCONFIG_GENERIC_IDLE_POLL_SETUP=y\nCONFIG_GENERIC_IRQ_CHIP=y\nCONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y\nCONFIG_GENERIC_IRQ_MIGRATION=y\nCONFIG_GENERIC_IRQ_MULTI_HANDLER=y\nCONFIG_GENERIC_IRQ_SHOW=y\nCONFIG_GENERIC_IRQ_SHOW_LEVEL=y\nCONFIG_GENERIC_MSI_IRQ=y\nCONFIG_GENERIC_MSI_IRQ_DOMAIN=y\nCONFIG_GENERIC_PCI_IOMAP=y\nCONFIG_GENERIC_PHY=y\nCONFIG_GENERIC_PINCONF=y\nCONFIG_GENERIC_PINCTRL_GROUPS=y\nCONFIG_GENERIC_PINMUX_FUNCTIONS=y\nCONFIG_GENERIC_SCHED_CLOCK=y\nCONFIG_GENERIC_SMP_IDLE_THREAD=y\nCONFIG_GENERIC_STRNCPY_FROM_USER=y\nCONFIG_GENERIC_STRNLEN_USER=y\nCONFIG_GENERIC_TIME_VSYSCALL=y\nCONFIG_GENERIC_VDSO_32=y\nCONFIG_GPIOLIB=y\nCONFIG_GPIOLIB_IRQCHIP=y\nCONFIG_GPIO_BCM_VIRT=y\n# CONFIG_GPIO_FSM is not set\nCONFIG_GPIO_RASPBERRYPI_EXP=y\nCONFIG_HANDLE_DOMAIN_IRQ=y\nCONFIG_HARDEN_BRANCH_PREDICTOR=y\nCONFIG_HARDIRQS_SW_RESEND=y\nCONFIG_HAS_DMA=y\nCONFIG_HAS_IOMEM=y\nCONFIG_HAS_IOPORT_MAP=y\nCONFIG_HAVE_SMP=y\nCONFIG_HIGHMEM=y\nCONFIG_HIGHPTE=y\nCONFIG_HOTPLUG_CPU=y\nCONFIG_HW_CONSOLE=y\nCONFIG_HW_RANDOM=y\nCONFIG_HW_RANDOM_BCM2835=y\nCONFIG_HW_RANDOM_IPROC_RNG200=y\nCONFIG_HZ_FIXED=0\nCONFIG_I2C=y\n# CONFIG_I2C_BCM2708 is not set\nCONFIG_I2C_BOARDINFO=y\n# CONFIG_I2C_BRCMSTB is not set\nCONFIG_IKCONFIG=y\nCONFIG_IKCONFIG_PROC=y\nCONFIG_INPUT=y\nCONFIG_INPUT_MOUSEDEV=y\n# CONFIG_INPUT_MOUSEDEV_PSAUX is not set\nCONFIG_INPUT_MOUSEDEV_SCREEN_X=1024\nCONFIG_INPUT_MOUSEDEV_SCREEN_Y=768\nCONFIG_IRQCHIP=y\nCONFIG_IRQ_DOMAIN=y\nCONFIG_IRQ_DOMAIN_HIERARCHY=y\nCONFIG_IRQ_FORCED_THREADING=y\nCONFIG_IRQ_WORK=y\nCONFIG_JBD2=y\nCONFIG_KEYS=y\nCONFIG_LEDS_GPIO=y\nCONFIG_LEDS_TRIGGER_ACTPWR=y\nCONFIG_LEDS_TRIGGER_INPUT=y\nCONFIG_LIBFDT=y\nCONFIG_LOCK_DEBUGGING_SUPPORT=y\nCONFIG_LOCK_SPIN_ON_OWNER=y\nCONFIG_LOGO=y\nCONFIG_LOGO_LINUX_CLUT224=y\n# CONFIG_LOGO_LINUX_MONO is not set\n# CONFIG_LOGO_LINUX_VGA16 is not set\nCONFIG_MAC_PARTITION=y\nCONFIG_MAGIC_SYSRQ=y\nCONFIG_MAILBOX=y\n# CONFIG_MAILBOX_TEST is not set\nCONFIG_MAX_RAW_DEVS=256\nCONFIG_MDIO_BCM_UNIMAC=y\nCONFIG_MDIO_BUS=y\nCONFIG_MDIO_DEVICE=y\nCONFIG_MDIO_DEVRES=y\nCONFIG_MEMFD_CREATE=y\nCONFIG_MEMORY_ISOLATION=y\nCONFIG_MFD_CORE=y\n# CONFIG_MFD_RPISENSE_CORE is not set\nCONFIG_MFD_SYSCON=y\nCONFIG_MICROCHIP_PHY=y\nCONFIG_MIGHT_HAVE_CACHE_L2X0=y\nCONFIG_MIGRATION=y\nCONFIG_MMC=y\nCONFIG_MMC_BCM2835=y\nCONFIG_MMC_BCM2835_DMA=y\nCONFIG_MMC_BCM2835_MMC=y\nCONFIG_MMC_BCM2835_PIO_DMA_BARRIER=2\nCONFIG_MMC_BCM2835_SDHOST=y\nCONFIG_MMC_BLOCK=y\nCONFIG_MMC_BLOCK_MINORS=32\nCONFIG_MMC_SDHCI=y\nCONFIG_MMC_SDHCI_IO_ACCESSORS=y\nCONFIG_MMC_SDHCI_IPROC=y\n# CONFIG_MMC_SDHCI_PCI is not set\nCONFIG_MMC_SDHCI_PLTFM=y\nCONFIG_MODULES_USE_ELF_REL=y\n# CONFIG_MTD is not set\nCONFIG_MUTEX_SPIN_ON_OWNER=y\nCONFIG_NEED_DMA_MAP_STATE=y\nCONFIG_NEON=y\nCONFIG_NET_FLOW_LIMIT=y\nCONFIG_NLS=y\nCONFIG_NLS_ASCII=y\nCONFIG_NOP_USB_XCEIV=y\nCONFIG_NO_HZ=y\nCONFIG_NO_HZ_COMMON=y\nCONFIG_NO_HZ_IDLE=y\nCONFIG_NR_CPUS=4\nCONFIG_NVMEM=y\n# CONFIG_NVMEM_RMEM is not set\nCONFIG_OABI_COMPAT=y\nCONFIG_OF=y\nCONFIG_OF_ADDRESS=y\nCONFIG_OF_CONFIGFS=y\nCONFIG_OF_DYNAMIC=y\nCONFIG_OF_EARLY_FLATTREE=y\nCONFIG_OF_FLATTREE=y\nCONFIG_OF_GPIO=y\nCONFIG_OF_IRQ=y\nCONFIG_OF_KOBJ=y\nCONFIG_OF_MDIO=y\nCONFIG_OF_NET=y\nCONFIG_OF_OVERLAY=y\nCONFIG_OF_RESOLVE=y\nCONFIG_OLD_SIGACTION=y\nCONFIG_OLD_SIGSUSPEND3=y\nCONFIG_PADATA=y\nCONFIG_PAGE_OFFSET=0xC0000000\nCONFIG_PCI=y\nCONFIG_PCIEAER=y\nCONFIG_PCIEPORTBUS=y\nCONFIG_PCIE_BRCMSTB=y\nCONFIG_PCIE_PME=y\nCONFIG_PCI_DOMAINS=y\nCONFIG_PCI_DOMAINS_GENERIC=y\nCONFIG_PCI_MSI=y\nCONFIG_PCI_MSI_IRQ_DOMAIN=y\nCONFIG_PERF_USE_VMALLOC=y\nCONFIG_PGTABLE_LEVELS=3\nCONFIG_PHYLIB=y\nCONFIG_PHYS_ADDR_T_64BIT=y\nCONFIG_PINCTRL=y\nCONFIG_PINCTRL_BCM2835=y\nCONFIG_PM=y\nCONFIG_PM_CLK=y\nCONFIG_PM_GENERIC_DOMAINS=y\nCONFIG_PM_GENERIC_DOMAINS_OF=y\nCONFIG_PM_GENERIC_DOMAINS_SLEEP=y\nCONFIG_PM_OPP=y\nCONFIG_PM_SLEEP=y\nCONFIG_PM_SLEEP_SMP=y\nCONFIG_POWER_SUPPLY=y\nCONFIG_PRINTK_TIME=y\nCONFIG_RAS=y\nCONFIG_RASPBERRYPI_FIRMWARE=y\nCONFIG_RASPBERRYPI_POWER=y\nCONFIG_RATIONAL=y\n# CONFIG_RAVE_SP_CORE is not set\nCONFIG_RAW_DRIVER=y\nCONFIG_REGMAP=y\nCONFIG_REGMAP_MMIO=y\nCONFIG_REGULATOR=y\nCONFIG_REGULATOR_FIXED_VOLTAGE=y\nCONFIG_REGULATOR_GPIO=y\nCONFIG_RESET_CONTROLLER=y\nCONFIG_RESET_RASPBERRYPI=y\nCONFIG_RESET_SIMPLE=y\nCONFIG_RFS_ACCEL=y\n# CONFIG_RPIVID_MEM is not set\n# CONFIG_RPI_AXIPERF is not set\n# CONFIG_RPI_POE_POWER is not set\nCONFIG_RPS=y\nCONFIG_RWSEM_SPIN_ON_OWNER=y\nCONFIG_SCSI=y\n# CONFIG_SCSI_LOWLEVEL is not set\n# CONFIG_SCSI_PROC_FS is not set\nCONFIG_SERIAL_8250_BCM2835AUX=y\n# CONFIG_SERIAL_8250_DMA is not set\nCONFIG_SERIAL_8250_EXTENDED=y\nCONFIG_SERIAL_8250_FSL=y\nCONFIG_SERIAL_8250_NR_UARTS=1\nCONFIG_SERIAL_8250_RUNTIME_UARTS=0\nCONFIG_SERIAL_8250_SHARE_IRQ=y\nCONFIG_SERIAL_AMBA_PL011=y\nCONFIG_SERIAL_AMBA_PL011_CONSOLE=y\nCONFIG_SERIAL_DEV_BUS=y\n# CONFIG_SERIAL_DEV_CTRL_TTYPORT is not set\nCONFIG_SERIAL_MCTRL_GPIO=y\nCONFIG_SERIAL_OF_PLATFORM=y\nCONFIG_SG_POOL=y\nCONFIG_SMP=y\nCONFIG_SMP_ON_UP=y\nCONFIG_SMSC_PHY=y\n# CONFIG_SND_SOC_AD193X_I2C is not set\n# CONFIG_SND_SOC_AD193X_SPI is not set\nCONFIG_SPARSE_IRQ=y\nCONFIG_SRCU=y\n# CONFIG_STRIP_ASM_SYMS is not set\nCONFIG_SUSPEND=y\nCONFIG_SUSPEND_FREEZER=y\nCONFIG_SWIOTLB=y\nCONFIG_SWPHY=y\nCONFIG_SWP_EMULATE=y\nCONFIG_SYS_SUPPORTS_APM_EMULATION=y\nCONFIG_SYS_SUPPORTS_HUGETLBFS=y\n# CONFIG_TEXTSEARCH is not set\nCONFIG_THERMAL=y\nCONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y\nCONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0\nCONFIG_THERMAL_GOV_STEP_WISE=y\nCONFIG_THERMAL_OF=y\nCONFIG_TICK_CPU_ACCOUNTING=y\nCONFIG_TIMER_OF=y\nCONFIG_TIMER_PROBE=y\nCONFIG_TMPFS_POSIX_ACL=y\nCONFIG_TREE_RCU=y\nCONFIG_TREE_SRCU=y\nCONFIG_UEVENT_HELPER_PATH=\"\"\n# CONFIG_UID16 is not set\nCONFIG_UNCOMPRESS_INCLUDE=\"debug/uncompress.h\"\nCONFIG_UNWINDER_ARM=y\nCONFIG_USB=y\nCONFIG_USB_ANNOUNCE_NEW_DEVICES=y\nCONFIG_USB_COMMON=y\nCONFIG_USB_DWCOTG=y\nCONFIG_USB_GADGET=y\nCONFIG_USB_LAN78XX=y\nCONFIG_USB_NET_DRIVERS=y\nCONFIG_USB_NET_SMSC95XX=y\nCONFIG_USB_PCI=y\nCONFIG_USB_PHY=y\nCONFIG_USB_STORAGE=y\nCONFIG_USB_SUPPORT=y\nCONFIG_USB_UAS=y\n# CONFIG_USB_UHCI_HCD is not set\nCONFIG_USB_USBNET=y\nCONFIG_USB_XHCI_HCD=y\nCONFIG_USB_XHCI_PCI=y\nCONFIG_USB_XHCI_PLATFORM=y\nCONFIG_USE_OF=y\nCONFIG_VFP=y\nCONFIG_VFPv3=y\nCONFIG_VT=y\nCONFIG_VT_CONSOLE=y\nCONFIG_VT_CONSOLE_SLEEP=y\nCONFIG_VT_HW_CONSOLE_BINDING=y\nCONFIG_WATCHDOG_CORE=y\nCONFIG_XPS=y\nCONFIG_XZ_DEC_ARM=y\nCONFIG_XZ_DEC_BCJ=y\nCONFIG_ZBOOT_ROM_BSS=0\nCONFIG_ZBOOT_ROM_TEXT=0\n"
  },
  {
    "path": "target/linux/bcm27xx/bcm2709/target.mk",
    "content": "#\n# Copyright (C) 2015-2019 OpenWrt.org\n# Copyright (C) 2017 LEDE project\n#\n\nSUBTARGET:=bcm2709\nBOARDNAME:=BCM2709/BCM2710/BCM2711 boards (32 bit)\nCPU_TYPE:=cortex-a7\nCPU_SUBTYPE:=neon-vfpv4\n\ndefine Target/Description\n\tBuild firmware image for BCM2709/BCM2710/BCM2711 devices.\n\tThis firmware features a 32 bit kernel.\nendef\n"
  },
  {
    "path": "target/linux/bcm27xx/bcm2710/config-5.10",
    "content": "CONFIG_64BIT=y\n# CONFIG_AIO is not set\nCONFIG_ARCH_BCM2835=y\nCONFIG_ARCH_DMA_ADDR_T_64BIT=y\nCONFIG_ARCH_HIBERNATION_POSSIBLE=y\nCONFIG_ARCH_KEEP_MEMBLOCK=y\nCONFIG_ARCH_MMAP_RND_BITS=18\nCONFIG_ARCH_MMAP_RND_BITS_MAX=24\nCONFIG_ARCH_MMAP_RND_BITS_MIN=18\nCONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11\nCONFIG_ARCH_PROC_KCORE_TEXT=y\nCONFIG_ARCH_SELECT_MEMORY_MODEL=y\nCONFIG_ARCH_SPARSEMEM_DEFAULT=y\nCONFIG_ARCH_SPARSEMEM_ENABLE=y\nCONFIG_ARCH_STACKWALK=y\nCONFIG_ARCH_SUSPEND_POSSIBLE=y\nCONFIG_ARM64=y\nCONFIG_ARM64_4K_PAGES=y\nCONFIG_ARM64_CNP=y\nCONFIG_ARM64_ERRATUM_819472=y\nCONFIG_ARM64_ERRATUM_824069=y\nCONFIG_ARM64_ERRATUM_826319=y\nCONFIG_ARM64_ERRATUM_827319=y\nCONFIG_ARM64_ERRATUM_832075=y\nCONFIG_ARM64_ERRATUM_843419=y\nCONFIG_ARM64_HW_AFDBM=y\nCONFIG_ARM64_MODULE_PLTS=y\nCONFIG_ARM64_PAGE_SHIFT=12\nCONFIG_ARM64_PAN=y\nCONFIG_ARM64_PA_BITS=48\nCONFIG_ARM64_PA_BITS_48=y\nCONFIG_ARM64_PTR_AUTH=y\nCONFIG_ARM64_SVE=y\nCONFIG_ARM64_TAGGED_ADDR_ABI=y\nCONFIG_ARM64_UAO=y\nCONFIG_ARM64_VA_BITS=39\nCONFIG_ARM64_VA_BITS_39=y\nCONFIG_ARM64_VHE=y\nCONFIG_ARM64_WORKAROUND_CLEAN_CACHE=y\nCONFIG_ARM_AMBA=y\nCONFIG_ARM_ARCH_TIMER=y\nCONFIG_ARM_ARCH_TIMER_EVTSTREAM=y\nCONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y\nCONFIG_ARM_GIC=y\nCONFIG_ARM_GIC_V2M=y\nCONFIG_ARM_GIC_V3=y\nCONFIG_ARM_GIC_V3_ITS=y\nCONFIG_ARM_GIC_V3_ITS_PCI=y\nCONFIG_ARM_PSCI_FW=y\nCONFIG_ARM_RASPBERRYPI_CPUFREQ=y\nCONFIG_ARM_TIMER_SP804=y\nCONFIG_ASSOCIATIVE_ARRAY=y\nCONFIG_AUDIT_ARCH_COMPAT_GENERIC=y\nCONFIG_BCM2708_VCMEM=y\n# CONFIG_BCM2711_THERMAL is not set\nCONFIG_BCM2835_DEVGPIOMEM=y\nCONFIG_BCM2835_MBOX=y\nCONFIG_BCM2835_POWER=y\n# CONFIG_BCM2835_SMI is not set\nCONFIG_BCM2835_THERMAL=y\nCONFIG_BCM2835_VCHIQ=y\n# CONFIG_BCM2835_VCHIQ_MMAL is not set\nCONFIG_BCM2835_WDT=y\nCONFIG_BCM_VCIO=y\n# CONFIG_BCM_VC_SM_CMA is not set\nCONFIG_BCM_VIDEOCORE=y\n# CONFIG_BLK_DEV_INITRD is not set\nCONFIG_BLK_DEV_LOOP=y\nCONFIG_BLK_DEV_RAM=y\nCONFIG_BLK_DEV_RAM_COUNT=16\nCONFIG_BLK_DEV_RAM_SIZE=4096\nCONFIG_BLK_DEV_SD=y\nCONFIG_BLK_MQ_PCI=y\nCONFIG_BLK_PM=y\nCONFIG_BLK_SCSI_REQUEST=y\nCONFIG_BOUNCE=y\nCONFIG_BRCMSTB_L2_IRQ=y\nCONFIG_BRCM_CHAR_DRIVERS=y\nCONFIG_CAVIUM_ERRATUM_22375=y\nCONFIG_CAVIUM_ERRATUM_23154=y\nCONFIG_CAVIUM_ERRATUM_27456=y\nCONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y\nCONFIG_CLKDEV_LOOKUP=y\nCONFIG_CLKSRC_MMIO=y\nCONFIG_CLK_BCM2711_DVP=y\nCONFIG_CLK_BCM2835=y\nCONFIG_CLK_RASPBERRYPI=y\nCONFIG_CLONE_BACKWARDS=y\nCONFIG_CMA=y\nCONFIG_CMA_ALIGNMENT=8\nCONFIG_CMA_AREAS=7\n# CONFIG_CMA_DEBUG is not set\n# CONFIG_CMA_DEBUGFS is not set\nCONFIG_CMA_SIZE_MBYTES=5\n# CONFIG_CMA_SIZE_SEL_MAX is not set\nCONFIG_CMA_SIZE_SEL_MBYTES=y\n# CONFIG_CMA_SIZE_SEL_MIN is not set\n# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set\nCONFIG_COMMON_CLK=y\nCONFIG_COMMON_CLK_XGENE=y\n# CONFIG_COMPAT_32BIT_TIME is not set\nCONFIG_CONFIGFS_FS=y\nCONFIG_CONSOLE_TRANSLATIONS=y\nCONFIG_CONTIG_ALLOC=y\nCONFIG_CPUFREQ_DT=y\nCONFIG_CPUFREQ_DT_PLATDEV=y\nCONFIG_CPU_FREQ=y\nCONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y\n# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set\nCONFIG_CPU_FREQ_GOV_ATTR_SET=y\nCONFIG_CPU_FREQ_GOV_COMMON=y\nCONFIG_CPU_FREQ_GOV_CONSERVATIVE=y\nCONFIG_CPU_FREQ_GOV_ONDEMAND=y\nCONFIG_CPU_FREQ_GOV_PERFORMANCE=y\nCONFIG_CPU_FREQ_GOV_POWERSAVE=y\nCONFIG_CPU_FREQ_GOV_USERSPACE=y\nCONFIG_CPU_FREQ_STAT=y\nCONFIG_CPU_IDLE=y\nCONFIG_CPU_IDLE_GOV_LADDER=y\nCONFIG_CPU_IDLE_GOV_MENU=y\nCONFIG_CPU_PM=y\nCONFIG_CPU_RMAP=y\nCONFIG_CRC16=y\nCONFIG_CRYPTO_CBC=y\nCONFIG_CRYPTO_CRC32=y\nCONFIG_CRYPTO_CRC32C=y\nCONFIG_CRYPTO_CTS=y\nCONFIG_CRYPTO_DRBG=y\nCONFIG_CRYPTO_DRBG_HMAC=y\nCONFIG_CRYPTO_DRBG_MENU=y\nCONFIG_CRYPTO_ECB=y\nCONFIG_CRYPTO_HMAC=y\nCONFIG_CRYPTO_JITTERENTROPY=y\nCONFIG_CRYPTO_LIB_SHA256=y\nCONFIG_CRYPTO_RNG=y\nCONFIG_CRYPTO_RNG2=y\nCONFIG_CRYPTO_RNG_DEFAULT=y\nCONFIG_CRYPTO_SEQIV=y\nCONFIG_CRYPTO_SHA256=y\nCONFIG_CRYPTO_SHA512=y\nCONFIG_CRYPTO_XTS=y\nCONFIG_DCACHE_WORD_ACCESS=y\nCONFIG_DEBUG_BUGVERBOSE=y\nCONFIG_DEBUG_INFO=y\nCONFIG_DMABUF_HEAPS=y\nCONFIG_DMABUF_HEAPS_CMA=y\nCONFIG_DMABUF_HEAPS_SYSTEM=y\nCONFIG_DMADEVICES=y\nCONFIG_DMA_BCM2708=y\nCONFIG_DMA_BCM2835=y\nCONFIG_DMA_CMA=y\nCONFIG_DMA_DIRECT_REMAP=y\nCONFIG_DMA_ENGINE=y\nCONFIG_DMA_OF=y\nCONFIG_DMA_REMAP=y\nCONFIG_DMA_SHARED_BUFFER=y\nCONFIG_DMA_VIRTUAL_CHANNELS=y\nCONFIG_DNOTIFY=y\nCONFIG_DTC=y\nCONFIG_DUMMY_CONSOLE=y\nCONFIG_EDAC_SUPPORT=y\nCONFIG_ENABLE_MUST_CHECK=y\nCONFIG_EXT4_FS=y\nCONFIG_EXT4_FS_POSIX_ACL=y\nCONFIG_EXT4_FS_SECURITY=y\nCONFIG_EXTCON=y\nCONFIG_F2FS_FS=y\nCONFIG_FB=y\nCONFIG_FB_BCM2708=y\nCONFIG_FB_CFB_COPYAREA=y\nCONFIG_FB_CFB_FILLRECT=y\nCONFIG_FB_CFB_IMAGEBLIT=y\nCONFIG_FB_CMDLINE=y\n# CONFIG_FB_RPISENSE is not set\nCONFIG_FB_SIMPLE=y\nCONFIG_FIXED_PHY=y\nCONFIG_FIX_EARLYCON_MEM=y\n# CONFIG_FLATMEM_MANUAL is not set\nCONFIG_FONT_8x16=y\nCONFIG_FONT_8x8=y\nCONFIG_FONT_SUPPORT=y\nCONFIG_FRAMEBUFFER_CONSOLE=y\n# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set\nCONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y\nCONFIG_FRAME_POINTER=y\nCONFIG_FREEZER=y\nCONFIG_FSL_ERRATUM_A008585=y\nCONFIG_FS_ENCRYPTION=y\nCONFIG_FS_ENCRYPTION_ALGS=y\nCONFIG_FS_IOMAP=y\nCONFIG_FS_MBCACHE=y\nCONFIG_FS_POSIX_ACL=y\nCONFIG_FW_CACHE=y\nCONFIG_FW_LOADER_PAGED_BUF=y\nCONFIG_GENERIC_ALLOCATOR=y\nCONFIG_GENERIC_ARCH_TOPOLOGY=y\nCONFIG_GENERIC_BUG=y\nCONFIG_GENERIC_BUG_RELATIVE_POINTERS=y\nCONFIG_GENERIC_CLOCKEVENTS=y\nCONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y\nCONFIG_GENERIC_CPU_AUTOPROBE=y\nCONFIG_GENERIC_CPU_VULNERABILITIES=y\nCONFIG_GENERIC_CSUM=y\nCONFIG_GENERIC_EARLY_IOREMAP=y\nCONFIG_GENERIC_GETTIMEOFDAY=y\nCONFIG_GENERIC_IDLE_POLL_SETUP=y\nCONFIG_GENERIC_IRQ_CHIP=y\nCONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y\nCONFIG_GENERIC_IRQ_MIGRATION=y\nCONFIG_GENERIC_IRQ_MULTI_HANDLER=y\nCONFIG_GENERIC_IRQ_SHOW=y\nCONFIG_GENERIC_IRQ_SHOW_LEVEL=y\nCONFIG_GENERIC_MSI_IRQ=y\nCONFIG_GENERIC_MSI_IRQ_DOMAIN=y\nCONFIG_GENERIC_PCI_IOMAP=y\nCONFIG_GENERIC_PINCONF=y\nCONFIG_GENERIC_PINCTRL_GROUPS=y\nCONFIG_GENERIC_PINMUX_FUNCTIONS=y\nCONFIG_GENERIC_SCHED_CLOCK=y\nCONFIG_GENERIC_SMP_IDLE_THREAD=y\nCONFIG_GENERIC_STRNCPY_FROM_USER=y\nCONFIG_GENERIC_STRNLEN_USER=y\nCONFIG_GENERIC_TIME_VSYSCALL=y\nCONFIG_GPIOLIB=y\nCONFIG_GPIOLIB_IRQCHIP=y\nCONFIG_GPIO_BCM_VIRT=y\n# CONFIG_GPIO_FSM is not set\nCONFIG_GPIO_RASPBERRYPI_EXP=y\nCONFIG_HANDLE_DOMAIN_IRQ=y\nCONFIG_HARDIRQS_SW_RESEND=y\nCONFIG_HAS_DMA=y\nCONFIG_HAS_IOMEM=y\nCONFIG_HAS_IOPORT_MAP=y\nCONFIG_HOLES_IN_ZONE=y\nCONFIG_HOTPLUG_CPU=y\nCONFIG_HW_CONSOLE=y\nCONFIG_HW_RANDOM=y\nCONFIG_HW_RANDOM_BCM2835=y\nCONFIG_I2C=y\n# CONFIG_I2C_BCM2708 is not set\nCONFIG_I2C_BOARDINFO=y\n# CONFIG_I2C_BRCMSTB is not set\nCONFIG_IKCONFIG=y\nCONFIG_IKCONFIG_PROC=y\nCONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000\nCONFIG_INPUT=y\nCONFIG_INPUT_MOUSEDEV=y\n# CONFIG_INPUT_MOUSEDEV_PSAUX is not set\nCONFIG_INPUT_MOUSEDEV_SCREEN_X=1024\nCONFIG_INPUT_MOUSEDEV_SCREEN_Y=768\nCONFIG_IRQCHIP=y\nCONFIG_IRQ_DOMAIN=y\nCONFIG_IRQ_DOMAIN_HIERARCHY=y\nCONFIG_IRQ_FORCED_THREADING=y\nCONFIG_IRQ_WORK=y\nCONFIG_JBD2=y\nCONFIG_KEYS=y\nCONFIG_LEDS_GPIO=y\nCONFIG_LEDS_TRIGGER_ACTPWR=y\nCONFIG_LEDS_TRIGGER_INPUT=y\nCONFIG_LIBFDT=y\nCONFIG_LOCK_DEBUGGING_SUPPORT=y\nCONFIG_LOCK_SPIN_ON_OWNER=y\nCONFIG_LOGO=y\nCONFIG_LOGO_LINUX_CLUT224=y\n# CONFIG_LOGO_LINUX_MONO is not set\n# CONFIG_LOGO_LINUX_VGA16 is not set\nCONFIG_MAC_PARTITION=y\nCONFIG_MAGIC_SYSRQ=y\nCONFIG_MAILBOX=y\n# CONFIG_MAILBOX_TEST is not set\nCONFIG_MAX_RAW_DEVS=256\nCONFIG_MDIO_BUS=y\nCONFIG_MDIO_DEVICE=y\nCONFIG_MDIO_DEVRES=y\nCONFIG_MEMFD_CREATE=y\nCONFIG_MEMORY_ISOLATION=y\nCONFIG_MFD_CORE=y\n# CONFIG_MFD_RPISENSE_CORE is not set\nCONFIG_MFD_SYSCON=y\nCONFIG_MICROCHIP_PHY=y\nCONFIG_MIGRATION=y\nCONFIG_MMC=y\nCONFIG_MMC_BCM2835=y\nCONFIG_MMC_BCM2835_DMA=y\nCONFIG_MMC_BCM2835_MMC=y\nCONFIG_MMC_BCM2835_PIO_DMA_BARRIER=2\nCONFIG_MMC_BCM2835_SDHOST=y\nCONFIG_MMC_BLOCK=y\nCONFIG_MMC_BLOCK_MINORS=32\nCONFIG_MMC_SDHCI=y\nCONFIG_MMC_SDHCI_IO_ACCESSORS=y\nCONFIG_MMC_SDHCI_IPROC=y\n# CONFIG_MMC_SDHCI_PCI is not set\nCONFIG_MMC_SDHCI_PLTFM=y\nCONFIG_MODULES_USE_ELF_RELA=y\n# CONFIG_MTD is not set\nCONFIG_MUTEX_SPIN_ON_OWNER=y\nCONFIG_NEED_DMA_MAP_STATE=y\nCONFIG_NEED_SG_DMA_LENGTH=y\nCONFIG_NET_FLOW_LIMIT=y\nCONFIG_NLS=y\nCONFIG_NLS_ASCII=y\nCONFIG_NO_HZ=y\nCONFIG_NO_HZ_COMMON=y\nCONFIG_NO_HZ_IDLE=y\nCONFIG_NR_CPUS=4\nCONFIG_NVMEM=y\n# CONFIG_NVMEM_RMEM is not set\nCONFIG_OF=y\nCONFIG_OF_ADDRESS=y\nCONFIG_OF_CONFIGFS=y\nCONFIG_OF_DYNAMIC=y\nCONFIG_OF_EARLY_FLATTREE=y\nCONFIG_OF_FLATTREE=y\nCONFIG_OF_GPIO=y\nCONFIG_OF_IRQ=y\nCONFIG_OF_KOBJ=y\nCONFIG_OF_MDIO=y\nCONFIG_OF_NET=y\nCONFIG_OF_OVERLAY=y\nCONFIG_OF_RESOLVE=y\nCONFIG_PADATA=y\nCONFIG_PARTITION_PERCPU=y\nCONFIG_PCI=y\n# CONFIG_PCIE_BRCMSTB is not set\nCONFIG_PCI_DOMAINS=y\nCONFIG_PCI_DOMAINS_GENERIC=y\nCONFIG_PCI_MSI=y\nCONFIG_PCI_MSI_IRQ_DOMAIN=y\nCONFIG_PGTABLE_LEVELS=3\nCONFIG_PHYLIB=y\nCONFIG_PHYS_ADDR_T_64BIT=y\nCONFIG_PINCTRL=y\nCONFIG_PINCTRL_BCM2835=y\nCONFIG_PM=y\nCONFIG_PM_CLK=y\nCONFIG_PM_GENERIC_DOMAINS=y\nCONFIG_PM_GENERIC_DOMAINS_OF=y\nCONFIG_PM_GENERIC_DOMAINS_SLEEP=y\nCONFIG_PM_OPP=y\nCONFIG_PM_SLEEP=y\nCONFIG_PM_SLEEP_SMP=y\nCONFIG_POWER_RESET=y\nCONFIG_POWER_SUPPLY=y\nCONFIG_PRINTK_TIME=y\nCONFIG_QUEUED_RWLOCKS=y\nCONFIG_QUEUED_SPINLOCKS=y\nCONFIG_RASPBERRYPI_FIRMWARE=y\nCONFIG_RASPBERRYPI_POWER=y\nCONFIG_RATIONAL=y\n# CONFIG_RAVE_SP_CORE is not set\nCONFIG_RAW_DRIVER=y\nCONFIG_REGMAP=y\nCONFIG_REGMAP_MMIO=y\nCONFIG_REGULATOR=y\nCONFIG_REGULATOR_FIXED_VOLTAGE=y\nCONFIG_REGULATOR_GPIO=y\nCONFIG_RESET_CONTROLLER=y\n# CONFIG_RESET_RASPBERRYPI is not set\nCONFIG_RESET_SIMPLE=y\nCONFIG_RFS_ACCEL=y\nCONFIG_RODATA_FULL_DEFAULT_ENABLED=y\n# CONFIG_RPIVID_MEM is not set\n# CONFIG_RPI_AXIPERF is not set\n# CONFIG_RPI_POE_POWER is not set\nCONFIG_RPS=y\nCONFIG_RWSEM_SPIN_ON_OWNER=y\nCONFIG_SCSI=y\n# CONFIG_SCSI_LOWLEVEL is not set\n# CONFIG_SCSI_PROC_FS is not set\nCONFIG_SERIAL_8250_BCM2835AUX=y\n# CONFIG_SERIAL_8250_DMA is not set\nCONFIG_SERIAL_8250_EXTENDED=y\nCONFIG_SERIAL_8250_FSL=y\nCONFIG_SERIAL_8250_NR_UARTS=1\nCONFIG_SERIAL_8250_RUNTIME_UARTS=0\nCONFIG_SERIAL_8250_SHARE_IRQ=y\nCONFIG_SERIAL_AMBA_PL011=y\nCONFIG_SERIAL_AMBA_PL011_CONSOLE=y\nCONFIG_SERIAL_DEV_BUS=y\n# CONFIG_SERIAL_DEV_CTRL_TTYPORT is not set\nCONFIG_SERIAL_MCTRL_GPIO=y\nCONFIG_SERIAL_OF_PLATFORM=y\nCONFIG_SG_POOL=y\nCONFIG_SMP=y\nCONFIG_SMSC_PHY=y\n# CONFIG_SND_SOC_AD193X_I2C is not set\n# CONFIG_SND_SOC_AD193X_SPI is not set\nCONFIG_SPARSEMEM=y\nCONFIG_SPARSEMEM_EXTREME=y\nCONFIG_SPARSEMEM_MANUAL=y\nCONFIG_SPARSEMEM_VMEMMAP=y\nCONFIG_SPARSEMEM_VMEMMAP_ENABLE=y\nCONFIG_SPARSE_IRQ=y\nCONFIG_SRCU=y\n# CONFIG_STRIP_ASM_SYMS is not set\nCONFIG_SUSPEND=y\nCONFIG_SUSPEND_FREEZER=y\nCONFIG_SWIOTLB=y\nCONFIG_SWPHY=y\nCONFIG_SYSCTL_EXCEPTION_TRACE=y\nCONFIG_SYS_SUPPORTS_HUGETLBFS=y\n# CONFIG_TEXTSEARCH is not set\nCONFIG_THERMAL=y\nCONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y\nCONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0\nCONFIG_THERMAL_GOV_STEP_WISE=y\nCONFIG_THERMAL_OF=y\nCONFIG_THERMAL_WRITABLE_TRIPS=y\nCONFIG_THREAD_INFO_IN_TASK=y\nCONFIG_TICK_CPU_ACCOUNTING=y\nCONFIG_TIMER_OF=y\nCONFIG_TIMER_PROBE=y\nCONFIG_TMPFS_POSIX_ACL=y\nCONFIG_TREE_RCU=y\nCONFIG_TREE_SRCU=y\nCONFIG_UEVENT_HELPER_PATH=\"\"\nCONFIG_UNMAP_KERNEL_AT_EL0=y\nCONFIG_USB=y\nCONFIG_USB_ANNOUNCE_NEW_DEVICES=y\nCONFIG_USB_COMMON=y\nCONFIG_USB_DWCOTG=y\nCONFIG_USB_LAN78XX=y\nCONFIG_USB_NET_DRIVERS=y\nCONFIG_USB_NET_SMSC95XX=y\nCONFIG_USB_STORAGE=y\nCONFIG_USB_SUPPORT=y\nCONFIG_USB_UAS=y\nCONFIG_USB_USBNET=y\nCONFIG_VMAP_STACK=y\nCONFIG_VT=y\nCONFIG_VT_CONSOLE=y\nCONFIG_VT_CONSOLE_SLEEP=y\nCONFIG_VT_HW_CONSOLE_BINDING=y\nCONFIG_WATCHDOG_CORE=y\nCONFIG_XPS=y\nCONFIG_XZ_DEC_ARM=y\nCONFIG_XZ_DEC_BCJ=y\nCONFIG_ZONE_DMA32=y\n"
  },
  {
    "path": "target/linux/bcm27xx/bcm2710/target.mk",
    "content": "#\n# Copyright (C) 2016-2019 OpenWrt.org\n# Copyright (C) 2017 LEDE project\n#\n\nARCH:=aarch64\nSUBTARGET:=bcm2710\nBOARDNAME:=BCM2710 boards (64 bit)\nCPU_TYPE:=cortex-a53\n\ndefine Target/Description\n\tBuild firmware image for BCM2710 devices.\n\tThis firmware features a 64 bit kernel.\nendef\n"
  },
  {
    "path": "target/linux/bcm27xx/bcm2711/config-5.10",
    "content": "CONFIG_64BIT=y\n# CONFIG_AIO is not set\nCONFIG_ARCH_BCM2835=y\nCONFIG_ARCH_DMA_ADDR_T_64BIT=y\nCONFIG_ARCH_HIBERNATION_POSSIBLE=y\nCONFIG_ARCH_KEEP_MEMBLOCK=y\nCONFIG_ARCH_MMAP_RND_BITS=18\nCONFIG_ARCH_MMAP_RND_BITS_MAX=24\nCONFIG_ARCH_MMAP_RND_BITS_MIN=18\nCONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11\nCONFIG_ARCH_PROC_KCORE_TEXT=y\nCONFIG_ARCH_SELECT_MEMORY_MODEL=y\nCONFIG_ARCH_SPARSEMEM_DEFAULT=y\nCONFIG_ARCH_SPARSEMEM_ENABLE=y\nCONFIG_ARCH_STACKWALK=y\nCONFIG_ARCH_SUSPEND_POSSIBLE=y\nCONFIG_ARM64=y\nCONFIG_ARM64_4K_PAGES=y\nCONFIG_ARM64_CNP=y\nCONFIG_ARM64_ERRATUM_819472=y\nCONFIG_ARM64_ERRATUM_824069=y\nCONFIG_ARM64_ERRATUM_826319=y\nCONFIG_ARM64_ERRATUM_827319=y\nCONFIG_ARM64_ERRATUM_832075=y\nCONFIG_ARM64_ERRATUM_843419=y\nCONFIG_ARM64_HW_AFDBM=y\nCONFIG_ARM64_MODULE_PLTS=y\nCONFIG_ARM64_PAGE_SHIFT=12\nCONFIG_ARM64_PAN=y\nCONFIG_ARM64_PA_BITS=48\nCONFIG_ARM64_PA_BITS_48=y\nCONFIG_ARM64_PTR_AUTH=y\nCONFIG_ARM64_SVE=y\nCONFIG_ARM64_TAGGED_ADDR_ABI=y\nCONFIG_ARM64_UAO=y\nCONFIG_ARM64_VA_BITS=39\nCONFIG_ARM64_VA_BITS_39=y\nCONFIG_ARM64_VHE=y\nCONFIG_ARM64_WORKAROUND_CLEAN_CACHE=y\nCONFIG_ARM_AMBA=y\nCONFIG_ARM_ARCH_TIMER=y\nCONFIG_ARM_ARCH_TIMER_EVTSTREAM=y\nCONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y\nCONFIG_ARM_GIC=y\nCONFIG_ARM_GIC_V2M=y\nCONFIG_ARM_GIC_V3=y\nCONFIG_ARM_GIC_V3_ITS=y\nCONFIG_ARM_GIC_V3_ITS_PCI=y\nCONFIG_ARM_PSCI_FW=y\nCONFIG_ARM_RASPBERRYPI_CPUFREQ=y\nCONFIG_ARM_TIMER_SP804=y\nCONFIG_ASSOCIATIVE_ARRAY=y\nCONFIG_AUDIT_ARCH_COMPAT_GENERIC=y\nCONFIG_BCM2708_VCMEM=y\nCONFIG_BCM2711_THERMAL=y\nCONFIG_BCM2835_DEVGPIOMEM=y\nCONFIG_BCM2835_MBOX=y\nCONFIG_BCM2835_POWER=y\n# CONFIG_BCM2835_SMI is not set\n# CONFIG_BCM2835_THERMAL is not set\nCONFIG_BCM2835_VCHIQ=y\n# CONFIG_BCM2835_VCHIQ_MMAL is not set\nCONFIG_BCM2835_WDT=y\nCONFIG_BCM7XXX_PHY=y\nCONFIG_BCMGENET=y\nCONFIG_BCM_NET_PHYLIB=y\nCONFIG_BCM_VCIO=y\n# CONFIG_BCM_VC_SM_CMA is not set\nCONFIG_BCM_VIDEOCORE=y\n# CONFIG_BLK_DEV_INITRD is not set\nCONFIG_BLK_DEV_LOOP=y\nCONFIG_BLK_DEV_RAM=y\nCONFIG_BLK_DEV_RAM_COUNT=16\nCONFIG_BLK_DEV_RAM_SIZE=4096\nCONFIG_BLK_DEV_SD=y\nCONFIG_BLK_MQ_PCI=y\nCONFIG_BLK_PM=y\nCONFIG_BLK_SCSI_REQUEST=y\nCONFIG_BOUNCE=y\nCONFIG_BRCMSTB_L2_IRQ=y\nCONFIG_BRCM_CHAR_DRIVERS=y\nCONFIG_BROADCOM_PHY=y\nCONFIG_CAVIUM_ERRATUM_22375=y\nCONFIG_CAVIUM_ERRATUM_23154=y\nCONFIG_CAVIUM_ERRATUM_27456=y\nCONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y\nCONFIG_CLKDEV_LOOKUP=y\nCONFIG_CLKSRC_MMIO=y\nCONFIG_CLK_BCM2711_DVP=y\nCONFIG_CLK_BCM2835=y\nCONFIG_CLK_RASPBERRYPI=y\nCONFIG_CLONE_BACKWARDS=y\nCONFIG_CMA=y\nCONFIG_CMA_ALIGNMENT=8\nCONFIG_CMA_AREAS=7\n# CONFIG_CMA_DEBUG is not set\n# CONFIG_CMA_DEBUGFS is not set\nCONFIG_CMA_SIZE_MBYTES=5\n# CONFIG_CMA_SIZE_SEL_MAX is not set\nCONFIG_CMA_SIZE_SEL_MBYTES=y\n# CONFIG_CMA_SIZE_SEL_MIN is not set\n# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set\nCONFIG_COMMON_CLK=y\nCONFIG_COMMON_CLK_XGENE=y\n# CONFIG_COMPAT_32BIT_TIME is not set\nCONFIG_CONFIGFS_FS=y\nCONFIG_CONSOLE_TRANSLATIONS=y\nCONFIG_CONTIG_ALLOC=y\nCONFIG_CPUFREQ_DT=y\nCONFIG_CPUFREQ_DT_PLATDEV=y\nCONFIG_CPU_FREQ=y\nCONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y\n# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set\nCONFIG_CPU_FREQ_GOV_ATTR_SET=y\nCONFIG_CPU_FREQ_GOV_COMMON=y\nCONFIG_CPU_FREQ_GOV_CONSERVATIVE=y\nCONFIG_CPU_FREQ_GOV_ONDEMAND=y\nCONFIG_CPU_FREQ_GOV_PERFORMANCE=y\nCONFIG_CPU_FREQ_GOV_POWERSAVE=y\nCONFIG_CPU_FREQ_GOV_USERSPACE=y\nCONFIG_CPU_FREQ_STAT=y\nCONFIG_CPU_IDLE=y\nCONFIG_CPU_IDLE_GOV_LADDER=y\nCONFIG_CPU_IDLE_GOV_MENU=y\nCONFIG_CPU_PM=y\nCONFIG_CPU_RMAP=y\nCONFIG_CRC16=y\nCONFIG_CRYPTO_CBC=y\nCONFIG_CRYPTO_CRC32=y\nCONFIG_CRYPTO_CRC32C=y\nCONFIG_CRYPTO_CTS=y\nCONFIG_CRYPTO_DRBG=y\nCONFIG_CRYPTO_DRBG_HMAC=y\nCONFIG_CRYPTO_DRBG_MENU=y\nCONFIG_CRYPTO_ECB=y\nCONFIG_CRYPTO_HMAC=y\nCONFIG_CRYPTO_JITTERENTROPY=y\nCONFIG_CRYPTO_LIB_SHA256=y\nCONFIG_CRYPTO_RNG=y\nCONFIG_CRYPTO_RNG2=y\nCONFIG_CRYPTO_RNG_DEFAULT=y\nCONFIG_CRYPTO_SEQIV=y\nCONFIG_CRYPTO_SHA256=y\nCONFIG_CRYPTO_SHA512=y\nCONFIG_CRYPTO_XTS=y\nCONFIG_DCACHE_WORD_ACCESS=y\nCONFIG_DEBUG_BUGVERBOSE=y\nCONFIG_DEBUG_INFO=y\nCONFIG_DIMLIB=y\nCONFIG_DMABUF_HEAPS=y\nCONFIG_DMABUF_HEAPS_CMA=y\nCONFIG_DMABUF_HEAPS_SYSTEM=y\nCONFIG_DMADEVICES=y\nCONFIG_DMA_BCM2708=y\nCONFIG_DMA_BCM2835=y\nCONFIG_DMA_CMA=y\nCONFIG_DMA_DIRECT_REMAP=y\nCONFIG_DMA_ENGINE=y\nCONFIG_DMA_OF=y\nCONFIG_DMA_REMAP=y\nCONFIG_DMA_SHARED_BUFFER=y\nCONFIG_DMA_VIRTUAL_CHANNELS=y\nCONFIG_DNOTIFY=y\nCONFIG_DTC=y\nCONFIG_DUMMY_CONSOLE=y\nCONFIG_EDAC_SUPPORT=y\nCONFIG_ENABLE_MUST_CHECK=y\nCONFIG_EXT4_FS=y\nCONFIG_EXT4_FS_POSIX_ACL=y\nCONFIG_EXT4_FS_SECURITY=y\nCONFIG_EXTCON=y\nCONFIG_F2FS_FS=y\nCONFIG_FB=y\nCONFIG_FB_BCM2708=y\nCONFIG_FB_CFB_COPYAREA=y\nCONFIG_FB_CFB_FILLRECT=y\nCONFIG_FB_CFB_IMAGEBLIT=y\nCONFIG_FB_CMDLINE=y\n# CONFIG_FB_RPISENSE is not set\nCONFIG_FB_SIMPLE=y\nCONFIG_FIXED_PHY=y\nCONFIG_FIX_EARLYCON_MEM=y\n# CONFIG_FLATMEM_MANUAL is not set\nCONFIG_FONT_8x16=y\nCONFIG_FONT_8x8=y\nCONFIG_FONT_SUPPORT=y\nCONFIG_FRAMEBUFFER_CONSOLE=y\n# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set\nCONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y\nCONFIG_FRAME_POINTER=y\nCONFIG_FREEZER=y\nCONFIG_FSL_ERRATUM_A008585=y\nCONFIG_FS_ENCRYPTION=y\nCONFIG_FS_ENCRYPTION_ALGS=y\nCONFIG_FS_IOMAP=y\nCONFIG_FS_MBCACHE=y\nCONFIG_FS_POSIX_ACL=y\nCONFIG_FW_CACHE=y\nCONFIG_FW_LOADER_PAGED_BUF=y\nCONFIG_GENERIC_ALLOCATOR=y\nCONFIG_GENERIC_ARCH_TOPOLOGY=y\nCONFIG_GENERIC_BUG=y\nCONFIG_GENERIC_BUG_RELATIVE_POINTERS=y\nCONFIG_GENERIC_CLOCKEVENTS=y\nCONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y\nCONFIG_GENERIC_CPU_AUTOPROBE=y\nCONFIG_GENERIC_CPU_VULNERABILITIES=y\nCONFIG_GENERIC_CSUM=y\nCONFIG_GENERIC_EARLY_IOREMAP=y\nCONFIG_GENERIC_GETTIMEOFDAY=y\nCONFIG_GENERIC_IDLE_POLL_SETUP=y\nCONFIG_GENERIC_IRQ_CHIP=y\nCONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y\nCONFIG_GENERIC_IRQ_MIGRATION=y\nCONFIG_GENERIC_IRQ_MULTI_HANDLER=y\nCONFIG_GENERIC_IRQ_SHOW=y\nCONFIG_GENERIC_IRQ_SHOW_LEVEL=y\nCONFIG_GENERIC_MSI_IRQ=y\nCONFIG_GENERIC_MSI_IRQ_DOMAIN=y\nCONFIG_GENERIC_PCI_IOMAP=y\nCONFIG_GENERIC_PHY=y\nCONFIG_GENERIC_PINCONF=y\nCONFIG_GENERIC_PINCTRL_GROUPS=y\nCONFIG_GENERIC_PINMUX_FUNCTIONS=y\nCONFIG_GENERIC_SCHED_CLOCK=y\nCONFIG_GENERIC_SMP_IDLE_THREAD=y\nCONFIG_GENERIC_STRNCPY_FROM_USER=y\nCONFIG_GENERIC_STRNLEN_USER=y\nCONFIG_GENERIC_TIME_VSYSCALL=y\nCONFIG_GPIOLIB=y\nCONFIG_GPIOLIB_IRQCHIP=y\nCONFIG_GPIO_BCM_VIRT=y\n# CONFIG_GPIO_FSM is not set\nCONFIG_GPIO_RASPBERRYPI_EXP=y\nCONFIG_HANDLE_DOMAIN_IRQ=y\nCONFIG_HARDIRQS_SW_RESEND=y\nCONFIG_HAS_DMA=y\nCONFIG_HAS_IOMEM=y\nCONFIG_HAS_IOPORT_MAP=y\nCONFIG_HOLES_IN_ZONE=y\nCONFIG_HOTPLUG_CPU=y\nCONFIG_HW_CONSOLE=y\nCONFIG_HW_RANDOM=y\n# CONFIG_HW_RANDOM_BCM2835 is not set\nCONFIG_HW_RANDOM_IPROC_RNG200=y\nCONFIG_I2C=y\n# CONFIG_I2C_BCM2708 is not set\nCONFIG_I2C_BOARDINFO=y\n# CONFIG_I2C_BRCMSTB is not set\nCONFIG_IKCONFIG=y\nCONFIG_IKCONFIG_PROC=y\nCONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000\nCONFIG_INPUT=y\nCONFIG_INPUT_MOUSEDEV=y\n# CONFIG_INPUT_MOUSEDEV_PSAUX is not set\nCONFIG_INPUT_MOUSEDEV_SCREEN_X=1024\nCONFIG_INPUT_MOUSEDEV_SCREEN_Y=768\nCONFIG_IRQCHIP=y\nCONFIG_IRQ_DOMAIN=y\nCONFIG_IRQ_DOMAIN_HIERARCHY=y\nCONFIG_IRQ_FORCED_THREADING=y\nCONFIG_IRQ_WORK=y\nCONFIG_JBD2=y\nCONFIG_KEYS=y\nCONFIG_LEDS_GPIO=y\nCONFIG_LEDS_TRIGGER_ACTPWR=y\nCONFIG_LEDS_TRIGGER_INPUT=y\nCONFIG_LIBFDT=y\nCONFIG_LOCK_DEBUGGING_SUPPORT=y\nCONFIG_LOCK_SPIN_ON_OWNER=y\nCONFIG_LOGO=y\nCONFIG_LOGO_LINUX_CLUT224=y\n# CONFIG_LOGO_LINUX_MONO is not set\n# CONFIG_LOGO_LINUX_VGA16 is not set\nCONFIG_MAC_PARTITION=y\nCONFIG_MAGIC_SYSRQ=y\nCONFIG_MAILBOX=y\n# CONFIG_MAILBOX_TEST is not set\nCONFIG_MAX_RAW_DEVS=256\nCONFIG_MDIO_BCM_UNIMAC=y\nCONFIG_MDIO_BUS=y\nCONFIG_MDIO_DEVICE=y\nCONFIG_MDIO_DEVRES=y\nCONFIG_MEMFD_CREATE=y\nCONFIG_MEMORY_ISOLATION=y\nCONFIG_MFD_CORE=y\n# CONFIG_MFD_RPISENSE_CORE is not set\nCONFIG_MFD_SYSCON=y\nCONFIG_MIGRATION=y\nCONFIG_MMC=y\nCONFIG_MMC_BCM2835=y\nCONFIG_MMC_BCM2835_DMA=y\nCONFIG_MMC_BCM2835_MMC=y\nCONFIG_MMC_BCM2835_PIO_DMA_BARRIER=2\nCONFIG_MMC_BCM2835_SDHOST=y\nCONFIG_MMC_BLOCK=y\nCONFIG_MMC_BLOCK_MINORS=32\nCONFIG_MMC_SDHCI=y\nCONFIG_MMC_SDHCI_IO_ACCESSORS=y\nCONFIG_MMC_SDHCI_IPROC=y\n# CONFIG_MMC_SDHCI_PCI is not set\nCONFIG_MMC_SDHCI_PLTFM=y\nCONFIG_MODULES_USE_ELF_RELA=y\n# CONFIG_MTD is not set\nCONFIG_MUTEX_SPIN_ON_OWNER=y\nCONFIG_NEED_DMA_MAP_STATE=y\nCONFIG_NEED_SG_DMA_LENGTH=y\nCONFIG_NET_FLOW_LIMIT=y\nCONFIG_NLS=y\nCONFIG_NLS_ASCII=y\nCONFIG_NOP_USB_XCEIV=y\nCONFIG_NO_HZ=y\nCONFIG_NO_HZ_COMMON=y\nCONFIG_NO_HZ_IDLE=y\nCONFIG_NR_CPUS=4\nCONFIG_NVMEM=y\n# CONFIG_NVMEM_RMEM is not set\nCONFIG_OF=y\nCONFIG_OF_ADDRESS=y\nCONFIG_OF_CONFIGFS=y\nCONFIG_OF_DYNAMIC=y\nCONFIG_OF_EARLY_FLATTREE=y\nCONFIG_OF_FLATTREE=y\nCONFIG_OF_GPIO=y\nCONFIG_OF_IRQ=y\nCONFIG_OF_KOBJ=y\nCONFIG_OF_MDIO=y\nCONFIG_OF_NET=y\nCONFIG_OF_OVERLAY=y\nCONFIG_OF_RESOLVE=y\nCONFIG_PADATA=y\nCONFIG_PARTITION_PERCPU=y\nCONFIG_PCI=y\nCONFIG_PCIEAER=y\nCONFIG_PCIEPORTBUS=y\nCONFIG_PCIE_BRCMSTB=y\nCONFIG_PCIE_PME=y\nCONFIG_PCI_DOMAINS=y\nCONFIG_PCI_DOMAINS_GENERIC=y\nCONFIG_PCI_MSI=y\nCONFIG_PCI_MSI_IRQ_DOMAIN=y\nCONFIG_PGTABLE_LEVELS=3\nCONFIG_PHYLIB=y\nCONFIG_PHYS_ADDR_T_64BIT=y\nCONFIG_PINCTRL=y\nCONFIG_PINCTRL_BCM2835=y\nCONFIG_PM=y\nCONFIG_PM_CLK=y\nCONFIG_PM_GENERIC_DOMAINS=y\nCONFIG_PM_GENERIC_DOMAINS_OF=y\nCONFIG_PM_GENERIC_DOMAINS_SLEEP=y\nCONFIG_PM_OPP=y\nCONFIG_PM_SLEEP=y\nCONFIG_PM_SLEEP_SMP=y\nCONFIG_POWER_RESET=y\nCONFIG_POWER_SUPPLY=y\nCONFIG_PRINTK_TIME=y\nCONFIG_QUEUED_RWLOCKS=y\nCONFIG_QUEUED_SPINLOCKS=y\nCONFIG_RAS=y\nCONFIG_RASPBERRYPI_FIRMWARE=y\nCONFIG_RASPBERRYPI_POWER=y\nCONFIG_RATIONAL=y\n# CONFIG_RAVE_SP_CORE is not set\nCONFIG_RAW_DRIVER=y\nCONFIG_REGMAP=y\nCONFIG_REGMAP_MMIO=y\nCONFIG_REGULATOR=y\nCONFIG_REGULATOR_FIXED_VOLTAGE=y\nCONFIG_REGULATOR_GPIO=y\nCONFIG_RESET_CONTROLLER=y\nCONFIG_RESET_RASPBERRYPI=y\nCONFIG_RESET_SIMPLE=y\nCONFIG_RFS_ACCEL=y\nCONFIG_RODATA_FULL_DEFAULT_ENABLED=y\n# CONFIG_RPIVID_MEM is not set\n# CONFIG_RPI_AXIPERF is not set\n# CONFIG_RPI_POE_POWER is not set\nCONFIG_RPS=y\nCONFIG_RWSEM_SPIN_ON_OWNER=y\nCONFIG_SCSI=y\n# CONFIG_SCSI_LOWLEVEL is not set\n# CONFIG_SCSI_PROC_FS is not set\nCONFIG_SERIAL_8250_BCM2835AUX=y\n# CONFIG_SERIAL_8250_DMA is not set\nCONFIG_SERIAL_8250_EXTENDED=y\nCONFIG_SERIAL_8250_FSL=y\nCONFIG_SERIAL_8250_NR_UARTS=1\nCONFIG_SERIAL_8250_RUNTIME_UARTS=0\nCONFIG_SERIAL_8250_SHARE_IRQ=y\nCONFIG_SERIAL_AMBA_PL011=y\nCONFIG_SERIAL_AMBA_PL011_CONSOLE=y\nCONFIG_SERIAL_DEV_BUS=y\n# CONFIG_SERIAL_DEV_CTRL_TTYPORT is not set\nCONFIG_SERIAL_MCTRL_GPIO=y\nCONFIG_SERIAL_OF_PLATFORM=y\nCONFIG_SG_POOL=y\nCONFIG_SMP=y\n# CONFIG_SND_SOC_AD193X_I2C is not set\n# CONFIG_SND_SOC_AD193X_SPI is not set\nCONFIG_SPARSEMEM=y\nCONFIG_SPARSEMEM_EXTREME=y\nCONFIG_SPARSEMEM_MANUAL=y\nCONFIG_SPARSEMEM_VMEMMAP=y\nCONFIG_SPARSEMEM_VMEMMAP_ENABLE=y\nCONFIG_SPARSE_IRQ=y\nCONFIG_SRCU=y\n# CONFIG_STRIP_ASM_SYMS is not set\nCONFIG_SUSPEND=y\nCONFIG_SUSPEND_FREEZER=y\nCONFIG_SWIOTLB=y\nCONFIG_SWPHY=y\nCONFIG_SYSCTL_EXCEPTION_TRACE=y\nCONFIG_SYS_SUPPORTS_HUGETLBFS=y\n# CONFIG_TEXTSEARCH is not set\nCONFIG_THERMAL=y\nCONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y\nCONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0\nCONFIG_THERMAL_GOV_STEP_WISE=y\nCONFIG_THERMAL_OF=y\nCONFIG_THERMAL_WRITABLE_TRIPS=y\nCONFIG_THREAD_INFO_IN_TASK=y\nCONFIG_TICK_CPU_ACCOUNTING=y\nCONFIG_TIMER_OF=y\nCONFIG_TIMER_PROBE=y\nCONFIG_TMPFS_POSIX_ACL=y\nCONFIG_TREE_RCU=y\nCONFIG_TREE_SRCU=y\nCONFIG_UEVENT_HELPER_PATH=\"\"\nCONFIG_UNMAP_KERNEL_AT_EL0=y\nCONFIG_USB=y\nCONFIG_USB_ANNOUNCE_NEW_DEVICES=y\nCONFIG_USB_COMMON=y\nCONFIG_USB_DWCOTG=y\nCONFIG_USB_GADGET=y\nCONFIG_USB_PCI=y\nCONFIG_USB_PHY=y\nCONFIG_USB_STORAGE=y\nCONFIG_USB_SUPPORT=y\nCONFIG_USB_UAS=y\n# CONFIG_USB_UHCI_HCD is not set\nCONFIG_USB_XHCI_HCD=y\nCONFIG_USB_XHCI_PCI=y\nCONFIG_USB_XHCI_PLATFORM=y\nCONFIG_VMAP_STACK=y\nCONFIG_VT=y\nCONFIG_VT_CONSOLE=y\nCONFIG_VT_CONSOLE_SLEEP=y\nCONFIG_VT_HW_CONSOLE_BINDING=y\nCONFIG_WATCHDOG_CORE=y\nCONFIG_XPS=y\nCONFIG_XZ_DEC_ARM=y\nCONFIG_XZ_DEC_BCJ=y\nCONFIG_ZONE_DMA32=y\n"
  },
  {
    "path": "target/linux/bcm27xx/bcm2711/target.mk",
    "content": "#\n# Copyright (C) 2019 OpenWrt.org\n#\n\nARCH:=aarch64\nSUBTARGET:=bcm2711\nBOARDNAME:=BCM2711 boards (64 bit)\nCPU_TYPE:=cortex-a72\n\ndefine Target/Description\n\tBuild firmware image for BCM2711 devices.\n\tThis firmware features a 64 bit kernel.\nendef\n"
  },
  {
    "path": "target/linux/bcm27xx/image/Makefile",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2012-2019 OpenWrt.org\n# Copyright (C) 2016-2017 LEDE project\n\ninclude $(TOPDIR)/rules.mk\ninclude $(INCLUDE_DIR)/image.mk\n\nFAT32_BLOCK_SIZE=1024\nFAT32_BLOCKS=$(shell echo $$(($(CONFIG_TARGET_KERNEL_PARTSIZE)*1024*1024/$(FAT32_BLOCK_SIZE))))\n\ndefine Build/Compile\n\t$(CP) $(LINUX_DIR)/COPYING $(KDIR)/COPYING.linux\nendef\n\n### Image scripts ###\ndefine Build/boot-common\n\trm -f $@.boot\n\tmkfs.fat -n boot -C $@.boot $(FAT32_BLOCKS)\n\tmcopy -i $@.boot $(KDIR)/COPYING.linux ::\n\tmcopy -i $@.boot $(KDIR)/LICENCE.broadcom ::\n\tmcopy -i $@.boot cmdline.txt ::\n\tmcopy -i $@.boot config.txt ::\n\tmcopy -i $@.boot distroconfig.txt ::\n\tmcopy -i $@.boot $(IMAGE_KERNEL) ::$(KERNEL_IMG)\n\t$(foreach dts,$(shell echo $(DEVICE_DTS)),mcopy -i $@.boot $(DTS_DIR)/$(dts).dtb ::;)\n\tmmd -i $@.boot ::/overlays\n\tmcopy -i $@.boot $(DTS_DIR)/overlays/*.dtbo ::/overlays/\n\tmcopy -i $@.boot $(DTS_DIR)/overlays/README ::/overlays/\nendef\n\ndefine Build/boot-2708\n\tmcopy -i $@.boot $(KDIR)/bootcode.bin ::\n\tmcopy -i $@.boot $(KDIR)/start.elf ::\n\tmcopy -i $@.boot $(KDIR)/start_cd.elf ::\n\tmcopy -i $@.boot $(KDIR)/start_x.elf ::\n\tmcopy -i $@.boot $(KDIR)/fixup.dat ::\n\tmcopy -i $@.boot $(KDIR)/fixup_cd.dat ::\n\tmcopy -i $@.boot $(KDIR)/fixup_x.dat ::\nendef\n\ndefine Build/boot-2711\n\tmcopy -i $@.boot $(KDIR)/start4.elf ::\n\tmcopy -i $@.boot $(KDIR)/start4cd.elf ::\n\tmcopy -i $@.boot $(KDIR)/start4x.elf ::\n\tmcopy -i $@.boot $(KDIR)/fixup4.dat ::\n\tmcopy -i $@.boot $(KDIR)/fixup4cd.dat ::\n\tmcopy -i $@.boot $(KDIR)/fixup4x.dat ::\nendef\n\ndefine Build/sdcard-img\n\t./gen_rpi_sdcard_img.sh $@ $@.boot $(IMAGE_ROOTFS) \\\n\t\t$(CONFIG_TARGET_KERNEL_PARTSIZE) $(CONFIG_TARGET_ROOTFS_PARTSIZE)\nendef\n\n### Devices ###\ndefine Device/Default\n  DEVICE_VENDOR := Raspberry Pi\n  KERNEL := kernel-bin\n  KERNEL_IMG := kernel.img\n  IMAGES := factory.img.gz sysupgrade.img.gz\n  IMAGE/sysupgrade.img.gz := boot-common | boot-2708 | sdcard-img | gzip | append-metadata\n  IMAGE/factory.img.gz := boot-common | boot-2708 | sdcard-img | gzip\nendef\n\ndefine Device/rpi\n  DEVICE_MODEL := B/B+/CM/Zero/ZeroW\n  DEVICE_DTS := \\\n\tbcm2708-rpi-b bcm2708-rpi-b-rev1 bcm2708-rpi-b-plus \\\n\tbcm2708-rpi-cm \\\n\tbcm2708-rpi-zero bcm2708-rpi-zero-w\n  SUPPORTED_DEVICES := \\\n\trpi-b rpi-b-plus rpi-cm rpi-zero rpi-zero-w \\\n\traspberrypi,model-b raspberrypi,model-b-plus raspberrypi,model-b-rev2 \\\n\traspberrypi,compute-module raspberrypi,compute-module-1 \\\n\traspberrypi,model-zero raspberrypi,model-zero-w\n  DEVICE_PACKAGES := \\\n\tcypress-firmware-43430-sdio \\\n\tcypress-nvram-43430-sdio-rpi-zero-w \\\n\tkmod-brcmfmac wpad-basic-wolfssl\nendef\nifeq ($(SUBTARGET),bcm2708)\n  TARGET_DEVICES += rpi\nendif\n\ndefine Device/rpi-2\n  DEVICE_MODEL := 2B/2B 1.2\n  DEVICE_VARIANT := (32bit)\n  DEVICE_ALT0_VENDOR := Raspberry Pi\n  DEVICE_ALT0_MODEL := 3B/3B+/3CM\n  DEVICE_ALT0_VARIANT := (32bit)\n  DEVICE_ALT1_VENDOR := Raspberry Pi\n  DEVICE_ALT1_MODEL := 4B/400/4CM\n  DEVICE_ALT1_VARIANT := (32bit)\n  DEVICE_DTS := \\\n\tbcm2709-rpi-2-b bcm2710-rpi-2-b \\\n\tbcm2710-rpi-3-b bcm2710-rpi-3-b-plus \\\n\tbcm2711-rpi-4-b bcm2711-rpi-400 \\\n\tbcm2710-rpi-cm3 bcm2711-rpi-cm4\n  SUPPORTED_DEVICES := \\\n\trpi-2-b rpi-3-b rpi-3-b-plus rpi-cm \\\n\traspberrypi,2-model-b raspberrypi,2-model-b-rev2 \\\n\traspberrypi,3-model-b raspberrypi,3-model-b-plus \\\n\traspberrypi,3-compute-module raspberrypi,compute-module-3 \\\n\traspberrypi,400 raspberrypi,4-compute-module raspberrypi,4-model-b\n  DEVICE_PACKAGES := \\\n\tcypress-firmware-43430-sdio \\\n\tcypress-nvram-43430-sdio-rpi-3b \\\n\tcypress-firmware-43455-sdio \\\n\tcypress-nvram-43455-sdio-rpi-3b-plus cypress-nvram-43455-sdio-rpi-4b \\\n\tkmod-brcmfmac wpad-basic-wolfssl\n  IMAGE/sysupgrade.img.gz := boot-common | boot-2708 | boot-2711 | sdcard-img | gzip | append-metadata\n  IMAGE/factory.img.gz := boot-common | boot-2708 | boot-2711 | sdcard-img | gzip\nendef\nifeq ($(SUBTARGET),bcm2709)\n  TARGET_DEVICES += rpi-2\nendif\n\ndefine Device/rpi-3\n  DEVICE_MODEL := 3B/3B+/3CM\n  DEVICE_VARIANT := (64bit)\n  DEVICE_ALT0_VENDOR := Raspberry Pi\n  DEVICE_ALT0_MODEL := 2B-1.2\n  DEVICE_ALT0_VARIANT := (64bit)\n  KERNEL_IMG := kernel8.img\n  DEVICE_DTS := \\\n\tbroadcom/bcm2710-rpi-2-b \\\n\tbroadcom/bcm2710-rpi-3-b broadcom/bcm2710-rpi-3-b-plus \\\n\tbroadcom/bcm2710-rpi-cm3\n  SUPPORTED_DEVICES := \\\n\trpi-3-b rpi-3-b-plus \\\n\traspberrypi,2-model-b-rev2 \\\n\traspberrypi,3-model-b raspberrypi,3-model-b-plus \\\n\traspberrypi,3-compute-module raspberrypi,compute-module-3\n  DEVICE_PACKAGES := \\\n\tcypress-firmware-43430-sdio \\\n\tcypress-nvram-43430-sdio-rpi-3b \\\n\tcypress-firmware-43455-sdio \\\n\tcypress-nvram-43455-sdio-rpi-3b-plus \\\n\tkmod-brcmfmac wpad-basic-wolfssl\nendef\nifeq ($(SUBTARGET),bcm2710)\n  TARGET_DEVICES += rpi-3\nendif\n\ndefine Device/rpi-4\n  DEVICE_MODEL := 4B/400/4CM\n  DEVICE_VARIANT := (64bit)\n  KERNEL_IMG := kernel8.img\n  DEVICE_DTS := \\\n\tbroadcom/bcm2711-rpi-400 \\\n\tbroadcom/bcm2711-rpi-4-b \\\n\tbroadcom/bcm2711-rpi-cm4\n  SUPPORTED_DEVICES := \\\n\traspberrypi,400 \\\n\traspberrypi,4-compute-module \\\n\traspberrypi,4-model-b\n  DEVICE_PACKAGES := \\\n\tcypress-firmware-43455-sdio \\\n\tcypress-nvram-43455-sdio-rpi-4b \\\n\tkmod-brcmfmac wpad-basic-wolfssl \\\n\tkmod-usb-net-lan78xx\n  IMAGE/sysupgrade.img.gz := boot-common | boot-2711 | sdcard-img | gzip | append-metadata\n  IMAGE/factory.img.gz := boot-common | boot-2711 | sdcard-img | gzip\nendef\nifeq ($(SUBTARGET),bcm2711)\n  TARGET_DEVICES += rpi-4\nendif\n\n$(eval $(call BuildImage))\n"
  },
  {
    "path": "target/linux/bcm27xx/image/cmdline.txt",
    "content": "console=serial0,115200 console=tty1 root=/dev/mmcblk0p2 rootfstype=squashfs,ext4 rootwait\n"
  },
  {
    "path": "target/linux/bcm27xx/image/config.txt",
    "content": "################################################################################\n# Bootloader configuration - config.txt\n################################################################################\n\n################################################################################\n# For overclocking and various other settings, see:\n# https://www.raspberrypi.org/documentation/configuration/config-txt/README.md\n################################################################################\n\n# OpenWrt config\ninclude distroconfig.txt\n\n[all]\n# Place your custom settings here.\n"
  },
  {
    "path": "target/linux/bcm27xx/image/distroconfig.txt",
    "content": "################################################################################\n# Bootloader configuration - distroconfig.txt\n################################################################################\n\n# Restore PL011 (ttyAMA0) to GPIOs 14 & 15, instead of Mini UART (ttyS0).\n# Mini UART is disabled by default unless \"enable_uart=1\" is specified,\n#  which changes the core frequency to a fixed value and impacts performance.\n# See https://www.raspberrypi.org/documentation/configuration/uart.md\n[pi0w]\ndtoverlay=disable-bt\n[pi3]\ndtoverlay=disable-bt\n[pi4]\ndtoverlay=disable-bt\n# Run as fast as firmware / board allows\narm_boost=1\n"
  },
  {
    "path": "target/linux/bcm27xx/image/gen_rpi_sdcard_img.sh",
    "content": "#!/bin/sh\n\nset -x\n[ $# -eq 5 ] || {\n    echo \"SYNTAX: $0 <file> <bootfs image> <rootfs image> <bootfs size> <rootfs size>\"\n    exit 1\n}\n\nOUTPUT=\"$1\"\nBOOTFS=\"$2\"\nROOTFS=\"$3\"\nBOOTFSSIZE=\"$4\"\nROOTFSSIZE=\"$5\"\n\nhead=4\nsect=63\n\nset $(ptgen -o $OUTPUT -h $head -s $sect -l 4096 -t c -p ${BOOTFSSIZE}M -t 83 -p ${ROOTFSSIZE}M)\n\nBOOTOFFSET=\"$(($1 / 512))\"\nBOOTSIZE=\"$(($2 / 512))\"\nROOTFSOFFSET=\"$(($3 / 512))\"\nROOTFSSIZE=\"$(($4 / 512))\"\n\ndd bs=512 if=\"$BOOTFS\" of=\"$OUTPUT\" seek=\"$BOOTOFFSET\" conv=notrunc\ndd bs=512 if=\"$ROOTFS\" of=\"$OUTPUT\" seek=\"$ROOTFSOFFSET\" conv=notrunc\n\n\n\n"
  },
  {
    "path": "target/linux/bcm27xx/modules/hwmon.mk",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2019 OpenWrt.org\n\ndefine KernelPackage/hwmon-raspberrypi\n  TITLE:=Raspberry Pi voltage monitor\n  KCONFIG:=CONFIG_SENSORS_RASPBERRYPI_HWMON\n  FILES:=$(LINUX_DIR)/drivers/hwmon/raspberrypi-hwmon.ko\n  AUTOLOAD:=$(call AutoLoad,60,raspberrypi-hwmon)\n  $(call AddDepends/hwmon,@TARGET_bcm27xx)\nendef\n\ndefine KernelPackage/hwmon-raspberrypi/description\n  Kernel module for voltage sensor on the Raspberry Pi\nendef\n\n$(eval $(call KernelPackage,hwmon-raspberrypi))\n\n\ndefine KernelPackage/hwmon-rpi-poe-fan\n  SUBMENU:=$(HWMON_MENU)\n  TITLE:=Raspberry Pi PoE HAT fan\n  DEPENDS:=@TARGET_bcm27xx +kmod-hwmon-core\n  KCONFIG:=CONFIG_SENSORS_RPI_POE_FAN\n  FILES:=$(LINUX_DIR)/drivers/hwmon/rpi-poe-fan.ko\n  AUTOLOAD:=$(call AutoProbe,rpi-poe-fan)\nendef\n\ndefine KernelPackage/hwmon-rpi-poe-fan/description\n  Raspberry Pi PoE HAT fan driver\nendef\n\n$(eval $(call KernelPackage,hwmon-rpi-poe-fan))\n"
  },
  {
    "path": "target/linux/bcm27xx/modules/i2c.mk",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2019 OpenWrt.org\n\nI2C_BCM2835_MODULES:=\\\n  CONFIG_I2C_BCM2835:drivers/i2c/busses/i2c-bcm2835\n\ndefine KernelPackage/i2c-bcm2835\n  $(call i2c_defaults,$(I2C_BCM2835_MODULES),59)\n  TITLE:=Broadcom BCM2835 I2C master controller driver\n  DEPENDS:=@TARGET_bcm27xx +kmod-i2c-core\nendef\n\ndefine KernelPackage/i2c-bcm2835/description\n  This package contains the Broadcom 2835 I2C master controller driver\nendef\n\n$(eval $(call KernelPackage,i2c-bcm2835))\n"
  },
  {
    "path": "target/linux/bcm27xx/modules/other.mk",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2019 OpenWrt.org\n\ndefine KernelPackage/pwm-bcm2835\n  SUBMENU:=$(OTHER_MENU)\n  TITLE:=BCM2835 PWM driver\n  KCONFIG:= \\\n    CONFIG_PWM=y \\\n    CONFIG_PWM_BCM2835\n  FILES:=$(LINUX_DIR)/drivers/pwm/pwm-bcm2835.ko\n  AUTOLOAD:=$(call AutoLoad,60,pwm-bcm2835)\n  DEPENDS:=@TARGET_bcm27xx\nendef\n\ndefine KernelPackage/pwm-bcm2835/description\n  This package contains the PWM framework driver for BCM2835 controller (Raspberry Pi)\nendef\n\n$(eval $(call KernelPackage,pwm-bcm2835))\n\n\ndefine KernelPackage/smi-bcm2835\n  SUBMENU:=$(OTHER_MENU)\n  TITLE:=BCM2835 SMI driver\n  KCONFIG:=CONFIG_BCM2835_SMI\n  FILES:=$(LINUX_DIR)/drivers/misc/bcm2835_smi.ko\n  AUTOLOAD:=$(call AutoLoad,20,bcm2835_smi)\n  DEPENDS:=@TARGET_bcm27xx\nendef\n\ndefine KernelPackage/smi-bcm2835/description\n  This package contains the Character device driver for Broadcom Secondary\n  Memory Interface\nendef\n\n$(eval $(call KernelPackage,smi-bcm2835))\n\n\ndefine KernelPackage/smi-bcm2835-dev\n  SUBMENU:=$(OTHER_MENU)\n  TITLE:=BCM2835 SMI device driver\n  KCONFIG:=CONFIG_BCM2835_SMI_DEV\n  FILES:=$(LINUX_DIR)/drivers/char/broadcom/bcm2835_smi_dev.ko\n  AUTOLOAD:=$(call AutoLoad,21,bcm2835_smi_dev)\n  DEPENDS:=@TARGET_bcm27xx +kmod-smi-bcm2835\nendef\n\ndefine KernelPackage/smi-bcm2835-dev/description\n  This driver provides a character device interface (ioctl + read/write) to\n  Broadcom's Secondary Memory interface. The low-level functionality is provided\n  by the SMI driver itself.\nendef\n\n$(eval $(call KernelPackage,smi-bcm2835-dev))\n"
  },
  {
    "path": "target/linux/bcm27xx/modules/sound.mk",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2019 OpenWrt.org\n\ndefine KernelPackage/sound-arm-bcm2835\n  TITLE:=BCM2835 ALSA driver\n  KCONFIG:= \\\n    CONFIG_SND_ARM=y \\\n    CONFIG_SND_BCM2835 \\\n    CONFIG_SND_ARMAACI=n\n  FILES:= \\\n    $(LINUX_DIR)/drivers/staging/vc04_services/bcm2835-audio/snd-bcm2835.ko\n  AUTOLOAD:=$(call AutoLoad,68,snd-bcm2835)\n  DEPENDS:=@TARGET_bcm27xx\n  $(call AddDepends/sound)\nendef\n\ndefine KernelPackage/sound-arm-bcm2835/description\n  This package contains the BCM2835 ALSA pcm card driver\nendef\n\n$(eval $(call KernelPackage,sound-arm-bcm2835))\n\n\ndefine KernelPackage/sound-soc-bcm2835-i2s\n  TITLE:=SoC Audio support for the Broadcom 2835 I2S module\n  KCONFIG:= \\\n    CONFIG_SND_BCM2835_SOC_I2S \\\n    CONFIG_SND_SOC_DMAENGINE_PCM=y \\\n    CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y\n  FILES:= \\\n    $(LINUX_DIR)/sound/soc/bcm/snd-soc-bcm2835-i2s.ko\n  AUTOLOAD:=$(call AutoLoad,68,snd-soc-bcm2835-i2s)\n  DEPENDS:=@TARGET_bcm27xx +kmod-sound-soc-core\n  $(call AddDepends/sound)\nendef\n\ndefine KernelPackage/sound-soc-bcm2835-i2s/description\n  This package contains support for codecs attached to the Broadcom 2835 I2S interface\nendef\n\n$(eval $(call KernelPackage,sound-soc-bcm2835-i2s))\n\n\ndefine KernelPackage/sound-soc-rpi-simple-soundcard\n  TITLE:=Support for Raspberry Pi simple soundcards\n  KCONFIG:= \\\n    CONFIG_SND_RPI_SIMPLE_SOUNDCARD\n  FILES:= \\\n    $(LINUX_DIR)/sound/soc/bcm/snd-soc-rpi-simple-soundcard.ko\n  AUTOLOAD:=$(call AutoLoad,68,snd-soc-rpi-simple-soundcard)\n  DEPENDS:= \\\n    kmod-sound-soc-bcm2835-i2s\n  $(call AddDepends/sound)\nendef\n\ndefine KernelPackage/sound-soc-rpi-simple-soundcard/description\n  This package contains support for Raspbery Pi simple soundcards\nendef\n\n$(eval $(call KernelPackage,sound-soc-rpi-simple-soundcard))\n\n\ndefine KernelPackage/sound-soc-rpi-wm8804-soundcard\n  TITLE:=Support for Raspberry Pi generic WM8804 soundcards\n  KCONFIG:= \\\n    CONFIG_SND_RPI_WM8804_SOUNDCARD\n  FILES:= \\\n    $(LINUX_DIR)/sound/soc/bcm/snd-soc-rpi-wm8804-soundcard.ko\n  AUTOLOAD:=$(call AutoLoad,68,snd-soc-rpi-wm8804-soundcard)\n  DEPENDS:= \\\n    kmod-sound-soc-bcm2835-i2s\n  $(call AddDepends/sound)\nendef\n\ndefine KernelPackage/sound-soc-rpi-wm8804-soundcard/description\n  This package contains support for Raspbery Pi simple soundcards\nendef\n\n$(eval $(call KernelPackage,sound-soc-rpi-wm8804-soundcard))\n\n\ndefine KernelPackage/sound-soc-adau1977-adc\n  TITLE:=Support for ADAU1977 ADC\n  KCONFIG:= \\\n    CONFIG_SND_BCM2708_SOC_ADAU1977_ADC \\\n    CONFIG_SND_SOC_ADAU1977 \\\n    CONFIG_SND_SOC_ADAU1977_I2C\n  FILES:= \\\n    $(LINUX_DIR)/sound/soc/codecs/snd-soc-adau1977.ko \\\n    $(LINUX_DIR)/sound/soc/codecs/snd-soc-adau1977-i2c.ko\n  AUTOLOAD:=$(call AutoLoad,68,snd-soc-adau1977 snd-soc-adau1977-i2c)\n  DEPENDS:= \\\n    kmod-sound-soc-bcm2835-i2s \\\n    +kmod-sound-soc-rpi-simple-soundcard \\\n    +kmod-i2c-bcm2835 \\\n    +kmod-regmap-i2c\n  $(call AddDepends/sound)\nendef\n\ndefine KernelPackage/sound-soc-adau1977-adc/description\n  This package contains support for ADAU1977 ADC\nendef\n\n$(eval $(call KernelPackage,sound-soc-adau1977-adc))\n\n\ndefine KernelPackage/sound-soc-allo-boss-dac\n  TITLE:=Support for Allo Boss DAC\n  KCONFIG:= \\\n    CONFIG_SND_BCM2708_SOC_ALLO_BOSS_DAC \\\n    CONFIG_SND_SOC_PCM512x \\\n    CONFIG_SND_SOC_PCM512x_I2C\n  FILES:= \\\n    $(LINUX_DIR)/sound/soc/bcm/snd-soc-allo-boss-dac.ko \\\n    $(LINUX_DIR)/sound/soc/codecs/snd-soc-pcm512x.ko \\\n    $(LINUX_DIR)/sound/soc/codecs/snd-soc-pcm512x-i2c.ko\n  AUTOLOAD:=$(call AutoLoad,68,snd-soc-pcm512x-i2c snd-soc-pcm512x \\\n    snd-soc-allo-boss-dac)\n  DEPENDS:= \\\n    kmod-sound-soc-bcm2835-i2s \\\n    +kmod-i2c-bcm2835 \\\n    +kmod-regmap-i2c\n  $(call AddDepends/sound)\nendef\n\ndefine KernelPackage/sound-soc-allo-boss-dac/description\n  This package contains support for Allo Boss DAC\nendef\n\n$(eval $(call KernelPackage,sound-soc-allo-boss-dac))\n\n\ndefine KernelPackage/sound-soc-allo-boss2-dac\n  TITLE:=Support for Allo Boss2 DAC\n  KCONFIG:= \\\n    CONFIG_SND_AUDIO_GRAPH_CARD \\\n    CONFIG_SND_BCM2708_SOC_ALLO_BOSS2_DAC\n  FILES:= \\\n    $(LINUX_DIR)/sound/soc/bcm/snd-soc-allo-boss2-dac.ko\n  AUTOLOAD:=$(call AutoLoad,68,snd-soc-allo-boss2-dac)\n  DEPENDS:= \\\n    kmod-sound-soc-bcm2835-i2s \\\n    +kmod-i2c-bcm2835 \\\n    +kmod-regmap-i2c\n  $(call AddDepends/sound)\nendef\n\ndefine KernelPackage/sound-soc-allo-boss2-dac/description\n  This package contains support for Allo Boss2 DAC\nendef\n\n$(eval $(call KernelPackage,sound-soc-allo-boss2-dac))\n\n\ndefine KernelPackage/sound-soc-allo-digione\n  TITLE:=Support for Allo Piano DigiOne\n  KCONFIG:= \\\n    CONFIG_SND_BCM2708_SOC_ALLO_DIGIONE \\\n    CONFIG_SND_SOC_WM8804 \\\n    CONFIG_SND_SOC_WM8804_I2C\n  FILES:= \\\n    $(LINUX_DIR)/sound/soc/codecs/snd-soc-wm8804.ko \\\n    $(LINUX_DIR)/sound/soc/codecs/snd-soc-wm8804-i2c.ko\n  AUTOLOAD:=$(call AutoLoad,68,snd-soc-wm8804-i2c snd-soc-wm8804 \\\n    snd-soc-allo-digione)\n  DEPENDS:= \\\n    kmod-sound-soc-bcm2835-i2s \\\n    +kmod-sound-soc-rpi-wm8804-soundcard \\\n    +kmod-i2c-bcm2835 \\\n    +kmod-regmap-i2c\n  $(call AddDepends/sound)\nendef\n\ndefine KernelPackage/sound-soc-allo-digione/description\n  This package contains support for Allo DigiOne\nendef\n\n$(eval $(call KernelPackage,sound-soc-allo-digione))\n\n\ndefine KernelPackage/sound-soc-allo-piano-dac\n  TITLE:=Support for Allo Piano DAC\n  KCONFIG:= \\\n    CONFIG_SND_BCM2708_SOC_ALLO_PIANO_DAC \\\n    CONFIG_SND_SOC_PCM512x \\\n    CONFIG_SND_SOC_PCM512x_I2C\n  FILES:= \\\n    $(LINUX_DIR)/sound/soc/bcm/snd-soc-allo-piano-dac.ko \\\n    $(LINUX_DIR)/sound/soc/codecs/snd-soc-pcm512x.ko \\\n    $(LINUX_DIR)/sound/soc/codecs/snd-soc-pcm512x-i2c.ko\n  AUTOLOAD:=$(call AutoLoad,68,snd-soc-pcm512x-i2c snd-soc-pcm512x \\\n    snd-soc-allo-piano-dac)\n  DEPENDS:= \\\n    kmod-sound-soc-bcm2835-i2s \\\n    +kmod-i2c-bcm2835 \\\n    +kmod-regmap-i2c\n  $(call AddDepends/sound)\nendef\n\ndefine KernelPackage/sound-soc-allo-piano-dac/description\n  This package contains support for Allo Piano DAC\nendef\n\n$(eval $(call KernelPackage,sound-soc-allo-piano-dac))\n\n\ndefine KernelPackage/sound-soc-allo-piano-dac-plus\n  TITLE:=Support for Allo Piano DAC Plus\n  KCONFIG:= \\\n    CONFIG_SND_BCM2708_SOC_ALLO_PIANO_DAC_PLUS \\\n    CONFIG_SND_SOC_PCM512x \\\n    CONFIG_SND_SOC_PCM512x_I2C\n  FILES:= \\\n    $(LINUX_DIR)/sound/soc/bcm/snd-soc-allo-piano-dac-plus.ko \\\n    $(LINUX_DIR)/sound/soc/codecs/snd-soc-pcm512x.ko \\\n    $(LINUX_DIR)/sound/soc/codecs/snd-soc-pcm512x-i2c.ko\n  AUTOLOAD:=$(call AutoLoad,68,snd-soc-pcm512x-i2c snd-soc-pcm512x \\\n    snd-soc-allo-piano-dac-plus)\n  DEPENDS:= \\\n    kmod-sound-soc-bcm2835-i2s \\\n    +kmod-i2c-bcm2835 \\\n    +kmod-regmap-i2c\n  $(call AddDepends/sound)\nendef\n\ndefine KernelPackage/sound-soc-allo-piano-dac-plus/description\n  This package contains support for Allo Piano DAC Plus\nendef\n\n$(eval $(call KernelPackage,sound-soc-allo-piano-dac-plus))\n\n\ndefine KernelPackage/sound-soc-audiosense-pi\n  TITLE:=Support for AudioSense Add-On Soundcard\n  KCONFIG:= \\\n    CONFIG_SND_AUDIOSENSE_PI \\\n    CONFIG_SND_SOC_TLV320AIC32X4 \\\n    CONFIG_SND_SOC_TLV320AIC32X4_I2C\n  FILES:= \\\n    $(LINUX_DIR)/sound/soc/bcm/snd-soc-audiosense-pi.ko \\\n    $(LINUX_DIR)/sound/soc/codecs/snd-soc-tlv320aic32x4.ko \\\n    $(LINUX_DIR)/sound/soc/codecs/snd-soc-tlv320aic32x4-i2c.ko\n  AUTOLOAD:=$(call AutoLoad,68,snd-soc-tlv320aic32x4-i2c snd-soc-tlv320aic32x4 \\\n    snd-soc-audiosense-pi)\n  DEPENDS:= \\\n    kmod-sound-soc-bcm2835-i2s \\\n    +kmod-i2c-bcm2835 \\\n    +kmod-regmap-i2c\n  $(call AddDepends/sound)\nendef\n\ndefine KernelPackage/sound-soc-audiosense-pi/description\n  This package contains support for AudioSense Add-On Soundcard\nendef\n\n$(eval $(call KernelPackage,sound-soc-audiosense-pi))\n\n\ndefine KernelPackage/sound-soc-allo-katana-codec\n  TITLE:=Support for Allo Katana DAC\n  KCONFIG:= \\\n    CONFIG_SND_AUDIO_GRAPH_CARD \\\n    CONFIG_SND_BCM2708_SOC_ALLO_KATANA_DAC \\\n    CONFIG_SND_SOC_PCM512x \\\n    CONFIG_SND_SOC_PCM512x_I2C \\\n    CONFIG_SND_SIMPLE_CARD_UTILS\n  FILES:= \\\n    $(LINUX_DIR)/sound/soc/bcm/snd-soc-allo-katana-codec.ko \\\n    $(LINUX_DIR)/sound/soc/codecs/snd-soc-pcm512x.ko \\\n    $(LINUX_DIR)/sound/soc/codecs/snd-soc-pcm512x-i2c.ko\n  AUTOLOAD:=$(call AutoLoad,68,snd-soc-pcm512x-i2c snd-soc-pcm512x \\\n    snd-soc-allo-katana-codec)\n  DEPENDS:= \\\n    kmod-sound-soc-bcm2835-i2s \\\n    +kmod-i2c-bcm2835 \\\n    +kmod-regmap-i2c\n  $(call AddDepends/sound)\nendef\n\ndefine KernelPackage/sound-soc-allo-katana-codec/description\n  This package contains support for Allo Katana DAC\nendef\n\n$(eval $(call KernelPackage,sound-soc-allo-katana-codec))\n\n\ndefine KernelPackage/sound-soc-audioinjector-isolated-soundcard\n  TITLE:=Support for AudioInjector Isolated soundcard\n  KCONFIG:= \\\n    CONFIG_SND_AUDIOINJECTOR_ISOLATED_SOUNDCARD \\\n    CONFIG_SND_SOC_CS4271 \\\n    CONFIG_SND_SOC_CS4271_I2C\n  FILES:= \\\n    $(LINUX_DIR)/sound/soc/bcm/snd-soc-audioinjector-isolated-soundcard.ko \\\n    $(LINUX_DIR)/sound/soc/codecs/snd-soc-wm8731.ko\n  AUTOLOAD:=$(call AutoLoad,68,snd-soc-cs4271.o \\\n    snd-soc-cs4271-i2c \\\n    snd-soc-audioinjector-isolated-soundcard)\n  DEPENDS:= \\\n    kmod-sound-soc-bcm2835-i2s \\\n    +kmod-i2c-bcm2835 \\\n    +kmod-regmap-i2c \\\n    +kmod-regmap-spi\n  $(call AddDepends/sound)\nendef\n\ndefine KernelPackage/sound-soc-audioinjector-isolated-soundcard/description\n  This package contains support for AudioInjector Isolated soundcard\nendef\n\n$(eval $(call KernelPackage,sound-soc-audioinjector-isolated-soundcard))\n\n\ndefine KernelPackage/sound-soc-audioinjector-octo-soundcard\n  TITLE:=Support for AudioInjector Octo soundcard\n  KCONFIG:= \\\n    CONFIG_SND_AUDIOINJECTOR_OCTO_SOUNDCARD \\\n    CONFIG_SND_SOC_CS42XX8 \\\n    CONFIG_SND_SOC_CS42XX8_I2C\n  FILES:= \\\n    $(LINUX_DIR)/sound/soc/bcm/snd-soc-audioinjector-octo-soundcard.ko \\\n    $(LINUX_DIR)/sound/soc/codecs/snd-soc-cs42xx8.ko \\\n    $(LINUX_DIR)/sound/soc/codecs/snd-soc-cs42xx8-i2c.ko\n  AUTOLOAD:=$(call AutoLoad,68,snd-soc- \\\n    snd-soc-audioinjector-octo-soundcard)\n  DEPENDS:= \\\n    kmod-sound-soc-bcm2835-i2s \\\n    +kmod-i2c-bcm2835 \\\n    +kmod-regmap-i2c\n  $(call AddDepends/sound)\nendef\n\ndefine KernelPackage/sound-soc-audioinjector-octo-soundcard/description\n  This package contains support for AudioInjector Octo soundcard\nendef\n\n$(eval $(call KernelPackage,sound-soc-audioinjector-octo-soundcard))\n\n\ndefine KernelPackage/sound-soc-audioinjector-pi-soundcard\n  TITLE:=Support for AudioInjector Pi soundcard\n  KCONFIG:= \\\n    CONFIG_SND_AUDIOINJECTOR_PI_SOUNDCARD \\\n    CONFIG_SND_SOC_WM8731\n  FILES:= \\\n    $(LINUX_DIR)/sound/soc/bcm/snd-soc-audioinjector-pi-soundcard.ko \\\n    $(LINUX_DIR)/sound/soc/codecs/snd-soc-wm8731.ko\n  AUTOLOAD:=$(call AutoLoad,68,snd-soc-wm8731 \\\n    snd-soc-audioinjector-pi-soundcard)\n  DEPENDS:= \\\n    kmod-sound-soc-bcm2835-i2s \\\n    +kmod-i2c-bcm2835 \\\n    +kmod-regmap-i2c \\\n    +kmod-regmap-spi\n  $(call AddDepends/sound)\nendef\n\ndefine KernelPackage/sound-soc-audioinjector-pi-soundcard/description\n  This package contains support for AudioInjector Pi soundcard\nendef\n\n$(eval $(call KernelPackage,sound-soc-audioinjector-pi-soundcard))\n\n\ndefine KernelPackage/sound-soc-chipdip-dac\n  TITLE:=Support for ChipDip DAC\n  KCONFIG:= \\\n    CONFIG_SND_BCM2708_SOC_CHIPDIP_DAC\n  FILES:= \\\n    $(LINUX_DIR)/sound/soc/bcm/snd-soc-chipdip-dac.ko\n  AUTOLOAD:=$(call AutoLoad,68,snd-soc-chipdip-dac)\n  DEPENDS:= \\\n    kmod-sound-soc-bcm2835-i2s \\\n    @LINUX_5_10\n  $(call AddDepends/sound)\nendef\n\ndefine KernelPackage/sound-soc-chipdip-dac/description\n  This package contains support for ChipDip DAC\nendef\n\n$(eval $(call KernelPackage,sound-soc-chipdip-dac))\n\n\ndefine KernelPackage/sound-soc-digidac1-soundcard\n  TITLE:=Support for RRA DigiDAC1\n  KCONFIG:= \\\n    CONFIG_SND_DIGIDAC1_SOUNDCARD \\\n    CONFIG_SND_SOC_WM8741 \\\n    CONFIG_SND_SOC_WM8804 \\\n    CONFIG_SND_SOC_WM8804_I2C\n  FILES:= \\\n    $(LINUX_DIR)/sound/soc/bcm/snd-soc-digidac1-soundcard.ko \\\n    $(LINUX_DIR)/sound/soc/codecs/snd-soc-wm8741.ko \\\n    $(LINUX_DIR)/sound/soc/codecs/snd-soc-wm8804.ko \\\n    $(LINUX_DIR)/sound/soc/codecs/snd-soc-wm8804-i2c.ko\n  AUTOLOAD:=$(call AutoLoad,68,snd-soc-wm8741 \\\n    snd-soc-wm8804 snd-soc-wm8804-i2c \\\n    snd-soc-digidac1-soundcard)\n  DEPENDS:= \\\n    kmod-sound-soc-bcm2835-i2s \\\n    +kmod-i2c-bcm2835 \\\n    +kmod-regmap-i2c \\\n    +kmod-regmap-spi\n  $(call AddDepends/sound)\nendef\n\ndefine KernelPackage/sound-soc-digidac1-soundcard/description\n  This package contains support for RRA DigiDAC1\nendef\n\n$(eval $(call KernelPackage,sound-soc-digidac1-soundcard))\n\n\ndefine KernelPackage/sound-soc-dionaudio-loco\n  TITLE:=Support for Dion Audio LOCO DAC-AMP\n  KCONFIG:= \\\n    CONFIG_SND_BCM2708_SOC_DIONAUDIO_LOCO \\\n    CONFIG_SND_SOC_PCM5102A\n  FILES:= \\\n    $(LINUX_DIR)/sound/soc/bcm/snd-soc-dionaudio-loco.ko \\\n    $(LINUX_DIR)/sound/soc/codecs/snd-soc-pcm5102a.ko\n  AUTOLOAD:=$(call AutoLoad,68,snd-soc-pcm5102a \\\n    snd-soc-dionaudio-loco)\n  DEPENDS:= \\\n    kmod-sound-soc-bcm2835-i2s\n  $(call AddDepends/sound)\nendef\n\ndefine KernelPackage/sound-soc-dionaudio-loco/description\n  This package contains support for Dion Audio LOCO DAC-AMP\nendef\n\n$(eval $(call KernelPackage,sound-soc-dionaudio-loco))\n\n\ndefine KernelPackage/sound-soc-dionaudio-loco-v2\n  TITLE:=Support for Dion Audio LOCO-V2 DAC-AMP\n  KCONFIG:= \\\n    CONFIG_SND_BCM2708_SOC_DIONAUDIO_LOCO_V2 \\\n    CONFIG_SND_SOC_PCM512x \\\n    CONFIG_SND_SOC_PCM512x_I2C\n  FILES:= \\\n    $(LINUX_DIR)/sound/soc/bcm/snd-soc-dionaudio-loco.ko \\\n    $(LINUX_DIR)/sound/soc/codecs/snd-soc-pcm512x.ko \\\n    $(LINUX_DIR)/sound/soc/codecs/snd-soc-pcm512x-i2c.ko\n  AUTOLOAD:=$(call AutoLoad,68,snd-soc-pcm512x snd-soc-pcm512x-i2c \\\n    snd-soc-dionaudio-loco)\n  DEPENDS:= \\\n    kmod-sound-soc-bcm2835-i2s \\\n    +kmod-regmap-i2c\n  $(call AddDepends/sound)\nendef\n\ndefine KernelPackage/sound-soc-dionaudio-loco-v2/description\n  This package contains support for Dion Audio LOCO-V2 DAC-AMP\nendef\n\n$(eval $(call KernelPackage,sound-soc-dionaudio-loco-v2))\n\n\ndefine KernelPackage/sound-soc-fe-pi\n  TITLE:=Support for Fe-Pi Audio Sound Card\n  KCONFIG:= \\\n    CONFIG_SND_BCM2708_SOC_FE_PI_AUDIO \\\n    CONFIG_SND_SOC_SGTL5000\n  FILES:= \\\n    $(LINUX_DIR)/sound/soc/bcm/snd-soc-fe-pi-audio.ko \\\n    $(LINUX_DIR)/sound/soc/codecs/snd-soc-sgtl5000.ko\n  AUTOLOAD:=$(call AutoLoad,68,snd-soc-sgtl5000 \\\n    snd-soc-fe-pi-audio)\n  DEPENDS:= \\\n    kmod-sound-soc-bcm2835-i2s \\\n    +kmod-regmap-i2c\n  $(call AddDepends/sound)\nendef\n\ndefine KernelPackage/sound-soc-fe-pi/description\n  This package contains support for Fe-Pi Audio Sound Card\nendef\n\n$(eval $(call KernelPackage,sound-soc-fe-pi))\n\n\ndefine KernelPackage/sound-soc-googlevoicehat\n  TITLE:=Support for Google VoiceHAT Sound Card\n  KCONFIG:= \\\n    CONFIG_SND_BCM2708_SOC_GOOGLEVOICEHAT_SOUNDCARD \\\n    CONFIG_SND_SOC_VOICEHAT\n  FILES:= \\\n    $(LINUX_DIR)/sound/soc/bcm/snd-soc-googlevoicehat-codec.ko\n  AUTOLOAD:=$(call AutoLoad,68,snd-soc-googlevoicehat-codec)\n  DEPENDS:= \\\n    kmod-sound-soc-bcm2835-i2s \\\n    +kmod-sound-soc-rpi-simple-soundcard\n  $(call AddDepends/sound)\nendef\n\ndefine KernelPackage/sound-soc-googlevoicehat/description\n  This package contains support for Google VoiceHAT Sound Card\nendef\n\n$(eval $(call KernelPackage,sound-soc-googlevoicehat))\n\n\ndefine KernelPackage/sound-soc-hifiberry-dac\n  TITLE:=Support for HifiBerry DAC\n  KCONFIG:= \\\n    CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC \\\n    CONFIG_SND_SOC_PCM5102A\n  FILES:= \\\n    $(LINUX_DIR)/sound/soc/codecs/snd-soc-pcm5102a.ko\n  AUTOLOAD:=$(call AutoLoad,68,snd-soc-pcm5102a)\n  DEPENDS:= \\\n    kmod-sound-soc-bcm2835-i2s \\\n    +kmod-sound-soc-rpi-simple-soundcard \\\n    +kmod-i2c-bcm2835\n  $(call AddDepends/sound)\nendef\n\ndefine KernelPackage/sound-soc-hifiberry-dac/description\n  This package contains support for HifiBerry DAC\nendef\n\n$(eval $(call KernelPackage,sound-soc-hifiberry-dac))\n\n\ndefine KernelPackage/sound-soc-hifiberry-dacplus\n  TITLE:=Support for HifiBerry DAC+ / DAC+ Pro / Amp2\n  KCONFIG:= \\\n    CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS \\\n    CONFIG_SND_SOC_PCM512x \\\n    CONFIG_SND_SOC_PCM512x_I2C\n  FILES:= \\\n    $(LINUX_DIR)/drivers/clk/clk-hifiberry-dacpro.ko \\\n    $(LINUX_DIR)/sound/soc/bcm/snd-soc-hifiberry-dacplus.ko \\\n    $(LINUX_DIR)/sound/soc/codecs/snd-soc-pcm512x.ko \\\n    $(LINUX_DIR)/sound/soc/codecs/snd-soc-pcm512x-i2c.ko\n  AUTOLOAD:=$(call AutoLoad,68,clk-hifiberry-dacpro snd-soc-pcm512x \\\n    snd-soc-pcm512x-i2c snd-soc-hifiberry-dacplus)\n  DEPENDS:= \\\n    kmod-sound-soc-bcm2835-i2s \\\n    +kmod-i2c-bcm2835 \\\n    +kmod-regmap-i2c\n  $(call AddDepends/sound)\nendef\n\ndefine KernelPackage/sound-soc-hifiberry-dacplus/description\n  This package contains support for HifiBerry DAC+ / DAC+ Pro / Amp2\nendef\n\n$(eval $(call KernelPackage,sound-soc-hifiberry-dacplus))\n\n\ndefine KernelPackage/sound-soc-hifiberry-dacplusadc\n  TITLE:=Support for HifiBerry DAC+ADC\n  KCONFIG:= \\\n    CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUSADC \\\n    CONFIG_SND_SOC_PCM512x \\\n    CONFIG_SND_SOC_DMIC\n  FILES:= \\\n    $(LINUX_DIR)/drivers/clk/clk-hifiberry-dacpro.ko \\\n    $(LINUX_DIR)/sound/soc/bcm/snd-soc-hifiberry-dacplusadc.ko \\\n    $(LINUX_DIR)/sound/soc/codecs/snd-soc-pcm512x.ko \\\n    $(LINUX_DIR)/sound/soc/codecs/snd-soc-dmic.ko\n  AUTOLOAD:=$(call AutoLoad,68,clk-hifiberry-dacpro snd-soc-pcm512x \\\n    snd-soc-dmic snd-soc-hifiberry-dacplusadc)\n  DEPENDS:= \\\n    kmod-sound-soc-bcm2835-i2s \\\n    +kmod-i2c-bcm2835\n  $(call AddDepends/sound)\nendef\n\ndefine KernelPackage/sound-soc-hifiberry-dacplusadc/description\n  This package contains support for HifiBerry DAC+ADC\nendef\n\n$(eval $(call KernelPackage,sound-soc-hifiberry-dacplusadc))\n\n\ndefine KernelPackage/sound-soc-hifiberry-dacplusdsp\n  TITLE:=Support for HifiBerry DAC+DSP\n  KCONFIG:= \\\n    CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUSDSP\n  FILES:= \\\n    $(LINUX_DIR)/sound/soc/bcm/snd-soc-hifiberry-dacplusdsp.ko\n  AUTOLOAD:=$(call AutoLoad,68,snd-soc-hifiberry-dacplusdsp)\n  DEPENDS:= \\\n    kmod-sound-soc-bcm2835-i2s \\\n    +kmod-sound-soc-rpi-simple-soundcard\n  $(call AddDepends/sound)\nendef\n\ndefine KernelPackage/sound-soc-hifiberry-dacplusdsp/description\n  This package contains support for HifiBerry DAC+DSP\nendef\n\n$(eval $(call KernelPackage,sound-soc-hifiberry-dacplusdsp))\n\n\ndefine KernelPackage/sound-soc-hifiberry-dacplushd\n  TITLE:=Support for HifiBerry DAC+HD\n  KCONFIG:= \\\n    CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUSHD \\\n    CONFIG_SND_SOC_PCM179X \\\n    CONFIG_SND_SOC_PCM179X_I2C\n  FILES:= \\\n    $(LINUX_DIR)/drivers/clk/clk-hifiberry-dachd.ko \\\n    $(LINUX_DIR)/sound/soc/bcm/snd-soc-hifiberry-dacplushd.ko \\\n    $(LINUX_DIR)/sound/soc/codecs/snd-soc-pcm179x-codec.ko \\\n    $(LINUX_DIR)/sound/soc/codecs/snd-soc-pcm179x-i2c.ko\n  AUTOLOAD:=$(call AutoLoad,68,clk-hifiberry-dachd snd-soc-pcm179x-codec \\\n    snd-soc-pcm179x-i2c snd-soc-hifiberry-dacplushd)\n  DEPENDS:= \\\n    kmod-sound-soc-bcm2835-i2s \\\n    +kmod-i2c-bcm2835 \\\n    +kmod-regmap-i2c\n  $(call AddDepends/sound)\nendef\n\ndefine KernelPackage/sound-soc-hifiberry-dacplushd/description\n  This package contains support for HifiBerry DAC+HD\nendef\n\n$(eval $(call KernelPackage,sound-soc-hifiberry-dacplushd))\n\n\ndefine KernelPackage/sound-soc-hifiberry-dacplusadc-pro\n  TITLE:=Support for HifiBerry DAC+ADC PRO\n  KCONFIG:= \\\n    CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUSADCPRO \\\n    CONFIG_SND_SOC_PCM186X \\\n    CONFIG_SND_SOC_PCM186X_I2C \\\n    CONFIG_SND_SOC_PCM512x \\\n    CONFIG_SND_SOC_PCM512x_I2C\n  FILES:= \\\n    $(LINUX_DIR)/sound/soc/bcm/snd-soc-hifiberry-dacplusadcpro.ko \\\n    $(LINUX_DIR)/sound/soc/codecs/snd-soc-pcm186x.ko \\\n    $(LINUX_DIR)/sound/soc/codecs/snd-soc-pcm186x-i2c.ko \\\n    $(LINUX_DIR)/sound/soc/codecs/snd-soc-pcm512x.ko \\\n    $(LINUX_DIR)/sound/soc/codecs/snd-soc-pcm512x-i2c.ko\n  AUTOLOAD:=$(call AutoLoad,68,snd-soc-pcm186x snd-soc-pcm186x-i2c \\\n    snd-soc-pcm512x snd-soc-pcm512x-i2c snd-soc-hifiberry-dacplusadcpro)\n  DEPENDS:= \\\n    kmod-sound-soc-bcm2835-i2s \\\n    +kmod-i2c-bcm2835 \\\n    +kmod-regmap-i2c\n  $(call AddDepends/sound)\nendef\n\ndefine KernelPackage/sound-soc-hifiberry-dacplusadc-pro/description\n  This package contains support for HifiBerry DAC+ADC PRO\nendef\n\n$(eval $(call KernelPackage,sound-soc-hifiberry-dacplusadc-pro))\n\n\ndefine KernelPackage/sound-soc-hifiberry-digi\n  TITLE:=Support for HifiBerry Digi / Digi+ / Digi+ Pro\n  KCONFIG:= \\\n    CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI \\\n    CONFIG_SND_SOC_WM8804\n  FILES:= \\\n    $(LINUX_DIR)/sound/soc/codecs/snd-soc-wm8804.ko\n  AUTOLOAD:=$(call AutoLoad,68,snd-soc-wm8804)\n  DEPENDS:= \\\n    kmod-sound-soc-bcm2835-i2s \\\n    +kmod-sound-soc-rpi-wm8804-soundcard \\\n    +kmod-i2c-bcm2835\n  $(call AddDepends/sound)\nendef\n\ndefine KernelPackage/sound-soc-hifiberry-digi/description\n  This package contains support for HifiBerry Digi\nendef\n\n$(eval $(call KernelPackage,sound-soc-hifiberry-digi))\n\n\ndefine KernelPackage/sound-soc-hifiberry-amp\n  TITLE:=Support for HifiBerry Amp\n  KCONFIG:= \\\n    CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP \\\n    CONFIG_SND_SOC_TAS5713\n  FILES:= \\\n    $(LINUX_DIR)/sound/soc/codecs/snd-soc-tas5713.ko\n  AUTOLOAD:=$(call AutoLoad,68,snd-soc-tas5713)\n  DEPENDS:= \\\n    kmod-sound-soc-bcm2835-i2s \\\n    +kmod-sound-soc-rpi-simple-soundcard \\\n    +kmod-i2c-bcm2835 \\\n    +kmod-regmap-i2c\n  $(call AddDepends/sound)\nendef\n\ndefine KernelPackage/sound-soc-hifiberry-amp/description\n  This package contains support for HifiBerry Amp\nendef\n\n$(eval $(call KernelPackage,sound-soc-hifiberry-amp))\n\n\ndefine KernelPackage/sound-soc-iqaudio-codec\n  TITLE:=Support for IQaudIO-CODEC\n  KCONFIG:= \\\n    CONFIG_SND_BCM2708_SOC_IQAUDIO_CODEC \\\n    CONFIG_SND_SOC_DA7213\n  FILES:= \\\n    $(LINUX_DIR)/sound/soc/bcm/snd-soc-iqaudio-codec.ko \\\n    $(LINUX_DIR)/sound/soc/codecs/snd-soc-da7213.ko\n  AUTOLOAD:=$(call AutoLoad,68,snd-soc-da7213 snd-soc-iqaudio-codec)\n  DEPENDS:= \\\n    kmod-sound-soc-bcm2835-i2s \\\n    +kmod-i2c-bcm2835 \\\n    +kmod-regmap-i2c\n  $(call AddDepends/sound)\nendef\n\ndefine KernelPackage/sound-soc-iqaudio-codec/description\n  This package contains support for IQaudIO-CODEC\nendef\n\n$(eval $(call KernelPackage,sound-soc-iqaudio-codec))\n\n\ndefine KernelPackage/sound-soc-iqaudio-dac\n  TITLE:=Support for IQaudIO-DAC\n  KCONFIG:= \\\n    CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC \\\n    CONFIG_SND_SOC_PCM512x \\\n    CONFIG_SND_SOC_PCM512x_I2C\n  FILES:= \\\n    $(LINUX_DIR)/sound/soc/bcm/snd-soc-iqaudio-dac.ko \\\n    $(LINUX_DIR)/sound/soc/codecs/snd-soc-pcm512x.ko \\\n    $(LINUX_DIR)/sound/soc/codecs/snd-soc-pcm512x-i2c.ko\n  AUTOLOAD:=$(call AutoLoad,68,snd-soc-pcm512x snd-soc-pcm512x-i2c \\\n    snd-soc-iqaudio-dac)\n  DEPENDS:= \\\n    kmod-sound-soc-bcm2835-i2s \\\n    +kmod-i2c-bcm2835 \\\n    +kmod-regmap-i2c\n  $(call AddDepends/sound)\nendef\n\ndefine KernelPackage/sound-soc-iqaudio-dac/description\n  This package contains support for IQaudIO-DAC\nendef\n\n$(eval $(call KernelPackage,sound-soc-iqaudio-dac))\n\n\ndefine KernelPackage/sound-soc-iqaudio-digi\n  TITLE:=Support for IQaudIO-DIGI\n  KCONFIG:= \\\n    CONFIG_SND_BCM2708_SOC_IQAUDIO_DIGI \\\n    CONFIG_SND_SOC_WM8804 \\\n    CONFIG_SND_SOC_WM8804_I2C\n  FILES:= \\\n    $(LINUX_DIR)/sound/soc/codecs/snd-soc-wm8804.ko \\\n    $(LINUX_DIR)/sound/soc/codecs/snd-soc-wm8804-i2c.ko\n  AUTOLOAD:=$(call AutoLoad,68,snd-soc-wm8804 snd-soc-wm8804-i2c)\n  DEPENDS:= \\\n    kmod-sound-soc-bcm2835-i2s \\\n    +kmod-sound-soc-rpi-wm8804-soundcard \\\n    +kmod-i2c-bcm2835 \\\n    +kmod-regmap-i2c\n  $(call AddDepends/sound)\nendef\n\ndefine KernelPackage/sound-soc-iqaudio-digi/description\n  This package contains support for IQaudIO-DIGI\nendef\n\n$(eval $(call KernelPackage,sound-soc-iqaudio-digi))\n\n\ndefine KernelPackage/sound-soc-i-sabe-q2m\n  TITLE:=Support for Audiophonics I-Sabre Q2M DAC\n  KCONFIG:= \\\n    CONFIG_SND_BCM2708_SOC_I_SABRE_Q2M \\\n    CONFIG_SND_SOC_I_SABRE_CODEC\n  FILES:= \\\n    $(LINUX_DIR)/sound/soc/bcm/snd-soc-i-sabre-q2m.ko \\\n    $(LINUX_DIR)/sound/soc/codecs/snd-soc-i-sabre-codec.ko\n  AUTOLOAD:=$(call AutoLoad,68,snd-soc-i-sabre-codec snd-soc-i-sabre-q2m)\n  DEPENDS:= \\\n    kmod-sound-soc-bcm2835-i2s \\\n    +kmod-i2c-bcm2835 \\\n    +kmod-regmap-i2c\n  $(call AddDepends/sound)\nendef\n\ndefine KernelPackage/sound-soc-i-sabe-q2m/description\n  This package contains support for Audiophonics I-SABRE Q2M DAC\nendef\n\n$(eval $(call KernelPackage,sound-soc-i-sabe-q2m))\n\n\ndefine KernelPackage/sound-soc-justboom-both\n  TITLE:=Support for JustBoom DAC and Digi\n  KCONFIG:= \\\n    CONFIG_SND_BCM2708_SOC_JUSTBOOM_BOTH \\\n    CONFIG_SND_SOC_PCM512x \\\n    CONFIG_SND_SOC_WM8804\n  FILES:= \\\n    $(LINUX_DIR)/sound/soc/bcm/snd-soc-justboom-both.ko \\\n    $(LINUX_DIR)/sound/soc/codecs/snd-soc-pcm512x.ko \\\n    $(LINUX_DIR)/sound/soc/codecs/snd-soc-wm8804.ko\n  AUTOLOAD:=$(call AutoLoad,68,snd-soc-pcm512x snd-soc-wm8804 \\\n    snd-soc-justboom-both)\n  DEPENDS:= \\\n    kmod-sound-soc-bcm2835-i2s \\\n    +kmod-sound-soc-rpi-wm8804-soundcard \\\n    +kmod-i2c-bcm2835\n  $(call AddDepends/sound)\nendef\n\ndefine KernelPackage/sound-soc-justboom-both/description\n  This package contains support for JustBoom DAC and Digi\nendef\n\n$(eval $(call KernelPackage,sound-soc-justboom-both))\n\n\ndefine KernelPackage/sound-soc-justboom-dac\n  TITLE:=Support for JustBoom DAC\n  KCONFIG:= \\\n    CONFIG_SND_BCM2708_SOC_JUSTBOOM_DAC \\\n    CONFIG_SND_SOC_PCM512x\n  FILES:= \\\n    $(LINUX_DIR)/sound/soc/bcm/snd-soc-justboom-dac.ko \\\n    $(LINUX_DIR)/sound/soc/codecs/snd-soc-pcm512x.ko\n  AUTOLOAD:=$(call AutoLoad,68,snd-soc-pcm512x snd-soc-justboom-dac)\n  DEPENDS:= \\\n    kmod-sound-soc-bcm2835-i2s \\\n    +kmod-i2c-bcm2835\n  $(call AddDepends/sound)\nendef\n\ndefine KernelPackage/sound-soc-justboom-dac/description\n  This package contains support for JustBoom DAC\nendef\n\n$(eval $(call KernelPackage,sound-soc-justboom-dac))\n\n\ndefine KernelPackage/sound-soc-justboom-digi\n  TITLE:=Support for JustBoom Digi\n  KCONFIG:= \\\n    CONFIG_SND_BCM2708_SOC_JUSTBOOM_DIGI \\\n    CONFIG_SND_SOC_WM8804\n  FILES:= \\\n    $(LINUX_DIR)/sound/soc/codecs/snd-soc-wm8804.ko\n  AUTOLOAD:=$(call AutoLoad,68,snd-soc-wm8804)\n  DEPENDS:= \\\n    kmod-sound-soc-bcm2835-i2s \\\n    +kmod-sound-soc-rpi-wm8804-soundcard \\\n    +kmod-i2c-bcm2835\n  $(call AddDepends/sound)\nendef\n\ndefine KernelPackage/sound-soc-justboom-digi/description\n  This package contains support for JustBoom Digi\nendef\n\n$(eval $(call KernelPackage,sound-soc-justboom-digi))\n\n\ndefine KernelPackage/sound-soc-pifi-40-amp\n  TITLE:=Support for PiFi-40 amp\n  KCONFIG:= \\\n    CONFIG_SND_BCM2708_SOC_PIFI_40 \\\n    CONFIG_SND_PIFI_40 \\\n    CONFIG_SND_SOC_TAS571X\n  FILES:= \\\n    $(LINUX_DIR)/sound/soc/bcm/snd-soc-pifi-40.ko \\\n    $(LINUX_DIR)/sound/soc/codecs/snd-soc-tas571x.ko\n  AUTOLOAD:=$(call AutoLoad,68,snd-soc-tas571x)\n  DEPENDS:= \\\n    kmod-sound-soc-bcm2835-i2s\n  $(call AddDepends/sound)\nendef\n\ndefine KernelPackage/sound-soc-pifi-40-amp/description\n  This package contains support for PiFi-40 amp\nendef\n\n$(eval $(call KernelPackage,sound-soc-pifi-40-amp))\n\n\ndefine KernelPackage/sound-soc-pisound\n  TITLE:=Support for Blokas Labs PiSound\n  KCONFIG:= \\\n    CONFIG_SND_PISOUND \\\n    CONFIG_SND_SOC_PCM5102A\n  FILES:= \\\n    $(LINUX_DIR)/sound/soc/bcm/snd-soc-pisound.ko \\\n    $(LINUX_DIR)/sound/soc/codecs/snd-soc-pcm5102a.ko\n  AUTOLOAD:=$(call AutoLoad,68,snd-soc-pcm5102a snd-soc-pisound)\n  DEPENDS:= \\\n    kmod-sound-soc-bcm2835-i2s\n  $(call AddDepends/sound)\nendef\n\ndefine KernelPackage/sound-soc-pisound/description\n  This package contains support for Blokas Labs PiSound\nendef\n\n$(eval $(call KernelPackage,sound-soc-pisound))\n\n\ndefine KernelPackage/sound-soc-rpi-cirrus\n  TITLE:=Support for Cirrus Logic Audio Card\n  KCONFIG:= \\\n    CONFIG_GPIO_ARIZONA \\\n    CONFIG_INPUT_ARIZONA_HAPTICS=n \\\n    CONFIG_MFD_ARIZONA=y \\\n    CONFIG_MFD_ARIZONA_I2C \\\n    CONFIG_MFD_CS47L24=n \\\n    CONFIG_MFD_WM5102=n \\\n    CONFIG_MFD_WM5110=n \\\n    CONFIG_MFD_WM8997=n \\\n    CONFIG_MFD_WM8998=n \\\n    CONFIG_REGULATOR_ARIZONA \\\n    CONFIG_REGULATOR_ARIZONA_LDO1 \\\n    CONFIG_REGULATOR_ARIZONA_MICSUPP \\\n    CONFIG_SND_BCM2708_SOC_RPI_CIRRUS \\\n    CONFIG_SND_SOC_ARIZONA \\\n    CONFIG_SND_SOC_WM5102 \\\n    CONFIG_SND_SOC_WM8804 \\\n    CONFIG_SND_SOC_WM_ADSP\n  FILES:= \\\n    $(LINUX_DIR)/sound/soc/bcm/snd-soc-rpi-cirrus.ko \\\n    $(LINUX_DIR)/sound/soc/codecs/snd-soc-arizona.ko \\\n    $(LINUX_DIR)/sound/soc/codecs/snd-soc-wm-adsp.ko \\\n    $(LINUX_DIR)/sound/soc/codecs/snd-soc-wm5102.ko \\\n    $(LINUX_DIR)/sound/soc/codecs/snd-soc-wm8804.ko\n  AUTOLOAD:=$(call AutoLoad,68,snd-soc-pcm1794a snd-soc-rpi-cirrus)\n  DEPENDS:= \\\n    +kmod-i2c-bcm2835 \\\n    kmod-sound-soc-bcm2835-i2s\n  $(call AddDepends/sound)\nendef\n\ndefine KernelPackage/sound-soc-rpi-cirrus/description\n  This package contains support for RPi-Cirrus\nendef\n\n$(eval $(call KernelPackage,sound-soc-rpi-cirrus))\n\n\ndefine KernelPackage/sound-soc-rpi-dac\n  TITLE:=Support for RPi-DAC\n  KCONFIG:= \\\n    CONFIG_SND_BCM2708_SOC_RPI_DAC \\\n    CONFIG_SND_SOC_PCM1794A\n  FILES:= \\\n    $(LINUX_DIR)/sound/soc/codecs/snd-soc-pcm1794a.ko\n  AUTOLOAD:=$(call AutoLoad,68,snd-soc-pcm1794a)\n  DEPENDS:= \\\n    kmod-sound-soc-bcm2835-i2s \\\n    +kmod-sound-soc-rpi-simple-soundcard \\\n    +kmod-i2c-bcm2835\n  $(call AddDepends/sound)\nendef\n\ndefine KernelPackage/sound-soc-rpi-dac/description\n  This package contains support for RPi-DAC\nendef\n\n$(eval $(call KernelPackage,sound-soc-rpi-dac))\n\n\ndefine KernelPackage/sound-soc-merus-amp\n  TITLE:=Support for Infineon Merus Amp\n  KCONFIG:= \\\n    CONFIG_SND_SOC_MA120X0P\n  FILES:= \\\n    $(LINUX_DIR)/sound/soc/codecs/snd-soc-ma120x0p.ko\n  AUTOLOAD:=$(call AutoLoad,68,snd-soc-ma120x0p)\n  DEPENDS:= \\\n    kmod-sound-soc-bcm2835-i2s \\\n    +kmod-sound-soc-rpi-simple-soundcard \\\n    +kmod-i2c-bcm2835 \\\n    +kmod-regmap-i2c\n  $(call AddDepends/sound)\nendef\n\ndefine KernelPackage/sound-soc-merus-amp/description\n  This package contains support for Infineon Merus Amp\nendef\n\n$(eval $(call KernelPackage,sound-soc-merus-amp))\n\n\ndefine KernelPackage/sound-soc-rpi-proto\n  TITLE:=Support for RPi-PROTO\n  KCONFIG:= \\\n    CONFIG_SND_BCM2708_SOC_RPI_PROTO \\\n    CONFIG_SND_SOC_WM8731\n  FILES:= \\\n    $(LINUX_DIR)/sound/soc/bcm/snd-soc-rpi-proto.ko \\\n    $(LINUX_DIR)/sound/soc/codecs/snd-soc-wm8731.ko\n  AUTOLOAD:=$(call AutoLoad,68,snd-soc-wm8731 snd-soc-rpi-proto)\n  DEPENDS:= \\\n    kmod-sound-soc-bcm2835-i2s \\\n    +kmod-i2c-bcm2835 \\\n    +kmod-regmap-i2c \\\n    +kmod-regmap-spi\n  $(call AddDepends/sound)\nendef\n\ndefine KernelPackage/sound-soc-rpi-proto/description\n  This package contains support for RPi-PROTO\nendef\n\n$(eval $(call KernelPackage,sound-soc-rpi-proto))\n"
  },
  {
    "path": "target/linux/bcm27xx/modules/spi.mk",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2019 OpenWrt.org\n\ndefine KernelPackage/spi-bcm2835\n  SUBMENU:=$(SPI_MENU)\n  TITLE:=BCM2835 SPI controller driver\n  KCONFIG:=\\\n    CONFIG_SPI=y \\\n    CONFIG_SPI_BCM2835 \\\n    CONFIG_SPI_MASTER=y\n  FILES:=$(LINUX_DIR)/drivers/spi/spi-bcm2835.ko\n  AUTOLOAD:=$(call AutoLoad,89,spi-bcm2835)\n  DEPENDS:=@TARGET_bcm27xx\nendef\n\ndefine KernelPackage/spi-bcm2835/description\n  This package contains the Broadcom 2835 SPI master controller driver\nendef\n\n$(eval $(call KernelPackage,spi-bcm2835))\n\n\ndefine KernelPackage/spi-bcm2835-aux\n  SUBMENU:=$(SPI_MENU)\n  TITLE:=BCM2835 Aux SPI controller driver\n  KCONFIG:=\\\n    CONFIG_SPI=y \\\n    CONFIG_SPI_BCM2835AUX \\\n    CONFIG_SPI_MASTER=y\n  FILES:=$(LINUX_DIR)/drivers/spi/spi-bcm2835aux.ko\n  AUTOLOAD:=$(call AutoLoad,89,spi-bcm2835aux)\n  DEPENDS:=@TARGET_bcm27xx\nendef\n\ndefine KernelPackage/spi-bcm2835-aux/description\n  This package contains the Broadcom 2835 Aux SPI master controller driver\nendef\n\n$(eval $(call KernelPackage,spi-bcm2835-aux))\n"
  },
  {
    "path": "target/linux/bcm27xx/modules/video.mk",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2019 OpenWrt.org\n\ndefine KernelPackage/camera-bcm2835\n  TITLE:=BCM2835 Camera\n  KCONFIG:= \\\n    CONFIG_VIDEO_BCM2835 \\\n    CONFIG_VIDEO_BCM2835_MMAL \\\n    CONFIG_VIDEO_BCM2835_UNICAM=n \\\n    CONFIG_VIDEO_ISP_BCM2835=n\n  FILES:= \\\n    $(LINUX_DIR)/drivers/staging/vc04_services/bcm2835-camera/bcm2835-v4l2.ko\n  AUTOLOAD:=$(call AutoLoad,65,bcm2835-v4l2)\n  $(call AddDepends/video,@TARGET_bcm27xx +kmod-vchiq-mmal-bcm2835 +kmod-video-videobuf2)\nendef\n\ndefine KernelPackage/camera-bcm2835/description\n  Camera host interface devices for Broadcom BCM2835 SoC.\n  This operates over the VCHIQ interface to a service running on VideoCore.\nendef\n\n$(eval $(call KernelPackage,camera-bcm2835))\n\n\ndefine KernelPackage/drm-vc4\n  SUBMENU:=$(VIDEO_MENU)\n  TITLE:=Broadcom VC4 Graphics\n  DEPENDS:= \\\n    @TARGET_bcm27xx +kmod-drm \\\n    +kmod-sound-core \\\n    +kmod-sound-soc-core\n  KCONFIG:= \\\n    CONFIG_DRM_VC4 \\\n    CONFIG_DRM_VC4_HDMI_CEC=y \\\n    CONFIG_DRM_GUD=n \\\n    CONFIG_DRM_V3D=n \\\n    CONFIG_DRM_TVE200=n\n  FILES:= \\\n    $(LINUX_DIR)/drivers/gpu/drm/vc4/vc4.ko \\\n    $(LINUX_DIR)/drivers/gpu/drm/drm_kms_helper.ko \\\n    $(LINUX_DIR)/drivers/media/cec/cec.ko@lt5.10 \\\n    $(LINUX_DIR)/drivers/media/cec/core/cec.ko@ge5.10\n  AUTOLOAD:=$(call AutoProbe,vc4)\nendef\n\ndefine KernelPackage/drm-vc4/description\n  Direct Rendering Manager (DRM) support for Broadcom VideoCore IV GPU\n  used in BCM2835, BCM2836 and BCM2837 SoCs (e.g. Raspberry Pi).\nendef\n\n$(eval $(call KernelPackage,drm-vc4))\n\n\ndefine KernelPackage/vc-sm-cma\n  TITLE:=VideoCore Shared Memory (CMA) driver\n  KCONFIG:= \\\n    CONFIG_BCM_VC_SM_CMA\n  FILES:= \\\n    $(LINUX_DIR)/drivers/staging/vc04_services/vc-sm-cma/vc-sm-cma.ko\n  $(call AddDepends/video,@TARGET_bcm27xx)\nendef\n\ndefine KernelPackage/vc-sm-cma/description\n  Shared memory interface that supports sharing dmabufs with VideoCore.\n  This operates over the VCHIQ interface to a service running on VideoCore.\nendef\n\n$(eval $(call KernelPackage,vc-sm-cma))\n\n\ndefine KernelPackage/vchiq-mmal-bcm2835\n  TITLE:=BCM2835 MMAL VCHIQ service\n  KCONFIG:= \\\n    CONFIG_BCM2835_VCHIQ_MMAL \\\n    CONFIG_VIDEO_CODEC_BCM2835=n\n  FILES:= \\\n    $(LINUX_DIR)/drivers/staging/vc04_services/vchiq-mmal/bcm2835-mmal-vchiq.ko\n  $(call AddDepends/video,@TARGET_bcm27xx +kmod-vc-sm-cma)\nendef\n\ndefine KernelPackage/vchiq-mmal-bcm2835/description\n  Enables the MMAL API over VCHIQ as used for the\n  majority of the multimedia services on VideoCore.\nendef\n\n$(eval $(call KernelPackage,vchiq-mmal-bcm2835))\n"
  },
  {
    "path": "target/linux/bcm27xx/modules.mk",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2019 OpenWrt.org\n\ninclude $(TOPDIR)/target/linux/bcm27xx/modules/*.mk\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0001-arm-partially-revert-702b94bff3c50542a6e4ab9a4f4cef0.patch",
    "content": "From c966ee565b122d840d7aac4c07c53b0d679d2d33 Mon Sep 17 00:00:00 2001\nFrom: Dan Pasanen <dan.pasanen@gmail.com>\nDate: Thu, 21 Sep 2017 09:55:42 -0500\nSubject: [PATCH] arm: partially revert\n 702b94bff3c50542a6e4ab9a4f4cef093262fe65\n\n* Re-expose some dmi APIs for use in VCSM\n---\n arch/arm/include/asm/cacheflush.h | 21 +++++++++++++++++++++\n arch/arm/include/asm/glue-cache.h |  2 ++\n arch/arm/mm/proc-macros.S         |  2 ++\n arch/arm/mm/proc-syms.c           |  3 +++\n 4 files changed, 28 insertions(+)\n\n--- a/arch/arm/include/asm/cacheflush.h\n+++ b/arch/arm/include/asm/cacheflush.h\n@@ -91,6 +91,21 @@\n  *\tDMA Cache Coherency\n  *\t===================\n  *\n+ *\tdma_inv_range(start, end)\n+ *\n+ *\t\tInvalidate (discard) the specified virtual address range.\n+ *\t\tMay not write back any entries.  If 'start' or 'end'\n+ *\t\tare not cache line aligned, those lines must be written\n+ *\t\tback.\n+ *\t\t- start  - virtual start address\n+ *\t\t- end    - virtual end address\n+ *\n+ *\tdma_clean_range(start, end)\n+ *\n+ *\t\tClean (write back) the specified virtual address range.\n+ *\t\t- start  - virtual start address\n+ *\t\t- end    - virtual end address\n+ *\n  *\tdma_flush_range(start, end)\n  *\n  *\t\tClean and invalidate the specified virtual address range.\n@@ -112,6 +127,8 @@ struct cpu_cache_fns {\n \tvoid (*dma_map_area)(const void *, size_t, int);\n \tvoid (*dma_unmap_area)(const void *, size_t, int);\n \n+\tvoid (*dma_inv_range)(const void *, const void *);\n+\tvoid (*dma_clean_range)(const void *, const void *);\n \tvoid (*dma_flush_range)(const void *, const void *);\n } __no_randomize_layout;\n \n@@ -137,6 +154,8 @@ extern struct cpu_cache_fns cpu_cache;\n  * is visible to DMA, or data written by DMA to system memory is\n  * visible to the CPU.\n  */\n+#define dmac_inv_range\t\t\tcpu_cache.dma_inv_range\n+#define dmac_clean_range\t\tcpu_cache.dma_clean_range\n #define dmac_flush_range\t\tcpu_cache.dma_flush_range\n \n #else\n@@ -156,6 +175,8 @@ extern void __cpuc_flush_dcache_area(voi\n  * is visible to DMA, or data written by DMA to system memory is\n  * visible to the CPU.\n  */\n+extern void dmac_inv_range(const void *, const void *);\n+extern void dmac_clean_range(const void *, const void *);\n extern void dmac_flush_range(const void *, const void *);\n \n #endif\n--- a/arch/arm/include/asm/glue-cache.h\n+++ b/arch/arm/include/asm/glue-cache.h\n@@ -155,6 +155,8 @@ static inline void nop_dma_unmap_area(co\n #define __cpuc_coherent_user_range\t__glue(_CACHE,_coherent_user_range)\n #define __cpuc_flush_dcache_area\t__glue(_CACHE,_flush_kern_dcache_area)\n \n+#define dmac_inv_range\t\t\t__glue(_CACHE,_dma_inv_range)\n+#define dmac_clean_range\t\t__glue(_CACHE,_dma_clean_range)\n #define dmac_flush_range\t\t__glue(_CACHE,_dma_flush_range)\n #endif\n \n--- a/arch/arm/mm/proc-macros.S\n+++ b/arch/arm/mm/proc-macros.S\n@@ -334,6 +334,8 @@ ENTRY(\\name\\()_cache_fns)\n \t.long\t\\name\\()_flush_kern_dcache_area\n \t.long\t\\name\\()_dma_map_area\n \t.long\t\\name\\()_dma_unmap_area\n+\t.long\t\\name\\()_dma_inv_range\n+\t.long\t\\name\\()_dma_clean_range\n \t.long\t\\name\\()_dma_flush_range\n \t.size\t\\name\\()_cache_fns, . - \\name\\()_cache_fns\n .endm\n--- a/arch/arm/mm/proc-syms.c\n+++ b/arch/arm/mm/proc-syms.c\n@@ -27,6 +27,9 @@ EXPORT_SYMBOL(__cpuc_flush_user_all);\n EXPORT_SYMBOL(__cpuc_flush_user_range);\n EXPORT_SYMBOL(__cpuc_coherent_kern_range);\n EXPORT_SYMBOL(__cpuc_flush_dcache_area);\n+EXPORT_SYMBOL(dmac_inv_range);\n+EXPORT_SYMBOL(dmac_clean_range);\n+EXPORT_SYMBOL(dmac_flush_range);\n #else\n EXPORT_SYMBOL(cpu_cache);\n #endif\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0002-Revert-rtc-pcf8523-properly-handle-oscillator-stop-b.patch",
    "content": "From f4888774b6bf2f68fa2b389690eee07d7e8efdb9 Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.org>\nDate: Mon, 29 Oct 2018 14:45:45 +0000\nSubject: [PATCH] Revert \"rtc: pcf8523: properly handle oscillator stop\n bit\"\n\nThis reverts commit ede44c908d44b166a5b6bd7caacd105c2ff5a70f.\n\nSee: https://github.com/raspberrypi/firmware/issues/1065\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.org>\n---\n drivers/rtc/rtc-pcf8523.c | 25 ++++++++++++++++++++++---\n 1 file changed, 22 insertions(+), 3 deletions(-)\n\n--- a/drivers/rtc/rtc-pcf8523.c\n+++ b/drivers/rtc/rtc-pcf8523.c\n@@ -205,8 +205,28 @@ static int pcf8523_rtc_read_time(struct\n \tif (err < 0)\n \t\treturn err;\n \n-\tif (regs[0] & REG_SECONDS_OS)\n-\t\treturn -EINVAL;\n+\tif (regs[0] & REG_SECONDS_OS) {\n+\t\t/*\n+\t\t * If the oscillator was stopped, try to clear the flag. Upon\n+\t\t * power-up the flag is always set, but if we cannot clear it\n+\t\t * the oscillator isn't running properly for some reason. The\n+\t\t * sensible thing therefore is to return an error, signalling\n+\t\t * that the clock cannot be assumed to be correct.\n+\t\t */\n+\n+\t\tregs[0] &= ~REG_SECONDS_OS;\n+\n+\t\terr = pcf8523_write(client, REG_SECONDS, regs[0]);\n+\t\tif (err < 0)\n+\t\t\treturn err;\n+\n+\t\terr = pcf8523_read(client, REG_SECONDS, &regs[0]);\n+\t\tif (err < 0)\n+\t\t\treturn err;\n+\n+\t\tif (regs[0] & REG_SECONDS_OS)\n+\t\t\treturn -EAGAIN;\n+\t}\n \n \ttm->tm_sec = bcd2bin(regs[0] & 0x7f);\n \ttm->tm_min = bcd2bin(regs[1] & 0x7f);\n@@ -242,7 +262,6 @@ static int pcf8523_rtc_set_time(struct d\n \t\treturn err;\n \n \tregs[0] = REG_SECONDS;\n-\t/* This will purposely overwrite REG_SECONDS_OS */\n \tregs[1] = bin2bcd(tm->tm_sec);\n \tregs[2] = bin2bcd(tm->tm_min);\n \tregs[3] = bin2bcd(tm->tm_hour);\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0003-Revert-staging-bcm2835-audio-Drop-DT-dependency.patch",
    "content": "From 2aa4bd3751f6792bf00d59e4d9cd8a5550872cdb Mon Sep 17 00:00:00 2001\nFrom: popcornmix <popcornmix@gmail.com>\nDate: Fri, 15 Mar 2019 21:11:10 +0000\nSubject: [PATCH] Revert \"staging: bcm2835-audio: Drop DT dependency\"\n\nThis reverts commit b7491a9fca2dc2535b9dc922550a37c5baae9d3d.\n---\n .../vc04_services/bcm2835-audio/bcm2835.c     | 31 +++++++++++++------\n 1 file changed, 22 insertions(+), 9 deletions(-)\n\n--- a/drivers/staging/vc04_services/bcm2835-audio/bcm2835.c\n+++ b/drivers/staging/vc04_services/bcm2835-audio/bcm2835.c\n@@ -6,13 +6,13 @@\n #include <linux/init.h>\n #include <linux/slab.h>\n #include <linux/module.h>\n+#include <linux/of.h>\n \n #include \"bcm2835.h\"\n \n static bool enable_hdmi;\n static bool enable_headphones;\n static bool enable_compat_alsa = true;\n-static int num_channels = MAX_SUBSTREAMS;\n \n module_param(enable_hdmi, bool, 0444);\n MODULE_PARM_DESC(enable_hdmi, \"Enables HDMI virtual audio device\");\n@@ -21,8 +21,6 @@ MODULE_PARM_DESC(enable_headphones, \"Ena\n module_param(enable_compat_alsa, bool, 0444);\n MODULE_PARM_DESC(enable_compat_alsa,\n \t\t \"Enables ALSA compatibility virtual audio device\");\n-module_param(num_channels, int, 0644);\n-MODULE_PARM_DESC(num_channels, \"Number of audio channels (default: 8)\");\n \n static void bcm2835_devm_free_vchi_ctx(struct device *dev, void *res)\n {\n@@ -296,19 +294,28 @@ static int snd_add_child_devices(struct\n static int snd_bcm2835_alsa_probe(struct platform_device *pdev)\n {\n \tstruct device *dev = &pdev->dev;\n+\tu32 numchans;\n \tint err;\n \n-\tif (num_channels <= 0 || num_channels > MAX_SUBSTREAMS) {\n-\t\tnum_channels = MAX_SUBSTREAMS;\n-\t\tdev_warn(dev, \"Illegal num_channels value, will use %u\\n\",\n-\t\t\t num_channels);\n+\terr = of_property_read_u32(dev->of_node, \"brcm,pwm-channels\",\n+\t\t\t\t   &numchans);\n+\tif (err) {\n+\t\tdev_err(dev, \"Failed to get DT property 'brcm,pwm-channels'\");\n+\t\treturn err;\n+\t}\n+\n+\tif (numchans == 0 || numchans > MAX_SUBSTREAMS) {\n+\t\tnumchans = MAX_SUBSTREAMS;\n+\t\tdev_warn(dev,\n+\t\t\t \"Illegal 'brcm,pwm-channels' value, will use %u\\n\",\n+\t\t\t numchans);\n \t}\n \n \terr = bcm2835_devm_add_vchi_ctx(dev);\n \tif (err)\n \t\treturn err;\n \n-\terr = snd_add_child_devices(dev, num_channels);\n+\terr = snd_add_child_devices(dev, numchans);\n \tif (err)\n \t\treturn err;\n \n@@ -330,6 +337,12 @@ static int snd_bcm2835_alsa_resume(struc\n \n #endif\n \n+static const struct of_device_id snd_bcm2835_of_match_table[] = {\n+\t{ .compatible = \"brcm,bcm2835-audio\",},\n+\t{},\n+};\n+MODULE_DEVICE_TABLE(of, snd_bcm2835_of_match_table);\n+\n static struct platform_driver bcm2835_alsa_driver = {\n \t.probe = snd_bcm2835_alsa_probe,\n #ifdef CONFIG_PM\n@@ -338,6 +351,7 @@ static struct platform_driver bcm2835_al\n #endif\n \t.driver = {\n \t\t.name = \"bcm2835_audio\",\n+\t\t.of_match_table = snd_bcm2835_of_match_table,\n \t},\n };\n module_platform_driver(bcm2835_alsa_driver);\n@@ -345,4 +359,3 @@ module_platform_driver(bcm2835_alsa_driv\n MODULE_AUTHOR(\"Dom Cobley\");\n MODULE_DESCRIPTION(\"Alsa driver for BCM2835 chip\");\n MODULE_LICENSE(\"GPL\");\n-MODULE_ALIAS(\"platform:bcm2835_audio\");\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0004-Revert-spi-spidev-Fix-CS-polarity-if-GPIO-descriptor.patch",
    "content": "From 086a38a1e0eea3b7cbb207384b92d5dc82c62454 Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.com>\nDate: Mon, 20 Apr 2020 13:41:10 +0100\nSubject: [PATCH] Revert \"spi: spidev: Fix CS polarity if GPIO\n descriptors are used\"\n\nThis reverts commit 83b2a8fe43bda0c11981ad6afa5dd0104d78be28.\n---\n drivers/spi/spidev.c | 5 -----\n 1 file changed, 5 deletions(-)\n\n--- a/drivers/spi/spidev.c\n+++ b/drivers/spi/spidev.c\n@@ -402,7 +402,6 @@ spidev_ioctl(struct file *filp, unsigned\n \t\telse\n \t\t\tretval = get_user(tmp, (u32 __user *)arg);\n \t\tif (retval == 0) {\n-\t\t\tstruct spi_controller *ctlr = spi->controller;\n \t\t\tu32\tsave = spi->mode;\n \n \t\t\tif (tmp & ~SPI_MODE_MASK) {\n@@ -410,10 +409,6 @@ spidev_ioctl(struct file *filp, unsigned\n \t\t\t\tbreak;\n \t\t\t}\n \n-\t\t\tif (ctlr->use_gpio_descriptors && ctlr->cs_gpiods &&\n-\t\t\t    ctlr->cs_gpiods[spi->chip_select])\n-\t\t\t\ttmp |= SPI_CS_HIGH;\n-\n \t\t\ttmp |= spi->mode & ~SPI_MODE_MASK;\n \t\t\tspi->mode = (u16)tmp;\n \t\t\tretval = spi_setup(spi);\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0005-Revert-mailbox-avoid-timer-start-from-callback.patch",
    "content": "From a8fb0d43b8acd25d68a0d2c24fd0260393148447 Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.com>\nDate: Tue, 3 Nov 2020 11:49:53 +0000\nSubject: [PATCH] Revert \"mailbox: avoid timer start from callback\"\n\nThis reverts commit c7dacf5b0f32957b24ef29df1207dc2cd8307743.\n\nThe Pi 400 shutdown/poweroff mechanism relies on being able to set\na GPIO on the expander in the pm_power_off handler, something that\nrequires two mailbox calls - GET_GPIO_STATE and SET_GPIO_STATE. A\nrecent kernel change introduces a reasonable possibility that the\nGET call doesn't completes, and bisecting led to a commit from\nOctober that changes the timer usage of the mailbox.\n\nMy theory is that there is a race condition in the new code that breaks\nthe poll timer, but that it normally goes unnoticed because subsequent\nmailbox activity wakes it up again. The power-off mailbox calls happen\nat a time when other subsystems have been shut down, so if one of them\nfails then there is nothing to allow it to recover.\n\nSee: https://github.com/raspberrypi/linux/issues/3941\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.com>\n---\n drivers/mailbox/mailbox.c | 12 +++++-------\n 1 file changed, 5 insertions(+), 7 deletions(-)\n\n--- a/drivers/mailbox/mailbox.c\n+++ b/drivers/mailbox/mailbox.c\n@@ -82,12 +82,9 @@ static void msg_submit(struct mbox_chan\n exit:\n \tspin_unlock_irqrestore(&chan->lock, flags);\n \n-\t/* kick start the timer immediately to avoid delays */\n-\tif (!err && (chan->txdone_method & TXDONE_BY_POLL)) {\n-\t\t/* but only if not already active */\n-\t\tif (!hrtimer_active(&chan->mbox->poll_hrt))\n-\t\t\thrtimer_start(&chan->mbox->poll_hrt, 0, HRTIMER_MODE_REL);\n-\t}\n+\tif (!err && (chan->txdone_method & TXDONE_BY_POLL))\n+\t\t/* kick start the timer immediately to avoid delays */\n+\t\thrtimer_start(&chan->mbox->poll_hrt, 0, HRTIMER_MODE_REL);\n }\n \n static void tx_tick(struct mbox_chan *chan, int r)\n@@ -125,10 +122,11 @@ static enum hrtimer_restart txdone_hrtim\n \t\tstruct mbox_chan *chan = &mbox->chans[i];\n \n \t\tif (chan->active_req && chan->cl) {\n-\t\t\tresched = true;\n \t\t\ttxdone = chan->mbox->ops->last_tx_done(chan);\n \t\t\tif (txdone)\n \t\t\t\ttx_tick(chan, 0);\n+\t\t\telse\n+\t\t\t\tresched = true;\n \t\t}\n \t}\n \n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0006-smsx95xx-fix-crimes-against-truesize.patch",
    "content": "From dbfae4876cd4c8525a0100f19307f16cf7fb384a Mon Sep 17 00:00:00 2001\nFrom: Steve Glendinning <steve.glendinning@smsc.com>\nDate: Thu, 19 Feb 2015 18:47:12 +0000\nSubject: [PATCH] smsx95xx: fix crimes against truesize\n\nsmsc95xx is adjusting truesize when it shouldn't, and following a recent patch from Eric this is now triggering warnings.\n\nThis patch stops smsc95xx from changing truesize.\n\nSigned-off-by: Steve Glendinning <steve.glendinning@smsc.com>\n---\n drivers/net/usb/smsc95xx.c | 10 ++++++++--\n 1 file changed, 8 insertions(+), 2 deletions(-)\n\n--- a/drivers/net/usb/smsc95xx.c\n+++ b/drivers/net/usb/smsc95xx.c\n@@ -67,6 +67,10 @@ static bool turbo_mode = true;\n module_param(turbo_mode, bool, 0644);\n MODULE_PARM_DESC(turbo_mode, \"Enable multiple frames per Rx transaction\");\n \n+static bool truesize_mode = false;\n+module_param(truesize_mode, bool, 0644);\n+MODULE_PARM_DESC(truesize_mode, \"Report larger truesize value\");\n+\n static int __must_check __smsc95xx_read_reg(struct usbnet *dev, u32 index,\n \t\t\t\t\t    u32 *data, int in_pm)\n {\n@@ -1839,7 +1843,8 @@ static int smsc95xx_rx_fixup(struct usbn\n \t\t\t\tif (dev->net->features & NETIF_F_RXCSUM)\n \t\t\t\t\tsmsc95xx_rx_csum_offload(skb);\n \t\t\t\tskb_trim(skb, skb->len - 4); /* remove fcs */\n-\t\t\t\tskb->truesize = size + sizeof(struct sk_buff);\n+\t\t\t\tif (truesize_mode)\n+\t\t\t\t\tskb->truesize = size + sizeof(struct sk_buff);\n \n \t\t\t\treturn 1;\n \t\t\t}\n@@ -1857,7 +1862,8 @@ static int smsc95xx_rx_fixup(struct usbn\n \t\t\tif (dev->net->features & NETIF_F_RXCSUM)\n \t\t\t\tsmsc95xx_rx_csum_offload(ax_skb);\n \t\t\tskb_trim(ax_skb, ax_skb->len - 4); /* remove fcs */\n-\t\t\tax_skb->truesize = size + sizeof(struct sk_buff);\n+\t\t\tif (truesize_mode)\n+\t\t\t\tax_skb->truesize = size + sizeof(struct sk_buff);\n \n \t\t\tusbnet_skb_return(dev, ax_skb);\n \t\t}\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0007-smsc95xx-Experimental-Enable-turbo_mode-and-packetsi.patch",
    "content": "From 5792c081bb959c57b381439e40d07c919193a993 Mon Sep 17 00:00:00 2001\nFrom: Sam Nazarko <email@samnazarko.co.uk>\nDate: Fri, 1 Apr 2016 17:27:21 +0100\nSubject: [PATCH] smsc95xx: Experimental: Enable turbo_mode and\n packetsize=2560 by default\n\nSee: http://forum.kodi.tv/showthread.php?tid=285288\n---\n drivers/net/usb/smsc95xx.c | 14 +++++++++-----\n 1 file changed, 9 insertions(+), 5 deletions(-)\n\n--- a/drivers/net/usb/smsc95xx.c\n+++ b/drivers/net/usb/smsc95xx.c\n@@ -71,6 +71,10 @@ static bool truesize_mode = false;\n module_param(truesize_mode, bool, 0644);\n MODULE_PARM_DESC(truesize_mode, \"Report larger truesize value\");\n \n+static int packetsize = 2560;\n+module_param(packetsize, int, 0644);\n+MODULE_PARM_DESC(packetsize, \"Override the RX URB packet size\");\n+\n static int __must_check __smsc95xx_read_reg(struct usbnet *dev, u32 index,\n \t\t\t\t\t    u32 *data, int in_pm)\n {\n@@ -917,13 +921,13 @@ static int smsc95xx_reset(struct usbnet\n \n \tif (!turbo_mode) {\n \t\tburst_cap = 0;\n-\t\tdev->rx_urb_size = MAX_SINGLE_PACKET_SIZE;\n+\t\tdev->rx_urb_size = packetsize ? packetsize : MAX_SINGLE_PACKET_SIZE;\n \t} else if (dev->udev->speed == USB_SPEED_HIGH) {\n-\t\tburst_cap = DEFAULT_HS_BURST_CAP_SIZE / HS_USB_PKT_SIZE;\n-\t\tdev->rx_urb_size = DEFAULT_HS_BURST_CAP_SIZE;\n+\t\tdev->rx_urb_size = packetsize ? packetsize : DEFAULT_HS_BURST_CAP_SIZE;\n+\t\tburst_cap = dev->rx_urb_size / HS_USB_PKT_SIZE;\n \t} else {\n-\t\tburst_cap = DEFAULT_FS_BURST_CAP_SIZE / FS_USB_PKT_SIZE;\n-\t\tdev->rx_urb_size = DEFAULT_FS_BURST_CAP_SIZE;\n+\t\tdev->rx_urb_size = packetsize ? packetsize : DEFAULT_FS_BURST_CAP_SIZE;\n+\t\tburst_cap = dev->rx_urb_size / FS_USB_PKT_SIZE;\n \t}\n \n \tnetif_dbg(dev, ifup, dev->net, \"rx_urb_size=%ld\\n\",\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0008-Allow-mac-address-to-be-set-in-smsc95xx.patch",
    "content": "From a5e86e4e7cc86e6a24844d758d2258c8b23f18f0 Mon Sep 17 00:00:00 2001\nFrom: popcornmix <popcornmix@gmail.com>\nDate: Tue, 26 Mar 2013 17:26:38 +0000\nSubject: [PATCH] Allow mac address to be set in smsc95xx\n\nSigned-off-by: popcornmix <popcornmix@gmail.com>\n---\n drivers/net/usb/smsc95xx.c | 56 ++++++++++++++++++++++++++++++++++++++\n 1 file changed, 56 insertions(+)\n\n--- a/drivers/net/usb/smsc95xx.c\n+++ b/drivers/net/usb/smsc95xx.c\n@@ -50,6 +50,7 @@\n #define SUSPEND_SUSPEND3\t\t(0x08)\n #define SUSPEND_ALLMODES\t\t(SUSPEND_SUSPEND0 | SUSPEND_SUSPEND1 | \\\n \t\t\t\t\t SUSPEND_SUSPEND2 | SUSPEND_SUSPEND3)\n+#define MAC_ADDR_LEN                    (6)\n \n struct smsc95xx_priv {\n \tu32 mac_cr;\n@@ -75,6 +76,10 @@ static int packetsize = 2560;\n module_param(packetsize, int, 0644);\n MODULE_PARM_DESC(packetsize, \"Override the RX URB packet size\");\n \n+static char *macaddr = \":\";\n+module_param(macaddr, charp, 0);\n+MODULE_PARM_DESC(macaddr, \"MAC address\");\n+\n static int __must_check __smsc95xx_read_reg(struct usbnet *dev, u32 index,\n \t\t\t\t\t    u32 *data, int in_pm)\n {\n@@ -773,6 +778,53 @@ static int smsc95xx_ioctl(struct net_dev\n \treturn phy_mii_ioctl(netdev->phydev, rq, cmd);\n }\n \n+/* Check the macaddr module parameter for a MAC address */\n+static int smsc95xx_is_macaddr_param(struct usbnet *dev, u8 *dev_mac)\n+{\n+       int i, j, got_num, num;\n+       u8 mtbl[MAC_ADDR_LEN];\n+\n+       if (macaddr[0] == ':')\n+               return 0;\n+\n+       i = 0;\n+       j = 0;\n+       num = 0;\n+       got_num = 0;\n+       while (j < MAC_ADDR_LEN) {\n+               if (macaddr[i] && macaddr[i] != ':') {\n+                       got_num++;\n+                       if ('0' <= macaddr[i] && macaddr[i] <= '9')\n+                               num = num * 16 + macaddr[i] - '0';\n+                       else if ('A' <= macaddr[i] && macaddr[i] <= 'F')\n+                               num = num * 16 + 10 + macaddr[i] - 'A';\n+                       else if ('a' <= macaddr[i] && macaddr[i] <= 'f')\n+                               num = num * 16 + 10 + macaddr[i] - 'a';\n+                       else\n+                               break;\n+                       i++;\n+               } else if (got_num == 2) {\n+                       mtbl[j++] = (u8) num;\n+                       num = 0;\n+                       got_num = 0;\n+                       i++;\n+               } else {\n+                       break;\n+               }\n+       }\n+\n+       if (j == MAC_ADDR_LEN) {\n+               netif_dbg(dev, ifup, dev->net, \"Overriding MAC address with: \"\n+               \"%02x:%02x:%02x:%02x:%02x:%02x\\n\", mtbl[0], mtbl[1], mtbl[2],\n+                                               mtbl[3], mtbl[4], mtbl[5]);\n+               for (i = 0; i < MAC_ADDR_LEN; i++)\n+                       dev_mac[i] = mtbl[i];\n+               return 1;\n+       } else {\n+               return 0;\n+       }\n+}\n+\n static void smsc95xx_init_mac_address(struct usbnet *dev)\n {\n \t/* maybe the boot loader passed the MAC address in devicetree */\n@@ -795,6 +847,10 @@ static void smsc95xx_init_mac_address(st\n \t\t}\n \t}\n \n+\t/* Check module parameters */\n+\tif (smsc95xx_is_macaddr_param(dev, dev->net->dev_addr))\n+\t\treturn;\n+\n \t/* no useful static MAC address found. generate a random one */\n \teth_hw_addr_random(dev->net);\n \tnetif_dbg(dev, ifup, dev->net, \"MAC address set to eth_random_addr\\n\");\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0009-Protect-__release_resource-against-resources-without.patch",
    "content": "From f146f2bb597fe00b6c2e5da169a766dc8ab2a4fa Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.org>\nDate: Fri, 13 Mar 2015 12:43:36 +0000\nSubject: [PATCH] Protect __release_resource against resources without\n parents\n\nWithout this patch, removing a device tree overlay can crash here.\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.org>\n---\n kernel/resource.c | 6 ++++++\n 1 file changed, 6 insertions(+)\n\n--- a/kernel/resource.c\n+++ b/kernel/resource.c\n@@ -214,6 +214,12 @@ static int __release_resource(struct res\n {\n \tstruct resource *tmp, **p, *chd;\n \n+\tif (!old->parent) {\n+\t\tWARN(old->sibling, \"sibling but no parent\");\n+\t\tif (old->sibling)\n+\t\t\treturn -EINVAL;\n+\t\treturn 0;\n+\t}\n \tp = &old->parent->child;\n \tfor (;;) {\n \t\ttmp = *p;\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0010-irq-bcm2836-Avoid-Invalid-trigger-warning.patch",
    "content": "From 55a3a6691b480c57613f9db3a0e1aca02b7f68c1 Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.org>\nDate: Thu, 9 Feb 2017 14:33:30 +0000\nSubject: [PATCH] irq-bcm2836: Avoid \"Invalid trigger warning\"\n\nInitialise the level for each IRQ to avoid a warning from the\narm arch timer code.\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.org>\n---\n drivers/irqchip/irq-bcm2836.c | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/drivers/irqchip/irq-bcm2836.c\n+++ b/drivers/irqchip/irq-bcm2836.c\n@@ -128,7 +128,7 @@ static int bcm2836_map(struct irq_domain\n \tirq_set_percpu_devid(irq);\n \tirq_domain_set_info(d, irq, hw, chip, d->host_data,\n \t\t\t    handle_percpu_devid_irq, NULL, NULL);\n-\tirq_set_status_flags(irq, IRQ_NOAUTOEN);\n+\tirq_set_status_flags(irq, IRQ_NOAUTOEN | IRQ_TYPE_LEVEL_LOW);\n \n \treturn 0;\n }\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0011-irqchip-bcm2835-Add-FIQ-support.patch",
    "content": "From ad12646921360036adf7ecdcf1325b9a880b316a Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Noralf=20Tr=C3=B8nnes?= <noralf@tronnes.org>\nDate: Fri, 12 Jun 2015 19:01:05 +0200\nSubject: [PATCH] irqchip: bcm2835: Add FIQ support\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nAdd a duplicate irq range with an offset on the hwirq's so the\ndriver can detect that enable_fiq() is used.\nTested with downstream dwc_otg USB controller driver.\n\nSigned-off-by: Noralf Trønnes <noralf@tronnes.org>\nReviewed-by: Eric Anholt <eric@anholt.net>\nAcked-by: Stephen Warren <swarren@wwwdotorg.org>\n---\n arch/arm/mach-bcm/Kconfig     |  1 +\n drivers/irqchip/irq-bcm2835.c | 51 +++++++++++++++++++++++++++++++----\n 2 files changed, 47 insertions(+), 5 deletions(-)\n\n--- a/arch/arm/mach-bcm/Kconfig\n+++ b/arch/arm/mach-bcm/Kconfig\n@@ -161,6 +161,7 @@ config ARCH_BCM2835\n \tselect ARM_TIMER_SP804\n \tselect HAVE_ARM_ARCH_TIMER if ARCH_MULTI_V7\n \tselect BCM2835_TIMER\n+\tselect FIQ\n \tselect PINCTRL\n \tselect PINCTRL_BCM2835\n \tselect MFD_CORE\n--- a/drivers/irqchip/irq-bcm2835.c\n+++ b/drivers/irqchip/irq-bcm2835.c\n@@ -45,7 +45,7 @@\n #include <asm/exception.h>\n \n /* Put the bank and irq (32 bits) into the hwirq */\n-#define MAKE_HWIRQ(b, n)\t((b << 5) | (n))\n+#define MAKE_HWIRQ(b, n)\t(((b) << 5) | (n))\n #define HWIRQ_BANK(i)\t\t(i >> 5)\n #define HWIRQ_BIT(i)\t\tBIT(i & 0x1f)\n \n@@ -62,9 +62,13 @@\n \n #define REG_FIQ_CONTROL\t\t0x0c\n #define FIQ_CONTROL_ENABLE\tBIT(7)\n+#define REG_FIQ_ENABLE\t\tFIQ_CONTROL_ENABLE\n+#define REG_FIQ_DISABLE\t0\n \n #define NR_BANKS\t\t3\n #define IRQS_PER_BANK\t\t32\n+#define NUMBER_IRQS\t\tMAKE_HWIRQ(NR_BANKS, 0)\n+#define FIQ_START\t\t(NR_IRQS_BANK0 + MAKE_HWIRQ(NR_BANKS - 1, 0))\n \n static const int reg_pending[] __initconst = { 0x00, 0x04, 0x08 };\n static const int reg_enable[] __initconst = { 0x18, 0x10, 0x14 };\n@@ -89,14 +93,38 @@ static void __exception_irq_entry bcm283\n \tstruct pt_regs *regs);\n static void bcm2836_chained_handle_irq(struct irq_desc *desc);\n \n+static inline unsigned int hwirq_to_fiq(unsigned long hwirq)\n+{\n+\thwirq -= NUMBER_IRQS;\n+\t/*\n+\t * The hwirq numbering used in this driver is:\n+\t *   BASE (0-7) GPU1 (32-63) GPU2 (64-95).\n+\t * This differ from the one used in the FIQ register:\n+\t *   GPU1 (0-31) GPU2 (32-63) BASE (64-71)\n+\t */\n+\tif (hwirq >= 32)\n+\t\treturn hwirq - 32;\n+\n+\treturn hwirq + 64;\n+}\n+\n static void armctrl_mask_irq(struct irq_data *d)\n {\n-\twritel_relaxed(HWIRQ_BIT(d->hwirq), intc.disable[HWIRQ_BANK(d->hwirq)]);\n+\tif (d->hwirq >= NUMBER_IRQS)\n+\t\twritel_relaxed(REG_FIQ_DISABLE, intc.base + REG_FIQ_CONTROL);\n+\telse\n+\t\twritel_relaxed(HWIRQ_BIT(d->hwirq),\n+\t\t\t       intc.disable[HWIRQ_BANK(d->hwirq)]);\n }\n \n static void armctrl_unmask_irq(struct irq_data *d)\n {\n-\twritel_relaxed(HWIRQ_BIT(d->hwirq), intc.enable[HWIRQ_BANK(d->hwirq)]);\n+\tif (d->hwirq >= NUMBER_IRQS)\n+\t\twritel_relaxed(REG_FIQ_ENABLE | hwirq_to_fiq(d->hwirq),\n+\t\t\t       intc.base + REG_FIQ_CONTROL);\n+\telse\n+\t\twritel_relaxed(HWIRQ_BIT(d->hwirq),\n+\t\t\t       intc.enable[HWIRQ_BANK(d->hwirq)]);\n }\n \n static struct irq_chip armctrl_chip = {\n@@ -142,8 +170,9 @@ static int __init armctrl_of_init(struct\n \tif (!base)\n \t\tpanic(\"%pOF: unable to map IC registers\\n\", node);\n \n-\tintc.domain = irq_domain_add_linear(node, MAKE_HWIRQ(NR_BANKS, 0),\n-\t\t\t&armctrl_ops, NULL);\n+\tintc.base = base;\n+\tintc.domain = irq_domain_add_linear(node, NUMBER_IRQS * 2,\n+\t\t\t\t\t    &armctrl_ops, NULL);\n \tif (!intc.domain)\n \t\tpanic(\"%pOF: unable to create IRQ domain\\n\", node);\n \n@@ -186,6 +215,18 @@ static int __init armctrl_of_init(struct\n \t\tset_handle_irq(bcm2835_handle_irq);\n \t}\n \n+\t/* Make a duplicate irq range which is used to enable FIQ */\n+\tfor (b = 0; b < NR_BANKS; b++) {\n+\t\tfor (i = 0; i < bank_irqs[b]; i++) {\n+\t\t\tirq = irq_create_mapping(intc.domain,\n+\t\t\t\t\tMAKE_HWIRQ(b, i) + NUMBER_IRQS);\n+\t\t\tBUG_ON(irq <= 0);\n+\t\t\tirq_set_chip(irq, &armctrl_chip);\n+\t\t\tset_irq_flags(irq, IRQF_VALID | IRQF_PROBE);\n+\t\t}\n+\t}\n+\tinit_FIQ(FIQ_START);\n+\n \treturn 0;\n }\n \n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0012-irqchip-irq-bcm2835-Add-2836-FIQ-support.patch",
    "content": "From 18774f96f2766eb711d462842626ae603110c18e Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Noralf=20Tr=C3=B8nnes?= <noralf@tronnes.org>\nDate: Fri, 23 Oct 2015 16:26:55 +0200\nSubject: [PATCH] irqchip: irq-bcm2835: Add 2836 FIQ support\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nSigned-off-by: Noralf Trønnes <noralf@tronnes.org>\n---\n drivers/irqchip/irq-bcm2835.c | 43 +++++++++++++++++++++++++++++++++--\n 1 file changed, 41 insertions(+), 2 deletions(-)\n\n--- a/drivers/irqchip/irq-bcm2835.c\n+++ b/drivers/irqchip/irq-bcm2835.c\n@@ -41,8 +41,11 @@\n #include <linux/of_irq.h>\n #include <linux/irqchip.h>\n #include <linux/irqdomain.h>\n+#include <linux/mfd/syscon.h>\n+#include <linux/regmap.h>\n \n #include <asm/exception.h>\n+#include <asm/mach/irq.h>\n \n /* Put the bank and irq (32 bits) into the hwirq */\n #define MAKE_HWIRQ(b, n)\t(((b) << 5) | (n))\n@@ -60,6 +63,9 @@\n #define BANK0_VALID_MASK\t(BANK0_HWIRQ_MASK | BANK1_HWIRQ | BANK2_HWIRQ \\\n \t\t\t\t\t| SHORTCUT1_MASK | SHORTCUT2_MASK)\n \n+#undef ARM_LOCAL_GPU_INT_ROUTING\n+#define ARM_LOCAL_GPU_INT_ROUTING 0x0c\n+\n #define REG_FIQ_CONTROL\t\t0x0c\n #define FIQ_CONTROL_ENABLE\tBIT(7)\n #define REG_FIQ_ENABLE\t\tFIQ_CONTROL_ENABLE\n@@ -86,6 +92,7 @@ struct armctrl_ic {\n \tvoid __iomem *enable[NR_BANKS];\n \tvoid __iomem *disable[NR_BANKS];\n \tstruct irq_domain *domain;\n+\tstruct regmap *local_regmap;\n };\n \n static struct armctrl_ic intc __read_mostly;\n@@ -119,12 +126,35 @@ static void armctrl_mask_irq(struct irq_\n \n static void armctrl_unmask_irq(struct irq_data *d)\n {\n-\tif (d->hwirq >= NUMBER_IRQS)\n+\tif (d->hwirq >= NUMBER_IRQS) {\n+\t\tif (num_online_cpus() > 1) {\n+\t\t\tunsigned int data;\n+\t\t\tint ret;\n+\n+\t\t\tif (!intc.local_regmap) {\n+\t\t\t\tpr_err(\"FIQ is disabled due to missing regmap\\n\");\n+\t\t\t\treturn;\n+\t\t\t}\n+\n+\t\t\tret = regmap_read(intc.local_regmap,\n+\t\t\t\t\t  ARM_LOCAL_GPU_INT_ROUTING, &data);\n+\t\t\tif (ret) {\n+\t\t\t\tpr_err(\"Failed to read int routing %d\\n\", ret);\n+\t\t\t\treturn;\n+\t\t\t}\n+\n+\t\t\tdata &= ~0xc;\n+\t\t\tdata |= (1 << 2);\n+\t\t\tregmap_write(intc.local_regmap,\n+\t\t\t\t     ARM_LOCAL_GPU_INT_ROUTING, data);\n+\t\t}\n+\n \t\twritel_relaxed(REG_FIQ_ENABLE | hwirq_to_fiq(d->hwirq),\n \t\t\t       intc.base + REG_FIQ_CONTROL);\n-\telse\n+\t} else {\n \t\twritel_relaxed(HWIRQ_BIT(d->hwirq),\n \t\t\t       intc.enable[HWIRQ_BANK(d->hwirq)]);\n+\t}\n }\n \n static struct irq_chip armctrl_chip = {\n@@ -215,6 +245,15 @@ static int __init armctrl_of_init(struct\n \t\tset_handle_irq(bcm2835_handle_irq);\n \t}\n \n+\tif (is_2836) {\n+\t\tintc.local_regmap =\n+\t\t\tsyscon_regmap_lookup_by_compatible(\"brcm,bcm2836-arm-local\");\n+\t\tif (IS_ERR(intc.local_regmap)) {\n+\t\t\tpr_err(\"Failed to get local register map. FIQ is disabled for cpus > 1\\n\");\n+\t\t\tintc.local_regmap = NULL;\n+\t\t}\n+\t}\n+\n \t/* Make a duplicate irq range which is used to enable FIQ */\n \tfor (b = 0; b < NR_BANKS; b++) {\n \t\tfor (i = 0; i < bank_irqs[b]; i++) {\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0013-spi-spidev-Completely-disable-the-spidev-warning.patch",
    "content": "From 8469be136aebf9fe06746ec47e4495c77d5522f5 Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.org>\nDate: Tue, 14 Jul 2015 10:26:09 +0100\nSubject: [PATCH] spi: spidev: Completely disable the spidev warning\n\nAn alternative strategy would be to use \"rpi,spidev\" instead, but that\nwould require many Raspberry Pi Device Tree changes.\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.org>\n---\n drivers/spi/spidev.c | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/drivers/spi/spidev.c\n+++ b/drivers/spi/spidev.c\n@@ -733,7 +733,7 @@ static int spidev_probe(struct spi_devic\n \t * compatible string, it is a Linux implementation thing\n \t * rather than a description of the hardware.\n \t */\n-\tWARN(spi->dev.of_node &&\n+\tWARN(0 && spi->dev.of_node &&\n \t     of_device_is_compatible(spi->dev.of_node, \"spidev\"),\n \t     \"%pOF: buggy DT: spidev listed directly in DT\\n\", spi->dev.of_node);\n \n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0014-dmaengine-bcm2835-Load-driver-early-and-support-lega.patch",
    "content": "From 1fafff0383c50bbbb2d5bb3205923904f3f55ce8 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Noralf=20Tr=C3=B8nnes?= <noralf@tronnes.org>\nDate: Sat, 3 Oct 2015 22:22:55 +0200\nSubject: [PATCH] dmaengine: bcm2835: Load driver early and support\n legacy API\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nLoad driver early since at least bcm2708_fb doesn't support deferred\nprobing and even if it did, we don't want the video driver deferred.\nSupport the legacy DMA API which is needed by bcm2708_fb.\nDon't mask out channel 2.\n\nSigned-off-by: Noralf Trønnes <noralf@tronnes.org>\n---\n drivers/dma/Kconfig       |  2 +-\n drivers/dma/bcm2835-dma.c | 26 +++++++++++++++++++++++++-\n 2 files changed, 26 insertions(+), 2 deletions(-)\n\n--- a/drivers/dma/Kconfig\n+++ b/drivers/dma/Kconfig\n@@ -134,7 +134,7 @@ config COH901318\n \n config DMA_BCM2835\n \ttristate \"BCM2835 DMA engine support\"\n-\tdepends on ARCH_BCM2835\n+\tdepends on ARCH_BCM2835 || ARCH_BCM2708 || ARCH_BCM2709\n \tselect DMA_ENGINE\n \tselect DMA_VIRTUAL_CHANNELS\n \n--- a/drivers/dma/bcm2835-dma.c\n+++ b/drivers/dma/bcm2835-dma.c\n@@ -25,6 +25,7 @@\n #include <linux/interrupt.h>\n #include <linux/list.h>\n #include <linux/module.h>\n+#include <linux/platform_data/dma-bcm2708.h>\n #include <linux/platform_device.h>\n #include <linux/slab.h>\n #include <linux/io.h>\n@@ -36,6 +37,7 @@\n \n #define BCM2835_DMA_MAX_DMA_CHAN_SUPPORTED 14\n #define BCM2835_DMA_CHAN_NAME_SIZE 8\n+#define BCM2835_DMA_BULK_MASK  BIT(0)\n \n /**\n  * struct bcm2835_dmadev - BCM2835 DMA controller\n@@ -906,6 +908,9 @@ static int bcm2835_dma_probe(struct plat\n \tbase = devm_ioremap_resource(&pdev->dev, res);\n \tif (IS_ERR(base))\n \t\treturn PTR_ERR(base);\n+\trc = bcm_dmaman_probe(pdev, base, BCM2835_DMA_BULK_MASK);\n+\tif (rc)\n+\t\tdev_err(&pdev->dev, \"Failed to initialize the legacy API\\n\");\n \n \tod->base = base;\n \n@@ -951,6 +956,9 @@ static int bcm2835_dma_probe(struct plat\n \t\tgoto err_no_dma;\n \t}\n \n+\t/* Channel 0 is used by the legacy API */\n+\tchans_available &= ~BCM2835_DMA_BULK_MASK;\n+\n \t/* get irqs for each channel that we support */\n \tfor (i = 0; i <= BCM2835_DMA_MAX_DMA_CHAN_SUPPORTED; i++) {\n \t\t/* skip masked out channels */\n@@ -1025,6 +1033,7 @@ static int bcm2835_dma_remove(struct pla\n {\n \tstruct bcm2835_dmadev *od = platform_get_drvdata(pdev);\n \n+\tbcm_dmaman_remove(pdev);\n \tdma_async_device_unregister(&od->ddev);\n \tbcm2835_dma_free(od);\n \n@@ -1040,7 +1049,22 @@ static struct platform_driver bcm2835_dm\n \t},\n };\n \n-module_platform_driver(bcm2835_dma_driver);\n+static int bcm2835_dma_init(void)\n+{\n+\treturn platform_driver_register(&bcm2835_dma_driver);\n+}\n+\n+static void bcm2835_dma_exit(void)\n+{\n+\tplatform_driver_unregister(&bcm2835_dma_driver);\n+}\n+\n+/*\n+ * Load after serial driver (arch_initcall) so we see the messages if it fails,\n+ * but before drivers (module_init) that need a DMA channel.\n+ */\n+subsys_initcall(bcm2835_dma_init);\n+module_exit(bcm2835_dma_exit);\n \n MODULE_ALIAS(\"platform:bcm2835-dma\");\n MODULE_DESCRIPTION(\"BCM2835 DMA engine driver\");\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0015-firmware-Updated-mailbox-header.patch",
    "content": "From b7ad81911a06fd8047ca36c07bd49d8317833502 Mon Sep 17 00:00:00 2001\nFrom: popcornmix <popcornmix@gmail.com>\nDate: Mon, 25 Jan 2016 17:25:12 +0000\nSubject: [PATCH] firmware: Updated mailbox header\n\n---\n include/soc/bcm2835/raspberrypi-firmware.h | 3 +++\n 1 file changed, 3 insertions(+)\n\n--- a/include/soc/bcm2835/raspberrypi-firmware.h\n+++ b/include/soc/bcm2835/raspberrypi-firmware.h\n@@ -9,6 +9,8 @@\n #include <linux/types.h>\n #include <linux/of_device.h>\n \n+#define RPI_FIRMWARE_CHAN_FB\t\t1\n+\n struct rpi_firmware;\n \n enum rpi_firmware_property_status {\n@@ -161,5 +163,6 @@ static inline struct rpi_firmware *rpi_f\n \treturn NULL;\n }\n #endif\n+int rpi_firmware_transaction(struct rpi_firmware *fw, u32 chan, u32 data);\n \n #endif /* __SOC_RASPBERRY_FIRMWARE_H__ */\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0016-rtc-Add-SPI-alias-for-pcf2123-driver.patch",
    "content": "From d9fa2c594a6dfd5f538c50eaa6a06449d06c5a8e Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.org>\nDate: Wed, 15 Jun 2016 16:48:41 +0100\nSubject: [PATCH] rtc: Add SPI alias for pcf2123 driver\n\nWithout this alias, Device Tree won't cause the driver\nto be loaded.\n\nSee: https://github.com/raspberrypi/linux/pull/1510\n---\n drivers/rtc/rtc-pcf2123.c | 1 +\n 1 file changed, 1 insertion(+)\n\n--- a/drivers/rtc/rtc-pcf2123.c\n+++ b/drivers/rtc/rtc-pcf2123.c\n@@ -465,3 +465,4 @@ module_spi_driver(pcf2123_driver);\n MODULE_AUTHOR(\"Chris Verges <chrisv@cyberswitching.com>\");\n MODULE_DESCRIPTION(\"NXP PCF2123 RTC driver\");\n MODULE_LICENSE(\"GPL\");\n+MODULE_ALIAS(\"spi:rtc-pcf2123\");\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0017-watchdog-bcm2835-Support-setting-reboot-partition.patch",
    "content": "From 351b9cbfc6aed837c7e23462d7109372de22e2bb Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Noralf=20Tr=C3=B8nnes?= <noralf@tronnes.org>\nDate: Fri, 7 Oct 2016 16:50:59 +0200\nSubject: [PATCH] watchdog: bcm2835: Support setting reboot partition\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nThe Raspberry Pi firmware looks at the RSTS register to know which\npartition to boot from. The reboot syscall command\nLINUX_REBOOT_CMD_RESTART2 supports passing in a string argument.\n\nAdd support for passing in a partition number 0..63 to boot from.\nPartition 63 is a special partiton indicating halt.\nIf the partition doesn't exist, the firmware falls back to partition 0.\n\nSigned-off-by: Noralf Trønnes <noralf@tronnes.org>\n---\n drivers/watchdog/bcm2835_wdt.c | 49 +++++++++++++++++++---------------\n 1 file changed, 27 insertions(+), 22 deletions(-)\n\n--- a/drivers/watchdog/bcm2835_wdt.c\n+++ b/drivers/watchdog/bcm2835_wdt.c\n@@ -32,13 +32,7 @@\n #define PM_RSTC_WRCFG_SET\t\t0x00000030\n #define PM_RSTC_WRCFG_FULL_RESET\t0x00000020\n #define PM_RSTC_RESET\t\t\t0x00000102\n-\n-/*\n- * The Raspberry Pi firmware uses the RSTS register to know which partition\n- * to boot from. The partition value is spread into bits 0, 2, 4, 6, 8, 10.\n- * Partition 63 is a special partition used by the firmware to indicate halt.\n- */\n-#define PM_RSTS_RASPBERRYPI_HALT\t0x555\n+#define PM_RSTS_PARTITION_CLR          0xfffffaaa\n \n #define SECS_TO_WDOG_TICKS(x) ((x) << 16)\n #define WDOG_TICKS_TO_SECS(x) ((x) >> 16)\n@@ -97,9 +91,24 @@ static unsigned int bcm2835_wdt_get_time\n \treturn WDOG_TICKS_TO_SECS(ret & PM_WDOG_TIME_SET);\n }\n \n-static void __bcm2835_restart(struct bcm2835_wdt *wdt)\n+/*\n+ * The Raspberry Pi firmware uses the RSTS register to know which partiton\n+ * to boot from. The partiton value is spread into bits 0, 2, 4, 6, 8, 10.\n+ * Partiton 63 is a special partition used by the firmware to indicate halt.\n+ */\n+\n+static void __bcm2835_restart(struct bcm2835_wdt *wdt, u8 partition)\n {\n-\tu32 val;\n+\tu32 val, rsts;\n+\n+\trsts = (partition & BIT(0)) | ((partition & BIT(1)) << 1) |\n+\t       ((partition & BIT(2)) << 2) | ((partition & BIT(3)) << 3) |\n+\t       ((partition & BIT(4)) << 4) | ((partition & BIT(5)) << 5);\n+\n+\tval = readl_relaxed(wdt->base + PM_RSTS);\n+\tval &= PM_RSTS_PARTITION_CLR;\n+\tval |= PM_PASSWORD | rsts;\n+\twritel_relaxed(val, wdt->base + PM_RSTS);\n \n \t/* use a timeout of 10 ticks (~150us) */\n \twritel_relaxed(10 | PM_PASSWORD, wdt->base + PM_WDOG);\n@@ -117,7 +126,13 @@ static int bcm2835_restart(struct watchd\n {\n \tstruct bcm2835_wdt *wdt = watchdog_get_drvdata(wdog);\n \n-\t__bcm2835_restart(wdt);\n+\tunsigned long long val;\n+\tu8 partition = 0;\n+\n+\tif (data && !kstrtoull(data, 0, &val) && val <= 63)\n+\t\tpartition = val;\n+\n+\t__bcm2835_restart(wdt, partition);\n \n \treturn 0;\n }\n@@ -152,19 +167,9 @@ static struct watchdog_device bcm2835_wd\n static void bcm2835_power_off(void)\n {\n \tstruct bcm2835_wdt *wdt = bcm2835_power_off_wdt;\n-\tu32 val;\n-\n-\t/*\n-\t * We set the watchdog hard reset bit here to distinguish this reset\n-\t * from the normal (full) reset. bootcode.bin will not reboot after a\n-\t * hard reset.\n-\t */\n-\tval = readl_relaxed(wdt->base + PM_RSTS);\n-\tval |= PM_PASSWORD | PM_RSTS_RASPBERRYPI_HALT;\n-\twritel_relaxed(val, wdt->base + PM_RSTS);\n \n-\t/* Continue with normal reset mechanism */\n-\t__bcm2835_restart(wdt);\n+\t/* Partition 63 tells the firmware that this is a halt */\n+\t__bcm2835_restart(wdt, 63);\n }\n \n static int bcm2835_wdt_probe(struct platform_device *pdev)\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0018-reboot-Use-power-off-rather-than-busy-spinning-when-.patch",
    "content": "From e722eb6ced1ad7a162782fe10dd5d4225a6b4e0d Mon Sep 17 00:00:00 2001\nFrom: popcornmix <popcornmix@gmail.com>\nDate: Tue, 5 Apr 2016 19:40:12 +0100\nSubject: [PATCH] reboot: Use power off rather than busy spinning when\n halt is requested\n\n---\n arch/arm/kernel/reboot.c | 4 +---\n 1 file changed, 1 insertion(+), 3 deletions(-)\n\n--- a/arch/arm/kernel/reboot.c\n+++ b/arch/arm/kernel/reboot.c\n@@ -102,9 +102,7 @@ void machine_shutdown(void)\n  */\n void machine_halt(void)\n {\n-\tlocal_irq_disable();\n-\tsmp_send_stop();\n-\twhile (1);\n+\tmachine_power_off();\n }\n \n /*\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0019-bcm-Make-RASPBERRYPI_POWER-depend-on-PM.patch",
    "content": "From 0bc33dc51825662d4fc7a46c5e622de00e5cbf80 Mon Sep 17 00:00:00 2001\nFrom: popcornmix <popcornmix@gmail.com>\nDate: Wed, 9 Nov 2016 13:02:52 +0000\nSubject: [PATCH] bcm: Make RASPBERRYPI_POWER depend on PM\n\n---\n drivers/soc/bcm/Kconfig | 1 +\n 1 file changed, 1 insertion(+)\n\n--- a/drivers/soc/bcm/Kconfig\n+++ b/drivers/soc/bcm/Kconfig\n@@ -17,6 +17,7 @@ config RASPBERRYPI_POWER\n \tbool \"Raspberry Pi power domain driver\"\n \tdepends on ARCH_BCM2835 || (COMPILE_TEST && OF)\n \tdepends on RASPBERRYPI_FIRMWARE=y\n+\tdepends on PM\n \tselect PM_GENERIC_DOMAINS if PM\n \thelp\n \t  This enables support for the RPi power domains which can be enabled\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0020-Register-the-clocks-early-during-the-boot-process-so.patch",
    "content": "From 41e34cd05d40eca6674e25eb9a85e5f7992d4e83 Mon Sep 17 00:00:00 2001\nFrom: Martin Sperl <kernel@martin.sperl.org>\nDate: Fri, 2 Sep 2016 16:45:27 +0100\nSubject: [PATCH] Register the clocks early during the boot process, so\n that special/critical clocks can get enabled early on in the boot process\n avoiding the risk of disabling a clock, pll_divider or pll when a claiming\n driver fails to install propperly - maybe it needs to defer.\n\nSigned-off-by: Martin Sperl <kernel@martin.sperl.org>\n---\n drivers/clk/bcm/clk-bcm2835.c | 15 +++++++++++++--\n 1 file changed, 13 insertions(+), 2 deletions(-)\n\n--- a/drivers/clk/bcm/clk-bcm2835.c\n+++ b/drivers/clk/bcm/clk-bcm2835.c\n@@ -2290,8 +2290,15 @@ static int bcm2835_clk_probe(struct plat\n \tif (ret)\n \t\treturn ret;\n \n-\treturn of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,\n+\tret = of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,\n \t\t\t\t      &cprman->onecell);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\t/* note that we have registered all the clocks */\n+\tdev_dbg(dev, \"registered %d clocks\\n\", asize);\n+\n+\treturn 0;\n }\n \n static const struct cprman_plat_data cprman_bcm2835_plat_data = {\n@@ -2317,7 +2324,11 @@ static struct platform_driver bcm2835_cl\n \t.probe          = bcm2835_clk_probe,\n };\n \n-builtin_platform_driver(bcm2835_clk_driver);\n+static int __init __bcm2835_clk_driver_init(void)\n+{\n+\treturn platform_driver_register(&bcm2835_clk_driver);\n+}\n+core_initcall(__bcm2835_clk_driver_init);\n \n MODULE_AUTHOR(\"Eric Anholt <eric@anholt.net>\");\n MODULE_DESCRIPTION(\"BCM2835 clock driver\");\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0021-bcm2835-rng-Avoid-initialising-if-already-enabled.patch",
    "content": "From 102d9fbd0a8d762835a9f9a7917e9eace3a9d84e Mon Sep 17 00:00:00 2001\nFrom: popcornmix <popcornmix@gmail.com>\nDate: Tue, 6 Dec 2016 17:05:39 +0000\nSubject: [PATCH] bcm2835-rng: Avoid initialising if already enabled\n\nAvoids the 0x40000 cycles of warmup again if firmware has already used it\n---\n drivers/char/hw_random/bcm2835-rng.c | 6 ++++--\n 1 file changed, 4 insertions(+), 2 deletions(-)\n\n--- a/drivers/char/hw_random/bcm2835-rng.c\n+++ b/drivers/char/hw_random/bcm2835-rng.c\n@@ -102,8 +102,10 @@ static int bcm2835_rng_init(struct hwrng\n \t}\n \n \t/* set warm-up count & enable */\n-\trng_writel(priv, RNG_WARMUP_COUNT, RNG_STATUS);\n-\trng_writel(priv, RNG_RBGEN, RNG_CTRL);\n+\tif (!(rng_readl(priv, RNG_CTRL) & RNG_RBGEN)) {\n+\t\trng_writel(priv, RNG_WARMUP_COUNT, RNG_STATUS);\n+\t\trng_writel(priv, RNG_RBGEN, RNG_CTRL);\n+\t}\n \n \treturn ret;\n }\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0022-clk-bcm2835-Mark-used-PLLs-and-dividers-CRITICAL.patch",
    "content": "From 3af9c4ed5775b7675e679a80a381eafe2ce726ae Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.org>\nDate: Mon, 13 Feb 2017 17:20:08 +0000\nSubject: [PATCH] clk-bcm2835: Mark used PLLs and dividers CRITICAL\n\nThe VPU configures and relies on several PLLs and dividers. Mark all\nenabled dividers and their PLLs as CRITICAL to prevent the kernel from\nswitching them off.\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.org>\n---\n drivers/clk/bcm/clk-bcm2835.c | 5 +++++\n 1 file changed, 5 insertions(+)\n\n--- a/drivers/clk/bcm/clk-bcm2835.c\n+++ b/drivers/clk/bcm/clk-bcm2835.c\n@@ -1379,6 +1379,11 @@ bcm2835_register_pll_divider(struct bcm2\n \tdivider->div.hw.init = &init;\n \tdivider->div.table = NULL;\n \n+\tif (!(cprman_read(cprman, data->cm_reg) & data->hold_mask)) {\n+\t\tinit.flags |= CLK_IS_CRITICAL;\n+\t\tdivider->div.flags |= CLK_IS_CRITICAL;\n+\t}\n+\n \tdivider->cprman = cprman;\n \tdivider->data = divider_data;\n \n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0023-clk-bcm2835-Add-claim-clocks-property.patch",
    "content": "From 05cae664e29e510111cf24f2beb1c31cba09bcce Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.org>\nDate: Mon, 13 Feb 2017 17:20:08 +0000\nSubject: [PATCH] clk-bcm2835: Add claim-clocks property\n\nThe claim-clocks property can be used to prevent PLLs and dividers\nfrom being marked as critical. It contains a vector of clock IDs,\nas defined by dt-bindings/clock/bcm2835.h.\n\nUse this mechanism to claim PLLD_DSI0, PLLD_DSI1, PLLH_AUX and\nPLLH_PIX for the vc4_kms_v3d driver.\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.org>\n---\n drivers/clk/bcm/clk-bcm2835.c | 45 ++++++++++++++++++++++++++++++++---\n 1 file changed, 42 insertions(+), 3 deletions(-)\n\n--- a/drivers/clk/bcm/clk-bcm2835.c\n+++ b/drivers/clk/bcm/clk-bcm2835.c\n@@ -1307,6 +1307,8 @@ static const struct clk_ops bcm2835_vpu_\n \t.debug_init = bcm2835_clock_debug_init,\n };\n \n+static bool bcm2835_clk_is_claimed(const char *name);\n+\n static struct clk_hw *bcm2835_register_pll(struct bcm2835_cprman *cprman,\n \t\t\t\t\t   const void *data)\n {\n@@ -1324,6 +1326,9 @@ static struct clk_hw *bcm2835_register_p\n \tinit.ops = &bcm2835_pll_clk_ops;\n \tinit.flags = pll_data->flags | CLK_IGNORE_UNUSED;\n \n+\tif (!bcm2835_clk_is_claimed(pll_data->name))\n+\t\tinit.flags |= CLK_IS_CRITICAL;\n+\n \tpll = kzalloc(sizeof(*pll), GFP_KERNEL);\n \tif (!pll)\n \t\treturn NULL;\n@@ -1379,9 +1384,11 @@ bcm2835_register_pll_divider(struct bcm2\n \tdivider->div.hw.init = &init;\n \tdivider->div.table = NULL;\n \n-\tif (!(cprman_read(cprman, data->cm_reg) & data->hold_mask)) {\n-\t\tinit.flags |= CLK_IS_CRITICAL;\n-\t\tdivider->div.flags |= CLK_IS_CRITICAL;\n+\tif (!(cprman_read(cprman, divider_data->cm_reg) & divider_data->hold_mask)) {\n+\t\tif (!bcm2835_clk_is_claimed(divider_data->source_pll))\n+\t\t\tinit.flags |= CLK_IS_CRITICAL;\n+\t\tif (!bcm2835_clk_is_claimed(divider_data->name))\n+\t\t\tdivider->div.flags |= CLK_IS_CRITICAL;\n \t}\n \n \tdivider->cprman = cprman;\n@@ -1438,6 +1445,15 @@ static struct clk_hw *bcm2835_register_c\n \tinit.flags = clock_data->flags | CLK_IGNORE_UNUSED;\n \n \t/*\n+\t * Some GPIO clocks for ethernet/wifi PLLs are marked as\n+\t * critical (since some platforms use them), but if the\n+\t * firmware didn't have them turned on then they clearly\n+\t * aren't actually critical.\n+\t */\n+\tif ((cprman_read(cprman, clock_data->ctl_reg) & CM_ENABLE) == 0)\n+\t\tinit.flags &= ~CLK_IS_CRITICAL;\n+\n+\t/*\n \t * Pass the CLK_SET_RATE_PARENT flag if we are allowed to propagate\n \t * rate changes on at least of the parents.\n \t */\n@@ -2216,6 +2232,8 @@ static const struct bcm2835_clk_desc clk\n \t\t.ctl_reg = CM_PERIICTL),\n };\n \n+static bool bcm2835_clk_claimed[ARRAY_SIZE(clk_desc_array)];\n+\n /*\n  * Permanently take a reference on the parent of the SDRAM clock.\n  *\n@@ -2235,6 +2253,19 @@ static int bcm2835_mark_sdc_parent_criti\n \treturn clk_prepare_enable(parent);\n }\n \n+static bool bcm2835_clk_is_claimed(const char *name)\n+{\n+\tint i;\n+\n+\tfor (i = 0; i < ARRAY_SIZE(clk_desc_array); i++) {\n+\t\tconst char *clk_name = *(const char **)(clk_desc_array[i].data);\n+\t\tif (!strcmp(name, clk_name))\n+\t\t    return bcm2835_clk_claimed[i];\n+\t}\n+\n+\treturn false;\n+}\n+\n static int bcm2835_clk_probe(struct platform_device *pdev)\n {\n \tstruct device *dev = &pdev->dev;\n@@ -2244,6 +2275,7 @@ static int bcm2835_clk_probe(struct plat\n \tconst size_t asize = ARRAY_SIZE(clk_desc_array);\n \tconst struct cprman_plat_data *pdata;\n \tsize_t i;\n+\tu32 clk_id;\n \tint ret;\n \n \tpdata = of_device_get_match_data(&pdev->dev);\n@@ -2262,6 +2294,13 @@ static int bcm2835_clk_probe(struct plat\n \tif (IS_ERR(cprman->regs))\n \t\treturn PTR_ERR(cprman->regs);\n \n+\tmemset(bcm2835_clk_claimed, 0, sizeof(bcm2835_clk_claimed));\n+\tfor (i = 0;\n+\t     !of_property_read_u32_index(pdev->dev.of_node, \"claim-clocks\",\n+\t\t\t\t\t i, &clk_id);\n+\t     i++)\n+\t\tbcm2835_clk_claimed[clk_id]= true;\n+\n \tmemcpy(cprman->real_parent_names, cprman_parent_names,\n \t       sizeof(cprman_parent_names));\n \tof_clk_parent_fill(dev->of_node, cprman->real_parent_names,\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0024-clk-bcm2835-Read-max-core-clock-from-firmware.patch",
    "content": "From 6ac8a6c58b51d02780b7a1fc882df33ae2560798 Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.org>\nDate: Mon, 6 Mar 2017 09:06:18 +0000\nSubject: [PATCH] clk-bcm2835: Read max core clock from firmware\n\nThe VPU is responsible for managing the core clock, usually under\ndirection from the bcm2835-cpufreq driver but not via the clk-bcm2835\ndriver. Since the core frequency can change without warning, it is\nsafer to report the maximum clock rate to users of the core clock -\nI2C, SPI and the mini UART - to err on the safe side when calculating\nclock divisors.\n\nIf the DT node for the clock driver includes a reference to the\nfirmware node, use the firmware API to query the maximum core clock\ninstead of reading the divider registers.\n\nPrior to this patch, a \"100KHz\" I2C bus was sometimes clocked at about\n160KHz. In particular, switching to the 4.9 kernel was likely to break\nSenseHAT usage on a Pi3.\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.org>\n---\n drivers/clk/bcm/clk-bcm2835.c | 39 ++++++++++++++++++++++++++++++++++-\n 1 file changed, 38 insertions(+), 1 deletion(-)\n\n--- a/drivers/clk/bcm/clk-bcm2835.c\n+++ b/drivers/clk/bcm/clk-bcm2835.c\n@@ -35,6 +35,7 @@\n #include <linux/platform_device.h>\n #include <linux/slab.h>\n #include <dt-bindings/clock/bcm2835.h>\n+#include <soc/bcm2835/raspberrypi-firmware.h>\n \n #define CM_PASSWORD\t\t0x5a000000\n \n@@ -295,6 +296,8 @@\n #define SOC_BCM2711\t\tBIT(1)\n #define SOC_ALL\t\t\t(SOC_BCM2835 | SOC_BCM2711)\n \n+#define VCMSG_ID_CORE_CLOCK     4\n+\n /*\n  * Names of clocks used within the driver that need to be replaced\n  * with an external parent's name.  This array is in the order that\n@@ -313,6 +316,7 @@ static const char *const cprman_parent_n\n struct bcm2835_cprman {\n \tstruct device *dev;\n \tvoid __iomem *regs;\n+\tstruct rpi_firmware *fw;\n \tspinlock_t regs_lock; /* spinlock for all clocks */\n \tunsigned int soc;\n \n@@ -1011,6 +1015,30 @@ static unsigned long bcm2835_clock_get_r\n \treturn bcm2835_clock_rate_from_divisor(clock, parent_rate, div);\n }\n \n+static unsigned long bcm2835_clock_get_rate_vpu(struct clk_hw *hw,\n+\t\t\t\t\t\tunsigned long parent_rate)\n+{\n+\tstruct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);\n+\tstruct bcm2835_cprman *cprman = clock->cprman;\n+\n+\tif (cprman->fw) {\n+\t\tstruct {\n+\t\t\tu32 id;\n+\t\t\tu32 val;\n+\t\t} packet;\n+\n+\t\tpacket.id = VCMSG_ID_CORE_CLOCK;\n+\t\tpacket.val = 0;\n+\n+\t\tif (!rpi_firmware_property(cprman->fw,\n+\t\t\t\t\t   RPI_FIRMWARE_GET_MAX_CLOCK_RATE,\n+\t\t\t\t\t   &packet, sizeof(packet)))\n+\t\t\treturn packet.val;\n+\t}\n+\n+\treturn bcm2835_clock_get_rate(hw, parent_rate);\n+}\n+\n static void bcm2835_clock_wait_busy(struct bcm2835_clock *clock)\n {\n \tstruct bcm2835_cprman *cprman = clock->cprman;\n@@ -1299,7 +1327,7 @@ static int bcm2835_vpu_clock_is_on(struc\n  */\n static const struct clk_ops bcm2835_vpu_clock_clk_ops = {\n \t.is_prepared = bcm2835_vpu_clock_is_on,\n-\t.recalc_rate = bcm2835_clock_get_rate,\n+\t.recalc_rate = bcm2835_clock_get_rate_vpu,\n \t.set_rate = bcm2835_clock_set_rate,\n \t.determine_rate = bcm2835_clock_determine_rate,\n \t.set_parent = bcm2835_clock_set_parent,\n@@ -2274,6 +2302,7 @@ static int bcm2835_clk_probe(struct plat\n \tconst struct bcm2835_clk_desc *desc;\n \tconst size_t asize = ARRAY_SIZE(clk_desc_array);\n \tconst struct cprman_plat_data *pdata;\n+\tstruct device_node *fw_node;\n \tsize_t i;\n \tu32 clk_id;\n \tint ret;\n@@ -2294,6 +2323,14 @@ static int bcm2835_clk_probe(struct plat\n \tif (IS_ERR(cprman->regs))\n \t\treturn PTR_ERR(cprman->regs);\n \n+\tfw_node = of_parse_phandle(dev->of_node, \"firmware\", 0);\n+\tif (fw_node) {\n+\t\tstruct rpi_firmware *fw = rpi_firmware_get(NULL);\n+\t\tif (!fw)\n+\t\t\treturn -EPROBE_DEFER;\n+\t\tcprman->fw = fw;\n+\t}\n+\n \tmemset(bcm2835_clk_claimed, 0, sizeof(bcm2835_clk_claimed));\n \tfor (i = 0;\n \t     !of_property_read_u32_index(pdev->dev.of_node, \"claim-clocks\",\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0025-sound-Demote-deferral-errors-to-INFO-level.patch",
    "content": "From 2a0e0c15c001bfde3666f159552e414217fe44ac Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.org>\nDate: Thu, 9 Feb 2017 14:36:44 +0000\nSubject: [PATCH] sound: Demote deferral errors to INFO level\n\nAt present there is no mechanism to specify driver load order,\nwhich can lead to deferrals and repeated retries until successful.\nSince this situation is expected, reduce the dmesg level to\nINFO and mention that the operation will be retried.\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.org>\n---\n sound/soc/soc-core.c | 4 ++--\n 1 file changed, 2 insertions(+), 2 deletions(-)\n\n--- a/sound/soc/soc-core.c\n+++ b/sound/soc/soc-core.c\n@@ -1016,7 +1016,7 @@ int snd_soc_add_pcm_runtime(struct snd_s\n \tfor_each_link_cpus(dai_link, i, cpu) {\n \t\tasoc_rtd_to_cpu(rtd, i) = snd_soc_find_dai(cpu);\n \t\tif (!asoc_rtd_to_cpu(rtd, i)) {\n-\t\t\tdev_info(card->dev, \"ASoC: CPU DAI %s not registered\\n\",\n+\t\t\tdev_info(card->dev, \"ASoC: CPU DAI %s not registered - will retry\\n\",\n \t\t\t\t cpu->dai_name);\n \t\t\tgoto _err_defer;\n \t\t}\n@@ -1027,7 +1027,7 @@ int snd_soc_add_pcm_runtime(struct snd_s\n \tfor_each_link_codecs(dai_link, i, codec) {\n \t\tasoc_rtd_to_codec(rtd, i) = snd_soc_find_dai(codec);\n \t\tif (!asoc_rtd_to_codec(rtd, i)) {\n-\t\t\tdev_info(card->dev, \"ASoC: CODEC DAI %s not registered\\n\",\n+\t\t\tdev_info(card->dev, \"ASoC: CODEC DAI %s not registered- will retry\\n\",\n \t\t\t\t codec->dai_name);\n \t\t\tgoto _err_defer;\n \t\t}\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0026-Update-vfpmodule.c.patch",
    "content": "From 55f18cc01fc9c93999ea935f7d869d136f5204ed Mon Sep 17 00:00:00 2001\nFrom: Claggy3 <stephen.maclagan@hotmail.com>\nDate: Sat, 11 Feb 2017 14:00:30 +0000\nSubject: [PATCH] Update vfpmodule.c\n\nChristopher Alexander Tobias Schulze - May 2, 2015, 11:57 a.m.\nThis patch fixes a problem with VFP state save and restore related\nto exception handling (panic with message \"BUG: unsupported FP\ninstruction in kernel mode\") present on VFP11 floating point units\n(as used with ARM1176JZF-S CPUs, e.g. on first generation Raspberry\nPi boards). This patch was developed and discussed on\n\n   https://github.com/raspberrypi/linux/issues/859\n\nA precondition to see the crashes is that floating point exception\ntraps are enabled. In this case, the VFP11 might determine that a FPU\noperation needs to trap at a point in time when it is not possible to\nsignal this to the ARM11 core any more. The VFP11 will then set the\nFPEXC.EX bit and store the trapped opcode in FPINST. (In some cases,\na second opcode might have been accepted by the VFP11 before the\nexception was detected and could be reported to the ARM11 - in this\ncase, the VFP11 also sets FPEXC.FP2V and stores the second opcode in\nFPINST2.)\n\nIf FPEXC.EX is set, the VFP11 will \"bounce\" the next FPU opcode issued\nby the ARM11 CPU, which will be seen by the ARM11 as an undefined opcode\ntrap. The VFP support code examines the FPEXC.EX and FPEXC.FP2V bits\nto decide what actions to take, i.e., whether to emulate the opcodes\nfound in FPINST and FPINST2, and whether to retry the bounced instruction.\n\nIf a user space application has left the VFP11 in this \"pending trap\"\nstate, the next FPU opcode issued to the VFP11 might actually be the\nVSTMIA operation vfp_save_state() uses to store the FPU registers\nto memory (in our test cases, when building the signal stack frame).\nIn this case, the kernel crashes as described above.\n\nThis patch fixes the problem by making sure that vfp_save_state() is\nalways entered with FPEXC.EX cleared. (The current value of FPEXC has\nalready been saved, so this does not corrupt the context. Clearing\nFPEXC.EX has no effects on FPINST or FPINST2. Also note that many\ncallers already modify FPEXC by setting FPEXC.EN before invoking\nvfp_save_state().)\n\nThis patch also addresses a second problem related to FPEXC.EX: After\nreturning from signal handling, the kernel reloads the VFP context\nfrom the user mode stack. However, the current code explicitly clears\nboth FPEXC.EX and FPEXC.FP2V during reload. As VFP11 requires these\nbits to be preserved, this patch disables clearing them for VFP\nimplementations belonging to architecture 1. There should be no\nnegative side effects: the user can set both bits by executing FPU\nopcodes anyway, and while user code may now place arbitrary values\ninto FPINST and FPINST2 (e.g., non-VFP ARM opcodes) the VFP support\ncode knows which instructions can be emulated, and rejects other\nopcodes with \"unhandled bounce\" messages, so there should be no\nsecurity impact from allowing reloading FPEXC.EX and FPEXC.FP2V.\n\nSigned-off-by: Christopher Alexander Tobias Schulze <cat.schulze@alice-dsl.net>\n---\n arch/arm/vfp/vfpmodule.c | 25 +++++++++++++++++++------\n 1 file changed, 19 insertions(+), 6 deletions(-)\n\n--- a/arch/arm/vfp/vfpmodule.c\n+++ b/arch/arm/vfp/vfpmodule.c\n@@ -176,8 +176,11 @@ static int vfp_notifier(struct notifier_\n \t\t * case the thread migrates to a different CPU. The\n \t\t * restoring is done lazily.\n \t\t */\n-\t\tif ((fpexc & FPEXC_EN) && vfp_current_hw_state[cpu])\n+\t\tif ((fpexc & FPEXC_EN) && vfp_current_hw_state[cpu]) {\n+\t\t\t/* vfp_save_state oopses on VFP11 if EX bit set */\n+\t\t\tfmxr(FPEXC, fpexc & ~FPEXC_EX);\n \t\t\tvfp_save_state(vfp_current_hw_state[cpu], fpexc);\n+\t\t}\n #endif\n \n \t\t/*\n@@ -454,13 +457,16 @@ static int vfp_pm_suspend(void)\n \t/* if vfp is on, then save state for resumption */\n \tif (fpexc & FPEXC_EN) {\n \t\tpr_debug(\"%s: saving vfp state\\n\", __func__);\n+\t\t/* vfp_save_state oopses on VFP11 if EX bit set */\n+\t\tfmxr(FPEXC, fpexc & ~FPEXC_EX);\n \t\tvfp_save_state(&ti->vfpstate, fpexc);\n \n \t\t/* disable, just in case */\n \t\tfmxr(FPEXC, fmrx(FPEXC) & ~FPEXC_EN);\n \t} else if (vfp_current_hw_state[ti->cpu]) {\n #ifndef CONFIG_SMP\n-\t\tfmxr(FPEXC, fpexc | FPEXC_EN);\n+\t\t/* vfp_save_state oopses on VFP11 if EX bit set */\n+\t\tfmxr(FPEXC, (fpexc & ~FPEXC_EX) | FPEXC_EN);\n \t\tvfp_save_state(vfp_current_hw_state[ti->cpu], fpexc);\n \t\tfmxr(FPEXC, fpexc);\n #endif\n@@ -523,7 +529,8 @@ void vfp_sync_hwstate(struct thread_info\n \t\t/*\n \t\t * Save the last VFP state on this CPU.\n \t\t */\n-\t\tfmxr(FPEXC, fpexc | FPEXC_EN);\n+\t\t/* vfp_save_state oopses on VFP11 if EX bit set */\n+\t\tfmxr(FPEXC, (fpexc & ~FPEXC_EX) | FPEXC_EN);\n \t\tvfp_save_state(&thread->vfpstate, fpexc | FPEXC_EN);\n \t\tfmxr(FPEXC, fpexc);\n \t}\n@@ -589,6 +596,7 @@ int vfp_restore_user_hwstate(struct user\n \tstruct thread_info *thread = current_thread_info();\n \tstruct vfp_hard_struct *hwstate = &thread->vfpstate.hard;\n \tunsigned long fpexc;\n+\tu32 fpsid = fmrx(FPSID);\n \n \t/* Disable VFP to avoid corrupting the new thread state. */\n \tvfp_flush_hwstate(thread);\n@@ -611,8 +619,12 @@ int vfp_restore_user_hwstate(struct user\n \t/* Ensure the VFP is enabled. */\n \tfpexc |= FPEXC_EN;\n \n-\t/* Ensure FPINST2 is invalid and the exception flag is cleared. */\n-\tfpexc &= ~(FPEXC_EX | FPEXC_FP2V);\n+\t/* Mask FPXEC_EX and FPEXC_FP2V if not required by VFP arch */\n+\tif ((fpsid & FPSID_ARCH_MASK) != (1 << FPSID_ARCH_BIT)) {\n+\t\t/* Ensure FPINST2 is invalid and the exception flag is cleared. */\n+\t\tfpexc &= ~(FPEXC_EX | FPEXC_FP2V);\n+\t}\n+\n \thwstate->fpexc = fpexc;\n \n \thwstate->fpinst = ufp_exc->fpinst;\n@@ -726,7 +738,8 @@ void kernel_neon_begin(void)\n \tcpu = get_cpu();\n \n \tfpexc = fmrx(FPEXC) | FPEXC_EN;\n-\tfmxr(FPEXC, fpexc);\n+\t/* vfp_save_state oopses on VFP11 if EX bit set */\n+\tfmxr(FPEXC, fpexc & ~FPEXC_EX);\n \n \t/*\n \t * Save the userland NEON/VFP state. Under UP,\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0027-i2c-bcm2835-Add-debug-support.patch",
    "content": "From ee7f5d2470712e25e2bde81ead7c191a3eff41e2 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Noralf=20Tr=C3=B8nnes?= <noralf@tronnes.org>\nDate: Tue, 1 Nov 2016 15:15:41 +0100\nSubject: [PATCH] i2c: bcm2835: Add debug support\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nThis adds a debug module parameter to aid in debugging transfer issues\nby printing info to the kernel log. When enabled, status values are\ncollected in the interrupt routine and msg info in\nbcm2835_i2c_start_transfer(). This is done in a way that tries to avoid\naffecting timing. Having printk in the isr can mask issues.\n\ndebug values (additive):\n1: Print info on error\n2: Print info on all transfers\n3: Print messages before transfer is started\n\nThe value can be changed at runtime:\n/sys/module/i2c_bcm2835/parameters/debug\n\nExample output, debug=3:\n[  747.114448] bcm2835_i2c_xfer: msg(1/2) write addr=0x54, len=2 flags= [i2c1]\n[  747.114463] bcm2835_i2c_xfer: msg(2/2) read addr=0x54, len=32 flags= [i2c1]\n[  747.117809] start_transfer: msg(1/2) write addr=0x54, len=2 flags= [i2c1]\n[  747.117825] isr: remain=2, status=0x30000055 : TA TXW TXD TXE  [i2c1]\n[  747.117839] start_transfer: msg(2/2) read addr=0x54, len=32 flags= [i2c1]\n[  747.117849] isr: remain=32, status=0xd0000039 : TA RXR TXD RXD  [i2c1]\n[  747.117861] isr: remain=20, status=0xd0000039 : TA RXR TXD RXD  [i2c1]\n[  747.117870] isr: remain=8, status=0x32 : DONE TXD RXD  [i2c1]\n\nSigned-off-by: Noralf Trønnes <noralf@tronnes.org>\n---\n drivers/i2c/busses/i2c-bcm2835.c | 99 +++++++++++++++++++++++++++++++-\n 1 file changed, 98 insertions(+), 1 deletion(-)\n\n--- a/drivers/i2c/busses/i2c-bcm2835.c\n+++ b/drivers/i2c/busses/i2c-bcm2835.c\n@@ -56,6 +56,18 @@\n #define BCM2835_I2C_CDIV_MIN\t0x0002\n #define BCM2835_I2C_CDIV_MAX\t0xFFFE\n \n+static unsigned int debug;\n+module_param(debug, uint, 0644);\n+MODULE_PARM_DESC(debug, \"1=err, 2=isr, 3=xfer\");\n+\n+#define BCM2835_DEBUG_MAX\t512\n+struct bcm2835_debug {\n+\tstruct i2c_msg *msg;\n+\tint msg_idx;\n+\tsize_t remain;\n+\tu32 status;\n+};\n+\n struct bcm2835_i2c_dev {\n \tstruct device *dev;\n \tvoid __iomem *regs;\n@@ -68,8 +80,78 @@ struct bcm2835_i2c_dev {\n \tu32 msg_err;\n \tu8 *msg_buf;\n \tsize_t msg_buf_remaining;\n+\tstruct bcm2835_debug debug[BCM2835_DEBUG_MAX];\n+\tunsigned int debug_num;\n+\tunsigned int debug_num_msgs;\n };\n \n+static inline void bcm2835_debug_add(struct bcm2835_i2c_dev *i2c_dev, u32 s)\n+{\n+\tif (!i2c_dev->debug_num_msgs || i2c_dev->debug_num >= BCM2835_DEBUG_MAX)\n+\t\treturn;\n+\n+\ti2c_dev->debug[i2c_dev->debug_num].msg = i2c_dev->curr_msg;\n+\ti2c_dev->debug[i2c_dev->debug_num].msg_idx =\n+\t\t\t\ti2c_dev->debug_num_msgs - i2c_dev->num_msgs;\n+\ti2c_dev->debug[i2c_dev->debug_num].remain = i2c_dev->msg_buf_remaining;\n+\ti2c_dev->debug[i2c_dev->debug_num].status = s;\n+\ti2c_dev->debug_num++;\n+}\n+\n+static void bcm2835_debug_print_status(struct bcm2835_i2c_dev *i2c_dev,\n+\t\t\t\t       struct bcm2835_debug *d)\n+{\n+\tu32 s = d->status;\n+\n+\tpr_info(\"isr: remain=%zu, status=0x%x : %s%s%s%s%s%s%s%s%s%s [i2c%d]\\n\",\n+\t\td->remain, s,\n+\t\ts & BCM2835_I2C_S_TA ? \"TA \" : \"\",\n+\t\ts & BCM2835_I2C_S_DONE ? \"DONE \" : \"\",\n+\t\ts & BCM2835_I2C_S_TXW ? \"TXW \" : \"\",\n+\t\ts & BCM2835_I2C_S_RXR ? \"RXR \" : \"\",\n+\t\ts & BCM2835_I2C_S_TXD ? \"TXD \" : \"\",\n+\t\ts & BCM2835_I2C_S_RXD ? \"RXD \" : \"\",\n+\t\ts & BCM2835_I2C_S_TXE ? \"TXE \" : \"\",\n+\t\ts & BCM2835_I2C_S_RXF ? \"RXF \" : \"\",\n+\t\ts & BCM2835_I2C_S_ERR ? \"ERR \" : \"\",\n+\t\ts & BCM2835_I2C_S_CLKT ? \"CLKT \" : \"\",\n+\t\ti2c_dev->adapter.nr);\n+}\n+\n+static void bcm2835_debug_print_msg(struct bcm2835_i2c_dev *i2c_dev,\n+\t\t\t\t    struct i2c_msg *msg, int i, int total,\n+\t\t\t\t    const char *fname)\n+{\n+\tpr_info(\"%s: msg(%d/%d) %s addr=0x%02x, len=%u flags=%s%s%s%s%s%s%s [i2c%d]\\n\",\n+\t\tfname, i, total,\n+\t\tmsg->flags & I2C_M_RD ? \"read\" : \"write\", msg->addr, msg->len,\n+\t\tmsg->flags & I2C_M_TEN ? \"TEN\" : \"\",\n+\t\tmsg->flags & I2C_M_RECV_LEN ? \"RECV_LEN\" : \"\",\n+\t\tmsg->flags & I2C_M_NO_RD_ACK ? \"NO_RD_ACK\" : \"\",\n+\t\tmsg->flags & I2C_M_IGNORE_NAK ? \"IGNORE_NAK\" : \"\",\n+\t\tmsg->flags & I2C_M_REV_DIR_ADDR ? \"REV_DIR_ADDR\" : \"\",\n+\t\tmsg->flags & I2C_M_NOSTART ? \"NOSTART\" : \"\",\n+\t\tmsg->flags & I2C_M_STOP ? \"STOP\" : \"\",\n+\t\ti2c_dev->adapter.nr);\n+}\n+\n+static void bcm2835_debug_print(struct bcm2835_i2c_dev *i2c_dev)\n+{\n+\tstruct bcm2835_debug *d;\n+\tunsigned int i;\n+\n+\tfor (i = 0; i < i2c_dev->debug_num; i++) {\n+\t\td = &i2c_dev->debug[i];\n+\t\tif (d->status == ~0)\n+\t\t\tbcm2835_debug_print_msg(i2c_dev, d->msg, d->msg_idx,\n+\t\t\t\ti2c_dev->debug_num_msgs, \"start_transfer\");\n+\t\telse\n+\t\t\tbcm2835_debug_print_status(i2c_dev, d);\n+\t}\n+\tif (i2c_dev->debug_num >= BCM2835_DEBUG_MAX)\n+\t\tpr_info(\"BCM2835_DEBUG_MAX reached\\n\");\n+}\n+\n static inline void bcm2835_i2c_writel(struct bcm2835_i2c_dev *i2c_dev,\n \t\t\t\t      u32 reg, u32 val)\n {\n@@ -257,6 +339,7 @@ static void bcm2835_i2c_start_transfer(s\n \tbcm2835_i2c_writel(i2c_dev, BCM2835_I2C_A, msg->addr);\n \tbcm2835_i2c_writel(i2c_dev, BCM2835_I2C_DLEN, msg->len);\n \tbcm2835_i2c_writel(i2c_dev, BCM2835_I2C_C, c);\n+\tbcm2835_debug_add(i2c_dev, ~0);\n }\n \n static void bcm2835_i2c_finish_transfer(struct bcm2835_i2c_dev *i2c_dev)\n@@ -283,6 +366,7 @@ static irqreturn_t bcm2835_i2c_isr(int t\n \tu32 val, err;\n \n \tval = bcm2835_i2c_readl(i2c_dev, BCM2835_I2C_S);\n+\tbcm2835_debug_add(i2c_dev, val);\n \n \terr = val & (BCM2835_I2C_S_CLKT | BCM2835_I2C_S_ERR);\n \tif (err) {\n@@ -349,6 +433,13 @@ static int bcm2835_i2c_xfer(struct i2c_a\n \tunsigned long time_left;\n \tint i;\n \n+\tif (debug)\n+\t\ti2c_dev->debug_num_msgs = num;\n+\n+\tif (debug > 2)\n+\t\tfor (i = 0; i < num; i++)\n+\t\t\tbcm2835_debug_print_msg(i2c_dev, &msgs[i], i + 1, num, __func__);\n+\n \tfor (i = 0; i < (num - 1); i++)\n \t\tif (msgs[i].flags & I2C_M_RD) {\n \t\t\tdev_warn_once(i2c_dev->dev,\n@@ -367,6 +458,10 @@ static int bcm2835_i2c_xfer(struct i2c_a\n \n \tbcm2835_i2c_finish_transfer(i2c_dev);\n \n+\tif (debug > 1 || (debug && (!time_left || i2c_dev->msg_err)))\n+\t\tbcm2835_debug_print(i2c_dev);\n+\ti2c_dev->debug_num_msgs = 0;\n+\ti2c_dev->debug_num = 0;\n \tif (!time_left) {\n \t\tbcm2835_i2c_writel(i2c_dev, BCM2835_I2C_C,\n \t\t\t\t   BCM2835_I2C_C_CLEAR);\n@@ -377,7 +472,9 @@ static int bcm2835_i2c_xfer(struct i2c_a\n \tif (!i2c_dev->msg_err)\n \t\treturn num;\n \n-\tdev_dbg(i2c_dev->dev, \"i2c transfer failed: %x\\n\", i2c_dev->msg_err);\n+\tif (debug)\n+\t\tdev_err(i2c_dev->dev, \"i2c transfer failed: %x\\n\",\n+\t\t\ti2c_dev->msg_err);\n \n \tif (i2c_dev->msg_err & BCM2835_I2C_S_ERR)\n \t\treturn -EREMOTEIO;\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0028-mm-Remove-the-PFN-busy-warning.patch",
    "content": "From a432a3f7142e7e76fd1708debe509ffbea3a3658 Mon Sep 17 00:00:00 2001\nFrom: Eric Anholt <eric@anholt.net>\nDate: Thu, 18 Dec 2014 16:07:15 -0800\nSubject: [PATCH] mm: Remove the PFN busy warning\n\nSee commit dae803e165a11bc88ca8dbc07a11077caf97bbcb -- the warning is\nexpected sometimes when using CMA.  However, that commit still spams\nmy kernel log with these warnings.\n\nSigned-off-by: Eric Anholt <eric@anholt.net>\n---\n mm/page_alloc.c | 2 --\n 1 file changed, 2 deletions(-)\n\n--- a/mm/page_alloc.c\n+++ b/mm/page_alloc.c\n@@ -8603,8 +8603,6 @@ int alloc_contig_range(unsigned long sta\n \n \t/* Make sure the range is really isolated. */\n \tif (test_pages_isolated(outer_start, end, 0)) {\n-\t\tpr_info_ratelimited(\"%s: [%lx, %lx) PFNs busy\\n\",\n-\t\t\t__func__, outer_start, end);\n \t\tret = -EBUSY;\n \t\tgoto done;\n \t}\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0029-irqchip-irq-bcm2836-Remove-regmap-and-syscon-use.patch",
    "content": "From 9ab633ec6dd4bb60c13486c8474cf30045c0a422 Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.org>\nDate: Tue, 23 Jan 2018 16:52:45 +0000\nSubject: [PATCH] irqchip: irq-bcm2836: Remove regmap and syscon use\n\nThe syscon node defines a register range that duplicates that used by\nthe local_intc node on bcm2836/7. Since irq-bcm2835 and irq-bcm2836 are\nbuilt in and always present together (both drivers are enabled by\nCONFIG_ARCH_BCM2835), it is possible to replace the syscon usage with a\nglobal variable that simplifies the code. Doing so does lose the\nlocking provided by regmap, but as only one side is using the regmap\ninterface (irq-bcm2835 uses readl and write) there is no loss of\natomicity.\n\nSee: https://github.com/raspberrypi/firmware/issues/926\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.org>\n---\n drivers/irqchip/irq-bcm2835.c | 32 ++++++++++++--------------------\n drivers/irqchip/irq-bcm2836.c |  5 +++++\n 2 files changed, 17 insertions(+), 20 deletions(-)\n\n--- a/drivers/irqchip/irq-bcm2835.c\n+++ b/drivers/irqchip/irq-bcm2835.c\n@@ -41,8 +41,6 @@\n #include <linux/of_irq.h>\n #include <linux/irqchip.h>\n #include <linux/irqdomain.h>\n-#include <linux/mfd/syscon.h>\n-#include <linux/regmap.h>\n \n #include <asm/exception.h>\n #include <asm/mach/irq.h>\n@@ -92,7 +90,7 @@ struct armctrl_ic {\n \tvoid __iomem *enable[NR_BANKS];\n \tvoid __iomem *disable[NR_BANKS];\n \tstruct irq_domain *domain;\n-\tstruct regmap *local_regmap;\n+\tvoid __iomem *local_base;\n };\n \n static struct armctrl_ic intc __read_mostly;\n@@ -129,24 +127,20 @@ static void armctrl_unmask_irq(struct ir\n \tif (d->hwirq >= NUMBER_IRQS) {\n \t\tif (num_online_cpus() > 1) {\n \t\t\tunsigned int data;\n-\t\t\tint ret;\n \n-\t\t\tif (!intc.local_regmap) {\n-\t\t\t\tpr_err(\"FIQ is disabled due to missing regmap\\n\");\n+\t\t\tif (!intc.local_base) {\n+\t\t\t\tpr_err(\"FIQ is disabled due to missing arm_local_intc\\n\");\n \t\t\t\treturn;\n \t\t\t}\n \n-\t\t\tret = regmap_read(intc.local_regmap,\n-\t\t\t\t\t  ARM_LOCAL_GPU_INT_ROUTING, &data);\n-\t\t\tif (ret) {\n-\t\t\t\tpr_err(\"Failed to read int routing %d\\n\", ret);\n-\t\t\t\treturn;\n-\t\t\t}\n+\t\t\tdata = readl_relaxed(intc.local_base +\n+\t\t\t\t\t     ARM_LOCAL_GPU_INT_ROUTING);\n \n \t\t\tdata &= ~0xc;\n \t\t\tdata |= (1 << 2);\n-\t\t\tregmap_write(intc.local_regmap,\n-\t\t\t\t     ARM_LOCAL_GPU_INT_ROUTING, data);\n+\t\t\twritel_relaxed(data,\n+\t\t\t\t       intc.local_base +\n+\t\t\t\t       ARM_LOCAL_GPU_INT_ROUTING);\n \t\t}\n \n \t\twritel_relaxed(REG_FIQ_ENABLE | hwirq_to_fiq(d->hwirq),\n@@ -246,12 +240,10 @@ static int __init armctrl_of_init(struct\n \t}\n \n \tif (is_2836) {\n-\t\tintc.local_regmap =\n-\t\t\tsyscon_regmap_lookup_by_compatible(\"brcm,bcm2836-arm-local\");\n-\t\tif (IS_ERR(intc.local_regmap)) {\n-\t\t\tpr_err(\"Failed to get local register map. FIQ is disabled for cpus > 1\\n\");\n-\t\t\tintc.local_regmap = NULL;\n-\t\t}\n+\t\textern void __iomem * __attribute__((weak)) arm_local_intc;\n+\t\tintc.local_base = arm_local_intc;\n+\t\tif (!intc.local_base)\n+\t\t\tpr_err(\"Failed to get local intc base. FIQ is disabled for cpus > 1\\n\");\n \t}\n \n \t/* Make a duplicate irq range which is used to enable FIQ */\n--- a/drivers/irqchip/irq-bcm2836.c\n+++ b/drivers/irqchip/irq-bcm2836.c\n@@ -22,6 +22,9 @@ struct bcm2836_arm_irqchip_intc {\n \n static struct bcm2836_arm_irqchip_intc intc  __read_mostly;\n \n+void __iomem *arm_local_intc;\n+EXPORT_SYMBOL_GPL(arm_local_intc);\n+\n static void bcm2836_arm_irqchip_mask_per_cpu_irq(unsigned int reg_offset,\n \t\t\t\t\t\t unsigned int bit,\n \t\t\t\t\t\t int cpu)\n@@ -323,6 +326,8 @@ static int __init bcm2836_arm_irqchip_l1\n \t\tpanic(\"%pOF: unable to map local interrupt registers\\n\", node);\n \t}\n \n+\tarm_local_intc = intc.base;\n+\n \tbcm2835_init_local_timer_frequency();\n \n \tintc.domain = irq_domain_add_linear(node, LAST_IRQ + 1,\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0030-lan78xx-Enable-LEDs-and-auto-negotiation.patch",
    "content": "From 021908b753875198daddfa9e77a0d2fd8004a469 Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.org>\nDate: Tue, 17 Oct 2017 15:04:29 +0100\nSubject: [PATCH] lan78xx: Enable LEDs and auto-negotiation\n\nFor applications of the LAN78xx that don't have valid programmed\nEEPROMs or OTPs, enabling both LEDs and auto-negotiation by default\nseems reasonable.\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.org>\n---\n drivers/net/usb/lan78xx.c | 11 +++++++++++\n 1 file changed, 11 insertions(+)\n\n--- a/drivers/net/usb/lan78xx.c\n+++ b/drivers/net/usb/lan78xx.c\n@@ -2463,6 +2463,11 @@ static int lan78xx_reset(struct lan78xx_\n \tint ret = 0;\n \tunsigned long timeout;\n \tu8 sig;\n+\tbool has_eeprom;\n+\tbool has_otp;\n+\n+\thas_eeprom = !lan78xx_read_eeprom(dev, 0, 0, NULL);\n+\thas_otp = !lan78xx_read_otp(dev, 0, 0, NULL);\n \n \tret = lan78xx_read_reg(dev, HW_CFG, &buf);\n \tbuf |= HW_CFG_LRST_;\n@@ -2516,6 +2521,9 @@ static int lan78xx_reset(struct lan78xx_\n \n \tret = lan78xx_read_reg(dev, HW_CFG, &buf);\n \tbuf |= HW_CFG_MEF_;\n+\t/* If no valid EEPROM and no valid OTP, enable the LEDs by default */\n+\tif (!has_eeprom && !has_otp)\n+\t    buf |= HW_CFG_LED0_EN_ | HW_CFG_LED1_EN_;\n \tret = lan78xx_write_reg(dev, HW_CFG, buf);\n \n \tret = lan78xx_read_reg(dev, USB_CFG0, &buf);\n@@ -2571,6 +2579,9 @@ static int lan78xx_reset(struct lan78xx_\n \t\t\tbuf |= MAC_CR_AUTO_DUPLEX_ | MAC_CR_AUTO_SPEED_;\n \t\t}\n \t}\n+\t/* If no valid EEPROM and no valid OTP, enable AUTO negotiation */\n+\tif (!has_eeprom && !has_otp)\n+\t    buf |= MAC_CR_AUTO_DUPLEX_ | MAC_CR_AUTO_SPEED_;\n \tret = lan78xx_write_reg(dev, MAC_CR, buf);\n \n \tret = lan78xx_read_reg(dev, MAC_TX, &buf);\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0031-amba_pl011-Don-t-use-DT-aliases-for-numbering.patch",
    "content": "From a79b4327445a827be28b9939592da8e812a19b29 Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.org>\nDate: Tue, 23 Feb 2016 17:26:48 +0000\nSubject: [PATCH] amba_pl011: Don't use DT aliases for numbering\n\nThe pl011 driver looks for DT aliases of the form \"serial<n>\",\nand if found uses <n> as the device ID. This can cause\n/dev/ttyAMA0 to become /dev/ttyAMA1, which is confusing if the\nother serial port is provided by the 8250 driver which doesn't\nuse the same logic.\n---\n drivers/tty/serial/amba-pl011.c | 5 +++++\n 1 file changed, 5 insertions(+)\n\n--- a/drivers/tty/serial/amba-pl011.c\n+++ b/drivers/tty/serial/amba-pl011.c\n@@ -2578,7 +2578,12 @@ static int pl011_setup_port(struct devic\n \tif (IS_ERR(base))\n \t\treturn PTR_ERR(base);\n \n+\t/* Don't use DT serial<n> aliases - it causes the device to\n+\t   be renumbered to ttyAMA1 if it is the second serial port in the\n+\t   system, even though the other one is ttyS0. The 8250 driver\n+\t   doesn't use this logic, so always remains ttyS0.\n \tindex = pl011_probe_dt_alias(index, dev);\n+\t*/\n \n \tuap->old_cr = 0;\n \tuap->port.dev = dev;\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0032-amba_pl011-Round-input-clock-up.patch",
    "content": "From e3f28ae66fd94f4a7a10099a96d6dd5273904943 Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.org>\nDate: Wed, 1 Mar 2017 16:07:39 +0000\nSubject: [PATCH] amba_pl011: Round input clock up\n\nThe UART clock is initialised to be as close to the requested\nfrequency as possible without exceeding it. Now that there is a\nclock manager that returns the actual frequencies, an expected\n48MHz clock is reported as 47999625. If the requested baudrate\n== requested clock/16, there is no headroom and the slight\nreduction in actual clock rate results in failure.\n\nDetect cases where it looks like a \"round\" clock was chosen and\nadjust the reported clock to match that \"round\" value. As the\ncode comment says:\n\n/*\n * If increasing a clock by less than 0.1% changes it\n * from ..999.. to ..000.., round up.\n */\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.org>\n---\n drivers/tty/serial/amba-pl011.c | 23 +++++++++++++++++++++--\n 1 file changed, 21 insertions(+), 2 deletions(-)\n\n--- a/drivers/tty/serial/amba-pl011.c\n+++ b/drivers/tty/serial/amba-pl011.c\n@@ -1642,6 +1642,23 @@ static void pl011_put_poll_char(struct u\n \n #endif /* CONFIG_CONSOLE_POLL */\n \n+unsigned long pl011_clk_round(unsigned long clk)\n+{\n+\tunsigned long scaler;\n+\n+\t/*\n+\t * If increasing a clock by less than 0.1% changes it\n+\t * from ..999.. to ..000.., round up.\n+\t */\n+\tscaler = 1;\n+\twhile (scaler * 100000 < clk)\n+\t\tscaler *= 10;\n+\tif ((clk + scaler - 1)/scaler % 1000 == 0)\n+\t\tclk = (clk/scaler + 1) * scaler;\n+\n+\treturn clk;\n+}\n+\n static int pl011_hwinit(struct uart_port *port)\n {\n \tstruct uart_amba_port *uap =\n@@ -1658,7 +1675,7 @@ static int pl011_hwinit(struct uart_port\n \tif (retval)\n \t\treturn retval;\n \n-\tuap->port.uartclk = clk_get_rate(uap->clk);\n+\tuap->port.uartclk = pl011_clk_round(clk_get_rate(uap->clk));\n \n \t/* Clear pending error and receive interrupts */\n \tpl011_write(UART011_OEIS | UART011_BEIS | UART011_PEIS |\n@@ -2292,7 +2309,7 @@ static int pl011_console_setup(struct co\n \t\t\tplat->init();\n \t}\n \n-\tuap->port.uartclk = clk_get_rate(uap->clk);\n+\tuap->port.uartclk = pl011_clk_round(clk_get_rate(uap->clk));\n \n \tif (uap->vendor->fixed_options) {\n \t\tbaud = uap->fixed_baud;\n@@ -2509,6 +2526,7 @@ static struct uart_driver amba_reg = {\n \t.cons\t\t\t= AMBA_CONSOLE,\n };\n \n+#if 0\n static int pl011_probe_dt_alias(int index, struct device *dev)\n {\n \tstruct device_node *np;\n@@ -2540,6 +2558,7 @@ static int pl011_probe_dt_alias(int inde\n \n \treturn ret;\n }\n+#endif\n \n /* unregisters the driver also if no more ports are left */\n static void pl011_unregister_port(struct uart_amba_port *uap)\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0033-amba_pl011-Insert-mb-for-correct-FIFO-handling.patch",
    "content": "From f44d321993ccf1707f5774dc443b900adae5d9d5 Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.org>\nDate: Fri, 29 Sep 2017 10:32:19 +0100\nSubject: [PATCH] amba_pl011: Insert mb() for correct FIFO handling\n\nThe pl011 register accessor functions use the _relaxed versions of the\nstandard readl() and writel() functions, meaning that there are no\nautomatic memory barriers. When polling a FIFO status register to check\nfor fullness, it is necessary to ensure that any outstanding writes have\ncompleted; otherwise the flags are effectively stale, making it possible\nthat the next write is to a full FIFO.\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.org>\n---\n drivers/tty/serial/amba-pl011.c | 1 +\n 1 file changed, 1 insertion(+)\n\n--- a/drivers/tty/serial/amba-pl011.c\n+++ b/drivers/tty/serial/amba-pl011.c\n@@ -1377,6 +1377,7 @@ static bool pl011_tx_char(struct uart_am\n \t\treturn false; /* unable to transmit character */\n \n \tpl011_write(c, uap, REG_DR);\n+\tmb();\n \tuap->port.icount.tx++;\n \n \treturn true;\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0034-amba_pl011-Add-cts-event-workaround-DT-property.patch",
    "content": "From 8ccf96729972504acf4ca0e1868278ba549e0f5a Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.org>\nDate: Fri, 29 Sep 2017 10:32:19 +0100\nSubject: [PATCH] amba_pl011: Add cts-event-workaround DT property\n\nThe BCM2835 PL011 implementation seems to have a bug that can lead to a\ntransmission lockup if CTS changes frequently. A workaround was added to\nthe driver with a vendor-specific flag to enable it, but this flag is\ncurrently not set for ARM implementations.\n\nAdd a \"cts-event-workaround\" property to Pi DTBs and use the presence\nof that property to force the flag to be enabled in the driver.\n\nSee: https://github.com/raspberrypi/linux/issues/1280\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.org>\n---\n Documentation/devicetree/bindings/serial/pl011.yaml | 6 ++++++\n drivers/tty/serial/amba-pl011.c                     | 5 +++++\n 2 files changed, 11 insertions(+)\n\n--- a/Documentation/devicetree/bindings/serial/pl011.yaml\n+++ b/Documentation/devicetree/bindings/serial/pl011.yaml\n@@ -98,6 +98,12 @@ properties:\n     $ref: /schemas/types.yaml#/definitions/uint32\n     default: 3000\n \n+  cts-event-workaround:\n+    description:\n+      Enables the (otherwise vendor-specific) workaround for the\n+      CTS-induced TX lockup.\n+    type: boolean\n+\n required:\n   - compatible\n   - reg\n--- a/drivers/tty/serial/amba-pl011.c\n+++ b/drivers/tty/serial/amba-pl011.c\n@@ -2665,6 +2665,11 @@ static int pl011_probe(struct amba_devic\n \tif (IS_ERR(uap->clk))\n \t\treturn PTR_ERR(uap->clk);\n \n+\tif (of_property_read_bool(dev->dev.of_node, \"cts-event-workaround\")) {\n+\t    vendor->cts_event_workaround = true;\n+\t    dev_info(&dev->dev, \"cts_event_workaround enabled\\n\");\n+\t}\n+\n \tuap->reg_offset = vendor->reg_offset;\n \tuap->vendor = vendor;\n \tuap->fifosize = vendor->get_fifosize(dev);\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0035-tty-amba-pl011-Make-TX-optimisation-conditional.patch",
    "content": "From 28c2408f991d97de5e3d1da9711cf5486f411d02 Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.org>\nDate: Thu, 11 Jul 2019 13:13:39 +0100\nSubject: [PATCH] tty: amba-pl011: Make TX optimisation conditional\n\npl011_tx_chars takes a \"from_irq\" parameter to reduce the number of\nregister accesses. When from_irq is true the function assumes that the\nFIFO is half empty and writes up to half a FIFO's worth of bytes\nwithout polling the FIFO status register, the reasoning being that\nthe function is being called as a result of the TX interrupt being\nraised. This logic would work were it not for the fact that\npl011_rx_chars, called from pl011_int before pl011_tx_chars, releases\nthe spinlock before calling tty_flip_buffer_push.\n\nA user thread writing to the UART claims the spinlock and ultimately\ncalls pl011_tx_chars with from_irq set to false. This reverts to the\nolder logic that polls the FIFO status register before sending every\nbyte. If this happen on an SMP system during the section of the IRQ\nhandler where the spinlock has been released, then by the time the TX\ninterrupt handler is called, the FIFO may already be full, and any\nfurther writes are likely to be lost.\n\nThe fix involves adding a per-port flag that is true iff running from\nwithin the interrupt handler and the spinlock has not yet been released.\nThis flag is then used as the value for the from_irq parameter of\npl011_tx_chars, causing polling to be used in the unsafe case.\n\nFixes: 1e84d22322ce (\"serial/amba-pl011: Refactor and simplify TX FIFO handling\")\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.org>\n---\n drivers/tty/serial/amba-pl011.c | 7 ++++++-\n 1 file changed, 6 insertions(+), 1 deletion(-)\n\n--- a/drivers/tty/serial/amba-pl011.c\n+++ b/drivers/tty/serial/amba-pl011.c\n@@ -265,6 +265,7 @@ struct uart_amba_port {\n \tunsigned int\t\told_cr;\t\t/* state during shutdown */\n \tunsigned int\t\tfixed_baud;\t/* vendor-set fixed baud rate */\n \tchar\t\t\ttype[12];\n+\tbool\t\t\tirq_locked;\t/* in irq, unreleased lock */\n #ifdef CONFIG_DMA_ENGINE\n \t/* DMA stuff */\n \tbool\t\t\tusing_tx_dma;\n@@ -811,6 +812,7 @@ __acquires(&uap->port.lock)\n \tif (!uap->using_tx_dma)\n \t\treturn;\n \n+\tuap->irq_locked = 0;\n \tdmaengine_terminate_async(uap->dmatx.chan);\n \n \tif (uap->dmatx.queued) {\n@@ -937,6 +939,7 @@ static void pl011_dma_rx_chars(struct ua\n \t\tfifotaken = pl011_fifo_to_tty(uap);\n \t}\n \n+\tuap->irq_locked = 0;\n \tspin_unlock(&uap->port.lock);\n \tdev_vdbg(uap->port.dev,\n \t\t \"Took %d chars from DMA buffer and %d chars from the FIFO\\n\",\n@@ -1341,6 +1344,7 @@ __acquires(&uap->port.lock)\n {\n \tpl011_fifo_to_tty(uap);\n \n+\tuap->irq_locked = 0;\n \tspin_unlock(&uap->port.lock);\n \ttty_flip_buffer_push(&uap->port.state->port);\n \t/*\n@@ -1474,6 +1478,7 @@ static irqreturn_t pl011_int(int irq, vo\n \tint handled = 0;\n \n \tspin_lock_irqsave(&uap->port.lock, flags);\n+\tuap->irq_locked = 1;\n \tstatus = pl011_read(uap, REG_RIS) & uap->im;\n \tif (status) {\n \t\tdo {\n@@ -1493,7 +1498,7 @@ static irqreturn_t pl011_int(int irq, vo\n \t\t\t\t      UART011_CTSMIS|UART011_RIMIS))\n \t\t\t\tpl011_modem_status(uap);\n \t\t\tif (status & UART011_TXIS)\n-\t\t\t\tpl011_tx_chars(uap, true);\n+\t\t\t\tpl011_tx_chars(uap, uap->irq_locked);\n \n \t\t\tif (pass_counter-- == 0)\n \t\t\t\tbreak;\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0036-tty-amba-pl011-Add-un-throttle-support.patch",
    "content": "From 3cec61f1b19a6f589f8b2aef97977e1c38eb7b70 Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.org>\nDate: Fri, 24 Jan 2020 11:38:28 +0000\nSubject: [PATCH] tty: amba-pl011: Add un/throttle support\n\nThe PL011 driver lacks throttle and unthrottle methods. As a result,\nsending more data to the Pi than it can immediately sink while CRTSCTS\nis enabled causes a NULL pointer to be followed.\n\nAdd a throttle handler that disables the RX interrupts, and an\nunthrottle handler that reenables them.\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.org>\n---\n drivers/tty/serial/amba-pl011.c | 28 ++++++++++++++++++++++++++++\n 1 file changed, 28 insertions(+)\n\n--- a/drivers/tty/serial/amba-pl011.c\n+++ b/drivers/tty/serial/amba-pl011.c\n@@ -1317,6 +1317,32 @@ static void pl011_start_tx(struct uart_p\n \t\tpl011_start_tx_pio(uap);\n }\n \n+static void pl011_throttle(struct uart_port *port)\n+{\n+\tstruct uart_amba_port *uap =\n+\t    container_of(port, struct uart_amba_port, port);\n+\tunsigned long flags;\n+\n+\tspin_lock_irqsave(&uap->port.lock, flags);\n+\tuap->im &= ~(UART011_RTIM | UART011_RXIM);\n+\tpl011_write(uap->im, uap, REG_IMSC);\n+\tspin_unlock_irqrestore(&uap->port.lock, flags);\n+}\n+\n+static void pl011_unthrottle(struct uart_port *port)\n+{\n+\tstruct uart_amba_port *uap =\n+\t    container_of(port, struct uart_amba_port, port);\n+\tunsigned long flags;\n+\n+\tspin_lock_irqsave(&uap->port.lock, flags);\n+\tuap->im |= UART011_RTIM;\n+\tif (!pl011_dma_rx_running(uap))\n+\t    uap->im |= UART011_RXIM;\n+\tpl011_write(uap->im, uap, REG_IMSC);\n+\tspin_unlock_irqrestore(&uap->port.lock, flags);\n+}\n+\n static void pl011_stop_rx(struct uart_port *port)\n {\n \tstruct uart_amba_port *uap =\n@@ -2139,6 +2165,8 @@ static const struct uart_ops amba_pl011_\n \t.stop_tx\t= pl011_stop_tx,\n \t.start_tx\t= pl011_start_tx,\n \t.stop_rx\t= pl011_stop_rx,\n+\t.throttle\t= pl011_throttle,\n+\t.unthrottle\t= pl011_unthrottle,\n \t.enable_ms\t= pl011_enable_ms,\n \t.break_ctl\t= pl011_break_ctl,\n \t.startup\t= pl011_startup,\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0037-tty-amba-pl011-Avoid-rare-write-when-full-error.patch",
    "content": "From e9addfee683ceabeae5da9dc5503fef536f7385a Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.org>\nDate: Wed, 29 Jan 2020 09:35:19 +0000\nSubject: [PATCH] tty: amba-pl011: Avoid rare write-when-full error\n\nUnder some circumstances on BCM283x processors data loss can be\nobserved - a single byte missing from the TX output stream. These bytes\nare always the last byte of a batch of 8 written from pl011_tx_chars\nwhen from_irq is true, meaning that the FIFO full flag is not checked\nbefore writing.\n\nThe transmit optimisation relies on the FIFO being half-empty when the\nTX interrupt is raised. Instrumenting the driver further showed that\nthe failure case correlated with the TX FIFO full flag being set at the\npoint where the last byte was written to the data register, which\nexplains the data loss but not how the FIFO appeared to be prematurely\nfull. A possible explanation is that a FIFO write was in flight at the\ntime the interrupt was raised, but as yet there is no hypothesis as to\nhow this might occur.\n\nIn the absence of a clear understanding of the failure mechanism, avoid\nthe problem by checking the FIFO levels before writing the last byte of\nthe group, which will have minimal performance impact.\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.org>\n---\n drivers/tty/serial/amba-pl011.c | 4 ++++\n 1 file changed, 4 insertions(+)\n\n--- a/drivers/tty/serial/amba-pl011.c\n+++ b/drivers/tty/serial/amba-pl011.c\n@@ -1438,6 +1438,10 @@ static bool pl011_tx_chars(struct uart_a\n \t\tif (likely(from_irq) && count-- == 0)\n \t\t\tbreak;\n \n+\t\tif (likely(from_irq) && count == 0 &&\n+\t\t    pl011_read(uap, REG_FR) & UART01x_FR_TXFF)\n+\t\t\tbreak;\n+\n \t\tif (!pl011_tx_char(uap, xmit->buf[xmit->tail], from_irq))\n \t\t\tbreak;\n \n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0038-pinctrl-bcm2835-Set-base-to-0-give-expected-gpio-num.patch",
    "content": "From 68ef623a719071e05f5d62270c7bee35a2984452 Mon Sep 17 00:00:00 2001\nFrom: notro <notro@tronnes.org>\nDate: Thu, 10 Jul 2014 13:59:47 +0200\nSubject: [PATCH] pinctrl-bcm2835: Set base to 0 give expected gpio\n numbering\n\nSigned-off-by: Noralf Tronnes <notro@tronnes.org>\n---\n drivers/pinctrl/bcm/pinctrl-bcm2835.c | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/drivers/pinctrl/bcm/pinctrl-bcm2835.c\n+++ b/drivers/pinctrl/bcm/pinctrl-bcm2835.c\n@@ -362,7 +362,7 @@ static const struct gpio_chip bcm2835_gp\n \t.get = bcm2835_gpio_get,\n \t.set = bcm2835_gpio_set,\n \t.set_config = gpiochip_generic_config,\n-\t.base = -1,\n+\t.base = 0,\n \t.ngpio = BCM2835_NUM_GPIOS,\n \t.can_sleep = false,\n };\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0039-Main-bcm2708-bcm2709-linux-port.patch",
    "content": "From 0ef60858b9927024cd310038c97976e27e4daada Mon Sep 17 00:00:00 2001\nFrom: popcornmix <popcornmix@gmail.com>\nDate: Sun, 12 May 2013 12:24:19 +0100\nSubject: [PATCH] Main bcm2708/bcm2709 linux port\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nSigned-off-by: popcornmix <popcornmix@gmail.com>\nSigned-off-by: Noralf Trønnes <noralf@tronnes.org>\n\nbcm2709: Drop platform smp and timer init code\n\nirq-bcm2836 handles this through these functions:\nbcm2835_init_local_timer_frequency()\nbcm2836_arm_irqchip_smp_init()\n\nSigned-off-by: Noralf Trønnes <noralf@tronnes.org>\n\nbcm270x: Use watchdog for reboot/poweroff\n\nThe watchdog driver already has support for reboot/poweroff.\nMake use of this and remove the code from the platform files.\n\nSigned-off-by: Noralf Trønnes <noralf@tronnes.org>\n\nboard_bcm2835: Remove coherent dma pool increase - API has gone\n---\n arch/arm/mach-bcm/Kconfig         |  1 +\n arch/arm/mm/proc-v6.S             | 15 ++++++++++++---\n drivers/irqchip/irq-bcm2835.c     |  7 ++++++-\n drivers/mailbox/bcm2835-mailbox.c | 18 ++++++++++++++++--\n 4 files changed, 35 insertions(+), 6 deletions(-)\n\n--- a/arch/arm/mach-bcm/Kconfig\n+++ b/arch/arm/mach-bcm/Kconfig\n@@ -165,6 +165,7 @@ config ARCH_BCM2835\n \tselect PINCTRL\n \tselect PINCTRL_BCM2835\n \tselect MFD_CORE\n+\tselect MFD_SYSCON if ARCH_MULTI_V7\n \thelp\n \t  This enables support for the Broadcom BCM2711 and BCM283x SoCs.\n \t  This SoC is used in the Raspberry Pi and Roku 2 devices.\n--- a/arch/arm/mm/proc-v6.S\n+++ b/arch/arm/mm/proc-v6.S\n@@ -70,10 +70,19 @@ ENDPROC(cpu_v6_reset)\n  *\n  *\tIRQs are already disabled.\n  */\n+\n+/* See jira SW-5991 for details of this workaround */\n ENTRY(cpu_v6_do_idle)\n-\tmov\tr1, #0\n-\tmcr\tp15, 0, r1, c7, c10, 4\t\t@ DWB - WFI may enter a low-power mode\n-\tmcr\tp15, 0, r1, c7, c0, 4\t\t@ wait for interrupt\n+\t.align 5\n+\tmov     r1, #2\n+1:\tsubs\tr1, #1\n+\tnop\n+\tmcreq\tp15, 0, r1, c7, c10, 4\t\t@ DWB - WFI may enter a low-power mode\n+\tmcreq\tp15, 0, r1, c7, c0, 4\t\t@ wait for interrupt\n+\tnop\n+\tnop\n+\tnop\n+\tbne 1b\n \tret\tlr\n \n ENTRY(cpu_v6_dcache_clean_area)\n--- a/drivers/irqchip/irq-bcm2835.c\n+++ b/drivers/irqchip/irq-bcm2835.c\n@@ -43,7 +43,9 @@\n #include <linux/irqdomain.h>\n \n #include <asm/exception.h>\n+#ifndef CONFIG_ARM64\n #include <asm/mach/irq.h>\n+#endif\n \n /* Put the bank and irq (32 bits) into the hwirq */\n #define MAKE_HWIRQ(b, n)\t(((b) << 5) | (n))\n@@ -72,6 +74,7 @@\n #define NR_BANKS\t\t3\n #define IRQS_PER_BANK\t\t32\n #define NUMBER_IRQS\t\tMAKE_HWIRQ(NR_BANKS, 0)\n+#undef FIQ_START\n #define FIQ_START\t\t(NR_IRQS_BANK0 + MAKE_HWIRQ(NR_BANKS - 1, 0))\n \n static const int reg_pending[] __initconst = { 0x00, 0x04, 0x08 };\n@@ -253,10 +256,12 @@ static int __init armctrl_of_init(struct\n \t\t\t\t\tMAKE_HWIRQ(b, i) + NUMBER_IRQS);\n \t\t\tBUG_ON(irq <= 0);\n \t\t\tirq_set_chip(irq, &armctrl_chip);\n-\t\t\tset_irq_flags(irq, IRQF_VALID | IRQF_PROBE);\n+\t\t\tirq_set_probe(irq);\n \t\t}\n \t}\n+#ifndef CONFIG_ARM64\n \tinit_FIQ(FIQ_START);\n+#endif\n \n \treturn 0;\n }\n--- a/drivers/mailbox/bcm2835-mailbox.c\n+++ b/drivers/mailbox/bcm2835-mailbox.c\n@@ -45,12 +45,15 @@\n #define MAIL1_WRT\t(ARM_0_MAIL1 + 0x00)\n #define MAIL1_STA\t(ARM_0_MAIL1 + 0x18)\n \n+/* On ARCH_BCM270x these come through <linux/interrupt.h> (arm_control.h ) */\n+#ifndef ARM_MS_FULL\n /* Status register: FIFO state. */\n #define ARM_MS_FULL\t\tBIT(31)\n #define ARM_MS_EMPTY\t\tBIT(30)\n \n /* Configuration register: Enable interrupts. */\n #define ARM_MC_IHAVEDATAIRQEN\tBIT(0)\n+#endif\n \n struct bcm2835_mbox {\n \tvoid __iomem *regs;\n@@ -145,7 +148,7 @@ static int bcm2835_mbox_probe(struct pla\n \t\treturn -ENOMEM;\n \tspin_lock_init(&mbox->lock);\n \n-\tret = devm_request_irq(dev, irq_of_parse_and_map(dev->of_node, 0),\n+\tret = devm_request_irq(dev, platform_get_irq(pdev, 0),\n \t\t\t       bcm2835_mbox_irq, 0, dev_name(dev), mbox);\n \tif (ret) {\n \t\tdev_err(dev, \"Failed to register a mailbox IRQ handler: %d\\n\",\n@@ -195,7 +198,18 @@ static struct platform_driver bcm2835_mb\n \t},\n \t.probe\t\t= bcm2835_mbox_probe,\n };\n-module_platform_driver(bcm2835_mbox_driver);\n+\n+static int __init bcm2835_mbox_init(void)\n+{\n+\treturn platform_driver_register(&bcm2835_mbox_driver);\n+}\n+arch_initcall(bcm2835_mbox_init);\n+\n+static void __init bcm2835_mbox_exit(void)\n+{\n+\tplatform_driver_unregister(&bcm2835_mbox_driver);\n+}\n+module_exit(bcm2835_mbox_exit);\n \n MODULE_AUTHOR(\"Lubomir Rintel <lkundrak@v3.sk>\");\n MODULE_DESCRIPTION(\"BCM2835 mailbox IPC driver\");\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0040-Add-dwc_otg-driver.patch",
    "content": "From 8c7c80cd6068b80a4bde7276ff79964de48d4ed0 Mon Sep 17 00:00:00 2001\nFrom: popcornmix <popcornmix@gmail.com>\nDate: Wed, 1 May 2013 19:46:17 +0100\nSubject: [PATCH] Add dwc_otg driver\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nSigned-off-by: popcornmix <popcornmix@gmail.com>\n\nusb: dwc: fix lockdep false positive\n\nSigned-off-by: Kari Suvanto <karis79@gmail.com>\n\nusb: dwc: fix inconsistent lock state\n\nSigned-off-by: Kari Suvanto <karis79@gmail.com>\n\nAdd FIQ patch to dwc_otg driver. Enable with dwc_otg.fiq_fix_enable=1. Should give about 10% more ARM performance.\nThanks to Gordon and Costas\n\nAvoid dynamic memory allocation for channel lock in USB driver. Thanks ddv2005.\n\nAdd NAK holdoff scheme. Enabled by default, disable with dwc_otg.nak_holdoff_enable=0. Thanks gsh\n\nMake sure we wait for the reset to finish\n\ndwc_otg: fix bug in dwc_otg_hcd.c resulting in silent kernel\n\t memory corruption, escalating to OOPS under high USB load.\n\ndwc_otg: Fix unsafe access of QTD during URB enqueue\n\nIn dwc_otg_hcd_urb_enqueue during qtd creation, it was possible that the\ntransaction could complete almost immediately after the qtd was assigned\nto a host channel during URB enqueue, which meant the qtd pointer was no\nlonger valid having been completed and removed. Usually, this resulted in\nan OOPS during URB submission. By predetermining whether transactions\nneed to be queued or not, this unsafe pointer access is avoided.\n\nThis bug was only evident on the Pi model A where a device was attached\nthat had no periodic endpoints (e.g. USB pendrive or some wlan devices).\n\ndwc_otg: Fix incorrect URB allocation error handling\n\nIf the memory allocation for a dwc_otg_urb failed, the kernel would OOPS\nbecause for some reason a member of the *unallocated* struct was set to\nzero. Error handling changed to fail correctly.\n\ndwc_otg: fix potential use-after-free case in interrupt handler\n\nIf a transaction had previously aborted, certain interrupts are\nenabled to track error counts and reset where necessary. On IN\nendpoints the host generates an ACK interrupt near-simultaneously\nwith completion of transfer. In the case where this transfer had\npreviously had an error, this results in a use-after-free on\nthe QTD memory space with a 1-byte length being overwritten to\n0x00.\n\ndwc_otg: add handling of SPLIT transaction data toggle errors\n\nPreviously a data toggle error on packets from a USB1.1 device behind\na TT would result in the Pi locking up as the driver never handled\nthe associated interrupt. Patch adds basic retry mechanism and\ninterrupt acknowledgement to cater for either a chance toggle error or\nfor devices that have a broken initial toggle state (FT8U232/FT232BM).\n\ndwc_otg: implement tasklet for returning URBs to usbcore hcd layer\n\nThe dwc_otg driver interrupt handler for transfer completion will spend\na very long time with interrupts disabled when a URB is completed -\nthis is because usb_hcd_giveback_urb is called from within the handler\nwhich for a USB device driver with complicated processing (e.g. webcam)\nwill take an exorbitant amount of time to complete. This results in\nmissed completion interrupts for other USB packets which lead to them\nbeing dropped due to microframe overruns.\n\nThis patch splits returning the URB to the usb hcd layer into a\nhigh-priority tasklet. This will have most benefit for isochronous IN\ntransfers but will also have incidental benefit where multiple periodic\ndevices are active at once.\n\ndwc_otg: fix NAK holdoff and allow on split transactions only\n\nThis corrects a bug where if a single active non-periodic endpoint\nhad at least one transaction in its qh, on frnum == MAX_FRNUM the qh\nwould get skipped and never get queued again. This would result in\na silent device until error detection (automatic or otherwise) would\neither reset the device or flush and requeue the URBs.\n\nAdditionally the NAK holdoff was enabled for all transactions - this\nwould potentially stall a HS endpoint for 1ms if a previous error state\nenabled this interrupt and the next response was a NAK. Fix so that\nonly split transactions get held off.\n\ndwc_otg: Call usb_hcd_unlink_urb_from_ep with lock held in completion handler\n\nusb_hcd_unlink_urb_from_ep must be called with the HCD lock held.  Calling it\nasynchronously in the tasklet was not safe (regression in\nc4564d4a1a0a9b10d4419e48239f5d99e88d2667).\n\nThis change unlinks it from the endpoint prior to queueing it for handling in\nthe tasklet, and also adds a check to ensure the urb is OK to be unlinked\nbefore doing so.\n\nNULL pointer dereference kernel oopses had been observed in usb_hcd_giveback_urb\nwhen a USB device was unplugged/replugged during data transfer.  This effect\nwas reproduced using automated USB port power control, hundreds of replug\nevents were performed during active transfers to confirm that the problem was\neliminated.\n\nUSB fix using a FIQ to implement split transactions\n\nThis commit adds a FIQ implementaion that schedules\nthe split transactions using a FIQ so we don't get\nheld off by the interrupt latency of Linux\n\ndwc_otg: fix device attributes and avoid kernel warnings on boot\n\ndcw_otg: avoid logging function that can cause panics\n\nSee: https://github.com/raspberrypi/firmware/issues/21\nThanks to cleverca22 for fix\n\ndwc_otg: mask correct interrupts after transaction error recovery\n\nThe dwc_otg driver will unmask certain interrupts on a transaction\nthat previously halted in the error state in order to reset the\nQTD error count. The various fine-grained interrupt handlers do not\nconsider that other interrupts besides themselves were unmasked.\n\nBy disabling the two other interrupts only ever enabled in DMA mode\nfor this purpose, we can avoid unnecessary function calls in the\nIRQ handler. This will also prevent an unneccesary FIQ interrupt\nfrom being generated if the FIQ is enabled.\n\ndwc_otg: fiq: prevent FIQ thrash and incorrect state passing to IRQ\n\nIn the case of a transaction to a device that had previously aborted\ndue to an error, several interrupts are enabled to reset the error\ncount when a device responds. This has the side-effect of making the\nFIQ thrash because the hardware will generate multiple instances of\na NAK on an IN bulk/interrupt endpoint and multiple instances of ACK\non an OUT bulk/interrupt endpoint. Make the FIQ mask and clear the\nassociated interrupts.\n\nAdditionally, on non-split transactions make sure that only unmasked\ninterrupts are cleared. This caused a hard-to-trigger but serious\nrace condition when you had the combination of an endpoint awaiting\nerror recovery and a transaction completed on an endpoint - due to\nthe sequencing and timing of interrupts generated by the dwc_otg core,\nit was possible to confuse the IRQ handler.\n\nFix function tracing\n\ndwc_otg: whitespace cleanup in dwc_otg_urb_enqueue\n\ndwc_otg: prevent OOPSes during device disconnects\n\nThe dwc_otg_urb_enqueue function is thread-unsafe. In particular the\naccess of urb->hcpriv, usb_hcd_link_urb_to_ep, dwc_otg_urb->qtd and\nfriends does not occur within a critical section and so if a device\nwas unplugged during activity there was a high chance that the\nusbcore hub_thread would try to disable the endpoint with partially-\nformed entries in the URB queue. This would result in BUG() or null\npointer dereferences.\n\nFix so that access of urb->hcpriv, enqueuing to the hardware and\nadding to usbcore endpoint URB lists is contained within a single\ncritical section.\n\ndwc_otg: prevent BUG() in TT allocation if hub address is > 16\n\nA fixed-size array is used to track TT allocation. This was\npreviously set to 16 which caused a crash because\ndwc_otg_hcd_allocate_port would read past the end of the array.\n\nThis was hit if a hub was plugged in which enumerated as addr > 16,\ndue to previous device resets or unplugs.\n\nAlso add #ifdef FIQ_DEBUG around hcd->hub_port_alloc[], which grows\nto a large size if 128 hub addresses are supported. This field is\nfor debug only for tracking which frame an allocate happened in.\n\ndwc_otg: make channel halts with unknown state less damaging\n\nIf the IRQ received a channel halt interrupt through the FIQ\nwith no other bits set, the IRQ would not release the host\nchannel and never complete the URB.\n\nAdd catchall handling to treat as a transaction error and retry.\n\ndwc_otg: fiq_split: use TTs with more granularity\n\nThis fixes certain issues with split transaction scheduling.\n\n- Isochronous multi-packet OUT transactions now hog the TT until\n  they are completed - this prevents hubs aborting transactions\n  if they get a periodic start-split out-of-order\n- Don't perform TT allocation on non-periodic endpoints - this\n  allows simultaneous use of the TT's bulk/control and periodic\n  transaction buffers\n\nThis commit will mainly affect USB audio playback.\n\ndwc_otg: fix potential sleep while atomic during urb enqueue\n\nFixes a regression introduced with eb1b482a. Kmalloc called from\ndwc_otg_hcd_qtd_add / dwc_otg_hcd_qtd_create did not always have\nthe GPF_ATOMIC flag set. Force this flag when inside the larger\ncritical section.\n\ndwc_otg: make fiq_split_enable imply fiq_fix_enable\n\nFailing to set up the FIQ correctly would result in\n\"IRQ 32: nobody cared\" errors in dmesg.\n\ndwc_otg: prevent crashes on host port disconnects\n\nFix several issues resulting in crashes or inconsistent state\nif a Model A root port was disconnected.\n\n- Clean up queue heads properly in kill_urbs_in_qh_list by\n  removing the empty QHs from the schedule lists\n- Set the halt status properly to prevent IRQ handlers from\n  using freed memory\n- Add fiq_split related cleanup for saved registers\n- Make microframe scheduling reclaim host channels if\n  active during a disconnect\n- Abort URBs with -ESHUTDOWN status response, informing\n  device drivers so they respond in a more correct fashion\n  and don't try to resubmit URBs\n- Prevent IRQ handlers from attempting to handle channel\n  interrupts if the associated URB was dequeued (and the\n  driver state was cleared)\n\ndwc_otg: prevent leaking URBs during enqueue\n\nA dwc_otg_urb would get leaked if the HCD enqueue function\nfailed for any reason. Free the URB at the appropriate points.\n\ndwc_otg: Enable NAK holdoff for control split transactions\n\nCertain low-speed devices take a very long time to complete a\ndata or status stage of a control transaction, producing NAK\nresponses until they complete internal processing - the USB2.0\nspec limit is up to 500mS. This causes the same type of interrupt\nstorm as seen with USB-serial dongles prior to c8edb238.\n\nIn certain circumstances, usually while booting, this interrupt\nstorm could cause SD card timeouts.\n\ndwc_otg: Fix for occasional lockup on boot when doing a USB reset\n\ndwc_otg: Don't issue traffic to LS devices in FS mode\n\nIssuing low-speed packets when the root port is in full-speed mode\ncauses the root port to stop responding. Explicitly fail when\nenqueuing URBs to a LS endpoint on a FS bus.\n\nFix ARM architecture issue with local_irq_restore()\n\nIf local_fiq_enable() is called before a local_irq_restore(flags) where\nthe flags variable has the F bit set, the FIQ will be erroneously disabled.\n\nFixup arch_local_irq_restore to avoid trampling the F bit in CPSR.\n\nAlso fix some of the hacks previously implemented for previous dwc_otg\nincarnations.\n\ndwc_otg: fiq_fsm: Base commit for driver rewrite\n\nThis commit removes the previous FIQ fixes entirely and adds fiq_fsm.\n\nThis rewrite features much more complete support for split transactions\nand takes into account several OTG hardware bugs. High-speed\nisochronous transactions are also capable of being performed by fiq_fsm.\n\nAll driver options have been removed and replaced with:\n  - dwc_otg.fiq_enable (bool)\n  - dwc_otg.fiq_fsm_enable (bool)\n  - dwc_otg.fiq_fsm_mask (bitmask)\n  - dwc_otg.nak_holdoff (unsigned int)\n\nDefaults are specified such that fiq_fsm behaves similarly to the\npreviously implemented FIQ fixes.\n\nfiq_fsm: Push error recovery into the FIQ when fiq_fsm is used\n\nIf the transfer associated with a QTD failed due to a bus error, the HCD\nwould retry the transfer up to 3 times (implementing the USB2.0\nthree-strikes retry in software).\n\nDue to the masking mechanism used by fiq_fsm, it is only possible to pass\na single interrupt through to the HCD per-transfer.\n\nIn this instance host channels would fall off the radar because the error\nreset would function, but the subsequent channel halt would be lost.\n\nPush the error count reset into the FIQ handler.\n\nfiq_fsm: Implement timeout mechanism\n\nFor full-speed endpoints with a large packet size, interrupt latency\nruns the risk of the FIQ starting a transaction too late in a full-speed\nframe. If the device is still transmitting data when EOF2 for the\ndownstream frame occurs, the hub will disable the port. This change is\nnot reflected in the hub status endpoint and the device becomes\nunresponsive.\n\nPrevent high-bandwidth transactions from being started too late in a\nframe. The mechanism is not guaranteed: a combination of bit stuffing\nand hub latency may still result in a device overrunning.\n\nfiq_fsm: fix bounce buffer utilisation for Isochronous OUT\n\nMulti-packet isochronous OUT transactions were subject to a few bounday\nbugs. Fix them.\n\nAudio playback is now much more robust: however, an issue stands with\ndevices that have adaptive sinks - ALSA plays samples too fast.\n\ndwc_otg: Return full-speed frame numbers in HS mode\n\nThe frame counter increments on every *microframe* in high-speed mode.\nMost device drivers expect this number to be in full-speed frames - this\ncaused considerable confusion to e.g. snd_usb_audio which uses the\nframe counter to estimate the number of samples played.\n\nfiq_fsm: save PID on completion of interrupt OUT transfers\n\nAlso add edge case handling for interrupt transports.\n\nNote that for periodic split IN, data toggles are unimplemented in the\nOTG host hardware - it unconditionally accepts any PID.\n\nfiq_fsm: add missing case for fiq_fsm_tt_in_use()\n\nCertain combinations of bitrate and endpoint activity could\nresult in a periodic transaction erroneously getting started\nwhile the previous Isochronous OUT was still active.\n\nfiq_fsm: clear hcintmsk for aborted transactions\n\nPrevents the FIQ from erroneously handling interrupts\non a timed out channel.\n\nfiq_fsm: enable by default\n\nfiq_fsm: fix dequeues for non-periodic split transactions\n\nIf a dequeue happened between the SSPLIT and CSPLIT phases of the\ntransaction, the HCD would never receive an interrupt.\n\nfiq_fsm: Disable by default\n\nfiq_fsm: Handle HC babble errors\n\nThe HCTSIZ transfer size field raises a babble interrupt if\nthe counter wraps. Handle the resulting interrupt in this case.\n\ndwc_otg: fix interrupt registration for fiq_enable=0\n\nAdditionally make the module parameter conditional for wherever\nhcd->fiq_state is touched.\n\nfiq_fsm: Enable by default\n\ndwc_otg: Fix various issues with root port and transaction errors\n\nProcess the host port interrupts correctly (and don't trample them).\nRoot port hotplug now functional again.\n\nFix a few thinkos with the transaction error passthrough for fiq_fsm.\n\nfiq_fsm: Implement hack for Split Interrupt transactions\n\nHubs aren't too picky about which endpoint we send Control type split\ntransactions to. By treating Interrupt transfers as Control, it is\npossible to use the non-periodic queue in the OTG core as well as the\nnon-periodic FIFOs in the hub itself. This massively reduces the\nmicroframe exclusivity/contention that periodic split transactions\notherwise have to enforce.\n\nIt goes without saying that this is a fairly egregious USB specification\nviolation, but it works.\n\nOriginal idea by Hans Petter Selasky @ FreeBSD.org.\n\ndwc_otg: FIQ support on SMP. Set up FIQ stack and handler on Core 0 only.\n\ndwc_otg: introduce fiq_fsm_spin(un|)lock()\n\nSMP safety for the FIQ relies on register read-modify write cycles being\ncompleted in the correct order. Several places in the DWC code modify\nregisters also touched by the FIQ. Protect these by a bare-bones lock\nmechanism.\n\nThis also makes it possible to run the FIQ and IRQ handlers on different\ncores.\n\nfiq_fsm: fix build on bcm2708 and bcm2709 platforms\n\ndwc_otg: put some barriers back where they should be for UP\n\nbcm2709/dwc_otg: Setup FIQ on core 1 if >1 core active\n\ndwc_otg: fixup read-modify-write in critical paths\n\nBe more careful about read-modify-write on registers that the FIQ\nalso touches.\n\nGuard fiq_fsm_spin_lock with fiq_enable check\n\nfiq_fsm: Falling out of the state machine isn't fatal\n\nThis edge case can be hit if the port is disabled while the FIQ is\nin the middle of a transaction. Make the effects less severe.\n\nAlso get rid of the useless return value.\n\nsquash: dwc_otg: Allow to build without SMP\n\nusb: core: make overcurrent messages more prominent\n\nHub overcurrent messages are more serious than \"debug\". Increase loglevel.\n\nusb: dwc_otg: Don't use dma_to_virt()\n\nCommit 6ce0d20 changes dma_to_virt() which breaks this driver.\nOpen code the old dma_to_virt() implementation to work around this.\n\nLimit the use of __bus_to_virt() to cases where transfer_buffer_length\nis set and transfer_buffer is not set. This is done to increase the\nchance that this driver will also work on ARCH_BCM2835.\n\ntransfer_buffer should not be NULL if the length is set, but the\ncomment in the code indicates that there are situations where this\nmight happen. drivers/usb/isp1760/isp1760-hcd.c also has a similar\ncomment pointing to a possible: 'usb storage / SCSI bug'.\n\nSigned-off-by: Noralf Trønnes <noralf@tronnes.org>\n\ndwc_otg: Fix crash when fiq_enable=0\n\ndwc_otg: fiq_fsm: Make high-speed isochronous strided transfers work properly\n\nCertain low-bandwidth high-speed USB devices (specialist audio devices,\ncompressed-frame webcams) have packet intervals > 1 microframe.\n\nStride these transfers in the FIQ by using the start-of-frame interrupt\nto restart the channel at the right time.\n\ndwc_otg: Force host mode to fix incorrect compute module boards\n\ndwc_otg: Add ARCH_BCM2835 support\n\nSigned-off-by: Noralf Trønnes <noralf@tronnes.org>\n\ndwc_otg: Simplify FIQ irq number code\n\nDropping ATAGS means we can simplify the FIQ irq number code.\nAlso add error checking on the returned irq number.\n\nSigned-off-by: Noralf Trønnes <noralf@tronnes.org>\n\ndwc_otg: Remove duplicate gadget probe/unregister function\n\ndwc_otg: Properly set the HFIR\n\nDouglas Anderson reported:\n\nAccording to the most up to date version of the dwc2 databook, the FRINT\nfield of the HFIR register should be programmed to:\n* 125 us * (PHY clock freq for HS) - 1\n* 1000 us * (PHY clock freq for FS/LS) - 1\n\nThis is opposed to older versions of the doc that claimed it should be:\n* 125 us * (PHY clock freq for HS)\n* 1000 us * (PHY clock freq for FS/LS)\n\nand reported lower timing jitter on a USB analyser\n\ndcw_otg: trim xfer length when buffer larger than allocated size is received\n\ndwc_otg: Don't free qh align buffers in atomic context\n\ndwc_otg: Enable the hack for Split Interrupt transactions by default\n\ndwc_otg.fiq_fsm_mask=0xF has long been a suggestion for users with audio stutters or other USB bandwidth issues.\nSo far we are aware of many success stories but no failure caused by this setting.\nMake it a default to learn more.\n\nSee: https://www.raspberrypi.org/forums/viewtopic.php?f=28&t=70437\n\nSigned-off-by: popcornmix <popcornmix@gmail.com>\n\ndwc_otg: Use kzalloc when suitable\n\ndwc_otg: Pass struct device to dma_alloc*()\n\nThis makes it possible to get the bus address from Device Tree.\n\nSigned-off-by: Noralf Trønnes <noralf@tronnes.org>\n\ndwc_otg: fix summarize urb->actual_length for isochronous transfers\n\nKernel does not copy input data of ISO transfers to userspace\nif actual_length is set only in ISO transfers and not summarized\nin urb->actual_length. Fixes raspberrypi/linux#903\n\nfiq_fsm: Use correct states when starting isoc OUT transfers\n\nIn fiq_fsm_start_next_periodic() if an isochronous OUT transfer\nwas selected, no regard was given as to whether this was a single-packet\ntransfer or a multi-packet staged transfer.\n\nFor single-packet transfers, this had the effect of repeatedly sending\nOUT packets with bogus data and lengths.\n\nEventually if the channel was repeatedly enabled enough times, this\nwould lock up the OTG core and no further bus transfers would happen.\n\nSet the FSM state up properly if we select a single-packet transfer.\n\nFixes https://github.com/raspberrypi/linux/issues/1842\n\ndwc_otg: make nak_holdoff work as intended with empty queues\n\nIf URBs reading from non-periodic split endpoints were dequeued and\nthe last transfer from the endpoint was a NAK handshake, the resulting\nqh->nak_frame value was stale which would result in unnecessarily long\npolling intervals for the first subsequent transfer with a fresh URB.\n\nFixup qh->nak_frame in dwc_otg_hcd_urb_dequeue and also guard against\na case where a single URB is submitted to the endpoint, a NAK was\nreceived on the transfer immediately prior to receiving data and the\ndevice subsequently resubmits another URB past the qh->nak_frame interval.\n\nFixes https://github.com/raspberrypi/linux/issues/1709\n\ndwc_otg: fix split transaction data toggle handling around dequeues\n\nSee https://github.com/raspberrypi/linux/issues/1709\n\nFix several issues regarding endpoint state when URBs are dequeued\n- If the HCD is disconnected, flush FIQ-enabled channels properly\n- Save the data toggle state for bulk endpoints if the last transfer\n  from an endpoint where URBs were dequeued returned a data packet\n- Reset hc->start_pkt_count properly in assign_and_init_hc()\n\ndwc_otg: fix several potential crash sources\n\nOn root port disconnect events, the host driver state is cleared and\nin-progress host channels are forcibly stopped. This doesn't play\nwell with the FIQ running in the background, so:\n- Guard the disconnect callback with both the host spinlock and FIQ\n  spinlock\n- Move qtd dereference in dwc_otg_handle_hc_fsm() after the early-out\n  so we don't dereference a qtd that has gone away\n- Turn catch-all BUG()s in dwc_otg_handle_hc_fsm() into warnings.\n\ndwc_otg: delete hcd->channel_lock\n\nThe lock serves no purpose as it is only held while the HCD spinlock\nis already being held.\n\ndwc_otg: remove unnecessary dma-mode channel halts on disconnect interrupt\n\nHost channels are already halted in kill_urbs_in_qh_list() with the\nsubsequent interrupt processing behaving as if the URB was dequeued\nvia HCD callback.\n\nThere's no need to clobber the host channel registers a second time\nas this exposes races between the driver and host channel resulting\nin hcd->free_hc_list becoming corrupted.\n\ndwcotg: Allow to build without FIQ on ARM64\n\nSigned-off-by: popcornmix <popcornmix@gmail.com>\n\ndwc_otg: make periodic scheduling behave properly for FS buses\n\nIf the root port is in full-speed mode, transfer times at 12mbit/s\nwould be calculated but matched against high-speed quotas.\n\nReinitialise hcd->frame_usecs[i] on each port enable event so that\nfull-speed bandwidth can be tracked sensibly.\n\nAlso, don't bother using the FIQ for transfers when in full-speed\nmode - at the slower bus speed, interrupt frequency is reduced by\nan order of magnitude.\n\nRelated issue: https://github.com/raspberrypi/linux/issues/2020\n\ndwc_otg: fiq_fsm: Make isochronous compatibility checks work properly\n\nGet rid of the spammy printk and local pointer mangling.\nAlso, there is a nominal benefit for using fiq_fsm for isochronous\ntransfers in FS mode (~1.1k IRQs per second vs 2.1k IRQs per second)\nso remove the root port speed check.\n\ndwc_otg: add module parameter int_ep_interval_min\n\nAdd a module parameter (defaulting to ignored) that clamps the polling rate\nof high-speed Interrupt endpoints to a minimum microframe interval.\n\nThe parameter is modifiable at runtime as it is used when activating new\nendpoints (such as on device connect).\n\ndwc_otg: fiq_fsm: Add non-periodic TT exclusivity constraints\n\nCertain hub types do not discriminate between pipe direction (IN or OUT)\nwhen considering non-periodic transfers. Therefore these hubs get confused\nif multiple transfers are issued in different directions with the same\ndevice address and endpoint number.\n\nConstrain queuing non-periodic split transactions so they are performed\nserially in such cases.\n\nRelated: https://github.com/raspberrypi/linux/issues/2024\n\ndwc_otg: Fixup change to DRIVER_ATTR interface\n\ndwc_otg: Fix compilation warnings\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.org>\n\nUSB_DWCOTG: Disable building dwc_otg as a module (#2265)\n\nWhen dwc_otg is built as a module, build will fail with the following\nerror:\n\nERROR: \"DWC_TASK_HI_SCHEDULE\" [drivers/usb/host/dwc_otg/dwc_otg.ko] undefined!\nscripts/Makefile.modpost:91: recipe for target '__modpost' failed\nmake[1]: *** [__modpost] Error 1\nMakefile:1199: recipe for target 'modules' failed\nmake: *** [modules] Error 2\n\nEven if the error is solved by including the missing\nDWC_TASK_HI_SCHEDULE function, the kernel will panic when loading\ndwc_otg.\n\nAs a workaround, simply prevent user from building dwc_otg as a module\nas the current kernel does not support it.\n\nSee: https://github.com/raspberrypi/linux/issues/2258\n\nSigned-off-by: Malik Olivier Boussejra <malik@boussejra.com>\n\ndwc_otg: New timer API\n\ndwc_otg: Fix removed ACCESS_ONCE->READ_ONCE\n\ndwc_otg: don't unconditionally force host mode in dwc_otg_cil_init()\n\nAdd the ability to disable force_host_mode for those that want to use\ndwc_otg in both device and host modes.\n\ndwc_otg: Fix a regression when dequeueing isochronous transfers\n\nIn 282bed95 (dwc_otg: make nak_holdoff work as intended with empty queues)\nthe dequeue mechanism was changed to leave FIQ-enabled transfers to run\nto completion - to avoid leaving hub TT buffers with stale packets lying\naround.\n\nThis broke FIQ-accelerated isochronous transfers, as this then meant that\ndozens of transfers were performed after the dequeue function returned.\n\nRestore the state machine fence for isochronous transfers.\n\nfiq_fsm: rewind DMA pointer for OUT transactions that fail (#2288)\n\nSee: https://github.com/raspberrypi/linux/issues/2140\n\ndwc_otg: add smp_mb() to prevent driver state corruption on boot\n\nOccasional crashes have been seen where the FIQ code dereferences\ninvalid/random pointers immediately after being set up, leading to\npanic on boot.\n\nThe crash occurs as the FIQ code races against hcd_init_fiq() and\nthe hcd_init_fiq() code races against the outstanding memory stores\nfrom dwc_otg_hcd_init(). Use explicit barriers after touching\ndriver state.\n\nusb: dwc_otg: fix memory corruption in dwc_otg driver\n\n[Upstream commit 51b1b6491752ac066ee8d32cc66042fcc955fef6]\n\nThe move from the staging tree to the main tree exposed a\nlongstanding memory corruption bug in the dwc2 driver. The\nreordering of the driver initialization caused the dwc2 driver\nto corrupt the initialization data of the sdhci driver on the\nRaspberry Pi platform, which made the bug show up.\n\nThe error is in calling to_usb_device(hsotg->dev), since ->dev\nis not a member of struct usb_device. The easiest fix is to\njust remove the offending code, since it is not really needed.\n\nThanks to Stephen Warren for tracking down the cause of this.\n\nReported-by: Andre Heider <a.heider@gmail.com>\nTested-by: Stephen Warren <swarren@wwwdotorg.org>\nSigned-off-by: Paul Zimmerman <paulz@synopsys.com>\nSigned-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>\n[lukas: port from upstream dwc2 to out-of-tree dwc_otg driver]\nSigned-off-by: Lukas Wunner <lukas@wunner.de>\n\nusb: dwb_otg: Fix unreachable switch statement warning\n\nThis warning appears with GCC 7.3.0 from toolchains.bootlin.com:\n\n../drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c: In function ‘fiq_fsm_update_hs_isoc’:\n../drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c:595:61: warning: statement will never be executed [-Wswitch-unreachable]\n   st->hctsiz_copy.b.xfersize = nrpackets * st->hcchar_copy.b.mps;\n                                            ~~~~~~~~~~~~~~~~~^~~~\n\nSigned-off-by: Nathan Chancellor <natechancellor@gmail.com>\n\ndwc_otg: fiq_fsm: fix incorrect DMA register offset calculation\n\nRationalise the offset and update all call sites.\n\nFixes https://github.com/raspberrypi/linux/issues/2408\n\ndwc_otg: fix bug with port_addr assignment for single-TT hubs\n\nSee https://github.com/raspberrypi/linux/issues/2734\n\nThe \"Hub Port\" field in the split transaction packet was always set\nto 1 for single-TT hubs. The majority of single-TT hub products\napparently ignore this field and broadcast to all downstream enabled\nports, which masked the issue. A subset of hub devices apparently\nneed the port number to be exact or split transactions will fail.\n\nusb: dwc_otg: Clean up build warnings on 64bit kernels\n\nNo functional changes. Almost all are changes to logging lines.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>\n\nusb: dwc_otg: Use dma allocation for mphi dummy_send buffer\n\nThe FIQ driver used a kzalloc'ed buffer for dummy_send,\npassing a kernel virtual address to the hardware block.\nThe buffer is only ever used for a dummy read, so it\nshould be harmless, but there is the chance that it will\ncause exceptions.\n\nUse a dma allocation so that we have a genuine bus address,\nand read from that.\nFree the allocation when done for good measure.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>\n\ndwc_otg: only do_split when we actually need to do a split\n\nThe previous test would fail if the root port was in fullspeed mode\nand there was a hub between the FS device and the root port. While\nthe transfer worked, the schedule mangling performed for high-speed\nsplit transfers would break leading to an 8ms polling interval.\n\ndwc_otg: fix locking around dequeueing and killing URBs\n\nkill_urbs_in_qh_list() is practically only ever called with the fiq lock\nalready held, so don't spinlock twice in the case where we need to cancel\nan isochronous transfer.\n\nAlso fix up a case where the global interrupt register could be read with\nthe fiq lock not held.\n\nFixes the deadlock seen in https://github.com/raspberrypi/linux/issues/2907\n\nARM64/DWC_OTG: Port dwc_otg driver to ARM64\n\nIn ARM64, the FIQ mechanism used by this driver is not current\nimplemented.   As a workaround, reqular IRQ is used instead\nof FIQ.\n\nIn a separate change, the IRQ-CPU mapping is round robined\non ARM64 to increase concurrency and allow multiple interrupts\nto be serviced at a time.  This reduces the need for FIQ.\n\nTests Run:\n\nThis mechanism is most likely to break when multiple USB devices\nare attached at the same time.  So the system was tested under\nstress.\n\nDevices:\n\n1. USB Speakers playing back a FLAC audio through VLC\n   at 96KHz.(Higher then typically, but supported on my speakers).\n\n2. sftp transferring large files through the buildin ethernet\n   connection which is connected through USB.\n\n3. Keyboard and mouse attached and being used.\n\nAlthough I do occasionally hear some glitches, the music seems to\nplay quite well.\n\nSigned-off-by: Michael Zoran <mzoran@crowfest.net>\n\nusb: dwc_otg: Clean up interrupt claiming code\n\nThe FIQ/IRQ interrupt number identification code is scattered through\nthe dwc_otg driver. Rationalise it, simplifying the code and solving\nan existing issue.\n\nSee: https://github.com/raspberrypi/linux/issues/2612\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.org>\n\ndwc_otg: Choose appropriate IRQ handover strategy\n\n2711 has no MPHI peripheral, but the ARM Control block can fake\ninterrupts. Use the size of the DTB \"mphi\" reg block to determine\nwhich is required.\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.org>\n\nusb: host: dwc_otg: fix compiling in separate directory\n\nThe dwc_otg Makefile does not respect the O=path argument correctly:\ninclude paths in CFLAGS are given relatively to object path, not source\npath. Compiling in a separate directory yields #include errors.\n\nSigned-off-by: Marek Behún <marek.behun@nic.cz>\n\ndwc_otg: use align_buf for small IN control transfers (#3150)\n\nThe hardware will do a 4-byte write to memory on any IN packet received\nthat is between 1 and 3 bytes long. This tramples memory in the uvcvideo\ndriver, as it uses a sequence of 1- and 2-byte control transfers to\nquery the min/max/range/step of each individual camera control and\ngives us buffers that are offsets into a struct.\n\nCatch small control transfers in the data phase and use the align_buf\nto bounce the correct number of bytes into the URB's buffer.\n\nIn general, short packets on non-control endpoints should be OK as URBs\nshould have enough buffer space for a wMaxPacket size transfer.\n\nSee: https://github.com/raspberrypi/linux/issues/3148\n\nSigned-off-by: Jonathan Bell <jonathan@raspberrypi.org>\n\ndwc_otg: Declare DMA capability with HCD_DMA flag\n\nFollowing [1], USB controllers have to declare DMA capabilities in\norder for them to be used by adding the HCD_DMA flag to their hc_driver\nstruct.\n\n[1] 7b81cb6bddd2 (\"usb: add a HCD_DMA flag instead of guestimating DMA capabilities\")\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.org>\n\ndwc_otg: checking the urb->transfer_buffer too early (#3332)\n\nAfter enable the HIGHMEM and VMSPLIT_3G, the dwc_otg driver doesn't\nwork well on Pi2/3 boards with 1G physical ram. Users experience\nthe failure when copying a file of 600M size to the USB stick. And\nat the same time, the dmesg shows:\nusb 1-1.1.2: reset high-speed USB device number 8 using dwc_otg\nsd 0:0:0:0: [sda] tag#0 FAILED Result: hostbyte=DID_ERROR driverbyte=DRIVER_OK\nblk_update_request: I/O error, dev sda, sector 3024048 op 0x1:(WRITE) flags 0x4000 phys_seg 15 prio class 0\n\nWhen this happens, the sg_buf sent to the driver is located in the\nhighmem region, the usb_sg_init() in the core/message.c will leave\ntransfer_buffer to NULL if the sg_buf is in highmem, but in the\ndwc_otg driver, it returns -EINVAL unconditionally if transfer_buffer\nis NULL.\n\nThe driver can handle the situation of buffer to be NULL, if it is in\nDMA mode, it will convert an address from transfer_dma.\n\nBut if the conversion fails or it is in the PIO mode, we should check\nbuffer and return -EINVAL if it is NULL.\n\nBugLink: https://bugs.launchpad.net/bugs/1852510\nSigned-off-by: Hui Wang <hui.wang@canonical.com>\n\ndwc_otg: constrain endpoint max packet and transfer size on split IN\n\nThe hcd would unconditionally set the transfer length to the endpoint\npacket size for non-isoc IN transfers. If the remaining buffer length\nwas less than the length of returned data, random memory would get\nscribbled over, with bad effects if it crossed a page boundary.\n\nForce a babble error if this happens by limiting the max transfer size\nto the available buffer space. DMA will stop writing to memory on a\nbabble condition.\n\nThe hardware expects xfersize to be an integer multiple of maxpacket\nsize, so override hcchar.b.mps as well.\n\nSigned-off-by: Jonathan Bell <jonathan@raspberrypi.org>\n\ndwc_otg: fiq_fsm: pause when cancelling split transactions\n\nNon-periodic splits will DMA to/from the driver-provided transfer_buffer,\nwhich may be freed immediately after the dequeue call returns. Block until\nwe know the transfer is complete.\n\nA similar delay is needed when cleaning up disconnects, as the FIQ could\nhave started a periodic transfer in the previous microframe to the one\nthat triggered a disconnect.\n\nSigned-off-by: Jonathan Bell <jonathan@raspberrypi.org>\n\ndwc_otg: fiq_fsm: add a barrier on entry into FIQ handler(s)\n\nOn BCM2835, there is no hardware guarantee that multiple outstanding\nreads to different peripherals will complete in-order. The FIQ code\nuses peripheral reads without barriers for performance, so in the case\nwhere a read to a slow peripheral was issued immediately prior to FIQ\nentry, the first peripheral read that the FIQ did could end up with\nwrong read data returned.\n\nAdd dsb(sy) on entry so that all outstanding reads are retired.\n\nThe FIQ only issues reads to the dwc_otg core, so per-read barriers\nin the handler itself are not required.\n\nOn BCM2836 and BCM2837 the barrier is not strictly required due to\ndifferences in how the peripheral bus is implemented, but having\narch-specific handlers that introduce different latencies is risky.\n\nSigned-off-by: Jonathan Bell <jonathan@raspberrypi.org>\n---\n arch/arm/include/asm/irqflags.h               |   16 +-\n arch/arm/kernel/fiqasm.S                      |    4 +\n drivers/usb/Makefile                          |    1 +\n drivers/usb/core/generic.c                    |    1 +\n drivers/usb/core/hub.c                        |    2 +-\n drivers/usb/core/message.c                    |   79 +\n drivers/usb/core/otg_productlist.h            |  114 +-\n drivers/usb/gadget/file_storage.c             | 3676 +++++++++\n drivers/usb/host/Kconfig                      |   10 +\n drivers/usb/host/Makefile                     |    1 +\n drivers/usb/host/dwc_common_port/Makefile     |   58 +\n .../usb/host/dwc_common_port/Makefile.fbsd    |   17 +\n .../usb/host/dwc_common_port/Makefile.linux   |   49 +\n drivers/usb/host/dwc_common_port/changes.txt  |  174 +\n .../usb/host/dwc_common_port/doc/doxygen.cfg  |  270 +\n drivers/usb/host/dwc_common_port/dwc_cc.c     |  532 ++\n drivers/usb/host/dwc_common_port/dwc_cc.h     |  224 +\n .../host/dwc_common_port/dwc_common_fbsd.c    | 1308 +++\n .../host/dwc_common_port/dwc_common_linux.c   | 1409 ++++\n .../host/dwc_common_port/dwc_common_nbsd.c    | 1275 +++\n drivers/usb/host/dwc_common_port/dwc_crypto.c |  308 +\n drivers/usb/host/dwc_common_port/dwc_crypto.h |  111 +\n drivers/usb/host/dwc_common_port/dwc_dh.c     |  291 +\n drivers/usb/host/dwc_common_port/dwc_dh.h     |  106 +\n drivers/usb/host/dwc_common_port/dwc_list.h   |  594 ++\n drivers/usb/host/dwc_common_port/dwc_mem.c    |  245 +\n drivers/usb/host/dwc_common_port/dwc_modpow.c |  636 ++\n drivers/usb/host/dwc_common_port/dwc_modpow.h |   34 +\n .../usb/host/dwc_common_port/dwc_notifier.c   |  319 +\n .../usb/host/dwc_common_port/dwc_notifier.h   |  122 +\n drivers/usb/host/dwc_common_port/dwc_os.h     | 1276 +++\n drivers/usb/host/dwc_common_port/usb.h        |  946 +++\n drivers/usb/host/dwc_otg/Makefile             |   85 +\n drivers/usb/host/dwc_otg/doc/doxygen.cfg      |  224 +\n drivers/usb/host/dwc_otg/dummy_audio.c        | 1574 ++++\n drivers/usb/host/dwc_otg/dwc_cfi_common.h     |  142 +\n drivers/usb/host/dwc_otg/dwc_otg_adp.c        |  854 ++\n drivers/usb/host/dwc_otg/dwc_otg_adp.h        |   80 +\n drivers/usb/host/dwc_otg/dwc_otg_attr.c       | 1212 +++\n drivers/usb/host/dwc_otg/dwc_otg_attr.h       |   89 +\n drivers/usb/host/dwc_otg/dwc_otg_cfi.c        | 1876 +++++\n drivers/usb/host/dwc_otg/dwc_otg_cfi.h        |  320 +\n drivers/usb/host/dwc_otg/dwc_otg_cil.c        | 7146 +++++++++++++++++\n drivers/usb/host/dwc_otg/dwc_otg_cil.h        | 1464 ++++\n drivers/usb/host/dwc_otg/dwc_otg_cil_intr.c   | 1601 ++++\n drivers/usb/host/dwc_otg/dwc_otg_core_if.h    |  705 ++\n drivers/usb/host/dwc_otg/dwc_otg_dbg.h        |  117 +\n drivers/usb/host/dwc_otg/dwc_otg_driver.c     | 1772 ++++\n drivers/usb/host/dwc_otg/dwc_otg_driver.h     |   86 +\n drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c    | 1431 ++++\n drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.h    |  399 +\n drivers/usb/host/dwc_otg/dwc_otg_fiq_stub.S   |   80 +\n drivers/usb/host/dwc_otg/dwc_otg_hcd.c        | 4356 ++++++++++\n drivers/usb/host/dwc_otg/dwc_otg_hcd.h        |  870 ++\n drivers/usb/host/dwc_otg/dwc_otg_hcd_ddma.c   | 1134 +++\n drivers/usb/host/dwc_otg/dwc_otg_hcd_if.h     |  421 +\n drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c   | 2757 +++++++\n drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c  | 1086 +++\n drivers/usb/host/dwc_otg/dwc_otg_hcd_queue.c  |  970 +++\n drivers/usb/host/dwc_otg/dwc_otg_os_dep.h     |  200 +\n drivers/usb/host/dwc_otg/dwc_otg_pcd.c        | 2725 +++++++\n drivers/usb/host/dwc_otg/dwc_otg_pcd.h        |  273 +\n drivers/usb/host/dwc_otg/dwc_otg_pcd_if.h     |  361 +\n drivers/usb/host/dwc_otg/dwc_otg_pcd_intr.c   | 5148 ++++++++++++\n drivers/usb/host/dwc_otg/dwc_otg_pcd_linux.c  | 1262 +++\n drivers/usb/host/dwc_otg/dwc_otg_regs.h       | 2550 ++++++\n drivers/usb/host/dwc_otg/test/Makefile        |   16 +\n drivers/usb/host/dwc_otg/test/dwc_otg_test.pm |  337 +\n .../usb/host/dwc_otg/test/test_mod_param.pl   |  133 +\n drivers/usb/host/dwc_otg/test/test_sysfs.pl   |  193 +\n 70 files changed, 60241 insertions(+), 16 deletions(-)\n create mode 100644 drivers/usb/gadget/file_storage.c\n create mode 100644 drivers/usb/host/dwc_common_port/Makefile\n create mode 100644 drivers/usb/host/dwc_common_port/Makefile.fbsd\n create mode 100644 drivers/usb/host/dwc_common_port/Makefile.linux\n create mode 100644 drivers/usb/host/dwc_common_port/changes.txt\n create mode 100644 drivers/usb/host/dwc_common_port/doc/doxygen.cfg\n create mode 100644 drivers/usb/host/dwc_common_port/dwc_cc.c\n create mode 100644 drivers/usb/host/dwc_common_port/dwc_cc.h\n create mode 100644 drivers/usb/host/dwc_common_port/dwc_common_fbsd.c\n create mode 100644 drivers/usb/host/dwc_common_port/dwc_common_linux.c\n create mode 100644 drivers/usb/host/dwc_common_port/dwc_common_nbsd.c\n create mode 100644 drivers/usb/host/dwc_common_port/dwc_crypto.c\n create mode 100644 drivers/usb/host/dwc_common_port/dwc_crypto.h\n create mode 100644 drivers/usb/host/dwc_common_port/dwc_dh.c\n create mode 100644 drivers/usb/host/dwc_common_port/dwc_dh.h\n create mode 100644 drivers/usb/host/dwc_common_port/dwc_list.h\n create mode 100644 drivers/usb/host/dwc_common_port/dwc_mem.c\n create mode 100644 drivers/usb/host/dwc_common_port/dwc_modpow.c\n create mode 100644 drivers/usb/host/dwc_common_port/dwc_modpow.h\n create mode 100644 drivers/usb/host/dwc_common_port/dwc_notifier.c\n create mode 100644 drivers/usb/host/dwc_common_port/dwc_notifier.h\n create mode 100644 drivers/usb/host/dwc_common_port/dwc_os.h\n create mode 100644 drivers/usb/host/dwc_common_port/usb.h\n create mode 100644 drivers/usb/host/dwc_otg/Makefile\n create mode 100644 drivers/usb/host/dwc_otg/doc/doxygen.cfg\n create mode 100644 drivers/usb/host/dwc_otg/dummy_audio.c\n create mode 100644 drivers/usb/host/dwc_otg/dwc_cfi_common.h\n create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_adp.c\n create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_adp.h\n create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_attr.c\n create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_attr.h\n create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_cfi.c\n create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_cfi.h\n create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_cil.c\n create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_cil.h\n create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_cil_intr.c\n create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_core_if.h\n create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_dbg.h\n create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_driver.c\n create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_driver.h\n create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c\n create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.h\n create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_fiq_stub.S\n create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_hcd.c\n create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_hcd.h\n create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_hcd_ddma.c\n create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_hcd_if.h\n create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c\n create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c\n create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_hcd_queue.c\n create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_os_dep.h\n create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_pcd.c\n create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_pcd.h\n create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_pcd_if.h\n create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_pcd_intr.c\n create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_pcd_linux.c\n create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_regs.h\n create mode 100644 drivers/usb/host/dwc_otg/test/Makefile\n create mode 100644 drivers/usb/host/dwc_otg/test/dwc_otg_test.pm\n create mode 100644 drivers/usb/host/dwc_otg/test/test_mod_param.pl\n create mode 100644 drivers/usb/host/dwc_otg/test/test_sysfs.pl\n\n--- a/arch/arm/include/asm/irqflags.h\n+++ b/arch/arm/include/asm/irqflags.h\n@@ -163,13 +163,23 @@ static inline unsigned long arch_local_s\n }\n \n /*\n- * restore saved IRQ & FIQ state\n+ * restore saved IRQ state\n  */\n #define arch_local_irq_restore arch_local_irq_restore\n static inline void arch_local_irq_restore(unsigned long flags)\n {\n-\tasm volatile(\n-\t\t\"\tmsr\t\" IRQMASK_REG_NAME_W \", %0\t@ local_irq_restore\"\n+\tunsigned long temp = 0;\n+\tflags &= ~(1 << 6);\n+\tasm volatile (\n+\t\t\" mrs %0, cpsr\"\n+\t\t: \"=r\" (temp)\n+\t\t:\n+\t\t: \"memory\", \"cc\");\n+\t\t/* Preserve FIQ bit */\n+\t\ttemp &= (1 << 6);\n+\t\tflags = flags | temp;\n+\tasm volatile (\n+\t\t\"    msr    cpsr_c, %0    @ local_irq_restore\"\n \t\t:\n \t\t: \"r\" (flags)\n \t\t: \"memory\", \"cc\");\n--- a/arch/arm/kernel/fiqasm.S\n+++ b/arch/arm/kernel/fiqasm.S\n@@ -47,3 +47,7 @@ ENTRY(__get_fiq_regs)\n \tmov\tr0, r0\t\t@ avoid hazard prior to ARMv4\n \tret\tlr\n ENDPROC(__get_fiq_regs)\n+\n+ENTRY(__FIQ_Branch)\n+\tmov pc, r8\n+ENDPROC(__FIQ_Branch)\n--- a/drivers/usb/Makefile\n+++ b/drivers/usb/Makefile\n@@ -9,6 +9,7 @@ obj-$(CONFIG_USB_COMMON)\t+= common/\n obj-$(CONFIG_USB)\t\t+= core/\n obj-$(CONFIG_USB_SUPPORT)\t+= phy/\n \n+obj-$(CONFIG_USB_DWCOTG)\t+= host/\n obj-$(CONFIG_USB_DWC3)\t\t+= dwc3/\n obj-$(CONFIG_USB_DWC2)\t\t+= dwc2/\n obj-$(CONFIG_USB_ISP1760)\t+= isp1760/\n--- a/drivers/usb/core/generic.c\n+++ b/drivers/usb/core/generic.c\n@@ -190,6 +190,7 @@ int usb_choose_configuration(struct usb_\n \t\tdev_warn(&udev->dev,\n \t\t\t\"no configuration chosen from %d choice%s\\n\",\n \t\t\tnum_configs, plural(num_configs));\n+\t\tdev_warn(&udev->dev, \"No support over %dmA\\n\", udev->bus_mA);\n \t}\n \treturn i;\n }\n--- a/drivers/usb/core/hub.c\n+++ b/drivers/usb/core/hub.c\n@@ -5506,7 +5506,7 @@ static void port_event(struct usb_hub *h\n \t\tport_dev->over_current_count++;\n \t\tport_over_current_notify(port_dev);\n \n-\t\tdev_dbg(&port_dev->dev, \"over-current change #%u\\n\",\n+\t\tdev_notice(&port_dev->dev, \"over-current change #%u\\n\",\n \t\t\tport_dev->over_current_count);\n \t\tusb_clear_port_feature(hdev, port1,\n \t\t\t\tUSB_PORT_FEAT_C_OVER_CURRENT);\n--- a/drivers/usb/core/message.c\n+++ b/drivers/usb/core/message.c\n@@ -2135,6 +2135,85 @@ free_interfaces:\n \tif (cp->string == NULL &&\n \t\t\t!(dev->quirks & USB_QUIRK_CONFIG_INTF_STRINGS))\n \t\tcp->string = usb_cache_string(dev, cp->desc.iConfiguration);\n+/* Uncomment this define to enable the HS Electrical Test support */\n+#define DWC_HS_ELECT_TST 1\n+#ifdef DWC_HS_ELECT_TST\n+\t\t/* Here we implement the HS Electrical Test support. The\n+\t\t * tester uses a vendor ID of 0x1A0A to indicate we should\n+\t\t * run a special test sequence. The product ID tells us\n+\t\t * which sequence to run. We invoke the test sequence by\n+\t\t * sending a non-standard SetFeature command to our root\n+\t\t * hub port. Our dwc_otg_hcd_hub_control() routine will\n+\t\t * recognize the command and perform the desired test\n+\t\t * sequence.\n+\t\t */\n+\t\tif (dev->descriptor.idVendor == 0x1A0A) {\n+\t\t\t/* HSOTG Electrical Test */\n+\t\t\tdev_warn(&dev->dev, \"VID from HSOTG Electrical Test Fixture\\n\");\n+\n+\t\t\tif (dev->bus && dev->bus->root_hub) {\n+\t\t\t\tstruct usb_device *hdev = dev->bus->root_hub;\n+\t\t\t\tdev_warn(&dev->dev, \"Got PID 0x%x\\n\", dev->descriptor.idProduct);\n+\n+\t\t\t\tswitch (dev->descriptor.idProduct) {\n+\t\t\t\tcase 0x0101:\t/* TEST_SE0_NAK */\n+\t\t\t\t\tdev_warn(&dev->dev, \"TEST_SE0_NAK\\n\");\n+\t\t\t\t\tusb_control_msg(hdev, usb_sndctrlpipe(hdev, 0),\n+\t\t\t\t\t\t\tUSB_REQ_SET_FEATURE, USB_RT_PORT,\n+\t\t\t\t\t\t\tUSB_PORT_FEAT_TEST, 0x300, NULL, 0, HZ);\n+\t\t\t\t\tbreak;\n+\n+\t\t\t\tcase 0x0102:\t/* TEST_J */\n+\t\t\t\t\tdev_warn(&dev->dev, \"TEST_J\\n\");\n+\t\t\t\t\tusb_control_msg(hdev, usb_sndctrlpipe(hdev, 0),\n+\t\t\t\t\t\t\tUSB_REQ_SET_FEATURE, USB_RT_PORT,\n+\t\t\t\t\t\t\tUSB_PORT_FEAT_TEST, 0x100, NULL, 0, HZ);\n+\t\t\t\t\tbreak;\n+\n+\t\t\t\tcase 0x0103:\t/* TEST_K */\n+\t\t\t\t\tdev_warn(&dev->dev, \"TEST_K\\n\");\n+\t\t\t\t\tusb_control_msg(hdev, usb_sndctrlpipe(hdev, 0),\n+\t\t\t\t\t\t\tUSB_REQ_SET_FEATURE, USB_RT_PORT,\n+\t\t\t\t\t\t\tUSB_PORT_FEAT_TEST, 0x200, NULL, 0, HZ);\n+\t\t\t\t\tbreak;\n+\n+\t\t\t\tcase 0x0104:\t/* TEST_PACKET */\n+\t\t\t\t\tdev_warn(&dev->dev, \"TEST_PACKET\\n\");\n+\t\t\t\t\tusb_control_msg(hdev, usb_sndctrlpipe(hdev, 0),\n+\t\t\t\t\t\t\tUSB_REQ_SET_FEATURE, USB_RT_PORT,\n+\t\t\t\t\t\t\tUSB_PORT_FEAT_TEST, 0x400, NULL, 0, HZ);\n+\t\t\t\t\tbreak;\n+\n+\t\t\t\tcase 0x0105:\t/* TEST_FORCE_ENABLE */\n+\t\t\t\t\tdev_warn(&dev->dev, \"TEST_FORCE_ENABLE\\n\");\n+\t\t\t\t\tusb_control_msg(hdev, usb_sndctrlpipe(hdev, 0),\n+\t\t\t\t\t\t\tUSB_REQ_SET_FEATURE, USB_RT_PORT,\n+\t\t\t\t\t\t\tUSB_PORT_FEAT_TEST, 0x500, NULL, 0, HZ);\n+\t\t\t\t\tbreak;\n+\n+\t\t\t\tcase 0x0106:\t/* HS_HOST_PORT_SUSPEND_RESUME */\n+\t\t\t\t\tdev_warn(&dev->dev, \"HS_HOST_PORT_SUSPEND_RESUME\\n\");\n+\t\t\t\t\tusb_control_msg(hdev, usb_sndctrlpipe(hdev, 0),\n+\t\t\t\t\t\t\tUSB_REQ_SET_FEATURE, USB_RT_PORT,\n+\t\t\t\t\t\t\tUSB_PORT_FEAT_TEST, 0x600, NULL, 0, 40 * HZ);\n+\t\t\t\t\tbreak;\n+\n+\t\t\t\tcase 0x0107:\t/* SINGLE_STEP_GET_DEVICE_DESCRIPTOR setup */\n+\t\t\t\t\tdev_warn(&dev->dev, \"SINGLE_STEP_GET_DEVICE_DESCRIPTOR setup\\n\");\n+\t\t\t\t\tusb_control_msg(hdev, usb_sndctrlpipe(hdev, 0),\n+\t\t\t\t\t\t\tUSB_REQ_SET_FEATURE, USB_RT_PORT,\n+\t\t\t\t\t\t\tUSB_PORT_FEAT_TEST, 0x700, NULL, 0, 40 * HZ);\n+\t\t\t\t\tbreak;\n+\n+\t\t\t\tcase 0x0108:\t/* SINGLE_STEP_GET_DEVICE_DESCRIPTOR execute */\n+\t\t\t\t\tdev_warn(&dev->dev, \"SINGLE_STEP_GET_DEVICE_DESCRIPTOR execute\\n\");\n+\t\t\t\t\tusb_control_msg(hdev, usb_sndctrlpipe(hdev, 0),\n+\t\t\t\t\t\t\tUSB_REQ_SET_FEATURE, USB_RT_PORT,\n+\t\t\t\t\t\t\tUSB_PORT_FEAT_TEST, 0x800, NULL, 0, 40 * HZ);\n+\t\t\t\t}\n+\t\t\t}\n+\t\t}\n+#endif /* DWC_HS_ELECT_TST */\n \n \t/* Now that the interfaces are installed, re-enable LPM. */\n \tusb_unlocked_enable_lpm(dev);\n--- a/drivers/usb/core/otg_productlist.h\n+++ b/drivers/usb/core/otg_productlist.h\n@@ -11,33 +11,82 @@\n static struct usb_device_id productlist_table[] = {\n \n /* hubs are optional in OTG, but very handy ... */\n+#define CERT_WITHOUT_HUBS\n+#if defined(CERT_WITHOUT_HUBS)\n+{ USB_DEVICE( 0x0000, 0x0000 ), }, /* Root HUB Only*/\n+#else\n { USB_DEVICE_INFO(USB_CLASS_HUB, 0, 0), },\n { USB_DEVICE_INFO(USB_CLASS_HUB, 0, 1), },\n+{ USB_DEVICE_INFO(USB_CLASS_HUB, 0, 2), },\n+#endif\n \n #ifdef\tCONFIG_USB_PRINTER\t\t/* ignoring nonstatic linkage! */\n /* FIXME actually, printers are NOT supposed to use device classes;\n  * they're supposed to use interface classes...\n  */\n-{ USB_DEVICE_INFO(7, 1, 1) },\n-{ USB_DEVICE_INFO(7, 1, 2) },\n-{ USB_DEVICE_INFO(7, 1, 3) },\n+//{ USB_DEVICE_INFO(7, 1, 1) },\n+//{ USB_DEVICE_INFO(7, 1, 2) },\n+//{ USB_DEVICE_INFO(7, 1, 3) },\n #endif\n \n #ifdef\tCONFIG_USB_NET_CDCETHER\n /* Linux-USB CDC Ethernet gadget */\n-{ USB_DEVICE(0x0525, 0xa4a1), },\n+//{ USB_DEVICE(0x0525, 0xa4a1), },\n /* Linux-USB CDC Ethernet + RNDIS gadget */\n-{ USB_DEVICE(0x0525, 0xa4a2), },\n+//{ USB_DEVICE(0x0525, 0xa4a2), },\n #endif\n \n #if\tIS_ENABLED(CONFIG_USB_TEST)\n /* gadget zero, for testing */\n-{ USB_DEVICE(0x0525, 0xa4a0), },\n+//{ USB_DEVICE(0x0525, 0xa4a0), },\n #endif\n \n+/* OPT Tester */\n+{ USB_DEVICE( 0x1a0a, 0x0101 ), }, /* TEST_SE0_NAK */\n+{ USB_DEVICE( 0x1a0a, 0x0102 ), }, /* Test_J */\n+{ USB_DEVICE( 0x1a0a, 0x0103 ), }, /* Test_K */\n+{ USB_DEVICE( 0x1a0a, 0x0104 ), }, /* Test_PACKET */\n+{ USB_DEVICE( 0x1a0a, 0x0105 ), }, /* Test_FORCE_ENABLE */\n+{ USB_DEVICE( 0x1a0a, 0x0106 ), }, /* HS_PORT_SUSPEND_RESUME  */\n+{ USB_DEVICE( 0x1a0a, 0x0107 ), }, /* SINGLE_STEP_GET_DESCRIPTOR setup */\n+{ USB_DEVICE( 0x1a0a, 0x0108 ), }, /* SINGLE_STEP_GET_DESCRIPTOR execute */\n+\n+/* Sony cameras */\n+{ USB_DEVICE_VER(0x054c,0x0010,0x0410, 0x0500), },\n+\n+/* Memory Devices */\n+//{ USB_DEVICE( 0x0781, 0x5150 ), }, /* SanDisk */\n+//{ USB_DEVICE( 0x05DC, 0x0080 ), }, /* Lexar */\n+//{ USB_DEVICE( 0x4146, 0x9281 ), }, /* IOMEGA */\n+//{ USB_DEVICE( 0x067b, 0x2507 ), }, /* Hammer 20GB External HD  */\n+{ USB_DEVICE( 0x0EA0, 0x2168 ), }, /* Ours Technology Inc. (BUFFALO ClipDrive)*/\n+//{ USB_DEVICE( 0x0457, 0x0150 ), }, /* Silicon Integrated Systems Corp. */\n+\n+/* HP Printers */\n+//{ USB_DEVICE( 0x03F0, 0x1102 ), }, /* HP Photosmart 245 */\n+//{ USB_DEVICE( 0x03F0, 0x1302 ), }, /* HP Photosmart 370 Series */\n+\n+/* Speakers */\n+//{ USB_DEVICE( 0x0499, 0x3002 ), }, /* YAMAHA YST-MS35D USB Speakers */\n+//{ USB_DEVICE( 0x0672, 0x1041 ), }, /* Labtec USB Headset */\n+\n { }\t/* Terminating entry */\n };\n \n+static inline void report_errors(struct usb_device *dev)\n+{\n+\t/* OTG MESSAGE: report errors here, customize to match your product */\n+\tdev_info(&dev->dev, \"device Vendor:%04x Product:%04x is not supported\\n\",\n+\t\t le16_to_cpu(dev->descriptor.idVendor),\n+\t\t le16_to_cpu(dev->descriptor.idProduct));\n+        if (USB_CLASS_HUB == dev->descriptor.bDeviceClass){\n+                dev_printk(KERN_CRIT, &dev->dev, \"Unsupported Hub Topology\\n\");\n+        } else {\n+                dev_printk(KERN_CRIT, &dev->dev, \"Attached Device is not Supported\\n\");\n+        }\n+}\n+\n+\n static int is_targeted(struct usb_device *dev)\n {\n \tstruct usb_device_id\t*id = productlist_table;\n@@ -87,16 +136,57 @@ static int is_targeted(struct usb_device\n \t\t\tcontinue;\n \n \t\treturn 1;\n-\t}\n+\t\t/* NOTE: can't use usb_match_id() since interface caches\n+\t\t * aren't set up yet. this is cut/paste from that code.\n+\t\t */\n+\t\tfor (id = whitelist_table; id->match_flags; id++) {\n+#ifdef DEBUG\n+\t\t\tdev_dbg(&dev->dev,\n+\t\t\t\t\"ID: V:%04x P:%04x DC:%04x SC:%04x PR:%04x \\n\",\n+\t\t\t\tid->idVendor,\n+\t\t\t\tid->idProduct,\n+\t\t\t\tid->bDeviceClass,\n+\t\t\t\tid->bDeviceSubClass,\n+\t\t\t\tid->bDeviceProtocol);\n+#endif\n \n-\t/* add other match criteria here ... */\n+\t\t\tif ((id->match_flags & USB_DEVICE_ID_MATCH_VENDOR) &&\n+\t\t\t    id->idVendor != le16_to_cpu(dev->descriptor.idVendor))\n+\t\t\t\tcontinue;\n+\n+\t\t\tif ((id->match_flags & USB_DEVICE_ID_MATCH_PRODUCT) &&\n+\t\t\t    id->idProduct != le16_to_cpu(dev->descriptor.idProduct))\n+\t\t\t\tcontinue;\n+\n+\t\t\t/* No need to test id->bcdDevice_lo != 0, since 0 is never\n+\t\t\t   greater than any unsigned number. */\n+\t\t\tif ((id->match_flags & USB_DEVICE_ID_MATCH_DEV_LO) &&\n+\t\t\t    (id->bcdDevice_lo > le16_to_cpu(dev->descriptor.bcdDevice)))\n+\t\t\t\tcontinue;\n+\n+\t\t\tif ((id->match_flags & USB_DEVICE_ID_MATCH_DEV_HI) &&\n+\t\t\t    (id->bcdDevice_hi < le16_to_cpu(dev->descriptor.bcdDevice)))\n+\t\t\t\tcontinue;\n+\n+\t\t\tif ((id->match_flags & USB_DEVICE_ID_MATCH_DEV_CLASS) &&\n+\t\t\t    (id->bDeviceClass != dev->descriptor.bDeviceClass))\n+\t\t\t\tcontinue;\n+\n+\t\t\tif ((id->match_flags & USB_DEVICE_ID_MATCH_DEV_SUBCLASS) &&\n+\t\t\t    (id->bDeviceSubClass != dev->descriptor.bDeviceSubClass))\n+\t\t\t\tcontinue;\n+\n+\t\t\tif ((id->match_flags & USB_DEVICE_ID_MATCH_DEV_PROTOCOL) &&\n+\t\t\t    (id->bDeviceProtocol != dev->descriptor.bDeviceProtocol))\n+\t\t\t\tcontinue;\n \n+\t\t\treturn 1;\n+\t\t}\n+\t}\n \n-\t/* OTG MESSAGE: report errors here, customize to match your product */\n-\tdev_err(&dev->dev, \"device v%04x p%04x is not supported\\n\",\n-\t\tle16_to_cpu(dev->descriptor.idVendor),\n-\t\tle16_to_cpu(dev->descriptor.idProduct));\n+\t/* add other match criteria here ... */\n \n+\treport_errors(dev);\n \treturn 0;\n }\n \n--- /dev/null\n+++ b/drivers/usb/gadget/file_storage.c\n@@ -0,0 +1,3676 @@\n+/*\n+ * file_storage.c -- File-backed USB Storage Gadget, for USB development\n+ *\n+ * Copyright (C) 2003-2008 Alan Stern\n+ * All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ * 1. Redistributions of source code must retain the above copyright\n+ *    notice, this list of conditions, and the following disclaimer,\n+ *    without modification.\n+ * 2. Redistributions in binary form must reproduce the above copyright\n+ *    notice, this list of conditions and the following disclaimer in the\n+ *    documentation and/or other materials provided with the distribution.\n+ * 3. The names of the above-listed copyright holders may not be used\n+ *    to endorse or promote products derived from this software without\n+ *    specific prior written permission.\n+ *\n+ * ALTERNATIVELY, this software may be distributed under the terms of the\n+ * GNU General Public License (\"GPL\") as published by the Free Software\n+ * Foundation, either version 2 of that License or (at your option) any\n+ * later version.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS\n+ * IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,\n+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\n+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR\n+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\n+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\n+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR\n+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\n+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\n+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+\n+/*\n+ * The File-backed Storage Gadget acts as a USB Mass Storage device,\n+ * appearing to the host as a disk drive or as a CD-ROM drive.  In addition\n+ * to providing an example of a genuinely useful gadget driver for a USB\n+ * device, it also illustrates a technique of double-buffering for increased\n+ * throughput.  Last but not least, it gives an easy way to probe the\n+ * behavior of the Mass Storage drivers in a USB host.\n+ *\n+ * Backing storage is provided by a regular file or a block device, specified\n+ * by the \"file\" module parameter.  Access can be limited to read-only by\n+ * setting the optional \"ro\" module parameter.  (For CD-ROM emulation,\n+ * access is always read-only.)  The gadget will indicate that it has\n+ * removable media if the optional \"removable\" module parameter is set.\n+ *\n+ * The gadget supports the Control-Bulk (CB), Control-Bulk-Interrupt (CBI),\n+ * and Bulk-Only (also known as Bulk-Bulk-Bulk or BBB) transports, selected\n+ * by the optional \"transport\" module parameter.  It also supports the\n+ * following protocols: RBC (0x01), ATAPI or SFF-8020i (0x02), QIC-157 (0c03),\n+ * UFI (0x04), SFF-8070i (0x05), and transparent SCSI (0x06), selected by\n+ * the optional \"protocol\" module parameter.  In addition, the default\n+ * Vendor ID, Product ID, release number and serial number can be overridden.\n+ *\n+ * There is support for multiple logical units (LUNs), each of which has\n+ * its own backing file.  The number of LUNs can be set using the optional\n+ * \"luns\" module parameter (anywhere from 1 to 8), and the corresponding\n+ * files are specified using comma-separated lists for \"file\" and \"ro\".\n+ * The default number of LUNs is taken from the number of \"file\" elements;\n+ * it is 1 if \"file\" is not given.  If \"removable\" is not set then a backing\n+ * file must be specified for each LUN.  If it is set, then an unspecified\n+ * or empty backing filename means the LUN's medium is not loaded.  Ideally\n+ * each LUN would be settable independently as a disk drive or a CD-ROM\n+ * drive, but currently all LUNs have to be the same type.  The CD-ROM\n+ * emulation includes a single data track and no audio tracks; hence there\n+ * need be only one backing file per LUN.\n+ *\n+ * Requirements are modest; only a bulk-in and a bulk-out endpoint are\n+ * needed (an interrupt-out endpoint is also needed for CBI).  The memory\n+ * requirement amounts to two 16K buffers, size configurable by a parameter.\n+ * Support is included for both full-speed and high-speed operation.\n+ *\n+ * Note that the driver is slightly non-portable in that it assumes a\n+ * single memory/DMA buffer will be useable for bulk-in, bulk-out, and\n+ * interrupt-in endpoints.  With most device controllers this isn't an\n+ * issue, but there may be some with hardware restrictions that prevent\n+ * a buffer from being used by more than one endpoint.\n+ *\n+ * Module options:\n+ *\n+ *\tfile=filename[,filename...]\n+ *\t\t\t\tRequired if \"removable\" is not set, names of\n+ *\t\t\t\t\tthe files or block devices used for\n+ *\t\t\t\t\tbacking storage\n+ *\tserial=HHHH...\t\tRequired serial number (string of hex chars)\n+ *\tro=b[,b...]\t\tDefault false, booleans for read-only access\n+ *\tremovable\t\tDefault false, boolean for removable media\n+ *\tluns=N\t\t\tDefault N = number of filenames, number of\n+ *\t\t\t\t\tLUNs to support\n+ *\tnofua=b[,b...]\t\tDefault false, booleans for ignore FUA flag\n+ *\t\t\t\t\tin SCSI WRITE(10,12) commands\n+ *\tstall\t\t\tDefault determined according to the type of\n+ *\t\t\t\t\tUSB device controller (usually true),\n+ *\t\t\t\t\tboolean to permit the driver to halt\n+ *\t\t\t\t\tbulk endpoints\n+ *\tcdrom\t\t\tDefault false, boolean for whether to emulate\n+ *\t\t\t\t\ta CD-ROM drive\n+ *\ttransport=XXX\t\tDefault BBB, transport name (CB, CBI, or BBB)\n+ *\tprotocol=YYY\t\tDefault SCSI, protocol name (RBC, 8020 or\n+ *\t\t\t\t\tATAPI, QIC, UFI, 8070, or SCSI;\n+ *\t\t\t\t\talso 1 - 6)\n+ *\tvendor=0xVVVV\t\tDefault 0x0525 (NetChip), USB Vendor ID\n+ *\tproduct=0xPPPP\t\tDefault 0xa4a5 (FSG), USB Product ID\n+ *\trelease=0xRRRR\t\tOverride the USB release number (bcdDevice)\n+ *\tbuflen=N\t\tDefault N=16384, buffer size used (will be\n+ *\t\t\t\t\trounded down to a multiple of\n+ *\t\t\t\t\tPAGE_CACHE_SIZE)\n+ *\n+ * If CONFIG_USB_FILE_STORAGE_TEST is not set, only the \"file\", \"serial\", \"ro\",\n+ * \"removable\", \"luns\", \"nofua\", \"stall\", and \"cdrom\" options are available;\n+ * default values are used for everything else.\n+ *\n+ * The pathnames of the backing files and the ro settings are available in\n+ * the attribute files \"file\", \"nofua\", and \"ro\" in the lun<n> subdirectory of\n+ * the gadget's sysfs directory.  If the \"removable\" option is set, writing to\n+ * these files will simulate ejecting/loading the medium (writing an empty\n+ * line means eject) and adjusting a write-enable tab.  Changes to the ro\n+ * setting are not allowed when the medium is loaded or if CD-ROM emulation\n+ * is being used.\n+ *\n+ * This gadget driver is heavily based on \"Gadget Zero\" by David Brownell.\n+ * The driver's SCSI command interface was based on the \"Information\n+ * technology - Small Computer System Interface - 2\" document from\n+ * X3T9.2 Project 375D, Revision 10L, 7-SEP-93, available at\n+ * <http://www.t10.org/ftp/t10/drafts/s2/s2-r10l.pdf>.  The single exception\n+ * is opcode 0x23 (READ FORMAT CAPACITIES), which was based on the\n+ * \"Universal Serial Bus Mass Storage Class UFI Command Specification\"\n+ * document, Revision 1.0, December 14, 1998, available at\n+ * <http://www.usb.org/developers/devclass_docs/usbmass-ufi10.pdf>.\n+ */\n+\n+\n+/*\n+ *\t\t\t\tDriver Design\n+ *\n+ * The FSG driver is fairly straightforward.  There is a main kernel\n+ * thread that handles most of the work.  Interrupt routines field\n+ * callbacks from the controller driver: bulk- and interrupt-request\n+ * completion notifications, endpoint-0 events, and disconnect events.\n+ * Completion events are passed to the main thread by wakeup calls.  Many\n+ * ep0 requests are handled at interrupt time, but SetInterface,\n+ * SetConfiguration, and device reset requests are forwarded to the\n+ * thread in the form of \"exceptions\" using SIGUSR1 signals (since they\n+ * should interrupt any ongoing file I/O operations).\n+ *\n+ * The thread's main routine implements the standard command/data/status\n+ * parts of a SCSI interaction.  It and its subroutines are full of tests\n+ * for pending signals/exceptions -- all this polling is necessary since\n+ * the kernel has no setjmp/longjmp equivalents.  (Maybe this is an\n+ * indication that the driver really wants to be running in userspace.)\n+ * An important point is that so long as the thread is alive it keeps an\n+ * open reference to the backing file.  This will prevent unmounting\n+ * the backing file's underlying filesystem and could cause problems\n+ * during system shutdown, for example.  To prevent such problems, the\n+ * thread catches INT, TERM, and KILL signals and converts them into\n+ * an EXIT exception.\n+ *\n+ * In normal operation the main thread is started during the gadget's\n+ * fsg_bind() callback and stopped during fsg_unbind().  But it can also\n+ * exit when it receives a signal, and there's no point leaving the\n+ * gadget running when the thread is dead.  So just before the thread\n+ * exits, it deregisters the gadget driver.  This makes things a little\n+ * tricky: The driver is deregistered at two places, and the exiting\n+ * thread can indirectly call fsg_unbind() which in turn can tell the\n+ * thread to exit.  The first problem is resolved through the use of the\n+ * REGISTERED atomic bitflag; the driver will only be deregistered once.\n+ * The second problem is resolved by having fsg_unbind() check\n+ * fsg->state; it won't try to stop the thread if the state is already\n+ * FSG_STATE_TERMINATED.\n+ *\n+ * To provide maximum throughput, the driver uses a circular pipeline of\n+ * buffer heads (struct fsg_buffhd).  In principle the pipeline can be\n+ * arbitrarily long; in practice the benefits don't justify having more\n+ * than 2 stages (i.e., double buffering).  But it helps to think of the\n+ * pipeline as being a long one.  Each buffer head contains a bulk-in and\n+ * a bulk-out request pointer (since the buffer can be used for both\n+ * output and input -- directions always are given from the host's\n+ * point of view) as well as a pointer to the buffer and various state\n+ * variables.\n+ *\n+ * Use of the pipeline follows a simple protocol.  There is a variable\n+ * (fsg->next_buffhd_to_fill) that points to the next buffer head to use.\n+ * At any time that buffer head may still be in use from an earlier\n+ * request, so each buffer head has a state variable indicating whether\n+ * it is EMPTY, FULL, or BUSY.  Typical use involves waiting for the\n+ * buffer head to be EMPTY, filling the buffer either by file I/O or by\n+ * USB I/O (during which the buffer head is BUSY), and marking the buffer\n+ * head FULL when the I/O is complete.  Then the buffer will be emptied\n+ * (again possibly by USB I/O, during which it is marked BUSY) and\n+ * finally marked EMPTY again (possibly by a completion routine).\n+ *\n+ * A module parameter tells the driver to avoid stalling the bulk\n+ * endpoints wherever the transport specification allows.  This is\n+ * necessary for some UDCs like the SuperH, which cannot reliably clear a\n+ * halt on a bulk endpoint.  However, under certain circumstances the\n+ * Bulk-only specification requires a stall.  In such cases the driver\n+ * will halt the endpoint and set a flag indicating that it should clear\n+ * the halt in software during the next device reset.  Hopefully this\n+ * will permit everything to work correctly.  Furthermore, although the\n+ * specification allows the bulk-out endpoint to halt when the host sends\n+ * too much data, implementing this would cause an unavoidable race.\n+ * The driver will always use the \"no-stall\" approach for OUT transfers.\n+ *\n+ * One subtle point concerns sending status-stage responses for ep0\n+ * requests.  Some of these requests, such as device reset, can involve\n+ * interrupting an ongoing file I/O operation, which might take an\n+ * arbitrarily long time.  During that delay the host might give up on\n+ * the original ep0 request and issue a new one.  When that happens the\n+ * driver should not notify the host about completion of the original\n+ * request, as the host will no longer be waiting for it.  So the driver\n+ * assigns to each ep0 request a unique tag, and it keeps track of the\n+ * tag value of the request associated with a long-running exception\n+ * (device-reset, interface-change, or configuration-change).  When the\n+ * exception handler is finished, the status-stage response is submitted\n+ * only if the current ep0 request tag is equal to the exception request\n+ * tag.  Thus only the most recently received ep0 request will get a\n+ * status-stage response.\n+ *\n+ * Warning: This driver source file is too long.  It ought to be split up\n+ * into a header file plus about 3 separate .c files, to handle the details\n+ * of the Gadget, USB Mass Storage, and SCSI protocols.\n+ */\n+\n+\n+/* #define VERBOSE_DEBUG */\n+/* #define DUMP_MSGS */\n+\n+\n+#include <linux/blkdev.h>\n+#include <linux/completion.h>\n+#include <linux/dcache.h>\n+#include <linux/delay.h>\n+#include <linux/device.h>\n+#include <linux/fcntl.h>\n+#include <linux/file.h>\n+#include <linux/fs.h>\n+#include <linux/kref.h>\n+#include <linux/kthread.h>\n+#include <linux/limits.h>\n+#include <linux/module.h>\n+#include <linux/rwsem.h>\n+#include <linux/slab.h>\n+#include <linux/spinlock.h>\n+#include <linux/string.h>\n+#include <linux/freezer.h>\n+#include <linux/utsname.h>\n+\n+#include <linux/usb/ch9.h>\n+#include <linux/usb/gadget.h>\n+\n+#include \"gadget_chips.h\"\n+\n+\n+\n+/*\n+ * Kbuild is not very cooperative with respect to linking separately\n+ * compiled library objects into one module.  So for now we won't use\n+ * separate compilation ... ensuring init/exit sections work to shrink\n+ * the runtime footprint, and giving us at least some parts of what\n+ * a \"gcc --combine ... part1.c part2.c part3.c ... \" build would.\n+ */\n+#include \"usbstring.c\"\n+#include \"config.c\"\n+#include \"epautoconf.c\"\n+\n+/*-------------------------------------------------------------------------*/\n+\n+#define DRIVER_DESC\t\t\"File-backed Storage Gadget\"\n+#define DRIVER_NAME\t\t\"g_file_storage\"\n+#define DRIVER_VERSION\t\t\"1 September 2010\"\n+\n+static       char fsg_string_manufacturer[64];\n+static const char fsg_string_product[] = DRIVER_DESC;\n+static const char fsg_string_config[] = \"Self-powered\";\n+static const char fsg_string_interface[] = \"Mass Storage\";\n+\n+\n+#include \"storage_common.c\"\n+\n+\n+MODULE_DESCRIPTION(DRIVER_DESC);\n+MODULE_AUTHOR(\"Alan Stern\");\n+MODULE_LICENSE(\"Dual BSD/GPL\");\n+\n+/*\n+ * This driver assumes self-powered hardware and has no way for users to\n+ * trigger remote wakeup.  It uses autoconfiguration to select endpoints\n+ * and endpoint addresses.\n+ */\n+\n+\n+/*-------------------------------------------------------------------------*/\n+\n+\n+/* Encapsulate the module parameter settings */\n+\n+static struct {\n+\tchar\t\t*file[FSG_MAX_LUNS];\n+\tchar\t\t*serial;\n+\tbool\t\tro[FSG_MAX_LUNS];\n+\tbool\t\tnofua[FSG_MAX_LUNS];\n+\tunsigned int\tnum_filenames;\n+\tunsigned int\tnum_ros;\n+\tunsigned int\tnum_nofuas;\n+\tunsigned int\tnluns;\n+\n+\tbool\t\tremovable;\n+\tbool\t\tcan_stall;\n+\tbool\t\tcdrom;\n+\n+\tchar\t\t*transport_parm;\n+\tchar\t\t*protocol_parm;\n+\tunsigned short\tvendor;\n+\tunsigned short\tproduct;\n+\tunsigned short\trelease;\n+\tunsigned int\tbuflen;\n+\n+\tint\t\ttransport_type;\n+\tchar\t\t*transport_name;\n+\tint\t\tprotocol_type;\n+\tchar\t\t*protocol_name;\n+\n+} mod_data = {\t\t\t\t\t// Default values\n+\t.transport_parm\t\t= \"BBB\",\n+\t.protocol_parm\t\t= \"SCSI\",\n+\t.removable\t\t= 0,\n+\t.can_stall\t\t= 1,\n+\t.cdrom\t\t\t= 0,\n+\t.vendor\t\t\t= FSG_VENDOR_ID,\n+\t.product\t\t= FSG_PRODUCT_ID,\n+\t.release\t\t= 0xffff,\t// Use controller chip type\n+\t.buflen\t\t\t= 16384,\n+\t};\n+\n+\n+module_param_array_named(file, mod_data.file, charp, &mod_data.num_filenames,\n+\t\tS_IRUGO);\n+MODULE_PARM_DESC(file, \"names of backing files or devices\");\n+\n+module_param_named(serial, mod_data.serial, charp, S_IRUGO);\n+MODULE_PARM_DESC(serial, \"USB serial number\");\n+\n+module_param_array_named(ro, mod_data.ro, bool, &mod_data.num_ros, S_IRUGO);\n+MODULE_PARM_DESC(ro, \"true to force read-only\");\n+\n+module_param_array_named(nofua, mod_data.nofua, bool, &mod_data.num_nofuas,\n+\t\tS_IRUGO);\n+MODULE_PARM_DESC(nofua, \"true to ignore SCSI WRITE(10,12) FUA bit\");\n+\n+module_param_named(luns, mod_data.nluns, uint, S_IRUGO);\n+MODULE_PARM_DESC(luns, \"number of LUNs\");\n+\n+module_param_named(removable, mod_data.removable, bool, S_IRUGO);\n+MODULE_PARM_DESC(removable, \"true to simulate removable media\");\n+\n+module_param_named(stall, mod_data.can_stall, bool, S_IRUGO);\n+MODULE_PARM_DESC(stall, \"false to prevent bulk stalls\");\n+\n+module_param_named(cdrom, mod_data.cdrom, bool, S_IRUGO);\n+MODULE_PARM_DESC(cdrom, \"true to emulate cdrom instead of disk\");\n+\n+/* In the non-TEST version, only the module parameters listed above\n+ * are available. */\n+#ifdef CONFIG_USB_FILE_STORAGE_TEST\n+\n+module_param_named(transport, mod_data.transport_parm, charp, S_IRUGO);\n+MODULE_PARM_DESC(transport, \"type of transport (BBB, CBI, or CB)\");\n+\n+module_param_named(protocol, mod_data.protocol_parm, charp, S_IRUGO);\n+MODULE_PARM_DESC(protocol, \"type of protocol (RBC, 8020, QIC, UFI, \"\n+\t\t\"8070, or SCSI)\");\n+\n+module_param_named(vendor, mod_data.vendor, ushort, S_IRUGO);\n+MODULE_PARM_DESC(vendor, \"USB Vendor ID\");\n+\n+module_param_named(product, mod_data.product, ushort, S_IRUGO);\n+MODULE_PARM_DESC(product, \"USB Product ID\");\n+\n+module_param_named(release, mod_data.release, ushort, S_IRUGO);\n+MODULE_PARM_DESC(release, \"USB release number\");\n+\n+module_param_named(buflen, mod_data.buflen, uint, S_IRUGO);\n+MODULE_PARM_DESC(buflen, \"I/O buffer size\");\n+\n+#endif /* CONFIG_USB_FILE_STORAGE_TEST */\n+\n+\n+/*\n+ * These definitions will permit the compiler to avoid generating code for\n+ * parts of the driver that aren't used in the non-TEST version.  Even gcc\n+ * can recognize when a test of a constant expression yields a dead code\n+ * path.\n+ */\n+\n+#ifdef CONFIG_USB_FILE_STORAGE_TEST\n+\n+#define transport_is_bbb()\t(mod_data.transport_type == USB_PR_BULK)\n+#define transport_is_cbi()\t(mod_data.transport_type == USB_PR_CBI)\n+#define protocol_is_scsi()\t(mod_data.protocol_type == USB_SC_SCSI)\n+\n+#else\n+\n+#define transport_is_bbb()\t1\n+#define transport_is_cbi()\t0\n+#define protocol_is_scsi()\t1\n+\n+#endif /* CONFIG_USB_FILE_STORAGE_TEST */\n+\n+\n+/*-------------------------------------------------------------------------*/\n+\n+\n+struct fsg_dev {\n+\t/* lock protects: state, all the req_busy's, and cbbuf_cmnd */\n+\tspinlock_t\t\tlock;\n+\tstruct usb_gadget\t*gadget;\n+\n+\t/* filesem protects: backing files in use */\n+\tstruct rw_semaphore\tfilesem;\n+\n+\t/* reference counting: wait until all LUNs are released */\n+\tstruct kref\t\tref;\n+\n+\tstruct usb_ep\t\t*ep0;\t\t// Handy copy of gadget->ep0\n+\tstruct usb_request\t*ep0req;\t// For control responses\n+\tunsigned int\t\tep0_req_tag;\n+\tconst char\t\t*ep0req_name;\n+\n+\tstruct usb_request\t*intreq;\t// For interrupt responses\n+\tint\t\t\tintreq_busy;\n+\tstruct fsg_buffhd\t*intr_buffhd;\n+\n+\tunsigned int\t\tbulk_out_maxpacket;\n+\tenum fsg_state\t\tstate;\t\t// For exception handling\n+\tunsigned int\t\texception_req_tag;\n+\n+\tu8\t\t\tconfig, new_config;\n+\n+\tunsigned int\t\trunning : 1;\n+\tunsigned int\t\tbulk_in_enabled : 1;\n+\tunsigned int\t\tbulk_out_enabled : 1;\n+\tunsigned int\t\tintr_in_enabled : 1;\n+\tunsigned int\t\tphase_error : 1;\n+\tunsigned int\t\tshort_packet_received : 1;\n+\tunsigned int\t\tbad_lun_okay : 1;\n+\n+\tunsigned long\t\tatomic_bitflags;\n+#define REGISTERED\t\t0\n+#define IGNORE_BULK_OUT\t\t1\n+#define SUSPENDED\t\t2\n+\n+\tstruct usb_ep\t\t*bulk_in;\n+\tstruct usb_ep\t\t*bulk_out;\n+\tstruct usb_ep\t\t*intr_in;\n+\n+\tstruct fsg_buffhd\t*next_buffhd_to_fill;\n+\tstruct fsg_buffhd\t*next_buffhd_to_drain;\n+\n+\tint\t\t\tthread_wakeup_needed;\n+\tstruct completion\tthread_notifier;\n+\tstruct task_struct\t*thread_task;\n+\n+\tint\t\t\tcmnd_size;\n+\tu8\t\t\tcmnd[MAX_COMMAND_SIZE];\n+\tenum data_direction\tdata_dir;\n+\tu32\t\t\tdata_size;\n+\tu32\t\t\tdata_size_from_cmnd;\n+\tu32\t\t\ttag;\n+\tunsigned int\t\tlun;\n+\tu32\t\t\tresidue;\n+\tu32\t\t\tusb_amount_left;\n+\n+\t/* The CB protocol offers no way for a host to know when a command\n+\t * has completed.  As a result the next command may arrive early,\n+\t * and we will still have to handle it.  For that reason we need\n+\t * a buffer to store new commands when using CB (or CBI, which\n+\t * does not oblige a host to wait for command completion either). */\n+\tint\t\t\tcbbuf_cmnd_size;\n+\tu8\t\t\tcbbuf_cmnd[MAX_COMMAND_SIZE];\n+\n+\tunsigned int\t\tnluns;\n+\tstruct fsg_lun\t\t*luns;\n+\tstruct fsg_lun\t\t*curlun;\n+\t/* Must be the last entry */\n+\tstruct fsg_buffhd\tbuffhds[];\n+};\n+\n+typedef void (*fsg_routine_t)(struct fsg_dev *);\n+\n+static int exception_in_progress(struct fsg_dev *fsg)\n+{\n+\treturn (fsg->state > FSG_STATE_IDLE);\n+}\n+\n+/* Make bulk-out requests be divisible by the maxpacket size */\n+static void set_bulk_out_req_length(struct fsg_dev *fsg,\n+\t\tstruct fsg_buffhd *bh, unsigned int length)\n+{\n+\tunsigned int\trem;\n+\n+\tbh->bulk_out_intended_length = length;\n+\trem = length % fsg->bulk_out_maxpacket;\n+\tif (rem > 0)\n+\t\tlength += fsg->bulk_out_maxpacket - rem;\n+\tbh->outreq->length = length;\n+}\n+\n+static struct fsg_dev\t\t\t*the_fsg;\n+static struct usb_gadget_driver\t\tfsg_driver;\n+\n+\n+/*-------------------------------------------------------------------------*/\n+\n+static int fsg_set_halt(struct fsg_dev *fsg, struct usb_ep *ep)\n+{\n+\tconst char\t*name;\n+\n+\tif (ep == fsg->bulk_in)\n+\t\tname = \"bulk-in\";\n+\telse if (ep == fsg->bulk_out)\n+\t\tname = \"bulk-out\";\n+\telse\n+\t\tname = ep->name;\n+\tDBG(fsg, \"%s set halt\\n\", name);\n+\treturn usb_ep_set_halt(ep);\n+}\n+\n+\n+/*-------------------------------------------------------------------------*/\n+\n+/*\n+ * DESCRIPTORS ... most are static, but strings and (full) configuration\n+ * descriptors are built on demand.  Also the (static) config and interface\n+ * descriptors are adjusted during fsg_bind().\n+ */\n+\n+/* There is only one configuration. */\n+#define\tCONFIG_VALUE\t\t1\n+\n+static struct usb_device_descriptor\n+device_desc = {\n+\t.bLength =\t\tsizeof device_desc,\n+\t.bDescriptorType =\tUSB_DT_DEVICE,\n+\n+\t.bcdUSB =\t\tcpu_to_le16(0x0200),\n+\t.bDeviceClass =\t\tUSB_CLASS_PER_INTERFACE,\n+\n+\t/* The next three values can be overridden by module parameters */\n+\t.idVendor =\t\tcpu_to_le16(FSG_VENDOR_ID),\n+\t.idProduct =\t\tcpu_to_le16(FSG_PRODUCT_ID),\n+\t.bcdDevice =\t\tcpu_to_le16(0xffff),\n+\n+\t.iManufacturer =\tFSG_STRING_MANUFACTURER,\n+\t.iProduct =\t\tFSG_STRING_PRODUCT,\n+\t.iSerialNumber =\tFSG_STRING_SERIAL,\n+\t.bNumConfigurations =\t1,\n+};\n+\n+static struct usb_config_descriptor\n+config_desc = {\n+\t.bLength =\t\tsizeof config_desc,\n+\t.bDescriptorType =\tUSB_DT_CONFIG,\n+\n+\t/* wTotalLength computed by usb_gadget_config_buf() */\n+\t.bNumInterfaces =\t1,\n+\t.bConfigurationValue =\tCONFIG_VALUE,\n+\t.iConfiguration =\tFSG_STRING_CONFIG,\n+\t.bmAttributes =\t\tUSB_CONFIG_ATT_ONE | USB_CONFIG_ATT_SELFPOWER,\n+\t.bMaxPower =\t\tCONFIG_USB_GADGET_VBUS_DRAW / 2,\n+};\n+\n+\n+static struct usb_qualifier_descriptor\n+dev_qualifier = {\n+\t.bLength =\t\tsizeof dev_qualifier,\n+\t.bDescriptorType =\tUSB_DT_DEVICE_QUALIFIER,\n+\n+\t.bcdUSB =\t\tcpu_to_le16(0x0200),\n+\t.bDeviceClass =\t\tUSB_CLASS_PER_INTERFACE,\n+\n+\t.bNumConfigurations =\t1,\n+};\n+\n+static int populate_bos(struct fsg_dev *fsg, u8 *buf)\n+{\n+\tmemcpy(buf, &fsg_bos_desc, USB_DT_BOS_SIZE);\n+\tbuf += USB_DT_BOS_SIZE;\n+\n+\tmemcpy(buf, &fsg_ext_cap_desc, USB_DT_USB_EXT_CAP_SIZE);\n+\tbuf += USB_DT_USB_EXT_CAP_SIZE;\n+\n+\tmemcpy(buf, &fsg_ss_cap_desc, USB_DT_USB_SS_CAP_SIZE);\n+\n+\treturn USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE\n+\t\t+ USB_DT_USB_EXT_CAP_SIZE;\n+}\n+\n+/*\n+ * Config descriptors must agree with the code that sets configurations\n+ * and with code managing interfaces and their altsettings.  They must\n+ * also handle different speeds and other-speed requests.\n+ */\n+static int populate_config_buf(struct usb_gadget *gadget,\n+\t\tu8 *buf, u8 type, unsigned index)\n+{\n+\tenum usb_device_speed\t\t\tspeed = gadget->speed;\n+\tint\t\t\t\t\tlen;\n+\tconst struct usb_descriptor_header\t**function;\n+\n+\tif (index > 0)\n+\t\treturn -EINVAL;\n+\n+\tif (gadget_is_dualspeed(gadget) && type == USB_DT_OTHER_SPEED_CONFIG)\n+\t\tspeed = (USB_SPEED_FULL + USB_SPEED_HIGH) - speed;\n+\tfunction = gadget_is_dualspeed(gadget) && speed == USB_SPEED_HIGH\n+\t\t? (const struct usb_descriptor_header **)fsg_hs_function\n+\t\t: (const struct usb_descriptor_header **)fsg_fs_function;\n+\n+\t/* for now, don't advertise srp-only devices */\n+\tif (!gadget_is_otg(gadget))\n+\t\tfunction++;\n+\n+\tlen = usb_gadget_config_buf(&config_desc, buf, EP0_BUFSIZE, function);\n+\t((struct usb_config_descriptor *) buf)->bDescriptorType = type;\n+\treturn len;\n+}\n+\n+\n+/*-------------------------------------------------------------------------*/\n+\n+/* These routines may be called in process context or in_irq */\n+\n+/* Caller must hold fsg->lock */\n+static void wakeup_thread(struct fsg_dev *fsg)\n+{\n+\t/* Tell the main thread that something has happened */\n+\tfsg->thread_wakeup_needed = 1;\n+\tif (fsg->thread_task)\n+\t\twake_up_process(fsg->thread_task);\n+}\n+\n+\n+static void raise_exception(struct fsg_dev *fsg, enum fsg_state new_state)\n+{\n+\tunsigned long\t\tflags;\n+\n+\t/* Do nothing if a higher-priority exception is already in progress.\n+\t * If a lower-or-equal priority exception is in progress, preempt it\n+\t * and notify the main thread by sending it a signal. */\n+\tspin_lock_irqsave(&fsg->lock, flags);\n+\tif (fsg->state <= new_state) {\n+\t\tfsg->exception_req_tag = fsg->ep0_req_tag;\n+\t\tfsg->state = new_state;\n+\t\tif (fsg->thread_task)\n+\t\t\tsend_sig_info(SIGUSR1, SEND_SIG_FORCED,\n+\t\t\t\t\tfsg->thread_task);\n+\t}\n+\tspin_unlock_irqrestore(&fsg->lock, flags);\n+}\n+\n+\n+/*-------------------------------------------------------------------------*/\n+\n+/* The disconnect callback and ep0 routines.  These always run in_irq,\n+ * except that ep0_queue() is called in the main thread to acknowledge\n+ * completion of various requests: set config, set interface, and\n+ * Bulk-only device reset. */\n+\n+static void fsg_disconnect(struct usb_gadget *gadget)\n+{\n+\tstruct fsg_dev\t\t*fsg = get_gadget_data(gadget);\n+\n+\tDBG(fsg, \"disconnect or port reset\\n\");\n+\traise_exception(fsg, FSG_STATE_DISCONNECT);\n+}\n+\n+\n+static int ep0_queue(struct fsg_dev *fsg)\n+{\n+\tint\trc;\n+\n+\trc = usb_ep_queue(fsg->ep0, fsg->ep0req, GFP_ATOMIC);\n+\tif (rc != 0 && rc != -ESHUTDOWN) {\n+\n+\t\t/* We can't do much more than wait for a reset */\n+\t\tWARNING(fsg, \"error in submission: %s --> %d\\n\",\n+\t\t\t\tfsg->ep0->name, rc);\n+\t}\n+\treturn rc;\n+}\n+\n+static void ep0_complete(struct usb_ep *ep, struct usb_request *req)\n+{\n+\tstruct fsg_dev\t\t*fsg = ep->driver_data;\n+\n+\tif (req->actual > 0)\n+\t\tdump_msg(fsg, fsg->ep0req_name, req->buf, req->actual);\n+\tif (req->status || req->actual != req->length)\n+\t\tDBG(fsg, \"%s --> %d, %u/%u\\n\", __func__,\n+\t\t\t\treq->status, req->actual, req->length);\n+\tif (req->status == -ECONNRESET)\t\t// Request was cancelled\n+\t\tusb_ep_fifo_flush(ep);\n+\n+\tif (req->status == 0 && req->context)\n+\t\t((fsg_routine_t) (req->context))(fsg);\n+}\n+\n+\n+/*-------------------------------------------------------------------------*/\n+\n+/* Bulk and interrupt endpoint completion handlers.\n+ * These always run in_irq. */\n+\n+static void bulk_in_complete(struct usb_ep *ep, struct usb_request *req)\n+{\n+\tstruct fsg_dev\t\t*fsg = ep->driver_data;\n+\tstruct fsg_buffhd\t*bh = req->context;\n+\n+\tif (req->status || req->actual != req->length)\n+\t\tDBG(fsg, \"%s --> %d, %u/%u\\n\", __func__,\n+\t\t\t\treq->status, req->actual, req->length);\n+\tif (req->status == -ECONNRESET)\t\t// Request was cancelled\n+\t\tusb_ep_fifo_flush(ep);\n+\n+\t/* Hold the lock while we update the request and buffer states */\n+\tsmp_wmb();\n+\tspin_lock(&fsg->lock);\n+\tbh->inreq_busy = 0;\n+\tbh->state = BUF_STATE_EMPTY;\n+\twakeup_thread(fsg);\n+\tspin_unlock(&fsg->lock);\n+}\n+\n+static void bulk_out_complete(struct usb_ep *ep, struct usb_request *req)\n+{\n+\tstruct fsg_dev\t\t*fsg = ep->driver_data;\n+\tstruct fsg_buffhd\t*bh = req->context;\n+\n+\tdump_msg(fsg, \"bulk-out\", req->buf, req->actual);\n+\tif (req->status || req->actual != bh->bulk_out_intended_length)\n+\t\tDBG(fsg, \"%s --> %d, %u/%u\\n\", __func__,\n+\t\t\t\treq->status, req->actual,\n+\t\t\t\tbh->bulk_out_intended_length);\n+\tif (req->status == -ECONNRESET)\t\t// Request was cancelled\n+\t\tusb_ep_fifo_flush(ep);\n+\n+\t/* Hold the lock while we update the request and buffer states */\n+\tsmp_wmb();\n+\tspin_lock(&fsg->lock);\n+\tbh->outreq_busy = 0;\n+\tbh->state = BUF_STATE_FULL;\n+\twakeup_thread(fsg);\n+\tspin_unlock(&fsg->lock);\n+}\n+\n+\n+#ifdef CONFIG_USB_FILE_STORAGE_TEST\n+static void intr_in_complete(struct usb_ep *ep, struct usb_request *req)\n+{\n+\tstruct fsg_dev\t\t*fsg = ep->driver_data;\n+\tstruct fsg_buffhd\t*bh = req->context;\n+\n+\tif (req->status || req->actual != req->length)\n+\t\tDBG(fsg, \"%s --> %d, %u/%u\\n\", __func__,\n+\t\t\t\treq->status, req->actual, req->length);\n+\tif (req->status == -ECONNRESET)\t\t// Request was cancelled\n+\t\tusb_ep_fifo_flush(ep);\n+\n+\t/* Hold the lock while we update the request and buffer states */\n+\tsmp_wmb();\n+\tspin_lock(&fsg->lock);\n+\tfsg->intreq_busy = 0;\n+\tbh->state = BUF_STATE_EMPTY;\n+\twakeup_thread(fsg);\n+\tspin_unlock(&fsg->lock);\n+}\n+\n+#else\n+static void intr_in_complete(struct usb_ep *ep, struct usb_request *req)\n+{}\n+#endif /* CONFIG_USB_FILE_STORAGE_TEST */\n+\n+\n+/*-------------------------------------------------------------------------*/\n+\n+/* Ep0 class-specific handlers.  These always run in_irq. */\n+\n+#ifdef CONFIG_USB_FILE_STORAGE_TEST\n+static void received_cbi_adsc(struct fsg_dev *fsg, struct fsg_buffhd *bh)\n+{\n+\tstruct usb_request\t*req = fsg->ep0req;\n+\tstatic u8\t\tcbi_reset_cmnd[6] = {\n+\t\t\tSEND_DIAGNOSTIC, 4, 0xff, 0xff, 0xff, 0xff};\n+\n+\t/* Error in command transfer? */\n+\tif (req->status || req->length != req->actual ||\n+\t\t\treq->actual < 6 || req->actual > MAX_COMMAND_SIZE) {\n+\n+\t\t/* Not all controllers allow a protocol stall after\n+\t\t * receiving control-out data, but we'll try anyway. */\n+\t\tfsg_set_halt(fsg, fsg->ep0);\n+\t\treturn;\t\t\t// Wait for reset\n+\t}\n+\n+\t/* Is it the special reset command? */\n+\tif (req->actual >= sizeof cbi_reset_cmnd &&\n+\t\t\tmemcmp(req->buf, cbi_reset_cmnd,\n+\t\t\t\tsizeof cbi_reset_cmnd) == 0) {\n+\n+\t\t/* Raise an exception to stop the current operation\n+\t\t * and reinitialize our state. */\n+\t\tDBG(fsg, \"cbi reset request\\n\");\n+\t\traise_exception(fsg, FSG_STATE_RESET);\n+\t\treturn;\n+\t}\n+\n+\tVDBG(fsg, \"CB[I] accept device-specific command\\n\");\n+\tspin_lock(&fsg->lock);\n+\n+\t/* Save the command for later */\n+\tif (fsg->cbbuf_cmnd_size)\n+\t\tWARNING(fsg, \"CB[I] overwriting previous command\\n\");\n+\tfsg->cbbuf_cmnd_size = req->actual;\n+\tmemcpy(fsg->cbbuf_cmnd, req->buf, fsg->cbbuf_cmnd_size);\n+\n+\twakeup_thread(fsg);\n+\tspin_unlock(&fsg->lock);\n+}\n+\n+#else\n+static void received_cbi_adsc(struct fsg_dev *fsg, struct fsg_buffhd *bh)\n+{}\n+#endif /* CONFIG_USB_FILE_STORAGE_TEST */\n+\n+\n+static int class_setup_req(struct fsg_dev *fsg,\n+\t\tconst struct usb_ctrlrequest *ctrl)\n+{\n+\tstruct usb_request\t*req = fsg->ep0req;\n+\tint\t\t\tvalue = -EOPNOTSUPP;\n+\tu16\t\t\tw_index = le16_to_cpu(ctrl->wIndex);\n+\tu16                     w_value = le16_to_cpu(ctrl->wValue);\n+\tu16\t\t\tw_length = le16_to_cpu(ctrl->wLength);\n+\n+\tif (!fsg->config)\n+\t\treturn value;\n+\n+\t/* Handle Bulk-only class-specific requests */\n+\tif (transport_is_bbb()) {\n+\t\tswitch (ctrl->bRequest) {\n+\n+\t\tcase US_BULK_RESET_REQUEST:\n+\t\t\tif (ctrl->bRequestType != (USB_DIR_OUT |\n+\t\t\t\t\tUSB_TYPE_CLASS | USB_RECIP_INTERFACE))\n+\t\t\t\tbreak;\n+\t\t\tif (w_index != 0 || w_value != 0 || w_length != 0) {\n+\t\t\t\tvalue = -EDOM;\n+\t\t\t\tbreak;\n+\t\t\t}\n+\n+\t\t\t/* Raise an exception to stop the current operation\n+\t\t\t * and reinitialize our state. */\n+\t\t\tDBG(fsg, \"bulk reset request\\n\");\n+\t\t\traise_exception(fsg, FSG_STATE_RESET);\n+\t\t\tvalue = DELAYED_STATUS;\n+\t\t\tbreak;\n+\n+\t\tcase US_BULK_GET_MAX_LUN:\n+\t\t\tif (ctrl->bRequestType != (USB_DIR_IN |\n+\t\t\t\t\tUSB_TYPE_CLASS | USB_RECIP_INTERFACE))\n+\t\t\t\tbreak;\n+\t\t\tif (w_index != 0 || w_value != 0 || w_length != 1) {\n+\t\t\t\tvalue = -EDOM;\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t\tVDBG(fsg, \"get max LUN\\n\");\n+\t\t\t*(u8 *) req->buf = fsg->nluns - 1;\n+\t\t\tvalue = 1;\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\n+\t/* Handle CBI class-specific requests */\n+\telse {\n+\t\tswitch (ctrl->bRequest) {\n+\n+\t\tcase USB_CBI_ADSC_REQUEST:\n+\t\t\tif (ctrl->bRequestType != (USB_DIR_OUT |\n+\t\t\t\t\tUSB_TYPE_CLASS | USB_RECIP_INTERFACE))\n+\t\t\t\tbreak;\n+\t\t\tif (w_index != 0 || w_value != 0) {\n+\t\t\t\tvalue = -EDOM;\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t\tif (w_length > MAX_COMMAND_SIZE) {\n+\t\t\t\tvalue = -EOVERFLOW;\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t\tvalue = w_length;\n+\t\t\tfsg->ep0req->context = received_cbi_adsc;\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\n+\tif (value == -EOPNOTSUPP)\n+\t\tVDBG(fsg,\n+\t\t\t\"unknown class-specific control req \"\n+\t\t\t\"%02x.%02x v%04x i%04x l%u\\n\",\n+\t\t\tctrl->bRequestType, ctrl->bRequest,\n+\t\t\tle16_to_cpu(ctrl->wValue), w_index, w_length);\n+\treturn value;\n+}\n+\n+\n+/*-------------------------------------------------------------------------*/\n+\n+/* Ep0 standard request handlers.  These always run in_irq. */\n+\n+static int standard_setup_req(struct fsg_dev *fsg,\n+\t\tconst struct usb_ctrlrequest *ctrl)\n+{\n+\tstruct usb_request\t*req = fsg->ep0req;\n+\tint\t\t\tvalue = -EOPNOTSUPP;\n+\tu16\t\t\tw_index = le16_to_cpu(ctrl->wIndex);\n+\tu16\t\t\tw_value = le16_to_cpu(ctrl->wValue);\n+\n+\t/* Usually this just stores reply data in the pre-allocated ep0 buffer,\n+\t * but config change events will also reconfigure hardware. */\n+\tswitch (ctrl->bRequest) {\n+\n+\tcase USB_REQ_GET_DESCRIPTOR:\n+\t\tif (ctrl->bRequestType != (USB_DIR_IN | USB_TYPE_STANDARD |\n+\t\t\t\tUSB_RECIP_DEVICE))\n+\t\t\tbreak;\n+\t\tswitch (w_value >> 8) {\n+\n+\t\tcase USB_DT_DEVICE:\n+\t\t\tVDBG(fsg, \"get device descriptor\\n\");\n+\t\t\tdevice_desc.bMaxPacketSize0 = fsg->ep0->maxpacket;\n+\t\t\tvalue = sizeof device_desc;\n+\t\t\tmemcpy(req->buf, &device_desc, value);\n+\t\t\tbreak;\n+\t\tcase USB_DT_DEVICE_QUALIFIER:\n+\t\t\tVDBG(fsg, \"get device qualifier\\n\");\n+\t\t\tif (!gadget_is_dualspeed(fsg->gadget) ||\n+\t\t\t\t\tfsg->gadget->speed == USB_SPEED_SUPER)\n+\t\t\t\tbreak;\n+\t\t\t/*\n+\t\t\t * Assume ep0 uses the same maxpacket value for both\n+\t\t\t * speeds\n+\t\t\t */\n+\t\t\tdev_qualifier.bMaxPacketSize0 = fsg->ep0->maxpacket;\n+\t\t\tvalue = sizeof dev_qualifier;\n+\t\t\tmemcpy(req->buf, &dev_qualifier, value);\n+\t\t\tbreak;\n+\n+\t\tcase USB_DT_OTHER_SPEED_CONFIG:\n+\t\t\tVDBG(fsg, \"get other-speed config descriptor\\n\");\n+\t\t\tif (!gadget_is_dualspeed(fsg->gadget) ||\n+\t\t\t\t\tfsg->gadget->speed == USB_SPEED_SUPER)\n+\t\t\t\tbreak;\n+\t\t\tgoto get_config;\n+\t\tcase USB_DT_CONFIG:\n+\t\t\tVDBG(fsg, \"get configuration descriptor\\n\");\n+get_config:\n+\t\t\tvalue = populate_config_buf(fsg->gadget,\n+\t\t\t\t\treq->buf,\n+\t\t\t\t\tw_value >> 8,\n+\t\t\t\t\tw_value & 0xff);\n+\t\t\tbreak;\n+\n+\t\tcase USB_DT_STRING:\n+\t\t\tVDBG(fsg, \"get string descriptor\\n\");\n+\n+\t\t\t/* wIndex == language code */\n+\t\t\tvalue = usb_gadget_get_string(&fsg_stringtab,\n+\t\t\t\t\tw_value & 0xff, req->buf);\n+\t\t\tbreak;\n+\n+\t\tcase USB_DT_BOS:\n+\t\t\tVDBG(fsg, \"get bos descriptor\\n\");\n+\n+\t\t\tif (gadget_is_superspeed(fsg->gadget))\n+\t\t\t\tvalue = populate_bos(fsg, req->buf);\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\tbreak;\n+\n+\t/* One config, two speeds */\n+\tcase USB_REQ_SET_CONFIGURATION:\n+\t\tif (ctrl->bRequestType != (USB_DIR_OUT | USB_TYPE_STANDARD |\n+\t\t\t\tUSB_RECIP_DEVICE))\n+\t\t\tbreak;\n+\t\tVDBG(fsg, \"set configuration\\n\");\n+\t\tif (w_value == CONFIG_VALUE || w_value == 0) {\n+\t\t\tfsg->new_config = w_value;\n+\n+\t\t\t/* Raise an exception to wipe out previous transaction\n+\t\t\t * state (queued bufs, etc) and set the new config. */\n+\t\t\traise_exception(fsg, FSG_STATE_CONFIG_CHANGE);\n+\t\t\tvalue = DELAYED_STATUS;\n+\t\t}\n+\t\tbreak;\n+\tcase USB_REQ_GET_CONFIGURATION:\n+\t\tif (ctrl->bRequestType != (USB_DIR_IN | USB_TYPE_STANDARD |\n+\t\t\t\tUSB_RECIP_DEVICE))\n+\t\t\tbreak;\n+\t\tVDBG(fsg, \"get configuration\\n\");\n+\t\t*(u8 *) req->buf = fsg->config;\n+\t\tvalue = 1;\n+\t\tbreak;\n+\n+\tcase USB_REQ_SET_INTERFACE:\n+\t\tif (ctrl->bRequestType != (USB_DIR_OUT| USB_TYPE_STANDARD |\n+\t\t\t\tUSB_RECIP_INTERFACE))\n+\t\t\tbreak;\n+\t\tif (fsg->config && w_index == 0) {\n+\n+\t\t\t/* Raise an exception to wipe out previous transaction\n+\t\t\t * state (queued bufs, etc) and install the new\n+\t\t\t * interface altsetting. */\n+\t\t\traise_exception(fsg, FSG_STATE_INTERFACE_CHANGE);\n+\t\t\tvalue = DELAYED_STATUS;\n+\t\t}\n+\t\tbreak;\n+\tcase USB_REQ_GET_INTERFACE:\n+\t\tif (ctrl->bRequestType != (USB_DIR_IN | USB_TYPE_STANDARD |\n+\t\t\t\tUSB_RECIP_INTERFACE))\n+\t\t\tbreak;\n+\t\tif (!fsg->config)\n+\t\t\tbreak;\n+\t\tif (w_index != 0) {\n+\t\t\tvalue = -EDOM;\n+\t\t\tbreak;\n+\t\t}\n+\t\tVDBG(fsg, \"get interface\\n\");\n+\t\t*(u8 *) req->buf = 0;\n+\t\tvalue = 1;\n+\t\tbreak;\n+\n+\tdefault:\n+\t\tVDBG(fsg,\n+\t\t\t\"unknown control req %02x.%02x v%04x i%04x l%u\\n\",\n+\t\t\tctrl->bRequestType, ctrl->bRequest,\n+\t\t\tw_value, w_index, le16_to_cpu(ctrl->wLength));\n+\t}\n+\n+\treturn value;\n+}\n+\n+\n+static int fsg_setup(struct usb_gadget *gadget,\n+\t\tconst struct usb_ctrlrequest *ctrl)\n+{\n+\tstruct fsg_dev\t\t*fsg = get_gadget_data(gadget);\n+\tint\t\t\trc;\n+\tint\t\t\tw_length = le16_to_cpu(ctrl->wLength);\n+\n+\t++fsg->ep0_req_tag;\t\t// Record arrival of a new request\n+\tfsg->ep0req->context = NULL;\n+\tfsg->ep0req->length = 0;\n+\tdump_msg(fsg, \"ep0-setup\", (u8 *) ctrl, sizeof(*ctrl));\n+\n+\tif ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_CLASS)\n+\t\trc = class_setup_req(fsg, ctrl);\n+\telse\n+\t\trc = standard_setup_req(fsg, ctrl);\n+\n+\t/* Respond with data/status or defer until later? */\n+\tif (rc >= 0 && rc != DELAYED_STATUS) {\n+\t\trc = min(rc, w_length);\n+\t\tfsg->ep0req->length = rc;\n+\t\tfsg->ep0req->zero = rc < w_length;\n+\t\tfsg->ep0req_name = (ctrl->bRequestType & USB_DIR_IN ?\n+\t\t\t\t\"ep0-in\" : \"ep0-out\");\n+\t\trc = ep0_queue(fsg);\n+\t}\n+\n+\t/* Device either stalls (rc < 0) or reports success */\n+\treturn rc;\n+}\n+\n+\n+/*-------------------------------------------------------------------------*/\n+\n+/* All the following routines run in process context */\n+\n+\n+/* Use this for bulk or interrupt transfers, not ep0 */\n+static void start_transfer(struct fsg_dev *fsg, struct usb_ep *ep,\n+\t\tstruct usb_request *req, int *pbusy,\n+\t\tenum fsg_buffer_state *state)\n+{\n+\tint\trc;\n+\n+\tif (ep == fsg->bulk_in)\n+\t\tdump_msg(fsg, \"bulk-in\", req->buf, req->length);\n+\telse if (ep == fsg->intr_in)\n+\t\tdump_msg(fsg, \"intr-in\", req->buf, req->length);\n+\n+\tspin_lock_irq(&fsg->lock);\n+\t*pbusy = 1;\n+\t*state = BUF_STATE_BUSY;\n+\tspin_unlock_irq(&fsg->lock);\n+\trc = usb_ep_queue(ep, req, GFP_KERNEL);\n+\tif (rc != 0) {\n+\t\t*pbusy = 0;\n+\t\t*state = BUF_STATE_EMPTY;\n+\n+\t\t/* We can't do much more than wait for a reset */\n+\n+\t\t/* Note: currently the net2280 driver fails zero-length\n+\t\t * submissions if DMA is enabled. */\n+\t\tif (rc != -ESHUTDOWN && !(rc == -EOPNOTSUPP &&\n+\t\t\t\t\t\treq->length == 0))\n+\t\t\tWARNING(fsg, \"error in submission: %s --> %d\\n\",\n+\t\t\t\t\tep->name, rc);\n+\t}\n+}\n+\n+\n+static int sleep_thread(struct fsg_dev *fsg)\n+{\n+\tint\trc = 0;\n+\n+\t/* Wait until a signal arrives or we are woken up */\n+\tfor (;;) {\n+\t\ttry_to_freeze();\n+\t\tset_current_state(TASK_INTERRUPTIBLE);\n+\t\tif (signal_pending(current)) {\n+\t\t\trc = -EINTR;\n+\t\t\tbreak;\n+\t\t}\n+\t\tif (fsg->thread_wakeup_needed)\n+\t\t\tbreak;\n+\t\tschedule();\n+\t}\n+\t__set_current_state(TASK_RUNNING);\n+\tfsg->thread_wakeup_needed = 0;\n+\treturn rc;\n+}\n+\n+\n+/*-------------------------------------------------------------------------*/\n+\n+static int do_read(struct fsg_dev *fsg)\n+{\n+\tstruct fsg_lun\t\t*curlun = fsg->curlun;\n+\tu32\t\t\tlba;\n+\tstruct fsg_buffhd\t*bh;\n+\tint\t\t\trc;\n+\tu32\t\t\tamount_left;\n+\tloff_t\t\t\tfile_offset, file_offset_tmp;\n+\tunsigned int\t\tamount;\n+\tssize_t\t\t\tnread;\n+\n+\t/* Get the starting Logical Block Address and check that it's\n+\t * not too big */\n+\tif (fsg->cmnd[0] == READ_6)\n+\t\tlba = get_unaligned_be24(&fsg->cmnd[1]);\n+\telse {\n+\t\tlba = get_unaligned_be32(&fsg->cmnd[2]);\n+\n+\t\t/* We allow DPO (Disable Page Out = don't save data in the\n+\t\t * cache) and FUA (Force Unit Access = don't read from the\n+\t\t * cache), but we don't implement them. */\n+\t\tif ((fsg->cmnd[1] & ~0x18) != 0) {\n+\t\t\tcurlun->sense_data = SS_INVALID_FIELD_IN_CDB;\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t}\n+\tif (lba >= curlun->num_sectors) {\n+\t\tcurlun->sense_data = SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE;\n+\t\treturn -EINVAL;\n+\t}\n+\tfile_offset = ((loff_t) lba) << curlun->blkbits;\n+\n+\t/* Carry out the file reads */\n+\tamount_left = fsg->data_size_from_cmnd;\n+\tif (unlikely(amount_left == 0))\n+\t\treturn -EIO;\t\t// No default reply\n+\n+\tfor (;;) {\n+\n+\t\t/* Figure out how much we need to read:\n+\t\t * Try to read the remaining amount.\n+\t\t * But don't read more than the buffer size.\n+\t\t * And don't try to read past the end of the file.\n+\t\t */\n+\t\tamount = min((unsigned int) amount_left, mod_data.buflen);\n+\t\tamount = min((loff_t) amount,\n+\t\t\t\tcurlun->file_length - file_offset);\n+\n+\t\t/* Wait for the next buffer to become available */\n+\t\tbh = fsg->next_buffhd_to_fill;\n+\t\twhile (bh->state != BUF_STATE_EMPTY) {\n+\t\t\trc = sleep_thread(fsg);\n+\t\t\tif (rc)\n+\t\t\t\treturn rc;\n+\t\t}\n+\n+\t\t/* If we were asked to read past the end of file,\n+\t\t * end with an empty buffer. */\n+\t\tif (amount == 0) {\n+\t\t\tcurlun->sense_data =\n+\t\t\t\t\tSS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE;\n+\t\t\tcurlun->sense_data_info = file_offset >> curlun->blkbits;\n+\t\t\tcurlun->info_valid = 1;\n+\t\t\tbh->inreq->length = 0;\n+\t\t\tbh->state = BUF_STATE_FULL;\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\t/* Perform the read */\n+\t\tfile_offset_tmp = file_offset;\n+\t\tnread = vfs_read(curlun->filp,\n+\t\t\t\t(char __user *) bh->buf,\n+\t\t\t\tamount, &file_offset_tmp);\n+\t\tVLDBG(curlun, \"file read %u @ %llu -> %d\\n\", amount,\n+\t\t\t\t(unsigned long long) file_offset,\n+\t\t\t\t(int) nread);\n+\t\tif (signal_pending(current))\n+\t\t\treturn -EINTR;\n+\n+\t\tif (nread < 0) {\n+\t\t\tLDBG(curlun, \"error in file read: %d\\n\",\n+\t\t\t\t\t(int) nread);\n+\t\t\tnread = 0;\n+\t\t} else if (nread < amount) {\n+\t\t\tLDBG(curlun, \"partial file read: %d/%u\\n\",\n+\t\t\t\t\t(int) nread, amount);\n+\t\t\tnread = round_down(nread, curlun->blksize);\n+\t\t}\n+\t\tfile_offset  += nread;\n+\t\tamount_left  -= nread;\n+\t\tfsg->residue -= nread;\n+\n+\t\t/* Except at the end of the transfer, nread will be\n+\t\t * equal to the buffer size, which is divisible by the\n+\t\t * bulk-in maxpacket size.\n+\t\t */\n+\t\tbh->inreq->length = nread;\n+\t\tbh->state = BUF_STATE_FULL;\n+\n+\t\t/* If an error occurred, report it and its position */\n+\t\tif (nread < amount) {\n+\t\t\tcurlun->sense_data = SS_UNRECOVERED_READ_ERROR;\n+\t\t\tcurlun->sense_data_info = file_offset >> curlun->blkbits;\n+\t\t\tcurlun->info_valid = 1;\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\tif (amount_left == 0)\n+\t\t\tbreak;\t\t// No more left to read\n+\n+\t\t/* Send this buffer and go read some more */\n+\t\tbh->inreq->zero = 0;\n+\t\tstart_transfer(fsg, fsg->bulk_in, bh->inreq,\n+\t\t\t\t&bh->inreq_busy, &bh->state);\n+\t\tfsg->next_buffhd_to_fill = bh->next;\n+\t}\n+\n+\treturn -EIO;\t\t// No default reply\n+}\n+\n+\n+/*-------------------------------------------------------------------------*/\n+\n+static int do_write(struct fsg_dev *fsg)\n+{\n+\tstruct fsg_lun\t\t*curlun = fsg->curlun;\n+\tu32\t\t\tlba;\n+\tstruct fsg_buffhd\t*bh;\n+\tint\t\t\tget_some_more;\n+\tu32\t\t\tamount_left_to_req, amount_left_to_write;\n+\tloff_t\t\t\tusb_offset, file_offset, file_offset_tmp;\n+\tunsigned int\t\tamount;\n+\tssize_t\t\t\tnwritten;\n+\tint\t\t\trc;\n+\n+\tif (curlun->ro) {\n+\t\tcurlun->sense_data = SS_WRITE_PROTECTED;\n+\t\treturn -EINVAL;\n+\t}\n+\tspin_lock(&curlun->filp->f_lock);\n+\tcurlun->filp->f_flags &= ~O_SYNC;\t// Default is not to wait\n+\tspin_unlock(&curlun->filp->f_lock);\n+\n+\t/* Get the starting Logical Block Address and check that it's\n+\t * not too big */\n+\tif (fsg->cmnd[0] == WRITE_6)\n+\t\tlba = get_unaligned_be24(&fsg->cmnd[1]);\n+\telse {\n+\t\tlba = get_unaligned_be32(&fsg->cmnd[2]);\n+\n+\t\t/* We allow DPO (Disable Page Out = don't save data in the\n+\t\t * cache) and FUA (Force Unit Access = write directly to the\n+\t\t * medium).  We don't implement DPO; we implement FUA by\n+\t\t * performing synchronous output. */\n+\t\tif ((fsg->cmnd[1] & ~0x18) != 0) {\n+\t\t\tcurlun->sense_data = SS_INVALID_FIELD_IN_CDB;\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t\t/* FUA */\n+\t\tif (!curlun->nofua && (fsg->cmnd[1] & 0x08)) {\n+\t\t\tspin_lock(&curlun->filp->f_lock);\n+\t\t\tcurlun->filp->f_flags |= O_DSYNC;\n+\t\t\tspin_unlock(&curlun->filp->f_lock);\n+\t\t}\n+\t}\n+\tif (lba >= curlun->num_sectors) {\n+\t\tcurlun->sense_data = SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE;\n+\t\treturn -EINVAL;\n+\t}\n+\n+\t/* Carry out the file writes */\n+\tget_some_more = 1;\n+\tfile_offset = usb_offset = ((loff_t) lba) << curlun->blkbits;\n+\tamount_left_to_req = amount_left_to_write = fsg->data_size_from_cmnd;\n+\n+\twhile (amount_left_to_write > 0) {\n+\n+\t\t/* Queue a request for more data from the host */\n+\t\tbh = fsg->next_buffhd_to_fill;\n+\t\tif (bh->state == BUF_STATE_EMPTY && get_some_more) {\n+\n+\t\t\t/* Figure out how much we want to get:\n+\t\t\t * Try to get the remaining amount,\n+\t\t\t * but not more than the buffer size.\n+\t\t\t */\n+\t\t\tamount = min(amount_left_to_req, mod_data.buflen);\n+\n+\t\t\t/* Beyond the end of the backing file? */\n+\t\t\tif (usb_offset >= curlun->file_length) {\n+\t\t\t\tget_some_more = 0;\n+\t\t\t\tcurlun->sense_data =\n+\t\t\t\t\tSS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE;\n+\t\t\t\tcurlun->sense_data_info = usb_offset >> curlun->blkbits;\n+\t\t\t\tcurlun->info_valid = 1;\n+\t\t\t\tcontinue;\n+\t\t\t}\n+\n+\t\t\t/* Get the next buffer */\n+\t\t\tusb_offset += amount;\n+\t\t\tfsg->usb_amount_left -= amount;\n+\t\t\tamount_left_to_req -= amount;\n+\t\t\tif (amount_left_to_req == 0)\n+\t\t\t\tget_some_more = 0;\n+\n+\t\t\t/* Except at the end of the transfer, amount will be\n+\t\t\t * equal to the buffer size, which is divisible by\n+\t\t\t * the bulk-out maxpacket size.\n+\t\t\t */\n+\t\t\tset_bulk_out_req_length(fsg, bh, amount);\n+\t\t\tstart_transfer(fsg, fsg->bulk_out, bh->outreq,\n+\t\t\t\t\t&bh->outreq_busy, &bh->state);\n+\t\t\tfsg->next_buffhd_to_fill = bh->next;\n+\t\t\tcontinue;\n+\t\t}\n+\n+\t\t/* Write the received data to the backing file */\n+\t\tbh = fsg->next_buffhd_to_drain;\n+\t\tif (bh->state == BUF_STATE_EMPTY && !get_some_more)\n+\t\t\tbreak;\t\t\t// We stopped early\n+\t\tif (bh->state == BUF_STATE_FULL) {\n+\t\t\tsmp_rmb();\n+\t\t\tfsg->next_buffhd_to_drain = bh->next;\n+\t\t\tbh->state = BUF_STATE_EMPTY;\n+\n+\t\t\t/* Did something go wrong with the transfer? */\n+\t\t\tif (bh->outreq->status != 0) {\n+\t\t\t\tcurlun->sense_data = SS_COMMUNICATION_FAILURE;\n+\t\t\t\tcurlun->sense_data_info = file_offset >> curlun->blkbits;\n+\t\t\t\tcurlun->info_valid = 1;\n+\t\t\t\tbreak;\n+\t\t\t}\n+\n+\t\t\tamount = bh->outreq->actual;\n+\t\t\tif (curlun->file_length - file_offset < amount) {\n+\t\t\t\tLERROR(curlun,\n+\t\"write %u @ %llu beyond end %llu\\n\",\n+\tamount, (unsigned long long) file_offset,\n+\t(unsigned long long) curlun->file_length);\n+\t\t\t\tamount = curlun->file_length - file_offset;\n+\t\t\t}\n+\n+\t\t\t/* Don't accept excess data.  The spec doesn't say\n+\t\t\t * what to do in this case.  We'll ignore the error.\n+\t\t\t */\n+\t\t\tamount = min(amount, bh->bulk_out_intended_length);\n+\n+\t\t\t/* Don't write a partial block */\n+\t\t\tamount = round_down(amount, curlun->blksize);\n+\t\t\tif (amount == 0)\n+\t\t\t\tgoto empty_write;\n+\n+\t\t\t/* Perform the write */\n+\t\t\tfile_offset_tmp = file_offset;\n+\t\t\tnwritten = vfs_write(curlun->filp,\n+\t\t\t\t\t(char __user *) bh->buf,\n+\t\t\t\t\tamount, &file_offset_tmp);\n+\t\t\tVLDBG(curlun, \"file write %u @ %llu -> %d\\n\", amount,\n+\t\t\t\t\t(unsigned long long) file_offset,\n+\t\t\t\t\t(int) nwritten);\n+\t\t\tif (signal_pending(current))\n+\t\t\t\treturn -EINTR;\t\t// Interrupted!\n+\n+\t\t\tif (nwritten < 0) {\n+\t\t\t\tLDBG(curlun, \"error in file write: %d\\n\",\n+\t\t\t\t\t\t(int) nwritten);\n+\t\t\t\tnwritten = 0;\n+\t\t\t} else if (nwritten < amount) {\n+\t\t\t\tLDBG(curlun, \"partial file write: %d/%u\\n\",\n+\t\t\t\t\t\t(int) nwritten, amount);\n+\t\t\t\tnwritten = round_down(nwritten, curlun->blksize);\n+\t\t\t}\n+\t\t\tfile_offset += nwritten;\n+\t\t\tamount_left_to_write -= nwritten;\n+\t\t\tfsg->residue -= nwritten;\n+\n+\t\t\t/* If an error occurred, report it and its position */\n+\t\t\tif (nwritten < amount) {\n+\t\t\t\tcurlun->sense_data = SS_WRITE_ERROR;\n+\t\t\t\tcurlun->sense_data_info = file_offset >> curlun->blkbits;\n+\t\t\t\tcurlun->info_valid = 1;\n+\t\t\t\tbreak;\n+\t\t\t}\n+\n+ empty_write:\n+\t\t\t/* Did the host decide to stop early? */\n+\t\t\tif (bh->outreq->actual < bh->bulk_out_intended_length) {\n+\t\t\t\tfsg->short_packet_received = 1;\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t\tcontinue;\n+\t\t}\n+\n+\t\t/* Wait for something to happen */\n+\t\trc = sleep_thread(fsg);\n+\t\tif (rc)\n+\t\t\treturn rc;\n+\t}\n+\n+\treturn -EIO;\t\t// No default reply\n+}\n+\n+\n+/*-------------------------------------------------------------------------*/\n+\n+static int do_synchronize_cache(struct fsg_dev *fsg)\n+{\n+\tstruct fsg_lun\t*curlun = fsg->curlun;\n+\tint\t\trc;\n+\n+\t/* We ignore the requested LBA and write out all file's\n+\t * dirty data buffers. */\n+\trc = fsg_lun_fsync_sub(curlun);\n+\tif (rc)\n+\t\tcurlun->sense_data = SS_WRITE_ERROR;\n+\treturn 0;\n+}\n+\n+\n+/*-------------------------------------------------------------------------*/\n+\n+static void invalidate_sub(struct fsg_lun *curlun)\n+{\n+\tstruct file\t*filp = curlun->filp;\n+\tstruct inode\t*inode = filp->f_path.dentry->d_inode;\n+\tunsigned long\trc;\n+\n+\trc = invalidate_mapping_pages(inode->i_mapping, 0, -1);\n+\tVLDBG(curlun, \"invalidate_mapping_pages -> %ld\\n\", rc);\n+}\n+\n+static int do_verify(struct fsg_dev *fsg)\n+{\n+\tstruct fsg_lun\t\t*curlun = fsg->curlun;\n+\tu32\t\t\tlba;\n+\tu32\t\t\tverification_length;\n+\tstruct fsg_buffhd\t*bh = fsg->next_buffhd_to_fill;\n+\tloff_t\t\t\tfile_offset, file_offset_tmp;\n+\tu32\t\t\tamount_left;\n+\tunsigned int\t\tamount;\n+\tssize_t\t\t\tnread;\n+\n+\t/* Get the starting Logical Block Address and check that it's\n+\t * not too big */\n+\tlba = get_unaligned_be32(&fsg->cmnd[2]);\n+\tif (lba >= curlun->num_sectors) {\n+\t\tcurlun->sense_data = SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE;\n+\t\treturn -EINVAL;\n+\t}\n+\n+\t/* We allow DPO (Disable Page Out = don't save data in the\n+\t * cache) but we don't implement it. */\n+\tif ((fsg->cmnd[1] & ~0x10) != 0) {\n+\t\tcurlun->sense_data = SS_INVALID_FIELD_IN_CDB;\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tverification_length = get_unaligned_be16(&fsg->cmnd[7]);\n+\tif (unlikely(verification_length == 0))\n+\t\treturn -EIO;\t\t// No default reply\n+\n+\t/* Prepare to carry out the file verify */\n+\tamount_left = verification_length << curlun->blkbits;\n+\tfile_offset = ((loff_t) lba) << curlun->blkbits;\n+\n+\t/* Write out all the dirty buffers before invalidating them */\n+\tfsg_lun_fsync_sub(curlun);\n+\tif (signal_pending(current))\n+\t\treturn -EINTR;\n+\n+\tinvalidate_sub(curlun);\n+\tif (signal_pending(current))\n+\t\treturn -EINTR;\n+\n+\t/* Just try to read the requested blocks */\n+\twhile (amount_left > 0) {\n+\n+\t\t/* Figure out how much we need to read:\n+\t\t * Try to read the remaining amount, but not more than\n+\t\t * the buffer size.\n+\t\t * And don't try to read past the end of the file.\n+\t\t */\n+\t\tamount = min((unsigned int) amount_left, mod_data.buflen);\n+\t\tamount = min((loff_t) amount,\n+\t\t\t\tcurlun->file_length - file_offset);\n+\t\tif (amount == 0) {\n+\t\t\tcurlun->sense_data =\n+\t\t\t\t\tSS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE;\n+\t\t\tcurlun->sense_data_info = file_offset >> curlun->blkbits;\n+\t\t\tcurlun->info_valid = 1;\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\t/* Perform the read */\n+\t\tfile_offset_tmp = file_offset;\n+\t\tnread = vfs_read(curlun->filp,\n+\t\t\t\t(char __user *) bh->buf,\n+\t\t\t\tamount, &file_offset_tmp);\n+\t\tVLDBG(curlun, \"file read %u @ %llu -> %d\\n\", amount,\n+\t\t\t\t(unsigned long long) file_offset,\n+\t\t\t\t(int) nread);\n+\t\tif (signal_pending(current))\n+\t\t\treturn -EINTR;\n+\n+\t\tif (nread < 0) {\n+\t\t\tLDBG(curlun, \"error in file verify: %d\\n\",\n+\t\t\t\t\t(int) nread);\n+\t\t\tnread = 0;\n+\t\t} else if (nread < amount) {\n+\t\t\tLDBG(curlun, \"partial file verify: %d/%u\\n\",\n+\t\t\t\t\t(int) nread, amount);\n+\t\t\tnread = round_down(nread, curlun->blksize);\n+\t\t}\n+\t\tif (nread == 0) {\n+\t\t\tcurlun->sense_data = SS_UNRECOVERED_READ_ERROR;\n+\t\t\tcurlun->sense_data_info = file_offset >> curlun->blkbits;\n+\t\t\tcurlun->info_valid = 1;\n+\t\t\tbreak;\n+\t\t}\n+\t\tfile_offset += nread;\n+\t\tamount_left -= nread;\n+\t}\n+\treturn 0;\n+}\n+\n+\n+/*-------------------------------------------------------------------------*/\n+\n+static int do_inquiry(struct fsg_dev *fsg, struct fsg_buffhd *bh)\n+{\n+\tu8\t*buf = (u8 *) bh->buf;\n+\n+\tstatic char vendor_id[] = \"Linux   \";\n+\tstatic char product_disk_id[] = \"File-Stor Gadget\";\n+\tstatic char product_cdrom_id[] = \"File-CD Gadget  \";\n+\n+\tif (!fsg->curlun) {\t\t// Unsupported LUNs are okay\n+\t\tfsg->bad_lun_okay = 1;\n+\t\tmemset(buf, 0, 36);\n+\t\tbuf[0] = 0x7f;\t\t// Unsupported, no device-type\n+\t\tbuf[4] = 31;\t\t// Additional length\n+\t\treturn 36;\n+\t}\n+\n+\tmemset(buf, 0, 8);\n+\tbuf[0] = (mod_data.cdrom ? TYPE_ROM : TYPE_DISK);\n+\tif (mod_data.removable)\n+\t\tbuf[1] = 0x80;\n+\tbuf[2] = 2;\t\t// ANSI SCSI level 2\n+\tbuf[3] = 2;\t\t// SCSI-2 INQUIRY data format\n+\tbuf[4] = 31;\t\t// Additional length\n+\t\t\t\t// No special options\n+\tsprintf(buf + 8, \"%-8s%-16s%04x\", vendor_id,\n+\t\t\t(mod_data.cdrom ? product_cdrom_id :\n+\t\t\t\tproduct_disk_id),\n+\t\t\tmod_data.release);\n+\treturn 36;\n+}\n+\n+\n+static int do_request_sense(struct fsg_dev *fsg, struct fsg_buffhd *bh)\n+{\n+\tstruct fsg_lun\t*curlun = fsg->curlun;\n+\tu8\t\t*buf = (u8 *) bh->buf;\n+\tu32\t\tsd, sdinfo;\n+\tint\t\tvalid;\n+\n+\t/*\n+\t * From the SCSI-2 spec., section 7.9 (Unit attention condition):\n+\t *\n+\t * If a REQUEST SENSE command is received from an initiator\n+\t * with a pending unit attention condition (before the target\n+\t * generates the contingent allegiance condition), then the\n+\t * target shall either:\n+\t *   a) report any pending sense data and preserve the unit\n+\t *\tattention condition on the logical unit, or,\n+\t *   b) report the unit attention condition, may discard any\n+\t *\tpending sense data, and clear the unit attention\n+\t *\tcondition on the logical unit for that initiator.\n+\t *\n+\t * FSG normally uses option a); enable this code to use option b).\n+\t */\n+#if 0\n+\tif (curlun && curlun->unit_attention_data != SS_NO_SENSE) {\n+\t\tcurlun->sense_data = curlun->unit_attention_data;\n+\t\tcurlun->unit_attention_data = SS_NO_SENSE;\n+\t}\n+#endif\n+\n+\tif (!curlun) {\t\t// Unsupported LUNs are okay\n+\t\tfsg->bad_lun_okay = 1;\n+\t\tsd = SS_LOGICAL_UNIT_NOT_SUPPORTED;\n+\t\tsdinfo = 0;\n+\t\tvalid = 0;\n+\t} else {\n+\t\tsd = curlun->sense_data;\n+\t\tsdinfo = curlun->sense_data_info;\n+\t\tvalid = curlun->info_valid << 7;\n+\t\tcurlun->sense_data = SS_NO_SENSE;\n+\t\tcurlun->sense_data_info = 0;\n+\t\tcurlun->info_valid = 0;\n+\t}\n+\n+\tmemset(buf, 0, 18);\n+\tbuf[0] = valid | 0x70;\t\t\t// Valid, current error\n+\tbuf[2] = SK(sd);\n+\tput_unaligned_be32(sdinfo, &buf[3]);\t/* Sense information */\n+\tbuf[7] = 18 - 8;\t\t\t// Additional sense length\n+\tbuf[12] = ASC(sd);\n+\tbuf[13] = ASCQ(sd);\n+\treturn 18;\n+}\n+\n+\n+static int do_read_capacity(struct fsg_dev *fsg, struct fsg_buffhd *bh)\n+{\n+\tstruct fsg_lun\t*curlun = fsg->curlun;\n+\tu32\t\tlba = get_unaligned_be32(&fsg->cmnd[2]);\n+\tint\t\tpmi = fsg->cmnd[8];\n+\tu8\t\t*buf = (u8 *) bh->buf;\n+\n+\t/* Check the PMI and LBA fields */\n+\tif (pmi > 1 || (pmi == 0 && lba != 0)) {\n+\t\tcurlun->sense_data = SS_INVALID_FIELD_IN_CDB;\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tput_unaligned_be32(curlun->num_sectors - 1, &buf[0]);\n+\t\t\t\t\t\t/* Max logical block */\n+\tput_unaligned_be32(curlun->blksize, &buf[4]);\t/* Block length */\n+\treturn 8;\n+}\n+\n+\n+static int do_read_header(struct fsg_dev *fsg, struct fsg_buffhd *bh)\n+{\n+\tstruct fsg_lun\t*curlun = fsg->curlun;\n+\tint\t\tmsf = fsg->cmnd[1] & 0x02;\n+\tu32\t\tlba = get_unaligned_be32(&fsg->cmnd[2]);\n+\tu8\t\t*buf = (u8 *) bh->buf;\n+\n+\tif ((fsg->cmnd[1] & ~0x02) != 0) {\t\t/* Mask away MSF */\n+\t\tcurlun->sense_data = SS_INVALID_FIELD_IN_CDB;\n+\t\treturn -EINVAL;\n+\t}\n+\tif (lba >= curlun->num_sectors) {\n+\t\tcurlun->sense_data = SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE;\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tmemset(buf, 0, 8);\n+\tbuf[0] = 0x01;\t\t/* 2048 bytes of user data, rest is EC */\n+\tstore_cdrom_address(&buf[4], msf, lba);\n+\treturn 8;\n+}\n+\n+\n+static int do_read_toc(struct fsg_dev *fsg, struct fsg_buffhd *bh)\n+{\n+\tstruct fsg_lun\t*curlun = fsg->curlun;\n+\tint\t\tmsf = fsg->cmnd[1] & 0x02;\n+\tint\t\tstart_track = fsg->cmnd[6];\n+\tu8\t\t*buf = (u8 *) bh->buf;\n+\n+\tif ((fsg->cmnd[1] & ~0x02) != 0 ||\t\t/* Mask away MSF */\n+\t\t\tstart_track > 1) {\n+\t\tcurlun->sense_data = SS_INVALID_FIELD_IN_CDB;\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tmemset(buf, 0, 20);\n+\tbuf[1] = (20-2);\t\t/* TOC data length */\n+\tbuf[2] = 1;\t\t\t/* First track number */\n+\tbuf[3] = 1;\t\t\t/* Last track number */\n+\tbuf[5] = 0x16;\t\t\t/* Data track, copying allowed */\n+\tbuf[6] = 0x01;\t\t\t/* Only track is number 1 */\n+\tstore_cdrom_address(&buf[8], msf, 0);\n+\n+\tbuf[13] = 0x16;\t\t\t/* Lead-out track is data */\n+\tbuf[14] = 0xAA;\t\t\t/* Lead-out track number */\n+\tstore_cdrom_address(&buf[16], msf, curlun->num_sectors);\n+\treturn 20;\n+}\n+\n+\n+static int do_mode_sense(struct fsg_dev *fsg, struct fsg_buffhd *bh)\n+{\n+\tstruct fsg_lun\t*curlun = fsg->curlun;\n+\tint\t\tmscmnd = fsg->cmnd[0];\n+\tu8\t\t*buf = (u8 *) bh->buf;\n+\tu8\t\t*buf0 = buf;\n+\tint\t\tpc, page_code;\n+\tint\t\tchangeable_values, all_pages;\n+\tint\t\tvalid_page = 0;\n+\tint\t\tlen, limit;\n+\n+\tif ((fsg->cmnd[1] & ~0x08) != 0) {\t\t// Mask away DBD\n+\t\tcurlun->sense_data = SS_INVALID_FIELD_IN_CDB;\n+\t\treturn -EINVAL;\n+\t}\n+\tpc = fsg->cmnd[2] >> 6;\n+\tpage_code = fsg->cmnd[2] & 0x3f;\n+\tif (pc == 3) {\n+\t\tcurlun->sense_data = SS_SAVING_PARAMETERS_NOT_SUPPORTED;\n+\t\treturn -EINVAL;\n+\t}\n+\tchangeable_values = (pc == 1);\n+\tall_pages = (page_code == 0x3f);\n+\n+\t/* Write the mode parameter header.  Fixed values are: default\n+\t * medium type, no cache control (DPOFUA), and no block descriptors.\n+\t * The only variable value is the WriteProtect bit.  We will fill in\n+\t * the mode data length later. */\n+\tmemset(buf, 0, 8);\n+\tif (mscmnd == MODE_SENSE) {\n+\t\tbuf[2] = (curlun->ro ? 0x80 : 0x00);\t\t// WP, DPOFUA\n+\t\tbuf += 4;\n+\t\tlimit = 255;\n+\t} else {\t\t\t// MODE_SENSE_10\n+\t\tbuf[3] = (curlun->ro ? 0x80 : 0x00);\t\t// WP, DPOFUA\n+\t\tbuf += 8;\n+\t\tlimit = 65535;\t\t// Should really be mod_data.buflen\n+\t}\n+\n+\t/* No block descriptors */\n+\n+\t/* The mode pages, in numerical order.  The only page we support\n+\t * is the Caching page. */\n+\tif (page_code == 0x08 || all_pages) {\n+\t\tvalid_page = 1;\n+\t\tbuf[0] = 0x08;\t\t// Page code\n+\t\tbuf[1] = 10;\t\t// Page length\n+\t\tmemset(buf+2, 0, 10);\t// None of the fields are changeable\n+\n+\t\tif (!changeable_values) {\n+\t\t\tbuf[2] = 0x04;\t// Write cache enable,\n+\t\t\t\t\t// Read cache not disabled\n+\t\t\t\t\t// No cache retention priorities\n+\t\t\tput_unaligned_be16(0xffff, &buf[4]);\n+\t\t\t\t\t/* Don't disable prefetch */\n+\t\t\t\t\t/* Minimum prefetch = 0 */\n+\t\t\tput_unaligned_be16(0xffff, &buf[8]);\n+\t\t\t\t\t/* Maximum prefetch */\n+\t\t\tput_unaligned_be16(0xffff, &buf[10]);\n+\t\t\t\t\t/* Maximum prefetch ceiling */\n+\t\t}\n+\t\tbuf += 12;\n+\t}\n+\n+\t/* Check that a valid page was requested and the mode data length\n+\t * isn't too long. */\n+\tlen = buf - buf0;\n+\tif (!valid_page || len > limit) {\n+\t\tcurlun->sense_data = SS_INVALID_FIELD_IN_CDB;\n+\t\treturn -EINVAL;\n+\t}\n+\n+\t/*  Store the mode data length */\n+\tif (mscmnd == MODE_SENSE)\n+\t\tbuf0[0] = len - 1;\n+\telse\n+\t\tput_unaligned_be16(len - 2, buf0);\n+\treturn len;\n+}\n+\n+\n+static int do_start_stop(struct fsg_dev *fsg)\n+{\n+\tstruct fsg_lun\t*curlun = fsg->curlun;\n+\tint\t\tloej, start;\n+\n+\tif (!mod_data.removable) {\n+\t\tcurlun->sense_data = SS_INVALID_COMMAND;\n+\t\treturn -EINVAL;\n+\t}\n+\n+\t// int immed = fsg->cmnd[1] & 0x01;\n+\tloej = fsg->cmnd[4] & 0x02;\n+\tstart = fsg->cmnd[4] & 0x01;\n+\n+#ifdef CONFIG_USB_FILE_STORAGE_TEST\n+\tif ((fsg->cmnd[1] & ~0x01) != 0 ||\t\t// Mask away Immed\n+\t\t\t(fsg->cmnd[4] & ~0x03) != 0) {\t// Mask LoEj, Start\n+\t\tcurlun->sense_data = SS_INVALID_FIELD_IN_CDB;\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (!start) {\n+\n+\t\t/* Are we allowed to unload the media? */\n+\t\tif (curlun->prevent_medium_removal) {\n+\t\t\tLDBG(curlun, \"unload attempt prevented\\n\");\n+\t\t\tcurlun->sense_data = SS_MEDIUM_REMOVAL_PREVENTED;\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t\tif (loej) {\t\t// Simulate an unload/eject\n+\t\t\tup_read(&fsg->filesem);\n+\t\t\tdown_write(&fsg->filesem);\n+\t\t\tfsg_lun_close(curlun);\n+\t\t\tup_write(&fsg->filesem);\n+\t\t\tdown_read(&fsg->filesem);\n+\t\t}\n+\t} else {\n+\n+\t\t/* Our emulation doesn't support mounting; the medium is\n+\t\t * available for use as soon as it is loaded. */\n+\t\tif (!fsg_lun_is_open(curlun)) {\n+\t\t\tcurlun->sense_data = SS_MEDIUM_NOT_PRESENT;\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t}\n+#endif\n+\treturn 0;\n+}\n+\n+\n+static int do_prevent_allow(struct fsg_dev *fsg)\n+{\n+\tstruct fsg_lun\t*curlun = fsg->curlun;\n+\tint\t\tprevent;\n+\n+\tif (!mod_data.removable) {\n+\t\tcurlun->sense_data = SS_INVALID_COMMAND;\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tprevent = fsg->cmnd[4] & 0x01;\n+\tif ((fsg->cmnd[4] & ~0x01) != 0) {\t\t// Mask away Prevent\n+\t\tcurlun->sense_data = SS_INVALID_FIELD_IN_CDB;\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (curlun->prevent_medium_removal && !prevent)\n+\t\tfsg_lun_fsync_sub(curlun);\n+\tcurlun->prevent_medium_removal = prevent;\n+\treturn 0;\n+}\n+\n+\n+static int do_read_format_capacities(struct fsg_dev *fsg,\n+\t\t\tstruct fsg_buffhd *bh)\n+{\n+\tstruct fsg_lun\t*curlun = fsg->curlun;\n+\tu8\t\t*buf = (u8 *) bh->buf;\n+\n+\tbuf[0] = buf[1] = buf[2] = 0;\n+\tbuf[3] = 8;\t\t// Only the Current/Maximum Capacity Descriptor\n+\tbuf += 4;\n+\n+\tput_unaligned_be32(curlun->num_sectors, &buf[0]);\n+\t\t\t\t\t\t/* Number of blocks */\n+\tput_unaligned_be32(curlun->blksize, &buf[4]);\t/* Block length */\n+\tbuf[4] = 0x02;\t\t\t\t/* Current capacity */\n+\treturn 12;\n+}\n+\n+\n+static int do_mode_select(struct fsg_dev *fsg, struct fsg_buffhd *bh)\n+{\n+\tstruct fsg_lun\t*curlun = fsg->curlun;\n+\n+\t/* We don't support MODE SELECT */\n+\tcurlun->sense_data = SS_INVALID_COMMAND;\n+\treturn -EINVAL;\n+}\n+\n+\n+/*-------------------------------------------------------------------------*/\n+\n+static int halt_bulk_in_endpoint(struct fsg_dev *fsg)\n+{\n+\tint\trc;\n+\n+\trc = fsg_set_halt(fsg, fsg->bulk_in);\n+\tif (rc == -EAGAIN)\n+\t\tVDBG(fsg, \"delayed bulk-in endpoint halt\\n\");\n+\twhile (rc != 0) {\n+\t\tif (rc != -EAGAIN) {\n+\t\t\tWARNING(fsg, \"usb_ep_set_halt -> %d\\n\", rc);\n+\t\t\trc = 0;\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\t/* Wait for a short time and then try again */\n+\t\tif (msleep_interruptible(100) != 0)\n+\t\t\treturn -EINTR;\n+\t\trc = usb_ep_set_halt(fsg->bulk_in);\n+\t}\n+\treturn rc;\n+}\n+\n+static int wedge_bulk_in_endpoint(struct fsg_dev *fsg)\n+{\n+\tint\trc;\n+\n+\tDBG(fsg, \"bulk-in set wedge\\n\");\n+\trc = usb_ep_set_wedge(fsg->bulk_in);\n+\tif (rc == -EAGAIN)\n+\t\tVDBG(fsg, \"delayed bulk-in endpoint wedge\\n\");\n+\twhile (rc != 0) {\n+\t\tif (rc != -EAGAIN) {\n+\t\t\tWARNING(fsg, \"usb_ep_set_wedge -> %d\\n\", rc);\n+\t\t\trc = 0;\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\t/* Wait for a short time and then try again */\n+\t\tif (msleep_interruptible(100) != 0)\n+\t\t\treturn -EINTR;\n+\t\trc = usb_ep_set_wedge(fsg->bulk_in);\n+\t}\n+\treturn rc;\n+}\n+\n+static int throw_away_data(struct fsg_dev *fsg)\n+{\n+\tstruct fsg_buffhd\t*bh;\n+\tu32\t\t\tamount;\n+\tint\t\t\trc;\n+\n+\twhile ((bh = fsg->next_buffhd_to_drain)->state != BUF_STATE_EMPTY ||\n+\t\t\tfsg->usb_amount_left > 0) {\n+\n+\t\t/* Throw away the data in a filled buffer */\n+\t\tif (bh->state == BUF_STATE_FULL) {\n+\t\t\tsmp_rmb();\n+\t\t\tbh->state = BUF_STATE_EMPTY;\n+\t\t\tfsg->next_buffhd_to_drain = bh->next;\n+\n+\t\t\t/* A short packet or an error ends everything */\n+\t\t\tif (bh->outreq->actual < bh->bulk_out_intended_length ||\n+\t\t\t\t\tbh->outreq->status != 0) {\n+\t\t\t\traise_exception(fsg, FSG_STATE_ABORT_BULK_OUT);\n+\t\t\t\treturn -EINTR;\n+\t\t\t}\n+\t\t\tcontinue;\n+\t\t}\n+\n+\t\t/* Try to submit another request if we need one */\n+\t\tbh = fsg->next_buffhd_to_fill;\n+\t\tif (bh->state == BUF_STATE_EMPTY && fsg->usb_amount_left > 0) {\n+\t\t\tamount = min(fsg->usb_amount_left,\n+\t\t\t\t\t(u32) mod_data.buflen);\n+\n+\t\t\t/* Except at the end of the transfer, amount will be\n+\t\t\t * equal to the buffer size, which is divisible by\n+\t\t\t * the bulk-out maxpacket size.\n+\t\t\t */\n+\t\t\tset_bulk_out_req_length(fsg, bh, amount);\n+\t\t\tstart_transfer(fsg, fsg->bulk_out, bh->outreq,\n+\t\t\t\t\t&bh->outreq_busy, &bh->state);\n+\t\t\tfsg->next_buffhd_to_fill = bh->next;\n+\t\t\tfsg->usb_amount_left -= amount;\n+\t\t\tcontinue;\n+\t\t}\n+\n+\t\t/* Otherwise wait for something to happen */\n+\t\trc = sleep_thread(fsg);\n+\t\tif (rc)\n+\t\t\treturn rc;\n+\t}\n+\treturn 0;\n+}\n+\n+\n+static int finish_reply(struct fsg_dev *fsg)\n+{\n+\tstruct fsg_buffhd\t*bh = fsg->next_buffhd_to_fill;\n+\tint\t\t\trc = 0;\n+\n+\tswitch (fsg->data_dir) {\n+\tcase DATA_DIR_NONE:\n+\t\tbreak;\t\t\t// Nothing to send\n+\n+\t/* If we don't know whether the host wants to read or write,\n+\t * this must be CB or CBI with an unknown command.  We mustn't\n+\t * try to send or receive any data.  So stall both bulk pipes\n+\t * if we can and wait for a reset. */\n+\tcase DATA_DIR_UNKNOWN:\n+\t\tif (mod_data.can_stall) {\n+\t\t\tfsg_set_halt(fsg, fsg->bulk_out);\n+\t\t\trc = halt_bulk_in_endpoint(fsg);\n+\t\t}\n+\t\tbreak;\n+\n+\t/* All but the last buffer of data must have already been sent */\n+\tcase DATA_DIR_TO_HOST:\n+\t\tif (fsg->data_size == 0)\n+\t\t\t;\t\t// Nothing to send\n+\n+\t\t/* If there's no residue, simply send the last buffer */\n+\t\telse if (fsg->residue == 0) {\n+\t\t\tbh->inreq->zero = 0;\n+\t\t\tstart_transfer(fsg, fsg->bulk_in, bh->inreq,\n+\t\t\t\t\t&bh->inreq_busy, &bh->state);\n+\t\t\tfsg->next_buffhd_to_fill = bh->next;\n+\t\t}\n+\n+\t\t/* There is a residue.  For CB and CBI, simply mark the end\n+\t\t * of the data with a short packet.  However, if we are\n+\t\t * allowed to stall, there was no data at all (residue ==\n+\t\t * data_size), and the command failed (invalid LUN or\n+\t\t * sense data is set), then halt the bulk-in endpoint\n+\t\t * instead. */\n+\t\telse if (!transport_is_bbb()) {\n+\t\t\tif (mod_data.can_stall &&\n+\t\t\t\t\tfsg->residue == fsg->data_size &&\n+\t(!fsg->curlun || fsg->curlun->sense_data != SS_NO_SENSE)) {\n+\t\t\t\tbh->state = BUF_STATE_EMPTY;\n+\t\t\t\trc = halt_bulk_in_endpoint(fsg);\n+\t\t\t} else {\n+\t\t\t\tbh->inreq->zero = 1;\n+\t\t\t\tstart_transfer(fsg, fsg->bulk_in, bh->inreq,\n+\t\t\t\t\t\t&bh->inreq_busy, &bh->state);\n+\t\t\t\tfsg->next_buffhd_to_fill = bh->next;\n+\t\t\t}\n+\t\t}\n+\n+\t\t/*\n+\t\t * For Bulk-only, mark the end of the data with a short\n+\t\t * packet.  If we are allowed to stall, halt the bulk-in\n+\t\t * endpoint.  (Note: This violates the Bulk-Only Transport\n+\t\t * specification, which requires us to pad the data if we\n+\t\t * don't halt the endpoint.  Presumably nobody will mind.)\n+\t\t */\n+\t\telse {\n+\t\t\tbh->inreq->zero = 1;\n+\t\t\tstart_transfer(fsg, fsg->bulk_in, bh->inreq,\n+\t\t\t\t\t&bh->inreq_busy, &bh->state);\n+\t\t\tfsg->next_buffhd_to_fill = bh->next;\n+\t\t\tif (mod_data.can_stall)\n+\t\t\t\trc = halt_bulk_in_endpoint(fsg);\n+\t\t}\n+\t\tbreak;\n+\n+\t/* We have processed all we want from the data the host has sent.\n+\t * There may still be outstanding bulk-out requests. */\n+\tcase DATA_DIR_FROM_HOST:\n+\t\tif (fsg->residue == 0)\n+\t\t\t;\t\t// Nothing to receive\n+\n+\t\t/* Did the host stop sending unexpectedly early? */\n+\t\telse if (fsg->short_packet_received) {\n+\t\t\traise_exception(fsg, FSG_STATE_ABORT_BULK_OUT);\n+\t\t\trc = -EINTR;\n+\t\t}\n+\n+\t\t/* We haven't processed all the incoming data.  Even though\n+\t\t * we may be allowed to stall, doing so would cause a race.\n+\t\t * The controller may already have ACK'ed all the remaining\n+\t\t * bulk-out packets, in which case the host wouldn't see a\n+\t\t * STALL.  Not realizing the endpoint was halted, it wouldn't\n+\t\t * clear the halt -- leading to problems later on. */\n+#if 0\n+\t\telse if (mod_data.can_stall) {\n+\t\t\tfsg_set_halt(fsg, fsg->bulk_out);\n+\t\t\traise_exception(fsg, FSG_STATE_ABORT_BULK_OUT);\n+\t\t\trc = -EINTR;\n+\t\t}\n+#endif\n+\n+\t\t/* We can't stall.  Read in the excess data and throw it\n+\t\t * all away. */\n+\t\telse\n+\t\t\trc = throw_away_data(fsg);\n+\t\tbreak;\n+\t}\n+\treturn rc;\n+}\n+\n+\n+static int send_status(struct fsg_dev *fsg)\n+{\n+\tstruct fsg_lun\t\t*curlun = fsg->curlun;\n+\tstruct fsg_buffhd\t*bh;\n+\tint\t\t\trc;\n+\tu8\t\t\tstatus = US_BULK_STAT_OK;\n+\tu32\t\t\tsd, sdinfo = 0;\n+\n+\t/* Wait for the next buffer to become available */\n+\tbh = fsg->next_buffhd_to_fill;\n+\twhile (bh->state != BUF_STATE_EMPTY) {\n+\t\trc = sleep_thread(fsg);\n+\t\tif (rc)\n+\t\t\treturn rc;\n+\t}\n+\n+\tif (curlun) {\n+\t\tsd = curlun->sense_data;\n+\t\tsdinfo = curlun->sense_data_info;\n+\t} else if (fsg->bad_lun_okay)\n+\t\tsd = SS_NO_SENSE;\n+\telse\n+\t\tsd = SS_LOGICAL_UNIT_NOT_SUPPORTED;\n+\n+\tif (fsg->phase_error) {\n+\t\tDBG(fsg, \"sending phase-error status\\n\");\n+\t\tstatus = US_BULK_STAT_PHASE;\n+\t\tsd = SS_INVALID_COMMAND;\n+\t} else if (sd != SS_NO_SENSE) {\n+\t\tDBG(fsg, \"sending command-failure status\\n\");\n+\t\tstatus = US_BULK_STAT_FAIL;\n+\t\tVDBG(fsg, \"  sense data: SK x%02x, ASC x%02x, ASCQ x%02x;\"\n+\t\t\t\t\"  info x%x\\n\",\n+\t\t\t\tSK(sd), ASC(sd), ASCQ(sd), sdinfo);\n+\t}\n+\n+\tif (transport_is_bbb()) {\n+\t\tstruct bulk_cs_wrap\t*csw = bh->buf;\n+\n+\t\t/* Store and send the Bulk-only CSW */\n+\t\tcsw->Signature = cpu_to_le32(US_BULK_CS_SIGN);\n+\t\tcsw->Tag = fsg->tag;\n+\t\tcsw->Residue = cpu_to_le32(fsg->residue);\n+\t\tcsw->Status = status;\n+\n+\t\tbh->inreq->length = US_BULK_CS_WRAP_LEN;\n+\t\tbh->inreq->zero = 0;\n+\t\tstart_transfer(fsg, fsg->bulk_in, bh->inreq,\n+\t\t\t\t&bh->inreq_busy, &bh->state);\n+\n+\t} else if (mod_data.transport_type == USB_PR_CB) {\n+\n+\t\t/* Control-Bulk transport has no status phase! */\n+\t\treturn 0;\n+\n+\t} else {\t\t\t// USB_PR_CBI\n+\t\tstruct interrupt_data\t*buf = bh->buf;\n+\n+\t\t/* Store and send the Interrupt data.  UFI sends the ASC\n+\t\t * and ASCQ bytes.  Everything else sends a Type (which\n+\t\t * is always 0) and the status Value. */\n+\t\tif (mod_data.protocol_type == USB_SC_UFI) {\n+\t\t\tbuf->bType = ASC(sd);\n+\t\t\tbuf->bValue = ASCQ(sd);\n+\t\t} else {\n+\t\t\tbuf->bType = 0;\n+\t\t\tbuf->bValue = status;\n+\t\t}\n+\t\tfsg->intreq->length = CBI_INTERRUPT_DATA_LEN;\n+\n+\t\tfsg->intr_buffhd = bh;\t\t// Point to the right buffhd\n+\t\tfsg->intreq->buf = bh->inreq->buf;\n+\t\tfsg->intreq->context = bh;\n+\t\tstart_transfer(fsg, fsg->intr_in, fsg->intreq,\n+\t\t\t\t&fsg->intreq_busy, &bh->state);\n+\t}\n+\n+\tfsg->next_buffhd_to_fill = bh->next;\n+\treturn 0;\n+}\n+\n+\n+/*-------------------------------------------------------------------------*/\n+\n+/* Check whether the command is properly formed and whether its data size\n+ * and direction agree with the values we already have. */\n+static int check_command(struct fsg_dev *fsg, int cmnd_size,\n+\t\tenum data_direction data_dir, unsigned int mask,\n+\t\tint needs_medium, const char *name)\n+{\n+\tint\t\t\ti;\n+\tint\t\t\tlun = fsg->cmnd[1] >> 5;\n+\tstatic const char\tdirletter[4] = {'u', 'o', 'i', 'n'};\n+\tchar\t\t\thdlen[20];\n+\tstruct fsg_lun\t\t*curlun;\n+\n+\t/* Adjust the expected cmnd_size for protocol encapsulation padding.\n+\t * Transparent SCSI doesn't pad. */\n+\tif (protocol_is_scsi())\n+\t\t;\n+\n+\t/* There's some disagreement as to whether RBC pads commands or not.\n+\t * We'll play it safe and accept either form. */\n+\telse if (mod_data.protocol_type == USB_SC_RBC) {\n+\t\tif (fsg->cmnd_size == 12)\n+\t\t\tcmnd_size = 12;\n+\n+\t/* All the other protocols pad to 12 bytes */\n+\t} else\n+\t\tcmnd_size = 12;\n+\n+\thdlen[0] = 0;\n+\tif (fsg->data_dir != DATA_DIR_UNKNOWN)\n+\t\tsprintf(hdlen, \", H%c=%u\", dirletter[(int) fsg->data_dir],\n+\t\t\t\tfsg->data_size);\n+\tVDBG(fsg, \"SCSI command: %s;  Dc=%d, D%c=%u;  Hc=%d%s\\n\",\n+\t\t\tname, cmnd_size, dirletter[(int) data_dir],\n+\t\t\tfsg->data_size_from_cmnd, fsg->cmnd_size, hdlen);\n+\n+\t/* We can't reply at all until we know the correct data direction\n+\t * and size. */\n+\tif (fsg->data_size_from_cmnd == 0)\n+\t\tdata_dir = DATA_DIR_NONE;\n+\tif (fsg->data_dir == DATA_DIR_UNKNOWN) {\t// CB or CBI\n+\t\tfsg->data_dir = data_dir;\n+\t\tfsg->data_size = fsg->data_size_from_cmnd;\n+\n+\t} else {\t\t\t\t\t// Bulk-only\n+\t\tif (fsg->data_size < fsg->data_size_from_cmnd) {\n+\n+\t\t\t/* Host data size < Device data size is a phase error.\n+\t\t\t * Carry out the command, but only transfer as much\n+\t\t\t * as we are allowed. */\n+\t\t\tfsg->data_size_from_cmnd = fsg->data_size;\n+\t\t\tfsg->phase_error = 1;\n+\t\t}\n+\t}\n+\tfsg->residue = fsg->usb_amount_left = fsg->data_size;\n+\n+\t/* Conflicting data directions is a phase error */\n+\tif (fsg->data_dir != data_dir && fsg->data_size_from_cmnd > 0) {\n+\t\tfsg->phase_error = 1;\n+\t\treturn -EINVAL;\n+\t}\n+\n+\t/* Verify the length of the command itself */\n+\tif (cmnd_size != fsg->cmnd_size) {\n+\n+\t\t/* Special case workaround: There are plenty of buggy SCSI\n+\t\t * implementations. Many have issues with cbw->Length\n+\t\t * field passing a wrong command size. For those cases we\n+\t\t * always try to work around the problem by using the length\n+\t\t * sent by the host side provided it is at least as large\n+\t\t * as the correct command length.\n+\t\t * Examples of such cases would be MS-Windows, which issues\n+\t\t * REQUEST SENSE with cbw->Length == 12 where it should\n+\t\t * be 6, and xbox360 issuing INQUIRY, TEST UNIT READY and\n+\t\t * REQUEST SENSE with cbw->Length == 10 where it should\n+\t\t * be 6 as well.\n+\t\t */\n+\t\tif (cmnd_size <= fsg->cmnd_size) {\n+\t\t\tDBG(fsg, \"%s is buggy! Expected length %d \"\n+\t\t\t\t\t\"but we got %d\\n\", name,\n+\t\t\t\t\tcmnd_size, fsg->cmnd_size);\n+\t\t\tcmnd_size = fsg->cmnd_size;\n+\t\t} else {\n+\t\t\tfsg->phase_error = 1;\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t}\n+\n+\t/* Check that the LUN values are consistent */\n+\tif (transport_is_bbb()) {\n+\t\tif (fsg->lun != lun)\n+\t\t\tDBG(fsg, \"using LUN %d from CBW, \"\n+\t\t\t\t\t\"not LUN %d from CDB\\n\",\n+\t\t\t\t\tfsg->lun, lun);\n+\t}\n+\n+\t/* Check the LUN */\n+\tcurlun = fsg->curlun;\n+\tif (curlun) {\n+\t\tif (fsg->cmnd[0] != REQUEST_SENSE) {\n+\t\t\tcurlun->sense_data = SS_NO_SENSE;\n+\t\t\tcurlun->sense_data_info = 0;\n+\t\t\tcurlun->info_valid = 0;\n+\t\t}\n+\t} else {\n+\t\tfsg->bad_lun_okay = 0;\n+\n+\t\t/* INQUIRY and REQUEST SENSE commands are explicitly allowed\n+\t\t * to use unsupported LUNs; all others may not. */\n+\t\tif (fsg->cmnd[0] != INQUIRY &&\n+\t\t\t\tfsg->cmnd[0] != REQUEST_SENSE) {\n+\t\t\tDBG(fsg, \"unsupported LUN %d\\n\", fsg->lun);\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t}\n+\n+\t/* If a unit attention condition exists, only INQUIRY and\n+\t * REQUEST SENSE commands are allowed; anything else must fail. */\n+\tif (curlun && curlun->unit_attention_data != SS_NO_SENSE &&\n+\t\t\tfsg->cmnd[0] != INQUIRY &&\n+\t\t\tfsg->cmnd[0] != REQUEST_SENSE) {\n+\t\tcurlun->sense_data = curlun->unit_attention_data;\n+\t\tcurlun->unit_attention_data = SS_NO_SENSE;\n+\t\treturn -EINVAL;\n+\t}\n+\n+\t/* Check that only command bytes listed in the mask are non-zero */\n+\tfsg->cmnd[1] &= 0x1f;\t\t\t// Mask away the LUN\n+\tfor (i = 1; i < cmnd_size; ++i) {\n+\t\tif (fsg->cmnd[i] && !(mask & (1 << i))) {\n+\t\t\tif (curlun)\n+\t\t\t\tcurlun->sense_data = SS_INVALID_FIELD_IN_CDB;\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t}\n+\n+\t/* If the medium isn't mounted and the command needs to access\n+\t * it, return an error. */\n+\tif (curlun && !fsg_lun_is_open(curlun) && needs_medium) {\n+\t\tcurlun->sense_data = SS_MEDIUM_NOT_PRESENT;\n+\t\treturn -EINVAL;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+/* wrapper of check_command for data size in blocks handling */\n+static int check_command_size_in_blocks(struct fsg_dev *fsg, int cmnd_size,\n+\t\tenum data_direction data_dir, unsigned int mask,\n+\t\tint needs_medium, const char *name)\n+{\n+\tif (fsg->curlun)\n+\t\tfsg->data_size_from_cmnd <<= fsg->curlun->blkbits;\n+\treturn check_command(fsg, cmnd_size, data_dir,\n+\t\t\tmask, needs_medium, name);\n+}\n+\n+static int do_scsi_command(struct fsg_dev *fsg)\n+{\n+\tstruct fsg_buffhd\t*bh;\n+\tint\t\t\trc;\n+\tint\t\t\treply = -EINVAL;\n+\tint\t\t\ti;\n+\tstatic char\t\tunknown[16];\n+\n+\tdump_cdb(fsg);\n+\n+\t/* Wait for the next buffer to become available for data or status */\n+\tbh = fsg->next_buffhd_to_drain = fsg->next_buffhd_to_fill;\n+\twhile (bh->state != BUF_STATE_EMPTY) {\n+\t\trc = sleep_thread(fsg);\n+\t\tif (rc)\n+\t\t\treturn rc;\n+\t}\n+\tfsg->phase_error = 0;\n+\tfsg->short_packet_received = 0;\n+\n+\tdown_read(&fsg->filesem);\t// We're using the backing file\n+\tswitch (fsg->cmnd[0]) {\n+\n+\tcase INQUIRY:\n+\t\tfsg->data_size_from_cmnd = fsg->cmnd[4];\n+\t\tif ((reply = check_command(fsg, 6, DATA_DIR_TO_HOST,\n+\t\t\t\t(1<<4), 0,\n+\t\t\t\t\"INQUIRY\")) == 0)\n+\t\t\treply = do_inquiry(fsg, bh);\n+\t\tbreak;\n+\n+\tcase MODE_SELECT:\n+\t\tfsg->data_size_from_cmnd = fsg->cmnd[4];\n+\t\tif ((reply = check_command(fsg, 6, DATA_DIR_FROM_HOST,\n+\t\t\t\t(1<<1) | (1<<4), 0,\n+\t\t\t\t\"MODE SELECT(6)\")) == 0)\n+\t\t\treply = do_mode_select(fsg, bh);\n+\t\tbreak;\n+\n+\tcase MODE_SELECT_10:\n+\t\tfsg->data_size_from_cmnd = get_unaligned_be16(&fsg->cmnd[7]);\n+\t\tif ((reply = check_command(fsg, 10, DATA_DIR_FROM_HOST,\n+\t\t\t\t(1<<1) | (3<<7), 0,\n+\t\t\t\t\"MODE SELECT(10)\")) == 0)\n+\t\t\treply = do_mode_select(fsg, bh);\n+\t\tbreak;\n+\n+\tcase MODE_SENSE:\n+\t\tfsg->data_size_from_cmnd = fsg->cmnd[4];\n+\t\tif ((reply = check_command(fsg, 6, DATA_DIR_TO_HOST,\n+\t\t\t\t(1<<1) | (1<<2) | (1<<4), 0,\n+\t\t\t\t\"MODE SENSE(6)\")) == 0)\n+\t\t\treply = do_mode_sense(fsg, bh);\n+\t\tbreak;\n+\n+\tcase MODE_SENSE_10:\n+\t\tfsg->data_size_from_cmnd = get_unaligned_be16(&fsg->cmnd[7]);\n+\t\tif ((reply = check_command(fsg, 10, DATA_DIR_TO_HOST,\n+\t\t\t\t(1<<1) | (1<<2) | (3<<7), 0,\n+\t\t\t\t\"MODE SENSE(10)\")) == 0)\n+\t\t\treply = do_mode_sense(fsg, bh);\n+\t\tbreak;\n+\n+\tcase ALLOW_MEDIUM_REMOVAL:\n+\t\tfsg->data_size_from_cmnd = 0;\n+\t\tif ((reply = check_command(fsg, 6, DATA_DIR_NONE,\n+\t\t\t\t(1<<4), 0,\n+\t\t\t\t\"PREVENT-ALLOW MEDIUM REMOVAL\")) == 0)\n+\t\t\treply = do_prevent_allow(fsg);\n+\t\tbreak;\n+\n+\tcase READ_6:\n+\t\ti = fsg->cmnd[4];\n+\t\tfsg->data_size_from_cmnd = (i == 0) ? 256 : i;\n+\t\tif ((reply = check_command_size_in_blocks(fsg, 6,\n+\t\t\t\tDATA_DIR_TO_HOST,\n+\t\t\t\t(7<<1) | (1<<4), 1,\n+\t\t\t\t\"READ(6)\")) == 0)\n+\t\t\treply = do_read(fsg);\n+\t\tbreak;\n+\n+\tcase READ_10:\n+\t\tfsg->data_size_from_cmnd = get_unaligned_be16(&fsg->cmnd[7]);\n+\t\tif ((reply = check_command_size_in_blocks(fsg, 10,\n+\t\t\t\tDATA_DIR_TO_HOST,\n+\t\t\t\t(1<<1) | (0xf<<2) | (3<<7), 1,\n+\t\t\t\t\"READ(10)\")) == 0)\n+\t\t\treply = do_read(fsg);\n+\t\tbreak;\n+\n+\tcase READ_12:\n+\t\tfsg->data_size_from_cmnd = get_unaligned_be32(&fsg->cmnd[6]);\n+\t\tif ((reply = check_command_size_in_blocks(fsg, 12,\n+\t\t\t\tDATA_DIR_TO_HOST,\n+\t\t\t\t(1<<1) | (0xf<<2) | (0xf<<6), 1,\n+\t\t\t\t\"READ(12)\")) == 0)\n+\t\t\treply = do_read(fsg);\n+\t\tbreak;\n+\n+\tcase READ_CAPACITY:\n+\t\tfsg->data_size_from_cmnd = 8;\n+\t\tif ((reply = check_command(fsg, 10, DATA_DIR_TO_HOST,\n+\t\t\t\t(0xf<<2) | (1<<8), 1,\n+\t\t\t\t\"READ CAPACITY\")) == 0)\n+\t\t\treply = do_read_capacity(fsg, bh);\n+\t\tbreak;\n+\n+\tcase READ_HEADER:\n+\t\tif (!mod_data.cdrom)\n+\t\t\tgoto unknown_cmnd;\n+\t\tfsg->data_size_from_cmnd = get_unaligned_be16(&fsg->cmnd[7]);\n+\t\tif ((reply = check_command(fsg, 10, DATA_DIR_TO_HOST,\n+\t\t\t\t(3<<7) | (0x1f<<1), 1,\n+\t\t\t\t\"READ HEADER\")) == 0)\n+\t\t\treply = do_read_header(fsg, bh);\n+\t\tbreak;\n+\n+\tcase READ_TOC:\n+\t\tif (!mod_data.cdrom)\n+\t\t\tgoto unknown_cmnd;\n+\t\tfsg->data_size_from_cmnd = get_unaligned_be16(&fsg->cmnd[7]);\n+\t\tif ((reply = check_command(fsg, 10, DATA_DIR_TO_HOST,\n+\t\t\t\t(7<<6) | (1<<1), 1,\n+\t\t\t\t\"READ TOC\")) == 0)\n+\t\t\treply = do_read_toc(fsg, bh);\n+\t\tbreak;\n+\n+\tcase READ_FORMAT_CAPACITIES:\n+\t\tfsg->data_size_from_cmnd = get_unaligned_be16(&fsg->cmnd[7]);\n+\t\tif ((reply = check_command(fsg, 10, DATA_DIR_TO_HOST,\n+\t\t\t\t(3<<7), 1,\n+\t\t\t\t\"READ FORMAT CAPACITIES\")) == 0)\n+\t\t\treply = do_read_format_capacities(fsg, bh);\n+\t\tbreak;\n+\n+\tcase REQUEST_SENSE:\n+\t\tfsg->data_size_from_cmnd = fsg->cmnd[4];\n+\t\tif ((reply = check_command(fsg, 6, DATA_DIR_TO_HOST,\n+\t\t\t\t(1<<4), 0,\n+\t\t\t\t\"REQUEST SENSE\")) == 0)\n+\t\t\treply = do_request_sense(fsg, bh);\n+\t\tbreak;\n+\n+\tcase START_STOP:\n+\t\tfsg->data_size_from_cmnd = 0;\n+\t\tif ((reply = check_command(fsg, 6, DATA_DIR_NONE,\n+\t\t\t\t(1<<1) | (1<<4), 0,\n+\t\t\t\t\"START-STOP UNIT\")) == 0)\n+\t\t\treply = do_start_stop(fsg);\n+\t\tbreak;\n+\n+\tcase SYNCHRONIZE_CACHE:\n+\t\tfsg->data_size_from_cmnd = 0;\n+\t\tif ((reply = check_command(fsg, 10, DATA_DIR_NONE,\n+\t\t\t\t(0xf<<2) | (3<<7), 1,\n+\t\t\t\t\"SYNCHRONIZE CACHE\")) == 0)\n+\t\t\treply = do_synchronize_cache(fsg);\n+\t\tbreak;\n+\n+\tcase TEST_UNIT_READY:\n+\t\tfsg->data_size_from_cmnd = 0;\n+\t\treply = check_command(fsg, 6, DATA_DIR_NONE,\n+\t\t\t\t0, 1,\n+\t\t\t\t\"TEST UNIT READY\");\n+\t\tbreak;\n+\n+\t/* Although optional, this command is used by MS-Windows.  We\n+\t * support a minimal version: BytChk must be 0. */\n+\tcase VERIFY:\n+\t\tfsg->data_size_from_cmnd = 0;\n+\t\tif ((reply = check_command(fsg, 10, DATA_DIR_NONE,\n+\t\t\t\t(1<<1) | (0xf<<2) | (3<<7), 1,\n+\t\t\t\t\"VERIFY\")) == 0)\n+\t\t\treply = do_verify(fsg);\n+\t\tbreak;\n+\n+\tcase WRITE_6:\n+\t\ti = fsg->cmnd[4];\n+\t\tfsg->data_size_from_cmnd = (i == 0) ? 256 : i;\n+\t\tif ((reply = check_command_size_in_blocks(fsg, 6,\n+\t\t\t\tDATA_DIR_FROM_HOST,\n+\t\t\t\t(7<<1) | (1<<4), 1,\n+\t\t\t\t\"WRITE(6)\")) == 0)\n+\t\t\treply = do_write(fsg);\n+\t\tbreak;\n+\n+\tcase WRITE_10:\n+\t\tfsg->data_size_from_cmnd = get_unaligned_be16(&fsg->cmnd[7]);\n+\t\tif ((reply = check_command_size_in_blocks(fsg, 10,\n+\t\t\t\tDATA_DIR_FROM_HOST,\n+\t\t\t\t(1<<1) | (0xf<<2) | (3<<7), 1,\n+\t\t\t\t\"WRITE(10)\")) == 0)\n+\t\t\treply = do_write(fsg);\n+\t\tbreak;\n+\n+\tcase WRITE_12:\n+\t\tfsg->data_size_from_cmnd = get_unaligned_be32(&fsg->cmnd[6]);\n+\t\tif ((reply = check_command_size_in_blocks(fsg, 12,\n+\t\t\t\tDATA_DIR_FROM_HOST,\n+\t\t\t\t(1<<1) | (0xf<<2) | (0xf<<6), 1,\n+\t\t\t\t\"WRITE(12)\")) == 0)\n+\t\t\treply = do_write(fsg);\n+\t\tbreak;\n+\n+\t/* Some mandatory commands that we recognize but don't implement.\n+\t * They don't mean much in this setting.  It's left as an exercise\n+\t * for anyone interested to implement RESERVE and RELEASE in terms\n+\t * of Posix locks. */\n+\tcase FORMAT_UNIT:\n+\tcase RELEASE:\n+\tcase RESERVE:\n+\tcase SEND_DIAGNOSTIC:\n+\t\t// Fall through\n+\n+\tdefault:\n+ unknown_cmnd:\n+\t\tfsg->data_size_from_cmnd = 0;\n+\t\tsprintf(unknown, \"Unknown x%02x\", fsg->cmnd[0]);\n+\t\tif ((reply = check_command(fsg, fsg->cmnd_size,\n+\t\t\t\tDATA_DIR_UNKNOWN, ~0, 0, unknown)) == 0) {\n+\t\t\tfsg->curlun->sense_data = SS_INVALID_COMMAND;\n+\t\t\treply = -EINVAL;\n+\t\t}\n+\t\tbreak;\n+\t}\n+\tup_read(&fsg->filesem);\n+\n+\tif (reply == -EINTR || signal_pending(current))\n+\t\treturn -EINTR;\n+\n+\t/* Set up the single reply buffer for finish_reply() */\n+\tif (reply == -EINVAL)\n+\t\treply = 0;\t\t// Error reply length\n+\tif (reply >= 0 && fsg->data_dir == DATA_DIR_TO_HOST) {\n+\t\treply = min((u32) reply, fsg->data_size_from_cmnd);\n+\t\tbh->inreq->length = reply;\n+\t\tbh->state = BUF_STATE_FULL;\n+\t\tfsg->residue -= reply;\n+\t}\t\t\t\t// Otherwise it's already set\n+\n+\treturn 0;\n+}\n+\n+\n+/*-------------------------------------------------------------------------*/\n+\n+static int received_cbw(struct fsg_dev *fsg, struct fsg_buffhd *bh)\n+{\n+\tstruct usb_request\t\t*req = bh->outreq;\n+\tstruct bulk_cb_wrap\t*cbw = req->buf;\n+\n+\t/* Was this a real packet?  Should it be ignored? */\n+\tif (req->status || test_bit(IGNORE_BULK_OUT, &fsg->atomic_bitflags))\n+\t\treturn -EINVAL;\n+\n+\t/* Is the CBW valid? */\n+\tif (req->actual != US_BULK_CB_WRAP_LEN ||\n+\t\t\tcbw->Signature != cpu_to_le32(\n+\t\t\t\tUS_BULK_CB_SIGN)) {\n+\t\tDBG(fsg, \"invalid CBW: len %u sig 0x%x\\n\",\n+\t\t\t\treq->actual,\n+\t\t\t\tle32_to_cpu(cbw->Signature));\n+\n+\t\t/* The Bulk-only spec says we MUST stall the IN endpoint\n+\t\t * (6.6.1), so it's unavoidable.  It also says we must\n+\t\t * retain this state until the next reset, but there's\n+\t\t * no way to tell the controller driver it should ignore\n+\t\t * Clear-Feature(HALT) requests.\n+\t\t *\n+\t\t * We aren't required to halt the OUT endpoint; instead\n+\t\t * we can simply accept and discard any data received\n+\t\t * until the next reset. */\n+\t\twedge_bulk_in_endpoint(fsg);\n+\t\tset_bit(IGNORE_BULK_OUT, &fsg->atomic_bitflags);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\t/* Is the CBW meaningful? */\n+\tif (cbw->Lun >= FSG_MAX_LUNS || cbw->Flags & ~US_BULK_FLAG_IN ||\n+\t\t\tcbw->Length <= 0 || cbw->Length > MAX_COMMAND_SIZE) {\n+\t\tDBG(fsg, \"non-meaningful CBW: lun = %u, flags = 0x%x, \"\n+\t\t\t\t\"cmdlen %u\\n\",\n+\t\t\t\tcbw->Lun, cbw->Flags, cbw->Length);\n+\n+\t\t/* We can do anything we want here, so let's stall the\n+\t\t * bulk pipes if we are allowed to. */\n+\t\tif (mod_data.can_stall) {\n+\t\t\tfsg_set_halt(fsg, fsg->bulk_out);\n+\t\t\thalt_bulk_in_endpoint(fsg);\n+\t\t}\n+\t\treturn -EINVAL;\n+\t}\n+\n+\t/* Save the command for later */\n+\tfsg->cmnd_size = cbw->Length;\n+\tmemcpy(fsg->cmnd, cbw->CDB, fsg->cmnd_size);\n+\tif (cbw->Flags & US_BULK_FLAG_IN)\n+\t\tfsg->data_dir = DATA_DIR_TO_HOST;\n+\telse\n+\t\tfsg->data_dir = DATA_DIR_FROM_HOST;\n+\tfsg->data_size = le32_to_cpu(cbw->DataTransferLength);\n+\tif (fsg->data_size == 0)\n+\t\tfsg->data_dir = DATA_DIR_NONE;\n+\tfsg->lun = cbw->Lun;\n+\tfsg->tag = cbw->Tag;\n+\treturn 0;\n+}\n+\n+\n+static int get_next_command(struct fsg_dev *fsg)\n+{\n+\tstruct fsg_buffhd\t*bh;\n+\tint\t\t\trc = 0;\n+\n+\tif (transport_is_bbb()) {\n+\n+\t\t/* Wait for the next buffer to become available */\n+\t\tbh = fsg->next_buffhd_to_fill;\n+\t\twhile (bh->state != BUF_STATE_EMPTY) {\n+\t\t\trc = sleep_thread(fsg);\n+\t\t\tif (rc)\n+\t\t\t\treturn rc;\n+\t\t}\n+\n+\t\t/* Queue a request to read a Bulk-only CBW */\n+\t\tset_bulk_out_req_length(fsg, bh, US_BULK_CB_WRAP_LEN);\n+\t\tstart_transfer(fsg, fsg->bulk_out, bh->outreq,\n+\t\t\t\t&bh->outreq_busy, &bh->state);\n+\n+\t\t/* We will drain the buffer in software, which means we\n+\t\t * can reuse it for the next filling.  No need to advance\n+\t\t * next_buffhd_to_fill. */\n+\n+\t\t/* Wait for the CBW to arrive */\n+\t\twhile (bh->state != BUF_STATE_FULL) {\n+\t\t\trc = sleep_thread(fsg);\n+\t\t\tif (rc)\n+\t\t\t\treturn rc;\n+\t\t}\n+\t\tsmp_rmb();\n+\t\trc = received_cbw(fsg, bh);\n+\t\tbh->state = BUF_STATE_EMPTY;\n+\n+\t} else {\t\t// USB_PR_CB or USB_PR_CBI\n+\n+\t\t/* Wait for the next command to arrive */\n+\t\twhile (fsg->cbbuf_cmnd_size == 0) {\n+\t\t\trc = sleep_thread(fsg);\n+\t\t\tif (rc)\n+\t\t\t\treturn rc;\n+\t\t}\n+\n+\t\t/* Is the previous status interrupt request still busy?\n+\t\t * The host is allowed to skip reading the status,\n+\t\t * so we must cancel it. */\n+\t\tif (fsg->intreq_busy)\n+\t\t\tusb_ep_dequeue(fsg->intr_in, fsg->intreq);\n+\n+\t\t/* Copy the command and mark the buffer empty */\n+\t\tfsg->data_dir = DATA_DIR_UNKNOWN;\n+\t\tspin_lock_irq(&fsg->lock);\n+\t\tfsg->cmnd_size = fsg->cbbuf_cmnd_size;\n+\t\tmemcpy(fsg->cmnd, fsg->cbbuf_cmnd, fsg->cmnd_size);\n+\t\tfsg->cbbuf_cmnd_size = 0;\n+\t\tspin_unlock_irq(&fsg->lock);\n+\n+\t\t/* Use LUN from the command */\n+\t\tfsg->lun = fsg->cmnd[1] >> 5;\n+\t}\n+\n+\t/* Update current lun */\n+\tif (fsg->lun >= 0 && fsg->lun < fsg->nluns)\n+\t\tfsg->curlun = &fsg->luns[fsg->lun];\n+\telse\n+\t\tfsg->curlun = NULL;\n+\n+\treturn rc;\n+}\n+\n+\n+/*-------------------------------------------------------------------------*/\n+\n+static int enable_endpoint(struct fsg_dev *fsg, struct usb_ep *ep,\n+\t\tconst struct usb_endpoint_descriptor *d)\n+{\n+\tint\trc;\n+\n+\tep->driver_data = fsg;\n+\tep->desc = d;\n+\trc = usb_ep_enable(ep);\n+\tif (rc)\n+\t\tERROR(fsg, \"can't enable %s, result %d\\n\", ep->name, rc);\n+\treturn rc;\n+}\n+\n+static int alloc_request(struct fsg_dev *fsg, struct usb_ep *ep,\n+\t\tstruct usb_request **preq)\n+{\n+\t*preq = usb_ep_alloc_request(ep, GFP_ATOMIC);\n+\tif (*preq)\n+\t\treturn 0;\n+\tERROR(fsg, \"can't allocate request for %s\\n\", ep->name);\n+\treturn -ENOMEM;\n+}\n+\n+/*\n+ * Reset interface setting and re-init endpoint state (toggle etc).\n+ * Call with altsetting < 0 to disable the interface.  The only other\n+ * available altsetting is 0, which enables the interface.\n+ */\n+static int do_set_interface(struct fsg_dev *fsg, int altsetting)\n+{\n+\tint\trc = 0;\n+\tint\ti;\n+\tconst struct usb_endpoint_descriptor\t*d;\n+\n+\tif (fsg->running)\n+\t\tDBG(fsg, \"reset interface\\n\");\n+\n+reset:\n+\t/* Deallocate the requests */\n+\tfor (i = 0; i < fsg_num_buffers; ++i) {\n+\t\tstruct fsg_buffhd *bh = &fsg->buffhds[i];\n+\n+\t\tif (bh->inreq) {\n+\t\t\tusb_ep_free_request(fsg->bulk_in, bh->inreq);\n+\t\t\tbh->inreq = NULL;\n+\t\t}\n+\t\tif (bh->outreq) {\n+\t\t\tusb_ep_free_request(fsg->bulk_out, bh->outreq);\n+\t\t\tbh->outreq = NULL;\n+\t\t}\n+\t}\n+\tif (fsg->intreq) {\n+\t\tusb_ep_free_request(fsg->intr_in, fsg->intreq);\n+\t\tfsg->intreq = NULL;\n+\t}\n+\n+\t/* Disable the endpoints */\n+\tif (fsg->bulk_in_enabled) {\n+\t\tusb_ep_disable(fsg->bulk_in);\n+\t\tfsg->bulk_in_enabled = 0;\n+\t}\n+\tif (fsg->bulk_out_enabled) {\n+\t\tusb_ep_disable(fsg->bulk_out);\n+\t\tfsg->bulk_out_enabled = 0;\n+\t}\n+\tif (fsg->intr_in_enabled) {\n+\t\tusb_ep_disable(fsg->intr_in);\n+\t\tfsg->intr_in_enabled = 0;\n+\t}\n+\n+\tfsg->running = 0;\n+\tif (altsetting < 0 || rc != 0)\n+\t\treturn rc;\n+\n+\tDBG(fsg, \"set interface %d\\n\", altsetting);\n+\n+\t/* Enable the endpoints */\n+\td = fsg_ep_desc(fsg->gadget,\n+\t\t\t&fsg_fs_bulk_in_desc, &fsg_hs_bulk_in_desc,\n+\t\t\t&fsg_ss_bulk_in_desc);\n+\tif ((rc = enable_endpoint(fsg, fsg->bulk_in, d)) != 0)\n+\t\tgoto reset;\n+\tfsg->bulk_in_enabled = 1;\n+\n+\td = fsg_ep_desc(fsg->gadget,\n+\t\t\t&fsg_fs_bulk_out_desc, &fsg_hs_bulk_out_desc,\n+\t\t\t&fsg_ss_bulk_out_desc);\n+\tif ((rc = enable_endpoint(fsg, fsg->bulk_out, d)) != 0)\n+\t\tgoto reset;\n+\tfsg->bulk_out_enabled = 1;\n+\tfsg->bulk_out_maxpacket = usb_endpoint_maxp(d);\n+\tclear_bit(IGNORE_BULK_OUT, &fsg->atomic_bitflags);\n+\n+\tif (transport_is_cbi()) {\n+\t\td = fsg_ep_desc(fsg->gadget,\n+\t\t\t\t&fsg_fs_intr_in_desc, &fsg_hs_intr_in_desc,\n+\t\t\t\t&fsg_ss_intr_in_desc);\n+\t\tif ((rc = enable_endpoint(fsg, fsg->intr_in, d)) != 0)\n+\t\t\tgoto reset;\n+\t\tfsg->intr_in_enabled = 1;\n+\t}\n+\n+\t/* Allocate the requests */\n+\tfor (i = 0; i < fsg_num_buffers; ++i) {\n+\t\tstruct fsg_buffhd\t*bh = &fsg->buffhds[i];\n+\n+\t\tif ((rc = alloc_request(fsg, fsg->bulk_in, &bh->inreq)) != 0)\n+\t\t\tgoto reset;\n+\t\tif ((rc = alloc_request(fsg, fsg->bulk_out, &bh->outreq)) != 0)\n+\t\t\tgoto reset;\n+\t\tbh->inreq->buf = bh->outreq->buf = bh->buf;\n+\t\tbh->inreq->context = bh->outreq->context = bh;\n+\t\tbh->inreq->complete = bulk_in_complete;\n+\t\tbh->outreq->complete = bulk_out_complete;\n+\t}\n+\tif (transport_is_cbi()) {\n+\t\tif ((rc = alloc_request(fsg, fsg->intr_in, &fsg->intreq)) != 0)\n+\t\t\tgoto reset;\n+\t\tfsg->intreq->complete = intr_in_complete;\n+\t}\n+\n+\tfsg->running = 1;\n+\tfor (i = 0; i < fsg->nluns; ++i)\n+\t\tfsg->luns[i].unit_attention_data = SS_RESET_OCCURRED;\n+\treturn rc;\n+}\n+\n+\n+/*\n+ * Change our operational configuration.  This code must agree with the code\n+ * that returns config descriptors, and with interface altsetting code.\n+ *\n+ * It's also responsible for power management interactions.  Some\n+ * configurations might not work with our current power sources.\n+ * For now we just assume the gadget is always self-powered.\n+ */\n+static int do_set_config(struct fsg_dev *fsg, u8 new_config)\n+{\n+\tint\trc = 0;\n+\n+\t/* Disable the single interface */\n+\tif (fsg->config != 0) {\n+\t\tDBG(fsg, \"reset config\\n\");\n+\t\tfsg->config = 0;\n+\t\trc = do_set_interface(fsg, -1);\n+\t}\n+\n+\t/* Enable the interface */\n+\tif (new_config != 0) {\n+\t\tfsg->config = new_config;\n+\t\tif ((rc = do_set_interface(fsg, 0)) != 0)\n+\t\t\tfsg->config = 0;\t// Reset on errors\n+\t\telse\n+\t\t\tINFO(fsg, \"%s config #%d\\n\",\n+\t\t\t     usb_speed_string(fsg->gadget->speed),\n+\t\t\t     fsg->config);\n+\t}\n+\treturn rc;\n+}\n+\n+\n+/*-------------------------------------------------------------------------*/\n+\n+static void handle_exception(struct fsg_dev *fsg)\n+{\n+\tsiginfo_t\t\tinfo;\n+\tint\t\t\tsig;\n+\tint\t\t\ti;\n+\tint\t\t\tnum_active;\n+\tstruct fsg_buffhd\t*bh;\n+\tenum fsg_state\t\told_state;\n+\tu8\t\t\tnew_config;\n+\tstruct fsg_lun\t\t*curlun;\n+\tunsigned int\t\texception_req_tag;\n+\tint\t\t\trc;\n+\n+\t/* Clear the existing signals.  Anything but SIGUSR1 is converted\n+\t * into a high-priority EXIT exception. */\n+\tfor (;;) {\n+\t\tsig = dequeue_signal_lock(current, &current->blocked, &info);\n+\t\tif (!sig)\n+\t\t\tbreak;\n+\t\tif (sig != SIGUSR1) {\n+\t\t\tif (fsg->state < FSG_STATE_EXIT)\n+\t\t\t\tDBG(fsg, \"Main thread exiting on signal\\n\");\n+\t\t\traise_exception(fsg, FSG_STATE_EXIT);\n+\t\t}\n+\t}\n+\n+\t/* Cancel all the pending transfers */\n+\tif (fsg->intreq_busy)\n+\t\tusb_ep_dequeue(fsg->intr_in, fsg->intreq);\n+\tfor (i = 0; i < fsg_num_buffers; ++i) {\n+\t\tbh = &fsg->buffhds[i];\n+\t\tif (bh->inreq_busy)\n+\t\t\tusb_ep_dequeue(fsg->bulk_in, bh->inreq);\n+\t\tif (bh->outreq_busy)\n+\t\t\tusb_ep_dequeue(fsg->bulk_out, bh->outreq);\n+\t}\n+\n+\t/* Wait until everything is idle */\n+\tfor (;;) {\n+\t\tnum_active = fsg->intreq_busy;\n+\t\tfor (i = 0; i < fsg_num_buffers; ++i) {\n+\t\t\tbh = &fsg->buffhds[i];\n+\t\t\tnum_active += bh->inreq_busy + bh->outreq_busy;\n+\t\t}\n+\t\tif (num_active == 0)\n+\t\t\tbreak;\n+\t\tif (sleep_thread(fsg))\n+\t\t\treturn;\n+\t}\n+\n+\t/* Clear out the controller's fifos */\n+\tif (fsg->bulk_in_enabled)\n+\t\tusb_ep_fifo_flush(fsg->bulk_in);\n+\tif (fsg->bulk_out_enabled)\n+\t\tusb_ep_fifo_flush(fsg->bulk_out);\n+\tif (fsg->intr_in_enabled)\n+\t\tusb_ep_fifo_flush(fsg->intr_in);\n+\n+\t/* Reset the I/O buffer states and pointers, the SCSI\n+\t * state, and the exception.  Then invoke the handler. */\n+\tspin_lock_irq(&fsg->lock);\n+\n+\tfor (i = 0; i < fsg_num_buffers; ++i) {\n+\t\tbh = &fsg->buffhds[i];\n+\t\tbh->state = BUF_STATE_EMPTY;\n+\t}\n+\tfsg->next_buffhd_to_fill = fsg->next_buffhd_to_drain =\n+\t\t\t&fsg->buffhds[0];\n+\n+\texception_req_tag = fsg->exception_req_tag;\n+\tnew_config = fsg->new_config;\n+\told_state = fsg->state;\n+\n+\tif (old_state == FSG_STATE_ABORT_BULK_OUT)\n+\t\tfsg->state = FSG_STATE_STATUS_PHASE;\n+\telse {\n+\t\tfor (i = 0; i < fsg->nluns; ++i) {\n+\t\t\tcurlun = &fsg->luns[i];\n+\t\t\tcurlun->prevent_medium_removal = 0;\n+\t\t\tcurlun->sense_data = curlun->unit_attention_data =\n+\t\t\t\t\tSS_NO_SENSE;\n+\t\t\tcurlun->sense_data_info = 0;\n+\t\t\tcurlun->info_valid = 0;\n+\t\t}\n+\t\tfsg->state = FSG_STATE_IDLE;\n+\t}\n+\tspin_unlock_irq(&fsg->lock);\n+\n+\t/* Carry out any extra actions required for the exception */\n+\tswitch (old_state) {\n+\tdefault:\n+\t\tbreak;\n+\n+\tcase FSG_STATE_ABORT_BULK_OUT:\n+\t\tsend_status(fsg);\n+\t\tspin_lock_irq(&fsg->lock);\n+\t\tif (fsg->state == FSG_STATE_STATUS_PHASE)\n+\t\t\tfsg->state = FSG_STATE_IDLE;\n+\t\tspin_unlock_irq(&fsg->lock);\n+\t\tbreak;\n+\n+\tcase FSG_STATE_RESET:\n+\t\t/* In case we were forced against our will to halt a\n+\t\t * bulk endpoint, clear the halt now.  (The SuperH UDC\n+\t\t * requires this.) */\n+\t\tif (test_and_clear_bit(IGNORE_BULK_OUT, &fsg->atomic_bitflags))\n+\t\t\tusb_ep_clear_halt(fsg->bulk_in);\n+\n+\t\tif (transport_is_bbb()) {\n+\t\t\tif (fsg->ep0_req_tag == exception_req_tag)\n+\t\t\t\tep0_queue(fsg);\t// Complete the status stage\n+\n+\t\t} else if (transport_is_cbi())\n+\t\t\tsend_status(fsg);\t// Status by interrupt pipe\n+\n+\t\t/* Technically this should go here, but it would only be\n+\t\t * a waste of time.  Ditto for the INTERFACE_CHANGE and\n+\t\t * CONFIG_CHANGE cases. */\n+\t\t// for (i = 0; i < fsg->nluns; ++i)\n+\t\t//\tfsg->luns[i].unit_attention_data = SS_RESET_OCCURRED;\n+\t\tbreak;\n+\n+\tcase FSG_STATE_INTERFACE_CHANGE:\n+\t\trc = do_set_interface(fsg, 0);\n+\t\tif (fsg->ep0_req_tag != exception_req_tag)\n+\t\t\tbreak;\n+\t\tif (rc != 0)\t\t\t// STALL on errors\n+\t\t\tfsg_set_halt(fsg, fsg->ep0);\n+\t\telse\t\t\t\t// Complete the status stage\n+\t\t\tep0_queue(fsg);\n+\t\tbreak;\n+\n+\tcase FSG_STATE_CONFIG_CHANGE:\n+\t\trc = do_set_config(fsg, new_config);\n+\t\tif (fsg->ep0_req_tag != exception_req_tag)\n+\t\t\tbreak;\n+\t\tif (rc != 0)\t\t\t// STALL on errors\n+\t\t\tfsg_set_halt(fsg, fsg->ep0);\n+\t\telse\t\t\t\t// Complete the status stage\n+\t\t\tep0_queue(fsg);\n+\t\tbreak;\n+\n+\tcase FSG_STATE_DISCONNECT:\n+\t\tfor (i = 0; i < fsg->nluns; ++i)\n+\t\t\tfsg_lun_fsync_sub(fsg->luns + i);\n+\t\tdo_set_config(fsg, 0);\t\t// Unconfigured state\n+\t\tbreak;\n+\n+\tcase FSG_STATE_EXIT:\n+\tcase FSG_STATE_TERMINATED:\n+\t\tdo_set_config(fsg, 0);\t\t\t// Free resources\n+\t\tspin_lock_irq(&fsg->lock);\n+\t\tfsg->state = FSG_STATE_TERMINATED;\t// Stop the thread\n+\t\tspin_unlock_irq(&fsg->lock);\n+\t\tbreak;\n+\t}\n+}\n+\n+\n+/*-------------------------------------------------------------------------*/\n+\n+static int fsg_main_thread(void *fsg_)\n+{\n+\tstruct fsg_dev\t\t*fsg = fsg_;\n+\n+\t/* Allow the thread to be killed by a signal, but set the signal mask\n+\t * to block everything but INT, TERM, KILL, and USR1. */\n+\tallow_signal(SIGINT);\n+\tallow_signal(SIGTERM);\n+\tallow_signal(SIGKILL);\n+\tallow_signal(SIGUSR1);\n+\n+\t/* Allow the thread to be frozen */\n+\tset_freezable();\n+\n+\t/* Arrange for userspace references to be interpreted as kernel\n+\t * pointers.  That way we can pass a kernel pointer to a routine\n+\t * that expects a __user pointer and it will work okay. */\n+\tset_fs(get_ds());\n+\n+\t/* The main loop */\n+\twhile (fsg->state != FSG_STATE_TERMINATED) {\n+\t\tif (exception_in_progress(fsg) || signal_pending(current)) {\n+\t\t\thandle_exception(fsg);\n+\t\t\tcontinue;\n+\t\t}\n+\n+\t\tif (!fsg->running) {\n+\t\t\tsleep_thread(fsg);\n+\t\t\tcontinue;\n+\t\t}\n+\n+\t\tif (get_next_command(fsg))\n+\t\t\tcontinue;\n+\n+\t\tspin_lock_irq(&fsg->lock);\n+\t\tif (!exception_in_progress(fsg))\n+\t\t\tfsg->state = FSG_STATE_DATA_PHASE;\n+\t\tspin_unlock_irq(&fsg->lock);\n+\n+\t\tif (do_scsi_command(fsg) || finish_reply(fsg))\n+\t\t\tcontinue;\n+\n+\t\tspin_lock_irq(&fsg->lock);\n+\t\tif (!exception_in_progress(fsg))\n+\t\t\tfsg->state = FSG_STATE_STATUS_PHASE;\n+\t\tspin_unlock_irq(&fsg->lock);\n+\n+\t\tif (send_status(fsg))\n+\t\t\tcontinue;\n+\n+\t\tspin_lock_irq(&fsg->lock);\n+\t\tif (!exception_in_progress(fsg))\n+\t\t\tfsg->state = FSG_STATE_IDLE;\n+\t\tspin_unlock_irq(&fsg->lock);\n+\t\t}\n+\n+\tspin_lock_irq(&fsg->lock);\n+\tfsg->thread_task = NULL;\n+\tspin_unlock_irq(&fsg->lock);\n+\n+\t/* If we are exiting because of a signal, unregister the\n+\t * gadget driver. */\n+\tif (test_and_clear_bit(REGISTERED, &fsg->atomic_bitflags))\n+\t\tusb_gadget_unregister_driver(&fsg_driver);\n+\n+\t/* Let the unbind and cleanup routines know the thread has exited */\n+\tcomplete_and_exit(&fsg->thread_notifier, 0);\n+}\n+\n+\n+/*-------------------------------------------------------------------------*/\n+\n+\n+/* The write permissions and store_xxx pointers are set in fsg_bind() */\n+static DEVICE_ATTR(ro, 0444, fsg_show_ro, NULL);\n+static DEVICE_ATTR(nofua, 0644, fsg_show_nofua, NULL);\n+static DEVICE_ATTR(file, 0444, fsg_show_file, NULL);\n+\n+\n+/*-------------------------------------------------------------------------*/\n+\n+static void fsg_release(struct kref *ref)\n+{\n+\tstruct fsg_dev\t*fsg = container_of(ref, struct fsg_dev, ref);\n+\n+\tkfree(fsg->luns);\n+\tkfree(fsg);\n+}\n+\n+static void lun_release(struct device *dev)\n+{\n+\tstruct rw_semaphore\t*filesem = dev_get_drvdata(dev);\n+\tstruct fsg_dev\t\t*fsg =\n+\t\tcontainer_of(filesem, struct fsg_dev, filesem);\n+\n+\tkref_put(&fsg->ref, fsg_release);\n+}\n+\n+static void /* __init_or_exit */ fsg_unbind(struct usb_gadget *gadget)\n+{\n+\tstruct fsg_dev\t\t*fsg = get_gadget_data(gadget);\n+\tint\t\t\ti;\n+\tstruct fsg_lun\t\t*curlun;\n+\tstruct usb_request\t*req = fsg->ep0req;\n+\n+\tDBG(fsg, \"unbind\\n\");\n+\tclear_bit(REGISTERED, &fsg->atomic_bitflags);\n+\n+\t/* If the thread isn't already dead, tell it to exit now */\n+\tif (fsg->state != FSG_STATE_TERMINATED) {\n+\t\traise_exception(fsg, FSG_STATE_EXIT);\n+\t\twait_for_completion(&fsg->thread_notifier);\n+\n+\t\t/* The cleanup routine waits for this completion also */\n+\t\tcomplete(&fsg->thread_notifier);\n+\t}\n+\n+\t/* Unregister the sysfs attribute files and the LUNs */\n+\tfor (i = 0; i < fsg->nluns; ++i) {\n+\t\tcurlun = &fsg->luns[i];\n+\t\tif (curlun->registered) {\n+\t\t\tdevice_remove_file(&curlun->dev, &dev_attr_nofua);\n+\t\t\tdevice_remove_file(&curlun->dev, &dev_attr_ro);\n+\t\t\tdevice_remove_file(&curlun->dev, &dev_attr_file);\n+\t\t\tfsg_lun_close(curlun);\n+\t\t\tdevice_unregister(&curlun->dev);\n+\t\t\tcurlun->registered = 0;\n+\t\t}\n+\t}\n+\n+\t/* Free the data buffers */\n+\tfor (i = 0; i < fsg_num_buffers; ++i)\n+\t\tkfree(fsg->buffhds[i].buf);\n+\n+\t/* Free the request and buffer for endpoint 0 */\n+\tif (req) {\n+\t\tkfree(req->buf);\n+\t\tusb_ep_free_request(fsg->ep0, req);\n+\t}\n+\n+\tset_gadget_data(gadget, NULL);\n+}\n+\n+\n+static int __init check_parameters(struct fsg_dev *fsg)\n+{\n+\tint\tprot;\n+\tint\tgcnum;\n+\n+\t/* Store the default values */\n+\tmod_data.transport_type = USB_PR_BULK;\n+\tmod_data.transport_name = \"Bulk-only\";\n+\tmod_data.protocol_type = USB_SC_SCSI;\n+\tmod_data.protocol_name = \"Transparent SCSI\";\n+\n+\t/* Some peripheral controllers are known not to be able to\n+\t * halt bulk endpoints correctly.  If one of them is present,\n+\t * disable stalls.\n+\t */\n+\tif (gadget_is_at91(fsg->gadget))\n+\t\tmod_data.can_stall = 0;\n+\n+\tif (mod_data.release == 0xffff) {\t// Parameter wasn't set\n+\t\tgcnum = usb_gadget_controller_number(fsg->gadget);\n+\t\tif (gcnum >= 0)\n+\t\t\tmod_data.release = 0x0300 + gcnum;\n+\t\telse {\n+\t\t\tWARNING(fsg, \"controller '%s' not recognized\\n\",\n+\t\t\t\tfsg->gadget->name);\n+\t\t\tmod_data.release = 0x0399;\n+\t\t}\n+\t}\n+\n+\tprot = simple_strtol(mod_data.protocol_parm, NULL, 0);\n+\n+#ifdef CONFIG_USB_FILE_STORAGE_TEST\n+\tif (strnicmp(mod_data.transport_parm, \"BBB\", 10) == 0) {\n+\t\t;\t\t// Use default setting\n+\t} else if (strnicmp(mod_data.transport_parm, \"CB\", 10) == 0) {\n+\t\tmod_data.transport_type = USB_PR_CB;\n+\t\tmod_data.transport_name = \"Control-Bulk\";\n+\t} else if (strnicmp(mod_data.transport_parm, \"CBI\", 10) == 0) {\n+\t\tmod_data.transport_type = USB_PR_CBI;\n+\t\tmod_data.transport_name = \"Control-Bulk-Interrupt\";\n+\t} else {\n+\t\tERROR(fsg, \"invalid transport: %s\\n\", mod_data.transport_parm);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (strnicmp(mod_data.protocol_parm, \"SCSI\", 10) == 0 ||\n+\t\t\tprot == USB_SC_SCSI) {\n+\t\t;\t\t// Use default setting\n+\t} else if (strnicmp(mod_data.protocol_parm, \"RBC\", 10) == 0 ||\n+\t\t\tprot == USB_SC_RBC) {\n+\t\tmod_data.protocol_type = USB_SC_RBC;\n+\t\tmod_data.protocol_name = \"RBC\";\n+\t} else if (strnicmp(mod_data.protocol_parm, \"8020\", 4) == 0 ||\n+\t\t\tstrnicmp(mod_data.protocol_parm, \"ATAPI\", 10) == 0 ||\n+\t\t\tprot == USB_SC_8020) {\n+\t\tmod_data.protocol_type = USB_SC_8020;\n+\t\tmod_data.protocol_name = \"8020i (ATAPI)\";\n+\t} else if (strnicmp(mod_data.protocol_parm, \"QIC\", 3) == 0 ||\n+\t\t\tprot == USB_SC_QIC) {\n+\t\tmod_data.protocol_type = USB_SC_QIC;\n+\t\tmod_data.protocol_name = \"QIC-157\";\n+\t} else if (strnicmp(mod_data.protocol_parm, \"UFI\", 10) == 0 ||\n+\t\t\tprot == USB_SC_UFI) {\n+\t\tmod_data.protocol_type = USB_SC_UFI;\n+\t\tmod_data.protocol_name = \"UFI\";\n+\t} else if (strnicmp(mod_data.protocol_parm, \"8070\", 4) == 0 ||\n+\t\t\tprot == USB_SC_8070) {\n+\t\tmod_data.protocol_type = USB_SC_8070;\n+\t\tmod_data.protocol_name = \"8070i\";\n+\t} else {\n+\t\tERROR(fsg, \"invalid protocol: %s\\n\", mod_data.protocol_parm);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tmod_data.buflen &= PAGE_CACHE_MASK;\n+\tif (mod_data.buflen <= 0) {\n+\t\tERROR(fsg, \"invalid buflen\\n\");\n+\t\treturn -ETOOSMALL;\n+\t}\n+\n+#endif /* CONFIG_USB_FILE_STORAGE_TEST */\n+\n+\t/* Serial string handling.\n+\t * On a real device, the serial string would be loaded\n+\t * from permanent storage. */\n+\tif (mod_data.serial) {\n+\t\tconst char *ch;\n+\t\tunsigned len = 0;\n+\n+\t\t/* Sanity check :\n+\t\t * The CB[I] specification limits the serial string to\n+\t\t * 12 uppercase hexadecimal characters.\n+\t\t * BBB need at least 12 uppercase hexadecimal characters,\n+\t\t * with a maximum of 126. */\n+\t\tfor (ch = mod_data.serial; *ch; ++ch) {\n+\t\t\t++len;\n+\t\t\tif ((*ch < '0' || *ch > '9') &&\n+\t\t\t    (*ch < 'A' || *ch > 'F')) { /* not uppercase hex */\n+\t\t\t\tWARNING(fsg,\n+\t\t\t\t\t\"Invalid serial string character: %c\\n\",\n+\t\t\t\t\t*ch);\n+\t\t\t\tgoto no_serial;\n+\t\t\t}\n+\t\t}\n+\t\tif (len > 126 ||\n+\t\t    (mod_data.transport_type == USB_PR_BULK && len < 12) ||\n+\t\t    (mod_data.transport_type != USB_PR_BULK && len > 12)) {\n+\t\t\tWARNING(fsg, \"Invalid serial string length!\\n\");\n+\t\t\tgoto no_serial;\n+\t\t}\n+\t\tfsg_strings[FSG_STRING_SERIAL - 1].s = mod_data.serial;\n+\t} else {\n+\t\tWARNING(fsg, \"No serial-number string provided!\\n\");\n+ no_serial:\n+\t\tdevice_desc.iSerialNumber = 0;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+\n+static int __init fsg_bind(struct usb_gadget *gadget)\n+{\n+\tstruct fsg_dev\t\t*fsg = the_fsg;\n+\tint\t\t\trc;\n+\tint\t\t\ti;\n+\tstruct fsg_lun\t\t*curlun;\n+\tstruct usb_ep\t\t*ep;\n+\tstruct usb_request\t*req;\n+\tchar\t\t\t*pathbuf, *p;\n+\n+\tfsg->gadget = gadget;\n+\tset_gadget_data(gadget, fsg);\n+\tfsg->ep0 = gadget->ep0;\n+\tfsg->ep0->driver_data = fsg;\n+\n+\tif ((rc = check_parameters(fsg)) != 0)\n+\t\tgoto out;\n+\n+\tif (mod_data.removable) {\t// Enable the store_xxx attributes\n+\t\tdev_attr_file.attr.mode = 0644;\n+\t\tdev_attr_file.store = fsg_store_file;\n+\t\tif (!mod_data.cdrom) {\n+\t\t\tdev_attr_ro.attr.mode = 0644;\n+\t\t\tdev_attr_ro.store = fsg_store_ro;\n+\t\t}\n+\t}\n+\n+\t/* Only for removable media? */\n+\tdev_attr_nofua.attr.mode = 0644;\n+\tdev_attr_nofua.store = fsg_store_nofua;\n+\n+\t/* Find out how many LUNs there should be */\n+\ti = mod_data.nluns;\n+\tif (i == 0)\n+\t\ti = max(mod_data.num_filenames, 1u);\n+\tif (i > FSG_MAX_LUNS) {\n+\t\tERROR(fsg, \"invalid number of LUNs: %d\\n\", i);\n+\t\trc = -EINVAL;\n+\t\tgoto out;\n+\t}\n+\n+\t/* Create the LUNs, open their backing files, and register the\n+\t * LUN devices in sysfs. */\n+\tfsg->luns = kzalloc(i * sizeof(struct fsg_lun), GFP_KERNEL);\n+\tif (!fsg->luns) {\n+\t\trc = -ENOMEM;\n+\t\tgoto out;\n+\t}\n+\tfsg->nluns = i;\n+\n+\tfor (i = 0; i < fsg->nluns; ++i) {\n+\t\tcurlun = &fsg->luns[i];\n+\t\tcurlun->cdrom = !!mod_data.cdrom;\n+\t\tcurlun->ro = mod_data.cdrom || mod_data.ro[i];\n+\t\tcurlun->initially_ro = curlun->ro;\n+\t\tcurlun->removable = mod_data.removable;\n+\t\tcurlun->nofua = mod_data.nofua[i];\n+\t\tcurlun->dev.release = lun_release;\n+\t\tcurlun->dev.parent = &gadget->dev;\n+\t\tcurlun->dev.driver = &fsg_driver.driver;\n+\t\tdev_set_drvdata(&curlun->dev, &fsg->filesem);\n+\t\tdev_set_name(&curlun->dev,\"%s-lun%d\",\n+\t\t\t     dev_name(&gadget->dev), i);\n+\n+\t\tkref_get(&fsg->ref);\n+\t\trc = device_register(&curlun->dev);\n+\t\tif (rc) {\n+\t\t\tINFO(fsg, \"failed to register LUN%d: %d\\n\", i, rc);\n+\t\t\tput_device(&curlun->dev);\n+\t\t\tgoto out;\n+\t\t}\n+\t\tcurlun->registered = 1;\n+\n+\t\trc = device_create_file(&curlun->dev, &dev_attr_ro);\n+\t\tif (rc)\n+\t\t\tgoto out;\n+\t\trc = device_create_file(&curlun->dev, &dev_attr_nofua);\n+\t\tif (rc)\n+\t\t\tgoto out;\n+\t\trc = device_create_file(&curlun->dev, &dev_attr_file);\n+\t\tif (rc)\n+\t\t\tgoto out;\n+\n+\t\tif (mod_data.file[i] && *mod_data.file[i]) {\n+\t\t\trc = fsg_lun_open(curlun, mod_data.file[i]);\n+\t\t\tif (rc)\n+\t\t\t\tgoto out;\n+\t\t} else if (!mod_data.removable) {\n+\t\t\tERROR(fsg, \"no file given for LUN%d\\n\", i);\n+\t\t\trc = -EINVAL;\n+\t\t\tgoto out;\n+\t\t}\n+\t}\n+\n+\t/* Find all the endpoints we will use */\n+\tusb_ep_autoconfig_reset(gadget);\n+\tep = usb_ep_autoconfig(gadget, &fsg_fs_bulk_in_desc);\n+\tif (!ep)\n+\t\tgoto autoconf_fail;\n+\tep->driver_data = fsg;\t\t// claim the endpoint\n+\tfsg->bulk_in = ep;\n+\n+\tep = usb_ep_autoconfig(gadget, &fsg_fs_bulk_out_desc);\n+\tif (!ep)\n+\t\tgoto autoconf_fail;\n+\tep->driver_data = fsg;\t\t// claim the endpoint\n+\tfsg->bulk_out = ep;\n+\n+\tif (transport_is_cbi()) {\n+\t\tep = usb_ep_autoconfig(gadget, &fsg_fs_intr_in_desc);\n+\t\tif (!ep)\n+\t\t\tgoto autoconf_fail;\n+\t\tep->driver_data = fsg;\t\t// claim the endpoint\n+\t\tfsg->intr_in = ep;\n+\t}\n+\n+\t/* Fix up the descriptors */\n+\tdevice_desc.idVendor = cpu_to_le16(mod_data.vendor);\n+\tdevice_desc.idProduct = cpu_to_le16(mod_data.product);\n+\tdevice_desc.bcdDevice = cpu_to_le16(mod_data.release);\n+\n+\ti = (transport_is_cbi() ? 3 : 2);\t// Number of endpoints\n+\tfsg_intf_desc.bNumEndpoints = i;\n+\tfsg_intf_desc.bInterfaceSubClass = mod_data.protocol_type;\n+\tfsg_intf_desc.bInterfaceProtocol = mod_data.transport_type;\n+\tfsg_fs_function[i + FSG_FS_FUNCTION_PRE_EP_ENTRIES] = NULL;\n+\n+\tif (gadget_is_dualspeed(gadget)) {\n+\t\tfsg_hs_function[i + FSG_HS_FUNCTION_PRE_EP_ENTRIES] = NULL;\n+\n+\t\t/* Assume endpoint addresses are the same for both speeds */\n+\t\tfsg_hs_bulk_in_desc.bEndpointAddress =\n+\t\t\tfsg_fs_bulk_in_desc.bEndpointAddress;\n+\t\tfsg_hs_bulk_out_desc.bEndpointAddress =\n+\t\t\tfsg_fs_bulk_out_desc.bEndpointAddress;\n+\t\tfsg_hs_intr_in_desc.bEndpointAddress =\n+\t\t\tfsg_fs_intr_in_desc.bEndpointAddress;\n+\t}\n+\n+\tif (gadget_is_superspeed(gadget)) {\n+\t\tunsigned\t\tmax_burst;\n+\n+\t\tfsg_ss_function[i + FSG_SS_FUNCTION_PRE_EP_ENTRIES] = NULL;\n+\n+\t\t/* Calculate bMaxBurst, we know packet size is 1024 */\n+\t\tmax_burst = min_t(unsigned, mod_data.buflen / 1024, 15);\n+\n+\t\t/* Assume endpoint addresses are the same for both speeds */\n+\t\tfsg_ss_bulk_in_desc.bEndpointAddress =\n+\t\t\tfsg_fs_bulk_in_desc.bEndpointAddress;\n+\t\tfsg_ss_bulk_in_comp_desc.bMaxBurst = max_burst;\n+\n+\t\tfsg_ss_bulk_out_desc.bEndpointAddress =\n+\t\t\tfsg_fs_bulk_out_desc.bEndpointAddress;\n+\t\tfsg_ss_bulk_out_comp_desc.bMaxBurst = max_burst;\n+\t}\n+\n+\tif (gadget_is_otg(gadget))\n+\t\tfsg_otg_desc.bmAttributes |= USB_OTG_HNP;\n+\n+\trc = -ENOMEM;\n+\n+\t/* Allocate the request and buffer for endpoint 0 */\n+\tfsg->ep0req = req = usb_ep_alloc_request(fsg->ep0, GFP_KERNEL);\n+\tif (!req)\n+\t\tgoto out;\n+\treq->buf = kmalloc(EP0_BUFSIZE, GFP_KERNEL);\n+\tif (!req->buf)\n+\t\tgoto out;\n+\treq->complete = ep0_complete;\n+\n+\t/* Allocate the data buffers */\n+\tfor (i = 0; i < fsg_num_buffers; ++i) {\n+\t\tstruct fsg_buffhd\t*bh = &fsg->buffhds[i];\n+\n+\t\t/* Allocate for the bulk-in endpoint.  We assume that\n+\t\t * the buffer will also work with the bulk-out (and\n+\t\t * interrupt-in) endpoint. */\n+\t\tbh->buf = kmalloc(mod_data.buflen, GFP_KERNEL);\n+\t\tif (!bh->buf)\n+\t\t\tgoto out;\n+\t\tbh->next = bh + 1;\n+\t}\n+\tfsg->buffhds[fsg_num_buffers - 1].next = &fsg->buffhds[0];\n+\n+\t/* This should reflect the actual gadget power source */\n+\tusb_gadget_set_selfpowered(gadget);\n+\n+\tsnprintf(fsg_string_manufacturer, sizeof fsg_string_manufacturer,\n+\t\t\t\"%s %s with %s\",\n+\t\t\tinit_utsname()->sysname, init_utsname()->release,\n+\t\t\tgadget->name);\n+\n+\tfsg->thread_task = kthread_create(fsg_main_thread, fsg,\n+\t\t\t\"file-storage-gadget\");\n+\tif (IS_ERR(fsg->thread_task)) {\n+\t\trc = PTR_ERR(fsg->thread_task);\n+\t\tgoto out;\n+\t}\n+\n+\tINFO(fsg, DRIVER_DESC \", version: \" DRIVER_VERSION \"\\n\");\n+\tINFO(fsg, \"NOTE: This driver is deprecated.  \"\n+\t\t\t\"Consider using g_mass_storage instead.\\n\");\n+\tINFO(fsg, \"Number of LUNs=%d\\n\", fsg->nluns);\n+\n+\tpathbuf = kmalloc(PATH_MAX, GFP_KERNEL);\n+\tfor (i = 0; i < fsg->nluns; ++i) {\n+\t\tcurlun = &fsg->luns[i];\n+\t\tif (fsg_lun_is_open(curlun)) {\n+\t\t\tp = NULL;\n+\t\t\tif (pathbuf) {\n+\t\t\t\tp = d_path(&curlun->filp->f_path,\n+\t\t\t\t\t   pathbuf, PATH_MAX);\n+\t\t\t\tif (IS_ERR(p))\n+\t\t\t\t\tp = NULL;\n+\t\t\t}\n+\t\t\tLINFO(curlun, \"ro=%d, nofua=%d, file: %s\\n\",\n+\t\t\t      curlun->ro, curlun->nofua, (p ? p : \"(error)\"));\n+\t\t}\n+\t}\n+\tkfree(pathbuf);\n+\n+\tDBG(fsg, \"transport=%s (x%02x)\\n\",\n+\t\t\tmod_data.transport_name, mod_data.transport_type);\n+\tDBG(fsg, \"protocol=%s (x%02x)\\n\",\n+\t\t\tmod_data.protocol_name, mod_data.protocol_type);\n+\tDBG(fsg, \"VendorID=x%04x, ProductID=x%04x, Release=x%04x\\n\",\n+\t\t\tmod_data.vendor, mod_data.product, mod_data.release);\n+\tDBG(fsg, \"removable=%d, stall=%d, cdrom=%d, buflen=%u\\n\",\n+\t\t\tmod_data.removable, mod_data.can_stall,\n+\t\t\tmod_data.cdrom, mod_data.buflen);\n+\tDBG(fsg, \"I/O thread pid: %d\\n\", task_pid_nr(fsg->thread_task));\n+\n+\tset_bit(REGISTERED, &fsg->atomic_bitflags);\n+\n+\t/* Tell the thread to start working */\n+\twake_up_process(fsg->thread_task);\n+\treturn 0;\n+\n+autoconf_fail:\n+\tERROR(fsg, \"unable to autoconfigure all endpoints\\n\");\n+\trc = -ENOTSUPP;\n+\n+out:\n+\tfsg->state = FSG_STATE_TERMINATED;\t// The thread is dead\n+\tfsg_unbind(gadget);\n+\tcomplete(&fsg->thread_notifier);\n+\treturn rc;\n+}\n+\n+\n+/*-------------------------------------------------------------------------*/\n+\n+static void fsg_suspend(struct usb_gadget *gadget)\n+{\n+\tstruct fsg_dev\t\t*fsg = get_gadget_data(gadget);\n+\n+\tDBG(fsg, \"suspend\\n\");\n+\tset_bit(SUSPENDED, &fsg->atomic_bitflags);\n+}\n+\n+static void fsg_resume(struct usb_gadget *gadget)\n+{\n+\tstruct fsg_dev\t\t*fsg = get_gadget_data(gadget);\n+\n+\tDBG(fsg, \"resume\\n\");\n+\tclear_bit(SUSPENDED, &fsg->atomic_bitflags);\n+}\n+\n+\n+/*-------------------------------------------------------------------------*/\n+\n+static struct usb_gadget_driver\t\tfsg_driver = {\n+\t.max_speed\t= USB_SPEED_SUPER,\n+\t.function\t= (char *) fsg_string_product,\n+\t.unbind\t\t= fsg_unbind,\n+\t.disconnect\t= fsg_disconnect,\n+\t.setup\t\t= fsg_setup,\n+\t.suspend\t= fsg_suspend,\n+\t.resume\t\t= fsg_resume,\n+\n+\t.driver\t\t= {\n+\t\t.name\t\t= DRIVER_NAME,\n+\t\t.owner\t\t= THIS_MODULE,\n+\t\t// .release = ...\n+\t\t// .suspend = ...\n+\t\t// .resume = ...\n+\t},\n+};\n+\n+\n+static int __init fsg_alloc(void)\n+{\n+\tstruct fsg_dev\t\t*fsg;\n+\n+\tfsg = kzalloc(sizeof *fsg +\n+\t\t      fsg_num_buffers * sizeof *(fsg->buffhds), GFP_KERNEL);\n+\n+\tif (!fsg)\n+\t\treturn -ENOMEM;\n+\tspin_lock_init(&fsg->lock);\n+\tinit_rwsem(&fsg->filesem);\n+\tkref_init(&fsg->ref);\n+\tinit_completion(&fsg->thread_notifier);\n+\n+\tthe_fsg = fsg;\n+\treturn 0;\n+}\n+\n+\n+static int __init fsg_init(void)\n+{\n+\tint\t\trc;\n+\tstruct fsg_dev\t*fsg;\n+\n+\trc = fsg_num_buffers_validate();\n+\tif (rc != 0)\n+\t\treturn rc;\n+\n+\tif ((rc = fsg_alloc()) != 0)\n+\t\treturn rc;\n+\tfsg = the_fsg;\n+\tif ((rc = usb_gadget_probe_driver(&fsg_driver, fsg_bind)) != 0)\n+\t\tkref_put(&fsg->ref, fsg_release);\n+\treturn rc;\n+}\n+module_init(fsg_init);\n+\n+\n+static void __exit fsg_cleanup(void)\n+{\n+\tstruct fsg_dev\t*fsg = the_fsg;\n+\n+\t/* Unregister the driver iff the thread hasn't already done so */\n+\tif (test_and_clear_bit(REGISTERED, &fsg->atomic_bitflags))\n+\t\tusb_gadget_unregister_driver(&fsg_driver);\n+\n+\t/* Wait for the thread to finish up */\n+\twait_for_completion(&fsg->thread_notifier);\n+\n+\tkref_put(&fsg->ref, fsg_release);\n+}\n+module_exit(fsg_cleanup);\n--- a/drivers/usb/host/Kconfig\n+++ b/drivers/usb/host/Kconfig\n@@ -741,6 +741,16 @@ config USB_RENESAS_USBHS_HCD\n \t  To compile this driver as a module, choose M here: the\n \t  module will be called renesas-usbhs.\n \n+config USB_DWCOTG\n+\tbool \"Synopsis DWC host support\"\n+\tdepends on USB && (FIQ || ARM64)\n+\thelp\n+\t  The Synopsis DWC controller is a dual-role\n+\t  host/peripheral/OTG (\"On The Go\") USB controllers.\n+\n+\t  Enable this option to support this IP in host controller mode.\n+\t  If unsure, say N.\n+\n config USB_IMX21_HCD\n \ttristate \"i.MX21 HCD support\"\n \tdepends on ARM && ARCH_MXC\n--- a/drivers/usb/host/Makefile\n+++ b/drivers/usb/host/Makefile\n@@ -81,6 +81,7 @@ obj-$(CONFIG_USB_SL811_HCD)\t+= sl811-hcd\n obj-$(CONFIG_USB_SL811_CS)\t+= sl811_cs.o\n obj-$(CONFIG_USB_U132_HCD)\t+= u132-hcd.o\n obj-$(CONFIG_USB_R8A66597_HCD)\t+= r8a66597-hcd.o\n+obj-$(CONFIG_USB_DWCOTG)        += dwc_otg/ dwc_common_port/\n obj-$(CONFIG_USB_IMX21_HCD)\t+= imx21-hcd.o\n obj-$(CONFIG_USB_FSL_USB2)\t+= fsl-mph-dr-of.o\n obj-$(CONFIG_USB_EHCI_FSL)\t+= fsl-mph-dr-of.o\n--- /dev/null\n+++ b/drivers/usb/host/dwc_common_port/Makefile\n@@ -0,0 +1,58 @@\n+#\n+# Makefile for DWC_common library\n+#\n+\n+ifneq ($(KERNELRELEASE),)\n+\n+ccflags-y\t+= -DDWC_LINUX\n+#ccflags-y\t+= -DDEBUG\n+#ccflags-y\t+= -DDWC_DEBUG_REGS\n+#ccflags-y\t+= -DDWC_DEBUG_MEMORY\n+\n+ccflags-y\t+= -DDWC_LIBMODULE\n+ccflags-y\t+= -DDWC_CCLIB\n+#ccflags-y\t+= -DDWC_CRYPTOLIB\n+ccflags-y\t+= -DDWC_NOTIFYLIB\n+ccflags-y\t+= -DDWC_UTFLIB\n+\n+obj-$(CONFIG_USB_DWCOTG)\t+= dwc_common_port_lib.o\n+dwc_common_port_lib-objs := dwc_cc.o dwc_modpow.o dwc_dh.o \\\n+\t\t\t    dwc_crypto.o dwc_notifier.o \\\n+\t\t\t    dwc_common_linux.o dwc_mem.o\n+\n+kernrelwd := $(subst ., ,$(KERNELRELEASE))\n+kernrel3 := $(word 1,$(kernrelwd)).$(word 2,$(kernrelwd)).$(word 3,$(kernrelwd))\n+\n+ifneq ($(kernrel3),2.6.20)\n+# grayg - I only know that we use ccflags-y in 2.6.31 actually\n+ccflags-y += $(CPPFLAGS)\n+endif\n+\n+else\n+\n+#ifeq ($(KDIR),)\n+#$(error Must give \"KDIR=/path/to/kernel/source\" on command line or in environment)\n+#endif\n+\n+ifeq ($(ARCH),)\n+$(error Must give \"ARCH=<arch>\" on command line or in environment. Also, if \\\n+ cross-compiling, must give \"CROSS_COMPILE=/path/to/compiler/plus/tool-prefix-\")\n+endif\n+\n+ifeq ($(DOXYGEN),)\n+DOXYGEN\t\t:= doxygen\n+endif\n+\n+default:\n+\t$(MAKE) -C$(KDIR) M=$(PWD) ARCH=$(ARCH) CROSS_COMPILE=$(CROSS_COMPILE) modules\n+\n+docs:\t$(wildcard *.[hc]) doc/doxygen.cfg\n+\t$(DOXYGEN) doc/doxygen.cfg\n+\n+tags:\t$(wildcard *.[hc])\n+\t$(CTAGS) -e $(wildcard *.[hc]) $(wildcard linux/*.[hc]) $(wildcard $(KDIR)/include/linux/usb*.h)\n+\n+endif\n+\n+clean:\n+\trm -rf *.o *.ko .*.cmd *.mod.c .*.o.d .*.o.tmp modules.order Module.markers Module.symvers .tmp_versions/\n--- /dev/null\n+++ b/drivers/usb/host/dwc_common_port/Makefile.fbsd\n@@ -0,0 +1,17 @@\n+CFLAGS\t+= -I/sys/i386/compile/GENERIC -I/sys/i386/include -I/usr/include\n+CFLAGS\t+= -DDWC_FREEBSD\n+CFLAGS\t+= -DDEBUG\n+#CFLAGS\t+= -DDWC_DEBUG_REGS\n+#CFLAGS\t+= -DDWC_DEBUG_MEMORY\n+\n+#CFLAGS\t+= -DDWC_LIBMODULE\n+#CFLAGS\t+= -DDWC_CCLIB\n+#CFLAGS\t+= -DDWC_CRYPTOLIB\n+#CFLAGS\t+= -DDWC_NOTIFYLIB\n+#CFLAGS\t+= -DDWC_UTFLIB\n+\n+KMOD = dwc_common_port_lib\n+SRCS = dwc_cc.c dwc_modpow.c dwc_dh.c dwc_crypto.c dwc_notifier.c \\\n+       dwc_common_fbsd.c dwc_mem.c\n+\n+.include <bsd.kmod.mk>\n--- /dev/null\n+++ b/drivers/usb/host/dwc_common_port/Makefile.linux\n@@ -0,0 +1,49 @@\n+#\n+# Makefile for DWC_common library\n+#\n+ifneq ($(KERNELRELEASE),)\n+\n+ccflags-y\t+= -DDWC_LINUX\n+#ccflags-y\t+= -DDEBUG\n+#ccflags-y\t+= -DDWC_DEBUG_REGS\n+#ccflags-y\t+= -DDWC_DEBUG_MEMORY\n+\n+ccflags-y\t+= -DDWC_LIBMODULE\n+ccflags-y\t+= -DDWC_CCLIB\n+ccflags-y\t+= -DDWC_CRYPTOLIB\n+ccflags-y\t+= -DDWC_NOTIFYLIB\n+ccflags-y\t+= -DDWC_UTFLIB\n+\n+obj-m\t\t\t := dwc_common_port_lib.o\n+dwc_common_port_lib-objs := dwc_cc.o dwc_modpow.o dwc_dh.o \\\n+\t\t\t    dwc_crypto.o dwc_notifier.o \\\n+\t\t\t    dwc_common_linux.o dwc_mem.o\n+\n+else\n+\n+ifeq ($(KDIR),)\n+$(error Must give \"KDIR=/path/to/kernel/source\" on command line or in environment)\n+endif\n+\n+ifeq ($(ARCH),)\n+$(error Must give \"ARCH=<arch>\" on command line or in environment. Also, if \\\n+ cross-compiling, must give \"CROSS_COMPILE=/path/to/compiler/plus/tool-prefix-\")\n+endif\n+\n+ifeq ($(DOXYGEN),)\n+DOXYGEN\t\t:= doxygen\n+endif\n+\n+default:\n+\t$(MAKE) -C$(KDIR) M=$(PWD) ARCH=$(ARCH) CROSS_COMPILE=$(CROSS_COMPILE) modules\n+\n+docs:\t$(wildcard *.[hc]) doc/doxygen.cfg\n+\t$(DOXYGEN) doc/doxygen.cfg\n+\n+tags:\t$(wildcard *.[hc])\n+\t$(CTAGS) -e $(wildcard *.[hc]) $(wildcard linux/*.[hc]) $(wildcard $(KDIR)/include/linux/usb*.h)\n+\n+endif\n+\n+clean:\n+\trm -rf *.o *.ko .*.cmd *.mod.c .*.o.d .*.o.tmp modules.order Module.markers Module.symvers .tmp_versions/\n--- /dev/null\n+++ b/drivers/usb/host/dwc_common_port/changes.txt\n@@ -0,0 +1,174 @@\n+\n+dwc_read_reg32() and friends now take an additional parameter, a pointer to an\n+IO context struct. The IO context struct should live in an os-dependent struct\n+in your driver. As an example, the dwc_usb3 driver has an os-dependent struct\n+named 'os_dep' embedded in the main device struct. So there these calls look\n+like this:\n+\n+\tdwc_read_reg32(&usb3_dev->os_dep.ioctx, &pcd->dev_global_regs->dcfg);\n+\n+\tdwc_write_reg32(&usb3_dev->os_dep.ioctx,\n+\t\t\t&pcd->dev_global_regs->dcfg, 0);\n+\n+Note that for the existing Linux driver ports, it is not necessary to actually\n+define the 'ioctx' member in the os-dependent struct. Since Linux does not\n+require an IO context, its macros for dwc_read_reg32() and friends do not\n+use the context pointer, so it is optimized away by the compiler. But it is\n+necessary to add the pointer parameter to all of the call sites, to be ready\n+for any future ports (such as FreeBSD) which do require an IO context.\n+\n+\n+Similarly, dwc_alloc(), dwc_alloc_atomic(), dwc_strdup(), and dwc_free() now\n+take an additional parameter, a pointer to a memory context. Examples:\n+\n+\taddr = dwc_alloc(&usb3_dev->os_dep.memctx, size);\n+\n+\tdwc_free(&usb3_dev->os_dep.memctx, addr);\n+\n+Again, for the Linux ports, it is not necessary to actually define the memctx\n+member, but it is necessary to add the pointer parameter to all of the call\n+sites.\n+\n+\n+Same for dwc_dma_alloc() and dwc_dma_free(). Examples:\n+\n+\tvirt_addr = dwc_dma_alloc(&usb3_dev->os_dep.dmactx, size, &phys_addr);\n+\n+\tdwc_dma_free(&usb3_dev->os_dep.dmactx, size, virt_addr, phys_addr);\n+\n+\n+Same for dwc_mutex_alloc() and dwc_mutex_free(). Examples:\n+\n+\tmutex = dwc_mutex_alloc(&usb3_dev->os_dep.mtxctx);\n+\n+\tdwc_mutex_free(&usb3_dev->os_dep.mtxctx, mutex);\n+\n+\n+Same for dwc_spinlock_alloc() and dwc_spinlock_free(). Examples:\n+\n+\tlock = dwc_spinlock_alloc(&usb3_dev->osdep.splctx);\n+\n+\tdwc_spinlock_free(&usb3_dev->osdep.splctx, lock);\n+\n+\n+Same for dwc_timer_alloc(). Example:\n+\n+\ttimer = dwc_timer_alloc(&usb3_dev->os_dep.tmrctx, \"dwc_usb3_tmr1\",\n+\t\t\t\tcb_func, cb_data);\n+\n+\n+Same for dwc_waitq_alloc(). Example:\n+\n+\twaitq = dwc_waitq_alloc(&usb3_dev->os_dep.wtqctx);\n+\n+\n+Same for dwc_thread_run(). Example:\n+\n+\tthread = dwc_thread_run(&usb3_dev->os_dep.thdctx, func,\n+\t\t\t\t\"dwc_usb3_thd1\", data);\n+\n+\n+Same for dwc_workq_alloc(). Example:\n+\n+\tworkq = dwc_workq_alloc(&usb3_dev->osdep.wkqctx, \"dwc_usb3_wkq1\");\n+\n+\n+Same for dwc_task_alloc(). Example:\n+\n+\ttask = dwc_task_alloc(&usb3_dev->os_dep.tskctx, \"dwc_usb3_tsk1\",\n+\t\t\t      cb_func, cb_data);\n+\n+\n+In addition to the context pointer additions, a few core functions have had\n+other changes made to their parameters:\n+\n+The 'flags' parameter to dwc_spinlock_irqsave() and dwc_spinunlock_irqrestore()\n+has been changed from a uint64_t to a dwc_irqflags_t.\n+\n+dwc_thread_should_stop() now takes a 'dwc_thread_t *' parameter, because the\n+FreeBSD equivalent of that function requires it.\n+\n+And, in addition to the context pointer, dwc_task_alloc() also adds a\n+'char *name' parameter, to be consistent with dwc_thread_run() and\n+dwc_workq_alloc(), and because the FreeBSD equivalent of that function\n+requires a unique name.\n+\n+\n+Here is a complete list of the core functions that now take a pointer to a\n+context as their first parameter:\n+\n+\tdwc_read_reg32\n+\tdwc_read_reg64\n+\tdwc_write_reg32\n+\tdwc_write_reg64\n+\tdwc_modify_reg32\n+\tdwc_modify_reg64\n+\tdwc_alloc\n+\tdwc_alloc_atomic\n+\tdwc_strdup\n+\tdwc_free\n+\tdwc_dma_alloc\n+\tdwc_dma_free\n+\tdwc_mutex_alloc\n+\tdwc_mutex_free\n+\tdwc_spinlock_alloc\n+\tdwc_spinlock_free\n+\tdwc_timer_alloc\n+\tdwc_waitq_alloc\n+\tdwc_thread_run\n+\tdwc_workq_alloc\n+\tdwc_task_alloc     Also adds a 'char *name' as its 2nd parameter\n+\n+And here are the core functions that have other changes to their parameters:\n+\n+\tdwc_spinlock_irqsave      'flags' param is now a 'dwc_irqflags_t *'\n+\tdwc_spinunlock_irqrestore 'flags' param is now a 'dwc_irqflags_t'\n+\tdwc_thread_should_stop    Adds a 'dwc_thread_t *' parameter\n+\n+\n+\n+The changes to the core functions also require some of the other library\n+functions to change:\n+\n+\tdwc_cc_if_alloc() and dwc_cc_if_free() now take a 'void *memctx'\n+\t(for memory allocation) as the 1st param and a 'void *mtxctx'\n+\t(for mutex allocation) as the 2nd param.\n+\n+\tdwc_cc_clear(), dwc_cc_add(), dwc_cc_change(), dwc_cc_remove(),\n+\tdwc_cc_data_for_save(), and dwc_cc_restore_from_data() now take a\n+\t'void *memctx' as the 1st param.\n+\n+\tdwc_dh_modpow(), dwc_dh_pk(), and dwc_dh_derive_keys() now take a\n+\t'void *memctx' as the 1st param.\n+\n+\tdwc_modpow() now takes a 'void *memctx' as the 1st param.\n+\n+\tdwc_alloc_notification_manager() now takes a 'void *memctx' as the\n+\t1st param and a 'void *wkqctx' (for work queue allocation) as the 2nd\n+\tparam, and also now returns an integer value that is non-zero if\n+\tallocation of its data structures or work queue fails.\n+\n+\tdwc_register_notifier() now takes a 'void *memctx' as the 1st param.\n+\n+\tdwc_memory_debug_start() now takes a 'void *mem_ctx' as the first\n+\tparam, and also now returns an integer value that is non-zero if\n+\tallocation of its data structures fails.\n+\n+\n+\n+Other miscellaneous changes:\n+\n+The DEBUG_MEMORY and DEBUG_REGS #define's have been renamed to\n+DWC_DEBUG_MEMORY and DWC_DEBUG_REGS.\n+\n+The following #define's have been added to allow selectively compiling library\n+features:\n+\n+\tDWC_CCLIB\n+\tDWC_CRYPTOLIB\n+\tDWC_NOTIFYLIB\n+\tDWC_UTFLIB\n+\n+A DWC_LIBMODULE #define has also been added. If this is not defined, then the\n+module code in dwc_common_linux.c is not compiled in. This allows linking the\n+library code directly into a driver module, instead of as a standalone module.\n--- /dev/null\n+++ b/drivers/usb/host/dwc_common_port/doc/doxygen.cfg\n@@ -0,0 +1,270 @@\n+# Doxyfile 1.4.5\n+\n+#---------------------------------------------------------------------------\n+# Project related configuration options\n+#---------------------------------------------------------------------------\n+PROJECT_NAME           = \"Synopsys DWC Portability and Common Library for UWB\"\n+PROJECT_NUMBER         =\n+OUTPUT_DIRECTORY       = doc\n+CREATE_SUBDIRS         = NO\n+OUTPUT_LANGUAGE        = English\n+BRIEF_MEMBER_DESC      = YES\n+REPEAT_BRIEF           = YES\n+ABBREVIATE_BRIEF       = \"The $name class\" \\\n+                         \"The $name widget\" \\\n+                         \"The $name file\" \\\n+                         is \\\n+                         provides \\\n+                         specifies \\\n+                         contains \\\n+                         represents \\\n+                         a \\\n+                         an \\\n+                         the\n+ALWAYS_DETAILED_SEC    = YES\n+INLINE_INHERITED_MEMB  = NO\n+FULL_PATH_NAMES        = NO\n+STRIP_FROM_PATH        = ..\n+STRIP_FROM_INC_PATH    =\n+SHORT_NAMES            = NO\n+JAVADOC_AUTOBRIEF      = YES\n+MULTILINE_CPP_IS_BRIEF = NO\n+DETAILS_AT_TOP         = YES\n+INHERIT_DOCS           = YES\n+SEPARATE_MEMBER_PAGES  = NO\n+TAB_SIZE               = 8\n+ALIASES                =\n+OPTIMIZE_OUTPUT_FOR_C  = YES\n+OPTIMIZE_OUTPUT_JAVA   = NO\n+BUILTIN_STL_SUPPORT    = NO\n+DISTRIBUTE_GROUP_DOC   = NO\n+SUBGROUPING            = NO\n+#---------------------------------------------------------------------------\n+# Build related configuration options\n+#---------------------------------------------------------------------------\n+EXTRACT_ALL            = NO\n+EXTRACT_PRIVATE        = NO\n+EXTRACT_STATIC         = YES\n+EXTRACT_LOCAL_CLASSES  = NO\n+EXTRACT_LOCAL_METHODS  = NO\n+HIDE_UNDOC_MEMBERS     = NO\n+HIDE_UNDOC_CLASSES     = NO\n+HIDE_FRIEND_COMPOUNDS  = NO\n+HIDE_IN_BODY_DOCS      = NO\n+INTERNAL_DOCS          = NO\n+CASE_SENSE_NAMES       = YES\n+HIDE_SCOPE_NAMES       = NO\n+SHOW_INCLUDE_FILES     = NO\n+INLINE_INFO            = YES\n+SORT_MEMBER_DOCS       = NO\n+SORT_BRIEF_DOCS        = NO\n+SORT_BY_SCOPE_NAME     = NO\n+GENERATE_TODOLIST      = YES\n+GENERATE_TESTLIST      = YES\n+GENERATE_BUGLIST       = YES\n+GENERATE_DEPRECATEDLIST= YES\n+ENABLED_SECTIONS       =\n+MAX_INITIALIZER_LINES  = 30\n+SHOW_USED_FILES        = YES\n+SHOW_DIRECTORIES       = YES\n+FILE_VERSION_FILTER    =\n+#---------------------------------------------------------------------------\n+# configuration options related to warning and progress messages\n+#---------------------------------------------------------------------------\n+QUIET                  = YES\n+WARNINGS               = YES\n+WARN_IF_UNDOCUMENTED   = NO\n+WARN_IF_DOC_ERROR      = YES\n+WARN_NO_PARAMDOC       = YES\n+WARN_FORMAT            = \"$file:$line: $text\"\n+WARN_LOGFILE           =\n+#---------------------------------------------------------------------------\n+# configuration options related to the input files\n+#---------------------------------------------------------------------------\n+INPUT                  = .\n+FILE_PATTERNS          = *.c \\\n+                         *.cc \\\n+                         *.cxx \\\n+                         *.cpp \\\n+                         *.c++ \\\n+                         *.d \\\n+                         *.java \\\n+                         *.ii \\\n+                         *.ixx \\\n+                         *.ipp \\\n+                         *.i++ \\\n+                         *.inl \\\n+                         *.h \\\n+                         *.hh \\\n+                         *.hxx \\\n+                         *.hpp \\\n+                         *.h++ \\\n+                         *.idl \\\n+                         *.odl \\\n+                         *.cs \\\n+                         *.php \\\n+                         *.php3 \\\n+                         *.inc \\\n+                         *.m \\\n+                         *.mm \\\n+                         *.dox \\\n+                         *.py \\\n+                         *.C \\\n+                         *.CC \\\n+                         *.C++ \\\n+                         *.II \\\n+                         *.I++ \\\n+                         *.H \\\n+                         *.HH \\\n+                         *.H++ \\\n+                         *.CS \\\n+                         *.PHP \\\n+                         *.PHP3 \\\n+                         *.M \\\n+                         *.MM \\\n+                         *.PY\n+RECURSIVE              = NO\n+EXCLUDE                =\n+EXCLUDE_SYMLINKS       = NO\n+EXCLUDE_PATTERNS       =\n+EXAMPLE_PATH           =\n+EXAMPLE_PATTERNS       = *\n+EXAMPLE_RECURSIVE      = NO\n+IMAGE_PATH             =\n+INPUT_FILTER           =\n+FILTER_PATTERNS        =\n+FILTER_SOURCE_FILES    = NO\n+#---------------------------------------------------------------------------\n+# configuration options related to source browsing\n+#---------------------------------------------------------------------------\n+SOURCE_BROWSER         = NO\n+INLINE_SOURCES         = NO\n+STRIP_CODE_COMMENTS    = YES\n+REFERENCED_BY_RELATION = YES\n+REFERENCES_RELATION    = YES\n+USE_HTAGS              = NO\n+VERBATIM_HEADERS       = NO\n+#---------------------------------------------------------------------------\n+# configuration options related to the alphabetical class index\n+#---------------------------------------------------------------------------\n+ALPHABETICAL_INDEX     = NO\n+COLS_IN_ALPHA_INDEX    = 5\n+IGNORE_PREFIX          =\n+#---------------------------------------------------------------------------\n+# configuration options related to the HTML output\n+#---------------------------------------------------------------------------\n+GENERATE_HTML          = YES\n+HTML_OUTPUT            = html\n+HTML_FILE_EXTENSION    = .html\n+HTML_HEADER            =\n+HTML_FOOTER            =\n+HTML_STYLESHEET        =\n+HTML_ALIGN_MEMBERS     = YES\n+GENERATE_HTMLHELP      = NO\n+CHM_FILE               =\n+HHC_LOCATION           =\n+GENERATE_CHI           = NO\n+BINARY_TOC             = NO\n+TOC_EXPAND             = NO\n+DISABLE_INDEX          = NO\n+ENUM_VALUES_PER_LINE   = 4\n+GENERATE_TREEVIEW      = YES\n+TREEVIEW_WIDTH         = 250\n+#---------------------------------------------------------------------------\n+# configuration options related to the LaTeX output\n+#---------------------------------------------------------------------------\n+GENERATE_LATEX         = NO\n+LATEX_OUTPUT           = latex\n+LATEX_CMD_NAME         = latex\n+MAKEINDEX_CMD_NAME     = makeindex\n+COMPACT_LATEX          = NO\n+PAPER_TYPE             = a4wide\n+EXTRA_PACKAGES         =\n+LATEX_HEADER           =\n+PDF_HYPERLINKS         = NO\n+USE_PDFLATEX           = NO\n+LATEX_BATCHMODE        = NO\n+LATEX_HIDE_INDICES     = NO\n+#---------------------------------------------------------------------------\n+# configuration options related to the RTF output\n+#---------------------------------------------------------------------------\n+GENERATE_RTF           = NO\n+RTF_OUTPUT             = rtf\n+COMPACT_RTF            = NO\n+RTF_HYPERLINKS         = NO\n+RTF_STYLESHEET_FILE    =\n+RTF_EXTENSIONS_FILE    =\n+#---------------------------------------------------------------------------\n+# configuration options related to the man page output\n+#---------------------------------------------------------------------------\n+GENERATE_MAN           = NO\n+MAN_OUTPUT             = man\n+MAN_EXTENSION          = .3\n+MAN_LINKS              = NO\n+#---------------------------------------------------------------------------\n+# configuration options related to the XML output\n+#---------------------------------------------------------------------------\n+GENERATE_XML           = NO\n+XML_OUTPUT             = xml\n+XML_SCHEMA             =\n+XML_DTD                =\n+XML_PROGRAMLISTING     = YES\n+#---------------------------------------------------------------------------\n+# configuration options for the AutoGen Definitions output\n+#---------------------------------------------------------------------------\n+GENERATE_AUTOGEN_DEF   = NO\n+#---------------------------------------------------------------------------\n+# configuration options related to the Perl module output\n+#---------------------------------------------------------------------------\n+GENERATE_PERLMOD       = NO\n+PERLMOD_LATEX          = NO\n+PERLMOD_PRETTY         = YES\n+PERLMOD_MAKEVAR_PREFIX =\n+#---------------------------------------------------------------------------\n+# Configuration options related to the preprocessor\n+#---------------------------------------------------------------------------\n+ENABLE_PREPROCESSING   = YES\n+MACRO_EXPANSION        = NO\n+EXPAND_ONLY_PREDEF     = NO\n+SEARCH_INCLUDES        = YES\n+INCLUDE_PATH           =\n+INCLUDE_FILE_PATTERNS  =\n+PREDEFINED             = DEBUG DEBUG_MEMORY\n+EXPAND_AS_DEFINED      =\n+SKIP_FUNCTION_MACROS   = YES\n+#---------------------------------------------------------------------------\n+# Configuration::additions related to external references\n+#---------------------------------------------------------------------------\n+TAGFILES               =\n+GENERATE_TAGFILE       =\n+ALLEXTERNALS           = NO\n+EXTERNAL_GROUPS        = YES\n+PERL_PATH              = /usr/bin/perl\n+#---------------------------------------------------------------------------\n+# Configuration options related to the dot tool\n+#---------------------------------------------------------------------------\n+CLASS_DIAGRAMS         = YES\n+HIDE_UNDOC_RELATIONS   = YES\n+HAVE_DOT               = NO\n+CLASS_GRAPH            = YES\n+COLLABORATION_GRAPH    = YES\n+GROUP_GRAPHS           = YES\n+UML_LOOK               = NO\n+TEMPLATE_RELATIONS     = NO\n+INCLUDE_GRAPH          = NO\n+INCLUDED_BY_GRAPH      = YES\n+CALL_GRAPH             = NO\n+GRAPHICAL_HIERARCHY    = YES\n+DIRECTORY_GRAPH        = YES\n+DOT_IMAGE_FORMAT       = png\n+DOT_PATH               =\n+DOTFILE_DIRS           =\n+MAX_DOT_GRAPH_DEPTH    = 1000\n+DOT_TRANSPARENT        = NO\n+DOT_MULTI_TARGETS      = NO\n+GENERATE_LEGEND        = YES\n+DOT_CLEANUP            = YES\n+#---------------------------------------------------------------------------\n+# Configuration::additions related to the search engine\n+#---------------------------------------------------------------------------\n+SEARCHENGINE           = NO\n--- /dev/null\n+++ b/drivers/usb/host/dwc_common_port/dwc_cc.c\n@@ -0,0 +1,532 @@\n+/* =========================================================================\n+ * $File: //dwh/usb_iip/dev/software/dwc_common_port_2/dwc_cc.c $\n+ * $Revision: #4 $\n+ * $Date: 2010/11/04 $\n+ * $Change: 1621692 $\n+ *\n+ * Synopsys Portability Library Software and documentation\n+ * (hereinafter, \"Software\") is an Unsupported proprietary work of\n+ * Synopsys, Inc. unless otherwise expressly agreed to in writing\n+ * between Synopsys and you.\n+ *\n+ * The Software IS NOT an item of Licensed Software or Licensed Product\n+ * under any End User Software License Agreement or Agreement for\n+ * Licensed Product with Synopsys or any supplement thereto. You are\n+ * permitted to use and redistribute this Software in source and binary\n+ * forms, with or without modification, provided that redistributions\n+ * of source code must retain this notice. You may not view, use,\n+ * disclose, copy or distribute this file or any information contained\n+ * herein except pursuant to this license grant from Synopsys. If you\n+ * do not agree with this notice, including the disclaimer below, then\n+ * you are not authorized to use the Software.\n+ *\n+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN \"AS IS\"\n+ * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n+ * FOR A PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL\n+ * SYNOPSYS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\n+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\n+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR\n+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY\n+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE\n+ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH\n+ * DAMAGE.\n+ * ========================================================================= */\n+#ifdef DWC_CCLIB\n+\n+#include \"dwc_cc.h\"\n+\n+typedef struct dwc_cc\n+{\n+\tuint32_t uid;\n+\tuint8_t chid[16];\n+\tuint8_t cdid[16];\n+\tuint8_t ck[16];\n+\tuint8_t *name;\n+\tuint8_t length;\n+        DWC_CIRCLEQ_ENTRY(dwc_cc) list_entry;\n+} dwc_cc_t;\n+\n+DWC_CIRCLEQ_HEAD(context_list, dwc_cc);\n+\n+/** The main structure for CC management.  */\n+struct dwc_cc_if\n+{\n+\tdwc_mutex_t *mutex;\n+\tchar *filename;\n+\n+\tunsigned is_host:1;\n+\n+\tdwc_notifier_t *notifier;\n+\n+\tstruct context_list list;\n+};\n+\n+#ifdef DEBUG\n+static inline void dump_bytes(char *name, uint8_t *bytes, int len)\n+{\n+\tint i;\n+\tDWC_PRINTF(\"%s: \", name);\n+\tfor (i=0; i<len; i++) {\n+\t\tDWC_PRINTF(\"%02x \", bytes[i]);\n+\t}\n+\tDWC_PRINTF(\"\\n\");\n+}\n+#else\n+#define dump_bytes(x...)\n+#endif\n+\n+static dwc_cc_t *alloc_cc(void *mem_ctx, uint8_t *name, uint32_t length)\n+{\n+\tdwc_cc_t *cc = dwc_alloc(mem_ctx, sizeof(dwc_cc_t));\n+\tif (!cc) {\n+\t\treturn NULL;\n+\t}\n+\tDWC_MEMSET(cc, 0, sizeof(dwc_cc_t));\n+\n+\tif (name) {\n+\t\tcc->length = length;\n+\t\tcc->name = dwc_alloc(mem_ctx, length);\n+\t\tif (!cc->name) {\n+\t\t\tdwc_free(mem_ctx, cc);\n+\t\t\treturn NULL;\n+\t\t}\n+\n+\t\tDWC_MEMCPY(cc->name, name, length);\n+\t}\n+\n+\treturn cc;\n+}\n+\n+static void free_cc(void *mem_ctx, dwc_cc_t *cc)\n+{\n+\tif (cc->name) {\n+\t\tdwc_free(mem_ctx, cc->name);\n+\t}\n+\tdwc_free(mem_ctx, cc);\n+}\n+\n+static uint32_t next_uid(dwc_cc_if_t *cc_if)\n+{\n+\tuint32_t uid = 0;\n+\tdwc_cc_t *cc;\n+\tDWC_CIRCLEQ_FOREACH(cc, &cc_if->list, list_entry) {\n+\t\tif (cc->uid > uid) {\n+\t\t\tuid = cc->uid;\n+\t\t}\n+\t}\n+\n+\tif (uid == 0) {\n+\t\tuid = 255;\n+\t}\n+\n+\treturn uid + 1;\n+}\n+\n+static dwc_cc_t *cc_find(dwc_cc_if_t *cc_if, uint32_t uid)\n+{\n+\tdwc_cc_t *cc;\n+\tDWC_CIRCLEQ_FOREACH(cc, &cc_if->list, list_entry) {\n+\t\tif (cc->uid == uid) {\n+\t\t\treturn cc;\n+\t\t}\n+\t}\n+\treturn NULL;\n+}\n+\n+static unsigned int cc_data_size(dwc_cc_if_t *cc_if)\n+{\n+\tunsigned int size = 0;\n+\tdwc_cc_t *cc;\n+\tDWC_CIRCLEQ_FOREACH(cc, &cc_if->list, list_entry) {\n+\t\tsize += (48 + 1);\n+\t\tif (cc->name) {\n+\t\t\tsize += cc->length;\n+\t\t}\n+\t}\n+\treturn size;\n+}\n+\n+static uint32_t cc_match_chid(dwc_cc_if_t *cc_if, uint8_t *chid)\n+{\n+\tuint32_t uid = 0;\n+\tdwc_cc_t *cc;\n+\n+\tDWC_CIRCLEQ_FOREACH(cc, &cc_if->list, list_entry) {\n+\t\tif (DWC_MEMCMP(cc->chid, chid, 16) == 0) {\n+\t\t\tuid = cc->uid;\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\treturn uid;\n+}\n+static uint32_t cc_match_cdid(dwc_cc_if_t *cc_if, uint8_t *cdid)\n+{\n+\tuint32_t uid = 0;\n+\tdwc_cc_t *cc;\n+\n+\tDWC_CIRCLEQ_FOREACH(cc, &cc_if->list, list_entry) {\n+\t\tif (DWC_MEMCMP(cc->cdid, cdid, 16) == 0) {\n+\t\t\tuid = cc->uid;\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\treturn uid;\n+}\n+\n+/* Internal cc_add */\n+static int32_t cc_add(void *mem_ctx, dwc_cc_if_t *cc_if, uint8_t *chid,\n+\t\t      uint8_t *cdid, uint8_t *ck, uint8_t *name, uint8_t length)\n+{\n+\tdwc_cc_t *cc;\n+\tuint32_t uid;\n+\n+\tif (cc_if->is_host) {\n+\t\tuid = cc_match_cdid(cc_if, cdid);\n+\t}\n+\telse {\n+\t\tuid = cc_match_chid(cc_if, chid);\n+\t}\n+\n+\tif (uid) {\n+\t\tDWC_DEBUGC(\"Replacing previous connection context id=%d name=%p name_len=%d\", uid, name, length);\n+\t\tcc = cc_find(cc_if, uid);\n+\t}\n+\telse {\n+\t\tcc = alloc_cc(mem_ctx, name, length);\n+\t\tcc->uid = next_uid(cc_if);\n+\t\tDWC_CIRCLEQ_INSERT_TAIL(&cc_if->list, cc, list_entry);\n+\t}\n+\n+\tDWC_MEMCPY(&(cc->chid[0]), chid, 16);\n+\tDWC_MEMCPY(&(cc->cdid[0]), cdid, 16);\n+\tDWC_MEMCPY(&(cc->ck[0]), ck, 16);\n+\n+\tDWC_DEBUGC(\"Added connection context id=%d name=%p name_len=%d\", cc->uid, name, length);\n+\tdump_bytes(\"CHID\", cc->chid, 16);\n+\tdump_bytes(\"CDID\", cc->cdid, 16);\n+\tdump_bytes(\"CK\", cc->ck, 16);\n+\treturn cc->uid;\n+}\n+\n+/* Internal cc_clear */\n+static void cc_clear(void *mem_ctx, dwc_cc_if_t *cc_if)\n+{\n+\twhile (!DWC_CIRCLEQ_EMPTY(&cc_if->list)) {\n+\t\tdwc_cc_t *cc = DWC_CIRCLEQ_FIRST(&cc_if->list);\n+\t\tDWC_CIRCLEQ_REMOVE_INIT(&cc_if->list, cc, list_entry);\n+\t\tfree_cc(mem_ctx, cc);\n+\t}\n+}\n+\n+dwc_cc_if_t *dwc_cc_if_alloc(void *mem_ctx, void *mtx_ctx,\n+\t\t\t     dwc_notifier_t *notifier, unsigned is_host)\n+{\n+\tdwc_cc_if_t *cc_if = NULL;\n+\n+\t/* Allocate a common_cc_if structure */\n+\tcc_if = dwc_alloc(mem_ctx, sizeof(dwc_cc_if_t));\n+\n+\tif (!cc_if)\n+\t\treturn NULL;\n+\n+#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_MUTEXES))\n+\tDWC_MUTEX_ALLOC_LINUX_DEBUG(cc_if->mutex);\n+#else\n+\tcc_if->mutex = dwc_mutex_alloc(mtx_ctx);\n+#endif\n+\tif (!cc_if->mutex) {\n+\t\tdwc_free(mem_ctx, cc_if);\n+\t\treturn NULL;\n+\t}\n+\n+\tDWC_CIRCLEQ_INIT(&cc_if->list);\n+\tcc_if->is_host = is_host;\n+\tcc_if->notifier = notifier;\n+\treturn cc_if;\n+}\n+\n+void dwc_cc_if_free(void *mem_ctx, void *mtx_ctx, dwc_cc_if_t *cc_if)\n+{\n+#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_MUTEXES))\n+\tDWC_MUTEX_FREE(cc_if->mutex);\n+#else\n+\tdwc_mutex_free(mtx_ctx, cc_if->mutex);\n+#endif\n+\tcc_clear(mem_ctx, cc_if);\n+\tdwc_free(mem_ctx, cc_if);\n+}\n+\n+static void cc_changed(dwc_cc_if_t *cc_if)\n+{\n+\tif (cc_if->notifier) {\n+\t\tdwc_notify(cc_if->notifier, DWC_CC_LIST_CHANGED_NOTIFICATION, cc_if);\n+\t}\n+}\n+\n+void dwc_cc_clear(void *mem_ctx, dwc_cc_if_t *cc_if)\n+{\n+\tDWC_MUTEX_LOCK(cc_if->mutex);\n+\tcc_clear(mem_ctx, cc_if);\n+\tDWC_MUTEX_UNLOCK(cc_if->mutex);\n+\tcc_changed(cc_if);\n+}\n+\n+int32_t dwc_cc_add(void *mem_ctx, dwc_cc_if_t *cc_if, uint8_t *chid,\n+\t\t   uint8_t *cdid, uint8_t *ck, uint8_t *name, uint8_t length)\n+{\n+\tuint32_t uid;\n+\n+\tDWC_MUTEX_LOCK(cc_if->mutex);\n+\tuid = cc_add(mem_ctx, cc_if, chid, cdid, ck, name, length);\n+\tDWC_MUTEX_UNLOCK(cc_if->mutex);\n+\tcc_changed(cc_if);\n+\n+\treturn uid;\n+}\n+\n+void dwc_cc_change(void *mem_ctx, dwc_cc_if_t *cc_if, int32_t id, uint8_t *chid,\n+\t\t   uint8_t *cdid, uint8_t *ck, uint8_t *name, uint8_t length)\n+{\n+\tdwc_cc_t* cc;\n+\n+\tDWC_DEBUGC(\"Change connection context %d\", id);\n+\n+\tDWC_MUTEX_LOCK(cc_if->mutex);\n+\tcc = cc_find(cc_if, id);\n+\tif (!cc) {\n+\t\tDWC_ERROR(\"Uid %d not found in cc list\\n\", id);\n+\t\tDWC_MUTEX_UNLOCK(cc_if->mutex);\n+\t\treturn;\n+\t}\n+\n+\tif (chid) {\n+\t\tDWC_MEMCPY(&(cc->chid[0]), chid, 16);\n+\t}\n+\tif (cdid) {\n+\t\tDWC_MEMCPY(&(cc->cdid[0]), cdid, 16);\n+\t}\n+\tif (ck) {\n+\t\tDWC_MEMCPY(&(cc->ck[0]), ck, 16);\n+\t}\n+\n+\tif (name) {\n+\t\tif (cc->name) {\n+\t\t\tdwc_free(mem_ctx, cc->name);\n+\t\t}\n+\t\tcc->name = dwc_alloc(mem_ctx, length);\n+\t\tif (!cc->name) {\n+\t\t\tDWC_ERROR(\"Out of memory in dwc_cc_change()\\n\");\n+\t\t\tDWC_MUTEX_UNLOCK(cc_if->mutex);\n+\t\t\treturn;\n+\t\t}\n+\t\tcc->length = length;\n+\t\tDWC_MEMCPY(cc->name, name, length);\n+\t}\n+\n+\tDWC_MUTEX_UNLOCK(cc_if->mutex);\n+\n+\tcc_changed(cc_if);\n+\n+\tDWC_DEBUGC(\"Changed connection context id=%d\\n\", id);\n+\tdump_bytes(\"New CHID\", cc->chid, 16);\n+\tdump_bytes(\"New CDID\", cc->cdid, 16);\n+\tdump_bytes(\"New CK\", cc->ck, 16);\n+}\n+\n+void dwc_cc_remove(void *mem_ctx, dwc_cc_if_t *cc_if, int32_t id)\n+{\n+\tdwc_cc_t *cc;\n+\n+\tDWC_DEBUGC(\"Removing connection context %d\", id);\n+\n+\tDWC_MUTEX_LOCK(cc_if->mutex);\n+\tcc = cc_find(cc_if, id);\n+\tif (!cc) {\n+\t\tDWC_ERROR(\"Uid %d not found in cc list\\n\", id);\n+\t\tDWC_MUTEX_UNLOCK(cc_if->mutex);\n+\t\treturn;\n+\t}\n+\n+\tDWC_CIRCLEQ_REMOVE_INIT(&cc_if->list, cc, list_entry);\n+\tDWC_MUTEX_UNLOCK(cc_if->mutex);\n+\tfree_cc(mem_ctx, cc);\n+\n+\tcc_changed(cc_if);\n+}\n+\n+uint8_t *dwc_cc_data_for_save(void *mem_ctx, dwc_cc_if_t *cc_if, unsigned int *length)\n+{\n+\tuint8_t *buf, *x;\n+\tuint8_t zero = 0;\n+\tdwc_cc_t *cc;\n+\n+\tDWC_MUTEX_LOCK(cc_if->mutex);\n+\t*length = cc_data_size(cc_if);\n+\tif (!(*length)) {\n+\t\tDWC_MUTEX_UNLOCK(cc_if->mutex);\n+\t\treturn NULL;\n+\t}\n+\n+\tDWC_DEBUGC(\"Creating data for saving (length=%d)\", *length);\n+\n+\tbuf = dwc_alloc(mem_ctx, *length);\n+\tif (!buf) {\n+\t\t*length = 0;\n+\t\tDWC_MUTEX_UNLOCK(cc_if->mutex);\n+\t\treturn NULL;\n+\t}\n+\n+\tx = buf;\n+\tDWC_CIRCLEQ_FOREACH(cc, &cc_if->list, list_entry) {\n+\t\tDWC_MEMCPY(x, cc->chid, 16);\n+\t\tx += 16;\n+\t\tDWC_MEMCPY(x, cc->cdid, 16);\n+\t\tx += 16;\n+\t\tDWC_MEMCPY(x, cc->ck, 16);\n+\t\tx += 16;\n+\t\tif (cc->name) {\n+\t\t\tDWC_MEMCPY(x, &cc->length, 1);\n+\t\t\tx += 1;\n+\t\t\tDWC_MEMCPY(x, cc->name, cc->length);\n+\t\t\tx += cc->length;\n+\t\t}\n+\t\telse {\n+\t\t\tDWC_MEMCPY(x, &zero, 1);\n+\t\t\tx += 1;\n+\t\t}\n+\t}\n+\tDWC_MUTEX_UNLOCK(cc_if->mutex);\n+\n+\treturn buf;\n+}\n+\n+void dwc_cc_restore_from_data(void *mem_ctx, dwc_cc_if_t *cc_if, uint8_t *data, uint32_t length)\n+{\n+\tuint8_t name_length;\n+\tuint8_t *name;\n+\tuint8_t *chid;\n+\tuint8_t *cdid;\n+\tuint8_t *ck;\n+\tuint32_t i = 0;\n+\n+\tDWC_MUTEX_LOCK(cc_if->mutex);\n+\tcc_clear(mem_ctx, cc_if);\n+\n+\twhile (i < length) {\n+\t\tchid = &data[i];\n+\t\ti += 16;\n+\t\tcdid = &data[i];\n+\t\ti += 16;\n+\t\tck = &data[i];\n+\t\ti += 16;\n+\n+\t\tname_length = data[i];\n+\t\ti ++;\n+\n+\t\tif (name_length) {\n+\t\t\tname = &data[i];\n+\t\t\ti += name_length;\n+\t\t}\n+\t\telse {\n+\t\t\tname = NULL;\n+\t\t}\n+\n+\t\t/* check to see if we haven't overflown the buffer */\n+\t\tif (i > length) {\n+\t\t\tDWC_ERROR(\"Data format error while attempting to load CCs \"\n+\t\t\t\t  \"(nlen=%d, iter=%d, buflen=%d).\\n\", name_length, i, length);\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\tcc_add(mem_ctx, cc_if, chid, cdid, ck, name, name_length);\n+\t}\n+\tDWC_MUTEX_UNLOCK(cc_if->mutex);\n+\n+\tcc_changed(cc_if);\n+}\n+\n+uint32_t dwc_cc_match_chid(dwc_cc_if_t *cc_if, uint8_t *chid)\n+{\n+\tuint32_t uid = 0;\n+\n+\tDWC_MUTEX_LOCK(cc_if->mutex);\n+\tuid = cc_match_chid(cc_if, chid);\n+\tDWC_MUTEX_UNLOCK(cc_if->mutex);\n+\treturn uid;\n+}\n+uint32_t dwc_cc_match_cdid(dwc_cc_if_t *cc_if, uint8_t *cdid)\n+{\n+\tuint32_t uid = 0;\n+\n+\tDWC_MUTEX_LOCK(cc_if->mutex);\n+\tuid = cc_match_cdid(cc_if, cdid);\n+\tDWC_MUTEX_UNLOCK(cc_if->mutex);\n+\treturn uid;\n+}\n+\n+uint8_t *dwc_cc_ck(dwc_cc_if_t *cc_if, int32_t id)\n+{\n+\tuint8_t *ck = NULL;\n+\tdwc_cc_t *cc;\n+\n+\tDWC_MUTEX_LOCK(cc_if->mutex);\n+\tcc = cc_find(cc_if, id);\n+\tif (cc) {\n+\t\tck = cc->ck;\n+\t}\n+\tDWC_MUTEX_UNLOCK(cc_if->mutex);\n+\n+\treturn ck;\n+\n+}\n+\n+uint8_t *dwc_cc_chid(dwc_cc_if_t *cc_if, int32_t id)\n+{\n+\tuint8_t *retval = NULL;\n+\tdwc_cc_t *cc;\n+\n+\tDWC_MUTEX_LOCK(cc_if->mutex);\n+\tcc = cc_find(cc_if, id);\n+\tif (cc) {\n+\t\tretval = cc->chid;\n+\t}\n+\tDWC_MUTEX_UNLOCK(cc_if->mutex);\n+\n+\treturn retval;\n+}\n+\n+uint8_t *dwc_cc_cdid(dwc_cc_if_t *cc_if, int32_t id)\n+{\n+\tuint8_t *retval = NULL;\n+\tdwc_cc_t *cc;\n+\n+\tDWC_MUTEX_LOCK(cc_if->mutex);\n+\tcc = cc_find(cc_if, id);\n+\tif (cc) {\n+\t\tretval = cc->cdid;\n+\t}\n+\tDWC_MUTEX_UNLOCK(cc_if->mutex);\n+\n+\treturn retval;\n+}\n+\n+uint8_t *dwc_cc_name(dwc_cc_if_t *cc_if, int32_t id, uint8_t *length)\n+{\n+\tuint8_t *retval = NULL;\n+\tdwc_cc_t *cc;\n+\n+\tDWC_MUTEX_LOCK(cc_if->mutex);\n+\t*length = 0;\n+\tcc = cc_find(cc_if, id);\n+\tif (cc) {\n+\t\t*length = cc->length;\n+\t\tretval = cc->name;\n+\t}\n+\tDWC_MUTEX_UNLOCK(cc_if->mutex);\n+\n+\treturn retval;\n+}\n+\n+#endif\t/* DWC_CCLIB */\n--- /dev/null\n+++ b/drivers/usb/host/dwc_common_port/dwc_cc.h\n@@ -0,0 +1,224 @@\n+/* =========================================================================\n+ * $File: //dwh/usb_iip/dev/software/dwc_common_port_2/dwc_cc.h $\n+ * $Revision: #4 $\n+ * $Date: 2010/09/28 $\n+ * $Change: 1596182 $\n+ *\n+ * Synopsys Portability Library Software and documentation\n+ * (hereinafter, \"Software\") is an Unsupported proprietary work of\n+ * Synopsys, Inc. unless otherwise expressly agreed to in writing\n+ * between Synopsys and you.\n+ *\n+ * The Software IS NOT an item of Licensed Software or Licensed Product\n+ * under any End User Software License Agreement or Agreement for\n+ * Licensed Product with Synopsys or any supplement thereto. You are\n+ * permitted to use and redistribute this Software in source and binary\n+ * forms, with or without modification, provided that redistributions\n+ * of source code must retain this notice. You may not view, use,\n+ * disclose, copy or distribute this file or any information contained\n+ * herein except pursuant to this license grant from Synopsys. If you\n+ * do not agree with this notice, including the disclaimer below, then\n+ * you are not authorized to use the Software.\n+ *\n+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN \"AS IS\"\n+ * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n+ * FOR A PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL\n+ * SYNOPSYS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\n+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\n+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR\n+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY\n+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE\n+ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH\n+ * DAMAGE.\n+ * ========================================================================= */\n+#ifndef _DWC_CC_H_\n+#define _DWC_CC_H_\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+/** @file\n+ *\n+ * This file defines the Context Context library.\n+ *\n+ * The main data structure is dwc_cc_if_t which is returned by either the\n+ * dwc_cc_if_alloc function or returned by the module to the user via a provided\n+ * function. The data structure is opaque and should only be manipulated via the\n+ * functions provied in this API.\n+ *\n+ * It manages a list of connection contexts and operations can be performed to\n+ * add, remove, query, search, and change, those contexts.  Additionally,\n+ * a dwc_notifier_t object can be requested from the manager so that\n+ * the user can be notified whenever the context list has changed.\n+ */\n+\n+#include \"dwc_os.h\"\n+#include \"dwc_list.h\"\n+#include \"dwc_notifier.h\"\n+\n+\n+/* Notifications */\n+#define DWC_CC_LIST_CHANGED_NOTIFICATION \"DWC_CC_LIST_CHANGED_NOTIFICATION\"\n+\n+struct dwc_cc_if;\n+typedef struct dwc_cc_if dwc_cc_if_t;\n+\n+\n+/** @name Connection Context Operations */\n+/** @{ */\n+\n+/** This function allocates memory for a dwc_cc_if_t structure, initializes\n+ * fields to default values, and returns a pointer to the structure or NULL on\n+ * error. */\n+extern dwc_cc_if_t *dwc_cc_if_alloc(void *mem_ctx, void *mtx_ctx,\n+\t\t\t\t    dwc_notifier_t *notifier, unsigned is_host);\n+\n+/** Frees the memory for the specified CC structure allocated from\n+ * dwc_cc_if_alloc(). */\n+extern void dwc_cc_if_free(void *mem_ctx, void *mtx_ctx, dwc_cc_if_t *cc_if);\n+\n+/** Removes all contexts from the connection context list */\n+extern void dwc_cc_clear(void *mem_ctx, dwc_cc_if_t *cc_if);\n+\n+/** Adds a connection context (CHID, CK, CDID, Name) to the connection context list.\n+ * If a CHID already exists, the CK and name are overwritten.  Statistics are\n+ * not overwritten.\n+ *\n+ * @param cc_if The cc_if structure.\n+ * @param chid A pointer to the 16-byte CHID.  This value will be copied.\n+ * @param ck A pointer to the 16-byte CK.  This value will be copied.\n+ * @param cdid A pointer to the 16-byte CDID.  This value will be copied.\n+ * @param name An optional host friendly name as defined in the association model\n+ * spec.  Must be a UTF16-LE unicode string.  Can be NULL to indicated no name.\n+ * @param length The length othe unicode string.\n+ * @return A unique identifier used to refer to this context that is valid for\n+ * as long as this context is still in the list. */\n+extern int32_t dwc_cc_add(void *mem_ctx, dwc_cc_if_t *cc_if, uint8_t *chid,\n+\t\t\t  uint8_t *cdid, uint8_t *ck, uint8_t *name,\n+\t\t\t  uint8_t length);\n+\n+/** Changes the CHID, CK, CDID, or Name values of a connection context in the\n+ * list, preserving any accumulated statistics.  This would typically be called\n+ * if the host decideds to change the context with a SET_CONNECTION request.\n+ *\n+ * @param cc_if The cc_if structure.\n+ * @param id The identifier of the connection context.\n+ * @param chid A pointer to the 16-byte CHID.  This value will be copied.  NULL\n+ * indicates no change.\n+ * @param cdid A pointer to the 16-byte CDID.  This value will be copied.  NULL\n+ * indicates no change.\n+ * @param ck A pointer to the 16-byte CK.  This value will be copied.  NULL\n+ * indicates no change.\n+ * @param name Host friendly name UTF16-LE.  NULL indicates no change.\n+ * @param length Length of name. */\n+extern void dwc_cc_change(void *mem_ctx, dwc_cc_if_t *cc_if, int32_t id,\n+\t\t\t  uint8_t *chid, uint8_t *cdid, uint8_t *ck,\n+\t\t\t  uint8_t *name, uint8_t length);\n+\n+/** Remove the specified connection context.\n+ * @param cc_if The cc_if structure.\n+ * @param id The identifier of the connection context to remove. */\n+extern void dwc_cc_remove(void *mem_ctx, dwc_cc_if_t *cc_if, int32_t id);\n+\n+/** Get a binary block of data for the connection context list and attributes.\n+ * This data can be used by the OS specific driver to save the connection\n+ * context list into non-volatile memory.\n+ *\n+ * @param cc_if The cc_if structure.\n+ * @param length Return the length of the data buffer.\n+ * @return A pointer to the data buffer.  The memory for this buffer should be\n+ * freed with DWC_FREE() after use. */\n+extern uint8_t *dwc_cc_data_for_save(void *mem_ctx, dwc_cc_if_t *cc_if,\n+\t\t\t\t     unsigned int *length);\n+\n+/** Restore the connection context list from the binary data that was previously\n+ * returned from a call to dwc_cc_data_for_save.  This can be used by the OS specific\n+ * driver to load a connection context list from non-volatile memory.\n+ *\n+ * @param cc_if The cc_if structure.\n+ * @param data The data bytes as returned from dwc_cc_data_for_save.\n+ * @param length The length of the data. */\n+extern void dwc_cc_restore_from_data(void *mem_ctx, dwc_cc_if_t *cc_if,\n+\t\t\t\t     uint8_t *data, unsigned int length);\n+\n+/** Find the connection context from the specified CHID.\n+ *\n+ * @param cc_if The cc_if structure.\n+ * @param chid A pointer to the CHID data.\n+ * @return A non-zero identifier of the connection context if the CHID matches.\n+ * Otherwise returns 0. */\n+extern uint32_t dwc_cc_match_chid(dwc_cc_if_t *cc_if, uint8_t *chid);\n+\n+/** Find the connection context from the specified CDID.\n+ *\n+ * @param cc_if The cc_if structure.\n+ * @param cdid A pointer to the CDID data.\n+ * @return A non-zero identifier of the connection context if the CHID matches.\n+ * Otherwise returns 0. */\n+extern uint32_t dwc_cc_match_cdid(dwc_cc_if_t *cc_if, uint8_t *cdid);\n+\n+/** Retrieve the CK from the specified connection context.\n+ *\n+ * @param cc_if The cc_if structure.\n+ * @param id The identifier of the connection context.\n+ * @return A pointer to the CK data.  The memory does not need to be freed. */\n+extern uint8_t *dwc_cc_ck(dwc_cc_if_t *cc_if, int32_t id);\n+\n+/** Retrieve the CHID from the specified connection context.\n+ *\n+ * @param cc_if The cc_if structure.\n+ * @param id The identifier of the connection context.\n+ * @return A pointer to the CHID data.  The memory does not need to be freed. */\n+extern uint8_t *dwc_cc_chid(dwc_cc_if_t *cc_if, int32_t id);\n+\n+/** Retrieve the CDID from the specified connection context.\n+ *\n+ * @param cc_if The cc_if structure.\n+ * @param id The identifier of the connection context.\n+ * @return A pointer to the CDID data.  The memory does not need to be freed. */\n+extern uint8_t *dwc_cc_cdid(dwc_cc_if_t *cc_if, int32_t id);\n+\n+extern uint8_t *dwc_cc_name(dwc_cc_if_t *cc_if, int32_t id, uint8_t *length);\n+\n+/** Checks a buffer for non-zero.\n+ * @param id A pointer to a 16 byte buffer.\n+ * @return true if the 16 byte value is non-zero. */\n+static inline unsigned dwc_assoc_is_not_zero_id(uint8_t *id) {\n+\tint i;\n+\tfor (i=0; i<16; i++) {\n+\t\tif (id[i]) return 1;\n+\t}\n+\treturn 0;\n+}\n+\n+/** Checks a buffer for zero.\n+ * @param id A pointer to a 16 byte buffer.\n+ * @return true if the 16 byte value is zero. */\n+static inline unsigned dwc_assoc_is_zero_id(uint8_t *id) {\n+\treturn !dwc_assoc_is_not_zero_id(id);\n+}\n+\n+/** Prints an ASCII representation for the 16-byte chid, cdid, or ck, into\n+ * buffer. */\n+static inline int dwc_print_id_string(char *buffer, uint8_t *id) {\n+\tchar *ptr = buffer;\n+\tint i;\n+\tfor (i=0; i<16; i++) {\n+\t\tptr += DWC_SPRINTF(ptr, \"%02x\", id[i]);\n+\t\tif (i < 15) {\n+\t\t\tptr += DWC_SPRINTF(ptr, \" \");\n+\t\t}\n+\t}\n+\treturn ptr - buffer;\n+}\n+\n+/** @} */\n+\n+#ifdef __cplusplus\n+}\n+#endif\n+\n+#endif /* _DWC_CC_H_ */\n--- /dev/null\n+++ b/drivers/usb/host/dwc_common_port/dwc_common_fbsd.c\n@@ -0,0 +1,1308 @@\n+#include \"dwc_os.h\"\n+#include \"dwc_list.h\"\n+\n+#ifdef DWC_CCLIB\n+# include \"dwc_cc.h\"\n+#endif\n+\n+#ifdef DWC_CRYPTOLIB\n+# include \"dwc_modpow.h\"\n+# include \"dwc_dh.h\"\n+# include \"dwc_crypto.h\"\n+#endif\n+\n+#ifdef DWC_NOTIFYLIB\n+# include \"dwc_notifier.h\"\n+#endif\n+\n+/* OS-Level Implementations */\n+\n+/* This is the FreeBSD 7.0 kernel implementation of the DWC platform library. */\n+\n+\n+/* MISC */\n+\n+void *DWC_MEMSET(void *dest, uint8_t byte, uint32_t size)\n+{\n+\treturn memset(dest, byte, size);\n+}\n+\n+void *DWC_MEMCPY(void *dest, void const *src, uint32_t size)\n+{\n+\treturn memcpy(dest, src, size);\n+}\n+\n+void *DWC_MEMMOVE(void *dest, void *src, uint32_t size)\n+{\n+\tbcopy(src, dest, size);\n+\treturn dest;\n+}\n+\n+int DWC_MEMCMP(void *m1, void *m2, uint32_t size)\n+{\n+\treturn memcmp(m1, m2, size);\n+}\n+\n+int DWC_STRNCMP(void *s1, void *s2, uint32_t size)\n+{\n+\treturn strncmp(s1, s2, size);\n+}\n+\n+int DWC_STRCMP(void *s1, void *s2)\n+{\n+\treturn strcmp(s1, s2);\n+}\n+\n+int DWC_STRLEN(char const *str)\n+{\n+\treturn strlen(str);\n+}\n+\n+char *DWC_STRCPY(char *to, char const *from)\n+{\n+\treturn strcpy(to, from);\n+}\n+\n+char *DWC_STRDUP(char const *str)\n+{\n+\tint len = DWC_STRLEN(str) + 1;\n+\tchar *new = DWC_ALLOC_ATOMIC(len);\n+\n+\tif (!new) {\n+\t\treturn NULL;\n+\t}\n+\n+\tDWC_MEMCPY(new, str, len);\n+\treturn new;\n+}\n+\n+int DWC_ATOI(char *str, int32_t *value)\n+{\n+\tchar *end = NULL;\n+\n+\t*value = strtol(str, &end, 0);\n+\tif (*end == '\\0') {\n+\t\treturn 0;\n+\t}\n+\n+\treturn -1;\n+}\n+\n+int DWC_ATOUI(char *str, uint32_t *value)\n+{\n+\tchar *end = NULL;\n+\n+\t*value = strtoul(str, &end, 0);\n+\tif (*end == '\\0') {\n+\t\treturn 0;\n+\t}\n+\n+\treturn -1;\n+}\n+\n+\n+#ifdef DWC_UTFLIB\n+/* From usbstring.c */\n+\n+int DWC_UTF8_TO_UTF16LE(uint8_t const *s, uint16_t *cp, unsigned len)\n+{\n+\tint\tcount = 0;\n+\tu8\tc;\n+\tu16\tuchar;\n+\n+\t/* this insists on correct encodings, though not minimal ones.\n+\t * BUT it currently rejects legit 4-byte UTF-8 code points,\n+\t * which need surrogate pairs.  (Unicode 3.1 can use them.)\n+\t */\n+\twhile (len != 0 && (c = (u8) *s++) != 0) {\n+\t\tif (unlikely(c & 0x80)) {\n+\t\t\t// 2-byte sequence:\n+\t\t\t// 00000yyyyyxxxxxx = 110yyyyy 10xxxxxx\n+\t\t\tif ((c & 0xe0) == 0xc0) {\n+\t\t\t\tuchar = (c & 0x1f) << 6;\n+\n+\t\t\t\tc = (u8) *s++;\n+\t\t\t\tif ((c & 0xc0) != 0xc0)\n+\t\t\t\t\tgoto fail;\n+\t\t\t\tc &= 0x3f;\n+\t\t\t\tuchar |= c;\n+\n+\t\t\t// 3-byte sequence (most CJKV characters):\n+\t\t\t// zzzzyyyyyyxxxxxx = 1110zzzz 10yyyyyy 10xxxxxx\n+\t\t\t} else if ((c & 0xf0) == 0xe0) {\n+\t\t\t\tuchar = (c & 0x0f) << 12;\n+\n+\t\t\t\tc = (u8) *s++;\n+\t\t\t\tif ((c & 0xc0) != 0xc0)\n+\t\t\t\t\tgoto fail;\n+\t\t\t\tc &= 0x3f;\n+\t\t\t\tuchar |= c << 6;\n+\n+\t\t\t\tc = (u8) *s++;\n+\t\t\t\tif ((c & 0xc0) != 0xc0)\n+\t\t\t\t\tgoto fail;\n+\t\t\t\tc &= 0x3f;\n+\t\t\t\tuchar |= c;\n+\n+\t\t\t\t/* no bogus surrogates */\n+\t\t\t\tif (0xd800 <= uchar && uchar <= 0xdfff)\n+\t\t\t\t\tgoto fail;\n+\n+\t\t\t// 4-byte sequence (surrogate pairs, currently rare):\n+\t\t\t// 11101110wwwwzzzzyy + 110111yyyyxxxxxx\n+\t\t\t//     = 11110uuu 10uuzzzz 10yyyyyy 10xxxxxx\n+\t\t\t// (uuuuu = wwww + 1)\n+\t\t\t// FIXME accept the surrogate code points (only)\n+\t\t\t} else\n+\t\t\t\tgoto fail;\n+\t\t} else\n+\t\t\tuchar = c;\n+\t\tput_unaligned (cpu_to_le16 (uchar), cp++);\n+\t\tcount++;\n+\t\tlen--;\n+\t}\n+\treturn count;\n+fail:\n+\treturn -1;\n+}\n+\n+#endif\t/* DWC_UTFLIB */\n+\n+\n+/* dwc_debug.h */\n+\n+dwc_bool_t DWC_IN_IRQ(void)\n+{\n+//\treturn in_irq();\n+\treturn 0;\n+}\n+\n+dwc_bool_t DWC_IN_BH(void)\n+{\n+//\treturn in_softirq();\n+\treturn 0;\n+}\n+\n+void DWC_VPRINTF(char *format, va_list args)\n+{\n+\tvprintf(format, args);\n+}\n+\n+int DWC_VSNPRINTF(char *str, int size, char *format, va_list args)\n+{\n+\treturn vsnprintf(str, size, format, args);\n+}\n+\n+void DWC_PRINTF(char *format, ...)\n+{\n+\tva_list args;\n+\n+\tva_start(args, format);\n+\tDWC_VPRINTF(format, args);\n+\tva_end(args);\n+}\n+\n+int DWC_SPRINTF(char *buffer, char *format, ...)\n+{\n+\tint retval;\n+\tva_list args;\n+\n+\tva_start(args, format);\n+\tretval = vsprintf(buffer, format, args);\n+\tva_end(args);\n+\treturn retval;\n+}\n+\n+int DWC_SNPRINTF(char *buffer, int size, char *format, ...)\n+{\n+\tint retval;\n+\tva_list args;\n+\n+\tva_start(args, format);\n+\tretval = vsnprintf(buffer, size, format, args);\n+\tva_end(args);\n+\treturn retval;\n+}\n+\n+void __DWC_WARN(char *format, ...)\n+{\n+\tva_list args;\n+\n+\tva_start(args, format);\n+\tDWC_VPRINTF(format, args);\n+\tva_end(args);\n+}\n+\n+void __DWC_ERROR(char *format, ...)\n+{\n+\tva_list args;\n+\n+\tva_start(args, format);\n+\tDWC_VPRINTF(format, args);\n+\tva_end(args);\n+}\n+\n+void DWC_EXCEPTION(char *format, ...)\n+{\n+\tva_list args;\n+\n+\tva_start(args, format);\n+\tDWC_VPRINTF(format, args);\n+\tva_end(args);\n+//\tBUG_ON(1);\t???\n+}\n+\n+#ifdef DEBUG\n+void __DWC_DEBUG(char *format, ...)\n+{\n+\tva_list args;\n+\n+\tva_start(args, format);\n+\tDWC_VPRINTF(format, args);\n+\tva_end(args);\n+}\n+#endif\n+\n+\n+/* dwc_mem.h */\n+\n+#if 0\n+dwc_pool_t *DWC_DMA_POOL_CREATE(uint32_t size,\n+\t\t\t\tuint32_t align,\n+\t\t\t\tuint32_t alloc)\n+{\n+\tstruct dma_pool *pool = dma_pool_create(\"Pool\", NULL,\n+\t\t\t\t\t\tsize, align, alloc);\n+\treturn (dwc_pool_t *)pool;\n+}\n+\n+void DWC_DMA_POOL_DESTROY(dwc_pool_t *pool)\n+{\n+\tdma_pool_destroy((struct dma_pool *)pool);\n+}\n+\n+void *DWC_DMA_POOL_ALLOC(dwc_pool_t *pool, uint64_t *dma_addr)\n+{\n+//\treturn dma_pool_alloc((struct dma_pool *)pool, GFP_KERNEL, dma_addr);\n+\treturn dma_pool_alloc((struct dma_pool *)pool, M_WAITOK, dma_addr);\n+}\n+\n+void *DWC_DMA_POOL_ZALLOC(dwc_pool_t *pool, uint64_t *dma_addr)\n+{\n+\tvoid *vaddr = DWC_DMA_POOL_ALLOC(pool, dma_addr);\n+\tmemset(..);\n+}\n+\n+void DWC_DMA_POOL_FREE(dwc_pool_t *pool, void *vaddr, void *daddr)\n+{\n+\tdma_pool_free(pool, vaddr, daddr);\n+}\n+#endif\n+\n+static void dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)\n+{\n+\tif (error)\n+\t\treturn;\n+\t*(bus_addr_t *)arg = segs[0].ds_addr;\n+}\n+\n+void *__DWC_DMA_ALLOC(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr)\n+{\n+\tdwc_dmactx_t *dma = (dwc_dmactx_t *)dma_ctx;\n+\tint error;\n+\n+\terror = bus_dma_tag_create(\n+#if __FreeBSD_version >= 700000\n+\t\t\tbus_get_dma_tag(dma->dev),\t/* parent */\n+#else\n+\t\t\tNULL,\t\t\t\t/* parent */\n+#endif\n+\t\t\t4, 0,\t\t\t\t/* alignment, bounds */\n+\t\t\tBUS_SPACE_MAXADDR_32BIT,\t/* lowaddr */\n+\t\t\tBUS_SPACE_MAXADDR,\t\t/* highaddr */\n+\t\t\tNULL, NULL,\t\t\t/* filter, filterarg */\n+\t\t\tsize,\t\t\t\t/* maxsize */\n+\t\t\t1,\t\t\t\t/* nsegments */\n+\t\t\tsize,\t\t\t\t/* maxsegsize */\n+\t\t\t0,\t\t\t\t/* flags */\n+\t\t\tNULL,\t\t\t\t/* lockfunc */\n+\t\t\tNULL,\t\t\t\t/* lockarg */\n+\t\t\t&dma->dma_tag);\n+\tif (error) {\n+\t\tdevice_printf(dma->dev, \"%s: bus_dma_tag_create failed: %d\\n\",\n+\t\t\t      __func__, error);\n+\t\tgoto fail_0;\n+\t}\n+\n+\terror = bus_dmamem_alloc(dma->dma_tag, &dma->dma_vaddr,\n+\t\t\t\t BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &dma->dma_map);\n+\tif (error) {\n+\t\tdevice_printf(dma->dev, \"%s: bus_dmamem_alloc(%ju) failed: %d\\n\",\n+\t\t\t      __func__, (uintmax_t)size, error);\n+\t\tgoto fail_1;\n+\t}\n+\n+\tdma->dma_paddr = 0;\n+\terror = bus_dmamap_load(dma->dma_tag, dma->dma_map, dma->dma_vaddr, size,\n+\t\t\t\tdmamap_cb, &dma->dma_paddr, BUS_DMA_NOWAIT);\n+\tif (error || dma->dma_paddr == 0) {\n+\t\tdevice_printf(dma->dev, \"%s: bus_dmamap_load failed: %d\\n\",\n+\t\t\t      __func__, error);\n+\t\tgoto fail_2;\n+\t}\n+\n+\t*dma_addr = dma->dma_paddr;\n+\treturn dma->dma_vaddr;\n+\n+fail_2:\n+\tbus_dmamap_unload(dma->dma_tag, dma->dma_map);\n+fail_1:\n+\tbus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map);\n+\tbus_dma_tag_destroy(dma->dma_tag);\n+fail_0:\n+\tdma->dma_map = NULL;\n+\tdma->dma_tag = NULL;\n+\n+\treturn NULL;\n+}\n+\n+void __DWC_DMA_FREE(void *dma_ctx, uint32_t size, void *virt_addr, dwc_dma_t dma_addr)\n+{\n+\tdwc_dmactx_t *dma = (dwc_dmactx_t *)dma_ctx;\n+\n+\tif (dma->dma_tag == NULL)\n+\t\treturn;\n+\tif (dma->dma_map != NULL) {\n+\t\tbus_dmamap_sync(dma->dma_tag, dma->dma_map,\n+\t\t\t\tBUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);\n+\t\tbus_dmamap_unload(dma->dma_tag, dma->dma_map);\n+\t\tbus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map);\n+\t\tdma->dma_map = NULL;\n+\t}\n+\n+\tbus_dma_tag_destroy(dma->dma_tag);\n+\tdma->dma_tag = NULL;\n+}\n+\n+void *__DWC_ALLOC(void *mem_ctx, uint32_t size)\n+{\n+\treturn malloc(size, M_DEVBUF, M_WAITOK | M_ZERO);\n+}\n+\n+void *__DWC_ALLOC_ATOMIC(void *mem_ctx, uint32_t size)\n+{\n+\treturn malloc(size, M_DEVBUF, M_NOWAIT | M_ZERO);\n+}\n+\n+void __DWC_FREE(void *mem_ctx, void *addr)\n+{\n+\tfree(addr, M_DEVBUF);\n+}\n+\n+\n+#ifdef DWC_CRYPTOLIB\n+/* dwc_crypto.h */\n+\n+void DWC_RANDOM_BYTES(uint8_t *buffer, uint32_t length)\n+{\n+\tget_random_bytes(buffer, length);\n+}\n+\n+int DWC_AES_CBC(uint8_t *message, uint32_t messagelen, uint8_t *key, uint32_t keylen, uint8_t iv[16], uint8_t *out)\n+{\n+\tstruct crypto_blkcipher *tfm;\n+\tstruct blkcipher_desc desc;\n+\tstruct scatterlist sgd;\n+\tstruct scatterlist sgs;\n+\n+\ttfm = crypto_alloc_blkcipher(\"cbc(aes)\", 0, CRYPTO_ALG_ASYNC);\n+\tif (tfm == NULL) {\n+\t\tprintk(\"failed to load transform for aes CBC\\n\");\n+\t\treturn -1;\n+\t}\n+\n+\tcrypto_blkcipher_setkey(tfm, key, keylen);\n+\tcrypto_blkcipher_set_iv(tfm, iv, 16);\n+\n+\tsg_init_one(&sgd, out, messagelen);\n+\tsg_init_one(&sgs, message, messagelen);\n+\n+\tdesc.tfm = tfm;\n+\tdesc.flags = 0;\n+\n+\tif (crypto_blkcipher_encrypt(&desc, &sgd, &sgs, messagelen)) {\n+\t\tcrypto_free_blkcipher(tfm);\n+\t\tDWC_ERROR(\"AES CBC encryption failed\");\n+\t\treturn -1;\n+\t}\n+\n+\tcrypto_free_blkcipher(tfm);\n+\treturn 0;\n+}\n+\n+int DWC_SHA256(uint8_t *message, uint32_t len, uint8_t *out)\n+{\n+\tstruct crypto_hash *tfm;\n+\tstruct hash_desc desc;\n+\tstruct scatterlist sg;\n+\n+\ttfm = crypto_alloc_hash(\"sha256\", 0, CRYPTO_ALG_ASYNC);\n+\tif (IS_ERR(tfm)) {\n+\t\tDWC_ERROR(\"Failed to load transform for sha256: %ld\", PTR_ERR(tfm));\n+\t\treturn 0;\n+\t}\n+\tdesc.tfm = tfm;\n+\tdesc.flags = 0;\n+\n+\tsg_init_one(&sg, message, len);\n+\tcrypto_hash_digest(&desc, &sg, len, out);\n+\tcrypto_free_hash(tfm);\n+\n+\treturn 1;\n+}\n+\n+int DWC_HMAC_SHA256(uint8_t *message, uint32_t messagelen,\n+\t\t    uint8_t *key, uint32_t keylen, uint8_t *out)\n+{\n+\tstruct crypto_hash *tfm;\n+\tstruct hash_desc desc;\n+\tstruct scatterlist sg;\n+\n+\ttfm = crypto_alloc_hash(\"hmac(sha256)\", 0, CRYPTO_ALG_ASYNC);\n+\tif (IS_ERR(tfm)) {\n+\t\tDWC_ERROR(\"Failed to load transform for hmac(sha256): %ld\", PTR_ERR(tfm));\n+\t\treturn 0;\n+\t}\n+\tdesc.tfm = tfm;\n+\tdesc.flags = 0;\n+\n+\tsg_init_one(&sg, message, messagelen);\n+\tcrypto_hash_setkey(tfm, key, keylen);\n+\tcrypto_hash_digest(&desc, &sg, messagelen, out);\n+\tcrypto_free_hash(tfm);\n+\n+\treturn 1;\n+}\n+\n+#endif\t/* DWC_CRYPTOLIB */\n+\n+\n+/* Byte Ordering Conversions */\n+\n+uint32_t DWC_CPU_TO_LE32(uint32_t *p)\n+{\n+#ifdef __LITTLE_ENDIAN\n+\treturn *p;\n+#else\n+\tuint8_t *u_p = (uint8_t *)p;\n+\n+\treturn (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24));\n+#endif\n+}\n+\n+uint32_t DWC_CPU_TO_BE32(uint32_t *p)\n+{\n+#ifdef __BIG_ENDIAN\n+\treturn *p;\n+#else\n+\tuint8_t *u_p = (uint8_t *)p;\n+\n+\treturn (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24));\n+#endif\n+}\n+\n+uint32_t DWC_LE32_TO_CPU(uint32_t *p)\n+{\n+#ifdef __LITTLE_ENDIAN\n+\treturn *p;\n+#else\n+\tuint8_t *u_p = (uint8_t *)p;\n+\n+\treturn (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24));\n+#endif\n+}\n+\n+uint32_t DWC_BE32_TO_CPU(uint32_t *p)\n+{\n+#ifdef __BIG_ENDIAN\n+\treturn *p;\n+#else\n+\tuint8_t *u_p = (uint8_t *)p;\n+\n+\treturn (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24));\n+#endif\n+}\n+\n+uint16_t DWC_CPU_TO_LE16(uint16_t *p)\n+{\n+#ifdef __LITTLE_ENDIAN\n+\treturn *p;\n+#else\n+\tuint8_t *u_p = (uint8_t *)p;\n+\treturn (u_p[1] | (u_p[0] << 8));\n+#endif\n+}\n+\n+uint16_t DWC_CPU_TO_BE16(uint16_t *p)\n+{\n+#ifdef __BIG_ENDIAN\n+\treturn *p;\n+#else\n+\tuint8_t *u_p = (uint8_t *)p;\n+\treturn (u_p[1] | (u_p[0] << 8));\n+#endif\n+}\n+\n+uint16_t DWC_LE16_TO_CPU(uint16_t *p)\n+{\n+#ifdef __LITTLE_ENDIAN\n+\treturn *p;\n+#else\n+\tuint8_t *u_p = (uint8_t *)p;\n+\treturn (u_p[1] | (u_p[0] << 8));\n+#endif\n+}\n+\n+uint16_t DWC_BE16_TO_CPU(uint16_t *p)\n+{\n+#ifdef __BIG_ENDIAN\n+\treturn *p;\n+#else\n+\tuint8_t *u_p = (uint8_t *)p;\n+\treturn (u_p[1] | (u_p[0] << 8));\n+#endif\n+}\n+\n+\n+/* Registers */\n+\n+uint32_t DWC_READ_REG32(void *io_ctx, uint32_t volatile *reg)\n+{\n+\tdwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx;\n+\tbus_size_t ior = (bus_size_t)reg;\n+\n+\treturn bus_space_read_4(io->iot, io->ioh, ior);\n+}\n+\n+#if 0\n+uint64_t DWC_READ_REG64(void *io_ctx, uint64_t volatile *reg)\n+{\n+\tdwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx;\n+\tbus_size_t ior = (bus_size_t)reg;\n+\n+\treturn bus_space_read_8(io->iot, io->ioh, ior);\n+}\n+#endif\n+\n+void DWC_WRITE_REG32(void *io_ctx, uint32_t volatile *reg, uint32_t value)\n+{\n+\tdwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx;\n+\tbus_size_t ior = (bus_size_t)reg;\n+\n+\tbus_space_write_4(io->iot, io->ioh, ior, value);\n+}\n+\n+#if 0\n+void DWC_WRITE_REG64(void *io_ctx, uint64_t volatile *reg, uint64_t value)\n+{\n+\tdwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx;\n+\tbus_size_t ior = (bus_size_t)reg;\n+\n+\tbus_space_write_8(io->iot, io->ioh, ior, value);\n+}\n+#endif\n+\n+void DWC_MODIFY_REG32(void *io_ctx, uint32_t volatile *reg, uint32_t clear_mask,\n+\t\t      uint32_t set_mask)\n+{\n+\tdwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx;\n+\tbus_size_t ior = (bus_size_t)reg;\n+\n+\tbus_space_write_4(io->iot, io->ioh, ior,\n+\t\t\t  (bus_space_read_4(io->iot, io->ioh, ior) &\n+\t\t\t   ~clear_mask) | set_mask);\n+}\n+\n+#if 0\n+void DWC_MODIFY_REG64(void *io_ctx, uint64_t volatile *reg, uint64_t clear_mask,\n+\t\t      uint64_t set_mask)\n+{\n+\tdwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx;\n+\tbus_size_t ior = (bus_size_t)reg;\n+\n+\tbus_space_write_8(io->iot, io->ioh, ior,\n+\t\t\t  (bus_space_read_8(io->iot, io->ioh, ior) &\n+\t\t\t   ~clear_mask) | set_mask);\n+}\n+#endif\n+\n+\n+/* Locking */\n+\n+dwc_spinlock_t *DWC_SPINLOCK_ALLOC(void)\n+{\n+\tstruct mtx *sl = DWC_ALLOC(sizeof(*sl));\n+\n+\tif (!sl) {\n+\t\tDWC_ERROR(\"Cannot allocate memory for spinlock\");\n+\t\treturn NULL;\n+\t}\n+\n+\tmtx_init(sl, \"dw3spn\", NULL, MTX_SPIN);\n+\treturn (dwc_spinlock_t *)sl;\n+}\n+\n+void DWC_SPINLOCK_FREE(dwc_spinlock_t *lock)\n+{\n+\tstruct mtx *sl = (struct mtx *)lock;\n+\n+\tmtx_destroy(sl);\n+\tDWC_FREE(sl);\n+}\n+\n+void DWC_SPINLOCK(dwc_spinlock_t *lock)\n+{\n+\tmtx_lock_spin((struct mtx *)lock);\t// ???\n+}\n+\n+void DWC_SPINUNLOCK(dwc_spinlock_t *lock)\n+{\n+\tmtx_unlock_spin((struct mtx *)lock);\t// ???\n+}\n+\n+void DWC_SPINLOCK_IRQSAVE(dwc_spinlock_t *lock, dwc_irqflags_t *flags)\n+{\n+\tmtx_lock_spin((struct mtx *)lock);\n+}\n+\n+void DWC_SPINUNLOCK_IRQRESTORE(dwc_spinlock_t *lock, dwc_irqflags_t flags)\n+{\n+\tmtx_unlock_spin((struct mtx *)lock);\n+}\n+\n+dwc_mutex_t *DWC_MUTEX_ALLOC(void)\n+{\n+\tstruct mtx *m;\n+\tdwc_mutex_t *mutex = (dwc_mutex_t *)DWC_ALLOC(sizeof(struct mtx));\n+\n+\tif (!mutex) {\n+\t\tDWC_ERROR(\"Cannot allocate memory for mutex\");\n+\t\treturn NULL;\n+\t}\n+\n+\tm = (struct mtx *)mutex;\n+\tmtx_init(m, \"dw3mtx\", NULL, MTX_DEF);\n+\treturn mutex;\n+}\n+\n+#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_MUTEXES))\n+#else\n+void DWC_MUTEX_FREE(dwc_mutex_t *mutex)\n+{\n+\tmtx_destroy((struct mtx *)mutex);\n+\tDWC_FREE(mutex);\n+}\n+#endif\n+\n+void DWC_MUTEX_LOCK(dwc_mutex_t *mutex)\n+{\n+\tstruct mtx *m = (struct mtx *)mutex;\n+\n+\tmtx_lock(m);\n+}\n+\n+int DWC_MUTEX_TRYLOCK(dwc_mutex_t *mutex)\n+{\n+\tstruct mtx *m = (struct mtx *)mutex;\n+\n+\treturn mtx_trylock(m);\n+}\n+\n+void DWC_MUTEX_UNLOCK(dwc_mutex_t *mutex)\n+{\n+\tstruct mtx *m = (struct mtx *)mutex;\n+\n+\tmtx_unlock(m);\n+}\n+\n+\n+/* Timing */\n+\n+void DWC_UDELAY(uint32_t usecs)\n+{\n+\tDELAY(usecs);\n+}\n+\n+void DWC_MDELAY(uint32_t msecs)\n+{\n+\tdo {\n+\t\tDELAY(1000);\n+\t} while (--msecs);\n+}\n+\n+void DWC_MSLEEP(uint32_t msecs)\n+{\n+\tstruct timeval tv;\n+\n+\ttv.tv_sec = msecs / 1000;\n+\ttv.tv_usec = (msecs - tv.tv_sec * 1000) * 1000;\n+\tpause(\"dw3slp\", tvtohz(&tv));\n+}\n+\n+uint32_t DWC_TIME(void)\n+{\n+\tstruct timeval tv;\n+\n+\tmicrouptime(&tv);\t// or getmicrouptime? (less precise, but faster)\n+\treturn tv.tv_sec * 1000 + tv.tv_usec / 1000;\n+}\n+\n+\n+/* Timers */\n+\n+struct dwc_timer {\n+\tstruct callout t;\n+\tchar *name;\n+\tdwc_spinlock_t *lock;\n+\tdwc_timer_callback_t cb;\n+\tvoid *data;\n+};\n+\n+dwc_timer_t *DWC_TIMER_ALLOC(char *name, dwc_timer_callback_t cb, void *data)\n+{\n+\tdwc_timer_t *t = DWC_ALLOC(sizeof(*t));\n+\n+\tif (!t) {\n+\t\tDWC_ERROR(\"Cannot allocate memory for timer\");\n+\t\treturn NULL;\n+\t}\n+\n+\tcallout_init(&t->t, 1);\n+\n+\tt->name = DWC_STRDUP(name);\n+\tif (!t->name) {\n+\t\tDWC_ERROR(\"Cannot allocate memory for timer->name\");\n+\t\tgoto no_name;\n+\t}\n+\n+\tt->lock = DWC_SPINLOCK_ALLOC();\n+\tif (!t->lock) {\n+\t\tDWC_ERROR(\"Cannot allocate memory for lock\");\n+\t\tgoto no_lock;\n+\t}\n+\n+\tt->cb = cb;\n+\tt->data = data;\n+\n+\treturn t;\n+\n+ no_lock:\n+\tDWC_FREE(t->name);\n+ no_name:\n+\tDWC_FREE(t);\n+\n+\treturn NULL;\n+}\n+\n+void DWC_TIMER_FREE(dwc_timer_t *timer)\n+{\n+\tcallout_stop(&timer->t);\n+\tDWC_SPINLOCK_FREE(timer->lock);\n+\tDWC_FREE(timer->name);\n+\tDWC_FREE(timer);\n+}\n+\n+void DWC_TIMER_SCHEDULE(dwc_timer_t *timer, uint32_t time)\n+{\n+\tstruct timeval tv;\n+\n+\ttv.tv_sec = time / 1000;\n+\ttv.tv_usec = (time - tv.tv_sec * 1000) * 1000;\n+\tcallout_reset(&timer->t, tvtohz(&tv), timer->cb, timer->data);\n+}\n+\n+void DWC_TIMER_CANCEL(dwc_timer_t *timer)\n+{\n+\tcallout_stop(&timer->t);\n+}\n+\n+\n+/* Wait Queues */\n+\n+struct dwc_waitq {\n+\tstruct mtx lock;\n+\tint abort;\n+};\n+\n+dwc_waitq_t *DWC_WAITQ_ALLOC(void)\n+{\n+\tdwc_waitq_t *wq = DWC_ALLOC(sizeof(*wq));\n+\n+\tif (!wq) {\n+\t\tDWC_ERROR(\"Cannot allocate memory for waitqueue\");\n+\t\treturn NULL;\n+\t}\n+\n+\tmtx_init(&wq->lock, \"dw3wtq\", NULL, MTX_DEF);\n+\twq->abort = 0;\n+\n+\treturn wq;\n+}\n+\n+void DWC_WAITQ_FREE(dwc_waitq_t *wq)\n+{\n+\tmtx_destroy(&wq->lock);\n+\tDWC_FREE(wq);\n+}\n+\n+int32_t DWC_WAITQ_WAIT(dwc_waitq_t *wq, dwc_waitq_condition_t cond, void *data)\n+{\n+//\tintrmask_t ipl;\n+\tint result = 0;\n+\n+\tmtx_lock(&wq->lock);\n+//\tipl = splbio();\n+\n+\t/* Skip the sleep if already aborted or triggered */\n+\tif (!wq->abort && !cond(data)) {\n+//\t\tsplx(ipl);\n+\t\tresult = msleep(wq, &wq->lock, PCATCH, \"dw3wat\", 0); // infinite timeout\n+//\t\tipl = splbio();\n+\t}\n+\n+\tif (result == ERESTART) {\t// signaled - restart\n+\t\tresult = -DWC_E_RESTART;\n+\n+\t} else if (result == EINTR) {\t// signaled - interrupt\n+\t\tresult = -DWC_E_ABORT;\n+\n+\t} else if (wq->abort) {\n+\t\tresult = -DWC_E_ABORT;\n+\n+\t} else {\n+\t\tresult = 0;\n+\t}\n+\n+\twq->abort = 0;\n+//\tsplx(ipl);\n+\tmtx_unlock(&wq->lock);\n+\treturn result;\n+}\n+\n+int32_t DWC_WAITQ_WAIT_TIMEOUT(dwc_waitq_t *wq, dwc_waitq_condition_t cond,\n+\t\t\t       void *data, int32_t msecs)\n+{\n+\tstruct timeval tv, tv1, tv2;\n+//\tintrmask_t ipl;\n+\tint result = 0;\n+\n+\ttv.tv_sec = msecs / 1000;\n+\ttv.tv_usec = (msecs - tv.tv_sec * 1000) * 1000;\n+\n+\tmtx_lock(&wq->lock);\n+//\tipl = splbio();\n+\n+\t/* Skip the sleep if already aborted or triggered */\n+\tif (!wq->abort && !cond(data)) {\n+//\t\tsplx(ipl);\n+\t\tgetmicrouptime(&tv1);\n+\t\tresult = msleep(wq, &wq->lock, PCATCH, \"dw3wto\", tvtohz(&tv));\n+\t\tgetmicrouptime(&tv2);\n+//\t\tipl = splbio();\n+\t}\n+\n+\tif (result == 0) {\t\t\t// awoken\n+\t\tif (wq->abort) {\n+\t\t\tresult = -DWC_E_ABORT;\n+\t\t} else {\n+\t\t\ttv2.tv_usec -= tv1.tv_usec;\n+\t\t\tif (tv2.tv_usec < 0) {\n+\t\t\t\ttv2.tv_usec += 1000000;\n+\t\t\t\ttv2.tv_sec--;\n+\t\t\t}\n+\n+\t\t\ttv2.tv_sec -= tv1.tv_sec;\n+\t\t\tresult = tv2.tv_sec * 1000 + tv2.tv_usec / 1000;\n+\t\t\tresult = msecs - result;\n+\t\t\tif (result <= 0)\n+\t\t\t\tresult = 1;\n+\t\t}\n+\t} else if (result == ERESTART) {\t// signaled - restart\n+\t\tresult = -DWC_E_RESTART;\n+\n+\t} else if (result == EINTR) {\t\t// signaled - interrupt\n+\t\tresult = -DWC_E_ABORT;\n+\n+\t} else {\t\t\t\t// timed out\n+\t\tresult = -DWC_E_TIMEOUT;\n+\t}\n+\n+\twq->abort = 0;\n+//\tsplx(ipl);\n+\tmtx_unlock(&wq->lock);\n+\treturn result;\n+}\n+\n+void DWC_WAITQ_TRIGGER(dwc_waitq_t *wq)\n+{\n+\twakeup(wq);\n+}\n+\n+void DWC_WAITQ_ABORT(dwc_waitq_t *wq)\n+{\n+//\tintrmask_t ipl;\n+\n+\tmtx_lock(&wq->lock);\n+//\tipl = splbio();\n+\twq->abort = 1;\n+\twakeup(wq);\n+//\tsplx(ipl);\n+\tmtx_unlock(&wq->lock);\n+}\n+\n+\n+/* Threading */\n+\n+struct dwc_thread {\n+\tstruct proc *proc;\n+\tint abort;\n+};\n+\n+dwc_thread_t *DWC_THREAD_RUN(dwc_thread_function_t func, char *name, void *data)\n+{\n+\tint retval;\n+\tdwc_thread_t *thread = DWC_ALLOC(sizeof(*thread));\n+\n+\tif (!thread) {\n+\t\treturn NULL;\n+\t}\n+\n+\tthread->abort = 0;\n+\tretval = kthread_create((void (*)(void *))func, data, &thread->proc,\n+\t\t\t\tRFPROC | RFNOWAIT, 0, \"%s\", name);\n+\tif (retval) {\n+\t\tDWC_FREE(thread);\n+\t\treturn NULL;\n+\t}\n+\n+\treturn thread;\n+}\n+\n+int DWC_THREAD_STOP(dwc_thread_t *thread)\n+{\n+\tint retval;\n+\n+\tthread->abort = 1;\n+\tretval = tsleep(&thread->abort, 0, \"dw3stp\", 60 * hz);\n+\n+\tif (retval == 0) {\n+\t\t/* DWC_THREAD_EXIT() will free the thread struct */\n+\t\treturn 0;\n+\t}\n+\n+\t/* NOTE: We leak the thread struct if thread doesn't die */\n+\n+\tif (retval == EWOULDBLOCK) {\n+\t\treturn -DWC_E_TIMEOUT;\n+\t}\n+\n+\treturn -DWC_E_UNKNOWN;\n+}\n+\n+dwc_bool_t DWC_THREAD_SHOULD_STOP(dwc_thread_t *thread)\n+{\n+\treturn thread->abort;\n+}\n+\n+void DWC_THREAD_EXIT(dwc_thread_t *thread)\n+{\n+\twakeup(&thread->abort);\n+\tDWC_FREE(thread);\n+\tkthread_exit(0);\n+}\n+\n+\n+/* tasklets\n+ - Runs in interrupt context (cannot sleep)\n+ - Each tasklet runs on a single CPU [ How can we ensure this on FreeBSD? Does it matter? ]\n+ - Different tasklets can be running simultaneously on different CPUs [ shouldn't matter ]\n+ */\n+struct dwc_tasklet {\n+\tstruct task t;\n+\tdwc_tasklet_callback_t cb;\n+\tvoid *data;\n+};\n+\n+static void tasklet_callback(void *data, int pending)\t// what to do with pending ???\n+{\n+\tdwc_tasklet_t *task = (dwc_tasklet_t *)data;\n+\n+\ttask->cb(task->data);\n+}\n+\n+dwc_tasklet_t *DWC_TASK_ALLOC(char *name, dwc_tasklet_callback_t cb, void *data)\n+{\n+\tdwc_tasklet_t *task = DWC_ALLOC(sizeof(*task));\n+\n+\tif (task) {\n+\t\ttask->cb = cb;\n+\t\ttask->data = data;\n+\t\tTASK_INIT(&task->t, 0, tasklet_callback, task);\n+\t} else {\n+\t\tDWC_ERROR(\"Cannot allocate memory for tasklet\");\n+\t}\n+\n+\treturn task;\n+}\n+\n+void DWC_TASK_FREE(dwc_tasklet_t *task)\n+{\n+\ttaskqueue_drain(taskqueue_fast, &task->t);\t// ???\n+\tDWC_FREE(task);\n+}\n+\n+void DWC_TASK_SCHEDULE(dwc_tasklet_t *task)\n+{\n+\t/* Uses predefined system queue */\n+\ttaskqueue_enqueue_fast(taskqueue_fast, &task->t);\n+}\n+\n+\n+/* workqueues\n+ - Runs in process context (can sleep)\n+ */\n+typedef struct work_container {\n+\tdwc_work_callback_t cb;\n+\tvoid *data;\n+\tdwc_workq_t *wq;\n+\tchar *name;\n+\tint hz;\n+\n+#ifdef DEBUG\n+\tDWC_CIRCLEQ_ENTRY(work_container) entry;\n+#endif\n+\tstruct task task;\n+} work_container_t;\n+\n+#ifdef DEBUG\n+DWC_CIRCLEQ_HEAD(work_container_queue, work_container);\n+#endif\n+\n+struct dwc_workq {\n+\tstruct taskqueue *taskq;\n+\tdwc_spinlock_t *lock;\n+\tdwc_waitq_t *waitq;\n+\tint pending;\n+\n+#ifdef DEBUG\n+\tstruct work_container_queue entries;\n+#endif\n+};\n+\n+static void do_work(void *data, int pending)\t// what to do with pending ???\n+{\n+\twork_container_t *container = (work_container_t *)data;\n+\tdwc_workq_t *wq = container->wq;\n+\tdwc_irqflags_t flags;\n+\n+\tif (container->hz) {\n+\t\tpause(\"dw3wrk\", container->hz);\n+\t}\n+\n+\tcontainer->cb(container->data);\n+\tDWC_DEBUG(\"Work done: %s, container=%p\", container->name, container);\n+\n+\tDWC_SPINLOCK_IRQSAVE(wq->lock, &flags);\n+\n+#ifdef DEBUG\n+\tDWC_CIRCLEQ_REMOVE(&wq->entries, container, entry);\n+#endif\n+\tif (container->name)\n+\t\tDWC_FREE(container->name);\n+\tDWC_FREE(container);\n+\twq->pending--;\n+\tDWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags);\n+\tDWC_WAITQ_TRIGGER(wq->waitq);\n+}\n+\n+static int work_done(void *data)\n+{\n+\tdwc_workq_t *workq = (dwc_workq_t *)data;\n+\n+\treturn workq->pending == 0;\n+}\n+\n+int DWC_WORKQ_WAIT_WORK_DONE(dwc_workq_t *workq, int timeout)\n+{\n+\treturn DWC_WAITQ_WAIT_TIMEOUT(workq->waitq, work_done, workq, timeout);\n+}\n+\n+dwc_workq_t *DWC_WORKQ_ALLOC(char *name)\n+{\n+\tdwc_workq_t *wq = DWC_ALLOC(sizeof(*wq));\n+\n+\tif (!wq) {\n+\t\tDWC_ERROR(\"Cannot allocate memory for workqueue\");\n+\t\treturn NULL;\n+\t}\n+\n+\twq->taskq = taskqueue_create(name, M_NOWAIT, taskqueue_thread_enqueue, &wq->taskq);\n+\tif (!wq->taskq) {\n+\t\tDWC_ERROR(\"Cannot allocate memory for taskqueue\");\n+\t\tgoto no_taskq;\n+\t}\n+\n+\twq->pending = 0;\n+\n+\twq->lock = DWC_SPINLOCK_ALLOC();\n+\tif (!wq->lock) {\n+\t\tDWC_ERROR(\"Cannot allocate memory for spinlock\");\n+\t\tgoto no_lock;\n+\t}\n+\n+\twq->waitq = DWC_WAITQ_ALLOC();\n+\tif (!wq->waitq) {\n+\t\tDWC_ERROR(\"Cannot allocate memory for waitqueue\");\n+\t\tgoto no_waitq;\n+\t}\n+\n+\ttaskqueue_start_threads(&wq->taskq, 1, PWAIT, \"%s taskq\", \"dw3tsk\");\n+\n+#ifdef DEBUG\n+\tDWC_CIRCLEQ_INIT(&wq->entries);\n+#endif\n+\treturn wq;\n+\n+ no_waitq:\n+\tDWC_SPINLOCK_FREE(wq->lock);\n+ no_lock:\n+\ttaskqueue_free(wq->taskq);\n+ no_taskq:\n+\tDWC_FREE(wq);\n+\n+\treturn NULL;\n+}\n+\n+void DWC_WORKQ_FREE(dwc_workq_t *wq)\n+{\n+#ifdef DEBUG\n+\tdwc_irqflags_t flags;\n+\n+\tDWC_SPINLOCK_IRQSAVE(wq->lock, &flags);\n+\n+\tif (wq->pending != 0) {\n+\t\tstruct work_container *container;\n+\n+\t\tDWC_ERROR(\"Destroying work queue with pending work\");\n+\n+\t\tDWC_CIRCLEQ_FOREACH(container, &wq->entries, entry) {\n+\t\t\tDWC_ERROR(\"Work %s still pending\", container->name);\n+\t\t}\n+\t}\n+\n+\tDWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags);\n+#endif\n+\tDWC_WAITQ_FREE(wq->waitq);\n+\tDWC_SPINLOCK_FREE(wq->lock);\n+\ttaskqueue_free(wq->taskq);\n+\tDWC_FREE(wq);\n+}\n+\n+void DWC_WORKQ_SCHEDULE(dwc_workq_t *wq, dwc_work_callback_t cb, void *data,\n+\t\t\tchar *format, ...)\n+{\n+\tdwc_irqflags_t flags;\n+\twork_container_t *container;\n+\tstatic char name[128];\n+\tva_list args;\n+\n+\tva_start(args, format);\n+\tDWC_VSNPRINTF(name, 128, format, args);\n+\tva_end(args);\n+\n+\tDWC_SPINLOCK_IRQSAVE(wq->lock, &flags);\n+\twq->pending++;\n+\tDWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags);\n+\tDWC_WAITQ_TRIGGER(wq->waitq);\n+\n+\tcontainer = DWC_ALLOC_ATOMIC(sizeof(*container));\n+\tif (!container) {\n+\t\tDWC_ERROR(\"Cannot allocate memory for container\");\n+\t\treturn;\n+\t}\n+\n+\tcontainer->name = DWC_STRDUP(name);\n+\tif (!container->name) {\n+\t\tDWC_ERROR(\"Cannot allocate memory for container->name\");\n+\t\tDWC_FREE(container);\n+\t\treturn;\n+\t}\n+\n+\tcontainer->cb = cb;\n+\tcontainer->data = data;\n+\tcontainer->wq = wq;\n+\tcontainer->hz = 0;\n+\n+\tDWC_DEBUG(\"Queueing work: %s, container=%p\", container->name, container);\n+\n+\tTASK_INIT(&container->task, 0, do_work, container);\n+\n+#ifdef DEBUG\n+\tDWC_CIRCLEQ_INSERT_TAIL(&wq->entries, container, entry);\n+#endif\n+\ttaskqueue_enqueue_fast(wq->taskq, &container->task);\n+}\n+\n+void DWC_WORKQ_SCHEDULE_DELAYED(dwc_workq_t *wq, dwc_work_callback_t cb,\n+\t\t\t\tvoid *data, uint32_t time, char *format, ...)\n+{\n+\tdwc_irqflags_t flags;\n+\twork_container_t *container;\n+\tstatic char name[128];\n+\tstruct timeval tv;\n+\tva_list args;\n+\n+\tva_start(args, format);\n+\tDWC_VSNPRINTF(name, 128, format, args);\n+\tva_end(args);\n+\n+\tDWC_SPINLOCK_IRQSAVE(wq->lock, &flags);\n+\twq->pending++;\n+\tDWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags);\n+\tDWC_WAITQ_TRIGGER(wq->waitq);\n+\n+\tcontainer = DWC_ALLOC_ATOMIC(sizeof(*container));\n+\tif (!container) {\n+\t\tDWC_ERROR(\"Cannot allocate memory for container\");\n+\t\treturn;\n+\t}\n+\n+\tcontainer->name = DWC_STRDUP(name);\n+\tif (!container->name) {\n+\t\tDWC_ERROR(\"Cannot allocate memory for container->name\");\n+\t\tDWC_FREE(container);\n+\t\treturn;\n+\t}\n+\n+\tcontainer->cb = cb;\n+\tcontainer->data = data;\n+\tcontainer->wq = wq;\n+\n+\ttv.tv_sec = time / 1000;\n+\ttv.tv_usec = (time - tv.tv_sec * 1000) * 1000;\n+\tcontainer->hz = tvtohz(&tv);\n+\n+\tDWC_DEBUG(\"Queueing work: %s, container=%p\", container->name, container);\n+\n+\tTASK_INIT(&container->task, 0, do_work, container);\n+\n+#ifdef DEBUG\n+\tDWC_CIRCLEQ_INSERT_TAIL(&wq->entries, container, entry);\n+#endif\n+\ttaskqueue_enqueue_fast(wq->taskq, &container->task);\n+}\n+\n+int DWC_WORKQ_PENDING(dwc_workq_t *wq)\n+{\n+\treturn wq->pending;\n+}\n--- /dev/null\n+++ b/drivers/usb/host/dwc_common_port/dwc_common_linux.c\n@@ -0,0 +1,1409 @@\n+#include <linux/kernel.h>\n+#include <linux/init.h>\n+#include <linux/module.h>\n+#include <linux/kthread.h>\n+\n+#ifdef DWC_CCLIB\n+# include \"dwc_cc.h\"\n+#endif\n+\n+#ifdef DWC_CRYPTOLIB\n+# include \"dwc_modpow.h\"\n+# include \"dwc_dh.h\"\n+# include \"dwc_crypto.h\"\n+#endif\n+\n+#ifdef DWC_NOTIFYLIB\n+# include \"dwc_notifier.h\"\n+#endif\n+\n+/* OS-Level Implementations */\n+\n+/* This is the Linux kernel implementation of the DWC platform library. */\n+#include <linux/moduleparam.h>\n+#include <linux/ctype.h>\n+#include <linux/crypto.h>\n+#include <linux/delay.h>\n+#include <linux/device.h>\n+#include <linux/dma-mapping.h>\n+#include <linux/cdev.h>\n+#include <linux/errno.h>\n+#include <linux/interrupt.h>\n+#include <linux/jiffies.h>\n+#include <linux/list.h>\n+#include <linux/pci.h>\n+#include <linux/random.h>\n+#include <linux/scatterlist.h>\n+#include <linux/slab.h>\n+#include <linux/stat.h>\n+#include <linux/string.h>\n+#include <linux/timer.h>\n+#include <linux/usb.h>\n+\n+#include <linux/version.h>\n+\n+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24)\n+# include <linux/usb/gadget.h>\n+#else\n+# include <linux/usb_gadget.h>\n+#endif\n+\n+#include <asm/io.h>\n+#include <asm/page.h>\n+#include <asm/uaccess.h>\n+#include <asm/unaligned.h>\n+\n+#include \"dwc_os.h\"\n+#include \"dwc_list.h\"\n+\n+\n+/* MISC */\n+\n+void *DWC_MEMSET(void *dest, uint8_t byte, uint32_t size)\n+{\n+\treturn memset(dest, byte, size);\n+}\n+\n+void *DWC_MEMCPY(void *dest, void const *src, uint32_t size)\n+{\n+\treturn memcpy(dest, src, size);\n+}\n+\n+void *DWC_MEMMOVE(void *dest, void *src, uint32_t size)\n+{\n+\treturn memmove(dest, src, size);\n+}\n+\n+int DWC_MEMCMP(void *m1, void *m2, uint32_t size)\n+{\n+\treturn memcmp(m1, m2, size);\n+}\n+\n+int DWC_STRNCMP(void *s1, void *s2, uint32_t size)\n+{\n+\treturn strncmp(s1, s2, size);\n+}\n+\n+int DWC_STRCMP(void *s1, void *s2)\n+{\n+\treturn strcmp(s1, s2);\n+}\n+\n+int DWC_STRLEN(char const *str)\n+{\n+\treturn strlen(str);\n+}\n+\n+char *DWC_STRCPY(char *to, char const *from)\n+{\n+\treturn strcpy(to, from);\n+}\n+\n+char *DWC_STRDUP(char const *str)\n+{\n+\tint len = DWC_STRLEN(str) + 1;\n+\tchar *new = DWC_ALLOC_ATOMIC(len);\n+\n+\tif (!new) {\n+\t\treturn NULL;\n+\t}\n+\n+\tDWC_MEMCPY(new, str, len);\n+\treturn new;\n+}\n+\n+int DWC_ATOI(const char *str, int32_t *value)\n+{\n+\tchar *end = NULL;\n+\n+\t*value = simple_strtol(str, &end, 0);\n+\tif (*end == '\\0') {\n+\t\treturn 0;\n+\t}\n+\n+\treturn -1;\n+}\n+\n+int DWC_ATOUI(const char *str, uint32_t *value)\n+{\n+\tchar *end = NULL;\n+\n+\t*value = simple_strtoul(str, &end, 0);\n+\tif (*end == '\\0') {\n+\t\treturn 0;\n+\t}\n+\n+\treturn -1;\n+}\n+\n+\n+#ifdef DWC_UTFLIB\n+/* From usbstring.c */\n+\n+int DWC_UTF8_TO_UTF16LE(uint8_t const *s, uint16_t *cp, unsigned len)\n+{\n+\tint\tcount = 0;\n+\tu8\tc;\n+\tu16\tuchar;\n+\n+\t/* this insists on correct encodings, though not minimal ones.\n+\t * BUT it currently rejects legit 4-byte UTF-8 code points,\n+\t * which need surrogate pairs.  (Unicode 3.1 can use them.)\n+\t */\n+\twhile (len != 0 && (c = (u8) *s++) != 0) {\n+\t\tif (unlikely(c & 0x80)) {\n+\t\t\t// 2-byte sequence:\n+\t\t\t// 00000yyyyyxxxxxx = 110yyyyy 10xxxxxx\n+\t\t\tif ((c & 0xe0) == 0xc0) {\n+\t\t\t\tuchar = (c & 0x1f) << 6;\n+\n+\t\t\t\tc = (u8) *s++;\n+\t\t\t\tif ((c & 0xc0) != 0xc0)\n+\t\t\t\t\tgoto fail;\n+\t\t\t\tc &= 0x3f;\n+\t\t\t\tuchar |= c;\n+\n+\t\t\t// 3-byte sequence (most CJKV characters):\n+\t\t\t// zzzzyyyyyyxxxxxx = 1110zzzz 10yyyyyy 10xxxxxx\n+\t\t\t} else if ((c & 0xf0) == 0xe0) {\n+\t\t\t\tuchar = (c & 0x0f) << 12;\n+\n+\t\t\t\tc = (u8) *s++;\n+\t\t\t\tif ((c & 0xc0) != 0xc0)\n+\t\t\t\t\tgoto fail;\n+\t\t\t\tc &= 0x3f;\n+\t\t\t\tuchar |= c << 6;\n+\n+\t\t\t\tc = (u8) *s++;\n+\t\t\t\tif ((c & 0xc0) != 0xc0)\n+\t\t\t\t\tgoto fail;\n+\t\t\t\tc &= 0x3f;\n+\t\t\t\tuchar |= c;\n+\n+\t\t\t\t/* no bogus surrogates */\n+\t\t\t\tif (0xd800 <= uchar && uchar <= 0xdfff)\n+\t\t\t\t\tgoto fail;\n+\n+\t\t\t// 4-byte sequence (surrogate pairs, currently rare):\n+\t\t\t// 11101110wwwwzzzzyy + 110111yyyyxxxxxx\n+\t\t\t//     = 11110uuu 10uuzzzz 10yyyyyy 10xxxxxx\n+\t\t\t// (uuuuu = wwww + 1)\n+\t\t\t// FIXME accept the surrogate code points (only)\n+\t\t\t} else\n+\t\t\t\tgoto fail;\n+\t\t} else\n+\t\t\tuchar = c;\n+\t\tput_unaligned (cpu_to_le16 (uchar), cp++);\n+\t\tcount++;\n+\t\tlen--;\n+\t}\n+\treturn count;\n+fail:\n+\treturn -1;\n+}\n+#endif\t/* DWC_UTFLIB */\n+\n+\n+/* dwc_debug.h */\n+\n+dwc_bool_t DWC_IN_IRQ(void)\n+{\n+\treturn in_irq();\n+}\n+\n+dwc_bool_t DWC_IN_BH(void)\n+{\n+\treturn in_softirq();\n+}\n+\n+void DWC_VPRINTF(char *format, va_list args)\n+{\n+\tvprintk(format, args);\n+}\n+\n+int DWC_VSNPRINTF(char *str, int size, char *format, va_list args)\n+{\n+\treturn vsnprintf(str, size, format, args);\n+}\n+\n+void DWC_PRINTF(char *format, ...)\n+{\n+\tva_list args;\n+\n+\tva_start(args, format);\n+\tDWC_VPRINTF(format, args);\n+\tva_end(args);\n+}\n+\n+int DWC_SPRINTF(char *buffer, char *format, ...)\n+{\n+\tint retval;\n+\tva_list args;\n+\n+\tva_start(args, format);\n+\tretval = vsprintf(buffer, format, args);\n+\tva_end(args);\n+\treturn retval;\n+}\n+\n+int DWC_SNPRINTF(char *buffer, int size, char *format, ...)\n+{\n+\tint retval;\n+\tva_list args;\n+\n+\tva_start(args, format);\n+\tretval = vsnprintf(buffer, size, format, args);\n+\tva_end(args);\n+\treturn retval;\n+}\n+\n+void __DWC_WARN(char *format, ...)\n+{\n+\tva_list args;\n+\n+\tva_start(args, format);\n+\tDWC_PRINTF(KERN_WARNING);\n+\tDWC_VPRINTF(format, args);\n+\tva_end(args);\n+}\n+\n+void __DWC_ERROR(char *format, ...)\n+{\n+\tva_list args;\n+\n+\tva_start(args, format);\n+\tDWC_PRINTF(KERN_ERR);\n+\tDWC_VPRINTF(format, args);\n+\tva_end(args);\n+}\n+\n+void DWC_EXCEPTION(char *format, ...)\n+{\n+\tva_list args;\n+\n+\tva_start(args, format);\n+\tDWC_PRINTF(KERN_ERR);\n+\tDWC_VPRINTF(format, args);\n+\tva_end(args);\n+\tBUG_ON(1);\n+}\n+\n+#ifdef DEBUG\n+void __DWC_DEBUG(char *format, ...)\n+{\n+\tva_list args;\n+\n+\tva_start(args, format);\n+\tDWC_PRINTF(KERN_DEBUG);\n+\tDWC_VPRINTF(format, args);\n+\tva_end(args);\n+}\n+#endif\n+\n+\n+/* dwc_mem.h */\n+\n+#if 0\n+dwc_pool_t *DWC_DMA_POOL_CREATE(uint32_t size,\n+\t\t\t\tuint32_t align,\n+\t\t\t\tuint32_t alloc)\n+{\n+\tstruct dma_pool *pool = dma_pool_create(\"Pool\", NULL,\n+\t\t\t\t\t\tsize, align, alloc);\n+\treturn (dwc_pool_t *)pool;\n+}\n+\n+void DWC_DMA_POOL_DESTROY(dwc_pool_t *pool)\n+{\n+\tdma_pool_destroy((struct dma_pool *)pool);\n+}\n+\n+void *DWC_DMA_POOL_ALLOC(dwc_pool_t *pool, uint64_t *dma_addr)\n+{\n+\treturn dma_pool_alloc((struct dma_pool *)pool, GFP_KERNEL, dma_addr);\n+}\n+\n+void *DWC_DMA_POOL_ZALLOC(dwc_pool_t *pool, uint64_t *dma_addr)\n+{\n+\tvoid *vaddr = DWC_DMA_POOL_ALLOC(pool, dma_addr);\n+\tmemset(..);\n+}\n+\n+void DWC_DMA_POOL_FREE(dwc_pool_t *pool, void *vaddr, void *daddr)\n+{\n+\tdma_pool_free(pool, vaddr, daddr);\n+}\n+#endif\n+\n+void *__DWC_DMA_ALLOC(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr)\n+{\n+\treturn dma_alloc_coherent(dma_ctx, size, dma_addr, GFP_KERNEL | GFP_DMA32);\n+}\n+\n+void *__DWC_DMA_ALLOC_ATOMIC(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr)\n+{\n+\treturn dma_alloc_coherent(dma_ctx, size, dma_addr, GFP_ATOMIC);\n+}\n+\n+void __DWC_DMA_FREE(void *dma_ctx, uint32_t size, void *virt_addr, dwc_dma_t dma_addr)\n+{\n+\tdma_free_coherent(dma_ctx, size, virt_addr, dma_addr);\n+}\n+\n+void *__DWC_ALLOC(void *mem_ctx, uint32_t size)\n+{\n+\treturn kzalloc(size, GFP_KERNEL);\n+}\n+\n+void *__DWC_ALLOC_ATOMIC(void *mem_ctx, uint32_t size)\n+{\n+\treturn kzalloc(size, GFP_ATOMIC);\n+}\n+\n+void __DWC_FREE(void *mem_ctx, void *addr)\n+{\n+\tkfree(addr);\n+}\n+\n+\n+#ifdef DWC_CRYPTOLIB\n+/* dwc_crypto.h */\n+\n+void DWC_RANDOM_BYTES(uint8_t *buffer, uint32_t length)\n+{\n+\tget_random_bytes(buffer, length);\n+}\n+\n+int DWC_AES_CBC(uint8_t *message, uint32_t messagelen, uint8_t *key, uint32_t keylen, uint8_t iv[16], uint8_t *out)\n+{\n+\tstruct crypto_blkcipher *tfm;\n+\tstruct blkcipher_desc desc;\n+\tstruct scatterlist sgd;\n+\tstruct scatterlist sgs;\n+\n+\ttfm = crypto_alloc_blkcipher(\"cbc(aes)\", 0, CRYPTO_ALG_ASYNC);\n+\tif (tfm == NULL) {\n+\t\tprintk(\"failed to load transform for aes CBC\\n\");\n+\t\treturn -1;\n+\t}\n+\n+\tcrypto_blkcipher_setkey(tfm, key, keylen);\n+\tcrypto_blkcipher_set_iv(tfm, iv, 16);\n+\n+\tsg_init_one(&sgd, out, messagelen);\n+\tsg_init_one(&sgs, message, messagelen);\n+\n+\tdesc.tfm = tfm;\n+\tdesc.flags = 0;\n+\n+\tif (crypto_blkcipher_encrypt(&desc, &sgd, &sgs, messagelen)) {\n+\t\tcrypto_free_blkcipher(tfm);\n+\t\tDWC_ERROR(\"AES CBC encryption failed\");\n+\t\treturn -1;\n+\t}\n+\n+\tcrypto_free_blkcipher(tfm);\n+\treturn 0;\n+}\n+\n+int DWC_SHA256(uint8_t *message, uint32_t len, uint8_t *out)\n+{\n+\tstruct crypto_hash *tfm;\n+\tstruct hash_desc desc;\n+\tstruct scatterlist sg;\n+\n+\ttfm = crypto_alloc_hash(\"sha256\", 0, CRYPTO_ALG_ASYNC);\n+\tif (IS_ERR(tfm)) {\n+\t\tDWC_ERROR(\"Failed to load transform for sha256: %ld\\n\", PTR_ERR(tfm));\n+\t\treturn 0;\n+\t}\n+\tdesc.tfm = tfm;\n+\tdesc.flags = 0;\n+\n+\tsg_init_one(&sg, message, len);\n+\tcrypto_hash_digest(&desc, &sg, len, out);\n+\tcrypto_free_hash(tfm);\n+\n+\treturn 1;\n+}\n+\n+int DWC_HMAC_SHA256(uint8_t *message, uint32_t messagelen,\n+\t\t    uint8_t *key, uint32_t keylen, uint8_t *out)\n+{\n+\tstruct crypto_hash *tfm;\n+\tstruct hash_desc desc;\n+\tstruct scatterlist sg;\n+\n+\ttfm = crypto_alloc_hash(\"hmac(sha256)\", 0, CRYPTO_ALG_ASYNC);\n+\tif (IS_ERR(tfm)) {\n+\t\tDWC_ERROR(\"Failed to load transform for hmac(sha256): %ld\\n\", PTR_ERR(tfm));\n+\t\treturn 0;\n+\t}\n+\tdesc.tfm = tfm;\n+\tdesc.flags = 0;\n+\n+\tsg_init_one(&sg, message, messagelen);\n+\tcrypto_hash_setkey(tfm, key, keylen);\n+\tcrypto_hash_digest(&desc, &sg, messagelen, out);\n+\tcrypto_free_hash(tfm);\n+\n+\treturn 1;\n+}\n+#endif\t/* DWC_CRYPTOLIB */\n+\n+\n+/* Byte Ordering Conversions */\n+\n+uint32_t DWC_CPU_TO_LE32(uint32_t *p)\n+{\n+#ifdef __LITTLE_ENDIAN\n+\treturn *p;\n+#else\n+\tuint8_t *u_p = (uint8_t *)p;\n+\n+\treturn (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24));\n+#endif\n+}\n+\n+uint32_t DWC_CPU_TO_BE32(uint32_t *p)\n+{\n+#ifdef __BIG_ENDIAN\n+\treturn *p;\n+#else\n+\tuint8_t *u_p = (uint8_t *)p;\n+\n+\treturn (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24));\n+#endif\n+}\n+\n+uint32_t DWC_LE32_TO_CPU(uint32_t *p)\n+{\n+#ifdef __LITTLE_ENDIAN\n+\treturn *p;\n+#else\n+\tuint8_t *u_p = (uint8_t *)p;\n+\n+\treturn (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24));\n+#endif\n+}\n+\n+uint32_t DWC_BE32_TO_CPU(uint32_t *p)\n+{\n+#ifdef __BIG_ENDIAN\n+\treturn *p;\n+#else\n+\tuint8_t *u_p = (uint8_t *)p;\n+\n+\treturn (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24));\n+#endif\n+}\n+\n+uint16_t DWC_CPU_TO_LE16(uint16_t *p)\n+{\n+#ifdef __LITTLE_ENDIAN\n+\treturn *p;\n+#else\n+\tuint8_t *u_p = (uint8_t *)p;\n+\treturn (u_p[1] | (u_p[0] << 8));\n+#endif\n+}\n+\n+uint16_t DWC_CPU_TO_BE16(uint16_t *p)\n+{\n+#ifdef __BIG_ENDIAN\n+\treturn *p;\n+#else\n+\tuint8_t *u_p = (uint8_t *)p;\n+\treturn (u_p[1] | (u_p[0] << 8));\n+#endif\n+}\n+\n+uint16_t DWC_LE16_TO_CPU(uint16_t *p)\n+{\n+#ifdef __LITTLE_ENDIAN\n+\treturn *p;\n+#else\n+\tuint8_t *u_p = (uint8_t *)p;\n+\treturn (u_p[1] | (u_p[0] << 8));\n+#endif\n+}\n+\n+uint16_t DWC_BE16_TO_CPU(uint16_t *p)\n+{\n+#ifdef __BIG_ENDIAN\n+\treturn *p;\n+#else\n+\tuint8_t *u_p = (uint8_t *)p;\n+\treturn (u_p[1] | (u_p[0] << 8));\n+#endif\n+}\n+\n+\n+/* Registers */\n+\n+uint32_t DWC_READ_REG32(uint32_t volatile *reg)\n+{\n+\treturn readl(reg);\n+}\n+\n+#if 0\n+uint64_t DWC_READ_REG64(uint64_t volatile *reg)\n+{\n+}\n+#endif\n+\n+void DWC_WRITE_REG32(uint32_t volatile *reg, uint32_t value)\n+{\n+\twritel(value, reg);\n+}\n+\n+#if 0\n+void DWC_WRITE_REG64(uint64_t volatile *reg, uint64_t value)\n+{\n+}\n+#endif\n+\n+void DWC_MODIFY_REG32(uint32_t volatile *reg, uint32_t clear_mask, uint32_t set_mask)\n+{\n+\twritel((readl(reg) & ~clear_mask) | set_mask, reg);\n+}\n+\n+#if 0\n+void DWC_MODIFY_REG64(uint64_t volatile *reg, uint64_t clear_mask, uint64_t set_mask)\n+{\n+}\n+#endif\n+\n+\n+/* Locking */\n+\n+dwc_spinlock_t *DWC_SPINLOCK_ALLOC(void)\n+{\n+\tspinlock_t *sl = (spinlock_t *)1;\n+\n+#if defined(CONFIG_PREEMPT) || defined(CONFIG_SMP)\n+\tsl = DWC_ALLOC(sizeof(*sl));\n+\tif (!sl) {\n+\t\tDWC_ERROR(\"Cannot allocate memory for spinlock\\n\");\n+\t\treturn NULL;\n+\t}\n+\n+\tspin_lock_init(sl);\n+#endif\n+\treturn (dwc_spinlock_t *)sl;\n+}\n+\n+void DWC_SPINLOCK_FREE(dwc_spinlock_t *lock)\n+{\n+#if defined(CONFIG_PREEMPT) || defined(CONFIG_SMP)\n+\tDWC_FREE(lock);\n+#endif\n+}\n+\n+void DWC_SPINLOCK(dwc_spinlock_t *lock)\n+{\n+#if defined(CONFIG_PREEMPT) || defined(CONFIG_SMP)\n+\tspin_lock((spinlock_t *)lock);\n+#endif\n+}\n+\n+void DWC_SPINUNLOCK(dwc_spinlock_t *lock)\n+{\n+#if defined(CONFIG_PREEMPT) || defined(CONFIG_SMP)\n+\tspin_unlock((spinlock_t *)lock);\n+#endif\n+}\n+\n+void DWC_SPINLOCK_IRQSAVE(dwc_spinlock_t *lock, dwc_irqflags_t *flags)\n+{\n+\tdwc_irqflags_t f;\n+\n+#if defined(CONFIG_PREEMPT) || defined(CONFIG_SMP)\n+\tspin_lock_irqsave((spinlock_t *)lock, f);\n+#else\n+\tlocal_irq_save(f);\n+#endif\n+\t*flags = f;\n+}\n+\n+void DWC_SPINUNLOCK_IRQRESTORE(dwc_spinlock_t *lock, dwc_irqflags_t flags)\n+{\n+#if defined(CONFIG_PREEMPT) || defined(CONFIG_SMP)\n+\tspin_unlock_irqrestore((spinlock_t *)lock, flags);\n+#else\n+\tlocal_irq_restore(flags);\n+#endif\n+}\n+\n+dwc_mutex_t *DWC_MUTEX_ALLOC(void)\n+{\n+\tstruct mutex *m;\n+\tdwc_mutex_t *mutex = (dwc_mutex_t *)DWC_ALLOC(sizeof(struct mutex));\n+\n+\tif (!mutex) {\n+\t\tDWC_ERROR(\"Cannot allocate memory for mutex\\n\");\n+\t\treturn NULL;\n+\t}\n+\n+\tm = (struct mutex *)mutex;\n+\tmutex_init(m);\n+\treturn mutex;\n+}\n+\n+#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_MUTEXES))\n+#else\n+void DWC_MUTEX_FREE(dwc_mutex_t *mutex)\n+{\n+\tmutex_destroy((struct mutex *)mutex);\n+\tDWC_FREE(mutex);\n+}\n+#endif\n+\n+void DWC_MUTEX_LOCK(dwc_mutex_t *mutex)\n+{\n+\tstruct mutex *m = (struct mutex *)mutex;\n+\tmutex_lock(m);\n+}\n+\n+int DWC_MUTEX_TRYLOCK(dwc_mutex_t *mutex)\n+{\n+\tstruct mutex *m = (struct mutex *)mutex;\n+\treturn mutex_trylock(m);\n+}\n+\n+void DWC_MUTEX_UNLOCK(dwc_mutex_t *mutex)\n+{\n+\tstruct mutex *m = (struct mutex *)mutex;\n+\tmutex_unlock(m);\n+}\n+\n+\n+/* Timing */\n+\n+void DWC_UDELAY(uint32_t usecs)\n+{\n+\tudelay(usecs);\n+}\n+\n+void DWC_MDELAY(uint32_t msecs)\n+{\n+\tmdelay(msecs);\n+}\n+\n+void DWC_MSLEEP(uint32_t msecs)\n+{\n+\tmsleep(msecs);\n+}\n+\n+uint32_t DWC_TIME(void)\n+{\n+\treturn jiffies_to_msecs(jiffies);\n+}\n+\n+\n+/* Timers */\n+\n+struct dwc_timer {\n+\tstruct timer_list t;\n+\tchar *name;\n+\tdwc_timer_callback_t cb;\n+\tvoid *data;\n+\tuint8_t scheduled;\n+\tdwc_spinlock_t *lock;\n+};\n+\n+static void timer_callback(struct timer_list *tt)\n+{\n+\tdwc_timer_t *timer = from_timer(timer, tt, t);\n+\tdwc_irqflags_t flags;\n+\n+\tDWC_SPINLOCK_IRQSAVE(timer->lock, &flags);\n+\ttimer->scheduled = 0;\n+\tDWC_SPINUNLOCK_IRQRESTORE(timer->lock, flags);\n+\tDWC_DEBUGC(\"Timer %s callback\", timer->name);\n+\ttimer->cb(timer->data);\n+}\n+\n+dwc_timer_t *DWC_TIMER_ALLOC(char *name, dwc_timer_callback_t cb, void *data)\n+{\n+\tdwc_timer_t *t = DWC_ALLOC(sizeof(*t));\n+\n+\tif (!t) {\n+\t\tDWC_ERROR(\"Cannot allocate memory for timer\");\n+\t\treturn NULL;\n+\t}\n+\n+\tt->name = DWC_STRDUP(name);\n+\tif (!t->name) {\n+\t\tDWC_ERROR(\"Cannot allocate memory for timer->name\");\n+\t\tgoto no_name;\n+\t}\n+\n+#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_SPINLOCK))\n+\tDWC_SPINLOCK_ALLOC_LINUX_DEBUG(t->lock);\n+#else\n+\tt->lock = DWC_SPINLOCK_ALLOC();\n+#endif\n+\tif (!t->lock) {\n+\t\tDWC_ERROR(\"Cannot allocate memory for lock\");\n+\t\tgoto no_lock;\n+\t}\n+\n+\tt->scheduled = 0;\n+\tt->t.expires = jiffies;\n+\ttimer_setup(&t->t, timer_callback, 0);\n+\n+\tt->cb = cb;\n+\tt->data = data;\n+\n+\treturn t;\n+\n+ no_lock:\n+\tDWC_FREE(t->name);\n+ no_name:\n+\tDWC_FREE(t);\n+\treturn NULL;\n+}\n+\n+void DWC_TIMER_FREE(dwc_timer_t *timer)\n+{\n+\tdwc_irqflags_t flags;\n+\n+\tDWC_SPINLOCK_IRQSAVE(timer->lock, &flags);\n+\n+\tif (timer->scheduled) {\n+\t\tdel_timer(&timer->t);\n+\t\ttimer->scheduled = 0;\n+\t}\n+\n+\tDWC_SPINUNLOCK_IRQRESTORE(timer->lock, flags);\n+\tDWC_SPINLOCK_FREE(timer->lock);\n+\tDWC_FREE(timer->name);\n+\tDWC_FREE(timer);\n+}\n+\n+void DWC_TIMER_SCHEDULE(dwc_timer_t *timer, uint32_t time)\n+{\n+\tdwc_irqflags_t flags;\n+\n+\tDWC_SPINLOCK_IRQSAVE(timer->lock, &flags);\n+\n+\tif (!timer->scheduled) {\n+\t\ttimer->scheduled = 1;\n+\t\tDWC_DEBUGC(\"Scheduling timer %s to expire in +%d msec\", timer->name, time);\n+\t\ttimer->t.expires = jiffies + msecs_to_jiffies(time);\n+\t\tadd_timer(&timer->t);\n+\t} else {\n+\t\tDWC_DEBUGC(\"Modifying timer %s to expire in +%d msec\", timer->name, time);\n+\t\tmod_timer(&timer->t, jiffies + msecs_to_jiffies(time));\n+\t}\n+\n+\tDWC_SPINUNLOCK_IRQRESTORE(timer->lock, flags);\n+}\n+\n+void DWC_TIMER_CANCEL(dwc_timer_t *timer)\n+{\n+\tdel_timer(&timer->t);\n+}\n+\n+\n+/* Wait Queues */\n+\n+struct dwc_waitq {\n+\twait_queue_head_t queue;\n+\tint abort;\n+};\n+\n+dwc_waitq_t *DWC_WAITQ_ALLOC(void)\n+{\n+\tdwc_waitq_t *wq = DWC_ALLOC(sizeof(*wq));\n+\n+\tif (!wq) {\n+\t\tDWC_ERROR(\"Cannot allocate memory for waitqueue\\n\");\n+\t\treturn NULL;\n+\t}\n+\n+\tinit_waitqueue_head(&wq->queue);\n+\twq->abort = 0;\n+\treturn wq;\n+}\n+\n+void DWC_WAITQ_FREE(dwc_waitq_t *wq)\n+{\n+\tDWC_FREE(wq);\n+}\n+\n+int32_t DWC_WAITQ_WAIT(dwc_waitq_t *wq, dwc_waitq_condition_t cond, void *data)\n+{\n+\tint result = wait_event_interruptible(wq->queue,\n+\t\t\t\t\t      cond(data) || wq->abort);\n+\tif (result == -ERESTARTSYS) {\n+\t\twq->abort = 0;\n+\t\treturn -DWC_E_RESTART;\n+\t}\n+\n+\tif (wq->abort == 1) {\n+\t\twq->abort = 0;\n+\t\treturn -DWC_E_ABORT;\n+\t}\n+\n+\twq->abort = 0;\n+\n+\tif (result == 0) {\n+\t\treturn 0;\n+\t}\n+\n+\treturn -DWC_E_UNKNOWN;\n+}\n+\n+int32_t DWC_WAITQ_WAIT_TIMEOUT(dwc_waitq_t *wq, dwc_waitq_condition_t cond,\n+\t\t\t       void *data, int32_t msecs)\n+{\n+\tint32_t tmsecs;\n+\tint result = wait_event_interruptible_timeout(wq->queue,\n+\t\t\t\t\t\t      cond(data) || wq->abort,\n+\t\t\t\t\t\t      msecs_to_jiffies(msecs));\n+\tif (result == -ERESTARTSYS) {\n+\t\twq->abort = 0;\n+\t\treturn -DWC_E_RESTART;\n+\t}\n+\n+\tif (wq->abort == 1) {\n+\t\twq->abort = 0;\n+\t\treturn -DWC_E_ABORT;\n+\t}\n+\n+\twq->abort = 0;\n+\n+\tif (result > 0) {\n+\t\ttmsecs = jiffies_to_msecs(result);\n+\t\tif (!tmsecs) {\n+\t\t\treturn 1;\n+\t\t}\n+\n+\t\treturn tmsecs;\n+\t}\n+\n+\tif (result == 0) {\n+\t\treturn -DWC_E_TIMEOUT;\n+\t}\n+\n+\treturn -DWC_E_UNKNOWN;\n+}\n+\n+void DWC_WAITQ_TRIGGER(dwc_waitq_t *wq)\n+{\n+\twq->abort = 0;\n+\twake_up_interruptible(&wq->queue);\n+}\n+\n+void DWC_WAITQ_ABORT(dwc_waitq_t *wq)\n+{\n+\twq->abort = 1;\n+\twake_up_interruptible(&wq->queue);\n+}\n+\n+\n+/* Threading */\n+\n+dwc_thread_t *DWC_THREAD_RUN(dwc_thread_function_t func, char *name, void *data)\n+{\n+\tstruct task_struct *thread = kthread_run(func, data, name);\n+\n+\tif (thread == ERR_PTR(-ENOMEM)) {\n+\t\treturn NULL;\n+\t}\n+\n+\treturn (dwc_thread_t *)thread;\n+}\n+\n+int DWC_THREAD_STOP(dwc_thread_t *thread)\n+{\n+\treturn kthread_stop((struct task_struct *)thread);\n+}\n+\n+dwc_bool_t DWC_THREAD_SHOULD_STOP(void)\n+{\n+\treturn kthread_should_stop();\n+}\n+\n+\n+/* tasklets\n+ - run in interrupt context (cannot sleep)\n+ - each tasklet runs on a single CPU\n+ - different tasklets can be running simultaneously on different CPUs\n+ */\n+struct dwc_tasklet {\n+\tstruct tasklet_struct t;\n+\tdwc_tasklet_callback_t cb;\n+\tvoid *data;\n+};\n+\n+static void tasklet_callback(unsigned long data)\n+{\n+\tdwc_tasklet_t *t = (dwc_tasklet_t *)data;\n+\tt->cb(t->data);\n+}\n+\n+dwc_tasklet_t *DWC_TASK_ALLOC(char *name, dwc_tasklet_callback_t cb, void *data)\n+{\n+\tdwc_tasklet_t *t = DWC_ALLOC(sizeof(*t));\n+\n+\tif (t) {\n+\t\tt->cb = cb;\n+\t\tt->data = data;\n+\t\ttasklet_init(&t->t, tasklet_callback, (unsigned long)t);\n+\t} else {\n+\t\tDWC_ERROR(\"Cannot allocate memory for tasklet\\n\");\n+\t}\n+\n+\treturn t;\n+}\n+\n+void DWC_TASK_FREE(dwc_tasklet_t *task)\n+{\n+\tDWC_FREE(task);\n+}\n+\n+void DWC_TASK_SCHEDULE(dwc_tasklet_t *task)\n+{\n+\ttasklet_schedule(&task->t);\n+}\n+\n+void DWC_TASK_HI_SCHEDULE(dwc_tasklet_t *task)\n+{\n+\ttasklet_hi_schedule(&task->t);\n+}\n+\n+\n+/* workqueues\n+ - run in process context (can sleep)\n+ */\n+typedef struct work_container {\n+\tdwc_work_callback_t cb;\n+\tvoid *data;\n+\tdwc_workq_t *wq;\n+\tchar *name;\n+\n+#ifdef DEBUG\n+\tDWC_CIRCLEQ_ENTRY(work_container) entry;\n+#endif\n+\tstruct delayed_work work;\n+} work_container_t;\n+\n+#ifdef DEBUG\n+DWC_CIRCLEQ_HEAD(work_container_queue, work_container);\n+#endif\n+\n+struct dwc_workq {\n+\tstruct workqueue_struct *wq;\n+\tdwc_spinlock_t *lock;\n+\tdwc_waitq_t *waitq;\n+\tint pending;\n+\n+#ifdef DEBUG\n+\tstruct work_container_queue entries;\n+#endif\n+};\n+\n+static void do_work(struct work_struct *work)\n+{\n+\tdwc_irqflags_t flags;\n+\tstruct delayed_work *dw = container_of(work, struct delayed_work, work);\n+\twork_container_t *container = container_of(dw, struct work_container, work);\n+\tdwc_workq_t *wq = container->wq;\n+\n+\tcontainer->cb(container->data);\n+\n+#ifdef DEBUG\n+\tDWC_CIRCLEQ_REMOVE(&wq->entries, container, entry);\n+#endif\n+\tDWC_DEBUGC(\"Work done: %s, container=%p\", container->name, container);\n+\tif (container->name) {\n+\t\tDWC_FREE(container->name);\n+\t}\n+\tDWC_FREE(container);\n+\n+\tDWC_SPINLOCK_IRQSAVE(wq->lock, &flags);\n+\twq->pending--;\n+\tDWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags);\n+\tDWC_WAITQ_TRIGGER(wq->waitq);\n+}\n+\n+static int work_done(void *data)\n+{\n+\tdwc_workq_t *workq = (dwc_workq_t *)data;\n+\treturn workq->pending == 0;\n+}\n+\n+int DWC_WORKQ_WAIT_WORK_DONE(dwc_workq_t *workq, int timeout)\n+{\n+\treturn DWC_WAITQ_WAIT_TIMEOUT(workq->waitq, work_done, workq, timeout);\n+}\n+\n+dwc_workq_t *DWC_WORKQ_ALLOC(char *name)\n+{\n+\tdwc_workq_t *wq = DWC_ALLOC(sizeof(*wq));\n+\n+\tif (!wq) {\n+\t\treturn NULL;\n+\t}\n+\n+\twq->wq = create_singlethread_workqueue(name);\n+\tif (!wq->wq) {\n+\t\tgoto no_wq;\n+\t}\n+\n+\twq->pending = 0;\n+\n+#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_SPINLOCK))\n+\tDWC_SPINLOCK_ALLOC_LINUX_DEBUG(wq->lock);\n+#else\n+\twq->lock = DWC_SPINLOCK_ALLOC();\n+#endif\n+\tif (!wq->lock) {\n+\t\tgoto no_lock;\n+\t}\n+\n+\twq->waitq = DWC_WAITQ_ALLOC();\n+\tif (!wq->waitq) {\n+\t\tgoto no_waitq;\n+\t}\n+\n+#ifdef DEBUG\n+\tDWC_CIRCLEQ_INIT(&wq->entries);\n+#endif\n+\treturn wq;\n+\n+ no_waitq:\n+\tDWC_SPINLOCK_FREE(wq->lock);\n+ no_lock:\n+\tdestroy_workqueue(wq->wq);\n+ no_wq:\n+\tDWC_FREE(wq);\n+\n+\treturn NULL;\n+}\n+\n+void DWC_WORKQ_FREE(dwc_workq_t *wq)\n+{\n+#ifdef DEBUG\n+\tif (wq->pending != 0) {\n+\t\tstruct work_container *wc;\n+\t\tDWC_ERROR(\"Destroying work queue with pending work\");\n+\t\tDWC_CIRCLEQ_FOREACH(wc, &wq->entries, entry) {\n+\t\t\tDWC_ERROR(\"Work %s still pending\", wc->name);\n+\t\t}\n+\t}\n+#endif\n+\tdestroy_workqueue(wq->wq);\n+\tDWC_SPINLOCK_FREE(wq->lock);\n+\tDWC_WAITQ_FREE(wq->waitq);\n+\tDWC_FREE(wq);\n+}\n+\n+void DWC_WORKQ_SCHEDULE(dwc_workq_t *wq, dwc_work_callback_t cb, void *data,\n+\t\t\tchar *format, ...)\n+{\n+\tdwc_irqflags_t flags;\n+\twork_container_t *container;\n+\tstatic char name[128];\n+\tva_list args;\n+\n+\tva_start(args, format);\n+\tDWC_VSNPRINTF(name, 128, format, args);\n+\tva_end(args);\n+\n+\tDWC_SPINLOCK_IRQSAVE(wq->lock, &flags);\n+\twq->pending++;\n+\tDWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags);\n+\tDWC_WAITQ_TRIGGER(wq->waitq);\n+\n+\tcontainer = DWC_ALLOC_ATOMIC(sizeof(*container));\n+\tif (!container) {\n+\t\tDWC_ERROR(\"Cannot allocate memory for container\\n\");\n+\t\treturn;\n+\t}\n+\n+\tcontainer->name = DWC_STRDUP(name);\n+\tif (!container->name) {\n+\t\tDWC_ERROR(\"Cannot allocate memory for container->name\\n\");\n+\t\tDWC_FREE(container);\n+\t\treturn;\n+\t}\n+\n+\tcontainer->cb = cb;\n+\tcontainer->data = data;\n+\tcontainer->wq = wq;\n+\tDWC_DEBUGC(\"Queueing work: %s, container=%p\", container->name, container);\n+\tINIT_WORK(&container->work.work, do_work);\n+\n+#ifdef DEBUG\n+\tDWC_CIRCLEQ_INSERT_TAIL(&wq->entries, container, entry);\n+#endif\n+\tqueue_work(wq->wq, &container->work.work);\n+}\n+\n+void DWC_WORKQ_SCHEDULE_DELAYED(dwc_workq_t *wq, dwc_work_callback_t cb,\n+\t\t\t\tvoid *data, uint32_t time, char *format, ...)\n+{\n+\tdwc_irqflags_t flags;\n+\twork_container_t *container;\n+\tstatic char name[128];\n+\tva_list args;\n+\n+\tva_start(args, format);\n+\tDWC_VSNPRINTF(name, 128, format, args);\n+\tva_end(args);\n+\n+\tDWC_SPINLOCK_IRQSAVE(wq->lock, &flags);\n+\twq->pending++;\n+\tDWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags);\n+\tDWC_WAITQ_TRIGGER(wq->waitq);\n+\n+\tcontainer = DWC_ALLOC_ATOMIC(sizeof(*container));\n+\tif (!container) {\n+\t\tDWC_ERROR(\"Cannot allocate memory for container\\n\");\n+\t\treturn;\n+\t}\n+\n+\tcontainer->name = DWC_STRDUP(name);\n+\tif (!container->name) {\n+\t\tDWC_ERROR(\"Cannot allocate memory for container->name\\n\");\n+\t\tDWC_FREE(container);\n+\t\treturn;\n+\t}\n+\n+\tcontainer->cb = cb;\n+\tcontainer->data = data;\n+\tcontainer->wq = wq;\n+\tDWC_DEBUGC(\"Queueing work: %s, container=%p\", container->name, container);\n+\tINIT_DELAYED_WORK(&container->work, do_work);\n+\n+#ifdef DEBUG\n+\tDWC_CIRCLEQ_INSERT_TAIL(&wq->entries, container, entry);\n+#endif\n+\tqueue_delayed_work(wq->wq, &container->work, msecs_to_jiffies(time));\n+}\n+\n+int DWC_WORKQ_PENDING(dwc_workq_t *wq)\n+{\n+\treturn wq->pending;\n+}\n+\n+\n+#ifdef DWC_LIBMODULE\n+\n+#ifdef DWC_CCLIB\n+/* CC */\n+EXPORT_SYMBOL(dwc_cc_if_alloc);\n+EXPORT_SYMBOL(dwc_cc_if_free);\n+EXPORT_SYMBOL(dwc_cc_clear);\n+EXPORT_SYMBOL(dwc_cc_add);\n+EXPORT_SYMBOL(dwc_cc_remove);\n+EXPORT_SYMBOL(dwc_cc_change);\n+EXPORT_SYMBOL(dwc_cc_data_for_save);\n+EXPORT_SYMBOL(dwc_cc_restore_from_data);\n+EXPORT_SYMBOL(dwc_cc_match_chid);\n+EXPORT_SYMBOL(dwc_cc_match_cdid);\n+EXPORT_SYMBOL(dwc_cc_ck);\n+EXPORT_SYMBOL(dwc_cc_chid);\n+EXPORT_SYMBOL(dwc_cc_cdid);\n+EXPORT_SYMBOL(dwc_cc_name);\n+#endif\t/* DWC_CCLIB */\n+\n+#ifdef DWC_CRYPTOLIB\n+# ifndef CONFIG_MACH_IPMATE\n+/* Modpow */\n+EXPORT_SYMBOL(dwc_modpow);\n+\n+/* DH */\n+EXPORT_SYMBOL(dwc_dh_modpow);\n+EXPORT_SYMBOL(dwc_dh_derive_keys);\n+EXPORT_SYMBOL(dwc_dh_pk);\n+# endif\t/* CONFIG_MACH_IPMATE */\n+\n+/* Crypto */\n+EXPORT_SYMBOL(dwc_wusb_aes_encrypt);\n+EXPORT_SYMBOL(dwc_wusb_cmf);\n+EXPORT_SYMBOL(dwc_wusb_prf);\n+EXPORT_SYMBOL(dwc_wusb_fill_ccm_nonce);\n+EXPORT_SYMBOL(dwc_wusb_gen_nonce);\n+EXPORT_SYMBOL(dwc_wusb_gen_key);\n+EXPORT_SYMBOL(dwc_wusb_gen_mic);\n+#endif\t/* DWC_CRYPTOLIB */\n+\n+/* Notification */\n+#ifdef DWC_NOTIFYLIB\n+EXPORT_SYMBOL(dwc_alloc_notification_manager);\n+EXPORT_SYMBOL(dwc_free_notification_manager);\n+EXPORT_SYMBOL(dwc_register_notifier);\n+EXPORT_SYMBOL(dwc_unregister_notifier);\n+EXPORT_SYMBOL(dwc_add_observer);\n+EXPORT_SYMBOL(dwc_remove_observer);\n+EXPORT_SYMBOL(dwc_notify);\n+#endif\n+\n+/* Memory Debugging Routines */\n+#ifdef DWC_DEBUG_MEMORY\n+EXPORT_SYMBOL(dwc_alloc_debug);\n+EXPORT_SYMBOL(dwc_alloc_atomic_debug);\n+EXPORT_SYMBOL(dwc_free_debug);\n+EXPORT_SYMBOL(dwc_dma_alloc_debug);\n+EXPORT_SYMBOL(dwc_dma_free_debug);\n+#endif\n+\n+EXPORT_SYMBOL(DWC_MEMSET);\n+EXPORT_SYMBOL(DWC_MEMCPY);\n+EXPORT_SYMBOL(DWC_MEMMOVE);\n+EXPORT_SYMBOL(DWC_MEMCMP);\n+EXPORT_SYMBOL(DWC_STRNCMP);\n+EXPORT_SYMBOL(DWC_STRCMP);\n+EXPORT_SYMBOL(DWC_STRLEN);\n+EXPORT_SYMBOL(DWC_STRCPY);\n+EXPORT_SYMBOL(DWC_STRDUP);\n+EXPORT_SYMBOL(DWC_ATOI);\n+EXPORT_SYMBOL(DWC_ATOUI);\n+\n+#ifdef DWC_UTFLIB\n+EXPORT_SYMBOL(DWC_UTF8_TO_UTF16LE);\n+#endif\t/* DWC_UTFLIB */\n+\n+EXPORT_SYMBOL(DWC_IN_IRQ);\n+EXPORT_SYMBOL(DWC_IN_BH);\n+EXPORT_SYMBOL(DWC_VPRINTF);\n+EXPORT_SYMBOL(DWC_VSNPRINTF);\n+EXPORT_SYMBOL(DWC_PRINTF);\n+EXPORT_SYMBOL(DWC_SPRINTF);\n+EXPORT_SYMBOL(DWC_SNPRINTF);\n+EXPORT_SYMBOL(__DWC_WARN);\n+EXPORT_SYMBOL(__DWC_ERROR);\n+EXPORT_SYMBOL(DWC_EXCEPTION);\n+\n+#ifdef DEBUG\n+EXPORT_SYMBOL(__DWC_DEBUG);\n+#endif\n+\n+EXPORT_SYMBOL(__DWC_DMA_ALLOC);\n+EXPORT_SYMBOL(__DWC_DMA_ALLOC_ATOMIC);\n+EXPORT_SYMBOL(__DWC_DMA_FREE);\n+EXPORT_SYMBOL(__DWC_ALLOC);\n+EXPORT_SYMBOL(__DWC_ALLOC_ATOMIC);\n+EXPORT_SYMBOL(__DWC_FREE);\n+\n+#ifdef DWC_CRYPTOLIB\n+EXPORT_SYMBOL(DWC_RANDOM_BYTES);\n+EXPORT_SYMBOL(DWC_AES_CBC);\n+EXPORT_SYMBOL(DWC_SHA256);\n+EXPORT_SYMBOL(DWC_HMAC_SHA256);\n+#endif\n+\n+EXPORT_SYMBOL(DWC_CPU_TO_LE32);\n+EXPORT_SYMBOL(DWC_CPU_TO_BE32);\n+EXPORT_SYMBOL(DWC_LE32_TO_CPU);\n+EXPORT_SYMBOL(DWC_BE32_TO_CPU);\n+EXPORT_SYMBOL(DWC_CPU_TO_LE16);\n+EXPORT_SYMBOL(DWC_CPU_TO_BE16);\n+EXPORT_SYMBOL(DWC_LE16_TO_CPU);\n+EXPORT_SYMBOL(DWC_BE16_TO_CPU);\n+EXPORT_SYMBOL(DWC_READ_REG32);\n+EXPORT_SYMBOL(DWC_WRITE_REG32);\n+EXPORT_SYMBOL(DWC_MODIFY_REG32);\n+\n+#if 0\n+EXPORT_SYMBOL(DWC_READ_REG64);\n+EXPORT_SYMBOL(DWC_WRITE_REG64);\n+EXPORT_SYMBOL(DWC_MODIFY_REG64);\n+#endif\n+\n+EXPORT_SYMBOL(DWC_SPINLOCK_ALLOC);\n+EXPORT_SYMBOL(DWC_SPINLOCK_FREE);\n+EXPORT_SYMBOL(DWC_SPINLOCK);\n+EXPORT_SYMBOL(DWC_SPINUNLOCK);\n+EXPORT_SYMBOL(DWC_SPINLOCK_IRQSAVE);\n+EXPORT_SYMBOL(DWC_SPINUNLOCK_IRQRESTORE);\n+EXPORT_SYMBOL(DWC_MUTEX_ALLOC);\n+\n+#if (!defined(DWC_LINUX) || !defined(CONFIG_DEBUG_MUTEXES))\n+EXPORT_SYMBOL(DWC_MUTEX_FREE);\n+#endif\n+\n+EXPORT_SYMBOL(DWC_MUTEX_LOCK);\n+EXPORT_SYMBOL(DWC_MUTEX_TRYLOCK);\n+EXPORT_SYMBOL(DWC_MUTEX_UNLOCK);\n+EXPORT_SYMBOL(DWC_UDELAY);\n+EXPORT_SYMBOL(DWC_MDELAY);\n+EXPORT_SYMBOL(DWC_MSLEEP);\n+EXPORT_SYMBOL(DWC_TIME);\n+EXPORT_SYMBOL(DWC_TIMER_ALLOC);\n+EXPORT_SYMBOL(DWC_TIMER_FREE);\n+EXPORT_SYMBOL(DWC_TIMER_SCHEDULE);\n+EXPORT_SYMBOL(DWC_TIMER_CANCEL);\n+EXPORT_SYMBOL(DWC_WAITQ_ALLOC);\n+EXPORT_SYMBOL(DWC_WAITQ_FREE);\n+EXPORT_SYMBOL(DWC_WAITQ_WAIT);\n+EXPORT_SYMBOL(DWC_WAITQ_WAIT_TIMEOUT);\n+EXPORT_SYMBOL(DWC_WAITQ_TRIGGER);\n+EXPORT_SYMBOL(DWC_WAITQ_ABORT);\n+EXPORT_SYMBOL(DWC_THREAD_RUN);\n+EXPORT_SYMBOL(DWC_THREAD_STOP);\n+EXPORT_SYMBOL(DWC_THREAD_SHOULD_STOP);\n+EXPORT_SYMBOL(DWC_TASK_ALLOC);\n+EXPORT_SYMBOL(DWC_TASK_FREE);\n+EXPORT_SYMBOL(DWC_TASK_SCHEDULE);\n+EXPORT_SYMBOL(DWC_WORKQ_WAIT_WORK_DONE);\n+EXPORT_SYMBOL(DWC_WORKQ_ALLOC);\n+EXPORT_SYMBOL(DWC_WORKQ_FREE);\n+EXPORT_SYMBOL(DWC_WORKQ_SCHEDULE);\n+EXPORT_SYMBOL(DWC_WORKQ_SCHEDULE_DELAYED);\n+EXPORT_SYMBOL(DWC_WORKQ_PENDING);\n+\n+static int dwc_common_port_init_module(void)\n+{\n+\tint result = 0;\n+\n+\tprintk(KERN_DEBUG \"Module dwc_common_port init\\n\" );\n+\n+#ifdef DWC_DEBUG_MEMORY\n+\tresult = dwc_memory_debug_start(NULL);\n+\tif (result) {\n+\t\tprintk(KERN_ERR\n+\t\t       \"dwc_memory_debug_start() failed with error %d\\n\",\n+\t\t       result);\n+\t\treturn result;\n+\t}\n+#endif\n+\n+#ifdef DWC_NOTIFYLIB\n+\tresult = dwc_alloc_notification_manager(NULL, NULL);\n+\tif (result) {\n+\t\tprintk(KERN_ERR\n+\t\t       \"dwc_alloc_notification_manager() failed with error %d\\n\",\n+\t\t       result);\n+\t\treturn result;\n+\t}\n+#endif\n+\treturn result;\n+}\n+\n+static void dwc_common_port_exit_module(void)\n+{\n+\tprintk(KERN_DEBUG \"Module dwc_common_port exit\\n\" );\n+\n+#ifdef DWC_NOTIFYLIB\n+\tdwc_free_notification_manager();\n+#endif\n+\n+#ifdef DWC_DEBUG_MEMORY\n+\tdwc_memory_debug_stop();\n+#endif\n+}\n+\n+module_init(dwc_common_port_init_module);\n+module_exit(dwc_common_port_exit_module);\n+\n+MODULE_DESCRIPTION(\"DWC Common Library - Portable version\");\n+MODULE_AUTHOR(\"Synopsys Inc.\");\n+MODULE_LICENSE (\"GPL\");\n+\n+#endif\t/* DWC_LIBMODULE */\n--- /dev/null\n+++ b/drivers/usb/host/dwc_common_port/dwc_common_nbsd.c\n@@ -0,0 +1,1275 @@\n+#include \"dwc_os.h\"\n+#include \"dwc_list.h\"\n+\n+#ifdef DWC_CCLIB\n+# include \"dwc_cc.h\"\n+#endif\n+\n+#ifdef DWC_CRYPTOLIB\n+# include \"dwc_modpow.h\"\n+# include \"dwc_dh.h\"\n+# include \"dwc_crypto.h\"\n+#endif\n+\n+#ifdef DWC_NOTIFYLIB\n+# include \"dwc_notifier.h\"\n+#endif\n+\n+/* OS-Level Implementations */\n+\n+/* This is the NetBSD 4.0.1 kernel implementation of the DWC platform library. */\n+\n+\n+/* MISC */\n+\n+void *DWC_MEMSET(void *dest, uint8_t byte, uint32_t size)\n+{\n+\treturn memset(dest, byte, size);\n+}\n+\n+void *DWC_MEMCPY(void *dest, void const *src, uint32_t size)\n+{\n+\treturn memcpy(dest, src, size);\n+}\n+\n+void *DWC_MEMMOVE(void *dest, void *src, uint32_t size)\n+{\n+\tbcopy(src, dest, size);\n+\treturn dest;\n+}\n+\n+int DWC_MEMCMP(void *m1, void *m2, uint32_t size)\n+{\n+\treturn memcmp(m1, m2, size);\n+}\n+\n+int DWC_STRNCMP(void *s1, void *s2, uint32_t size)\n+{\n+\treturn strncmp(s1, s2, size);\n+}\n+\n+int DWC_STRCMP(void *s1, void *s2)\n+{\n+\treturn strcmp(s1, s2);\n+}\n+\n+int DWC_STRLEN(char const *str)\n+{\n+\treturn strlen(str);\n+}\n+\n+char *DWC_STRCPY(char *to, char const *from)\n+{\n+\treturn strcpy(to, from);\n+}\n+\n+char *DWC_STRDUP(char const *str)\n+{\n+\tint len = DWC_STRLEN(str) + 1;\n+\tchar *new = DWC_ALLOC_ATOMIC(len);\n+\n+\tif (!new) {\n+\t\treturn NULL;\n+\t}\n+\n+\tDWC_MEMCPY(new, str, len);\n+\treturn new;\n+}\n+\n+int DWC_ATOI(char *str, int32_t *value)\n+{\n+\tchar *end = NULL;\n+\n+\t/* NetBSD doesn't have 'strtol' in the kernel, but 'strtoul'\n+\t * should be equivalent on 2's complement machines\n+\t */\n+\t*value = strtoul(str, &end, 0);\n+\tif (*end == '\\0') {\n+\t\treturn 0;\n+\t}\n+\n+\treturn -1;\n+}\n+\n+int DWC_ATOUI(char *str, uint32_t *value)\n+{\n+\tchar *end = NULL;\n+\n+\t*value = strtoul(str, &end, 0);\n+\tif (*end == '\\0') {\n+\t\treturn 0;\n+\t}\n+\n+\treturn -1;\n+}\n+\n+\n+#ifdef DWC_UTFLIB\n+/* From usbstring.c */\n+\n+int DWC_UTF8_TO_UTF16LE(uint8_t const *s, uint16_t *cp, unsigned len)\n+{\n+\tint\tcount = 0;\n+\tu8\tc;\n+\tu16\tuchar;\n+\n+\t/* this insists on correct encodings, though not minimal ones.\n+\t * BUT it currently rejects legit 4-byte UTF-8 code points,\n+\t * which need surrogate pairs.  (Unicode 3.1 can use them.)\n+\t */\n+\twhile (len != 0 && (c = (u8) *s++) != 0) {\n+\t\tif (unlikely(c & 0x80)) {\n+\t\t\t// 2-byte sequence:\n+\t\t\t// 00000yyyyyxxxxxx = 110yyyyy 10xxxxxx\n+\t\t\tif ((c & 0xe0) == 0xc0) {\n+\t\t\t\tuchar = (c & 0x1f) << 6;\n+\n+\t\t\t\tc = (u8) *s++;\n+\t\t\t\tif ((c & 0xc0) != 0xc0)\n+\t\t\t\t\tgoto fail;\n+\t\t\t\tc &= 0x3f;\n+\t\t\t\tuchar |= c;\n+\n+\t\t\t// 3-byte sequence (most CJKV characters):\n+\t\t\t// zzzzyyyyyyxxxxxx = 1110zzzz 10yyyyyy 10xxxxxx\n+\t\t\t} else if ((c & 0xf0) == 0xe0) {\n+\t\t\t\tuchar = (c & 0x0f) << 12;\n+\n+\t\t\t\tc = (u8) *s++;\n+\t\t\t\tif ((c & 0xc0) != 0xc0)\n+\t\t\t\t\tgoto fail;\n+\t\t\t\tc &= 0x3f;\n+\t\t\t\tuchar |= c << 6;\n+\n+\t\t\t\tc = (u8) *s++;\n+\t\t\t\tif ((c & 0xc0) != 0xc0)\n+\t\t\t\t\tgoto fail;\n+\t\t\t\tc &= 0x3f;\n+\t\t\t\tuchar |= c;\n+\n+\t\t\t\t/* no bogus surrogates */\n+\t\t\t\tif (0xd800 <= uchar && uchar <= 0xdfff)\n+\t\t\t\t\tgoto fail;\n+\n+\t\t\t// 4-byte sequence (surrogate pairs, currently rare):\n+\t\t\t// 11101110wwwwzzzzyy + 110111yyyyxxxxxx\n+\t\t\t//     = 11110uuu 10uuzzzz 10yyyyyy 10xxxxxx\n+\t\t\t// (uuuuu = wwww + 1)\n+\t\t\t// FIXME accept the surrogate code points (only)\n+\t\t\t} else\n+\t\t\t\tgoto fail;\n+\t\t} else\n+\t\t\tuchar = c;\n+\t\tput_unaligned (cpu_to_le16 (uchar), cp++);\n+\t\tcount++;\n+\t\tlen--;\n+\t}\n+\treturn count;\n+fail:\n+\treturn -1;\n+}\n+\n+#endif\t/* DWC_UTFLIB */\n+\n+\n+/* dwc_debug.h */\n+\n+dwc_bool_t DWC_IN_IRQ(void)\n+{\n+//\treturn in_irq();\n+\treturn 0;\n+}\n+\n+dwc_bool_t DWC_IN_BH(void)\n+{\n+//\treturn in_softirq();\n+\treturn 0;\n+}\n+\n+void DWC_VPRINTF(char *format, va_list args)\n+{\n+\tvprintf(format, args);\n+}\n+\n+int DWC_VSNPRINTF(char *str, int size, char *format, va_list args)\n+{\n+\treturn vsnprintf(str, size, format, args);\n+}\n+\n+void DWC_PRINTF(char *format, ...)\n+{\n+\tva_list args;\n+\n+\tva_start(args, format);\n+\tDWC_VPRINTF(format, args);\n+\tva_end(args);\n+}\n+\n+int DWC_SPRINTF(char *buffer, char *format, ...)\n+{\n+\tint retval;\n+\tva_list args;\n+\n+\tva_start(args, format);\n+\tretval = vsprintf(buffer, format, args);\n+\tva_end(args);\n+\treturn retval;\n+}\n+\n+int DWC_SNPRINTF(char *buffer, int size, char *format, ...)\n+{\n+\tint retval;\n+\tva_list args;\n+\n+\tva_start(args, format);\n+\tretval = vsnprintf(buffer, size, format, args);\n+\tva_end(args);\n+\treturn retval;\n+}\n+\n+void __DWC_WARN(char *format, ...)\n+{\n+\tva_list args;\n+\n+\tva_start(args, format);\n+\tDWC_VPRINTF(format, args);\n+\tva_end(args);\n+}\n+\n+void __DWC_ERROR(char *format, ...)\n+{\n+\tva_list args;\n+\n+\tva_start(args, format);\n+\tDWC_VPRINTF(format, args);\n+\tva_end(args);\n+}\n+\n+void DWC_EXCEPTION(char *format, ...)\n+{\n+\tva_list args;\n+\n+\tva_start(args, format);\n+\tDWC_VPRINTF(format, args);\n+\tva_end(args);\n+//\tBUG_ON(1);\t???\n+}\n+\n+#ifdef DEBUG\n+void __DWC_DEBUG(char *format, ...)\n+{\n+\tva_list args;\n+\n+\tva_start(args, format);\n+\tDWC_VPRINTF(format, args);\n+\tva_end(args);\n+}\n+#endif\n+\n+\n+/* dwc_mem.h */\n+\n+#if 0\n+dwc_pool_t *DWC_DMA_POOL_CREATE(uint32_t size,\n+\t\t\t\tuint32_t align,\n+\t\t\t\tuint32_t alloc)\n+{\n+\tstruct dma_pool *pool = dma_pool_create(\"Pool\", NULL,\n+\t\t\t\t\t\tsize, align, alloc);\n+\treturn (dwc_pool_t *)pool;\n+}\n+\n+void DWC_DMA_POOL_DESTROY(dwc_pool_t *pool)\n+{\n+\tdma_pool_destroy((struct dma_pool *)pool);\n+}\n+\n+void *DWC_DMA_POOL_ALLOC(dwc_pool_t *pool, uint64_t *dma_addr)\n+{\n+//\treturn dma_pool_alloc((struct dma_pool *)pool, GFP_KERNEL, dma_addr);\n+\treturn dma_pool_alloc((struct dma_pool *)pool, M_WAITOK, dma_addr);\n+}\n+\n+void *DWC_DMA_POOL_ZALLOC(dwc_pool_t *pool, uint64_t *dma_addr)\n+{\n+\tvoid *vaddr = DWC_DMA_POOL_ALLOC(pool, dma_addr);\n+\tmemset(..);\n+}\n+\n+void DWC_DMA_POOL_FREE(dwc_pool_t *pool, void *vaddr, void *daddr)\n+{\n+\tdma_pool_free(pool, vaddr, daddr);\n+}\n+#endif\n+\n+void *__DWC_DMA_ALLOC(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr)\n+{\n+\tdwc_dmactx_t *dma = (dwc_dmactx_t *)dma_ctx;\n+\tint error;\n+\n+\terror = bus_dmamem_alloc(dma->dma_tag, size, 1, size, dma->segs,\n+\t\t\t\t sizeof(dma->segs) / sizeof(dma->segs[0]),\n+\t\t\t\t &dma->nsegs, BUS_DMA_NOWAIT);\n+\tif (error) {\n+\t\tprintf(\"%s: bus_dmamem_alloc(%ju) failed: %d\\n\", __func__,\n+\t\t       (uintmax_t)size, error);\n+\t\tgoto fail_0;\n+\t}\n+\n+\terror = bus_dmamem_map(dma->dma_tag, dma->segs, dma->nsegs, size,\n+\t\t\t       (caddr_t *)&dma->dma_vaddr,\n+\t\t\t       BUS_DMA_NOWAIT | BUS_DMA_COHERENT);\n+\tif (error) {\n+\t\tprintf(\"%s: bus_dmamem_map failed: %d\\n\", __func__, error);\n+\t\tgoto fail_1;\n+\t}\n+\n+\terror = bus_dmamap_create(dma->dma_tag, size, 1, size, 0,\n+\t\t\t\t  BUS_DMA_NOWAIT, &dma->dma_map);\n+\tif (error) {\n+\t\tprintf(\"%s: bus_dmamap_create failed: %d\\n\", __func__, error);\n+\t\tgoto fail_2;\n+\t}\n+\n+\terror = bus_dmamap_load(dma->dma_tag, dma->dma_map, dma->dma_vaddr,\n+\t\t\t\tsize, NULL, BUS_DMA_NOWAIT);\n+\tif (error) {\n+\t\tprintf(\"%s: bus_dmamap_load failed: %d\\n\", __func__, error);\n+\t\tgoto fail_3;\n+\t}\n+\n+\tdma->dma_paddr = (bus_addr_t)dma->segs[0].ds_addr;\n+\t*dma_addr = dma->dma_paddr;\n+\treturn dma->dma_vaddr;\n+\n+fail_3:\n+\tbus_dmamap_destroy(dma->dma_tag, dma->dma_map);\n+fail_2:\n+\tbus_dmamem_unmap(dma->dma_tag, dma->dma_vaddr, size);\n+fail_1:\n+\tbus_dmamem_free(dma->dma_tag, dma->segs, dma->nsegs);\n+fail_0:\n+\tdma->dma_map = NULL;\n+\tdma->dma_vaddr = NULL;\n+\tdma->nsegs = 0;\n+\n+\treturn NULL;\n+}\n+\n+void __DWC_DMA_FREE(void *dma_ctx, uint32_t size, void *virt_addr, dwc_dma_t dma_addr)\n+{\n+\tdwc_dmactx_t *dma = (dwc_dmactx_t *)dma_ctx;\n+\n+\tif (dma->dma_map != NULL) {\n+\t\tbus_dmamap_sync(dma->dma_tag, dma->dma_map, 0, size,\n+\t\t\t\tBUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);\n+\t\tbus_dmamap_unload(dma->dma_tag, dma->dma_map);\n+\t\tbus_dmamap_destroy(dma->dma_tag, dma->dma_map);\n+\t\tbus_dmamem_unmap(dma->dma_tag, dma->dma_vaddr, size);\n+\t\tbus_dmamem_free(dma->dma_tag, dma->segs, dma->nsegs);\n+\t\tdma->dma_paddr = 0;\n+\t\tdma->dma_map = NULL;\n+\t\tdma->dma_vaddr = NULL;\n+\t\tdma->nsegs = 0;\n+\t}\n+}\n+\n+void *__DWC_ALLOC(void *mem_ctx, uint32_t size)\n+{\n+\treturn malloc(size, M_DEVBUF, M_WAITOK | M_ZERO);\n+}\n+\n+void *__DWC_ALLOC_ATOMIC(void *mem_ctx, uint32_t size)\n+{\n+\treturn malloc(size, M_DEVBUF, M_NOWAIT | M_ZERO);\n+}\n+\n+void __DWC_FREE(void *mem_ctx, void *addr)\n+{\n+\tfree(addr, M_DEVBUF);\n+}\n+\n+\n+#ifdef DWC_CRYPTOLIB\n+/* dwc_crypto.h */\n+\n+void DWC_RANDOM_BYTES(uint8_t *buffer, uint32_t length)\n+{\n+\tget_random_bytes(buffer, length);\n+}\n+\n+int DWC_AES_CBC(uint8_t *message, uint32_t messagelen, uint8_t *key, uint32_t keylen, uint8_t iv[16], uint8_t *out)\n+{\n+\tstruct crypto_blkcipher *tfm;\n+\tstruct blkcipher_desc desc;\n+\tstruct scatterlist sgd;\n+\tstruct scatterlist sgs;\n+\n+\ttfm = crypto_alloc_blkcipher(\"cbc(aes)\", 0, CRYPTO_ALG_ASYNC);\n+\tif (tfm == NULL) {\n+\t\tprintk(\"failed to load transform for aes CBC\\n\");\n+\t\treturn -1;\n+\t}\n+\n+\tcrypto_blkcipher_setkey(tfm, key, keylen);\n+\tcrypto_blkcipher_set_iv(tfm, iv, 16);\n+\n+\tsg_init_one(&sgd, out, messagelen);\n+\tsg_init_one(&sgs, message, messagelen);\n+\n+\tdesc.tfm = tfm;\n+\tdesc.flags = 0;\n+\n+\tif (crypto_blkcipher_encrypt(&desc, &sgd, &sgs, messagelen)) {\n+\t\tcrypto_free_blkcipher(tfm);\n+\t\tDWC_ERROR(\"AES CBC encryption failed\");\n+\t\treturn -1;\n+\t}\n+\n+\tcrypto_free_blkcipher(tfm);\n+\treturn 0;\n+}\n+\n+int DWC_SHA256(uint8_t *message, uint32_t len, uint8_t *out)\n+{\n+\tstruct crypto_hash *tfm;\n+\tstruct hash_desc desc;\n+\tstruct scatterlist sg;\n+\n+\ttfm = crypto_alloc_hash(\"sha256\", 0, CRYPTO_ALG_ASYNC);\n+\tif (IS_ERR(tfm)) {\n+\t\tDWC_ERROR(\"Failed to load transform for sha256: %ld\", PTR_ERR(tfm));\n+\t\treturn 0;\n+\t}\n+\tdesc.tfm = tfm;\n+\tdesc.flags = 0;\n+\n+\tsg_init_one(&sg, message, len);\n+\tcrypto_hash_digest(&desc, &sg, len, out);\n+\tcrypto_free_hash(tfm);\n+\n+\treturn 1;\n+}\n+\n+int DWC_HMAC_SHA256(uint8_t *message, uint32_t messagelen,\n+\t\t    uint8_t *key, uint32_t keylen, uint8_t *out)\n+{\n+\tstruct crypto_hash *tfm;\n+\tstruct hash_desc desc;\n+\tstruct scatterlist sg;\n+\n+\ttfm = crypto_alloc_hash(\"hmac(sha256)\", 0, CRYPTO_ALG_ASYNC);\n+\tif (IS_ERR(tfm)) {\n+\t\tDWC_ERROR(\"Failed to load transform for hmac(sha256): %ld\", PTR_ERR(tfm));\n+\t\treturn 0;\n+\t}\n+\tdesc.tfm = tfm;\n+\tdesc.flags = 0;\n+\n+\tsg_init_one(&sg, message, messagelen);\n+\tcrypto_hash_setkey(tfm, key, keylen);\n+\tcrypto_hash_digest(&desc, &sg, messagelen, out);\n+\tcrypto_free_hash(tfm);\n+\n+\treturn 1;\n+}\n+\n+#endif\t/* DWC_CRYPTOLIB */\n+\n+\n+/* Byte Ordering Conversions */\n+\n+uint32_t DWC_CPU_TO_LE32(uint32_t *p)\n+{\n+#ifdef __LITTLE_ENDIAN\n+\treturn *p;\n+#else\n+\tuint8_t *u_p = (uint8_t *)p;\n+\n+\treturn (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24));\n+#endif\n+}\n+\n+uint32_t DWC_CPU_TO_BE32(uint32_t *p)\n+{\n+#ifdef __BIG_ENDIAN\n+\treturn *p;\n+#else\n+\tuint8_t *u_p = (uint8_t *)p;\n+\n+\treturn (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24));\n+#endif\n+}\n+\n+uint32_t DWC_LE32_TO_CPU(uint32_t *p)\n+{\n+#ifdef __LITTLE_ENDIAN\n+\treturn *p;\n+#else\n+\tuint8_t *u_p = (uint8_t *)p;\n+\n+\treturn (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24));\n+#endif\n+}\n+\n+uint32_t DWC_BE32_TO_CPU(uint32_t *p)\n+{\n+#ifdef __BIG_ENDIAN\n+\treturn *p;\n+#else\n+\tuint8_t *u_p = (uint8_t *)p;\n+\n+\treturn (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24));\n+#endif\n+}\n+\n+uint16_t DWC_CPU_TO_LE16(uint16_t *p)\n+{\n+#ifdef __LITTLE_ENDIAN\n+\treturn *p;\n+#else\n+\tuint8_t *u_p = (uint8_t *)p;\n+\treturn (u_p[1] | (u_p[0] << 8));\n+#endif\n+}\n+\n+uint16_t DWC_CPU_TO_BE16(uint16_t *p)\n+{\n+#ifdef __BIG_ENDIAN\n+\treturn *p;\n+#else\n+\tuint8_t *u_p = (uint8_t *)p;\n+\treturn (u_p[1] | (u_p[0] << 8));\n+#endif\n+}\n+\n+uint16_t DWC_LE16_TO_CPU(uint16_t *p)\n+{\n+#ifdef __LITTLE_ENDIAN\n+\treturn *p;\n+#else\n+\tuint8_t *u_p = (uint8_t *)p;\n+\treturn (u_p[1] | (u_p[0] << 8));\n+#endif\n+}\n+\n+uint16_t DWC_BE16_TO_CPU(uint16_t *p)\n+{\n+#ifdef __BIG_ENDIAN\n+\treturn *p;\n+#else\n+\tuint8_t *u_p = (uint8_t *)p;\n+\treturn (u_p[1] | (u_p[0] << 8));\n+#endif\n+}\n+\n+\n+/* Registers */\n+\n+uint32_t DWC_READ_REG32(void *io_ctx, uint32_t volatile *reg)\n+{\n+\tdwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx;\n+\tbus_size_t ior = (bus_size_t)reg;\n+\n+\treturn bus_space_read_4(io->iot, io->ioh, ior);\n+}\n+\n+#if 0\n+uint64_t DWC_READ_REG64(void *io_ctx, uint64_t volatile *reg)\n+{\n+\tdwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx;\n+\tbus_size_t ior = (bus_size_t)reg;\n+\n+\treturn bus_space_read_8(io->iot, io->ioh, ior);\n+}\n+#endif\n+\n+void DWC_WRITE_REG32(void *io_ctx, uint32_t volatile *reg, uint32_t value)\n+{\n+\tdwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx;\n+\tbus_size_t ior = (bus_size_t)reg;\n+\n+\tbus_space_write_4(io->iot, io->ioh, ior, value);\n+}\n+\n+#if 0\n+void DWC_WRITE_REG64(void *io_ctx, uint64_t volatile *reg, uint64_t value)\n+{\n+\tdwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx;\n+\tbus_size_t ior = (bus_size_t)reg;\n+\n+\tbus_space_write_8(io->iot, io->ioh, ior, value);\n+}\n+#endif\n+\n+void DWC_MODIFY_REG32(void *io_ctx, uint32_t volatile *reg, uint32_t clear_mask,\n+\t\t      uint32_t set_mask)\n+{\n+\tdwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx;\n+\tbus_size_t ior = (bus_size_t)reg;\n+\n+\tbus_space_write_4(io->iot, io->ioh, ior,\n+\t\t\t  (bus_space_read_4(io->iot, io->ioh, ior) &\n+\t\t\t   ~clear_mask) | set_mask);\n+}\n+\n+#if 0\n+void DWC_MODIFY_REG64(void *io_ctx, uint64_t volatile *reg, uint64_t clear_mask,\n+\t\t      uint64_t set_mask)\n+{\n+\tdwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx;\n+\tbus_size_t ior = (bus_size_t)reg;\n+\n+\tbus_space_write_8(io->iot, io->ioh, ior,\n+\t\t\t  (bus_space_read_8(io->iot, io->ioh, ior) &\n+\t\t\t   ~clear_mask) | set_mask);\n+}\n+#endif\n+\n+\n+/* Locking */\n+\n+dwc_spinlock_t *DWC_SPINLOCK_ALLOC(void)\n+{\n+\tstruct simplelock *sl = DWC_ALLOC(sizeof(*sl));\n+\n+\tif (!sl) {\n+\t\tDWC_ERROR(\"Cannot allocate memory for spinlock\");\n+\t\treturn NULL;\n+\t}\n+\n+\tsimple_lock_init(sl);\n+\treturn (dwc_spinlock_t *)sl;\n+}\n+\n+void DWC_SPINLOCK_FREE(dwc_spinlock_t *lock)\n+{\n+\tstruct simplelock *sl = (struct simplelock *)lock;\n+\n+\tDWC_FREE(sl);\n+}\n+\n+void DWC_SPINLOCK(dwc_spinlock_t *lock)\n+{\n+\tsimple_lock((struct simplelock *)lock);\n+}\n+\n+void DWC_SPINUNLOCK(dwc_spinlock_t *lock)\n+{\n+\tsimple_unlock((struct simplelock *)lock);\n+}\n+\n+void DWC_SPINLOCK_IRQSAVE(dwc_spinlock_t *lock, dwc_irqflags_t *flags)\n+{\n+\tsimple_lock((struct simplelock *)lock);\n+\t*flags = splbio();\n+}\n+\n+void DWC_SPINUNLOCK_IRQRESTORE(dwc_spinlock_t *lock, dwc_irqflags_t flags)\n+{\n+\tsplx(flags);\n+\tsimple_unlock((struct simplelock *)lock);\n+}\n+\n+dwc_mutex_t *DWC_MUTEX_ALLOC(void)\n+{\n+\tdwc_mutex_t *mutex = DWC_ALLOC(sizeof(struct lock));\n+\n+\tif (!mutex) {\n+\t\tDWC_ERROR(\"Cannot allocate memory for mutex\");\n+\t\treturn NULL;\n+\t}\n+\n+\tlockinit((struct lock *)mutex, 0, \"dw3mtx\", 0, 0);\n+\treturn mutex;\n+}\n+\n+#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_MUTEXES))\n+#else\n+void DWC_MUTEX_FREE(dwc_mutex_t *mutex)\n+{\n+\tDWC_FREE(mutex);\n+}\n+#endif\n+\n+void DWC_MUTEX_LOCK(dwc_mutex_t *mutex)\n+{\n+\tlockmgr((struct lock *)mutex, LK_EXCLUSIVE, NULL);\n+}\n+\n+int DWC_MUTEX_TRYLOCK(dwc_mutex_t *mutex)\n+{\n+\tint status;\n+\n+\tstatus = lockmgr((struct lock *)mutex, LK_EXCLUSIVE | LK_NOWAIT, NULL);\n+\treturn status == 0;\n+}\n+\n+void DWC_MUTEX_UNLOCK(dwc_mutex_t *mutex)\n+{\n+\tlockmgr((struct lock *)mutex, LK_RELEASE, NULL);\n+}\n+\n+\n+/* Timing */\n+\n+void DWC_UDELAY(uint32_t usecs)\n+{\n+\tDELAY(usecs);\n+}\n+\n+void DWC_MDELAY(uint32_t msecs)\n+{\n+\tdo {\n+\t\tDELAY(1000);\n+\t} while (--msecs);\n+}\n+\n+void DWC_MSLEEP(uint32_t msecs)\n+{\n+\tstruct timeval tv;\n+\n+\ttv.tv_sec = msecs / 1000;\n+\ttv.tv_usec = (msecs - tv.tv_sec * 1000) * 1000;\n+\ttsleep(&tv, 0, \"dw3slp\", tvtohz(&tv));\n+}\n+\n+uint32_t DWC_TIME(void)\n+{\n+\tstruct timeval tv;\n+\n+\tmicrouptime(&tv);\t// or getmicrouptime? (less precise, but faster)\n+\treturn tv.tv_sec * 1000 + tv.tv_usec / 1000;\n+}\n+\n+\n+/* Timers */\n+\n+struct dwc_timer {\n+\tstruct callout t;\n+\tchar *name;\n+\tdwc_spinlock_t *lock;\n+\tdwc_timer_callback_t cb;\n+\tvoid *data;\n+};\n+\n+dwc_timer_t *DWC_TIMER_ALLOC(char *name, dwc_timer_callback_t cb, void *data)\n+{\n+\tdwc_timer_t *t = DWC_ALLOC(sizeof(*t));\n+\n+\tif (!t) {\n+\t\tDWC_ERROR(\"Cannot allocate memory for timer\");\n+\t\treturn NULL;\n+\t}\n+\n+\tcallout_init(&t->t);\n+\n+\tt->name = DWC_STRDUP(name);\n+\tif (!t->name) {\n+\t\tDWC_ERROR(\"Cannot allocate memory for timer->name\");\n+\t\tgoto no_name;\n+\t}\n+\n+\tt->lock = DWC_SPINLOCK_ALLOC();\n+\tif (!t->lock) {\n+\t\tDWC_ERROR(\"Cannot allocate memory for timer->lock\");\n+\t\tgoto no_lock;\n+\t}\n+\n+\tt->cb = cb;\n+\tt->data = data;\n+\n+\treturn t;\n+\n+ no_lock:\n+\tDWC_FREE(t->name);\n+ no_name:\n+\tDWC_FREE(t);\n+\n+\treturn NULL;\n+}\n+\n+void DWC_TIMER_FREE(dwc_timer_t *timer)\n+{\n+\tcallout_stop(&timer->t);\n+\tDWC_SPINLOCK_FREE(timer->lock);\n+\tDWC_FREE(timer->name);\n+\tDWC_FREE(timer);\n+}\n+\n+void DWC_TIMER_SCHEDULE(dwc_timer_t *timer, uint32_t time)\n+{\n+\tstruct timeval tv;\n+\n+\ttv.tv_sec = time / 1000;\n+\ttv.tv_usec = (time - tv.tv_sec * 1000) * 1000;\n+\tcallout_reset(&timer->t, tvtohz(&tv), timer->cb, timer->data);\n+}\n+\n+void DWC_TIMER_CANCEL(dwc_timer_t *timer)\n+{\n+\tcallout_stop(&timer->t);\n+}\n+\n+\n+/* Wait Queues */\n+\n+struct dwc_waitq {\n+\tstruct simplelock lock;\n+\tint abort;\n+};\n+\n+dwc_waitq_t *DWC_WAITQ_ALLOC(void)\n+{\n+\tdwc_waitq_t *wq = DWC_ALLOC(sizeof(*wq));\n+\n+\tif (!wq) {\n+\t\tDWC_ERROR(\"Cannot allocate memory for waitqueue\");\n+\t\treturn NULL;\n+\t}\n+\n+\tsimple_lock_init(&wq->lock);\n+\twq->abort = 0;\n+\n+\treturn wq;\n+}\n+\n+void DWC_WAITQ_FREE(dwc_waitq_t *wq)\n+{\n+\tDWC_FREE(wq);\n+}\n+\n+int32_t DWC_WAITQ_WAIT(dwc_waitq_t *wq, dwc_waitq_condition_t cond, void *data)\n+{\n+\tint ipl;\n+\tint result = 0;\n+\n+\tsimple_lock(&wq->lock);\n+\tipl = splbio();\n+\n+\t/* Skip the sleep if already aborted or triggered */\n+\tif (!wq->abort && !cond(data)) {\n+\t\tsplx(ipl);\n+\t\tresult = ltsleep(wq, PCATCH, \"dw3wat\", 0, &wq->lock); // infinite timeout\n+\t\tipl = splbio();\n+\t}\n+\n+\tif (result == 0) {\t\t\t// awoken\n+\t\tif (wq->abort) {\n+\t\t\twq->abort = 0;\n+\t\t\tresult = -DWC_E_ABORT;\n+\t\t} else {\n+\t\t\tresult = 0;\n+\t\t}\n+\n+\t\tsplx(ipl);\n+\t\tsimple_unlock(&wq->lock);\n+\t} else {\n+\t\twq->abort = 0;\n+\t\tsplx(ipl);\n+\t\tsimple_unlock(&wq->lock);\n+\n+\t\tif (result == ERESTART) {\t// signaled - restart\n+\t\t\tresult = -DWC_E_RESTART;\n+\t\t} else {\t\t\t// signaled - must be EINTR\n+\t\t\tresult = -DWC_E_ABORT;\n+\t\t}\n+\t}\n+\n+\treturn result;\n+}\n+\n+int32_t DWC_WAITQ_WAIT_TIMEOUT(dwc_waitq_t *wq, dwc_waitq_condition_t cond,\n+\t\t\t       void *data, int32_t msecs)\n+{\n+\tstruct timeval tv, tv1, tv2;\n+\tint ipl;\n+\tint result = 0;\n+\n+\ttv.tv_sec = msecs / 1000;\n+\ttv.tv_usec = (msecs - tv.tv_sec * 1000) * 1000;\n+\n+\tsimple_lock(&wq->lock);\n+\tipl = splbio();\n+\n+\t/* Skip the sleep if already aborted or triggered */\n+\tif (!wq->abort && !cond(data)) {\n+\t\tsplx(ipl);\n+\t\tgetmicrouptime(&tv1);\n+\t\tresult = ltsleep(wq, PCATCH, \"dw3wto\", tvtohz(&tv), &wq->lock);\n+\t\tgetmicrouptime(&tv2);\n+\t\tipl = splbio();\n+\t}\n+\n+\tif (result == 0) {\t\t\t// awoken\n+\t\tif (wq->abort) {\n+\t\t\twq->abort = 0;\n+\t\t\tsplx(ipl);\n+\t\t\tsimple_unlock(&wq->lock);\n+\t\t\tresult = -DWC_E_ABORT;\n+\t\t} else {\n+\t\t\tsplx(ipl);\n+\t\t\tsimple_unlock(&wq->lock);\n+\n+\t\t\ttv2.tv_usec -= tv1.tv_usec;\n+\t\t\tif (tv2.tv_usec < 0) {\n+\t\t\t\ttv2.tv_usec += 1000000;\n+\t\t\t\ttv2.tv_sec--;\n+\t\t\t}\n+\n+\t\t\ttv2.tv_sec -= tv1.tv_sec;\n+\t\t\tresult = tv2.tv_sec * 1000 + tv2.tv_usec / 1000;\n+\t\t\tresult = msecs - result;\n+\t\t\tif (result <= 0)\n+\t\t\t\tresult = 1;\n+\t\t}\n+\t} else {\n+\t\twq->abort = 0;\n+\t\tsplx(ipl);\n+\t\tsimple_unlock(&wq->lock);\n+\n+\t\tif (result == ERESTART) {\t// signaled - restart\n+\t\t\tresult = -DWC_E_RESTART;\n+\n+\t\t} else if (result == EINTR) {\t\t// signaled - interrupt\n+\t\t\tresult = -DWC_E_ABORT;\n+\n+\t\t} else {\t\t\t\t// timed out\n+\t\t\tresult = -DWC_E_TIMEOUT;\n+\t\t}\n+\t}\n+\n+\treturn result;\n+}\n+\n+void DWC_WAITQ_TRIGGER(dwc_waitq_t *wq)\n+{\n+\twakeup(wq);\n+}\n+\n+void DWC_WAITQ_ABORT(dwc_waitq_t *wq)\n+{\n+\tint ipl;\n+\n+\tsimple_lock(&wq->lock);\n+\tipl = splbio();\n+\twq->abort = 1;\n+\twakeup(wq);\n+\tsplx(ipl);\n+\tsimple_unlock(&wq->lock);\n+}\n+\n+\n+/* Threading */\n+\n+struct dwc_thread {\n+\tstruct proc *proc;\n+\tint abort;\n+};\n+\n+dwc_thread_t *DWC_THREAD_RUN(dwc_thread_function_t func, char *name, void *data)\n+{\n+\tint retval;\n+\tdwc_thread_t *thread = DWC_ALLOC(sizeof(*thread));\n+\n+\tif (!thread) {\n+\t\treturn NULL;\n+\t}\n+\n+\tthread->abort = 0;\n+\tretval = kthread_create1((void (*)(void *))func, data, &thread->proc,\n+\t\t\t\t \"%s\", name);\n+\tif (retval) {\n+\t\tDWC_FREE(thread);\n+\t\treturn NULL;\n+\t}\n+\n+\treturn thread;\n+}\n+\n+int DWC_THREAD_STOP(dwc_thread_t *thread)\n+{\n+\tint retval;\n+\n+\tthread->abort = 1;\n+\tretval = tsleep(&thread->abort, 0, \"dw3stp\", 60 * hz);\n+\n+\tif (retval == 0) {\n+\t\t/* DWC_THREAD_EXIT() will free the thread struct */\n+\t\treturn 0;\n+\t}\n+\n+\t/* NOTE: We leak the thread struct if thread doesn't die */\n+\n+\tif (retval == EWOULDBLOCK) {\n+\t\treturn -DWC_E_TIMEOUT;\n+\t}\n+\n+\treturn -DWC_E_UNKNOWN;\n+}\n+\n+dwc_bool_t DWC_THREAD_SHOULD_STOP(dwc_thread_t *thread)\n+{\n+\treturn thread->abort;\n+}\n+\n+void DWC_THREAD_EXIT(dwc_thread_t *thread)\n+{\n+\twakeup(&thread->abort);\n+\tDWC_FREE(thread);\n+\tkthread_exit(0);\n+}\n+\n+/* tasklets\n+ - Runs in interrupt context (cannot sleep)\n+ - Each tasklet runs on a single CPU\n+ - Different tasklets can be running simultaneously on different CPUs\n+ [ On NetBSD there is no corresponding mechanism, drivers don't have bottom-\n+   halves. So we just call the callback directly from DWC_TASK_SCHEDULE() ]\n+ */\n+struct dwc_tasklet {\n+\tdwc_tasklet_callback_t cb;\n+\tvoid *data;\n+};\n+\n+static void tasklet_callback(void *data)\n+{\n+\tdwc_tasklet_t *task = (dwc_tasklet_t *)data;\n+\n+\ttask->cb(task->data);\n+}\n+\n+dwc_tasklet_t *DWC_TASK_ALLOC(char *name, dwc_tasklet_callback_t cb, void *data)\n+{\n+\tdwc_tasklet_t *task = DWC_ALLOC(sizeof(*task));\n+\n+\tif (task) {\n+\t\ttask->cb = cb;\n+\t\ttask->data = data;\n+\t} else {\n+\t\tDWC_ERROR(\"Cannot allocate memory for tasklet\");\n+\t}\n+\n+\treturn task;\n+}\n+\n+void DWC_TASK_FREE(dwc_tasklet_t *task)\n+{\n+\tDWC_FREE(task);\n+}\n+\n+void DWC_TASK_SCHEDULE(dwc_tasklet_t *task)\n+{\n+\ttasklet_callback(task);\n+}\n+\n+\n+/* workqueues\n+ - Runs in process context (can sleep)\n+ */\n+typedef struct work_container {\n+\tdwc_work_callback_t cb;\n+\tvoid *data;\n+\tdwc_workq_t *wq;\n+\tchar *name;\n+\tint hz;\n+\tstruct work task;\n+} work_container_t;\n+\n+struct dwc_workq {\n+\tstruct workqueue *taskq;\n+\tdwc_spinlock_t *lock;\n+\tdwc_waitq_t *waitq;\n+\tint pending;\n+\tstruct work_container *container;\n+};\n+\n+static void do_work(struct work *task, void *data)\n+{\n+\tdwc_workq_t *wq = (dwc_workq_t *)data;\n+\twork_container_t *container = wq->container;\n+\tdwc_irqflags_t flags;\n+\n+\tif (container->hz) {\n+\t\ttsleep(container, 0, \"dw3wrk\", container->hz);\n+\t}\n+\n+\tcontainer->cb(container->data);\n+\tDWC_DEBUG(\"Work done: %s, container=%p\", container->name, container);\n+\n+\tDWC_SPINLOCK_IRQSAVE(wq->lock, &flags);\n+\tif (container->name)\n+\t\tDWC_FREE(container->name);\n+\tDWC_FREE(container);\n+\twq->pending--;\n+\tDWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags);\n+\tDWC_WAITQ_TRIGGER(wq->waitq);\n+}\n+\n+static int work_done(void *data)\n+{\n+\tdwc_workq_t *workq = (dwc_workq_t *)data;\n+\n+\treturn workq->pending == 0;\n+}\n+\n+int DWC_WORKQ_WAIT_WORK_DONE(dwc_workq_t *workq, int timeout)\n+{\n+\treturn DWC_WAITQ_WAIT_TIMEOUT(workq->waitq, work_done, workq, timeout);\n+}\n+\n+dwc_workq_t *DWC_WORKQ_ALLOC(char *name)\n+{\n+\tint result;\n+\tdwc_workq_t *wq = DWC_ALLOC(sizeof(*wq));\n+\n+\tif (!wq) {\n+\t\tDWC_ERROR(\"Cannot allocate memory for workqueue\");\n+\t\treturn NULL;\n+\t}\n+\n+\tresult = workqueue_create(&wq->taskq, name, do_work, wq, 0 /*PWAIT*/,\n+\t\t\t\t  IPL_BIO, 0);\n+\tif (result) {\n+\t\tDWC_ERROR(\"Cannot create workqueue\");\n+\t\tgoto no_taskq;\n+\t}\n+\n+\twq->pending = 0;\n+\n+\twq->lock = DWC_SPINLOCK_ALLOC();\n+\tif (!wq->lock) {\n+\t\tDWC_ERROR(\"Cannot allocate memory for spinlock\");\n+\t\tgoto no_lock;\n+\t}\n+\n+\twq->waitq = DWC_WAITQ_ALLOC();\n+\tif (!wq->waitq) {\n+\t\tDWC_ERROR(\"Cannot allocate memory for waitqueue\");\n+\t\tgoto no_waitq;\n+\t}\n+\n+\treturn wq;\n+\n+ no_waitq:\n+\tDWC_SPINLOCK_FREE(wq->lock);\n+ no_lock:\n+\tworkqueue_destroy(wq->taskq);\n+ no_taskq:\n+\tDWC_FREE(wq);\n+\n+\treturn NULL;\n+}\n+\n+void DWC_WORKQ_FREE(dwc_workq_t *wq)\n+{\n+#ifdef DEBUG\n+\tdwc_irqflags_t flags;\n+\n+\tDWC_SPINLOCK_IRQSAVE(wq->lock, &flags);\n+\n+\tif (wq->pending != 0) {\n+\t\tstruct work_container *container = wq->container;\n+\n+\t\tDWC_ERROR(\"Destroying work queue with pending work\");\n+\n+\t\tif (container && container->name) {\n+\t\t\tDWC_ERROR(\"Work %s still pending\", container->name);\n+\t\t}\n+\t}\n+\n+\tDWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags);\n+#endif\n+\tDWC_WAITQ_FREE(wq->waitq);\n+\tDWC_SPINLOCK_FREE(wq->lock);\n+\tworkqueue_destroy(wq->taskq);\n+\tDWC_FREE(wq);\n+}\n+\n+void DWC_WORKQ_SCHEDULE(dwc_workq_t *wq, dwc_work_callback_t cb, void *data,\n+\t\t\tchar *format, ...)\n+{\n+\tdwc_irqflags_t flags;\n+\twork_container_t *container;\n+\tstatic char name[128];\n+\tva_list args;\n+\n+\tva_start(args, format);\n+\tDWC_VSNPRINTF(name, 128, format, args);\n+\tva_end(args);\n+\n+\tDWC_SPINLOCK_IRQSAVE(wq->lock, &flags);\n+\twq->pending++;\n+\tDWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags);\n+\tDWC_WAITQ_TRIGGER(wq->waitq);\n+\n+\tcontainer = DWC_ALLOC_ATOMIC(sizeof(*container));\n+\tif (!container) {\n+\t\tDWC_ERROR(\"Cannot allocate memory for container\");\n+\t\treturn;\n+\t}\n+\n+\tcontainer->name = DWC_STRDUP(name);\n+\tif (!container->name) {\n+\t\tDWC_ERROR(\"Cannot allocate memory for container->name\");\n+\t\tDWC_FREE(container);\n+\t\treturn;\n+\t}\n+\n+\tcontainer->cb = cb;\n+\tcontainer->data = data;\n+\tcontainer->wq = wq;\n+\tcontainer->hz = 0;\n+\twq->container = container;\n+\n+\tDWC_DEBUG(\"Queueing work: %s, container=%p\", container->name, container);\n+\tworkqueue_enqueue(wq->taskq, &container->task);\n+}\n+\n+void DWC_WORKQ_SCHEDULE_DELAYED(dwc_workq_t *wq, dwc_work_callback_t cb,\n+\t\t\t\tvoid *data, uint32_t time, char *format, ...)\n+{\n+\tdwc_irqflags_t flags;\n+\twork_container_t *container;\n+\tstatic char name[128];\n+\tstruct timeval tv;\n+\tva_list args;\n+\n+\tva_start(args, format);\n+\tDWC_VSNPRINTF(name, 128, format, args);\n+\tva_end(args);\n+\n+\tDWC_SPINLOCK_IRQSAVE(wq->lock, &flags);\n+\twq->pending++;\n+\tDWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags);\n+\tDWC_WAITQ_TRIGGER(wq->waitq);\n+\n+\tcontainer = DWC_ALLOC_ATOMIC(sizeof(*container));\n+\tif (!container) {\n+\t\tDWC_ERROR(\"Cannot allocate memory for container\");\n+\t\treturn;\n+\t}\n+\n+\tcontainer->name = DWC_STRDUP(name);\n+\tif (!container->name) {\n+\t\tDWC_ERROR(\"Cannot allocate memory for container->name\");\n+\t\tDWC_FREE(container);\n+\t\treturn;\n+\t}\n+\n+\tcontainer->cb = cb;\n+\tcontainer->data = data;\n+\tcontainer->wq = wq;\n+\ttv.tv_sec = time / 1000;\n+\ttv.tv_usec = (time - tv.tv_sec * 1000) * 1000;\n+\tcontainer->hz = tvtohz(&tv);\n+\twq->container = container;\n+\n+\tDWC_DEBUG(\"Queueing work: %s, container=%p\", container->name, container);\n+\tworkqueue_enqueue(wq->taskq, &container->task);\n+}\n+\n+int DWC_WORKQ_PENDING(dwc_workq_t *wq)\n+{\n+\treturn wq->pending;\n+}\n--- /dev/null\n+++ b/drivers/usb/host/dwc_common_port/dwc_crypto.c\n@@ -0,0 +1,308 @@\n+/* =========================================================================\n+ * $File: //dwh/usb_iip/dev/software/dwc_common_port_2/dwc_crypto.c $\n+ * $Revision: #5 $\n+ * $Date: 2010/09/28 $\n+ * $Change: 1596182 $\n+ *\n+ * Synopsys Portability Library Software and documentation\n+ * (hereinafter, \"Software\") is an Unsupported proprietary work of\n+ * Synopsys, Inc. unless otherwise expressly agreed to in writing\n+ * between Synopsys and you.\n+ *\n+ * The Software IS NOT an item of Licensed Software or Licensed Product\n+ * under any End User Software License Agreement or Agreement for\n+ * Licensed Product with Synopsys or any supplement thereto. You are\n+ * permitted to use and redistribute this Software in source and binary\n+ * forms, with or without modification, provided that redistributions\n+ * of source code must retain this notice. You may not view, use,\n+ * disclose, copy or distribute this file or any information contained\n+ * herein except pursuant to this license grant from Synopsys. If you\n+ * do not agree with this notice, including the disclaimer below, then\n+ * you are not authorized to use the Software.\n+ *\n+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN \"AS IS\"\n+ * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n+ * FOR A PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL\n+ * SYNOPSYS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\n+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\n+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR\n+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY\n+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE\n+ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH\n+ * DAMAGE.\n+ * ========================================================================= */\n+\n+/** @file\n+ * This file contains the WUSB cryptographic routines.\n+ */\n+\n+#ifdef DWC_CRYPTOLIB\n+\n+#include \"dwc_crypto.h\"\n+#include \"usb.h\"\n+\n+#ifdef DEBUG\n+static inline void dump_bytes(char *name, uint8_t *bytes, int len)\n+{\n+\tint i;\n+\tDWC_PRINTF(\"%s: \", name);\n+\tfor (i=0; i<len; i++) {\n+\t\tDWC_PRINTF(\"%02x \", bytes[i]);\n+\t}\n+\tDWC_PRINTF(\"\\n\");\n+}\n+#else\n+#define dump_bytes(x...)\n+#endif\n+\n+/* Display a block */\n+void show_block(const u8 *blk, const char *prefix, const char *suffix, int a)\n+{\n+#ifdef DWC_DEBUG_CRYPTO\n+\tint i, blksize = 16;\n+\n+\tDWC_DEBUG(\"%s\", prefix);\n+\n+\tif (suffix == NULL) {\n+\t\tsuffix = \"\\n\";\n+\t\tblksize = a;\n+\t}\n+\n+\tfor (i = 0; i < blksize; i++)\n+\t\tDWC_PRINT(\"%02x%s\", *blk++, ((i & 3) == 3) ? \"  \" : \" \");\n+\tDWC_PRINT(suffix);\n+#endif\n+}\n+\n+/**\n+ * Encrypts an array of bytes using the AES encryption engine.\n+ * If <code>dst</code> == <code>src</code>, then the bytes will be encrypted\n+ * in-place.\n+ *\n+ * @return  0 on success, negative error code on error.\n+ */\n+int dwc_wusb_aes_encrypt(u8 *src, u8 *key, u8 *dst)\n+{\n+\tu8 block_t[16];\n+\tDWC_MEMSET(block_t, 0, 16);\n+\n+\treturn DWC_AES_CBC(src, 16, key, 16, block_t, dst);\n+}\n+\n+/**\n+ * The CCM-MAC-FUNCTION described in section 6.5 of the WUSB spec.\n+ * This function takes a data string and returns the encrypted CBC\n+ * Counter-mode MIC.\n+ *\n+ * @param key     The 128-bit symmetric key.\n+ * @param nonce   The CCM nonce.\n+ * @param label   The unique 14-byte ASCII text label.\n+ * @param bytes   The byte array to be encrypted.\n+ * @param len     Length of the byte array.\n+ * @param result  Byte array to receive the 8-byte encrypted MIC.\n+ */\n+void dwc_wusb_cmf(u8 *key, u8 *nonce,\n+\t\t  char *label, u8 *bytes, int len, u8 *result)\n+{\n+\tu8 block_m[16];\n+\tu8 block_x[16];\n+\tu8 block_t[8];\n+\tint idx, blkNum;\n+\tu16 la = (u16)(len + 14);\n+\n+\t/* Set the AES-128 key */\n+\t//dwc_aes_setkey(tfm, key, 16);\n+\n+\t/* Fill block B0 from flags = 0x59, N, and l(m) = 0 */\n+\tblock_m[0] = 0x59;\n+\tfor (idx = 0; idx < 13; idx++)\n+\t\tblock_m[idx + 1] = nonce[idx];\n+\tblock_m[14] = 0;\n+\tblock_m[15] = 0;\n+\n+\t/* Produce the CBC IV */\n+\tdwc_wusb_aes_encrypt(block_m, key, block_x);\n+\tshow_block(block_m, \"CBC IV in: \", \"\\n\", 0);\n+\tshow_block(block_x, \"CBC IV out:\", \"\\n\", 0);\n+\n+\t/* Fill block B1 from l(a) = Blen + 14, and A */\n+\tblock_x[0] ^= (u8)(la >> 8);\n+\tblock_x[1] ^= (u8)la;\n+\tfor (idx = 0; idx < 14; idx++)\n+\t\tblock_x[idx + 2] ^= label[idx];\n+\tshow_block(block_x, \"After xor: \", \"b1\\n\", 16);\n+\n+\tdwc_wusb_aes_encrypt(block_x, key, block_x);\n+\tshow_block(block_x, \"After AES: \", \"b1\\n\", 16);\n+\n+\tidx = 0;\n+\tblkNum = 0;\n+\n+\t/* Fill remaining blocks with B */\n+\twhile (len-- > 0) {\n+\t\tblock_x[idx] ^= *bytes++;\n+\t\tif (++idx >= 16) {\n+\t\t\tidx = 0;\n+\t\t\tshow_block(block_x, \"After xor: \", \"\\n\", blkNum);\n+\t\t\tdwc_wusb_aes_encrypt(block_x, key, block_x);\n+\t\t\tshow_block(block_x, \"After AES: \", \"\\n\", blkNum);\n+\t\t\tblkNum++;\n+\t\t}\n+\t}\n+\n+\t/* Handle partial last block */\n+\tif (idx > 0) {\n+\t\tshow_block(block_x, \"After xor: \", \"\\n\", blkNum);\n+\t\tdwc_wusb_aes_encrypt(block_x, key, block_x);\n+\t\tshow_block(block_x, \"After AES: \", \"\\n\", blkNum);\n+\t}\n+\n+\t/* Save the MIC tag */\n+\tDWC_MEMCPY(block_t, block_x, 8);\n+\tshow_block(block_t, \"MIC tag  : \", NULL, 8);\n+\n+\t/* Fill block A0 from flags = 0x01, N, and counter = 0 */\n+\tblock_m[0] = 0x01;\n+\tblock_m[14] = 0;\n+\tblock_m[15] = 0;\n+\n+\t/* Encrypt the counter */\n+\tdwc_wusb_aes_encrypt(block_m, key, block_x);\n+\tshow_block(block_x, \"CTR[MIC] : \", NULL, 8);\n+\n+\t/* XOR with MIC tag */\n+\tfor (idx = 0; idx < 8; idx++) {\n+\t\tblock_t[idx] ^= block_x[idx];\n+\t}\n+\n+\t/* Return result to caller */\n+\tDWC_MEMCPY(result, block_t, 8);\n+\tshow_block(result, \"CCM-MIC  : \", NULL, 8);\n+\n+}\n+\n+/**\n+ * The PRF function described in section 6.5 of the WUSB spec. This function\n+ * concatenates MIC values returned from dwc_cmf() to create a value of\n+ * the requested length.\n+ *\n+ * @param prf_len  Length of the PRF function in bits (64, 128, or 256).\n+ * @param key, nonce, label, bytes, len  Same as for dwc_cmf().\n+ * @param result   Byte array to receive the result.\n+ */\n+void dwc_wusb_prf(int prf_len, u8 *key,\n+\t\t  u8 *nonce, char *label, u8 *bytes, int len, u8 *result)\n+{\n+\tint i;\n+\n+\tnonce[0] = 0;\n+\tfor (i = 0; i < prf_len >> 6; i++, nonce[0]++) {\n+\t\tdwc_wusb_cmf(key, nonce, label, bytes, len, result);\n+\t\tresult += 8;\n+\t}\n+}\n+\n+/**\n+ * Fills in CCM Nonce per the WUSB spec.\n+ *\n+ * @param[in] haddr Host address.\n+ * @param[in] daddr Device address.\n+ * @param[in] tkid Session Key(PTK) identifier.\n+ * @param[out] nonce Pointer to where the CCM Nonce output is to be written.\n+ */\n+void dwc_wusb_fill_ccm_nonce(uint16_t haddr, uint16_t daddr, uint8_t *tkid,\n+\t\t\t     uint8_t *nonce)\n+{\n+\n+\tDWC_DEBUG(\"%s %x %x\\n\", __func__, daddr, haddr);\n+\n+\tDWC_MEMSET(&nonce[0], 0, 16);\n+\n+\tDWC_MEMCPY(&nonce[6], tkid, 3);\n+\tnonce[9] = daddr & 0xFF;\n+\tnonce[10] = (daddr >> 8) & 0xFF;\n+\tnonce[11] = haddr & 0xFF;\n+\tnonce[12] = (haddr >> 8) & 0xFF;\n+\n+\tdump_bytes(\"CCM nonce\", nonce, 16);\n+}\n+\n+/**\n+ * Generates a 16-byte cryptographic-grade random number for the Host/Device\n+ * Nonce.\n+ */\n+void dwc_wusb_gen_nonce(uint16_t addr, uint8_t *nonce)\n+{\n+\tuint8_t inonce[16];\n+\tuint32_t temp[4];\n+\n+\t/* Fill in the Nonce */\n+\tDWC_MEMSET(&inonce[0], 0, sizeof(inonce));\n+\tinonce[9] = addr & 0xFF;\n+\tinonce[10] = (addr >> 8) & 0xFF;\n+\tinonce[11] = inonce[9];\n+\tinonce[12] = inonce[10];\n+\n+\t/* Collect \"randomness samples\" */\n+\tDWC_RANDOM_BYTES((uint8_t *)temp, 16);\n+\n+\tdwc_wusb_prf_128((uint8_t *)temp, nonce,\n+\t\t\t \"Random Numbers\", (uint8_t *)temp, sizeof(temp),\n+\t\t\t nonce);\n+}\n+\n+/**\n+ * Generates the Session Key (PTK) and Key Confirmation Key (KCK) per the\n+ * WUSB spec.\n+ *\n+ * @param[in] ccm_nonce Pointer to CCM Nonce.\n+ * @param[in] mk Master Key to derive the session from\n+ * @param[in] hnonce Pointer to Host Nonce.\n+ * @param[in] dnonce Pointer to Device Nonce.\n+ * @param[out] kck Pointer to where the KCK output is to be written.\n+ * @param[out] ptk Pointer to where the PTK output is to be written.\n+ */\n+void dwc_wusb_gen_key(uint8_t *ccm_nonce, uint8_t *mk, uint8_t *hnonce,\n+\t\t      uint8_t *dnonce, uint8_t *kck, uint8_t *ptk)\n+{\n+\tuint8_t idata[32];\n+\tuint8_t odata[32];\n+\n+\tdump_bytes(\"ck\", mk, 16);\n+\tdump_bytes(\"hnonce\", hnonce, 16);\n+\tdump_bytes(\"dnonce\", dnonce, 16);\n+\n+\t/* The data is the HNonce and DNonce concatenated */\n+\tDWC_MEMCPY(&idata[0], hnonce, 16);\n+\tDWC_MEMCPY(&idata[16], dnonce, 16);\n+\n+\tdwc_wusb_prf_256(mk, ccm_nonce, \"Pair-wise keys\", idata, 32, odata);\n+\n+\t/* Low 16 bytes of the result is the KCK, high 16 is the PTK */\n+\tDWC_MEMCPY(kck, &odata[0], 16);\n+\tDWC_MEMCPY(ptk, &odata[16], 16);\n+\n+\tdump_bytes(\"kck\", kck, 16);\n+\tdump_bytes(\"ptk\", ptk, 16);\n+}\n+\n+/**\n+ * Generates the Message Integrity Code over the Handshake data per the\n+ * WUSB spec.\n+ *\n+ * @param ccm_nonce Pointer to CCM Nonce.\n+ * @param kck   Pointer to Key Confirmation Key.\n+ * @param data  Pointer to Handshake data to be checked.\n+ * @param mic   Pointer to where the MIC output is to be written.\n+ */\n+void dwc_wusb_gen_mic(uint8_t *ccm_nonce, uint8_t *kck,\n+\t\t      uint8_t *data, uint8_t *mic)\n+{\n+\n+\tdwc_wusb_prf_64(kck, ccm_nonce, \"out-of-bandMIC\",\n+\t\t\tdata, WUSB_HANDSHAKE_LEN_FOR_MIC, mic);\n+}\n+\n+#endif\t/* DWC_CRYPTOLIB */\n--- /dev/null\n+++ b/drivers/usb/host/dwc_common_port/dwc_crypto.h\n@@ -0,0 +1,111 @@\n+/* =========================================================================\n+ * $File: //dwh/usb_iip/dev/software/dwc_common_port_2/dwc_crypto.h $\n+ * $Revision: #3 $\n+ * $Date: 2010/09/28 $\n+ * $Change: 1596182 $\n+ *\n+ * Synopsys Portability Library Software and documentation\n+ * (hereinafter, \"Software\") is an Unsupported proprietary work of\n+ * Synopsys, Inc. unless otherwise expressly agreed to in writing\n+ * between Synopsys and you.\n+ *\n+ * The Software IS NOT an item of Licensed Software or Licensed Product\n+ * under any End User Software License Agreement or Agreement for\n+ * Licensed Product with Synopsys or any supplement thereto. You are\n+ * permitted to use and redistribute this Software in source and binary\n+ * forms, with or without modification, provided that redistributions\n+ * of source code must retain this notice. You may not view, use,\n+ * disclose, copy or distribute this file or any information contained\n+ * herein except pursuant to this license grant from Synopsys. If you\n+ * do not agree with this notice, including the disclaimer below, then\n+ * you are not authorized to use the Software.\n+ *\n+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN \"AS IS\"\n+ * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n+ * FOR A PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL\n+ * SYNOPSYS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\n+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\n+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR\n+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY\n+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE\n+ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH\n+ * DAMAGE.\n+ * ========================================================================= */\n+\n+#ifndef _DWC_CRYPTO_H_\n+#define _DWC_CRYPTO_H_\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+/** @file\n+ *\n+ * This file contains declarations for the WUSB Cryptographic routines as\n+ * defined in the WUSB spec.  They are only to be used internally by the DWC UWB\n+ * modules.\n+ */\n+\n+#include \"dwc_os.h\"\n+\n+int dwc_wusb_aes_encrypt(u8 *src, u8 *key, u8 *dst);\n+\n+void dwc_wusb_cmf(u8 *key, u8 *nonce,\n+\t\t  char *label, u8 *bytes, int len, u8 *result);\n+void dwc_wusb_prf(int prf_len, u8 *key,\n+\t\t  u8 *nonce, char *label, u8 *bytes, int len, u8 *result);\n+\n+/**\n+ * The PRF-64 function described in section 6.5 of the WUSB spec.\n+ *\n+ * @param key, nonce, label, bytes, len, result  Same as for dwc_prf().\n+ */\n+static inline void dwc_wusb_prf_64(u8 *key, u8 *nonce,\n+\t\t\t\t   char *label, u8 *bytes, int len, u8 *result)\n+{\n+\tdwc_wusb_prf(64, key, nonce, label, bytes, len, result);\n+}\n+\n+/**\n+ * The PRF-128 function described in section 6.5 of the WUSB spec.\n+ *\n+ * @param key, nonce, label, bytes, len, result  Same as for dwc_prf().\n+ */\n+static inline void dwc_wusb_prf_128(u8 *key, u8 *nonce,\n+\t\t\t\t    char *label, u8 *bytes, int len, u8 *result)\n+{\n+\tdwc_wusb_prf(128, key, nonce, label, bytes, len, result);\n+}\n+\n+/**\n+ * The PRF-256 function described in section 6.5 of the WUSB spec.\n+ *\n+ * @param key, nonce, label, bytes, len, result  Same as for dwc_prf().\n+ */\n+static inline void dwc_wusb_prf_256(u8 *key, u8 *nonce,\n+\t\t\t\t    char *label, u8 *bytes, int len, u8 *result)\n+{\n+\tdwc_wusb_prf(256, key, nonce, label, bytes, len, result);\n+}\n+\n+\n+void dwc_wusb_fill_ccm_nonce(uint16_t haddr, uint16_t daddr, uint8_t *tkid,\n+\t\t\t       uint8_t *nonce);\n+void dwc_wusb_gen_nonce(uint16_t addr,\n+\t\t\t  uint8_t *nonce);\n+\n+void dwc_wusb_gen_key(uint8_t *ccm_nonce, uint8_t *mk,\n+\t\t\tuint8_t *hnonce, uint8_t *dnonce,\n+\t\t\tuint8_t *kck, uint8_t *ptk);\n+\n+\n+void dwc_wusb_gen_mic(uint8_t *ccm_nonce, uint8_t\n+\t\t\t*kck, uint8_t *data, uint8_t *mic);\n+\n+#ifdef __cplusplus\n+}\n+#endif\n+\n+#endif /* _DWC_CRYPTO_H_ */\n--- /dev/null\n+++ b/drivers/usb/host/dwc_common_port/dwc_dh.c\n@@ -0,0 +1,291 @@\n+/* =========================================================================\n+ * $File: //dwh/usb_iip/dev/software/dwc_common_port_2/dwc_dh.c $\n+ * $Revision: #3 $\n+ * $Date: 2010/09/28 $\n+ * $Change: 1596182 $\n+ *\n+ * Synopsys Portability Library Software and documentation\n+ * (hereinafter, \"Software\") is an Unsupported proprietary work of\n+ * Synopsys, Inc. unless otherwise expressly agreed to in writing\n+ * between Synopsys and you.\n+ *\n+ * The Software IS NOT an item of Licensed Software or Licensed Product\n+ * under any End User Software License Agreement or Agreement for\n+ * Licensed Product with Synopsys or any supplement thereto. You are\n+ * permitted to use and redistribute this Software in source and binary\n+ * forms, with or without modification, provided that redistributions\n+ * of source code must retain this notice. You may not view, use,\n+ * disclose, copy or distribute this file or any information contained\n+ * herein except pursuant to this license grant from Synopsys. If you\n+ * do not agree with this notice, including the disclaimer below, then\n+ * you are not authorized to use the Software.\n+ *\n+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN \"AS IS\"\n+ * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n+ * FOR A PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL\n+ * SYNOPSYS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\n+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\n+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR\n+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY\n+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE\n+ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH\n+ * DAMAGE.\n+ * ========================================================================= */\n+#ifdef DWC_CRYPTOLIB\n+\n+#ifndef CONFIG_MACH_IPMATE\n+\n+#include \"dwc_dh.h\"\n+#include \"dwc_modpow.h\"\n+\n+#ifdef DEBUG\n+/* This function prints out a buffer in the format described in the Association\n+ * Model specification. */\n+static void dh_dump(char *str, void *_num, int len)\n+{\n+\tuint8_t *num = _num;\n+\tint i;\n+\tDWC_PRINTF(\"%s\\n\", str);\n+\tfor (i = 0; i < len; i ++) {\n+\t\tDWC_PRINTF(\"%02x\", num[i]);\n+\t\tif (((i + 1) % 2) == 0) DWC_PRINTF(\" \");\n+\t\tif (((i + 1) % 26) == 0) DWC_PRINTF(\"\\n\");\n+\t}\n+\n+\tDWC_PRINTF(\"\\n\");\n+}\n+#else\n+#define dh_dump(_x...) do {; } while(0)\n+#endif\n+\n+/* Constant g value */\n+static __u32 dh_g[] = {\n+\t0x02000000,\n+};\n+\n+/* Constant p value */\n+static __u32 dh_p[] = {\n+\t0xFFFFFFFF, 0xFFFFFFFF, 0xA2DA0FC9, 0x34C26821, 0x8B62C6C4, 0xD11CDC80, 0x084E0229, 0x74CC678A,\n+\t0xA6BE0B02, 0x229B133B, 0x79084A51, 0xDD04348E, 0xB31995EF, 0x1B433ACD, 0x6D0A2B30, 0x37145FF2,\n+\t0x6D35E14F, 0x45C2516D, 0x76B585E4, 0xC67E5E62, 0xE9424CF4, 0x6BED37A6, 0xB65CFF0B, 0xEDB706F4,\n+\t0xFB6B38EE, 0xA59F895A, 0x11249FAE, 0xE61F4B7C, 0x51662849, 0x3D5BE4EC, 0xB87C00C2, 0x05BF63A1,\n+\t0x3648DA98, 0x9AD3551C, 0xA83F1669, 0x5FCF24FD, 0x235D6583, 0x96ADA3DC, 0x56F3621C, 0xBB528520,\n+\t0x0729D59E, 0x6D969670, 0x4E350C67, 0x0498BC4A, 0x086C74F1, 0x7C2118CA, 0x465E9032, 0x3BCE362E,\n+\t0x2C779EE3, 0x03860E18, 0xA283279B, 0x8FA207EC, 0xF05DC5B5, 0xC9524C6F, 0xF6CB2BDE, 0x18175895,\n+\t0x7C499539, 0xE56A95EA, 0x1826D215, 0x1005FA98, 0x5A8E7215, 0x2DC4AA8A, 0x0D1733AD, 0x337A5004,\n+\t0xAB2155A8, 0x64BA1CDF, 0x0485FBEC, 0x0AEFDB58, 0x5771EA8A, 0x7D0C065D, 0x850F97B3, 0xC7E4E1A6,\n+\t0x8CAEF5AB, 0xD73309DB, 0xE0948C1E, 0x9D61254A, 0x26D2E3CE, 0x6BEED21A, 0x06FA2FF1, 0x64088AD9,\n+\t0x730276D8, 0x646AC83E, 0x182B1F52, 0x0C207B17, 0x5717E1BB, 0x6C5D617A, 0xC0880977, 0xE246D9BA,\n+\t0xA04FE208, 0x31ABE574, 0xFC5BDB43, 0x8E10FDE0, 0x20D1824B, 0xCAD23AA9, 0xFFFFFFFF, 0xFFFFFFFF,\n+};\n+\n+static void dh_swap_bytes(void *_in, void *_out, uint32_t len)\n+{\n+\tuint8_t *in = _in;\n+\tuint8_t *out = _out;\n+\tint i;\n+\tfor (i=0; i<len; i++) {\n+\t\tout[i] = in[len-1-i];\n+\t}\n+}\n+\n+/* Computes the modular exponentiation (num^exp % mod).  num, exp, and mod are\n+ * big endian numbers of size len, in bytes.  Each len value must be a multiple\n+ * of 4. */\n+int dwc_dh_modpow(void *mem_ctx, void *num, uint32_t num_len,\n+\t\t  void *exp, uint32_t exp_len,\n+\t\t  void *mod, uint32_t mod_len,\n+\t\t  void *out)\n+{\n+\t/* modpow() takes little endian numbers.  AM uses big-endian.  This\n+\t * function swaps bytes of numbers before passing onto modpow. */\n+\n+\tint retval = 0;\n+\tuint32_t *result;\n+\n+\tuint32_t *bignum_num = dwc_alloc(mem_ctx, num_len + 4);\n+\tuint32_t *bignum_exp = dwc_alloc(mem_ctx, exp_len + 4);\n+\tuint32_t *bignum_mod = dwc_alloc(mem_ctx, mod_len + 4);\n+\n+\tdh_swap_bytes(num, &bignum_num[1], num_len);\n+\tbignum_num[0] = num_len / 4;\n+\n+\tdh_swap_bytes(exp, &bignum_exp[1], exp_len);\n+\tbignum_exp[0] = exp_len / 4;\n+\n+\tdh_swap_bytes(mod, &bignum_mod[1], mod_len);\n+\tbignum_mod[0] = mod_len / 4;\n+\n+\tresult = dwc_modpow(mem_ctx, bignum_num, bignum_exp, bignum_mod);\n+\tif (!result) {\n+\t\tretval = -1;\n+\t\tgoto dh_modpow_nomem;\n+\t}\n+\n+\tdh_swap_bytes(&result[1], out, result[0] * 4);\n+\tdwc_free(mem_ctx, result);\n+\n+ dh_modpow_nomem:\n+\tdwc_free(mem_ctx, bignum_num);\n+\tdwc_free(mem_ctx, bignum_exp);\n+\tdwc_free(mem_ctx, bignum_mod);\n+\treturn retval;\n+}\n+\n+\n+int dwc_dh_pk(void *mem_ctx, uint8_t nd, uint8_t *exp, uint8_t *pk, uint8_t *hash)\n+{\n+\tint retval;\n+\tuint8_t m3[385];\n+\n+#ifndef DH_TEST_VECTORS\n+\tDWC_RANDOM_BYTES(exp, 32);\n+#endif\n+\n+\t/* Compute the pkd */\n+\tif ((retval = dwc_dh_modpow(mem_ctx, dh_g, 4,\n+\t\t\t\t    exp, 32,\n+\t\t\t\t    dh_p, 384, pk))) {\n+\t\treturn retval;\n+\t}\n+\n+\tm3[384] = nd;\n+\tDWC_MEMCPY(&m3[0], pk, 384);\n+\tDWC_SHA256(m3, 385, hash);\n+\n+\tdh_dump(\"PK\", pk, 384);\n+\tdh_dump(\"SHA-256(M3)\", hash, 32);\n+\treturn 0;\n+}\n+\n+int dwc_dh_derive_keys(void *mem_ctx, uint8_t nd, uint8_t *pkh, uint8_t *pkd,\n+\t\t       uint8_t *exp, int is_host,\n+\t\t       char *dd, uint8_t *ck, uint8_t *kdk)\n+{\n+\tint retval;\n+\tuint8_t mv[784];\n+\tuint8_t sha_result[32];\n+\tuint8_t dhkey[384];\n+\tuint8_t shared_secret[384];\n+\tchar *message;\n+\tuint32_t vd;\n+\n+\tuint8_t *pk;\n+\n+\tif (is_host) {\n+\t\tpk = pkd;\n+\t}\n+\telse {\n+\t\tpk = pkh;\n+\t}\n+\n+\tif ((retval = dwc_dh_modpow(mem_ctx, pk, 384,\n+\t\t\t\t    exp, 32,\n+\t\t\t\t    dh_p, 384, shared_secret))) {\n+\t\treturn retval;\n+\t}\n+\tdh_dump(\"Shared Secret\", shared_secret, 384);\n+\n+\tDWC_SHA256(shared_secret, 384, dhkey);\n+\tdh_dump(\"DHKEY\", dhkey, 384);\n+\n+\tDWC_MEMCPY(&mv[0], pkd, 384);\n+\tDWC_MEMCPY(&mv[384], pkh, 384);\n+\tDWC_MEMCPY(&mv[768], \"displayed digest\", 16);\n+\tdh_dump(\"MV\", mv, 784);\n+\n+\tDWC_SHA256(mv, 784, sha_result);\n+\tdh_dump(\"SHA-256(MV)\", sha_result, 32);\n+\tdh_dump(\"First 32-bits of SHA-256(MV)\", sha_result, 4);\n+\n+\tdh_swap_bytes(sha_result, &vd, 4);\n+#ifdef DEBUG\n+\tDWC_PRINTF(\"Vd (decimal) = %d\\n\", vd);\n+#endif\n+\n+\tswitch (nd) {\n+\tcase 2:\n+\t\tvd = vd % 100;\n+\t\tDWC_SPRINTF(dd, \"%02d\", vd);\n+\t\tbreak;\n+\tcase 3:\n+\t\tvd = vd % 1000;\n+\t\tDWC_SPRINTF(dd, \"%03d\", vd);\n+\t\tbreak;\n+\tcase 4:\n+\t\tvd = vd % 10000;\n+\t\tDWC_SPRINTF(dd, \"%04d\", vd);\n+\t\tbreak;\n+\t}\n+#ifdef DEBUG\n+\tDWC_PRINTF(\"Display Digits: %s\\n\", dd);\n+#endif\n+\n+\tmessage = \"connection key\";\n+\tDWC_HMAC_SHA256(message, DWC_STRLEN(message), dhkey, 32, sha_result);\n+\tdh_dump(\"HMAC(SHA-256, DHKey, connection key)\", sha_result, 32);\n+\tDWC_MEMCPY(ck, sha_result, 16);\n+\n+\tmessage = \"key derivation key\";\n+\tDWC_HMAC_SHA256(message, DWC_STRLEN(message), dhkey, 32, sha_result);\n+\tdh_dump(\"HMAC(SHA-256, DHKey, key derivation key)\", sha_result, 32);\n+\tDWC_MEMCPY(kdk, sha_result, 32);\n+\n+\treturn 0;\n+}\n+\n+\n+#ifdef DH_TEST_VECTORS\n+\n+static __u8 dh_a[] = {\n+\t0x44, 0x00, 0x51, 0xd6,\n+\t0xf0, 0xb5, 0x5e, 0xa9,\n+\t0x67, 0xab, 0x31, 0xc6,\n+\t0x8a, 0x8b, 0x5e, 0x37,\n+\t0xd9, 0x10, 0xda, 0xe0,\n+\t0xe2, 0xd4, 0x59, 0xa4,\n+\t0x86, 0x45, 0x9c, 0xaa,\n+\t0xdf, 0x36, 0x75, 0x16,\n+};\n+\n+static __u8 dh_b[] = {\n+\t0x5d, 0xae, 0xc7, 0x86,\n+\t0x79, 0x80, 0xa3, 0x24,\n+\t0x8c, 0xe3, 0x57, 0x8f,\n+\t0xc7, 0x5f, 0x1b, 0x0f,\n+\t0x2d, 0xf8, 0x9d, 0x30,\n+\t0x6f, 0xa4, 0x52, 0xcd,\n+\t0xe0, 0x7a, 0x04, 0x8a,\n+\t0xde, 0xd9, 0x26, 0x56,\n+};\n+\n+void dwc_run_dh_test_vectors(void *mem_ctx)\n+{\n+\tuint8_t pkd[384];\n+\tuint8_t pkh[384];\n+\tuint8_t hashd[32];\n+\tuint8_t hashh[32];\n+\tuint8_t ck[16];\n+\tuint8_t kdk[32];\n+\tchar dd[5];\n+\n+\tDWC_PRINTF(\"\\n\\n\\nDH_TEST_VECTORS\\n\\n\");\n+\n+\t/* compute the PKd and SHA-256(PKd || Nd) */\n+\tDWC_PRINTF(\"Computing PKd\\n\");\n+\tdwc_dh_pk(mem_ctx, 2, dh_a, pkd, hashd);\n+\n+\t/* compute the PKd and SHA-256(PKh || Nd) */\n+\tDWC_PRINTF(\"Computing PKh\\n\");\n+\tdwc_dh_pk(mem_ctx, 2, dh_b, pkh, hashh);\n+\n+\t/* compute the dhkey */\n+\tdwc_dh_derive_keys(mem_ctx, 2, pkh, pkd, dh_a, 0, dd, ck, kdk);\n+}\n+#endif /* DH_TEST_VECTORS */\n+\n+#endif /* !CONFIG_MACH_IPMATE */\n+\n+#endif /* DWC_CRYPTOLIB */\n--- /dev/null\n+++ b/drivers/usb/host/dwc_common_port/dwc_dh.h\n@@ -0,0 +1,106 @@\n+/* =========================================================================\n+ * $File: //dwh/usb_iip/dev/software/dwc_common_port_2/dwc_dh.h $\n+ * $Revision: #4 $\n+ * $Date: 2010/09/28 $\n+ * $Change: 1596182 $\n+ *\n+ * Synopsys Portability Library Software and documentation\n+ * (hereinafter, \"Software\") is an Unsupported proprietary work of\n+ * Synopsys, Inc. unless otherwise expressly agreed to in writing\n+ * between Synopsys and you.\n+ *\n+ * The Software IS NOT an item of Licensed Software or Licensed Product\n+ * under any End User Software License Agreement or Agreement for\n+ * Licensed Product with Synopsys or any supplement thereto. You are\n+ * permitted to use and redistribute this Software in source and binary\n+ * forms, with or without modification, provided that redistributions\n+ * of source code must retain this notice. You may not view, use,\n+ * disclose, copy or distribute this file or any information contained\n+ * herein except pursuant to this license grant from Synopsys. If you\n+ * do not agree with this notice, including the disclaimer below, then\n+ * you are not authorized to use the Software.\n+ *\n+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN \"AS IS\"\n+ * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n+ * FOR A PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL\n+ * SYNOPSYS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\n+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\n+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR\n+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY\n+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE\n+ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH\n+ * DAMAGE.\n+ * ========================================================================= */\n+#ifndef _DWC_DH_H_\n+#define _DWC_DH_H_\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+#include \"dwc_os.h\"\n+\n+/** @file\n+ *\n+ * This file defines the common functions on device and host for performing\n+ * numeric association as defined in the WUSB spec.  They are only to be\n+ * used internally by the DWC UWB modules. */\n+\n+extern int dwc_dh_sha256(uint8_t *message, uint32_t len, uint8_t *out);\n+extern int dwc_dh_hmac_sha256(uint8_t *message, uint32_t messagelen,\n+\t\t\t      uint8_t *key, uint32_t keylen,\n+\t\t\t      uint8_t *out);\n+extern int dwc_dh_modpow(void *mem_ctx, void *num, uint32_t num_len,\n+\t\t\t void *exp, uint32_t exp_len,\n+\t\t\t void *mod, uint32_t mod_len,\n+\t\t\t void *out);\n+\n+/** Computes PKD or PKH, and SHA-256(PKd || Nd)\n+ *\n+ * PK = g^exp mod p.\n+ *\n+ * Input:\n+ * Nd = Number of digits on the device.\n+ *\n+ * Output:\n+ * exp = A 32-byte buffer to be filled with a randomly generated number.\n+ *       used as either A or B.\n+ * pk = A 384-byte buffer to be filled with the PKH or PKD.\n+ * hash = A 32-byte buffer to be filled with SHA-256(PK || ND).\n+ */\n+extern int dwc_dh_pk(void *mem_ctx, uint8_t nd, uint8_t *exp, uint8_t *pkd, uint8_t *hash);\n+\n+/** Computes the DHKEY, and VD.\n+ *\n+ * If called from host, then it will comput DHKEY=PKD^exp % p.\n+ * If called from device, then it will comput DHKEY=PKH^exp % p.\n+ *\n+ * Input:\n+ * pkd = The PKD value.\n+ * pkh = The PKH value.\n+ * exp = The A value (if device) or B value (if host) generated in dwc_wudev_dh_pk.\n+ * is_host = Set to non zero if a WUSB host is calling this function.\n+ *\n+ * Output:\n+\n+ * dd = A pointer to an buffer to be set to the displayed digits string to be shown\n+ *      to the user.  This buffer should be at 5 bytes long to hold 4 digits plus a\n+ *      null termination character.  This buffer can be used directly for display.\n+ * ck = A 16-byte buffer to be filled with the CK.\n+ * kdk = A 32-byte buffer to be filled with the KDK.\n+ */\n+extern int dwc_dh_derive_keys(void *mem_ctx, uint8_t nd, uint8_t *pkh, uint8_t *pkd,\n+\t\t\t      uint8_t *exp, int is_host,\n+\t\t\t      char *dd, uint8_t *ck, uint8_t *kdk);\n+\n+#ifdef DH_TEST_VECTORS\n+extern void dwc_run_dh_test_vectors(void);\n+#endif\n+\n+#ifdef __cplusplus\n+}\n+#endif\n+\n+#endif /* _DWC_DH_H_ */\n--- /dev/null\n+++ b/drivers/usb/host/dwc_common_port/dwc_list.h\n@@ -0,0 +1,594 @@\n+/*\t$OpenBSD: queue.h,v 1.26 2004/05/04 16:59:32 grange Exp $\t*/\n+/*\t$NetBSD: queue.h,v 1.11 1996/05/16 05:17:14 mycroft Exp $\t*/\n+\n+/*\n+ * Copyright (c) 1991, 1993\n+ *\tThe Regents of the University of California.  All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ * 1. Redistributions of source code must retain the above copyright\n+ *    notice, this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright\n+ *    notice, this list of conditions and the following disclaimer in the\n+ *    documentation and/or other materials provided with the distribution.\n+ * 3. Neither the name of the University nor the names of its contributors\n+ *    may be used to endorse or promote products derived from this software\n+ *    without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n+ * SUCH DAMAGE.\n+ *\n+ *\t@(#)queue.h\t8.5 (Berkeley) 8/20/94\n+ */\n+\n+#ifndef _DWC_LIST_H_\n+#define _DWC_LIST_H_\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+/** @file\n+ *\n+ * This file defines linked list operations.  It is derived from BSD with\n+ * only the MACRO names being prefixed with DWC_.  This is because a few of\n+ * these names conflict with those on Linux.  For documentation on use, see the\n+ * inline comments in the source code.  The original license for this source\n+ * code applies and is preserved in the dwc_list.h source file.\n+ */\n+\n+/*\n+ * This file defines five types of data structures: singly-linked lists,\n+ * lists, simple queues, tail queues, and circular queues.\n+ *\n+ *\n+ * A singly-linked list is headed by a single forward pointer. The elements\n+ * are singly linked for minimum space and pointer manipulation overhead at\n+ * the expense of O(n) removal for arbitrary elements. New elements can be\n+ * added to the list after an existing element or at the head of the list.\n+ * Elements being removed from the head of the list should use the explicit\n+ * macro for this purpose for optimum efficiency. A singly-linked list may\n+ * only be traversed in the forward direction.  Singly-linked lists are ideal\n+ * for applications with large datasets and few or no removals or for\n+ * implementing a LIFO queue.\n+ *\n+ * A list is headed by a single forward pointer (or an array of forward\n+ * pointers for a hash table header). The elements are doubly linked\n+ * so that an arbitrary element can be removed without a need to\n+ * traverse the list. New elements can be added to the list before\n+ * or after an existing element or at the head of the list. A list\n+ * may only be traversed in the forward direction.\n+ *\n+ * A simple queue is headed by a pair of pointers, one the head of the\n+ * list and the other to the tail of the list. The elements are singly\n+ * linked to save space, so elements can only be removed from the\n+ * head of the list. New elements can be added to the list before or after\n+ * an existing element, at the head of the list, or at the end of the\n+ * list. A simple queue may only be traversed in the forward direction.\n+ *\n+ * A tail queue is headed by a pair of pointers, one to the head of the\n+ * list and the other to the tail of the list. The elements are doubly\n+ * linked so that an arbitrary element can be removed without a need to\n+ * traverse the list. New elements can be added to the list before or\n+ * after an existing element, at the head of the list, or at the end of\n+ * the list. A tail queue may be traversed in either direction.\n+ *\n+ * A circle queue is headed by a pair of pointers, one to the head of the\n+ * list and the other to the tail of the list. The elements are doubly\n+ * linked so that an arbitrary element can be removed without a need to\n+ * traverse the list. New elements can be added to the list before or after\n+ * an existing element, at the head of the list, or at the end of the list.\n+ * A circle queue may be traversed in either direction, but has a more\n+ * complex end of list detection.\n+ *\n+ * For details on the use of these macros, see the queue(3) manual page.\n+ */\n+\n+/*\n+ * Double-linked List.\n+ */\n+\n+typedef struct dwc_list_link {\n+\tstruct dwc_list_link *next;\n+\tstruct dwc_list_link *prev;\n+} dwc_list_link_t;\n+\n+#define DWC_LIST_INIT(link) do {\t\\\n+\t(link)->next = (link);\t\t\\\n+\t(link)->prev = (link);\t\t\\\n+} while (0)\n+\n+#define DWC_LIST_FIRST(link)\t((link)->next)\n+#define DWC_LIST_LAST(link)\t((link)->prev)\n+#define DWC_LIST_END(link)\t(link)\n+#define DWC_LIST_NEXT(link)\t((link)->next)\n+#define DWC_LIST_PREV(link)\t((link)->prev)\n+#define DWC_LIST_EMPTY(link)\t\\\n+\t(DWC_LIST_FIRST(link) == DWC_LIST_END(link))\n+#define DWC_LIST_ENTRY(link, type, field)\t\t\t\\\n+\t(type *)((uint8_t *)(link) - (size_t)(&((type *)0)->field))\n+\n+#if 0\n+#define DWC_LIST_INSERT_HEAD(list, link) do {\t\t\t\\\n+\t(link)->next = (list)->next;\t\t\t\t\\\n+\t(link)->prev = (list);\t\t\t\t\t\\\n+\t(list)->next->prev = (link);\t\t\t\t\\\n+\t(list)->next = (link);\t\t\t\t\t\\\n+} while (0)\n+\n+#define DWC_LIST_INSERT_TAIL(list, link) do {\t\t\t\\\n+\t(link)->next = (list);\t\t\t\t\t\\\n+\t(link)->prev = (list)->prev;\t\t\t\t\\\n+\t(list)->prev->next = (link);\t\t\t\t\\\n+\t(list)->prev = (link);\t\t\t\t\t\\\n+} while (0)\n+#else\n+#define DWC_LIST_INSERT_HEAD(list, link) do {\t\t\t\\\n+\tdwc_list_link_t *__next__ = (list)->next;\t\t\\\n+\t__next__->prev = (link);\t\t\t\t\\\n+\t(link)->next = __next__;\t\t\t\t\\\n+\t(link)->prev = (list);\t\t\t\t\t\\\n+\t(list)->next = (link);\t\t\t\t\t\\\n+} while (0)\n+\n+#define DWC_LIST_INSERT_TAIL(list, link) do {\t\t\t\\\n+\tdwc_list_link_t *__prev__ = (list)->prev;\t\t\\\n+\t(list)->prev = (link);\t\t\t\t\t\\\n+\t(link)->next = (list);\t\t\t\t\t\\\n+\t(link)->prev = __prev__;\t\t\t\t\\\n+\t__prev__->next = (link);\t\t\t\t\\\n+} while (0)\n+#endif\n+\n+#if 0\n+static inline void __list_add(struct list_head *new,\n+                              struct list_head *prev,\n+                              struct list_head *next)\n+{\n+        next->prev = new;\n+        new->next = next;\n+        new->prev = prev;\n+        prev->next = new;\n+}\n+\n+static inline void list_add(struct list_head *new, struct list_head *head)\n+{\n+        __list_add(new, head, head->next);\n+}\n+\n+static inline void list_add_tail(struct list_head *new, struct list_head *head)\n+{\n+        __list_add(new, head->prev, head);\n+}\n+\n+static inline void __list_del(struct list_head * prev, struct list_head * next)\n+{\n+        next->prev = prev;\n+        prev->next = next;\n+}\n+\n+static inline void list_del(struct list_head *entry)\n+{\n+        __list_del(entry->prev, entry->next);\n+        entry->next = LIST_POISON1;\n+        entry->prev = LIST_POISON2;\n+}\n+#endif\n+\n+#define DWC_LIST_REMOVE(link) do {\t\t\t\t\\\n+\t(link)->next->prev = (link)->prev;\t\t\t\\\n+\t(link)->prev->next = (link)->next;\t\t\t\\\n+} while (0)\n+\n+#define DWC_LIST_REMOVE_INIT(link) do {\t\t\t\t\\\n+\tDWC_LIST_REMOVE(link);\t\t\t\t\t\\\n+\tDWC_LIST_INIT(link);\t\t\t\t\t\\\n+} while (0)\n+\n+#define DWC_LIST_MOVE_HEAD(list, link) do {\t\t\t\\\n+\tDWC_LIST_REMOVE(link);\t\t\t\t\t\\\n+\tDWC_LIST_INSERT_HEAD(list, link);\t\t\t\\\n+} while (0)\n+\n+#define DWC_LIST_MOVE_TAIL(list, link) do {\t\t\t\\\n+\tDWC_LIST_REMOVE(link);\t\t\t\t\t\\\n+\tDWC_LIST_INSERT_TAIL(list, link);\t\t\t\\\n+} while (0)\n+\n+#define DWC_LIST_FOREACH(var, list)\t\t\t\t\\\n+\tfor((var) = DWC_LIST_FIRST(list);\t\t\t\\\n+\t    (var) != DWC_LIST_END(list);\t\t\t\\\n+\t    (var) = DWC_LIST_NEXT(var))\n+\n+#define DWC_LIST_FOREACH_SAFE(var, var2, list)\t\t\t\\\n+\tfor((var) = DWC_LIST_FIRST(list), (var2) = DWC_LIST_NEXT(var);\t\\\n+\t    (var) != DWC_LIST_END(list);\t\t\t\\\n+\t    (var) = (var2), (var2) = DWC_LIST_NEXT(var2))\n+\n+#define DWC_LIST_FOREACH_REVERSE(var, list)\t\t\t\\\n+\tfor((var) = DWC_LIST_LAST(list);\t\t\t\\\n+\t    (var) != DWC_LIST_END(list);\t\t\t\\\n+\t    (var) = DWC_LIST_PREV(var))\n+\n+/*\n+ * Singly-linked List definitions.\n+ */\n+#define DWC_SLIST_HEAD(name, type)\t\t\t\t\t\\\n+struct name {\t\t\t\t\t\t\t\t\\\n+\tstruct type *slh_first;\t/* first element */\t\t\t\\\n+}\n+\n+#define DWC_SLIST_HEAD_INITIALIZER(head)\t\t\t\t\\\n+\t{ NULL }\n+\n+#define DWC_SLIST_ENTRY(type)\t\t\t\t\t\t\\\n+struct {\t\t\t\t\t\t\t\t\\\n+\tstruct type *sle_next;\t/* next element */\t\t\t\\\n+}\n+\n+/*\n+ * Singly-linked List access methods.\n+ */\n+#define DWC_SLIST_FIRST(head)\t((head)->slh_first)\n+#define DWC_SLIST_END(head)\t\tNULL\n+#define DWC_SLIST_EMPTY(head)\t(SLIST_FIRST(head) == SLIST_END(head))\n+#define DWC_SLIST_NEXT(elm, field)\t((elm)->field.sle_next)\n+\n+#define DWC_SLIST_FOREACH(var, head, field)\t\t\t\t\\\n+\tfor((var) = SLIST_FIRST(head);\t\t\t\t\t\\\n+\t    (var) != SLIST_END(head);\t\t\t\t\t\\\n+\t    (var) = SLIST_NEXT(var, field))\n+\n+#define DWC_SLIST_FOREACH_PREVPTR(var, varp, head, field)\t\t\\\n+\tfor((varp) = &SLIST_FIRST((head));\t\t\t\t\\\n+\t    ((var) = *(varp)) != SLIST_END(head);\t\t\t\\\n+\t    (varp) = &SLIST_NEXT((var), field))\n+\n+/*\n+ * Singly-linked List functions.\n+ */\n+#define DWC_SLIST_INIT(head) {\t\t\t\t\t\t\\\n+\tSLIST_FIRST(head) = SLIST_END(head);\t\t\t\t\\\n+}\n+\n+#define DWC_SLIST_INSERT_AFTER(slistelm, elm, field) do {\t\t\\\n+\t(elm)->field.sle_next = (slistelm)->field.sle_next;\t\t\\\n+\t(slistelm)->field.sle_next = (elm);\t\t\t\t\\\n+} while (0)\n+\n+#define DWC_SLIST_INSERT_HEAD(head, elm, field) do {\t\t\t\\\n+\t(elm)->field.sle_next = (head)->slh_first;\t\t\t\\\n+\t(head)->slh_first = (elm);\t\t\t\t\t\\\n+} while (0)\n+\n+#define DWC_SLIST_REMOVE_NEXT(head, elm, field) do {\t\t\t\\\n+\t(elm)->field.sle_next = (elm)->field.sle_next->field.sle_next;\t\\\n+} while (0)\n+\n+#define DWC_SLIST_REMOVE_HEAD(head, field) do {\t\t\t\t\\\n+\t(head)->slh_first = (head)->slh_first->field.sle_next;\t\t\\\n+} while (0)\n+\n+#define DWC_SLIST_REMOVE(head, elm, type, field) do {\t\t\t\\\n+\tif ((head)->slh_first == (elm)) {\t\t\t\t\\\n+\t\tSLIST_REMOVE_HEAD((head), field);\t\t\t\\\n+\t}\t\t\t\t\t\t\t\t\\\n+\telse {\t\t\t\t\t\t\t\t\\\n+\t\tstruct type *curelm = (head)->slh_first;\t\t\\\n+\t\twhile( curelm->field.sle_next != (elm) )\t\t\\\n+\t\t\tcurelm = curelm->field.sle_next;\t\t\\\n+\t\tcurelm->field.sle_next =\t\t\t\t\\\n+\t\t    curelm->field.sle_next->field.sle_next;\t\t\\\n+\t}\t\t\t\t\t\t\t\t\\\n+} while (0)\n+\n+/*\n+ * Simple queue definitions.\n+ */\n+#define DWC_SIMPLEQ_HEAD(name, type)\t\t\t\t\t\\\n+struct name {\t\t\t\t\t\t\t\t\\\n+\tstruct type *sqh_first;\t/* first element */\t\t\t\\\n+\tstruct type **sqh_last;\t/* addr of last next element */\t\t\\\n+}\n+\n+#define DWC_SIMPLEQ_HEAD_INITIALIZER(head)\t\t\t\t\\\n+\t{ NULL, &(head).sqh_first }\n+\n+#define DWC_SIMPLEQ_ENTRY(type)\t\t\t\t\t\t\\\n+struct {\t\t\t\t\t\t\t\t\\\n+\tstruct type *sqe_next;\t/* next element */\t\t\t\\\n+}\n+\n+/*\n+ * Simple queue access methods.\n+ */\n+#define DWC_SIMPLEQ_FIRST(head)\t    ((head)->sqh_first)\n+#define DWC_SIMPLEQ_END(head)\t    NULL\n+#define DWC_SIMPLEQ_EMPTY(head)\t    (SIMPLEQ_FIRST(head) == SIMPLEQ_END(head))\n+#define DWC_SIMPLEQ_NEXT(elm, field)    ((elm)->field.sqe_next)\n+\n+#define DWC_SIMPLEQ_FOREACH(var, head, field)\t\t\t\t\\\n+\tfor((var) = SIMPLEQ_FIRST(head);\t\t\t\t\\\n+\t    (var) != SIMPLEQ_END(head);\t\t\t\t\t\\\n+\t    (var) = SIMPLEQ_NEXT(var, field))\n+\n+/*\n+ * Simple queue functions.\n+ */\n+#define DWC_SIMPLEQ_INIT(head) do {\t\t\t\t\t\\\n+\t(head)->sqh_first = NULL;\t\t\t\t\t\\\n+\t(head)->sqh_last = &(head)->sqh_first;\t\t\t\t\\\n+} while (0)\n+\n+#define DWC_SIMPLEQ_INSERT_HEAD(head, elm, field) do {\t\t\t\\\n+\tif (((elm)->field.sqe_next = (head)->sqh_first) == NULL)\t\\\n+\t\t(head)->sqh_last = &(elm)->field.sqe_next;\t\t\\\n+\t(head)->sqh_first = (elm);\t\t\t\t\t\\\n+} while (0)\n+\n+#define DWC_SIMPLEQ_INSERT_TAIL(head, elm, field) do {\t\t\t\\\n+\t(elm)->field.sqe_next = NULL;\t\t\t\t\t\\\n+\t*(head)->sqh_last = (elm);\t\t\t\t\t\\\n+\t(head)->sqh_last = &(elm)->field.sqe_next;\t\t\t\\\n+} while (0)\n+\n+#define DWC_SIMPLEQ_INSERT_AFTER(head, listelm, elm, field) do {\t\\\n+\tif (((elm)->field.sqe_next = (listelm)->field.sqe_next) == NULL)\\\n+\t\t(head)->sqh_last = &(elm)->field.sqe_next;\t\t\\\n+\t(listelm)->field.sqe_next = (elm);\t\t\t\t\\\n+} while (0)\n+\n+#define DWC_SIMPLEQ_REMOVE_HEAD(head, field) do {\t\t\t\\\n+\tif (((head)->sqh_first = (head)->sqh_first->field.sqe_next) == NULL) \\\n+\t\t(head)->sqh_last = &(head)->sqh_first;\t\t\t\\\n+} while (0)\n+\n+/*\n+ * Tail queue definitions.\n+ */\n+#define DWC_TAILQ_HEAD(name, type)\t\t\t\t\t\\\n+struct name {\t\t\t\t\t\t\t\t\\\n+\tstruct type *tqh_first;\t/* first element */\t\t\t\\\n+\tstruct type **tqh_last;\t/* addr of last next element */\t\t\\\n+}\n+\n+#define DWC_TAILQ_HEAD_INITIALIZER(head)\t\t\t\t\\\n+\t{ NULL, &(head).tqh_first }\n+\n+#define DWC_TAILQ_ENTRY(type)\t\t\t\t\t\t\\\n+struct {\t\t\t\t\t\t\t\t\\\n+\tstruct type *tqe_next;\t/* next element */\t\t\t\\\n+\tstruct type **tqe_prev;\t/* address of previous next element */\t\\\n+}\n+\n+/*\n+ * tail queue access methods\n+ */\n+#define DWC_TAILQ_FIRST(head)\t\t((head)->tqh_first)\n+#define DWC_TAILQ_END(head)\t\tNULL\n+#define DWC_TAILQ_NEXT(elm, field)\t((elm)->field.tqe_next)\n+#define DWC_TAILQ_LAST(head, headname)\t\t\t\t\t\\\n+\t(*(((struct headname *)((head)->tqh_last))->tqh_last))\n+/* XXX */\n+#define DWC_TAILQ_PREV(elm, headname, field)\t\t\t\t\\\n+\t(*(((struct headname *)((elm)->field.tqe_prev))->tqh_last))\n+#define DWC_TAILQ_EMPTY(head)\t\t\t\t\t\t\\\n+\t(DWC_TAILQ_FIRST(head) == DWC_TAILQ_END(head))\n+\n+#define DWC_TAILQ_FOREACH(var, head, field)\t\t\t\t\\\n+\tfor ((var) = DWC_TAILQ_FIRST(head);\t\t\t\t\\\n+\t    (var) != DWC_TAILQ_END(head);\t\t\t\t\\\n+\t    (var) = DWC_TAILQ_NEXT(var, field))\n+\n+#define DWC_TAILQ_FOREACH_REVERSE(var, head, headname, field)\t\t\\\n+\tfor ((var) = DWC_TAILQ_LAST(head, headname);\t\t\t\\\n+\t    (var) != DWC_TAILQ_END(head);\t\t\t\t\\\n+\t    (var) = DWC_TAILQ_PREV(var, headname, field))\n+\n+/*\n+ * Tail queue functions.\n+ */\n+#define DWC_TAILQ_INIT(head) do {\t\t\t\t\t\\\n+\t(head)->tqh_first = NULL;\t\t\t\t\t\\\n+\t(head)->tqh_last = &(head)->tqh_first;\t\t\t\t\\\n+} while (0)\n+\n+#define DWC_TAILQ_INSERT_HEAD(head, elm, field) do {\t\t\t\\\n+\tif (((elm)->field.tqe_next = (head)->tqh_first) != NULL)\t\\\n+\t\t(head)->tqh_first->field.tqe_prev =\t\t\t\\\n+\t\t    &(elm)->field.tqe_next;\t\t\t\t\\\n+\telse\t\t\t\t\t\t\t\t\\\n+\t\t(head)->tqh_last = &(elm)->field.tqe_next;\t\t\\\n+\t(head)->tqh_first = (elm);\t\t\t\t\t\\\n+\t(elm)->field.tqe_prev = &(head)->tqh_first;\t\t\t\\\n+} while (0)\n+\n+#define DWC_TAILQ_INSERT_TAIL(head, elm, field) do {\t\t\t\\\n+\t(elm)->field.tqe_next = NULL;\t\t\t\t\t\\\n+\t(elm)->field.tqe_prev = (head)->tqh_last;\t\t\t\\\n+\t*(head)->tqh_last = (elm);\t\t\t\t\t\\\n+\t(head)->tqh_last = &(elm)->field.tqe_next;\t\t\t\\\n+} while (0)\n+\n+#define DWC_TAILQ_INSERT_AFTER(head, listelm, elm, field) do {\t\t\\\n+\tif (((elm)->field.tqe_next = (listelm)->field.tqe_next) != NULL)\\\n+\t\t(elm)->field.tqe_next->field.tqe_prev =\t\t\t\\\n+\t\t    &(elm)->field.tqe_next;\t\t\t\t\\\n+\telse\t\t\t\t\t\t\t\t\\\n+\t\t(head)->tqh_last = &(elm)->field.tqe_next;\t\t\\\n+\t(listelm)->field.tqe_next = (elm);\t\t\t\t\\\n+\t(elm)->field.tqe_prev = &(listelm)->field.tqe_next;\t\t\\\n+} while (0)\n+\n+#define DWC_TAILQ_INSERT_BEFORE(listelm, elm, field) do {\t\t\\\n+\t(elm)->field.tqe_prev = (listelm)->field.tqe_prev;\t\t\\\n+\t(elm)->field.tqe_next = (listelm);\t\t\t\t\\\n+\t*(listelm)->field.tqe_prev = (elm);\t\t\t\t\\\n+\t(listelm)->field.tqe_prev = &(elm)->field.tqe_next;\t\t\\\n+} while (0)\n+\n+#define DWC_TAILQ_REMOVE(head, elm, field) do {\t\t\t\t\\\n+\tif (((elm)->field.tqe_next) != NULL)\t\t\t\t\\\n+\t\t(elm)->field.tqe_next->field.tqe_prev =\t\t\t\\\n+\t\t    (elm)->field.tqe_prev;\t\t\t\t\\\n+\telse\t\t\t\t\t\t\t\t\\\n+\t\t(head)->tqh_last = (elm)->field.tqe_prev;\t\t\\\n+\t*(elm)->field.tqe_prev = (elm)->field.tqe_next;\t\t\t\\\n+} while (0)\n+\n+#define DWC_TAILQ_REPLACE(head, elm, elm2, field) do {\t\t\t\\\n+\tif (((elm2)->field.tqe_next = (elm)->field.tqe_next) != NULL)\t\\\n+\t\t(elm2)->field.tqe_next->field.tqe_prev =\t\t\\\n+\t\t    &(elm2)->field.tqe_next;\t\t\t\t\\\n+\telse\t\t\t\t\t\t\t\t\\\n+\t\t(head)->tqh_last = &(elm2)->field.tqe_next;\t\t\\\n+\t(elm2)->field.tqe_prev = (elm)->field.tqe_prev;\t\t\t\\\n+\t*(elm2)->field.tqe_prev = (elm2);\t\t\t\t\\\n+} while (0)\n+\n+/*\n+ * Circular queue definitions.\n+ */\n+#define DWC_CIRCLEQ_HEAD(name, type)\t\t\t\t\t\\\n+struct name {\t\t\t\t\t\t\t\t\\\n+\tstruct type *cqh_first;\t\t/* first element */\t\t\\\n+\tstruct type *cqh_last;\t\t/* last element */\t\t\\\n+}\n+\n+#define DWC_CIRCLEQ_HEAD_INITIALIZER(head)\t\t\t\t\\\n+\t{ DWC_CIRCLEQ_END(&head), DWC_CIRCLEQ_END(&head) }\n+\n+#define DWC_CIRCLEQ_ENTRY(type)\t\t\t\t\t\t\\\n+struct {\t\t\t\t\t\t\t\t\\\n+\tstruct type *cqe_next;\t\t/* next element */\t\t\\\n+\tstruct type *cqe_prev;\t\t/* previous element */\t\t\\\n+}\n+\n+/*\n+ * Circular queue access methods\n+ */\n+#define DWC_CIRCLEQ_FIRST(head)\t\t((head)->cqh_first)\n+#define DWC_CIRCLEQ_LAST(head)\t\t((head)->cqh_last)\n+#define DWC_CIRCLEQ_END(head)\t\t((void *)(head))\n+#define DWC_CIRCLEQ_NEXT(elm, field)\t((elm)->field.cqe_next)\n+#define DWC_CIRCLEQ_PREV(elm, field)\t((elm)->field.cqe_prev)\n+#define DWC_CIRCLEQ_EMPTY(head)\t\t\t\t\t\t\\\n+\t(DWC_CIRCLEQ_FIRST(head) == DWC_CIRCLEQ_END(head))\n+\n+#define DWC_CIRCLEQ_EMPTY_ENTRY(elm, field) (((elm)->field.cqe_next == NULL) && ((elm)->field.cqe_prev == NULL))\n+\n+#define DWC_CIRCLEQ_FOREACH(var, head, field)\t\t\t\t\\\n+\tfor((var) = DWC_CIRCLEQ_FIRST(head);\t\t\t\t\\\n+\t    (var) != DWC_CIRCLEQ_END(head);\t\t\t\t\\\n+\t    (var) = DWC_CIRCLEQ_NEXT(var, field))\n+\n+#define DWC_CIRCLEQ_FOREACH_SAFE(var, var2, head, field)\t\t\t\\\n+\tfor((var) = DWC_CIRCLEQ_FIRST(head), var2 = DWC_CIRCLEQ_NEXT(var, field); \\\n+\t    (var) != DWC_CIRCLEQ_END(head);\t\t\t\t\t\\\n+\t    (var) = var2, var2 = DWC_CIRCLEQ_NEXT(var, field))\n+\n+#define DWC_CIRCLEQ_FOREACH_REVERSE(var, head, field)\t\t\t\\\n+\tfor((var) = DWC_CIRCLEQ_LAST(head);\t\t\t\t\\\n+\t    (var) != DWC_CIRCLEQ_END(head);\t\t\t\t\\\n+\t    (var) = DWC_CIRCLEQ_PREV(var, field))\n+\n+/*\n+ * Circular queue functions.\n+ */\n+#define DWC_CIRCLEQ_INIT(head) do {\t\t\t\t\t\\\n+\t(head)->cqh_first = DWC_CIRCLEQ_END(head);\t\t\t\\\n+\t(head)->cqh_last = DWC_CIRCLEQ_END(head);\t\t\t\\\n+} while (0)\n+\n+#define DWC_CIRCLEQ_INIT_ENTRY(elm, field) do {\t\t\t\t\\\n+\t(elm)->field.cqe_next = NULL;\t\t\t\t\t\\\n+\t(elm)->field.cqe_prev = NULL;\t\t\t\t\t\\\n+} while (0)\n+\n+#define DWC_CIRCLEQ_INSERT_AFTER(head, listelm, elm, field) do {\t\\\n+\t(elm)->field.cqe_next = (listelm)->field.cqe_next;\t\t\\\n+\t(elm)->field.cqe_prev = (listelm);\t\t\t\t\\\n+\tif ((listelm)->field.cqe_next == DWC_CIRCLEQ_END(head))\t\t\\\n+\t\t(head)->cqh_last = (elm);\t\t\t\t\\\n+\telse\t\t\t\t\t\t\t\t\\\n+\t\t(listelm)->field.cqe_next->field.cqe_prev = (elm);\t\\\n+\t(listelm)->field.cqe_next = (elm);\t\t\t\t\\\n+} while (0)\n+\n+#define DWC_CIRCLEQ_INSERT_BEFORE(head, listelm, elm, field) do {\t\\\n+\t(elm)->field.cqe_next = (listelm);\t\t\t\t\\\n+\t(elm)->field.cqe_prev = (listelm)->field.cqe_prev;\t\t\\\n+\tif ((listelm)->field.cqe_prev == DWC_CIRCLEQ_END(head))\t\t\\\n+\t\t(head)->cqh_first = (elm);\t\t\t\t\\\n+\telse\t\t\t\t\t\t\t\t\\\n+\t\t(listelm)->field.cqe_prev->field.cqe_next = (elm);\t\\\n+\t(listelm)->field.cqe_prev = (elm);\t\t\t\t\\\n+} while (0)\n+\n+#define DWC_CIRCLEQ_INSERT_HEAD(head, elm, field) do {\t\t\t\\\n+\t(elm)->field.cqe_next = (head)->cqh_first;\t\t\t\\\n+\t(elm)->field.cqe_prev = DWC_CIRCLEQ_END(head);\t\t\t\\\n+\tif ((head)->cqh_last == DWC_CIRCLEQ_END(head))\t\t\t\\\n+\t\t(head)->cqh_last = (elm);\t\t\t\t\\\n+\telse\t\t\t\t\t\t\t\t\\\n+\t\t(head)->cqh_first->field.cqe_prev = (elm);\t\t\\\n+\t(head)->cqh_first = (elm);\t\t\t\t\t\\\n+} while (0)\n+\n+#define DWC_CIRCLEQ_INSERT_TAIL(head, elm, field) do {\t\t\t\\\n+\t(elm)->field.cqe_next = DWC_CIRCLEQ_END(head);\t\t\t\\\n+\t(elm)->field.cqe_prev = (head)->cqh_last;\t\t\t\\\n+\tif ((head)->cqh_first == DWC_CIRCLEQ_END(head))\t\t\t\\\n+\t\t(head)->cqh_first = (elm);\t\t\t\t\\\n+\telse\t\t\t\t\t\t\t\t\\\n+\t\t(head)->cqh_last->field.cqe_next = (elm);\t\t\\\n+\t(head)->cqh_last = (elm);\t\t\t\t\t\\\n+} while (0)\n+\n+#define DWC_CIRCLEQ_REMOVE(head, elm, field) do {\t\t\t\\\n+\tif ((elm)->field.cqe_next == DWC_CIRCLEQ_END(head))\t\t\\\n+\t\t(head)->cqh_last = (elm)->field.cqe_prev;\t\t\\\n+\telse\t\t\t\t\t\t\t\t\\\n+\t\t(elm)->field.cqe_next->field.cqe_prev =\t\t\t\\\n+\t\t    (elm)->field.cqe_prev;\t\t\t\t\\\n+\tif ((elm)->field.cqe_prev == DWC_CIRCLEQ_END(head))\t\t\\\n+\t\t(head)->cqh_first = (elm)->field.cqe_next;\t\t\\\n+\telse\t\t\t\t\t\t\t\t\\\n+\t\t(elm)->field.cqe_prev->field.cqe_next =\t\t\t\\\n+\t\t    (elm)->field.cqe_next;\t\t\t\t\\\n+} while (0)\n+\n+#define DWC_CIRCLEQ_REMOVE_INIT(head, elm, field) do {\t\t\t\\\n+\tDWC_CIRCLEQ_REMOVE(head, elm, field);\t\t\t\t\\\n+\tDWC_CIRCLEQ_INIT_ENTRY(elm, field);\t\t\t\t\\\n+} while (0)\n+\n+#define DWC_CIRCLEQ_REPLACE(head, elm, elm2, field) do {\t\t\\\n+\tif (((elm2)->field.cqe_next = (elm)->field.cqe_next) ==\t\t\\\n+\t    DWC_CIRCLEQ_END(head))\t\t\t\t\t\\\n+\t\t(head).cqh_last = (elm2);\t\t\t\t\\\n+\telse\t\t\t\t\t\t\t\t\\\n+\t\t(elm2)->field.cqe_next->field.cqe_prev = (elm2);\t\\\n+\tif (((elm2)->field.cqe_prev = (elm)->field.cqe_prev) ==\t\t\\\n+\t    DWC_CIRCLEQ_END(head))\t\t\t\t\t\\\n+\t\t(head).cqh_first = (elm2);\t\t\t\t\\\n+\telse\t\t\t\t\t\t\t\t\\\n+\t\t(elm2)->field.cqe_prev->field.cqe_next = (elm2);\t\\\n+} while (0)\n+\n+#ifdef __cplusplus\n+}\n+#endif\n+\n+#endif /* _DWC_LIST_H_ */\n--- /dev/null\n+++ b/drivers/usb/host/dwc_common_port/dwc_mem.c\n@@ -0,0 +1,245 @@\n+/* Memory Debugging */\n+#ifdef DWC_DEBUG_MEMORY\n+\n+#include \"dwc_os.h\"\n+#include \"dwc_list.h\"\n+\n+struct allocation {\n+\tvoid *addr;\n+\tvoid *ctx;\n+\tchar *func;\n+\tint line;\n+\tuint32_t size;\n+\tint dma;\n+\tDWC_CIRCLEQ_ENTRY(allocation) entry;\n+};\n+\n+DWC_CIRCLEQ_HEAD(allocation_queue, allocation);\n+\n+struct allocation_manager {\n+\tvoid *mem_ctx;\n+\tstruct allocation_queue allocations;\n+\n+\t/* statistics */\n+\tint num;\n+\tint num_freed;\n+\tint num_active;\n+\tuint32_t total;\n+\tuint32_t cur;\n+\tuint32_t max;\n+};\n+\n+static struct allocation_manager *manager = NULL;\n+\n+static int add_allocation(void *ctx, uint32_t size, char const *func, int line, void *addr,\n+\t\t\t  int dma)\n+{\n+\tstruct allocation *a;\n+\n+\tDWC_ASSERT(manager != NULL, \"manager not allocated\");\n+\n+\ta = __DWC_ALLOC_ATOMIC(manager->mem_ctx, sizeof(*a));\n+\tif (!a) {\n+\t\treturn -DWC_E_NO_MEMORY;\n+\t}\n+\n+\ta->func = __DWC_ALLOC_ATOMIC(manager->mem_ctx, DWC_STRLEN(func) + 1);\n+\tif (!a->func) {\n+\t\t__DWC_FREE(manager->mem_ctx, a);\n+\t\treturn -DWC_E_NO_MEMORY;\n+\t}\n+\n+\tDWC_MEMCPY(a->func, func, DWC_STRLEN(func) + 1);\n+\ta->addr = addr;\n+\ta->ctx = ctx;\n+\ta->line = line;\n+\ta->size = size;\n+\ta->dma = dma;\n+\tDWC_CIRCLEQ_INSERT_TAIL(&manager->allocations, a, entry);\n+\n+\t/* Update stats */\n+\tmanager->num++;\n+\tmanager->num_active++;\n+\tmanager->total += size;\n+\tmanager->cur += size;\n+\n+\tif (manager->max < manager->cur) {\n+\t\tmanager->max = manager->cur;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static struct allocation *find_allocation(void *ctx, void *addr)\n+{\n+\tstruct allocation *a;\n+\n+\tDWC_CIRCLEQ_FOREACH(a, &manager->allocations, entry) {\n+\t\tif (a->ctx == ctx && a->addr == addr) {\n+\t\t\treturn a;\n+\t\t}\n+\t}\n+\n+\treturn NULL;\n+}\n+\n+static void free_allocation(void *ctx, void *addr, char const *func, int line)\n+{\n+\tstruct allocation *a = find_allocation(ctx, addr);\n+\n+\tif (!a) {\n+\t\tDWC_ASSERT(0,\n+\t\t\t   \"Free of address %p that was never allocated or already freed %s:%d\",\n+\t\t\t   addr, func, line);\n+\t\treturn;\n+\t}\n+\n+\tDWC_CIRCLEQ_REMOVE(&manager->allocations, a, entry);\n+\n+\tmanager->num_active--;\n+\tmanager->num_freed++;\n+\tmanager->cur -= a->size;\n+\t__DWC_FREE(manager->mem_ctx, a->func);\n+\t__DWC_FREE(manager->mem_ctx, a);\n+}\n+\n+int dwc_memory_debug_start(void *mem_ctx)\n+{\n+\tDWC_ASSERT(manager == NULL, \"Memory debugging has already started\\n\");\n+\n+\tif (manager) {\n+\t\treturn -DWC_E_BUSY;\n+\t}\n+\n+\tmanager = __DWC_ALLOC(mem_ctx, sizeof(*manager));\n+\tif (!manager) {\n+\t\treturn -DWC_E_NO_MEMORY;\n+\t}\n+\n+\tDWC_CIRCLEQ_INIT(&manager->allocations);\n+\tmanager->mem_ctx = mem_ctx;\n+\tmanager->num = 0;\n+\tmanager->num_freed = 0;\n+\tmanager->num_active = 0;\n+\tmanager->total = 0;\n+\tmanager->cur = 0;\n+\tmanager->max = 0;\n+\n+\treturn 0;\n+}\n+\n+void dwc_memory_debug_stop(void)\n+{\n+\tstruct allocation *a;\n+\n+\tdwc_memory_debug_report();\n+\n+\tDWC_CIRCLEQ_FOREACH(a, &manager->allocations, entry) {\n+\t\tDWC_ERROR(\"Memory leaked from %s:%d\\n\", a->func, a->line);\n+\t\tfree_allocation(a->ctx, a->addr, NULL, -1);\n+\t}\n+\n+\t__DWC_FREE(manager->mem_ctx, manager);\n+}\n+\n+void dwc_memory_debug_report(void)\n+{\n+\tstruct allocation *a;\n+\n+\tDWC_PRINTF(\"\\n\\n\\n----------------- Memory Debugging Report -----------------\\n\\n\");\n+\tDWC_PRINTF(\"Num Allocations = %d\\n\", manager->num);\n+\tDWC_PRINTF(\"Freed = %d\\n\", manager->num_freed);\n+\tDWC_PRINTF(\"Active = %d\\n\", manager->num_active);\n+\tDWC_PRINTF(\"Current Memory Used = %d\\n\", manager->cur);\n+\tDWC_PRINTF(\"Total Memory Used = %d\\n\", manager->total);\n+\tDWC_PRINTF(\"Maximum Memory Used at Once = %d\\n\", manager->max);\n+\tDWC_PRINTF(\"Unfreed allocations:\\n\");\n+\n+\tDWC_CIRCLEQ_FOREACH(a, &manager->allocations, entry) {\n+\t\tDWC_PRINTF(\"    addr=%p, size=%d from %s:%d, DMA=%d\\n\",\n+\t\t\t   a->addr, a->size, a->func, a->line, a->dma);\n+\t}\n+}\n+\n+/* The replacement functions */\n+void *dwc_alloc_debug(void *mem_ctx, uint32_t size, char const *func, int line)\n+{\n+\tvoid *addr = __DWC_ALLOC(mem_ctx, size);\n+\n+\tif (!addr) {\n+\t\treturn NULL;\n+\t}\n+\n+\tif (add_allocation(mem_ctx, size, func, line, addr, 0)) {\n+\t\t__DWC_FREE(mem_ctx, addr);\n+\t\treturn NULL;\n+\t}\n+\n+\treturn addr;\n+}\n+\n+void *dwc_alloc_atomic_debug(void *mem_ctx, uint32_t size, char const *func,\n+\t\t\t     int line)\n+{\n+\tvoid *addr = __DWC_ALLOC_ATOMIC(mem_ctx, size);\n+\n+\tif (!addr) {\n+\t\treturn NULL;\n+\t}\n+\n+\tif (add_allocation(mem_ctx, size, func, line, addr, 0)) {\n+\t\t__DWC_FREE(mem_ctx, addr);\n+\t\treturn NULL;\n+\t}\n+\n+\treturn addr;\n+}\n+\n+void dwc_free_debug(void *mem_ctx, void *addr, char const *func, int line)\n+{\n+\tfree_allocation(mem_ctx, addr, func, line);\n+\t__DWC_FREE(mem_ctx, addr);\n+}\n+\n+void *dwc_dma_alloc_debug(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr,\n+\t\t\t  char const *func, int line)\n+{\n+\tvoid *addr = __DWC_DMA_ALLOC(dma_ctx, size, dma_addr);\n+\n+\tif (!addr) {\n+\t\treturn NULL;\n+\t}\n+\n+\tif (add_allocation(dma_ctx, size, func, line, addr, 1)) {\n+\t\t__DWC_DMA_FREE(dma_ctx, size, addr, *dma_addr);\n+\t\treturn NULL;\n+\t}\n+\n+\treturn addr;\n+}\n+\n+void *dwc_dma_alloc_atomic_debug(void *dma_ctx, uint32_t size,\n+\t\t\t\t dwc_dma_t *dma_addr, char const *func, int line)\n+{\n+\tvoid *addr = __DWC_DMA_ALLOC_ATOMIC(dma_ctx, size, dma_addr);\n+\n+\tif (!addr) {\n+\t\treturn NULL;\n+\t}\n+\n+\tif (add_allocation(dma_ctx, size, func, line, addr, 1)) {\n+\t\t__DWC_DMA_FREE(dma_ctx, size, addr, *dma_addr);\n+\t\treturn NULL;\n+\t}\n+\n+\treturn addr;\n+}\n+\n+void dwc_dma_free_debug(void *dma_ctx, uint32_t size, void *virt_addr,\n+\t\t\tdwc_dma_t dma_addr, char const *func, int line)\n+{\n+\tfree_allocation(dma_ctx, virt_addr, func, line);\n+\t__DWC_DMA_FREE(dma_ctx, size, virt_addr, dma_addr);\n+}\n+\n+#endif /* DWC_DEBUG_MEMORY */\n--- /dev/null\n+++ b/drivers/usb/host/dwc_common_port/dwc_modpow.c\n@@ -0,0 +1,636 @@\n+/* Bignum routines adapted from PUTTY sources.  PuTTY copyright notice follows.\n+ *\n+ * PuTTY is copyright 1997-2007 Simon Tatham.\n+ *\n+ * Portions copyright Robert de Bath, Joris van Rantwijk, Delian\n+ * Delchev, Andreas Schultz, Jeroen Massar, Wez Furlong, Nicolas Barry,\n+ * Justin Bradford, Ben Harris, Malcolm Smith, Ahmad Khalifa, Markus\n+ * Kuhn, and CORE SDI S.A.\n+ *\n+ * Permission is hereby granted, free of charge, to any person\n+ * obtaining a copy of this software and associated documentation files\n+ * (the \"Software\"), to deal in the Software without restriction,\n+ * including without limitation the rights to use, copy, modify, merge,\n+ * publish, distribute, sublicense, and/or sell copies of the Software,\n+ * and to permit persons to whom the Software is furnished to do so,\n+ * subject to the following conditions:\n+ *\n+ * The above copyright notice and this permission notice shall be\n+ * included in all copies or substantial portions of the Software.\n+\n+ * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n+ * NONINFRINGEMENT.  IN NO EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE\n+ * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF\n+ * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION\n+ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n+ *\n+ */\n+#ifdef DWC_CRYPTOLIB\n+\n+#ifndef CONFIG_MACH_IPMATE\n+\n+#include \"dwc_modpow.h\"\n+\n+#define BIGNUM_INT_MASK  0xFFFFFFFFUL\n+#define BIGNUM_TOP_BIT   0x80000000UL\n+#define BIGNUM_INT_BITS  32\n+\n+\n+static void *snmalloc(void *mem_ctx, size_t n, size_t size)\n+{\n+    void *p;\n+    size *= n;\n+    if (size == 0) size = 1;\n+    p = dwc_alloc(mem_ctx, size);\n+    return p;\n+}\n+\n+#define snewn(ctx, n, type) ((type *)snmalloc((ctx), (n), sizeof(type)))\n+#define sfree dwc_free\n+\n+/*\n+ * Usage notes:\n+ *  * Do not call the DIVMOD_WORD macro with expressions such as array\n+ *    subscripts, as some implementations object to this (see below).\n+ *  * Note that none of the division methods below will cope if the\n+ *    quotient won't fit into BIGNUM_INT_BITS. Callers should be careful\n+ *    to avoid this case.\n+ *    If this condition occurs, in the case of the x86 DIV instruction,\n+ *    an overflow exception will occur, which (according to a correspondent)\n+ *    will manifest on Windows as something like\n+ *      0xC0000095: Integer overflow\n+ *    The C variant won't give the right answer, either.\n+ */\n+\n+#define MUL_WORD(w1, w2) ((BignumDblInt)w1 * w2)\n+\n+#if defined __GNUC__ && defined __i386__\n+#define DIVMOD_WORD(q, r, hi, lo, w) \\\n+    __asm__(\"div %2\" : \\\n+\t    \"=d\" (r), \"=a\" (q) : \\\n+\t    \"r\" (w), \"d\" (hi), \"a\" (lo))\n+#else\n+#define DIVMOD_WORD(q, r, hi, lo, w) do { \\\n+    BignumDblInt n = (((BignumDblInt)hi) << BIGNUM_INT_BITS) | lo; \\\n+    q = n / w; \\\n+    r = n % w; \\\n+} while (0)\n+#endif\n+\n+//    q = n / w;\n+//    r = n % w;\n+\n+#define BIGNUM_INT_BYTES (BIGNUM_INT_BITS / 8)\n+\n+#define BIGNUM_INTERNAL\n+\n+static Bignum newbn(void *mem_ctx, int length)\n+{\n+    Bignum b = snewn(mem_ctx, length + 1, BignumInt);\n+    //if (!b)\n+    //abort();\t\t       /* FIXME */\n+    DWC_MEMSET(b, 0, (length + 1) * sizeof(*b));\n+    b[0] = length;\n+    return b;\n+}\n+\n+void freebn(void *mem_ctx, Bignum b)\n+{\n+    /*\n+     * Burn the evidence, just in case.\n+     */\n+    DWC_MEMSET(b, 0, sizeof(b[0]) * (b[0] + 1));\n+    sfree(mem_ctx, b);\n+}\n+\n+/*\n+ * Compute c = a * b.\n+ * Input is in the first len words of a and b.\n+ * Result is returned in the first 2*len words of c.\n+ */\n+static void internal_mul(BignumInt *a, BignumInt *b,\n+\t\t\t BignumInt *c, int len)\n+{\n+    int i, j;\n+    BignumDblInt t;\n+\n+    for (j = 0; j < 2 * len; j++)\n+\tc[j] = 0;\n+\n+    for (i = len - 1; i >= 0; i--) {\n+\tt = 0;\n+\tfor (j = len - 1; j >= 0; j--) {\n+\t    t += MUL_WORD(a[i], (BignumDblInt) b[j]);\n+\t    t += (BignumDblInt) c[i + j + 1];\n+\t    c[i + j + 1] = (BignumInt) t;\n+\t    t = t >> BIGNUM_INT_BITS;\n+\t}\n+\tc[i] = (BignumInt) t;\n+    }\n+}\n+\n+static void internal_add_shifted(BignumInt *number,\n+\t\t\t\t unsigned n, int shift)\n+{\n+    int word = 1 + (shift / BIGNUM_INT_BITS);\n+    int bshift = shift % BIGNUM_INT_BITS;\n+    BignumDblInt addend;\n+\n+    addend = (BignumDblInt)n << bshift;\n+\n+    while (addend) {\n+\taddend += number[word];\n+\tnumber[word] = (BignumInt) addend & BIGNUM_INT_MASK;\n+\taddend >>= BIGNUM_INT_BITS;\n+\tword++;\n+    }\n+}\n+\n+/*\n+ * Compute a = a % m.\n+ * Input in first alen words of a and first mlen words of m.\n+ * Output in first alen words of a\n+ * (of which first alen-mlen words will be zero).\n+ * The MSW of m MUST have its high bit set.\n+ * Quotient is accumulated in the `quotient' array, which is a Bignum\n+ * rather than the internal bigendian format. Quotient parts are shifted\n+ * left by `qshift' before adding into quot.\n+ */\n+static void internal_mod(BignumInt *a, int alen,\n+\t\t\t BignumInt *m, int mlen,\n+\t\t\t BignumInt *quot, int qshift)\n+{\n+    BignumInt m0, m1;\n+    unsigned int h;\n+    int i, k;\n+\n+    m0 = m[0];\n+    if (mlen > 1)\n+\tm1 = m[1];\n+    else\n+\tm1 = 0;\n+\n+    for (i = 0; i <= alen - mlen; i++) {\n+\tBignumDblInt t;\n+\tunsigned int q, r, c, ai1;\n+\n+\tif (i == 0) {\n+\t    h = 0;\n+\t} else {\n+\t    h = a[i - 1];\n+\t    a[i - 1] = 0;\n+\t}\n+\n+\tif (i == alen - 1)\n+\t    ai1 = 0;\n+\telse\n+\t    ai1 = a[i + 1];\n+\n+\t/* Find q = h:a[i] / m0 */\n+\tif (h >= m0) {\n+\t    /*\n+\t     * Special case.\n+\t     *\n+\t     * To illustrate it, suppose a BignumInt is 8 bits, and\n+\t     * we are dividing (say) A1:23:45:67 by A1:B2:C3. Then\n+\t     * our initial division will be 0xA123 / 0xA1, which\n+\t     * will give a quotient of 0x100 and a divide overflow.\n+\t     * However, the invariants in this division algorithm\n+\t     * are not violated, since the full number A1:23:... is\n+\t     * _less_ than the quotient prefix A1:B2:... and so the\n+\t     * following correction loop would have sorted it out.\n+\t     *\n+\t     * In this situation we set q to be the largest\n+\t     * quotient we _can_ stomach (0xFF, of course).\n+\t     */\n+\t    q = BIGNUM_INT_MASK;\n+\t} else {\n+\t    /* Macro doesn't want an array subscript expression passed\n+\t     * into it (see definition), so use a temporary. */\n+\t    BignumInt tmplo = a[i];\n+\t    DIVMOD_WORD(q, r, h, tmplo, m0);\n+\n+\t    /* Refine our estimate of q by looking at\n+\t     h:a[i]:a[i+1] / m0:m1 */\n+\t    t = MUL_WORD(m1, q);\n+\t    if (t > ((BignumDblInt) r << BIGNUM_INT_BITS) + ai1) {\n+\t\tq--;\n+\t\tt -= m1;\n+\t\tr = (r + m0) & BIGNUM_INT_MASK;     /* overflow? */\n+\t\tif (r >= (BignumDblInt) m0 &&\n+\t\t    t > ((BignumDblInt) r << BIGNUM_INT_BITS) + ai1) q--;\n+\t    }\n+\t}\n+\n+\t/* Subtract q * m from a[i...] */\n+\tc = 0;\n+\tfor (k = mlen - 1; k >= 0; k--) {\n+\t    t = MUL_WORD(q, m[k]);\n+\t    t += c;\n+\t    c = (unsigned)(t >> BIGNUM_INT_BITS);\n+\t    if ((BignumInt) t > a[i + k])\n+\t\tc++;\n+\t    a[i + k] -= (BignumInt) t;\n+\t}\n+\n+\t/* Add back m in case of borrow */\n+\tif (c != h) {\n+\t    t = 0;\n+\t    for (k = mlen - 1; k >= 0; k--) {\n+\t\tt += m[k];\n+\t\tt += a[i + k];\n+\t\ta[i + k] = (BignumInt) t;\n+\t\tt = t >> BIGNUM_INT_BITS;\n+\t    }\n+\t    q--;\n+\t}\n+\tif (quot)\n+\t    internal_add_shifted(quot, q, qshift + BIGNUM_INT_BITS * (alen - mlen - i));\n+    }\n+}\n+\n+/*\n+ * Compute p % mod.\n+ * The most significant word of mod MUST be non-zero.\n+ * We assume that the result array is the same size as the mod array.\n+ * We optionally write out a quotient if `quotient' is non-NULL.\n+ * We can avoid writing out the result if `result' is NULL.\n+ */\n+void bigdivmod(void *mem_ctx, Bignum p, Bignum mod, Bignum result, Bignum quotient)\n+{\n+    BignumInt *n, *m;\n+    int mshift;\n+    int plen, mlen, i, j;\n+\n+    /* Allocate m of size mlen, copy mod to m */\n+    /* We use big endian internally */\n+    mlen = mod[0];\n+    m = snewn(mem_ctx, mlen, BignumInt);\n+    //if (!m)\n+    //abort();\t\t       /* FIXME */\n+    for (j = 0; j < mlen; j++)\n+\tm[j] = mod[mod[0] - j];\n+\n+    /* Shift m left to make msb bit set */\n+    for (mshift = 0; mshift < BIGNUM_INT_BITS-1; mshift++)\n+\tif ((m[0] << mshift) & BIGNUM_TOP_BIT)\n+\t    break;\n+    if (mshift) {\n+\tfor (i = 0; i < mlen - 1; i++)\n+\t    m[i] = (m[i] << mshift) | (m[i + 1] >> (BIGNUM_INT_BITS - mshift));\n+\tm[mlen - 1] = m[mlen - 1] << mshift;\n+    }\n+\n+    plen = p[0];\n+    /* Ensure plen > mlen */\n+    if (plen <= mlen)\n+\tplen = mlen + 1;\n+\n+    /* Allocate n of size plen, copy p to n */\n+    n = snewn(mem_ctx, plen, BignumInt);\n+    //if (!n)\n+    //abort();\t\t       /* FIXME */\n+    for (j = 0; j < plen; j++)\n+\tn[j] = 0;\n+    for (j = 1; j <= (int)p[0]; j++)\n+\tn[plen - j] = p[j];\n+\n+    /* Main computation */\n+    internal_mod(n, plen, m, mlen, quotient, mshift);\n+\n+    /* Fixup result in case the modulus was shifted */\n+    if (mshift) {\n+\tfor (i = plen - mlen - 1; i < plen - 1; i++)\n+\t    n[i] = (n[i] << mshift) | (n[i + 1] >> (BIGNUM_INT_BITS - mshift));\n+\tn[plen - 1] = n[plen - 1] << mshift;\n+\tinternal_mod(n, plen, m, mlen, quotient, 0);\n+\tfor (i = plen - 1; i >= plen - mlen; i--)\n+\t    n[i] = (n[i] >> mshift) | (n[i - 1] << (BIGNUM_INT_BITS - mshift));\n+    }\n+\n+    /* Copy result to buffer */\n+    if (result) {\n+\tfor (i = 1; i <= (int)result[0]; i++) {\n+\t    int j = plen - i;\n+\t    result[i] = j >= 0 ? n[j] : 0;\n+\t}\n+    }\n+\n+    /* Free temporary arrays */\n+    for (i = 0; i < mlen; i++)\n+\tm[i] = 0;\n+    sfree(mem_ctx, m);\n+    for (i = 0; i < plen; i++)\n+\tn[i] = 0;\n+    sfree(mem_ctx, n);\n+}\n+\n+/*\n+ * Simple remainder.\n+ */\n+Bignum bigmod(void *mem_ctx, Bignum a, Bignum b)\n+{\n+    Bignum r = newbn(mem_ctx, b[0]);\n+    bigdivmod(mem_ctx, a, b, r, NULL);\n+    return r;\n+}\n+\n+/*\n+ * Compute (base ^ exp) % mod.\n+ */\n+Bignum dwc_modpow(void *mem_ctx, Bignum base_in, Bignum exp, Bignum mod)\n+{\n+    BignumInt *a, *b, *n, *m;\n+    int mshift;\n+    int mlen, i, j;\n+    Bignum base, result;\n+\n+    /*\n+     * The most significant word of mod needs to be non-zero. It\n+     * should already be, but let's make sure.\n+     */\n+    //assert(mod[mod[0]] != 0);\n+\n+    /*\n+     * Make sure the base is smaller than the modulus, by reducing\n+     * it modulo the modulus if not.\n+     */\n+    base = bigmod(mem_ctx, base_in, mod);\n+\n+    /* Allocate m of size mlen, copy mod to m */\n+    /* We use big endian internally */\n+    mlen = mod[0];\n+    m = snewn(mem_ctx, mlen, BignumInt);\n+    //if (!m)\n+    //abort();\t\t       /* FIXME */\n+    for (j = 0; j < mlen; j++)\n+\tm[j] = mod[mod[0] - j];\n+\n+    /* Shift m left to make msb bit set */\n+    for (mshift = 0; mshift < BIGNUM_INT_BITS - 1; mshift++)\n+\tif ((m[0] << mshift) & BIGNUM_TOP_BIT)\n+\t    break;\n+    if (mshift) {\n+\tfor (i = 0; i < mlen - 1; i++)\n+\t    m[i] =\n+\t\t(m[i] << mshift) | (m[i + 1] >>\n+\t\t\t\t    (BIGNUM_INT_BITS - mshift));\n+\tm[mlen - 1] = m[mlen - 1] << mshift;\n+    }\n+\n+    /* Allocate n of size mlen, copy base to n */\n+    n = snewn(mem_ctx, mlen, BignumInt);\n+    //if (!n)\n+    //abort();\t\t       /* FIXME */\n+    i = mlen - base[0];\n+    for (j = 0; j < i; j++)\n+\tn[j] = 0;\n+    for (j = 0; j < base[0]; j++)\n+\tn[i + j] = base[base[0] - j];\n+\n+    /* Allocate a and b of size 2*mlen. Set a = 1 */\n+    a = snewn(mem_ctx, 2 * mlen, BignumInt);\n+    //if (!a)\n+    //abort();\t\t       /* FIXME */\n+    b = snewn(mem_ctx, 2 * mlen, BignumInt);\n+    //if (!b)\n+    //abort();\t\t       /* FIXME */\n+    for (i = 0; i < 2 * mlen; i++)\n+\ta[i] = 0;\n+    a[2 * mlen - 1] = 1;\n+\n+    /* Skip leading zero bits of exp. */\n+    i = 0;\n+    j = BIGNUM_INT_BITS - 1;\n+    while (i < exp[0] && (exp[exp[0] - i] & (1 << j)) == 0) {\n+\tj--;\n+\tif (j < 0) {\n+\t    i++;\n+\t    j = BIGNUM_INT_BITS - 1;\n+\t}\n+    }\n+\n+    /* Main computation */\n+    while (i < exp[0]) {\n+\twhile (j >= 0) {\n+\t    internal_mul(a + mlen, a + mlen, b, mlen);\n+\t    internal_mod(b, mlen * 2, m, mlen, NULL, 0);\n+\t    if ((exp[exp[0] - i] & (1 << j)) != 0) {\n+\t\tinternal_mul(b + mlen, n, a, mlen);\n+\t\tinternal_mod(a, mlen * 2, m, mlen, NULL, 0);\n+\t    } else {\n+\t\tBignumInt *t;\n+\t\tt = a;\n+\t\ta = b;\n+\t\tb = t;\n+\t    }\n+\t    j--;\n+\t}\n+\ti++;\n+\tj = BIGNUM_INT_BITS - 1;\n+    }\n+\n+    /* Fixup result in case the modulus was shifted */\n+    if (mshift) {\n+\tfor (i = mlen - 1; i < 2 * mlen - 1; i++)\n+\t    a[i] =\n+\t\t(a[i] << mshift) | (a[i + 1] >>\n+\t\t\t\t    (BIGNUM_INT_BITS - mshift));\n+\ta[2 * mlen - 1] = a[2 * mlen - 1] << mshift;\n+\tinternal_mod(a, mlen * 2, m, mlen, NULL, 0);\n+\tfor (i = 2 * mlen - 1; i >= mlen; i--)\n+\t    a[i] =\n+\t\t(a[i] >> mshift) | (a[i - 1] <<\n+\t\t\t\t    (BIGNUM_INT_BITS - mshift));\n+    }\n+\n+    /* Copy result to buffer */\n+    result = newbn(mem_ctx, mod[0]);\n+    for (i = 0; i < mlen; i++)\n+\tresult[result[0] - i] = a[i + mlen];\n+    while (result[0] > 1 && result[result[0]] == 0)\n+\tresult[0]--;\n+\n+    /* Free temporary arrays */\n+    for (i = 0; i < 2 * mlen; i++)\n+\ta[i] = 0;\n+    sfree(mem_ctx, a);\n+    for (i = 0; i < 2 * mlen; i++)\n+\tb[i] = 0;\n+    sfree(mem_ctx, b);\n+    for (i = 0; i < mlen; i++)\n+\tm[i] = 0;\n+    sfree(mem_ctx, m);\n+    for (i = 0; i < mlen; i++)\n+\tn[i] = 0;\n+    sfree(mem_ctx, n);\n+\n+    freebn(mem_ctx, base);\n+\n+    return result;\n+}\n+\n+\n+#ifdef UNITTEST\n+\n+static __u32 dh_p[] = {\n+\t96,\n+\t0xFFFFFFFF,\n+\t0xFFFFFFFF,\n+\t0xA93AD2CA,\n+\t0x4B82D120,\n+\t0xE0FD108E,\n+\t0x43DB5BFC,\n+\t0x74E5AB31,\n+\t0x08E24FA0,\n+\t0xBAD946E2,\n+\t0x770988C0,\n+\t0x7A615D6C,\n+\t0xBBE11757,\n+\t0x177B200C,\n+\t0x521F2B18,\n+\t0x3EC86A64,\n+\t0xD8760273,\n+\t0xD98A0864,\n+\t0xF12FFA06,\n+\t0x1AD2EE6B,\n+\t0xCEE3D226,\n+\t0x4A25619D,\n+\t0x1E8C94E0,\n+\t0xDB0933D7,\n+\t0xABF5AE8C,\n+\t0xA6E1E4C7,\n+\t0xB3970F85,\n+\t0x5D060C7D,\n+\t0x8AEA7157,\n+\t0x58DBEF0A,\n+\t0xECFB8504,\n+\t0xDF1CBA64,\n+\t0xA85521AB,\n+\t0x04507A33,\n+\t0xAD33170D,\n+\t0x8AAAC42D,\n+\t0x15728E5A,\n+\t0x98FA0510,\n+\t0x15D22618,\n+\t0xEA956AE5,\n+\t0x3995497C,\n+\t0x95581718,\n+\t0xDE2BCBF6,\n+\t0x6F4C52C9,\n+\t0xB5C55DF0,\n+\t0xEC07A28F,\n+\t0x9B2783A2,\n+\t0x180E8603,\n+\t0xE39E772C,\n+\t0x2E36CE3B,\n+\t0x32905E46,\n+\t0xCA18217C,\n+\t0xF1746C08,\n+\t0x4ABC9804,\n+\t0x670C354E,\n+\t0x7096966D,\n+\t0x9ED52907,\n+\t0x208552BB,\n+\t0x1C62F356,\n+\t0xDCA3AD96,\n+\t0x83655D23,\n+\t0xFD24CF5F,\n+\t0x69163FA8,\n+\t0x1C55D39A,\n+\t0x98DA4836,\n+\t0xA163BF05,\n+\t0xC2007CB8,\n+\t0xECE45B3D,\n+\t0x49286651,\n+\t0x7C4B1FE6,\n+\t0xAE9F2411,\n+\t0x5A899FA5,\n+\t0xEE386BFB,\n+\t0xF406B7ED,\n+\t0x0BFF5CB6,\n+\t0xA637ED6B,\n+\t0xF44C42E9,\n+\t0x625E7EC6,\n+\t0xE485B576,\n+\t0x6D51C245,\n+\t0x4FE1356D,\n+\t0xF25F1437,\n+\t0x302B0A6D,\n+\t0xCD3A431B,\n+\t0xEF9519B3,\n+\t0x8E3404DD,\n+\t0x514A0879,\n+\t0x3B139B22,\n+\t0x020BBEA6,\n+\t0x8A67CC74,\n+\t0x29024E08,\n+\t0x80DC1CD1,\n+\t0xC4C6628B,\n+\t0x2168C234,\n+\t0xC90FDAA2,\n+\t0xFFFFFFFF,\n+\t0xFFFFFFFF,\n+};\n+\n+static __u32 dh_a[] = {\n+\t8,\n+\t0xdf367516,\n+\t0x86459caa,\n+\t0xe2d459a4,\n+\t0xd910dae0,\n+\t0x8a8b5e37,\n+\t0x67ab31c6,\n+\t0xf0b55ea9,\n+\t0x440051d6,\n+};\n+\n+static __u32 dh_b[] = {\n+\t8,\n+\t0xded92656,\n+\t0xe07a048a,\n+\t0x6fa452cd,\n+\t0x2df89d30,\n+\t0xc75f1b0f,\n+\t0x8ce3578f,\n+\t0x7980a324,\n+\t0x5daec786,\n+};\n+\n+static __u32 dh_g[] = {\n+\t1,\n+\t2,\n+};\n+\n+int main(void)\n+{\n+\tint i;\n+\t__u32 *k;\n+\tk = dwc_modpow(NULL, dh_g, dh_a, dh_p);\n+\n+\tprintf(\"\\n\\n\");\n+\tfor (i=0; i<k[0]; i++) {\n+\t\t__u32 word32 = k[k[0] - i];\n+\t\t__u16 l = word32 & 0xffff;\n+\t\t__u16 m = (word32 & 0xffff0000) >> 16;\n+\t\tprintf(\"%04x %04x \", m, l);\n+\t\tif (!((i + 1)%13)) printf(\"\\n\");\n+\t}\n+\tprintf(\"\\n\\n\");\n+\n+\tif ((k[0] == 0x60) && (k[1] == 0x28e490e5) && (k[0x60] == 0x5a0d3d4e)) {\n+\t\tprintf(\"PASS\\n\\n\");\n+\t}\n+\telse {\n+\t\tprintf(\"FAIL\\n\\n\");\n+\t}\n+\n+}\n+\n+#endif /* UNITTEST */\n+\n+#endif /* CONFIG_MACH_IPMATE */\n+\n+#endif /*DWC_CRYPTOLIB */\n--- /dev/null\n+++ b/drivers/usb/host/dwc_common_port/dwc_modpow.h\n@@ -0,0 +1,34 @@\n+/*\n+ * dwc_modpow.h\n+ * See dwc_modpow.c for license and changes\n+ */\n+#ifndef _DWC_MODPOW_H\n+#define _DWC_MODPOW_H\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+#include \"dwc_os.h\"\n+\n+/** @file\n+ *\n+ * This file defines the module exponentiation function which is only used\n+ * internally by the DWC UWB modules for calculation of PKs during numeric\n+ * association.  The routine is taken from the PUTTY, an open source terminal\n+ * emulator.  The PUTTY License is preserved in the dwc_modpow.c file.\n+ *\n+ */\n+\n+typedef uint32_t BignumInt;\n+typedef uint64_t BignumDblInt;\n+typedef BignumInt *Bignum;\n+\n+/* Compute modular exponentiaion */\n+extern Bignum dwc_modpow(void *mem_ctx, Bignum base_in, Bignum exp, Bignum mod);\n+\n+#ifdef __cplusplus\n+}\n+#endif\n+\n+#endif /* _LINUX_BIGNUM_H */\n--- /dev/null\n+++ b/drivers/usb/host/dwc_common_port/dwc_notifier.c\n@@ -0,0 +1,319 @@\n+#ifdef DWC_NOTIFYLIB\n+\n+#include \"dwc_notifier.h\"\n+#include \"dwc_list.h\"\n+\n+typedef struct dwc_observer {\n+\tvoid *observer;\n+\tdwc_notifier_callback_t callback;\n+\tvoid *data;\n+\tchar *notification;\n+\tDWC_CIRCLEQ_ENTRY(dwc_observer) list_entry;\n+} observer_t;\n+\n+DWC_CIRCLEQ_HEAD(observer_queue, dwc_observer);\n+\n+typedef struct dwc_notifier {\n+\tvoid *mem_ctx;\n+\tvoid *object;\n+\tstruct observer_queue observers;\n+\tDWC_CIRCLEQ_ENTRY(dwc_notifier) list_entry;\n+} notifier_t;\n+\n+DWC_CIRCLEQ_HEAD(notifier_queue, dwc_notifier);\n+\n+typedef struct manager {\n+\tvoid *mem_ctx;\n+\tvoid *wkq_ctx;\n+\tdwc_workq_t *wq;\n+//\tdwc_mutex_t *mutex;\n+\tstruct notifier_queue notifiers;\n+} manager_t;\n+\n+static manager_t *manager = NULL;\n+\n+static int create_manager(void *mem_ctx, void *wkq_ctx)\n+{\n+\tmanager = dwc_alloc(mem_ctx, sizeof(manager_t));\n+\tif (!manager) {\n+\t\treturn -DWC_E_NO_MEMORY;\n+\t}\n+\n+\tDWC_CIRCLEQ_INIT(&manager->notifiers);\n+\n+\tmanager->wq = dwc_workq_alloc(wkq_ctx, \"DWC Notification WorkQ\");\n+\tif (!manager->wq) {\n+\t\treturn -DWC_E_NO_MEMORY;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static void free_manager(void)\n+{\n+\tdwc_workq_free(manager->wq);\n+\n+\t/* All notifiers must have unregistered themselves before this module\n+\t * can be removed.  Hitting this assertion indicates a programmer\n+\t * error. */\n+\tDWC_ASSERT(DWC_CIRCLEQ_EMPTY(&manager->notifiers),\n+\t\t   \"Notification manager being freed before all notifiers have been removed\");\n+\tdwc_free(manager->mem_ctx, manager);\n+}\n+\n+#ifdef DEBUG\n+static void dump_manager(void)\n+{\n+\tnotifier_t *n;\n+\tobserver_t *o;\n+\n+\tDWC_ASSERT(manager, \"Notification manager not found\");\n+\n+\tDWC_DEBUG(\"List of all notifiers and observers:\\n\");\n+\tDWC_CIRCLEQ_FOREACH(n, &manager->notifiers, list_entry) {\n+\t\tDWC_DEBUG(\"Notifier %p has observers:\\n\", n->object);\n+\t\tDWC_CIRCLEQ_FOREACH(o, &n->observers, list_entry) {\n+\t\t\tDWC_DEBUG(\"    %p watching %s\\n\", o->observer, o->notification);\n+\t\t}\n+\t}\n+}\n+#else\n+#define dump_manager(...)\n+#endif\n+\n+static observer_t *alloc_observer(void *mem_ctx, void *observer, char *notification,\n+\t\t\t\t  dwc_notifier_callback_t callback, void *data)\n+{\n+\tobserver_t *new_observer = dwc_alloc(mem_ctx, sizeof(observer_t));\n+\n+\tif (!new_observer) {\n+\t\treturn NULL;\n+\t}\n+\n+\tDWC_CIRCLEQ_INIT_ENTRY(new_observer, list_entry);\n+\tnew_observer->observer = observer;\n+\tnew_observer->notification = notification;\n+\tnew_observer->callback = callback;\n+\tnew_observer->data = data;\n+\treturn new_observer;\n+}\n+\n+static void free_observer(void *mem_ctx, observer_t *observer)\n+{\n+\tdwc_free(mem_ctx, observer);\n+}\n+\n+static notifier_t *alloc_notifier(void *mem_ctx, void *object)\n+{\n+\tnotifier_t *notifier;\n+\n+\tif (!object) {\n+\t\treturn NULL;\n+\t}\n+\n+\tnotifier = dwc_alloc(mem_ctx, sizeof(notifier_t));\n+\tif (!notifier) {\n+\t\treturn NULL;\n+\t}\n+\n+\tDWC_CIRCLEQ_INIT(&notifier->observers);\n+\tDWC_CIRCLEQ_INIT_ENTRY(notifier, list_entry);\n+\n+\tnotifier->mem_ctx = mem_ctx;\n+\tnotifier->object = object;\n+\treturn notifier;\n+}\n+\n+static void free_notifier(notifier_t *notifier)\n+{\n+\tobserver_t *observer;\n+\n+\tDWC_CIRCLEQ_FOREACH(observer, &notifier->observers, list_entry) {\n+\t\tfree_observer(notifier->mem_ctx, observer);\n+\t}\n+\n+\tdwc_free(notifier->mem_ctx, notifier);\n+}\n+\n+static notifier_t *find_notifier(void *object)\n+{\n+\tnotifier_t *notifier;\n+\n+\tDWC_ASSERT(manager, \"Notification manager not found\");\n+\n+\tif (!object) {\n+\t\treturn NULL;\n+\t}\n+\n+\tDWC_CIRCLEQ_FOREACH(notifier, &manager->notifiers, list_entry) {\n+\t\tif (notifier->object == object) {\n+\t\t\treturn notifier;\n+\t\t}\n+\t}\n+\n+\treturn NULL;\n+}\n+\n+int dwc_alloc_notification_manager(void *mem_ctx, void *wkq_ctx)\n+{\n+\treturn create_manager(mem_ctx, wkq_ctx);\n+}\n+\n+void dwc_free_notification_manager(void)\n+{\n+\tfree_manager();\n+}\n+\n+dwc_notifier_t *dwc_register_notifier(void *mem_ctx, void *object)\n+{\n+\tnotifier_t *notifier;\n+\n+\tDWC_ASSERT(manager, \"Notification manager not found\");\n+\n+\tnotifier = find_notifier(object);\n+\tif (notifier) {\n+\t\tDWC_ERROR(\"Notifier %p is already registered\\n\", object);\n+\t\treturn NULL;\n+\t}\n+\n+\tnotifier = alloc_notifier(mem_ctx, object);\n+\tif (!notifier) {\n+\t\treturn NULL;\n+\t}\n+\n+\tDWC_CIRCLEQ_INSERT_TAIL(&manager->notifiers, notifier, list_entry);\n+\n+\tDWC_INFO(\"Notifier %p registered\", object);\n+\tdump_manager();\n+\n+\treturn notifier;\n+}\n+\n+void dwc_unregister_notifier(dwc_notifier_t *notifier)\n+{\n+\tDWC_ASSERT(manager, \"Notification manager not found\");\n+\n+\tif (!DWC_CIRCLEQ_EMPTY(&notifier->observers)) {\n+\t\tobserver_t *o;\n+\n+\t\tDWC_ERROR(\"Notifier %p has active observers when removing\\n\", notifier->object);\n+\t\tDWC_CIRCLEQ_FOREACH(o, &notifier->observers, list_entry) {\n+\t\t\tDWC_DEBUGC(\"    %p watching %s\\n\", o->observer, o->notification);\n+\t\t}\n+\n+\t\tDWC_ASSERT(DWC_CIRCLEQ_EMPTY(&notifier->observers),\n+\t\t\t   \"Notifier %p has active observers when removing\", notifier);\n+\t}\n+\n+\tDWC_CIRCLEQ_REMOVE_INIT(&manager->notifiers, notifier, list_entry);\n+\tfree_notifier(notifier);\n+\n+\tDWC_INFO(\"Notifier unregistered\");\n+\tdump_manager();\n+}\n+\n+/* Add an observer to observe the notifier for a particular state, event, or notification. */\n+int dwc_add_observer(void *observer, void *object, char *notification,\n+\t\t     dwc_notifier_callback_t callback, void *data)\n+{\n+\tnotifier_t *notifier = find_notifier(object);\n+\tobserver_t *new_observer;\n+\n+\tif (!notifier) {\n+\t\tDWC_ERROR(\"Notifier %p is not found when adding observer\\n\", object);\n+\t\treturn -DWC_E_INVALID;\n+\t}\n+\n+\tnew_observer = alloc_observer(notifier->mem_ctx, observer, notification, callback, data);\n+\tif (!new_observer) {\n+\t\treturn -DWC_E_NO_MEMORY;\n+\t}\n+\n+\tDWC_CIRCLEQ_INSERT_TAIL(&notifier->observers, new_observer, list_entry);\n+\n+\tDWC_INFO(\"Added observer %p to notifier %p observing notification %s, callback=%p, data=%p\",\n+\t\t observer, object, notification, callback, data);\n+\n+\tdump_manager();\n+\treturn 0;\n+}\n+\n+int dwc_remove_observer(void *observer)\n+{\n+\tnotifier_t *n;\n+\n+\tDWC_ASSERT(manager, \"Notification manager not found\");\n+\n+\tDWC_CIRCLEQ_FOREACH(n, &manager->notifiers, list_entry) {\n+\t\tobserver_t *o;\n+\t\tobserver_t *o2;\n+\n+\t\tDWC_CIRCLEQ_FOREACH_SAFE(o, o2, &n->observers, list_entry) {\n+\t\t\tif (o->observer == observer) {\n+\t\t\t\tDWC_CIRCLEQ_REMOVE_INIT(&n->observers, o, list_entry);\n+\t\t\t\tDWC_INFO(\"Removing observer %p from notifier %p watching notification %s:\",\n+\t\t\t\t\t o->observer, n->object, o->notification);\n+\t\t\t\tfree_observer(n->mem_ctx, o);\n+\t\t\t}\n+\t\t}\n+\t}\n+\n+\tdump_manager();\n+\treturn 0;\n+}\n+\n+typedef struct callback_data {\n+\tvoid *mem_ctx;\n+\tdwc_notifier_callback_t cb;\n+\tvoid *observer;\n+\tvoid *data;\n+\tvoid *object;\n+\tchar *notification;\n+\tvoid *notification_data;\n+} cb_data_t;\n+\n+static void cb_task(void *data)\n+{\n+\tcb_data_t *cb = (cb_data_t *)data;\n+\n+\tcb->cb(cb->object, cb->notification, cb->observer, cb->notification_data, cb->data);\n+\tdwc_free(cb->mem_ctx, cb);\n+}\n+\n+void dwc_notify(dwc_notifier_t *notifier, char *notification, void *notification_data)\n+{\n+\tobserver_t *o;\n+\n+\tDWC_ASSERT(manager, \"Notification manager not found\");\n+\n+\tDWC_CIRCLEQ_FOREACH(o, &notifier->observers, list_entry) {\n+\t\tint len = DWC_STRLEN(notification);\n+\n+\t\tif (DWC_STRLEN(o->notification) != len) {\n+\t\t\tcontinue;\n+\t\t}\n+\n+\t\tif (DWC_STRNCMP(o->notification, notification, len) == 0) {\n+\t\t\tcb_data_t *cb_data = dwc_alloc(notifier->mem_ctx, sizeof(cb_data_t));\n+\n+\t\t\tif (!cb_data) {\n+\t\t\t\tDWC_ERROR(\"Failed to allocate callback data\\n\");\n+\t\t\t\treturn;\n+\t\t\t}\n+\n+\t\t\tcb_data->mem_ctx = notifier->mem_ctx;\n+\t\t\tcb_data->cb = o->callback;\n+\t\t\tcb_data->observer = o->observer;\n+\t\t\tcb_data->data = o->data;\n+\t\t\tcb_data->object = notifier->object;\n+\t\t\tcb_data->notification = notification;\n+\t\t\tcb_data->notification_data = notification_data;\n+\t\t\tDWC_DEBUGC(\"Observer found %p for notification %s\\n\", o->observer, notification);\n+\t\t\tDWC_WORKQ_SCHEDULE(manager->wq, cb_task, cb_data,\n+\t\t\t\t\t   \"Notify callback from %p for Notification %s, to observer %p\",\n+\t\t\t\t\t   cb_data->object, notification, cb_data->observer);\n+\t\t}\n+\t}\n+}\n+\n+#endif\t/* DWC_NOTIFYLIB */\n--- /dev/null\n+++ b/drivers/usb/host/dwc_common_port/dwc_notifier.h\n@@ -0,0 +1,122 @@\n+\n+#ifndef __DWC_NOTIFIER_H__\n+#define __DWC_NOTIFIER_H__\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+#include \"dwc_os.h\"\n+\n+/** @file\n+ *\n+ * A simple implementation of the Observer pattern.  Any \"module\" can\n+ * register as an observer or notifier.  The notion of \"module\" is abstract and\n+ * can mean anything used to identify either an observer or notifier.  Usually\n+ * it will be a pointer to a data structure which contains some state, ie an\n+ * object.\n+ *\n+ * Before any notifiers can be added, the global notification manager must be\n+ * brought up with dwc_alloc_notification_manager().\n+ * dwc_free_notification_manager() will bring it down and free all resources.\n+ * These would typically be called upon module load and unload.  The\n+ * notification manager is a single global instance that handles all registered\n+ * observable modules and observers so this should be done only once.\n+ *\n+ * A module can be observable by using Notifications to publicize some general\n+ * information about it's state or operation.  It does not care who listens, or\n+ * even if anyone listens, or what they do with the information.  The observable\n+ * modules do not need to know any information about it's observers or their\n+ * interface, or their state or data.\n+ *\n+ * Any module can register to emit Notifications.  It should publish a list of\n+ * notifications that it can emit and their behavior, such as when they will get\n+ * triggered, and what information will be provided to the observer.  Then it\n+ * should register itself as an observable module. See dwc_register_notifier().\n+ *\n+ * Any module can observe any observable, registered module, provided it has a\n+ * handle to the other module and knows what notifications to observe.  See\n+ * dwc_add_observer().\n+ *\n+ * A function of type dwc_notifier_callback_t is called whenever a notification\n+ * is triggered with one or more observers observing it.  This function is\n+ * called in it's own process so it may sleep or block if needed.  It is\n+ * guaranteed to be called sometime after the notification has occurred and will\n+ * be called once per each time the notification is triggered.  It will NOT be\n+ * called in the same process context used to trigger the notification.\n+ *\n+ * @section Limitiations\n+ *\n+ * Keep in mind that Notifications that can be triggered in rapid sucession may\n+ * schedule too many processes too handle.  Be aware of this limitation when\n+ * designing to use notifications, and only add notifications for appropriate\n+ * observable information.\n+ *\n+ * Also Notification callbacks are not synchronous.  If you need to synchronize\n+ * the behavior between module/observer you must use other means.  And perhaps\n+ * that will mean Notifications are not the proper solution.\n+ */\n+\n+struct dwc_notifier;\n+typedef struct dwc_notifier dwc_notifier_t;\n+\n+/** The callback function must be of this type.\n+ *\n+ * @param object This is the object that is being observed.\n+ * @param notification This is the notification that was triggered.\n+ * @param observer This is the observer\n+ * @param notification_data This is notification-specific data that the notifier\n+ * has included in this notification.  The value of this should be published in\n+ * the documentation of the observable module with the notifications.\n+ * @param user_data This is any custom data that the observer provided when\n+ * adding itself as an observer to the notification. */\n+typedef void (*dwc_notifier_callback_t)(void *object, char *notification, void *observer,\n+\t\t\t\t\tvoid *notification_data, void *user_data);\n+\n+/** Brings up the notification manager. */\n+extern int dwc_alloc_notification_manager(void *mem_ctx, void *wkq_ctx);\n+/** Brings down the notification manager. */\n+extern void dwc_free_notification_manager(void);\n+\n+/** This function registers an observable module.  A dwc_notifier_t object is\n+ * returned to the observable module.  This is an opaque object that is used by\n+ * the observable module to trigger notifications.  This object should only be\n+ * accessible to functions that are authorized to trigger notifications for this\n+ * module.  Observers do not need this object. */\n+extern dwc_notifier_t *dwc_register_notifier(void *mem_ctx, void *object);\n+\n+/** This function unregisters an observable module.  All observers have to be\n+ * removed prior to unregistration. */\n+extern void dwc_unregister_notifier(dwc_notifier_t *notifier);\n+\n+/** Add a module as an observer to the observable module.  The observable module\n+ * needs to have previously registered with the notification manager.\n+ *\n+ * @param observer The observer module\n+ * @param object The module to observe\n+ * @param notification The notification to observe\n+ * @param callback The callback function to call\n+ * @param user_data Any additional user data to pass into the callback function */\n+extern int dwc_add_observer(void *observer, void *object, char *notification,\n+\t\t\t    dwc_notifier_callback_t callback, void *user_data);\n+\n+/** Removes the specified observer from all notifications that it is currently\n+ * observing. */\n+extern int dwc_remove_observer(void *observer);\n+\n+/** This function triggers a Notification.  It should be called by the\n+ * observable module, or any module or library which the observable module\n+ * allows to trigger notification on it's behalf.  Such as the dwc_cc_t.\n+ *\n+ * dwc_notify is a non-blocking function.  Callbacks are scheduled called in\n+ * their own process context for each trigger.  Callbacks can be blocking.\n+ * dwc_notify can be called from interrupt context if needed.\n+ *\n+ */\n+void dwc_notify(dwc_notifier_t *notifier, char *notification, void *notification_data);\n+\n+#ifdef __cplusplus\n+}\n+#endif\n+\n+#endif /* __DWC_NOTIFIER_H__ */\n--- /dev/null\n+++ b/drivers/usb/host/dwc_common_port/dwc_os.h\n@@ -0,0 +1,1276 @@\n+/* =========================================================================\n+ * $File: //dwh/usb_iip/dev/software/dwc_common_port_2/dwc_os.h $\n+ * $Revision: #14 $\n+ * $Date: 2010/11/04 $\n+ * $Change: 1621695 $\n+ *\n+ * Synopsys Portability Library Software and documentation\n+ * (hereinafter, \"Software\") is an Unsupported proprietary work of\n+ * Synopsys, Inc. unless otherwise expressly agreed to in writing\n+ * between Synopsys and you.\n+ *\n+ * The Software IS NOT an item of Licensed Software or Licensed Product\n+ * under any End User Software License Agreement or Agreement for\n+ * Licensed Product with Synopsys or any supplement thereto. You are\n+ * permitted to use and redistribute this Software in source and binary\n+ * forms, with or without modification, provided that redistributions\n+ * of source code must retain this notice. You may not view, use,\n+ * disclose, copy or distribute this file or any information contained\n+ * herein except pursuant to this license grant from Synopsys. If you\n+ * do not agree with this notice, including the disclaimer below, then\n+ * you are not authorized to use the Software.\n+ *\n+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN \"AS IS\"\n+ * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n+ * FOR A PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL\n+ * SYNOPSYS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\n+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\n+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR\n+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY\n+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE\n+ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH\n+ * DAMAGE.\n+ * ========================================================================= */\n+#ifndef _DWC_OS_H_\n+#define _DWC_OS_H_\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+/** @file\n+ *\n+ * DWC portability library, low level os-wrapper functions\n+ *\n+ */\n+\n+/* These basic types need to be defined by some OS header file or custom header\n+ * file for your specific target architecture.\n+ *\n+ * uint8_t, int8_t, uint16_t, int16_t, uint32_t, int32_t, uint64_t, int64_t\n+ *\n+ * Any custom or alternate header file must be added and enabled here.\n+ */\n+\n+#ifdef DWC_LINUX\n+# include <linux/types.h>\n+# ifdef CONFIG_DEBUG_MUTEXES\n+#  include <linux/mutex.h>\n+# endif\n+# include <linux/spinlock.h>\n+# include <linux/errno.h>\n+# include <stdarg.h>\n+#endif\n+\n+#if defined(DWC_FREEBSD) || defined(DWC_NETBSD)\n+# include <os_dep.h>\n+#endif\n+\n+\n+/** @name Primitive Types and Values */\n+\n+/** We define a boolean type for consistency.  Can be either YES or NO */\n+typedef uint8_t dwc_bool_t;\n+#define YES  1\n+#define NO   0\n+\n+#ifdef DWC_LINUX\n+\n+/** @name Error Codes */\n+#define DWC_E_INVALID\t\tEINVAL\n+#define DWC_E_NO_MEMORY\t\tENOMEM\n+#define DWC_E_NO_DEVICE\t\tENODEV\n+#define DWC_E_NOT_SUPPORTED\tEOPNOTSUPP\n+#define DWC_E_TIMEOUT\t\tETIMEDOUT\n+#define DWC_E_BUSY\t\tEBUSY\n+#define DWC_E_AGAIN\t\tEAGAIN\n+#define DWC_E_RESTART\t\tERESTART\n+#define DWC_E_ABORT\t\tECONNABORTED\n+#define DWC_E_SHUTDOWN\t\tESHUTDOWN\n+#define DWC_E_NO_DATA\t\tENODATA\n+#define DWC_E_DISCONNECT\tECONNRESET\n+#define DWC_E_UNKNOWN\t\tEINVAL\n+#define DWC_E_NO_STREAM_RES\tENOSR\n+#define DWC_E_COMMUNICATION\tECOMM\n+#define DWC_E_OVERFLOW\t\tEOVERFLOW\n+#define DWC_E_PROTOCOL\t\tEPROTO\n+#define DWC_E_IN_PROGRESS\tEINPROGRESS\n+#define DWC_E_PIPE\t\tEPIPE\n+#define DWC_E_IO\t\tEIO\n+#define DWC_E_NO_SPACE\t\tENOSPC\n+\n+#else\n+\n+/** @name Error Codes */\n+#define DWC_E_INVALID\t\t1001\n+#define DWC_E_NO_MEMORY\t\t1002\n+#define DWC_E_NO_DEVICE\t\t1003\n+#define DWC_E_NOT_SUPPORTED\t1004\n+#define DWC_E_TIMEOUT\t\t1005\n+#define DWC_E_BUSY\t\t1006\n+#define DWC_E_AGAIN\t\t1007\n+#define DWC_E_RESTART\t\t1008\n+#define DWC_E_ABORT\t\t1009\n+#define DWC_E_SHUTDOWN\t\t1010\n+#define DWC_E_NO_DATA\t\t1011\n+#define DWC_E_DISCONNECT\t2000\n+#define DWC_E_UNKNOWN\t\t3000\n+#define DWC_E_NO_STREAM_RES\t4001\n+#define DWC_E_COMMUNICATION\t4002\n+#define DWC_E_OVERFLOW\t\t4003\n+#define DWC_E_PROTOCOL\t\t4004\n+#define DWC_E_IN_PROGRESS\t4005\n+#define DWC_E_PIPE\t\t4006\n+#define DWC_E_IO\t\t4007\n+#define DWC_E_NO_SPACE\t\t4008\n+\n+#endif\n+\n+\n+/** @name Tracing/Logging Functions\n+ *\n+ * These function provide the capability to add tracing, debugging, and error\n+ * messages, as well exceptions as assertions.  The WUDEV uses these\n+ * extensively.  These could be logged to the main console, the serial port, an\n+ * internal buffer, etc.  These functions could also be no-op if they are too\n+ * expensive on your system.  By default undefining the DEBUG macro already\n+ * no-ops some of these functions. */\n+\n+/** Returns non-zero if in interrupt context. */\n+extern dwc_bool_t DWC_IN_IRQ(void);\n+#define dwc_in_irq DWC_IN_IRQ\n+\n+/** Returns \"IRQ\" if DWC_IN_IRQ is true. */\n+static inline char *dwc_irq(void) {\n+\treturn DWC_IN_IRQ() ? \"IRQ\" : \"\";\n+}\n+\n+/** Returns non-zero if in bottom-half context. */\n+extern dwc_bool_t DWC_IN_BH(void);\n+#define dwc_in_bh DWC_IN_BH\n+\n+/** Returns \"BH\" if DWC_IN_BH is true. */\n+static inline char *dwc_bh(void) {\n+\treturn DWC_IN_BH() ? \"BH\" : \"\";\n+}\n+\n+/**\n+ * A vprintf() clone.  Just call vprintf if you've got it.\n+ */\n+extern void DWC_VPRINTF(char *format, va_list args);\n+#define dwc_vprintf DWC_VPRINTF\n+\n+/**\n+ * A vsnprintf() clone.  Just call vprintf if you've got it.\n+ */\n+extern int DWC_VSNPRINTF(char *str, int size, char *format, va_list args);\n+#define dwc_vsnprintf DWC_VSNPRINTF\n+\n+/**\n+ * printf() clone.  Just call printf if you've go it.\n+ */\n+extern void DWC_PRINTF(char *format, ...)\n+/* This provides compiler level static checking of the parameters if you're\n+ * using GCC. */\n+#ifdef __GNUC__\n+\t__attribute__ ((format(printf, 1, 2)));\n+#else\n+\t;\n+#endif\n+#define dwc_printf DWC_PRINTF\n+\n+/**\n+ * sprintf() clone.  Just call sprintf if you've got it.\n+ */\n+extern int DWC_SPRINTF(char *string, char *format, ...)\n+#ifdef __GNUC__\n+\t__attribute__ ((format(printf, 2, 3)));\n+#else\n+\t;\n+#endif\n+#define dwc_sprintf DWC_SPRINTF\n+\n+/**\n+ * snprintf() clone.  Just call snprintf if you've got it.\n+ */\n+extern int DWC_SNPRINTF(char *string, int size, char *format, ...)\n+#ifdef __GNUC__\n+\t__attribute__ ((format(printf, 3, 4)));\n+#else\n+\t;\n+#endif\n+#define dwc_snprintf DWC_SNPRINTF\n+\n+/**\n+ * Prints a WARNING message.  On systems that don't differentiate between\n+ * warnings and regular log messages, just print it.  Indicates that something\n+ * may be wrong with the driver.  Works like printf().\n+ *\n+ * Use the DWC_WARN macro to call this function.\n+ */\n+extern void __DWC_WARN(char *format, ...)\n+#ifdef __GNUC__\n+\t__attribute__ ((format(printf, 1, 2)));\n+#else\n+\t;\n+#endif\n+\n+/**\n+ * Prints an error message.  On systems that don't differentiate between errors\n+ * and regular log messages, just print it.  Indicates that something went wrong\n+ * with the driver.  Works like printf().\n+ *\n+ * Use the DWC_ERROR macro to call this function.\n+ */\n+extern void __DWC_ERROR(char *format, ...)\n+#ifdef __GNUC__\n+\t__attribute__ ((format(printf, 1, 2)));\n+#else\n+\t;\n+#endif\n+\n+/**\n+ * Prints an exception error message and takes some user-defined action such as\n+ * print out a backtrace or trigger a breakpoint.  Indicates that something went\n+ * abnormally wrong with the driver such as programmer error, or other\n+ * exceptional condition.  It should not be ignored so even on systems without\n+ * printing capability, some action should be taken to notify the developer of\n+ * it.  Works like printf().\n+ */\n+extern void DWC_EXCEPTION(char *format, ...)\n+#ifdef __GNUC__\n+\t__attribute__ ((format(printf, 1, 2)));\n+#else\n+\t;\n+#endif\n+#define dwc_exception DWC_EXCEPTION\n+\n+#ifndef DWC_OTG_DEBUG_LEV\n+#define DWC_OTG_DEBUG_LEV 0\n+#endif\n+\n+#ifdef DEBUG\n+/**\n+ * Prints out a debug message.  Used for logging/trace messages.\n+ *\n+ * Use the DWC_DEBUG macro to call this function\n+ */\n+extern void __DWC_DEBUG(char *format, ...)\n+#ifdef __GNUC__\n+\t__attribute__ ((format(printf, 1, 2)));\n+#else\n+\t;\n+#endif\n+#else\n+#define __DWC_DEBUG printk\n+#endif\n+\n+/**\n+ * Prints out a Debug message.\n+ */\n+#define DWC_DEBUG(_format, _args...) __DWC_DEBUG(\"DEBUG:%s:%s: \" _format \"\\n\", \\\n+\t\t\t\t\t\t __func__, dwc_irq(), ## _args)\n+#define dwc_debug DWC_DEBUG\n+/**\n+ * Prints out a Debug message if enabled at compile time.\n+ */\n+#if DWC_OTG_DEBUG_LEV > 0\n+#define DWC_DEBUGC(_format, _args...) DWC_DEBUG(_format, ##_args )\n+#else\n+#define DWC_DEBUGC(_format, _args...)\n+#endif\n+#define dwc_debugc DWC_DEBUGC\n+/**\n+ * Prints out an informative message.\n+ */\n+#define DWC_INFO(_format, _args...) DWC_PRINTF(\"INFO:%s: \" _format \"\\n\", \\\n+\t\t\t\t\t       dwc_irq(), ## _args)\n+#define dwc_info DWC_INFO\n+/**\n+ * Prints out an informative message if enabled at compile time.\n+ */\n+#if DWC_OTG_DEBUG_LEV > 1\n+#define DWC_INFOC(_format, _args...) DWC_INFO(_format, ##_args )\n+#else\n+#define DWC_INFOC(_format, _args...)\n+#endif\n+#define dwc_infoc DWC_INFOC\n+/**\n+ * Prints out a warning message.\n+ */\n+#define DWC_WARN(_format, _args...) __DWC_WARN(\"WARN:%s:%s:%d: \" _format \"\\n\", \\\n+\t\t\t\t\tdwc_irq(), __func__, __LINE__, ## _args)\n+#define dwc_warn DWC_WARN\n+/**\n+ * Prints out an error message.\n+ */\n+#define DWC_ERROR(_format, _args...) __DWC_ERROR(\"ERROR:%s:%s:%d: \" _format \"\\n\", \\\n+\t\t\t\t\tdwc_irq(), __func__, __LINE__, ## _args)\n+#define dwc_error DWC_ERROR\n+\n+#define DWC_PROTO_ERROR(_format, _args...) __DWC_WARN(\"ERROR:%s:%s:%d: \" _format \"\\n\", \\\n+\t\t\t\t\t\tdwc_irq(), __func__, __LINE__, ## _args)\n+#define dwc_proto_error DWC_PROTO_ERROR\n+\n+#ifdef DEBUG\n+/** Prints out a exception error message if the _expr expression fails.  Disabled\n+ * if DEBUG is not enabled. */\n+#define DWC_ASSERT(_expr, _format, _args...) do { \\\n+\tif (!(_expr)) { DWC_EXCEPTION(\"%s:%s:%d: \" _format \"\\n\", dwc_irq(), \\\n+\t\t\t\t      __FILE__, __LINE__, ## _args); } \\\n+\t} while (0)\n+#else\n+#define DWC_ASSERT(_x...)\n+#endif\n+#define dwc_assert DWC_ASSERT\n+\n+\n+/** @name Byte Ordering\n+ * The following functions are for conversions between processor's byte ordering\n+ * and specific ordering you want.\n+ */\n+\n+/** Converts 32 bit data in CPU byte ordering to little endian. */\n+extern uint32_t DWC_CPU_TO_LE32(uint32_t *p);\n+#define dwc_cpu_to_le32 DWC_CPU_TO_LE32\n+\n+/** Converts 32 bit data in CPU byte orderint to big endian. */\n+extern uint32_t DWC_CPU_TO_BE32(uint32_t *p);\n+#define dwc_cpu_to_be32 DWC_CPU_TO_BE32\n+\n+/** Converts 32 bit little endian data to CPU byte ordering. */\n+extern uint32_t DWC_LE32_TO_CPU(uint32_t *p);\n+#define dwc_le32_to_cpu DWC_LE32_TO_CPU\n+\n+/** Converts 32 bit big endian data to CPU byte ordering. */\n+extern uint32_t DWC_BE32_TO_CPU(uint32_t *p);\n+#define dwc_be32_to_cpu DWC_BE32_TO_CPU\n+\n+/** Converts 16 bit data in CPU byte ordering to little endian. */\n+extern uint16_t DWC_CPU_TO_LE16(uint16_t *p);\n+#define dwc_cpu_to_le16 DWC_CPU_TO_LE16\n+\n+/** Converts 16 bit data in CPU byte orderint to big endian. */\n+extern uint16_t DWC_CPU_TO_BE16(uint16_t *p);\n+#define dwc_cpu_to_be16 DWC_CPU_TO_BE16\n+\n+/** Converts 16 bit little endian data to CPU byte ordering. */\n+extern uint16_t DWC_LE16_TO_CPU(uint16_t *p);\n+#define dwc_le16_to_cpu DWC_LE16_TO_CPU\n+\n+/** Converts 16 bit bi endian data to CPU byte ordering. */\n+extern uint16_t DWC_BE16_TO_CPU(uint16_t *p);\n+#define dwc_be16_to_cpu DWC_BE16_TO_CPU\n+\n+\n+/** @name Register Read/Write\n+ *\n+ * The following six functions should be implemented to read/write registers of\n+ * 32-bit and 64-bit sizes.  All modules use this to read/write register values.\n+ * The reg value is a pointer to the register calculated from the void *base\n+ * variable passed into the driver when it is started.  */\n+\n+#ifdef DWC_LINUX\n+/* Linux doesn't need any extra parameters for register read/write, so we\n+ * just throw away the IO context parameter.\n+ */\n+/** Reads the content of a 32-bit register. */\n+extern uint32_t DWC_READ_REG32(uint32_t volatile *reg);\n+#define dwc_read_reg32(_ctx_,_reg_) DWC_READ_REG32(_reg_)\n+\n+/** Reads the content of a 64-bit register. */\n+extern uint64_t DWC_READ_REG64(uint64_t volatile *reg);\n+#define dwc_read_reg64(_ctx_,_reg_) DWC_READ_REG64(_reg_)\n+\n+/** Writes to a 32-bit register. */\n+extern void DWC_WRITE_REG32(uint32_t volatile *reg, uint32_t value);\n+#define dwc_write_reg32(_ctx_,_reg_,_val_) DWC_WRITE_REG32(_reg_, _val_)\n+\n+/** Writes to a 64-bit register. */\n+extern void DWC_WRITE_REG64(uint64_t volatile *reg, uint64_t value);\n+#define dwc_write_reg64(_ctx_,_reg_,_val_) DWC_WRITE_REG64(_reg_, _val_)\n+\n+/**\n+ * Modify bit values in a register.  Using the\n+ * algorithm: (reg_contents & ~clear_mask) | set_mask.\n+ */\n+extern void DWC_MODIFY_REG32(uint32_t volatile *reg, uint32_t clear_mask, uint32_t set_mask);\n+#define dwc_modify_reg32(_ctx_,_reg_,_cmsk_,_smsk_) DWC_MODIFY_REG32(_reg_,_cmsk_,_smsk_)\n+extern void DWC_MODIFY_REG64(uint64_t volatile *reg, uint64_t clear_mask, uint64_t set_mask);\n+#define dwc_modify_reg64(_ctx_,_reg_,_cmsk_,_smsk_) DWC_MODIFY_REG64(_reg_,_cmsk_,_smsk_)\n+\n+#endif\t/* DWC_LINUX */\n+\n+#if defined(DWC_FREEBSD) || defined(DWC_NETBSD)\n+typedef struct dwc_ioctx {\n+\tstruct device *dev;\n+\tbus_space_tag_t iot;\n+\tbus_space_handle_t ioh;\n+} dwc_ioctx_t;\n+\n+/** BSD needs two extra parameters for register read/write, so we pass\n+ * them in using the IO context parameter.\n+ */\n+/** Reads the content of a 32-bit register. */\n+extern uint32_t DWC_READ_REG32(void *io_ctx, uint32_t volatile *reg);\n+#define dwc_read_reg32 DWC_READ_REG32\n+\n+/** Reads the content of a 64-bit register. */\n+extern uint64_t DWC_READ_REG64(void *io_ctx, uint64_t volatile *reg);\n+#define dwc_read_reg64 DWC_READ_REG64\n+\n+/** Writes to a 32-bit register. */\n+extern void DWC_WRITE_REG32(void *io_ctx, uint32_t volatile *reg, uint32_t value);\n+#define dwc_write_reg32 DWC_WRITE_REG32\n+\n+/** Writes to a 64-bit register. */\n+extern void DWC_WRITE_REG64(void *io_ctx, uint64_t volatile *reg, uint64_t value);\n+#define dwc_write_reg64 DWC_WRITE_REG64\n+\n+/**\n+ * Modify bit values in a register.  Using the\n+ * algorithm: (reg_contents & ~clear_mask) | set_mask.\n+ */\n+extern void DWC_MODIFY_REG32(void *io_ctx, uint32_t volatile *reg, uint32_t clear_mask, uint32_t set_mask);\n+#define dwc_modify_reg32 DWC_MODIFY_REG32\n+extern void DWC_MODIFY_REG64(void *io_ctx, uint64_t volatile *reg, uint64_t clear_mask, uint64_t set_mask);\n+#define dwc_modify_reg64 DWC_MODIFY_REG64\n+\n+#endif\t/* DWC_FREEBSD || DWC_NETBSD */\n+\n+/** @cond */\n+\n+/** @name Some convenience MACROS used internally.  Define DWC_DEBUG_REGS to log the\n+ * register writes. */\n+\n+#ifdef DWC_LINUX\n+\n+# ifdef DWC_DEBUG_REGS\n+\n+#define dwc_define_read_write_reg_n(_reg,_container_type) \\\n+static inline uint32_t dwc_read_##_reg##_n(_container_type *container, int num) { \\\n+\treturn DWC_READ_REG32(&container->regs->_reg[num]); \\\n+} \\\n+static inline void dwc_write_##_reg##_n(_container_type *container, int num, uint32_t data) { \\\n+\tDWC_DEBUG(\"WRITING %8s[%d]: %p: %08x\", #_reg, num, \\\n+\t\t  &(((uint32_t*)container->regs->_reg)[num]), data); \\\n+\tDWC_WRITE_REG32(&(((uint32_t*)container->regs->_reg)[num]), data); \\\n+}\n+\n+#define dwc_define_read_write_reg(_reg,_container_type) \\\n+static inline uint32_t dwc_read_##_reg(_container_type *container) { \\\n+\treturn DWC_READ_REG32(&container->regs->_reg); \\\n+} \\\n+static inline void dwc_write_##_reg(_container_type *container, uint32_t data) { \\\n+\tDWC_DEBUG(\"WRITING %11s: %p: %08x\", #_reg, &container->regs->_reg, data); \\\n+\tDWC_WRITE_REG32(&container->regs->_reg, data); \\\n+}\n+\n+# else\t/* DWC_DEBUG_REGS */\n+\n+#define dwc_define_read_write_reg_n(_reg,_container_type) \\\n+static inline uint32_t dwc_read_##_reg##_n(_container_type *container, int num) { \\\n+\treturn DWC_READ_REG32(&container->regs->_reg[num]); \\\n+} \\\n+static inline void dwc_write_##_reg##_n(_container_type *container, int num, uint32_t data) { \\\n+\tDWC_WRITE_REG32(&(((uint32_t*)container->regs->_reg)[num]), data); \\\n+}\n+\n+#define dwc_define_read_write_reg(_reg,_container_type) \\\n+static inline uint32_t dwc_read_##_reg(_container_type *container) { \\\n+\treturn DWC_READ_REG32(&container->regs->_reg); \\\n+} \\\n+static inline void dwc_write_##_reg(_container_type *container, uint32_t data) { \\\n+\tDWC_WRITE_REG32(&container->regs->_reg, data); \\\n+}\n+\n+# endif\t/* DWC_DEBUG_REGS */\n+\n+#endif\t/* DWC_LINUX */\n+\n+#if defined(DWC_FREEBSD) || defined(DWC_NETBSD)\n+\n+# ifdef DWC_DEBUG_REGS\n+\n+#define dwc_define_read_write_reg_n(_reg,_container_type) \\\n+static inline uint32_t dwc_read_##_reg##_n(void *io_ctx, _container_type *container, int num) { \\\n+\treturn DWC_READ_REG32(io_ctx, &container->regs->_reg[num]); \\\n+} \\\n+static inline void dwc_write_##_reg##_n(void *io_ctx, _container_type *container, int num, uint32_t data) { \\\n+\tDWC_DEBUG(\"WRITING %8s[%d]: %p: %08x\", #_reg, num, \\\n+\t\t  &(((uint32_t*)container->regs->_reg)[num]), data); \\\n+\tDWC_WRITE_REG32(io_ctx, &(((uint32_t*)container->regs->_reg)[num]), data); \\\n+}\n+\n+#define dwc_define_read_write_reg(_reg,_container_type) \\\n+static inline uint32_t dwc_read_##_reg(void *io_ctx, _container_type *container) { \\\n+\treturn DWC_READ_REG32(io_ctx, &container->regs->_reg); \\\n+} \\\n+static inline void dwc_write_##_reg(void *io_ctx, _container_type *container, uint32_t data) { \\\n+\tDWC_DEBUG(\"WRITING %11s: %p: %08x\", #_reg, &container->regs->_reg, data); \\\n+\tDWC_WRITE_REG32(io_ctx, &container->regs->_reg, data); \\\n+}\n+\n+# else\t/* DWC_DEBUG_REGS */\n+\n+#define dwc_define_read_write_reg_n(_reg,_container_type) \\\n+static inline uint32_t dwc_read_##_reg##_n(void *io_ctx, _container_type *container, int num) { \\\n+\treturn DWC_READ_REG32(io_ctx, &container->regs->_reg[num]); \\\n+} \\\n+static inline void dwc_write_##_reg##_n(void *io_ctx, _container_type *container, int num, uint32_t data) { \\\n+\tDWC_WRITE_REG32(io_ctx, &(((uint32_t*)container->regs->_reg)[num]), data); \\\n+}\n+\n+#define dwc_define_read_write_reg(_reg,_container_type) \\\n+static inline uint32_t dwc_read_##_reg(void *io_ctx, _container_type *container) { \\\n+\treturn DWC_READ_REG32(io_ctx, &container->regs->_reg); \\\n+} \\\n+static inline void dwc_write_##_reg(void *io_ctx, _container_type *container, uint32_t data) { \\\n+\tDWC_WRITE_REG32(io_ctx, &container->regs->_reg, data); \\\n+}\n+\n+# endif\t/* DWC_DEBUG_REGS */\n+\n+#endif\t/* DWC_FREEBSD || DWC_NETBSD */\n+\n+/** @endcond */\n+\n+\n+#ifdef DWC_CRYPTOLIB\n+/** @name Crypto Functions\n+ *\n+ * These are the low-level cryptographic functions used by the driver. */\n+\n+/** Perform AES CBC */\n+extern int DWC_AES_CBC(uint8_t *message, uint32_t messagelen, uint8_t *key, uint32_t keylen, uint8_t iv[16], uint8_t *out);\n+#define dwc_aes_cbc DWC_AES_CBC\n+\n+/** Fill the provided buffer with random bytes.  These should be cryptographic grade random numbers. */\n+extern void DWC_RANDOM_BYTES(uint8_t *buffer, uint32_t length);\n+#define dwc_random_bytes DWC_RANDOM_BYTES\n+\n+/** Perform the SHA-256 hash function */\n+extern int DWC_SHA256(uint8_t *message, uint32_t len, uint8_t *out);\n+#define dwc_sha256 DWC_SHA256\n+\n+/** Calculated the HMAC-SHA256 */\n+extern int DWC_HMAC_SHA256(uint8_t *message, uint32_t messagelen, uint8_t *key, uint32_t keylen, uint8_t *out);\n+#define dwc_hmac_sha256 DWC_HMAC_SHA256\n+\n+#endif\t/* DWC_CRYPTOLIB */\n+\n+\n+/** @name Memory Allocation\n+ *\n+ * These function provide access to memory allocation.  There are only 2 DMA\n+ * functions and 3 Regular memory functions that need to be implemented.  None\n+ * of the memory debugging routines need to be implemented.  The allocation\n+ * routines all ZERO the contents of the memory.\n+ *\n+ * Defining DWC_DEBUG_MEMORY turns on memory debugging and statistic gathering.\n+ * This checks for memory leaks, keeping track of alloc/free pairs.  It also\n+ * keeps track of how much memory the driver is using at any given time. */\n+\n+#define DWC_PAGE_SIZE 4096\n+#define DWC_PAGE_OFFSET(addr) (((uint32_t)addr) & 0xfff)\n+#define DWC_PAGE_ALIGNED(addr) ((((uint32_t)addr) & 0xfff) == 0)\n+\n+#define DWC_INVALID_DMA_ADDR 0x0\n+\n+#ifdef DWC_LINUX\n+/** Type for a DMA address */\n+typedef dma_addr_t dwc_dma_t;\n+#endif\n+\n+#if defined(DWC_FREEBSD) || defined(DWC_NETBSD)\n+typedef bus_addr_t dwc_dma_t;\n+#endif\n+\n+#ifdef DWC_FREEBSD\n+typedef struct dwc_dmactx {\n+\tstruct device *dev;\n+\tbus_dma_tag_t dma_tag;\n+\tbus_dmamap_t dma_map;\n+\tbus_addr_t dma_paddr;\n+\tvoid *dma_vaddr;\n+} dwc_dmactx_t;\n+#endif\n+\n+#ifdef DWC_NETBSD\n+typedef struct dwc_dmactx {\n+\tstruct device *dev;\n+\tbus_dma_tag_t dma_tag;\n+\tbus_dmamap_t dma_map;\n+\tbus_dma_segment_t segs[1];\n+\tint nsegs;\n+\tbus_addr_t dma_paddr;\n+\tvoid *dma_vaddr;\n+} dwc_dmactx_t;\n+#endif\n+\n+/* @todo these functions will be added in the future */\n+#if 0\n+/**\n+ * Creates a DMA pool from which you can allocate DMA buffers.  Buffers\n+ * allocated from this pool will be guaranteed to meet the size, alignment, and\n+ * boundary requirements specified.\n+ *\n+ * @param[in] size Specifies the size of the buffers that will be allocated from\n+ * this pool.\n+ * @param[in] align Specifies the byte alignment requirements of the buffers\n+ * allocated from this pool.  Must be a power of 2.\n+ * @param[in] boundary Specifies the N-byte boundary that buffers allocated from\n+ * this pool must not cross.\n+ *\n+ * @returns A pointer to an internal opaque structure which is not to be\n+ * accessed outside of these library functions.  Use this handle to specify\n+ * which pools to allocate/free DMA buffers from and also to destroy the pool,\n+ * when you are done with it.\n+ */\n+extern dwc_pool_t *DWC_DMA_POOL_CREATE(uint32_t size, uint32_t align, uint32_t boundary);\n+\n+/**\n+ * Destroy a DMA pool.  All buffers allocated from that pool must be freed first.\n+ */\n+extern void DWC_DMA_POOL_DESTROY(dwc_pool_t *pool);\n+\n+/**\n+ * Allocate a buffer from the specified DMA pool and zeros its contents.\n+ */\n+extern void *DWC_DMA_POOL_ALLOC(dwc_pool_t *pool, uint64_t *dma_addr);\n+\n+/**\n+ * Free a previously allocated buffer from the DMA pool.\n+ */\n+extern void DWC_DMA_POOL_FREE(dwc_pool_t *pool, void *vaddr, void *daddr);\n+#endif\n+\n+/** Allocates a DMA capable buffer and zeroes its contents. */\n+extern void *__DWC_DMA_ALLOC(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr);\n+\n+/** Allocates a DMA capable buffer and zeroes its contents in atomic contest */\n+extern void *__DWC_DMA_ALLOC_ATOMIC(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr);\n+\n+/** Frees a previously allocated buffer. */\n+extern void __DWC_DMA_FREE(void *dma_ctx, uint32_t size, void *virt_addr, dwc_dma_t dma_addr);\n+\n+/** Allocates a block of memory and zeroes its contents. */\n+extern void *__DWC_ALLOC(void *mem_ctx, uint32_t size);\n+\n+/** Allocates a block of memory and zeroes its contents, in an atomic manner\n+ * which can be used inside interrupt context.  The size should be sufficiently\n+ * small, a few KB at most, such that failures are not likely to occur.  Can just call\n+ * __DWC_ALLOC if it is atomic. */\n+extern void *__DWC_ALLOC_ATOMIC(void *mem_ctx, uint32_t size);\n+\n+/** Frees a previously allocated buffer. */\n+extern void __DWC_FREE(void *mem_ctx, void *addr);\n+\n+#ifndef DWC_DEBUG_MEMORY\n+\n+#define DWC_ALLOC(_size_) __DWC_ALLOC(NULL, _size_)\n+#define DWC_ALLOC_ATOMIC(_size_) __DWC_ALLOC_ATOMIC(NULL, _size_)\n+#define DWC_FREE(_addr_) __DWC_FREE(NULL, _addr_)\n+\n+# ifdef DWC_LINUX\n+#define DWC_DMA_ALLOC(_dev, _size_, _dma_) __DWC_DMA_ALLOC(_dev, _size_, _dma_)\n+#define DWC_DMA_ALLOC_ATOMIC(_dev, _size_, _dma_) __DWC_DMA_ALLOC_ATOMIC(_dev, _size_, _dma_)\n+#define DWC_DMA_FREE(_dev, _size_,_virt_, _dma_) __DWC_DMA_FREE(_dev, _size_, _virt_, _dma_)\n+# endif\n+\n+# if defined(DWC_FREEBSD) || defined(DWC_NETBSD)\n+#define DWC_DMA_ALLOC __DWC_DMA_ALLOC\n+#define DWC_DMA_FREE __DWC_DMA_FREE\n+# endif\n+extern void *dwc_dma_alloc_atomic_debug(uint32_t size, dwc_dma_t *dma_addr, char const *func, int line);\n+\n+#else\t/* DWC_DEBUG_MEMORY */\n+\n+extern void *dwc_alloc_debug(void *mem_ctx, uint32_t size, char const *func, int line);\n+extern void *dwc_alloc_atomic_debug(void *mem_ctx, uint32_t size, char const *func, int line);\n+extern void dwc_free_debug(void *mem_ctx, void *addr, char const *func, int line);\n+extern void *dwc_dma_alloc_debug(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr,\n+\t\t\t\t char const *func, int line);\n+extern void *dwc_dma_alloc_atomic_debug(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr,\n+\t\t\t\tchar const *func, int line);\n+extern void dwc_dma_free_debug(void *dma_ctx, uint32_t size, void *virt_addr,\n+\t\t\t       dwc_dma_t dma_addr, char const *func, int line);\n+\n+extern int dwc_memory_debug_start(void *mem_ctx);\n+extern void dwc_memory_debug_stop(void);\n+extern void dwc_memory_debug_report(void);\n+\n+#define DWC_ALLOC(_size_) dwc_alloc_debug(NULL, _size_, __func__, __LINE__)\n+#define DWC_ALLOC_ATOMIC(_size_) dwc_alloc_atomic_debug(NULL, _size_, \\\n+\t\t\t\t\t\t\t__func__, __LINE__)\n+#define DWC_FREE(_addr_) dwc_free_debug(NULL, _addr_, __func__, __LINE__)\n+\n+# ifdef DWC_LINUX\n+#define DWC_DMA_ALLOC(_dev, _size_, _dma_) \\\n+\tdwc_dma_alloc_debug(_dev, _size_, _dma_, __func__, __LINE__)\n+#define DWC_DMA_ALLOC_ATOMIC(_dev, _size_, _dma_) \\\n+\tdwc_dma_alloc_atomic_debug(_dev, _size_, _dma_, __func__, __LINE__)\n+#define DWC_DMA_FREE(_dev, _size_, _virt_, _dma_) \\\n+\tdwc_dma_free_debug(_dev, _size_, _virt_, _dma_, __func__, __LINE__)\n+# endif\n+\n+# if defined(DWC_FREEBSD) || defined(DWC_NETBSD)\n+#define DWC_DMA_ALLOC(_ctx_,_size_,_dma_) dwc_dma_alloc_debug(_ctx_, _size_, \\\n+\t\t\t\t\t\t_dma_, __func__, __LINE__)\n+#define DWC_DMA_FREE(_ctx_,_size_,_virt_,_dma_) dwc_dma_free_debug(_ctx_, _size_, \\\n+\t\t\t\t\t\t _virt_, _dma_, __func__, __LINE__)\n+# endif\n+\n+#endif /* DWC_DEBUG_MEMORY */\n+\n+#define dwc_alloc(_ctx_,_size_) DWC_ALLOC(_size_)\n+#define dwc_alloc_atomic(_ctx_,_size_) DWC_ALLOC_ATOMIC(_size_)\n+#define dwc_free(_ctx_,_addr_) DWC_FREE(_addr_)\n+\n+#ifdef DWC_LINUX\n+/* Linux doesn't need any extra parameters for DMA buffer allocation, so we\n+ * just throw away the DMA context parameter.\n+ */\n+#define dwc_dma_alloc(_ctx_,_size_,_dma_) DWC_DMA_ALLOC(_size_, _dma_)\n+#define dwc_dma_alloc_atomic(_ctx_,_size_,_dma_) DWC_DMA_ALLOC_ATOMIC(_size_, _dma_)\n+#define dwc_dma_free(_ctx_,_size_,_virt_,_dma_) DWC_DMA_FREE(_size_, _virt_, _dma_)\n+#endif\n+\n+#if defined(DWC_FREEBSD) || defined(DWC_NETBSD)\n+/** BSD needs several extra parameters for DMA buffer allocation, so we pass\n+ * them in using the DMA context parameter.\n+ */\n+#define dwc_dma_alloc DWC_DMA_ALLOC\n+#define dwc_dma_free DWC_DMA_FREE\n+#endif\n+\n+\n+/** @name Memory and String Processing */\n+\n+/** memset() clone */\n+extern void *DWC_MEMSET(void *dest, uint8_t byte, uint32_t size);\n+#define dwc_memset DWC_MEMSET\n+\n+/** memcpy() clone */\n+extern void *DWC_MEMCPY(void *dest, void const *src, uint32_t size);\n+#define dwc_memcpy DWC_MEMCPY\n+\n+/** memmove() clone */\n+extern void *DWC_MEMMOVE(void *dest, void *src, uint32_t size);\n+#define dwc_memmove DWC_MEMMOVE\n+\n+/** memcmp() clone */\n+extern int DWC_MEMCMP(void *m1, void *m2, uint32_t size);\n+#define dwc_memcmp DWC_MEMCMP\n+\n+/** strcmp() clone */\n+extern int DWC_STRCMP(void *s1, void *s2);\n+#define dwc_strcmp DWC_STRCMP\n+\n+/** strncmp() clone */\n+extern int DWC_STRNCMP(void *s1, void *s2, uint32_t size);\n+#define dwc_strncmp DWC_STRNCMP\n+\n+/** strlen() clone, for NULL terminated ASCII strings */\n+extern int DWC_STRLEN(char const *str);\n+#define dwc_strlen DWC_STRLEN\n+\n+/** strcpy() clone, for NULL terminated ASCII strings */\n+extern char *DWC_STRCPY(char *to, const char *from);\n+#define dwc_strcpy DWC_STRCPY\n+\n+/** strdup() clone.  If you wish to use memory allocation debugging, this\n+ * implementation of strdup should use the DWC_* memory routines instead of\n+ * calling a predefined strdup.  Otherwise the memory allocated by this routine\n+ * will not be seen by the debugging routines. */\n+extern char *DWC_STRDUP(char const *str);\n+#define dwc_strdup(_ctx_,_str_) DWC_STRDUP(_str_)\n+\n+/** NOT an atoi() clone.  Read the description carefully.  Returns an integer\n+ * converted from the string str in base 10 unless the string begins with a \"0x\"\n+ * in which case it is base 16.  String must be a NULL terminated sequence of\n+ * ASCII characters and may optionally begin with whitespace, a + or -, and a\n+ * \"0x\" prefix if base 16.  The remaining characters must be valid digits for\n+ * the number and end with a NULL character.  If any invalid characters are\n+ * encountered or it returns with a negative error code and the results of the\n+ * conversion are undefined.  On sucess it returns 0.  Overflow conditions are\n+ * undefined.  An example implementation using atoi() can be referenced from the\n+ * Linux implementation. */\n+extern int DWC_ATOI(const char *str, int32_t *value);\n+#define dwc_atoi DWC_ATOI\n+\n+/** Same as above but for unsigned. */\n+extern int DWC_ATOUI(const char *str, uint32_t *value);\n+#define dwc_atoui DWC_ATOUI\n+\n+#ifdef DWC_UTFLIB\n+/** This routine returns a UTF16LE unicode encoded string from a UTF8 string. */\n+extern int DWC_UTF8_TO_UTF16LE(uint8_t const *utf8string, uint16_t *utf16string, unsigned len);\n+#define dwc_utf8_to_utf16le DWC_UTF8_TO_UTF16LE\n+#endif\n+\n+\n+/** @name Wait queues\n+ *\n+ * Wait queues provide a means of synchronizing between threads or processes.  A\n+ * process can block on a waitq if some condition is not true, waiting for it to\n+ * become true.  When the waitq is triggered all waiting process will get\n+ * unblocked and the condition will be check again.  Waitqs should be triggered\n+ * every time a condition can potentially change.*/\n+struct dwc_waitq;\n+\n+/** Type for a waitq */\n+typedef struct dwc_waitq dwc_waitq_t;\n+\n+/** The type of waitq condition callback function.  This is called every time\n+ * condition is evaluated. */\n+typedef int (*dwc_waitq_condition_t)(void *data);\n+\n+/** Allocate a waitq */\n+extern dwc_waitq_t *DWC_WAITQ_ALLOC(void);\n+#define dwc_waitq_alloc(_ctx_) DWC_WAITQ_ALLOC()\n+\n+/** Free a waitq */\n+extern void DWC_WAITQ_FREE(dwc_waitq_t *wq);\n+#define dwc_waitq_free DWC_WAITQ_FREE\n+\n+/** Check the condition and if it is false, block on the waitq.  When unblocked, check the\n+ * condition again.  The function returns when the condition becomes true.  The return value\n+ * is 0 on condition true, DWC_WAITQ_ABORTED on abort or killed, or DWC_WAITQ_UNKNOWN on error. */\n+extern int32_t DWC_WAITQ_WAIT(dwc_waitq_t *wq, dwc_waitq_condition_t cond, void *data);\n+#define dwc_waitq_wait DWC_WAITQ_WAIT\n+\n+/** Check the condition and if it is false, block on the waitq.  When unblocked,\n+ * check the condition again.  The function returns when the condition become\n+ * true or the timeout has passed.  The return value is 0 on condition true or\n+ * DWC_TIMED_OUT on timeout, or DWC_WAITQ_ABORTED, or DWC_WAITQ_UNKNOWN on\n+ * error. */\n+extern int32_t DWC_WAITQ_WAIT_TIMEOUT(dwc_waitq_t *wq, dwc_waitq_condition_t cond,\n+\t\t\t\t      void *data, int32_t msecs);\n+#define dwc_waitq_wait_timeout DWC_WAITQ_WAIT_TIMEOUT\n+\n+/** Trigger a waitq, unblocking all processes.  This should be called whenever a condition\n+ * has potentially changed. */\n+extern void DWC_WAITQ_TRIGGER(dwc_waitq_t *wq);\n+#define dwc_waitq_trigger DWC_WAITQ_TRIGGER\n+\n+/** Unblock all processes waiting on the waitq with an ABORTED result. */\n+extern void DWC_WAITQ_ABORT(dwc_waitq_t *wq);\n+#define dwc_waitq_abort DWC_WAITQ_ABORT\n+\n+\n+/** @name Threads\n+ *\n+ * A thread must be explicitly stopped.  It must check DWC_THREAD_SHOULD_STOP\n+ * whenever it is woken up, and then return.  The DWC_THREAD_STOP function\n+ * returns the value from the thread.\n+ */\n+\n+struct dwc_thread;\n+\n+/** Type for a thread */\n+typedef struct dwc_thread dwc_thread_t;\n+\n+/** The thread function */\n+typedef int (*dwc_thread_function_t)(void *data);\n+\n+/** Create a thread and start it running the thread_function.  Returns a handle\n+ * to the thread */\n+extern dwc_thread_t *DWC_THREAD_RUN(dwc_thread_function_t func, char *name, void *data);\n+#define dwc_thread_run(_ctx_,_func_,_name_,_data_) DWC_THREAD_RUN(_func_, _name_, _data_)\n+\n+/** Stops a thread.  Return the value returned by the thread.  Or will return\n+ * DWC_ABORT if the thread never started. */\n+extern int DWC_THREAD_STOP(dwc_thread_t *thread);\n+#define dwc_thread_stop DWC_THREAD_STOP\n+\n+/** Signifies to the thread that it must stop. */\n+#ifdef DWC_LINUX\n+/* Linux doesn't need any parameters for kthread_should_stop() */\n+extern dwc_bool_t DWC_THREAD_SHOULD_STOP(void);\n+#define dwc_thread_should_stop(_thrd_) DWC_THREAD_SHOULD_STOP()\n+\n+/* No thread_exit function in Linux */\n+#define dwc_thread_exit(_thrd_)\n+#endif\n+\n+#if defined(DWC_FREEBSD) || defined(DWC_NETBSD)\n+/** BSD needs the thread pointer for kthread_suspend_check() */\n+extern dwc_bool_t DWC_THREAD_SHOULD_STOP(dwc_thread_t *thread);\n+#define dwc_thread_should_stop DWC_THREAD_SHOULD_STOP\n+\n+/** The thread must call this to exit. */\n+extern void DWC_THREAD_EXIT(dwc_thread_t *thread);\n+#define dwc_thread_exit DWC_THREAD_EXIT\n+#endif\n+\n+\n+/** @name Work queues\n+ *\n+ * Workqs are used to queue a callback function to be called at some later time,\n+ * in another thread. */\n+struct dwc_workq;\n+\n+/** Type for a workq */\n+typedef struct dwc_workq dwc_workq_t;\n+\n+/** The type of the callback function to be called. */\n+typedef void (*dwc_work_callback_t)(void *data);\n+\n+/** Allocate a workq */\n+extern dwc_workq_t *DWC_WORKQ_ALLOC(char *name);\n+#define dwc_workq_alloc(_ctx_,_name_) DWC_WORKQ_ALLOC(_name_)\n+\n+/** Free a workq.  All work must be completed before being freed. */\n+extern void DWC_WORKQ_FREE(dwc_workq_t *workq);\n+#define dwc_workq_free DWC_WORKQ_FREE\n+\n+/** Schedule a callback on the workq, passing in data.  The function will be\n+ * scheduled at some later time. */\n+extern void DWC_WORKQ_SCHEDULE(dwc_workq_t *workq, dwc_work_callback_t cb,\n+\t\t\t       void *data, char *format, ...)\n+#ifdef __GNUC__\n+\t__attribute__ ((format(printf, 4, 5)));\n+#else\n+\t;\n+#endif\n+#define dwc_workq_schedule DWC_WORKQ_SCHEDULE\n+\n+/** Schedule a callback on the workq, that will be called until at least\n+ * given number miliseconds have passed. */\n+extern void DWC_WORKQ_SCHEDULE_DELAYED(dwc_workq_t *workq, dwc_work_callback_t cb,\n+\t\t\t\t       void *data, uint32_t time, char *format, ...)\n+#ifdef __GNUC__\n+\t__attribute__ ((format(printf, 5, 6)));\n+#else\n+\t;\n+#endif\n+#define dwc_workq_schedule_delayed DWC_WORKQ_SCHEDULE_DELAYED\n+\n+/** The number of processes in the workq */\n+extern int DWC_WORKQ_PENDING(dwc_workq_t *workq);\n+#define dwc_workq_pending DWC_WORKQ_PENDING\n+\n+/** Blocks until all the work in the workq is complete or timed out.  Returns <\n+ * 0 on timeout. */\n+extern int DWC_WORKQ_WAIT_WORK_DONE(dwc_workq_t *workq, int timeout);\n+#define dwc_workq_wait_work_done DWC_WORKQ_WAIT_WORK_DONE\n+\n+\n+/** @name Tasklets\n+ *\n+ */\n+struct dwc_tasklet;\n+\n+/** Type for a tasklet */\n+typedef struct dwc_tasklet dwc_tasklet_t;\n+\n+/** The type of the callback function to be called */\n+typedef void (*dwc_tasklet_callback_t)(void *data);\n+\n+/** Allocates a tasklet */\n+extern dwc_tasklet_t *DWC_TASK_ALLOC(char *name, dwc_tasklet_callback_t cb, void *data);\n+#define dwc_task_alloc(_ctx_,_name_,_cb_,_data_) DWC_TASK_ALLOC(_name_, _cb_, _data_)\n+\n+/** Frees a tasklet */\n+extern void DWC_TASK_FREE(dwc_tasklet_t *task);\n+#define dwc_task_free DWC_TASK_FREE\n+\n+/** Schedules a tasklet to run */\n+extern void DWC_TASK_SCHEDULE(dwc_tasklet_t *task);\n+#define dwc_task_schedule DWC_TASK_SCHEDULE\n+\n+extern void DWC_TASK_HI_SCHEDULE(dwc_tasklet_t *task);\n+#define dwc_task_hi_schedule DWC_TASK_HI_SCHEDULE\n+\n+/** @name Timer\n+ *\n+ * Callbacks must be small and atomic.\n+ */\n+struct dwc_timer;\n+\n+/** Type for a timer */\n+typedef struct dwc_timer dwc_timer_t;\n+\n+/** The type of the callback function to be called */\n+typedef void (*dwc_timer_callback_t)(void *data);\n+\n+/** Allocates a timer */\n+extern dwc_timer_t *DWC_TIMER_ALLOC(char *name, dwc_timer_callback_t cb, void *data);\n+#define dwc_timer_alloc(_ctx_,_name_,_cb_,_data_) DWC_TIMER_ALLOC(_name_,_cb_,_data_)\n+\n+/** Frees a timer */\n+extern void DWC_TIMER_FREE(dwc_timer_t *timer);\n+#define dwc_timer_free DWC_TIMER_FREE\n+\n+/** Schedules the timer to run at time ms from now.  And will repeat at every\n+ * repeat_interval msec therafter\n+ *\n+ * Modifies a timer that is still awaiting execution to a new expiration time.\n+ * The mod_time is added to the old time.  */\n+extern void DWC_TIMER_SCHEDULE(dwc_timer_t *timer, uint32_t time);\n+#define dwc_timer_schedule DWC_TIMER_SCHEDULE\n+\n+/** Disables the timer from execution. */\n+extern void DWC_TIMER_CANCEL(dwc_timer_t *timer);\n+#define dwc_timer_cancel DWC_TIMER_CANCEL\n+\n+\n+/** @name Spinlocks\n+ *\n+ * These locks are used when the work between the lock/unlock is atomic and\n+ * short.  Interrupts are also disabled during the lock/unlock and thus they are\n+ * suitable to lock between interrupt/non-interrupt context.  They also lock\n+ * between processes if you have multiple CPUs or Preemption.  If you don't have\n+ * multiple CPUS or Preemption, then the you can simply implement the\n+ * DWC_SPINLOCK and DWC_SPINUNLOCK to disable and enable interrupts.  Because\n+ * the work between the lock/unlock is atomic, the process context will never\n+ * change, and so you never have to lock between processes.  */\n+\n+struct dwc_spinlock;\n+\n+/** Type for a spinlock */\n+typedef struct dwc_spinlock dwc_spinlock_t;\n+\n+/** Type for the 'flags' argument to spinlock funtions */\n+typedef unsigned long dwc_irqflags_t;\n+\n+/** Returns an initialized lock variable.  This function should allocate and\n+ * initialize the OS-specific data structure used for locking.  This data\n+ * structure is to be used for the DWC_LOCK and DWC_UNLOCK functions and should\n+ * be freed by the DWC_FREE_LOCK when it is no longer used.\n+ *\n+ * For Linux Spinlock Debugging make it macro because the debugging routines use\n+ * the symbol name to determine recursive locking. Using a wrapper function\n+ * makes it falsely think recursive locking occurs. */\n+#if defined(DWC_LINUX) && defined(CONFIG_DEBUG_SPINLOCK)\n+#define DWC_SPINLOCK_ALLOC_LINUX_DEBUG(lock) ({ \\\n+\tlock = DWC_ALLOC(sizeof(spinlock_t)); \\\n+\tif (lock) { \\\n+\t\tspin_lock_init((spinlock_t *)lock); \\\n+\t} \\\n+})\n+#else\n+extern dwc_spinlock_t *DWC_SPINLOCK_ALLOC(void);\n+#define dwc_spinlock_alloc(_ctx_) DWC_SPINLOCK_ALLOC()\n+#endif\n+\n+/** Frees an initialized lock variable. */\n+extern void DWC_SPINLOCK_FREE(dwc_spinlock_t *lock);\n+#define dwc_spinlock_free(_ctx_,_lock_) DWC_SPINLOCK_FREE(_lock_)\n+\n+/** Disables interrupts and blocks until it acquires the lock.\n+ *\n+ * @param lock Pointer to the spinlock.\n+ * @param flags Unsigned long for irq flags storage.\n+ */\n+extern void DWC_SPINLOCK_IRQSAVE(dwc_spinlock_t *lock, dwc_irqflags_t *flags);\n+#define dwc_spinlock_irqsave DWC_SPINLOCK_IRQSAVE\n+\n+/** Re-enables the interrupt and releases the lock.\n+ *\n+ * @param lock Pointer to the spinlock.\n+ * @param flags Unsigned long for irq flags storage.  Must be the same as was\n+ * passed into DWC_LOCK.\n+ */\n+extern void DWC_SPINUNLOCK_IRQRESTORE(dwc_spinlock_t *lock, dwc_irqflags_t flags);\n+#define dwc_spinunlock_irqrestore DWC_SPINUNLOCK_IRQRESTORE\n+\n+/** Blocks until it acquires the lock.\n+ *\n+ * @param lock Pointer to the spinlock.\n+ */\n+extern void DWC_SPINLOCK(dwc_spinlock_t *lock);\n+#define dwc_spinlock DWC_SPINLOCK\n+\n+/** Releases the lock.\n+ *\n+ * @param lock Pointer to the spinlock.\n+ */\n+extern void DWC_SPINUNLOCK(dwc_spinlock_t *lock);\n+#define dwc_spinunlock DWC_SPINUNLOCK\n+\n+\n+/** @name Mutexes\n+ *\n+ * Unlike spinlocks Mutexes lock only between processes and the work between the\n+ * lock/unlock CAN block, therefore it CANNOT be called from interrupt context.\n+ */\n+\n+struct dwc_mutex;\n+\n+/** Type for a mutex */\n+typedef struct dwc_mutex dwc_mutex_t;\n+\n+/* For Linux Mutex Debugging make it inline because the debugging routines use\n+ * the symbol to determine recursive locking.  This makes it falsely think\n+ * recursive locking occurs. */\n+#if defined(DWC_LINUX) && defined(CONFIG_DEBUG_MUTEXES)\n+#define DWC_MUTEX_ALLOC_LINUX_DEBUG(__mutexp) ({ \\\n+\t__mutexp = (dwc_mutex_t *)DWC_ALLOC(sizeof(struct mutex)); \\\n+\tmutex_init((struct mutex *)__mutexp); \\\n+})\n+#endif\n+\n+/** Allocate a mutex */\n+extern dwc_mutex_t *DWC_MUTEX_ALLOC(void);\n+#define dwc_mutex_alloc(_ctx_) DWC_MUTEX_ALLOC()\n+\n+/* For memory leak debugging when using Linux Mutex Debugging */\n+#if defined(DWC_LINUX) && defined(CONFIG_DEBUG_MUTEXES)\n+#define DWC_MUTEX_FREE(__mutexp) do { \\\n+\tmutex_destroy((struct mutex *)__mutexp); \\\n+\tDWC_FREE(__mutexp); \\\n+} while(0)\n+#else\n+/** Free a mutex */\n+extern void DWC_MUTEX_FREE(dwc_mutex_t *mutex);\n+#define dwc_mutex_free(_ctx_,_mutex_) DWC_MUTEX_FREE(_mutex_)\n+#endif\n+\n+/** Lock a mutex */\n+extern void DWC_MUTEX_LOCK(dwc_mutex_t *mutex);\n+#define dwc_mutex_lock DWC_MUTEX_LOCK\n+\n+/** Non-blocking lock returns 1 on successful lock. */\n+extern int DWC_MUTEX_TRYLOCK(dwc_mutex_t *mutex);\n+#define dwc_mutex_trylock DWC_MUTEX_TRYLOCK\n+\n+/** Unlock a mutex */\n+extern void DWC_MUTEX_UNLOCK(dwc_mutex_t *mutex);\n+#define dwc_mutex_unlock DWC_MUTEX_UNLOCK\n+\n+\n+/** @name Time */\n+\n+/** Microsecond delay.\n+ *\n+ * @param usecs  Microseconds to delay.\n+ */\n+extern void DWC_UDELAY(uint32_t usecs);\n+#define dwc_udelay DWC_UDELAY\n+\n+/** Millisecond delay.\n+ *\n+ * @param msecs  Milliseconds to delay.\n+ */\n+extern void DWC_MDELAY(uint32_t msecs);\n+#define dwc_mdelay DWC_MDELAY\n+\n+/** Non-busy waiting.\n+ * Sleeps for specified number of milliseconds.\n+ *\n+ * @param msecs Milliseconds to sleep.\n+ */\n+extern void DWC_MSLEEP(uint32_t msecs);\n+#define dwc_msleep DWC_MSLEEP\n+\n+/**\n+ * Returns number of milliseconds since boot.\n+ */\n+extern uint32_t DWC_TIME(void);\n+#define dwc_time DWC_TIME\n+\n+\n+\n+\n+/* @mainpage DWC Portability and Common Library\n+ *\n+ * This is the documentation for the DWC Portability and Common Library.\n+ *\n+ * @section intro Introduction\n+ *\n+ * The DWC Portability library consists of wrapper calls and data structures to\n+ * all low-level functions which are typically provided by the OS.  The WUDEV\n+ * driver uses only these functions.  In order to port the WUDEV driver, only\n+ * the functions in this library need to be re-implemented, with the same\n+ * behavior as documented here.\n+ *\n+ * The Common library consists of higher level functions, which rely only on\n+ * calling the functions from the DWC Portability library.  These common\n+ * routines are shared across modules.  Some of the common libraries need to be\n+ * used directly by the driver programmer when porting WUDEV.  Such as the\n+ * parameter and notification libraries.\n+ *\n+ * @section low Portability Library OS Wrapper Functions\n+ *\n+ * Any function starting with DWC and in all CAPS is a low-level OS-wrapper that\n+ * needs to be implemented when porting, for example DWC_MUTEX_ALLOC().  All of\n+ * these functions are included in the dwc_os.h file.\n+ *\n+ * There are many functions here covering a wide array of OS services.  Please\n+ * see dwc_os.h for details, and implementation notes for each function.\n+ *\n+ * @section common Common Library Functions\n+ *\n+ * Any function starting with dwc and in all lowercase is a common library\n+ * routine.  These functions have a portable implementation and do not need to\n+ * be reimplemented when porting.  The common routines can be used by any\n+ * driver, and some must be used by the end user to control the drivers.  For\n+ * example, you must use the Parameter common library in order to set the\n+ * parameters in the WUDEV module.\n+ *\n+ * The common libraries consist of the following:\n+ *\n+ * - Connection Contexts - Used internally and can be used by end-user.  See dwc_cc.h\n+ * - Parameters - Used internally and can be used by end-user.  See dwc_params.h\n+ * - Notifications - Used internally and can be used by end-user.  See dwc_notifier.h\n+ * - Lists - Used internally and can be used by end-user.  See dwc_list.h\n+ * - Memory Debugging - Used internally and can be used by end-user.  See dwc_os.h\n+ * - Modpow - Used internally only.  See dwc_modpow.h\n+ * - DH - Used internally only.  See dwc_dh.h\n+ * - Crypto - Used internally only.  See dwc_crypto.h\n+ *\n+ *\n+ * @section prereq Prerequistes For dwc_os.h\n+ * @subsection types Data Types\n+ *\n+ * The dwc_os.h file assumes that several low-level data types are pre defined for the\n+ * compilation environment.  These data types are:\n+ *\n+ * - uint8_t - unsigned 8-bit data type\n+ * - int8_t - signed 8-bit data type\n+ * - uint16_t - unsigned 16-bit data type\n+ * - int16_t - signed 16-bit data type\n+ * - uint32_t - unsigned 32-bit data type\n+ * - int32_t - signed 32-bit data type\n+ * - uint64_t - unsigned 64-bit data type\n+ * - int64_t - signed 64-bit data type\n+ *\n+ * Ensure that these are defined before using dwc_os.h.  The easiest way to do\n+ * that is to modify the top of the file to include the appropriate header.\n+ * This is already done for the Linux environment.  If the DWC_LINUX macro is\n+ * defined, the correct header will be added.  A standard header <stdint.h> is\n+ * also used for environments where standard C headers are available.\n+ *\n+ * @subsection stdarg Variable Arguments\n+ *\n+ * Variable arguments are provided by a standard C header <stdarg.h>.  it is\n+ * available in Both the Linux and ANSI C enviornment.  An equivalent must be\n+ * provided in your enviornment in order to use dwc_os.h with the debug and\n+ * tracing message functionality.\n+ *\n+ * @subsection thread Threading\n+ *\n+ * WUDEV Core must be run on an operating system that provides for multiple\n+ * threads/processes.  Threading can be implemented in many ways, even in\n+ * embedded systems without an operating system.  At the bare minimum, the\n+ * system should be able to start any number of processes at any time to handle\n+ * special work.  It need not be a pre-emptive system.  Process context can\n+ * change upon a call to a blocking function.  The hardware interrupt context\n+ * that calls the module's ISR() function must be differentiable from process\n+ * context, even if your processes are impemented via a hardware interrupt.\n+ * Further locking mechanism between process must exist (or be implemented), and\n+ * process context must have a way to disable interrupts for a period of time to\n+ * lock them out.  If all of this exists, the functions in dwc_os.h related to\n+ * threading should be able to be implemented with the defined behavior.\n+ *\n+ */\n+\n+#ifdef __cplusplus\n+}\n+#endif\n+\n+#endif /* _DWC_OS_H_ */\n--- /dev/null\n+++ b/drivers/usb/host/dwc_common_port/usb.h\n@@ -0,0 +1,946 @@\n+/*\n+ * Copyright (c) 1998 The NetBSD Foundation, Inc.\n+ * All rights reserved.\n+ *\n+ * This code is derived from software contributed to The NetBSD Foundation\n+ * by Lennart Augustsson (lennart@augustsson.net) at\n+ * Carlstedt Research & Technology.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ * 1. Redistributions of source code must retain the above copyright\n+ *    notice, this list of conditions and the following disclaimer.\n+ * 2. Redistributions in binary form must reproduce the above copyright\n+ *    notice, this list of conditions and the following disclaimer in the\n+ *    documentation and/or other materials provided with the distribution.\n+ * 3. All advertising materials mentioning features or use of this software\n+ *    must display the following acknowledgement:\n+ *        This product includes software developed by the NetBSD\n+ *        Foundation, Inc. and its contributors.\n+ * 4. Neither the name of The NetBSD Foundation nor the names of its\n+ *    contributors may be used to endorse or promote products derived\n+ *    from this software without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS\n+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED\n+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\n+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS\n+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n+ * POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+/* Modified by Synopsys, Inc, 12/12/2007 */\n+\n+\n+#ifndef _USB_H_\n+#define _USB_H_\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+/*\n+ * The USB records contain some unaligned little-endian word\n+ * components.  The U[SG]ETW macros take care of both the alignment\n+ * and endian problem and should always be used to access non-byte\n+ * values.\n+ */\n+typedef u_int8_t uByte;\n+typedef u_int8_t uWord[2];\n+typedef u_int8_t uDWord[4];\n+\n+#define USETW2(w,h,l) ((w)[0] = (u_int8_t)(l), (w)[1] = (u_int8_t)(h))\n+#define UCONSTW(x)\t{ (x) & 0xff, ((x) >> 8) & 0xff }\n+#define UCONSTDW(x)\t{ (x) & 0xff, ((x) >> 8) & 0xff, \\\n+\t\t\t  ((x) >> 16) & 0xff, ((x) >> 24) & 0xff }\n+\n+#if 1\n+#define UGETW(w) ((w)[0] | ((w)[1] << 8))\n+#define USETW(w,v) ((w)[0] = (u_int8_t)(v), (w)[1] = (u_int8_t)((v) >> 8))\n+#define UGETDW(w) ((w)[0] | ((w)[1] << 8) | ((w)[2] << 16) | ((w)[3] << 24))\n+#define USETDW(w,v) ((w)[0] = (u_int8_t)(v), \\\n+\t\t     (w)[1] = (u_int8_t)((v) >> 8), \\\n+\t\t     (w)[2] = (u_int8_t)((v) >> 16), \\\n+\t\t     (w)[3] = (u_int8_t)((v) >> 24))\n+#else\n+/*\n+ * On little-endian machines that can handle unanliged accesses\n+ * (e.g. i386) these macros can be replaced by the following.\n+ */\n+#define UGETW(w) (*(u_int16_t *)(w))\n+#define USETW(w,v) (*(u_int16_t *)(w) = (v))\n+#define UGETDW(w) (*(u_int32_t *)(w))\n+#define USETDW(w,v) (*(u_int32_t *)(w) = (v))\n+#endif\n+\n+/*\n+ * Macros for accessing UAS IU fields, which are big-endian\n+ */\n+#define IUSETW2(w,h,l) ((w)[0] = (u_int8_t)(h), (w)[1] = (u_int8_t)(l))\n+#define IUCONSTW(x)\t{ ((x) >> 8) & 0xff, (x) & 0xff }\n+#define IUCONSTDW(x)\t{ ((x) >> 24) & 0xff, ((x) >> 16) & 0xff, \\\n+\t\t\t((x) >> 8) & 0xff, (x) & 0xff }\n+#define IUGETW(w) (((w)[0] << 8) | (w)[1])\n+#define IUSETW(w,v) ((w)[0] = (u_int8_t)((v) >> 8), (w)[1] = (u_int8_t)(v))\n+#define IUGETDW(w) (((w)[0] << 24) | ((w)[1] << 16) | ((w)[2] << 8) | (w)[3])\n+#define IUSETDW(w,v) ((w)[0] = (u_int8_t)((v) >> 24), \\\n+\t\t      (w)[1] = (u_int8_t)((v) >> 16), \\\n+\t\t      (w)[2] = (u_int8_t)((v) >> 8), \\\n+\t\t      (w)[3] = (u_int8_t)(v))\n+\n+#define UPACKED __attribute__((__packed__))\n+\n+typedef struct {\n+\tuByte\t\tbmRequestType;\n+\tuByte\t\tbRequest;\n+\tuWord\t\twValue;\n+\tuWord\t\twIndex;\n+\tuWord\t\twLength;\n+} UPACKED usb_device_request_t;\n+\n+#define UT_GET_DIR(a) ((a) & 0x80)\n+#define UT_WRITE\t\t0x00\n+#define UT_READ\t\t\t0x80\n+\n+#define UT_GET_TYPE(a) ((a) & 0x60)\n+#define UT_STANDARD\t\t0x00\n+#define UT_CLASS\t\t0x20\n+#define UT_VENDOR\t\t0x40\n+\n+#define UT_GET_RECIPIENT(a) ((a) & 0x1f)\n+#define UT_DEVICE\t\t0x00\n+#define UT_INTERFACE\t\t0x01\n+#define UT_ENDPOINT\t\t0x02\n+#define UT_OTHER\t\t0x03\n+\n+#define UT_READ_DEVICE\t\t(UT_READ  | UT_STANDARD | UT_DEVICE)\n+#define UT_READ_INTERFACE\t(UT_READ  | UT_STANDARD | UT_INTERFACE)\n+#define UT_READ_ENDPOINT\t(UT_READ  | UT_STANDARD | UT_ENDPOINT)\n+#define UT_WRITE_DEVICE\t\t(UT_WRITE | UT_STANDARD | UT_DEVICE)\n+#define UT_WRITE_INTERFACE\t(UT_WRITE | UT_STANDARD | UT_INTERFACE)\n+#define UT_WRITE_ENDPOINT\t(UT_WRITE | UT_STANDARD | UT_ENDPOINT)\n+#define UT_READ_CLASS_DEVICE\t(UT_READ  | UT_CLASS | UT_DEVICE)\n+#define UT_READ_CLASS_INTERFACE\t(UT_READ  | UT_CLASS | UT_INTERFACE)\n+#define UT_READ_CLASS_OTHER\t(UT_READ  | UT_CLASS | UT_OTHER)\n+#define UT_READ_CLASS_ENDPOINT\t(UT_READ  | UT_CLASS | UT_ENDPOINT)\n+#define UT_WRITE_CLASS_DEVICE\t(UT_WRITE | UT_CLASS | UT_DEVICE)\n+#define UT_WRITE_CLASS_INTERFACE (UT_WRITE | UT_CLASS | UT_INTERFACE)\n+#define UT_WRITE_CLASS_OTHER\t(UT_WRITE | UT_CLASS | UT_OTHER)\n+#define UT_WRITE_CLASS_ENDPOINT\t(UT_WRITE | UT_CLASS | UT_ENDPOINT)\n+#define UT_READ_VENDOR_DEVICE\t(UT_READ  | UT_VENDOR | UT_DEVICE)\n+#define UT_READ_VENDOR_INTERFACE (UT_READ  | UT_VENDOR | UT_INTERFACE)\n+#define UT_READ_VENDOR_OTHER\t(UT_READ  | UT_VENDOR | UT_OTHER)\n+#define UT_READ_VENDOR_ENDPOINT\t(UT_READ  | UT_VENDOR | UT_ENDPOINT)\n+#define UT_WRITE_VENDOR_DEVICE\t(UT_WRITE | UT_VENDOR | UT_DEVICE)\n+#define UT_WRITE_VENDOR_INTERFACE (UT_WRITE | UT_VENDOR | UT_INTERFACE)\n+#define UT_WRITE_VENDOR_OTHER\t(UT_WRITE | UT_VENDOR | UT_OTHER)\n+#define UT_WRITE_VENDOR_ENDPOINT (UT_WRITE | UT_VENDOR | UT_ENDPOINT)\n+\n+/* Requests */\n+#define UR_GET_STATUS\t\t0x00\n+#define  USTAT_STANDARD_STATUS  0x00\n+#define  WUSTAT_WUSB_FEATURE    0x01\n+#define  WUSTAT_CHANNEL_INFO    0x02\n+#define  WUSTAT_RECEIVED_DATA   0x03\n+#define  WUSTAT_MAS_AVAILABILITY 0x04\n+#define  WUSTAT_CURRENT_TRANSMIT_POWER 0x05\n+#define UR_CLEAR_FEATURE\t0x01\n+#define UR_SET_FEATURE\t\t0x03\n+#define UR_SET_AND_TEST_FEATURE 0x0c\n+#define UR_SET_ADDRESS\t\t0x05\n+#define UR_GET_DESCRIPTOR\t0x06\n+#define  UDESC_DEVICE\t\t0x01\n+#define  UDESC_CONFIG\t\t0x02\n+#define  UDESC_STRING\t\t0x03\n+#define  UDESC_INTERFACE\t0x04\n+#define  UDESC_ENDPOINT\t\t0x05\n+#define  UDESC_SS_USB_COMPANION\t0x30\n+#define  UDESC_DEVICE_QUALIFIER\t0x06\n+#define  UDESC_OTHER_SPEED_CONFIGURATION 0x07\n+#define  UDESC_INTERFACE_POWER\t0x08\n+#define  UDESC_OTG\t\t0x09\n+#define  WUDESC_SECURITY\t0x0c\n+#define  WUDESC_KEY\t\t0x0d\n+#define   WUD_GET_KEY_INDEX(_wValue_) ((_wValue_) & 0xf)\n+#define   WUD_GET_KEY_TYPE(_wValue_) (((_wValue_) & 0x30) >> 4)\n+#define    WUD_KEY_TYPE_ASSOC    0x01\n+#define    WUD_KEY_TYPE_GTK      0x02\n+#define   WUD_GET_KEY_ORIGIN(_wValue_) (((_wValue_) & 0x40) >> 6)\n+#define    WUD_KEY_ORIGIN_HOST   0x00\n+#define    WUD_KEY_ORIGIN_DEVICE 0x01\n+#define  WUDESC_ENCRYPTION_TYPE\t0x0e\n+#define  WUDESC_BOS\t\t0x0f\n+#define  WUDESC_DEVICE_CAPABILITY 0x10\n+#define  WUDESC_WIRELESS_ENDPOINT_COMPANION 0x11\n+#define  UDESC_BOS\t\t0x0f\n+#define  UDESC_DEVICE_CAPABILITY 0x10\n+#define  UDESC_CS_DEVICE\t0x21\t/* class specific */\n+#define  UDESC_CS_CONFIG\t0x22\n+#define  UDESC_CS_STRING\t0x23\n+#define  UDESC_CS_INTERFACE\t0x24\n+#define  UDESC_CS_ENDPOINT\t0x25\n+#define  UDESC_HUB\t\t0x29\n+#define UR_SET_DESCRIPTOR\t0x07\n+#define UR_GET_CONFIG\t\t0x08\n+#define UR_SET_CONFIG\t\t0x09\n+#define UR_GET_INTERFACE\t0x0a\n+#define UR_SET_INTERFACE\t0x0b\n+#define UR_SYNCH_FRAME\t\t0x0c\n+#define WUR_SET_ENCRYPTION      0x0d\n+#define WUR_GET_ENCRYPTION\t0x0e\n+#define WUR_SET_HANDSHAKE\t0x0f\n+#define WUR_GET_HANDSHAKE\t0x10\n+#define WUR_SET_CONNECTION\t0x11\n+#define WUR_SET_SECURITY_DATA\t0x12\n+#define WUR_GET_SECURITY_DATA\t0x13\n+#define WUR_SET_WUSB_DATA\t0x14\n+#define  WUDATA_DRPIE_INFO\t0x01\n+#define  WUDATA_TRANSMIT_DATA\t0x02\n+#define  WUDATA_TRANSMIT_PARAMS\t0x03\n+#define  WUDATA_RECEIVE_PARAMS\t0x04\n+#define  WUDATA_TRANSMIT_POWER\t0x05\n+#define WUR_LOOPBACK_DATA_WRITE\t0x15\n+#define WUR_LOOPBACK_DATA_READ\t0x16\n+#define WUR_SET_INTERFACE_DS\t0x17\n+\n+/* Feature numbers */\n+#define UF_ENDPOINT_HALT\t0\n+#define UF_DEVICE_REMOTE_WAKEUP\t1\n+#define UF_TEST_MODE\t\t2\n+#define UF_DEVICE_B_HNP_ENABLE\t3\n+#define UF_DEVICE_A_HNP_SUPPORT\t4\n+#define UF_DEVICE_A_ALT_HNP_SUPPORT 5\n+#define WUF_WUSB\t\t3\n+#define  WUF_TX_DRPIE\t\t0x0\n+#define  WUF_DEV_XMIT_PACKET\t0x1\n+#define  WUF_COUNT_PACKETS\t0x2\n+#define  WUF_CAPTURE_PACKETS\t0x3\n+#define UF_FUNCTION_SUSPEND\t0\n+#define UF_U1_ENABLE\t\t48\n+#define UF_U2_ENABLE\t\t49\n+#define UF_LTM_ENABLE\t\t50\n+\n+/* Class requests from the USB 2.0 hub spec, table 11-15 */\n+#define UCR_CLEAR_HUB_FEATURE\t\t(0x2000 | UR_CLEAR_FEATURE)\n+#define UCR_CLEAR_PORT_FEATURE\t\t(0x2300 | UR_CLEAR_FEATURE)\n+#define UCR_GET_HUB_DESCRIPTOR\t\t(0xa000 | UR_GET_DESCRIPTOR)\n+#define UCR_GET_HUB_STATUS\t\t(0xa000 | UR_GET_STATUS)\n+#define UCR_GET_PORT_STATUS\t\t(0xa300 | UR_GET_STATUS)\n+#define UCR_SET_HUB_FEATURE\t\t(0x2000 | UR_SET_FEATURE)\n+#define UCR_SET_PORT_FEATURE\t\t(0x2300 | UR_SET_FEATURE)\n+#define UCR_SET_AND_TEST_PORT_FEATURE\t(0xa300 | UR_SET_AND_TEST_FEATURE)\n+\n+#ifdef _MSC_VER\n+#include <pshpack1.h>\n+#endif\n+\n+typedef struct {\n+\tuByte\t\tbLength;\n+\tuByte\t\tbDescriptorType;\n+\tuByte\t\tbDescriptorSubtype;\n+} UPACKED usb_descriptor_t;\n+\n+typedef struct {\n+\tuByte\t\tbLength;\n+\tuByte\t\tbDescriptorType;\n+} UPACKED usb_descriptor_header_t;\n+\n+typedef struct {\n+\tuByte\t\tbLength;\n+\tuByte\t\tbDescriptorType;\n+\tuWord\t\tbcdUSB;\n+#define UD_USB_2_0\t\t0x0200\n+#define UD_IS_USB2(d) (UGETW((d)->bcdUSB) >= UD_USB_2_0)\n+\tuByte\t\tbDeviceClass;\n+\tuByte\t\tbDeviceSubClass;\n+\tuByte\t\tbDeviceProtocol;\n+\tuByte\t\tbMaxPacketSize;\n+\t/* The fields below are not part of the initial descriptor. */\n+\tuWord\t\tidVendor;\n+\tuWord\t\tidProduct;\n+\tuWord\t\tbcdDevice;\n+\tuByte\t\tiManufacturer;\n+\tuByte\t\tiProduct;\n+\tuByte\t\tiSerialNumber;\n+\tuByte\t\tbNumConfigurations;\n+} UPACKED usb_device_descriptor_t;\n+#define USB_DEVICE_DESCRIPTOR_SIZE 18\n+\n+typedef struct {\n+\tuByte\t\tbLength;\n+\tuByte\t\tbDescriptorType;\n+\tuWord\t\twTotalLength;\n+\tuByte\t\tbNumInterface;\n+\tuByte\t\tbConfigurationValue;\n+\tuByte\t\tiConfiguration;\n+#define UC_ATT_ONE\t\t(1 << 7)\t/* must be set */\n+#define UC_ATT_SELFPOWER\t(1 << 6)\t/* self powered */\n+#define UC_ATT_WAKEUP\t\t(1 << 5)\t/* can wakeup */\n+#define UC_ATT_BATTERY\t\t(1 << 4)\t/* battery powered */\n+\tuByte\t\tbmAttributes;\n+#define UC_BUS_POWERED\t\t0x80\n+#define UC_SELF_POWERED\t\t0x40\n+#define UC_REMOTE_WAKEUP\t0x20\n+\tuByte\t\tbMaxPower; /* max current in 2 mA units */\n+#define UC_POWER_FACTOR 2\n+} UPACKED usb_config_descriptor_t;\n+#define USB_CONFIG_DESCRIPTOR_SIZE 9\n+\n+typedef struct {\n+\tuByte\t\tbLength;\n+\tuByte\t\tbDescriptorType;\n+\tuByte\t\tbInterfaceNumber;\n+\tuByte\t\tbAlternateSetting;\n+\tuByte\t\tbNumEndpoints;\n+\tuByte\t\tbInterfaceClass;\n+\tuByte\t\tbInterfaceSubClass;\n+\tuByte\t\tbInterfaceProtocol;\n+\tuByte\t\tiInterface;\n+} UPACKED usb_interface_descriptor_t;\n+#define USB_INTERFACE_DESCRIPTOR_SIZE 9\n+\n+typedef struct {\n+\tuByte\t\tbLength;\n+\tuByte\t\tbDescriptorType;\n+\tuByte\t\tbEndpointAddress;\n+#define UE_GET_DIR(a)\t((a) & 0x80)\n+#define UE_SET_DIR(a,d)\t((a) | (((d)&1) << 7))\n+#define UE_DIR_IN\t0x80\n+#define UE_DIR_OUT\t0x00\n+#define UE_ADDR\t\t0x0f\n+#define UE_GET_ADDR(a)\t((a) & UE_ADDR)\n+\tuByte\t\tbmAttributes;\n+#define UE_XFERTYPE\t0x03\n+#define  UE_CONTROL\t0x00\n+#define  UE_ISOCHRONOUS\t0x01\n+#define  UE_BULK\t0x02\n+#define  UE_INTERRUPT\t0x03\n+#define UE_GET_XFERTYPE(a)\t((a) & UE_XFERTYPE)\n+#define UE_ISO_TYPE\t0x0c\n+#define  UE_ISO_ASYNC\t0x04\n+#define  UE_ISO_ADAPT\t0x08\n+#define  UE_ISO_SYNC\t0x0c\n+#define UE_GET_ISO_TYPE(a)\t((a) & UE_ISO_TYPE)\n+\tuWord\t\twMaxPacketSize;\n+\tuByte\t\tbInterval;\n+} UPACKED usb_endpoint_descriptor_t;\n+#define USB_ENDPOINT_DESCRIPTOR_SIZE 7\n+\n+typedef struct ss_endpoint_companion_descriptor {\n+\tuByte bLength;\n+\tuByte bDescriptorType;\n+\tuByte bMaxBurst;\n+#define USSE_GET_MAX_STREAMS(a)\t\t((a) & 0x1f)\n+#define USSE_SET_MAX_STREAMS(a, b)\t((a) | ((b) & 0x1f))\n+#define USSE_GET_MAX_PACKET_NUM(a)\t((a) & 0x03)\n+#define USSE_SET_MAX_PACKET_NUM(a, b)\t((a) | ((b) & 0x03))\n+\tuByte bmAttributes;\n+\tuWord wBytesPerInterval;\n+} UPACKED ss_endpoint_companion_descriptor_t;\n+#define USB_SS_ENDPOINT_COMPANION_DESCRIPTOR_SIZE 6\n+\n+typedef struct {\n+\tuByte\t\tbLength;\n+\tuByte\t\tbDescriptorType;\n+\tuWord\t\tbString[127];\n+} UPACKED usb_string_descriptor_t;\n+#define USB_MAX_STRING_LEN 128\n+#define USB_LANGUAGE_TABLE 0\t/* # of the string language id table */\n+\n+/* Hub specific request */\n+#define UR_GET_BUS_STATE\t0x02\n+#define UR_CLEAR_TT_BUFFER\t0x08\n+#define UR_RESET_TT\t\t0x09\n+#define UR_GET_TT_STATE\t\t0x0a\n+#define UR_STOP_TT\t\t0x0b\n+\n+/* Hub features */\n+#define UHF_C_HUB_LOCAL_POWER\t0\n+#define UHF_C_HUB_OVER_CURRENT\t1\n+#define UHF_PORT_CONNECTION\t0\n+#define UHF_PORT_ENABLE\t\t1\n+#define UHF_PORT_SUSPEND\t2\n+#define UHF_PORT_OVER_CURRENT\t3\n+#define UHF_PORT_RESET\t\t4\n+#define UHF_PORT_L1\t\t5\n+#define UHF_PORT_POWER\t\t8\n+#define UHF_PORT_LOW_SPEED\t9\n+#define UHF_PORT_HIGH_SPEED\t10\n+#define UHF_C_PORT_CONNECTION\t16\n+#define UHF_C_PORT_ENABLE\t17\n+#define UHF_C_PORT_SUSPEND\t18\n+#define UHF_C_PORT_OVER_CURRENT\t19\n+#define UHF_C_PORT_RESET\t20\n+#define UHF_C_PORT_L1\t\t23\n+#define UHF_PORT_TEST\t\t21\n+#define UHF_PORT_INDICATOR\t22\n+\n+typedef struct {\n+\tuByte\t\tbDescLength;\n+\tuByte\t\tbDescriptorType;\n+\tuByte\t\tbNbrPorts;\n+\tuWord\t\twHubCharacteristics;\n+#define UHD_PWR\t\t\t0x0003\n+#define  UHD_PWR_GANGED\t\t0x0000\n+#define  UHD_PWR_INDIVIDUAL\t0x0001\n+#define  UHD_PWR_NO_SWITCH\t0x0002\n+#define UHD_COMPOUND\t\t0x0004\n+#define UHD_OC\t\t\t0x0018\n+#define  UHD_OC_GLOBAL\t\t0x0000\n+#define  UHD_OC_INDIVIDUAL\t0x0008\n+#define  UHD_OC_NONE\t\t0x0010\n+#define UHD_TT_THINK\t\t0x0060\n+#define  UHD_TT_THINK_8\t\t0x0000\n+#define  UHD_TT_THINK_16\t0x0020\n+#define  UHD_TT_THINK_24\t0x0040\n+#define  UHD_TT_THINK_32\t0x0060\n+#define UHD_PORT_IND\t\t0x0080\n+\tuByte\t\tbPwrOn2PwrGood;\t/* delay in 2 ms units */\n+#define UHD_PWRON_FACTOR 2\n+\tuByte\t\tbHubContrCurrent;\n+\tuByte\t\tDeviceRemovable[32]; /* max 255 ports */\n+#define UHD_NOT_REMOV(desc, i) \\\n+    (((desc)->DeviceRemovable[(i)/8] >> ((i) % 8)) & 1)\n+\t/* deprecated */ uByte\t\tPortPowerCtrlMask[1];\n+} UPACKED usb_hub_descriptor_t;\n+#define USB_HUB_DESCRIPTOR_SIZE 9 /* includes deprecated PortPowerCtrlMask */\n+\n+typedef struct {\n+\tuByte\t\tbLength;\n+\tuByte\t\tbDescriptorType;\n+\tuWord\t\tbcdUSB;\n+\tuByte\t\tbDeviceClass;\n+\tuByte\t\tbDeviceSubClass;\n+\tuByte\t\tbDeviceProtocol;\n+\tuByte\t\tbMaxPacketSize0;\n+\tuByte\t\tbNumConfigurations;\n+\tuByte\t\tbReserved;\n+} UPACKED usb_device_qualifier_t;\n+#define USB_DEVICE_QUALIFIER_SIZE 10\n+\n+typedef struct {\n+\tuByte\t\tbLength;\n+\tuByte\t\tbDescriptorType;\n+\tuByte\t\tbmAttributes;\n+#define UOTG_SRP\t0x01\n+#define UOTG_HNP\t0x02\n+} UPACKED usb_otg_descriptor_t;\n+\n+/* OTG feature selectors */\n+#define UOTG_B_HNP_ENABLE\t3\n+#define UOTG_A_HNP_SUPPORT\t4\n+#define UOTG_A_ALT_HNP_SUPPORT\t5\n+\n+typedef struct {\n+\tuWord\t\twStatus;\n+/* Device status flags */\n+#define UDS_SELF_POWERED\t\t0x0001\n+#define UDS_REMOTE_WAKEUP\t\t0x0002\n+/* Endpoint status flags */\n+#define UES_HALT\t\t\t0x0001\n+} UPACKED usb_status_t;\n+\n+typedef struct {\n+\tuWord\t\twHubStatus;\n+#define UHS_LOCAL_POWER\t\t\t0x0001\n+#define UHS_OVER_CURRENT\t\t0x0002\n+\tuWord\t\twHubChange;\n+} UPACKED usb_hub_status_t;\n+\n+typedef struct {\n+\tuWord\t\twPortStatus;\n+#define UPS_CURRENT_CONNECT_STATUS\t0x0001\n+#define UPS_PORT_ENABLED\t\t0x0002\n+#define UPS_SUSPEND\t\t\t0x0004\n+#define UPS_OVERCURRENT_INDICATOR\t0x0008\n+#define UPS_RESET\t\t\t0x0010\n+#define UPS_PORT_POWER\t\t\t0x0100\n+#define UPS_LOW_SPEED\t\t\t0x0200\n+#define UPS_HIGH_SPEED\t\t\t0x0400\n+#define UPS_PORT_TEST\t\t\t0x0800\n+#define UPS_PORT_INDICATOR\t\t0x1000\n+\tuWord\t\twPortChange;\n+#define UPS_C_CONNECT_STATUS\t\t0x0001\n+#define UPS_C_PORT_ENABLED\t\t0x0002\n+#define UPS_C_SUSPEND\t\t\t0x0004\n+#define UPS_C_OVERCURRENT_INDICATOR\t0x0008\n+#define UPS_C_PORT_RESET\t\t0x0010\n+} UPACKED usb_port_status_t;\n+\n+#ifdef _MSC_VER\n+#include <poppack.h>\n+#endif\n+\n+/* Device class codes */\n+#define UDCLASS_IN_INTERFACE\t0x00\n+#define UDCLASS_COMM\t\t0x02\n+#define UDCLASS_HUB\t\t0x09\n+#define  UDSUBCLASS_HUB\t\t0x00\n+#define  UDPROTO_FSHUB\t\t0x00\n+#define  UDPROTO_HSHUBSTT\t0x01\n+#define  UDPROTO_HSHUBMTT\t0x02\n+#define UDCLASS_DIAGNOSTIC\t0xdc\n+#define UDCLASS_WIRELESS\t0xe0\n+#define  UDSUBCLASS_RF\t\t0x01\n+#define   UDPROTO_BLUETOOTH\t0x01\n+#define UDCLASS_VENDOR\t\t0xff\n+\n+/* Interface class codes */\n+#define UICLASS_UNSPEC\t\t0x00\n+\n+#define UICLASS_AUDIO\t\t0x01\n+#define  UISUBCLASS_AUDIOCONTROL\t1\n+#define  UISUBCLASS_AUDIOSTREAM\t\t2\n+#define  UISUBCLASS_MIDISTREAM\t\t3\n+\n+#define UICLASS_CDC\t\t0x02 /* communication */\n+#define  UISUBCLASS_DIRECT_LINE_CONTROL_MODEL\t1\n+#define  UISUBCLASS_ABSTRACT_CONTROL_MODEL\t2\n+#define  UISUBCLASS_TELEPHONE_CONTROL_MODEL\t3\n+#define  UISUBCLASS_MULTICHANNEL_CONTROL_MODEL\t4\n+#define  UISUBCLASS_CAPI_CONTROLMODEL\t\t5\n+#define  UISUBCLASS_ETHERNET_NETWORKING_CONTROL_MODEL 6\n+#define  UISUBCLASS_ATM_NETWORKING_CONTROL_MODEL 7\n+#define   UIPROTO_CDC_AT\t\t\t1\n+\n+#define UICLASS_HID\t\t0x03\n+#define  UISUBCLASS_BOOT\t1\n+#define  UIPROTO_BOOT_KEYBOARD\t1\n+\n+#define UICLASS_PHYSICAL\t0x05\n+\n+#define UICLASS_IMAGE\t\t0x06\n+\n+#define UICLASS_PRINTER\t\t0x07\n+#define  UISUBCLASS_PRINTER\t1\n+#define  UIPROTO_PRINTER_UNI\t1\n+#define  UIPROTO_PRINTER_BI\t2\n+#define  UIPROTO_PRINTER_1284\t3\n+\n+#define UICLASS_MASS\t\t0x08\n+#define  UISUBCLASS_RBC\t\t1\n+#define  UISUBCLASS_SFF8020I\t2\n+#define  UISUBCLASS_QIC157\t3\n+#define  UISUBCLASS_UFI\t\t4\n+#define  UISUBCLASS_SFF8070I\t5\n+#define  UISUBCLASS_SCSI\t6\n+#define  UIPROTO_MASS_CBI_I\t0\n+#define  UIPROTO_MASS_CBI\t1\n+#define  UIPROTO_MASS_BBB_OLD\t2\t/* Not in the spec anymore */\n+#define  UIPROTO_MASS_BBB\t80\t/* 'P' for the Iomega Zip drive */\n+\n+#define UICLASS_HUB\t\t0x09\n+#define  UISUBCLASS_HUB\t\t0\n+#define  UIPROTO_FSHUB\t\t0\n+#define  UIPROTO_HSHUBSTT\t0 /* Yes, same as previous */\n+#define  UIPROTO_HSHUBMTT\t1\n+\n+#define UICLASS_CDC_DATA\t0x0a\n+#define  UISUBCLASS_DATA\t\t0\n+#define   UIPROTO_DATA_ISDNBRI\t\t0x30    /* Physical iface */\n+#define   UIPROTO_DATA_HDLC\t\t0x31    /* HDLC */\n+#define   UIPROTO_DATA_TRANSPARENT\t0x32    /* Transparent */\n+#define   UIPROTO_DATA_Q921M\t\t0x50    /* Management for Q921 */\n+#define   UIPROTO_DATA_Q921\t\t0x51    /* Data for Q921 */\n+#define   UIPROTO_DATA_Q921TM\t\t0x52    /* TEI multiplexer for Q921 */\n+#define   UIPROTO_DATA_V42BIS\t\t0x90    /* Data compression */\n+#define   UIPROTO_DATA_Q931\t\t0x91    /* Euro-ISDN */\n+#define   UIPROTO_DATA_V120\t\t0x92    /* V.24 rate adaption */\n+#define   UIPROTO_DATA_CAPI\t\t0x93    /* CAPI 2.0 commands */\n+#define   UIPROTO_DATA_HOST_BASED\t0xfd    /* Host based driver */\n+#define   UIPROTO_DATA_PUF\t\t0xfe    /* see Prot. Unit Func. Desc.*/\n+#define   UIPROTO_DATA_VENDOR\t\t0xff    /* Vendor specific */\n+\n+#define UICLASS_SMARTCARD\t0x0b\n+\n+/*#define UICLASS_FIRM_UPD\t0x0c*/\n+\n+#define UICLASS_SECURITY\t0x0d\n+\n+#define UICLASS_DIAGNOSTIC\t0xdc\n+\n+#define UICLASS_WIRELESS\t0xe0\n+#define  UISUBCLASS_RF\t\t\t0x01\n+#define   UIPROTO_BLUETOOTH\t\t0x01\n+\n+#define UICLASS_APPL_SPEC\t0xfe\n+#define  UISUBCLASS_FIRMWARE_DOWNLOAD\t1\n+#define  UISUBCLASS_IRDA\t\t2\n+#define  UIPROTO_IRDA\t\t\t0\n+\n+#define UICLASS_VENDOR\t\t0xff\n+\n+#define USB_HUB_MAX_DEPTH 5\n+\n+/*\n+ * Minimum time a device needs to be powered down to go through\n+ * a power cycle.  XXX Are these time in the spec?\n+ */\n+#define USB_POWER_DOWN_TIME\t200 /* ms */\n+#define USB_PORT_POWER_DOWN_TIME\t100 /* ms */\n+\n+#if 0\n+/* These are the values from the spec. */\n+#define USB_PORT_RESET_DELAY\t10  /* ms */\n+#define USB_PORT_ROOT_RESET_DELAY 50  /* ms */\n+#define USB_PORT_RESET_RECOVERY\t10  /* ms */\n+#define USB_PORT_POWERUP_DELAY\t100 /* ms */\n+#define USB_SET_ADDRESS_SETTLE\t2   /* ms */\n+#define USB_RESUME_DELAY\t(20*5)  /* ms */\n+#define USB_RESUME_WAIT\t\t10  /* ms */\n+#define USB_RESUME_RECOVERY\t10  /* ms */\n+#define USB_EXTRA_POWER_UP_TIME\t0   /* ms */\n+#else\n+/* Allow for marginal (i.e. non-conforming) devices. */\n+#define USB_PORT_RESET_DELAY\t50  /* ms */\n+#define USB_PORT_ROOT_RESET_DELAY 250  /* ms */\n+#define USB_PORT_RESET_RECOVERY\t250  /* ms */\n+#define USB_PORT_POWERUP_DELAY\t300 /* ms */\n+#define USB_SET_ADDRESS_SETTLE\t10  /* ms */\n+#define USB_RESUME_DELAY\t(50*5)  /* ms */\n+#define USB_RESUME_WAIT\t\t50  /* ms */\n+#define USB_RESUME_RECOVERY\t50  /* ms */\n+#define USB_EXTRA_POWER_UP_TIME\t20  /* ms */\n+#endif\n+\n+#define USB_MIN_POWER\t\t100 /* mA */\n+#define USB_MAX_POWER\t\t500 /* mA */\n+\n+#define USB_BUS_RESET_DELAY\t100 /* ms XXX?*/\n+\n+#define USB_UNCONFIG_NO 0\n+#define USB_UNCONFIG_INDEX (-1)\n+\n+/*** ioctl() related stuff ***/\n+\n+struct usb_ctl_request {\n+\tint\tucr_addr;\n+\tusb_device_request_t ucr_request;\n+\tvoid\t*ucr_data;\n+\tint\tucr_flags;\n+#define USBD_SHORT_XFER_OK\t0x04\t/* allow short reads */\n+\tint\tucr_actlen;\t\t/* actual length transferred */\n+};\n+\n+struct usb_alt_interface {\n+\tint\tuai_config_index;\n+\tint\tuai_interface_index;\n+\tint\tuai_alt_no;\n+};\n+\n+#define USB_CURRENT_CONFIG_INDEX (-1)\n+#define USB_CURRENT_ALT_INDEX (-1)\n+\n+struct usb_config_desc {\n+\tint\tucd_config_index;\n+\tusb_config_descriptor_t ucd_desc;\n+};\n+\n+struct usb_interface_desc {\n+\tint\tuid_config_index;\n+\tint\tuid_interface_index;\n+\tint\tuid_alt_index;\n+\tusb_interface_descriptor_t uid_desc;\n+};\n+\n+struct usb_endpoint_desc {\n+\tint\tued_config_index;\n+\tint\tued_interface_index;\n+\tint\tued_alt_index;\n+\tint\tued_endpoint_index;\n+\tusb_endpoint_descriptor_t ued_desc;\n+};\n+\n+struct usb_full_desc {\n+\tint\tufd_config_index;\n+\tu_int\tufd_size;\n+\tu_char\t*ufd_data;\n+};\n+\n+struct usb_string_desc {\n+\tint\tusd_string_index;\n+\tint\tusd_language_id;\n+\tusb_string_descriptor_t usd_desc;\n+};\n+\n+struct usb_ctl_report_desc {\n+\tint\tucrd_size;\n+\tu_char\tucrd_data[1024];\t/* filled data size will vary */\n+};\n+\n+typedef struct { u_int32_t cookie; } usb_event_cookie_t;\n+\n+#define USB_MAX_DEVNAMES 4\n+#define USB_MAX_DEVNAMELEN 16\n+struct usb_device_info {\n+\tu_int8_t\tudi_bus;\n+\tu_int8_t\tudi_addr;\t/* device address */\n+\tusb_event_cookie_t udi_cookie;\n+\tchar\t\tudi_product[USB_MAX_STRING_LEN];\n+\tchar\t\tudi_vendor[USB_MAX_STRING_LEN];\n+\tchar\t\tudi_release[8];\n+\tu_int16_t\tudi_productNo;\n+\tu_int16_t\tudi_vendorNo;\n+\tu_int16_t\tudi_releaseNo;\n+\tu_int8_t\tudi_class;\n+\tu_int8_t\tudi_subclass;\n+\tu_int8_t\tudi_protocol;\n+\tu_int8_t\tudi_config;\n+\tu_int8_t\tudi_speed;\n+#define USB_SPEED_UNKNOWN\t0\n+#define USB_SPEED_LOW\t\t1\n+#define USB_SPEED_FULL\t\t2\n+#define USB_SPEED_HIGH\t\t3\n+#define USB_SPEED_VARIABLE\t4\n+#define USB_SPEED_SUPER\t\t5\n+\tint\t\tudi_power;\t/* power consumption in mA, 0 if selfpowered */\n+\tint\t\tudi_nports;\n+\tchar\t\tudi_devnames[USB_MAX_DEVNAMES][USB_MAX_DEVNAMELEN];\n+\tu_int8_t\tudi_ports[16];/* hub only: addresses of devices on ports */\n+#define USB_PORT_ENABLED 0xff\n+#define USB_PORT_SUSPENDED 0xfe\n+#define USB_PORT_POWERED 0xfd\n+#define USB_PORT_DISABLED 0xfc\n+};\n+\n+struct usb_ctl_report {\n+\tint\tucr_report;\n+\tu_char\tucr_data[1024];\t/* filled data size will vary */\n+};\n+\n+struct usb_device_stats {\n+\tu_long\tuds_requests[4];\t/* indexed by transfer type UE_* */\n+};\n+\n+#define WUSB_MIN_IE\t\t\t0x80\n+#define WUSB_WCTA_IE\t\t\t0x80\n+#define WUSB_WCONNECTACK_IE\t\t0x81\n+#define WUSB_WHOSTINFO_IE\t\t0x82\n+#define  WUHI_GET_CA(_bmAttributes_) ((_bmAttributes_) & 0x3)\n+#define   WUHI_CA_RECONN\t\t0x00\n+#define   WUHI_CA_LIMITED\t\t0x01\n+#define   WUHI_CA_ALL\t\t\t0x03\n+#define  WUHI_GET_MLSI(_bmAttributes_) (((_bmAttributes_) & 0x38) >> 3)\n+#define WUSB_WCHCHANGEANNOUNCE_IE\t0x83\n+#define WUSB_WDEV_DISCONNECT_IE\t\t0x84\n+#define WUSB_WHOST_DISCONNECT_IE\t0x85\n+#define WUSB_WRELEASE_CHANNEL_IE\t0x86\n+#define WUSB_WWORK_IE\t\t\t0x87\n+#define WUSB_WCHANNEL_STOP_IE\t\t0x88\n+#define WUSB_WDEV_KEEPALIVE_IE\t\t0x89\n+#define WUSB_WISOCH_DISCARD_IE\t\t0x8A\n+#define WUSB_WRESETDEVICE_IE\t\t0x8B\n+#define WUSB_WXMIT_PACKET_ADJUST_IE\t0x8C\n+#define WUSB_MAX_IE\t\t\t0x8C\n+\n+/* Device Notification Types */\n+\n+#define WUSB_DN_MIN\t\t\t0x01\n+#define WUSB_DN_CONNECT\t\t\t0x01\n+# define WUSB_DA_OLDCONN\t0x00\n+# define WUSB_DA_NEWCONN\t0x01\n+# define WUSB_DA_SELF_BEACON\t0x02\n+# define WUSB_DA_DIR_BEACON\t0x04\n+# define WUSB_DA_NO_BEACON\t0x06\n+#define WUSB_DN_DISCONNECT\t\t0x02\n+#define WUSB_DN_EPRDY\t\t\t0x03\n+#define WUSB_DN_MASAVAILCHANGED\t\t0x04\n+#define WUSB_DN_REMOTEWAKEUP\t\t0x05\n+#define WUSB_DN_SLEEP\t\t\t0x06\n+#define WUSB_DN_ALIVE\t\t\t0x07\n+#define WUSB_DN_MAX\t\t\t0x07\n+\n+#ifdef _MSC_VER\n+#include <pshpack1.h>\n+#endif\n+\n+/* WUSB Handshake Data.  Used during the SET/GET HANDSHAKE requests */\n+typedef struct wusb_hndshk_data {\n+\tuByte bMessageNumber;\n+\tuByte bStatus;\n+\tuByte tTKID[3];\n+\tuByte bReserved;\n+\tuByte CDID[16];\n+\tuByte Nonce[16];\n+\tuByte MIC[8];\n+} UPACKED wusb_hndshk_data_t;\n+#define WUSB_HANDSHAKE_LEN_FOR_MIC\t38\n+\n+/* WUSB Connection Context */\n+typedef struct wusb_conn_context {\n+\tuByte CHID [16];\n+\tuByte CDID [16];\n+\tuByte CK [16];\n+} UPACKED wusb_conn_context_t;\n+\n+/* WUSB Security Descriptor */\n+typedef struct wusb_security_desc {\n+\tuByte bLength;\n+\tuByte bDescriptorType;\n+\tuWord wTotalLength;\n+\tuByte bNumEncryptionTypes;\n+} UPACKED wusb_security_desc_t;\n+\n+/* WUSB Encryption Type Descriptor */\n+typedef struct wusb_encrypt_type_desc {\n+\tuByte bLength;\n+\tuByte bDescriptorType;\n+\n+\tuByte bEncryptionType;\n+#define WUETD_UNSECURE\t\t0\n+#define WUETD_WIRED\t\t1\n+#define WUETD_CCM_1\t\t2\n+#define WUETD_RSA_1\t\t3\n+\n+\tuByte bEncryptionValue;\n+\tuByte bAuthKeyIndex;\n+} UPACKED wusb_encrypt_type_desc_t;\n+\n+/* WUSB Key Descriptor */\n+typedef struct wusb_key_desc {\n+\tuByte bLength;\n+\tuByte bDescriptorType;\n+\tuByte tTKID[3];\n+\tuByte bReserved;\n+\tuByte KeyData[1];\t/* variable length */\n+} UPACKED wusb_key_desc_t;\n+\n+/* WUSB BOS Descriptor (Binary device Object Store) */\n+typedef struct wusb_bos_desc {\n+\tuByte bLength;\n+\tuByte bDescriptorType;\n+\tuWord wTotalLength;\n+\tuByte bNumDeviceCaps;\n+} UPACKED wusb_bos_desc_t;\n+\n+#define USB_DEVICE_CAPABILITY_20_EXTENSION\t0x02\n+typedef struct usb_dev_cap_20_ext_desc {\n+\tuByte bLength;\n+\tuByte bDescriptorType;\n+\tuByte bDevCapabilityType;\n+#define USB_20_EXT_LPM\t\t\t\t0x02\n+\tuDWord bmAttributes;\n+} UPACKED usb_dev_cap_20_ext_desc_t;\n+\n+#define USB_DEVICE_CAPABILITY_SS_USB\t\t0x03\n+typedef struct usb_dev_cap_ss_usb {\n+\tuByte bLength;\n+\tuByte bDescriptorType;\n+\tuByte bDevCapabilityType;\n+#define USB_DC_SS_USB_LTM_CAPABLE\t\t0x02\n+\tuByte bmAttributes;\n+#define USB_DC_SS_USB_SPEED_SUPPORT_LOW\t\t0x01\n+#define USB_DC_SS_USB_SPEED_SUPPORT_FULL\t0x02\n+#define USB_DC_SS_USB_SPEED_SUPPORT_HIGH\t0x04\n+#define USB_DC_SS_USB_SPEED_SUPPORT_SS\t\t0x08\n+\tuWord wSpeedsSupported;\n+\tuByte bFunctionalitySupport;\n+\tuByte bU1DevExitLat;\n+\tuWord wU2DevExitLat;\n+} UPACKED usb_dev_cap_ss_usb_t;\n+\n+#define USB_DEVICE_CAPABILITY_CONTAINER_ID\t0x04\n+typedef struct usb_dev_cap_container_id {\n+\tuByte bLength;\n+\tuByte bDescriptorType;\n+\tuByte bDevCapabilityType;\n+\tuByte bReserved;\n+\tuByte containerID[16];\n+} UPACKED usb_dev_cap_container_id_t;\n+\n+/* Device Capability Type Codes */\n+#define WUSB_DEVICE_CAPABILITY_WIRELESS_USB 0x01\n+\n+/* Device Capability Descriptor */\n+typedef struct wusb_dev_cap_desc {\n+\tuByte bLength;\n+\tuByte bDescriptorType;\n+\tuByte bDevCapabilityType;\n+\tuByte caps[1];\t/* Variable length */\n+} UPACKED wusb_dev_cap_desc_t;\n+\n+/* Device Capability Descriptor */\n+typedef struct wusb_dev_cap_uwb_desc {\n+\tuByte bLength;\n+\tuByte bDescriptorType;\n+\tuByte bDevCapabilityType;\n+\tuByte bmAttributes;\n+\tuWord wPHYRates;\t/* Bitmap */\n+\tuByte bmTFITXPowerInfo;\n+\tuByte bmFFITXPowerInfo;\n+\tuWord bmBandGroup;\n+\tuByte bReserved;\n+} UPACKED wusb_dev_cap_uwb_desc_t;\n+\n+/* Wireless USB Endpoint Companion Descriptor */\n+typedef struct wusb_endpoint_companion_desc {\n+\tuByte bLength;\n+\tuByte bDescriptorType;\n+\tuByte bMaxBurst;\n+\tuByte bMaxSequence;\n+\tuWord wMaxStreamDelay;\n+\tuWord wOverTheAirPacketSize;\n+\tuByte bOverTheAirInterval;\n+\tuByte bmCompAttributes;\n+} UPACKED wusb_endpoint_companion_desc_t;\n+\n+/* Wireless USB Numeric Association M1 Data Structure */\n+typedef struct wusb_m1_data {\n+\tuByte version;\n+\tuWord langId;\n+\tuByte deviceFriendlyNameLength;\n+\tuByte sha_256_m3[32];\n+\tuByte deviceFriendlyName[256];\n+} UPACKED wusb_m1_data_t;\n+\n+typedef struct wusb_m2_data {\n+\tuByte version;\n+\tuWord langId;\n+\tuByte hostFriendlyNameLength;\n+\tuByte pkh[384];\n+\tuByte hostFriendlyName[256];\n+} UPACKED wusb_m2_data_t;\n+\n+typedef struct wusb_m3_data {\n+\tuByte pkd[384];\n+\tuByte nd;\n+} UPACKED wusb_m3_data_t;\n+\n+typedef struct wusb_m4_data {\n+\tuDWord _attributeTypeIdAndLength_1;\n+\tuWord  associationTypeId;\n+\n+\tuDWord _attributeTypeIdAndLength_2;\n+\tuWord  associationSubTypeId;\n+\n+\tuDWord _attributeTypeIdAndLength_3;\n+\tuDWord length;\n+\n+\tuDWord _attributeTypeIdAndLength_4;\n+\tuDWord associationStatus;\n+\n+\tuDWord _attributeTypeIdAndLength_5;\n+\tuByte  chid[16];\n+\n+\tuDWord _attributeTypeIdAndLength_6;\n+\tuByte  cdid[16];\n+\n+\tuDWord _attributeTypeIdAndLength_7;\n+\tuByte  bandGroups[2];\n+} UPACKED wusb_m4_data_t;\n+\n+#ifdef _MSC_VER\n+#include <poppack.h>\n+#endif\n+\n+#ifdef __cplusplus\n+}\n+#endif\n+\n+#endif /* _USB_H_ */\n--- /dev/null\n+++ b/drivers/usb/host/dwc_otg/Makefile\n@@ -0,0 +1,85 @@\n+#\n+# Makefile for DWC_otg Highspeed USB controller driver\n+#\n+\n+ifneq ($(KERNELRELEASE),)\n+\n+# Use the BUS_INTERFACE variable to compile the software for either\n+# PCI(PCI_INTERFACE) or LM(LM_INTERFACE) bus.\n+ifeq ($(BUS_INTERFACE),)\n+#\tBUS_INTERFACE = -DPCI_INTERFACE\n+#\tBUS_INTERFACE = -DLM_INTERFACE\n+        BUS_INTERFACE = -DPLATFORM_INTERFACE\n+endif\n+\n+#ccflags-y\t+= -DDEBUG\n+#ccflags-y\t+= -DDWC_OTG_DEBUGLEV=1 # reduce common debug msgs\n+\n+# Use one of the following flags to compile the software in host-only or\n+# device-only mode.\n+#ccflags-y        += -DDWC_HOST_ONLY\n+#ccflags-y        += -DDWC_DEVICE_ONLY\n+\n+ccflags-y\t+= -Dlinux -DDWC_HS_ELECT_TST\n+#ccflags-y\t+= -DDWC_EN_ISOC\n+ccflags-y   \t+= -I$(srctree)/drivers/usb/host/dwc_common_port\n+#ccflags-y   \t+= -I$(PORTLIB)\n+ccflags-y   \t+= -DDWC_LINUX\n+ccflags-y   \t+= $(CFI)\n+ccflags-y\t+= $(BUS_INTERFACE)\n+#ccflags-y\t+= -DDWC_DEV_SRPCAP\n+\n+obj-$(CONFIG_USB_DWCOTG) += dwc_otg.o\n+\n+dwc_otg-objs\t:= dwc_otg_driver.o dwc_otg_attr.o\n+dwc_otg-objs\t+= dwc_otg_cil.o dwc_otg_cil_intr.o\n+dwc_otg-objs\t+= dwc_otg_pcd_linux.o dwc_otg_pcd.o dwc_otg_pcd_intr.o\n+dwc_otg-objs\t+= dwc_otg_hcd.o dwc_otg_hcd_linux.o dwc_otg_hcd_intr.o dwc_otg_hcd_queue.o dwc_otg_hcd_ddma.o\n+dwc_otg-objs\t+= dwc_otg_adp.o\n+dwc_otg-objs\t+= dwc_otg_fiq_fsm.o\n+ifneq ($(CONFIG_ARM64),y)\n+dwc_otg-objs\t+= dwc_otg_fiq_stub.o\n+endif\n+\n+ifneq ($(CFI),)\n+dwc_otg-objs\t+= dwc_otg_cfi.o\n+endif\n+\n+kernrelwd := $(subst ., ,$(KERNELRELEASE))\n+kernrel3 := $(word 1,$(kernrelwd)).$(word 2,$(kernrelwd)).$(word 3,$(kernrelwd))\n+\n+ifneq ($(kernrel3),2.6.20)\n+ccflags-y += $(CPPFLAGS)\n+endif\n+\n+else\n+\n+PWD\t\t:= $(shell pwd)\n+PORTLIB\t\t:= $(PWD)/../dwc_common_port\n+\n+# Command paths\n+CTAGS\t\t:= $(CTAGS)\n+DOXYGEN\t\t:= $(DOXYGEN)\n+\n+default: portlib\n+\t$(MAKE) -C$(KDIR) M=$(PWD) ARCH=$(ARCH) CROSS_COMPILE=$(CROSS_COMPILE) modules\n+\n+install: default\n+\t$(MAKE) -C$(KDIR) M=$(PORTLIB) modules_install\n+\t$(MAKE) -C$(KDIR) M=$(PWD) modules_install\n+\n+portlib:\n+\t$(MAKE) -C$(KDIR) M=$(PORTLIB) ARCH=$(ARCH) CROSS_COMPILE=$(CROSS_COMPILE) modules\n+\tcp $(PORTLIB)/Module.symvers $(PWD)/\n+\n+docs:\t$(wildcard *.[hc]) doc/doxygen.cfg\n+\t$(DOXYGEN) doc/doxygen.cfg\n+\n+tags:\t$(wildcard *.[hc])\n+\t$(CTAGS) -e $(wildcard *.[hc]) $(wildcard linux/*.[hc]) $(wildcard $(KDIR)/include/linux/usb*.h)\n+\n+\n+clean:\n+\trm -rf   *.o *.ko .*cmd *.mod.c .tmp_versions Module.symvers\n+\n+endif\n--- /dev/null\n+++ b/drivers/usb/host/dwc_otg/doc/doxygen.cfg\n@@ -0,0 +1,224 @@\n+# Doxyfile 1.3.9.1\n+\n+#---------------------------------------------------------------------------\n+# Project related configuration options\n+#---------------------------------------------------------------------------\n+PROJECT_NAME           = \"DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver\"\n+PROJECT_NUMBER         = v3.00a\n+OUTPUT_DIRECTORY       = ./doc/\n+CREATE_SUBDIRS         = NO\n+OUTPUT_LANGUAGE        = English\n+BRIEF_MEMBER_DESC      = YES\n+REPEAT_BRIEF           = YES\n+ABBREVIATE_BRIEF       = \"The $name class\" \\\n+                         \"The $name widget\" \\\n+                         \"The $name file\" \\\n+                         is \\\n+                         provides \\\n+                         specifies \\\n+                         contains \\\n+                         represents \\\n+                         a \\\n+                         an \\\n+                         the\n+ALWAYS_DETAILED_SEC    = NO\n+INLINE_INHERITED_MEMB  = NO\n+FULL_PATH_NAMES        = NO\n+STRIP_FROM_PATH        =\n+STRIP_FROM_INC_PATH    =\n+SHORT_NAMES            = NO\n+JAVADOC_AUTOBRIEF      = YES\n+MULTILINE_CPP_IS_BRIEF = NO\n+INHERIT_DOCS           = YES\n+DISTRIBUTE_GROUP_DOC   = NO\n+TAB_SIZE               = 8\n+ALIASES                =\n+OPTIMIZE_OUTPUT_FOR_C  = YES\n+OPTIMIZE_OUTPUT_JAVA   = NO\n+SUBGROUPING            = YES\n+#---------------------------------------------------------------------------\n+# Build related configuration options\n+#---------------------------------------------------------------------------\n+EXTRACT_ALL            = NO\n+EXTRACT_PRIVATE        = YES\n+EXTRACT_STATIC         = YES\n+EXTRACT_LOCAL_CLASSES  = YES\n+EXTRACT_LOCAL_METHODS  = NO\n+HIDE_UNDOC_MEMBERS     = NO\n+HIDE_UNDOC_CLASSES     = NO\n+HIDE_FRIEND_COMPOUNDS  = NO\n+HIDE_IN_BODY_DOCS      = NO\n+INTERNAL_DOCS          = NO\n+CASE_SENSE_NAMES       = NO\n+HIDE_SCOPE_NAMES       = NO\n+SHOW_INCLUDE_FILES     = YES\n+INLINE_INFO            = YES\n+SORT_MEMBER_DOCS       = NO\n+SORT_BRIEF_DOCS        = NO\n+SORT_BY_SCOPE_NAME     = NO\n+GENERATE_TODOLIST      = YES\n+GENERATE_TESTLIST      = YES\n+GENERATE_BUGLIST       = YES\n+GENERATE_DEPRECATEDLIST= YES\n+ENABLED_SECTIONS       =\n+MAX_INITIALIZER_LINES  = 30\n+SHOW_USED_FILES        = YES\n+SHOW_DIRECTORIES       = YES\n+#---------------------------------------------------------------------------\n+# configuration options related to warning and progress messages\n+#---------------------------------------------------------------------------\n+QUIET                  = YES\n+WARNINGS               = YES\n+WARN_IF_UNDOCUMENTED   = NO\n+WARN_IF_DOC_ERROR      = YES\n+WARN_FORMAT            = \"$file:$line: $text\"\n+WARN_LOGFILE           =\n+#---------------------------------------------------------------------------\n+# configuration options related to the input files\n+#---------------------------------------------------------------------------\n+INPUT                  = .\n+FILE_PATTERNS          = *.c \\\n+                         *.h \\\n+                         ./linux/*.c \\\n+                         ./linux/*.h\n+RECURSIVE              = NO\n+EXCLUDE                = ./test/ \\\n+                         ./dwc_otg/.AppleDouble/\n+EXCLUDE_SYMLINKS       = YES\n+EXCLUDE_PATTERNS       = *.mod.*\n+EXAMPLE_PATH           =\n+EXAMPLE_PATTERNS       = *\n+EXAMPLE_RECURSIVE      = NO\n+IMAGE_PATH             =\n+INPUT_FILTER           =\n+FILTER_PATTERNS        =\n+FILTER_SOURCE_FILES    = NO\n+#---------------------------------------------------------------------------\n+# configuration options related to source browsing\n+#---------------------------------------------------------------------------\n+SOURCE_BROWSER         = YES\n+INLINE_SOURCES         = NO\n+STRIP_CODE_COMMENTS    = YES\n+REFERENCED_BY_RELATION = NO\n+REFERENCES_RELATION    = NO\n+VERBATIM_HEADERS       = NO\n+#---------------------------------------------------------------------------\n+# configuration options related to the alphabetical class index\n+#---------------------------------------------------------------------------\n+ALPHABETICAL_INDEX     = NO\n+COLS_IN_ALPHA_INDEX    = 5\n+IGNORE_PREFIX          =\n+#---------------------------------------------------------------------------\n+# configuration options related to the HTML output\n+#---------------------------------------------------------------------------\n+GENERATE_HTML          = YES\n+HTML_OUTPUT            = html\n+HTML_FILE_EXTENSION    = .html\n+HTML_HEADER            =\n+HTML_FOOTER            =\n+HTML_STYLESHEET        =\n+HTML_ALIGN_MEMBERS     = YES\n+GENERATE_HTMLHELP      = NO\n+CHM_FILE               =\n+HHC_LOCATION           =\n+GENERATE_CHI           = NO\n+BINARY_TOC             = NO\n+TOC_EXPAND             = NO\n+DISABLE_INDEX          = NO\n+ENUM_VALUES_PER_LINE   = 4\n+GENERATE_TREEVIEW      = YES\n+TREEVIEW_WIDTH         = 250\n+#---------------------------------------------------------------------------\n+# configuration options related to the LaTeX output\n+#---------------------------------------------------------------------------\n+GENERATE_LATEX         = NO\n+LATEX_OUTPUT           = latex\n+LATEX_CMD_NAME         = latex\n+MAKEINDEX_CMD_NAME     = makeindex\n+COMPACT_LATEX          = NO\n+PAPER_TYPE             = a4wide\n+EXTRA_PACKAGES         =\n+LATEX_HEADER           =\n+PDF_HYPERLINKS         = NO\n+USE_PDFLATEX           = NO\n+LATEX_BATCHMODE        = NO\n+LATEX_HIDE_INDICES     = NO\n+#---------------------------------------------------------------------------\n+# configuration options related to the RTF output\n+#---------------------------------------------------------------------------\n+GENERATE_RTF           = NO\n+RTF_OUTPUT             = rtf\n+COMPACT_RTF            = NO\n+RTF_HYPERLINKS         = NO\n+RTF_STYLESHEET_FILE    =\n+RTF_EXTENSIONS_FILE    =\n+#---------------------------------------------------------------------------\n+# configuration options related to the man page output\n+#---------------------------------------------------------------------------\n+GENERATE_MAN           = NO\n+MAN_OUTPUT             = man\n+MAN_EXTENSION          = .3\n+MAN_LINKS              = NO\n+#---------------------------------------------------------------------------\n+# configuration options related to the XML output\n+#---------------------------------------------------------------------------\n+GENERATE_XML           = NO\n+XML_OUTPUT             = xml\n+XML_SCHEMA             =\n+XML_DTD                =\n+XML_PROGRAMLISTING     = YES\n+#---------------------------------------------------------------------------\n+# configuration options for the AutoGen Definitions output\n+#---------------------------------------------------------------------------\n+GENERATE_AUTOGEN_DEF   = NO\n+#---------------------------------------------------------------------------\n+# configuration options related to the Perl module output\n+#---------------------------------------------------------------------------\n+GENERATE_PERLMOD       = NO\n+PERLMOD_LATEX          = NO\n+PERLMOD_PRETTY         = YES\n+PERLMOD_MAKEVAR_PREFIX =\n+#---------------------------------------------------------------------------\n+# Configuration options related to the preprocessor\n+#---------------------------------------------------------------------------\n+ENABLE_PREPROCESSING   = YES\n+MACRO_EXPANSION        = YES\n+EXPAND_ONLY_PREDEF     = YES\n+SEARCH_INCLUDES        = YES\n+INCLUDE_PATH           =\n+INCLUDE_FILE_PATTERNS  =\n+PREDEFINED             = DEVICE_ATTR DWC_EN_ISOC\n+EXPAND_AS_DEFINED      = DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW DWC_OTG_DEVICE_ATTR_BITFIELD_STORE DWC_OTG_DEVICE_ATTR_BITFIELD_RW DWC_OTG_DEVICE_ATTR_BITFIELD_RO DWC_OTG_DEVICE_ATTR_REG_SHOW DWC_OTG_DEVICE_ATTR_REG_STORE DWC_OTG_DEVICE_ATTR_REG32_RW DWC_OTG_DEVICE_ATTR_REG32_RO DWC_EN_ISOC\n+SKIP_FUNCTION_MACROS   = NO\n+#---------------------------------------------------------------------------\n+# Configuration::additions related to external references\n+#---------------------------------------------------------------------------\n+TAGFILES               =\n+GENERATE_TAGFILE       =\n+ALLEXTERNALS           = NO\n+EXTERNAL_GROUPS        = YES\n+PERL_PATH              = /usr/bin/perl\n+#---------------------------------------------------------------------------\n+# Configuration options related to the dot tool\n+#---------------------------------------------------------------------------\n+CLASS_DIAGRAMS         = YES\n+HIDE_UNDOC_RELATIONS   = YES\n+HAVE_DOT               = NO\n+CLASS_GRAPH            = YES\n+COLLABORATION_GRAPH    = YES\n+UML_LOOK               = NO\n+TEMPLATE_RELATIONS     = NO\n+INCLUDE_GRAPH          = YES\n+INCLUDED_BY_GRAPH      = YES\n+CALL_GRAPH             = NO\n+GRAPHICAL_HIERARCHY    = YES\n+DOT_IMAGE_FORMAT       = png\n+DOT_PATH               =\n+DOTFILE_DIRS           =\n+MAX_DOT_GRAPH_DEPTH    = 1000\n+GENERATE_LEGEND        = YES\n+DOT_CLEANUP            = YES\n+#---------------------------------------------------------------------------\n+# Configuration::additions related to the search engine\n+#---------------------------------------------------------------------------\n+SEARCHENGINE           = NO\n--- /dev/null\n+++ b/drivers/usb/host/dwc_otg/dummy_audio.c\n@@ -0,0 +1,1574 @@\n+/*\n+ * zero.c -- Gadget Zero, for USB development\n+ *\n+ * Copyright (C) 2003-2004 David Brownell\n+ * All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ * 1. Redistributions of source code must retain the above copyright\n+ *    notice, this list of conditions, and the following disclaimer,\n+ *    without modification.\n+ * 2. Redistributions in binary form must reproduce the above copyright\n+ *    notice, this list of conditions and the following disclaimer in the\n+ *    documentation and/or other materials provided with the distribution.\n+ * 3. The names of the above-listed copyright holders may not be used\n+ *    to endorse or promote products derived from this software without\n+ *    specific prior written permission.\n+ *\n+ * ALTERNATIVELY, this software may be distributed under the terms of the\n+ * GNU General Public License (\"GPL\") as published by the Free Software\n+ * Foundation, either version 2 of that License or (at your option) any\n+ * later version.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS\n+ * IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,\n+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\n+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR\n+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\n+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\n+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR\n+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\n+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\n+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+\n+/*\n+ * Gadget Zero only needs two bulk endpoints, and is an example of how you\n+ * can write a hardware-agnostic gadget driver running inside a USB device.\n+ *\n+ * Hardware details are visible (see CONFIG_USB_ZERO_* below) but don't\n+ * affect most of the driver.\n+ *\n+ * Use it with the Linux host/master side \"usbtest\" driver to get a basic\n+ * functional test of your device-side usb stack, or with \"usb-skeleton\".\n+ *\n+ * It supports two similar configurations.  One sinks whatever the usb host\n+ * writes, and in return sources zeroes.  The other loops whatever the host\n+ * writes back, so the host can read it.  Module options include:\n+ *\n+ *   buflen=N\t\tdefault N=4096, buffer size used\n+ *   qlen=N\t\tdefault N=32, how many buffers in the loopback queue\n+ *   loopdefault\tdefault false, list loopback config first\n+ *\n+ * Many drivers will only have one configuration, letting them be much\n+ * simpler if they also don't support high speed operation (like this\n+ * driver does).\n+ */\n+\n+#include <linux/config.h>\n+#include <linux/module.h>\n+#include <linux/kernel.h>\n+#include <linux/delay.h>\n+#include <linux/ioport.h>\n+#include <linux/sched.h>\n+#include <linux/slab.h>\n+#include <linux/smp_lock.h>\n+#include <linux/errno.h>\n+#include <linux/init.h>\n+#include <linux/timer.h>\n+#include <linux/list.h>\n+#include <linux/interrupt.h>\n+#include <linux/uts.h>\n+#include <linux/version.h>\n+#include <linux/device.h>\n+#include <linux/moduleparam.h>\n+#include <linux/proc_fs.h>\n+\n+#include <asm/byteorder.h>\n+#include <asm/io.h>\n+#include <asm/irq.h>\n+#include <asm/system.h>\n+#include <asm/unaligned.h>\n+\n+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,21)\n+# include <linux/usb/ch9.h>\n+#else\n+# include <linux/usb_ch9.h>\n+#endif\n+\n+#include <linux/usb_gadget.h>\n+\n+\n+/*-------------------------------------------------------------------------*/\n+/*-------------------------------------------------------------------------*/\n+\n+\n+static int utf8_to_utf16le(const char *s, u16 *cp, unsigned len)\n+{\n+\tint\tcount = 0;\n+\tu8\tc;\n+\tu16\tuchar;\n+\n+\t/* this insists on correct encodings, though not minimal ones.\n+\t * BUT it currently rejects legit 4-byte UTF-8 code points,\n+\t * which need surrogate pairs.  (Unicode 3.1 can use them.)\n+\t */\n+\twhile (len != 0 && (c = (u8) *s++) != 0) {\n+\t\tif (unlikely(c & 0x80)) {\n+\t\t\t// 2-byte sequence:\n+\t\t\t// 00000yyyyyxxxxxx = 110yyyyy 10xxxxxx\n+\t\t\tif ((c & 0xe0) == 0xc0) {\n+\t\t\t\tuchar = (c & 0x1f) << 6;\n+\n+\t\t\t\tc = (u8) *s++;\n+\t\t\t\tif ((c & 0xc0) != 0xc0)\n+\t\t\t\t\tgoto fail;\n+\t\t\t\tc &= 0x3f;\n+\t\t\t\tuchar |= c;\n+\n+\t\t\t// 3-byte sequence (most CJKV characters):\n+\t\t\t// zzzzyyyyyyxxxxxx = 1110zzzz 10yyyyyy 10xxxxxx\n+\t\t\t} else if ((c & 0xf0) == 0xe0) {\n+\t\t\t\tuchar = (c & 0x0f) << 12;\n+\n+\t\t\t\tc = (u8) *s++;\n+\t\t\t\tif ((c & 0xc0) != 0xc0)\n+\t\t\t\t\tgoto fail;\n+\t\t\t\tc &= 0x3f;\n+\t\t\t\tuchar |= c << 6;\n+\n+\t\t\t\tc = (u8) *s++;\n+\t\t\t\tif ((c & 0xc0) != 0xc0)\n+\t\t\t\t\tgoto fail;\n+\t\t\t\tc &= 0x3f;\n+\t\t\t\tuchar |= c;\n+\n+\t\t\t\t/* no bogus surrogates */\n+\t\t\t\tif (0xd800 <= uchar && uchar <= 0xdfff)\n+\t\t\t\t\tgoto fail;\n+\n+\t\t\t// 4-byte sequence (surrogate pairs, currently rare):\n+\t\t\t// 11101110wwwwzzzzyy + 110111yyyyxxxxxx\n+\t\t\t//     = 11110uuu 10uuzzzz 10yyyyyy 10xxxxxx\n+\t\t\t// (uuuuu = wwww + 1)\n+\t\t\t// FIXME accept the surrogate code points (only)\n+\n+\t\t\t} else\n+\t\t\t\tgoto fail;\n+\t\t} else\n+\t\t\tuchar = c;\n+\t\tput_unaligned (cpu_to_le16 (uchar), cp++);\n+\t\tcount++;\n+\t\tlen--;\n+\t}\n+\treturn count;\n+fail:\n+\treturn -1;\n+}\n+\n+\n+/**\n+ * usb_gadget_get_string - fill out a string descriptor\n+ * @table: of c strings encoded using UTF-8\n+ * @id: string id, from low byte of wValue in get string descriptor\n+ * @buf: at least 256 bytes\n+ *\n+ * Finds the UTF-8 string matching the ID, and converts it into a\n+ * string descriptor in utf16-le.\n+ * Returns length of descriptor (always even) or negative errno\n+ *\n+ * If your driver needs stings in multiple languages, you'll probably\n+ * \"switch (wIndex) { ... }\"  in your ep0 string descriptor logic,\n+ * using this routine after choosing which set of UTF-8 strings to use.\n+ * Note that US-ASCII is a strict subset of UTF-8; any string bytes with\n+ * the eighth bit set will be multibyte UTF-8 characters, not ISO-8859/1\n+ * characters (which are also widely used in C strings).\n+ */\n+int\n+usb_gadget_get_string (struct usb_gadget_strings *table, int id, u8 *buf)\n+{\n+\tstruct usb_string\t*s;\n+\tint\t\t\tlen;\n+\n+\t/* descriptor 0 has the language id */\n+\tif (id == 0) {\n+\t\tbuf [0] = 4;\n+\t\tbuf [1] = USB_DT_STRING;\n+\t\tbuf [2] = (u8) table->language;\n+\t\tbuf [3] = (u8) (table->language >> 8);\n+\t\treturn 4;\n+\t}\n+\tfor (s = table->strings; s && s->s; s++)\n+\t\tif (s->id == id)\n+\t\t\tbreak;\n+\n+\t/* unrecognized: stall. */\n+\tif (!s || !s->s)\n+\t\treturn -EINVAL;\n+\n+\t/* string descriptors have length, tag, then UTF16-LE text */\n+\tlen = min ((size_t) 126, strlen (s->s));\n+\tmemset (buf + 2, 0, 2 * len);\t/* zero all the bytes */\n+\tlen = utf8_to_utf16le(s->s, (u16 *)&buf[2], len);\n+\tif (len < 0)\n+\t\treturn -EINVAL;\n+\tbuf [0] = (len + 1) * 2;\n+\tbuf [1] = USB_DT_STRING;\n+\treturn buf [0];\n+}\n+\n+\n+/*-------------------------------------------------------------------------*/\n+/*-------------------------------------------------------------------------*/\n+\n+\n+/**\n+ * usb_descriptor_fillbuf - fill buffer with descriptors\n+ * @buf: Buffer to be filled\n+ * @buflen: Size of buf\n+ * @src: Array of descriptor pointers, terminated by null pointer.\n+ *\n+ * Copies descriptors into the buffer, returning the length or a\n+ * negative error code if they can't all be copied.  Useful when\n+ * assembling descriptors for an associated set of interfaces used\n+ * as part of configuring a composite device; or in other cases where\n+ * sets of descriptors need to be marshaled.\n+ */\n+int\n+usb_descriptor_fillbuf(void *buf, unsigned buflen,\n+\t\tconst struct usb_descriptor_header **src)\n+{\n+\tu8\t*dest = buf;\n+\n+\tif (!src)\n+\t\treturn -EINVAL;\n+\n+\t/* fill buffer from src[] until null descriptor ptr */\n+\tfor (; 0 != *src; src++) {\n+\t\tunsigned\t\tlen = (*src)->bLength;\n+\n+\t\tif (len > buflen)\n+\t\t\treturn -EINVAL;\n+\t\tmemcpy(dest, *src, len);\n+\t\tbuflen -= len;\n+\t\tdest += len;\n+\t}\n+\treturn dest - (u8 *)buf;\n+}\n+\n+\n+/**\n+ * usb_gadget_config_buf - builts a complete configuration descriptor\n+ * @config: Header for the descriptor, including characteristics such\n+ *\tas power requirements and number of interfaces.\n+ * @desc: Null-terminated vector of pointers to the descriptors (interface,\n+ *\tendpoint, etc) defining all functions in this device configuration.\n+ * @buf: Buffer for the resulting configuration descriptor.\n+ * @length: Length of buffer.  If this is not big enough to hold the\n+ *\tentire configuration descriptor, an error code will be returned.\n+ *\n+ * This copies descriptors into the response buffer, building a descriptor\n+ * for that configuration.  It returns the buffer length or a negative\n+ * status code.  The config.wTotalLength field is set to match the length\n+ * of the result, but other descriptor fields (including power usage and\n+ * interface count) must be set by the caller.\n+ *\n+ * Gadget drivers could use this when constructing a config descriptor\n+ * in response to USB_REQ_GET_DESCRIPTOR.  They will need to patch the\n+ * resulting bDescriptorType value if USB_DT_OTHER_SPEED_CONFIG is needed.\n+ */\n+int usb_gadget_config_buf(\n+\tconst struct usb_config_descriptor\t*config,\n+\tvoid\t\t\t\t\t*buf,\n+\tunsigned\t\t\t\tlength,\n+\tconst struct usb_descriptor_header\t**desc\n+)\n+{\n+\tstruct usb_config_descriptor\t\t*cp = buf;\n+\tint\t\t\t\t\tlen;\n+\n+\t/* config descriptor first */\n+\tif (length < USB_DT_CONFIG_SIZE || !desc)\n+\t\treturn -EINVAL;\n+\t*cp = *config;\n+\n+\t/* then interface/endpoint/class/vendor/... */\n+\tlen = usb_descriptor_fillbuf(USB_DT_CONFIG_SIZE + (u8*)buf,\n+\t\t\tlength - USB_DT_CONFIG_SIZE, desc);\n+\tif (len < 0)\n+\t\treturn len;\n+\tlen += USB_DT_CONFIG_SIZE;\n+\tif (len > 0xffff)\n+\t\treturn -EINVAL;\n+\n+\t/* patch up the config descriptor */\n+\tcp->bLength = USB_DT_CONFIG_SIZE;\n+\tcp->bDescriptorType = USB_DT_CONFIG;\n+\tcp->wTotalLength = cpu_to_le16(len);\n+\tcp->bmAttributes |= USB_CONFIG_ATT_ONE;\n+\treturn len;\n+}\n+\n+/*-------------------------------------------------------------------------*/\n+/*-------------------------------------------------------------------------*/\n+\n+\n+#define RBUF_LEN (1024*1024)\n+static int rbuf_start;\n+static int rbuf_len;\n+static __u8 rbuf[RBUF_LEN];\n+\n+/*-------------------------------------------------------------------------*/\n+\n+#define DRIVER_VERSION\t\t\"St Patrick's Day 2004\"\n+\n+static const char shortname [] = \"zero\";\n+static const char longname [] = \"YAMAHA YST-MS35D USB Speaker  \";\n+\n+static const char source_sink [] = \"source and sink data\";\n+static const char loopback [] = \"loop input to output\";\n+\n+/*-------------------------------------------------------------------------*/\n+\n+/*\n+ * driver assumes self-powered hardware, and\n+ * has no way for users to trigger remote wakeup.\n+ *\n+ * this version autoconfigures as much as possible,\n+ * which is reasonable for most \"bulk-only\" drivers.\n+ */\n+static const char *EP_IN_NAME;\t\t/* source */\n+static const char *EP_OUT_NAME;\t\t/* sink */\n+\n+/*-------------------------------------------------------------------------*/\n+\n+/* big enough to hold our biggest descriptor */\n+#define USB_BUFSIZ\t512\n+\n+struct zero_dev {\n+\tspinlock_t\t\tlock;\n+\tstruct usb_gadget\t*gadget;\n+\tstruct usb_request\t*req;\t\t/* for control responses */\n+\n+\t/* when configured, we have one of two configs:\n+\t * - source data (in to host) and sink it (out from host)\n+\t * - or loop it back (out from host back in to host)\n+\t */\n+\tu8\t\t\tconfig;\n+\tstruct usb_ep\t\t*in_ep, *out_ep;\n+\n+\t/* autoresume timer */\n+\tstruct timer_list\tresume;\n+};\n+\n+#define xprintk(d,level,fmt,args...) \\\n+\tdev_printk(level , &(d)->gadget->dev , fmt , ## args)\n+\n+#ifdef DEBUG\n+#define DBG(dev,fmt,args...) \\\n+\txprintk(dev , KERN_DEBUG , fmt , ## args)\n+#else\n+#define DBG(dev,fmt,args...) \\\n+\tdo { } while (0)\n+#endif /* DEBUG */\n+\n+#ifdef VERBOSE\n+#define VDBG\tDBG\n+#else\n+#define VDBG(dev,fmt,args...) \\\n+\tdo { } while (0)\n+#endif /* VERBOSE */\n+\n+#define ERROR(dev,fmt,args...) \\\n+\txprintk(dev , KERN_ERR , fmt , ## args)\n+#define WARN(dev,fmt,args...) \\\n+\txprintk(dev , KERN_WARNING , fmt , ## args)\n+#define INFO(dev,fmt,args...) \\\n+\txprintk(dev , KERN_INFO , fmt , ## args)\n+\n+/*-------------------------------------------------------------------------*/\n+\n+static unsigned buflen = 4096;\n+static unsigned qlen = 32;\n+static unsigned pattern = 0;\n+\n+module_param (buflen, uint, S_IRUGO|S_IWUSR);\n+module_param (qlen, uint, S_IRUGO|S_IWUSR);\n+module_param (pattern, uint, S_IRUGO|S_IWUSR);\n+\n+/*\n+ * if it's nonzero, autoresume says how many seconds to wait\n+ * before trying to wake up the host after suspend.\n+ */\n+static unsigned autoresume = 0;\n+module_param (autoresume, uint, 0);\n+\n+/*\n+ * Normally the \"loopback\" configuration is second (index 1) so\n+ * it's not the default.  Here's where to change that order, to\n+ * work better with hosts where config changes are problematic.\n+ * Or controllers (like superh) that only support one config.\n+ */\n+static int loopdefault = 0;\n+\n+module_param (loopdefault, bool, S_IRUGO|S_IWUSR);\n+\n+/*-------------------------------------------------------------------------*/\n+\n+/* Thanks to NetChip Technologies for donating this product ID.\n+ *\n+ * DO NOT REUSE THESE IDs with a protocol-incompatible driver!!  Ever!!\n+ * Instead:  allocate your own, using normal USB-IF procedures.\n+ */\n+#ifndef\tCONFIG_USB_ZERO_HNPTEST\n+#define DRIVER_VENDOR_NUM\t0x0525\t\t/* NetChip */\n+#define DRIVER_PRODUCT_NUM\t0xa4a0\t\t/* Linux-USB \"Gadget Zero\" */\n+#else\n+#define DRIVER_VENDOR_NUM\t0x1a0a\t\t/* OTG test device IDs */\n+#define DRIVER_PRODUCT_NUM\t0xbadd\n+#endif\n+\n+/*-------------------------------------------------------------------------*/\n+\n+/*\n+ * DESCRIPTORS ... most are static, but strings and (full)\n+ * configuration descriptors are built on demand.\n+ */\n+\n+/*\n+#define STRING_MANUFACTURER\t\t25\n+#define STRING_PRODUCT\t\t\t42\n+#define STRING_SERIAL\t\t\t101\n+*/\n+#define STRING_MANUFACTURER\t\t1\n+#define STRING_PRODUCT\t\t\t2\n+#define STRING_SERIAL\t\t\t3\n+\n+#define STRING_SOURCE_SINK\t\t250\n+#define STRING_LOOPBACK\t\t\t251\n+\n+/*\n+ * This device advertises two configurations; these numbers work\n+ * on a pxa250 as well as more flexible hardware.\n+ */\n+#define\tCONFIG_SOURCE_SINK\t3\n+#define\tCONFIG_LOOPBACK\t\t2\n+\n+/*\n+static struct usb_device_descriptor\n+device_desc = {\n+\t.bLength =\t\tsizeof device_desc,\n+\t.bDescriptorType =\tUSB_DT_DEVICE,\n+\n+\t.bcdUSB =\t\t__constant_cpu_to_le16 (0x0200),\n+\t.bDeviceClass =\t\tUSB_CLASS_VENDOR_SPEC,\n+\n+\t.idVendor =\t\t__constant_cpu_to_le16 (DRIVER_VENDOR_NUM),\n+\t.idProduct =\t\t__constant_cpu_to_le16 (DRIVER_PRODUCT_NUM),\n+\t.iManufacturer =\tSTRING_MANUFACTURER,\n+\t.iProduct =\t\tSTRING_PRODUCT,\n+\t.iSerialNumber =\tSTRING_SERIAL,\n+\t.bNumConfigurations =\t2,\n+};\n+*/\n+static struct usb_device_descriptor\n+device_desc = {\n+\t.bLength =\t\tsizeof device_desc,\n+\t.bDescriptorType =\tUSB_DT_DEVICE,\n+\t.bcdUSB =\t\t__constant_cpu_to_le16 (0x0100),\n+\t.bDeviceClass =\t\tUSB_CLASS_PER_INTERFACE,\n+\t.bDeviceSubClass =      0,\n+\t.bDeviceProtocol =      0,\n+\t.bMaxPacketSize0 =      64,\n+\t.bcdDevice =            __constant_cpu_to_le16 (0x0100),\n+\t.idVendor =\t\t__constant_cpu_to_le16 (0x0499),\n+\t.idProduct =\t\t__constant_cpu_to_le16 (0x3002),\n+\t.iManufacturer =\tSTRING_MANUFACTURER,\n+\t.iProduct =\t\tSTRING_PRODUCT,\n+\t.iSerialNumber =\tSTRING_SERIAL,\n+\t.bNumConfigurations =\t1,\n+};\n+\n+static struct usb_config_descriptor\n+z_config = {\n+\t.bLength =\t\tsizeof z_config,\n+\t.bDescriptorType =\tUSB_DT_CONFIG,\n+\n+\t/* compute wTotalLength on the fly */\n+\t.bNumInterfaces =\t2,\n+\t.bConfigurationValue =\t1,\n+\t.iConfiguration =\t0,\n+\t.bmAttributes =\t\t0x40,\n+\t.bMaxPower =\t\t0,\t/* self-powered */\n+};\n+\n+\n+static struct usb_otg_descriptor\n+otg_descriptor = {\n+\t.bLength =\t\tsizeof otg_descriptor,\n+\t.bDescriptorType =\tUSB_DT_OTG,\n+\n+\t.bmAttributes =\t\tUSB_OTG_SRP,\n+};\n+\n+/* one interface in each configuration */\n+#ifdef\tCONFIG_USB_GADGET_DUALSPEED\n+\n+/*\n+ * usb 2.0 devices need to expose both high speed and full speed\n+ * descriptors, unless they only run at full speed.\n+ *\n+ * that means alternate endpoint descriptors (bigger packets)\n+ * and a \"device qualifier\" ... plus more construction options\n+ * for the config descriptor.\n+ */\n+\n+static struct usb_qualifier_descriptor\n+dev_qualifier = {\n+\t.bLength =\t\tsizeof dev_qualifier,\n+\t.bDescriptorType =\tUSB_DT_DEVICE_QUALIFIER,\n+\n+\t.bcdUSB =\t\t__constant_cpu_to_le16 (0x0200),\n+\t.bDeviceClass =\t\tUSB_CLASS_VENDOR_SPEC,\n+\n+\t.bNumConfigurations =\t2,\n+};\n+\n+\n+struct usb_cs_as_general_descriptor {\n+\t__u8  bLength;\n+\t__u8  bDescriptorType;\n+\n+\t__u8  bDescriptorSubType;\n+\t__u8  bTerminalLink;\n+\t__u8  bDelay;\n+\t__u16  wFormatTag;\n+} __attribute__ ((packed));\n+\n+struct usb_cs_as_format_descriptor {\n+\t__u8  bLength;\n+\t__u8  bDescriptorType;\n+\n+\t__u8  bDescriptorSubType;\n+\t__u8  bFormatType;\n+\t__u8  bNrChannels;\n+\t__u8  bSubframeSize;\n+\t__u8  bBitResolution;\n+\t__u8  bSamfreqType;\n+\t__u8  tLowerSamFreq[3];\n+\t__u8  tUpperSamFreq[3];\n+} __attribute__ ((packed));\n+\n+static const struct usb_interface_descriptor\n+z_audio_control_if_desc = {\n+\t.bLength =\t\tsizeof z_audio_control_if_desc,\n+\t.bDescriptorType =\tUSB_DT_INTERFACE,\n+\t.bInterfaceNumber = 0,\n+\t.bAlternateSetting = 0,\n+\t.bNumEndpoints = 0,\n+\t.bInterfaceClass = USB_CLASS_AUDIO,\n+\t.bInterfaceSubClass = 0x1,\n+\t.bInterfaceProtocol = 0,\n+\t.iInterface = 0,\n+};\n+\n+static const struct usb_interface_descriptor\n+z_audio_if_desc = {\n+\t.bLength =\t\tsizeof z_audio_if_desc,\n+\t.bDescriptorType =\tUSB_DT_INTERFACE,\n+\t.bInterfaceNumber = 1,\n+\t.bAlternateSetting = 0,\n+\t.bNumEndpoints = 0,\n+\t.bInterfaceClass = USB_CLASS_AUDIO,\n+\t.bInterfaceSubClass = 0x2,\n+\t.bInterfaceProtocol = 0,\n+\t.iInterface = 0,\n+};\n+\n+static const struct usb_interface_descriptor\n+z_audio_if_desc2 = {\n+\t.bLength =\t\tsizeof z_audio_if_desc,\n+\t.bDescriptorType =\tUSB_DT_INTERFACE,\n+\t.bInterfaceNumber = 1,\n+\t.bAlternateSetting = 1,\n+\t.bNumEndpoints = 1,\n+\t.bInterfaceClass = USB_CLASS_AUDIO,\n+\t.bInterfaceSubClass = 0x2,\n+\t.bInterfaceProtocol = 0,\n+\t.iInterface = 0,\n+};\n+\n+static const struct usb_cs_as_general_descriptor\n+z_audio_cs_as_if_desc = {\n+\t.bLength = 7,\n+\t.bDescriptorType = 0x24,\n+\n+\t.bDescriptorSubType = 0x01,\n+\t.bTerminalLink = 0x01,\n+\t.bDelay = 0x0,\n+\t.wFormatTag = __constant_cpu_to_le16 (0x0001)\n+};\n+\n+\n+static const struct usb_cs_as_format_descriptor\n+z_audio_cs_as_format_desc = {\n+\t.bLength = 0xe,\n+\t.bDescriptorType = 0x24,\n+\n+\t.bDescriptorSubType = 2,\n+\t.bFormatType = 1,\n+\t.bNrChannels = 1,\n+\t.bSubframeSize = 1,\n+\t.bBitResolution = 8,\n+\t.bSamfreqType = 0,\n+\t.tLowerSamFreq = {0x7e, 0x13, 0x00},\n+\t.tUpperSamFreq = {0xe2, 0xd6, 0x00},\n+};\n+\n+static const struct usb_endpoint_descriptor\n+z_iso_ep = {\n+\t.bLength = 0x09,\n+\t.bDescriptorType = 0x05,\n+\t.bEndpointAddress = 0x04,\n+\t.bmAttributes = 0x09,\n+\t.wMaxPacketSize = 0x0038,\n+\t.bInterval = 0x01,\n+\t.bRefresh = 0x00,\n+\t.bSynchAddress = 0x00,\n+};\n+\n+static char z_iso_ep2[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02};\n+\n+// 9 bytes\n+static char z_ac_interface_header_desc[] =\n+{ 0x09, 0x24, 0x01, 0x00, 0x01, 0x2b, 0x00, 0x01, 0x01 };\n+\n+// 12 bytes\n+static char z_0[] = {0x0c, 0x24, 0x02, 0x01, 0x01, 0x01, 0x00, 0x02,\n+\t\t     0x03, 0x00, 0x00, 0x00};\n+// 13 bytes\n+static char z_1[] = {0x0d, 0x24, 0x06, 0x02, 0x01, 0x02, 0x15, 0x00,\n+\t\t     0x02, 0x00, 0x02, 0x00, 0x00};\n+// 9 bytes\n+static char z_2[] = {0x09, 0x24, 0x03, 0x03, 0x01, 0x03, 0x00, 0x02,\n+\t\t     0x00};\n+\n+static char za_0[] = {0x09, 0x04, 0x01, 0x02, 0x01, 0x01, 0x02, 0x00,\n+\t\t      0x00};\n+\n+static char za_1[] = {0x07, 0x24, 0x01, 0x01, 0x00, 0x01, 0x00};\n+\n+static char za_2[] = {0x0e, 0x24, 0x02, 0x01, 0x02, 0x01, 0x08, 0x00,\n+\t\t      0x7e, 0x13, 0x00, 0xe2, 0xd6, 0x00};\n+\n+static char za_3[] = {0x09, 0x05, 0x04, 0x09, 0x70, 0x00, 0x01, 0x00,\n+\t\t      0x00};\n+\n+static char za_4[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02};\n+\n+static char za_5[] = {0x09, 0x04, 0x01, 0x03, 0x01, 0x01, 0x02, 0x00,\n+\t\t      0x00};\n+\n+static char za_6[] = {0x07, 0x24, 0x01, 0x01, 0x00, 0x01, 0x00};\n+\n+static char za_7[] = {0x0e, 0x24, 0x02, 0x01, 0x01, 0x02, 0x10, 0x00,\n+\t\t      0x7e, 0x13, 0x00, 0xe2, 0xd6, 0x00};\n+\n+static char za_8[] = {0x09, 0x05, 0x04, 0x09, 0x70, 0x00, 0x01, 0x00,\n+\t\t      0x00};\n+\n+static char za_9[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02};\n+\n+static char za_10[] = {0x09, 0x04, 0x01, 0x04, 0x01, 0x01, 0x02, 0x00,\n+\t\t       0x00};\n+\n+static char za_11[] = {0x07, 0x24, 0x01, 0x01, 0x00, 0x01, 0x00};\n+\n+static char za_12[] = {0x0e, 0x24, 0x02, 0x01, 0x02, 0x02, 0x10, 0x00,\n+\t\t       0x73, 0x13, 0x00, 0xe2, 0xd6, 0x00};\n+\n+static char za_13[] = {0x09, 0x05, 0x04, 0x09, 0xe0, 0x00, 0x01, 0x00,\n+\t\t       0x00};\n+\n+static char za_14[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02};\n+\n+static char za_15[] = {0x09, 0x04, 0x01, 0x05, 0x01, 0x01, 0x02, 0x00,\n+\t\t       0x00};\n+\n+static char za_16[] = {0x07, 0x24, 0x01, 0x01, 0x00, 0x01, 0x00};\n+\n+static char za_17[] = {0x0e, 0x24, 0x02, 0x01, 0x01, 0x03, 0x14, 0x00,\n+\t\t       0x7e, 0x13, 0x00, 0xe2, 0xd6, 0x00};\n+\n+static char za_18[] = {0x09, 0x05, 0x04, 0x09, 0xa8, 0x00, 0x01, 0x00,\n+\t\t       0x00};\n+\n+static char za_19[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02};\n+\n+static char za_20[] = {0x09, 0x04, 0x01, 0x06, 0x01, 0x01, 0x02, 0x00,\n+\t\t       0x00};\n+\n+static char za_21[] = {0x07, 0x24, 0x01, 0x01, 0x00, 0x01, 0x00};\n+\n+static char za_22[] = {0x0e, 0x24, 0x02, 0x01, 0x02, 0x03, 0x14, 0x00,\n+\t\t       0x7e, 0x13, 0x00, 0xe2, 0xd6, 0x00};\n+\n+static char za_23[] = {0x09, 0x05, 0x04, 0x09, 0x50, 0x01, 0x01, 0x00,\n+\t\t       0x00};\n+\n+static char za_24[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02};\n+\n+\n+\n+static const struct usb_descriptor_header *z_function [] = {\n+\t(struct usb_descriptor_header *) &z_audio_control_if_desc,\n+\t(struct usb_descriptor_header *) &z_ac_interface_header_desc,\n+\t(struct usb_descriptor_header *) &z_0,\n+\t(struct usb_descriptor_header *) &z_1,\n+\t(struct usb_descriptor_header *) &z_2,\n+\t(struct usb_descriptor_header *) &z_audio_if_desc,\n+\t(struct usb_descriptor_header *) &z_audio_if_desc2,\n+\t(struct usb_descriptor_header *) &z_audio_cs_as_if_desc,\n+\t(struct usb_descriptor_header *) &z_audio_cs_as_format_desc,\n+\t(struct usb_descriptor_header *) &z_iso_ep,\n+\t(struct usb_descriptor_header *) &z_iso_ep2,\n+\t(struct usb_descriptor_header *) &za_0,\n+\t(struct usb_descriptor_header *) &za_1,\n+\t(struct usb_descriptor_header *) &za_2,\n+\t(struct usb_descriptor_header *) &za_3,\n+\t(struct usb_descriptor_header *) &za_4,\n+\t(struct usb_descriptor_header *) &za_5,\n+\t(struct usb_descriptor_header *) &za_6,\n+\t(struct usb_descriptor_header *) &za_7,\n+\t(struct usb_descriptor_header *) &za_8,\n+\t(struct usb_descriptor_header *) &za_9,\n+\t(struct usb_descriptor_header *) &za_10,\n+\t(struct usb_descriptor_header *) &za_11,\n+\t(struct usb_descriptor_header *) &za_12,\n+\t(struct usb_descriptor_header *) &za_13,\n+\t(struct usb_descriptor_header *) &za_14,\n+\t(struct usb_descriptor_header *) &za_15,\n+\t(struct usb_descriptor_header *) &za_16,\n+\t(struct usb_descriptor_header *) &za_17,\n+\t(struct usb_descriptor_header *) &za_18,\n+\t(struct usb_descriptor_header *) &za_19,\n+\t(struct usb_descriptor_header *) &za_20,\n+\t(struct usb_descriptor_header *) &za_21,\n+\t(struct usb_descriptor_header *) &za_22,\n+\t(struct usb_descriptor_header *) &za_23,\n+\t(struct usb_descriptor_header *) &za_24,\n+\tNULL,\n+};\n+\n+/* maxpacket and other transfer characteristics vary by speed. */\n+#define ep_desc(g,hs,fs) (((g)->speed==USB_SPEED_HIGH)?(hs):(fs))\n+\n+#else\n+\n+/* if there's no high speed support, maxpacket doesn't change. */\n+#define ep_desc(g,hs,fs) fs\n+\n+#endif\t/* !CONFIG_USB_GADGET_DUALSPEED */\n+\n+static char\t\t\t\tmanufacturer [40];\n+//static char\t\t\t\tserial [40];\n+static char\t\t\t\tserial [] = \"Ser 00 em\";\n+\n+/* static strings, in UTF-8 */\n+static struct usb_string\t\tstrings [] = {\n+\t{ STRING_MANUFACTURER, manufacturer, },\n+\t{ STRING_PRODUCT, longname, },\n+\t{ STRING_SERIAL, serial, },\n+\t{ STRING_LOOPBACK, loopback, },\n+\t{ STRING_SOURCE_SINK, source_sink, },\n+\t{  }\t\t\t/* end of list */\n+};\n+\n+static struct usb_gadget_strings\tstringtab = {\n+\t.language\t= 0x0409,\t/* en-us */\n+\t.strings\t= strings,\n+};\n+\n+/*\n+ * config descriptors are also handcrafted.  these must agree with code\n+ * that sets configurations, and with code managing interfaces and their\n+ * altsettings.  other complexity may come from:\n+ *\n+ *  - high speed support, including \"other speed config\" rules\n+ *  - multiple configurations\n+ *  - interfaces with alternate settings\n+ *  - embedded class or vendor-specific descriptors\n+ *\n+ * this handles high speed, and has a second config that could as easily\n+ * have been an alternate interface setting (on most hardware).\n+ *\n+ * NOTE:  to demonstrate (and test) more USB capabilities, this driver\n+ * should include an altsetting to test interrupt transfers, including\n+ * high bandwidth modes at high speed.  (Maybe work like Intel's test\n+ * device?)\n+ */\n+static int\n+config_buf (struct usb_gadget *gadget, u8 *buf, u8 type, unsigned index)\n+{\n+\tint len;\n+\tconst struct usb_descriptor_header **function;\n+\n+\tfunction = z_function;\n+\tlen = usb_gadget_config_buf (&z_config, buf, USB_BUFSIZ, function);\n+\tif (len < 0)\n+\t\treturn len;\n+\t((struct usb_config_descriptor *) buf)->bDescriptorType = type;\n+\treturn len;\n+}\n+\n+/*-------------------------------------------------------------------------*/\n+\n+static struct usb_request *\n+alloc_ep_req (struct usb_ep *ep, unsigned length)\n+{\n+\tstruct usb_request\t*req;\n+\n+\treq = usb_ep_alloc_request (ep, GFP_ATOMIC);\n+\tif (req) {\n+\t\treq->length = length;\n+\t\treq->buf = usb_ep_alloc_buffer (ep, length,\n+\t\t\t\t&req->dma, GFP_ATOMIC);\n+\t\tif (!req->buf) {\n+\t\t\tusb_ep_free_request (ep, req);\n+\t\t\treq = NULL;\n+\t\t}\n+\t}\n+\treturn req;\n+}\n+\n+static void free_ep_req (struct usb_ep *ep, struct usb_request *req)\n+{\n+\tif (req->buf)\n+\t\tusb_ep_free_buffer (ep, req->buf, req->dma, req->length);\n+\tusb_ep_free_request (ep, req);\n+}\n+\n+/*-------------------------------------------------------------------------*/\n+\n+/* optionally require specific source/sink data patterns  */\n+\n+static int\n+check_read_data (\n+\tstruct zero_dev\t\t*dev,\n+\tstruct usb_ep\t\t*ep,\n+\tstruct usb_request\t*req\n+)\n+{\n+\tunsigned\ti;\n+\tu8\t\t*buf = req->buf;\n+\n+\tfor (i = 0; i < req->actual; i++, buf++) {\n+\t\tswitch (pattern) {\n+\t\t/* all-zeroes has no synchronization issues */\n+\t\tcase 0:\n+\t\t\tif (*buf == 0)\n+\t\t\t\tcontinue;\n+\t\t\tbreak;\n+\t\t/* mod63 stays in sync with short-terminated transfers,\n+\t\t * or otherwise when host and gadget agree on how large\n+\t\t * each usb transfer request should be.  resync is done\n+\t\t * with set_interface or set_config.\n+\t\t */\n+\t\tcase 1:\n+\t\t\tif (*buf == (u8)(i % 63))\n+\t\t\t\tcontinue;\n+\t\t\tbreak;\n+\t\t}\n+\t\tERROR (dev, \"bad OUT byte, buf [%d] = %d\\n\", i, *buf);\n+\t\tusb_ep_set_halt (ep);\n+\t\treturn -EINVAL;\n+\t}\n+\treturn 0;\n+}\n+\n+/*-------------------------------------------------------------------------*/\n+\n+static void zero_reset_config (struct zero_dev *dev)\n+{\n+\tif (dev->config == 0)\n+\t\treturn;\n+\n+\tDBG (dev, \"reset config\\n\");\n+\n+\t/* just disable endpoints, forcing completion of pending i/o.\n+\t * all our completion handlers free their requests in this case.\n+\t */\n+\tif (dev->in_ep) {\n+\t\tusb_ep_disable (dev->in_ep);\n+\t\tdev->in_ep = NULL;\n+\t}\n+\tif (dev->out_ep) {\n+\t\tusb_ep_disable (dev->out_ep);\n+\t\tdev->out_ep = NULL;\n+\t}\n+\tdev->config = 0;\n+\tdel_timer (&dev->resume);\n+}\n+\n+#define _write(f, buf, sz) (f->f_op->write(f, buf, sz, &f->f_pos))\n+\n+static void\n+zero_isoc_complete (struct usb_ep *ep, struct usb_request *req)\n+{\n+\tstruct zero_dev\t*dev = ep->driver_data;\n+\tint\t\tstatus = req->status;\n+\tint i, j;\n+\n+\tswitch (status) {\n+\n+\tcase 0: \t\t\t/* normal completion? */\n+\t\t//printk (\"\\nzero ---------------> isoc normal completion %d bytes\\n\", req->actual);\n+\t\tfor (i=0, j=rbuf_start; i<req->actual; i++) {\n+\t\t\t//printk (\"%02x \", ((__u8*)req->buf)[i]);\n+\t\t\trbuf[j] = ((__u8*)req->buf)[i];\n+\t\t\tj++;\n+\t\t\tif (j >= RBUF_LEN) j=0;\n+\t\t}\n+\t\trbuf_start = j;\n+\t\t//printk (\"\\n\\n\");\n+\n+\t\tif (rbuf_len < RBUF_LEN) {\n+\t\t\trbuf_len += req->actual;\n+\t\t\tif (rbuf_len > RBUF_LEN) {\n+\t\t\t\trbuf_len = RBUF_LEN;\n+\t\t\t}\n+\t\t}\n+\n+\t\tbreak;\n+\n+\t/* this endpoint is normally active while we're configured */\n+\tcase -ECONNABORTED: \t\t/* hardware forced ep reset */\n+\tcase -ECONNRESET:\t\t/* request dequeued */\n+\tcase -ESHUTDOWN:\t\t/* disconnect from host */\n+\t\tVDBG (dev, \"%s gone (%d), %d/%d\\n\", ep->name, status,\n+\t\t\t\treq->actual, req->length);\n+\t\tif (ep == dev->out_ep)\n+\t\t\tcheck_read_data (dev, ep, req);\n+\t\tfree_ep_req (ep, req);\n+\t\treturn;\n+\n+\tcase -EOVERFLOW:\t\t/* buffer overrun on read means that\n+\t\t\t\t\t * we didn't provide a big enough\n+\t\t\t\t\t * buffer.\n+\t\t\t\t\t */\n+\tdefault:\n+#if 1\n+\t\tDBG (dev, \"%s complete --> %d, %d/%d\\n\", ep->name,\n+\t\t\t\tstatus, req->actual, req->length);\n+#endif\n+\tcase -EREMOTEIO:\t\t/* short read */\n+\t\tbreak;\n+\t}\n+\n+\tstatus = usb_ep_queue (ep, req, GFP_ATOMIC);\n+\tif (status) {\n+\t\tERROR (dev, \"kill %s:  resubmit %d bytes --> %d\\n\",\n+\t\t\t\tep->name, req->length, status);\n+\t\tusb_ep_set_halt (ep);\n+\t\t/* FIXME recover later ... somehow */\n+\t}\n+}\n+\n+static struct usb_request *\n+zero_start_isoc_ep (struct usb_ep *ep, int gfp_flags)\n+{\n+\tstruct usb_request\t*req;\n+\tint\t\t\tstatus;\n+\n+\treq = alloc_ep_req (ep, 512);\n+\tif (!req)\n+\t\treturn NULL;\n+\n+\treq->complete = zero_isoc_complete;\n+\n+\tstatus = usb_ep_queue (ep, req, gfp_flags);\n+\tif (status) {\n+\t\tstruct zero_dev\t*dev = ep->driver_data;\n+\n+\t\tERROR (dev, \"start %s --> %d\\n\", ep->name, status);\n+\t\tfree_ep_req (ep, req);\n+\t\treq = NULL;\n+\t}\n+\n+\treturn req;\n+}\n+\n+/* change our operational config.  this code must agree with the code\n+ * that returns config descriptors, and altsetting code.\n+ *\n+ * it's also responsible for power management interactions. some\n+ * configurations might not work with our current power sources.\n+ *\n+ * note that some device controller hardware will constrain what this\n+ * code can do, perhaps by disallowing more than one configuration or\n+ * by limiting configuration choices (like the pxa2xx).\n+ */\n+static int\n+zero_set_config (struct zero_dev *dev, unsigned number, int gfp_flags)\n+{\n+\tint\t\t\tresult = 0;\n+\tstruct usb_gadget\t*gadget = dev->gadget;\n+\tconst struct usb_endpoint_descriptor\t*d;\n+\tstruct usb_ep\t\t*ep;\n+\n+\tif (number == dev->config)\n+\t\treturn 0;\n+\n+\tzero_reset_config (dev);\n+\n+\tgadget_for_each_ep (ep, gadget) {\n+\n+\t\tif (strcmp (ep->name, \"ep4\") == 0) {\n+\n+\t\t\td = (struct usb_endpoint_descripter *)&za_23; // isoc ep desc for audio i/f alt setting 6\n+\t\t\tresult = usb_ep_enable (ep, d);\n+\n+\t\t\tif (result == 0) {\n+\t\t\t\tep->driver_data = dev;\n+\t\t\t\tdev->in_ep = ep;\n+\n+\t\t\t\tif (zero_start_isoc_ep (ep, gfp_flags) != 0) {\n+\n+\t\t\t\t\tdev->in_ep = ep;\n+\t\t\t\t\tcontinue;\n+\t\t\t\t}\n+\n+\t\t\t\tusb_ep_disable (ep);\n+\t\t\t\tresult = -EIO;\n+\t\t\t}\n+\t\t}\n+\n+\t}\n+\n+\tdev->config = number;\n+\treturn result;\n+}\n+\n+/*-------------------------------------------------------------------------*/\n+\n+static void zero_setup_complete (struct usb_ep *ep, struct usb_request *req)\n+{\n+\tif (req->status || req->actual != req->length)\n+\t\tDBG ((struct zero_dev *) ep->driver_data,\n+\t\t\t\t\"setup complete --> %d, %d/%d\\n\",\n+\t\t\t\treq->status, req->actual, req->length);\n+}\n+\n+/*\n+ * The setup() callback implements all the ep0 functionality that's\n+ * not handled lower down, in hardware or the hardware driver (like\n+ * device and endpoint feature flags, and their status).  It's all\n+ * housekeeping for the gadget function we're implementing.  Most of\n+ * the work is in config-specific setup.\n+ */\n+static int\n+zero_setup (struct usb_gadget *gadget, const struct usb_ctrlrequest *ctrl)\n+{\n+\tstruct zero_dev\t\t*dev = get_gadget_data (gadget);\n+\tstruct usb_request\t*req = dev->req;\n+\tint\t\t\tvalue = -EOPNOTSUPP;\n+\n+\t/* usually this stores reply data in the pre-allocated ep0 buffer,\n+\t * but config change events will reconfigure hardware.\n+\t */\n+\treq->zero = 0;\n+\tswitch (ctrl->bRequest) {\n+\n+\tcase USB_REQ_GET_DESCRIPTOR:\n+\n+\t\tswitch (ctrl->wValue >> 8) {\n+\n+\t\tcase USB_DT_DEVICE:\n+\t\t\tvalue = min (ctrl->wLength, (u16) sizeof device_desc);\n+\t\t\tmemcpy (req->buf, &device_desc, value);\n+\t\t\tbreak;\n+#ifdef CONFIG_USB_GADGET_DUALSPEED\n+\t\tcase USB_DT_DEVICE_QUALIFIER:\n+\t\t\tif (!gadget->is_dualspeed)\n+\t\t\t\tbreak;\n+\t\t\tvalue = min (ctrl->wLength, (u16) sizeof dev_qualifier);\n+\t\t\tmemcpy (req->buf, &dev_qualifier, value);\n+\t\t\tbreak;\n+\n+\t\tcase USB_DT_OTHER_SPEED_CONFIG:\n+\t\t\tif (!gadget->is_dualspeed)\n+\t\t\t\tbreak;\n+\t\t\t// FALLTHROUGH\n+#endif /* CONFIG_USB_GADGET_DUALSPEED */\n+\t\tcase USB_DT_CONFIG:\n+\t\t\tvalue = config_buf (gadget, req->buf,\n+\t\t\t\t\tctrl->wValue >> 8,\n+\t\t\t\t\tctrl->wValue & 0xff);\n+\t\t\tif (value >= 0)\n+\t\t\t\tvalue = min (ctrl->wLength, (u16) value);\n+\t\t\tbreak;\n+\n+\t\tcase USB_DT_STRING:\n+\t\t\t/* wIndex == language code.\n+\t\t\t * this driver only handles one language, you can\n+\t\t\t * add string tables for other languages, using\n+\t\t\t * any UTF-8 characters\n+\t\t\t */\n+\t\t\tvalue = usb_gadget_get_string (&stringtab,\n+\t\t\t\t\tctrl->wValue & 0xff, req->buf);\n+\t\t\tif (value >= 0) {\n+\t\t\t\tvalue = min (ctrl->wLength, (u16) value);\n+\t\t\t}\n+\t\t\tbreak;\n+\t\t}\n+\t\tbreak;\n+\n+\t/* currently two configs, two speeds */\n+\tcase USB_REQ_SET_CONFIGURATION:\n+\t\tif (ctrl->bRequestType != 0)\n+\t\t\tgoto unknown;\n+\n+\t\tspin_lock (&dev->lock);\n+\t\tvalue = zero_set_config (dev, ctrl->wValue, GFP_ATOMIC);\n+\t\tspin_unlock (&dev->lock);\n+\t\tbreak;\n+\tcase USB_REQ_GET_CONFIGURATION:\n+\t\tif (ctrl->bRequestType != USB_DIR_IN)\n+\t\t\tgoto unknown;\n+\t\t*(u8 *)req->buf = dev->config;\n+\t\tvalue = min (ctrl->wLength, (u16) 1);\n+\t\tbreak;\n+\n+\t/* until we add altsetting support, or other interfaces,\n+\t * only 0/0 are possible.  pxa2xx only supports 0/0 (poorly)\n+\t * and already killed pending endpoint I/O.\n+\t */\n+\tcase USB_REQ_SET_INTERFACE:\n+\n+\t\tif (ctrl->bRequestType != USB_RECIP_INTERFACE)\n+\t\t\tgoto unknown;\n+\t\tspin_lock (&dev->lock);\n+\t\tif (dev->config) {\n+\t\t\tu8\t\tconfig = dev->config;\n+\n+\t\t\t/* resets interface configuration, forgets about\n+\t\t\t * previous transaction state (queued bufs, etc)\n+\t\t\t * and re-inits endpoint state (toggle etc)\n+\t\t\t * no response queued, just zero status == success.\n+\t\t\t * if we had more than one interface we couldn't\n+\t\t\t * use this \"reset the config\" shortcut.\n+\t\t\t */\n+\t\t\tzero_reset_config (dev);\n+\t\t\tzero_set_config (dev, config, GFP_ATOMIC);\n+\t\t\tvalue = 0;\n+\t\t}\n+\t\tspin_unlock (&dev->lock);\n+\t\tbreak;\n+\tcase USB_REQ_GET_INTERFACE:\n+\t\tif ((ctrl->bRequestType == 0x21) && (ctrl->wIndex == 0x02)) {\n+\t\t\tvalue = ctrl->wLength;\n+\t\t\tbreak;\n+\t\t}\n+\t\telse {\n+\t\t\tif (ctrl->bRequestType != (USB_DIR_IN|USB_RECIP_INTERFACE))\n+\t\t\t\tgoto unknown;\n+\t\t\tif (!dev->config)\n+\t\t\t\tbreak;\n+\t\t\tif (ctrl->wIndex != 0) {\n+\t\t\t\tvalue = -EDOM;\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t\t*(u8 *)req->buf = 0;\n+\t\t\tvalue = min (ctrl->wLength, (u16) 1);\n+\t\t}\n+\t\tbreak;\n+\n+\t/*\n+\t * These are the same vendor-specific requests supported by\n+\t * Intel's USB 2.0 compliance test devices.  We exceed that\n+\t * device spec by allowing multiple-packet requests.\n+\t */\n+\tcase 0x5b:\t/* control WRITE test -- fill the buffer */\n+\t\tif (ctrl->bRequestType != (USB_DIR_OUT|USB_TYPE_VENDOR))\n+\t\t\tgoto unknown;\n+\t\tif (ctrl->wValue || ctrl->wIndex)\n+\t\t\tbreak;\n+\t\t/* just read that many bytes into the buffer */\n+\t\tif (ctrl->wLength > USB_BUFSIZ)\n+\t\t\tbreak;\n+\t\tvalue = ctrl->wLength;\n+\t\tbreak;\n+\tcase 0x5c:\t/* control READ test -- return the buffer */\n+\t\tif (ctrl->bRequestType != (USB_DIR_IN|USB_TYPE_VENDOR))\n+\t\t\tgoto unknown;\n+\t\tif (ctrl->wValue || ctrl->wIndex)\n+\t\t\tbreak;\n+\t\t/* expect those bytes are still in the buffer; send back */\n+\t\tif (ctrl->wLength > USB_BUFSIZ\n+\t\t\t\t|| ctrl->wLength != req->length)\n+\t\t\tbreak;\n+\t\tvalue = ctrl->wLength;\n+\t\tbreak;\n+\n+\tcase 0x01: // SET_CUR\n+\tcase 0x02:\n+\tcase 0x03:\n+\tcase 0x04:\n+\tcase 0x05:\n+\t\tvalue = ctrl->wLength;\n+\t\tbreak;\n+\tcase 0x81:\n+\t\tswitch (ctrl->wValue) {\n+\t\tcase 0x0201:\n+\t\tcase 0x0202:\n+\t\t\t((u8*)req->buf)[0] = 0x00;\n+\t\t\t((u8*)req->buf)[1] = 0xe3;\n+\t\t\tbreak;\n+\t\tcase 0x0300:\n+\t\tcase 0x0500:\n+\t\t\t((u8*)req->buf)[0] = 0x00;\n+\t\t\tbreak;\n+\t\t}\n+\t\t//((u8*)req->buf)[0] = 0x81;\n+\t\t//((u8*)req->buf)[1] = 0x81;\n+\t\tvalue = ctrl->wLength;\n+\t\tbreak;\n+\tcase 0x82:\n+\t\tswitch (ctrl->wValue) {\n+\t\tcase 0x0201:\n+\t\tcase 0x0202:\n+\t\t\t((u8*)req->buf)[0] = 0x00;\n+\t\t\t((u8*)req->buf)[1] = 0xc3;\n+\t\t\tbreak;\n+\t\tcase 0x0300:\n+\t\tcase 0x0500:\n+\t\t\t((u8*)req->buf)[0] = 0x00;\n+\t\t\tbreak;\n+\t\t}\n+\t\t//((u8*)req->buf)[0] = 0x82;\n+\t\t//((u8*)req->buf)[1] = 0x82;\n+\t\tvalue = ctrl->wLength;\n+\t\tbreak;\n+\tcase 0x83:\n+\t\tswitch (ctrl->wValue) {\n+\t\tcase 0x0201:\n+\t\tcase 0x0202:\n+\t\t\t((u8*)req->buf)[0] = 0x00;\n+\t\t\t((u8*)req->buf)[1] = 0x00;\n+\t\t\tbreak;\n+\t\tcase 0x0300:\n+\t\t\t((u8*)req->buf)[0] = 0x60;\n+\t\t\tbreak;\n+\t\tcase 0x0500:\n+\t\t\t((u8*)req->buf)[0] = 0x18;\n+\t\t\tbreak;\n+\t\t}\n+\t\t//((u8*)req->buf)[0] = 0x83;\n+\t\t//((u8*)req->buf)[1] = 0x83;\n+\t\tvalue = ctrl->wLength;\n+\t\tbreak;\n+\tcase 0x84:\n+\t\tswitch (ctrl->wValue) {\n+\t\tcase 0x0201:\n+\t\tcase 0x0202:\n+\t\t\t((u8*)req->buf)[0] = 0x00;\n+\t\t\t((u8*)req->buf)[1] = 0x01;\n+\t\t\tbreak;\n+\t\tcase 0x0300:\n+\t\tcase 0x0500:\n+\t\t\t((u8*)req->buf)[0] = 0x08;\n+\t\t\tbreak;\n+\t\t}\n+\t\t//((u8*)req->buf)[0] = 0x84;\n+\t\t//((u8*)req->buf)[1] = 0x84;\n+\t\tvalue = ctrl->wLength;\n+\t\tbreak;\n+\tcase 0x85:\n+\t\t((u8*)req->buf)[0] = 0x85;\n+\t\t((u8*)req->buf)[1] = 0x85;\n+\t\tvalue = ctrl->wLength;\n+\t\tbreak;\n+\n+\n+\tdefault:\n+unknown:\n+\t\tprintk(\"unknown control req%02x.%02x v%04x i%04x l%d\\n\",\n+\t\t\tctrl->bRequestType, ctrl->bRequest,\n+\t\t\tctrl->wValue, ctrl->wIndex, ctrl->wLength);\n+\t}\n+\n+\t/* respond with data transfer before status phase? */\n+\tif (value >= 0) {\n+\t\treq->length = value;\n+\t\treq->zero = value < ctrl->wLength\n+\t\t\t\t&& (value % gadget->ep0->maxpacket) == 0;\n+\t\tvalue = usb_ep_queue (gadget->ep0, req, GFP_ATOMIC);\n+\t\tif (value < 0) {\n+\t\t\tDBG (dev, \"ep_queue < 0 --> %d\\n\", value);\n+\t\t\treq->status = 0;\n+\t\t\tzero_setup_complete (gadget->ep0, req);\n+\t\t}\n+\t}\n+\n+\t/* device either stalls (value < 0) or reports success */\n+\treturn value;\n+}\n+\n+static void\n+zero_disconnect (struct usb_gadget *gadget)\n+{\n+\tstruct zero_dev\t\t*dev = get_gadget_data (gadget);\n+\tunsigned long\t\tflags;\n+\n+\tspin_lock_irqsave (&dev->lock, flags);\n+\tzero_reset_config (dev);\n+\n+\t/* a more significant application might have some non-usb\n+\t * activities to quiesce here, saving resources like power\n+\t * or pushing the notification up a network stack.\n+\t */\n+\tspin_unlock_irqrestore (&dev->lock, flags);\n+\n+\t/* next we may get setup() calls to enumerate new connections;\n+\t * or an unbind() during shutdown (including removing module).\n+\t */\n+}\n+\n+static void\n+zero_autoresume (unsigned long _dev)\n+{\n+\tstruct zero_dev\t*dev = (struct zero_dev *) _dev;\n+\tint\t\tstatus;\n+\n+\t/* normally the host would be woken up for something\n+\t * more significant than just a timer firing...\n+\t */\n+\tif (dev->gadget->speed != USB_SPEED_UNKNOWN) {\n+\t\tstatus = usb_gadget_wakeup (dev->gadget);\n+\t\tDBG (dev, \"wakeup --> %d\\n\", status);\n+\t}\n+}\n+\n+/*-------------------------------------------------------------------------*/\n+\n+static void\n+zero_unbind (struct usb_gadget *gadget)\n+{\n+\tstruct zero_dev\t\t*dev = get_gadget_data (gadget);\n+\n+\tDBG (dev, \"unbind\\n\");\n+\n+\t/* we've already been disconnected ... no i/o is active */\n+\tif (dev->req)\n+\t\tfree_ep_req (gadget->ep0, dev->req);\n+\tdel_timer_sync (&dev->resume);\n+\tkfree (dev);\n+\tset_gadget_data (gadget, NULL);\n+}\n+\n+static int\n+zero_bind (struct usb_gadget *gadget)\n+{\n+\tstruct zero_dev\t\t*dev;\n+\t//struct usb_ep\t\t*ep;\n+\n+\tprintk(\"binding\\n\");\n+\t/*\n+\t * DRIVER POLICY CHOICE:  you may want to do this differently.\n+\t * One thing to avoid is reusing a bcdDevice revision code\n+\t * with different host-visible configurations or behavior\n+\t * restrictions -- using ep1in/ep2out vs ep1out/ep3in, etc\n+\t */\n+\t//device_desc.bcdDevice = __constant_cpu_to_le16 (0x0201);\n+\n+\n+\t/* ok, we made sense of the hardware ... */\n+\tdev = kzalloc (sizeof *dev, SLAB_KERNEL);\n+\tif (!dev)\n+\t\treturn -ENOMEM;\n+\tspin_lock_init (&dev->lock);\n+\tdev->gadget = gadget;\n+\tset_gadget_data (gadget, dev);\n+\n+\t/* preallocate control response and buffer */\n+\tdev->req = usb_ep_alloc_request (gadget->ep0, GFP_KERNEL);\n+\tif (!dev->req)\n+\t\tgoto enomem;\n+\tdev->req->buf = usb_ep_alloc_buffer (gadget->ep0, USB_BUFSIZ,\n+\t\t\t\t&dev->req->dma, GFP_KERNEL);\n+\tif (!dev->req->buf)\n+\t\tgoto enomem;\n+\n+\tdev->req->complete = zero_setup_complete;\n+\n+\tdevice_desc.bMaxPacketSize0 = gadget->ep0->maxpacket;\n+\n+#ifdef CONFIG_USB_GADGET_DUALSPEED\n+\t/* assume ep0 uses the same value for both speeds ... */\n+\tdev_qualifier.bMaxPacketSize0 = device_desc.bMaxPacketSize0;\n+\n+\t/* and that all endpoints are dual-speed */\n+\t//hs_source_desc.bEndpointAddress = fs_source_desc.bEndpointAddress;\n+\t//hs_sink_desc.bEndpointAddress = fs_sink_desc.bEndpointAddress;\n+#endif\n+\n+\tusb_gadget_set_selfpowered (gadget);\n+\n+\tinit_timer (&dev->resume);\n+\tdev->resume.function = zero_autoresume;\n+\tdev->resume.data = (unsigned long) dev;\n+\n+\tgadget->ep0->driver_data = dev;\n+\n+\tINFO (dev, \"%s, version: \" DRIVER_VERSION \"\\n\", longname);\n+\tINFO (dev, \"using %s, OUT %s IN %s\\n\", gadget->name,\n+\t\tEP_OUT_NAME, EP_IN_NAME);\n+\n+\tsnprintf (manufacturer, sizeof manufacturer,\n+\t\tUTS_SYSNAME \" \" UTS_RELEASE \" with %s\",\n+\t\tgadget->name);\n+\n+\treturn 0;\n+\n+enomem:\n+\tzero_unbind (gadget);\n+\treturn -ENOMEM;\n+}\n+\n+/*-------------------------------------------------------------------------*/\n+\n+static void\n+zero_suspend (struct usb_gadget *gadget)\n+{\n+\tstruct zero_dev\t\t*dev = get_gadget_data (gadget);\n+\n+\tif (gadget->speed == USB_SPEED_UNKNOWN)\n+\t\treturn;\n+\n+\tif (autoresume) {\n+\t\tmod_timer (&dev->resume, jiffies + (HZ * autoresume));\n+\t\tDBG (dev, \"suspend, wakeup in %d seconds\\n\", autoresume);\n+\t} else\n+\t\tDBG (dev, \"suspend\\n\");\n+}\n+\n+static void\n+zero_resume (struct usb_gadget *gadget)\n+{\n+\tstruct zero_dev\t\t*dev = get_gadget_data (gadget);\n+\n+\tDBG (dev, \"resume\\n\");\n+\tdel_timer (&dev->resume);\n+}\n+\n+\n+/*-------------------------------------------------------------------------*/\n+\n+static struct usb_gadget_driver zero_driver = {\n+#ifdef CONFIG_USB_GADGET_DUALSPEED\n+\t.speed\t\t= USB_SPEED_HIGH,\n+#else\n+\t.speed\t\t= USB_SPEED_FULL,\n+#endif\n+\t.function\t= (char *) longname,\n+\t.bind\t\t= zero_bind,\n+\t.unbind\t\t= zero_unbind,\n+\n+\t.setup\t\t= zero_setup,\n+\t.disconnect\t= zero_disconnect,\n+\n+\t.suspend\t= zero_suspend,\n+\t.resume\t\t= zero_resume,\n+\n+\t.driver \t= {\n+\t\t.name\t\t= (char *) shortname,\n+\t\t// .shutdown = ...\n+\t\t// .suspend = ...\n+\t\t// .resume = ...\n+\t},\n+};\n+\n+MODULE_AUTHOR (\"David Brownell\");\n+MODULE_LICENSE (\"Dual BSD/GPL\");\n+\n+static struct proc_dir_entry *pdir, *pfile;\n+\n+static int isoc_read_data (char *page, char **start,\n+\t\t\t   off_t off, int count,\n+\t\t\t   int *eof, void *data)\n+{\n+\tint i;\n+\tstatic int c = 0;\n+\tstatic int done = 0;\n+\tstatic int s = 0;\n+\n+/*\n+\tprintk (\"\\ncount: %d\\n\", count);\n+\tprintk (\"rbuf_start: %d\\n\", rbuf_start);\n+\tprintk (\"rbuf_len: %d\\n\", rbuf_len);\n+\tprintk (\"off: %d\\n\", off);\n+\tprintk (\"start: %p\\n\\n\", *start);\n+*/\n+\tif (done) {\n+\t\tc = 0;\n+\t\tdone = 0;\n+\t\t*eof = 1;\n+\t\treturn 0;\n+\t}\n+\n+\tif (c == 0) {\n+\t\tif (rbuf_len == RBUF_LEN)\n+\t\t\ts = rbuf_start;\n+\t\telse s = 0;\n+\t}\n+\n+\tfor (i=0; i<count && c<rbuf_len; i++, c++) {\n+\t\tpage[i] = rbuf[(c+s) % RBUF_LEN];\n+\t}\n+\t*start = page;\n+\n+\tif (c >= rbuf_len) {\n+\t\t*eof = 1;\n+\t\tdone = 1;\n+\t}\n+\n+\n+\treturn i;\n+}\n+\n+static int __init init (void)\n+{\n+\n+\tint retval = 0;\n+\n+\tpdir = proc_mkdir(\"isoc_test\", NULL);\n+\tif(pdir == NULL) {\n+\t\tretval = -ENOMEM;\n+\t\tprintk(\"Error creating dir\\n\");\n+\t\tgoto done;\n+\t}\n+\tpdir->owner = THIS_MODULE;\n+\n+\tpfile = create_proc_read_entry(\"isoc_data\",\n+\t\t\t\t       0444, pdir,\n+\t\t\t\t       isoc_read_data,\n+\t\t\t\t       NULL);\n+\tif (pfile == NULL) {\n+\t\tretval = -ENOMEM;\n+\t\tprintk(\"Error creating file\\n\");\n+\t\tgoto no_file;\n+\t}\n+\tpfile->owner = THIS_MODULE;\n+\n+\treturn usb_gadget_register_driver (&zero_driver);\n+\n+ no_file:\n+\tremove_proc_entry(\"isoc_data\", NULL);\n+ done:\n+\treturn retval;\n+}\n+module_init (init);\n+\n+static void __exit cleanup (void)\n+{\n+\n+\tusb_gadget_unregister_driver (&zero_driver);\n+\n+\tremove_proc_entry(\"isoc_data\", pdir);\n+\tremove_proc_entry(\"isoc_test\", NULL);\n+}\n+module_exit (cleanup);\n--- /dev/null\n+++ b/drivers/usb/host/dwc_otg/dwc_cfi_common.h\n@@ -0,0 +1,142 @@\n+/* ==========================================================================\n+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,\n+ * \"Software\") is an Unsupported proprietary work of Synopsys, Inc. unless\n+ * otherwise expressly agreed to in writing between Synopsys and you.\n+ *\n+ * The Software IS NOT an item of Licensed Software or Licensed Product under\n+ * any End User Software License Agreement or Agreement for Licensed Product\n+ * with Synopsys or any supplement thereto. You are permitted to use and\n+ * redistribute this Software in source and binary forms, with or without\n+ * modification, provided that redistributions of source code must retain this\n+ * notice. You may not view, use, disclose, copy or distribute this file or\n+ * any information contained herein except pursuant to this license grant from\n+ * Synopsys. If you do not agree with this notice, including the disclaimer\n+ * below, then you are not authorized to use the Software.\n+ *\n+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN \"AS IS\" BASIS\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,\n+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH\n+ * DAMAGE.\n+ * ========================================================================== */\n+\n+#if !defined(__DWC_CFI_COMMON_H__)\n+#define __DWC_CFI_COMMON_H__\n+\n+//#include <linux/types.h>\n+\n+/**\n+ * @file\n+ *\n+ * This file contains the CFI specific common constants, interfaces\n+ * (functions and macros) and structures for Linux. No PCD specific\n+ * data structure or definition is to be included in this file.\n+ *\n+ */\n+\n+/** This is a request for all Core Features */\n+#define VEN_CORE_GET_FEATURES\t\t0xB1\n+\n+/** This is a request to get the value of a specific Core Feature */\n+#define VEN_CORE_GET_FEATURE\t\t0xB2\n+\n+/** This command allows the host to set the value of a specific Core Feature */\n+#define VEN_CORE_SET_FEATURE\t\t0xB3\n+\n+/** This command allows the host to set the default values of\n+ * either all or any specific Core Feature\n+ */\n+#define VEN_CORE_RESET_FEATURES\t\t0xB4\n+\n+/** This command forces the PCD to write the deferred values of a Core Features */\n+#define VEN_CORE_ACTIVATE_FEATURES\t0xB5\n+\n+/** This request reads a DWORD value from a register at the specified offset */\n+#define VEN_CORE_READ_REGISTER\t\t0xB6\n+\n+/** This request writes a DWORD value into a register at the specified offset */\n+#define VEN_CORE_WRITE_REGISTER\t\t0xB7\n+\n+/** This structure is the header of the Core Features dataset returned to\n+ *  the Host\n+ */\n+struct cfi_all_features_header {\n+/** The features header structure length is */\n+#define CFI_ALL_FEATURES_HDR_LEN\t\t8\n+\t/**\n+\t * The total length of the features dataset returned to the Host\n+\t */\n+\tuint16_t wTotalLen;\n+\n+\t/**\n+\t * CFI version number inBinary-Coded Decimal (i.e., 1.00 is 100H).\n+\t * This field identifies the version of the CFI Specification with which\n+\t * the device is compliant.\n+\t */\n+\tuint16_t wVersion;\n+\n+\t/** The ID of the Core */\n+\tuint16_t wCoreID;\n+#define CFI_CORE_ID_UDC\t\t1\n+#define CFI_CORE_ID_OTG\t\t2\n+#define CFI_CORE_ID_WUDEV\t3\n+\n+\t/** Number of features returned by VEN_CORE_GET_FEATURES request */\n+\tuint16_t wNumFeatures;\n+} UPACKED;\n+\n+typedef struct cfi_all_features_header cfi_all_features_header_t;\n+\n+/** This structure is a header of the Core Feature descriptor dataset returned to\n+ *  the Host after the VEN_CORE_GET_FEATURES request\n+ */\n+struct cfi_feature_desc_header {\n+#define CFI_FEATURE_DESC_HDR_LEN\t8\n+\n+\t/** The feature ID */\n+\tuint16_t wFeatureID;\n+\n+\t/** Length of this feature descriptor in bytes - including the\n+\t * length of the feature name string\n+\t */\n+\tuint16_t wLength;\n+\n+\t/** The data length of this feature in bytes */\n+\tuint16_t wDataLength;\n+\n+\t/**\n+\t * Attributes of this features\n+\t * D0: Access rights\n+\t * 0 - Read/Write\n+\t * 1 - Read only\n+\t */\n+\tuint8_t bmAttributes;\n+#define CFI_FEATURE_ATTR_RO\t\t1\n+#define CFI_FEATURE_ATTR_RW\t\t0\n+\n+\t/** Length of the feature name in bytes */\n+\tuint8_t bNameLen;\n+\n+\t/** The feature name buffer */\n+\t//uint8_t *name;\n+} UPACKED;\n+\n+typedef struct cfi_feature_desc_header cfi_feature_desc_header_t;\n+\n+/**\n+ * This structure describes a NULL terminated string referenced by its id field.\n+ * It is very similar to usb_string structure but has the id field type set to 16-bit.\n+ */\n+struct cfi_string {\n+\tuint16_t id;\n+\tconst uint8_t *s;\n+};\n+typedef struct cfi_string cfi_string_t;\n+\n+#endif\n--- /dev/null\n+++ b/drivers/usb/host/dwc_otg/dwc_otg_adp.c\n@@ -0,0 +1,854 @@\n+/* ==========================================================================\n+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_adp.c $\n+ * $Revision: #12 $\n+ * $Date: 2011/10/26 $\n+ * $Change: 1873028 $\n+ *\n+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,\n+ * \"Software\") is an Unsupported proprietary work of Synopsys, Inc. unless\n+ * otherwise expressly agreed to in writing between Synopsys and you.\n+ *\n+ * The Software IS NOT an item of Licensed Software or Licensed Product under\n+ * any End User Software License Agreement or Agreement for Licensed Product\n+ * with Synopsys or any supplement thereto. You are permitted to use and\n+ * redistribute this Software in source and binary forms, with or without\n+ * modification, provided that redistributions of source code must retain this\n+ * notice. You may not view, use, disclose, copy or distribute this file or\n+ * any information contained herein except pursuant to this license grant from\n+ * Synopsys. If you do not agree with this notice, including the disclaimer\n+ * below, then you are not authorized to use the Software.\n+ *\n+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN \"AS IS\" BASIS\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,\n+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH\n+ * DAMAGE.\n+ * ========================================================================== */\n+\n+#include \"dwc_os.h\"\n+#include \"dwc_otg_regs.h\"\n+#include \"dwc_otg_cil.h\"\n+#include \"dwc_otg_adp.h\"\n+\n+/** @file\n+ *\n+ * This file contains the most of the Attach Detect Protocol implementation for\n+ * the driver to support OTG Rev2.0.\n+ *\n+ */\n+\n+void dwc_otg_adp_write_reg(dwc_otg_core_if_t * core_if, uint32_t value)\n+{\n+\tadpctl_data_t adpctl;\n+\n+\tadpctl.d32 = value;\n+\tadpctl.b.ar = 0x2;\n+\n+\tDWC_WRITE_REG32(&core_if->core_global_regs->adpctl, adpctl.d32);\n+\n+\twhile (adpctl.b.ar) {\n+\t\tadpctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->adpctl);\n+\t}\n+\n+}\n+\n+/**\n+ * Function is called to read ADP registers\n+ */\n+uint32_t dwc_otg_adp_read_reg(dwc_otg_core_if_t * core_if)\n+{\n+\tadpctl_data_t adpctl;\n+\n+\tadpctl.d32 = 0;\n+\tadpctl.b.ar = 0x1;\n+\n+\tDWC_WRITE_REG32(&core_if->core_global_regs->adpctl, adpctl.d32);\n+\n+\twhile (adpctl.b.ar) {\n+\t\tadpctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->adpctl);\n+\t}\n+\n+\treturn adpctl.d32;\n+}\n+\n+/**\n+ * Function is called to read ADPCTL register and filter Write-clear bits\n+ */\n+uint32_t dwc_otg_adp_read_reg_filter(dwc_otg_core_if_t * core_if)\n+{\n+\tadpctl_data_t adpctl;\n+\n+\tadpctl.d32 = dwc_otg_adp_read_reg(core_if);\n+\tadpctl.b.adp_tmout_int = 0;\n+\tadpctl.b.adp_prb_int = 0;\n+\tadpctl.b.adp_tmout_int = 0;\n+\n+\treturn adpctl.d32;\n+}\n+\n+/**\n+ * Function is called to write ADP registers\n+ */\n+void dwc_otg_adp_modify_reg(dwc_otg_core_if_t * core_if, uint32_t clr,\n+\t\t\t    uint32_t set)\n+{\n+\tdwc_otg_adp_write_reg(core_if,\n+\t\t\t      (dwc_otg_adp_read_reg(core_if) & (~clr)) | set);\n+}\n+\n+static void adp_sense_timeout(void *ptr)\n+{\n+\tdwc_otg_core_if_t *core_if = (dwc_otg_core_if_t *) ptr;\n+\tcore_if->adp.sense_timer_started = 0;\n+\tDWC_PRINTF(\"ADP SENSE TIMEOUT\\n\");\n+\tif (core_if->adp_enable) {\n+\t\tdwc_otg_adp_sense_stop(core_if);\n+\t\tdwc_otg_adp_probe_start(core_if);\n+\t}\n+}\n+\n+/**\n+ * This function is called when the ADP vbus timer expires. Timeout is 1.1s.\n+ */\n+static void adp_vbuson_timeout(void *ptr)\n+{\n+\tgpwrdn_data_t gpwrdn;\n+\tdwc_otg_core_if_t *core_if = (dwc_otg_core_if_t *) ptr;\n+\thprt0_data_t hprt0 = {.d32 = 0 };\n+\tpcgcctl_data_t pcgcctl = {.d32 = 0 };\n+\tDWC_PRINTF(\"%s: 1.1 seconds expire after turning on VBUS\\n\",__FUNCTION__);\n+\tif (core_if) {\n+\t\tcore_if->adp.vbuson_timer_started = 0;\n+\t\t/* Turn off vbus */\n+\t\thprt0.b.prtpwr = 1;\n+\t\tDWC_MODIFY_REG32(core_if->host_if->hprt0, hprt0.d32, 0);\n+\t\tgpwrdn.d32 = 0;\n+\n+\t\t/* Power off the core */\n+\t\tif (core_if->power_down == 2) {\n+\t\t\t/* Enable Wakeup Logic */\n+//                      gpwrdn.b.wkupactiv = 1;\n+\t\t\tgpwrdn.b.pmuactv = 0;\n+\t\t\tgpwrdn.b.pwrdnrstn = 1;\n+\t\t\tgpwrdn.b.pwrdnclmp = 1;\n+\t\t\tDWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0,\n+\t\t\t\t\t gpwrdn.d32);\n+\n+\t\t\t/* Suspend the Phy Clock */\n+\t\t\tpcgcctl.b.stoppclk = 1;\n+\t\t\tDWC_MODIFY_REG32(core_if->pcgcctl, 0, pcgcctl.d32);\n+\n+\t\t\t/* Switch on VDD */\n+//                      gpwrdn.b.wkupactiv = 1;\n+\t\t\tgpwrdn.b.pmuactv = 1;\n+\t\t\tgpwrdn.b.pwrdnrstn = 1;\n+\t\t\tgpwrdn.b.pwrdnclmp = 1;\n+\t\t\tDWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0,\n+\t\t\t\t\t gpwrdn.d32);\n+\t\t} else {\n+\t\t\t/* Enable Power Down Logic */\n+\t\t\tgpwrdn.b.pmuintsel = 1;\n+\t\t\tgpwrdn.b.pmuactv = 1;\n+\t\t\tDWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);\n+\t\t}\n+\n+\t\t/* Power off the core */\n+\t\tif (core_if->power_down == 2) {\n+\t\t\tgpwrdn.d32 = 0;\n+\t\t\tgpwrdn.b.pwrdnswtch = 1;\n+\t\t\tDWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn,\n+\t\t\t\t\t gpwrdn.d32, 0);\n+\t\t}\n+\n+\t\t/* Unmask SRP detected interrupt from Power Down Logic */\n+\t\tgpwrdn.d32 = 0;\n+\t\tgpwrdn.b.srp_det_msk = 1;\n+\t\tDWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);\n+\n+\t\tdwc_otg_adp_probe_start(core_if);\n+\t\tdwc_otg_dump_global_registers(core_if);\n+\t\tdwc_otg_dump_host_registers(core_if);\n+\t}\n+\n+}\n+\n+/**\n+ * Start the ADP Initial Probe timer to detect if Port Connected interrupt is\n+ * not asserted within 1.1 seconds.\n+ *\n+ * @param core_if the pointer to core_if strucure.\n+ */\n+void dwc_otg_adp_vbuson_timer_start(dwc_otg_core_if_t * core_if)\n+{\n+\tcore_if->adp.vbuson_timer_started = 1;\n+\tif (core_if->adp.vbuson_timer)\n+\t{\n+\t\tDWC_PRINTF(\"SCHEDULING VBUSON TIMER\\n\");\n+\t\t/* 1.1 secs + 60ms necessary for cil_hcd_start*/\n+\t\tDWC_TIMER_SCHEDULE(core_if->adp.vbuson_timer, 1160);\n+\t} else {\n+\t\tDWC_WARN(\"VBUSON_TIMER = %p\\n\",core_if->adp.vbuson_timer);\n+\t}\n+}\n+\n+#if 0\n+/**\n+ * Masks all DWC OTG core interrupts\n+ *\n+ */\n+static void mask_all_interrupts(dwc_otg_core_if_t * core_if)\n+{\n+\tint i;\n+\tgahbcfg_data_t ahbcfg = {.d32 = 0 };\n+\n+\t/* Mask Host Interrupts */\n+\n+\t/* Clear and disable HCINTs */\n+\tfor (i = 0; i < core_if->core_params->host_channels; i++) {\n+\t\tDWC_WRITE_REG32(&core_if->host_if->hc_regs[i]->hcintmsk, 0);\n+\t\tDWC_WRITE_REG32(&core_if->host_if->hc_regs[i]->hcint, 0xFFFFFFFF);\n+\n+\t}\n+\n+\t/* Clear and disable HAINT */\n+\tDWC_WRITE_REG32(&core_if->host_if->host_global_regs->haintmsk, 0x0000);\n+\tDWC_WRITE_REG32(&core_if->host_if->host_global_regs->haint, 0xFFFFFFFF);\n+\n+\t/* Mask Device Interrupts */\n+\tif (!core_if->multiproc_int_enable) {\n+\t\t/* Clear and disable IN Endpoint interrupts */\n+\t\tDWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->diepmsk, 0);\n+\t\tfor (i = 0; i <= core_if->dev_if->num_in_eps; i++) {\n+\t\t\tDWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[i]->\n+\t\t\t\t\tdiepint, 0xFFFFFFFF);\n+\t\t}\n+\n+\t\t/* Clear and disable OUT Endpoint interrupts */\n+\t\tDWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->doepmsk, 0);\n+\t\tfor (i = 0; i <= core_if->dev_if->num_out_eps; i++) {\n+\t\t\tDWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[i]->\n+\t\t\t\t\tdoepint, 0xFFFFFFFF);\n+\t\t}\n+\n+\t\t/* Clear and disable DAINT */\n+\t\tDWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->daint,\n+\t\t\t\t0xFFFFFFFF);\n+\t\tDWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->daintmsk, 0);\n+\t} else {\n+\t\tfor (i = 0; i < core_if->dev_if->num_in_eps; ++i) {\n+\t\t\tDWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->\n+\t\t\t\t\tdiepeachintmsk[i], 0);\n+\t\t\tDWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[i]->\n+\t\t\t\t\tdiepint, 0xFFFFFFFF);\n+\t\t}\n+\n+\t\tfor (i = 0; i < core_if->dev_if->num_out_eps; ++i) {\n+\t\t\tDWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->\n+\t\t\t\t\tdoepeachintmsk[i], 0);\n+\t\t\tDWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[i]->\n+\t\t\t\t\tdoepint, 0xFFFFFFFF);\n+\t\t}\n+\n+\t\tDWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->deachintmsk,\n+\t\t\t\t0);\n+\t\tDWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->deachint,\n+\t\t\t\t0xFFFFFFFF);\n+\n+\t}\n+\n+\t/* Disable interrupts */\n+\tahbcfg.b.glblintrmsk = 1;\n+\tDWC_MODIFY_REG32(&core_if->core_global_regs->gahbcfg, ahbcfg.d32, 0);\n+\n+\t/* Disable all interrupts. */\n+\tDWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, 0);\n+\n+\t/* Clear any pending interrupts */\n+\tDWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);\n+\n+\t/* Clear any pending OTG Interrupts */\n+\tDWC_WRITE_REG32(&core_if->core_global_regs->gotgint, 0xFFFFFFFF);\n+}\n+\n+/**\n+ * Unmask Port Connection Detected interrupt\n+ *\n+ */\n+static void unmask_conn_det_intr(dwc_otg_core_if_t * core_if)\n+{\n+\tgintmsk_data_t gintmsk = {.d32 = 0,.b.portintr = 1 };\n+\n+\tDWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, gintmsk.d32);\n+}\n+#endif\n+\n+/**\n+ * Starts the ADP Probing\n+ *\n+ * @param core_if the pointer to core_if structure.\n+ */\n+uint32_t dwc_otg_adp_probe_start(dwc_otg_core_if_t * core_if)\n+{\n+\n+\tadpctl_data_t adpctl = {.d32 = 0};\n+\tgpwrdn_data_t gpwrdn;\n+#if 0\n+\tadpctl_data_t adpctl_int = {.d32 = 0, .b.adp_prb_int = 1,\n+\t\t\t\t\t\t\t\t.b.adp_sns_int = 1, b.adp_tmout_int};\n+#endif\n+\tdwc_otg_disable_global_interrupts(core_if);\n+\tDWC_PRINTF(\"ADP Probe Start\\n\");\n+\tcore_if->adp.probe_enabled = 1;\n+\n+\tadpctl.b.adpres = 1;\n+\tdwc_otg_adp_write_reg(core_if, adpctl.d32);\n+\n+\twhile (adpctl.b.adpres) {\n+\t\tadpctl.d32 = dwc_otg_adp_read_reg(core_if);\n+\t}\n+\n+\tadpctl.d32 = 0;\n+\tgpwrdn.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);\n+\n+\t/* In Host mode unmask SRP detected interrupt */\n+\tgpwrdn.d32 = 0;\n+\tgpwrdn.b.sts_chngint_msk = 1;\n+\tif (!gpwrdn.b.idsts) {\n+\t\tgpwrdn.b.srp_det_msk = 1;\n+\t}\n+\tDWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);\n+\n+\tadpctl.b.adp_tmout_int_msk = 1;\n+\tadpctl.b.adp_prb_int_msk = 1;\n+\tadpctl.b.prb_dschg = 1;\n+\tadpctl.b.prb_delta = 1;\n+\tadpctl.b.prb_per = 1;\n+\tadpctl.b.adpen = 1;\n+\tadpctl.b.enaprb = 1;\n+\n+\tdwc_otg_adp_write_reg(core_if, adpctl.d32);\n+\tDWC_PRINTF(\"ADP Probe Finish\\n\");\n+\treturn 0;\n+}\n+\n+/**\n+ * Starts the ADP Sense timer to detect if ADP Sense interrupt is not asserted\n+ * within 3 seconds.\n+ *\n+ * @param core_if the pointer to core_if strucure.\n+ */\n+void dwc_otg_adp_sense_timer_start(dwc_otg_core_if_t * core_if)\n+{\n+\tcore_if->adp.sense_timer_started = 1;\n+\tDWC_TIMER_SCHEDULE(core_if->adp.sense_timer, 3000 /* 3 secs */ );\n+}\n+\n+/**\n+ * Starts the ADP Sense\n+ *\n+ * @param core_if the pointer to core_if strucure.\n+ */\n+uint32_t dwc_otg_adp_sense_start(dwc_otg_core_if_t * core_if)\n+{\n+\tadpctl_data_t adpctl;\n+\n+\tDWC_PRINTF(\"ADP Sense Start\\n\");\n+\n+\t/* Unmask ADP sense interrupt and mask all other from the core */\n+\tadpctl.d32 = dwc_otg_adp_read_reg_filter(core_if);\n+\tadpctl.b.adp_sns_int_msk = 1;\n+\tdwc_otg_adp_write_reg(core_if, adpctl.d32);\n+\tdwc_otg_disable_global_interrupts(core_if); // vahrama\n+\n+\t/* Set ADP reset bit*/\n+\tadpctl.d32 = dwc_otg_adp_read_reg_filter(core_if);\n+\tadpctl.b.adpres = 1;\n+\tdwc_otg_adp_write_reg(core_if, adpctl.d32);\n+\n+\twhile (adpctl.b.adpres) {\n+\t\tadpctl.d32 = dwc_otg_adp_read_reg(core_if);\n+\t}\n+\n+\tadpctl.b.adpres = 0;\n+\tadpctl.b.adpen = 1;\n+\tadpctl.b.enasns = 1;\n+\tdwc_otg_adp_write_reg(core_if, adpctl.d32);\n+\n+\tdwc_otg_adp_sense_timer_start(core_if);\n+\n+\treturn 0;\n+}\n+\n+/**\n+ * Stops the ADP Probing\n+ *\n+ * @param core_if the pointer to core_if strucure.\n+ */\n+uint32_t dwc_otg_adp_probe_stop(dwc_otg_core_if_t * core_if)\n+{\n+\n+\tadpctl_data_t adpctl;\n+\tDWC_PRINTF(\"Stop ADP probe\\n\");\n+\tcore_if->adp.probe_enabled = 0;\n+\tcore_if->adp.probe_counter = 0;\n+\tadpctl.d32 = dwc_otg_adp_read_reg(core_if);\n+\n+\tadpctl.b.adpen = 0;\n+\tadpctl.b.adp_prb_int = 1;\n+\tadpctl.b.adp_tmout_int = 1;\n+\tadpctl.b.adp_sns_int = 1;\n+\tdwc_otg_adp_write_reg(core_if, adpctl.d32);\n+\n+\treturn 0;\n+}\n+\n+/**\n+ * Stops the ADP Sensing\n+ *\n+ * @param core_if the pointer to core_if strucure.\n+ */\n+uint32_t dwc_otg_adp_sense_stop(dwc_otg_core_if_t * core_if)\n+{\n+\tadpctl_data_t adpctl;\n+\n+\tcore_if->adp.sense_enabled = 0;\n+\n+\tadpctl.d32 = dwc_otg_adp_read_reg_filter(core_if);\n+\tadpctl.b.enasns = 0;\n+\tadpctl.b.adp_sns_int = 1;\n+\tdwc_otg_adp_write_reg(core_if, adpctl.d32);\n+\n+\treturn 0;\n+}\n+\n+/**\n+ * Called to turn on the VBUS after initial ADP probe in host mode.\n+ * If port power was already enabled in cil_hcd_start function then\n+ * only schedule a timer.\n+ *\n+ * @param core_if the pointer to core_if structure.\n+ */\n+void dwc_otg_adp_turnon_vbus(dwc_otg_core_if_t * core_if)\n+{\n+\thprt0_data_t hprt0 = {.d32 = 0 };\n+\thprt0.d32 = dwc_otg_read_hprt0(core_if);\n+\tDWC_PRINTF(\"Turn on VBUS for 1.1s, port power is %d\\n\", hprt0.b.prtpwr);\n+\n+\tif (hprt0.b.prtpwr == 0) {\n+\t\thprt0.b.prtpwr = 1;\n+\t\t//DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);\n+\t}\n+\n+\tdwc_otg_adp_vbuson_timer_start(core_if);\n+}\n+\n+/**\n+ * Called right after driver is loaded\n+ * to perform initial actions for ADP\n+ *\n+ * @param core_if the pointer to core_if structure.\n+ * @param is_host - flag for current mode of operation either from GINTSTS or GPWRDN\n+ */\n+void dwc_otg_adp_start(dwc_otg_core_if_t * core_if, uint8_t is_host)\n+{\n+\tgpwrdn_data_t gpwrdn;\n+\n+\tDWC_PRINTF(\"ADP Initial Start\\n\");\n+\tcore_if->adp.adp_started = 1;\n+\n+\tDWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);\n+\tdwc_otg_disable_global_interrupts(core_if);\n+\tif (is_host) {\n+\t\tDWC_PRINTF(\"HOST MODE\\n\");\n+\t\t/* Enable Power Down Logic Interrupt*/\n+\t\tgpwrdn.d32 = 0;\n+\t\tgpwrdn.b.pmuintsel = 1;\n+\t\tgpwrdn.b.pmuactv = 1;\n+\t\tDWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);\n+\t\t/* Initialize first ADP probe to obtain Ramp Time value */\n+\t\tcore_if->adp.initial_probe = 1;\n+\t\tdwc_otg_adp_probe_start(core_if);\n+\t} else {\n+\t\tgotgctl_data_t gotgctl;\n+\t\tgotgctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->gotgctl);\n+\t\tDWC_PRINTF(\"DEVICE MODE\\n\");\n+\t\tif (gotgctl.b.bsesvld == 0) {\n+\t\t\t/* Enable Power Down Logic Interrupt*/\n+\t\t\tgpwrdn.d32 = 0;\n+\t\t\tDWC_PRINTF(\"VBUS is not valid - start ADP probe\\n\");\n+\t\t\tgpwrdn.b.pmuintsel = 1;\n+\t\t\tgpwrdn.b.pmuactv = 1;\n+\t\t\tDWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);\n+\t\t\tcore_if->adp.initial_probe = 1;\n+\t\t\tdwc_otg_adp_probe_start(core_if);\n+\t\t} else {\n+\t\t\tDWC_PRINTF(\"VBUS is valid - initialize core as a Device\\n\");\n+\t\t\tcore_if->op_state = B_PERIPHERAL;\n+\t\t\tdwc_otg_core_init(core_if);\n+\t\t\tdwc_otg_enable_global_interrupts(core_if);\n+\t\t\tcil_pcd_start(core_if);\n+\t\t\tdwc_otg_dump_global_registers(core_if);\n+\t\t\tdwc_otg_dump_dev_registers(core_if);\n+\t\t}\n+\t}\n+}\n+\n+void dwc_otg_adp_init(dwc_otg_core_if_t * core_if)\n+{\n+\tcore_if->adp.adp_started = 0;\n+\tcore_if->adp.initial_probe = 0;\n+\tcore_if->adp.probe_timer_values[0] = -1;\n+\tcore_if->adp.probe_timer_values[1] = -1;\n+\tcore_if->adp.probe_enabled = 0;\n+\tcore_if->adp.sense_enabled = 0;\n+\tcore_if->adp.sense_timer_started = 0;\n+\tcore_if->adp.vbuson_timer_started = 0;\n+\tcore_if->adp.probe_counter = 0;\n+\tcore_if->adp.gpwrdn = 0;\n+\tcore_if->adp.attached = DWC_OTG_ADP_UNKOWN;\n+\t/* Initialize timers */\n+\tcore_if->adp.sense_timer =\n+\t    DWC_TIMER_ALLOC(\"ADP SENSE TIMER\", adp_sense_timeout, core_if);\n+\tcore_if->adp.vbuson_timer =\n+\t    DWC_TIMER_ALLOC(\"ADP VBUS ON TIMER\", adp_vbuson_timeout, core_if);\n+\tif (!core_if->adp.sense_timer || !core_if->adp.vbuson_timer)\n+\t{\n+\t\tDWC_ERROR(\"Could not allocate memory for ADP timers\\n\");\n+\t}\n+}\n+\n+void dwc_otg_adp_remove(dwc_otg_core_if_t * core_if)\n+{\n+\tgpwrdn_data_t gpwrdn = { .d32 = 0 };\n+\tgpwrdn.b.pmuintsel = 1;\n+\tgpwrdn.b.pmuactv = 1;\n+\tDWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);\n+\n+\tif (core_if->adp.probe_enabled)\n+\t\tdwc_otg_adp_probe_stop(core_if);\n+\tif (core_if->adp.sense_enabled)\n+\t\tdwc_otg_adp_sense_stop(core_if);\n+\tif (core_if->adp.sense_timer_started)\n+\t\tDWC_TIMER_CANCEL(core_if->adp.sense_timer);\n+\tif (core_if->adp.vbuson_timer_started)\n+\t\tDWC_TIMER_CANCEL(core_if->adp.vbuson_timer);\n+\tDWC_TIMER_FREE(core_if->adp.sense_timer);\n+\tDWC_TIMER_FREE(core_if->adp.vbuson_timer);\n+}\n+\n+/////////////////////////////////////////////////////////////////////\n+////////////// ADP Interrupt Handlers ///////////////////////////////\n+/////////////////////////////////////////////////////////////////////\n+/**\n+ * This function sets Ramp Timer values\n+ */\n+static uint32_t set_timer_value(dwc_otg_core_if_t * core_if, uint32_t val)\n+{\n+\tif (core_if->adp.probe_timer_values[0] == -1) {\n+\t\tcore_if->adp.probe_timer_values[0] = val;\n+\t\tcore_if->adp.probe_timer_values[1] = -1;\n+\t\treturn 1;\n+\t} else {\n+\t\tcore_if->adp.probe_timer_values[1] =\n+\t\t    core_if->adp.probe_timer_values[0];\n+\t\tcore_if->adp.probe_timer_values[0] = val;\n+\t\treturn 0;\n+\t}\n+}\n+\n+/**\n+ * This function compares Ramp Timer values\n+ */\n+static uint32_t compare_timer_values(dwc_otg_core_if_t * core_if)\n+{\n+\tuint32_t diff;\n+\tif (core_if->adp.probe_timer_values[0]>=core_if->adp.probe_timer_values[1])\n+\t\t\tdiff = core_if->adp.probe_timer_values[0]-core_if->adp.probe_timer_values[1];\n+\telse\n+\t\t\tdiff = core_if->adp.probe_timer_values[1]-core_if->adp.probe_timer_values[0];\n+\tif(diff < 2) {\n+\t\treturn 0;\n+\t} else {\n+\t\treturn 1;\n+\t}\n+}\n+\n+/**\n+ * This function handles ADP Probe Interrupts\n+ */\n+static int32_t dwc_otg_adp_handle_prb_intr(dwc_otg_core_if_t * core_if,\n+\t\t\t\t\t\t uint32_t val)\n+{\n+\tadpctl_data_t adpctl = {.d32 = 0 };\n+\tgpwrdn_data_t gpwrdn, temp;\n+\tadpctl.d32 = val;\n+\n+\ttemp.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);\n+\tcore_if->adp.probe_counter++;\n+\tcore_if->adp.gpwrdn = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);\n+\tif (adpctl.b.rtim == 0 && !temp.b.idsts){\n+\t\tDWC_PRINTF(\"RTIM value is 0\\n\");\n+\t\tgoto exit;\n+\t}\n+\tif (set_timer_value(core_if, adpctl.b.rtim) &&\n+\t    core_if->adp.initial_probe) {\n+\t\tcore_if->adp.initial_probe = 0;\n+\t\tdwc_otg_adp_probe_stop(core_if);\n+\t\tgpwrdn.d32 = 0;\n+\t\tgpwrdn.b.pmuactv = 1;\n+\t\tgpwrdn.b.pmuintsel = 1;\n+\t\tDWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);\n+\t\tDWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);\n+\n+\t\t/* check which value is for device mode and which for Host mode */\n+\t\tif (!temp.b.idsts) {\t/* considered host mode value is 0 */\n+\t\t\t/*\n+\t\t\t * Turn on VBUS after initial ADP probe.\n+\t\t\t */\n+\t\t\tcore_if->op_state = A_HOST;\n+\t\t\tdwc_otg_enable_global_interrupts(core_if);\n+\t\t\tDWC_SPINUNLOCK(core_if->lock);\n+\t\t\tcil_hcd_start(core_if);\n+\t\t\tdwc_otg_adp_turnon_vbus(core_if);\n+\t\t\tDWC_SPINLOCK(core_if->lock);\n+\t\t} else {\n+\t\t\t/*\n+\t\t\t * Initiate SRP after initial ADP probe.\n+\t\t\t */\n+\t\t\tdwc_otg_enable_global_interrupts(core_if);\n+\t\t\tdwc_otg_initiate_srp(core_if);\n+\t\t}\n+\t} else if (core_if->adp.probe_counter > 2){\n+\t\tgpwrdn.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);\n+\t\tif (compare_timer_values(core_if)) {\n+\t\t\tDWC_PRINTF(\"Difference in timer values !!! \\n\");\n+//                      core_if->adp.attached = DWC_OTG_ADP_ATTACHED;\n+\t\t\tdwc_otg_adp_probe_stop(core_if);\n+\n+\t\t\t/* Power on the core */\n+\t\t\tif (core_if->power_down == 2) {\n+\t\t\t\tgpwrdn.b.pwrdnswtch = 1;\n+\t\t\t\tDWC_MODIFY_REG32(&core_if->core_global_regs->\n+\t\t\t\t\t\t gpwrdn, 0, gpwrdn.d32);\n+\t\t\t}\n+\n+\t\t\t/* check which value is for device mode and which for Host mode */\n+\t\t\tif (!temp.b.idsts) {\t/* considered host mode value is 0 */\n+\t\t\t\t/* Disable Interrupt from Power Down Logic */\n+\t\t\t\tgpwrdn.d32 = 0;\n+\t\t\t\tgpwrdn.b.pmuintsel = 1;\n+\t\t\t\tgpwrdn.b.pmuactv = 1;\n+\t\t\t\tDWC_MODIFY_REG32(&core_if->core_global_regs->\n+\t\t\t\t\t\t gpwrdn, gpwrdn.d32, 0);\n+\n+\t\t\t\t/*\n+\t\t\t\t * Initialize the Core for Host mode.\n+\t\t\t\t */\n+\t\t\t\tcore_if->op_state = A_HOST;\n+\t\t\t\tdwc_otg_core_init(core_if);\n+\t\t\t\tdwc_otg_enable_global_interrupts(core_if);\n+\t\t\t\tcil_hcd_start(core_if);\n+\t\t\t} else {\n+\t\t\t\tgotgctl_data_t gotgctl;\n+\t\t\t\t/* Mask SRP detected interrupt from Power Down Logic */\n+\t\t\t\tgpwrdn.d32 = 0;\n+\t\t\t\tgpwrdn.b.srp_det_msk = 1;\n+\t\t\t\tDWC_MODIFY_REG32(&core_if->core_global_regs->\n+\t\t\t\t\t\t gpwrdn, gpwrdn.d32, 0);\n+\n+\t\t\t\t/* Disable Power Down Logic */\n+\t\t\t\tgpwrdn.d32 = 0;\n+\t\t\t\tgpwrdn.b.pmuintsel = 1;\n+\t\t\t\tgpwrdn.b.pmuactv = 1;\n+\t\t\t\tDWC_MODIFY_REG32(&core_if->core_global_regs->\n+\t\t\t\t\t\t gpwrdn, gpwrdn.d32, 0);\n+\n+\t\t\t\t/*\n+\t\t\t\t * Initialize the Core for Device mode.\n+\t\t\t\t */\n+\t\t\t\tcore_if->op_state = B_PERIPHERAL;\n+\t\t\t\tdwc_otg_core_init(core_if);\n+\t\t\t\tdwc_otg_enable_global_interrupts(core_if);\n+\t\t\t\tcil_pcd_start(core_if);\n+\n+\t\t\t\tgotgctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->gotgctl);\n+\t\t\t\tif (!gotgctl.b.bsesvld) {\n+\t\t\t\t\tdwc_otg_initiate_srp(core_if);\n+\t\t\t\t}\n+\t\t\t}\n+\t\t}\n+\t\tif (core_if->power_down == 2) {\n+\t\t\tif (gpwrdn.b.bsessvld) {\n+\t\t\t\t/* Mask SRP detected interrupt from Power Down Logic */\n+\t\t\t\tgpwrdn.d32 = 0;\n+\t\t\t\tgpwrdn.b.srp_det_msk = 1;\n+\t\t\t\tDWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);\n+\n+\t\t\t\t/* Disable Power Down Logic */\n+\t\t\t\tgpwrdn.d32 = 0;\n+\t\t\t\tgpwrdn.b.pmuactv = 1;\n+\t\t\t\tDWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);\n+\n+\t\t\t\t/*\n+\t\t\t\t * Initialize the Core for Device mode.\n+\t\t\t\t */\n+\t\t\t\tcore_if->op_state = B_PERIPHERAL;\n+\t\t\t\tdwc_otg_core_init(core_if);\n+\t\t\t\tdwc_otg_enable_global_interrupts(core_if);\n+\t\t\t\tcil_pcd_start(core_if);\n+\t\t\t}\n+\t\t}\n+\t}\n+exit:\n+\t/* Clear interrupt */\n+\tadpctl.d32 = dwc_otg_adp_read_reg(core_if);\n+\tadpctl.b.adp_prb_int = 1;\n+\tdwc_otg_adp_write_reg(core_if, adpctl.d32);\n+\n+\treturn 0;\n+}\n+\n+/**\n+ * This function hadles ADP Sense Interrupt\n+ */\n+static int32_t dwc_otg_adp_handle_sns_intr(dwc_otg_core_if_t * core_if)\n+{\n+\tadpctl_data_t adpctl;\n+\t/* Stop ADP Sense timer */\n+\tDWC_TIMER_CANCEL(core_if->adp.sense_timer);\n+\n+\t/* Restart ADP Sense timer */\n+\tdwc_otg_adp_sense_timer_start(core_if);\n+\n+\t/* Clear interrupt */\n+\tadpctl.d32 = dwc_otg_adp_read_reg(core_if);\n+\tadpctl.b.adp_sns_int = 1;\n+\tdwc_otg_adp_write_reg(core_if, adpctl.d32);\n+\n+\treturn 0;\n+}\n+\n+/**\n+ * This function handles ADP Probe Interrupts\n+ */\n+static int32_t dwc_otg_adp_handle_prb_tmout_intr(dwc_otg_core_if_t * core_if,\n+\t\t\t\t\t\t uint32_t val)\n+{\n+\tadpctl_data_t adpctl = {.d32 = 0 };\n+\tadpctl.d32 = val;\n+\tset_timer_value(core_if, adpctl.b.rtim);\n+\n+\t/* Clear interrupt */\n+\tadpctl.d32 = dwc_otg_adp_read_reg(core_if);\n+\tadpctl.b.adp_tmout_int = 1;\n+\tdwc_otg_adp_write_reg(core_if, adpctl.d32);\n+\n+\treturn 0;\n+}\n+\n+/**\n+ * ADP Interrupt handler.\n+ *\n+ */\n+int32_t dwc_otg_adp_handle_intr(dwc_otg_core_if_t * core_if)\n+{\n+\tint retval = 0;\n+\tadpctl_data_t adpctl = {.d32 = 0};\n+\n+\tadpctl.d32 = dwc_otg_adp_read_reg(core_if);\n+\tDWC_PRINTF(\"ADPCTL = %08x\\n\",adpctl.d32);\n+\n+\tif (adpctl.b.adp_sns_int & adpctl.b.adp_sns_int_msk) {\n+\t\tDWC_PRINTF(\"ADP Sense interrupt\\n\");\n+\t\tretval |= dwc_otg_adp_handle_sns_intr(core_if);\n+\t}\n+\tif (adpctl.b.adp_tmout_int & adpctl.b.adp_tmout_int_msk) {\n+\t\tDWC_PRINTF(\"ADP timeout interrupt\\n\");\n+\t\tretval |= dwc_otg_adp_handle_prb_tmout_intr(core_if, adpctl.d32);\n+\t}\n+\tif (adpctl.b.adp_prb_int & adpctl.b.adp_prb_int_msk) {\n+\t\tDWC_PRINTF(\"ADP Probe interrupt\\n\");\n+\t\tadpctl.b.adp_prb_int = 1;\n+\t\tretval |= dwc_otg_adp_handle_prb_intr(core_if, adpctl.d32);\n+\t}\n+\n+//\tdwc_otg_adp_modify_reg(core_if, adpctl.d32, 0);\n+\t//dwc_otg_adp_write_reg(core_if, adpctl.d32);\n+\tDWC_PRINTF(\"RETURN FROM ADP ISR\\n\");\n+\n+\treturn retval;\n+}\n+\n+/**\n+ *\n+ * @param core_if Programming view of DWC_otg controller.\n+ */\n+int32_t dwc_otg_adp_handle_srp_intr(dwc_otg_core_if_t * core_if)\n+{\n+\n+#ifndef DWC_HOST_ONLY\n+\thprt0_data_t hprt0;\n+\tgpwrdn_data_t gpwrdn;\n+\tDWC_DEBUGPL(DBG_ANY, \"++ Power Down Logic Session Request Interrupt++\\n\");\n+\n+\tgpwrdn.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);\n+\t/* check which value is for device mode and which for Host mode */\n+\tif (!gpwrdn.b.idsts) {\t/* considered host mode value is 0 */\n+\t\tDWC_PRINTF(\"SRP: Host mode\\n\");\n+\n+\t\tif (core_if->adp_enable) {\n+\t\t\tdwc_otg_adp_probe_stop(core_if);\n+\n+\t\t\t/* Power on the core */\n+\t\t\tif (core_if->power_down == 2) {\n+\t\t\t\tgpwrdn.b.pwrdnswtch = 1;\n+\t\t\t\tDWC_MODIFY_REG32(&core_if->core_global_regs->\n+\t\t\t\t\t\t gpwrdn, 0, gpwrdn.d32);\n+\t\t\t}\n+\n+\t\t\tcore_if->op_state = A_HOST;\n+\t\t\tdwc_otg_core_init(core_if);\n+\t\t\tdwc_otg_enable_global_interrupts(core_if);\n+\t\t\tcil_hcd_start(core_if);\n+\t\t}\n+\n+\t\t/* Turn on the port power bit. */\n+\t\thprt0.d32 = dwc_otg_read_hprt0(core_if);\n+\t\thprt0.b.prtpwr = 1;\n+\t\tDWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);\n+\n+\t\t/* Start the Connection timer. So a message can be displayed\n+\t\t * if connect does not occur within 10 seconds. */\n+\t\tcil_hcd_session_start(core_if);\n+\t} else {\n+\t\tDWC_PRINTF(\"SRP: Device mode %s\\n\", __FUNCTION__);\n+\t\tif (core_if->adp_enable) {\n+\t\t\tdwc_otg_adp_probe_stop(core_if);\n+\n+\t\t\t/* Power on the core */\n+\t\t\tif (core_if->power_down == 2) {\n+\t\t\t\tgpwrdn.b.pwrdnswtch = 1;\n+\t\t\t\tDWC_MODIFY_REG32(&core_if->core_global_regs->\n+\t\t\t\t\t\t gpwrdn, 0, gpwrdn.d32);\n+\t\t\t}\n+\n+\t\t\tgpwrdn.d32 = 0;\n+\t\t\tgpwrdn.b.pmuactv = 0;\n+\t\t\tDWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0,\n+\t\t\t\t\t gpwrdn.d32);\n+\n+\t\t\tcore_if->op_state = B_PERIPHERAL;\n+\t\t\tdwc_otg_core_init(core_if);\n+\t\t\tdwc_otg_enable_global_interrupts(core_if);\n+\t\t\tcil_pcd_start(core_if);\n+\t\t}\n+\t}\n+#endif\n+\treturn 1;\n+}\n--- /dev/null\n+++ b/drivers/usb/host/dwc_otg/dwc_otg_adp.h\n@@ -0,0 +1,80 @@\n+/* ==========================================================================\n+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_adp.h $\n+ * $Revision: #7 $\n+ * $Date: 2011/10/24 $\n+ * $Change: 1871159 $\n+ *\n+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,\n+ * \"Software\") is an Unsupported proprietary work of Synopsys, Inc. unless\n+ * otherwise expressly agreed to in writing between Synopsys and you.\n+ *\n+ * The Software IS NOT an item of Licensed Software or Licensed Product under\n+ * any End User Software License Agreement or Agreement for Licensed Product\n+ * with Synopsys or any supplement thereto. You are permitted to use and\n+ * redistribute this Software in source and binary forms, with or without\n+ * modification, provided that redistributions of source code must retain this\n+ * notice. You may not view, use, disclose, copy or distribute this file or\n+ * any information contained herein except pursuant to this license grant from\n+ * Synopsys. If you do not agree with this notice, including the disclaimer\n+ * below, then you are not authorized to use the Software.\n+ *\n+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN \"AS IS\" BASIS\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,\n+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH\n+ * DAMAGE.\n+ * ========================================================================== */\n+\n+#ifndef __DWC_OTG_ADP_H__\n+#define __DWC_OTG_ADP_H__\n+\n+/**\n+ * @file\n+ *\n+ * This file contains the Attach Detect Protocol interfaces and defines\n+ * (functions) and structures for Linux.\n+ *\n+ */\n+\n+#define DWC_OTG_ADP_UNATTACHED\t0\n+#define DWC_OTG_ADP_ATTACHED\t1\n+#define DWC_OTG_ADP_UNKOWN\t2\n+\n+typedef struct dwc_otg_adp {\n+\tuint32_t adp_started;\n+\tuint32_t initial_probe;\n+\tint32_t probe_timer_values[2];\n+\tuint32_t probe_enabled;\n+\tuint32_t sense_enabled;\n+\tdwc_timer_t *sense_timer;\n+\tuint32_t sense_timer_started;\n+\tdwc_timer_t *vbuson_timer;\n+\tuint32_t vbuson_timer_started;\n+\tuint32_t attached;\n+\tuint32_t probe_counter;\n+\tuint32_t gpwrdn;\n+} dwc_otg_adp_t;\n+\n+/**\n+ * Attach Detect Protocol functions\n+ */\n+\n+extern void dwc_otg_adp_write_reg(dwc_otg_core_if_t * core_if, uint32_t value);\n+extern uint32_t dwc_otg_adp_read_reg(dwc_otg_core_if_t * core_if);\n+extern uint32_t dwc_otg_adp_probe_start(dwc_otg_core_if_t * core_if);\n+extern uint32_t dwc_otg_adp_sense_start(dwc_otg_core_if_t * core_if);\n+extern uint32_t dwc_otg_adp_probe_stop(dwc_otg_core_if_t * core_if);\n+extern uint32_t dwc_otg_adp_sense_stop(dwc_otg_core_if_t * core_if);\n+extern void dwc_otg_adp_start(dwc_otg_core_if_t * core_if, uint8_t is_host);\n+extern void dwc_otg_adp_init(dwc_otg_core_if_t * core_if);\n+extern void dwc_otg_adp_remove(dwc_otg_core_if_t * core_if);\n+extern int32_t dwc_otg_adp_handle_intr(dwc_otg_core_if_t * core_if);\n+extern int32_t dwc_otg_adp_handle_srp_intr(dwc_otg_core_if_t * core_if);\n+\n+#endif //__DWC_OTG_ADP_H__\n--- /dev/null\n+++ b/drivers/usb/host/dwc_otg/dwc_otg_attr.c\n@@ -0,0 +1,1212 @@\n+/* ==========================================================================\n+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_attr.c $\n+ * $Revision: #44 $\n+ * $Date: 2010/11/29 $\n+ * $Change: 1636033 $\n+ *\n+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,\n+ * \"Software\") is an Unsupported proprietary work of Synopsys, Inc. unless\n+ * otherwise expressly agreed to in writing between Synopsys and you.\n+ *\n+ * The Software IS NOT an item of Licensed Software or Licensed Product under\n+ * any End User Software License Agreement or Agreement for Licensed Product\n+ * with Synopsys or any supplement thereto. You are permitted to use and\n+ * redistribute this Software in source and binary forms, with or without\n+ * modification, provided that redistributions of source code must retain this\n+ * notice. You may not view, use, disclose, copy or distribute this file or\n+ * any information contained herein except pursuant to this license grant from\n+ * Synopsys. If you do not agree with this notice, including the disclaimer\n+ * below, then you are not authorized to use the Software.\n+ *\n+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN \"AS IS\" BASIS\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,\n+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH\n+ * DAMAGE.\n+ * ========================================================================== */\n+\n+/** @file\n+ *\n+ * The diagnostic interface will provide access to the controller for\n+ * bringing up the hardware and testing.  The Linux driver attributes\n+ * feature will be used to provide the Linux Diagnostic\n+ * Interface. These attributes are accessed through sysfs.\n+ */\n+\n+/** @page \"Linux Module Attributes\"\n+ *\n+ * The Linux module attributes feature is used to provide the Linux\n+ * Diagnostic Interface.  These attributes are accessed through sysfs.\n+ * The diagnostic interface will provide access to the controller for\n+ * bringing up the hardware and testing.\n+\n+ The following table shows the attributes.\n+ <table>\n+ <tr>\n+ <td><b> Name</b></td>\n+ <td><b> Description</b></td>\n+ <td><b> Access</b></td>\n+ </tr>\n+\n+ <tr>\n+ <td> mode </td>\n+ <td> Returns the current mode: 0 for device mode, 1 for host mode</td>\n+ <td> Read</td>\n+ </tr>\n+\n+ <tr>\n+ <td> hnpcapable </td>\n+ <td> Gets or sets the \"HNP-capable\" bit in the Core USB Configuraton Register.\n+ Read returns the current value.</td>\n+ <td> Read/Write</td>\n+ </tr>\n+\n+ <tr>\n+ <td> srpcapable </td>\n+ <td> Gets or sets the \"SRP-capable\" bit in the Core USB Configuraton Register.\n+ Read returns the current value.</td>\n+ <td> Read/Write</td>\n+ </tr>\n+\n+ <tr>\n+ <td> hsic_connect </td>\n+ <td> Gets or sets the \"HSIC-Connect\" bit in the GLPMCFG Register.\n+ Read returns the current value.</td>\n+ <td> Read/Write</td>\n+ </tr>\n+\n+ <tr>\n+ <td> inv_sel_hsic </td>\n+ <td> Gets or sets the \"Invert Select HSIC\" bit in the GLPMFG Register.\n+ Read returns the current value.</td>\n+ <td> Read/Write</td>\n+ </tr>\n+\n+ <tr>\n+ <td> hnp </td>\n+ <td> Initiates the Host Negotiation Protocol.  Read returns the status.</td>\n+ <td> Read/Write</td>\n+ </tr>\n+\n+ <tr>\n+ <td> srp </td>\n+ <td> Initiates the Session Request Protocol.  Read returns the status.</td>\n+ <td> Read/Write</td>\n+ </tr>\n+\n+ <tr>\n+ <td> buspower </td>\n+ <td> Gets or sets the Power State of the bus (0 - Off or 1 - On)</td>\n+ <td> Read/Write</td>\n+ </tr>\n+\n+ <tr>\n+ <td> bussuspend </td>\n+ <td> Suspends the USB bus.</td>\n+ <td> Read/Write</td>\n+ </tr>\n+\n+ <tr>\n+ <td> busconnected </td>\n+ <td> Gets the connection status of the bus</td>\n+ <td> Read</td>\n+ </tr>\n+\n+ <tr>\n+ <td> gotgctl </td>\n+ <td> Gets or sets the Core Control Status Register.</td>\n+ <td> Read/Write</td>\n+ </tr>\n+\n+ <tr>\n+ <td> gusbcfg </td>\n+ <td> Gets or sets the Core USB Configuration Register</td>\n+ <td> Read/Write</td>\n+ </tr>\n+\n+ <tr>\n+ <td> grxfsiz </td>\n+ <td> Gets or sets the Receive FIFO Size Register</td>\n+ <td> Read/Write</td>\n+ </tr>\n+\n+ <tr>\n+ <td> gnptxfsiz </td>\n+ <td> Gets or sets the non-periodic Transmit Size Register</td>\n+ <td> Read/Write</td>\n+ </tr>\n+\n+ <tr>\n+ <td> gpvndctl </td>\n+ <td> Gets or sets the PHY Vendor Control Register</td>\n+ <td> Read/Write</td>\n+ </tr>\n+\n+ <tr>\n+ <td> ggpio </td>\n+ <td> Gets the value in the lower 16-bits of the General Purpose IO Register\n+ or sets the upper 16 bits.</td>\n+ <td> Read/Write</td>\n+ </tr>\n+\n+ <tr>\n+ <td> guid </td>\n+ <td> Gets or sets the value of the User ID Register</td>\n+ <td> Read/Write</td>\n+ </tr>\n+\n+ <tr>\n+ <td> gsnpsid </td>\n+ <td> Gets the value of the Synopsys ID Regester</td>\n+ <td> Read</td>\n+ </tr>\n+\n+ <tr>\n+ <td> devspeed </td>\n+ <td> Gets or sets the device speed setting in the DCFG register</td>\n+ <td> Read/Write</td>\n+ </tr>\n+\n+ <tr>\n+ <td> enumspeed </td>\n+ <td> Gets the device enumeration Speed.</td>\n+ <td> Read</td>\n+ </tr>\n+\n+ <tr>\n+ <td> hptxfsiz </td>\n+ <td> Gets the value of the Host Periodic Transmit FIFO</td>\n+ <td> Read</td>\n+ </tr>\n+\n+ <tr>\n+ <td> hprt0 </td>\n+ <td> Gets or sets the value in the Host Port Control and Status Register</td>\n+ <td> Read/Write</td>\n+ </tr>\n+\n+ <tr>\n+ <td> regoffset </td>\n+ <td> Sets the register offset for the next Register Access</td>\n+ <td> Read/Write</td>\n+ </tr>\n+\n+ <tr>\n+ <td> regvalue </td>\n+ <td> Gets or sets the value of the register at the offset in the regoffset attribute.</td>\n+ <td> Read/Write</td>\n+ </tr>\n+\n+ <tr>\n+ <td> remote_wakeup </td>\n+ <td> On read, shows the status of Remote Wakeup. On write, initiates a remote\n+ wakeup of the host. When bit 0 is 1 and Remote Wakeup is enabled, the Remote\n+ Wakeup signalling bit in the Device Control Register is set for 1\n+ milli-second.</td>\n+ <td> Read/Write</td>\n+ </tr>\n+\n+ <tr>\n+ <td> rem_wakeup_pwrdn </td>\n+ <td> On read, shows the status core - hibernated or not. On write, initiates\n+ a remote wakeup of the device from Hibernation. </td>\n+ <td> Read/Write</td>\n+ </tr>\n+\n+ <tr>\n+ <td> mode_ch_tim_en </td>\n+ <td> This bit is used to enable or disable the host core to wait for 200 PHY\n+ clock cycles at the end of Resume to change the opmode signal to the PHY to 00\n+ after Suspend or LPM. </td>\n+ <td> Read/Write</td>\n+ </tr>\n+\n+ <tr>\n+ <td> fr_interval </td>\n+ <td> On read, shows the value of HFIR Frame Interval. On write, dynamically\n+ reload HFIR register during runtime. The application can write a value to this\n+ register only after the Port Enable bit of the Host Port Control and Status\n+ register (HPRT.PrtEnaPort) has been set </td>\n+ <td> Read/Write</td>\n+ </tr>\n+\n+ <tr>\n+ <td> disconnect_us </td>\n+ <td> On read, shows the status of disconnect_device_us. On write, sets disconnect_us\n+ which causes soft disconnect for 100us. Applicable only for device mode of operation.</td>\n+ <td> Read/Write</td>\n+ </tr>\n+\n+ <tr>\n+ <td> regdump </td>\n+ <td> Dumps the contents of core registers.</td>\n+ <td> Read</td>\n+ </tr>\n+\n+ <tr>\n+ <td> spramdump </td>\n+ <td> Dumps the contents of core registers.</td>\n+ <td> Read</td>\n+ </tr>\n+\n+ <tr>\n+ <td> hcddump </td>\n+ <td> Dumps the current HCD state.</td>\n+ <td> Read</td>\n+ </tr>\n+\n+ <tr>\n+ <td> hcd_frrem </td>\n+ <td> Shows the average value of the Frame Remaining\n+ field in the Host Frame Number/Frame Remaining register when an SOF interrupt\n+ occurs. This can be used to determine the average interrupt latency. Also\n+ shows the average Frame Remaining value for start_transfer and the \"a\" and\n+ \"b\" sample points. The \"a\" and \"b\" sample points may be used during debugging\n+ bto determine how long it takes to execute a section of the HCD code.</td>\n+ <td> Read</td>\n+ </tr>\n+\n+ <tr>\n+ <td> rd_reg_test </td>\n+ <td> Displays the time required to read the GNPTXFSIZ register many times\n+ (the output shows the number of times the register is read).\n+ <td> Read</td>\n+ </tr>\n+\n+ <tr>\n+ <td> wr_reg_test </td>\n+ <td> Displays the time required to write the GNPTXFSIZ register many times\n+ (the output shows the number of times the register is written).\n+ <td> Read</td>\n+ </tr>\n+\n+ <tr>\n+ <td> lpm_response </td>\n+ <td> Gets or sets lpm_response mode. Applicable only in device mode.\n+ <td> Write</td>\n+ </tr>\n+\n+ <tr>\n+ <td> sleep_status </td>\n+ <td> Shows sleep status of device.\n+ <td> Read</td>\n+ </tr>\n+\n+ </table>\n+\n+ Example usage:\n+ To get the current mode:\n+ cat /sys/devices/lm0/mode\n+\n+ To power down the USB:\n+ echo 0 > /sys/devices/lm0/buspower\n+ */\n+\n+#include \"dwc_otg_os_dep.h\"\n+#include \"dwc_os.h\"\n+#include \"dwc_otg_driver.h\"\n+#include \"dwc_otg_attr.h\"\n+#include \"dwc_otg_core_if.h\"\n+#include \"dwc_otg_pcd_if.h\"\n+#include \"dwc_otg_hcd_if.h\"\n+\n+/*\n+ * MACROs for defining sysfs attribute\n+ */\n+#ifdef LM_INTERFACE\n+\n+#define DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_string_) \\\n+static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \\\n+{ \\\n+\tstruct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); \\\n+\tdwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);\t\t\\\n+\tuint32_t val; \\\n+\tval = dwc_otg_get_##_otg_attr_name_ (otg_dev->core_if); \\\n+\treturn sprintf (buf, \"%s = 0x%x\\n\", _string_, val); \\\n+}\n+#define DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_string_) \\\n+static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \\\n+\t\t\t\t\tconst char *buf, size_t count) \\\n+{ \\\n+\tstruct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); \\\n+\tdwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); \\\n+\tuint32_t set = simple_strtoul(buf, NULL, 16); \\\n+\tdwc_otg_set_##_otg_attr_name_(otg_dev->core_if, set);\\\n+\treturn count; \\\n+}\n+\n+#elif defined(PCI_INTERFACE)\n+\n+#define DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_string_) \\\n+static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \\\n+{ \\\n+\tdwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);\t\\\n+\tuint32_t val; \\\n+\tval = dwc_otg_get_##_otg_attr_name_ (otg_dev->core_if); \\\n+\treturn sprintf (buf, \"%s = 0x%x\\n\", _string_, val); \\\n+}\n+#define DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_string_) \\\n+static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \\\n+\t\t\t\t\tconst char *buf, size_t count) \\\n+{ \\\n+\tdwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);  \\\n+\tuint32_t set = simple_strtoul(buf, NULL, 16); \\\n+\tdwc_otg_set_##_otg_attr_name_(otg_dev->core_if, set);\\\n+\treturn count; \\\n+}\n+\n+#elif defined(PLATFORM_INTERFACE)\n+\n+#define DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_string_) \\\n+static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \\\n+{ \\\n+        struct platform_device *platform_dev = \\\n+                container_of(_dev, struct platform_device, dev); \\\n+        dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev);  \\\n+\tuint32_t val; \\\n+\tDWC_PRINTF(\"%s(%p) -> platform_dev %p, otg_dev %p\\n\", \\\n+                    __func__, _dev, platform_dev, otg_dev); \\\n+\tval = dwc_otg_get_##_otg_attr_name_ (otg_dev->core_if); \\\n+\treturn sprintf (buf, \"%s = 0x%x\\n\", _string_, val); \\\n+}\n+#define DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_string_) \\\n+static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \\\n+\t\t\t\t\tconst char *buf, size_t count) \\\n+{ \\\n+        struct platform_device *platform_dev = container_of(_dev, struct platform_device, dev); \\\n+        dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev); \\\n+\tuint32_t set = simple_strtoul(buf, NULL, 16); \\\n+\tdwc_otg_set_##_otg_attr_name_(otg_dev->core_if, set);\\\n+\treturn count; \\\n+}\n+#endif\n+\n+/*\n+ * MACROs for defining sysfs attribute for 32-bit registers\n+ */\n+#ifdef LM_INTERFACE\n+#define DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_string_) \\\n+static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \\\n+{ \\\n+\tstruct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); \\\n+\tdwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); \\\n+\tuint32_t val; \\\n+\tval = dwc_otg_get_##_otg_attr_name_ (otg_dev->core_if); \\\n+\treturn sprintf (buf, \"%s = 0x%08x\\n\", _string_, val); \\\n+}\n+#define DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_string_) \\\n+static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \\\n+\t\t\t\t\tconst char *buf, size_t count) \\\n+{ \\\n+\tstruct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); \\\n+\tdwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); \\\n+\tuint32_t val = simple_strtoul(buf, NULL, 16); \\\n+\tdwc_otg_set_##_otg_attr_name_ (otg_dev->core_if, val); \\\n+\treturn count; \\\n+}\n+#elif defined(PCI_INTERFACE)\n+#define DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_string_) \\\n+static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \\\n+{ \\\n+\tdwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);  \\\n+\tuint32_t val; \\\n+\tval = dwc_otg_get_##_otg_attr_name_ (otg_dev->core_if); \\\n+\treturn sprintf (buf, \"%s = 0x%08x\\n\", _string_, val); \\\n+}\n+#define DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_string_) \\\n+static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \\\n+\t\t\t\t\tconst char *buf, size_t count) \\\n+{ \\\n+\tdwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);  \\\n+\tuint32_t val = simple_strtoul(buf, NULL, 16); \\\n+\tdwc_otg_set_##_otg_attr_name_ (otg_dev->core_if, val); \\\n+\treturn count; \\\n+}\n+\n+#elif defined(PLATFORM_INTERFACE)\n+#include \"dwc_otg_dbg.h\"\n+#define DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_string_) \\\n+static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \\\n+{ \\\n+\tstruct platform_device *platform_dev = container_of(_dev, struct platform_device, dev); \\\n+\tdwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev); \\\n+\tuint32_t val; \\\n+\tDWC_PRINTF(\"%s(%p) -> platform_dev %p, otg_dev %p\\n\", \\\n+                    __func__, _dev, platform_dev, otg_dev); \\\n+\tval = dwc_otg_get_##_otg_attr_name_ (otg_dev->core_if); \\\n+\treturn sprintf (buf, \"%s = 0x%08x\\n\", _string_, val); \\\n+}\n+#define DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_string_) \\\n+static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \\\n+\t\t\t\t\tconst char *buf, size_t count) \\\n+{ \\\n+\tstruct platform_device *platform_dev = container_of(_dev, struct platform_device, dev); \\\n+\tdwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev); \\\n+\tuint32_t val = simple_strtoul(buf, NULL, 16); \\\n+\tdwc_otg_set_##_otg_attr_name_ (otg_dev->core_if, val); \\\n+\treturn count; \\\n+}\n+\n+#endif\n+\n+#define DWC_OTG_DEVICE_ATTR_BITFIELD_RW(_otg_attr_name_,_string_) \\\n+DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_string_) \\\n+DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_string_) \\\n+DEVICE_ATTR(_otg_attr_name_,0644,_otg_attr_name_##_show,_otg_attr_name_##_store);\n+\n+#define DWC_OTG_DEVICE_ATTR_BITFIELD_RO(_otg_attr_name_,_string_) \\\n+DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_string_) \\\n+DEVICE_ATTR(_otg_attr_name_,0444,_otg_attr_name_##_show,NULL);\n+\n+#define DWC_OTG_DEVICE_ATTR_REG32_RW(_otg_attr_name_,_addr_,_string_) \\\n+DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_string_) \\\n+DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_string_) \\\n+DEVICE_ATTR(_otg_attr_name_,0644,_otg_attr_name_##_show,_otg_attr_name_##_store);\n+\n+#define DWC_OTG_DEVICE_ATTR_REG32_RO(_otg_attr_name_,_addr_,_string_) \\\n+DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_string_) \\\n+DEVICE_ATTR(_otg_attr_name_,0444,_otg_attr_name_##_show,NULL);\n+\n+/** @name Functions for Show/Store of Attributes */\n+/**@{*/\n+\n+/**\n+ * Helper function returning the otg_device structure of the given device\n+ */\n+static dwc_otg_device_t *dwc_otg_drvdev(struct device *_dev)\n+{\n+        dwc_otg_device_t *otg_dev;\n+        DWC_OTG_GETDRVDEV(otg_dev, _dev);\n+        return otg_dev;\n+}\n+\n+/**\n+ * Show the register offset of the Register Access.\n+ */\n+static ssize_t regoffset_show(struct device *_dev,\n+\t\t\t      struct device_attribute *attr, char *buf)\n+{\n+        dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);\n+\treturn snprintf(buf, sizeof(\"0xFFFFFFFF\\n\") + 1, \"0x%08x\\n\",\n+\t\t\totg_dev->os_dep.reg_offset);\n+}\n+\n+/**\n+ * Set the register offset for the next Register Access \tRead/Write\n+ */\n+static ssize_t regoffset_store(struct device *_dev,\n+\t\t\t       struct device_attribute *attr,\n+\t\t\t       const char *buf, size_t count)\n+{\n+        dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);\n+\tuint32_t offset = simple_strtoul(buf, NULL, 16);\n+#if defined(LM_INTERFACE) || defined(PLATFORM_INTERFACE)\n+\tif (offset < SZ_256K) {\n+#elif  defined(PCI_INTERFACE)\n+\tif (offset < 0x00040000) {\n+#endif\n+\t\totg_dev->os_dep.reg_offset = offset;\n+\t} else {\n+\t\tdev_err(_dev, \"invalid offset\\n\");\n+\t}\n+\n+\treturn count;\n+}\n+\n+DEVICE_ATTR(regoffset, S_IRUGO | S_IWUSR, regoffset_show, regoffset_store);\n+\n+/**\n+ * Show the value of the register at the offset in the reg_offset\n+ * attribute.\n+ */\n+static ssize_t regvalue_show(struct device *_dev,\n+\t\t\t     struct device_attribute *attr, char *buf)\n+{\n+        dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);\n+\tuint32_t val;\n+\tvolatile uint32_t *addr;\n+\n+\tif (otg_dev->os_dep.reg_offset != 0xFFFFFFFF && 0 != otg_dev->os_dep.base) {\n+\t\t/* Calculate the address */\n+\t\taddr = (uint32_t *) (otg_dev->os_dep.reg_offset +\n+\t\t\t\t     (uint8_t *) otg_dev->os_dep.base);\n+\t\tval = DWC_READ_REG32(addr);\n+\t\treturn snprintf(buf,\n+\t\t\t\tsizeof(\"Reg@0xFFFFFFFF = 0xFFFFFFFF\\n\") + 1,\n+\t\t\t\t\"Reg@0x%06x = 0x%08x\\n\", otg_dev->os_dep.reg_offset,\n+\t\t\t\tval);\n+\t} else {\n+\t\tdev_err(_dev, \"Invalid offset (0x%0x)\\n\", otg_dev->os_dep.reg_offset);\n+\t\treturn sprintf(buf, \"invalid offset\\n\");\n+\t}\n+}\n+\n+/**\n+ * Store the value in the register at the offset in the reg_offset\n+ * attribute.\n+ *\n+ */\n+static ssize_t regvalue_store(struct device *_dev,\n+\t\t\t      struct device_attribute *attr,\n+\t\t\t      const char *buf, size_t count)\n+{\n+        dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);\n+\tvolatile uint32_t *addr;\n+\tuint32_t val = simple_strtoul(buf, NULL, 16);\n+\t//dev_dbg(_dev, \"Offset=0x%08x Val=0x%08x\\n\", otg_dev->reg_offset, val);\n+\tif (otg_dev->os_dep.reg_offset != 0xFFFFFFFF && 0 != otg_dev->os_dep.base) {\n+\t\t/* Calculate the address */\n+\t\taddr = (uint32_t *) (otg_dev->os_dep.reg_offset +\n+\t\t\t\t     (uint8_t *) otg_dev->os_dep.base);\n+\t\tDWC_WRITE_REG32(addr, val);\n+\t} else {\n+\t\tdev_err(_dev, \"Invalid Register Offset (0x%08x)\\n\",\n+\t\t\totg_dev->os_dep.reg_offset);\n+\t}\n+\treturn count;\n+}\n+\n+DEVICE_ATTR(regvalue, S_IRUGO | S_IWUSR, regvalue_show, regvalue_store);\n+\n+/*\n+ * Attributes\n+ */\n+DWC_OTG_DEVICE_ATTR_BITFIELD_RO(mode, \"Mode\");\n+DWC_OTG_DEVICE_ATTR_BITFIELD_RW(hnpcapable, \"HNPCapable\");\n+DWC_OTG_DEVICE_ATTR_BITFIELD_RW(srpcapable, \"SRPCapable\");\n+DWC_OTG_DEVICE_ATTR_BITFIELD_RW(hsic_connect, \"HSIC Connect\");\n+DWC_OTG_DEVICE_ATTR_BITFIELD_RW(inv_sel_hsic, \"Invert Select HSIC\");\n+\n+//DWC_OTG_DEVICE_ATTR_BITFIELD_RW(buspower,&(otg_dev->core_if->core_global_regs->gotgctl),(1<<8),8,\"Mode\");\n+//DWC_OTG_DEVICE_ATTR_BITFIELD_RW(bussuspend,&(otg_dev->core_if->core_global_regs->gotgctl),(1<<8),8,\"Mode\");\n+DWC_OTG_DEVICE_ATTR_BITFIELD_RO(busconnected, \"Bus Connected\");\n+\n+DWC_OTG_DEVICE_ATTR_REG32_RW(gotgctl, 0, \"GOTGCTL\");\n+DWC_OTG_DEVICE_ATTR_REG32_RW(gusbcfg,\n+\t\t\t     &(otg_dev->core_if->core_global_regs->gusbcfg),\n+\t\t\t     \"GUSBCFG\");\n+DWC_OTG_DEVICE_ATTR_REG32_RW(grxfsiz,\n+\t\t\t     &(otg_dev->core_if->core_global_regs->grxfsiz),\n+\t\t\t     \"GRXFSIZ\");\n+DWC_OTG_DEVICE_ATTR_REG32_RW(gnptxfsiz,\n+\t\t\t     &(otg_dev->core_if->core_global_regs->gnptxfsiz),\n+\t\t\t     \"GNPTXFSIZ\");\n+DWC_OTG_DEVICE_ATTR_REG32_RW(gpvndctl,\n+\t\t\t     &(otg_dev->core_if->core_global_regs->gpvndctl),\n+\t\t\t     \"GPVNDCTL\");\n+DWC_OTG_DEVICE_ATTR_REG32_RW(ggpio,\n+\t\t\t     &(otg_dev->core_if->core_global_regs->ggpio),\n+\t\t\t     \"GGPIO\");\n+DWC_OTG_DEVICE_ATTR_REG32_RW(guid, &(otg_dev->core_if->core_global_regs->guid),\n+\t\t\t     \"GUID\");\n+DWC_OTG_DEVICE_ATTR_REG32_RO(gsnpsid,\n+\t\t\t     &(otg_dev->core_if->core_global_regs->gsnpsid),\n+\t\t\t     \"GSNPSID\");\n+DWC_OTG_DEVICE_ATTR_BITFIELD_RW(devspeed, \"Device Speed\");\n+DWC_OTG_DEVICE_ATTR_BITFIELD_RO(enumspeed, \"Device Enumeration Speed\");\n+\n+DWC_OTG_DEVICE_ATTR_REG32_RO(hptxfsiz,\n+\t\t\t     &(otg_dev->core_if->core_global_regs->hptxfsiz),\n+\t\t\t     \"HPTXFSIZ\");\n+DWC_OTG_DEVICE_ATTR_REG32_RW(hprt0, otg_dev->core_if->host_if->hprt0, \"HPRT0\");\n+\n+/**\n+ * @todo Add code to initiate the HNP.\n+ */\n+/**\n+ * Show the HNP status bit\n+ */\n+static ssize_t hnp_show(struct device *_dev,\n+\t\t\tstruct device_attribute *attr, char *buf)\n+{\n+        dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);\n+\treturn sprintf(buf, \"HstNegScs = 0x%x\\n\",\n+\t\t       dwc_otg_get_hnpstatus(otg_dev->core_if));\n+}\n+\n+/**\n+ * Set the HNP Request bit\n+ */\n+static ssize_t hnp_store(struct device *_dev,\n+\t\t\t struct device_attribute *attr,\n+\t\t\t const char *buf, size_t count)\n+{\n+        dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);\n+\tuint32_t in = simple_strtoul(buf, NULL, 16);\n+\tdwc_otg_set_hnpreq(otg_dev->core_if, in);\n+\treturn count;\n+}\n+\n+DEVICE_ATTR(hnp, 0644, hnp_show, hnp_store);\n+\n+/**\n+ * @todo Add code to initiate the SRP.\n+ */\n+/**\n+ * Show the SRP status bit\n+ */\n+static ssize_t srp_show(struct device *_dev,\n+\t\t\tstruct device_attribute *attr, char *buf)\n+{\n+#ifndef DWC_HOST_ONLY\n+        dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);\n+\treturn sprintf(buf, \"SesReqScs = 0x%x\\n\",\n+\t\t       dwc_otg_get_srpstatus(otg_dev->core_if));\n+#else\n+\treturn sprintf(buf, \"Host Only Mode!\\n\");\n+#endif\n+}\n+\n+/**\n+ * Set the SRP Request bit\n+ */\n+static ssize_t srp_store(struct device *_dev,\n+\t\t\t struct device_attribute *attr,\n+\t\t\t const char *buf, size_t count)\n+{\n+#ifndef DWC_HOST_ONLY\n+        dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);\n+\tdwc_otg_pcd_initiate_srp(otg_dev->pcd);\n+#endif\n+\treturn count;\n+}\n+\n+DEVICE_ATTR(srp, 0644, srp_show, srp_store);\n+\n+/**\n+ * @todo Need to do more for power on/off?\n+ */\n+/**\n+ * Show the Bus Power status\n+ */\n+static ssize_t buspower_show(struct device *_dev,\n+\t\t\t     struct device_attribute *attr, char *buf)\n+{\n+        dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);\n+\treturn sprintf(buf, \"Bus Power = 0x%x\\n\",\n+\t\t       dwc_otg_get_prtpower(otg_dev->core_if));\n+}\n+\n+/**\n+ * Set the Bus Power status\n+ */\n+static ssize_t buspower_store(struct device *_dev,\n+\t\t\t      struct device_attribute *attr,\n+\t\t\t      const char *buf, size_t count)\n+{\n+        dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);\n+\tuint32_t on = simple_strtoul(buf, NULL, 16);\n+\tdwc_otg_set_prtpower(otg_dev->core_if, on);\n+\treturn count;\n+}\n+\n+DEVICE_ATTR(buspower, 0644, buspower_show, buspower_store);\n+\n+/**\n+ * @todo Need to do more for suspend?\n+ */\n+/**\n+ * Show the Bus Suspend status\n+ */\n+static ssize_t bussuspend_show(struct device *_dev,\n+\t\t\t       struct device_attribute *attr, char *buf)\n+{\n+        dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);\n+\treturn sprintf(buf, \"Bus Suspend = 0x%x\\n\",\n+\t\t       dwc_otg_get_prtsuspend(otg_dev->core_if));\n+}\n+\n+/**\n+ * Set the Bus Suspend status\n+ */\n+static ssize_t bussuspend_store(struct device *_dev,\n+\t\t\t\tstruct device_attribute *attr,\n+\t\t\t\tconst char *buf, size_t count)\n+{\n+        dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);\n+\tuint32_t in = simple_strtoul(buf, NULL, 16);\n+\tdwc_otg_set_prtsuspend(otg_dev->core_if, in);\n+\treturn count;\n+}\n+\n+DEVICE_ATTR(bussuspend, 0644, bussuspend_show, bussuspend_store);\n+\n+/**\n+ * Show the Mode Change Ready Timer status\n+ */\n+static ssize_t mode_ch_tim_en_show(struct device *_dev,\n+\t\t\t\t   struct device_attribute *attr, char *buf)\n+{\n+        dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);\n+\treturn sprintf(buf, \"Mode Change Ready Timer Enable = 0x%x\\n\",\n+\t\t       dwc_otg_get_mode_ch_tim(otg_dev->core_if));\n+}\n+\n+/**\n+ * Set the Mode Change Ready Timer status\n+ */\n+static ssize_t mode_ch_tim_en_store(struct device *_dev,\n+\t\t\t\t    struct device_attribute *attr,\n+\t\t\t\t    const char *buf, size_t count)\n+{\n+        dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);\n+\tuint32_t in = simple_strtoul(buf, NULL, 16);\n+\tdwc_otg_set_mode_ch_tim(otg_dev->core_if, in);\n+\treturn count;\n+}\n+\n+DEVICE_ATTR(mode_ch_tim_en, 0644, mode_ch_tim_en_show, mode_ch_tim_en_store);\n+\n+/**\n+ * Show the value of HFIR Frame Interval bitfield\n+ */\n+static ssize_t fr_interval_show(struct device *_dev,\n+\t\t\t\tstruct device_attribute *attr, char *buf)\n+{\n+        dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);\n+\treturn sprintf(buf, \"Frame Interval = 0x%x\\n\",\n+\t\t       dwc_otg_get_fr_interval(otg_dev->core_if));\n+}\n+\n+/**\n+ * Set the HFIR Frame Interval value\n+ */\n+static ssize_t fr_interval_store(struct device *_dev,\n+\t\t\t\t struct device_attribute *attr,\n+\t\t\t\t const char *buf, size_t count)\n+{\n+        dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);\n+\tuint32_t in = simple_strtoul(buf, NULL, 10);\n+\tdwc_otg_set_fr_interval(otg_dev->core_if, in);\n+\treturn count;\n+}\n+\n+DEVICE_ATTR(fr_interval, 0644, fr_interval_show, fr_interval_store);\n+\n+/**\n+ * Show the status of Remote Wakeup.\n+ */\n+static ssize_t remote_wakeup_show(struct device *_dev,\n+\t\t\t\t  struct device_attribute *attr, char *buf)\n+{\n+#ifndef DWC_HOST_ONLY\n+        dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);\n+\n+\treturn sprintf(buf,\n+\t\t       \"Remote Wakeup Sig = %d Enabled = %d LPM Remote Wakeup = %d\\n\",\n+\t\t       dwc_otg_get_remotewakesig(otg_dev->core_if),\n+\t\t       dwc_otg_pcd_get_rmwkup_enable(otg_dev->pcd),\n+\t\t       dwc_otg_get_lpm_remotewakeenabled(otg_dev->core_if));\n+#else\n+\treturn sprintf(buf, \"Host Only Mode!\\n\");\n+#endif /* DWC_HOST_ONLY */\n+}\n+\n+/**\n+ * Initiate a remote wakeup of the host.  The Device control register\n+ * Remote Wakeup Signal bit is written if the PCD Remote wakeup enable\n+ * flag is set.\n+ *\n+ */\n+static ssize_t remote_wakeup_store(struct device *_dev,\n+\t\t\t\t   struct device_attribute *attr,\n+\t\t\t\t   const char *buf, size_t count)\n+{\n+#ifndef DWC_HOST_ONLY\n+        dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);\n+\tuint32_t val = simple_strtoul(buf, NULL, 16);\n+\n+\tif (val & 1) {\n+\t\tdwc_otg_pcd_remote_wakeup(otg_dev->pcd, 1);\n+\t} else {\n+\t\tdwc_otg_pcd_remote_wakeup(otg_dev->pcd, 0);\n+\t}\n+#endif /* DWC_HOST_ONLY */\n+\treturn count;\n+}\n+\n+DEVICE_ATTR(remote_wakeup, S_IRUGO | S_IWUSR, remote_wakeup_show,\n+\t    remote_wakeup_store);\n+\n+/**\n+ * Show the whether core is hibernated or not.\n+ */\n+static ssize_t rem_wakeup_pwrdn_show(struct device *_dev,\n+\t\t\t\t     struct device_attribute *attr, char *buf)\n+{\n+#ifndef DWC_HOST_ONLY\n+        dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);\n+\n+\tif (dwc_otg_get_core_state(otg_dev->core_if)) {\n+\t\tDWC_PRINTF(\"Core is in hibernation\\n\");\n+\t} else {\n+\t\tDWC_PRINTF(\"Core is not in hibernation\\n\");\n+\t}\n+#endif /* DWC_HOST_ONLY */\n+\treturn 0;\n+}\n+\n+extern int dwc_otg_device_hibernation_restore(dwc_otg_core_if_t * core_if,\n+\t\t\t\t\t      int rem_wakeup, int reset);\n+\n+/**\n+ * Initiate a remote wakeup of the device to exit from hibernation.\n+ */\n+static ssize_t rem_wakeup_pwrdn_store(struct device *_dev,\n+\t\t\t\t      struct device_attribute *attr,\n+\t\t\t\t      const char *buf, size_t count)\n+{\n+#ifndef DWC_HOST_ONLY\n+        dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);\n+\tdwc_otg_device_hibernation_restore(otg_dev->core_if, 1, 0);\n+#endif\n+\treturn count;\n+}\n+\n+DEVICE_ATTR(rem_wakeup_pwrdn, S_IRUGO | S_IWUSR, rem_wakeup_pwrdn_show,\n+\t    rem_wakeup_pwrdn_store);\n+\n+static ssize_t disconnect_us(struct device *_dev,\n+\t\t\t     struct device_attribute *attr,\n+\t\t\t     const char *buf, size_t count)\n+{\n+\n+#ifndef DWC_HOST_ONLY\n+        dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);\n+\tuint32_t val = simple_strtoul(buf, NULL, 16);\n+\tDWC_PRINTF(\"The Passed value is %04x\\n\", val);\n+\n+\tdwc_otg_pcd_disconnect_us(otg_dev->pcd, 50);\n+\n+#endif /* DWC_HOST_ONLY */\n+\treturn count;\n+}\n+\n+DEVICE_ATTR(disconnect_us, S_IWUSR, 0, disconnect_us);\n+\n+/**\n+ * Dump global registers and either host or device registers (depending on the\n+ * current mode of the core).\n+ */\n+static ssize_t regdump_show(struct device *_dev,\n+\t\t\t    struct device_attribute *attr, char *buf)\n+{\n+        dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);\n+\n+\tdwc_otg_dump_global_registers(otg_dev->core_if);\n+\tif (dwc_otg_is_host_mode(otg_dev->core_if)) {\n+\t\tdwc_otg_dump_host_registers(otg_dev->core_if);\n+\t} else {\n+\t\tdwc_otg_dump_dev_registers(otg_dev->core_if);\n+\n+\t}\n+\treturn sprintf(buf, \"Register Dump\\n\");\n+}\n+\n+DEVICE_ATTR(regdump, S_IRUGO, regdump_show, 0);\n+\n+/**\n+ * Dump global registers and either host or device registers (depending on the\n+ * current mode of the core).\n+ */\n+static ssize_t spramdump_show(struct device *_dev,\n+\t\t\t      struct device_attribute *attr, char *buf)\n+{\n+#if 0\n+\tdwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);\n+\n+\tdwc_otg_dump_spram(otg_dev->core_if);\n+#endif\n+\n+\treturn sprintf(buf, \"SPRAM Dump\\n\");\n+}\n+\n+DEVICE_ATTR(spramdump, S_IRUGO, spramdump_show, 0);\n+\n+/**\n+ * Dump the current hcd state.\n+ */\n+static ssize_t hcddump_show(struct device *_dev,\n+\t\t\t    struct device_attribute *attr, char *buf)\n+{\n+#ifndef DWC_DEVICE_ONLY\n+        dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);\n+\tdwc_otg_hcd_dump_state(otg_dev->hcd);\n+#endif /* DWC_DEVICE_ONLY */\n+\treturn sprintf(buf, \"HCD Dump\\n\");\n+}\n+\n+DEVICE_ATTR(hcddump, S_IRUGO, hcddump_show, 0);\n+\n+/**\n+ * Dump the average frame remaining at SOF. This can be used to\n+ * determine average interrupt latency. Frame remaining is also shown for\n+ * start transfer and two additional sample points.\n+ */\n+static ssize_t hcd_frrem_show(struct device *_dev,\n+\t\t\t      struct device_attribute *attr, char *buf)\n+{\n+#ifndef DWC_DEVICE_ONLY\n+        dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);\n+\n+\tdwc_otg_hcd_dump_frrem(otg_dev->hcd);\n+#endif /* DWC_DEVICE_ONLY */\n+\treturn sprintf(buf, \"HCD Dump Frame Remaining\\n\");\n+}\n+\n+DEVICE_ATTR(hcd_frrem, S_IRUGO, hcd_frrem_show, 0);\n+\n+/**\n+ * Displays the time required to read the GNPTXFSIZ register many times (the\n+ * output shows the number of times the register is read).\n+ */\n+#define RW_REG_COUNT 10000000\n+#define MSEC_PER_JIFFIE 1000/HZ\n+static ssize_t rd_reg_test_show(struct device *_dev,\n+\t\t\t\tstruct device_attribute *attr, char *buf)\n+{\n+        dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);\n+\tint i;\n+\tint time;\n+\tint start_jiffies;\n+\n+\tprintk(\"HZ %d, MSEC_PER_JIFFIE %d, loops_per_jiffy %lu\\n\",\n+\t       HZ, MSEC_PER_JIFFIE, loops_per_jiffy);\n+\tstart_jiffies = jiffies;\n+\tfor (i = 0; i < RW_REG_COUNT; i++) {\n+\t\tdwc_otg_get_gnptxfsiz(otg_dev->core_if);\n+\t}\n+\ttime = jiffies - start_jiffies;\n+\treturn sprintf(buf,\n+\t\t       \"Time to read GNPTXFSIZ reg %d times: %d msecs (%d jiffies)\\n\",\n+\t\t       RW_REG_COUNT, time * MSEC_PER_JIFFIE, time);\n+}\n+\n+DEVICE_ATTR(rd_reg_test, S_IRUGO, rd_reg_test_show, 0);\n+\n+/**\n+ * Displays the time required to write the GNPTXFSIZ register many times (the\n+ * output shows the number of times the register is written).\n+ */\n+static ssize_t wr_reg_test_show(struct device *_dev,\n+\t\t\t\tstruct device_attribute *attr, char *buf)\n+{\n+        dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);\n+\tuint32_t reg_val;\n+\tint i;\n+\tint time;\n+\tint start_jiffies;\n+\n+\tprintk(\"HZ %d, MSEC_PER_JIFFIE %d, loops_per_jiffy %lu\\n\",\n+\t       HZ, MSEC_PER_JIFFIE, loops_per_jiffy);\n+\treg_val = dwc_otg_get_gnptxfsiz(otg_dev->core_if);\n+\tstart_jiffies = jiffies;\n+\tfor (i = 0; i < RW_REG_COUNT; i++) {\n+\t\tdwc_otg_set_gnptxfsiz(otg_dev->core_if, reg_val);\n+\t}\n+\ttime = jiffies - start_jiffies;\n+\treturn sprintf(buf,\n+\t\t       \"Time to write GNPTXFSIZ reg %d times: %d msecs (%d jiffies)\\n\",\n+\t\t       RW_REG_COUNT, time * MSEC_PER_JIFFIE, time);\n+}\n+\n+DEVICE_ATTR(wr_reg_test, S_IRUGO, wr_reg_test_show, 0);\n+\n+#ifdef CONFIG_USB_DWC_OTG_LPM\n+\n+/**\n+* Show the lpm_response attribute.\n+*/\n+static ssize_t lpmresp_show(struct device *_dev,\n+\t\t\t    struct device_attribute *attr, char *buf)\n+{\n+        dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);\n+\n+\tif (!dwc_otg_get_param_lpm_enable(otg_dev->core_if))\n+\t\treturn sprintf(buf, \"** LPM is DISABLED **\\n\");\n+\n+\tif (!dwc_otg_is_device_mode(otg_dev->core_if)) {\n+\t\treturn sprintf(buf, \"** Current mode is not device mode\\n\");\n+\t}\n+\treturn sprintf(buf, \"lpm_response = %d\\n\",\n+\t\t       dwc_otg_get_lpmresponse(otg_dev->core_if));\n+}\n+\n+/**\n+* Store the lpm_response attribute.\n+*/\n+static ssize_t lpmresp_store(struct device *_dev,\n+\t\t\t     struct device_attribute *attr,\n+\t\t\t     const char *buf, size_t count)\n+{\n+        dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);\n+\tuint32_t val = simple_strtoul(buf, NULL, 16);\n+\n+\tif (!dwc_otg_get_param_lpm_enable(otg_dev->core_if)) {\n+\t\treturn 0;\n+\t}\n+\n+\tif (!dwc_otg_is_device_mode(otg_dev->core_if)) {\n+\t\treturn 0;\n+\t}\n+\n+\tdwc_otg_set_lpmresponse(otg_dev->core_if, val);\n+\treturn count;\n+}\n+\n+DEVICE_ATTR(lpm_response, S_IRUGO | S_IWUSR, lpmresp_show, lpmresp_store);\n+\n+/**\n+* Show the sleep_status attribute.\n+*/\n+static ssize_t sleepstatus_show(struct device *_dev,\n+\t\t\t\tstruct device_attribute *attr, char *buf)\n+{\n+        dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);\n+\treturn sprintf(buf, \"Sleep Status = %d\\n\",\n+\t\t       dwc_otg_get_lpm_portsleepstatus(otg_dev->core_if));\n+}\n+\n+/**\n+ * Store the sleep_status attribure.\n+ */\n+static ssize_t sleepstatus_store(struct device *_dev,\n+\t\t\t\t struct device_attribute *attr,\n+\t\t\t\t const char *buf, size_t count)\n+{\n+        dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);\n+\tdwc_otg_core_if_t *core_if = otg_dev->core_if;\n+\n+\tif (dwc_otg_get_lpm_portsleepstatus(otg_dev->core_if)) {\n+\t\tif (dwc_otg_is_host_mode(core_if)) {\n+\n+\t\t\tDWC_PRINTF(\"Host initiated resume\\n\");\n+\t\t\tdwc_otg_set_prtresume(otg_dev->core_if, 1);\n+\t\t}\n+\t}\n+\n+\treturn count;\n+}\n+\n+DEVICE_ATTR(sleep_status, S_IRUGO | S_IWUSR, sleepstatus_show,\n+\t    sleepstatus_store);\n+\n+#endif /* CONFIG_USB_DWC_OTG_LPM_ENABLE */\n+\n+/**@}*/\n+\n+/**\n+ * Create the device files\n+ */\n+void dwc_otg_attr_create(\n+#ifdef LM_INTERFACE\n+\tstruct lm_device *dev\n+#elif  defined(PCI_INTERFACE)\n+\tstruct pci_dev *dev\n+#elif  defined(PLATFORM_INTERFACE)\n+        struct platform_device *dev\n+#endif\n+    )\n+{\n+\tint error;\n+\n+\terror = device_create_file(&dev->dev, &dev_attr_regoffset);\n+\terror = device_create_file(&dev->dev, &dev_attr_regvalue);\n+\terror = device_create_file(&dev->dev, &dev_attr_mode);\n+\terror = device_create_file(&dev->dev, &dev_attr_hnpcapable);\n+\terror = device_create_file(&dev->dev, &dev_attr_srpcapable);\n+\terror = device_create_file(&dev->dev, &dev_attr_hsic_connect);\n+\terror = device_create_file(&dev->dev, &dev_attr_inv_sel_hsic);\n+\terror = device_create_file(&dev->dev, &dev_attr_hnp);\n+\terror = device_create_file(&dev->dev, &dev_attr_srp);\n+\terror = device_create_file(&dev->dev, &dev_attr_buspower);\n+\terror = device_create_file(&dev->dev, &dev_attr_bussuspend);\n+\terror = device_create_file(&dev->dev, &dev_attr_mode_ch_tim_en);\n+\terror = device_create_file(&dev->dev, &dev_attr_fr_interval);\n+\terror = device_create_file(&dev->dev, &dev_attr_busconnected);\n+\terror = device_create_file(&dev->dev, &dev_attr_gotgctl);\n+\terror = device_create_file(&dev->dev, &dev_attr_gusbcfg);\n+\terror = device_create_file(&dev->dev, &dev_attr_grxfsiz);\n+\terror = device_create_file(&dev->dev, &dev_attr_gnptxfsiz);\n+\terror = device_create_file(&dev->dev, &dev_attr_gpvndctl);\n+\terror = device_create_file(&dev->dev, &dev_attr_ggpio);\n+\terror = device_create_file(&dev->dev, &dev_attr_guid);\n+\terror = device_create_file(&dev->dev, &dev_attr_gsnpsid);\n+\terror = device_create_file(&dev->dev, &dev_attr_devspeed);\n+\terror = device_create_file(&dev->dev, &dev_attr_enumspeed);\n+\terror = device_create_file(&dev->dev, &dev_attr_hptxfsiz);\n+\terror = device_create_file(&dev->dev, &dev_attr_hprt0);\n+\terror = device_create_file(&dev->dev, &dev_attr_remote_wakeup);\n+\terror = device_create_file(&dev->dev, &dev_attr_rem_wakeup_pwrdn);\n+\terror = device_create_file(&dev->dev, &dev_attr_disconnect_us);\n+\terror = device_create_file(&dev->dev, &dev_attr_regdump);\n+\terror = device_create_file(&dev->dev, &dev_attr_spramdump);\n+\terror = device_create_file(&dev->dev, &dev_attr_hcddump);\n+\terror = device_create_file(&dev->dev, &dev_attr_hcd_frrem);\n+\terror = device_create_file(&dev->dev, &dev_attr_rd_reg_test);\n+\terror = device_create_file(&dev->dev, &dev_attr_wr_reg_test);\n+#ifdef CONFIG_USB_DWC_OTG_LPM\n+\terror = device_create_file(&dev->dev, &dev_attr_lpm_response);\n+\terror = device_create_file(&dev->dev, &dev_attr_sleep_status);\n+#endif\n+}\n+\n+/**\n+ * Remove the device files\n+ */\n+void dwc_otg_attr_remove(\n+#ifdef LM_INTERFACE\n+\tstruct lm_device *dev\n+#elif  defined(PCI_INTERFACE)\n+\tstruct pci_dev *dev\n+#elif  defined(PLATFORM_INTERFACE)\n+\tstruct platform_device *dev\n+#endif\n+    )\n+{\n+\tdevice_remove_file(&dev->dev, &dev_attr_regoffset);\n+\tdevice_remove_file(&dev->dev, &dev_attr_regvalue);\n+\tdevice_remove_file(&dev->dev, &dev_attr_mode);\n+\tdevice_remove_file(&dev->dev, &dev_attr_hnpcapable);\n+\tdevice_remove_file(&dev->dev, &dev_attr_srpcapable);\n+\tdevice_remove_file(&dev->dev, &dev_attr_hsic_connect);\n+\tdevice_remove_file(&dev->dev, &dev_attr_inv_sel_hsic);\n+\tdevice_remove_file(&dev->dev, &dev_attr_hnp);\n+\tdevice_remove_file(&dev->dev, &dev_attr_srp);\n+\tdevice_remove_file(&dev->dev, &dev_attr_buspower);\n+\tdevice_remove_file(&dev->dev, &dev_attr_bussuspend);\n+\tdevice_remove_file(&dev->dev, &dev_attr_mode_ch_tim_en);\n+\tdevice_remove_file(&dev->dev, &dev_attr_fr_interval);\n+\tdevice_remove_file(&dev->dev, &dev_attr_busconnected);\n+\tdevice_remove_file(&dev->dev, &dev_attr_gotgctl);\n+\tdevice_remove_file(&dev->dev, &dev_attr_gusbcfg);\n+\tdevice_remove_file(&dev->dev, &dev_attr_grxfsiz);\n+\tdevice_remove_file(&dev->dev, &dev_attr_gnptxfsiz);\n+\tdevice_remove_file(&dev->dev, &dev_attr_gpvndctl);\n+\tdevice_remove_file(&dev->dev, &dev_attr_ggpio);\n+\tdevice_remove_file(&dev->dev, &dev_attr_guid);\n+\tdevice_remove_file(&dev->dev, &dev_attr_gsnpsid);\n+\tdevice_remove_file(&dev->dev, &dev_attr_devspeed);\n+\tdevice_remove_file(&dev->dev, &dev_attr_enumspeed);\n+\tdevice_remove_file(&dev->dev, &dev_attr_hptxfsiz);\n+\tdevice_remove_file(&dev->dev, &dev_attr_hprt0);\n+\tdevice_remove_file(&dev->dev, &dev_attr_remote_wakeup);\n+\tdevice_remove_file(&dev->dev, &dev_attr_rem_wakeup_pwrdn);\n+\tdevice_remove_file(&dev->dev, &dev_attr_disconnect_us);\n+\tdevice_remove_file(&dev->dev, &dev_attr_regdump);\n+\tdevice_remove_file(&dev->dev, &dev_attr_spramdump);\n+\tdevice_remove_file(&dev->dev, &dev_attr_hcddump);\n+\tdevice_remove_file(&dev->dev, &dev_attr_hcd_frrem);\n+\tdevice_remove_file(&dev->dev, &dev_attr_rd_reg_test);\n+\tdevice_remove_file(&dev->dev, &dev_attr_wr_reg_test);\n+#ifdef CONFIG_USB_DWC_OTG_LPM\n+\tdevice_remove_file(&dev->dev, &dev_attr_lpm_response);\n+\tdevice_remove_file(&dev->dev, &dev_attr_sleep_status);\n+#endif\n+}\n--- /dev/null\n+++ b/drivers/usb/host/dwc_otg/dwc_otg_attr.h\n@@ -0,0 +1,89 @@\n+/* ==========================================================================\n+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_attr.h $\n+ * $Revision: #13 $\n+ * $Date: 2010/06/21 $\n+ * $Change: 1532021 $\n+ *\n+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,\n+ * \"Software\") is an Unsupported proprietary work of Synopsys, Inc. unless\n+ * otherwise expressly agreed to in writing between Synopsys and you.\n+ *\n+ * The Software IS NOT an item of Licensed Software or Licensed Product under\n+ * any End User Software License Agreement or Agreement for Licensed Product\n+ * with Synopsys or any supplement thereto. You are permitted to use and\n+ * redistribute this Software in source and binary forms, with or without\n+ * modification, provided that redistributions of source code must retain this\n+ * notice. You may not view, use, disclose, copy or distribute this file or\n+ * any information contained herein except pursuant to this license grant from\n+ * Synopsys. If you do not agree with this notice, including the disclaimer\n+ * below, then you are not authorized to use the Software.\n+ *\n+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN \"AS IS\" BASIS\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,\n+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH\n+ * DAMAGE.\n+ * ========================================================================== */\n+\n+#if !defined(__DWC_OTG_ATTR_H__)\n+#define __DWC_OTG_ATTR_H__\n+\n+/** @file\n+ * This file contains the interface to the Linux device attributes.\n+ */\n+extern struct device_attribute dev_attr_regoffset;\n+extern struct device_attribute dev_attr_regvalue;\n+\n+extern struct device_attribute dev_attr_mode;\n+extern struct device_attribute dev_attr_hnpcapable;\n+extern struct device_attribute dev_attr_srpcapable;\n+extern struct device_attribute dev_attr_hnp;\n+extern struct device_attribute dev_attr_srp;\n+extern struct device_attribute dev_attr_buspower;\n+extern struct device_attribute dev_attr_bussuspend;\n+extern struct device_attribute dev_attr_mode_ch_tim_en;\n+extern struct device_attribute dev_attr_fr_interval;\n+extern struct device_attribute dev_attr_busconnected;\n+extern struct device_attribute dev_attr_gotgctl;\n+extern struct device_attribute dev_attr_gusbcfg;\n+extern struct device_attribute dev_attr_grxfsiz;\n+extern struct device_attribute dev_attr_gnptxfsiz;\n+extern struct device_attribute dev_attr_gpvndctl;\n+extern struct device_attribute dev_attr_ggpio;\n+extern struct device_attribute dev_attr_guid;\n+extern struct device_attribute dev_attr_gsnpsid;\n+extern struct device_attribute dev_attr_devspeed;\n+extern struct device_attribute dev_attr_enumspeed;\n+extern struct device_attribute dev_attr_hptxfsiz;\n+extern struct device_attribute dev_attr_hprt0;\n+#ifdef CONFIG_USB_DWC_OTG_LPM\n+extern struct device_attribute dev_attr_lpm_response;\n+extern struct device_attribute devi_attr_sleep_status;\n+#endif\n+\n+void dwc_otg_attr_create(\n+#ifdef LM_INTERFACE\n+\t\t\t\tstruct lm_device *dev\n+#elif  defined(PCI_INTERFACE)\n+\t\t\t\tstruct pci_dev *dev\n+#elif  defined(PLATFORM_INTERFACE)\n+\tstruct platform_device *dev\n+#endif\n+    );\n+\n+void dwc_otg_attr_remove(\n+#ifdef LM_INTERFACE\n+\t\t\t\tstruct lm_device *dev\n+#elif  defined(PCI_INTERFACE)\n+\t\t\t\tstruct pci_dev *dev\n+#elif  defined(PLATFORM_INTERFACE)\n+\tstruct platform_device *dev\n+#endif\n+    );\n+#endif\n--- /dev/null\n+++ b/drivers/usb/host/dwc_otg/dwc_otg_cfi.c\n@@ -0,0 +1,1876 @@\n+/* ==========================================================================\n+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,\n+ * \"Software\") is an Unsupported proprietary work of Synopsys, Inc. unless\n+ * otherwise expressly agreed to in writing between Synopsys and you.\n+ *\n+ * The Software IS NOT an item of Licensed Software or Licensed Product under\n+ * any End User Software License Agreement or Agreement for Licensed Product\n+ * with Synopsys or any supplement thereto. You are permitted to use and\n+ * redistribute this Software in source and binary forms, with or without\n+ * modification, provided that redistributions of source code must retain this\n+ * notice. You may not view, use, disclose, copy or distribute this file or\n+ * any information contained herein except pursuant to this license grant from\n+ * Synopsys. If you do not agree with this notice, including the disclaimer\n+ * below, then you are not authorized to use the Software.\n+ *\n+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN \"AS IS\" BASIS\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,\n+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH\n+ * DAMAGE.\n+ * ========================================================================== */\n+\n+/** @file\n+ *\n+ * This file contains the most of the CFI(Core Feature Interface)\n+ * implementation for the OTG.\n+ */\n+\n+#ifdef DWC_UTE_CFI\n+\n+#include \"dwc_otg_pcd.h\"\n+#include \"dwc_otg_cfi.h\"\n+\n+/** This definition should actually migrate to the Portability Library */\n+#define DWC_CONSTANT_CPU_TO_LE16(x) (x)\n+\n+extern dwc_otg_pcd_ep_t *get_ep_by_addr(dwc_otg_pcd_t * pcd, u16 wIndex);\n+\n+static int cfi_core_features_buf(uint8_t * buf, uint16_t buflen);\n+static int cfi_get_feature_value(uint8_t * buf, uint16_t buflen,\n+\t\t\t\t struct dwc_otg_pcd *pcd,\n+\t\t\t\t struct cfi_usb_ctrlrequest *ctrl_req);\n+static int cfi_set_feature_value(struct dwc_otg_pcd *pcd);\n+static int cfi_ep_get_sg_val(uint8_t * buf, struct dwc_otg_pcd *pcd,\n+\t\t\t     struct cfi_usb_ctrlrequest *req);\n+static int cfi_ep_get_concat_val(uint8_t * buf, struct dwc_otg_pcd *pcd,\n+\t\t\t\t struct cfi_usb_ctrlrequest *req);\n+static int cfi_ep_get_align_val(uint8_t * buf, struct dwc_otg_pcd *pcd,\n+\t\t\t\tstruct cfi_usb_ctrlrequest *req);\n+static int cfi_preproc_reset(struct dwc_otg_pcd *pcd,\n+\t\t\t     struct cfi_usb_ctrlrequest *req);\n+static void cfi_free_ep_bs_dyn_data(cfi_ep_t * cfiep);\n+\n+static uint16_t get_dfifo_size(dwc_otg_core_if_t * core_if);\n+static int32_t get_rxfifo_size(dwc_otg_core_if_t * core_if, uint16_t wValue);\n+static int32_t get_txfifo_size(struct dwc_otg_pcd *pcd, uint16_t wValue);\n+\n+static uint8_t resize_fifos(dwc_otg_core_if_t * core_if);\n+\n+/** This is the header of the all features descriptor */\n+static cfi_all_features_header_t all_props_desc_header = {\n+\t.wVersion = DWC_CONSTANT_CPU_TO_LE16(0x100),\n+\t.wCoreID = DWC_CONSTANT_CPU_TO_LE16(CFI_CORE_ID_OTG),\n+\t.wNumFeatures = DWC_CONSTANT_CPU_TO_LE16(9),\n+};\n+\n+/** This is an array of statically allocated feature descriptors */\n+static cfi_feature_desc_header_t prop_descs[] = {\n+\n+\t/* FT_ID_DMA_MODE */\n+\t{\n+\t .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_DMA_MODE),\n+\t .bmAttributes = CFI_FEATURE_ATTR_RW,\n+\t .wDataLength = DWC_CONSTANT_CPU_TO_LE16(1),\n+\t },\n+\n+\t/* FT_ID_DMA_BUFFER_SETUP */\n+\t{\n+\t .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_DMA_BUFFER_SETUP),\n+\t .bmAttributes = CFI_FEATURE_ATTR_RW,\n+\t .wDataLength = DWC_CONSTANT_CPU_TO_LE16(6),\n+\t },\n+\n+\t/* FT_ID_DMA_BUFF_ALIGN */\n+\t{\n+\t .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_DMA_BUFF_ALIGN),\n+\t .bmAttributes = CFI_FEATURE_ATTR_RW,\n+\t .wDataLength = DWC_CONSTANT_CPU_TO_LE16(2),\n+\t },\n+\n+\t/* FT_ID_DMA_CONCAT_SETUP */\n+\t{\n+\t .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_DMA_CONCAT_SETUP),\n+\t .bmAttributes = CFI_FEATURE_ATTR_RW,\n+\t //.wDataLength  = DWC_CONSTANT_CPU_TO_LE16(6),\n+\t },\n+\n+\t/* FT_ID_DMA_CIRCULAR */\n+\t{\n+\t .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_DMA_CIRCULAR),\n+\t .bmAttributes = CFI_FEATURE_ATTR_RW,\n+\t .wDataLength = DWC_CONSTANT_CPU_TO_LE16(6),\n+\t },\n+\n+\t/* FT_ID_THRESHOLD_SETUP */\n+\t{\n+\t .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_THRESHOLD_SETUP),\n+\t .bmAttributes = CFI_FEATURE_ATTR_RW,\n+\t .wDataLength = DWC_CONSTANT_CPU_TO_LE16(6),\n+\t },\n+\n+\t/* FT_ID_DFIFO_DEPTH */\n+\t{\n+\t .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_DFIFO_DEPTH),\n+\t .bmAttributes = CFI_FEATURE_ATTR_RO,\n+\t .wDataLength = DWC_CONSTANT_CPU_TO_LE16(2),\n+\t },\n+\n+\t/* FT_ID_TX_FIFO_DEPTH */\n+\t{\n+\t .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_TX_FIFO_DEPTH),\n+\t .bmAttributes = CFI_FEATURE_ATTR_RW,\n+\t .wDataLength = DWC_CONSTANT_CPU_TO_LE16(2),\n+\t },\n+\n+\t/* FT_ID_RX_FIFO_DEPTH */\n+\t{\n+\t .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_RX_FIFO_DEPTH),\n+\t .bmAttributes = CFI_FEATURE_ATTR_RW,\n+\t .wDataLength = DWC_CONSTANT_CPU_TO_LE16(2),\n+\t }\n+};\n+\n+/** The table of feature names */\n+cfi_string_t prop_name_table[] = {\n+\t{FT_ID_DMA_MODE, \"dma_mode\"},\n+\t{FT_ID_DMA_BUFFER_SETUP, \"buffer_setup\"},\n+\t{FT_ID_DMA_BUFF_ALIGN, \"buffer_align\"},\n+\t{FT_ID_DMA_CONCAT_SETUP, \"concat_setup\"},\n+\t{FT_ID_DMA_CIRCULAR, \"buffer_circular\"},\n+\t{FT_ID_THRESHOLD_SETUP, \"threshold_setup\"},\n+\t{FT_ID_DFIFO_DEPTH, \"dfifo_depth\"},\n+\t{FT_ID_TX_FIFO_DEPTH, \"txfifo_depth\"},\n+\t{FT_ID_RX_FIFO_DEPTH, \"rxfifo_depth\"},\n+\t{}\n+};\n+\n+/************************************************************************/\n+\n+/**\n+ * Returns the name of the feature by its ID\n+ * or NULL if no featute ID matches.\n+ *\n+ */\n+const uint8_t *get_prop_name(uint16_t prop_id, int *len)\n+{\n+\tcfi_string_t *pstr;\n+\t*len = 0;\n+\n+\tfor (pstr = prop_name_table; pstr && pstr->s; pstr++) {\n+\t\tif (pstr->id == prop_id) {\n+\t\t\t*len = DWC_STRLEN(pstr->s);\n+\t\t\treturn pstr->s;\n+\t\t}\n+\t}\n+\treturn NULL;\n+}\n+\n+/**\n+ * This function handles all CFI specific control requests.\n+ *\n+ * Return a negative value to stall the DCE.\n+ */\n+int cfi_setup(struct dwc_otg_pcd *pcd, struct cfi_usb_ctrlrequest *ctrl)\n+{\n+\tint retval = 0;\n+\tdwc_otg_pcd_ep_t *ep = NULL;\n+\tcfiobject_t *cfi = pcd->cfi;\n+\tstruct dwc_otg_core_if *coreif = GET_CORE_IF(pcd);\n+\tuint16_t wLen = DWC_LE16_TO_CPU(&ctrl->wLength);\n+\tuint16_t wValue = DWC_LE16_TO_CPU(&ctrl->wValue);\n+\tuint16_t wIndex = DWC_LE16_TO_CPU(&ctrl->wIndex);\n+\tuint32_t regaddr = 0;\n+\tuint32_t regval = 0;\n+\n+\t/* Save this Control Request in the CFI object.\n+\t * The data field will be assigned in the data stage completion CB function.\n+\t */\n+\tcfi->ctrl_req = *ctrl;\n+\tcfi->ctrl_req.data = NULL;\n+\n+\tcfi->need_gadget_att = 0;\n+\tcfi->need_status_in_complete = 0;\n+\n+\tswitch (ctrl->bRequest) {\n+\tcase VEN_CORE_GET_FEATURES:\n+\t\tretval = cfi_core_features_buf(cfi->buf_in.buf, CFI_IN_BUF_LEN);\n+\t\tif (retval >= 0) {\n+\t\t\t//dump_msg(cfi->buf_in.buf, retval);\n+\t\t\tep = &pcd->ep0;\n+\n+\t\t\tretval = min((uint16_t) retval, wLen);\n+\t\t\t/* Transfer this buffer to the host through the EP0-IN EP */\n+\t\t\tep->dwc_ep.dma_addr = cfi->buf_in.addr;\n+\t\t\tep->dwc_ep.start_xfer_buff = cfi->buf_in.buf;\n+\t\t\tep->dwc_ep.xfer_buff = cfi->buf_in.buf;\n+\t\t\tep->dwc_ep.xfer_len = retval;\n+\t\t\tep->dwc_ep.xfer_count = 0;\n+\t\t\tep->dwc_ep.sent_zlp = 0;\n+\t\t\tep->dwc_ep.total_len = ep->dwc_ep.xfer_len;\n+\n+\t\t\tpcd->ep0_pending = 1;\n+\t\t\tdwc_otg_ep0_start_transfer(coreif, &ep->dwc_ep);\n+\t\t}\n+\t\tretval = 0;\n+\t\tbreak;\n+\n+\tcase VEN_CORE_GET_FEATURE:\n+\t\tCFI_INFO(\"VEN_CORE_GET_FEATURE\\n\");\n+\t\tretval = cfi_get_feature_value(cfi->buf_in.buf, CFI_IN_BUF_LEN,\n+\t\t\t\t\t       pcd, ctrl);\n+\t\tif (retval >= 0) {\n+\t\t\tep = &pcd->ep0;\n+\n+\t\t\tretval = min((uint16_t) retval, wLen);\n+\t\t\t/* Transfer this buffer to the host through the EP0-IN EP */\n+\t\t\tep->dwc_ep.dma_addr = cfi->buf_in.addr;\n+\t\t\tep->dwc_ep.start_xfer_buff = cfi->buf_in.buf;\n+\t\t\tep->dwc_ep.xfer_buff = cfi->buf_in.buf;\n+\t\t\tep->dwc_ep.xfer_len = retval;\n+\t\t\tep->dwc_ep.xfer_count = 0;\n+\t\t\tep->dwc_ep.sent_zlp = 0;\n+\t\t\tep->dwc_ep.total_len = ep->dwc_ep.xfer_len;\n+\n+\t\t\tpcd->ep0_pending = 1;\n+\t\t\tdwc_otg_ep0_start_transfer(coreif, &ep->dwc_ep);\n+\t\t}\n+\t\tCFI_INFO(\"VEN_CORE_GET_FEATURE=%d\\n\", retval);\n+\t\tdump_msg(cfi->buf_in.buf, retval);\n+\t\tbreak;\n+\n+\tcase VEN_CORE_SET_FEATURE:\n+\t\tCFI_INFO(\"VEN_CORE_SET_FEATURE\\n\");\n+\t\t/* Set up an XFER to get the data stage of the control request,\n+\t\t * which is the new value of the feature to be modified.\n+\t\t */\n+\t\tep = &pcd->ep0;\n+\t\tep->dwc_ep.is_in = 0;\n+\t\tep->dwc_ep.dma_addr = cfi->buf_out.addr;\n+\t\tep->dwc_ep.start_xfer_buff = cfi->buf_out.buf;\n+\t\tep->dwc_ep.xfer_buff = cfi->buf_out.buf;\n+\t\tep->dwc_ep.xfer_len = wLen;\n+\t\tep->dwc_ep.xfer_count = 0;\n+\t\tep->dwc_ep.sent_zlp = 0;\n+\t\tep->dwc_ep.total_len = ep->dwc_ep.xfer_len;\n+\n+\t\tpcd->ep0_pending = 1;\n+\t\t/* Read the control write's data stage */\n+\t\tdwc_otg_ep0_start_transfer(coreif, &ep->dwc_ep);\n+\t\tretval = 0;\n+\t\tbreak;\n+\n+\tcase VEN_CORE_RESET_FEATURES:\n+\t\tCFI_INFO(\"VEN_CORE_RESET_FEATURES\\n\");\n+\t\tcfi->need_gadget_att = 1;\n+\t\tcfi->need_status_in_complete = 1;\n+\t\tretval = cfi_preproc_reset(pcd, ctrl);\n+\t\tCFI_INFO(\"VEN_CORE_RESET_FEATURES = (%d)\\n\", retval);\n+\t\tbreak;\n+\n+\tcase VEN_CORE_ACTIVATE_FEATURES:\n+\t\tCFI_INFO(\"VEN_CORE_ACTIVATE_FEATURES\\n\");\n+\t\tbreak;\n+\n+\tcase VEN_CORE_READ_REGISTER:\n+\t\tCFI_INFO(\"VEN_CORE_READ_REGISTER\\n\");\n+\t\t/* wValue optionally contains the HI WORD of the register offset and\n+\t\t * wIndex contains the LOW WORD of the register offset\n+\t\t */\n+\t\tif (wValue == 0) {\n+\t\t\t/* @TODO - MAS - fix the access to the base field */\n+\t\t\tregaddr = 0;\n+\t\t\t//regaddr = (uint32_t) pcd->otg_dev->os_dep.base;\n+\t\t\t//GET_CORE_IF(pcd)->co\n+\t\t\tregaddr |= wIndex;\n+\t\t} else {\n+\t\t\tregaddr = (wValue << 16) | wIndex;\n+\t\t}\n+\n+\t\t/* Read a 32-bit value of the memory at the regaddr */\n+\t\tregval = DWC_READ_REG32((uint32_t *) regaddr);\n+\n+\t\tep = &pcd->ep0;\n+\t\tdwc_memcpy(cfi->buf_in.buf, &regval, sizeof(uint32_t));\n+\t\tep->dwc_ep.is_in = 1;\n+\t\tep->dwc_ep.dma_addr = cfi->buf_in.addr;\n+\t\tep->dwc_ep.start_xfer_buff = cfi->buf_in.buf;\n+\t\tep->dwc_ep.xfer_buff = cfi->buf_in.buf;\n+\t\tep->dwc_ep.xfer_len = wLen;\n+\t\tep->dwc_ep.xfer_count = 0;\n+\t\tep->dwc_ep.sent_zlp = 0;\n+\t\tep->dwc_ep.total_len = ep->dwc_ep.xfer_len;\n+\n+\t\tpcd->ep0_pending = 1;\n+\t\tdwc_otg_ep0_start_transfer(coreif, &ep->dwc_ep);\n+\t\tcfi->need_gadget_att = 0;\n+\t\tretval = 0;\n+\t\tbreak;\n+\n+\tcase VEN_CORE_WRITE_REGISTER:\n+\t\tCFI_INFO(\"VEN_CORE_WRITE_REGISTER\\n\");\n+\t\t/* Set up an XFER to get the data stage of the control request,\n+\t\t * which is the new value of the register to be modified.\n+\t\t */\n+\t\tep = &pcd->ep0;\n+\t\tep->dwc_ep.is_in = 0;\n+\t\tep->dwc_ep.dma_addr = cfi->buf_out.addr;\n+\t\tep->dwc_ep.start_xfer_buff = cfi->buf_out.buf;\n+\t\tep->dwc_ep.xfer_buff = cfi->buf_out.buf;\n+\t\tep->dwc_ep.xfer_len = wLen;\n+\t\tep->dwc_ep.xfer_count = 0;\n+\t\tep->dwc_ep.sent_zlp = 0;\n+\t\tep->dwc_ep.total_len = ep->dwc_ep.xfer_len;\n+\n+\t\tpcd->ep0_pending = 1;\n+\t\t/* Read the control write's data stage */\n+\t\tdwc_otg_ep0_start_transfer(coreif, &ep->dwc_ep);\n+\t\tretval = 0;\n+\t\tbreak;\n+\n+\tdefault:\n+\t\tretval = -DWC_E_NOT_SUPPORTED;\n+\t\tbreak;\n+\t}\n+\n+\treturn retval;\n+}\n+\n+/**\n+ * This function prepares the core features descriptors and copies its\n+ * raw representation into the buffer <buf>.\n+ *\n+ * The buffer structure is as follows:\n+ *\tall_features_header (8 bytes)\n+ *\tfeatures_#1 (8 bytes + feature name string length)\n+ *\tfeatures_#2 (8 bytes + feature name string length)\n+ *\t.....\n+ *\tfeatures_#n - where n=the total count of feature descriptors\n+ */\n+static int cfi_core_features_buf(uint8_t * buf, uint16_t buflen)\n+{\n+\tcfi_feature_desc_header_t *prop_hdr = prop_descs;\n+\tcfi_feature_desc_header_t *prop;\n+\tcfi_all_features_header_t *all_props_hdr = &all_props_desc_header;\n+\tcfi_all_features_header_t *tmp;\n+\tuint8_t *tmpbuf = buf;\n+\tconst uint8_t *pname = NULL;\n+\tint i, j, namelen = 0, totlen;\n+\n+\t/* Prepare and copy the core features into the buffer */\n+\tCFI_INFO(\"%s:\\n\", __func__);\n+\n+\ttmp = (cfi_all_features_header_t *) tmpbuf;\n+\t*tmp = *all_props_hdr;\n+\ttmpbuf += CFI_ALL_FEATURES_HDR_LEN;\n+\n+\tj = sizeof(prop_descs) / sizeof(cfi_all_features_header_t);\n+\tfor (i = 0; i < j; i++, prop_hdr++) {\n+\t\tpname = get_prop_name(prop_hdr->wFeatureID, &namelen);\n+\t\tprop = (cfi_feature_desc_header_t *) tmpbuf;\n+\t\t*prop = *prop_hdr;\n+\n+\t\tprop->bNameLen = namelen;\n+\t\tprop->wLength =\n+\t\t    DWC_CONSTANT_CPU_TO_LE16(CFI_FEATURE_DESC_HDR_LEN +\n+\t\t\t\t\t     namelen);\n+\n+\t\ttmpbuf += CFI_FEATURE_DESC_HDR_LEN;\n+\t\tdwc_memcpy(tmpbuf, pname, namelen);\n+\t\ttmpbuf += namelen;\n+\t}\n+\n+\ttotlen = tmpbuf - buf;\n+\n+\tif (totlen > 0) {\n+\t\ttmp = (cfi_all_features_header_t *) buf;\n+\t\ttmp->wTotalLen = DWC_CONSTANT_CPU_TO_LE16(totlen);\n+\t}\n+\n+\treturn totlen;\n+}\n+\n+/**\n+ * This function releases all the dynamic memory in the CFI object.\n+ */\n+static void cfi_release(cfiobject_t * cfiobj)\n+{\n+\tcfi_ep_t *cfiep;\n+\tdwc_list_link_t *tmp;\n+\n+\tCFI_INFO(\"%s\\n\", __func__);\n+\n+\tif (cfiobj->buf_in.buf) {\n+\t\tDWC_DMA_FREE(CFI_IN_BUF_LEN, cfiobj->buf_in.buf,\n+\t\t\t     cfiobj->buf_in.addr);\n+\t\tcfiobj->buf_in.buf = NULL;\n+\t}\n+\n+\tif (cfiobj->buf_out.buf) {\n+\t\tDWC_DMA_FREE(CFI_OUT_BUF_LEN, cfiobj->buf_out.buf,\n+\t\t\t     cfiobj->buf_out.addr);\n+\t\tcfiobj->buf_out.buf = NULL;\n+\t}\n+\n+\t/* Free the Buffer Setup values for each EP */\n+\t//list_for_each_entry(cfiep, &cfiobj->active_eps, lh) {\n+\tDWC_LIST_FOREACH(tmp, &cfiobj->active_eps) {\n+\t\tcfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh);\n+\t\tcfi_free_ep_bs_dyn_data(cfiep);\n+\t}\n+}\n+\n+/**\n+ * This function frees the dynamically allocated EP buffer setup data.\n+ */\n+static void cfi_free_ep_bs_dyn_data(cfi_ep_t * cfiep)\n+{\n+\tif (cfiep->bm_sg) {\n+\t\tDWC_FREE(cfiep->bm_sg);\n+\t\tcfiep->bm_sg = NULL;\n+\t}\n+\n+\tif (cfiep->bm_align) {\n+\t\tDWC_FREE(cfiep->bm_align);\n+\t\tcfiep->bm_align = NULL;\n+\t}\n+\n+\tif (cfiep->bm_concat) {\n+\t\tif (NULL != cfiep->bm_concat->wTxBytes) {\n+\t\t\tDWC_FREE(cfiep->bm_concat->wTxBytes);\n+\t\t\tcfiep->bm_concat->wTxBytes = NULL;\n+\t\t}\n+\t\tDWC_FREE(cfiep->bm_concat);\n+\t\tcfiep->bm_concat = NULL;\n+\t}\n+}\n+\n+/**\n+ * This function initializes the default values of the features\n+ * for a specific endpoint and should be called only once when\n+ * the EP is enabled first time.\n+ */\n+static int cfi_ep_init_defaults(struct dwc_otg_pcd *pcd, cfi_ep_t * cfiep)\n+{\n+\tint retval = 0;\n+\n+\tcfiep->bm_sg = DWC_ALLOC(sizeof(ddma_sg_buffer_setup_t));\n+\tif (NULL == cfiep->bm_sg) {\n+\t\tCFI_INFO(\"Failed to allocate memory for SG feature value\\n\");\n+\t\treturn -DWC_E_NO_MEMORY;\n+\t}\n+\tdwc_memset(cfiep->bm_sg, 0, sizeof(ddma_sg_buffer_setup_t));\n+\n+\t/* For the Concatenation feature's default value we do not allocate\n+\t * memory for the wTxBytes field - it will be done in the set_feature_value\n+\t * request handler.\n+\t */\n+\tcfiep->bm_concat = DWC_ALLOC(sizeof(ddma_concat_buffer_setup_t));\n+\tif (NULL == cfiep->bm_concat) {\n+\t\tCFI_INFO\n+\t\t    (\"Failed to allocate memory for CONCATENATION feature value\\n\");\n+\t\tDWC_FREE(cfiep->bm_sg);\n+\t\treturn -DWC_E_NO_MEMORY;\n+\t}\n+\tdwc_memset(cfiep->bm_concat, 0, sizeof(ddma_concat_buffer_setup_t));\n+\n+\tcfiep->bm_align = DWC_ALLOC(sizeof(ddma_align_buffer_setup_t));\n+\tif (NULL == cfiep->bm_align) {\n+\t\tCFI_INFO\n+\t\t    (\"Failed to allocate memory for Alignment feature value\\n\");\n+\t\tDWC_FREE(cfiep->bm_sg);\n+\t\tDWC_FREE(cfiep->bm_concat);\n+\t\treturn -DWC_E_NO_MEMORY;\n+\t}\n+\tdwc_memset(cfiep->bm_align, 0, sizeof(ddma_align_buffer_setup_t));\n+\n+\treturn retval;\n+}\n+\n+/**\n+ * The callback function that notifies the CFI on the activation of\n+ * an endpoint in the PCD. The following steps are done in this function:\n+ *\n+ *\tCreate a dynamically allocated cfi_ep_t object (a CFI wrapper to the PCD's\n+ *\t\tactive endpoint)\n+ *\tCreate MAX_DMA_DESCS_PER_EP count DMA Descriptors for the EP\n+ *\tSet the Buffer Mode to standard\n+ *\tInitialize the default values for all EP modes (SG, Circular, Concat, Align)\n+ *\tAdd the cfi_ep_t object to the list of active endpoints in the CFI object\n+ */\n+static int cfi_ep_enable(struct cfiobject *cfi, struct dwc_otg_pcd *pcd,\n+\t\t\t struct dwc_otg_pcd_ep *ep)\n+{\n+\tcfi_ep_t *cfiep;\n+\tint retval = -DWC_E_NOT_SUPPORTED;\n+\n+\tCFI_INFO(\"%s: epname=%s; epnum=0x%02x\\n\", __func__,\n+\t\t \"EP_\" /*ep->ep.name */ , ep->desc->bEndpointAddress);\n+\t/* MAS - Check whether this endpoint already is in the list */\n+\tcfiep = get_cfi_ep_by_pcd_ep(cfi, ep);\n+\n+\tif (NULL == cfiep) {\n+\t\t/* Allocate a cfi_ep_t object */\n+\t\tcfiep = DWC_ALLOC(sizeof(cfi_ep_t));\n+\t\tif (NULL == cfiep) {\n+\t\t\tCFI_INFO\n+\t\t\t    (\"Unable to allocate memory for <cfiep> in function %s\\n\",\n+\t\t\t     __func__);\n+\t\t\treturn -DWC_E_NO_MEMORY;\n+\t\t}\n+\t\tdwc_memset(cfiep, 0, sizeof(cfi_ep_t));\n+\n+\t\t/* Save the dwc_otg_pcd_ep pointer in the cfiep object */\n+\t\tcfiep->ep = ep;\n+\n+\t\t/* Allocate the DMA Descriptors chain of MAX_DMA_DESCS_PER_EP count */\n+\t\tep->dwc_ep.descs =\n+\t\t    DWC_DMA_ALLOC(MAX_DMA_DESCS_PER_EP *\n+\t\t\t\t  sizeof(dwc_otg_dma_desc_t),\n+\t\t\t\t  &ep->dwc_ep.descs_dma_addr);\n+\n+\t\tif (NULL == ep->dwc_ep.descs) {\n+\t\t\tDWC_FREE(cfiep);\n+\t\t\treturn -DWC_E_NO_MEMORY;\n+\t\t}\n+\n+\t\tDWC_LIST_INIT(&cfiep->lh);\n+\n+\t\t/* Set the buffer mode to BM_STANDARD. It will be modified\n+\t\t * when building descriptors for a specific buffer mode */\n+\t\tep->dwc_ep.buff_mode = BM_STANDARD;\n+\n+\t\t/* Create and initialize the default values for this EP's Buffer modes */\n+\t\tif ((retval = cfi_ep_init_defaults(pcd, cfiep)) < 0)\n+\t\t\treturn retval;\n+\n+\t\t/* Add the cfi_ep_t object to the CFI object's list of active endpoints */\n+\t\tDWC_LIST_INSERT_TAIL(&cfi->active_eps, &cfiep->lh);\n+\t\tretval = 0;\n+\t} else {\t\t/* The sought EP already is in the list */\n+\t\tCFI_INFO(\"%s: The sought EP already is in the list\\n\",\n+\t\t\t __func__);\n+\t}\n+\n+\treturn retval;\n+}\n+\n+/**\n+ * This function is called when the data stage of a 3-stage Control Write request\n+ * is complete.\n+ *\n+ */\n+static int cfi_ctrl_write_complete(struct cfiobject *cfi,\n+\t\t\t\t   struct dwc_otg_pcd *pcd)\n+{\n+\tuint32_t addr, reg_value;\n+\tuint16_t wIndex, wValue;\n+\tuint8_t bRequest;\n+\tuint8_t *buf = cfi->buf_out.buf;\n+\t//struct usb_ctrlrequest *ctrl_req = &cfi->ctrl_req_saved;\n+\tstruct cfi_usb_ctrlrequest *ctrl_req = &cfi->ctrl_req;\n+\tint retval = -DWC_E_NOT_SUPPORTED;\n+\n+\tCFI_INFO(\"%s\\n\", __func__);\n+\n+\tbRequest = ctrl_req->bRequest;\n+\twIndex = DWC_CONSTANT_CPU_TO_LE16(ctrl_req->wIndex);\n+\twValue = DWC_CONSTANT_CPU_TO_LE16(ctrl_req->wValue);\n+\n+\t/*\n+\t * Save the pointer to the data stage in the ctrl_req's <data> field.\n+\t * The request should be already saved in the command stage by now.\n+\t */\n+\tctrl_req->data = cfi->buf_out.buf;\n+\tcfi->need_status_in_complete = 0;\n+\tcfi->need_gadget_att = 0;\n+\n+\tswitch (bRequest) {\n+\tcase VEN_CORE_WRITE_REGISTER:\n+\t\t/* The buffer contains raw data of the new value for the register */\n+\t\treg_value = *((uint32_t *) buf);\n+\t\tif (wValue == 0) {\n+\t\t\taddr = 0;\n+\t\t\t//addr = (uint32_t) pcd->otg_dev->os_dep.base;\n+\t\t\taddr += wIndex;\n+\t\t} else {\n+\t\t\taddr = (wValue << 16) | wIndex;\n+\t\t}\n+\n+\t\t//writel(reg_value, addr);\n+\n+\t\tretval = 0;\n+\t\tcfi->need_status_in_complete = 1;\n+\t\tbreak;\n+\n+\tcase VEN_CORE_SET_FEATURE:\n+\t\t/* The buffer contains raw data of the new value of the feature */\n+\t\tretval = cfi_set_feature_value(pcd);\n+\t\tif (retval < 0)\n+\t\t\treturn retval;\n+\n+\t\tcfi->need_status_in_complete = 1;\n+\t\tbreak;\n+\n+\tdefault:\n+\t\tbreak;\n+\t}\n+\n+\treturn retval;\n+}\n+\n+/**\n+ * This function builds the DMA descriptors for the SG buffer mode.\n+ */\n+static void cfi_build_sg_descs(struct cfiobject *cfi, cfi_ep_t * cfiep,\n+\t\t\t       dwc_otg_pcd_request_t * req)\n+{\n+\tstruct dwc_otg_pcd_ep *ep = cfiep->ep;\n+\tddma_sg_buffer_setup_t *sgval = cfiep->bm_sg;\n+\tstruct dwc_otg_dma_desc *desc = cfiep->ep->dwc_ep.descs;\n+\tstruct dwc_otg_dma_desc *desc_last = cfiep->ep->dwc_ep.descs;\n+\tdma_addr_t buff_addr = req->dma;\n+\tint i;\n+\tuint32_t txsize, off;\n+\n+\ttxsize = sgval->wSize;\n+\toff = sgval->bOffset;\n+\n+//      CFI_INFO(\"%s: %s TXSIZE=0x%08x; OFFSET=0x%08x\\n\",\n+//              __func__, cfiep->ep->ep.name, txsize, off);\n+\n+\tfor (i = 0; i < sgval->bCount; i++) {\n+\t\tdesc->status.b.bs = BS_HOST_BUSY;\n+\t\tdesc->buf = buff_addr;\n+\t\tdesc->status.b.l = 0;\n+\t\tdesc->status.b.ioc = 0;\n+\t\tdesc->status.b.sp = 0;\n+\t\tdesc->status.b.bytes = txsize;\n+\t\tdesc->status.b.bs = BS_HOST_READY;\n+\n+\t\t/* Set the next address of the buffer */\n+\t\tbuff_addr += txsize + off;\n+\t\tdesc_last = desc;\n+\t\tdesc++;\n+\t}\n+\n+\t/* Set the last, ioc and sp bits on the Last DMA Descriptor */\n+\tdesc_last->status.b.l = 1;\n+\tdesc_last->status.b.ioc = 1;\n+\tdesc_last->status.b.sp = ep->dwc_ep.sent_zlp;\n+\t/* Save the last DMA descriptor pointer */\n+\tcfiep->dma_desc_last = desc_last;\n+\tcfiep->desc_count = sgval->bCount;\n+}\n+\n+/**\n+ * This function builds the DMA descriptors for the Concatenation buffer mode.\n+ */\n+static void cfi_build_concat_descs(struct cfiobject *cfi, cfi_ep_t * cfiep,\n+\t\t\t\t   dwc_otg_pcd_request_t * req)\n+{\n+\tstruct dwc_otg_pcd_ep *ep = cfiep->ep;\n+\tddma_concat_buffer_setup_t *concatval = cfiep->bm_concat;\n+\tstruct dwc_otg_dma_desc *desc = cfiep->ep->dwc_ep.descs;\n+\tstruct dwc_otg_dma_desc *desc_last = cfiep->ep->dwc_ep.descs;\n+\tdma_addr_t buff_addr = req->dma;\n+\tint i;\n+\tuint16_t *txsize;\n+\n+\ttxsize = concatval->wTxBytes;\n+\n+\tfor (i = 0; i < concatval->hdr.bDescCount; i++) {\n+\t\tdesc->buf = buff_addr;\n+\t\tdesc->status.b.bs = BS_HOST_BUSY;\n+\t\tdesc->status.b.l = 0;\n+\t\tdesc->status.b.ioc = 0;\n+\t\tdesc->status.b.sp = 0;\n+\t\tdesc->status.b.bytes = *txsize;\n+\t\tdesc->status.b.bs = BS_HOST_READY;\n+\n+\t\ttxsize++;\n+\t\t/* Set the next address of the buffer */\n+\t\tbuff_addr += UGETW(ep->desc->wMaxPacketSize);\n+\t\tdesc_last = desc;\n+\t\tdesc++;\n+\t}\n+\n+\t/* Set the last, ioc and sp bits on the Last DMA Descriptor */\n+\tdesc_last->status.b.l = 1;\n+\tdesc_last->status.b.ioc = 1;\n+\tdesc_last->status.b.sp = ep->dwc_ep.sent_zlp;\n+\tcfiep->dma_desc_last = desc_last;\n+\tcfiep->desc_count = concatval->hdr.bDescCount;\n+}\n+\n+/**\n+ * This function builds the DMA descriptors for the Circular buffer mode\n+ */\n+static void cfi_build_circ_descs(struct cfiobject *cfi, cfi_ep_t * cfiep,\n+\t\t\t\t dwc_otg_pcd_request_t * req)\n+{\n+\t/* @todo: MAS - add implementation when this feature needs to be tested */\n+}\n+\n+/**\n+ * This function builds the DMA descriptors for the Alignment buffer mode\n+ */\n+static void cfi_build_align_descs(struct cfiobject *cfi, cfi_ep_t * cfiep,\n+\t\t\t\t  dwc_otg_pcd_request_t * req)\n+{\n+\tstruct dwc_otg_pcd_ep *ep = cfiep->ep;\n+\tddma_align_buffer_setup_t *alignval = cfiep->bm_align;\n+\tstruct dwc_otg_dma_desc *desc = cfiep->ep->dwc_ep.descs;\n+\tdma_addr_t buff_addr = req->dma;\n+\n+\tdesc->status.b.bs = BS_HOST_BUSY;\n+\tdesc->status.b.l = 1;\n+\tdesc->status.b.ioc = 1;\n+\tdesc->status.b.sp = ep->dwc_ep.sent_zlp;\n+\tdesc->status.b.bytes = req->length;\n+\t/* Adjust the buffer alignment */\n+\tdesc->buf = (buff_addr + alignval->bAlign);\n+\tdesc->status.b.bs = BS_HOST_READY;\n+\tcfiep->dma_desc_last = desc;\n+\tcfiep->desc_count = 1;\n+}\n+\n+/**\n+ * This function builds the DMA descriptors chain for different modes of the\n+ * buffer setup of an endpoint.\n+ */\n+static void cfi_build_descriptors(struct cfiobject *cfi,\n+\t\t\t\t  struct dwc_otg_pcd *pcd,\n+\t\t\t\t  struct dwc_otg_pcd_ep *ep,\n+\t\t\t\t  dwc_otg_pcd_request_t * req)\n+{\n+\tcfi_ep_t *cfiep;\n+\n+\t/* Get the cfiep by the dwc_otg_pcd_ep */\n+\tcfiep = get_cfi_ep_by_pcd_ep(cfi, ep);\n+\tif (NULL == cfiep) {\n+\t\tCFI_INFO(\"%s: Unable to find a matching active endpoint\\n\",\n+\t\t\t __func__);\n+\t\treturn;\n+\t}\n+\n+\tcfiep->xfer_len = req->length;\n+\n+\t/* Iterate through all the DMA descriptors */\n+\tswitch (cfiep->ep->dwc_ep.buff_mode) {\n+\tcase BM_SG:\n+\t\tcfi_build_sg_descs(cfi, cfiep, req);\n+\t\tbreak;\n+\n+\tcase BM_CONCAT:\n+\t\tcfi_build_concat_descs(cfi, cfiep, req);\n+\t\tbreak;\n+\n+\tcase BM_CIRCULAR:\n+\t\tcfi_build_circ_descs(cfi, cfiep, req);\n+\t\tbreak;\n+\n+\tcase BM_ALIGN:\n+\t\tcfi_build_align_descs(cfi, cfiep, req);\n+\t\tbreak;\n+\n+\tdefault:\n+\t\tbreak;\n+\t}\n+}\n+\n+/**\n+ * Allocate DMA buffer for different Buffer modes.\n+ */\n+static void *cfi_ep_alloc_buf(struct cfiobject *cfi, struct dwc_otg_pcd *pcd,\n+\t\t\t      struct dwc_otg_pcd_ep *ep, dma_addr_t * dma,\n+\t\t\t      unsigned size, gfp_t flags)\n+{\n+\treturn DWC_DMA_ALLOC(size, dma);\n+}\n+\n+/**\n+ * This function initializes the CFI object.\n+ */\n+int init_cfi(cfiobject_t * cfiobj)\n+{\n+\tCFI_INFO(\"%s\\n\", __func__);\n+\n+\t/* Allocate a buffer for IN XFERs */\n+\tcfiobj->buf_in.buf =\n+\t    DWC_DMA_ALLOC(CFI_IN_BUF_LEN, &cfiobj->buf_in.addr);\n+\tif (NULL == cfiobj->buf_in.buf) {\n+\t\tCFI_INFO(\"Unable to allocate buffer for INs\\n\");\n+\t\treturn -DWC_E_NO_MEMORY;\n+\t}\n+\n+\t/* Allocate a buffer for OUT XFERs */\n+\tcfiobj->buf_out.buf =\n+\t    DWC_DMA_ALLOC(CFI_OUT_BUF_LEN, &cfiobj->buf_out.addr);\n+\tif (NULL == cfiobj->buf_out.buf) {\n+\t\tCFI_INFO(\"Unable to allocate buffer for OUT\\n\");\n+\t\treturn -DWC_E_NO_MEMORY;\n+\t}\n+\n+\t/* Initialize the callback function pointers */\n+\tcfiobj->ops.release = cfi_release;\n+\tcfiobj->ops.ep_enable = cfi_ep_enable;\n+\tcfiobj->ops.ctrl_write_complete = cfi_ctrl_write_complete;\n+\tcfiobj->ops.build_descriptors = cfi_build_descriptors;\n+\tcfiobj->ops.ep_alloc_buf = cfi_ep_alloc_buf;\n+\n+\t/* Initialize the list of active endpoints in the CFI object */\n+\tDWC_LIST_INIT(&cfiobj->active_eps);\n+\n+\treturn 0;\n+}\n+\n+/**\n+ * This function reads the required feature's current value into the buffer\n+ *\n+ * @retval: Returns negative as error, or the data length of the feature\n+ */\n+static int cfi_get_feature_value(uint8_t * buf, uint16_t buflen,\n+\t\t\t\t struct dwc_otg_pcd *pcd,\n+\t\t\t\t struct cfi_usb_ctrlrequest *ctrl_req)\n+{\n+\tint retval = -DWC_E_NOT_SUPPORTED;\n+\tstruct dwc_otg_core_if *coreif = GET_CORE_IF(pcd);\n+\tuint16_t dfifo, rxfifo, txfifo;\n+\n+\tswitch (ctrl_req->wIndex) {\n+\t\t/* Whether the DDMA is enabled or not */\n+\tcase FT_ID_DMA_MODE:\n+\t\t*buf = (coreif->dma_enable && coreif->dma_desc_enable) ? 1 : 0;\n+\t\tretval = 1;\n+\t\tbreak;\n+\n+\tcase FT_ID_DMA_BUFFER_SETUP:\n+\t\tretval = cfi_ep_get_sg_val(buf, pcd, ctrl_req);\n+\t\tbreak;\n+\n+\tcase FT_ID_DMA_BUFF_ALIGN:\n+\t\tretval = cfi_ep_get_align_val(buf, pcd, ctrl_req);\n+\t\tbreak;\n+\n+\tcase FT_ID_DMA_CONCAT_SETUP:\n+\t\tretval = cfi_ep_get_concat_val(buf, pcd, ctrl_req);\n+\t\tbreak;\n+\n+\tcase FT_ID_DMA_CIRCULAR:\n+\t\tCFI_INFO(\"GetFeature value (FT_ID_DMA_CIRCULAR)\\n\");\n+\t\tbreak;\n+\n+\tcase FT_ID_THRESHOLD_SETUP:\n+\t\tCFI_INFO(\"GetFeature value (FT_ID_THRESHOLD_SETUP)\\n\");\n+\t\tbreak;\n+\n+\tcase FT_ID_DFIFO_DEPTH:\n+\t\tdfifo = get_dfifo_size(coreif);\n+\t\t*((uint16_t *) buf) = dfifo;\n+\t\tretval = sizeof(uint16_t);\n+\t\tbreak;\n+\n+\tcase FT_ID_TX_FIFO_DEPTH:\n+\t\tretval = get_txfifo_size(pcd, ctrl_req->wValue);\n+\t\tif (retval >= 0) {\n+\t\t\ttxfifo = retval;\n+\t\t\t*((uint16_t *) buf) = txfifo;\n+\t\t\tretval = sizeof(uint16_t);\n+\t\t}\n+\t\tbreak;\n+\n+\tcase FT_ID_RX_FIFO_DEPTH:\n+\t\tretval = get_rxfifo_size(coreif, ctrl_req->wValue);\n+\t\tif (retval >= 0) {\n+\t\t\trxfifo = retval;\n+\t\t\t*((uint16_t *) buf) = rxfifo;\n+\t\t\tretval = sizeof(uint16_t);\n+\t\t}\n+\t\tbreak;\n+\t}\n+\n+\treturn retval;\n+}\n+\n+/**\n+ * This function resets the SG for the specified EP to its default value\n+ */\n+static int cfi_reset_sg_val(cfi_ep_t * cfiep)\n+{\n+\tdwc_memset(cfiep->bm_sg, 0, sizeof(ddma_sg_buffer_setup_t));\n+\treturn 0;\n+}\n+\n+/**\n+ * This function resets the Alignment for the specified EP to its default value\n+ */\n+static int cfi_reset_align_val(cfi_ep_t * cfiep)\n+{\n+\tdwc_memset(cfiep->bm_sg, 0, sizeof(ddma_sg_buffer_setup_t));\n+\treturn 0;\n+}\n+\n+/**\n+ * This function resets the Concatenation for the specified EP to its default value\n+ * This function will also set the value of the wTxBytes field to NULL after\n+ * freeing the memory previously allocated for this field.\n+ */\n+static int cfi_reset_concat_val(cfi_ep_t * cfiep)\n+{\n+\t/* First we need to free the wTxBytes field */\n+\tif (cfiep->bm_concat->wTxBytes) {\n+\t\tDWC_FREE(cfiep->bm_concat->wTxBytes);\n+\t\tcfiep->bm_concat->wTxBytes = NULL;\n+\t}\n+\n+\tdwc_memset(cfiep->bm_concat, 0, sizeof(ddma_concat_buffer_setup_t));\n+\treturn 0;\n+}\n+\n+/**\n+ * This function resets all the buffer setups of the specified endpoint\n+ */\n+static int cfi_ep_reset_all_setup_vals(cfi_ep_t * cfiep)\n+{\n+\tcfi_reset_sg_val(cfiep);\n+\tcfi_reset_align_val(cfiep);\n+\tcfi_reset_concat_val(cfiep);\n+\treturn 0;\n+}\n+\n+static int cfi_handle_reset_fifo_val(struct dwc_otg_pcd *pcd, uint8_t ep_addr,\n+\t\t\t\t     uint8_t rx_rst, uint8_t tx_rst)\n+{\n+\tint retval = -DWC_E_INVALID;\n+\tuint16_t tx_siz[15];\n+\tuint16_t rx_siz = 0;\n+\tdwc_otg_pcd_ep_t *ep = NULL;\n+\tdwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);\n+\tdwc_otg_core_params_t *params = GET_CORE_IF(pcd)->core_params;\n+\n+\tif (rx_rst) {\n+\t\trx_siz = params->dev_rx_fifo_size;\n+\t\tparams->dev_rx_fifo_size = GET_CORE_IF(pcd)->init_rxfsiz;\n+\t}\n+\n+\tif (tx_rst) {\n+\t\tif (ep_addr == 0) {\n+\t\t\tint i;\n+\n+\t\t\tfor (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {\n+\t\t\t\ttx_siz[i] =\n+\t\t\t\t    core_if->core_params->dev_tx_fifo_size[i];\n+\t\t\t\tcore_if->core_params->dev_tx_fifo_size[i] =\n+\t\t\t\t    core_if->init_txfsiz[i];\n+\t\t\t}\n+\t\t} else {\n+\n+\t\t\tep = get_ep_by_addr(pcd, ep_addr);\n+\n+\t\t\tif (NULL == ep) {\n+\t\t\t\tCFI_INFO\n+\t\t\t\t    (\"%s: Unable to get the endpoint addr=0x%02x\\n\",\n+\t\t\t\t     __func__, ep_addr);\n+\t\t\t\treturn -DWC_E_INVALID;\n+\t\t\t}\n+\n+\t\t\ttx_siz[0] =\n+\t\t\t    params->dev_tx_fifo_size[ep->dwc_ep.tx_fifo_num -\n+\t\t\t\t\t\t     1];\n+\t\t\tparams->dev_tx_fifo_size[ep->dwc_ep.tx_fifo_num - 1] =\n+\t\t\t    GET_CORE_IF(pcd)->init_txfsiz[ep->\n+\t\t\t\t\t\t\t  dwc_ep.tx_fifo_num -\n+\t\t\t\t\t\t\t  1];\n+\t\t}\n+\t}\n+\n+\tif (resize_fifos(GET_CORE_IF(pcd))) {\n+\t\tretval = 0;\n+\t} else {\n+\t\tCFI_INFO\n+\t\t    (\"%s: Error resetting the feature Reset All(FIFO size)\\n\",\n+\t\t     __func__);\n+\t\tif (rx_rst) {\n+\t\t\tparams->dev_rx_fifo_size = rx_siz;\n+\t\t}\n+\n+\t\tif (tx_rst) {\n+\t\t\tif (ep_addr == 0) {\n+\t\t\t\tint i;\n+\t\t\t\tfor (i = 0; i < core_if->hwcfg4.b.num_in_eps;\n+\t\t\t\t     i++) {\n+\t\t\t\t\tcore_if->\n+\t\t\t\t\t    core_params->dev_tx_fifo_size[i] =\n+\t\t\t\t\t    tx_siz[i];\n+\t\t\t\t}\n+\t\t\t} else {\n+\t\t\t\tparams->dev_tx_fifo_size[ep->\n+\t\t\t\t\t\t\t dwc_ep.tx_fifo_num -\n+\t\t\t\t\t\t\t 1] = tx_siz[0];\n+\t\t\t}\n+\t\t}\n+\t\tretval = -DWC_E_INVALID;\n+\t}\n+\treturn retval;\n+}\n+\n+static int cfi_handle_reset_all(struct dwc_otg_pcd *pcd, uint8_t addr)\n+{\n+\tint retval = 0;\n+\tcfi_ep_t *cfiep;\n+\tcfiobject_t *cfi = pcd->cfi;\n+\tdwc_list_link_t *tmp;\n+\n+\tretval = cfi_handle_reset_fifo_val(pcd, addr, 1, 1);\n+\tif (retval < 0) {\n+\t\treturn retval;\n+\t}\n+\n+\t/* If the EP address is known then reset the features for only that EP */\n+\tif (addr) {\n+\t\tcfiep = get_cfi_ep_by_addr(pcd->cfi, addr);\n+\t\tif (NULL == cfiep) {\n+\t\t\tCFI_INFO(\"%s: Error getting the EP address 0x%02x\\n\",\n+\t\t\t\t __func__, addr);\n+\t\t\treturn -DWC_E_INVALID;\n+\t\t}\n+\t\tretval = cfi_ep_reset_all_setup_vals(cfiep);\n+\t\tcfiep->ep->dwc_ep.buff_mode = BM_STANDARD;\n+\t}\n+\t/* Otherwise (wValue == 0), reset all features of all EP's */\n+\telse {\n+\t\t/* Traverse all the active EP's and reset the feature(s) value(s) */\n+\t\t//list_for_each_entry(cfiep, &cfi->active_eps, lh) {\n+\t\tDWC_LIST_FOREACH(tmp, &cfi->active_eps) {\n+\t\t\tcfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh);\n+\t\t\tretval = cfi_ep_reset_all_setup_vals(cfiep);\n+\t\t\tcfiep->ep->dwc_ep.buff_mode = BM_STANDARD;\n+\t\t\tif (retval < 0) {\n+\t\t\t\tCFI_INFO\n+\t\t\t\t    (\"%s: Error resetting the feature Reset All\\n\",\n+\t\t\t\t     __func__);\n+\t\t\t\treturn retval;\n+\t\t\t}\n+\t\t}\n+\t}\n+\treturn retval;\n+}\n+\n+static int cfi_handle_reset_dma_buff_setup(struct dwc_otg_pcd *pcd,\n+\t\t\t\t\t   uint8_t addr)\n+{\n+\tint retval = 0;\n+\tcfi_ep_t *cfiep;\n+\tcfiobject_t *cfi = pcd->cfi;\n+\tdwc_list_link_t *tmp;\n+\n+\t/* If the EP address is known then reset the features for only that EP */\n+\tif (addr) {\n+\t\tcfiep = get_cfi_ep_by_addr(pcd->cfi, addr);\n+\t\tif (NULL == cfiep) {\n+\t\t\tCFI_INFO(\"%s: Error getting the EP address 0x%02x\\n\",\n+\t\t\t\t __func__, addr);\n+\t\t\treturn -DWC_E_INVALID;\n+\t\t}\n+\t\tretval = cfi_reset_sg_val(cfiep);\n+\t}\n+\t/* Otherwise (wValue == 0), reset all features of all EP's */\n+\telse {\n+\t\t/* Traverse all the active EP's and reset the feature(s) value(s) */\n+\t\t//list_for_each_entry(cfiep, &cfi->active_eps, lh) {\n+\t\tDWC_LIST_FOREACH(tmp, &cfi->active_eps) {\n+\t\t\tcfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh);\n+\t\t\tretval = cfi_reset_sg_val(cfiep);\n+\t\t\tif (retval < 0) {\n+\t\t\t\tCFI_INFO\n+\t\t\t\t    (\"%s: Error resetting the feature Buffer Setup\\n\",\n+\t\t\t\t     __func__);\n+\t\t\t\treturn retval;\n+\t\t\t}\n+\t\t}\n+\t}\n+\treturn retval;\n+}\n+\n+static int cfi_handle_reset_concat_val(struct dwc_otg_pcd *pcd, uint8_t addr)\n+{\n+\tint retval = 0;\n+\tcfi_ep_t *cfiep;\n+\tcfiobject_t *cfi = pcd->cfi;\n+\tdwc_list_link_t *tmp;\n+\n+\t/* If the EP address is known then reset the features for only that EP */\n+\tif (addr) {\n+\t\tcfiep = get_cfi_ep_by_addr(pcd->cfi, addr);\n+\t\tif (NULL == cfiep) {\n+\t\t\tCFI_INFO(\"%s: Error getting the EP address 0x%02x\\n\",\n+\t\t\t\t __func__, addr);\n+\t\t\treturn -DWC_E_INVALID;\n+\t\t}\n+\t\tretval = cfi_reset_concat_val(cfiep);\n+\t}\n+\t/* Otherwise (wValue == 0), reset all features of all EP's */\n+\telse {\n+\t\t/* Traverse all the active EP's and reset the feature(s) value(s) */\n+\t\t//list_for_each_entry(cfiep, &cfi->active_eps, lh) {\n+\t\tDWC_LIST_FOREACH(tmp, &cfi->active_eps) {\n+\t\t\tcfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh);\n+\t\t\tretval = cfi_reset_concat_val(cfiep);\n+\t\t\tif (retval < 0) {\n+\t\t\t\tCFI_INFO\n+\t\t\t\t    (\"%s: Error resetting the feature Concatenation Value\\n\",\n+\t\t\t\t     __func__);\n+\t\t\t\treturn retval;\n+\t\t\t}\n+\t\t}\n+\t}\n+\treturn retval;\n+}\n+\n+static int cfi_handle_reset_align_val(struct dwc_otg_pcd *pcd, uint8_t addr)\n+{\n+\tint retval = 0;\n+\tcfi_ep_t *cfiep;\n+\tcfiobject_t *cfi = pcd->cfi;\n+\tdwc_list_link_t *tmp;\n+\n+\t/* If the EP address is known then reset the features for only that EP */\n+\tif (addr) {\n+\t\tcfiep = get_cfi_ep_by_addr(pcd->cfi, addr);\n+\t\tif (NULL == cfiep) {\n+\t\t\tCFI_INFO(\"%s: Error getting the EP address 0x%02x\\n\",\n+\t\t\t\t __func__, addr);\n+\t\t\treturn -DWC_E_INVALID;\n+\t\t}\n+\t\tretval = cfi_reset_align_val(cfiep);\n+\t}\n+\t/* Otherwise (wValue == 0), reset all features of all EP's */\n+\telse {\n+\t\t/* Traverse all the active EP's and reset the feature(s) value(s) */\n+\t\t//list_for_each_entry(cfiep, &cfi->active_eps, lh) {\n+\t\tDWC_LIST_FOREACH(tmp, &cfi->active_eps) {\n+\t\t\tcfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh);\n+\t\t\tretval = cfi_reset_align_val(cfiep);\n+\t\t\tif (retval < 0) {\n+\t\t\t\tCFI_INFO\n+\t\t\t\t    (\"%s: Error resetting the feature Aliignment Value\\n\",\n+\t\t\t\t     __func__);\n+\t\t\t\treturn retval;\n+\t\t\t}\n+\t\t}\n+\t}\n+\treturn retval;\n+\n+}\n+\n+static int cfi_preproc_reset(struct dwc_otg_pcd *pcd,\n+\t\t\t     struct cfi_usb_ctrlrequest *req)\n+{\n+\tint retval = 0;\n+\n+\tswitch (req->wIndex) {\n+\tcase 0:\n+\t\t/* Reset all features */\n+\t\tretval = cfi_handle_reset_all(pcd, req->wValue & 0xff);\n+\t\tbreak;\n+\n+\tcase FT_ID_DMA_BUFFER_SETUP:\n+\t\t/* Reset the SG buffer setup */\n+\t\tretval =\n+\t\t    cfi_handle_reset_dma_buff_setup(pcd, req->wValue & 0xff);\n+\t\tbreak;\n+\n+\tcase FT_ID_DMA_CONCAT_SETUP:\n+\t\t/* Reset the Concatenation buffer setup */\n+\t\tretval = cfi_handle_reset_concat_val(pcd, req->wValue & 0xff);\n+\t\tbreak;\n+\n+\tcase FT_ID_DMA_BUFF_ALIGN:\n+\t\t/* Reset the Alignment buffer setup */\n+\t\tretval = cfi_handle_reset_align_val(pcd, req->wValue & 0xff);\n+\t\tbreak;\n+\n+\tcase FT_ID_TX_FIFO_DEPTH:\n+\t\tretval =\n+\t\t    cfi_handle_reset_fifo_val(pcd, req->wValue & 0xff, 0, 1);\n+\t\tpcd->cfi->need_gadget_att = 0;\n+\t\tbreak;\n+\n+\tcase FT_ID_RX_FIFO_DEPTH:\n+\t\tretval = cfi_handle_reset_fifo_val(pcd, 0, 1, 0);\n+\t\tpcd->cfi->need_gadget_att = 0;\n+\t\tbreak;\n+\tdefault:\n+\t\tbreak;\n+\t}\n+\treturn retval;\n+}\n+\n+/**\n+ * This function sets a new value for the SG buffer setup.\n+ */\n+static int cfi_ep_set_sg_val(uint8_t * buf, struct dwc_otg_pcd *pcd)\n+{\n+\tuint8_t inaddr, outaddr;\n+\tcfi_ep_t *epin, *epout;\n+\tddma_sg_buffer_setup_t *psgval;\n+\tuint32_t desccount, size;\n+\n+\tCFI_INFO(\"%s\\n\", __func__);\n+\n+\tpsgval = (ddma_sg_buffer_setup_t *) buf;\n+\tdesccount = (uint32_t) psgval->bCount;\n+\tsize = (uint32_t) psgval->wSize;\n+\n+\t/* Check the DMA descriptor count */\n+\tif ((desccount > MAX_DMA_DESCS_PER_EP) || (desccount == 0)) {\n+\t\tCFI_INFO\n+\t\t    (\"%s: The count of DMA Descriptors should be between 1 and %d\\n\",\n+\t\t     __func__, MAX_DMA_DESCS_PER_EP);\n+\t\treturn -DWC_E_INVALID;\n+\t}\n+\n+\t/* Check the DMA descriptor count */\n+\n+\tif (size == 0) {\n+\n+\t\tCFI_INFO(\"%s: The transfer size should be at least 1 byte\\n\",\n+\t\t\t __func__);\n+\n+\t\treturn -DWC_E_INVALID;\n+\n+\t}\n+\n+\tinaddr = psgval->bInEndpointAddress;\n+\toutaddr = psgval->bOutEndpointAddress;\n+\n+\tepin = get_cfi_ep_by_addr(pcd->cfi, inaddr);\n+\tepout = get_cfi_ep_by_addr(pcd->cfi, outaddr);\n+\n+\tif (NULL == epin || NULL == epout) {\n+\t\tCFI_INFO\n+\t\t    (\"%s: Unable to get the endpoints inaddr=0x%02x outaddr=0x%02x\\n\",\n+\t\t     __func__, inaddr, outaddr);\n+\t\treturn -DWC_E_INVALID;\n+\t}\n+\n+\tepin->ep->dwc_ep.buff_mode = BM_SG;\n+\tdwc_memcpy(epin->bm_sg, psgval, sizeof(ddma_sg_buffer_setup_t));\n+\n+\tepout->ep->dwc_ep.buff_mode = BM_SG;\n+\tdwc_memcpy(epout->bm_sg, psgval, sizeof(ddma_sg_buffer_setup_t));\n+\n+\treturn 0;\n+}\n+\n+/**\n+ * This function sets a new value for the buffer Alignment setup.\n+ */\n+static int cfi_ep_set_alignment_val(uint8_t * buf, struct dwc_otg_pcd *pcd)\n+{\n+\tcfi_ep_t *ep;\n+\tuint8_t addr;\n+\tddma_align_buffer_setup_t *palignval;\n+\n+\tpalignval = (ddma_align_buffer_setup_t *) buf;\n+\taddr = palignval->bEndpointAddress;\n+\n+\tep = get_cfi_ep_by_addr(pcd->cfi, addr);\n+\n+\tif (NULL == ep) {\n+\t\tCFI_INFO(\"%s: Unable to get the endpoint addr=0x%02x\\n\",\n+\t\t\t __func__, addr);\n+\t\treturn -DWC_E_INVALID;\n+\t}\n+\n+\tep->ep->dwc_ep.buff_mode = BM_ALIGN;\n+\tdwc_memcpy(ep->bm_align, palignval, sizeof(ddma_align_buffer_setup_t));\n+\n+\treturn 0;\n+}\n+\n+/**\n+ * This function sets a new value for the Concatenation buffer setup.\n+ */\n+static int cfi_ep_set_concat_val(uint8_t * buf, struct dwc_otg_pcd *pcd)\n+{\n+\tuint8_t addr;\n+\tcfi_ep_t *ep;\n+\tstruct _ddma_concat_buffer_setup_hdr *pConcatValHdr;\n+\tuint16_t *pVals;\n+\tuint32_t desccount;\n+\tint i;\n+\tuint16_t mps;\n+\n+\tpConcatValHdr = (struct _ddma_concat_buffer_setup_hdr *)buf;\n+\tdesccount = (uint32_t) pConcatValHdr->bDescCount;\n+\tpVals = (uint16_t *) (buf + BS_CONCAT_VAL_HDR_LEN);\n+\n+\t/* Check the DMA descriptor count */\n+\tif (desccount > MAX_DMA_DESCS_PER_EP) {\n+\t\tCFI_INFO(\"%s: Maximum DMA Descriptor count should be %d\\n\",\n+\t\t\t __func__, MAX_DMA_DESCS_PER_EP);\n+\t\treturn -DWC_E_INVALID;\n+\t}\n+\n+\taddr = pConcatValHdr->bEndpointAddress;\n+\tep = get_cfi_ep_by_addr(pcd->cfi, addr);\n+\tif (NULL == ep) {\n+\t\tCFI_INFO(\"%s: Unable to get the endpoint addr=0x%02x\\n\",\n+\t\t\t __func__, addr);\n+\t\treturn -DWC_E_INVALID;\n+\t}\n+\n+\tmps = UGETW(ep->ep->desc->wMaxPacketSize);\n+\n+#if 0\n+\tfor (i = 0; i < desccount; i++) {\n+\t\tCFI_INFO(\"%s: wTxSize[%d]=0x%04x\\n\", __func__, i, pVals[i]);\n+\t}\n+\tCFI_INFO(\"%s: epname=%s; mps=%d\\n\", __func__, ep->ep->ep.name, mps);\n+#endif\n+\n+\t/* Check the wTxSizes to be less than or equal to the mps */\n+\tfor (i = 0; i < desccount; i++) {\n+\t\tif (pVals[i] > mps) {\n+\t\t\tCFI_INFO\n+\t\t\t    (\"%s: ERROR - the wTxSize[%d] should be <= MPS (wTxSize=%d)\\n\",\n+\t\t\t     __func__, i, pVals[i]);\n+\t\t\treturn -DWC_E_INVALID;\n+\t\t}\n+\t}\n+\n+\tep->ep->dwc_ep.buff_mode = BM_CONCAT;\n+\tdwc_memcpy(ep->bm_concat, pConcatValHdr, BS_CONCAT_VAL_HDR_LEN);\n+\n+\t/* Free the previously allocated storage for the wTxBytes */\n+\tif (ep->bm_concat->wTxBytes) {\n+\t\tDWC_FREE(ep->bm_concat->wTxBytes);\n+\t}\n+\n+\t/* Allocate a new storage for the wTxBytes field */\n+\tep->bm_concat->wTxBytes =\n+\t    DWC_ALLOC(sizeof(uint16_t) * pConcatValHdr->bDescCount);\n+\tif (NULL == ep->bm_concat->wTxBytes) {\n+\t\tCFI_INFO(\"%s: Unable to allocate memory\\n\", __func__);\n+\t\treturn -DWC_E_NO_MEMORY;\n+\t}\n+\n+\t/* Copy the new values into the wTxBytes filed */\n+\tdwc_memcpy(ep->bm_concat->wTxBytes, buf + BS_CONCAT_VAL_HDR_LEN,\n+\t\t   sizeof(uint16_t) * pConcatValHdr->bDescCount);\n+\n+\treturn 0;\n+}\n+\n+/**\n+ * This function calculates the total of all FIFO sizes\n+ *\n+ * @param core_if Programming view of DWC_otg controller\n+ *\n+ * @return The total of data FIFO sizes.\n+ *\n+ */\n+static uint16_t get_dfifo_size(dwc_otg_core_if_t * core_if)\n+{\n+\tdwc_otg_core_params_t *params = core_if->core_params;\n+\tuint16_t dfifo_total = 0;\n+\tint i;\n+\n+\t/* The shared RxFIFO size */\n+\tdfifo_total =\n+\t    params->dev_rx_fifo_size + params->dev_nperio_tx_fifo_size;\n+\n+\t/* Add up each TxFIFO size to the total */\n+\tfor (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {\n+\t\tdfifo_total += params->dev_tx_fifo_size[i];\n+\t}\n+\n+\treturn dfifo_total;\n+}\n+\n+/**\n+ * This function returns Rx FIFO size\n+ *\n+ * @param core_if Programming view of DWC_otg controller\n+ *\n+ * @return The total of data FIFO sizes.\n+ *\n+ */\n+static int32_t get_rxfifo_size(dwc_otg_core_if_t * core_if, uint16_t wValue)\n+{\n+\tswitch (wValue >> 8) {\n+\tcase 0:\n+\t\treturn (core_if->pwron_rxfsiz <\n+\t\t\t32768) ? core_if->pwron_rxfsiz : 32768;\n+\t\tbreak;\n+\tcase 1:\n+\t\treturn core_if->core_params->dev_rx_fifo_size;\n+\t\tbreak;\n+\tdefault:\n+\t\treturn -DWC_E_INVALID;\n+\t\tbreak;\n+\t}\n+}\n+\n+/**\n+ * This function returns Tx FIFO size for IN EP\n+ *\n+ * @param core_if Programming view of DWC_otg controller\n+ *\n+ * @return The total of data FIFO sizes.\n+ *\n+ */\n+static int32_t get_txfifo_size(struct dwc_otg_pcd *pcd, uint16_t wValue)\n+{\n+\tdwc_otg_pcd_ep_t *ep;\n+\n+\tep = get_ep_by_addr(pcd, wValue & 0xff);\n+\n+\tif (NULL == ep) {\n+\t\tCFI_INFO(\"%s: Unable to get the endpoint addr=0x%02x\\n\",\n+\t\t\t __func__, wValue & 0xff);\n+\t\treturn -DWC_E_INVALID;\n+\t}\n+\n+\tif (!ep->dwc_ep.is_in) {\n+\t\tCFI_INFO\n+\t\t    (\"%s: No Tx FIFO assingned to the Out endpoint addr=0x%02x\\n\",\n+\t\t     __func__, wValue & 0xff);\n+\t\treturn -DWC_E_INVALID;\n+\t}\n+\n+\tswitch (wValue >> 8) {\n+\tcase 0:\n+\t\treturn (GET_CORE_IF(pcd)->pwron_txfsiz\n+\t\t\t[ep->dwc_ep.tx_fifo_num - 1] <\n+\t\t\t768) ? GET_CORE_IF(pcd)->pwron_txfsiz[ep->\n+\t\t\t\t\t\t\t      dwc_ep.tx_fifo_num\n+\t\t\t\t\t\t\t      - 1] : 32768;\n+\t\tbreak;\n+\tcase 1:\n+\t\treturn GET_CORE_IF(pcd)->core_params->\n+\t\t    dev_tx_fifo_size[ep->dwc_ep.num - 1];\n+\t\tbreak;\n+\tdefault:\n+\t\treturn -DWC_E_INVALID;\n+\t\tbreak;\n+\t}\n+}\n+\n+/**\n+ * This function checks if the submitted combination of\n+ * device mode FIFO sizes is possible or not.\n+ *\n+ * @param core_if Programming view of DWC_otg controller\n+ *\n+ * @return 1 if possible, 0 otherwise.\n+ *\n+ */\n+static uint8_t check_fifo_sizes(dwc_otg_core_if_t * core_if)\n+{\n+\tuint16_t dfifo_actual = 0;\n+\tdwc_otg_core_params_t *params = core_if->core_params;\n+\tuint16_t start_addr = 0;\n+\tint i;\n+\n+\tdfifo_actual =\n+\t    params->dev_rx_fifo_size + params->dev_nperio_tx_fifo_size;\n+\n+\tfor (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {\n+\t\tdfifo_actual += params->dev_tx_fifo_size[i];\n+\t}\n+\n+\tif (dfifo_actual > core_if->total_fifo_size) {\n+\t\treturn 0;\n+\t}\n+\n+\tif (params->dev_rx_fifo_size > 32768 || params->dev_rx_fifo_size < 16)\n+\t\treturn 0;\n+\n+\tif (params->dev_nperio_tx_fifo_size > 32768\n+\t    || params->dev_nperio_tx_fifo_size < 16)\n+\t\treturn 0;\n+\n+\tfor (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {\n+\n+\t\tif (params->dev_tx_fifo_size[i] > 768\n+\t\t    || params->dev_tx_fifo_size[i] < 4)\n+\t\t\treturn 0;\n+\t}\n+\n+\tif (params->dev_rx_fifo_size > core_if->pwron_rxfsiz)\n+\t\treturn 0;\n+\tstart_addr = params->dev_rx_fifo_size;\n+\n+\tif (params->dev_nperio_tx_fifo_size > core_if->pwron_gnptxfsiz)\n+\t\treturn 0;\n+\tstart_addr += params->dev_nperio_tx_fifo_size;\n+\n+\tfor (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {\n+\n+\t\tif (params->dev_tx_fifo_size[i] > core_if->pwron_txfsiz[i])\n+\t\t\treturn 0;\n+\t\tstart_addr += params->dev_tx_fifo_size[i];\n+\t}\n+\n+\treturn 1;\n+}\n+\n+/**\n+ * This function resizes Device mode FIFOs\n+ *\n+ * @param core_if Programming view of DWC_otg controller\n+ *\n+ * @return 1 if successful, 0 otherwise\n+ *\n+ */\n+static uint8_t resize_fifos(dwc_otg_core_if_t * core_if)\n+{\n+\tint i = 0;\n+\tdwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;\n+\tdwc_otg_core_params_t *params = core_if->core_params;\n+\tuint32_t rx_fifo_size;\n+\tfifosize_data_t nptxfifosize;\n+\tfifosize_data_t txfifosize[15];\n+\n+\tuint32_t rx_fsz_bak;\n+\tuint32_t nptxfsz_bak;\n+\tuint32_t txfsz_bak[15];\n+\n+\tuint16_t start_address;\n+\tuint8_t retval = 1;\n+\n+\tif (!check_fifo_sizes(core_if)) {\n+\t\treturn 0;\n+\t}\n+\n+\t/* Configure data FIFO sizes */\n+\tif (core_if->hwcfg2.b.dynamic_fifo && params->enable_dynamic_fifo) {\n+\t\trx_fsz_bak = DWC_READ_REG32(&global_regs->grxfsiz);\n+\t\trx_fifo_size = params->dev_rx_fifo_size;\n+\t\tDWC_WRITE_REG32(&global_regs->grxfsiz, rx_fifo_size);\n+\n+\t\t/*\n+\t\t * Tx FIFOs These FIFOs are numbered from 1 to 15.\n+\t\t * Indexes of the FIFO size module parameters in the\n+\t\t * dev_tx_fifo_size array and the FIFO size registers in\n+\t\t * the dtxfsiz array run from 0 to 14.\n+\t\t */\n+\n+\t\t/* Non-periodic Tx FIFO */\n+\t\tnptxfsz_bak = DWC_READ_REG32(&global_regs->gnptxfsiz);\n+\t\tnptxfifosize.b.depth = params->dev_nperio_tx_fifo_size;\n+\t\tstart_address = params->dev_rx_fifo_size;\n+\t\tnptxfifosize.b.startaddr = start_address;\n+\n+\t\tDWC_WRITE_REG32(&global_regs->gnptxfsiz, nptxfifosize.d32);\n+\n+\t\tstart_address += nptxfifosize.b.depth;\n+\n+\t\tfor (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {\n+\t\t\ttxfsz_bak[i] = DWC_READ_REG32(&global_regs->dtxfsiz[i]);\n+\n+\t\t\ttxfifosize[i].b.depth = params->dev_tx_fifo_size[i];\n+\t\t\ttxfifosize[i].b.startaddr = start_address;\n+\t\t\tDWC_WRITE_REG32(&global_regs->dtxfsiz[i],\n+\t\t\t\t\ttxfifosize[i].d32);\n+\n+\t\t\tstart_address += txfifosize[i].b.depth;\n+\t\t}\n+\n+\t\t/** Check if register values are set correctly */\n+\t\tif (rx_fifo_size != DWC_READ_REG32(&global_regs->grxfsiz)) {\n+\t\t\tretval = 0;\n+\t\t}\n+\n+\t\tif (nptxfifosize.d32 != DWC_READ_REG32(&global_regs->gnptxfsiz)) {\n+\t\t\tretval = 0;\n+\t\t}\n+\n+\t\tfor (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {\n+\t\t\tif (txfifosize[i].d32 !=\n+\t\t\t    DWC_READ_REG32(&global_regs->dtxfsiz[i])) {\n+\t\t\t\tretval = 0;\n+\t\t\t}\n+\t\t}\n+\n+\t\t/** If register values are not set correctly, reset old values */\n+\t\tif (retval == 0) {\n+\t\t\tDWC_WRITE_REG32(&global_regs->grxfsiz, rx_fsz_bak);\n+\n+\t\t\t/* Non-periodic Tx FIFO */\n+\t\t\tDWC_WRITE_REG32(&global_regs->gnptxfsiz, nptxfsz_bak);\n+\n+\t\t\tfor (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {\n+\t\t\t\tDWC_WRITE_REG32(&global_regs->dtxfsiz[i],\n+\t\t\t\t\t\ttxfsz_bak[i]);\n+\t\t\t}\n+\t\t}\n+\t} else {\n+\t\treturn 0;\n+\t}\n+\n+\t/* Flush the FIFOs */\n+\tdwc_otg_flush_tx_fifo(core_if, 0x10);\t/* all Tx FIFOs */\n+\tdwc_otg_flush_rx_fifo(core_if);\n+\n+\treturn retval;\n+}\n+\n+/**\n+ * This function sets a new value for the buffer Alignment setup.\n+ */\n+static int cfi_ep_set_tx_fifo_val(uint8_t * buf, dwc_otg_pcd_t * pcd)\n+{\n+\tint retval;\n+\tuint32_t fsiz;\n+\tuint16_t size;\n+\tuint16_t ep_addr;\n+\tdwc_otg_pcd_ep_t *ep;\n+\tdwc_otg_core_params_t *params = GET_CORE_IF(pcd)->core_params;\n+\ttx_fifo_size_setup_t *ptxfifoval;\n+\n+\tptxfifoval = (tx_fifo_size_setup_t *) buf;\n+\tep_addr = ptxfifoval->bEndpointAddress;\n+\tsize = ptxfifoval->wDepth;\n+\n+\tep = get_ep_by_addr(pcd, ep_addr);\n+\n+\tCFI_INFO\n+\t    (\"%s: Set Tx FIFO size: endpoint addr=0x%02x, depth=%d, FIFO Num=%d\\n\",\n+\t     __func__, ep_addr, size, ep->dwc_ep.tx_fifo_num);\n+\n+\tif (NULL == ep) {\n+\t\tCFI_INFO(\"%s: Unable to get the endpoint addr=0x%02x\\n\",\n+\t\t\t __func__, ep_addr);\n+\t\treturn -DWC_E_INVALID;\n+\t}\n+\n+\tfsiz = params->dev_tx_fifo_size[ep->dwc_ep.tx_fifo_num - 1];\n+\tparams->dev_tx_fifo_size[ep->dwc_ep.tx_fifo_num - 1] = size;\n+\n+\tif (resize_fifos(GET_CORE_IF(pcd))) {\n+\t\tretval = 0;\n+\t} else {\n+\t\tCFI_INFO\n+\t\t    (\"%s: Error setting the feature Tx FIFO Size for EP%d\\n\",\n+\t\t     __func__, ep_addr);\n+\t\tparams->dev_tx_fifo_size[ep->dwc_ep.tx_fifo_num - 1] = fsiz;\n+\t\tretval = -DWC_E_INVALID;\n+\t}\n+\n+\treturn retval;\n+}\n+\n+/**\n+ * This function sets a new value for the buffer Alignment setup.\n+ */\n+static int cfi_set_rx_fifo_val(uint8_t * buf, dwc_otg_pcd_t * pcd)\n+{\n+\tint retval;\n+\tuint32_t fsiz;\n+\tuint16_t size;\n+\tdwc_otg_core_params_t *params = GET_CORE_IF(pcd)->core_params;\n+\trx_fifo_size_setup_t *prxfifoval;\n+\n+\tprxfifoval = (rx_fifo_size_setup_t *) buf;\n+\tsize = prxfifoval->wDepth;\n+\n+\tfsiz = params->dev_rx_fifo_size;\n+\tparams->dev_rx_fifo_size = size;\n+\n+\tif (resize_fifos(GET_CORE_IF(pcd))) {\n+\t\tretval = 0;\n+\t} else {\n+\t\tCFI_INFO(\"%s: Error setting the feature Rx FIFO Size\\n\",\n+\t\t\t __func__);\n+\t\tparams->dev_rx_fifo_size = fsiz;\n+\t\tretval = -DWC_E_INVALID;\n+\t}\n+\n+\treturn retval;\n+}\n+\n+/**\n+ * This function reads the SG of an EP's buffer setup into the buffer buf\n+ */\n+static int cfi_ep_get_sg_val(uint8_t * buf, struct dwc_otg_pcd *pcd,\n+\t\t\t     struct cfi_usb_ctrlrequest *req)\n+{\n+\tint retval = -DWC_E_INVALID;\n+\tuint8_t addr;\n+\tcfi_ep_t *ep;\n+\n+\t/* The Low Byte of the wValue contains a non-zero address of the endpoint */\n+\taddr = req->wValue & 0xFF;\n+\tif (addr == 0)\t\t/* The address should be non-zero */\n+\t\treturn retval;\n+\n+\tep = get_cfi_ep_by_addr(pcd->cfi, addr);\n+\tif (NULL == ep) {\n+\t\tCFI_INFO(\"%s: Unable to get the endpoint address(0x%02x)\\n\",\n+\t\t\t __func__, addr);\n+\t\treturn retval;\n+\t}\n+\n+\tdwc_memcpy(buf, ep->bm_sg, BS_SG_VAL_DESC_LEN);\n+\tretval = BS_SG_VAL_DESC_LEN;\n+\treturn retval;\n+}\n+\n+/**\n+ * This function reads the Concatenation value of an EP's buffer mode into\n+ * the buffer buf\n+ */\n+static int cfi_ep_get_concat_val(uint8_t * buf, struct dwc_otg_pcd *pcd,\n+\t\t\t\t struct cfi_usb_ctrlrequest *req)\n+{\n+\tint retval = -DWC_E_INVALID;\n+\tuint8_t addr;\n+\tcfi_ep_t *ep;\n+\tuint8_t desc_count;\n+\n+\t/* The Low Byte of the wValue contains a non-zero address of the endpoint */\n+\taddr = req->wValue & 0xFF;\n+\tif (addr == 0)\t\t/* The address should be non-zero */\n+\t\treturn retval;\n+\n+\tep = get_cfi_ep_by_addr(pcd->cfi, addr);\n+\tif (NULL == ep) {\n+\t\tCFI_INFO(\"%s: Unable to get the endpoint address(0x%02x)\\n\",\n+\t\t\t __func__, addr);\n+\t\treturn retval;\n+\t}\n+\n+\t/* Copy the header to the buffer */\n+\tdwc_memcpy(buf, ep->bm_concat, BS_CONCAT_VAL_HDR_LEN);\n+\t/* Advance the buffer pointer by the header size */\n+\tbuf += BS_CONCAT_VAL_HDR_LEN;\n+\n+\tdesc_count = ep->bm_concat->hdr.bDescCount;\n+\t/* Copy alll the wTxBytes to the buffer */\n+\tdwc_memcpy(buf, ep->bm_concat->wTxBytes, sizeof(uid16_t) * desc_count);\n+\n+\tretval = BS_CONCAT_VAL_HDR_LEN + sizeof(uid16_t) * desc_count;\n+\treturn retval;\n+}\n+\n+/**\n+ * This function reads the buffer Alignment value of an EP's buffer mode into\n+ * the buffer buf\n+ *\n+ * @return The total number of bytes copied to the buffer or negative error code.\n+ */\n+static int cfi_ep_get_align_val(uint8_t * buf, struct dwc_otg_pcd *pcd,\n+\t\t\t\tstruct cfi_usb_ctrlrequest *req)\n+{\n+\tint retval = -DWC_E_INVALID;\n+\tuint8_t addr;\n+\tcfi_ep_t *ep;\n+\n+\t/* The Low Byte of the wValue contains a non-zero address of the endpoint */\n+\taddr = req->wValue & 0xFF;\n+\tif (addr == 0)\t\t/* The address should be non-zero */\n+\t\treturn retval;\n+\n+\tep = get_cfi_ep_by_addr(pcd->cfi, addr);\n+\tif (NULL == ep) {\n+\t\tCFI_INFO(\"%s: Unable to get the endpoint address(0x%02x)\\n\",\n+\t\t\t __func__, addr);\n+\t\treturn retval;\n+\t}\n+\n+\tdwc_memcpy(buf, ep->bm_align, BS_ALIGN_VAL_HDR_LEN);\n+\tretval = BS_ALIGN_VAL_HDR_LEN;\n+\n+\treturn retval;\n+}\n+\n+/**\n+ * This function sets a new value for the specified feature\n+ *\n+ * @param\tpcd\tA pointer to the PCD object\n+ *\n+ * @return 0 if successful, negative error code otherwise to stall the DCE.\n+ */\n+static int cfi_set_feature_value(struct dwc_otg_pcd *pcd)\n+{\n+\tint retval = -DWC_E_NOT_SUPPORTED;\n+\tuint16_t wIndex, wValue;\n+\tuint8_t bRequest;\n+\tstruct dwc_otg_core_if *coreif;\n+\tcfiobject_t *cfi = pcd->cfi;\n+\tstruct cfi_usb_ctrlrequest *ctrl_req;\n+\tuint8_t *buf;\n+\tctrl_req = &cfi->ctrl_req;\n+\n+\tbuf = pcd->cfi->ctrl_req.data;\n+\n+\tcoreif = GET_CORE_IF(pcd);\n+\tbRequest = ctrl_req->bRequest;\n+\twIndex = DWC_CONSTANT_CPU_TO_LE16(ctrl_req->wIndex);\n+\twValue = DWC_CONSTANT_CPU_TO_LE16(ctrl_req->wValue);\n+\n+\t/* See which feature is to be modified */\n+\tswitch (wIndex) {\n+\tcase FT_ID_DMA_BUFFER_SETUP:\n+\t\t/* Modify the feature */\n+\t\tif ((retval = cfi_ep_set_sg_val(buf, pcd)) < 0)\n+\t\t\treturn retval;\n+\n+\t\t/* And send this request to the gadget */\n+\t\tcfi->need_gadget_att = 1;\n+\t\tbreak;\n+\n+\tcase FT_ID_DMA_BUFF_ALIGN:\n+\t\tif ((retval = cfi_ep_set_alignment_val(buf, pcd)) < 0)\n+\t\t\treturn retval;\n+\t\tcfi->need_gadget_att = 1;\n+\t\tbreak;\n+\n+\tcase FT_ID_DMA_CONCAT_SETUP:\n+\t\t/* Modify the feature */\n+\t\tif ((retval = cfi_ep_set_concat_val(buf, pcd)) < 0)\n+\t\t\treturn retval;\n+\t\tcfi->need_gadget_att = 1;\n+\t\tbreak;\n+\n+\tcase FT_ID_DMA_CIRCULAR:\n+\t\tCFI_INFO(\"FT_ID_DMA_CIRCULAR\\n\");\n+\t\tbreak;\n+\n+\tcase FT_ID_THRESHOLD_SETUP:\n+\t\tCFI_INFO(\"FT_ID_THRESHOLD_SETUP\\n\");\n+\t\tbreak;\n+\n+\tcase FT_ID_DFIFO_DEPTH:\n+\t\tCFI_INFO(\"FT_ID_DFIFO_DEPTH\\n\");\n+\t\tbreak;\n+\n+\tcase FT_ID_TX_FIFO_DEPTH:\n+\t\tCFI_INFO(\"FT_ID_TX_FIFO_DEPTH\\n\");\n+\t\tif ((retval = cfi_ep_set_tx_fifo_val(buf, pcd)) < 0)\n+\t\t\treturn retval;\n+\t\tcfi->need_gadget_att = 0;\n+\t\tbreak;\n+\n+\tcase FT_ID_RX_FIFO_DEPTH:\n+\t\tCFI_INFO(\"FT_ID_RX_FIFO_DEPTH\\n\");\n+\t\tif ((retval = cfi_set_rx_fifo_val(buf, pcd)) < 0)\n+\t\t\treturn retval;\n+\t\tcfi->need_gadget_att = 0;\n+\t\tbreak;\n+\t}\n+\n+\treturn retval;\n+}\n+\n+#endif //DWC_UTE_CFI\n--- /dev/null\n+++ b/drivers/usb/host/dwc_otg/dwc_otg_cfi.h\n@@ -0,0 +1,320 @@\n+/* ==========================================================================\n+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,\n+ * \"Software\") is an Unsupported proprietary work of Synopsys, Inc. unless\n+ * otherwise expressly agreed to in writing between Synopsys and you.\n+ *\n+ * The Software IS NOT an item of Licensed Software or Licensed Product under\n+ * any End User Software License Agreement or Agreement for Licensed Product\n+ * with Synopsys or any supplement thereto. You are permitted to use and\n+ * redistribute this Software in source and binary forms, with or without\n+ * modification, provided that redistributions of source code must retain this\n+ * notice. You may not view, use, disclose, copy or distribute this file or\n+ * any information contained herein except pursuant to this license grant from\n+ * Synopsys. If you do not agree with this notice, including the disclaimer\n+ * below, then you are not authorized to use the Software.\n+ *\n+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN \"AS IS\" BASIS\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,\n+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH\n+ * DAMAGE.\n+ * ========================================================================== */\n+\n+#if !defined(__DWC_OTG_CFI_H__)\n+#define __DWC_OTG_CFI_H__\n+\n+#include \"dwc_otg_pcd.h\"\n+#include \"dwc_cfi_common.h\"\n+\n+/**\n+ * @file\n+ * This file contains the CFI related OTG PCD specific common constants,\n+ * interfaces(functions and macros) and data structures.The CFI Protocol is an\n+ * optional interface for internal testing purposes that a DUT may implement to\n+ * support testing of configurable features.\n+ *\n+ */\n+\n+struct dwc_otg_pcd;\n+struct dwc_otg_pcd_ep;\n+\n+/** OTG CFI Features (properties) ID constants */\n+/** This is a request for all Core Features */\n+#define FT_ID_DMA_MODE\t\t\t\t\t0x0001\n+#define FT_ID_DMA_BUFFER_SETUP\t\t\t0x0002\n+#define FT_ID_DMA_BUFF_ALIGN\t\t\t0x0003\n+#define FT_ID_DMA_CONCAT_SETUP\t\t\t0x0004\n+#define FT_ID_DMA_CIRCULAR\t\t\t\t0x0005\n+#define FT_ID_THRESHOLD_SETUP\t\t\t0x0006\n+#define FT_ID_DFIFO_DEPTH\t\t\t\t0x0007\n+#define FT_ID_TX_FIFO_DEPTH\t\t\t\t0x0008\n+#define FT_ID_RX_FIFO_DEPTH\t\t\t\t0x0009\n+\n+/**********************************************************/\n+#define CFI_INFO_DEF\n+\n+#ifdef CFI_INFO_DEF\n+#define CFI_INFO(fmt...)\tDWC_PRINTF(\"CFI: \" fmt);\n+#else\n+#define CFI_INFO(fmt...)\n+#endif\n+\n+#define min(x,y) ({ \\\n+\tx < y ? x : y; })\n+\n+#define max(x,y) ({ \\\n+\tx > y ? x : y; })\n+\n+/**\n+ * Descriptor DMA SG Buffer setup structure (SG buffer). This structure is\n+ * also used for setting up a buffer for Circular DDMA.\n+ */\n+struct _ddma_sg_buffer_setup {\n+#define BS_SG_VAL_DESC_LEN\t6\n+\t/* The OUT EP address */\n+\tuint8_t bOutEndpointAddress;\n+\t/* The IN EP address */\n+\tuint8_t bInEndpointAddress;\n+\t/* Number of bytes to put between transfer segments (must be DWORD boundaries) */\n+\tuint8_t bOffset;\n+\t/* The number of transfer segments (a DMA descriptors per each segment) */\n+\tuint8_t bCount;\n+\t/* Size (in byte) of each transfer segment */\n+\tuint16_t wSize;\n+} __attribute__ ((packed));\n+typedef struct _ddma_sg_buffer_setup ddma_sg_buffer_setup_t;\n+\n+/** Descriptor DMA Concatenation Buffer setup structure */\n+struct _ddma_concat_buffer_setup_hdr {\n+#define BS_CONCAT_VAL_HDR_LEN\t4\n+\t/* The endpoint for which the buffer is to be set up */\n+\tuint8_t bEndpointAddress;\n+\t/* The count of descriptors to be used */\n+\tuint8_t bDescCount;\n+\t/* The total size of the transfer */\n+\tuint16_t wSize;\n+} __attribute__ ((packed));\n+typedef struct _ddma_concat_buffer_setup_hdr ddma_concat_buffer_setup_hdr_t;\n+\n+/** Descriptor DMA Concatenation Buffer setup structure */\n+struct _ddma_concat_buffer_setup {\n+\t/* The SG header */\n+\tddma_concat_buffer_setup_hdr_t hdr;\n+\n+\t/* The XFER sizes pointer (allocated dynamically) */\n+\tuint16_t *wTxBytes;\n+} __attribute__ ((packed));\n+typedef struct _ddma_concat_buffer_setup ddma_concat_buffer_setup_t;\n+\n+/** Descriptor DMA Alignment Buffer setup structure */\n+struct _ddma_align_buffer_setup {\n+#define BS_ALIGN_VAL_HDR_LEN\t2\n+\tuint8_t bEndpointAddress;\n+\tuint8_t bAlign;\n+} __attribute__ ((packed));\n+typedef struct _ddma_align_buffer_setup ddma_align_buffer_setup_t;\n+\n+/** Transmit FIFO Size setup structure */\n+struct _tx_fifo_size_setup {\n+\tuint8_t bEndpointAddress;\n+\tuint16_t wDepth;\n+} __attribute__ ((packed));\n+typedef struct _tx_fifo_size_setup tx_fifo_size_setup_t;\n+\n+/** Transmit FIFO Size setup structure */\n+struct _rx_fifo_size_setup {\n+\tuint16_t wDepth;\n+} __attribute__ ((packed));\n+typedef struct _rx_fifo_size_setup rx_fifo_size_setup_t;\n+\n+/**\n+ * struct cfi_usb_ctrlrequest - the CFI implementation of the struct usb_ctrlrequest\n+ * This structure encapsulates the standard usb_ctrlrequest and adds a pointer\n+ * to the data returned in the data stage of a 3-stage Control Write requests.\n+ */\n+struct cfi_usb_ctrlrequest {\n+\tuint8_t bRequestType;\n+\tuint8_t bRequest;\n+\tuint16_t wValue;\n+\tuint16_t wIndex;\n+\tuint16_t wLength;\n+\tuint8_t *data;\n+} UPACKED;\n+\n+/*---------------------------------------------------------------------------*/\n+\n+/**\n+ * The CFI wrapper of the enabled and activated dwc_otg_pcd_ep structures.\n+ * This structure is used to store the buffer setup data for any\n+ * enabled endpoint in the PCD.\n+ */\n+struct cfi_ep {\n+\t/* Entry for the list container */\n+\tdwc_list_link_t lh;\n+\t/* Pointer to the active PCD endpoint structure */\n+\tstruct dwc_otg_pcd_ep *ep;\n+\t/* The last descriptor in the chain of DMA descriptors of the endpoint */\n+\tstruct dwc_otg_dma_desc *dma_desc_last;\n+\t/* The SG feature value */\n+\tddma_sg_buffer_setup_t *bm_sg;\n+\t/* The Circular feature value */\n+\tddma_sg_buffer_setup_t *bm_circ;\n+\t/* The Concatenation feature value */\n+\tddma_concat_buffer_setup_t *bm_concat;\n+\t/* The Alignment feature value */\n+\tddma_align_buffer_setup_t *bm_align;\n+\t/* XFER length */\n+\tuint32_t xfer_len;\n+\t/*\n+\t * Count of DMA descriptors currently used.\n+\t * The total should not exceed the MAX_DMA_DESCS_PER_EP value\n+\t * defined in the dwc_otg_cil.h\n+\t */\n+\tuint32_t desc_count;\n+};\n+typedef struct cfi_ep cfi_ep_t;\n+\n+typedef struct cfi_dma_buff {\n+#define CFI_IN_BUF_LEN\t1024\n+#define CFI_OUT_BUF_LEN\t1024\n+\tdma_addr_t addr;\n+\tuint8_t *buf;\n+} cfi_dma_buff_t;\n+\n+struct cfiobject;\n+\n+/**\n+ * This is the interface for the CFI operations.\n+ *\n+ * @param\tep_enable\t\t\tCalled when any endpoint is enabled and activated.\n+ * @param\trelease\t\t\t\tCalled when the CFI object is released and it needs to correctly\n+ *\t\t\t\t\t\t\t\tdeallocate the dynamic memory\n+ * @param\tctrl_write_complete\tCalled when the data stage of the request is complete\n+ */\n+typedef struct cfi_ops {\n+\tint (*ep_enable) (struct cfiobject * cfi, struct dwc_otg_pcd * pcd,\n+\t\t\t  struct dwc_otg_pcd_ep * ep);\n+\tvoid *(*ep_alloc_buf) (struct cfiobject * cfi, struct dwc_otg_pcd * pcd,\n+\t\t\t       struct dwc_otg_pcd_ep * ep, dma_addr_t * dma,\n+\t\t\t       unsigned size, gfp_t flags);\n+\tvoid (*release) (struct cfiobject * cfi);\n+\tint (*ctrl_write_complete) (struct cfiobject * cfi,\n+\t\t\t\t    struct dwc_otg_pcd * pcd);\n+\tvoid (*build_descriptors) (struct cfiobject * cfi,\n+\t\t\t\t   struct dwc_otg_pcd * pcd,\n+\t\t\t\t   struct dwc_otg_pcd_ep * ep,\n+\t\t\t\t   dwc_otg_pcd_request_t * req);\n+} cfi_ops_t;\n+\n+struct cfiobject {\n+\tcfi_ops_t ops;\n+\tstruct dwc_otg_pcd *pcd;\n+\tstruct usb_gadget *gadget;\n+\n+\t/* Buffers used to send/receive CFI-related request data */\n+\tcfi_dma_buff_t buf_in;\n+\tcfi_dma_buff_t buf_out;\n+\n+\t/* CFI specific Control request wrapper */\n+\tstruct cfi_usb_ctrlrequest ctrl_req;\n+\n+\t/* The list of active EP's in the PCD of type cfi_ep_t */\n+\tdwc_list_link_t active_eps;\n+\n+\t/* This flag shall control the propagation of a specific request\n+\t * to the gadget's processing routines.\n+\t * 0 - no gadget handling\n+\t * 1 - the gadget needs to know about this request (w/o completing a status\n+\t * phase - just return a 0 to the _setup callback)\n+\t */\n+\tuint8_t need_gadget_att;\n+\n+\t/* Flag indicating whether the status IN phase needs to be\n+\t * completed by the PCD\n+\t */\n+\tuint8_t need_status_in_complete;\n+};\n+typedef struct cfiobject cfiobject_t;\n+\n+#define DUMP_MSG\n+\n+#if defined(DUMP_MSG)\n+static inline void dump_msg(const u8 * buf, unsigned int length)\n+{\n+\tunsigned int start, num, i;\n+\tchar line[52], *p;\n+\n+\tif (length >= 512)\n+\t\treturn;\n+\n+\tstart = 0;\n+\twhile (length > 0) {\n+\t\tnum = min(length, 16u);\n+\t\tp = line;\n+\t\tfor (i = 0; i < num; ++i) {\n+\t\t\tif (i == 8)\n+\t\t\t\t*p++ = ' ';\n+\t\t\tDWC_SPRINTF(p, \" %02x\", buf[i]);\n+\t\t\tp += 3;\n+\t\t}\n+\t\t*p = 0;\n+\t\tDWC_DEBUG(\"%6x: %s\\n\", start, line);\n+\t\tbuf += num;\n+\t\tstart += num;\n+\t\tlength -= num;\n+\t}\n+}\n+#else\n+static inline void dump_msg(const u8 * buf, unsigned int length)\n+{\n+}\n+#endif\n+\n+/**\n+ * This function returns a pointer to cfi_ep_t object with the addr address.\n+ */\n+static inline struct cfi_ep *get_cfi_ep_by_addr(struct cfiobject *cfi,\n+\t\t\t\t\t\tuint8_t addr)\n+{\n+\tstruct cfi_ep *pcfiep;\n+\tdwc_list_link_t *tmp;\n+\n+\tDWC_LIST_FOREACH(tmp, &cfi->active_eps) {\n+\t\tpcfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh);\n+\n+\t\tif (pcfiep->ep->desc->bEndpointAddress == addr) {\n+\t\t\treturn pcfiep;\n+\t\t}\n+\t}\n+\n+\treturn NULL;\n+}\n+\n+/**\n+ * This function returns a pointer to cfi_ep_t object that matches\n+ * the dwc_otg_pcd_ep object.\n+ */\n+static inline struct cfi_ep *get_cfi_ep_by_pcd_ep(struct cfiobject *cfi,\n+\t\t\t\t\t\t  struct dwc_otg_pcd_ep *ep)\n+{\n+\tstruct cfi_ep *pcfiep = NULL;\n+\tdwc_list_link_t *tmp;\n+\n+\tDWC_LIST_FOREACH(tmp, &cfi->active_eps) {\n+\t\tpcfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh);\n+\t\tif (pcfiep->ep == ep) {\n+\t\t\treturn pcfiep;\n+\t\t}\n+\t}\n+\treturn NULL;\n+}\n+\n+int cfi_setup(struct dwc_otg_pcd *pcd, struct cfi_usb_ctrlrequest *ctrl);\n+\n+#endif /* (__DWC_OTG_CFI_H__) */\n--- /dev/null\n+++ b/drivers/usb/host/dwc_otg/dwc_otg_cil.c\n@@ -0,0 +1,7146 @@\n+/* ==========================================================================\n+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_cil.c $\n+ * $Revision: #191 $\n+ * $Date: 2012/08/10 $\n+ * $Change: 2047372 $\n+ *\n+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,\n+ * \"Software\") is an Unsupported proprietary work of Synopsys, Inc. unless\n+ * otherwise expressly agreed to in writing between Synopsys and you.\n+ *\n+ * The Software IS NOT an item of Licensed Software or Licensed Product under\n+ * any End User Software License Agreement or Agreement for Licensed Product\n+ * with Synopsys or any supplement thereto. You are permitted to use and\n+ * redistribute this Software in source and binary forms, with or without\n+ * modification, provided that redistributions of source code must retain this\n+ * notice. You may not view, use, disclose, copy or distribute this file or\n+ * any information contained herein except pursuant to this license grant from\n+ * Synopsys. If you do not agree with this notice, including the disclaimer\n+ * below, then you are not authorized to use the Software.\n+ *\n+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN \"AS IS\" BASIS\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,\n+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH\n+ * DAMAGE.\n+ * ========================================================================== */\n+\n+/** @file\n+ *\n+ * The Core Interface Layer provides basic services for accessing and\n+ * managing the DWC_otg hardware. These services are used by both the\n+ * Host Controller Driver and the Peripheral Controller Driver.\n+ *\n+ * The CIL manages the memory map for the core so that the HCD and PCD\n+ * don't have to do this separately. It also handles basic tasks like\n+ * reading/writing the registers and data FIFOs in the controller.\n+ * Some of the data access functions provide encapsulation of several\n+ * operations required to perform a task, such as writing multiple\n+ * registers to start a transfer. Finally, the CIL performs basic\n+ * services that are not specific to either the host or device modes\n+ * of operation. These services include management of the OTG Host\n+ * Negotiation Protocol (HNP) and Session Request Protocol (SRP). A\n+ * Diagnostic API is also provided to allow testing of the controller\n+ * hardware.\n+ *\n+ * The Core Interface Layer has the following requirements:\n+ * - Provides basic controller operations.\n+ * - Minimal use of OS services.\n+ * - The OS services used will be abstracted by using inline functions\n+ *\t or macros.\n+ *\n+ */\n+\n+#include \"dwc_os.h\"\n+#include \"dwc_otg_regs.h\"\n+#include \"dwc_otg_cil.h\"\n+\n+extern bool cil_force_host;\n+\n+static int dwc_otg_setup_params(dwc_otg_core_if_t * core_if);\n+\n+/**\n+ * This function is called to initialize the DWC_otg CSR data\n+ * structures. The register addresses in the device and host\n+ * structures are initialized from the base address supplied by the\n+ * caller. The calling function must make the OS calls to get the\n+ * base address of the DWC_otg controller registers. The core_params\n+ * argument holds the parameters that specify how the core should be\n+ * configured.\n+ *\n+ * @param reg_base_addr Base address of DWC_otg core registers\n+ *\n+ */\n+dwc_otg_core_if_t *dwc_otg_cil_init(const uint32_t * reg_base_addr)\n+{\n+\tdwc_otg_core_if_t *core_if = 0;\n+\tdwc_otg_dev_if_t *dev_if = 0;\n+\tdwc_otg_host_if_t *host_if = 0;\n+\tuint8_t *reg_base = (uint8_t *) reg_base_addr;\n+\tint i = 0;\n+\n+\tDWC_DEBUGPL(DBG_CILV, \"%s(%p)\\n\", __func__, reg_base_addr);\n+\n+\tcore_if = DWC_ALLOC(sizeof(dwc_otg_core_if_t));\n+\n+\tif (core_if == NULL) {\n+\t\tDWC_DEBUGPL(DBG_CIL,\n+\t\t\t    \"Allocation of dwc_otg_core_if_t failed\\n\");\n+\t\treturn 0;\n+\t}\n+\tcore_if->core_global_regs = (dwc_otg_core_global_regs_t *) reg_base;\n+\n+\t/*\n+\t * Allocate the Device Mode structures.\n+\t */\n+\tdev_if = DWC_ALLOC(sizeof(dwc_otg_dev_if_t));\n+\n+\tif (dev_if == NULL) {\n+\t\tDWC_DEBUGPL(DBG_CIL, \"Allocation of dwc_otg_dev_if_t failed\\n\");\n+\t\tDWC_FREE(core_if);\n+\t\treturn 0;\n+\t}\n+\n+\tdev_if->dev_global_regs =\n+\t    (dwc_otg_device_global_regs_t *) (reg_base +\n+\t\t\t\t\t      DWC_DEV_GLOBAL_REG_OFFSET);\n+\n+\tfor (i = 0; i < MAX_EPS_CHANNELS; i++) {\n+\t\tdev_if->in_ep_regs[i] = (dwc_otg_dev_in_ep_regs_t *)\n+\t\t    (reg_base + DWC_DEV_IN_EP_REG_OFFSET +\n+\t\t     (i * DWC_EP_REG_OFFSET));\n+\n+\t\tdev_if->out_ep_regs[i] = (dwc_otg_dev_out_ep_regs_t *)\n+\t\t    (reg_base + DWC_DEV_OUT_EP_REG_OFFSET +\n+\t\t     (i * DWC_EP_REG_OFFSET));\n+\t\tDWC_DEBUGPL(DBG_CILV, \"in_ep_regs[%d]->diepctl=%p\\n\",\n+\t\t\t    i, &dev_if->in_ep_regs[i]->diepctl);\n+\t\tDWC_DEBUGPL(DBG_CILV, \"out_ep_regs[%d]->doepctl=%p\\n\",\n+\t\t\t    i, &dev_if->out_ep_regs[i]->doepctl);\n+\t}\n+\n+\tdev_if->speed = 0;\t// unknown\n+\n+\tcore_if->dev_if = dev_if;\n+\n+\t/*\n+\t * Allocate the Host Mode structures.\n+\t */\n+\thost_if = DWC_ALLOC(sizeof(dwc_otg_host_if_t));\n+\n+\tif (host_if == NULL) {\n+\t\tDWC_DEBUGPL(DBG_CIL,\n+\t\t\t    \"Allocation of dwc_otg_host_if_t failed\\n\");\n+\t\tDWC_FREE(dev_if);\n+\t\tDWC_FREE(core_if);\n+\t\treturn 0;\n+\t}\n+\n+\thost_if->host_global_regs = (dwc_otg_host_global_regs_t *)\n+\t    (reg_base + DWC_OTG_HOST_GLOBAL_REG_OFFSET);\n+\n+\thost_if->hprt0 =\n+\t    (uint32_t *) (reg_base + DWC_OTG_HOST_PORT_REGS_OFFSET);\n+\n+\tfor (i = 0; i < MAX_EPS_CHANNELS; i++) {\n+\t\thost_if->hc_regs[i] = (dwc_otg_hc_regs_t *)\n+\t\t    (reg_base + DWC_OTG_HOST_CHAN_REGS_OFFSET +\n+\t\t     (i * DWC_OTG_CHAN_REGS_OFFSET));\n+\t\tDWC_DEBUGPL(DBG_CILV, \"hc_reg[%d]->hcchar=%p\\n\",\n+\t\t\t    i, &host_if->hc_regs[i]->hcchar);\n+\t}\n+\n+\thost_if->num_host_channels = MAX_EPS_CHANNELS;\n+\tcore_if->host_if = host_if;\n+\n+\tfor (i = 0; i < MAX_EPS_CHANNELS; i++) {\n+\t\tcore_if->data_fifo[i] =\n+\t\t    (uint32_t *) (reg_base + DWC_OTG_DATA_FIFO_OFFSET +\n+\t\t\t\t  (i * DWC_OTG_DATA_FIFO_SIZE));\n+\t\tDWC_DEBUGPL(DBG_CILV, \"data_fifo[%d]=0x%08lx\\n\",\n+\t\t\t    i, (unsigned long)core_if->data_fifo[i]);\n+\t}\n+\n+\tcore_if->pcgcctl = (uint32_t *) (reg_base + DWC_OTG_PCGCCTL_OFFSET);\n+\n+\t/* Initiate lx_state to L3 disconnected state */\n+\tcore_if->lx_state = DWC_OTG_L3;\n+\t/*\n+\t * Store the contents of the hardware configuration registers here for\n+\t * easy access later.\n+\t */\n+\tcore_if->hwcfg1.d32 =\n+\t    DWC_READ_REG32(&core_if->core_global_regs->ghwcfg1);\n+\tcore_if->hwcfg2.d32 =\n+\t    DWC_READ_REG32(&core_if->core_global_regs->ghwcfg2);\n+\tcore_if->hwcfg3.d32 =\n+\t    DWC_READ_REG32(&core_if->core_global_regs->ghwcfg3);\n+\tcore_if->hwcfg4.d32 =\n+\t    DWC_READ_REG32(&core_if->core_global_regs->ghwcfg4);\n+\n+\t/* Force host mode to get HPTXFSIZ exact power on value */\n+\t{\n+\t\tgusbcfg_data_t gusbcfg = {.d32 = 0 };\n+\t\tgusbcfg.d32 =  DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);\n+\t\tgusbcfg.b.force_host_mode = 1;\n+\t\tDWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, gusbcfg.d32);\n+\t\tdwc_mdelay(100);\n+\t\tcore_if->hptxfsiz.d32 =\n+\t\tDWC_READ_REG32(&core_if->core_global_regs->hptxfsiz);\n+\t\tgusbcfg.d32 =  DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);\n+\t\tif (cil_force_host)\n+\t\t\tgusbcfg.b.force_host_mode = 1;\n+\t\telse\n+\t\t\tgusbcfg.b.force_host_mode = 0;\n+\t\tDWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, gusbcfg.d32);\n+\t\tdwc_mdelay(100);\n+\t}\n+\n+\tDWC_DEBUGPL(DBG_CILV, \"hwcfg1=%08x\\n\", core_if->hwcfg1.d32);\n+\tDWC_DEBUGPL(DBG_CILV, \"hwcfg2=%08x\\n\", core_if->hwcfg2.d32);\n+\tDWC_DEBUGPL(DBG_CILV, \"hwcfg3=%08x\\n\", core_if->hwcfg3.d32);\n+\tDWC_DEBUGPL(DBG_CILV, \"hwcfg4=%08x\\n\", core_if->hwcfg4.d32);\n+\n+\tcore_if->hcfg.d32 =\n+\t    DWC_READ_REG32(&core_if->host_if->host_global_regs->hcfg);\n+\tcore_if->dcfg.d32 =\n+\t    DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg);\n+\n+\tDWC_DEBUGPL(DBG_CILV, \"hcfg=%08x\\n\", core_if->hcfg.d32);\n+\tDWC_DEBUGPL(DBG_CILV, \"dcfg=%08x\\n\", core_if->dcfg.d32);\n+\n+\tDWC_DEBUGPL(DBG_CILV, \"op_mode=%0x\\n\", core_if->hwcfg2.b.op_mode);\n+\tDWC_DEBUGPL(DBG_CILV, \"arch=%0x\\n\", core_if->hwcfg2.b.architecture);\n+\tDWC_DEBUGPL(DBG_CILV, \"num_dev_ep=%d\\n\", core_if->hwcfg2.b.num_dev_ep);\n+\tDWC_DEBUGPL(DBG_CILV, \"num_host_chan=%d\\n\",\n+\t\t    core_if->hwcfg2.b.num_host_chan);\n+\tDWC_DEBUGPL(DBG_CILV, \"nonperio_tx_q_depth=0x%0x\\n\",\n+\t\t    core_if->hwcfg2.b.nonperio_tx_q_depth);\n+\tDWC_DEBUGPL(DBG_CILV, \"host_perio_tx_q_depth=0x%0x\\n\",\n+\t\t    core_if->hwcfg2.b.host_perio_tx_q_depth);\n+\tDWC_DEBUGPL(DBG_CILV, \"dev_token_q_depth=0x%0x\\n\",\n+\t\t    core_if->hwcfg2.b.dev_token_q_depth);\n+\n+\tDWC_DEBUGPL(DBG_CILV, \"Total FIFO SZ=%d\\n\",\n+\t\t    core_if->hwcfg3.b.dfifo_depth);\n+\tDWC_DEBUGPL(DBG_CILV, \"xfer_size_cntr_width=%0x\\n\",\n+\t\t    core_if->hwcfg3.b.xfer_size_cntr_width);\n+\n+\t/*\n+\t * Set the SRP sucess bit for FS-I2c\n+\t */\n+\tcore_if->srp_success = 0;\n+\tcore_if->srp_timer_started = 0;\n+\n+\t/*\n+\t * Create new workqueue and init works\n+\t */\n+\tcore_if->wq_otg = DWC_WORKQ_ALLOC(\"dwc_otg\");\n+\tif (core_if->wq_otg == 0) {\n+\t\tDWC_WARN(\"DWC_WORKQ_ALLOC failed\\n\");\n+\t\tDWC_FREE(host_if);\n+\t\tDWC_FREE(dev_if);\n+\t\tDWC_FREE(core_if);\n+\t\treturn 0;\n+\t}\n+\n+\tcore_if->snpsid = DWC_READ_REG32(&core_if->core_global_regs->gsnpsid);\n+\n+\tDWC_PRINTF(\"Core Release: %x.%x%x%x\\n\",\n+\t\t   (core_if->snpsid >> 12 & 0xF),\n+\t\t   (core_if->snpsid >> 8 & 0xF),\n+\t\t   (core_if->snpsid >> 4 & 0xF), (core_if->snpsid & 0xF));\n+\n+\tcore_if->wkp_timer = DWC_TIMER_ALLOC(\"Wake Up Timer\",\n+\t\t\t\t\t     w_wakeup_detected, core_if);\n+\tif (core_if->wkp_timer == 0) {\n+\t\tDWC_WARN(\"DWC_TIMER_ALLOC failed\\n\");\n+\t\tDWC_FREE(host_if);\n+\t\tDWC_FREE(dev_if);\n+\t\tDWC_WORKQ_FREE(core_if->wq_otg);\n+\t\tDWC_FREE(core_if);\n+\t\treturn 0;\n+\t}\n+\n+\tif (dwc_otg_setup_params(core_if)) {\n+\t\tDWC_WARN(\"Error while setting core params\\n\");\n+\t}\n+\n+\tcore_if->hibernation_suspend = 0;\n+\n+\t/** ADP initialization */\n+\tdwc_otg_adp_init(core_if);\n+\n+\treturn core_if;\n+}\n+\n+/**\n+ * This function frees the structures allocated by dwc_otg_cil_init().\n+ *\n+ * @param core_if The core interface pointer returned from\n+ * \t\t  dwc_otg_cil_init().\n+ *\n+ */\n+void dwc_otg_cil_remove(dwc_otg_core_if_t * core_if)\n+{\n+\tdctl_data_t dctl = {.d32 = 0 };\n+\tDWC_DEBUGPL(DBG_CILV, \"%s(%p)\\n\", __func__, core_if);\n+\n+\t/* Disable all interrupts */\n+\tDWC_MODIFY_REG32(&core_if->core_global_regs->gahbcfg, 1, 0);\n+\tDWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, 0);\n+\n+\tdctl.b.sftdiscon = 1;\n+\tif (core_if->snpsid >= OTG_CORE_REV_3_00a) {\n+\t\tDWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0,\n+\t\t\t\t dctl.d32);\n+\t}\n+\n+\tif (core_if->wq_otg) {\n+\t\tDWC_WORKQ_WAIT_WORK_DONE(core_if->wq_otg, 500);\n+\t\tDWC_WORKQ_FREE(core_if->wq_otg);\n+\t}\n+\tif (core_if->dev_if) {\n+\t\tDWC_FREE(core_if->dev_if);\n+\t}\n+\tif (core_if->host_if) {\n+\t\tDWC_FREE(core_if->host_if);\n+\t}\n+\n+\t/** Remove ADP Stuff  */\n+\tdwc_otg_adp_remove(core_if);\n+\tif (core_if->core_params) {\n+\t\tDWC_FREE(core_if->core_params);\n+\t}\n+\tif (core_if->wkp_timer) {\n+\t\tDWC_TIMER_FREE(core_if->wkp_timer);\n+\t}\n+\tif (core_if->srp_timer) {\n+\t\tDWC_TIMER_FREE(core_if->srp_timer);\n+\t}\n+\tDWC_FREE(core_if);\n+}\n+\n+/**\n+ * This function enables the controller's Global Interrupt in the AHB Config\n+ * register.\n+ *\n+ * @param core_if Programming view of DWC_otg controller.\n+ */\n+void dwc_otg_enable_global_interrupts(dwc_otg_core_if_t * core_if)\n+{\n+\tgahbcfg_data_t ahbcfg = {.d32 = 0 };\n+\tahbcfg.b.glblintrmsk = 1;\t/* Enable interrupts */\n+\tDWC_MODIFY_REG32(&core_if->core_global_regs->gahbcfg, 0, ahbcfg.d32);\n+}\n+\n+/**\n+ * This function disables the controller's Global Interrupt in the AHB Config\n+ * register.\n+ *\n+ * @param core_if Programming view of DWC_otg controller.\n+ */\n+void dwc_otg_disable_global_interrupts(dwc_otg_core_if_t * core_if)\n+{\n+\tgahbcfg_data_t ahbcfg = {.d32 = 0 };\n+\tahbcfg.b.glblintrmsk = 1;\t/* Disable interrupts */\n+\tDWC_MODIFY_REG32(&core_if->core_global_regs->gahbcfg, ahbcfg.d32, 0);\n+}\n+\n+/**\n+ * This function initializes the commmon interrupts, used in both\n+ * device and host modes.\n+ *\n+ * @param core_if Programming view of the DWC_otg controller\n+ *\n+ */\n+static void dwc_otg_enable_common_interrupts(dwc_otg_core_if_t * core_if)\n+{\n+\tdwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;\n+\tgintmsk_data_t intr_mask = {.d32 = 0 };\n+\n+\t/* Clear any pending OTG Interrupts */\n+\tDWC_WRITE_REG32(&global_regs->gotgint, 0xFFFFFFFF);\n+\n+\t/* Clear any pending interrupts */\n+\tDWC_WRITE_REG32(&global_regs->gintsts, 0xFFFFFFFF);\n+\n+\t/*\n+\t * Enable the interrupts in the GINTMSK.\n+\t */\n+\tintr_mask.b.modemismatch = 1;\n+\tintr_mask.b.otgintr = 1;\n+\n+\tif (!core_if->dma_enable) {\n+\t\tintr_mask.b.rxstsqlvl = 1;\n+\t}\n+\n+\tintr_mask.b.conidstschng = 1;\n+\tintr_mask.b.wkupintr = 1;\n+\tintr_mask.b.disconnect = 0;\n+\tintr_mask.b.usbsuspend = 1;\n+\tintr_mask.b.sessreqintr = 1;\n+#ifdef CONFIG_USB_DWC_OTG_LPM\n+\tif (core_if->core_params->lpm_enable) {\n+\t\tintr_mask.b.lpmtranrcvd = 1;\n+\t}\n+#endif\n+\tDWC_WRITE_REG32(&global_regs->gintmsk, intr_mask.d32);\n+}\n+\n+/*\n+ * The restore operation is modified to support Synopsys Emulated Powerdown and\n+ * Hibernation. This function is for exiting from Device mode hibernation by\n+ * Host Initiated Resume/Reset and Device Initiated Remote-Wakeup.\n+ * @param core_if Programming view of DWC_otg controller.\n+ * @param rem_wakeup - indicates whether resume is initiated by Device or Host.\n+ * @param reset - indicates whether resume is initiated by Reset.\n+ */\n+int dwc_otg_device_hibernation_restore(dwc_otg_core_if_t * core_if,\n+\t\t\t\t       int rem_wakeup, int reset)\n+{\n+\tgpwrdn_data_t gpwrdn = {.d32 = 0 };\n+\tpcgcctl_data_t pcgcctl = {.d32 = 0 };\n+\tdctl_data_t dctl = {.d32 = 0 };\n+\n+\tint timeout = 2000;\n+\n+\tif (!core_if->hibernation_suspend) {\n+\t\tDWC_PRINTF(\"Already exited from Hibernation\\n\");\n+\t\treturn 1;\n+\t}\n+\n+\tDWC_DEBUGPL(DBG_PCD, \"%s called\\n\", __FUNCTION__);\n+\t/* Switch-on voltage to the core */\n+\tgpwrdn.b.pwrdnswtch = 1;\n+\tDWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);\n+\tdwc_udelay(10);\n+\n+\t/* Reset core */\n+\tgpwrdn.d32 = 0;\n+\tgpwrdn.b.pwrdnrstn = 1;\n+\tDWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);\n+\tdwc_udelay(10);\n+\n+\t/* Assert Restore signal */\n+\tgpwrdn.d32 = 0;\n+\tgpwrdn.b.restore = 1;\n+\tDWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);\n+\tdwc_udelay(10);\n+\n+\t/* Disable power clamps */\n+\tgpwrdn.d32 = 0;\n+\tgpwrdn.b.pwrdnclmp = 1;\n+\tDWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);\n+\n+\tif (rem_wakeup) {\n+\t\tdwc_udelay(70);\n+\t}\n+\n+\t/* Deassert Reset core */\n+\tgpwrdn.d32 = 0;\n+\tgpwrdn.b.pwrdnrstn = 1;\n+\tDWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);\n+\tdwc_udelay(10);\n+\n+\t/* Disable PMU interrupt */\n+\tgpwrdn.d32 = 0;\n+\tgpwrdn.b.pmuintsel = 1;\n+\tDWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);\n+\n+\t/* Mask interrupts from gpwrdn */\n+\tgpwrdn.d32 = 0;\n+\tgpwrdn.b.connect_det_msk = 1;\n+\tgpwrdn.b.srp_det_msk = 1;\n+\tgpwrdn.b.disconn_det_msk = 1;\n+\tgpwrdn.b.rst_det_msk = 1;\n+\tgpwrdn.b.lnstchng_msk = 1;\n+\tDWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);\n+\n+\t/* Indicates that we are going out from hibernation */\n+\tcore_if->hibernation_suspend = 0;\n+\n+\t/*\n+\t * Set Restore Essential Regs bit in PCGCCTL register, restore_mode = 1\n+\t * indicates restore from remote_wakeup\n+\t */\n+\trestore_essential_regs(core_if, rem_wakeup, 0);\n+\n+\t/*\n+\t * Wait a little for seeing new value of variable hibernation_suspend if\n+\t * Restore done interrupt received before polling\n+\t */\n+\tdwc_udelay(10);\n+\n+\tif (core_if->hibernation_suspend == 0) {\n+\t\t/*\n+\t\t * Wait For Restore_done Interrupt. This mechanism of polling the\n+\t\t * interrupt is introduced to avoid any possible race conditions\n+\t\t */\n+\t\tdo {\n+\t\t\tgintsts_data_t gintsts;\n+\t\t\tgintsts.d32 =\n+\t\t\t    DWC_READ_REG32(&core_if->core_global_regs->gintsts);\n+\t\t\tif (gintsts.b.restoredone) {\n+\t\t\t\tgintsts.d32 = 0;\n+\t\t\t\tgintsts.b.restoredone = 1;\n+\t\t\t\tDWC_WRITE_REG32(&core_if->core_global_regs->\n+\t\t\t\t\t\tgintsts, gintsts.d32);\n+\t\t\t\tDWC_PRINTF(\"Restore Done Interrupt seen\\n\");\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t\tdwc_udelay(10);\n+\t\t} while (--timeout);\n+\t\tif (!timeout) {\n+\t\t\tDWC_PRINTF(\"Restore Done interrupt wasn't generated here\\n\");\n+\t\t}\n+\t}\n+\t/* Clear all pending interupts */\n+\tDWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);\n+\n+\t/* De-assert Restore */\n+\tgpwrdn.d32 = 0;\n+\tgpwrdn.b.restore = 1;\n+\tDWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);\n+\tdwc_udelay(10);\n+\n+\tif (!rem_wakeup) {\n+\t\tpcgcctl.d32 = 0;\n+\t\tpcgcctl.b.rstpdwnmodule = 1;\n+\t\tDWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0);\n+\t}\n+\n+\t/* Restore GUSBCFG and DCFG */\n+\tDWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg,\n+\t\t\tcore_if->gr_backup->gusbcfg_local);\n+\tDWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg,\n+\t\t\tcore_if->dr_backup->dcfg);\n+\n+\t/* De-assert Wakeup Logic */\n+\tgpwrdn.d32 = 0;\n+\tgpwrdn.b.pmuactv = 1;\n+\tDWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);\n+\tdwc_udelay(10);\n+\n+\tif (!rem_wakeup) {\n+\t\t/* Set Device programming done bit */\n+\t\tdctl.b.pwronprgdone = 1;\n+\t\tDWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0, dctl.d32);\n+\t} else {\n+\t\t/* Start Remote Wakeup Signaling */\n+\t\tdctl.d32 = core_if->dr_backup->dctl;\n+\t\tdctl.b.rmtwkupsig = 1;\n+\t\tDWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32);\n+\t}\n+\n+\tdwc_mdelay(2);\n+\t/* Clear all pending interupts */\n+\tDWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);\n+\n+\t/* Restore global registers */\n+\tdwc_otg_restore_global_regs(core_if);\n+\t/* Restore device global registers */\n+\tdwc_otg_restore_dev_regs(core_if, rem_wakeup);\n+\n+\tif (rem_wakeup) {\n+\t\tdwc_mdelay(7);\n+\t\tdctl.d32 = 0;\n+\t\tdctl.b.rmtwkupsig = 1;\n+\t\tDWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32, 0);\n+\t}\n+\n+\tcore_if->hibernation_suspend = 0;\n+\t/* The core will be in ON STATE */\n+\tcore_if->lx_state = DWC_OTG_L0;\n+\tDWC_PRINTF(\"Hibernation recovery completes here\\n\");\n+\n+\treturn 1;\n+}\n+\n+/*\n+ * The restore operation is modified to support Synopsys Emulated Powerdown and\n+ * Hibernation. This function is for exiting from Host mode hibernation by\n+ * Host Initiated Resume/Reset and Device Initiated Remote-Wakeup.\n+ * @param core_if Programming view of DWC_otg controller.\n+ * @param rem_wakeup - indicates whether resume is initiated by Device or Host.\n+ * @param reset - indicates whether resume is initiated by Reset.\n+ */\n+int dwc_otg_host_hibernation_restore(dwc_otg_core_if_t * core_if,\n+\t\t\t\t     int rem_wakeup, int reset)\n+{\n+\tgpwrdn_data_t gpwrdn = {.d32 = 0 };\n+\thprt0_data_t hprt0 = {.d32 = 0 };\n+\n+\tint timeout = 2000;\n+\n+\tDWC_DEBUGPL(DBG_HCD, \"%s called\\n\", __FUNCTION__);\n+\t/* Switch-on voltage to the core */\n+\tgpwrdn.b.pwrdnswtch = 1;\n+\tDWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);\n+\tdwc_udelay(10);\n+\n+\t/* Reset core */\n+\tgpwrdn.d32 = 0;\n+\tgpwrdn.b.pwrdnrstn = 1;\n+\tDWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);\n+\tdwc_udelay(10);\n+\n+\t/* Assert Restore signal */\n+\tgpwrdn.d32 = 0;\n+\tgpwrdn.b.restore = 1;\n+\tDWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);\n+\tdwc_udelay(10);\n+\n+\t/* Disable power clamps */\n+\tgpwrdn.d32 = 0;\n+\tgpwrdn.b.pwrdnclmp = 1;\n+\tDWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);\n+\n+\tif (!rem_wakeup) {\n+\t\tdwc_udelay(50);\n+\t}\n+\n+\t/* Deassert Reset core */\n+\tgpwrdn.d32 = 0;\n+\tgpwrdn.b.pwrdnrstn = 1;\n+\tDWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);\n+\tdwc_udelay(10);\n+\n+\t/* Disable PMU interrupt */\n+\tgpwrdn.d32 = 0;\n+\tgpwrdn.b.pmuintsel = 1;\n+\tDWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);\n+\n+\tgpwrdn.d32 = 0;\n+\tgpwrdn.b.connect_det_msk = 1;\n+\tgpwrdn.b.srp_det_msk = 1;\n+\tgpwrdn.b.disconn_det_msk = 1;\n+\tgpwrdn.b.rst_det_msk = 1;\n+\tgpwrdn.b.lnstchng_msk = 1;\n+\tDWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);\n+\n+\t/* Indicates that we are going out from hibernation */\n+\tcore_if->hibernation_suspend = 0;\n+\n+\t/* Set Restore Essential Regs bit in PCGCCTL register */\n+\trestore_essential_regs(core_if, rem_wakeup, 1);\n+\n+\t/* Wait a little for seeing new value of variable hibernation_suspend if\n+\t * Restore done interrupt received before polling */\n+\tdwc_udelay(10);\n+\n+\tif (core_if->hibernation_suspend == 0) {\n+\t\t/* Wait For Restore_done Interrupt. This mechanism of polling the\n+\t\t * interrupt is introduced to avoid any possible race conditions\n+\t\t */\n+\t\tdo {\n+\t\t\tgintsts_data_t gintsts;\n+\t\t\tgintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts);\n+\t\t\tif (gintsts.b.restoredone) {\n+\t\t\t\tgintsts.d32 = 0;\n+\t\t\t\tgintsts.b.restoredone = 1;\n+\t\t\tDWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);\n+\t\t\t\tDWC_DEBUGPL(DBG_HCD,\"Restore Done Interrupt seen\\n\");\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t\tdwc_udelay(10);\n+\t\t} while (--timeout);\n+\t\tif (!timeout) {\n+\t\t\tDWC_WARN(\"Restore Done interrupt wasn't generated\\n\");\n+\t\t}\n+\t}\n+\n+\t/* Set the flag's value to 0 again after receiving restore done interrupt */\n+\tcore_if->hibernation_suspend = 0;\n+\n+\t/* This step is not described in functional spec but if not wait for this\n+\t * delay, mismatch interrupts occurred because just after restore core is\n+\t * in Device mode(gintsts.curmode == 0) */\n+\tdwc_mdelay(100);\n+\n+\t/* Clear all pending interrupts */\n+\tDWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);\n+\n+\t/* De-assert Restore */\n+\tgpwrdn.d32 = 0;\n+\tgpwrdn.b.restore = 1;\n+\tDWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);\n+\tdwc_udelay(10);\n+\n+\t/* Restore GUSBCFG and HCFG */\n+\tDWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg,\n+\t\t\tcore_if->gr_backup->gusbcfg_local);\n+\tDWC_WRITE_REG32(&core_if->host_if->host_global_regs->hcfg,\n+\t\t\tcore_if->hr_backup->hcfg_local);\n+\n+\t/* De-assert Wakeup Logic */\n+\tgpwrdn.d32 = 0;\n+\tgpwrdn.b.pmuactv = 1;\n+\tDWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);\n+\tdwc_udelay(10);\n+\n+\t/* Start the Resume operation by programming HPRT0 */\n+\thprt0.d32 = core_if->hr_backup->hprt0_local;\n+\thprt0.b.prtpwr = 1;\n+\thprt0.b.prtena = 0;\n+\thprt0.b.prtsusp = 0;\n+\tDWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);\n+\n+\tDWC_PRINTF(\"Resume Starts Now\\n\");\n+\tif (!reset) {\t\t// Indicates it is Resume Operation\n+\t\thprt0.d32 = core_if->hr_backup->hprt0_local;\n+\t\thprt0.b.prtres = 1;\n+\t\thprt0.b.prtpwr = 1;\n+\t\thprt0.b.prtena = 0;\n+\t\thprt0.b.prtsusp = 0;\n+\t\tDWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);\n+\n+\t\tif (!rem_wakeup)\n+\t\t\thprt0.b.prtres = 0;\n+\t\t/* Wait for Resume time and then program HPRT again */\n+\t\tdwc_mdelay(100);\n+\t\tDWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);\n+\n+\t} else {\t\t// Indicates it is Reset Operation\n+\t\thprt0.d32 = core_if->hr_backup->hprt0_local;\n+\t\thprt0.b.prtrst = 1;\n+\t\thprt0.b.prtpwr = 1;\n+\t\thprt0.b.prtena = 0;\n+\t\thprt0.b.prtsusp = 0;\n+\t\tDWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);\n+\t\t/* Wait for Reset time and then program HPRT again */\n+\t\tdwc_mdelay(60);\n+\t\thprt0.b.prtrst = 0;\n+\t\tDWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);\n+\t}\n+\t/* Clear all interrupt status */\n+\thprt0.d32 = dwc_otg_read_hprt0(core_if);\n+\thprt0.b.prtconndet = 1;\n+\thprt0.b.prtenchng = 1;\n+\tDWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);\n+\n+\t/* Clear all pending interupts */\n+\tDWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);\n+\n+\t/* Restore global registers */\n+\tdwc_otg_restore_global_regs(core_if);\n+\t/* Restore host global registers */\n+\tdwc_otg_restore_host_regs(core_if, reset);\n+\n+\t/* The core will be in ON STATE */\n+\tcore_if->lx_state = DWC_OTG_L0;\n+\tDWC_PRINTF(\"Hibernation recovery is complete here\\n\");\n+\treturn 0;\n+}\n+\n+/** Saves some register values into system memory. */\n+int dwc_otg_save_global_regs(dwc_otg_core_if_t * core_if)\n+{\n+\tstruct dwc_otg_global_regs_backup *gr;\n+\tint i;\n+\n+\tgr = core_if->gr_backup;\n+\tif (!gr) {\n+\t\tgr = DWC_ALLOC(sizeof(*gr));\n+\t\tif (!gr) {\n+\t\t\treturn -DWC_E_NO_MEMORY;\n+\t\t}\n+\t\tcore_if->gr_backup = gr;\n+\t}\n+\n+\tgr->gotgctl_local = DWC_READ_REG32(&core_if->core_global_regs->gotgctl);\n+\tgr->gintmsk_local = DWC_READ_REG32(&core_if->core_global_regs->gintmsk);\n+\tgr->gahbcfg_local = DWC_READ_REG32(&core_if->core_global_regs->gahbcfg);\n+\tgr->gusbcfg_local = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);\n+\tgr->grxfsiz_local = DWC_READ_REG32(&core_if->core_global_regs->grxfsiz);\n+\tgr->gnptxfsiz_local = DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz);\n+\tgr->hptxfsiz_local = DWC_READ_REG32(&core_if->core_global_regs->hptxfsiz);\n+#ifdef CONFIG_USB_DWC_OTG_LPM\n+\tgr->glpmcfg_local = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);\n+#endif\n+\tgr->gi2cctl_local = DWC_READ_REG32(&core_if->core_global_regs->gi2cctl);\n+\tgr->pcgcctl_local = DWC_READ_REG32(core_if->pcgcctl);\n+\tgr->gdfifocfg_local =\n+\t    DWC_READ_REG32(&core_if->core_global_regs->gdfifocfg);\n+\tfor (i = 0; i < MAX_EPS_CHANNELS; i++) {\n+\t\tgr->dtxfsiz_local[i] =\n+\t\t    DWC_READ_REG32(&(core_if->core_global_regs->dtxfsiz[i]));\n+\t}\n+\n+\tDWC_DEBUGPL(DBG_ANY, \"===========Backing Global registers==========\\n\");\n+\tDWC_DEBUGPL(DBG_ANY, \"Backed up gotgctl   = %08x\\n\", gr->gotgctl_local);\n+\tDWC_DEBUGPL(DBG_ANY, \"Backed up gintmsk   = %08x\\n\", gr->gintmsk_local);\n+\tDWC_DEBUGPL(DBG_ANY, \"Backed up gahbcfg   = %08x\\n\", gr->gahbcfg_local);\n+\tDWC_DEBUGPL(DBG_ANY, \"Backed up gusbcfg   = %08x\\n\", gr->gusbcfg_local);\n+\tDWC_DEBUGPL(DBG_ANY, \"Backed up grxfsiz   = %08x\\n\", gr->grxfsiz_local);\n+\tDWC_DEBUGPL(DBG_ANY, \"Backed up gnptxfsiz = %08x\\n\",\n+\t\t    gr->gnptxfsiz_local);\n+\tDWC_DEBUGPL(DBG_ANY, \"Backed up hptxfsiz  = %08x\\n\",\n+\t\t    gr->hptxfsiz_local);\n+#ifdef CONFIG_USB_DWC_OTG_LPM\n+\tDWC_DEBUGPL(DBG_ANY, \"Backed up glpmcfg   = %08x\\n\", gr->glpmcfg_local);\n+#endif\n+\tDWC_DEBUGPL(DBG_ANY, \"Backed up gi2cctl   = %08x\\n\", gr->gi2cctl_local);\n+\tDWC_DEBUGPL(DBG_ANY, \"Backed up pcgcctl   = %08x\\n\", gr->pcgcctl_local);\n+\tDWC_DEBUGPL(DBG_ANY,\"Backed up gdfifocfg   = %08x\\n\",gr->gdfifocfg_local);\n+\n+\treturn 0;\n+}\n+\n+/** Saves GINTMSK register before setting the msk bits. */\n+int dwc_otg_save_gintmsk_reg(dwc_otg_core_if_t * core_if)\n+{\n+\tstruct dwc_otg_global_regs_backup *gr;\n+\n+\tgr = core_if->gr_backup;\n+\tif (!gr) {\n+\t\tgr = DWC_ALLOC(sizeof(*gr));\n+\t\tif (!gr) {\n+\t\t\treturn -DWC_E_NO_MEMORY;\n+\t\t}\n+\t\tcore_if->gr_backup = gr;\n+\t}\n+\n+\tgr->gintmsk_local = DWC_READ_REG32(&core_if->core_global_regs->gintmsk);\n+\n+\tDWC_DEBUGPL(DBG_ANY,\"=============Backing GINTMSK registers============\\n\");\n+\tDWC_DEBUGPL(DBG_ANY, \"Backed up gintmsk   = %08x\\n\", gr->gintmsk_local);\n+\n+\treturn 0;\n+}\n+\n+int dwc_otg_save_dev_regs(dwc_otg_core_if_t * core_if)\n+{\n+\tstruct dwc_otg_dev_regs_backup *dr;\n+\tint i;\n+\n+\tdr = core_if->dr_backup;\n+\tif (!dr) {\n+\t\tdr = DWC_ALLOC(sizeof(*dr));\n+\t\tif (!dr) {\n+\t\t\treturn -DWC_E_NO_MEMORY;\n+\t\t}\n+\t\tcore_if->dr_backup = dr;\n+\t}\n+\n+\tdr->dcfg = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg);\n+\tdr->dctl = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl);\n+\tdr->daintmsk =\n+\t    DWC_READ_REG32(&core_if->dev_if->dev_global_regs->daintmsk);\n+\tdr->diepmsk =\n+\t    DWC_READ_REG32(&core_if->dev_if->dev_global_regs->diepmsk);\n+\tdr->doepmsk =\n+\t    DWC_READ_REG32(&core_if->dev_if->dev_global_regs->doepmsk);\n+\n+\tfor (i = 0; i < core_if->dev_if->num_in_eps; ++i) {\n+\t\tdr->diepctl[i] =\n+\t\t    DWC_READ_REG32(&core_if->dev_if->in_ep_regs[i]->diepctl);\n+\t\tdr->dieptsiz[i] =\n+\t\t    DWC_READ_REG32(&core_if->dev_if->in_ep_regs[i]->dieptsiz);\n+\t\tdr->diepdma[i] =\n+\t\t    DWC_READ_REG32(&core_if->dev_if->in_ep_regs[i]->diepdma);\n+\t}\n+\n+\tDWC_DEBUGPL(DBG_ANY,\n+\t\t    \"=============Backing Host registers==============\\n\");\n+\tDWC_DEBUGPL(DBG_ANY, \"Backed up dcfg            = %08x\\n\", dr->dcfg);\n+\tDWC_DEBUGPL(DBG_ANY, \"Backed up dctl        = %08x\\n\", dr->dctl);\n+\tDWC_DEBUGPL(DBG_ANY, \"Backed up daintmsk            = %08x\\n\",\n+\t\t    dr->daintmsk);\n+\tDWC_DEBUGPL(DBG_ANY, \"Backed up diepmsk        = %08x\\n\", dr->diepmsk);\n+\tDWC_DEBUGPL(DBG_ANY, \"Backed up doepmsk        = %08x\\n\", dr->doepmsk);\n+\tfor (i = 0; i < core_if->dev_if->num_in_eps; ++i) {\n+\t\tDWC_DEBUGPL(DBG_ANY, \"Backed up diepctl[%d]        = %08x\\n\", i,\n+\t\t\t    dr->diepctl[i]);\n+\t\tDWC_DEBUGPL(DBG_ANY, \"Backed up dieptsiz[%d]        = %08x\\n\",\n+\t\t\t    i, dr->dieptsiz[i]);\n+\t\tDWC_DEBUGPL(DBG_ANY, \"Backed up diepdma[%d]        = %08x\\n\", i,\n+\t\t\t    dr->diepdma[i]);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+int dwc_otg_save_host_regs(dwc_otg_core_if_t * core_if)\n+{\n+\tstruct dwc_otg_host_regs_backup *hr;\n+\tint i;\n+\n+\thr = core_if->hr_backup;\n+\tif (!hr) {\n+\t\thr = DWC_ALLOC(sizeof(*hr));\n+\t\tif (!hr) {\n+\t\t\treturn -DWC_E_NO_MEMORY;\n+\t\t}\n+\t\tcore_if->hr_backup = hr;\n+\t}\n+\n+\thr->hcfg_local =\n+\t    DWC_READ_REG32(&core_if->host_if->host_global_regs->hcfg);\n+\thr->haintmsk_local =\n+\t    DWC_READ_REG32(&core_if->host_if->host_global_regs->haintmsk);\n+\tfor (i = 0; i < dwc_otg_get_param_host_channels(core_if); ++i) {\n+\t\thr->hcintmsk_local[i] =\n+\t\t    DWC_READ_REG32(&core_if->host_if->hc_regs[i]->hcintmsk);\n+\t}\n+\thr->hprt0_local = DWC_READ_REG32(core_if->host_if->hprt0);\n+\thr->hfir_local =\n+\t    DWC_READ_REG32(&core_if->host_if->host_global_regs->hfir);\n+\n+\tDWC_DEBUGPL(DBG_ANY,\n+\t\t    \"=============Backing Host registers===============\\n\");\n+\tDWC_DEBUGPL(DBG_ANY, \"Backed up hcfg\t\t= %08x\\n\",\n+\t\t    hr->hcfg_local);\n+\tDWC_DEBUGPL(DBG_ANY, \"Backed up haintmsk = %08x\\n\", hr->haintmsk_local);\n+\tfor (i = 0; i < dwc_otg_get_param_host_channels(core_if); ++i) {\n+\t\tDWC_DEBUGPL(DBG_ANY, \"Backed up hcintmsk[%02d]=%08x\\n\", i,\n+\t\t\t    hr->hcintmsk_local[i]);\n+\t}\n+\tDWC_DEBUGPL(DBG_ANY, \"Backed up hprt0           = %08x\\n\",\n+\t\t    hr->hprt0_local);\n+\tDWC_DEBUGPL(DBG_ANY, \"Backed up hfir           = %08x\\n\",\n+\t\t    hr->hfir_local);\n+\n+\treturn 0;\n+}\n+\n+int dwc_otg_restore_global_regs(dwc_otg_core_if_t *core_if)\n+{\n+\tstruct dwc_otg_global_regs_backup *gr;\n+\tint i;\n+\n+\tgr = core_if->gr_backup;\n+\tif (!gr) {\n+\t\treturn -DWC_E_INVALID;\n+\t}\n+\n+\tDWC_WRITE_REG32(&core_if->core_global_regs->gotgctl, gr->gotgctl_local);\n+\tDWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, gr->gintmsk_local);\n+\tDWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, gr->gusbcfg_local);\n+\tDWC_WRITE_REG32(&core_if->core_global_regs->gahbcfg, gr->gahbcfg_local);\n+\tDWC_WRITE_REG32(&core_if->core_global_regs->grxfsiz, gr->grxfsiz_local);\n+\tDWC_WRITE_REG32(&core_if->core_global_regs->gnptxfsiz,\n+\t\t\tgr->gnptxfsiz_local);\n+\tDWC_WRITE_REG32(&core_if->core_global_regs->hptxfsiz,\n+\t\t\tgr->hptxfsiz_local);\n+\tDWC_WRITE_REG32(&core_if->core_global_regs->gdfifocfg,\n+\t\t\tgr->gdfifocfg_local);\n+\tfor (i = 0; i < MAX_EPS_CHANNELS; i++) {\n+\t\tDWC_WRITE_REG32(&core_if->core_global_regs->dtxfsiz[i],\n+\t\t\t\tgr->dtxfsiz_local[i]);\n+\t}\n+\n+\tDWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);\n+\tDWC_WRITE_REG32(core_if->host_if->hprt0, 0x0000100A);\n+\tDWC_WRITE_REG32(&core_if->core_global_regs->gahbcfg,\n+\t\t\t(gr->gahbcfg_local));\n+\treturn 0;\n+}\n+\n+int dwc_otg_restore_dev_regs(dwc_otg_core_if_t * core_if, int rem_wakeup)\n+{\n+\tstruct dwc_otg_dev_regs_backup *dr;\n+\tint i;\n+\n+\tdr = core_if->dr_backup;\n+\n+\tif (!dr) {\n+\t\treturn -DWC_E_INVALID;\n+\t}\n+\n+\tif (!rem_wakeup) {\n+\t\tDWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl,\n+\t\t\t\tdr->dctl);\n+\t}\n+\n+\tDWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->daintmsk, dr->daintmsk);\n+\tDWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->diepmsk, dr->diepmsk);\n+\tDWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->doepmsk, dr->doepmsk);\n+\n+\tfor (i = 0; i < core_if->dev_if->num_in_eps; ++i) {\n+\t\tDWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[i]->dieptsiz, dr->dieptsiz[i]);\n+\t\tDWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[i]->diepdma, dr->diepdma[i]);\n+\t\tDWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[i]->diepctl, dr->diepctl[i]);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+int dwc_otg_restore_host_regs(dwc_otg_core_if_t * core_if, int reset)\n+{\n+\tstruct dwc_otg_host_regs_backup *hr;\n+\tint i;\n+\thr = core_if->hr_backup;\n+\n+\tif (!hr) {\n+\t\treturn -DWC_E_INVALID;\n+\t}\n+\n+\tDWC_WRITE_REG32(&core_if->host_if->host_global_regs->hcfg, hr->hcfg_local);\n+\t//if (!reset)\n+\t//{\n+\t//      DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hfir, hr->hfir_local);\n+\t//}\n+\n+\tDWC_WRITE_REG32(&core_if->host_if->host_global_regs->haintmsk,\n+\t\t\thr->haintmsk_local);\n+\tfor (i = 0; i < dwc_otg_get_param_host_channels(core_if); ++i) {\n+\t\tDWC_WRITE_REG32(&core_if->host_if->hc_regs[i]->hcintmsk,\n+\t\t\t\thr->hcintmsk_local[i]);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+int restore_lpm_i2c_regs(dwc_otg_core_if_t * core_if)\n+{\n+\tstruct dwc_otg_global_regs_backup *gr;\n+\n+\tgr = core_if->gr_backup;\n+\n+\t/* Restore values for LPM and I2C */\n+#ifdef CONFIG_USB_DWC_OTG_LPM\n+\tDWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg, gr->glpmcfg_local);\n+#endif\n+\tDWC_WRITE_REG32(&core_if->core_global_regs->gi2cctl, gr->gi2cctl_local);\n+\n+\treturn 0;\n+}\n+\n+int restore_essential_regs(dwc_otg_core_if_t * core_if, int rmode, int is_host)\n+{\n+\tstruct dwc_otg_global_regs_backup *gr;\n+\tpcgcctl_data_t pcgcctl = {.d32 = 0 };\n+\tgahbcfg_data_t gahbcfg = {.d32 = 0 };\n+\tgusbcfg_data_t gusbcfg = {.d32 = 0 };\n+\tgintmsk_data_t gintmsk = {.d32 = 0 };\n+\n+\t/* Restore LPM and I2C registers */\n+\trestore_lpm_i2c_regs(core_if);\n+\n+\t/* Set PCGCCTL to 0 */\n+\tDWC_WRITE_REG32(core_if->pcgcctl, 0x00000000);\n+\n+\tgr = core_if->gr_backup;\n+\t/* Load restore values for [31:14] bits */\n+\tDWC_WRITE_REG32(core_if->pcgcctl,\n+\t\t\t((gr->pcgcctl_local & 0xffffc000) | 0x00020000));\n+\n+\t/* Umnask global Interrupt in GAHBCFG and restore it */\n+\tgahbcfg.d32 = gr->gahbcfg_local;\n+\tgahbcfg.b.glblintrmsk = 1;\n+\tDWC_WRITE_REG32(&core_if->core_global_regs->gahbcfg, gahbcfg.d32);\n+\n+\t/* Clear all pending interupts */\n+\tDWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);\n+\n+\t/* Unmask restore done interrupt */\n+\tgintmsk.b.restoredone = 1;\n+\tDWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, gintmsk.d32);\n+\n+\t/* Restore GUSBCFG and HCFG/DCFG */\n+\tgusbcfg.d32 = core_if->gr_backup->gusbcfg_local;\n+\tDWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, gusbcfg.d32);\n+\n+\tif (is_host) {\n+\t\thcfg_data_t hcfg = {.d32 = 0 };\n+\t\thcfg.d32 = core_if->hr_backup->hcfg_local;\n+\t\tDWC_WRITE_REG32(&core_if->host_if->host_global_regs->hcfg,\n+\t\t\t\thcfg.d32);\n+\n+\t\t/* Load restore values for [31:14] bits */\n+\t\tpcgcctl.d32 = gr->pcgcctl_local & 0xffffc000;\n+\t\tpcgcctl.d32 = gr->pcgcctl_local | 0x00020000;\n+\n+\t\tif (rmode)\n+\t\t\tpcgcctl.b.restoremode = 1;\n+\t\tDWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32);\n+\t\tdwc_udelay(10);\n+\n+\t\t/* Load restore values for [31:14] bits and set EssRegRestored bit */\n+\t\tpcgcctl.d32 = gr->pcgcctl_local | 0xffffc000;\n+\t\tpcgcctl.d32 = gr->pcgcctl_local & 0xffffc000;\n+\t\tpcgcctl.b.ess_reg_restored = 1;\n+\t\tif (rmode)\n+\t\t\tpcgcctl.b.restoremode = 1;\n+\t\tDWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32);\n+\t} else {\n+\t\tdcfg_data_t dcfg = {.d32 = 0 };\n+\t\tdcfg.d32 = core_if->dr_backup->dcfg;\n+\t\tDWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg, dcfg.d32);\n+\n+\t\t/* Load restore values for [31:14] bits */\n+\t\tpcgcctl.d32 = gr->pcgcctl_local & 0xffffc000;\n+\t\tpcgcctl.d32 = gr->pcgcctl_local | 0x00020000;\n+\t\tif (!rmode) {\n+\t\t\tpcgcctl.d32 |= 0x208;\n+\t\t}\n+\t\tDWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32);\n+\t\tdwc_udelay(10);\n+\n+\t\t/* Load restore values for [31:14] bits */\n+\t\tpcgcctl.d32 = gr->pcgcctl_local & 0xffffc000;\n+\t\tpcgcctl.d32 = gr->pcgcctl_local | 0x00020000;\n+\t\tpcgcctl.b.ess_reg_restored = 1;\n+\t\tif (!rmode)\n+\t\t\tpcgcctl.d32 |= 0x208;\n+\t\tDWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+/**\n+ * Initializes the FSLSPClkSel field of the HCFG register depending on the PHY\n+ * type.\n+ */\n+static void init_fslspclksel(dwc_otg_core_if_t * core_if)\n+{\n+\tuint32_t val;\n+\thcfg_data_t hcfg;\n+\n+\tif (((core_if->hwcfg2.b.hs_phy_type == 2) &&\n+\t     (core_if->hwcfg2.b.fs_phy_type == 1) &&\n+\t     (core_if->core_params->ulpi_fs_ls)) ||\n+\t    (core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS)) {\n+\t\t/* Full speed PHY */\n+\t\tval = DWC_HCFG_48_MHZ;\n+\t} else {\n+\t\t/* High speed PHY running at full speed or high speed */\n+\t\tval = DWC_HCFG_30_60_MHZ;\n+\t}\n+\n+\tDWC_DEBUGPL(DBG_CIL, \"Initializing HCFG.FSLSPClkSel to 0x%1x\\n\", val);\n+\thcfg.d32 = DWC_READ_REG32(&core_if->host_if->host_global_regs->hcfg);\n+\thcfg.b.fslspclksel = val;\n+\tDWC_WRITE_REG32(&core_if->host_if->host_global_regs->hcfg, hcfg.d32);\n+}\n+\n+/**\n+ * Initializes the DevSpd field of the DCFG register depending on the PHY type\n+ * and the enumeration speed of the device.\n+ */\n+static void init_devspd(dwc_otg_core_if_t * core_if)\n+{\n+\tuint32_t val;\n+\tdcfg_data_t dcfg;\n+\n+\tif (((core_if->hwcfg2.b.hs_phy_type == 2) &&\n+\t     (core_if->hwcfg2.b.fs_phy_type == 1) &&\n+\t     (core_if->core_params->ulpi_fs_ls)) ||\n+\t    (core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS)) {\n+\t\t/* Full speed PHY */\n+\t\tval = 0x3;\n+\t} else if (core_if->core_params->speed == DWC_SPEED_PARAM_FULL) {\n+\t\t/* High speed PHY running at full speed */\n+\t\tval = 0x1;\n+\t} else {\n+\t\t/* High speed PHY running at high speed */\n+\t\tval = 0x0;\n+\t}\n+\n+\tDWC_DEBUGPL(DBG_CIL, \"Initializing DCFG.DevSpd to 0x%1x\\n\", val);\n+\n+\tdcfg.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg);\n+\tdcfg.b.devspd = val;\n+\tDWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg, dcfg.d32);\n+}\n+\n+/**\n+ * This function calculates the number of IN EPS\n+ * using GHWCFG1 and GHWCFG2 registers values\n+ *\n+ * @param core_if Programming view of the DWC_otg controller\n+ */\n+static uint32_t calc_num_in_eps(dwc_otg_core_if_t * core_if)\n+{\n+\tuint32_t num_in_eps = 0;\n+\tuint32_t num_eps = core_if->hwcfg2.b.num_dev_ep;\n+\tuint32_t hwcfg1 = core_if->hwcfg1.d32 >> 3;\n+\tuint32_t num_tx_fifos = core_if->hwcfg4.b.num_in_eps;\n+\tint i;\n+\n+\tfor (i = 0; i < num_eps; ++i) {\n+\t\tif (!(hwcfg1 & 0x1))\n+\t\t\tnum_in_eps++;\n+\n+\t\thwcfg1 >>= 2;\n+\t}\n+\n+\tif (core_if->hwcfg4.b.ded_fifo_en) {\n+\t\tnum_in_eps =\n+\t\t    (num_in_eps > num_tx_fifos) ? num_tx_fifos : num_in_eps;\n+\t}\n+\n+\treturn num_in_eps;\n+}\n+\n+/**\n+ * This function calculates the number of OUT EPS\n+ * using GHWCFG1 and GHWCFG2 registers values\n+ *\n+ * @param core_if Programming view of the DWC_otg controller\n+ */\n+static uint32_t calc_num_out_eps(dwc_otg_core_if_t * core_if)\n+{\n+\tuint32_t num_out_eps = 0;\n+\tuint32_t num_eps = core_if->hwcfg2.b.num_dev_ep;\n+\tuint32_t hwcfg1 = core_if->hwcfg1.d32 >> 2;\n+\tint i;\n+\n+\tfor (i = 0; i < num_eps; ++i) {\n+\t\tif (!(hwcfg1 & 0x1))\n+\t\t\tnum_out_eps++;\n+\n+\t\thwcfg1 >>= 2;\n+\t}\n+\treturn num_out_eps;\n+}\n+\n+/**\n+ * This function initializes the DWC_otg controller registers and\n+ * prepares the core for device mode or host mode operation.\n+ *\n+ * @param core_if Programming view of the DWC_otg controller\n+ *\n+ */\n+void dwc_otg_core_init(dwc_otg_core_if_t * core_if)\n+{\n+\tint i = 0;\n+\tdwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;\n+\tdwc_otg_dev_if_t *dev_if = core_if->dev_if;\n+\tgahbcfg_data_t ahbcfg = {.d32 = 0 };\n+\tgusbcfg_data_t usbcfg = {.d32 = 0 };\n+\tgi2cctl_data_t i2cctl = {.d32 = 0 };\n+\n+\tDWC_DEBUGPL(DBG_CILV, \"dwc_otg_core_init(%p) regs at %p\\n\",\n+                    core_if, global_regs);\n+\n+\t/* Common Initialization */\n+\tusbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);\n+\n+\t/* Program the ULPI External VBUS bit if needed */\n+\tusbcfg.b.ulpi_ext_vbus_drv =\n+\t    (core_if->core_params->phy_ulpi_ext_vbus ==\n+\t     DWC_PHY_ULPI_EXTERNAL_VBUS) ? 1 : 0;\n+\n+\t/* Set external TS Dline pulsing */\n+\tusbcfg.b.term_sel_dl_pulse =\n+\t    (core_if->core_params->ts_dline == 1) ? 1 : 0;\n+\tDWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);\n+\n+\t/* Reset the Controller */\n+\tdwc_otg_core_reset(core_if);\n+\n+\tcore_if->adp_enable = core_if->core_params->adp_supp_enable;\n+\tcore_if->power_down = core_if->core_params->power_down;\n+\tcore_if->otg_sts = 0;\n+\n+\t/* Initialize parameters from Hardware configuration registers. */\n+\tdev_if->num_in_eps = calc_num_in_eps(core_if);\n+\tdev_if->num_out_eps = calc_num_out_eps(core_if);\n+\n+\tDWC_DEBUGPL(DBG_CIL, \"num_dev_perio_in_ep=%d\\n\",\n+\t\t    core_if->hwcfg4.b.num_dev_perio_in_ep);\n+\n+\tfor (i = 0; i < core_if->hwcfg4.b.num_dev_perio_in_ep; i++) {\n+\t\tdev_if->perio_tx_fifo_size[i] =\n+\t\t    DWC_READ_REG32(&global_regs->dtxfsiz[i]) >> 16;\n+\t\tDWC_DEBUGPL(DBG_CIL, \"Periodic Tx FIFO SZ #%d=0x%0x\\n\",\n+\t\t\t    i, dev_if->perio_tx_fifo_size[i]);\n+\t}\n+\n+\tfor (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {\n+\t\tdev_if->tx_fifo_size[i] =\n+\t\t    DWC_READ_REG32(&global_regs->dtxfsiz[i]) >> 16;\n+\t\tDWC_DEBUGPL(DBG_CIL, \"Tx FIFO SZ #%d=0x%0x\\n\",\n+\t\t\t    i, dev_if->tx_fifo_size[i]);\n+\t}\n+\n+\tcore_if->total_fifo_size = core_if->hwcfg3.b.dfifo_depth;\n+\tcore_if->rx_fifo_size = DWC_READ_REG32(&global_regs->grxfsiz);\n+\tcore_if->nperio_tx_fifo_size =\n+\t    DWC_READ_REG32(&global_regs->gnptxfsiz) >> 16;\n+\n+\tDWC_DEBUGPL(DBG_CIL, \"Total FIFO SZ=%d\\n\", core_if->total_fifo_size);\n+\tDWC_DEBUGPL(DBG_CIL, \"Rx FIFO SZ=%d\\n\", core_if->rx_fifo_size);\n+\tDWC_DEBUGPL(DBG_CIL, \"NP Tx FIFO SZ=%d\\n\",\n+\t\t    core_if->nperio_tx_fifo_size);\n+\n+\t/* This programming sequence needs to happen in FS mode before any other\n+\t * programming occurs */\n+\tif ((core_if->core_params->speed == DWC_SPEED_PARAM_FULL) &&\n+\t    (core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS)) {\n+\t\t/* If FS mode with FS PHY */\n+\n+\t\t/* core_init() is now called on every switch so only call the\n+\t\t * following for the first time through. */\n+\t\tif (!core_if->phy_init_done) {\n+\t\t\tcore_if->phy_init_done = 1;\n+\t\t\tDWC_DEBUGPL(DBG_CIL, \"FS_PHY detected\\n\");\n+\t\t\tusbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);\n+\t\t\tusbcfg.b.physel = 1;\n+\t\t\tDWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);\n+\n+\t\t\t/* Reset after a PHY select */\n+\t\t\tdwc_otg_core_reset(core_if);\n+\t\t}\n+\n+\t\t/* Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS.      Also\n+\t\t * do this on HNP Dev/Host mode switches (done in dev_init and\n+\t\t * host_init). */\n+\t\tif (dwc_otg_is_host_mode(core_if)) {\n+\t\t\tinit_fslspclksel(core_if);\n+\t\t} else {\n+\t\t\tinit_devspd(core_if);\n+\t\t}\n+\n+\t\tif (core_if->core_params->i2c_enable) {\n+\t\t\tDWC_DEBUGPL(DBG_CIL, \"FS_PHY Enabling I2c\\n\");\n+\t\t\t/* Program GUSBCFG.OtgUtmifsSel to I2C */\n+\t\t\tusbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);\n+\t\t\tusbcfg.b.otgutmifssel = 1;\n+\t\t\tDWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);\n+\n+\t\t\t/* Program GI2CCTL.I2CEn */\n+\t\t\ti2cctl.d32 = DWC_READ_REG32(&global_regs->gi2cctl);\n+\t\t\ti2cctl.b.i2cdevaddr = 1;\n+\t\t\ti2cctl.b.i2cen = 0;\n+\t\t\tDWC_WRITE_REG32(&global_regs->gi2cctl, i2cctl.d32);\n+\t\t\ti2cctl.b.i2cen = 1;\n+\t\t\tDWC_WRITE_REG32(&global_regs->gi2cctl, i2cctl.d32);\n+\t\t}\n+\n+\t} /* endif speed == DWC_SPEED_PARAM_FULL */\n+\telse {\n+\t\t/* High speed PHY. */\n+\t\tif (!core_if->phy_init_done) {\n+\t\t\tcore_if->phy_init_done = 1;\n+\t\t\t/* HS PHY parameters.  These parameters are preserved\n+\t\t\t * during soft reset so only program the first time.  Do\n+\t\t\t * a soft reset immediately after setting phyif.  */\n+\n+\t\t\tif (core_if->core_params->phy_type == 2) {\n+\t\t\t\t/* ULPI interface */\n+\t\t\t\tusbcfg.b.ulpi_utmi_sel = 1;\n+\t\t\t\tusbcfg.b.phyif = 0;\n+\t\t\t\tusbcfg.b.ddrsel =\n+\t\t\t\t    core_if->core_params->phy_ulpi_ddr;\n+\t\t\t} else if (core_if->core_params->phy_type == 1) {\n+\t\t\t\t/* UTMI+ interface */\n+\t\t\t\tusbcfg.b.ulpi_utmi_sel = 0;\n+\t\t\t\tif (core_if->core_params->phy_utmi_width == 16) {\n+\t\t\t\t\tusbcfg.b.phyif = 1;\n+\n+\t\t\t\t} else {\n+\t\t\t\t\tusbcfg.b.phyif = 0;\n+\t\t\t\t}\n+\t\t\t} else {\n+\t\t\t\tDWC_ERROR(\"FS PHY TYPE\\n\");\n+\t\t\t}\n+\t\t\tDWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);\n+\t\t\t/* Reset after setting the PHY parameters */\n+\t\t\tdwc_otg_core_reset(core_if);\n+\t\t}\n+\t}\n+\n+\tif ((core_if->hwcfg2.b.hs_phy_type == 2) &&\n+\t    (core_if->hwcfg2.b.fs_phy_type == 1) &&\n+\t    (core_if->core_params->ulpi_fs_ls)) {\n+\t\tDWC_DEBUGPL(DBG_CIL, \"Setting ULPI FSLS\\n\");\n+\t\tusbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);\n+\t\tusbcfg.b.ulpi_fsls = 1;\n+\t\tusbcfg.b.ulpi_clk_sus_m = 1;\n+\t\tDWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);\n+\t} else {\n+\t\tusbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);\n+\t\tusbcfg.b.ulpi_fsls = 0;\n+\t\tusbcfg.b.ulpi_clk_sus_m = 0;\n+\t\tDWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);\n+\t}\n+\n+\t/* Program the GAHBCFG Register. */\n+\tswitch (core_if->hwcfg2.b.architecture) {\n+\n+\tcase DWC_SLAVE_ONLY_ARCH:\n+\t\tDWC_DEBUGPL(DBG_CIL, \"Slave Only Mode\\n\");\n+\t\tahbcfg.b.nptxfemplvl_txfemplvl =\n+\t\t    DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY;\n+\t\tahbcfg.b.ptxfemplvl = DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY;\n+\t\tcore_if->dma_enable = 0;\n+\t\tcore_if->dma_desc_enable = 0;\n+\t\tbreak;\n+\n+\tcase DWC_EXT_DMA_ARCH:\n+\t\tDWC_DEBUGPL(DBG_CIL, \"External DMA Mode\\n\");\n+\t\t{\n+\t\t\tuint8_t brst_sz = core_if->core_params->dma_burst_size;\n+\t\t\tahbcfg.b.hburstlen = 0;\n+\t\t\twhile (brst_sz > 1) {\n+\t\t\t\tahbcfg.b.hburstlen++;\n+\t\t\t\tbrst_sz >>= 1;\n+\t\t\t}\n+\t\t}\n+\t\tcore_if->dma_enable = (core_if->core_params->dma_enable != 0);\n+\t\tcore_if->dma_desc_enable =\n+\t\t    (core_if->core_params->dma_desc_enable != 0);\n+\t\tbreak;\n+\n+\tcase DWC_INT_DMA_ARCH:\n+\t\tDWC_DEBUGPL(DBG_CIL, \"Internal DMA Mode\\n\");\n+\t\t/* Old value was DWC_GAHBCFG_INT_DMA_BURST_INCR - done for\n+\t\t  Host mode ISOC in issue fix - vahrama */\n+\t\t/* Broadcom had altered to (1<<3)|(0<<0) - WRESP=1, max 4 beats */\n+\t\tahbcfg.b.hburstlen = (1<<3)|(0<<0);//DWC_GAHBCFG_INT_DMA_BURST_INCR4;\n+\t\tcore_if->dma_enable = (core_if->core_params->dma_enable != 0);\n+\t\tcore_if->dma_desc_enable =\n+\t\t    (core_if->core_params->dma_desc_enable != 0);\n+\t\tbreak;\n+\n+\t}\n+\tif (core_if->dma_enable) {\n+\t\tif (core_if->dma_desc_enable) {\n+\t\t\tDWC_PRINTF(\"Using Descriptor DMA mode\\n\");\n+\t\t} else {\n+\t\t\tDWC_PRINTF(\"Using Buffer DMA mode\\n\");\n+\n+\t\t}\n+\t} else {\n+\t\tDWC_PRINTF(\"Using Slave mode\\n\");\n+\t\tcore_if->dma_desc_enable = 0;\n+\t}\n+\n+\tif (core_if->core_params->ahb_single) {\n+\t\tahbcfg.b.ahbsingle = 1;\n+\t}\n+\n+\tahbcfg.b.dmaenable = core_if->dma_enable;\n+\tDWC_WRITE_REG32(&global_regs->gahbcfg, ahbcfg.d32);\n+\n+\tcore_if->en_multiple_tx_fifo = core_if->hwcfg4.b.ded_fifo_en;\n+\n+\tcore_if->pti_enh_enable = core_if->core_params->pti_enable != 0;\n+\tcore_if->multiproc_int_enable = core_if->core_params->mpi_enable;\n+\tDWC_PRINTF(\"Periodic Transfer Interrupt Enhancement - %s\\n\",\n+\t\t   ((core_if->pti_enh_enable) ? \"enabled\" : \"disabled\"));\n+\tDWC_PRINTF(\"Multiprocessor Interrupt Enhancement - %s\\n\",\n+\t\t   ((core_if->multiproc_int_enable) ? \"enabled\" : \"disabled\"));\n+\n+\t/*\n+\t * Program the GUSBCFG register.\n+\t */\n+\tusbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);\n+\n+\tswitch (core_if->hwcfg2.b.op_mode) {\n+\tcase DWC_MODE_HNP_SRP_CAPABLE:\n+\t\tusbcfg.b.hnpcap = (core_if->core_params->otg_cap ==\n+\t\t\t\t   DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE);\n+\t\tusbcfg.b.srpcap = (core_if->core_params->otg_cap !=\n+\t\t\t\t   DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);\n+\t\tbreak;\n+\n+\tcase DWC_MODE_SRP_ONLY_CAPABLE:\n+\t\tusbcfg.b.hnpcap = 0;\n+\t\tusbcfg.b.srpcap = (core_if->core_params->otg_cap !=\n+\t\t\t\t   DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);\n+\t\tbreak;\n+\n+\tcase DWC_MODE_NO_HNP_SRP_CAPABLE:\n+\t\tusbcfg.b.hnpcap = 0;\n+\t\tusbcfg.b.srpcap = 0;\n+\t\tbreak;\n+\n+\tcase DWC_MODE_SRP_CAPABLE_DEVICE:\n+\t\tusbcfg.b.hnpcap = 0;\n+\t\tusbcfg.b.srpcap = (core_if->core_params->otg_cap !=\n+\t\t\t\t   DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);\n+\t\tbreak;\n+\n+\tcase DWC_MODE_NO_SRP_CAPABLE_DEVICE:\n+\t\tusbcfg.b.hnpcap = 0;\n+\t\tusbcfg.b.srpcap = 0;\n+\t\tbreak;\n+\n+\tcase DWC_MODE_SRP_CAPABLE_HOST:\n+\t\tusbcfg.b.hnpcap = 0;\n+\t\tusbcfg.b.srpcap = (core_if->core_params->otg_cap !=\n+\t\t\t\t   DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);\n+\t\tbreak;\n+\n+\tcase DWC_MODE_NO_SRP_CAPABLE_HOST:\n+\t\tusbcfg.b.hnpcap = 0;\n+\t\tusbcfg.b.srpcap = 0;\n+\t\tbreak;\n+\t}\n+\n+\tDWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);\n+\n+#ifdef CONFIG_USB_DWC_OTG_LPM\n+\tif (core_if->core_params->lpm_enable) {\n+\t\tglpmcfg_data_t lpmcfg = {.d32 = 0 };\n+\n+\t\t/* To enable LPM support set lpm_cap_en bit */\n+\t\tlpmcfg.b.lpm_cap_en = 1;\n+\n+\t\t/* Make AppL1Res ACK */\n+\t\tlpmcfg.b.appl_resp = 1;\n+\n+\t\t/* Retry 3 times */\n+\t\tlpmcfg.b.retry_count = 3;\n+\n+\t\tDWC_MODIFY_REG32(&core_if->core_global_regs->glpmcfg,\n+\t\t\t\t 0, lpmcfg.d32);\n+\n+\t}\n+#endif\n+\tif (core_if->core_params->ic_usb_cap) {\n+\t\tgusbcfg_data_t gusbcfg = {.d32 = 0 };\n+\t\tgusbcfg.b.ic_usb_cap = 1;\n+\t\tDWC_MODIFY_REG32(&core_if->core_global_regs->gusbcfg,\n+\t\t\t\t 0, gusbcfg.d32);\n+\t}\n+\t{\n+\t\tgotgctl_data_t gotgctl = {.d32 = 0 };\n+\t\tgotgctl.b.otgver = core_if->core_params->otg_ver;\n+\t\tDWC_MODIFY_REG32(&core_if->core_global_regs->gotgctl, 0,\n+\t\t\t\t gotgctl.d32);\n+\t\t/* Set OTG version supported */\n+\t\tcore_if->otg_ver = core_if->core_params->otg_ver;\n+\t\tDWC_PRINTF(\"OTG VER PARAM: %d, OTG VER FLAG: %d\\n\",\n+\t\t\t   core_if->core_params->otg_ver, core_if->otg_ver);\n+\t}\n+\n+\n+\t/* Enable common interrupts */\n+\tdwc_otg_enable_common_interrupts(core_if);\n+\n+\t/* Do device or host intialization based on mode during PCD\n+\t * and HCD initialization  */\n+\tif (dwc_otg_is_host_mode(core_if)) {\n+\t\tDWC_DEBUGPL(DBG_ANY, \"Host Mode\\n\");\n+\t\tcore_if->op_state = A_HOST;\n+\t} else {\n+\t\tDWC_DEBUGPL(DBG_ANY, \"Device Mode\\n\");\n+\t\tcore_if->op_state = B_PERIPHERAL;\n+#ifdef DWC_DEVICE_ONLY\n+\t\tdwc_otg_core_dev_init(core_if);\n+#endif\n+\t}\n+}\n+\n+/**\n+ * This function enables the Device mode interrupts.\n+ *\n+ * @param core_if Programming view of DWC_otg controller\n+ */\n+void dwc_otg_enable_device_interrupts(dwc_otg_core_if_t * core_if)\n+{\n+\tgintmsk_data_t intr_mask = {.d32 = 0 };\n+\tdwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;\n+\n+\tDWC_DEBUGPL(DBG_CIL, \"%s()\\n\", __func__);\n+\n+\t/* Disable all interrupts. */\n+\tDWC_WRITE_REG32(&global_regs->gintmsk, 0);\n+\n+\t/* Clear any pending interrupts */\n+\tDWC_WRITE_REG32(&global_regs->gintsts, 0xFFFFFFFF);\n+\n+\t/* Enable the common interrupts */\n+\tdwc_otg_enable_common_interrupts(core_if);\n+\n+\t/* Enable interrupts */\n+\tintr_mask.b.usbreset = 1;\n+\tintr_mask.b.enumdone = 1;\n+\t/* Disable Disconnect interrupt in Device mode */\n+\tintr_mask.b.disconnect = 0;\n+\n+\tif (!core_if->multiproc_int_enable) {\n+\t\tintr_mask.b.inepintr = 1;\n+\t\tintr_mask.b.outepintr = 1;\n+\t}\n+\n+\tintr_mask.b.erlysuspend = 1;\n+\n+\tif (core_if->en_multiple_tx_fifo == 0) {\n+\t\tintr_mask.b.epmismatch = 1;\n+\t}\n+\n+\t//intr_mask.b.incomplisoout = 1;\n+\tintr_mask.b.incomplisoin = 1;\n+\n+/* Enable the ignore frame number for ISOC xfers - MAS */\n+/* Disable to support high bandwith ISOC transfers - manukz */\n+#if 0\n+#ifdef DWC_UTE_PER_IO\n+\tif (core_if->dma_enable) {\n+\t\tif (core_if->dma_desc_enable) {\n+\t\t\tdctl_data_t dctl1 = {.d32 = 0 };\n+\t\t\tdctl1.b.ifrmnum = 1;\n+\t\t\tDWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->\n+\t\t\t\t\t dctl, 0, dctl1.d32);\n+\t\t\tDWC_DEBUG(\"----Enabled Ignore frame number (0x%08x)\",\n+\t\t\t\t  DWC_READ_REG32(&core_if->dev_if->\n+\t\t\t\t\t\t dev_global_regs->dctl));\n+\t\t}\n+\t}\n+#endif\n+#endif\n+#ifdef DWC_EN_ISOC\n+\tif (core_if->dma_enable) {\n+\t\tif (core_if->dma_desc_enable == 0) {\n+\t\t\tif (core_if->pti_enh_enable) {\n+\t\t\t\tdctl_data_t dctl = {.d32 = 0 };\n+\t\t\t\tdctl.b.ifrmnum = 1;\n+\t\t\t\tDWC_MODIFY_REG32(&core_if->\n+\t\t\t\t\t\t dev_if->dev_global_regs->dctl,\n+\t\t\t\t\t\t 0, dctl.d32);\n+\t\t\t} else {\n+\t\t\t\tintr_mask.b.incomplisoin = 1;\n+\t\t\t\tintr_mask.b.incomplisoout = 1;\n+\t\t\t}\n+\t\t}\n+\t} else {\n+\t\tintr_mask.b.incomplisoin = 1;\n+\t\tintr_mask.b.incomplisoout = 1;\n+\t}\n+#endif /* DWC_EN_ISOC */\n+\n+\t/** @todo NGS: Should this be a module parameter? */\n+#ifdef USE_PERIODIC_EP\n+\tintr_mask.b.isooutdrop = 1;\n+\tintr_mask.b.eopframe = 1;\n+\tintr_mask.b.incomplisoin = 1;\n+\tintr_mask.b.incomplisoout = 1;\n+#endif\n+\n+\tDWC_MODIFY_REG32(&global_regs->gintmsk, intr_mask.d32, intr_mask.d32);\n+\n+\tDWC_DEBUGPL(DBG_CIL, \"%s() gintmsk=%0x\\n\", __func__,\n+\t\t    DWC_READ_REG32(&global_regs->gintmsk));\n+}\n+\n+/**\n+ * This function initializes the DWC_otg controller registers for\n+ * device mode.\n+ *\n+ * @param core_if Programming view of DWC_otg controller\n+ *\n+ */\n+void dwc_otg_core_dev_init(dwc_otg_core_if_t * core_if)\n+{\n+\tint i;\n+\tdwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;\n+\tdwc_otg_dev_if_t *dev_if = core_if->dev_if;\n+\tdwc_otg_core_params_t *params = core_if->core_params;\n+\tdcfg_data_t dcfg = {.d32 = 0 };\n+\tdepctl_data_t diepctl = {.d32 = 0 };\n+\tgrstctl_t resetctl = {.d32 = 0 };\n+\tuint32_t rx_fifo_size;\n+\tfifosize_data_t nptxfifosize;\n+\tfifosize_data_t txfifosize;\n+\tdthrctl_data_t dthrctl;\n+\tfifosize_data_t ptxfifosize;\n+\tuint16_t rxfsiz, nptxfsiz;\n+\tgdfifocfg_data_t gdfifocfg = {.d32 = 0 };\n+\thwcfg3_data_t hwcfg3 = {.d32 = 0 };\n+\n+\t/* Restart the Phy Clock */\n+\tDWC_WRITE_REG32(core_if->pcgcctl, 0);\n+\n+\t/* Device configuration register */\n+\tinit_devspd(core_if);\n+\tdcfg.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dcfg);\n+\tdcfg.b.descdma = (core_if->dma_desc_enable) ? 1 : 0;\n+\tdcfg.b.perfrint = DWC_DCFG_FRAME_INTERVAL_80;\n+\t/* Enable Device OUT NAK in case of DDMA mode*/\n+\tif (core_if->core_params->dev_out_nak) {\n+\t\tdcfg.b.endevoutnak = 1;\n+\t}\n+\n+\tif (core_if->core_params->cont_on_bna) {\n+\t\tdctl_data_t dctl = {.d32 = 0 };\n+\t\tdctl.b.encontonbna = 1;\n+\t\tDWC_MODIFY_REG32(&dev_if->dev_global_regs->dctl, 0, dctl.d32);\n+\t}\n+\n+\n+\tDWC_WRITE_REG32(&dev_if->dev_global_regs->dcfg, dcfg.d32);\n+\n+\t/* Configure data FIFO sizes */\n+\tif (core_if->hwcfg2.b.dynamic_fifo && params->enable_dynamic_fifo) {\n+\t\tDWC_DEBUGPL(DBG_CIL, \"Total FIFO Size=%d\\n\",\n+\t\t\t    core_if->total_fifo_size);\n+\t\tDWC_DEBUGPL(DBG_CIL, \"Rx FIFO Size=%d\\n\",\n+\t\t\t    params->dev_rx_fifo_size);\n+\t\tDWC_DEBUGPL(DBG_CIL, \"NP Tx FIFO Size=%d\\n\",\n+\t\t\t    params->dev_nperio_tx_fifo_size);\n+\n+\t\t/* Rx FIFO */\n+\t\tDWC_DEBUGPL(DBG_CIL, \"initial grxfsiz=%08x\\n\",\n+\t\t\t    DWC_READ_REG32(&global_regs->grxfsiz));\n+\n+#ifdef DWC_UTE_CFI\n+\t\tcore_if->pwron_rxfsiz = DWC_READ_REG32(&global_regs->grxfsiz);\n+\t\tcore_if->init_rxfsiz = params->dev_rx_fifo_size;\n+#endif\n+\t\trx_fifo_size = params->dev_rx_fifo_size;\n+\t\tDWC_WRITE_REG32(&global_regs->grxfsiz, rx_fifo_size);\n+\n+\t\tDWC_DEBUGPL(DBG_CIL, \"new grxfsiz=%08x\\n\",\n+\t\t\t    DWC_READ_REG32(&global_regs->grxfsiz));\n+\n+\t\t/** Set Periodic Tx FIFO Mask all bits 0 */\n+\t\tcore_if->p_tx_msk = 0;\n+\n+\t\t/** Set Tx FIFO Mask all bits 0 */\n+\t\tcore_if->tx_msk = 0;\n+\n+\t\tif (core_if->en_multiple_tx_fifo == 0) {\n+\t\t\t/* Non-periodic Tx FIFO */\n+\t\t\tDWC_DEBUGPL(DBG_CIL, \"initial gnptxfsiz=%08x\\n\",\n+\t\t\t\t    DWC_READ_REG32(&global_regs->gnptxfsiz));\n+\n+\t\t\tnptxfifosize.b.depth = params->dev_nperio_tx_fifo_size;\n+\t\t\tnptxfifosize.b.startaddr = params->dev_rx_fifo_size;\n+\n+\t\t\tDWC_WRITE_REG32(&global_regs->gnptxfsiz,\n+\t\t\t\t\tnptxfifosize.d32);\n+\n+\t\t\tDWC_DEBUGPL(DBG_CIL, \"new gnptxfsiz=%08x\\n\",\n+\t\t\t\t    DWC_READ_REG32(&global_regs->gnptxfsiz));\n+\n+\t\t\t/**@todo NGS: Fix Periodic FIFO Sizing! */\n+\t\t\t/*\n+\t\t\t * Periodic Tx FIFOs These FIFOs are numbered from 1 to 15.\n+\t\t\t * Indexes of the FIFO size module parameters in the\n+\t\t\t * dev_perio_tx_fifo_size array and the FIFO size registers in\n+\t\t\t * the dptxfsiz array run from 0 to 14.\n+\t\t\t */\n+\t\t\t/** @todo Finish debug of this */\n+\t\t\tptxfifosize.b.startaddr =\n+\t\t\t    nptxfifosize.b.startaddr + nptxfifosize.b.depth;\n+\t\t\tfor (i = 0; i < core_if->hwcfg4.b.num_dev_perio_in_ep; i++) {\n+\t\t\t\tptxfifosize.b.depth =\n+\t\t\t\t    params->dev_perio_tx_fifo_size[i];\n+\t\t\t\tDWC_DEBUGPL(DBG_CIL,\n+\t\t\t\t\t    \"initial dtxfsiz[%d]=%08x\\n\", i,\n+\t\t\t\t\t    DWC_READ_REG32(&global_regs->dtxfsiz\n+\t\t\t\t\t\t\t   [i]));\n+\t\t\t\tDWC_WRITE_REG32(&global_regs->dtxfsiz[i],\n+\t\t\t\t\t\tptxfifosize.d32);\n+\t\t\t\tDWC_DEBUGPL(DBG_CIL, \"new dtxfsiz[%d]=%08x\\n\",\n+\t\t\t\t\t    i,\n+\t\t\t\t\t    DWC_READ_REG32(&global_regs->dtxfsiz\n+\t\t\t\t\t\t\t   [i]));\n+\t\t\t\tptxfifosize.b.startaddr += ptxfifosize.b.depth;\n+\t\t\t}\n+\t\t} else {\n+\t\t\t/*\n+\t\t\t * Tx FIFOs These FIFOs are numbered from 1 to 15.\n+\t\t\t * Indexes of the FIFO size module parameters in the\n+\t\t\t * dev_tx_fifo_size array and the FIFO size registers in\n+\t\t\t * the dtxfsiz array run from 0 to 14.\n+\t\t\t */\n+\n+\t\t\t/* Non-periodic Tx FIFO */\n+\t\t\tDWC_DEBUGPL(DBG_CIL, \"initial gnptxfsiz=%08x\\n\",\n+\t\t\t\t    DWC_READ_REG32(&global_regs->gnptxfsiz));\n+\n+#ifdef DWC_UTE_CFI\n+\t\t\tcore_if->pwron_gnptxfsiz =\n+\t\t\t    (DWC_READ_REG32(&global_regs->gnptxfsiz) >> 16);\n+\t\t\tcore_if->init_gnptxfsiz =\n+\t\t\t    params->dev_nperio_tx_fifo_size;\n+#endif\n+\t\t\tnptxfifosize.b.depth = params->dev_nperio_tx_fifo_size;\n+\t\t\tnptxfifosize.b.startaddr = params->dev_rx_fifo_size;\n+\n+\t\t\tDWC_WRITE_REG32(&global_regs->gnptxfsiz,\n+\t\t\t\t\tnptxfifosize.d32);\n+\n+\t\t\tDWC_DEBUGPL(DBG_CIL, \"new gnptxfsiz=%08x\\n\",\n+\t\t\t\t    DWC_READ_REG32(&global_regs->gnptxfsiz));\n+\n+\t\t\ttxfifosize.b.startaddr =\n+\t\t\t    nptxfifosize.b.startaddr + nptxfifosize.b.depth;\n+\n+\t\t\tfor (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {\n+\n+\t\t\t\ttxfifosize.b.depth =\n+\t\t\t\t    params->dev_tx_fifo_size[i];\n+\n+\t\t\t\tDWC_DEBUGPL(DBG_CIL,\n+\t\t\t\t\t    \"initial dtxfsiz[%d]=%08x\\n\",\n+\t\t\t\t\t    i,\n+\t\t\t\t\t    DWC_READ_REG32(&global_regs->dtxfsiz\n+\t\t\t\t\t\t\t   [i]));\n+\n+#ifdef DWC_UTE_CFI\n+\t\t\t\tcore_if->pwron_txfsiz[i] =\n+\t\t\t\t    (DWC_READ_REG32\n+\t\t\t\t     (&global_regs->dtxfsiz[i]) >> 16);\n+\t\t\t\tcore_if->init_txfsiz[i] =\n+\t\t\t\t    params->dev_tx_fifo_size[i];\n+#endif\n+\t\t\t\tDWC_WRITE_REG32(&global_regs->dtxfsiz[i],\n+\t\t\t\t\t\ttxfifosize.d32);\n+\n+\t\t\t\tDWC_DEBUGPL(DBG_CIL,\n+\t\t\t\t\t    \"new dtxfsiz[%d]=%08x\\n\",\n+\t\t\t\t\t    i,\n+\t\t\t\t\t    DWC_READ_REG32(&global_regs->dtxfsiz\n+\t\t\t\t\t\t\t   [i]));\n+\n+\t\t\t\ttxfifosize.b.startaddr += txfifosize.b.depth;\n+\t\t\t}\n+\t\t\tif (core_if->snpsid <= OTG_CORE_REV_2_94a) {\n+\t\t\t\t/* Calculating DFIFOCFG for Device mode to include RxFIFO and NPTXFIFO */\n+\t\t\t\tgdfifocfg.d32 = DWC_READ_REG32(&global_regs->gdfifocfg);\n+\t\t\t\thwcfg3.d32 = DWC_READ_REG32(&global_regs->ghwcfg3);\n+\t\t\t\tgdfifocfg.b.gdfifocfg = (DWC_READ_REG32(&global_regs->ghwcfg3) >> 16);\n+\t\t\t\tDWC_WRITE_REG32(&global_regs->gdfifocfg, gdfifocfg.d32);\n+\t\t\t\trxfsiz = (DWC_READ_REG32(&global_regs->grxfsiz) & 0x0000ffff);\n+\t\t\t\tnptxfsiz = (DWC_READ_REG32(&global_regs->gnptxfsiz) >> 16);\n+\t\t\t\tgdfifocfg.b.epinfobase = rxfsiz + nptxfsiz;\n+\t\t\t\tDWC_WRITE_REG32(&global_regs->gdfifocfg, gdfifocfg.d32);\n+\t\t\t}\n+\t\t}\n+\n+\t\t/* Flush the FIFOs */\n+\t\tdwc_otg_flush_tx_fifo(core_if, 0x10);\t/* all Tx FIFOs */\n+\t\tdwc_otg_flush_rx_fifo(core_if);\n+\n+\t\t/* Flush the Learning Queue. */\n+\t\tresetctl.b.intknqflsh = 1;\n+\t\tDWC_WRITE_REG32(&core_if->core_global_regs->grstctl, resetctl.d32);\n+\n+\t\tif (!core_if->core_params->en_multiple_tx_fifo && core_if->dma_enable) {\n+\t\t\tcore_if->start_predict = 0;\n+\t\t\tfor (i = 0; i<= core_if->dev_if->num_in_eps; ++i) {\n+\t\t\t\tcore_if->nextep_seq[i] = 0xff;\t// 0xff - EP not active\n+\t\t\t}\n+\t\t\tcore_if->nextep_seq[0] = 0;\n+\t\t\tcore_if->first_in_nextep_seq = 0;\n+\t\t\tdiepctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[0]->diepctl);\n+\t\t\tdiepctl.b.nextep = 0;\n+\t\t\tDWC_WRITE_REG32(&dev_if->in_ep_regs[0]->diepctl, diepctl.d32);\n+\n+\t\t\t/* Update IN Endpoint Mismatch Count by active IN NP EP count + 1 */\n+\t\t\tdcfg.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dcfg);\n+\t\t\tdcfg.b.epmscnt = 2;\n+\t\t\tDWC_WRITE_REG32(&dev_if->dev_global_regs->dcfg, dcfg.d32);\n+\n+\t\t\tDWC_DEBUGPL(DBG_CILV,\"%s first_in_nextep_seq= %2d; nextep_seq[]:\\n\",\n+\t\t\t\t__func__, core_if->first_in_nextep_seq);\n+\t\t\tfor (i=0; i <= core_if->dev_if->num_in_eps; i++) {\n+\t\t\t\tDWC_DEBUGPL(DBG_CILV, \"%2d \", core_if->nextep_seq[i]);\n+\t\t\t}\n+\t\t\tDWC_DEBUGPL(DBG_CILV,\"\\n\");\n+\t\t}\n+\n+\t\t/* Clear all pending Device Interrupts */\n+\t\t/** @todo - if the condition needed to be checked\n+\t\t *  or in any case all pending interrutps should be cleared?\n+\t     */\n+\t\tif (core_if->multiproc_int_enable) {\n+\t\t\tfor (i = 0; i < core_if->dev_if->num_in_eps; ++i) {\n+\t\t\t\tDWC_WRITE_REG32(&dev_if->\n+\t\t\t\t\t\tdev_global_regs->diepeachintmsk[i], 0);\n+\t\t\t}\n+\t\t}\n+\n+\t\tfor (i = 0; i < core_if->dev_if->num_out_eps; ++i) {\n+\t\t\tDWC_WRITE_REG32(&dev_if->\n+\t\t\t\t\tdev_global_regs->doepeachintmsk[i], 0);\n+\t\t}\n+\n+\t\tDWC_WRITE_REG32(&dev_if->dev_global_regs->deachint, 0xFFFFFFFF);\n+\t\tDWC_WRITE_REG32(&dev_if->dev_global_regs->deachintmsk, 0);\n+\t} else {\n+\t\tDWC_WRITE_REG32(&dev_if->dev_global_regs->diepmsk, 0);\n+\t\tDWC_WRITE_REG32(&dev_if->dev_global_regs->doepmsk, 0);\n+\t\tDWC_WRITE_REG32(&dev_if->dev_global_regs->daint, 0xFFFFFFFF);\n+\t\tDWC_WRITE_REG32(&dev_if->dev_global_regs->daintmsk, 0);\n+\t}\n+\n+\tfor (i = 0; i <= dev_if->num_in_eps; i++) {\n+\t\tdepctl_data_t depctl;\n+\t\tdepctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl);\n+\t\tif (depctl.b.epena) {\n+\t\t\tdepctl.d32 = 0;\n+\t\t\tdepctl.b.epdis = 1;\n+\t\t\tdepctl.b.snak = 1;\n+\t\t} else {\n+\t\t\tdepctl.d32 = 0;\n+\t\t}\n+\n+\t\tDWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepctl, depctl.d32);\n+\n+\t\tDWC_WRITE_REG32(&dev_if->in_ep_regs[i]->dieptsiz, 0);\n+\t\tDWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepdma, 0);\n+\t\tDWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepint, 0xFF);\n+\t}\n+\n+\tfor (i = 0; i <= dev_if->num_out_eps; i++) {\n+\t\tdepctl_data_t depctl;\n+\t\tdepctl.d32 = DWC_READ_REG32(&dev_if->out_ep_regs[i]->doepctl);\n+\t\tif (depctl.b.epena) {\n+\t\t\tdctl_data_t dctl = {.d32 = 0 };\n+\t\t\tgintmsk_data_t gintsts = {.d32 = 0 };\n+\t\t\tdoepint_data_t doepint = {.d32 = 0 };\n+\t\t\tdctl.b.sgoutnak = 1;\n+\t\t\tDWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0, dctl.d32);\n+\t\t\tdo {\n+\t\t\t\tdwc_udelay(10);\n+\t\t\t\tgintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts);\n+\t\t\t} while (!gintsts.b.goutnakeff);\n+\t\t\tgintsts.d32 = 0;\n+\t\t\tgintsts.b.goutnakeff = 1;\n+\t\t\tDWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);\n+\n+\t\t\tdepctl.d32 = 0;\n+\t\t\tdepctl.b.epdis = 1;\n+\t\t\tdepctl.b.snak = 1;\n+\t\t\tDWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[i]->doepctl, depctl.d32);\n+\t\t\tdo {\n+\t\t\t\tdwc_udelay(10);\n+\t\t\t\tdoepint.d32 = DWC_READ_REG32(&core_if->dev_if->\n+\t\t\t\t\tout_ep_regs[i]->doepint);\n+\t\t\t} while (!doepint.b.epdisabled);\n+\n+\t\t\tdoepint.b.epdisabled = 1;\n+\t\t\tDWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[i]->doepint, doepint.d32);\n+\n+\t\t\tdctl.d32 = 0;\n+\t\t\tdctl.b.cgoutnak = 1;\n+\t\t\tDWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0, dctl.d32);\n+\t\t} else {\n+\t\t\tdepctl.d32 = 0;\n+\t\t}\n+\n+\t\tDWC_WRITE_REG32(&dev_if->out_ep_regs[i]->doepctl, depctl.d32);\n+\n+\t\tDWC_WRITE_REG32(&dev_if->out_ep_regs[i]->doeptsiz, 0);\n+\t\tDWC_WRITE_REG32(&dev_if->out_ep_regs[i]->doepdma, 0);\n+\t\tDWC_WRITE_REG32(&dev_if->out_ep_regs[i]->doepint, 0xFF);\n+\t}\n+\n+\tif (core_if->en_multiple_tx_fifo && core_if->dma_enable) {\n+\t\tdev_if->non_iso_tx_thr_en = params->thr_ctl & 0x1;\n+\t\tdev_if->iso_tx_thr_en = (params->thr_ctl >> 1) & 0x1;\n+\t\tdev_if->rx_thr_en = (params->thr_ctl >> 2) & 0x1;\n+\n+\t\tdev_if->rx_thr_length = params->rx_thr_length;\n+\t\tdev_if->tx_thr_length = params->tx_thr_length;\n+\n+\t\tdev_if->setup_desc_index = 0;\n+\n+\t\tdthrctl.d32 = 0;\n+\t\tdthrctl.b.non_iso_thr_en = dev_if->non_iso_tx_thr_en;\n+\t\tdthrctl.b.iso_thr_en = dev_if->iso_tx_thr_en;\n+\t\tdthrctl.b.tx_thr_len = dev_if->tx_thr_length;\n+\t\tdthrctl.b.rx_thr_en = dev_if->rx_thr_en;\n+\t\tdthrctl.b.rx_thr_len = dev_if->rx_thr_length;\n+\t\tdthrctl.b.ahb_thr_ratio = params->ahb_thr_ratio;\n+\n+\t\tDWC_WRITE_REG32(&dev_if->dev_global_regs->dtknqr3_dthrctl,\n+\t\t\t\tdthrctl.d32);\n+\n+\t\tDWC_DEBUGPL(DBG_CIL,\n+\t\t\t    \"Non ISO Tx Thr - %d\\nISO Tx Thr - %d\\nRx Thr - %d\\nTx Thr Len - %d\\nRx Thr Len - %d\\n\",\n+\t\t\t    dthrctl.b.non_iso_thr_en, dthrctl.b.iso_thr_en,\n+\t\t\t    dthrctl.b.rx_thr_en, dthrctl.b.tx_thr_len,\n+\t\t\t    dthrctl.b.rx_thr_len);\n+\n+\t}\n+\n+\tdwc_otg_enable_device_interrupts(core_if);\n+\n+\t{\n+\t\tdiepmsk_data_t msk = {.d32 = 0 };\n+\t\tmsk.b.txfifoundrn = 1;\n+\t\tif (core_if->multiproc_int_enable) {\n+\t\t\tDWC_MODIFY_REG32(&dev_if->dev_global_regs->\n+\t\t\t\t\t diepeachintmsk[0], msk.d32, msk.d32);\n+\t\t} else {\n+\t\t\tDWC_MODIFY_REG32(&dev_if->dev_global_regs->diepmsk,\n+\t\t\t\t\t msk.d32, msk.d32);\n+\t\t}\n+\t}\n+\n+\tif (core_if->multiproc_int_enable) {\n+\t\t/* Set NAK on Babble */\n+\t\tdctl_data_t dctl = {.d32 = 0 };\n+\t\tdctl.b.nakonbble = 1;\n+\t\tDWC_MODIFY_REG32(&dev_if->dev_global_regs->dctl, 0, dctl.d32);\n+\t}\n+\n+\tif (core_if->snpsid >= OTG_CORE_REV_2_94a) {\n+\t\tdctl_data_t dctl = {.d32 = 0 };\n+\t\tdctl.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dctl);\n+\t\tdctl.b.sftdiscon = 0;\n+\t\tDWC_WRITE_REG32(&dev_if->dev_global_regs->dctl, dctl.d32);\n+\t}\n+}\n+\n+/**\n+ * This function enables the Host mode interrupts.\n+ *\n+ * @param core_if Programming view of DWC_otg controller\n+ */\n+void dwc_otg_enable_host_interrupts(dwc_otg_core_if_t * core_if)\n+{\n+\tdwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;\n+\tgintmsk_data_t intr_mask = {.d32 = 0 };\n+\n+\tDWC_DEBUGPL(DBG_CIL, \"%s(%p)\\n\", __func__, core_if);\n+\n+\t/* Disable all interrupts. */\n+\tDWC_WRITE_REG32(&global_regs->gintmsk, 0);\n+\n+\t/* Clear any pending interrupts. */\n+\tDWC_WRITE_REG32(&global_regs->gintsts, 0xFFFFFFFF);\n+\n+\t/* Enable the common interrupts */\n+\tdwc_otg_enable_common_interrupts(core_if);\n+\n+\t/*\n+\t * Enable host mode interrupts without disturbing common\n+\t * interrupts.\n+\t */\n+\n+\tintr_mask.b.disconnect = 1;\n+\tintr_mask.b.portintr = 1;\n+\tintr_mask.b.hcintr = 1;\n+\n+\tDWC_MODIFY_REG32(&global_regs->gintmsk, intr_mask.d32, intr_mask.d32);\n+}\n+\n+/**\n+ * This function disables the Host Mode interrupts.\n+ *\n+ * @param core_if Programming view of DWC_otg controller\n+ */\n+void dwc_otg_disable_host_interrupts(dwc_otg_core_if_t * core_if)\n+{\n+\tdwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;\n+\tgintmsk_data_t intr_mask = {.d32 = 0 };\n+\n+\tDWC_DEBUGPL(DBG_CILV, \"%s()\\n\", __func__);\n+\n+\t/*\n+\t * Disable host mode interrupts without disturbing common\n+\t * interrupts.\n+\t */\n+\tintr_mask.b.sofintr = 1;\n+\tintr_mask.b.portintr = 1;\n+\tintr_mask.b.hcintr = 1;\n+\tintr_mask.b.ptxfempty = 1;\n+\tintr_mask.b.nptxfempty = 1;\n+\n+\tDWC_MODIFY_REG32(&global_regs->gintmsk, intr_mask.d32, 0);\n+}\n+\n+/**\n+ * This function initializes the DWC_otg controller registers for\n+ * host mode.\n+ *\n+ * This function flushes the Tx and Rx FIFOs and it flushes any entries in the\n+ * request queues. Host channels are reset to ensure that they are ready for\n+ * performing transfers.\n+ *\n+ * @param core_if Programming view of DWC_otg controller\n+ *\n+ */\n+void dwc_otg_core_host_init(dwc_otg_core_if_t * core_if)\n+{\n+\tdwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;\n+\tdwc_otg_host_if_t *host_if = core_if->host_if;\n+\tdwc_otg_core_params_t *params = core_if->core_params;\n+\thprt0_data_t hprt0 = {.d32 = 0 };\n+\tfifosize_data_t nptxfifosize;\n+\tfifosize_data_t ptxfifosize;\n+\tuint16_t rxfsiz, nptxfsiz, hptxfsiz;\n+\tgdfifocfg_data_t gdfifocfg = {.d32 = 0 };\n+\tint i;\n+\thcchar_data_t hcchar;\n+\thcfg_data_t hcfg;\n+\thfir_data_t hfir;\n+\tdwc_otg_hc_regs_t *hc_regs;\n+\tint num_channels;\n+\tgotgctl_data_t gotgctl = {.d32 = 0 };\n+\n+\tDWC_DEBUGPL(DBG_CILV, \"%s(%p)\\n\", __func__, core_if);\n+\n+\t/* Restart the Phy Clock */\n+\tDWC_WRITE_REG32(core_if->pcgcctl, 0);\n+\n+\t/* Initialize Host Configuration Register */\n+\tinit_fslspclksel(core_if);\n+\tif (core_if->core_params->speed == DWC_SPEED_PARAM_FULL) {\n+\t\thcfg.d32 = DWC_READ_REG32(&host_if->host_global_regs->hcfg);\n+\t\thcfg.b.fslssupp = 1;\n+\t\tDWC_WRITE_REG32(&host_if->host_global_regs->hcfg, hcfg.d32);\n+\n+\t}\n+\n+\t/* This bit allows dynamic reloading of the HFIR register\n+\t * during runtime. This bit needs to be programmed during\n+\t * initial configuration and its value must not be changed\n+\t * during runtime.*/\n+\tif (core_if->core_params->reload_ctl == 1) {\n+\t\thfir.d32 = DWC_READ_REG32(&host_if->host_global_regs->hfir);\n+\t\thfir.b.hfirrldctrl = 1;\n+\t\tDWC_WRITE_REG32(&host_if->host_global_regs->hfir, hfir.d32);\n+\t}\n+\n+\tif (core_if->core_params->dma_desc_enable) {\n+\t\tuint8_t op_mode = core_if->hwcfg2.b.op_mode;\n+\t\tif (!\n+\t\t    (core_if->hwcfg4.b.desc_dma\n+\t\t     && (core_if->snpsid >= OTG_CORE_REV_2_90a)\n+\t\t     && ((op_mode == DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG)\n+\t\t\t || (op_mode == DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG)\n+\t\t\t || (op_mode ==\n+\t\t\t     DWC_HWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE_OTG)\n+\t\t\t || (op_mode == DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST)\n+\t\t\t || (op_mode ==\n+\t\t\t     DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST)))) {\n+\n+\t\t\tDWC_ERROR(\"Host can't operate in Descriptor DMA mode.\\n\"\n+\t\t\t\t  \"Either core version is below 2.90a or \"\n+\t\t\t\t  \"GHWCFG2, GHWCFG4 registers' values do not allow Descriptor DMA in host mode.\\n\"\n+\t\t\t\t  \"To run the driver in Buffer DMA host mode set dma_desc_enable \"\n+\t\t\t\t  \"module parameter to 0.\\n\");\n+\t\t\treturn;\n+\t\t}\n+\t\thcfg.d32 = DWC_READ_REG32(&host_if->host_global_regs->hcfg);\n+\t\thcfg.b.descdma = 1;\n+\t\tDWC_WRITE_REG32(&host_if->host_global_regs->hcfg, hcfg.d32);\n+\t}\n+\n+\t/* Configure data FIFO sizes */\n+\tif (core_if->hwcfg2.b.dynamic_fifo && params->enable_dynamic_fifo) {\n+\t\tDWC_DEBUGPL(DBG_CIL, \"Total FIFO Size=%d\\n\",\n+\t\t\t    core_if->total_fifo_size);\n+\t\tDWC_DEBUGPL(DBG_CIL, \"Rx FIFO Size=%d\\n\",\n+\t\t\t    params->host_rx_fifo_size);\n+\t\tDWC_DEBUGPL(DBG_CIL, \"NP Tx FIFO Size=%d\\n\",\n+\t\t\t    params->host_nperio_tx_fifo_size);\n+\t\tDWC_DEBUGPL(DBG_CIL, \"P Tx FIFO Size=%d\\n\",\n+\t\t\t    params->host_perio_tx_fifo_size);\n+\n+\t\t/* Rx FIFO */\n+\t\tDWC_DEBUGPL(DBG_CIL, \"initial grxfsiz=%08x\\n\",\n+\t\t\t    DWC_READ_REG32(&global_regs->grxfsiz));\n+\t\tDWC_WRITE_REG32(&global_regs->grxfsiz,\n+\t\t\t\tparams->host_rx_fifo_size);\n+\t\tDWC_DEBUGPL(DBG_CIL, \"new grxfsiz=%08x\\n\",\n+\t\t\t    DWC_READ_REG32(&global_regs->grxfsiz));\n+\n+\t\t/* Non-periodic Tx FIFO */\n+\t\tDWC_DEBUGPL(DBG_CIL, \"initial gnptxfsiz=%08x\\n\",\n+\t\t\t    DWC_READ_REG32(&global_regs->gnptxfsiz));\n+\t\tnptxfifosize.b.depth = params->host_nperio_tx_fifo_size;\n+\t\tnptxfifosize.b.startaddr = params->host_rx_fifo_size;\n+\t\tDWC_WRITE_REG32(&global_regs->gnptxfsiz, nptxfifosize.d32);\n+\t\tDWC_DEBUGPL(DBG_CIL, \"new gnptxfsiz=%08x\\n\",\n+\t\t\t    DWC_READ_REG32(&global_regs->gnptxfsiz));\n+\n+\t\t/* Periodic Tx FIFO */\n+\t\tDWC_DEBUGPL(DBG_CIL, \"initial hptxfsiz=%08x\\n\",\n+\t\t\t    DWC_READ_REG32(&global_regs->hptxfsiz));\n+\t\tptxfifosize.b.depth = params->host_perio_tx_fifo_size;\n+\t\tptxfifosize.b.startaddr =\n+\t\t    nptxfifosize.b.startaddr + nptxfifosize.b.depth;\n+\t\tDWC_WRITE_REG32(&global_regs->hptxfsiz, ptxfifosize.d32);\n+\t\tDWC_DEBUGPL(DBG_CIL, \"new hptxfsiz=%08x\\n\",\n+\t\t\t    DWC_READ_REG32(&global_regs->hptxfsiz));\n+\n+\t\tif (core_if->en_multiple_tx_fifo\n+\t\t    && core_if->snpsid <= OTG_CORE_REV_2_94a) {\n+\t\t\t/* Global DFIFOCFG calculation for Host mode - include RxFIFO, NPTXFIFO and HPTXFIFO */\n+\t\t\tgdfifocfg.d32 = DWC_READ_REG32(&global_regs->gdfifocfg);\n+\t\t\trxfsiz = (DWC_READ_REG32(&global_regs->grxfsiz) & 0x0000ffff);\n+\t\t\tnptxfsiz = (DWC_READ_REG32(&global_regs->gnptxfsiz) >> 16);\n+\t\t\thptxfsiz = (DWC_READ_REG32(&global_regs->hptxfsiz) >> 16);\n+\t\t\tgdfifocfg.b.epinfobase = rxfsiz + nptxfsiz + hptxfsiz;\n+\t\t\tDWC_WRITE_REG32(&global_regs->gdfifocfg, gdfifocfg.d32);\n+\t\t}\n+\t}\n+\n+\t/* TODO - check this */\n+\t/* Clear Host Set HNP Enable in the OTG Control Register */\n+\tgotgctl.b.hstsethnpen = 1;\n+\tDWC_MODIFY_REG32(&global_regs->gotgctl, gotgctl.d32, 0);\n+\t/* Make sure the FIFOs are flushed. */\n+\tdwc_otg_flush_tx_fifo(core_if, 0x10 /* all TX FIFOs */ );\n+\tdwc_otg_flush_rx_fifo(core_if);\n+\n+\t/* Clear Host Set HNP Enable in the OTG Control Register */\n+\tgotgctl.b.hstsethnpen = 1;\n+\tDWC_MODIFY_REG32(&global_regs->gotgctl, gotgctl.d32, 0);\n+\n+\tif (!core_if->core_params->dma_desc_enable) {\n+\t\t/* Flush out any leftover queued requests. */\n+\t\tnum_channels = core_if->core_params->host_channels;\n+\n+\t\tfor (i = 0; i < num_channels; i++) {\n+\t\t\thc_regs = core_if->host_if->hc_regs[i];\n+\t\t\thcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);\n+\t\t\thcchar.b.chen = 0;\n+\t\t\thcchar.b.chdis = 1;\n+\t\t\thcchar.b.epdir = 0;\n+\t\t\tDWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);\n+\t\t}\n+\n+\t\t/* Halt all channels to put them into a known state. */\n+\t\tfor (i = 0; i < num_channels; i++) {\n+\t\t\tint count = 0;\n+\t\t\thc_regs = core_if->host_if->hc_regs[i];\n+\t\t\thcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);\n+\t\t\thcchar.b.chen = 1;\n+\t\t\thcchar.b.chdis = 1;\n+\t\t\thcchar.b.epdir = 0;\n+\t\t\tDWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);\n+\t\t\tDWC_DEBUGPL(DBG_HCDV, \"%s: Halt channel %d regs %p\\n\", __func__, i, hc_regs);\n+\t\t\tdo {\n+\t\t\t\thcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);\n+\t\t\t\tif (++count > 1000) {\n+\t\t\t\t\tDWC_ERROR\n+\t\t\t\t\t    (\"%s: Unable to clear halt on channel %d (timeout HCCHAR 0x%X @%p)\\n\",\n+\t\t\t\t\t     __func__, i, hcchar.d32, &hc_regs->hcchar);\n+\t\t\t\t\tbreak;\n+\t\t\t\t}\n+\t\t\t\tdwc_udelay(1);\n+\t\t\t} while (hcchar.b.chen);\n+\t\t}\n+\t}\n+\n+\t/* Turn on the vbus power. */\n+\tDWC_PRINTF(\"Init: Port Power? op_state=%d\\n\", core_if->op_state);\n+\tif (core_if->op_state == A_HOST) {\n+\t\thprt0.d32 = dwc_otg_read_hprt0(core_if);\n+\t\tDWC_PRINTF(\"Init: Power Port (%d)\\n\", hprt0.b.prtpwr);\n+\t\tif (hprt0.b.prtpwr == 0) {\n+\t\t\thprt0.b.prtpwr = 1;\n+\t\t\tDWC_WRITE_REG32(host_if->hprt0, hprt0.d32);\n+\t\t}\n+\t}\n+\n+\tdwc_otg_enable_host_interrupts(core_if);\n+}\n+\n+/**\n+ * Prepares a host channel for transferring packets to/from a specific\n+ * endpoint. The HCCHARn register is set up with the characteristics specified\n+ * in _hc. Host channel interrupts that may need to be serviced while this\n+ * transfer is in progress are enabled.\n+ *\n+ * @param core_if Programming view of DWC_otg controller\n+ * @param hc Information needed to initialize the host channel\n+ */\n+void dwc_otg_hc_init(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)\n+{\n+\thcintmsk_data_t hc_intr_mask;\n+\thcchar_data_t hcchar;\n+\thcsplt_data_t hcsplt;\n+\n+\tuint8_t hc_num = hc->hc_num;\n+\tdwc_otg_host_if_t *host_if = core_if->host_if;\n+\tdwc_otg_hc_regs_t *hc_regs = host_if->hc_regs[hc_num];\n+\n+\t/* Clear old interrupt conditions for this host channel. */\n+\thc_intr_mask.d32 = 0xFFFFFFFF;\n+\thc_intr_mask.b.reserved14_31 = 0;\n+\tDWC_WRITE_REG32(&hc_regs->hcint, hc_intr_mask.d32);\n+\n+\t/* Enable channel interrupts required for this transfer. */\n+\thc_intr_mask.d32 = 0;\n+\thc_intr_mask.b.chhltd = 1;\n+\tif (core_if->dma_enable) {\n+\t\t/* For Descriptor DMA mode core halts the channel on AHB error. Interrupt is not required */\n+\t\tif (!core_if->dma_desc_enable)\n+\t\t\thc_intr_mask.b.ahberr = 1;\n+\t\telse {\n+\t\t\tif (hc->ep_type == DWC_OTG_EP_TYPE_ISOC)\n+\t\t\t\thc_intr_mask.b.xfercompl = 1;\n+\t\t}\n+\n+\t\tif (hc->error_state && !hc->do_split &&\n+\t\t    hc->ep_type != DWC_OTG_EP_TYPE_ISOC) {\n+\t\t\thc_intr_mask.b.ack = 1;\n+\t\t\tif (hc->ep_is_in) {\n+\t\t\t\thc_intr_mask.b.datatglerr = 1;\n+\t\t\t\tif (hc->ep_type != DWC_OTG_EP_TYPE_INTR) {\n+\t\t\t\t\thc_intr_mask.b.nak = 1;\n+\t\t\t\t}\n+\t\t\t}\n+\t\t}\n+\t} else {\n+\t\tswitch (hc->ep_type) {\n+\t\tcase DWC_OTG_EP_TYPE_CONTROL:\n+\t\tcase DWC_OTG_EP_TYPE_BULK:\n+\t\t\thc_intr_mask.b.xfercompl = 1;\n+\t\t\thc_intr_mask.b.stall = 1;\n+\t\t\thc_intr_mask.b.xacterr = 1;\n+\t\t\thc_intr_mask.b.datatglerr = 1;\n+\t\t\tif (hc->ep_is_in) {\n+\t\t\t\thc_intr_mask.b.bblerr = 1;\n+\t\t\t} else {\n+\t\t\t\thc_intr_mask.b.nak = 1;\n+\t\t\t\thc_intr_mask.b.nyet = 1;\n+\t\t\t\tif (hc->do_ping) {\n+\t\t\t\t\thc_intr_mask.b.ack = 1;\n+\t\t\t\t}\n+\t\t\t}\n+\n+\t\t\tif (hc->do_split) {\n+\t\t\t\thc_intr_mask.b.nak = 1;\n+\t\t\t\tif (hc->complete_split) {\n+\t\t\t\t\thc_intr_mask.b.nyet = 1;\n+\t\t\t\t} else {\n+\t\t\t\t\thc_intr_mask.b.ack = 1;\n+\t\t\t\t}\n+\t\t\t}\n+\n+\t\t\tif (hc->error_state) {\n+\t\t\t\thc_intr_mask.b.ack = 1;\n+\t\t\t}\n+\t\t\tbreak;\n+\t\tcase DWC_OTG_EP_TYPE_INTR:\n+\t\t\thc_intr_mask.b.xfercompl = 1;\n+\t\t\thc_intr_mask.b.nak = 1;\n+\t\t\thc_intr_mask.b.stall = 1;\n+\t\t\thc_intr_mask.b.xacterr = 1;\n+\t\t\thc_intr_mask.b.datatglerr = 1;\n+\t\t\thc_intr_mask.b.frmovrun = 1;\n+\n+\t\t\tif (hc->ep_is_in) {\n+\t\t\t\thc_intr_mask.b.bblerr = 1;\n+\t\t\t}\n+\t\t\tif (hc->error_state) {\n+\t\t\t\thc_intr_mask.b.ack = 1;\n+\t\t\t}\n+\t\t\tif (hc->do_split) {\n+\t\t\t\tif (hc->complete_split) {\n+\t\t\t\t\thc_intr_mask.b.nyet = 1;\n+\t\t\t\t} else {\n+\t\t\t\t\thc_intr_mask.b.ack = 1;\n+\t\t\t\t}\n+\t\t\t}\n+\t\t\tbreak;\n+\t\tcase DWC_OTG_EP_TYPE_ISOC:\n+\t\t\thc_intr_mask.b.xfercompl = 1;\n+\t\t\thc_intr_mask.b.frmovrun = 1;\n+\t\t\thc_intr_mask.b.ack = 1;\n+\n+\t\t\tif (hc->ep_is_in) {\n+\t\t\t\thc_intr_mask.b.xacterr = 1;\n+\t\t\t\thc_intr_mask.b.bblerr = 1;\n+\t\t\t}\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\tDWC_WRITE_REG32(&hc_regs->hcintmsk, hc_intr_mask.d32);\n+\n+\t/*\n+\t * Program the HCCHARn register with the endpoint characteristics for\n+\t * the current transfer.\n+\t */\n+\thcchar.d32 = 0;\n+\thcchar.b.devaddr = hc->dev_addr;\n+\thcchar.b.epnum = hc->ep_num;\n+\thcchar.b.epdir = hc->ep_is_in;\n+\thcchar.b.lspddev = (hc->speed == DWC_OTG_EP_SPEED_LOW);\n+\thcchar.b.eptype = hc->ep_type;\n+\thcchar.b.mps = hc->max_packet;\n+\n+\tDWC_WRITE_REG32(&host_if->hc_regs[hc_num]->hcchar, hcchar.d32);\n+\n+\tDWC_DEBUGPL(DBG_HCDV, \"%s: Channel %d, Dev Addr %d, EP #%d\\n\",\n+                    __func__, hc->hc_num, hcchar.b.devaddr, hcchar.b.epnum);\n+\tDWC_DEBUGPL(DBG_HCDV, \"\t Is In %d, Is Low Speed %d, EP Type %d, \"\n+                                \"Max Pkt %d, Multi Cnt %d\\n\",\n+                    hcchar.b.epdir, hcchar.b.lspddev, hcchar.b.eptype,\n+                    hcchar.b.mps, hcchar.b.multicnt);\n+\n+\t/*\n+\t * Program the HCSPLIT register for SPLITs\n+\t */\n+\thcsplt.d32 = 0;\n+\tif (hc->do_split) {\n+\t\tDWC_DEBUGPL(DBG_HCDV, \"Programming HC %d with split --> %s\\n\",\n+\t\t\t    hc->hc_num,\n+\t\t\t    hc->complete_split ? \"CSPLIT\" : \"SSPLIT\");\n+\t\thcsplt.b.compsplt = hc->complete_split;\n+\t\thcsplt.b.xactpos = hc->xact_pos;\n+\t\thcsplt.b.hubaddr = hc->hub_addr;\n+\t\thcsplt.b.prtaddr = hc->port_addr;\n+\t\tDWC_DEBUGPL(DBG_HCDV, \"\\t  comp split %d\\n\", hc->complete_split);\n+\t\tDWC_DEBUGPL(DBG_HCDV, \"\\t  xact pos %d\\n\", hc->xact_pos);\n+\t\tDWC_DEBUGPL(DBG_HCDV, \"\\t  hub addr %d\\n\", hc->hub_addr);\n+\t\tDWC_DEBUGPL(DBG_HCDV, \"\\t  port addr %d\\n\", hc->port_addr);\n+\t\tDWC_DEBUGPL(DBG_HCDV, \"\\t  is_in %d\\n\", hc->ep_is_in);\n+\t\tDWC_DEBUGPL(DBG_HCDV, \"\\t  Max Pkt: %d\\n\", hcchar.b.mps);\n+\t\tDWC_DEBUGPL(DBG_HCDV, \"\\t  xferlen: %d\\n\", hc->xfer_len);\n+\t}\n+\tDWC_WRITE_REG32(&host_if->hc_regs[hc_num]->hcsplt, hcsplt.d32);\n+\n+}\n+\n+/**\n+ * Attempts to halt a host channel. This function should only be called in\n+ * Slave mode or to abort a transfer in either Slave mode or DMA mode. Under\n+ * normal circumstances in DMA mode, the controller halts the channel when the\n+ * transfer is complete or a condition occurs that requires application\n+ * intervention.\n+ *\n+ * In slave mode, checks for a free request queue entry, then sets the Channel\n+ * Enable and Channel Disable bits of the Host Channel Characteristics\n+ * register of the specified channel to intiate the halt. If there is no free\n+ * request queue entry, sets only the Channel Disable bit of the HCCHARn\n+ * register to flush requests for this channel. In the latter case, sets a\n+ * flag to indicate that the host channel needs to be halted when a request\n+ * queue slot is open.\n+ *\n+ * In DMA mode, always sets the Channel Enable and Channel Disable bits of the\n+ * HCCHARn register. The controller ensures there is space in the request\n+ * queue before submitting the halt request.\n+ *\n+ * Some time may elapse before the core flushes any posted requests for this\n+ * host channel and halts. The Channel Halted interrupt handler completes the\n+ * deactivation of the host channel.\n+ *\n+ * @param core_if Controller register interface.\n+ * @param hc Host channel to halt.\n+ * @param halt_status Reason for halting the channel.\n+ */\n+void dwc_otg_hc_halt(dwc_otg_core_if_t * core_if,\n+\t\t     dwc_hc_t * hc, dwc_otg_halt_status_e halt_status)\n+{\n+\tgnptxsts_data_t nptxsts;\n+\thptxsts_data_t hptxsts;\n+\thcchar_data_t hcchar;\n+\tdwc_otg_hc_regs_t *hc_regs;\n+\tdwc_otg_core_global_regs_t *global_regs;\n+\tdwc_otg_host_global_regs_t *host_global_regs;\n+\n+\thc_regs = core_if->host_if->hc_regs[hc->hc_num];\n+\tglobal_regs = core_if->core_global_regs;\n+\thost_global_regs = core_if->host_if->host_global_regs;\n+\n+\tDWC_ASSERT(!(halt_status == DWC_OTG_HC_XFER_NO_HALT_STATUS),\n+\t\t   \"halt_status = %d\\n\", halt_status);\n+\n+\tif (halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE ||\n+\t    halt_status == DWC_OTG_HC_XFER_AHB_ERR) {\n+\t\t/*\n+\t\t * Disable all channel interrupts except Ch Halted. The QTD\n+\t\t * and QH state associated with this transfer has been cleared\n+\t\t * (in the case of URB_DEQUEUE), so the channel needs to be\n+\t\t * shut down carefully to prevent crashes.\n+\t\t */\n+\t\thcintmsk_data_t hcintmsk;\n+\t\thcintmsk.d32 = 0;\n+\t\thcintmsk.b.chhltd = 1;\n+\t\tDWC_WRITE_REG32(&hc_regs->hcintmsk, hcintmsk.d32);\n+\n+\t\t/*\n+\t\t * Make sure no other interrupts besides halt are currently\n+\t\t * pending. Handling another interrupt could cause a crash due\n+\t\t * to the QTD and QH state.\n+\t\t */\n+\t\tDWC_WRITE_REG32(&hc_regs->hcint, ~hcintmsk.d32);\n+\n+\t\t/*\n+\t\t * Make sure the halt status is set to URB_DEQUEUE or AHB_ERR\n+\t\t * even if the channel was already halted for some other\n+\t\t * reason.\n+\t\t */\n+\t\thc->halt_status = halt_status;\n+\n+\t\thcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);\n+\t\tif (hcchar.b.chen == 0) {\n+\t\t\t/*\n+\t\t\t * The channel is either already halted or it hasn't\n+\t\t\t * started yet. In DMA mode, the transfer may halt if\n+\t\t\t * it finishes normally or a condition occurs that\n+\t\t\t * requires driver intervention. Don't want to halt\n+\t\t\t * the channel again. In either Slave or DMA mode,\n+\t\t\t * it's possible that the transfer has been assigned\n+\t\t\t * to a channel, but not started yet when an URB is\n+\t\t\t * dequeued. Don't want to halt a channel that hasn't\n+\t\t\t * started yet.\n+\t\t\t */\n+\t\t\treturn;\n+\t\t}\n+\t}\n+\tif (hc->halt_pending) {\n+\t\t/*\n+\t\t * A halt has already been issued for this channel. This might\n+\t\t * happen when a transfer is aborted by a higher level in\n+\t\t * the stack.\n+\t\t */\n+#ifdef DEBUG\n+\t\tDWC_PRINTF\n+\t\t    (\"*** %s: Channel %d, _hc->halt_pending already set ***\\n\",\n+\t\t     __func__, hc->hc_num);\n+\n+#endif\n+\t\treturn;\n+\t}\n+\n+\thcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);\n+\n+\t/* No need to set the bit in DDMA for disabling the channel */\n+\t//TODO check it everywhere channel is disabled\n+\tif (!core_if->core_params->dma_desc_enable)\n+\t\thcchar.b.chen = 1;\n+\thcchar.b.chdis = 1;\n+\n+\tif (!core_if->dma_enable) {\n+\t\t/* Check for space in the request queue to issue the halt. */\n+\t\tif (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL ||\n+\t\t    hc->ep_type == DWC_OTG_EP_TYPE_BULK) {\n+\t\t\tnptxsts.d32 = DWC_READ_REG32(&global_regs->gnptxsts);\n+\t\t\tif (nptxsts.b.nptxqspcavail == 0) {\n+\t\t\t\thcchar.b.chen = 0;\n+\t\t\t}\n+\t\t} else {\n+\t\t\thptxsts.d32 =\n+\t\t\t    DWC_READ_REG32(&host_global_regs->hptxsts);\n+\t\t\tif ((hptxsts.b.ptxqspcavail == 0)\n+\t\t\t    || (core_if->queuing_high_bandwidth)) {\n+\t\t\t\thcchar.b.chen = 0;\n+\t\t\t}\n+\t\t}\n+\t}\n+\tDWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);\n+\n+\thc->halt_status = halt_status;\n+\n+\tif (hcchar.b.chen) {\n+\t\thc->halt_pending = 1;\n+\t\thc->halt_on_queue = 0;\n+\t} else {\n+\t\thc->halt_on_queue = 1;\n+\t}\n+\n+\tDWC_DEBUGPL(DBG_HCDV, \"%s: Channel %d\\n\", __func__, hc->hc_num);\n+\tDWC_DEBUGPL(DBG_HCDV, \"\t hcchar: 0x%08x\\n\", hcchar.d32);\n+\tDWC_DEBUGPL(DBG_HCDV, \"\t halt_pending: %d\\n\", hc->halt_pending);\n+\tDWC_DEBUGPL(DBG_HCDV, \"\t halt_on_queue: %d\\n\", hc->halt_on_queue);\n+\tDWC_DEBUGPL(DBG_HCDV, \"\t halt_status: %d\\n\", hc->halt_status);\n+\n+\treturn;\n+}\n+\n+/**\n+ * Clears the transfer state for a host channel. This function is normally\n+ * called after a transfer is done and the host channel is being released.\n+ *\n+ * @param core_if Programming view of DWC_otg controller.\n+ * @param hc Identifies the host channel to clean up.\n+ */\n+void dwc_otg_hc_cleanup(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)\n+{\n+\tdwc_otg_hc_regs_t *hc_regs;\n+\n+\thc->xfer_started = 0;\n+\n+\t/*\n+\t * Clear channel interrupt enables and any unhandled channel interrupt\n+\t * conditions.\n+\t */\n+\thc_regs = core_if->host_if->hc_regs[hc->hc_num];\n+\tDWC_WRITE_REG32(&hc_regs->hcintmsk, 0);\n+\tDWC_WRITE_REG32(&hc_regs->hcint, 0xFFFFFFFF);\n+#ifdef DEBUG\n+\tDWC_TIMER_CANCEL(core_if->hc_xfer_timer[hc->hc_num]);\n+#endif\n+}\n+\n+/**\n+ * Sets the channel property that indicates in which frame a periodic transfer\n+ * should occur. This is always set to the _next_ frame. This function has no\n+ * effect on non-periodic transfers.\n+ *\n+ * @param core_if Programming view of DWC_otg controller.\n+ * @param hc Identifies the host channel to set up and its properties.\n+ * @param hcchar Current value of the HCCHAR register for the specified host\n+ * channel.\n+ */\n+static inline void hc_set_even_odd_frame(dwc_otg_core_if_t * core_if,\n+\t\t\t\t\t dwc_hc_t * hc, hcchar_data_t * hcchar)\n+{\n+\tif (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||\n+\t    hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {\n+\t\thfnum_data_t hfnum;\n+\t\thfnum.d32 =\n+\t\t    DWC_READ_REG32(&core_if->host_if->host_global_regs->hfnum);\n+\n+\t\t/* 1 if _next_ frame is odd, 0 if it's even */\n+\t\thcchar->b.oddfrm = (hfnum.b.frnum & 0x1) ? 0 : 1;\n+#ifdef DEBUG\n+\t\tif (hc->ep_type == DWC_OTG_EP_TYPE_INTR && hc->do_split\n+\t\t    && !hc->complete_split) {\n+\t\t\tswitch (hfnum.b.frnum & 0x7) {\n+\t\t\tcase 7:\n+\t\t\t\tcore_if->hfnum_7_samples++;\n+\t\t\t\tcore_if->hfnum_7_frrem_accum += hfnum.b.frrem;\n+\t\t\t\tbreak;\n+\t\t\tcase 0:\n+\t\t\t\tcore_if->hfnum_0_samples++;\n+\t\t\t\tcore_if->hfnum_0_frrem_accum += hfnum.b.frrem;\n+\t\t\t\tbreak;\n+\t\t\tdefault:\n+\t\t\t\tcore_if->hfnum_other_samples++;\n+\t\t\t\tcore_if->hfnum_other_frrem_accum +=\n+\t\t\t\t    hfnum.b.frrem;\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t}\n+#endif\n+\t}\n+}\n+\n+#ifdef DEBUG\n+void hc_xfer_timeout(void *ptr)\n+{\n+\thc_xfer_info_t *xfer_info = NULL;\n+\tint hc_num = 0;\n+\n+\tif (ptr)\n+\t\txfer_info = (hc_xfer_info_t *) ptr;\n+\n+\tif (!xfer_info->hc) {\n+\t\tDWC_ERROR(\"xfer_info->hc = %p\\n\", xfer_info->hc);\n+\t\treturn;\n+\t}\n+\n+\thc_num = xfer_info->hc->hc_num;\n+\tDWC_WARN(\"%s: timeout on channel %d\\n\", __func__, hc_num);\n+\tDWC_WARN(\"\tstart_hcchar_val 0x%08x\\n\",\n+\t\t xfer_info->core_if->start_hcchar_val[hc_num]);\n+}\n+#endif\n+\n+void ep_xfer_timeout(void *ptr)\n+{\n+\tep_xfer_info_t *xfer_info = NULL;\n+\tint ep_num = 0;\n+\tdctl_data_t dctl = {.d32 = 0 };\n+\tgintsts_data_t gintsts = {.d32 = 0 };\n+\tgintmsk_data_t gintmsk = {.d32 = 0 };\n+\n+\tif (ptr)\n+\t\txfer_info = (ep_xfer_info_t *) ptr;\n+\n+\tif (!xfer_info->ep) {\n+\t\tDWC_ERROR(\"xfer_info->ep = %p\\n\", xfer_info->ep);\n+\t\treturn;\n+\t}\n+\n+\tep_num = xfer_info->ep->num;\n+\tDWC_WARN(\"%s: timeout on endpoit %d\\n\", __func__, ep_num);\n+\t/* Put the sate to 2 as it was time outed */\n+\txfer_info->state = 2;\n+\n+\tdctl.d32 =\n+\t    DWC_READ_REG32(&xfer_info->core_if->dev_if->dev_global_regs->dctl);\n+\tgintsts.d32 =\n+\t    DWC_READ_REG32(&xfer_info->core_if->core_global_regs->gintsts);\n+\tgintmsk.d32 =\n+\t    DWC_READ_REG32(&xfer_info->core_if->core_global_regs->gintmsk);\n+\n+\tif (!gintmsk.b.goutnakeff) {\n+\t\t/* Unmask it */\n+\t\tgintmsk.b.goutnakeff = 1;\n+\t\tDWC_WRITE_REG32(&xfer_info->core_if->core_global_regs->gintmsk,\n+\t\t\t\tgintmsk.d32);\n+\n+\t}\n+\n+\tif (!gintsts.b.goutnakeff) {\n+\t\tdctl.b.sgoutnak = 1;\n+\t}\n+\tDWC_WRITE_REG32(&xfer_info->core_if->dev_if->dev_global_regs->dctl,\n+\t\t\tdctl.d32);\n+\n+}\n+\n+void set_pid_isoc(dwc_hc_t * hc)\n+{\n+\t/* Set up the initial PID for the transfer. */\n+\tif (hc->speed == DWC_OTG_EP_SPEED_HIGH) {\n+\t\tif (hc->ep_is_in) {\n+\t\t\tif (hc->multi_count == 1) {\n+\t\t\t\thc->data_pid_start = DWC_OTG_HC_PID_DATA0;\n+\t\t\t} else if (hc->multi_count == 2) {\n+\t\t\t\thc->data_pid_start = DWC_OTG_HC_PID_DATA1;\n+\t\t\t} else {\n+\t\t\t\thc->data_pid_start = DWC_OTG_HC_PID_DATA2;\n+\t\t\t}\n+\t\t} else {\n+\t\t\tif (hc->multi_count == 1) {\n+\t\t\t\thc->data_pid_start = DWC_OTG_HC_PID_DATA0;\n+\t\t\t} else {\n+\t\t\t\thc->data_pid_start = DWC_OTG_HC_PID_MDATA;\n+\t\t\t}\n+\t\t}\n+\t} else {\n+\t\thc->data_pid_start = DWC_OTG_HC_PID_DATA0;\n+\t}\n+}\n+\n+/**\n+ * This function does the setup for a data transfer for a host channel and\n+ * starts the transfer. May be called in either Slave mode or DMA mode. In\n+ * Slave mode, the caller must ensure that there is sufficient space in the\n+ * request queue and Tx Data FIFO.\n+ *\n+ * For an OUT transfer in Slave mode, it loads a data packet into the\n+ * appropriate FIFO. If necessary, additional data packets will be loaded in\n+ * the Host ISR.\n+ *\n+ * For an IN transfer in Slave mode, a data packet is requested. The data\n+ * packets are unloaded from the Rx FIFO in the Host ISR. If necessary,\n+ * additional data packets are requested in the Host ISR.\n+ *\n+ * For a PING transfer in Slave mode, the Do Ping bit is set in the HCTSIZ\n+ * register along with a packet count of 1 and the channel is enabled. This\n+ * causes a single PING transaction to occur. Other fields in HCTSIZ are\n+ * simply set to 0 since no data transfer occurs in this case.\n+ *\n+ * For a PING transfer in DMA mode, the HCTSIZ register is initialized with\n+ * all the information required to perform the subsequent data transfer. In\n+ * addition, the Do Ping bit is set in the HCTSIZ register. In this case, the\n+ * controller performs the entire PING protocol, then starts the data\n+ * transfer.\n+ *\n+ * @param core_if Programming view of DWC_otg controller.\n+ * @param hc Information needed to initialize the host channel. The xfer_len\n+ * value may be reduced to accommodate the max widths of the XferSize and\n+ * PktCnt fields in the HCTSIZn register. The multi_count value may be changed\n+ * to reflect the final xfer_len value.\n+ */\n+void dwc_otg_hc_start_transfer(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)\n+{\n+\thcchar_data_t hcchar;\n+\thctsiz_data_t hctsiz;\n+\tuint16_t num_packets;\n+\tuint32_t max_hc_xfer_size = core_if->core_params->max_transfer_size;\n+\tuint16_t max_hc_pkt_count = core_if->core_params->max_packet_count;\n+\tdwc_otg_hc_regs_t *hc_regs = core_if->host_if->hc_regs[hc->hc_num];\n+\n+\thctsiz.d32 = 0;\n+\n+\tif (hc->do_ping) {\n+\t\tif (!core_if->dma_enable) {\n+\t\t\tdwc_otg_hc_do_ping(core_if, hc);\n+\t\t\thc->xfer_started = 1;\n+\t\t\treturn;\n+\t\t} else {\n+\t\t\thctsiz.b.dopng = 1;\n+\t\t}\n+\t}\n+\n+\tif (hc->do_split) {\n+\t\tnum_packets = 1;\n+\n+\t\tif (hc->complete_split && !hc->ep_is_in) {\n+\t\t\t/* For CSPLIT OUT Transfer, set the size to 0 so the\n+\t\t\t * core doesn't expect any data written to the FIFO */\n+\t\t\thc->xfer_len = 0;\n+\t\t} else if (hc->ep_is_in || (hc->xfer_len > hc->max_packet)) {\n+\t\t\thc->xfer_len = hc->max_packet;\n+\t\t} else if (!hc->ep_is_in && (hc->xfer_len > 188)) {\n+\t\t\thc->xfer_len = 188;\n+\t\t}\n+\n+\t\thctsiz.b.xfersize = hc->xfer_len;\n+\t} else {\n+\t\t/*\n+\t\t * Ensure that the transfer length and packet count will fit\n+\t\t * in the widths allocated for them in the HCTSIZn register.\n+\t\t */\n+\t\tif (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||\n+\t\t    hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {\n+\t\t\t/*\n+\t\t\t * Make sure the transfer size is no larger than one\n+\t\t\t * (micro)frame's worth of data. (A check was done\n+\t\t\t * when the periodic transfer was accepted to ensure\n+\t\t\t * that a (micro)frame's worth of data can be\n+\t\t\t * programmed into a channel.)\n+\t\t\t */\n+\t\t\tuint32_t max_periodic_len =\n+\t\t\t    hc->multi_count * hc->max_packet;\n+\t\t\tif (hc->xfer_len > max_periodic_len) {\n+\t\t\t\thc->xfer_len = max_periodic_len;\n+\t\t\t} else {\n+\t\t\t}\n+\t\t} else if (hc->xfer_len > max_hc_xfer_size) {\n+\t\t\t/* Make sure that xfer_len is a multiple of max packet size. */\n+\t\t\thc->xfer_len = max_hc_xfer_size - hc->max_packet + 1;\n+\t\t}\n+\n+\t\tif (hc->xfer_len > 0) {\n+\t\t\tnum_packets =\n+\t\t\t    (hc->xfer_len + hc->max_packet -\n+\t\t\t     1) / hc->max_packet;\n+\t\t\tif (num_packets > max_hc_pkt_count) {\n+\t\t\t\tnum_packets = max_hc_pkt_count;\n+\t\t\t\thc->xfer_len = num_packets * hc->max_packet;\n+\t\t\t}\n+\t\t} else {\n+\t\t\t/* Need 1 packet for transfer length of 0. */\n+\t\t\tnum_packets = 1;\n+\t\t}\n+\n+\t\tif (hc->ep_is_in) {\n+\t\t\t/* Always program an integral # of max packets for IN transfers. */\n+\t\t\thc->xfer_len = num_packets * hc->max_packet;\n+\t\t}\n+\n+\t\tif (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||\n+\t\t    hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {\n+\t\t\t/*\n+\t\t\t * Make sure that the multi_count field matches the\n+\t\t\t * actual transfer length.\n+\t\t\t */\n+\t\t\thc->multi_count = num_packets;\n+\t\t}\n+\n+\t\tif (hc->ep_type == DWC_OTG_EP_TYPE_ISOC)\n+\t\t\tset_pid_isoc(hc);\n+\n+\t\thctsiz.b.xfersize = hc->xfer_len;\n+\t}\n+\n+\thc->start_pkt_count = num_packets;\n+\thctsiz.b.pktcnt = num_packets;\n+\thctsiz.b.pid = hc->data_pid_start;\n+\tDWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32);\n+\n+\tDWC_DEBUGPL(DBG_HCDV, \"%s: Channel %d\\n\", __func__, hc->hc_num);\n+\tDWC_DEBUGPL(DBG_HCDV, \"\t Xfer Size: %d\\n\", hctsiz.b.xfersize);\n+\tDWC_DEBUGPL(DBG_HCDV, \"\t Num Pkts: %d\\n\", hctsiz.b.pktcnt);\n+\tDWC_DEBUGPL(DBG_HCDV, \"\t Start PID: %d\\n\", hctsiz.b.pid);\n+\n+\tif (core_if->dma_enable) {\n+\t\tdwc_dma_t dma_addr;\n+\t\tif (hc->align_buff) {\n+\t\t\tdma_addr = hc->align_buff;\n+\t\t} else {\n+\t\t\tdma_addr = ((unsigned long)hc->xfer_buff & 0xffffffff);\n+\t\t}\n+\t\tDWC_WRITE_REG32(&hc_regs->hcdma, dma_addr);\n+\t}\n+\n+\t/* Start the split */\n+\tif (hc->do_split) {\n+\t\thcsplt_data_t hcsplt;\n+\t\thcsplt.d32 = DWC_READ_REG32(&hc_regs->hcsplt);\n+\t\thcsplt.b.spltena = 1;\n+\t\tDWC_WRITE_REG32(&hc_regs->hcsplt, hcsplt.d32);\n+\t}\n+\n+\thcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);\n+\thcchar.b.multicnt = hc->multi_count;\n+\thc_set_even_odd_frame(core_if, hc, &hcchar);\n+#ifdef DEBUG\n+\tcore_if->start_hcchar_val[hc->hc_num] = hcchar.d32;\n+\tif (hcchar.b.chdis) {\n+\t\tDWC_WARN(\"%s: chdis set, channel %d, hcchar 0x%08x\\n\",\n+\t\t\t __func__, hc->hc_num, hcchar.d32);\n+\t}\n+#endif\n+\n+\t/* Set host channel enable after all other setup is complete. */\n+\thcchar.b.chen = 1;\n+\thcchar.b.chdis = 0;\n+\tDWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);\n+\n+\thc->xfer_started = 1;\n+\thc->requests++;\n+\n+\tif (!core_if->dma_enable && !hc->ep_is_in && hc->xfer_len > 0) {\n+\t\t/* Load OUT packet into the appropriate Tx FIFO. */\n+\t\tdwc_otg_hc_write_packet(core_if, hc);\n+\t}\n+#ifdef DEBUG\n+\tif (hc->ep_type != DWC_OTG_EP_TYPE_INTR) {\n+                DWC_DEBUGPL(DBG_HCDV, \"transfer %d from core_if %p\\n\",\n+                            hc->hc_num, core_if);//GRAYG\n+\t\tcore_if->hc_xfer_info[hc->hc_num].core_if = core_if;\n+\t\tcore_if->hc_xfer_info[hc->hc_num].hc = hc;\n+\n+\t\t/* Start a timer for this transfer. */\n+\t\tDWC_TIMER_SCHEDULE(core_if->hc_xfer_timer[hc->hc_num], 10000);\n+\t}\n+#endif\n+}\n+\n+/**\n+ * This function does the setup for a data transfer for a host channel\n+ * and starts the transfer in Descriptor DMA mode.\n+ *\n+ * Initializes HCTSIZ register. For a PING transfer the Do Ping bit is set.\n+ * Sets PID and NTD values. For periodic transfers\n+ * initializes SCHED_INFO field with micro-frame bitmap.\n+ *\n+ * Initializes HCDMA register with descriptor list address and CTD value\n+ * then starts the transfer via enabling the channel.\n+ *\n+ * @param core_if Programming view of DWC_otg controller.\n+ * @param hc Information needed to initialize the host channel.\n+ */\n+void dwc_otg_hc_start_transfer_ddma(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)\n+{\n+\tdwc_otg_hc_regs_t *hc_regs = core_if->host_if->hc_regs[hc->hc_num];\n+\thcchar_data_t hcchar;\n+\thctsiz_data_t hctsiz;\n+\thcdma_data_t hcdma;\n+\n+\thctsiz.d32 = 0;\n+\n+\tif (hc->do_ping)\n+\t\thctsiz.b_ddma.dopng = 1;\n+\n+\tif (hc->ep_type == DWC_OTG_EP_TYPE_ISOC)\n+\t\tset_pid_isoc(hc);\n+\n+\t/* Packet Count and Xfer Size are not used in Descriptor DMA mode */\n+\thctsiz.b_ddma.pid = hc->data_pid_start;\n+\thctsiz.b_ddma.ntd = hc->ntd - 1;\t/* 0 - 1 descriptor, 1 - 2 descriptors, etc. */\n+\thctsiz.b_ddma.schinfo = hc->schinfo;\t/* Non-zero only for high-speed interrupt endpoints */\n+\n+\tDWC_DEBUGPL(DBG_HCDV, \"%s: Channel %d\\n\", __func__, hc->hc_num);\n+\tDWC_DEBUGPL(DBG_HCDV, \"\t Start PID: %d\\n\", hctsiz.b.pid);\n+\tDWC_DEBUGPL(DBG_HCDV, \"\t NTD: %d\\n\", hctsiz.b_ddma.ntd);\n+\n+\tDWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32);\n+\n+\thcdma.d32 = 0;\n+\thcdma.b.dma_addr = ((uint32_t) hc->desc_list_addr) >> 11;\n+\n+\t/* Always start from first descriptor. */\n+\thcdma.b.ctd = 0;\n+\tDWC_WRITE_REG32(&hc_regs->hcdma, hcdma.d32);\n+\n+\thcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);\n+\thcchar.b.multicnt = hc->multi_count;\n+\n+#ifdef DEBUG\n+\tcore_if->start_hcchar_val[hc->hc_num] = hcchar.d32;\n+\tif (hcchar.b.chdis) {\n+\t\tDWC_WARN(\"%s: chdis set, channel %d, hcchar 0x%08x\\n\",\n+\t\t\t __func__, hc->hc_num, hcchar.d32);\n+\t}\n+#endif\n+\n+\t/* Set host channel enable after all other setup is complete. */\n+\thcchar.b.chen = 1;\n+\thcchar.b.chdis = 0;\n+\n+\tDWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);\n+\n+\thc->xfer_started = 1;\n+\thc->requests++;\n+\n+#ifdef DEBUG\n+\tif ((hc->ep_type != DWC_OTG_EP_TYPE_INTR)\n+\t    && (hc->ep_type != DWC_OTG_EP_TYPE_ISOC)) {\n+                DWC_DEBUGPL(DBG_HCDV, \"DMA transfer %d from core_if %p\\n\",\n+                            hc->hc_num, core_if);//GRAYG\n+\t\tcore_if->hc_xfer_info[hc->hc_num].core_if = core_if;\n+\t\tcore_if->hc_xfer_info[hc->hc_num].hc = hc;\n+\t\t/* Start a timer for this transfer. */\n+\t\tDWC_TIMER_SCHEDULE(core_if->hc_xfer_timer[hc->hc_num], 10000);\n+\t}\n+#endif\n+\n+}\n+\n+/**\n+ * This function continues a data transfer that was started by previous call\n+ * to <code>dwc_otg_hc_start_transfer</code>. The caller must ensure there is\n+ * sufficient space in the request queue and Tx Data FIFO. This function\n+ * should only be called in Slave mode. In DMA mode, the controller acts\n+ * autonomously to complete transfers programmed to a host channel.\n+ *\n+ * For an OUT transfer, a new data packet is loaded into the appropriate FIFO\n+ * if there is any data remaining to be queued. For an IN transfer, another\n+ * data packet is always requested. For the SETUP phase of a control transfer,\n+ * this function does nothing.\n+ *\n+ * @return 1 if a new request is queued, 0 if no more requests are required\n+ * for this transfer.\n+ */\n+int dwc_otg_hc_continue_transfer(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)\n+{\n+\tDWC_DEBUGPL(DBG_HCDV, \"%s: Channel %d\\n\", __func__, hc->hc_num);\n+\n+\tif (hc->do_split) {\n+\t\t/* SPLITs always queue just once per channel */\n+\t\treturn 0;\n+\t} else if (hc->data_pid_start == DWC_OTG_HC_PID_SETUP) {\n+\t\t/* SETUPs are queued only once since they can't be NAKed. */\n+\t\treturn 0;\n+\t} else if (hc->ep_is_in) {\n+\t\t/*\n+\t\t * Always queue another request for other IN transfers. If\n+\t\t * back-to-back INs are issued and NAKs are received for both,\n+\t\t * the driver may still be processing the first NAK when the\n+\t\t * second NAK is received. When the interrupt handler clears\n+\t\t * the NAK interrupt for the first NAK, the second NAK will\n+\t\t * not be seen. So we can't depend on the NAK interrupt\n+\t\t * handler to requeue a NAKed request. Instead, IN requests\n+\t\t * are issued each time this function is called. When the\n+\t\t * transfer completes, the extra requests for the channel will\n+\t\t * be flushed.\n+\t\t */\n+\t\thcchar_data_t hcchar;\n+\t\tdwc_otg_hc_regs_t *hc_regs =\n+\t\t    core_if->host_if->hc_regs[hc->hc_num];\n+\n+\t\thcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);\n+\t\thc_set_even_odd_frame(core_if, hc, &hcchar);\n+\t\thcchar.b.chen = 1;\n+\t\thcchar.b.chdis = 0;\n+\t\tDWC_DEBUGPL(DBG_HCDV, \"\t IN xfer: hcchar = 0x%08x\\n\",\n+\t\t\t    hcchar.d32);\n+\t\tDWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);\n+\t\thc->requests++;\n+\t\treturn 1;\n+\t} else {\n+\t\t/* OUT transfers. */\n+\t\tif (hc->xfer_count < hc->xfer_len) {\n+\t\t\tif (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||\n+\t\t\t    hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {\n+\t\t\t\thcchar_data_t hcchar;\n+\t\t\t\tdwc_otg_hc_regs_t *hc_regs;\n+\t\t\t\thc_regs = core_if->host_if->hc_regs[hc->hc_num];\n+\t\t\t\thcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);\n+\t\t\t\thc_set_even_odd_frame(core_if, hc, &hcchar);\n+\t\t\t}\n+\n+\t\t\t/* Load OUT packet into the appropriate Tx FIFO. */\n+\t\t\tdwc_otg_hc_write_packet(core_if, hc);\n+\t\t\thc->requests++;\n+\t\t\treturn 1;\n+\t\t} else {\n+\t\t\treturn 0;\n+\t\t}\n+\t}\n+}\n+\n+/**\n+ * Starts a PING transfer. This function should only be called in Slave mode.\n+ * The Do Ping bit is set in the HCTSIZ register, then the channel is enabled.\n+ */\n+void dwc_otg_hc_do_ping(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)\n+{\n+\thcchar_data_t hcchar;\n+\thctsiz_data_t hctsiz;\n+\tdwc_otg_hc_regs_t *hc_regs = core_if->host_if->hc_regs[hc->hc_num];\n+\n+\tDWC_DEBUGPL(DBG_HCDV, \"%s: Channel %d\\n\", __func__, hc->hc_num);\n+\n+\thctsiz.d32 = 0;\n+\thctsiz.b.dopng = 1;\n+\thctsiz.b.pktcnt = 1;\n+\tDWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32);\n+\n+\thcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);\n+\thcchar.b.chen = 1;\n+\thcchar.b.chdis = 0;\n+\tDWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);\n+}\n+\n+/*\n+ * This function writes a packet into the Tx FIFO associated with the Host\n+ * Channel. For a channel associated with a non-periodic EP, the non-periodic\n+ * Tx FIFO is written. For a channel associated with a periodic EP, the\n+ * periodic Tx FIFO is written. This function should only be called in Slave\n+ * mode.\n+ *\n+ * Upon return the xfer_buff and xfer_count fields in _hc are incremented by\n+ * then number of bytes written to the Tx FIFO.\n+ */\n+void dwc_otg_hc_write_packet(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)\n+{\n+\tuint32_t i;\n+\tuint32_t remaining_count;\n+\tuint32_t byte_count;\n+\tuint32_t dword_count;\n+\n+\tuint32_t *data_buff = (uint32_t *) (hc->xfer_buff);\n+\tuint32_t *data_fifo = core_if->data_fifo[hc->hc_num];\n+\n+\tremaining_count = hc->xfer_len - hc->xfer_count;\n+\tif (remaining_count > hc->max_packet) {\n+\t\tbyte_count = hc->max_packet;\n+\t} else {\n+\t\tbyte_count = remaining_count;\n+\t}\n+\n+\tdword_count = (byte_count + 3) / 4;\n+\n+\tif ((((unsigned long)data_buff) & 0x3) == 0) {\n+\t\t/* xfer_buff is DWORD aligned. */\n+\t\tfor (i = 0; i < dword_count; i++, data_buff++) {\n+\t\t\tDWC_WRITE_REG32(data_fifo, *data_buff);\n+\t\t}\n+\t} else {\n+\t\t/* xfer_buff is not DWORD aligned. */\n+\t\tfor (i = 0; i < dword_count; i++, data_buff++) {\n+\t\t\tuint32_t data;\n+\t\t\tdata =\n+\t\t\t    (data_buff[0] | data_buff[1] << 8 | data_buff[2] <<\n+\t\t\t     16 | data_buff[3] << 24);\n+\t\t\tDWC_WRITE_REG32(data_fifo, data);\n+\t\t}\n+\t}\n+\n+\thc->xfer_count += byte_count;\n+\thc->xfer_buff += byte_count;\n+}\n+\n+/**\n+ * Gets the current USB frame number. This is the frame number from the last\n+ * SOF packet.\n+ */\n+uint32_t dwc_otg_get_frame_number(dwc_otg_core_if_t * core_if)\n+{\n+\tdsts_data_t dsts;\n+\tdsts.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);\n+\n+\t/* read current frame/microframe number from DSTS register */\n+\treturn dsts.b.soffn;\n+}\n+\n+/**\n+ * Calculates and gets the frame Interval value of HFIR register according PHY\n+ * type and speed.The application can modify a value of HFIR register only after\n+ * the Port Enable bit of the Host Port Control and Status register\n+ * (HPRT.PrtEnaPort) has been set.\n+*/\n+\n+uint32_t calc_frame_interval(dwc_otg_core_if_t * core_if)\n+{\n+\tgusbcfg_data_t usbcfg;\n+\thwcfg2_data_t hwcfg2;\n+\thprt0_data_t hprt0;\n+\tint clock = 60;\t\t// default value\n+\tusbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);\n+\thwcfg2.d32 = DWC_READ_REG32(&core_if->core_global_regs->ghwcfg2);\n+\thprt0.d32 = DWC_READ_REG32(core_if->host_if->hprt0);\n+\tif (!usbcfg.b.physel && usbcfg.b.ulpi_utmi_sel && !usbcfg.b.phyif)\n+\t\tclock = 60;\n+\tif (usbcfg.b.physel && hwcfg2.b.fs_phy_type == 3)\n+\t\tclock = 48;\n+\tif (!usbcfg.b.phylpwrclksel && !usbcfg.b.physel &&\n+\t    !usbcfg.b.ulpi_utmi_sel && usbcfg.b.phyif)\n+\t\tclock = 30;\n+\tif (!usbcfg.b.phylpwrclksel && !usbcfg.b.physel &&\n+\t    !usbcfg.b.ulpi_utmi_sel && !usbcfg.b.phyif)\n+\t\tclock = 60;\n+\tif (usbcfg.b.phylpwrclksel && !usbcfg.b.physel &&\n+\t    !usbcfg.b.ulpi_utmi_sel && usbcfg.b.phyif)\n+\t\tclock = 48;\n+\tif (usbcfg.b.physel && !usbcfg.b.phyif && hwcfg2.b.fs_phy_type == 2)\n+\t\tclock = 48;\n+\tif (usbcfg.b.physel && hwcfg2.b.fs_phy_type == 1)\n+\t\tclock = 48;\n+\tif (hprt0.b.prtspd == 0)\n+\t\t/* High speed case */\n+\t\treturn 125 * clock - 1;\n+\telse\n+\t\t/* FS/LS case */\n+\t\treturn 1000 * clock - 1;\n+}\n+\n+/**\n+ * This function reads a setup packet from the Rx FIFO into the destination\n+ * buffer. This function is called from the Rx Status Queue Level (RxStsQLvl)\n+ * Interrupt routine when a SETUP packet has been received in Slave mode.\n+ *\n+ * @param core_if Programming view of DWC_otg controller.\n+ * @param dest Destination buffer for packet data.\n+ */\n+void dwc_otg_read_setup_packet(dwc_otg_core_if_t * core_if, uint32_t * dest)\n+{\n+\tdevice_grxsts_data_t status;\n+\t/* Get the 8 bytes of a setup transaction data */\n+\n+\t/* Pop 2 DWORDS off the receive data FIFO into memory */\n+\tdest[0] = DWC_READ_REG32(core_if->data_fifo[0]);\n+\tdest[1] = DWC_READ_REG32(core_if->data_fifo[0]);\n+\tif (core_if->snpsid >= OTG_CORE_REV_3_00a) {\n+\t\tstatus.d32 =\n+\t\t    DWC_READ_REG32(&core_if->core_global_regs->grxstsp);\n+\t\tDWC_DEBUGPL(DBG_ANY,\n+\t\t\t    \"EP:%d BCnt:%d \" \"pktsts:%x Frame:%d(0x%0x)\\n\",\n+\t\t\t    status.b.epnum, status.b.bcnt, status.b.pktsts,\n+\t\t\t    status.b.fn, status.b.fn);\n+\t}\n+}\n+\n+/**\n+ * This function enables EP0 OUT to receive SETUP packets and configures EP0\n+ * IN for transmitting packets. It is normally called when the\n+ * \"Enumeration Done\" interrupt occurs.\n+ *\n+ * @param core_if Programming view of DWC_otg controller.\n+ * @param ep The EP0 data.\n+ */\n+void dwc_otg_ep0_activate(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)\n+{\n+\tdwc_otg_dev_if_t *dev_if = core_if->dev_if;\n+\tdsts_data_t dsts;\n+\tdepctl_data_t diepctl;\n+\tdepctl_data_t doepctl;\n+\tdctl_data_t dctl = {.d32 = 0 };\n+\n+\tep->stp_rollover = 0;\n+\t/* Read the Device Status and Endpoint 0 Control registers */\n+\tdsts.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dsts);\n+\tdiepctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[0]->diepctl);\n+\tdoepctl.d32 = DWC_READ_REG32(&dev_if->out_ep_regs[0]->doepctl);\n+\n+\t/* Set the MPS of the IN EP based on the enumeration speed */\n+\tswitch (dsts.b.enumspd) {\n+\tcase DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ:\n+\tcase DWC_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ:\n+\tcase DWC_DSTS_ENUMSPD_FS_PHY_48MHZ:\n+\t\tdiepctl.b.mps = DWC_DEP0CTL_MPS_64;\n+\t\tbreak;\n+\tcase DWC_DSTS_ENUMSPD_LS_PHY_6MHZ:\n+\t\tdiepctl.b.mps = DWC_DEP0CTL_MPS_8;\n+\t\tbreak;\n+\t}\n+\n+\tDWC_WRITE_REG32(&dev_if->in_ep_regs[0]->diepctl, diepctl.d32);\n+\n+\t/* Enable OUT EP for receive */\n+\tif (core_if->snpsid <= OTG_CORE_REV_2_94a) {\n+\tdoepctl.b.epena = 1;\n+\tDWC_WRITE_REG32(&dev_if->out_ep_regs[0]->doepctl, doepctl.d32);\n+\t}\n+#ifdef VERBOSE\n+\tDWC_DEBUGPL(DBG_PCDV, \"doepctl0=%0x\\n\",\n+\t\t    DWC_READ_REG32(&dev_if->out_ep_regs[0]->doepctl));\n+\tDWC_DEBUGPL(DBG_PCDV, \"diepctl0=%0x\\n\",\n+\t\t    DWC_READ_REG32(&dev_if->in_ep_regs[0]->diepctl));\n+#endif\n+\tdctl.b.cgnpinnak = 1;\n+\n+\tDWC_MODIFY_REG32(&dev_if->dev_global_regs->dctl, dctl.d32, dctl.d32);\n+\tDWC_DEBUGPL(DBG_PCDV, \"dctl=%0x\\n\",\n+\t\t    DWC_READ_REG32(&dev_if->dev_global_regs->dctl));\n+\n+}\n+\n+/**\n+ * This function activates an EP.  The Device EP control register for\n+ * the EP is configured as defined in the ep structure. Note: This\n+ * function is not used for EP0.\n+ *\n+ * @param core_if Programming view of DWC_otg controller.\n+ * @param ep The EP to activate.\n+ */\n+void dwc_otg_ep_activate(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)\n+{\n+\tdwc_otg_dev_if_t *dev_if = core_if->dev_if;\n+\tdepctl_data_t depctl;\n+\tvolatile uint32_t *addr;\n+\tdaint_data_t daintmsk = {.d32 = 0 };\n+\tdcfg_data_t dcfg;\n+\tuint8_t i;\n+\n+\tDWC_DEBUGPL(DBG_PCDV, \"%s() EP%d-%s\\n\", __func__, ep->num,\n+\t\t    (ep->is_in ? \"IN\" : \"OUT\"));\n+\n+#ifdef DWC_UTE_PER_IO\n+\tep->xiso_frame_num = 0xFFFFFFFF;\n+\tep->xiso_active_xfers = 0;\n+\tep->xiso_queued_xfers = 0;\n+#endif\n+\t/* Read DEPCTLn register */\n+\tif (ep->is_in == 1) {\n+\t\taddr = &dev_if->in_ep_regs[ep->num]->diepctl;\n+\t\tdaintmsk.ep.in = 1 << ep->num;\n+\t} else {\n+\t\taddr = &dev_if->out_ep_regs[ep->num]->doepctl;\n+\t\tdaintmsk.ep.out = 1 << ep->num;\n+\t}\n+\n+\t/* If the EP is already active don't change the EP Control\n+\t * register. */\n+\tdepctl.d32 = DWC_READ_REG32(addr);\n+\tif (!depctl.b.usbactep) {\n+\t\tdepctl.b.mps = ep->maxpacket;\n+\t\tdepctl.b.eptype = ep->type;\n+\t\tdepctl.b.txfnum = ep->tx_fifo_num;\n+\n+\t\tif (ep->type == DWC_OTG_EP_TYPE_ISOC) {\n+\t\t\tdepctl.b.setd0pid = 1;\t// ???\n+\t\t} else {\n+\t\t\tdepctl.b.setd0pid = 1;\n+\t\t}\n+\t\tdepctl.b.usbactep = 1;\n+\n+\t\t/* Update nextep_seq array and EPMSCNT in DCFG*/\n+\t\tif (!(depctl.b.eptype & 1) && (ep->is_in == 1)) {\t// NP IN EP\n+\t\t\tfor (i = 0; i <= core_if->dev_if->num_in_eps; i++) {\n+\t\t\t\tif (core_if->nextep_seq[i] == core_if->first_in_nextep_seq)\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t\tcore_if->nextep_seq[i] = ep->num;\n+\t\t\tcore_if->nextep_seq[ep->num] = core_if->first_in_nextep_seq;\n+\t\t\tdepctl.b.nextep = core_if->nextep_seq[ep->num];\n+\t\t\tdcfg.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dcfg);\n+\t\t\tdcfg.b.epmscnt++;\n+\t\t\tDWC_WRITE_REG32(&dev_if->dev_global_regs->dcfg, dcfg.d32);\n+\n+\t\t\tDWC_DEBUGPL(DBG_PCDV,\n+\t\t\t\t    \"%s first_in_nextep_seq= %2d; nextep_seq[]:\\n\",\n+\t\t\t\t__func__, core_if->first_in_nextep_seq);\n+\t\t\tfor (i=0; i <= core_if->dev_if->num_in_eps; i++) {\n+\t\t\t\tDWC_DEBUGPL(DBG_PCDV, \"%2d\\n\",\n+\t\t\t\t\t    core_if->nextep_seq[i]);\n+\t\t\t}\n+\n+\t\t}\n+\n+\n+\t\tDWC_WRITE_REG32(addr, depctl.d32);\n+\t\tDWC_DEBUGPL(DBG_PCDV, \"DEPCTL=%08x\\n\", DWC_READ_REG32(addr));\n+\t}\n+\n+\t/* Enable the Interrupt for this EP */\n+\tif (core_if->multiproc_int_enable) {\n+\t\tif (ep->is_in == 1) {\n+\t\t\tdiepmsk_data_t diepmsk = {.d32 = 0 };\n+\t\t\tdiepmsk.b.xfercompl = 1;\n+\t\t\tdiepmsk.b.timeout = 1;\n+\t\t\tdiepmsk.b.epdisabled = 1;\n+\t\t\tdiepmsk.b.ahberr = 1;\n+\t\t\tdiepmsk.b.intknepmis = 1;\n+\t\t\tif (!core_if->en_multiple_tx_fifo && core_if->dma_enable)\n+\t\t\t\tdiepmsk.b.intknepmis = 0;\n+\t\t\tdiepmsk.b.txfifoundrn = 1;\t//?????\n+\t\t\tif (ep->type == DWC_OTG_EP_TYPE_ISOC) {\n+\t\t\t\tdiepmsk.b.nak = 1;\n+\t\t\t}\n+\n+\n+\n+/*\n+\t\t\tif (core_if->dma_desc_enable) {\n+\t\t\t\tdiepmsk.b.bna = 1;\n+\t\t\t}\n+*/\n+/*\n+\t\t\tif (core_if->dma_enable) {\n+\t\t\t\tdoepmsk.b.nak = 1;\n+\t\t\t}\n+*/\n+\t\t\tDWC_WRITE_REG32(&dev_if->dev_global_regs->\n+\t\t\t\t\tdiepeachintmsk[ep->num], diepmsk.d32);\n+\n+\t\t} else {\n+\t\t\tdoepmsk_data_t doepmsk = {.d32 = 0 };\n+\t\t\tdoepmsk.b.xfercompl = 1;\n+\t\t\tdoepmsk.b.ahberr = 1;\n+\t\t\tdoepmsk.b.epdisabled = 1;\n+\t\t\tif (ep->type == DWC_OTG_EP_TYPE_ISOC)\n+\t\t\t\tdoepmsk.b.outtknepdis = 1;\n+\n+/*\n+\n+\t\t\tif (core_if->dma_desc_enable) {\n+\t\t\t\tdoepmsk.b.bna = 1;\n+\t\t\t}\n+*/\n+/*\n+\t\t\tdoepmsk.b.babble = 1;\n+\t\t\tdoepmsk.b.nyet = 1;\n+\t\t\tdoepmsk.b.nak = 1;\n+*/\n+\t\t\tDWC_WRITE_REG32(&dev_if->dev_global_regs->\n+\t\t\t\t\tdoepeachintmsk[ep->num], doepmsk.d32);\n+\t\t}\n+\t\tDWC_MODIFY_REG32(&dev_if->dev_global_regs->deachintmsk,\n+\t\t\t\t 0, daintmsk.d32);\n+\t} else {\n+\t\tif (ep->type == DWC_OTG_EP_TYPE_ISOC) {\n+\t\t\tif (ep->is_in) {\n+\t\t\t\tdiepmsk_data_t diepmsk = {.d32 = 0 };\n+\t\t\t\tdiepmsk.b.nak = 1;\n+\t\t\t\tDWC_MODIFY_REG32(&dev_if->dev_global_regs->diepmsk, 0, diepmsk.d32);\n+\t\t\t} else {\n+\t\t\t\tdoepmsk_data_t doepmsk = {.d32 = 0 };\n+\t\t\t\tdoepmsk.b.outtknepdis = 1;\n+\t\t\t\tDWC_MODIFY_REG32(&dev_if->dev_global_regs->doepmsk, 0, doepmsk.d32);\n+\t\t\t}\n+\t\t}\n+\t\tDWC_MODIFY_REG32(&dev_if->dev_global_regs->daintmsk,\n+\t\t\t\t 0, daintmsk.d32);\n+\t}\n+\n+\tDWC_DEBUGPL(DBG_PCDV, \"DAINTMSK=%0x\\n\",\n+\t\t    DWC_READ_REG32(&dev_if->dev_global_regs->daintmsk));\n+\n+\tep->stall_clear_flag = 0;\n+\n+\treturn;\n+}\n+\n+/**\n+ * This function deactivates an EP. This is done by clearing the USB Active\n+ * EP bit in the Device EP control register. Note: This function is not used\n+ * for EP0. EP0 cannot be deactivated.\n+ *\n+ * @param core_if Programming view of DWC_otg controller.\n+ * @param ep The EP to deactivate.\n+ */\n+void dwc_otg_ep_deactivate(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)\n+{\n+\tdepctl_data_t depctl = {.d32 = 0 };\n+\tvolatile uint32_t *addr;\n+\tdaint_data_t daintmsk = {.d32 = 0 };\n+\tdcfg_data_t dcfg;\n+\tuint8_t i = 0;\n+\n+#ifdef DWC_UTE_PER_IO\n+\tep->xiso_frame_num = 0xFFFFFFFF;\n+\tep->xiso_active_xfers = 0;\n+\tep->xiso_queued_xfers = 0;\n+#endif\n+\n+\t/* Read DEPCTLn register */\n+\tif (ep->is_in == 1) {\n+\t\taddr = &core_if->dev_if->in_ep_regs[ep->num]->diepctl;\n+\t\tdaintmsk.ep.in = 1 << ep->num;\n+\t} else {\n+\t\taddr = &core_if->dev_if->out_ep_regs[ep->num]->doepctl;\n+\t\tdaintmsk.ep.out = 1 << ep->num;\n+\t}\n+\n+\tdepctl.d32 = DWC_READ_REG32(addr);\n+\n+\tdepctl.b.usbactep = 0;\n+\n+\t/* Update nextep_seq array and EPMSCNT in DCFG*/\n+\tif (!(depctl.b.eptype & 1) && ep->is_in == 1) {\t// NP EP IN\n+\t\tfor (i = 0; i <= core_if->dev_if->num_in_eps; i++) {\n+\t\t\tif (core_if->nextep_seq[i] == ep->num)\n+\t\t\tbreak;\n+\t\t}\n+\t\tcore_if->nextep_seq[i] = core_if->nextep_seq[ep->num];\n+\t\tif (core_if->first_in_nextep_seq == ep->num)\n+\t\t\tcore_if->first_in_nextep_seq = i;\n+\t\tcore_if->nextep_seq[ep->num] = 0xff;\n+\t\tdepctl.b.nextep = 0;\n+\t\tdcfg.d32 =\n+\t\t    DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg);\n+\t\tdcfg.b.epmscnt--;\n+\t\tDWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg,\n+\t\t\t\tdcfg.d32);\n+\n+\t\tDWC_DEBUGPL(DBG_PCDV,\n+\t\t\t    \"%s first_in_nextep_seq= %2d; nextep_seq[]:\\n\",\n+\t\t\t\t__func__, core_if->first_in_nextep_seq);\n+\t\t\tfor (i=0; i <= core_if->dev_if->num_in_eps; i++) {\n+\t\t\t\tDWC_DEBUGPL(DBG_PCDV, \"%2d\\n\", core_if->nextep_seq[i]);\n+\t\t\t}\n+\t}\n+\n+\tif (ep->is_in == 1)\n+\t\tdepctl.b.txfnum = 0;\n+\n+\tif (core_if->dma_desc_enable)\n+\t\tdepctl.b.epdis = 1;\n+\n+\tDWC_WRITE_REG32(addr, depctl.d32);\n+\tdepctl.d32 = DWC_READ_REG32(addr);\n+\tif (core_if->dma_enable && ep->type == DWC_OTG_EP_TYPE_ISOC\n+\t    && depctl.b.epena) {\n+\t\tdepctl_data_t depctl = {.d32 = 0};\n+\t\tif (ep->is_in) {\n+\t\t\tdiepint_data_t diepint = {.d32 = 0};\n+\n+\t\t\tdepctl.b.snak = 1;\n+\t\t\tDWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[ep->num]->\n+\t\t\t\t\tdiepctl, depctl.d32);\n+\t\t\tdo {\n+\t\t\t\tdwc_udelay(10);\n+\t\t\t\tdiepint.d32 =\n+\t\t\t\t    DWC_READ_REG32(&core_if->\n+\t\t\t\t\t\t   dev_if->in_ep_regs[ep->num]->\n+\t\t\t\t\t\t   diepint);\n+\t\t\t} while (!diepint.b.inepnakeff);\n+\t\t\tdiepint.b.inepnakeff = 1;\n+\t\t\tDWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[ep->num]->\n+\t\t\t\t\tdiepint, diepint.d32);\n+\t\t\tdepctl.d32 = 0;\n+\t\t\tdepctl.b.epdis = 1;\n+\t\t\tDWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[ep->num]->\n+\t\t\t\t\tdiepctl, depctl.d32);\n+\t\t\tdo {\n+\t\t\t\tdwc_udelay(10);\n+\t\t\t\tdiepint.d32 =\n+\t\t\t\t    DWC_READ_REG32(&core_if->\n+\t\t\t\t\t\t   dev_if->in_ep_regs[ep->num]->\n+\t\t\t\t\t\t   diepint);\n+\t\t\t} while (!diepint.b.epdisabled);\n+\t\t\tdiepint.b.epdisabled = 1;\n+\t\t\tDWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[ep->num]->\n+\t\t\t\t\tdiepint, diepint.d32);\n+\t\t} else {\n+\t\t\tdctl_data_t dctl = {.d32 = 0};\n+\t\t\tgintmsk_data_t gintsts = {.d32 = 0};\n+\t\t\tdoepint_data_t doepint = {.d32 = 0};\n+\t\t\tdctl.b.sgoutnak = 1;\n+\t\t\tDWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->\n+\t\t\t\t\t dctl, 0, dctl.d32);\n+\t\t\tdo {\n+\t\t\t\tdwc_udelay(10);\n+\t\t\t\tgintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts);\n+\t\t\t} while (!gintsts.b.goutnakeff);\n+\t\t\tgintsts.d32 = 0;\n+\t\t\tgintsts.b.goutnakeff = 1;\n+\t\t\tDWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);\n+\n+\t\t\tdepctl.d32 = 0;\n+\t\t\tdepctl.b.epdis = 1;\n+\t\t\tdepctl.b.snak = 1;\n+\t\t\tDWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[ep->num]->doepctl, depctl.d32);\n+\t\t\tdo\n+\t\t\t{\n+\t\t\t\tdwc_udelay(10);\n+\t\t\t\tdoepint.d32 = DWC_READ_REG32(&core_if->dev_if->\n+\t\t\t\t\t\t\t\t\t\t\tout_ep_regs[ep->num]->doepint);\n+\t\t\t} while (!doepint.b.epdisabled);\n+\n+\t\t\tdoepint.b.epdisabled = 1;\n+\t\t\tDWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[ep->num]->doepint, doepint.d32);\n+\n+\t\t\tdctl.d32 = 0;\n+\t\t\tdctl.b.cgoutnak = 1;\n+\t\t\tDWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0, dctl.d32);\n+\t\t}\n+\t}\n+\n+\t/* Disable the Interrupt for this EP */\n+\tif (core_if->multiproc_int_enable) {\n+\t\tDWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->deachintmsk,\n+\t\t\t\t daintmsk.d32, 0);\n+\n+\t\tif (ep->is_in == 1) {\n+\t\t\tDWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->\n+\t\t\t\t\tdiepeachintmsk[ep->num], 0);\n+\t\t} else {\n+\t\t\tDWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->\n+\t\t\t\t\tdoepeachintmsk[ep->num], 0);\n+\t\t}\n+\t} else {\n+\t\tDWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->daintmsk,\n+\t\t\t\t daintmsk.d32, 0);\n+\t}\n+\n+}\n+\n+/**\n+ * This function initializes dma descriptor chain.\n+ *\n+ * @param core_if Programming view of DWC_otg controller.\n+ * @param ep The EP to start the transfer on.\n+ */\n+static void init_dma_desc_chain(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)\n+{\n+\tdwc_otg_dev_dma_desc_t *dma_desc;\n+\tuint32_t offset;\n+\tuint32_t xfer_est;\n+\tint i;\n+\tunsigned maxxfer_local, total_len;\n+\n+\tif (!ep->is_in && ep->type == DWC_OTG_EP_TYPE_INTR &&\n+\t\t\t\t\t(ep->maxpacket%4)) {\n+\t\tmaxxfer_local = ep->maxpacket;\n+\t\ttotal_len = ep->xfer_len;\n+\t} else {\n+\t\tmaxxfer_local = ep->maxxfer;\n+\t\ttotal_len = ep->total_len;\n+\t}\n+\n+\tep->desc_cnt = (total_len / maxxfer_local) +\n+            ((total_len % maxxfer_local) ? 1 : 0);\n+\n+\tif (!ep->desc_cnt)\n+\t\tep->desc_cnt = 1;\n+\n+\tif (ep->desc_cnt > MAX_DMA_DESC_CNT)\n+\t\tep->desc_cnt = MAX_DMA_DESC_CNT;\n+\n+\tdma_desc = ep->desc_addr;\n+\tif (maxxfer_local == ep->maxpacket) {\n+\t\tif ((total_len % maxxfer_local) &&\n+\t\t\t\t(total_len/maxxfer_local < MAX_DMA_DESC_CNT)) {\n+\t\t\txfer_est = (ep->desc_cnt - 1) * maxxfer_local +\n+\t\t\t\t\t(total_len % maxxfer_local);\n+\t\t} else\n+\t\t\txfer_est = ep->desc_cnt * maxxfer_local;\n+\t} else\n+\t\txfer_est = total_len;\n+\toffset = 0;\n+\tfor (i = 0; i < ep->desc_cnt; ++i) {\n+\t\t/** DMA Descriptor Setup */\n+\t\tif (xfer_est > maxxfer_local) {\n+\t\t\tdma_desc->status.b.bs = BS_HOST_BUSY;\n+\t\t\tdma_desc->status.b.l = 0;\n+\t\t\tdma_desc->status.b.ioc = 0;\n+\t\t\tdma_desc->status.b.sp = 0;\n+\t\t\tdma_desc->status.b.bytes = maxxfer_local;\n+\t\t\tdma_desc->buf = ep->dma_addr + offset;\n+\t\t\tdma_desc->status.b.sts = 0;\n+\t\t\tdma_desc->status.b.bs = BS_HOST_READY;\n+\n+\t\t\txfer_est -= maxxfer_local;\n+\t\t\toffset += maxxfer_local;\n+\t\t} else {\n+\t\t\tdma_desc->status.b.bs = BS_HOST_BUSY;\n+\t\t\tdma_desc->status.b.l = 1;\n+\t\t\tdma_desc->status.b.ioc = 1;\n+\t\t\tif (ep->is_in) {\n+\t\t\t\tdma_desc->status.b.sp =\n+\t\t\t\t    (xfer_est %\n+\t\t\t\t     ep->maxpacket) ? 1 : ((ep->\n+\t\t\t\t\t\t\t    sent_zlp) ? 1 : 0);\n+\t\t\t\tdma_desc->status.b.bytes = xfer_est;\n+\t\t\t} else {\n+\t\t\t\tif (maxxfer_local == ep->maxpacket)\n+\t\t\t\t\tdma_desc->status.b.bytes = xfer_est;\n+\t\t\t\telse\n+\t\t\t\t\tdma_desc->status.b.bytes =\n+\t\t\t\t\t\txfer_est + ((4 - (xfer_est & 0x3)) & 0x3);\n+\t\t\t}\n+\n+\t\t\tdma_desc->buf = ep->dma_addr + offset;\n+\t\t\tdma_desc->status.b.sts = 0;\n+\t\t\tdma_desc->status.b.bs = BS_HOST_READY;\n+\t\t}\n+\t\tdma_desc++;\n+\t}\n+}\n+/**\n+ * This function is called when to write ISOC data into appropriate dedicated\n+ * periodic FIFO.\n+ */\n+static int32_t write_isoc_tx_fifo(dwc_otg_core_if_t * core_if, dwc_ep_t * dwc_ep)\n+{\n+\tdwc_otg_dev_if_t *dev_if = core_if->dev_if;\n+\tdwc_otg_dev_in_ep_regs_t *ep_regs;\n+\tdtxfsts_data_t txstatus = {.d32 = 0 };\n+\tuint32_t len = 0;\n+\tint epnum = dwc_ep->num;\n+\tint dwords;\n+\n+\tDWC_DEBUGPL(DBG_PCD, \"Dedicated TxFifo Empty: %d \\n\", epnum);\n+\n+\tep_regs = core_if->dev_if->in_ep_regs[epnum];\n+\n+\tlen = dwc_ep->xfer_len - dwc_ep->xfer_count;\n+\n+\tif (len > dwc_ep->maxpacket) {\n+\t\tlen = dwc_ep->maxpacket;\n+\t}\n+\n+\tdwords = (len + 3) / 4;\n+\n+\t/* While there is space in the queue and space in the FIFO and\n+\t * More data to tranfer, Write packets to the Tx FIFO */\n+\ttxstatus.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dtxfsts);\n+\tDWC_DEBUGPL(DBG_PCDV, \"b4 dtxfsts[%d]=0x%08x\\n\", epnum, txstatus.d32);\n+\n+\twhile (txstatus.b.txfspcavail > dwords &&\n+\t       dwc_ep->xfer_count < dwc_ep->xfer_len && dwc_ep->xfer_len != 0) {\n+\t\t/* Write the FIFO */\n+\t\tdwc_otg_ep_write_packet(core_if, dwc_ep, 0);\n+\n+\t\tlen = dwc_ep->xfer_len - dwc_ep->xfer_count;\n+\t\tif (len > dwc_ep->maxpacket) {\n+\t\t\tlen = dwc_ep->maxpacket;\n+\t\t}\n+\n+\t\tdwords = (len + 3) / 4;\n+\t\ttxstatus.d32 =\n+\t\t    DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dtxfsts);\n+\t\tDWC_DEBUGPL(DBG_PCDV, \"dtxfsts[%d]=0x%08x\\n\", epnum,\n+\t\t\t    txstatus.d32);\n+\t}\n+\n+\tDWC_DEBUGPL(DBG_PCDV, \"b4 dtxfsts[%d]=0x%08x\\n\", epnum,\n+\t\t    DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dtxfsts));\n+\n+\treturn 1;\n+}\n+/**\n+ * This function does the setup for a data transfer for an EP and\n+ * starts the transfer. For an IN transfer, the packets will be\n+ * loaded into the appropriate Tx FIFO in the ISR. For OUT transfers,\n+ * the packets are unloaded from the Rx FIFO in the ISR.  the ISR.\n+ *\n+ * @param core_if Programming view of DWC_otg controller.\n+ * @param ep The EP to start the transfer on.\n+ */\n+\n+void dwc_otg_ep_start_transfer(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)\n+{\n+\tdepctl_data_t depctl;\n+\tdeptsiz_data_t deptsiz;\n+\tgintmsk_data_t intr_mask = {.d32 = 0 };\n+\n+\tDWC_DEBUGPL((DBG_PCDV | DBG_CILV), \"%s()\\n\", __func__);\n+\tDWC_DEBUGPL(DBG_PCD, \"ep%d-%s xfer_len=%d xfer_cnt=%d \"\n+\t\t    \"xfer_buff=%p start_xfer_buff=%p, total_len = %d\\n\",\n+\t\t    ep->num, (ep->is_in ? \"IN\" : \"OUT\"), ep->xfer_len,\n+\t\t    ep->xfer_count, ep->xfer_buff, ep->start_xfer_buff,\n+\t\t    ep->total_len);\n+\t/* IN endpoint */\n+\tif (ep->is_in == 1) {\n+\t\tdwc_otg_dev_in_ep_regs_t *in_regs =\n+\t\t    core_if->dev_if->in_ep_regs[ep->num];\n+\n+\t\tgnptxsts_data_t gtxstatus;\n+\n+\t\tgtxstatus.d32 =\n+\t\t    DWC_READ_REG32(&core_if->core_global_regs->gnptxsts);\n+\n+\t\tif (core_if->en_multiple_tx_fifo == 0\n+\t\t    && gtxstatus.b.nptxqspcavail == 0 && !core_if->dma_enable) {\n+#ifdef DEBUG\n+\t\t\tDWC_PRINTF(\"TX Queue Full (0x%0x)\\n\", gtxstatus.d32);\n+#endif\n+\t\t\treturn;\n+\t\t}\n+\n+\t\tdepctl.d32 = DWC_READ_REG32(&(in_regs->diepctl));\n+\t\tdeptsiz.d32 = DWC_READ_REG32(&(in_regs->dieptsiz));\n+\n+\t\tif (ep->maxpacket > ep->maxxfer / MAX_PKT_CNT)\n+\t\t\tep->xfer_len += (ep->maxxfer < (ep->total_len - ep->xfer_len)) ?\n+\t\t\t\tep->maxxfer : (ep->total_len - ep->xfer_len);\n+\t\telse\n+\t\t\tep->xfer_len += (MAX_PKT_CNT * ep->maxpacket < (ep->total_len - ep->xfer_len)) ?\n+\t\t\t\t MAX_PKT_CNT * ep->maxpacket : (ep->total_len - ep->xfer_len);\n+\n+\n+\t\t/* Zero Length Packet? */\n+\t\tif ((ep->xfer_len - ep->xfer_count) == 0) {\n+\t\t\tdeptsiz.b.xfersize = 0;\n+\t\t\tdeptsiz.b.pktcnt = 1;\n+\t\t} else {\n+\t\t\t/* Program the transfer size and packet count\n+\t\t\t *      as follows: xfersize = N * maxpacket +\n+\t\t\t *      short_packet pktcnt = N + (short_packet\n+\t\t\t *      exist ? 1 : 0)\n+\t\t\t */\n+\t\t\tdeptsiz.b.xfersize = ep->xfer_len - ep->xfer_count;\n+\t\t\tdeptsiz.b.pktcnt =\n+\t\t\t    (ep->xfer_len - ep->xfer_count - 1 +\n+\t\t\t     ep->maxpacket) / ep->maxpacket;\n+\t\t\tif (deptsiz.b.pktcnt > MAX_PKT_CNT) {\n+\t\t\t\tdeptsiz.b.pktcnt = MAX_PKT_CNT;\n+\t\t\t\tdeptsiz.b.xfersize = deptsiz.b.pktcnt * ep->maxpacket;\n+\t\t\t}\n+\t\t\tif (ep->type == DWC_OTG_EP_TYPE_ISOC)\n+\t\t\t\tdeptsiz.b.mc = deptsiz.b.pktcnt;\n+\t\t}\n+\n+\t\t/* Write the DMA register */\n+\t\tif (core_if->dma_enable) {\n+\t\t\tif (core_if->dma_desc_enable == 0) {\n+\t\t\t\tif (ep->type != DWC_OTG_EP_TYPE_ISOC)\n+\t\t\t\t\tdeptsiz.b.mc = 1;\n+\t\t\t\tDWC_WRITE_REG32(&in_regs->dieptsiz,\n+\t\t\t\t\t\tdeptsiz.d32);\n+\t\t\t\tDWC_WRITE_REG32(&(in_regs->diepdma),\n+\t\t\t\t\t\t(uint32_t) ep->dma_addr);\n+\t\t\t} else {\n+#ifdef DWC_UTE_CFI\n+\t\t\t\t/* The descriptor chain should be already initialized by now */\n+\t\t\t\tif (ep->buff_mode != BM_STANDARD) {\n+\t\t\t\t\tDWC_WRITE_REG32(&in_regs->diepdma,\n+\t\t\t\t\t\t\tep->descs_dma_addr);\n+\t\t\t\t} else {\n+#endif\n+\t\t\t\t\tinit_dma_desc_chain(core_if, ep);\n+\t\t\t\t/** DIEPDMAn Register write */\n+\t\t\t\t\tDWC_WRITE_REG32(&in_regs->diepdma,\n+\t\t\t\t\t\t\tep->dma_desc_addr);\n+#ifdef DWC_UTE_CFI\n+\t\t\t\t}\n+#endif\n+\t\t\t}\n+\t\t} else {\n+\t\t\tDWC_WRITE_REG32(&in_regs->dieptsiz, deptsiz.d32);\n+\t\t\tif (ep->type != DWC_OTG_EP_TYPE_ISOC) {\n+\t\t\t\t/**\n+\t\t\t\t * Enable the Non-Periodic Tx FIFO empty interrupt,\n+\t\t\t\t * or the Tx FIFO epmty interrupt in dedicated Tx FIFO mode,\n+\t\t\t\t * the data will be written into the fifo by the ISR.\n+\t\t\t\t */\n+\t\t\t\tif (core_if->en_multiple_tx_fifo == 0) {\n+\t\t\t\t\tintr_mask.b.nptxfempty = 1;\n+\t\t\t\t\tDWC_MODIFY_REG32\n+\t\t\t\t\t    (&core_if->core_global_regs->gintmsk,\n+\t\t\t\t\t     intr_mask.d32, intr_mask.d32);\n+\t\t\t\t} else {\n+\t\t\t\t\t/* Enable the Tx FIFO Empty Interrupt for this EP */\n+\t\t\t\t\tif (ep->xfer_len > 0) {\n+\t\t\t\t\t\tuint32_t fifoemptymsk = 0;\n+\t\t\t\t\t\tfifoemptymsk = 1 << ep->num;\n+\t\t\t\t\t\tDWC_MODIFY_REG32\n+\t\t\t\t\t\t    (&core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk,\n+\t\t\t\t\t\t     0, fifoemptymsk);\n+\n+\t\t\t\t\t}\n+\t\t\t\t}\n+\t\t\t}  else {\n+\t\t\t\t\t write_isoc_tx_fifo(core_if, ep);\n+\t\t\t}\n+\t\t}\n+\t\tif (!core_if->core_params->en_multiple_tx_fifo && core_if->dma_enable)\n+\t\t\tdepctl.b.nextep = core_if->nextep_seq[ep->num];\n+\n+\t\tif (ep->type == DWC_OTG_EP_TYPE_ISOC) {\n+\t\t\tdsts_data_t dsts = {.d32 = 0};\n+\t\t\tif (ep->bInterval == 1) {\n+\t\t\t\tdsts.d32 =\n+\t\t\t\t    DWC_READ_REG32(&core_if->dev_if->\n+\t\t\t\t\t\t   dev_global_regs->dsts);\n+\t\t\t\tep->frame_num = dsts.b.soffn + ep->bInterval;\n+\t\t\t\tif (ep->frame_num > 0x3FFF) {\n+\t\t\t\t\tep->frm_overrun = 1;\n+\t\t\t\t\tep->frame_num &= 0x3FFF;\n+\t\t\t\t} else\n+\t\t\t\t\tep->frm_overrun = 0;\n+\t\t\t\tif (ep->frame_num & 0x1) {\n+\t\t\t\t\tdepctl.b.setd1pid = 1;\n+\t\t\t\t} else {\n+\t\t\t\t\tdepctl.b.setd0pid = 1;\n+\t\t\t\t}\n+\t\t\t}\n+\t\t}\n+\t\t/* EP enable, IN data in FIFO */\n+\t\tdepctl.b.cnak = 1;\n+\t\tdepctl.b.epena = 1;\n+\t\tDWC_WRITE_REG32(&in_regs->diepctl, depctl.d32);\n+\n+\t} else {\n+\t\t/* OUT endpoint */\n+\t\tdwc_otg_dev_out_ep_regs_t *out_regs =\n+\t\t    core_if->dev_if->out_ep_regs[ep->num];\n+\n+\t\tdepctl.d32 = DWC_READ_REG32(&(out_regs->doepctl));\n+\t\tdeptsiz.d32 = DWC_READ_REG32(&(out_regs->doeptsiz));\n+\n+\t\tif (!core_if->dma_desc_enable) {\n+\t\t\tif (ep->maxpacket > ep->maxxfer / MAX_PKT_CNT)\n+\t\t\t\tep->xfer_len += (ep->maxxfer < (ep->total_len - ep->xfer_len)) ?\n+\t\t\t\tep->maxxfer : (ep->total_len - ep->xfer_len);\n+                else\n+\t\t\t\t\tep->xfer_len += (MAX_PKT_CNT * ep->maxpacket < (ep->total_len\n+\t\t\t\t\t- ep->xfer_len)) ? MAX_PKT_CNT * ep->maxpacket : (ep->total_len - ep->xfer_len);\n+\t\t}\n+\n+\t\t/* Program the transfer size and packet count as follows:\n+\t\t *\n+\t\t *      pktcnt = N\n+\t\t *      xfersize = N * maxpacket\n+\t\t */\n+\t\tif ((ep->xfer_len - ep->xfer_count) == 0) {\n+\t\t\t/* Zero Length Packet */\n+\t\t\tdeptsiz.b.xfersize = ep->maxpacket;\n+\t\t\tdeptsiz.b.pktcnt = 1;\n+\t\t} else {\n+\t\t\tdeptsiz.b.pktcnt =\n+\t\t\t    (ep->xfer_len - ep->xfer_count +\n+\t\t\t     (ep->maxpacket - 1)) / ep->maxpacket;\n+\t\t\tif (deptsiz.b.pktcnt > MAX_PKT_CNT) {\n+\t\t\t\tdeptsiz.b.pktcnt = MAX_PKT_CNT;\n+\t\t\t}\n+\t\t\tif (!core_if->dma_desc_enable) {\n+\t\t\t\tep->xfer_len =\n+\t\t\t\t\tdeptsiz.b.pktcnt * ep->maxpacket + ep->xfer_count;\n+\t\t\t}\n+\t\t\tdeptsiz.b.xfersize = ep->xfer_len - ep->xfer_count;\n+\t\t}\n+\n+\t\tDWC_DEBUGPL(DBG_PCDV, \"ep%d xfersize=%d pktcnt=%d\\n\",\n+\t\t\t    ep->num, deptsiz.b.xfersize, deptsiz.b.pktcnt);\n+\n+\t\tif (core_if->dma_enable) {\n+\t\t\tif (!core_if->dma_desc_enable) {\n+\t\t\t\tDWC_WRITE_REG32(&out_regs->doeptsiz,\n+\t\t\t\t\t\tdeptsiz.d32);\n+\n+\t\t\t\tDWC_WRITE_REG32(&(out_regs->doepdma),\n+\t\t\t\t\t\t(uint32_t) ep->dma_addr);\n+\t\t\t} else {\n+#ifdef DWC_UTE_CFI\n+\t\t\t\t/* The descriptor chain should be already initialized by now */\n+\t\t\t\tif (ep->buff_mode != BM_STANDARD) {\n+\t\t\t\t\tDWC_WRITE_REG32(&out_regs->doepdma,\n+\t\t\t\t\t\t\tep->descs_dma_addr);\n+\t\t\t\t} else {\n+#endif\n+\t\t\t\t\t/** This is used for interrupt out transfers*/\n+\t\t\t\t\tif (!ep->xfer_len)\n+\t\t\t\t\t\tep->xfer_len = ep->total_len;\n+\t\t\t\t\tinit_dma_desc_chain(core_if, ep);\n+\n+\t\t\t\t\tif (core_if->core_params->dev_out_nak) {\n+\t\t\t\t\t\tif (ep->type == DWC_OTG_EP_TYPE_BULK) {\n+\t\t\t\t\t\t\tdeptsiz.b.pktcnt = (ep->total_len +\n+\t\t\t\t\t\t\t\t(ep->maxpacket - 1)) / ep->maxpacket;\n+\t\t\t\t\t\t\tdeptsiz.b.xfersize = ep->total_len;\n+\t\t\t\t\t\t\t/* Remember initial value of doeptsiz */\n+\t\t\t\t\t\t\tcore_if->start_doeptsiz_val[ep->num] = deptsiz.d32;\n+\t\t\t\t\t\t\tDWC_WRITE_REG32(&out_regs->doeptsiz,\n+\t\t\t\t\t\t\t\tdeptsiz.d32);\n+\t\t\t\t\t\t}\n+\t\t\t\t\t}\n+\t\t\t\t/** DOEPDMAn Register write */\n+\t\t\t\t\tDWC_WRITE_REG32(&out_regs->doepdma,\n+\t\t\t\t\t\t\tep->dma_desc_addr);\n+#ifdef DWC_UTE_CFI\n+\t\t\t\t}\n+#endif\n+\t\t\t}\n+\t\t} else {\n+\t\t\tDWC_WRITE_REG32(&out_regs->doeptsiz, deptsiz.d32);\n+\t\t}\n+\n+\t\tif (ep->type == DWC_OTG_EP_TYPE_ISOC) {\n+\t\t\tdsts_data_t dsts = {.d32 = 0};\n+\t\t\tif (ep->bInterval == 1) {\n+\t\t\t\tdsts.d32 =\n+\t\t\t\t    DWC_READ_REG32(&core_if->dev_if->\n+\t\t\t\t\t\t   dev_global_regs->dsts);\n+\t\t\t\tep->frame_num = dsts.b.soffn + ep->bInterval;\n+\t\t\t\tif (ep->frame_num > 0x3FFF) {\n+\t\t\t\t\tep->frm_overrun = 1;\n+\t\t\t\t\tep->frame_num &= 0x3FFF;\n+\t\t\t\t} else\n+\t\t\t\t\tep->frm_overrun = 0;\n+\n+\t\t\t\tif (ep->frame_num & 0x1) {\n+\t\t\t\t\tdepctl.b.setd1pid = 1;\n+\t\t\t\t} else {\n+\t\t\t\t\tdepctl.b.setd0pid = 1;\n+\t\t\t\t}\n+\t\t\t}\n+\t\t}\n+\n+\t\t/* EP enable */\n+\t\tdepctl.b.cnak = 1;\n+\t\tdepctl.b.epena = 1;\n+\n+\t\tDWC_WRITE_REG32(&out_regs->doepctl, depctl.d32);\n+\n+\t\tDWC_DEBUGPL(DBG_PCD, \"DOEPCTL=%08x DOEPTSIZ=%08x\\n\",\n+\t\t\t    DWC_READ_REG32(&out_regs->doepctl),\n+\t\t\t    DWC_READ_REG32(&out_regs->doeptsiz));\n+\t\tDWC_DEBUGPL(DBG_PCD, \"DAINTMSK=%08x GINTMSK=%08x\\n\",\n+\t\t\t    DWC_READ_REG32(&core_if->dev_if->dev_global_regs->\n+\t\t\t\t\t   daintmsk),\n+\t\t\t    DWC_READ_REG32(&core_if->core_global_regs->\n+\t\t\t\t\t   gintmsk));\n+\n+\t\t/* Timer is scheduling only for out bulk transfers for\n+\t\t * \"Device DDMA OUT NAK Enhancement\" feature to inform user\n+\t\t * about received data payload in case of timeout\n+\t\t */\n+\t\tif (core_if->core_params->dev_out_nak) {\n+\t\t\tif (ep->type == DWC_OTG_EP_TYPE_BULK) {\n+\t\t\t\tcore_if->ep_xfer_info[ep->num].core_if = core_if;\n+\t\t\t\tcore_if->ep_xfer_info[ep->num].ep = ep;\n+\t\t\t\tcore_if->ep_xfer_info[ep->num].state = 1;\n+\n+\t\t\t\t/* Start a timer for this transfer. */\n+\t\t\t\tDWC_TIMER_SCHEDULE(core_if->ep_xfer_timer[ep->num], 10000);\n+\t\t\t}\n+\t\t}\n+\t}\n+}\n+\n+/**\n+ * This function setup a zero length transfer in Buffer DMA and\n+ * Slave modes for usb requests with zero field set\n+ *\n+ * @param core_if Programming view of DWC_otg controller.\n+ * @param ep The EP to start the transfer on.\n+ *\n+ */\n+void dwc_otg_ep_start_zl_transfer(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)\n+{\n+\n+\tdepctl_data_t depctl;\n+\tdeptsiz_data_t deptsiz;\n+\tgintmsk_data_t intr_mask = {.d32 = 0 };\n+\n+\tDWC_DEBUGPL((DBG_PCDV | DBG_CILV), \"%s()\\n\", __func__);\n+\tDWC_PRINTF(\"zero length transfer is called\\n\");\n+\n+\t/* IN endpoint */\n+\tif (ep->is_in == 1) {\n+\t\tdwc_otg_dev_in_ep_regs_t *in_regs =\n+\t\t    core_if->dev_if->in_ep_regs[ep->num];\n+\n+\t\tdepctl.d32 = DWC_READ_REG32(&(in_regs->diepctl));\n+\t\tdeptsiz.d32 = DWC_READ_REG32(&(in_regs->dieptsiz));\n+\n+\t\tdeptsiz.b.xfersize = 0;\n+\t\tdeptsiz.b.pktcnt = 1;\n+\n+\t\t/* Write the DMA register */\n+\t\tif (core_if->dma_enable) {\n+\t\t\tif (core_if->dma_desc_enable == 0) {\n+\t\t\t\tdeptsiz.b.mc = 1;\n+\t\t\t\tDWC_WRITE_REG32(&in_regs->dieptsiz,\n+\t\t\t\t\t\tdeptsiz.d32);\n+\t\t\t\tDWC_WRITE_REG32(&(in_regs->diepdma),\n+\t\t\t\t\t\t(uint32_t) ep->dma_addr);\n+\t\t\t}\n+\t\t} else {\n+\t\t\tDWC_WRITE_REG32(&in_regs->dieptsiz, deptsiz.d32);\n+\t\t\t/**\n+\t\t\t * Enable the Non-Periodic Tx FIFO empty interrupt,\n+\t\t\t * or the Tx FIFO epmty interrupt in dedicated Tx FIFO mode,\n+\t\t\t * the data will be written into the fifo by the ISR.\n+\t\t\t */\n+\t\t\tif (core_if->en_multiple_tx_fifo == 0) {\n+\t\t\t\tintr_mask.b.nptxfempty = 1;\n+\t\t\t\tDWC_MODIFY_REG32(&core_if->\n+\t\t\t\t\t\t core_global_regs->gintmsk,\n+\t\t\t\t\t\t intr_mask.d32, intr_mask.d32);\n+\t\t\t} else {\n+\t\t\t\t/* Enable the Tx FIFO Empty Interrupt for this EP */\n+\t\t\t\tif (ep->xfer_len > 0) {\n+\t\t\t\t\tuint32_t fifoemptymsk = 0;\n+\t\t\t\t\tfifoemptymsk = 1 << ep->num;\n+\t\t\t\t\tDWC_MODIFY_REG32(&core_if->\n+\t\t\t\t\t\t\t dev_if->dev_global_regs->dtknqr4_fifoemptymsk,\n+\t\t\t\t\t\t\t 0, fifoemptymsk);\n+\t\t\t\t}\n+\t\t\t}\n+\t\t}\n+\n+\t\tif (!core_if->core_params->en_multiple_tx_fifo && core_if->dma_enable)\n+\t\t\tdepctl.b.nextep = core_if->nextep_seq[ep->num];\n+\t\t/* EP enable, IN data in FIFO */\n+\t\tdepctl.b.cnak = 1;\n+\t\tdepctl.b.epena = 1;\n+\t\tDWC_WRITE_REG32(&in_regs->diepctl, depctl.d32);\n+\n+\t} else {\n+\t\t/* OUT endpoint */\n+\t\tdwc_otg_dev_out_ep_regs_t *out_regs =\n+\t\t    core_if->dev_if->out_ep_regs[ep->num];\n+\n+\t\tdepctl.d32 = DWC_READ_REG32(&(out_regs->doepctl));\n+\t\tdeptsiz.d32 = DWC_READ_REG32(&(out_regs->doeptsiz));\n+\n+\t\t/* Zero Length Packet */\n+\t\tdeptsiz.b.xfersize = ep->maxpacket;\n+\t\tdeptsiz.b.pktcnt = 1;\n+\n+\t\tif (core_if->dma_enable) {\n+\t\t\tif (!core_if->dma_desc_enable) {\n+\t\t\t\tDWC_WRITE_REG32(&out_regs->doeptsiz,\n+\t\t\t\t\t\tdeptsiz.d32);\n+\n+\t\t\t\tDWC_WRITE_REG32(&(out_regs->doepdma),\n+\t\t\t\t\t\t(uint32_t) ep->dma_addr);\n+\t\t\t}\n+\t\t} else {\n+\t\t\tDWC_WRITE_REG32(&out_regs->doeptsiz, deptsiz.d32);\n+\t\t}\n+\n+\t\t/* EP enable */\n+\t\tdepctl.b.cnak = 1;\n+\t\tdepctl.b.epena = 1;\n+\n+\t\tDWC_WRITE_REG32(&out_regs->doepctl, depctl.d32);\n+\n+\t}\n+}\n+\n+/**\n+ * This function does the setup for a data transfer for EP0 and starts\n+ * the transfer.  For an IN transfer, the packets will be loaded into\n+ * the appropriate Tx FIFO in the ISR. For OUT transfers, the packets are\n+ * unloaded from the Rx FIFO in the ISR.\n+ *\n+ * @param core_if Programming view of DWC_otg controller.\n+ * @param ep The EP0 data.\n+ */\n+void dwc_otg_ep0_start_transfer(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)\n+{\n+\tdepctl_data_t depctl;\n+\tdeptsiz0_data_t deptsiz;\n+\tgintmsk_data_t intr_mask = {.d32 = 0 };\n+\tdwc_otg_dev_dma_desc_t *dma_desc;\n+\n+\tDWC_DEBUGPL(DBG_PCD, \"ep%d-%s xfer_len=%d xfer_cnt=%d \"\n+\t\t    \"xfer_buff=%p start_xfer_buff=%p \\n\",\n+\t\t    ep->num, (ep->is_in ? \"IN\" : \"OUT\"), ep->xfer_len,\n+\t\t    ep->xfer_count, ep->xfer_buff, ep->start_xfer_buff);\n+\n+\tep->total_len = ep->xfer_len;\n+\n+\t/* IN endpoint */\n+\tif (ep->is_in == 1) {\n+\t\tdwc_otg_dev_in_ep_regs_t *in_regs =\n+\t\t    core_if->dev_if->in_ep_regs[0];\n+\n+\t\tgnptxsts_data_t gtxstatus;\n+\n+\t\tif (core_if->snpsid >= OTG_CORE_REV_3_00a) {\n+\t\t\tdepctl.d32 = DWC_READ_REG32(&in_regs->diepctl);\n+\t\t\tif (depctl.b.epena)\n+\t\t\t\treturn;\n+\t\t}\n+\n+\t\tgtxstatus.d32 =\n+\t\t    DWC_READ_REG32(&core_if->core_global_regs->gnptxsts);\n+\n+\t\t/* If dedicated FIFO every time flush fifo before enable ep*/\n+\t\tif (core_if->en_multiple_tx_fifo && core_if->snpsid >= OTG_CORE_REV_3_00a)\n+\t\t\tdwc_otg_flush_tx_fifo(core_if, ep->tx_fifo_num);\n+\n+\t\tif (core_if->en_multiple_tx_fifo == 0\n+\t\t    && gtxstatus.b.nptxqspcavail == 0\n+\t\t    && !core_if->dma_enable) {\n+#ifdef DEBUG\n+\t\t\tdeptsiz.d32 = DWC_READ_REG32(&in_regs->dieptsiz);\n+\t\t\tDWC_DEBUGPL(DBG_PCD, \"DIEPCTL0=%0x\\n\",\n+\t\t\t\t    DWC_READ_REG32(&in_regs->diepctl));\n+\t\t\tDWC_DEBUGPL(DBG_PCD, \"DIEPTSIZ0=%0x (sz=%d, pcnt=%d)\\n\",\n+\t\t\t\t    deptsiz.d32,\n+\t\t\t\t    deptsiz.b.xfersize, deptsiz.b.pktcnt);\n+\t\t\tDWC_PRINTF(\"TX Queue or FIFO Full (0x%0x)\\n\",\n+\t\t\t\t   gtxstatus.d32);\n+#endif\n+\t\t\treturn;\n+\t\t}\n+\n+\t\tdepctl.d32 = DWC_READ_REG32(&in_regs->diepctl);\n+\t\tdeptsiz.d32 = DWC_READ_REG32(&in_regs->dieptsiz);\n+\n+\t\t/* Zero Length Packet? */\n+\t\tif (ep->xfer_len == 0) {\n+\t\t\tdeptsiz.b.xfersize = 0;\n+\t\t\tdeptsiz.b.pktcnt = 1;\n+\t\t} else {\n+\t\t\t/* Program the transfer size and packet count\n+\t\t\t *      as follows: xfersize = N * maxpacket +\n+\t\t\t *      short_packet pktcnt = N + (short_packet\n+\t\t\t *      exist ? 1 : 0)\n+\t\t\t */\n+\t\t\tif (ep->xfer_len > ep->maxpacket) {\n+\t\t\t\tep->xfer_len = ep->maxpacket;\n+\t\t\t\tdeptsiz.b.xfersize = ep->maxpacket;\n+\t\t\t} else {\n+\t\t\t\tdeptsiz.b.xfersize = ep->xfer_len;\n+\t\t\t}\n+\t\t\tdeptsiz.b.pktcnt = 1;\n+\n+\t\t}\n+\t\tDWC_DEBUGPL(DBG_PCDV,\n+\t\t\t    \"IN len=%d  xfersize=%d pktcnt=%d [%08x]\\n\",\n+\t\t\t    ep->xfer_len, deptsiz.b.xfersize, deptsiz.b.pktcnt,\n+\t\t\t    deptsiz.d32);\n+\n+\t\t/* Write the DMA register */\n+\t\tif (core_if->dma_enable) {\n+\t\t\tif (core_if->dma_desc_enable == 0) {\n+\t\t\t\tDWC_WRITE_REG32(&in_regs->dieptsiz,\n+\t\t\t\t\t\tdeptsiz.d32);\n+\n+\t\t\t\tDWC_WRITE_REG32(&(in_regs->diepdma),\n+\t\t\t\t\t\t(uint32_t) ep->dma_addr);\n+\t\t\t} else {\n+\t\t\t\tdma_desc = core_if->dev_if->in_desc_addr;\n+\n+\t\t\t\t/** DMA Descriptor Setup */\n+\t\t\t\tdma_desc->status.b.bs = BS_HOST_BUSY;\n+\t\t\t\tdma_desc->status.b.l = 1;\n+\t\t\t\tdma_desc->status.b.ioc = 1;\n+\t\t\t\tdma_desc->status.b.sp =\n+\t\t\t\t    (ep->xfer_len == ep->maxpacket) ? 0 : 1;\n+\t\t\t\tdma_desc->status.b.bytes = ep->xfer_len;\n+\t\t\t\tdma_desc->buf = ep->dma_addr;\n+\t\t\t\tdma_desc->status.b.sts = 0;\n+\t\t\t\tdma_desc->status.b.bs = BS_HOST_READY;\n+\n+\t\t\t\t/** DIEPDMA0 Register write */\n+\t\t\t\tDWC_WRITE_REG32(&in_regs->diepdma,\n+\t\t\t\t\t\tcore_if->\n+\t\t\t\t\t\tdev_if->dma_in_desc_addr);\n+\t\t\t}\n+\t\t} else {\n+\t\t\tDWC_WRITE_REG32(&in_regs->dieptsiz, deptsiz.d32);\n+\t\t}\n+\n+\t\tif (!core_if->core_params->en_multiple_tx_fifo && core_if->dma_enable)\n+\t\t\tdepctl.b.nextep = core_if->nextep_seq[ep->num];\n+\t\t/* EP enable, IN data in FIFO */\n+\t\tdepctl.b.cnak = 1;\n+\t\tdepctl.b.epena = 1;\n+\t\tDWC_WRITE_REG32(&in_regs->diepctl, depctl.d32);\n+\n+\t\t/**\n+\t\t * Enable the Non-Periodic Tx FIFO empty interrupt, the\n+\t\t * data will be written into the fifo by the ISR.\n+\t\t */\n+\t\tif (!core_if->dma_enable) {\n+\t\t\tif (core_if->en_multiple_tx_fifo == 0) {\n+\t\t\t\tintr_mask.b.nptxfempty = 1;\n+\t\t\t\tDWC_MODIFY_REG32(&core_if->\n+\t\t\t\t\t\t core_global_regs->gintmsk,\n+\t\t\t\t\t\t intr_mask.d32, intr_mask.d32);\n+\t\t\t} else {\n+\t\t\t\t/* Enable the Tx FIFO Empty Interrupt for this EP */\n+\t\t\t\tif (ep->xfer_len > 0) {\n+\t\t\t\t\tuint32_t fifoemptymsk = 0;\n+\t\t\t\t\tfifoemptymsk |= 1 << ep->num;\n+\t\t\t\t\tDWC_MODIFY_REG32(&core_if->\n+\t\t\t\t\t\t\t dev_if->dev_global_regs->dtknqr4_fifoemptymsk,\n+\t\t\t\t\t\t\t 0, fifoemptymsk);\n+\t\t\t\t}\n+\t\t\t}\n+\t\t}\n+\t} else {\n+\t\t/* OUT endpoint */\n+\t\tdwc_otg_dev_out_ep_regs_t *out_regs =\n+\t\t    core_if->dev_if->out_ep_regs[0];\n+\n+\t\tdepctl.d32 = DWC_READ_REG32(&out_regs->doepctl);\n+\t\tdeptsiz.d32 = DWC_READ_REG32(&out_regs->doeptsiz);\n+\n+\t\t/* Program the transfer size and packet count as follows:\n+\t\t *      xfersize = N * (maxpacket + 4 - (maxpacket % 4))\n+\t\t *      pktcnt = N                                                                                      */\n+\t\t/* Zero Length Packet */\n+\t\tdeptsiz.b.xfersize = ep->maxpacket;\n+\t\tdeptsiz.b.pktcnt = 1;\n+\t\tif (core_if->snpsid >= OTG_CORE_REV_3_00a)\n+\t\t\tdeptsiz.b.supcnt = 3;\n+\n+\t\tDWC_DEBUGPL(DBG_PCDV, \"len=%d  xfersize=%d pktcnt=%d\\n\",\n+\t\t\t    ep->xfer_len, deptsiz.b.xfersize, deptsiz.b.pktcnt);\n+\n+\t\tif (core_if->dma_enable) {\n+\t\t\tif (!core_if->dma_desc_enable) {\n+\t\t\t\tDWC_WRITE_REG32(&out_regs->doeptsiz,\n+\t\t\t\t\t\tdeptsiz.d32);\n+\n+\t\t\t\tDWC_WRITE_REG32(&(out_regs->doepdma),\n+\t\t\t\t\t\t(uint32_t) ep->dma_addr);\n+\t\t\t} else {\n+\t\t\t\tdma_desc = core_if->dev_if->out_desc_addr;\n+\n+\t\t\t\t/** DMA Descriptor Setup */\n+\t\t\t\tdma_desc->status.b.bs = BS_HOST_BUSY;\n+\t\t\t\tif (core_if->snpsid >= OTG_CORE_REV_3_00a) {\n+\t\t\t\t\tdma_desc->status.b.mtrf = 0;\n+\t\t\t\t\tdma_desc->status.b.sr = 0;\n+\t\t\t\t}\n+\t\t\t\tdma_desc->status.b.l = 1;\n+\t\t\t\tdma_desc->status.b.ioc = 1;\n+\t\t\t\tdma_desc->status.b.bytes = ep->maxpacket;\n+\t\t\t\tdma_desc->buf = ep->dma_addr;\n+\t\t\t\tdma_desc->status.b.sts = 0;\n+\t\t\t\tdma_desc->status.b.bs = BS_HOST_READY;\n+\n+\t\t\t\t/** DOEPDMA0 Register write */\n+\t\t\t\tDWC_WRITE_REG32(&out_regs->doepdma,\n+\t\t\t\t\t\tcore_if->dev_if->\n+\t\t\t\t\t\tdma_out_desc_addr);\n+\t\t\t}\n+\t\t} else {\n+\t\t\tDWC_WRITE_REG32(&out_regs->doeptsiz, deptsiz.d32);\n+\t\t}\n+\n+\t\t/* EP enable */\n+\t\tdepctl.b.cnak = 1;\n+\t\tdepctl.b.epena = 1;\n+\t\tDWC_WRITE_REG32(&(out_regs->doepctl), depctl.d32);\n+\t}\n+}\n+\n+/**\n+ * This function continues control IN transfers started by\n+ * dwc_otg_ep0_start_transfer, when the transfer does not fit in a\n+ * single packet.  NOTE: The DIEPCTL0/DOEPCTL0 registers only have one\n+ * bit for the packet count.\n+ *\n+ * @param core_if Programming view of DWC_otg controller.\n+ * @param ep The EP0 data.\n+ */\n+void dwc_otg_ep0_continue_transfer(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)\n+{\n+\tdepctl_data_t depctl;\n+\tdeptsiz0_data_t deptsiz;\n+\tgintmsk_data_t intr_mask = {.d32 = 0 };\n+\tdwc_otg_dev_dma_desc_t *dma_desc;\n+\n+\tif (ep->is_in == 1) {\n+\t\tdwc_otg_dev_in_ep_regs_t *in_regs =\n+\t\t    core_if->dev_if->in_ep_regs[0];\n+\t\tgnptxsts_data_t tx_status = {.d32 = 0 };\n+\n+\t\ttx_status.d32 =\n+\t\t    DWC_READ_REG32(&core_if->core_global_regs->gnptxsts);\n+\t\t/** @todo Should there be check for room in the Tx\n+\t\t * Status Queue.  If not remove the code above this comment. */\n+\n+\t\tdepctl.d32 = DWC_READ_REG32(&in_regs->diepctl);\n+\t\tdeptsiz.d32 = DWC_READ_REG32(&in_regs->dieptsiz);\n+\n+\t\t/* Program the transfer size and packet count\n+\t\t *      as follows: xfersize = N * maxpacket +\n+\t\t *      short_packet pktcnt = N + (short_packet\n+\t\t *      exist ? 1 : 0)\n+\t\t */\n+\n+\t\tif (core_if->dma_desc_enable == 0) {\n+\t\t\tdeptsiz.b.xfersize =\n+\t\t\t    (ep->total_len - ep->xfer_count) >\n+\t\t\t    ep->maxpacket ? ep->maxpacket : (ep->total_len -\n+\t\t\t\t\t\t\t     ep->xfer_count);\n+\t\t\tdeptsiz.b.pktcnt = 1;\n+\t\t\tif (core_if->dma_enable == 0) {\n+\t\t\t\tep->xfer_len += deptsiz.b.xfersize;\n+\t\t\t} else {\n+\t\t\t\tep->xfer_len = deptsiz.b.xfersize;\n+\t\t\t}\n+\t\t\tDWC_WRITE_REG32(&in_regs->dieptsiz, deptsiz.d32);\n+\t\t} else {\n+\t\t\tep->xfer_len =\n+\t\t\t    (ep->total_len - ep->xfer_count) >\n+\t\t\t    ep->maxpacket ? ep->maxpacket : (ep->total_len -\n+\t\t\t\t\t\t\t     ep->xfer_count);\n+\n+\t\t\tdma_desc = core_if->dev_if->in_desc_addr;\n+\n+\t\t\t/** DMA Descriptor Setup */\n+\t\t\tdma_desc->status.b.bs = BS_HOST_BUSY;\n+\t\t\tdma_desc->status.b.l = 1;\n+\t\t\tdma_desc->status.b.ioc = 1;\n+\t\t\tdma_desc->status.b.sp =\n+\t\t\t    (ep->xfer_len == ep->maxpacket) ? 0 : 1;\n+\t\t\tdma_desc->status.b.bytes = ep->xfer_len;\n+\t\t\tdma_desc->buf = ep->dma_addr;\n+\t\t\tdma_desc->status.b.sts = 0;\n+\t\t\tdma_desc->status.b.bs = BS_HOST_READY;\n+\n+\t\t\t/** DIEPDMA0 Register write */\n+\t\t\tDWC_WRITE_REG32(&in_regs->diepdma,\n+\t\t\t\t\tcore_if->dev_if->dma_in_desc_addr);\n+\t\t}\n+\n+\t\tDWC_DEBUGPL(DBG_PCDV,\n+\t\t\t    \"IN len=%d  xfersize=%d pktcnt=%d [%08x]\\n\",\n+\t\t\t    ep->xfer_len, deptsiz.b.xfersize, deptsiz.b.pktcnt,\n+\t\t\t    deptsiz.d32);\n+\n+\t\t/* Write the DMA register */\n+\t\tif (core_if->hwcfg2.b.architecture == DWC_INT_DMA_ARCH) {\n+\t\t\tif (core_if->dma_desc_enable == 0)\n+\t\t\t\tDWC_WRITE_REG32(&(in_regs->diepdma),\n+\t\t\t\t\t\t(uint32_t) ep->dma_addr);\n+\t\t}\n+\t\tif (!core_if->core_params->en_multiple_tx_fifo && core_if->dma_enable)\n+\t\t\tdepctl.b.nextep = core_if->nextep_seq[ep->num];\n+\t\t/* EP enable, IN data in FIFO */\n+\t\tdepctl.b.cnak = 1;\n+\t\tdepctl.b.epena = 1;\n+\t\tDWC_WRITE_REG32(&in_regs->diepctl, depctl.d32);\n+\n+\t\t/**\n+\t\t * Enable the Non-Periodic Tx FIFO empty interrupt, the\n+\t\t * data will be written into the fifo by the ISR.\n+\t\t */\n+\t\tif (!core_if->dma_enable) {\n+\t\t\tif (core_if->en_multiple_tx_fifo == 0) {\n+\t\t\t\t/* First clear it from GINTSTS */\n+\t\t\t\tintr_mask.b.nptxfempty = 1;\n+\t\t\t\tDWC_MODIFY_REG32(&core_if->\n+\t\t\t\t\t\t core_global_regs->gintmsk,\n+\t\t\t\t\t\t intr_mask.d32, intr_mask.d32);\n+\n+\t\t\t} else {\n+\t\t\t\t/* Enable the Tx FIFO Empty Interrupt for this EP */\n+\t\t\t\tif (ep->xfer_len > 0) {\n+\t\t\t\t\tuint32_t fifoemptymsk = 0;\n+\t\t\t\t\tfifoemptymsk |= 1 << ep->num;\n+\t\t\t\t\tDWC_MODIFY_REG32(&core_if->\n+\t\t\t\t\t\t\t dev_if->dev_global_regs->dtknqr4_fifoemptymsk,\n+\t\t\t\t\t\t\t 0, fifoemptymsk);\n+\t\t\t\t}\n+\t\t\t}\n+\t\t}\n+\t} else {\n+\t\tdwc_otg_dev_out_ep_regs_t *out_regs =\n+\t\t    core_if->dev_if->out_ep_regs[0];\n+\n+\t\tdepctl.d32 = DWC_READ_REG32(&out_regs->doepctl);\n+\t\tdeptsiz.d32 = DWC_READ_REG32(&out_regs->doeptsiz);\n+\n+\t\t/* Program the transfer size and packet count\n+\t\t *      as follows: xfersize = N * maxpacket +\n+\t\t *      short_packet pktcnt = N + (short_packet\n+\t\t *      exist ? 1 : 0)\n+\t\t */\n+\t\tdeptsiz.b.xfersize = ep->maxpacket;\n+\t\tdeptsiz.b.pktcnt = 1;\n+\n+\t\tif (core_if->dma_desc_enable == 0) {\n+\t\t\tDWC_WRITE_REG32(&out_regs->doeptsiz, deptsiz.d32);\n+\t\t} else {\n+\t\t\tdma_desc = core_if->dev_if->out_desc_addr;\n+\n+\t\t\t/** DMA Descriptor Setup */\n+\t\t\tdma_desc->status.b.bs = BS_HOST_BUSY;\n+\t\t\tdma_desc->status.b.l = 1;\n+\t\t\tdma_desc->status.b.ioc = 1;\n+\t\t\tdma_desc->status.b.bytes = ep->maxpacket;\n+\t\t\tdma_desc->buf = ep->dma_addr;\n+\t\t\tdma_desc->status.b.sts = 0;\n+\t\t\tdma_desc->status.b.bs = BS_HOST_READY;\n+\n+\t\t\t/** DOEPDMA0 Register write */\n+\t\t\tDWC_WRITE_REG32(&out_regs->doepdma,\n+\t\t\t\t\tcore_if->dev_if->dma_out_desc_addr);\n+\t\t}\n+\n+\t\tDWC_DEBUGPL(DBG_PCDV,\n+\t\t\t    \"IN len=%d  xfersize=%d pktcnt=%d [%08x]\\n\",\n+\t\t\t    ep->xfer_len, deptsiz.b.xfersize, deptsiz.b.pktcnt,\n+\t\t\t    deptsiz.d32);\n+\n+\t\t/* Write the DMA register */\n+\t\tif (core_if->hwcfg2.b.architecture == DWC_INT_DMA_ARCH) {\n+\t\t\tif (core_if->dma_desc_enable == 0)\n+\t\t\t\tDWC_WRITE_REG32(&(out_regs->doepdma),\n+\t\t\t\t\t\t(uint32_t) ep->dma_addr);\n+\n+\t\t}\n+\n+\t\t/* EP enable, IN data in FIFO */\n+\t\tdepctl.b.cnak = 1;\n+\t\tdepctl.b.epena = 1;\n+\t\tDWC_WRITE_REG32(&out_regs->doepctl, depctl.d32);\n+\n+\t}\n+}\n+\n+#ifdef DEBUG\n+void dump_msg(const u8 * buf, unsigned int length)\n+{\n+\tunsigned int start, num, i;\n+\tchar line[52], *p;\n+\n+\tif (length >= 512)\n+\t\treturn;\n+\tstart = 0;\n+\twhile (length > 0) {\n+\t\tnum = length < 16u ? length : 16u;\n+\t\tp = line;\n+\t\tfor (i = 0; i < num; ++i) {\n+\t\t\tif (i == 8)\n+\t\t\t\t*p++ = ' ';\n+\t\t\tDWC_SPRINTF(p, \" %02x\", buf[i]);\n+\t\t\tp += 3;\n+\t\t}\n+\t\t*p = 0;\n+\t\tDWC_PRINTF(\"%6x: %s\\n\", start, line);\n+\t\tbuf += num;\n+\t\tstart += num;\n+\t\tlength -= num;\n+\t}\n+}\n+#else\n+static inline void dump_msg(const u8 * buf, unsigned int length)\n+{\n+}\n+#endif\n+\n+/**\n+ * This function writes a packet into the Tx FIFO associated with the\n+ * EP. For non-periodic EPs the non-periodic Tx FIFO is written.  For\n+ * periodic EPs the periodic Tx FIFO associated with the EP is written\n+ * with all packets for the next micro-frame.\n+ *\n+ * @param core_if Programming view of DWC_otg controller.\n+ * @param ep The EP to write packet for.\n+ * @param dma Indicates if DMA is being used.\n+ */\n+void dwc_otg_ep_write_packet(dwc_otg_core_if_t * core_if, dwc_ep_t * ep,\n+\t\t\t     int dma)\n+{\n+\t/**\n+\t * The buffer is padded to DWORD on a per packet basis in\n+\t * slave/dma mode if the MPS is not DWORD aligned. The last\n+\t * packet, if short, is also padded to a multiple of DWORD.\n+\t *\n+\t * ep->xfer_buff always starts DWORD aligned in memory and is a\n+\t * multiple of DWORD in length\n+\t *\n+\t * ep->xfer_len can be any number of bytes\n+\t *\n+\t * ep->xfer_count is a multiple of ep->maxpacket until the last\n+\t *\tpacket\n+\t *\n+\t * FIFO access is DWORD */\n+\n+\tuint32_t i;\n+\tuint32_t byte_count;\n+\tuint32_t dword_count;\n+\tuint32_t *fifo;\n+\tuint32_t *data_buff = (uint32_t *) ep->xfer_buff;\n+\n+\tDWC_DEBUGPL((DBG_PCDV | DBG_CILV), \"%s(%p,%p)\\n\", __func__, core_if,\n+\t\t    ep);\n+\tif (ep->xfer_count >= ep->xfer_len) {\n+\t\tDWC_WARN(\"%s() No data for EP%d!!!\\n\", __func__, ep->num);\n+\t\treturn;\n+\t}\n+\n+\t/* Find the byte length of the packet either short packet or MPS */\n+\tif ((ep->xfer_len - ep->xfer_count) < ep->maxpacket) {\n+\t\tbyte_count = ep->xfer_len - ep->xfer_count;\n+\t} else {\n+\t\tbyte_count = ep->maxpacket;\n+\t}\n+\n+\t/* Find the DWORD length, padded by extra bytes as neccessary if MPS\n+\t * is not a multiple of DWORD */\n+\tdword_count = (byte_count + 3) / 4;\n+\n+#ifdef VERBOSE\n+\tdump_msg(ep->xfer_buff, byte_count);\n+#endif\n+\n+\t/**@todo NGS Where are the Periodic Tx FIFO addresses\n+\t * intialized?\tWhat should this be? */\n+\n+\tfifo = core_if->data_fifo[ep->num];\n+\n+\tDWC_DEBUGPL((DBG_PCDV | DBG_CILV), \"fifo=%p buff=%p *p=%08x bc=%d\\n\",\n+\t\t    fifo, data_buff, *data_buff, byte_count);\n+\n+\tif (!dma) {\n+\t\tfor (i = 0; i < dword_count; i++, data_buff++) {\n+\t\t\tDWC_WRITE_REG32(fifo, *data_buff);\n+\t\t}\n+\t}\n+\n+\tep->xfer_count += byte_count;\n+\tep->xfer_buff += byte_count;\n+\tep->dma_addr += byte_count;\n+}\n+\n+/**\n+ * Set the EP STALL.\n+ *\n+ * @param core_if Programming view of DWC_otg controller.\n+ * @param ep The EP to set the stall on.\n+ */\n+void dwc_otg_ep_set_stall(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)\n+{\n+\tdepctl_data_t depctl;\n+\tvolatile uint32_t *depctl_addr;\n+\n+\tDWC_DEBUGPL(DBG_PCD, \"%s ep%d-%s\\n\", __func__, ep->num,\n+\t\t    (ep->is_in ? \"IN\" : \"OUT\"));\n+\n+\tif (ep->is_in == 1) {\n+\t\tdepctl_addr = &(core_if->dev_if->in_ep_regs[ep->num]->diepctl);\n+\t\tdepctl.d32 = DWC_READ_REG32(depctl_addr);\n+\n+\t\t/* set the disable and stall bits */\n+\t\tif (depctl.b.epena) {\n+\t\t\tdepctl.b.epdis = 1;\n+\t\t}\n+\t\tdepctl.b.stall = 1;\n+\t\tDWC_WRITE_REG32(depctl_addr, depctl.d32);\n+\t} else {\n+\t\tdepctl_addr = &(core_if->dev_if->out_ep_regs[ep->num]->doepctl);\n+\t\tdepctl.d32 = DWC_READ_REG32(depctl_addr);\n+\n+\t\t/* set the stall bit */\n+\t\tdepctl.b.stall = 1;\n+\t\tDWC_WRITE_REG32(depctl_addr, depctl.d32);\n+\t}\n+\n+\tDWC_DEBUGPL(DBG_PCD, \"DEPCTL=%0x\\n\", DWC_READ_REG32(depctl_addr));\n+\n+\treturn;\n+}\n+\n+/**\n+ * Clear the EP STALL.\n+ *\n+ * @param core_if Programming view of DWC_otg controller.\n+ * @param ep The EP to clear stall from.\n+ */\n+void dwc_otg_ep_clear_stall(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)\n+{\n+\tdepctl_data_t depctl;\n+\tvolatile uint32_t *depctl_addr;\n+\n+\tDWC_DEBUGPL(DBG_PCD, \"%s ep%d-%s\\n\", __func__, ep->num,\n+\t\t    (ep->is_in ? \"IN\" : \"OUT\"));\n+\n+\tif (ep->is_in == 1) {\n+\t\tdepctl_addr = &(core_if->dev_if->in_ep_regs[ep->num]->diepctl);\n+\t} else {\n+\t\tdepctl_addr = &(core_if->dev_if->out_ep_regs[ep->num]->doepctl);\n+\t}\n+\n+\tdepctl.d32 = DWC_READ_REG32(depctl_addr);\n+\n+\t/* clear the stall bits */\n+\tdepctl.b.stall = 0;\n+\n+\t/*\n+\t * USB Spec 9.4.5: For endpoints using data toggle, regardless\n+\t * of whether an endpoint has the Halt feature set, a\n+\t * ClearFeature(ENDPOINT_HALT) request always results in the\n+\t * data toggle being reinitialized to DATA0.\n+\t */\n+\tif (ep->type == DWC_OTG_EP_TYPE_INTR ||\n+\t    ep->type == DWC_OTG_EP_TYPE_BULK) {\n+\t\tdepctl.b.setd0pid = 1;\t/* DATA0 */\n+\t}\n+\n+\tDWC_WRITE_REG32(depctl_addr, depctl.d32);\n+\tDWC_DEBUGPL(DBG_PCD, \"DEPCTL=%0x\\n\", DWC_READ_REG32(depctl_addr));\n+\treturn;\n+}\n+\n+/**\n+ * This function reads a packet from the Rx FIFO into the destination\n+ * buffer. To read SETUP data use dwc_otg_read_setup_packet.\n+ *\n+ * @param core_if Programming view of DWC_otg controller.\n+ * @param dest\t  Destination buffer for the packet.\n+ * @param bytes  Number of bytes to copy to the destination.\n+ */\n+void dwc_otg_read_packet(dwc_otg_core_if_t * core_if,\n+\t\t\t uint8_t * dest, uint16_t bytes)\n+{\n+\tint i;\n+\tint word_count = (bytes + 3) / 4;\n+\n+\tvolatile uint32_t *fifo = core_if->data_fifo[0];\n+\tuint32_t *data_buff = (uint32_t *) dest;\n+\n+\t/**\n+\t * @todo Account for the case where _dest is not dword aligned. This\n+\t * requires reading data from the FIFO into a uint32_t temp buffer,\n+\t * then moving it into the data buffer.\n+\t */\n+\n+\tDWC_DEBUGPL((DBG_PCDV | DBG_CILV), \"%s(%p,%p,%d)\\n\", __func__,\n+\t\t    core_if, dest, bytes);\n+\n+\tfor (i = 0; i < word_count; i++, data_buff++) {\n+\t\t*data_buff = DWC_READ_REG32(fifo);\n+\t}\n+\n+\treturn;\n+}\n+\n+/**\n+ * This functions reads the device registers and prints them\n+ *\n+ * @param core_if Programming view of DWC_otg controller.\n+ */\n+void dwc_otg_dump_dev_registers(dwc_otg_core_if_t * core_if)\n+{\n+\tint i;\n+\tvolatile uint32_t *addr;\n+\n+\tDWC_PRINTF(\"Device Global Registers\\n\");\n+\taddr = &core_if->dev_if->dev_global_regs->dcfg;\n+\tDWC_PRINTF(\"DCFG\t\t @0x%08lX : 0x%08X\\n\",\n+\t\t   (unsigned long)addr, DWC_READ_REG32(addr));\n+\taddr = &core_if->dev_if->dev_global_regs->dctl;\n+\tDWC_PRINTF(\"DCTL\t\t @0x%08lX : 0x%08X\\n\",\n+\t\t   (unsigned long)addr, DWC_READ_REG32(addr));\n+\taddr = &core_if->dev_if->dev_global_regs->dsts;\n+\tDWC_PRINTF(\"DSTS\t\t @0x%08lX : 0x%08X\\n\",\n+\t\t   (unsigned long)addr, DWC_READ_REG32(addr));\n+\taddr = &core_if->dev_if->dev_global_regs->diepmsk;\n+\tDWC_PRINTF(\"DIEPMSK\t @0x%08lX : 0x%08X\\n\", (unsigned long)addr,\n+\t\t   DWC_READ_REG32(addr));\n+\taddr = &core_if->dev_if->dev_global_regs->doepmsk;\n+\tDWC_PRINTF(\"DOEPMSK\t @0x%08lX : 0x%08X\\n\", (unsigned long)addr,\n+\t\t   DWC_READ_REG32(addr));\n+\taddr = &core_if->dev_if->dev_global_regs->daint;\n+\tDWC_PRINTF(\"DAINT\t @0x%08lX : 0x%08X\\n\", (unsigned long)addr,\n+\t\t   DWC_READ_REG32(addr));\n+\taddr = &core_if->dev_if->dev_global_regs->daintmsk;\n+\tDWC_PRINTF(\"DAINTMSK\t @0x%08lX : 0x%08X\\n\", (unsigned long)addr,\n+\t\t   DWC_READ_REG32(addr));\n+\taddr = &core_if->dev_if->dev_global_regs->dtknqr1;\n+\tDWC_PRINTF(\"DTKNQR1\t @0x%08lX : 0x%08X\\n\", (unsigned long)addr,\n+\t\t   DWC_READ_REG32(addr));\n+\tif (core_if->hwcfg2.b.dev_token_q_depth > 6) {\n+\t\taddr = &core_if->dev_if->dev_global_regs->dtknqr2;\n+\t\tDWC_PRINTF(\"DTKNQR2\t @0x%08lX : 0x%08X\\n\",\n+\t\t\t   (unsigned long)addr, DWC_READ_REG32(addr));\n+\t}\n+\n+\taddr = &core_if->dev_if->dev_global_regs->dvbusdis;\n+\tDWC_PRINTF(\"DVBUSID\t @0x%08lX : 0x%08X\\n\", (unsigned long)addr,\n+\t\t   DWC_READ_REG32(addr));\n+\n+\taddr = &core_if->dev_if->dev_global_regs->dvbuspulse;\n+\tDWC_PRINTF(\"DVBUSPULSE\t@0x%08lX : 0x%08X\\n\",\n+\t\t   (unsigned long)addr, DWC_READ_REG32(addr));\n+\n+\taddr = &core_if->dev_if->dev_global_regs->dtknqr3_dthrctl;\n+\tDWC_PRINTF(\"DTKNQR3_DTHRCTL\t @0x%08lX : 0x%08X\\n\",\n+\t\t   (unsigned long)addr, DWC_READ_REG32(addr));\n+\n+\tif (core_if->hwcfg2.b.dev_token_q_depth > 22) {\n+\t\taddr = &core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk;\n+\t\tDWC_PRINTF(\"DTKNQR4\t @0x%08lX : 0x%08X\\n\",\n+\t\t\t   (unsigned long)addr, DWC_READ_REG32(addr));\n+\t}\n+\n+\taddr = &core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk;\n+\tDWC_PRINTF(\"FIFOEMPMSK\t @0x%08lX : 0x%08X\\n\", (unsigned long)addr,\n+\t\t   DWC_READ_REG32(addr));\n+\n+\tif (core_if->hwcfg2.b.multi_proc_int) {\n+\n+\t\taddr = &core_if->dev_if->dev_global_regs->deachint;\n+\t\tDWC_PRINTF(\"DEACHINT\t @0x%08lX : 0x%08X\\n\",\n+\t\t\t   (unsigned long)addr, DWC_READ_REG32(addr));\n+\t\taddr = &core_if->dev_if->dev_global_regs->deachintmsk;\n+\t\tDWC_PRINTF(\"DEACHINTMSK\t @0x%08lX : 0x%08X\\n\",\n+\t\t\t   (unsigned long)addr, DWC_READ_REG32(addr));\n+\n+\t\tfor (i = 0; i <= core_if->dev_if->num_in_eps; i++) {\n+\t\t\taddr =\n+\t\t\t    &core_if->dev_if->\n+\t\t\t    dev_global_regs->diepeachintmsk[i];\n+\t\t\tDWC_PRINTF(\"DIEPEACHINTMSK[%d]\t @0x%08lX : 0x%08X\\n\",\n+\t\t\t\t   i, (unsigned long)addr,\n+\t\t\t\t   DWC_READ_REG32(addr));\n+\t\t}\n+\n+\t\tfor (i = 0; i <= core_if->dev_if->num_out_eps; i++) {\n+\t\t\taddr =\n+\t\t\t    &core_if->dev_if->\n+\t\t\t    dev_global_regs->doepeachintmsk[i];\n+\t\t\tDWC_PRINTF(\"DOEPEACHINTMSK[%d]\t @0x%08lX : 0x%08X\\n\",\n+\t\t\t\t   i, (unsigned long)addr,\n+\t\t\t\t   DWC_READ_REG32(addr));\n+\t\t}\n+\t}\n+\n+\tfor (i = 0; i <= core_if->dev_if->num_in_eps; i++) {\n+\t\tDWC_PRINTF(\"Device IN EP %d Registers\\n\", i);\n+\t\taddr = &core_if->dev_if->in_ep_regs[i]->diepctl;\n+\t\tDWC_PRINTF(\"DIEPCTL\t @0x%08lX : 0x%08X\\n\",\n+\t\t\t   (unsigned long)addr, DWC_READ_REG32(addr));\n+\t\taddr = &core_if->dev_if->in_ep_regs[i]->diepint;\n+\t\tDWC_PRINTF(\"DIEPINT\t @0x%08lX : 0x%08X\\n\",\n+\t\t\t   (unsigned long)addr, DWC_READ_REG32(addr));\n+\t\taddr = &core_if->dev_if->in_ep_regs[i]->dieptsiz;\n+\t\tDWC_PRINTF(\"DIETSIZ\t @0x%08lX : 0x%08X\\n\",\n+\t\t\t   (unsigned long)addr, DWC_READ_REG32(addr));\n+\t\taddr = &core_if->dev_if->in_ep_regs[i]->diepdma;\n+\t\tDWC_PRINTF(\"DIEPDMA\t @0x%08lX : 0x%08X\\n\",\n+\t\t\t   (unsigned long)addr, DWC_READ_REG32(addr));\n+\t\taddr = &core_if->dev_if->in_ep_regs[i]->dtxfsts;\n+\t\tDWC_PRINTF(\"DTXFSTS\t @0x%08lX : 0x%08X\\n\",\n+\t\t\t   (unsigned long)addr, DWC_READ_REG32(addr));\n+\t\taddr = &core_if->dev_if->in_ep_regs[i]->diepdmab;\n+\t\tDWC_PRINTF(\"DIEPDMAB\t @0x%08lX : 0x%08X\\n\",\n+\t\t\t   (unsigned long)addr, 0 /*DWC_READ_REG32(addr) */ );\n+\t}\n+\n+\tfor (i = 0; i <= core_if->dev_if->num_out_eps; i++) {\n+\t\tDWC_PRINTF(\"Device OUT EP %d Registers\\n\", i);\n+\t\taddr = &core_if->dev_if->out_ep_regs[i]->doepctl;\n+\t\tDWC_PRINTF(\"DOEPCTL\t @0x%08lX : 0x%08X\\n\",\n+\t\t\t   (unsigned long)addr, DWC_READ_REG32(addr));\n+\t\taddr = &core_if->dev_if->out_ep_regs[i]->doepint;\n+\t\tDWC_PRINTF(\"DOEPINT\t @0x%08lX : 0x%08X\\n\",\n+\t\t\t   (unsigned long)addr, DWC_READ_REG32(addr));\n+\t\taddr = &core_if->dev_if->out_ep_regs[i]->doeptsiz;\n+\t\tDWC_PRINTF(\"DOETSIZ\t @0x%08lX : 0x%08X\\n\",\n+\t\t\t   (unsigned long)addr, DWC_READ_REG32(addr));\n+\t\taddr = &core_if->dev_if->out_ep_regs[i]->doepdma;\n+\t\tDWC_PRINTF(\"DOEPDMA\t @0x%08lX : 0x%08X\\n\",\n+\t\t\t   (unsigned long)addr, DWC_READ_REG32(addr));\n+\t\tif (core_if->dma_enable) {\t/* Don't access this register in SLAVE mode */\n+\t\t\taddr = &core_if->dev_if->out_ep_regs[i]->doepdmab;\n+\t\t\tDWC_PRINTF(\"DOEPDMAB\t @0x%08lX : 0x%08X\\n\",\n+\t\t\t\t   (unsigned long)addr, DWC_READ_REG32(addr));\n+\t\t}\n+\n+\t}\n+}\n+\n+/**\n+ * This functions reads the SPRAM and prints its content\n+ *\n+ * @param core_if Programming view of DWC_otg controller.\n+ */\n+void dwc_otg_dump_spram(dwc_otg_core_if_t * core_if)\n+{\n+\tvolatile uint8_t *addr, *start_addr, *end_addr;\n+\n+\tDWC_PRINTF(\"SPRAM Data:\\n\");\n+\tstart_addr = (void *)core_if->core_global_regs;\n+\tDWC_PRINTF(\"Base Address: 0x%8lX\\n\", (unsigned long)start_addr);\n+\tstart_addr += 0x00028000;\n+\tend_addr = (void *)core_if->core_global_regs;\n+\tend_addr += 0x000280e0;\n+\n+\tfor (addr = start_addr; addr < end_addr; addr += 16) {\n+\t\tDWC_PRINTF\n+\t\t    (\"0x%8lX:\\t%2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X\\n\",\n+\t\t     (unsigned long)addr, addr[0], addr[1], addr[2], addr[3],\n+\t\t     addr[4], addr[5], addr[6], addr[7], addr[8], addr[9],\n+\t\t     addr[10], addr[11], addr[12], addr[13], addr[14], addr[15]\n+\t\t    );\n+\t}\n+\n+\treturn;\n+}\n+\n+/**\n+ * This function reads the host registers and prints them\n+ *\n+ * @param core_if Programming view of DWC_otg controller.\n+ */\n+void dwc_otg_dump_host_registers(dwc_otg_core_if_t * core_if)\n+{\n+\tint i;\n+\tvolatile uint32_t *addr;\n+\n+\tDWC_PRINTF(\"Host Global Registers\\n\");\n+\taddr = &core_if->host_if->host_global_regs->hcfg;\n+\tDWC_PRINTF(\"HCFG\t\t @0x%08lX : 0x%08X\\n\",\n+\t\t   (unsigned long)addr, DWC_READ_REG32(addr));\n+\taddr = &core_if->host_if->host_global_regs->hfir;\n+\tDWC_PRINTF(\"HFIR\t\t @0x%08lX : 0x%08X\\n\",\n+\t\t   (unsigned long)addr, DWC_READ_REG32(addr));\n+\taddr = &core_if->host_if->host_global_regs->hfnum;\n+\tDWC_PRINTF(\"HFNUM\t @0x%08lX : 0x%08X\\n\", (unsigned long)addr,\n+\t\t   DWC_READ_REG32(addr));\n+\taddr = &core_if->host_if->host_global_regs->hptxsts;\n+\tDWC_PRINTF(\"HPTXSTS\t @0x%08lX : 0x%08X\\n\", (unsigned long)addr,\n+\t\t   DWC_READ_REG32(addr));\n+\taddr = &core_if->host_if->host_global_regs->haint;\n+\tDWC_PRINTF(\"HAINT\t @0x%08lX : 0x%08X\\n\", (unsigned long)addr,\n+\t\t   DWC_READ_REG32(addr));\n+\taddr = &core_if->host_if->host_global_regs->haintmsk;\n+\tDWC_PRINTF(\"HAINTMSK\t @0x%08lX : 0x%08X\\n\", (unsigned long)addr,\n+\t\t   DWC_READ_REG32(addr));\n+\tif (core_if->dma_desc_enable) {\n+\t\taddr = &core_if->host_if->host_global_regs->hflbaddr;\n+\t\tDWC_PRINTF(\"HFLBADDR\t @0x%08lX : 0x%08X\\n\",\n+\t\t\t   (unsigned long)addr, DWC_READ_REG32(addr));\n+\t}\n+\n+\taddr = core_if->host_if->hprt0;\n+\tDWC_PRINTF(\"HPRT0\t @0x%08lX : 0x%08X\\n\", (unsigned long)addr,\n+\t\t   DWC_READ_REG32(addr));\n+\n+\tfor (i = 0; i < core_if->core_params->host_channels; i++) {\n+\t\tDWC_PRINTF(\"Host Channel %d Specific Registers\\n\", i);\n+\t\taddr = &core_if->host_if->hc_regs[i]->hcchar;\n+\t\tDWC_PRINTF(\"HCCHAR\t @0x%08lX : 0x%08X\\n\",\n+\t\t\t   (unsigned long)addr, DWC_READ_REG32(addr));\n+\t\taddr = &core_if->host_if->hc_regs[i]->hcsplt;\n+\t\tDWC_PRINTF(\"HCSPLT\t @0x%08lX : 0x%08X\\n\",\n+\t\t\t   (unsigned long)addr, DWC_READ_REG32(addr));\n+\t\taddr = &core_if->host_if->hc_regs[i]->hcint;\n+\t\tDWC_PRINTF(\"HCINT\t @0x%08lX : 0x%08X\\n\",\n+\t\t\t   (unsigned long)addr, DWC_READ_REG32(addr));\n+\t\taddr = &core_if->host_if->hc_regs[i]->hcintmsk;\n+\t\tDWC_PRINTF(\"HCINTMSK\t @0x%08lX : 0x%08X\\n\",\n+\t\t\t   (unsigned long)addr, DWC_READ_REG32(addr));\n+\t\taddr = &core_if->host_if->hc_regs[i]->hctsiz;\n+\t\tDWC_PRINTF(\"HCTSIZ\t @0x%08lX : 0x%08X\\n\",\n+\t\t\t   (unsigned long)addr, DWC_READ_REG32(addr));\n+\t\taddr = &core_if->host_if->hc_regs[i]->hcdma;\n+\t\tDWC_PRINTF(\"HCDMA\t @0x%08lX : 0x%08X\\n\",\n+\t\t\t   (unsigned long)addr, DWC_READ_REG32(addr));\n+\t\tif (core_if->dma_desc_enable) {\n+\t\t\taddr = &core_if->host_if->hc_regs[i]->hcdmab;\n+\t\t\tDWC_PRINTF(\"HCDMAB\t @0x%08lX : 0x%08X\\n\",\n+\t\t\t\t   (unsigned long)addr, DWC_READ_REG32(addr));\n+\t\t}\n+\n+\t}\n+\treturn;\n+}\n+\n+/**\n+ * This function reads the core global registers and prints them\n+ *\n+ * @param core_if Programming view of DWC_otg controller.\n+ */\n+void dwc_otg_dump_global_registers(dwc_otg_core_if_t * core_if)\n+{\n+\tint i, ep_num;\n+\tvolatile uint32_t *addr;\n+\tchar *txfsiz;\n+\n+\tDWC_PRINTF(\"Core Global Registers\\n\");\n+\taddr = &core_if->core_global_regs->gotgctl;\n+\tDWC_PRINTF(\"GOTGCTL\t @0x%08lX : 0x%08X\\n\", (unsigned long)addr,\n+\t\t   DWC_READ_REG32(addr));\n+\taddr = &core_if->core_global_regs->gotgint;\n+\tDWC_PRINTF(\"GOTGINT\t @0x%08lX : 0x%08X\\n\", (unsigned long)addr,\n+\t\t   DWC_READ_REG32(addr));\n+\taddr = &core_if->core_global_regs->gahbcfg;\n+\tDWC_PRINTF(\"GAHBCFG\t @0x%08lX : 0x%08X\\n\", (unsigned long)addr,\n+\t\t   DWC_READ_REG32(addr));\n+\taddr = &core_if->core_global_regs->gusbcfg;\n+\tDWC_PRINTF(\"GUSBCFG\t @0x%08lX : 0x%08X\\n\", (unsigned long)addr,\n+\t\t   DWC_READ_REG32(addr));\n+\taddr = &core_if->core_global_regs->grstctl;\n+\tDWC_PRINTF(\"GRSTCTL\t @0x%08lX : 0x%08X\\n\", (unsigned long)addr,\n+\t\t   DWC_READ_REG32(addr));\n+\taddr = &core_if->core_global_regs->gintsts;\n+\tDWC_PRINTF(\"GINTSTS\t @0x%08lX : 0x%08X\\n\", (unsigned long)addr,\n+\t\t   DWC_READ_REG32(addr));\n+\taddr = &core_if->core_global_regs->gintmsk;\n+\tDWC_PRINTF(\"GINTMSK\t @0x%08lX : 0x%08X\\n\", (unsigned long)addr,\n+\t\t   DWC_READ_REG32(addr));\n+\taddr = &core_if->core_global_regs->grxstsr;\n+\tDWC_PRINTF(\"GRXSTSR\t @0x%08lX : 0x%08X\\n\", (unsigned long)addr,\n+\t\t   DWC_READ_REG32(addr));\n+\taddr = &core_if->core_global_regs->grxfsiz;\n+\tDWC_PRINTF(\"GRXFSIZ\t @0x%08lX : 0x%08X\\n\", (unsigned long)addr,\n+\t\t   DWC_READ_REG32(addr));\n+\taddr = &core_if->core_global_regs->gnptxfsiz;\n+\tDWC_PRINTF(\"GNPTXFSIZ @0x%08lX : 0x%08X\\n\", (unsigned long)addr,\n+\t\t   DWC_READ_REG32(addr));\n+\taddr = &core_if->core_global_regs->gnptxsts;\n+\tDWC_PRINTF(\"GNPTXSTS\t @0x%08lX : 0x%08X\\n\", (unsigned long)addr,\n+\t\t   DWC_READ_REG32(addr));\n+\taddr = &core_if->core_global_regs->gi2cctl;\n+\tDWC_PRINTF(\"GI2CCTL\t @0x%08lX : 0x%08X\\n\", (unsigned long)addr,\n+\t\t   DWC_READ_REG32(addr));\n+\taddr = &core_if->core_global_regs->gpvndctl;\n+\tDWC_PRINTF(\"GPVNDCTL\t @0x%08lX : 0x%08X\\n\", (unsigned long)addr,\n+\t\t   DWC_READ_REG32(addr));\n+\taddr = &core_if->core_global_regs->ggpio;\n+\tDWC_PRINTF(\"GGPIO\t @0x%08lX : 0x%08X\\n\", (unsigned long)addr,\n+\t\t   DWC_READ_REG32(addr));\n+\taddr = &core_if->core_global_regs->guid;\n+\tDWC_PRINTF(\"GUID\t\t @0x%08lX : 0x%08X\\n\",\n+\t\t   (unsigned long)addr, DWC_READ_REG32(addr));\n+\taddr = &core_if->core_global_regs->gsnpsid;\n+\tDWC_PRINTF(\"GSNPSID\t @0x%08lX : 0x%08X\\n\", (unsigned long)addr,\n+\t\t   DWC_READ_REG32(addr));\n+\taddr = &core_if->core_global_regs->ghwcfg1;\n+\tDWC_PRINTF(\"GHWCFG1\t @0x%08lX : 0x%08X\\n\", (unsigned long)addr,\n+\t\t   DWC_READ_REG32(addr));\n+\taddr = &core_if->core_global_regs->ghwcfg2;\n+\tDWC_PRINTF(\"GHWCFG2\t @0x%08lX : 0x%08X\\n\", (unsigned long)addr,\n+\t\t   DWC_READ_REG32(addr));\n+\taddr = &core_if->core_global_regs->ghwcfg3;\n+\tDWC_PRINTF(\"GHWCFG3\t @0x%08lX : 0x%08X\\n\", (unsigned long)addr,\n+\t\t   DWC_READ_REG32(addr));\n+\taddr = &core_if->core_global_regs->ghwcfg4;\n+\tDWC_PRINTF(\"GHWCFG4\t @0x%08lX : 0x%08X\\n\", (unsigned long)addr,\n+\t\t   DWC_READ_REG32(addr));\n+\taddr = &core_if->core_global_regs->glpmcfg;\n+\tDWC_PRINTF(\"GLPMCFG\t @0x%08lX : 0x%08X\\n\", (unsigned long)addr,\n+\t\t   DWC_READ_REG32(addr));\n+\taddr = &core_if->core_global_regs->gpwrdn;\n+\tDWC_PRINTF(\"GPWRDN\t @0x%08lX : 0x%08X\\n\", (unsigned long)addr,\n+\t\t   DWC_READ_REG32(addr));\n+\taddr = &core_if->core_global_regs->gdfifocfg;\n+\tDWC_PRINTF(\"GDFIFOCFG\t @0x%08lX : 0x%08X\\n\", (unsigned long)addr,\n+\t\t   DWC_READ_REG32(addr));\n+\taddr = &core_if->core_global_regs->adpctl;\n+\tDWC_PRINTF(\"ADPCTL\t @0x%08lX : 0x%08X\\n\", (unsigned long)addr,\n+\t\t   dwc_otg_adp_read_reg(core_if));\n+\taddr = &core_if->core_global_regs->hptxfsiz;\n+\tDWC_PRINTF(\"HPTXFSIZ\t @0x%08lX : 0x%08X\\n\", (unsigned long)addr,\n+\t\t   DWC_READ_REG32(addr));\n+\n+\tif (core_if->en_multiple_tx_fifo == 0) {\n+\t\tep_num = core_if->hwcfg4.b.num_dev_perio_in_ep;\n+\t\ttxfsiz = \"DPTXFSIZ\";\n+\t} else {\n+\t\tep_num = core_if->hwcfg4.b.num_in_eps;\n+\t\ttxfsiz = \"DIENPTXF\";\n+\t}\n+\tfor (i = 0; i < ep_num; i++) {\n+\t\taddr = &core_if->core_global_regs->dtxfsiz[i];\n+\t\tDWC_PRINTF(\"%s[%d] @0x%08lX : 0x%08X\\n\", txfsiz, i + 1,\n+\t\t\t   (unsigned long)addr, DWC_READ_REG32(addr));\n+\t}\n+\taddr = core_if->pcgcctl;\n+\tDWC_PRINTF(\"PCGCCTL\t @0x%08lX : 0x%08X\\n\", (unsigned long)addr,\n+\t\t   DWC_READ_REG32(addr));\n+}\n+\n+/**\n+ * Flush a Tx FIFO.\n+ *\n+ * @param core_if Programming view of DWC_otg controller.\n+ * @param num Tx FIFO to flush.\n+ */\n+void dwc_otg_flush_tx_fifo(dwc_otg_core_if_t * core_if, const int num)\n+{\n+\tdwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;\n+\tvolatile grstctl_t greset = {.d32 = 0 };\n+\tint count = 0;\n+\n+\tDWC_DEBUGPL((DBG_CIL | DBG_PCDV), \"Flush Tx FIFO %d\\n\", num);\n+\n+\tgreset.b.txfflsh = 1;\n+\tgreset.b.txfnum = num;\n+\tDWC_WRITE_REG32(&global_regs->grstctl, greset.d32);\n+\n+\tdo {\n+\t\tgreset.d32 = DWC_READ_REG32(&global_regs->grstctl);\n+\t\tif (++count > 10000) {\n+\t\t\tDWC_WARN(\"%s() HANG! GRSTCTL=%0x GNPTXSTS=0x%08x\\n\",\n+\t\t\t\t __func__, greset.d32,\n+\t\t\t\t DWC_READ_REG32(&global_regs->gnptxsts));\n+\t\t\tbreak;\n+\t\t}\n+\t\tdwc_udelay(1);\n+\t} while (greset.b.txfflsh == 1);\n+\n+\t/* Wait for 3 PHY Clocks */\n+\tdwc_udelay(1);\n+}\n+\n+/**\n+ * Flush Rx FIFO.\n+ *\n+ * @param core_if Programming view of DWC_otg controller.\n+ */\n+void dwc_otg_flush_rx_fifo(dwc_otg_core_if_t * core_if)\n+{\n+\tdwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;\n+\tvolatile grstctl_t greset = {.d32 = 0 };\n+\tint count = 0;\n+\n+\tDWC_DEBUGPL((DBG_CIL | DBG_PCDV), \"%s\\n\", __func__);\n+\t/*\n+\t *\n+\t */\n+\tgreset.b.rxfflsh = 1;\n+\tDWC_WRITE_REG32(&global_regs->grstctl, greset.d32);\n+\n+\tdo {\n+\t\tgreset.d32 = DWC_READ_REG32(&global_regs->grstctl);\n+\t\tif (++count > 10000) {\n+\t\t\tDWC_WARN(\"%s() HANG! GRSTCTL=%0x\\n\", __func__,\n+\t\t\t\t greset.d32);\n+\t\t\tbreak;\n+\t\t}\n+\t\tdwc_udelay(1);\n+\t} while (greset.b.rxfflsh == 1);\n+\n+\t/* Wait for 3 PHY Clocks */\n+\tdwc_udelay(1);\n+}\n+\n+/**\n+ * Do core a soft reset of the core.  Be careful with this because it\n+ * resets all the internal state machines of the core.\n+ */\n+void dwc_otg_core_reset(dwc_otg_core_if_t * core_if)\n+{\n+\tdwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;\n+\tvolatile grstctl_t greset = {.d32 = 0 };\n+\tint count = 0;\n+\n+\tDWC_DEBUGPL(DBG_CILV, \"%s\\n\", __func__);\n+\t/* Wait for AHB master IDLE state. */\n+\tdo {\n+\t\tdwc_udelay(10);\n+\t\tgreset.d32 = DWC_READ_REG32(&global_regs->grstctl);\n+\t\tif (++count > 100000) {\n+\t\t\tDWC_WARN(\"%s() HANG! AHB Idle GRSTCTL=%0x\\n\", __func__,\n+\t\t\t\t greset.d32);\n+\t\t\treturn;\n+\t\t}\n+\t}\n+\twhile (greset.b.ahbidle == 0);\n+\n+\t/* Core Soft Reset */\n+\tcount = 0;\n+\tgreset.b.csftrst = 1;\n+\tDWC_WRITE_REG32(&global_regs->grstctl, greset.d32);\n+\tdo {\n+\t\tgreset.d32 = DWC_READ_REG32(&global_regs->grstctl);\n+\t\tif (++count > 10000) {\n+\t\t\tDWC_WARN(\"%s() HANG! Soft Reset GRSTCTL=%0x\\n\",\n+\t\t\t\t __func__, greset.d32);\n+\t\t\tbreak;\n+\t\t}\n+\t\tdwc_udelay(1);\n+\t}\n+\twhile (greset.b.csftrst == 1);\n+\n+\t/* Wait for 3 PHY Clocks */\n+\tdwc_mdelay(100);\n+}\n+\n+uint8_t dwc_otg_is_device_mode(dwc_otg_core_if_t * _core_if)\n+{\n+\treturn (dwc_otg_mode(_core_if) != DWC_HOST_MODE);\n+}\n+\n+uint8_t dwc_otg_is_host_mode(dwc_otg_core_if_t * _core_if)\n+{\n+\treturn (dwc_otg_mode(_core_if) == DWC_HOST_MODE);\n+}\n+\n+/**\n+ * Register HCD callbacks. The callbacks are used to start and stop\n+ * the HCD for interrupt processing.\n+ *\n+ * @param core_if Programming view of DWC_otg controller.\n+ * @param cb the HCD callback structure.\n+ * @param p pointer to be passed to callback function (usb_hcd*).\n+ */\n+void dwc_otg_cil_register_hcd_callbacks(dwc_otg_core_if_t * core_if,\n+\t\t\t\t\tdwc_otg_cil_callbacks_t * cb, void *p)\n+{\n+\tcore_if->hcd_cb = cb;\n+\tcb->p = p;\n+}\n+\n+/**\n+ * Register PCD callbacks. The callbacks are used to start and stop\n+ * the PCD for interrupt processing.\n+ *\n+ * @param core_if Programming view of DWC_otg controller.\n+ * @param cb the PCD callback structure.\n+ * @param p pointer to be passed to callback function (pcd*).\n+ */\n+void dwc_otg_cil_register_pcd_callbacks(dwc_otg_core_if_t * core_if,\n+\t\t\t\t\tdwc_otg_cil_callbacks_t * cb, void *p)\n+{\n+\tcore_if->pcd_cb = cb;\n+\tcb->p = p;\n+}\n+\n+#ifdef DWC_EN_ISOC\n+\n+/**\n+ * This function writes isoc data per 1 (micro)frame into tx fifo\n+ *\n+ * @param core_if Programming view of DWC_otg controller.\n+ * @param ep The EP to start the transfer on.\n+ *\n+ */\n+void write_isoc_frame_data(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)\n+{\n+\tdwc_otg_dev_in_ep_regs_t *ep_regs;\n+\tdtxfsts_data_t txstatus = {.d32 = 0 };\n+\tuint32_t len = 0;\n+\tuint32_t dwords;\n+\n+\tep->xfer_len = ep->data_per_frame;\n+\tep->xfer_count = 0;\n+\n+\tep_regs = core_if->dev_if->in_ep_regs[ep->num];\n+\n+\tlen = ep->xfer_len - ep->xfer_count;\n+\n+\tif (len > ep->maxpacket) {\n+\t\tlen = ep->maxpacket;\n+\t}\n+\n+\tdwords = (len + 3) / 4;\n+\n+\t/* While there is space in the queue and space in the FIFO and\n+\t * More data to tranfer, Write packets to the Tx FIFO */\n+\ttxstatus.d32 =\n+\t    DWC_READ_REG32(&core_if->dev_if->in_ep_regs[ep->num]->dtxfsts);\n+\tDWC_DEBUGPL(DBG_PCDV, \"b4 dtxfsts[%d]=0x%08x\\n\", ep->num, txstatus.d32);\n+\n+\twhile (txstatus.b.txfspcavail > dwords &&\n+\t       ep->xfer_count < ep->xfer_len && ep->xfer_len != 0) {\n+\t\t/* Write the FIFO */\n+\t\tdwc_otg_ep_write_packet(core_if, ep, 0);\n+\n+\t\tlen = ep->xfer_len - ep->xfer_count;\n+\t\tif (len > ep->maxpacket) {\n+\t\t\tlen = ep->maxpacket;\n+\t\t}\n+\n+\t\tdwords = (len + 3) / 4;\n+\t\ttxstatus.d32 =\n+\t\t    DWC_READ_REG32(&core_if->dev_if->in_ep_regs[ep->num]->\n+\t\t\t\t   dtxfsts);\n+\t\tDWC_DEBUGPL(DBG_PCDV, \"dtxfsts[%d]=0x%08x\\n\", ep->num,\n+\t\t\t    txstatus.d32);\n+\t}\n+}\n+\n+/**\n+ * This function initializes a descriptor chain for Isochronous transfer\n+ *\n+ * @param core_if Programming view of DWC_otg controller.\n+ * @param ep The EP to start the transfer on.\n+ *\n+ */\n+void dwc_otg_iso_ep_start_frm_transfer(dwc_otg_core_if_t * core_if,\n+\t\t\t\t       dwc_ep_t * ep)\n+{\n+\tdeptsiz_data_t deptsiz = {.d32 = 0 };\n+\tdepctl_data_t depctl = {.d32 = 0 };\n+\tdsts_data_t dsts = {.d32 = 0 };\n+\tvolatile uint32_t *addr;\n+\n+\tif (ep->is_in) {\n+\t\taddr = &core_if->dev_if->in_ep_regs[ep->num]->diepctl;\n+\t} else {\n+\t\taddr = &core_if->dev_if->out_ep_regs[ep->num]->doepctl;\n+\t}\n+\n+\tep->xfer_len = ep->data_per_frame;\n+\tep->xfer_count = 0;\n+\tep->xfer_buff = ep->cur_pkt_addr;\n+\tep->dma_addr = ep->cur_pkt_dma_addr;\n+\n+\tif (ep->is_in) {\n+\t\t/* Program the transfer size and packet count\n+\t\t *      as follows: xfersize = N * maxpacket +\n+\t\t *      short_packet pktcnt = N + (short_packet\n+\t\t *      exist ? 1 : 0)\n+\t\t */\n+\t\tdeptsiz.b.xfersize = ep->xfer_len;\n+\t\tdeptsiz.b.pktcnt =\n+\t\t    (ep->xfer_len - 1 + ep->maxpacket) / ep->maxpacket;\n+\t\tdeptsiz.b.mc = deptsiz.b.pktcnt;\n+\t\tDWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[ep->num]->dieptsiz,\n+\t\t\t\tdeptsiz.d32);\n+\n+\t\t/* Write the DMA register */\n+\t\tif (core_if->dma_enable) {\n+\t\t\tDWC_WRITE_REG32(&\n+\t\t\t\t\t(core_if->dev_if->in_ep_regs[ep->num]->\n+\t\t\t\t\t diepdma), (uint32_t) ep->dma_addr);\n+\t\t}\n+\t} else {\n+\t\tdeptsiz.b.pktcnt =\n+\t\t    (ep->xfer_len + (ep->maxpacket - 1)) / ep->maxpacket;\n+\t\tdeptsiz.b.xfersize = deptsiz.b.pktcnt * ep->maxpacket;\n+\n+\t\tDWC_WRITE_REG32(&core_if->dev_if->\n+\t\t\t\tout_ep_regs[ep->num]->doeptsiz, deptsiz.d32);\n+\n+\t\tif (core_if->dma_enable) {\n+\t\t\tDWC_WRITE_REG32(&\n+\t\t\t\t\t(core_if->dev_if->\n+\t\t\t\t\t out_ep_regs[ep->num]->doepdma),\n+\t\t\t\t\t(uint32_t) ep->dma_addr);\n+\t\t}\n+\t}\n+\n+\t/** Enable endpoint, clear nak  */\n+\n+\tdepctl.d32 = 0;\n+\tif (ep->bInterval == 1) {\n+\t\tdsts.d32 =\n+\t\t    DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);\n+\t\tep->next_frame = dsts.b.soffn + ep->bInterval;\n+\n+\t\tif (ep->next_frame & 0x1) {\n+\t\t\tdepctl.b.setd1pid = 1;\n+\t\t} else {\n+\t\t\tdepctl.b.setd0pid = 1;\n+\t\t}\n+\t} else {\n+\t\tep->next_frame += ep->bInterval;\n+\n+\t\tif (ep->next_frame & 0x1) {\n+\t\t\tdepctl.b.setd1pid = 1;\n+\t\t} else {\n+\t\t\tdepctl.b.setd0pid = 1;\n+\t\t}\n+\t}\n+\tdepctl.b.epena = 1;\n+\tdepctl.b.cnak = 1;\n+\n+\tDWC_MODIFY_REG32(addr, 0, depctl.d32);\n+\tdepctl.d32 = DWC_READ_REG32(addr);\n+\n+\tif (ep->is_in && core_if->dma_enable == 0) {\n+\t\twrite_isoc_frame_data(core_if, ep);\n+\t}\n+\n+}\n+#endif /* DWC_EN_ISOC */\n+\n+static void dwc_otg_set_uninitialized(int32_t * p, int size)\n+{\n+\tint i;\n+\tfor (i = 0; i < size; i++) {\n+\t\tp[i] = -1;\n+\t}\n+}\n+\n+static int dwc_otg_param_initialized(int32_t val)\n+{\n+\treturn val != -1;\n+}\n+\n+static int dwc_otg_setup_params(dwc_otg_core_if_t * core_if)\n+{\n+\tint i;\n+\tcore_if->core_params = DWC_ALLOC(sizeof(*core_if->core_params));\n+\tif (!core_if->core_params) {\n+\t\treturn -DWC_E_NO_MEMORY;\n+\t}\n+\tdwc_otg_set_uninitialized((int32_t *) core_if->core_params,\n+\t\t\t\t  sizeof(*core_if->core_params) /\n+\t\t\t\t  sizeof(int32_t));\n+\tDWC_PRINTF(\"Setting default values for core params\\n\");\n+\tdwc_otg_set_param_otg_cap(core_if, dwc_param_otg_cap_default);\n+\tdwc_otg_set_param_dma_enable(core_if, dwc_param_dma_enable_default);\n+\tdwc_otg_set_param_dma_desc_enable(core_if,\n+\t\t\t\t\t  dwc_param_dma_desc_enable_default);\n+\tdwc_otg_set_param_opt(core_if, dwc_param_opt_default);\n+\tdwc_otg_set_param_dma_burst_size(core_if,\n+\t\t\t\t\t dwc_param_dma_burst_size_default);\n+\tdwc_otg_set_param_host_support_fs_ls_low_power(core_if,\n+\t\t\t\t\t\t       dwc_param_host_support_fs_ls_low_power_default);\n+\tdwc_otg_set_param_enable_dynamic_fifo(core_if,\n+\t\t\t\t\t      dwc_param_enable_dynamic_fifo_default);\n+\tdwc_otg_set_param_data_fifo_size(core_if,\n+\t\t\t\t\t dwc_param_data_fifo_size_default);\n+\tdwc_otg_set_param_dev_rx_fifo_size(core_if,\n+\t\t\t\t\t   dwc_param_dev_rx_fifo_size_default);\n+\tdwc_otg_set_param_dev_nperio_tx_fifo_size(core_if,\n+\t\t\t\t\t\t  dwc_param_dev_nperio_tx_fifo_size_default);\n+\tdwc_otg_set_param_host_rx_fifo_size(core_if,\n+\t\t\t\t\t    dwc_param_host_rx_fifo_size_default);\n+\tdwc_otg_set_param_host_nperio_tx_fifo_size(core_if,\n+\t\t\t\t\t\t   dwc_param_host_nperio_tx_fifo_size_default);\n+\tdwc_otg_set_param_host_perio_tx_fifo_size(core_if,\n+\t\t\t\t\t\t  dwc_param_host_perio_tx_fifo_size_default);\n+\tdwc_otg_set_param_max_transfer_size(core_if,\n+\t\t\t\t\t    dwc_param_max_transfer_size_default);\n+\tdwc_otg_set_param_max_packet_count(core_if,\n+\t\t\t\t\t   dwc_param_max_packet_count_default);\n+\tdwc_otg_set_param_host_channels(core_if,\n+\t\t\t\t\tdwc_param_host_channels_default);\n+\tdwc_otg_set_param_dev_endpoints(core_if,\n+\t\t\t\t\tdwc_param_dev_endpoints_default);\n+\tdwc_otg_set_param_phy_type(core_if, dwc_param_phy_type_default);\n+\tdwc_otg_set_param_speed(core_if, dwc_param_speed_default);\n+\tdwc_otg_set_param_host_ls_low_power_phy_clk(core_if,\n+\t\t\t\t\t\t    dwc_param_host_ls_low_power_phy_clk_default);\n+\tdwc_otg_set_param_phy_ulpi_ddr(core_if, dwc_param_phy_ulpi_ddr_default);\n+\tdwc_otg_set_param_phy_ulpi_ext_vbus(core_if,\n+\t\t\t\t\t    dwc_param_phy_ulpi_ext_vbus_default);\n+\tdwc_otg_set_param_phy_utmi_width(core_if,\n+\t\t\t\t\t dwc_param_phy_utmi_width_default);\n+\tdwc_otg_set_param_ts_dline(core_if, dwc_param_ts_dline_default);\n+\tdwc_otg_set_param_i2c_enable(core_if, dwc_param_i2c_enable_default);\n+\tdwc_otg_set_param_ulpi_fs_ls(core_if, dwc_param_ulpi_fs_ls_default);\n+\tdwc_otg_set_param_en_multiple_tx_fifo(core_if,\n+\t\t\t\t\t      dwc_param_en_multiple_tx_fifo_default);\n+\tfor (i = 0; i < 15; i++) {\n+\t\tdwc_otg_set_param_dev_perio_tx_fifo_size(core_if,\n+\t\t\t\t\t\t\t dwc_param_dev_perio_tx_fifo_size_default,\n+\t\t\t\t\t\t\t i);\n+\t}\n+\n+\tfor (i = 0; i < 15; i++) {\n+\t\tdwc_otg_set_param_dev_tx_fifo_size(core_if,\n+\t\t\t\t\t\t   dwc_param_dev_tx_fifo_size_default,\n+\t\t\t\t\t\t   i);\n+\t}\n+\tdwc_otg_set_param_thr_ctl(core_if, dwc_param_thr_ctl_default);\n+\tdwc_otg_set_param_mpi_enable(core_if, dwc_param_mpi_enable_default);\n+\tdwc_otg_set_param_pti_enable(core_if, dwc_param_pti_enable_default);\n+\tdwc_otg_set_param_lpm_enable(core_if, dwc_param_lpm_enable_default);\n+\tdwc_otg_set_param_ic_usb_cap(core_if, dwc_param_ic_usb_cap_default);\n+\tdwc_otg_set_param_tx_thr_length(core_if,\n+\t\t\t\t\tdwc_param_tx_thr_length_default);\n+\tdwc_otg_set_param_rx_thr_length(core_if,\n+\t\t\t\t\tdwc_param_rx_thr_length_default);\n+\tdwc_otg_set_param_ahb_thr_ratio(core_if,\n+\t\t\t\t\tdwc_param_ahb_thr_ratio_default);\n+\tdwc_otg_set_param_power_down(core_if, dwc_param_power_down_default);\n+\tdwc_otg_set_param_reload_ctl(core_if, dwc_param_reload_ctl_default);\n+\tdwc_otg_set_param_dev_out_nak(core_if, dwc_param_dev_out_nak_default);\n+\tdwc_otg_set_param_cont_on_bna(core_if, dwc_param_cont_on_bna_default);\n+\tdwc_otg_set_param_ahb_single(core_if, dwc_param_ahb_single_default);\n+\tdwc_otg_set_param_otg_ver(core_if, dwc_param_otg_ver_default);\n+\tdwc_otg_set_param_adp_enable(core_if, dwc_param_adp_enable_default);\n+\tDWC_PRINTF(\"Finished setting default values for core params\\n\");\n+\n+\treturn 0;\n+}\n+\n+uint8_t dwc_otg_is_dma_enable(dwc_otg_core_if_t * core_if)\n+{\n+\treturn core_if->dma_enable;\n+}\n+\n+/* Checks if the parameter is outside of its valid range of values */\n+#define DWC_OTG_PARAM_TEST(_param_, _low_, _high_) \\\n+\t\t(((_param_) < (_low_)) || \\\n+\t\t((_param_) > (_high_)))\n+\n+/* Parameter access functions */\n+int dwc_otg_set_param_otg_cap(dwc_otg_core_if_t * core_if, int32_t val)\n+{\n+\tint valid;\n+\tint retval = 0;\n+\tif (DWC_OTG_PARAM_TEST(val, 0, 2)) {\n+\t\tDWC_WARN(\"Wrong value for otg_cap parameter\\n\");\n+\t\tDWC_WARN(\"otg_cap parameter must be 0,1 or 2\\n\");\n+\t\tretval = -DWC_E_INVALID;\n+\t\tgoto out;\n+\t}\n+\n+\tvalid = 1;\n+\tswitch (val) {\n+\tcase DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE:\n+\t\tif (core_if->hwcfg2.b.op_mode !=\n+\t\t    DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG)\n+\t\t\tvalid = 0;\n+\t\tbreak;\n+\tcase DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE:\n+\t\tif ((core_if->hwcfg2.b.op_mode !=\n+\t\t     DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG)\n+\t\t    && (core_if->hwcfg2.b.op_mode !=\n+\t\t\tDWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG)\n+\t\t    && (core_if->hwcfg2.b.op_mode !=\n+\t\t\tDWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE)\n+\t\t    && (core_if->hwcfg2.b.op_mode !=\n+\t\t\tDWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST)) {\n+\t\t\tvalid = 0;\n+\t\t}\n+\t\tbreak;\n+\tcase DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE:\n+\t\t/* always valid */\n+\t\tbreak;\n+\t}\n+\tif (!valid) {\n+\t\tif (dwc_otg_param_initialized(core_if->core_params->otg_cap)) {\n+\t\t\tDWC_ERROR\n+\t\t\t    (\"%d invalid for otg_cap paremter. Check HW configuration.\\n\",\n+\t\t\t     val);\n+\t\t}\n+\t\tval =\n+\t\t    (((core_if->hwcfg2.b.op_mode ==\n+\t\t       DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG)\n+\t\t      || (core_if->hwcfg2.b.op_mode ==\n+\t\t\t  DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG)\n+\t\t      || (core_if->hwcfg2.b.op_mode ==\n+\t\t\t  DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE)\n+\t\t      || (core_if->hwcfg2.b.op_mode ==\n+\t\t\t  DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST)) ?\n+\t\t     DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE :\n+\t\t     DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);\n+\t\tretval = -DWC_E_INVALID;\n+\t}\n+\n+\tcore_if->core_params->otg_cap = val;\n+out:\n+\treturn retval;\n+}\n+\n+int32_t dwc_otg_get_param_otg_cap(dwc_otg_core_if_t * core_if)\n+{\n+\treturn core_if->core_params->otg_cap;\n+}\n+\n+int dwc_otg_set_param_opt(dwc_otg_core_if_t * core_if, int32_t val)\n+{\n+\tif (DWC_OTG_PARAM_TEST(val, 0, 1)) {\n+\t\tDWC_WARN(\"Wrong value for opt parameter\\n\");\n+\t\treturn -DWC_E_INVALID;\n+\t}\n+\tcore_if->core_params->opt = val;\n+\treturn 0;\n+}\n+\n+int32_t dwc_otg_get_param_opt(dwc_otg_core_if_t * core_if)\n+{\n+\treturn core_if->core_params->opt;\n+}\n+\n+int dwc_otg_set_param_dma_enable(dwc_otg_core_if_t * core_if, int32_t val)\n+{\n+\tint retval = 0;\n+\tif (DWC_OTG_PARAM_TEST(val, 0, 1)) {\n+\t\tDWC_WARN(\"Wrong value for dma enable\\n\");\n+\t\treturn -DWC_E_INVALID;\n+\t}\n+\n+\tif ((val == 1) && (core_if->hwcfg2.b.architecture == 0)) {\n+\t\tif (dwc_otg_param_initialized(core_if->core_params->dma_enable)) {\n+\t\t\tDWC_ERROR\n+\t\t\t    (\"%d invalid for dma_enable paremter. Check HW configuration.\\n\",\n+\t\t\t     val);\n+\t\t}\n+\t\tval = 0;\n+\t\tretval = -DWC_E_INVALID;\n+\t}\n+\n+\tcore_if->core_params->dma_enable = val;\n+\tif (val == 0) {\n+\t\tdwc_otg_set_param_dma_desc_enable(core_if, 0);\n+\t}\n+\treturn retval;\n+}\n+\n+int32_t dwc_otg_get_param_dma_enable(dwc_otg_core_if_t * core_if)\n+{\n+\treturn core_if->core_params->dma_enable;\n+}\n+\n+int dwc_otg_set_param_dma_desc_enable(dwc_otg_core_if_t * core_if, int32_t val)\n+{\n+\tint retval = 0;\n+\tif (DWC_OTG_PARAM_TEST(val, 0, 1)) {\n+\t\tDWC_WARN(\"Wrong value for dma_enable\\n\");\n+\t\tDWC_WARN(\"dma_desc_enable must be 0 or 1\\n\");\n+\t\treturn -DWC_E_INVALID;\n+\t}\n+\n+\tif ((val == 1)\n+\t    && ((dwc_otg_get_param_dma_enable(core_if) == 0)\n+\t\t|| (core_if->hwcfg4.b.desc_dma == 0))) {\n+\t\tif (dwc_otg_param_initialized\n+\t\t    (core_if->core_params->dma_desc_enable)) {\n+\t\t\tDWC_ERROR\n+\t\t\t    (\"%d invalid for dma_desc_enable paremter. Check HW configuration.\\n\",\n+\t\t\t     val);\n+\t\t}\n+\t\tval = 0;\n+\t\tretval = -DWC_E_INVALID;\n+\t}\n+\tcore_if->core_params->dma_desc_enable = val;\n+\treturn retval;\n+}\n+\n+int32_t dwc_otg_get_param_dma_desc_enable(dwc_otg_core_if_t * core_if)\n+{\n+\treturn core_if->core_params->dma_desc_enable;\n+}\n+\n+int dwc_otg_set_param_host_support_fs_ls_low_power(dwc_otg_core_if_t * core_if,\n+\t\t\t\t\t\t   int32_t val)\n+{\n+\tif (DWC_OTG_PARAM_TEST(val, 0, 1)) {\n+\t\tDWC_WARN(\"Wrong value for host_support_fs_low_power\\n\");\n+\t\tDWC_WARN(\"host_support_fs_low_power must be 0 or 1\\n\");\n+\t\treturn -DWC_E_INVALID;\n+\t}\n+\tcore_if->core_params->host_support_fs_ls_low_power = val;\n+\treturn 0;\n+}\n+\n+int32_t dwc_otg_get_param_host_support_fs_ls_low_power(dwc_otg_core_if_t *\n+\t\t\t\t\t\t       core_if)\n+{\n+\treturn core_if->core_params->host_support_fs_ls_low_power;\n+}\n+\n+int dwc_otg_set_param_enable_dynamic_fifo(dwc_otg_core_if_t * core_if,\n+\t\t\t\t\t  int32_t val)\n+{\n+\tint retval = 0;\n+\tif (DWC_OTG_PARAM_TEST(val, 0, 1)) {\n+\t\tDWC_WARN(\"Wrong value for enable_dynamic_fifo\\n\");\n+\t\tDWC_WARN(\"enable_dynamic_fifo must be 0 or 1\\n\");\n+\t\treturn -DWC_E_INVALID;\n+\t}\n+\n+\tif ((val == 1) && (core_if->hwcfg2.b.dynamic_fifo == 0)) {\n+\t\tif (dwc_otg_param_initialized\n+\t\t    (core_if->core_params->enable_dynamic_fifo)) {\n+\t\t\tDWC_ERROR\n+\t\t\t    (\"%d invalid for enable_dynamic_fifo paremter. Check HW configuration.\\n\",\n+\t\t\t     val);\n+\t\t}\n+\t\tval = 0;\n+\t\tretval = -DWC_E_INVALID;\n+\t}\n+\tcore_if->core_params->enable_dynamic_fifo = val;\n+\treturn retval;\n+}\n+\n+int32_t dwc_otg_get_param_enable_dynamic_fifo(dwc_otg_core_if_t * core_if)\n+{\n+\treturn core_if->core_params->enable_dynamic_fifo;\n+}\n+\n+int dwc_otg_set_param_data_fifo_size(dwc_otg_core_if_t * core_if, int32_t val)\n+{\n+\tint retval = 0;\n+\tif (DWC_OTG_PARAM_TEST(val, 32, 32768)) {\n+\t\tDWC_WARN(\"Wrong value for data_fifo_size\\n\");\n+\t\tDWC_WARN(\"data_fifo_size must be 32-32768\\n\");\n+\t\treturn -DWC_E_INVALID;\n+\t}\n+\n+\tif (val > core_if->hwcfg3.b.dfifo_depth) {\n+\t\tif (dwc_otg_param_initialized\n+\t\t    (core_if->core_params->data_fifo_size)) {\n+\t\t\tDWC_ERROR\n+\t\t\t    (\"%d invalid for data_fifo_size parameter. Check HW configuration.\\n\",\n+\t\t\t     val);\n+\t\t}\n+\t\tval = core_if->hwcfg3.b.dfifo_depth;\n+\t\tretval = -DWC_E_INVALID;\n+\t}\n+\n+\tcore_if->core_params->data_fifo_size = val;\n+\treturn retval;\n+}\n+\n+int32_t dwc_otg_get_param_data_fifo_size(dwc_otg_core_if_t * core_if)\n+{\n+\treturn core_if->core_params->data_fifo_size;\n+}\n+\n+int dwc_otg_set_param_dev_rx_fifo_size(dwc_otg_core_if_t * core_if, int32_t val)\n+{\n+\tint retval = 0;\n+\tif (DWC_OTG_PARAM_TEST(val, 16, 32768)) {\n+\t\tDWC_WARN(\"Wrong value for dev_rx_fifo_size\\n\");\n+\t\tDWC_WARN(\"dev_rx_fifo_size must be 16-32768\\n\");\n+\t\treturn -DWC_E_INVALID;\n+\t}\n+\n+\tif (val > DWC_READ_REG32(&core_if->core_global_regs->grxfsiz)) {\n+\t\tif (dwc_otg_param_initialized(core_if->core_params->dev_rx_fifo_size)) {\n+\t\tDWC_WARN(\"%d invalid for dev_rx_fifo_size parameter\\n\", val);\n+\t\t}\n+\t\tval = DWC_READ_REG32(&core_if->core_global_regs->grxfsiz);\n+\t\tretval = -DWC_E_INVALID;\n+\t}\n+\n+\tcore_if->core_params->dev_rx_fifo_size = val;\n+\treturn retval;\n+}\n+\n+int32_t dwc_otg_get_param_dev_rx_fifo_size(dwc_otg_core_if_t * core_if)\n+{\n+\treturn core_if->core_params->dev_rx_fifo_size;\n+}\n+\n+int dwc_otg_set_param_dev_nperio_tx_fifo_size(dwc_otg_core_if_t * core_if,\n+\t\t\t\t\t      int32_t val)\n+{\n+\tint retval = 0;\n+\n+\tif (DWC_OTG_PARAM_TEST(val, 16, 32768)) {\n+\t\tDWC_WARN(\"Wrong value for dev_nperio_tx_fifo\\n\");\n+\t\tDWC_WARN(\"dev_nperio_tx_fifo must be 16-32768\\n\");\n+\t\treturn -DWC_E_INVALID;\n+\t}\n+\n+\tif (val > (DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz) >> 16)) {\n+\t\tif (dwc_otg_param_initialized\n+\t\t    (core_if->core_params->dev_nperio_tx_fifo_size)) {\n+\t\t\tDWC_ERROR\n+\t\t\t    (\"%d invalid for dev_nperio_tx_fifo_size. Check HW configuration.\\n\",\n+\t\t\t     val);\n+\t\t}\n+\t\tval =\n+\t\t    (DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz) >>\n+\t\t     16);\n+\t\tretval = -DWC_E_INVALID;\n+\t}\n+\n+\tcore_if->core_params->dev_nperio_tx_fifo_size = val;\n+\treturn retval;\n+}\n+\n+int32_t dwc_otg_get_param_dev_nperio_tx_fifo_size(dwc_otg_core_if_t * core_if)\n+{\n+\treturn core_if->core_params->dev_nperio_tx_fifo_size;\n+}\n+\n+int dwc_otg_set_param_host_rx_fifo_size(dwc_otg_core_if_t * core_if,\n+\t\t\t\t\tint32_t val)\n+{\n+\tint retval = 0;\n+\n+\tif (DWC_OTG_PARAM_TEST(val, 16, 32768)) {\n+\t\tDWC_WARN(\"Wrong value for host_rx_fifo_size\\n\");\n+\t\tDWC_WARN(\"host_rx_fifo_size must be 16-32768\\n\");\n+\t\treturn -DWC_E_INVALID;\n+\t}\n+\n+\tif (val > DWC_READ_REG32(&core_if->core_global_regs->grxfsiz)) {\n+\t\tif (dwc_otg_param_initialized\n+\t\t    (core_if->core_params->host_rx_fifo_size)) {\n+\t\t\tDWC_ERROR\n+\t\t\t    (\"%d invalid for host_rx_fifo_size. Check HW configuration.\\n\",\n+\t\t\t     val);\n+\t\t}\n+\t\tval = DWC_READ_REG32(&core_if->core_global_regs->grxfsiz);\n+\t\tretval = -DWC_E_INVALID;\n+\t}\n+\n+\tcore_if->core_params->host_rx_fifo_size = val;\n+\treturn retval;\n+\n+}\n+\n+int32_t dwc_otg_get_param_host_rx_fifo_size(dwc_otg_core_if_t * core_if)\n+{\n+\treturn core_if->core_params->host_rx_fifo_size;\n+}\n+\n+int dwc_otg_set_param_host_nperio_tx_fifo_size(dwc_otg_core_if_t * core_if,\n+\t\t\t\t\t       int32_t val)\n+{\n+\tint retval = 0;\n+\n+\tif (DWC_OTG_PARAM_TEST(val, 16, 32768)) {\n+\t\tDWC_WARN(\"Wrong value for host_nperio_tx_fifo_size\\n\");\n+\t\tDWC_WARN(\"host_nperio_tx_fifo_size must be 16-32768\\n\");\n+\t\treturn -DWC_E_INVALID;\n+\t}\n+\n+\tif (val > (DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz) >> 16)) {\n+\t\tif (dwc_otg_param_initialized\n+\t\t    (core_if->core_params->host_nperio_tx_fifo_size)) {\n+\t\t\tDWC_ERROR\n+\t\t\t    (\"%d invalid for host_nperio_tx_fifo_size. Check HW configuration.\\n\",\n+\t\t\t     val);\n+\t\t}\n+\t\tval =\n+\t\t    (DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz) >>\n+\t\t     16);\n+\t\tretval = -DWC_E_INVALID;\n+\t}\n+\n+\tcore_if->core_params->host_nperio_tx_fifo_size = val;\n+\treturn retval;\n+}\n+\n+int32_t dwc_otg_get_param_host_nperio_tx_fifo_size(dwc_otg_core_if_t * core_if)\n+{\n+\treturn core_if->core_params->host_nperio_tx_fifo_size;\n+}\n+\n+int dwc_otg_set_param_host_perio_tx_fifo_size(dwc_otg_core_if_t * core_if,\n+\t\t\t\t\t      int32_t val)\n+{\n+\tint retval = 0;\n+\tif (DWC_OTG_PARAM_TEST(val, 16, 32768)) {\n+\t\tDWC_WARN(\"Wrong value for host_perio_tx_fifo_size\\n\");\n+\t\tDWC_WARN(\"host_perio_tx_fifo_size must be 16-32768\\n\");\n+\t\treturn -DWC_E_INVALID;\n+\t}\n+\n+\tif (val > ((core_if->hptxfsiz.d32) >> 16)) {\n+\t\tif (dwc_otg_param_initialized\n+\t\t    (core_if->core_params->host_perio_tx_fifo_size)) {\n+\t\t\tDWC_ERROR\n+\t\t\t    (\"%d invalid for host_perio_tx_fifo_size. Check HW configuration.\\n\",\n+\t\t\t     val);\n+\t\t}\n+\t\tval = (core_if->hptxfsiz.d32) >> 16;\n+\t\tretval = -DWC_E_INVALID;\n+\t}\n+\n+\tcore_if->core_params->host_perio_tx_fifo_size = val;\n+\treturn retval;\n+}\n+\n+int32_t dwc_otg_get_param_host_perio_tx_fifo_size(dwc_otg_core_if_t * core_if)\n+{\n+\treturn core_if->core_params->host_perio_tx_fifo_size;\n+}\n+\n+int dwc_otg_set_param_max_transfer_size(dwc_otg_core_if_t * core_if,\n+\t\t\t\t\tint32_t val)\n+{\n+\tint retval = 0;\n+\n+\tif (DWC_OTG_PARAM_TEST(val, 2047, 524288)) {\n+\t\tDWC_WARN(\"Wrong value for max_transfer_size\\n\");\n+\t\tDWC_WARN(\"max_transfer_size must be 2047-524288\\n\");\n+\t\treturn -DWC_E_INVALID;\n+\t}\n+\n+\tif (val >= (1 << (core_if->hwcfg3.b.xfer_size_cntr_width + 11))) {\n+\t\tif (dwc_otg_param_initialized\n+\t\t    (core_if->core_params->max_transfer_size)) {\n+\t\t\tDWC_ERROR\n+\t\t\t    (\"%d invalid for max_transfer_size. Check HW configuration.\\n\",\n+\t\t\t     val);\n+\t\t}\n+\t\tval =\n+\t\t    ((1 << (core_if->hwcfg3.b.packet_size_cntr_width + 11)) -\n+\t\t     1);\n+\t\tretval = -DWC_E_INVALID;\n+\t}\n+\n+\tcore_if->core_params->max_transfer_size = val;\n+\treturn retval;\n+}\n+\n+int32_t dwc_otg_get_param_max_transfer_size(dwc_otg_core_if_t * core_if)\n+{\n+\treturn core_if->core_params->max_transfer_size;\n+}\n+\n+int dwc_otg_set_param_max_packet_count(dwc_otg_core_if_t * core_if, int32_t val)\n+{\n+\tint retval = 0;\n+\n+\tif (DWC_OTG_PARAM_TEST(val, 15, 511)) {\n+\t\tDWC_WARN(\"Wrong value for max_packet_count\\n\");\n+\t\tDWC_WARN(\"max_packet_count must be 15-511\\n\");\n+\t\treturn -DWC_E_INVALID;\n+\t}\n+\n+\tif (val > (1 << (core_if->hwcfg3.b.packet_size_cntr_width + 4))) {\n+\t\tif (dwc_otg_param_initialized\n+\t\t    (core_if->core_params->max_packet_count)) {\n+\t\t\tDWC_ERROR\n+\t\t\t    (\"%d invalid for max_packet_count. Check HW configuration.\\n\",\n+\t\t\t     val);\n+\t\t}\n+\t\tval =\n+\t\t    ((1 << (core_if->hwcfg3.b.packet_size_cntr_width + 4)) - 1);\n+\t\tretval = -DWC_E_INVALID;\n+\t}\n+\n+\tcore_if->core_params->max_packet_count = val;\n+\treturn retval;\n+}\n+\n+int32_t dwc_otg_get_param_max_packet_count(dwc_otg_core_if_t * core_if)\n+{\n+\treturn core_if->core_params->max_packet_count;\n+}\n+\n+int dwc_otg_set_param_host_channels(dwc_otg_core_if_t * core_if, int32_t val)\n+{\n+\tint retval = 0;\n+\n+\tif (DWC_OTG_PARAM_TEST(val, 1, 16)) {\n+\t\tDWC_WARN(\"Wrong value for host_channels\\n\");\n+\t\tDWC_WARN(\"host_channels must be 1-16\\n\");\n+\t\treturn -DWC_E_INVALID;\n+\t}\n+\n+\tif (val > (core_if->hwcfg2.b.num_host_chan + 1)) {\n+\t\tif (dwc_otg_param_initialized\n+\t\t    (core_if->core_params->host_channels)) {\n+\t\t\tDWC_ERROR\n+\t\t\t    (\"%d invalid for host_channels. Check HW configurations.\\n\",\n+\t\t\t     val);\n+\t\t}\n+\t\tval = (core_if->hwcfg2.b.num_host_chan + 1);\n+\t\tretval = -DWC_E_INVALID;\n+\t}\n+\n+\tcore_if->core_params->host_channels = val;\n+\treturn retval;\n+}\n+\n+int32_t dwc_otg_get_param_host_channels(dwc_otg_core_if_t * core_if)\n+{\n+\treturn core_if->core_params->host_channels;\n+}\n+\n+int dwc_otg_set_param_dev_endpoints(dwc_otg_core_if_t * core_if, int32_t val)\n+{\n+\tint retval = 0;\n+\n+\tif (DWC_OTG_PARAM_TEST(val, 1, 15)) {\n+\t\tDWC_WARN(\"Wrong value for dev_endpoints\\n\");\n+\t\tDWC_WARN(\"dev_endpoints must be 1-15\\n\");\n+\t\treturn -DWC_E_INVALID;\n+\t}\n+\n+\tif (val > (core_if->hwcfg2.b.num_dev_ep)) {\n+\t\tif (dwc_otg_param_initialized\n+\t\t    (core_if->core_params->dev_endpoints)) {\n+\t\t\tDWC_ERROR\n+\t\t\t    (\"%d invalid for dev_endpoints. Check HW configurations.\\n\",\n+\t\t\t     val);\n+\t\t}\n+\t\tval = core_if->hwcfg2.b.num_dev_ep;\n+\t\tretval = -DWC_E_INVALID;\n+\t}\n+\n+\tcore_if->core_params->dev_endpoints = val;\n+\treturn retval;\n+}\n+\n+int32_t dwc_otg_get_param_dev_endpoints(dwc_otg_core_if_t * core_if)\n+{\n+\treturn core_if->core_params->dev_endpoints;\n+}\n+\n+int dwc_otg_set_param_phy_type(dwc_otg_core_if_t * core_if, int32_t val)\n+{\n+\tint retval = 0;\n+\tint valid = 0;\n+\n+\tif (DWC_OTG_PARAM_TEST(val, 0, 2)) {\n+\t\tDWC_WARN(\"Wrong value for phy_type\\n\");\n+\t\tDWC_WARN(\"phy_type must be 0,1 or 2\\n\");\n+\t\treturn -DWC_E_INVALID;\n+\t}\n+#ifndef NO_FS_PHY_HW_CHECKS\n+\tif ((val == DWC_PHY_TYPE_PARAM_UTMI) &&\n+\t    ((core_if->hwcfg2.b.hs_phy_type == 1) ||\n+\t     (core_if->hwcfg2.b.hs_phy_type == 3))) {\n+\t\tvalid = 1;\n+\t} else if ((val == DWC_PHY_TYPE_PARAM_ULPI) &&\n+\t\t   ((core_if->hwcfg2.b.hs_phy_type == 2) ||\n+\t\t    (core_if->hwcfg2.b.hs_phy_type == 3))) {\n+\t\tvalid = 1;\n+\t} else if ((val == DWC_PHY_TYPE_PARAM_FS) &&\n+\t\t   (core_if->hwcfg2.b.fs_phy_type == 1)) {\n+\t\tvalid = 1;\n+\t}\n+\tif (!valid) {\n+\t\tif (dwc_otg_param_initialized(core_if->core_params->phy_type)) {\n+\t\t\tDWC_ERROR\n+\t\t\t    (\"%d invalid for phy_type. Check HW configurations.\\n\",\n+\t\t\t     val);\n+\t\t}\n+\t\tif (core_if->hwcfg2.b.hs_phy_type) {\n+\t\t\tif ((core_if->hwcfg2.b.hs_phy_type == 3) ||\n+\t\t\t    (core_if->hwcfg2.b.hs_phy_type == 1)) {\n+\t\t\t\tval = DWC_PHY_TYPE_PARAM_UTMI;\n+\t\t\t} else {\n+\t\t\t\tval = DWC_PHY_TYPE_PARAM_ULPI;\n+\t\t\t}\n+\t\t}\n+\t\tretval = -DWC_E_INVALID;\n+\t}\n+#endif\n+\tcore_if->core_params->phy_type = val;\n+\treturn retval;\n+}\n+\n+int32_t dwc_otg_get_param_phy_type(dwc_otg_core_if_t * core_if)\n+{\n+\treturn core_if->core_params->phy_type;\n+}\n+\n+int dwc_otg_set_param_speed(dwc_otg_core_if_t * core_if, int32_t val)\n+{\n+\tint retval = 0;\n+\tif (DWC_OTG_PARAM_TEST(val, 0, 1)) {\n+\t\tDWC_WARN(\"Wrong value for speed parameter\\n\");\n+\t\tDWC_WARN(\"max_speed parameter must be 0 or 1\\n\");\n+\t\treturn -DWC_E_INVALID;\n+\t}\n+\tif ((val == 0)\n+\t    && dwc_otg_get_param_phy_type(core_if) == DWC_PHY_TYPE_PARAM_FS) {\n+\t\tif (dwc_otg_param_initialized(core_if->core_params->speed)) {\n+\t\t\tDWC_ERROR\n+\t\t\t    (\"%d invalid for speed paremter. Check HW configuration.\\n\",\n+\t\t\t     val);\n+\t\t}\n+\t\tval =\n+\t\t    (dwc_otg_get_param_phy_type(core_if) ==\n+\t\t     DWC_PHY_TYPE_PARAM_FS ? 1 : 0);\n+\t\tretval = -DWC_E_INVALID;\n+\t}\n+\tcore_if->core_params->speed = val;\n+\treturn retval;\n+}\n+\n+int32_t dwc_otg_get_param_speed(dwc_otg_core_if_t * core_if)\n+{\n+\treturn core_if->core_params->speed;\n+}\n+\n+int dwc_otg_set_param_host_ls_low_power_phy_clk(dwc_otg_core_if_t * core_if,\n+\t\t\t\t\t\tint32_t val)\n+{\n+\tint retval = 0;\n+\n+\tif (DWC_OTG_PARAM_TEST(val, 0, 1)) {\n+\t\tDWC_WARN\n+\t\t    (\"Wrong value for host_ls_low_power_phy_clk parameter\\n\");\n+\t\tDWC_WARN(\"host_ls_low_power_phy_clk must be 0 or 1\\n\");\n+\t\treturn -DWC_E_INVALID;\n+\t}\n+\n+\tif ((val == DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ)\n+\t    && (dwc_otg_get_param_phy_type(core_if) == DWC_PHY_TYPE_PARAM_FS)) {\n+\t\tif (dwc_otg_param_initialized\n+\t\t    (core_if->core_params->host_ls_low_power_phy_clk)) {\n+\t\t\tDWC_ERROR\n+\t\t\t    (\"%d invalid for host_ls_low_power_phy_clk. Check HW configuration.\\n\",\n+\t\t\t     val);\n+\t\t}\n+\t\tval =\n+\t\t    (dwc_otg_get_param_phy_type(core_if) ==\n+\t\t     DWC_PHY_TYPE_PARAM_FS) ?\n+\t\t    DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ :\n+\t\t    DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ;\n+\t\tretval = -DWC_E_INVALID;\n+\t}\n+\n+\tcore_if->core_params->host_ls_low_power_phy_clk = val;\n+\treturn retval;\n+}\n+\n+int32_t dwc_otg_get_param_host_ls_low_power_phy_clk(dwc_otg_core_if_t * core_if)\n+{\n+\treturn core_if->core_params->host_ls_low_power_phy_clk;\n+}\n+\n+int dwc_otg_set_param_phy_ulpi_ddr(dwc_otg_core_if_t * core_if, int32_t val)\n+{\n+\tif (DWC_OTG_PARAM_TEST(val, 0, 1)) {\n+\t\tDWC_WARN(\"Wrong value for phy_ulpi_ddr\\n\");\n+\t\tDWC_WARN(\"phy_upli_ddr must be 0 or 1\\n\");\n+\t\treturn -DWC_E_INVALID;\n+\t}\n+\n+\tcore_if->core_params->phy_ulpi_ddr = val;\n+\treturn 0;\n+}\n+\n+int32_t dwc_otg_get_param_phy_ulpi_ddr(dwc_otg_core_if_t * core_if)\n+{\n+\treturn core_if->core_params->phy_ulpi_ddr;\n+}\n+\n+int dwc_otg_set_param_phy_ulpi_ext_vbus(dwc_otg_core_if_t * core_if,\n+\t\t\t\t\tint32_t val)\n+{\n+\tif (DWC_OTG_PARAM_TEST(val, 0, 1)) {\n+\t\tDWC_WARN(\"Wrong valaue for phy_ulpi_ext_vbus\\n\");\n+\t\tDWC_WARN(\"phy_ulpi_ext_vbus must be 0 or 1\\n\");\n+\t\treturn -DWC_E_INVALID;\n+\t}\n+\n+\tcore_if->core_params->phy_ulpi_ext_vbus = val;\n+\treturn 0;\n+}\n+\n+int32_t dwc_otg_get_param_phy_ulpi_ext_vbus(dwc_otg_core_if_t * core_if)\n+{\n+\treturn core_if->core_params->phy_ulpi_ext_vbus;\n+}\n+\n+int dwc_otg_set_param_phy_utmi_width(dwc_otg_core_if_t * core_if, int32_t val)\n+{\n+\tif (DWC_OTG_PARAM_TEST(val, 8, 8) && DWC_OTG_PARAM_TEST(val, 16, 16)) {\n+\t\tDWC_WARN(\"Wrong valaue for phy_utmi_width\\n\");\n+\t\tDWC_WARN(\"phy_utmi_width must be 8 or 16\\n\");\n+\t\treturn -DWC_E_INVALID;\n+\t}\n+\n+\tcore_if->core_params->phy_utmi_width = val;\n+\treturn 0;\n+}\n+\n+int32_t dwc_otg_get_param_phy_utmi_width(dwc_otg_core_if_t * core_if)\n+{\n+\treturn core_if->core_params->phy_utmi_width;\n+}\n+\n+int dwc_otg_set_param_ulpi_fs_ls(dwc_otg_core_if_t * core_if, int32_t val)\n+{\n+\tif (DWC_OTG_PARAM_TEST(val, 0, 1)) {\n+\t\tDWC_WARN(\"Wrong valaue for ulpi_fs_ls\\n\");\n+\t\tDWC_WARN(\"ulpi_fs_ls must be 0 or 1\\n\");\n+\t\treturn -DWC_E_INVALID;\n+\t}\n+\n+\tcore_if->core_params->ulpi_fs_ls = val;\n+\treturn 0;\n+}\n+\n+int32_t dwc_otg_get_param_ulpi_fs_ls(dwc_otg_core_if_t * core_if)\n+{\n+\treturn core_if->core_params->ulpi_fs_ls;\n+}\n+\n+int dwc_otg_set_param_ts_dline(dwc_otg_core_if_t * core_if, int32_t val)\n+{\n+\tif (DWC_OTG_PARAM_TEST(val, 0, 1)) {\n+\t\tDWC_WARN(\"Wrong valaue for ts_dline\\n\");\n+\t\tDWC_WARN(\"ts_dline must be 0 or 1\\n\");\n+\t\treturn -DWC_E_INVALID;\n+\t}\n+\n+\tcore_if->core_params->ts_dline = val;\n+\treturn 0;\n+}\n+\n+int32_t dwc_otg_get_param_ts_dline(dwc_otg_core_if_t * core_if)\n+{\n+\treturn core_if->core_params->ts_dline;\n+}\n+\n+int dwc_otg_set_param_i2c_enable(dwc_otg_core_if_t * core_if, int32_t val)\n+{\n+\tint retval = 0;\n+\tif (DWC_OTG_PARAM_TEST(val, 0, 1)) {\n+\t\tDWC_WARN(\"Wrong valaue for i2c_enable\\n\");\n+\t\tDWC_WARN(\"i2c_enable must be 0 or 1\\n\");\n+\t\treturn -DWC_E_INVALID;\n+\t}\n+#ifndef NO_FS_PHY_HW_CHECK\n+\tif (val == 1 && core_if->hwcfg3.b.i2c == 0) {\n+\t\tif (dwc_otg_param_initialized(core_if->core_params->i2c_enable)) {\n+\t\t\tDWC_ERROR\n+\t\t\t    (\"%d invalid for i2c_enable. Check HW configuration.\\n\",\n+\t\t\t     val);\n+\t\t}\n+\t\tval = 0;\n+\t\tretval = -DWC_E_INVALID;\n+\t}\n+#endif\n+\n+\tcore_if->core_params->i2c_enable = val;\n+\treturn retval;\n+}\n+\n+int32_t dwc_otg_get_param_i2c_enable(dwc_otg_core_if_t * core_if)\n+{\n+\treturn core_if->core_params->i2c_enable;\n+}\n+\n+int dwc_otg_set_param_dev_perio_tx_fifo_size(dwc_otg_core_if_t * core_if,\n+\t\t\t\t\t     int32_t val, int fifo_num)\n+{\n+\tint retval = 0;\n+\n+\tif (DWC_OTG_PARAM_TEST(val, 4, 768)) {\n+\t\tDWC_WARN(\"Wrong value for dev_perio_tx_fifo_size\\n\");\n+\t\tDWC_WARN(\"dev_perio_tx_fifo_size must be 4-768\\n\");\n+\t\treturn -DWC_E_INVALID;\n+\t}\n+\n+\tif (val >\n+\t    (DWC_READ_REG32(&core_if->core_global_regs->dtxfsiz[fifo_num]))) {\n+\t\tif (dwc_otg_param_initialized\n+\t\t    (core_if->core_params->dev_perio_tx_fifo_size[fifo_num])) {\n+\t\t\tDWC_ERROR\n+\t\t\t    (\"`%d' invalid for parameter `dev_perio_fifo_size_%d'. Check HW configuration.\\n\",\n+\t\t\t     val, fifo_num);\n+\t\t}\n+\t\tval = (DWC_READ_REG32(&core_if->core_global_regs->dtxfsiz[fifo_num]));\n+\t\tretval = -DWC_E_INVALID;\n+\t}\n+\n+\tcore_if->core_params->dev_perio_tx_fifo_size[fifo_num] = val;\n+\treturn retval;\n+}\n+\n+int32_t dwc_otg_get_param_dev_perio_tx_fifo_size(dwc_otg_core_if_t * core_if,\n+\t\t\t\t\t\t int fifo_num)\n+{\n+\treturn core_if->core_params->dev_perio_tx_fifo_size[fifo_num];\n+}\n+\n+int dwc_otg_set_param_en_multiple_tx_fifo(dwc_otg_core_if_t * core_if,\n+\t\t\t\t\t  int32_t val)\n+{\n+\tint retval = 0;\n+\tif (DWC_OTG_PARAM_TEST(val, 0, 1)) {\n+\t\tDWC_WARN(\"Wrong valaue for en_multiple_tx_fifo,\\n\");\n+\t\tDWC_WARN(\"en_multiple_tx_fifo must be 0 or 1\\n\");\n+\t\treturn -DWC_E_INVALID;\n+\t}\n+\n+\tif (val == 1 && core_if->hwcfg4.b.ded_fifo_en == 0) {\n+\t\tif (dwc_otg_param_initialized\n+\t\t    (core_if->core_params->en_multiple_tx_fifo)) {\n+\t\t\tDWC_ERROR\n+\t\t\t    (\"%d invalid for parameter en_multiple_tx_fifo. Check HW configuration.\\n\",\n+\t\t\t     val);\n+\t\t}\n+\t\tval = 0;\n+\t\tretval = -DWC_E_INVALID;\n+\t}\n+\n+\tcore_if->core_params->en_multiple_tx_fifo = val;\n+\treturn retval;\n+}\n+\n+int32_t dwc_otg_get_param_en_multiple_tx_fifo(dwc_otg_core_if_t * core_if)\n+{\n+\treturn core_if->core_params->en_multiple_tx_fifo;\n+}\n+\n+int dwc_otg_set_param_dev_tx_fifo_size(dwc_otg_core_if_t * core_if, int32_t val,\n+\t\t\t\t       int fifo_num)\n+{\n+\tint retval = 0;\n+\n+\tif (DWC_OTG_PARAM_TEST(val, 4, 768)) {\n+\t\tDWC_WARN(\"Wrong value for dev_tx_fifo_size\\n\");\n+\t\tDWC_WARN(\"dev_tx_fifo_size must be 4-768\\n\");\n+\t\treturn -DWC_E_INVALID;\n+\t}\n+\n+\tif (val >\n+\t    (DWC_READ_REG32(&core_if->core_global_regs->dtxfsiz[fifo_num]))) {\n+\t\tif (dwc_otg_param_initialized\n+\t\t    (core_if->core_params->dev_tx_fifo_size[fifo_num])) {\n+\t\t\tDWC_ERROR\n+\t\t\t    (\"`%d' invalid for parameter `dev_tx_fifo_size_%d'. Check HW configuration.\\n\",\n+\t\t\t     val, fifo_num);\n+\t\t}\n+\t\tval = (DWC_READ_REG32(&core_if->core_global_regs->dtxfsiz[fifo_num]));\n+\t\tretval = -DWC_E_INVALID;\n+\t}\n+\n+\tcore_if->core_params->dev_tx_fifo_size[fifo_num] = val;\n+\treturn retval;\n+}\n+\n+int32_t dwc_otg_get_param_dev_tx_fifo_size(dwc_otg_core_if_t * core_if,\n+\t\t\t\t\t   int fifo_num)\n+{\n+\treturn core_if->core_params->dev_tx_fifo_size[fifo_num];\n+}\n+\n+int dwc_otg_set_param_thr_ctl(dwc_otg_core_if_t * core_if, int32_t val)\n+{\n+\tint retval = 0;\n+\n+\tif (DWC_OTG_PARAM_TEST(val, 0, 7)) {\n+\t\tDWC_WARN(\"Wrong value for thr_ctl\\n\");\n+\t\tDWC_WARN(\"thr_ctl must be 0-7\\n\");\n+\t\treturn -DWC_E_INVALID;\n+\t}\n+\n+\tif ((val != 0) &&\n+\t    (!dwc_otg_get_param_dma_enable(core_if) ||\n+\t     !core_if->hwcfg4.b.ded_fifo_en)) {\n+\t\tif (dwc_otg_param_initialized(core_if->core_params->thr_ctl)) {\n+\t\t\tDWC_ERROR\n+\t\t\t    (\"%d invalid for parameter thr_ctl. Check HW configuration.\\n\",\n+\t\t\t     val);\n+\t\t}\n+\t\tval = 0;\n+\t\tretval = -DWC_E_INVALID;\n+\t}\n+\n+\tcore_if->core_params->thr_ctl = val;\n+\treturn retval;\n+}\n+\n+int32_t dwc_otg_get_param_thr_ctl(dwc_otg_core_if_t * core_if)\n+{\n+\treturn core_if->core_params->thr_ctl;\n+}\n+\n+int dwc_otg_set_param_lpm_enable(dwc_otg_core_if_t * core_if, int32_t val)\n+{\n+\tint retval = 0;\n+\n+\tif (DWC_OTG_PARAM_TEST(val, 0, 1)) {\n+\t\tDWC_WARN(\"Wrong value for lpm_enable\\n\");\n+\t\tDWC_WARN(\"lpm_enable must be 0 or 1\\n\");\n+\t\treturn -DWC_E_INVALID;\n+\t}\n+\n+\tif (val && !core_if->hwcfg3.b.otg_lpm_en) {\n+\t\tif (dwc_otg_param_initialized(core_if->core_params->lpm_enable)) {\n+\t\t\tDWC_ERROR\n+\t\t\t    (\"%d invalid for parameter lpm_enable. Check HW configuration.\\n\",\n+\t\t\t     val);\n+\t\t}\n+\t\tval = 0;\n+\t\tretval = -DWC_E_INVALID;\n+\t}\n+\n+\tcore_if->core_params->lpm_enable = val;\n+\treturn retval;\n+}\n+\n+int32_t dwc_otg_get_param_lpm_enable(dwc_otg_core_if_t * core_if)\n+{\n+\treturn core_if->core_params->lpm_enable;\n+}\n+\n+int dwc_otg_set_param_tx_thr_length(dwc_otg_core_if_t * core_if, int32_t val)\n+{\n+\tif (DWC_OTG_PARAM_TEST(val, 8, 128)) {\n+\t\tDWC_WARN(\"Wrong valaue for tx_thr_length\\n\");\n+\t\tDWC_WARN(\"tx_thr_length must be 8 - 128\\n\");\n+\t\treturn -DWC_E_INVALID;\n+\t}\n+\n+\tcore_if->core_params->tx_thr_length = val;\n+\treturn 0;\n+}\n+\n+int32_t dwc_otg_get_param_tx_thr_length(dwc_otg_core_if_t * core_if)\n+{\n+\treturn core_if->core_params->tx_thr_length;\n+}\n+\n+int dwc_otg_set_param_rx_thr_length(dwc_otg_core_if_t * core_if, int32_t val)\n+{\n+\tif (DWC_OTG_PARAM_TEST(val, 8, 128)) {\n+\t\tDWC_WARN(\"Wrong valaue for rx_thr_length\\n\");\n+\t\tDWC_WARN(\"rx_thr_length must be 8 - 128\\n\");\n+\t\treturn -DWC_E_INVALID;\n+\t}\n+\n+\tcore_if->core_params->rx_thr_length = val;\n+\treturn 0;\n+}\n+\n+int32_t dwc_otg_get_param_rx_thr_length(dwc_otg_core_if_t * core_if)\n+{\n+\treturn core_if->core_params->rx_thr_length;\n+}\n+\n+int dwc_otg_set_param_dma_burst_size(dwc_otg_core_if_t * core_if, int32_t val)\n+{\n+\tif (DWC_OTG_PARAM_TEST(val, 1, 1) &&\n+\t    DWC_OTG_PARAM_TEST(val, 4, 4) &&\n+\t    DWC_OTG_PARAM_TEST(val, 8, 8) &&\n+\t    DWC_OTG_PARAM_TEST(val, 16, 16) &&\n+\t    DWC_OTG_PARAM_TEST(val, 32, 32) &&\n+\t    DWC_OTG_PARAM_TEST(val, 64, 64) &&\n+\t    DWC_OTG_PARAM_TEST(val, 128, 128) &&\n+\t    DWC_OTG_PARAM_TEST(val, 256, 256)) {\n+\t\tDWC_WARN(\"`%d' invalid for parameter `dma_burst_size'\\n\", val);\n+\t\treturn -DWC_E_INVALID;\n+\t}\n+\tcore_if->core_params->dma_burst_size = val;\n+\treturn 0;\n+}\n+\n+int32_t dwc_otg_get_param_dma_burst_size(dwc_otg_core_if_t * core_if)\n+{\n+\treturn core_if->core_params->dma_burst_size;\n+}\n+\n+int dwc_otg_set_param_pti_enable(dwc_otg_core_if_t * core_if, int32_t val)\n+{\n+\tint retval = 0;\n+\tif (DWC_OTG_PARAM_TEST(val, 0, 1)) {\n+\t\tDWC_WARN(\"`%d' invalid for parameter `pti_enable'\\n\", val);\n+\t\treturn -DWC_E_INVALID;\n+\t}\n+\tif (val && (core_if->snpsid < OTG_CORE_REV_2_72a)) {\n+\t\tif (dwc_otg_param_initialized(core_if->core_params->pti_enable)) {\n+\t\t\tDWC_ERROR\n+\t\t\t    (\"%d invalid for parameter pti_enable. Check HW configuration.\\n\",\n+\t\t\t     val);\n+\t\t}\n+\t\tretval = -DWC_E_INVALID;\n+\t\tval = 0;\n+\t}\n+\tcore_if->core_params->pti_enable = val;\n+\treturn retval;\n+}\n+\n+int32_t dwc_otg_get_param_pti_enable(dwc_otg_core_if_t * core_if)\n+{\n+\treturn core_if->core_params->pti_enable;\n+}\n+\n+int dwc_otg_set_param_mpi_enable(dwc_otg_core_if_t * core_if, int32_t val)\n+{\n+\tint retval = 0;\n+\tif (DWC_OTG_PARAM_TEST(val, 0, 1)) {\n+\t\tDWC_WARN(\"`%d' invalid for parameter `mpi_enable'\\n\", val);\n+\t\treturn -DWC_E_INVALID;\n+\t}\n+\tif (val && (core_if->hwcfg2.b.multi_proc_int == 0)) {\n+\t\tif (dwc_otg_param_initialized(core_if->core_params->mpi_enable)) {\n+\t\t\tDWC_ERROR\n+\t\t\t    (\"%d invalid for parameter mpi_enable. Check HW configuration.\\n\",\n+\t\t\t     val);\n+\t\t}\n+\t\tretval = -DWC_E_INVALID;\n+\t\tval = 0;\n+\t}\n+\tcore_if->core_params->mpi_enable = val;\n+\treturn retval;\n+}\n+\n+int32_t dwc_otg_get_param_mpi_enable(dwc_otg_core_if_t * core_if)\n+{\n+\treturn core_if->core_params->mpi_enable;\n+}\n+\n+int dwc_otg_set_param_adp_enable(dwc_otg_core_if_t * core_if, int32_t val)\n+{\n+\tint retval = 0;\n+\tif (DWC_OTG_PARAM_TEST(val, 0, 1)) {\n+\t\tDWC_WARN(\"`%d' invalid for parameter `adp_enable'\\n\", val);\n+\t\treturn -DWC_E_INVALID;\n+\t}\n+\tif (val && (core_if->hwcfg3.b.adp_supp == 0)) {\n+\t\tif (dwc_otg_param_initialized\n+\t\t    (core_if->core_params->adp_supp_enable)) {\n+\t\t\tDWC_ERROR\n+\t\t\t    (\"%d invalid for parameter adp_enable. Check HW configuration.\\n\",\n+\t\t\t     val);\n+\t\t}\n+\t\tretval = -DWC_E_INVALID;\n+\t\tval = 0;\n+\t}\n+\tcore_if->core_params->adp_supp_enable = val;\n+\t/*Set OTG version 2.0 in case of enabling ADP*/\n+\tif (val)\n+\t\tdwc_otg_set_param_otg_ver(core_if, 1);\n+\n+\treturn retval;\n+}\n+\n+int32_t dwc_otg_get_param_adp_enable(dwc_otg_core_if_t * core_if)\n+{\n+\treturn core_if->core_params->adp_supp_enable;\n+}\n+\n+int dwc_otg_set_param_ic_usb_cap(dwc_otg_core_if_t * core_if, int32_t val)\n+{\n+\tint retval = 0;\n+\tif (DWC_OTG_PARAM_TEST(val, 0, 1)) {\n+\t\tDWC_WARN(\"`%d' invalid for parameter `ic_usb_cap'\\n\", val);\n+\t\tDWC_WARN(\"ic_usb_cap must be 0 or 1\\n\");\n+\t\treturn -DWC_E_INVALID;\n+\t}\n+\n+\tif (val && (core_if->hwcfg2.b.otg_enable_ic_usb == 0)) {\n+\t\tif (dwc_otg_param_initialized(core_if->core_params->ic_usb_cap)) {\n+\t\t\tDWC_ERROR\n+\t\t\t    (\"%d invalid for parameter ic_usb_cap. Check HW configuration.\\n\",\n+\t\t\t     val);\n+\t\t}\n+\t\tretval = -DWC_E_INVALID;\n+\t\tval = 0;\n+\t}\n+\tcore_if->core_params->ic_usb_cap = val;\n+\treturn retval;\n+}\n+\n+int32_t dwc_otg_get_param_ic_usb_cap(dwc_otg_core_if_t * core_if)\n+{\n+\treturn core_if->core_params->ic_usb_cap;\n+}\n+\n+int dwc_otg_set_param_ahb_thr_ratio(dwc_otg_core_if_t * core_if, int32_t val)\n+{\n+\tint retval = 0;\n+\tint valid = 1;\n+\n+\tif (DWC_OTG_PARAM_TEST(val, 0, 3)) {\n+\t\tDWC_WARN(\"`%d' invalid for parameter `ahb_thr_ratio'\\n\", val);\n+\t\tDWC_WARN(\"ahb_thr_ratio must be 0 - 3\\n\");\n+\t\treturn -DWC_E_INVALID;\n+\t}\n+\n+\tif (val\n+\t    && (core_if->snpsid < OTG_CORE_REV_2_81a\n+\t\t|| !dwc_otg_get_param_thr_ctl(core_if))) {\n+\t\tvalid = 0;\n+\t} else if (val\n+\t\t   && ((dwc_otg_get_param_tx_thr_length(core_if) / (1 << val)) <\n+\t\t       4)) {\n+\t\tvalid = 0;\n+\t}\n+\tif (valid == 0) {\n+\t\tif (dwc_otg_param_initialized\n+\t\t    (core_if->core_params->ahb_thr_ratio)) {\n+\t\t\tDWC_ERROR\n+\t\t\t    (\"%d invalid for parameter ahb_thr_ratio. Check HW configuration.\\n\",\n+\t\t\t     val);\n+\t\t}\n+\t\tretval = -DWC_E_INVALID;\n+\t\tval = 0;\n+\t}\n+\n+\tcore_if->core_params->ahb_thr_ratio = val;\n+\treturn retval;\n+}\n+\n+int32_t dwc_otg_get_param_ahb_thr_ratio(dwc_otg_core_if_t * core_if)\n+{\n+\treturn core_if->core_params->ahb_thr_ratio;\n+}\n+\n+int dwc_otg_set_param_power_down(dwc_otg_core_if_t * core_if, int32_t val)\n+{\n+\tint retval = 0;\n+\tint valid = 1;\n+\thwcfg4_data_t hwcfg4 = {.d32 = 0 };\n+\thwcfg4.d32 = DWC_READ_REG32(&core_if->core_global_regs->ghwcfg4);\n+\n+\tif (DWC_OTG_PARAM_TEST(val, 0, 3)) {\n+\t\tDWC_WARN(\"`%d' invalid for parameter `power_down'\\n\", val);\n+\t\tDWC_WARN(\"power_down must be 0 - 2\\n\");\n+\t\treturn -DWC_E_INVALID;\n+\t}\n+\n+\tif ((val == 2) && (core_if->snpsid < OTG_CORE_REV_2_91a)) {\n+\t\tvalid = 0;\n+\t}\n+\tif ((val == 3)\n+\t    && ((core_if->snpsid < OTG_CORE_REV_3_00a)\n+\t\t|| (hwcfg4.b.xhiber == 0))) {\n+\t\tvalid = 0;\n+\t}\n+\tif (valid == 0) {\n+\t\tif (dwc_otg_param_initialized(core_if->core_params->power_down)) {\n+\t\t\tDWC_ERROR\n+\t\t\t    (\"%d invalid for parameter power_down. Check HW configuration.\\n\",\n+\t\t\t     val);\n+\t\t}\n+\t\tretval = -DWC_E_INVALID;\n+\t\tval = 0;\n+\t}\n+\tcore_if->core_params->power_down = val;\n+\treturn retval;\n+}\n+\n+int32_t dwc_otg_get_param_power_down(dwc_otg_core_if_t * core_if)\n+{\n+\treturn core_if->core_params->power_down;\n+}\n+\n+int dwc_otg_set_param_reload_ctl(dwc_otg_core_if_t * core_if, int32_t val)\n+{\n+\tint retval = 0;\n+\tint valid = 1;\n+\n+\tif (DWC_OTG_PARAM_TEST(val, 0, 1)) {\n+\t\tDWC_WARN(\"`%d' invalid for parameter `reload_ctl'\\n\", val);\n+\t\tDWC_WARN(\"reload_ctl must be 0 or 1\\n\");\n+\t\treturn -DWC_E_INVALID;\n+\t}\n+\n+\tif ((val == 1) && (core_if->snpsid < OTG_CORE_REV_2_92a)) {\n+\t\tvalid = 0;\n+\t}\n+\tif (valid == 0) {\n+\t\tif (dwc_otg_param_initialized(core_if->core_params->reload_ctl)) {\n+\t\t\tDWC_ERROR(\"%d invalid for parameter reload_ctl.\"\n+\t\t\t\t  \"Check HW configuration.\\n\", val);\n+\t\t}\n+\t\tretval = -DWC_E_INVALID;\n+\t\tval = 0;\n+\t}\n+\tcore_if->core_params->reload_ctl = val;\n+\treturn retval;\n+}\n+\n+int32_t dwc_otg_get_param_reload_ctl(dwc_otg_core_if_t * core_if)\n+{\n+\treturn core_if->core_params->reload_ctl;\n+}\n+\n+int dwc_otg_set_param_dev_out_nak(dwc_otg_core_if_t * core_if, int32_t val)\n+{\n+\tint retval = 0;\n+\tint valid = 1;\n+\n+\tif (DWC_OTG_PARAM_TEST(val, 0, 1)) {\n+\t\tDWC_WARN(\"`%d' invalid for parameter `dev_out_nak'\\n\", val);\n+\t\tDWC_WARN(\"dev_out_nak must be 0 or 1\\n\");\n+\t\treturn -DWC_E_INVALID;\n+\t}\n+\n+\tif ((val == 1) && ((core_if->snpsid < OTG_CORE_REV_2_93a) ||\n+\t\t!(core_if->core_params->dma_desc_enable))) {\n+\t\tvalid = 0;\n+\t}\n+\tif (valid == 0) {\n+\t\tif (dwc_otg_param_initialized(core_if->core_params->dev_out_nak)) {\n+\t\t\tDWC_ERROR(\"%d invalid for parameter dev_out_nak.\"\n+\t\t\t\t\"Check HW configuration.\\n\", val);\n+\t\t}\n+\t\tretval = -DWC_E_INVALID;\n+\t\tval = 0;\n+\t}\n+\tcore_if->core_params->dev_out_nak = val;\n+\treturn retval;\n+}\n+\n+int32_t dwc_otg_get_param_dev_out_nak(dwc_otg_core_if_t * core_if)\n+{\n+\treturn core_if->core_params->dev_out_nak;\n+}\n+\n+int dwc_otg_set_param_cont_on_bna(dwc_otg_core_if_t * core_if, int32_t val)\n+{\n+\tint retval = 0;\n+\tint valid = 1;\n+\n+\tif (DWC_OTG_PARAM_TEST(val, 0, 1)) {\n+\t\tDWC_WARN(\"`%d' invalid for parameter `cont_on_bna'\\n\", val);\n+\t\tDWC_WARN(\"cont_on_bna must be 0 or 1\\n\");\n+\t\treturn -DWC_E_INVALID;\n+\t}\n+\n+\tif ((val == 1) && ((core_if->snpsid < OTG_CORE_REV_2_94a) ||\n+\t\t!(core_if->core_params->dma_desc_enable))) {\n+\t\t\tvalid = 0;\n+\t}\n+\tif (valid == 0) {\n+\t\tif (dwc_otg_param_initialized(core_if->core_params->cont_on_bna)) {\n+\t\t\tDWC_ERROR(\"%d invalid for parameter cont_on_bna.\"\n+\t\t\t\t\"Check HW configuration.\\n\", val);\n+\t\t}\n+\t\tretval = -DWC_E_INVALID;\n+\t\tval = 0;\n+\t}\n+\tcore_if->core_params->cont_on_bna = val;\n+\treturn retval;\n+}\n+\n+int32_t dwc_otg_get_param_cont_on_bna(dwc_otg_core_if_t * core_if)\n+{\n+\treturn core_if->core_params->cont_on_bna;\n+}\n+\n+int dwc_otg_set_param_ahb_single(dwc_otg_core_if_t * core_if, int32_t val)\n+{\n+\tint retval = 0;\n+\tint valid = 1;\n+\n+\tif (DWC_OTG_PARAM_TEST(val, 0, 1)) {\n+\t\tDWC_WARN(\"`%d' invalid for parameter `ahb_single'\\n\", val);\n+\t\tDWC_WARN(\"ahb_single must be 0 or 1\\n\");\n+\t\treturn -DWC_E_INVALID;\n+\t}\n+\n+\tif ((val == 1) && (core_if->snpsid < OTG_CORE_REV_2_94a)) {\n+\t\t\tvalid = 0;\n+\t}\n+\tif (valid == 0) {\n+\t\tif (dwc_otg_param_initialized(core_if->core_params->ahb_single)) {\n+\t\t\tDWC_ERROR(\"%d invalid for parameter ahb_single.\"\n+\t\t\t\t\"Check HW configuration.\\n\", val);\n+\t\t}\n+\t\tretval = -DWC_E_INVALID;\n+\t\tval = 0;\n+\t}\n+\tcore_if->core_params->ahb_single = val;\n+\treturn retval;\n+}\n+\n+int32_t dwc_otg_get_param_ahb_single(dwc_otg_core_if_t * core_if)\n+{\n+\treturn core_if->core_params->ahb_single;\n+}\n+\n+int dwc_otg_set_param_otg_ver(dwc_otg_core_if_t * core_if, int32_t val)\n+{\n+\tint retval = 0;\n+\n+\tif (DWC_OTG_PARAM_TEST(val, 0, 1)) {\n+\t\tDWC_WARN(\"`%d' invalid for parameter `otg_ver'\\n\", val);\n+\t\tDWC_WARN\n+\t\t    (\"otg_ver must be 0(for OTG 1.3 support) or 1(for OTG 2.0 support)\\n\");\n+\t\treturn -DWC_E_INVALID;\n+\t}\n+\n+\tcore_if->core_params->otg_ver = val;\n+\treturn retval;\n+}\n+\n+int32_t dwc_otg_get_param_otg_ver(dwc_otg_core_if_t * core_if)\n+{\n+\treturn core_if->core_params->otg_ver;\n+}\n+\n+uint32_t dwc_otg_get_hnpstatus(dwc_otg_core_if_t * core_if)\n+{\n+\tgotgctl_data_t otgctl;\n+\totgctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->gotgctl);\n+\treturn otgctl.b.hstnegscs;\n+}\n+\n+uint32_t dwc_otg_get_srpstatus(dwc_otg_core_if_t * core_if)\n+{\n+\tgotgctl_data_t otgctl;\n+\totgctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->gotgctl);\n+\treturn otgctl.b.sesreqscs;\n+}\n+\n+void dwc_otg_set_hnpreq(dwc_otg_core_if_t * core_if, uint32_t val)\n+{\n+\tif(core_if->otg_ver == 0) {\n+\t\tgotgctl_data_t otgctl;\n+\t\totgctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->gotgctl);\n+\t\totgctl.b.hnpreq = val;\n+\t\tDWC_WRITE_REG32(&core_if->core_global_regs->gotgctl, otgctl.d32);\n+\t} else {\n+\t\tcore_if->otg_sts = val;\n+\t}\n+}\n+\n+uint32_t dwc_otg_get_gsnpsid(dwc_otg_core_if_t * core_if)\n+{\n+\treturn core_if->snpsid;\n+}\n+\n+uint32_t dwc_otg_get_mode(dwc_otg_core_if_t * core_if)\n+{\n+\tgintsts_data_t gintsts;\n+\tgintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts);\n+\treturn gintsts.b.curmode;\n+}\n+\n+uint32_t dwc_otg_get_hnpcapable(dwc_otg_core_if_t * core_if)\n+{\n+\tgusbcfg_data_t usbcfg;\n+\tusbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);\n+\treturn usbcfg.b.hnpcap;\n+}\n+\n+void dwc_otg_set_hnpcapable(dwc_otg_core_if_t * core_if, uint32_t val)\n+{\n+\tgusbcfg_data_t usbcfg;\n+\tusbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);\n+\tusbcfg.b.hnpcap = val;\n+\tDWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, usbcfg.d32);\n+}\n+\n+uint32_t dwc_otg_get_srpcapable(dwc_otg_core_if_t * core_if)\n+{\n+\tgusbcfg_data_t usbcfg;\n+\tusbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);\n+\treturn usbcfg.b.srpcap;\n+}\n+\n+void dwc_otg_set_srpcapable(dwc_otg_core_if_t * core_if, uint32_t val)\n+{\n+\tgusbcfg_data_t usbcfg;\n+\tusbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);\n+\tusbcfg.b.srpcap = val;\n+\tDWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, usbcfg.d32);\n+}\n+\n+uint32_t dwc_otg_get_devspeed(dwc_otg_core_if_t * core_if)\n+{\n+\tdcfg_data_t dcfg;\n+\t/* originally: dcfg.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg); */\n+\n+        dcfg.d32 = -1; //GRAYG\n+        DWC_DEBUGPL(DBG_CILV, \"%s - core_if(%p)\\n\", __func__, core_if);\n+        if (NULL == core_if)\n+                DWC_ERROR(\"reg request with NULL core_if\\n\");\n+        DWC_DEBUGPL(DBG_CILV, \"%s - core_if(%p)->dev_if(%p)\\n\", __func__,\n+                    core_if, core_if->dev_if);\n+        if (NULL == core_if->dev_if)\n+                DWC_ERROR(\"reg request with NULL dev_if\\n\");\n+        DWC_DEBUGPL(DBG_CILV, \"%s - core_if(%p)->dev_if(%p)->\"\n+                    \"dev_global_regs(%p)\\n\", __func__,\n+                    core_if, core_if->dev_if,\n+                    core_if->dev_if->dev_global_regs);\n+        if (NULL == core_if->dev_if->dev_global_regs)\n+                DWC_ERROR(\"reg request with NULL dev_global_regs\\n\");\n+        else {\n+                DWC_DEBUGPL(DBG_CILV, \"%s - &core_if(%p)->dev_if(%p)->\"\n+                            \"dev_global_regs(%p)->dcfg = %p\\n\", __func__,\n+                            core_if, core_if->dev_if,\n+                            core_if->dev_if->dev_global_regs,\n+                            &core_if->dev_if->dev_global_regs->dcfg);\n+\t\tdcfg.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg);\n+        }\n+\treturn dcfg.b.devspd;\n+}\n+\n+void dwc_otg_set_devspeed(dwc_otg_core_if_t * core_if, uint32_t val)\n+{\n+\tdcfg_data_t dcfg;\n+\tdcfg.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg);\n+\tdcfg.b.devspd = val;\n+\tDWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg, dcfg.d32);\n+}\n+\n+uint32_t dwc_otg_get_busconnected(dwc_otg_core_if_t * core_if)\n+{\n+\thprt0_data_t hprt0;\n+\thprt0.d32 = DWC_READ_REG32(core_if->host_if->hprt0);\n+\treturn hprt0.b.prtconnsts;\n+}\n+\n+uint32_t dwc_otg_get_enumspeed(dwc_otg_core_if_t * core_if)\n+{\n+\tdsts_data_t dsts;\n+\tdsts.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);\n+\treturn dsts.b.enumspd;\n+}\n+\n+uint32_t dwc_otg_get_prtpower(dwc_otg_core_if_t * core_if)\n+{\n+\thprt0_data_t hprt0;\n+\thprt0.d32 = DWC_READ_REG32(core_if->host_if->hprt0);\n+\treturn hprt0.b.prtpwr;\n+\n+}\n+\n+uint32_t dwc_otg_get_core_state(dwc_otg_core_if_t * core_if)\n+{\n+\treturn core_if->hibernation_suspend;\n+}\n+\n+void dwc_otg_set_prtpower(dwc_otg_core_if_t * core_if, uint32_t val)\n+{\n+\thprt0_data_t hprt0;\n+\thprt0.d32 = dwc_otg_read_hprt0(core_if);\n+\thprt0.b.prtpwr = val;\n+\tDWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);\n+}\n+\n+uint32_t dwc_otg_get_prtsuspend(dwc_otg_core_if_t * core_if)\n+{\n+\thprt0_data_t hprt0;\n+\thprt0.d32 = DWC_READ_REG32(core_if->host_if->hprt0);\n+\treturn hprt0.b.prtsusp;\n+\n+}\n+\n+void dwc_otg_set_prtsuspend(dwc_otg_core_if_t * core_if, uint32_t val)\n+{\n+\thprt0_data_t hprt0;\n+\thprt0.d32 = dwc_otg_read_hprt0(core_if);\n+\thprt0.b.prtsusp = val;\n+\tDWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);\n+}\n+\n+uint32_t dwc_otg_get_fr_interval(dwc_otg_core_if_t * core_if)\n+{\n+\thfir_data_t hfir;\n+\thfir.d32 = DWC_READ_REG32(&core_if->host_if->host_global_regs->hfir);\n+\treturn hfir.b.frint;\n+\n+}\n+\n+void dwc_otg_set_fr_interval(dwc_otg_core_if_t * core_if, uint32_t val)\n+{\n+\thfir_data_t hfir;\n+\tuint32_t fram_int;\n+\tfram_int = calc_frame_interval(core_if);\n+\thfir.d32 = DWC_READ_REG32(&core_if->host_if->host_global_regs->hfir);\n+\tif (!core_if->core_params->reload_ctl) {\n+\t\tDWC_WARN(\"\\nCannot reload HFIR register.HFIR.HFIRRldCtrl bit is\"\n+\t\t\t \"not set to 1.\\nShould load driver with reload_ctl=1\"\n+\t\t\t \" module parameter\\n\");\n+\t\treturn;\n+\t}\n+\tswitch (fram_int) {\n+\tcase 3750:\n+\t\tif ((val < 3350) || (val > 4150)) {\n+\t\t\tDWC_WARN(\"HFIR interval for HS core and 30 MHz\"\n+\t\t\t\t \"clock freq should be from 3350 to 4150\\n\");\n+\t\t\treturn;\n+\t\t}\n+\t\tbreak;\n+\tcase 30000:\n+\t\tif ((val < 26820) || (val > 33180)) {\n+\t\t\tDWC_WARN(\"HFIR interval for FS/LS core and 30 MHz\"\n+\t\t\t\t \"clock freq should be from 26820 to 33180\\n\");\n+\t\t\treturn;\n+\t\t}\n+\t\tbreak;\n+\tcase 6000:\n+\t\tif ((val < 5360) || (val > 6640)) {\n+\t\t\tDWC_WARN(\"HFIR interval for HS core and 48 MHz\"\n+\t\t\t\t \"clock freq should be from 5360 to 6640\\n\");\n+\t\t\treturn;\n+\t\t}\n+\t\tbreak;\n+\tcase 48000:\n+\t\tif ((val < 42912) || (val > 53088)) {\n+\t\t\tDWC_WARN(\"HFIR interval for FS/LS core and 48 MHz\"\n+\t\t\t\t \"clock freq should be from 42912 to 53088\\n\");\n+\t\t\treturn;\n+\t\t}\n+\t\tbreak;\n+\tcase 7500:\n+\t\tif ((val < 6700) || (val > 8300)) {\n+\t\t\tDWC_WARN(\"HFIR interval for HS core and 60 MHz\"\n+\t\t\t\t \"clock freq should be from 6700 to 8300\\n\");\n+\t\t\treturn;\n+\t\t}\n+\t\tbreak;\n+\tcase 60000:\n+\t\tif ((val < 53640) || (val > 65536)) {\n+\t\t\tDWC_WARN(\"HFIR interval for FS/LS core and 60 MHz\"\n+\t\t\t\t \"clock freq should be from 53640 to 65536\\n\");\n+\t\t\treturn;\n+\t\t}\n+\t\tbreak;\n+\tdefault:\n+\t\tDWC_WARN(\"Unknown frame interval\\n\");\n+\t\treturn;\n+\t\tbreak;\n+\n+\t}\n+\thfir.b.frint = val;\n+\tDWC_WRITE_REG32(&core_if->host_if->host_global_regs->hfir, hfir.d32);\n+}\n+\n+uint32_t dwc_otg_get_mode_ch_tim(dwc_otg_core_if_t * core_if)\n+{\n+\thcfg_data_t hcfg;\n+\thcfg.d32 = DWC_READ_REG32(&core_if->host_if->host_global_regs->hcfg);\n+\treturn hcfg.b.modechtimen;\n+\n+}\n+\n+void dwc_otg_set_mode_ch_tim(dwc_otg_core_if_t * core_if, uint32_t val)\n+{\n+\thcfg_data_t hcfg;\n+\thcfg.d32 = DWC_READ_REG32(&core_if->host_if->host_global_regs->hcfg);\n+\thcfg.b.modechtimen = val;\n+\tDWC_WRITE_REG32(&core_if->host_if->host_global_regs->hcfg, hcfg.d32);\n+}\n+\n+void dwc_otg_set_prtresume(dwc_otg_core_if_t * core_if, uint32_t val)\n+{\n+\thprt0_data_t hprt0;\n+\thprt0.d32 = dwc_otg_read_hprt0(core_if);\n+\thprt0.b.prtres = val;\n+\tDWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);\n+}\n+\n+uint32_t dwc_otg_get_remotewakesig(dwc_otg_core_if_t * core_if)\n+{\n+\tdctl_data_t dctl;\n+\tdctl.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl);\n+\treturn dctl.b.rmtwkupsig;\n+}\n+\n+uint32_t dwc_otg_get_lpm_portsleepstatus(dwc_otg_core_if_t * core_if)\n+{\n+\tglpmcfg_data_t lpmcfg;\n+\tlpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);\n+\n+\tDWC_ASSERT(!\n+\t\t   ((core_if->lx_state == DWC_OTG_L1) ^ lpmcfg.b.prt_sleep_sts),\n+\t\t   \"lx_state = %d, lmpcfg.prt_sleep_sts = %d\\n\",\n+\t\t   core_if->lx_state, lpmcfg.b.prt_sleep_sts);\n+\n+\treturn lpmcfg.b.prt_sleep_sts;\n+}\n+\n+uint32_t dwc_otg_get_lpm_remotewakeenabled(dwc_otg_core_if_t * core_if)\n+{\n+\tglpmcfg_data_t lpmcfg;\n+\tlpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);\n+\treturn lpmcfg.b.rem_wkup_en;\n+}\n+\n+uint32_t dwc_otg_get_lpmresponse(dwc_otg_core_if_t * core_if)\n+{\n+\tglpmcfg_data_t lpmcfg;\n+\tlpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);\n+\treturn lpmcfg.b.appl_resp;\n+}\n+\n+void dwc_otg_set_lpmresponse(dwc_otg_core_if_t * core_if, uint32_t val)\n+{\n+\tglpmcfg_data_t lpmcfg;\n+\tlpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);\n+\tlpmcfg.b.appl_resp = val;\n+\tDWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg, lpmcfg.d32);\n+}\n+\n+uint32_t dwc_otg_get_hsic_connect(dwc_otg_core_if_t * core_if)\n+{\n+\tglpmcfg_data_t lpmcfg;\n+\tlpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);\n+\treturn lpmcfg.b.hsic_connect;\n+}\n+\n+void dwc_otg_set_hsic_connect(dwc_otg_core_if_t * core_if, uint32_t val)\n+{\n+\tglpmcfg_data_t lpmcfg;\n+\tlpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);\n+\tlpmcfg.b.hsic_connect = val;\n+\tDWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg, lpmcfg.d32);\n+}\n+\n+uint32_t dwc_otg_get_inv_sel_hsic(dwc_otg_core_if_t * core_if)\n+{\n+\tglpmcfg_data_t lpmcfg;\n+\tlpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);\n+\treturn lpmcfg.b.inv_sel_hsic;\n+\n+}\n+\n+void dwc_otg_set_inv_sel_hsic(dwc_otg_core_if_t * core_if, uint32_t val)\n+{\n+\tglpmcfg_data_t lpmcfg;\n+\tlpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);\n+\tlpmcfg.b.inv_sel_hsic = val;\n+\tDWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg, lpmcfg.d32);\n+}\n+\n+uint32_t dwc_otg_get_gotgctl(dwc_otg_core_if_t * core_if)\n+{\n+\treturn DWC_READ_REG32(&core_if->core_global_regs->gotgctl);\n+}\n+\n+void dwc_otg_set_gotgctl(dwc_otg_core_if_t * core_if, uint32_t val)\n+{\n+\tDWC_WRITE_REG32(&core_if->core_global_regs->gotgctl, val);\n+}\n+\n+uint32_t dwc_otg_get_gusbcfg(dwc_otg_core_if_t * core_if)\n+{\n+\treturn DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);\n+}\n+\n+void dwc_otg_set_gusbcfg(dwc_otg_core_if_t * core_if, uint32_t val)\n+{\n+\tDWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, val);\n+}\n+\n+uint32_t dwc_otg_get_grxfsiz(dwc_otg_core_if_t * core_if)\n+{\n+\treturn DWC_READ_REG32(&core_if->core_global_regs->grxfsiz);\n+}\n+\n+void dwc_otg_set_grxfsiz(dwc_otg_core_if_t * core_if, uint32_t val)\n+{\n+\tDWC_WRITE_REG32(&core_if->core_global_regs->grxfsiz, val);\n+}\n+\n+uint32_t dwc_otg_get_gnptxfsiz(dwc_otg_core_if_t * core_if)\n+{\n+\treturn DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz);\n+}\n+\n+void dwc_otg_set_gnptxfsiz(dwc_otg_core_if_t * core_if, uint32_t val)\n+{\n+\tDWC_WRITE_REG32(&core_if->core_global_regs->gnptxfsiz, val);\n+}\n+\n+uint32_t dwc_otg_get_gpvndctl(dwc_otg_core_if_t * core_if)\n+{\n+\treturn DWC_READ_REG32(&core_if->core_global_regs->gpvndctl);\n+}\n+\n+void dwc_otg_set_gpvndctl(dwc_otg_core_if_t * core_if, uint32_t val)\n+{\n+\tDWC_WRITE_REG32(&core_if->core_global_regs->gpvndctl, val);\n+}\n+\n+uint32_t dwc_otg_get_ggpio(dwc_otg_core_if_t * core_if)\n+{\n+\treturn DWC_READ_REG32(&core_if->core_global_regs->ggpio);\n+}\n+\n+void dwc_otg_set_ggpio(dwc_otg_core_if_t * core_if, uint32_t val)\n+{\n+\tDWC_WRITE_REG32(&core_if->core_global_regs->ggpio, val);\n+}\n+\n+uint32_t dwc_otg_get_hprt0(dwc_otg_core_if_t * core_if)\n+{\n+\treturn DWC_READ_REG32(core_if->host_if->hprt0);\n+\n+}\n+\n+void dwc_otg_set_hprt0(dwc_otg_core_if_t * core_if, uint32_t val)\n+{\n+\tDWC_WRITE_REG32(core_if->host_if->hprt0, val);\n+}\n+\n+uint32_t dwc_otg_get_guid(dwc_otg_core_if_t * core_if)\n+{\n+\treturn DWC_READ_REG32(&core_if->core_global_regs->guid);\n+}\n+\n+void dwc_otg_set_guid(dwc_otg_core_if_t * core_if, uint32_t val)\n+{\n+\tDWC_WRITE_REG32(&core_if->core_global_regs->guid, val);\n+}\n+\n+uint32_t dwc_otg_get_hptxfsiz(dwc_otg_core_if_t * core_if)\n+{\n+\treturn DWC_READ_REG32(&core_if->core_global_regs->hptxfsiz);\n+}\n+\n+uint16_t dwc_otg_get_otg_version(dwc_otg_core_if_t * core_if)\n+{\n+\treturn ((core_if->otg_ver == 1) ? (uint16_t)0x0200 : (uint16_t)0x0103);\n+}\n+\n+/**\n+ * Start the SRP timer to detect when the SRP does not complete within\n+ * 6 seconds.\n+ *\n+ * @param core_if the pointer to core_if strucure.\n+ */\n+void dwc_otg_pcd_start_srp_timer(dwc_otg_core_if_t * core_if)\n+{\n+\tcore_if->srp_timer_started = 1;\n+\tDWC_TIMER_SCHEDULE(core_if->srp_timer, 6000 /* 6 secs */ );\n+}\n+\n+void dwc_otg_initiate_srp(dwc_otg_core_if_t * core_if)\n+{\n+\tuint32_t *addr = (uint32_t *) & (core_if->core_global_regs->gotgctl);\n+\tgotgctl_data_t mem;\n+\tgotgctl_data_t val;\n+\n+\tval.d32 = DWC_READ_REG32(addr);\n+\tif (val.b.sesreq) {\n+\t\tDWC_ERROR(\"Session Request Already active!\\n\");\n+\t\treturn;\n+\t}\n+\n+\tDWC_INFO(\"Session Request Initated\\n\");\t//NOTICE\n+\tmem.d32 = DWC_READ_REG32(addr);\n+\tmem.b.sesreq = 1;\n+\tDWC_WRITE_REG32(addr, mem.d32);\n+\n+\t/* Start the SRP timer */\n+\tdwc_otg_pcd_start_srp_timer(core_if);\n+\treturn;\n+}\n--- /dev/null\n+++ b/drivers/usb/host/dwc_otg/dwc_otg_cil.h\n@@ -0,0 +1,1464 @@\n+/* ==========================================================================\n+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_cil.h $\n+ * $Revision: #123 $\n+ * $Date: 2012/08/10 $\n+ * $Change: 2047372 $\n+ *\n+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,\n+ * \"Software\") is an Unsupported proprietary work of Synopsys, Inc. unless\n+ * otherwise expressly agreed to in writing between Synopsys and you.\n+ *\n+ * The Software IS NOT an item of Licensed Software or Licensed Product under\n+ * any End User Software License Agreement or Agreement for Licensed Product\n+ * with Synopsys or any supplement thereto. You are permitted to use and\n+ * redistribute this Software in source and binary forms, with or without\n+ * modification, provided that redistributions of source code must retain this\n+ * notice. You may not view, use, disclose, copy or distribute this file or\n+ * any information contained herein except pursuant to this license grant from\n+ * Synopsys. If you do not agree with this notice, including the disclaimer\n+ * below, then you are not authorized to use the Software.\n+ *\n+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN \"AS IS\" BASIS\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,\n+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH\n+ * DAMAGE.\n+ * ========================================================================== */\n+\n+#if !defined(__DWC_CIL_H__)\n+#define __DWC_CIL_H__\n+\n+#include \"dwc_list.h\"\n+#include \"dwc_otg_dbg.h\"\n+#include \"dwc_otg_regs.h\"\n+\n+#include \"dwc_otg_core_if.h\"\n+#include \"dwc_otg_adp.h\"\n+\n+/**\n+ * @file\n+ * This file contains the interface to the Core Interface Layer.\n+ */\n+\n+#ifdef DWC_UTE_CFI\n+\n+#define MAX_DMA_DESCS_PER_EP\t256\n+\n+/**\n+ * Enumeration for the data buffer mode\n+ */\n+typedef enum _data_buffer_mode {\n+\tBM_STANDARD = 0,\t/* data buffer is in normal mode */\n+\tBM_SG = 1,\t\t/* data buffer uses the scatter/gather mode */\n+\tBM_CONCAT = 2,\t\t/* data buffer uses the concatenation mode */\n+\tBM_CIRCULAR = 3,\t/* data buffer uses the circular DMA mode */\n+\tBM_ALIGN = 4\t\t/* data buffer is in buffer alignment mode */\n+} data_buffer_mode_e;\n+#endif //DWC_UTE_CFI\n+\n+/** Macros defined for DWC OTG HW Release version */\n+\n+#define OTG_CORE_REV_2_60a\t0x4F54260A\n+#define OTG_CORE_REV_2_71a\t0x4F54271A\n+#define OTG_CORE_REV_2_72a\t0x4F54272A\n+#define OTG_CORE_REV_2_80a\t0x4F54280A\n+#define OTG_CORE_REV_2_81a\t0x4F54281A\n+#define OTG_CORE_REV_2_90a\t0x4F54290A\n+#define OTG_CORE_REV_2_91a\t0x4F54291A\n+#define OTG_CORE_REV_2_92a\t0x4F54292A\n+#define OTG_CORE_REV_2_93a\t0x4F54293A\n+#define OTG_CORE_REV_2_94a\t0x4F54294A\n+#define OTG_CORE_REV_3_00a\t0x4F54300A\n+\n+/**\n+ * Information for each ISOC packet.\n+ */\n+typedef struct iso_pkt_info {\n+\tuint32_t offset;\n+\tuint32_t length;\n+\tint32_t status;\n+} iso_pkt_info_t;\n+\n+/**\n+ * The <code>dwc_ep</code> structure represents the state of a single\n+ * endpoint when acting in device mode. It contains the data items\n+ * needed for an endpoint to be activated and transfer packets.\n+ */\n+typedef struct dwc_ep {\n+\t/** EP number used for register address lookup */\n+\tuint8_t num;\n+\t/** EP direction 0 = OUT */\n+\tunsigned is_in:1;\n+\t/** EP active. */\n+\tunsigned active:1;\n+\n+\t/**\n+\t * Periodic Tx FIFO # for IN EPs For INTR EP set to 0 to use non-periodic\n+\t * Tx FIFO. If dedicated Tx FIFOs are enabled Tx FIFO # FOR IN EPs*/\n+\tunsigned tx_fifo_num:4;\n+\t/** EP type: 0 - Control, 1 - ISOC,\t 2 - BULK,\t3 - INTR */\n+\tunsigned type:2;\n+#define DWC_OTG_EP_TYPE_CONTROL\t   0\n+#define DWC_OTG_EP_TYPE_ISOC\t   1\n+#define DWC_OTG_EP_TYPE_BULK\t   2\n+#define DWC_OTG_EP_TYPE_INTR\t   3\n+\n+\t/** DATA start PID for INTR and BULK EP */\n+\tunsigned data_pid_start:1;\n+\t/** Frame (even/odd) for ISOC EP */\n+\tunsigned even_odd_frame:1;\n+\t/** Max Packet bytes */\n+\tunsigned maxpacket:11;\n+\n+\t/** Max Transfer size */\n+\tuint32_t maxxfer;\n+\n+\t/** @name Transfer state */\n+\t/** @{ */\n+\n+\t/**\n+\t * Pointer to the beginning of the transfer buffer -- do not modify\n+\t * during transfer.\n+\t */\n+\n+\tdwc_dma_t dma_addr;\n+\n+\tdwc_dma_t dma_desc_addr;\n+\tdwc_otg_dev_dma_desc_t *desc_addr;\n+\n+\tuint8_t *start_xfer_buff;\n+\t/** pointer to the transfer buffer */\n+\tuint8_t *xfer_buff;\n+\t/** Number of bytes to transfer */\n+\tunsigned xfer_len:19;\n+\t/** Number of bytes transferred. */\n+\tunsigned xfer_count:19;\n+\t/** Sent ZLP */\n+\tunsigned sent_zlp:1;\n+\t/** Total len for control transfer */\n+\tunsigned total_len:19;\n+\n+\t/** stall clear flag */\n+\tunsigned stall_clear_flag:1;\n+\n+\t/** SETUP pkt cnt rollover flag for EP0 out*/\n+\tunsigned stp_rollover;\n+\n+#ifdef DWC_UTE_CFI\n+\t/* The buffer mode */\n+\tdata_buffer_mode_e buff_mode;\n+\n+\t/* The chain of DMA descriptors.\n+\t * MAX_DMA_DESCS_PER_EP will be allocated for each active EP.\n+\t */\n+\tdwc_otg_dma_desc_t *descs;\n+\n+\t/* The DMA address of the descriptors chain start */\n+\tdma_addr_t descs_dma_addr;\n+\t/** This variable stores the length of the last enqueued request */\n+\tuint32_t cfi_req_len;\n+#endif\t\t\t\t//DWC_UTE_CFI\n+\n+/** Max DMA Descriptor count for any EP */\n+#define MAX_DMA_DESC_CNT 256\n+\t/** Allocated DMA Desc count */\n+\tuint32_t desc_cnt;\n+\n+\t/** bInterval */\n+\tuint32_t bInterval;\n+\t/** Next frame num to setup next ISOC transfer */\n+\tuint32_t frame_num;\n+\t/** Indicates SOF number overrun in DSTS */\n+\tuint8_t frm_overrun;\n+\n+#ifdef DWC_UTE_PER_IO\n+\t/** Next frame num for which will be setup DMA Desc */\n+\tuint32_t xiso_frame_num;\n+\t/** bInterval */\n+\tuint32_t xiso_bInterval;\n+\t/** Count of currently active transfers - shall be either 0 or 1 */\n+\tint xiso_active_xfers;\n+\tint xiso_queued_xfers;\n+#endif\n+#ifdef DWC_EN_ISOC\n+\t/**\n+\t * Variables specific for ISOC EPs\n+\t *\n+\t */\n+\t/** DMA addresses of ISOC buffers */\n+\tdwc_dma_t dma_addr0;\n+\tdwc_dma_t dma_addr1;\n+\n+\tdwc_dma_t iso_dma_desc_addr;\n+\tdwc_otg_dev_dma_desc_t *iso_desc_addr;\n+\n+\t/** pointer to the transfer buffers */\n+\tuint8_t *xfer_buff0;\n+\tuint8_t *xfer_buff1;\n+\n+\t/** number of ISOC Buffer is processing */\n+\tuint32_t proc_buf_num;\n+\t/** Interval of ISOC Buffer processing */\n+\tuint32_t buf_proc_intrvl;\n+\t/** Data size for regular frame */\n+\tuint32_t data_per_frame;\n+\n+\t/* todo - pattern data support is to be implemented in the future */\n+\t/** Data size for pattern frame */\n+\tuint32_t data_pattern_frame;\n+\t/** Frame number of pattern data */\n+\tuint32_t sync_frame;\n+\n+\t/** bInterval */\n+\tuint32_t bInterval;\n+\t/** ISO Packet number per frame */\n+\tuint32_t pkt_per_frm;\n+\t/** Next frame num for which will be setup DMA Desc */\n+\tuint32_t next_frame;\n+\t/** Number of packets per buffer processing */\n+\tuint32_t pkt_cnt;\n+\t/** Info for all isoc packets */\n+\tiso_pkt_info_t *pkt_info;\n+\t/** current pkt number */\n+\tuint32_t cur_pkt;\n+\t/** current pkt number */\n+\tuint8_t *cur_pkt_addr;\n+\t/** current pkt number */\n+\tuint32_t cur_pkt_dma_addr;\n+#endif\t\t\t\t/* DWC_EN_ISOC */\n+\n+/** @} */\n+} dwc_ep_t;\n+\n+/*\n+ * Reasons for halting a host channel.\n+ */\n+typedef enum dwc_otg_halt_status {\n+\tDWC_OTG_HC_XFER_NO_HALT_STATUS,\n+\tDWC_OTG_HC_XFER_COMPLETE,\n+\tDWC_OTG_HC_XFER_URB_COMPLETE,\n+\tDWC_OTG_HC_XFER_ACK,\n+\tDWC_OTG_HC_XFER_NAK,\n+\tDWC_OTG_HC_XFER_NYET,\n+\tDWC_OTG_HC_XFER_STALL,\n+\tDWC_OTG_HC_XFER_XACT_ERR,\n+\tDWC_OTG_HC_XFER_FRAME_OVERRUN,\n+\tDWC_OTG_HC_XFER_BABBLE_ERR,\n+\tDWC_OTG_HC_XFER_DATA_TOGGLE_ERR,\n+\tDWC_OTG_HC_XFER_AHB_ERR,\n+\tDWC_OTG_HC_XFER_PERIODIC_INCOMPLETE,\n+\tDWC_OTG_HC_XFER_URB_DEQUEUE\n+} dwc_otg_halt_status_e;\n+\n+/**\n+ * Host channel descriptor. This structure represents the state of a single\n+ * host channel when acting in host mode. It contains the data items needed to\n+ * transfer packets to an endpoint via a host channel.\n+ */\n+typedef struct dwc_hc {\n+\t/** Host channel number used for register address lookup */\n+\tuint8_t hc_num;\n+\n+\t/** Device to access */\n+\tunsigned dev_addr:7;\n+\n+\t/** EP to access */\n+\tunsigned ep_num:4;\n+\n+\t/** EP direction. 0: OUT, 1: IN */\n+\tunsigned ep_is_in:1;\n+\n+\t/**\n+\t * EP speed.\n+\t * One of the following values:\n+\t *\t- DWC_OTG_EP_SPEED_LOW\n+\t *\t- DWC_OTG_EP_SPEED_FULL\n+\t *\t- DWC_OTG_EP_SPEED_HIGH\n+\t */\n+\tunsigned speed:2;\n+#define DWC_OTG_EP_SPEED_LOW\t0\n+#define DWC_OTG_EP_SPEED_FULL\t1\n+#define DWC_OTG_EP_SPEED_HIGH\t2\n+\n+\t/**\n+\t * Endpoint type.\n+\t * One of the following values:\n+\t *\t- DWC_OTG_EP_TYPE_CONTROL: 0\n+\t *\t- DWC_OTG_EP_TYPE_ISOC: 1\n+\t *\t- DWC_OTG_EP_TYPE_BULK: 2\n+\t *\t- DWC_OTG_EP_TYPE_INTR: 3\n+\t */\n+\tunsigned ep_type:2;\n+\n+\t/** Max packet size in bytes */\n+\tunsigned max_packet:11;\n+\n+\t/**\n+\t * PID for initial transaction.\n+\t * 0: DATA0,<br>\n+\t * 1: DATA2,<br>\n+\t * 2: DATA1,<br>\n+\t * 3: MDATA (non-Control EP),\n+\t *\t  SETUP (Control EP)\n+\t */\n+\tunsigned data_pid_start:2;\n+#define DWC_OTG_HC_PID_DATA0 0\n+#define DWC_OTG_HC_PID_DATA2 1\n+#define DWC_OTG_HC_PID_DATA1 2\n+#define DWC_OTG_HC_PID_MDATA 3\n+#define DWC_OTG_HC_PID_SETUP 3\n+\n+\t/** Number of periodic transactions per (micro)frame */\n+\tunsigned multi_count:2;\n+\n+\t/** @name Transfer State */\n+\t/** @{ */\n+\n+\t/** Pointer to the current transfer buffer position. */\n+\tuint8_t *xfer_buff;\n+\t/**\n+\t * In Buffer DMA mode this buffer will be used\n+\t * if xfer_buff is not DWORD aligned.\n+\t */\n+\tdwc_dma_t align_buff;\n+\t/** Total number of bytes to transfer. */\n+\tuint32_t xfer_len;\n+\t/** Number of bytes transferred so far. */\n+\tuint32_t xfer_count;\n+\t/** Packet count at start of transfer.*/\n+\tuint16_t start_pkt_count;\n+\n+\t/**\n+\t * Flag to indicate whether the transfer has been started. Set to 1 if\n+\t * it has been started, 0 otherwise.\n+\t */\n+\tuint8_t xfer_started;\n+\n+\t/**\n+\t * Set to 1 to indicate that a PING request should be issued on this\n+\t * channel. If 0, process normally.\n+\t */\n+\tuint8_t do_ping;\n+\n+\t/**\n+\t * Set to 1 to indicate that the error count for this transaction is\n+\t * non-zero. Set to 0 if the error count is 0.\n+\t */\n+\tuint8_t error_state;\n+\n+\t/**\n+\t * Set to 1 to indicate that this channel should be halted the next\n+\t * time a request is queued for the channel. This is necessary in\n+\t * slave mode if no request queue space is available when an attempt\n+\t * is made to halt the channel.\n+\t */\n+\tuint8_t halt_on_queue;\n+\n+\t/**\n+\t * Set to 1 if the host channel has been halted, but the core is not\n+\t * finished flushing queued requests. Otherwise 0.\n+\t */\n+\tuint8_t halt_pending;\n+\n+\t/**\n+\t * Reason for halting the host channel.\n+\t */\n+\tdwc_otg_halt_status_e halt_status;\n+\n+\t/*\n+\t * Split settings for the host channel\n+\t */\n+\tuint8_t do_split;\t\t   /**< Enable split for the channel */\n+\tuint8_t complete_split;\t   /**< Enable complete split */\n+\tuint8_t hub_addr;\t\t   /**< Address of high speed hub */\n+\n+\tuint8_t port_addr;\t\t   /**< Port of the low/full speed device */\n+\t/** Split transaction position\n+\t * One of the following values:\n+\t *\t  - DWC_HCSPLIT_XACTPOS_MID\n+\t *\t  - DWC_HCSPLIT_XACTPOS_BEGIN\n+\t *\t  - DWC_HCSPLIT_XACTPOS_END\n+\t *\t  - DWC_HCSPLIT_XACTPOS_ALL */\n+\tuint8_t xact_pos;\n+\n+\t/** Set when the host channel does a short read. */\n+\tuint8_t short_read;\n+\n+\t/**\n+\t * Number of requests issued for this channel since it was assigned to\n+\t * the current transfer (not counting PINGs).\n+\t */\n+\tuint8_t requests;\n+\n+\t/**\n+\t * Queue Head for the transfer being processed by this channel.\n+\t */\n+\tstruct dwc_otg_qh *qh;\n+\n+\t/** @} */\n+\n+\t/** Entry in list of host channels. */\n+\t DWC_CIRCLEQ_ENTRY(dwc_hc) hc_list_entry;\n+\n+\t/** @name Descriptor DMA support */\n+\t/** @{ */\n+\n+\t/** Number of Transfer Descriptors */\n+\tuint16_t ntd;\n+\n+\t/** Descriptor List DMA address */\n+\tdwc_dma_t desc_list_addr;\n+\n+\t/** Scheduling micro-frame bitmap. */\n+\tuint8_t schinfo;\n+\n+\t/** @} */\n+} dwc_hc_t;\n+\n+/**\n+ * The following parameters may be specified when starting the module. These\n+ * parameters define how the DWC_otg controller should be configured.\n+ */\n+typedef struct dwc_otg_core_params {\n+\tint32_t opt;\n+\n+\t/**\n+\t * Specifies the OTG capabilities. The driver will automatically\n+\t * detect the value for this parameter if none is specified.\n+\t * 0 - HNP and SRP capable (default)\n+\t * 1 - SRP Only capable\n+\t * 2 - No HNP/SRP capable\n+\t */\n+\tint32_t otg_cap;\n+\n+\t/**\n+\t * Specifies whether to use slave or DMA mode for accessing the data\n+\t * FIFOs. The driver will automatically detect the value for this\n+\t * parameter if none is specified.\n+\t * 0 - Slave\n+\t * 1 - DMA (default, if available)\n+\t */\n+\tint32_t dma_enable;\n+\n+\t/**\n+\t * When DMA mode is enabled specifies whether to use address DMA or DMA\n+\t * Descriptor mode for accessing the data FIFOs in device mode. The driver\n+\t * will automatically detect the value for this if none is specified.\n+\t * 0 - address DMA\n+\t * 1 - DMA Descriptor(default, if available)\n+\t */\n+\tint32_t dma_desc_enable;\n+\t/** The DMA Burst size (applicable only for External DMA\n+\t * Mode). 1, 4, 8 16, 32, 64, 128, 256 (default 32)\n+\t */\n+\tint32_t dma_burst_size;\t/* Translate this to GAHBCFG values */\n+\n+\t/**\n+\t * Specifies the maximum speed of operation in host and device mode.\n+\t * The actual speed depends on the speed of the attached device and\n+\t * the value of phy_type. The actual speed depends on the speed of the\n+\t * attached device.\n+\t * 0 - High Speed (default)\n+\t * 1 - Full Speed\n+\t */\n+\tint32_t speed;\n+\t/** Specifies whether low power mode is supported when attached\n+\t *\tto a Full Speed or Low Speed device in host mode.\n+\t * 0 - Don't support low power mode (default)\n+\t * 1 - Support low power mode\n+\t */\n+\tint32_t host_support_fs_ls_low_power;\n+\n+\t/** Specifies the PHY clock rate in low power mode when connected to a\n+\t * Low Speed device in host mode. This parameter is applicable only if\n+\t * HOST_SUPPORT_FS_LS_LOW_POWER is enabled. If PHY_TYPE is set to FS\n+\t * then defaults to 6 MHZ otherwise 48 MHZ.\n+\t *\n+\t * 0 - 48 MHz\n+\t * 1 - 6 MHz\n+\t */\n+\tint32_t host_ls_low_power_phy_clk;\n+\n+\t/**\n+\t * 0 - Use cC FIFO size parameters\n+\t * 1 - Allow dynamic FIFO sizing (default)\n+\t */\n+\tint32_t enable_dynamic_fifo;\n+\n+\t/** Total number of 4-byte words in the data FIFO memory. This\n+\t * memory includes the Rx FIFO, non-periodic Tx FIFO, and periodic\n+\t * Tx FIFOs.\n+\t * 32 to 32768 (default 8192)\n+\t * Note: The total FIFO memory depth in the FPGA configuration is 8192.\n+\t */\n+\tint32_t data_fifo_size;\n+\n+\t/** Number of 4-byte words in the Rx FIFO in device mode when dynamic\n+\t * FIFO sizing is enabled.\n+\t * 16 to 32768 (default 1064)\n+\t */\n+\tint32_t dev_rx_fifo_size;\n+\n+\t/** Number of 4-byte words in the non-periodic Tx FIFO in device mode\n+\t * when dynamic FIFO sizing is enabled.\n+\t * 16 to 32768 (default 1024)\n+\t */\n+\tint32_t dev_nperio_tx_fifo_size;\n+\n+\t/** Number of 4-byte words in each of the periodic Tx FIFOs in device\n+\t * mode when dynamic FIFO sizing is enabled.\n+\t * 4 to 768 (default 256)\n+\t */\n+\tuint32_t dev_perio_tx_fifo_size[MAX_PERIO_FIFOS];\n+\n+\t/** Number of 4-byte words in the Rx FIFO in host mode when dynamic\n+\t * FIFO sizing is enabled.\n+\t * 16 to 32768 (default 1024)\n+\t */\n+\tint32_t host_rx_fifo_size;\n+\n+\t/** Number of 4-byte words in the non-periodic Tx FIFO in host mode\n+\t * when Dynamic FIFO sizing is enabled in the core.\n+\t * 16 to 32768 (default 1024)\n+\t */\n+\tint32_t host_nperio_tx_fifo_size;\n+\n+\t/** Number of 4-byte words in the host periodic Tx FIFO when dynamic\n+\t * FIFO sizing is enabled.\n+\t * 16 to 32768 (default 1024)\n+\t */\n+\tint32_t host_perio_tx_fifo_size;\n+\n+\t/** The maximum transfer size supported in bytes.\n+\t * 2047 to 65,535  (default 65,535)\n+\t */\n+\tint32_t max_transfer_size;\n+\n+\t/** The maximum number of packets in a transfer.\n+\t * 15 to 511  (default 511)\n+\t */\n+\tint32_t max_packet_count;\n+\n+\t/** The number of host channel registers to use.\n+\t * 1 to 16 (default 12)\n+\t * Note: The FPGA configuration supports a maximum of 12 host channels.\n+\t */\n+\tint32_t host_channels;\n+\n+\t/** The number of endpoints in addition to EP0 available for device\n+\t * mode operations.\n+\t * 1 to 15 (default 6 IN and OUT)\n+\t * Note: The FPGA configuration supports a maximum of 6 IN and OUT\n+\t * endpoints in addition to EP0.\n+\t */\n+\tint32_t dev_endpoints;\n+\n+\t\t/**\n+\t\t * Specifies the type of PHY interface to use. By default, the driver\n+\t\t * will automatically detect the phy_type.\n+\t\t *\n+\t\t * 0 - Full Speed PHY\n+\t\t * 1 - UTMI+ (default)\n+\t\t * 2 - ULPI\n+\t\t */\n+\tint32_t phy_type;\n+\n+\t/**\n+\t * Specifies the UTMI+ Data Width. This parameter is\n+\t * applicable for a PHY_TYPE of UTMI+ or ULPI. (For a ULPI\n+\t * PHY_TYPE, this parameter indicates the data width between\n+\t * the MAC and the ULPI Wrapper.) Also, this parameter is\n+\t * applicable only if the OTG_HSPHY_WIDTH cC parameter was set\n+\t * to \"8 and 16 bits\", meaning that the core has been\n+\t * configured to work at either data path width.\n+\t *\n+\t * 8 or 16 bits (default 16)\n+\t */\n+\tint32_t phy_utmi_width;\n+\n+\t/**\n+\t * Specifies whether the ULPI operates at double or single\n+\t * data rate. This parameter is only applicable if PHY_TYPE is\n+\t * ULPI.\n+\t *\n+\t * 0 - single data rate ULPI interface with 8 bit wide data\n+\t * bus (default)\n+\t * 1 - double data rate ULPI interface with 4 bit wide data\n+\t * bus\n+\t */\n+\tint32_t phy_ulpi_ddr;\n+\n+\t/**\n+\t * Specifies whether to use the internal or external supply to\n+\t * drive the vbus with a ULPI phy.\n+\t */\n+\tint32_t phy_ulpi_ext_vbus;\n+\n+\t/**\n+\t * Specifies whether to use the I2Cinterface for full speed PHY. This\n+\t * parameter is only applicable if PHY_TYPE is FS.\n+\t * 0 - No (default)\n+\t * 1 - Yes\n+\t */\n+\tint32_t i2c_enable;\n+\n+\tint32_t ulpi_fs_ls;\n+\n+\tint32_t ts_dline;\n+\n+\t/**\n+\t * Specifies whether dedicated transmit FIFOs are\n+\t * enabled for non periodic IN endpoints in device mode\n+\t * 0 - No\n+\t * 1 - Yes\n+\t */\n+\tint32_t en_multiple_tx_fifo;\n+\n+\t/** Number of 4-byte words in each of the Tx FIFOs in device\n+\t * mode when dynamic FIFO sizing is enabled.\n+\t * 4 to 768 (default 256)\n+\t */\n+\tuint32_t dev_tx_fifo_size[MAX_TX_FIFOS];\n+\n+\t/** Thresholding enable flag-\n+\t * bit 0 - enable non-ISO Tx thresholding\n+\t * bit 1 - enable ISO Tx thresholding\n+\t * bit 2 - enable Rx thresholding\n+\t */\n+\tuint32_t thr_ctl;\n+\n+\t/** Thresholding length for Tx\n+\t *\tFIFOs in 32 bit DWORDs\n+\t */\n+\tuint32_t tx_thr_length;\n+\n+\t/** Thresholding length for Rx\n+\t *\tFIFOs in 32 bit DWORDs\n+\t */\n+\tuint32_t rx_thr_length;\n+\n+\t/**\n+\t * Specifies whether LPM (Link Power Management) support is enabled\n+\t */\n+\tint32_t lpm_enable;\n+\n+\t/** Per Transfer Interrupt\n+\t *\tmode enable flag\n+\t * 1 - Enabled\n+\t * 0 - Disabled\n+\t */\n+\tint32_t pti_enable;\n+\n+\t/** Multi Processor Interrupt\n+\t *\tmode enable flag\n+\t * 1 - Enabled\n+\t * 0 - Disabled\n+\t */\n+\tint32_t mpi_enable;\n+\n+\t/** IS_USB Capability\n+\t * 1 - Enabled\n+\t * 0 - Disabled\n+\t */\n+\tint32_t ic_usb_cap;\n+\n+\t/** AHB Threshold Ratio\n+\t * 2'b00 AHB Threshold = \tMAC Threshold\n+\t * 2'b01 AHB Threshold = 1/2 \tMAC Threshold\n+\t * 2'b10 AHB Threshold = 1/4\tMAC Threshold\n+\t * 2'b11 AHB Threshold = 1/8\tMAC Threshold\n+\t */\n+\tint32_t ahb_thr_ratio;\n+\n+\t/** ADP Support\n+\t * 1 - Enabled\n+\t * 0 - Disabled\n+\t */\n+\tint32_t adp_supp_enable;\n+\n+\t/** HFIR Reload Control\n+\t * 0 - The HFIR cannot be reloaded dynamically.\n+\t * 1 - Allow dynamic reloading of the HFIR register during runtime.\n+\t */\n+\tint32_t reload_ctl;\n+\n+\t/** DCFG: Enable device Out NAK\n+\t * 0 - The core does not set NAK after Bulk Out transfer complete.\n+\t * 1 - The core sets NAK after Bulk OUT transfer complete.\n+\t */\n+\tint32_t dev_out_nak;\n+\n+\t/** DCFG: Enable Continue on BNA\n+\t * After receiving BNA interrupt the core disables the endpoint,when the\n+\t * endpoint is re-enabled by the application the core starts processing\n+\t * 0 - from the DOEPDMA descriptor\n+\t * 1 - from the descriptor which received the BNA.\n+\t */\n+\tint32_t cont_on_bna;\n+\n+\t/** GAHBCFG: AHB Single Support\n+\t * This bit when programmed supports SINGLE transfers for remainder\n+\t * data in a transfer for DMA mode of operation.\n+\t * 0 - in this case the remainder data will be sent using INCR burst size.\n+\t * 1 - in this case the remainder data will be sent using SINGLE burst size.\n+\t */\n+\tint32_t ahb_single;\n+\n+\t/** Core Power down mode\n+\t * 0 - No Power Down is enabled\n+\t * 1 - Reserved\n+\t * 2 - Complete Power Down (Hibernation)\n+\t */\n+\tint32_t power_down;\n+\n+\t/** OTG revision supported\n+\t * 0 - OTG 1.3 revision\n+\t * 1 - OTG 2.0 revision\n+\t */\n+\tint32_t otg_ver;\n+\n+} dwc_otg_core_params_t;\n+\n+#ifdef DEBUG\n+struct dwc_otg_core_if;\n+typedef struct hc_xfer_info {\n+\tstruct dwc_otg_core_if *core_if;\n+\tdwc_hc_t *hc;\n+} hc_xfer_info_t;\n+#endif\n+\n+typedef struct ep_xfer_info {\n+\tstruct dwc_otg_core_if *core_if;\n+\tdwc_ep_t *ep;\n+\tuint8_t state;\n+} ep_xfer_info_t;\n+/*\n+ * Device States\n+ */\n+typedef enum dwc_otg_lx_state {\n+\t/** On state */\n+\tDWC_OTG_L0,\n+\t/** LPM sleep state*/\n+\tDWC_OTG_L1,\n+\t/** USB suspend state*/\n+\tDWC_OTG_L2,\n+\t/** Off state*/\n+\tDWC_OTG_L3\n+} dwc_otg_lx_state_e;\n+\n+struct dwc_otg_global_regs_backup {\n+\tuint32_t gotgctl_local;\n+\tuint32_t gintmsk_local;\n+\tuint32_t gahbcfg_local;\n+\tuint32_t gusbcfg_local;\n+\tuint32_t grxfsiz_local;\n+\tuint32_t gnptxfsiz_local;\n+#ifdef CONFIG_USB_DWC_OTG_LPM\n+\tuint32_t glpmcfg_local;\n+#endif\n+\tuint32_t gi2cctl_local;\n+\tuint32_t hptxfsiz_local;\n+\tuint32_t pcgcctl_local;\n+\tuint32_t gdfifocfg_local;\n+\tuint32_t dtxfsiz_local[MAX_EPS_CHANNELS];\n+\tuint32_t gpwrdn_local;\n+\tuint32_t xhib_pcgcctl;\n+\tuint32_t xhib_gpwrdn;\n+};\n+\n+struct dwc_otg_host_regs_backup {\n+\tuint32_t hcfg_local;\n+\tuint32_t haintmsk_local;\n+\tuint32_t hcintmsk_local[MAX_EPS_CHANNELS];\n+\tuint32_t hprt0_local;\n+\tuint32_t hfir_local;\n+};\n+\n+struct dwc_otg_dev_regs_backup {\n+\tuint32_t dcfg;\n+\tuint32_t dctl;\n+\tuint32_t daintmsk;\n+\tuint32_t diepmsk;\n+\tuint32_t doepmsk;\n+\tuint32_t diepctl[MAX_EPS_CHANNELS];\n+\tuint32_t dieptsiz[MAX_EPS_CHANNELS];\n+\tuint32_t diepdma[MAX_EPS_CHANNELS];\n+};\n+/**\n+ * The <code>dwc_otg_core_if</code> structure contains information needed to manage\n+ * the DWC_otg controller acting in either host or device mode. It\n+ * represents the programming view of the controller as a whole.\n+ */\n+struct dwc_otg_core_if {\n+\t/** Parameters that define how the core should be configured.*/\n+\tdwc_otg_core_params_t *core_params;\n+\n+\t/** Core Global registers starting at offset 000h. */\n+\tdwc_otg_core_global_regs_t *core_global_regs;\n+\n+\t/** Device-specific information */\n+\tdwc_otg_dev_if_t *dev_if;\n+\t/** Host-specific information */\n+\tdwc_otg_host_if_t *host_if;\n+\n+\t/** Value from SNPSID register */\n+\tuint32_t snpsid;\n+\n+\t/*\n+\t * Set to 1 if the core PHY interface bits in USBCFG have been\n+\t * initialized.\n+\t */\n+\tuint8_t phy_init_done;\n+\n+\t/*\n+\t * SRP Success flag, set by srp success interrupt in FS I2C mode\n+\t */\n+\tuint8_t srp_success;\n+\tuint8_t srp_timer_started;\n+\t/** Timer for SRP. If it expires before SRP is successful\n+\t * clear the SRP. */\n+\tdwc_timer_t *srp_timer;\n+\n+#ifdef DWC_DEV_SRPCAP\n+\t/* This timer is needed to power on the hibernated host core if SRP is not\n+\t * initiated on connected SRP capable device for limited period of time\n+\t */\n+\tuint8_t pwron_timer_started;\n+\tdwc_timer_t *pwron_timer;\n+#endif\n+\t/* Common configuration information */\n+\t/** Power and Clock Gating Control Register */\n+\tvolatile uint32_t *pcgcctl;\n+#define DWC_OTG_PCGCCTL_OFFSET 0xE00\n+\n+\t/** Push/pop addresses for endpoints or host channels.*/\n+\tuint32_t *data_fifo[MAX_EPS_CHANNELS];\n+#define DWC_OTG_DATA_FIFO_OFFSET 0x1000\n+#define DWC_OTG_DATA_FIFO_SIZE 0x1000\n+\n+\t/** Total RAM for FIFOs (Bytes) */\n+\tuint16_t total_fifo_size;\n+\t/** Size of Rx FIFO (Bytes) */\n+\tuint16_t rx_fifo_size;\n+\t/** Size of Non-periodic Tx FIFO (Bytes) */\n+\tuint16_t nperio_tx_fifo_size;\n+\n+\t/** 1 if DMA is enabled, 0 otherwise. */\n+\tuint8_t dma_enable;\n+\n+\t/** 1 if DMA descriptor is enabled, 0 otherwise. */\n+\tuint8_t dma_desc_enable;\n+\n+\t/** 1 if PTI Enhancement mode is enabled, 0 otherwise. */\n+\tuint8_t pti_enh_enable;\n+\n+\t/** 1 if MPI Enhancement mode is enabled, 0 otherwise. */\n+\tuint8_t multiproc_int_enable;\n+\n+\t/** 1 if dedicated Tx FIFOs are enabled, 0 otherwise. */\n+\tuint8_t en_multiple_tx_fifo;\n+\n+\t/** Set to 1 if multiple packets of a high-bandwidth transfer is in\n+\t * process of being queued */\n+\tuint8_t queuing_high_bandwidth;\n+\n+\t/** Hardware Configuration -- stored here for convenience.*/\n+\thwcfg1_data_t hwcfg1;\n+\thwcfg2_data_t hwcfg2;\n+\thwcfg3_data_t hwcfg3;\n+\thwcfg4_data_t hwcfg4;\n+\tfifosize_data_t hptxfsiz;\n+\n+\t/** Host and Device Configuration -- stored here for convenience.*/\n+\thcfg_data_t hcfg;\n+\tdcfg_data_t dcfg;\n+\n+\t/** The operational State, during transations\n+\t * (a_host>>a_peripherial and b_device=>b_host) this may not\n+\t * match the core but allows the software to determine\n+\t * transitions.\n+\t */\n+\tuint8_t op_state;\n+\n+\t/**\n+\t * Set to 1 if the HCD needs to be restarted on a session request\n+\t * interrupt. This is required if no connector ID status change has\n+\t * occurred since the HCD was last disconnected.\n+\t */\n+\tuint8_t restart_hcd_on_session_req;\n+\n+\t/** HCD callbacks */\n+\t/** A-Device is a_host */\n+#define A_HOST\t\t(1)\n+\t/** A-Device is a_suspend */\n+#define A_SUSPEND\t(2)\n+\t/** A-Device is a_peripherial */\n+#define A_PERIPHERAL\t(3)\n+\t/** B-Device is operating as a Peripheral. */\n+#define B_PERIPHERAL\t(4)\n+\t/** B-Device is operating as a Host. */\n+#define B_HOST\t\t(5)\n+\n+\t/** HCD callbacks */\n+\tstruct dwc_otg_cil_callbacks *hcd_cb;\n+\t/** PCD callbacks */\n+\tstruct dwc_otg_cil_callbacks *pcd_cb;\n+\n+\t/** Device mode Periodic Tx FIFO Mask */\n+\tuint32_t p_tx_msk;\n+\t/** Device mode Periodic Tx FIFO Mask */\n+\tuint32_t tx_msk;\n+\n+\t/** Workqueue object used for handling several interrupts */\n+\tdwc_workq_t *wq_otg;\n+\n+\t/** Timer object used for handling \"Wakeup Detected\" Interrupt */\n+\tdwc_timer_t *wkp_timer;\n+\t/** This arrays used for debug purposes for DEV OUT NAK enhancement */\n+\tuint32_t start_doeptsiz_val[MAX_EPS_CHANNELS];\n+\tep_xfer_info_t ep_xfer_info[MAX_EPS_CHANNELS];\n+\tdwc_timer_t *ep_xfer_timer[MAX_EPS_CHANNELS];\n+#ifdef DEBUG\n+\tuint32_t start_hcchar_val[MAX_EPS_CHANNELS];\n+\n+\thc_xfer_info_t hc_xfer_info[MAX_EPS_CHANNELS];\n+\tdwc_timer_t *hc_xfer_timer[MAX_EPS_CHANNELS];\n+\n+\tuint32_t hfnum_7_samples;\n+\tuint64_t hfnum_7_frrem_accum;\n+\tuint32_t hfnum_0_samples;\n+\tuint64_t hfnum_0_frrem_accum;\n+\tuint32_t hfnum_other_samples;\n+\tuint64_t hfnum_other_frrem_accum;\n+#endif\n+\n+#ifdef DWC_UTE_CFI\n+\tuint16_t pwron_rxfsiz;\n+\tuint16_t pwron_gnptxfsiz;\n+\tuint16_t pwron_txfsiz[15];\n+\n+\tuint16_t init_rxfsiz;\n+\tuint16_t init_gnptxfsiz;\n+\tuint16_t init_txfsiz[15];\n+#endif\n+\n+\t/** Lx state of device */\n+\tdwc_otg_lx_state_e lx_state;\n+\n+\t/** Saved Core Global registers */\n+\tstruct dwc_otg_global_regs_backup *gr_backup;\n+\t/** Saved Host registers */\n+\tstruct dwc_otg_host_regs_backup *hr_backup;\n+\t/** Saved Device registers */\n+\tstruct dwc_otg_dev_regs_backup *dr_backup;\n+\n+\t/** Power Down Enable */\n+\tuint32_t power_down;\n+\n+\t/** ADP support Enable */\n+\tuint32_t adp_enable;\n+\n+\t/** ADP structure object */\n+\tdwc_otg_adp_t adp;\n+\n+\t/** hibernation/suspend flag */\n+\tint hibernation_suspend;\n+\n+\t/** Device mode extended hibernation flag */\n+\tint xhib;\n+\n+\t/** OTG revision supported */\n+\tuint32_t otg_ver;\n+\n+\t/** OTG status flag used for HNP polling */\n+\tuint8_t otg_sts;\n+\n+\t/** Pointer to either hcd->lock or pcd->lock */\n+\tdwc_spinlock_t *lock;\n+\n+\t/** Start predict NextEP based on Learning Queue if equal 1,\n+\t * also used as counter of disabled NP IN EP's */\n+\tuint8_t start_predict;\n+\n+\t/** NextEp sequence, including EP0: nextep_seq[] = EP if non-periodic and\n+\t * active, 0xff otherwise */\n+\tuint8_t nextep_seq[MAX_EPS_CHANNELS];\n+\n+\t/** Index of fisrt EP in nextep_seq array which should be re-enabled **/\n+\tuint8_t first_in_nextep_seq;\n+\n+\t/** Frame number while entering to ISR - needed for ISOCs **/\n+\tuint32_t frame_num;\n+\n+};\n+\n+#ifdef DEBUG\n+/*\n+ * This function is called when transfer is timed out.\n+ */\n+extern void hc_xfer_timeout(void *ptr);\n+#endif\n+\n+/*\n+ * This function is called when transfer is timed out on endpoint.\n+ */\n+extern void ep_xfer_timeout(void *ptr);\n+\n+/*\n+ * The following functions are functions for works\n+ * using during handling some interrupts\n+ */\n+extern void w_conn_id_status_change(void *p);\n+\n+extern void w_wakeup_detected(void *p);\n+\n+/** Saves global register values into system memory. */\n+extern int dwc_otg_save_global_regs(dwc_otg_core_if_t * core_if);\n+/** Saves device register values into system memory. */\n+extern int dwc_otg_save_dev_regs(dwc_otg_core_if_t * core_if);\n+/** Saves host register values into system memory. */\n+extern int dwc_otg_save_host_regs(dwc_otg_core_if_t * core_if);\n+/** Restore global register values. */\n+extern int dwc_otg_restore_global_regs(dwc_otg_core_if_t * core_if);\n+/** Restore host register values. */\n+extern int dwc_otg_restore_host_regs(dwc_otg_core_if_t * core_if, int reset);\n+/** Restore device register values. */\n+extern int dwc_otg_restore_dev_regs(dwc_otg_core_if_t * core_if,\n+\t\t\t\t    int rem_wakeup);\n+extern int restore_lpm_i2c_regs(dwc_otg_core_if_t * core_if);\n+extern int restore_essential_regs(dwc_otg_core_if_t * core_if, int rmode,\n+\t\t\t\t  int is_host);\n+\n+extern int dwc_otg_host_hibernation_restore(dwc_otg_core_if_t * core_if,\n+\t\t\t\t\t    int restore_mode, int reset);\n+extern int dwc_otg_device_hibernation_restore(dwc_otg_core_if_t * core_if,\n+\t\t\t\t\t      int rem_wakeup, int reset);\n+\n+/*\n+ * The following functions support initialization of the CIL driver component\n+ * and the DWC_otg controller.\n+ */\n+extern void dwc_otg_core_host_init(dwc_otg_core_if_t * _core_if);\n+extern void dwc_otg_core_dev_init(dwc_otg_core_if_t * _core_if);\n+\n+/** @name Device CIL Functions\n+ * The following functions support managing the DWC_otg controller in device\n+ * mode.\n+ */\n+/**@{*/\n+extern void dwc_otg_wakeup(dwc_otg_core_if_t * _core_if);\n+extern void dwc_otg_read_setup_packet(dwc_otg_core_if_t * _core_if,\n+\t\t\t\t      uint32_t * _dest);\n+extern uint32_t dwc_otg_get_frame_number(dwc_otg_core_if_t * _core_if);\n+extern void dwc_otg_ep0_activate(dwc_otg_core_if_t * _core_if, dwc_ep_t * _ep);\n+extern void dwc_otg_ep_activate(dwc_otg_core_if_t * _core_if, dwc_ep_t * _ep);\n+extern void dwc_otg_ep_deactivate(dwc_otg_core_if_t * _core_if, dwc_ep_t * _ep);\n+extern void dwc_otg_ep_start_transfer(dwc_otg_core_if_t * _core_if,\n+\t\t\t\t      dwc_ep_t * _ep);\n+extern void dwc_otg_ep_start_zl_transfer(dwc_otg_core_if_t * _core_if,\n+\t\t\t\t\t dwc_ep_t * _ep);\n+extern void dwc_otg_ep0_start_transfer(dwc_otg_core_if_t * _core_if,\n+\t\t\t\t       dwc_ep_t * _ep);\n+extern void dwc_otg_ep0_continue_transfer(dwc_otg_core_if_t * _core_if,\n+\t\t\t\t\t  dwc_ep_t * _ep);\n+extern void dwc_otg_ep_write_packet(dwc_otg_core_if_t * _core_if,\n+\t\t\t\t    dwc_ep_t * _ep, int _dma);\n+extern void dwc_otg_ep_set_stall(dwc_otg_core_if_t * _core_if, dwc_ep_t * _ep);\n+extern void dwc_otg_ep_clear_stall(dwc_otg_core_if_t * _core_if,\n+\t\t\t\t   dwc_ep_t * _ep);\n+extern void dwc_otg_enable_device_interrupts(dwc_otg_core_if_t * _core_if);\n+\n+#ifdef DWC_EN_ISOC\n+extern void dwc_otg_iso_ep_start_frm_transfer(dwc_otg_core_if_t * core_if,\n+\t\t\t\t\t      dwc_ep_t * ep);\n+extern void dwc_otg_iso_ep_start_buf_transfer(dwc_otg_core_if_t * core_if,\n+\t\t\t\t\t      dwc_ep_t * ep);\n+#endif /* DWC_EN_ISOC */\n+/**@}*/\n+\n+/** @name Host CIL Functions\n+ * The following functions support managing the DWC_otg controller in host\n+ * mode.\n+ */\n+/**@{*/\n+extern void dwc_otg_hc_init(dwc_otg_core_if_t * _core_if, dwc_hc_t * _hc);\n+extern void dwc_otg_hc_halt(dwc_otg_core_if_t * _core_if,\n+\t\t\t    dwc_hc_t * _hc, dwc_otg_halt_status_e _halt_status);\n+extern void dwc_otg_hc_cleanup(dwc_otg_core_if_t * _core_if, dwc_hc_t * _hc);\n+extern void dwc_otg_hc_start_transfer(dwc_otg_core_if_t * _core_if,\n+\t\t\t\t      dwc_hc_t * _hc);\n+extern int dwc_otg_hc_continue_transfer(dwc_otg_core_if_t * _core_if,\n+\t\t\t\t\tdwc_hc_t * _hc);\n+extern void dwc_otg_hc_do_ping(dwc_otg_core_if_t * _core_if, dwc_hc_t * _hc);\n+extern void dwc_otg_hc_write_packet(dwc_otg_core_if_t * _core_if,\n+\t\t\t\t    dwc_hc_t * _hc);\n+extern void dwc_otg_enable_host_interrupts(dwc_otg_core_if_t * _core_if);\n+extern void dwc_otg_disable_host_interrupts(dwc_otg_core_if_t * _core_if);\n+\n+extern void dwc_otg_hc_start_transfer_ddma(dwc_otg_core_if_t * core_if,\n+\t\t\t\t\t   dwc_hc_t * hc);\n+\n+extern uint32_t calc_frame_interval(dwc_otg_core_if_t * core_if);\n+\n+/* Macro used to clear one channel interrupt */\n+#define clear_hc_int(_hc_regs_, _intr_) \\\n+do { \\\n+\thcint_data_t hcint_clear = {.d32 = 0}; \\\n+\thcint_clear.b._intr_ = 1; \\\n+\tDWC_WRITE_REG32(&(_hc_regs_)->hcint, hcint_clear.d32); \\\n+} while (0)\n+\n+/*\n+ * Macro used to disable one channel interrupt. Channel interrupts are\n+ * disabled when the channel is halted or released by the interrupt handler.\n+ * There is no need to handle further interrupts of that type until the\n+ * channel is re-assigned. In fact, subsequent handling may cause crashes\n+ * because the channel structures are cleaned up when the channel is released.\n+ */\n+#define disable_hc_int(_hc_regs_, _intr_) \\\n+do { \\\n+\thcintmsk_data_t hcintmsk = {.d32 = 0}; \\\n+\thcintmsk.b._intr_ = 1; \\\n+\tDWC_MODIFY_REG32(&(_hc_regs_)->hcintmsk, hcintmsk.d32, 0); \\\n+} while (0)\n+\n+/**\n+ * This function Reads HPRT0 in preparation to modify. It keeps the\n+ * WC bits 0 so that if they are read as 1, they won't clear when you\n+ * write it back\n+ */\n+static inline uint32_t dwc_otg_read_hprt0(dwc_otg_core_if_t * _core_if)\n+{\n+\thprt0_data_t hprt0;\n+\thprt0.d32 = DWC_READ_REG32(_core_if->host_if->hprt0);\n+\thprt0.b.prtena = 0;\n+\thprt0.b.prtconndet = 0;\n+\thprt0.b.prtenchng = 0;\n+\thprt0.b.prtovrcurrchng = 0;\n+\treturn hprt0.d32;\n+}\n+\n+/**@}*/\n+\n+/** @name Common CIL Functions\n+ * The following functions support managing the DWC_otg controller in either\n+ * device or host mode.\n+ */\n+/**@{*/\n+\n+extern void dwc_otg_read_packet(dwc_otg_core_if_t * core_if,\n+\t\t\t\tuint8_t * dest, uint16_t bytes);\n+\n+extern void dwc_otg_flush_tx_fifo(dwc_otg_core_if_t * _core_if, const int _num);\n+extern void dwc_otg_flush_rx_fifo(dwc_otg_core_if_t * _core_if);\n+extern void dwc_otg_core_reset(dwc_otg_core_if_t * _core_if);\n+\n+/**\n+ * This function returns the Core Interrupt register.\n+ */\n+static inline uint32_t dwc_otg_read_core_intr(dwc_otg_core_if_t * core_if)\n+{\n+\treturn (DWC_READ_REG32(&core_if->core_global_regs->gintsts) &\n+\t\tDWC_READ_REG32(&core_if->core_global_regs->gintmsk));\n+}\n+\n+/**\n+ * This function returns the OTG Interrupt register.\n+ */\n+static inline uint32_t dwc_otg_read_otg_intr(dwc_otg_core_if_t * core_if)\n+{\n+\treturn (DWC_READ_REG32(&core_if->core_global_regs->gotgint));\n+}\n+\n+/**\n+ * This function reads the Device All Endpoints Interrupt register and\n+ * returns the IN endpoint interrupt bits.\n+ */\n+static inline uint32_t dwc_otg_read_dev_all_in_ep_intr(dwc_otg_core_if_t *\n+\t\t\t\t\t\t       core_if)\n+{\n+\n+\tuint32_t v;\n+\n+\tif (core_if->multiproc_int_enable) {\n+\t\tv = DWC_READ_REG32(&core_if->dev_if->\n+\t\t\t\t   dev_global_regs->deachint) &\n+\t\t    DWC_READ_REG32(&core_if->\n+\t\t\t\t   dev_if->dev_global_regs->deachintmsk);\n+\t} else {\n+\t\tv = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->daint) &\n+\t\t    DWC_READ_REG32(&core_if->dev_if->dev_global_regs->daintmsk);\n+\t}\n+\treturn (v & 0xffff);\n+}\n+\n+/**\n+ * This function reads the Device All Endpoints Interrupt register and\n+ * returns the OUT endpoint interrupt bits.\n+ */\n+static inline uint32_t dwc_otg_read_dev_all_out_ep_intr(dwc_otg_core_if_t *\n+\t\t\t\t\t\t\tcore_if)\n+{\n+\tuint32_t v;\n+\n+\tif (core_if->multiproc_int_enable) {\n+\t\tv = DWC_READ_REG32(&core_if->dev_if->\n+\t\t\t\t   dev_global_regs->deachint) &\n+\t\t    DWC_READ_REG32(&core_if->\n+\t\t\t\t   dev_if->dev_global_regs->deachintmsk);\n+\t} else {\n+\t\tv = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->daint) &\n+\t\t    DWC_READ_REG32(&core_if->dev_if->dev_global_regs->daintmsk);\n+\t}\n+\n+\treturn ((v & 0xffff0000) >> 16);\n+}\n+\n+/**\n+ * This function returns the Device IN EP Interrupt register\n+ */\n+static inline uint32_t dwc_otg_read_dev_in_ep_intr(dwc_otg_core_if_t * core_if,\n+\t\t\t\t\t\t   dwc_ep_t * ep)\n+{\n+\tdwc_otg_dev_if_t *dev_if = core_if->dev_if;\n+\tuint32_t v, msk, emp;\n+\n+\tif (core_if->multiproc_int_enable) {\n+\t\tmsk =\n+\t\t    DWC_READ_REG32(&dev_if->\n+\t\t\t\t   dev_global_regs->diepeachintmsk[ep->num]);\n+\t\temp =\n+\t\t    DWC_READ_REG32(&dev_if->\n+\t\t\t\t   dev_global_regs->dtknqr4_fifoemptymsk);\n+\t\tmsk |= ((emp >> ep->num) & 0x1) << 7;\n+\t\tv = DWC_READ_REG32(&dev_if->in_ep_regs[ep->num]->diepint) & msk;\n+\t} else {\n+\t\tmsk = DWC_READ_REG32(&dev_if->dev_global_regs->diepmsk);\n+\t\temp =\n+\t\t    DWC_READ_REG32(&dev_if->\n+\t\t\t\t   dev_global_regs->dtknqr4_fifoemptymsk);\n+\t\tmsk |= ((emp >> ep->num) & 0x1) << 7;\n+\t\tv = DWC_READ_REG32(&dev_if->in_ep_regs[ep->num]->diepint) & msk;\n+\t}\n+\n+\treturn v;\n+}\n+\n+/**\n+ * This function returns the Device OUT EP Interrupt register\n+ */\n+static inline uint32_t dwc_otg_read_dev_out_ep_intr(dwc_otg_core_if_t *\n+\t\t\t\t\t\t    _core_if, dwc_ep_t * _ep)\n+{\n+\tdwc_otg_dev_if_t *dev_if = _core_if->dev_if;\n+\tuint32_t v;\n+\tdoepmsk_data_t msk = {.d32 = 0 };\n+\n+\tif (_core_if->multiproc_int_enable) {\n+\t\tmsk.d32 =\n+\t\t    DWC_READ_REG32(&dev_if->\n+\t\t\t\t   dev_global_regs->doepeachintmsk[_ep->num]);\n+\t\tif (_core_if->pti_enh_enable) {\n+\t\t\tmsk.b.pktdrpsts = 1;\n+\t\t}\n+\t\tv = DWC_READ_REG32(&dev_if->\n+\t\t\t\t   out_ep_regs[_ep->num]->doepint) & msk.d32;\n+\t} else {\n+\t\tmsk.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->doepmsk);\n+\t\tif (_core_if->pti_enh_enable) {\n+\t\t\tmsk.b.pktdrpsts = 1;\n+\t\t}\n+\t\tv = DWC_READ_REG32(&dev_if->\n+\t\t\t\t   out_ep_regs[_ep->num]->doepint) & msk.d32;\n+\t}\n+\treturn v;\n+}\n+\n+/**\n+ * This function returns the Host All Channel Interrupt register\n+ */\n+static inline uint32_t dwc_otg_read_host_all_channels_intr(dwc_otg_core_if_t *\n+\t\t\t\t\t\t\t   _core_if)\n+{\n+\treturn (DWC_READ_REG32(&_core_if->host_if->host_global_regs->haint));\n+}\n+\n+static inline uint32_t dwc_otg_read_host_channel_intr(dwc_otg_core_if_t *\n+\t\t\t\t\t\t      _core_if, dwc_hc_t * _hc)\n+{\n+\treturn (DWC_READ_REG32\n+\t\t(&_core_if->host_if->hc_regs[_hc->hc_num]->hcint));\n+}\n+\n+/**\n+ * This function returns the mode of the operation, host or device.\n+ *\n+ * @return 0 - Device Mode, 1 - Host Mode\n+ */\n+static inline uint32_t dwc_otg_mode(dwc_otg_core_if_t * _core_if)\n+{\n+\treturn (DWC_READ_REG32(&_core_if->core_global_regs->gintsts) & 0x1);\n+}\n+\n+/**@}*/\n+\n+/**\n+ * DWC_otg CIL callback structure. This structure allows the HCD and\n+ * PCD to register functions used for starting and stopping the PCD\n+ * and HCD for role change on for a DRD.\n+ */\n+typedef struct dwc_otg_cil_callbacks {\n+\t/** Start function for role change */\n+\tint (*start) (void *_p);\n+\t/** Stop Function for role change */\n+\tint (*stop) (void *_p);\n+\t/** Disconnect Function for role change */\n+\tint (*disconnect) (void *_p);\n+\t/** Resume/Remote wakeup Function */\n+\tint (*resume_wakeup) (void *_p);\n+\t/** Suspend function */\n+\tint (*suspend) (void *_p);\n+\t/** Session Start (SRP) */\n+\tint (*session_start) (void *_p);\n+#ifdef CONFIG_USB_DWC_OTG_LPM\n+\t/** Sleep (switch to L0 state) */\n+\tint (*sleep) (void *_p);\n+#endif\n+\t/** Pointer passed to start() and stop() */\n+\tvoid *p;\n+} dwc_otg_cil_callbacks_t;\n+\n+extern void dwc_otg_cil_register_pcd_callbacks(dwc_otg_core_if_t * _core_if,\n+\t\t\t\t\t       dwc_otg_cil_callbacks_t * _cb,\n+\t\t\t\t\t       void *_p);\n+extern void dwc_otg_cil_register_hcd_callbacks(dwc_otg_core_if_t * _core_if,\n+\t\t\t\t\t       dwc_otg_cil_callbacks_t * _cb,\n+\t\t\t\t\t       void *_p);\n+\n+void dwc_otg_initiate_srp(dwc_otg_core_if_t * core_if);\n+\n+//////////////////////////////////////////////////////////////////////\n+/** Start the HCD.  Helper function for using the HCD callbacks.\n+ *\n+ * @param core_if Programming view of DWC_otg controller.\n+ */\n+static inline void cil_hcd_start(dwc_otg_core_if_t * core_if)\n+{\n+\tif (core_if->hcd_cb && core_if->hcd_cb->start) {\n+\t\tcore_if->hcd_cb->start(core_if->hcd_cb->p);\n+\t}\n+}\n+\n+/** Stop the HCD.  Helper function for using the HCD callbacks.\n+ *\n+ * @param core_if Programming view of DWC_otg controller.\n+ */\n+static inline void cil_hcd_stop(dwc_otg_core_if_t * core_if)\n+{\n+\tif (core_if->hcd_cb && core_if->hcd_cb->stop) {\n+\t\tcore_if->hcd_cb->stop(core_if->hcd_cb->p);\n+\t}\n+}\n+\n+/** Disconnect the HCD.  Helper function for using the HCD callbacks.\n+ *\n+ * @param core_if Programming view of DWC_otg controller.\n+ */\n+static inline void cil_hcd_disconnect(dwc_otg_core_if_t * core_if)\n+{\n+\tif (core_if->hcd_cb && core_if->hcd_cb->disconnect) {\n+\t\tcore_if->hcd_cb->disconnect(core_if->hcd_cb->p);\n+\t}\n+}\n+\n+/** Inform the HCD the a New Session has begun.  Helper function for\n+ * using the HCD callbacks.\n+ *\n+ * @param core_if Programming view of DWC_otg controller.\n+ */\n+static inline void cil_hcd_session_start(dwc_otg_core_if_t * core_if)\n+{\n+\tif (core_if->hcd_cb && core_if->hcd_cb->session_start) {\n+\t\tcore_if->hcd_cb->session_start(core_if->hcd_cb->p);\n+\t}\n+}\n+\n+#ifdef CONFIG_USB_DWC_OTG_LPM\n+/**\n+ * Inform the HCD about LPM sleep.\n+ * Helper function for using the HCD callbacks.\n+ *\n+ * @param core_if Programming view of DWC_otg controller.\n+ */\n+static inline void cil_hcd_sleep(dwc_otg_core_if_t * core_if)\n+{\n+\tif (core_if->hcd_cb && core_if->hcd_cb->sleep) {\n+\t\tcore_if->hcd_cb->sleep(core_if->hcd_cb->p);\n+\t}\n+}\n+#endif\n+\n+/** Resume the HCD.  Helper function for using the HCD callbacks.\n+ *\n+ * @param core_if Programming view of DWC_otg controller.\n+ */\n+static inline void cil_hcd_resume(dwc_otg_core_if_t * core_if)\n+{\n+\tif (core_if->hcd_cb && core_if->hcd_cb->resume_wakeup) {\n+\t\tcore_if->hcd_cb->resume_wakeup(core_if->hcd_cb->p);\n+\t}\n+}\n+\n+/** Start the PCD.  Helper function for using the PCD callbacks.\n+ *\n+ * @param core_if Programming view of DWC_otg controller.\n+ */\n+static inline void cil_pcd_start(dwc_otg_core_if_t * core_if)\n+{\n+\tif (core_if->pcd_cb && core_if->pcd_cb->start) {\n+\t\tcore_if->pcd_cb->start(core_if->pcd_cb->p);\n+\t}\n+}\n+\n+/** Stop the PCD.  Helper function for using the PCD callbacks.\n+ *\n+ * @param core_if Programming view of DWC_otg controller.\n+ */\n+static inline void cil_pcd_stop(dwc_otg_core_if_t * core_if)\n+{\n+\tif (core_if->pcd_cb && core_if->pcd_cb->stop) {\n+\t\tcore_if->pcd_cb->stop(core_if->pcd_cb->p);\n+\t}\n+}\n+\n+/** Suspend the PCD.  Helper function for using the PCD callbacks.\n+ *\n+ * @param core_if Programming view of DWC_otg controller.\n+ */\n+static inline void cil_pcd_suspend(dwc_otg_core_if_t * core_if)\n+{\n+\tif (core_if->pcd_cb && core_if->pcd_cb->suspend) {\n+\t\tcore_if->pcd_cb->suspend(core_if->pcd_cb->p);\n+\t}\n+}\n+\n+/** Resume the PCD.  Helper function for using the PCD callbacks.\n+ *\n+ * @param core_if Programming view of DWC_otg controller.\n+ */\n+static inline void cil_pcd_resume(dwc_otg_core_if_t * core_if)\n+{\n+\tif (core_if->pcd_cb && core_if->pcd_cb->resume_wakeup) {\n+\t\tcore_if->pcd_cb->resume_wakeup(core_if->pcd_cb->p);\n+\t}\n+}\n+\n+//////////////////////////////////////////////////////////////////////\n+\n+#endif\n--- /dev/null\n+++ b/drivers/usb/host/dwc_otg/dwc_otg_cil_intr.c\n@@ -0,0 +1,1601 @@\n+/* ==========================================================================\n+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_cil_intr.c $\n+ * $Revision: #32 $\n+ * $Date: 2012/08/10 $\n+ * $Change: 2047372 $\n+ *\n+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,\n+ * \"Software\") is an Unsupported proprietary work of Synopsys, Inc. unless\n+ * otherwise expressly agreed to in writing between Synopsys and you.\n+ *\n+ * The Software IS NOT an item of Licensed Software or Licensed Product under\n+ * any End User Software License Agreement or Agreement for Licensed Product\n+ * with Synopsys or any supplement thereto. You are permitted to use and\n+ * redistribute this Software in source and binary forms, with or without\n+ * modification, provided that redistributions of source code must retain this\n+ * notice. You may not view, use, disclose, copy or distribute this file or\n+ * any information contained herein except pursuant to this license grant from\n+ * Synopsys. If you do not agree with this notice, including the disclaimer\n+ * below, then you are not authorized to use the Software.\n+ *\n+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN \"AS IS\" BASIS\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,\n+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH\n+ * DAMAGE.\n+ * ========================================================================== */\n+\n+/** @file\n+ *\n+ * The Core Interface Layer provides basic services for accessing and\n+ * managing the DWC_otg hardware. These services are used by both the\n+ * Host Controller Driver and the Peripheral Controller Driver.\n+ *\n+ * This file contains the Common Interrupt handlers.\n+ */\n+#include \"dwc_os.h\"\n+#include \"dwc_otg_regs.h\"\n+#include \"dwc_otg_cil.h\"\n+#include \"dwc_otg_driver.h\"\n+#include \"dwc_otg_pcd.h\"\n+#include \"dwc_otg_hcd.h\"\n+\n+#ifdef DEBUG\n+inline const char *op_state_str(dwc_otg_core_if_t * core_if)\n+{\n+\treturn (core_if->op_state == A_HOST ? \"a_host\" :\n+\t\t(core_if->op_state == A_SUSPEND ? \"a_suspend\" :\n+\t\t (core_if->op_state == A_PERIPHERAL ? \"a_peripheral\" :\n+\t\t  (core_if->op_state == B_PERIPHERAL ? \"b_peripheral\" :\n+\t\t   (core_if->op_state == B_HOST ? \"b_host\" : \"unknown\")))));\n+}\n+#endif\n+\n+/** This function will log a debug message\n+ *\n+ * @param core_if Programming view of DWC_otg controller.\n+ */\n+int32_t dwc_otg_handle_mode_mismatch_intr(dwc_otg_core_if_t * core_if)\n+{\n+\tgintsts_data_t gintsts;\n+\tDWC_WARN(\"Mode Mismatch Interrupt: currently in %s mode\\n\",\n+\t\t dwc_otg_mode(core_if) ? \"Host\" : \"Device\");\n+\n+\t/* Clear interrupt */\n+\tgintsts.d32 = 0;\n+\tgintsts.b.modemismatch = 1;\n+\tDWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);\n+\treturn 1;\n+}\n+\n+/**\n+ * This function handles the OTG Interrupts. It reads the OTG\n+ * Interrupt Register (GOTGINT) to determine what interrupt has\n+ * occurred.\n+ *\n+ * @param core_if Programming view of DWC_otg controller.\n+ */\n+int32_t dwc_otg_handle_otg_intr(dwc_otg_core_if_t * core_if)\n+{\n+\tdwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;\n+\tgotgint_data_t gotgint;\n+\tgotgctl_data_t gotgctl;\n+\tgintmsk_data_t gintmsk;\n+\tgpwrdn_data_t gpwrdn;\n+\n+\tgotgint.d32 = DWC_READ_REG32(&global_regs->gotgint);\n+\tgotgctl.d32 = DWC_READ_REG32(&global_regs->gotgctl);\n+\tDWC_DEBUGPL(DBG_CIL, \"++OTG Interrupt gotgint=%0x [%s]\\n\", gotgint.d32,\n+\t\t    op_state_str(core_if));\n+\n+\tif (gotgint.b.sesenddet) {\n+\t\tDWC_DEBUGPL(DBG_ANY, \" ++OTG Interrupt: \"\n+\t\t\t    \"Session End Detected++ (%s)\\n\",\n+\t\t\t    op_state_str(core_if));\n+\t\tgotgctl.d32 = DWC_READ_REG32(&global_regs->gotgctl);\n+\n+\t\tif (core_if->op_state == B_HOST) {\n+\t\t\tcil_pcd_start(core_if);\n+\t\t\tcore_if->op_state = B_PERIPHERAL;\n+\t\t} else {\n+\t\t\t/* If not B_HOST and Device HNP still set. HNP\n+\t\t\t * Did not succeed!*/\n+\t\t\tif (gotgctl.b.devhnpen) {\n+\t\t\t\tDWC_DEBUGPL(DBG_ANY, \"Session End Detected\\n\");\n+\t\t\t\t__DWC_ERROR(\"Device Not Connected/Responding!\\n\");\n+\t\t\t}\n+\n+\t\t\t/* If Session End Detected the B-Cable has\n+\t\t\t * been disconnected. */\n+\t\t\t/* Reset PCD and Gadget driver to a\n+\t\t\t * clean state. */\n+\t\t\tcore_if->lx_state = DWC_OTG_L0;\n+\t\t\tDWC_SPINUNLOCK(core_if->lock);\n+\t\t\tcil_pcd_stop(core_if);\n+\t\t\tDWC_SPINLOCK(core_if->lock);\n+\n+\t\t\tif (core_if->adp_enable) {\n+\t\t\t\tif (core_if->power_down == 2) {\n+\t\t\t\t\tgpwrdn.d32 = 0;\n+\t\t\t\t\tgpwrdn.b.pwrdnswtch = 1;\n+\t\t\t\t\tDWC_MODIFY_REG32(&core_if->\n+\t\t\t\t\t\t\t core_global_regs->\n+\t\t\t\t\t\t\t gpwrdn, gpwrdn.d32, 0);\n+\t\t\t\t}\n+\n+\t\t\t\tgpwrdn.d32 = 0;\n+\t\t\t\tgpwrdn.b.pmuintsel = 1;\n+\t\t\t\tgpwrdn.b.pmuactv = 1;\n+\t\t\t\tDWC_MODIFY_REG32(&core_if->core_global_regs->\n+\t\t\t\t\t\t gpwrdn, 0, gpwrdn.d32);\n+\n+\t\t\t\tdwc_otg_adp_sense_start(core_if);\n+\t\t\t}\n+\t\t}\n+\n+\t\tgotgctl.d32 = 0;\n+\t\tgotgctl.b.devhnpen = 1;\n+\t\tDWC_MODIFY_REG32(&global_regs->gotgctl, gotgctl.d32, 0);\n+\t}\n+\tif (gotgint.b.sesreqsucstschng) {\n+\t\tDWC_DEBUGPL(DBG_ANY, \" ++OTG Interrupt: \"\n+\t\t\t    \"Session Reqeust Success Status Change++\\n\");\n+\t\tgotgctl.d32 = DWC_READ_REG32(&global_regs->gotgctl);\n+\t\tif (gotgctl.b.sesreqscs) {\n+\n+\t\t\tif ((core_if->core_params->phy_type ==\n+\t\t\t     DWC_PHY_TYPE_PARAM_FS) && (core_if->core_params->i2c_enable)) {\n+\t\t\t\tcore_if->srp_success = 1;\n+\t\t\t} else {\n+\t\t\t\tDWC_SPINUNLOCK(core_if->lock);\n+\t\t\t\tcil_pcd_resume(core_if);\n+\t\t\t\tDWC_SPINLOCK(core_if->lock);\n+\t\t\t\t/* Clear Session Request */\n+\t\t\t\tgotgctl.d32 = 0;\n+\t\t\t\tgotgctl.b.sesreq = 1;\n+\t\t\t\tDWC_MODIFY_REG32(&global_regs->gotgctl,\n+\t\t\t\t\t\t gotgctl.d32, 0);\n+\t\t\t}\n+\t\t}\n+\t}\n+\tif (gotgint.b.hstnegsucstschng) {\n+\t\t/* Print statements during the HNP interrupt handling\n+\t\t * can cause it to fail.*/\n+\t\tgotgctl.d32 = DWC_READ_REG32(&global_regs->gotgctl);\n+\t\t/* WA for 3.00a- HW is not setting cur_mode, even sometimes\n+\t\t * this does not help*/\n+\t\tif (core_if->snpsid >= OTG_CORE_REV_3_00a)\n+\t\t\tdwc_udelay(100);\n+\t\tif (gotgctl.b.hstnegscs) {\n+\t\t\tif (dwc_otg_is_host_mode(core_if)) {\n+\t\t\t\tcore_if->op_state = B_HOST;\n+\t\t\t\t/*\n+\t\t\t\t * Need to disable SOF interrupt immediately.\n+\t\t\t\t * When switching from device to host, the PCD\n+\t\t\t\t * interrupt handler won't handle the\n+\t\t\t\t * interrupt if host mode is already set. The\n+\t\t\t\t * HCD interrupt handler won't get called if\n+\t\t\t\t * the HCD state is HALT. This means that the\n+\t\t\t\t * interrupt does not get handled and Linux\n+\t\t\t\t * complains loudly.\n+\t\t\t\t */\n+\t\t\t\tgintmsk.d32 = 0;\n+\t\t\t\tgintmsk.b.sofintr = 1;\n+\t\t\t\tDWC_MODIFY_REG32(&global_regs->gintmsk,\n+\t\t\t\t\t\t gintmsk.d32, 0);\n+\t\t\t\t/* Call callback function with spin lock released */\n+\t\t\t\tDWC_SPINUNLOCK(core_if->lock);\n+\t\t\t\tcil_pcd_stop(core_if);\n+\t\t\t\t/*\n+\t\t\t\t * Initialize the Core for Host mode.\n+\t\t\t\t */\n+\t\t\t\tcil_hcd_start(core_if);\n+\t\t\t\tDWC_SPINLOCK(core_if->lock);\n+\t\t\t\tcore_if->op_state = B_HOST;\n+\t\t\t}\n+\t\t} else {\n+\t\t\tgotgctl.d32 = 0;\n+\t\t\tgotgctl.b.hnpreq = 1;\n+\t\t\tgotgctl.b.devhnpen = 1;\n+\t\t\tDWC_MODIFY_REG32(&global_regs->gotgctl, gotgctl.d32, 0);\n+\t\t\tDWC_DEBUGPL(DBG_ANY, \"HNP Failed\\n\");\n+\t\t\t__DWC_ERROR(\"Device Not Connected/Responding\\n\");\n+\t\t}\n+\t}\n+\tif (gotgint.b.hstnegdet) {\n+\t\t/* The disconnect interrupt is set at the same time as\n+\t\t * Host Negotiation Detected.  During the mode\n+\t\t * switch all interrupts are cleared so the disconnect\n+\t\t * interrupt handler will not get executed.\n+\t\t */\n+\t\tDWC_DEBUGPL(DBG_ANY, \" ++OTG Interrupt: \"\n+\t\t\t    \"Host Negotiation Detected++ (%s)\\n\",\n+\t\t\t    (dwc_otg_is_host_mode(core_if) ? \"Host\" :\n+\t\t\t     \"Device\"));\n+\t\tif (dwc_otg_is_device_mode(core_if)) {\n+\t\t\tDWC_DEBUGPL(DBG_ANY, \"a_suspend->a_peripheral (%d)\\n\",\n+\t\t\t\t    core_if->op_state);\n+\t\t\tDWC_SPINUNLOCK(core_if->lock);\n+\t\t\tcil_hcd_disconnect(core_if);\n+\t\t\tcil_pcd_start(core_if);\n+\t\t\tDWC_SPINLOCK(core_if->lock);\n+\t\t\tcore_if->op_state = A_PERIPHERAL;\n+\t\t} else {\n+\t\t\t/*\n+\t\t\t * Need to disable SOF interrupt immediately. When\n+\t\t\t * switching from device to host, the PCD interrupt\n+\t\t\t * handler won't handle the interrupt if host mode is\n+\t\t\t * already set. The HCD interrupt handler won't get\n+\t\t\t * called if the HCD state is HALT. This means that\n+\t\t\t * the interrupt does not get handled and Linux\n+\t\t\t * complains loudly.\n+\t\t\t */\n+\t\t\tgintmsk.d32 = 0;\n+\t\t\tgintmsk.b.sofintr = 1;\n+\t\t\tDWC_MODIFY_REG32(&global_regs->gintmsk, gintmsk.d32, 0);\n+\t\t\tDWC_SPINUNLOCK(core_if->lock);\n+\t\t\tcil_pcd_stop(core_if);\n+\t\t\tcil_hcd_start(core_if);\n+\t\t\tDWC_SPINLOCK(core_if->lock);\n+\t\t\tcore_if->op_state = A_HOST;\n+\t\t}\n+\t}\n+\tif (gotgint.b.adevtoutchng) {\n+\t\tDWC_DEBUGPL(DBG_ANY, \" ++OTG Interrupt: \"\n+\t\t\t    \"A-Device Timeout Change++\\n\");\n+\t}\n+\tif (gotgint.b.debdone) {\n+\t\tDWC_DEBUGPL(DBG_ANY, \" ++OTG Interrupt: \" \"Debounce Done++\\n\");\n+\t}\n+\n+\t/* Clear GOTGINT */\n+\tDWC_WRITE_REG32(&core_if->core_global_regs->gotgint, gotgint.d32);\n+\n+\treturn 1;\n+}\n+\n+void w_conn_id_status_change(void *p)\n+{\n+\tdwc_otg_core_if_t *core_if = p;\n+\tuint32_t count = 0;\n+\tgotgctl_data_t gotgctl = {.d32 = 0 };\n+\n+\tgotgctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->gotgctl);\n+\tDWC_DEBUGPL(DBG_CIL, \"gotgctl=%0x\\n\", gotgctl.d32);\n+\tDWC_DEBUGPL(DBG_CIL, \"gotgctl.b.conidsts=%d\\n\", gotgctl.b.conidsts);\n+\n+\t/* B-Device connector (Device Mode) */\n+\tif (gotgctl.b.conidsts) {\n+\t\t/* Wait for switch to device mode. */\n+\t\twhile (!dwc_otg_is_device_mode(core_if)) {\n+\t\t\tDWC_PRINTF(\"Waiting for Peripheral Mode, Mode=%s\\n\",\n+\t\t\t\t   (dwc_otg_is_host_mode(core_if) ? \"Host\" :\n+\t\t\t\t    \"Peripheral\"));\n+\t\t\tdwc_mdelay(100);\n+\t\t\tif (++count > 10000)\n+\t\t\t\tbreak;\n+\t\t}\n+\t\tDWC_ASSERT(++count < 10000,\n+\t\t\t   \"Connection id status change timed out\");\n+\t\tcore_if->op_state = B_PERIPHERAL;\n+\t\tdwc_otg_core_init(core_if);\n+\t\tdwc_otg_enable_global_interrupts(core_if);\n+\t\tcil_pcd_start(core_if);\n+\t} else {\n+\t\t/* A-Device connector (Host Mode) */\n+\t\twhile (!dwc_otg_is_host_mode(core_if)) {\n+\t\t\tDWC_PRINTF(\"Waiting for Host Mode, Mode=%s\\n\",\n+\t\t\t\t   (dwc_otg_is_host_mode(core_if) ? \"Host\" :\n+\t\t\t\t    \"Peripheral\"));\n+\t\t\tdwc_mdelay(100);\n+\t\t\tif (++count > 10000)\n+\t\t\t\tbreak;\n+\t\t}\n+\t\tDWC_ASSERT(++count < 10000,\n+\t\t\t   \"Connection id status change timed out\");\n+\t\tcore_if->op_state = A_HOST;\n+\t\t/*\n+\t\t * Initialize the Core for Host mode.\n+\t\t */\n+\t\tdwc_otg_core_init(core_if);\n+\t\tdwc_otg_enable_global_interrupts(core_if);\n+\t\tcil_hcd_start(core_if);\n+\t}\n+}\n+\n+/**\n+ * This function handles the Connector ID Status Change Interrupt.  It\n+ * reads the OTG Interrupt Register (GOTCTL) to determine whether this\n+ * is a Device to Host Mode transition or a Host Mode to Device\n+ * Transition.\n+ *\n+ * This only occurs when the cable is connected/removed from the PHY\n+ * connector.\n+ *\n+ * @param core_if Programming view of DWC_otg controller.\n+ */\n+int32_t dwc_otg_handle_conn_id_status_change_intr(dwc_otg_core_if_t * core_if)\n+{\n+\n+\t/*\n+\t * Need to disable SOF interrupt immediately. If switching from device\n+\t * to host, the PCD interrupt handler won't handle the interrupt if\n+\t * host mode is already set. The HCD interrupt handler won't get\n+\t * called if the HCD state is HALT. This means that the interrupt does\n+\t * not get handled and Linux complains loudly.\n+\t */\n+\tgintmsk_data_t gintmsk = {.d32 = 0 };\n+\tgintsts_data_t gintsts = {.d32 = 0 };\n+\n+\tgintmsk.b.sofintr = 1;\n+\tDWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, gintmsk.d32, 0);\n+\n+\tDWC_DEBUGPL(DBG_CIL,\n+\t\t    \" ++Connector ID Status Change Interrupt++  (%s)\\n\",\n+\t\t    (dwc_otg_is_host_mode(core_if) ? \"Host\" : \"Device\"));\n+\n+\tDWC_SPINUNLOCK(core_if->lock);\n+\n+\t/*\n+\t * Need to schedule a work, as there are possible DELAY function calls\n+\t * Release lock before scheduling workq as it holds spinlock during scheduling\n+\t */\n+\n+\tDWC_WORKQ_SCHEDULE(core_if->wq_otg, w_conn_id_status_change,\n+\t\t\t   core_if, \"connection id status change\");\n+\tDWC_SPINLOCK(core_if->lock);\n+\n+\t/* Set flag and clear interrupt */\n+\tgintsts.b.conidstschng = 1;\n+\tDWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);\n+\n+\treturn 1;\n+}\n+\n+/**\n+ * This interrupt indicates that a device is initiating the Session\n+ * Request Protocol to request the host to turn on bus power so a new\n+ * session can begin. The handler responds by turning on bus power. If\n+ * the DWC_otg controller is in low power mode, the handler brings the\n+ * controller out of low power mode before turning on bus power.\n+ *\n+ * @param core_if Programming view of DWC_otg controller.\n+ */\n+int32_t dwc_otg_handle_session_req_intr(dwc_otg_core_if_t * core_if)\n+{\n+\tgintsts_data_t gintsts;\n+\n+#ifndef DWC_HOST_ONLY\n+\tDWC_DEBUGPL(DBG_ANY, \"++Session Request Interrupt++\\n\");\n+\n+\tif (dwc_otg_is_device_mode(core_if)) {\n+\t\tDWC_PRINTF(\"SRP: Device mode\\n\");\n+\t} else {\n+\t\thprt0_data_t hprt0;\n+\t\tDWC_PRINTF(\"SRP: Host mode\\n\");\n+\n+\t\t/* Turn on the port power bit. */\n+\t\thprt0.d32 = dwc_otg_read_hprt0(core_if);\n+\t\thprt0.b.prtpwr = 1;\n+\t\tDWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);\n+\n+\t\t/* Start the Connection timer. So a message can be displayed\n+\t\t * if connect does not occur within 10 seconds. */\n+\t\tcil_hcd_session_start(core_if);\n+\t}\n+#endif\n+\n+\t/* Clear interrupt */\n+\tgintsts.d32 = 0;\n+\tgintsts.b.sessreqintr = 1;\n+\tDWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);\n+\n+\treturn 1;\n+}\n+\n+void w_wakeup_detected(void *p)\n+{\n+\tdwc_otg_core_if_t *core_if = (dwc_otg_core_if_t *) p;\n+\t/*\n+\t * Clear the Resume after 70ms. (Need 20 ms minimum. Use 70 ms\n+\t * so that OPT tests pass with all PHYs).\n+\t */\n+\thprt0_data_t hprt0 = {.d32 = 0 };\n+#if 0\n+\tpcgcctl_data_t pcgcctl = {.d32 = 0 };\n+\t/* Restart the Phy Clock */\n+\tpcgcctl.b.stoppclk = 1;\n+\tDWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0);\n+\tdwc_udelay(10);\n+#endif //0\n+\thprt0.d32 = dwc_otg_read_hprt0(core_if);\n+\tDWC_DEBUGPL(DBG_ANY, \"Resume: HPRT0=%0x\\n\", hprt0.d32);\n+//      dwc_mdelay(70);\n+\thprt0.b.prtres = 0;\t/* Resume */\n+\tDWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);\n+\tDWC_DEBUGPL(DBG_ANY, \"Clear Resume: HPRT0=%0x\\n\",\n+\t\t    DWC_READ_REG32(core_if->host_if->hprt0));\n+\n+\tcil_hcd_resume(core_if);\n+\n+\t/** Change to L0 state*/\n+\tcore_if->lx_state = DWC_OTG_L0;\n+}\n+\n+/**\n+ * This interrupt indicates that the DWC_otg controller has detected a\n+ * resume or remote wakeup sequence. If the DWC_otg controller is in\n+ * low power mode, the handler must brings the controller out of low\n+ * power mode. The controller automatically begins resume\n+ * signaling. The handler schedules a time to stop resume signaling.\n+ */\n+int32_t dwc_otg_handle_wakeup_detected_intr(dwc_otg_core_if_t * core_if)\n+{\n+\tgintsts_data_t gintsts;\n+\n+\tDWC_DEBUGPL(DBG_ANY,\n+\t\t    \"++Resume and Remote Wakeup Detected Interrupt++\\n\");\n+\n+\tDWC_PRINTF(\"%s lxstate = %d\\n\", __func__, core_if->lx_state);\n+\n+\tif (dwc_otg_is_device_mode(core_if)) {\n+\t\tdctl_data_t dctl = {.d32 = 0 };\n+\t\tDWC_DEBUGPL(DBG_PCD, \"DSTS=0x%0x\\n\",\n+\t\t\t    DWC_READ_REG32(&core_if->dev_if->dev_global_regs->\n+\t\t\t\t\t   dsts));\n+\t\tif (core_if->lx_state == DWC_OTG_L2) {\n+#ifdef PARTIAL_POWER_DOWN\n+\t\t\tif (core_if->hwcfg4.b.power_optimiz) {\n+\t\t\t\tpcgcctl_data_t power = {.d32 = 0 };\n+\n+\t\t\t\tpower.d32 = DWC_READ_REG32(core_if->pcgcctl);\n+\t\t\t\tDWC_DEBUGPL(DBG_CIL, \"PCGCCTL=%0x\\n\",\n+\t\t\t\t\t    power.d32);\n+\n+\t\t\t\tpower.b.stoppclk = 0;\n+\t\t\t\tDWC_WRITE_REG32(core_if->pcgcctl, power.d32);\n+\n+\t\t\t\tpower.b.pwrclmp = 0;\n+\t\t\t\tDWC_WRITE_REG32(core_if->pcgcctl, power.d32);\n+\n+\t\t\t\tpower.b.rstpdwnmodule = 0;\n+\t\t\t\tDWC_WRITE_REG32(core_if->pcgcctl, power.d32);\n+\t\t\t}\n+#endif\n+\t\t\t/* Clear the Remote Wakeup Signaling */\n+\t\t\tdctl.b.rmtwkupsig = 1;\n+\t\t\tDWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->\n+\t\t\t\t\t dctl, dctl.d32, 0);\n+\n+\t\t\tDWC_SPINUNLOCK(core_if->lock);\n+\t\t\tif (core_if->pcd_cb && core_if->pcd_cb->resume_wakeup) {\n+\t\t\t\tcore_if->pcd_cb->resume_wakeup(core_if->pcd_cb->p);\n+\t\t\t}\n+\t\t\tDWC_SPINLOCK(core_if->lock);\n+\t\t} else {\n+\t\t\tglpmcfg_data_t lpmcfg;\n+\t\t\tlpmcfg.d32 =\n+\t\t\t    DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);\n+\t\t\tlpmcfg.b.hird_thres &= (~(1 << 4));\n+\t\t\tDWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg,\n+\t\t\t\t\tlpmcfg.d32);\n+\t\t}\n+\t\t/** Change to L0 state*/\n+\t\tcore_if->lx_state = DWC_OTG_L0;\n+\t} else {\n+\t\tif (core_if->lx_state != DWC_OTG_L1) {\n+\t\t\tpcgcctl_data_t pcgcctl = {.d32 = 0 };\n+\n+\t\t\t/* Restart the Phy Clock */\n+\t\t\tpcgcctl.b.stoppclk = 1;\n+\t\t\tDWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0);\n+\t\t\tDWC_TIMER_SCHEDULE(core_if->wkp_timer, 71);\n+\t\t} else {\n+\t\t\t/** Change to L0 state*/\n+\t\t\tcore_if->lx_state = DWC_OTG_L0;\n+\t\t}\n+\t}\n+\n+\t/* Clear interrupt */\n+\tgintsts.d32 = 0;\n+\tgintsts.b.wkupintr = 1;\n+\tDWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);\n+\n+\treturn 1;\n+}\n+\n+/**\n+ * This interrupt indicates that the Wakeup Logic has detected a\n+ * Device disconnect.\n+ */\n+static int32_t dwc_otg_handle_pwrdn_disconnect_intr(dwc_otg_core_if_t *core_if)\n+{\n+\tgpwrdn_data_t gpwrdn = { .d32 = 0 };\n+\tgpwrdn_data_t gpwrdn_temp = { .d32 = 0 };\n+\tgpwrdn_temp.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);\n+\n+\tDWC_PRINTF(\"%s called\\n\", __FUNCTION__);\n+\n+\tif (!core_if->hibernation_suspend) {\n+\t\tDWC_PRINTF(\"Already exited from Hibernation\\n\");\n+\t\treturn 1;\n+\t}\n+\n+\t/* Switch on the voltage to the core */\n+\tgpwrdn.b.pwrdnswtch = 1;\n+\tDWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);\n+\tdwc_udelay(10);\n+\n+\t/* Reset the core */\n+\tgpwrdn.d32 = 0;\n+\tgpwrdn.b.pwrdnrstn = 1;\n+\tDWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);\n+\tdwc_udelay(10);\n+\n+\t/* Disable power clamps*/\n+\tgpwrdn.d32 = 0;\n+\tgpwrdn.b.pwrdnclmp = 1;\n+\tDWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);\n+\n+\t/* Remove reset the core signal */\n+\tgpwrdn.d32 = 0;\n+\tgpwrdn.b.pwrdnrstn = 1;\n+\tDWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);\n+\tdwc_udelay(10);\n+\n+\t/* Disable PMU interrupt */\n+\tgpwrdn.d32 = 0;\n+\tgpwrdn.b.pmuintsel = 1;\n+\tDWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);\n+\n+\tcore_if->hibernation_suspend = 0;\n+\n+\t/* Disable PMU */\n+\tgpwrdn.d32 = 0;\n+\tgpwrdn.b.pmuactv = 1;\n+\tDWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);\n+\tdwc_udelay(10);\n+\n+\tif (gpwrdn_temp.b.idsts) {\n+\t\tcore_if->op_state = B_PERIPHERAL;\n+\t\tdwc_otg_core_init(core_if);\n+\t\tdwc_otg_enable_global_interrupts(core_if);\n+\t\tcil_pcd_start(core_if);\n+\t} else {\n+\t\tcore_if->op_state = A_HOST;\n+\t\tdwc_otg_core_init(core_if);\n+\t\tdwc_otg_enable_global_interrupts(core_if);\n+\t\tcil_hcd_start(core_if);\n+\t}\n+\n+\treturn 1;\n+}\n+\n+/**\n+ * This interrupt indicates that the Wakeup Logic has detected a\n+ * remote wakeup sequence.\n+ */\n+static int32_t dwc_otg_handle_pwrdn_wakeup_detected_intr(dwc_otg_core_if_t * core_if)\n+{\n+\tgpwrdn_data_t gpwrdn = {.d32 = 0 };\n+\tDWC_DEBUGPL(DBG_ANY,\n+\t\t    \"++Powerdown Remote Wakeup Detected Interrupt++\\n\");\n+\n+\tif (!core_if->hibernation_suspend) {\n+\t\tDWC_PRINTF(\"Already exited from Hibernation\\n\");\n+\t\treturn 1;\n+\t}\n+\n+\tgpwrdn.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);\n+\tif (gpwrdn.b.idsts) {\t// Device Mode\n+\t\tif ((core_if->power_down == 2)\n+\t\t    && (core_if->hibernation_suspend == 1)) {\n+\t\t\tdwc_otg_device_hibernation_restore(core_if, 0, 0);\n+\t\t}\n+\t} else {\n+\t\tif ((core_if->power_down == 2)\n+\t\t    && (core_if->hibernation_suspend == 1)) {\n+\t\t\tdwc_otg_host_hibernation_restore(core_if, 1, 0);\n+\t\t}\n+\t}\n+\treturn 1;\n+}\n+\n+static int32_t dwc_otg_handle_pwrdn_idsts_change(dwc_otg_device_t *otg_dev)\n+{\n+\tgpwrdn_data_t gpwrdn = {.d32 = 0 };\n+\tgpwrdn_data_t gpwrdn_temp = {.d32 = 0 };\n+\tdwc_otg_core_if_t *core_if = otg_dev->core_if;\n+\n+\tDWC_DEBUGPL(DBG_ANY, \"%s called\\n\", __FUNCTION__);\n+\tgpwrdn_temp.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);\n+\tif (core_if->power_down == 2) {\n+\t\tif (!core_if->hibernation_suspend) {\n+\t\t\tDWC_PRINTF(\"Already exited from Hibernation\\n\");\n+\t\t\treturn 1;\n+\t\t}\n+\t\tDWC_DEBUGPL(DBG_ANY, \"Exit from hibernation on ID sts change\\n\");\n+\t\t/* Switch on the voltage to the core */\n+\t\tgpwrdn.b.pwrdnswtch = 1;\n+\t\tDWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);\n+\t\tdwc_udelay(10);\n+\n+\t\t/* Reset the core */\n+\t\tgpwrdn.d32 = 0;\n+\t\tgpwrdn.b.pwrdnrstn = 1;\n+\t\tDWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);\n+\t\tdwc_udelay(10);\n+\n+\t\t/* Disable power clamps */\n+\t\tgpwrdn.d32 = 0;\n+\t\tgpwrdn.b.pwrdnclmp = 1;\n+\t\tDWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);\n+\n+\t\t/* Remove reset the core signal */\n+\t\tgpwrdn.d32 = 0;\n+\t\tgpwrdn.b.pwrdnrstn = 1;\n+\t\tDWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);\n+\t\tdwc_udelay(10);\n+\n+\t\t/* Disable PMU interrupt */\n+\t\tgpwrdn.d32 = 0;\n+\t\tgpwrdn.b.pmuintsel = 1;\n+\t\tDWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);\n+\n+\t\t/*Indicates that we are exiting from hibernation */\n+\t\tcore_if->hibernation_suspend = 0;\n+\n+\t\t/* Disable PMU */\n+\t\tgpwrdn.d32 = 0;\n+\t\tgpwrdn.b.pmuactv = 1;\n+\t\tDWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);\n+\t\tdwc_udelay(10);\n+\n+\t\tgpwrdn.d32 = core_if->gr_backup->gpwrdn_local;\n+\t\tif (gpwrdn.b.dis_vbus == 1) {\n+\t\t\tgpwrdn.d32 = 0;\n+\t\t\tgpwrdn.b.dis_vbus = 1;\n+\t\t\tDWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);\n+\t\t}\n+\n+\t\tif (gpwrdn_temp.b.idsts) {\n+\t\t\tcore_if->op_state = B_PERIPHERAL;\n+\t\t\tdwc_otg_core_init(core_if);\n+\t\t\tdwc_otg_enable_global_interrupts(core_if);\n+\t\t\tcil_pcd_start(core_if);\n+\t\t} else {\n+\t\t\tcore_if->op_state = A_HOST;\n+\t\t\tdwc_otg_core_init(core_if);\n+\t\t\tdwc_otg_enable_global_interrupts(core_if);\n+\t\t\tcil_hcd_start(core_if);\n+\t\t}\n+\t}\n+\n+\tif (core_if->adp_enable) {\n+\t\tuint8_t is_host = 0;\n+\t\tDWC_SPINUNLOCK(core_if->lock);\n+\t\t/* Change the core_if's lock to hcd/pcd lock depend on mode? */\n+#ifndef DWC_HOST_ONLY\n+\t\tif (gpwrdn_temp.b.idsts)\n+\t\t\tcore_if->lock = otg_dev->pcd->lock;\n+#endif\n+#ifndef DWC_DEVICE_ONLY\n+\t\tif (!gpwrdn_temp.b.idsts) {\n+\t\t\t\tcore_if->lock = otg_dev->hcd->lock;\n+\t\t\t\tis_host = 1;\n+\t\t}\n+#endif\n+\t\tDWC_PRINTF(\"RESTART ADP\\n\");\n+\t\tif (core_if->adp.probe_enabled)\n+\t\t\tdwc_otg_adp_probe_stop(core_if);\n+\t\tif (core_if->adp.sense_enabled)\n+\t\t\tdwc_otg_adp_sense_stop(core_if);\n+\t\tif (core_if->adp.sense_timer_started)\n+\t\t\tDWC_TIMER_CANCEL(core_if->adp.sense_timer);\n+\t\tif (core_if->adp.vbuson_timer_started)\n+\t\t\tDWC_TIMER_CANCEL(core_if->adp.vbuson_timer);\n+\t\tcore_if->adp.probe_timer_values[0] = -1;\n+\t\tcore_if->adp.probe_timer_values[1] = -1;\n+\t\tcore_if->adp.sense_timer_started = 0;\n+\t\tcore_if->adp.vbuson_timer_started = 0;\n+\t\tcore_if->adp.probe_counter = 0;\n+\t\tcore_if->adp.gpwrdn = 0;\n+\n+\t\t/* Disable PMU and restart ADP */\n+\t\tgpwrdn_temp.d32 = 0;\n+\t\tgpwrdn_temp.b.pmuactv = 1;\n+\t\tgpwrdn_temp.b.pmuintsel = 1;\n+\t\tDWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);\n+\t\tDWC_PRINTF(\"Check point 1\\n\");\n+\t\tdwc_mdelay(110);\n+\t\tdwc_otg_adp_start(core_if, is_host);\n+\t\tDWC_SPINLOCK(core_if->lock);\n+\t}\n+\n+\n+\treturn 1;\n+}\n+\n+static int32_t dwc_otg_handle_pwrdn_session_change(dwc_otg_core_if_t * core_if)\n+{\n+\tgpwrdn_data_t gpwrdn = {.d32 = 0 };\n+\tint32_t otg_cap_param = core_if->core_params->otg_cap;\n+\tDWC_DEBUGPL(DBG_ANY, \"%s called\\n\", __FUNCTION__);\n+\n+\tgpwrdn.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);\n+\tif (core_if->power_down == 2) {\n+\t\tif (!core_if->hibernation_suspend) {\n+\t\t\tDWC_PRINTF(\"Already exited from Hibernation\\n\");\n+\t\t\treturn 1;\n+\t\t}\n+\n+\t\tif ((otg_cap_param != DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE ||\n+\t\t\t otg_cap_param != DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE) &&\n+\t\t\tgpwrdn.b.bsessvld == 0) {\n+\t\t\t/* Save gpwrdn register for further usage if stschng interrupt */\n+\t\t\tcore_if->gr_backup->gpwrdn_local =\n+\t\t\t\tDWC_READ_REG32(&core_if->core_global_regs->gpwrdn);\n+\t\t\t/*Exit from ISR and wait for stschng interrupt with bsessvld = 1 */\n+\t\t\treturn 1;\n+\t\t}\n+\n+\t\t/* Switch on the voltage to the core */\n+\t\tgpwrdn.d32 = 0;\n+\t\tgpwrdn.b.pwrdnswtch = 1;\n+\t\tDWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);\n+\t\tdwc_udelay(10);\n+\n+\t\t/* Reset the core */\n+\t\tgpwrdn.d32 = 0;\n+\t\tgpwrdn.b.pwrdnrstn = 1;\n+\t\tDWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);\n+\t\tdwc_udelay(10);\n+\n+\t\t/* Disable power clamps */\n+\t\tgpwrdn.d32 = 0;\n+\t\tgpwrdn.b.pwrdnclmp = 1;\n+\t\tDWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);\n+\n+\t\t/* Remove reset the core signal */\n+\t\tgpwrdn.d32 = 0;\n+\t\tgpwrdn.b.pwrdnrstn = 1;\n+\t\tDWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);\n+\t\tdwc_udelay(10);\n+\n+\t\t/* Disable PMU interrupt */\n+\t\tgpwrdn.d32 = 0;\n+\t\tgpwrdn.b.pmuintsel = 1;\n+\t\tDWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);\n+\t\tdwc_udelay(10);\n+\n+\t\t/*Indicates that we are exiting from hibernation */\n+\t\tcore_if->hibernation_suspend = 0;\n+\n+\t\t/* Disable PMU */\n+\t\tgpwrdn.d32 = 0;\n+\t\tgpwrdn.b.pmuactv = 1;\n+\t\tDWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);\n+\t\tdwc_udelay(10);\n+\n+\t\tcore_if->op_state = B_PERIPHERAL;\n+\t\tdwc_otg_core_init(core_if);\n+\t\tdwc_otg_enable_global_interrupts(core_if);\n+\t\tcil_pcd_start(core_if);\n+\n+\t\tif (otg_cap_param == DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE ||\n+\t\t\totg_cap_param == DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE) {\n+\t\t\t/*\n+\t\t\t * Initiate SRP after initial ADP probe.\n+\t\t\t */\n+\t\t\tdwc_otg_initiate_srp(core_if);\n+\t\t}\n+\t}\n+\n+\treturn 1;\n+}\n+/**\n+ * This interrupt indicates that the Wakeup Logic has detected a\n+ * status change either on IDDIG or BSessVld.\n+ */\n+static uint32_t dwc_otg_handle_pwrdn_stschng_intr(dwc_otg_device_t *otg_dev)\n+{\n+\tint retval;\n+\tgpwrdn_data_t gpwrdn = {.d32 = 0 };\n+\tgpwrdn_data_t gpwrdn_temp = {.d32 = 0 };\n+\tdwc_otg_core_if_t *core_if = otg_dev->core_if;\n+\n+\tDWC_PRINTF(\"%s called\\n\", __FUNCTION__);\n+\n+\tif (core_if->power_down == 2) {\n+\t\tif (core_if->hibernation_suspend <= 0) {\n+\t\t\tDWC_PRINTF(\"Already exited from Hibernation\\n\");\n+\t\t\treturn 1;\n+\t\t} else\n+\t\t\tgpwrdn_temp.d32 = core_if->gr_backup->gpwrdn_local;\n+\n+\t} else {\n+\t\tgpwrdn_temp.d32 = core_if->adp.gpwrdn;\n+\t}\n+\n+\tgpwrdn.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);\n+\n+\tif (gpwrdn.b.idsts ^ gpwrdn_temp.b.idsts) {\n+\t\tretval = dwc_otg_handle_pwrdn_idsts_change(otg_dev);\n+\t} else if (gpwrdn.b.bsessvld ^ gpwrdn_temp.b.bsessvld) {\n+\t\tretval = dwc_otg_handle_pwrdn_session_change(core_if);\n+\t}\n+\n+\treturn retval;\n+}\n+\n+/**\n+ * This interrupt indicates that the Wakeup Logic has detected a\n+ * SRP.\n+ */\n+static int32_t dwc_otg_handle_pwrdn_srp_intr(dwc_otg_core_if_t * core_if)\n+{\n+\tgpwrdn_data_t gpwrdn = {.d32 = 0 };\n+\n+\tDWC_PRINTF(\"%s called\\n\", __FUNCTION__);\n+\n+\tif (!core_if->hibernation_suspend) {\n+\t\tDWC_PRINTF(\"Already exited from Hibernation\\n\");\n+\t\treturn 1;\n+\t}\n+#ifdef DWC_DEV_SRPCAP\n+\tif (core_if->pwron_timer_started) {\n+\t\tcore_if->pwron_timer_started = 0;\n+\t\tDWC_TIMER_CANCEL(core_if->pwron_timer);\n+\t}\n+#endif\n+\n+\t/* Switch on the voltage to the core */\n+\tgpwrdn.b.pwrdnswtch = 1;\n+\tDWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);\n+\tdwc_udelay(10);\n+\n+\t/* Reset the core */\n+\tgpwrdn.d32 = 0;\n+\tgpwrdn.b.pwrdnrstn = 1;\n+\tDWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);\n+\tdwc_udelay(10);\n+\n+\t/* Disable power clamps */\n+\tgpwrdn.d32 = 0;\n+\tgpwrdn.b.pwrdnclmp = 1;\n+\tDWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);\n+\n+\t/* Remove reset the core signal */\n+\tgpwrdn.d32 = 0;\n+\tgpwrdn.b.pwrdnrstn = 1;\n+\tDWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);\n+\tdwc_udelay(10);\n+\n+\t/* Disable PMU interrupt */\n+\tgpwrdn.d32 = 0;\n+\tgpwrdn.b.pmuintsel = 1;\n+\tDWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);\n+\n+\t/* Indicates that we are exiting from hibernation */\n+\tcore_if->hibernation_suspend = 0;\n+\n+\t/* Disable PMU */\n+\tgpwrdn.d32 = 0;\n+\tgpwrdn.b.pmuactv = 1;\n+\tDWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);\n+\tdwc_udelay(10);\n+\n+\t/* Programm Disable VBUS to 0 */\n+\tgpwrdn.d32 = 0;\n+\tgpwrdn.b.dis_vbus = 1;\n+\tDWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);\n+\n+\t/*Initialize the core as Host */\n+\tcore_if->op_state = A_HOST;\n+\tdwc_otg_core_init(core_if);\n+\tdwc_otg_enable_global_interrupts(core_if);\n+\tcil_hcd_start(core_if);\n+\n+\treturn 1;\n+}\n+\n+/** This interrupt indicates that restore command after Hibernation\n+ * was completed by the core. */\n+int32_t dwc_otg_handle_restore_done_intr(dwc_otg_core_if_t * core_if)\n+{\n+\tpcgcctl_data_t pcgcctl;\n+\tDWC_DEBUGPL(DBG_ANY, \"++Restore Done Interrupt++\\n\");\n+\n+\t//TODO De-assert restore signal. 8.a\n+\tpcgcctl.d32 = DWC_READ_REG32(core_if->pcgcctl);\n+\tif (pcgcctl.b.restoremode == 1) {\n+\t\tgintmsk_data_t gintmsk = {.d32 = 0 };\n+\t\t/*\n+\t\t * If restore mode is Remote Wakeup,\n+\t\t * unmask Remote Wakeup interrupt.\n+\t\t */\n+\t\tgintmsk.b.wkupintr = 1;\n+\t\tDWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk,\n+\t\t\t\t 0, gintmsk.d32);\n+\t}\n+\n+\treturn 1;\n+}\n+\n+/**\n+ * This interrupt indicates that a device has been disconnected from\n+ * the root port.\n+ */\n+int32_t dwc_otg_handle_disconnect_intr(dwc_otg_core_if_t * core_if)\n+{\n+\tgintsts_data_t gintsts;\n+\n+\tDWC_DEBUGPL(DBG_ANY, \"++Disconnect Detected Interrupt++ (%s) %s\\n\",\n+\t\t    (dwc_otg_is_host_mode(core_if) ? \"Host\" : \"Device\"),\n+\t\t    op_state_str(core_if));\n+\n+/** @todo Consolidate this if statement. */\n+#ifndef DWC_HOST_ONLY\n+\tif (core_if->op_state == B_HOST) {\n+\t\t/* If in device mode Disconnect and stop the HCD, then\n+\t\t * start the PCD. */\n+\t\tDWC_SPINUNLOCK(core_if->lock);\n+\t\tcil_hcd_disconnect(core_if);\n+\t\tcil_pcd_start(core_if);\n+\t\tDWC_SPINLOCK(core_if->lock);\n+\t\tcore_if->op_state = B_PERIPHERAL;\n+\t} else if (dwc_otg_is_device_mode(core_if)) {\n+\t\tgotgctl_data_t gotgctl = {.d32 = 0 };\n+\t\tgotgctl.d32 =\n+\t\t    DWC_READ_REG32(&core_if->core_global_regs->gotgctl);\n+\t\tif (gotgctl.b.hstsethnpen == 1) {\n+\t\t\t/* Do nothing, if HNP in process the OTG\n+\t\t\t * interrupt \"Host Negotiation Detected\"\n+\t\t\t * interrupt will do the mode switch.\n+\t\t\t */\n+\t\t} else if (gotgctl.b.devhnpen == 0) {\n+\t\t\t/* If in device mode Disconnect and stop the HCD, then\n+\t\t\t * start the PCD. */\n+\t\t\tDWC_SPINUNLOCK(core_if->lock);\n+\t\t\tcil_hcd_disconnect(core_if);\n+\t\t\tcil_pcd_start(core_if);\n+\t\t\tDWC_SPINLOCK(core_if->lock);\n+\t\t\tcore_if->op_state = B_PERIPHERAL;\n+\t\t} else {\n+\t\t\tDWC_DEBUGPL(DBG_ANY, \"!a_peripheral && !devhnpen\\n\");\n+\t\t}\n+\t} else {\n+\t\tif (core_if->op_state == A_HOST) {\n+\t\t\t/* A-Cable still connected but device disconnected. */\n+\t\t\tDWC_SPINUNLOCK(core_if->lock);\n+\t\t\tcil_hcd_disconnect(core_if);\n+\t\t\tDWC_SPINLOCK(core_if->lock);\n+\t\t\tif (core_if->adp_enable) {\n+\t\t\t\tgpwrdn_data_t gpwrdn = { .d32 = 0 };\n+\t\t\t\tcil_hcd_stop(core_if);\n+\t\t\t\t/* Enable Power Down Logic */\n+\t\t\t\tgpwrdn.b.pmuintsel = 1;\n+\t\t\t\tgpwrdn.b.pmuactv = 1;\n+\t\t\t\tDWC_MODIFY_REG32(&core_if->core_global_regs->\n+\t\t\t\t\t\t gpwrdn, 0, gpwrdn.d32);\n+\t\t\t\tdwc_otg_adp_probe_start(core_if);\n+\n+\t\t\t\t/* Power off the core */\n+\t\t\t\tif (core_if->power_down == 2) {\n+\t\t\t\t\tgpwrdn.d32 = 0;\n+\t\t\t\t\tgpwrdn.b.pwrdnswtch = 1;\n+\t\t\t\t\tDWC_MODIFY_REG32\n+\t\t\t\t\t    (&core_if->core_global_regs->gpwrdn,\n+\t\t\t\t\t     gpwrdn.d32, 0);\n+\t\t\t\t}\n+\t\t\t}\n+\t\t}\n+\t}\n+#endif\n+\t/* Change to L3(OFF) state */\n+\tcore_if->lx_state = DWC_OTG_L3;\n+\n+\tgintsts.d32 = 0;\n+\tgintsts.b.disconnect = 1;\n+\tDWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);\n+\treturn 1;\n+}\n+\n+/**\n+ * This interrupt indicates that SUSPEND state has been detected on\n+ * the USB.\n+ *\n+ * For HNP the USB Suspend interrupt signals the change from\n+ * \"a_peripheral\" to \"a_host\".\n+ *\n+ * When power management is enabled the core will be put in low power\n+ * mode.\n+ */\n+int32_t dwc_otg_handle_usb_suspend_intr(dwc_otg_core_if_t * core_if)\n+{\n+\tdsts_data_t dsts;\n+\tgintsts_data_t gintsts;\n+\tdcfg_data_t dcfg;\n+\n+\tDWC_DEBUGPL(DBG_ANY, \"USB SUSPEND\\n\");\n+\n+\tif (dwc_otg_is_device_mode(core_if)) {\n+\t\t/* Check the Device status register to determine if the Suspend\n+\t\t * state is active. */\n+\t\tdsts.d32 =\n+\t\t    DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);\n+\t\tDWC_DEBUGPL(DBG_PCD, \"DSTS=0x%0x\\n\", dsts.d32);\n+\t\tDWC_DEBUGPL(DBG_PCD, \"DSTS.Suspend Status=%d \"\n+\t\t\t    \"HWCFG4.power Optimize=%d\\n\",\n+\t\t\t    dsts.b.suspsts, core_if->hwcfg4.b.power_optimiz);\n+\n+#ifdef PARTIAL_POWER_DOWN\n+/** @todo Add a module parameter for power management. */\n+\n+\t\tif (dsts.b.suspsts && core_if->hwcfg4.b.power_optimiz) {\n+\t\t\tpcgcctl_data_t power = {.d32 = 0 };\n+\t\t\tDWC_DEBUGPL(DBG_CIL, \"suspend\\n\");\n+\n+\t\t\tpower.b.pwrclmp = 1;\n+\t\t\tDWC_WRITE_REG32(core_if->pcgcctl, power.d32);\n+\n+\t\t\tpower.b.rstpdwnmodule = 1;\n+\t\t\tDWC_MODIFY_REG32(core_if->pcgcctl, 0, power.d32);\n+\n+\t\t\tpower.b.stoppclk = 1;\n+\t\t\tDWC_MODIFY_REG32(core_if->pcgcctl, 0, power.d32);\n+\n+\t\t} else {\n+\t\t\tDWC_DEBUGPL(DBG_ANY, \"disconnect?\\n\");\n+\t\t}\n+#endif\n+\t\t/* PCD callback for suspend. Release the lock inside of callback function */\n+\t\tcil_pcd_suspend(core_if);\n+\t\tif (core_if->power_down == 2)\n+\t\t{\n+\t\t\tdcfg.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg);\n+\t\t\tDWC_DEBUGPL(DBG_ANY,\"lx_state = %08x\\n\",core_if->lx_state);\n+\t\t\tDWC_DEBUGPL(DBG_ANY,\" device address = %08d\\n\",dcfg.b.devaddr);\n+\n+\t\t\tif (core_if->lx_state != DWC_OTG_L3 && dcfg.b.devaddr) {\n+\t\t\t\tpcgcctl_data_t pcgcctl = {.d32 = 0 };\n+\t\t\t\tgpwrdn_data_t gpwrdn = {.d32 = 0 };\n+\t\t\t\tgusbcfg_data_t gusbcfg = {.d32 = 0 };\n+\n+\t\t\t\t/* Change to L2(suspend) state */\n+\t\t\t\tcore_if->lx_state = DWC_OTG_L2;\n+\n+\t\t\t\t/* Clear interrupt in gintsts */\n+\t\t\t\tgintsts.d32 = 0;\n+\t\t\t\tgintsts.b.usbsuspend = 1;\n+\t\t\t\tDWC_WRITE_REG32(&core_if->core_global_regs->\n+\t\t\t\t\t\tgintsts, gintsts.d32);\n+\t\t\t\tDWC_PRINTF(\"Start of hibernation completed\\n\");\n+\t\t\t\tdwc_otg_save_global_regs(core_if);\n+\t\t\t\tdwc_otg_save_dev_regs(core_if);\n+\n+\t\t\t\tgusbcfg.d32 =\n+\t\t\t\t    DWC_READ_REG32(&core_if->core_global_regs->\n+\t\t\t\t\t\t   gusbcfg);\n+\t\t\t\tif (gusbcfg.b.ulpi_utmi_sel == 1) {\n+\t\t\t\t\t/* ULPI interface */\n+\t\t\t\t\t/* Suspend the Phy Clock */\n+\t\t\t\t\tpcgcctl.d32 = 0;\n+\t\t\t\t\tpcgcctl.b.stoppclk = 1;\n+\t\t\t\t\tDWC_MODIFY_REG32(core_if->pcgcctl, 0,\n+\t\t\t\t\t\t\t pcgcctl.d32);\n+\t\t\t\t\tdwc_udelay(10);\n+\t\t\t\t\tgpwrdn.b.pmuactv = 1;\n+\t\t\t\t\tDWC_MODIFY_REG32(&core_if->\n+\t\t\t\t\t\t\t core_global_regs->\n+\t\t\t\t\t\t\t gpwrdn, 0, gpwrdn.d32);\n+\t\t\t\t} else {\n+\t\t\t\t\t/* UTMI+ Interface */\n+\t\t\t\t\tgpwrdn.b.pmuactv = 1;\n+\t\t\t\t\tDWC_MODIFY_REG32(&core_if->\n+\t\t\t\t\t\t\t core_global_regs->\n+\t\t\t\t\t\t\t gpwrdn, 0, gpwrdn.d32);\n+\t\t\t\t\tdwc_udelay(10);\n+\t\t\t\t\tpcgcctl.b.stoppclk = 1;\n+\t\t\t\t\tDWC_MODIFY_REG32(core_if->pcgcctl, 0,\n+\t\t\t\t\t\t\t pcgcctl.d32);\n+\t\t\t\t\tdwc_udelay(10);\n+\t\t\t\t}\n+\n+\t\t\t\t/* Set flag to indicate that we are in hibernation */\n+\t\t\t\tcore_if->hibernation_suspend = 1;\n+\t\t\t\t/* Enable interrupts from wake up logic */\n+\t\t\t\tgpwrdn.d32 = 0;\n+\t\t\t\tgpwrdn.b.pmuintsel = 1;\n+\t\t\t\tDWC_MODIFY_REG32(&core_if->core_global_regs->\n+\t\t\t\t\t\t gpwrdn, 0, gpwrdn.d32);\n+\t\t\t\tdwc_udelay(10);\n+\n+\t\t\t\t/* Unmask device mode interrupts in GPWRDN */\n+\t\t\t\tgpwrdn.d32 = 0;\n+\t\t\t\tgpwrdn.b.rst_det_msk = 1;\n+\t\t\t\tgpwrdn.b.lnstchng_msk = 1;\n+\t\t\t\tgpwrdn.b.sts_chngint_msk = 1;\n+\t\t\t\tDWC_MODIFY_REG32(&core_if->core_global_regs->\n+\t\t\t\t\t\t gpwrdn, 0, gpwrdn.d32);\n+\t\t\t\tdwc_udelay(10);\n+\n+\t\t\t\t/* Enable Power Down Clamp */\n+\t\t\t\tgpwrdn.d32 = 0;\n+\t\t\t\tgpwrdn.b.pwrdnclmp = 1;\n+\t\t\t\tDWC_MODIFY_REG32(&core_if->core_global_regs->\n+\t\t\t\t\t\t gpwrdn, 0, gpwrdn.d32);\n+\t\t\t\tdwc_udelay(10);\n+\n+\t\t\t\t/* Switch off VDD */\n+\t\t\t\tgpwrdn.d32 = 0;\n+\t\t\t\tgpwrdn.b.pwrdnswtch = 1;\n+\t\t\t\tDWC_MODIFY_REG32(&core_if->core_global_regs->\n+\t\t\t\t\t\t gpwrdn, 0, gpwrdn.d32);\n+\n+\t\t\t\t/* Save gpwrdn register for further usage if stschng interrupt */\n+\t\t\t\tcore_if->gr_backup->gpwrdn_local =\n+\t\t\t\t\t\t\tDWC_READ_REG32(&core_if->core_global_regs->gpwrdn);\n+\t\t\t\tDWC_PRINTF(\"Hibernation completed\\n\");\n+\n+\t\t\t\treturn 1;\n+\t\t\t}\n+\t\t} else if (core_if->power_down == 3) {\n+\t\t\tpcgcctl_data_t pcgcctl = {.d32 = 0 };\n+\t\t\tdcfg.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg);\n+\t\t\tDWC_DEBUGPL(DBG_ANY, \"lx_state = %08x\\n\",core_if->lx_state);\n+\t\t\tDWC_DEBUGPL(DBG_ANY, \" device address = %08d\\n\",dcfg.b.devaddr);\n+\n+\t\t\tif (core_if->lx_state != DWC_OTG_L3 && dcfg.b.devaddr) {\n+\t\t\t\tDWC_DEBUGPL(DBG_ANY, \"Start entering to extended hibernation\\n\");\n+\t\t\t\tcore_if->xhib = 1;\n+\n+\t\t\t\t/* Clear interrupt in gintsts */\n+\t\t\t\tgintsts.d32 = 0;\n+\t\t\t\tgintsts.b.usbsuspend = 1;\n+\t\t\t\tDWC_WRITE_REG32(&core_if->core_global_regs->\n+\t\t\t\t\tgintsts, gintsts.d32);\n+\n+\t\t\t\tdwc_otg_save_global_regs(core_if);\n+\t\t\t\tdwc_otg_save_dev_regs(core_if);\n+\n+\t\t\t\t/* Wait for 10 PHY clocks */\n+\t\t\t\tdwc_udelay(10);\n+\n+\t\t\t\t/* Program GPIO register while entering to xHib */\n+\t\t\t\tDWC_WRITE_REG32(&core_if->core_global_regs->ggpio, 0x1);\n+\n+\t\t\t\tpcgcctl.b.enbl_extnd_hiber = 1;\n+\t\t\t\tDWC_MODIFY_REG32(core_if->pcgcctl, 0, pcgcctl.d32);\n+\t\t\t\tDWC_MODIFY_REG32(core_if->pcgcctl, 0, pcgcctl.d32);\n+\n+\t\t\t\tpcgcctl.d32 = 0;\n+\t\t\t\tpcgcctl.b.extnd_hiber_pwrclmp = 1;\n+\t\t\t\tDWC_MODIFY_REG32(core_if->pcgcctl, 0, pcgcctl.d32);\n+\n+\t\t\t\tpcgcctl.d32 = 0;\n+\t\t\t\tpcgcctl.b.extnd_hiber_switch = 1;\n+\t\t\t\tcore_if->gr_backup->xhib_gpwrdn = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);\n+\t\t\t\tcore_if->gr_backup->xhib_pcgcctl = DWC_READ_REG32(core_if->pcgcctl) | pcgcctl.d32;\n+\t\t\t\tDWC_MODIFY_REG32(core_if->pcgcctl, 0, pcgcctl.d32);\n+\n+\t\t\t\tDWC_DEBUGPL(DBG_ANY, \"Finished entering to extended hibernation\\n\");\n+\n+\t\t\t\treturn 1;\n+\t\t\t}\n+\t\t}\n+\t} else {\n+\t\tif (core_if->op_state == A_PERIPHERAL) {\n+\t\t\tDWC_DEBUGPL(DBG_ANY, \"a_peripheral->a_host\\n\");\n+\t\t\t/* Clear the a_peripheral flag, back to a_host. */\n+\t\t\tDWC_SPINUNLOCK(core_if->lock);\n+\t\t\tcil_pcd_stop(core_if);\n+\t\t\tcil_hcd_start(core_if);\n+\t\t\tDWC_SPINLOCK(core_if->lock);\n+\t\t\tcore_if->op_state = A_HOST;\n+\t\t}\n+\t}\n+\n+\t/* Change to L2(suspend) state */\n+\tcore_if->lx_state = DWC_OTG_L2;\n+\n+\t/* Clear interrupt */\n+\tgintsts.d32 = 0;\n+\tgintsts.b.usbsuspend = 1;\n+\tDWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);\n+\n+\treturn 1;\n+}\n+\n+static int32_t dwc_otg_handle_xhib_exit_intr(dwc_otg_core_if_t * core_if)\n+{\n+\tgpwrdn_data_t gpwrdn = {.d32 = 0 };\n+\tpcgcctl_data_t pcgcctl = {.d32 = 0 };\n+\tgahbcfg_data_t gahbcfg = {.d32 = 0 };\n+\n+\tdwc_udelay(10);\n+\n+\t/* Program GPIO register while entering to xHib */\n+\tDWC_WRITE_REG32(&core_if->core_global_regs->ggpio, 0x0);\n+\n+\tpcgcctl.d32 = core_if->gr_backup->xhib_pcgcctl;\n+\tpcgcctl.b.extnd_hiber_pwrclmp = 0;\n+\tDWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32);\n+\tdwc_udelay(10);\n+\n+\tgpwrdn.d32 = core_if->gr_backup->xhib_gpwrdn;\n+\tgpwrdn.b.restore = 1;\n+\tDWC_WRITE_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32);\n+\tdwc_udelay(10);\n+\n+\trestore_lpm_i2c_regs(core_if);\n+\n+\tpcgcctl.d32 = core_if->gr_backup->pcgcctl_local & (0x3FFFF << 14);\n+\tpcgcctl.b.max_xcvrselect = 1;\n+\tpcgcctl.b.ess_reg_restored = 0;\n+\tpcgcctl.b.extnd_hiber_switch = 0;\n+\tpcgcctl.b.extnd_hiber_pwrclmp = 0;\n+\tpcgcctl.b.enbl_extnd_hiber = 1;\n+\tDWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32);\n+\n+\tgahbcfg.d32 = core_if->gr_backup->gahbcfg_local;\n+\tgahbcfg.b.glblintrmsk = 1;\n+\tDWC_WRITE_REG32(&core_if->core_global_regs->gahbcfg, gahbcfg.d32);\n+\n+\tDWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);\n+\tDWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, 0x1 << 16);\n+\n+\tDWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg,\n+\t\t\tcore_if->gr_backup->gusbcfg_local);\n+\tDWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg,\n+\t\t\tcore_if->dr_backup->dcfg);\n+\n+\tpcgcctl.d32 = 0;\n+\tpcgcctl.d32 = core_if->gr_backup->pcgcctl_local & (0x3FFFF << 14);\n+\tpcgcctl.b.max_xcvrselect = 1;\n+\tpcgcctl.d32 |= 0x608;\n+\tDWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32);\n+\tdwc_udelay(10);\n+\n+\tpcgcctl.d32 = 0;\n+\tpcgcctl.d32 = core_if->gr_backup->pcgcctl_local & (0x3FFFF << 14);\n+\tpcgcctl.b.max_xcvrselect = 1;\n+\tpcgcctl.b.ess_reg_restored = 1;\n+\tpcgcctl.b.enbl_extnd_hiber = 1;\n+\tpcgcctl.b.rstpdwnmodule = 1;\n+\tpcgcctl.b.restoremode = 1;\n+\tDWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32);\n+\n+\tDWC_DEBUGPL(DBG_ANY, \"%s called\\n\", __FUNCTION__);\n+\n+\treturn 1;\n+}\n+\n+#ifdef CONFIG_USB_DWC_OTG_LPM\n+/**\n+ * This function hadles LPM transaction received interrupt.\n+ */\n+static int32_t dwc_otg_handle_lpm_intr(dwc_otg_core_if_t * core_if)\n+{\n+\tglpmcfg_data_t lpmcfg;\n+\tgintsts_data_t gintsts;\n+\n+\tif (!core_if->core_params->lpm_enable) {\n+\t\tDWC_PRINTF(\"Unexpected LPM interrupt\\n\");\n+\t}\n+\n+\tlpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);\n+\tDWC_PRINTF(\"LPM config register = 0x%08x\\n\", lpmcfg.d32);\n+\n+\tif (dwc_otg_is_host_mode(core_if)) {\n+\t\tcil_hcd_sleep(core_if);\n+\t} else {\n+\t\tlpmcfg.b.hird_thres |= (1 << 4);\n+\t\tDWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg,\n+\t\t\t\tlpmcfg.d32);\n+\t}\n+\n+\t/* Examine prt_sleep_sts after TL1TokenTetry period max (10 us) */\n+\tdwc_udelay(10);\n+\tlpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);\n+\tif (lpmcfg.b.prt_sleep_sts) {\n+\t\t/* Save the current state */\n+\t\tcore_if->lx_state = DWC_OTG_L1;\n+\t}\n+\n+\t/* Clear interrupt  */\n+\tgintsts.d32 = 0;\n+\tgintsts.b.lpmtranrcvd = 1;\n+\tDWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);\n+\treturn 1;\n+}\n+#endif /* CONFIG_USB_DWC_OTG_LPM */\n+\n+/**\n+ * This function returns the Core Interrupt register.\n+ */\n+static inline uint32_t dwc_otg_read_common_intr(dwc_otg_core_if_t * core_if, gintmsk_data_t *reenable_gintmsk, dwc_otg_hcd_t *hcd)\n+{\n+\tgahbcfg_data_t gahbcfg = {.d32 = 0 };\n+\tgintsts_data_t gintsts;\n+\tgintmsk_data_t gintmsk;\n+\tgintmsk_data_t gintmsk_common = {.d32 = 0 };\n+\tgintmsk_common.b.wkupintr = 1;\n+\tgintmsk_common.b.sessreqintr = 1;\n+\tgintmsk_common.b.conidstschng = 1;\n+\tgintmsk_common.b.otgintr = 1;\n+\tgintmsk_common.b.modemismatch = 1;\n+\tgintmsk_common.b.disconnect = 1;\n+\tgintmsk_common.b.usbsuspend = 1;\n+#ifdef CONFIG_USB_DWC_OTG_LPM\n+\tgintmsk_common.b.lpmtranrcvd = 1;\n+#endif\n+\tgintmsk_common.b.restoredone = 1;\n+\tif(dwc_otg_is_device_mode(core_if))\n+\t{\n+\t\t/** @todo: The port interrupt occurs while in device\n+\t\t * mode. Added code to CIL to clear the interrupt for now!\n+\t\t */\n+\t\tgintmsk_common.b.portintr = 1;\n+\t}\n+\tif(fiq_enable) {\n+\t\tlocal_fiq_disable();\n+\t\tfiq_fsm_spin_lock(&hcd->fiq_state->lock);\n+\t\tgintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts);\n+\t\tgintmsk.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintmsk);\n+\t\t/* Pull in the interrupts that the FIQ has masked */\n+\t\tgintmsk.d32 |= ~(hcd->fiq_state->gintmsk_saved.d32);\n+\t\tgintmsk.d32 |= gintmsk_common.d32;\n+\t\t/* for the upstairs function to reenable - have to read it here in case FIQ triggers again */\n+\t\treenable_gintmsk->d32 = gintmsk.d32;\n+\t\tfiq_fsm_spin_unlock(&hcd->fiq_state->lock);\n+\t\tlocal_fiq_enable();\n+\t} else {\n+\t\tgintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts);\n+\t\tgintmsk.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintmsk);\n+\t}\n+\n+\tgahbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gahbcfg);\n+\n+#ifdef DEBUG\n+\t/* if any common interrupts set */\n+\tif (gintsts.d32 & gintmsk_common.d32) {\n+\t\tDWC_DEBUGPL(DBG_ANY, \"common_intr: gintsts=%08x  gintmsk=%08x\\n\",\n+\t\t\t    gintsts.d32, gintmsk.d32);\n+\t}\n+#endif\n+\tif (!fiq_enable){\n+\t\tif (gahbcfg.b.glblintrmsk)\n+\t\t\treturn ((gintsts.d32 & gintmsk.d32) & gintmsk_common.d32);\n+\t\telse\n+\t\t\treturn 0;\n+\t} else {\n+\t\t/* Our IRQ kicker is no longer the USB hardware, it's the MPHI interface.\n+\t\t * Can't trust the global interrupt mask bit in this case.\n+\t\t */\n+\t\treturn ((gintsts.d32 & gintmsk.d32) & gintmsk_common.d32);\n+\t}\n+\n+}\n+\n+/* MACRO for clearing interupt bits in GPWRDN register */\n+#define CLEAR_GPWRDN_INTR(__core_if,__intr) \\\n+do { \\\n+\t\tgpwrdn_data_t gpwrdn = {.d32=0}; \\\n+\t\tgpwrdn.b.__intr = 1; \\\n+\t\tDWC_MODIFY_REG32(&__core_if->core_global_regs->gpwrdn, \\\n+\t\t0, gpwrdn.d32); \\\n+} while (0)\n+\n+/**\n+ * Common interrupt handler.\n+ *\n+ * The common interrupts are those that occur in both Host and Device mode.\n+ * This handler handles the following interrupts:\n+ * - Mode Mismatch Interrupt\n+ * - Disconnect Interrupt\n+ * - OTG Interrupt\n+ * - Connector ID Status Change Interrupt\n+ * - Session Request Interrupt.\n+ * - Resume / Remote Wakeup Detected Interrupt.\n+ * - LPM Transaction Received Interrupt\n+ * - ADP Transaction Received Interrupt\n+ *\n+ */\n+int32_t dwc_otg_handle_common_intr(void *dev)\n+{\n+\tint retval = 0;\n+\tgintsts_data_t gintsts;\n+\tgintmsk_data_t gintmsk_reenable = { .d32 = 0 };\n+\tgpwrdn_data_t gpwrdn = {.d32 = 0 };\n+\tdwc_otg_device_t *otg_dev = dev;\n+\tdwc_otg_core_if_t *core_if = otg_dev->core_if;\n+\tgpwrdn.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);\n+\tif (dwc_otg_is_device_mode(core_if))\n+\t\tcore_if->frame_num = dwc_otg_get_frame_number(core_if);\n+\n+\tif (core_if->lock)\n+\t\tDWC_SPINLOCK(core_if->lock);\n+\n+\tif (core_if->power_down == 3 && core_if->xhib == 1) {\n+\t\tDWC_DEBUGPL(DBG_ANY, \"Exiting from xHIB state\\n\");\n+\t\tretval |= dwc_otg_handle_xhib_exit_intr(core_if);\n+\t\tcore_if->xhib = 2;\n+\t\tif (core_if->lock)\n+\t\t\tDWC_SPINUNLOCK(core_if->lock);\n+\n+\t\treturn retval;\n+\t}\n+\n+\tif (core_if->hibernation_suspend <= 0) {\n+\t\t/* read_common will have to poke the FIQ's saved mask. We must then clear this mask at the end\n+\t\t * of this handler - god only knows why it's done like this\n+\t\t */\n+\t\tgintsts.d32 = dwc_otg_read_common_intr(core_if, &gintmsk_reenable, otg_dev->hcd);\n+\n+\t\tif (gintsts.b.modemismatch) {\n+\t\t\tretval |= dwc_otg_handle_mode_mismatch_intr(core_if);\n+\t\t}\n+\t\tif (gintsts.b.otgintr) {\n+\t\t\tretval |= dwc_otg_handle_otg_intr(core_if);\n+\t\t}\n+\t\tif (gintsts.b.conidstschng) {\n+\t\t\tretval |=\n+\t\t\t    dwc_otg_handle_conn_id_status_change_intr(core_if);\n+\t\t}\n+\t\tif (gintsts.b.disconnect) {\n+\t\t\tretval |= dwc_otg_handle_disconnect_intr(core_if);\n+\t\t}\n+\t\tif (gintsts.b.sessreqintr) {\n+\t\t\tretval |= dwc_otg_handle_session_req_intr(core_if);\n+\t\t}\n+\t\tif (gintsts.b.wkupintr) {\n+\t\t\tretval |= dwc_otg_handle_wakeup_detected_intr(core_if);\n+\t\t}\n+\t\tif (gintsts.b.usbsuspend) {\n+\t\t\tretval |= dwc_otg_handle_usb_suspend_intr(core_if);\n+\t\t}\n+#ifdef CONFIG_USB_DWC_OTG_LPM\n+\t\tif (gintsts.b.lpmtranrcvd) {\n+\t\t\tretval |= dwc_otg_handle_lpm_intr(core_if);\n+\t\t}\n+#endif\n+\t\tif (gintsts.b.restoredone) {\n+\t\t\tgintsts.d32 = 0;\n+\t                if (core_if->power_down == 2)\n+\t\t\t\tcore_if->hibernation_suspend = -1;\n+\t\t\telse if (core_if->power_down == 3 && core_if->xhib == 2) {\n+\t\t\t\tgpwrdn_data_t gpwrdn = {.d32 = 0 };\n+\t\t\t\tpcgcctl_data_t pcgcctl = {.d32 = 0 };\n+\t\t\t\tdctl_data_t dctl = {.d32 = 0 };\n+\n+\t\t\t\tDWC_WRITE_REG32(&core_if->core_global_regs->\n+\t\t\t\t\t\tgintsts, 0xFFFFFFFF);\n+\n+\t\t\t\tDWC_DEBUGPL(DBG_ANY,\n+\t\t\t\t\t    \"RESTORE DONE generated\\n\");\n+\n+\t\t\t\tgpwrdn.b.restore = 1;\n+\t\t\t\tDWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);\n+\t\t\t\tdwc_udelay(10);\n+\n+\t\t\t\tpcgcctl.b.rstpdwnmodule = 1;\n+\t\t\t\tDWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0);\n+\n+\t\t\t\tDWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, core_if->gr_backup->gusbcfg_local);\n+\t\t\t\tDWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg, core_if->dr_backup->dcfg);\n+\t\t\t\tDWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, core_if->dr_backup->dctl);\n+\t\t\t\tdwc_udelay(50);\n+\n+\t\t\t\tdctl.b.pwronprgdone = 1;\n+\t\t\t\tDWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0, dctl.d32);\n+\t\t\t\tdwc_udelay(10);\n+\n+\t\t\t\tdwc_otg_restore_global_regs(core_if);\n+\t\t\t\tdwc_otg_restore_dev_regs(core_if, 0);\n+\n+\t\t\t\tdctl.d32 = 0;\n+\t\t\t\tdctl.b.pwronprgdone = 1;\n+\t\t\t\tDWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32, 0);\n+\t\t\t\tdwc_udelay(10);\n+\n+\t\t\t\tpcgcctl.d32 = 0;\n+\t\t\t\tpcgcctl.b.enbl_extnd_hiber = 1;\n+\t\t\t\tDWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0);\n+\n+\t\t\t\t/* The core will be in ON STATE */\n+\t\t\t\tcore_if->lx_state = DWC_OTG_L0;\n+\t\t\t\tcore_if->xhib = 0;\n+\n+\t\t\t\tDWC_SPINUNLOCK(core_if->lock);\n+\t\t\t\tif (core_if->pcd_cb && core_if->pcd_cb->resume_wakeup) {\n+\t\t\t\t\tcore_if->pcd_cb->resume_wakeup(core_if->pcd_cb->p);\n+\t\t\t\t}\n+\t\t\t\tDWC_SPINLOCK(core_if->lock);\n+\n+\t\t\t}\n+\n+\t\t\tgintsts.b.restoredone = 1;\n+\t\t\tDWC_WRITE_REG32(&core_if->core_global_regs->gintsts,gintsts.d32);\n+\t\t\tDWC_PRINTF(\" --Restore done interrupt received-- \\n\");\n+\t\t\tretval |= 1;\n+\t\t}\n+\t\tif (gintsts.b.portintr && dwc_otg_is_device_mode(core_if)) {\n+\t\t\t/* The port interrupt occurs while in device mode with HPRT0\n+\t\t\t * Port Enable/Disable.\n+\t\t\t */\n+\t\t\tgintsts.d32 = 0;\n+\t\t\tgintsts.b.portintr = 1;\n+\t\t\tDWC_WRITE_REG32(&core_if->core_global_regs->gintsts,gintsts.d32);\n+\t\t\tretval |= 1;\n+\t\t\tgintmsk_reenable.b.portintr = 1;\n+\n+\t\t}\n+\t\t/* Did we actually handle anything? if so, unmask the interrupt */\n+//\t\tfiq_print(FIQDBG_INT, otg_dev->hcd->fiq_state, \"CILOUT %1d\", retval);\n+//\t\tfiq_print(FIQDBG_INT, otg_dev->hcd->fiq_state, \"%08x\", gintsts.d32);\n+//\t\tfiq_print(FIQDBG_INT, otg_dev->hcd->fiq_state, \"%08x\", gintmsk_reenable.d32);\n+\t\tif (retval && fiq_enable) {\n+\t\t\tDWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, gintmsk_reenable.d32);\n+\t\t}\n+\n+\t} else {\n+\t\tDWC_DEBUGPL(DBG_ANY, \"gpwrdn=%08x\\n\", gpwrdn.d32);\n+\n+\t\tif (gpwrdn.b.disconn_det && gpwrdn.b.disconn_det_msk) {\n+\t\t\tCLEAR_GPWRDN_INTR(core_if, disconn_det);\n+\t\t\tif (gpwrdn.b.linestate == 0) {\n+\t\t\t\tdwc_otg_handle_pwrdn_disconnect_intr(core_if);\n+\t\t\t} else {\n+\t\t\t\tDWC_PRINTF(\"Disconnect detected while linestate is not 0\\n\");\n+\t\t\t}\n+\n+\t\t\tretval |= 1;\n+\t\t}\n+\t\tif (gpwrdn.b.lnstschng && gpwrdn.b.lnstchng_msk) {\n+\t\t\tCLEAR_GPWRDN_INTR(core_if, lnstschng);\n+\t\t\t/* remote wakeup from hibernation */\n+\t\t\tif (gpwrdn.b.linestate == 2 || gpwrdn.b.linestate == 1) {\n+\t\t\t\tdwc_otg_handle_pwrdn_wakeup_detected_intr(core_if);\n+\t\t\t} else {\n+\t\t\t\tDWC_PRINTF(\"gpwrdn.linestate = %d\\n\", gpwrdn.b.linestate);\n+\t\t\t}\n+\t\t\tretval |= 1;\n+\t\t}\n+\t\tif (gpwrdn.b.rst_det && gpwrdn.b.rst_det_msk) {\n+\t\t\tCLEAR_GPWRDN_INTR(core_if, rst_det);\n+\t\t\tif (gpwrdn.b.linestate == 0) {\n+\t\t\t\tDWC_PRINTF(\"Reset detected\\n\");\n+\t\t\t\tretval |= dwc_otg_device_hibernation_restore(core_if, 0, 1);\n+\t\t\t}\n+\t\t}\n+\t\tif (gpwrdn.b.srp_det && gpwrdn.b.srp_det_msk) {\n+\t\t\tCLEAR_GPWRDN_INTR(core_if, srp_det);\n+\t\t\tdwc_otg_handle_pwrdn_srp_intr(core_if);\n+\t\t\tretval |= 1;\n+\t\t}\n+\t}\n+\t/* Handle ADP interrupt here */\n+\tif (gpwrdn.b.adp_int) {\n+\t\tDWC_PRINTF(\"ADP interrupt\\n\");\n+\t\tCLEAR_GPWRDN_INTR(core_if, adp_int);\n+\t\tdwc_otg_adp_handle_intr(core_if);\n+\t\tretval |= 1;\n+\t}\n+\tif (gpwrdn.b.sts_chngint && gpwrdn.b.sts_chngint_msk) {\n+\t\tDWC_PRINTF(\"STS CHNG interrupt asserted\\n\");\n+\t\tCLEAR_GPWRDN_INTR(core_if, sts_chngint);\n+\t\tdwc_otg_handle_pwrdn_stschng_intr(otg_dev);\n+\n+\t\tretval |= 1;\n+\t}\n+\tif (core_if->lock)\n+\t\tDWC_SPINUNLOCK(core_if->lock);\n+\treturn retval;\n+}\n--- /dev/null\n+++ b/drivers/usb/host/dwc_otg/dwc_otg_core_if.h\n@@ -0,0 +1,705 @@\n+/* ==========================================================================\n+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_core_if.h $\n+ * $Revision: #13 $\n+ * $Date: 2012/08/10 $\n+ * $Change: 2047372 $\n+ *\n+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,\n+ * \"Software\") is an Unsupported proprietary work of Synopsys, Inc. unless\n+ * otherwise expressly agreed to in writing between Synopsys and you.\n+ *\n+ * The Software IS NOT an item of Licensed Software or Licensed Product under\n+ * any End User Software License Agreement or Agreement for Licensed Product\n+ * with Synopsys or any supplement thereto. You are permitted to use and\n+ * redistribute this Software in source and binary forms, with or without\n+ * modification, provided that redistributions of source code must retain this\n+ * notice. You may not view, use, disclose, copy or distribute this file or\n+ * any information contained herein except pursuant to this license grant from\n+ * Synopsys. If you do not agree with this notice, including the disclaimer\n+ * below, then you are not authorized to use the Software.\n+ *\n+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN \"AS IS\" BASIS\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,\n+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH\n+ * DAMAGE.\n+ * ========================================================================== */\n+#if !defined(__DWC_CORE_IF_H__)\n+#define __DWC_CORE_IF_H__\n+\n+#include \"dwc_os.h\"\n+\n+/** @file\n+ * This file defines DWC_OTG Core API\n+ */\n+\n+struct dwc_otg_core_if;\n+typedef struct dwc_otg_core_if dwc_otg_core_if_t;\n+\n+/** Maximum number of Periodic FIFOs */\n+#define MAX_PERIO_FIFOS 15\n+/** Maximum number of Periodic FIFOs */\n+#define MAX_TX_FIFOS 15\n+\n+/** Maximum number of Endpoints/HostChannels */\n+#define MAX_EPS_CHANNELS 16\n+\n+extern dwc_otg_core_if_t *dwc_otg_cil_init(const uint32_t * _reg_base_addr);\n+extern void dwc_otg_core_init(dwc_otg_core_if_t * _core_if);\n+extern void dwc_otg_cil_remove(dwc_otg_core_if_t * _core_if);\n+\n+extern void dwc_otg_enable_global_interrupts(dwc_otg_core_if_t * _core_if);\n+extern void dwc_otg_disable_global_interrupts(dwc_otg_core_if_t * _core_if);\n+\n+extern uint8_t dwc_otg_is_device_mode(dwc_otg_core_if_t * _core_if);\n+extern uint8_t dwc_otg_is_host_mode(dwc_otg_core_if_t * _core_if);\n+\n+extern uint8_t dwc_otg_is_dma_enable(dwc_otg_core_if_t * core_if);\n+\n+/** This function should be called on every hardware interrupt. */\n+extern int32_t dwc_otg_handle_common_intr(void *otg_dev);\n+\n+/** @name OTG Core Parameters */\n+/** @{ */\n+\n+/**\n+ * Specifies the OTG capabilities. The driver will automatically\n+ * detect the value for this parameter if none is specified.\n+ * 0 - HNP and SRP capable (default)\n+ * 1 - SRP Only capable\n+ * 2 - No HNP/SRP capable\n+ */\n+extern int dwc_otg_set_param_otg_cap(dwc_otg_core_if_t * core_if, int32_t val);\n+extern int32_t dwc_otg_get_param_otg_cap(dwc_otg_core_if_t * core_if);\n+#define DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE 0\n+#define DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE 1\n+#define DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE 2\n+#define dwc_param_otg_cap_default DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE\n+\n+extern int dwc_otg_set_param_opt(dwc_otg_core_if_t * core_if, int32_t val);\n+extern int32_t dwc_otg_get_param_opt(dwc_otg_core_if_t * core_if);\n+#define dwc_param_opt_default 1\n+\n+/**\n+ * Specifies whether to use slave or DMA mode for accessing the data\n+ * FIFOs. The driver will automatically detect the value for this\n+ * parameter if none is specified.\n+ * 0 - Slave\n+ * 1 - DMA (default, if available)\n+ */\n+extern int dwc_otg_set_param_dma_enable(dwc_otg_core_if_t * core_if,\n+\t\t\t\t\tint32_t val);\n+extern int32_t dwc_otg_get_param_dma_enable(dwc_otg_core_if_t * core_if);\n+#define dwc_param_dma_enable_default 1\n+\n+/**\n+ * When DMA mode is enabled specifies whether to use\n+ * address DMA or DMA Descritor mode for accessing the data\n+ * FIFOs in device mode. The driver will automatically detect\n+ * the value for this parameter if none is specified.\n+ * 0 - address DMA\n+ * 1 - DMA Descriptor(default, if available)\n+ */\n+extern int dwc_otg_set_param_dma_desc_enable(dwc_otg_core_if_t * core_if,\n+\t\t\t\t\t     int32_t val);\n+extern int32_t dwc_otg_get_param_dma_desc_enable(dwc_otg_core_if_t * core_if);\n+//#define dwc_param_dma_desc_enable_default 1\n+#define dwc_param_dma_desc_enable_default 0 // Broadcom BCM2708\n+\n+/** The DMA Burst size (applicable only for External DMA\n+ * Mode). 1, 4, 8 16, 32, 64, 128, 256 (default 32)\n+ */\n+extern int dwc_otg_set_param_dma_burst_size(dwc_otg_core_if_t * core_if,\n+\t\t\t\t\t    int32_t val);\n+extern int32_t dwc_otg_get_param_dma_burst_size(dwc_otg_core_if_t * core_if);\n+#define dwc_param_dma_burst_size_default 32\n+\n+/**\n+ * Specifies the maximum speed of operation in host and device mode.\n+ * The actual speed depends on the speed of the attached device and\n+ * the value of phy_type. The actual speed depends on the speed of the\n+ * attached device.\n+ * 0 - High Speed (default)\n+ * 1 - Full Speed\n+ */\n+extern int dwc_otg_set_param_speed(dwc_otg_core_if_t * core_if, int32_t val);\n+extern int32_t dwc_otg_get_param_speed(dwc_otg_core_if_t * core_if);\n+#define dwc_param_speed_default 0\n+#define DWC_SPEED_PARAM_HIGH 0\n+#define DWC_SPEED_PARAM_FULL 1\n+\n+/** Specifies whether low power mode is supported when attached\n+ *\tto a Full Speed or Low Speed device in host mode.\n+ * 0 - Don't support low power mode (default)\n+ * 1 - Support low power mode\n+ */\n+extern int dwc_otg_set_param_host_support_fs_ls_low_power(dwc_otg_core_if_t *\n+\t\t\t\t\t\t\t  core_if, int32_t val);\n+extern int32_t dwc_otg_get_param_host_support_fs_ls_low_power(dwc_otg_core_if_t\n+\t\t\t\t\t\t\t      * core_if);\n+#define dwc_param_host_support_fs_ls_low_power_default 0\n+\n+/** Specifies the PHY clock rate in low power mode when connected to a\n+ * Low Speed device in host mode. This parameter is applicable only if\n+ * HOST_SUPPORT_FS_LS_LOW_POWER is enabled. If PHY_TYPE is set to FS\n+ * then defaults to 6 MHZ otherwise 48 MHZ.\n+ *\n+ * 0 - 48 MHz\n+ * 1 - 6 MHz\n+ */\n+extern int dwc_otg_set_param_host_ls_low_power_phy_clk(dwc_otg_core_if_t *\n+\t\t\t\t\t\t       core_if, int32_t val);\n+extern int32_t dwc_otg_get_param_host_ls_low_power_phy_clk(dwc_otg_core_if_t *\n+\t\t\t\t\t\t\t   core_if);\n+#define dwc_param_host_ls_low_power_phy_clk_default 0\n+#define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ 0\n+#define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ 1\n+\n+/**\n+ * 0 - Use cC FIFO size parameters\n+ * 1 - Allow dynamic FIFO sizing (default)\n+ */\n+extern int dwc_otg_set_param_enable_dynamic_fifo(dwc_otg_core_if_t * core_if,\n+\t\t\t\t\t\t int32_t val);\n+extern int32_t dwc_otg_get_param_enable_dynamic_fifo(dwc_otg_core_if_t *\n+\t\t\t\t\t\t     core_if);\n+#define dwc_param_enable_dynamic_fifo_default 1\n+\n+/** Total number of 4-byte words in the data FIFO memory. This\n+ * memory includes the Rx FIFO, non-periodic Tx FIFO, and periodic\n+ * Tx FIFOs.\n+ * 32 to 32768 (default 8192)\n+ * Note: The total FIFO memory depth in the FPGA configuration is 8192.\n+ */\n+extern int dwc_otg_set_param_data_fifo_size(dwc_otg_core_if_t * core_if,\n+\t\t\t\t\t    int32_t val);\n+extern int32_t dwc_otg_get_param_data_fifo_size(dwc_otg_core_if_t * core_if);\n+//#define dwc_param_data_fifo_size_default 8192\n+#define dwc_param_data_fifo_size_default 0xFF0 // Broadcom BCM2708\n+\n+/** Number of 4-byte words in the Rx FIFO in device mode when dynamic\n+ * FIFO sizing is enabled.\n+ * 16 to 32768 (default 1064)\n+ */\n+extern int dwc_otg_set_param_dev_rx_fifo_size(dwc_otg_core_if_t * core_if,\n+\t\t\t\t\t      int32_t val);\n+extern int32_t dwc_otg_get_param_dev_rx_fifo_size(dwc_otg_core_if_t * core_if);\n+#define dwc_param_dev_rx_fifo_size_default 1064\n+\n+/** Number of 4-byte words in the non-periodic Tx FIFO in device mode\n+ * when dynamic FIFO sizing is enabled.\n+ * 16 to 32768 (default 1024)\n+ */\n+extern int dwc_otg_set_param_dev_nperio_tx_fifo_size(dwc_otg_core_if_t *\n+\t\t\t\t\t\t     core_if, int32_t val);\n+extern int32_t dwc_otg_get_param_dev_nperio_tx_fifo_size(dwc_otg_core_if_t *\n+\t\t\t\t\t\t\t core_if);\n+#define dwc_param_dev_nperio_tx_fifo_size_default 1024\n+\n+/** Number of 4-byte words in each of the periodic Tx FIFOs in device\n+ * mode when dynamic FIFO sizing is enabled.\n+ * 4 to 768 (default 256)\n+ */\n+extern int dwc_otg_set_param_dev_perio_tx_fifo_size(dwc_otg_core_if_t * core_if,\n+\t\t\t\t\t\t    int32_t val, int fifo_num);\n+extern int32_t dwc_otg_get_param_dev_perio_tx_fifo_size(dwc_otg_core_if_t *\n+\t\t\t\t\t\t\tcore_if, int fifo_num);\n+#define dwc_param_dev_perio_tx_fifo_size_default 256\n+\n+/** Number of 4-byte words in the Rx FIFO in host mode when dynamic\n+ * FIFO sizing is enabled.\n+ * 16 to 32768 (default 1024)\n+ */\n+extern int dwc_otg_set_param_host_rx_fifo_size(dwc_otg_core_if_t * core_if,\n+\t\t\t\t\t       int32_t val);\n+extern int32_t dwc_otg_get_param_host_rx_fifo_size(dwc_otg_core_if_t * core_if);\n+//#define dwc_param_host_rx_fifo_size_default 1024\n+#define dwc_param_host_rx_fifo_size_default 774 // Broadcom BCM2708\n+\n+/** Number of 4-byte words in the non-periodic Tx FIFO in host mode\n+ * when Dynamic FIFO sizing is enabled in the core.\n+ * 16 to 32768 (default 1024)\n+ */\n+extern int dwc_otg_set_param_host_nperio_tx_fifo_size(dwc_otg_core_if_t *\n+\t\t\t\t\t\t      core_if, int32_t val);\n+extern int32_t dwc_otg_get_param_host_nperio_tx_fifo_size(dwc_otg_core_if_t *\n+\t\t\t\t\t\t\t  core_if);\n+//#define dwc_param_host_nperio_tx_fifo_size_default 1024\n+#define dwc_param_host_nperio_tx_fifo_size_default 0x100 // Broadcom BCM2708\n+\n+/** Number of 4-byte words in the host periodic Tx FIFO when dynamic\n+ * FIFO sizing is enabled.\n+ * 16 to 32768 (default 1024)\n+ */\n+extern int dwc_otg_set_param_host_perio_tx_fifo_size(dwc_otg_core_if_t *\n+\t\t\t\t\t\t     core_if, int32_t val);\n+extern int32_t dwc_otg_get_param_host_perio_tx_fifo_size(dwc_otg_core_if_t *\n+\t\t\t\t\t\t\t core_if);\n+//#define dwc_param_host_perio_tx_fifo_size_default 1024\n+#define dwc_param_host_perio_tx_fifo_size_default 0x200 // Broadcom BCM2708\n+\n+/** The maximum transfer size supported in bytes.\n+ * 2047 to 65,535  (default 65,535)\n+ */\n+extern int dwc_otg_set_param_max_transfer_size(dwc_otg_core_if_t * core_if,\n+\t\t\t\t\t       int32_t val);\n+extern int32_t dwc_otg_get_param_max_transfer_size(dwc_otg_core_if_t * core_if);\n+#define dwc_param_max_transfer_size_default 65535\n+\n+/** The maximum number of packets in a transfer.\n+ * 15 to 511  (default 511)\n+ */\n+extern int dwc_otg_set_param_max_packet_count(dwc_otg_core_if_t * core_if,\n+\t\t\t\t\t      int32_t val);\n+extern int32_t dwc_otg_get_param_max_packet_count(dwc_otg_core_if_t * core_if);\n+#define dwc_param_max_packet_count_default 511\n+\n+/** The number of host channel registers to use.\n+ * 1 to 16 (default 12)\n+ * Note: The FPGA configuration supports a maximum of 12 host channels.\n+ */\n+extern int dwc_otg_set_param_host_channels(dwc_otg_core_if_t * core_if,\n+\t\t\t\t\t   int32_t val);\n+extern int32_t dwc_otg_get_param_host_channels(dwc_otg_core_if_t * core_if);\n+//#define dwc_param_host_channels_default 12\n+#define dwc_param_host_channels_default 8 // Broadcom BCM2708\n+\n+/** The number of endpoints in addition to EP0 available for device\n+ * mode operations.\n+ * 1 to 15 (default 6 IN and OUT)\n+ * Note: The FPGA configuration supports a maximum of 6 IN and OUT\n+ * endpoints in addition to EP0.\n+ */\n+extern int dwc_otg_set_param_dev_endpoints(dwc_otg_core_if_t * core_if,\n+\t\t\t\t\t   int32_t val);\n+extern int32_t dwc_otg_get_param_dev_endpoints(dwc_otg_core_if_t * core_if);\n+#define dwc_param_dev_endpoints_default 6\n+\n+/**\n+ * Specifies the type of PHY interface to use. By default, the driver\n+ * will automatically detect the phy_type.\n+ *\n+ * 0 - Full Speed PHY\n+ * 1 - UTMI+ (default)\n+ * 2 - ULPI\n+ */\n+extern int dwc_otg_set_param_phy_type(dwc_otg_core_if_t * core_if, int32_t val);\n+extern int32_t dwc_otg_get_param_phy_type(dwc_otg_core_if_t * core_if);\n+#define DWC_PHY_TYPE_PARAM_FS 0\n+#define DWC_PHY_TYPE_PARAM_UTMI 1\n+#define DWC_PHY_TYPE_PARAM_ULPI 2\n+#define dwc_param_phy_type_default DWC_PHY_TYPE_PARAM_UTMI\n+\n+/**\n+ * Specifies the UTMI+ Data Width. This parameter is\n+ * applicable for a PHY_TYPE of UTMI+ or ULPI. (For a ULPI\n+ * PHY_TYPE, this parameter indicates the data width between\n+ * the MAC and the ULPI Wrapper.) Also, this parameter is\n+ * applicable only if the OTG_HSPHY_WIDTH cC parameter was set\n+ * to \"8 and 16 bits\", meaning that the core has been\n+ * configured to work at either data path width.\n+ *\n+ * 8 or 16 bits (default 16)\n+ */\n+extern int dwc_otg_set_param_phy_utmi_width(dwc_otg_core_if_t * core_if,\n+\t\t\t\t\t    int32_t val);\n+extern int32_t dwc_otg_get_param_phy_utmi_width(dwc_otg_core_if_t * core_if);\n+//#define dwc_param_phy_utmi_width_default 16\n+#define dwc_param_phy_utmi_width_default 8 // Broadcom BCM2708\n+\n+/**\n+ * Specifies whether the ULPI operates at double or single\n+ * data rate. This parameter is only applicable if PHY_TYPE is\n+ * ULPI.\n+ *\n+ * 0 - single data rate ULPI interface with 8 bit wide data\n+ * bus (default)\n+ * 1 - double data rate ULPI interface with 4 bit wide data\n+ * bus\n+ */\n+extern int dwc_otg_set_param_phy_ulpi_ddr(dwc_otg_core_if_t * core_if,\n+\t\t\t\t\t  int32_t val);\n+extern int32_t dwc_otg_get_param_phy_ulpi_ddr(dwc_otg_core_if_t * core_if);\n+#define dwc_param_phy_ulpi_ddr_default 0\n+\n+/**\n+ * Specifies whether to use the internal or external supply to\n+ * drive the vbus with a ULPI phy.\n+ */\n+extern int dwc_otg_set_param_phy_ulpi_ext_vbus(dwc_otg_core_if_t * core_if,\n+\t\t\t\t\t       int32_t val);\n+extern int32_t dwc_otg_get_param_phy_ulpi_ext_vbus(dwc_otg_core_if_t * core_if);\n+#define DWC_PHY_ULPI_INTERNAL_VBUS 0\n+#define DWC_PHY_ULPI_EXTERNAL_VBUS 1\n+#define dwc_param_phy_ulpi_ext_vbus_default DWC_PHY_ULPI_INTERNAL_VBUS\n+\n+/**\n+ * Specifies whether to use the I2Cinterface for full speed PHY. This\n+ * parameter is only applicable if PHY_TYPE is FS.\n+ * 0 - No (default)\n+ * 1 - Yes\n+ */\n+extern int dwc_otg_set_param_i2c_enable(dwc_otg_core_if_t * core_if,\n+\t\t\t\t\tint32_t val);\n+extern int32_t dwc_otg_get_param_i2c_enable(dwc_otg_core_if_t * core_if);\n+#define dwc_param_i2c_enable_default 0\n+\n+extern int dwc_otg_set_param_ulpi_fs_ls(dwc_otg_core_if_t * core_if,\n+\t\t\t\t\tint32_t val);\n+extern int32_t dwc_otg_get_param_ulpi_fs_ls(dwc_otg_core_if_t * core_if);\n+#define dwc_param_ulpi_fs_ls_default 0\n+\n+extern int dwc_otg_set_param_ts_dline(dwc_otg_core_if_t * core_if, int32_t val);\n+extern int32_t dwc_otg_get_param_ts_dline(dwc_otg_core_if_t * core_if);\n+#define dwc_param_ts_dline_default 0\n+\n+/**\n+ * Specifies whether dedicated transmit FIFOs are\n+ * enabled for non periodic IN endpoints in device mode\n+ * 0 - No\n+ * 1 - Yes\n+ */\n+extern int dwc_otg_set_param_en_multiple_tx_fifo(dwc_otg_core_if_t * core_if,\n+\t\t\t\t\t\t int32_t val);\n+extern int32_t dwc_otg_get_param_en_multiple_tx_fifo(dwc_otg_core_if_t *\n+\t\t\t\t\t\t     core_if);\n+#define dwc_param_en_multiple_tx_fifo_default 1\n+\n+/** Number of 4-byte words in each of the Tx FIFOs in device\n+ * mode when dynamic FIFO sizing is enabled.\n+ * 4 to 768 (default 256)\n+ */\n+extern int dwc_otg_set_param_dev_tx_fifo_size(dwc_otg_core_if_t * core_if,\n+\t\t\t\t\t      int fifo_num, int32_t val);\n+extern int32_t dwc_otg_get_param_dev_tx_fifo_size(dwc_otg_core_if_t * core_if,\n+\t\t\t\t\t\t  int fifo_num);\n+#define dwc_param_dev_tx_fifo_size_default 768\n+\n+/** Thresholding enable flag-\n+ * bit 0 - enable non-ISO Tx thresholding\n+ * bit 1 - enable ISO Tx thresholding\n+ * bit 2 - enable Rx thresholding\n+ */\n+extern int dwc_otg_set_param_thr_ctl(dwc_otg_core_if_t * core_if, int32_t val);\n+extern int32_t dwc_otg_get_thr_ctl(dwc_otg_core_if_t * core_if, int fifo_num);\n+#define dwc_param_thr_ctl_default 0\n+\n+/** Thresholding length for Tx\n+ * FIFOs in 32 bit DWORDs\n+ */\n+extern int dwc_otg_set_param_tx_thr_length(dwc_otg_core_if_t * core_if,\n+\t\t\t\t\t   int32_t val);\n+extern int32_t dwc_otg_get_tx_thr_length(dwc_otg_core_if_t * core_if);\n+#define dwc_param_tx_thr_length_default 64\n+\n+/** Thresholding length for Rx\n+ *\tFIFOs in 32 bit DWORDs\n+ */\n+extern int dwc_otg_set_param_rx_thr_length(dwc_otg_core_if_t * core_if,\n+\t\t\t\t\t   int32_t val);\n+extern int32_t dwc_otg_get_rx_thr_length(dwc_otg_core_if_t * core_if);\n+#define dwc_param_rx_thr_length_default 64\n+\n+/**\n+ * Specifies whether LPM (Link Power Management) support is enabled\n+ */\n+extern int dwc_otg_set_param_lpm_enable(dwc_otg_core_if_t * core_if,\n+\t\t\t\t\tint32_t val);\n+extern int32_t dwc_otg_get_param_lpm_enable(dwc_otg_core_if_t * core_if);\n+#define dwc_param_lpm_enable_default 1\n+\n+/**\n+ * Specifies whether PTI enhancement is enabled\n+ */\n+extern int dwc_otg_set_param_pti_enable(dwc_otg_core_if_t * core_if,\n+\t\t\t\t\tint32_t val);\n+extern int32_t dwc_otg_get_param_pti_enable(dwc_otg_core_if_t * core_if);\n+#define dwc_param_pti_enable_default 0\n+\n+/**\n+ * Specifies whether MPI enhancement is enabled\n+ */\n+extern int dwc_otg_set_param_mpi_enable(dwc_otg_core_if_t * core_if,\n+\t\t\t\t\tint32_t val);\n+extern int32_t dwc_otg_get_param_mpi_enable(dwc_otg_core_if_t * core_if);\n+#define dwc_param_mpi_enable_default 0\n+\n+/**\n+ * Specifies whether ADP capability is enabled\n+ */\n+extern int dwc_otg_set_param_adp_enable(dwc_otg_core_if_t * core_if,\n+\t\t\t\t\tint32_t val);\n+extern int32_t dwc_otg_get_param_adp_enable(dwc_otg_core_if_t * core_if);\n+#define dwc_param_adp_enable_default 0\n+\n+/**\n+ * Specifies whether IC_USB capability is enabled\n+ */\n+\n+extern int dwc_otg_set_param_ic_usb_cap(dwc_otg_core_if_t * core_if,\n+\t\t\t\t\tint32_t val);\n+extern int32_t dwc_otg_get_param_ic_usb_cap(dwc_otg_core_if_t * core_if);\n+#define dwc_param_ic_usb_cap_default 0\n+\n+extern int dwc_otg_set_param_ahb_thr_ratio(dwc_otg_core_if_t * core_if,\n+\t\t\t\t\t   int32_t val);\n+extern int32_t dwc_otg_get_param_ahb_thr_ratio(dwc_otg_core_if_t * core_if);\n+#define dwc_param_ahb_thr_ratio_default 0\n+\n+extern int dwc_otg_set_param_power_down(dwc_otg_core_if_t * core_if,\n+\t\t\t\t\tint32_t val);\n+extern int32_t dwc_otg_get_param_power_down(dwc_otg_core_if_t * core_if);\n+#define dwc_param_power_down_default 0\n+\n+extern int dwc_otg_set_param_reload_ctl(dwc_otg_core_if_t * core_if,\n+\t\t\t\t\tint32_t val);\n+extern int32_t dwc_otg_get_param_reload_ctl(dwc_otg_core_if_t * core_if);\n+#define dwc_param_reload_ctl_default 0\n+\n+extern int dwc_otg_set_param_dev_out_nak(dwc_otg_core_if_t * core_if,\n+\t\t\t\t\t\t\t\t\t\tint32_t val);\n+extern int32_t dwc_otg_get_param_dev_out_nak(dwc_otg_core_if_t * core_if);\n+#define dwc_param_dev_out_nak_default 0\n+\n+extern int dwc_otg_set_param_cont_on_bna(dwc_otg_core_if_t * core_if,\n+\t\t\t\t\t\t\t\t\t\t int32_t val);\n+extern int32_t dwc_otg_get_param_cont_on_bna(dwc_otg_core_if_t * core_if);\n+#define dwc_param_cont_on_bna_default 0\n+\n+extern int dwc_otg_set_param_ahb_single(dwc_otg_core_if_t * core_if,\n+\t\t\t\t\t\t\t\t\t\t int32_t val);\n+extern int32_t dwc_otg_get_param_ahb_single(dwc_otg_core_if_t * core_if);\n+#define dwc_param_ahb_single_default 0\n+\n+extern int dwc_otg_set_param_otg_ver(dwc_otg_core_if_t * core_if, int32_t val);\n+extern int32_t dwc_otg_get_param_otg_ver(dwc_otg_core_if_t * core_if);\n+#define dwc_param_otg_ver_default 0\n+\n+/** @} */\n+\n+/** @name Access to registers and bit-fields */\n+\n+/**\n+ * Dump core registers and SPRAM\n+ */\n+extern void dwc_otg_dump_dev_registers(dwc_otg_core_if_t * _core_if);\n+extern void dwc_otg_dump_spram(dwc_otg_core_if_t * _core_if);\n+extern void dwc_otg_dump_host_registers(dwc_otg_core_if_t * _core_if);\n+extern void dwc_otg_dump_global_registers(dwc_otg_core_if_t * _core_if);\n+\n+/**\n+ * Get host negotiation status.\n+ */\n+extern uint32_t dwc_otg_get_hnpstatus(dwc_otg_core_if_t * core_if);\n+\n+/**\n+ * Get srp status\n+ */\n+extern uint32_t dwc_otg_get_srpstatus(dwc_otg_core_if_t * core_if);\n+\n+/**\n+ * Set hnpreq bit in the GOTGCTL register.\n+ */\n+extern void dwc_otg_set_hnpreq(dwc_otg_core_if_t * core_if, uint32_t val);\n+\n+/**\n+ * Get Content of SNPSID register.\n+ */\n+extern uint32_t dwc_otg_get_gsnpsid(dwc_otg_core_if_t * core_if);\n+\n+/**\n+ * Get current mode.\n+ * Returns 0 if in device mode, and 1 if in host mode.\n+ */\n+extern uint32_t dwc_otg_get_mode(dwc_otg_core_if_t * core_if);\n+\n+/**\n+ * Get value of hnpcapable field in the GUSBCFG register\n+ */\n+extern uint32_t dwc_otg_get_hnpcapable(dwc_otg_core_if_t * core_if);\n+/**\n+ * Set value of hnpcapable field in the GUSBCFG register\n+ */\n+extern void dwc_otg_set_hnpcapable(dwc_otg_core_if_t * core_if, uint32_t val);\n+\n+/**\n+ * Get value of srpcapable field in the GUSBCFG register\n+ */\n+extern uint32_t dwc_otg_get_srpcapable(dwc_otg_core_if_t * core_if);\n+/**\n+ * Set value of srpcapable field in the GUSBCFG register\n+ */\n+extern void dwc_otg_set_srpcapable(dwc_otg_core_if_t * core_if, uint32_t val);\n+\n+/**\n+ * Get value of devspeed field in the DCFG register\n+ */\n+extern uint32_t dwc_otg_get_devspeed(dwc_otg_core_if_t * core_if);\n+/**\n+ * Set value of devspeed field in the DCFG register\n+ */\n+extern void dwc_otg_set_devspeed(dwc_otg_core_if_t * core_if, uint32_t val);\n+\n+/**\n+ * Get the value of busconnected field from the HPRT0 register\n+ */\n+extern uint32_t dwc_otg_get_busconnected(dwc_otg_core_if_t * core_if);\n+\n+/**\n+ * Gets the device enumeration Speed.\n+ */\n+extern uint32_t dwc_otg_get_enumspeed(dwc_otg_core_if_t * core_if);\n+\n+/**\n+ * Get value of prtpwr field from the HPRT0 register\n+ */\n+extern uint32_t dwc_otg_get_prtpower(dwc_otg_core_if_t * core_if);\n+\n+/**\n+ * Get value of flag indicating core state - hibernated or not\n+ */\n+extern uint32_t dwc_otg_get_core_state(dwc_otg_core_if_t * core_if);\n+\n+/**\n+ * Set value of prtpwr field from the HPRT0 register\n+ */\n+extern void dwc_otg_set_prtpower(dwc_otg_core_if_t * core_if, uint32_t val);\n+\n+/**\n+ * Get value of prtsusp field from the HPRT0 regsiter\n+ */\n+extern uint32_t dwc_otg_get_prtsuspend(dwc_otg_core_if_t * core_if);\n+/**\n+ * Set value of prtpwr field from the HPRT0 register\n+ */\n+extern void dwc_otg_set_prtsuspend(dwc_otg_core_if_t * core_if, uint32_t val);\n+\n+/**\n+ * Get value of ModeChTimEn field from the HCFG regsiter\n+ */\n+extern uint32_t dwc_otg_get_mode_ch_tim(dwc_otg_core_if_t * core_if);\n+/**\n+ * Set value of ModeChTimEn field from the HCFG regsiter\n+ */\n+extern void dwc_otg_set_mode_ch_tim(dwc_otg_core_if_t * core_if, uint32_t val);\n+\n+/**\n+ * Get value of Fram Interval field from the HFIR regsiter\n+ */\n+extern uint32_t dwc_otg_get_fr_interval(dwc_otg_core_if_t * core_if);\n+/**\n+ * Set value of Frame Interval field from the HFIR regsiter\n+ */\n+extern void dwc_otg_set_fr_interval(dwc_otg_core_if_t * core_if, uint32_t val);\n+\n+/**\n+ * Set value of prtres field from the HPRT0 register\n+ *FIXME Remove?\n+ */\n+extern void dwc_otg_set_prtresume(dwc_otg_core_if_t * core_if, uint32_t val);\n+\n+/**\n+ * Get value of rmtwkupsig bit in DCTL register\n+ */\n+extern uint32_t dwc_otg_get_remotewakesig(dwc_otg_core_if_t * core_if);\n+\n+/**\n+ * Get value of prt_sleep_sts field from the GLPMCFG register\n+ */\n+extern uint32_t dwc_otg_get_lpm_portsleepstatus(dwc_otg_core_if_t * core_if);\n+\n+/**\n+ * Get value of rem_wkup_en field from the GLPMCFG register\n+ */\n+extern uint32_t dwc_otg_get_lpm_remotewakeenabled(dwc_otg_core_if_t * core_if);\n+\n+/**\n+ * Get value of appl_resp field from the GLPMCFG register\n+ */\n+extern uint32_t dwc_otg_get_lpmresponse(dwc_otg_core_if_t * core_if);\n+/**\n+ * Set value of appl_resp field from the GLPMCFG register\n+ */\n+extern void dwc_otg_set_lpmresponse(dwc_otg_core_if_t * core_if, uint32_t val);\n+\n+/**\n+ * Get value of hsic_connect field from the GLPMCFG register\n+ */\n+extern uint32_t dwc_otg_get_hsic_connect(dwc_otg_core_if_t * core_if);\n+/**\n+ * Set value of hsic_connect field from the GLPMCFG register\n+ */\n+extern void dwc_otg_set_hsic_connect(dwc_otg_core_if_t * core_if, uint32_t val);\n+\n+/**\n+ * Get value of inv_sel_hsic field from the GLPMCFG register.\n+ */\n+extern uint32_t dwc_otg_get_inv_sel_hsic(dwc_otg_core_if_t * core_if);\n+/**\n+ * Set value of inv_sel_hsic field from the GLPMFG register.\n+ */\n+extern void dwc_otg_set_inv_sel_hsic(dwc_otg_core_if_t * core_if, uint32_t val);\n+\n+/*\n+ * Some functions for accessing registers\n+ */\n+\n+/**\n+ *  GOTGCTL register\n+ */\n+extern uint32_t dwc_otg_get_gotgctl(dwc_otg_core_if_t * core_if);\n+extern void dwc_otg_set_gotgctl(dwc_otg_core_if_t * core_if, uint32_t val);\n+\n+/**\n+ * GUSBCFG register\n+ */\n+extern uint32_t dwc_otg_get_gusbcfg(dwc_otg_core_if_t * core_if);\n+extern void dwc_otg_set_gusbcfg(dwc_otg_core_if_t * core_if, uint32_t val);\n+\n+/**\n+ * GRXFSIZ register\n+ */\n+extern uint32_t dwc_otg_get_grxfsiz(dwc_otg_core_if_t * core_if);\n+extern void dwc_otg_set_grxfsiz(dwc_otg_core_if_t * core_if, uint32_t val);\n+\n+/**\n+ * GNPTXFSIZ register\n+ */\n+extern uint32_t dwc_otg_get_gnptxfsiz(dwc_otg_core_if_t * core_if);\n+extern void dwc_otg_set_gnptxfsiz(dwc_otg_core_if_t * core_if, uint32_t val);\n+\n+extern uint32_t dwc_otg_get_gpvndctl(dwc_otg_core_if_t * core_if);\n+extern void dwc_otg_set_gpvndctl(dwc_otg_core_if_t * core_if, uint32_t val);\n+\n+/**\n+ * GGPIO register\n+ */\n+extern uint32_t dwc_otg_get_ggpio(dwc_otg_core_if_t * core_if);\n+extern void dwc_otg_set_ggpio(dwc_otg_core_if_t * core_if, uint32_t val);\n+\n+/**\n+ * GUID register\n+ */\n+extern uint32_t dwc_otg_get_guid(dwc_otg_core_if_t * core_if);\n+extern void dwc_otg_set_guid(dwc_otg_core_if_t * core_if, uint32_t val);\n+\n+/**\n+ * HPRT0 register\n+ */\n+extern uint32_t dwc_otg_get_hprt0(dwc_otg_core_if_t * core_if);\n+extern void dwc_otg_set_hprt0(dwc_otg_core_if_t * core_if, uint32_t val);\n+\n+/**\n+ * GHPTXFSIZE\n+ */\n+extern uint32_t dwc_otg_get_hptxfsiz(dwc_otg_core_if_t * core_if);\n+\n+/** @} */\n+\n+#endif\t\t\t\t/* __DWC_CORE_IF_H__ */\n--- /dev/null\n+++ b/drivers/usb/host/dwc_otg/dwc_otg_dbg.h\n@@ -0,0 +1,117 @@\n+/* ==========================================================================\n+ *\n+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,\n+ * \"Software\") is an Unsupported proprietary work of Synopsys, Inc. unless\n+ * otherwise expressly agreed to in writing between Synopsys and you.\n+ *\n+ * The Software IS NOT an item of Licensed Software or Licensed Product under\n+ * any End User Software License Agreement or Agreement for Licensed Product\n+ * with Synopsys or any supplement thereto. You are permitted to use and\n+ * redistribute this Software in source and binary forms, with or without\n+ * modification, provided that redistributions of source code must retain this\n+ * notice. You may not view, use, disclose, copy or distribute this file or\n+ * any information contained herein except pursuant to this license grant from\n+ * Synopsys. If you do not agree with this notice, including the disclaimer\n+ * below, then you are not authorized to use the Software.\n+ *\n+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN \"AS IS\" BASIS\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,\n+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH\n+ * DAMAGE.\n+ * ========================================================================== */\n+\n+#ifndef __DWC_OTG_DBG_H__\n+#define __DWC_OTG_DBG_H__\n+\n+/** @file\n+ * This file defines debug levels.\n+ * Debugging support vanishes in non-debug builds.\n+ */\n+\n+/**\n+ * The Debug Level bit-mask variable.\n+ */\n+extern uint32_t g_dbg_lvl;\n+/**\n+ * Set the Debug Level variable.\n+ */\n+static inline uint32_t SET_DEBUG_LEVEL(const uint32_t new)\n+{\n+\tuint32_t old = g_dbg_lvl;\n+\tg_dbg_lvl = new;\n+\treturn old;\n+}\n+\n+#define DBG_USER\t(0x1)\n+/** When debug level has the DBG_CIL bit set, display CIL Debug messages. */\n+#define DBG_CIL\t\t(0x2)\n+/** When debug level has the DBG_CILV bit set, display CIL Verbose debug\n+ * messages */\n+#define DBG_CILV\t(0x20)\n+/**  When debug level has the DBG_PCD bit set, display PCD (Device) debug\n+ *  messages */\n+#define DBG_PCD\t\t(0x4)\n+/** When debug level has the DBG_PCDV set, display PCD (Device) Verbose debug\n+ * messages */\n+#define DBG_PCDV\t(0x40)\n+/** When debug level has the DBG_HCD bit set, display Host debug messages */\n+#define DBG_HCD\t\t(0x8)\n+/** When debug level has the DBG_HCDV bit set, display Verbose Host debug\n+ * messages */\n+#define DBG_HCDV\t(0x80)\n+/** When debug level has the DBG_HCD_URB bit set, display enqueued URBs in host\n+ *  mode. */\n+#define DBG_HCD_URB\t(0x800)\n+/** When debug level has the DBG_HCDI bit set, display host interrupt\n+ *  messages. */\n+#define DBG_HCDI\t(0x1000)\n+\n+/** When debug level has any bit set, display debug messages */\n+#define DBG_ANY\t\t(0xFF)\n+\n+/** All debug messages off */\n+#define DBG_OFF\t\t0\n+\n+/** Prefix string for DWC_DEBUG print macros. */\n+#define USB_DWC \"DWC_otg: \"\n+\n+/**\n+ * Print a debug message when the Global debug level variable contains\n+ * the bit defined in <code>lvl</code>.\n+ *\n+ * @param[in] lvl - Debug level, use one of the DBG_ constants above.\n+ * @param[in] x - like printf\n+ *\n+ *    Example:<p>\n+ * <code>\n+ *      DWC_DEBUGPL( DBG_ANY, \"%s(%p)\\n\", __func__, _reg_base_addr);\n+ * </code>\n+ * <br>\n+ * results in:<br>\n+ * <code>\n+ * usb-DWC_otg: dwc_otg_cil_init(ca867000)\n+ * </code>\n+ */\n+#ifdef DEBUG\n+\n+# define DWC_DEBUGPL(lvl, x...) do{ if ((lvl)&g_dbg_lvl)__DWC_DEBUG(USB_DWC x ); }while(0)\n+# define DWC_DEBUGP(x...)\tDWC_DEBUGPL(DBG_ANY, x )\n+\n+# define CHK_DEBUG_LEVEL(level) ((level) & g_dbg_lvl)\n+\n+#else\n+\n+# define DWC_DEBUGPL(lvl, x...) do{}while(0)\n+# define DWC_DEBUGP(x...)\n+\n+# define CHK_DEBUG_LEVEL(level) (0)\n+\n+#endif /*DEBUG*/\n+#endif\n--- /dev/null\n+++ b/drivers/usb/host/dwc_otg/dwc_otg_driver.c\n@@ -0,0 +1,1772 @@\n+/* ==========================================================================\n+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_driver.c $\n+ * $Revision: #92 $\n+ * $Date: 2012/08/10 $\n+ * $Change: 2047372 $\n+ *\n+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,\n+ * \"Software\") is an Unsupported proprietary work of Synopsys, Inc. unless\n+ * otherwise expressly agreed to in writing between Synopsys and you.\n+ *\n+ * The Software IS NOT an item of Licensed Software or Licensed Product under\n+ * any End User Software License Agreement or Agreement for Licensed Product\n+ * with Synopsys or any supplement thereto. You are permitted to use and\n+ * redistribute this Software in source and binary forms, with or without\n+ * modification, provided that redistributions of source code must retain this\n+ * notice. You may not view, use, disclose, copy or distribute this file or\n+ * any information contained herein except pursuant to this license grant from\n+ * Synopsys. If you do not agree with this notice, including the disclaimer\n+ * below, then you are not authorized to use the Software.\n+ *\n+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN \"AS IS\" BASIS\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,\n+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH\n+ * DAMAGE.\n+ * ========================================================================== */\n+\n+/** @file\n+ * The dwc_otg_driver module provides the initialization and cleanup entry\n+ * points for the DWC_otg driver. This module will be dynamically installed\n+ * after Linux is booted using the insmod command. When the module is\n+ * installed, the dwc_otg_driver_init function is called. When the module is\n+ * removed (using rmmod), the dwc_otg_driver_cleanup function is called.\n+ *\n+ * This module also defines a data structure for the dwc_otg_driver, which is\n+ * used in conjunction with the standard ARM lm_device structure. These\n+ * structures allow the OTG driver to comply with the standard Linux driver\n+ * model in which devices and drivers are registered with a bus driver. This\n+ * has the benefit that Linux can expose attributes of the driver and device\n+ * in its special sysfs file system. Users can then read or write files in\n+ * this file system to perform diagnostics on the driver components or the\n+ * device.\n+ */\n+\n+#include \"dwc_otg_os_dep.h\"\n+#include \"dwc_os.h\"\n+#include \"dwc_otg_dbg.h\"\n+#include \"dwc_otg_driver.h\"\n+#include \"dwc_otg_attr.h\"\n+#include \"dwc_otg_core_if.h\"\n+#include \"dwc_otg_pcd_if.h\"\n+#include \"dwc_otg_hcd_if.h\"\n+#include \"dwc_otg_fiq_fsm.h\"\n+\n+#define DWC_DRIVER_VERSION\t\"3.00a 10-AUG-2012\"\n+#define DWC_DRIVER_DESC\t\t\"HS OTG USB Controller driver\"\n+\n+bool microframe_schedule=true;\n+\n+static const char dwc_driver_name[] = \"dwc_otg\";\n+\n+\n+extern int pcd_init(\n+#ifdef LM_INTERFACE\n+\t\t\t   struct lm_device *_dev\n+#elif  defined(PCI_INTERFACE)\n+\t\t\t   struct pci_dev *_dev\n+#elif  defined(PLATFORM_INTERFACE)\n+\tstruct platform_device *dev\n+#endif\n+    );\n+extern int hcd_init(\n+#ifdef LM_INTERFACE\n+\t\t\t   struct lm_device *_dev\n+#elif  defined(PCI_INTERFACE)\n+\t\t\t   struct pci_dev *_dev\n+#elif  defined(PLATFORM_INTERFACE)\n+\tstruct platform_device *dev\n+#endif\n+    );\n+\n+extern int pcd_remove(\n+#ifdef LM_INTERFACE\n+\t\t\t     struct lm_device *_dev\n+#elif  defined(PCI_INTERFACE)\n+\t\t\t     struct pci_dev *_dev\n+#elif  defined(PLATFORM_INTERFACE)\n+\tstruct platform_device *_dev\n+#endif\n+    );\n+\n+extern void hcd_remove(\n+#ifdef LM_INTERFACE\n+\t\t\t      struct lm_device *_dev\n+#elif  defined(PCI_INTERFACE)\n+\t\t\t      struct pci_dev *_dev\n+#elif  defined(PLATFORM_INTERFACE)\n+\tstruct platform_device *_dev\n+#endif\n+    );\n+\n+extern void dwc_otg_adp_start(dwc_otg_core_if_t * core_if, uint8_t is_host);\n+\n+/*-------------------------------------------------------------------------*/\n+/* Encapsulate the module parameter settings */\n+\n+struct dwc_otg_driver_module_params {\n+\tint32_t opt;\n+\tint32_t otg_cap;\n+\tint32_t dma_enable;\n+\tint32_t dma_desc_enable;\n+\tint32_t dma_burst_size;\n+\tint32_t speed;\n+\tint32_t host_support_fs_ls_low_power;\n+\tint32_t host_ls_low_power_phy_clk;\n+\tint32_t enable_dynamic_fifo;\n+\tint32_t data_fifo_size;\n+\tint32_t dev_rx_fifo_size;\n+\tint32_t dev_nperio_tx_fifo_size;\n+\tuint32_t dev_perio_tx_fifo_size[MAX_PERIO_FIFOS];\n+\tint32_t host_rx_fifo_size;\n+\tint32_t host_nperio_tx_fifo_size;\n+\tint32_t host_perio_tx_fifo_size;\n+\tint32_t max_transfer_size;\n+\tint32_t max_packet_count;\n+\tint32_t host_channels;\n+\tint32_t dev_endpoints;\n+\tint32_t phy_type;\n+\tint32_t phy_utmi_width;\n+\tint32_t phy_ulpi_ddr;\n+\tint32_t phy_ulpi_ext_vbus;\n+\tint32_t i2c_enable;\n+\tint32_t ulpi_fs_ls;\n+\tint32_t ts_dline;\n+\tint32_t en_multiple_tx_fifo;\n+\tuint32_t dev_tx_fifo_size[MAX_TX_FIFOS];\n+\tuint32_t thr_ctl;\n+\tuint32_t tx_thr_length;\n+\tuint32_t rx_thr_length;\n+\tint32_t pti_enable;\n+\tint32_t mpi_enable;\n+\tint32_t lpm_enable;\n+\tint32_t ic_usb_cap;\n+\tint32_t ahb_thr_ratio;\n+\tint32_t power_down;\n+\tint32_t reload_ctl;\n+\tint32_t dev_out_nak;\n+\tint32_t cont_on_bna;\n+\tint32_t ahb_single;\n+\tint32_t otg_ver;\n+\tint32_t adp_enable;\n+};\n+\n+static struct dwc_otg_driver_module_params dwc_otg_module_params = {\n+\t.opt = -1,\n+\t.otg_cap = -1,\n+\t.dma_enable = -1,\n+\t.dma_desc_enable = -1,\n+\t.dma_burst_size = -1,\n+\t.speed = -1,\n+\t.host_support_fs_ls_low_power = -1,\n+\t.host_ls_low_power_phy_clk = -1,\n+\t.enable_dynamic_fifo = -1,\n+\t.data_fifo_size = -1,\n+\t.dev_rx_fifo_size = -1,\n+\t.dev_nperio_tx_fifo_size = -1,\n+\t.dev_perio_tx_fifo_size = {\n+\t\t\t\t   /* dev_perio_tx_fifo_size_1 */\n+\t\t\t\t   -1,\n+\t\t\t\t   -1,\n+\t\t\t\t   -1,\n+\t\t\t\t   -1,\n+\t\t\t\t   -1,\n+\t\t\t\t   -1,\n+\t\t\t\t   -1,\n+\t\t\t\t   -1,\n+\t\t\t\t   -1,\n+\t\t\t\t   -1,\n+\t\t\t\t   -1,\n+\t\t\t\t   -1,\n+\t\t\t\t   -1,\n+\t\t\t\t   -1,\n+\t\t\t\t   -1\n+\t\t\t\t   /* 15 */\n+\t\t\t\t   },\n+\t.host_rx_fifo_size = -1,\n+\t.host_nperio_tx_fifo_size = -1,\n+\t.host_perio_tx_fifo_size = -1,\n+\t.max_transfer_size = -1,\n+\t.max_packet_count = -1,\n+\t.host_channels = -1,\n+\t.dev_endpoints = -1,\n+\t.phy_type = -1,\n+\t.phy_utmi_width = -1,\n+\t.phy_ulpi_ddr = -1,\n+\t.phy_ulpi_ext_vbus = -1,\n+\t.i2c_enable = -1,\n+\t.ulpi_fs_ls = -1,\n+\t.ts_dline = -1,\n+\t.en_multiple_tx_fifo = -1,\n+\t.dev_tx_fifo_size = {\n+\t\t\t     /* dev_tx_fifo_size */\n+\t\t\t     -1,\n+\t\t\t     -1,\n+\t\t\t     -1,\n+\t\t\t     -1,\n+\t\t\t     -1,\n+\t\t\t     -1,\n+\t\t\t     -1,\n+\t\t\t     -1,\n+\t\t\t     -1,\n+\t\t\t     -1,\n+\t\t\t     -1,\n+\t\t\t     -1,\n+\t\t\t     -1,\n+\t\t\t     -1,\n+\t\t\t     -1\n+\t\t\t     /* 15 */\n+\t\t\t     },\n+\t.thr_ctl = -1,\n+\t.tx_thr_length = -1,\n+\t.rx_thr_length = -1,\n+\t.pti_enable = -1,\n+\t.mpi_enable = -1,\n+\t.lpm_enable = 0,\n+\t.ic_usb_cap = -1,\n+\t.ahb_thr_ratio = -1,\n+\t.power_down = -1,\n+\t.reload_ctl = -1,\n+\t.dev_out_nak = -1,\n+\t.cont_on_bna = -1,\n+\t.ahb_single = -1,\n+\t.otg_ver = -1,\n+\t.adp_enable = -1,\n+};\n+\n+//Global variable to switch the fiq fix on or off\n+bool fiq_enable = 1;\n+// Global variable to enable the split transaction fix\n+bool fiq_fsm_enable = true;\n+//Bulk split-transaction NAK holdoff in microframes\n+uint16_t nak_holdoff = 8;\n+\n+//Force host mode during CIL re-init\n+bool cil_force_host = true;\n+\n+unsigned short fiq_fsm_mask = 0x0F;\n+\n+unsigned short int_ep_interval_min = 0;\n+/**\n+ * This function shows the Driver Version.\n+ */\n+static ssize_t version_show(struct device_driver *dev, char *buf)\n+{\n+\treturn snprintf(buf, sizeof(DWC_DRIVER_VERSION) + 2, \"%s\\n\",\n+\t\t\tDWC_DRIVER_VERSION);\n+}\n+\n+static DRIVER_ATTR_RO(version);\n+\n+/**\n+ * Global Debug Level Mask.\n+ */\n+uint32_t g_dbg_lvl = 0;\t\t/* OFF */\n+\n+/**\n+ * This function shows the driver Debug Level.\n+ */\n+static ssize_t debuglevel_show(struct device_driver *drv, char *buf)\n+{\n+\treturn sprintf(buf, \"0x%0x\\n\", g_dbg_lvl);\n+}\n+\n+/**\n+ * This function stores the driver Debug Level.\n+ */\n+static ssize_t debuglevel_store(struct device_driver *drv, const char *buf,\n+\t\t\t       size_t count)\n+{\n+\tg_dbg_lvl = simple_strtoul(buf, NULL, 16);\n+\treturn count;\n+}\n+\n+static DRIVER_ATTR_RW(debuglevel);\n+\n+/**\n+ * This function is called during module intialization\n+ * to pass module parameters to the DWC_OTG CORE.\n+ */\n+static int set_parameters(dwc_otg_core_if_t * core_if)\n+{\n+\tint retval = 0;\n+\tint i;\n+\n+\tif (dwc_otg_module_params.otg_cap != -1) {\n+\t\tretval +=\n+\t\t    dwc_otg_set_param_otg_cap(core_if,\n+\t\t\t\t\t      dwc_otg_module_params.otg_cap);\n+\t}\n+\tif (dwc_otg_module_params.dma_enable != -1) {\n+\t\tretval +=\n+\t\t    dwc_otg_set_param_dma_enable(core_if,\n+\t\t\t\t\t\t dwc_otg_module_params.\n+\t\t\t\t\t\t dma_enable);\n+\t}\n+\tif (dwc_otg_module_params.dma_desc_enable != -1) {\n+\t\tretval +=\n+\t\t    dwc_otg_set_param_dma_desc_enable(core_if,\n+\t\t\t\t\t\t      dwc_otg_module_params.\n+\t\t\t\t\t\t      dma_desc_enable);\n+\t}\n+\tif (dwc_otg_module_params.opt != -1) {\n+\t\tretval +=\n+\t\t    dwc_otg_set_param_opt(core_if, dwc_otg_module_params.opt);\n+\t}\n+\tif (dwc_otg_module_params.dma_burst_size != -1) {\n+\t\tretval +=\n+\t\t    dwc_otg_set_param_dma_burst_size(core_if,\n+\t\t\t\t\t\t     dwc_otg_module_params.\n+\t\t\t\t\t\t     dma_burst_size);\n+\t}\n+\tif (dwc_otg_module_params.host_support_fs_ls_low_power != -1) {\n+\t\tretval +=\n+\t\t    dwc_otg_set_param_host_support_fs_ls_low_power(core_if,\n+\t\t\t\t\t\t\t\t   dwc_otg_module_params.\n+\t\t\t\t\t\t\t\t   host_support_fs_ls_low_power);\n+\t}\n+\tif (dwc_otg_module_params.enable_dynamic_fifo != -1) {\n+\t\tretval +=\n+\t\t    dwc_otg_set_param_enable_dynamic_fifo(core_if,\n+\t\t\t\t\t\t\t  dwc_otg_module_params.\n+\t\t\t\t\t\t\t  enable_dynamic_fifo);\n+\t}\n+\tif (dwc_otg_module_params.data_fifo_size != -1) {\n+\t\tretval +=\n+\t\t    dwc_otg_set_param_data_fifo_size(core_if,\n+\t\t\t\t\t\t     dwc_otg_module_params.\n+\t\t\t\t\t\t     data_fifo_size);\n+\t}\n+\tif (dwc_otg_module_params.dev_rx_fifo_size != -1) {\n+\t\tretval +=\n+\t\t    dwc_otg_set_param_dev_rx_fifo_size(core_if,\n+\t\t\t\t\t\t       dwc_otg_module_params.\n+\t\t\t\t\t\t       dev_rx_fifo_size);\n+\t}\n+\tif (dwc_otg_module_params.dev_nperio_tx_fifo_size != -1) {\n+\t\tretval +=\n+\t\t    dwc_otg_set_param_dev_nperio_tx_fifo_size(core_if,\n+\t\t\t\t\t\t\t      dwc_otg_module_params.\n+\t\t\t\t\t\t\t      dev_nperio_tx_fifo_size);\n+\t}\n+\tif (dwc_otg_module_params.host_rx_fifo_size != -1) {\n+\t\tretval +=\n+\t\t    dwc_otg_set_param_host_rx_fifo_size(core_if,\n+\t\t\t\t\t\t\tdwc_otg_module_params.host_rx_fifo_size);\n+\t}\n+\tif (dwc_otg_module_params.host_nperio_tx_fifo_size != -1) {\n+\t\tretval +=\n+\t\t    dwc_otg_set_param_host_nperio_tx_fifo_size(core_if,\n+\t\t\t\t\t\t\t       dwc_otg_module_params.\n+\t\t\t\t\t\t\t       host_nperio_tx_fifo_size);\n+\t}\n+\tif (dwc_otg_module_params.host_perio_tx_fifo_size != -1) {\n+\t\tretval +=\n+\t\t    dwc_otg_set_param_host_perio_tx_fifo_size(core_if,\n+\t\t\t\t\t\t\t      dwc_otg_module_params.\n+\t\t\t\t\t\t\t      host_perio_tx_fifo_size);\n+\t}\n+\tif (dwc_otg_module_params.max_transfer_size != -1) {\n+\t\tretval +=\n+\t\t    dwc_otg_set_param_max_transfer_size(core_if,\n+\t\t\t\t\t\t\tdwc_otg_module_params.\n+\t\t\t\t\t\t\tmax_transfer_size);\n+\t}\n+\tif (dwc_otg_module_params.max_packet_count != -1) {\n+\t\tretval +=\n+\t\t    dwc_otg_set_param_max_packet_count(core_if,\n+\t\t\t\t\t\t       dwc_otg_module_params.\n+\t\t\t\t\t\t       max_packet_count);\n+\t}\n+\tif (dwc_otg_module_params.host_channels != -1) {\n+\t\tretval +=\n+\t\t    dwc_otg_set_param_host_channels(core_if,\n+\t\t\t\t\t\t    dwc_otg_module_params.\n+\t\t\t\t\t\t    host_channels);\n+\t}\n+\tif (dwc_otg_module_params.dev_endpoints != -1) {\n+\t\tretval +=\n+\t\t    dwc_otg_set_param_dev_endpoints(core_if,\n+\t\t\t\t\t\t    dwc_otg_module_params.\n+\t\t\t\t\t\t    dev_endpoints);\n+\t}\n+\tif (dwc_otg_module_params.phy_type != -1) {\n+\t\tretval +=\n+\t\t    dwc_otg_set_param_phy_type(core_if,\n+\t\t\t\t\t       dwc_otg_module_params.phy_type);\n+\t}\n+\tif (dwc_otg_module_params.speed != -1) {\n+\t\tretval +=\n+\t\t    dwc_otg_set_param_speed(core_if,\n+\t\t\t\t\t    dwc_otg_module_params.speed);\n+\t}\n+\tif (dwc_otg_module_params.host_ls_low_power_phy_clk != -1) {\n+\t\tretval +=\n+\t\t    dwc_otg_set_param_host_ls_low_power_phy_clk(core_if,\n+\t\t\t\t\t\t\t\tdwc_otg_module_params.\n+\t\t\t\t\t\t\t\thost_ls_low_power_phy_clk);\n+\t}\n+\tif (dwc_otg_module_params.phy_ulpi_ddr != -1) {\n+\t\tretval +=\n+\t\t    dwc_otg_set_param_phy_ulpi_ddr(core_if,\n+\t\t\t\t\t\t   dwc_otg_module_params.\n+\t\t\t\t\t\t   phy_ulpi_ddr);\n+\t}\n+\tif (dwc_otg_module_params.phy_ulpi_ext_vbus != -1) {\n+\t\tretval +=\n+\t\t    dwc_otg_set_param_phy_ulpi_ext_vbus(core_if,\n+\t\t\t\t\t\t\tdwc_otg_module_params.\n+\t\t\t\t\t\t\tphy_ulpi_ext_vbus);\n+\t}\n+\tif (dwc_otg_module_params.phy_utmi_width != -1) {\n+\t\tretval +=\n+\t\t    dwc_otg_set_param_phy_utmi_width(core_if,\n+\t\t\t\t\t\t     dwc_otg_module_params.\n+\t\t\t\t\t\t     phy_utmi_width);\n+\t}\n+\tif (dwc_otg_module_params.ulpi_fs_ls != -1) {\n+\t\tretval +=\n+\t\t    dwc_otg_set_param_ulpi_fs_ls(core_if,\n+\t\t\t\t\t\t dwc_otg_module_params.ulpi_fs_ls);\n+\t}\n+\tif (dwc_otg_module_params.ts_dline != -1) {\n+\t\tretval +=\n+\t\t    dwc_otg_set_param_ts_dline(core_if,\n+\t\t\t\t\t       dwc_otg_module_params.ts_dline);\n+\t}\n+\tif (dwc_otg_module_params.i2c_enable != -1) {\n+\t\tretval +=\n+\t\t    dwc_otg_set_param_i2c_enable(core_if,\n+\t\t\t\t\t\t dwc_otg_module_params.\n+\t\t\t\t\t\t i2c_enable);\n+\t}\n+\tif (dwc_otg_module_params.en_multiple_tx_fifo != -1) {\n+\t\tretval +=\n+\t\t    dwc_otg_set_param_en_multiple_tx_fifo(core_if,\n+\t\t\t\t\t\t\t  dwc_otg_module_params.\n+\t\t\t\t\t\t\t  en_multiple_tx_fifo);\n+\t}\n+\tfor (i = 0; i < 15; i++) {\n+\t\tif (dwc_otg_module_params.dev_perio_tx_fifo_size[i] != -1) {\n+\t\t\tretval +=\n+\t\t\t    dwc_otg_set_param_dev_perio_tx_fifo_size(core_if,\n+\t\t\t\t\t\t\t\t     dwc_otg_module_params.\n+\t\t\t\t\t\t\t\t     dev_perio_tx_fifo_size\n+\t\t\t\t\t\t\t\t     [i], i);\n+\t\t}\n+\t}\n+\n+\tfor (i = 0; i < 15; i++) {\n+\t\tif (dwc_otg_module_params.dev_tx_fifo_size[i] != -1) {\n+\t\t\tretval += dwc_otg_set_param_dev_tx_fifo_size(core_if,\n+\t\t\t\t\t\t\t\t     dwc_otg_module_params.\n+\t\t\t\t\t\t\t\t     dev_tx_fifo_size\n+\t\t\t\t\t\t\t\t     [i], i);\n+\t\t}\n+\t}\n+\tif (dwc_otg_module_params.thr_ctl != -1) {\n+\t\tretval +=\n+\t\t    dwc_otg_set_param_thr_ctl(core_if,\n+\t\t\t\t\t      dwc_otg_module_params.thr_ctl);\n+\t}\n+\tif (dwc_otg_module_params.mpi_enable != -1) {\n+\t\tretval +=\n+\t\t    dwc_otg_set_param_mpi_enable(core_if,\n+\t\t\t\t\t\t dwc_otg_module_params.\n+\t\t\t\t\t\t mpi_enable);\n+\t}\n+\tif (dwc_otg_module_params.pti_enable != -1) {\n+\t\tretval +=\n+\t\t    dwc_otg_set_param_pti_enable(core_if,\n+\t\t\t\t\t\t dwc_otg_module_params.\n+\t\t\t\t\t\t pti_enable);\n+\t}\n+\tif (dwc_otg_module_params.lpm_enable != -1) {\n+\t\tretval +=\n+\t\t    dwc_otg_set_param_lpm_enable(core_if,\n+\t\t\t\t\t\t dwc_otg_module_params.\n+\t\t\t\t\t\t lpm_enable);\n+\t}\n+\tif (dwc_otg_module_params.ic_usb_cap != -1) {\n+\t\tretval +=\n+\t\t    dwc_otg_set_param_ic_usb_cap(core_if,\n+\t\t\t\t\t\t dwc_otg_module_params.\n+\t\t\t\t\t\t ic_usb_cap);\n+\t}\n+\tif (dwc_otg_module_params.tx_thr_length != -1) {\n+\t\tretval +=\n+\t\t    dwc_otg_set_param_tx_thr_length(core_if,\n+\t\t\t\t\t\t    dwc_otg_module_params.tx_thr_length);\n+\t}\n+\tif (dwc_otg_module_params.rx_thr_length != -1) {\n+\t\tretval +=\n+\t\t    dwc_otg_set_param_rx_thr_length(core_if,\n+\t\t\t\t\t\t    dwc_otg_module_params.\n+\t\t\t\t\t\t    rx_thr_length);\n+\t}\n+\tif (dwc_otg_module_params.ahb_thr_ratio != -1) {\n+\t\tretval +=\n+\t\t    dwc_otg_set_param_ahb_thr_ratio(core_if,\n+\t\t\t\t\t\t    dwc_otg_module_params.ahb_thr_ratio);\n+\t}\n+\tif (dwc_otg_module_params.power_down != -1) {\n+\t\tretval +=\n+\t\t    dwc_otg_set_param_power_down(core_if,\n+\t\t\t\t\t\t dwc_otg_module_params.power_down);\n+\t}\n+\tif (dwc_otg_module_params.reload_ctl != -1) {\n+\t\tretval +=\n+\t\t    dwc_otg_set_param_reload_ctl(core_if,\n+\t\t\t\t\t\t dwc_otg_module_params.reload_ctl);\n+\t}\n+\n+\tif (dwc_otg_module_params.dev_out_nak != -1) {\n+\t\tretval +=\n+\t\t\tdwc_otg_set_param_dev_out_nak(core_if,\n+\t\t\tdwc_otg_module_params.dev_out_nak);\n+\t}\n+\n+\tif (dwc_otg_module_params.cont_on_bna != -1) {\n+\t\tretval +=\n+\t\t\tdwc_otg_set_param_cont_on_bna(core_if,\n+\t\t\tdwc_otg_module_params.cont_on_bna);\n+\t}\n+\n+\tif (dwc_otg_module_params.ahb_single != -1) {\n+\t\tretval +=\n+\t\t\tdwc_otg_set_param_ahb_single(core_if,\n+\t\t\tdwc_otg_module_params.ahb_single);\n+\t}\n+\n+\tif (dwc_otg_module_params.otg_ver != -1) {\n+\t\tretval +=\n+\t\t    dwc_otg_set_param_otg_ver(core_if,\n+\t\t\t\t\t      dwc_otg_module_params.otg_ver);\n+\t}\n+\tif (dwc_otg_module_params.adp_enable != -1) {\n+\t\tretval +=\n+\t\t    dwc_otg_set_param_adp_enable(core_if,\n+\t\t\t\t\t\t dwc_otg_module_params.\n+\t\t\t\t\t\t adp_enable);\n+\t}\n+\treturn retval;\n+}\n+\n+/**\n+ * This function is the top level interrupt handler for the Common\n+ * (Device and host modes) interrupts.\n+ */\n+static irqreturn_t dwc_otg_common_irq(int irq, void *dev)\n+{\n+\tint32_t retval = IRQ_NONE;\n+\n+\tretval = dwc_otg_handle_common_intr(dev);\n+\tif (retval != 0) {\n+\t\tS3C2410X_CLEAR_EINTPEND();\n+\t}\n+\treturn IRQ_RETVAL(retval);\n+}\n+\n+/**\n+ * This function is called when a lm_device is unregistered with the\n+ * dwc_otg_driver. This happens, for example, when the rmmod command is\n+ * executed. The device may or may not be electrically present. If it is\n+ * present, the driver stops device processing. Any resources used on behalf\n+ * of this device are freed.\n+ *\n+ * @param _dev\n+ */\n+#ifdef LM_INTERFACE\n+#define REM_RETVAL(n)\n+static void dwc_otg_driver_remove(\t struct lm_device *_dev )\n+{       dwc_otg_device_t *otg_dev = lm_get_drvdata(_dev);\n+#elif  defined(PCI_INTERFACE)\n+#define REM_RETVAL(n)\n+static void dwc_otg_driver_remove(\t struct pci_dev *_dev )\n+{\tdwc_otg_device_t *otg_dev = pci_get_drvdata(_dev);\n+#elif  defined(PLATFORM_INTERFACE)\n+#define REM_RETVAL(n) n\n+static int dwc_otg_driver_remove(        struct platform_device *_dev )\n+{       dwc_otg_device_t *otg_dev = platform_get_drvdata(_dev);\n+#endif\n+\n+\tDWC_DEBUGPL(DBG_ANY, \"%s(%p) otg_dev %p\\n\", __func__, _dev, otg_dev);\n+\n+\tif (!otg_dev) {\n+\t\t/* Memory allocation for the dwc_otg_device failed. */\n+\t\tDWC_DEBUGPL(DBG_ANY, \"%s: otg_dev NULL!\\n\", __func__);\n+                return REM_RETVAL(-ENOMEM);\n+\t}\n+#ifndef DWC_DEVICE_ONLY\n+\tif (otg_dev->hcd) {\n+\t\thcd_remove(_dev);\n+\t} else {\n+\t\tDWC_DEBUGPL(DBG_ANY, \"%s: otg_dev->hcd NULL!\\n\", __func__);\n+                return REM_RETVAL(-EINVAL);\n+\t}\n+#endif\n+\n+#ifndef DWC_HOST_ONLY\n+\tif (otg_dev->pcd) {\n+\t\tpcd_remove(_dev);\n+\t} else {\n+\t\tDWC_DEBUGPL(DBG_ANY, \"%s: otg_dev->pcd NULL!\\n\", __func__);\n+                return REM_RETVAL(-EINVAL);\n+\t}\n+#endif\n+\t/*\n+\t * Free the IRQ\n+\t */\n+\tif (otg_dev->common_irq_installed) {\n+\t\tfree_irq(otg_dev->os_dep.irq_num, otg_dev);\n+        } else {\n+\t\tDWC_DEBUGPL(DBG_ANY, \"%s: There is no installed irq!\\n\", __func__);\n+\t\treturn REM_RETVAL(-ENXIO);\n+\t}\n+\n+\tif (otg_dev->core_if) {\n+\t\tdwc_otg_cil_remove(otg_dev->core_if);\n+\t} else {\n+\t\tDWC_DEBUGPL(DBG_ANY, \"%s: otg_dev->core_if NULL!\\n\", __func__);\n+\t\treturn REM_RETVAL(-ENXIO);\n+\t}\n+\n+\t/*\n+\t * Remove the device attributes\n+\t */\n+\tdwc_otg_attr_remove(_dev);\n+\n+\t/*\n+\t * Return the memory.\n+\t */\n+\tif (otg_dev->os_dep.base) {\n+\t\tiounmap(otg_dev->os_dep.base);\n+\t}\n+\tDWC_FREE(otg_dev);\n+\n+\t/*\n+\t * Clear the drvdata pointer.\n+\t */\n+#ifdef LM_INTERFACE\n+\tlm_set_drvdata(_dev, 0);\n+#elif defined(PCI_INTERFACE)\n+        release_mem_region(otg_dev->os_dep.rsrc_start,\n+                           otg_dev->os_dep.rsrc_len);\n+\tpci_set_drvdata(_dev, 0);\n+#elif  defined(PLATFORM_INTERFACE)\n+        platform_set_drvdata(_dev, 0);\n+#endif\n+        return REM_RETVAL(0);\n+}\n+\n+/**\n+ * This function is called when an lm_device is bound to a\n+ * dwc_otg_driver. It creates the driver components required to\n+ * control the device (CIL, HCD, and PCD) and it initializes the\n+ * device. The driver components are stored in a dwc_otg_device\n+ * structure. A reference to the dwc_otg_device is saved in the\n+ * lm_device. This allows the driver to access the dwc_otg_device\n+ * structure on subsequent calls to driver methods for this device.\n+ *\n+ * @param _dev Bus device\n+ */\n+static int dwc_otg_driver_probe(\n+#ifdef LM_INTERFACE\n+\t\t\t\t       struct lm_device *_dev\n+#elif defined(PCI_INTERFACE)\n+\t\t\t\t       struct pci_dev *_dev,\n+\t\t\t\t       const struct pci_device_id *id\n+#elif  defined(PLATFORM_INTERFACE)\n+                                       struct platform_device *_dev\n+#endif\n+    )\n+{\n+\tint retval = 0;\n+\tdwc_otg_device_t *dwc_otg_device;\n+        int devirq;\n+\n+\tdev_dbg(&_dev->dev, \"dwc_otg_driver_probe(%p)\\n\", _dev);\n+#ifdef LM_INTERFACE\n+\tdev_dbg(&_dev->dev, \"start=0x%08x\\n\", (unsigned)_dev->resource.start);\n+#elif defined(PCI_INTERFACE)\n+\tif (!id) {\n+\t\tDWC_ERROR(\"Invalid pci_device_id %p\", id);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (!_dev || (pci_enable_device(_dev) < 0)) {\n+\t\tDWC_ERROR(\"Invalid pci_device %p\", _dev);\n+\t\treturn -ENODEV;\n+\t}\n+\tdev_dbg(&_dev->dev, \"start=0x%08x\\n\", (unsigned)pci_resource_start(_dev,0));\n+\t/* other stuff needed as well? */\n+\n+#elif  defined(PLATFORM_INTERFACE)\n+\tdev_dbg(&_dev->dev, \"start=0x%08x (len 0x%x)\\n\",\n+                (unsigned)_dev->resource->start,\n+                (unsigned)(_dev->resource->end - _dev->resource->start));\n+#endif\n+\n+\tdwc_otg_device = DWC_ALLOC(sizeof(dwc_otg_device_t));\n+\n+\tif (!dwc_otg_device) {\n+\t\tdev_err(&_dev->dev, \"kmalloc of dwc_otg_device failed\\n\");\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\tmemset(dwc_otg_device, 0, sizeof(*dwc_otg_device));\n+\tdwc_otg_device->os_dep.reg_offset = 0xFFFFFFFF;\n+\tdwc_otg_device->os_dep.platformdev = _dev;\n+\n+\t/*\n+\t * Map the DWC_otg Core memory into virtual address space.\n+\t */\n+#ifdef LM_INTERFACE\n+\tdwc_otg_device->os_dep.base = ioremap(_dev->resource.start, SZ_256K);\n+\n+\tif (!dwc_otg_device->os_dep.base) {\n+\t\tdev_err(&_dev->dev, \"ioremap() failed\\n\");\n+\t\tDWC_FREE(dwc_otg_device);\n+\t\treturn -ENOMEM;\n+\t}\n+\tdev_dbg(&_dev->dev, \"base=0x%08x\\n\",\n+\t\t(unsigned)dwc_otg_device->os_dep.base);\n+#elif defined(PCI_INTERFACE)\n+\t_dev->current_state = PCI_D0;\n+\t_dev->dev.power.power_state = PMSG_ON;\n+\n+\tif (!_dev->irq) {\n+\t\tDWC_ERROR(\"Found HC with no IRQ. Check BIOS/PCI %s setup!\",\n+\t\t\t  pci_name(_dev));\n+\t\tiounmap(dwc_otg_device->os_dep.base);\n+\t\tDWC_FREE(dwc_otg_device);\n+\t\treturn -ENODEV;\n+\t}\n+\n+\tdwc_otg_device->os_dep.rsrc_start = pci_resource_start(_dev, 0);\n+\tdwc_otg_device->os_dep.rsrc_len = pci_resource_len(_dev, 0);\n+\tDWC_DEBUGPL(DBG_ANY, \"PCI resource: start=%08x, len=%08x\\n\",\n+\t\t    (unsigned)dwc_otg_device->os_dep.rsrc_start,\n+\t\t    (unsigned)dwc_otg_device->os_dep.rsrc_len);\n+\tif (!request_mem_region\n+\t    (dwc_otg_device->os_dep.rsrc_start, dwc_otg_device->os_dep.rsrc_len,\n+\t     \"dwc_otg\")) {\n+\t\tdev_dbg(&_dev->dev, \"error requesting memory\\n\");\n+\t\tiounmap(dwc_otg_device->os_dep.base);\n+\t\tDWC_FREE(dwc_otg_device);\n+\t\treturn -EFAULT;\n+\t}\n+\n+\tdwc_otg_device->os_dep.base =\n+\t    ioremap(dwc_otg_device->os_dep.rsrc_start,\n+\t\t\t    dwc_otg_device->os_dep.rsrc_len);\n+\tif (dwc_otg_device->os_dep.base == NULL) {\n+\t\tdev_dbg(&_dev->dev, \"error mapping memory\\n\");\n+\t\trelease_mem_region(dwc_otg_device->os_dep.rsrc_start,\n+\t\t\t\t   dwc_otg_device->os_dep.rsrc_len);\n+\t\tiounmap(dwc_otg_device->os_dep.base);\n+\t\tDWC_FREE(dwc_otg_device);\n+\t\treturn -EFAULT;\n+\t}\n+\tdev_dbg(&_dev->dev, \"base=0x%p (before adjust) \\n\",\n+\t\tdwc_otg_device->os_dep.base);\n+\tdwc_otg_device->os_dep.base = (char *)dwc_otg_device->os_dep.base;\n+\tdev_dbg(&_dev->dev, \"base=0x%p (after adjust) \\n\",\n+\t\tdwc_otg_device->os_dep.base);\n+\tdev_dbg(&_dev->dev, \"%s: mapped PA 0x%x to VA 0x%p\\n\", __func__,\n+\t\t(unsigned)dwc_otg_device->os_dep.rsrc_start,\n+\t\tdwc_otg_device->os_dep.base);\n+\n+\tpci_set_master(_dev);\n+\tpci_set_drvdata(_dev, dwc_otg_device);\n+#elif defined(PLATFORM_INTERFACE)\n+        DWC_DEBUGPL(DBG_ANY,\"Platform resource: start=%08x, len=%08x\\n\",\n+                    _dev->resource->start,\n+                    _dev->resource->end - _dev->resource->start + 1);\n+#if 1\n+        if (!request_mem_region(_dev->resource[0].start,\n+                                _dev->resource[0].end - _dev->resource[0].start + 1,\n+                                \"dwc_otg\")) {\n+          dev_dbg(&_dev->dev, \"error reserving mapped memory\\n\");\n+          retval = -EFAULT;\n+          goto fail;\n+        }\n+\n+\tdwc_otg_device->os_dep.base = ioremap(_dev->resource[0].start,\n+                                                      _dev->resource[0].end -\n+                                                      _dev->resource[0].start+1);\n+\tif (fiq_enable)\n+\t{\n+\t\tif (!request_mem_region(_dev->resource[1].start,\n+\t                                _dev->resource[1].end - _dev->resource[1].start + 1,\n+\t                                \"dwc_otg\")) {\n+\t\t\tdev_dbg(&_dev->dev, \"error reserving mapped memory\\n\");\n+\t\t\tretval = -EFAULT;\n+\t\t\tgoto fail;\n+\t\t}\n+\n+\t\tdwc_otg_device->os_dep.mphi_base = ioremap(_dev->resource[1].start,\n+\t\t\t\t\t\t\t    _dev->resource[1].end -\n+\t\t\t\t\t\t\t    _dev->resource[1].start + 1);\n+\t\tdwc_otg_device->os_dep.use_swirq = (_dev->resource[1].end - _dev->resource[1].start) == 0x200;\n+\t}\n+\n+#else\n+        {\n+                struct map_desc desc = {\n+                    .virtual = IO_ADDRESS((unsigned)_dev->resource->start),\n+                    .pfn     = __phys_to_pfn((unsigned)_dev->resource->start),\n+                    .length  = SZ_128K,\n+                    .type    = MT_DEVICE\n+                };\n+                iotable_init(&desc, 1);\n+                dwc_otg_device->os_dep.base = (void *)desc.virtual;\n+        }\n+#endif\n+\tif (!dwc_otg_device->os_dep.base) {\n+\t\tdev_err(&_dev->dev, \"ioremap() failed\\n\");\n+\t\tretval = -ENOMEM;\n+\t\tgoto fail;\n+\t}\n+#endif\n+\n+\t/*\n+\t * Initialize driver data to point to the global DWC_otg\n+\t * Device structure.\n+\t */\n+#ifdef LM_INTERFACE\n+\tlm_set_drvdata(_dev, dwc_otg_device);\n+#elif defined(PLATFORM_INTERFACE)\n+\tplatform_set_drvdata(_dev, dwc_otg_device);\n+#endif\n+\tdev_dbg(&_dev->dev, \"dwc_otg_device=0x%p\\n\", dwc_otg_device);\n+\n+\tdwc_otg_device->core_if = dwc_otg_cil_init(dwc_otg_device->os_dep.base);\n+        DWC_DEBUGPL(DBG_HCDV, \"probe of device %p given core_if %p\\n\",\n+                    dwc_otg_device, dwc_otg_device->core_if);//GRAYG\n+\n+\tif (!dwc_otg_device->core_if) {\n+\t\tdev_err(&_dev->dev, \"CIL initialization failed!\\n\");\n+\t\tretval = -ENOMEM;\n+\t\tgoto fail;\n+\t}\n+\n+\tdev_dbg(&_dev->dev, \"Calling get_gsnpsid\\n\");\n+\t/*\n+\t * Attempt to ensure this device is really a DWC_otg Controller.\n+\t * Read and verify the SNPSID register contents. The value should be\n+\t * 0x45F42XXX or 0x45F42XXX, which corresponds to either \"OT2\" or \"OTG3\",\n+\t * as in \"OTG version 2.XX\" or \"OTG version 3.XX\".\n+\t */\n+\n+\tif (((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) !=\t0x4F542000) &&\n+\t\t((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) != 0x4F543000)) {\n+\t\tdev_err(&_dev->dev, \"Bad value for SNPSID: 0x%08x\\n\",\n+\t\t\tdwc_otg_get_gsnpsid(dwc_otg_device->core_if));\n+\t\tretval = -EINVAL;\n+\t\tgoto fail;\n+\t}\n+\n+\t/*\n+\t * Validate parameter values.\n+\t */\n+\tdev_dbg(&_dev->dev, \"Calling set_parameters\\n\");\n+\tif (set_parameters(dwc_otg_device->core_if)) {\n+\t\tretval = -EINVAL;\n+\t\tgoto fail;\n+\t}\n+\n+\t/*\n+\t * Create Device Attributes in sysfs\n+\t */\n+\tdev_dbg(&_dev->dev, \"Calling attr_create\\n\");\n+\tdwc_otg_attr_create(_dev);\n+\n+\t/*\n+\t * Disable the global interrupt until all the interrupt\n+\t * handlers are installed.\n+\t */\n+\tdev_dbg(&_dev->dev, \"Calling disable_global_interrupts\\n\");\n+\tdwc_otg_disable_global_interrupts(dwc_otg_device->core_if);\n+\n+\t/*\n+\t * Install the interrupt handler for the common interrupts before\n+\t * enabling common interrupts in core_init below.\n+\t */\n+\n+#if defined(PLATFORM_INTERFACE)\n+\tdevirq = platform_get_irq_byname(_dev, fiq_enable ? \"soft\" : \"usb\");\n+\tif (devirq < 0)\n+\t    devirq = platform_get_irq(_dev, fiq_enable ? 0 : 1);\n+#else\n+\tdevirq = _dev->irq;\n+#endif\n+\tDWC_DEBUGPL(DBG_CIL, \"registering (common) handler for irq%d\\n\",\n+\t\t    devirq);\n+\tdev_dbg(&_dev->dev, \"Calling request_irq(%d)\\n\", devirq);\n+\tretval = request_irq(devirq, dwc_otg_common_irq,\n+                             IRQF_SHARED,\n+                             \"dwc_otg\", dwc_otg_device);\n+\tif (retval) {\n+\t\tDWC_ERROR(\"request of irq%d failed\\n\", devirq);\n+\t\tretval = -EBUSY;\n+\t\tgoto fail;\n+\t} else {\n+\t\tdwc_otg_device->common_irq_installed = 1;\n+\t}\n+\tdwc_otg_device->os_dep.irq_num = devirq;\n+\tdwc_otg_device->os_dep.fiq_num = -EINVAL;\n+\tif (fiq_enable) {\n+\t\tint devfiq = platform_get_irq_byname(_dev, \"usb\");\n+\t\tif (devfiq < 0)\n+\t\t\tdevfiq = platform_get_irq(_dev, 1);\n+\t\tdwc_otg_device->os_dep.fiq_num = devfiq;\n+\t}\n+\n+#ifndef IRQF_TRIGGER_LOW\n+#if defined(LM_INTERFACE) || defined(PLATFORM_INTERFACE)\n+\tdev_dbg(&_dev->dev, \"Calling set_irq_type\\n\");\n+\tset_irq_type(devirq,\n+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30))\n+                     IRQT_LOW\n+#else\n+                     IRQ_TYPE_LEVEL_LOW\n+#endif\n+                    );\n+#endif\n+#endif /*IRQF_TRIGGER_LOW*/\n+\n+\t/*\n+\t * Initialize the DWC_otg core.\n+\t */\n+\tdev_dbg(&_dev->dev, \"Calling dwc_otg_core_init\\n\");\n+\tdwc_otg_core_init(dwc_otg_device->core_if);\n+\n+#ifndef DWC_HOST_ONLY\n+\t/*\n+\t * Initialize the PCD\n+\t */\n+\tdev_dbg(&_dev->dev, \"Calling pcd_init\\n\");\n+\tretval = pcd_init(_dev);\n+\tif (retval != 0) {\n+\t\tDWC_ERROR(\"pcd_init failed\\n\");\n+\t\tdwc_otg_device->pcd = NULL;\n+\t\tgoto fail;\n+\t}\n+#endif\n+#ifndef DWC_DEVICE_ONLY\n+\t/*\n+\t * Initialize the HCD\n+\t */\n+\tdev_dbg(&_dev->dev, \"Calling hcd_init\\n\");\n+\tretval = hcd_init(_dev);\n+\tif (retval != 0) {\n+\t\tDWC_ERROR(\"hcd_init failed\\n\");\n+\t\tdwc_otg_device->hcd = NULL;\n+\t\tgoto fail;\n+\t}\n+#endif\n+        /* Recover from drvdata having been overwritten by hcd_init() */\n+#ifdef LM_INTERFACE\n+\tlm_set_drvdata(_dev, dwc_otg_device);\n+#elif defined(PLATFORM_INTERFACE)\n+\tplatform_set_drvdata(_dev, dwc_otg_device);\n+#elif defined(PCI_INTERFACE)\n+\tpci_set_drvdata(_dev, dwc_otg_device);\n+\tdwc_otg_device->os_dep.pcidev = _dev;\n+#endif\n+\n+\t/*\n+\t * Enable the global interrupt after all the interrupt\n+\t * handlers are installed if there is no ADP support else\n+\t * perform initial actions required for Internal ADP logic.\n+\t */\n+\tif (!dwc_otg_get_param_adp_enable(dwc_otg_device->core_if)) {\n+\t        dev_dbg(&_dev->dev, \"Calling enable_global_interrupts\\n\");\n+\t\tdwc_otg_enable_global_interrupts(dwc_otg_device->core_if);\n+\t        dev_dbg(&_dev->dev, \"Done\\n\");\n+\t} else\n+\t\tdwc_otg_adp_start(dwc_otg_device->core_if,\n+\t\t\t\t\t\t\tdwc_otg_is_host_mode(dwc_otg_device->core_if));\n+\n+\treturn 0;\n+\n+fail:\n+\tdwc_otg_driver_remove(_dev);\n+\treturn retval;\n+}\n+\n+/**\n+ * This structure defines the methods to be called by a bus driver\n+ * during the lifecycle of a device on that bus. Both drivers and\n+ * devices are registered with a bus driver. The bus driver matches\n+ * devices to drivers based on information in the device and driver\n+ * structures.\n+ *\n+ * The probe function is called when the bus driver matches a device\n+ * to this driver. The remove function is called when a device is\n+ * unregistered with the bus driver.\n+ */\n+#ifdef LM_INTERFACE\n+static struct lm_driver dwc_otg_driver = {\n+\t.drv = {.name = (char *)dwc_driver_name,},\n+\t.probe = dwc_otg_driver_probe,\n+\t.remove = dwc_otg_driver_remove,\n+        // 'suspend' and 'resume' absent\n+};\n+#elif defined(PCI_INTERFACE)\n+static const struct pci_device_id pci_ids[] = { {\n+\t\t\t\t\t\t PCI_DEVICE(0x16c3, 0xabcd),\n+\t\t\t\t\t\t .driver_data =\n+\t\t\t\t\t\t (unsigned long)0xdeadbeef,\n+\t\t\t\t\t\t }, { /* end: all zeroes */ }\n+};\n+\n+MODULE_DEVICE_TABLE(pci, pci_ids);\n+\n+/* pci driver glue; this is a \"new style\" PCI driver module */\n+static struct pci_driver dwc_otg_driver = {\n+\t.name = \"dwc_otg\",\n+\t.id_table = pci_ids,\n+\n+\t.probe = dwc_otg_driver_probe,\n+\t.remove = dwc_otg_driver_remove,\n+\n+\t.driver = {\n+\t\t   .name = (char *)dwc_driver_name,\n+\t\t   },\n+};\n+#elif defined(PLATFORM_INTERFACE)\n+static struct platform_device_id platform_ids[] = {\n+        {\n+              .name = \"bcm2708_usb\",\n+              .driver_data = (kernel_ulong_t) 0xdeadbeef,\n+        },\n+        { /* end: all zeroes */ }\n+};\n+MODULE_DEVICE_TABLE(platform, platform_ids);\n+\n+static const struct of_device_id dwc_otg_of_match_table[] = {\n+\t{ .compatible = \"brcm,bcm2708-usb\", },\n+\t{},\n+};\n+MODULE_DEVICE_TABLE(of, dwc_otg_of_match_table);\n+\n+static struct platform_driver dwc_otg_driver = {\n+\t.driver = {\n+\t\t.name = (char *)dwc_driver_name,\n+\t\t.of_match_table = dwc_otg_of_match_table,\n+\t\t},\n+        .id_table = platform_ids,\n+\n+\t.probe = dwc_otg_driver_probe,\n+\t.remove = dwc_otg_driver_remove,\n+        // no 'shutdown', 'suspend', 'resume', 'suspend_late' or 'resume_early'\n+};\n+#endif\n+\n+/**\n+ * This function is called when the dwc_otg_driver is installed with the\n+ * insmod command. It registers the dwc_otg_driver structure with the\n+ * appropriate bus driver. This will cause the dwc_otg_driver_probe function\n+ * to be called. In addition, the bus driver will automatically expose\n+ * attributes defined for the device and driver in the special sysfs file\n+ * system.\n+ *\n+ * @return\n+ */\n+static int __init dwc_otg_driver_init(void)\n+{\n+\tint retval = 0;\n+\tint error;\n+        struct device_driver *drv;\n+\n+\tif(fiq_fsm_enable && !fiq_enable) {\n+\t\tprintk(KERN_WARNING \"dwc_otg: fiq_fsm_enable was set without fiq_enable! Correcting.\\n\");\n+\t\tfiq_enable = 1;\n+\t}\n+\n+\tprintk(KERN_INFO \"%s: version %s (%s bus)\\n\", dwc_driver_name,\n+\t       DWC_DRIVER_VERSION,\n+#ifdef LM_INTERFACE\n+               \"logicmodule\");\n+\tretval = lm_driver_register(&dwc_otg_driver);\n+        drv = &dwc_otg_driver.drv;\n+#elif defined(PCI_INTERFACE)\n+               \"pci\");\n+\tretval = pci_register_driver(&dwc_otg_driver);\n+        drv = &dwc_otg_driver.driver;\n+#elif defined(PLATFORM_INTERFACE)\n+               \"platform\");\n+\tretval = platform_driver_register(&dwc_otg_driver);\n+        drv = &dwc_otg_driver.driver;\n+#endif\n+\tif (retval < 0) {\n+\t\tprintk(KERN_ERR \"%s retval=%d\\n\", __func__, retval);\n+\t\treturn retval;\n+\t}\n+\tprintk(KERN_DEBUG \"dwc_otg: FIQ %s\\n\", fiq_enable ? \"enabled\":\"disabled\");\n+\tprintk(KERN_DEBUG \"dwc_otg: NAK holdoff %s\\n\", nak_holdoff ? \"enabled\":\"disabled\");\n+\tprintk(KERN_DEBUG \"dwc_otg: FIQ split-transaction FSM %s\\n\", fiq_fsm_enable ? \"enabled\":\"disabled\");\n+\n+\terror = driver_create_file(drv, &driver_attr_version);\n+#ifdef DEBUG\n+\terror = driver_create_file(drv, &driver_attr_debuglevel);\n+#endif\n+\treturn retval;\n+}\n+\n+module_init(dwc_otg_driver_init);\n+\n+/**\n+ * This function is called when the driver is removed from the kernel\n+ * with the rmmod command. The driver unregisters itself with its bus\n+ * driver.\n+ *\n+ */\n+static void __exit dwc_otg_driver_cleanup(void)\n+{\n+\tprintk(KERN_DEBUG \"dwc_otg_driver_cleanup()\\n\");\n+\n+#ifdef LM_INTERFACE\n+\tdriver_remove_file(&dwc_otg_driver.drv, &driver_attr_debuglevel);\n+\tdriver_remove_file(&dwc_otg_driver.drv, &driver_attr_version);\n+\tlm_driver_unregister(&dwc_otg_driver);\n+#elif defined(PCI_INTERFACE)\n+\tdriver_remove_file(&dwc_otg_driver.driver, &driver_attr_debuglevel);\n+\tdriver_remove_file(&dwc_otg_driver.driver, &driver_attr_version);\n+\tpci_unregister_driver(&dwc_otg_driver);\n+#elif defined(PLATFORM_INTERFACE)\n+\tdriver_remove_file(&dwc_otg_driver.driver, &driver_attr_debuglevel);\n+\tdriver_remove_file(&dwc_otg_driver.driver, &driver_attr_version);\n+\tplatform_driver_unregister(&dwc_otg_driver);\n+#endif\n+\n+\tprintk(KERN_INFO \"%s module removed\\n\", dwc_driver_name);\n+}\n+\n+module_exit(dwc_otg_driver_cleanup);\n+\n+MODULE_DESCRIPTION(DWC_DRIVER_DESC);\n+MODULE_AUTHOR(\"Synopsys Inc.\");\n+MODULE_LICENSE(\"GPL\");\n+\n+module_param_named(otg_cap, dwc_otg_module_params.otg_cap, int, 0444);\n+MODULE_PARM_DESC(otg_cap, \"OTG Capabilities 0=HNP&SRP 1=SRP Only 2=None\");\n+module_param_named(opt, dwc_otg_module_params.opt, int, 0444);\n+MODULE_PARM_DESC(opt, \"OPT Mode\");\n+module_param_named(dma_enable, dwc_otg_module_params.dma_enable, int, 0444);\n+MODULE_PARM_DESC(dma_enable, \"DMA Mode 0=Slave 1=DMA enabled\");\n+\n+module_param_named(dma_desc_enable, dwc_otg_module_params.dma_desc_enable, int,\n+\t\t   0444);\n+MODULE_PARM_DESC(dma_desc_enable,\n+\t\t \"DMA Desc Mode 0=Address DMA 1=DMA Descriptor enabled\");\n+\n+module_param_named(dma_burst_size, dwc_otg_module_params.dma_burst_size, int,\n+\t\t   0444);\n+MODULE_PARM_DESC(dma_burst_size,\n+\t\t \"DMA Burst Size 1, 4, 8, 16, 32, 64, 128, 256\");\n+module_param_named(speed, dwc_otg_module_params.speed, int, 0444);\n+MODULE_PARM_DESC(speed, \"Speed 0=High Speed 1=Full Speed\");\n+module_param_named(host_support_fs_ls_low_power,\n+\t\t   dwc_otg_module_params.host_support_fs_ls_low_power, int,\n+\t\t   0444);\n+MODULE_PARM_DESC(host_support_fs_ls_low_power,\n+\t\t \"Support Low Power w/FS or LS 0=Support 1=Don't Support\");\n+module_param_named(host_ls_low_power_phy_clk,\n+\t\t   dwc_otg_module_params.host_ls_low_power_phy_clk, int, 0444);\n+MODULE_PARM_DESC(host_ls_low_power_phy_clk,\n+\t\t \"Low Speed Low Power Clock 0=48Mhz 1=6Mhz\");\n+module_param_named(enable_dynamic_fifo,\n+\t\t   dwc_otg_module_params.enable_dynamic_fifo, int, 0444);\n+MODULE_PARM_DESC(enable_dynamic_fifo, \"0=cC Setting 1=Allow Dynamic Sizing\");\n+module_param_named(data_fifo_size, dwc_otg_module_params.data_fifo_size, int,\n+\t\t   0444);\n+MODULE_PARM_DESC(data_fifo_size,\n+\t\t \"Total number of words in the data FIFO memory 32-32768\");\n+module_param_named(dev_rx_fifo_size, dwc_otg_module_params.dev_rx_fifo_size,\n+\t\t   int, 0444);\n+MODULE_PARM_DESC(dev_rx_fifo_size, \"Number of words in the Rx FIFO 16-32768\");\n+module_param_named(dev_nperio_tx_fifo_size,\n+\t\t   dwc_otg_module_params.dev_nperio_tx_fifo_size, int, 0444);\n+MODULE_PARM_DESC(dev_nperio_tx_fifo_size,\n+\t\t \"Number of words in the non-periodic Tx FIFO 16-32768\");\n+module_param_named(dev_perio_tx_fifo_size_1,\n+\t\t   dwc_otg_module_params.dev_perio_tx_fifo_size[0], int, 0444);\n+MODULE_PARM_DESC(dev_perio_tx_fifo_size_1,\n+\t\t \"Number of words in the periodic Tx FIFO 4-768\");\n+module_param_named(dev_perio_tx_fifo_size_2,\n+\t\t   dwc_otg_module_params.dev_perio_tx_fifo_size[1], int, 0444);\n+MODULE_PARM_DESC(dev_perio_tx_fifo_size_2,\n+\t\t \"Number of words in the periodic Tx FIFO 4-768\");\n+module_param_named(dev_perio_tx_fifo_size_3,\n+\t\t   dwc_otg_module_params.dev_perio_tx_fifo_size[2], int, 0444);\n+MODULE_PARM_DESC(dev_perio_tx_fifo_size_3,\n+\t\t \"Number of words in the periodic Tx FIFO 4-768\");\n+module_param_named(dev_perio_tx_fifo_size_4,\n+\t\t   dwc_otg_module_params.dev_perio_tx_fifo_size[3], int, 0444);\n+MODULE_PARM_DESC(dev_perio_tx_fifo_size_4,\n+\t\t \"Number of words in the periodic Tx FIFO 4-768\");\n+module_param_named(dev_perio_tx_fifo_size_5,\n+\t\t   dwc_otg_module_params.dev_perio_tx_fifo_size[4], int, 0444);\n+MODULE_PARM_DESC(dev_perio_tx_fifo_size_5,\n+\t\t \"Number of words in the periodic Tx FIFO 4-768\");\n+module_param_named(dev_perio_tx_fifo_size_6,\n+\t\t   dwc_otg_module_params.dev_perio_tx_fifo_size[5], int, 0444);\n+MODULE_PARM_DESC(dev_perio_tx_fifo_size_6,\n+\t\t \"Number of words in the periodic Tx FIFO 4-768\");\n+module_param_named(dev_perio_tx_fifo_size_7,\n+\t\t   dwc_otg_module_params.dev_perio_tx_fifo_size[6], int, 0444);\n+MODULE_PARM_DESC(dev_perio_tx_fifo_size_7,\n+\t\t \"Number of words in the periodic Tx FIFO 4-768\");\n+module_param_named(dev_perio_tx_fifo_size_8,\n+\t\t   dwc_otg_module_params.dev_perio_tx_fifo_size[7], int, 0444);\n+MODULE_PARM_DESC(dev_perio_tx_fifo_size_8,\n+\t\t \"Number of words in the periodic Tx FIFO 4-768\");\n+module_param_named(dev_perio_tx_fifo_size_9,\n+\t\t   dwc_otg_module_params.dev_perio_tx_fifo_size[8], int, 0444);\n+MODULE_PARM_DESC(dev_perio_tx_fifo_size_9,\n+\t\t \"Number of words in the periodic Tx FIFO 4-768\");\n+module_param_named(dev_perio_tx_fifo_size_10,\n+\t\t   dwc_otg_module_params.dev_perio_tx_fifo_size[9], int, 0444);\n+MODULE_PARM_DESC(dev_perio_tx_fifo_size_10,\n+\t\t \"Number of words in the periodic Tx FIFO 4-768\");\n+module_param_named(dev_perio_tx_fifo_size_11,\n+\t\t   dwc_otg_module_params.dev_perio_tx_fifo_size[10], int, 0444);\n+MODULE_PARM_DESC(dev_perio_tx_fifo_size_11,\n+\t\t \"Number of words in the periodic Tx FIFO 4-768\");\n+module_param_named(dev_perio_tx_fifo_size_12,\n+\t\t   dwc_otg_module_params.dev_perio_tx_fifo_size[11], int, 0444);\n+MODULE_PARM_DESC(dev_perio_tx_fifo_size_12,\n+\t\t \"Number of words in the periodic Tx FIFO 4-768\");\n+module_param_named(dev_perio_tx_fifo_size_13,\n+\t\t   dwc_otg_module_params.dev_perio_tx_fifo_size[12], int, 0444);\n+MODULE_PARM_DESC(dev_perio_tx_fifo_size_13,\n+\t\t \"Number of words in the periodic Tx FIFO 4-768\");\n+module_param_named(dev_perio_tx_fifo_size_14,\n+\t\t   dwc_otg_module_params.dev_perio_tx_fifo_size[13], int, 0444);\n+MODULE_PARM_DESC(dev_perio_tx_fifo_size_14,\n+\t\t \"Number of words in the periodic Tx FIFO 4-768\");\n+module_param_named(dev_perio_tx_fifo_size_15,\n+\t\t   dwc_otg_module_params.dev_perio_tx_fifo_size[14], int, 0444);\n+MODULE_PARM_DESC(dev_perio_tx_fifo_size_15,\n+\t\t \"Number of words in the periodic Tx FIFO 4-768\");\n+module_param_named(host_rx_fifo_size, dwc_otg_module_params.host_rx_fifo_size,\n+\t\t   int, 0444);\n+MODULE_PARM_DESC(host_rx_fifo_size, \"Number of words in the Rx FIFO 16-32768\");\n+module_param_named(host_nperio_tx_fifo_size,\n+\t\t   dwc_otg_module_params.host_nperio_tx_fifo_size, int, 0444);\n+MODULE_PARM_DESC(host_nperio_tx_fifo_size,\n+\t\t \"Number of words in the non-periodic Tx FIFO 16-32768\");\n+module_param_named(host_perio_tx_fifo_size,\n+\t\t   dwc_otg_module_params.host_perio_tx_fifo_size, int, 0444);\n+MODULE_PARM_DESC(host_perio_tx_fifo_size,\n+\t\t \"Number of words in the host periodic Tx FIFO 16-32768\");\n+module_param_named(max_transfer_size, dwc_otg_module_params.max_transfer_size,\n+\t\t   int, 0444);\n+/** @todo Set the max to 512K, modify checks */\n+MODULE_PARM_DESC(max_transfer_size,\n+\t\t \"The maximum transfer size supported in bytes 2047-65535\");\n+module_param_named(max_packet_count, dwc_otg_module_params.max_packet_count,\n+\t\t   int, 0444);\n+MODULE_PARM_DESC(max_packet_count,\n+\t\t \"The maximum number of packets in a transfer 15-511\");\n+module_param_named(host_channels, dwc_otg_module_params.host_channels, int,\n+\t\t   0444);\n+MODULE_PARM_DESC(host_channels,\n+\t\t \"The number of host channel registers to use 1-16\");\n+module_param_named(dev_endpoints, dwc_otg_module_params.dev_endpoints, int,\n+\t\t   0444);\n+MODULE_PARM_DESC(dev_endpoints,\n+\t\t \"The number of endpoints in addition to EP0 available for device mode 1-15\");\n+module_param_named(phy_type, dwc_otg_module_params.phy_type, int, 0444);\n+MODULE_PARM_DESC(phy_type, \"0=Reserved 1=UTMI+ 2=ULPI\");\n+module_param_named(phy_utmi_width, dwc_otg_module_params.phy_utmi_width, int,\n+\t\t   0444);\n+MODULE_PARM_DESC(phy_utmi_width, \"Specifies the UTMI+ Data Width 8 or 16 bits\");\n+module_param_named(phy_ulpi_ddr, dwc_otg_module_params.phy_ulpi_ddr, int, 0444);\n+MODULE_PARM_DESC(phy_ulpi_ddr,\n+\t\t \"ULPI at double or single data rate 0=Single 1=Double\");\n+module_param_named(phy_ulpi_ext_vbus, dwc_otg_module_params.phy_ulpi_ext_vbus,\n+\t\t   int, 0444);\n+MODULE_PARM_DESC(phy_ulpi_ext_vbus,\n+\t\t \"ULPI PHY using internal or external vbus 0=Internal\");\n+module_param_named(i2c_enable, dwc_otg_module_params.i2c_enable, int, 0444);\n+MODULE_PARM_DESC(i2c_enable, \"FS PHY Interface\");\n+module_param_named(ulpi_fs_ls, dwc_otg_module_params.ulpi_fs_ls, int, 0444);\n+MODULE_PARM_DESC(ulpi_fs_ls, \"ULPI PHY FS/LS mode only\");\n+module_param_named(ts_dline, dwc_otg_module_params.ts_dline, int, 0444);\n+MODULE_PARM_DESC(ts_dline, \"Term select Dline pulsing for all PHYs\");\n+module_param_named(debug, g_dbg_lvl, int, 0444);\n+MODULE_PARM_DESC(debug, \"\");\n+\n+module_param_named(en_multiple_tx_fifo,\n+\t\t   dwc_otg_module_params.en_multiple_tx_fifo, int, 0444);\n+MODULE_PARM_DESC(en_multiple_tx_fifo,\n+\t\t \"Dedicated Non Periodic Tx FIFOs 0=disabled 1=enabled\");\n+module_param_named(dev_tx_fifo_size_1,\n+\t\t   dwc_otg_module_params.dev_tx_fifo_size[0], int, 0444);\n+MODULE_PARM_DESC(dev_tx_fifo_size_1, \"Number of words in the Tx FIFO 4-768\");\n+module_param_named(dev_tx_fifo_size_2,\n+\t\t   dwc_otg_module_params.dev_tx_fifo_size[1], int, 0444);\n+MODULE_PARM_DESC(dev_tx_fifo_size_2, \"Number of words in the Tx FIFO 4-768\");\n+module_param_named(dev_tx_fifo_size_3,\n+\t\t   dwc_otg_module_params.dev_tx_fifo_size[2], int, 0444);\n+MODULE_PARM_DESC(dev_tx_fifo_size_3, \"Number of words in the Tx FIFO 4-768\");\n+module_param_named(dev_tx_fifo_size_4,\n+\t\t   dwc_otg_module_params.dev_tx_fifo_size[3], int, 0444);\n+MODULE_PARM_DESC(dev_tx_fifo_size_4, \"Number of words in the Tx FIFO 4-768\");\n+module_param_named(dev_tx_fifo_size_5,\n+\t\t   dwc_otg_module_params.dev_tx_fifo_size[4], int, 0444);\n+MODULE_PARM_DESC(dev_tx_fifo_size_5, \"Number of words in the Tx FIFO 4-768\");\n+module_param_named(dev_tx_fifo_size_6,\n+\t\t   dwc_otg_module_params.dev_tx_fifo_size[5], int, 0444);\n+MODULE_PARM_DESC(dev_tx_fifo_size_6, \"Number of words in the Tx FIFO 4-768\");\n+module_param_named(dev_tx_fifo_size_7,\n+\t\t   dwc_otg_module_params.dev_tx_fifo_size[6], int, 0444);\n+MODULE_PARM_DESC(dev_tx_fifo_size_7, \"Number of words in the Tx FIFO 4-768\");\n+module_param_named(dev_tx_fifo_size_8,\n+\t\t   dwc_otg_module_params.dev_tx_fifo_size[7], int, 0444);\n+MODULE_PARM_DESC(dev_tx_fifo_size_8, \"Number of words in the Tx FIFO 4-768\");\n+module_param_named(dev_tx_fifo_size_9,\n+\t\t   dwc_otg_module_params.dev_tx_fifo_size[8], int, 0444);\n+MODULE_PARM_DESC(dev_tx_fifo_size_9, \"Number of words in the Tx FIFO 4-768\");\n+module_param_named(dev_tx_fifo_size_10,\n+\t\t   dwc_otg_module_params.dev_tx_fifo_size[9], int, 0444);\n+MODULE_PARM_DESC(dev_tx_fifo_size_10, \"Number of words in the Tx FIFO 4-768\");\n+module_param_named(dev_tx_fifo_size_11,\n+\t\t   dwc_otg_module_params.dev_tx_fifo_size[10], int, 0444);\n+MODULE_PARM_DESC(dev_tx_fifo_size_11, \"Number of words in the Tx FIFO 4-768\");\n+module_param_named(dev_tx_fifo_size_12,\n+\t\t   dwc_otg_module_params.dev_tx_fifo_size[11], int, 0444);\n+MODULE_PARM_DESC(dev_tx_fifo_size_12, \"Number of words in the Tx FIFO 4-768\");\n+module_param_named(dev_tx_fifo_size_13,\n+\t\t   dwc_otg_module_params.dev_tx_fifo_size[12], int, 0444);\n+MODULE_PARM_DESC(dev_tx_fifo_size_13, \"Number of words in the Tx FIFO 4-768\");\n+module_param_named(dev_tx_fifo_size_14,\n+\t\t   dwc_otg_module_params.dev_tx_fifo_size[13], int, 0444);\n+MODULE_PARM_DESC(dev_tx_fifo_size_14, \"Number of words in the Tx FIFO 4-768\");\n+module_param_named(dev_tx_fifo_size_15,\n+\t\t   dwc_otg_module_params.dev_tx_fifo_size[14], int, 0444);\n+MODULE_PARM_DESC(dev_tx_fifo_size_15, \"Number of words in the Tx FIFO 4-768\");\n+\n+module_param_named(thr_ctl, dwc_otg_module_params.thr_ctl, int, 0444);\n+MODULE_PARM_DESC(thr_ctl,\n+\t\t \"Thresholding enable flag bit 0 - non ISO Tx thr., 1 - ISO Tx thr., 2 - Rx thr.- bit 0=disabled 1=enabled\");\n+module_param_named(tx_thr_length, dwc_otg_module_params.tx_thr_length, int,\n+\t\t   0444);\n+MODULE_PARM_DESC(tx_thr_length, \"Tx Threshold length in 32 bit DWORDs\");\n+module_param_named(rx_thr_length, dwc_otg_module_params.rx_thr_length, int,\n+\t\t   0444);\n+MODULE_PARM_DESC(rx_thr_length, \"Rx Threshold length in 32 bit DWORDs\");\n+\n+module_param_named(pti_enable, dwc_otg_module_params.pti_enable, int, 0444);\n+module_param_named(mpi_enable, dwc_otg_module_params.mpi_enable, int, 0444);\n+module_param_named(lpm_enable, dwc_otg_module_params.lpm_enable, int, 0444);\n+MODULE_PARM_DESC(lpm_enable, \"LPM Enable 0=LPM Disabled 1=LPM Enabled\");\n+module_param_named(ic_usb_cap, dwc_otg_module_params.ic_usb_cap, int, 0444);\n+MODULE_PARM_DESC(ic_usb_cap,\n+\t\t \"IC_USB Capability 0=IC_USB Disabled 1=IC_USB Enabled\");\n+module_param_named(ahb_thr_ratio, dwc_otg_module_params.ahb_thr_ratio, int,\n+\t\t   0444);\n+MODULE_PARM_DESC(ahb_thr_ratio, \"AHB Threshold Ratio\");\n+module_param_named(power_down, dwc_otg_module_params.power_down, int, 0444);\n+MODULE_PARM_DESC(power_down, \"Power Down Mode\");\n+module_param_named(reload_ctl, dwc_otg_module_params.reload_ctl, int, 0444);\n+MODULE_PARM_DESC(reload_ctl, \"HFIR Reload Control\");\n+module_param_named(dev_out_nak, dwc_otg_module_params.dev_out_nak, int, 0444);\n+MODULE_PARM_DESC(dev_out_nak, \"Enable Device OUT NAK\");\n+module_param_named(cont_on_bna, dwc_otg_module_params.cont_on_bna, int, 0444);\n+MODULE_PARM_DESC(cont_on_bna, \"Enable Enable Continue on BNA\");\n+module_param_named(ahb_single, dwc_otg_module_params.ahb_single, int, 0444);\n+MODULE_PARM_DESC(ahb_single, \"Enable AHB Single Support\");\n+module_param_named(adp_enable, dwc_otg_module_params.adp_enable, int, 0444);\n+MODULE_PARM_DESC(adp_enable, \"ADP Enable 0=ADP Disabled 1=ADP Enabled\");\n+module_param_named(otg_ver, dwc_otg_module_params.otg_ver, int, 0444);\n+MODULE_PARM_DESC(otg_ver, \"OTG revision supported 0=OTG 1.3 1=OTG 2.0\");\n+module_param(microframe_schedule, bool, 0444);\n+MODULE_PARM_DESC(microframe_schedule, \"Enable the microframe scheduler\");\n+\n+module_param(fiq_enable, bool, 0444);\n+MODULE_PARM_DESC(fiq_enable, \"Enable the FIQ\");\n+module_param(nak_holdoff, ushort, 0644);\n+MODULE_PARM_DESC(nak_holdoff, \"Throttle duration for bulk split-transaction endpoints on a NAK. Default 8\");\n+module_param(fiq_fsm_enable, bool, 0444);\n+MODULE_PARM_DESC(fiq_fsm_enable, \"Enable the FIQ to perform split transactions as defined by fiq_fsm_mask\");\n+module_param(fiq_fsm_mask, ushort, 0444);\n+MODULE_PARM_DESC(fiq_fsm_mask, \"Bitmask of transactions to perform in the FIQ.\\n\"\n+\t\t\t\t\t\"Bit 0 : Non-periodic split transactions\\n\"\n+\t\t\t\t\t\"Bit 1 : Periodic split transactions\\n\"\n+\t\t\t\t\t\"Bit 2 : High-speed multi-transfer isochronous\\n\"\n+\t\t\t\t\t\"All other bits should be set 0.\");\n+module_param(int_ep_interval_min, ushort, 0644);\n+MODULE_PARM_DESC(int_ep_interval_min, \"Clamp high-speed Interrupt endpoints to a minimum polling interval.\\n\"\n+\t\t\t\t\t\"0..1 = Use endpoint default\\n\"\n+\t\t\t\t\t\"2..n = Minimum interval n microframes. Use powers of 2.\\n\");\n+\n+module_param(cil_force_host, bool, 0644);\n+MODULE_PARM_DESC(cil_force_host, \"On a connector-ID status change, \"\n+\t\t\t\t\t\"force Host Mode regardless of OTG state.\");\n+\n+/** @page \"Module Parameters\"\n+ *\n+ * The following parameters may be specified when starting the module.\n+ * These parameters define how the DWC_otg controller should be\n+ * configured. Parameter values are passed to the CIL initialization\n+ * function dwc_otg_cil_init\n+ *\n+ * Example: <code>modprobe dwc_otg speed=1 otg_cap=1</code>\n+ *\n+\n+ <table>\n+ <tr><td>Parameter Name</td><td>Meaning</td></tr>\n+\n+ <tr>\n+ <td>otg_cap</td>\n+ <td>Specifies the OTG capabilities. The driver will automatically detect the\n+ value for this parameter if none is specified.\n+ - 0: HNP and SRP capable (default, if available)\n+ - 1: SRP Only capable\n+ - 2: No HNP/SRP capable\n+ </td></tr>\n+\n+ <tr>\n+ <td>dma_enable</td>\n+ <td>Specifies whether to use slave or DMA mode for accessing the data FIFOs.\n+ The driver will automatically detect the value for this parameter if none is\n+ specified.\n+ - 0: Slave\n+ - 1: DMA (default, if available)\n+ </td></tr>\n+\n+ <tr>\n+ <td>dma_burst_size</td>\n+ <td>The DMA Burst size (applicable only for External DMA Mode).\n+ - Values: 1, 4, 8 16, 32, 64, 128, 256 (default 32)\n+ </td></tr>\n+\n+ <tr>\n+ <td>speed</td>\n+ <td>Specifies the maximum speed of operation in host and device mode. The\n+ actual speed depends on the speed of the attached device and the value of\n+ phy_type.\n+ - 0: High Speed (default)\n+ - 1: Full Speed\n+ </td></tr>\n+\n+ <tr>\n+ <td>host_support_fs_ls_low_power</td>\n+ <td>Specifies whether low power mode is supported when attached to a Full\n+ Speed or Low Speed device in host mode.\n+ - 0: Don't support low power mode (default)\n+ - 1: Support low power mode\n+ </td></tr>\n+\n+ <tr>\n+ <td>host_ls_low_power_phy_clk</td>\n+ <td>Specifies the PHY clock rate in low power mode when connected to a Low\n+ Speed device in host mode. This parameter is applicable only if\n+ HOST_SUPPORT_FS_LS_LOW_POWER is enabled.\n+ - 0: 48 MHz (default)\n+ - 1: 6 MHz\n+ </td></tr>\n+\n+ <tr>\n+ <td>enable_dynamic_fifo</td>\n+ <td> Specifies whether FIFOs may be resized by the driver software.\n+ - 0: Use cC FIFO size parameters\n+ - 1: Allow dynamic FIFO sizing (default)\n+ </td></tr>\n+\n+ <tr>\n+ <td>data_fifo_size</td>\n+ <td>Total number of 4-byte words in the data FIFO memory. This memory\n+ includes the Rx FIFO, non-periodic Tx FIFO, and periodic Tx FIFOs.\n+ - Values: 32 to 32768 (default 8192)\n+\n+ Note: The total FIFO memory depth in the FPGA configuration is 8192.\n+ </td></tr>\n+\n+ <tr>\n+ <td>dev_rx_fifo_size</td>\n+ <td>Number of 4-byte words in the Rx FIFO in device mode when dynamic\n+ FIFO sizing is enabled.\n+ - Values: 16 to 32768 (default 1064)\n+ </td></tr>\n+\n+ <tr>\n+ <td>dev_nperio_tx_fifo_size</td>\n+ <td>Number of 4-byte words in the non-periodic Tx FIFO in device mode when\n+ dynamic FIFO sizing is enabled.\n+ - Values: 16 to 32768 (default 1024)\n+ </td></tr>\n+\n+ <tr>\n+ <td>dev_perio_tx_fifo_size_n (n = 1 to 15)</td>\n+ <td>Number of 4-byte words in each of the periodic Tx FIFOs in device mode\n+ when dynamic FIFO sizing is enabled.\n+ - Values: 4 to 768 (default 256)\n+ </td></tr>\n+\n+ <tr>\n+ <td>host_rx_fifo_size</td>\n+ <td>Number of 4-byte words in the Rx FIFO in host mode when dynamic FIFO\n+ sizing is enabled.\n+ - Values: 16 to 32768 (default 1024)\n+ </td></tr>\n+\n+ <tr>\n+ <td>host_nperio_tx_fifo_size</td>\n+ <td>Number of 4-byte words in the non-periodic Tx FIFO in host mode when\n+ dynamic FIFO sizing is enabled in the core.\n+ - Values: 16 to 32768 (default 1024)\n+ </td></tr>\n+\n+ <tr>\n+ <td>host_perio_tx_fifo_size</td>\n+ <td>Number of 4-byte words in the host periodic Tx FIFO when dynamic FIFO\n+ sizing is enabled.\n+ - Values: 16 to 32768 (default 1024)\n+ </td></tr>\n+\n+ <tr>\n+ <td>max_transfer_size</td>\n+ <td>The maximum transfer size supported in bytes.\n+ - Values: 2047 to 65,535 (default 65,535)\n+ </td></tr>\n+\n+ <tr>\n+ <td>max_packet_count</td>\n+ <td>The maximum number of packets in a transfer.\n+ - Values: 15 to 511 (default 511)\n+ </td></tr>\n+\n+ <tr>\n+ <td>host_channels</td>\n+ <td>The number of host channel registers to use.\n+ - Values: 1 to 16 (default 12)\n+\n+ Note: The FPGA configuration supports a maximum of 12 host channels.\n+ </td></tr>\n+\n+ <tr>\n+ <td>dev_endpoints</td>\n+ <td>The number of endpoints in addition to EP0 available for device mode\n+ operations.\n+ - Values: 1 to 15 (default 6 IN and OUT)\n+\n+ Note: The FPGA configuration supports a maximum of 6 IN and OUT endpoints in\n+ addition to EP0.\n+ </td></tr>\n+\n+ <tr>\n+ <td>phy_type</td>\n+ <td>Specifies the type of PHY interface to use. By default, the driver will\n+ automatically detect the phy_type.\n+ - 0: Full Speed\n+ - 1: UTMI+ (default, if available)\n+ - 2: ULPI\n+ </td></tr>\n+\n+ <tr>\n+ <td>phy_utmi_width</td>\n+ <td>Specifies the UTMI+ Data Width. This parameter is applicable for a\n+ phy_type of UTMI+. Also, this parameter is applicable only if the\n+ OTG_HSPHY_WIDTH cC parameter was set to \"8 and 16 bits\", meaning that the\n+ core has been configured to work at either data path width.\n+ - Values: 8 or 16 bits (default 16)\n+ </td></tr>\n+\n+ <tr>\n+ <td>phy_ulpi_ddr</td>\n+ <td>Specifies whether the ULPI operates at double or single data rate. This\n+ parameter is only applicable if phy_type is ULPI.\n+ - 0: single data rate ULPI interface with 8 bit wide data bus (default)\n+ - 1: double data rate ULPI interface with 4 bit wide data bus\n+ </td></tr>\n+\n+ <tr>\n+ <td>i2c_enable</td>\n+ <td>Specifies whether to use the I2C interface for full speed PHY. This\n+ parameter is only applicable if PHY_TYPE is FS.\n+ - 0: Disabled (default)\n+ - 1: Enabled\n+ </td></tr>\n+\n+ <tr>\n+ <td>ulpi_fs_ls</td>\n+ <td>Specifies whether to use ULPI FS/LS mode only.\n+ - 0: Disabled (default)\n+ - 1: Enabled\n+ </td></tr>\n+\n+ <tr>\n+ <td>ts_dline</td>\n+ <td>Specifies whether term select D-Line pulsing for all PHYs is enabled.\n+ - 0: Disabled (default)\n+ - 1: Enabled\n+ </td></tr>\n+\n+ <tr>\n+ <td>en_multiple_tx_fifo</td>\n+ <td>Specifies whether dedicatedto tx fifos are enabled for non periodic IN EPs.\n+ The driver will automatically detect the value for this parameter if none is\n+ specified.\n+ - 0: Disabled\n+ - 1: Enabled (default, if available)\n+ </td></tr>\n+\n+ <tr>\n+ <td>dev_tx_fifo_size_n (n = 1 to 15)</td>\n+ <td>Number of 4-byte words in each of the Tx FIFOs in device mode\n+ when dynamic FIFO sizing is enabled.\n+ - Values: 4 to 768 (default 256)\n+ </td></tr>\n+\n+ <tr>\n+ <td>tx_thr_length</td>\n+ <td>Transmit Threshold length in 32 bit double words\n+ - Values: 8 to 128 (default 64)\n+ </td></tr>\n+\n+ <tr>\n+ <td>rx_thr_length</td>\n+ <td>Receive Threshold length in 32 bit double words\n+ - Values: 8 to 128 (default 64)\n+ </td></tr>\n+\n+<tr>\n+ <td>thr_ctl</td>\n+ <td>Specifies whether to enable Thresholding for Device mode. Bits 0, 1, 2 of\n+ this parmater specifies if thresholding is enabled for non-Iso Tx, Iso Tx and\n+ Rx transfers accordingly.\n+ The driver will automatically detect the value for this parameter if none is\n+ specified.\n+ - Values: 0 to 7 (default 0)\n+ Bit values indicate:\n+ - 0: Thresholding disabled\n+ - 1: Thresholding enabled\n+ </td></tr>\n+\n+<tr>\n+ <td>dma_desc_enable</td>\n+ <td>Specifies whether to enable Descriptor DMA mode.\n+ The driver will automatically detect the value for this parameter if none is\n+ specified.\n+ - 0: Descriptor DMA disabled\n+ - 1: Descriptor DMA (default, if available)\n+ </td></tr>\n+\n+<tr>\n+ <td>mpi_enable</td>\n+ <td>Specifies whether to enable MPI enhancement mode.\n+ The driver will automatically detect the value for this parameter if none is\n+ specified.\n+ - 0: MPI disabled (default)\n+ - 1: MPI enable\n+ </td></tr>\n+\n+<tr>\n+ <td>pti_enable</td>\n+ <td>Specifies whether to enable PTI enhancement support.\n+ The driver will automatically detect the value for this parameter if none is\n+ specified.\n+ - 0: PTI disabled (default)\n+ - 1: PTI enable\n+ </td></tr>\n+\n+<tr>\n+ <td>lpm_enable</td>\n+ <td>Specifies whether to enable LPM support.\n+ The driver will automatically detect the value for this parameter if none is\n+ specified.\n+ - 0: LPM disabled\n+ - 1: LPM enable (default, if available)\n+ </td></tr>\n+\n+<tr>\n+ <td>ic_usb_cap</td>\n+ <td>Specifies whether to enable IC_USB capability.\n+ The driver will automatically detect the value for this parameter if none is\n+ specified.\n+ - 0: IC_USB disabled (default, if available)\n+ - 1: IC_USB enable\n+ </td></tr>\n+\n+<tr>\n+ <td>ahb_thr_ratio</td>\n+ <td>Specifies AHB Threshold ratio.\n+ - Values: 0 to 3 (default 0)\n+ </td></tr>\n+\n+<tr>\n+ <td>power_down</td>\n+ <td>Specifies Power Down(Hibernation) Mode.\n+ The driver will automatically detect the value for this parameter if none is\n+ specified.\n+ - 0: Power Down disabled (default)\n+ - 2: Power Down enabled\n+ </td></tr>\n+\n+ <tr>\n+ <td>reload_ctl</td>\n+ <td>Specifies whether dynamic reloading of the HFIR register is allowed during\n+ run time. The driver will automatically detect the value for this parameter if\n+ none is specified. In case the HFIR value is reloaded when HFIR.RldCtrl == 1'b0\n+ the core might misbehave.\n+ - 0: Reload Control disabled (default)\n+ - 1: Reload Control enabled\n+ </td></tr>\n+\n+ <tr>\n+ <td>dev_out_nak</td>\n+ <td>Specifies whether  Device OUT NAK enhancement enabled or no.\n+ The driver will automatically detect the value for this parameter if\n+ none is specified. This parameter is valid only when OTG_EN_DESC_DMA == 1b1.\n+ - 0: The core does not set NAK after Bulk OUT transfer complete (default)\n+ - 1: The core sets NAK after Bulk OUT transfer complete\n+ </td></tr>\n+\n+ <tr>\n+ <td>cont_on_bna</td>\n+ <td>Specifies whether Enable Continue on BNA enabled or no.\n+ After receiving BNA interrupt the core disables the endpoint,when the\n+ endpoint is re-enabled by the application the\n+ - 0: Core starts processing from the DOEPDMA descriptor (default)\n+ - 1: Core starts processing from the descriptor which received the BNA.\n+ This parameter is valid only when OTG_EN_DESC_DMA == 1b1.\n+ </td></tr>\n+\n+ <tr>\n+ <td>ahb_single</td>\n+ <td>This bit when programmed supports SINGLE transfers for remainder data\n+ in a transfer for DMA mode of operation.\n+ - 0: The remainder data will be sent using INCR burst size (default)\n+ - 1: The remainder data will be sent using SINGLE burst size.\n+ </td></tr>\n+\n+<tr>\n+ <td>adp_enable</td>\n+ <td>Specifies whether ADP feature is enabled.\n+ The driver will automatically detect the value for this parameter if none is\n+ specified.\n+ - 0: ADP feature disabled (default)\n+ - 1: ADP feature enabled\n+ </td></tr>\n+\n+  <tr>\n+ <td>otg_ver</td>\n+ <td>Specifies whether OTG is performing as USB OTG Revision 2.0 or Revision 1.3\n+ USB OTG device.\n+ - 0: OTG 2.0 support disabled (default)\n+ - 1: OTG 2.0 support enabled\n+ </td></tr>\n+\n+*/\n--- /dev/null\n+++ b/drivers/usb/host/dwc_otg/dwc_otg_driver.h\n@@ -0,0 +1,86 @@\n+/* ==========================================================================\n+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_driver.h $\n+ * $Revision: #19 $\n+ * $Date: 2010/11/15 $\n+ * $Change: 1627671 $\n+ *\n+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,\n+ * \"Software\") is an Unsupported proprietary work of Synopsys, Inc. unless\n+ * otherwise expressly agreed to in writing between Synopsys and you.\n+ *\n+ * The Software IS NOT an item of Licensed Software or Licensed Product under\n+ * any End User Software License Agreement or Agreement for Licensed Product\n+ * with Synopsys or any supplement thereto. You are permitted to use and\n+ * redistribute this Software in source and binary forms, with or without\n+ * modification, provided that redistributions of source code must retain this\n+ * notice. You may not view, use, disclose, copy or distribute this file or\n+ * any information contained herein except pursuant to this license grant from\n+ * Synopsys. If you do not agree with this notice, including the disclaimer\n+ * below, then you are not authorized to use the Software.\n+ *\n+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN \"AS IS\" BASIS\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,\n+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH\n+ * DAMAGE.\n+ * ========================================================================== */\n+\n+#ifndef __DWC_OTG_DRIVER_H__\n+#define __DWC_OTG_DRIVER_H__\n+\n+/** @file\n+ * This file contains the interface to the Linux driver.\n+ */\n+#include \"dwc_otg_os_dep.h\"\n+#include \"dwc_otg_core_if.h\"\n+\n+/* Type declarations */\n+struct dwc_otg_pcd;\n+struct dwc_otg_hcd;\n+\n+/**\n+ * This structure is a wrapper that encapsulates the driver components used to\n+ * manage a single DWC_otg controller.\n+ */\n+typedef struct dwc_otg_device {\n+\t/** Structure containing OS-dependent stuff. KEEP THIS STRUCT AT THE\n+\t * VERY BEGINNING OF THE DEVICE STRUCT. OSes such as FreeBSD and NetBSD\n+\t * require this. */\n+\tstruct os_dependent os_dep;\n+\n+\t/** Pointer to the core interface structure. */\n+\tdwc_otg_core_if_t *core_if;\n+\n+\t/** Pointer to the PCD structure. */\n+\tstruct dwc_otg_pcd *pcd;\n+\n+\t/** Pointer to the HCD structure. */\n+\tstruct dwc_otg_hcd *hcd;\n+\n+\t/** Flag to indicate whether the common IRQ handler is installed. */\n+\tuint8_t common_irq_installed;\n+\n+} dwc_otg_device_t;\n+\n+/*We must clear S3C24XX_EINTPEND external interrupt register\n+ * because after clearing in this register trigerred IRQ from\n+ * H/W core in kernel interrupt can be occured again before OTG\n+ * handlers clear all IRQ sources of Core registers because of\n+ * timing latencies and Low Level IRQ Type.\n+ */\n+#ifdef CONFIG_MACH_IPMATE\n+#define  S3C2410X_CLEAR_EINTPEND()   \\\n+do { \\\n+\t__raw_writel(1UL << 11,S3C24XX_EINTPEND); \\\n+} while (0)\n+#else\n+#define  S3C2410X_CLEAR_EINTPEND()   do { } while (0)\n+#endif\n+\n+#endif\n--- /dev/null\n+++ b/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c\n@@ -0,0 +1,1431 @@\n+/*\n+ * dwc_otg_fiq_fsm.c - The finite state machine FIQ\n+ *\n+ * Copyright (c) 2013 Raspberry Pi Foundation\n+ *\n+ * Author: Jonathan Bell <jonathan@raspberrypi.org>\n+ * All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions are met:\n+ *\t* Redistributions of source code must retain the above copyright\n+ *\t  notice, this list of conditions and the following disclaimer.\n+ *\t* Redistributions in binary form must reproduce the above copyright\n+ *\t  notice, this list of conditions and the following disclaimer in the\n+ *\t  documentation and/or other materials provided with the distribution.\n+ *\t* Neither the name of Raspberry Pi nor the\n+ *\t  names of its contributors may be used to endorse or promote products\n+ *\t  derived from this software without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" AND\n+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY\n+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\n+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ * This FIQ implements functionality that performs split transactions on\n+ * the dwc_otg hardware without any outside intervention. A split transaction\n+ * is \"queued\" by nominating a specific host channel to perform the entirety\n+ * of a split transaction. This FIQ will then perform the microframe-precise\n+ * scheduling required in each phase of the transaction until completion.\n+ *\n+ * The FIQ functionality is glued into the Synopsys driver via the entry point\n+ * in the FSM enqueue function, and at the exit point in handling a HC interrupt\n+ * for a FSM-enabled channel.\n+ *\n+ * NB: Large parts of this implementation have architecture-specific code.\n+ * For porting this functionality to other ARM machines, the minimum is required:\n+ * - An interrupt controller allowing the top-level dwc USB interrupt to be routed\n+ *   to the FIQ\n+ * - A method of forcing a software generated interrupt from FIQ mode that then\n+ *   triggers an IRQ entry (with the dwc USB handler called by this IRQ number)\n+ * - Guaranteed interrupt routing such that both the FIQ and SGI occur on the same\n+ *   processor core - there is no locking between the FIQ and IRQ (aside from\n+ *   local_fiq_disable)\n+ *\n+ */\n+\n+#include \"dwc_otg_fiq_fsm.h\"\n+\n+\n+char buffer[1000*16];\n+int wptr;\n+void notrace _fiq_print(enum fiq_debug_level dbg_lvl, volatile struct fiq_state *state, char *fmt, ...)\n+{\n+\tenum fiq_debug_level dbg_lvl_req = FIQDBG_ERR;\n+\tva_list args;\n+\tchar text[17];\n+\thfnum_data_t hfnum = { .d32 = FIQ_READ(state->dwc_regs_base + 0x408) };\n+\n+\tif((dbg_lvl & dbg_lvl_req) || dbg_lvl == FIQDBG_ERR)\n+\t{\n+\t\tsnprintf(text, 9, \" %4d:%1u  \", hfnum.b.frnum/8, hfnum.b.frnum & 7);\n+\t\tva_start(args, fmt);\n+\t\tvsnprintf(text+8, 9, fmt, args);\n+\t\tva_end(args);\n+\n+\t\tmemcpy(buffer + wptr, text, 16);\n+\t\twptr = (wptr + 16) % sizeof(buffer);\n+\t}\n+}\n+\n+\n+#ifdef CONFIG_ARM64\n+\n+inline void fiq_fsm_spin_lock(fiq_lock_t *lock)\n+{\n+\tspin_lock((spinlock_t *)lock);\n+}\n+\n+inline void fiq_fsm_spin_unlock(fiq_lock_t *lock)\n+{\n+\tspin_unlock((spinlock_t *)lock);\n+}\n+\n+#else\n+\n+/**\n+ * fiq_fsm_spin_lock() - ARMv6+ bare bones spinlock\n+ * Must be called with local interrupts and FIQ disabled.\n+ */\n+#if defined(CONFIG_ARCH_BCM2835) && defined(CONFIG_SMP)\n+inline void fiq_fsm_spin_lock(fiq_lock_t *lock)\n+{\n+\tunsigned long tmp;\n+\tuint32_t newval;\n+\tfiq_lock_t lockval;\n+\t/* Nested locking, yay. If we are on the same CPU as the fiq, then the disable\n+\t * will be sufficient. If we are on a different CPU, then the lock protects us. */\n+\tprefetchw(&lock->slock);\n+\tasm volatile (\n+\t\"1:     ldrex   %0, [%3]\\n\"\n+\t\"       add     %1, %0, %4\\n\"\n+\t\"       strex   %2, %1, [%3]\\n\"\n+\t\"       teq     %2, #0\\n\"\n+\t\"       bne     1b\"\n+\t: \"=&r\" (lockval), \"=&r\" (newval), \"=&r\" (tmp)\n+\t: \"r\" (&lock->slock), \"I\" (1 << 16)\n+\t: \"cc\");\n+\n+\twhile (lockval.tickets.next != lockval.tickets.owner) {\n+\t\twfe();\n+\t\tlockval.tickets.owner = READ_ONCE(lock->tickets.owner);\n+\t}\n+\tsmp_mb();\n+}\n+#else\n+inline void fiq_fsm_spin_lock(fiq_lock_t *lock) { }\n+#endif\n+\n+/**\n+ * fiq_fsm_spin_unlock() - ARMv6+ bare bones spinunlock\n+ */\n+#if defined(CONFIG_ARCH_BCM2835) && defined(CONFIG_SMP)\n+inline void fiq_fsm_spin_unlock(fiq_lock_t *lock)\n+{\n+\tsmp_mb();\n+\tlock->tickets.owner++;\n+\tdsb_sev();\n+}\n+#else\n+inline void fiq_fsm_spin_unlock(fiq_lock_t *lock) { }\n+#endif\n+\n+#endif\n+\n+/**\n+ * fiq_fsm_restart_channel() - Poke channel enable bit for a split transaction\n+ * @channel: channel to re-enable\n+ */\n+static void fiq_fsm_restart_channel(struct fiq_state *st, int n, int force)\n+{\n+\thcchar_data_t hcchar = { .d32 = FIQ_READ(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR) };\n+\n+\thcchar.b.chen = 0;\n+\tif (st->channel[n].hcchar_copy.b.eptype & 0x1) {\n+\t\thfnum_data_t hfnum = { .d32 = FIQ_READ(st->dwc_regs_base + HFNUM) };\n+\t\t/* Hardware bug workaround: update the ssplit index */\n+\t\tif (st->channel[n].hcsplt_copy.b.spltena)\n+\t\t\tst->channel[n].expected_uframe = (hfnum.b.frnum + 1) & 0x3FFF;\n+\n+\t\thcchar.b.oddfrm = (hfnum.b.frnum & 0x1) ? 0\t: 1;\n+\t}\n+\n+\tFIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR, hcchar.d32);\n+\thcchar.d32 = FIQ_READ(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR);\n+\thcchar.b.chen = 1;\n+\n+\tFIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR, hcchar.d32);\n+\tfiq_print(FIQDBG_INT, st, \"HCGO %01d %01d\", n, force);\n+}\n+\n+/**\n+ * fiq_fsm_setup_csplit() - Prepare a host channel for a CSplit transaction stage\n+ * @st: Pointer to the channel's state\n+ * @n : channel number\n+ *\n+ * Change host channel registers to perform a complete-split transaction. Being mindful of the\n+ * endpoint direction, set control regs up correctly.\n+ */\n+static void notrace fiq_fsm_setup_csplit(struct fiq_state *st, int n)\n+{\n+\thcsplt_data_t hcsplt = { .d32 = FIQ_READ(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCSPLT) };\n+\thctsiz_data_t hctsiz = { .d32 = FIQ_READ(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCTSIZ) };\n+\n+\thcsplt.b.compsplt = 1;\n+\tif (st->channel[n].hcchar_copy.b.epdir == 1) {\n+\t\t// If IN, the CSPLIT result contains the data or a hub handshake. hctsiz = maxpacket.\n+\t\thctsiz.b.xfersize = st->channel[n].hctsiz_copy.b.xfersize;\n+\t} else {\n+\t\t// If OUT, the CSPLIT result contains handshake only.\n+\t\thctsiz.b.xfersize = 0;\n+\t}\n+\tFIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCSPLT, hcsplt.d32);\n+\tFIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCTSIZ, hctsiz.d32);\n+\tmb();\n+}\n+\n+/**\n+ * fiq_fsm_restart_np_pending() - Restart a single non-periodic contended transfer\n+ * @st: Pointer to the channel's state\n+ * @num_channels: Total number of host channels\n+ * @orig_channel: Channel index of completed transfer\n+ *\n+ * In the case where an IN and OUT transfer are simultaneously scheduled to the\n+ * same device/EP, inadequate hub implementations will misbehave. Once the first\n+ * transfer is complete, a pending non-periodic split can then be issued.\n+ */\n+static void notrace fiq_fsm_restart_np_pending(struct fiq_state *st, int num_channels, int orig_channel)\n+{\n+\tint i;\n+\tint dev_addr = st->channel[orig_channel].hcchar_copy.b.devaddr;\n+\tint ep_num = st->channel[orig_channel].hcchar_copy.b.epnum;\n+\tfor (i = 0; i < num_channels; i++) {\n+\t\tif (st->channel[i].fsm == FIQ_NP_SSPLIT_PENDING &&\n+\t\t\tst->channel[i].hcchar_copy.b.devaddr == dev_addr &&\n+\t\t\tst->channel[i].hcchar_copy.b.epnum == ep_num) {\n+\t\t\tst->channel[i].fsm = FIQ_NP_SSPLIT_STARTED;\n+\t\t\tfiq_fsm_restart_channel(st, i, 0);\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+}\n+\n+static inline int notrace fiq_get_xfer_len(struct fiq_state *st, int n)\n+{\n+\t/* The xfersize register is a bit wonky. For IN transfers, it decrements by the packet size. */\n+\thctsiz_data_t hctsiz = { .d32 = FIQ_READ(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCTSIZ) };\n+\n+\tif (st->channel[n].hcchar_copy.b.epdir == 0) {\n+\t\treturn st->channel[n].hctsiz_copy.b.xfersize;\n+\t} else {\n+\t\treturn st->channel[n].hctsiz_copy.b.xfersize - hctsiz.b.xfersize;\n+\t}\n+\n+}\n+\n+\n+/**\n+ * fiq_increment_dma_buf() - update DMA address for bounce buffers after a CSPLIT\n+ *\n+ * Of use only for IN periodic transfers.\n+ */\n+static int notrace fiq_increment_dma_buf(struct fiq_state *st, int num_channels, int n)\n+{\n+\thcdma_data_t hcdma;\n+\tint i = st->channel[n].dma_info.index;\n+\tint len;\n+\tstruct fiq_dma_blob *blob = (struct fiq_dma_blob *) st->dma_base;\n+\n+\tlen = fiq_get_xfer_len(st, n);\n+\tfiq_print(FIQDBG_INT, st, \"LEN: %03d\", len);\n+\tst->channel[n].dma_info.slot_len[i] = len;\n+\ti++;\n+\tif (i > 6)\n+\t\tBUG();\n+\n+\thcdma.d32 = (dma_addr_t) &blob->channel[n].index[i].buf[0];\n+\tFIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HC_DMA, hcdma.d32);\n+\tst->channel[n].dma_info.index = i;\n+\treturn 0;\n+}\n+\n+/**\n+ * fiq_reload_hctsiz() - for IN transactions, reset HCTSIZ\n+ */\n+static void notrace fiq_fsm_reload_hctsiz(struct fiq_state *st, int n)\n+{\n+\thctsiz_data_t hctsiz = { .d32 = FIQ_READ(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCTSIZ) };\n+\thctsiz.b.xfersize = st->channel[n].hctsiz_copy.b.xfersize;\n+\thctsiz.b.pktcnt = 1;\n+\tFIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCTSIZ, hctsiz.d32);\n+}\n+\n+/**\n+ * fiq_fsm_reload_hcdma() - for OUT transactions, rewind DMA pointer\n+ */\n+static void notrace fiq_fsm_reload_hcdma(struct fiq_state *st, int n)\n+{\n+\thcdma_data_t hcdma = st->channel[n].hcdma_copy;\n+\tFIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HC_DMA, hcdma.d32);\n+}\n+\n+/**\n+ * fiq_iso_out_advance() - update DMA address and split position bits\n+ * for isochronous OUT transactions.\n+ *\n+ * Returns 1 if this is the last packet queued, 0 otherwise. Split-ALL and\n+ * Split-BEGIN states are not handled - this is done when the transaction was queued.\n+ *\n+ * This function must only be called from the FIQ_ISO_OUT_ACTIVE state.\n+ */\n+static int notrace fiq_iso_out_advance(struct fiq_state *st, int num_channels, int n)\n+{\n+\thcsplt_data_t hcsplt;\n+\thctsiz_data_t hctsiz;\n+\thcdma_data_t hcdma;\n+\tstruct fiq_dma_blob *blob = (struct fiq_dma_blob *) st->dma_base;\n+\tint last = 0;\n+\tint i = st->channel[n].dma_info.index;\n+\n+\tfiq_print(FIQDBG_INT, st, \"ADV %01d %01d \", n, i);\n+\ti++;\n+\tif (i == 4)\n+\t\tlast = 1;\n+\tif (st->channel[n].dma_info.slot_len[i+1] == 255)\n+\t\tlast = 1;\n+\n+\t/* New DMA address - address of bounce buffer referred to in index */\n+\thcdma.d32 = (dma_addr_t) blob->channel[n].index[i].buf;\n+\t//hcdma.d32 = FIQ_READ(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HC_DMA);\n+\t//hcdma.d32 += st->channel[n].dma_info.slot_len[i];\n+\tfiq_print(FIQDBG_INT, st, \"LAST: %01d \", last);\n+\tfiq_print(FIQDBG_INT, st, \"LEN: %03d\", st->channel[n].dma_info.slot_len[i]);\n+\thcsplt.d32 = FIQ_READ(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCSPLT);\n+\thctsiz.d32 = FIQ_READ(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCTSIZ);\n+\thcsplt.b.xactpos = (last) ? ISOC_XACTPOS_END : ISOC_XACTPOS_MID;\n+\t/* Set up new packet length */\n+\thctsiz.b.pktcnt = 1;\n+\thctsiz.b.xfersize = st->channel[n].dma_info.slot_len[i];\n+\tfiq_print(FIQDBG_INT, st, \"%08x\", hctsiz.d32);\n+\n+\tst->channel[n].dma_info.index++;\n+\tFIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCSPLT, hcsplt.d32);\n+\tFIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCTSIZ, hctsiz.d32);\n+\tFIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HC_DMA, hcdma.d32);\n+\treturn last;\n+}\n+\n+/**\n+ * fiq_fsm_tt_next_isoc() - queue next pending isochronous out start-split on a TT\n+ *\n+ * Despite the limitations of the DWC core, we can force a microframe pipeline of\n+ * isochronous OUT start-split transactions while waiting for a corresponding other-type\n+ * of endpoint to finish its CSPLITs. TTs have big periodic buffers therefore it\n+ * is very unlikely that filling the start-split FIFO will cause data loss.\n+ * This allows much better interleaving of transactions in an order-independent way-\n+ * there is no requirement to prioritise isochronous, just a state-space search has\n+ * to be performed on each periodic start-split complete interrupt.\n+ */\n+static int notrace fiq_fsm_tt_next_isoc(struct fiq_state *st, int num_channels, int n)\n+{\n+\tint hub_addr = st->channel[n].hub_addr;\n+\tint port_addr = st->channel[n].port_addr;\n+\tint i, poked = 0;\n+\tfor (i = 0; i < num_channels; i++) {\n+\t\tif (i == n || st->channel[i].fsm == FIQ_PASSTHROUGH)\n+\t\t\tcontinue;\n+\t\tif (st->channel[i].hub_addr == hub_addr &&\n+\t\t\tst->channel[i].port_addr == port_addr) {\n+\t\t\tswitch (st->channel[i].fsm) {\n+\t\t\tcase FIQ_PER_ISO_OUT_PENDING:\n+\t\t\t\tif (st->channel[i].nrpackets == 1) {\n+\t\t\t\t\tst->channel[i].fsm = FIQ_PER_ISO_OUT_LAST;\n+\t\t\t\t} else {\n+\t\t\t\t\tst->channel[i].fsm = FIQ_PER_ISO_OUT_ACTIVE;\n+\t\t\t\t}\n+\t\t\t\tfiq_fsm_restart_channel(st, i, 0);\n+\t\t\t\tpoked = 1;\n+\t\t\t\tbreak;\n+\n+\t\t\tdefault:\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t}\n+\t\tif (poked)\n+\t\t\tbreak;\n+\t}\n+\treturn poked;\n+}\n+\n+/**\n+ * fiq_fsm_tt_in_use() - search for host channels using this TT\n+ * @n: Channel to use as reference\n+ *\n+ */\n+int notrace noinline fiq_fsm_tt_in_use(struct fiq_state *st, int num_channels, int n)\n+{\n+\tint hub_addr = st->channel[n].hub_addr;\n+\tint port_addr = st->channel[n].port_addr;\n+\tint i, in_use = 0;\n+\tfor (i = 0; i < num_channels; i++) {\n+\t\tif (i == n || st->channel[i].fsm == FIQ_PASSTHROUGH)\n+\t\t\tcontinue;\n+\t\tswitch (st->channel[i].fsm) {\n+\t\t/* TT is reserved for channels that are in the middle of a periodic\n+\t\t * split transaction.\n+\t\t */\n+\t\tcase FIQ_PER_SSPLIT_STARTED:\n+\t\tcase FIQ_PER_CSPLIT_WAIT:\n+\t\tcase FIQ_PER_CSPLIT_NYET1:\n+\t\t//case FIQ_PER_CSPLIT_POLL:\n+\t\tcase FIQ_PER_ISO_OUT_ACTIVE:\n+\t\tcase FIQ_PER_ISO_OUT_LAST:\n+\t\t\tif (st->channel[i].hub_addr == hub_addr &&\n+\t\t\t\tst->channel[i].port_addr == port_addr) {\n+\t\t\t\tin_use = 1;\n+\t\t\t}\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tbreak;\n+\t\t}\n+\t\tif (in_use)\n+\t\t\tbreak;\n+\t}\n+\treturn in_use;\n+}\n+\n+/**\n+ * fiq_fsm_more_csplits() - determine whether additional CSPLITs need\n+ * \t\t\tto be issued for this IN transaction.\n+ *\n+ * We cannot tell the inbound PID of a data packet due to hardware limitations.\n+ * we need to make an educated guess as to whether we need to queue another CSPLIT\n+ * or not. A no-brainer is when we have received enough data to fill the endpoint\n+ * size, but for endpoints that give variable-length data then we have to resort\n+ * to heuristics.\n+ *\n+ * We also return whether this is the last CSPLIT to be queued, again based on\n+ * heuristics. This is to allow a 1-uframe overlap of periodic split transactions.\n+ * Note: requires at least 1 CSPLIT to have been performed prior to being called.\n+ */\n+\n+/*\n+ * We need some way of guaranteeing if a returned periodic packet of size X\n+ * has a DATA0 PID.\n+ * The heuristic value of 144 bytes assumes that the received data has maximal\n+ * bit-stuffing and the clock frequency of the transmitting device is at the lowest\n+ * permissible limit. If the transfer length results in a final packet size\n+ * 144 < p <= 188, then an erroneous CSPLIT will be issued.\n+ * Also used to ensure that an endpoint will nominally only return a single\n+ * complete-split worth of data.\n+ */\n+#define DATA0_PID_HEURISTIC 144\n+\n+static int notrace noinline fiq_fsm_more_csplits(struct fiq_state *state, int n, int *probably_last)\n+{\n+\n+\tint i;\n+\tint total_len = 0;\n+\tint more_needed = 1;\n+\tstruct fiq_channel_state *st = &state->channel[n];\n+\n+\tfor (i = 0; i < st->dma_info.index; i++) {\n+\t\t\ttotal_len += st->dma_info.slot_len[i];\n+\t}\n+\n+\t*probably_last = 0;\n+\n+\tif (st->hcchar_copy.b.eptype == 0x3) {\n+\t\t/*\n+\t\t * An interrupt endpoint will take max 2 CSPLITs. if we are receiving data\n+\t\t * then this is definitely the last CSPLIT.\n+\t\t */\n+\t\t*probably_last = 1;\n+\t} else {\n+\t\t/* Isoc IN. This is a bit risky if we are the first transaction:\n+\t\t * we may have been held off slightly. */\n+\t\tif (i > 1 && st->dma_info.slot_len[st->dma_info.index-1] <= DATA0_PID_HEURISTIC) {\n+\t\t\tmore_needed = 0;\n+\t\t}\n+\t\t/* If in the next uframe we will receive enough data to fill the endpoint,\n+\t\t * then only issue 1 more csplit.\n+\t\t */\n+\t\tif (st->hctsiz_copy.b.xfersize - total_len <= DATA0_PID_HEURISTIC)\n+\t\t\t*probably_last = 1;\n+\t}\n+\n+\tif (total_len >= st->hctsiz_copy.b.xfersize ||\n+\t\ti == 6 || total_len == 0)\n+\t\t/* Note: due to bit stuffing it is possible to have > 6 CSPLITs for\n+\t\t * a single endpoint. Accepting more would completely break our scheduling mechanism though\n+\t\t * - in these extreme cases we will pass through a truncated packet.\n+\t\t */\n+\t\tmore_needed = 0;\n+\n+\treturn more_needed;\n+}\n+\n+/**\n+ * fiq_fsm_too_late() - Test transaction for lateness\n+ *\n+ * If a SSPLIT for a large IN transaction is issued too late in a frame,\n+ * the hub will disable the port to the device and respond with ERR handshakes.\n+ * The hub status endpoint will not reflect this change.\n+ * Returns 1 if we will issue a SSPLIT that will result in a device babble.\n+ */\n+int notrace fiq_fsm_too_late(struct fiq_state *st, int n)\n+{\n+\tint uframe;\n+\thfnum_data_t hfnum = { .d32 = FIQ_READ(st->dwc_regs_base + HFNUM) };\n+\tuframe = hfnum.b.frnum & 0x7;\n+\tif ((uframe < 6) && (st->channel[n].nrpackets + 1 + uframe > 7)) {\n+\t\treturn 1;\n+\t} else {\n+\t\treturn 0;\n+\t}\n+}\n+\n+\n+/**\n+ * fiq_fsm_start_next_periodic() - A half-arsed attempt at a microframe pipeline\n+ *\n+ * Search pending transactions in the start-split pending state and queue them.\n+ * Don't queue packets in uframe .5 (comes out in .6) (USB2.0 11.18.4).\n+ * Note: we specifically don't do isochronous OUT transactions first because better\n+ * use of the TT's start-split fifo can be achieved by pipelining an IN before an OUT.\n+ */\n+static void notrace noinline fiq_fsm_start_next_periodic(struct fiq_state *st, int num_channels)\n+{\n+\tint n;\n+\thfnum_data_t hfnum = { .d32 = FIQ_READ(st->dwc_regs_base + HFNUM) };\n+\tif ((hfnum.b.frnum & 0x7) == 5)\n+\t\treturn;\n+\tfor (n = 0; n < num_channels; n++) {\n+\t\tif (st->channel[n].fsm == FIQ_PER_SSPLIT_QUEUED) {\n+\t\t\t/* Check to see if any other transactions are using this TT */\n+\t\t\tif(!fiq_fsm_tt_in_use(st, num_channels, n)) {\n+\t\t\t\tif (!fiq_fsm_too_late(st, n)) {\n+\t\t\t\t\tst->channel[n].fsm = FIQ_PER_SSPLIT_STARTED;\n+\t\t\t\t\tfiq_print(FIQDBG_INT, st, \"NEXTPER \");\n+\t\t\t\t\tfiq_fsm_restart_channel(st, n, 0);\n+\t\t\t\t} else {\n+\t\t\t\t\tst->channel[n].fsm = FIQ_PER_SPLIT_TIMEOUT;\n+\t\t\t\t}\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t}\n+\t}\n+\tfor (n = 0; n < num_channels; n++) {\n+\t\tif (st->channel[n].fsm == FIQ_PER_ISO_OUT_PENDING) {\n+\t\t\tif (!fiq_fsm_tt_in_use(st, num_channels, n)) {\n+\t\t\t\tfiq_print(FIQDBG_INT, st, \"NEXTISO \");\n+\t\t\t\tif (st->channel[n].nrpackets == 1)\n+\t\t\t\t\tst->channel[n].fsm = FIQ_PER_ISO_OUT_LAST;\n+\t\t\t\telse\n+\t\t\t\t\tst->channel[n].fsm = FIQ_PER_ISO_OUT_ACTIVE;\n+\t\t\t\tfiq_fsm_restart_channel(st, n, 0);\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t}\n+\t}\n+}\n+\n+/**\n+ * fiq_fsm_update_hs_isoc() - update isochronous frame and transfer data\n+ * @state:\tPointer to fiq_state\n+ * @n:\t\tChannel transaction is active on\n+ * @hcint:\tCopy of host channel interrupt register\n+ *\n+ * Returns 0 if there are no more transactions for this HC to do, 1\n+ * otherwise.\n+ */\n+static int notrace noinline fiq_fsm_update_hs_isoc(struct fiq_state *state, int n, hcint_data_t hcint)\n+{\n+\tstruct fiq_channel_state *st = &state->channel[n];\n+\tint xfer_len = 0, nrpackets = 0;\n+\thcdma_data_t hcdma;\n+\tfiq_print(FIQDBG_INT, state, \"HSISO %02d\", n);\n+\n+\txfer_len = fiq_get_xfer_len(state, n);\n+\tst->hs_isoc_info.iso_desc[st->hs_isoc_info.index].actual_length = xfer_len;\n+\n+\tst->hs_isoc_info.iso_desc[st->hs_isoc_info.index].status = hcint.d32;\n+\n+\tst->hs_isoc_info.index++;\n+\tif (st->hs_isoc_info.index == st->hs_isoc_info.nrframes) {\n+\t\treturn 0;\n+\t}\n+\n+\t/* grab the next DMA address offset from the array */\n+\thcdma.d32 = st->hcdma_copy.d32 + st->hs_isoc_info.iso_desc[st->hs_isoc_info.index].offset;\n+\tFIQ_WRITE(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HC_DMA, hcdma.d32);\n+\n+\t/* We need to set multi_count. This is a bit tricky - has to be set per-transaction as\n+\t * the core needs to be told to send the correct number. Caution: for IN transfers,\n+\t * this is always set to the maximum size of the endpoint. */\n+\txfer_len = st->hs_isoc_info.iso_desc[st->hs_isoc_info.index].length;\n+\t/* Integer divide in a FIQ: fun. FIXME: make this not suck */\n+\tnrpackets = (xfer_len + st->hcchar_copy.b.mps - 1) / st->hcchar_copy.b.mps;\n+\tif (nrpackets == 0)\n+\t\tnrpackets = 1;\n+\tst->hcchar_copy.b.multicnt = nrpackets;\n+\tst->hctsiz_copy.b.pktcnt = nrpackets;\n+\n+\t/* Initial PID also needs to be set */\n+\tif (st->hcchar_copy.b.epdir == 0) {\n+\t\tst->hctsiz_copy.b.xfersize = xfer_len;\n+\t\tswitch (st->hcchar_copy.b.multicnt) {\n+\t\tcase 1:\n+\t\t\tst->hctsiz_copy.b.pid = DWC_PID_DATA0;\n+\t\t\tbreak;\n+\t\tcase 2:\n+\t\tcase 3:\n+\t\t\tst->hctsiz_copy.b.pid = DWC_PID_MDATA;\n+\t\t\tbreak;\n+\t\t}\n+\n+\t} else {\n+\t\tst->hctsiz_copy.b.xfersize = nrpackets * st->hcchar_copy.b.mps;\n+\t\tswitch (st->hcchar_copy.b.multicnt) {\n+\t\tcase 1:\n+\t\t\tst->hctsiz_copy.b.pid = DWC_PID_DATA0;\n+\t\t\tbreak;\n+\t\tcase 2:\n+\t\t\tst->hctsiz_copy.b.pid = DWC_PID_DATA1;\n+\t\t\tbreak;\n+\t\tcase 3:\n+\t\t\tst->hctsiz_copy.b.pid = DWC_PID_DATA2;\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\tFIQ_WRITE(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCTSIZ, st->hctsiz_copy.d32);\n+\tFIQ_WRITE(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR, st->hcchar_copy.d32);\n+\t/* Channel is enabled on hcint handler exit */\n+\tfiq_print(FIQDBG_INT, state, \"HSISOOUT\");\n+\treturn 1;\n+}\n+\n+\n+/**\n+ * fiq_fsm_do_sof() - FSM start-of-frame interrupt handler\n+ * @state:\tPointer to the state struct passed from banked FIQ mode registers.\n+ * @num_channels:\tset according to the DWC hardware configuration\n+ *\n+ * The SOF handler in FSM mode has two functions\n+ * 1. Hold off SOF from causing schedule advancement in IRQ context if there's\n+ *    nothing to do\n+ * 2. Advance certain FSM states that require either a microframe delay, or a microframe\n+ *    of holdoff.\n+ *\n+ * The second part is architecture-specific to mach-bcm2835 -\n+ * a sane interrupt controller would have a mask register for ARM interrupt sources\n+ * to be promoted to the nFIQ line, but it doesn't. Instead a single interrupt\n+ * number (USB) can be enabled. This means that certain parts of the USB specification\n+ * that require \"wait a little while, then issue another packet\" cannot be fulfilled with\n+ * the timing granularity required to achieve optimal throughout. The workaround is to use\n+ * the SOF \"timer\" (125uS) to perform this task.\n+ */\n+static int notrace noinline fiq_fsm_do_sof(struct fiq_state *state, int num_channels)\n+{\n+\thfnum_data_t hfnum = { .d32 = FIQ_READ(state->dwc_regs_base + HFNUM) };\n+\tint n;\n+\tint kick_irq = 0;\n+\n+\tif ((hfnum.b.frnum & 0x7) == 1) {\n+\t\t/* We cannot issue csplits for transactions in the last frame past (n+1).1\n+\t\t * Check to see if there are any transactions that are stale.\n+\t\t * Boot them out.\n+\t\t */\n+\t\tfor (n = 0; n < num_channels; n++) {\n+\t\t\tswitch (state->channel[n].fsm) {\n+\t\t\tcase FIQ_PER_CSPLIT_WAIT:\n+\t\t\tcase FIQ_PER_CSPLIT_NYET1:\n+\t\t\tcase FIQ_PER_CSPLIT_POLL:\n+\t\t\tcase FIQ_PER_CSPLIT_LAST:\n+\t\t\t\t/* Check if we are no longer in the same full-speed frame. */\n+\t\t\t\tif (((state->channel[n].expected_uframe & 0x3FFF) & ~0x7) <\n+\t\t\t\t\t\t(hfnum.b.frnum & ~0x7))\n+\t\t\t\t\tstate->channel[n].fsm = FIQ_PER_SPLIT_TIMEOUT;\n+\t\t\t\tbreak;\n+\t\t\tdefault:\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t}\n+\t}\n+\n+\tfor (n = 0; n < num_channels; n++) {\n+\t\tswitch (state->channel[n].fsm) {\n+\n+\t\tcase FIQ_NP_SSPLIT_RETRY:\n+\t\tcase FIQ_NP_IN_CSPLIT_RETRY:\n+\t\tcase FIQ_NP_OUT_CSPLIT_RETRY:\n+\t\t\tfiq_fsm_restart_channel(state, n, 0);\n+\t\t\tbreak;\n+\n+\t\tcase FIQ_HS_ISOC_SLEEPING:\n+\t\t\t/* Is it time to wake this channel yet? */\n+\t\t\tif (--state->channel[n].uframe_sleeps == 0) {\n+\t\t\t\tstate->channel[n].fsm = FIQ_HS_ISOC_TURBO;\n+\t\t\t\tfiq_fsm_restart_channel(state, n, 0);\n+\t\t\t}\n+\t\t\tbreak;\n+\n+\t\tcase FIQ_PER_SSPLIT_QUEUED:\n+\t\t\tif ((hfnum.b.frnum & 0x7) == 5)\n+\t\t\t\tbreak;\n+\t\t\tif(!fiq_fsm_tt_in_use(state, num_channels, n)) {\n+\t\t\t\tif (!fiq_fsm_too_late(state, n)) {\n+\t\t\t\t\tfiq_print(FIQDBG_INT, state, \"SOF GO %01d\", n);\n+\t\t\t\t\tfiq_fsm_restart_channel(state, n, 0);\n+\t\t\t\t\tstate->channel[n].fsm = FIQ_PER_SSPLIT_STARTED;\n+\t\t\t\t} else {\n+\t\t\t\t\t/* Transaction cannot be started without risking a device babble error */\n+\t\t\t\t\tstate->channel[n].fsm = FIQ_PER_SPLIT_TIMEOUT;\n+\t\t\t\t\tstate->haintmsk_saved.b2.chint &= ~(1 << n);\n+\t\t\t\t\tFIQ_WRITE(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCINTMSK, 0);\n+\t\t\t\t\tkick_irq |= 1;\n+\t\t\t\t}\n+\t\t\t}\n+\t\t\tbreak;\n+\n+\t\tcase FIQ_PER_ISO_OUT_PENDING:\n+\t\t\t/* Ordinarily, this should be poked after the SSPLIT\n+\t\t\t * complete interrupt for a competing transfer on the same\n+\t\t\t * TT. Doesn't happen for aborted transactions though.\n+\t\t\t */\n+\t\t\tif ((hfnum.b.frnum & 0x7) >= 5)\n+\t\t\t\tbreak;\n+\t\t\tif (!fiq_fsm_tt_in_use(state, num_channels, n)) {\n+\t\t\t\t/* Hardware bug. SOF can sometimes occur after the channel halt interrupt\n+\t\t\t\t * that caused this.\n+\t\t\t\t */\n+\t\t\t\t\tfiq_fsm_restart_channel(state, n, 0);\n+\t\t\t\t\tfiq_print(FIQDBG_INT, state, \"SOF ISOC\");\n+\t\t\t\t\tif (state->channel[n].nrpackets == 1) {\n+\t\t\t\t\t\tstate->channel[n].fsm = FIQ_PER_ISO_OUT_LAST;\n+\t\t\t\t\t} else {\n+\t\t\t\t\t\tstate->channel[n].fsm = FIQ_PER_ISO_OUT_ACTIVE;\n+\t\t\t\t\t}\n+\t\t\t}\n+\t\t\tbreak;\n+\n+\t\tcase FIQ_PER_CSPLIT_WAIT:\n+\t\t\t/* we are guaranteed to be in this state if and only if the SSPLIT interrupt\n+\t\t\t * occurred when the bus transaction occurred. The SOF interrupt reversal bug\n+\t\t\t * will utterly bugger this up though.\n+\t\t\t */\n+\t\t\tif (hfnum.b.frnum != state->channel[n].expected_uframe) {\n+\t\t\t\tfiq_print(FIQDBG_INT, state, \"SOFCS %d \", n);\n+\t\t\t\tstate->channel[n].fsm = FIQ_PER_CSPLIT_POLL;\n+\t\t\t\tfiq_fsm_restart_channel(state, n, 0);\n+\t\t\t\tfiq_fsm_start_next_periodic(state, num_channels);\n+\n+\t\t\t}\n+\t\t\tbreak;\n+\n+\t\tcase FIQ_PER_SPLIT_TIMEOUT:\n+\t\tcase FIQ_DEQUEUE_ISSUED:\n+\t\t\t/* Ugly: we have to force a HCD interrupt.\n+\t\t\t * Poke the mask for the channel in question.\n+\t\t\t * We will take a fake SOF because of this, but\n+\t\t\t * that's OK.\n+\t\t\t */\n+\t\t\tstate->haintmsk_saved.b2.chint &= ~(1 << n);\n+\t\t\tFIQ_WRITE(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCINTMSK, 0);\n+\t\t\tkick_irq |= 1;\n+\t\t\tbreak;\n+\n+\t\tdefault:\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\n+\tif (state->kick_np_queues ||\n+\t\t\tdwc_frame_num_le(state->next_sched_frame, hfnum.b.frnum))\n+\t\tkick_irq |= 1;\n+\n+\treturn !kick_irq;\n+}\n+\n+\n+/**\n+ * fiq_fsm_do_hcintr() - FSM host channel interrupt handler\n+ * @state: Pointer to the FIQ state struct\n+ * @num_channels: Number of channels as per hardware config\n+ * @n: channel for which HAINT(i) was raised\n+ *\n+ * An important property is that only the CHHLT interrupt is unmasked. Unfortunately, AHBerr is as well.\n+ */\n+static int notrace noinline fiq_fsm_do_hcintr(struct fiq_state *state, int num_channels, int n)\n+{\n+\thcint_data_t hcint;\n+\thcintmsk_data_t hcintmsk;\n+\thcint_data_t hcint_probe;\n+\thcchar_data_t hcchar;\n+\tint handled = 0;\n+\tint restart = 0;\n+\tint last_csplit = 0;\n+\tint start_next_periodic = 0;\n+\tstruct fiq_channel_state *st = &state->channel[n];\n+\thfnum_data_t hfnum;\n+\n+\thcint.d32 = FIQ_READ(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCINT);\n+\thcintmsk.d32 = FIQ_READ(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCINTMSK);\n+\thcint_probe.d32 = hcint.d32 & hcintmsk.d32;\n+\n+\tif (st->fsm != FIQ_PASSTHROUGH) {\n+\t\tfiq_print(FIQDBG_INT, state, \"HC%01d ST%02d\", n, st->fsm);\n+\t\tfiq_print(FIQDBG_INT, state, \"%08x\", hcint.d32);\n+\t}\n+\n+\tswitch (st->fsm) {\n+\n+\tcase FIQ_PASSTHROUGH:\n+\tcase FIQ_DEQUEUE_ISSUED:\n+\t\t/* doesn't belong to us, kick it upstairs */\n+\t\tbreak;\n+\n+\tcase FIQ_PASSTHROUGH_ERRORSTATE:\n+\t\t/* We are here to emulate the error recovery mechanism of the dwc HCD.\n+\t\t * Several interrupts are unmasked if a previous transaction failed - it's\n+\t\t * death for the FIQ to attempt to handle them as the channel isn't halted.\n+\t\t * Emulate what the HCD does in this situation: mask and continue.\n+\t\t * The FSM has no other state setup so this has to be handled out-of-band.\n+\t\t */\n+\t\tfiq_print(FIQDBG_ERR, state, \"ERRST %02d\", n);\n+\t\tif (hcint_probe.b.nak || hcint_probe.b.ack || hcint_probe.b.datatglerr) {\n+\t\t\tfiq_print(FIQDBG_ERR, state, \"RESET %02d\", n);\n+\t\t\t/* In some random cases we can get a NAK interrupt coincident with a Xacterr\n+\t\t\t * interrupt, after the device has disappeared.\n+\t\t\t */\n+\t\t\tif (!hcint.b.xacterr)\n+\t\t\t\tst->nr_errors = 0;\n+\t\t\thcintmsk.b.nak = 0;\n+\t\t\thcintmsk.b.ack = 0;\n+\t\t\thcintmsk.b.datatglerr = 0;\n+\t\t\tFIQ_WRITE(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCINTMSK, hcintmsk.d32);\n+\t\t\treturn 1;\n+\t\t}\n+\t\tif (hcint_probe.b.chhltd) {\n+\t\t\tfiq_print(FIQDBG_ERR, state, \"CHHLT %02d\", n);\n+\t\t\tfiq_print(FIQDBG_ERR, state, \"%08x\", hcint.d32);\n+\t\t\treturn 0;\n+\t\t}\n+\t\tbreak;\n+\n+\t/* Non-periodic state groups */\n+\tcase FIQ_NP_SSPLIT_STARTED:\n+\tcase FIQ_NP_SSPLIT_RETRY:\n+\t\t/* Got a HCINT for a NP SSPLIT. Expected ACK / NAK / fail */\n+\t\tif (hcint.b.ack) {\n+\t\t\t/* SSPLIT complete. For OUT, the data has been sent. For IN, the LS transaction\n+\t\t\t * will start shortly. SOF needs to kick the transaction to prevent a NYET flood.\n+\t\t\t */\n+\t\t\tif(st->hcchar_copy.b.epdir == 1)\n+\t\t\t\tst->fsm = FIQ_NP_IN_CSPLIT_RETRY;\n+\t\t\telse\n+\t\t\t\tst->fsm = FIQ_NP_OUT_CSPLIT_RETRY;\n+\t\t\tst->nr_errors = 0;\n+\t\t\thandled = 1;\n+\t\t\tfiq_fsm_setup_csplit(state, n);\n+\t\t} else if (hcint.b.nak) {\n+\t\t\t// No buffer space in TT. Retry on a uframe boundary.\n+\t\t\tfiq_fsm_reload_hcdma(state, n);\n+\t\t\tst->fsm = FIQ_NP_SSPLIT_RETRY;\n+\t\t\thandled = 1;\n+\t\t} else if (hcint.b.xacterr) {\n+\t\t\t// The only other one we care about is xacterr. This implies HS bus error - retry.\n+\t\t\tst->nr_errors++;\n+\t\t\tif(st->hcchar_copy.b.epdir == 0)\n+\t\t\t\tfiq_fsm_reload_hcdma(state, n);\n+\t\t\tst->fsm = FIQ_NP_SSPLIT_RETRY;\n+\t\t\tif (st->nr_errors >= 3) {\n+\t\t\t\tst->fsm = FIQ_NP_SPLIT_HS_ABORTED;\n+\t\t\t} else {\n+\t\t\t\thandled = 1;\n+\t\t\t\trestart = 1;\n+\t\t\t}\n+\t\t} else {\n+\t\t\tst->fsm = FIQ_NP_SPLIT_LS_ABORTED;\n+\t\t\thandled = 0;\n+\t\t\trestart = 0;\n+\t\t}\n+\t\tbreak;\n+\n+\tcase FIQ_NP_IN_CSPLIT_RETRY:\n+\t\t/* Received a CSPLIT done interrupt.\n+\t\t * Expected Data/NAK/STALL/NYET for IN.\n+\t\t */\n+\t\tif (hcint.b.xfercomp) {\n+\t\t\t/* For IN, data is present. */\n+\t\t\tst->fsm = FIQ_NP_SPLIT_DONE;\n+\t\t} else if (hcint.b.nak) {\n+\t\t\t/* no endpoint data. Punt it upstairs */\n+\t\t\tst->fsm = FIQ_NP_SPLIT_DONE;\n+\t\t} else if (hcint.b.nyet) {\n+\t\t\t/* CSPLIT NYET - retry on a uframe boundary. */\n+\t\t\thandled = 1;\n+\t\t\tst->nr_errors = 0;\n+\t\t} else if (hcint.b.datatglerr) {\n+\t\t\t/* data toggle errors do not set the xfercomp bit. */\n+\t\t\tst->fsm = FIQ_NP_SPLIT_LS_ABORTED;\n+\t\t} else if (hcint.b.xacterr) {\n+\t\t\t/* HS error. Retry immediate */\n+\t\t\tst->fsm = FIQ_NP_IN_CSPLIT_RETRY;\n+\t\t\tst->nr_errors++;\n+\t\t\tif (st->nr_errors >= 3) {\n+\t\t\t\tst->fsm = FIQ_NP_SPLIT_HS_ABORTED;\n+\t\t\t} else {\n+\t\t\t\thandled = 1;\n+\t\t\t\trestart = 1;\n+\t\t\t}\n+\t\t} else if (hcint.b.stall || hcint.b.bblerr) {\n+\t\t\t/* A STALL implies either a LS bus error or a genuine STALL. */\n+\t\t\tst->fsm = FIQ_NP_SPLIT_LS_ABORTED;\n+\t\t} else {\n+\t\t\t/*  Hardware bug. It's possible in some cases to\n+\t\t\t *  get a channel halt with nothing else set when\n+\t\t\t *  the response was a NYET. Treat as local 3-strikes retry.\n+\t\t\t */\n+\t\t\thcint_data_t hcint_test = hcint;\n+\t\t\thcint_test.b.chhltd = 0;\n+\t\t\tif (!hcint_test.d32) {\n+\t\t\t\tst->nr_errors++;\n+\t\t\t\tif (st->nr_errors >= 3) {\n+\t\t\t\t\tst->fsm = FIQ_NP_SPLIT_HS_ABORTED;\n+\t\t\t\t} else {\n+\t\t\t\t\thandled = 1;\n+\t\t\t\t}\n+\t\t\t} else {\n+\t\t\t\t/* Bail out if something unexpected happened */\n+\t\t\t\tst->fsm = FIQ_NP_SPLIT_HS_ABORTED;\n+\t\t\t}\n+\t\t}\n+\t\tif (st->fsm != FIQ_NP_IN_CSPLIT_RETRY) {\n+\t\t\tfiq_fsm_restart_np_pending(state, num_channels, n);\n+\t\t}\n+\t\tbreak;\n+\n+\tcase FIQ_NP_OUT_CSPLIT_RETRY:\n+\t\t/* Received a CSPLIT done interrupt.\n+\t\t * Expected ACK/NAK/STALL/NYET/XFERCOMP for OUT.*/\n+\t\tif (hcint.b.xfercomp) {\n+\t\t\tst->fsm = FIQ_NP_SPLIT_DONE;\n+\t\t} else if (hcint.b.nak) {\n+\t\t\t// The HCD will implement the holdoff on frame boundaries.\n+\t\t\tst->fsm = FIQ_NP_SPLIT_DONE;\n+\t\t} else if (hcint.b.nyet) {\n+\t\t\t// Hub still processing.\n+\t\t\tst->fsm = FIQ_NP_OUT_CSPLIT_RETRY;\n+\t\t\thandled = 1;\n+\t\t\tst->nr_errors = 0;\n+\t\t\t//restart = 1;\n+\t\t} else if (hcint.b.xacterr) {\n+\t\t\t/* HS error. retry immediate */\n+\t\t\tst->fsm = FIQ_NP_OUT_CSPLIT_RETRY;\n+\t\t\tst->nr_errors++;\n+\t\t\tif (st->nr_errors >= 3) {\n+\t\t\t\tst->fsm = FIQ_NP_SPLIT_HS_ABORTED;\n+\t\t\t} else {\n+\t\t\t\thandled = 1;\n+\t\t\t\trestart = 1;\n+\t\t\t}\n+\t\t} else if (hcint.b.stall) {\n+\t\t\t/* LS bus error or genuine stall */\n+\t\t\tst->fsm = FIQ_NP_SPLIT_LS_ABORTED;\n+\t\t} else {\n+\t\t\t/*\n+\t\t\t * Hardware bug. It's possible in some cases to get a\n+\t\t\t * channel halt with nothing else set when the response was a NYET.\n+\t\t\t * Treat as local 3-strikes retry.\n+\t\t\t */\n+\t\t\thcint_data_t hcint_test = hcint;\n+\t\t\thcint_test.b.chhltd = 0;\n+\t\t\tif (!hcint_test.d32) {\n+\t\t\t\tst->nr_errors++;\n+\t\t\t\tif (st->nr_errors >= 3) {\n+\t\t\t\t\tst->fsm = FIQ_NP_SPLIT_HS_ABORTED;\n+\t\t\t\t} else {\n+\t\t\t\t\thandled = 1;\n+\t\t\t\t}\n+\t\t\t} else {\n+\t\t\t\t// Something unexpected happened. AHBerror or babble perhaps. Let the IRQ deal with it.\n+\t\t\t\tst->fsm = FIQ_NP_SPLIT_HS_ABORTED;\n+\t\t\t}\n+\t\t}\n+\t\tif (st->fsm != FIQ_NP_OUT_CSPLIT_RETRY) {\n+\t\t\tfiq_fsm_restart_np_pending(state, num_channels, n);\n+\t\t}\n+\t\tbreak;\n+\n+\t/* Periodic split states (except isoc out) */\n+\tcase FIQ_PER_SSPLIT_STARTED:\n+\t\t/* Expect an ACK or failure for SSPLIT */\n+\t\tif (hcint.b.ack) {\n+\t\t\t/*\n+\t\t\t * SSPLIT transfer complete interrupt - the generation of this interrupt is fraught with bugs.\n+\t\t\t * For a packet queued in microframe n-3 to appear in n-2, if the channel is enabled near the EOF1\n+\t\t\t * point for microframe n-3, the packet will not appear on the bus until microframe n.\n+\t\t\t * Additionally, the generation of the actual interrupt is dodgy. For a packet appearing on the bus\n+\t\t\t * in microframe n, sometimes the interrupt is generated immediately. Sometimes, it appears in n+1\n+\t\t\t * coincident with SOF for n+1.\n+\t\t\t * SOF is also buggy. It can sometimes be raised AFTER the first bus transaction has taken place.\n+\t\t\t * These appear to be caused by timing/clock crossing bugs within the core itself.\n+\t\t\t * State machine workaround.\n+\t\t\t */\n+\t\t\thfnum.d32 = FIQ_READ(state->dwc_regs_base + HFNUM);\n+\t\t\thcchar.d32 = FIQ_READ(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR);\n+\t\t\tfiq_fsm_setup_csplit(state, n);\n+\t\t\t/* Poke the oddfrm bit. If we are equivalent, we received the interrupt at the correct\n+\t\t\t * time. If not, then we're in the next SOF.\n+\t\t\t */\n+\t\t\tif ((hfnum.b.frnum & 0x1) == hcchar.b.oddfrm) {\n+\t\t\t\tfiq_print(FIQDBG_INT, state, \"CSWAIT %01d\", n);\n+\t\t\t\tst->expected_uframe = hfnum.b.frnum;\n+\t\t\t\tst->fsm = FIQ_PER_CSPLIT_WAIT;\n+\t\t\t} else {\n+\t\t\t\tfiq_print(FIQDBG_INT, state, \"CSPOL  %01d\", n);\n+\t\t\t\t/* For isochronous IN endpoints,\n+\t\t\t\t * we need to hold off if we are expecting a lot of data */\n+\t\t\t\tif (st->hcchar_copy.b.mps < DATA0_PID_HEURISTIC) {\n+\t\t\t\t\tstart_next_periodic = 1;\n+\t\t\t\t}\n+\t\t\t\t/* Danger will robinson: we are in a broken state. If our first interrupt after\n+\t\t\t\t * this is a NYET, it will be delayed by 1 uframe and result in an unrecoverable\n+\t\t\t\t * lag. Unmask the NYET interrupt.\n+\t\t\t\t */\n+\t\t\t\tst->expected_uframe = (hfnum.b.frnum + 1) & 0x3FFF;\n+\t\t\t\tst->fsm = FIQ_PER_CSPLIT_BROKEN_NYET1;\n+\t\t\t\trestart = 1;\n+\t\t\t}\n+\t\t\thandled = 1;\n+\t\t} else if (hcint.b.xacterr) {\n+\t\t\t/* 3-strikes retry is enabled, we have hit our max nr_errors */\n+\t\t\tst->fsm = FIQ_PER_SPLIT_HS_ABORTED;\n+\t\t\tstart_next_periodic = 1;\n+\t\t} else {\n+\t\t\tst->fsm = FIQ_PER_SPLIT_HS_ABORTED;\n+\t\t\tstart_next_periodic = 1;\n+\t\t}\n+\t\t/* We can now queue the next isochronous OUT transaction, if one is pending. */\n+\t\tif(fiq_fsm_tt_next_isoc(state, num_channels, n)) {\n+\t\t\tfiq_print(FIQDBG_INT, state, \"NEXTISO \");\n+\t\t}\n+\t\tbreak;\n+\n+\tcase FIQ_PER_CSPLIT_NYET1:\n+\t\t/* First CSPLIT attempt was a NYET. If we get a subsequent NYET,\n+\t\t * we are too late and the TT has dropped its CSPLIT fifo.\n+\t\t */\n+\t\thfnum.d32 = FIQ_READ(state->dwc_regs_base + HFNUM);\n+\t\thcchar.d32 = FIQ_READ(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR);\n+\t\tstart_next_periodic = 1;\n+\t\tif (hcint.b.nak) {\n+\t\t\tst->fsm = FIQ_PER_SPLIT_DONE;\n+\t\t} else if (hcint.b.xfercomp) {\n+\t\t\tfiq_increment_dma_buf(state, num_channels, n);\n+\t\t\tst->fsm = FIQ_PER_CSPLIT_POLL;\n+\t\t\tst->nr_errors = 0;\n+\t\t\tif (fiq_fsm_more_csplits(state, n, &last_csplit)) {\n+\t\t\t\thandled = 1;\n+\t\t\t\trestart = 1;\n+\t\t\t\tif (!last_csplit)\n+\t\t\t\t\tstart_next_periodic = 0;\n+\t\t\t} else {\n+\t\t\t\tst->fsm = FIQ_PER_SPLIT_DONE;\n+\t\t\t}\n+\t\t} else if (hcint.b.nyet) {\n+\t\t\t/* Doh. Data lost. */\n+\t\t\tst->fsm = FIQ_PER_SPLIT_NYET_ABORTED;\n+\t\t} else if (hcint.b.xacterr || hcint.b.stall || hcint.b.bblerr) {\n+\t\t\tst->fsm = FIQ_PER_SPLIT_LS_ABORTED;\n+\t\t} else {\n+\t\t\tst->fsm = FIQ_PER_SPLIT_HS_ABORTED;\n+\t\t}\n+\t\tbreak;\n+\n+\tcase FIQ_PER_CSPLIT_BROKEN_NYET1:\n+\t\t/*\n+\t\t * we got here because our host channel is in the delayed-interrupt\n+\t\t * state and we cannot take a NYET interrupt any later than when it\n+\t\t * occurred. Disable then re-enable the channel if this happens to force\n+\t\t * CSPLITs to occur at the right time.\n+\t\t */\n+\t\thfnum.d32 = FIQ_READ(state->dwc_regs_base + HFNUM);\n+\t\thcchar.d32 = FIQ_READ(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR);\n+\t\tfiq_print(FIQDBG_INT, state, \"BROK: %01d \", n);\n+\t\tif (hcint.b.nak) {\n+\t\t\tst->fsm = FIQ_PER_SPLIT_DONE;\n+\t\t\tstart_next_periodic = 1;\n+\t\t} else if (hcint.b.xfercomp) {\n+\t\t\tfiq_increment_dma_buf(state, num_channels, n);\n+\t\t\tif (fiq_fsm_more_csplits(state, n, &last_csplit)) {\n+\t\t\t\tst->fsm = FIQ_PER_CSPLIT_POLL;\n+\t\t\t\thandled = 1;\n+\t\t\t\trestart = 1;\n+\t\t\t\tstart_next_periodic = 1;\n+\t\t\t\t/* Reload HCTSIZ for the next transfer */\n+\t\t\t\tfiq_fsm_reload_hctsiz(state, n);\n+\t\t\t\tif (!last_csplit)\n+\t\t\t\t\tstart_next_periodic = 0;\n+\t\t\t} else {\n+\t\t\t\tst->fsm = FIQ_PER_SPLIT_DONE;\n+\t\t\t}\n+\t\t} else if (hcint.b.nyet) {\n+\t\t\tst->fsm = FIQ_PER_SPLIT_NYET_ABORTED;\n+\t\t\tstart_next_periodic = 1;\n+\t\t} else if (hcint.b.xacterr || hcint.b.stall || hcint.b.bblerr) {\n+\t\t\t/* Local 3-strikes retry is handled by the core. This is a ERR response.*/\n+\t\t\tst->fsm = FIQ_PER_SPLIT_LS_ABORTED;\n+\t\t} else {\n+\t\t\tst->fsm = FIQ_PER_SPLIT_HS_ABORTED;\n+\t\t}\n+\t\tbreak;\n+\n+\tcase FIQ_PER_CSPLIT_POLL:\n+\t\thfnum.d32 = FIQ_READ(state->dwc_regs_base + HFNUM);\n+\t\thcchar.d32 = FIQ_READ(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR);\n+\t\tstart_next_periodic = 1;\n+\t\tif (hcint.b.nak) {\n+\t\t\tst->fsm = FIQ_PER_SPLIT_DONE;\n+\t\t} else if (hcint.b.xfercomp) {\n+\t\t\tfiq_increment_dma_buf(state, num_channels, n);\n+\t\t\tif (fiq_fsm_more_csplits(state, n, &last_csplit)) {\n+\t\t\t\thandled = 1;\n+\t\t\t\trestart = 1;\n+\t\t\t\t/* Reload HCTSIZ for the next transfer */\n+\t\t\t\tfiq_fsm_reload_hctsiz(state, n);\n+\t\t\t\tif (!last_csplit)\n+\t\t\t\t\tstart_next_periodic = 0;\n+\t\t\t} else {\n+\t\t\t\tst->fsm = FIQ_PER_SPLIT_DONE;\n+\t\t\t}\n+\t\t} else if (hcint.b.nyet) {\n+\t\t\t/* Are we a NYET after the first data packet? */\n+\t\t\tif (st->nrpackets == 0) {\n+\t\t\t\tst->fsm = FIQ_PER_CSPLIT_NYET1;\n+\t\t\t\thandled = 1;\n+\t\t\t\trestart = 1;\n+\t\t\t} else {\n+\t\t\t\t/* We got a NYET when polling CSPLITs. Can happen\n+\t\t\t\t * if our heuristic fails, or if someone disables us\n+\t\t\t\t * for any significant length of time.\n+\t\t\t\t */\n+\t\t\t\tif (st->nr_errors >= 3) {\n+\t\t\t\t\tst->fsm = FIQ_PER_SPLIT_NYET_ABORTED;\n+\t\t\t\t} else {\n+\t\t\t\t\tst->fsm = FIQ_PER_SPLIT_DONE;\n+\t\t\t\t}\n+\t\t\t}\n+\t\t} else if (hcint.b.xacterr || hcint.b.stall || hcint.b.bblerr) {\n+\t\t\t/* For xacterr, Local 3-strikes retry is handled by the core. This is a ERR response.*/\n+\t\t\tst->fsm = FIQ_PER_SPLIT_LS_ABORTED;\n+\t\t} else {\n+\t\t\tst->fsm = FIQ_PER_SPLIT_HS_ABORTED;\n+\t\t}\n+\t\tbreak;\n+\n+\tcase FIQ_HS_ISOC_TURBO:\n+\t\tif (fiq_fsm_update_hs_isoc(state, n, hcint)) {\n+\t\t\t/* more transactions to come */\n+\t\t\thandled = 1;\n+\t\t\tfiq_print(FIQDBG_INT, state, \"HSISO M \");\n+\t\t\t/* For strided transfers, put ourselves to sleep */\n+\t\t\tif (st->hs_isoc_info.stride > 1) {\n+\t\t\t\tst->uframe_sleeps = st->hs_isoc_info.stride - 1;\n+\t\t\t\tst->fsm = FIQ_HS_ISOC_SLEEPING;\n+\t\t\t} else {\n+\t\t\t\trestart = 1;\n+\t\t\t}\n+\t\t} else {\n+\t\t\tst->fsm = FIQ_HS_ISOC_DONE;\n+\t\t\tfiq_print(FIQDBG_INT, state, \"HSISO F \");\n+\t\t}\n+\t\tbreak;\n+\n+\tcase FIQ_HS_ISOC_ABORTED:\n+\t\t/* This abort is called by the driver rewriting the state mid-transaction\n+\t\t * which allows the dequeue mechanism to work more effectively.\n+\t\t */\n+\t\tbreak;\n+\n+\tcase FIQ_PER_ISO_OUT_ACTIVE:\n+\t\tif (hcint.b.ack) {\n+\t\t\tif(fiq_iso_out_advance(state, num_channels, n)) {\n+\t\t\t\t/* last OUT transfer */\n+\t\t\t\tst->fsm = FIQ_PER_ISO_OUT_LAST;\n+\t\t\t\t/*\n+\t\t\t\t * Assuming the periodic FIFO in the dwc core\n+\t\t\t\t * actually does its job properly, we can queue\n+\t\t\t\t * the next ssplit now and in theory, the wire\n+\t\t\t\t * transactions will be in-order.\n+\t\t\t\t */\n+\t\t\t\t// No it doesn't. It appears to process requests in host channel order.\n+\t\t\t\t//start_next_periodic = 1;\n+\t\t\t}\n+\t\t\thandled = 1;\n+\t\t\trestart = 1;\n+\t\t} else {\n+\t\t\t/*\n+\t\t\t * Isochronous transactions carry on regardless. Log the error\n+\t\t\t * and continue.\n+\t\t\t */\n+\t\t\t//explode += 1;\n+\t\t\tst->nr_errors++;\n+\t\t\tif(fiq_iso_out_advance(state, num_channels, n)) {\n+\t\t\t\tst->fsm = FIQ_PER_ISO_OUT_LAST;\n+\t\t\t\t//start_next_periodic = 1;\n+\t\t\t}\n+\t\t\thandled = 1;\n+\t\t\trestart = 1;\n+\t\t}\n+\t\tbreak;\n+\n+\tcase FIQ_PER_ISO_OUT_LAST:\n+\t\tif (hcint.b.ack) {\n+\t\t\t/* All done here */\n+\t\t\tst->fsm = FIQ_PER_ISO_OUT_DONE;\n+\t\t} else {\n+\t\t\tst->fsm = FIQ_PER_ISO_OUT_DONE;\n+\t\t\tst->nr_errors++;\n+\t\t}\n+\t\tstart_next_periodic = 1;\n+\t\tbreak;\n+\n+\tcase FIQ_PER_SPLIT_TIMEOUT:\n+\t\t/* SOF kicked us because we overran. */\n+\t\tstart_next_periodic = 1;\n+\t\tbreak;\n+\n+\tdefault:\n+\t\tbreak;\n+\t}\n+\n+\tif (handled) {\n+\t\tFIQ_WRITE(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCINT, hcint.d32);\n+\t} else {\n+\t\t/* Copy the regs into the state so the IRQ knows what to do */\n+\t\tst->hcint_copy.d32 = hcint.d32;\n+\t}\n+\n+\tif (restart) {\n+\t\t/* Restart always implies handled. */\n+\t\tif (restart == 2) {\n+\t\t\t/* For complete-split INs, the show must go on.\n+\t\t\t * Force a channel restart */\n+\t\t\tfiq_fsm_restart_channel(state, n, 1);\n+\t\t} else {\n+\t\t\tfiq_fsm_restart_channel(state, n, 0);\n+\t\t}\n+\t}\n+\tif (start_next_periodic) {\n+\t\tfiq_fsm_start_next_periodic(state, num_channels);\n+\t}\n+\tif (st->fsm != FIQ_PASSTHROUGH)\n+\t\tfiq_print(FIQDBG_INT, state, \"FSMOUT%02d\", st->fsm);\n+\n+\treturn handled;\n+}\n+\n+\n+/**\n+ * dwc_otg_fiq_fsm() - Flying State Machine (monster) FIQ\n+ * @state:\t\tpointer to state struct passed from the banked FIQ mode registers.\n+ * @num_channels:\tset according to the DWC hardware configuration\n+ * @dma:\t\tpointer to DMA bounce buffers for split transaction slots\n+ *\n+ * The FSM FIQ performs the low-level tasks that normally would be performed by the microcode\n+ * inside an EHCI or similar host controller regarding split transactions. The DWC core\n+ * interrupts each and every time a split transaction packet is received or sent successfully.\n+ * This results in either an interrupt storm when everything is working \"properly\", or\n+ * the interrupt latency of the system in general breaks time-sensitive periodic split\n+ * transactions. Pushing the low-level, but relatively easy state machine work into the FIQ\n+ * solves these problems.\n+ *\n+ * Return: void\n+ */\n+void notrace dwc_otg_fiq_fsm(struct fiq_state *state, int num_channels)\n+{\n+\tgintsts_data_t gintsts, gintsts_handled;\n+\tgintmsk_data_t gintmsk;\n+\t//hfnum_data_t hfnum;\n+\thaint_data_t haint, haint_handled;\n+\thaintmsk_data_t haintmsk;\n+\tint kick_irq = 0;\n+\n+\t/* Ensure peripheral reads issued prior to FIQ entry are complete */\n+\tdsb(sy);\n+\n+\tgintsts_handled.d32 = 0;\n+\thaint_handled.d32 = 0;\n+\n+\tfiq_fsm_spin_lock(&state->lock);\n+\tgintsts.d32 = FIQ_READ(state->dwc_regs_base + GINTSTS);\n+\tgintmsk.d32 = FIQ_READ(state->dwc_regs_base + GINTMSK);\n+\tgintsts.d32 &= gintmsk.d32;\n+\n+\tif (gintsts.b.sofintr) {\n+\t\t/* For FSM mode, SOF is required to keep the state machine advance for\n+\t\t * certain stages of the periodic pipeline. It's death to mask this\n+\t\t * interrupt in that case.\n+\t\t */\n+\n+\t\tif (!fiq_fsm_do_sof(state, num_channels)) {\n+\t\t\t/* Kick IRQ once. Queue advancement means that all pending transactions\n+\t\t\t * will get serviced when the IRQ finally executes.\n+\t\t\t */\n+\t\t\tif (state->gintmsk_saved.b.sofintr == 1)\n+\t\t\t\tkick_irq |= 1;\n+\t\t\tstate->gintmsk_saved.b.sofintr = 0;\n+\t\t}\n+\t\tgintsts_handled.b.sofintr = 1;\n+\t}\n+\n+\tif (gintsts.b.hcintr) {\n+\t\tint i;\n+\t\thaint.d32 = FIQ_READ(state->dwc_regs_base + HAINT);\n+\t\thaintmsk.d32 = FIQ_READ(state->dwc_regs_base + HAINTMSK);\n+\t\thaint.d32 &= haintmsk.d32;\n+\t\thaint_handled.d32 = 0;\n+\t\tfor (i=0; i<num_channels; i++) {\n+\t\t\tif (haint.b2.chint & (1 << i)) {\n+\t\t\t\tif(!fiq_fsm_do_hcintr(state, num_channels, i)) {\n+\t\t\t\t\t/* HCINT was not handled in FIQ\n+\t\t\t\t\t * HAINT is level-sensitive, leading to level-sensitive ginststs.b.hcint bit.\n+\t\t\t\t\t * Mask HAINT(i) but keep top-level hcint unmasked.\n+\t\t\t\t\t */\n+\t\t\t\t\tstate->haintmsk_saved.b2.chint &= ~(1 << i);\n+\t\t\t\t} else {\n+\t\t\t\t\t/* do_hcintr cleaned up after itself, but clear haint */\n+\t\t\t\t\thaint_handled.b2.chint |= (1 << i);\n+\t\t\t\t}\n+\t\t\t}\n+\t\t}\n+\n+\t\tif (haint_handled.b2.chint) {\n+\t\t\tFIQ_WRITE(state->dwc_regs_base + HAINT, haint_handled.d32);\n+\t\t}\n+\n+\t\tif (haintmsk.d32 != (haintmsk.d32 & state->haintmsk_saved.d32)) {\n+\t\t\t/*\n+\t\t\t * This is necessary to avoid multiple retriggers of the MPHI in the case\n+\t\t\t * where interrupts are held off and HCINTs start to pile up.\n+\t\t\t * Only wake up the IRQ if a new interrupt came in, was not handled and was\n+\t\t\t * masked.\n+\t\t\t */\n+\t\t\thaintmsk.d32 &= state->haintmsk_saved.d32;\n+\t\t\tFIQ_WRITE(state->dwc_regs_base + HAINTMSK, haintmsk.d32);\n+\t\t\tkick_irq |= 1;\n+\t\t}\n+\t\t/* Top-Level interrupt - always handled because it's level-sensitive */\n+\t\tgintsts_handled.b.hcintr = 1;\n+\t}\n+\n+\n+\t/* Clear the bits in the saved register that were not handled but were triggered. */\n+\tstate->gintmsk_saved.d32 &= ~(gintsts.d32 & ~gintsts_handled.d32);\n+\n+\t/* FIQ didn't handle something - mask has changed - write new mask */\n+\tif (gintmsk.d32 != (gintmsk.d32 & state->gintmsk_saved.d32)) {\n+\t\tgintmsk.d32 &= state->gintmsk_saved.d32;\n+\t\tgintmsk.b.sofintr = 1;\n+\t\tFIQ_WRITE(state->dwc_regs_base + GINTMSK, gintmsk.d32);\n+//\t\tfiq_print(FIQDBG_INT, state, \"KICKGINT\");\n+//\t\tfiq_print(FIQDBG_INT, state, \"%08x\", gintmsk.d32);\n+//\t\tfiq_print(FIQDBG_INT, state, \"%08x\", state->gintmsk_saved.d32);\n+\t\tkick_irq |= 1;\n+\t}\n+\n+\tif (gintsts_handled.d32) {\n+\t\t/* Only applies to edge-sensitive bits in GINTSTS */\n+\t\tFIQ_WRITE(state->dwc_regs_base + GINTSTS, gintsts_handled.d32);\n+\t}\n+\n+\t/* We got an interrupt, didn't handle it. */\n+\tif (kick_irq) {\n+\t\tstate->mphi_int_count++;\n+\t\tif (state->mphi_regs.swirq_set) {\n+\t\t\tFIQ_WRITE(state->mphi_regs.swirq_set, 1);\n+\t\t} else {\n+\t\t\tFIQ_WRITE(state->mphi_regs.outdda, state->dummy_send_dma);\n+\t\t\tFIQ_WRITE(state->mphi_regs.outddb, (1<<29));\n+\t\t}\n+\n+\t}\n+\tstate->fiq_done++;\n+\tmb();\n+\tfiq_fsm_spin_unlock(&state->lock);\n+}\n+\n+\n+/**\n+ * dwc_otg_fiq_nop() - FIQ \"lite\"\n+ * @state:\tpointer to state struct passed from the banked FIQ mode registers.\n+ *\n+ * The \"nop\" handler does not intervene on any interrupts other than SOF.\n+ * It is limited in scope to deciding at each SOF if the IRQ SOF handler (which deals\n+ * with non-periodic/periodic queues) needs to be kicked.\n+ *\n+ * This is done to hold off the SOF interrupt, which occurs at a rate of 8000 per second.\n+ *\n+ * Return: void\n+ */\n+void notrace dwc_otg_fiq_nop(struct fiq_state *state)\n+{\n+\tgintsts_data_t gintsts, gintsts_handled;\n+\tgintmsk_data_t gintmsk;\n+\thfnum_data_t hfnum;\n+\n+\t/* Ensure peripheral reads issued prior to FIQ entry are complete */\n+\tdsb(sy);\n+\n+\tfiq_fsm_spin_lock(&state->lock);\n+\thfnum.d32 = FIQ_READ(state->dwc_regs_base + HFNUM);\n+\tgintsts.d32 = FIQ_READ(state->dwc_regs_base + GINTSTS);\n+\tgintmsk.d32 = FIQ_READ(state->dwc_regs_base + GINTMSK);\n+\tgintsts.d32 &= gintmsk.d32;\n+\tgintsts_handled.d32 = 0;\n+\n+\tif (gintsts.b.sofintr) {\n+\t\tif (!state->kick_np_queues &&\n+\t\t\t\tdwc_frame_num_gt(state->next_sched_frame, hfnum.b.frnum)) {\n+\t\t\t/* SOF handled, no work to do, just ACK interrupt */\n+\t\t\tgintsts_handled.b.sofintr = 1;\n+\t\t} else {\n+\t\t\t/* Kick IRQ */\n+\t\t\tstate->gintmsk_saved.b.sofintr = 0;\n+\t\t}\n+\t}\n+\n+\t/* Reset handled interrupts */\n+\tif(gintsts_handled.d32) {\n+\t\tFIQ_WRITE(state->dwc_regs_base + GINTSTS, gintsts_handled.d32);\n+\t}\n+\n+\t/* Clear the bits in the saved register that were not handled but were triggered. */\n+\tstate->gintmsk_saved.d32 &= ~(gintsts.d32 & ~gintsts_handled.d32);\n+\n+\t/* We got an interrupt, didn't handle it and want to mask it */\n+\tif (~(state->gintmsk_saved.d32)) {\n+\t\tstate->mphi_int_count++;\n+\t\tgintmsk.d32 &= state->gintmsk_saved.d32;\n+\t\tFIQ_WRITE(state->dwc_regs_base + GINTMSK, gintmsk.d32);\n+\t\tif (state->mphi_regs.swirq_set) {\n+\t\t\tFIQ_WRITE(state->mphi_regs.swirq_set, 1);\n+\t\t} else {\n+\t\t\t/* Force a clear before another dummy send */\n+\t\t\tFIQ_WRITE(state->mphi_regs.intstat, (1<<29));\n+\t\t\tFIQ_WRITE(state->mphi_regs.outdda, state->dummy_send_dma);\n+\t\t\tFIQ_WRITE(state->mphi_regs.outddb, (1<<29));\n+\t\t}\n+\t}\n+\tstate->fiq_done++;\n+\tmb();\n+\tfiq_fsm_spin_unlock(&state->lock);\n+}\n--- /dev/null\n+++ b/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.h\n@@ -0,0 +1,399 @@\n+/*\n+ * dwc_otg_fiq_fsm.h - Finite state machine FIQ header definitions\n+ *\n+ * Copyright (c) 2013 Raspberry Pi Foundation\n+ *\n+ * Author: Jonathan Bell <jonathan@raspberrypi.org>\n+ * All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions are met:\n+ *\t* Redistributions of source code must retain the above copyright\n+ *\t  notice, this list of conditions and the following disclaimer.\n+ *\t* Redistributions in binary form must reproduce the above copyright\n+ *\t  notice, this list of conditions and the following disclaimer in the\n+ *\t  documentation and/or other materials provided with the distribution.\n+ *\t* Neither the name of Raspberry Pi nor the\n+ *\t  names of its contributors may be used to endorse or promote products\n+ *\t  derived from this software without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" AND\n+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY\n+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\n+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ *\n+ * This FIQ implements functionality that performs split transactions on\n+ * the dwc_otg hardware without any outside intervention. A split transaction\n+ * is \"queued\" by nominating a specific host channel to perform the entirety\n+ * of a split transaction. This FIQ will then perform the microframe-precise\n+ * scheduling required in each phase of the transaction until completion.\n+ *\n+ * The FIQ functionality has been surgically implanted into the Synopsys\n+ * vendor-provided driver.\n+ *\n+ */\n+\n+#ifndef DWC_OTG_FIQ_FSM_H_\n+#define DWC_OTG_FIQ_FSM_H_\n+\n+#include \"dwc_otg_regs.h\"\n+#include \"dwc_otg_cil.h\"\n+#include \"dwc_otg_hcd.h\"\n+#include <linux/kernel.h>\n+#include <linux/irqflags.h>\n+#include <linux/string.h>\n+#include <asm/barrier.h>\n+\n+#if 0\n+#define FLAME_ON(x)\t\t\t\t\t\\\n+do {\t\t\t\t\t\t\t\\\n+\tint gpioreg;                                    \\\n+\t\t\t\t\t\t\t\\\n+\tgpioreg = readl(__io_address(0x20200000+0x8));\t\\\n+\tgpioreg &= ~(7 << (x-20)*3);\t\t\t\\\n+\tgpioreg |= 0x1 << (x-20)*3;\t\t\t\\\n+\twritel(gpioreg, __io_address(0x20200000+0x8));\t\\\n+\t\t\t\t\t\t\t\\\n+\twritel(1<<x, __io_address(0x20200000+(0x1C)));\t\\\n+} while (0)\n+\n+#define FLAME_OFF(x)\t\t\t\t\t\\\n+do {\t\t\t\t\t\t\t\\\n+\twritel(1<<x, __io_address(0x20200000+(0x28)));\t\\\n+} while (0)\n+#else\n+#define FLAME_ON(x) do { } while (0)\n+#define FLAME_OFF(X) do { } while (0)\n+#endif\n+\n+/* This is a quick-and-dirty arch-specific register read/write. We know that\n+ * writes to a peripheral on BCM2835 will always arrive in-order, also that\n+ * reads and writes are executed in-order therefore the need for memory barriers\n+ * is obviated if we're only talking to USB.\n+ */\n+#define FIQ_WRITE(_addr_,_data_) (*(volatile unsigned int *) (_addr_) = (_data_))\n+#define FIQ_READ(_addr_) (*(volatile unsigned int *) (_addr_))\n+\n+/* FIQ-ified register definitions. Offsets are from dwc_regs_base. */\n+#define GINTSTS\t\t0x014\n+#define GINTMSK\t\t0x018\n+/* Debug register. Poll the top of the received packets FIFO. */\n+#define GRXSTSR\t\t0x01C\n+#define HFNUM\t\t0x408\n+#define HAINT\t\t0x414\n+#define HAINTMSK\t0x418\n+#define HPRT0\t\t0x440\n+\n+/* HC_regs start from an offset of 0x500 */\n+#define HC_START\t0x500\n+#define HC_OFFSET\t0x020\n+\n+#define HC_DMA\t\t0x14\n+\n+#define HCCHAR\t\t0x00\n+#define HCSPLT\t\t0x04\n+#define HCINT\t\t0x08\n+#define HCINTMSK\t0x0C\n+#define HCTSIZ\t\t0x10\n+\n+#define ISOC_XACTPOS_ALL \t0b11\n+#define ISOC_XACTPOS_BEGIN\t0b10\n+#define ISOC_XACTPOS_MID\t0b00\n+#define ISOC_XACTPOS_END\t0b01\n+\n+#define DWC_PID_DATA2\t0b01\n+#define DWC_PID_MDATA\t0b11\n+#define DWC_PID_DATA1\t0b10\n+#define DWC_PID_DATA0\t0b00\n+\n+typedef struct {\n+\tvolatile void* base;\n+\tvolatile void* ctrl;\n+\tvolatile void* outdda;\n+\tvolatile void* outddb;\n+\tvolatile void* intstat;\n+\tvolatile void* swirq_set;\n+\tvolatile void* swirq_clr;\n+} mphi_regs_t;\n+\n+enum fiq_debug_level {\n+\tFIQDBG_SCHED = (1 << 0),\n+\tFIQDBG_INT   = (1 << 1),\n+\tFIQDBG_ERR   = (1 << 2),\n+\tFIQDBG_PORTHUB = (1 << 3),\n+};\n+\n+#ifdef CONFIG_ARM64\n+\n+typedef spinlock_t fiq_lock_t;\n+\n+#else\n+\n+typedef struct {\n+\tunion {\n+\t\tuint32_t slock;\n+\t\tstruct _tickets {\n+\t\t\tuint16_t owner;\n+\t\t\tuint16_t next;\n+\t\t} tickets;\n+\t};\n+} fiq_lock_t;\n+\n+#endif\n+\n+struct fiq_state;\n+\n+extern void _fiq_print (enum fiq_debug_level dbg_lvl, volatile struct fiq_state *state, char *fmt, ...);\n+#if 0\n+#define fiq_print _fiq_print\n+#else\n+#define fiq_print(x, y, ...)\n+#endif\n+\n+extern bool fiq_enable, fiq_fsm_enable;\n+extern ushort nak_holdoff;\n+\n+/**\n+ * enum fiq_fsm_state - The FIQ FSM states.\n+ *\n+ * This is the \"core\" of the FIQ FSM. Broadly, the FSM states follow the\n+ * USB2.0 specification for host responses to various transaction states.\n+ * There are modifications to this host state machine because of a variety of\n+ * quirks and limitations in the dwc_otg hardware.\n+ *\n+ * The fsm state is also used to communicate back to the driver on completion of\n+ * a split transaction. The end states are used in conjunction with the interrupts\n+ * raised by the final transaction.\n+ */\n+enum fiq_fsm_state {\n+\t/* FIQ isn't enabled for this host channel */\n+\tFIQ_PASSTHROUGH = 0,\n+\t/* For the first interrupt received for this channel,\n+\t * the FIQ has to ack any interrupts indicating success. */\n+\tFIQ_PASSTHROUGH_ERRORSTATE = 31,\n+\t/* Nonperiodic state groups */\n+\tFIQ_NP_SSPLIT_STARTED = 1,\n+\tFIQ_NP_SSPLIT_RETRY = 2,\n+\t/* TT contention - working around hub bugs */\n+\tFIQ_NP_SSPLIT_PENDING = 33,\n+\tFIQ_NP_OUT_CSPLIT_RETRY = 3,\n+\tFIQ_NP_IN_CSPLIT_RETRY = 4,\n+\tFIQ_NP_SPLIT_DONE = 5,\n+\tFIQ_NP_SPLIT_LS_ABORTED = 6,\n+\t/* This differentiates a HS transaction error from a LS one\n+\t * (handling the hub state is different) */\n+\tFIQ_NP_SPLIT_HS_ABORTED = 7,\n+\n+\t/* Periodic state groups */\n+\t/* Periodic transactions are either started directly by the IRQ handler\n+\t * or deferred if the TT is already in use.\n+\t */\n+\tFIQ_PER_SSPLIT_QUEUED = 8,\n+\tFIQ_PER_SSPLIT_STARTED = 9,\n+\tFIQ_PER_SSPLIT_LAST = 10,\n+\n+\n+\tFIQ_PER_ISO_OUT_PENDING = 11,\n+\tFIQ_PER_ISO_OUT_ACTIVE = 12,\n+\tFIQ_PER_ISO_OUT_LAST = 13,\n+\tFIQ_PER_ISO_OUT_DONE = 27,\n+\n+\tFIQ_PER_CSPLIT_WAIT = 14,\n+\tFIQ_PER_CSPLIT_NYET1 = 15,\n+\tFIQ_PER_CSPLIT_BROKEN_NYET1 = 28,\n+\tFIQ_PER_CSPLIT_NYET_FAFF = 29,\n+\t/* For multiple CSPLITs (large isoc IN, or delayed interrupt) */\n+\tFIQ_PER_CSPLIT_POLL = 16,\n+\t/* The last CSPLIT for a transaction has been issued, differentiates\n+\t * for the state machine to queue the next packet.\n+\t */\n+\tFIQ_PER_CSPLIT_LAST = 17,\n+\n+\tFIQ_PER_SPLIT_DONE = 18,\n+\tFIQ_PER_SPLIT_LS_ABORTED = 19,\n+\tFIQ_PER_SPLIT_HS_ABORTED = 20,\n+\tFIQ_PER_SPLIT_NYET_ABORTED = 21,\n+\t/* Frame rollover has occurred without the transaction finishing. */\n+\tFIQ_PER_SPLIT_TIMEOUT = 22,\n+\n+\t/* FIQ-accelerated HS Isochronous state groups */\n+\tFIQ_HS_ISOC_TURBO = 23,\n+\t/* For interval > 1, SOF wakes up the isochronous FSM */\n+\tFIQ_HS_ISOC_SLEEPING = 24,\n+\tFIQ_HS_ISOC_DONE = 25,\n+\tFIQ_HS_ISOC_ABORTED = 26,\n+\tFIQ_DEQUEUE_ISSUED = 30,\n+\tFIQ_TEST = 32,\n+};\n+\n+struct fiq_stack {\n+\tint magic1;\n+\tuint8_t stack[2048];\n+\tint magic2;\n+};\n+\n+\n+/**\n+ * struct fiq_dma_info - DMA bounce buffer utilisation information (per-channel)\n+ * @index:\tNumber of slots reported used for IN transactions / number of slots\n+ *\t\t\ttransmitted for an OUT transaction\n+ * @slot_len[6]: Number of actual transfer bytes in each slot (255 if unused)\n+ *\n+ * Split transaction transfers can have variable length depending on other bus\n+ * traffic. The OTG core DMA engine requires 4-byte aligned addresses therefore\n+ * each transaction needs a guaranteed aligned address. A maximum of 6 split transfers\n+ * can happen per-frame.\n+ */\n+struct fiq_dma_info {\n+\tu8 index;\n+\tu8 slot_len[6];\n+};\n+\n+struct __attribute__((packed)) fiq_split_dma_slot {\n+\tu8 buf[188];\n+};\n+\n+struct fiq_dma_channel {\n+\tstruct __attribute__((packed)) fiq_split_dma_slot index[6];\n+};\n+\n+struct fiq_dma_blob {\n+\tstruct __attribute__((packed)) fiq_dma_channel channel[0];\n+};\n+\n+/**\n+ * struct fiq_hs_isoc_info - USB2.0 isochronous data\n+ * @iso_frame:\tPointer to the array of OTG URB iso_frame_descs.\n+ * @nrframes:\tTotal length of iso_frame_desc array\n+ * @index:\tCurrent index (FIQ-maintained)\n+ * @stride:\tInterval in uframes between HS isoc transactions\n+ */\n+struct fiq_hs_isoc_info {\n+\tstruct dwc_otg_hcd_iso_packet_desc *iso_desc;\n+\tunsigned int nrframes;\n+\tunsigned int index;\n+\tunsigned int stride;\n+};\n+\n+/**\n+ * struct fiq_channel_state - FIQ state machine storage\n+ * @fsm:\tCurrent state of the channel as understood by the FIQ\n+ * @nr_errors:\tNumber of transaction errors on this split-transaction\n+ * @hub_addr:   SSPLIT/CSPLIT destination hub\n+ * @port_addr:  SSPLIT/CSPLIT destination port - always 1 if single TT hub\n+ * @nrpackets:  For isoc OUT, the number of split-OUT packets to transmit. For\n+ * \t\tsplit-IN, number of CSPLIT data packets that were received.\n+ * @hcchar_copy:\n+ * @hcsplt_copy:\n+ * @hcintmsk_copy:\n+ * @hctsiz_copy:\tCopies of the host channel registers.\n+ * \t\t\tFor use as scratch, or for returning state.\n+ *\n+ * The fiq_channel_state is state storage between interrupts for a host channel. The\n+ * FSM state is stored here. Members of this structure must only be set up by the\n+ * driver prior to enabling the FIQ for this host channel, and not touched until the FIQ\n+ * has updated the state to either a COMPLETE state group or ABORT state group.\n+ */\n+\n+struct fiq_channel_state {\n+\tenum fiq_fsm_state fsm;\n+\tunsigned int nr_errors;\n+\tunsigned int hub_addr;\n+\tunsigned int port_addr;\n+\t/* Hardware bug workaround: sometimes channel halt interrupts are\n+\t * delayed until the next SOF. Keep track of when we expected to get interrupted. */\n+\tunsigned int expected_uframe;\n+\t/* number of uframes remaining (for interval > 1 HS isoc transfers) before next transfer */\n+\tunsigned int uframe_sleeps;\n+\t/* in/out for communicating number of dma buffers used, or number of ISOC to do */\n+\tunsigned int nrpackets;\n+\tstruct fiq_dma_info dma_info;\n+\tstruct fiq_hs_isoc_info hs_isoc_info;\n+\t/* Copies of HC registers - in/out communication from/to IRQ handler\n+\t * and for ease of channel setup. A bit of mungeing is performed - for\n+\t * example the hctsiz.b.maxp is _always_ the max packet size of the endpoint.\n+\t */\n+\thcchar_data_t hcchar_copy;\n+\thcsplt_data_t hcsplt_copy;\n+\thcint_data_t hcint_copy;\n+\thcintmsk_data_t hcintmsk_copy;\n+\thctsiz_data_t hctsiz_copy;\n+\thcdma_data_t hcdma_copy;\n+};\n+\n+/**\n+ * struct fiq_state - top-level FIQ state machine storage\n+ * @mphi_regs:\t\tvirtual address of the MPHI peripheral register file\n+ * @dwc_regs_base:\tvirtual address of the base of the DWC core register file\n+ * @dma_base:\t\tphysical address for the base of the DMA bounce buffers\n+ * @dummy_send:\t\tScratch area for sending a fake message to the MPHI peripheral\n+ * @gintmsk_saved:\tTop-level mask of interrupts that the FIQ has not handled.\n+ * \t\t\tUsed for determining which interrupts fired to set off the IRQ handler.\n+ * @haintmsk_saved:\tMask of interrupts from host channels that the FIQ did not handle internally.\n+ * @np_count:\t\tNon-periodic transactions in the active queue\n+ * @np_sent:\t\tCount of non-periodic transactions that have completed\n+ * @next_sched_frame:\tFor periodic transactions handled by the driver's SOF-driven queuing mechanism,\n+ * \t\t\tthis is the next frame on which a SOF interrupt is required. Used to hold off\n+ * \t\t\tpassing SOF through to the driver until necessary.\n+ * @channel[n]:\t\tPer-channel FIQ state. Allocated during init depending on the number of host\n+ * \t\t\tchannels configured into the core logic.\n+ *\n+ * This is passed as the first argument to the dwc_otg_fiq_fsm top-level FIQ handler from the asm stub.\n+ * It contains top-level state information.\n+ */\n+struct fiq_state {\n+\tfiq_lock_t lock;\n+\tmphi_regs_t mphi_regs;\n+\tvoid *dwc_regs_base;\n+\tdma_addr_t dma_base;\n+\tstruct fiq_dma_blob *fiq_dmab;\n+\tvoid *dummy_send;\n+\tdma_addr_t dummy_send_dma;\n+\tgintmsk_data_t gintmsk_saved;\n+\thaintmsk_data_t haintmsk_saved;\n+\tint mphi_int_count;\n+\tunsigned int fiq_done;\n+\tunsigned int kick_np_queues;\n+\tunsigned int next_sched_frame;\n+#ifdef FIQ_DEBUG\n+\tchar * buffer;\n+\tunsigned int bufsiz;\n+#endif\n+\tstruct fiq_channel_state channel[0];\n+};\n+\n+#ifdef CONFIG_ARM64\n+\n+#ifdef local_fiq_enable\n+#undef local_fiq_enable\n+#endif\n+\n+#ifdef local_fiq_disable\n+#undef local_fiq_disable\n+#endif\n+\n+extern void local_fiq_enable(void);\n+\n+extern void local_fiq_disable(void);\n+\n+#endif\n+\n+extern void fiq_fsm_spin_lock(fiq_lock_t *lock);\n+\n+extern void fiq_fsm_spin_unlock(fiq_lock_t *lock);\n+\n+extern int fiq_fsm_too_late(struct fiq_state *st, int n);\n+\n+extern int fiq_fsm_tt_in_use(struct fiq_state *st, int num_channels, int n);\n+\n+extern void dwc_otg_fiq_fsm(struct fiq_state *state, int num_channels);\n+\n+extern void dwc_otg_fiq_nop(struct fiq_state *state);\n+\n+#endif /* DWC_OTG_FIQ_FSM_H_ */\n--- /dev/null\n+++ b/drivers/usb/host/dwc_otg/dwc_otg_fiq_stub.S\n@@ -0,0 +1,80 @@\n+/*\n+ * dwc_otg_fiq_fsm.S - assembly stub for the FSM FIQ\n+ *\n+ * Copyright (c) 2013 Raspberry Pi Foundation\n+ *\n+ * Author: Jonathan Bell <jonathan@raspberrypi.org>\n+ * All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions are met:\n+ *\t* Redistributions of source code must retain the above copyright\n+ *\t  notice, this list of conditions and the following disclaimer.\n+ *\t* Redistributions in binary form must reproduce the above copyright\n+ *\t  notice, this list of conditions and the following disclaimer in the\n+ *\t  documentation and/or other materials provided with the distribution.\n+ *\t* Neither the name of Raspberry Pi nor the\n+ *\t  names of its contributors may be used to endorse or promote products\n+ *\t  derived from this software without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" AND\n+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+ * DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY\n+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\n+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+\n+#include <asm/assembler.h>\n+#include <linux/linkage.h>\n+\n+\n+.text\n+\n+.global _dwc_otg_fiq_stub_end;\n+\n+/**\n+  * _dwc_otg_fiq_stub() - entry copied to the FIQ vector page to allow\n+  * a C-style function call with arguments from the FIQ banked registers.\n+  * r0 = &hcd->fiq_state\n+  * r1 = &hcd->num_channels\n+  * r2 = &hcd->dma_buffers\n+  * Tramples: r0, r1, r2, r4, fp, ip\n+  */\n+\n+ENTRY(_dwc_otg_fiq_stub)\n+\t/* Stash unbanked regs - SP will have been set up for us */\n+\tmov ip, sp;\n+\tstmdb sp!, {r0-r12, lr};\n+#ifdef FIQ_DEBUG\n+\t// Cycle profiling - read cycle counter at start\n+\tmrc p15, 0, r5, c15, c12, 1;\n+#endif\n+\t/* r11 = fp, don't trample it */\n+\tmov r4, fp;\n+\t/* set EABI frame size */\n+\tsub fp, ip, #512;\n+\n+\t/* for fiq NOP mode - just need state */\n+\tmov r0, r8;\n+\t/* r9 = num_channels */\n+\tmov r1, r9;\n+\t/* r10 = struct *dma_bufs */\n+//\tmov r2, r10;\n+\n+\t/* r4 = &fiq_c_function */\n+\tblx r4;\n+#ifdef FIQ_DEBUG\n+\tmrc p15, 0, r4, c15, c12, 1;\n+\tsubs r5, r5, r4;\n+\t// r5 is now the cycle count time for executing the FIQ. Store it somewhere?\n+#endif\n+\tldmia sp!, {r0-r12, lr};\n+\tsubs pc, lr, #4;\n+_dwc_otg_fiq_stub_end:\n+END(_dwc_otg_fiq_stub)\n--- /dev/null\n+++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd.c\n@@ -0,0 +1,4356 @@\n+\n+/* ==========================================================================\n+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd.c $\n+ * $Revision: #104 $\n+ * $Date: 2011/10/24 $\n+ * $Change: 1871159 $\n+ *\n+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,\n+ * \"Software\") is an Unsupported proprietary work of Synopsys, Inc. unless\n+ * otherwise expressly agreed to in writing between Synopsys and you.\n+ *\n+ * The Software IS NOT an item of Licensed Software or Licensed Product under\n+ * any End User Software License Agreement or Agreement for Licensed Product\n+ * with Synopsys or any supplement thereto. You are permitted to use and\n+ * redistribute this Software in source and binary forms, with or without\n+ * modification, provided that redistributions of source code must retain this\n+ * notice. You may not view, use, disclose, copy or distribute this file or\n+ * any information contained herein except pursuant to this license grant from\n+ * Synopsys. If you do not agree with this notice, including the disclaimer\n+ * below, then you are not authorized to use the Software.\n+ *\n+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN \"AS IS\" BASIS\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,\n+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH\n+ * DAMAGE.\n+ * ========================================================================== */\n+#ifndef DWC_DEVICE_ONLY\n+\n+/** @file\n+ * This file implements HCD Core. All code in this file is portable and doesn't\n+ * use any OS specific functions.\n+ * Interface provided by HCD Core is defined in <code><hcd_if.h></code>\n+ * header file.\n+ */\n+\n+#include <linux/usb.h>\n+#include <linux/usb/hcd.h>\n+\n+#include \"dwc_otg_hcd.h\"\n+#include \"dwc_otg_regs.h\"\n+#include \"dwc_otg_fiq_fsm.h\"\n+\n+extern bool microframe_schedule;\n+extern uint16_t fiq_fsm_mask, nak_holdoff;\n+\n+//#define DEBUG_HOST_CHANNELS\n+#ifdef DEBUG_HOST_CHANNELS\n+static int last_sel_trans_num_per_scheduled = 0;\n+static int last_sel_trans_num_nonper_scheduled = 0;\n+static int last_sel_trans_num_avail_hc_at_start = 0;\n+static int last_sel_trans_num_avail_hc_at_end = 0;\n+#endif /* DEBUG_HOST_CHANNELS */\n+\n+\n+dwc_otg_hcd_t *dwc_otg_hcd_alloc_hcd(void)\n+{\n+\treturn DWC_ALLOC(sizeof(dwc_otg_hcd_t));\n+}\n+\n+/**\n+ * Connection timeout function.  An OTG host is required to display a\n+ * message if the device does not connect within 10 seconds.\n+ */\n+void dwc_otg_hcd_connect_timeout(void *ptr)\n+{\n+\tDWC_DEBUGPL(DBG_HCDV, \"%s(%p)\\n\", __func__, ptr);\n+\tDWC_PRINTF(\"Connect Timeout\\n\");\n+\t__DWC_ERROR(\"Device Not Connected/Responding\\n\");\n+}\n+\n+#if defined(DEBUG)\n+static void dump_channel_info(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)\n+{\n+\tif (qh->channel != NULL) {\n+\t\tdwc_hc_t *hc = qh->channel;\n+\t\tdwc_list_link_t *item;\n+\t\tdwc_otg_qh_t *qh_item;\n+\t\tint num_channels = hcd->core_if->core_params->host_channels;\n+\t\tint i;\n+\n+\t\tdwc_otg_hc_regs_t *hc_regs;\n+\t\thcchar_data_t hcchar;\n+\t\thcsplt_data_t hcsplt;\n+\t\thctsiz_data_t hctsiz;\n+\t\tuint32_t hcdma;\n+\n+\t\thc_regs = hcd->core_if->host_if->hc_regs[hc->hc_num];\n+\t\thcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);\n+\t\thcsplt.d32 = DWC_READ_REG32(&hc_regs->hcsplt);\n+\t\thctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);\n+\t\thcdma = DWC_READ_REG32(&hc_regs->hcdma);\n+\n+\t\tDWC_PRINTF(\"  Assigned to channel %p:\\n\", hc);\n+\t\tDWC_PRINTF(\"    hcchar 0x%08x, hcsplt 0x%08x\\n\", hcchar.d32,\n+\t\t\t   hcsplt.d32);\n+\t\tDWC_PRINTF(\"    hctsiz 0x%08x, hcdma 0x%08x\\n\", hctsiz.d32,\n+\t\t\t   hcdma);\n+\t\tDWC_PRINTF(\"    dev_addr: %d, ep_num: %d, ep_is_in: %d\\n\",\n+\t\t\t   hc->dev_addr, hc->ep_num, hc->ep_is_in);\n+\t\tDWC_PRINTF(\"    ep_type: %d\\n\", hc->ep_type);\n+\t\tDWC_PRINTF(\"    max_packet: %d\\n\", hc->max_packet);\n+\t\tDWC_PRINTF(\"    data_pid_start: %d\\n\", hc->data_pid_start);\n+\t\tDWC_PRINTF(\"    xfer_started: %d\\n\", hc->xfer_started);\n+\t\tDWC_PRINTF(\"    halt_status: %d\\n\", hc->halt_status);\n+\t\tDWC_PRINTF(\"    xfer_buff: %p\\n\", hc->xfer_buff);\n+\t\tDWC_PRINTF(\"    xfer_len: %d\\n\", hc->xfer_len);\n+\t\tDWC_PRINTF(\"    qh: %p\\n\", hc->qh);\n+\t\tDWC_PRINTF(\"  NP inactive sched:\\n\");\n+\t\tDWC_LIST_FOREACH(item, &hcd->non_periodic_sched_inactive) {\n+\t\t\tqh_item =\n+\t\t\t    DWC_LIST_ENTRY(item, dwc_otg_qh_t, qh_list_entry);\n+\t\t\tDWC_PRINTF(\"    %p\\n\", qh_item);\n+\t\t}\n+\t\tDWC_PRINTF(\"  NP active sched:\\n\");\n+\t\tDWC_LIST_FOREACH(item, &hcd->non_periodic_sched_active) {\n+\t\t\tqh_item =\n+\t\t\t    DWC_LIST_ENTRY(item, dwc_otg_qh_t, qh_list_entry);\n+\t\t\tDWC_PRINTF(\"    %p\\n\", qh_item);\n+\t\t}\n+\t\tDWC_PRINTF(\"  Channels: \\n\");\n+\t\tfor (i = 0; i < num_channels; i++) {\n+\t\t\tdwc_hc_t *hc = hcd->hc_ptr_array[i];\n+\t\t\tDWC_PRINTF(\"    %2d: %p\\n\", i, hc);\n+\t\t}\n+\t}\n+}\n+#else\n+#define dump_channel_info(hcd, qh)\n+#endif /* DEBUG */\n+\n+/**\n+ * Work queue function for starting the HCD when A-Cable is connected.\n+ * The hcd_start() must be called in a process context.\n+ */\n+static void hcd_start_func(void *_vp)\n+{\n+\tdwc_otg_hcd_t *hcd = (dwc_otg_hcd_t *) _vp;\n+\n+\tDWC_DEBUGPL(DBG_HCDV, \"%s() %p\\n\", __func__, hcd);\n+\tif (hcd) {\n+\t\thcd->fops->start(hcd);\n+\t}\n+}\n+\n+static void del_xfer_timers(dwc_otg_hcd_t * hcd)\n+{\n+#ifdef DEBUG\n+\tint i;\n+\tint num_channels = hcd->core_if->core_params->host_channels;\n+\tfor (i = 0; i < num_channels; i++) {\n+\t\tDWC_TIMER_CANCEL(hcd->core_if->hc_xfer_timer[i]);\n+\t}\n+#endif\n+}\n+\n+static void del_timers(dwc_otg_hcd_t * hcd)\n+{\n+\tdel_xfer_timers(hcd);\n+\tDWC_TIMER_CANCEL(hcd->conn_timer);\n+}\n+\n+/**\n+ * Processes all the URBs in a single list of QHs. Completes them with\n+ * -ESHUTDOWN and frees the QTD.\n+ */\n+static void kill_urbs_in_qh_list(dwc_otg_hcd_t * hcd, dwc_list_link_t * qh_list)\n+{\n+\tdwc_list_link_t *qh_item, *qh_tmp;\n+\tdwc_otg_qh_t *qh;\n+\tdwc_otg_qtd_t *qtd, *qtd_tmp;\n+\tint quiesced = 0;\n+\n+\tDWC_LIST_FOREACH_SAFE(qh_item, qh_tmp, qh_list) {\n+\t\tqh = DWC_LIST_ENTRY(qh_item, dwc_otg_qh_t, qh_list_entry);\n+\t\tDWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp,\n+\t\t\t\t\t &qh->qtd_list, qtd_list_entry) {\n+\t\t\tqtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list);\n+\t\t\tif (qtd->urb != NULL) {\n+\t\t\t\thcd->fops->complete(hcd, qtd->urb->priv,\n+\t\t\t\t\t\t    qtd->urb, -DWC_E_SHUTDOWN);\n+\t\t\t\tdwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh);\n+\t\t\t}\n+\n+\t\t}\n+\t\tif(qh->channel) {\n+\t\t\tint n = qh->channel->hc_num;\n+\t\t\t/* Using hcchar.chen == 1 is not a reliable test.\n+\t\t\t * It is possible that the channel has already halted\n+\t\t\t * but not yet been through the IRQ handler.\n+\t\t\t */\n+\t\t\tif (fiq_fsm_enable && (hcd->fiq_state->channel[qh->channel->hc_num].fsm != FIQ_PASSTHROUGH)) {\n+\t\t\t\tqh->channel->halt_status = DWC_OTG_HC_XFER_URB_DEQUEUE;\n+\t\t\t\tqh->channel->halt_pending = 1;\n+\t\t\t\tif (hcd->fiq_state->channel[n].fsm == FIQ_HS_ISOC_TURBO ||\n+\t\t\t\t    hcd->fiq_state->channel[n].fsm == FIQ_HS_ISOC_SLEEPING)\n+\t\t\t\t\thcd->fiq_state->channel[n].fsm = FIQ_HS_ISOC_ABORTED;\n+\t\t\t\t/* We're called from disconnect callback or in the middle of freeing the HCD here,\n+\t\t\t\t * so FIQ is disabled, top-level interrupts masked and we're holding the spinlock.\n+\t\t\t\t * No further URBs will be submitted, but wait 1 microframe for any previously\n+\t\t\t\t * submitted periodic DMA to finish.\n+\t\t\t\t */\n+\t\t\t\tif (!quiesced) {\n+\t\t\t\t\tudelay(125);\n+\t\t\t\t\tquiesced = 1;\n+\t\t\t\t}\n+\t\t\t} else {\n+\t\t\t\tdwc_otg_hc_halt(hcd->core_if, qh->channel,\n+\t\t\t\t\t\tDWC_OTG_HC_XFER_URB_DEQUEUE);\n+\t\t\t}\n+\t\t\tqh->channel = NULL;\n+\t\t}\n+\t\tdwc_otg_hcd_qh_remove(hcd, qh);\n+\t}\n+}\n+\n+/**\n+ * Responds with an error status of ESHUTDOWN to all URBs in the non-periodic\n+ * and periodic schedules. The QTD associated with each URB is removed from\n+ * the schedule and freed. This function may be called when a disconnect is\n+ * detected or when the HCD is being stopped.\n+ */\n+static void kill_all_urbs(dwc_otg_hcd_t * hcd)\n+{\n+\tkill_urbs_in_qh_list(hcd, &hcd->non_periodic_sched_inactive);\n+\tkill_urbs_in_qh_list(hcd, &hcd->non_periodic_sched_active);\n+\tkill_urbs_in_qh_list(hcd, &hcd->periodic_sched_inactive);\n+\tkill_urbs_in_qh_list(hcd, &hcd->periodic_sched_ready);\n+\tkill_urbs_in_qh_list(hcd, &hcd->periodic_sched_assigned);\n+\tkill_urbs_in_qh_list(hcd, &hcd->periodic_sched_queued);\n+}\n+\n+/**\n+ * Start the connection timer.  An OTG host is required to display a\n+ * message if the device does not connect within 10 seconds.  The\n+ * timer is deleted if a port connect interrupt occurs before the\n+ * timer expires.\n+ */\n+static void dwc_otg_hcd_start_connect_timer(dwc_otg_hcd_t * hcd)\n+{\n+\tDWC_TIMER_SCHEDULE(hcd->conn_timer, 10000 /* 10 secs */ );\n+}\n+\n+/**\n+ * HCD Callback function for disconnect of the HCD.\n+ *\n+ * @param p void pointer to the <code>struct usb_hcd</code>\n+ */\n+static int32_t dwc_otg_hcd_session_start_cb(void *p)\n+{\n+\tdwc_otg_hcd_t *dwc_otg_hcd;\n+\tDWC_DEBUGPL(DBG_HCDV, \"%s(%p)\\n\", __func__, p);\n+\tdwc_otg_hcd = p;\n+\tdwc_otg_hcd_start_connect_timer(dwc_otg_hcd);\n+\treturn 1;\n+}\n+\n+/**\n+ * HCD Callback function for starting the HCD when A-Cable is\n+ * connected.\n+ *\n+ * @param p void pointer to the <code>struct usb_hcd</code>\n+ */\n+static int32_t dwc_otg_hcd_start_cb(void *p)\n+{\n+\tdwc_otg_hcd_t *dwc_otg_hcd = p;\n+\tdwc_otg_core_if_t *core_if;\n+\thprt0_data_t hprt0;\n+\n+\tcore_if = dwc_otg_hcd->core_if;\n+\n+\tif (core_if->op_state == B_HOST) {\n+\t\t/*\n+\t\t * Reset the port.  During a HNP mode switch the reset\n+\t\t * needs to occur within 1ms and have a duration of at\n+\t\t * least 50ms.\n+\t\t */\n+\t\thprt0.d32 = dwc_otg_read_hprt0(core_if);\n+\t\thprt0.b.prtrst = 1;\n+\t\tDWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);\n+\t}\n+\tDWC_WORKQ_SCHEDULE_DELAYED(core_if->wq_otg,\n+\t\t\t\t   hcd_start_func, dwc_otg_hcd, 50,\n+\t\t\t\t   \"start hcd\");\n+\n+\treturn 1;\n+}\n+\n+/**\n+ * HCD Callback function for disconnect of the HCD.\n+ *\n+ * @param p void pointer to the <code>struct usb_hcd</code>\n+ */\n+static int32_t dwc_otg_hcd_disconnect_cb(void *p)\n+{\n+\tgintsts_data_t intr;\n+\tdwc_otg_hcd_t *dwc_otg_hcd = p;\n+\n+\tDWC_SPINLOCK(dwc_otg_hcd->lock);\n+\t/*\n+\t * Set status flags for the hub driver.\n+\t */\n+\tdwc_otg_hcd->flags.b.port_connect_status_change = 1;\n+\tdwc_otg_hcd->flags.b.port_connect_status = 0;\n+\tif(fiq_enable) {\n+\t\tlocal_fiq_disable();\n+\t\tfiq_fsm_spin_lock(&dwc_otg_hcd->fiq_state->lock);\n+\t}\n+\t/*\n+\t * Shutdown any transfers in process by clearing the Tx FIFO Empty\n+\t * interrupt mask and status bits and disabling subsequent host\n+\t * channel interrupts.\n+\t */\n+\tintr.d32 = 0;\n+\tintr.b.nptxfempty = 1;\n+\tintr.b.ptxfempty = 1;\n+\tintr.b.hcintr = 1;\n+\tDWC_MODIFY_REG32(&dwc_otg_hcd->core_if->core_global_regs->gintmsk,\n+\t\t\t intr.d32, 0);\n+\tDWC_MODIFY_REG32(&dwc_otg_hcd->core_if->core_global_regs->gintsts,\n+\t\t\t intr.d32, 0);\n+\n+\tdel_timers(dwc_otg_hcd);\n+\n+\t/*\n+\t * Turn off the vbus power only if the core has transitioned to device\n+\t * mode. If still in host mode, need to keep power on to detect a\n+\t * reconnection.\n+\t */\n+\tif (dwc_otg_is_device_mode(dwc_otg_hcd->core_if)) {\n+\t\tif (dwc_otg_hcd->core_if->op_state != A_SUSPEND) {\n+\t\t\thprt0_data_t hprt0 = {.d32 = 0 };\n+\t\t\tDWC_PRINTF(\"Disconnect: PortPower off\\n\");\n+\t\t\thprt0.b.prtpwr = 0;\n+\t\t\tDWC_WRITE_REG32(dwc_otg_hcd->core_if->host_if->hprt0,\n+\t\t\t\t\thprt0.d32);\n+\t\t}\n+\n+\t\tdwc_otg_disable_host_interrupts(dwc_otg_hcd->core_if);\n+\t}\n+\n+\t/* Respond with an error status to all URBs in the schedule. */\n+\tkill_all_urbs(dwc_otg_hcd);\n+\n+\tif (dwc_otg_is_host_mode(dwc_otg_hcd->core_if)) {\n+\t\t/* Clean up any host channels that were in use. */\n+\t\tint num_channels;\n+\t\tint i;\n+\t\tdwc_hc_t *channel;\n+\t\tdwc_otg_hc_regs_t *hc_regs;\n+\t\thcchar_data_t hcchar;\n+\n+\t\tnum_channels = dwc_otg_hcd->core_if->core_params->host_channels;\n+\n+\t\tif (!dwc_otg_hcd->core_if->dma_enable) {\n+\t\t\t/* Flush out any channel requests in slave mode. */\n+\t\t\tfor (i = 0; i < num_channels; i++) {\n+\t\t\t\tchannel = dwc_otg_hcd->hc_ptr_array[i];\n+\t\t\t\tif (DWC_CIRCLEQ_EMPTY_ENTRY\n+\t\t\t\t    (channel, hc_list_entry)) {\n+\t\t\t\t\thc_regs =\n+\t\t\t\t\t    dwc_otg_hcd->core_if->\n+\t\t\t\t\t    host_if->hc_regs[i];\n+\t\t\t\t\thcchar.d32 =\n+\t\t\t\t\t    DWC_READ_REG32(&hc_regs->hcchar);\n+\t\t\t\t\tif (hcchar.b.chen) {\n+\t\t\t\t\t\thcchar.b.chen = 0;\n+\t\t\t\t\t\thcchar.b.chdis = 1;\n+\t\t\t\t\t\thcchar.b.epdir = 0;\n+\t\t\t\t\t\tDWC_WRITE_REG32\n+\t\t\t\t\t\t    (&hc_regs->hcchar,\n+\t\t\t\t\t\t     hcchar.d32);\n+\t\t\t\t\t}\n+\t\t\t\t}\n+\t\t\t}\n+\t\t}\n+\n+\t\tif(fiq_fsm_enable) {\n+\t\t\tfor(i=0; i < 128; i++) {\n+\t\t\t\tdwc_otg_hcd->hub_port[i] = 0;\n+\t\t\t}\n+\t\t}\n+\t}\n+\n+\tif(fiq_enable) {\n+\t\tfiq_fsm_spin_unlock(&dwc_otg_hcd->fiq_state->lock);\n+\t\tlocal_fiq_enable();\n+\t}\n+\n+\tif (dwc_otg_hcd->fops->disconnect) {\n+\t\tdwc_otg_hcd->fops->disconnect(dwc_otg_hcd);\n+\t}\n+\n+\tDWC_SPINUNLOCK(dwc_otg_hcd->lock);\n+\treturn 1;\n+}\n+\n+/**\n+ * HCD Callback function for stopping the HCD.\n+ *\n+ * @param p void pointer to the <code>struct usb_hcd</code>\n+ */\n+static int32_t dwc_otg_hcd_stop_cb(void *p)\n+{\n+\tdwc_otg_hcd_t *dwc_otg_hcd = p;\n+\n+\tDWC_DEBUGPL(DBG_HCDV, \"%s(%p)\\n\", __func__, p);\n+\tdwc_otg_hcd_stop(dwc_otg_hcd);\n+\treturn 1;\n+}\n+\n+#ifdef CONFIG_USB_DWC_OTG_LPM\n+/**\n+ * HCD Callback function for sleep of HCD.\n+ *\n+ * @param p void pointer to the <code>struct usb_hcd</code>\n+ */\n+static int dwc_otg_hcd_sleep_cb(void *p)\n+{\n+\tdwc_otg_hcd_t *hcd = p;\n+\n+\tdwc_otg_hcd_free_hc_from_lpm(hcd);\n+\n+\treturn 0;\n+}\n+#endif\n+\n+\n+/**\n+ * HCD Callback function for Remote Wakeup.\n+ *\n+ * @param p void pointer to the <code>struct usb_hcd</code>\n+ */\n+static int dwc_otg_hcd_rem_wakeup_cb(void *p)\n+{\n+\tdwc_otg_hcd_t *hcd = p;\n+\n+\tif (hcd->core_if->lx_state == DWC_OTG_L2) {\n+\t\thcd->flags.b.port_suspend_change = 1;\n+\t}\n+#ifdef CONFIG_USB_DWC_OTG_LPM\n+\telse {\n+\t\thcd->flags.b.port_l1_change = 1;\n+\t}\n+#endif\n+\treturn 0;\n+}\n+\n+/**\n+ * Halts the DWC_otg host mode operations in a clean manner. USB transfers are\n+ * stopped.\n+ */\n+void dwc_otg_hcd_stop(dwc_otg_hcd_t * hcd)\n+{\n+\thprt0_data_t hprt0 = {.d32 = 0 };\n+\n+\tDWC_DEBUGPL(DBG_HCD, \"DWC OTG HCD STOP\\n\");\n+\n+\t/*\n+\t * The root hub should be disconnected before this function is called.\n+\t * The disconnect will clear the QTD lists (via ..._hcd_urb_dequeue)\n+\t * and the QH lists (via ..._hcd_endpoint_disable).\n+\t */\n+\n+\t/* Turn off all host-specific interrupts. */\n+\tdwc_otg_disable_host_interrupts(hcd->core_if);\n+\n+\t/* Turn off the vbus power */\n+\tDWC_PRINTF(\"PortPower off\\n\");\n+\thprt0.b.prtpwr = 0;\n+\tDWC_WRITE_REG32(hcd->core_if->host_if->hprt0, hprt0.d32);\n+\tdwc_mdelay(1);\n+}\n+\n+int dwc_otg_hcd_urb_enqueue(dwc_otg_hcd_t * hcd,\n+\t\t\t    dwc_otg_hcd_urb_t * dwc_otg_urb, void **ep_handle,\n+\t\t\t    int atomic_alloc)\n+{\n+\tint retval = 0;\n+\tuint8_t needs_scheduling = 0;\n+\tdwc_otg_transaction_type_e tr_type;\n+\tdwc_otg_qtd_t *qtd;\n+\tgintmsk_data_t intr_mask = {.d32 = 0 };\n+\thprt0_data_t hprt0 = { .d32 = 0 };\n+\n+#ifdef DEBUG /* integrity checks (Broadcom) */\n+\tif (NULL == hcd->core_if) {\n+\t\tDWC_ERROR(\"**** DWC OTG HCD URB Enqueue - HCD has NULL core_if\\n\");\n+\t\t/* No longer connected. */\n+\t\treturn -DWC_E_INVALID;\n+\t}\n+#endif\n+\tif (!hcd->flags.b.port_connect_status) {\n+\t\t/* No longer connected. */\n+\t\tDWC_ERROR(\"Not connected\\n\");\n+\t\treturn -DWC_E_NO_DEVICE;\n+\t}\n+\n+\t/* Some core configurations cannot support LS traffic on a FS root port */\n+\tif ((hcd->fops->speed(hcd, dwc_otg_urb->priv) == USB_SPEED_LOW) &&\n+\t\t(hcd->core_if->hwcfg2.b.fs_phy_type == 1) &&\n+\t\t(hcd->core_if->hwcfg2.b.hs_phy_type == 1)) {\n+\t\t\thprt0.d32 = DWC_READ_REG32(hcd->core_if->host_if->hprt0);\n+\t\t\tif (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_FULL_SPEED) {\n+\t\t\t\treturn -DWC_E_NO_DEVICE;\n+\t\t\t}\n+\t}\n+\n+\tqtd = dwc_otg_hcd_qtd_create(dwc_otg_urb, atomic_alloc);\n+\tif (qtd == NULL) {\n+\t\tDWC_ERROR(\"DWC OTG HCD URB Enqueue failed creating QTD\\n\");\n+\t\treturn -DWC_E_NO_MEMORY;\n+\t}\n+#ifdef DEBUG /* integrity checks (Broadcom) */\n+\tif (qtd->urb == NULL) {\n+\t\tDWC_ERROR(\"**** DWC OTG HCD URB Enqueue created QTD with no URBs\\n\");\n+\t\treturn -DWC_E_NO_MEMORY;\n+\t}\n+\tif (qtd->urb->priv == NULL) {\n+\t\tDWC_ERROR(\"**** DWC OTG HCD URB Enqueue created QTD URB with no URB handle\\n\");\n+\t\treturn -DWC_E_NO_MEMORY;\n+\t}\n+#endif\n+\tintr_mask.d32 = DWC_READ_REG32(&hcd->core_if->core_global_regs->gintmsk);\n+\tif(!intr_mask.b.sofintr || fiq_enable) needs_scheduling = 1;\n+\tif((((dwc_otg_qh_t *)ep_handle)->ep_type == UE_BULK) && !(qtd->urb->flags & URB_GIVEBACK_ASAP))\n+\t\t/* Do not schedule SG transactions until qtd has URB_GIVEBACK_ASAP set */\n+\t\tneeds_scheduling = 0;\n+\n+\tretval = dwc_otg_hcd_qtd_add(qtd, hcd, (dwc_otg_qh_t **) ep_handle, atomic_alloc);\n+            // creates a new queue in ep_handle if it doesn't exist already\n+\tif (retval < 0) {\n+\t\tDWC_ERROR(\"DWC OTG HCD URB Enqueue failed adding QTD. \"\n+\t\t\t  \"Error status %d\\n\", retval);\n+\t\tdwc_otg_hcd_qtd_free(qtd);\n+\t\treturn retval;\n+\t}\n+\n+\tif(needs_scheduling) {\n+\t\ttr_type = dwc_otg_hcd_select_transactions(hcd);\n+\t\tif (tr_type != DWC_OTG_TRANSACTION_NONE) {\n+\t\t\tdwc_otg_hcd_queue_transactions(hcd, tr_type);\n+\t\t}\n+\t}\n+\treturn retval;\n+}\n+\n+int dwc_otg_hcd_urb_dequeue(dwc_otg_hcd_t * hcd,\n+\t\t\t    dwc_otg_hcd_urb_t * dwc_otg_urb)\n+{\n+\tdwc_otg_qh_t *qh;\n+\tdwc_otg_qtd_t *urb_qtd;\n+\tBUG_ON(!hcd);\n+\tBUG_ON(!dwc_otg_urb);\n+\n+#ifdef DEBUG /* integrity checks (Broadcom) */\n+\n+\tif (hcd == NULL) {\n+\t\tDWC_ERROR(\"**** DWC OTG HCD URB Dequeue has NULL HCD\\n\");\n+\t\treturn -DWC_E_INVALID;\n+\t}\n+\tif (dwc_otg_urb == NULL) {\n+\t\tDWC_ERROR(\"**** DWC OTG HCD URB Dequeue has NULL URB\\n\");\n+\t\treturn -DWC_E_INVALID;\n+\t}\n+\tif (dwc_otg_urb->qtd == NULL) {\n+\t\tDWC_ERROR(\"**** DWC OTG HCD URB Dequeue with NULL QTD\\n\");\n+\t\treturn -DWC_E_INVALID;\n+\t}\n+\turb_qtd = dwc_otg_urb->qtd;\n+\tBUG_ON(!urb_qtd);\n+\tif (urb_qtd->qh == NULL) {\n+\t\tDWC_ERROR(\"**** DWC OTG HCD URB Dequeue with QTD with NULL Q handler\\n\");\n+\t\treturn -DWC_E_INVALID;\n+\t}\n+#else\n+\turb_qtd = dwc_otg_urb->qtd;\n+\tBUG_ON(!urb_qtd);\n+#endif\n+\tqh = urb_qtd->qh;\n+\tBUG_ON(!qh);\n+\tif (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {\n+\t\tif (urb_qtd->in_process) {\n+\t\t\tdump_channel_info(hcd, qh);\n+\t\t}\n+\t}\n+#ifdef DEBUG /* integrity checks (Broadcom) */\n+\tif (hcd->core_if == NULL) {\n+\t\tDWC_ERROR(\"**** DWC OTG HCD URB Dequeue HCD has NULL core_if\\n\");\n+\t\treturn -DWC_E_INVALID;\n+\t}\n+#endif\n+\tif (urb_qtd->in_process && qh->channel) {\n+\t\t/* The QTD is in process (it has been assigned to a channel). */\n+\t\tif (hcd->flags.b.port_connect_status) {\n+\t\t\tint n = qh->channel->hc_num;\n+\t\t\t/*\n+\t\t\t * If still connected (i.e. in host mode), halt the\n+\t\t\t * channel so it can be used for other transfers. If\n+\t\t\t * no longer connected, the host registers can't be\n+\t\t\t * written to halt the channel since the core is in\n+\t\t\t * device mode.\n+\t\t\t */\n+\t\t\t/* In FIQ FSM mode, we need to shut down carefully.\n+\t\t\t * The FIQ may attempt to restart a disabled channel */\n+\t\t\tif (fiq_fsm_enable && (hcd->fiq_state->channel[n].fsm != FIQ_PASSTHROUGH)) {\n+\t\t\t\tint retries = 3;\n+\t\t\t\tint running = 0;\n+\t\t\t\tenum fiq_fsm_state state;\n+\n+\t\t\t\tlocal_fiq_disable();\n+\t\t\t\tfiq_fsm_spin_lock(&hcd->fiq_state->lock);\n+\t\t\t\tqh->channel->halt_status = DWC_OTG_HC_XFER_URB_DEQUEUE;\n+\t\t\t\tqh->channel->halt_pending = 1;\n+\t\t\t\tif (hcd->fiq_state->channel[n].fsm == FIQ_HS_ISOC_TURBO ||\n+\t\t\t\t    hcd->fiq_state->channel[n].fsm == FIQ_HS_ISOC_SLEEPING)\n+\t\t\t\t\thcd->fiq_state->channel[n].fsm = FIQ_HS_ISOC_ABORTED;\n+\t\t\t\tfiq_fsm_spin_unlock(&hcd->fiq_state->lock);\n+\t\t\t\tlocal_fiq_enable();\n+\n+\t\t\t\tif (dwc_qh_is_non_per(qh)) {\n+\t\t\t\t\tdo {\n+\t\t\t\t\t\tstate = READ_ONCE(hcd->fiq_state->channel[n].fsm);\n+\t\t\t\t\t\trunning = (state != FIQ_NP_SPLIT_DONE) &&\n+\t\t\t\t\t\t\t  (state != FIQ_NP_SPLIT_LS_ABORTED) &&\n+\t\t\t\t\t\t\t  (state != FIQ_NP_SPLIT_HS_ABORTED);\n+\t\t\t\t\t\tif (!running)\n+\t\t\t\t\t\t\tbreak;\n+\t\t\t\t\t\tudelay(125);\n+\t\t\t\t\t} while(--retries);\n+\t\t\t\t\tif (!retries)\n+\t\t\t\t\t\tDWC_WARN(\"Timed out waiting for FSM NP transfer to complete on %d\",\n+\t\t\t\t\t\t\t qh->channel->hc_num);\n+\t\t\t\t}\n+\t\t\t} else {\n+\t\t\t\tdwc_otg_hc_halt(hcd->core_if, qh->channel,\n+\t\t\t\t\t\tDWC_OTG_HC_XFER_URB_DEQUEUE);\n+\t\t\t}\n+\t\t}\n+\t}\n+\n+\t/*\n+\t * Free the QTD and clean up the associated QH. Leave the QH in the\n+\t * schedule if it has any remaining QTDs.\n+\t */\n+\n+\tDWC_DEBUGPL(DBG_HCD, \"DWC OTG HCD URB Dequeue - \"\n+                    \"delete %sQueue handler\\n\",\n+                    hcd->core_if->dma_desc_enable?\"DMA \":\"\");\n+\tif (!hcd->core_if->dma_desc_enable) {\n+\t\tuint8_t b = urb_qtd->in_process;\n+\t\tif (nak_holdoff && qh->do_split && dwc_qh_is_non_per(qh))\n+\t\t\tqh->nak_frame = 0xFFFF;\n+\t\tdwc_otg_hcd_qtd_remove_and_free(hcd, urb_qtd, qh);\n+\t\tif (b) {\n+\t\t\tdwc_otg_hcd_qh_deactivate(hcd, qh, 0);\n+\t\t\tqh->channel = NULL;\n+\t\t} else if (DWC_CIRCLEQ_EMPTY(&qh->qtd_list)) {\n+\t\t\tdwc_otg_hcd_qh_remove(hcd, qh);\n+\t\t}\n+\t} else {\n+\t\tdwc_otg_hcd_qtd_remove_and_free(hcd, urb_qtd, qh);\n+\t}\n+\treturn 0;\n+}\n+\n+int dwc_otg_hcd_endpoint_disable(dwc_otg_hcd_t * hcd, void *ep_handle,\n+\t\t\t\t int retry)\n+{\n+\tdwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;\n+\tint retval = 0;\n+\tdwc_irqflags_t flags;\n+\n+\tif (retry < 0) {\n+\t\tretval = -DWC_E_INVALID;\n+\t\tgoto done;\n+\t}\n+\n+\tif (!qh) {\n+\t\tretval = -DWC_E_INVALID;\n+\t\tgoto done;\n+\t}\n+\n+\tDWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);\n+\n+\twhile (!DWC_CIRCLEQ_EMPTY(&qh->qtd_list) && retry) {\n+\t\tDWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);\n+\t\tretry--;\n+\t\tdwc_msleep(5);\n+\t\tDWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);\n+\t}\n+\n+\tdwc_otg_hcd_qh_remove(hcd, qh);\n+\n+\tDWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);\n+\t/*\n+\t * Split dwc_otg_hcd_qh_remove_and_free() into qh_remove\n+\t * and qh_free to prevent stack dump on DWC_DMA_FREE() with\n+\t * irq_disabled (spinlock_irqsave) in dwc_otg_hcd_desc_list_free()\n+\t * and dwc_otg_hcd_frame_list_alloc().\n+\t */\n+\tdwc_otg_hcd_qh_free(hcd, qh);\n+\n+done:\n+\treturn retval;\n+}\n+\n+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,30)\n+int dwc_otg_hcd_endpoint_reset(dwc_otg_hcd_t * hcd, void *ep_handle)\n+{\n+\tint retval = 0;\n+\tdwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;\n+\tif (!qh)\n+\t\treturn -DWC_E_INVALID;\n+\n+\tqh->data_toggle = DWC_OTG_HC_PID_DATA0;\n+\treturn retval;\n+}\n+#endif\n+\n+/**\n+ * HCD Callback structure for handling mode switching.\n+ */\n+static dwc_otg_cil_callbacks_t hcd_cil_callbacks = {\n+\t.start = dwc_otg_hcd_start_cb,\n+\t.stop = dwc_otg_hcd_stop_cb,\n+\t.disconnect = dwc_otg_hcd_disconnect_cb,\n+\t.session_start = dwc_otg_hcd_session_start_cb,\n+\t.resume_wakeup = dwc_otg_hcd_rem_wakeup_cb,\n+#ifdef CONFIG_USB_DWC_OTG_LPM\n+\t.sleep = dwc_otg_hcd_sleep_cb,\n+#endif\n+\t.p = 0,\n+};\n+\n+/**\n+ * Reset tasklet function\n+ */\n+static void reset_tasklet_func(void *data)\n+{\n+\tdwc_otg_hcd_t *dwc_otg_hcd = (dwc_otg_hcd_t *) data;\n+\tdwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;\n+\thprt0_data_t hprt0;\n+\n+\tDWC_DEBUGPL(DBG_HCDV, \"USB RESET tasklet called\\n\");\n+\n+\thprt0.d32 = dwc_otg_read_hprt0(core_if);\n+\thprt0.b.prtrst = 1;\n+\tDWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);\n+\tdwc_mdelay(60);\n+\n+\thprt0.b.prtrst = 0;\n+\tDWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);\n+\tdwc_otg_hcd->flags.b.port_reset_change = 1;\n+}\n+\n+static void completion_tasklet_func(void *ptr)\n+{\n+\tdwc_otg_hcd_t *hcd = (dwc_otg_hcd_t *) ptr;\n+\tstruct urb *urb;\n+\turb_tq_entry_t *item;\n+\tdwc_irqflags_t flags;\n+\n+\t/* This could just be spin_lock_irq */\n+\tDWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);\n+\twhile (!DWC_TAILQ_EMPTY(&hcd->completed_urb_list)) {\n+\t\titem = DWC_TAILQ_FIRST(&hcd->completed_urb_list);\n+\t\turb = item->urb;\n+\t\tDWC_TAILQ_REMOVE(&hcd->completed_urb_list, item,\n+\t\t\t\turb_tq_entries);\n+\t\tDWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);\n+\t\tDWC_FREE(item);\n+\n+\t\tusb_hcd_giveback_urb(hcd->priv, urb, urb->status);\n+\n+\n+\t\tDWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);\n+\t}\n+\tDWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);\n+\treturn;\n+}\n+\n+static void qh_list_free(dwc_otg_hcd_t * hcd, dwc_list_link_t * qh_list)\n+{\n+\tdwc_list_link_t *item;\n+\tdwc_otg_qh_t *qh;\n+\tdwc_irqflags_t flags;\n+\n+\tif (!qh_list->next) {\n+\t\t/* The list hasn't been initialized yet. */\n+\t\treturn;\n+\t}\n+\t/*\n+\t * Hold spinlock here. Not needed in that case if bellow\n+\t * function is being called from ISR\n+\t */\n+\tDWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);\n+\t/* Ensure there are no QTDs or URBs left. */\n+\tkill_urbs_in_qh_list(hcd, qh_list);\n+\tDWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);\n+\n+\tDWC_LIST_FOREACH(item, qh_list) {\n+\t\tqh = DWC_LIST_ENTRY(item, dwc_otg_qh_t, qh_list_entry);\n+\t\tdwc_otg_hcd_qh_remove_and_free(hcd, qh);\n+\t}\n+}\n+\n+/**\n+ * Exit from Hibernation if Host did not detect SRP from connected SRP capable\n+ * Device during SRP time by host power up.\n+ */\n+void dwc_otg_hcd_power_up(void *ptr)\n+{\n+\tgpwrdn_data_t gpwrdn = {.d32 = 0 };\n+\tdwc_otg_core_if_t *core_if = (dwc_otg_core_if_t *) ptr;\n+\n+\tDWC_PRINTF(\"%s called\\n\", __FUNCTION__);\n+\n+\tif (!core_if->hibernation_suspend) {\n+\t\tDWC_PRINTF(\"Already exited from Hibernation\\n\");\n+\t\treturn;\n+\t}\n+\n+\t/* Switch on the voltage to the core */\n+\tgpwrdn.b.pwrdnswtch = 1;\n+\tDWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);\n+\tdwc_udelay(10);\n+\n+\t/* Reset the core */\n+\tgpwrdn.d32 = 0;\n+\tgpwrdn.b.pwrdnrstn = 1;\n+\tDWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);\n+\tdwc_udelay(10);\n+\n+\t/* Disable power clamps */\n+\tgpwrdn.d32 = 0;\n+\tgpwrdn.b.pwrdnclmp = 1;\n+\tDWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);\n+\n+\t/* Remove reset the core signal */\n+\tgpwrdn.d32 = 0;\n+\tgpwrdn.b.pwrdnrstn = 1;\n+\tDWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);\n+\tdwc_udelay(10);\n+\n+\t/* Disable PMU interrupt */\n+\tgpwrdn.d32 = 0;\n+\tgpwrdn.b.pmuintsel = 1;\n+\tDWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);\n+\n+\tcore_if->hibernation_suspend = 0;\n+\n+\t/* Disable PMU */\n+\tgpwrdn.d32 = 0;\n+\tgpwrdn.b.pmuactv = 1;\n+\tDWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);\n+\tdwc_udelay(10);\n+\n+\t/* Enable VBUS */\n+\tgpwrdn.d32 = 0;\n+\tgpwrdn.b.dis_vbus = 1;\n+\tDWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);\n+\n+\tcore_if->op_state = A_HOST;\n+\tdwc_otg_core_init(core_if);\n+\tdwc_otg_enable_global_interrupts(core_if);\n+\tcil_hcd_start(core_if);\n+}\n+\n+void dwc_otg_cleanup_fiq_channel(dwc_otg_hcd_t *hcd, uint32_t num)\n+{\n+\tstruct fiq_channel_state *st = &hcd->fiq_state->channel[num];\n+\tstruct fiq_dma_blob *blob = hcd->fiq_dmab;\n+\tint i;\n+\n+\tst->fsm = FIQ_PASSTHROUGH;\n+\tst->hcchar_copy.d32 = 0;\n+\tst->hcsplt_copy.d32 = 0;\n+\tst->hcint_copy.d32 = 0;\n+\tst->hcintmsk_copy.d32 = 0;\n+\tst->hctsiz_copy.d32 = 0;\n+\tst->hcdma_copy.d32 = 0;\n+\tst->nr_errors = 0;\n+\tst->hub_addr = 0;\n+\tst->port_addr = 0;\n+\tst->expected_uframe = 0;\n+\tst->nrpackets = 0;\n+\tst->dma_info.index = 0;\n+\tfor (i = 0; i < 6; i++)\n+\t\tst->dma_info.slot_len[i] = 255;\n+\tst->hs_isoc_info.index = 0;\n+\tst->hs_isoc_info.iso_desc = NULL;\n+\tst->hs_isoc_info.nrframes = 0;\n+\n+\tDWC_MEMSET(&blob->channel[num].index[0], 0x6b, 1128);\n+}\n+\n+/**\n+ * Frees secondary storage associated with the dwc_otg_hcd structure contained\n+ * in the struct usb_hcd field.\n+ */\n+static void dwc_otg_hcd_free(dwc_otg_hcd_t * dwc_otg_hcd)\n+{\n+\tstruct device *dev = dwc_otg_hcd_to_dev(dwc_otg_hcd);\n+\tint i;\n+\n+\tDWC_DEBUGPL(DBG_HCD, \"DWC OTG HCD FREE\\n\");\n+\n+\tdel_timers(dwc_otg_hcd);\n+\n+\t/* Free memory for QH/QTD lists */\n+\tqh_list_free(dwc_otg_hcd, &dwc_otg_hcd->non_periodic_sched_inactive);\n+\tqh_list_free(dwc_otg_hcd, &dwc_otg_hcd->non_periodic_sched_active);\n+\tqh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_inactive);\n+\tqh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_ready);\n+\tqh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_assigned);\n+\tqh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_queued);\n+\n+\t/* Free memory for the host channels. */\n+\tfor (i = 0; i < MAX_EPS_CHANNELS; i++) {\n+\t\tdwc_hc_t *hc = dwc_otg_hcd->hc_ptr_array[i];\n+\n+#ifdef DEBUG\n+\t\tif (dwc_otg_hcd->core_if->hc_xfer_timer[i]) {\n+\t\t\tDWC_TIMER_FREE(dwc_otg_hcd->core_if->hc_xfer_timer[i]);\n+\t\t}\n+#endif\n+\t\tif (hc != NULL) {\n+\t\t\tDWC_DEBUGPL(DBG_HCDV, \"HCD Free channel #%i, hc=%p\\n\",\n+\t\t\t\t    i, hc);\n+\t\t\tDWC_FREE(hc);\n+\t\t}\n+\t}\n+\n+\tif (dwc_otg_hcd->core_if->dma_enable) {\n+\t\tif (dwc_otg_hcd->status_buf_dma) {\n+\t\t\tDWC_DMA_FREE(dev, DWC_OTG_HCD_STATUS_BUF_SIZE,\n+\t\t\t\t     dwc_otg_hcd->status_buf,\n+\t\t\t\t     dwc_otg_hcd->status_buf_dma);\n+\t\t}\n+\t} else if (dwc_otg_hcd->status_buf != NULL) {\n+\t\tDWC_FREE(dwc_otg_hcd->status_buf);\n+\t}\n+\tDWC_SPINLOCK_FREE(dwc_otg_hcd->lock);\n+\t/* Set core_if's lock pointer to NULL */\n+\tdwc_otg_hcd->core_if->lock = NULL;\n+\n+\tDWC_TIMER_FREE(dwc_otg_hcd->conn_timer);\n+\tDWC_TASK_FREE(dwc_otg_hcd->reset_tasklet);\n+\tDWC_TASK_FREE(dwc_otg_hcd->completion_tasklet);\n+\tDWC_DMA_FREE(dev, 16, dwc_otg_hcd->fiq_state->dummy_send,\n+\t\t     dwc_otg_hcd->fiq_state->dummy_send_dma);\n+\tDWC_FREE(dwc_otg_hcd->fiq_state);\n+\n+#ifdef DWC_DEV_SRPCAP\n+\tif (dwc_otg_hcd->core_if->power_down == 2 &&\n+\t    dwc_otg_hcd->core_if->pwron_timer) {\n+\t\tDWC_TIMER_FREE(dwc_otg_hcd->core_if->pwron_timer);\n+\t}\n+#endif\n+\tDWC_FREE(dwc_otg_hcd);\n+}\n+\n+int dwc_otg_hcd_init(dwc_otg_hcd_t * hcd, dwc_otg_core_if_t * core_if)\n+{\n+\tstruct device *dev = dwc_otg_hcd_to_dev(hcd);\n+\tint retval = 0;\n+\tint num_channels;\n+\tint i;\n+\tdwc_hc_t *channel;\n+\n+#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_SPINLOCK))\n+\tDWC_SPINLOCK_ALLOC_LINUX_DEBUG(hcd->lock);\n+#else\n+\thcd->lock = DWC_SPINLOCK_ALLOC();\n+#endif\n+        DWC_DEBUGPL(DBG_HCDV, \"init of HCD %p given core_if %p\\n\",\n+                    hcd, core_if);\n+\tif (!hcd->lock) {\n+\t\tDWC_ERROR(\"Could not allocate lock for pcd\");\n+\t\tDWC_FREE(hcd);\n+\t\tretval = -DWC_E_NO_MEMORY;\n+\t\tgoto out;\n+\t}\n+\thcd->core_if = core_if;\n+\n+\t/* Register the HCD CIL Callbacks */\n+\tdwc_otg_cil_register_hcd_callbacks(hcd->core_if,\n+\t\t\t\t\t   &hcd_cil_callbacks, hcd);\n+\n+\t/* Initialize the non-periodic schedule. */\n+\tDWC_LIST_INIT(&hcd->non_periodic_sched_inactive);\n+\tDWC_LIST_INIT(&hcd->non_periodic_sched_active);\n+\n+\t/* Initialize the periodic schedule. */\n+\tDWC_LIST_INIT(&hcd->periodic_sched_inactive);\n+\tDWC_LIST_INIT(&hcd->periodic_sched_ready);\n+\tDWC_LIST_INIT(&hcd->periodic_sched_assigned);\n+\tDWC_LIST_INIT(&hcd->periodic_sched_queued);\n+\tDWC_TAILQ_INIT(&hcd->completed_urb_list);\n+\t/*\n+\t * Create a host channel descriptor for each host channel implemented\n+\t * in the controller. Initialize the channel descriptor array.\n+\t */\n+\tDWC_CIRCLEQ_INIT(&hcd->free_hc_list);\n+\tnum_channels = hcd->core_if->core_params->host_channels;\n+\tDWC_MEMSET(hcd->hc_ptr_array, 0, sizeof(hcd->hc_ptr_array));\n+\tfor (i = 0; i < num_channels; i++) {\n+\t\tchannel = DWC_ALLOC(sizeof(dwc_hc_t));\n+\t\tif (channel == NULL) {\n+\t\t\tretval = -DWC_E_NO_MEMORY;\n+\t\t\tDWC_ERROR(\"%s: host channel allocation failed\\n\",\n+\t\t\t\t  __func__);\n+\t\t\tdwc_otg_hcd_free(hcd);\n+\t\t\tgoto out;\n+\t\t}\n+\t\tchannel->hc_num = i;\n+\t\thcd->hc_ptr_array[i] = channel;\n+#ifdef DEBUG\n+\t\thcd->core_if->hc_xfer_timer[i] =\n+\t\t    DWC_TIMER_ALLOC(\"hc timer\", hc_xfer_timeout,\n+\t\t\t\t    &hcd->core_if->hc_xfer_info[i]);\n+#endif\n+\t\tDWC_DEBUGPL(DBG_HCDV, \"HCD Added channel #%d, hc=%p\\n\", i,\n+\t\t\t    channel);\n+\t}\n+\n+\tif (fiq_enable) {\n+\t\thcd->fiq_state = DWC_ALLOC(sizeof(struct fiq_state) + (sizeof(struct fiq_channel_state) * num_channels));\n+\t\tif (!hcd->fiq_state) {\n+\t\t\tretval = -DWC_E_NO_MEMORY;\n+\t\t\tDWC_ERROR(\"%s: cannot allocate fiq_state structure\\n\", __func__);\n+\t\t\tdwc_otg_hcd_free(hcd);\n+\t\t\tgoto out;\n+\t\t}\n+\t\tDWC_MEMSET(hcd->fiq_state, 0, (sizeof(struct fiq_state) + (sizeof(struct fiq_channel_state) * num_channels)));\n+\n+#ifdef CONFIG_ARM64\n+\t\tspin_lock_init(&hcd->fiq_state->lock);\n+#endif\n+\n+\t\tfor (i = 0; i < num_channels; i++) {\n+\t\t\thcd->fiq_state->channel[i].fsm = FIQ_PASSTHROUGH;\n+\t\t}\n+\t\thcd->fiq_state->dummy_send = DWC_DMA_ALLOC_ATOMIC(dev, 16,\n+\t\t\t\t\t\t\t &hcd->fiq_state->dummy_send_dma);\n+\n+\t\thcd->fiq_stack = DWC_ALLOC(sizeof(struct fiq_stack));\n+\t\tif (!hcd->fiq_stack) {\n+\t\t\tretval = -DWC_E_NO_MEMORY;\n+\t\t\tDWC_ERROR(\"%s: cannot allocate fiq_stack structure\\n\", __func__);\n+\t\t\tdwc_otg_hcd_free(hcd);\n+\t\t\tgoto out;\n+\t\t}\n+\t\thcd->fiq_stack->magic1 = 0xDEADBEEF;\n+\t\thcd->fiq_stack->magic2 = 0xD00DFEED;\n+\t\thcd->fiq_state->gintmsk_saved.d32 = ~0;\n+\t\thcd->fiq_state->haintmsk_saved.b2.chint = ~0;\n+\n+\t\t/* This bit is terrible and uses no API, but necessary. The FIQ has no concept of DMA pools\n+\t\t * (and if it did, would be a lot slower). This allocates a chunk of memory (~9kiB for 8 host channels)\n+\t\t * for use as transaction bounce buffers in a 2-D array. Our access into this chunk is done by some\n+\t\t * moderately readable array casts.\n+\t\t */\n+\t\thcd->fiq_dmab = DWC_DMA_ALLOC(dev, (sizeof(struct fiq_dma_channel) * num_channels), &hcd->fiq_state->dma_base);\n+\t\tDWC_WARN(\"FIQ DMA bounce buffers: virt = %px dma = %pad len=%zu\",\n+\t\t\t\thcd->fiq_dmab, &hcd->fiq_state->dma_base,\n+\t\t\t\tsizeof(struct fiq_dma_channel) * num_channels);\n+\n+\t\tDWC_MEMSET(hcd->fiq_dmab, 0x6b, 9024);\n+\n+\t\t/* pointer for debug in fiq_print */\n+\t\thcd->fiq_state->fiq_dmab = hcd->fiq_dmab;\n+\t\tif (fiq_fsm_enable) {\n+\t\t\tint i;\n+\t\t\tfor (i=0; i < hcd->core_if->core_params->host_channels; i++) {\n+\t\t\t\tdwc_otg_cleanup_fiq_channel(hcd, i);\n+\t\t\t}\n+\t\t\tDWC_PRINTF(\"FIQ FSM acceleration enabled for :\\n%s%s%s%s\",\n+\t\t\t\t(fiq_fsm_mask & 0x1) ? \"Non-periodic Split Transactions\\n\" : \"\",\n+\t\t\t\t(fiq_fsm_mask & 0x2) ? \"Periodic Split Transactions\\n\" : \"\",\n+\t\t\t\t(fiq_fsm_mask & 0x4) ? \"High-Speed Isochronous Endpoints\\n\" : \"\",\n+\t\t\t\t(fiq_fsm_mask & 0x8) ? \"Interrupt/Control Split Transaction hack enabled\\n\" : \"\");\n+\t\t}\n+\t}\n+\n+\t/* Initialize the Connection timeout timer. */\n+\thcd->conn_timer = DWC_TIMER_ALLOC(\"Connection timer\",\n+\t\t\t\t\t  dwc_otg_hcd_connect_timeout, 0);\n+\n+\tprintk(KERN_DEBUG \"dwc_otg: Microframe scheduler %s\\n\", microframe_schedule ? \"enabled\":\"disabled\");\n+\tif (microframe_schedule)\n+\t\tinit_hcd_usecs(hcd);\n+\n+\t/* Initialize reset tasklet. */\n+\thcd->reset_tasklet = DWC_TASK_ALLOC(\"reset_tasklet\", reset_tasklet_func, hcd);\n+\n+\thcd->completion_tasklet = DWC_TASK_ALLOC(\"completion_tasklet\",\n+\t\t\t\t\t\tcompletion_tasklet_func, hcd);\n+#ifdef DWC_DEV_SRPCAP\n+\tif (hcd->core_if->power_down == 2) {\n+\t\t/* Initialize Power on timer for Host power up in case hibernation */\n+\t\thcd->core_if->pwron_timer = DWC_TIMER_ALLOC(\"PWRON TIMER\",\n+\t\t\t\t\t\t\t\t\tdwc_otg_hcd_power_up, core_if);\n+\t}\n+#endif\n+\n+\t/*\n+\t * Allocate space for storing data on status transactions. Normally no\n+\t * data is sent, but this space acts as a bit bucket. This must be\n+\t * done after usb_add_hcd since that function allocates the DMA buffer\n+\t * pool.\n+\t */\n+\tif (hcd->core_if->dma_enable) {\n+\t\thcd->status_buf =\n+\t\t    DWC_DMA_ALLOC(dev, DWC_OTG_HCD_STATUS_BUF_SIZE,\n+\t\t\t\t  &hcd->status_buf_dma);\n+\t} else {\n+\t\thcd->status_buf = DWC_ALLOC(DWC_OTG_HCD_STATUS_BUF_SIZE);\n+\t}\n+\tif (!hcd->status_buf) {\n+\t\tretval = -DWC_E_NO_MEMORY;\n+\t\tDWC_ERROR(\"%s: status_buf allocation failed\\n\", __func__);\n+\t\tdwc_otg_hcd_free(hcd);\n+\t\tgoto out;\n+\t}\n+\n+\thcd->otg_port = 1;\n+\thcd->frame_list = NULL;\n+\thcd->frame_list_dma = 0;\n+\thcd->periodic_qh_count = 0;\n+\n+\tDWC_MEMSET(hcd->hub_port, 0, sizeof(hcd->hub_port));\n+#ifdef FIQ_DEBUG\n+\tDWC_MEMSET(hcd->hub_port_alloc, -1, sizeof(hcd->hub_port_alloc));\n+#endif\n+\n+out:\n+\treturn retval;\n+}\n+\n+void dwc_otg_hcd_remove(dwc_otg_hcd_t * hcd)\n+{\n+\t/* Turn off all host-specific interrupts. */\n+\tdwc_otg_disable_host_interrupts(hcd->core_if);\n+\n+\tdwc_otg_hcd_free(hcd);\n+}\n+\n+/**\n+ * Initializes dynamic portions of the DWC_otg HCD state.\n+ */\n+static void dwc_otg_hcd_reinit(dwc_otg_hcd_t * hcd)\n+{\n+\tint num_channels;\n+\tint i;\n+\tdwc_hc_t *channel;\n+\tdwc_hc_t *channel_tmp;\n+\n+\thcd->flags.d32 = 0;\n+\n+\thcd->non_periodic_qh_ptr = &hcd->non_periodic_sched_active;\n+\tif (!microframe_schedule) {\n+\t\thcd->non_periodic_channels = 0;\n+\t\thcd->periodic_channels = 0;\n+\t} else {\n+\t\thcd->available_host_channels = hcd->core_if->core_params->host_channels;\n+\t}\n+\t/*\n+\t * Put all channels in the free channel list and clean up channel\n+\t * states.\n+\t */\n+\tDWC_CIRCLEQ_FOREACH_SAFE(channel, channel_tmp,\n+\t\t\t\t &hcd->free_hc_list, hc_list_entry) {\n+\t\tDWC_CIRCLEQ_REMOVE(&hcd->free_hc_list, channel, hc_list_entry);\n+\t}\n+\n+\tnum_channels = hcd->core_if->core_params->host_channels;\n+\tfor (i = 0; i < num_channels; i++) {\n+\t\tchannel = hcd->hc_ptr_array[i];\n+\t\tDWC_CIRCLEQ_INSERT_TAIL(&hcd->free_hc_list, channel,\n+\t\t\t\t\thc_list_entry);\n+\t\tdwc_otg_hc_cleanup(hcd->core_if, channel);\n+\t}\n+\n+\t/* Initialize the DWC core for host mode operation. */\n+\tdwc_otg_core_host_init(hcd->core_if);\n+\n+\t/* Set core_if's lock pointer to the hcd->lock */\n+\thcd->core_if->lock = hcd->lock;\n+}\n+\n+/**\n+ * Assigns transactions from a QTD to a free host channel and initializes the\n+ * host channel to perform the transactions. The host channel is removed from\n+ * the free list.\n+ *\n+ * @param hcd The HCD state structure.\n+ * @param qh Transactions from the first QTD for this QH are selected and\n+ * assigned to a free host channel.\n+ */\n+static void assign_and_init_hc(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)\n+{\n+\tdwc_hc_t *hc;\n+\tdwc_otg_qtd_t *qtd;\n+\tdwc_otg_hcd_urb_t *urb;\n+\tvoid* ptr = NULL;\n+\tuint16_t wLength;\n+\tuint32_t intr_enable;\n+\tunsigned long flags;\n+\tgintmsk_data_t gintmsk = { .d32 = 0, };\n+\tstruct device *dev = dwc_otg_hcd_to_dev(hcd);\n+\n+\tqtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list);\n+\n+\turb = qtd->urb;\n+\n+\tDWC_DEBUGPL(DBG_HCDV, \"%s(%p,%p) - urb %x, actual_length %d\\n\", __func__, hcd, qh, (unsigned int)urb, urb->actual_length);\n+\n+\tif (((urb->actual_length < 0) || (urb->actual_length > urb->length)) && !dwc_otg_hcd_is_pipe_in(&urb->pipe_info))\n+\t\turb->actual_length = urb->length;\n+\n+\n+\thc = DWC_CIRCLEQ_FIRST(&hcd->free_hc_list);\n+\n+\t/* Remove the host channel from the free list. */\n+\tDWC_CIRCLEQ_REMOVE_INIT(&hcd->free_hc_list, hc, hc_list_entry);\n+\n+\tqh->channel = hc;\n+\n+\tqtd->in_process = 1;\n+\n+\t/*\n+\t * Use usb_pipedevice to determine device address. This address is\n+\t * 0 before the SET_ADDRESS command and the correct address afterward.\n+\t */\n+\thc->dev_addr = dwc_otg_hcd_get_dev_addr(&urb->pipe_info);\n+\thc->ep_num = dwc_otg_hcd_get_ep_num(&urb->pipe_info);\n+\thc->speed = qh->dev_speed;\n+\thc->max_packet = dwc_max_packet(qh->maxp);\n+\n+\thc->xfer_started = 0;\n+\thc->halt_status = DWC_OTG_HC_XFER_NO_HALT_STATUS;\n+\thc->error_state = (qtd->error_count > 0);\n+\thc->halt_on_queue = 0;\n+\thc->halt_pending = 0;\n+\thc->requests = 0;\n+\n+\t/*\n+\t * The following values may be modified in the transfer type section\n+\t * below. The xfer_len value may be reduced when the transfer is\n+\t * started to accommodate the max widths of the XferSize and PktCnt\n+\t * fields in the HCTSIZn register.\n+\t */\n+\n+\thc->ep_is_in = (dwc_otg_hcd_is_pipe_in(&urb->pipe_info) != 0);\n+\tif (hc->ep_is_in) {\n+\t\thc->do_ping = 0;\n+\t} else {\n+\t\thc->do_ping = qh->ping_state;\n+\t}\n+\n+\thc->data_pid_start = qh->data_toggle;\n+\thc->multi_count = 1;\n+\n+\tif (hcd->core_if->dma_enable) {\n+\t\thc->xfer_buff = (uint8_t *) urb->dma + urb->actual_length;\n+\n+\t\t/* For non-dword aligned case */\n+\t\tif (((unsigned long)hc->xfer_buff & 0x3)\n+\t\t    && !hcd->core_if->dma_desc_enable) {\n+\t\t\tptr = (uint8_t *) urb->buf + urb->actual_length;\n+\t\t}\n+\t} else {\n+\t\thc->xfer_buff = (uint8_t *) urb->buf + urb->actual_length;\n+\t}\n+\thc->xfer_len = urb->length - urb->actual_length;\n+\thc->xfer_count = 0;\n+\n+\t/*\n+\t * Set the split attributes\n+\t */\n+\thc->do_split = 0;\n+\tif (qh->do_split) {\n+\t\tuint32_t hub_addr, port_addr;\n+\t\thc->do_split = 1;\n+\t\thc->start_pkt_count = 1;\n+\t\thc->xact_pos = qtd->isoc_split_pos;\n+\t\t/* We don't need to do complete splits anymore */\n+//\t\tif(fiq_fsm_enable)\n+\t\tif (0)\n+\t\t\thc->complete_split = qtd->complete_split = 0;\n+\t\telse\n+\t\t\thc->complete_split = qtd->complete_split;\n+\n+\t\thcd->fops->hub_info(hcd, urb->priv, &hub_addr, &port_addr);\n+\t\thc->hub_addr = (uint8_t) hub_addr;\n+\t\thc->port_addr = (uint8_t) port_addr;\n+\t}\n+\n+\tswitch (dwc_otg_hcd_get_pipe_type(&urb->pipe_info)) {\n+\tcase UE_CONTROL:\n+\t\thc->ep_type = DWC_OTG_EP_TYPE_CONTROL;\n+\t\tswitch (qtd->control_phase) {\n+\t\tcase DWC_OTG_CONTROL_SETUP:\n+\t\t\tDWC_DEBUGPL(DBG_HCDV, \"  Control setup transaction\\n\");\n+\t\t\thc->do_ping = 0;\n+\t\t\thc->ep_is_in = 0;\n+\t\t\thc->data_pid_start = DWC_OTG_HC_PID_SETUP;\n+\t\t\tif (hcd->core_if->dma_enable) {\n+\t\t\t\thc->xfer_buff = (uint8_t *) urb->setup_dma;\n+\t\t\t} else {\n+\t\t\t\thc->xfer_buff = (uint8_t *) urb->setup_packet;\n+\t\t\t}\n+\t\t\thc->xfer_len = 8;\n+\t\t\tptr = NULL;\n+\t\t\tbreak;\n+\t\tcase DWC_OTG_CONTROL_DATA:\n+\t\t\tDWC_DEBUGPL(DBG_HCDV, \"  Control data transaction\\n\");\n+\t\t\t/*\n+\t\t\t * Hardware bug: small IN packets with length < 4\n+\t\t\t * cause a 4-byte write to memory. We can only catch\n+\t\t\t * the case where we know a short packet is going to be\n+\t\t\t * returned in a control transfer, as the length is\n+\t\t\t * specified in the setup packet. This is only an issue\n+\t\t\t * for drivers that insist on packing a device's various\n+\t\t\t * properties into a struct and querying them one at a\n+\t\t\t * time (uvcvideo).\n+\t\t\t * Force the use of align_buf so that the subsequent\n+\t\t\t * memcpy puts the right number of bytes in the URB's\n+\t\t\t * buffer.\n+\t\t\t */\n+\t\t\twLength = ((uint16_t *)urb->setup_packet)[3];\n+\t\t\tif (hc->ep_is_in && wLength < 4)\n+\t\t\t\tptr = hc->xfer_buff;\n+\n+\t\t\thc->data_pid_start = qtd->data_toggle;\n+\t\t\tbreak;\n+\t\tcase DWC_OTG_CONTROL_STATUS:\n+\t\t\t/*\n+\t\t\t * Direction is opposite of data direction or IN if no\n+\t\t\t * data.\n+\t\t\t */\n+\t\t\tDWC_DEBUGPL(DBG_HCDV, \"  Control status transaction\\n\");\n+\t\t\tif (urb->length == 0) {\n+\t\t\t\thc->ep_is_in = 1;\n+\t\t\t} else {\n+\t\t\t\thc->ep_is_in =\n+\t\t\t\t    dwc_otg_hcd_is_pipe_out(&urb->pipe_info);\n+\t\t\t}\n+\t\t\tif (hc->ep_is_in) {\n+\t\t\t\thc->do_ping = 0;\n+\t\t\t}\n+\n+\t\t\thc->data_pid_start = DWC_OTG_HC_PID_DATA1;\n+\n+\t\t\thc->xfer_len = 0;\n+\t\t\tif (hcd->core_if->dma_enable) {\n+\t\t\t\thc->xfer_buff = (uint8_t *) hcd->status_buf_dma;\n+\t\t\t} else {\n+\t\t\t\thc->xfer_buff = (uint8_t *) hcd->status_buf;\n+\t\t\t}\n+\t\t\tptr = NULL;\n+\t\t\tbreak;\n+\t\t}\n+\t\tbreak;\n+\tcase UE_BULK:\n+\t\thc->ep_type = DWC_OTG_EP_TYPE_BULK;\n+\t\tbreak;\n+\tcase UE_INTERRUPT:\n+\t\thc->ep_type = DWC_OTG_EP_TYPE_INTR;\n+\t\tbreak;\n+\tcase UE_ISOCHRONOUS:\n+\t\t{\n+\t\t\tstruct dwc_otg_hcd_iso_packet_desc *frame_desc;\n+\n+\t\t\thc->ep_type = DWC_OTG_EP_TYPE_ISOC;\n+\n+\t\t\tif (hcd->core_if->dma_desc_enable)\n+\t\t\t\tbreak;\n+\n+\t\t\tframe_desc = &urb->iso_descs[qtd->isoc_frame_index];\n+\n+\t\t\tframe_desc->status = 0;\n+\n+\t\t\tif (hcd->core_if->dma_enable) {\n+\t\t\t\thc->xfer_buff = (uint8_t *) urb->dma;\n+\t\t\t} else {\n+\t\t\t\thc->xfer_buff = (uint8_t *) urb->buf;\n+\t\t\t}\n+\t\t\thc->xfer_buff +=\n+\t\t\t    frame_desc->offset + qtd->isoc_split_offset;\n+\t\t\thc->xfer_len =\n+\t\t\t    frame_desc->length - qtd->isoc_split_offset;\n+\n+\t\t\t/* For non-dword aligned buffers */\n+\t\t\tif (((unsigned long)hc->xfer_buff & 0x3)\n+\t\t\t    && hcd->core_if->dma_enable) {\n+\t\t\t\tptr =\n+\t\t\t\t    (uint8_t *) urb->buf + frame_desc->offset +\n+\t\t\t\t    qtd->isoc_split_offset;\n+\t\t\t} else\n+\t\t\t\tptr = NULL;\n+\n+\t\t\tif (hc->xact_pos == DWC_HCSPLIT_XACTPOS_ALL) {\n+\t\t\t\tif (hc->xfer_len <= 188) {\n+\t\t\t\t\thc->xact_pos = DWC_HCSPLIT_XACTPOS_ALL;\n+\t\t\t\t} else {\n+\t\t\t\t\thc->xact_pos =\n+\t\t\t\t\t    DWC_HCSPLIT_XACTPOS_BEGIN;\n+\t\t\t\t}\n+\t\t\t}\n+\t\t}\n+\t\tbreak;\n+\t}\n+\t/* non DWORD-aligned buffer case */\n+\tif (ptr) {\n+\t\tuint32_t buf_size;\n+\t\tif (hc->ep_type != DWC_OTG_EP_TYPE_ISOC) {\n+\t\t\tbuf_size = hcd->core_if->core_params->max_transfer_size;\n+\t\t} else {\n+\t\t\tbuf_size = 4096;\n+\t\t}\n+\t\tif (!qh->dw_align_buf) {\n+\t\t\tqh->dw_align_buf = DWC_DMA_ALLOC_ATOMIC(dev, buf_size,\n+\t\t\t\t\t\t\t &qh->dw_align_buf_dma);\n+\t\t\tif (!qh->dw_align_buf) {\n+\t\t\t\tDWC_ERROR\n+\t\t\t\t    (\"%s: Failed to allocate memory to handle \"\n+\t\t\t\t     \"non-dword aligned buffer case\\n\",\n+\t\t\t\t     __func__);\n+\t\t\t\treturn;\n+\t\t\t}\n+\t\t}\n+\t\tif (!hc->ep_is_in) {\n+\t\t\tdwc_memcpy(qh->dw_align_buf, ptr, hc->xfer_len);\n+\t\t}\n+\t\thc->align_buff = qh->dw_align_buf_dma;\n+\t} else {\n+\t\thc->align_buff = 0;\n+\t}\n+\n+\tif (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||\n+\t    hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {\n+\t\t/*\n+\t\t * This value may be modified when the transfer is started to\n+\t\t * reflect the actual transfer length.\n+\t\t */\n+\t\thc->multi_count = dwc_hb_mult(qh->maxp);\n+\t}\n+\n+\tif (hcd->core_if->dma_desc_enable)\n+\t\thc->desc_list_addr = qh->desc_list_dma;\n+\n+\tdwc_otg_hc_init(hcd->core_if, hc);\n+\n+\tlocal_irq_save(flags);\n+\n+\tif (fiq_enable) {\n+\t\tlocal_fiq_disable();\n+\t\tfiq_fsm_spin_lock(&hcd->fiq_state->lock);\n+\t}\n+\n+\t/* Enable the top level host channel interrupt. */\n+\tintr_enable = (1 << hc->hc_num);\n+\tDWC_MODIFY_REG32(&hcd->core_if->host_if->host_global_regs->haintmsk, 0, intr_enable);\n+\n+\t/* Make sure host channel interrupts are enabled. */\n+\tgintmsk.b.hcintr = 1;\n+\tDWC_MODIFY_REG32(&hcd->core_if->core_global_regs->gintmsk, 0, gintmsk.d32);\n+\n+\tif (fiq_enable) {\n+\t\tfiq_fsm_spin_unlock(&hcd->fiq_state->lock);\n+\t\tlocal_fiq_enable();\n+\t}\n+\n+\tlocal_irq_restore(flags);\n+\thc->qh = qh;\n+}\n+\n+\n+/**\n+ * fiq_fsm_transaction_suitable() - Test a QH for compatibility with the FIQ\n+ * @hcd:\tPointer to the dwc_otg_hcd struct\n+ * @qh:\tpointer to the endpoint's queue head\n+ *\n+ * Transaction start/end control flow is grafted onto the existing dwc_otg\n+ * mechanisms, to avoid spaghettifying the functions more than they already are.\n+ * This function's eligibility check is altered by debug parameter.\n+ *\n+ * Returns: 0 for unsuitable, 1 implies the FIQ can be enabled for this transaction.\n+ */\n+\n+int fiq_fsm_transaction_suitable(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)\n+{\n+\tif (qh->do_split) {\n+\t\tswitch (qh->ep_type) {\n+\t\tcase UE_CONTROL:\n+\t\tcase UE_BULK:\n+\t\t\tif (fiq_fsm_mask & (1 << 0))\n+\t\t\t\treturn 1;\n+\t\t\tbreak;\n+\t\tcase UE_INTERRUPT:\n+\t\tcase UE_ISOCHRONOUS:\n+\t\t\tif (fiq_fsm_mask & (1 << 1))\n+\t\t\t\treturn 1;\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tbreak;\n+\t\t}\n+\t} else if (qh->ep_type == UE_ISOCHRONOUS) {\n+\t\tif (fiq_fsm_mask & (1 << 2)) {\n+\t\t\t/* ISOCH support. We test for compatibility:\n+\t\t\t * - DWORD aligned buffers\n+\t\t\t * - Must be at least 2 transfers (otherwise pointless to use the FIQ)\n+\t\t\t * If yes, then the fsm enqueue function will handle the state machine setup.\n+\t\t\t */\n+\t\t\tdwc_otg_qtd_t *qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list);\n+\t\t\tdwc_otg_hcd_urb_t *urb = qtd->urb;\n+\t\t\tdwc_dma_t ptr;\n+\t\t\tint i;\n+\n+\t\t\tif (urb->packet_count < 2)\n+\t\t\t\treturn 0;\n+\t\t\tfor (i = 0; i < urb->packet_count; i++) {\n+\t\t\t\tptr = urb->dma + urb->iso_descs[i].offset;\n+\t\t\t\tif (ptr & 0x3)\n+\t\t\t\t\treturn 0;\n+\t\t\t}\n+\t\t\treturn 1;\n+\t\t}\n+\t}\n+\treturn 0;\n+}\n+\n+/**\n+ * fiq_fsm_setup_periodic_dma() - Set up DMA bounce buffers\n+ * @hcd: Pointer to the dwc_otg_hcd struct\n+ * @qh: Pointer to the endpoint's queue head\n+ *\n+ * Periodic split transactions are transmitted modulo 188 bytes.\n+ * This necessitates slicing data up into buckets for isochronous out\n+ * and fixing up the DMA address for all IN transfers.\n+ *\n+ * Returns 1 if the DMA bounce buffers have been used, 0 if the default\n+ * HC buffer has been used.\n+ */\n+int fiq_fsm_setup_periodic_dma(dwc_otg_hcd_t *hcd, struct fiq_channel_state *st, dwc_otg_qh_t *qh)\n+ {\n+\tint frame_length, i = 0;\n+\tuint8_t *ptr = NULL;\n+\tdwc_hc_t *hc = qh->channel;\n+\tstruct fiq_dma_blob *blob;\n+\tstruct dwc_otg_hcd_iso_packet_desc *frame_desc;\n+\n+\tfor (i = 0; i < 6; i++) {\n+\t\tst->dma_info.slot_len[i] = 255;\n+\t}\n+\tst->dma_info.index = 0;\n+\ti = 0;\n+\tif (hc->ep_is_in) {\n+\t\t/*\n+\t\t * Set dma_regs to bounce buffer. FIQ will update the\n+\t\t * state depending on transaction progress.\n+\t\t * Pointer arithmetic on hcd->fiq_state->dma_base (a dma_addr_t)\n+\t\t * to point it to the correct offset in the allocated buffers.\n+\t\t */\n+\t\tblob = (struct fiq_dma_blob *) hcd->fiq_state->dma_base;\n+\t\tst->hcdma_copy.d32 = (dma_addr_t) blob->channel[hc->hc_num].index[0].buf;\n+\n+\t\t/* Calculate the max number of CSPLITS such that the FIQ can time out\n+\t\t * a transaction if it fails.\n+\t\t */\n+\t\tframe_length = st->hcchar_copy.b.mps;\n+\t\tdo {\n+\t\t\ti++;\n+\t\t\tframe_length -= 188;\n+\t\t} while (frame_length >= 0);\n+\t\tst->nrpackets = i;\n+\t\treturn 1;\n+\t} else {\n+\t\tif (qh->ep_type == UE_ISOCHRONOUS) {\n+\n+\t\t\tdwc_otg_qtd_t *qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list);\n+\n+\t\t\tframe_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index];\n+\t\t\tframe_length = frame_desc->length;\n+\n+\t\t\t/* Virtual address for bounce buffers */\n+\t\t\tblob = hcd->fiq_dmab;\n+\n+\t\t\tptr = qtd->urb->buf + frame_desc->offset;\n+\t\t\tif (frame_length == 0) {\n+\t\t\t\t/*\n+\t\t\t\t * for isochronous transactions, we must still transmit a packet\n+\t\t\t\t * even if the length is zero.\n+\t\t\t\t */\n+\t\t\t\tst->dma_info.slot_len[0] = 0;\n+\t\t\t\tst->nrpackets = 1;\n+\t\t\t} else {\n+\t\t\t\tdo {\n+\t\t\t\t\tif (frame_length <= 188) {\n+\t\t\t\t\t\tdwc_memcpy(&blob->channel[hc->hc_num].index[i].buf[0], ptr, frame_length);\n+\t\t\t\t\t\tst->dma_info.slot_len[i] = frame_length;\n+\t\t\t\t\t\tptr += frame_length;\n+\t\t\t\t\t} else {\n+\t\t\t\t\t\tdwc_memcpy(&blob->channel[hc->hc_num].index[i].buf[0], ptr, 188);\n+\t\t\t\t\t\tst->dma_info.slot_len[i] = 188;\n+\t\t\t\t\t\tptr += 188;\n+\t\t\t\t\t}\n+\t\t\t\t\ti++;\n+\t\t\t\t\tframe_length -= 188;\n+\t\t\t\t} while (frame_length > 0);\n+\t\t\t\tst->nrpackets = i;\n+\t\t\t}\n+\t\t\tptr = qtd->urb->buf + frame_desc->offset;\n+\t\t\t/*\n+\t\t\t * Point the HC at the DMA address of the bounce buffers\n+\t\t\t *\n+\t\t\t * Pointer arithmetic on hcd->fiq_state->dma_base (a\n+\t\t\t * dma_addr_t) to point it to the correct offset in the\n+\t\t\t * allocated buffers.\n+\t\t\t */\n+\t\t\tblob = (struct fiq_dma_blob *) hcd->fiq_state->dma_base;\n+\t\t\tst->hcdma_copy.d32 = (dma_addr_t) blob->channel[hc->hc_num].index[0].buf;\n+\n+\t\t\t/* fixup xfersize to the actual packet size */\n+\t\t\tst->hctsiz_copy.b.pid = 0;\n+\t\t\tst->hctsiz_copy.b.xfersize = st->dma_info.slot_len[0];\n+\t\t\treturn 1;\n+\t\t} else {\n+\t\t\t/* For interrupt, single OUT packet required, goes in the SSPLIT from hc_buff. */\n+\t\t\treturn 0;\n+\t\t}\n+\t}\n+}\n+\n+/**\n+ * fiq_fsm_np_tt_contended() - Avoid performing contended non-periodic transfers\n+ * @hcd: Pointer to the dwc_otg_hcd struct\n+ * @qh: Pointer to the endpoint's queue head\n+ *\n+ * Certain hub chips don't differentiate between IN and OUT non-periodic pipes\n+ * with the same endpoint number. If transfers get completed out of order\n+ * (disregarding the direction token) then the hub can lock up\n+ * or return erroneous responses.\n+ *\n+ * Returns 1 if initiating the transfer would cause contention, 0 otherwise.\n+ */\n+int fiq_fsm_np_tt_contended(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)\n+{\n+\tint i;\n+\tstruct fiq_channel_state *st;\n+\tint dev_addr = qh->channel->dev_addr;\n+\tint ep_num = qh->channel->ep_num;\n+\tfor (i = 0; i < hcd->core_if->core_params->host_channels; i++) {\n+\t\tif (i == qh->channel->hc_num)\n+\t\t\tcontinue;\n+\t\tst = &hcd->fiq_state->channel[i];\n+\t\tswitch (st->fsm) {\n+\t\tcase FIQ_NP_SSPLIT_STARTED:\n+\t\tcase FIQ_NP_SSPLIT_RETRY:\n+\t\tcase FIQ_NP_SSPLIT_PENDING:\n+\t\tcase FIQ_NP_OUT_CSPLIT_RETRY:\n+\t\tcase FIQ_NP_IN_CSPLIT_RETRY:\n+\t\t\tif (st->hcchar_copy.b.devaddr == dev_addr &&\n+\t\t\t\tst->hcchar_copy.b.epnum == ep_num)\n+\t\t\t\treturn 1;\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\treturn 0;\n+}\n+\n+/*\n+ * Pushing a periodic request into the queue near the EOF1 point\n+ * in a microframe causes erroneous behaviour (frmovrun) interrupt.\n+ * Usually, the request goes out on the bus causing a transfer but\n+ * the core does not transfer the data to memory.\n+ * This guard interval (in number of 60MHz clocks) is required which\n+ * must cater for CPU latency between reading the value and enabling\n+ * the channel.\n+ */\n+#define PERIODIC_FRREM_BACKOFF 1000\n+\n+int fiq_fsm_queue_isoc_transaction(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)\n+{\n+\tdwc_hc_t *hc = qh->channel;\n+\tdwc_otg_hc_regs_t *hc_regs = hcd->core_if->host_if->hc_regs[hc->hc_num];\n+\tdwc_otg_qtd_t *qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list);\n+\tint frame;\n+\tstruct fiq_channel_state *st = &hcd->fiq_state->channel[hc->hc_num];\n+\tint xfer_len, nrpackets;\n+\thcdma_data_t hcdma;\n+\thfnum_data_t hfnum;\n+\n+\tif (st->fsm != FIQ_PASSTHROUGH)\n+\t\treturn 0;\n+\n+\tst->nr_errors = 0;\n+\n+\tst->hcchar_copy.d32 = 0;\n+\tst->hcchar_copy.b.mps = hc->max_packet;\n+\tst->hcchar_copy.b.epdir = hc->ep_is_in;\n+\tst->hcchar_copy.b.devaddr = hc->dev_addr;\n+\tst->hcchar_copy.b.epnum = hc->ep_num;\n+\tst->hcchar_copy.b.eptype = hc->ep_type;\n+\n+\tst->hcintmsk_copy.b.chhltd = 1;\n+\n+\tframe = dwc_otg_hcd_get_frame_number(hcd);\n+\tst->hcchar_copy.b.oddfrm = (frame & 0x1) ? 0 : 1;\n+\n+\tst->hcchar_copy.b.lspddev = 0;\n+\t/* Enable the channel later as a final register write. */\n+\n+\tst->hcsplt_copy.d32 = 0;\n+\n+\tst->hs_isoc_info.iso_desc = (struct dwc_otg_hcd_iso_packet_desc *) &qtd->urb->iso_descs;\n+\tst->hs_isoc_info.nrframes = qtd->urb->packet_count;\n+\t/* grab the next DMA address offset from the array */\n+\tst->hcdma_copy.d32 = qtd->urb->dma;\n+\thcdma.d32 = st->hcdma_copy.d32 + st->hs_isoc_info.iso_desc[0].offset;\n+\n+\t/* We need to set multi_count. This is a bit tricky - has to be set per-transaction as\n+\t * the core needs to be told to send the correct number. Caution: for IN transfers,\n+\t * this is always set to the maximum size of the endpoint. */\n+\txfer_len = st->hs_isoc_info.iso_desc[0].length;\n+\tnrpackets = (xfer_len + st->hcchar_copy.b.mps - 1) / st->hcchar_copy.b.mps;\n+\tif (nrpackets == 0)\n+\t\tnrpackets = 1;\n+\tst->hcchar_copy.b.multicnt = nrpackets;\n+\tst->hctsiz_copy.b.pktcnt = nrpackets;\n+\n+\t/* Initial PID also needs to be set */\n+\tif (st->hcchar_copy.b.epdir == 0) {\n+\t\tst->hctsiz_copy.b.xfersize = xfer_len;\n+\t\tswitch (st->hcchar_copy.b.multicnt) {\n+\t\tcase 1:\n+\t\t\tst->hctsiz_copy.b.pid = DWC_PID_DATA0;\n+\t\t\tbreak;\n+\t\tcase 2:\n+\t\tcase 3:\n+\t\t\tst->hctsiz_copy.b.pid = DWC_PID_MDATA;\n+\t\t\tbreak;\n+\t\t}\n+\n+\t} else {\n+\t\tst->hctsiz_copy.b.xfersize = nrpackets * st->hcchar_copy.b.mps;\n+\t\tswitch (st->hcchar_copy.b.multicnt) {\n+\t\tcase 1:\n+\t\t\tst->hctsiz_copy.b.pid = DWC_PID_DATA0;\n+\t\t\tbreak;\n+\t\tcase 2:\n+\t\t\tst->hctsiz_copy.b.pid = DWC_PID_DATA1;\n+\t\t\tbreak;\n+\t\tcase 3:\n+\t\t\tst->hctsiz_copy.b.pid = DWC_PID_DATA2;\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\n+\tst->hs_isoc_info.stride = qh->interval;\n+\tst->uframe_sleeps = 0;\n+\n+\tfiq_print(FIQDBG_INT, hcd->fiq_state, \"FSMQ  %01d \", hc->hc_num);\n+\tfiq_print(FIQDBG_INT, hcd->fiq_state, \"%08x\", st->hcchar_copy.d32);\n+\tfiq_print(FIQDBG_INT, hcd->fiq_state, \"%08x\", st->hctsiz_copy.d32);\n+\tfiq_print(FIQDBG_INT, hcd->fiq_state, \"%08x\", st->hcdma_copy.d32);\n+\thfnum.d32 = DWC_READ_REG32(&hcd->core_if->host_if->host_global_regs->hfnum);\n+\tlocal_fiq_disable();\n+\tfiq_fsm_spin_lock(&hcd->fiq_state->lock);\n+\tDWC_WRITE_REG32(&hc_regs->hctsiz, st->hctsiz_copy.d32);\n+\tDWC_WRITE_REG32(&hc_regs->hcsplt, st->hcsplt_copy.d32);\n+\tDWC_WRITE_REG32(&hc_regs->hcdma, st->hcdma_copy.d32);\n+\tDWC_WRITE_REG32(&hc_regs->hcchar, st->hcchar_copy.d32);\n+\tDWC_WRITE_REG32(&hc_regs->hcintmsk, st->hcintmsk_copy.d32);\n+\tif (hfnum.b.frrem < PERIODIC_FRREM_BACKOFF) {\n+\t\t/* Prevent queueing near EOF1. Bad things happen if a periodic\n+\t\t * split transaction is queued very close to EOF. SOF interrupt handler\n+\t\t * will wake this channel at the next interrupt.\n+\t\t */\n+\t\tst->fsm = FIQ_HS_ISOC_SLEEPING;\n+\t\tst->uframe_sleeps = 1;\n+\t} else {\n+\t\tst->fsm = FIQ_HS_ISOC_TURBO;\n+\t\tst->hcchar_copy.b.chen = 1;\n+\t\tDWC_WRITE_REG32(&hc_regs->hcchar, st->hcchar_copy.d32);\n+\t}\n+\tmb();\n+\tst->hcchar_copy.b.chen = 0;\n+\tfiq_fsm_spin_unlock(&hcd->fiq_state->lock);\n+\tlocal_fiq_enable();\n+\treturn 0;\n+}\n+\n+\n+/**\n+ * fiq_fsm_queue_split_transaction() - Set up a host channel and FIQ state\n+ * @hcd: Pointer to the dwc_otg_hcd struct\n+ * @qh: Pointer to the endpoint's queue head\n+ *\n+ * This overrides the dwc_otg driver's normal method of queueing a transaction.\n+ * Called from dwc_otg_hcd_queue_transactions(), this performs specific setup\n+ * for the nominated host channel.\n+ *\n+ * For periodic transfers, it also peeks at the FIQ state to see if an immediate\n+ * start is possible. If not, then the FIQ is left to start the transfer.\n+ */\n+int fiq_fsm_queue_split_transaction(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)\n+{\n+\tint start_immediate = 1, i;\n+\thfnum_data_t hfnum;\n+\tdwc_hc_t *hc = qh->channel;\n+\tdwc_otg_hc_regs_t *hc_regs = hcd->core_if->host_if->hc_regs[hc->hc_num];\n+\t/* Program HC registers, setup FIQ_state, examine FIQ if periodic, start transfer (not if uframe 5) */\n+\tint hub_addr, port_addr, frame, uframe;\n+\tstruct fiq_channel_state *st = &hcd->fiq_state->channel[hc->hc_num];\n+\n+\t/*\n+\t * Non-periodic channel assignments stay in the non_periodic_active queue.\n+\t * Therefore we get repeatedly called until the FIQ's done processing this channel.\n+\t */\n+\tif (qh->channel->xfer_started == 1)\n+\t\treturn 0;\n+\n+\tif (st->fsm != FIQ_PASSTHROUGH) {\n+\t\tpr_warn_ratelimited(\"%s:%d: Queue called for an active channel\\n\", __func__, __LINE__);\n+\t\treturn 0;\n+\t}\n+\n+\tqh->channel->xfer_started = 1;\n+\n+\tst->nr_errors = 0;\n+\n+\tst->hcchar_copy.d32 = 0;\n+\tst->hcchar_copy.b.mps = min_t(uint32_t, hc->xfer_len, hc->max_packet);\n+\tst->hcchar_copy.b.epdir = hc->ep_is_in;\n+\tst->hcchar_copy.b.devaddr = hc->dev_addr;\n+\tst->hcchar_copy.b.epnum = hc->ep_num;\n+\tst->hcchar_copy.b.eptype = hc->ep_type;\n+\tif (hc->ep_type & 0x1) {\n+\t\tif (hc->ep_is_in)\n+\t\t\tst->hcchar_copy.b.multicnt = 3;\n+\t\telse\n+\t\t\t/* Docs say set this to 1, but driver sets to 0! */\n+\t\t\tst->hcchar_copy.b.multicnt = 0;\n+\t} else {\n+\t\tst->hcchar_copy.b.multicnt = 1;\n+\t\tst->hcchar_copy.b.oddfrm = 0;\n+\t}\n+\tst->hcchar_copy.b.lspddev = (hc->speed == DWC_OTG_EP_SPEED_LOW) ? 1 : 0;\n+\t/* Enable the channel later as a final register write. */\n+\n+\tst->hcsplt_copy.d32 = 0;\n+\tif(qh->do_split) {\n+\t\thcd->fops->hub_info(hcd, DWC_CIRCLEQ_FIRST(&qh->qtd_list)->urb->priv, &hub_addr, &port_addr);\n+\t\tst->hcsplt_copy.b.compsplt = 0;\n+\t\tst->hcsplt_copy.b.spltena = 1;\n+\t\t// XACTPOS is for isoc-out only but needs initialising anyway.\n+\t\tst->hcsplt_copy.b.xactpos = ISOC_XACTPOS_ALL;\n+\t\tif((qh->ep_type == DWC_OTG_EP_TYPE_ISOC) && (!qh->ep_is_in)) {\n+\t\t\t/* For packetsize 0 < L < 188, ISOC_XACTPOS_ALL.\n+\t\t\t * for longer than this, ISOC_XACTPOS_BEGIN and the FIQ\n+\t\t\t * will update as necessary.\n+\t\t\t */\n+\t\t\tif (hc->xfer_len > 188) {\n+\t\t\t\tst->hcsplt_copy.b.xactpos = ISOC_XACTPOS_BEGIN;\n+\t\t\t}\n+\t\t}\n+\t\tst->hcsplt_copy.b.hubaddr = (uint8_t) hub_addr;\n+\t\tst->hcsplt_copy.b.prtaddr = (uint8_t) port_addr;\n+\t\tst->hub_addr = hub_addr;\n+\t\tst->port_addr = port_addr;\n+\t}\n+\n+\tst->hctsiz_copy.d32 = 0;\n+\tst->hctsiz_copy.b.dopng = 0;\n+\tst->hctsiz_copy.b.pid = hc->data_pid_start;\n+\n+\tif (hc->ep_is_in || (hc->xfer_len > hc->max_packet)) {\n+\t\thc->xfer_len = min_t(uint32_t, hc->xfer_len, hc->max_packet);\n+\t} else if (!hc->ep_is_in && (hc->xfer_len > 188)) {\n+\t\thc->xfer_len = 188;\n+\t}\n+\tst->hctsiz_copy.b.xfersize = hc->xfer_len;\n+\n+\tst->hctsiz_copy.b.pktcnt = 1;\n+\n+\tif (hc->ep_type & 0x1) {\n+\t\t/*\n+\t\t * For potentially multi-packet transfers, must use the DMA bounce buffers. For IN transfers,\n+\t\t * the DMA address is the address of the first 188byte slot buffer in the bounce buffer array.\n+\t\t * For multi-packet OUT transfers, we need to copy the data into the bounce buffer array so the FIQ can punt\n+\t\t * the right address out as necessary. hc->xfer_buff and hc->xfer_len have already been set\n+\t\t * in assign_and_init_hc(), but this is for the eventual transaction completion only. The FIQ\n+\t\t * must not touch internal driver state.\n+\t\t */\n+\t\tif(!fiq_fsm_setup_periodic_dma(hcd, st, qh)) {\n+\t\t\tif (hc->align_buff) {\n+\t\t\t\tst->hcdma_copy.d32 = hc->align_buff;\n+\t\t\t} else {\n+\t\t\t\tst->hcdma_copy.d32 = ((unsigned long) hc->xfer_buff & 0xFFFFFFFF);\n+\t\t\t}\n+\t\t}\n+\t} else {\n+\t\tif (hc->align_buff) {\n+\t\t\tst->hcdma_copy.d32 = hc->align_buff;\n+\t\t} else {\n+\t\t\tst->hcdma_copy.d32 = ((unsigned long) hc->xfer_buff & 0xFFFFFFFF);\n+\t\t}\n+\t}\n+\t/* The FIQ depends upon no other interrupts being enabled except channel halt.\n+\t * Fixup channel interrupt mask. */\n+\tst->hcintmsk_copy.d32 = 0;\n+\tst->hcintmsk_copy.b.chhltd = 1;\n+\tst->hcintmsk_copy.b.ahberr = 1;\n+\n+\t/* Hack courtesy of FreeBSD: apparently forcing Interrupt Split transactions\n+\t * as Control puts the transfer into the non-periodic request queue and the\n+\t * non-periodic handler in the hub. Makes things lots easier.\n+\t */\n+\tif ((fiq_fsm_mask & 0x8) && hc->ep_type == UE_INTERRUPT) {\n+\t\tst->hcchar_copy.b.multicnt = 0;\n+\t\tst->hcchar_copy.b.oddfrm = 0;\n+\t\tst->hcchar_copy.b.eptype = UE_CONTROL;\n+\t\tif (hc->align_buff) {\n+\t\t\tst->hcdma_copy.d32 = hc->align_buff;\n+\t\t} else {\n+\t\t\tst->hcdma_copy.d32 = ((unsigned long) hc->xfer_buff & 0xFFFFFFFF);\n+\t\t}\n+\t}\n+\tDWC_WRITE_REG32(&hc_regs->hcdma, st->hcdma_copy.d32);\n+\tDWC_WRITE_REG32(&hc_regs->hctsiz, st->hctsiz_copy.d32);\n+\tDWC_WRITE_REG32(&hc_regs->hcsplt, st->hcsplt_copy.d32);\n+\tDWC_WRITE_REG32(&hc_regs->hcchar, st->hcchar_copy.d32);\n+\tDWC_WRITE_REG32(&hc_regs->hcintmsk, st->hcintmsk_copy.d32);\n+\n+\tlocal_fiq_disable();\n+\tfiq_fsm_spin_lock(&hcd->fiq_state->lock);\n+\n+\tif (hc->ep_type & 0x1) {\n+\t\thfnum.d32 = DWC_READ_REG32(&hcd->core_if->host_if->host_global_regs->hfnum);\n+\t\tframe = (hfnum.b.frnum & ~0x7) >> 3;\n+\t\tuframe = hfnum.b.frnum & 0x7;\n+\t\tif (hfnum.b.frrem < PERIODIC_FRREM_BACKOFF) {\n+\t\t\t/* Prevent queueing near EOF1. Bad things happen if a periodic\n+\t\t\t * split transaction is queued very close to EOF.\n+\t\t\t */\n+\t\t\tstart_immediate = 0;\n+\t\t} else if (uframe == 5) {\n+\t\t\tstart_immediate = 0;\n+\t\t} else if (hc->ep_type == UE_ISOCHRONOUS && !hc->ep_is_in) {\n+\t\t\tstart_immediate = 0;\n+\t\t} else if (hc->ep_is_in && fiq_fsm_too_late(hcd->fiq_state, hc->hc_num)) {\n+\t\t\tstart_immediate = 0;\n+\t\t} else {\n+\t\t\t/* Search through all host channels to determine if a transaction\n+\t\t\t * is currently in progress */\n+\t\t\tfor (i = 0; i < hcd->core_if->core_params->host_channels; i++) {\n+\t\t\t\tif (i == hc->hc_num || hcd->fiq_state->channel[i].fsm == FIQ_PASSTHROUGH)\n+\t\t\t\t\tcontinue;\n+\t\t\t\tswitch (hcd->fiq_state->channel[i].fsm) {\n+\t\t\t\t/* TT is reserved for channels that are in the middle of a periodic\n+\t\t\t\t * split transaction.\n+\t\t\t\t */\n+\t\t\t\tcase FIQ_PER_SSPLIT_STARTED:\n+\t\t\t\tcase FIQ_PER_CSPLIT_WAIT:\n+\t\t\t\tcase FIQ_PER_CSPLIT_NYET1:\n+\t\t\t\tcase FIQ_PER_CSPLIT_POLL:\n+\t\t\t\tcase FIQ_PER_ISO_OUT_ACTIVE:\n+\t\t\t\tcase FIQ_PER_ISO_OUT_LAST:\n+\t\t\t\t\tif (hcd->fiq_state->channel[i].hub_addr == hub_addr &&\n+\t\t\t\t\t\t\thcd->fiq_state->channel[i].port_addr == port_addr) {\n+\t\t\t\t\t\tstart_immediate = 0;\n+\t\t\t\t\t}\n+\t\t\t\t\tbreak;\n+\t\t\t\tdefault:\n+\t\t\t\t\tbreak;\n+\t\t\t\t}\n+\t\t\t\tif (!start_immediate)\n+\t\t\t\t\tbreak;\n+\t\t\t}\n+\t\t}\n+\t}\n+\tif ((fiq_fsm_mask & 0x8) && hc->ep_type == UE_INTERRUPT)\n+\t\tstart_immediate = 1;\n+\n+\tfiq_print(FIQDBG_INT, hcd->fiq_state, \"FSMQ %01d %01d\", hc->hc_num, start_immediate);\n+\tfiq_print(FIQDBG_INT, hcd->fiq_state, \"%08d\", hfnum.b.frrem);\n+\t//fiq_print(FIQDBG_INT, hcd->fiq_state, \"H:%02dP:%02d\", hub_addr, port_addr);\n+\t//fiq_print(FIQDBG_INT, hcd->fiq_state, \"%08x\", st->hctsiz_copy.d32);\n+\t//fiq_print(FIQDBG_INT, hcd->fiq_state, \"%08x\", st->hcdma_copy.d32);\n+\tswitch (hc->ep_type) {\n+\t\tcase UE_CONTROL:\n+\t\tcase UE_BULK:\n+\t\t\tif (fiq_fsm_np_tt_contended(hcd, qh)) {\n+\t\t\t\tst->fsm = FIQ_NP_SSPLIT_PENDING;\n+\t\t\t\tstart_immediate = 0;\n+\t\t\t} else {\n+\t\t\t\tst->fsm = FIQ_NP_SSPLIT_STARTED;\n+\t\t\t}\n+\t\t\tbreak;\n+\t\tcase UE_ISOCHRONOUS:\n+\t\t\tif (hc->ep_is_in) {\n+\t\t\t\tif (start_immediate) {\n+\t\t\t\t\tst->fsm = FIQ_PER_SSPLIT_STARTED;\n+\t\t\t\t} else {\n+\t\t\t\t\tst->fsm = FIQ_PER_SSPLIT_QUEUED;\n+\t\t\t\t}\n+\t\t\t} else {\n+\t\t\t\tif (start_immediate) {\n+\t\t\t\t\t/* Single-isoc OUT packets don't require FIQ involvement */\n+\t\t\t\t\tif (st->nrpackets == 1) {\n+\t\t\t\t\t\tst->fsm = FIQ_PER_ISO_OUT_LAST;\n+\t\t\t\t\t} else {\n+\t\t\t\t\t\tst->fsm = FIQ_PER_ISO_OUT_ACTIVE;\n+\t\t\t\t\t}\n+\t\t\t\t} else {\n+\t\t\t\t\tst->fsm = FIQ_PER_ISO_OUT_PENDING;\n+\t\t\t\t}\n+\t\t\t}\n+\t\t\tbreak;\n+\t\tcase UE_INTERRUPT:\n+\t\t\tif (fiq_fsm_mask & 0x8) {\n+\t\t\t\tif (fiq_fsm_np_tt_contended(hcd, qh)) {\n+\t\t\t\t\tst->fsm = FIQ_NP_SSPLIT_PENDING;\n+\t\t\t\t\tstart_immediate = 0;\n+\t\t\t\t} else {\n+\t\t\t\t\tst->fsm = FIQ_NP_SSPLIT_STARTED;\n+\t\t\t\t}\n+\t\t\t} else if (start_immediate) {\n+\t\t\t\t\tst->fsm = FIQ_PER_SSPLIT_STARTED;\n+\t\t\t} else {\n+\t\t\t\tst->fsm = FIQ_PER_SSPLIT_QUEUED;\n+\t\t\t}\n+\t\tdefault:\n+\t\t\tbreak;\n+\t}\n+\tif (start_immediate) {\n+\t\t/* Set the oddfrm bit as close as possible to actual queueing */\n+\t\tframe = dwc_otg_hcd_get_frame_number(hcd);\n+\t\tst->expected_uframe = (frame + 1) & 0x3FFF;\n+\t\tst->hcchar_copy.b.oddfrm = (frame & 0x1) ? 0 : 1;\n+\t\tst->hcchar_copy.b.chen = 1;\n+\t\tDWC_WRITE_REG32(&hc_regs->hcchar, st->hcchar_copy.d32);\n+\t}\n+\tmb();\n+\tfiq_fsm_spin_unlock(&hcd->fiq_state->lock);\n+\tlocal_fiq_enable();\n+\treturn 0;\n+}\n+\n+\n+/**\n+ * This function selects transactions from the HCD transfer schedule and\n+ * assigns them to available host channels. It is called from HCD interrupt\n+ * handler functions.\n+ *\n+ * @param hcd The HCD state structure.\n+ *\n+ * @return The types of new transactions that were assigned to host channels.\n+ */\n+dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t * hcd)\n+{\n+\tdwc_list_link_t *qh_ptr;\n+\tdwc_otg_qh_t *qh;\n+\tint num_channels;\n+\tdwc_otg_transaction_type_e ret_val = DWC_OTG_TRANSACTION_NONE;\n+\n+#ifdef DEBUG_HOST_CHANNELS\n+\tlast_sel_trans_num_per_scheduled = 0;\n+\tlast_sel_trans_num_nonper_scheduled = 0;\n+\tlast_sel_trans_num_avail_hc_at_start = hcd->available_host_channels;\n+#endif /* DEBUG_HOST_CHANNELS */\n+\n+\t/* Process entries in the periodic ready list. */\n+\tqh_ptr = DWC_LIST_FIRST(&hcd->periodic_sched_ready);\n+\n+\twhile (qh_ptr != &hcd->periodic_sched_ready &&\n+\t       !DWC_CIRCLEQ_EMPTY(&hcd->free_hc_list)) {\n+\n+\t\tqh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry);\n+\n+\t\tif (microframe_schedule) {\n+\t\t\t// Make sure we leave one channel for non periodic transactions.\n+\t\t\tif (hcd->available_host_channels <= 1) {\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t\thcd->available_host_channels--;\n+#ifdef DEBUG_HOST_CHANNELS\n+\t\t\tlast_sel_trans_num_per_scheduled++;\n+#endif /* DEBUG_HOST_CHANNELS */\n+\t\t}\n+\t\tqh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry);\n+\t\tassign_and_init_hc(hcd, qh);\n+\n+\t\t/*\n+\t\t * Move the QH from the periodic ready schedule to the\n+\t\t * periodic assigned schedule.\n+\t\t */\n+\t\tqh_ptr = DWC_LIST_NEXT(qh_ptr);\n+\t\tDWC_LIST_MOVE_HEAD(&hcd->periodic_sched_assigned,\n+\t\t\t\t   &qh->qh_list_entry);\n+\t}\n+\n+\t/*\n+\t * Process entries in the inactive portion of the non-periodic\n+\t * schedule. Some free host channels may not be used if they are\n+\t * reserved for periodic transfers.\n+\t */\n+\tqh_ptr = hcd->non_periodic_sched_inactive.next;\n+\tnum_channels = hcd->core_if->core_params->host_channels;\n+\twhile (qh_ptr != &hcd->non_periodic_sched_inactive &&\n+\t       (microframe_schedule || hcd->non_periodic_channels <\n+\t\tnum_channels - hcd->periodic_channels) &&\n+\t       !DWC_CIRCLEQ_EMPTY(&hcd->free_hc_list)) {\n+\n+\t\tqh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry);\n+\t\t/*\n+\t\t * Check to see if this is a NAK'd retransmit, in which case ignore for retransmission\n+\t\t * we hold off on bulk retransmissions to reduce NAK interrupt overhead for full-speed\n+\t\t * cheeky devices that just hold off using NAKs\n+\t\t */\n+\t\tif (fiq_enable && nak_holdoff && qh->do_split) {\n+\t\t\tif (qh->nak_frame != 0xffff) {\n+\t\t\t\tuint16_t next_frame = dwc_frame_num_inc(qh->nak_frame, (qh->ep_type == UE_BULK) ? nak_holdoff : 8);\n+\t\t\t\tuint16_t frame = dwc_otg_hcd_get_frame_number(hcd);\n+\t\t\t\tif (dwc_frame_num_le(frame, next_frame)) {\n+\t\t\t\t\tif(dwc_frame_num_le(next_frame, hcd->fiq_state->next_sched_frame)) {\n+\t\t\t\t\t\thcd->fiq_state->next_sched_frame = next_frame;\n+\t\t\t\t\t}\n+\t\t\t\t\tqh_ptr = DWC_LIST_NEXT(qh_ptr);\n+\t\t\t\t\tcontinue;\n+\t\t\t\t} else {\n+\t\t\t\t\tqh->nak_frame = 0xFFFF;\n+\t\t\t\t}\n+\t\t\t}\n+\t\t}\n+\n+\t\tif (microframe_schedule) {\n+\t\t\t\tif (hcd->available_host_channels < 1) {\n+\t\t\t\t\tbreak;\n+\t\t\t\t}\n+\t\t\t\thcd->available_host_channels--;\n+#ifdef DEBUG_HOST_CHANNELS\n+\t\t\t\tlast_sel_trans_num_nonper_scheduled++;\n+#endif /* DEBUG_HOST_CHANNELS */\n+\t\t}\n+\n+\t\tassign_and_init_hc(hcd, qh);\n+\n+\t\t/*\n+\t\t * Move the QH from the non-periodic inactive schedule to the\n+\t\t * non-periodic active schedule.\n+\t\t */\n+\t\tqh_ptr = DWC_LIST_NEXT(qh_ptr);\n+\t\tDWC_LIST_MOVE_HEAD(&hcd->non_periodic_sched_active,\n+\t\t\t\t   &qh->qh_list_entry);\n+\n+\t\tif (!microframe_schedule)\n+\t\t\thcd->non_periodic_channels++;\n+\t}\n+\t/* we moved a non-periodic QH to the active schedule. If the inactive queue is empty,\n+\t * stop the FIQ from kicking us. We could potentially still have elements here if we\n+\t * ran out of host channels.\n+\t */\n+\tif (fiq_enable) {\n+\t\tif (DWC_LIST_EMPTY(&hcd->non_periodic_sched_inactive)) {\n+\t\t\thcd->fiq_state->kick_np_queues = 0;\n+\t\t} else {\n+\t\t\t/* For each entry remaining in the NP inactive queue,\n+\t\t\t* if this a NAK'd retransmit then don't set the kick flag.\n+\t\t\t*/\n+\t\t\tif(nak_holdoff) {\n+\t\t\t\tDWC_LIST_FOREACH(qh_ptr, &hcd->non_periodic_sched_inactive) {\n+\t\t\t\t\tqh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry);\n+\t\t\t\t\tif (qh->nak_frame == 0xFFFF) {\n+\t\t\t\t\t\thcd->fiq_state->kick_np_queues = 1;\n+\t\t\t\t\t}\n+\t\t\t\t}\n+\t\t\t}\n+\t\t}\n+\t}\n+\tif(!DWC_LIST_EMPTY(&hcd->periodic_sched_assigned))\n+\t\tret_val |= DWC_OTG_TRANSACTION_PERIODIC;\n+\n+\tif(!DWC_LIST_EMPTY(&hcd->non_periodic_sched_active))\n+\t\tret_val |= DWC_OTG_TRANSACTION_NON_PERIODIC;\n+\n+\n+#ifdef DEBUG_HOST_CHANNELS\n+\tlast_sel_trans_num_avail_hc_at_end = hcd->available_host_channels;\n+#endif /* DEBUG_HOST_CHANNELS */\n+\treturn ret_val;\n+}\n+\n+/**\n+ * Attempts to queue a single transaction request for a host channel\n+ * associated with either a periodic or non-periodic transfer. This function\n+ * assumes that there is space available in the appropriate request queue. For\n+ * an OUT transfer or SETUP transaction in Slave mode, it checks whether space\n+ * is available in the appropriate Tx FIFO.\n+ *\n+ * @param hcd The HCD state structure.\n+ * @param hc Host channel descriptor associated with either a periodic or\n+ * non-periodic transfer.\n+ * @param fifo_dwords_avail Number of DWORDs available in the periodic Tx\n+ * FIFO for periodic transfers or the non-periodic Tx FIFO for non-periodic\n+ * transfers.\n+ *\n+ * @return 1 if a request is queued and more requests may be needed to\n+ * complete the transfer, 0 if no more requests are required for this\n+ * transfer, -1 if there is insufficient space in the Tx FIFO.\n+ */\n+static int queue_transaction(dwc_otg_hcd_t * hcd,\n+\t\t\t     dwc_hc_t * hc, uint16_t fifo_dwords_avail)\n+{\n+\tint retval;\n+\n+\tif (hcd->core_if->dma_enable) {\n+\t\tif (hcd->core_if->dma_desc_enable) {\n+\t\t\tif (!hc->xfer_started\n+\t\t\t    || (hc->ep_type == DWC_OTG_EP_TYPE_ISOC)) {\n+\t\t\t\tdwc_otg_hcd_start_xfer_ddma(hcd, hc->qh);\n+\t\t\t\thc->qh->ping_state = 0;\n+\t\t\t}\n+\t\t} else if (!hc->xfer_started) {\n+\t\t\tif (fiq_fsm_enable && hc->error_state) {\n+\t\t\t\thcd->fiq_state->channel[hc->hc_num].nr_errors =\n+\t\t\t\t\tDWC_CIRCLEQ_FIRST(&hc->qh->qtd_list)->error_count;\n+\t\t\t\thcd->fiq_state->channel[hc->hc_num].fsm =\n+\t\t\t\t\tFIQ_PASSTHROUGH_ERRORSTATE;\n+\t\t\t}\n+\t\t\tdwc_otg_hc_start_transfer(hcd->core_if, hc);\n+\t\t\thc->qh->ping_state = 0;\n+\t\t}\n+\t\tretval = 0;\n+\t} else if (hc->halt_pending) {\n+\t\t/* Don't queue a request if the channel has been halted. */\n+\t\tretval = 0;\n+\t} else if (hc->halt_on_queue) {\n+\t\tdwc_otg_hc_halt(hcd->core_if, hc, hc->halt_status);\n+\t\tretval = 0;\n+\t} else if (hc->do_ping) {\n+\t\tif (!hc->xfer_started) {\n+\t\t\tdwc_otg_hc_start_transfer(hcd->core_if, hc);\n+\t\t}\n+\t\tretval = 0;\n+\t} else if (!hc->ep_is_in || hc->data_pid_start == DWC_OTG_HC_PID_SETUP) {\n+\t\tif ((fifo_dwords_avail * 4) >= hc->max_packet) {\n+\t\t\tif (!hc->xfer_started) {\n+\t\t\t\tdwc_otg_hc_start_transfer(hcd->core_if, hc);\n+\t\t\t\tretval = 1;\n+\t\t\t} else {\n+\t\t\t\tretval =\n+\t\t\t\t    dwc_otg_hc_continue_transfer(hcd->core_if,\n+\t\t\t\t\t\t\t\t hc);\n+\t\t\t}\n+\t\t} else {\n+\t\t\tretval = -1;\n+\t\t}\n+\t} else {\n+\t\tif (!hc->xfer_started) {\n+\t\t\tdwc_otg_hc_start_transfer(hcd->core_if, hc);\n+\t\t\tretval = 1;\n+\t\t} else {\n+\t\t\tretval = dwc_otg_hc_continue_transfer(hcd->core_if, hc);\n+\t\t}\n+\t}\n+\n+\treturn retval;\n+}\n+\n+/**\n+ * Processes periodic channels for the next frame and queues transactions for\n+ * these channels to the DWC_otg controller. After queueing transactions, the\n+ * Periodic Tx FIFO Empty interrupt is enabled if there are more transactions\n+ * to queue as Periodic Tx FIFO or request queue space becomes available.\n+ * Otherwise, the Periodic Tx FIFO Empty interrupt is disabled.\n+ */\n+static void process_periodic_channels(dwc_otg_hcd_t * hcd)\n+{\n+\thptxsts_data_t tx_status;\n+\tdwc_list_link_t *qh_ptr;\n+\tdwc_otg_qh_t *qh;\n+\tint status = 0;\n+\tint no_queue_space = 0;\n+\tint no_fifo_space = 0;\n+\n+\tdwc_otg_host_global_regs_t *host_regs;\n+\thost_regs = hcd->core_if->host_if->host_global_regs;\n+\n+\tDWC_DEBUGPL(DBG_HCDV, \"Queue periodic transactions\\n\");\n+#ifdef DEBUG\n+\ttx_status.d32 = DWC_READ_REG32(&host_regs->hptxsts);\n+\tDWC_DEBUGPL(DBG_HCDV,\n+\t\t    \"  P Tx Req Queue Space Avail (before queue): %d\\n\",\n+\t\t    tx_status.b.ptxqspcavail);\n+\tDWC_DEBUGPL(DBG_HCDV, \"  P Tx FIFO Space Avail (before queue): %d\\n\",\n+\t\t    tx_status.b.ptxfspcavail);\n+#endif\n+\n+\tqh_ptr = hcd->periodic_sched_assigned.next;\n+\twhile (qh_ptr != &hcd->periodic_sched_assigned) {\n+\t\ttx_status.d32 = DWC_READ_REG32(&host_regs->hptxsts);\n+\t\tif (tx_status.b.ptxqspcavail == 0) {\n+\t\t\tno_queue_space = 1;\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\tqh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry);\n+\n+\t\t// Do not send a split start transaction any later than frame .6\n+\t\t// Note, we have to schedule a periodic in .5 to make it go in .6\n+\t\tif(fiq_fsm_enable && qh->do_split && ((dwc_otg_hcd_get_frame_number(hcd) + 1) & 7) > 6)\n+\t\t{\n+\t\t\tqh_ptr = qh_ptr->next;\n+\t\t\thcd->fiq_state->next_sched_frame = dwc_otg_hcd_get_frame_number(hcd) | 7;\n+\t\t\tcontinue;\n+\t\t}\n+\n+\t\tif (fiq_fsm_enable && fiq_fsm_transaction_suitable(hcd, qh)) {\n+\t\t\tif (qh->do_split)\n+\t\t\t\tfiq_fsm_queue_split_transaction(hcd, qh);\n+\t\t\telse\n+\t\t\t\tfiq_fsm_queue_isoc_transaction(hcd, qh);\n+\t\t} else {\n+\n+\t\t\t/*\n+\t\t\t * Set a flag if we're queueing high-bandwidth in slave mode.\n+\t\t\t * The flag prevents any halts to get into the request queue in\n+\t\t\t * the middle of multiple high-bandwidth packets getting queued.\n+\t\t\t */\n+\t\t\tif (!hcd->core_if->dma_enable && qh->channel->multi_count > 1) {\n+\t\t\t\thcd->core_if->queuing_high_bandwidth = 1;\n+\t\t\t}\n+\t\t\tstatus = queue_transaction(hcd, qh->channel,\n+\t\t\t\t\t\t\ttx_status.b.ptxfspcavail);\n+\t\t\tif (status < 0) {\n+\t\t\t\tno_fifo_space = 1;\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t}\n+\n+\t\t/*\n+\t\t * In Slave mode, stay on the current transfer until there is\n+\t\t * nothing more to do or the high-bandwidth request count is\n+\t\t * reached. In DMA mode, only need to queue one request. The\n+\t\t * controller automatically handles multiple packets for\n+\t\t * high-bandwidth transfers.\n+\t\t */\n+\t\tif (hcd->core_if->dma_enable || status == 0 ||\n+\t\t    qh->channel->requests == qh->channel->multi_count) {\n+\t\t\tqh_ptr = qh_ptr->next;\n+\t\t\t/*\n+\t\t\t * Move the QH from the periodic assigned schedule to\n+\t\t\t * the periodic queued schedule.\n+\t\t\t */\n+\t\t\tDWC_LIST_MOVE_HEAD(&hcd->periodic_sched_queued,\n+\t\t\t\t\t   &qh->qh_list_entry);\n+\n+\t\t\t/* done queuing high bandwidth */\n+\t\t\thcd->core_if->queuing_high_bandwidth = 0;\n+\t\t}\n+\t}\n+\n+\tif (!hcd->core_if->dma_enable) {\n+\t\tdwc_otg_core_global_regs_t *global_regs;\n+\t\tgintmsk_data_t intr_mask = {.d32 = 0 };\n+\n+\t\tglobal_regs = hcd->core_if->core_global_regs;\n+\t\tintr_mask.b.ptxfempty = 1;\n+#ifdef DEBUG\n+\t\ttx_status.d32 = DWC_READ_REG32(&host_regs->hptxsts);\n+\t\tDWC_DEBUGPL(DBG_HCDV,\n+\t\t\t    \"  P Tx Req Queue Space Avail (after queue): %d\\n\",\n+\t\t\t    tx_status.b.ptxqspcavail);\n+\t\tDWC_DEBUGPL(DBG_HCDV,\n+\t\t\t    \"  P Tx FIFO Space Avail (after queue): %d\\n\",\n+\t\t\t    tx_status.b.ptxfspcavail);\n+#endif\n+\t\tif (!DWC_LIST_EMPTY(&hcd->periodic_sched_assigned) ||\n+\t\t    no_queue_space || no_fifo_space) {\n+\t\t\t/*\n+\t\t\t * May need to queue more transactions as the request\n+\t\t\t * queue or Tx FIFO empties. Enable the periodic Tx\n+\t\t\t * FIFO empty interrupt. (Always use the half-empty\n+\t\t\t * level to ensure that new requests are loaded as\n+\t\t\t * soon as possible.)\n+\t\t\t */\n+\t\t\tDWC_MODIFY_REG32(&global_regs->gintmsk, 0,\n+\t\t\t\t\t intr_mask.d32);\n+\t\t} else {\n+\t\t\t/*\n+\t\t\t * Disable the Tx FIFO empty interrupt since there are\n+\t\t\t * no more transactions that need to be queued right\n+\t\t\t * now. This function is called from interrupt\n+\t\t\t * handlers to queue more transactions as transfer\n+\t\t\t * states change.\n+\t\t\t */\n+\t\t\tDWC_MODIFY_REG32(&global_regs->gintmsk, intr_mask.d32,\n+\t\t\t\t\t 0);\n+\t\t}\n+\t}\n+}\n+\n+/**\n+ * Processes active non-periodic channels and queues transactions for these\n+ * channels to the DWC_otg controller. After queueing transactions, the NP Tx\n+ * FIFO Empty interrupt is enabled if there are more transactions to queue as\n+ * NP Tx FIFO or request queue space becomes available. Otherwise, the NP Tx\n+ * FIFO Empty interrupt is disabled.\n+ */\n+static void process_non_periodic_channels(dwc_otg_hcd_t * hcd)\n+{\n+\tgnptxsts_data_t tx_status;\n+\tdwc_list_link_t *orig_qh_ptr;\n+\tdwc_otg_qh_t *qh;\n+\tint status;\n+\tint no_queue_space = 0;\n+\tint no_fifo_space = 0;\n+\tint more_to_do = 0;\n+\n+\tdwc_otg_core_global_regs_t *global_regs =\n+\t    hcd->core_if->core_global_regs;\n+\n+\tDWC_DEBUGPL(DBG_HCDV, \"Queue non-periodic transactions\\n\");\n+#ifdef DEBUG\n+\ttx_status.d32 = DWC_READ_REG32(&global_regs->gnptxsts);\n+\tDWC_DEBUGPL(DBG_HCDV,\n+\t\t    \"  NP Tx Req Queue Space Avail (before queue): %d\\n\",\n+\t\t    tx_status.b.nptxqspcavail);\n+\tDWC_DEBUGPL(DBG_HCDV, \"  NP Tx FIFO Space Avail (before queue): %d\\n\",\n+\t\t    tx_status.b.nptxfspcavail);\n+#endif\n+\t/*\n+\t * Keep track of the starting point. Skip over the start-of-list\n+\t * entry.\n+\t */\n+\tif (hcd->non_periodic_qh_ptr == &hcd->non_periodic_sched_active) {\n+\t\thcd->non_periodic_qh_ptr = hcd->non_periodic_qh_ptr->next;\n+\t}\n+\torig_qh_ptr = hcd->non_periodic_qh_ptr;\n+\n+\t/*\n+\t * Process once through the active list or until no more space is\n+\t * available in the request queue or the Tx FIFO.\n+\t */\n+\tdo {\n+\t\ttx_status.d32 = DWC_READ_REG32(&global_regs->gnptxsts);\n+\t\tif (!hcd->core_if->dma_enable && tx_status.b.nptxqspcavail == 0) {\n+\t\t\tno_queue_space = 1;\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\tqh = DWC_LIST_ENTRY(hcd->non_periodic_qh_ptr, dwc_otg_qh_t,\n+\t\t\t\t    qh_list_entry);\n+\n+\t\tif(fiq_fsm_enable && fiq_fsm_transaction_suitable(hcd, qh)) {\n+\t\t\tfiq_fsm_queue_split_transaction(hcd, qh);\n+\t\t} else {\n+\t\t\tstatus = queue_transaction(hcd, qh->channel,\n+\t\t\t\t\t\ttx_status.b.nptxfspcavail);\n+\n+\t\t\tif (status > 0) {\n+\t\t\t\tmore_to_do = 1;\n+\t\t\t} else if (status < 0) {\n+\t\t\t\tno_fifo_space = 1;\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t}\n+\t\t/* Advance to next QH, skipping start-of-list entry. */\n+\t\thcd->non_periodic_qh_ptr = hcd->non_periodic_qh_ptr->next;\n+\t\tif (hcd->non_periodic_qh_ptr == &hcd->non_periodic_sched_active) {\n+\t\t\thcd->non_periodic_qh_ptr =\n+\t\t\t    hcd->non_periodic_qh_ptr->next;\n+\t\t}\n+\n+\t} while (hcd->non_periodic_qh_ptr != orig_qh_ptr);\n+\n+\tif (!hcd->core_if->dma_enable) {\n+\t\tgintmsk_data_t intr_mask = {.d32 = 0 };\n+\t\tintr_mask.b.nptxfempty = 1;\n+\n+#ifdef DEBUG\n+\t\ttx_status.d32 = DWC_READ_REG32(&global_regs->gnptxsts);\n+\t\tDWC_DEBUGPL(DBG_HCDV,\n+\t\t\t    \"  NP Tx Req Queue Space Avail (after queue): %d\\n\",\n+\t\t\t    tx_status.b.nptxqspcavail);\n+\t\tDWC_DEBUGPL(DBG_HCDV,\n+\t\t\t    \"  NP Tx FIFO Space Avail (after queue): %d\\n\",\n+\t\t\t    tx_status.b.nptxfspcavail);\n+#endif\n+\t\tif (more_to_do || no_queue_space || no_fifo_space) {\n+\t\t\t/*\n+\t\t\t * May need to queue more transactions as the request\n+\t\t\t * queue or Tx FIFO empties. Enable the non-periodic\n+\t\t\t * Tx FIFO empty interrupt. (Always use the half-empty\n+\t\t\t * level to ensure that new requests are loaded as\n+\t\t\t * soon as possible.)\n+\t\t\t */\n+\t\t\tDWC_MODIFY_REG32(&global_regs->gintmsk, 0,\n+\t\t\t\t\t intr_mask.d32);\n+\t\t} else {\n+\t\t\t/*\n+\t\t\t * Disable the Tx FIFO empty interrupt since there are\n+\t\t\t * no more transactions that need to be queued right\n+\t\t\t * now. This function is called from interrupt\n+\t\t\t * handlers to queue more transactions as transfer\n+\t\t\t * states change.\n+\t\t\t */\n+\t\t\tDWC_MODIFY_REG32(&global_regs->gintmsk, intr_mask.d32,\n+\t\t\t\t\t 0);\n+\t\t}\n+\t}\n+}\n+\n+/**\n+ * This function processes the currently active host channels and queues\n+ * transactions for these channels to the DWC_otg controller. It is called\n+ * from HCD interrupt handler functions.\n+ *\n+ * @param hcd The HCD state structure.\n+ * @param tr_type The type(s) of transactions to queue (non-periodic,\n+ * periodic, or both).\n+ */\n+void dwc_otg_hcd_queue_transactions(dwc_otg_hcd_t * hcd,\n+\t\t\t\t    dwc_otg_transaction_type_e tr_type)\n+{\n+#ifdef DEBUG_SOF\n+\tDWC_DEBUGPL(DBG_HCD, \"Queue Transactions\\n\");\n+#endif\n+\t/* Process host channels associated with periodic transfers. */\n+\tif ((tr_type == DWC_OTG_TRANSACTION_PERIODIC ||\n+\t     tr_type == DWC_OTG_TRANSACTION_ALL) &&\n+\t    !DWC_LIST_EMPTY(&hcd->periodic_sched_assigned)) {\n+\n+\t\tprocess_periodic_channels(hcd);\n+\t}\n+\n+\t/* Process host channels associated with non-periodic transfers. */\n+\tif (tr_type == DWC_OTG_TRANSACTION_NON_PERIODIC ||\n+\t    tr_type == DWC_OTG_TRANSACTION_ALL) {\n+\t\tif (!DWC_LIST_EMPTY(&hcd->non_periodic_sched_active)) {\n+\t\t\tprocess_non_periodic_channels(hcd);\n+\t\t} else {\n+\t\t\t/*\n+\t\t\t * Ensure NP Tx FIFO empty interrupt is disabled when\n+\t\t\t * there are no non-periodic transfers to process.\n+\t\t\t */\n+\t\t\tgintmsk_data_t gintmsk = {.d32 = 0 };\n+\t\t\tgintmsk.b.nptxfempty = 1;\n+\n+\t\t\tif (fiq_enable) {\n+\t\t\t\tlocal_fiq_disable();\n+\t\t\t\tfiq_fsm_spin_lock(&hcd->fiq_state->lock);\n+\t\t\t\tDWC_MODIFY_REG32(&hcd->core_if->core_global_regs->gintmsk, gintmsk.d32, 0);\n+\t\t\t\tfiq_fsm_spin_unlock(&hcd->fiq_state->lock);\n+\t\t\t\tlocal_fiq_enable();\n+\t\t\t} else {\n+\t\t\t\tDWC_MODIFY_REG32(&hcd->core_if->core_global_regs->gintmsk, gintmsk.d32, 0);\n+\t\t\t}\n+\t\t}\n+\t}\n+}\n+\n+#ifdef DWC_HS_ELECT_TST\n+/*\n+ * Quick and dirty hack to implement the HS Electrical Test\n+ * SINGLE_STEP_GET_DEVICE_DESCRIPTOR feature.\n+ *\n+ * This code was copied from our userspace app \"hset\". It sends a\n+ * Get Device Descriptor control sequence in two parts, first the\n+ * Setup packet by itself, followed some time later by the In and\n+ * Ack packets. Rather than trying to figure out how to add this\n+ * functionality to the normal driver code, we just hijack the\n+ * hardware, using these two function to drive the hardware\n+ * directly.\n+ */\n+\n+static dwc_otg_core_global_regs_t *global_regs;\n+static dwc_otg_host_global_regs_t *hc_global_regs;\n+static dwc_otg_hc_regs_t *hc_regs;\n+static uint32_t *data_fifo;\n+\n+static void do_setup(void)\n+{\n+\tgintsts_data_t gintsts;\n+\thctsiz_data_t hctsiz;\n+\thcchar_data_t hcchar;\n+\thaint_data_t haint;\n+\thcint_data_t hcint;\n+\n+\t/* Enable HAINTs */\n+\tDWC_WRITE_REG32(&hc_global_regs->haintmsk, 0x0001);\n+\n+\t/* Enable HCINTs */\n+\tDWC_WRITE_REG32(&hc_regs->hcintmsk, 0x04a3);\n+\n+\t/* Read GINTSTS */\n+\tgintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);\n+\n+\t/* Read HAINT */\n+\thaint.d32 = DWC_READ_REG32(&hc_global_regs->haint);\n+\n+\t/* Read HCINT */\n+\thcint.d32 = DWC_READ_REG32(&hc_regs->hcint);\n+\n+\t/* Read HCCHAR */\n+\thcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);\n+\n+\t/* Clear HCINT */\n+\tDWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);\n+\n+\t/* Clear HAINT */\n+\tDWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);\n+\n+\t/* Clear GINTSTS */\n+\tDWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);\n+\n+\t/* Read GINTSTS */\n+\tgintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);\n+\n+\t/*\n+\t * Send Setup packet (Get Device Descriptor)\n+\t */\n+\n+\t/* Make sure channel is disabled */\n+\thcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);\n+\tif (hcchar.b.chen) {\n+\t\thcchar.b.chdis = 1;\n+//              hcchar.b.chen = 1;\n+\t\tDWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);\n+\t\t//sleep(1);\n+\t\tdwc_mdelay(1000);\n+\n+\t\t/* Read GINTSTS */\n+\t\tgintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);\n+\n+\t\t/* Read HAINT */\n+\t\thaint.d32 = DWC_READ_REG32(&hc_global_regs->haint);\n+\n+\t\t/* Read HCINT */\n+\t\thcint.d32 = DWC_READ_REG32(&hc_regs->hcint);\n+\n+\t\t/* Read HCCHAR */\n+\t\thcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);\n+\n+\t\t/* Clear HCINT */\n+\t\tDWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);\n+\n+\t\t/* Clear HAINT */\n+\t\tDWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);\n+\n+\t\t/* Clear GINTSTS */\n+\t\tDWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);\n+\n+\t\thcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);\n+\t}\n+\n+\t/* Set HCTSIZ */\n+\thctsiz.d32 = 0;\n+\thctsiz.b.xfersize = 8;\n+\thctsiz.b.pktcnt = 1;\n+\thctsiz.b.pid = DWC_OTG_HC_PID_SETUP;\n+\tDWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32);\n+\n+\t/* Set HCCHAR */\n+\thcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);\n+\thcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;\n+\thcchar.b.epdir = 0;\n+\thcchar.b.epnum = 0;\n+\thcchar.b.mps = 8;\n+\thcchar.b.chen = 1;\n+\tDWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);\n+\n+\t/* Fill FIFO with Setup data for Get Device Descriptor */\n+\tdata_fifo = (uint32_t *) ((char *)global_regs + 0x1000);\n+\tDWC_WRITE_REG32(data_fifo++, 0x01000680);\n+\tDWC_WRITE_REG32(data_fifo++, 0x00080000);\n+\n+\tgintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);\n+\n+\t/* Wait for host channel interrupt */\n+\tdo {\n+\t\tgintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);\n+\t} while (gintsts.b.hcintr == 0);\n+\n+\t/* Disable HCINTs */\n+\tDWC_WRITE_REG32(&hc_regs->hcintmsk, 0x0000);\n+\n+\t/* Disable HAINTs */\n+\tDWC_WRITE_REG32(&hc_global_regs->haintmsk, 0x0000);\n+\n+\t/* Read HAINT */\n+\thaint.d32 = DWC_READ_REG32(&hc_global_regs->haint);\n+\n+\t/* Read HCINT */\n+\thcint.d32 = DWC_READ_REG32(&hc_regs->hcint);\n+\n+\t/* Read HCCHAR */\n+\thcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);\n+\n+\t/* Clear HCINT */\n+\tDWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);\n+\n+\t/* Clear HAINT */\n+\tDWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);\n+\n+\t/* Clear GINTSTS */\n+\tDWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);\n+\n+\t/* Read GINTSTS */\n+\tgintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);\n+}\n+\n+static void do_in_ack(void)\n+{\n+\tgintsts_data_t gintsts;\n+\thctsiz_data_t hctsiz;\n+\thcchar_data_t hcchar;\n+\thaint_data_t haint;\n+\thcint_data_t hcint;\n+\thost_grxsts_data_t grxsts;\n+\n+\t/* Enable HAINTs */\n+\tDWC_WRITE_REG32(&hc_global_regs->haintmsk, 0x0001);\n+\n+\t/* Enable HCINTs */\n+\tDWC_WRITE_REG32(&hc_regs->hcintmsk, 0x04a3);\n+\n+\t/* Read GINTSTS */\n+\tgintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);\n+\n+\t/* Read HAINT */\n+\thaint.d32 = DWC_READ_REG32(&hc_global_regs->haint);\n+\n+\t/* Read HCINT */\n+\thcint.d32 = DWC_READ_REG32(&hc_regs->hcint);\n+\n+\t/* Read HCCHAR */\n+\thcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);\n+\n+\t/* Clear HCINT */\n+\tDWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);\n+\n+\t/* Clear HAINT */\n+\tDWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);\n+\n+\t/* Clear GINTSTS */\n+\tDWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);\n+\n+\t/* Read GINTSTS */\n+\tgintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);\n+\n+\t/*\n+\t * Receive Control In packet\n+\t */\n+\n+\t/* Make sure channel is disabled */\n+\thcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);\n+\tif (hcchar.b.chen) {\n+\t\thcchar.b.chdis = 1;\n+\t\thcchar.b.chen = 1;\n+\t\tDWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);\n+\t\t//sleep(1);\n+\t\tdwc_mdelay(1000);\n+\n+\t\t/* Read GINTSTS */\n+\t\tgintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);\n+\n+\t\t/* Read HAINT */\n+\t\thaint.d32 = DWC_READ_REG32(&hc_global_regs->haint);\n+\n+\t\t/* Read HCINT */\n+\t\thcint.d32 = DWC_READ_REG32(&hc_regs->hcint);\n+\n+\t\t/* Read HCCHAR */\n+\t\thcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);\n+\n+\t\t/* Clear HCINT */\n+\t\tDWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);\n+\n+\t\t/* Clear HAINT */\n+\t\tDWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);\n+\n+\t\t/* Clear GINTSTS */\n+\t\tDWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);\n+\n+\t\thcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);\n+\t}\n+\n+\t/* Set HCTSIZ */\n+\thctsiz.d32 = 0;\n+\thctsiz.b.xfersize = 8;\n+\thctsiz.b.pktcnt = 1;\n+\thctsiz.b.pid = DWC_OTG_HC_PID_DATA1;\n+\tDWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32);\n+\n+\t/* Set HCCHAR */\n+\thcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);\n+\thcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;\n+\thcchar.b.epdir = 1;\n+\thcchar.b.epnum = 0;\n+\thcchar.b.mps = 8;\n+\thcchar.b.chen = 1;\n+\tDWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);\n+\n+\tgintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);\n+\n+\t/* Wait for receive status queue interrupt */\n+\tdo {\n+\t\tgintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);\n+\t} while (gintsts.b.rxstsqlvl == 0);\n+\n+\t/* Read RXSTS */\n+\tgrxsts.d32 = DWC_READ_REG32(&global_regs->grxstsp);\n+\n+\t/* Clear RXSTSQLVL in GINTSTS */\n+\tgintsts.d32 = 0;\n+\tgintsts.b.rxstsqlvl = 1;\n+\tDWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);\n+\n+\tswitch (grxsts.b.pktsts) {\n+\tcase DWC_GRXSTS_PKTSTS_IN:\n+\t\t/* Read the data into the host buffer */\n+\t\tif (grxsts.b.bcnt > 0) {\n+\t\t\tint i;\n+\t\t\tint word_count = (grxsts.b.bcnt + 3) / 4;\n+\n+\t\t\tdata_fifo = (uint32_t *) ((char *)global_regs + 0x1000);\n+\n+\t\t\tfor (i = 0; i < word_count; i++) {\n+\t\t\t\t(void)DWC_READ_REG32(data_fifo++);\n+\t\t\t}\n+\t\t}\n+\t\tbreak;\n+\n+\tdefault:\n+\t\tbreak;\n+\t}\n+\n+\tgintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);\n+\n+\t/* Wait for receive status queue interrupt */\n+\tdo {\n+\t\tgintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);\n+\t} while (gintsts.b.rxstsqlvl == 0);\n+\n+\t/* Read RXSTS */\n+\tgrxsts.d32 = DWC_READ_REG32(&global_regs->grxstsp);\n+\n+\t/* Clear RXSTSQLVL in GINTSTS */\n+\tgintsts.d32 = 0;\n+\tgintsts.b.rxstsqlvl = 1;\n+\tDWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);\n+\n+\tswitch (grxsts.b.pktsts) {\n+\tcase DWC_GRXSTS_PKTSTS_IN_XFER_COMP:\n+\t\tbreak;\n+\n+\tdefault:\n+\t\tbreak;\n+\t}\n+\n+\tgintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);\n+\n+\t/* Wait for host channel interrupt */\n+\tdo {\n+\t\tgintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);\n+\t} while (gintsts.b.hcintr == 0);\n+\n+\t/* Read HAINT */\n+\thaint.d32 = DWC_READ_REG32(&hc_global_regs->haint);\n+\n+\t/* Read HCINT */\n+\thcint.d32 = DWC_READ_REG32(&hc_regs->hcint);\n+\n+\t/* Read HCCHAR */\n+\thcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);\n+\n+\t/* Clear HCINT */\n+\tDWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);\n+\n+\t/* Clear HAINT */\n+\tDWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);\n+\n+\t/* Clear GINTSTS */\n+\tDWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);\n+\n+\t/* Read GINTSTS */\n+\tgintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);\n+\n+//      usleep(100000);\n+//      mdelay(100);\n+\tdwc_mdelay(1);\n+\n+\t/*\n+\t * Send handshake packet\n+\t */\n+\n+\t/* Read HAINT */\n+\thaint.d32 = DWC_READ_REG32(&hc_global_regs->haint);\n+\n+\t/* Read HCINT */\n+\thcint.d32 = DWC_READ_REG32(&hc_regs->hcint);\n+\n+\t/* Read HCCHAR */\n+\thcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);\n+\n+\t/* Clear HCINT */\n+\tDWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);\n+\n+\t/* Clear HAINT */\n+\tDWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);\n+\n+\t/* Clear GINTSTS */\n+\tDWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);\n+\n+\t/* Read GINTSTS */\n+\tgintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);\n+\n+\t/* Make sure channel is disabled */\n+\thcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);\n+\tif (hcchar.b.chen) {\n+\t\thcchar.b.chdis = 1;\n+\t\thcchar.b.chen = 1;\n+\t\tDWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);\n+\t\t//sleep(1);\n+\t\tdwc_mdelay(1000);\n+\n+\t\t/* Read GINTSTS */\n+\t\tgintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);\n+\n+\t\t/* Read HAINT */\n+\t\thaint.d32 = DWC_READ_REG32(&hc_global_regs->haint);\n+\n+\t\t/* Read HCINT */\n+\t\thcint.d32 = DWC_READ_REG32(&hc_regs->hcint);\n+\n+\t\t/* Read HCCHAR */\n+\t\thcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);\n+\n+\t\t/* Clear HCINT */\n+\t\tDWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);\n+\n+\t\t/* Clear HAINT */\n+\t\tDWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);\n+\n+\t\t/* Clear GINTSTS */\n+\t\tDWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);\n+\n+\t\thcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);\n+\t}\n+\n+\t/* Set HCTSIZ */\n+\thctsiz.d32 = 0;\n+\thctsiz.b.xfersize = 0;\n+\thctsiz.b.pktcnt = 1;\n+\thctsiz.b.pid = DWC_OTG_HC_PID_DATA1;\n+\tDWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32);\n+\n+\t/* Set HCCHAR */\n+\thcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);\n+\thcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;\n+\thcchar.b.epdir = 0;\n+\thcchar.b.epnum = 0;\n+\thcchar.b.mps = 8;\n+\thcchar.b.chen = 1;\n+\tDWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);\n+\n+\tgintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);\n+\n+\t/* Wait for host channel interrupt */\n+\tdo {\n+\t\tgintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);\n+\t} while (gintsts.b.hcintr == 0);\n+\n+\t/* Disable HCINTs */\n+\tDWC_WRITE_REG32(&hc_regs->hcintmsk, 0x0000);\n+\n+\t/* Disable HAINTs */\n+\tDWC_WRITE_REG32(&hc_global_regs->haintmsk, 0x0000);\n+\n+\t/* Read HAINT */\n+\thaint.d32 = DWC_READ_REG32(&hc_global_regs->haint);\n+\n+\t/* Read HCINT */\n+\thcint.d32 = DWC_READ_REG32(&hc_regs->hcint);\n+\n+\t/* Read HCCHAR */\n+\thcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);\n+\n+\t/* Clear HCINT */\n+\tDWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);\n+\n+\t/* Clear HAINT */\n+\tDWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);\n+\n+\t/* Clear GINTSTS */\n+\tDWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);\n+\n+\t/* Read GINTSTS */\n+\tgintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);\n+}\n+#endif\n+\n+/** Handles hub class-specific requests. */\n+int dwc_otg_hcd_hub_control(dwc_otg_hcd_t * dwc_otg_hcd,\n+\t\t\t    uint16_t typeReq,\n+\t\t\t    uint16_t wValue,\n+\t\t\t    uint16_t wIndex, uint8_t * buf, uint16_t wLength)\n+{\n+\tint retval = 0;\n+\n+\tdwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;\n+\tusb_hub_descriptor_t *hub_desc;\n+\thprt0_data_t hprt0 = {.d32 = 0 };\n+\n+\tuint32_t port_status;\n+\n+\tswitch (typeReq) {\n+\tcase UCR_CLEAR_HUB_FEATURE:\n+\t\tDWC_DEBUGPL(DBG_HCD, \"DWC OTG HCD HUB CONTROL - \"\n+\t\t\t    \"ClearHubFeature 0x%x\\n\", wValue);\n+\t\tswitch (wValue) {\n+\t\tcase UHF_C_HUB_LOCAL_POWER:\n+\t\tcase UHF_C_HUB_OVER_CURRENT:\n+\t\t\t/* Nothing required here */\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tretval = -DWC_E_INVALID;\n+\t\t\tDWC_ERROR(\"DWC OTG HCD - \"\n+\t\t\t\t  \"ClearHubFeature request %xh unknown\\n\",\n+\t\t\t\t  wValue);\n+\t\t}\n+\t\tbreak;\n+\tcase UCR_CLEAR_PORT_FEATURE:\n+#ifdef CONFIG_USB_DWC_OTG_LPM\n+\t\tif (wValue != UHF_PORT_L1)\n+#endif\n+\t\t\tif (!wIndex || wIndex > 1)\n+\t\t\t\tgoto error;\n+\n+\t\tswitch (wValue) {\n+\t\tcase UHF_PORT_ENABLE:\n+\t\t\tDWC_DEBUGPL(DBG_ANY, \"DWC OTG HCD HUB CONTROL - \"\n+\t\t\t\t    \"ClearPortFeature USB_PORT_FEAT_ENABLE\\n\");\n+\t\t\thprt0.d32 = dwc_otg_read_hprt0(core_if);\n+\t\t\thprt0.b.prtena = 1;\n+\t\t\tDWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);\n+\t\t\tbreak;\n+\t\tcase UHF_PORT_SUSPEND:\n+\t\t\tDWC_DEBUGPL(DBG_HCD, \"DWC OTG HCD HUB CONTROL - \"\n+\t\t\t\t    \"ClearPortFeature USB_PORT_FEAT_SUSPEND\\n\");\n+\n+\t\t\tif (core_if->power_down == 2) {\n+\t\t\t\tdwc_otg_host_hibernation_restore(core_if, 0, 0);\n+\t\t\t} else {\n+\t\t\t\tDWC_WRITE_REG32(core_if->pcgcctl, 0);\n+\t\t\t\tdwc_mdelay(5);\n+\n+\t\t\t\thprt0.d32 = dwc_otg_read_hprt0(core_if);\n+\t\t\t\thprt0.b.prtres = 1;\n+\t\t\t\tDWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);\n+\t\t\t\thprt0.b.prtsusp = 0;\n+\t\t\t\t/* Clear Resume bit */\n+\t\t\t\tdwc_mdelay(100);\n+\t\t\t\thprt0.b.prtres = 0;\n+\t\t\t\tDWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);\n+\t\t\t}\n+\t\t\tbreak;\n+#ifdef CONFIG_USB_DWC_OTG_LPM\n+\t\tcase UHF_PORT_L1:\n+\t\t\t{\n+\t\t\t\tpcgcctl_data_t pcgcctl = {.d32 = 0 };\n+\t\t\t\tglpmcfg_data_t lpmcfg = {.d32 = 0 };\n+\n+\t\t\t\tlpmcfg.d32 =\n+\t\t\t\t    DWC_READ_REG32(&core_if->\n+\t\t\t\t\t\t   core_global_regs->glpmcfg);\n+\t\t\t\tlpmcfg.b.en_utmi_sleep = 0;\n+\t\t\t\tlpmcfg.b.hird_thres &= (~(1 << 4));\n+\t\t\t\tlpmcfg.b.prt_sleep_sts = 1;\n+\t\t\t\tDWC_WRITE_REG32(&core_if->\n+\t\t\t\t\t\tcore_global_regs->glpmcfg,\n+\t\t\t\t\t\tlpmcfg.d32);\n+\n+\t\t\t\t/* Clear Enbl_L1Gating bit. */\n+\t\t\t\tpcgcctl.b.enbl_sleep_gating = 1;\n+\t\t\t\tDWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32,\n+\t\t\t\t\t\t 0);\n+\n+\t\t\t\tdwc_mdelay(5);\n+\n+\t\t\t\thprt0.d32 = dwc_otg_read_hprt0(core_if);\n+\t\t\t\thprt0.b.prtres = 1;\n+\t\t\t\tDWC_WRITE_REG32(core_if->host_if->hprt0,\n+\t\t\t\t\t\thprt0.d32);\n+\t\t\t\t/* This bit will be cleared in wakeup interrupt handle */\n+\t\t\t\tbreak;\n+\t\t\t}\n+#endif\n+\t\tcase UHF_PORT_POWER:\n+\t\t\tDWC_DEBUGPL(DBG_HCD, \"DWC OTG HCD HUB CONTROL - \"\n+\t\t\t\t    \"ClearPortFeature USB_PORT_FEAT_POWER\\n\");\n+\t\t\thprt0.d32 = dwc_otg_read_hprt0(core_if);\n+\t\t\thprt0.b.prtpwr = 0;\n+\t\t\tDWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);\n+\t\t\tbreak;\n+\t\tcase UHF_PORT_INDICATOR:\n+\t\t\tDWC_DEBUGPL(DBG_HCD, \"DWC OTG HCD HUB CONTROL - \"\n+\t\t\t\t    \"ClearPortFeature USB_PORT_FEAT_INDICATOR\\n\");\n+\t\t\t/* Port inidicator not supported */\n+\t\t\tbreak;\n+\t\tcase UHF_C_PORT_CONNECTION:\n+\t\t\t/* Clears drivers internal connect status change\n+\t\t\t * flag */\n+\t\t\tDWC_DEBUGPL(DBG_HCD, \"DWC OTG HCD HUB CONTROL - \"\n+\t\t\t\t    \"ClearPortFeature USB_PORT_FEAT_C_CONNECTION\\n\");\n+\t\t\tdwc_otg_hcd->flags.b.port_connect_status_change = 0;\n+\t\t\tbreak;\n+\t\tcase UHF_C_PORT_RESET:\n+\t\t\t/* Clears the driver's internal Port Reset Change\n+\t\t\t * flag */\n+\t\t\tDWC_DEBUGPL(DBG_HCD, \"DWC OTG HCD HUB CONTROL - \"\n+\t\t\t\t    \"ClearPortFeature USB_PORT_FEAT_C_RESET\\n\");\n+\t\t\tdwc_otg_hcd->flags.b.port_reset_change = 0;\n+\t\t\tbreak;\n+\t\tcase UHF_C_PORT_ENABLE:\n+\t\t\t/* Clears the driver's internal Port\n+\t\t\t * Enable/Disable Change flag */\n+\t\t\tDWC_DEBUGPL(DBG_HCD, \"DWC OTG HCD HUB CONTROL - \"\n+\t\t\t\t    \"ClearPortFeature USB_PORT_FEAT_C_ENABLE\\n\");\n+\t\t\tdwc_otg_hcd->flags.b.port_enable_change = 0;\n+\t\t\tbreak;\n+\t\tcase UHF_C_PORT_SUSPEND:\n+\t\t\t/* Clears the driver's internal Port Suspend\n+\t\t\t * Change flag, which is set when resume signaling on\n+\t\t\t * the host port is complete */\n+\t\t\tDWC_DEBUGPL(DBG_HCD, \"DWC OTG HCD HUB CONTROL - \"\n+\t\t\t\t    \"ClearPortFeature USB_PORT_FEAT_C_SUSPEND\\n\");\n+\t\t\tdwc_otg_hcd->flags.b.port_suspend_change = 0;\n+\t\t\tbreak;\n+#ifdef CONFIG_USB_DWC_OTG_LPM\n+\t\tcase UHF_C_PORT_L1:\n+\t\t\tdwc_otg_hcd->flags.b.port_l1_change = 0;\n+\t\t\tbreak;\n+#endif\n+\t\tcase UHF_C_PORT_OVER_CURRENT:\n+\t\t\tDWC_DEBUGPL(DBG_HCD, \"DWC OTG HCD HUB CONTROL - \"\n+\t\t\t\t    \"ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\\n\");\n+\t\t\tdwc_otg_hcd->flags.b.port_over_current_change = 0;\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tretval = -DWC_E_INVALID;\n+\t\t\tDWC_ERROR(\"DWC OTG HCD - \"\n+\t\t\t\t  \"ClearPortFeature request %xh \"\n+\t\t\t\t  \"unknown or unsupported\\n\", wValue);\n+\t\t}\n+\t\tbreak;\n+\tcase UCR_GET_HUB_DESCRIPTOR:\n+\t\tDWC_DEBUGPL(DBG_HCD, \"DWC OTG HCD HUB CONTROL - \"\n+\t\t\t    \"GetHubDescriptor\\n\");\n+\t\thub_desc = (usb_hub_descriptor_t *) buf;\n+\t\thub_desc->bDescLength = 9;\n+\t\thub_desc->bDescriptorType = 0x29;\n+\t\thub_desc->bNbrPorts = 1;\n+\t\tUSETW(hub_desc->wHubCharacteristics, 0x08);\n+\t\thub_desc->bPwrOn2PwrGood = 1;\n+\t\thub_desc->bHubContrCurrent = 0;\n+\t\thub_desc->DeviceRemovable[0] = 0;\n+\t\thub_desc->DeviceRemovable[1] = 0xff;\n+\t\tbreak;\n+\tcase UCR_GET_HUB_STATUS:\n+\t\tDWC_DEBUGPL(DBG_HCD, \"DWC OTG HCD HUB CONTROL - \"\n+\t\t\t    \"GetHubStatus\\n\");\n+\t\tDWC_MEMSET(buf, 0, 4);\n+\t\tbreak;\n+\tcase UCR_GET_PORT_STATUS:\n+\t\tDWC_DEBUGPL(DBG_HCD, \"DWC OTG HCD HUB CONTROL - \"\n+\t\t\t    \"GetPortStatus wIndex = 0x%04x FLAGS=0x%08x\\n\",\n+\t\t\t    wIndex, dwc_otg_hcd->flags.d32);\n+\t\tif (!wIndex || wIndex > 1)\n+\t\t\tgoto error;\n+\n+\t\tport_status = 0;\n+\n+\t\tif (dwc_otg_hcd->flags.b.port_connect_status_change)\n+\t\t\tport_status |= (1 << UHF_C_PORT_CONNECTION);\n+\n+\t\tif (dwc_otg_hcd->flags.b.port_enable_change)\n+\t\t\tport_status |= (1 << UHF_C_PORT_ENABLE);\n+\n+\t\tif (dwc_otg_hcd->flags.b.port_suspend_change)\n+\t\t\tport_status |= (1 << UHF_C_PORT_SUSPEND);\n+\n+\t\tif (dwc_otg_hcd->flags.b.port_l1_change)\n+\t\t\tport_status |= (1 << UHF_C_PORT_L1);\n+\n+\t\tif (dwc_otg_hcd->flags.b.port_reset_change) {\n+\t\t\tport_status |= (1 << UHF_C_PORT_RESET);\n+\t\t}\n+\n+\t\tif (dwc_otg_hcd->flags.b.port_over_current_change) {\n+\t\t\tDWC_WARN(\"Overcurrent change detected\\n\");\n+\t\t\tport_status |= (1 << UHF_C_PORT_OVER_CURRENT);\n+\t\t}\n+\n+\t\tif (!dwc_otg_hcd->flags.b.port_connect_status) {\n+\t\t\t/*\n+\t\t\t * The port is disconnected, which means the core is\n+\t\t\t * either in device mode or it soon will be. Just\n+\t\t\t * return 0's for the remainder of the port status\n+\t\t\t * since the port register can't be read if the core\n+\t\t\t * is in device mode.\n+\t\t\t */\n+\t\t\t*((__le32 *) buf) = dwc_cpu_to_le32(&port_status);\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\thprt0.d32 = DWC_READ_REG32(core_if->host_if->hprt0);\n+\t\tDWC_DEBUGPL(DBG_HCDV, \"  HPRT0: 0x%08x\\n\", hprt0.d32);\n+\n+\t\tif (hprt0.b.prtconnsts)\n+\t\t\tport_status |= (1 << UHF_PORT_CONNECTION);\n+\n+\t\tif (hprt0.b.prtena)\n+\t\t\tport_status |= (1 << UHF_PORT_ENABLE);\n+\n+\t\tif (hprt0.b.prtsusp)\n+\t\t\tport_status |= (1 << UHF_PORT_SUSPEND);\n+\n+\t\tif (hprt0.b.prtovrcurract)\n+\t\t\tport_status |= (1 << UHF_PORT_OVER_CURRENT);\n+\n+\t\tif (hprt0.b.prtrst)\n+\t\t\tport_status |= (1 << UHF_PORT_RESET);\n+\n+\t\tif (hprt0.b.prtpwr)\n+\t\t\tport_status |= (1 << UHF_PORT_POWER);\n+\n+\t\tif (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_HIGH_SPEED)\n+\t\t\tport_status |= (1 << UHF_PORT_HIGH_SPEED);\n+\t\telse if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_LOW_SPEED)\n+\t\t\tport_status |= (1 << UHF_PORT_LOW_SPEED);\n+\n+\t\tif (hprt0.b.prttstctl)\n+\t\t\tport_status |= (1 << UHF_PORT_TEST);\n+\t\tif (dwc_otg_get_lpm_portsleepstatus(dwc_otg_hcd->core_if)) {\n+\t\t\tport_status |= (1 << UHF_PORT_L1);\n+\t\t}\n+\t\t/*\n+\t\t   For Synopsys HW emulation of Power down wkup_control asserts the\n+\t\t   hreset_n and prst_n on suspned. This causes the HPRT0 to be zero.\n+\t\t   We intentionally tell the software that port is in L2Suspend state.\n+\t\t   Only for STE.\n+\t\t*/\n+\t\tif ((core_if->power_down == 2)\n+\t\t    && (core_if->hibernation_suspend == 1)) {\n+\t\t\tport_status |= (1 << UHF_PORT_SUSPEND);\n+\t\t}\n+\t\t/* USB_PORT_FEAT_INDICATOR unsupported always 0 */\n+\n+\t\t*((__le32 *) buf) = dwc_cpu_to_le32(&port_status);\n+\n+\t\tbreak;\n+\tcase UCR_SET_HUB_FEATURE:\n+\t\tDWC_DEBUGPL(DBG_HCD, \"DWC OTG HCD HUB CONTROL - \"\n+\t\t\t    \"SetHubFeature\\n\");\n+\t\t/* No HUB features supported */\n+\t\tbreak;\n+\tcase UCR_SET_PORT_FEATURE:\n+\t\tif (wValue != UHF_PORT_TEST && (!wIndex || wIndex > 1))\n+\t\t\tgoto error;\n+\n+\t\tif (!dwc_otg_hcd->flags.b.port_connect_status) {\n+\t\t\t/*\n+\t\t\t * The port is disconnected, which means the core is\n+\t\t\t * either in device mode or it soon will be. Just\n+\t\t\t * return without doing anything since the port\n+\t\t\t * register can't be written if the core is in device\n+\t\t\t * mode.\n+\t\t\t */\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\tswitch (wValue) {\n+\t\tcase UHF_PORT_SUSPEND:\n+\t\t\tDWC_DEBUGPL(DBG_HCD, \"DWC OTG HCD HUB CONTROL - \"\n+\t\t\t\t    \"SetPortFeature - USB_PORT_FEAT_SUSPEND\\n\");\n+\t\t\tif (dwc_otg_hcd_otg_port(dwc_otg_hcd) != wIndex) {\n+\t\t\t\tgoto error;\n+\t\t\t}\n+\t\t\tif (core_if->power_down == 2) {\n+\t\t\t\tint timeout = 300;\n+\t\t\t\tdwc_irqflags_t flags;\n+\t\t\t\tpcgcctl_data_t pcgcctl = {.d32 = 0 };\n+\t\t\t\tgpwrdn_data_t gpwrdn = {.d32 = 0 };\n+\t\t\t\tgusbcfg_data_t gusbcfg = {.d32 = 0 };\n+#ifdef DWC_DEV_SRPCAP\n+\t\t\t\tint32_t otg_cap_param = core_if->core_params->otg_cap;\n+#endif\n+\t\t\t\tDWC_PRINTF(\"Preparing for complete power-off\\n\");\n+\n+\t\t\t\t/* Save registers before hibernation */\n+\t\t\t\tdwc_otg_save_global_regs(core_if);\n+\t\t\t\tdwc_otg_save_host_regs(core_if);\n+\n+\t\t\t\thprt0.d32 = dwc_otg_read_hprt0(core_if);\n+\t\t\t\thprt0.b.prtsusp = 1;\n+\t\t\t\thprt0.b.prtena = 0;\n+\t\t\t\tDWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);\n+\t\t\t\t/* Spin hprt0.b.prtsusp to became 1 */\n+\t\t\t\tdo {\n+\t\t\t\t\thprt0.d32 = dwc_otg_read_hprt0(core_if);\n+\t\t\t\t\tif (hprt0.b.prtsusp) {\n+\t\t\t\t\t\tbreak;\n+\t\t\t\t\t}\n+\t\t\t\t\tdwc_mdelay(1);\n+\t\t\t\t} while (--timeout);\n+\t\t\t\tif (!timeout) {\n+\t\t\t\t\tDWC_WARN(\"Suspend wasn't genereted\\n\");\n+\t\t\t\t}\n+\t\t\t\tdwc_udelay(10);\n+\n+\t\t\t\t/*\n+\t\t\t\t * We need to disable interrupts to prevent servicing of any IRQ\n+\t\t\t\t * during going to hibernation\n+\t\t\t\t */\n+\t\t\t\tDWC_SPINLOCK_IRQSAVE(dwc_otg_hcd->lock, &flags);\n+\t\t\t\tcore_if->lx_state = DWC_OTG_L2;\n+#ifdef DWC_DEV_SRPCAP\n+\t\t\t\thprt0.d32 = dwc_otg_read_hprt0(core_if);\n+\t\t\t\thprt0.b.prtpwr = 0;\n+\t\t\t\thprt0.b.prtena = 0;\n+\t\t\t\tDWC_WRITE_REG32(core_if->host_if->hprt0,\n+\t\t\t\t\t\thprt0.d32);\n+#endif\n+\t\t\t\tgusbcfg.d32 =\n+\t\t\t\t    DWC_READ_REG32(&core_if->core_global_regs->\n+\t\t\t\t\t\t   gusbcfg);\n+\t\t\t\tif (gusbcfg.b.ulpi_utmi_sel == 1) {\n+\t\t\t\t\t/* ULPI interface */\n+\t\t\t\t\t/* Suspend the Phy Clock */\n+\t\t\t\t\tpcgcctl.d32 = 0;\n+\t\t\t\t\tpcgcctl.b.stoppclk = 1;\n+\t\t\t\t\tDWC_MODIFY_REG32(core_if->pcgcctl, 0,\n+\t\t\t\t\t\t\t pcgcctl.d32);\n+\t\t\t\t\tdwc_udelay(10);\n+\t\t\t\t\tgpwrdn.b.pmuactv = 1;\n+\t\t\t\t\tDWC_MODIFY_REG32(&core_if->\n+\t\t\t\t\t\t\t core_global_regs->\n+\t\t\t\t\t\t\t gpwrdn, 0, gpwrdn.d32);\n+\t\t\t\t} else {\n+\t\t\t\t\t/* UTMI+ Interface */\n+\t\t\t\t\tgpwrdn.b.pmuactv = 1;\n+\t\t\t\t\tDWC_MODIFY_REG32(&core_if->\n+\t\t\t\t\t\t\t core_global_regs->\n+\t\t\t\t\t\t\t gpwrdn, 0, gpwrdn.d32);\n+\t\t\t\t\tdwc_udelay(10);\n+\t\t\t\t\tpcgcctl.b.stoppclk = 1;\n+\t\t\t\t\tDWC_MODIFY_REG32(core_if->pcgcctl, 0, pcgcctl.d32);\n+\t\t\t\t\tdwc_udelay(10);\n+\t\t\t\t}\n+#ifdef DWC_DEV_SRPCAP\n+\t\t\t\tgpwrdn.d32 = 0;\n+\t\t\t\tgpwrdn.b.dis_vbus = 1;\n+\t\t\t\tDWC_MODIFY_REG32(&core_if->core_global_regs->\n+\t\t\t\t\t\t gpwrdn, 0, gpwrdn.d32);\n+#endif\n+\t\t\t\tgpwrdn.d32 = 0;\n+\t\t\t\tgpwrdn.b.pmuintsel = 1;\n+\t\t\t\tDWC_MODIFY_REG32(&core_if->core_global_regs->\n+\t\t\t\t\t\t gpwrdn, 0, gpwrdn.d32);\n+\t\t\t\tdwc_udelay(10);\n+\n+\t\t\t\tgpwrdn.d32 = 0;\n+#ifdef DWC_DEV_SRPCAP\n+\t\t\t\tgpwrdn.b.srp_det_msk = 1;\n+#endif\n+\t\t\t\tgpwrdn.b.disconn_det_msk = 1;\n+\t\t\t\tgpwrdn.b.lnstchng_msk = 1;\n+\t\t\t\tgpwrdn.b.sts_chngint_msk = 1;\n+\t\t\t\tDWC_MODIFY_REG32(&core_if->core_global_regs->\n+\t\t\t\t\t\t gpwrdn, 0, gpwrdn.d32);\n+\t\t\t\tdwc_udelay(10);\n+\n+\t\t\t\t/* Enable Power Down Clamp and all interrupts in GPWRDN */\n+\t\t\t\tgpwrdn.d32 = 0;\n+\t\t\t\tgpwrdn.b.pwrdnclmp = 1;\n+\t\t\t\tDWC_MODIFY_REG32(&core_if->core_global_regs->\n+\t\t\t\t\t\t gpwrdn, 0, gpwrdn.d32);\n+\t\t\t\tdwc_udelay(10);\n+\n+\t\t\t\t/* Switch off VDD */\n+\t\t\t\tgpwrdn.d32 = 0;\n+\t\t\t\tgpwrdn.b.pwrdnswtch = 1;\n+\t\t\t\tDWC_MODIFY_REG32(&core_if->core_global_regs->\n+\t\t\t\t\t\t gpwrdn, 0, gpwrdn.d32);\n+\n+#ifdef DWC_DEV_SRPCAP\n+\t\t\t\tif (otg_cap_param == DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE)\n+\t\t\t\t{\n+\t\t\t\t\tcore_if->pwron_timer_started = 1;\n+\t\t\t\t\tDWC_TIMER_SCHEDULE(core_if->pwron_timer, 6000 /* 6 secs */ );\n+\t\t\t\t}\n+#endif\n+\t\t\t\t/* Save gpwrdn register for further usage if stschng interrupt */\n+\t\t\t\tcore_if->gr_backup->gpwrdn_local =\n+\t\t\t\t\t\tDWC_READ_REG32(&core_if->core_global_regs->gpwrdn);\n+\n+\t\t\t\t/* Set flag to indicate that we are in hibernation */\n+\t\t\t\tcore_if->hibernation_suspend = 1;\n+\t\t\t\tDWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock,flags);\n+\n+\t\t\t\tDWC_PRINTF(\"Host hibernation completed\\n\");\n+\t\t\t\t// Exit from case statement\n+\t\t\t\tbreak;\n+\n+\t\t\t}\n+\t\t\tif (dwc_otg_hcd_otg_port(dwc_otg_hcd) == wIndex &&\n+\t\t\t    dwc_otg_hcd->fops->get_b_hnp_enable(dwc_otg_hcd)) {\n+\t\t\t\tgotgctl_data_t gotgctl = {.d32 = 0 };\n+\t\t\t\tgotgctl.b.hstsethnpen = 1;\n+\t\t\t\tDWC_MODIFY_REG32(&core_if->core_global_regs->\n+\t\t\t\t\t\t gotgctl, 0, gotgctl.d32);\n+\t\t\t\tcore_if->op_state = A_SUSPEND;\n+\t\t\t}\n+\t\t\thprt0.d32 = dwc_otg_read_hprt0(core_if);\n+\t\t\thprt0.b.prtsusp = 1;\n+\t\t\tDWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);\n+\t\t\t{\n+\t\t\t\tdwc_irqflags_t flags;\n+\t\t\t\t/* Update lx_state */\n+\t\t\t\tDWC_SPINLOCK_IRQSAVE(dwc_otg_hcd->lock, &flags);\n+\t\t\t\tcore_if->lx_state = DWC_OTG_L2;\n+\t\t\t\tDWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock, flags);\n+\t\t\t}\n+\t\t\t/* Suspend the Phy Clock */\n+\t\t\t{\n+\t\t\t\tpcgcctl_data_t pcgcctl = {.d32 = 0 };\n+\t\t\t\tpcgcctl.b.stoppclk = 1;\n+\t\t\t\tDWC_MODIFY_REG32(core_if->pcgcctl, 0,\n+\t\t\t\t\t\t pcgcctl.d32);\n+\t\t\t\tdwc_udelay(10);\n+\t\t\t}\n+\n+\t\t\t/* For HNP the bus must be suspended for at least 200ms. */\n+\t\t\tif (dwc_otg_hcd->fops->get_b_hnp_enable(dwc_otg_hcd)) {\n+\t\t\t\tpcgcctl_data_t pcgcctl = {.d32 = 0 };\n+\t\t\t\tpcgcctl.b.stoppclk = 1;\n+                DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0);\n+\t\t\t\tdwc_mdelay(200);\n+\t\t\t}\n+\n+\t\t\t/** @todo - check how sw can wait for 1 sec to check asesvld??? */\n+#if 0 //vahrama !!!!!!!!!!!!!!!!!!\n+\t\t\tif (core_if->adp_enable) {\n+\t\t\t\tgotgctl_data_t gotgctl = {.d32 = 0 };\n+\t\t\t\tgpwrdn_data_t gpwrdn;\n+\n+\t\t\t\twhile (gotgctl.b.asesvld == 1) {\n+\t\t\t\t\tgotgctl.d32 =\n+\t\t\t\t\t    DWC_READ_REG32(&core_if->\n+\t\t\t\t\t\t\t   core_global_regs->\n+\t\t\t\t\t\t\t   gotgctl);\n+\t\t\t\t\tdwc_mdelay(100);\n+\t\t\t\t}\n+\n+\t\t\t\t/* Enable Power Down Logic */\n+\t\t\t\tgpwrdn.d32 = 0;\n+\t\t\t\tgpwrdn.b.pmuactv = 1;\n+\t\t\t\tDWC_MODIFY_REG32(&core_if->core_global_regs->\n+\t\t\t\t\t\t gpwrdn, 0, gpwrdn.d32);\n+\n+\t\t\t\t/* Unmask SRP detected interrupt from Power Down Logic */\n+\t\t\t\tgpwrdn.d32 = 0;\n+\t\t\t\tgpwrdn.b.srp_det_msk = 1;\n+\t\t\t\tDWC_MODIFY_REG32(&core_if->core_global_regs->\n+\t\t\t\t\t\t gpwrdn, 0, gpwrdn.d32);\n+\n+\t\t\t\tdwc_otg_adp_probe_start(core_if);\n+\t\t\t}\n+#endif\n+\t\t\tbreak;\n+\t\tcase UHF_PORT_POWER:\n+\t\t\tDWC_DEBUGPL(DBG_HCD, \"DWC OTG HCD HUB CONTROL - \"\n+\t\t\t\t    \"SetPortFeature - USB_PORT_FEAT_POWER\\n\");\n+\t\t\thprt0.d32 = dwc_otg_read_hprt0(core_if);\n+\t\t\thprt0.b.prtpwr = 1;\n+\t\t\tDWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);\n+\t\t\tbreak;\n+\t\tcase UHF_PORT_RESET:\n+\t\t\tif ((core_if->power_down == 2)\n+\t\t\t    && (core_if->hibernation_suspend == 1)) {\n+\t\t\t\t/* If we are going to exit from Hibernated\n+\t\t\t\t * state via USB RESET.\n+\t\t\t\t */\n+\t\t\t\tdwc_otg_host_hibernation_restore(core_if, 0, 1);\n+\t\t\t} else {\n+\t\t\t\thprt0.d32 = dwc_otg_read_hprt0(core_if);\n+\n+\t\t\t\tDWC_DEBUGPL(DBG_HCD,\n+\t\t\t\t\t    \"DWC OTG HCD HUB CONTROL - \"\n+\t\t\t\t\t    \"SetPortFeature - USB_PORT_FEAT_RESET\\n\");\n+\t\t\t\t{\n+\t\t\t\t\tpcgcctl_data_t pcgcctl = {.d32 = 0 };\n+\t\t\t\t\tpcgcctl.b.enbl_sleep_gating = 1;\n+\t\t\t\t\tpcgcctl.b.stoppclk = 1;\n+\t\t\t\t\tDWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0);\n+\t\t\t\t\tDWC_WRITE_REG32(core_if->pcgcctl, 0);\n+\t\t\t\t}\n+#ifdef CONFIG_USB_DWC_OTG_LPM\n+\t\t\t\t{\n+\t\t\t\t\tglpmcfg_data_t lpmcfg;\n+\t\t\t\t\tlpmcfg.d32 =\n+\t\t\t\t\t\tDWC_READ_REG32(&core_if->core_global_regs->glpmcfg);\n+\t\t\t\t\tif (lpmcfg.b.prt_sleep_sts) {\n+\t\t\t\t\t\tlpmcfg.b.en_utmi_sleep = 0;\n+\t\t\t\t\t\tlpmcfg.b.hird_thres &= (~(1 << 4));\n+\t\t\t\t\t\tDWC_WRITE_REG32\n+\t\t\t\t\t\t    (&core_if->core_global_regs->glpmcfg,\n+\t\t\t\t\t\t     lpmcfg.d32);\n+\t\t\t\t\t\tdwc_mdelay(1);\n+\t\t\t\t\t}\n+\t\t\t\t}\n+#endif\n+\t\t\t\thprt0.d32 = dwc_otg_read_hprt0(core_if);\n+\t\t\t\t/* Clear suspend bit if resetting from suspended state. */\n+\t\t\t\thprt0.b.prtsusp = 0;\n+\t\t\t\t/* When B-Host the Port reset bit is set in\n+\t\t\t\t * the Start HCD Callback function, so that\n+\t\t\t\t * the reset is started within 1ms of the HNP\n+\t\t\t\t * success interrupt. */\n+\t\t\t\tif (!dwc_otg_hcd_is_b_host(dwc_otg_hcd)) {\n+\t\t\t\t\thprt0.b.prtpwr = 1;\n+\t\t\t\t\thprt0.b.prtrst = 1;\n+\t\t\t\t\tDWC_PRINTF(\"Indeed it is in host mode hprt0 = %08x\\n\",hprt0.d32);\n+\t\t\t\t\tDWC_WRITE_REG32(core_if->host_if->hprt0,\n+\t\t\t\t\t\t\thprt0.d32);\n+\t\t\t\t}\n+\t\t\t\t/* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */\n+\t\t\t\tdwc_mdelay(60);\n+\t\t\t\thprt0.b.prtrst = 0;\n+\t\t\t\tDWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);\n+\t\t\t\tcore_if->lx_state = DWC_OTG_L0;\t/* Now back to the on state */\n+\t\t\t}\n+\t\t\tbreak;\n+#ifdef DWC_HS_ELECT_TST\n+\t\tcase UHF_PORT_TEST:\n+\t\t\t{\n+\t\t\t\tuint32_t t;\n+\t\t\t\tgintmsk_data_t gintmsk;\n+\n+\t\t\t\tt = (wIndex >> 8);\t/* MSB wIndex USB */\n+\t\t\t\tDWC_DEBUGPL(DBG_HCD,\n+\t\t\t\t\t    \"DWC OTG HCD HUB CONTROL - \"\n+\t\t\t\t\t    \"SetPortFeature - USB_PORT_FEAT_TEST %d\\n\",\n+\t\t\t\t\t    t);\n+\t\t\t\tDWC_WARN(\"USB_PORT_FEAT_TEST %d\\n\", t);\n+\t\t\t\tif (t < 6) {\n+\t\t\t\t\thprt0.d32 = dwc_otg_read_hprt0(core_if);\n+\t\t\t\t\thprt0.b.prttstctl = t;\n+\t\t\t\t\tDWC_WRITE_REG32(core_if->host_if->hprt0,\n+\t\t\t\t\t\t\thprt0.d32);\n+\t\t\t\t} else {\n+\t\t\t\t\t/* Setup global vars with reg addresses (quick and\n+\t\t\t\t\t * dirty hack, should be cleaned up)\n+\t\t\t\t\t */\n+\t\t\t\t\tglobal_regs = core_if->core_global_regs;\n+\t\t\t\t\thc_global_regs =\n+\t\t\t\t\t    core_if->host_if->host_global_regs;\n+\t\t\t\t\thc_regs =\n+\t\t\t\t\t    (dwc_otg_hc_regs_t *) ((char *)\n+\t\t\t\t\t\t\t\t   global_regs +\n+\t\t\t\t\t\t\t\t   0x500);\n+\t\t\t\t\tdata_fifo =\n+\t\t\t\t\t    (uint32_t *) ((char *)global_regs +\n+\t\t\t\t\t\t\t  0x1000);\n+\n+\t\t\t\t\tif (t == 6) {\t/* HS_HOST_PORT_SUSPEND_RESUME */\n+\t\t\t\t\t\t/* Save current interrupt mask */\n+\t\t\t\t\t\tgintmsk.d32 =\n+\t\t\t\t\t\t    DWC_READ_REG32\n+\t\t\t\t\t\t    (&global_regs->gintmsk);\n+\n+\t\t\t\t\t\t/* Disable all interrupts while we muck with\n+\t\t\t\t\t\t * the hardware directly\n+\t\t\t\t\t\t */\n+\t\t\t\t\t\tDWC_WRITE_REG32(&global_regs->gintmsk, 0);\n+\n+\t\t\t\t\t\t/* 15 second delay per the test spec */\n+\t\t\t\t\t\tdwc_mdelay(15000);\n+\n+\t\t\t\t\t\t/* Drive suspend on the root port */\n+\t\t\t\t\t\thprt0.d32 =\n+\t\t\t\t\t\t    dwc_otg_read_hprt0(core_if);\n+\t\t\t\t\t\thprt0.b.prtsusp = 1;\n+\t\t\t\t\t\thprt0.b.prtres = 0;\n+\t\t\t\t\t\tDWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);\n+\n+\t\t\t\t\t\t/* 15 second delay per the test spec */\n+\t\t\t\t\t\tdwc_mdelay(15000);\n+\n+\t\t\t\t\t\t/* Drive resume on the root port */\n+\t\t\t\t\t\thprt0.d32 =\n+\t\t\t\t\t\t    dwc_otg_read_hprt0(core_if);\n+\t\t\t\t\t\thprt0.b.prtsusp = 0;\n+\t\t\t\t\t\thprt0.b.prtres = 1;\n+\t\t\t\t\t\tDWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);\n+\t\t\t\t\t\tdwc_mdelay(100);\n+\n+\t\t\t\t\t\t/* Clear the resume bit */\n+\t\t\t\t\t\thprt0.b.prtres = 0;\n+\t\t\t\t\t\tDWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);\n+\n+\t\t\t\t\t\t/* Restore interrupts */\n+\t\t\t\t\t\tDWC_WRITE_REG32(&global_regs->gintmsk, gintmsk.d32);\n+\t\t\t\t\t} else if (t == 7) {\t/* SINGLE_STEP_GET_DEVICE_DESCRIPTOR setup */\n+\t\t\t\t\t\t/* Save current interrupt mask */\n+\t\t\t\t\t\tgintmsk.d32 =\n+\t\t\t\t\t\t    DWC_READ_REG32\n+\t\t\t\t\t\t    (&global_regs->gintmsk);\n+\n+\t\t\t\t\t\t/* Disable all interrupts while we muck with\n+\t\t\t\t\t\t * the hardware directly\n+\t\t\t\t\t\t */\n+\t\t\t\t\t\tDWC_WRITE_REG32(&global_regs->gintmsk, 0);\n+\n+\t\t\t\t\t\t/* 15 second delay per the test spec */\n+\t\t\t\t\t\tdwc_mdelay(15000);\n+\n+\t\t\t\t\t\t/* Send the Setup packet */\n+\t\t\t\t\t\tdo_setup();\n+\n+\t\t\t\t\t\t/* 15 second delay so nothing else happens for awhile */\n+\t\t\t\t\t\tdwc_mdelay(15000);\n+\n+\t\t\t\t\t\t/* Restore interrupts */\n+\t\t\t\t\t\tDWC_WRITE_REG32(&global_regs->gintmsk, gintmsk.d32);\n+\t\t\t\t\t} else if (t == 8) {\t/* SINGLE_STEP_GET_DEVICE_DESCRIPTOR execute */\n+\t\t\t\t\t\t/* Save current interrupt mask */\n+\t\t\t\t\t\tgintmsk.d32 =\n+\t\t\t\t\t\t    DWC_READ_REG32\n+\t\t\t\t\t\t    (&global_regs->gintmsk);\n+\n+\t\t\t\t\t\t/* Disable all interrupts while we muck with\n+\t\t\t\t\t\t * the hardware directly\n+\t\t\t\t\t\t */\n+\t\t\t\t\t\tDWC_WRITE_REG32(&global_regs->gintmsk, 0);\n+\n+\t\t\t\t\t\t/* Send the Setup packet */\n+\t\t\t\t\t\tdo_setup();\n+\n+\t\t\t\t\t\t/* 15 second delay so nothing else happens for awhile */\n+\t\t\t\t\t\tdwc_mdelay(15000);\n+\n+\t\t\t\t\t\t/* Send the In and Ack packets */\n+\t\t\t\t\t\tdo_in_ack();\n+\n+\t\t\t\t\t\t/* 15 second delay so nothing else happens for awhile */\n+\t\t\t\t\t\tdwc_mdelay(15000);\n+\n+\t\t\t\t\t\t/* Restore interrupts */\n+\t\t\t\t\t\tDWC_WRITE_REG32(&global_regs->gintmsk, gintmsk.d32);\n+\t\t\t\t\t}\n+\t\t\t\t}\n+\t\t\t\tbreak;\n+\t\t\t}\n+#endif /* DWC_HS_ELECT_TST */\n+\n+\t\tcase UHF_PORT_INDICATOR:\n+\t\t\tDWC_DEBUGPL(DBG_HCD, \"DWC OTG HCD HUB CONTROL - \"\n+\t\t\t\t    \"SetPortFeature - USB_PORT_FEAT_INDICATOR\\n\");\n+\t\t\t/* Not supported */\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tretval = -DWC_E_INVALID;\n+\t\t\tDWC_ERROR(\"DWC OTG HCD - \"\n+\t\t\t\t  \"SetPortFeature request %xh \"\n+\t\t\t\t  \"unknown or unsupported\\n\", wValue);\n+\t\t\tbreak;\n+\t\t}\n+\t\tbreak;\n+#ifdef CONFIG_USB_DWC_OTG_LPM\n+\tcase UCR_SET_AND_TEST_PORT_FEATURE:\n+\t\tif (wValue != UHF_PORT_L1) {\n+\t\t\tgoto error;\n+\t\t}\n+\t\t{\n+\t\t\tint portnum, hird, devaddr, remwake;\n+\t\t\tglpmcfg_data_t lpmcfg;\n+\t\t\tuint32_t time_usecs;\n+\t\t\tgintsts_data_t gintsts;\n+\t\t\tgintmsk_data_t gintmsk;\n+\n+\t\t\tif (!dwc_otg_get_param_lpm_enable(core_if)) {\n+\t\t\t\tgoto error;\n+\t\t\t}\n+\t\t\tif (wValue != UHF_PORT_L1 || wLength != 1) {\n+\t\t\t\tgoto error;\n+\t\t\t}\n+\t\t\t/* Check if the port currently is in SLEEP state */\n+\t\t\tlpmcfg.d32 =\n+\t\t\t    DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);\n+\t\t\tif (lpmcfg.b.prt_sleep_sts) {\n+\t\t\t\tDWC_INFO(\"Port is already in sleep mode\\n\");\n+\t\t\t\tbuf[0] = 0;\t/* Return success */\n+\t\t\t\tbreak;\n+\t\t\t}\n+\n+\t\t\tportnum = wIndex & 0xf;\n+\t\t\third = (wIndex >> 4) & 0xf;\n+\t\t\tdevaddr = (wIndex >> 8) & 0x7f;\n+\t\t\tremwake = (wIndex >> 15);\n+\n+\t\t\tif (portnum != 1) {\n+\t\t\t\tretval = -DWC_E_INVALID;\n+\t\t\t\tDWC_WARN\n+\t\t\t\t    (\"Wrong port number(%d) in SetandTestPortFeature request\\n\",\n+\t\t\t\t     portnum);\n+\t\t\t\tbreak;\n+\t\t\t}\n+\n+\t\t\tDWC_PRINTF\n+\t\t\t    (\"SetandTestPortFeature request: portnum = %d, hird = %d, devaddr = %d, rewake = %d\\n\",\n+\t\t\t     portnum, hird, devaddr, remwake);\n+\t\t\t/* Disable LPM interrupt */\n+\t\t\tgintmsk.d32 = 0;\n+\t\t\tgintmsk.b.lpmtranrcvd = 1;\n+\t\t\tDWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk,\n+\t\t\t\t\t gintmsk.d32, 0);\n+\n+\t\t\tif (dwc_otg_hcd_send_lpm\n+\t\t\t    (dwc_otg_hcd, devaddr, hird, remwake)) {\n+\t\t\t\tretval = -DWC_E_INVALID;\n+\t\t\t\tbreak;\n+\t\t\t}\n+\n+\t\t\ttime_usecs = 10 * (lpmcfg.b.retry_count + 1);\n+\t\t\t/* We will consider timeout if time_usecs microseconds pass,\n+\t\t\t * and we don't receive LPM transaction status.\n+\t\t\t * After receiving non-error responce(ACK/NYET/STALL) from device,\n+\t\t\t *  core will set lpmtranrcvd bit.\n+\t\t\t */\n+\t\t\tdo {\n+\t\t\t\tgintsts.d32 =\n+\t\t\t\t    DWC_READ_REG32(&core_if->core_global_regs->gintsts);\n+\t\t\t\tif (gintsts.b.lpmtranrcvd) {\n+\t\t\t\t\tbreak;\n+\t\t\t\t}\n+\t\t\t\tdwc_udelay(1);\n+\t\t\t} while (--time_usecs);\n+\t\t\t/* lpm_int bit will be cleared in LPM interrupt handler */\n+\n+\t\t\t/* Now fill status\n+\t\t\t * 0x00 - Success\n+\t\t\t * 0x10 - NYET\n+\t\t\t * 0x11 - Timeout\n+\t\t\t */\n+\t\t\tif (!gintsts.b.lpmtranrcvd) {\n+\t\t\t\tbuf[0] = 0x3;\t/* Completion code is Timeout */\n+\t\t\t\tdwc_otg_hcd_free_hc_from_lpm(dwc_otg_hcd);\n+\t\t\t} else {\n+\t\t\t\tlpmcfg.d32 =\n+\t\t\t\t    DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);\n+\t\t\t\tif (lpmcfg.b.lpm_resp == 0x3) {\n+\t\t\t\t\t/* ACK responce from the device */\n+\t\t\t\t\tbuf[0] = 0x00;\t/* Success */\n+\t\t\t\t} else if (lpmcfg.b.lpm_resp == 0x2) {\n+\t\t\t\t\t/* NYET responce from the device */\n+\t\t\t\t\tbuf[0] = 0x2;\n+\t\t\t\t} else {\n+\t\t\t\t\t/* Otherwise responce with Timeout */\n+\t\t\t\t\tbuf[0] = 0x3;\n+\t\t\t\t}\n+\t\t\t}\n+\t\t\tDWC_PRINTF(\"Device responce to LPM trans is %x\\n\",\n+\t\t\t\t   lpmcfg.b.lpm_resp);\n+\t\t\tDWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, 0,\n+\t\t\t\t\t gintmsk.d32);\n+\n+\t\t\tbreak;\n+\t\t}\n+#endif /* CONFIG_USB_DWC_OTG_LPM */\n+\tdefault:\n+error:\n+\t\tretval = -DWC_E_INVALID;\n+\t\tDWC_WARN(\"DWC OTG HCD - \"\n+\t\t\t \"Unknown hub control request type or invalid typeReq: %xh wIndex: %xh wValue: %xh\\n\",\n+\t\t\t typeReq, wIndex, wValue);\n+\t\tbreak;\n+\t}\n+\n+\treturn retval;\n+}\n+\n+#ifdef CONFIG_USB_DWC_OTG_LPM\n+/** Returns index of host channel to perform LPM transaction. */\n+int dwc_otg_hcd_get_hc_for_lpm_tran(dwc_otg_hcd_t * hcd, uint8_t devaddr)\n+{\n+\tdwc_otg_core_if_t *core_if = hcd->core_if;\n+\tdwc_hc_t *hc;\n+\thcchar_data_t hcchar;\n+\tgintmsk_data_t gintmsk = {.d32 = 0 };\n+\n+\tif (DWC_CIRCLEQ_EMPTY(&hcd->free_hc_list)) {\n+\t\tDWC_PRINTF(\"No free channel to select for LPM transaction\\n\");\n+\t\treturn -1;\n+\t}\n+\n+\thc = DWC_CIRCLEQ_FIRST(&hcd->free_hc_list);\n+\n+\t/* Mask host channel interrupts. */\n+\tgintmsk.b.hcintr = 1;\n+\tDWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, gintmsk.d32, 0);\n+\n+\t/* Fill fields that core needs for LPM transaction */\n+\thcchar.b.devaddr = devaddr;\n+\thcchar.b.epnum = 0;\n+\thcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;\n+\thcchar.b.mps = 64;\n+\thcchar.b.lspddev = (hc->speed == DWC_OTG_EP_SPEED_LOW);\n+\thcchar.b.epdir = 0;\t/* OUT */\n+\tDWC_WRITE_REG32(&core_if->host_if->hc_regs[hc->hc_num]->hcchar,\n+\t\t\thcchar.d32);\n+\n+\t/* Remove the host channel from the free list. */\n+\tDWC_CIRCLEQ_REMOVE_INIT(&hcd->free_hc_list, hc, hc_list_entry);\n+\n+\tDWC_PRINTF(\"hcnum = %d devaddr = %d\\n\", hc->hc_num, devaddr);\n+\n+\treturn hc->hc_num;\n+}\n+\n+/** Release hc after performing LPM transaction */\n+void dwc_otg_hcd_free_hc_from_lpm(dwc_otg_hcd_t * hcd)\n+{\n+\tdwc_hc_t *hc;\n+\tglpmcfg_data_t lpmcfg;\n+\tuint8_t hc_num;\n+\n+\tlpmcfg.d32 = DWC_READ_REG32(&hcd->core_if->core_global_regs->glpmcfg);\n+\thc_num = lpmcfg.b.lpm_chan_index;\n+\n+\thc = hcd->hc_ptr_array[hc_num];\n+\n+\tDWC_PRINTF(\"Freeing channel %d after LPM\\n\", hc_num);\n+\t/* Return host channel to free list */\n+\tDWC_CIRCLEQ_INSERT_TAIL(&hcd->free_hc_list, hc, hc_list_entry);\n+}\n+\n+int dwc_otg_hcd_send_lpm(dwc_otg_hcd_t * hcd, uint8_t devaddr, uint8_t hird,\n+\t\t\t uint8_t bRemoteWake)\n+{\n+\tglpmcfg_data_t lpmcfg;\n+\tpcgcctl_data_t pcgcctl = {.d32 = 0 };\n+\tint channel;\n+\n+\tchannel = dwc_otg_hcd_get_hc_for_lpm_tran(hcd, devaddr);\n+\tif (channel < 0) {\n+\t\treturn channel;\n+\t}\n+\n+\tpcgcctl.b.enbl_sleep_gating = 1;\n+\tDWC_MODIFY_REG32(hcd->core_if->pcgcctl, 0, pcgcctl.d32);\n+\n+\t/* Read LPM config register */\n+\tlpmcfg.d32 = DWC_READ_REG32(&hcd->core_if->core_global_regs->glpmcfg);\n+\n+\t/* Program LPM transaction fields */\n+\tlpmcfg.b.rem_wkup_en = bRemoteWake;\n+\tlpmcfg.b.hird = hird;\n+\tlpmcfg.b.hird_thres = 0x1c;\n+\tlpmcfg.b.lpm_chan_index = channel;\n+\tlpmcfg.b.en_utmi_sleep = 1;\n+\t/* Program LPM config register */\n+\tDWC_WRITE_REG32(&hcd->core_if->core_global_regs->glpmcfg, lpmcfg.d32);\n+\n+\t/* Send LPM transaction */\n+\tlpmcfg.b.send_lpm = 1;\n+\tDWC_WRITE_REG32(&hcd->core_if->core_global_regs->glpmcfg, lpmcfg.d32);\n+\n+\treturn 0;\n+}\n+\n+#endif /* CONFIG_USB_DWC_OTG_LPM */\n+\n+int dwc_otg_hcd_is_status_changed(dwc_otg_hcd_t * hcd, int port)\n+{\n+\tint retval;\n+\n+\tif (port != 1) {\n+\t\treturn -DWC_E_INVALID;\n+\t}\n+\n+\tretval = (hcd->flags.b.port_connect_status_change ||\n+\t\t  hcd->flags.b.port_reset_change ||\n+\t\t  hcd->flags.b.port_enable_change ||\n+\t\t  hcd->flags.b.port_suspend_change ||\n+\t\t  hcd->flags.b.port_over_current_change);\n+#ifdef DEBUG\n+\tif (retval) {\n+\t\tDWC_DEBUGPL(DBG_HCD, \"DWC OTG HCD HUB STATUS DATA:\"\n+\t\t\t    \" Root port status changed\\n\");\n+\t\tDWC_DEBUGPL(DBG_HCDV, \"  port_connect_status_change: %d\\n\",\n+\t\t\t    hcd->flags.b.port_connect_status_change);\n+\t\tDWC_DEBUGPL(DBG_HCDV, \"  port_reset_change: %d\\n\",\n+\t\t\t    hcd->flags.b.port_reset_change);\n+\t\tDWC_DEBUGPL(DBG_HCDV, \"  port_enable_change: %d\\n\",\n+\t\t\t    hcd->flags.b.port_enable_change);\n+\t\tDWC_DEBUGPL(DBG_HCDV, \"  port_suspend_change: %d\\n\",\n+\t\t\t    hcd->flags.b.port_suspend_change);\n+\t\tDWC_DEBUGPL(DBG_HCDV, \"  port_over_current_change: %d\\n\",\n+\t\t\t    hcd->flags.b.port_over_current_change);\n+\t}\n+#endif\n+\treturn retval;\n+}\n+\n+int dwc_otg_hcd_get_frame_number(dwc_otg_hcd_t * dwc_otg_hcd)\n+{\n+\thfnum_data_t hfnum;\n+\thfnum.d32 =\n+\t    DWC_READ_REG32(&dwc_otg_hcd->core_if->host_if->host_global_regs->\n+\t\t\t   hfnum);\n+\n+#ifdef DEBUG_SOF\n+\tDWC_DEBUGPL(DBG_HCDV, \"DWC OTG HCD GET FRAME NUMBER %d\\n\",\n+\t\t    hfnum.b.frnum);\n+#endif\n+\treturn hfnum.b.frnum;\n+}\n+\n+int dwc_otg_hcd_start(dwc_otg_hcd_t * hcd,\n+\t\t      struct dwc_otg_hcd_function_ops *fops)\n+{\n+\tint retval = 0;\n+\n+\thcd->fops = fops;\n+\tif (!dwc_otg_is_device_mode(hcd->core_if) &&\n+\t\t(!hcd->core_if->adp_enable || hcd->core_if->adp.adp_started)) {\n+\t\tdwc_otg_hcd_reinit(hcd);\n+\t} else {\n+\t\tretval = -DWC_E_NO_DEVICE;\n+\t}\n+\n+\treturn retval;\n+}\n+\n+void *dwc_otg_hcd_get_priv_data(dwc_otg_hcd_t * hcd)\n+{\n+\treturn hcd->priv;\n+}\n+\n+void dwc_otg_hcd_set_priv_data(dwc_otg_hcd_t * hcd, void *priv_data)\n+{\n+\thcd->priv = priv_data;\n+}\n+\n+uint32_t dwc_otg_hcd_otg_port(dwc_otg_hcd_t * hcd)\n+{\n+\treturn hcd->otg_port;\n+}\n+\n+uint32_t dwc_otg_hcd_is_b_host(dwc_otg_hcd_t * hcd)\n+{\n+\tuint32_t is_b_host;\n+\tif (hcd->core_if->op_state == B_HOST) {\n+\t\tis_b_host = 1;\n+\t} else {\n+\t\tis_b_host = 0;\n+\t}\n+\n+\treturn is_b_host;\n+}\n+\n+dwc_otg_hcd_urb_t *dwc_otg_hcd_urb_alloc(dwc_otg_hcd_t * hcd,\n+\t\t\t\t\t int iso_desc_count, int atomic_alloc)\n+{\n+\tdwc_otg_hcd_urb_t *dwc_otg_urb;\n+\tuint32_t size;\n+\n+\tsize =\n+\t    sizeof(*dwc_otg_urb) +\n+\t    iso_desc_count * sizeof(struct dwc_otg_hcd_iso_packet_desc);\n+\tif (atomic_alloc)\n+\t\tdwc_otg_urb = DWC_ALLOC_ATOMIC(size);\n+\telse\n+\t\tdwc_otg_urb = DWC_ALLOC(size);\n+\n+        if (dwc_otg_urb)\n+\t\tdwc_otg_urb->packet_count = iso_desc_count;\n+        else {\n+\t\tDWC_ERROR(\"**** DWC OTG HCD URB alloc - \"\n+\t\t\t\"%salloc of %db failed\\n\",\n+\t\t\tatomic_alloc?\"atomic \":\"\", size);\n+\t}\n+\treturn dwc_otg_urb;\n+}\n+\n+void dwc_otg_hcd_urb_set_pipeinfo(dwc_otg_hcd_urb_t * dwc_otg_urb,\n+\t\t\t\t  uint8_t dev_addr, uint8_t ep_num,\n+\t\t\t\t  uint8_t ep_type, uint8_t ep_dir, uint16_t mps)\n+{\n+\tdwc_otg_hcd_fill_pipe(&dwc_otg_urb->pipe_info, dev_addr, ep_num,\n+\t\t\t      ep_type, ep_dir, mps);\n+#if 0\n+\tDWC_PRINTF\n+\t    (\"addr = %d, ep_num = %d, ep_dir = 0x%x, ep_type = 0x%x, mps = %d\\n\",\n+\t     dev_addr, ep_num, ep_dir, ep_type, mps);\n+#endif\n+}\n+\n+void dwc_otg_hcd_urb_set_params(dwc_otg_hcd_urb_t * dwc_otg_urb,\n+\t\t\t\tvoid *urb_handle, void *buf, dwc_dma_t dma,\n+\t\t\t\tuint32_t buflen, void *setup_packet,\n+\t\t\t\tdwc_dma_t setup_dma, uint32_t flags,\n+\t\t\t\tuint16_t interval)\n+{\n+\tdwc_otg_urb->priv = urb_handle;\n+\tdwc_otg_urb->buf = buf;\n+\tdwc_otg_urb->dma = dma;\n+\tdwc_otg_urb->length = buflen;\n+\tdwc_otg_urb->setup_packet = setup_packet;\n+\tdwc_otg_urb->setup_dma = setup_dma;\n+\tdwc_otg_urb->flags = flags;\n+\tdwc_otg_urb->interval = interval;\n+\tdwc_otg_urb->status = -DWC_E_IN_PROGRESS;\n+}\n+\n+uint32_t dwc_otg_hcd_urb_get_status(dwc_otg_hcd_urb_t * dwc_otg_urb)\n+{\n+\treturn dwc_otg_urb->status;\n+}\n+\n+uint32_t dwc_otg_hcd_urb_get_actual_length(dwc_otg_hcd_urb_t * dwc_otg_urb)\n+{\n+\treturn dwc_otg_urb->actual_length;\n+}\n+\n+uint32_t dwc_otg_hcd_urb_get_error_count(dwc_otg_hcd_urb_t * dwc_otg_urb)\n+{\n+\treturn dwc_otg_urb->error_count;\n+}\n+\n+void dwc_otg_hcd_urb_set_iso_desc_params(dwc_otg_hcd_urb_t * dwc_otg_urb,\n+\t\t\t\t\t int desc_num, uint32_t offset,\n+\t\t\t\t\t uint32_t length)\n+{\n+\tdwc_otg_urb->iso_descs[desc_num].offset = offset;\n+\tdwc_otg_urb->iso_descs[desc_num].length = length;\n+}\n+\n+uint32_t dwc_otg_hcd_urb_get_iso_desc_status(dwc_otg_hcd_urb_t * dwc_otg_urb,\n+\t\t\t\t\t     int desc_num)\n+{\n+\treturn dwc_otg_urb->iso_descs[desc_num].status;\n+}\n+\n+uint32_t dwc_otg_hcd_urb_get_iso_desc_actual_length(dwc_otg_hcd_urb_t *\n+\t\t\t\t\t\t    dwc_otg_urb, int desc_num)\n+{\n+\treturn dwc_otg_urb->iso_descs[desc_num].actual_length;\n+}\n+\n+int dwc_otg_hcd_is_bandwidth_allocated(dwc_otg_hcd_t * hcd, void *ep_handle)\n+{\n+\tint allocated = 0;\n+\tdwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;\n+\n+\tif (qh) {\n+\t\tif (!DWC_LIST_EMPTY(&qh->qh_list_entry)) {\n+\t\t\tallocated = 1;\n+\t\t}\n+\t}\n+\treturn allocated;\n+}\n+\n+int dwc_otg_hcd_is_bandwidth_freed(dwc_otg_hcd_t * hcd, void *ep_handle)\n+{\n+\tdwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;\n+\tint freed = 0;\n+\tDWC_ASSERT(qh, \"qh is not allocated\\n\");\n+\n+\tif (DWC_LIST_EMPTY(&qh->qh_list_entry)) {\n+\t\tfreed = 1;\n+\t}\n+\n+\treturn freed;\n+}\n+\n+uint8_t dwc_otg_hcd_get_ep_bandwidth(dwc_otg_hcd_t * hcd, void *ep_handle)\n+{\n+\tdwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;\n+\tDWC_ASSERT(qh, \"qh is not allocated\\n\");\n+\treturn qh->usecs;\n+}\n+\n+void dwc_otg_hcd_dump_state(dwc_otg_hcd_t * hcd)\n+{\n+#ifdef DEBUG\n+\tint num_channels;\n+\tint i;\n+\tgnptxsts_data_t np_tx_status;\n+\thptxsts_data_t p_tx_status;\n+\n+\tnum_channels = hcd->core_if->core_params->host_channels;\n+\tDWC_PRINTF(\"\\n\");\n+\tDWC_PRINTF\n+\t    (\"************************************************************\\n\");\n+\tDWC_PRINTF(\"HCD State:\\n\");\n+\tDWC_PRINTF(\"  Num channels: %d\\n\", num_channels);\n+\tfor (i = 0; i < num_channels; i++) {\n+\t\tdwc_hc_t *hc = hcd->hc_ptr_array[i];\n+\t\tDWC_PRINTF(\"  Channel %d:\\n\", i);\n+\t\tDWC_PRINTF(\"    dev_addr: %d, ep_num: %d, ep_is_in: %d\\n\",\n+\t\t\t   hc->dev_addr, hc->ep_num, hc->ep_is_in);\n+\t\tDWC_PRINTF(\"    speed: %d\\n\", hc->speed);\n+\t\tDWC_PRINTF(\"    ep_type: %d\\n\", hc->ep_type);\n+\t\tDWC_PRINTF(\"    max_packet: %d\\n\", hc->max_packet);\n+\t\tDWC_PRINTF(\"    data_pid_start: %d\\n\", hc->data_pid_start);\n+\t\tDWC_PRINTF(\"    multi_count: %d\\n\", hc->multi_count);\n+\t\tDWC_PRINTF(\"    xfer_started: %d\\n\", hc->xfer_started);\n+\t\tDWC_PRINTF(\"    xfer_buff: %p\\n\", hc->xfer_buff);\n+\t\tDWC_PRINTF(\"    xfer_len: %d\\n\", hc->xfer_len);\n+\t\tDWC_PRINTF(\"    xfer_count: %d\\n\", hc->xfer_count);\n+\t\tDWC_PRINTF(\"    halt_on_queue: %d\\n\", hc->halt_on_queue);\n+\t\tDWC_PRINTF(\"    halt_pending: %d\\n\", hc->halt_pending);\n+\t\tDWC_PRINTF(\"    halt_status: %d\\n\", hc->halt_status);\n+\t\tDWC_PRINTF(\"    do_split: %d\\n\", hc->do_split);\n+\t\tDWC_PRINTF(\"    complete_split: %d\\n\", hc->complete_split);\n+\t\tDWC_PRINTF(\"    hub_addr: %d\\n\", hc->hub_addr);\n+\t\tDWC_PRINTF(\"    port_addr: %d\\n\", hc->port_addr);\n+\t\tDWC_PRINTF(\"    xact_pos: %d\\n\", hc->xact_pos);\n+\t\tDWC_PRINTF(\"    requests: %d\\n\", hc->requests);\n+\t\tDWC_PRINTF(\"    qh: %p\\n\", hc->qh);\n+\t\tif (hc->xfer_started) {\n+\t\t\thfnum_data_t hfnum;\n+\t\t\thcchar_data_t hcchar;\n+\t\t\thctsiz_data_t hctsiz;\n+\t\t\thcint_data_t hcint;\n+\t\t\thcintmsk_data_t hcintmsk;\n+\t\t\thfnum.d32 =\n+\t\t\t    DWC_READ_REG32(&hcd->core_if->\n+\t\t\t\t\t   host_if->host_global_regs->hfnum);\n+\t\t\thcchar.d32 =\n+\t\t\t    DWC_READ_REG32(&hcd->core_if->host_if->\n+\t\t\t\t\t   hc_regs[i]->hcchar);\n+\t\t\thctsiz.d32 =\n+\t\t\t    DWC_READ_REG32(&hcd->core_if->host_if->\n+\t\t\t\t\t   hc_regs[i]->hctsiz);\n+\t\t\thcint.d32 =\n+\t\t\t    DWC_READ_REG32(&hcd->core_if->host_if->\n+\t\t\t\t\t   hc_regs[i]->hcint);\n+\t\t\thcintmsk.d32 =\n+\t\t\t    DWC_READ_REG32(&hcd->core_if->host_if->\n+\t\t\t\t\t   hc_regs[i]->hcintmsk);\n+\t\t\tDWC_PRINTF(\"    hfnum: 0x%08x\\n\", hfnum.d32);\n+\t\t\tDWC_PRINTF(\"    hcchar: 0x%08x\\n\", hcchar.d32);\n+\t\t\tDWC_PRINTF(\"    hctsiz: 0x%08x\\n\", hctsiz.d32);\n+\t\t\tDWC_PRINTF(\"    hcint: 0x%08x\\n\", hcint.d32);\n+\t\t\tDWC_PRINTF(\"    hcintmsk: 0x%08x\\n\", hcintmsk.d32);\n+\t\t}\n+\t\tif (hc->xfer_started && hc->qh) {\n+\t\t\tdwc_otg_qtd_t *qtd;\n+\t\t\tdwc_otg_hcd_urb_t *urb;\n+\n+\t\t\tDWC_CIRCLEQ_FOREACH(qtd, &hc->qh->qtd_list, qtd_list_entry) {\n+\t\t\t\tif (!qtd->in_process)\n+\t\t\t\t\tbreak;\n+\n+\t\t\t\turb = qtd->urb;\n+\t\t\tDWC_PRINTF(\"    URB Info:\\n\");\n+\t\t\tDWC_PRINTF(\"      qtd: %p, urb: %p\\n\", qtd, urb);\n+\t\t\tif (urb) {\n+\t\t\t\tDWC_PRINTF(\"      Dev: %d, EP: %d %s\\n\",\n+\t\t\t\t\t   dwc_otg_hcd_get_dev_addr(&urb->\n+\t\t\t\t\t\t\t\t    pipe_info),\n+\t\t\t\t\t   dwc_otg_hcd_get_ep_num(&urb->\n+\t\t\t\t\t\t\t\t  pipe_info),\n+\t\t\t\t\t   dwc_otg_hcd_is_pipe_in(&urb->\n+\t\t\t\t\t\t\t\t  pipe_info) ?\n+\t\t\t\t\t   \"IN\" : \"OUT\");\n+\t\t\t\tDWC_PRINTF(\"      Max packet size: %d\\n\",\n+\t\t\t\t\t   dwc_otg_hcd_get_mps(&urb->\n+\t\t\t\t\t\t\t       pipe_info));\n+\t\t\t\tDWC_PRINTF(\"      transfer_buffer: %p\\n\",\n+\t\t\t\t\t   urb->buf);\n+\t\t\t\tDWC_PRINTF(\"      transfer_dma: %p\\n\",\n+\t\t\t\t\t   (void *)urb->dma);\n+\t\t\t\tDWC_PRINTF(\"      transfer_buffer_length: %d\\n\",\n+\t\t\t\t\t   urb->length);\n+\t\t\t\t\tDWC_PRINTF(\"      actual_length: %d\\n\",\n+\t\t\t\t\t\t   urb->actual_length);\n+\t\t\t\t}\n+\t\t\t}\n+\t\t}\n+\t}\n+\tDWC_PRINTF(\"  non_periodic_channels: %d\\n\", hcd->non_periodic_channels);\n+\tDWC_PRINTF(\"  periodic_channels: %d\\n\", hcd->periodic_channels);\n+\tDWC_PRINTF(\"  periodic_usecs: %d\\n\", hcd->periodic_usecs);\n+\tnp_tx_status.d32 =\n+\t    DWC_READ_REG32(&hcd->core_if->core_global_regs->gnptxsts);\n+\tDWC_PRINTF(\"  NP Tx Req Queue Space Avail: %d\\n\",\n+\t\t   np_tx_status.b.nptxqspcavail);\n+\tDWC_PRINTF(\"  NP Tx FIFO Space Avail: %d\\n\",\n+\t\t   np_tx_status.b.nptxfspcavail);\n+\tp_tx_status.d32 =\n+\t    DWC_READ_REG32(&hcd->core_if->host_if->host_global_regs->hptxsts);\n+\tDWC_PRINTF(\"  P Tx Req Queue Space Avail: %d\\n\",\n+\t\t   p_tx_status.b.ptxqspcavail);\n+\tDWC_PRINTF(\"  P Tx FIFO Space Avail: %d\\n\", p_tx_status.b.ptxfspcavail);\n+\tdwc_otg_hcd_dump_frrem(hcd);\n+\tdwc_otg_dump_global_registers(hcd->core_if);\n+\tdwc_otg_dump_host_registers(hcd->core_if);\n+\tDWC_PRINTF\n+\t    (\"************************************************************\\n\");\n+\tDWC_PRINTF(\"\\n\");\n+#endif\n+}\n+\n+#ifdef DEBUG\n+void dwc_print_setup_data(uint8_t * setup)\n+{\n+\tint i;\n+\tif (CHK_DEBUG_LEVEL(DBG_HCD)) {\n+\t\tDWC_PRINTF(\"Setup Data = MSB \");\n+\t\tfor (i = 7; i >= 0; i--)\n+\t\t\tDWC_PRINTF(\"%02x \", setup[i]);\n+\t\tDWC_PRINTF(\"\\n\");\n+\t\tDWC_PRINTF(\"  bmRequestType Tranfer = %s\\n\",\n+\t\t\t   (setup[0] & 0x80) ? \"Device-to-Host\" :\n+\t\t\t   \"Host-to-Device\");\n+\t\tDWC_PRINTF(\"  bmRequestType Type = \");\n+\t\tswitch ((setup[0] & 0x60) >> 5) {\n+\t\tcase 0:\n+\t\t\tDWC_PRINTF(\"Standard\\n\");\n+\t\t\tbreak;\n+\t\tcase 1:\n+\t\t\tDWC_PRINTF(\"Class\\n\");\n+\t\t\tbreak;\n+\t\tcase 2:\n+\t\t\tDWC_PRINTF(\"Vendor\\n\");\n+\t\t\tbreak;\n+\t\tcase 3:\n+\t\t\tDWC_PRINTF(\"Reserved\\n\");\n+\t\t\tbreak;\n+\t\t}\n+\t\tDWC_PRINTF(\"  bmRequestType Recipient = \");\n+\t\tswitch (setup[0] & 0x1f) {\n+\t\tcase 0:\n+\t\t\tDWC_PRINTF(\"Device\\n\");\n+\t\t\tbreak;\n+\t\tcase 1:\n+\t\t\tDWC_PRINTF(\"Interface\\n\");\n+\t\t\tbreak;\n+\t\tcase 2:\n+\t\t\tDWC_PRINTF(\"Endpoint\\n\");\n+\t\t\tbreak;\n+\t\tcase 3:\n+\t\t\tDWC_PRINTF(\"Other\\n\");\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tDWC_PRINTF(\"Reserved\\n\");\n+\t\t\tbreak;\n+\t\t}\n+\t\tDWC_PRINTF(\"  bRequest = 0x%0x\\n\", setup[1]);\n+\t\tDWC_PRINTF(\"  wValue = 0x%0x\\n\", *((uint16_t *) & setup[2]));\n+\t\tDWC_PRINTF(\"  wIndex = 0x%0x\\n\", *((uint16_t *) & setup[4]));\n+\t\tDWC_PRINTF(\"  wLength = 0x%0x\\n\\n\", *((uint16_t *) & setup[6]));\n+\t}\n+}\n+#endif\n+\n+void dwc_otg_hcd_dump_frrem(dwc_otg_hcd_t * hcd)\n+{\n+#if 0\n+\tDWC_PRINTF(\"Frame remaining at SOF:\\n\");\n+\tDWC_PRINTF(\"  samples %u, accum %llu, avg %llu\\n\",\n+\t\t   hcd->frrem_samples, hcd->frrem_accum,\n+\t\t   (hcd->frrem_samples > 0) ?\n+\t\t   hcd->frrem_accum / hcd->frrem_samples : 0);\n+\n+\tDWC_PRINTF(\"\\n\");\n+\tDWC_PRINTF(\"Frame remaining at start_transfer (uframe 7):\\n\");\n+\tDWC_PRINTF(\"  samples %u, accum %llu, avg %llu\\n\",\n+\t\t   hcd->core_if->hfnum_7_samples,\n+\t\t   hcd->core_if->hfnum_7_frrem_accum,\n+\t\t   (hcd->core_if->hfnum_7_samples >\n+\t\t    0) ? hcd->core_if->hfnum_7_frrem_accum /\n+\t\t   hcd->core_if->hfnum_7_samples : 0);\n+\tDWC_PRINTF(\"Frame remaining at start_transfer (uframe 0):\\n\");\n+\tDWC_PRINTF(\"  samples %u, accum %llu, avg %llu\\n\",\n+\t\t   hcd->core_if->hfnum_0_samples,\n+\t\t   hcd->core_if->hfnum_0_frrem_accum,\n+\t\t   (hcd->core_if->hfnum_0_samples >\n+\t\t    0) ? hcd->core_if->hfnum_0_frrem_accum /\n+\t\t   hcd->core_if->hfnum_0_samples : 0);\n+\tDWC_PRINTF(\"Frame remaining at start_transfer (uframe 1-6):\\n\");\n+\tDWC_PRINTF(\"  samples %u, accum %llu, avg %llu\\n\",\n+\t\t   hcd->core_if->hfnum_other_samples,\n+\t\t   hcd->core_if->hfnum_other_frrem_accum,\n+\t\t   (hcd->core_if->hfnum_other_samples >\n+\t\t    0) ? hcd->core_if->hfnum_other_frrem_accum /\n+\t\t   hcd->core_if->hfnum_other_samples : 0);\n+\n+\tDWC_PRINTF(\"\\n\");\n+\tDWC_PRINTF(\"Frame remaining at sample point A (uframe 7):\\n\");\n+\tDWC_PRINTF(\"  samples %u, accum %llu, avg %llu\\n\",\n+\t\t   hcd->hfnum_7_samples_a, hcd->hfnum_7_frrem_accum_a,\n+\t\t   (hcd->hfnum_7_samples_a > 0) ?\n+\t\t   hcd->hfnum_7_frrem_accum_a / hcd->hfnum_7_samples_a : 0);\n+\tDWC_PRINTF(\"Frame remaining at sample point A (uframe 0):\\n\");\n+\tDWC_PRINTF(\"  samples %u, accum %llu, avg %llu\\n\",\n+\t\t   hcd->hfnum_0_samples_a, hcd->hfnum_0_frrem_accum_a,\n+\t\t   (hcd->hfnum_0_samples_a > 0) ?\n+\t\t   hcd->hfnum_0_frrem_accum_a / hcd->hfnum_0_samples_a : 0);\n+\tDWC_PRINTF(\"Frame remaining at sample point A (uframe 1-6):\\n\");\n+\tDWC_PRINTF(\"  samples %u, accum %llu, avg %llu\\n\",\n+\t\t   hcd->hfnum_other_samples_a, hcd->hfnum_other_frrem_accum_a,\n+\t\t   (hcd->hfnum_other_samples_a > 0) ?\n+\t\t   hcd->hfnum_other_frrem_accum_a /\n+\t\t   hcd->hfnum_other_samples_a : 0);\n+\n+\tDWC_PRINTF(\"\\n\");\n+\tDWC_PRINTF(\"Frame remaining at sample point B (uframe 7):\\n\");\n+\tDWC_PRINTF(\"  samples %u, accum %llu, avg %llu\\n\",\n+\t\t   hcd->hfnum_7_samples_b, hcd->hfnum_7_frrem_accum_b,\n+\t\t   (hcd->hfnum_7_samples_b > 0) ?\n+\t\t   hcd->hfnum_7_frrem_accum_b / hcd->hfnum_7_samples_b : 0);\n+\tDWC_PRINTF(\"Frame remaining at sample point B (uframe 0):\\n\");\n+\tDWC_PRINTF(\"  samples %u, accum %llu, avg %llu\\n\",\n+\t\t   hcd->hfnum_0_samples_b, hcd->hfnum_0_frrem_accum_b,\n+\t\t   (hcd->hfnum_0_samples_b > 0) ?\n+\t\t   hcd->hfnum_0_frrem_accum_b / hcd->hfnum_0_samples_b : 0);\n+\tDWC_PRINTF(\"Frame remaining at sample point B (uframe 1-6):\\n\");\n+\tDWC_PRINTF(\"  samples %u, accum %llu, avg %llu\\n\",\n+\t\t   hcd->hfnum_other_samples_b, hcd->hfnum_other_frrem_accum_b,\n+\t\t   (hcd->hfnum_other_samples_b > 0) ?\n+\t\t   hcd->hfnum_other_frrem_accum_b /\n+\t\t   hcd->hfnum_other_samples_b : 0);\n+#endif\n+}\n+\n+#endif /* DWC_DEVICE_ONLY */\n--- /dev/null\n+++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd.h\n@@ -0,0 +1,870 @@\n+/* ==========================================================================\n+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd.h $\n+ * $Revision: #58 $\n+ * $Date: 2011/09/15 $\n+ * $Change: 1846647 $\n+ *\n+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,\n+ * \"Software\") is an Unsupported proprietary work of Synopsys, Inc. unless\n+ * otherwise expressly agreed to in writing between Synopsys and you.\n+ *\n+ * The Software IS NOT an item of Licensed Software or Licensed Product under\n+ * any End User Software License Agreement or Agreement for Licensed Product\n+ * with Synopsys or any supplement thereto. You are permitted to use and\n+ * redistribute this Software in source and binary forms, with or without\n+ * modification, provided that redistributions of source code must retain this\n+ * notice. You may not view, use, disclose, copy or distribute this file or\n+ * any information contained herein except pursuant to this license grant from\n+ * Synopsys. If you do not agree with this notice, including the disclaimer\n+ * below, then you are not authorized to use the Software.\n+ *\n+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN \"AS IS\" BASIS\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,\n+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH\n+ * DAMAGE.\n+ * ========================================================================== */\n+#ifndef DWC_DEVICE_ONLY\n+#ifndef __DWC_HCD_H__\n+#define __DWC_HCD_H__\n+\n+#include \"dwc_otg_os_dep.h\"\n+#include \"usb.h\"\n+#include \"dwc_otg_hcd_if.h\"\n+#include \"dwc_otg_core_if.h\"\n+#include \"dwc_list.h\"\n+#include \"dwc_otg_cil.h\"\n+#include \"dwc_otg_fiq_fsm.h\"\n+#include \"dwc_otg_driver.h\"\n+\n+\n+/**\n+ * @file\n+ *\n+ * This file contains the structures, constants, and interfaces for\n+ * the Host Contoller Driver (HCD).\n+ *\n+ * The Host Controller Driver (HCD) is responsible for translating requests\n+ * from the USB Driver into the appropriate actions on the DWC_otg controller.\n+ * It isolates the USBD from the specifics of the controller by providing an\n+ * API to the USBD.\n+ */\n+\n+struct dwc_otg_hcd_pipe_info {\n+\tuint8_t dev_addr;\n+\tuint8_t ep_num;\n+\tuint8_t pipe_type;\n+\tuint8_t pipe_dir;\n+\tuint16_t mps;\n+};\n+\n+struct dwc_otg_hcd_iso_packet_desc {\n+\tuint32_t offset;\n+\tuint32_t length;\n+\tuint32_t actual_length;\n+\tuint32_t status;\n+};\n+\n+struct dwc_otg_qtd;\n+\n+struct dwc_otg_hcd_urb {\n+\tvoid *priv;\n+\tstruct dwc_otg_qtd *qtd;\n+\tvoid *buf;\n+\tdwc_dma_t dma;\n+\tvoid *setup_packet;\n+\tdwc_dma_t setup_dma;\n+\tuint32_t length;\n+\tuint32_t actual_length;\n+\tuint32_t status;\n+\tuint32_t error_count;\n+\tuint32_t packet_count;\n+\tuint32_t flags;\n+\tuint16_t interval;\n+\tstruct dwc_otg_hcd_pipe_info pipe_info;\n+\tstruct dwc_otg_hcd_iso_packet_desc iso_descs[0];\n+};\n+\n+static inline uint8_t dwc_otg_hcd_get_ep_num(struct dwc_otg_hcd_pipe_info *pipe)\n+{\n+\treturn pipe->ep_num;\n+}\n+\n+static inline uint8_t dwc_otg_hcd_get_pipe_type(struct dwc_otg_hcd_pipe_info\n+\t\t\t\t\t\t*pipe)\n+{\n+\treturn pipe->pipe_type;\n+}\n+\n+static inline uint16_t dwc_otg_hcd_get_mps(struct dwc_otg_hcd_pipe_info *pipe)\n+{\n+\treturn pipe->mps;\n+}\n+\n+static inline uint8_t dwc_otg_hcd_get_dev_addr(struct dwc_otg_hcd_pipe_info\n+\t\t\t\t\t       *pipe)\n+{\n+\treturn pipe->dev_addr;\n+}\n+\n+static inline uint8_t dwc_otg_hcd_is_pipe_isoc(struct dwc_otg_hcd_pipe_info\n+\t\t\t\t\t       *pipe)\n+{\n+\treturn (pipe->pipe_type == UE_ISOCHRONOUS);\n+}\n+\n+static inline uint8_t dwc_otg_hcd_is_pipe_int(struct dwc_otg_hcd_pipe_info\n+\t\t\t\t\t      *pipe)\n+{\n+\treturn (pipe->pipe_type == UE_INTERRUPT);\n+}\n+\n+static inline uint8_t dwc_otg_hcd_is_pipe_bulk(struct dwc_otg_hcd_pipe_info\n+\t\t\t\t\t       *pipe)\n+{\n+\treturn (pipe->pipe_type == UE_BULK);\n+}\n+\n+static inline uint8_t dwc_otg_hcd_is_pipe_control(struct dwc_otg_hcd_pipe_info\n+\t\t\t\t\t\t  *pipe)\n+{\n+\treturn (pipe->pipe_type == UE_CONTROL);\n+}\n+\n+static inline uint8_t dwc_otg_hcd_is_pipe_in(struct dwc_otg_hcd_pipe_info *pipe)\n+{\n+\treturn (pipe->pipe_dir == UE_DIR_IN);\n+}\n+\n+static inline uint8_t dwc_otg_hcd_is_pipe_out(struct dwc_otg_hcd_pipe_info\n+\t\t\t\t\t      *pipe)\n+{\n+\treturn (!dwc_otg_hcd_is_pipe_in(pipe));\n+}\n+\n+static inline void dwc_otg_hcd_fill_pipe(struct dwc_otg_hcd_pipe_info *pipe,\n+\t\t\t\t\t uint8_t devaddr, uint8_t ep_num,\n+\t\t\t\t\t uint8_t pipe_type, uint8_t pipe_dir,\n+\t\t\t\t\t uint16_t mps)\n+{\n+\tpipe->dev_addr = devaddr;\n+\tpipe->ep_num = ep_num;\n+\tpipe->pipe_type = pipe_type;\n+\tpipe->pipe_dir = pipe_dir;\n+\tpipe->mps = mps;\n+}\n+\n+/**\n+ * Phases for control transfers.\n+ */\n+typedef enum dwc_otg_control_phase {\n+\tDWC_OTG_CONTROL_SETUP,\n+\tDWC_OTG_CONTROL_DATA,\n+\tDWC_OTG_CONTROL_STATUS\n+} dwc_otg_control_phase_e;\n+\n+/** Transaction types. */\n+typedef enum dwc_otg_transaction_type {\n+\tDWC_OTG_TRANSACTION_NONE          = 0,\n+\tDWC_OTG_TRANSACTION_PERIODIC      = 1,\n+\tDWC_OTG_TRANSACTION_NON_PERIODIC  = 2,\n+\tDWC_OTG_TRANSACTION_ALL           = DWC_OTG_TRANSACTION_PERIODIC + DWC_OTG_TRANSACTION_NON_PERIODIC\n+} dwc_otg_transaction_type_e;\n+\n+struct dwc_otg_qh;\n+\n+/**\n+ * A Queue Transfer Descriptor (QTD) holds the state of a bulk, control,\n+ * interrupt, or isochronous transfer. A single QTD is created for each URB\n+ * (of one of these types) submitted to the HCD. The transfer associated with\n+ * a QTD may require one or multiple transactions.\n+ *\n+ * A QTD is linked to a Queue Head, which is entered in either the\n+ * non-periodic or periodic schedule for execution. When a QTD is chosen for\n+ * execution, some or all of its transactions may be executed. After\n+ * execution, the state of the QTD is updated. The QTD may be retired if all\n+ * its transactions are complete or if an error occurred. Otherwise, it\n+ * remains in the schedule so more transactions can be executed later.\n+ */\n+typedef struct dwc_otg_qtd {\n+\t/**\n+\t * Determines the PID of the next data packet for the data phase of\n+\t * control transfers. Ignored for other transfer types.<br>\n+\t * One of the following values:\n+\t *\t- DWC_OTG_HC_PID_DATA0\n+\t *\t- DWC_OTG_HC_PID_DATA1\n+\t */\n+\tuint8_t data_toggle;\n+\n+\t/** Current phase for control transfers (Setup, Data, or Status). */\n+\tdwc_otg_control_phase_e control_phase;\n+\n+\t/** Keep track of the current split type\n+\t * for FS/LS endpoints on a HS Hub */\n+\tuint8_t complete_split;\n+\n+\t/** How many bytes transferred during SSPLIT OUT */\n+\tuint32_t ssplit_out_xfer_count;\n+\n+\t/**\n+\t * Holds the number of bus errors that have occurred for a transaction\n+\t * within this transfer.\n+\t */\n+\tuint8_t error_count;\n+\n+\t/**\n+\t * Index of the next frame descriptor for an isochronous transfer. A\n+\t * frame descriptor describes the buffer position and length of the\n+\t * data to be transferred in the next scheduled (micro)frame of an\n+\t * isochronous transfer. It also holds status for that transaction.\n+\t * The frame index starts at 0.\n+\t */\n+\tuint16_t isoc_frame_index;\n+\n+\t/** Position of the ISOC split on full/low speed */\n+\tuint8_t isoc_split_pos;\n+\n+\t/** Position of the ISOC split in the buffer for the current frame */\n+\tuint16_t isoc_split_offset;\n+\n+\t/** URB for this transfer */\n+\tstruct dwc_otg_hcd_urb *urb;\n+\n+\tstruct dwc_otg_qh *qh;\n+\n+\t/** This list of QTDs */\n+\t DWC_CIRCLEQ_ENTRY(dwc_otg_qtd) qtd_list_entry;\n+\n+\t/** Indicates if this QTD is currently processed by HW. */\n+\tuint8_t in_process;\n+\n+\t/** Number of DMA descriptors for this QTD */\n+\tuint8_t n_desc;\n+\n+\t/**\n+\t * Last activated frame(packet) index.\n+\t * Used in Descriptor DMA mode only.\n+\t */\n+\tuint16_t isoc_frame_index_last;\n+\n+} dwc_otg_qtd_t;\n+\n+DWC_CIRCLEQ_HEAD(dwc_otg_qtd_list, dwc_otg_qtd);\n+\n+/**\n+ * A Queue Head (QH) holds the static characteristics of an endpoint and\n+ * maintains a list of transfers (QTDs) for that endpoint. A QH structure may\n+ * be entered in either the non-periodic or periodic schedule.\n+ */\n+typedef struct dwc_otg_qh {\n+\t/**\n+\t * Endpoint type.\n+\t * One of the following values:\n+\t *\t- UE_CONTROL\n+\t *\t- UE_BULK\n+\t *\t- UE_INTERRUPT\n+\t *\t- UE_ISOCHRONOUS\n+\t */\n+\tuint8_t ep_type;\n+\tuint8_t ep_is_in;\n+\n+\t/** wMaxPacketSize Field of Endpoint Descriptor. */\n+\tuint16_t maxp;\n+\n+\t/**\n+\t * Device speed.\n+\t * One of the following values:\n+\t *\t- DWC_OTG_EP_SPEED_LOW\n+\t *\t- DWC_OTG_EP_SPEED_FULL\n+\t *\t- DWC_OTG_EP_SPEED_HIGH\n+\t */\n+\tuint8_t dev_speed;\n+\n+\t/**\n+\t * Determines the PID of the next data packet for non-control\n+\t * transfers. Ignored for control transfers.<br>\n+\t * One of the following values:\n+\t *\t- DWC_OTG_HC_PID_DATA0\n+\t *\t- DWC_OTG_HC_PID_DATA1\n+\t */\n+\tuint8_t data_toggle;\n+\n+\t/** Ping state if 1. */\n+\tuint8_t ping_state;\n+\n+\t/**\n+\t * List of QTDs for this QH.\n+\t */\n+\tstruct dwc_otg_qtd_list qtd_list;\n+\n+\t/** Host channel currently processing transfers for this QH. */\n+\tstruct dwc_hc *channel;\n+\n+\t/** Full/low speed endpoint on high-speed hub requires split. */\n+\tuint8_t do_split;\n+\n+\t/** @name Periodic schedule information */\n+\t/** @{ */\n+\n+\t/** Bandwidth in microseconds per (micro)frame. */\n+\tuint16_t usecs;\n+\n+\t/** Interval between transfers in (micro)frames. */\n+\tuint16_t interval;\n+\n+\t/**\n+\t * (micro)frame to initialize a periodic transfer. The transfer\n+\t * executes in the following (micro)frame.\n+\t */\n+\tuint16_t sched_frame;\n+\n+\t/*\n+\t** Frame a NAK was received on this queue head, used to minimise NAK retransmission\n+\t*/\n+\tuint16_t nak_frame;\n+\n+\t/** (micro)frame at which last start split was initialized. */\n+\tuint16_t start_split_frame;\n+\n+\t/** @} */\n+\n+\t/**\n+\t * Used instead of original buffer if\n+\t * it(physical address) is not dword-aligned.\n+\t */\n+\tuint8_t *dw_align_buf;\n+\tdwc_dma_t dw_align_buf_dma;\n+\n+\t/** Entry for QH in either the periodic or non-periodic schedule. */\n+\tdwc_list_link_t qh_list_entry;\n+\n+\t/** @name Descriptor DMA support */\n+\t/** @{ */\n+\n+\t/** Descriptor List. */\n+\tdwc_otg_host_dma_desc_t *desc_list;\n+\n+\t/** Descriptor List physical address. */\n+\tdwc_dma_t desc_list_dma;\n+\n+\t/**\n+\t * Xfer Bytes array.\n+\t * Each element corresponds to a descriptor and indicates\n+\t * original XferSize size value for the descriptor.\n+\t */\n+\tuint32_t *n_bytes;\n+\n+\t/** Actual number of transfer descriptors in a list. */\n+\tuint16_t ntd;\n+\n+\t/** First activated isochronous transfer descriptor index. */\n+\tuint8_t td_first;\n+\t/** Last activated isochronous transfer descriptor index. */\n+\tuint8_t td_last;\n+\n+\t/** @} */\n+\n+\n+\tuint16_t speed;\n+\tuint16_t frame_usecs[8];\n+\n+\tuint32_t skip_count;\n+} dwc_otg_qh_t;\n+\n+DWC_CIRCLEQ_HEAD(hc_list, dwc_hc);\n+\n+typedef struct urb_tq_entry {\n+\tstruct urb *urb;\n+\tDWC_TAILQ_ENTRY(urb_tq_entry) urb_tq_entries;\n+} urb_tq_entry_t;\n+\n+DWC_TAILQ_HEAD(urb_list, urb_tq_entry);\n+\n+/**\n+ * This structure holds the state of the HCD, including the non-periodic and\n+ * periodic schedules.\n+ */\n+struct dwc_otg_hcd {\n+\t/** The DWC otg device pointer */\n+\tstruct dwc_otg_device *otg_dev;\n+\t/** DWC OTG Core Interface Layer */\n+\tdwc_otg_core_if_t *core_if;\n+\n+\t/** Function HCD driver callbacks */\n+\tstruct dwc_otg_hcd_function_ops *fops;\n+\n+\t/** Internal DWC HCD Flags */\n+\tvolatile union dwc_otg_hcd_internal_flags {\n+\t\tuint32_t d32;\n+\t\tstruct {\n+\t\t\tunsigned port_connect_status_change:1;\n+\t\t\tunsigned port_connect_status:1;\n+\t\t\tunsigned port_reset_change:1;\n+\t\t\tunsigned port_enable_change:1;\n+\t\t\tunsigned port_suspend_change:1;\n+\t\t\tunsigned port_over_current_change:1;\n+\t\t\tunsigned port_l1_change:1;\n+\t\t\tunsigned port_speed:2;\n+\t\t\tunsigned reserved:24;\n+\t\t} b;\n+\t} flags;\n+\n+\t/**\n+\t * Inactive items in the non-periodic schedule. This is a list of\n+\t * Queue Heads. Transfers associated with these Queue Heads are not\n+\t * currently assigned to a host channel.\n+\t */\n+\tdwc_list_link_t non_periodic_sched_inactive;\n+\n+\t/**\n+\t * Active items in the non-periodic schedule. This is a list of\n+\t * Queue Heads. Transfers associated with these Queue Heads are\n+\t * currently assigned to a host channel.\n+\t */\n+\tdwc_list_link_t non_periodic_sched_active;\n+\n+\t/**\n+\t * Pointer to the next Queue Head to process in the active\n+\t * non-periodic schedule.\n+\t */\n+\tdwc_list_link_t *non_periodic_qh_ptr;\n+\n+\t/**\n+\t * Inactive items in the periodic schedule. This is a list of QHs for\n+\t * periodic transfers that are _not_ scheduled for the next frame.\n+\t * Each QH in the list has an interval counter that determines when it\n+\t * needs to be scheduled for execution. This scheduling mechanism\n+\t * allows only a simple calculation for periodic bandwidth used (i.e.\n+\t * must assume that all periodic transfers may need to execute in the\n+\t * same frame). However, it greatly simplifies scheduling and should\n+\t * be sufficient for the vast majority of OTG hosts, which need to\n+\t * connect to a small number of peripherals at one time.\n+\t *\n+\t * Items move from this list to periodic_sched_ready when the QH\n+\t * interval counter is 0 at SOF.\n+\t */\n+\tdwc_list_link_t periodic_sched_inactive;\n+\n+\t/**\n+\t * List of periodic QHs that are ready for execution in the next\n+\t * frame, but have not yet been assigned to host channels.\n+\t *\n+\t * Items move from this list to periodic_sched_assigned as host\n+\t * channels become available during the current frame.\n+\t */\n+\tdwc_list_link_t periodic_sched_ready;\n+\n+\t/**\n+\t * List of periodic QHs to be executed in the next frame that are\n+\t * assigned to host channels.\n+\t *\n+\t * Items move from this list to periodic_sched_queued as the\n+\t * transactions for the QH are queued to the DWC_otg controller.\n+\t */\n+\tdwc_list_link_t periodic_sched_assigned;\n+\n+\t/**\n+\t * List of periodic QHs that have been queued for execution.\n+\t *\n+\t * Items move from this list to either periodic_sched_inactive or\n+\t * periodic_sched_ready when the channel associated with the transfer\n+\t * is released. If the interval for the QH is 1, the item moves to\n+\t * periodic_sched_ready because it must be rescheduled for the next\n+\t * frame. Otherwise, the item moves to periodic_sched_inactive.\n+\t */\n+\tdwc_list_link_t periodic_sched_queued;\n+\n+\t/**\n+\t * Total bandwidth claimed so far for periodic transfers. This value\n+\t * is in microseconds per (micro)frame. The assumption is that all\n+\t * periodic transfers may occur in the same (micro)frame.\n+\t */\n+\tuint16_t periodic_usecs;\n+\n+\t/**\n+\t * Total bandwidth claimed so far for all periodic transfers\n+\t * in a frame.\n+\t * This will include a mixture of HS and FS transfers.\n+\t * Units are microseconds per (micro)frame.\n+\t * We have a budget per frame and have to schedule\n+\t * transactions accordingly.\n+\t * Watch out for the fact that things are actually scheduled for the\n+\t * \"next frame\".\n+\t */\n+\tuint16_t                frame_usecs[8];\n+\n+\n+\t/**\n+\t * Frame number read from the core at SOF. The value ranges from 0 to\n+\t * DWC_HFNUM_MAX_FRNUM.\n+\t */\n+\tuint16_t frame_number;\n+\n+\t/**\n+\t * Count of periodic QHs, if using several eps. For SOF enable/disable.\n+\t */\n+\tuint16_t periodic_qh_count;\n+\n+\t/**\n+\t * Free host channels in the controller. This is a list of\n+\t * dwc_hc_t items.\n+\t */\n+\tstruct hc_list free_hc_list;\n+\t/**\n+\t * Number of host channels assigned to periodic transfers. Currently\n+\t * assuming that there is a dedicated host channel for each periodic\n+\t * transaction and at least one host channel available for\n+\t * non-periodic transactions.\n+\t */\n+\tint periodic_channels; /* microframe_schedule==0 */\n+\n+\t/**\n+\t * Number of host channels assigned to non-periodic transfers.\n+\t */\n+\tint non_periodic_channels; /* microframe_schedule==0 */\n+\n+\t/**\n+\t * Number of host channels assigned to non-periodic transfers.\n+\t */\n+\tint available_host_channels;\n+\n+\t/**\n+\t * Array of pointers to the host channel descriptors. Allows accessing\n+\t * a host channel descriptor given the host channel number. This is\n+\t * useful in interrupt handlers.\n+\t */\n+\tstruct dwc_hc *hc_ptr_array[MAX_EPS_CHANNELS];\n+\n+\t/**\n+\t * Buffer to use for any data received during the status phase of a\n+\t * control transfer. Normally no data is transferred during the status\n+\t * phase. This buffer is used as a bit bucket.\n+\t */\n+\tuint8_t *status_buf;\n+\n+\t/**\n+\t * DMA address for status_buf.\n+\t */\n+\tdma_addr_t status_buf_dma;\n+#define DWC_OTG_HCD_STATUS_BUF_SIZE 64\n+\n+\t/**\n+\t * Connection timer. An OTG host must display a message if the device\n+\t * does not connect. Started when the VBus power is turned on via\n+\t * sysfs attribute \"buspower\".\n+\t */\n+\tdwc_timer_t *conn_timer;\n+\n+\t/* Tasket to do a reset */\n+\tdwc_tasklet_t *reset_tasklet;\n+\n+\tdwc_tasklet_t *completion_tasklet;\n+\tstruct urb_list completed_urb_list;\n+\n+\t/*  */\n+\tdwc_spinlock_t *lock;\n+\t/**\n+\t * Private data that could be used by OS wrapper.\n+\t */\n+\tvoid *priv;\n+\n+\tuint8_t otg_port;\n+\n+\t/** Frame List */\n+\tuint32_t *frame_list;\n+\n+\t/** Hub - Port assignment */\n+\tint hub_port[128];\n+#ifdef FIQ_DEBUG\n+\tint hub_port_alloc[2048];\n+#endif\n+\n+\t/** Frame List DMA address */\n+\tdma_addr_t frame_list_dma;\n+\n+\tstruct fiq_stack *fiq_stack;\n+\tstruct fiq_state *fiq_state;\n+\n+\t/** Virtual address for split transaction DMA bounce buffers */\n+\tstruct fiq_dma_blob *fiq_dmab;\n+\n+#ifdef DEBUG\n+\tuint32_t frrem_samples;\n+\tuint64_t frrem_accum;\n+\n+\tuint32_t hfnum_7_samples_a;\n+\tuint64_t hfnum_7_frrem_accum_a;\n+\tuint32_t hfnum_0_samples_a;\n+\tuint64_t hfnum_0_frrem_accum_a;\n+\tuint32_t hfnum_other_samples_a;\n+\tuint64_t hfnum_other_frrem_accum_a;\n+\n+\tuint32_t hfnum_7_samples_b;\n+\tuint64_t hfnum_7_frrem_accum_b;\n+\tuint32_t hfnum_0_samples_b;\n+\tuint64_t hfnum_0_frrem_accum_b;\n+\tuint32_t hfnum_other_samples_b;\n+\tuint64_t hfnum_other_frrem_accum_b;\n+#endif\n+};\n+\n+static inline struct device *dwc_otg_hcd_to_dev(struct dwc_otg_hcd *hcd)\n+{\n+\treturn &hcd->otg_dev->os_dep.platformdev->dev;\n+}\n+\n+/** @name Transaction Execution Functions */\n+/** @{ */\n+extern dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t\n+\t\t\t\t\t\t\t\t  * hcd);\n+extern void dwc_otg_hcd_queue_transactions(dwc_otg_hcd_t * hcd,\n+\t\t\t\t\t   dwc_otg_transaction_type_e tr_type);\n+\n+int dwc_otg_hcd_allocate_port(dwc_otg_hcd_t * hcd, dwc_otg_qh_t *qh);\n+void dwc_otg_hcd_release_port(dwc_otg_hcd_t * dwc_otg_hcd, dwc_otg_qh_t *qh);\n+\n+extern int fiq_fsm_queue_transaction(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh);\n+extern int fiq_fsm_transaction_suitable(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh);\n+extern void dwc_otg_cleanup_fiq_channel(dwc_otg_hcd_t *hcd, uint32_t num);\n+\n+/** @} */\n+\n+/** @name Interrupt Handler Functions */\n+/** @{ */\n+extern int32_t dwc_otg_hcd_handle_intr(dwc_otg_hcd_t * dwc_otg_hcd);\n+extern int32_t dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd_t * dwc_otg_hcd);\n+extern int32_t dwc_otg_hcd_handle_rx_status_q_level_intr(dwc_otg_hcd_t *\n+\t\t\t\t\t\t\t dwc_otg_hcd);\n+extern int32_t dwc_otg_hcd_handle_np_tx_fifo_empty_intr(dwc_otg_hcd_t *\n+\t\t\t\t\t\t\tdwc_otg_hcd);\n+extern int32_t dwc_otg_hcd_handle_perio_tx_fifo_empty_intr(dwc_otg_hcd_t *\n+\t\t\t\t\t\t\t   dwc_otg_hcd);\n+extern int32_t dwc_otg_hcd_handle_incomplete_periodic_intr(dwc_otg_hcd_t *\n+\t\t\t\t\t\t\t   dwc_otg_hcd);\n+extern int32_t dwc_otg_hcd_handle_port_intr(dwc_otg_hcd_t * dwc_otg_hcd);\n+extern int32_t dwc_otg_hcd_handle_conn_id_status_change_intr(dwc_otg_hcd_t *\n+\t\t\t\t\t\t\t     dwc_otg_hcd);\n+extern int32_t dwc_otg_hcd_handle_disconnect_intr(dwc_otg_hcd_t * dwc_otg_hcd);\n+extern int32_t dwc_otg_hcd_handle_hc_intr(dwc_otg_hcd_t * dwc_otg_hcd);\n+extern int32_t dwc_otg_hcd_handle_hc_n_intr(dwc_otg_hcd_t * dwc_otg_hcd,\n+\t\t\t\t\t    uint32_t num);\n+extern int32_t dwc_otg_hcd_handle_session_req_intr(dwc_otg_hcd_t * dwc_otg_hcd);\n+extern int32_t dwc_otg_hcd_handle_wakeup_detected_intr(dwc_otg_hcd_t *\n+\t\t\t\t\t\t       dwc_otg_hcd);\n+/** @} */\n+\n+/** @name Schedule Queue Functions */\n+/** @{ */\n+\n+/* Implemented in dwc_otg_hcd_queue.c */\n+extern dwc_otg_qh_t *dwc_otg_hcd_qh_create(dwc_otg_hcd_t * hcd,\n+\t\t\t\t\t   dwc_otg_hcd_urb_t * urb, int atomic_alloc);\n+extern void dwc_otg_hcd_qh_free(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh);\n+extern int dwc_otg_hcd_qh_add(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh);\n+extern void dwc_otg_hcd_qh_remove(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh);\n+extern void dwc_otg_hcd_qh_deactivate(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh,\n+\t\t\t\t      int sched_csplit);\n+\n+/** Remove and free a QH */\n+static inline void dwc_otg_hcd_qh_remove_and_free(dwc_otg_hcd_t * hcd,\n+\t\t\t\t\t\t  dwc_otg_qh_t * qh)\n+{\n+\tdwc_irqflags_t flags;\n+\tDWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);\n+\tdwc_otg_hcd_qh_remove(hcd, qh);\n+\tDWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);\n+\tdwc_otg_hcd_qh_free(hcd, qh);\n+}\n+\n+/** Allocates memory for a QH structure.\n+ * @return Returns the memory allocate or NULL on error. */\n+static inline dwc_otg_qh_t *dwc_otg_hcd_qh_alloc(int atomic_alloc)\n+{\n+\tif (atomic_alloc)\n+\t\treturn (dwc_otg_qh_t *) DWC_ALLOC_ATOMIC(sizeof(dwc_otg_qh_t));\n+\telse\n+\t\treturn (dwc_otg_qh_t *) DWC_ALLOC(sizeof(dwc_otg_qh_t));\n+}\n+\n+extern dwc_otg_qtd_t *dwc_otg_hcd_qtd_create(dwc_otg_hcd_urb_t * urb,\n+\t\t\t\t\t     int atomic_alloc);\n+extern void dwc_otg_hcd_qtd_init(dwc_otg_qtd_t * qtd, dwc_otg_hcd_urb_t * urb);\n+extern int dwc_otg_hcd_qtd_add(dwc_otg_qtd_t * qtd, dwc_otg_hcd_t * dwc_otg_hcd,\n+\t\t\t       dwc_otg_qh_t ** qh, int atomic_alloc);\n+\n+/** Allocates memory for a QTD structure.\n+ * @return Returns the memory allocate or NULL on error. */\n+static inline dwc_otg_qtd_t *dwc_otg_hcd_qtd_alloc(int atomic_alloc)\n+{\n+\tif (atomic_alloc)\n+\t\treturn (dwc_otg_qtd_t *) DWC_ALLOC_ATOMIC(sizeof(dwc_otg_qtd_t));\n+\telse\n+\t\treturn (dwc_otg_qtd_t *) DWC_ALLOC(sizeof(dwc_otg_qtd_t));\n+}\n+\n+/** Frees the memory for a QTD structure.  QTD should already be removed from\n+ * list.\n+ * @param qtd QTD to free.*/\n+static inline void dwc_otg_hcd_qtd_free(dwc_otg_qtd_t * qtd)\n+{\n+\tDWC_FREE(qtd);\n+}\n+\n+/** Removes a QTD from list.\n+ * @param hcd HCD instance.\n+ * @param qtd QTD to remove from list.\n+ * @param qh QTD belongs to.\n+ */\n+static inline void dwc_otg_hcd_qtd_remove(dwc_otg_hcd_t * hcd,\n+\t\t\t\t\t  dwc_otg_qtd_t * qtd,\n+\t\t\t\t\t  dwc_otg_qh_t * qh)\n+{\n+\tDWC_CIRCLEQ_REMOVE(&qh->qtd_list, qtd, qtd_list_entry);\n+}\n+\n+/** Remove and free a QTD\n+  * Need to disable IRQ and hold hcd lock while calling this function out of\n+  * interrupt servicing chain */\n+static inline void dwc_otg_hcd_qtd_remove_and_free(dwc_otg_hcd_t * hcd,\n+\t\t\t\t\t\t   dwc_otg_qtd_t * qtd,\n+\t\t\t\t\t\t   dwc_otg_qh_t * qh)\n+{\n+\tdwc_otg_hcd_qtd_remove(hcd, qtd, qh);\n+\tdwc_otg_hcd_qtd_free(qtd);\n+}\n+\n+/** @} */\n+\n+/** @name Descriptor DMA Supporting Functions */\n+/** @{ */\n+\n+extern void dwc_otg_hcd_start_xfer_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh);\n+extern void dwc_otg_hcd_complete_xfer_ddma(dwc_otg_hcd_t * hcd,\n+\t\t\t\t\t   dwc_hc_t * hc,\n+\t\t\t\t\t   dwc_otg_hc_regs_t * hc_regs,\n+\t\t\t\t\t   dwc_otg_halt_status_e halt_status);\n+\n+extern int dwc_otg_hcd_qh_init_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh);\n+extern void dwc_otg_hcd_qh_free_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh);\n+\n+/** @} */\n+\n+/** @name Internal Functions */\n+/** @{ */\n+dwc_otg_qh_t *dwc_urb_to_qh(dwc_otg_hcd_urb_t * urb);\n+/** @} */\n+\n+#ifdef CONFIG_USB_DWC_OTG_LPM\n+extern int dwc_otg_hcd_get_hc_for_lpm_tran(dwc_otg_hcd_t * hcd,\n+\t\t\t\t\t   uint8_t devaddr);\n+extern void dwc_otg_hcd_free_hc_from_lpm(dwc_otg_hcd_t * hcd);\n+#endif\n+\n+/** Gets the QH that contains the list_head */\n+#define dwc_list_to_qh(_list_head_ptr_) container_of(_list_head_ptr_, dwc_otg_qh_t, qh_list_entry)\n+\n+/** Gets the QTD that contains the list_head */\n+#define dwc_list_to_qtd(_list_head_ptr_) container_of(_list_head_ptr_, dwc_otg_qtd_t, qtd_list_entry)\n+\n+/** Check if QH is non-periodic  */\n+#define dwc_qh_is_non_per(_qh_ptr_) ((_qh_ptr_->ep_type == UE_BULK) || \\\n+\t\t\t\t     (_qh_ptr_->ep_type == UE_CONTROL))\n+\n+/** High bandwidth multiplier as encoded in highspeed endpoint descriptors */\n+#define dwc_hb_mult(wMaxPacketSize) (1 + (((wMaxPacketSize) >> 11) & 0x03))\n+\n+/** Packet size for any kind of endpoint descriptor */\n+#define dwc_max_packet(wMaxPacketSize) ((wMaxPacketSize) & 0x07ff)\n+\n+/**\n+ * Returns true if _frame1 is less than or equal to _frame2. The comparison is\n+ * done modulo DWC_HFNUM_MAX_FRNUM. This accounts for the rollover of the\n+ * frame number when the max frame number is reached.\n+ */\n+static inline int dwc_frame_num_le(uint16_t frame1, uint16_t frame2)\n+{\n+\treturn ((frame2 - frame1) & DWC_HFNUM_MAX_FRNUM) <=\n+\t    (DWC_HFNUM_MAX_FRNUM >> 1);\n+}\n+\n+/**\n+ * Returns true if _frame1 is greater than _frame2. The comparison is done\n+ * modulo DWC_HFNUM_MAX_FRNUM. This accounts for the rollover of the frame\n+ * number when the max frame number is reached.\n+ */\n+static inline int dwc_frame_num_gt(uint16_t frame1, uint16_t frame2)\n+{\n+\treturn (frame1 != frame2) &&\n+\t    (((frame1 - frame2) & DWC_HFNUM_MAX_FRNUM) <\n+\t     (DWC_HFNUM_MAX_FRNUM >> 1));\n+}\n+\n+/**\n+ * Increments _frame by the amount specified by _inc. The addition is done\n+ * modulo DWC_HFNUM_MAX_FRNUM. Returns the incremented value.\n+ */\n+static inline uint16_t dwc_frame_num_inc(uint16_t frame, uint16_t inc)\n+{\n+\treturn (frame + inc) & DWC_HFNUM_MAX_FRNUM;\n+}\n+\n+static inline uint16_t dwc_full_frame_num(uint16_t frame)\n+{\n+\treturn (frame & DWC_HFNUM_MAX_FRNUM) >> 3;\n+}\n+\n+static inline uint16_t dwc_micro_frame_num(uint16_t frame)\n+{\n+\treturn frame & 0x7;\n+}\n+\n+extern void init_hcd_usecs(dwc_otg_hcd_t *_hcd);\n+\n+void dwc_otg_hcd_save_data_toggle(dwc_hc_t * hc,\n+\t\t\t\t  dwc_otg_hc_regs_t * hc_regs,\n+\t\t\t\t  dwc_otg_qtd_t * qtd);\n+\n+#ifdef DEBUG\n+/**\n+ * Macro to sample the remaining PHY clocks left in the current frame. This\n+ * may be used during debugging to determine the average time it takes to\n+ * execute sections of code. There are two possible sample points, \"a\" and\n+ * \"b\", so the _letter argument must be one of these values.\n+ *\n+ * To dump the average sample times, read the \"hcd_frrem\" sysfs attribute. For\n+ * example, \"cat /sys/devices/lm0/hcd_frrem\".\n+ */\n+#define dwc_sample_frrem(_hcd, _qh, _letter) \\\n+{ \\\n+\thfnum_data_t hfnum; \\\n+\tdwc_otg_qtd_t *qtd; \\\n+\tqtd = list_entry(_qh->qtd_list.next, dwc_otg_qtd_t, qtd_list_entry); \\\n+\tif (usb_pipeint(qtd->urb->pipe) && _qh->start_split_frame != 0 && !qtd->complete_split) { \\\n+\t\thfnum.d32 = DWC_READ_REG32(&_hcd->core_if->host_if->host_global_regs->hfnum); \\\n+\t\tswitch (hfnum.b.frnum & 0x7) { \\\n+\t\tcase 7: \\\n+\t\t\t_hcd->hfnum_7_samples_##_letter++; \\\n+\t\t\t_hcd->hfnum_7_frrem_accum_##_letter += hfnum.b.frrem; \\\n+\t\t\tbreak; \\\n+\t\tcase 0: \\\n+\t\t\t_hcd->hfnum_0_samples_##_letter++; \\\n+\t\t\t_hcd->hfnum_0_frrem_accum_##_letter += hfnum.b.frrem; \\\n+\t\t\tbreak; \\\n+\t\tdefault: \\\n+\t\t\t_hcd->hfnum_other_samples_##_letter++; \\\n+\t\t\t_hcd->hfnum_other_frrem_accum_##_letter += hfnum.b.frrem; \\\n+\t\t\tbreak; \\\n+\t\t} \\\n+\t} \\\n+}\n+#else\n+#define dwc_sample_frrem(_hcd, _qh, _letter)\n+#endif\n+#endif\n+#endif /* DWC_DEVICE_ONLY */\n--- /dev/null\n+++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd_ddma.c\n@@ -0,0 +1,1134 @@\n+/*==========================================================================\n+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_ddma.c $\n+ * $Revision: #10 $\n+ * $Date: 2011/10/20 $\n+ * $Change: 1869464 $\n+ *\n+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,\n+ * \"Software\") is an Unsupported proprietary work of Synopsys, Inc. unless\n+ * otherwise expressly agreed to in writing between Synopsys and you.\n+ *\n+ * The Software IS NOT an item of Licensed Software or Licensed Product under\n+ * any End User Software License Agreement or Agreement for Licensed Product\n+ * with Synopsys or any supplement thereto. You are permitted to use and\n+ * redistribute this Software in source and binary forms, with or without\n+ * modification, provided that redistributions of source code must retain this\n+ * notice. You may not view, use, disclose, copy or distribute this file or\n+ * any information contained herein except pursuant to this license grant from\n+ * Synopsys. If you do not agree with this notice, including the disclaimer\n+ * below, then you are not authorized to use the Software.\n+ *\n+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN \"AS IS\" BASIS\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,\n+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH\n+ * DAMAGE.\n+ * ========================================================================== */\n+#ifndef DWC_DEVICE_ONLY\n+\n+/** @file\n+ * This file contains Descriptor DMA support implementation for host mode.\n+ */\n+\n+#include \"dwc_otg_hcd.h\"\n+#include \"dwc_otg_regs.h\"\n+\n+extern bool microframe_schedule;\n+\n+static inline uint8_t frame_list_idx(uint16_t frame)\n+{\n+\treturn (frame & (MAX_FRLIST_EN_NUM - 1));\n+}\n+\n+static inline uint16_t desclist_idx_inc(uint16_t idx, uint16_t inc, uint8_t speed)\n+{\n+\treturn (idx + inc) &\n+\t    (((speed ==\n+\t       DWC_OTG_EP_SPEED_HIGH) ? MAX_DMA_DESC_NUM_HS_ISOC :\n+\t      MAX_DMA_DESC_NUM_GENERIC) - 1);\n+}\n+\n+static inline uint16_t desclist_idx_dec(uint16_t idx, uint16_t inc, uint8_t speed)\n+{\n+\treturn (idx - inc) &\n+\t    (((speed ==\n+\t       DWC_OTG_EP_SPEED_HIGH) ? MAX_DMA_DESC_NUM_HS_ISOC :\n+\t      MAX_DMA_DESC_NUM_GENERIC) - 1);\n+}\n+\n+static inline uint16_t max_desc_num(dwc_otg_qh_t * qh)\n+{\n+\treturn (((qh->ep_type == UE_ISOCHRONOUS)\n+\t\t && (qh->dev_speed == DWC_OTG_EP_SPEED_HIGH))\n+\t\t? MAX_DMA_DESC_NUM_HS_ISOC : MAX_DMA_DESC_NUM_GENERIC);\n+}\n+static inline uint16_t frame_incr_val(dwc_otg_qh_t * qh)\n+{\n+\treturn ((qh->dev_speed == DWC_OTG_EP_SPEED_HIGH)\n+\t\t? ((qh->interval + 8 - 1) / 8)\n+\t\t: qh->interval);\n+}\n+\n+static int desc_list_alloc(struct device *dev, dwc_otg_qh_t * qh)\n+{\n+\tint retval = 0;\n+\n+\tqh->desc_list = (dwc_otg_host_dma_desc_t *)\n+\t    DWC_DMA_ALLOC(dev, sizeof(dwc_otg_host_dma_desc_t) * max_desc_num(qh),\n+\t\t\t  &qh->desc_list_dma);\n+\n+\tif (!qh->desc_list) {\n+\t\tretval = -DWC_E_NO_MEMORY;\n+\t\tDWC_ERROR(\"%s: DMA descriptor list allocation failed\\n\", __func__);\n+\n+\t}\n+\n+\tdwc_memset(qh->desc_list, 0x00,\n+\t\t   sizeof(dwc_otg_host_dma_desc_t) * max_desc_num(qh));\n+\n+\tqh->n_bytes =\n+\t    (uint32_t *) DWC_ALLOC(sizeof(uint32_t) * max_desc_num(qh));\n+\n+\tif (!qh->n_bytes) {\n+\t\tretval = -DWC_E_NO_MEMORY;\n+\t\tDWC_ERROR\n+\t\t    (\"%s: Failed to allocate array for descriptors' size actual values\\n\",\n+\t\t     __func__);\n+\n+\t}\n+\treturn retval;\n+\n+}\n+\n+static void desc_list_free(struct device *dev, dwc_otg_qh_t * qh)\n+{\n+\tif (qh->desc_list) {\n+\t\tDWC_DMA_FREE(dev, max_desc_num(qh), qh->desc_list,\n+\t\t\t     qh->desc_list_dma);\n+\t\tqh->desc_list = NULL;\n+\t}\n+\n+\tif (qh->n_bytes) {\n+\t\tDWC_FREE(qh->n_bytes);\n+\t\tqh->n_bytes = NULL;\n+\t}\n+}\n+\n+static int frame_list_alloc(dwc_otg_hcd_t * hcd)\n+{\n+\tstruct device *dev = dwc_otg_hcd_to_dev(hcd);\n+\tint retval = 0;\n+\n+\tif (hcd->frame_list)\n+\t\treturn 0;\n+\n+\thcd->frame_list = DWC_DMA_ALLOC(dev, 4 * MAX_FRLIST_EN_NUM,\n+\t\t\t\t\t&hcd->frame_list_dma);\n+\tif (!hcd->frame_list) {\n+\t\tretval = -DWC_E_NO_MEMORY;\n+\t\tDWC_ERROR(\"%s: Frame List allocation failed\\n\", __func__);\n+\t}\n+\n+\tdwc_memset(hcd->frame_list, 0x00, 4 * MAX_FRLIST_EN_NUM);\n+\n+\treturn retval;\n+}\n+\n+static void frame_list_free(dwc_otg_hcd_t * hcd)\n+{\n+\tstruct device *dev = dwc_otg_hcd_to_dev(hcd);\n+\n+\tif (!hcd->frame_list)\n+\t\treturn;\n+\n+\tDWC_DMA_FREE(dev, 4 * MAX_FRLIST_EN_NUM, hcd->frame_list, hcd->frame_list_dma);\n+\thcd->frame_list = NULL;\n+}\n+\n+static void per_sched_enable(dwc_otg_hcd_t * hcd, uint16_t fr_list_en)\n+{\n+\n+\thcfg_data_t hcfg;\n+\n+\thcfg.d32 = DWC_READ_REG32(&hcd->core_if->host_if->host_global_regs->hcfg);\n+\n+\tif (hcfg.b.perschedena) {\n+\t\t/* already enabled */\n+\t\treturn;\n+\t}\n+\n+\tDWC_WRITE_REG32(&hcd->core_if->host_if->host_global_regs->hflbaddr,\n+\t\t\thcd->frame_list_dma);\n+\n+\tswitch (fr_list_en) {\n+\tcase 64:\n+\t\thcfg.b.frlisten = 3;\n+\t\tbreak;\n+\tcase 32:\n+\t\thcfg.b.frlisten = 2;\n+\t\tbreak;\n+\tcase 16:\n+\t\thcfg.b.frlisten = 1;\n+\t\tbreak;\n+\tcase 8:\n+\t\thcfg.b.frlisten = 0;\n+\t\tbreak;\n+\tdefault:\n+\t\tbreak;\n+\t}\n+\n+\thcfg.b.perschedena = 1;\n+\n+\tDWC_DEBUGPL(DBG_HCD, \"Enabling Periodic schedule\\n\");\n+\tDWC_WRITE_REG32(&hcd->core_if->host_if->host_global_regs->hcfg, hcfg.d32);\n+\n+}\n+\n+static void per_sched_disable(dwc_otg_hcd_t * hcd)\n+{\n+\thcfg_data_t hcfg;\n+\n+\thcfg.d32 = DWC_READ_REG32(&hcd->core_if->host_if->host_global_regs->hcfg);\n+\n+\tif (!hcfg.b.perschedena) {\n+\t\t/* already disabled */\n+\t\treturn;\n+\t}\n+\thcfg.b.perschedena = 0;\n+\n+\tDWC_DEBUGPL(DBG_HCD, \"Disabling Periodic schedule\\n\");\n+\tDWC_WRITE_REG32(&hcd->core_if->host_if->host_global_regs->hcfg, hcfg.d32);\n+}\n+\n+/*\n+ * Activates/Deactivates FrameList entries for the channel\n+ * based on endpoint servicing period.\n+ */\n+void update_frame_list(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh, uint8_t enable)\n+{\n+\tuint16_t i, j, inc;\n+\tdwc_hc_t *hc = NULL;\n+\n+\tif (!qh->channel) {\n+\t\tDWC_ERROR(\"qh->channel = %p\", qh->channel);\n+\t\treturn;\n+\t}\n+\n+\tif (!hcd) {\n+\t\tDWC_ERROR(\"------hcd = %p\", hcd);\n+\t\treturn;\n+\t}\n+\n+\tif (!hcd->frame_list) {\n+\t\tDWC_ERROR(\"-------hcd->frame_list = %p\", hcd->frame_list);\n+\t\treturn;\n+\t}\n+\n+\thc = qh->channel;\n+\tinc = frame_incr_val(qh);\n+\tif (qh->ep_type == UE_ISOCHRONOUS)\n+\t\ti = frame_list_idx(qh->sched_frame);\n+\telse\n+\t\ti = 0;\n+\n+\tj = i;\n+\tdo {\n+\t\tif (enable)\n+\t\t\thcd->frame_list[j] |= (1 << hc->hc_num);\n+\t\telse\n+\t\t\thcd->frame_list[j] &= ~(1 << hc->hc_num);\n+\t\tj = (j + inc) & (MAX_FRLIST_EN_NUM - 1);\n+\t}\n+\twhile (j != i);\n+\tif (!enable)\n+\t\treturn;\n+\thc->schinfo = 0;\n+\tif (qh->channel->speed == DWC_OTG_EP_SPEED_HIGH) {\n+\t\tj = 1;\n+\t\t/* TODO - check this */\n+\t\tinc = (8 + qh->interval - 1) / qh->interval;\n+\t\tfor (i = 0; i < inc; i++) {\n+\t\t\thc->schinfo |= j;\n+\t\t\tj = j << qh->interval;\n+\t\t}\n+\t} else {\n+\t\thc->schinfo = 0xff;\n+\t}\n+}\n+\n+#if 1\n+void dump_frame_list(dwc_otg_hcd_t * hcd)\n+{\n+\tint i = 0;\n+\tDWC_PRINTF(\"--FRAME LIST (hex) --\\n\");\n+\tfor (i = 0; i < MAX_FRLIST_EN_NUM; i++) {\n+\t\tDWC_PRINTF(\"%x\\t\", hcd->frame_list[i]);\n+\t\tif (!(i % 8) && i)\n+\t\t\tDWC_PRINTF(\"\\n\");\n+\t}\n+\tDWC_PRINTF(\"\\n----\\n\");\n+\n+}\n+#endif\n+\n+static void release_channel_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)\n+{\n+\tdwc_hc_t *hc = qh->channel;\n+\tif (dwc_qh_is_non_per(qh)) {\n+\t\tif (!microframe_schedule)\n+\t\t\thcd->non_periodic_channels--;\n+\t\telse\n+\t\t\thcd->available_host_channels++;\n+\t} else\n+\t\tupdate_frame_list(hcd, qh, 0);\n+\n+\t/*\n+\t * The condition is added to prevent double cleanup try in case of device\n+\t * disconnect. See channel cleanup in dwc_otg_hcd_disconnect_cb().\n+\t */\n+\tif (hc->qh) {\n+\t\tdwc_otg_hc_cleanup(hcd->core_if, hc);\n+\t\tDWC_CIRCLEQ_INSERT_TAIL(&hcd->free_hc_list, hc, hc_list_entry);\n+\t\thc->qh = NULL;\n+\t}\n+\n+\tqh->channel = NULL;\n+\tqh->ntd = 0;\n+\n+\tif (qh->desc_list) {\n+\t\tdwc_memset(qh->desc_list, 0x00,\n+\t\t\t   sizeof(dwc_otg_host_dma_desc_t) * max_desc_num(qh));\n+\t}\n+}\n+\n+/**\n+ * Initializes a QH structure's Descriptor DMA related members.\n+ * Allocates memory for descriptor list.\n+ * On first periodic QH, allocates memory for FrameList\n+ * and enables periodic scheduling.\n+ *\n+ * @param hcd The HCD state structure for the DWC OTG controller.\n+ * @param qh The QH to init.\n+ *\n+ * @return 0 if successful, negative error code otherwise.\n+ */\n+int dwc_otg_hcd_qh_init_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)\n+{\n+\tstruct device *dev = dwc_otg_hcd_to_dev(hcd);\n+\tint retval = 0;\n+\n+\tif (qh->do_split) {\n+\t\tDWC_ERROR(\"SPLIT Transfers are not supported in Descriptor DMA.\\n\");\n+\t\treturn -1;\n+\t}\n+\n+\tretval = desc_list_alloc(dev, qh);\n+\n+\tif ((retval == 0)\n+\t    && (qh->ep_type == UE_ISOCHRONOUS || qh->ep_type == UE_INTERRUPT)) {\n+\t\tif (!hcd->frame_list) {\n+\t\t\tretval = frame_list_alloc(hcd);\n+\t\t\t/* Enable periodic schedule on first periodic QH */\n+\t\t\tif (retval == 0)\n+\t\t\t\tper_sched_enable(hcd, MAX_FRLIST_EN_NUM);\n+\t\t}\n+\t}\n+\n+\tqh->ntd = 0;\n+\n+\treturn retval;\n+}\n+\n+/**\n+ * Frees descriptor list memory associated with the QH.\n+ * If QH is periodic and the last, frees FrameList memory\n+ * and disables periodic scheduling.\n+ *\n+ * @param hcd The HCD state structure for the DWC OTG controller.\n+ * @param qh The QH to init.\n+ */\n+void dwc_otg_hcd_qh_free_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)\n+{\n+\tstruct device *dev = dwc_otg_hcd_to_dev(hcd);\n+\n+\tdesc_list_free(dev, qh);\n+\n+\t/*\n+\t * Channel still assigned due to some reasons.\n+\t * Seen on Isoc URB dequeue. Channel halted but no subsequent\n+\t * ChHalted interrupt to release the channel. Afterwards\n+\t * when it comes here from endpoint disable routine\n+\t * channel remains assigned.\n+\t */\n+\tif (qh->channel)\n+\t\trelease_channel_ddma(hcd, qh);\n+\n+\tif ((qh->ep_type == UE_ISOCHRONOUS || qh->ep_type == UE_INTERRUPT)\n+\t    && (microframe_schedule || !hcd->periodic_channels) && hcd->frame_list) {\n+\n+\t\tper_sched_disable(hcd);\n+\t\tframe_list_free(hcd);\n+\t}\n+}\n+\n+static uint8_t frame_to_desc_idx(dwc_otg_qh_t * qh, uint16_t frame_idx)\n+{\n+\tif (qh->dev_speed == DWC_OTG_EP_SPEED_HIGH) {\n+\t\t/*\n+\t\t * Descriptor set(8 descriptors) index\n+\t\t * which is 8-aligned.\n+\t\t */\n+\t\treturn (frame_idx & ((MAX_DMA_DESC_NUM_HS_ISOC / 8) - 1)) * 8;\n+\t} else {\n+\t\treturn (frame_idx & (MAX_DMA_DESC_NUM_GENERIC - 1));\n+\t}\n+}\n+\n+/*\n+ * Determine starting frame for Isochronous transfer.\n+ * Few frames skipped to prevent race condition with HC.\n+ */\n+static uint8_t calc_starting_frame(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh,\n+\t\t\t\t   uint8_t * skip_frames)\n+{\n+\tuint16_t frame = 0;\n+\thcd->frame_number = dwc_otg_hcd_get_frame_number(hcd);\n+\n+\t/* sched_frame is always frame number(not uFrame) both in FS and HS !! */\n+\n+\t/*\n+\t * skip_frames is used to limit activated descriptors number\n+\t * to avoid the situation when HC services the last activated\n+\t * descriptor firstly.\n+\t * Example for FS:\n+\t * Current frame is 1, scheduled frame is 3. Since HC always fetches the descriptor\n+\t * corresponding to curr_frame+1, the descriptor corresponding to frame 2\n+\t * will be fetched. If the number of descriptors is max=64 (or greather) the\n+\t * list will be fully programmed with Active descriptors and it is possible\n+\t * case(rare) that the latest descriptor(considering rollback) corresponding\n+\t * to frame 2 will be serviced first. HS case is more probable because, in fact,\n+\t * up to 11 uframes(16 in the code) may be skipped.\n+\t */\n+\tif (qh->dev_speed == DWC_OTG_EP_SPEED_HIGH) {\n+\t\t/*\n+\t\t * Consider uframe counter also, to start xfer asap.\n+\t\t * If half of the frame elapsed skip 2 frames otherwise\n+\t\t * just 1 frame.\n+\t\t * Starting descriptor index must be 8-aligned, so\n+\t\t * if the current frame is near to complete the next one\n+\t\t * is skipped as well.\n+\t\t */\n+\n+\t\tif (dwc_micro_frame_num(hcd->frame_number) >= 5) {\n+\t\t\t*skip_frames = 2 * 8;\n+\t\t\tframe = dwc_frame_num_inc(hcd->frame_number, *skip_frames);\n+\t\t} else {\n+\t\t\t*skip_frames = 1 * 8;\n+\t\t\tframe = dwc_frame_num_inc(hcd->frame_number, *skip_frames);\n+\t\t}\n+\n+\t\tframe = dwc_full_frame_num(frame);\n+\t} else {\n+\t\t/*\n+\t\t * Two frames are skipped for FS - the current and the next.\n+\t\t * But for descriptor programming, 1 frame(descriptor) is enough,\n+\t\t * see example above.\n+\t\t */\n+\t\t*skip_frames = 1;\n+\t\tframe = dwc_frame_num_inc(hcd->frame_number, 2);\n+\t}\n+\n+\treturn frame;\n+}\n+\n+/*\n+ * Calculate initial descriptor index for isochronous transfer\n+ * based on scheduled frame.\n+ */\n+static uint8_t recalc_initial_desc_idx(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)\n+{\n+\tuint16_t frame = 0, fr_idx, fr_idx_tmp;\n+\tuint8_t skip_frames = 0;\n+\t/*\n+\t * With current ISOC processing algorithm the channel is being\n+\t * released when no more QTDs in the list(qh->ntd == 0).\n+\t * Thus this function is called only when qh->ntd == 0 and qh->channel == 0.\n+\t *\n+\t * So qh->channel != NULL branch is not used and just not removed from the\n+\t * source file. It is required for another possible approach which is,\n+\t * do not disable and release the channel when ISOC session completed,\n+\t * just move QH to inactive schedule until new QTD arrives.\n+\t * On new QTD, the QH moved back to 'ready' schedule,\n+\t * starting frame and therefore starting desc_index are recalculated.\n+\t * In this case channel is released only on ep_disable.\n+\t */\n+\n+\t/* Calculate starting descriptor index. For INTERRUPT endpoint it is always 0. */\n+\tif (qh->channel) {\n+\t\tframe = calc_starting_frame(hcd, qh, &skip_frames);\n+\t\t/*\n+\t\t * Calculate initial descriptor index based on FrameList current bitmap\n+\t\t * and servicing period.\n+\t\t */\n+\t\tfr_idx_tmp = frame_list_idx(frame);\n+\t\tfr_idx =\n+\t\t    (MAX_FRLIST_EN_NUM + frame_list_idx(qh->sched_frame) -\n+\t\t     fr_idx_tmp)\n+\t\t    % frame_incr_val(qh);\n+\t\tfr_idx = (fr_idx + fr_idx_tmp) % MAX_FRLIST_EN_NUM;\n+\t} else {\n+\t\tqh->sched_frame = calc_starting_frame(hcd, qh, &skip_frames);\n+\t\tfr_idx = frame_list_idx(qh->sched_frame);\n+\t}\n+\n+\tqh->td_first = qh->td_last = frame_to_desc_idx(qh, fr_idx);\n+\n+\treturn skip_frames;\n+}\n+\n+#define\tISOC_URB_GIVEBACK_ASAP\n+\n+#define MAX_ISOC_XFER_SIZE_FS 1023\n+#define MAX_ISOC_XFER_SIZE_HS 3072\n+#define DESCNUM_THRESHOLD 4\n+\n+static void init_isoc_dma_desc(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh,\n+\t\t\t       uint8_t skip_frames)\n+{\n+\tstruct dwc_otg_hcd_iso_packet_desc *frame_desc;\n+\tdwc_otg_qtd_t *qtd;\n+\tdwc_otg_host_dma_desc_t *dma_desc;\n+\tuint16_t idx, inc, n_desc, ntd_max, max_xfer_size;\n+\n+\tidx = qh->td_last;\n+\tinc = qh->interval;\n+\tn_desc = 0;\n+\n+\tntd_max = (max_desc_num(qh) + qh->interval - 1) / qh->interval;\n+\tif (skip_frames && !qh->channel)\n+\t\tntd_max = ntd_max - skip_frames / qh->interval;\n+\n+\tmax_xfer_size =\n+\t    (qh->dev_speed ==\n+\t     DWC_OTG_EP_SPEED_HIGH) ? MAX_ISOC_XFER_SIZE_HS :\n+\t    MAX_ISOC_XFER_SIZE_FS;\n+\n+\tDWC_CIRCLEQ_FOREACH(qtd, &qh->qtd_list, qtd_list_entry) {\n+\t\twhile ((qh->ntd < ntd_max)\n+\t\t       && (qtd->isoc_frame_index_last <\n+\t\t\t   qtd->urb->packet_count)) {\n+\n+\t\t\tdma_desc = &qh->desc_list[idx];\n+\t\t\tdwc_memset(dma_desc, 0x00, sizeof(dwc_otg_host_dma_desc_t));\n+\n+\t\t\tframe_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index_last];\n+\n+\t\t\tif (frame_desc->length > max_xfer_size)\n+\t\t\t\tqh->n_bytes[idx] = max_xfer_size;\n+\t\t\telse\n+\t\t\t\tqh->n_bytes[idx] = frame_desc->length;\n+\t\t\tdma_desc->status.b_isoc.n_bytes = qh->n_bytes[idx];\n+\t\t\tdma_desc->status.b_isoc.a = 1;\n+\t\t\tdma_desc->status.b_isoc.sts = 0;\n+\n+\t\t\tdma_desc->buf = qtd->urb->dma + frame_desc->offset;\n+\n+\t\t\tqh->ntd++;\n+\n+\t\t\tqtd->isoc_frame_index_last++;\n+\n+#ifdef\tISOC_URB_GIVEBACK_ASAP\n+\t\t\t/*\n+\t\t\t * Set IOC for each descriptor corresponding to the\n+\t\t\t * last frame of the URB.\n+\t\t\t */\n+\t\t\tif (qtd->isoc_frame_index_last ==\n+\t\t\t    qtd->urb->packet_count)\n+\t\t\t\tdma_desc->status.b_isoc.ioc = 1;\n+\n+#endif\n+\t\t\tidx = desclist_idx_inc(idx, inc, qh->dev_speed);\n+\t\t\tn_desc++;\n+\n+\t\t}\n+\t\tqtd->in_process = 1;\n+\t}\n+\n+\tqh->td_last = idx;\n+\n+#ifdef\tISOC_URB_GIVEBACK_ASAP\n+\t/* Set IOC for the last descriptor if descriptor list is full */\n+\tif (qh->ntd == ntd_max) {\n+\t\tidx = desclist_idx_dec(qh->td_last, inc, qh->dev_speed);\n+\t\tqh->desc_list[idx].status.b_isoc.ioc = 1;\n+\t}\n+#else\n+\t/*\n+\t * Set IOC bit only for one descriptor.\n+\t * Always try to be ahead of HW processing,\n+\t * i.e. on IOC generation driver activates next descriptors but\n+\t * core continues to process descriptors followed the one with IOC set.\n+\t */\n+\n+\tif (n_desc > DESCNUM_THRESHOLD) {\n+\t\t/*\n+\t\t * Move IOC \"up\". Required even if there is only one QTD\n+\t\t * in the list, cause QTDs migth continue to be queued,\n+\t\t * but during the activation it was only one queued.\n+\t\t * Actually more than one QTD might be in the list if this function called\n+\t\t * from XferCompletion - QTDs was queued during HW processing of the previous\n+\t\t * descriptor chunk.\n+\t\t */\n+\t\tidx = dwc_desclist_idx_dec(idx, inc * ((qh->ntd + 1) / 2), qh->dev_speed);\n+\t} else {\n+\t\t/*\n+\t\t * Set the IOC for the latest descriptor\n+\t\t * if either number of descriptor is not greather than threshold\n+\t\t * or no more new descriptors activated.\n+\t\t */\n+\t\tidx = dwc_desclist_idx_dec(qh->td_last, inc, qh->dev_speed);\n+\t}\n+\n+\tqh->desc_list[idx].status.b_isoc.ioc = 1;\n+#endif\n+}\n+\n+static void init_non_isoc_dma_desc(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)\n+{\n+\n+\tdwc_hc_t *hc;\n+\tdwc_otg_host_dma_desc_t *dma_desc;\n+\tdwc_otg_qtd_t *qtd;\n+\tint num_packets, len, n_desc = 0;\n+\n+\thc = qh->channel;\n+\n+\t/*\n+\t * Start with hc->xfer_buff initialized in\n+\t * assign_and_init_hc(), then if SG transfer consists of multiple URBs,\n+\t * this pointer re-assigned to the buffer of the currently processed QTD.\n+\t * For non-SG request there is always one QTD active.\n+\t */\n+\n+\tDWC_CIRCLEQ_FOREACH(qtd, &qh->qtd_list, qtd_list_entry) {\n+\n+\t\tif (n_desc) {\n+\t\t\t/* SG request - more than 1 QTDs */\n+\t\t\thc->xfer_buff = (uint8_t *)qtd->urb->dma + qtd->urb->actual_length;\n+\t\t\thc->xfer_len = qtd->urb->length - qtd->urb->actual_length;\n+\t\t}\n+\n+\t\tqtd->n_desc = 0;\n+\n+\t\tdo {\n+\t\t\tdma_desc = &qh->desc_list[n_desc];\n+\t\t\tlen = hc->xfer_len;\n+\n+\t\t\tif (len > MAX_DMA_DESC_SIZE)\n+\t\t\t\tlen = MAX_DMA_DESC_SIZE - hc->max_packet + 1;\n+\n+\t\t\tif (hc->ep_is_in) {\n+\t\t\t\tif (len > 0) {\n+\t\t\t\t\tnum_packets = (len + hc->max_packet - 1) / hc->max_packet;\n+\t\t\t\t} else {\n+\t\t\t\t\t/* Need 1 packet for transfer length of 0. */\n+\t\t\t\t\tnum_packets = 1;\n+\t\t\t\t}\n+\t\t\t\t/* Always program an integral # of max packets for IN transfers. */\n+\t\t\t\tlen = num_packets * hc->max_packet;\n+\t\t\t}\n+\n+\t\t\tdma_desc->status.b.n_bytes = len;\n+\n+\t\t\tqh->n_bytes[n_desc] = len;\n+\n+\t\t\tif ((qh->ep_type == UE_CONTROL)\n+\t\t\t    && (qtd->control_phase == DWC_OTG_CONTROL_SETUP))\n+\t\t\t\tdma_desc->status.b.sup = 1;\t/* Setup Packet */\n+\n+\t\t\tdma_desc->status.b.a = 1;\t/* Active descriptor */\n+\t\t\tdma_desc->status.b.sts = 0;\n+\n+\t\t\tdma_desc->buf =\n+\t\t\t    ((unsigned long)hc->xfer_buff & 0xffffffff);\n+\n+\t\t\t/*\n+\t\t\t * Last descriptor(or single) of IN transfer\n+\t\t\t * with actual size less than MaxPacket.\n+\t\t\t */\n+\t\t\tif (len > hc->xfer_len) {\n+\t\t\t\thc->xfer_len = 0;\n+\t\t\t} else {\n+\t\t\t\thc->xfer_buff += len;\n+\t\t\t\thc->xfer_len -= len;\n+\t\t\t}\n+\n+\t\t\tqtd->n_desc++;\n+\t\t\tn_desc++;\n+\t\t}\n+\t\twhile ((hc->xfer_len > 0) && (n_desc != MAX_DMA_DESC_NUM_GENERIC));\n+\n+\n+\t\tqtd->in_process = 1;\n+\n+\t\tif (qh->ep_type == UE_CONTROL)\n+\t\t\tbreak;\n+\n+\t\tif (n_desc == MAX_DMA_DESC_NUM_GENERIC)\n+\t\t\tbreak;\n+\t}\n+\n+\tif (n_desc) {\n+\t\t/* Request Transfer Complete interrupt for the last descriptor */\n+\t\tqh->desc_list[n_desc - 1].status.b.ioc = 1;\n+\t\t/* End of List indicator */\n+\t\tqh->desc_list[n_desc - 1].status.b.eol = 1;\n+\n+\t\thc->ntd = n_desc;\n+\t}\n+}\n+\n+/**\n+ * For Control and Bulk endpoints initializes descriptor list\n+ * and starts the transfer.\n+ *\n+ * For Interrupt and Isochronous endpoints initializes descriptor list\n+ * then updates FrameList, marking appropriate entries as active.\n+ * In case of Isochronous, the starting descriptor index is calculated based\n+ * on the scheduled frame, but only on the first transfer descriptor within a session.\n+ * Then starts the transfer via enabling the channel.\n+ * For Isochronous endpoint the channel is not halted on XferComplete\n+ * interrupt so remains assigned to the endpoint(QH) until session is done.\n+ *\n+ * @param hcd The HCD state structure for the DWC OTG controller.\n+ * @param qh The QH to init.\n+ *\n+ * @return 0 if successful, negative error code otherwise.\n+ */\n+void dwc_otg_hcd_start_xfer_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)\n+{\n+\t/* Channel is already assigned */\n+\tdwc_hc_t *hc = qh->channel;\n+\tuint8_t skip_frames = 0;\n+\n+\tswitch (hc->ep_type) {\n+\tcase DWC_OTG_EP_TYPE_CONTROL:\n+\tcase DWC_OTG_EP_TYPE_BULK:\n+\t\tinit_non_isoc_dma_desc(hcd, qh);\n+\n+\t\tdwc_otg_hc_start_transfer_ddma(hcd->core_if, hc);\n+\t\tbreak;\n+\tcase DWC_OTG_EP_TYPE_INTR:\n+\t\tinit_non_isoc_dma_desc(hcd, qh);\n+\n+\t\tupdate_frame_list(hcd, qh, 1);\n+\n+\t\tdwc_otg_hc_start_transfer_ddma(hcd->core_if, hc);\n+\t\tbreak;\n+\tcase DWC_OTG_EP_TYPE_ISOC:\n+\n+\t\tif (!qh->ntd)\n+\t\t\tskip_frames = recalc_initial_desc_idx(hcd, qh);\n+\n+\t\tinit_isoc_dma_desc(hcd, qh, skip_frames);\n+\n+\t\tif (!hc->xfer_started) {\n+\n+\t\t\tupdate_frame_list(hcd, qh, 1);\n+\n+\t\t\t/*\n+\t\t\t * Always set to max, instead of actual size.\n+\t\t\t * Otherwise ntd will be changed with\n+\t\t\t * channel being enabled. Not recommended.\n+\t\t\t *\n+\t\t\t */\n+\t\t\thc->ntd = max_desc_num(qh);\n+\t\t\t/* Enable channel only once for ISOC */\n+\t\t\tdwc_otg_hc_start_transfer_ddma(hcd->core_if, hc);\n+\t\t}\n+\n+\t\tbreak;\n+\tdefault:\n+\n+\t\tbreak;\n+\t}\n+}\n+\n+static void complete_isoc_xfer_ddma(dwc_otg_hcd_t * hcd,\n+\t\t\t\t    dwc_hc_t * hc,\n+\t\t\t\t    dwc_otg_hc_regs_t * hc_regs,\n+\t\t\t\t    dwc_otg_halt_status_e halt_status)\n+{\n+\tstruct dwc_otg_hcd_iso_packet_desc *frame_desc;\n+\tdwc_otg_qtd_t *qtd, *qtd_tmp;\n+\tdwc_otg_qh_t *qh;\n+\tdwc_otg_host_dma_desc_t *dma_desc;\n+\tuint16_t idx, remain;\n+\tuint8_t urb_compl;\n+\n+\tqh = hc->qh;\n+\tidx = qh->td_first;\n+\n+\tif (hc->halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE) {\n+\t\tDWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &hc->qh->qtd_list, qtd_list_entry)\n+\t\t    qtd->in_process = 0;\n+\t\treturn;\n+\t} else if ((halt_status == DWC_OTG_HC_XFER_AHB_ERR) ||\n+\t\t   (halt_status == DWC_OTG_HC_XFER_BABBLE_ERR)) {\n+\t\t/*\n+\t\t * Channel is halted in these error cases.\n+\t\t * Considered as serious issues.\n+\t\t * Complete all URBs marking all frames as failed,\n+\t\t * irrespective whether some of the descriptors(frames) succeeded or no.\n+\t\t * Pass error code to completion routine as well, to\n+\t\t * update urb->status, some of class drivers might use it to stop\n+\t\t * queing transfer requests.\n+\t\t */\n+\t\tint err = (halt_status == DWC_OTG_HC_XFER_AHB_ERR)\n+\t\t    ? (-DWC_E_IO)\n+\t\t    : (-DWC_E_OVERFLOW);\n+\n+\t\tDWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &hc->qh->qtd_list, qtd_list_entry) {\n+\t\t\tfor (idx = 0; idx < qtd->urb->packet_count; idx++) {\n+\t\t\t\tframe_desc = &qtd->urb->iso_descs[idx];\n+\t\t\t\tframe_desc->status = err;\n+\t\t\t}\n+\t\t\thcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, err);\n+\t\t\tdwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh);\n+\t\t}\n+\t\treturn;\n+\t}\n+\n+\tDWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &hc->qh->qtd_list, qtd_list_entry) {\n+\n+\t\tif (!qtd->in_process)\n+\t\t\tbreak;\n+\n+\t\turb_compl = 0;\n+\n+\t\tdo {\n+\n+\t\t\tdma_desc = &qh->desc_list[idx];\n+\n+\t\t\tframe_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index];\n+\t\t\tremain = hc->ep_is_in ? dma_desc->status.b_isoc.n_bytes : 0;\n+\n+\t\t\tif (dma_desc->status.b_isoc.sts == DMA_DESC_STS_PKTERR) {\n+\t\t\t\t/*\n+\t\t\t\t * XactError or, unable to complete all the transactions\n+\t\t\t\t * in the scheduled micro-frame/frame,\n+\t\t\t\t * both indicated by DMA_DESC_STS_PKTERR.\n+\t\t\t\t */\n+\t\t\t\tqtd->urb->error_count++;\n+\t\t\t\tframe_desc->actual_length = qh->n_bytes[idx] - remain;\n+\t\t\t\tframe_desc->status = -DWC_E_PROTOCOL;\n+\t\t\t} else {\n+\t\t\t\t/* Success */\n+\n+\t\t\t\tframe_desc->actual_length = qh->n_bytes[idx] - remain;\n+\t\t\t\tframe_desc->status = 0;\n+\t\t\t}\n+\n+\t\t\tif (++qtd->isoc_frame_index == qtd->urb->packet_count) {\n+\t\t\t\t/*\n+\t\t\t\t * urb->status is not used for isoc transfers here.\n+\t\t\t\t * The individual frame_desc status are used instead.\n+\t\t\t\t */\n+\n+\t\t\t\thcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0);\n+\t\t\t\tdwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh);\n+\n+\t\t\t\t/*\n+\t\t\t\t * This check is necessary because urb_dequeue can be called\n+\t\t\t\t * from urb complete callback(sound driver example).\n+\t\t\t\t * All pending URBs are dequeued there, so no need for\n+\t\t\t\t * further processing.\n+\t\t\t\t */\n+\t\t\t\tif (hc->halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE) {\n+\t\t\t\t\treturn;\n+\t\t\t\t}\n+\n+\t\t\t\turb_compl = 1;\n+\n+\t\t\t}\n+\n+\t\t\tqh->ntd--;\n+\n+\t\t\t/* Stop if IOC requested descriptor reached */\n+\t\t\tif (dma_desc->status.b_isoc.ioc) {\n+\t\t\t\tidx = desclist_idx_inc(idx, qh->interval, hc->speed);\n+\t\t\t\tgoto stop_scan;\n+\t\t\t}\n+\n+\t\t\tidx = desclist_idx_inc(idx, qh->interval, hc->speed);\n+\n+\t\t\tif (urb_compl)\n+\t\t\t\tbreak;\n+\t\t}\n+\t\twhile (idx != qh->td_first);\n+\t}\n+stop_scan:\n+\tqh->td_first = idx;\n+}\n+\n+uint8_t update_non_isoc_urb_state_ddma(dwc_otg_hcd_t * hcd,\n+\t\t\t\t       dwc_hc_t * hc,\n+\t\t\t\t       dwc_otg_qtd_t * qtd,\n+\t\t\t\t       dwc_otg_host_dma_desc_t * dma_desc,\n+\t\t\t\t       dwc_otg_halt_status_e halt_status,\n+\t\t\t\t       uint32_t n_bytes, uint8_t * xfer_done)\n+{\n+\n+\tuint16_t remain = hc->ep_is_in ? dma_desc->status.b.n_bytes : 0;\n+\tdwc_otg_hcd_urb_t *urb = qtd->urb;\n+\n+\tif (halt_status == DWC_OTG_HC_XFER_AHB_ERR) {\n+\t\turb->status = -DWC_E_IO;\n+\t\treturn 1;\n+\t}\n+\tif (dma_desc->status.b.sts == DMA_DESC_STS_PKTERR) {\n+\t\tswitch (halt_status) {\n+\t\tcase DWC_OTG_HC_XFER_STALL:\n+\t\t\turb->status = -DWC_E_PIPE;\n+\t\t\tbreak;\n+\t\tcase DWC_OTG_HC_XFER_BABBLE_ERR:\n+\t\t\turb->status = -DWC_E_OVERFLOW;\n+\t\t\tbreak;\n+\t\tcase DWC_OTG_HC_XFER_XACT_ERR:\n+\t\t\turb->status = -DWC_E_PROTOCOL;\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tDWC_ERROR(\"%s: Unhandled descriptor error status (%d)\\n\", __func__,\n+\t\t\t\t  halt_status);\n+\t\t\tbreak;\n+\t\t}\n+\t\treturn 1;\n+\t}\n+\n+\tif (dma_desc->status.b.a == 1) {\n+\t\tDWC_DEBUGPL(DBG_HCDV,\n+\t\t\t    \"Active descriptor encountered on channel %d\\n\",\n+\t\t\t    hc->hc_num);\n+\t\treturn 0;\n+\t}\n+\n+\tif (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL) {\n+\t\tif (qtd->control_phase == DWC_OTG_CONTROL_DATA) {\n+\t\t\turb->actual_length += n_bytes - remain;\n+\t\t\tif (remain || urb->actual_length == urb->length) {\n+\t\t\t\t/*\n+\t\t\t\t * For Control Data stage do not set urb->status=0 to prevent\n+\t\t\t\t * URB callback. Set it when Status phase done. See below.\n+\t\t\t\t */\n+\t\t\t\t*xfer_done = 1;\n+\t\t\t}\n+\n+\t\t} else if (qtd->control_phase == DWC_OTG_CONTROL_STATUS) {\n+\t\t\turb->status = 0;\n+\t\t\t*xfer_done = 1;\n+\t\t}\n+\t\t/* No handling for SETUP stage */\n+\t} else {\n+\t\t/* BULK and INTR */\n+\t\turb->actual_length += n_bytes - remain;\n+\t\tif (remain || urb->actual_length == urb->length) {\n+\t\t\turb->status = 0;\n+\t\t\t*xfer_done = 1;\n+\t\t}\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static void complete_non_isoc_xfer_ddma(dwc_otg_hcd_t * hcd,\n+\t\t\t\t\tdwc_hc_t * hc,\n+\t\t\t\t\tdwc_otg_hc_regs_t * hc_regs,\n+\t\t\t\t\tdwc_otg_halt_status_e halt_status)\n+{\n+\tdwc_otg_hcd_urb_t *urb = NULL;\n+\tdwc_otg_qtd_t *qtd, *qtd_tmp;\n+\tdwc_otg_qh_t *qh;\n+\tdwc_otg_host_dma_desc_t *dma_desc;\n+\tuint32_t n_bytes, n_desc, i;\n+\tuint8_t failed = 0, xfer_done;\n+\n+\tn_desc = 0;\n+\n+\tqh = hc->qh;\n+\n+\tif (hc->halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE) {\n+\t\tDWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &hc->qh->qtd_list, qtd_list_entry) {\n+\t\t\tqtd->in_process = 0;\n+\t\t}\n+\t\treturn;\n+\t}\n+\n+\tDWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &qh->qtd_list, qtd_list_entry) {\n+\n+\t\turb = qtd->urb;\n+\n+\t\tn_bytes = 0;\n+\t\txfer_done = 0;\n+\n+\t\tfor (i = 0; i < qtd->n_desc; i++) {\n+\t\t\tdma_desc = &qh->desc_list[n_desc];\n+\n+\t\t\tn_bytes = qh->n_bytes[n_desc];\n+\n+\t\t\tfailed =\n+\t\t\t    update_non_isoc_urb_state_ddma(hcd, hc, qtd,\n+\t\t\t\t\t\t\t   dma_desc,\n+\t\t\t\t\t\t\t   halt_status, n_bytes,\n+\t\t\t\t\t\t\t   &xfer_done);\n+\n+\t\t\tif (failed\n+\t\t\t    || (xfer_done\n+\t\t\t\t&& (urb->status != -DWC_E_IN_PROGRESS))) {\n+\n+\t\t\t\thcd->fops->complete(hcd, urb->priv, urb,\n+\t\t\t\t\t\t    urb->status);\n+\t\t\t\tdwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh);\n+\n+\t\t\t\tif (failed)\n+\t\t\t\t\tgoto stop_scan;\n+\t\t\t} else if (qh->ep_type == UE_CONTROL) {\n+\t\t\t\tif (qtd->control_phase == DWC_OTG_CONTROL_SETUP) {\n+\t\t\t\t\tif (urb->length > 0) {\n+\t\t\t\t\t\tqtd->control_phase = DWC_OTG_CONTROL_DATA;\n+\t\t\t\t\t} else {\n+\t\t\t\t\t\tqtd->control_phase = DWC_OTG_CONTROL_STATUS;\n+\t\t\t\t\t}\n+\t\t\t\t\tDWC_DEBUGPL(DBG_HCDV, \"  Control setup transaction done\\n\");\n+\t\t\t\t} else if (qtd->control_phase == DWC_OTG_CONTROL_DATA) {\n+\t\t\t\t\tif (xfer_done) {\n+\t\t\t\t\t\tqtd->control_phase = DWC_OTG_CONTROL_STATUS;\n+\t\t\t\t\t\tDWC_DEBUGPL(DBG_HCDV, \"  Control data transfer done\\n\");\n+\t\t\t\t\t} else if (i + 1 == qtd->n_desc) {\n+\t\t\t\t\t\t/*\n+\t\t\t\t\t\t * Last descriptor for Control data stage which is\n+\t\t\t\t\t\t * not completed yet.\n+\t\t\t\t\t\t */\n+\t\t\t\t\t\tdwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);\n+\t\t\t\t\t}\n+\t\t\t\t}\n+\t\t\t}\n+\n+\t\t\tn_desc++;\n+\t\t}\n+\n+\t}\n+\n+stop_scan:\n+\n+\tif (qh->ep_type != UE_CONTROL) {\n+\t\t/*\n+\t\t * Resetting the data toggle for bulk\n+\t\t * and interrupt endpoints in case of stall. See handle_hc_stall_intr()\n+\t\t */\n+\t\tif (halt_status == DWC_OTG_HC_XFER_STALL)\n+\t\t\tqh->data_toggle = DWC_OTG_HC_PID_DATA0;\n+\t\telse\n+\t\t\tdwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);\n+\t}\n+\n+\tif (halt_status == DWC_OTG_HC_XFER_COMPLETE) {\n+\t\thcint_data_t hcint;\n+\t\thcint.d32 = DWC_READ_REG32(&hc_regs->hcint);\n+\t\tif (hcint.b.nyet) {\n+\t\t\t/*\n+\t\t\t * Got a NYET on the last transaction of the transfer. It\n+\t\t\t * means that the endpoint should be in the PING state at the\n+\t\t\t * beginning of the next transfer.\n+\t\t\t */\n+\t\t\tqh->ping_state = 1;\n+\t\t\tclear_hc_int(hc_regs, nyet);\n+\t\t}\n+\n+\t}\n+\n+}\n+\n+/**\n+ * This function is called from interrupt handlers.\n+ * Scans the descriptor list, updates URB's status and\n+ * calls completion routine for the URB if it's done.\n+ * Releases the channel to be used by other transfers.\n+ * In case of Isochronous endpoint the channel is not halted until\n+ * the end of the session, i.e. QTD list is empty.\n+ * If periodic channel released the FrameList is updated accordingly.\n+ *\n+ * Calls transaction selection routines to activate pending transfers.\n+ *\n+ * @param hcd The HCD state structure for the DWC OTG controller.\n+ * @param hc Host channel, the transfer is completed on.\n+ * @param hc_regs Host channel registers.\n+ * @param halt_status Reason the channel is being halted,\n+ *\t\t      or just XferComplete for isochronous transfer\n+ */\n+void dwc_otg_hcd_complete_xfer_ddma(dwc_otg_hcd_t * hcd,\n+\t\t\t\t    dwc_hc_t * hc,\n+\t\t\t\t    dwc_otg_hc_regs_t * hc_regs,\n+\t\t\t\t    dwc_otg_halt_status_e halt_status)\n+{\n+\tuint8_t continue_isoc_xfer = 0;\n+\tdwc_otg_transaction_type_e tr_type;\n+\tdwc_otg_qh_t *qh = hc->qh;\n+\n+\tif (hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {\n+\n+\t\tcomplete_isoc_xfer_ddma(hcd, hc, hc_regs, halt_status);\n+\n+\t\t/* Release the channel if halted or session completed */\n+\t\tif (halt_status != DWC_OTG_HC_XFER_COMPLETE ||\n+\t\t    DWC_CIRCLEQ_EMPTY(&qh->qtd_list)) {\n+\n+\t\t\t/* Halt the channel if session completed */\n+\t\t\tif (halt_status == DWC_OTG_HC_XFER_COMPLETE) {\n+\t\t\t\tdwc_otg_hc_halt(hcd->core_if, hc, halt_status);\n+\t\t\t}\n+\n+\t\t\trelease_channel_ddma(hcd, qh);\n+\t\t\tdwc_otg_hcd_qh_remove(hcd, qh);\n+\t\t} else {\n+\t\t\t/* Keep in assigned schedule to continue transfer */\n+\t\t\tDWC_LIST_MOVE_HEAD(&hcd->periodic_sched_assigned,\n+\t\t\t\t\t   &qh->qh_list_entry);\n+\t\t\tcontinue_isoc_xfer = 1;\n+\n+\t\t}\n+\t\t/** @todo Consider the case when period exceeds FrameList size.\n+\t\t *  Frame Rollover interrupt should be used.\n+\t\t */\n+\t} else {\n+\t\t/* Scan descriptor list to complete the URB(s), then release the channel */\n+\t\tcomplete_non_isoc_xfer_ddma(hcd, hc, hc_regs, halt_status);\n+\n+\t\trelease_channel_ddma(hcd, qh);\n+\t\tdwc_otg_hcd_qh_remove(hcd, qh);\n+\n+\t\tif (!DWC_CIRCLEQ_EMPTY(&qh->qtd_list)) {\n+\t\t\t/* Add back to inactive non-periodic schedule on normal completion */\n+\t\t\tdwc_otg_hcd_qh_add(hcd, qh);\n+\t\t}\n+\n+\t}\n+\ttr_type = dwc_otg_hcd_select_transactions(hcd);\n+\tif (tr_type != DWC_OTG_TRANSACTION_NONE || continue_isoc_xfer) {\n+\t\tif (continue_isoc_xfer) {\n+\t\t\tif (tr_type == DWC_OTG_TRANSACTION_NONE) {\n+\t\t\t\ttr_type = DWC_OTG_TRANSACTION_PERIODIC;\n+\t\t\t} else if (tr_type == DWC_OTG_TRANSACTION_NON_PERIODIC) {\n+\t\t\t\ttr_type = DWC_OTG_TRANSACTION_ALL;\n+\t\t\t}\n+\t\t}\n+\t\tdwc_otg_hcd_queue_transactions(hcd, tr_type);\n+\t}\n+}\n+\n+#endif /* DWC_DEVICE_ONLY */\n--- /dev/null\n+++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd_if.h\n@@ -0,0 +1,421 @@\n+/* ==========================================================================\n+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_if.h $\n+ * $Revision: #12 $\n+ * $Date: 2011/10/26 $\n+ * $Change: 1873028 $\n+ *\n+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,\n+ * \"Software\") is an Unsupported proprietary work of Synopsys, Inc. unless\n+ * otherwise expressly agreed to in writing between Synopsys and you.\n+ *\n+ * The Software IS NOT an item of Licensed Software or Licensed Product under\n+ * any End User Software License Agreement or Agreement for Licensed Product\n+ * with Synopsys or any supplement thereto. You are permitted to use and\n+ * redistribute this Software in source and binary forms, with or without\n+ * modification, provided that redistributions of source code must retain this\n+ * notice. You may not view, use, disclose, copy or distribute this file or\n+ * any information contained herein except pursuant to this license grant from\n+ * Synopsys. If you do not agree with this notice, including the disclaimer\n+ * below, then you are not authorized to use the Software.\n+ *\n+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN \"AS IS\" BASIS\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,\n+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH\n+ * DAMAGE.\n+ * ========================================================================== */\n+#ifndef DWC_DEVICE_ONLY\n+#ifndef __DWC_HCD_IF_H__\n+#define __DWC_HCD_IF_H__\n+\n+#include \"dwc_otg_core_if.h\"\n+\n+/** @file\n+ * This file defines DWC_OTG HCD Core API.\n+ */\n+\n+struct dwc_otg_hcd;\n+typedef struct dwc_otg_hcd dwc_otg_hcd_t;\n+\n+struct dwc_otg_hcd_urb;\n+typedef struct dwc_otg_hcd_urb dwc_otg_hcd_urb_t;\n+\n+/** @name HCD Function Driver Callbacks */\n+/** @{ */\n+\n+/** This function is called whenever core switches to host mode. */\n+typedef int (*dwc_otg_hcd_start_cb_t) (dwc_otg_hcd_t * hcd);\n+\n+/** This function is called when device has been disconnected */\n+typedef int (*dwc_otg_hcd_disconnect_cb_t) (dwc_otg_hcd_t * hcd);\n+\n+/** Wrapper provides this function to HCD to core, so it can get hub information to which device is connected */\n+typedef int (*dwc_otg_hcd_hub_info_from_urb_cb_t) (dwc_otg_hcd_t * hcd,\n+\t\t\t\t\t\t   void *urb_handle,\n+\t\t\t\t\t\t   uint32_t * hub_addr,\n+\t\t\t\t\t\t   uint32_t * port_addr);\n+/** Via this function HCD core gets device speed */\n+typedef int (*dwc_otg_hcd_speed_from_urb_cb_t) (dwc_otg_hcd_t * hcd,\n+\t\t\t\t\t\tvoid *urb_handle);\n+\n+/** This function is called when urb is completed */\n+typedef int (*dwc_otg_hcd_complete_urb_cb_t) (dwc_otg_hcd_t * hcd,\n+\t\t\t\t\t      void *urb_handle,\n+\t\t\t\t\t      dwc_otg_hcd_urb_t * dwc_otg_urb,\n+\t\t\t\t\t      int32_t status);\n+\n+/** Via this function HCD core gets b_hnp_enable parameter */\n+typedef int (*dwc_otg_hcd_get_b_hnp_enable) (dwc_otg_hcd_t * hcd);\n+\n+struct dwc_otg_hcd_function_ops {\n+\tdwc_otg_hcd_start_cb_t start;\n+\tdwc_otg_hcd_disconnect_cb_t disconnect;\n+\tdwc_otg_hcd_hub_info_from_urb_cb_t hub_info;\n+\tdwc_otg_hcd_speed_from_urb_cb_t speed;\n+\tdwc_otg_hcd_complete_urb_cb_t complete;\n+\tdwc_otg_hcd_get_b_hnp_enable get_b_hnp_enable;\n+};\n+/** @} */\n+\n+/** @name HCD Core API */\n+/** @{ */\n+/** This function allocates dwc_otg_hcd structure and returns pointer on it. */\n+extern dwc_otg_hcd_t *dwc_otg_hcd_alloc_hcd(void);\n+\n+/** This function should be called to initiate HCD Core.\n+ *\n+ * @param hcd The HCD\n+ * @param core_if The DWC_OTG Core\n+ *\n+ * Returns -DWC_E_NO_MEMORY if no enough memory.\n+ * Returns 0 on success\n+ */\n+extern int dwc_otg_hcd_init(dwc_otg_hcd_t * hcd, dwc_otg_core_if_t * core_if);\n+\n+/** Frees HCD\n+ *\n+ * @param hcd The HCD\n+ */\n+extern void dwc_otg_hcd_remove(dwc_otg_hcd_t * hcd);\n+\n+/** This function should be called on every hardware interrupt.\n+ *\n+ * @param dwc_otg_hcd The HCD\n+ *\n+ * Returns non zero if interrupt is handled\n+ * Return 0 if interrupt is not handled\n+ */\n+extern int32_t dwc_otg_hcd_handle_intr(dwc_otg_hcd_t * dwc_otg_hcd);\n+\n+/** This function is used to handle the fast interrupt\n+ *\n+ */\n+#ifdef CONFIG_ARM64\n+extern void dwc_otg_hcd_handle_fiq(void);\n+#else\n+extern void __attribute__ ((naked)) dwc_otg_hcd_handle_fiq(void);\n+#endif\n+\n+/**\n+ * Returns private data set by\n+ * dwc_otg_hcd_set_priv_data function.\n+ *\n+ * @param hcd The HCD\n+ */\n+extern void *dwc_otg_hcd_get_priv_data(dwc_otg_hcd_t * hcd);\n+\n+/**\n+ * Set private data.\n+ *\n+ * @param hcd The HCD\n+ * @param priv_data pointer to be stored in private data\n+ */\n+extern void dwc_otg_hcd_set_priv_data(dwc_otg_hcd_t * hcd, void *priv_data);\n+\n+/**\n+ * This function initializes the HCD Core.\n+ *\n+ * @param hcd The HCD\n+ * @param fops The Function Driver Operations data structure containing pointers to all callbacks.\n+ *\n+ * Returns -DWC_E_NO_DEVICE if Core is currently is in device mode.\n+ * Returns 0 on success\n+ */\n+extern int dwc_otg_hcd_start(dwc_otg_hcd_t * hcd,\n+\t\t\t     struct dwc_otg_hcd_function_ops *fops);\n+\n+/**\n+ * Halts the DWC_otg host mode operations in a clean manner. USB transfers are\n+ * stopped.\n+ *\n+ * @param hcd The HCD\n+ */\n+extern void dwc_otg_hcd_stop(dwc_otg_hcd_t * hcd);\n+\n+/**\n+ * Handles hub class-specific requests.\n+ *\n+ * @param dwc_otg_hcd The HCD\n+ * @param typeReq Request Type\n+ * @param wValue wValue from control request\n+ * @param wIndex wIndex from control request\n+ * @param buf data buffer\n+ * @param wLength data buffer length\n+ *\n+ * Returns -DWC_E_INVALID if invalid argument is passed\n+ * Returns 0 on success\n+ */\n+extern int dwc_otg_hcd_hub_control(dwc_otg_hcd_t * dwc_otg_hcd,\n+\t\t\t\t   uint16_t typeReq, uint16_t wValue,\n+\t\t\t\t   uint16_t wIndex, uint8_t * buf,\n+\t\t\t\t   uint16_t wLength);\n+\n+/**\n+ * Returns otg port number.\n+ *\n+ * @param hcd The HCD\n+ */\n+extern uint32_t dwc_otg_hcd_otg_port(dwc_otg_hcd_t * hcd);\n+\n+/**\n+ * Returns OTG version - either 1.3 or 2.0.\n+ *\n+ * @param core_if The core_if structure pointer\n+ */\n+extern uint16_t dwc_otg_get_otg_version(dwc_otg_core_if_t * core_if);\n+\n+/**\n+ * Returns 1 if currently core is acting as B host, and 0 otherwise.\n+ *\n+ * @param hcd The HCD\n+ */\n+extern uint32_t dwc_otg_hcd_is_b_host(dwc_otg_hcd_t * hcd);\n+\n+/**\n+ * Returns current frame number.\n+ *\n+ * @param hcd The HCD\n+ */\n+extern int dwc_otg_hcd_get_frame_number(dwc_otg_hcd_t * hcd);\n+\n+/**\n+ * Dumps hcd state.\n+ *\n+ * @param hcd The HCD\n+ */\n+extern void dwc_otg_hcd_dump_state(dwc_otg_hcd_t * hcd);\n+\n+/**\n+ * Dump the average frame remaining at SOF. This can be used to\n+ * determine average interrupt latency. Frame remaining is also shown for\n+ * start transfer and two additional sample points.\n+ * Currently this function is not implemented.\n+ *\n+ * @param hcd The HCD\n+ */\n+extern void dwc_otg_hcd_dump_frrem(dwc_otg_hcd_t * hcd);\n+\n+/**\n+ * Sends LPM transaction to the local device.\n+ *\n+ * @param hcd The HCD\n+ * @param devaddr Device Address\n+ * @param hird Host initiated resume duration\n+ * @param bRemoteWake Value of bRemoteWake field in LPM transaction\n+ *\n+ * Returns negative value if sending LPM transaction was not succeeded.\n+ * Returns 0 on success.\n+ */\n+extern int dwc_otg_hcd_send_lpm(dwc_otg_hcd_t * hcd, uint8_t devaddr,\n+\t\t\t\tuint8_t hird, uint8_t bRemoteWake);\n+\n+/* URB interface */\n+\n+/**\n+ * Allocates memory for dwc_otg_hcd_urb structure.\n+ * Allocated memory should be freed by call of DWC_FREE.\n+ *\n+ * @param hcd The HCD\n+ * @param iso_desc_count Count of ISOC descriptors\n+ * @param atomic_alloc Specefies whether to perform atomic allocation.\n+ */\n+extern dwc_otg_hcd_urb_t *dwc_otg_hcd_urb_alloc(dwc_otg_hcd_t * hcd,\n+\t\t\t\t\t\tint iso_desc_count,\n+\t\t\t\t\t\tint atomic_alloc);\n+\n+/**\n+ * Set pipe information in URB.\n+ *\n+ * @param hcd_urb DWC_OTG URB\n+ * @param devaddr Device Address\n+ * @param ep_num Endpoint Number\n+ * @param ep_type Endpoint Type\n+ * @param ep_dir Endpoint Direction\n+ * @param mps Max Packet Size\n+ */\n+extern void dwc_otg_hcd_urb_set_pipeinfo(dwc_otg_hcd_urb_t * hcd_urb,\n+\t\t\t\t\t uint8_t devaddr, uint8_t ep_num,\n+\t\t\t\t\t uint8_t ep_type, uint8_t ep_dir,\n+\t\t\t\t\t uint16_t mps);\n+\n+/* Transfer flags */\n+#define URB_GIVEBACK_ASAP 0x1\n+#define URB_SEND_ZERO_PACKET 0x2\n+\n+/**\n+ * Sets dwc_otg_hcd_urb parameters.\n+ *\n+ * @param urb DWC_OTG URB allocated by dwc_otg_hcd_urb_alloc function.\n+ * @param urb_handle Unique handle for request, this will be passed back\n+ * to function driver in completion callback.\n+ * @param buf The buffer for the data\n+ * @param dma The DMA buffer for the data\n+ * @param buflen Transfer length\n+ * @param sp Buffer for setup data\n+ * @param sp_dma DMA address of setup data buffer\n+ * @param flags Transfer flags\n+ * @param interval Polling interval for interrupt or isochronous transfers.\n+ */\n+extern void dwc_otg_hcd_urb_set_params(dwc_otg_hcd_urb_t * urb,\n+\t\t\t\t       void *urb_handle, void *buf,\n+\t\t\t\t       dwc_dma_t dma, uint32_t buflen, void *sp,\n+\t\t\t\t       dwc_dma_t sp_dma, uint32_t flags,\n+\t\t\t\t       uint16_t interval);\n+\n+/** Gets status from dwc_otg_hcd_urb\n+ *\n+ * @param dwc_otg_urb DWC_OTG URB\n+ */\n+extern uint32_t dwc_otg_hcd_urb_get_status(dwc_otg_hcd_urb_t * dwc_otg_urb);\n+\n+/** Gets actual length from dwc_otg_hcd_urb\n+ *\n+ * @param dwc_otg_urb DWC_OTG URB\n+ */\n+extern uint32_t dwc_otg_hcd_urb_get_actual_length(dwc_otg_hcd_urb_t *\n+\t\t\t\t\t\t  dwc_otg_urb);\n+\n+/** Gets error count from dwc_otg_hcd_urb. Only for ISOC URBs\n+ *\n+ * @param dwc_otg_urb DWC_OTG URB\n+ */\n+extern uint32_t dwc_otg_hcd_urb_get_error_count(dwc_otg_hcd_urb_t *\n+\t\t\t\t\t\tdwc_otg_urb);\n+\n+/** Set ISOC descriptor offset and length\n+ *\n+ * @param dwc_otg_urb DWC_OTG URB\n+ * @param desc_num ISOC descriptor number\n+ * @param offset Offset from beginig of buffer.\n+ * @param length Transaction length\n+ */\n+extern void dwc_otg_hcd_urb_set_iso_desc_params(dwc_otg_hcd_urb_t * dwc_otg_urb,\n+\t\t\t\t\t\tint desc_num, uint32_t offset,\n+\t\t\t\t\t\tuint32_t length);\n+\n+/** Get status of ISOC descriptor, specified by desc_num\n+ *\n+ * @param dwc_otg_urb DWC_OTG URB\n+ * @param desc_num ISOC descriptor number\n+ */\n+extern uint32_t dwc_otg_hcd_urb_get_iso_desc_status(dwc_otg_hcd_urb_t *\n+\t\t\t\t\t\t    dwc_otg_urb, int desc_num);\n+\n+/** Get actual length of ISOC descriptor, specified by desc_num\n+ *\n+ * @param dwc_otg_urb DWC_OTG URB\n+ * @param desc_num ISOC descriptor number\n+ */\n+extern uint32_t dwc_otg_hcd_urb_get_iso_desc_actual_length(dwc_otg_hcd_urb_t *\n+\t\t\t\t\t\t\t   dwc_otg_urb,\n+\t\t\t\t\t\t\t   int desc_num);\n+\n+/** Queue URB. After transfer is completes, the complete callback will be called with the URB status\n+ *\n+ * @param dwc_otg_hcd The HCD\n+ * @param dwc_otg_urb DWC_OTG URB\n+ * @param ep_handle Out parameter for returning endpoint handle\n+ * @param atomic_alloc Flag to do atomic allocation if needed\n+ *\n+ * Returns -DWC_E_NO_DEVICE if no device is connected.\n+ * Returns -DWC_E_NO_MEMORY if there is no enough memory.\n+ * Returns 0 on success.\n+ */\n+extern int dwc_otg_hcd_urb_enqueue(dwc_otg_hcd_t * dwc_otg_hcd,\n+\t\t\t\t   dwc_otg_hcd_urb_t * dwc_otg_urb,\n+\t\t\t\t   void **ep_handle, int atomic_alloc);\n+\n+/** De-queue the specified URB\n+ *\n+ * @param dwc_otg_hcd The HCD\n+ * @param dwc_otg_urb DWC_OTG URB\n+ */\n+extern int dwc_otg_hcd_urb_dequeue(dwc_otg_hcd_t * dwc_otg_hcd,\n+\t\t\t\t   dwc_otg_hcd_urb_t * dwc_otg_urb);\n+\n+/** Frees resources in the DWC_otg controller related to a given endpoint.\n+ * Any URBs for the endpoint must already be dequeued.\n+ *\n+ * @param hcd The HCD\n+ * @param ep_handle Endpoint handle, returned by dwc_otg_hcd_urb_enqueue function\n+ * @param retry Number of retries if there are queued transfers.\n+ *\n+ * Returns -DWC_E_INVALID if invalid arguments are passed.\n+ * Returns 0 on success\n+ */\n+extern int dwc_otg_hcd_endpoint_disable(dwc_otg_hcd_t * hcd, void *ep_handle,\n+\t\t\t\t\tint retry);\n+\n+/* Resets the data toggle in qh structure. This function can be called from\n+ * usb_clear_halt routine.\n+ *\n+ * @param hcd The HCD\n+ * @param ep_handle Endpoint handle, returned by dwc_otg_hcd_urb_enqueue function\n+ *\n+ * Returns -DWC_E_INVALID if invalid arguments are passed.\n+ * Returns 0 on success\n+ */\n+extern int dwc_otg_hcd_endpoint_reset(dwc_otg_hcd_t * hcd, void *ep_handle);\n+\n+/** Returns 1 if status of specified port is changed and 0 otherwise.\n+ *\n+ * @param hcd The HCD\n+ * @param port Port number\n+ */\n+extern int dwc_otg_hcd_is_status_changed(dwc_otg_hcd_t * hcd, int port);\n+\n+/** Call this function to check if bandwidth was allocated for specified endpoint.\n+ * Only for ISOC and INTERRUPT endpoints.\n+ *\n+ * @param hcd The HCD\n+ * @param ep_handle Endpoint handle\n+ */\n+extern int dwc_otg_hcd_is_bandwidth_allocated(dwc_otg_hcd_t * hcd,\n+\t\t\t\t\t      void *ep_handle);\n+\n+/** Call this function to check if bandwidth was freed for specified endpoint.\n+ *\n+ * @param hcd The HCD\n+ * @param ep_handle Endpoint handle\n+ */\n+extern int dwc_otg_hcd_is_bandwidth_freed(dwc_otg_hcd_t * hcd, void *ep_handle);\n+\n+/** Returns bandwidth allocated for specified endpoint in microseconds.\n+ * Only for ISOC and INTERRUPT endpoints.\n+ *\n+ * @param hcd The HCD\n+ * @param ep_handle Endpoint handle\n+ */\n+extern uint8_t dwc_otg_hcd_get_ep_bandwidth(dwc_otg_hcd_t * hcd,\n+\t\t\t\t\t    void *ep_handle);\n+\n+/** @} */\n+\n+#endif /* __DWC_HCD_IF_H__ */\n+#endif /* DWC_DEVICE_ONLY */\n--- /dev/null\n+++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c\n@@ -0,0 +1,2757 @@\n+/* ==========================================================================\n+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_intr.c $\n+ * $Revision: #89 $\n+ * $Date: 2011/10/20 $\n+ * $Change: 1869487 $\n+ *\n+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,\n+ * \"Software\") is an Unsupported proprietary work of Synopsys, Inc. unless\n+ * otherwise expressly agreed to in writing between Synopsys and you.\n+ *\n+ * The Software IS NOT an item of Licensed Software or Licensed Product under\n+ * any End User Software License Agreement or Agreement for Licensed Product\n+ * with Synopsys or any supplement thereto. You are permitted to use and\n+ * redistribute this Software in source and binary forms, with or without\n+ * modification, provided that redistributions of source code must retain this\n+ * notice. You may not view, use, disclose, copy or distribute this file or\n+ * any information contained herein except pursuant to this license grant from\n+ * Synopsys. If you do not agree with this notice, including the disclaimer\n+ * below, then you are not authorized to use the Software.\n+ *\n+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN \"AS IS\" BASIS\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,\n+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH\n+ * DAMAGE.\n+ * ========================================================================== */\n+#ifndef DWC_DEVICE_ONLY\n+\n+#include \"dwc_otg_hcd.h\"\n+#include \"dwc_otg_regs.h\"\n+\n+#include <linux/jiffies.h>\n+#ifdef CONFIG_ARM\n+#include <asm/fiq.h>\n+#endif\n+\n+extern bool microframe_schedule;\n+\n+/** @file\n+ * This file contains the implementation of the HCD Interrupt handlers.\n+ */\n+\n+int fiq_done, int_done;\n+\n+#ifdef FIQ_DEBUG\n+char buffer[1000*16];\n+int wptr;\n+void notrace _fiq_print(FIQDBG_T dbg_lvl, char *fmt, ...)\n+{\n+\tFIQDBG_T dbg_lvl_req = FIQDBG_PORTHUB;\n+\tva_list args;\n+\tchar text[17];\n+\thfnum_data_t hfnum = { .d32 = FIQ_READ(dwc_regs_base + 0x408) };\n+\n+\tif(dbg_lvl & dbg_lvl_req || dbg_lvl == FIQDBG_ERR)\n+\t{\n+\t\tlocal_fiq_disable();\n+\t\tsnprintf(text, 9, \"%4d%d:%d \", hfnum.b.frnum/8, hfnum.b.frnum%8, 8 - hfnum.b.frrem/937);\n+\t\tva_start(args, fmt);\n+\t\tvsnprintf(text+8, 9, fmt, args);\n+\t\tva_end(args);\n+\n+\t\tmemcpy(buffer + wptr, text, 16);\n+\t\twptr = (wptr + 16) % sizeof(buffer);\n+\t\tlocal_fiq_enable();\n+\t}\n+}\n+#endif\n+\n+/** This function handles interrupts for the HCD. */\n+int32_t dwc_otg_hcd_handle_intr(dwc_otg_hcd_t * dwc_otg_hcd)\n+{\n+\tint retval = 0;\n+\tstatic int last_time;\n+\tdwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;\n+\tgintsts_data_t gintsts;\n+\tgintmsk_data_t gintmsk;\n+\thfnum_data_t hfnum;\n+\thaintmsk_data_t haintmsk;\n+\n+#ifdef DEBUG\n+\tdwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;\n+\n+#endif\n+\n+\tgintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts);\n+\tgintmsk.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintmsk);\n+\n+\t/* Exit from ISR if core is hibernated */\n+\tif (core_if->hibernation_suspend == 1) {\n+\t\tgoto exit_handler_routine;\n+\t}\n+\tDWC_SPINLOCK(dwc_otg_hcd->lock);\n+\t/* Check if HOST Mode */\n+\tif (dwc_otg_is_host_mode(core_if)) {\n+\t\tif (fiq_enable) {\n+\t\t\tlocal_fiq_disable();\n+\t\t\tfiq_fsm_spin_lock(&dwc_otg_hcd->fiq_state->lock);\n+\t\t\t/* Pull in from the FIQ's disabled mask */\n+\t\t\tgintmsk.d32 = gintmsk.d32 | ~(dwc_otg_hcd->fiq_state->gintmsk_saved.d32);\n+\t\t\tdwc_otg_hcd->fiq_state->gintmsk_saved.d32 = ~0;\n+\t\t}\n+\n+\t\tif (fiq_fsm_enable && ( 0x0000FFFF & ~(dwc_otg_hcd->fiq_state->haintmsk_saved.b2.chint))) {\n+\t\t\tgintsts.b.hcintr = 1;\n+\t\t}\n+\n+\t\t/* Danger will robinson: fake a SOF if necessary */\n+\t\tif (fiq_fsm_enable && (dwc_otg_hcd->fiq_state->gintmsk_saved.b.sofintr == 1)) {\n+\t\t\tgintsts.b.sofintr = 1;\n+\t\t}\n+\t\tgintsts.d32 &= gintmsk.d32;\n+\n+\t\tif (fiq_enable) {\n+\t\t\tfiq_fsm_spin_unlock(&dwc_otg_hcd->fiq_state->lock);\n+\t\t\tlocal_fiq_enable();\n+\t\t}\n+\n+\t\tif (!gintsts.d32) {\n+\t\t\tgoto exit_handler_routine;\n+\t\t}\n+\n+#ifdef DEBUG\n+\t\t// We should be OK doing this because the common interrupts should already have been serviced\n+\t\t/* Don't print debug message in the interrupt handler on SOF */\n+#ifndef DEBUG_SOF\n+\t\tif (gintsts.d32 != DWC_SOF_INTR_MASK)\n+#endif\n+\t\t\tDWC_DEBUGPL(DBG_HCDI, \"\\n\");\n+#endif\n+\n+#ifdef DEBUG\n+#ifndef DEBUG_SOF\n+\t\tif (gintsts.d32 != DWC_SOF_INTR_MASK)\n+#endif\n+\t\t\tDWC_DEBUGPL(DBG_HCDI,\n+\t\t\t\t    \"DWC OTG HCD Interrupt Detected gintsts&gintmsk=0x%08x core_if=%p\\n\",\n+\t\t\t\t    gintsts.d32, core_if);\n+#endif\n+\t\thfnum.d32 = DWC_READ_REG32(&dwc_otg_hcd->core_if->host_if->host_global_regs->hfnum);\n+\t\tif (gintsts.b.sofintr) {\n+\t\t\tretval |= dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd);\n+\t\t}\n+\n+\t\tif (gintsts.b.rxstsqlvl) {\n+\t\t\tretval |=\n+\t\t\t    dwc_otg_hcd_handle_rx_status_q_level_intr\n+\t\t\t    (dwc_otg_hcd);\n+\t\t}\n+\t\tif (gintsts.b.nptxfempty) {\n+\t\t\tretval |=\n+\t\t\t    dwc_otg_hcd_handle_np_tx_fifo_empty_intr\n+\t\t\t    (dwc_otg_hcd);\n+\t\t}\n+\t\tif (gintsts.b.i2cintr) {\n+\t\t\t/** @todo Implement i2cintr handler. */\n+\t\t}\n+\t\tif (gintsts.b.portintr) {\n+\n+\t\t\tgintmsk_data_t gintmsk = { .b.portintr = 1};\n+\t\t\tretval |= dwc_otg_hcd_handle_port_intr(dwc_otg_hcd);\n+\t\t\tif (fiq_enable) {\n+\t\t\t\tlocal_fiq_disable();\n+\t\t\t\tfiq_fsm_spin_lock(&dwc_otg_hcd->fiq_state->lock);\n+\t\t\t\tDWC_MODIFY_REG32(&dwc_otg_hcd->core_if->core_global_regs->gintmsk, 0, gintmsk.d32);\n+\t\t\t\tfiq_fsm_spin_unlock(&dwc_otg_hcd->fiq_state->lock);\n+\t\t\t\tlocal_fiq_enable();\n+\t\t\t} else {\n+\t\t\t\tDWC_MODIFY_REG32(&dwc_otg_hcd->core_if->core_global_regs->gintmsk, 0, gintmsk.d32);\n+\t\t\t}\n+\t\t}\n+\t\tif (gintsts.b.hcintr) {\n+\t\t\tretval |= dwc_otg_hcd_handle_hc_intr(dwc_otg_hcd);\n+\t\t}\n+\t\tif (gintsts.b.ptxfempty) {\n+\t\t\tretval |=\n+\t\t\t    dwc_otg_hcd_handle_perio_tx_fifo_empty_intr\n+\t\t\t    (dwc_otg_hcd);\n+\t\t}\n+#ifdef DEBUG\n+#ifndef DEBUG_SOF\n+\t\tif (gintsts.d32 != DWC_SOF_INTR_MASK)\n+#endif\n+\t\t{\n+\t\t\tDWC_DEBUGPL(DBG_HCDI,\n+\t\t\t\t    \"DWC OTG HCD Finished Servicing Interrupts\\n\");\n+\t\t\tDWC_DEBUGPL(DBG_HCDV, \"DWC OTG HCD gintsts=0x%08x\\n\",\n+\t\t\t\t    DWC_READ_REG32(&global_regs->gintsts));\n+\t\t\tDWC_DEBUGPL(DBG_HCDV, \"DWC OTG HCD gintmsk=0x%08x\\n\",\n+\t\t\t\t    DWC_READ_REG32(&global_regs->gintmsk));\n+\t\t}\n+#endif\n+\n+#ifdef DEBUG\n+#ifndef DEBUG_SOF\n+\t\tif (gintsts.d32 != DWC_SOF_INTR_MASK)\n+#endif\n+\t\t\tDWC_DEBUGPL(DBG_HCDI, \"\\n\");\n+#endif\n+\n+\t}\n+\n+exit_handler_routine:\n+\tif (fiq_enable)\t{\n+\t\tgintmsk_data_t gintmsk_new;\n+\t\thaintmsk_data_t haintmsk_new;\n+\t\tlocal_fiq_disable();\n+\t\tfiq_fsm_spin_lock(&dwc_otg_hcd->fiq_state->lock);\n+\t\tgintmsk_new.d32 = *(volatile uint32_t *)&dwc_otg_hcd->fiq_state->gintmsk_saved.d32;\n+\t\tif(fiq_fsm_enable)\n+\t\t\thaintmsk_new.d32 = *(volatile uint32_t *)&dwc_otg_hcd->fiq_state->haintmsk_saved.d32;\n+\t\telse\n+\t\t\thaintmsk_new.d32 = 0x0000FFFF;\n+\n+\t\t/* The FIQ could have sneaked another interrupt in. If so, don't clear MPHI */\n+\t\tif ((gintmsk_new.d32 == ~0) && (haintmsk_new.d32 == 0x0000FFFF)) {\n+\t\t\tif (dwc_otg_hcd->fiq_state->mphi_regs.swirq_clr) {\n+\t\t\t\tDWC_WRITE_REG32(dwc_otg_hcd->fiq_state->mphi_regs.swirq_clr, 1);\n+\t\t\t} else {\n+\t\t\t\tDWC_WRITE_REG32(dwc_otg_hcd->fiq_state->mphi_regs.intstat, (1<<16));\n+\t\t\t}\n+\t\t\tif (dwc_otg_hcd->fiq_state->mphi_int_count >= 50) {\n+\t\t\t\tfiq_print(FIQDBG_INT, dwc_otg_hcd->fiq_state, \"MPHI CLR\");\n+\t\t\t\t\tDWC_WRITE_REG32(dwc_otg_hcd->fiq_state->mphi_regs.ctrl, ((1<<31) + (1<<16)));\n+\t\t\t\t\twhile (!(DWC_READ_REG32(dwc_otg_hcd->fiq_state->mphi_regs.ctrl) & (1 << 17)))\n+\t\t\t\t\t\t;\n+\t\t\t\t\tDWC_WRITE_REG32(dwc_otg_hcd->fiq_state->mphi_regs.ctrl, (1<<31));\n+\t\t\t\t\tdwc_otg_hcd->fiq_state->mphi_int_count = 0;\n+\t\t\t}\n+\t\t\tint_done++;\n+\t\t}\n+\t\thaintmsk.d32 = DWC_READ_REG32(&core_if->host_if->host_global_regs->haintmsk);\n+\t\t/* Re-enable interrupts that the FIQ masked (first time round) */\n+\t\tFIQ_WRITE(dwc_otg_hcd->fiq_state->dwc_regs_base + GINTMSK, gintmsk.d32);\n+\t\tfiq_fsm_spin_unlock(&dwc_otg_hcd->fiq_state->lock);\n+\t\tlocal_fiq_enable();\n+\n+\t\tif ((jiffies / HZ) > last_time) {\n+\t\t\t//dwc_otg_qh_t *qh;\n+\t\t\t//dwc_list_link_t *cur;\n+\t\t\t/* Once a second output the fiq and irq numbers, useful for debug */\n+\t\t\tlast_time = jiffies / HZ;\n+\t\t//\t DWC_WARN(\"np_kick=%d AHC=%d sched_frame=%d cur_frame=%d int_done=%d fiq_done=%d\",\n+\t\t//\tdwc_otg_hcd->fiq_state->kick_np_queues, dwc_otg_hcd->available_host_channels,\n+\t\t//\tdwc_otg_hcd->fiq_state->next_sched_frame, hfnum.b.frnum, int_done, dwc_otg_hcd->fiq_state->fiq_done);\n+\t\t\t //printk(KERN_WARNING \"Periodic queues:\\n\");\n+\t\t}\n+\t}\n+\n+\tDWC_SPINUNLOCK(dwc_otg_hcd->lock);\n+\treturn retval;\n+}\n+\n+#ifdef DWC_TRACK_MISSED_SOFS\n+\n+#warning Compiling code to track missed SOFs\n+#define FRAME_NUM_ARRAY_SIZE 1000\n+/**\n+ * This function is for debug only.\n+ */\n+static inline void track_missed_sofs(uint16_t curr_frame_number)\n+{\n+\tstatic uint16_t frame_num_array[FRAME_NUM_ARRAY_SIZE];\n+\tstatic uint16_t last_frame_num_array[FRAME_NUM_ARRAY_SIZE];\n+\tstatic int frame_num_idx = 0;\n+\tstatic uint16_t last_frame_num = DWC_HFNUM_MAX_FRNUM;\n+\tstatic int dumped_frame_num_array = 0;\n+\n+\tif (frame_num_idx < FRAME_NUM_ARRAY_SIZE) {\n+\t\tif (((last_frame_num + 1) & DWC_HFNUM_MAX_FRNUM) !=\n+\t\t    curr_frame_number) {\n+\t\t\tframe_num_array[frame_num_idx] = curr_frame_number;\n+\t\t\tlast_frame_num_array[frame_num_idx++] = last_frame_num;\n+\t\t}\n+\t} else if (!dumped_frame_num_array) {\n+\t\tint i;\n+\t\tDWC_PRINTF(\"Frame     Last Frame\\n\");\n+\t\tDWC_PRINTF(\"-----     ----------\\n\");\n+\t\tfor (i = 0; i < FRAME_NUM_ARRAY_SIZE; i++) {\n+\t\t\tDWC_PRINTF(\"0x%04x    0x%04x\\n\",\n+\t\t\t\t   frame_num_array[i], last_frame_num_array[i]);\n+\t\t}\n+\t\tdumped_frame_num_array = 1;\n+\t}\n+\tlast_frame_num = curr_frame_number;\n+}\n+#endif\n+\n+/**\n+ * Handles the start-of-frame interrupt in host mode. Non-periodic\n+ * transactions may be queued to the DWC_otg controller for the current\n+ * (micro)frame. Periodic transactions may be queued to the controller for the\n+ * next (micro)frame.\n+ */\n+int32_t dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd_t * hcd)\n+{\n+\thfnum_data_t hfnum;\n+\tgintsts_data_t gintsts = { .d32 = 0 };\n+\tdwc_list_link_t *qh_entry;\n+\tdwc_otg_qh_t *qh;\n+\tdwc_otg_transaction_type_e tr_type;\n+\tint did_something = 0;\n+\tint32_t next_sched_frame = -1;\n+\n+\thfnum.d32 =\n+\t    DWC_READ_REG32(&hcd->core_if->host_if->host_global_regs->hfnum);\n+\n+#ifdef DEBUG_SOF\n+\tDWC_DEBUGPL(DBG_HCD, \"--Start of Frame Interrupt--\\n\");\n+#endif\n+\thcd->frame_number = hfnum.b.frnum;\n+\n+#ifdef DEBUG\n+\thcd->frrem_accum += hfnum.b.frrem;\n+\thcd->frrem_samples++;\n+#endif\n+\n+#ifdef DWC_TRACK_MISSED_SOFS\n+\ttrack_missed_sofs(hcd->frame_number);\n+#endif\n+\t/* Determine whether any periodic QHs should be executed. */\n+\tqh_entry = DWC_LIST_FIRST(&hcd->periodic_sched_inactive);\n+\twhile (qh_entry != &hcd->periodic_sched_inactive) {\n+\t\tqh = DWC_LIST_ENTRY(qh_entry, dwc_otg_qh_t, qh_list_entry);\n+\t\tqh_entry = qh_entry->next;\n+\t\tif (dwc_frame_num_le(qh->sched_frame, hcd->frame_number)) {\n+\n+\t\t\t/*\n+\t\t\t * Move QH to the ready list to be executed next\n+\t\t\t * (micro)frame.\n+\t\t\t */\n+\t\t\tDWC_LIST_MOVE_HEAD(&hcd->periodic_sched_ready,\n+\t\t\t\t\t   &qh->qh_list_entry);\n+\n+\t\t\tdid_something = 1;\n+\t\t}\n+\t\telse\n+\t\t{\n+\t\t\tif(next_sched_frame < 0 || dwc_frame_num_le(qh->sched_frame, next_sched_frame))\n+\t\t\t{\n+\t\t\t\tnext_sched_frame = qh->sched_frame;\n+\t\t\t}\n+\t\t}\n+\t}\n+\tif (fiq_enable)\n+\t\thcd->fiq_state->next_sched_frame = next_sched_frame;\n+\n+\ttr_type = dwc_otg_hcd_select_transactions(hcd);\n+\tif (tr_type != DWC_OTG_TRANSACTION_NONE) {\n+\t\tdwc_otg_hcd_queue_transactions(hcd, tr_type);\n+\t\tdid_something = 1;\n+\t}\n+\n+\t/* Clear interrupt - but do not trample on the FIQ sof */\n+\tif (!fiq_fsm_enable) {\n+\t\tgintsts.b.sofintr = 1;\n+\t\tDWC_WRITE_REG32(&hcd->core_if->core_global_regs->gintsts, gintsts.d32);\n+\t}\n+\treturn 1;\n+}\n+\n+/** Handles the Rx Status Queue Level Interrupt, which indicates that there is at\n+ * least one packet in the Rx FIFO.  The packets are moved from the FIFO to\n+ * memory if the DWC_otg controller is operating in Slave mode. */\n+int32_t dwc_otg_hcd_handle_rx_status_q_level_intr(dwc_otg_hcd_t * dwc_otg_hcd)\n+{\n+\thost_grxsts_data_t grxsts;\n+\tdwc_hc_t *hc = NULL;\n+\n+\tDWC_DEBUGPL(DBG_HCD, \"--RxStsQ Level Interrupt--\\n\");\n+\n+\tgrxsts.d32 =\n+\t    DWC_READ_REG32(&dwc_otg_hcd->core_if->core_global_regs->grxstsp);\n+\n+\thc = dwc_otg_hcd->hc_ptr_array[grxsts.b.chnum];\n+\tif (!hc) {\n+\t\tDWC_ERROR(\"Unable to get corresponding channel\\n\");\n+\t\treturn 0;\n+\t}\n+\n+\t/* Packet Status */\n+\tDWC_DEBUGPL(DBG_HCDV, \"    Ch num = %d\\n\", grxsts.b.chnum);\n+\tDWC_DEBUGPL(DBG_HCDV, \"    Count = %d\\n\", grxsts.b.bcnt);\n+\tDWC_DEBUGPL(DBG_HCDV, \"    DPID = %d, hc.dpid = %d\\n\", grxsts.b.dpid,\n+\t\t    hc->data_pid_start);\n+\tDWC_DEBUGPL(DBG_HCDV, \"    PStatus = %d\\n\", grxsts.b.pktsts);\n+\n+\tswitch (grxsts.b.pktsts) {\n+\tcase DWC_GRXSTS_PKTSTS_IN:\n+\t\t/* Read the data into the host buffer. */\n+\t\tif (grxsts.b.bcnt > 0) {\n+\t\t\tdwc_otg_read_packet(dwc_otg_hcd->core_if,\n+\t\t\t\t\t    hc->xfer_buff, grxsts.b.bcnt);\n+\n+\t\t\t/* Update the HC fields for the next packet received. */\n+\t\t\thc->xfer_count += grxsts.b.bcnt;\n+\t\t\thc->xfer_buff += grxsts.b.bcnt;\n+\t\t}\n+\n+\tcase DWC_GRXSTS_PKTSTS_IN_XFER_COMP:\n+\tcase DWC_GRXSTS_PKTSTS_DATA_TOGGLE_ERR:\n+\tcase DWC_GRXSTS_PKTSTS_CH_HALTED:\n+\t\t/* Handled in interrupt, just ignore data */\n+\t\tbreak;\n+\tdefault:\n+\t\tDWC_ERROR(\"RX_STS_Q Interrupt: Unknown status %d\\n\",\n+\t\t\t  grxsts.b.pktsts);\n+\t\tbreak;\n+\t}\n+\n+\treturn 1;\n+}\n+\n+/** This interrupt occurs when the non-periodic Tx FIFO is half-empty. More\n+ * data packets may be written to the FIFO for OUT transfers. More requests\n+ * may be written to the non-periodic request queue for IN transfers. This\n+ * interrupt is enabled only in Slave mode. */\n+int32_t dwc_otg_hcd_handle_np_tx_fifo_empty_intr(dwc_otg_hcd_t * dwc_otg_hcd)\n+{\n+\tDWC_DEBUGPL(DBG_HCD, \"--Non-Periodic TxFIFO Empty Interrupt--\\n\");\n+\tdwc_otg_hcd_queue_transactions(dwc_otg_hcd,\n+\t\t\t\t       DWC_OTG_TRANSACTION_NON_PERIODIC);\n+\treturn 1;\n+}\n+\n+/** This interrupt occurs when the periodic Tx FIFO is half-empty. More data\n+ * packets may be written to the FIFO for OUT transfers. More requests may be\n+ * written to the periodic request queue for IN transfers. This interrupt is\n+ * enabled only in Slave mode. */\n+int32_t dwc_otg_hcd_handle_perio_tx_fifo_empty_intr(dwc_otg_hcd_t * dwc_otg_hcd)\n+{\n+\tDWC_DEBUGPL(DBG_HCD, \"--Periodic TxFIFO Empty Interrupt--\\n\");\n+\tdwc_otg_hcd_queue_transactions(dwc_otg_hcd,\n+\t\t\t\t       DWC_OTG_TRANSACTION_PERIODIC);\n+\treturn 1;\n+}\n+\n+/** There are multiple conditions that can cause a port interrupt. This function\n+ * determines which interrupt conditions have occurred and handles them\n+ * appropriately. */\n+int32_t dwc_otg_hcd_handle_port_intr(dwc_otg_hcd_t * dwc_otg_hcd)\n+{\n+\tint retval = 0;\n+\thprt0_data_t hprt0;\n+\thprt0_data_t hprt0_modify;\n+\n+\thprt0.d32 = DWC_READ_REG32(dwc_otg_hcd->core_if->host_if->hprt0);\n+\thprt0_modify.d32 = DWC_READ_REG32(dwc_otg_hcd->core_if->host_if->hprt0);\n+\n+\t/* Clear appropriate bits in HPRT0 to clear the interrupt bit in\n+\t * GINTSTS */\n+\n+\thprt0_modify.b.prtena = 0;\n+\thprt0_modify.b.prtconndet = 0;\n+\thprt0_modify.b.prtenchng = 0;\n+\thprt0_modify.b.prtovrcurrchng = 0;\n+\n+\t/* Port Connect Detected\n+\t * Set flag and clear if detected */\n+\tif (dwc_otg_hcd->core_if->hibernation_suspend == 1) {\n+\t\t// Dont modify port status if we are in hibernation state\n+\t\thprt0_modify.b.prtconndet = 1;\n+\t\thprt0_modify.b.prtenchng = 1;\n+\t\tDWC_WRITE_REG32(dwc_otg_hcd->core_if->host_if->hprt0, hprt0_modify.d32);\n+\t\thprt0.d32 = DWC_READ_REG32(dwc_otg_hcd->core_if->host_if->hprt0);\n+\t\treturn retval;\n+\t}\n+\n+\tif (hprt0.b.prtconndet) {\n+\t\t/** @todo - check if steps performed in 'else' block should be perfromed regardles adp */\n+\t\tif (dwc_otg_hcd->core_if->adp_enable &&\n+\t\t\t\tdwc_otg_hcd->core_if->adp.vbuson_timer_started == 1) {\n+\t\t\tDWC_PRINTF(\"PORT CONNECT DETECTED ----------------\\n\");\n+\t\t\tDWC_TIMER_CANCEL(dwc_otg_hcd->core_if->adp.vbuson_timer);\n+\t\t\tdwc_otg_hcd->core_if->adp.vbuson_timer_started = 0;\n+\t\t\t/* TODO - check if this is required, as\n+\t\t\t * host initialization was already performed\n+\t\t\t * after initial ADP probing\n+\t\t\t */\n+\t\t\t/*dwc_otg_hcd->core_if->adp.vbuson_timer_started = 0;\n+\t\t\tdwc_otg_core_init(dwc_otg_hcd->core_if);\n+\t\t\tdwc_otg_enable_global_interrupts(dwc_otg_hcd->core_if);\n+\t\t\tcil_hcd_start(dwc_otg_hcd->core_if);*/\n+\t\t} else {\n+\n+\t\t\tDWC_DEBUGPL(DBG_HCD, \"--Port Interrupt HPRT0=0x%08x \"\n+\t\t\t\t    \"Port Connect Detected--\\n\", hprt0.d32);\n+\t\t\tdwc_otg_hcd->flags.b.port_connect_status_change = 1;\n+\t\t\tdwc_otg_hcd->flags.b.port_connect_status = 1;\n+\t\t\thprt0_modify.b.prtconndet = 1;\n+\n+\t\t\t/* B-Device has connected, Delete the connection timer. */\n+\t\t\tDWC_TIMER_CANCEL(dwc_otg_hcd->conn_timer);\n+\t\t}\n+\t\t/* The Hub driver asserts a reset when it sees port connect\n+\t\t * status change flag */\n+\t\tretval |= 1;\n+\t}\n+\n+\t/* Port Enable Changed\n+\t * Clear if detected - Set internal flag if disabled */\n+\tif (hprt0.b.prtenchng) {\n+\t\tDWC_DEBUGPL(DBG_HCD, \"  --Port Interrupt HPRT0=0x%08x \"\n+\t\t\t    \"Port Enable Changed--\\n\", hprt0.d32);\n+\t\thprt0_modify.b.prtenchng = 1;\n+\t\tif (hprt0.b.prtena == 1) {\n+\t\t\thfir_data_t hfir;\n+\t\t\tint do_reset = 0;\n+\t\t\tdwc_otg_core_params_t *params =\n+\t\t\t    dwc_otg_hcd->core_if->core_params;\n+\t\t\tdwc_otg_core_global_regs_t *global_regs =\n+\t\t\t    dwc_otg_hcd->core_if->core_global_regs;\n+\t\t\tdwc_otg_host_if_t *host_if =\n+\t\t\t    dwc_otg_hcd->core_if->host_if;\n+\n+\t\t\tdwc_otg_hcd->flags.b.port_speed = hprt0.b.prtspd;\n+\t\t\tif (microframe_schedule)\n+\t\t\t\tinit_hcd_usecs(dwc_otg_hcd);\n+\n+\t\t\t/* Every time when port enables calculate\n+\t\t\t * HFIR.FrInterval\n+\t\t\t */\n+\t\t\thfir.d32 = DWC_READ_REG32(&host_if->host_global_regs->hfir);\n+\t\t\thfir.b.frint = calc_frame_interval(dwc_otg_hcd->core_if);\n+\t\t\tDWC_WRITE_REG32(&host_if->host_global_regs->hfir, hfir.d32);\n+\n+\t\t\t/* Check if we need to adjust the PHY clock speed for\n+\t\t\t * low power and adjust it */\n+\t\t\tif (params->host_support_fs_ls_low_power) {\n+\t\t\t\tgusbcfg_data_t usbcfg;\n+\n+\t\t\t\tusbcfg.d32 =\n+\t\t\t\t    DWC_READ_REG32(&global_regs->gusbcfg);\n+\n+\t\t\t\tif (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_LOW_SPEED\n+\t\t\t\t    || hprt0.b.prtspd ==\n+\t\t\t\t    DWC_HPRT0_PRTSPD_FULL_SPEED) {\n+\t\t\t\t\t/*\n+\t\t\t\t\t * Low power\n+\t\t\t\t\t */\n+\t\t\t\t\thcfg_data_t hcfg;\n+\t\t\t\t\tif (usbcfg.b.phylpwrclksel == 0) {\n+\t\t\t\t\t\t/* Set PHY low power clock select for FS/LS devices */\n+\t\t\t\t\t\tusbcfg.b.phylpwrclksel = 1;\n+\t\t\t\t\t\tDWC_WRITE_REG32\n+\t\t\t\t\t\t    (&global_regs->gusbcfg,\n+\t\t\t\t\t\t     usbcfg.d32);\n+\t\t\t\t\t\tdo_reset = 1;\n+\t\t\t\t\t}\n+\n+\t\t\t\t\thcfg.d32 =\n+\t\t\t\t\t    DWC_READ_REG32\n+\t\t\t\t\t    (&host_if->host_global_regs->hcfg);\n+\n+\t\t\t\t\tif (hprt0.b.prtspd ==\n+\t\t\t\t\t    DWC_HPRT0_PRTSPD_LOW_SPEED\n+\t\t\t\t\t    && params->host_ls_low_power_phy_clk\n+\t\t\t\t\t    ==\n+\t\t\t\t\t    DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ)\n+\t\t\t\t\t{\n+\t\t\t\t\t\t/* 6 MHZ */\n+\t\t\t\t\t\tDWC_DEBUGPL(DBG_CIL,\n+\t\t\t\t\t\t\t    \"FS_PHY programming HCFG to 6 MHz (Low Power)\\n\");\n+\t\t\t\t\t\tif (hcfg.b.fslspclksel !=\n+\t\t\t\t\t\t    DWC_HCFG_6_MHZ) {\n+\t\t\t\t\t\t\thcfg.b.fslspclksel =\n+\t\t\t\t\t\t\t    DWC_HCFG_6_MHZ;\n+\t\t\t\t\t\t\tDWC_WRITE_REG32\n+\t\t\t\t\t\t\t    (&host_if->host_global_regs->hcfg,\n+\t\t\t\t\t\t\t     hcfg.d32);\n+\t\t\t\t\t\t\tdo_reset = 1;\n+\t\t\t\t\t\t}\n+\t\t\t\t\t} else {\n+\t\t\t\t\t\t/* 48 MHZ */\n+\t\t\t\t\t\tDWC_DEBUGPL(DBG_CIL,\n+\t\t\t\t\t\t\t    \"FS_PHY programming HCFG to 48 MHz ()\\n\");\n+\t\t\t\t\t\tif (hcfg.b.fslspclksel !=\n+\t\t\t\t\t\t    DWC_HCFG_48_MHZ) {\n+\t\t\t\t\t\t\thcfg.b.fslspclksel =\n+\t\t\t\t\t\t\t    DWC_HCFG_48_MHZ;\n+\t\t\t\t\t\t\tDWC_WRITE_REG32\n+\t\t\t\t\t\t\t    (&host_if->host_global_regs->hcfg,\n+\t\t\t\t\t\t\t     hcfg.d32);\n+\t\t\t\t\t\t\tdo_reset = 1;\n+\t\t\t\t\t\t}\n+\t\t\t\t\t}\n+\t\t\t\t} else {\n+\t\t\t\t\t/*\n+\t\t\t\t\t * Not low power\n+\t\t\t\t\t */\n+\t\t\t\t\tif (usbcfg.b.phylpwrclksel == 1) {\n+\t\t\t\t\t\tusbcfg.b.phylpwrclksel = 0;\n+\t\t\t\t\t\tDWC_WRITE_REG32\n+\t\t\t\t\t\t    (&global_regs->gusbcfg,\n+\t\t\t\t\t\t     usbcfg.d32);\n+\t\t\t\t\t\tdo_reset = 1;\n+\t\t\t\t\t}\n+\t\t\t\t}\n+\n+\t\t\t\tif (do_reset) {\n+\t\t\t\t\tDWC_TASK_SCHEDULE(dwc_otg_hcd->reset_tasklet);\n+\t\t\t\t}\n+\t\t\t}\n+\n+\t\t\tif (!do_reset) {\n+\t\t\t\t/* Port has been enabled set the reset change flag */\n+\t\t\t\tdwc_otg_hcd->flags.b.port_reset_change = 1;\n+\t\t\t}\n+\t\t} else {\n+\t\t\tdwc_otg_hcd->flags.b.port_enable_change = 1;\n+\t\t}\n+\t\tretval |= 1;\n+\t}\n+\n+\t/** Overcurrent Change Interrupt */\n+\tif (hprt0.b.prtovrcurrchng) {\n+\t\tDWC_DEBUGPL(DBG_HCD, \"  --Port Interrupt HPRT0=0x%08x \"\n+\t\t\t    \"Port Overcurrent Changed--\\n\", hprt0.d32);\n+\t\tdwc_otg_hcd->flags.b.port_over_current_change = 1;\n+\t\thprt0_modify.b.prtovrcurrchng = 1;\n+\t\tretval |= 1;\n+\t}\n+\n+\t/* Clear Port Interrupts */\n+\tDWC_WRITE_REG32(dwc_otg_hcd->core_if->host_if->hprt0, hprt0_modify.d32);\n+\n+\treturn retval;\n+}\n+\n+/** This interrupt indicates that one or more host channels has a pending\n+ * interrupt. There are multiple conditions that can cause each host channel\n+ * interrupt. This function determines which conditions have occurred for each\n+ * host channel interrupt and handles them appropriately. */\n+int32_t dwc_otg_hcd_handle_hc_intr(dwc_otg_hcd_t * dwc_otg_hcd)\n+{\n+\tint i;\n+\tint retval = 0;\n+\thaint_data_t haint = { .d32 = 0 } ;\n+\n+\t/* Clear appropriate bits in HCINTn to clear the interrupt bit in\n+\t * GINTSTS */\n+\n+\tif (!fiq_fsm_enable)\n+\t\thaint.d32 = dwc_otg_read_host_all_channels_intr(dwc_otg_hcd->core_if);\n+\n+\t// Overwrite with saved interrupts from fiq handler\n+\tif(fiq_fsm_enable)\n+\t{\n+\t\t/* check the mask? */\n+\t\tlocal_fiq_disable();\n+\t\tfiq_fsm_spin_lock(&dwc_otg_hcd->fiq_state->lock);\n+\t\thaint.b2.chint |= ~(dwc_otg_hcd->fiq_state->haintmsk_saved.b2.chint);\n+\t\tdwc_otg_hcd->fiq_state->haintmsk_saved.b2.chint = ~0;\n+\t\tfiq_fsm_spin_unlock(&dwc_otg_hcd->fiq_state->lock);\n+\t\tlocal_fiq_enable();\n+\t}\n+\n+\tfor (i = 0; i < dwc_otg_hcd->core_if->core_params->host_channels; i++) {\n+\t\tif (haint.b2.chint & (1 << i)) {\n+\t\t\tretval |= dwc_otg_hcd_handle_hc_n_intr(dwc_otg_hcd, i);\n+\t\t}\n+\t}\n+\n+\treturn retval;\n+}\n+\n+/**\n+ * Gets the actual length of a transfer after the transfer halts. _halt_status\n+ * holds the reason for the halt.\n+ *\n+ * For IN transfers where halt_status is DWC_OTG_HC_XFER_COMPLETE,\n+ * *short_read is set to 1 upon return if less than the requested\n+ * number of bytes were transferred. Otherwise, *short_read is set to 0 upon\n+ * return. short_read may also be NULL on entry, in which case it remains\n+ * unchanged.\n+ */\n+static uint32_t get_actual_xfer_length(dwc_hc_t * hc,\n+\t\t\t\t       dwc_otg_hc_regs_t * hc_regs,\n+\t\t\t\t       dwc_otg_qtd_t * qtd,\n+\t\t\t\t       dwc_otg_halt_status_e halt_status,\n+\t\t\t\t       int *short_read)\n+{\n+\thctsiz_data_t hctsiz;\n+\tuint32_t length;\n+\n+\tif (short_read != NULL) {\n+\t\t*short_read = 0;\n+\t}\n+\thctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);\n+\n+\tif (halt_status == DWC_OTG_HC_XFER_COMPLETE) {\n+\t\tif (hc->ep_is_in) {\n+\t\t\tlength = hc->xfer_len - hctsiz.b.xfersize;\n+\t\t\tif (short_read != NULL) {\n+\t\t\t\t*short_read = (hctsiz.b.xfersize != 0);\n+\t\t\t}\n+\t\t} else if (hc->qh->do_split) {\n+\t\t\t\t//length = split_out_xfersize[hc->hc_num];\n+\t\t\t\tlength = qtd->ssplit_out_xfer_count;\n+\t\t} else {\n+\t\t\tlength = hc->xfer_len;\n+\t\t}\n+\t} else {\n+\t\t/*\n+\t\t * Must use the hctsiz.pktcnt field to determine how much data\n+\t\t * has been transferred. This field reflects the number of\n+\t\t * packets that have been transferred via the USB. This is\n+\t\t * always an integral number of packets if the transfer was\n+\t\t * halted before its normal completion. (Can't use the\n+\t\t * hctsiz.xfersize field because that reflects the number of\n+\t\t * bytes transferred via the AHB, not the USB).\n+\t\t */\n+\t\tlength =\n+\t\t    (hc->start_pkt_count - hctsiz.b.pktcnt) * hc->max_packet;\n+\t}\n+\n+\treturn length;\n+}\n+\n+/**\n+ * Updates the state of the URB after a Transfer Complete interrupt on the\n+ * host channel. Updates the actual_length field of the URB based on the\n+ * number of bytes transferred via the host channel. Sets the URB status\n+ * if the data transfer is finished.\n+ *\n+ * @return 1 if the data transfer specified by the URB is completely finished,\n+ * 0 otherwise.\n+ */\n+static int update_urb_state_xfer_comp(dwc_hc_t * hc,\n+\t\t\t\t      dwc_otg_hc_regs_t * hc_regs,\n+\t\t\t\t      dwc_otg_hcd_urb_t * urb,\n+\t\t\t\t      dwc_otg_qtd_t * qtd)\n+{\n+\tint xfer_done = 0;\n+\tint short_read = 0;\n+\n+\tint xfer_length;\n+\n+\txfer_length = get_actual_xfer_length(hc, hc_regs, qtd,\n+\t\t\t\t\t     DWC_OTG_HC_XFER_COMPLETE,\n+\t\t\t\t\t     &short_read);\n+\n+\tif (urb->actual_length + xfer_length > urb->length) {\n+\t\tprintk_once(KERN_DEBUG \"dwc_otg: DEVICE:%03d : %s:%d:trimming xfer length\\n\",\n+\t\t\thc->dev_addr, __func__, __LINE__);\n+\t\txfer_length = urb->length - urb->actual_length;\n+\t}\n+\n+\t/* non DWORD-aligned buffer case handling. */\n+\tif (hc->align_buff && xfer_length && hc->ep_is_in) {\n+\t\tdwc_memcpy(urb->buf + urb->actual_length, hc->qh->dw_align_buf,\n+\t\t\t   xfer_length);\n+\t}\n+\n+\turb->actual_length += xfer_length;\n+\n+\tif (xfer_length && (hc->ep_type == DWC_OTG_EP_TYPE_BULK) &&\n+\t    (urb->flags & URB_SEND_ZERO_PACKET)\n+\t    && (urb->actual_length == urb->length)\n+\t    && !(urb->length % hc->max_packet)) {\n+\t\txfer_done = 0;\n+\t} else if (short_read || urb->actual_length >= urb->length) {\n+\t\txfer_done = 1;\n+\t\turb->status = 0;\n+\t}\n+\n+#ifdef DEBUG\n+\t{\n+\t\thctsiz_data_t hctsiz;\n+\t\thctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);\n+\t\tDWC_DEBUGPL(DBG_HCDV, \"DWC_otg: %s: %s, channel %d\\n\",\n+\t\t\t    __func__, (hc->ep_is_in ? \"IN\" : \"OUT\"),\n+\t\t\t    hc->hc_num);\n+\t\tDWC_DEBUGPL(DBG_HCDV, \"  hc->xfer_len %d\\n\", hc->xfer_len);\n+\t\tDWC_DEBUGPL(DBG_HCDV, \"  hctsiz.xfersize %d\\n\",\n+\t\t\t    hctsiz.b.xfersize);\n+\t\tDWC_DEBUGPL(DBG_HCDV, \"  urb->transfer_buffer_length %d\\n\",\n+\t\t\t    urb->length);\n+\t\tDWC_DEBUGPL(DBG_HCDV, \"  urb->actual_length %d\\n\",\n+\t\t\t    urb->actual_length);\n+\t\tDWC_DEBUGPL(DBG_HCDV, \"  short_read %d, xfer_done %d\\n\",\n+\t\t\t    short_read, xfer_done);\n+\t}\n+#endif\n+\n+\treturn xfer_done;\n+}\n+\n+/*\n+ * Save the starting data toggle for the next transfer. The data toggle is\n+ * saved in the QH for non-control transfers and it's saved in the QTD for\n+ * control transfers.\n+ */\n+void dwc_otg_hcd_save_data_toggle(dwc_hc_t * hc,\n+\t\t\t     dwc_otg_hc_regs_t * hc_regs, dwc_otg_qtd_t * qtd)\n+{\n+\thctsiz_data_t hctsiz;\n+\thctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);\n+\n+\tif (hc->ep_type != DWC_OTG_EP_TYPE_CONTROL) {\n+\t\tdwc_otg_qh_t *qh = hc->qh;\n+\t\tif (hctsiz.b.pid == DWC_HCTSIZ_DATA0) {\n+\t\t\tqh->data_toggle = DWC_OTG_HC_PID_DATA0;\n+\t\t} else {\n+\t\t\tqh->data_toggle = DWC_OTG_HC_PID_DATA1;\n+\t\t}\n+\t} else {\n+\t\tif (hctsiz.b.pid == DWC_HCTSIZ_DATA0) {\n+\t\t\tqtd->data_toggle = DWC_OTG_HC_PID_DATA0;\n+\t\t} else {\n+\t\t\tqtd->data_toggle = DWC_OTG_HC_PID_DATA1;\n+\t\t}\n+\t}\n+}\n+\n+/**\n+ * Updates the state of an Isochronous URB when the transfer is stopped for\n+ * any reason. The fields of the current entry in the frame descriptor array\n+ * are set based on the transfer state and the input _halt_status. Completes\n+ * the Isochronous URB if all the URB frames have been completed.\n+ *\n+ * @return DWC_OTG_HC_XFER_COMPLETE if there are more frames remaining to be\n+ * transferred in the URB. Otherwise return DWC_OTG_HC_XFER_URB_COMPLETE.\n+ */\n+static dwc_otg_halt_status_e\n+update_isoc_urb_state(dwc_otg_hcd_t * hcd,\n+\t\t      dwc_hc_t * hc,\n+\t\t      dwc_otg_hc_regs_t * hc_regs,\n+\t\t      dwc_otg_qtd_t * qtd, dwc_otg_halt_status_e halt_status)\n+{\n+\tdwc_otg_hcd_urb_t *urb = qtd->urb;\n+\tdwc_otg_halt_status_e ret_val = halt_status;\n+\tstruct dwc_otg_hcd_iso_packet_desc *frame_desc;\n+\n+\tframe_desc = &urb->iso_descs[qtd->isoc_frame_index];\n+\tswitch (halt_status) {\n+\tcase DWC_OTG_HC_XFER_COMPLETE:\n+\t\tframe_desc->status = 0;\n+\t\tframe_desc->actual_length =\n+\t\t    get_actual_xfer_length(hc, hc_regs, qtd, halt_status, NULL);\n+\n+\t\t/* non DWORD-aligned buffer case handling. */\n+\t\tif (hc->align_buff && frame_desc->actual_length && hc->ep_is_in) {\n+\t\t\tdwc_memcpy(urb->buf + frame_desc->offset + qtd->isoc_split_offset,\n+\t\t\t\t   hc->qh->dw_align_buf, frame_desc->actual_length);\n+\t\t}\n+\n+\t\tbreak;\n+\tcase DWC_OTG_HC_XFER_FRAME_OVERRUN:\n+\t\turb->error_count++;\n+\t\tif (hc->ep_is_in) {\n+\t\t\tframe_desc->status = -DWC_E_NO_STREAM_RES;\n+\t\t} else {\n+\t\t\tframe_desc->status = -DWC_E_COMMUNICATION;\n+\t\t}\n+\t\tframe_desc->actual_length = 0;\n+\t\tbreak;\n+\tcase DWC_OTG_HC_XFER_BABBLE_ERR:\n+\t\turb->error_count++;\n+\t\tframe_desc->status = -DWC_E_OVERFLOW;\n+\t\t/* Don't need to update actual_length in this case. */\n+\t\tbreak;\n+\tcase DWC_OTG_HC_XFER_XACT_ERR:\n+\t\turb->error_count++;\n+\t\tframe_desc->status = -DWC_E_PROTOCOL;\n+\t\tframe_desc->actual_length =\n+\t\t    get_actual_xfer_length(hc, hc_regs, qtd, halt_status, NULL);\n+\n+\t\t/* non DWORD-aligned buffer case handling. */\n+\t\tif (hc->align_buff && frame_desc->actual_length && hc->ep_is_in) {\n+\t\t\tdwc_memcpy(urb->buf + frame_desc->offset + qtd->isoc_split_offset,\n+\t\t\t\t   hc->qh->dw_align_buf, frame_desc->actual_length);\n+\t\t}\n+\t\t/* Skip whole frame */\n+\t\tif (hc->qh->do_split && (hc->ep_type == DWC_OTG_EP_TYPE_ISOC) &&\n+\t\t    hc->ep_is_in && hcd->core_if->dma_enable) {\n+\t\t\tqtd->complete_split = 0;\n+\t\t\tqtd->isoc_split_offset = 0;\n+\t\t}\n+\n+\t\tbreak;\n+\tdefault:\n+\t\tDWC_ASSERT(1, \"Unhandled _halt_status (%d)\\n\", halt_status);\n+\t\tbreak;\n+\t}\n+\tif (++qtd->isoc_frame_index == urb->packet_count) {\n+\t\t/*\n+\t\t * urb->status is not used for isoc transfers.\n+\t\t * The individual frame_desc statuses are used instead.\n+\t\t */\n+\t\thcd->fops->complete(hcd, urb->priv, urb, 0);\n+\t\tret_val = DWC_OTG_HC_XFER_URB_COMPLETE;\n+\t} else {\n+\t\tret_val = DWC_OTG_HC_XFER_COMPLETE;\n+\t}\n+\treturn ret_val;\n+}\n+\n+/**\n+ * Frees the first QTD in the QH's list if free_qtd is 1. For non-periodic\n+ * QHs, removes the QH from the active non-periodic schedule. If any QTDs are\n+ * still linked to the QH, the QH is added to the end of the inactive\n+ * non-periodic schedule. For periodic QHs, removes the QH from the periodic\n+ * schedule if no more QTDs are linked to the QH.\n+ */\n+static void deactivate_qh(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh, int free_qtd)\n+{\n+\tint continue_split = 0;\n+\tdwc_otg_qtd_t *qtd;\n+\n+\tDWC_DEBUGPL(DBG_HCDV, \"  %s(%p,%p,%d)\\n\", __func__, hcd, qh, free_qtd);\n+\n+\tqtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list);\n+\n+\tif (qtd->complete_split) {\n+\t\tcontinue_split = 1;\n+\t} else if (qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_MID ||\n+\t\t   qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_END) {\n+\t\tcontinue_split = 1;\n+\t}\n+\n+\tif (free_qtd) {\n+\t\tdwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh);\n+\t\tcontinue_split = 0;\n+\t}\n+\n+\tqh->channel = NULL;\n+\tdwc_otg_hcd_qh_deactivate(hcd, qh, continue_split);\n+}\n+\n+/**\n+ * Releases a host channel for use by other transfers. Attempts to select and\n+ * queue more transactions since at least one host channel is available.\n+ *\n+ * @param hcd The HCD state structure.\n+ * @param hc The host channel to release.\n+ * @param qtd The QTD associated with the host channel. This QTD may be freed\n+ * if the transfer is complete or an error has occurred.\n+ * @param halt_status Reason the channel is being released. This status\n+ * determines the actions taken by this function.\n+ */\n+static void release_channel(dwc_otg_hcd_t * hcd,\n+\t\t\t    dwc_hc_t * hc,\n+\t\t\t    dwc_otg_qtd_t * qtd,\n+\t\t\t    dwc_otg_halt_status_e halt_status)\n+{\n+\tdwc_otg_transaction_type_e tr_type;\n+\tint free_qtd;\n+\n+\tint hog_port = 0;\n+\n+\tDWC_DEBUGPL(DBG_HCDV, \"  %s: channel %d, halt_status %d, xfer_len %d\\n\",\n+\t\t    __func__, hc->hc_num, halt_status, hc->xfer_len);\n+\n+\tif(fiq_fsm_enable && hc->do_split) {\n+\t\tif(!hc->ep_is_in && hc->ep_type == UE_ISOCHRONOUS) {\n+\t\t\tif(hc->xact_pos == DWC_HCSPLIT_XACTPOS_MID ||\n+\t\t\t\t\thc->xact_pos == DWC_HCSPLIT_XACTPOS_BEGIN) {\n+\t\t\t\thog_port = 0;\n+\t\t\t}\n+\t\t}\n+\t}\n+\n+\tswitch (halt_status) {\n+\tcase DWC_OTG_HC_XFER_URB_COMPLETE:\n+\t\tfree_qtd = 1;\n+\t\tbreak;\n+\tcase DWC_OTG_HC_XFER_AHB_ERR:\n+\tcase DWC_OTG_HC_XFER_STALL:\n+\tcase DWC_OTG_HC_XFER_BABBLE_ERR:\n+\t\tfree_qtd = 1;\n+\t\tbreak;\n+\tcase DWC_OTG_HC_XFER_XACT_ERR:\n+\t\tif (qtd->error_count >= 3) {\n+\t\t\tDWC_DEBUGPL(DBG_HCDV,\n+\t\t\t\t    \"  Complete URB with transaction error\\n\");\n+\t\t\tfree_qtd = 1;\n+\t\t\tqtd->urb->status = -DWC_E_PROTOCOL;\n+\t\t\thcd->fops->complete(hcd, qtd->urb->priv,\n+\t\t\t\t\t    qtd->urb, -DWC_E_PROTOCOL);\n+\t\t} else {\n+\t\t\tfree_qtd = 0;\n+\t\t}\n+\t\tbreak;\n+\tcase DWC_OTG_HC_XFER_URB_DEQUEUE:\n+\t\t/*\n+\t\t * The QTD has already been removed and the QH has been\n+\t\t * deactivated. Don't want to do anything except release the\n+\t\t * host channel and try to queue more transfers.\n+\t\t */\n+\t\tgoto cleanup;\n+\tcase DWC_OTG_HC_XFER_NO_HALT_STATUS:\n+\t\tfree_qtd = 0;\n+\t\tbreak;\n+\tcase DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE:\n+\t\tDWC_DEBUGPL(DBG_HCDV,\n+\t\t\t\"  Complete URB with I/O error\\n\");\n+\t\tfree_qtd = 1;\n+\t\tqtd->urb->status = -DWC_E_IO;\n+\t\thcd->fops->complete(hcd, qtd->urb->priv,\n+\t\t\tqtd->urb, -DWC_E_IO);\n+\t\tbreak;\n+\tdefault:\n+\t\tfree_qtd = 0;\n+\t\tbreak;\n+\t}\n+\n+\tdeactivate_qh(hcd, hc->qh, free_qtd);\n+\n+cleanup:\n+\t/*\n+\t * Release the host channel for use by other transfers. The cleanup\n+\t * function clears the channel interrupt enables and conditions, so\n+\t * there's no need to clear the Channel Halted interrupt separately.\n+\t */\n+\tif (fiq_fsm_enable && hcd->fiq_state->channel[hc->hc_num].fsm != FIQ_PASSTHROUGH)\n+\t\tdwc_otg_cleanup_fiq_channel(hcd, hc->hc_num);\n+\tdwc_otg_hc_cleanup(hcd->core_if, hc);\n+\tDWC_CIRCLEQ_INSERT_TAIL(&hcd->free_hc_list, hc, hc_list_entry);\n+\n+\tif (!microframe_schedule) {\n+\t\tswitch (hc->ep_type) {\n+\t\tcase DWC_OTG_EP_TYPE_CONTROL:\n+\t\tcase DWC_OTG_EP_TYPE_BULK:\n+\t\t\thcd->non_periodic_channels--;\n+\t\t\tbreak;\n+\n+\t\tdefault:\n+\t\t\t/*\n+\t\t\t * Don't release reservations for periodic channels here.\n+\t\t\t * That's done when a periodic transfer is descheduled (i.e.\n+\t\t\t * when the QH is removed from the periodic schedule).\n+\t\t\t */\n+\t\t\tbreak;\n+\t\t}\n+\t} else {\n+\t\thcd->available_host_channels++;\n+\t\tfiq_print(FIQDBG_INT, hcd->fiq_state, \"AHC = %d \", hcd->available_host_channels);\n+\t}\n+\n+\t/* Try to queue more transfers now that there's a free channel. */\n+\ttr_type = dwc_otg_hcd_select_transactions(hcd);\n+\tif (tr_type != DWC_OTG_TRANSACTION_NONE) {\n+\t\tdwc_otg_hcd_queue_transactions(hcd, tr_type);\n+\t}\n+}\n+\n+/**\n+ * Halts a host channel. If the channel cannot be halted immediately because\n+ * the request queue is full, this function ensures that the FIFO empty\n+ * interrupt for the appropriate queue is enabled so that the halt request can\n+ * be queued when there is space in the request queue.\n+ *\n+ * This function may also be called in DMA mode. In that case, the channel is\n+ * simply released since the core always halts the channel automatically in\n+ * DMA mode.\n+ */\n+static void halt_channel(dwc_otg_hcd_t * hcd,\n+\t\t\t dwc_hc_t * hc,\n+\t\t\t dwc_otg_qtd_t * qtd, dwc_otg_halt_status_e halt_status)\n+{\n+\tif (hcd->core_if->dma_enable) {\n+\t\trelease_channel(hcd, hc, qtd, halt_status);\n+\t\treturn;\n+\t}\n+\n+\t/* Slave mode processing... */\n+\tdwc_otg_hc_halt(hcd->core_if, hc, halt_status);\n+\n+\tif (hc->halt_on_queue) {\n+\t\tgintmsk_data_t gintmsk = {.d32 = 0 };\n+\t\tdwc_otg_core_global_regs_t *global_regs;\n+\t\tglobal_regs = hcd->core_if->core_global_regs;\n+\n+\t\tif (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL ||\n+\t\t    hc->ep_type == DWC_OTG_EP_TYPE_BULK) {\n+\t\t\t/*\n+\t\t\t * Make sure the Non-periodic Tx FIFO empty interrupt\n+\t\t\t * is enabled so that the non-periodic schedule will\n+\t\t\t * be processed.\n+\t\t\t */\n+\t\t\tgintmsk.b.nptxfempty = 1;\n+\t\t\tif (fiq_enable) {\n+\t\t\t\tlocal_fiq_disable();\n+\t\t\t\tfiq_fsm_spin_lock(&hcd->fiq_state->lock);\n+\t\t\t\tDWC_MODIFY_REG32(&global_regs->gintmsk, 0, gintmsk.d32);\n+\t\t\t\tfiq_fsm_spin_unlock(&hcd->fiq_state->lock);\n+\t\t\t\tlocal_fiq_enable();\n+\t\t\t} else {\n+\t\t\t\tDWC_MODIFY_REG32(&global_regs->gintmsk, 0, gintmsk.d32);\n+\t\t\t}\n+\t\t} else {\n+\t\t\t/*\n+\t\t\t * Move the QH from the periodic queued schedule to\n+\t\t\t * the periodic assigned schedule. This allows the\n+\t\t\t * halt to be queued when the periodic schedule is\n+\t\t\t * processed.\n+\t\t\t */\n+\t\t\tDWC_LIST_MOVE_HEAD(&hcd->periodic_sched_assigned,\n+\t\t\t\t\t   &hc->qh->qh_list_entry);\n+\n+\t\t\t/*\n+\t\t\t * Make sure the Periodic Tx FIFO Empty interrupt is\n+\t\t\t * enabled so that the periodic schedule will be\n+\t\t\t * processed.\n+\t\t\t */\n+\t\t\tgintmsk.b.ptxfempty = 1;\n+\t\t\tif (fiq_enable) {\n+\t\t\t\tlocal_fiq_disable();\n+\t\t\t\tfiq_fsm_spin_lock(&hcd->fiq_state->lock);\n+\t\t\t\tDWC_MODIFY_REG32(&global_regs->gintmsk, 0, gintmsk.d32);\n+\t\t\t\tfiq_fsm_spin_unlock(&hcd->fiq_state->lock);\n+\t\t\t\tlocal_fiq_enable();\n+\t\t\t} else {\n+\t\t\t\tDWC_MODIFY_REG32(&global_regs->gintmsk, 0, gintmsk.d32);\n+\t\t\t}\n+\t\t}\n+\t}\n+}\n+\n+/**\n+ * Performs common cleanup for non-periodic transfers after a Transfer\n+ * Complete interrupt. This function should be called after any endpoint type\n+ * specific handling is finished to release the host channel.\n+ */\n+static void complete_non_periodic_xfer(dwc_otg_hcd_t * hcd,\n+\t\t\t\t       dwc_hc_t * hc,\n+\t\t\t\t       dwc_otg_hc_regs_t * hc_regs,\n+\t\t\t\t       dwc_otg_qtd_t * qtd,\n+\t\t\t\t       dwc_otg_halt_status_e halt_status)\n+{\n+\thcint_data_t hcint;\n+\n+\tqtd->error_count = 0;\n+\n+\thcint.d32 = DWC_READ_REG32(&hc_regs->hcint);\n+\tif (hcint.b.nyet) {\n+\t\t/*\n+\t\t * Got a NYET on the last transaction of the transfer. This\n+\t\t * means that the endpoint should be in the PING state at the\n+\t\t * beginning of the next transfer.\n+\t\t */\n+\t\thc->qh->ping_state = 1;\n+\t\tclear_hc_int(hc_regs, nyet);\n+\t}\n+\n+\t/*\n+\t * Always halt and release the host channel to make it available for\n+\t * more transfers. There may still be more phases for a control\n+\t * transfer or more data packets for a bulk transfer at this point,\n+\t * but the host channel is still halted. A channel will be reassigned\n+\t * to the transfer when the non-periodic schedule is processed after\n+\t * the channel is released. This allows transactions to be queued\n+\t * properly via dwc_otg_hcd_queue_transactions, which also enables the\n+\t * Tx FIFO Empty interrupt if necessary.\n+\t */\n+\tif (hc->ep_is_in) {\n+\t\t/*\n+\t\t * IN transfers in Slave mode require an explicit disable to\n+\t\t * halt the channel. (In DMA mode, this call simply releases\n+\t\t * the channel.)\n+\t\t */\n+\t\thalt_channel(hcd, hc, qtd, halt_status);\n+\t} else {\n+\t\t/*\n+\t\t * The channel is automatically disabled by the core for OUT\n+\t\t * transfers in Slave mode.\n+\t\t */\n+\t\trelease_channel(hcd, hc, qtd, halt_status);\n+\t}\n+}\n+\n+/**\n+ * Performs common cleanup for periodic transfers after a Transfer Complete\n+ * interrupt. This function should be called after any endpoint type specific\n+ * handling is finished to release the host channel.\n+ */\n+static void complete_periodic_xfer(dwc_otg_hcd_t * hcd,\n+\t\t\t\t   dwc_hc_t * hc,\n+\t\t\t\t   dwc_otg_hc_regs_t * hc_regs,\n+\t\t\t\t   dwc_otg_qtd_t * qtd,\n+\t\t\t\t   dwc_otg_halt_status_e halt_status)\n+{\n+\thctsiz_data_t hctsiz;\n+\tqtd->error_count = 0;\n+\n+\thctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);\n+\tif (!hc->ep_is_in || hctsiz.b.pktcnt == 0) {\n+\t\t/* Core halts channel in these cases. */\n+\t\trelease_channel(hcd, hc, qtd, halt_status);\n+\t} else {\n+\t\t/* Flush any outstanding requests from the Tx queue. */\n+\t\thalt_channel(hcd, hc, qtd, halt_status);\n+\t}\n+}\n+\n+static int32_t handle_xfercomp_isoc_split_in(dwc_otg_hcd_t * hcd,\n+\t\t\t\t\t     dwc_hc_t * hc,\n+\t\t\t\t\t     dwc_otg_hc_regs_t * hc_regs,\n+\t\t\t\t\t     dwc_otg_qtd_t * qtd)\n+{\n+\tuint32_t len;\n+\tstruct dwc_otg_hcd_iso_packet_desc *frame_desc;\n+\tframe_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index];\n+\n+\tlen = get_actual_xfer_length(hc, hc_regs, qtd,\n+\t\t\t\t     DWC_OTG_HC_XFER_COMPLETE, NULL);\n+\n+\tif (!len) {\n+\t\tqtd->complete_split = 0;\n+\t\tqtd->isoc_split_offset = 0;\n+\t\treturn 0;\n+\t}\n+\tframe_desc->actual_length += len;\n+\n+\tif (hc->align_buff && len)\n+\t\tdwc_memcpy(qtd->urb->buf + frame_desc->offset +\n+\t\t\t   qtd->isoc_split_offset, hc->qh->dw_align_buf, len);\n+\tqtd->isoc_split_offset += len;\n+\n+\tif (frame_desc->length == frame_desc->actual_length) {\n+\t\tframe_desc->status = 0;\n+\t\tqtd->isoc_frame_index++;\n+\t\tqtd->complete_split = 0;\n+\t\tqtd->isoc_split_offset = 0;\n+\t}\n+\n+\tif (qtd->isoc_frame_index == qtd->urb->packet_count) {\n+\t\thcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0);\n+\t\trelease_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE);\n+\t} else {\n+\t\trelease_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS);\n+\t}\n+\n+\treturn 1;\t\t/* Indicates that channel released */\n+}\n+\n+/**\n+ * Handles a host channel Transfer Complete interrupt. This handler may be\n+ * called in either DMA mode or Slave mode.\n+ */\n+static int32_t handle_hc_xfercomp_intr(dwc_otg_hcd_t * hcd,\n+\t\t\t\t       dwc_hc_t * hc,\n+\t\t\t\t       dwc_otg_hc_regs_t * hc_regs,\n+\t\t\t\t       dwc_otg_qtd_t * qtd)\n+{\n+\tint urb_xfer_done;\n+\tdwc_otg_halt_status_e halt_status = DWC_OTG_HC_XFER_COMPLETE;\n+\tdwc_otg_hcd_urb_t *urb = qtd->urb;\n+\tint pipe_type = dwc_otg_hcd_get_pipe_type(&urb->pipe_info);\n+\n+\tDWC_DEBUGPL(DBG_HCDI, \"--Host Channel %d Interrupt: \"\n+\t\t    \"Transfer Complete--\\n\", hc->hc_num);\n+\n+\tif (hcd->core_if->dma_desc_enable) {\n+\t\tdwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs, halt_status);\n+\t\tif (pipe_type == UE_ISOCHRONOUS) {\n+\t\t\t/* Do not disable the interrupt, just clear it */\n+\t\t\tclear_hc_int(hc_regs, xfercomp);\n+\t\t\treturn 1;\n+\t\t}\n+\t\tgoto handle_xfercomp_done;\n+\t}\n+\n+\t/*\n+\t * Handle xfer complete on CSPLIT.\n+\t */\n+\n+\tif (hc->qh->do_split) {\n+\t\tif ((hc->ep_type == DWC_OTG_EP_TYPE_ISOC) && hc->ep_is_in\n+\t\t    && hcd->core_if->dma_enable) {\n+\t\t\tif (qtd->complete_split\n+\t\t\t    && handle_xfercomp_isoc_split_in(hcd, hc, hc_regs,\n+\t\t\t\t\t\t\t     qtd))\n+\t\t\t\tgoto handle_xfercomp_done;\n+\t\t} else {\n+\t\t\tqtd->complete_split = 0;\n+\t\t}\n+\t}\n+\n+\t/* Update the QTD and URB states. */\n+\tswitch (pipe_type) {\n+\tcase UE_CONTROL:\n+\t\tswitch (qtd->control_phase) {\n+\t\tcase DWC_OTG_CONTROL_SETUP:\n+\t\t\tif (urb->length > 0) {\n+\t\t\t\tqtd->control_phase = DWC_OTG_CONTROL_DATA;\n+\t\t\t} else {\n+\t\t\t\tqtd->control_phase = DWC_OTG_CONTROL_STATUS;\n+\t\t\t}\n+\t\t\tDWC_DEBUGPL(DBG_HCDV,\n+\t\t\t\t    \"  Control setup transaction done\\n\");\n+\t\t\thalt_status = DWC_OTG_HC_XFER_COMPLETE;\n+\t\t\tbreak;\n+\t\tcase DWC_OTG_CONTROL_DATA:{\n+\t\t\t\turb_xfer_done =\n+\t\t\t\t    update_urb_state_xfer_comp(hc, hc_regs, urb,\n+\t\t\t\t\t\t\t       qtd);\n+\t\t\t\tif (urb_xfer_done) {\n+\t\t\t\t\tqtd->control_phase =\n+\t\t\t\t\t    DWC_OTG_CONTROL_STATUS;\n+\t\t\t\t\tDWC_DEBUGPL(DBG_HCDV,\n+\t\t\t\t\t\t    \"  Control data transfer done\\n\");\n+\t\t\t\t} else {\n+\t\t\t\t\tdwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);\n+\t\t\t\t}\n+\t\t\t\thalt_status = DWC_OTG_HC_XFER_COMPLETE;\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\tcase DWC_OTG_CONTROL_STATUS:\n+\t\t\tDWC_DEBUGPL(DBG_HCDV, \"  Control transfer complete\\n\");\n+\t\t\tif (urb->status == -DWC_E_IN_PROGRESS) {\n+\t\t\t\turb->status = 0;\n+\t\t\t}\n+\t\t\thcd->fops->complete(hcd, urb->priv, urb, urb->status);\n+\t\t\thalt_status = DWC_OTG_HC_XFER_URB_COMPLETE;\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\tcomplete_non_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status);\n+\t\tbreak;\n+\tcase UE_BULK:\n+\t\tDWC_DEBUGPL(DBG_HCDV, \"  Bulk transfer complete\\n\");\n+\t\turb_xfer_done =\n+\t\t    update_urb_state_xfer_comp(hc, hc_regs, urb, qtd);\n+\t\tif (urb_xfer_done) {\n+\t\t\thcd->fops->complete(hcd, urb->priv, urb, urb->status);\n+\t\t\thalt_status = DWC_OTG_HC_XFER_URB_COMPLETE;\n+\t\t} else {\n+\t\t\thalt_status = DWC_OTG_HC_XFER_COMPLETE;\n+\t\t}\n+\n+\t\tdwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);\n+\t\tcomplete_non_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status);\n+\t\tbreak;\n+\tcase UE_INTERRUPT:\n+\t\tDWC_DEBUGPL(DBG_HCDV, \"  Interrupt transfer complete\\n\");\n+\t\turb_xfer_done =\n+\t\t\tupdate_urb_state_xfer_comp(hc, hc_regs, urb, qtd);\n+\n+\t\t/*\n+\t\t * Interrupt URB is done on the first transfer complete\n+\t\t * interrupt.\n+\t\t */\n+\t\tif (urb_xfer_done) {\n+\t\t\t\thcd->fops->complete(hcd, urb->priv, urb, urb->status);\n+\t\t\t\thalt_status = DWC_OTG_HC_XFER_URB_COMPLETE;\n+\t\t} else {\n+\t\t\t\thalt_status = DWC_OTG_HC_XFER_COMPLETE;\n+\t\t}\n+\n+\t\tdwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);\n+\t\tcomplete_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status);\n+\t\tbreak;\n+\tcase UE_ISOCHRONOUS:\n+\t\tDWC_DEBUGPL(DBG_HCDV, \"  Isochronous transfer complete\\n\");\n+\t\tif (qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_ALL) {\n+\t\t\thalt_status =\n+\t\t\t    update_isoc_urb_state(hcd, hc, hc_regs, qtd,\n+\t\t\t\t\t\t  DWC_OTG_HC_XFER_COMPLETE);\n+\t\t}\n+\t\tcomplete_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status);\n+\t\tbreak;\n+\t}\n+\n+handle_xfercomp_done:\n+\tdisable_hc_int(hc_regs, xfercompl);\n+\n+\treturn 1;\n+}\n+\n+/**\n+ * Handles a host channel STALL interrupt. This handler may be called in\n+ * either DMA mode or Slave mode.\n+ */\n+static int32_t handle_hc_stall_intr(dwc_otg_hcd_t * hcd,\n+\t\t\t\t    dwc_hc_t * hc,\n+\t\t\t\t    dwc_otg_hc_regs_t * hc_regs,\n+\t\t\t\t    dwc_otg_qtd_t * qtd)\n+{\n+\tdwc_otg_hcd_urb_t *urb = qtd->urb;\n+\tint pipe_type = dwc_otg_hcd_get_pipe_type(&urb->pipe_info);\n+\n+\tDWC_DEBUGPL(DBG_HCD, \"--Host Channel %d Interrupt: \"\n+\t\t    \"STALL Received--\\n\", hc->hc_num);\n+\n+\tif (hcd->core_if->dma_desc_enable) {\n+\t\tdwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs, DWC_OTG_HC_XFER_STALL);\n+\t\tgoto handle_stall_done;\n+\t}\n+\n+\tif (pipe_type == UE_CONTROL) {\n+\t\thcd->fops->complete(hcd, urb->priv, urb, -DWC_E_PIPE);\n+\t}\n+\n+\tif (pipe_type == UE_BULK || pipe_type == UE_INTERRUPT) {\n+\t\thcd->fops->complete(hcd, urb->priv, urb, -DWC_E_PIPE);\n+\t\t/*\n+\t\t * USB protocol requires resetting the data toggle for bulk\n+\t\t * and interrupt endpoints when a CLEAR_FEATURE(ENDPOINT_HALT)\n+\t\t * setup command is issued to the endpoint. Anticipate the\n+\t\t * CLEAR_FEATURE command since a STALL has occurred and reset\n+\t\t * the data toggle now.\n+\t\t */\n+\t\thc->qh->data_toggle = 0;\n+\t}\n+\n+\thalt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_STALL);\n+\n+handle_stall_done:\n+\tdisable_hc_int(hc_regs, stall);\n+\n+\treturn 1;\n+}\n+\n+/*\n+ * Updates the state of the URB when a transfer has been stopped due to an\n+ * abnormal condition before the transfer completes. Modifies the\n+ * actual_length field of the URB to reflect the number of bytes that have\n+ * actually been transferred via the host channel.\n+ */\n+static void update_urb_state_xfer_intr(dwc_hc_t * hc,\n+\t\t\t\t       dwc_otg_hc_regs_t * hc_regs,\n+\t\t\t\t       dwc_otg_hcd_urb_t * urb,\n+\t\t\t\t       dwc_otg_qtd_t * qtd,\n+\t\t\t\t       dwc_otg_halt_status_e halt_status)\n+{\n+\tuint32_t bytes_transferred = get_actual_xfer_length(hc, hc_regs, qtd,\n+\t\t\t\t\t\t\t    halt_status, NULL);\n+\n+\tif (urb->actual_length + bytes_transferred > urb->length) {\n+\t\tprintk_once(KERN_DEBUG \"dwc_otg: DEVICE:%03d : %s:%d:trimming xfer length\\n\",\n+\t\t\thc->dev_addr, __func__, __LINE__);\n+\t\tbytes_transferred = urb->length - urb->actual_length;\n+\t}\n+\n+\t/* non DWORD-aligned buffer case handling. */\n+\tif (hc->align_buff && bytes_transferred && hc->ep_is_in) {\n+\t\tdwc_memcpy(urb->buf + urb->actual_length, hc->qh->dw_align_buf,\n+\t\t\t   bytes_transferred);\n+\t}\n+\n+\turb->actual_length += bytes_transferred;\n+\n+#ifdef DEBUG\n+\t{\n+\t\thctsiz_data_t hctsiz;\n+\t\thctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);\n+\t\tDWC_DEBUGPL(DBG_HCDV, \"DWC_otg: %s: %s, channel %d\\n\",\n+\t\t\t    __func__, (hc->ep_is_in ? \"IN\" : \"OUT\"),\n+\t\t\t    hc->hc_num);\n+\t\tDWC_DEBUGPL(DBG_HCDV, \"  hc->start_pkt_count %d\\n\",\n+\t\t\t    hc->start_pkt_count);\n+\t\tDWC_DEBUGPL(DBG_HCDV, \"  hctsiz.pktcnt %d\\n\", hctsiz.b.pktcnt);\n+\t\tDWC_DEBUGPL(DBG_HCDV, \"  hc->max_packet %d\\n\", hc->max_packet);\n+\t\tDWC_DEBUGPL(DBG_HCDV, \"  bytes_transferred %d\\n\",\n+\t\t\t    bytes_transferred);\n+\t\tDWC_DEBUGPL(DBG_HCDV, \"  urb->actual_length %d\\n\",\n+\t\t\t    urb->actual_length);\n+\t\tDWC_DEBUGPL(DBG_HCDV, \"  urb->transfer_buffer_length %d\\n\",\n+\t\t\t    urb->length);\n+\t}\n+#endif\n+}\n+\n+/**\n+ * Handles a host channel NAK interrupt. This handler may be called in either\n+ * DMA mode or Slave mode.\n+ */\n+static int32_t handle_hc_nak_intr(dwc_otg_hcd_t * hcd,\n+\t\t\t\t  dwc_hc_t * hc,\n+\t\t\t\t  dwc_otg_hc_regs_t * hc_regs,\n+\t\t\t\t  dwc_otg_qtd_t * qtd)\n+{\n+\tDWC_DEBUGPL(DBG_HCDI, \"--Host Channel %d Interrupt: \"\n+\t\t    \"NAK Received--\\n\", hc->hc_num);\n+\n+\t/*\n+\t * When we get bulk NAKs then remember this so we holdoff on this qh until\n+\t * the beginning of the next frame\n+\t */\n+\tswitch(dwc_otg_hcd_get_pipe_type(&qtd->urb->pipe_info)) {\n+\t\tcase UE_BULK:\n+\t\tcase UE_CONTROL:\n+\t\tif (nak_holdoff && qtd->qh->do_split)\n+\t\t\thc->qh->nak_frame = dwc_otg_hcd_get_frame_number(hcd);\n+\t}\n+\n+\t/*\n+\t * Handle NAK for IN/OUT SSPLIT/CSPLIT transfers, bulk, control, and\n+\t * interrupt.  Re-start the SSPLIT transfer.\n+\t */\n+\tif (hc->do_split) {\n+\t\tif (hc->complete_split) {\n+\t\t\tqtd->error_count = 0;\n+\t\t}\n+\t\tqtd->complete_split = 0;\n+\t\thalt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NAK);\n+\t\tgoto handle_nak_done;\n+\t}\n+\n+\tswitch (dwc_otg_hcd_get_pipe_type(&qtd->urb->pipe_info)) {\n+\tcase UE_CONTROL:\n+\tcase UE_BULK:\n+\t\tif (hcd->core_if->dma_enable && hc->ep_is_in) {\n+\t\t\t/*\n+\t\t\t * NAK interrupts are enabled on bulk/control IN\n+\t\t\t * transfers in DMA mode for the sole purpose of\n+\t\t\t * resetting the error count after a transaction error\n+\t\t\t * occurs. The core will continue transferring data.\n+\t\t\t * Disable other interrupts unmasked for the same\n+\t\t\t * reason.\n+\t\t\t */\n+\t\t\tdisable_hc_int(hc_regs, datatglerr);\n+\t\t\tdisable_hc_int(hc_regs, ack);\n+\t\t\tqtd->error_count = 0;\n+\t\t\tgoto handle_nak_done;\n+\t\t}\n+\n+\t\t/*\n+\t\t * NAK interrupts normally occur during OUT transfers in DMA\n+\t\t * or Slave mode. For IN transfers, more requests will be\n+\t\t * queued as request queue space is available.\n+\t\t */\n+\t\tqtd->error_count = 0;\n+\n+\t\tif (!hc->qh->ping_state) {\n+\t\t\tupdate_urb_state_xfer_intr(hc, hc_regs,\n+\t\t\t\t\t\t   qtd->urb, qtd,\n+\t\t\t\t\t\t   DWC_OTG_HC_XFER_NAK);\n+\t\t\tdwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);\n+\n+\t\t\tif (hc->speed == DWC_OTG_EP_SPEED_HIGH)\n+\t\t\t\thc->qh->ping_state = 1;\n+\t\t}\n+\n+\t\t/*\n+\t\t * Halt the channel so the transfer can be re-started from\n+\t\t * the appropriate point or the PING protocol will\n+\t\t * start/continue.\n+\t\t */\n+\t\thalt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NAK);\n+\t\tbreak;\n+\tcase UE_INTERRUPT:\n+\t\tqtd->error_count = 0;\n+\t\thalt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NAK);\n+\t\tbreak;\n+\tcase UE_ISOCHRONOUS:\n+\t\t/* Should never get called for isochronous transfers. */\n+\t\tDWC_ASSERT(1, \"NACK interrupt for ISOC transfer\\n\");\n+\t\tbreak;\n+\t}\n+\n+handle_nak_done:\n+\tdisable_hc_int(hc_regs, nak);\n+\n+\treturn 1;\n+}\n+\n+/**\n+ * Handles a host channel ACK interrupt. This interrupt is enabled when\n+ * performing the PING protocol in Slave mode, when errors occur during\n+ * either Slave mode or DMA mode, and during Start Split transactions.\n+ */\n+static int32_t handle_hc_ack_intr(dwc_otg_hcd_t * hcd,\n+\t\t\t\t  dwc_hc_t * hc,\n+\t\t\t\t  dwc_otg_hc_regs_t * hc_regs,\n+\t\t\t\t  dwc_otg_qtd_t * qtd)\n+{\n+\tDWC_DEBUGPL(DBG_HCDI, \"--Host Channel %d Interrupt: \"\n+\t\t    \"ACK Received--\\n\", hc->hc_num);\n+\n+\tif (hc->do_split) {\n+\t\t/*\n+\t\t * Handle ACK on SSPLIT.\n+\t\t * ACK should not occur in CSPLIT.\n+\t\t */\n+\t\tif (!hc->ep_is_in && hc->data_pid_start != DWC_OTG_HC_PID_SETUP) {\n+\t\t\tqtd->ssplit_out_xfer_count = hc->xfer_len;\n+\t\t}\n+\t\tif (!(hc->ep_type == DWC_OTG_EP_TYPE_ISOC && !hc->ep_is_in)) {\n+\t\t\t/* Don't need complete for isochronous out transfers. */\n+\t\t\tqtd->complete_split = 1;\n+\t\t}\n+\n+\t\t/* ISOC OUT */\n+\t\tif (hc->ep_type == DWC_OTG_EP_TYPE_ISOC && !hc->ep_is_in) {\n+\t\t\tswitch (hc->xact_pos) {\n+\t\t\tcase DWC_HCSPLIT_XACTPOS_ALL:\n+\t\t\t\tbreak;\n+\t\t\tcase DWC_HCSPLIT_XACTPOS_END:\n+\t\t\t\tqtd->isoc_split_pos = DWC_HCSPLIT_XACTPOS_ALL;\n+\t\t\t\tqtd->isoc_split_offset = 0;\n+\t\t\t\tbreak;\n+\t\t\tcase DWC_HCSPLIT_XACTPOS_BEGIN:\n+\t\t\tcase DWC_HCSPLIT_XACTPOS_MID:\n+\t\t\t\t/*\n+\t\t\t\t * For BEGIN or MID, calculate the length for\n+\t\t\t\t * the next microframe to determine the correct\n+\t\t\t\t * SSPLIT token, either MID or END.\n+\t\t\t\t */\n+\t\t\t\t{\n+\t\t\t\t\tstruct dwc_otg_hcd_iso_packet_desc\n+\t\t\t\t\t*frame_desc;\n+\n+\t\t\t\t\tframe_desc =\n+\t\t\t\t\t    &qtd->urb->\n+\t\t\t\t\t    iso_descs[qtd->isoc_frame_index];\n+\t\t\t\t\tqtd->isoc_split_offset += 188;\n+\n+\t\t\t\t\tif ((frame_desc->length -\n+\t\t\t\t\t     qtd->isoc_split_offset) <= 188) {\n+\t\t\t\t\t\tqtd->isoc_split_pos =\n+\t\t\t\t\t\t    DWC_HCSPLIT_XACTPOS_END;\n+\t\t\t\t\t} else {\n+\t\t\t\t\t\tqtd->isoc_split_pos =\n+\t\t\t\t\t\t    DWC_HCSPLIT_XACTPOS_MID;\n+\t\t\t\t\t}\n+\n+\t\t\t\t}\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t} else {\n+\t\t\thalt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_ACK);\n+\t\t}\n+\t} else {\n+\t\t/*\n+\t\t * An unmasked ACK on a non-split DMA transaction is\n+\t\t * for the sole purpose of resetting error counts. Disable other\n+\t\t * interrupts unmasked for the same reason.\n+\t\t */\n+\t\tif(hcd->core_if->dma_enable) {\n+\t\t\tdisable_hc_int(hc_regs, datatglerr);\n+\t\t\tdisable_hc_int(hc_regs, nak);\n+\t\t}\n+\t\tqtd->error_count = 0;\n+\n+\t\tif (hc->qh->ping_state) {\n+\t\t\thc->qh->ping_state = 0;\n+\t\t\t/*\n+\t\t\t * Halt the channel so the transfer can be re-started\n+\t\t\t * from the appropriate point. This only happens in\n+\t\t\t * Slave mode. In DMA mode, the ping_state is cleared\n+\t\t\t * when the transfer is started because the core\n+\t\t\t * automatically executes the PING, then the transfer.\n+\t\t\t */\n+\t\t\thalt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_ACK);\n+\t\t}\n+\t}\n+\n+\t/*\n+\t * If the ACK occurred when _not_ in the PING state, let the channel\n+\t * continue transferring data after clearing the error count.\n+\t */\n+\n+\tdisable_hc_int(hc_regs, ack);\n+\n+\treturn 1;\n+}\n+\n+/**\n+ * Handles a host channel NYET interrupt. This interrupt should only occur on\n+ * Bulk and Control OUT endpoints and for complete split transactions. If a\n+ * NYET occurs at the same time as a Transfer Complete interrupt, it is\n+ * handled in the xfercomp interrupt handler, not here. This handler may be\n+ * called in either DMA mode or Slave mode.\n+ */\n+static int32_t handle_hc_nyet_intr(dwc_otg_hcd_t * hcd,\n+\t\t\t\t   dwc_hc_t * hc,\n+\t\t\t\t   dwc_otg_hc_regs_t * hc_regs,\n+\t\t\t\t   dwc_otg_qtd_t * qtd)\n+{\n+\tDWC_DEBUGPL(DBG_HCDI, \"--Host Channel %d Interrupt: \"\n+\t\t    \"NYET Received--\\n\", hc->hc_num);\n+\n+\t/*\n+\t * NYET on CSPLIT\n+\t * re-do the CSPLIT immediately on non-periodic\n+\t */\n+\tif (hc->do_split && hc->complete_split) {\n+\t\tif (hc->ep_is_in && (hc->ep_type == DWC_OTG_EP_TYPE_ISOC)\n+\t\t    && hcd->core_if->dma_enable) {\n+\t\t\tqtd->complete_split = 0;\n+\t\t\tqtd->isoc_split_offset = 0;\n+\t\t\tif (++qtd->isoc_frame_index == qtd->urb->packet_count) {\n+\t\t\t\thcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0);\n+\t\t\t\trelease_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE);\n+\t\t\t}\n+\t\t\telse\n+\t\t\t\trelease_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS);\n+\t\t\tgoto handle_nyet_done;\n+\t\t}\n+\n+\t\tif (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||\n+\t\t    hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {\n+\t\t\tint frnum = dwc_otg_hcd_get_frame_number(hcd);\n+\n+\t\t\t// With the FIQ running we only ever see the failed NYET\n+\t\t\tif (dwc_full_frame_num(frnum) !=\n+\t\t\t    dwc_full_frame_num(hc->qh->sched_frame) ||\n+\t\t\t    fiq_fsm_enable) {\n+\t\t\t\t/*\n+\t\t\t\t * No longer in the same full speed frame.\n+\t\t\t\t * Treat this as a transaction error.\n+\t\t\t\t */\n+#if 0\n+\t\t\t\t/** @todo Fix system performance so this can\n+\t\t\t\t * be treated as an error. Right now complete\n+\t\t\t\t * splits cannot be scheduled precisely enough\n+\t\t\t\t * due to other system activity, so this error\n+\t\t\t\t * occurs regularly in Slave mode.\n+\t\t\t\t */\n+\t\t\t\tqtd->error_count++;\n+#endif\n+\t\t\t\tqtd->complete_split = 0;\n+\t\t\t\thalt_channel(hcd, hc, qtd,\n+\t\t\t\t\t     DWC_OTG_HC_XFER_XACT_ERR);\n+\t\t\t\t/** @todo add support for isoc release */\n+\t\t\t\tgoto handle_nyet_done;\n+\t\t\t}\n+\t\t}\n+\n+\t\thalt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NYET);\n+\t\tgoto handle_nyet_done;\n+\t}\n+\n+\thc->qh->ping_state = 1;\n+\tqtd->error_count = 0;\n+\n+\tupdate_urb_state_xfer_intr(hc, hc_regs, qtd->urb, qtd,\n+\t\t\t\t   DWC_OTG_HC_XFER_NYET);\n+\tdwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);\n+\n+\t/*\n+\t * Halt the channel and re-start the transfer so the PING\n+\t * protocol will start.\n+\t */\n+\thalt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NYET);\n+\n+handle_nyet_done:\n+\tdisable_hc_int(hc_regs, nyet);\n+\treturn 1;\n+}\n+\n+/**\n+ * Handles a host channel babble interrupt. This handler may be called in\n+ * either DMA mode or Slave mode.\n+ */\n+static int32_t handle_hc_babble_intr(dwc_otg_hcd_t * hcd,\n+\t\t\t\t     dwc_hc_t * hc,\n+\t\t\t\t     dwc_otg_hc_regs_t * hc_regs,\n+\t\t\t\t     dwc_otg_qtd_t * qtd)\n+{\n+\tDWC_DEBUGPL(DBG_HCDI, \"--Host Channel %d Interrupt: \"\n+\t\t    \"Babble Error--\\n\", hc->hc_num);\n+\n+\tif (hcd->core_if->dma_desc_enable) {\n+\t\tdwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs,\n+\t\t\t\t\t       DWC_OTG_HC_XFER_BABBLE_ERR);\n+\t\tgoto handle_babble_done;\n+\t}\n+\n+\tif (hc->ep_type != DWC_OTG_EP_TYPE_ISOC) {\n+\t\thcd->fops->complete(hcd, qtd->urb->priv,\n+\t\t\t\t    qtd->urb, -DWC_E_OVERFLOW);\n+\t\thalt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_BABBLE_ERR);\n+\t} else {\n+\t\tdwc_otg_halt_status_e halt_status;\n+\t\thalt_status = update_isoc_urb_state(hcd, hc, hc_regs, qtd,\n+\t\t\t\t\t\t    DWC_OTG_HC_XFER_BABBLE_ERR);\n+\t\thalt_channel(hcd, hc, qtd, halt_status);\n+\t}\n+\n+handle_babble_done:\n+\tdisable_hc_int(hc_regs, bblerr);\n+\treturn 1;\n+}\n+\n+/**\n+ * Handles a host channel AHB error interrupt. This handler is only called in\n+ * DMA mode.\n+ */\n+static int32_t handle_hc_ahberr_intr(dwc_otg_hcd_t * hcd,\n+\t\t\t\t     dwc_hc_t * hc,\n+\t\t\t\t     dwc_otg_hc_regs_t * hc_regs,\n+\t\t\t\t     dwc_otg_qtd_t * qtd)\n+{\n+\thcchar_data_t hcchar;\n+\thcsplt_data_t hcsplt;\n+\thctsiz_data_t hctsiz;\n+\tuint32_t hcdma;\n+\tchar *pipetype, *speed;\n+\n+\tdwc_otg_hcd_urb_t *urb = qtd->urb;\n+\n+\tDWC_DEBUGPL(DBG_HCDI, \"--Host Channel %d Interrupt: \"\n+\t\t    \"AHB Error--\\n\", hc->hc_num);\n+\n+\thcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);\n+\thcsplt.d32 = DWC_READ_REG32(&hc_regs->hcsplt);\n+\thctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);\n+\thcdma = DWC_READ_REG32(&hc_regs->hcdma);\n+\n+\tDWC_ERROR(\"AHB ERROR, Channel %d\\n\", hc->hc_num);\n+\tDWC_ERROR(\"  hcchar 0x%08x, hcsplt 0x%08x\\n\", hcchar.d32, hcsplt.d32);\n+\tDWC_ERROR(\"  hctsiz 0x%08x, hcdma 0x%08x\\n\", hctsiz.d32, hcdma);\n+\tDWC_DEBUGPL(DBG_HCD, \"DWC OTG HCD URB Enqueue\\n\");\n+\tDWC_ERROR(\"  Device address: %d\\n\",\n+\t\t  dwc_otg_hcd_get_dev_addr(&urb->pipe_info));\n+\tDWC_ERROR(\"  Endpoint: %d, %s\\n\",\n+\t\t  dwc_otg_hcd_get_ep_num(&urb->pipe_info),\n+\t\t  (dwc_otg_hcd_is_pipe_in(&urb->pipe_info) ? \"IN\" : \"OUT\"));\n+\n+\tswitch (dwc_otg_hcd_get_pipe_type(&urb->pipe_info)) {\n+\tcase UE_CONTROL:\n+\t\tpipetype = \"CONTROL\";\n+\t\tbreak;\n+\tcase UE_BULK:\n+\t\tpipetype = \"BULK\";\n+\t\tbreak;\n+\tcase UE_INTERRUPT:\n+\t\tpipetype = \"INTERRUPT\";\n+\t\tbreak;\n+\tcase UE_ISOCHRONOUS:\n+\t\tpipetype = \"ISOCHRONOUS\";\n+\t\tbreak;\n+\tdefault:\n+\t\tpipetype = \"UNKNOWN\";\n+\t\tbreak;\n+\t}\n+\n+\tDWC_ERROR(\"  Endpoint type: %s\\n\", pipetype);\n+\n+\tswitch (hc->speed) {\n+\tcase DWC_OTG_EP_SPEED_HIGH:\n+\t\tspeed = \"HIGH\";\n+\t\tbreak;\n+\tcase DWC_OTG_EP_SPEED_FULL:\n+\t\tspeed = \"FULL\";\n+\t\tbreak;\n+\tcase DWC_OTG_EP_SPEED_LOW:\n+\t\tspeed = \"LOW\";\n+\t\tbreak;\n+\tdefault:\n+\t\tspeed = \"UNKNOWN\";\n+\t\tbreak;\n+\t};\n+\n+\tDWC_ERROR(\"  Speed: %s\\n\", speed);\n+\n+\tDWC_ERROR(\"  Max packet size: %d\\n\",\n+\t\t  dwc_otg_hcd_get_mps(&urb->pipe_info));\n+\tDWC_ERROR(\"  Data buffer length: %d\\n\", urb->length);\n+\tDWC_ERROR(\"  Transfer buffer: %p, Transfer DMA: %p\\n\",\n+\t\t  urb->buf, (void *)urb->dma);\n+\tDWC_ERROR(\"  Setup buffer: %p, Setup DMA: %p\\n\",\n+\t\t  urb->setup_packet, (void *)urb->setup_dma);\n+\tDWC_ERROR(\"  Interval: %d\\n\", urb->interval);\n+\n+\t/* Core haltes the channel for Descriptor DMA mode */\n+\tif (hcd->core_if->dma_desc_enable) {\n+\t\tdwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs,\n+\t\t\t\t\t       DWC_OTG_HC_XFER_AHB_ERR);\n+\t\tgoto handle_ahberr_done;\n+\t}\n+\n+\thcd->fops->complete(hcd, urb->priv, urb, -DWC_E_IO);\n+\n+\t/*\n+\t * Force a channel halt. Don't call halt_channel because that won't\n+\t * write to the HCCHARn register in DMA mode to force the halt.\n+\t */\n+\tdwc_otg_hc_halt(hcd->core_if, hc, DWC_OTG_HC_XFER_AHB_ERR);\n+handle_ahberr_done:\n+\tdisable_hc_int(hc_regs, ahberr);\n+\treturn 1;\n+}\n+\n+/**\n+ * Handles a host channel transaction error interrupt. This handler may be\n+ * called in either DMA mode or Slave mode.\n+ */\n+static int32_t handle_hc_xacterr_intr(dwc_otg_hcd_t * hcd,\n+\t\t\t\t      dwc_hc_t * hc,\n+\t\t\t\t      dwc_otg_hc_regs_t * hc_regs,\n+\t\t\t\t      dwc_otg_qtd_t * qtd)\n+{\n+\tDWC_DEBUGPL(DBG_HCDI, \"--Host Channel %d Interrupt: \"\n+\t\t    \"Transaction Error--\\n\", hc->hc_num);\n+\n+\tif (hcd->core_if->dma_desc_enable) {\n+\t\tdwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs,\n+\t\t\t\t\t       DWC_OTG_HC_XFER_XACT_ERR);\n+\t\tgoto handle_xacterr_done;\n+\t}\n+\n+\tswitch (dwc_otg_hcd_get_pipe_type(&qtd->urb->pipe_info)) {\n+\tcase UE_CONTROL:\n+\tcase UE_BULK:\n+\t\tqtd->error_count++;\n+\t\tif (!hc->qh->ping_state) {\n+\n+\t\t\tupdate_urb_state_xfer_intr(hc, hc_regs,\n+\t\t\t\t\t\t   qtd->urb, qtd,\n+\t\t\t\t\t\t   DWC_OTG_HC_XFER_XACT_ERR);\n+\t\t\tdwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);\n+\t\t\tif (!hc->ep_is_in && hc->speed == DWC_OTG_EP_SPEED_HIGH) {\n+\t\t\t\thc->qh->ping_state = 1;\n+\t\t\t}\n+\t\t}\n+\n+\t\t/*\n+\t\t * Halt the channel so the transfer can be re-started from\n+\t\t * the appropriate point or the PING protocol will start.\n+\t\t */\n+\t\thalt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR);\n+\t\tbreak;\n+\tcase UE_INTERRUPT:\n+\t\tqtd->error_count++;\n+\t\tif (hc->do_split && hc->complete_split) {\n+\t\t\tqtd->complete_split = 0;\n+\t\t}\n+\t\thalt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR);\n+\t\tbreak;\n+\tcase UE_ISOCHRONOUS:\n+\t\t{\n+\t\t\tdwc_otg_halt_status_e halt_status;\n+\t\t\thalt_status =\n+\t\t\t    update_isoc_urb_state(hcd, hc, hc_regs, qtd,\n+\t\t\t\t\t\t  DWC_OTG_HC_XFER_XACT_ERR);\n+\n+\t\t\thalt_channel(hcd, hc, qtd, halt_status);\n+\t\t}\n+\t\tbreak;\n+\t}\n+handle_xacterr_done:\n+\tdisable_hc_int(hc_regs, xacterr);\n+\n+\treturn 1;\n+}\n+\n+/**\n+ * Handles a host channel frame overrun interrupt. This handler may be called\n+ * in either DMA mode or Slave mode.\n+ */\n+static int32_t handle_hc_frmovrun_intr(dwc_otg_hcd_t * hcd,\n+\t\t\t\t       dwc_hc_t * hc,\n+\t\t\t\t       dwc_otg_hc_regs_t * hc_regs,\n+\t\t\t\t       dwc_otg_qtd_t * qtd)\n+{\n+\tDWC_DEBUGPL(DBG_HCDI, \"--Host Channel %d Interrupt: \"\n+\t\t    \"Frame Overrun--\\n\", hc->hc_num);\n+\n+\tswitch (dwc_otg_hcd_get_pipe_type(&qtd->urb->pipe_info)) {\n+\tcase UE_CONTROL:\n+\tcase UE_BULK:\n+\t\tbreak;\n+\tcase UE_INTERRUPT:\n+\t\thalt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_FRAME_OVERRUN);\n+\t\tbreak;\n+\tcase UE_ISOCHRONOUS:\n+\t\t{\n+\t\t\tdwc_otg_halt_status_e halt_status;\n+\t\t\thalt_status =\n+\t\t\t    update_isoc_urb_state(hcd, hc, hc_regs, qtd,\n+\t\t\t\t\t\t  DWC_OTG_HC_XFER_FRAME_OVERRUN);\n+\n+\t\t\thalt_channel(hcd, hc, qtd, halt_status);\n+\t\t}\n+\t\tbreak;\n+\t}\n+\n+\tdisable_hc_int(hc_regs, frmovrun);\n+\n+\treturn 1;\n+}\n+\n+/**\n+ * Handles a host channel data toggle error interrupt. This handler may be\n+ * called in either DMA mode or Slave mode.\n+ */\n+static int32_t handle_hc_datatglerr_intr(dwc_otg_hcd_t * hcd,\n+\t\t\t\t\t dwc_hc_t * hc,\n+\t\t\t\t\t dwc_otg_hc_regs_t * hc_regs,\n+\t\t\t\t\t dwc_otg_qtd_t * qtd)\n+{\n+\tDWC_DEBUGPL(DBG_HCDI, \"--Host Channel %d Interrupt: \"\n+\t\t\"Data Toggle Error on %s transfer--\\n\",\n+\t\thc->hc_num, (hc->ep_is_in ? \"IN\" : \"OUT\"));\n+\n+\t/* Data toggles on split transactions cause the hc to halt.\n+\t * restart transfer */\n+\tif(hc->qh->do_split)\n+\t{\n+\t\tqtd->error_count++;\n+\t\tdwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);\n+\t\tupdate_urb_state_xfer_intr(hc, hc_regs,\n+\t\t\tqtd->urb, qtd, DWC_OTG_HC_XFER_XACT_ERR);\n+\t\thalt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR);\n+\t} else if (hc->ep_is_in) {\n+\t\t/* An unmasked data toggle error on a non-split DMA transaction is\n+\t\t * for the sole purpose of resetting error counts. Disable other\n+\t\t * interrupts unmasked for the same reason.\n+\t\t */\n+\t\tif(hcd->core_if->dma_enable) {\n+\t\t\tdisable_hc_int(hc_regs, ack);\n+\t\t\tdisable_hc_int(hc_regs, nak);\n+\t\t}\n+\t\tqtd->error_count = 0;\n+\t}\n+\n+\tdisable_hc_int(hc_regs, datatglerr);\n+\n+\treturn 1;\n+}\n+\n+#ifdef DEBUG\n+/**\n+ * This function is for debug only. It checks that a valid halt status is set\n+ * and that HCCHARn.chdis is clear. If there's a problem, corrective action is\n+ * taken and a warning is issued.\n+ * @return 1 if halt status is ok, 0 otherwise.\n+ */\n+static inline int halt_status_ok(dwc_otg_hcd_t * hcd,\n+\t\t\t\t dwc_hc_t * hc,\n+\t\t\t\t dwc_otg_hc_regs_t * hc_regs,\n+\t\t\t\t dwc_otg_qtd_t * qtd)\n+{\n+\thcchar_data_t hcchar;\n+\thctsiz_data_t hctsiz;\n+\thcint_data_t hcint;\n+\thcintmsk_data_t hcintmsk;\n+\thcsplt_data_t hcsplt;\n+\n+\tif (hc->halt_status == DWC_OTG_HC_XFER_NO_HALT_STATUS) {\n+\t\t/*\n+\t\t * This code is here only as a check. This condition should\n+\t\t * never happen. Ignore the halt if it does occur.\n+\t\t */\n+\t\thcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);\n+\t\thctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);\n+\t\thcint.d32 = DWC_READ_REG32(&hc_regs->hcint);\n+\t\thcintmsk.d32 = DWC_READ_REG32(&hc_regs->hcintmsk);\n+\t\thcsplt.d32 = DWC_READ_REG32(&hc_regs->hcsplt);\n+\t\tDWC_WARN\n+\t\t    (\"%s: hc->halt_status == DWC_OTG_HC_XFER_NO_HALT_STATUS, \"\n+\t\t     \"channel %d, hcchar 0x%08x, hctsiz 0x%08x, \"\n+\t\t     \"hcint 0x%08x, hcintmsk 0x%08x, \"\n+\t\t     \"hcsplt 0x%08x, qtd->complete_split %d\\n\", __func__,\n+\t\t     hc->hc_num, hcchar.d32, hctsiz.d32, hcint.d32,\n+\t\t     hcintmsk.d32, hcsplt.d32, qtd->complete_split);\n+\n+\t\tDWC_WARN(\"%s: no halt status, channel %d, ignoring interrupt\\n\",\n+\t\t\t __func__, hc->hc_num);\n+\t\tDWC_WARN(\"\\n\");\n+\t\tclear_hc_int(hc_regs, chhltd);\n+\t\treturn 0;\n+\t}\n+\n+\t/*\n+\t * This code is here only as a check. hcchar.chdis should\n+\t * never be set when the halt interrupt occurs. Halt the\n+\t * channel again if it does occur.\n+\t */\n+\thcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);\n+\tif (hcchar.b.chdis) {\n+\t\tDWC_WARN(\"%s: hcchar.chdis set unexpectedly, \"\n+\t\t\t \"hcchar 0x%08x, trying to halt again\\n\",\n+\t\t\t __func__, hcchar.d32);\n+\t\tclear_hc_int(hc_regs, chhltd);\n+\t\thc->halt_pending = 0;\n+\t\thalt_channel(hcd, hc, qtd, hc->halt_status);\n+\t\treturn 0;\n+\t}\n+\n+\treturn 1;\n+}\n+#endif\n+\n+/**\n+ * Handles a host Channel Halted interrupt in DMA mode. This handler\n+ * determines the reason the channel halted and proceeds accordingly.\n+ */\n+static void handle_hc_chhltd_intr_dma(dwc_otg_hcd_t * hcd,\n+\t\t\t\t      dwc_hc_t * hc,\n+\t\t\t\t      dwc_otg_hc_regs_t * hc_regs,\n+\t\t\t\t      dwc_otg_qtd_t * qtd)\n+{\n+\tint out_nak_enh = 0;\n+\thcint_data_t hcint;\n+\thcintmsk_data_t hcintmsk;\n+\t/* For core with OUT NAK enhancement, the flow for high-\n+\t * speed CONTROL/BULK OUT is handled a little differently.\n+\t */\n+\tif (hcd->core_if->snpsid >= OTG_CORE_REV_2_71a) {\n+\t\tif (hc->speed == DWC_OTG_EP_SPEED_HIGH && !hc->ep_is_in &&\n+\t\t    (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL ||\n+\t\t     hc->ep_type == DWC_OTG_EP_TYPE_BULK)) {\n+\t\t\tout_nak_enh = 1;\n+\t\t}\n+\t}\n+\n+\tif (hc->halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE ||\n+\t    (hc->halt_status == DWC_OTG_HC_XFER_AHB_ERR\n+\t     && !hcd->core_if->dma_desc_enable)) {\n+\t\t/*\n+\t\t * Just release the channel. A dequeue can happen on a\n+\t\t * transfer timeout. In the case of an AHB Error, the channel\n+\t\t * was forced to halt because there's no way to gracefully\n+\t\t * recover.\n+\t\t */\n+\t\tif (hcd->core_if->dma_desc_enable)\n+\t\t\tdwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs,\n+\t\t\t\t\t\t       hc->halt_status);\n+\t\telse\n+\t\t\trelease_channel(hcd, hc, qtd, hc->halt_status);\n+\t\treturn;\n+\t}\n+\n+\t/* Read the HCINTn register to determine the cause for the halt. */\n+\n+\thcint.d32 = DWC_READ_REG32(&hc_regs->hcint);\n+\thcintmsk.d32 = DWC_READ_REG32(&hc_regs->hcintmsk);\n+\n+\tif (hcint.b.xfercomp) {\n+\t\t/** @todo This is here because of a possible hardware bug.  Spec\n+\t\t * says that on SPLIT-ISOC OUT transfers in DMA mode that a HALT\n+\t\t * interrupt w/ACK bit set should occur, but I only see the\n+\t\t * XFERCOMP bit, even with it masked out.  This is a workaround\n+\t\t * for that behavior.  Should fix this when hardware is fixed.\n+\t\t */\n+\t\tif (hc->ep_type == DWC_OTG_EP_TYPE_ISOC && !hc->ep_is_in) {\n+\t\t\thandle_hc_ack_intr(hcd, hc, hc_regs, qtd);\n+\t\t}\n+\t\thandle_hc_xfercomp_intr(hcd, hc, hc_regs, qtd);\n+\t} else if (hcint.b.stall) {\n+\t\thandle_hc_stall_intr(hcd, hc, hc_regs, qtd);\n+\t} else if (hcint.b.xacterr && !hcd->core_if->dma_desc_enable) {\n+\t\tif (out_nak_enh) {\n+\t\t\tif (hcint.b.nyet || hcint.b.nak || hcint.b.ack) {\n+\t\t\t\tDWC_DEBUGPL(DBG_HCD, \"XactErr with NYET/NAK/ACK\\n\");\n+\t\t\t\tqtd->error_count = 0;\n+\t\t\t} else {\n+\t\t\t\tDWC_DEBUGPL(DBG_HCD, \"XactErr without NYET/NAK/ACK\\n\");\n+\t\t\t}\n+\t\t}\n+\n+\t\t/*\n+\t\t * Must handle xacterr before nak or ack. Could get a xacterr\n+\t\t * at the same time as either of these on a BULK/CONTROL OUT\n+\t\t * that started with a PING. The xacterr takes precedence.\n+\t\t */\n+\t\thandle_hc_xacterr_intr(hcd, hc, hc_regs, qtd);\n+\t} else if (hcint.b.xcs_xact && hcd->core_if->dma_desc_enable) {\n+\t\thandle_hc_xacterr_intr(hcd, hc, hc_regs, qtd);\n+\t} else if (hcint.b.ahberr && hcd->core_if->dma_desc_enable) {\n+\t\thandle_hc_ahberr_intr(hcd, hc, hc_regs, qtd);\n+\t} else if (hcint.b.bblerr) {\n+\t\thandle_hc_babble_intr(hcd, hc, hc_regs, qtd);\n+\t} else if (hcint.b.frmovrun) {\n+\t\thandle_hc_frmovrun_intr(hcd, hc, hc_regs, qtd);\n+\t} else if (hcint.b.datatglerr) {\n+\t\thandle_hc_datatglerr_intr(hcd, hc, hc_regs, qtd);\n+\t} else if (!out_nak_enh) {\n+\t\tif (hcint.b.nyet) {\n+\t\t\t/*\n+\t\t\t * Must handle nyet before nak or ack. Could get a nyet at the\n+\t\t\t * same time as either of those on a BULK/CONTROL OUT that\n+\t\t\t * started with a PING. The nyet takes precedence.\n+\t\t\t */\n+\t\t\thandle_hc_nyet_intr(hcd, hc, hc_regs, qtd);\n+\t\t} else if (hcint.b.nak && !hcintmsk.b.nak) {\n+\t\t\t/*\n+\t\t\t * If nak is not masked, it's because a non-split IN transfer\n+\t\t\t * is in an error state. In that case, the nak is handled by\n+\t\t\t * the nak interrupt handler, not here. Handle nak here for\n+\t\t\t * BULK/CONTROL OUT transfers, which halt on a NAK to allow\n+\t\t\t * rewinding the buffer pointer.\n+\t\t\t */\n+\t\t\thandle_hc_nak_intr(hcd, hc, hc_regs, qtd);\n+\t\t} else if (hcint.b.ack && !hcintmsk.b.ack) {\n+\t\t\t/*\n+\t\t\t * If ack is not masked, it's because a non-split IN transfer\n+\t\t\t * is in an error state. In that case, the ack is handled by\n+\t\t\t * the ack interrupt handler, not here. Handle ack here for\n+\t\t\t * split transfers. Start splits halt on ACK.\n+\t\t\t */\n+\t\t\thandle_hc_ack_intr(hcd, hc, hc_regs, qtd);\n+\t\t} else {\n+\t\t\tif (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||\n+\t\t\t    hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {\n+\t\t\t\t/*\n+\t\t\t\t * A periodic transfer halted with no other channel\n+\t\t\t\t * interrupts set. Assume it was halted by the core\n+\t\t\t\t * because it could not be completed in its scheduled\n+\t\t\t\t * (micro)frame.\n+\t\t\t\t */\n+#ifdef DEBUG\n+\t\t\t\tDWC_PRINTF\n+\t\t\t\t    (\"%s: Halt channel %d (assume incomplete periodic transfer)\\n\",\n+\t\t\t\t     __func__, hc->hc_num);\n+#endif\n+\t\t\t\thalt_channel(hcd, hc, qtd,\n+\t\t\t\t\t     DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE);\n+\t\t\t} else {\n+\t\t\t\tDWC_ERROR\n+\t\t\t\t    (\"%s: Channel %d, DMA Mode -- ChHltd set, but reason \"\n+\t\t\t\t     \"for halting is unknown, hcint 0x%08x, intsts 0x%08x\\n\",\n+\t\t\t\t     __func__, hc->hc_num, hcint.d32,\n+\t\t\t\t     DWC_READ_REG32(&hcd->\n+\t\t\t\t\t\t    core_if->core_global_regs->\n+\t\t\t\t\t\t    gintsts));\n+\t\t\t\t/* Failthrough: use 3-strikes rule */\n+\t\t\t\tqtd->error_count++;\n+\t\t\t\tdwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);\n+\t\t\t\tupdate_urb_state_xfer_intr(hc, hc_regs,\n+\t\t\t\t\t   qtd->urb, qtd, DWC_OTG_HC_XFER_XACT_ERR);\n+\t\t\t\thalt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR);\n+\t\t\t}\n+\n+\t\t}\n+\t} else {\n+\t\tDWC_PRINTF(\"NYET/NAK/ACK/other in non-error case, 0x%08x\\n\",\n+\t\t\t   hcint.d32);\n+\t\t/* Failthrough: use 3-strikes rule */\n+\t\tqtd->error_count++;\n+\t\tdwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);\n+\t\tupdate_urb_state_xfer_intr(hc, hc_regs,\n+\t\t\t   qtd->urb, qtd, DWC_OTG_HC_XFER_XACT_ERR);\n+\t\thalt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR);\n+\t}\n+}\n+\n+/**\n+ * Handles a host channel Channel Halted interrupt.\n+ *\n+ * In slave mode, this handler is called only when the driver specifically\n+ * requests a halt. This occurs during handling other host channel interrupts\n+ * (e.g. nak, xacterr, stall, nyet, etc.).\n+ *\n+ * In DMA mode, this is the interrupt that occurs when the core has finished\n+ * processing a transfer on a channel. Other host channel interrupts (except\n+ * ahberr) are disabled in DMA mode.\n+ */\n+static int32_t handle_hc_chhltd_intr(dwc_otg_hcd_t * hcd,\n+\t\t\t\t     dwc_hc_t * hc,\n+\t\t\t\t     dwc_otg_hc_regs_t * hc_regs,\n+\t\t\t\t     dwc_otg_qtd_t * qtd)\n+{\n+\tDWC_DEBUGPL(DBG_HCDI, \"--Host Channel %d Interrupt: \"\n+\t\t    \"Channel Halted--\\n\", hc->hc_num);\n+\n+\tif (hcd->core_if->dma_enable) {\n+\t\thandle_hc_chhltd_intr_dma(hcd, hc, hc_regs, qtd);\n+\t} else {\n+#ifdef DEBUG\n+\t\tif (!halt_status_ok(hcd, hc, hc_regs, qtd)) {\n+\t\t\treturn 1;\n+\t\t}\n+#endif\n+\t\trelease_channel(hcd, hc, qtd, hc->halt_status);\n+\t}\n+\n+\treturn 1;\n+}\n+\n+\n+/**\n+ * dwc_otg_fiq_unmangle_isoc() - Update the iso_frame_desc structure on\n+ * FIQ transfer completion\n+ * @hcd:\tPointer to dwc_otg_hcd struct\n+ * @num:\tHost channel number\n+ *\n+ * 1. Un-mangle the status as recorded in each iso_frame_desc status\n+ * 2. Copy it from the dwc_otg_urb into the real URB\n+ */\n+void dwc_otg_fiq_unmangle_isoc(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, dwc_otg_qtd_t *qtd, uint32_t num)\n+{\n+\tstruct dwc_otg_hcd_urb *dwc_urb = qtd->urb;\n+\tint nr_frames = dwc_urb->packet_count;\n+\tint i;\n+\thcint_data_t frame_hcint;\n+\n+\tfor (i = 0; i < nr_frames; i++) {\n+\t\tframe_hcint.d32 = dwc_urb->iso_descs[i].status;\n+\t\tif (frame_hcint.b.xfercomp) {\n+\t\t\tdwc_urb->iso_descs[i].status = 0;\n+\t\t\tdwc_urb->actual_length += dwc_urb->iso_descs[i].actual_length;\n+\t\t} else if (frame_hcint.b.frmovrun) {\n+\t\t\tif (qh->ep_is_in)\n+\t\t\t\tdwc_urb->iso_descs[i].status = -DWC_E_NO_STREAM_RES;\n+\t\t\telse\n+\t\t\t\tdwc_urb->iso_descs[i].status = -DWC_E_COMMUNICATION;\n+\t\t\tdwc_urb->error_count++;\n+\t\t\tdwc_urb->iso_descs[i].actual_length = 0;\n+\t\t} else if (frame_hcint.b.xacterr) {\n+\t\t\tdwc_urb->iso_descs[i].status = -DWC_E_PROTOCOL;\n+\t\t\tdwc_urb->error_count++;\n+\t\t\tdwc_urb->iso_descs[i].actual_length = 0;\n+\t\t} else if (frame_hcint.b.bblerr) {\n+\t\t\tdwc_urb->iso_descs[i].status = -DWC_E_OVERFLOW;\n+\t\t\tdwc_urb->error_count++;\n+\t\t\tdwc_urb->iso_descs[i].actual_length = 0;\n+\t\t} else {\n+\t\t\t/* Something went wrong */\n+\t\t\tdwc_urb->iso_descs[i].status = -1;\n+\t\t\tdwc_urb->iso_descs[i].actual_length = 0;\n+\t\t\tdwc_urb->error_count++;\n+\t\t}\n+\t}\n+\tqh->sched_frame = dwc_frame_num_inc(qh->sched_frame, qh->interval * (nr_frames - 1));\n+\n+\t//printk_ratelimited(KERN_INFO \"%s: HS isochronous of %d/%d frames with %d errors complete\\n\",\n+\t//\t\t\t__FUNCTION__, i, dwc_urb->packet_count, dwc_urb->error_count);\n+}\n+\n+/**\n+ * dwc_otg_fiq_unsetup_per_dma() - Remove data from bounce buffers for split transactions\n+ * @hcd:\tPointer to dwc_otg_hcd struct\n+ * @num:\tHost channel number\n+ *\n+ * Copies data from the FIQ bounce buffers into the URB's transfer buffer. Does not modify URB state.\n+ * Returns total length of data or -1 if the buffers were not used.\n+ *\n+ */\n+int dwc_otg_fiq_unsetup_per_dma(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, dwc_otg_qtd_t *qtd, uint32_t num)\n+{\n+\tdwc_hc_t *hc = qh->channel;\n+\tstruct fiq_dma_blob *blob = hcd->fiq_dmab;\n+\tstruct fiq_channel_state *st = &hcd->fiq_state->channel[num];\n+\tuint8_t *ptr = NULL;\n+\tint index = 0, len = 0;\n+\tint i = 0;\n+\tif (hc->ep_is_in) {\n+\t\t/* Copy data out of the DMA bounce buffers to the URB's buffer.\n+\t\t * The align_buf is ignored as this is ignored on FSM enqueue. */\n+\t\tptr = qtd->urb->buf;\n+\t\tif (qh->ep_type == UE_ISOCHRONOUS) {\n+\t\t\t/* Isoc IN transactions - grab the offset of the iso_frame_desc into the URB transfer buffer */\n+\t\t\tindex = qtd->isoc_frame_index;\n+\t\t\tptr += qtd->urb->iso_descs[index].offset;\n+\t\t} else {\n+\t\t\t/* Need to increment by actual_length for interrupt IN */\n+\t\t\tptr += qtd->urb->actual_length;\n+\t\t}\n+\n+\t\tfor (i = 0; i < st->dma_info.index; i++) {\n+\t\t\tlen += st->dma_info.slot_len[i];\n+\t\t\tdwc_memcpy(ptr, &blob->channel[num].index[i].buf[0], st->dma_info.slot_len[i]);\n+\t\t\tptr += st->dma_info.slot_len[i];\n+\t\t}\n+\t\treturn len;\n+\t} else {\n+\t\t/* OUT endpoints - nothing to do. */\n+\t\treturn -1;\n+\t}\n+\n+}\n+/**\n+ * dwc_otg_hcd_handle_hc_fsm() - handle an unmasked channel interrupt\n+ * \t\t\t\t from a channel handled in the FIQ\n+ * @hcd:\tPointer to dwc_otg_hcd struct\n+ * @num:\tHost channel number\n+ *\n+ * If a host channel interrupt was received by the IRQ and this was a channel\n+ * used by the FIQ, the execution flow for transfer completion is substantially\n+ * different from the normal (messy) path. This function and its friends handles\n+ * channel cleanup and transaction completion from a FIQ transaction.\n+ */\n+void dwc_otg_hcd_handle_hc_fsm(dwc_otg_hcd_t *hcd, uint32_t num)\n+{\n+\tstruct fiq_channel_state *st = &hcd->fiq_state->channel[num];\n+\tdwc_hc_t *hc = hcd->hc_ptr_array[num];\n+\tdwc_otg_qtd_t *qtd;\n+\tdwc_otg_hc_regs_t *hc_regs = hcd->core_if->host_if->hc_regs[num];\n+\thcint_data_t hcint = hcd->fiq_state->channel[num].hcint_copy;\n+\thctsiz_data_t hctsiz = hcd->fiq_state->channel[num].hctsiz_copy;\n+\tint hostchannels  = 0;\n+\tfiq_print(FIQDBG_INT, hcd->fiq_state, \"OUT %01d %01d \", num , st->fsm);\n+\n+\thostchannels = hcd->available_host_channels;\n+\tif (hc->halt_pending) {\n+\t\t/* Dequeue: The FIQ was allowed to complete the transfer but state has been cleared. */\n+\t\tif (hc->qh && st->fsm == FIQ_NP_SPLIT_DONE &&\n+\t\t\t\thcint.b.xfercomp && hc->qh->ep_type == UE_BULK) {\n+\t\t\tif (hctsiz.b.pid == DWC_HCTSIZ_DATA0) {\n+\t\t\t\thc->qh->data_toggle = DWC_OTG_HC_PID_DATA1;\n+\t\t\t} else {\n+\t\t\t\thc->qh->data_toggle = DWC_OTG_HC_PID_DATA0;\n+\t\t\t}\n+\t\t}\n+\t\trelease_channel(hcd, hc, NULL, hc->halt_status);\n+\t\treturn;\n+\t}\n+\n+\tqtd = DWC_CIRCLEQ_FIRST(&hc->qh->qtd_list);\n+\tswitch (st->fsm) {\n+\tcase FIQ_TEST:\n+\t\tbreak;\n+\n+\tcase FIQ_DEQUEUE_ISSUED:\n+\t\t/* Handled above, but keep for posterity */\n+\t\trelease_channel(hcd, hc, NULL, hc->halt_status);\n+\t\tbreak;\n+\n+\tcase FIQ_NP_SPLIT_DONE:\n+\t\t/* Nonperiodic transaction complete. */\n+\t\tif (!hc->ep_is_in) {\n+\t\t\tqtd->ssplit_out_xfer_count = hc->xfer_len;\n+\t\t}\n+\t\tif (hcint.b.xfercomp) {\n+\t\t\thandle_hc_xfercomp_intr(hcd, hc, hc_regs, qtd);\n+\t\t} else if (hcint.b.nak) {\n+\t\t\thandle_hc_nak_intr(hcd, hc, hc_regs, qtd);\n+\t\t} else {\n+\t\t\tDWC_WARN(\"Unexpected IRQ state on FSM transaction:\"\n+\t\t\t\t\t\"dev_addr=%d ep=%d fsm=%d, hcint=0x%08x\\n\",\n+\t\t\t\thc->dev_addr, hc->ep_num, st->fsm, hcint.d32);\n+\t\t\trelease_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS);\n+\t\t}\n+\t\tbreak;\n+\n+\tcase FIQ_NP_SPLIT_HS_ABORTED:\n+\t\t/* A HS abort is a 3-strikes on the HS bus at any point in the transaction.\n+\t\t * Normally a CLEAR_TT_BUFFER hub command would be required: we can't do that\n+\t\t * because there's no guarantee which order a non-periodic split happened in.\n+\t\t * We could end up clearing a perfectly good transaction out of the buffer.\n+\t\t */\n+\t\tif (hcint.b.xacterr) {\n+\t\t\tqtd->error_count += st->nr_errors;\n+\t\t\thandle_hc_xacterr_intr(hcd, hc, hc_regs, qtd);\n+\t\t} else if (hcint.b.ahberr) {\n+\t\t\thandle_hc_ahberr_intr(hcd, hc, hc_regs, qtd);\n+\t\t} else {\n+\t\t\tDWC_WARN(\"Unexpected IRQ state on FSM transaction:\"\n+\t\t\t\t\t\"dev_addr=%d ep=%d fsm=%d, hcint=0x%08x\\n\",\n+\t\t\t\thc->dev_addr, hc->ep_num, st->fsm, hcint.d32);\n+\t\t\trelease_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS);\n+\t\t}\n+\t\tbreak;\n+\n+\tcase FIQ_NP_SPLIT_LS_ABORTED:\n+\t\t/* A few cases can cause this - either an unknown state on a SSPLIT or\n+\t\t * STALL/data toggle error response on a CSPLIT */\n+\t\tif (hcint.b.stall) {\n+\t\t\thandle_hc_stall_intr(hcd, hc, hc_regs, qtd);\n+\t\t} else if (hcint.b.datatglerr) {\n+\t\t\thandle_hc_datatglerr_intr(hcd, hc, hc_regs, qtd);\n+\t\t} else if (hcint.b.bblerr) {\n+\t\t\thandle_hc_babble_intr(hcd, hc, hc_regs, qtd);\n+\t\t} else if (hcint.b.ahberr) {\n+\t\t\thandle_hc_ahberr_intr(hcd, hc, hc_regs, qtd);\n+\t\t} else {\n+\t\t\tDWC_WARN(\"Unexpected IRQ state on FSM transaction:\"\n+\t\t\t\t\t\"dev_addr=%d ep=%d fsm=%d, hcint=0x%08x\\n\",\n+\t\t\t\thc->dev_addr, hc->ep_num, st->fsm, hcint.d32);\n+\t\t\trelease_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS);\n+\t\t}\n+\t\tbreak;\n+\n+\tcase FIQ_PER_SPLIT_DONE:\n+\t\t/* Isoc IN or Interrupt IN/OUT */\n+\n+\t\t/* Flow control here is different from the normal execution by the driver.\n+\t\t* We need to completely ignore most of the driver's method of handling\n+\t\t* split transactions and do it ourselves.\n+\t\t*/\n+\t\tif (hc->ep_type == UE_INTERRUPT) {\n+\t\t\tif (hcint.b.nak) {\n+\t\t\t\t\thandle_hc_nak_intr(hcd, hc, hc_regs, qtd);\n+\t\t\t} else if (hc->ep_is_in) {\n+\t\t\t\tint len;\n+\t\t\t\tlen = dwc_otg_fiq_unsetup_per_dma(hcd, hc->qh, qtd, num);\n+\t\t\t\t//printk(KERN_NOTICE \"FIQ Transaction: hc=%d len=%d urb_len = %d\\n\", num, len, qtd->urb->length);\n+\t\t\t\tqtd->urb->actual_length += len;\n+\t\t\t\tif (qtd->urb->actual_length >= qtd->urb->length) {\n+\t\t\t\t\tqtd->urb->status = 0;\n+\t\t\t\t\thcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, qtd->urb->status);\n+\t\t\t\t\trelease_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE);\n+\t\t\t\t} else {\n+\t\t\t\t\t/* Interrupt transfer not complete yet - is it a short read? */\n+\t\t\t\t\tif (len < hc->max_packet) {\n+\t\t\t\t\t\t/* Interrupt transaction complete */\n+\t\t\t\t\t\tqtd->urb->status = 0;\n+\t\t\t\t\t\thcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, qtd->urb->status);\n+\t\t\t\t\t\trelease_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE);\n+\t\t\t\t\t} else {\n+\t\t\t\t\t\t/* Further transactions required */\n+\t\t\t\t\t\trelease_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_COMPLETE);\n+\t\t\t\t\t}\n+\t\t\t\t}\n+\t\t\t} else {\n+\t\t\t\t/* Interrupt OUT complete. */\n+\t\t\t\tdwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);\n+\t\t\t\tqtd->urb->actual_length += hc->xfer_len;\n+\t\t\t\tif (qtd->urb->actual_length >= qtd->urb->length) {\n+\t\t\t\t\tqtd->urb->status = 0;\n+\t\t\t\t\thcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, qtd->urb->status);\n+\t\t\t\t\trelease_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE);\n+\t\t\t\t} else {\n+\t\t\t\t\trelease_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_COMPLETE);\n+\t\t\t\t}\n+\t\t\t}\n+\t\t} else {\n+\t\t\t/* ISOC IN complete. */\n+\t\t\tstruct dwc_otg_hcd_iso_packet_desc *frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index];\n+\t\t\tint len = 0;\n+\t\t\t/* Record errors, update qtd. */\n+\t\t\tif (st->nr_errors) {\n+\t\t\t\tframe_desc->actual_length = 0;\n+\t\t\t\tframe_desc->status = -DWC_E_PROTOCOL;\n+\t\t\t} else {\n+\t\t\t\tframe_desc->status = 0;\n+\t\t\t\t/* Unswizzle dma */\n+\t\t\t\tlen = dwc_otg_fiq_unsetup_per_dma(hcd, hc->qh, qtd, num);\n+\t\t\t\tframe_desc->actual_length = len;\n+\t\t\t}\n+\t\t\tqtd->isoc_frame_index++;\n+\t\t\tif (qtd->isoc_frame_index == qtd->urb->packet_count) {\n+\t\t\t\thcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0);\n+\t\t\t\trelease_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE);\n+\t\t\t} else {\n+\t\t\t\trelease_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_COMPLETE);\n+\t\t\t}\n+\t\t}\n+\t\tbreak;\n+\n+\tcase FIQ_PER_ISO_OUT_DONE: {\n+\t\t\tstruct dwc_otg_hcd_iso_packet_desc *frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index];\n+\t\t\t/* Record errors, update qtd. */\n+\t\t\tif (st->nr_errors) {\n+\t\t\t\tframe_desc->actual_length = 0;\n+\t\t\t\tframe_desc->status = -DWC_E_PROTOCOL;\n+\t\t\t} else {\n+\t\t\t\tframe_desc->status = 0;\n+\t\t\t\tframe_desc->actual_length = frame_desc->length;\n+\t\t\t}\n+\t\t\tqtd->isoc_frame_index++;\n+\t\t\tqtd->isoc_split_offset = 0;\n+\t\t\tif (qtd->isoc_frame_index == qtd->urb->packet_count) {\n+\t\t\t\thcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0);\n+\t\t\t\trelease_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE);\n+\t\t\t} else {\n+\t\t\t\trelease_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_COMPLETE);\n+\t\t\t}\n+\t\t}\n+\t\tbreak;\n+\n+\tcase FIQ_PER_SPLIT_NYET_ABORTED:\n+\t\t/* Doh. lost the data. */\n+\t\tprintk_ratelimited(KERN_INFO \"Transfer to device %d endpoint 0x%x frame %d failed \"\n+\t\t\t\t\"- FIQ reported NYET. Data may have been lost.\\n\",\n+\t\t\t\thc->dev_addr, hc->ep_num, dwc_otg_hcd_get_frame_number(hcd) >> 3);\n+\t\tif (hc->ep_type == UE_ISOCHRONOUS) {\n+\t\t\tstruct dwc_otg_hcd_iso_packet_desc *frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index];\n+\t\t\t/* Record errors, update qtd. */\n+\t\t\tframe_desc->actual_length = 0;\n+\t\t\tframe_desc->status = -DWC_E_PROTOCOL;\n+\t\t\tqtd->isoc_frame_index++;\n+\t\t\tqtd->isoc_split_offset = 0;\n+\t\t\tif (qtd->isoc_frame_index == qtd->urb->packet_count) {\n+\t\t\t\thcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0);\n+\t\t\t\trelease_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE);\n+\t\t\t} else {\n+\t\t\t\trelease_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_COMPLETE);\n+\t\t\t}\n+\t\t} else {\n+\t\t\trelease_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS);\n+\t\t}\n+\t\tbreak;\n+\n+\tcase FIQ_HS_ISOC_DONE:\n+\t\t/* The FIQ has performed a whole pile of isochronous transactions.\n+\t\t * The status is recorded as the interrupt state should the transaction\n+\t\t * fail.\n+\t\t */\n+\t\tdwc_otg_fiq_unmangle_isoc(hcd, hc->qh, qtd, num);\n+\t\thcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0);\n+\t\trelease_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE);\n+\t\tbreak;\n+\n+\tcase FIQ_PER_SPLIT_LS_ABORTED:\n+\t\tif (hcint.b.xacterr) {\n+\t\t\t/* Hub has responded with an ERR packet. Device\n+\t\t\t * has been unplugged or the port has been disabled.\n+\t\t\t * TODO: need to issue a reset to the hub port. */\n+\t\t\tqtd->error_count += 3;\n+\t\t\thandle_hc_xacterr_intr(hcd, hc, hc_regs, qtd);\n+\t\t} else if (hcint.b.stall) {\n+\t\t\thandle_hc_stall_intr(hcd, hc, hc_regs, qtd);\n+\t\t} else if (hcint.b.bblerr) {\n+\t\t\thandle_hc_babble_intr(hcd, hc, hc_regs, qtd);\n+\t\t} else {\n+\t\t\tprintk_ratelimited(KERN_INFO \"Transfer to device %d endpoint 0x%x failed \"\n+\t\t\t\t\"- FIQ reported FSM=%d. Data may have been lost.\\n\",\n+\t\t\t\tst->fsm, hc->dev_addr, hc->ep_num);\n+\t\t\trelease_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS);\n+\t\t}\n+\t\tbreak;\n+\n+\tcase FIQ_PER_SPLIT_HS_ABORTED:\n+\t\t/* Either the SSPLIT phase suffered transaction errors or something\n+\t\t * unexpected happened.\n+\t\t */\n+\t\tqtd->error_count += 3;\n+\t\thandle_hc_xacterr_intr(hcd, hc, hc_regs, qtd);\n+\t\trelease_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS);\n+\t\tbreak;\n+\n+\tcase FIQ_PER_SPLIT_TIMEOUT:\n+\t\t/* Couldn't complete in the nominated frame */\n+\t\tprintk(KERN_INFO \"Transfer to device %d endpoint 0x%x frame %d failed \"\n+\t\t\t\t\"- FIQ timed out. Data may have been lost.\\n\",\n+\t\t\t\thc->dev_addr, hc->ep_num, dwc_otg_hcd_get_frame_number(hcd) >> 3);\n+\t\tif (hc->ep_type == UE_ISOCHRONOUS) {\n+\t\t\tstruct dwc_otg_hcd_iso_packet_desc *frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index];\n+\t\t\t/* Record errors, update qtd. */\n+\t\t\tframe_desc->actual_length = 0;\n+\t\t\tif (hc->ep_is_in) {\n+\t\t\t\tframe_desc->status = -DWC_E_NO_STREAM_RES;\n+\t\t\t} else {\n+\t\t\t\tframe_desc->status = -DWC_E_COMMUNICATION;\n+\t\t\t}\n+\t\t\tqtd->isoc_frame_index++;\n+\t\t\tif (qtd->isoc_frame_index == qtd->urb->packet_count) {\n+\t\t\t\thcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0);\n+\t\t\t\trelease_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE);\n+\t\t\t} else {\n+\t\t\t\trelease_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_COMPLETE);\n+\t\t\t}\n+\t\t} else {\n+\t\t\trelease_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS);\n+\t\t}\n+\t\tbreak;\n+\n+\tdefault:\n+\t\tDWC_WARN(\"Unexpected state received on hc=%d fsm=%d on transfer to device %d ep 0x%x\", \n+\t\t\t\t\thc->hc_num, st->fsm, hc->dev_addr, hc->ep_num);\n+\t\tqtd->error_count++;\n+\t\trelease_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS);\n+\t}\n+\treturn;\n+}\n+\n+/** Handles interrupt for a specific Host Channel */\n+int32_t dwc_otg_hcd_handle_hc_n_intr(dwc_otg_hcd_t * dwc_otg_hcd, uint32_t num)\n+{\n+\tint retval = 0;\n+\thcint_data_t hcint;\n+\thcintmsk_data_t hcintmsk;\n+\tdwc_hc_t *hc;\n+\tdwc_otg_hc_regs_t *hc_regs;\n+\tdwc_otg_qtd_t *qtd;\n+\n+\tDWC_DEBUGPL(DBG_HCDV, \"--Host Channel Interrupt--, Channel %d\\n\", num);\n+\n+\thc = dwc_otg_hcd->hc_ptr_array[num];\n+\thc_regs = dwc_otg_hcd->core_if->host_if->hc_regs[num];\n+\tif(hc->halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE) {\n+\t\t/* A dequeue was issued for this transfer. Our QTD has gone away\n+\t\t * but in the case of a FIQ transfer, the transfer would have run\n+\t\t * to completion.\n+\t\t */\n+\t\tif (fiq_fsm_enable && dwc_otg_hcd->fiq_state->channel[num].fsm != FIQ_PASSTHROUGH) {\n+\t\t\tdwc_otg_hcd_handle_hc_fsm(dwc_otg_hcd, num);\n+\t\t} else {\n+\t\t\trelease_channel(dwc_otg_hcd, hc, NULL, hc->halt_status);\n+\t\t}\n+\t\treturn 1;\n+\t}\n+\tqtd = DWC_CIRCLEQ_FIRST(&hc->qh->qtd_list);\n+\n+\t/*\n+\t * FSM mode: Check to see if this is a HC interrupt from a channel handled by the FIQ.\n+\t * Execution path is fundamentally different for the channels after a FIQ has completed\n+\t * a split transaction.\n+\t */\n+\tif (fiq_fsm_enable) {\n+\t\tswitch (dwc_otg_hcd->fiq_state->channel[num].fsm) {\n+\t\t\tcase FIQ_PASSTHROUGH:\n+\t\t\t\tbreak;\n+\t\t\tcase FIQ_PASSTHROUGH_ERRORSTATE:\n+\t\t\t\t/* Hook into the error count */\n+\t\t\t\tfiq_print(FIQDBG_ERR, dwc_otg_hcd->fiq_state, \"HCDERR%02d\", num);\n+\t\t\t\tif (!dwc_otg_hcd->fiq_state->channel[num].nr_errors) {\n+\t\t\t\t\tqtd->error_count = 0;\n+\t\t\t\t\tfiq_print(FIQDBG_ERR, dwc_otg_hcd->fiq_state, \"RESET   \");\n+\t\t\t\t}\n+\t\t\t\tbreak;\n+\t\t\tdefault:\n+\t\t\t\tdwc_otg_hcd_handle_hc_fsm(dwc_otg_hcd, num);\n+\t\t\t\treturn 1;\n+\t\t}\n+\t}\n+\n+\thcint.d32 = DWC_READ_REG32(&hc_regs->hcint);\n+\thcintmsk.d32 = DWC_READ_REG32(&hc_regs->hcintmsk);\n+\thcint.d32 = hcint.d32 & hcintmsk.d32;\n+\tif (!dwc_otg_hcd->core_if->dma_enable) {\n+\t\tif (hcint.b.chhltd && hcint.d32 != 0x2) {\n+\t\t\thcint.b.chhltd = 0;\n+\t\t}\n+\t}\n+\n+\tif (hcint.b.xfercomp) {\n+\t\tretval |=\n+\t\t    handle_hc_xfercomp_intr(dwc_otg_hcd, hc, hc_regs, qtd);\n+\t\t/*\n+\t\t * If NYET occurred at same time as Xfer Complete, the NYET is\n+\t\t * handled by the Xfer Complete interrupt handler. Don't want\n+\t\t * to call the NYET interrupt handler in this case.\n+\t\t */\n+\t\thcint.b.nyet = 0;\n+\t}\n+\tif (hcint.b.chhltd) {\n+\t\tretval |= handle_hc_chhltd_intr(dwc_otg_hcd, hc, hc_regs, qtd);\n+\t}\n+\tif (hcint.b.ahberr) {\n+\t\tretval |= handle_hc_ahberr_intr(dwc_otg_hcd, hc, hc_regs, qtd);\n+\t}\n+\tif (hcint.b.stall) {\n+\t\tretval |= handle_hc_stall_intr(dwc_otg_hcd, hc, hc_regs, qtd);\n+\t}\n+\tif (hcint.b.nak) {\n+\t\tretval |= handle_hc_nak_intr(dwc_otg_hcd, hc, hc_regs, qtd);\n+\t}\n+\tif (hcint.b.ack) {\n+\t\tif(!hcint.b.chhltd)\n+\t\t\tretval |= handle_hc_ack_intr(dwc_otg_hcd, hc, hc_regs, qtd);\n+\t}\n+\tif (hcint.b.nyet) {\n+\t\tretval |= handle_hc_nyet_intr(dwc_otg_hcd, hc, hc_regs, qtd);\n+\t}\n+\tif (hcint.b.xacterr) {\n+\t\tretval |= handle_hc_xacterr_intr(dwc_otg_hcd, hc, hc_regs, qtd);\n+\t}\n+\tif (hcint.b.bblerr) {\n+\t\tretval |= handle_hc_babble_intr(dwc_otg_hcd, hc, hc_regs, qtd);\n+\t}\n+\tif (hcint.b.frmovrun) {\n+\t\tretval |=\n+\t\t    handle_hc_frmovrun_intr(dwc_otg_hcd, hc, hc_regs, qtd);\n+\t}\n+\tif (hcint.b.datatglerr) {\n+\t\tretval |=\n+\t\t    handle_hc_datatglerr_intr(dwc_otg_hcd, hc, hc_regs, qtd);\n+\t}\n+\n+\treturn retval;\n+}\n+#endif /* DWC_DEVICE_ONLY */\n--- /dev/null\n+++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c\n@@ -0,0 +1,1086 @@\n+\n+/* ==========================================================================\n+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_linux.c $\n+ * $Revision: #20 $\n+ * $Date: 2011/10/26 $\n+ * $Change: 1872981 $\n+ *\n+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,\n+ * \"Software\") is an Unsupported proprietary work of Synopsys, Inc. unless\n+ * otherwise expressly agreed to in writing between Synopsys and you.\n+ *\n+ * The Software IS NOT an item of Licensed Software or Licensed Product under\n+ * any End User Software License Agreement or Agreement for Licensed Product\n+ * with Synopsys or any supplement thereto. You are permitted to use and\n+ * redistribute this Software in source and binary forms, with or without\n+ * modification, provided that redistributions of source code must retain this\n+ * notice. You may not view, use, disclose, copy or distribute this file or\n+ * any information contained herein except pursuant to this license grant from\n+ * Synopsys. If you do not agree with this notice, including the disclaimer\n+ * below, then you are not authorized to use the Software.\n+ *\n+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN \"AS IS\" BASIS\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,\n+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH\n+ * DAMAGE.\n+ * ========================================================================== */\n+#ifndef DWC_DEVICE_ONLY\n+\n+/**\n+ * @file\n+ *\n+ * This file contains the implementation of the HCD. In Linux, the HCD\n+ * implements the hc_driver API.\n+ */\n+#include <linux/kernel.h>\n+#include <linux/module.h>\n+#include <linux/moduleparam.h>\n+#include <linux/init.h>\n+#include <linux/device.h>\n+#include <linux/errno.h>\n+#include <linux/list.h>\n+#include <linux/interrupt.h>\n+#include <linux/string.h>\n+#include <linux/dma-mapping.h>\n+#include <linux/version.h>\n+#include <asm/io.h>\n+#ifdef CONFIG_ARM\n+#include <asm/fiq.h>\n+#endif\n+#include <linux/usb.h>\n+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,35)\n+#include <../drivers/usb/core/hcd.h>\n+#else\n+#include <linux/usb/hcd.h>\n+#endif\n+#include <asm/bug.h>\n+\n+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,30))\n+#define USB_URB_EP_LINKING 1\n+#else\n+#define USB_URB_EP_LINKING 0\n+#endif\n+\n+#include \"dwc_otg_hcd_if.h\"\n+#include \"dwc_otg_dbg.h\"\n+#include \"dwc_otg_driver.h\"\n+#include \"dwc_otg_hcd.h\"\n+\n+#ifndef __virt_to_bus\n+#define __virt_to_bus\t__virt_to_phys\n+#define __bus_to_virt\t__phys_to_virt\n+#define __pfn_to_bus(x)\t__pfn_to_phys(x)\n+#define __bus_to_pfn(x)\t__phys_to_pfn(x)\n+#endif\n+\n+extern unsigned char  _dwc_otg_fiq_stub, _dwc_otg_fiq_stub_end;\n+\n+/**\n+ * Gets the endpoint number from a _bEndpointAddress argument. The endpoint is\n+ * qualified with its direction (possible 32 endpoints per device).\n+ */\n+#define dwc_ep_addr_to_endpoint(_bEndpointAddress_) ((_bEndpointAddress_ & USB_ENDPOINT_NUMBER_MASK) | \\\n+\t\t\t\t\t\t     ((_bEndpointAddress_ & USB_DIR_IN) != 0) << 4)\n+\n+static const char dwc_otg_hcd_name[] = \"dwc_otg_hcd\";\n+\n+extern bool fiq_enable;\n+\n+/** @name Linux HC Driver API Functions */\n+/** @{ */\n+/* manage i/o requests, device state */\n+static int dwc_otg_urb_enqueue(struct usb_hcd *hcd,\n+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28)\n+\t\t       struct usb_host_endpoint *ep,\n+#endif\n+\t\t       struct urb *urb, gfp_t mem_flags);\n+\n+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30)\n+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28)\n+static int dwc_otg_urb_dequeue(struct usb_hcd *hcd, struct urb *urb);\n+#endif\n+#else /* kernels at or post 2.6.30 */\n+static int dwc_otg_urb_dequeue(struct usb_hcd *hcd,\n+                               struct urb *urb, int status);\n+#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30) */\n+\n+static void endpoint_disable(struct usb_hcd *hcd, struct usb_host_endpoint *ep);\n+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,30)\n+static void endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *ep);\n+#endif\n+static irqreturn_t dwc_otg_hcd_irq(struct usb_hcd *hcd);\n+extern int hcd_start(struct usb_hcd *hcd);\n+extern void hcd_stop(struct usb_hcd *hcd);\n+static int get_frame_number(struct usb_hcd *hcd);\n+extern int hub_status_data(struct usb_hcd *hcd, char *buf);\n+extern int hub_control(struct usb_hcd *hcd,\n+\t\t       u16 typeReq,\n+\t\t       u16 wValue, u16 wIndex, char *buf, u16 wLength);\n+\n+struct wrapper_priv_data {\n+\tdwc_otg_hcd_t *dwc_otg_hcd;\n+};\n+\n+/** @} */\n+\n+static struct hc_driver dwc_otg_hc_driver = {\n+\n+\t.description = dwc_otg_hcd_name,\n+\t.product_desc = \"DWC OTG Controller\",\n+\t.hcd_priv_size = sizeof(struct wrapper_priv_data),\n+\n+\t.irq = dwc_otg_hcd_irq,\n+\n+\t.flags = HCD_MEMORY | HCD_DMA | HCD_USB2,\n+\n+\t//.reset =\n+\t.start = hcd_start,\n+\t//.suspend =\n+\t//.resume =\n+\t.stop = hcd_stop,\n+\n+\t.urb_enqueue = dwc_otg_urb_enqueue,\n+\t.urb_dequeue = dwc_otg_urb_dequeue,\n+\t.endpoint_disable = endpoint_disable,\n+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,30)\n+\t.endpoint_reset = endpoint_reset,\n+#endif\n+\t.get_frame_number = get_frame_number,\n+\n+\t.hub_status_data = hub_status_data,\n+\t.hub_control = hub_control,\n+\t//.bus_suspend =\n+\t//.bus_resume =\n+};\n+\n+/** Gets the dwc_otg_hcd from a struct usb_hcd */\n+static inline dwc_otg_hcd_t *hcd_to_dwc_otg_hcd(struct usb_hcd *hcd)\n+{\n+\tstruct wrapper_priv_data *p;\n+\tp = (struct wrapper_priv_data *)(hcd->hcd_priv);\n+\treturn p->dwc_otg_hcd;\n+}\n+\n+/** Gets the struct usb_hcd that contains a dwc_otg_hcd_t. */\n+static inline struct usb_hcd *dwc_otg_hcd_to_hcd(dwc_otg_hcd_t * dwc_otg_hcd)\n+{\n+\treturn dwc_otg_hcd_get_priv_data(dwc_otg_hcd);\n+}\n+\n+/** Gets the usb_host_endpoint associated with an URB. */\n+inline struct usb_host_endpoint *dwc_urb_to_endpoint(struct urb *urb)\n+{\n+\tstruct usb_device *dev = urb->dev;\n+\tint ep_num = usb_pipeendpoint(urb->pipe);\n+\n+\tif (usb_pipein(urb->pipe))\n+\t\treturn dev->ep_in[ep_num];\n+\telse\n+\t\treturn dev->ep_out[ep_num];\n+}\n+\n+static int _disconnect(dwc_otg_hcd_t * hcd)\n+{\n+\tstruct usb_hcd *usb_hcd = dwc_otg_hcd_to_hcd(hcd);\n+\n+\tusb_hcd->self.is_b_host = 0;\n+\treturn 0;\n+}\n+\n+static int _start(dwc_otg_hcd_t * hcd)\n+{\n+\tstruct usb_hcd *usb_hcd = dwc_otg_hcd_to_hcd(hcd);\n+\n+\tusb_hcd->self.is_b_host = dwc_otg_hcd_is_b_host(hcd);\n+\thcd_start(usb_hcd);\n+\n+\treturn 0;\n+}\n+\n+static int _hub_info(dwc_otg_hcd_t * hcd, void *urb_handle, uint32_t * hub_addr,\n+\t\t     uint32_t * port_addr)\n+{\n+   struct urb *urb = (struct urb *)urb_handle;\n+   struct usb_bus *bus;\n+#if 1 //GRAYG - temporary\n+   if (NULL == urb_handle)\n+      DWC_ERROR(\"**** %s - NULL URB handle\\n\", __func__);//GRAYG\n+   if (NULL == urb->dev)\n+      DWC_ERROR(\"**** %s - URB has no device\\n\", __func__);//GRAYG\n+   if (NULL == port_addr)\n+      DWC_ERROR(\"**** %s - NULL port_address\\n\", __func__);//GRAYG\n+#endif\n+   if (urb->dev->tt) {\n+        if (NULL == urb->dev->tt->hub) {\n+                DWC_ERROR(\"**** %s - (URB's transactor has no TT - giving no hub)\\n\",\n+                           __func__); //GRAYG\n+                //*hub_addr = (u8)usb_pipedevice(urb->pipe); //GRAYG\n+                *hub_addr = 0; //GRAYG\n+                // we probably shouldn't have a transaction translator if\n+                // there's no associated hub?\n+        } else {\n+\t\tbus = hcd_to_bus(dwc_otg_hcd_to_hcd(hcd));\n+\t\tif (urb->dev->tt->hub == bus->root_hub)\n+\t\t\t*hub_addr = 0;\n+\t\telse\n+\t\t\t*hub_addr = urb->dev->tt->hub->devnum;\n+\t}\n+\t*port_addr = urb->dev->ttport;\n+   } else {\n+        *hub_addr = 0;\n+\t*port_addr = urb->dev->ttport;\n+   }\n+   return 0;\n+}\n+\n+static int _speed(dwc_otg_hcd_t * hcd, void *urb_handle)\n+{\n+\tstruct urb *urb = (struct urb *)urb_handle;\n+\treturn urb->dev->speed;\n+}\n+\n+static int _get_b_hnp_enable(dwc_otg_hcd_t * hcd)\n+{\n+\tstruct usb_hcd *usb_hcd = dwc_otg_hcd_to_hcd(hcd);\n+\treturn usb_hcd->self.b_hnp_enable;\n+}\n+\n+static void allocate_bus_bandwidth(struct usb_hcd *hcd, uint32_t bw,\n+\t\t\t\t   struct urb *urb)\n+{\n+\thcd_to_bus(hcd)->bandwidth_allocated += bw / urb->interval;\n+\tif (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {\n+\t\thcd_to_bus(hcd)->bandwidth_isoc_reqs++;\n+\t} else {\n+\t\thcd_to_bus(hcd)->bandwidth_int_reqs++;\n+\t}\n+}\n+\n+static void free_bus_bandwidth(struct usb_hcd *hcd, uint32_t bw,\n+\t\t\t       struct urb *urb)\n+{\n+\thcd_to_bus(hcd)->bandwidth_allocated -= bw / urb->interval;\n+\tif (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {\n+\t\thcd_to_bus(hcd)->bandwidth_isoc_reqs--;\n+\t} else {\n+\t\thcd_to_bus(hcd)->bandwidth_int_reqs--;\n+\t}\n+}\n+\n+/**\n+ * Sets the final status of an URB and returns it to the device driver. Any\n+ * required cleanup of the URB is performed.  The HCD lock should be held on\n+ * entry.\n+ */\n+static int _complete(dwc_otg_hcd_t * hcd, void *urb_handle,\n+\t\t     dwc_otg_hcd_urb_t * dwc_otg_urb, int32_t status)\n+{\n+\tstruct urb *urb = (struct urb *)urb_handle;\n+\turb_tq_entry_t *new_entry;\n+\tint rc = 0;\n+\tif (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {\n+\t\tDWC_PRINTF(\"%s: urb %p, device %d, ep %d %s, status=%d\\n\",\n+\t\t\t   __func__, urb, usb_pipedevice(urb->pipe),\n+\t\t\t   usb_pipeendpoint(urb->pipe),\n+\t\t\t   usb_pipein(urb->pipe) ? \"IN\" : \"OUT\", status);\n+\t\tif (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {\n+\t\t\tint i;\n+\t\t\tfor (i = 0; i < urb->number_of_packets; i++) {\n+\t\t\t\tDWC_PRINTF(\"  ISO Desc %d status: %d\\n\",\n+\t\t\t\t\t   i, urb->iso_frame_desc[i].status);\n+\t\t\t}\n+\t\t}\n+\t}\n+\tnew_entry = DWC_ALLOC_ATOMIC(sizeof(urb_tq_entry_t));\n+\turb->actual_length = dwc_otg_hcd_urb_get_actual_length(dwc_otg_urb);\n+\t/* Convert status value. */\n+\tswitch (status) {\n+\tcase -DWC_E_PROTOCOL:\n+\t\tstatus = -EPROTO;\n+\t\tbreak;\n+\tcase -DWC_E_IN_PROGRESS:\n+\t\tstatus = -EINPROGRESS;\n+\t\tbreak;\n+\tcase -DWC_E_PIPE:\n+\t\tstatus = -EPIPE;\n+\t\tbreak;\n+\tcase -DWC_E_IO:\n+\t\tstatus = -EIO;\n+\t\tbreak;\n+\tcase -DWC_E_TIMEOUT:\n+\t\tstatus = -ETIMEDOUT;\n+\t\tbreak;\n+\tcase -DWC_E_OVERFLOW:\n+\t\tstatus = -EOVERFLOW;\n+\t\tbreak;\n+\tcase -DWC_E_SHUTDOWN:\n+\t\tstatus = -ESHUTDOWN;\n+\t\tbreak;\n+\tdefault:\n+\t\tif (status) {\n+\t\t\tDWC_PRINTF(\"Uknown urb status %d\\n\", status);\n+\n+\t\t}\n+\t}\n+\n+\tif (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {\n+\t\tint i;\n+\n+\t\turb->error_count = dwc_otg_hcd_urb_get_error_count(dwc_otg_urb);\n+\t\turb->actual_length = 0;\n+\t\tfor (i = 0; i < urb->number_of_packets; ++i) {\n+\t\t\turb->iso_frame_desc[i].actual_length =\n+\t\t\t    dwc_otg_hcd_urb_get_iso_desc_actual_length\n+\t\t\t    (dwc_otg_urb, i);\n+\t\t\turb->actual_length += urb->iso_frame_desc[i].actual_length;\n+\t\t\turb->iso_frame_desc[i].status =\n+\t\t\t    dwc_otg_hcd_urb_get_iso_desc_status(dwc_otg_urb, i);\n+\t\t}\n+\t}\n+\n+\turb->status = status;\n+\turb->hcpriv = NULL;\n+\tif (!status) {\n+\t\tif ((urb->transfer_flags & URB_SHORT_NOT_OK) &&\n+\t\t    (urb->actual_length < urb->transfer_buffer_length)) {\n+\t\t\turb->status = -EREMOTEIO;\n+\t\t}\n+\t}\n+\n+\tif ((usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) ||\n+\t    (usb_pipetype(urb->pipe) == PIPE_INTERRUPT)) {\n+\t\tstruct usb_host_endpoint *ep = dwc_urb_to_endpoint(urb);\n+\t\tif (ep) {\n+\t\t\tfree_bus_bandwidth(dwc_otg_hcd_to_hcd(hcd),\n+\t\t\t\t\t   dwc_otg_hcd_get_ep_bandwidth(hcd,\n+\t\t\t\t\t\t\t\t\tep->hcpriv),\n+\t\t\t\t\t   urb);\n+\t\t}\n+\t}\n+\tDWC_FREE(dwc_otg_urb);\n+\tif (!new_entry) {\n+\t\tDWC_ERROR(\"dwc_otg_hcd: complete: cannot allocate URB TQ entry\\n\");\n+\t\turb->status = -EPROTO;\n+\t\t/* don't schedule the tasklet -\n+\t\t * directly return the packet here with error. */\n+#if USB_URB_EP_LINKING\n+\t\tusb_hcd_unlink_urb_from_ep(dwc_otg_hcd_to_hcd(hcd), urb);\n+#endif\n+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28)\n+\t\tusb_hcd_giveback_urb(dwc_otg_hcd_to_hcd(hcd), urb);\n+#else\n+\t\tusb_hcd_giveback_urb(dwc_otg_hcd_to_hcd(hcd), urb, urb->status);\n+#endif\n+\t} else {\n+\t\tnew_entry->urb = urb;\n+#if USB_URB_EP_LINKING\n+\t\trc = usb_hcd_check_unlink_urb(dwc_otg_hcd_to_hcd(hcd), urb, urb->status);\n+\t\tif(0 == rc) {\n+\t\t\tusb_hcd_unlink_urb_from_ep(dwc_otg_hcd_to_hcd(hcd), urb);\n+\t\t}\n+#endif\n+\t\tif(0 == rc) {\n+\t\t\tDWC_TAILQ_INSERT_TAIL(&hcd->completed_urb_list, new_entry,\n+\t\t\t\t\t\turb_tq_entries);\n+\t\t\tDWC_TASK_HI_SCHEDULE(hcd->completion_tasklet);\n+\t\t}\n+\t}\n+\treturn 0;\n+}\n+\n+static struct dwc_otg_hcd_function_ops hcd_fops = {\n+\t.start = _start,\n+\t.disconnect = _disconnect,\n+\t.hub_info = _hub_info,\n+\t.speed = _speed,\n+\t.complete = _complete,\n+\t.get_b_hnp_enable = _get_b_hnp_enable,\n+};\n+\n+#ifdef CONFIG_ARM64\n+\n+static int simfiq_irq = -1;\n+\n+void local_fiq_enable(void)\n+{\n+\tif (simfiq_irq >= 0)\n+\t\tenable_irq(simfiq_irq);\n+}\n+\n+void local_fiq_disable(void)\n+{\n+\tif (simfiq_irq >= 0)\n+\t\tdisable_irq(simfiq_irq);\n+}\n+\n+irqreturn_t fiq_irq_handler(int irq, void *dev_id)\n+{\n+\tdwc_otg_hcd_t *dwc_otg_hcd = (dwc_otg_hcd_t *)dev_id;\n+\n+\tif (fiq_fsm_enable)\n+\t\tdwc_otg_fiq_fsm(dwc_otg_hcd->fiq_state, dwc_otg_hcd->core_if->core_params->host_channels);\n+\telse\n+\t\tdwc_otg_fiq_nop(dwc_otg_hcd->fiq_state);\n+\n+\treturn IRQ_HANDLED;\n+}\n+\n+#else\n+static struct fiq_handler fh = {\n+  .name = \"usb_fiq\",\n+};\n+\n+#endif\n+\n+static void hcd_init_fiq(void *cookie)\n+{\n+\tdwc_otg_device_t *otg_dev = cookie;\n+\tdwc_otg_hcd_t *dwc_otg_hcd = otg_dev->hcd;\n+#ifdef CONFIG_ARM64\n+\tint retval = 0;\n+\tint irq;\n+#else\n+\tstruct pt_regs regs;\n+\tint irq;\n+\n+\tif (claim_fiq(&fh)) {\n+\t\tDWC_ERROR(\"Can't claim FIQ\");\n+\t\tBUG();\n+\t}\n+\tDWC_WARN(\"FIQ on core %d\", smp_processor_id());\n+\tDWC_WARN(\"FIQ ASM at %px length %d\", &_dwc_otg_fiq_stub, (int)(&_dwc_otg_fiq_stub_end - &_dwc_otg_fiq_stub));\n+\tset_fiq_handler((void *) &_dwc_otg_fiq_stub, &_dwc_otg_fiq_stub_end - &_dwc_otg_fiq_stub);\n+\tmemset(&regs,0,sizeof(regs));\n+\n+\tregs.ARM_r8 = (long) dwc_otg_hcd->fiq_state;\n+\tif (fiq_fsm_enable) {\n+\t\tregs.ARM_r9 = dwc_otg_hcd->core_if->core_params->host_channels;\n+\t\t//regs.ARM_r10 = dwc_otg_hcd->dma;\n+\t\tregs.ARM_fp = (long) dwc_otg_fiq_fsm;\n+\t} else {\n+\t\tregs.ARM_fp = (long) dwc_otg_fiq_nop;\n+\t}\n+\n+\tregs.ARM_sp = (long) dwc_otg_hcd->fiq_stack + (sizeof(struct fiq_stack) - 4);\n+\n+//\t\t__show_regs(&regs);\n+\tset_fiq_regs(&regs);\n+#endif\n+\n+\tdwc_otg_hcd->fiq_state->dwc_regs_base = otg_dev->os_dep.base;\n+\t//Set the mphi periph to the required registers\n+\tdwc_otg_hcd->fiq_state->mphi_regs.base    = otg_dev->os_dep.mphi_base;\n+\tif (otg_dev->os_dep.use_swirq) {\n+\t\tdwc_otg_hcd->fiq_state->mphi_regs.swirq_set =\n+\t\t\totg_dev->os_dep.mphi_base + 0x1f0;\n+\t\tdwc_otg_hcd->fiq_state->mphi_regs.swirq_clr =\n+\t\t\totg_dev->os_dep.mphi_base + 0x1f4;\n+\t\tDWC_WARN(\"Fake MPHI regs_base at 0x%08x\",\n+\t\t\t (int)dwc_otg_hcd->fiq_state->mphi_regs.base);\n+\t} else {\n+\t\tdwc_otg_hcd->fiq_state->mphi_regs.ctrl =\n+\t\t\totg_dev->os_dep.mphi_base + 0x4c;\n+\t\tdwc_otg_hcd->fiq_state->mphi_regs.outdda\n+\t\t\t= otg_dev->os_dep.mphi_base + 0x28;\n+\t\tdwc_otg_hcd->fiq_state->mphi_regs.outddb\n+\t\t\t= otg_dev->os_dep.mphi_base + 0x2c;\n+\t\tdwc_otg_hcd->fiq_state->mphi_regs.intstat\n+\t\t\t= otg_dev->os_dep.mphi_base + 0x50;\n+\t\tDWC_WARN(\"MPHI regs_base at %px\",\n+\t\t\t dwc_otg_hcd->fiq_state->mphi_regs.base);\n+\n+\t\t//Enable mphi peripheral\n+\t\twritel((1<<31),dwc_otg_hcd->fiq_state->mphi_regs.ctrl);\n+#ifdef DEBUG\n+\t\tif (readl(dwc_otg_hcd->fiq_state->mphi_regs.ctrl) & 0x80000000)\n+\t\t\tDWC_WARN(\"MPHI periph has been enabled\");\n+\t\telse\n+\t\t\tDWC_WARN(\"MPHI periph has NOT been enabled\");\n+#endif\n+\t}\n+\t// Enable FIQ interrupt from USB peripheral\n+#ifdef CONFIG_ARM64\n+\tirq = otg_dev->os_dep.fiq_num;\n+\n+\tif (irq < 0) {\n+\t\tDWC_ERROR(\"Can't get SIM-FIQ irq\");\n+\t\treturn;\n+\t}\n+\n+\tretval = request_irq(irq, fiq_irq_handler, 0, \"dwc_otg_sim-fiq\", dwc_otg_hcd);\n+\n+\tif (retval < 0) {\n+\t\tDWC_ERROR(\"Unable to request SIM-FIQ irq\\n\");\n+\t\treturn;\n+\t}\n+\n+\tsimfiq_irq = irq;\n+#else\n+#ifdef CONFIG_GENERIC_IRQ_MULTI_HANDLER\n+\tirq = otg_dev->os_dep.fiq_num;\n+#else\n+\tirq = INTERRUPT_VC_USB;\n+#endif\n+\tif (irq < 0) {\n+\t\tDWC_ERROR(\"Can't get FIQ irq\");\n+\t\treturn;\n+\t}\n+\t/*\n+\t * We could take an interrupt immediately after enabling the FIQ.\n+\t * Ensure coherency of hcd->fiq_state.\n+\t */\n+\tsmp_mb();\n+\tenable_fiq(irq);\n+\tlocal_fiq_enable();\n+#endif\n+\n+}\n+\n+/**\n+ * Initializes the HCD. This function allocates memory for and initializes the\n+ * static parts of the usb_hcd and dwc_otg_hcd structures. It also registers the\n+ * USB bus with the core and calls the hc_driver->start() function. It returns\n+ * a negative error on failure.\n+ */\n+int hcd_init(dwc_bus_dev_t *_dev)\n+{\n+\tstruct usb_hcd *hcd = NULL;\n+\tdwc_otg_hcd_t *dwc_otg_hcd = NULL;\n+\tdwc_otg_device_t *otg_dev = DWC_OTG_BUSDRVDATA(_dev);\n+\tint retval = 0;\n+        u64 dmamask;\n+\n+\tDWC_DEBUGPL(DBG_HCD, \"DWC OTG HCD INIT otg_dev=%p\\n\", otg_dev);\n+\n+\t/* Set device flags indicating whether the HCD supports DMA. */\n+\tif (dwc_otg_is_dma_enable(otg_dev->core_if))\n+                dmamask = DMA_BIT_MASK(32);\n+        else\n+                dmamask = 0;\n+\n+#if    defined(LM_INTERFACE) || defined(PLATFORM_INTERFACE)\n+        dma_set_mask(&_dev->dev, dmamask);\n+        dma_set_coherent_mask(&_dev->dev, dmamask);\n+#elif  defined(PCI_INTERFACE)\n+        pci_set_dma_mask(_dev, dmamask);\n+        pci_set_consistent_dma_mask(_dev, dmamask);\n+#endif\n+\n+\t/*\n+\t * Allocate memory for the base HCD plus the DWC OTG HCD.\n+\t * Initialize the base HCD.\n+\t */\n+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30)\n+\thcd = usb_create_hcd(&dwc_otg_hc_driver, &_dev->dev, _dev->dev.bus_id);\n+#else\n+\thcd = usb_create_hcd(&dwc_otg_hc_driver, &_dev->dev, dev_name(&_dev->dev));\n+\thcd->has_tt = 1;\n+//      hcd->uses_new_polling = 1;\n+//      hcd->poll_rh = 0;\n+#endif\n+\tif (!hcd) {\n+\t\tretval = -ENOMEM;\n+\t\tgoto error1;\n+\t}\n+\n+\thcd->regs = otg_dev->os_dep.base;\n+\n+\n+\t/* Initialize the DWC OTG HCD. */\n+\tdwc_otg_hcd = dwc_otg_hcd_alloc_hcd();\n+\tif (!dwc_otg_hcd) {\n+\t\tgoto error2;\n+\t}\n+\t((struct wrapper_priv_data *)(hcd->hcd_priv))->dwc_otg_hcd =\n+\t    dwc_otg_hcd;\n+\totg_dev->hcd = dwc_otg_hcd;\n+\totg_dev->hcd->otg_dev = otg_dev;\n+\n+#ifdef CONFIG_ARM64\n+\tif (dwc_otg_hcd_init(dwc_otg_hcd, otg_dev->core_if))\n+\t\tgoto error2;\n+\n+\tif (fiq_enable)\n+\t\thcd_init_fiq(otg_dev);\n+#else\n+\tif (dwc_otg_hcd_init(dwc_otg_hcd, otg_dev->core_if)) {\n+\t\tgoto error2;\n+\t}\n+\n+\tif (fiq_enable) {\n+\t\tif (num_online_cpus() > 1) {\n+\t\t\t/*\n+\t\t\t * bcm2709: can run the FIQ on a separate core to IRQs.\n+\t\t\t * Ensure driver state is visible to other cores before setting up the FIQ.\n+\t\t\t */\n+\t\t\tsmp_mb();\n+\t\t\tsmp_call_function_single(1, hcd_init_fiq, otg_dev, 1);\n+\t\t} else {\n+\t\t\tsmp_call_function_single(0, hcd_init_fiq, otg_dev, 1);\n+\t\t}\n+\t}\n+#endif\n+\n+\thcd->self.otg_port = dwc_otg_hcd_otg_port(dwc_otg_hcd);\n+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,33) //don't support for LM(with 2.6.20.1 kernel)\n+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,35) //version field absent later\n+\thcd->self.otg_version = dwc_otg_get_otg_version(otg_dev->core_if);\n+#endif\n+\t/* Don't support SG list at this point */\n+\thcd->self.sg_tablesize = 0;\n+#endif\n+\t/*\n+\t * Finish generic HCD initialization and start the HCD. This function\n+\t * allocates the DMA buffer pool, registers the USB bus, requests the\n+\t * IRQ line, and calls hcd_start method.\n+\t */\n+\tretval = usb_add_hcd(hcd, otg_dev->os_dep.irq_num, IRQF_SHARED);\n+\tif (retval < 0) {\n+\t\tgoto error2;\n+\t}\n+\n+\tdwc_otg_hcd_set_priv_data(dwc_otg_hcd, hcd);\n+\treturn 0;\n+\n+error2:\n+\tusb_put_hcd(hcd);\n+error1:\n+\treturn retval;\n+}\n+\n+/**\n+ * Removes the HCD.\n+ * Frees memory and resources associated with the HCD and deregisters the bus.\n+ */\n+void hcd_remove(dwc_bus_dev_t *_dev)\n+{\n+\tdwc_otg_device_t *otg_dev = DWC_OTG_BUSDRVDATA(_dev);\n+\tdwc_otg_hcd_t *dwc_otg_hcd;\n+\tstruct usb_hcd *hcd;\n+\n+\tDWC_DEBUGPL(DBG_HCD, \"DWC OTG HCD REMOVE otg_dev=%p\\n\", otg_dev);\n+\n+\tif (!otg_dev) {\n+\t\tDWC_DEBUGPL(DBG_ANY, \"%s: otg_dev NULL!\\n\", __func__);\n+\t\treturn;\n+\t}\n+\n+\tdwc_otg_hcd = otg_dev->hcd;\n+\n+\tif (!dwc_otg_hcd) {\n+\t\tDWC_DEBUGPL(DBG_ANY, \"%s: otg_dev->hcd NULL!\\n\", __func__);\n+\t\treturn;\n+\t}\n+\n+\thcd = dwc_otg_hcd_to_hcd(dwc_otg_hcd);\n+\n+\tif (!hcd) {\n+\t\tDWC_DEBUGPL(DBG_ANY,\n+\t\t\t    \"%s: dwc_otg_hcd_to_hcd(dwc_otg_hcd) NULL!\\n\",\n+\t\t\t    __func__);\n+\t\treturn;\n+\t}\n+\tusb_remove_hcd(hcd);\n+\tdwc_otg_hcd_set_priv_data(dwc_otg_hcd, NULL);\n+\tdwc_otg_hcd_remove(dwc_otg_hcd);\n+\tusb_put_hcd(hcd);\n+}\n+\n+/* =========================================================================\n+ *  Linux HC Driver Functions\n+ * ========================================================================= */\n+\n+/** Initializes the DWC_otg controller and its root hub and prepares it for host\n+ * mode operation. Activates the root port. Returns 0 on success and a negative\n+ * error code on failure. */\n+int hcd_start(struct usb_hcd *hcd)\n+{\n+\tdwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);\n+\tstruct usb_bus *bus;\n+\n+\tDWC_DEBUGPL(DBG_HCD, \"DWC OTG HCD START\\n\");\n+\tbus = hcd_to_bus(hcd);\n+\n+\thcd->state = HC_STATE_RUNNING;\n+\tif (dwc_otg_hcd_start(dwc_otg_hcd, &hcd_fops)) {\n+\t\treturn 0;\n+\t}\n+\n+\t/* Initialize and connect root hub if one is not already attached */\n+\tif (bus->root_hub) {\n+\t\tDWC_DEBUGPL(DBG_HCD, \"DWC OTG HCD Has Root Hub\\n\");\n+\t\t/* Inform the HUB driver to resume. */\n+\t\tusb_hcd_resume_root_hub(hcd);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+/**\n+ * Halts the DWC_otg host mode operations in a clean manner. USB transfers are\n+ * stopped.\n+ */\n+void hcd_stop(struct usb_hcd *hcd)\n+{\n+\tdwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);\n+\n+\tdwc_otg_hcd_stop(dwc_otg_hcd);\n+}\n+\n+/** Returns the current frame number. */\n+static int get_frame_number(struct usb_hcd *hcd)\n+{\n+\thprt0_data_t hprt0;\n+\tdwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);\n+\thprt0.d32 = DWC_READ_REG32(dwc_otg_hcd->core_if->host_if->hprt0);\n+\tif (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_HIGH_SPEED)\n+\t\treturn dwc_otg_hcd_get_frame_number(dwc_otg_hcd) >> 3;\n+\telse\n+\t\treturn dwc_otg_hcd_get_frame_number(dwc_otg_hcd);\n+}\n+\n+#ifdef DEBUG\n+static void dump_urb_info(struct urb *urb, char *fn_name)\n+{\n+\tDWC_PRINTF(\"%s, urb %p\\n\", fn_name, urb);\n+\tDWC_PRINTF(\"  Device address: %d\\n\", usb_pipedevice(urb->pipe));\n+\tDWC_PRINTF(\"  Endpoint: %d, %s\\n\", usb_pipeendpoint(urb->pipe),\n+\t\t   (usb_pipein(urb->pipe) ? \"IN\" : \"OUT\"));\n+\tDWC_PRINTF(\"  Endpoint type: %s\\n\", ( {\n+\t\t\t\t\t     char *pipetype;\n+\t\t\t\t\t     switch (usb_pipetype(urb->pipe)) {\n+case PIPE_CONTROL:\n+pipetype = \"CONTROL\"; break; case PIPE_BULK:\n+pipetype = \"BULK\"; break; case PIPE_INTERRUPT:\n+pipetype = \"INTERRUPT\"; break; case PIPE_ISOCHRONOUS:\n+pipetype = \"ISOCHRONOUS\"; break; default:\n+\t\t\t\t\t     pipetype = \"UNKNOWN\"; break;};\n+\t\t\t\t\t     pipetype;}\n+\t\t   )) ;\n+\tDWC_PRINTF(\"  Speed: %s\\n\", ( {\n+\t\t\t\t     char *speed; switch (urb->dev->speed) {\n+case USB_SPEED_HIGH:\n+speed = \"HIGH\"; break; case USB_SPEED_FULL:\n+speed = \"FULL\"; break; case USB_SPEED_LOW:\n+speed = \"LOW\"; break; default:\n+\t\t\t\t     speed = \"UNKNOWN\"; break;};\n+\t\t\t\t     speed;}\n+\t\t   )) ;\n+\tDWC_PRINTF(\"  Max packet size: %d\\n\",\n+\t\t   usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe)));\n+\tDWC_PRINTF(\"  Data buffer length: %d\\n\", urb->transfer_buffer_length);\n+\tDWC_PRINTF(\"  Transfer buffer: %p, Transfer DMA: %p\\n\",\n+\t\t   urb->transfer_buffer, (void *)urb->transfer_dma);\n+\tDWC_PRINTF(\"  Setup buffer: %p, Setup DMA: %p\\n\",\n+\t\t   urb->setup_packet, (void *)urb->setup_dma);\n+\tDWC_PRINTF(\"  Interval: %d\\n\", urb->interval);\n+\tif (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {\n+\t\tint i;\n+\t\tfor (i = 0; i < urb->number_of_packets; i++) {\n+\t\t\tDWC_PRINTF(\"  ISO Desc %d:\\n\", i);\n+\t\t\tDWC_PRINTF(\"    offset: %d, length %d\\n\",\n+\t\t\t\t   urb->iso_frame_desc[i].offset,\n+\t\t\t\t   urb->iso_frame_desc[i].length);\n+\t\t}\n+\t}\n+}\n+#endif\n+\n+/** Starts processing a USB transfer request specified by a USB Request Block\n+ * (URB). mem_flags indicates the type of memory allocation to use while\n+ * processing this URB. */\n+static int dwc_otg_urb_enqueue(struct usb_hcd *hcd,\n+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28)\n+\t\t       struct usb_host_endpoint *ep,\n+#endif\n+\t\t       struct urb *urb, gfp_t mem_flags)\n+{\n+\tint retval = 0;\n+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,28)\n+\tstruct usb_host_endpoint *ep = urb->ep;\n+#endif\n+\tdwc_irqflags_t irqflags;\n+        void **ref_ep_hcpriv = &ep->hcpriv;\n+\tdwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);\n+\tdwc_otg_hcd_urb_t *dwc_otg_urb;\n+\tint i;\n+\tint alloc_bandwidth = 0;\n+\tuint8_t ep_type = 0;\n+\tuint32_t flags = 0;\n+\tvoid *buf;\n+\n+#ifdef DEBUG\n+\tif (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {\n+\t\tdump_urb_info(urb, \"dwc_otg_urb_enqueue\");\n+\t}\n+#endif\n+\tif ((usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)\n+\t    || (usb_pipetype(urb->pipe) == PIPE_INTERRUPT)) {\n+\t\tif (!dwc_otg_hcd_is_bandwidth_allocated\n+\t\t    (dwc_otg_hcd, ref_ep_hcpriv)) {\n+\t\t\talloc_bandwidth = 1;\n+\t\t}\n+\t}\n+\n+\tswitch (usb_pipetype(urb->pipe)) {\n+\tcase PIPE_CONTROL:\n+\t\tep_type = USB_ENDPOINT_XFER_CONTROL;\n+\t\tbreak;\n+\tcase PIPE_ISOCHRONOUS:\n+\t\tep_type = USB_ENDPOINT_XFER_ISOC;\n+\t\tbreak;\n+\tcase PIPE_BULK:\n+\t\tep_type = USB_ENDPOINT_XFER_BULK;\n+\t\tbreak;\n+\tcase PIPE_INTERRUPT:\n+\t\tep_type = USB_ENDPOINT_XFER_INT;\n+\t\tbreak;\n+\tdefault:\n+                DWC_WARN(\"Wrong EP type - %d\\n\", usb_pipetype(urb->pipe));\n+\t}\n+\n+        /* # of packets is often 0 - do we really need to call this then? */\n+\tdwc_otg_urb = dwc_otg_hcd_urb_alloc(dwc_otg_hcd,\n+\t\t\t\t\t    urb->number_of_packets,\n+\t\t\t\t\t    mem_flags == GFP_ATOMIC ? 1 : 0);\n+\n+\tif(dwc_otg_urb == NULL)\n+\t\treturn -ENOMEM;\n+\n+\tif (!dwc_otg_urb && urb->number_of_packets)\n+\t\treturn -ENOMEM;\n+\n+\tdwc_otg_hcd_urb_set_pipeinfo(dwc_otg_urb, usb_pipedevice(urb->pipe),\n+\t\t\t\t     usb_pipeendpoint(urb->pipe), ep_type,\n+\t\t\t\t     usb_pipein(urb->pipe),\n+\t\t\t\t     usb_maxpacket(urb->dev, urb->pipe,\n+\t\t\t\t\t\t   !(usb_pipein(urb->pipe))));\n+\n+\tbuf = urb->transfer_buffer;\n+\tif (hcd_uses_dma(hcd) && !buf && urb->transfer_buffer_length) {\n+\t\t/*\n+\t\t * Calculate virtual address from physical address,\n+\t\t * because some class driver may not fill transfer_buffer.\n+\t\t * In Buffer DMA mode virual address is used,\n+\t\t * when handling non DWORD aligned buffers.\n+\t\t */\n+\t\tbuf = (void *)__bus_to_virt((unsigned long)urb->transfer_dma);\n+\t\tdev_warn_once(&urb->dev->dev,\n+\t\t\t      \"USB transfer_buffer was NULL, will use __bus_to_virt(%pad)=%p\\n\",\n+\t\t\t      &urb->transfer_dma, buf);\n+\t}\n+\n+\tif (!buf && urb->transfer_buffer_length) {\n+\t\tDWC_FREE(dwc_otg_urb);\n+\t\tDWC_ERROR(\"transfer_buffer is NULL in PIO mode or both \"\n+\t\t\t   \"transfer_buffer and transfer_dma are NULL in DMA mode\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (!(urb->transfer_flags & URB_NO_INTERRUPT))\n+\t\tflags |= URB_GIVEBACK_ASAP;\n+\tif (urb->transfer_flags & URB_ZERO_PACKET)\n+\t\tflags |= URB_SEND_ZERO_PACKET;\n+\n+\tdwc_otg_hcd_urb_set_params(dwc_otg_urb, urb, buf,\n+\t\t\t\t   urb->transfer_dma,\n+\t\t\t\t   urb->transfer_buffer_length,\n+\t\t\t\t   urb->setup_packet,\n+\t\t\t\t   urb->setup_dma, flags, urb->interval);\n+\n+\tfor (i = 0; i < urb->number_of_packets; ++i) {\n+\t\tdwc_otg_hcd_urb_set_iso_desc_params(dwc_otg_urb, i,\n+\t\t\t\t\t\t    urb->\n+\t\t\t\t\t\t    iso_frame_desc[i].offset,\n+\t\t\t\t\t\t    urb->\n+\t\t\t\t\t\t    iso_frame_desc[i].length);\n+\t}\n+\n+\tDWC_SPINLOCK_IRQSAVE(dwc_otg_hcd->lock, &irqflags);\n+\turb->hcpriv = dwc_otg_urb;\n+#if USB_URB_EP_LINKING\n+\tretval = usb_hcd_link_urb_to_ep(hcd, urb);\n+\tif (0 == retval)\n+#endif\n+\t{\n+\t\tretval = dwc_otg_hcd_urb_enqueue(dwc_otg_hcd, dwc_otg_urb,\n+\t\t\t\t\t\t/*(dwc_otg_qh_t **)*/\n+\t\t\t\t\t\tref_ep_hcpriv, 1);\n+\t\tif (0 == retval) {\n+\t\t\tif (alloc_bandwidth) {\n+\t\t\t\tallocate_bus_bandwidth(hcd,\n+\t\t\t\t\t\tdwc_otg_hcd_get_ep_bandwidth(\n+\t\t\t\t\t\t\tdwc_otg_hcd, *ref_ep_hcpriv),\n+\t\t\t\t\t\turb);\n+\t\t\t}\n+\t\t} else {\n+\t\t\tDWC_DEBUGPL(DBG_HCD, \"DWC OTG dwc_otg_hcd_urb_enqueue failed rc %d\\n\", retval);\n+#if USB_URB_EP_LINKING\n+\t\t\tusb_hcd_unlink_urb_from_ep(hcd, urb);\n+#endif\n+\t\t\tDWC_FREE(dwc_otg_urb);\n+\t\t\turb->hcpriv = NULL;\n+\t\t\tif (retval == -DWC_E_NO_DEVICE)\n+\t\t\t\tretval = -ENODEV;\n+\t\t}\n+\t}\n+#if USB_URB_EP_LINKING\n+\telse\n+\t{\n+\t\tDWC_FREE(dwc_otg_urb);\n+\t\turb->hcpriv = NULL;\n+\t}\n+#endif\n+\tDWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock, irqflags);\n+\treturn retval;\n+}\n+\n+/** Aborts/cancels a USB transfer request. Always returns 0 to indicate\n+ * success.  */\n+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28)\n+static int dwc_otg_urb_dequeue(struct usb_hcd *hcd, struct urb *urb)\n+#else\n+static int dwc_otg_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)\n+#endif\n+{\n+\tdwc_irqflags_t flags;\n+\tdwc_otg_hcd_t *dwc_otg_hcd;\n+        int rc;\n+\n+\tDWC_DEBUGPL(DBG_HCD, \"DWC OTG HCD URB Dequeue\\n\");\n+\n+\tdwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);\n+\n+#ifdef DEBUG\n+\tif (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {\n+\t\tdump_urb_info(urb, \"dwc_otg_urb_dequeue\");\n+\t}\n+#endif\n+\n+\tDWC_SPINLOCK_IRQSAVE(dwc_otg_hcd->lock, &flags);\n+\trc = usb_hcd_check_unlink_urb(hcd, urb, status);\n+\tif (0 == rc) {\n+\t\tif(urb->hcpriv != NULL) {\n+\t                dwc_otg_hcd_urb_dequeue(dwc_otg_hcd,\n+\t                                    (dwc_otg_hcd_urb_t *)urb->hcpriv);\n+\n+\t\t        DWC_FREE(urb->hcpriv);\n+\t\t\turb->hcpriv = NULL;\n+\t\t}\n+        }\n+\n+        if (0 == rc) {\n+\t\t/* Higher layer software sets URB status. */\n+#if USB_URB_EP_LINKING\n+                usb_hcd_unlink_urb_from_ep(hcd, urb);\n+#endif\n+\t\tDWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock, flags);\n+\n+\n+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28)\n+                usb_hcd_giveback_urb(hcd, urb);\n+#else\n+                usb_hcd_giveback_urb(hcd, urb, status);\n+#endif\n+                if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {\n+                        DWC_PRINTF(\"Called usb_hcd_giveback_urb() \\n\");\n+                        DWC_PRINTF(\"  1urb->status = %d\\n\", urb->status);\n+                }\n+                DWC_DEBUGPL(DBG_HCD, \"DWC OTG HCD URB Dequeue OK\\n\");\n+        } else {\n+\t\tDWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock, flags);\n+                DWC_DEBUGPL(DBG_HCD, \"DWC OTG HCD URB Dequeue failed - rc %d\\n\",\n+                            rc);\n+        }\n+\n+\treturn rc;\n+}\n+\n+/* Frees resources in the DWC_otg controller related to a given endpoint. Also\n+ * clears state in the HCD related to the endpoint. Any URBs for the endpoint\n+ * must already be dequeued. */\n+static void endpoint_disable(struct usb_hcd *hcd, struct usb_host_endpoint *ep)\n+{\n+\tdwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);\n+\n+\tDWC_DEBUGPL(DBG_HCD,\n+\t\t    \"DWC OTG HCD EP DISABLE: _bEndpointAddress=0x%02x, \"\n+\t\t    \"endpoint=%d\\n\", ep->desc.bEndpointAddress,\n+\t\t    dwc_ep_addr_to_endpoint(ep->desc.bEndpointAddress));\n+\tdwc_otg_hcd_endpoint_disable(dwc_otg_hcd, ep->hcpriv, 250);\n+\tep->hcpriv = NULL;\n+}\n+\n+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,30)\n+/* Resets endpoint specific parameter values, in current version used to reset\n+ * the data toggle(as a WA). This function can be called from usb_clear_halt routine */\n+static void endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *ep)\n+{\n+\tdwc_irqflags_t flags;\n+\tdwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);\n+\n+\tDWC_DEBUGPL(DBG_HCD, \"DWC OTG HCD EP RESET: Endpoint Num=0x%02d\\n\", epnum);\n+\n+\tDWC_SPINLOCK_IRQSAVE(dwc_otg_hcd->lock, &flags);\n+\tif (ep->hcpriv) {\n+\t\tdwc_otg_hcd_endpoint_reset(dwc_otg_hcd, ep->hcpriv);\n+\t}\n+\tDWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock, flags);\n+}\n+#endif\n+\n+/** Handles host mode interrupts for the DWC_otg controller. Returns IRQ_NONE if\n+ * there was no interrupt to handle. Returns IRQ_HANDLED if there was a valid\n+ * interrupt.\n+ *\n+ * This function is called by the USB core when an interrupt occurs */\n+static irqreturn_t dwc_otg_hcd_irq(struct usb_hcd *hcd)\n+{\n+\tdwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);\n+\tint32_t retval = dwc_otg_hcd_handle_intr(dwc_otg_hcd);\n+\tif (retval != 0) {\n+\t\tS3C2410X_CLEAR_EINTPEND();\n+\t}\n+\treturn IRQ_RETVAL(retval);\n+}\n+\n+/** Creates Status Change bitmap for the root hub and root port. The bitmap is\n+ * returned in buf. Bit 0 is the status change indicator for the root hub. Bit 1\n+ * is the status change indicator for the single root port. Returns 1 if either\n+ * change indicator is 1, otherwise returns 0. */\n+int hub_status_data(struct usb_hcd *hcd, char *buf)\n+{\n+\tdwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);\n+\n+\tbuf[0] = 0;\n+\tbuf[0] |= (dwc_otg_hcd_is_status_changed(dwc_otg_hcd, 1)) << 1;\n+\n+\treturn (buf[0] != 0);\n+}\n+\n+/** Handles hub class-specific requests. */\n+int hub_control(struct usb_hcd *hcd,\n+\t\tu16 typeReq, u16 wValue, u16 wIndex, char *buf, u16 wLength)\n+{\n+\tint retval;\n+\n+\tretval = dwc_otg_hcd_hub_control(hcd_to_dwc_otg_hcd(hcd),\n+\t\t\t\t\t typeReq, wValue, wIndex, buf, wLength);\n+\n+\tswitch (retval) {\n+\tcase -DWC_E_INVALID:\n+\t\tretval = -EINVAL;\n+\t\tbreak;\n+\t}\n+\n+\treturn retval;\n+}\n+\n+#endif /* DWC_DEVICE_ONLY */\n--- /dev/null\n+++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd_queue.c\n@@ -0,0 +1,970 @@\n+/* ==========================================================================\n+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_queue.c $\n+ * $Revision: #44 $\n+ * $Date: 2011/10/26 $\n+ * $Change: 1873028 $\n+ *\n+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,\n+ * \"Software\") is an Unsupported proprietary work of Synopsys, Inc. unless\n+ * otherwise expressly agreed to in writing between Synopsys and you.\n+ *\n+ * The Software IS NOT an item of Licensed Software or Licensed Product under\n+ * any End User Software License Agreement or Agreement for Licensed Product\n+ * with Synopsys or any supplement thereto. You are permitted to use and\n+ * redistribute this Software in source and binary forms, with or without\n+ * modification, provided that redistributions of source code must retain this\n+ * notice. You may not view, use, disclose, copy or distribute this file or\n+ * any information contained herein except pursuant to this license grant from\n+ * Synopsys. If you do not agree with this notice, including the disclaimer\n+ * below, then you are not authorized to use the Software.\n+ *\n+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN \"AS IS\" BASIS\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,\n+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH\n+ * DAMAGE.\n+ * ========================================================================== */\n+#ifndef DWC_DEVICE_ONLY\n+\n+/**\n+ * @file\n+ *\n+ * This file contains the functions to manage Queue Heads and Queue\n+ * Transfer Descriptors.\n+ */\n+\n+#include \"dwc_otg_hcd.h\"\n+#include \"dwc_otg_regs.h\"\n+\n+extern bool microframe_schedule;\n+extern unsigned short int_ep_interval_min;\n+\n+/**\n+ * Free each QTD in the QH's QTD-list then free the QH.  QH should already be\n+ * removed from a list.  QTD list should already be empty if called from URB\n+ * Dequeue.\n+ *\n+ * @param hcd HCD instance.\n+ * @param qh The QH to free.\n+ */\n+void dwc_otg_hcd_qh_free(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)\n+{\n+\tdwc_otg_qtd_t *qtd, *qtd_tmp;\n+\tdwc_irqflags_t flags;\n+\tuint32_t buf_size = 0;\n+\tuint8_t *align_buf_virt = NULL;\n+\tdwc_dma_t align_buf_dma;\n+\tstruct device *dev = dwc_otg_hcd_to_dev(hcd);\n+\n+\t/* Free each QTD in the QTD list */\n+\tDWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);\n+\tDWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &qh->qtd_list, qtd_list_entry) {\n+\t\tDWC_CIRCLEQ_REMOVE(&qh->qtd_list, qtd, qtd_list_entry);\n+\t\tdwc_otg_hcd_qtd_free(qtd);\n+\t}\n+\n+\tif (hcd->core_if->dma_desc_enable) {\n+\t\tdwc_otg_hcd_qh_free_ddma(hcd, qh);\n+\t} else if (qh->dw_align_buf) {\n+\t\tif (qh->ep_type == UE_ISOCHRONOUS) {\n+\t\t\tbuf_size = 4096;\n+\t\t} else {\n+\t\t\tbuf_size = hcd->core_if->core_params->max_transfer_size;\n+\t\t}\n+\t\talign_buf_virt = qh->dw_align_buf;\n+\t\talign_buf_dma = qh->dw_align_buf_dma;\n+\t}\n+\n+\tDWC_FREE(qh);\n+\tDWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);\n+\tif (align_buf_virt)\n+\t\tDWC_DMA_FREE(dev, buf_size, align_buf_virt, align_buf_dma);\n+\treturn;\n+}\n+\n+#define BitStuffTime(bytecount)  ((8 * 7* bytecount) / 6)\n+#define HS_HOST_DELAY\t\t5\t/* nanoseconds */\n+#define FS_LS_HOST_DELAY\t1000\t/* nanoseconds */\n+#define HUB_LS_SETUP\t\t333\t/* nanoseconds */\n+#define NS_TO_US(ns)\t\t((ns + 500) / 1000)\n+\t\t\t\t/* convert & round nanoseconds to microseconds */\n+\n+static uint32_t calc_bus_time(int speed, int is_in, int is_isoc, int bytecount)\n+{\n+\tunsigned long retval;\n+\n+\tswitch (speed) {\n+\tcase USB_SPEED_HIGH:\n+\t\tif (is_isoc) {\n+\t\t\tretval =\n+\t\t\t    ((38 * 8 * 2083) +\n+\t\t\t     (2083 * (3 + BitStuffTime(bytecount)))) / 1000 +\n+\t\t\t    HS_HOST_DELAY;\n+\t\t} else {\n+\t\t\tretval =\n+\t\t\t    ((55 * 8 * 2083) +\n+\t\t\t     (2083 * (3 + BitStuffTime(bytecount)))) / 1000 +\n+\t\t\t    HS_HOST_DELAY;\n+\t\t}\n+\t\tbreak;\n+\tcase USB_SPEED_FULL:\n+\t\tif (is_isoc) {\n+\t\t\tretval =\n+\t\t\t    (8354 * (31 + 10 * BitStuffTime(bytecount))) / 1000;\n+\t\t\tif (is_in) {\n+\t\t\t\tretval = 7268 + FS_LS_HOST_DELAY + retval;\n+\t\t\t} else {\n+\t\t\t\tretval = 6265 + FS_LS_HOST_DELAY + retval;\n+\t\t\t}\n+\t\t} else {\n+\t\t\tretval =\n+\t\t\t    (8354 * (31 + 10 * BitStuffTime(bytecount))) / 1000;\n+\t\t\tretval = 9107 + FS_LS_HOST_DELAY + retval;\n+\t\t}\n+\t\tbreak;\n+\tcase USB_SPEED_LOW:\n+\t\tif (is_in) {\n+\t\t\tretval =\n+\t\t\t    (67667 * (31 + 10 * BitStuffTime(bytecount))) /\n+\t\t\t    1000;\n+\t\t\tretval =\n+\t\t\t    64060 + (2 * HUB_LS_SETUP) + FS_LS_HOST_DELAY +\n+\t\t\t    retval;\n+\t\t} else {\n+\t\t\tretval =\n+\t\t\t    (66700 * (31 + 10 * BitStuffTime(bytecount))) /\n+\t\t\t    1000;\n+\t\t\tretval =\n+\t\t\t    64107 + (2 * HUB_LS_SETUP) + FS_LS_HOST_DELAY +\n+\t\t\t    retval;\n+\t\t}\n+\t\tbreak;\n+\tdefault:\n+\t\tDWC_WARN(\"Unknown device speed\\n\");\n+\t\tretval = -1;\n+\t}\n+\n+\treturn NS_TO_US(retval);\n+}\n+\n+/**\n+ * Initializes a QH structure.\n+ *\n+ * @param hcd The HCD state structure for the DWC OTG controller.\n+ * @param qh  The QH to init.\n+ * @param urb Holds the information about the device/endpoint that we need\n+ * \t      to initialize the QH.\n+ */\n+#define SCHEDULE_SLOP 10\n+void qh_init(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh, dwc_otg_hcd_urb_t * urb)\n+{\n+\tchar *speed, *type;\n+\tint dev_speed;\n+\tuint32_t hub_addr, hub_port;\n+\thprt0_data_t hprt;\n+\n+\tdwc_memset(qh, 0, sizeof(dwc_otg_qh_t));\n+\thprt.d32 = DWC_READ_REG32(hcd->core_if->host_if->hprt0);\n+\n+\t/* Initialize QH */\n+\tqh->ep_type = dwc_otg_hcd_get_pipe_type(&urb->pipe_info);\n+\tqh->ep_is_in = dwc_otg_hcd_is_pipe_in(&urb->pipe_info) ? 1 : 0;\n+\n+\tqh->data_toggle = DWC_OTG_HC_PID_DATA0;\n+\tqh->maxp = dwc_otg_hcd_get_mps(&urb->pipe_info);\n+\tDWC_CIRCLEQ_INIT(&qh->qtd_list);\n+\tDWC_LIST_INIT(&qh->qh_list_entry);\n+\tqh->channel = NULL;\n+\n+\t/* FS/LS Enpoint on HS Hub\n+\t * NOT virtual root hub */\n+\tdev_speed = hcd->fops->speed(hcd, urb->priv);\n+\n+\thcd->fops->hub_info(hcd, urb->priv, &hub_addr, &hub_port);\n+\tqh->do_split = 0;\n+\tif (microframe_schedule)\n+\t\tqh->speed = dev_speed;\n+\n+\tqh->nak_frame = 0xffff;\n+\n+\tif (hprt.b.prtspd == DWC_HPRT0_PRTSPD_HIGH_SPEED &&\n+\t\t\tdev_speed != USB_SPEED_HIGH) {\n+\t\tDWC_DEBUGPL(DBG_HCD,\n+\t\t\t    \"QH init: EP %d: TT found at hub addr %d, for port %d\\n\",\n+\t\t\t    dwc_otg_hcd_get_ep_num(&urb->pipe_info), hub_addr,\n+\t\t\t    hub_port);\n+\t\tqh->do_split = 1;\n+\t\tqh->skip_count = 0;\n+\t}\n+\n+\tif (qh->ep_type == UE_INTERRUPT || qh->ep_type == UE_ISOCHRONOUS) {\n+\t\t/* Compute scheduling parameters once and save them. */\n+\n+\t\t/** @todo Account for split transfers in the bus time. */\n+\t\tint bytecount =\n+\t\t    dwc_hb_mult(qh->maxp) * dwc_max_packet(qh->maxp);\n+\n+\t\tqh->usecs =\n+\t\t    calc_bus_time((qh->do_split ? USB_SPEED_HIGH : dev_speed),\n+\t\t\t\t  qh->ep_is_in, (qh->ep_type == UE_ISOCHRONOUS),\n+\t\t\t\t  bytecount);\n+\t\t/* Start in a slightly future (micro)frame. */\n+\t\tqh->sched_frame = dwc_frame_num_inc(hcd->frame_number,\n+\t\t\t\t\t\t    SCHEDULE_SLOP);\n+\t\tqh->interval = urb->interval;\n+\n+\t\tif (hprt.b.prtspd == DWC_HPRT0_PRTSPD_HIGH_SPEED) {\n+\t\t\tif (dev_speed == USB_SPEED_LOW ||\n+\t\t\t\t\tdev_speed == USB_SPEED_FULL) {\n+\t\t\t\tqh->interval *= 8;\n+\t\t\t\tqh->sched_frame |= 0x7;\n+\t\t\t\tqh->start_split_frame = qh->sched_frame;\n+\t\t\t} else if (int_ep_interval_min >= 2 &&\n+\t\t\t\t\tqh->interval < int_ep_interval_min &&\n+\t\t\t\t\tqh->ep_type == UE_INTERRUPT) {\n+\t\t\t\tqh->interval = int_ep_interval_min;\n+\t\t\t}\n+\t\t}\n+\t}\n+\n+\tDWC_DEBUGPL(DBG_HCD, \"DWC OTG HCD QH Initialized\\n\");\n+\tDWC_DEBUGPL(DBG_HCDV, \"DWC OTG HCD QH  - qh = %p\\n\", qh);\n+\tDWC_DEBUGPL(DBG_HCDV, \"DWC OTG HCD QH  - Device Address = %d\\n\",\n+\t\t    dwc_otg_hcd_get_dev_addr(&urb->pipe_info));\n+\tDWC_DEBUGPL(DBG_HCDV, \"DWC OTG HCD QH  - Endpoint %d, %s\\n\",\n+\t\t    dwc_otg_hcd_get_ep_num(&urb->pipe_info),\n+\t\t    dwc_otg_hcd_is_pipe_in(&urb->pipe_info) ? \"IN\" : \"OUT\");\n+\tswitch (dev_speed) {\n+\tcase USB_SPEED_LOW:\n+\t\tqh->dev_speed = DWC_OTG_EP_SPEED_LOW;\n+\t\tspeed = \"low\";\n+\t\tbreak;\n+\tcase USB_SPEED_FULL:\n+\t\tqh->dev_speed = DWC_OTG_EP_SPEED_FULL;\n+\t\tspeed = \"full\";\n+\t\tbreak;\n+\tcase USB_SPEED_HIGH:\n+\t\tqh->dev_speed = DWC_OTG_EP_SPEED_HIGH;\n+\t\tspeed = \"high\";\n+\t\tbreak;\n+\tdefault:\n+\t\tspeed = \"?\";\n+\t\tbreak;\n+\t}\n+\tDWC_DEBUGPL(DBG_HCDV, \"DWC OTG HCD QH  - Speed = %s\\n\", speed);\n+\n+\tswitch (qh->ep_type) {\n+\tcase UE_ISOCHRONOUS:\n+\t\ttype = \"isochronous\";\n+\t\tbreak;\n+\tcase UE_INTERRUPT:\n+\t\ttype = \"interrupt\";\n+\t\tbreak;\n+\tcase UE_CONTROL:\n+\t\ttype = \"control\";\n+\t\tbreak;\n+\tcase UE_BULK:\n+\t\ttype = \"bulk\";\n+\t\tbreak;\n+\tdefault:\n+\t\ttype = \"?\";\n+\t\tbreak;\n+\t}\n+\n+\tDWC_DEBUGPL(DBG_HCDV, \"DWC OTG HCD QH  - Type = %s\\n\", type);\n+\n+#ifdef DEBUG\n+\tif (qh->ep_type == UE_INTERRUPT) {\n+\t\tDWC_DEBUGPL(DBG_HCDV, \"DWC OTG HCD QH - usecs = %d\\n\",\n+\t\t\t    qh->usecs);\n+\t\tDWC_DEBUGPL(DBG_HCDV, \"DWC OTG HCD QH - interval = %d\\n\",\n+\t\t\t    qh->interval);\n+\t}\n+#endif\n+\n+}\n+\n+/**\n+ * This function allocates and initializes a QH.\n+ *\n+ * @param hcd The HCD state structure for the DWC OTG controller.\n+ * @param urb Holds the information about the device/endpoint that we need\n+ * \t      to initialize the QH.\n+ * @param atomic_alloc Flag to do atomic allocation if needed\n+ *\n+ * @return Returns pointer to the newly allocated QH, or NULL on error. */\n+dwc_otg_qh_t *dwc_otg_hcd_qh_create(dwc_otg_hcd_t * hcd,\n+\t\t\t\t    dwc_otg_hcd_urb_t * urb, int atomic_alloc)\n+{\n+\tdwc_otg_qh_t *qh;\n+\n+\t/* Allocate memory */\n+\t/** @todo add memflags argument */\n+\tqh = dwc_otg_hcd_qh_alloc(atomic_alloc);\n+\tif (qh == NULL) {\n+\t\tDWC_ERROR(\"qh allocation failed\");\n+\t\treturn NULL;\n+\t}\n+\n+\tqh_init(hcd, qh, urb);\n+\n+\tif (hcd->core_if->dma_desc_enable\n+\t    && (dwc_otg_hcd_qh_init_ddma(hcd, qh) < 0)) {\n+\t\tdwc_otg_hcd_qh_free(hcd, qh);\n+\t\treturn NULL;\n+\t}\n+\n+\treturn qh;\n+}\n+\n+/* microframe_schedule=0 start */\n+\n+/**\n+ * Checks that a channel is available for a periodic transfer.\n+ *\n+ * @return 0 if successful, negative error code otherise.\n+ */\n+static int periodic_channel_available(dwc_otg_hcd_t * hcd)\n+{\n+\t/*\n+\t * Currently assuming that there is a dedicated host channnel for each\n+\t * periodic transaction plus at least one host channel for\n+\t * non-periodic transactions.\n+\t */\n+\tint status;\n+\tint num_channels;\n+\n+\tnum_channels = hcd->core_if->core_params->host_channels;\n+\tif ((hcd->periodic_channels + hcd->non_periodic_channels < num_channels)\n+\t    && (hcd->periodic_channels < num_channels - 1)) {\n+\t\tstatus = 0;\n+\t} else {\n+\t\tDWC_INFO(\"%s: Total channels: %d, Periodic: %d, Non-periodic: %d\\n\",\n+\t\t\t__func__, num_channels, hcd->periodic_channels, hcd->non_periodic_channels);\t//NOTICE\n+\t\tstatus = -DWC_E_NO_SPACE;\n+\t}\n+\n+\treturn status;\n+}\n+\n+/**\n+ * Checks that there is sufficient bandwidth for the specified QH in the\n+ * periodic schedule. For simplicity, this calculation assumes that all the\n+ * transfers in the periodic schedule may occur in the same (micro)frame.\n+ *\n+ * @param hcd The HCD state structure for the DWC OTG controller.\n+ * @param qh QH containing periodic bandwidth required.\n+ *\n+ * @return 0 if successful, negative error code otherwise.\n+ */\n+static int check_periodic_bandwidth(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)\n+{\n+\tint status;\n+\tint16_t max_claimed_usecs;\n+\n+\tstatus = 0;\n+\n+\tif ((qh->dev_speed == DWC_OTG_EP_SPEED_HIGH) || qh->do_split) {\n+\t\t/*\n+\t\t * High speed mode.\n+\t\t * Max periodic usecs is 80% x 125 usec = 100 usec.\n+\t\t */\n+\n+\t\tmax_claimed_usecs = 100 - qh->usecs;\n+\t} else {\n+\t\t/*\n+\t\t * Full speed mode.\n+\t\t * Max periodic usecs is 90% x 1000 usec = 900 usec.\n+\t\t */\n+\t\tmax_claimed_usecs = 900 - qh->usecs;\n+\t}\n+\n+\tif (hcd->periodic_usecs > max_claimed_usecs) {\n+\t\tDWC_INFO(\"%s: already claimed usecs %d, required usecs %d\\n\", __func__, hcd->periodic_usecs, qh->usecs);\t//NOTICE\n+\t\tstatus = -DWC_E_NO_SPACE;\n+\t}\n+\n+\treturn status;\n+}\n+\n+/* microframe_schedule=0 end */\n+\n+/**\n+ * Microframe scheduler\n+ * track the total use in hcd->frame_usecs\n+ * keep each qh use in qh->frame_usecs\n+ * when surrendering the qh then donate the time back\n+ */\n+const unsigned short max_uframe_usecs[]={ 100, 100, 100, 100, 100, 100, 30, 0 };\n+\n+/*\n+ * called from dwc_otg_hcd.c:dwc_otg_hcd_init\n+ */\n+void init_hcd_usecs(dwc_otg_hcd_t *_hcd)\n+{\n+\tint i;\n+\tif (_hcd->flags.b.port_speed == DWC_HPRT0_PRTSPD_FULL_SPEED) {\n+\t\t_hcd->frame_usecs[0] = 900;\n+\t\tfor (i = 1; i < 8; i++)\n+\t\t\t_hcd->frame_usecs[i] = 0;\n+\t} else {\n+\t\tfor (i = 0; i < 8; i++)\n+\t\t\t_hcd->frame_usecs[i] = max_uframe_usecs[i];\n+\t}\n+}\n+\n+static int find_single_uframe(dwc_otg_hcd_t * _hcd, dwc_otg_qh_t * _qh)\n+{\n+\tint i;\n+\tunsigned short utime;\n+\tint t_left;\n+\tint ret;\n+\tint done;\n+\n+\tret = -1;\n+\tutime = _qh->usecs;\n+\tt_left = utime;\n+\ti = 0;\n+\tdone = 0;\n+\twhile (done == 0) {\n+\t\t/* At the start _hcd->frame_usecs[i] = max_uframe_usecs[i]; */\n+\t\tif (utime <= _hcd->frame_usecs[i]) {\n+\t\t\t_hcd->frame_usecs[i] -= utime;\n+\t\t\t_qh->frame_usecs[i] += utime;\n+\t\t\tt_left -= utime;\n+\t\t\tret = i;\n+\t\t\tdone = 1;\n+\t\t\treturn ret;\n+\t\t} else {\n+\t\t\ti++;\n+\t\t\tif (i == 8) {\n+\t\t\t\tdone = 1;\n+\t\t\t\tret = -1;\n+\t\t\t}\n+\t\t}\n+\t}\n+\treturn ret;\n+ }\n+\n+/*\n+ * use this for FS apps that can span multiple uframes\n+  */\n+static int find_multi_uframe(dwc_otg_hcd_t * _hcd, dwc_otg_qh_t * _qh)\n+{\n+\tint i;\n+\tint j;\n+\tunsigned short utime;\n+\tint t_left;\n+\tint ret;\n+\tint done;\n+\tunsigned short xtime;\n+\n+\tret = -1;\n+\tutime = _qh->usecs;\n+\tt_left = utime;\n+\ti = 0;\n+\tdone = 0;\n+loop:\n+\twhile (done == 0) {\n+\t\tif(_hcd->frame_usecs[i] <= 0) {\n+\t\t\ti++;\n+\t\t\tif (i == 8) {\n+\t\t\t\tdone = 1;\n+\t\t\t\tret = -1;\n+\t\t\t}\n+\t\t\tgoto loop;\n+\t\t}\n+\n+\t\t/*\n+\t\t * we need n consecutive slots\n+\t\t * so use j as a start slot j plus j+1 must be enough time (for now)\n+\t\t */\n+\t\txtime= _hcd->frame_usecs[i];\n+\t\tfor (j = i+1 ; j < 8 ; j++ ) {\n+                       /*\n+                        * if we add this frame remaining time to xtime we may\n+                        * be OK, if not we need to test j for a complete frame\n+                        */\n+                       if ((xtime+_hcd->frame_usecs[j]) < utime) {\n+                               if (_hcd->frame_usecs[j] < max_uframe_usecs[j]) {\n+                                       j = 8;\n+                                       ret = -1;\n+                                       continue;\n+                               }\n+                       }\n+                       if (xtime >= utime) {\n+                               ret = i;\n+                               j = 8;  /* stop loop with a good value ret */\n+                               continue;\n+                       }\n+                       /* add the frame time to x time */\n+                       xtime += _hcd->frame_usecs[j];\n+\t\t       /* we must have a fully available next frame or break */\n+\t\t       if ((xtime < utime)\n+\t\t\t\t       && (_hcd->frame_usecs[j] == max_uframe_usecs[j])) {\n+\t\t\t       ret = -1;\n+\t\t\t       j = 8;  /* stop loop with a bad value ret */\n+\t\t\t       continue;\n+\t\t       }\n+\t\t}\n+\t\tif (ret >= 0) {\n+\t\t\tt_left = utime;\n+\t\t\tfor (j = i; (t_left>0) && (j < 8); j++ ) {\n+\t\t\t\tt_left -= _hcd->frame_usecs[j];\n+\t\t\t\tif ( t_left <= 0 ) {\n+\t\t\t\t\t_qh->frame_usecs[j] += _hcd->frame_usecs[j] + t_left;\n+\t\t\t\t\t_hcd->frame_usecs[j]= -t_left;\n+\t\t\t\t\tret = i;\n+\t\t\t\t\tdone = 1;\n+\t\t\t\t} else {\n+\t\t\t\t\t_qh->frame_usecs[j] += _hcd->frame_usecs[j];\n+\t\t\t\t\t_hcd->frame_usecs[j] = 0;\n+\t\t\t\t}\n+\t\t\t}\n+\t\t} else {\n+\t\t\ti++;\n+\t\t\tif (i == 8) {\n+\t\t\t\tdone = 1;\n+\t\t\t\tret = -1;\n+\t\t\t}\n+\t\t}\n+\t}\n+\treturn ret;\n+}\n+\n+static int find_uframe(dwc_otg_hcd_t * _hcd, dwc_otg_qh_t * _qh)\n+{\n+\tint ret;\n+\tret = -1;\n+\n+\tif (_qh->speed == USB_SPEED_HIGH ||\n+\t\t_hcd->flags.b.port_speed == DWC_HPRT0_PRTSPD_FULL_SPEED) {\n+\t\t/* if this is a hs transaction we need a full frame - or account for FS usecs */\n+\t\tret = find_single_uframe(_hcd, _qh);\n+\t} else {\n+\t\t/* if this is a fs transaction we may need a sequence of frames */\n+\t\tret = find_multi_uframe(_hcd, _qh);\n+\t}\n+\treturn ret;\n+}\n+\n+/**\n+ * Checks that the max transfer size allowed in a host channel is large enough\n+ * to handle the maximum data transfer in a single (micro)frame for a periodic\n+ * transfer.\n+ *\n+ * @param hcd The HCD state structure for the DWC OTG controller.\n+ * @param qh QH for a periodic endpoint.\n+ *\n+ * @return 0 if successful, negative error code otherwise.\n+ */\n+static int check_max_xfer_size(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)\n+{\n+\tint status;\n+\tuint32_t max_xfer_size;\n+\tuint32_t max_channel_xfer_size;\n+\n+\tstatus = 0;\n+\n+\tmax_xfer_size = dwc_max_packet(qh->maxp) * dwc_hb_mult(qh->maxp);\n+\tmax_channel_xfer_size = hcd->core_if->core_params->max_transfer_size;\n+\n+\tif (max_xfer_size > max_channel_xfer_size) {\n+\t\tDWC_INFO(\"%s: Periodic xfer length %d > \" \"max xfer length for channel %d\\n\",\n+\t\t\t\t__func__, max_xfer_size, max_channel_xfer_size);\t//NOTICE\n+\t\tstatus = -DWC_E_NO_SPACE;\n+\t}\n+\n+\treturn status;\n+}\n+\n+\n+\n+/**\n+ * Schedules an interrupt or isochronous transfer in the periodic schedule.\n+ *\n+ * @param hcd The HCD state structure for the DWC OTG controller.\n+ * @param qh QH for the periodic transfer. The QH should already contain the\n+ * scheduling information.\n+ *\n+ * @return 0 if successful, negative error code otherwise.\n+ */\n+static int schedule_periodic(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)\n+{\n+\tint status = 0;\n+\n+\tif (microframe_schedule) {\n+\t\tint frame;\n+\t\tstatus = find_uframe(hcd, qh);\n+\t\tframe = -1;\n+\t\tif (status == 0) {\n+\t\t\tframe = 7;\n+\t\t} else {\n+\t\t\tif (status > 0 )\n+\t\t\t\tframe = status-1;\n+\t\t}\n+\n+\t\t/* Set the new frame up */\n+\t\tif (frame > -1) {\n+\t\t\tqh->sched_frame &= ~0x7;\n+\t\t\tqh->sched_frame |= (frame & 7);\n+\t\t}\n+\n+\t\tif (status != -1)\n+\t\t\tstatus = 0;\n+\t} else {\n+\t\tstatus = periodic_channel_available(hcd);\n+\t\tif (status) {\n+\t\t\tDWC_INFO(\"%s: No host channel available for periodic \" \"transfer.\\n\", __func__);\t//NOTICE\n+\t\t\treturn status;\n+\t\t}\n+\n+\t\tstatus = check_periodic_bandwidth(hcd, qh);\n+\t}\n+\tif (status) {\n+\t\tDWC_INFO(\"%s: Insufficient periodic bandwidth for \"\n+\t\t\t    \"periodic transfer.\\n\", __func__);\n+\t\treturn -DWC_E_NO_SPACE;\n+\t}\n+\tstatus = check_max_xfer_size(hcd, qh);\n+\tif (status) {\n+\t\tDWC_INFO(\"%s: Channel max transfer size too small \"\n+\t\t\t    \"for periodic transfer.\\n\", __func__);\n+\t\treturn status;\n+\t}\n+\n+\tif (hcd->core_if->dma_desc_enable) {\n+\t\t/* Don't rely on SOF and start in ready schedule */\n+\t\tDWC_LIST_INSERT_TAIL(&hcd->periodic_sched_ready, &qh->qh_list_entry);\n+\t}\n+\telse {\n+\t\tif(fiq_enable && (DWC_LIST_EMPTY(&hcd->periodic_sched_inactive) || dwc_frame_num_le(qh->sched_frame, hcd->fiq_state->next_sched_frame)))\n+\t\t{\n+\t\t\thcd->fiq_state->next_sched_frame = qh->sched_frame;\n+\n+\t\t}\n+\t\t/* Always start in the inactive schedule. */\n+\t\tDWC_LIST_INSERT_TAIL(&hcd->periodic_sched_inactive, &qh->qh_list_entry);\n+\t}\n+\n+\tif (!microframe_schedule) {\n+\t\t/* Reserve the periodic channel. */\n+\t\thcd->periodic_channels++;\n+\t}\n+\n+\t/* Update claimed usecs per (micro)frame. */\n+\thcd->periodic_usecs += qh->usecs;\n+\n+\treturn status;\n+}\n+\n+\n+/**\n+ * This function adds a QH to either the non periodic or periodic schedule if\n+ * it is not already in the schedule. If the QH is already in the schedule, no\n+ * action is taken.\n+ *\n+ * @return 0 if successful, negative error code otherwise.\n+ */\n+int dwc_otg_hcd_qh_add(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)\n+{\n+\tint status = 0;\n+\tgintmsk_data_t intr_mask = {.d32 = 0 };\n+\n+\tif (!DWC_LIST_EMPTY(&qh->qh_list_entry)) {\n+\t\t/* QH already in a schedule. */\n+\t\treturn status;\n+\t}\n+\n+\t/* Add the new QH to the appropriate schedule */\n+\tif (dwc_qh_is_non_per(qh)) {\n+\t\t/* Always start in the inactive schedule. */\n+\t\tDWC_LIST_INSERT_TAIL(&hcd->non_periodic_sched_inactive,\n+\t\t\t\t     &qh->qh_list_entry);\n+\t\t//hcd->fiq_state->kick_np_queues = 1;\n+\t} else {\n+\t\tstatus = schedule_periodic(hcd, qh);\n+\t\tif ( !hcd->periodic_qh_count ) {\n+\t\t\tintr_mask.b.sofintr = 1;\n+\t\t\tif (fiq_enable) {\n+\t\t\t\tlocal_fiq_disable();\n+\t\t\t\tfiq_fsm_spin_lock(&hcd->fiq_state->lock);\n+\t\t\t\tDWC_MODIFY_REG32(&hcd->core_if->core_global_regs->gintmsk, intr_mask.d32, intr_mask.d32);\n+\t\t\t\tfiq_fsm_spin_unlock(&hcd->fiq_state->lock);\n+\t\t\t\tlocal_fiq_enable();\n+\t\t\t} else {\n+\t\t\t\tDWC_MODIFY_REG32(&hcd->core_if->core_global_regs->gintmsk, intr_mask.d32, intr_mask.d32);\n+\t\t\t}\n+\t\t}\n+\t\thcd->periodic_qh_count++;\n+\t}\n+\n+\treturn status;\n+}\n+\n+/**\n+ * Removes an interrupt or isochronous transfer from the periodic schedule.\n+ *\n+ * @param hcd The HCD state structure for the DWC OTG controller.\n+ * @param qh QH for the periodic transfer.\n+ */\n+static void deschedule_periodic(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)\n+{\n+\tint i;\n+\tDWC_LIST_REMOVE_INIT(&qh->qh_list_entry);\n+\n+\t/* Update claimed usecs per (micro)frame. */\n+\thcd->periodic_usecs -= qh->usecs;\n+\n+\tif (!microframe_schedule) {\n+\t\t/* Release the periodic channel reservation. */\n+\t\thcd->periodic_channels--;\n+\t} else {\n+\t\tfor (i = 0; i < 8; i++) {\n+\t\t\thcd->frame_usecs[i] += qh->frame_usecs[i];\n+\t\t\tqh->frame_usecs[i] = 0;\n+\t\t}\n+\t}\n+}\n+\n+/**\n+ * Removes a QH from either the non-periodic or periodic schedule.  Memory is\n+ * not freed.\n+ *\n+ * @param hcd The HCD state structure.\n+ * @param qh QH to remove from schedule. */\n+void dwc_otg_hcd_qh_remove(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)\n+{\n+\tgintmsk_data_t intr_mask = {.d32 = 0 };\n+\n+\tif (DWC_LIST_EMPTY(&qh->qh_list_entry)) {\n+\t\t/* QH is not in a schedule. */\n+\t\treturn;\n+\t}\n+\n+\tif (dwc_qh_is_non_per(qh)) {\n+\t\tif (hcd->non_periodic_qh_ptr == &qh->qh_list_entry) {\n+\t\t\thcd->non_periodic_qh_ptr =\n+\t\t\t    hcd->non_periodic_qh_ptr->next;\n+\t\t}\n+\t\tDWC_LIST_REMOVE_INIT(&qh->qh_list_entry);\n+\t\t//if (!DWC_LIST_EMPTY(&hcd->non_periodic_sched_inactive))\n+\t\t//\thcd->fiq_state->kick_np_queues = 1;\n+\t} else {\n+\t\tdeschedule_periodic(hcd, qh);\n+\t\thcd->periodic_qh_count--;\n+\t\tif( !hcd->periodic_qh_count && !fiq_fsm_enable ) {\n+\t\t\tintr_mask.b.sofintr = 1;\n+\t\t\tif (fiq_enable) {\n+\t\t\t\tlocal_fiq_disable();\n+\t\t\t\tfiq_fsm_spin_lock(&hcd->fiq_state->lock);\n+\t\t\t\tDWC_MODIFY_REG32(&hcd->core_if->core_global_regs->gintmsk, intr_mask.d32, 0);\n+\t\t\t\tfiq_fsm_spin_unlock(&hcd->fiq_state->lock);\n+\t\t\t\tlocal_fiq_enable();\n+\t\t\t} else {\n+\t\t\t\tDWC_MODIFY_REG32(&hcd->core_if->core_global_regs->gintmsk, intr_mask.d32, 0);\n+\t\t\t}\n+\t\t}\n+\t}\n+}\n+\n+/**\n+ * Deactivates a QH. For non-periodic QHs, removes the QH from the active\n+ * non-periodic schedule. The QH is added to the inactive non-periodic\n+ * schedule if any QTDs are still attached to the QH.\n+ *\n+ * For periodic QHs, the QH is removed from the periodic queued schedule. If\n+ * there are any QTDs still attached to the QH, the QH is added to either the\n+ * periodic inactive schedule or the periodic ready schedule and its next\n+ * scheduled frame is calculated. The QH is placed in the ready schedule if\n+ * the scheduled frame has been reached already. Otherwise it's placed in the\n+ * inactive schedule. If there are no QTDs attached to the QH, the QH is\n+ * completely removed from the periodic schedule.\n+ */\n+void dwc_otg_hcd_qh_deactivate(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh,\n+\t\t\t       int sched_next_periodic_split)\n+{\n+\tif (dwc_qh_is_non_per(qh)) {\n+\t\tdwc_otg_hcd_qh_remove(hcd, qh);\n+\t\tif (!DWC_CIRCLEQ_EMPTY(&qh->qtd_list)) {\n+\t\t\t/* Add back to inactive non-periodic schedule. */\n+\t\t\tdwc_otg_hcd_qh_add(hcd, qh);\n+\t\t\t//hcd->fiq_state->kick_np_queues = 1;\n+\t\t} else {\n+\t\t\tif(nak_holdoff && qh->do_split) {\n+\t\t\t\tqh->nak_frame = 0xFFFF;\n+\t\t\t}\n+\t\t}\n+\t} else {\n+\t\tuint16_t frame_number = dwc_otg_hcd_get_frame_number(hcd);\n+\n+\t\tif (qh->do_split) {\n+\t\t\t/* Schedule the next continuing periodic split transfer */\n+\t\t\tif (sched_next_periodic_split) {\n+\n+\t\t\t\tqh->sched_frame = frame_number;\n+\n+\t\t\t\tif (dwc_frame_num_le(frame_number,\n+\t\t\t\t\t\t     dwc_frame_num_inc\n+\t\t\t\t\t\t     (qh->start_split_frame,\n+\t\t\t\t\t\t      1))) {\n+\t\t\t\t\t/*\n+\t\t\t\t\t * Allow one frame to elapse after start\n+\t\t\t\t\t * split microframe before scheduling\n+\t\t\t\t\t * complete split, but DONT if we are\n+\t\t\t\t\t * doing the next start split in the\n+\t\t\t\t\t * same frame for an ISOC out.\n+\t\t\t\t\t */\n+\t\t\t\t\tif ((qh->ep_type != UE_ISOCHRONOUS) ||\n+\t\t\t\t\t    (qh->ep_is_in != 0)) {\n+\t\t\t\t\t\tqh->sched_frame =\n+\t\t\t\t\t\t    dwc_frame_num_inc(qh->sched_frame, 1);\n+\t\t\t\t\t}\n+\t\t\t\t}\n+\t\t\t} else {\n+\t\t\t\tqh->sched_frame =\n+\t\t\t\t    dwc_frame_num_inc(qh->start_split_frame,\n+\t\t\t\t\t\t      qh->interval);\n+\t\t\t\tif (dwc_frame_num_le\n+\t\t\t\t    (qh->sched_frame, frame_number)) {\n+\t\t\t\t\tqh->sched_frame = frame_number;\n+\t\t\t\t}\n+\t\t\t\tqh->sched_frame |= 0x7;\n+\t\t\t\tqh->start_split_frame = qh->sched_frame;\n+\t\t\t}\n+\t\t} else {\n+\t\t\tqh->sched_frame =\n+\t\t\t    dwc_frame_num_inc(qh->sched_frame, qh->interval);\n+\t\t\tif (dwc_frame_num_le(qh->sched_frame, frame_number)) {\n+\t\t\t\tqh->sched_frame = frame_number;\n+\t\t\t}\n+\t\t}\n+\n+\t\tif (DWC_CIRCLEQ_EMPTY(&qh->qtd_list)) {\n+\t\t\tdwc_otg_hcd_qh_remove(hcd, qh);\n+\t\t} else {\n+\t\t\t/*\n+\t\t\t * Remove from periodic_sched_queued and move to\n+\t\t\t * appropriate queue.\n+\t\t\t */\n+\t\t\tif ((microframe_schedule && dwc_frame_num_le(qh->sched_frame, frame_number)) ||\n+\t\t\t(!microframe_schedule && qh->sched_frame == frame_number)) {\n+\t\t\t\tDWC_LIST_MOVE_HEAD(&hcd->periodic_sched_ready,\n+\t\t\t\t\t\t   &qh->qh_list_entry);\n+\t\t\t} else {\n+\t\t\t\tif(fiq_enable && !dwc_frame_num_le(hcd->fiq_state->next_sched_frame, qh->sched_frame))\n+\t\t\t\t{\n+\t\t\t\t\thcd->fiq_state->next_sched_frame = qh->sched_frame;\n+\t\t\t\t}\n+\n+\t\t\t\tDWC_LIST_MOVE_HEAD\n+\t\t\t\t    (&hcd->periodic_sched_inactive,\n+\t\t\t\t     &qh->qh_list_entry);\n+\t\t\t}\n+\t\t}\n+\t}\n+}\n+\n+/**\n+ * This function allocates and initializes a QTD.\n+ *\n+ * @param urb The URB to create a QTD from.  Each URB-QTD pair will end up\n+ * \t      pointing to each other so each pair should have a unique correlation.\n+ * @param atomic_alloc Flag to do atomic alloc if needed\n+ *\n+ * @return Returns pointer to the newly allocated QTD, or NULL on error. */\n+dwc_otg_qtd_t *dwc_otg_hcd_qtd_create(dwc_otg_hcd_urb_t * urb, int atomic_alloc)\n+{\n+\tdwc_otg_qtd_t *qtd;\n+\n+\tqtd = dwc_otg_hcd_qtd_alloc(atomic_alloc);\n+\tif (qtd == NULL) {\n+\t\treturn NULL;\n+\t}\n+\n+\tdwc_otg_hcd_qtd_init(qtd, urb);\n+\treturn qtd;\n+}\n+\n+/**\n+ * Initializes a QTD structure.\n+ *\n+ * @param qtd The QTD to initialize.\n+ * @param urb The URB to use for initialization.  */\n+void dwc_otg_hcd_qtd_init(dwc_otg_qtd_t * qtd, dwc_otg_hcd_urb_t * urb)\n+{\n+\tdwc_memset(qtd, 0, sizeof(dwc_otg_qtd_t));\n+\tqtd->urb = urb;\n+\tif (dwc_otg_hcd_get_pipe_type(&urb->pipe_info) == UE_CONTROL) {\n+\t\t/*\n+\t\t * The only time the QTD data toggle is used is on the data\n+\t\t * phase of control transfers. This phase always starts with\n+\t\t * DATA1.\n+\t\t */\n+\t\tqtd->data_toggle = DWC_OTG_HC_PID_DATA1;\n+\t\tqtd->control_phase = DWC_OTG_CONTROL_SETUP;\n+\t}\n+\n+\t/* start split */\n+\tqtd->complete_split = 0;\n+\tqtd->isoc_split_pos = DWC_HCSPLIT_XACTPOS_ALL;\n+\tqtd->isoc_split_offset = 0;\n+\tqtd->in_process = 0;\n+\n+\t/* Store the qtd ptr in the urb to reference what QTD. */\n+\turb->qtd = qtd;\n+\treturn;\n+}\n+\n+/**\n+ * This function adds a QTD to the QTD-list of a QH.  It will find the correct\n+ * QH to place the QTD into.  If it does not find a QH, then it will create a\n+ * new QH. If the QH to which the QTD is added is not currently scheduled, it\n+ * is placed into the proper schedule based on its EP type.\n+ * HCD lock must be held and interrupts must be disabled on entry\n+ *\n+ * @param[in] qtd The QTD to add\n+ * @param[in] hcd The DWC HCD structure\n+ * @param[out] qh out parameter to return queue head\n+ * @param atomic_alloc Flag to do atomic alloc if needed\n+ *\n+ * @return 0 if successful, negative error code otherwise.\n+ */\n+int dwc_otg_hcd_qtd_add(dwc_otg_qtd_t * qtd,\n+\t\t\tdwc_otg_hcd_t * hcd, dwc_otg_qh_t ** qh, int atomic_alloc)\n+{\n+\tint retval = 0;\n+\tdwc_otg_hcd_urb_t *urb = qtd->urb;\n+\n+\t/*\n+\t * Get the QH which holds the QTD-list to insert to. Create QH if it\n+\t * doesn't exist.\n+\t */\n+\tif (*qh == NULL) {\n+\t\t*qh = dwc_otg_hcd_qh_create(hcd, urb, atomic_alloc);\n+\t\tif (*qh == NULL) {\n+\t\t\tretval = -DWC_E_NO_MEMORY;\n+\t\t\tgoto done;\n+\t\t} else {\n+\t\t\tif (fiq_enable)\n+\t\t\t\thcd->fiq_state->kick_np_queues = 1;\n+\t\t}\n+\t}\n+\tretval = dwc_otg_hcd_qh_add(hcd, *qh);\n+\tif (retval == 0) {\n+\t\tDWC_CIRCLEQ_INSERT_TAIL(&((*qh)->qtd_list), qtd,\n+\t\t\t\t\tqtd_list_entry);\n+\t\tqtd->qh = *qh;\n+\t}\n+done:\n+\n+\treturn retval;\n+}\n+\n+#endif /* DWC_DEVICE_ONLY */\n--- /dev/null\n+++ b/drivers/usb/host/dwc_otg/dwc_otg_os_dep.h\n@@ -0,0 +1,200 @@\n+#ifndef _DWC_OS_DEP_H_\n+#define _DWC_OS_DEP_H_\n+\n+/**\n+ * @file\n+ *\n+ * This file contains OS dependent structures.\n+ *\n+ */\n+\n+#include <linux/kernel.h>\n+#include <linux/module.h>\n+#include <linux/moduleparam.h>\n+#include <linux/init.h>\n+#include <linux/device.h>\n+#include <linux/errno.h>\n+#include <linux/types.h>\n+#include <linux/slab.h>\n+#include <linux/list.h>\n+#include <linux/interrupt.h>\n+#include <linux/ctype.h>\n+#include <linux/string.h>\n+#include <linux/dma-mapping.h>\n+#include <linux/jiffies.h>\n+#include <linux/delay.h>\n+#include <linux/timer.h>\n+#include <linux/workqueue.h>\n+#include <linux/stat.h>\n+#include <linux/pci.h>\n+#include <linux/compiler.h>\n+\n+#include <linux/version.h>\n+\n+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)\n+# include <linux/irq.h>\n+#endif\n+\n+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,21)\n+# include <linux/usb/ch9.h>\n+#else\n+# include <linux/usb_ch9.h>\n+#endif\n+\n+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24)\n+# include <linux/usb/gadget.h>\n+#else\n+# include <linux/usb_gadget.h>\n+#endif\n+\n+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)\n+# include <asm/irq.h>\n+#endif\n+\n+#ifdef PCI_INTERFACE\n+# include <asm/io.h>\n+#endif\n+\n+#ifdef LM_INTERFACE\n+# include <asm/unaligned.h>\n+# include <asm/sizes.h>\n+# include <asm/param.h>\n+# include <asm/io.h>\n+# if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30))\n+#  include <asm/arch/hardware.h>\n+#  include <asm/arch/lm.h>\n+#  include <asm/arch/irqs.h>\n+#  include <asm/arch/regs-irq.h>\n+# else\n+/* in 2.6.31, at least, we seem to have lost the generic LM infrastructure -\n+   here we assume that the machine architecture provides definitions\n+   in its own header\n+*/\n+#  include <mach/lm.h>\n+#  include <mach/hardware.h>\n+# endif\n+#endif\n+\n+#ifdef PLATFORM_INTERFACE\n+#include <linux/platform_device.h>\n+#ifdef CONFIG_ARM\n+#include <asm/mach/map.h>\n+#endif\n+#endif\n+\n+/** The OS page size */\n+#define DWC_OS_PAGE_SIZE\tPAGE_SIZE\n+\n+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,14)\n+typedef int gfp_t;\n+#endif\n+\n+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18)\n+# define IRQF_SHARED SA_SHIRQ\n+#endif\n+\n+typedef struct os_dependent {\n+\t/** Base address returned from ioremap() */\n+\tvoid *base;\n+\n+\t/** Register offset for Diagnostic API */\n+\tuint32_t reg_offset;\n+\n+\t/** Base address for MPHI peripheral */\n+\tvoid *mphi_base;\n+\n+\t/** mphi_base actually points to the SWIRQ block */\n+\tbool use_swirq;\n+\n+\t/** IRQ number (<0 if not valid) */\n+\tint irq_num;\n+\n+\t/** FIQ number (<0 if not valid) */\n+\tint fiq_num;\n+\n+#ifdef LM_INTERFACE\n+\tstruct lm_device *lmdev;\n+#elif  defined(PCI_INTERFACE)\n+\tstruct pci_dev *pcidev;\n+\n+\t/** Start address of a PCI region */\n+\tresource_size_t rsrc_start;\n+\n+\t/** Length address of a PCI region */\n+\tresource_size_t rsrc_len;\n+#elif  defined(PLATFORM_INTERFACE)\n+\tstruct platform_device *platformdev;\n+#endif\n+\n+} os_dependent_t;\n+\n+#ifdef __cplusplus\n+}\n+#endif\n+\n+\n+\n+/* Type for the our device on the chosen bus */\n+#if   defined(LM_INTERFACE)\n+typedef struct lm_device       dwc_bus_dev_t;\n+#elif defined(PCI_INTERFACE)\n+typedef struct pci_dev         dwc_bus_dev_t;\n+#elif defined(PLATFORM_INTERFACE)\n+typedef struct platform_device dwc_bus_dev_t;\n+#endif\n+\n+/* Helper macro to retrieve drvdata from the device on the chosen bus */\n+#if    defined(LM_INTERFACE)\n+#define DWC_OTG_BUSDRVDATA(_dev) lm_get_drvdata(_dev)\n+#elif  defined(PCI_INTERFACE)\n+#define DWC_OTG_BUSDRVDATA(_dev) pci_get_drvdata(_dev)\n+#elif  defined(PLATFORM_INTERFACE)\n+#define DWC_OTG_BUSDRVDATA(_dev) platform_get_drvdata(_dev)\n+#endif\n+\n+/**\n+ * Helper macro returning the otg_device structure of a given struct device\n+ *\n+ * c.f. static dwc_otg_device_t *dwc_otg_drvdev(struct device *_dev)\n+ */\n+#ifdef LM_INTERFACE\n+#define DWC_OTG_GETDRVDEV(_var, _dev) do { \\\n+                struct lm_device *lm_dev = \\\n+                        container_of(_dev, struct lm_device, dev); \\\n+                _var = lm_get_drvdata(lm_dev); \\\n+        } while (0)\n+\n+#elif defined(PCI_INTERFACE)\n+#define DWC_OTG_GETDRVDEV(_var, _dev) do { \\\n+                _var = dev_get_drvdata(_dev); \\\n+        } while (0)\n+\n+#elif defined(PLATFORM_INTERFACE)\n+#define DWC_OTG_GETDRVDEV(_var, _dev) do { \\\n+                struct platform_device *platform_dev = \\\n+                        container_of(_dev, struct platform_device, dev); \\\n+                _var = platform_get_drvdata(platform_dev); \\\n+        } while (0)\n+#endif\n+\n+\n+/**\n+ * Helper macro returning the struct dev of the given struct os_dependent\n+ *\n+ * c.f. static struct device *dwc_otg_getdev(struct os_dependent *osdep)\n+ */\n+#ifdef LM_INTERFACE\n+#define DWC_OTG_OS_GETDEV(_osdep) \\\n+        ((_osdep).lmdev == NULL? NULL: &(_osdep).lmdev->dev)\n+#elif defined(PCI_INTERFACE)\n+#define DWC_OTG_OS_GETDEV(_osdep) \\\n+        ((_osdep).pci_dev == NULL? NULL: &(_osdep).pci_dev->dev)\n+#elif defined(PLATFORM_INTERFACE)\n+#define DWC_OTG_OS_GETDEV(_osdep) \\\n+        ((_osdep).platformdev == NULL? NULL: &(_osdep).platformdev->dev)\n+#endif\n+\n+\n+\n+\n+#endif /* _DWC_OS_DEP_H_ */\n--- /dev/null\n+++ b/drivers/usb/host/dwc_otg/dwc_otg_pcd.c\n@@ -0,0 +1,2725 @@\n+/* ==========================================================================\n+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd.c $\n+ * $Revision: #101 $\n+ * $Date: 2012/08/10 $\n+ * $Change: 2047372 $\n+ *\n+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,\n+ * \"Software\") is an Unsupported proprietary work of Synopsys, Inc. unless\n+ * otherwise expressly agreed to in writing between Synopsys and you.\n+ *\n+ * The Software IS NOT an item of Licensed Software or Licensed Product under\n+ * any End User Software License Agreement or Agreement for Licensed Product\n+ * with Synopsys or any supplement thereto. You are permitted to use and\n+ * redistribute this Software in source and binary forms, with or without\n+ * modification, provided that redistributions of source code must retain this\n+ * notice. You may not view, use, disclose, copy or distribute this file or\n+ * any information contained herein except pursuant to this license grant from\n+ * Synopsys. If you do not agree with this notice, including the disclaimer\n+ * below, then you are not authorized to use the Software.\n+ *\n+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN \"AS IS\" BASIS\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,\n+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH\n+ * DAMAGE.\n+ * ========================================================================== */\n+#ifndef DWC_HOST_ONLY\n+\n+/** @file\n+ * This file implements PCD Core. All code in this file is portable and doesn't\n+ * use any OS specific functions.\n+ * PCD Core provides Interface, defined in <code><dwc_otg_pcd_if.h></code>\n+ * header file, which can be used to implement OS specific PCD interface.\n+ *\n+ * An important function of the PCD is managing interrupts generated\n+ * by the DWC_otg controller. The implementation of the DWC_otg device\n+ * mode interrupt service routines is in dwc_otg_pcd_intr.c.\n+ *\n+ * @todo Add Device Mode test modes (Test J mode, Test K mode, etc).\n+ * @todo Does it work when the request size is greater than DEPTSIZ\n+ * transfer size\n+ *\n+ */\n+\n+#include \"dwc_otg_pcd.h\"\n+\n+#ifdef DWC_UTE_CFI\n+#include \"dwc_otg_cfi.h\"\n+\n+extern int init_cfi(cfiobject_t * cfiobj);\n+#endif\n+\n+/**\n+ * Choose endpoint from ep arrays using usb_ep structure.\n+ */\n+static dwc_otg_pcd_ep_t *get_ep_from_handle(dwc_otg_pcd_t * pcd, void *handle)\n+{\n+\tint i;\n+\tif (pcd->ep0.priv == handle) {\n+\t\treturn &pcd->ep0;\n+\t}\n+\tfor (i = 0; i < MAX_EPS_CHANNELS - 1; i++) {\n+\t\tif (pcd->in_ep[i].priv == handle)\n+\t\t\treturn &pcd->in_ep[i];\n+\t\tif (pcd->out_ep[i].priv == handle)\n+\t\t\treturn &pcd->out_ep[i];\n+\t}\n+\n+\treturn NULL;\n+}\n+\n+/**\n+ * This function completes a request.  It call's the request call back.\n+ */\n+void dwc_otg_request_done(dwc_otg_pcd_ep_t * ep, dwc_otg_pcd_request_t * req,\n+\t\t\t  int32_t status)\n+{\n+\tunsigned stopped = ep->stopped;\n+\n+\tDWC_DEBUGPL(DBG_PCDV, \"%s(ep %p req %p)\\n\", __func__, ep, req);\n+\tDWC_CIRCLEQ_REMOVE_INIT(&ep->queue, req, queue_entry);\n+\n+\t/* don't modify queue heads during completion callback */\n+\tep->stopped = 1;\n+\t/* spin_unlock/spin_lock now done in fops->complete() */\n+\tep->pcd->fops->complete(ep->pcd, ep->priv, req->priv, status,\n+\t\t\t\treq->actual);\n+\n+\tif (ep->pcd->request_pending > 0) {\n+\t\t--ep->pcd->request_pending;\n+\t}\n+\n+\tep->stopped = stopped;\n+\tDWC_FREE(req);\n+}\n+\n+/**\n+ * This function terminates all the requsts in the EP request queue.\n+ */\n+void dwc_otg_request_nuke(dwc_otg_pcd_ep_t * ep)\n+{\n+\tdwc_otg_pcd_request_t *req;\n+\n+\tep->stopped = 1;\n+\n+\t/* called with irqs blocked?? */\n+\twhile (!DWC_CIRCLEQ_EMPTY(&ep->queue)) {\n+\t\treq = DWC_CIRCLEQ_FIRST(&ep->queue);\n+\t\tdwc_otg_request_done(ep, req, -DWC_E_SHUTDOWN);\n+\t}\n+}\n+\n+void dwc_otg_pcd_start(dwc_otg_pcd_t * pcd,\n+\t\t       const struct dwc_otg_pcd_function_ops *fops)\n+{\n+\tpcd->fops = fops;\n+}\n+\n+/**\n+ * PCD Callback function for initializing the PCD when switching to\n+ * device mode.\n+ *\n+ * @param p void pointer to the <code>dwc_otg_pcd_t</code>\n+ */\n+static int32_t dwc_otg_pcd_start_cb(void *p)\n+{\n+\tdwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *) p;\n+\tdwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);\n+\n+\t/*\n+\t * Initialized the Core for Device mode.\n+\t */\n+\tif (dwc_otg_is_device_mode(core_if)) {\n+\t\tdwc_otg_core_dev_init(core_if);\n+\t\t/* Set core_if's lock pointer to the pcd->lock */\n+\t\tcore_if->lock = pcd->lock;\n+\t}\n+\treturn 1;\n+}\n+\n+/** CFI-specific buffer allocation function for EP */\n+#ifdef DWC_UTE_CFI\n+uint8_t *cfiw_ep_alloc_buffer(dwc_otg_pcd_t * pcd, void *pep, dwc_dma_t * addr,\n+\t\t\t      size_t buflen, int flags)\n+{\n+\tdwc_otg_pcd_ep_t *ep;\n+\tep = get_ep_from_handle(pcd, pep);\n+\tif (!ep) {\n+\t\tDWC_WARN(\"bad ep\\n\");\n+\t\treturn -DWC_E_INVALID;\n+\t}\n+\n+\treturn pcd->cfi->ops.ep_alloc_buf(pcd->cfi, pcd, ep, addr, buflen,\n+\t\t\t\t\t  flags);\n+}\n+#else\n+uint8_t *cfiw_ep_alloc_buffer(dwc_otg_pcd_t * pcd, void *pep, dwc_dma_t * addr,\n+\t\t\t      size_t buflen, int flags);\n+#endif\n+\n+/**\n+ * PCD Callback function for notifying the PCD when resuming from\n+ * suspend.\n+ *\n+ * @param p void pointer to the <code>dwc_otg_pcd_t</code>\n+ */\n+static int32_t dwc_otg_pcd_resume_cb(void *p)\n+{\n+\tdwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *) p;\n+\n+\tif (pcd->fops->resume) {\n+\t\tpcd->fops->resume(pcd);\n+\t}\n+\n+\t/* Stop the SRP timeout timer. */\n+\tif ((GET_CORE_IF(pcd)->core_params->phy_type != DWC_PHY_TYPE_PARAM_FS)\n+\t    || (!GET_CORE_IF(pcd)->core_params->i2c_enable)) {\n+\t\tif (GET_CORE_IF(pcd)->srp_timer_started) {\n+\t\t\tGET_CORE_IF(pcd)->srp_timer_started = 0;\n+\t\t\tDWC_TIMER_CANCEL(GET_CORE_IF(pcd)->srp_timer);\n+\t\t}\n+\t}\n+\treturn 1;\n+}\n+\n+/**\n+ * PCD Callback function for notifying the PCD device is suspended.\n+ *\n+ * @param p void pointer to the <code>dwc_otg_pcd_t</code>\n+ */\n+static int32_t dwc_otg_pcd_suspend_cb(void *p)\n+{\n+\tdwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *) p;\n+\n+\tif (pcd->fops->suspend) {\n+\t\tDWC_SPINUNLOCK(pcd->lock);\n+\t\tpcd->fops->suspend(pcd);\n+\t\tDWC_SPINLOCK(pcd->lock);\n+\t}\n+\n+\treturn 1;\n+}\n+\n+/**\n+ * PCD Callback function for stopping the PCD when switching to Host\n+ * mode.\n+ *\n+ * @param p void pointer to the <code>dwc_otg_pcd_t</code>\n+ */\n+static int32_t dwc_otg_pcd_stop_cb(void *p)\n+{\n+\tdwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *) p;\n+\textern void dwc_otg_pcd_stop(dwc_otg_pcd_t * _pcd);\n+\n+\tdwc_otg_pcd_stop(pcd);\n+\treturn 1;\n+}\n+\n+/**\n+ * PCD Callback structure for handling mode switching.\n+ */\n+static dwc_otg_cil_callbacks_t pcd_callbacks = {\n+\t.start = dwc_otg_pcd_start_cb,\n+\t.stop = dwc_otg_pcd_stop_cb,\n+\t.suspend = dwc_otg_pcd_suspend_cb,\n+\t.resume_wakeup = dwc_otg_pcd_resume_cb,\n+\t.p = 0,\t\t\t/* Set at registration */\n+};\n+\n+/**\n+ * This function allocates a DMA Descriptor chain for the Endpoint\n+ * buffer to be used for a transfer to/from the specified endpoint.\n+ */\n+dwc_otg_dev_dma_desc_t *dwc_otg_ep_alloc_desc_chain(struct device *dev,\n+\t\t\t\t\t\t    dwc_dma_t * dma_desc_addr,\n+\t\t\t\t\t\t    uint32_t count)\n+{\n+\treturn DWC_DMA_ALLOC_ATOMIC(dev, count * sizeof(dwc_otg_dev_dma_desc_t),\n+\t\t\t\t\t\t\tdma_desc_addr);\n+}\n+\n+/**\n+ * This function frees a DMA Descriptor chain that was allocated by ep_alloc_desc.\n+ */\n+void dwc_otg_ep_free_desc_chain(struct device *dev,\n+\t\t\t\tdwc_otg_dev_dma_desc_t * desc_addr,\n+\t\t\t\tuint32_t dma_desc_addr, uint32_t count)\n+{\n+\tDWC_DMA_FREE(dev, count * sizeof(dwc_otg_dev_dma_desc_t), desc_addr,\n+\t\t     dma_desc_addr);\n+}\n+\n+#ifdef DWC_EN_ISOC\n+\n+/**\n+ * This function initializes a descriptor chain for Isochronous transfer\n+ *\n+ * @param core_if Programming view of DWC_otg controller.\n+ * @param dwc_ep The EP to start the transfer on.\n+ *\n+ */\n+void dwc_otg_iso_ep_start_ddma_transfer(dwc_otg_core_if_t * core_if,\n+\t\t\t\t\tdwc_ep_t * dwc_ep)\n+{\n+\n+\tdsts_data_t dsts = {.d32 = 0 };\n+\tdepctl_data_t depctl = {.d32 = 0 };\n+\tvolatile uint32_t *addr;\n+\tint i, j;\n+\tuint32_t len;\n+\n+\tif (dwc_ep->is_in)\n+\t\tdwc_ep->desc_cnt = dwc_ep->buf_proc_intrvl / dwc_ep->bInterval;\n+\telse\n+\t\tdwc_ep->desc_cnt =\n+\t\t    dwc_ep->buf_proc_intrvl * dwc_ep->pkt_per_frm /\n+\t\t    dwc_ep->bInterval;\n+\n+\t/** Allocate descriptors for double buffering */\n+\tdwc_ep->iso_desc_addr =\n+\t    dwc_otg_ep_alloc_desc_chain(&dwc_ep->iso_dma_desc_addr,\n+\t\t\t\t\tdwc_ep->desc_cnt * 2);\n+\tif (dwc_ep->desc_addr) {\n+\t\tDWC_WARN(\"%s, can't allocate DMA descriptor chain\\n\", __func__);\n+\t\treturn;\n+\t}\n+\n+\tdsts.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);\n+\n+\t/** ISO OUT EP */\n+\tif (dwc_ep->is_in == 0) {\n+\t\tdev_dma_desc_sts_t sts = {.d32 = 0 };\n+\t\tdwc_otg_dev_dma_desc_t *dma_desc = dwc_ep->iso_desc_addr;\n+\t\tdma_addr_t dma_ad;\n+\t\tuint32_t data_per_desc;\n+\t\tdwc_otg_dev_out_ep_regs_t *out_regs =\n+\t\t    core_if->dev_if->out_ep_regs[dwc_ep->num];\n+\t\tint offset;\n+\n+\t\taddr = &core_if->dev_if->out_ep_regs[dwc_ep->num]->doepctl;\n+\t\tdma_ad = (dma_addr_t) DWC_READ_REG32(&(out_regs->doepdma));\n+\n+\t\t/** Buffer 0 descriptors setup */\n+\t\tdma_ad = dwc_ep->dma_addr0;\n+\n+\t\tsts.b_iso_out.bs = BS_HOST_READY;\n+\t\tsts.b_iso_out.rxsts = 0;\n+\t\tsts.b_iso_out.l = 0;\n+\t\tsts.b_iso_out.sp = 0;\n+\t\tsts.b_iso_out.ioc = 0;\n+\t\tsts.b_iso_out.pid = 0;\n+\t\tsts.b_iso_out.framenum = 0;\n+\n+\t\toffset = 0;\n+\t\tfor (i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm;\n+\t\t     i += dwc_ep->pkt_per_frm) {\n+\n+\t\t\tfor (j = 0; j < dwc_ep->pkt_per_frm; ++j) {\n+\t\t\t\tuint32_t len = (j + 1) * dwc_ep->maxpacket;\n+\t\t\t\tif (len > dwc_ep->data_per_frame)\n+\t\t\t\t\tdata_per_desc =\n+\t\t\t\t\t    dwc_ep->data_per_frame -\n+\t\t\t\t\t    j * dwc_ep->maxpacket;\n+\t\t\t\telse\n+\t\t\t\t\tdata_per_desc = dwc_ep->maxpacket;\n+\t\t\t\tlen = data_per_desc % 4;\n+\t\t\t\tif (len)\n+\t\t\t\t\tdata_per_desc += 4 - len;\n+\n+\t\t\t\tsts.b_iso_out.rxbytes = data_per_desc;\n+\t\t\t\tdma_desc->buf = dma_ad;\n+\t\t\t\tdma_desc->status.d32 = sts.d32;\n+\n+\t\t\t\toffset += data_per_desc;\n+\t\t\t\tdma_desc++;\n+\t\t\t\tdma_ad += data_per_desc;\n+\t\t\t}\n+\t\t}\n+\n+\t\tfor (j = 0; j < dwc_ep->pkt_per_frm - 1; ++j) {\n+\t\t\tuint32_t len = (j + 1) * dwc_ep->maxpacket;\n+\t\t\tif (len > dwc_ep->data_per_frame)\n+\t\t\t\tdata_per_desc =\n+\t\t\t\t    dwc_ep->data_per_frame -\n+\t\t\t\t    j * dwc_ep->maxpacket;\n+\t\t\telse\n+\t\t\t\tdata_per_desc = dwc_ep->maxpacket;\n+\t\t\tlen = data_per_desc % 4;\n+\t\t\tif (len)\n+\t\t\t\tdata_per_desc += 4 - len;\n+\t\t\tsts.b_iso_out.rxbytes = data_per_desc;\n+\t\t\tdma_desc->buf = dma_ad;\n+\t\t\tdma_desc->status.d32 = sts.d32;\n+\n+\t\t\toffset += data_per_desc;\n+\t\t\tdma_desc++;\n+\t\t\tdma_ad += data_per_desc;\n+\t\t}\n+\n+\t\tsts.b_iso_out.ioc = 1;\n+\t\tlen = (j + 1) * dwc_ep->maxpacket;\n+\t\tif (len > dwc_ep->data_per_frame)\n+\t\t\tdata_per_desc =\n+\t\t\t    dwc_ep->data_per_frame - j * dwc_ep->maxpacket;\n+\t\telse\n+\t\t\tdata_per_desc = dwc_ep->maxpacket;\n+\t\tlen = data_per_desc % 4;\n+\t\tif (len)\n+\t\t\tdata_per_desc += 4 - len;\n+\t\tsts.b_iso_out.rxbytes = data_per_desc;\n+\n+\t\tdma_desc->buf = dma_ad;\n+\t\tdma_desc->status.d32 = sts.d32;\n+\t\tdma_desc++;\n+\n+\t\t/** Buffer 1 descriptors setup */\n+\t\tsts.b_iso_out.ioc = 0;\n+\t\tdma_ad = dwc_ep->dma_addr1;\n+\n+\t\toffset = 0;\n+\t\tfor (i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm;\n+\t\t     i += dwc_ep->pkt_per_frm) {\n+\t\t\tfor (j = 0; j < dwc_ep->pkt_per_frm; ++j) {\n+\t\t\t\tuint32_t len = (j + 1) * dwc_ep->maxpacket;\n+\t\t\t\tif (len > dwc_ep->data_per_frame)\n+\t\t\t\t\tdata_per_desc =\n+\t\t\t\t\t    dwc_ep->data_per_frame -\n+\t\t\t\t\t    j * dwc_ep->maxpacket;\n+\t\t\t\telse\n+\t\t\t\t\tdata_per_desc = dwc_ep->maxpacket;\n+\t\t\t\tlen = data_per_desc % 4;\n+\t\t\t\tif (len)\n+\t\t\t\t\tdata_per_desc += 4 - len;\n+\n+\t\t\t\tdata_per_desc =\n+\t\t\t\t    sts.b_iso_out.rxbytes = data_per_desc;\n+\t\t\t\tdma_desc->buf = dma_ad;\n+\t\t\t\tdma_desc->status.d32 = sts.d32;\n+\n+\t\t\t\toffset += data_per_desc;\n+\t\t\t\tdma_desc++;\n+\t\t\t\tdma_ad += data_per_desc;\n+\t\t\t}\n+\t\t}\n+\t\tfor (j = 0; j < dwc_ep->pkt_per_frm - 1; ++j) {\n+\t\t\tdata_per_desc =\n+\t\t\t    ((j + 1) * dwc_ep->maxpacket >\n+\t\t\t     dwc_ep->data_per_frame) ? dwc_ep->data_per_frame -\n+\t\t\t    j * dwc_ep->maxpacket : dwc_ep->maxpacket;\n+\t\t\tdata_per_desc +=\n+\t\t\t    (data_per_desc % 4) ? (4 - data_per_desc % 4) : 0;\n+\t\t\tsts.b_iso_out.rxbytes = data_per_desc;\n+\t\t\tdma_desc->buf = dma_ad;\n+\t\t\tdma_desc->status.d32 = sts.d32;\n+\n+\t\t\toffset += data_per_desc;\n+\t\t\tdma_desc++;\n+\t\t\tdma_ad += data_per_desc;\n+\t\t}\n+\n+\t\tsts.b_iso_out.ioc = 1;\n+\t\tsts.b_iso_out.l = 1;\n+\t\tdata_per_desc =\n+\t\t    ((j + 1) * dwc_ep->maxpacket >\n+\t\t     dwc_ep->data_per_frame) ? dwc_ep->data_per_frame -\n+\t\t    j * dwc_ep->maxpacket : dwc_ep->maxpacket;\n+\t\tdata_per_desc +=\n+\t\t    (data_per_desc % 4) ? (4 - data_per_desc % 4) : 0;\n+\t\tsts.b_iso_out.rxbytes = data_per_desc;\n+\n+\t\tdma_desc->buf = dma_ad;\n+\t\tdma_desc->status.d32 = sts.d32;\n+\n+\t\tdwc_ep->next_frame = 0;\n+\n+\t\t/** Write dma_ad into DOEPDMA register */\n+\t\tDWC_WRITE_REG32(&(out_regs->doepdma),\n+\t\t\t\t(uint32_t) dwc_ep->iso_dma_desc_addr);\n+\n+\t}\n+\t/** ISO IN EP */\n+\telse {\n+\t\tdev_dma_desc_sts_t sts = {.d32 = 0 };\n+\t\tdwc_otg_dev_dma_desc_t *dma_desc = dwc_ep->iso_desc_addr;\n+\t\tdma_addr_t dma_ad;\n+\t\tdwc_otg_dev_in_ep_regs_t *in_regs =\n+\t\t    core_if->dev_if->in_ep_regs[dwc_ep->num];\n+\t\tunsigned int frmnumber;\n+\t\tfifosize_data_t txfifosize, rxfifosize;\n+\n+\t\ttxfifosize.d32 =\n+\t\t    DWC_READ_REG32(&core_if->dev_if->in_ep_regs[dwc_ep->num]->\n+\t\t\t\t   dtxfsts);\n+\t\trxfifosize.d32 =\n+\t\t    DWC_READ_REG32(&core_if->core_global_regs->grxfsiz);\n+\n+\t\taddr = &core_if->dev_if->in_ep_regs[dwc_ep->num]->diepctl;\n+\n+\t\tdma_ad = dwc_ep->dma_addr0;\n+\n+\t\tdsts.d32 =\n+\t\t    DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);\n+\n+\t\tsts.b_iso_in.bs = BS_HOST_READY;\n+\t\tsts.b_iso_in.txsts = 0;\n+\t\tsts.b_iso_in.sp =\n+\t\t    (dwc_ep->data_per_frame % dwc_ep->maxpacket) ? 1 : 0;\n+\t\tsts.b_iso_in.ioc = 0;\n+\t\tsts.b_iso_in.pid = dwc_ep->pkt_per_frm;\n+\n+\t\tfrmnumber = dwc_ep->next_frame;\n+\n+\t\tsts.b_iso_in.framenum = frmnumber;\n+\t\tsts.b_iso_in.txbytes = dwc_ep->data_per_frame;\n+\t\tsts.b_iso_in.l = 0;\n+\n+\t\t/** Buffer 0 descriptors setup */\n+\t\tfor (i = 0; i < dwc_ep->desc_cnt - 1; i++) {\n+\t\t\tdma_desc->buf = dma_ad;\n+\t\t\tdma_desc->status.d32 = sts.d32;\n+\t\t\tdma_desc++;\n+\n+\t\t\tdma_ad += dwc_ep->data_per_frame;\n+\t\t\tsts.b_iso_in.framenum += dwc_ep->bInterval;\n+\t\t}\n+\n+\t\tsts.b_iso_in.ioc = 1;\n+\t\tdma_desc->buf = dma_ad;\n+\t\tdma_desc->status.d32 = sts.d32;\n+\t\t++dma_desc;\n+\n+\t\t/** Buffer 1 descriptors setup */\n+\t\tsts.b_iso_in.ioc = 0;\n+\t\tdma_ad = dwc_ep->dma_addr1;\n+\n+\t\tfor (i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm;\n+\t\t     i += dwc_ep->pkt_per_frm) {\n+\t\t\tdma_desc->buf = dma_ad;\n+\t\t\tdma_desc->status.d32 = sts.d32;\n+\t\t\tdma_desc++;\n+\n+\t\t\tdma_ad += dwc_ep->data_per_frame;\n+\t\t\tsts.b_iso_in.framenum += dwc_ep->bInterval;\n+\n+\t\t\tsts.b_iso_in.ioc = 0;\n+\t\t}\n+\t\tsts.b_iso_in.ioc = 1;\n+\t\tsts.b_iso_in.l = 1;\n+\n+\t\tdma_desc->buf = dma_ad;\n+\t\tdma_desc->status.d32 = sts.d32;\n+\n+\t\tdwc_ep->next_frame = sts.b_iso_in.framenum + dwc_ep->bInterval;\n+\n+\t\t/** Write dma_ad into diepdma register */\n+\t\tDWC_WRITE_REG32(&(in_regs->diepdma),\n+\t\t\t\t(uint32_t) dwc_ep->iso_dma_desc_addr);\n+\t}\n+\t/** Enable endpoint, clear nak  */\n+\tdepctl.d32 = 0;\n+\tdepctl.b.epena = 1;\n+\tdepctl.b.usbactep = 1;\n+\tdepctl.b.cnak = 1;\n+\n+\tDWC_MODIFY_REG32(addr, depctl.d32, depctl.d32);\n+\tdepctl.d32 = DWC_READ_REG32(addr);\n+}\n+\n+/**\n+ * This function initializes a descriptor chain for Isochronous transfer\n+ *\n+ * @param core_if Programming view of DWC_otg controller.\n+ * @param ep The EP to start the transfer on.\n+ *\n+ */\n+void dwc_otg_iso_ep_start_buf_transfer(dwc_otg_core_if_t * core_if,\n+\t\t\t\t       dwc_ep_t * ep)\n+{\n+\tdepctl_data_t depctl = {.d32 = 0 };\n+\tvolatile uint32_t *addr;\n+\n+\tif (ep->is_in) {\n+\t\taddr = &core_if->dev_if->in_ep_regs[ep->num]->diepctl;\n+\t} else {\n+\t\taddr = &core_if->dev_if->out_ep_regs[ep->num]->doepctl;\n+\t}\n+\n+\tif (core_if->dma_enable == 0 || core_if->dma_desc_enable != 0) {\n+\t\treturn;\n+\t} else {\n+\t\tdeptsiz_data_t deptsiz = {.d32 = 0 };\n+\n+\t\tep->xfer_len =\n+\t\t    ep->data_per_frame * ep->buf_proc_intrvl / ep->bInterval;\n+\t\tep->pkt_cnt =\n+\t\t    (ep->xfer_len - 1 + ep->maxpacket) / ep->maxpacket;\n+\t\tep->xfer_count = 0;\n+\t\tep->xfer_buff =\n+\t\t    (ep->proc_buf_num) ? ep->xfer_buff1 : ep->xfer_buff0;\n+\t\tep->dma_addr =\n+\t\t    (ep->proc_buf_num) ? ep->dma_addr1 : ep->dma_addr0;\n+\n+\t\tif (ep->is_in) {\n+\t\t\t/* Program the transfer size and packet count\n+\t\t\t *      as follows: xfersize = N * maxpacket +\n+\t\t\t *      short_packet pktcnt = N + (short_packet\n+\t\t\t *      exist ? 1 : 0)\n+\t\t\t */\n+\t\t\tdeptsiz.b.mc = ep->pkt_per_frm;\n+\t\t\tdeptsiz.b.xfersize = ep->xfer_len;\n+\t\t\tdeptsiz.b.pktcnt =\n+\t\t\t    (ep->xfer_len - 1 + ep->maxpacket) / ep->maxpacket;\n+\t\t\tDWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[ep->num]->\n+\t\t\t\t\tdieptsiz, deptsiz.d32);\n+\n+\t\t\t/* Write the DMA register */\n+\t\t\tDWC_WRITE_REG32(&\n+\t\t\t\t\t(core_if->dev_if->in_ep_regs[ep->num]->\n+\t\t\t\t\t diepdma), (uint32_t) ep->dma_addr);\n+\n+\t\t} else {\n+\t\t\tdeptsiz.b.pktcnt =\n+\t\t\t    (ep->xfer_len + (ep->maxpacket - 1)) /\n+\t\t\t    ep->maxpacket;\n+\t\t\tdeptsiz.b.xfersize = deptsiz.b.pktcnt * ep->maxpacket;\n+\n+\t\t\tDWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[ep->num]->\n+\t\t\t\t\tdoeptsiz, deptsiz.d32);\n+\n+\t\t\t/* Write the DMA register */\n+\t\t\tDWC_WRITE_REG32(&\n+\t\t\t\t\t(core_if->dev_if->out_ep_regs[ep->num]->\n+\t\t\t\t\t doepdma), (uint32_t) ep->dma_addr);\n+\n+\t\t}\n+\t\t/** Enable endpoint, clear nak  */\n+\t\tdepctl.d32 = 0;\n+\t\tdepctl.b.epena = 1;\n+\t\tdepctl.b.cnak = 1;\n+\n+\t\tDWC_MODIFY_REG32(addr, depctl.d32, depctl.d32);\n+\t}\n+}\n+\n+/**\n+ * This function does the setup for a data transfer for an EP and\n+ * starts the transfer. For an IN transfer, the packets will be\n+ * loaded into the appropriate Tx FIFO in the ISR. For OUT transfers,\n+ * the packets are unloaded from the Rx FIFO in the ISR.\n+ *\n+ * @param core_if Programming view of DWC_otg controller.\n+ * @param ep The EP to start the transfer on.\n+ */\n+\n+static void dwc_otg_iso_ep_start_transfer(dwc_otg_core_if_t * core_if,\n+\t\t\t\t\t  dwc_ep_t * ep)\n+{\n+\tif (core_if->dma_enable) {\n+\t\tif (core_if->dma_desc_enable) {\n+\t\t\tif (ep->is_in) {\n+\t\t\t\tep->desc_cnt = ep->pkt_cnt / ep->pkt_per_frm;\n+\t\t\t} else {\n+\t\t\t\tep->desc_cnt = ep->pkt_cnt;\n+\t\t\t}\n+\t\t\tdwc_otg_iso_ep_start_ddma_transfer(core_if, ep);\n+\t\t} else {\n+\t\t\tif (core_if->pti_enh_enable) {\n+\t\t\t\tdwc_otg_iso_ep_start_buf_transfer(core_if, ep);\n+\t\t\t} else {\n+\t\t\t\tep->cur_pkt_addr =\n+\t\t\t\t    (ep->proc_buf_num) ? ep->xfer_buff1 : ep->\n+\t\t\t\t    xfer_buff0;\n+\t\t\t\tep->cur_pkt_dma_addr =\n+\t\t\t\t    (ep->proc_buf_num) ? ep->dma_addr1 : ep->\n+\t\t\t\t    dma_addr0;\n+\t\t\t\tdwc_otg_iso_ep_start_frm_transfer(core_if, ep);\n+\t\t\t}\n+\t\t}\n+\t} else {\n+\t\tep->cur_pkt_addr =\n+\t\t    (ep->proc_buf_num) ? ep->xfer_buff1 : ep->xfer_buff0;\n+\t\tep->cur_pkt_dma_addr =\n+\t\t    (ep->proc_buf_num) ? ep->dma_addr1 : ep->dma_addr0;\n+\t\tdwc_otg_iso_ep_start_frm_transfer(core_if, ep);\n+\t}\n+}\n+\n+/**\n+ * This function stops transfer for an EP and\n+ * resets the ep's variables.\n+ *\n+ * @param core_if Programming view of DWC_otg controller.\n+ * @param ep The EP to start the transfer on.\n+ */\n+\n+void dwc_otg_iso_ep_stop_transfer(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)\n+{\n+\tdepctl_data_t depctl = {.d32 = 0 };\n+\tvolatile uint32_t *addr;\n+\n+\tif (ep->is_in == 1) {\n+\t\taddr = &core_if->dev_if->in_ep_regs[ep->num]->diepctl;\n+\t} else {\n+\t\taddr = &core_if->dev_if->out_ep_regs[ep->num]->doepctl;\n+\t}\n+\n+\t/* disable the ep */\n+\tdepctl.d32 = DWC_READ_REG32(addr);\n+\n+\tdepctl.b.epdis = 1;\n+\tdepctl.b.snak = 1;\n+\n+\tDWC_WRITE_REG32(addr, depctl.d32);\n+\n+\tif (core_if->dma_desc_enable &&\n+\t    ep->iso_desc_addr && ep->iso_dma_desc_addr) {\n+\t\tdwc_otg_ep_free_desc_chain(ep->iso_desc_addr,\n+\t\t\t\t\t   ep->iso_dma_desc_addr,\n+\t\t\t\t\t   ep->desc_cnt * 2);\n+\t}\n+\n+\t/* reset varibales */\n+\tep->dma_addr0 = 0;\n+\tep->dma_addr1 = 0;\n+\tep->xfer_buff0 = 0;\n+\tep->xfer_buff1 = 0;\n+\tep->data_per_frame = 0;\n+\tep->data_pattern_frame = 0;\n+\tep->sync_frame = 0;\n+\tep->buf_proc_intrvl = 0;\n+\tep->bInterval = 0;\n+\tep->proc_buf_num = 0;\n+\tep->pkt_per_frm = 0;\n+\tep->pkt_per_frm = 0;\n+\tep->desc_cnt = 0;\n+\tep->iso_desc_addr = 0;\n+\tep->iso_dma_desc_addr = 0;\n+}\n+\n+int dwc_otg_pcd_iso_ep_start(dwc_otg_pcd_t * pcd, void *ep_handle,\n+\t\t\t     uint8_t * buf0, uint8_t * buf1, dwc_dma_t dma0,\n+\t\t\t     dwc_dma_t dma1, int sync_frame, int dp_frame,\n+\t\t\t     int data_per_frame, int start_frame,\n+\t\t\t     int buf_proc_intrvl, void *req_handle,\n+\t\t\t     int atomic_alloc)\n+{\n+\tdwc_otg_pcd_ep_t *ep;\n+\tdwc_irqflags_t flags = 0;\n+\tdwc_ep_t *dwc_ep;\n+\tint32_t frm_data;\n+\tdsts_data_t dsts;\n+\tdwc_otg_core_if_t *core_if;\n+\n+\tep = get_ep_from_handle(pcd, ep_handle);\n+\n+\tif (!ep || !ep->desc || ep->dwc_ep.num == 0) {\n+\t\tDWC_WARN(\"bad ep\\n\");\n+\t\treturn -DWC_E_INVALID;\n+\t}\n+\n+\tDWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);\n+\tcore_if = GET_CORE_IF(pcd);\n+\tdwc_ep = &ep->dwc_ep;\n+\n+\tif (ep->iso_req_handle) {\n+\t\tDWC_WARN(\"ISO request in progress\\n\");\n+\t}\n+\n+\tdwc_ep->dma_addr0 = dma0;\n+\tdwc_ep->dma_addr1 = dma1;\n+\n+\tdwc_ep->xfer_buff0 = buf0;\n+\tdwc_ep->xfer_buff1 = buf1;\n+\n+\tdwc_ep->data_per_frame = data_per_frame;\n+\n+\t/** @todo - pattern data support is to be implemented in the future */\n+\tdwc_ep->data_pattern_frame = dp_frame;\n+\tdwc_ep->sync_frame = sync_frame;\n+\n+\tdwc_ep->buf_proc_intrvl = buf_proc_intrvl;\n+\n+\tdwc_ep->bInterval = 1 << (ep->desc->bInterval - 1);\n+\n+\tdwc_ep->proc_buf_num = 0;\n+\n+\tdwc_ep->pkt_per_frm = 0;\n+\tfrm_data = ep->dwc_ep.data_per_frame;\n+\twhile (frm_data > 0) {\n+\t\tdwc_ep->pkt_per_frm++;\n+\t\tfrm_data -= ep->dwc_ep.maxpacket;\n+\t}\n+\n+\tdsts.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);\n+\n+\tif (start_frame == -1) {\n+\t\tdwc_ep->next_frame = dsts.b.soffn + 1;\n+\t\tif (dwc_ep->bInterval != 1) {\n+\t\t\tdwc_ep->next_frame =\n+\t\t\t    dwc_ep->next_frame + (dwc_ep->bInterval - 1 -\n+\t\t\t\t\t\t  dwc_ep->next_frame %\n+\t\t\t\t\t\t  dwc_ep->bInterval);\n+\t\t}\n+\t} else {\n+\t\tdwc_ep->next_frame = start_frame;\n+\t}\n+\n+\tif (!core_if->pti_enh_enable) {\n+\t\tdwc_ep->pkt_cnt =\n+\t\t    dwc_ep->buf_proc_intrvl * dwc_ep->pkt_per_frm /\n+\t\t    dwc_ep->bInterval;\n+\t} else {\n+\t\tdwc_ep->pkt_cnt =\n+\t\t    (dwc_ep->data_per_frame *\n+\t\t     (dwc_ep->buf_proc_intrvl / dwc_ep->bInterval)\n+\t\t     - 1 + dwc_ep->maxpacket) / dwc_ep->maxpacket;\n+\t}\n+\n+\tif (core_if->dma_desc_enable) {\n+\t\tdwc_ep->desc_cnt =\n+\t\t    dwc_ep->buf_proc_intrvl * dwc_ep->pkt_per_frm /\n+\t\t    dwc_ep->bInterval;\n+\t}\n+\n+\tif (atomic_alloc) {\n+\t\tdwc_ep->pkt_info =\n+\t\t    DWC_ALLOC_ATOMIC(sizeof(iso_pkt_info_t) * dwc_ep->pkt_cnt);\n+\t} else {\n+\t\tdwc_ep->pkt_info =\n+\t\t    DWC_ALLOC(sizeof(iso_pkt_info_t) * dwc_ep->pkt_cnt);\n+\t}\n+\tif (!dwc_ep->pkt_info) {\n+\t\tDWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);\n+\t\treturn -DWC_E_NO_MEMORY;\n+\t}\n+\tif (core_if->pti_enh_enable) {\n+\t\tdwc_memset(dwc_ep->pkt_info, 0,\n+\t\t\t   sizeof(iso_pkt_info_t) * dwc_ep->pkt_cnt);\n+\t}\n+\n+\tdwc_ep->cur_pkt = 0;\n+\tep->iso_req_handle = req_handle;\n+\n+\tDWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);\n+\tdwc_otg_iso_ep_start_transfer(core_if, dwc_ep);\n+\treturn 0;\n+}\n+\n+int dwc_otg_pcd_iso_ep_stop(dwc_otg_pcd_t * pcd, void *ep_handle,\n+\t\t\t    void *req_handle)\n+{\n+\tdwc_irqflags_t flags = 0;\n+\tdwc_otg_pcd_ep_t *ep;\n+\tdwc_ep_t *dwc_ep;\n+\n+\tep = get_ep_from_handle(pcd, ep_handle);\n+\tif (!ep || !ep->desc || ep->dwc_ep.num == 0) {\n+\t\tDWC_WARN(\"bad ep\\n\");\n+\t\treturn -DWC_E_INVALID;\n+\t}\n+\tdwc_ep = &ep->dwc_ep;\n+\n+\tdwc_otg_iso_ep_stop_transfer(GET_CORE_IF(pcd), dwc_ep);\n+\n+\tDWC_FREE(dwc_ep->pkt_info);\n+\tDWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);\n+\tif (ep->iso_req_handle != req_handle) {\n+\t\tDWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);\n+\t\treturn -DWC_E_INVALID;\n+\t}\n+\n+\tDWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);\n+\n+\tep->iso_req_handle = 0;\n+\treturn 0;\n+}\n+\n+/**\n+ * This function is used for perodical data exchnage between PCD and gadget drivers.\n+ * for Isochronous EPs\n+ *\n+ *\t- Every time a sync period completes this function is called to\n+ *\t  perform data exchange between PCD and gadget\n+ */\n+void dwc_otg_iso_buffer_done(dwc_otg_pcd_t * pcd, dwc_otg_pcd_ep_t * ep,\n+\t\t\t     void *req_handle)\n+{\n+\tint i;\n+\tdwc_ep_t *dwc_ep;\n+\n+\tdwc_ep = &ep->dwc_ep;\n+\n+\tDWC_SPINUNLOCK(ep->pcd->lock);\n+\tpcd->fops->isoc_complete(pcd, ep->priv, ep->iso_req_handle,\n+\t\t\t\t dwc_ep->proc_buf_num ^ 0x1);\n+\tDWC_SPINLOCK(ep->pcd->lock);\n+\n+\tfor (i = 0; i < dwc_ep->pkt_cnt; ++i) {\n+\t\tdwc_ep->pkt_info[i].status = 0;\n+\t\tdwc_ep->pkt_info[i].offset = 0;\n+\t\tdwc_ep->pkt_info[i].length = 0;\n+\t}\n+}\n+\n+int dwc_otg_pcd_get_iso_packet_count(dwc_otg_pcd_t * pcd, void *ep_handle,\n+\t\t\t\t     void *iso_req_handle)\n+{\n+\tdwc_otg_pcd_ep_t *ep;\n+\tdwc_ep_t *dwc_ep;\n+\n+\tep = get_ep_from_handle(pcd, ep_handle);\n+\tif (!ep->desc || ep->dwc_ep.num == 0) {\n+\t\tDWC_WARN(\"bad ep\\n\");\n+\t\treturn -DWC_E_INVALID;\n+\t}\n+\tdwc_ep = &ep->dwc_ep;\n+\n+\treturn dwc_ep->pkt_cnt;\n+}\n+\n+void dwc_otg_pcd_get_iso_packet_params(dwc_otg_pcd_t * pcd, void *ep_handle,\n+\t\t\t\t       void *iso_req_handle, int packet,\n+\t\t\t\t       int *status, int *actual, int *offset)\n+{\n+\tdwc_otg_pcd_ep_t *ep;\n+\tdwc_ep_t *dwc_ep;\n+\n+\tep = get_ep_from_handle(pcd, ep_handle);\n+\tif (!ep)\n+\t\tDWC_WARN(\"bad ep\\n\");\n+\n+\tdwc_ep = &ep->dwc_ep;\n+\n+\t*status = dwc_ep->pkt_info[packet].status;\n+\t*actual = dwc_ep->pkt_info[packet].length;\n+\t*offset = dwc_ep->pkt_info[packet].offset;\n+}\n+\n+#endif /* DWC_EN_ISOC */\n+\n+static void dwc_otg_pcd_init_ep(dwc_otg_pcd_t * pcd, dwc_otg_pcd_ep_t * pcd_ep,\n+\t\t\t\tuint32_t is_in, uint32_t ep_num)\n+{\n+\t/* Init EP structure */\n+\tpcd_ep->desc = 0;\n+\tpcd_ep->pcd = pcd;\n+\tpcd_ep->stopped = 1;\n+\tpcd_ep->queue_sof = 0;\n+\n+\t/* Init DWC ep structure */\n+\tpcd_ep->dwc_ep.is_in = is_in;\n+\tpcd_ep->dwc_ep.num = ep_num;\n+\tpcd_ep->dwc_ep.active = 0;\n+\tpcd_ep->dwc_ep.tx_fifo_num = 0;\n+\t/* Control until ep is actvated */\n+\tpcd_ep->dwc_ep.type = DWC_OTG_EP_TYPE_CONTROL;\n+\tpcd_ep->dwc_ep.maxpacket = MAX_PACKET_SIZE;\n+\tpcd_ep->dwc_ep.dma_addr = 0;\n+\tpcd_ep->dwc_ep.start_xfer_buff = 0;\n+\tpcd_ep->dwc_ep.xfer_buff = 0;\n+\tpcd_ep->dwc_ep.xfer_len = 0;\n+\tpcd_ep->dwc_ep.xfer_count = 0;\n+\tpcd_ep->dwc_ep.sent_zlp = 0;\n+\tpcd_ep->dwc_ep.total_len = 0;\n+\tpcd_ep->dwc_ep.desc_addr = 0;\n+\tpcd_ep->dwc_ep.dma_desc_addr = 0;\n+\tDWC_CIRCLEQ_INIT(&pcd_ep->queue);\n+}\n+\n+/**\n+ * Initialize ep's\n+ */\n+static void dwc_otg_pcd_reinit(dwc_otg_pcd_t * pcd)\n+{\n+\tint i;\n+\tuint32_t hwcfg1;\n+\tdwc_otg_pcd_ep_t *ep;\n+\tint in_ep_cntr, out_ep_cntr;\n+\tuint32_t num_in_eps = (GET_CORE_IF(pcd))->dev_if->num_in_eps;\n+\tuint32_t num_out_eps = (GET_CORE_IF(pcd))->dev_if->num_out_eps;\n+\n+\t/**\n+\t * Initialize the EP0 structure.\n+\t */\n+\tep = &pcd->ep0;\n+\tdwc_otg_pcd_init_ep(pcd, ep, 0, 0);\n+\n+\tin_ep_cntr = 0;\n+\thwcfg1 = (GET_CORE_IF(pcd))->hwcfg1.d32 >> 3;\n+\tfor (i = 1; in_ep_cntr < num_in_eps; i++) {\n+\t\tif ((hwcfg1 & 0x1) == 0) {\n+\t\t\tdwc_otg_pcd_ep_t *ep = &pcd->in_ep[in_ep_cntr];\n+\t\t\tin_ep_cntr++;\n+\t\t\t/**\n+\t\t\t * @todo NGS: Add direction to EP, based on contents\n+\t\t\t * of HWCFG1.  Need a copy of HWCFG1 in pcd structure?\n+\t\t\t * sprintf(\";r\n+\t\t\t */\n+\t\t\tdwc_otg_pcd_init_ep(pcd, ep, 1 /* IN */ , i);\n+\n+\t\t\tDWC_CIRCLEQ_INIT(&ep->queue);\n+\t\t}\n+\t\thwcfg1 >>= 2;\n+\t}\n+\n+\tout_ep_cntr = 0;\n+\thwcfg1 = (GET_CORE_IF(pcd))->hwcfg1.d32 >> 2;\n+\tfor (i = 1; out_ep_cntr < num_out_eps; i++) {\n+\t\tif ((hwcfg1 & 0x1) == 0) {\n+\t\t\tdwc_otg_pcd_ep_t *ep = &pcd->out_ep[out_ep_cntr];\n+\t\t\tout_ep_cntr++;\n+\t\t\t/**\n+\t\t\t * @todo NGS: Add direction to EP, based on contents\n+\t\t\t * of HWCFG1.  Need a copy of HWCFG1 in pcd structure?\n+\t\t\t * sprintf(\";r\n+\t\t\t */\n+\t\t\tdwc_otg_pcd_init_ep(pcd, ep, 0 /* OUT */ , i);\n+\t\t\tDWC_CIRCLEQ_INIT(&ep->queue);\n+\t\t}\n+\t\thwcfg1 >>= 2;\n+\t}\n+\n+\tpcd->ep0state = EP0_DISCONNECT;\n+\tpcd->ep0.dwc_ep.maxpacket = MAX_EP0_SIZE;\n+\tpcd->ep0.dwc_ep.type = DWC_OTG_EP_TYPE_CONTROL;\n+}\n+\n+/**\n+ * This function is called when the SRP timer expires. The SRP should\n+ * complete within 6 seconds.\n+ */\n+static void srp_timeout(void *ptr)\n+{\n+\tgotgctl_data_t gotgctl;\n+\tdwc_otg_core_if_t *core_if = (dwc_otg_core_if_t *) ptr;\n+\tvolatile uint32_t *addr = &core_if->core_global_regs->gotgctl;\n+\n+\tgotgctl.d32 = DWC_READ_REG32(addr);\n+\n+\tcore_if->srp_timer_started = 0;\n+\n+\tif (core_if->adp_enable) {\n+\t\tif (gotgctl.b.bsesvld == 0) {\n+\t\t\tgpwrdn_data_t gpwrdn = {.d32 = 0 };\n+\t\t\tDWC_PRINTF(\"SRP Timeout BSESSVLD = 0\\n\");\n+\t\t\t/* Power off the core */\n+\t\t\tif (core_if->power_down == 2) {\n+\t\t\t\tgpwrdn.b.pwrdnswtch = 1;\n+\t\t\t\tDWC_MODIFY_REG32(&core_if->\n+\t\t\t\t\t\t core_global_regs->gpwrdn,\n+\t\t\t\t\t\t gpwrdn.d32, 0);\n+\t\t\t}\n+\n+\t\t\tgpwrdn.d32 = 0;\n+\t\t\tgpwrdn.b.pmuintsel = 1;\n+\t\t\tgpwrdn.b.pmuactv = 1;\n+\t\t\tDWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0,\n+\t\t\t\t\t gpwrdn.d32);\n+\t\t\tdwc_otg_adp_probe_start(core_if);\n+\t\t} else {\n+\t\t\tDWC_PRINTF(\"SRP Timeout BSESSVLD = 1\\n\");\n+\t\t\tcore_if->op_state = B_PERIPHERAL;\n+\t\t\tdwc_otg_core_init(core_if);\n+\t\t\tdwc_otg_enable_global_interrupts(core_if);\n+\t\t\tcil_pcd_start(core_if);\n+\t\t}\n+\t}\n+\n+\tif ((core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS) &&\n+\t    (core_if->core_params->i2c_enable)) {\n+\t\tDWC_PRINTF(\"SRP Timeout\\n\");\n+\n+\t\tif ((core_if->srp_success) && (gotgctl.b.bsesvld)) {\n+\t\t\tif (core_if->pcd_cb && core_if->pcd_cb->resume_wakeup) {\n+\t\t\t\tcore_if->pcd_cb->resume_wakeup(core_if->pcd_cb->p);\n+\t\t\t}\n+\n+\t\t\t/* Clear Session Request */\n+\t\t\tgotgctl.d32 = 0;\n+\t\t\tgotgctl.b.sesreq = 1;\n+\t\t\tDWC_MODIFY_REG32(&core_if->core_global_regs->gotgctl,\n+\t\t\t\t\t gotgctl.d32, 0);\n+\n+\t\t\tcore_if->srp_success = 0;\n+\t\t} else {\n+\t\t\t__DWC_ERROR(\"Device not connected/responding\\n\");\n+\t\t\tgotgctl.b.sesreq = 0;\n+\t\t\tDWC_WRITE_REG32(addr, gotgctl.d32);\n+\t\t}\n+\t} else if (gotgctl.b.sesreq) {\n+\t\tDWC_PRINTF(\"SRP Timeout\\n\");\n+\n+\t\t__DWC_ERROR(\"Device not connected/responding\\n\");\n+\t\tgotgctl.b.sesreq = 0;\n+\t\tDWC_WRITE_REG32(addr, gotgctl.d32);\n+\t} else {\n+\t\tDWC_PRINTF(\" SRP GOTGCTL=%0x\\n\", gotgctl.d32);\n+\t}\n+}\n+\n+/**\n+ * Tasklet\n+ *\n+ */\n+extern void start_next_request(dwc_otg_pcd_ep_t * ep);\n+\n+static void start_xfer_tasklet_func(void *data)\n+{\n+\tdwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *) data;\n+\tdwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);\n+\n+\tint i;\n+\tdepctl_data_t diepctl;\n+\n+\tDWC_DEBUGPL(DBG_PCDV, \"Start xfer tasklet\\n\");\n+\n+\tdiepctl.d32 = DWC_READ_REG32(&core_if->dev_if->in_ep_regs[0]->diepctl);\n+\n+\tif (pcd->ep0.queue_sof) {\n+\t\tpcd->ep0.queue_sof = 0;\n+\t\tstart_next_request(&pcd->ep0);\n+\t\t// break;\n+\t}\n+\n+\tfor (i = 0; i < core_if->dev_if->num_in_eps; i++) {\n+\t\tdepctl_data_t diepctl;\n+\t\tdiepctl.d32 =\n+\t\t    DWC_READ_REG32(&core_if->dev_if->in_ep_regs[i]->diepctl);\n+\n+\t\tif (pcd->in_ep[i].queue_sof) {\n+\t\t\tpcd->in_ep[i].queue_sof = 0;\n+\t\t\tstart_next_request(&pcd->in_ep[i]);\n+\t\t\t// break;\n+\t\t}\n+\t}\n+\n+\treturn;\n+}\n+\n+/**\n+ * This function initialized the PCD portion of the driver.\n+ *\n+ */\n+dwc_otg_pcd_t *dwc_otg_pcd_init(dwc_otg_device_t *otg_dev)\n+{\n+\tstruct device *dev = &otg_dev->os_dep.platformdev->dev;\n+\tdwc_otg_core_if_t *core_if = otg_dev->core_if;\n+\tdwc_otg_pcd_t *pcd = NULL;\n+\tdwc_otg_dev_if_t *dev_if;\n+\tint i;\n+\n+\t/*\n+\t * Allocate PCD structure\n+\t */\n+\tpcd = DWC_ALLOC(sizeof(dwc_otg_pcd_t));\n+\n+\tif (pcd == NULL) {\n+\t\treturn NULL;\n+\t}\n+\n+#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_SPINLOCK))\n+\tDWC_SPINLOCK_ALLOC_LINUX_DEBUG(pcd->lock);\n+#else\n+\tpcd->lock = DWC_SPINLOCK_ALLOC();\n+#endif\n+        DWC_DEBUGPL(DBG_HCDV, \"Init of PCD %p given core_if %p\\n\",\n+                    pcd, core_if);//GRAYG\n+\tif (!pcd->lock) {\n+\t\tDWC_ERROR(\"Could not allocate lock for pcd\");\n+\t\tDWC_FREE(pcd);\n+\t\treturn NULL;\n+\t}\n+\t/* Set core_if's lock pointer to hcd->lock */\n+\tcore_if->lock = pcd->lock;\n+\tpcd->core_if = core_if;\n+\n+\tdev_if = core_if->dev_if;\n+\tdev_if->isoc_ep = NULL;\n+\n+\tif (core_if->hwcfg4.b.ded_fifo_en) {\n+\t\tDWC_PRINTF(\"Dedicated Tx FIFOs mode\\n\");\n+\t} else {\n+\t\tDWC_PRINTF(\"Shared Tx FIFO mode\\n\");\n+\t}\n+\n+\t/*\n+\t * Initialized the Core for Device mode here if there is nod ADP support.\n+\t * Otherwise it will be done later in dwc_otg_adp_start routine.\n+\t */\n+\tif (dwc_otg_is_device_mode(core_if) /*&& !core_if->adp_enable*/) {\n+\t\tdwc_otg_core_dev_init(core_if);\n+\t}\n+\n+\t/*\n+\t * Register the PCD Callbacks.\n+\t */\n+\tdwc_otg_cil_register_pcd_callbacks(core_if, &pcd_callbacks, pcd);\n+\n+\t/*\n+\t * Initialize the DMA buffer for SETUP packets\n+\t */\n+\tif (GET_CORE_IF(pcd)->dma_enable) {\n+\t\tpcd->setup_pkt =\n+\t\t    DWC_DMA_ALLOC(dev, sizeof(*pcd->setup_pkt) * 5,\n+\t\t\t\t  &pcd->setup_pkt_dma_handle);\n+\t\tif (pcd->setup_pkt == NULL) {\n+\t\t\tDWC_FREE(pcd);\n+\t\t\treturn NULL;\n+\t\t}\n+\n+\t\tpcd->status_buf =\n+\t\t    DWC_DMA_ALLOC(dev, sizeof(uint16_t),\n+\t\t\t\t  &pcd->status_buf_dma_handle);\n+\t\tif (pcd->status_buf == NULL) {\n+\t\t\tDWC_DMA_FREE(dev, sizeof(*pcd->setup_pkt) * 5,\n+\t\t\t\t     pcd->setup_pkt, pcd->setup_pkt_dma_handle);\n+\t\t\tDWC_FREE(pcd);\n+\t\t\treturn NULL;\n+\t\t}\n+\n+\t\tif (GET_CORE_IF(pcd)->dma_desc_enable) {\n+\t\t\tdev_if->setup_desc_addr[0] =\n+\t\t\t    dwc_otg_ep_alloc_desc_chain(dev,\n+\t\t\t\t&dev_if->dma_setup_desc_addr[0], 1);\n+\t\t\tdev_if->setup_desc_addr[1] =\n+\t\t\t    dwc_otg_ep_alloc_desc_chain(dev,\n+\t\t\t\t&dev_if->dma_setup_desc_addr[1], 1);\n+\t\t\tdev_if->in_desc_addr =\n+\t\t\t    dwc_otg_ep_alloc_desc_chain(dev,\n+\t\t\t\t&dev_if->dma_in_desc_addr, 1);\n+\t\t\tdev_if->out_desc_addr =\n+\t\t\t    dwc_otg_ep_alloc_desc_chain(dev,\n+\t\t\t\t&dev_if->dma_out_desc_addr, 1);\n+\t\t\tpcd->data_terminated = 0;\n+\n+\t\t\tif (dev_if->setup_desc_addr[0] == 0\n+\t\t\t    || dev_if->setup_desc_addr[1] == 0\n+\t\t\t    || dev_if->in_desc_addr == 0\n+\t\t\t    || dev_if->out_desc_addr == 0) {\n+\n+\t\t\t\tif (dev_if->out_desc_addr)\n+\t\t\t\t\tdwc_otg_ep_free_desc_chain(dev,\n+\t\t\t\t\t     dev_if->out_desc_addr,\n+\t\t\t\t\t     dev_if->dma_out_desc_addr, 1);\n+\t\t\t\tif (dev_if->in_desc_addr)\n+\t\t\t\t\tdwc_otg_ep_free_desc_chain(dev,\n+\t\t\t\t\t     dev_if->in_desc_addr,\n+\t\t\t\t\t     dev_if->dma_in_desc_addr, 1);\n+\t\t\t\tif (dev_if->setup_desc_addr[1])\n+\t\t\t\t\tdwc_otg_ep_free_desc_chain(dev,\n+\t\t\t\t\t     dev_if->setup_desc_addr[1],\n+\t\t\t\t\t     dev_if->dma_setup_desc_addr[1], 1);\n+\t\t\t\tif (dev_if->setup_desc_addr[0])\n+\t\t\t\t\tdwc_otg_ep_free_desc_chain(dev,\n+\t\t\t\t\t     dev_if->setup_desc_addr[0],\n+\t\t\t\t\t     dev_if->dma_setup_desc_addr[0], 1);\n+\n+\t\t\t\tDWC_DMA_FREE(dev, sizeof(*pcd->setup_pkt) * 5,\n+\t\t\t\t\t     pcd->setup_pkt,\n+\t\t\t\t\t     pcd->setup_pkt_dma_handle);\n+\t\t\t\tDWC_DMA_FREE(dev, sizeof(*pcd->status_buf),\n+\t\t\t\t\t     pcd->status_buf,\n+\t\t\t\t\t     pcd->status_buf_dma_handle);\n+\n+\t\t\t\tDWC_FREE(pcd);\n+\n+\t\t\t\treturn NULL;\n+\t\t\t}\n+\t\t}\n+\t} else {\n+\t\tpcd->setup_pkt = DWC_ALLOC(sizeof(*pcd->setup_pkt) * 5);\n+\t\tif (pcd->setup_pkt == NULL) {\n+\t\t\tDWC_FREE(pcd);\n+\t\t\treturn NULL;\n+\t\t}\n+\n+\t\tpcd->status_buf = DWC_ALLOC(sizeof(uint16_t));\n+\t\tif (pcd->status_buf == NULL) {\n+\t\t\tDWC_FREE(pcd->setup_pkt);\n+\t\t\tDWC_FREE(pcd);\n+\t\t\treturn NULL;\n+\t\t}\n+\t}\n+\n+\tdwc_otg_pcd_reinit(pcd);\n+\n+\t/* Allocate the cfi object for the PCD */\n+#ifdef DWC_UTE_CFI\n+\tpcd->cfi = DWC_ALLOC(sizeof(cfiobject_t));\n+\tif (NULL == pcd->cfi)\n+\t\tgoto fail;\n+\tif (init_cfi(pcd->cfi)) {\n+\t\tCFI_INFO(\"%s: Failed to init the CFI object\\n\", __func__);\n+\t\tgoto fail;\n+\t}\n+#endif\n+\n+\t/* Initialize tasklets */\n+\tpcd->start_xfer_tasklet = DWC_TASK_ALLOC(\"xfer_tasklet\",\n+\t\t\t\t\t\t start_xfer_tasklet_func, pcd);\n+\tpcd->test_mode_tasklet = DWC_TASK_ALLOC(\"test_mode_tasklet\",\n+\t\t\t\t\t\tdo_test_mode, pcd);\n+\n+\t/* Initialize SRP timer */\n+\tcore_if->srp_timer = DWC_TIMER_ALLOC(\"SRP TIMER\", srp_timeout, core_if);\n+\n+\tif (core_if->core_params->dev_out_nak) {\n+\t\t/**\n+\t\t* Initialize xfer timeout timer. Implemented for\n+\t\t* 2.93a feature \"Device DDMA OUT NAK Enhancement\"\n+\t\t*/\n+\t\tfor(i = 0; i < MAX_EPS_CHANNELS; i++) {\n+\t\t\tpcd->core_if->ep_xfer_timer[i] =\n+\t\t\t\tDWC_TIMER_ALLOC(\"ep timer\", ep_xfer_timeout,\n+\t\t\t\t&pcd->core_if->ep_xfer_info[i]);\n+\t\t}\n+\t}\n+\n+\treturn pcd;\n+#ifdef DWC_UTE_CFI\n+fail:\n+#endif\n+\tif (pcd->setup_pkt)\n+\t\tDWC_FREE(pcd->setup_pkt);\n+\tif (pcd->status_buf)\n+\t\tDWC_FREE(pcd->status_buf);\n+#ifdef DWC_UTE_CFI\n+\tif (pcd->cfi)\n+\t\tDWC_FREE(pcd->cfi);\n+#endif\n+\tif (pcd)\n+\t\tDWC_FREE(pcd);\n+\treturn NULL;\n+\n+}\n+\n+/**\n+ * Remove PCD specific data\n+ */\n+void dwc_otg_pcd_remove(dwc_otg_pcd_t * pcd)\n+{\n+\tdwc_otg_dev_if_t *dev_if = GET_CORE_IF(pcd)->dev_if;\n+\tstruct device *dev = dwc_otg_pcd_to_dev(pcd);\n+\tint i;\n+\n+\tif (pcd->core_if->core_params->dev_out_nak) {\n+\t\tfor (i = 0; i < MAX_EPS_CHANNELS; i++) {\n+\t\t\tDWC_TIMER_CANCEL(pcd->core_if->ep_xfer_timer[i]);\n+\t\t\tpcd->core_if->ep_xfer_info[i].state = 0;\n+\t\t}\n+\t}\n+\n+\tif (GET_CORE_IF(pcd)->dma_enable) {\n+\t\tDWC_DMA_FREE(dev, sizeof(*pcd->setup_pkt) * 5, pcd->setup_pkt,\n+\t\t\t     pcd->setup_pkt_dma_handle);\n+\t\tDWC_DMA_FREE(dev, sizeof(uint16_t), pcd->status_buf,\n+\t\t\t     pcd->status_buf_dma_handle);\n+\t\tif (GET_CORE_IF(pcd)->dma_desc_enable) {\n+\t\t\tdwc_otg_ep_free_desc_chain(dev,\n+\t\t\t\t\t\t   dev_if->setup_desc_addr[0],\n+\t\t\t\t\t\t   dev_if->dma_setup_desc_addr\n+\t\t\t\t\t\t   [0], 1);\n+\t\t\tdwc_otg_ep_free_desc_chain(dev,\n+\t\t\t\t\t\t   dev_if->setup_desc_addr[1],\n+\t\t\t\t\t\t   dev_if->dma_setup_desc_addr\n+\t\t\t\t\t\t   [1], 1);\n+\t\t\tdwc_otg_ep_free_desc_chain(dev,\n+\t\t\t\t\t\t   dev_if->in_desc_addr,\n+\t\t\t\t\t\t   dev_if->dma_in_desc_addr, 1);\n+\t\t\tdwc_otg_ep_free_desc_chain(dev,\n+\t\t\t\t\t\t   dev_if->out_desc_addr,\n+\t\t\t\t\t\t   dev_if->dma_out_desc_addr,\n+\t\t\t\t\t\t   1);\n+\t\t}\n+\t} else {\n+\t\tDWC_FREE(pcd->setup_pkt);\n+\t\tDWC_FREE(pcd->status_buf);\n+\t}\n+\tDWC_SPINLOCK_FREE(pcd->lock);\n+\t/* Set core_if's lock pointer to NULL */\n+\tpcd->core_if->lock = NULL;\n+\n+\tDWC_TASK_FREE(pcd->start_xfer_tasklet);\n+\tDWC_TASK_FREE(pcd->test_mode_tasklet);\n+\tif (pcd->core_if->core_params->dev_out_nak) {\n+\t\tfor (i = 0; i < MAX_EPS_CHANNELS; i++) {\n+\t\t\tif (pcd->core_if->ep_xfer_timer[i]) {\n+\t\t\t\t\tDWC_TIMER_FREE(pcd->core_if->ep_xfer_timer[i]);\n+\t\t\t}\n+\t\t}\n+\t}\n+\n+/* Release the CFI object's dynamic memory */\n+#ifdef DWC_UTE_CFI\n+\tif (pcd->cfi->ops.release) {\n+\t\tpcd->cfi->ops.release(pcd->cfi);\n+\t}\n+#endif\n+\n+\tDWC_FREE(pcd);\n+}\n+\n+/**\n+ * Returns whether registered pcd is dual speed or not\n+ */\n+uint32_t dwc_otg_pcd_is_dualspeed(dwc_otg_pcd_t * pcd)\n+{\n+\tdwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);\n+\n+\tif ((core_if->core_params->speed == DWC_SPEED_PARAM_FULL) ||\n+\t    ((core_if->hwcfg2.b.hs_phy_type == 2) &&\n+\t     (core_if->hwcfg2.b.fs_phy_type == 1) &&\n+\t     (core_if->core_params->ulpi_fs_ls))) {\n+\t\treturn 0;\n+\t}\n+\n+\treturn 1;\n+}\n+\n+/**\n+ * Returns whether registered pcd is OTG capable or not\n+ */\n+uint32_t dwc_otg_pcd_is_otg(dwc_otg_pcd_t * pcd)\n+{\n+\tdwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);\n+\tgusbcfg_data_t usbcfg = {.d32 = 0 };\n+\n+\tusbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);\n+\tif (!usbcfg.b.srpcap || !usbcfg.b.hnpcap) {\n+\t\treturn 0;\n+\t}\n+\n+\treturn 1;\n+}\n+\n+/**\n+ * This function assigns periodic Tx FIFO to an periodic EP\n+ * in shared Tx FIFO mode\n+ */\n+static uint32_t assign_tx_fifo(dwc_otg_core_if_t * core_if)\n+{\n+\tuint32_t TxMsk = 1;\n+\tint i;\n+\n+\tfor (i = 0; i < core_if->hwcfg4.b.num_in_eps; ++i) {\n+\t\tif ((TxMsk & core_if->tx_msk) == 0) {\n+\t\t\tcore_if->tx_msk |= TxMsk;\n+\t\t\treturn i + 1;\n+\t\t}\n+\t\tTxMsk <<= 1;\n+\t}\n+\treturn 0;\n+}\n+\n+/**\n+ * This function assigns periodic Tx FIFO to an periodic EP\n+ * in shared Tx FIFO mode\n+ */\n+static uint32_t assign_perio_tx_fifo(dwc_otg_core_if_t * core_if)\n+{\n+\tuint32_t PerTxMsk = 1;\n+\tint i;\n+\tfor (i = 0; i < core_if->hwcfg4.b.num_dev_perio_in_ep; ++i) {\n+\t\tif ((PerTxMsk & core_if->p_tx_msk) == 0) {\n+\t\t\tcore_if->p_tx_msk |= PerTxMsk;\n+\t\t\treturn i + 1;\n+\t\t}\n+\t\tPerTxMsk <<= 1;\n+\t}\n+\treturn 0;\n+}\n+\n+/**\n+ * This function releases periodic Tx FIFO\n+ * in shared Tx FIFO mode\n+ */\n+static void release_perio_tx_fifo(dwc_otg_core_if_t * core_if,\n+\t\t\t\t  uint32_t fifo_num)\n+{\n+\tcore_if->p_tx_msk =\n+\t    (core_if->p_tx_msk & (1 << (fifo_num - 1))) ^ core_if->p_tx_msk;\n+}\n+\n+/**\n+ * This function releases periodic Tx FIFO\n+ * in shared Tx FIFO mode\n+ */\n+static void release_tx_fifo(dwc_otg_core_if_t * core_if, uint32_t fifo_num)\n+{\n+\tcore_if->tx_msk =\n+\t    (core_if->tx_msk & (1 << (fifo_num - 1))) ^ core_if->tx_msk;\n+}\n+\n+/**\n+ * This function is being called from gadget\n+ * to enable PCD endpoint.\n+ */\n+int dwc_otg_pcd_ep_enable(dwc_otg_pcd_t * pcd,\n+\t\t\t  const uint8_t * ep_desc, void *usb_ep)\n+{\n+\tint num, dir;\n+\tdwc_otg_pcd_ep_t *ep = NULL;\n+\tconst usb_endpoint_descriptor_t *desc;\n+\tdwc_irqflags_t flags;\n+\tfifosize_data_t dptxfsiz = {.d32 = 0 };\n+\tgdfifocfg_data_t gdfifocfg = {.d32 = 0 };\n+\tgdfifocfg_data_t gdfifocfgbase = {.d32 = 0 };\n+\tint retval = 0;\n+\tint i, epcount;\n+\tstruct device *dev = dwc_otg_pcd_to_dev(pcd);\n+\n+\tdesc = (const usb_endpoint_descriptor_t *)ep_desc;\n+\n+\tif (!desc) {\n+\t\tpcd->ep0.priv = usb_ep;\n+\t\tep = &pcd->ep0;\n+\t\tretval = -DWC_E_INVALID;\n+\t\tgoto out;\n+\t}\n+\n+\tnum = UE_GET_ADDR(desc->bEndpointAddress);\n+\tdir = UE_GET_DIR(desc->bEndpointAddress);\n+\n+\tif (!desc->wMaxPacketSize) {\n+\t\tDWC_WARN(\"bad maxpacketsize\\n\");\n+\t\tretval = -DWC_E_INVALID;\n+\t\tgoto out;\n+\t}\n+\n+\tif (dir == UE_DIR_IN) {\n+\t\tepcount = pcd->core_if->dev_if->num_in_eps;\n+\t\tfor (i = 0; i < epcount; i++) {\n+\t\t\tif (num == pcd->in_ep[i].dwc_ep.num) {\n+\t\t\t\tep = &pcd->in_ep[i];\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t}\n+\t} else {\n+\t\tepcount = pcd->core_if->dev_if->num_out_eps;\n+\t\tfor (i = 0; i < epcount; i++) {\n+\t\t\tif (num == pcd->out_ep[i].dwc_ep.num) {\n+\t\t\t\tep = &pcd->out_ep[i];\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t}\n+\t}\n+\n+\tif (!ep) {\n+\t\tDWC_WARN(\"bad address\\n\");\n+\t\tretval = -DWC_E_INVALID;\n+\t\tgoto out;\n+\t}\n+\n+\tDWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);\n+\n+\tep->desc = desc;\n+\tep->priv = usb_ep;\n+\n+\t/*\n+\t * Activate the EP\n+\t */\n+\tep->stopped = 0;\n+\n+\tep->dwc_ep.is_in = (dir == UE_DIR_IN);\n+\tep->dwc_ep.maxpacket = UGETW(desc->wMaxPacketSize);\n+\n+\tep->dwc_ep.type = desc->bmAttributes & UE_XFERTYPE;\n+\n+\tif (ep->dwc_ep.is_in) {\n+\t\tif (!GET_CORE_IF(pcd)->en_multiple_tx_fifo) {\n+\t\t\tep->dwc_ep.tx_fifo_num = 0;\n+\n+\t\t\tif (ep->dwc_ep.type == UE_ISOCHRONOUS) {\n+\t\t\t\t/*\n+\t\t\t\t * if ISOC EP then assign a Periodic Tx FIFO.\n+\t\t\t\t */\n+\t\t\t\tep->dwc_ep.tx_fifo_num =\n+\t\t\t\t    assign_perio_tx_fifo(GET_CORE_IF(pcd));\n+\t\t\t}\n+\t\t} else {\n+\t\t\t/*\n+\t\t\t * if Dedicated FIFOs mode is on then assign a Tx FIFO.\n+\t\t\t */\n+\t\t\tep->dwc_ep.tx_fifo_num =\n+\t\t\t    assign_tx_fifo(GET_CORE_IF(pcd));\n+\t\t}\n+\n+\t\t/* Calculating EP info controller base address */\n+\t\tif (ep->dwc_ep.tx_fifo_num\n+\t\t    && GET_CORE_IF(pcd)->en_multiple_tx_fifo) {\n+\t\t\tgdfifocfg.d32 =\n+\t\t\t    DWC_READ_REG32(&GET_CORE_IF(pcd)->\n+\t\t\t\t\t   core_global_regs->gdfifocfg);\n+\t\t\tgdfifocfgbase.d32 = gdfifocfg.d32 >> 16;\n+\t\t\tdptxfsiz.d32 =\n+\t\t\t    (DWC_READ_REG32\n+\t\t\t     (&GET_CORE_IF(pcd)->core_global_regs->\n+\t\t\t      dtxfsiz[ep->dwc_ep.tx_fifo_num - 1]) >> 16);\n+\t\t\tgdfifocfg.b.epinfobase =\n+\t\t\t    gdfifocfgbase.d32 + dptxfsiz.d32;\n+\t\t\tif (GET_CORE_IF(pcd)->snpsid <= OTG_CORE_REV_2_94a) {\n+\t\t\t\tDWC_WRITE_REG32(&GET_CORE_IF(pcd)->\n+\t\t\t\t\t\tcore_global_regs->gdfifocfg,\n+\t\t\t\t\t\tgdfifocfg.d32);\n+\t\t\t}\n+\t\t}\n+\t}\n+\t/* Set initial data PID. */\n+\tif (ep->dwc_ep.type == UE_BULK) {\n+\t\tep->dwc_ep.data_pid_start = 0;\n+\t}\n+\n+\t/* Alloc DMA Descriptors */\n+\tif (GET_CORE_IF(pcd)->dma_desc_enable) {\n+#ifndef DWC_UTE_PER_IO\n+\t\tif (ep->dwc_ep.type != UE_ISOCHRONOUS) {\n+#endif\n+\t\t\tep->dwc_ep.desc_addr =\n+\t\t\t    dwc_otg_ep_alloc_desc_chain(dev,\n+\t\t\t\t\t\t&ep->dwc_ep.dma_desc_addr,\n+\t\t\t\t\t\tMAX_DMA_DESC_CNT);\n+\t\t\tif (!ep->dwc_ep.desc_addr) {\n+\t\t\t\tDWC_WARN(\"%s, can't allocate DMA descriptor\\n\",\n+\t\t\t\t\t __func__);\n+\t\t\t\tretval = -DWC_E_SHUTDOWN;\n+\t\t\t\tDWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);\n+\t\t\t\tgoto out;\n+\t\t\t}\n+#ifndef DWC_UTE_PER_IO\n+\t\t}\n+#endif\n+\t}\n+\n+\tDWC_DEBUGPL(DBG_PCD, \"Activate %s: type=%d, mps=%d desc=%p\\n\",\n+\t\t    (ep->dwc_ep.is_in ? \"IN\" : \"OUT\"),\n+\t\t    ep->dwc_ep.type, ep->dwc_ep.maxpacket, ep->desc);\n+#ifdef DWC_UTE_PER_IO\n+\tep->dwc_ep.xiso_bInterval = 1 << (ep->desc->bInterval - 1);\n+#endif\n+\tif (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) {\n+\t\tep->dwc_ep.bInterval = 1 << (ep->desc->bInterval - 1);\n+\t\tep->dwc_ep.frame_num = 0xFFFFFFFF;\n+\t}\n+\n+\tdwc_otg_ep_activate(GET_CORE_IF(pcd), &ep->dwc_ep);\n+\n+#ifdef DWC_UTE_CFI\n+\tif (pcd->cfi->ops.ep_enable) {\n+\t\tpcd->cfi->ops.ep_enable(pcd->cfi, pcd, ep);\n+\t}\n+#endif\n+\n+\tDWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);\n+\n+out:\n+\treturn retval;\n+}\n+\n+/**\n+ * This function is being called from gadget\n+ * to disable PCD endpoint.\n+ */\n+int dwc_otg_pcd_ep_disable(dwc_otg_pcd_t * pcd, void *ep_handle)\n+{\n+\tdwc_otg_pcd_ep_t *ep;\n+\tdwc_irqflags_t flags;\n+\tdwc_otg_dev_dma_desc_t *desc_addr;\n+\tdwc_dma_t dma_desc_addr;\n+\tgdfifocfg_data_t gdfifocfgbase = {.d32 = 0 };\n+\tgdfifocfg_data_t gdfifocfg = {.d32 = 0 };\n+\tfifosize_data_t dptxfsiz = {.d32 = 0 };\n+\tstruct device *dev = dwc_otg_pcd_to_dev(pcd);\n+\n+\tep = get_ep_from_handle(pcd, ep_handle);\n+\n+\tif (!ep || !ep->desc) {\n+\t\tDWC_DEBUGPL(DBG_PCD, \"bad ep address\\n\");\n+\t\treturn -DWC_E_INVALID;\n+\t}\n+\n+\tDWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);\n+\n+\tdwc_otg_request_nuke(ep);\n+\n+\tdwc_otg_ep_deactivate(GET_CORE_IF(pcd), &ep->dwc_ep);\n+\tif (pcd->core_if->core_params->dev_out_nak) {\n+\t\tDWC_TIMER_CANCEL(pcd->core_if->ep_xfer_timer[ep->dwc_ep.num]);\n+\t\tpcd->core_if->ep_xfer_info[ep->dwc_ep.num].state = 0;\n+\t}\n+\tep->desc = NULL;\n+\tep->stopped = 1;\n+\n+\tgdfifocfg.d32 =\n+\t    DWC_READ_REG32(&GET_CORE_IF(pcd)->core_global_regs->gdfifocfg);\n+\tgdfifocfgbase.d32 = gdfifocfg.d32 >> 16;\n+\n+\tif (ep->dwc_ep.is_in) {\n+\t\tif (GET_CORE_IF(pcd)->en_multiple_tx_fifo) {\n+\t\t\t/* Flush the Tx FIFO */\n+\t\t\tdwc_otg_flush_tx_fifo(GET_CORE_IF(pcd),\n+\t\t\t\t\t      ep->dwc_ep.tx_fifo_num);\n+\t\t}\n+\t\trelease_perio_tx_fifo(GET_CORE_IF(pcd), ep->dwc_ep.tx_fifo_num);\n+\t\trelease_tx_fifo(GET_CORE_IF(pcd), ep->dwc_ep.tx_fifo_num);\n+\t\tif (GET_CORE_IF(pcd)->en_multiple_tx_fifo) {\n+\t\t\t/* Decreasing EPinfo Base Addr */\n+\t\t\tdptxfsiz.d32 =\n+\t\t\t    (DWC_READ_REG32\n+\t\t\t     (&GET_CORE_IF(pcd)->\n+\t\t\t\tcore_global_regs->dtxfsiz[ep->dwc_ep.tx_fifo_num-1]) >> 16);\n+\t\t\tgdfifocfg.b.epinfobase = gdfifocfgbase.d32 - dptxfsiz.d32;\n+\t\t\tif (GET_CORE_IF(pcd)->snpsid <= OTG_CORE_REV_2_94a) {\n+\t\t\t\tDWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gdfifocfg,\n+\t\t\t\t\tgdfifocfg.d32);\n+\t\t\t}\n+\t\t}\n+\t}\n+\n+\t/* Free DMA Descriptors */\n+\tif (GET_CORE_IF(pcd)->dma_desc_enable) {\n+\t\tif (ep->dwc_ep.type != UE_ISOCHRONOUS) {\n+\t\t\tdesc_addr = ep->dwc_ep.desc_addr;\n+\t\t\tdma_desc_addr = ep->dwc_ep.dma_desc_addr;\n+\n+\t\t\t/* Cannot call dma_free_coherent() with IRQs disabled */\n+\t\t\tDWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);\n+\t\t\tdwc_otg_ep_free_desc_chain(dev, desc_addr, dma_desc_addr,\n+\t\t\t\t\t\t   MAX_DMA_DESC_CNT);\n+\n+\t\t\tgoto out_unlocked;\n+\t\t}\n+\t}\n+\tDWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);\n+\n+out_unlocked:\n+\tDWC_DEBUGPL(DBG_PCD, \"%d %s disabled\\n\", ep->dwc_ep.num,\n+\t\t    ep->dwc_ep.is_in ? \"IN\" : \"OUT\");\n+\treturn 0;\n+\n+}\n+\n+/******************************************************************************/\n+#ifdef DWC_UTE_PER_IO\n+\n+/**\n+ * Free the request and its extended parts\n+ *\n+ */\n+void dwc_pcd_xiso_ereq_free(dwc_otg_pcd_ep_t * ep, dwc_otg_pcd_request_t * req)\n+{\n+\tDWC_FREE(req->ext_req.per_io_frame_descs);\n+\tDWC_FREE(req);\n+}\n+\n+/**\n+ * Start the next request in the endpoint's queue.\n+ *\n+ */\n+int dwc_otg_pcd_xiso_start_next_request(dwc_otg_pcd_t * pcd,\n+\t\t\t\t\tdwc_otg_pcd_ep_t * ep)\n+{\n+\tint i;\n+\tdwc_otg_pcd_request_t *req = NULL;\n+\tdwc_ep_t *dwcep = NULL;\n+\tstruct dwc_iso_xreq_port *ereq = NULL;\n+\tstruct dwc_iso_pkt_desc_port *ddesc_iso;\n+\tuint16_t nat;\n+\tdepctl_data_t diepctl;\n+\n+\tdwcep = &ep->dwc_ep;\n+\n+\tif (dwcep->xiso_active_xfers > 0) {\n+#if 0\t//Disable this to decrease s/w overhead that is crucial for Isoc transfers\n+\t\tDWC_WARN(\"There are currently active transfers for EP%d \\\n+\t\t\t\t(active=%d; queued=%d)\", dwcep->num, dwcep->xiso_active_xfers,\n+\t\t\t\tdwcep->xiso_queued_xfers);\n+#endif\n+\t\treturn 0;\n+\t}\n+\n+\tnat = UGETW(ep->desc->wMaxPacketSize);\n+\tnat = (nat >> 11) & 0x03;\n+\n+\tif (!DWC_CIRCLEQ_EMPTY(&ep->queue)) {\n+\t\treq = DWC_CIRCLEQ_FIRST(&ep->queue);\n+\t\tereq = &req->ext_req;\n+\t\tep->stopped = 0;\n+\n+\t\t/* Get the frame number */\n+\t\tdwcep->xiso_frame_num =\n+\t\t    dwc_otg_get_frame_number(GET_CORE_IF(pcd));\n+\t\tDWC_DEBUG(\"FRM_NUM=%d\", dwcep->xiso_frame_num);\n+\n+\t\tddesc_iso = ereq->per_io_frame_descs;\n+\n+\t\tif (dwcep->is_in) {\n+\t\t\t/* Setup DMA Descriptor chain for IN Isoc request */\n+\t\t\tfor (i = 0; i < ereq->pio_pkt_count; i++) {\n+\t\t\t\t//if ((i % (nat + 1)) == 0)\n+\t\t\t\tif ( i > 0 )\n+\t\t\t\t\tdwcep->xiso_frame_num =\n+\t\t\t\t\t    (dwcep->xiso_bInterval +\n+\t\t\t\t\t\t\t\t\t\tdwcep->xiso_frame_num) & 0x3FFF;\n+\t\t\t\tdwcep->desc_addr[i].buf =\n+\t\t\t\t    req->dma + ddesc_iso[i].offset;\n+\t\t\t\tdwcep->desc_addr[i].status.b_iso_in.txbytes =\n+\t\t\t\t    ddesc_iso[i].length;\n+\t\t\t\tdwcep->desc_addr[i].status.b_iso_in.framenum =\n+\t\t\t\t    dwcep->xiso_frame_num;\n+\t\t\t\tdwcep->desc_addr[i].status.b_iso_in.bs =\n+\t\t\t\t    BS_HOST_READY;\n+\t\t\t\tdwcep->desc_addr[i].status.b_iso_in.txsts = 0;\n+\t\t\t\tdwcep->desc_addr[i].status.b_iso_in.sp =\n+\t\t\t\t    (ddesc_iso[i].length %\n+\t\t\t\t     dwcep->maxpacket) ? 1 : 0;\n+\t\t\t\tdwcep->desc_addr[i].status.b_iso_in.ioc = 0;\n+\t\t\t\tdwcep->desc_addr[i].status.b_iso_in.pid = nat + 1;\n+\t\t\t\tdwcep->desc_addr[i].status.b_iso_in.l = 0;\n+\n+\t\t\t\t/* Process the last descriptor */\n+\t\t\t\tif (i == ereq->pio_pkt_count - 1) {\n+\t\t\t\t\tdwcep->desc_addr[i].status.b_iso_in.ioc = 1;\n+\t\t\t\t\tdwcep->desc_addr[i].status.b_iso_in.l = 1;\n+\t\t\t\t}\n+\t\t\t}\n+\n+\t\t\t/* Setup and start the transfer for this endpoint */\n+\t\t\tdwcep->xiso_active_xfers++;\n+\t\t\tDWC_WRITE_REG32(&GET_CORE_IF(pcd)->dev_if->\n+\t\t\t\t\tin_ep_regs[dwcep->num]->diepdma,\n+\t\t\t\t\tdwcep->dma_desc_addr);\n+\t\t\tdiepctl.d32 = 0;\n+\t\t\tdiepctl.b.epena = 1;\n+\t\t\tdiepctl.b.cnak = 1;\n+\t\t\tDWC_MODIFY_REG32(&GET_CORE_IF(pcd)->dev_if->\n+\t\t\t\t\t in_ep_regs[dwcep->num]->diepctl, 0,\n+\t\t\t\t\t diepctl.d32);\n+\t\t} else {\n+\t\t\t/* Setup DMA Descriptor chain for OUT Isoc request */\n+\t\t\tfor (i = 0; i < ereq->pio_pkt_count; i++) {\n+\t\t\t\t//if ((i % (nat + 1)) == 0)\n+\t\t\t\tdwcep->xiso_frame_num = (dwcep->xiso_bInterval +\n+\t\t\t\t\t\t\t\t\t\tdwcep->xiso_frame_num) & 0x3FFF;\n+\t\t\t\tdwcep->desc_addr[i].buf =\n+\t\t\t\t    req->dma + ddesc_iso[i].offset;\n+\t\t\t\tdwcep->desc_addr[i].status.b_iso_out.rxbytes =\n+\t\t\t\t    ddesc_iso[i].length;\n+\t\t\t\tdwcep->desc_addr[i].status.b_iso_out.framenum =\n+\t\t\t\t    dwcep->xiso_frame_num;\n+\t\t\t\tdwcep->desc_addr[i].status.b_iso_out.bs =\n+\t\t\t\t    BS_HOST_READY;\n+\t\t\t\tdwcep->desc_addr[i].status.b_iso_out.rxsts = 0;\n+\t\t\t\tdwcep->desc_addr[i].status.b_iso_out.sp =\n+\t\t\t\t    (ddesc_iso[i].length %\n+\t\t\t\t     dwcep->maxpacket) ? 1 : 0;\n+\t\t\t\tdwcep->desc_addr[i].status.b_iso_out.ioc = 0;\n+\t\t\t\tdwcep->desc_addr[i].status.b_iso_out.pid = nat + 1;\n+\t\t\t\tdwcep->desc_addr[i].status.b_iso_out.l = 0;\n+\n+\t\t\t\t/* Process the last descriptor */\n+\t\t\t\tif (i == ereq->pio_pkt_count - 1) {\n+\t\t\t\t\tdwcep->desc_addr[i].status.b_iso_out.ioc = 1;\n+\t\t\t\t\tdwcep->desc_addr[i].status.b_iso_out.l = 1;\n+\t\t\t\t}\n+\t\t\t}\n+\n+\t\t\t/* Setup and start the transfer for this endpoint */\n+\t\t\tdwcep->xiso_active_xfers++;\n+\t\t\tDWC_WRITE_REG32(&GET_CORE_IF(pcd)->\n+\t\t\t\t\tdev_if->out_ep_regs[dwcep->num]->\n+\t\t\t\t\tdoepdma, dwcep->dma_desc_addr);\n+\t\t\tdiepctl.d32 = 0;\n+\t\t\tdiepctl.b.epena = 1;\n+\t\t\tdiepctl.b.cnak = 1;\n+\t\t\tDWC_MODIFY_REG32(&GET_CORE_IF(pcd)->\n+\t\t\t\t\t dev_if->out_ep_regs[dwcep->num]->\n+\t\t\t\t\t doepctl, 0, diepctl.d32);\n+\t\t}\n+\n+\t} else {\n+\t\tep->stopped = 1;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+/**\n+ *\t- Remove the request from the queue\n+ */\n+void complete_xiso_ep(dwc_otg_pcd_ep_t * ep)\n+{\n+\tdwc_otg_pcd_request_t *req = NULL;\n+\tstruct dwc_iso_xreq_port *ereq = NULL;\n+\tstruct dwc_iso_pkt_desc_port *ddesc_iso = NULL;\n+\tdwc_ep_t *dwcep = NULL;\n+\tint i;\n+\n+\t//DWC_DEBUG();\n+\tdwcep = &ep->dwc_ep;\n+\n+\t/* Get the first pending request from the queue */\n+\tif (!DWC_CIRCLEQ_EMPTY(&ep->queue)) {\n+\t\treq = DWC_CIRCLEQ_FIRST(&ep->queue);\n+\t\tif (!req) {\n+\t\t\tDWC_PRINTF(\"complete_ep 0x%p, req = NULL!\\n\", ep);\n+\t\t\treturn;\n+\t\t}\n+\t\tdwcep->xiso_active_xfers--;\n+\t\tdwcep->xiso_queued_xfers--;\n+\t\t/* Remove this request from the queue */\n+\t\tDWC_CIRCLEQ_REMOVE_INIT(&ep->queue, req, queue_entry);\n+\t} else {\n+\t\tDWC_PRINTF(\"complete_ep 0x%p, ep->queue empty!\\n\", ep);\n+\t\treturn;\n+\t}\n+\n+\tep->stopped = 1;\n+\tereq = &req->ext_req;\n+\tddesc_iso = ereq->per_io_frame_descs;\n+\n+\tif (dwcep->xiso_active_xfers < 0) {\n+\t\tDWC_WARN(\"EP#%d (xiso_active_xfers=%d)\", dwcep->num,\n+\t\t\t dwcep->xiso_active_xfers);\n+\t}\n+\n+\t/* Fill the Isoc descs of portable extended req from dma descriptors */\n+\tfor (i = 0; i < ereq->pio_pkt_count; i++) {\n+\t\tif (dwcep->is_in) {\t/* IN endpoints */\n+\t\t\tddesc_iso[i].actual_length = ddesc_iso[i].length -\n+\t\t\t    dwcep->desc_addr[i].status.b_iso_in.txbytes;\n+\t\t\tddesc_iso[i].status =\n+\t\t\t    dwcep->desc_addr[i].status.b_iso_in.txsts;\n+\t\t} else {\t/* OUT endpoints */\n+\t\t\tddesc_iso[i].actual_length = ddesc_iso[i].length -\n+\t\t\t    dwcep->desc_addr[i].status.b_iso_out.rxbytes;\n+\t\t\tddesc_iso[i].status =\n+\t\t\t    dwcep->desc_addr[i].status.b_iso_out.rxsts;\n+\t\t}\n+\t}\n+\n+\tDWC_SPINUNLOCK(ep->pcd->lock);\n+\n+\t/* Call the completion function in the non-portable logic */\n+\tep->pcd->fops->xisoc_complete(ep->pcd, ep->priv, req->priv, 0,\n+\t\t\t\t      &req->ext_req);\n+\n+\tDWC_SPINLOCK(ep->pcd->lock);\n+\n+\t/* Free the request - specific freeing needed for extended request object */\n+\tdwc_pcd_xiso_ereq_free(ep, req);\n+\n+\t/* Start the next request */\n+\tdwc_otg_pcd_xiso_start_next_request(ep->pcd, ep);\n+\n+\treturn;\n+}\n+\n+/**\n+ * Create and initialize the Isoc pkt descriptors of the extended request.\n+ *\n+ */\n+static int dwc_otg_pcd_xiso_create_pkt_descs(dwc_otg_pcd_request_t * req,\n+\t\t\t\t\t     void *ereq_nonport,\n+\t\t\t\t\t     int atomic_alloc)\n+{\n+\tstruct dwc_iso_xreq_port *ereq = NULL;\n+\tstruct dwc_iso_xreq_port *req_mapped = NULL;\n+\tstruct dwc_iso_pkt_desc_port *ipds = NULL;\t/* To be created in this function */\n+\tuint32_t pkt_count;\n+\tint i;\n+\n+\tereq = &req->ext_req;\n+\treq_mapped = (struct dwc_iso_xreq_port *)ereq_nonport;\n+\tpkt_count = req_mapped->pio_pkt_count;\n+\n+\t/* Create the isoc descs */\n+\tif (atomic_alloc) {\n+\t\tipds = DWC_ALLOC_ATOMIC(sizeof(*ipds) * pkt_count);\n+\t} else {\n+\t\tipds = DWC_ALLOC(sizeof(*ipds) * pkt_count);\n+\t}\n+\n+\tif (!ipds) {\n+\t\tDWC_ERROR(\"Failed to allocate isoc descriptors\");\n+\t\treturn -DWC_E_NO_MEMORY;\n+\t}\n+\n+\t/* Initialize the extended request fields */\n+\tereq->per_io_frame_descs = ipds;\n+\tereq->error_count = 0;\n+\tereq->pio_alloc_pkt_count = pkt_count;\n+\tereq->pio_pkt_count = pkt_count;\n+\tereq->tr_sub_flags = req_mapped->tr_sub_flags;\n+\n+\t/* Init the Isoc descriptors */\n+\tfor (i = 0; i < pkt_count; i++) {\n+\t\tipds[i].length = req_mapped->per_io_frame_descs[i].length;\n+\t\tipds[i].offset = req_mapped->per_io_frame_descs[i].offset;\n+\t\tipds[i].status = req_mapped->per_io_frame_descs[i].status;\t/* 0 */\n+\t\tipds[i].actual_length =\n+\t\t    req_mapped->per_io_frame_descs[i].actual_length;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static void prn_ext_request(struct dwc_iso_xreq_port *ereq)\n+{\n+\tstruct dwc_iso_pkt_desc_port *xfd = NULL;\n+\tint i;\n+\n+\tDWC_DEBUG(\"per_io_frame_descs=%p\", ereq->per_io_frame_descs);\n+\tDWC_DEBUG(\"tr_sub_flags=%d\", ereq->tr_sub_flags);\n+\tDWC_DEBUG(\"error_count=%d\", ereq->error_count);\n+\tDWC_DEBUG(\"pio_alloc_pkt_count=%d\", ereq->pio_alloc_pkt_count);\n+\tDWC_DEBUG(\"pio_pkt_count=%d\", ereq->pio_pkt_count);\n+\tDWC_DEBUG(\"res=%d\", ereq->res);\n+\n+\tfor (i = 0; i < ereq->pio_pkt_count; i++) {\n+\t\txfd = &ereq->per_io_frame_descs[0];\n+\t\tDWC_DEBUG(\"FD #%d\", i);\n+\n+\t\tDWC_DEBUG(\"xfd->actual_length=%d\", xfd->actual_length);\n+\t\tDWC_DEBUG(\"xfd->length=%d\", xfd->length);\n+\t\tDWC_DEBUG(\"xfd->offset=%d\", xfd->offset);\n+\t\tDWC_DEBUG(\"xfd->status=%d\", xfd->status);\n+\t}\n+}\n+\n+/**\n+ *\n+ */\n+int dwc_otg_pcd_xiso_ep_queue(dwc_otg_pcd_t * pcd, void *ep_handle,\n+\t\t\t      uint8_t * buf, dwc_dma_t dma_buf, uint32_t buflen,\n+\t\t\t      int zero, void *req_handle, int atomic_alloc,\n+\t\t\t      void *ereq_nonport)\n+{\n+\tdwc_otg_pcd_request_t *req = NULL;\n+\tdwc_otg_pcd_ep_t *ep;\n+\tdwc_irqflags_t flags;\n+\tint res;\n+\n+\tep = get_ep_from_handle(pcd, ep_handle);\n+\tif (!ep) {\n+\t\tDWC_WARN(\"bad ep\\n\");\n+\t\treturn -DWC_E_INVALID;\n+\t}\n+\n+\t/* We support this extension only for DDMA mode */\n+\tif (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC)\n+\t\tif (!GET_CORE_IF(pcd)->dma_desc_enable)\n+\t\t\treturn -DWC_E_INVALID;\n+\n+\t/* Create a dwc_otg_pcd_request_t object */\n+\tif (atomic_alloc) {\n+\t\treq = DWC_ALLOC_ATOMIC(sizeof(*req));\n+\t} else {\n+\t\treq = DWC_ALLOC(sizeof(*req));\n+\t}\n+\n+\tif (!req) {\n+\t\treturn -DWC_E_NO_MEMORY;\n+\t}\n+\n+\t/* Create the Isoc descs for this request which shall be the exact match\n+\t * of the structure sent to us from the non-portable logic */\n+\tres =\n+\t    dwc_otg_pcd_xiso_create_pkt_descs(req, ereq_nonport, atomic_alloc);\n+\tif (res) {\n+\t\tDWC_WARN(\"Failed to init the Isoc descriptors\");\n+\t\tDWC_FREE(req);\n+\t\treturn res;\n+\t}\n+\n+\tDWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);\n+\n+\tDWC_CIRCLEQ_INIT_ENTRY(req, queue_entry);\n+\treq->buf = buf;\n+\treq->dma = dma_buf;\n+\treq->length = buflen;\n+\treq->sent_zlp = zero;\n+\treq->priv = req_handle;\n+\n+\t//DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);\n+\tep->dwc_ep.dma_addr = dma_buf;\n+\tep->dwc_ep.start_xfer_buff = buf;\n+\tep->dwc_ep.xfer_buff = buf;\n+\tep->dwc_ep.xfer_len = 0;\n+\tep->dwc_ep.xfer_count = 0;\n+\tep->dwc_ep.sent_zlp = 0;\n+\tep->dwc_ep.total_len = buflen;\n+\n+\t/* Add this request to the tail */\n+\tDWC_CIRCLEQ_INSERT_TAIL(&ep->queue, req, queue_entry);\n+\tep->dwc_ep.xiso_queued_xfers++;\n+\n+//DWC_DEBUG(\"CP_0\");\n+//DWC_DEBUG(\"req->ext_req.tr_sub_flags=%d\", req->ext_req.tr_sub_flags);\n+//prn_ext_request((struct dwc_iso_xreq_port *) ereq_nonport);\n+//prn_ext_request(&req->ext_req);\n+\n+\t//DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);\n+\n+\t/* If the req->status == ASAP  then check if there is any active transfer\n+\t * for this endpoint. If no active transfers, then get the first entry\n+\t * from the queue and start that transfer\n+\t */\n+\tif (req->ext_req.tr_sub_flags == DWC_EREQ_TF_ASAP) {\n+\t\tres = dwc_otg_pcd_xiso_start_next_request(pcd, ep);\n+\t\tif (res) {\n+\t\t\tDWC_WARN(\"Failed to start the next Isoc transfer\");\n+\t\t\tDWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);\n+\t\t\tDWC_FREE(req);\n+\t\t\treturn res;\n+\t\t}\n+\t}\n+\n+\tDWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);\n+\treturn 0;\n+}\n+\n+#endif\n+/* END ifdef DWC_UTE_PER_IO ***************************************************/\n+int dwc_otg_pcd_ep_queue(dwc_otg_pcd_t * pcd, void *ep_handle,\n+\t\t\t uint8_t * buf, dwc_dma_t dma_buf, uint32_t buflen,\n+\t\t\t int zero, void *req_handle, int atomic_alloc)\n+{\n+\tstruct device *dev = dwc_otg_pcd_to_dev(pcd);\n+\tdwc_irqflags_t flags;\n+\tdwc_otg_pcd_request_t *req;\n+\tdwc_otg_pcd_ep_t *ep;\n+\tuint32_t max_transfer;\n+\n+\tep = get_ep_from_handle(pcd, ep_handle);\n+\tif (!ep || (!ep->desc && ep->dwc_ep.num != 0)) {\n+\t\tDWC_WARN(\"bad ep\\n\");\n+\t\treturn -DWC_E_INVALID;\n+\t}\n+\n+\tif (atomic_alloc) {\n+\t\treq = DWC_ALLOC_ATOMIC(sizeof(*req));\n+\t} else {\n+\t\treq = DWC_ALLOC(sizeof(*req));\n+\t}\n+\n+\tif (!req) {\n+\t\treturn -DWC_E_NO_MEMORY;\n+\t}\n+\tDWC_CIRCLEQ_INIT_ENTRY(req, queue_entry);\n+\tif (!GET_CORE_IF(pcd)->core_params->opt) {\n+\t\tif (ep->dwc_ep.num != 0) {\n+\t\t\tDWC_ERROR(\"queue req %p, len %d buf %p\\n\",\n+\t\t\t\t  req_handle, buflen, buf);\n+\t\t}\n+\t}\n+\n+\treq->buf = buf;\n+\treq->dma = dma_buf;\n+\treq->length = buflen;\n+\treq->sent_zlp = zero;\n+\treq->priv = req_handle;\n+\treq->dw_align_buf = NULL;\n+\tif ((dma_buf & 0x3) && GET_CORE_IF(pcd)->dma_enable\n+\t\t\t&& !GET_CORE_IF(pcd)->dma_desc_enable)\n+\t\treq->dw_align_buf = DWC_DMA_ALLOC(dev, buflen,\n+\t\t\t\t &req->dw_align_buf_dma);\n+\tDWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);\n+\n+\t/*\n+\t * After adding request to the queue for IN ISOC wait for In Token Received\n+\t * when TX FIFO is empty interrupt and for OUT ISOC wait for OUT Token\n+\t * Received when EP is disabled interrupt to obtain starting microframe\n+\t * (odd/even) start transfer\n+\t */\n+\tif (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) {\n+\t\tif (req != 0) {\n+\t\t\tdepctl_data_t depctl = {.d32 =\n+\t\t\t\t    DWC_READ_REG32(&pcd->core_if->dev_if->\n+\t\t\t\t\t\t   in_ep_regs[ep->dwc_ep.num]->\n+\t\t\t\t\t\t   diepctl) };\n+\t\t\t++pcd->request_pending;\n+\n+\t\t\tDWC_CIRCLEQ_INSERT_TAIL(&ep->queue, req, queue_entry);\n+\t\t\tif (ep->dwc_ep.is_in) {\n+\t\t\t\tdepctl.b.cnak = 1;\n+\t\t\t\tDWC_WRITE_REG32(&pcd->core_if->dev_if->\n+\t\t\t\t\t\tin_ep_regs[ep->dwc_ep.num]->\n+\t\t\t\t\t\tdiepctl, depctl.d32);\n+\t\t\t}\n+\n+\t\t\tDWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);\n+\t\t}\n+\t\treturn 0;\n+\t}\n+\n+\t/*\n+\t * For EP0 IN without premature status, zlp is required?\n+\t */\n+\tif (ep->dwc_ep.num == 0 && ep->dwc_ep.is_in) {\n+\t\tDWC_DEBUGPL(DBG_PCDV, \"%d-OUT ZLP\\n\", ep->dwc_ep.num);\n+\t\t//_req->zero = 1;\n+\t}\n+\n+\t/* Start the transfer */\n+\tif (DWC_CIRCLEQ_EMPTY(&ep->queue) && !ep->stopped) {\n+\t\t/* EP0 Transfer? */\n+\t\tif (ep->dwc_ep.num == 0) {\n+\t\t\tswitch (pcd->ep0state) {\n+\t\t\tcase EP0_IN_DATA_PHASE:\n+\t\t\t\tDWC_DEBUGPL(DBG_PCD,\n+\t\t\t\t\t    \"%s ep0: EP0_IN_DATA_PHASE\\n\",\n+\t\t\t\t\t    __func__);\n+\t\t\t\tbreak;\n+\n+\t\t\tcase EP0_OUT_DATA_PHASE:\n+\t\t\t\tDWC_DEBUGPL(DBG_PCD,\n+\t\t\t\t\t    \"%s ep0: EP0_OUT_DATA_PHASE\\n\",\n+\t\t\t\t\t    __func__);\n+\t\t\t\tif (pcd->request_config) {\n+\t\t\t\t\t/* Complete STATUS PHASE */\n+\t\t\t\t\tep->dwc_ep.is_in = 1;\n+\t\t\t\t\tpcd->ep0state = EP0_IN_STATUS_PHASE;\n+\t\t\t\t}\n+\t\t\t\tbreak;\n+\n+\t\t\tcase EP0_IN_STATUS_PHASE:\n+\t\t\t\tDWC_DEBUGPL(DBG_PCD,\n+\t\t\t\t\t    \"%s ep0: EP0_IN_STATUS_PHASE\\n\",\n+\t\t\t\t\t    __func__);\n+\t\t\t\tbreak;\n+\n+\t\t\tdefault:\n+\t\t\t\tDWC_DEBUGPL(DBG_ANY, \"ep0: odd state %d\\n\",\n+\t\t\t\t\t    pcd->ep0state);\n+\t\t\t\tDWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);\n+\t\t\t\treturn -DWC_E_SHUTDOWN;\n+\t\t\t}\n+\n+\t\t\tep->dwc_ep.dma_addr = dma_buf;\n+\t\t\tep->dwc_ep.start_xfer_buff = buf;\n+\t\t\tep->dwc_ep.xfer_buff = buf;\n+\t\t\tep->dwc_ep.xfer_len = buflen;\n+\t\t\tep->dwc_ep.xfer_count = 0;\n+\t\t\tep->dwc_ep.sent_zlp = 0;\n+\t\t\tep->dwc_ep.total_len = ep->dwc_ep.xfer_len;\n+\n+\t\t\tif (zero) {\n+\t\t\t\tif ((ep->dwc_ep.xfer_len %\n+\t\t\t\t     ep->dwc_ep.maxpacket == 0)\n+\t\t\t\t    && (ep->dwc_ep.xfer_len != 0)) {\n+\t\t\t\t\tep->dwc_ep.sent_zlp = 1;\n+\t\t\t\t}\n+\n+\t\t\t}\n+\n+\t\t\tdwc_otg_ep0_start_transfer(GET_CORE_IF(pcd),\n+\t\t\t\t\t\t   &ep->dwc_ep);\n+\t\t}\t\t// non-ep0 endpoints\n+\t\telse {\n+#ifdef DWC_UTE_CFI\n+\t\t\tif (ep->dwc_ep.buff_mode != BM_STANDARD) {\n+\t\t\t\t/* store the request length */\n+\t\t\t\tep->dwc_ep.cfi_req_len = buflen;\n+\t\t\t\tpcd->cfi->ops.build_descriptors(pcd->cfi, pcd,\n+\t\t\t\t\t\t\t\tep, req);\n+\t\t\t} else {\n+#endif\n+\t\t\t\tmax_transfer =\n+\t\t\t\t    GET_CORE_IF(ep->pcd)->core_params->\n+\t\t\t\t    max_transfer_size;\n+\n+\t\t\t\t/* Setup and start the Transfer */\n+\t\t\t\tif (req->dw_align_buf){\n+\t\t\t\t\tif (ep->dwc_ep.is_in)\n+\t\t\t\t\t\tdwc_memcpy(req->dw_align_buf,\n+\t\t\t\t\t\t\t   buf, buflen);\n+\t\t\t\t\tep->dwc_ep.dma_addr =\n+\t\t\t\t\t    req->dw_align_buf_dma;\n+\t\t\t\t\tep->dwc_ep.start_xfer_buff =\n+\t\t\t\t\t    req->dw_align_buf;\n+\t\t\t\t\tep->dwc_ep.xfer_buff =\n+\t\t\t\t\t    req->dw_align_buf;\n+\t\t\t\t} else {\n+\t\t\t\t\tep->dwc_ep.dma_addr = dma_buf;\n+\t\t\t\t\tep->dwc_ep.start_xfer_buff = buf;\n+                                        ep->dwc_ep.xfer_buff = buf;\n+\t\t\t\t}\n+\t\t\t\tep->dwc_ep.xfer_len = 0;\n+\t\t\t\tep->dwc_ep.xfer_count = 0;\n+\t\t\t\tep->dwc_ep.sent_zlp = 0;\n+\t\t\t\tep->dwc_ep.total_len = buflen;\n+\n+\t\t\t\tep->dwc_ep.maxxfer = max_transfer;\n+\t\t\t\tif (GET_CORE_IF(pcd)->dma_desc_enable) {\n+\t\t\t\t\tuint32_t out_max_xfer =\n+\t\t\t\t\t    DDMA_MAX_TRANSFER_SIZE -\n+\t\t\t\t\t    (DDMA_MAX_TRANSFER_SIZE % 4);\n+\t\t\t\t\tif (ep->dwc_ep.is_in) {\n+\t\t\t\t\t\tif (ep->dwc_ep.maxxfer >\n+\t\t\t\t\t\t    DDMA_MAX_TRANSFER_SIZE) {\n+\t\t\t\t\t\t\tep->dwc_ep.maxxfer =\n+\t\t\t\t\t\t\t    DDMA_MAX_TRANSFER_SIZE;\n+\t\t\t\t\t\t}\n+\t\t\t\t\t} else {\n+\t\t\t\t\t\tif (ep->dwc_ep.maxxfer >\n+\t\t\t\t\t\t    out_max_xfer) {\n+\t\t\t\t\t\t\tep->dwc_ep.maxxfer =\n+\t\t\t\t\t\t\t    out_max_xfer;\n+\t\t\t\t\t\t}\n+\t\t\t\t\t}\n+\t\t\t\t}\n+\t\t\t\tif (ep->dwc_ep.maxxfer < ep->dwc_ep.total_len) {\n+\t\t\t\t\tep->dwc_ep.maxxfer -=\n+\t\t\t\t\t    (ep->dwc_ep.maxxfer %\n+\t\t\t\t\t     ep->dwc_ep.maxpacket);\n+\t\t\t\t}\n+\n+\t\t\t\tif (zero) {\n+\t\t\t\t\tif ((ep->dwc_ep.total_len %\n+\t\t\t\t\t     ep->dwc_ep.maxpacket == 0)\n+\t\t\t\t\t    && (ep->dwc_ep.total_len != 0)) {\n+\t\t\t\t\t\tep->dwc_ep.sent_zlp = 1;\n+\t\t\t\t\t}\n+\t\t\t\t}\n+#ifdef DWC_UTE_CFI\n+\t\t\t}\n+#endif\n+\t\t\tdwc_otg_ep_start_transfer(GET_CORE_IF(pcd),\n+\t\t\t\t\t\t  &ep->dwc_ep);\n+\t\t}\n+\t}\n+\n+\tif (req != 0) {\n+\t\t++pcd->request_pending;\n+\t\tDWC_CIRCLEQ_INSERT_TAIL(&ep->queue, req, queue_entry);\n+\t\tif (ep->dwc_ep.is_in && ep->stopped\n+\t\t    && !(GET_CORE_IF(pcd)->dma_enable)) {\n+\t\t\t/** @todo NGS Create a function for this. */\n+\t\t\tdiepmsk_data_t diepmsk = {.d32 = 0 };\n+\t\t\tdiepmsk.b.intktxfemp = 1;\n+\t\t\tif (GET_CORE_IF(pcd)->multiproc_int_enable) {\n+\t\t\t\tDWC_MODIFY_REG32(&GET_CORE_IF(pcd)->\n+\t\t\t\t\t\t dev_if->dev_global_regs->diepeachintmsk\n+\t\t\t\t\t\t [ep->dwc_ep.num], 0,\n+\t\t\t\t\t\t diepmsk.d32);\n+\t\t\t} else {\n+\t\t\t\tDWC_MODIFY_REG32(&GET_CORE_IF(pcd)->\n+\t\t\t\t\t\t dev_if->dev_global_regs->\n+\t\t\t\t\t\t diepmsk, 0, diepmsk.d32);\n+\t\t\t}\n+\n+\t\t}\n+\t}\n+\tDWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);\n+\n+\treturn 0;\n+}\n+\n+int dwc_otg_pcd_ep_dequeue(dwc_otg_pcd_t * pcd, void *ep_handle,\n+\t\t\t   void *req_handle)\n+{\n+\tdwc_irqflags_t flags;\n+\tdwc_otg_pcd_request_t *req;\n+\tdwc_otg_pcd_ep_t *ep;\n+\n+\tep = get_ep_from_handle(pcd, ep_handle);\n+\tif (!ep || (!ep->desc && ep->dwc_ep.num != 0)) {\n+\t\tDWC_WARN(\"bad argument\\n\");\n+\t\treturn -DWC_E_INVALID;\n+\t}\n+\n+\tDWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);\n+\n+\t/* make sure it's actually queued on this endpoint */\n+\tDWC_CIRCLEQ_FOREACH(req, &ep->queue, queue_entry) {\n+\t\tif (req->priv == (void *)req_handle) {\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\n+\tif (req->priv != (void *)req_handle) {\n+\t\tDWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);\n+\t\treturn -DWC_E_INVALID;\n+\t}\n+\n+\tif (!DWC_CIRCLEQ_EMPTY_ENTRY(req, queue_entry)) {\n+\t\tdwc_otg_request_done(ep, req, -DWC_E_RESTART);\n+\t} else {\n+\t\treq = NULL;\n+\t}\n+\n+\tDWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);\n+\n+\treturn req ? 0 : -DWC_E_SHUTDOWN;\n+\n+}\n+\n+/**\n+ * dwc_otg_pcd_ep_wedge - sets the halt feature and ignores clear requests\n+ *\n+ * Use this to stall an endpoint and ignore CLEAR_FEATURE(HALT_ENDPOINT)\n+ * requests. If the gadget driver clears the halt status, it will\n+ * automatically unwedge the endpoint.\n+ *\n+ * Returns zero on success, else negative DWC error code.\n+ */\n+int dwc_otg_pcd_ep_wedge(dwc_otg_pcd_t * pcd, void *ep_handle)\n+{\n+\tdwc_otg_pcd_ep_t *ep;\n+\tdwc_irqflags_t flags;\n+\tint retval = 0;\n+\n+\tep = get_ep_from_handle(pcd, ep_handle);\n+\n+\tif ((!ep->desc && ep != &pcd->ep0) ||\n+\t    (ep->desc && (ep->desc->bmAttributes == UE_ISOCHRONOUS))) {\n+\t\tDWC_WARN(\"%s, bad ep\\n\", __func__);\n+\t\treturn -DWC_E_INVALID;\n+\t}\n+\n+\tDWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);\n+\tif (!DWC_CIRCLEQ_EMPTY(&ep->queue)) {\n+\t\tDWC_WARN(\"%d %s XFer In process\\n\", ep->dwc_ep.num,\n+\t\t\t ep->dwc_ep.is_in ? \"IN\" : \"OUT\");\n+\t\tretval = -DWC_E_AGAIN;\n+\t} else {\n+                /* This code needs to be reviewed */\n+\t\tif (ep->dwc_ep.is_in == 1 && GET_CORE_IF(pcd)->dma_desc_enable) {\n+\t\t\tdtxfsts_data_t txstatus;\n+\t\t\tfifosize_data_t txfifosize;\n+\n+\t\t\ttxfifosize.d32 =\n+\t\t\t    DWC_READ_REG32(&GET_CORE_IF(pcd)->\n+\t\t\t\t\t   core_global_regs->dtxfsiz[ep->dwc_ep.\n+\t\t\t\t\t\t\t\t     tx_fifo_num]);\n+\t\t\ttxstatus.d32 =\n+\t\t\t    DWC_READ_REG32(&GET_CORE_IF(pcd)->\n+\t\t\t\t\t   dev_if->in_ep_regs[ep->dwc_ep.num]->\n+\t\t\t\t\t   dtxfsts);\n+\n+\t\t\tif (txstatus.b.txfspcavail < txfifosize.b.depth) {\n+\t\t\t\tDWC_WARN(\"%s() Data In Tx Fifo\\n\", __func__);\n+\t\t\t\tretval = -DWC_E_AGAIN;\n+\t\t\t} else {\n+\t\t\t\tif (ep->dwc_ep.num == 0) {\n+\t\t\t\t\tpcd->ep0state = EP0_STALL;\n+\t\t\t\t}\n+\n+\t\t\t\tep->stopped = 1;\n+\t\t\t\tdwc_otg_ep_set_stall(GET_CORE_IF(pcd),\n+\t\t\t\t\t\t     &ep->dwc_ep);\n+\t\t\t}\n+\t\t} else {\n+\t\t\tif (ep->dwc_ep.num == 0) {\n+\t\t\t\tpcd->ep0state = EP0_STALL;\n+\t\t\t}\n+\n+\t\t\tep->stopped = 1;\n+\t\t\tdwc_otg_ep_set_stall(GET_CORE_IF(pcd), &ep->dwc_ep);\n+\t\t}\n+\t}\n+\n+\tDWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);\n+\n+\treturn retval;\n+}\n+\n+int dwc_otg_pcd_ep_halt(dwc_otg_pcd_t * pcd, void *ep_handle, int value)\n+{\n+\tdwc_otg_pcd_ep_t *ep;\n+\tdwc_irqflags_t flags;\n+\tint retval = 0;\n+\n+\tep = get_ep_from_handle(pcd, ep_handle);\n+\n+\tif (!ep || (!ep->desc && ep != &pcd->ep0) ||\n+\t    (ep->desc && (ep->desc->bmAttributes == UE_ISOCHRONOUS))) {\n+\t\tDWC_WARN(\"%s, bad ep\\n\", __func__);\n+\t\treturn -DWC_E_INVALID;\n+\t}\n+\n+\tDWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);\n+\tif (!DWC_CIRCLEQ_EMPTY(&ep->queue)) {\n+\t\tDWC_WARN(\"%d %s XFer In process\\n\", ep->dwc_ep.num,\n+\t\t\t ep->dwc_ep.is_in ? \"IN\" : \"OUT\");\n+\t\tretval = -DWC_E_AGAIN;\n+\t} else if (value == 0) {\n+\t\tdwc_otg_ep_clear_stall(GET_CORE_IF(pcd), &ep->dwc_ep);\n+\t} else if (value == 1) {\n+\t\tif (ep->dwc_ep.is_in == 1 && GET_CORE_IF(pcd)->dma_desc_enable) {\n+\t\t\tdtxfsts_data_t txstatus;\n+\t\t\tfifosize_data_t txfifosize;\n+\n+\t\t\ttxfifosize.d32 =\n+\t\t\t    DWC_READ_REG32(&GET_CORE_IF(pcd)->core_global_regs->\n+\t\t\t\t\t   dtxfsiz[ep->dwc_ep.tx_fifo_num]);\n+\t\t\ttxstatus.d32 =\n+\t\t\t    DWC_READ_REG32(&GET_CORE_IF(pcd)->dev_if->\n+\t\t\t\t\t   in_ep_regs[ep->dwc_ep.num]->dtxfsts);\n+\n+\t\t\tif (txstatus.b.txfspcavail < txfifosize.b.depth) {\n+\t\t\t\tDWC_WARN(\"%s() Data In Tx Fifo\\n\", __func__);\n+\t\t\t\tretval = -DWC_E_AGAIN;\n+\t\t\t} else {\n+\t\t\t\tif (ep->dwc_ep.num == 0) {\n+\t\t\t\t\tpcd->ep0state = EP0_STALL;\n+\t\t\t\t}\n+\n+\t\t\t\tep->stopped = 1;\n+\t\t\t\tdwc_otg_ep_set_stall(GET_CORE_IF(pcd),\n+\t\t\t\t\t\t     &ep->dwc_ep);\n+\t\t\t}\n+\t\t} else {\n+\t\t\tif (ep->dwc_ep.num == 0) {\n+\t\t\t\tpcd->ep0state = EP0_STALL;\n+\t\t\t}\n+\n+\t\t\tep->stopped = 1;\n+\t\t\tdwc_otg_ep_set_stall(GET_CORE_IF(pcd), &ep->dwc_ep);\n+\t\t}\n+\t} else if (value == 2) {\n+\t\tep->dwc_ep.stall_clear_flag = 0;\n+\t} else if (value == 3) {\n+\t\tep->dwc_ep.stall_clear_flag = 1;\n+\t}\n+\n+\tDWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);\n+\n+\treturn retval;\n+}\n+\n+/**\n+ * This function initiates remote wakeup of the host from suspend state.\n+ */\n+void dwc_otg_pcd_rem_wkup_from_suspend(dwc_otg_pcd_t * pcd, int set)\n+{\n+\tdctl_data_t dctl = { 0 };\n+\tdwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);\n+\tdsts_data_t dsts;\n+\n+\tdsts.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);\n+\tif (!dsts.b.suspsts) {\n+\t\tDWC_WARN(\"Remote wakeup while is not in suspend state\\n\");\n+\t}\n+\t/* Check if DEVICE_REMOTE_WAKEUP feature enabled */\n+\tif (pcd->remote_wakeup_enable) {\n+\t\tif (set) {\n+\n+\t\t\tif (core_if->adp_enable) {\n+\t\t\t\tgpwrdn_data_t gpwrdn;\n+\n+\t\t\t\tdwc_otg_adp_probe_stop(core_if);\n+\n+\t\t\t\t/* Mask SRP detected interrupt from Power Down Logic */\n+\t\t\t\tgpwrdn.d32 = 0;\n+\t\t\t\tgpwrdn.b.srp_det_msk = 1;\n+\t\t\t\tDWC_MODIFY_REG32(&core_if->\n+\t\t\t\t\t\t core_global_regs->gpwrdn,\n+\t\t\t\t\t\t gpwrdn.d32, 0);\n+\n+\t\t\t\t/* Disable Power Down Logic */\n+\t\t\t\tgpwrdn.d32 = 0;\n+\t\t\t\tgpwrdn.b.pmuactv = 1;\n+\t\t\t\tDWC_MODIFY_REG32(&core_if->\n+\t\t\t\t\t\t core_global_regs->gpwrdn,\n+\t\t\t\t\t\t gpwrdn.d32, 0);\n+\n+\t\t\t\t/*\n+\t\t\t\t * Initialize the Core for Device mode.\n+\t\t\t\t */\n+\t\t\t\tcore_if->op_state = B_PERIPHERAL;\n+\t\t\t\tdwc_otg_core_init(core_if);\n+\t\t\t\tdwc_otg_enable_global_interrupts(core_if);\n+\t\t\t\tcil_pcd_start(core_if);\n+\n+\t\t\t\tdwc_otg_initiate_srp(core_if);\n+\t\t\t}\n+\n+\t\t\tdctl.b.rmtwkupsig = 1;\n+\t\t\tDWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->\n+\t\t\t\t\t dctl, 0, dctl.d32);\n+\t\t\tDWC_DEBUGPL(DBG_PCD, \"Set Remote Wakeup\\n\");\n+\n+\t\t\tdwc_mdelay(2);\n+\t\t\tDWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->\n+\t\t\t\t\t dctl, dctl.d32, 0);\n+\t\t\tDWC_DEBUGPL(DBG_PCD, \"Clear Remote Wakeup\\n\");\n+\t\t}\n+\t} else {\n+\t\tDWC_DEBUGPL(DBG_PCD, \"Remote Wakeup is disabled\\n\");\n+\t}\n+}\n+\n+#ifdef CONFIG_USB_DWC_OTG_LPM\n+/**\n+ * This function initiates remote wakeup of the host from L1 sleep state.\n+ */\n+void dwc_otg_pcd_rem_wkup_from_sleep(dwc_otg_pcd_t * pcd, int set)\n+{\n+\tglpmcfg_data_t lpmcfg;\n+\tdwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);\n+\n+\tlpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);\n+\n+\t/* Check if we are in L1 state */\n+\tif (!lpmcfg.b.prt_sleep_sts) {\n+\t\tDWC_DEBUGPL(DBG_PCD, \"Device is not in sleep state\\n\");\n+\t\treturn;\n+\t}\n+\n+\t/* Check if host allows remote wakeup */\n+\tif (!lpmcfg.b.rem_wkup_en) {\n+\t\tDWC_DEBUGPL(DBG_PCD, \"Host does not allow remote wakeup\\n\");\n+\t\treturn;\n+\t}\n+\n+\t/* Check if Resume OK */\n+\tif (!lpmcfg.b.sleep_state_resumeok) {\n+\t\tDWC_DEBUGPL(DBG_PCD, \"Sleep state resume is not OK\\n\");\n+\t\treturn;\n+\t}\n+\n+\tlpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);\n+\tlpmcfg.b.en_utmi_sleep = 0;\n+\tlpmcfg.b.hird_thres &= (~(1 << 4));\n+\tDWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg, lpmcfg.d32);\n+\n+\tif (set) {\n+\t\tdctl_data_t dctl = {.d32 = 0 };\n+\t\tdctl.b.rmtwkupsig = 1;\n+\t\t/* Set RmtWkUpSig bit to start remote wakup signaling.\n+\t\t * Hardware will automatically clear this bit.\n+\t\t */\n+\t\tDWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl,\n+\t\t\t\t 0, dctl.d32);\n+\t\tDWC_DEBUGPL(DBG_PCD, \"Set Remote Wakeup\\n\");\n+\t}\n+\n+}\n+#endif\n+\n+/**\n+ * Performs remote wakeup.\n+ */\n+void dwc_otg_pcd_remote_wakeup(dwc_otg_pcd_t * pcd, int set)\n+{\n+\tdwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);\n+\tdwc_irqflags_t flags;\n+\tif (dwc_otg_is_device_mode(core_if)) {\n+\t\tDWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);\n+#ifdef CONFIG_USB_DWC_OTG_LPM\n+\t\tif (core_if->lx_state == DWC_OTG_L1) {\n+\t\t\tdwc_otg_pcd_rem_wkup_from_sleep(pcd, set);\n+\t\t} else {\n+#endif\n+\t\t\tdwc_otg_pcd_rem_wkup_from_suspend(pcd, set);\n+#ifdef CONFIG_USB_DWC_OTG_LPM\n+\t\t}\n+#endif\n+\t\tDWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);\n+\t}\n+\treturn;\n+}\n+\n+void dwc_otg_pcd_disconnect_us(dwc_otg_pcd_t * pcd, int no_of_usecs)\n+{\n+\tdwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);\n+\tdctl_data_t dctl = { 0 };\n+\n+\tif (dwc_otg_is_device_mode(core_if)) {\n+\t\tdctl.b.sftdiscon = 1;\n+\t\tDWC_PRINTF(\"Soft disconnect for %d useconds\\n\",no_of_usecs);\n+\t\tDWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0, dctl.d32);\n+\t\tdwc_udelay(no_of_usecs);\n+\t\tDWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32,0);\n+\n+\t} else{\n+\t\tDWC_PRINTF(\"NOT SUPPORTED IN HOST MODE\\n\");\n+\t}\n+\treturn;\n+\n+}\n+\n+int dwc_otg_pcd_wakeup(dwc_otg_pcd_t * pcd)\n+{\n+\tdsts_data_t dsts;\n+\tgotgctl_data_t gotgctl;\n+\n+\t/*\n+\t * This function starts the Protocol if no session is in progress. If\n+\t * a session is already in progress, but the device is suspended,\n+\t * remote wakeup signaling is started.\n+\t */\n+\n+\t/* Check if valid session */\n+\tgotgctl.d32 =\n+\t    DWC_READ_REG32(&(GET_CORE_IF(pcd)->core_global_regs->gotgctl));\n+\tif (gotgctl.b.bsesvld) {\n+\t\t/* Check if suspend state */\n+\t\tdsts.d32 =\n+\t\t    DWC_READ_REG32(&\n+\t\t\t\t   (GET_CORE_IF(pcd)->dev_if->\n+\t\t\t\t    dev_global_regs->dsts));\n+\t\tif (dsts.b.suspsts) {\n+\t\t\tdwc_otg_pcd_remote_wakeup(pcd, 1);\n+\t\t}\n+\t} else {\n+\t\tdwc_otg_pcd_initiate_srp(pcd);\n+\t}\n+\n+\treturn 0;\n+\n+}\n+\n+/**\n+ * Start the SRP timer to detect when the SRP does not complete within\n+ * 6 seconds.\n+ *\n+ * @param pcd the pcd structure.\n+ */\n+void dwc_otg_pcd_initiate_srp(dwc_otg_pcd_t * pcd)\n+{\n+\tdwc_irqflags_t flags;\n+\tDWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);\n+\tdwc_otg_initiate_srp(GET_CORE_IF(pcd));\n+\tDWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);\n+}\n+\n+int dwc_otg_pcd_get_frame_number(dwc_otg_pcd_t * pcd)\n+{\n+\treturn dwc_otg_get_frame_number(GET_CORE_IF(pcd));\n+}\n+\n+int dwc_otg_pcd_is_lpm_enabled(dwc_otg_pcd_t * pcd)\n+{\n+\treturn GET_CORE_IF(pcd)->core_params->lpm_enable;\n+}\n+\n+uint32_t get_b_hnp_enable(dwc_otg_pcd_t * pcd)\n+{\n+\treturn pcd->b_hnp_enable;\n+}\n+\n+uint32_t get_a_hnp_support(dwc_otg_pcd_t * pcd)\n+{\n+\treturn pcd->a_hnp_support;\n+}\n+\n+uint32_t get_a_alt_hnp_support(dwc_otg_pcd_t * pcd)\n+{\n+\treturn pcd->a_alt_hnp_support;\n+}\n+\n+int dwc_otg_pcd_get_rmwkup_enable(dwc_otg_pcd_t * pcd)\n+{\n+\treturn pcd->remote_wakeup_enable;\n+}\n+\n+#endif /* DWC_HOST_ONLY */\n--- /dev/null\n+++ b/drivers/usb/host/dwc_otg/dwc_otg_pcd.h\n@@ -0,0 +1,273 @@\n+/* ==========================================================================\n+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd.h $\n+ * $Revision: #48 $\n+ * $Date: 2012/08/10 $\n+ * $Change: 2047372 $\n+ *\n+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,\n+ * \"Software\") is an Unsupported proprietary work of Synopsys, Inc. unless\n+ * otherwise expressly agreed to in writing between Synopsys and you.\n+ *\n+ * The Software IS NOT an item of Licensed Software or Licensed Product under\n+ * any End User Software License Agreement or Agreement for Licensed Product\n+ * with Synopsys or any supplement thereto. You are permitted to use and\n+ * redistribute this Software in source and binary forms, with or without\n+ * modification, provided that redistributions of source code must retain this\n+ * notice. You may not view, use, disclose, copy or distribute this file or\n+ * any information contained herein except pursuant to this license grant from\n+ * Synopsys. If you do not agree with this notice, including the disclaimer\n+ * below, then you are not authorized to use the Software.\n+ *\n+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN \"AS IS\" BASIS\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,\n+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH\n+ * DAMAGE.\n+ * ========================================================================== */\n+#ifndef DWC_HOST_ONLY\n+#if !defined(__DWC_PCD_H__)\n+#define __DWC_PCD_H__\n+\n+#include \"dwc_otg_os_dep.h\"\n+#include \"usb.h\"\n+#include \"dwc_otg_cil.h\"\n+#include \"dwc_otg_pcd_if.h\"\n+#include \"dwc_otg_driver.h\"\n+\n+struct cfiobject;\n+\n+/**\n+ * @file\n+ *\n+ * This file contains the structures, constants, and interfaces for\n+ * the Perpherial Contoller Driver (PCD).\n+ *\n+ * The Peripheral Controller Driver (PCD) for Linux will implement the\n+ * Gadget API, so that the existing Gadget drivers can be used. For\n+ * the Mass Storage Function driver the File-backed USB Storage Gadget\n+ * (FBS) driver will be used.  The FBS driver supports the\n+ * Control-Bulk (CB), Control-Bulk-Interrupt (CBI), and Bulk-Only\n+ * transports.\n+ *\n+ */\n+\n+/** Invalid DMA Address */\n+#define DWC_DMA_ADDR_INVALID\t(~(dwc_dma_t)0)\n+\n+/** Max Transfer size for any EP */\n+#define DDMA_MAX_TRANSFER_SIZE 65535\n+\n+/**\n+ * Get the pointer to the core_if from the pcd pointer.\n+ */\n+#define GET_CORE_IF( _pcd ) (_pcd->core_if)\n+\n+/**\n+ * States of EP0.\n+ */\n+typedef enum ep0_state {\n+\tEP0_DISCONNECT,\t\t/* no host */\n+\tEP0_IDLE,\n+\tEP0_IN_DATA_PHASE,\n+\tEP0_OUT_DATA_PHASE,\n+\tEP0_IN_STATUS_PHASE,\n+\tEP0_OUT_STATUS_PHASE,\n+\tEP0_STALL,\n+} ep0state_e;\n+\n+/** Fordward declaration.*/\n+struct dwc_otg_pcd;\n+\n+/** DWC_otg iso request structure.\n+ *\n+ */\n+typedef struct usb_iso_request dwc_otg_pcd_iso_request_t;\n+\n+#ifdef DWC_UTE_PER_IO\n+\n+/**\n+ * This shall be the exact analogy of the same type structure defined in the\n+ * usb_gadget.h. Each descriptor contains\n+ */\n+struct dwc_iso_pkt_desc_port {\n+\tuint32_t offset;\n+\tuint32_t length;\t/* expected length */\n+\tuint32_t actual_length;\n+\tuint32_t status;\n+};\n+\n+struct dwc_iso_xreq_port {\n+\t/** transfer/submission flag */\n+\tuint32_t tr_sub_flags;\n+\t/** Start the request ASAP */\n+#define DWC_EREQ_TF_ASAP\t\t0x00000002\n+\t/** Just enqueue the request w/o initiating a transfer */\n+#define DWC_EREQ_TF_ENQUEUE\t\t0x00000004\n+\n+\t/**\n+\t* count of ISO packets attached to this request - shall\n+\t* not exceed the pio_alloc_pkt_count\n+\t*/\n+\tuint32_t pio_pkt_count;\n+\t/** count of ISO packets allocated for this request */\n+\tuint32_t pio_alloc_pkt_count;\n+\t/** number of ISO packet errors */\n+\tuint32_t error_count;\n+\t/** reserved for future extension */\n+\tuint32_t res;\n+\t/** Will be allocated and freed in the UTE gadget and based on the CFC value */\n+\tstruct dwc_iso_pkt_desc_port *per_io_frame_descs;\n+};\n+#endif\n+/** DWC_otg request structure.\n+ * This structure is a list of requests.\n+ */\n+typedef struct dwc_otg_pcd_request {\n+\tvoid *priv;\n+\tvoid *buf;\n+\tdwc_dma_t dma;\n+\tuint32_t length;\n+\tuint32_t actual;\n+\tunsigned sent_zlp:1;\n+    /**\n+     * Used instead of original buffer if\n+     * it(physical address) is not dword-aligned.\n+     **/\n+     uint8_t *dw_align_buf;\n+     dwc_dma_t dw_align_buf_dma;\n+\n+\t DWC_CIRCLEQ_ENTRY(dwc_otg_pcd_request) queue_entry;\n+#ifdef DWC_UTE_PER_IO\n+\tstruct dwc_iso_xreq_port ext_req;\n+\t//void *priv_ereq_nport; /*  */\n+#endif\n+} dwc_otg_pcd_request_t;\n+\n+DWC_CIRCLEQ_HEAD(req_list, dwc_otg_pcd_request);\n+\n+/**\t  PCD EP structure.\n+ * This structure describes an EP, there is an array of EPs in the PCD\n+ * structure.\n+ */\n+typedef struct dwc_otg_pcd_ep {\n+\t/** USB EP Descriptor */\n+\tconst usb_endpoint_descriptor_t *desc;\n+\n+\t/** queue of dwc_otg_pcd_requests. */\n+\tstruct req_list queue;\n+\tunsigned stopped:1;\n+\tunsigned disabling:1;\n+\tunsigned dma:1;\n+\tunsigned queue_sof:1;\n+\n+#ifdef DWC_EN_ISOC\n+\t/** ISOC req handle passed */\n+\tvoid *iso_req_handle;\n+#endif\t\t\t\t//_EN_ISOC_\n+\n+\t/** DWC_otg ep data. */\n+\tdwc_ep_t dwc_ep;\n+\n+\t/** Pointer to PCD */\n+\tstruct dwc_otg_pcd *pcd;\n+\n+\tvoid *priv;\n+} dwc_otg_pcd_ep_t;\n+\n+/** DWC_otg PCD Structure.\n+ * This structure encapsulates the data for the dwc_otg PCD.\n+ */\n+struct dwc_otg_pcd {\n+\tconst struct dwc_otg_pcd_function_ops *fops;\n+\t/** The DWC otg device pointer */\n+\tstruct dwc_otg_device *otg_dev;\n+\t/** Core Interface */\n+\tdwc_otg_core_if_t *core_if;\n+\t/** State of EP0 */\n+\tep0state_e ep0state;\n+\t/** EP0 Request is pending */\n+\tunsigned ep0_pending:1;\n+\t/** Indicates when SET CONFIGURATION Request is in process */\n+\tunsigned request_config:1;\n+\t/** The state of the Remote Wakeup Enable. */\n+\tunsigned remote_wakeup_enable:1;\n+\t/** The state of the B-Device HNP Enable. */\n+\tunsigned b_hnp_enable:1;\n+\t/** The state of A-Device HNP Support. */\n+\tunsigned a_hnp_support:1;\n+\t/** The state of the A-Device Alt HNP support. */\n+\tunsigned a_alt_hnp_support:1;\n+\t/** Count of pending Requests */\n+\tunsigned request_pending;\n+\n+\t/** SETUP packet for EP0\n+\t * This structure is allocated as a DMA buffer on PCD initialization\n+\t * with enough space for up to 3 setup packets.\n+\t */\n+\tunion {\n+\t\tusb_device_request_t req;\n+\t\tuint32_t d32[2];\n+\t} *setup_pkt;\n+\n+\tdwc_dma_t setup_pkt_dma_handle;\n+\n+\t/* Additional buffer and flag for CTRL_WR premature case */\n+\tuint8_t *backup_buf;\n+\tunsigned data_terminated;\n+\n+\t/** 2-byte dma buffer used to return status from GET_STATUS */\n+\tuint16_t *status_buf;\n+\tdwc_dma_t status_buf_dma_handle;\n+\n+\t/** EP0 */\n+\tdwc_otg_pcd_ep_t ep0;\n+\n+\t/** Array of IN EPs. */\n+\tdwc_otg_pcd_ep_t in_ep[MAX_EPS_CHANNELS - 1];\n+\t/** Array of OUT EPs. */\n+\tdwc_otg_pcd_ep_t out_ep[MAX_EPS_CHANNELS - 1];\n+\t/** number of valid EPs in the above array. */\n+//        unsigned      num_eps : 4;\n+\tdwc_spinlock_t *lock;\n+\n+\t/** Tasklet to defer starting of TEST mode transmissions until\n+\t *\tStatus Phase has been completed.\n+\t */\n+\tdwc_tasklet_t *test_mode_tasklet;\n+\n+\t/** Tasklet to delay starting of xfer in DMA mode */\n+\tdwc_tasklet_t *start_xfer_tasklet;\n+\n+\t/** The test mode to enter when the tasklet is executed. */\n+\tunsigned test_mode;\n+\t/** The cfi_api structure that implements most of the CFI API\n+\t * and OTG specific core configuration functionality\n+\t */\n+#ifdef DWC_UTE_CFI\n+\tstruct cfiobject *cfi;\n+#endif\n+\n+};\n+\n+static inline struct device *dwc_otg_pcd_to_dev(struct dwc_otg_pcd *pcd)\n+{\n+\treturn &pcd->otg_dev->os_dep.platformdev->dev;\n+}\n+\n+//FIXME this functions should be static, and this prototypes should be removed\n+extern void dwc_otg_request_nuke(dwc_otg_pcd_ep_t * ep);\n+extern void dwc_otg_request_done(dwc_otg_pcd_ep_t * ep,\n+\t\t\t\t dwc_otg_pcd_request_t * req, int32_t status);\n+\n+void dwc_otg_iso_buffer_done(dwc_otg_pcd_t * pcd, dwc_otg_pcd_ep_t * ep,\n+\t\t\t     void *req_handle);\n+\n+extern void do_test_mode(void *data);\n+#endif\n+#endif /* DWC_HOST_ONLY */\n--- /dev/null\n+++ b/drivers/usb/host/dwc_otg/dwc_otg_pcd_if.h\n@@ -0,0 +1,361 @@\n+/* ==========================================================================\n+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd_if.h $\n+ * $Revision: #11 $\n+ * $Date: 2011/10/26 $\n+ * $Change: 1873028 $\n+ *\n+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,\n+ * \"Software\") is an Unsupported proprietary work of Synopsys, Inc. unless\n+ * otherwise expressly agreed to in writing between Synopsys and you.\n+ *\n+ * The Software IS NOT an item of Licensed Software or Licensed Product under\n+ * any End User Software License Agreement or Agreement for Licensed Product\n+ * with Synopsys or any supplement thereto. You are permitted to use and\n+ * redistribute this Software in source and binary forms, with or without\n+ * modification, provided that redistributions of source code must retain this\n+ * notice. You may not view, use, disclose, copy or distribute this file or\n+ * any information contained herein except pursuant to this license grant from\n+ * Synopsys. If you do not agree with this notice, including the disclaimer\n+ * below, then you are not authorized to use the Software.\n+ *\n+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN \"AS IS\" BASIS\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,\n+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH\n+ * DAMAGE.\n+ * ========================================================================== */\n+#ifndef DWC_HOST_ONLY\n+\n+#if !defined(__DWC_PCD_IF_H__)\n+#define __DWC_PCD_IF_H__\n+\n+//#include \"dwc_os.h\"\n+#include \"dwc_otg_core_if.h\"\n+#include \"dwc_otg_driver.h\"\n+\n+/** @file\n+ * This file defines DWC_OTG PCD Core API.\n+ */\n+\n+struct dwc_otg_pcd;\n+typedef struct dwc_otg_pcd dwc_otg_pcd_t;\n+\n+/** Maxpacket size for EP0 */\n+#define MAX_EP0_SIZE\t64\n+/** Maxpacket size for any EP */\n+#define MAX_PACKET_SIZE 1024\n+\n+/** @name Function Driver Callbacks */\n+/** @{ */\n+\n+/** This function will be called whenever a previously queued request has\n+ * completed.  The status value will be set to -DWC_E_SHUTDOWN to indicated a\n+ * failed or aborted transfer, or -DWC_E_RESTART to indicate the device was reset,\n+ * or -DWC_E_TIMEOUT to indicate it timed out, or -DWC_E_INVALID to indicate invalid\n+ * parameters. */\n+typedef int (*dwc_completion_cb_t) (dwc_otg_pcd_t * pcd, void *ep_handle,\n+\t\t\t\t    void *req_handle, int32_t status,\n+\t\t\t\t    uint32_t actual);\n+/**\n+ * This function will be called whenever a previousle queued ISOC request has\n+ * completed. Count of ISOC packets could be read using dwc_otg_pcd_get_iso_packet_count\n+ * function.\n+ * The status of each ISOC packet could be read using dwc_otg_pcd_get_iso_packet_*\n+ * functions.\n+ */\n+typedef int (*dwc_isoc_completion_cb_t) (dwc_otg_pcd_t * pcd, void *ep_handle,\n+\t\t\t\t\t void *req_handle, int proc_buf_num);\n+/** This function should handle any SETUP request that cannot be handled by the\n+ * PCD Core.  This includes most GET_DESCRIPTORs, SET_CONFIGS, Any\n+ * class-specific requests, etc.  The function must non-blocking.\n+ *\n+ * Returns 0 on success.\n+ * Returns -DWC_E_NOT_SUPPORTED if the request is not supported.\n+ * Returns -DWC_E_INVALID if the setup request had invalid parameters or bytes.\n+ * Returns -DWC_E_SHUTDOWN on any other error. */\n+typedef int (*dwc_setup_cb_t) (dwc_otg_pcd_t * pcd, uint8_t * bytes);\n+/** This is called whenever the device has been disconnected.  The function\n+ * driver should take appropriate action to clean up all pending requests in the\n+ * PCD Core, remove all endpoints (except ep0), and initialize back to reset\n+ * state. */\n+typedef int (*dwc_disconnect_cb_t) (dwc_otg_pcd_t * pcd);\n+/** This function is called when device has been connected. */\n+typedef int (*dwc_connect_cb_t) (dwc_otg_pcd_t * pcd, int speed);\n+/** This function is called when device has been suspended */\n+typedef int (*dwc_suspend_cb_t) (dwc_otg_pcd_t * pcd);\n+/** This function is called when device has received LPM tokens, i.e.\n+ * device has been sent to sleep state. */\n+typedef int (*dwc_sleep_cb_t) (dwc_otg_pcd_t * pcd);\n+/** This function is called when device has been resumed\n+ * from suspend(L2) or L1 sleep state. */\n+typedef int (*dwc_resume_cb_t) (dwc_otg_pcd_t * pcd);\n+/** This function is called whenever hnp params has been changed.\n+ * User can call get_b_hnp_enable, get_a_hnp_support, get_a_alt_hnp_support functions\n+ * to get hnp parameters. */\n+typedef int (*dwc_hnp_params_changed_cb_t) (dwc_otg_pcd_t * pcd);\n+/** This function is called whenever USB RESET is detected. */\n+typedef int (*dwc_reset_cb_t) (dwc_otg_pcd_t * pcd);\n+\n+typedef int (*cfi_setup_cb_t) (dwc_otg_pcd_t * pcd, void *ctrl_req_bytes);\n+\n+/**\n+ *\n+ * @param ep_handle\tVoid pointer to the usb_ep structure\n+ * @param ereq_port Pointer to the extended request structure created in the\n+ *\t\t\t\t\tportable part.\n+ */\n+typedef int (*xiso_completion_cb_t) (dwc_otg_pcd_t * pcd, void *ep_handle,\n+\t\t\t\t     void *req_handle, int32_t status,\n+\t\t\t\t     void *ereq_port);\n+/** Function Driver Ops Data Structure */\n+struct dwc_otg_pcd_function_ops {\n+\tdwc_connect_cb_t connect;\n+\tdwc_disconnect_cb_t disconnect;\n+\tdwc_setup_cb_t setup;\n+\tdwc_completion_cb_t complete;\n+\tdwc_isoc_completion_cb_t isoc_complete;\n+\tdwc_suspend_cb_t suspend;\n+\tdwc_sleep_cb_t sleep;\n+\tdwc_resume_cb_t resume;\n+\tdwc_reset_cb_t reset;\n+\tdwc_hnp_params_changed_cb_t hnp_changed;\n+\tcfi_setup_cb_t cfi_setup;\n+#ifdef DWC_UTE_PER_IO\n+\txiso_completion_cb_t xisoc_complete;\n+#endif\n+};\n+/** @} */\n+\n+/** @name Function Driver Functions */\n+/** @{ */\n+\n+/** Call this function to get pointer on dwc_otg_pcd_t,\n+ * this pointer will be used for all PCD API functions.\n+ *\n+ * @param core_if The DWC_OTG Core\n+ */\n+extern dwc_otg_pcd_t *dwc_otg_pcd_init(dwc_otg_device_t *otg_dev);\n+\n+/** Frees PCD allocated by dwc_otg_pcd_init\n+ *\n+ * @param pcd The PCD\n+ */\n+extern void dwc_otg_pcd_remove(dwc_otg_pcd_t * pcd);\n+\n+/** Call this to bind the function driver to the PCD Core.\n+ *\n+ * @param pcd Pointer on dwc_otg_pcd_t returned by dwc_otg_pcd_init function.\n+ * @param fops The Function Driver Ops data structure containing pointers to all callbacks.\n+ */\n+extern void dwc_otg_pcd_start(dwc_otg_pcd_t * pcd,\n+\t\t\t      const struct dwc_otg_pcd_function_ops *fops);\n+\n+/** Enables an endpoint for use.  This function enables an endpoint in\n+ * the PCD.  The endpoint is described by the ep_desc which has the\n+ * same format as a USB ep descriptor.  The ep_handle parameter is used to refer\n+ * to the endpoint from other API functions and in callbacks.  Normally this\n+ * should be called after a SET_CONFIGURATION/SET_INTERFACE to configure the\n+ * core for that interface.\n+ *\n+ * Returns -DWC_E_INVALID if invalid parameters were passed.\n+ * Returns -DWC_E_SHUTDOWN if any other error ocurred.\n+ * Returns 0 on success.\n+ *\n+ * @param pcd The PCD\n+ * @param ep_desc Endpoint descriptor\n+ * @param usb_ep Handle on endpoint, that will be used to identify endpoint.\n+ */\n+extern int dwc_otg_pcd_ep_enable(dwc_otg_pcd_t * pcd,\n+\t\t\t\t const uint8_t * ep_desc, void *usb_ep);\n+\n+/** Disable the endpoint referenced by ep_handle.\n+ *\n+ * Returns -DWC_E_INVALID if invalid parameters were passed.\n+ * Returns -DWC_E_SHUTDOWN if any other error occurred.\n+ * Returns 0 on success. */\n+extern int dwc_otg_pcd_ep_disable(dwc_otg_pcd_t * pcd, void *ep_handle);\n+\n+/** Queue a data transfer request on the endpoint referenced by ep_handle.\n+ * After the transfer is completes, the complete callback will be called with\n+ * the request status.\n+ *\n+ * @param pcd The PCD\n+ * @param ep_handle The handle of the endpoint\n+ * @param buf The buffer for the data\n+ * @param dma_buf The DMA buffer for the data\n+ * @param buflen The length of the data transfer\n+ * @param zero Specifies whether to send zero length last packet.\n+ * @param req_handle Set this handle to any value to use to reference this\n+ * request in the ep_dequeue function or from the complete callback\n+ * @param atomic_alloc If driver need to perform atomic allocations\n+ * for internal data structures.\n+ *\n+ * Returns -DWC_E_INVALID if invalid parameters were passed.\n+ * Returns -DWC_E_SHUTDOWN if any other error ocurred.\n+ * Returns 0 on success. */\n+extern int dwc_otg_pcd_ep_queue(dwc_otg_pcd_t * pcd, void *ep_handle,\n+\t\t\t\tuint8_t * buf, dwc_dma_t dma_buf,\n+\t\t\t\tuint32_t buflen, int zero, void *req_handle,\n+\t\t\t\tint atomic_alloc);\n+#ifdef DWC_UTE_PER_IO\n+/**\n+ *\n+ * @param ereq_nonport\tPointer to the extended request part of the\n+ *\t\t\t\t\t\tusb_request structure defined in usb_gadget.h file.\n+ */\n+extern int dwc_otg_pcd_xiso_ep_queue(dwc_otg_pcd_t * pcd, void *ep_handle,\n+\t\t\t\t     uint8_t * buf, dwc_dma_t dma_buf,\n+\t\t\t\t     uint32_t buflen, int zero,\n+\t\t\t\t     void *req_handle, int atomic_alloc,\n+\t\t\t\t     void *ereq_nonport);\n+\n+#endif\n+\n+/** De-queue the specified data transfer that has not yet completed.\n+ *\n+ * Returns -DWC_E_INVALID if invalid parameters were passed.\n+ * Returns -DWC_E_SHUTDOWN if any other error ocurred.\n+ * Returns 0 on success. */\n+extern int dwc_otg_pcd_ep_dequeue(dwc_otg_pcd_t * pcd, void *ep_handle,\n+\t\t\t\t  void *req_handle);\n+\n+/** Halt (STALL) an endpoint or clear it.\n+ *\n+ * Returns -DWC_E_INVALID if invalid parameters were passed.\n+ * Returns -DWC_E_SHUTDOWN if any other error ocurred.\n+ * Returns -DWC_E_AGAIN if the STALL cannot be sent and must be tried again later\n+ * Returns 0 on success. */\n+extern int dwc_otg_pcd_ep_halt(dwc_otg_pcd_t * pcd, void *ep_handle, int value);\n+\n+/** This function */\n+extern int dwc_otg_pcd_ep_wedge(dwc_otg_pcd_t * pcd, void *ep_handle);\n+\n+/** This function should be called on every hardware interrupt */\n+extern int32_t dwc_otg_pcd_handle_intr(dwc_otg_pcd_t * pcd);\n+\n+/** This function returns current frame number */\n+extern int dwc_otg_pcd_get_frame_number(dwc_otg_pcd_t * pcd);\n+\n+/**\n+ * Start isochronous transfers on the endpoint referenced by ep_handle.\n+ * For isochronous transfers duble buffering is used.\n+ * After processing each of buffers comlete callback will be called with\n+ * status for each transaction.\n+ *\n+ * @param pcd The PCD\n+ * @param ep_handle The handle of the endpoint\n+ * @param buf0 The virtual address of first data buffer\n+ * @param buf1 The virtual address of second data buffer\n+ * @param dma0 The DMA address of first data buffer\n+ * @param dma1 The DMA address of second data buffer\n+ * @param sync_frame Data pattern frame number\n+ * @param dp_frame Data size for pattern frame\n+ * @param data_per_frame Data size for regular frame\n+ * @param start_frame Frame number to start transfers, if -1 then start transfers ASAP.\n+ * @param buf_proc_intrvl Interval of ISOC Buffer processing\n+ * @param req_handle Handle of ISOC request\n+ * @param atomic_alloc Specefies whether to perform atomic allocation for\n+ * \t\t\tinternal data structures.\n+ *\n+ * Returns -DWC_E_NO_MEMORY if there is no enough memory.\n+ * Returns -DWC_E_INVALID if incorrect arguments are passed to the function.\n+ * Returns -DW_E_SHUTDOWN for any other error.\n+ * Returns 0 on success\n+ */\n+extern int dwc_otg_pcd_iso_ep_start(dwc_otg_pcd_t * pcd, void *ep_handle,\n+\t\t\t\t    uint8_t * buf0, uint8_t * buf1,\n+\t\t\t\t    dwc_dma_t dma0, dwc_dma_t dma1,\n+\t\t\t\t    int sync_frame, int dp_frame,\n+\t\t\t\t    int data_per_frame, int start_frame,\n+\t\t\t\t    int buf_proc_intrvl, void *req_handle,\n+\t\t\t\t    int atomic_alloc);\n+\n+/** Stop ISOC transfers on endpoint referenced by ep_handle.\n+ *\n+ * @param pcd The PCD\n+ * @param ep_handle The handle of the endpoint\n+ * @param req_handle Handle of ISOC request\n+ *\n+ * Returns -DWC_E_INVALID if incorrect arguments are passed to the function\n+ * Returns 0 on success\n+ */\n+int dwc_otg_pcd_iso_ep_stop(dwc_otg_pcd_t * pcd, void *ep_handle,\n+\t\t\t    void *req_handle);\n+\n+/** Get ISOC packet status.\n+ *\n+ * @param pcd The PCD\n+ * @param ep_handle The handle of the endpoint\n+ * @param iso_req_handle Isochronoush request handle\n+ * @param packet Number of packet\n+ * @param status Out parameter for returning status\n+ * @param actual Out parameter for returning actual length\n+ * @param offset Out parameter for returning offset\n+ *\n+ */\n+extern void dwc_otg_pcd_get_iso_packet_params(dwc_otg_pcd_t * pcd,\n+\t\t\t\t\t      void *ep_handle,\n+\t\t\t\t\t      void *iso_req_handle, int packet,\n+\t\t\t\t\t      int *status, int *actual,\n+\t\t\t\t\t      int *offset);\n+\n+/** Get ISOC packet count.\n+ *\n+ * @param pcd The PCD\n+ * @param ep_handle The handle of the endpoint\n+ * @param iso_req_handle\n+ */\n+extern int dwc_otg_pcd_get_iso_packet_count(dwc_otg_pcd_t * pcd,\n+\t\t\t\t\t    void *ep_handle,\n+\t\t\t\t\t    void *iso_req_handle);\n+\n+/** This function starts the SRP Protocol if no session is in progress. If\n+ * a session is already in progress, but the device is suspended,\n+ * remote wakeup signaling is started.\n+ */\n+extern int dwc_otg_pcd_wakeup(dwc_otg_pcd_t * pcd);\n+\n+/** This function returns 1 if LPM support is enabled, and 0 otherwise. */\n+extern int dwc_otg_pcd_is_lpm_enabled(dwc_otg_pcd_t * pcd);\n+\n+/** This function returns 1 if remote wakeup is allowed and 0, otherwise. */\n+extern int dwc_otg_pcd_get_rmwkup_enable(dwc_otg_pcd_t * pcd);\n+\n+/** Initiate SRP */\n+extern void dwc_otg_pcd_initiate_srp(dwc_otg_pcd_t * pcd);\n+\n+/** Starts remote wakeup signaling. */\n+extern void dwc_otg_pcd_remote_wakeup(dwc_otg_pcd_t * pcd, int set);\n+\n+/** Starts micorsecond soft disconnect. */\n+extern void dwc_otg_pcd_disconnect_us(dwc_otg_pcd_t * pcd, int no_of_usecs);\n+/** This function returns whether device is dualspeed.*/\n+extern uint32_t dwc_otg_pcd_is_dualspeed(dwc_otg_pcd_t * pcd);\n+\n+/** This function returns whether device is otg. */\n+extern uint32_t dwc_otg_pcd_is_otg(dwc_otg_pcd_t * pcd);\n+\n+/** These functions allow to get hnp parameters */\n+extern uint32_t get_b_hnp_enable(dwc_otg_pcd_t * pcd);\n+extern uint32_t get_a_hnp_support(dwc_otg_pcd_t * pcd);\n+extern uint32_t get_a_alt_hnp_support(dwc_otg_pcd_t * pcd);\n+\n+/** CFI specific Interface functions */\n+/** Allocate a cfi buffer */\n+extern uint8_t *cfiw_ep_alloc_buffer(dwc_otg_pcd_t * pcd, void *pep,\n+\t\t\t\t     dwc_dma_t * addr, size_t buflen,\n+\t\t\t\t     int flags);\n+\n+/******************************************************************************/\n+\n+/** @} */\n+\n+#endif\t\t\t\t/* __DWC_PCD_IF_H__ */\n+\n+#endif\t\t\t\t/* DWC_HOST_ONLY */\n--- /dev/null\n+++ b/drivers/usb/host/dwc_otg/dwc_otg_pcd_intr.c\n@@ -0,0 +1,5148 @@\n+/* ==========================================================================\n+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd_intr.c $\n+ * $Revision: #116 $\n+ * $Date: 2012/08/10 $\n+ * $Change: 2047372 $\n+ *\n+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,\n+ * \"Software\") is an Unsupported proprietary work of Synopsys, Inc. unless\n+ * otherwise expressly agreed to in writing between Synopsys and you.\n+ *\n+ * The Software IS NOT an item of Licensed Software or Licensed Product under\n+ * any End User Software License Agreement or Agreement for Licensed Product\n+ * with Synopsys or any supplement thereto. You are permitted to use and\n+ * redistribute this Software in source and binary forms, with or without\n+ * modification, provided that redistributions of source code must retain this\n+ * notice. You may not view, use, disclose, copy or distribute this file or\n+ * any information contained herein except pursuant to this license grant from\n+ * Synopsys. If you do not agree with this notice, including the disclaimer\n+ * below, then you are not authorized to use the Software.\n+ *\n+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN \"AS IS\" BASIS\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,\n+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH\n+ * DAMAGE.\n+ * ========================================================================== */\n+#ifndef DWC_HOST_ONLY\n+\n+#include \"dwc_otg_pcd.h\"\n+\n+#ifdef DWC_UTE_CFI\n+#include \"dwc_otg_cfi.h\"\n+#endif\n+\n+#ifdef DWC_UTE_PER_IO\n+extern void complete_xiso_ep(dwc_otg_pcd_ep_t * ep);\n+#endif\n+//#define PRINT_CFI_DMA_DESCS\n+\n+#define DEBUG_EP0\n+\n+/**\n+ * This function updates OTG.\n+ */\n+static void dwc_otg_pcd_update_otg(dwc_otg_pcd_t * pcd, const unsigned reset)\n+{\n+\n+\tif (reset) {\n+\t\tpcd->b_hnp_enable = 0;\n+\t\tpcd->a_hnp_support = 0;\n+\t\tpcd->a_alt_hnp_support = 0;\n+\t}\n+\n+\tif (pcd->fops->hnp_changed) {\n+\t\tpcd->fops->hnp_changed(pcd);\n+\t}\n+}\n+\n+/** @file\n+ * This file contains the implementation of the PCD Interrupt handlers.\n+ *\n+ * The PCD handles the device interrupts.  Many conditions can cause a\n+ * device interrupt. When an interrupt occurs, the device interrupt\n+ * service routine determines the cause of the interrupt and\n+ * dispatches handling to the appropriate function. These interrupt\n+ * handling functions are described below.\n+ * All interrupt registers are processed from LSB to MSB.\n+ */\n+\n+/**\n+ * This function prints the ep0 state for debug purposes.\n+ */\n+static inline void print_ep0_state(dwc_otg_pcd_t * pcd)\n+{\n+#ifdef DEBUG\n+\tchar str[40];\n+\n+\tswitch (pcd->ep0state) {\n+\tcase EP0_DISCONNECT:\n+\t\tdwc_strcpy(str, \"EP0_DISCONNECT\");\n+\t\tbreak;\n+\tcase EP0_IDLE:\n+\t\tdwc_strcpy(str, \"EP0_IDLE\");\n+\t\tbreak;\n+\tcase EP0_IN_DATA_PHASE:\n+\t\tdwc_strcpy(str, \"EP0_IN_DATA_PHASE\");\n+\t\tbreak;\n+\tcase EP0_OUT_DATA_PHASE:\n+\t\tdwc_strcpy(str, \"EP0_OUT_DATA_PHASE\");\n+\t\tbreak;\n+\tcase EP0_IN_STATUS_PHASE:\n+\t\tdwc_strcpy(str, \"EP0_IN_STATUS_PHASE\");\n+\t\tbreak;\n+\tcase EP0_OUT_STATUS_PHASE:\n+\t\tdwc_strcpy(str, \"EP0_OUT_STATUS_PHASE\");\n+\t\tbreak;\n+\tcase EP0_STALL:\n+\t\tdwc_strcpy(str, \"EP0_STALL\");\n+\t\tbreak;\n+\tdefault:\n+\t\tdwc_strcpy(str, \"EP0_INVALID\");\n+\t}\n+\n+\tDWC_DEBUGPL(DBG_ANY, \"%s(%d)\\n\", str, pcd->ep0state);\n+#endif\n+}\n+\n+/**\n+ * This function calculate the size of the payload in the memory\n+ * for out endpoints and prints size for debug purposes(used in\n+ * 2.93a DevOutNak feature).\n+ */\n+static inline void print_memory_payload(dwc_otg_pcd_t * pcd,  dwc_ep_t * ep)\n+{\n+#ifdef DEBUG\n+\tdeptsiz_data_t deptsiz_init = {.d32 = 0 };\n+\tdeptsiz_data_t deptsiz_updt = {.d32 = 0 };\n+\tint pack_num;\n+\tunsigned payload;\n+\n+\tdeptsiz_init.d32 = pcd->core_if->start_doeptsiz_val[ep->num];\n+\tdeptsiz_updt.d32 =\n+\t\tDWC_READ_REG32(&pcd->core_if->dev_if->\n+\t\t\t\t\t\tout_ep_regs[ep->num]->doeptsiz);\n+\t/* Payload will be */\n+\tpayload = deptsiz_init.b.xfersize - deptsiz_updt.b.xfersize;\n+\t/* Packet count is decremented every time a packet\n+\t * is written to the RxFIFO not in to the external memory\n+\t * So, if payload == 0, then it means no packet was sent to ext memory*/\n+\tpack_num = (!payload) ? 0 : (deptsiz_init.b.pktcnt - deptsiz_updt.b.pktcnt);\n+\tDWC_DEBUGPL(DBG_PCDV,\n+\t\t\"Payload for EP%d-%s\\n\",\n+\t\tep->num, (ep->is_in ? \"IN\" : \"OUT\"));\n+\tDWC_DEBUGPL(DBG_PCDV,\n+\t\t\"Number of transfered bytes = 0x%08x\\n\", payload);\n+\tDWC_DEBUGPL(DBG_PCDV,\n+\t\t\"Number of transfered packets = %d\\n\", pack_num);\n+#endif\n+}\n+\n+\n+#ifdef DWC_UTE_CFI\n+static inline void print_desc(struct dwc_otg_dma_desc *ddesc,\n+\t\t\t      const uint8_t * epname, int descnum)\n+{\n+\tCFI_INFO\n+\t    (\"%s DMA_DESC(%d) buf=0x%08x bytes=0x%04x; sp=0x%x; l=0x%x; sts=0x%02x; bs=0x%02x\\n\",\n+\t     epname, descnum, ddesc->buf, ddesc->status.b.bytes,\n+\t     ddesc->status.b.sp, ddesc->status.b.l, ddesc->status.b.sts,\n+\t     ddesc->status.b.bs);\n+}\n+#endif\n+\n+/**\n+ * This function returns pointer to in ep struct with number ep_num\n+ */\n+static inline dwc_otg_pcd_ep_t *get_in_ep(dwc_otg_pcd_t * pcd, uint32_t ep_num)\n+{\n+\tint i;\n+\tint num_in_eps = GET_CORE_IF(pcd)->dev_if->num_in_eps;\n+\tif (ep_num == 0) {\n+\t\treturn &pcd->ep0;\n+\t} else {\n+\t\tfor (i = 0; i < num_in_eps; ++i) {\n+\t\t\tif (pcd->in_ep[i].dwc_ep.num == ep_num)\n+\t\t\t\treturn &pcd->in_ep[i];\n+\t\t}\n+\t\treturn 0;\n+\t}\n+}\n+\n+/**\n+ * This function returns pointer to out ep struct with number ep_num\n+ */\n+static inline dwc_otg_pcd_ep_t *get_out_ep(dwc_otg_pcd_t * pcd, uint32_t ep_num)\n+{\n+\tint i;\n+\tint num_out_eps = GET_CORE_IF(pcd)->dev_if->num_out_eps;\n+\tif (ep_num == 0) {\n+\t\treturn &pcd->ep0;\n+\t} else {\n+\t\tfor (i = 0; i < num_out_eps; ++i) {\n+\t\t\tif (pcd->out_ep[i].dwc_ep.num == ep_num)\n+\t\t\t\treturn &pcd->out_ep[i];\n+\t\t}\n+\t\treturn 0;\n+\t}\n+}\n+\n+/**\n+ * This functions gets a pointer to an EP from the wIndex address\n+ * value of the control request.\n+ */\n+dwc_otg_pcd_ep_t *get_ep_by_addr(dwc_otg_pcd_t * pcd, u16 wIndex)\n+{\n+\tdwc_otg_pcd_ep_t *ep;\n+\tuint32_t ep_num = UE_GET_ADDR(wIndex);\n+\n+\tif (ep_num == 0) {\n+\t\tep = &pcd->ep0;\n+\t} else if (UE_GET_DIR(wIndex) == UE_DIR_IN) {\t/* in ep */\n+\t\tep = &pcd->in_ep[ep_num - 1];\n+\t} else {\n+\t\tep = &pcd->out_ep[ep_num - 1];\n+\t}\n+\n+\treturn ep;\n+}\n+\n+/**\n+ * This function checks the EP request queue, if the queue is not\n+ * empty the next request is started.\n+ */\n+void start_next_request(dwc_otg_pcd_ep_t * ep)\n+{\n+\tdwc_otg_pcd_request_t *req = 0;\n+\tuint32_t max_transfer =\n+\t    GET_CORE_IF(ep->pcd)->core_params->max_transfer_size;\n+\n+#ifdef DWC_UTE_CFI\n+\tstruct dwc_otg_pcd *pcd;\n+\tpcd = ep->pcd;\n+#endif\n+\n+\tif (!DWC_CIRCLEQ_EMPTY(&ep->queue)) {\n+\t\treq = DWC_CIRCLEQ_FIRST(&ep->queue);\n+\n+#ifdef DWC_UTE_CFI\n+\t\tif (ep->dwc_ep.buff_mode != BM_STANDARD) {\n+\t\t\tep->dwc_ep.cfi_req_len = req->length;\n+\t\t\tpcd->cfi->ops.build_descriptors(pcd->cfi, pcd, ep, req);\n+\t\t} else {\n+#endif\n+\t\t\t/* Setup and start the Transfer */\n+\t\t\tif (req->dw_align_buf) {\n+\t\t\t\tep->dwc_ep.dma_addr = req->dw_align_buf_dma;\n+\t\t\t\tep->dwc_ep.start_xfer_buff = req->dw_align_buf;\n+\t\t\t\tep->dwc_ep.xfer_buff = req->dw_align_buf;\n+\t\t\t} else {\n+\t\t\t\tep->dwc_ep.dma_addr = req->dma;\n+\t\t\t\tep->dwc_ep.start_xfer_buff = req->buf;\n+\t\t\t\tep->dwc_ep.xfer_buff = req->buf;\n+\t\t\t}\n+\t\t\tep->dwc_ep.sent_zlp = 0;\n+\t\t\tep->dwc_ep.total_len = req->length;\n+\t\t\tep->dwc_ep.xfer_len = 0;\n+\t\t\tep->dwc_ep.xfer_count = 0;\n+\n+\t\t\tep->dwc_ep.maxxfer = max_transfer;\n+\t\t\tif (GET_CORE_IF(ep->pcd)->dma_desc_enable) {\n+\t\t\t\tuint32_t out_max_xfer = DDMA_MAX_TRANSFER_SIZE\n+\t\t\t\t    - (DDMA_MAX_TRANSFER_SIZE % 4);\n+\t\t\t\tif (ep->dwc_ep.is_in) {\n+\t\t\t\t\tif (ep->dwc_ep.maxxfer >\n+\t\t\t\t\t    DDMA_MAX_TRANSFER_SIZE) {\n+\t\t\t\t\t\tep->dwc_ep.maxxfer =\n+\t\t\t\t\t\t    DDMA_MAX_TRANSFER_SIZE;\n+\t\t\t\t\t}\n+\t\t\t\t} else {\n+\t\t\t\t\tif (ep->dwc_ep.maxxfer > out_max_xfer) {\n+\t\t\t\t\t\tep->dwc_ep.maxxfer =\n+\t\t\t\t\t\t    out_max_xfer;\n+\t\t\t\t\t}\n+\t\t\t\t}\n+\t\t\t}\n+\t\t\tif (ep->dwc_ep.maxxfer < ep->dwc_ep.total_len) {\n+\t\t\t\tep->dwc_ep.maxxfer -=\n+\t\t\t\t    (ep->dwc_ep.maxxfer % ep->dwc_ep.maxpacket);\n+\t\t\t}\n+\t\t\tif (req->sent_zlp) {\n+\t\t\t\tif ((ep->dwc_ep.total_len %\n+\t\t\t\t     ep->dwc_ep.maxpacket == 0)\n+\t\t\t\t    && (ep->dwc_ep.total_len != 0)) {\n+\t\t\t\t\tep->dwc_ep.sent_zlp = 1;\n+\t\t\t\t}\n+\n+\t\t\t}\n+#ifdef DWC_UTE_CFI\n+\t\t}\n+#endif\n+\t\tdwc_otg_ep_start_transfer(GET_CORE_IF(ep->pcd), &ep->dwc_ep);\n+\t} else if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) {\n+\t\tDWC_PRINTF(\"There are no more ISOC requests \\n\");\n+\t\tep->dwc_ep.frame_num = 0xFFFFFFFF;\n+\t}\n+}\n+\n+/**\n+ * This function handles the SOF Interrupts. At this time the SOF\n+ * Interrupt is disabled.\n+ */\n+int32_t dwc_otg_pcd_handle_sof_intr(dwc_otg_pcd_t * pcd)\n+{\n+\tdwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);\n+\n+\tgintsts_data_t gintsts;\n+\n+\tDWC_DEBUGPL(DBG_PCD, \"SOF\\n\");\n+\n+\t/* Clear interrupt */\n+\tgintsts.d32 = 0;\n+\tgintsts.b.sofintr = 1;\n+\tDWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);\n+\n+\treturn 1;\n+}\n+\n+/**\n+ * This function handles the Rx Status Queue Level Interrupt, which\n+ * indicates that there is a least one packet in the Rx FIFO.  The\n+ * packets are moved from the FIFO to memory, where they will be\n+ * processed when the Endpoint Interrupt Register indicates Transfer\n+ * Complete or SETUP Phase Done.\n+ *\n+ * Repeat the following until the Rx Status Queue is empty:\n+ *\t -# Read the Receive Status Pop Register (GRXSTSP) to get Packet\n+ *\t\tinfo\n+ *\t -# If Receive FIFO is empty then skip to step Clear the interrupt\n+ *\t\tand exit\n+ *\t -# If SETUP Packet call dwc_otg_read_setup_packet to copy the\n+ *\t\tSETUP data to the buffer\n+ *\t -# If OUT Data Packet call dwc_otg_read_packet to copy the data\n+ *\t\tto the destination buffer\n+ */\n+int32_t dwc_otg_pcd_handle_rx_status_q_level_intr(dwc_otg_pcd_t * pcd)\n+{\n+\tdwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);\n+\tdwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;\n+\tgintmsk_data_t gintmask = {.d32 = 0 };\n+\tdevice_grxsts_data_t status;\n+\tdwc_otg_pcd_ep_t *ep;\n+\tgintsts_data_t gintsts;\n+#ifdef DEBUG\n+\tstatic char *dpid_str[] = { \"D0\", \"D2\", \"D1\", \"MDATA\" };\n+#endif\n+\n+\t//DWC_DEBUGPL(DBG_PCDV, \"%s(%p)\\n\", __func__, _pcd);\n+\t/* Disable the Rx Status Queue Level interrupt */\n+\tgintmask.b.rxstsqlvl = 1;\n+\tDWC_MODIFY_REG32(&global_regs->gintmsk, gintmask.d32, 0);\n+\n+\t/* Get the Status from the top of the FIFO */\n+\tstatus.d32 = DWC_READ_REG32(&global_regs->grxstsp);\n+\n+\tDWC_DEBUGPL(DBG_PCD, \"EP:%d BCnt:%d DPID:%s \"\n+\t\t    \"pktsts:%x Frame:%d(0x%0x)\\n\",\n+\t\t    status.b.epnum, status.b.bcnt,\n+\t\t    dpid_str[status.b.dpid],\n+\t\t    status.b.pktsts, status.b.fn, status.b.fn);\n+\t/* Get pointer to EP structure */\n+\tep = get_out_ep(pcd, status.b.epnum);\n+\n+\tswitch (status.b.pktsts) {\n+\tcase DWC_DSTS_GOUT_NAK:\n+\t\tDWC_DEBUGPL(DBG_PCDV, \"Global OUT NAK\\n\");\n+\t\tbreak;\n+\tcase DWC_STS_DATA_UPDT:\n+\t\tDWC_DEBUGPL(DBG_PCDV, \"OUT Data Packet\\n\");\n+\t\tif (status.b.bcnt && ep->dwc_ep.xfer_buff) {\n+\t\t\t/** @todo NGS Check for buffer overflow? */\n+\t\t\tdwc_otg_read_packet(core_if,\n+\t\t\t\t\t    ep->dwc_ep.xfer_buff,\n+\t\t\t\t\t    status.b.bcnt);\n+\t\t\tep->dwc_ep.xfer_count += status.b.bcnt;\n+\t\t\tep->dwc_ep.xfer_buff += status.b.bcnt;\n+\t\t}\n+\t\tbreak;\n+\tcase DWC_STS_XFER_COMP:\n+\t\tDWC_DEBUGPL(DBG_PCDV, \"OUT Complete\\n\");\n+\t\tbreak;\n+\tcase DWC_DSTS_SETUP_COMP:\n+#ifdef DEBUG_EP0\n+\t\tDWC_DEBUGPL(DBG_PCDV, \"Setup Complete\\n\");\n+#endif\n+\t\tbreak;\n+\tcase DWC_DSTS_SETUP_UPDT:\n+\t\tdwc_otg_read_setup_packet(core_if, pcd->setup_pkt->d32);\n+#ifdef DEBUG_EP0\n+\t\tDWC_DEBUGPL(DBG_PCD,\n+\t\t\t    \"SETUP PKT: %02x.%02x v%04x i%04x l%04x\\n\",\n+\t\t\t    pcd->setup_pkt->req.bmRequestType,\n+\t\t\t    pcd->setup_pkt->req.bRequest,\n+\t\t\t    UGETW(pcd->setup_pkt->req.wValue),\n+\t\t\t    UGETW(pcd->setup_pkt->req.wIndex),\n+\t\t\t    UGETW(pcd->setup_pkt->req.wLength));\n+#endif\n+\t\tep->dwc_ep.xfer_count += status.b.bcnt;\n+\t\tbreak;\n+\tdefault:\n+\t\tDWC_DEBUGPL(DBG_PCDV, \"Invalid Packet Status (0x%0x)\\n\",\n+\t\t\t    status.b.pktsts);\n+\t\tbreak;\n+\t}\n+\n+\t/* Enable the Rx Status Queue Level interrupt */\n+\tDWC_MODIFY_REG32(&global_regs->gintmsk, 0, gintmask.d32);\n+\t/* Clear interrupt */\n+\tgintsts.d32 = 0;\n+\tgintsts.b.rxstsqlvl = 1;\n+\tDWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);\n+\n+\t//DWC_DEBUGPL(DBG_PCDV, \"EXIT: %s\\n\", __func__);\n+\treturn 1;\n+}\n+\n+/**\n+ * This function examines the Device IN Token Learning Queue to\n+ * determine the EP number of the last IN token received.  This\n+ * implementation is for the Mass Storage device where there are only\n+ * 2 IN EPs (Control-IN and BULK-IN).\n+ *\n+ * The EP numbers for the first six IN Tokens are in DTKNQR1 and there\n+ * are 8 EP Numbers in each of the other possible DTKNQ Registers.\n+ *\n+ * @param core_if Programming view of DWC_otg controller.\n+ *\n+ */\n+static inline int get_ep_of_last_in_token(dwc_otg_core_if_t * core_if)\n+{\n+\tdwc_otg_device_global_regs_t *dev_global_regs =\n+\t    core_if->dev_if->dev_global_regs;\n+\tconst uint32_t TOKEN_Q_DEPTH = core_if->hwcfg2.b.dev_token_q_depth;\n+\t/* Number of Token Queue Registers */\n+\tconst int DTKNQ_REG_CNT = (TOKEN_Q_DEPTH + 7) / 8;\n+\tdtknq1_data_t dtknqr1;\n+\tuint32_t in_tkn_epnums[4];\n+\tint ndx = 0;\n+\tint i = 0;\n+\tvolatile uint32_t *addr = &dev_global_regs->dtknqr1;\n+\tint epnum = 0;\n+\n+\t//DWC_DEBUGPL(DBG_PCD,\"dev_token_q_depth=%d\\n\",TOKEN_Q_DEPTH);\n+\n+\t/* Read the DTKNQ Registers */\n+\tfor (i = 0; i < DTKNQ_REG_CNT; i++) {\n+\t\tin_tkn_epnums[i] = DWC_READ_REG32(addr);\n+\t\tDWC_DEBUGPL(DBG_PCDV, \"DTKNQR%d=0x%08x\\n\", i + 1,\n+\t\t\t    in_tkn_epnums[i]);\n+\t\tif (addr == &dev_global_regs->dvbusdis) {\n+\t\t\taddr = &dev_global_regs->dtknqr3_dthrctl;\n+\t\t} else {\n+\t\t\t++addr;\n+\t\t}\n+\n+\t}\n+\n+\t/* Copy the DTKNQR1 data to the bit field. */\n+\tdtknqr1.d32 = in_tkn_epnums[0];\n+\t/* Get the EP numbers */\n+\tin_tkn_epnums[0] = dtknqr1.b.epnums0_5;\n+\tndx = dtknqr1.b.intknwptr - 1;\n+\n+\t//DWC_DEBUGPL(DBG_PCDV,\"ndx=%d\\n\",ndx);\n+\tif (ndx == -1) {\n+\t\t/** @todo Find a simpler way to calculate the max\n+\t\t * queue position.*/\n+\t\tint cnt = TOKEN_Q_DEPTH;\n+\t\tif (TOKEN_Q_DEPTH <= 6) {\n+\t\t\tcnt = TOKEN_Q_DEPTH - 1;\n+\t\t} else if (TOKEN_Q_DEPTH <= 14) {\n+\t\t\tcnt = TOKEN_Q_DEPTH - 7;\n+\t\t} else if (TOKEN_Q_DEPTH <= 22) {\n+\t\t\tcnt = TOKEN_Q_DEPTH - 15;\n+\t\t} else {\n+\t\t\tcnt = TOKEN_Q_DEPTH - 23;\n+\t\t}\n+\t\tepnum = (in_tkn_epnums[DTKNQ_REG_CNT - 1] >> (cnt * 4)) & 0xF;\n+\t} else {\n+\t\tif (ndx <= 5) {\n+\t\t\tepnum = (in_tkn_epnums[0] >> (ndx * 4)) & 0xF;\n+\t\t} else if (ndx <= 13) {\n+\t\t\tndx -= 6;\n+\t\t\tepnum = (in_tkn_epnums[1] >> (ndx * 4)) & 0xF;\n+\t\t} else if (ndx <= 21) {\n+\t\t\tndx -= 14;\n+\t\t\tepnum = (in_tkn_epnums[2] >> (ndx * 4)) & 0xF;\n+\t\t} else if (ndx <= 29) {\n+\t\t\tndx -= 22;\n+\t\t\tepnum = (in_tkn_epnums[3] >> (ndx * 4)) & 0xF;\n+\t\t}\n+\t}\n+\t//DWC_DEBUGPL(DBG_PCD,\"epnum=%d\\n\",epnum);\n+\treturn epnum;\n+}\n+\n+/**\n+ * This interrupt occurs when the non-periodic Tx FIFO is half-empty.\n+ * The active request is checked for the next packet to be loaded into\n+ * the non-periodic Tx FIFO.\n+ */\n+int32_t dwc_otg_pcd_handle_np_tx_fifo_empty_intr(dwc_otg_pcd_t * pcd)\n+{\n+\tdwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);\n+\tdwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;\n+\tdwc_otg_dev_in_ep_regs_t *ep_regs;\n+\tgnptxsts_data_t txstatus = {.d32 = 0 };\n+\tgintsts_data_t gintsts;\n+\n+\tint epnum = 0;\n+\tdwc_otg_pcd_ep_t *ep = 0;\n+\tuint32_t len = 0;\n+\tint dwords;\n+\n+\t/* Get the epnum from the IN Token Learning Queue. */\n+\tepnum = get_ep_of_last_in_token(core_if);\n+\tep = get_in_ep(pcd, epnum);\n+\n+\tDWC_DEBUGPL(DBG_PCD, \"NP TxFifo Empty: %d \\n\", epnum);\n+\n+\tep_regs = core_if->dev_if->in_ep_regs[epnum];\n+\n+\tlen = ep->dwc_ep.xfer_len - ep->dwc_ep.xfer_count;\n+\tif (len > ep->dwc_ep.maxpacket) {\n+\t\tlen = ep->dwc_ep.maxpacket;\n+\t}\n+\tdwords = (len + 3) / 4;\n+\n+\t/* While there is space in the queue and space in the FIFO and\n+\t * More data to tranfer, Write packets to the Tx FIFO */\n+\ttxstatus.d32 = DWC_READ_REG32(&global_regs->gnptxsts);\n+\tDWC_DEBUGPL(DBG_PCDV, \"b4 GNPTXSTS=0x%08x\\n\", txstatus.d32);\n+\n+\twhile (txstatus.b.nptxqspcavail > 0 &&\n+\t       txstatus.b.nptxfspcavail > dwords &&\n+\t       ep->dwc_ep.xfer_count < ep->dwc_ep.xfer_len) {\n+\t\t/* Write the FIFO */\n+\t\tdwc_otg_ep_write_packet(core_if, &ep->dwc_ep, 0);\n+\t\tlen = ep->dwc_ep.xfer_len - ep->dwc_ep.xfer_count;\n+\n+\t\tif (len > ep->dwc_ep.maxpacket) {\n+\t\t\tlen = ep->dwc_ep.maxpacket;\n+\t\t}\n+\n+\t\tdwords = (len + 3) / 4;\n+\t\ttxstatus.d32 = DWC_READ_REG32(&global_regs->gnptxsts);\n+\t\tDWC_DEBUGPL(DBG_PCDV, \"GNPTXSTS=0x%08x\\n\", txstatus.d32);\n+\t}\n+\n+\tDWC_DEBUGPL(DBG_PCDV, \"GNPTXSTS=0x%08x\\n\",\n+\t\t    DWC_READ_REG32(&global_regs->gnptxsts));\n+\n+\t/* Clear interrupt */\n+\tgintsts.d32 = 0;\n+\tgintsts.b.nptxfempty = 1;\n+\tDWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);\n+\n+\treturn 1;\n+}\n+\n+/**\n+ * This function is called when dedicated Tx FIFO Empty interrupt occurs.\n+ * The active request is checked for the next packet to be loaded into\n+ * apropriate Tx FIFO.\n+ */\n+static int32_t write_empty_tx_fifo(dwc_otg_pcd_t * pcd, uint32_t epnum)\n+{\n+\tdwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);\n+\tdwc_otg_dev_if_t *dev_if = core_if->dev_if;\n+\tdwc_otg_dev_in_ep_regs_t *ep_regs;\n+\tdtxfsts_data_t txstatus = {.d32 = 0 };\n+\tdwc_otg_pcd_ep_t *ep = 0;\n+\tuint32_t len = 0;\n+\tint dwords;\n+\n+\tep = get_in_ep(pcd, epnum);\n+\n+\tDWC_DEBUGPL(DBG_PCD, \"Dedicated TxFifo Empty: %d \\n\", epnum);\n+\n+\tep_regs = core_if->dev_if->in_ep_regs[epnum];\n+\n+\tlen = ep->dwc_ep.xfer_len - ep->dwc_ep.xfer_count;\n+\n+\tif (len > ep->dwc_ep.maxpacket) {\n+\t\tlen = ep->dwc_ep.maxpacket;\n+\t}\n+\n+\tdwords = (len + 3) / 4;\n+\n+\t/* While there is space in the queue and space in the FIFO and\n+\t * More data to tranfer, Write packets to the Tx FIFO */\n+\ttxstatus.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dtxfsts);\n+\tDWC_DEBUGPL(DBG_PCDV, \"b4 dtxfsts[%d]=0x%08x\\n\", epnum, txstatus.d32);\n+\n+\twhile (txstatus.b.txfspcavail > dwords &&\n+\t       ep->dwc_ep.xfer_count < ep->dwc_ep.xfer_len &&\n+\t       ep->dwc_ep.xfer_len != 0) {\n+\t\t/* Write the FIFO */\n+\t\tdwc_otg_ep_write_packet(core_if, &ep->dwc_ep, 0);\n+\n+\t\tlen = ep->dwc_ep.xfer_len - ep->dwc_ep.xfer_count;\n+\t\tif (len > ep->dwc_ep.maxpacket) {\n+\t\t\tlen = ep->dwc_ep.maxpacket;\n+\t\t}\n+\n+\t\tdwords = (len + 3) / 4;\n+\t\ttxstatus.d32 =\n+\t\t    DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dtxfsts);\n+\t\tDWC_DEBUGPL(DBG_PCDV, \"dtxfsts[%d]=0x%08x\\n\", epnum,\n+\t\t\t    txstatus.d32);\n+\t}\n+\n+\tDWC_DEBUGPL(DBG_PCDV, \"b4 dtxfsts[%d]=0x%08x\\n\", epnum,\n+\t\t    DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dtxfsts));\n+\n+\treturn 1;\n+}\n+\n+/**\n+ * This function is called when the Device is disconnected. It stops\n+ * any active requests and informs the Gadget driver of the\n+ * disconnect.\n+ */\n+void dwc_otg_pcd_stop(dwc_otg_pcd_t * pcd)\n+{\n+\tint i, num_in_eps, num_out_eps;\n+\tdwc_otg_pcd_ep_t *ep;\n+\n+\tgintmsk_data_t intr_mask = {.d32 = 0 };\n+\n+\tDWC_SPINLOCK(pcd->lock);\n+\n+\tnum_in_eps = GET_CORE_IF(pcd)->dev_if->num_in_eps;\n+\tnum_out_eps = GET_CORE_IF(pcd)->dev_if->num_out_eps;\n+\n+\tDWC_DEBUGPL(DBG_PCDV, \"%s() \\n\", __func__);\n+\t/* don't disconnect drivers more than once */\n+\tif (pcd->ep0state == EP0_DISCONNECT) {\n+\t\tDWC_DEBUGPL(DBG_ANY, \"%s() Already Disconnected\\n\", __func__);\n+\t\tDWC_SPINUNLOCK(pcd->lock);\n+\t\treturn;\n+\t}\n+\tpcd->ep0state = EP0_DISCONNECT;\n+\n+\t/* Reset the OTG state. */\n+\tdwc_otg_pcd_update_otg(pcd, 1);\n+\n+\t/* Disable the NP Tx Fifo Empty Interrupt. */\n+\tintr_mask.b.nptxfempty = 1;\n+\tDWC_MODIFY_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,\n+\t\t\t intr_mask.d32, 0);\n+\n+\t/* Flush the FIFOs */\n+\t/**@todo NGS Flush Periodic FIFOs */\n+\tdwc_otg_flush_tx_fifo(GET_CORE_IF(pcd), 0x10);\n+\tdwc_otg_flush_rx_fifo(GET_CORE_IF(pcd));\n+\n+\t/* prevent new request submissions, kill any outstanding requests  */\n+\tep = &pcd->ep0;\n+\tdwc_otg_request_nuke(ep);\n+\t/* prevent new request submissions, kill any outstanding requests  */\n+\tfor (i = 0; i < num_in_eps; i++) {\n+\t\tdwc_otg_pcd_ep_t *ep = &pcd->in_ep[i];\n+\t\tdwc_otg_request_nuke(ep);\n+\t}\n+\t/* prevent new request submissions, kill any outstanding requests  */\n+\tfor (i = 0; i < num_out_eps; i++) {\n+\t\tdwc_otg_pcd_ep_t *ep = &pcd->out_ep[i];\n+\t\tdwc_otg_request_nuke(ep);\n+\t}\n+\n+\t/* report disconnect; the driver is already quiesced */\n+\tif (pcd->fops->disconnect) {\n+\t\tDWC_SPINUNLOCK(pcd->lock);\n+\t\tpcd->fops->disconnect(pcd);\n+\t\tDWC_SPINLOCK(pcd->lock);\n+\t}\n+\tDWC_SPINUNLOCK(pcd->lock);\n+}\n+\n+/**\n+ * This interrupt indicates that ...\n+ */\n+int32_t dwc_otg_pcd_handle_i2c_intr(dwc_otg_pcd_t * pcd)\n+{\n+\tgintmsk_data_t intr_mask = {.d32 = 0 };\n+\tgintsts_data_t gintsts;\n+\n+\tDWC_PRINTF(\"INTERRUPT Handler not implemented for %s\\n\", \"i2cintr\");\n+\tintr_mask.b.i2cintr = 1;\n+\tDWC_MODIFY_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,\n+\t\t\t intr_mask.d32, 0);\n+\n+\t/* Clear interrupt */\n+\tgintsts.d32 = 0;\n+\tgintsts.b.i2cintr = 1;\n+\tDWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,\n+\t\t\tgintsts.d32);\n+\treturn 1;\n+}\n+\n+/**\n+ * This interrupt indicates that ...\n+ */\n+int32_t dwc_otg_pcd_handle_early_suspend_intr(dwc_otg_pcd_t * pcd)\n+{\n+\tgintsts_data_t gintsts;\n+#if defined(VERBOSE)\n+\tDWC_PRINTF(\"Early Suspend Detected\\n\");\n+#endif\n+\n+\t/* Clear interrupt */\n+\tgintsts.d32 = 0;\n+\tgintsts.b.erlysuspend = 1;\n+\tDWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,\n+\t\t\tgintsts.d32);\n+\treturn 1;\n+}\n+\n+/**\n+ * This function configures EPO to receive SETUP packets.\n+ *\n+ * @todo NGS: Update the comments from the HW FS.\n+ *\n+ *\t-# Program the following fields in the endpoint specific registers\n+ *\tfor Control OUT EP 0, in order to receive a setup packet\n+ *\t- DOEPTSIZ0.Packet Count = 3 (To receive up to 3 back to back\n+ *\t  setup packets)\n+ *\t- DOEPTSIZE0.Transfer Size = 24 Bytes (To receive up to 3 back\n+ *\t  to back setup packets)\n+ *\t\t- In DMA mode, DOEPDMA0 Register with a memory address to\n+ *\t\t  store any setup packets received\n+ *\n+ * @param core_if Programming view of DWC_otg controller.\n+ * @param pcd\t  Programming view of the PCD.\n+ */\n+static inline void ep0_out_start(dwc_otg_core_if_t * core_if,\n+\t\t\t\t dwc_otg_pcd_t * pcd)\n+{\n+\tdwc_otg_dev_if_t *dev_if = core_if->dev_if;\n+\tdeptsiz0_data_t doeptsize0 = {.d32 = 0 };\n+\tdwc_otg_dev_dma_desc_t *dma_desc;\n+\tdepctl_data_t doepctl = {.d32 = 0 };\n+\n+#ifdef VERBOSE\n+\tDWC_DEBUGPL(DBG_PCDV, \"%s() doepctl0=%0x\\n\", __func__,\n+\t\t    DWC_READ_REG32(&dev_if->out_ep_regs[0]->doepctl));\n+#endif\n+\tif (core_if->snpsid >= OTG_CORE_REV_3_00a) {\n+\t\tdoepctl.d32 = DWC_READ_REG32(&dev_if->out_ep_regs[0]->doepctl);\n+\t\tif (doepctl.b.epena) {\n+\t\t\treturn;\n+\t\t}\n+\t}\n+\n+\tdoeptsize0.b.supcnt = 3;\n+\tdoeptsize0.b.pktcnt = 1;\n+\tdoeptsize0.b.xfersize = 8 * 3;\n+\n+\tif (core_if->dma_enable) {\n+\t\tif (!core_if->dma_desc_enable) {\n+\t\t\t/** put here as for Hermes mode deptisz register should not be written */\n+\t\t\tDWC_WRITE_REG32(&dev_if->out_ep_regs[0]->doeptsiz,\n+\t\t\t\t\tdoeptsize0.d32);\n+\n+\t\t\t/** @todo dma needs to handle multiple setup packets (up to 3) */\n+\t\t\tDWC_WRITE_REG32(&dev_if->out_ep_regs[0]->doepdma,\n+\t\t\t\t\tpcd->setup_pkt_dma_handle);\n+\t\t} else {\n+\t\t\tdev_if->setup_desc_index =\n+\t\t\t    (dev_if->setup_desc_index + 1) & 1;\n+\t\t\tdma_desc =\n+\t\t\t    dev_if->setup_desc_addr[dev_if->setup_desc_index];\n+\n+\t\t\t/** DMA Descriptor Setup */\n+\t\t\tdma_desc->status.b.bs = BS_HOST_BUSY;\n+\t\t\tif (core_if->snpsid >= OTG_CORE_REV_3_00a) {\n+\t\t\t\tdma_desc->status.b.sr = 0;\n+\t\t\t\tdma_desc->status.b.mtrf = 0;\n+\t\t\t}\n+\t\t\tdma_desc->status.b.l = 1;\n+\t\t\tdma_desc->status.b.ioc = 1;\n+\t\t\tdma_desc->status.b.bytes = pcd->ep0.dwc_ep.maxpacket;\n+\t\t\tdma_desc->buf = pcd->setup_pkt_dma_handle;\n+\t\t\tdma_desc->status.b.sts = 0;\n+\t\t\tdma_desc->status.b.bs = BS_HOST_READY;\n+\n+\t\t\t/** DOEPDMA0 Register write */\n+\t\t\tDWC_WRITE_REG32(&dev_if->out_ep_regs[0]->doepdma,\n+\t\t\t\t\tdev_if->dma_setup_desc_addr\n+\t\t\t\t\t[dev_if->setup_desc_index]);\n+\t\t}\n+\n+\t} else {\n+\t\t/** put here as for Hermes mode deptisz register should not be written */\n+\t\tDWC_WRITE_REG32(&dev_if->out_ep_regs[0]->doeptsiz,\n+\t\t\t\tdoeptsize0.d32);\n+\t}\n+\n+\t/** DOEPCTL0 Register write cnak will be set after setup interrupt */\n+\tdoepctl.d32 = 0;\n+\tdoepctl.b.epena = 1;\n+\tif (core_if->snpsid <= OTG_CORE_REV_2_94a) {\n+\tdoepctl.b.cnak = 1;\n+\tDWC_WRITE_REG32(&dev_if->out_ep_regs[0]->doepctl, doepctl.d32);\n+\t} else {\n+\t\tDWC_MODIFY_REG32(&dev_if->out_ep_regs[0]->doepctl, 0, doepctl.d32);\n+\t}\n+\n+#ifdef VERBOSE\n+\tDWC_DEBUGPL(DBG_PCDV, \"doepctl0=%0x\\n\",\n+\t\t    DWC_READ_REG32(&dev_if->out_ep_regs[0]->doepctl));\n+\tDWC_DEBUGPL(DBG_PCDV, \"diepctl0=%0x\\n\",\n+\t\t    DWC_READ_REG32(&dev_if->in_ep_regs[0]->diepctl));\n+#endif\n+}\n+\n+/**\n+ * This interrupt occurs when a USB Reset is detected. When the USB\n+ * Reset Interrupt occurs the device state is set to DEFAULT and the\n+ * EP0 state is set to IDLE.\n+ *\t-#\tSet the NAK bit for all OUT endpoints (DOEPCTLn.SNAK = 1)\n+ *\t-#\tUnmask the following interrupt bits\n+ *\t\t- DAINTMSK.INEP0 = 1 (Control 0 IN endpoint)\n+ *\t- DAINTMSK.OUTEP0 = 1 (Control 0 OUT endpoint)\n+ *\t- DOEPMSK.SETUP = 1\n+ *\t- DOEPMSK.XferCompl = 1\n+ *\t- DIEPMSK.XferCompl = 1\n+ *\t- DIEPMSK.TimeOut = 1\n+ *\t-# Program the following fields in the endpoint specific registers\n+ *\tfor Control OUT EP 0, in order to receive a setup packet\n+ *\t- DOEPTSIZ0.Packet Count = 3 (To receive up to 3 back to back\n+ *\t  setup packets)\n+ *\t- DOEPTSIZE0.Transfer Size = 24 Bytes (To receive up to 3 back\n+ *\t  to back setup packets)\n+ *\t\t- In DMA mode, DOEPDMA0 Register with a memory address to\n+ *\t\t  store any setup packets received\n+ * At this point, all the required initialization, except for enabling\n+ * the control 0 OUT endpoint is done, for receiving SETUP packets.\n+ */\n+int32_t dwc_otg_pcd_handle_usb_reset_intr(dwc_otg_pcd_t * pcd)\n+{\n+\tdwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);\n+\tdwc_otg_dev_if_t *dev_if = core_if->dev_if;\n+\tdepctl_data_t doepctl = {.d32 = 0 };\n+\tdepctl_data_t diepctl = {.d32 = 0 };\n+\tdaint_data_t daintmsk = {.d32 = 0 };\n+\tdoepmsk_data_t doepmsk = {.d32 = 0 };\n+\tdiepmsk_data_t diepmsk = {.d32 = 0 };\n+\tdcfg_data_t dcfg = {.d32 = 0 };\n+\tgrstctl_t resetctl = {.d32 = 0 };\n+\tdctl_data_t dctl = {.d32 = 0 };\n+\tint i = 0;\n+\tgintsts_data_t gintsts;\n+\tpcgcctl_data_t power = {.d32 = 0 };\n+\n+\tpower.d32 = DWC_READ_REG32(core_if->pcgcctl);\n+\tif (power.b.stoppclk) {\n+\t\tpower.d32 = 0;\n+\t\tpower.b.stoppclk = 1;\n+\t\tDWC_MODIFY_REG32(core_if->pcgcctl, power.d32, 0);\n+\n+\t\tpower.b.pwrclmp = 1;\n+\t\tDWC_MODIFY_REG32(core_if->pcgcctl, power.d32, 0);\n+\n+\t\tpower.b.rstpdwnmodule = 1;\n+\t\tDWC_MODIFY_REG32(core_if->pcgcctl, power.d32, 0);\n+\t}\n+\n+\tcore_if->lx_state = DWC_OTG_L0;\n+\n+\tDWC_PRINTF(\"USB RESET\\n\");\n+#ifdef DWC_EN_ISOC\n+\tfor (i = 1; i < 16; ++i) {\n+\t\tdwc_otg_pcd_ep_t *ep;\n+\t\tdwc_ep_t *dwc_ep;\n+\t\tep = get_in_ep(pcd, i);\n+\t\tif (ep != 0) {\n+\t\t\tdwc_ep = &ep->dwc_ep;\n+\t\t\tdwc_ep->next_frame = 0xffffffff;\n+\t\t}\n+\t}\n+#endif /* DWC_EN_ISOC */\n+\n+\t/* reset the HNP settings */\n+\tdwc_otg_pcd_update_otg(pcd, 1);\n+\n+\t/* Clear the Remote Wakeup Signalling */\n+\tdctl.b.rmtwkupsig = 1;\n+\tDWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32, 0);\n+\n+\t/* Set NAK for all OUT EPs */\n+\tdoepctl.b.snak = 1;\n+\tfor (i = 0; i <= dev_if->num_out_eps; i++) {\n+\t\tDWC_WRITE_REG32(&dev_if->out_ep_regs[i]->doepctl, doepctl.d32);\n+\t}\n+\n+\t/* Flush the NP Tx FIFO */\n+\tdwc_otg_flush_tx_fifo(core_if, 0x10);\n+\t/* Flush the Learning Queue */\n+\tresetctl.b.intknqflsh = 1;\n+\tDWC_WRITE_REG32(&core_if->core_global_regs->grstctl, resetctl.d32);\n+\n+\tif (!core_if->core_params->en_multiple_tx_fifo && core_if->dma_enable) {\n+\t\tcore_if->start_predict = 0;\n+\t\tfor (i = 0; i<= core_if->dev_if->num_in_eps; ++i) {\n+\t\t\tcore_if->nextep_seq[i] = 0xff;\t// 0xff - EP not active\n+\t\t}\n+\t\tcore_if->nextep_seq[0] = 0;\n+\t\tcore_if->first_in_nextep_seq = 0;\n+\t\tdiepctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[0]->diepctl);\n+\t\tdiepctl.b.nextep = 0;\n+\t\tDWC_WRITE_REG32(&dev_if->in_ep_regs[0]->diepctl, diepctl.d32);\n+\n+\t\t/* Update IN Endpoint Mismatch Count by active IN NP EP count + 1 */\n+\t\tdcfg.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dcfg);\n+\t\tdcfg.b.epmscnt = 2;\n+\t\tDWC_WRITE_REG32(&dev_if->dev_global_regs->dcfg, dcfg.d32);\n+\n+\t\tDWC_DEBUGPL(DBG_PCDV,\n+\t\t\t    \"%s first_in_nextep_seq= %2d; nextep_seq[]:\\n\",\n+\t\t\t__func__, core_if->first_in_nextep_seq);\n+\t\tfor (i=0; i <= core_if->dev_if->num_in_eps; i++) {\n+\t\t\tDWC_DEBUGPL(DBG_PCDV, \"%2d\\n\", core_if->nextep_seq[i]);\n+\t\t}\n+\t}\n+\n+\tif (core_if->multiproc_int_enable) {\n+\t\tdaintmsk.b.inep0 = 1;\n+\t\tdaintmsk.b.outep0 = 1;\n+\t\tDWC_WRITE_REG32(&dev_if->dev_global_regs->deachintmsk,\n+\t\t\t\tdaintmsk.d32);\n+\n+\t\tdoepmsk.b.setup = 1;\n+\t\tdoepmsk.b.xfercompl = 1;\n+\t\tdoepmsk.b.ahberr = 1;\n+\t\tdoepmsk.b.epdisabled = 1;\n+\n+\t\tif ((core_if->dma_desc_enable) ||\n+\t\t    (core_if->dma_enable\n+\t\t     && core_if->snpsid >= OTG_CORE_REV_3_00a)) {\n+\t\t\tdoepmsk.b.stsphsercvd = 1;\n+\t\t}\n+\t\tif (core_if->dma_desc_enable)\n+\t\t\tdoepmsk.b.bna = 1;\n+/*\n+\t\tdoepmsk.b.babble = 1;\n+\t\tdoepmsk.b.nyet = 1;\n+\n+\t\tif (core_if->dma_enable) {\n+\t\t\tdoepmsk.b.nak = 1;\n+\t\t}\n+*/\n+\t\tDWC_WRITE_REG32(&dev_if->dev_global_regs->doepeachintmsk[0],\n+\t\t\t\tdoepmsk.d32);\n+\n+\t\tdiepmsk.b.xfercompl = 1;\n+\t\tdiepmsk.b.timeout = 1;\n+\t\tdiepmsk.b.epdisabled = 1;\n+\t\tdiepmsk.b.ahberr = 1;\n+\t\tdiepmsk.b.intknepmis = 1;\n+\t\tif (!core_if->en_multiple_tx_fifo && core_if->dma_enable)\n+\t\t\tdiepmsk.b.intknepmis = 0;\n+\n+/*\t\tif (core_if->dma_desc_enable) {\n+\t\t\tdiepmsk.b.bna = 1;\n+\t\t}\n+*/\n+/*\n+\t\tif (core_if->dma_enable) {\n+\t\t\tdiepmsk.b.nak = 1;\n+\t\t}\n+*/\n+\t\tDWC_WRITE_REG32(&dev_if->dev_global_regs->diepeachintmsk[0],\n+\t\t\t\tdiepmsk.d32);\n+\t} else {\n+\t\tdaintmsk.b.inep0 = 1;\n+\t\tdaintmsk.b.outep0 = 1;\n+\t\tDWC_WRITE_REG32(&dev_if->dev_global_regs->daintmsk,\n+\t\t\t\tdaintmsk.d32);\n+\n+\t\tdoepmsk.b.setup = 1;\n+\t\tdoepmsk.b.xfercompl = 1;\n+\t\tdoepmsk.b.ahberr = 1;\n+\t\tdoepmsk.b.epdisabled = 1;\n+\n+\t\tif ((core_if->dma_desc_enable) ||\n+\t\t    (core_if->dma_enable\n+\t\t     && core_if->snpsid >= OTG_CORE_REV_3_00a)) {\n+\t\t\tdoepmsk.b.stsphsercvd = 1;\n+\t\t}\n+\t\tif (core_if->dma_desc_enable)\n+\t\t\tdoepmsk.b.bna = 1;\n+\t\tDWC_WRITE_REG32(&dev_if->dev_global_regs->doepmsk, doepmsk.d32);\n+\n+\t\tdiepmsk.b.xfercompl = 1;\n+\t\tdiepmsk.b.timeout = 1;\n+\t\tdiepmsk.b.epdisabled = 1;\n+\t\tdiepmsk.b.ahberr = 1;\n+\t\tif (!core_if->en_multiple_tx_fifo && core_if->dma_enable)\n+\t\t\tdiepmsk.b.intknepmis = 0;\n+/*\n+\t\tif (core_if->dma_desc_enable) {\n+\t\t\tdiepmsk.b.bna = 1;\n+\t\t}\n+*/\n+\n+\t\tDWC_WRITE_REG32(&dev_if->dev_global_regs->diepmsk, diepmsk.d32);\n+\t}\n+\n+\t/* Reset Device Address */\n+\tdcfg.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dcfg);\n+\tdcfg.b.devaddr = 0;\n+\tDWC_WRITE_REG32(&dev_if->dev_global_regs->dcfg, dcfg.d32);\n+\n+\t/* setup EP0 to receive SETUP packets */\n+\tif (core_if->snpsid <= OTG_CORE_REV_2_94a)\n+\t\tep0_out_start(core_if, pcd);\n+\n+\t/* Clear interrupt */\n+\tgintsts.d32 = 0;\n+\tgintsts.b.usbreset = 1;\n+\tDWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);\n+\n+\treturn 1;\n+}\n+\n+/**\n+ * Get the device speed from the device status register and convert it\n+ * to USB speed constant.\n+ *\n+ * @param core_if Programming view of DWC_otg controller.\n+ */\n+static int get_device_speed(dwc_otg_core_if_t * core_if)\n+{\n+\tdsts_data_t dsts;\n+\tint speed = 0;\n+\tdsts.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);\n+\n+\tswitch (dsts.b.enumspd) {\n+\tcase DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ:\n+\t\tspeed = USB_SPEED_HIGH;\n+\t\tbreak;\n+\tcase DWC_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ:\n+\tcase DWC_DSTS_ENUMSPD_FS_PHY_48MHZ:\n+\t\tspeed = USB_SPEED_FULL;\n+\t\tbreak;\n+\n+\tcase DWC_DSTS_ENUMSPD_LS_PHY_6MHZ:\n+\t\tspeed = USB_SPEED_LOW;\n+\t\tbreak;\n+\t}\n+\n+\treturn speed;\n+}\n+\n+/**\n+ * Read the device status register and set the device speed in the\n+ * data structure.\n+ * Set up EP0 to receive SETUP packets by calling dwc_ep0_activate.\n+ */\n+int32_t dwc_otg_pcd_handle_enum_done_intr(dwc_otg_pcd_t * pcd)\n+{\n+\tdwc_otg_pcd_ep_t *ep0 = &pcd->ep0;\n+\tgintsts_data_t gintsts;\n+\tgusbcfg_data_t gusbcfg;\n+\tdwc_otg_core_global_regs_t *global_regs =\n+\t    GET_CORE_IF(pcd)->core_global_regs;\n+\tuint8_t utmi16b, utmi8b;\n+\tint speed;\n+\tDWC_DEBUGPL(DBG_PCD, \"SPEED ENUM\\n\");\n+\n+\tif (GET_CORE_IF(pcd)->snpsid >= OTG_CORE_REV_2_60a) {\n+\t\tutmi16b = 6;\t//vahrama old value was 6;\n+\t\tutmi8b = 9;\n+\t} else {\n+\t\tutmi16b = 4;\n+\t\tutmi8b = 8;\n+\t}\n+\tdwc_otg_ep0_activate(GET_CORE_IF(pcd), &ep0->dwc_ep);\n+\tif (GET_CORE_IF(pcd)->snpsid >= OTG_CORE_REV_3_00a) {\n+\t\tep0_out_start(GET_CORE_IF(pcd), pcd);\n+\t}\n+\n+#ifdef DEBUG_EP0\n+\tprint_ep0_state(pcd);\n+#endif\n+\n+\tif (pcd->ep0state == EP0_DISCONNECT) {\n+\t\tpcd->ep0state = EP0_IDLE;\n+\t} else if (pcd->ep0state == EP0_STALL) {\n+\t\tpcd->ep0state = EP0_IDLE;\n+\t}\n+\n+\tpcd->ep0state = EP0_IDLE;\n+\n+\tep0->stopped = 0;\n+\n+\tspeed = get_device_speed(GET_CORE_IF(pcd));\n+\tpcd->fops->connect(pcd, speed);\n+\n+\t/* Set USB turnaround time based on device speed and PHY interface. */\n+\tgusbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);\n+\tif (speed == USB_SPEED_HIGH) {\n+\t\tif (GET_CORE_IF(pcd)->hwcfg2.b.hs_phy_type ==\n+\t\t    DWC_HWCFG2_HS_PHY_TYPE_ULPI) {\n+\t\t\t/* ULPI interface */\n+\t\t\tgusbcfg.b.usbtrdtim = 9;\n+\t\t}\n+\t\tif (GET_CORE_IF(pcd)->hwcfg2.b.hs_phy_type ==\n+\t\t    DWC_HWCFG2_HS_PHY_TYPE_UTMI) {\n+\t\t\t/* UTMI+ interface */\n+\t\t\tif (GET_CORE_IF(pcd)->hwcfg4.b.utmi_phy_data_width == 0) {\n+\t\t\t\tgusbcfg.b.usbtrdtim = utmi8b;\n+\t\t\t} else if (GET_CORE_IF(pcd)->hwcfg4.\n+\t\t\t\t   b.utmi_phy_data_width == 1) {\n+\t\t\t\tgusbcfg.b.usbtrdtim = utmi16b;\n+\t\t\t} else if (GET_CORE_IF(pcd)->\n+\t\t\t\t   core_params->phy_utmi_width == 8) {\n+\t\t\t\tgusbcfg.b.usbtrdtim = utmi8b;\n+\t\t\t} else {\n+\t\t\t\tgusbcfg.b.usbtrdtim = utmi16b;\n+\t\t\t}\n+\t\t}\n+\t\tif (GET_CORE_IF(pcd)->hwcfg2.b.hs_phy_type ==\n+\t\t    DWC_HWCFG2_HS_PHY_TYPE_UTMI_ULPI) {\n+\t\t\t/* UTMI+  OR  ULPI interface */\n+\t\t\tif (gusbcfg.b.ulpi_utmi_sel == 1) {\n+\t\t\t\t/* ULPI interface */\n+\t\t\t\tgusbcfg.b.usbtrdtim = 9;\n+\t\t\t} else {\n+\t\t\t\t/* UTMI+ interface */\n+\t\t\t\tif (GET_CORE_IF(pcd)->\n+\t\t\t\t    core_params->phy_utmi_width == 16) {\n+\t\t\t\t\tgusbcfg.b.usbtrdtim = utmi16b;\n+\t\t\t\t} else {\n+\t\t\t\t\tgusbcfg.b.usbtrdtim = utmi8b;\n+\t\t\t\t}\n+\t\t\t}\n+\t\t}\n+\t} else {\n+\t\t/* Full or low speed */\n+\t\tgusbcfg.b.usbtrdtim = 9;\n+\t}\n+\tDWC_WRITE_REG32(&global_regs->gusbcfg, gusbcfg.d32);\n+\n+\t/* Clear interrupt */\n+\tgintsts.d32 = 0;\n+\tgintsts.b.enumdone = 1;\n+\tDWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,\n+\t\t\tgintsts.d32);\n+\treturn 1;\n+}\n+\n+/**\n+ * This interrupt indicates that the ISO OUT Packet was dropped due to\n+ * Rx FIFO full or Rx Status Queue Full.  If this interrupt occurs\n+ * read all the data from the Rx FIFO.\n+ */\n+int32_t dwc_otg_pcd_handle_isoc_out_packet_dropped_intr(dwc_otg_pcd_t * pcd)\n+{\n+\tgintmsk_data_t intr_mask = {.d32 = 0 };\n+\tgintsts_data_t gintsts;\n+\n+\tDWC_WARN(\"INTERRUPT Handler not implemented for %s\\n\",\n+\t\t \"ISOC Out Dropped\");\n+\n+\tintr_mask.b.isooutdrop = 1;\n+\tDWC_MODIFY_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,\n+\t\t\t intr_mask.d32, 0);\n+\n+\t/* Clear interrupt */\n+\tgintsts.d32 = 0;\n+\tgintsts.b.isooutdrop = 1;\n+\tDWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,\n+\t\t\tgintsts.d32);\n+\n+\treturn 1;\n+}\n+\n+/**\n+ * This interrupt indicates the end of the portion of the micro-frame\n+ * for periodic transactions.  If there is a periodic transaction for\n+ * the next frame, load the packets into the EP periodic Tx FIFO.\n+ */\n+int32_t dwc_otg_pcd_handle_end_periodic_frame_intr(dwc_otg_pcd_t * pcd)\n+{\n+\tgintmsk_data_t intr_mask = {.d32 = 0 };\n+\tgintsts_data_t gintsts;\n+\tDWC_PRINTF(\"INTERRUPT Handler not implemented for %s\\n\", \"EOP\");\n+\n+\tintr_mask.b.eopframe = 1;\n+\tDWC_MODIFY_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,\n+\t\t\t intr_mask.d32, 0);\n+\n+\t/* Clear interrupt */\n+\tgintsts.d32 = 0;\n+\tgintsts.b.eopframe = 1;\n+\tDWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,\n+\t\t\tgintsts.d32);\n+\n+\treturn 1;\n+}\n+\n+/**\n+ * This interrupt indicates that EP of the packet on the top of the\n+ * non-periodic Tx FIFO does not match EP of the IN Token received.\n+ *\n+ * The \"Device IN Token Queue\" Registers are read to determine the\n+ * order the IN Tokens have been received. The non-periodic Tx FIFO\n+ * is flushed, so it can be reloaded in the order seen in the IN Token\n+ * Queue.\n+ */\n+int32_t dwc_otg_pcd_handle_ep_mismatch_intr(dwc_otg_pcd_t * pcd)\n+{\n+\tgintsts_data_t gintsts;\n+\tdwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);\n+\tdctl_data_t dctl;\n+\tgintmsk_data_t intr_mask = {.d32 = 0 };\n+\n+\tif (!core_if->en_multiple_tx_fifo && core_if->dma_enable) {\n+\t\tcore_if->start_predict = 1;\n+\n+\t\tDWC_DEBUGPL(DBG_PCDV, \"%s(%p)\\n\", __func__, core_if);\n+\n+\t\tgintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts);\n+\t\tif (!gintsts.b.ginnakeff) {\n+\t\t\t/* Disable EP Mismatch interrupt */\n+\t\t\tintr_mask.d32 = 0;\n+\t\t\tintr_mask.b.epmismatch = 1;\n+\t\t\tDWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, intr_mask.d32, 0);\n+\t\t\t/* Enable the Global IN NAK Effective Interrupt */\n+\t\t\tintr_mask.d32 = 0;\n+\t\t\tintr_mask.b.ginnakeff = 1;\n+\t\t\tDWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, 0, intr_mask.d32);\n+\t\t\t/* Set the global non-periodic IN NAK handshake */\n+\t\t\tdctl.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl);\n+\t\t\tdctl.b.sgnpinnak = 1;\n+\t\t\tDWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32);\n+\t\t} else {\n+\t\t\tDWC_PRINTF(\"gintsts.b.ginnakeff = 1! dctl.b.sgnpinnak not set\\n\");\n+\t\t}\n+\t\t/* Disabling of all EP's will be done in dwc_otg_pcd_handle_in_nak_effective()\n+\t\t * handler after Global IN NAK Effective interrupt will be asserted */\n+\t}\n+\t/* Clear interrupt */\n+\tgintsts.d32 = 0;\n+\tgintsts.b.epmismatch = 1;\n+\tDWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);\n+\n+\treturn 1;\n+}\n+\n+/**\n+ * This interrupt is valid only in DMA mode. This interrupt indicates that the\n+ * core has stopped fetching data for IN endpoints due to the unavailability of\n+ * TxFIFO space or Request Queue space. This interrupt is used by the\n+ * application for an endpoint mismatch algorithm.\n+ *\n+ * @param pcd The PCD\n+ */\n+int32_t dwc_otg_pcd_handle_ep_fetsusp_intr(dwc_otg_pcd_t * pcd)\n+{\n+\tgintsts_data_t gintsts;\n+\tgintmsk_data_t gintmsk_data;\n+\tdctl_data_t dctl;\n+\tdwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);\n+\tDWC_DEBUGPL(DBG_PCDV, \"%s(%p)\\n\", __func__, core_if);\n+\n+\t/* Clear the global non-periodic IN NAK handshake */\n+\tdctl.d32 = 0;\n+\tdctl.b.cgnpinnak = 1;\n+\tDWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32, dctl.d32);\n+\n+\t/* Mask GINTSTS.FETSUSP interrupt */\n+\tgintmsk_data.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintmsk);\n+\tgintmsk_data.b.fetsusp = 0;\n+\tDWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, gintmsk_data.d32);\n+\n+\t/* Clear interrupt */\n+\tgintsts.d32 = 0;\n+\tgintsts.b.fetsusp = 1;\n+\tDWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);\n+\n+\treturn 1;\n+}\n+/**\n+ * This funcion stalls EP0.\n+ */\n+static inline void ep0_do_stall(dwc_otg_pcd_t * pcd, const int err_val)\n+{\n+\tdwc_otg_pcd_ep_t *ep0 = &pcd->ep0;\n+\tusb_device_request_t *ctrl = &pcd->setup_pkt->req;\n+\tDWC_WARN(\"req %02x.%02x protocol STALL; err %d\\n\",\n+\t\t ctrl->bmRequestType, ctrl->bRequest, err_val);\n+\n+\tep0->dwc_ep.is_in = 1;\n+\tdwc_otg_ep_set_stall(GET_CORE_IF(pcd), &ep0->dwc_ep);\n+\tpcd->ep0.stopped = 1;\n+\tpcd->ep0state = EP0_IDLE;\n+\tep0_out_start(GET_CORE_IF(pcd), pcd);\n+}\n+\n+/**\n+ * This functions delegates the setup command to the gadget driver.\n+ */\n+static inline void do_gadget_setup(dwc_otg_pcd_t * pcd,\n+\t\t\t\t   usb_device_request_t * ctrl)\n+{\n+\tint ret = 0;\n+\tDWC_SPINUNLOCK(pcd->lock);\n+\tret = pcd->fops->setup(pcd, (uint8_t *) ctrl);\n+\tDWC_SPINLOCK(pcd->lock);\n+\tif (ret < 0) {\n+\t\tep0_do_stall(pcd, ret);\n+\t}\n+\n+\t/** @todo This is a g_file_storage gadget driver specific\n+\t * workaround: a DELAYED_STATUS result from the fsg_setup\n+\t * routine will result in the gadget queueing a EP0 IN status\n+\t * phase for a two-stage control transfer. Exactly the same as\n+\t * a SET_CONFIGURATION/SET_INTERFACE except that this is a class\n+\t * specific request.  Need a generic way to know when the gadget\n+\t * driver will queue the status phase. Can we assume when we\n+\t * call the gadget driver setup() function that it will always\n+\t * queue and require the following flag? Need to look into\n+\t * this.\n+\t */\n+\n+\tif (ret == 256 + 999) {\n+\t\tpcd->request_config = 1;\n+\t}\n+}\n+\n+#ifdef DWC_UTE_CFI\n+/**\n+ * This functions delegates the CFI setup commands to the gadget driver.\n+ * This function will return a negative value to indicate a failure.\n+ */\n+static inline int cfi_gadget_setup(dwc_otg_pcd_t * pcd,\n+\t\t\t\t   struct cfi_usb_ctrlrequest *ctrl_req)\n+{\n+\tint ret = 0;\n+\n+\tif (pcd->fops && pcd->fops->cfi_setup) {\n+\t\tDWC_SPINUNLOCK(pcd->lock);\n+\t\tret = pcd->fops->cfi_setup(pcd, ctrl_req);\n+\t\tDWC_SPINLOCK(pcd->lock);\n+\t\tif (ret < 0) {\n+\t\t\tep0_do_stall(pcd, ret);\n+\t\t\treturn ret;\n+\t\t}\n+\t}\n+\n+\treturn ret;\n+}\n+#endif\n+\n+/**\n+ * This function starts the Zero-Length Packet for the IN status phase\n+ * of a 2 stage control transfer.\n+ */\n+static inline void do_setup_in_status_phase(dwc_otg_pcd_t * pcd)\n+{\n+\tdwc_otg_pcd_ep_t *ep0 = &pcd->ep0;\n+\tif (pcd->ep0state == EP0_STALL) {\n+\t\treturn;\n+\t}\n+\n+\tpcd->ep0state = EP0_IN_STATUS_PHASE;\n+\n+\t/* Prepare for more SETUP Packets */\n+\tDWC_DEBUGPL(DBG_PCD, \"EP0 IN ZLP\\n\");\n+\tif ((GET_CORE_IF(pcd)->snpsid >= OTG_CORE_REV_3_00a)\n+\t    && (pcd->core_if->dma_desc_enable)\n+\t    && (ep0->dwc_ep.xfer_count < ep0->dwc_ep.total_len)) {\n+\t\tDWC_DEBUGPL(DBG_PCDV,\n+\t\t\t    \"Data terminated wait next packet in out_desc_addr\\n\");\n+\t\tpcd->backup_buf = phys_to_virt(ep0->dwc_ep.dma_addr);\n+\t\tpcd->data_terminated = 1;\n+\t}\n+\tep0->dwc_ep.xfer_len = 0;\n+\tep0->dwc_ep.xfer_count = 0;\n+\tep0->dwc_ep.is_in = 1;\n+\tep0->dwc_ep.dma_addr = pcd->setup_pkt_dma_handle;\n+\tdwc_otg_ep0_start_transfer(GET_CORE_IF(pcd), &ep0->dwc_ep);\n+\n+\t/* Prepare for more SETUP Packets */\n+\t//ep0_out_start(GET_CORE_IF(pcd), pcd);\n+}\n+\n+/**\n+ * This function starts the Zero-Length Packet for the OUT status phase\n+ * of a 2 stage control transfer.\n+ */\n+static inline void do_setup_out_status_phase(dwc_otg_pcd_t * pcd)\n+{\n+\tdwc_otg_pcd_ep_t *ep0 = &pcd->ep0;\n+\tif (pcd->ep0state == EP0_STALL) {\n+\t\tDWC_DEBUGPL(DBG_PCD, \"EP0 STALLED\\n\");\n+\t\treturn;\n+\t}\n+\tpcd->ep0state = EP0_OUT_STATUS_PHASE;\n+\n+\tDWC_DEBUGPL(DBG_PCD, \"EP0 OUT ZLP\\n\");\n+\tep0->dwc_ep.xfer_len = 0;\n+\tep0->dwc_ep.xfer_count = 0;\n+\tep0->dwc_ep.is_in = 0;\n+\tep0->dwc_ep.dma_addr = pcd->setup_pkt_dma_handle;\n+\tdwc_otg_ep0_start_transfer(GET_CORE_IF(pcd), &ep0->dwc_ep);\n+\n+\t/* Prepare for more SETUP Packets */\n+\tif (GET_CORE_IF(pcd)->dma_enable == 0) {\n+\t\tep0_out_start(GET_CORE_IF(pcd), pcd);\n+\t}\n+}\n+\n+/**\n+ * Clear the EP halt (STALL) and if pending requests start the\n+ * transfer.\n+ */\n+static inline void pcd_clear_halt(dwc_otg_pcd_t * pcd, dwc_otg_pcd_ep_t * ep)\n+{\n+\tif (ep->dwc_ep.stall_clear_flag == 0)\n+\t\tdwc_otg_ep_clear_stall(GET_CORE_IF(pcd), &ep->dwc_ep);\n+\n+\t/* Reactive the EP */\n+\tdwc_otg_ep_activate(GET_CORE_IF(pcd), &ep->dwc_ep);\n+\tif (ep->stopped) {\n+\t\tep->stopped = 0;\n+\t\t/* If there is a request in the EP queue start it */\n+\n+\t\t/** @todo FIXME: this causes an EP mismatch in DMA mode.\n+\t\t * epmismatch not yet implemented. */\n+\n+\t\t/*\n+\t\t * Above fixme is solved by implmenting a tasklet to call the\n+\t\t * start_next_request(), outside of interrupt context at some\n+\t\t * time after the current time, after a clear-halt setup packet.\n+\t\t * Still need to implement ep mismatch in the future if a gadget\n+\t\t * ever uses more than one endpoint at once\n+\t\t */\n+\t\tep->queue_sof = 1;\n+\t\tDWC_TASK_SCHEDULE(pcd->start_xfer_tasklet);\n+\t}\n+\t/* Start Control Status Phase */\n+\tdo_setup_in_status_phase(pcd);\n+}\n+\n+/**\n+ * This function is called when the SET_FEATURE TEST_MODE Setup packet\n+ * is sent from the host.  The Device Control register is written with\n+ * the Test Mode bits set to the specified Test Mode.  This is done as\n+ * a tasklet so that the \"Status\" phase of the control transfer\n+ * completes before transmitting the TEST packets.\n+ *\n+ * @todo This has not been tested since the tasklet struct was put\n+ * into the PCD struct!\n+ *\n+ */\n+void do_test_mode(void *data)\n+{\n+\tdctl_data_t dctl;\n+\tdwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *) data;\n+\tdwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);\n+\tint test_mode = pcd->test_mode;\n+\n+//        DWC_WARN(\"%s() has not been tested since being rewritten!\\n\", __func__);\n+\n+\tdctl.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl);\n+\tswitch (test_mode) {\n+\tcase 1:\t\t// TEST_J\n+\t\tdctl.b.tstctl = 1;\n+\t\tbreak;\n+\n+\tcase 2:\t\t// TEST_K\n+\t\tdctl.b.tstctl = 2;\n+\t\tbreak;\n+\n+\tcase 3:\t\t// TEST_SE0_NAK\n+\t\tdctl.b.tstctl = 3;\n+\t\tbreak;\n+\n+\tcase 4:\t\t// TEST_PACKET\n+\t\tdctl.b.tstctl = 4;\n+\t\tbreak;\n+\n+\tcase 5:\t\t// TEST_FORCE_ENABLE\n+\t\tdctl.b.tstctl = 5;\n+\t\tbreak;\n+\t}\n+\tDWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32);\n+}\n+\n+/**\n+ * This function process the GET_STATUS Setup Commands.\n+ */\n+static inline void do_get_status(dwc_otg_pcd_t * pcd)\n+{\n+\tusb_device_request_t ctrl = pcd->setup_pkt->req;\n+\tdwc_otg_pcd_ep_t *ep;\n+\tdwc_otg_pcd_ep_t *ep0 = &pcd->ep0;\n+\tuint16_t *status = pcd->status_buf;\n+\tdwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);\n+\n+#ifdef DEBUG_EP0\n+\tDWC_DEBUGPL(DBG_PCD,\n+\t\t    \"GET_STATUS %02x.%02x v%04x i%04x l%04x\\n\",\n+\t\t    ctrl.bmRequestType, ctrl.bRequest,\n+\t\t    UGETW(ctrl.wValue), UGETW(ctrl.wIndex),\n+\t\t    UGETW(ctrl.wLength));\n+#endif\n+\n+\tswitch (UT_GET_RECIPIENT(ctrl.bmRequestType)) {\n+\tcase UT_DEVICE:\n+\t\tif(UGETW(ctrl.wIndex) == 0xF000) { /* OTG Status selector */\n+\t\t\tDWC_PRINTF(\"wIndex - %d\\n\", UGETW(ctrl.wIndex));\n+\t\t\tDWC_PRINTF(\"OTG VERSION - %d\\n\", core_if->otg_ver);\n+\t\t\tDWC_PRINTF(\"OTG CAP - %d, %d\\n\",\n+\t\t\t\t   core_if->core_params->otg_cap,\n+\t\t\t\t\t\tDWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE);\n+\t\t\tif (core_if->otg_ver == 1\n+\t\t\t    && core_if->core_params->otg_cap ==\n+\t\t\t    DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE) {\n+\t\t\t\tuint8_t *otgsts = (uint8_t*)pcd->status_buf;\n+\t\t\t\t*otgsts = (core_if->otg_sts & 0x1);\n+\t\t\t\tpcd->ep0_pending = 1;\n+\t\t\t\tep0->dwc_ep.start_xfer_buff =\n+\t\t\t\t    (uint8_t *) otgsts;\n+\t\t\t\tep0->dwc_ep.xfer_buff = (uint8_t *) otgsts;\n+\t\t\t\tep0->dwc_ep.dma_addr =\n+\t\t\t\t    pcd->status_buf_dma_handle;\n+\t\t\t\tep0->dwc_ep.xfer_len = 1;\n+\t\t\t\tep0->dwc_ep.xfer_count = 0;\n+\t\t\t\tep0->dwc_ep.total_len = ep0->dwc_ep.xfer_len;\n+\t\t\t\tdwc_otg_ep0_start_transfer(GET_CORE_IF(pcd),\n+\t\t\t\t\t\t\t   &ep0->dwc_ep);\n+\t\t\t\treturn;\n+\t\t\t} else {\n+\t\t\t\tep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);\n+\t\t\t\treturn;\n+\t\t\t}\n+\t\t\tbreak;\n+\t\t} else {\n+\t\t\t*status = 0x1;\t/* Self powered */\n+\t\t\t*status |= pcd->remote_wakeup_enable << 1;\n+\t\t\tbreak;\n+\t\t}\n+\tcase UT_INTERFACE:\n+\t\t*status = 0;\n+\t\tbreak;\n+\n+\tcase UT_ENDPOINT:\n+\t\tep = get_ep_by_addr(pcd, UGETW(ctrl.wIndex));\n+\t\tif (ep == 0 || UGETW(ctrl.wLength) > 2) {\n+\t\t\tep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);\n+\t\t\treturn;\n+\t\t}\n+\t\t/** @todo check for EP stall */\n+\t\t*status = ep->stopped;\n+\t\tbreak;\n+\t}\n+\tpcd->ep0_pending = 1;\n+\tep0->dwc_ep.start_xfer_buff = (uint8_t *) status;\n+\tep0->dwc_ep.xfer_buff = (uint8_t *) status;\n+\tep0->dwc_ep.dma_addr = pcd->status_buf_dma_handle;\n+\tep0->dwc_ep.xfer_len = 2;\n+\tep0->dwc_ep.xfer_count = 0;\n+\tep0->dwc_ep.total_len = ep0->dwc_ep.xfer_len;\n+\tdwc_otg_ep0_start_transfer(GET_CORE_IF(pcd), &ep0->dwc_ep);\n+}\n+\n+/**\n+ * This function process the SET_FEATURE Setup Commands.\n+ */\n+static inline void do_set_feature(dwc_otg_pcd_t * pcd)\n+{\n+\tdwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);\n+\tdwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;\n+\tusb_device_request_t ctrl = pcd->setup_pkt->req;\n+\tdwc_otg_pcd_ep_t *ep = 0;\n+\tint32_t otg_cap_param = core_if->core_params->otg_cap;\n+\tgotgctl_data_t gotgctl = {.d32 = 0 };\n+\n+\tDWC_DEBUGPL(DBG_PCD, \"SET_FEATURE:%02x.%02x v%04x i%04x l%04x\\n\",\n+\t\t    ctrl.bmRequestType, ctrl.bRequest,\n+\t\t    UGETW(ctrl.wValue), UGETW(ctrl.wIndex),\n+\t\t    UGETW(ctrl.wLength));\n+\tDWC_DEBUGPL(DBG_PCD, \"otg_cap=%d\\n\", otg_cap_param);\n+\n+\tswitch (UT_GET_RECIPIENT(ctrl.bmRequestType)) {\n+\tcase UT_DEVICE:\n+\t\tswitch (UGETW(ctrl.wValue)) {\n+\t\tcase UF_DEVICE_REMOTE_WAKEUP:\n+\t\t\tpcd->remote_wakeup_enable = 1;\n+\t\t\tbreak;\n+\n+\t\tcase UF_TEST_MODE:\n+\t\t\t/* Setup the Test Mode tasklet to do the Test\n+\t\t\t * Packet generation after the SETUP Status\n+\t\t\t * phase has completed. */\n+\n+\t\t\t/** @todo This has not been tested since the\n+\t\t\t * tasklet struct was put into the PCD\n+\t\t\t * struct! */\n+\t\t\tpcd->test_mode = UGETW(ctrl.wIndex) >> 8;\n+\t\t\tDWC_TASK_SCHEDULE(pcd->test_mode_tasklet);\n+\t\t\tbreak;\n+\n+\t\tcase UF_DEVICE_B_HNP_ENABLE:\n+\t\t\tDWC_DEBUGPL(DBG_PCDV,\n+\t\t\t\t    \"SET_FEATURE: USB_DEVICE_B_HNP_ENABLE\\n\");\n+\n+\t\t\t/* dev may initiate HNP */\n+\t\t\tif (otg_cap_param == DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE) {\n+\t\t\t\tpcd->b_hnp_enable = 1;\n+\t\t\t\tdwc_otg_pcd_update_otg(pcd, 0);\n+\t\t\t\tDWC_DEBUGPL(DBG_PCD, \"Request B HNP\\n\");\n+\t\t\t\t/**@todo Is the gotgctl.devhnpen cleared\n+\t\t\t\t * by a USB Reset? */\n+\t\t\t\tgotgctl.b.devhnpen = 1;\n+\t\t\t\tgotgctl.b.hnpreq = 1;\n+\t\t\t\tDWC_WRITE_REG32(&global_regs->gotgctl,\n+\t\t\t\t\t\tgotgctl.d32);\n+\t\t\t} else {\n+\t\t\t\tep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);\n+\t\t\t\treturn;\n+\t\t\t}\n+\t\t\tbreak;\n+\n+\t\tcase UF_DEVICE_A_HNP_SUPPORT:\n+\t\t\t/* RH port supports HNP */\n+\t\t\tDWC_DEBUGPL(DBG_PCDV,\n+\t\t\t\t    \"SET_FEATURE: USB_DEVICE_A_HNP_SUPPORT\\n\");\n+\t\t\tif (otg_cap_param == DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE) {\n+\t\t\t\tpcd->a_hnp_support = 1;\n+\t\t\t\tdwc_otg_pcd_update_otg(pcd, 0);\n+\t\t\t} else {\n+\t\t\t\tep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);\n+\t\t\t\treturn;\n+\t\t\t}\n+\t\t\tbreak;\n+\n+\t\tcase UF_DEVICE_A_ALT_HNP_SUPPORT:\n+\t\t\t/* other RH port does */\n+\t\t\tDWC_DEBUGPL(DBG_PCDV,\n+\t\t\t\t    \"SET_FEATURE: USB_DEVICE_A_ALT_HNP_SUPPORT\\n\");\n+\t\t\tif (otg_cap_param == DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE) {\n+\t\t\t\tpcd->a_alt_hnp_support = 1;\n+\t\t\t\tdwc_otg_pcd_update_otg(pcd, 0);\n+\t\t\t} else {\n+\t\t\t\tep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);\n+\t\t\t\treturn;\n+\t\t\t}\n+\t\t\tbreak;\n+\n+\t\tdefault:\n+\t\t\tep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);\n+\t\t\treturn;\n+\n+\t\t}\n+\t\tdo_setup_in_status_phase(pcd);\n+\t\tbreak;\n+\n+\tcase UT_INTERFACE:\n+\t\tdo_gadget_setup(pcd, &ctrl);\n+\t\tbreak;\n+\n+\tcase UT_ENDPOINT:\n+\t\tif (UGETW(ctrl.wValue) == UF_ENDPOINT_HALT) {\n+\t\t\tep = get_ep_by_addr(pcd, UGETW(ctrl.wIndex));\n+\t\t\tif (ep == 0) {\n+\t\t\t\tep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);\n+\t\t\t\treturn;\n+\t\t\t}\n+\t\t\tep->stopped = 1;\n+\t\t\tdwc_otg_ep_set_stall(core_if, &ep->dwc_ep);\n+\t\t}\n+\t\tdo_setup_in_status_phase(pcd);\n+\t\tbreak;\n+\t}\n+}\n+\n+/**\n+ * This function process the CLEAR_FEATURE Setup Commands.\n+ */\n+static inline void do_clear_feature(dwc_otg_pcd_t * pcd)\n+{\n+\tusb_device_request_t ctrl = pcd->setup_pkt->req;\n+\tdwc_otg_pcd_ep_t *ep = 0;\n+\n+\tDWC_DEBUGPL(DBG_PCD,\n+\t\t    \"CLEAR_FEATURE:%02x.%02x v%04x i%04x l%04x\\n\",\n+\t\t    ctrl.bmRequestType, ctrl.bRequest,\n+\t\t    UGETW(ctrl.wValue), UGETW(ctrl.wIndex),\n+\t\t    UGETW(ctrl.wLength));\n+\n+\tswitch (UT_GET_RECIPIENT(ctrl.bmRequestType)) {\n+\tcase UT_DEVICE:\n+\t\tswitch (UGETW(ctrl.wValue)) {\n+\t\tcase UF_DEVICE_REMOTE_WAKEUP:\n+\t\t\tpcd->remote_wakeup_enable = 0;\n+\t\t\tbreak;\n+\n+\t\tcase UF_TEST_MODE:\n+\t\t\t/** @todo Add CLEAR_FEATURE for TEST modes. */\n+\t\t\tbreak;\n+\n+\t\tdefault:\n+\t\t\tep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);\n+\t\t\treturn;\n+\t\t}\n+\t\tdo_setup_in_status_phase(pcd);\n+\t\tbreak;\n+\n+\tcase UT_ENDPOINT:\n+\t\tep = get_ep_by_addr(pcd, UGETW(ctrl.wIndex));\n+\t\tif (ep == 0) {\n+\t\t\tep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);\n+\t\t\treturn;\n+\t\t}\n+\n+\t\tpcd_clear_halt(pcd, ep);\n+\n+\t\tbreak;\n+\t}\n+}\n+\n+/**\n+ * This function process the SET_ADDRESS Setup Commands.\n+ */\n+static inline void do_set_address(dwc_otg_pcd_t * pcd)\n+{\n+\tdwc_otg_dev_if_t *dev_if = GET_CORE_IF(pcd)->dev_if;\n+\tusb_device_request_t ctrl = pcd->setup_pkt->req;\n+\n+\tif (ctrl.bmRequestType == UT_DEVICE) {\n+\t\tdcfg_data_t dcfg = {.d32 = 0 };\n+\n+#ifdef DEBUG_EP0\n+//                      DWC_DEBUGPL(DBG_PCDV, \"SET_ADDRESS:%d\\n\", ctrl.wValue);\n+#endif\n+\t\tdcfg.b.devaddr = UGETW(ctrl.wValue);\n+\t\tDWC_MODIFY_REG32(&dev_if->dev_global_regs->dcfg, 0, dcfg.d32);\n+\t\tdo_setup_in_status_phase(pcd);\n+\t}\n+}\n+\n+/**\n+ *\tThis function processes SETUP commands. In Linux, the USB Command\n+ *\tprocessing is done in two places - the first being the PCD and the\n+ *\tsecond in the Gadget Driver (for example, the File-Backed Storage\n+ *\tGadget Driver).\n+ *\n+ * <table>\n+ * <tr><td>Command\t</td><td>Driver </td><td>Description</td></tr>\n+ *\n+ * <tr><td>GET_STATUS </td><td>PCD </td><td>Command is processed as\n+ * defined in chapter 9 of the USB 2.0 Specification chapter 9\n+ * </td></tr>\n+ *\n+ * <tr><td>CLEAR_FEATURE </td><td>PCD </td><td>The Device and Endpoint\n+ * requests are the ENDPOINT_HALT feature is procesed, all others the\n+ * interface requests are ignored.</td></tr>\n+ *\n+ * <tr><td>SET_FEATURE </td><td>PCD </td><td>The Device and Endpoint\n+ * requests are processed by the PCD.  Interface requests are passed\n+ * to the Gadget Driver.</td></tr>\n+ *\n+ * <tr><td>SET_ADDRESS </td><td>PCD </td><td>Program the DCFG reg,\n+ * with device address received </td></tr>\n+ *\n+ * <tr><td>GET_DESCRIPTOR </td><td>Gadget Driver </td><td>Return the\n+ * requested descriptor</td></tr>\n+ *\n+ * <tr><td>SET_DESCRIPTOR </td><td>Gadget Driver </td><td>Optional -\n+ * not implemented by any of the existing Gadget Drivers.</td></tr>\n+ *\n+ * <tr><td>SET_CONFIGURATION </td><td>Gadget Driver </td><td>Disable\n+ * all EPs and enable EPs for new configuration.</td></tr>\n+ *\n+ * <tr><td>GET_CONFIGURATION </td><td>Gadget Driver </td><td>Return\n+ * the current configuration</td></tr>\n+ *\n+ * <tr><td>SET_INTERFACE </td><td>Gadget Driver </td><td>Disable all\n+ * EPs and enable EPs for new configuration.</td></tr>\n+ *\n+ * <tr><td>GET_INTERFACE </td><td>Gadget Driver </td><td>Return the\n+ * current interface.</td></tr>\n+ *\n+ * <tr><td>SYNC_FRAME </td><td>PCD </td><td>Display debug\n+ * message.</td></tr>\n+ * </table>\n+ *\n+ * When the SETUP Phase Done interrupt occurs, the PCD SETUP commands are\n+ * processed by pcd_setup. Calling the Function Driver's setup function from\n+ * pcd_setup processes the gadget SETUP commands.\n+ */\n+static inline void pcd_setup(dwc_otg_pcd_t * pcd)\n+{\n+\tdwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);\n+\tdwc_otg_dev_if_t *dev_if = core_if->dev_if;\n+\tusb_device_request_t ctrl = pcd->setup_pkt->req;\n+\tdwc_otg_pcd_ep_t *ep0 = &pcd->ep0;\n+\n+\tdeptsiz0_data_t doeptsize0 = {.d32 = 0 };\n+\n+#ifdef DWC_UTE_CFI\n+\tint retval = 0;\n+\tstruct cfi_usb_ctrlrequest cfi_req;\n+#endif\n+\n+\tdoeptsize0.d32 = DWC_READ_REG32(&dev_if->out_ep_regs[0]->doeptsiz);\n+\n+\t/** In BDMA more then 1 setup packet is not supported till 3.00a */\n+\tif (core_if->dma_enable && core_if->dma_desc_enable == 0\n+\t    && (doeptsize0.b.supcnt < 2)\n+\t    && (core_if->snpsid < OTG_CORE_REV_2_94a)) {\n+\t\tDWC_ERROR\n+\t\t    (\"\\n\\n-----------\t CANNOT handle > 1 setup packet in DMA mode\\n\\n\");\n+\t}\n+\tif ((core_if->snpsid >= OTG_CORE_REV_3_00a)\n+\t    && (core_if->dma_enable == 1) && (core_if->dma_desc_enable == 0)) {\n+\t\tctrl =\n+\t\t    (pcd->setup_pkt +\n+\t\t     (3 - doeptsize0.b.supcnt - 1 +\n+\t\t      ep0->dwc_ep.stp_rollover))->req;\n+\t}\n+#ifdef DEBUG_EP0\n+\tDWC_DEBUGPL(DBG_PCD, \"SETUP %02x.%02x v%04x i%04x l%04x\\n\",\n+\t\t    ctrl.bmRequestType, ctrl.bRequest,\n+\t\t    UGETW(ctrl.wValue), UGETW(ctrl.wIndex),\n+\t\t    UGETW(ctrl.wLength));\n+#endif\n+\n+\t/* Clean up the request queue */\n+\tdwc_otg_request_nuke(ep0);\n+\tep0->stopped = 0;\n+\n+\tif (ctrl.bmRequestType & UE_DIR_IN) {\n+\t\tep0->dwc_ep.is_in = 1;\n+\t\tpcd->ep0state = EP0_IN_DATA_PHASE;\n+\t} else {\n+\t\tep0->dwc_ep.is_in = 0;\n+\t\tpcd->ep0state = EP0_OUT_DATA_PHASE;\n+\t}\n+\n+\tif (UGETW(ctrl.wLength) == 0) {\n+\t\tep0->dwc_ep.is_in = 1;\n+\t\tpcd->ep0state = EP0_IN_STATUS_PHASE;\n+\t}\n+\n+\tif (UT_GET_TYPE(ctrl.bmRequestType) != UT_STANDARD) {\n+\n+#ifdef DWC_UTE_CFI\n+\t\tDWC_MEMCPY(&cfi_req, &ctrl, sizeof(usb_device_request_t));\n+\n+\t\t//printk(KERN_ALERT \"CFI: req_type=0x%02x; req=0x%02x\\n\",\n+\t\t\t\tctrl.bRequestType, ctrl.bRequest);\n+\t\tif (UT_GET_TYPE(cfi_req.bRequestType) == UT_VENDOR) {\n+\t\t\tif (cfi_req.bRequest > 0xB0 && cfi_req.bRequest < 0xBF) {\n+\t\t\t\tretval = cfi_setup(pcd, &cfi_req);\n+\t\t\t\tif (retval < 0) {\n+\t\t\t\t\tep0_do_stall(pcd, retval);\n+\t\t\t\t\tpcd->ep0_pending = 0;\n+\t\t\t\t\treturn;\n+\t\t\t\t}\n+\n+\t\t\t\t/* if need gadget setup then call it and check the retval */\n+\t\t\t\tif (pcd->cfi->need_gadget_att) {\n+\t\t\t\t\tretval =\n+\t\t\t\t\t    cfi_gadget_setup(pcd,\n+\t\t\t\t\t\t\t     &pcd->\n+\t\t\t\t\t\t\t     cfi->ctrl_req);\n+\t\t\t\t\tif (retval < 0) {\n+\t\t\t\t\t\tpcd->ep0_pending = 0;\n+\t\t\t\t\t\treturn;\n+\t\t\t\t\t}\n+\t\t\t\t}\n+\n+\t\t\t\tif (pcd->cfi->need_status_in_complete) {\n+\t\t\t\t\tdo_setup_in_status_phase(pcd);\n+\t\t\t\t}\n+\t\t\t\treturn;\n+\t\t\t}\n+\t\t}\n+#endif\n+\n+\t\t/* handle non-standard (class/vendor) requests in the gadget driver */\n+\t\tdo_gadget_setup(pcd, &ctrl);\n+\t\treturn;\n+\t}\n+\n+\t/** @todo NGS: Handle bad setup packet? */\n+\n+///////////////////////////////////////////\n+//// --- Standard Request handling --- ////\n+\n+\tswitch (ctrl.bRequest) {\n+\tcase UR_GET_STATUS:\n+\t\tdo_get_status(pcd);\n+\t\tbreak;\n+\n+\tcase UR_CLEAR_FEATURE:\n+\t\tdo_clear_feature(pcd);\n+\t\tbreak;\n+\n+\tcase UR_SET_FEATURE:\n+\t\tdo_set_feature(pcd);\n+\t\tbreak;\n+\n+\tcase UR_SET_ADDRESS:\n+\t\tdo_set_address(pcd);\n+\t\tbreak;\n+\n+\tcase UR_SET_INTERFACE:\n+\tcase UR_SET_CONFIG:\n+//              _pcd->request_config = 1;       /* Configuration changed */\n+\t\tdo_gadget_setup(pcd, &ctrl);\n+\t\tbreak;\n+\n+\tcase UR_SYNCH_FRAME:\n+\t\tdo_gadget_setup(pcd, &ctrl);\n+\t\tbreak;\n+\n+\tdefault:\n+\t\t/* Call the Gadget Driver's setup functions */\n+\t\tdo_gadget_setup(pcd, &ctrl);\n+\t\tbreak;\n+\t}\n+}\n+\n+/**\n+ * This function completes the ep0 control transfer.\n+ */\n+static int32_t ep0_complete_request(dwc_otg_pcd_ep_t * ep)\n+{\n+\tdwc_otg_core_if_t *core_if = GET_CORE_IF(ep->pcd);\n+\tdwc_otg_dev_if_t *dev_if = core_if->dev_if;\n+\tdwc_otg_dev_in_ep_regs_t *in_ep_regs =\n+\t    dev_if->in_ep_regs[ep->dwc_ep.num];\n+#ifdef DEBUG_EP0\n+\tdwc_otg_dev_out_ep_regs_t *out_ep_regs =\n+\t    dev_if->out_ep_regs[ep->dwc_ep.num];\n+#endif\n+\tdeptsiz0_data_t deptsiz;\n+\tdev_dma_desc_sts_t desc_sts;\n+\tdwc_otg_pcd_request_t *req;\n+\tint is_last = 0;\n+\tdwc_otg_pcd_t *pcd = ep->pcd;\n+\n+#ifdef DWC_UTE_CFI\n+\tstruct cfi_usb_ctrlrequest *ctrlreq;\n+\tint retval = -DWC_E_NOT_SUPPORTED;\n+#endif\n+\n+        desc_sts.b.bytes = 0;\n+\n+\tif (pcd->ep0_pending && DWC_CIRCLEQ_EMPTY(&ep->queue)) {\n+\t\tif (ep->dwc_ep.is_in) {\n+#ifdef DEBUG_EP0\n+\t\t\tDWC_DEBUGPL(DBG_PCDV, \"Do setup OUT status phase\\n\");\n+#endif\n+\t\t\tdo_setup_out_status_phase(pcd);\n+\t\t} else {\n+#ifdef DEBUG_EP0\n+\t\t\tDWC_DEBUGPL(DBG_PCDV, \"Do setup IN status phase\\n\");\n+#endif\n+\n+#ifdef DWC_UTE_CFI\n+\t\t\tctrlreq = &pcd->cfi->ctrl_req;\n+\n+\t\t\tif (UT_GET_TYPE(ctrlreq->bRequestType) == UT_VENDOR) {\n+\t\t\t\tif (ctrlreq->bRequest > 0xB0\n+\t\t\t\t    && ctrlreq->bRequest < 0xBF) {\n+\n+\t\t\t\t\t/* Return if the PCD failed to handle the request */\n+\t\t\t\t\tif ((retval =\n+\t\t\t\t\t     pcd->cfi->ops.\n+\t\t\t\t\t     ctrl_write_complete(pcd->cfi,\n+\t\t\t\t\t\t\t\t pcd)) < 0) {\n+\t\t\t\t\t\tCFI_INFO\n+\t\t\t\t\t\t    (\"ERROR setting a new value in the PCD(%d)\\n\",\n+\t\t\t\t\t\t     retval);\n+\t\t\t\t\t\tep0_do_stall(pcd, retval);\n+\t\t\t\t\t\tpcd->ep0_pending = 0;\n+\t\t\t\t\t\treturn 0;\n+\t\t\t\t\t}\n+\n+\t\t\t\t\t/* If the gadget needs to be notified on the request */\n+\t\t\t\t\tif (pcd->cfi->need_gadget_att == 1) {\n+\t\t\t\t\t\t//retval = do_gadget_setup(pcd, &pcd->cfi->ctrl_req);\n+\t\t\t\t\t\tretval =\n+\t\t\t\t\t\t    cfi_gadget_setup(pcd,\n+\t\t\t\t\t\t\t\t     &pcd->cfi->\n+\t\t\t\t\t\t\t\t     ctrl_req);\n+\n+\t\t\t\t\t\t/* Return from the function if the gadget failed to process\n+\t\t\t\t\t\t * the request properly - this should never happen !!!\n+\t\t\t\t\t\t */\n+\t\t\t\t\t\tif (retval < 0) {\n+\t\t\t\t\t\t\tCFI_INFO\n+\t\t\t\t\t\t\t    (\"ERROR setting a new value in the gadget(%d)\\n\",\n+\t\t\t\t\t\t\t     retval);\n+\t\t\t\t\t\t\tpcd->ep0_pending = 0;\n+\t\t\t\t\t\t\treturn 0;\n+\t\t\t\t\t\t}\n+\t\t\t\t\t}\n+\n+\t\t\t\t\tCFI_INFO(\"%s: RETVAL=%d\\n\", __func__,\n+\t\t\t\t\t\t retval);\n+\t\t\t\t\t/* If we hit here then the PCD and the gadget has properly\n+\t\t\t\t\t * handled the request - so send the ZLP IN to the host.\n+\t\t\t\t\t */\n+\t\t\t\t\t/* @todo: MAS - decide whether we need to start the setup\n+\t\t\t\t\t * stage based on the need_setup value of the cfi object\n+\t\t\t\t\t */\n+\t\t\t\t\tdo_setup_in_status_phase(pcd);\n+\t\t\t\t\tpcd->ep0_pending = 0;\n+\t\t\t\t\treturn 1;\n+\t\t\t\t}\n+\t\t\t}\n+#endif\n+\n+\t\t\tdo_setup_in_status_phase(pcd);\n+\t\t}\n+\t\tpcd->ep0_pending = 0;\n+\t\treturn 1;\n+\t}\n+\n+\tif (DWC_CIRCLEQ_EMPTY(&ep->queue)) {\n+\t\treturn 0;\n+\t}\n+\treq = DWC_CIRCLEQ_FIRST(&ep->queue);\n+\n+\tif (pcd->ep0state == EP0_OUT_STATUS_PHASE\n+\t    || pcd->ep0state == EP0_IN_STATUS_PHASE) {\n+\t\tis_last = 1;\n+\t} else if (ep->dwc_ep.is_in) {\n+\t\tdeptsiz.d32 = DWC_READ_REG32(&in_ep_regs->dieptsiz);\n+\t\tif (core_if->dma_desc_enable != 0)\n+\t\t\tdesc_sts = dev_if->in_desc_addr->status;\n+#ifdef DEBUG_EP0\n+\t\tDWC_DEBUGPL(DBG_PCDV, \"%d len=%d  xfersize=%d pktcnt=%d\\n\",\n+\t\t\t    ep->dwc_ep.num, ep->dwc_ep.xfer_len,\n+\t\t\t    deptsiz.b.xfersize, deptsiz.b.pktcnt);\n+#endif\n+\n+\t\tif (((core_if->dma_desc_enable == 0)\n+\t\t     && (deptsiz.b.xfersize == 0))\n+\t\t    || ((core_if->dma_desc_enable != 0)\n+\t\t\t&& (desc_sts.b.bytes == 0))) {\n+\t\t\treq->actual = ep->dwc_ep.xfer_count;\n+\t\t\t/* Is a Zero Len Packet needed? */\n+\t\t\tif (req->sent_zlp) {\n+#ifdef DEBUG_EP0\n+\t\t\t\tDWC_DEBUGPL(DBG_PCD, \"Setup Rx ZLP\\n\");\n+#endif\n+\t\t\t\treq->sent_zlp = 0;\n+\t\t\t}\n+\t\t\tdo_setup_out_status_phase(pcd);\n+\t\t}\n+\t} else {\n+\t\t/* ep0-OUT */\n+#ifdef DEBUG_EP0\n+\t\tdeptsiz.d32 = DWC_READ_REG32(&out_ep_regs->doeptsiz);\n+\t\tDWC_DEBUGPL(DBG_PCDV, \"%d len=%d xsize=%d pktcnt=%d\\n\",\n+\t\t\t    ep->dwc_ep.num, ep->dwc_ep.xfer_len,\n+\t\t\t    deptsiz.b.xfersize, deptsiz.b.pktcnt);\n+#endif\n+\t\treq->actual = ep->dwc_ep.xfer_count;\n+\n+\t\t/* Is a Zero Len Packet needed? */\n+\t\tif (req->sent_zlp) {\n+#ifdef DEBUG_EP0\n+\t\t\tDWC_DEBUGPL(DBG_PCDV, \"Setup Tx ZLP\\n\");\n+#endif\n+\t\t\treq->sent_zlp = 0;\n+\t\t}\n+\t\t/* For older cores do setup in status phase in Slave/BDMA modes,\n+\t\t * starting from 3.00 do that only in slave, and for DMA modes\n+\t\t * just re-enable ep 0 OUT here*/\n+\t\tif (core_if->dma_enable == 0\n+\t\t    || (core_if->dma_desc_enable == 0\n+\t\t\t&& core_if->snpsid <= OTG_CORE_REV_2_94a)) {\n+\t\t\tdo_setup_in_status_phase(pcd);\n+\t\t} else if (core_if->snpsid >= OTG_CORE_REV_3_00a) {\n+\t\t\tDWC_DEBUGPL(DBG_PCDV,\n+\t\t\t\t    \"Enable out ep before in status phase\\n\");\n+\t\t\tep0_out_start(core_if, pcd);\n+\t\t}\n+\t}\n+\n+\t/* Complete the request */\n+\tif (is_last) {\n+\t\tdwc_otg_request_done(ep, req, 0);\n+\t\tep->dwc_ep.start_xfer_buff = 0;\n+\t\tep->dwc_ep.xfer_buff = 0;\n+\t\tep->dwc_ep.xfer_len = 0;\n+\t\treturn 1;\n+\t}\n+\treturn 0;\n+}\n+\n+#ifdef DWC_UTE_CFI\n+/**\n+ * This function calculates traverses all the CFI DMA descriptors and\n+ * and accumulates the bytes that are left to be transfered.\n+ *\n+ * @return The total bytes left to transfered, or a negative value as failure\n+ */\n+static inline int cfi_calc_desc_residue(dwc_otg_pcd_ep_t * ep)\n+{\n+\tint32_t ret = 0;\n+\tint i;\n+\tstruct dwc_otg_dma_desc *ddesc = NULL;\n+\tstruct cfi_ep *cfiep;\n+\n+\t/* See if the pcd_ep has its respective cfi_ep mapped */\n+\tcfiep = get_cfi_ep_by_pcd_ep(ep->pcd->cfi, ep);\n+\tif (!cfiep) {\n+\t\tCFI_INFO(\"%s: Failed to find ep\\n\", __func__);\n+\t\treturn -1;\n+\t}\n+\n+\tddesc = ep->dwc_ep.descs;\n+\n+\tfor (i = 0; (i < cfiep->desc_count) && (i < MAX_DMA_DESCS_PER_EP); i++) {\n+\n+#if defined(PRINT_CFI_DMA_DESCS)\n+\t\tprint_desc(ddesc, ep->ep.name, i);\n+#endif\n+\t\tret += ddesc->status.b.bytes;\n+\t\tddesc++;\n+\t}\n+\n+\tif (ret)\n+\t\tCFI_INFO(\"!!!!!!!!!! WARNING (%s) - residue=%d\\n\", __func__,\n+\t\t\t ret);\n+\n+\treturn ret;\n+}\n+#endif\n+\n+/**\n+ * This function completes the request for the EP. If there are\n+ * additional requests for the EP in the queue they will be started.\n+ */\n+static void complete_ep(dwc_otg_pcd_ep_t * ep)\n+{\n+\tdwc_otg_core_if_t *core_if = GET_CORE_IF(ep->pcd);\n+\tstruct device *dev = dwc_otg_pcd_to_dev(ep->pcd);\n+\tdwc_otg_dev_if_t *dev_if = core_if->dev_if;\n+\tdwc_otg_dev_in_ep_regs_t *in_ep_regs =\n+\t    dev_if->in_ep_regs[ep->dwc_ep.num];\n+\tdeptsiz_data_t deptsiz;\n+\tdev_dma_desc_sts_t desc_sts;\n+\tdwc_otg_pcd_request_t *req = 0;\n+\tdwc_otg_dev_dma_desc_t *dma_desc;\n+\tuint32_t byte_count = 0;\n+\tint is_last = 0;\n+\tint i;\n+\n+\tDWC_DEBUGPL(DBG_PCDV, \"%s() %d-%s\\n\", __func__, ep->dwc_ep.num,\n+\t\t    (ep->dwc_ep.is_in ? \"IN\" : \"OUT\"));\n+\n+\t/* Get any pending requests */\n+\tif (!DWC_CIRCLEQ_EMPTY(&ep->queue)) {\n+\t\treq = DWC_CIRCLEQ_FIRST(&ep->queue);\n+\t\tif (!req) {\n+\t\t\tDWC_PRINTF(\"complete_ep 0x%p, req = NULL!\\n\", ep);\n+\t\t\treturn;\n+\t\t}\n+\t} else {\n+\t\tDWC_PRINTF(\"complete_ep 0x%p, ep->queue empty!\\n\", ep);\n+\t\treturn;\n+\t}\n+\n+\tDWC_DEBUGPL(DBG_PCD, \"Requests %d\\n\", ep->pcd->request_pending);\n+\n+\tif (ep->dwc_ep.is_in) {\n+\t\tdeptsiz.d32 = DWC_READ_REG32(&in_ep_regs->dieptsiz);\n+\n+\t\tif (core_if->dma_enable) {\n+\t\t\tif (core_if->dma_desc_enable == 0) {\n+\t\t\t\tif (deptsiz.b.xfersize == 0\n+\t\t\t\t    && deptsiz.b.pktcnt == 0) {\n+\t\t\t\t\tbyte_count =\n+\t\t\t\t\t    ep->dwc_ep.xfer_len -\n+\t\t\t\t\t    ep->dwc_ep.xfer_count;\n+\n+\t\t\t\t\tep->dwc_ep.xfer_buff += byte_count;\n+\t\t\t\t\tep->dwc_ep.dma_addr += byte_count;\n+\t\t\t\t\tep->dwc_ep.xfer_count += byte_count;\n+\n+\t\t\t\t\tDWC_DEBUGPL(DBG_PCDV,\n+\t\t\t\t\t\t    \"%d-%s len=%d  xfersize=%d pktcnt=%d\\n\",\n+\t\t\t\t\t\t    ep->dwc_ep.num,\n+\t\t\t\t\t\t    (ep->dwc_ep.\n+\t\t\t\t\t\t     is_in ? \"IN\" : \"OUT\"),\n+\t\t\t\t\t\t    ep->dwc_ep.xfer_len,\n+\t\t\t\t\t\t    deptsiz.b.xfersize,\n+\t\t\t\t\t\t    deptsiz.b.pktcnt);\n+\n+\t\t\t\t\tif (ep->dwc_ep.xfer_len <\n+\t\t\t\t\t    ep->dwc_ep.total_len) {\n+\t\t\t\t\t\tdwc_otg_ep_start_transfer\n+\t\t\t\t\t\t    (core_if, &ep->dwc_ep);\n+\t\t\t\t\t} else if (ep->dwc_ep.sent_zlp) {\n+\t\t\t\t\t\t/*\n+\t\t\t\t\t\t * This fragment of code should initiate 0\n+\t\t\t\t\t\t * length transfer in case if it is queued\n+\t\t\t\t\t\t * a transfer with size divisible to EPs max\n+\t\t\t\t\t\t * packet size and with usb_request zero field\n+\t\t\t\t\t\t * is set, which means that after data is transfered,\n+\t\t\t\t\t\t * it is also should be transfered\n+\t\t\t\t\t\t * a 0 length packet at the end. For Slave and\n+\t\t\t\t\t\t * Buffer DMA modes in this case SW has\n+\t\t\t\t\t\t * to initiate 2 transfers one with transfer size,\n+\t\t\t\t\t\t * and the second with 0 size. For Descriptor\n+\t\t\t\t\t\t * DMA mode SW is able to initiate a transfer,\n+\t\t\t\t\t\t * which will handle all the packets including\n+\t\t\t\t\t\t * the last  0 length.\n+\t\t\t\t\t\t */\n+\t\t\t\t\t\tep->dwc_ep.sent_zlp = 0;\n+\t\t\t\t\t\tdwc_otg_ep_start_zl_transfer\n+\t\t\t\t\t\t    (core_if, &ep->dwc_ep);\n+\t\t\t\t\t} else {\n+\t\t\t\t\t\tis_last = 1;\n+\t\t\t\t\t}\n+\t\t\t\t} else {\n+\t\t\t\t\tif (ep->dwc_ep.type ==\n+\t\t\t\t\t    DWC_OTG_EP_TYPE_ISOC) {\n+\t\t\t\t\t\treq->actual = 0;\n+\t\t\t\t\t\tdwc_otg_request_done(ep, req, 0);\n+\n+\t\t\t\t\t\tep->dwc_ep.start_xfer_buff = 0;\n+\t\t\t\t\t\tep->dwc_ep.xfer_buff = 0;\n+\t\t\t\t\t\tep->dwc_ep.xfer_len = 0;\n+\n+\t\t\t\t\t\t/* If there is a request in the queue start it. */\n+\t\t\t\t\t\tstart_next_request(ep);\n+\t\t\t\t\t} else\n+\t\t\t\t\t\tDWC_WARN\n+\t\t\t\t\t\t(\"Incomplete transfer (%d - %s [siz=%d pkt=%d])\\n\",\n+\t\t\t\t\t\tep->dwc_ep.num,\n+\t\t\t\t\t\t(ep->dwc_ep.is_in ? \"IN\" : \"OUT\"),\n+\t\t\t\t\t\tdeptsiz.b.xfersize,\n+\t\t\t\t\t\tdeptsiz.b.pktcnt);\n+\t\t\t\t}\n+\t\t\t} else {\n+\t\t\t\tdma_desc = ep->dwc_ep.desc_addr;\n+\t\t\t\tbyte_count = 0;\n+\t\t\t\tep->dwc_ep.sent_zlp = 0;\n+\n+#ifdef DWC_UTE_CFI\n+\t\t\t\tCFI_INFO(\"%s: BUFFER_MODE=%d\\n\", __func__,\n+\t\t\t\t\t ep->dwc_ep.buff_mode);\n+\t\t\t\tif (ep->dwc_ep.buff_mode != BM_STANDARD) {\n+\t\t\t\t\tint residue;\n+\n+\t\t\t\t\tresidue = cfi_calc_desc_residue(ep);\n+\t\t\t\t\tif (residue < 0)\n+\t\t\t\t\t\treturn;\n+\n+\t\t\t\t\tbyte_count = residue;\n+\t\t\t\t} else {\n+#endif\n+\t\t\t\t\tfor (i = 0; i < ep->dwc_ep.desc_cnt;\n+\t\t\t\t\t     ++i) {\n+\t\t\t\t\tdesc_sts = dma_desc->status;\n+\t\t\t\t\tbyte_count += desc_sts.b.bytes;\n+\t\t\t\t\tdma_desc++;\n+\t\t\t\t}\n+#ifdef DWC_UTE_CFI\n+\t\t\t\t}\n+#endif\n+\t\t\t\tif (byte_count == 0) {\n+\t\t\t\t\tep->dwc_ep.xfer_count =\n+\t\t\t\t\t    ep->dwc_ep.total_len;\n+\t\t\t\t\tis_last = 1;\n+\t\t\t\t} else {\n+\t\t\t\t\tDWC_WARN(\"Incomplete transfer\\n\");\n+\t\t\t\t}\n+\t\t\t}\n+\t\t} else {\n+\t\t\tif (deptsiz.b.xfersize == 0 && deptsiz.b.pktcnt == 0) {\n+\t\t\t\tDWC_DEBUGPL(DBG_PCDV,\n+\t\t\t\t\t    \"%d-%s len=%d  xfersize=%d pktcnt=%d\\n\",\n+\t\t\t\t\t    ep->dwc_ep.num,\n+\t\t\t\t\t    ep->dwc_ep.is_in ? \"IN\" : \"OUT\",\n+\t\t\t\t\t    ep->dwc_ep.xfer_len,\n+\t\t\t\t\t    deptsiz.b.xfersize,\n+\t\t\t\t\t    deptsiz.b.pktcnt);\n+\n+\t\t\t\t/*      Check if the whole transfer was completed,\n+\t\t\t\t *      if no, setup transfer for next portion of data\n+\t\t\t\t */\n+\t\t\t\tif (ep->dwc_ep.xfer_len < ep->dwc_ep.total_len) {\n+\t\t\t\t\tdwc_otg_ep_start_transfer(core_if,\n+\t\t\t\t\t\t\t\t  &ep->dwc_ep);\n+\t\t\t\t} else if (ep->dwc_ep.sent_zlp) {\n+\t\t\t\t\t/*\n+\t\t\t\t\t * This fragment of code should initiate 0\n+\t\t\t\t\t * length trasfer in case if it is queued\n+\t\t\t\t\t * a trasfer with size divisible to EPs max\n+\t\t\t\t\t * packet size and with usb_request zero field\n+\t\t\t\t\t * is set, which means that after data is transfered,\n+\t\t\t\t\t * it is also should be transfered\n+\t\t\t\t\t * a 0 length packet at the end. For Slave and\n+\t\t\t\t\t * Buffer DMA modes in this case SW has\n+\t\t\t\t\t * to initiate 2 transfers one with transfer size,\n+\t\t\t\t\t * and the second with 0 size. For Desriptor\n+\t\t\t\t\t * DMA mode SW is able to initiate a transfer,\n+\t\t\t\t\t * which will handle all the packets including\n+\t\t\t\t\t * the last  0 legth.\n+\t\t\t\t\t */\n+\t\t\t\t\tep->dwc_ep.sent_zlp = 0;\n+\t\t\t\t\tdwc_otg_ep_start_zl_transfer(core_if,\n+\t\t\t\t\t\t\t\t     &ep->dwc_ep);\n+\t\t\t\t} else {\n+\t\t\t\t\tis_last = 1;\n+\t\t\t\t}\n+\t\t\t} else {\n+\t\t\t\tDWC_WARN\n+\t\t\t\t    (\"Incomplete transfer (%d-%s [siz=%d pkt=%d])\\n\",\n+\t\t\t\t     ep->dwc_ep.num,\n+\t\t\t\t     (ep->dwc_ep.is_in ? \"IN\" : \"OUT\"),\n+\t\t\t\t     deptsiz.b.xfersize, deptsiz.b.pktcnt);\n+\t\t\t}\n+\t\t}\n+\t} else {\n+\t\tdwc_otg_dev_out_ep_regs_t *out_ep_regs =\n+\t\t    dev_if->out_ep_regs[ep->dwc_ep.num];\n+\t\tdesc_sts.d32 = 0;\n+\t\tif (core_if->dma_enable) {\n+\t\t\tif (core_if->dma_desc_enable) {\n+\t\t\t\tdma_desc = ep->dwc_ep.desc_addr;\n+\t\t\t\tbyte_count = 0;\n+\t\t\t\tep->dwc_ep.sent_zlp = 0;\n+\n+#ifdef DWC_UTE_CFI\n+\t\t\t\tCFI_INFO(\"%s: BUFFER_MODE=%d\\n\", __func__,\n+\t\t\t\t\t ep->dwc_ep.buff_mode);\n+\t\t\t\tif (ep->dwc_ep.buff_mode != BM_STANDARD) {\n+\t\t\t\t\tint residue;\n+\t\t\t\t\tresidue = cfi_calc_desc_residue(ep);\n+\t\t\t\t\tif (residue < 0)\n+\t\t\t\t\t\treturn;\n+\t\t\t\t\tbyte_count = residue;\n+\t\t\t\t} else {\n+#endif\n+\n+\t\t\t\t\tfor (i = 0; i < ep->dwc_ep.desc_cnt;\n+\t\t\t\t\t     ++i) {\n+\t\t\t\t\t\tdesc_sts = dma_desc->status;\n+\t\t\t\t\t\tbyte_count += desc_sts.b.bytes;\n+\t\t\t\t\t\tdma_desc++;\n+\t\t\t\t\t}\n+\n+#ifdef DWC_UTE_CFI\n+\t\t\t\t}\n+#endif\n+\t\t\t\t/* Checking for interrupt Out transfers with not\n+\t\t\t\t * dword aligned mps sizes\n+\t\t\t\t */\n+\t\t\t\tif (ep->dwc_ep.type == DWC_OTG_EP_TYPE_INTR &&\n+\t\t\t\t\t\t\t(ep->dwc_ep.maxpacket%4)) {\n+\t\t\t\t\tep->dwc_ep.xfer_count =\n+\t\t\t\t\t    ep->dwc_ep.total_len - byte_count;\n+\t\t\t\t\tif ((ep->dwc_ep.xfer_len %\n+\t\t\t\t\t     ep->dwc_ep.maxpacket)\n+\t\t\t\t\t    && (ep->dwc_ep.xfer_len /\n+\t\t\t\t\t\tep->dwc_ep.maxpacket <\n+\t\t\t\t\t\tMAX_DMA_DESC_CNT))\n+\t\t\t\t\t\tep->dwc_ep.xfer_len -=\n+\t\t\t\t\t\t    (ep->dwc_ep.desc_cnt -\n+\t\t\t\t\t\t     1) * ep->dwc_ep.maxpacket +\n+\t\t\t\t\t\t    ep->dwc_ep.xfer_len %\n+\t\t\t\t\t\t    ep->dwc_ep.maxpacket;\n+\t\t\t\t\telse\n+\t\t\t\t\t\tep->dwc_ep.xfer_len -=\n+\t\t\t\t\t\t    ep->dwc_ep.desc_cnt *\n+\t\t\t\t\t\t    ep->dwc_ep.maxpacket;\n+\t\t\t\t\tif (ep->dwc_ep.xfer_len > 0) {\n+\t\t\t\t\t\tdwc_otg_ep_start_transfer\n+\t\t\t\t\t\t    (core_if, &ep->dwc_ep);\n+\t\t\t\t\t} else {\n+\t\t\t\t\t\tis_last = 1;\n+\t\t\t\t\t}\n+\t\t\t\t} else {\n+\t\t\t\t\tep->dwc_ep.xfer_count =\n+\t\t\t\t\t    ep->dwc_ep.total_len - byte_count +\n+\t\t\t\t\t    ((4 -\n+\t\t\t\t\t      (ep->dwc_ep.\n+\t\t\t\t\t       total_len & 0x3)) & 0x3);\n+\t\t\t\t\tis_last = 1;\n+\t\t\t\t}\n+\t\t\t} else {\n+\t\t\t\tdeptsiz.d32 = 0;\n+\t\t\t\tdeptsiz.d32 =\n+\t\t\t\t    DWC_READ_REG32(&out_ep_regs->doeptsiz);\n+\n+\t\t\t\tbyte_count = (ep->dwc_ep.xfer_len -\n+\t\t\t\t\t      ep->dwc_ep.xfer_count -\n+\t\t\t\t\t      deptsiz.b.xfersize);\n+\t\t\t\tep->dwc_ep.xfer_buff += byte_count;\n+\t\t\t\tep->dwc_ep.dma_addr += byte_count;\n+\t\t\t\tep->dwc_ep.xfer_count += byte_count;\n+\n+\t\t\t\t/*      Check if the whole transfer was completed,\n+\t\t\t\t *      if no, setup transfer for next portion of data\n+\t\t\t\t */\n+\t\t\t\tif (ep->dwc_ep.xfer_len < ep->dwc_ep.total_len) {\n+\t\t\t\t\tdwc_otg_ep_start_transfer(core_if,\n+\t\t\t\t\t\t\t\t  &ep->dwc_ep);\n+\t\t\t\t} else if (ep->dwc_ep.sent_zlp) {\n+\t\t\t\t\t/*\n+\t\t\t\t\t * This fragment of code should initiate 0\n+\t\t\t\t\t * length trasfer in case if it is queued\n+\t\t\t\t\t * a trasfer with size divisible to EPs max\n+\t\t\t\t\t * packet size and with usb_request zero field\n+\t\t\t\t\t * is set, which means that after data is transfered,\n+\t\t\t\t\t * it is also should be transfered\n+\t\t\t\t\t * a 0 length packet at the end. For Slave and\n+\t\t\t\t\t * Buffer DMA modes in this case SW has\n+\t\t\t\t\t * to initiate 2 transfers one with transfer size,\n+\t\t\t\t\t * and the second with 0 size. For Desriptor\n+\t\t\t\t\t * DMA mode SW is able to initiate a transfer,\n+\t\t\t\t\t * which will handle all the packets including\n+\t\t\t\t\t * the last  0 legth.\n+\t\t\t\t\t */\n+\t\t\t\t\tep->dwc_ep.sent_zlp = 0;\n+\t\t\t\t\tdwc_otg_ep_start_zl_transfer(core_if,\n+\t\t\t\t\t\t\t\t     &ep->dwc_ep);\n+\t\t\t\t} else {\n+\t\t\t\t\tis_last = 1;\n+\t\t\t\t}\n+\t\t\t}\n+\t\t} else {\n+\t\t\t/*      Check if the whole transfer was completed,\n+\t\t\t *      if no, setup transfer for next portion of data\n+\t\t\t */\n+\t\t\tif (ep->dwc_ep.xfer_len < ep->dwc_ep.total_len) {\n+\t\t\t\tdwc_otg_ep_start_transfer(core_if, &ep->dwc_ep);\n+\t\t\t} else if (ep->dwc_ep.sent_zlp) {\n+\t\t\t\t/*\n+\t\t\t\t * This fragment of code should initiate 0\n+\t\t\t\t * length transfer in case if it is queued\n+\t\t\t\t * a transfer with size divisible to EPs max\n+\t\t\t\t * packet size and with usb_request zero field\n+\t\t\t\t * is set, which means that after data is transfered,\n+\t\t\t\t * it is also should be transfered\n+\t\t\t\t * a 0 length packet at the end. For Slave and\n+\t\t\t\t * Buffer DMA modes in this case SW has\n+\t\t\t\t * to initiate 2 transfers one with transfer size,\n+\t\t\t\t * and the second with 0 size. For Descriptor\n+\t\t\t\t * DMA mode SW is able to initiate a transfer,\n+\t\t\t\t * which will handle all the packets including\n+\t\t\t\t * the last  0 length.\n+\t\t\t\t */\n+\t\t\t\tep->dwc_ep.sent_zlp = 0;\n+\t\t\t\tdwc_otg_ep_start_zl_transfer(core_if,\n+\t\t\t\t\t\t\t     &ep->dwc_ep);\n+\t\t\t} else {\n+\t\t\t\tis_last = 1;\n+\t\t\t}\n+\t\t}\n+\n+\t\tDWC_DEBUGPL(DBG_PCDV,\n+\t\t\t    \"addr %p,\t %d-%s len=%d cnt=%d xsize=%d pktcnt=%d\\n\",\n+\t\t\t    &out_ep_regs->doeptsiz, ep->dwc_ep.num,\n+\t\t\t    ep->dwc_ep.is_in ? \"IN\" : \"OUT\",\n+\t\t\t    ep->dwc_ep.xfer_len, ep->dwc_ep.xfer_count,\n+\t\t\t    deptsiz.b.xfersize, deptsiz.b.pktcnt);\n+\t}\n+\n+\t/* Complete the request */\n+\tif (is_last) {\n+#ifdef DWC_UTE_CFI\n+\t\tif (ep->dwc_ep.buff_mode != BM_STANDARD) {\n+\t\t\treq->actual = ep->dwc_ep.cfi_req_len - byte_count;\n+\t\t} else {\n+#endif\n+\t\t\treq->actual = ep->dwc_ep.xfer_count;\n+#ifdef DWC_UTE_CFI\n+\t\t}\n+#endif\n+\t\tif (req->dw_align_buf) {\n+\t\t\tif (!ep->dwc_ep.is_in) {\n+\t\t\t\tdwc_memcpy(req->buf, req->dw_align_buf, req->length);\n+\t\t\t}\n+\t\t\tDWC_DMA_FREE(dev, req->length, req->dw_align_buf,\n+\t\t\t\t     req->dw_align_buf_dma);\n+\t\t}\n+\n+\t\tdwc_otg_request_done(ep, req, 0);\n+\n+\t\tep->dwc_ep.start_xfer_buff = 0;\n+\t\tep->dwc_ep.xfer_buff = 0;\n+\t\tep->dwc_ep.xfer_len = 0;\n+\n+\t\t/* If there is a request in the queue start it. */\n+\t\tstart_next_request(ep);\n+\t}\n+}\n+\n+#ifdef DWC_EN_ISOC\n+\n+/**\n+ * This function BNA interrupt for Isochronous EPs\n+ *\n+ */\n+static void dwc_otg_pcd_handle_iso_bna(dwc_otg_pcd_ep_t * ep)\n+{\n+\tdwc_ep_t *dwc_ep = &ep->dwc_ep;\n+\tvolatile uint32_t *addr;\n+\tdepctl_data_t depctl = {.d32 = 0 };\n+\tdwc_otg_pcd_t *pcd = ep->pcd;\n+\tdwc_otg_dev_dma_desc_t *dma_desc;\n+\tint i;\n+\n+\tdma_desc =\n+\t    dwc_ep->iso_desc_addr + dwc_ep->desc_cnt * (dwc_ep->proc_buf_num);\n+\n+\tif (dwc_ep->is_in) {\n+\t\tdev_dma_desc_sts_t sts = {.d32 = 0 };\n+\t\tfor (i = 0; i < dwc_ep->desc_cnt; ++i, ++dma_desc) {\n+\t\t\tsts.d32 = dma_desc->status.d32;\n+\t\t\tsts.b_iso_in.bs = BS_HOST_READY;\n+\t\t\tdma_desc->status.d32 = sts.d32;\n+\t\t}\n+\t} else {\n+\t\tdev_dma_desc_sts_t sts = {.d32 = 0 };\n+\t\tfor (i = 0; i < dwc_ep->desc_cnt; ++i, ++dma_desc) {\n+\t\t\tsts.d32 = dma_desc->status.d32;\n+\t\t\tsts.b_iso_out.bs = BS_HOST_READY;\n+\t\t\tdma_desc->status.d32 = sts.d32;\n+\t\t}\n+\t}\n+\n+\tif (dwc_ep->is_in == 0) {\n+\t\taddr =\n+\t\t    &GET_CORE_IF(pcd)->dev_if->out_ep_regs[dwc_ep->\n+\t\t\t\t\t\t\t   num]->doepctl;\n+\t} else {\n+\t\taddr =\n+\t\t    &GET_CORE_IF(pcd)->dev_if->in_ep_regs[dwc_ep->num]->diepctl;\n+\t}\n+\tdepctl.b.epena = 1;\n+\tDWC_MODIFY_REG32(addr, depctl.d32, depctl.d32);\n+}\n+\n+/**\n+ * This function sets latest iso packet information(non-PTI mode)\n+ *\n+ * @param core_if Programming view of DWC_otg controller.\n+ * @param ep The EP to start the transfer on.\n+ *\n+ */\n+void set_current_pkt_info(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)\n+{\n+\tdeptsiz_data_t deptsiz = {.d32 = 0 };\n+\tdma_addr_t dma_addr;\n+\tuint32_t offset;\n+\n+\tif (ep->proc_buf_num)\n+\t\tdma_addr = ep->dma_addr1;\n+\telse\n+\t\tdma_addr = ep->dma_addr0;\n+\n+\tif (ep->is_in) {\n+\t\tdeptsiz.d32 =\n+\t\t    DWC_READ_REG32(&core_if->dev_if->\n+\t\t\t\t   in_ep_regs[ep->num]->dieptsiz);\n+\t\toffset = ep->data_per_frame;\n+\t} else {\n+\t\tdeptsiz.d32 =\n+\t\t    DWC_READ_REG32(&core_if->dev_if->\n+\t\t\t\t   out_ep_regs[ep->num]->doeptsiz);\n+\t\toffset =\n+\t\t    ep->data_per_frame +\n+\t\t    (0x4 & (0x4 - (ep->data_per_frame & 0x3)));\n+\t}\n+\n+\tif (!deptsiz.b.xfersize) {\n+\t\tep->pkt_info[ep->cur_pkt].length = ep->data_per_frame;\n+\t\tep->pkt_info[ep->cur_pkt].offset =\n+\t\t    ep->cur_pkt_dma_addr - dma_addr;\n+\t\tep->pkt_info[ep->cur_pkt].status = 0;\n+\t} else {\n+\t\tep->pkt_info[ep->cur_pkt].length = ep->data_per_frame;\n+\t\tep->pkt_info[ep->cur_pkt].offset =\n+\t\t    ep->cur_pkt_dma_addr - dma_addr;\n+\t\tep->pkt_info[ep->cur_pkt].status = -DWC_E_NO_DATA;\n+\t}\n+\tep->cur_pkt_addr += offset;\n+\tep->cur_pkt_dma_addr += offset;\n+\tep->cur_pkt++;\n+}\n+\n+/**\n+ * This function sets latest iso packet information(DDMA mode)\n+ *\n+ * @param core_if Programming view of DWC_otg controller.\n+ * @param dwc_ep The EP to start the transfer on.\n+ *\n+ */\n+static void set_ddma_iso_pkts_info(dwc_otg_core_if_t * core_if,\n+\t\t\t\t   dwc_ep_t * dwc_ep)\n+{\n+\tdwc_otg_dev_dma_desc_t *dma_desc;\n+\tdev_dma_desc_sts_t sts = {.d32 = 0 };\n+\tiso_pkt_info_t *iso_packet;\n+\tuint32_t data_per_desc;\n+\tuint32_t offset;\n+\tint i, j;\n+\n+\tiso_packet = dwc_ep->pkt_info;\n+\n+\t/** Reinit closed DMA Descriptors*/\n+\t/** ISO OUT EP */\n+\tif (dwc_ep->is_in == 0) {\n+\t\tdma_desc =\n+\t\t    dwc_ep->iso_desc_addr +\n+\t\t    dwc_ep->desc_cnt * dwc_ep->proc_buf_num;\n+\t\toffset = 0;\n+\n+\t\tfor (i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm;\n+\t\t     i += dwc_ep->pkt_per_frm) {\n+\t\t\tfor (j = 0; j < dwc_ep->pkt_per_frm; ++j) {\n+\t\t\t\tdata_per_desc =\n+\t\t\t\t    ((j + 1) * dwc_ep->maxpacket >\n+\t\t\t\t     dwc_ep->\n+\t\t\t\t     data_per_frame) ? dwc_ep->data_per_frame -\n+\t\t\t\t    j * dwc_ep->maxpacket : dwc_ep->maxpacket;\n+\t\t\t\tdata_per_desc +=\n+\t\t\t\t    (data_per_desc % 4) ? (4 -\n+\t\t\t\t\t\t\t   data_per_desc %\n+\t\t\t\t\t\t\t   4) : 0;\n+\n+\t\t\t\tsts.d32 = dma_desc->status.d32;\n+\n+\t\t\t\t/* Write status in iso_packet_decsriptor  */\n+\t\t\t\tiso_packet->status =\n+\t\t\t\t    sts.b_iso_out.rxsts +\n+\t\t\t\t    (sts.b_iso_out.bs ^ BS_DMA_DONE);\n+\t\t\t\tif (iso_packet->status) {\n+\t\t\t\t\tiso_packet->status = -DWC_E_NO_DATA;\n+\t\t\t\t}\n+\n+\t\t\t\t/* Received data length */\n+\t\t\t\tif (!sts.b_iso_out.rxbytes) {\n+\t\t\t\t\tiso_packet->length =\n+\t\t\t\t\t    data_per_desc -\n+\t\t\t\t\t    sts.b_iso_out.rxbytes;\n+\t\t\t\t} else {\n+\t\t\t\t\tiso_packet->length =\n+\t\t\t\t\t    data_per_desc -\n+\t\t\t\t\t    sts.b_iso_out.rxbytes + (4 -\n+\t\t\t\t\t\t\t\t     dwc_ep->data_per_frame\n+\t\t\t\t\t\t\t\t     % 4);\n+\t\t\t\t}\n+\n+\t\t\t\tiso_packet->offset = offset;\n+\n+\t\t\t\toffset += data_per_desc;\n+\t\t\t\tdma_desc++;\n+\t\t\t\tiso_packet++;\n+\t\t\t}\n+\t\t}\n+\n+\t\tfor (j = 0; j < dwc_ep->pkt_per_frm - 1; ++j) {\n+\t\t\tdata_per_desc =\n+\t\t\t    ((j + 1) * dwc_ep->maxpacket >\n+\t\t\t     dwc_ep->data_per_frame) ? dwc_ep->data_per_frame -\n+\t\t\t    j * dwc_ep->maxpacket : dwc_ep->maxpacket;\n+\t\t\tdata_per_desc +=\n+\t\t\t    (data_per_desc % 4) ? (4 - data_per_desc % 4) : 0;\n+\n+\t\t\tsts.d32 = dma_desc->status.d32;\n+\n+\t\t\t/* Write status in iso_packet_decsriptor  */\n+\t\t\tiso_packet->status =\n+\t\t\t    sts.b_iso_out.rxsts +\n+\t\t\t    (sts.b_iso_out.bs ^ BS_DMA_DONE);\n+\t\t\tif (iso_packet->status) {\n+\t\t\t\tiso_packet->status = -DWC_E_NO_DATA;\n+\t\t\t}\n+\n+\t\t\t/* Received data length */\n+\t\t\tiso_packet->length =\n+\t\t\t    dwc_ep->data_per_frame - sts.b_iso_out.rxbytes;\n+\n+\t\t\tiso_packet->offset = offset;\n+\n+\t\t\toffset += data_per_desc;\n+\t\t\tiso_packet++;\n+\t\t\tdma_desc++;\n+\t\t}\n+\n+\t\tsts.d32 = dma_desc->status.d32;\n+\n+\t\t/* Write status in iso_packet_decsriptor  */\n+\t\tiso_packet->status =\n+\t\t    sts.b_iso_out.rxsts + (sts.b_iso_out.bs ^ BS_DMA_DONE);\n+\t\tif (iso_packet->status) {\n+\t\t\tiso_packet->status = -DWC_E_NO_DATA;\n+\t\t}\n+\t\t/* Received data length */\n+\t\tif (!sts.b_iso_out.rxbytes) {\n+\t\t\tiso_packet->length =\n+\t\t\t    dwc_ep->data_per_frame - sts.b_iso_out.rxbytes;\n+\t\t} else {\n+\t\t\tiso_packet->length =\n+\t\t\t    dwc_ep->data_per_frame - sts.b_iso_out.rxbytes +\n+\t\t\t    (4 - dwc_ep->data_per_frame % 4);\n+\t\t}\n+\n+\t\tiso_packet->offset = offset;\n+\t} else {\n+/** ISO IN EP */\n+\n+\t\tdma_desc =\n+\t\t    dwc_ep->iso_desc_addr +\n+\t\t    dwc_ep->desc_cnt * dwc_ep->proc_buf_num;\n+\n+\t\tfor (i = 0; i < dwc_ep->desc_cnt - 1; i++) {\n+\t\t\tsts.d32 = dma_desc->status.d32;\n+\n+\t\t\t/* Write status in iso packet descriptor */\n+\t\t\tiso_packet->status =\n+\t\t\t    sts.b_iso_in.txsts +\n+\t\t\t    (sts.b_iso_in.bs ^ BS_DMA_DONE);\n+\t\t\tif (iso_packet->status != 0) {\n+\t\t\t\tiso_packet->status = -DWC_E_NO_DATA;\n+\n+\t\t\t}\n+\t\t\t/* Bytes has been transfered */\n+\t\t\tiso_packet->length =\n+\t\t\t    dwc_ep->data_per_frame - sts.b_iso_in.txbytes;\n+\n+\t\t\tdma_desc++;\n+\t\t\tiso_packet++;\n+\t\t}\n+\n+\t\tsts.d32 = dma_desc->status.d32;\n+\t\twhile (sts.b_iso_in.bs == BS_DMA_BUSY) {\n+\t\t\tsts.d32 = dma_desc->status.d32;\n+\t\t}\n+\n+\t\t/* Write status in iso packet descriptor ??? do be done with ERROR codes */\n+\t\tiso_packet->status =\n+\t\t    sts.b_iso_in.txsts + (sts.b_iso_in.bs ^ BS_DMA_DONE);\n+\t\tif (iso_packet->status != 0) {\n+\t\t\tiso_packet->status = -DWC_E_NO_DATA;\n+\t\t}\n+\n+\t\t/* Bytes has been transfered */\n+\t\tiso_packet->length =\n+\t\t    dwc_ep->data_per_frame - sts.b_iso_in.txbytes;\n+\t}\n+}\n+\n+/**\n+ * This function reinitialize DMA Descriptors for Isochronous transfer\n+ *\n+ * @param core_if Programming view of DWC_otg controller.\n+ * @param dwc_ep The EP to start the transfer on.\n+ *\n+ */\n+static void reinit_ddma_iso_xfer(dwc_otg_core_if_t * core_if, dwc_ep_t * dwc_ep)\n+{\n+\tint i, j;\n+\tdwc_otg_dev_dma_desc_t *dma_desc;\n+\tdma_addr_t dma_ad;\n+\tvolatile uint32_t *addr;\n+\tdev_dma_desc_sts_t sts = {.d32 = 0 };\n+\tuint32_t data_per_desc;\n+\n+\tif (dwc_ep->is_in == 0) {\n+\t\taddr = &core_if->dev_if->out_ep_regs[dwc_ep->num]->doepctl;\n+\t} else {\n+\t\taddr = &core_if->dev_if->in_ep_regs[dwc_ep->num]->diepctl;\n+\t}\n+\n+\tif (dwc_ep->proc_buf_num == 0) {\n+\t\t/** Buffer 0 descriptors setup */\n+\t\tdma_ad = dwc_ep->dma_addr0;\n+\t} else {\n+\t\t/** Buffer 1 descriptors setup */\n+\t\tdma_ad = dwc_ep->dma_addr1;\n+\t}\n+\n+\t/** Reinit closed DMA Descriptors*/\n+\t/** ISO OUT EP */\n+\tif (dwc_ep->is_in == 0) {\n+\t\tdma_desc =\n+\t\t    dwc_ep->iso_desc_addr +\n+\t\t    dwc_ep->desc_cnt * dwc_ep->proc_buf_num;\n+\n+\t\tsts.b_iso_out.bs = BS_HOST_READY;\n+\t\tsts.b_iso_out.rxsts = 0;\n+\t\tsts.b_iso_out.l = 0;\n+\t\tsts.b_iso_out.sp = 0;\n+\t\tsts.b_iso_out.ioc = 0;\n+\t\tsts.b_iso_out.pid = 0;\n+\t\tsts.b_iso_out.framenum = 0;\n+\n+\t\tfor (i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm;\n+\t\t     i += dwc_ep->pkt_per_frm) {\n+\t\t\tfor (j = 0; j < dwc_ep->pkt_per_frm; ++j) {\n+\t\t\t\tdata_per_desc =\n+\t\t\t\t    ((j + 1) * dwc_ep->maxpacket >\n+\t\t\t\t     dwc_ep->\n+\t\t\t\t     data_per_frame) ? dwc_ep->data_per_frame -\n+\t\t\t\t    j * dwc_ep->maxpacket : dwc_ep->maxpacket;\n+\t\t\t\tdata_per_desc +=\n+\t\t\t\t    (data_per_desc % 4) ? (4 -\n+\t\t\t\t\t\t\t   data_per_desc %\n+\t\t\t\t\t\t\t   4) : 0;\n+\t\t\t\tsts.b_iso_out.rxbytes = data_per_desc;\n+\t\t\t\tdma_desc->buf = dma_ad;\n+\t\t\t\tdma_desc->status.d32 = sts.d32;\n+\n+\t\t\t\tdma_ad += data_per_desc;\n+\t\t\t\tdma_desc++;\n+\t\t\t}\n+\t\t}\n+\n+\t\tfor (j = 0; j < dwc_ep->pkt_per_frm - 1; ++j) {\n+\n+\t\t\tdata_per_desc =\n+\t\t\t    ((j + 1) * dwc_ep->maxpacket >\n+\t\t\t     dwc_ep->data_per_frame) ? dwc_ep->data_per_frame -\n+\t\t\t    j * dwc_ep->maxpacket : dwc_ep->maxpacket;\n+\t\t\tdata_per_desc +=\n+\t\t\t    (data_per_desc % 4) ? (4 - data_per_desc % 4) : 0;\n+\t\t\tsts.b_iso_out.rxbytes = data_per_desc;\n+\n+\t\t\tdma_desc->buf = dma_ad;\n+\t\t\tdma_desc->status.d32 = sts.d32;\n+\n+\t\t\tdma_desc++;\n+\t\t\tdma_ad += data_per_desc;\n+\t\t}\n+\n+\t\tsts.b_iso_out.ioc = 1;\n+\t\tsts.b_iso_out.l = dwc_ep->proc_buf_num;\n+\n+\t\tdata_per_desc =\n+\t\t    ((j + 1) * dwc_ep->maxpacket >\n+\t\t     dwc_ep->data_per_frame) ? dwc_ep->data_per_frame -\n+\t\t    j * dwc_ep->maxpacket : dwc_ep->maxpacket;\n+\t\tdata_per_desc +=\n+\t\t    (data_per_desc % 4) ? (4 - data_per_desc % 4) : 0;\n+\t\tsts.b_iso_out.rxbytes = data_per_desc;\n+\n+\t\tdma_desc->buf = dma_ad;\n+\t\tdma_desc->status.d32 = sts.d32;\n+\t} else {\n+/** ISO IN EP */\n+\n+\t\tdma_desc =\n+\t\t    dwc_ep->iso_desc_addr +\n+\t\t    dwc_ep->desc_cnt * dwc_ep->proc_buf_num;\n+\n+\t\tsts.b_iso_in.bs = BS_HOST_READY;\n+\t\tsts.b_iso_in.txsts = 0;\n+\t\tsts.b_iso_in.sp = 0;\n+\t\tsts.b_iso_in.ioc = 0;\n+\t\tsts.b_iso_in.pid = dwc_ep->pkt_per_frm;\n+\t\tsts.b_iso_in.framenum = dwc_ep->next_frame;\n+\t\tsts.b_iso_in.txbytes = dwc_ep->data_per_frame;\n+\t\tsts.b_iso_in.l = 0;\n+\n+\t\tfor (i = 0; i < dwc_ep->desc_cnt - 1; i++) {\n+\t\t\tdma_desc->buf = dma_ad;\n+\t\t\tdma_desc->status.d32 = sts.d32;\n+\n+\t\t\tsts.b_iso_in.framenum += dwc_ep->bInterval;\n+\t\t\tdma_ad += dwc_ep->data_per_frame;\n+\t\t\tdma_desc++;\n+\t\t}\n+\n+\t\tsts.b_iso_in.ioc = 1;\n+\t\tsts.b_iso_in.l = dwc_ep->proc_buf_num;\n+\n+\t\tdma_desc->buf = dma_ad;\n+\t\tdma_desc->status.d32 = sts.d32;\n+\n+\t\tdwc_ep->next_frame =\n+\t\t    sts.b_iso_in.framenum + dwc_ep->bInterval * 1;\n+\t}\n+\tdwc_ep->proc_buf_num = (dwc_ep->proc_buf_num ^ 1) & 0x1;\n+}\n+\n+/**\n+ * This function is to handle Iso EP transfer complete interrupt\n+ * in case Iso out packet was dropped\n+ *\n+ * @param core_if Programming view of DWC_otg controller.\n+ * @param dwc_ep The EP for wihich transfer complete was asserted\n+ *\n+ */\n+static uint32_t handle_iso_out_pkt_dropped(dwc_otg_core_if_t * core_if,\n+\t\t\t\t\t   dwc_ep_t * dwc_ep)\n+{\n+\tuint32_t dma_addr;\n+\tuint32_t drp_pkt;\n+\tuint32_t drp_pkt_cnt;\n+\tdeptsiz_data_t deptsiz = {.d32 = 0 };\n+\tdepctl_data_t depctl = {.d32 = 0 };\n+\tint i;\n+\n+\tdeptsiz.d32 =\n+\t    DWC_READ_REG32(&core_if->dev_if->\n+\t\t\t   out_ep_regs[dwc_ep->num]->doeptsiz);\n+\n+\tdrp_pkt = dwc_ep->pkt_cnt - deptsiz.b.pktcnt;\n+\tdrp_pkt_cnt = dwc_ep->pkt_per_frm - (drp_pkt % dwc_ep->pkt_per_frm);\n+\n+\t/* Setting dropped packets status */\n+\tfor (i = 0; i < drp_pkt_cnt; ++i) {\n+\t\tdwc_ep->pkt_info[drp_pkt].status = -DWC_E_NO_DATA;\n+\t\tdrp_pkt++;\n+\t\tdeptsiz.b.pktcnt--;\n+\t}\n+\n+\tif (deptsiz.b.pktcnt > 0) {\n+\t\tdeptsiz.b.xfersize =\n+\t\t    dwc_ep->xfer_len - (dwc_ep->pkt_cnt -\n+\t\t\t\t\tdeptsiz.b.pktcnt) * dwc_ep->maxpacket;\n+\t} else {\n+\t\tdeptsiz.b.xfersize = 0;\n+\t\tdeptsiz.b.pktcnt = 0;\n+\t}\n+\n+\tDWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->doeptsiz,\n+\t\t\tdeptsiz.d32);\n+\n+\tif (deptsiz.b.pktcnt > 0) {\n+\t\tif (dwc_ep->proc_buf_num) {\n+\t\t\tdma_addr =\n+\t\t\t    dwc_ep->dma_addr1 + dwc_ep->xfer_len -\n+\t\t\t    deptsiz.b.xfersize;\n+\t\t} else {\n+\t\t\tdma_addr =\n+\t\t\t    dwc_ep->dma_addr0 + dwc_ep->xfer_len -\n+\t\t\t    deptsiz.b.xfersize;;\n+\t\t}\n+\n+\t\tDWC_WRITE_REG32(&core_if->dev_if->\n+\t\t\t\tout_ep_regs[dwc_ep->num]->doepdma, dma_addr);\n+\n+\t\t/** Re-enable endpoint, clear nak  */\n+\t\tdepctl.d32 = 0;\n+\t\tdepctl.b.epena = 1;\n+\t\tdepctl.b.cnak = 1;\n+\n+\t\tDWC_MODIFY_REG32(&core_if->dev_if->\n+\t\t\t\t out_ep_regs[dwc_ep->num]->doepctl, depctl.d32,\n+\t\t\t\t depctl.d32);\n+\t\treturn 0;\n+\t} else {\n+\t\treturn 1;\n+\t}\n+}\n+\n+/**\n+ * This function sets iso packets information(PTI mode)\n+ *\n+ * @param core_if Programming view of DWC_otg controller.\n+ * @param ep The EP to start the transfer on.\n+ *\n+ */\n+static uint32_t set_iso_pkts_info(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)\n+{\n+\tint i, j;\n+\tdma_addr_t dma_ad;\n+\tiso_pkt_info_t *packet_info = ep->pkt_info;\n+\tuint32_t offset;\n+\tuint32_t frame_data;\n+\tdeptsiz_data_t deptsiz;\n+\n+\tif (ep->proc_buf_num == 0) {\n+\t\t/** Buffer 0 descriptors setup */\n+\t\tdma_ad = ep->dma_addr0;\n+\t} else {\n+\t\t/** Buffer 1 descriptors setup */\n+\t\tdma_ad = ep->dma_addr1;\n+\t}\n+\n+\tif (ep->is_in) {\n+\t\tdeptsiz.d32 =\n+\t\t    DWC_READ_REG32(&core_if->dev_if->in_ep_regs[ep->num]->\n+\t\t\t\t   dieptsiz);\n+\t} else {\n+\t\tdeptsiz.d32 =\n+\t\t    DWC_READ_REG32(&core_if->dev_if->out_ep_regs[ep->num]->\n+\t\t\t\t   doeptsiz);\n+\t}\n+\n+\tif (!deptsiz.b.xfersize) {\n+\t\toffset = 0;\n+\t\tfor (i = 0; i < ep->pkt_cnt; i += ep->pkt_per_frm) {\n+\t\t\tframe_data = ep->data_per_frame;\n+\t\t\tfor (j = 0; j < ep->pkt_per_frm; ++j) {\n+\n+\t\t\t\t/* Packet status - is not set as initially\n+\t\t\t\t * it is set to 0 and if packet was sent\n+\t\t\t\t successfully, status field will remain 0*/\n+\n+\t\t\t\t/* Bytes has been transfered */\n+\t\t\t\tpacket_info->length =\n+\t\t\t\t    (ep->maxpacket <\n+\t\t\t\t     frame_data) ? ep->maxpacket : frame_data;\n+\n+\t\t\t\t/* Received packet offset */\n+\t\t\t\tpacket_info->offset = offset;\n+\t\t\t\toffset += packet_info->length;\n+\t\t\t\tframe_data -= packet_info->length;\n+\n+\t\t\t\tpacket_info++;\n+\t\t\t}\n+\t\t}\n+\t\treturn 1;\n+\t} else {\n+\t\t/* This is a workaround for in case of Transfer Complete with\n+\t\t * PktDrpSts interrupts merging - in this case Transfer complete\n+\t\t * interrupt for Isoc Out Endpoint is asserted without PktDrpSts\n+\t\t * set and with DOEPTSIZ register non zero. Investigations showed,\n+\t\t * that this happens when Out packet is dropped, but because of\n+\t\t * interrupts merging during first interrupt handling PktDrpSts\n+\t\t * bit is cleared and for next merged interrupts it is not reset.\n+\t\t * In this case SW hadles the interrupt as if PktDrpSts bit is set.\n+\t\t */\n+\t\tif (ep->is_in) {\n+\t\t\treturn 1;\n+\t\t} else {\n+\t\t\treturn handle_iso_out_pkt_dropped(core_if, ep);\n+\t\t}\n+\t}\n+}\n+\n+/**\n+ * This function is to handle Iso EP transfer complete interrupt\n+ *\n+ * @param pcd The PCD\n+ * @param ep The EP for which transfer complete was asserted\n+ *\n+ */\n+static void complete_iso_ep(dwc_otg_pcd_t * pcd, dwc_otg_pcd_ep_t * ep)\n+{\n+\tdwc_otg_core_if_t *core_if = GET_CORE_IF(ep->pcd);\n+\tdwc_ep_t *dwc_ep = &ep->dwc_ep;\n+\tuint8_t is_last = 0;\n+\n+\tif (ep->dwc_ep.next_frame == 0xffffffff) {\n+\t\tDWC_WARN(\"Next frame is not set!\\n\");\n+\t\treturn;\n+\t}\n+\n+\tif (core_if->dma_enable) {\n+\t\tif (core_if->dma_desc_enable) {\n+\t\t\tset_ddma_iso_pkts_info(core_if, dwc_ep);\n+\t\t\treinit_ddma_iso_xfer(core_if, dwc_ep);\n+\t\t\tis_last = 1;\n+\t\t} else {\n+\t\t\tif (core_if->pti_enh_enable) {\n+\t\t\t\tif (set_iso_pkts_info(core_if, dwc_ep)) {\n+\t\t\t\t\tdwc_ep->proc_buf_num =\n+\t\t\t\t\t    (dwc_ep->proc_buf_num ^ 1) & 0x1;\n+\t\t\t\t\tdwc_otg_iso_ep_start_buf_transfer\n+\t\t\t\t\t    (core_if, dwc_ep);\n+\t\t\t\t\tis_last = 1;\n+\t\t\t\t}\n+\t\t\t} else {\n+\t\t\t\tset_current_pkt_info(core_if, dwc_ep);\n+\t\t\t\tif (dwc_ep->cur_pkt >= dwc_ep->pkt_cnt) {\n+\t\t\t\t\tis_last = 1;\n+\t\t\t\t\tdwc_ep->cur_pkt = 0;\n+\t\t\t\t\tdwc_ep->proc_buf_num =\n+\t\t\t\t\t    (dwc_ep->proc_buf_num ^ 1) & 0x1;\n+\t\t\t\t\tif (dwc_ep->proc_buf_num) {\n+\t\t\t\t\t\tdwc_ep->cur_pkt_addr =\n+\t\t\t\t\t\t    dwc_ep->xfer_buff1;\n+\t\t\t\t\t\tdwc_ep->cur_pkt_dma_addr =\n+\t\t\t\t\t\t    dwc_ep->dma_addr1;\n+\t\t\t\t\t} else {\n+\t\t\t\t\t\tdwc_ep->cur_pkt_addr =\n+\t\t\t\t\t\t    dwc_ep->xfer_buff0;\n+\t\t\t\t\t\tdwc_ep->cur_pkt_dma_addr =\n+\t\t\t\t\t\t    dwc_ep->dma_addr0;\n+\t\t\t\t\t}\n+\n+\t\t\t\t}\n+\t\t\t\tdwc_otg_iso_ep_start_frm_transfer(core_if,\n+\t\t\t\t\t\t\t\t  dwc_ep);\n+\t\t\t}\n+\t\t}\n+\t} else {\n+\t\tset_current_pkt_info(core_if, dwc_ep);\n+\t\tif (dwc_ep->cur_pkt >= dwc_ep->pkt_cnt) {\n+\t\t\tis_last = 1;\n+\t\t\tdwc_ep->cur_pkt = 0;\n+\t\t\tdwc_ep->proc_buf_num = (dwc_ep->proc_buf_num ^ 1) & 0x1;\n+\t\t\tif (dwc_ep->proc_buf_num) {\n+\t\t\t\tdwc_ep->cur_pkt_addr = dwc_ep->xfer_buff1;\n+\t\t\t\tdwc_ep->cur_pkt_dma_addr = dwc_ep->dma_addr1;\n+\t\t\t} else {\n+\t\t\t\tdwc_ep->cur_pkt_addr = dwc_ep->xfer_buff0;\n+\t\t\t\tdwc_ep->cur_pkt_dma_addr = dwc_ep->dma_addr0;\n+\t\t\t}\n+\n+\t\t}\n+\t\tdwc_otg_iso_ep_start_frm_transfer(core_if, dwc_ep);\n+\t}\n+\tif (is_last)\n+\t\tdwc_otg_iso_buffer_done(pcd, ep, ep->iso_req_handle);\n+}\n+#endif /* DWC_EN_ISOC */\n+\n+/**\n+ * This function handle BNA interrupt for Non Isochronous EPs\n+ *\n+ */\n+static void dwc_otg_pcd_handle_noniso_bna(dwc_otg_pcd_ep_t * ep)\n+{\n+\tdwc_ep_t *dwc_ep = &ep->dwc_ep;\n+\tvolatile uint32_t *addr;\n+\tdepctl_data_t depctl = {.d32 = 0 };\n+\tdwc_otg_pcd_t *pcd = ep->pcd;\n+\tdwc_otg_dev_dma_desc_t *dma_desc;\n+\tdev_dma_desc_sts_t sts = {.d32 = 0 };\n+\tdwc_otg_core_if_t *core_if = ep->pcd->core_if;\n+\tint i, start;\n+\n+\tif (!dwc_ep->desc_cnt)\n+\t\tDWC_WARN(\"Ep%d %s Descriptor count = %d \\n\", dwc_ep->num,\n+\t\t\t (dwc_ep->is_in ? \"IN\" : \"OUT\"), dwc_ep->desc_cnt);\n+\n+\tif (core_if->core_params->cont_on_bna && !dwc_ep->is_in\n+\t\t\t\t\t\t\t&& dwc_ep->type != DWC_OTG_EP_TYPE_CONTROL) {\n+\t\tuint32_t doepdma;\n+\t\tdwc_otg_dev_out_ep_regs_t *out_regs =\n+\t\t\tcore_if->dev_if->out_ep_regs[dwc_ep->num];\n+\t\tdoepdma = DWC_READ_REG32(&(out_regs->doepdma));\n+\t\tstart = (doepdma - dwc_ep->dma_desc_addr)/sizeof(dwc_otg_dev_dma_desc_t);\n+\t\tdma_desc = &(dwc_ep->desc_addr[start]);\n+\t} else {\n+\t\tstart = 0;\n+\t\tdma_desc = dwc_ep->desc_addr;\n+\t}\n+\n+\n+\tfor (i = start; i < dwc_ep->desc_cnt; ++i, ++dma_desc) {\n+\t\tsts.d32 = dma_desc->status.d32;\n+\t\tsts.b.bs = BS_HOST_READY;\n+\t\tdma_desc->status.d32 = sts.d32;\n+\t}\n+\n+\tif (dwc_ep->is_in == 0) {\n+\t\taddr =\n+\t\t    &GET_CORE_IF(pcd)->dev_if->out_ep_regs[dwc_ep->num]->\n+\t\t    doepctl;\n+\t} else {\n+\t\taddr =\n+\t\t    &GET_CORE_IF(pcd)->dev_if->in_ep_regs[dwc_ep->num]->diepctl;\n+\t}\n+\tdepctl.b.epena = 1;\n+\tdepctl.b.cnak = 1;\n+\tDWC_MODIFY_REG32(addr, 0, depctl.d32);\n+}\n+\n+/**\n+ * This function handles EP0 Control transfers.\n+ *\n+ * The state of the control transfers are tracked in\n+ * <code>ep0state</code>.\n+ */\n+static void handle_ep0(dwc_otg_pcd_t * pcd)\n+{\n+\tdwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);\n+\tdwc_otg_pcd_ep_t *ep0 = &pcd->ep0;\n+\tdev_dma_desc_sts_t desc_sts;\n+\tdeptsiz0_data_t deptsiz;\n+\tuint32_t byte_count;\n+\n+#ifdef DEBUG_EP0\n+\tDWC_DEBUGPL(DBG_PCDV, \"%s()\\n\", __func__);\n+\tprint_ep0_state(pcd);\n+#endif\n+\n+//      DWC_PRINTF(\"HANDLE EP0\\n\");\n+\n+\tswitch (pcd->ep0state) {\n+\tcase EP0_DISCONNECT:\n+\t\tbreak;\n+\n+\tcase EP0_IDLE:\n+\t\tpcd->request_config = 0;\n+\n+\t\tpcd_setup(pcd);\n+\t\tbreak;\n+\n+\tcase EP0_IN_DATA_PHASE:\n+#ifdef DEBUG_EP0\n+\t\tDWC_DEBUGPL(DBG_PCD, \"DATA_IN EP%d-%s: type=%d, mps=%d\\n\",\n+\t\t\t    ep0->dwc_ep.num, (ep0->dwc_ep.is_in ? \"IN\" : \"OUT\"),\n+\t\t\t    ep0->dwc_ep.type, ep0->dwc_ep.maxpacket);\n+#endif\n+\n+\t\tif (core_if->dma_enable != 0) {\n+\t\t\t/*\n+\t\t\t * For EP0 we can only program 1 packet at a time so we\n+\t\t\t * need to do the make calculations after each complete.\n+\t\t\t * Call write_packet to make the calculations, as in\n+\t\t\t * slave mode, and use those values to determine if we\n+\t\t\t * can complete.\n+\t\t\t */\n+\t\t\tif (core_if->dma_desc_enable == 0) {\n+\t\t\t\tdeptsiz.d32 =\n+\t\t\t\t    DWC_READ_REG32(&core_if->\n+\t\t\t\t\t\t   dev_if->in_ep_regs[0]->\n+\t\t\t\t\t\t   dieptsiz);\n+\t\t\t\tbyte_count =\n+\t\t\t\t    ep0->dwc_ep.xfer_len - deptsiz.b.xfersize;\n+\t\t\t} else {\n+\t\t\t\tdesc_sts =\n+\t\t\t\t    core_if->dev_if->in_desc_addr->status;\n+\t\t\t\tbyte_count =\n+\t\t\t\t    ep0->dwc_ep.xfer_len - desc_sts.b.bytes;\n+\t\t\t}\n+\t\t\tep0->dwc_ep.xfer_count += byte_count;\n+\t\t\tep0->dwc_ep.xfer_buff += byte_count;\n+\t\t\tep0->dwc_ep.dma_addr += byte_count;\n+\t\t}\n+\t\tif (ep0->dwc_ep.xfer_count < ep0->dwc_ep.total_len) {\n+\t\t\tdwc_otg_ep0_continue_transfer(GET_CORE_IF(pcd),\n+\t\t\t\t\t\t      &ep0->dwc_ep);\n+\t\t\tDWC_DEBUGPL(DBG_PCD, \"CONTINUE TRANSFER\\n\");\n+\t\t} else if (ep0->dwc_ep.sent_zlp) {\n+\t\t\tdwc_otg_ep0_continue_transfer(GET_CORE_IF(pcd),\n+\t\t\t\t\t\t      &ep0->dwc_ep);\n+\t\t\tep0->dwc_ep.sent_zlp = 0;\n+\t\t\tDWC_DEBUGPL(DBG_PCD, \"CONTINUE TRANSFER sent zlp\\n\");\n+\t\t} else {\n+\t\t\tep0_complete_request(ep0);\n+\t\t\tDWC_DEBUGPL(DBG_PCD, \"COMPLETE TRANSFER\\n\");\n+\t\t}\n+\t\tbreak;\n+\tcase EP0_OUT_DATA_PHASE:\n+#ifdef DEBUG_EP0\n+\t\tDWC_DEBUGPL(DBG_PCD, \"DATA_OUT EP%d-%s: type=%d, mps=%d\\n\",\n+\t\t\t    ep0->dwc_ep.num, (ep0->dwc_ep.is_in ? \"IN\" : \"OUT\"),\n+\t\t\t    ep0->dwc_ep.type, ep0->dwc_ep.maxpacket);\n+#endif\n+\t\tif (core_if->dma_enable != 0) {\n+\t\t\tif (core_if->dma_desc_enable == 0) {\n+\t\t\t\tdeptsiz.d32 =\n+\t\t\t\t    DWC_READ_REG32(&core_if->\n+\t\t\t\t\t\t   dev_if->out_ep_regs[0]->\n+\t\t\t\t\t\t   doeptsiz);\n+\t\t\t\tbyte_count =\n+\t\t\t\t    ep0->dwc_ep.maxpacket - deptsiz.b.xfersize;\n+\t\t\t} else {\n+\t\t\t\tdesc_sts =\n+\t\t\t\t    core_if->dev_if->out_desc_addr->status;\n+\t\t\t\tbyte_count =\n+\t\t\t\t    ep0->dwc_ep.maxpacket - desc_sts.b.bytes;\n+\t\t\t}\n+\t\t\tep0->dwc_ep.xfer_count += byte_count;\n+\t\t\tep0->dwc_ep.xfer_buff += byte_count;\n+\t\t\tep0->dwc_ep.dma_addr += byte_count;\n+\t\t}\n+\t\tif (ep0->dwc_ep.xfer_count < ep0->dwc_ep.total_len) {\n+\t\t\tdwc_otg_ep0_continue_transfer(GET_CORE_IF(pcd),\n+\t\t\t\t\t\t      &ep0->dwc_ep);\n+\t\t\tDWC_DEBUGPL(DBG_PCD, \"CONTINUE TRANSFER\\n\");\n+\t\t} else if (ep0->dwc_ep.sent_zlp) {\n+\t\t\tdwc_otg_ep0_continue_transfer(GET_CORE_IF(pcd),\n+\t\t\t\t\t\t      &ep0->dwc_ep);\n+\t\t\tep0->dwc_ep.sent_zlp = 0;\n+\t\t\tDWC_DEBUGPL(DBG_PCD, \"CONTINUE TRANSFER sent zlp\\n\");\n+\t\t} else {\n+\t\t\tep0_complete_request(ep0);\n+\t\t\tDWC_DEBUGPL(DBG_PCD, \"COMPLETE TRANSFER\\n\");\n+\t\t}\n+\t\tbreak;\n+\n+\tcase EP0_IN_STATUS_PHASE:\n+\tcase EP0_OUT_STATUS_PHASE:\n+\t\tDWC_DEBUGPL(DBG_PCD, \"CASE: EP0_STATUS\\n\");\n+\t\tep0_complete_request(ep0);\n+\t\tpcd->ep0state = EP0_IDLE;\n+\t\tep0->stopped = 1;\n+\t\tep0->dwc_ep.is_in = 0;\t/* OUT for next SETUP */\n+\n+\t\t/* Prepare for more SETUP Packets */\n+\t\tif (core_if->dma_enable) {\n+\t\t\tep0_out_start(core_if, pcd);\n+\t\t}\n+\t\tbreak;\n+\n+\tcase EP0_STALL:\n+\t\tDWC_ERROR(\"EP0 STALLed, should not get here pcd_setup()\\n\");\n+\t\tbreak;\n+\t}\n+#ifdef DEBUG_EP0\n+\tprint_ep0_state(pcd);\n+#endif\n+}\n+\n+/**\n+ * Restart transfer\n+ */\n+static void restart_transfer(dwc_otg_pcd_t * pcd, const uint32_t epnum)\n+{\n+\tdwc_otg_core_if_t *core_if;\n+\tdwc_otg_dev_if_t *dev_if;\n+\tdeptsiz_data_t dieptsiz = {.d32 = 0 };\n+\tdwc_otg_pcd_ep_t *ep;\n+\n+\tep = get_in_ep(pcd, epnum);\n+\n+#ifdef DWC_EN_ISOC\n+\tif (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) {\n+\t\treturn;\n+\t}\n+#endif /* DWC_EN_ISOC  */\n+\n+\tcore_if = GET_CORE_IF(pcd);\n+\tdev_if = core_if->dev_if;\n+\n+\tdieptsiz.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dieptsiz);\n+\n+\tDWC_DEBUGPL(DBG_PCD, \"xfer_buff=%p xfer_count=%0x xfer_len=%0x\"\n+\t\t    \" stopped=%d\\n\", ep->dwc_ep.xfer_buff,\n+\t\t    ep->dwc_ep.xfer_count, ep->dwc_ep.xfer_len, ep->stopped);\n+\t/*\n+\t * If xfersize is 0 and pktcnt in not 0, resend the last packet.\n+\t */\n+\tif (dieptsiz.b.pktcnt && dieptsiz.b.xfersize == 0 &&\n+\t    ep->dwc_ep.start_xfer_buff != 0) {\n+\t\tif (ep->dwc_ep.total_len <= ep->dwc_ep.maxpacket) {\n+\t\t\tep->dwc_ep.xfer_count = 0;\n+\t\t\tep->dwc_ep.xfer_buff = ep->dwc_ep.start_xfer_buff;\n+\t\t\tep->dwc_ep.xfer_len = ep->dwc_ep.xfer_count;\n+\t\t} else {\n+\t\t\tep->dwc_ep.xfer_count -= ep->dwc_ep.maxpacket;\n+\t\t\t/* convert packet size to dwords. */\n+\t\t\tep->dwc_ep.xfer_buff -= ep->dwc_ep.maxpacket;\n+\t\t\tep->dwc_ep.xfer_len = ep->dwc_ep.xfer_count;\n+\t\t}\n+\t\tep->stopped = 0;\n+\t\tDWC_DEBUGPL(DBG_PCD, \"xfer_buff=%p xfer_count=%0x \"\n+\t\t\t    \"xfer_len=%0x stopped=%d\\n\",\n+\t\t\t    ep->dwc_ep.xfer_buff,\n+\t\t\t    ep->dwc_ep.xfer_count, ep->dwc_ep.xfer_len,\n+\t\t\t    ep->stopped);\n+\t\tif (epnum == 0) {\n+\t\t\tdwc_otg_ep0_start_transfer(core_if, &ep->dwc_ep);\n+\t\t} else {\n+\t\t\tdwc_otg_ep_start_transfer(core_if, &ep->dwc_ep);\n+\t\t}\n+\t}\n+}\n+\n+/*\n+ * This function create new nextep sequnce based on Learn Queue.\n+ *\n+ * @param core_if Programming view of DWC_otg controller\n+ */\n+void predict_nextep_seq( dwc_otg_core_if_t * core_if)\n+{\n+\tdwc_otg_device_global_regs_t *dev_global_regs =\n+\t    core_if->dev_if->dev_global_regs;\n+\tconst uint32_t TOKEN_Q_DEPTH = core_if->hwcfg2.b.dev_token_q_depth;\n+\t/* Number of Token Queue Registers */\n+\tconst int DTKNQ_REG_CNT = (TOKEN_Q_DEPTH + 7) / 8;\n+\tdtknq1_data_t dtknqr1;\n+\tuint32_t in_tkn_epnums[4];\n+\tuint8_t seqnum[MAX_EPS_CHANNELS];\n+\tuint8_t intkn_seq[TOKEN_Q_DEPTH];\n+\tgrstctl_t resetctl = {.d32 = 0 };\n+\tuint8_t temp;\n+\tint ndx = 0;\n+\tint start = 0;\n+\tint end = 0;\n+\tint sort_done = 0;\n+\tint i = 0;\n+\tvolatile uint32_t *addr = &dev_global_regs->dtknqr1;\n+\n+\n+\tDWC_DEBUGPL(DBG_PCD,\"dev_token_q_depth=%d\\n\",TOKEN_Q_DEPTH);\n+\n+\t/* Read the DTKNQ Registers */\n+\tfor (i = 0; i < DTKNQ_REG_CNT; i++) {\n+\t\tin_tkn_epnums[i] = DWC_READ_REG32(addr);\n+\t\tDWC_DEBUGPL(DBG_PCDV, \"DTKNQR%d=0x%08x\\n\", i + 1,\n+\t\t\t    in_tkn_epnums[i]);\n+\t\tif (addr == &dev_global_regs->dvbusdis) {\n+\t\t\taddr = &dev_global_regs->dtknqr3_dthrctl;\n+\t\t} else {\n+\t\t\t++addr;\n+\t\t}\n+\n+\t}\n+\n+\t/* Copy the DTKNQR1 data to the bit field. */\n+\tdtknqr1.d32 = in_tkn_epnums[0];\n+\tif (dtknqr1.b.wrap_bit) {\n+\t\tndx = dtknqr1.b.intknwptr;\n+\t\tend = ndx -1;\n+\t\tif (end < 0)\n+\t\t\tend = TOKEN_Q_DEPTH -1;\n+\t} else {\n+\t\tndx = 0;\n+\t\tend = dtknqr1.b.intknwptr -1;\n+\t\tif (end < 0)\n+\t\t\tend = 0;\n+\t}\n+\tstart = ndx;\n+\n+\t/* Fill seqnum[] by initial values: EP number + 31 */\n+\tfor (i=0; i <= core_if->dev_if->num_in_eps; i++) {\n+\t\tseqnum[i] = i +31;\n+\t}\n+\n+\t/* Fill intkn_seq[] from in_tkn_epnums[0] */\n+\tfor (i=0; i < 6; i++)\n+\t\tintkn_seq[i] = (in_tkn_epnums[0] >> ((7-i) * 4)) & 0xf;\n+\n+\tif (TOKEN_Q_DEPTH > 6) {\n+\t\t/* Fill intkn_seq[] from in_tkn_epnums[1] */\n+\t\tfor (i=6; i < 14; i++)\n+\t\t\tintkn_seq[i] =\n+\t\t\t    (in_tkn_epnums[1] >> ((7 - (i - 6)) * 4)) & 0xf;\n+\t}\n+\n+\tif (TOKEN_Q_DEPTH > 14) {\n+\t\t/* Fill intkn_seq[] from in_tkn_epnums[1] */\n+\t\tfor (i=14; i < 22; i++)\n+\t\t\tintkn_seq[i] =\n+\t\t\t    (in_tkn_epnums[2] >> ((7 - (i - 14)) * 4)) & 0xf;\n+\t}\n+\n+\tif (TOKEN_Q_DEPTH > 22) {\n+\t\t/* Fill intkn_seq[] from in_tkn_epnums[1] */\n+\t\tfor (i=22; i < 30; i++)\n+\t\t\tintkn_seq[i] =\n+\t\t\t    (in_tkn_epnums[3] >> ((7 - (i - 22)) * 4)) & 0xf;\n+\t}\n+\n+\tDWC_DEBUGPL(DBG_PCDV, \"%s start=%d end=%d intkn_seq[]:\\n\", __func__,\n+\t\t    start, end);\n+\tfor (i=0; i<TOKEN_Q_DEPTH; i++)\n+\t\tDWC_DEBUGPL(DBG_PCDV,\"%d\\n\", intkn_seq[i]);\n+\n+\t/* Update seqnum based on intkn_seq[] */\n+\ti = 0;\n+\tdo {\n+\t\tseqnum[intkn_seq[ndx]] = i;\n+\t\tndx++;\n+\t\ti++;\n+\t\tif (ndx == TOKEN_Q_DEPTH)\n+\t\t\tndx = 0;\n+\t} while ( i < TOKEN_Q_DEPTH );\n+\n+\t/* Mark non active EP's in seqnum[] by 0xff */\n+\tfor (i=0; i<=core_if->dev_if->num_in_eps; i++) {\n+\t\tif (core_if->nextep_seq[i] == 0xff )\n+\t\t\tseqnum[i] = 0xff;\n+\t}\n+\n+\t/* Sort seqnum[] */\n+\tsort_done = 0;\n+\twhile (!sort_done) {\n+\t\tsort_done = 1;\n+\t\tfor (i=0; i<core_if->dev_if->num_in_eps; i++) {\n+\t\t\tif (seqnum[i] > seqnum[i+1]) {\n+\t\t\t\ttemp = seqnum[i];\n+\t\t\t\tseqnum[i] = seqnum[i+1];\n+\t\t\t\tseqnum[i+1] = temp;\n+\t\t\t\tsort_done = 0;\n+\t\t\t}\n+\t\t}\n+\t}\n+\n+\tndx = start + seqnum[0];\n+\tif (ndx >= TOKEN_Q_DEPTH)\n+\t\tndx = ndx % TOKEN_Q_DEPTH;\n+\tcore_if->first_in_nextep_seq = intkn_seq[ndx];\n+\n+\t/* Update seqnum[] by EP numbers  */\n+\tfor (i=0; i<=core_if->dev_if->num_in_eps; i++) {\n+\t\tndx = start + i;\n+\t\tif (seqnum[i] < 31) {\n+\t\t\tndx = start + seqnum[i];\n+\t\t\tif (ndx >= TOKEN_Q_DEPTH)\n+\t\t\t\tndx = ndx % TOKEN_Q_DEPTH;\n+\t\t\tseqnum[i] = intkn_seq[ndx];\n+\t\t} else {\n+\t\t\tif (seqnum[i] < 0xff) {\n+\t\t\t\tseqnum[i] = seqnum[i] - 31;\n+\t\t\t} else {\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t}\n+\t}\n+\n+\t/* Update nextep_seq[] based on seqnum[] */\n+\tfor (i=0; i<core_if->dev_if->num_in_eps; i++) {\n+\t\tif (seqnum[i] != 0xff) {\n+\t\t\tif (seqnum[i+1] != 0xff) {\n+\t\t\t\tcore_if->nextep_seq[seqnum[i]] = seqnum[i+1];\n+\t\t\t} else {\n+\t\t\t\tcore_if->nextep_seq[seqnum[i]] = core_if->first_in_nextep_seq;\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t} else {\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\n+\tDWC_DEBUGPL(DBG_PCDV, \"%s first_in_nextep_seq= %2d; nextep_seq[]:\\n\",\n+\t\t__func__, core_if->first_in_nextep_seq);\n+\tfor (i=0; i <= core_if->dev_if->num_in_eps; i++) {\n+\t\tDWC_DEBUGPL(DBG_PCDV,\"%2d\\n\", core_if->nextep_seq[i]);\n+\t}\n+\n+\t/* Flush the Learning Queue */\n+\tresetctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->grstctl);\n+\tresetctl.b.intknqflsh = 1;\n+\tDWC_WRITE_REG32(&core_if->core_global_regs->grstctl, resetctl.d32);\n+\n+\n+}\n+\n+/**\n+ * handle the IN EP disable interrupt.\n+ */\n+static inline void handle_in_ep_disable_intr(dwc_otg_pcd_t * pcd,\n+\t\t\t\t\t     const uint32_t epnum)\n+{\n+\tdwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);\n+\tdwc_otg_dev_if_t *dev_if = core_if->dev_if;\n+\tdeptsiz_data_t dieptsiz = {.d32 = 0 };\n+\tdctl_data_t dctl = {.d32 = 0 };\n+\tdwc_otg_pcd_ep_t *ep;\n+\tdwc_ep_t *dwc_ep;\n+\tgintmsk_data_t gintmsk_data;\n+\tdepctl_data_t depctl;\n+\tuint32_t diepdma;\n+\tuint32_t remain_to_transfer = 0;\n+\tuint8_t i;\n+\tuint32_t xfer_size;\n+\n+\tep = get_in_ep(pcd, epnum);\n+\tdwc_ep = &ep->dwc_ep;\n+\n+\tif (dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {\n+\t\tdwc_otg_flush_tx_fifo(core_if, dwc_ep->tx_fifo_num);\n+\t\tcomplete_ep(ep);\n+\t\treturn;\n+\t}\n+\n+\tDWC_DEBUGPL(DBG_PCD, \"diepctl%d=%0x\\n\", epnum,\n+\t\t    DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->diepctl));\n+\tdieptsiz.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dieptsiz);\n+\tdepctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->diepctl);\n+\n+\tDWC_DEBUGPL(DBG_ANY, \"pktcnt=%d size=%d\\n\",\n+\t\t    dieptsiz.b.pktcnt, dieptsiz.b.xfersize);\n+\n+\tif ((core_if->start_predict == 0) || (depctl.b.eptype & 1)) {\n+\t\tif (ep->stopped) {\n+\t\t\tif (core_if->en_multiple_tx_fifo)\n+\t\t\t\t/* Flush the Tx FIFO */\n+\t\t\t\tdwc_otg_flush_tx_fifo(core_if, dwc_ep->tx_fifo_num);\n+\t\t\t/* Clear the Global IN NP NAK */\n+\t\t\tdctl.d32 = 0;\n+\t\t\tdctl.b.cgnpinnak = 1;\n+\t\t\tDWC_MODIFY_REG32(&dev_if->dev_global_regs->dctl, dctl.d32, dctl.d32);\n+\t\t\t/* Restart the transaction */\n+\t\t\tif (dieptsiz.b.pktcnt != 0 || dieptsiz.b.xfersize != 0) {\n+\t\t\t\trestart_transfer(pcd, epnum);\n+\t\t\t}\n+\t\t} else {\n+\t\t\t/* Restart the transaction */\n+\t\t\tif (dieptsiz.b.pktcnt != 0 || dieptsiz.b.xfersize != 0) {\n+\t\t\t\trestart_transfer(pcd, epnum);\n+\t\t\t}\n+\t\t\tDWC_DEBUGPL(DBG_ANY, \"STOPPED!!!\\n\");\n+\t\t}\n+\t\treturn;\n+\t}\n+\n+\tif (core_if->start_predict > 2) {\t// NP IN EP\n+\t\tcore_if->start_predict--;\n+\t\treturn;\n+\t}\n+\n+\tcore_if->start_predict--;\n+\n+\tif (core_if->start_predict == 1) {\t// All NP IN Ep's disabled now\n+\n+\t\tpredict_nextep_seq(core_if);\n+\n+\t\t/* Update all active IN EP's NextEP field based of nextep_seq[] */\n+\t\tfor ( i = 0; i <= core_if->dev_if->num_in_eps; i++) {\n+\t\t\tdepctl.d32 =\n+\t\t\t    DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl);\n+\t\t\tif (core_if->nextep_seq[i] != 0xff) {\t// Active NP IN EP\n+\t\t\t\tdepctl.b.nextep = core_if->nextep_seq[i];\n+\t\t\t\tDWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepctl, depctl.d32);\n+\t\t\t}\n+\t\t}\n+\t\t/* Flush Shared NP TxFIFO */\n+\t\tdwc_otg_flush_tx_fifo(core_if, 0);\n+\t\t/* Rewind buffers */\n+\t\tif (!core_if->dma_desc_enable) {\n+\t\t\ti = core_if->first_in_nextep_seq;\n+\t\t\tdo {\n+\t\t\t\tep = get_in_ep(pcd, i);\n+\t\t\t\tdieptsiz.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->dieptsiz);\n+\t\t\t\txfer_size = ep->dwc_ep.total_len - ep->dwc_ep.xfer_count;\n+\t\t\t\tif (xfer_size > ep->dwc_ep.maxxfer)\n+\t\t\t\t\txfer_size = ep->dwc_ep.maxxfer;\n+\t\t\t\tdepctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl);\n+\t\t\t\tif (dieptsiz.b.pktcnt != 0) {\n+\t\t\t\t\tif (xfer_size == 0) {\n+\t\t\t\t\t\tremain_to_transfer = 0;\n+\t\t\t\t\t} else {\n+\t\t\t\t\t\tif ((xfer_size % ep->dwc_ep.maxpacket) == 0) {\n+\t\t\t\t\t\t\tremain_to_transfer =\n+\t\t\t\t\t\t\t\tdieptsiz.b.pktcnt * ep->dwc_ep.maxpacket;\n+\t\t\t\t\t\t} else {\n+\t\t\t\t\t\t\tremain_to_transfer = ((dieptsiz.b.pktcnt -1) * ep->dwc_ep.maxpacket)\n+\t\t\t\t\t\t\t\t+ (xfer_size % ep->dwc_ep.maxpacket);\n+\t\t\t\t\t\t}\n+\t\t\t\t\t}\n+\t\t\t\t\tdiepdma = DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepdma);\n+\t\t\t\t\tdieptsiz.b.xfersize = remain_to_transfer;\n+\t\t\t\t\tDWC_WRITE_REG32(&dev_if->in_ep_regs[i]->dieptsiz, dieptsiz.d32);\n+\t\t\t\t\tdiepdma = ep->dwc_ep.dma_addr + (xfer_size - remain_to_transfer);\n+\t\t\t\t\tDWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepdma, diepdma);\n+\t\t\t\t}\n+\t\t\t\ti = core_if->nextep_seq[i];\n+\t\t\t} while (i != core_if->first_in_nextep_seq);\n+\t\t} else { // dma_desc_enable\n+\t\t\t\tDWC_PRINTF(\"%s Learning Queue not supported in DDMA\\n\", __func__);\n+\t\t}\n+\n+\t\t/* Restart transfers in predicted sequences */\n+\t\ti = core_if->first_in_nextep_seq;\n+\t\tdo {\n+\t\t\tdieptsiz.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->dieptsiz);\n+\t\t\tdepctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl);\n+\t\t\tif (dieptsiz.b.pktcnt != 0) {\n+\t\t\t\tdepctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl);\n+\t\t\t\tdepctl.b.epena = 1;\n+\t\t\t\tdepctl.b.cnak = 1;\n+\t\t\t\tDWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepctl, depctl.d32);\n+\t\t\t}\n+\t\t\ti = core_if->nextep_seq[i];\n+\t\t} while (i != core_if->first_in_nextep_seq);\n+\n+\t\t/* Clear the global non-periodic IN NAK handshake */\n+\t\tdctl.d32 = 0;\n+\t\tdctl.b.cgnpinnak = 1;\n+\t\tDWC_MODIFY_REG32(&dev_if->dev_global_regs->dctl, dctl.d32, dctl.d32);\n+\n+\t\t/* Unmask EP Mismatch interrupt */\n+\t\tgintmsk_data.d32 = 0;\n+\t\tgintmsk_data.b.epmismatch = 1;\n+\t\tDWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, 0, gintmsk_data.d32);\n+\n+\t\tcore_if->start_predict = 0;\n+\n+\t}\n+}\n+\n+/**\n+ * Handler for the IN EP timeout handshake interrupt.\n+ */\n+static inline void handle_in_ep_timeout_intr(dwc_otg_pcd_t * pcd,\n+\t\t\t\t\t     const uint32_t epnum)\n+{\n+\tdwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);\n+\tdwc_otg_dev_if_t *dev_if = core_if->dev_if;\n+\n+#ifdef DEBUG\n+\tdeptsiz_data_t dieptsiz = {.d32 = 0 };\n+\tuint32_t num = 0;\n+#endif\n+\tdctl_data_t dctl = {.d32 = 0 };\n+\tdwc_otg_pcd_ep_t *ep;\n+\n+\tgintmsk_data_t intr_mask = {.d32 = 0 };\n+\n+\tep = get_in_ep(pcd, epnum);\n+\n+\t/* Disable the NP Tx Fifo Empty Interrrupt */\n+\tif (!core_if->dma_enable) {\n+\t\tintr_mask.b.nptxfempty = 1;\n+\t\tDWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk,\n+\t\t\t\t intr_mask.d32, 0);\n+\t}\n+\t/** @todo NGS Check EP type.\n+\t * Implement for Periodic EPs */\n+\t/*\n+\t * Non-periodic EP\n+\t */\n+\t/* Enable the Global IN NAK Effective Interrupt */\n+\tintr_mask.b.ginnakeff = 1;\n+\tDWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, 0, intr_mask.d32);\n+\n+\t/* Set Global IN NAK */\n+\tdctl.b.sgnpinnak = 1;\n+\tDWC_MODIFY_REG32(&dev_if->dev_global_regs->dctl, dctl.d32, dctl.d32);\n+\n+\tep->stopped = 1;\n+\n+#ifdef DEBUG\n+\tdieptsiz.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[num]->dieptsiz);\n+\tDWC_DEBUGPL(DBG_ANY, \"pktcnt=%d size=%d\\n\",\n+\t\t    dieptsiz.b.pktcnt, dieptsiz.b.xfersize);\n+#endif\n+\n+#ifdef DISABLE_PERIODIC_EP\n+\t/*\n+\t * Set the NAK bit for this EP to\n+\t * start the disable process.\n+\t */\n+\tdiepctl.d32 = 0;\n+\tdiepctl.b.snak = 1;\n+\tDWC_MODIFY_REG32(&dev_if->in_ep_regs[num]->diepctl, diepctl.d32,\n+\t\t\t diepctl.d32);\n+\tep->disabling = 1;\n+\tep->stopped = 1;\n+#endif\n+}\n+\n+/**\n+ * Handler for the IN EP NAK interrupt.\n+ */\n+static inline int32_t handle_in_ep_nak_intr(dwc_otg_pcd_t * pcd,\n+\t\t\t\t\t    const uint32_t epnum)\n+{\n+\t/** @todo implement ISR */\n+\tdwc_otg_core_if_t *core_if;\n+\tdiepmsk_data_t intr_mask = {.d32 = 0 };\n+\n+\tDWC_PRINTF(\"INTERRUPT Handler not implemented for %s\\n\", \"IN EP NAK\");\n+\tcore_if = GET_CORE_IF(pcd);\n+\tintr_mask.b.nak = 1;\n+\n+\tif (core_if->multiproc_int_enable) {\n+\t\tDWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->\n+\t\t\t\t diepeachintmsk[epnum], intr_mask.d32, 0);\n+\t} else {\n+\t\tDWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->diepmsk,\n+\t\t\t\t intr_mask.d32, 0);\n+\t}\n+\n+\treturn 1;\n+}\n+\n+/**\n+ * Handler for the OUT EP Babble interrupt.\n+ */\n+static inline int32_t handle_out_ep_babble_intr(dwc_otg_pcd_t * pcd,\n+\t\t\t\t\t\tconst uint32_t epnum)\n+{\n+\t/** @todo implement ISR */\n+\tdwc_otg_core_if_t *core_if;\n+\tdoepmsk_data_t intr_mask = {.d32 = 0 };\n+\n+\tDWC_PRINTF(\"INTERRUPT Handler not implemented for %s\\n\",\n+\t\t   \"OUT EP Babble\");\n+\tcore_if = GET_CORE_IF(pcd);\n+\tintr_mask.b.babble = 1;\n+\n+\tif (core_if->multiproc_int_enable) {\n+\t\tDWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->\n+\t\t\t\t doepeachintmsk[epnum], intr_mask.d32, 0);\n+\t} else {\n+\t\tDWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->doepmsk,\n+\t\t\t\t intr_mask.d32, 0);\n+\t}\n+\n+\treturn 1;\n+}\n+\n+/**\n+ * Handler for the OUT EP NAK interrupt.\n+ */\n+static inline int32_t handle_out_ep_nak_intr(dwc_otg_pcd_t * pcd,\n+\t\t\t\t\t     const uint32_t epnum)\n+{\n+\t/** @todo implement ISR */\n+\tdwc_otg_core_if_t *core_if;\n+\tdoepmsk_data_t intr_mask = {.d32 = 0 };\n+\n+\tDWC_DEBUGPL(DBG_ANY, \"INTERRUPT Handler not implemented for %s\\n\", \"OUT EP NAK\");\n+\tcore_if = GET_CORE_IF(pcd);\n+\tintr_mask.b.nak = 1;\n+\n+\tif (core_if->multiproc_int_enable) {\n+\t\tDWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->\n+\t\t\t\t doepeachintmsk[epnum], intr_mask.d32, 0);\n+\t} else {\n+\t\tDWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->doepmsk,\n+\t\t\t\t intr_mask.d32, 0);\n+\t}\n+\n+\treturn 1;\n+}\n+\n+/**\n+ * Handler for the OUT EP NYET interrupt.\n+ */\n+static inline int32_t handle_out_ep_nyet_intr(dwc_otg_pcd_t * pcd,\n+\t\t\t\t\t      const uint32_t epnum)\n+{\n+\t/** @todo implement ISR */\n+\tdwc_otg_core_if_t *core_if;\n+\tdoepmsk_data_t intr_mask = {.d32 = 0 };\n+\n+\tDWC_PRINTF(\"INTERRUPT Handler not implemented for %s\\n\", \"OUT EP NYET\");\n+\tcore_if = GET_CORE_IF(pcd);\n+\tintr_mask.b.nyet = 1;\n+\n+\tif (core_if->multiproc_int_enable) {\n+\t\tDWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->\n+\t\t\t\t doepeachintmsk[epnum], intr_mask.d32, 0);\n+\t} else {\n+\t\tDWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->doepmsk,\n+\t\t\t\t intr_mask.d32, 0);\n+\t}\n+\n+\treturn 1;\n+}\n+\n+/**\n+ * This interrupt indicates that an IN EP has a pending Interrupt.\n+ * The sequence for handling the IN EP interrupt is shown below:\n+ * -#\tRead the Device All Endpoint Interrupt register\n+ * -#\tRepeat the following for each IN EP interrupt bit set (from\n+ *\t\tLSB to MSB).\n+ * -#\tRead the Device Endpoint Interrupt (DIEPINTn) register\n+ * -#\tIf \"Transfer Complete\" call the request complete function\n+ * -#\tIf \"Endpoint Disabled\" complete the EP disable procedure.\n+ * -#\tIf \"AHB Error Interrupt\" log error\n+ * -#\tIf \"Time-out Handshake\" log error\n+ * -#\tIf \"IN Token Received when TxFIFO Empty\" write packet to Tx\n+ *\t\tFIFO.\n+ * -#\tIf \"IN Token EP Mismatch\" (disable, this is handled by EP\n+ *\t\tMismatch Interrupt)\n+ */\n+static int32_t dwc_otg_pcd_handle_in_ep_intr(dwc_otg_pcd_t * pcd)\n+{\n+#define CLEAR_IN_EP_INTR(__core_if,__epnum,__intr) \\\n+do { \\\n+\t\tdiepint_data_t diepint = {.d32=0}; \\\n+\t\tdiepint.b.__intr = 1; \\\n+\t\tDWC_WRITE_REG32(&__core_if->dev_if->in_ep_regs[__epnum]->diepint, \\\n+\t\tdiepint.d32); \\\n+} while (0)\n+\n+\tdwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);\n+\tdwc_otg_dev_if_t *dev_if = core_if->dev_if;\n+\tdiepint_data_t diepint = {.d32 = 0 };\n+\tdepctl_data_t depctl = {.d32 = 0 };\n+\tuint32_t ep_intr;\n+\tuint32_t epnum = 0;\n+\tdwc_otg_pcd_ep_t *ep;\n+\tdwc_ep_t *dwc_ep;\n+\tgintmsk_data_t intr_mask = {.d32 = 0 };\n+\n+\tDWC_DEBUGPL(DBG_PCDV, \"%s(%p)\\n\", __func__, pcd);\n+\n+\t/* Read in the device interrupt bits */\n+\tep_intr = dwc_otg_read_dev_all_in_ep_intr(core_if);\n+\n+\t/* Service the Device IN interrupts for each endpoint */\n+\twhile (ep_intr) {\n+\t\tif (ep_intr & 0x1) {\n+\t\t\tuint32_t empty_msk;\n+\t\t\t/* Get EP pointer */\n+\t\t\tep = get_in_ep(pcd, epnum);\n+\t\t\tdwc_ep = &ep->dwc_ep;\n+\n+\t\t\tdepctl.d32 =\n+\t\t\t    DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->diepctl);\n+\t\t\tempty_msk =\n+\t\t\t    DWC_READ_REG32(&dev_if->\n+\t\t\t\t\t   dev_global_regs->dtknqr4_fifoemptymsk);\n+\n+\t\t\tDWC_DEBUGPL(DBG_PCDV,\n+\t\t\t\t    \"IN EP INTERRUPT - %d\\nepmty_msk - %8x  diepctl - %8x\\n\",\n+\t\t\t\t    epnum, empty_msk, depctl.d32);\n+\n+\t\t\tDWC_DEBUGPL(DBG_PCD,\n+\t\t\t\t    \"EP%d-%s: type=%d, mps=%d\\n\",\n+\t\t\t\t    dwc_ep->num, (dwc_ep->is_in ? \"IN\" : \"OUT\"),\n+\t\t\t\t    dwc_ep->type, dwc_ep->maxpacket);\n+\n+\t\t\tdiepint.d32 =\n+\t\t\t    dwc_otg_read_dev_in_ep_intr(core_if, dwc_ep);\n+\n+\t\t\tDWC_DEBUGPL(DBG_PCDV,\n+\t\t\t\t    \"EP %d Interrupt Register - 0x%x\\n\", epnum,\n+\t\t\t\t    diepint.d32);\n+\t\t\t/* Transfer complete */\n+\t\t\tif (diepint.b.xfercompl) {\n+\t\t\t\t/* Disable the NP Tx FIFO Empty\n+\t\t\t\t * Interrupt */\n+\t\t\t\tif (core_if->en_multiple_tx_fifo == 0) {\n+\t\t\t\t\tintr_mask.b.nptxfempty = 1;\n+\t\t\t\t\tDWC_MODIFY_REG32\n+\t\t\t\t\t    (&core_if->core_global_regs->gintmsk,\n+\t\t\t\t\t     intr_mask.d32, 0);\n+\t\t\t\t} else {\n+\t\t\t\t\t/* Disable the Tx FIFO Empty Interrupt for this EP */\n+\t\t\t\t\tuint32_t fifoemptymsk =\n+\t\t\t\t\t    0x1 << dwc_ep->num;\n+\t\t\t\t\tDWC_MODIFY_REG32(&core_if->\n+\t\t\t\t\t\t\t dev_if->dev_global_regs->dtknqr4_fifoemptymsk,\n+\t\t\t\t\t\t\t fifoemptymsk, 0);\n+\t\t\t\t}\n+\t\t\t\t/* Clear the bit in DIEPINTn for this interrupt */\n+\t\t\t\tCLEAR_IN_EP_INTR(core_if, epnum, xfercompl);\n+\n+\t\t\t\t/* Complete the transfer */\n+\t\t\t\tif (epnum == 0) {\n+\t\t\t\t\thandle_ep0(pcd);\n+\t\t\t\t}\n+#ifdef DWC_EN_ISOC\n+\t\t\t\telse if (dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {\n+\t\t\t\t\tif (!ep->stopped)\n+\t\t\t\t\t\tcomplete_iso_ep(pcd, ep);\n+\t\t\t\t}\n+#endif /* DWC_EN_ISOC */\n+#ifdef DWC_UTE_PER_IO\n+\t\t\t\telse if (dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {\n+\t\t\t\t\tif (!ep->stopped)\n+\t\t\t\t\t\tcomplete_xiso_ep(ep);\n+\t\t\t\t}\n+#endif /* DWC_UTE_PER_IO */\n+\t\t\t\telse {\n+\t\t\t\t\tif (dwc_ep->type == DWC_OTG_EP_TYPE_ISOC &&\n+\t\t\t\t\t\t\tdwc_ep->bInterval > 1) {\n+\t\t\t\t\t\tdwc_ep->frame_num += dwc_ep->bInterval;\n+\t\t\t\t\t\tif (dwc_ep->frame_num > 0x3FFF)\n+\t\t\t\t\t\t{\n+\t\t\t\t\t\t\tdwc_ep->frm_overrun = 1;\n+\t\t\t\t\t\t\tdwc_ep->frame_num &= 0x3FFF;\n+\t\t\t\t\t\t} else\n+\t\t\t\t\t\t\tdwc_ep->frm_overrun = 0;\n+\t\t\t\t\t}\n+\t\t\t\t\tcomplete_ep(ep);\n+\t\t\t\t\tif(diepint.b.nak)\n+\t\t\t\t\t\tCLEAR_IN_EP_INTR(core_if, epnum, nak);\n+\t\t\t\t}\n+\t\t\t}\n+\t\t\t/* Endpoint disable      */\n+\t\t\tif (diepint.b.epdisabled) {\n+\t\t\t\tDWC_DEBUGPL(DBG_ANY, \"EP%d IN disabled\\n\",\n+\t\t\t\t\t    epnum);\n+\t\t\t\thandle_in_ep_disable_intr(pcd, epnum);\n+\n+\t\t\t\t/* Clear the bit in DIEPINTn for this interrupt */\n+\t\t\t\tCLEAR_IN_EP_INTR(core_if, epnum, epdisabled);\n+\t\t\t}\n+\t\t\t/* AHB Error */\n+\t\t\tif (diepint.b.ahberr) {\n+\t\t\t\tDWC_ERROR(\"EP%d IN AHB Error\\n\", epnum);\n+\t\t\t\t/* Clear the bit in DIEPINTn for this interrupt */\n+\t\t\t\tCLEAR_IN_EP_INTR(core_if, epnum, ahberr);\n+\t\t\t}\n+\t\t\t/* TimeOUT Handshake (non-ISOC IN EPs) */\n+\t\t\tif (diepint.b.timeout) {\n+\t\t\t\tDWC_ERROR(\"EP%d IN Time-out\\n\", epnum);\n+\t\t\t\thandle_in_ep_timeout_intr(pcd, epnum);\n+\n+\t\t\t\tCLEAR_IN_EP_INTR(core_if, epnum, timeout);\n+\t\t\t}\n+\t\t\t/** IN Token received with TxF Empty */\n+\t\t\tif (diepint.b.intktxfemp) {\n+\t\t\t\tDWC_DEBUGPL(DBG_ANY,\n+\t\t\t\t\t    \"EP%d IN TKN TxFifo Empty\\n\",\n+\t\t\t\t\t    epnum);\n+\t\t\t\tif (!ep->stopped && epnum != 0) {\n+\n+\t\t\t\t\tdiepmsk_data_t diepmsk = {.d32 = 0 };\n+\t\t\t\t\tdiepmsk.b.intktxfemp = 1;\n+\n+\t\t\t\t\tif (core_if->multiproc_int_enable) {\n+\t\t\t\t\t\tDWC_MODIFY_REG32\n+\t\t\t\t\t\t    (&dev_if->dev_global_regs->diepeachintmsk\n+\t\t\t\t\t\t     [epnum], diepmsk.d32, 0);\n+\t\t\t\t\t} else {\n+\t\t\t\t\t\tDWC_MODIFY_REG32\n+\t\t\t\t\t\t    (&dev_if->dev_global_regs->diepmsk,\n+\t\t\t\t\t\t     diepmsk.d32, 0);\n+\t\t\t\t\t}\n+\t\t\t\t} else if (core_if->dma_desc_enable\n+\t\t\t\t\t   && epnum == 0\n+\t\t\t\t\t   && pcd->ep0state ==\n+\t\t\t\t\t   EP0_OUT_STATUS_PHASE) {\n+\t\t\t\t\t// EP0 IN set STALL\n+\t\t\t\t\tdepctl.d32 =\n+\t\t\t\t\t    DWC_READ_REG32(&dev_if->in_ep_regs\n+\t\t\t\t\t\t\t   [epnum]->diepctl);\n+\n+\t\t\t\t\t/* set the disable and stall bits */\n+\t\t\t\t\tif (depctl.b.epena) {\n+\t\t\t\t\t\tdepctl.b.epdis = 1;\n+\t\t\t\t\t}\n+\t\t\t\t\tdepctl.b.stall = 1;\n+\t\t\t\t\tDWC_WRITE_REG32(&dev_if->in_ep_regs\n+\t\t\t\t\t\t\t[epnum]->diepctl,\n+\t\t\t\t\t\t\tdepctl.d32);\n+\t\t\t\t}\n+\t\t\t\tCLEAR_IN_EP_INTR(core_if, epnum, intktxfemp);\n+\t\t\t}\n+\t\t\t/** IN Token Received with EP mismatch */\n+\t\t\tif (diepint.b.intknepmis) {\n+\t\t\t\tDWC_DEBUGPL(DBG_ANY,\n+\t\t\t\t\t    \"EP%d IN TKN EP Mismatch\\n\", epnum);\n+\t\t\t\tCLEAR_IN_EP_INTR(core_if, epnum, intknepmis);\n+\t\t\t}\n+\t\t\t/** IN Endpoint NAK Effective */\n+\t\t\tif (diepint.b.inepnakeff) {\n+\t\t\t\tDWC_DEBUGPL(DBG_ANY,\n+\t\t\t\t\t    \"EP%d IN EP NAK Effective\\n\",\n+\t\t\t\t\t    epnum);\n+\t\t\t\t/* Periodic EP */\n+\t\t\t\tif (ep->disabling) {\n+\t\t\t\t\tdepctl.d32 = 0;\n+\t\t\t\t\tdepctl.b.snak = 1;\n+\t\t\t\t\tdepctl.b.epdis = 1;\n+\t\t\t\t\tDWC_MODIFY_REG32(&dev_if->in_ep_regs\n+\t\t\t\t\t\t\t [epnum]->diepctl,\n+\t\t\t\t\t\t\t depctl.d32,\n+\t\t\t\t\t\t\t depctl.d32);\n+\t\t\t\t}\n+\t\t\t\tCLEAR_IN_EP_INTR(core_if, epnum, inepnakeff);\n+\n+\t\t\t}\n+\n+\t\t\t/** IN EP Tx FIFO Empty Intr */\n+\t\t\tif (diepint.b.emptyintr) {\n+\t\t\t\tDWC_DEBUGPL(DBG_ANY,\n+\t\t\t\t\t    \"EP%d Tx FIFO Empty Intr \\n\",\n+\t\t\t\t\t    epnum);\n+\t\t\t\twrite_empty_tx_fifo(pcd, epnum);\n+\n+\t\t\t\tCLEAR_IN_EP_INTR(core_if, epnum, emptyintr);\n+\n+\t\t\t}\n+\n+\t\t\t/** IN EP BNA Intr */\n+\t\t\tif (diepint.b.bna) {\n+\t\t\t\tCLEAR_IN_EP_INTR(core_if, epnum, bna);\n+\t\t\t\tif (core_if->dma_desc_enable) {\n+#ifdef DWC_EN_ISOC\n+\t\t\t\t\tif (dwc_ep->type ==\n+\t\t\t\t\t    DWC_OTG_EP_TYPE_ISOC) {\n+\t\t\t\t\t\t/*\n+\t\t\t\t\t\t * This checking is performed to prevent first \"false\" BNA\n+\t\t\t\t\t\t * handling occuring right after reconnect\n+\t\t\t\t\t\t */\n+\t\t\t\t\t\tif (dwc_ep->next_frame !=\n+\t\t\t\t\t\t    0xffffffff)\n+\t\t\t\t\t\t\tdwc_otg_pcd_handle_iso_bna(ep);\n+\t\t\t\t\t} else\n+#endif\t\t\t\t/* DWC_EN_ISOC */\n+\t\t\t\t\t{\n+\t\t\t\t\t\tdwc_otg_pcd_handle_noniso_bna(ep);\n+\t\t\t\t\t}\n+\t\t\t\t}\n+\t\t\t}\n+\t\t\t/* NAK Interrutp */\n+\t\t\tif (diepint.b.nak) {\n+\t\t\t\tDWC_DEBUGPL(DBG_ANY, \"EP%d IN NAK Interrupt\\n\",\n+\t\t\t\t\t    epnum);\n+\t\t\t\tif (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) {\n+\t\t\t\t\tdepctl_data_t depctl;\n+\t\t\t\t\tif (ep->dwc_ep.frame_num == 0xFFFFFFFF) {\n+\t\t\t\t\t\tep->dwc_ep.frame_num = core_if->frame_num;\n+\t\t\t\t\t\tif (ep->dwc_ep.bInterval > 1) {\n+\t\t\t\t\t\t\tdepctl.d32 = 0;\n+\t\t\t\t\t\t\tdepctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->diepctl);\n+\t\t\t\t\t\t\tif (ep->dwc_ep.frame_num & 0x1) {\n+\t\t\t\t\t\t\t\tdepctl.b.setd1pid = 1;\n+\t\t\t\t\t\t\t\tdepctl.b.setd0pid = 0;\n+\t\t\t\t\t\t\t} else {\n+\t\t\t\t\t\t\t\tdepctl.b.setd0pid = 1;\n+\t\t\t\t\t\t\t\tdepctl.b.setd1pid = 0;\n+\t\t\t\t\t\t\t}\n+\t\t\t\t\t\t\tDWC_WRITE_REG32(&dev_if->in_ep_regs[epnum]->diepctl, depctl.d32);\n+\t\t\t\t\t\t}\n+\t\t\t\t\t\tstart_next_request(ep);\n+\t\t\t\t\t}\n+\t\t\t\t\tep->dwc_ep.frame_num += ep->dwc_ep.bInterval;\n+\t\t\t\t\tif (dwc_ep->frame_num > 0x3FFF)\t{\n+\t\t\t\t\t\tdwc_ep->frm_overrun = 1;\n+\t\t\t\t\t\tdwc_ep->frame_num &= 0x3FFF;\n+\t\t\t\t\t} else\n+\t\t\t\t\t\tdwc_ep->frm_overrun = 0;\n+\t\t\t\t}\n+\n+\t\t\t\tCLEAR_IN_EP_INTR(core_if, epnum, nak);\n+\t\t\t}\n+\t\t}\n+\t\tepnum++;\n+\t\tep_intr >>= 1;\n+\t}\n+\n+\treturn 1;\n+#undef CLEAR_IN_EP_INTR\n+}\n+\n+/**\n+ * This interrupt indicates that an OUT EP has a pending Interrupt.\n+ * The sequence for handling the OUT EP interrupt is shown below:\n+ * -#\tRead the Device All Endpoint Interrupt register\n+ * -#\tRepeat the following for each OUT EP interrupt bit set (from\n+ *\t\tLSB to MSB).\n+ * -#\tRead the Device Endpoint Interrupt (DOEPINTn) register\n+ * -#\tIf \"Transfer Complete\" call the request complete function\n+ * -#\tIf \"Endpoint Disabled\" complete the EP disable procedure.\n+ * -#\tIf \"AHB Error Interrupt\" log error\n+ * -#\tIf \"Setup Phase Done\" process Setup Packet (See Standard USB\n+ *\t\tCommand Processing)\n+ */\n+static int32_t dwc_otg_pcd_handle_out_ep_intr(dwc_otg_pcd_t * pcd)\n+{\n+#define CLEAR_OUT_EP_INTR(__core_if,__epnum,__intr) \\\n+do { \\\n+\t\tdoepint_data_t doepint = {.d32=0}; \\\n+\t\tdoepint.b.__intr = 1; \\\n+\t\tDWC_WRITE_REG32(&__core_if->dev_if->out_ep_regs[__epnum]->doepint, \\\n+\t\tdoepint.d32); \\\n+} while (0)\n+\n+\tdwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);\n+\tuint32_t ep_intr;\n+\tdoepint_data_t doepint = {.d32 = 0 };\n+\tuint32_t epnum = 0;\n+\tdwc_otg_pcd_ep_t *ep;\n+\tdwc_ep_t *dwc_ep;\n+\tdctl_data_t dctl = {.d32 = 0 };\n+\tgintmsk_data_t gintmsk = {.d32 = 0 };\n+\n+\n+\tDWC_DEBUGPL(DBG_PCDV, \"%s()\\n\", __func__);\n+\n+\t/* Read in the device interrupt bits */\n+\tep_intr = dwc_otg_read_dev_all_out_ep_intr(core_if);\n+\n+\twhile (ep_intr) {\n+\t\tif (ep_intr & 0x1) {\n+\t\t\t/* Get EP pointer */\n+\t\t\tep = get_out_ep(pcd, epnum);\n+\t\t\tdwc_ep = &ep->dwc_ep;\n+\n+#ifdef VERBOSE\n+\t\t\tDWC_DEBUGPL(DBG_PCDV,\n+\t\t\t\t    \"EP%d-%s: type=%d, mps=%d\\n\",\n+\t\t\t\t    dwc_ep->num, (dwc_ep->is_in ? \"IN\" : \"OUT\"),\n+\t\t\t\t    dwc_ep->type, dwc_ep->maxpacket);\n+#endif\n+\t\t\tdoepint.d32 =\n+\t\t\t    dwc_otg_read_dev_out_ep_intr(core_if, dwc_ep);\n+\t\t\t/* Moved this interrupt upper due to core deffect of asserting\n+\t\t\t * OUT EP 0 xfercompl along with stsphsrcvd in BDMA */\n+\t\t\tif (doepint.b.stsphsercvd) {\n+\t\t\t\tdeptsiz0_data_t deptsiz;\n+\t\t\t\tCLEAR_OUT_EP_INTR(core_if, epnum, stsphsercvd);\n+\t\t\t\tdeptsiz.d32 =\n+\t\t\t\t    DWC_READ_REG32(&core_if->dev_if->\n+\t\t\t\t\t\t   out_ep_regs[0]->doeptsiz);\n+\t\t\t\tif (core_if->snpsid >= OTG_CORE_REV_3_00a\n+\t\t\t\t    && core_if->dma_enable\n+\t\t\t\t    && core_if->dma_desc_enable == 0\n+\t\t\t\t    && doepint.b.xfercompl\n+\t\t\t\t    && deptsiz.b.xfersize == 24) {\n+\t\t\t\t\tCLEAR_OUT_EP_INTR(core_if, epnum,\n+\t\t\t\t\t\t\t  xfercompl);\n+\t\t\t\t\tdoepint.b.xfercompl = 0;\n+\t\t\t\t\tep0_out_start(core_if, pcd);\n+\t\t\t\t}\n+\t\t\t\tif ((core_if->dma_desc_enable) ||\n+\t\t\t\t    (core_if->dma_enable\n+\t\t\t\t     && core_if->snpsid >=\n+\t\t\t\t     OTG_CORE_REV_3_00a)) {\n+\t\t\t\t\tdo_setup_in_status_phase(pcd);\n+\t\t\t\t}\n+\t\t\t}\n+\t\t\t/* Transfer complete */\n+\t\t\tif (doepint.b.xfercompl) {\n+\n+\t\t\t\tif (epnum == 0) {\n+\t\t\t\t\t/* Clear the bit in DOEPINTn for this interrupt */\n+\t\t\t\t\tCLEAR_OUT_EP_INTR(core_if, epnum, xfercompl);\n+\t\t\t\t\tif (core_if->snpsid >= OTG_CORE_REV_3_00a) {\n+\t\t\t\t\t\tDWC_DEBUGPL(DBG_PCDV, \"DOEPINT=%x doepint=%x\\n\",\n+\t\t\t\t\t\t\tDWC_READ_REG32(&core_if->dev_if->out_ep_regs[0]->doepint),\n+\t\t\t\t\t\t\tdoepint.d32);\n+\t\t\t\t\t\tDWC_DEBUGPL(DBG_PCDV, \"DOEPCTL=%x \\n\",\n+\t\t\t\t\t\t\tDWC_READ_REG32(&core_if->dev_if->out_ep_regs[0]->doepctl));\n+\n+\t\t\t\t\t\tif (core_if->snpsid >= OTG_CORE_REV_3_00a\n+\t\t\t\t\t\t\t&& core_if->dma_enable == 0) {\n+\t\t\t\t\t\t\tdoepint_data_t doepint;\n+\t\t\t\t\t\t\tdoepint.d32 = DWC_READ_REG32(&core_if->dev_if->\n+\t\t\t\t\t\t\t\t\t\t\t\t\t\tout_ep_regs[0]->doepint);\n+\t\t\t\t\t\t\tif (pcd->ep0state == EP0_IDLE && doepint.b.sr) {\n+\t\t\t\t\t\t\t\tCLEAR_OUT_EP_INTR(core_if, epnum, sr);\n+\t\t\t\t\t\t\t\tgoto exit_xfercompl;\n+\t\t\t\t\t\t\t}\n+\t\t\t\t\t\t}\n+\t\t\t\t\t\t/* In case of DDMA  look at SR bit to go to the Data Stage */\n+\t\t\t\t\t\tif (core_if->dma_desc_enable) {\n+\t\t\t\t\t\t\tdev_dma_desc_sts_t status = {.d32 = 0};\n+\t\t\t\t\t\t\tif (pcd->ep0state == EP0_IDLE) {\n+\t\t\t\t\t\t\t\tstatus.d32 = core_if->dev_if->setup_desc_addr[core_if->\n+\t\t\t\t\t\t\t\t\t\t\tdev_if->setup_desc_index]->status.d32;\n+\t\t\t\t\t\t\t\tif(pcd->data_terminated) {\n+\t\t\t\t\t\t\t\t\t pcd->data_terminated = 0;\n+\t\t\t\t\t\t\t\t\t status.d32 = core_if->dev_if->out_desc_addr->status.d32;\n+\t\t\t\t\t\t\t\t\t dwc_memcpy(&pcd->setup_pkt->req, pcd->backup_buf, 8);\n+\t\t\t\t\t\t\t\t}\n+\t\t\t\t\t\t\t\tif (status.b.sr) {\n+\t\t\t\t\t\t\t\t\tif (doepint.b.setup) {\n+\t\t\t\t\t\t\t\t\t\tDWC_DEBUGPL(DBG_PCDV, \"DMA DESC EP0_IDLE SR=1 setup=1\\n\");\n+\t\t\t\t\t\t\t\t\t\t/* Already started data stage, clear setup */\n+\t\t\t\t\t\t\t\t\t\tCLEAR_OUT_EP_INTR(core_if, epnum, setup);\n+\t\t\t\t\t\t\t\t\t\tdoepint.b.setup = 0;\n+\t\t\t\t\t\t\t\t\t\thandle_ep0(pcd);\n+\t\t\t\t\t\t\t\t\t\t/* Prepare for more setup packets */\n+\t\t\t\t\t\t\t\t\t\tif (pcd->ep0state == EP0_IN_STATUS_PHASE ||\n+\t\t\t\t\t\t\t\t\t\t\tpcd->ep0state == EP0_IN_DATA_PHASE) {\n+\t\t\t\t\t\t\t\t\t\t\tep0_out_start(core_if, pcd);\n+\t\t\t\t\t\t\t\t\t\t}\n+\n+\t\t\t\t\t\t\t\t\t\tgoto exit_xfercompl;\n+\t\t\t\t\t\t\t\t\t} else {\n+\t\t\t\t\t\t\t\t\t\t/* Prepare for more setup packets */\n+\t\t\t\t\t\t\t\t\t\tDWC_DEBUGPL(DBG_PCDV,\n+\t\t\t\t\t\t\t\t\t\t\t\"EP0_IDLE SR=1 setup=0 new setup comes\\n\");\n+\t\t\t\t\t\t\t\t\t\tep0_out_start(core_if, pcd);\n+\t\t\t\t\t\t\t\t\t}\n+\t\t\t\t\t\t\t\t}\n+\t\t\t\t\t\t\t} else {\n+\t\t\t\t\t\t\t\tdwc_otg_pcd_request_t *req;\n+\t\t\t\t\t\t\t\tdev_dma_desc_sts_t status = {.d32 = 0};\n+\t\t\t\t\t\t\t\tdiepint_data_t diepint0;\n+\t\t\t\t\t\t\t\tdiepint0.d32 = DWC_READ_REG32(&core_if->dev_if->\n+\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tin_ep_regs[0]->diepint);\n+\n+\t\t\t\t\t\t\t\tif (pcd->ep0state == EP0_STALL || pcd->ep0state == EP0_DISCONNECT) {\n+\t\t\t\t\t\t\t\t\tDWC_ERROR(\"EP0 is stalled/disconnected\\n\");\n+\t\t\t\t\t\t\t\t}\n+\n+\t\t\t\t\t\t\t\t/* Clear IN xfercompl if set */\n+\t\t\t\t\t\t\t\tif (diepint0.b.xfercompl && (pcd->ep0state == EP0_IN_STATUS_PHASE\n+\t\t\t\t\t\t\t\t\t|| pcd->ep0state == EP0_IN_DATA_PHASE)) {\n+\t\t\t\t\t\t\t\t\tDWC_WRITE_REG32(&core_if->dev_if->\n+\t\t\t\t\t\t\t\t\t\tin_ep_regs[0]->diepint, diepint0.d32);\n+\t\t\t\t\t\t\t\t}\n+\n+\t\t\t\t\t\t\t\tstatus.d32 = core_if->dev_if->setup_desc_addr[core_if->\n+\t\t\t\t\t\t\t\t\tdev_if->setup_desc_index]->status.d32;\n+\n+\t\t\t\t\t\t\t\tif (ep->dwc_ep.xfer_count != ep->dwc_ep.total_len\n+\t\t\t\t\t\t\t\t\t&& (pcd->ep0state == EP0_OUT_DATA_PHASE))\n+\t\t\t\t\t\t\t\t\tstatus.d32 = core_if->dev_if->out_desc_addr->status.d32;\n+\t\t\t\t\t\t\t\tif (pcd->ep0state == EP0_OUT_STATUS_PHASE)\n+\t\t\t\t\t\t\t\t\tstatus.d32 = core_if->dev_if->\n+\t\t\t\t\t\t\t\t\tout_desc_addr->status.d32;\n+\n+\t\t\t\t\t\t\t\tif (status.b.sr) {\n+\t\t\t\t\t\t\t\t\tif (DWC_CIRCLEQ_EMPTY(&ep->queue)) {\n+\t\t\t\t\t\t\t\t\t\tDWC_DEBUGPL(DBG_PCDV, \"Request queue empty!!\\n\");\n+\t\t\t\t\t\t\t\t\t} else {\n+\t\t\t\t\t\t\t\t\t\tDWC_DEBUGPL(DBG_PCDV, \"complete req!!\\n\");\n+\t\t\t\t\t\t\t\t\t\treq = DWC_CIRCLEQ_FIRST(&ep->queue);\n+\t\t\t\t\t\t\t\t\t\tif (ep->dwc_ep.xfer_count != ep->dwc_ep.total_len &&\n+\t\t\t\t\t\t\t\t\t\t\tpcd->ep0state == EP0_OUT_DATA_PHASE) {\n+\t\t\t\t\t\t\t\t\t\t\t\t/* Read arrived setup packet from req->buf */\n+\t\t\t\t\t\t\t\t\t\t\t\tdwc_memcpy(&pcd->setup_pkt->req,\n+\t\t\t\t\t\t\t\t\t\t\t\t\treq->buf + ep->dwc_ep.xfer_count, 8);\n+\t\t\t\t\t\t\t\t\t\t}\n+\t\t\t\t\t\t\t\t\t\treq->actual = ep->dwc_ep.xfer_count;\n+\t\t\t\t\t\t\t\t\t\tdwc_otg_request_done(ep, req, -ECONNRESET);\n+\t\t\t\t\t\t\t\t\t\tep->dwc_ep.start_xfer_buff = 0;\n+\t\t\t\t\t\t\t\t\t\tep->dwc_ep.xfer_buff = 0;\n+\t\t\t\t\t\t\t\t\t\tep->dwc_ep.xfer_len = 0;\n+\t\t\t\t\t\t\t\t\t}\n+\t\t\t\t\t\t\t\t\tpcd->ep0state = EP0_IDLE;\n+\t\t\t\t\t\t\t\t\tif (doepint.b.setup) {\n+\t\t\t\t\t\t\t\t\t\tDWC_DEBUGPL(DBG_PCDV, \"EP0_IDLE SR=1 setup=1\\n\");\n+\t\t\t\t\t\t\t\t\t\t/* Data stage started, clear setup */\n+\t\t\t\t\t\t\t\t\t\tCLEAR_OUT_EP_INTR(core_if, epnum, setup);\n+\t\t\t\t\t\t\t\t\t\tdoepint.b.setup = 0;\n+\t\t\t\t\t\t\t\t\t\thandle_ep0(pcd);\n+\t\t\t\t\t\t\t\t\t\t/* Prepare for setup packets if ep0in was enabled*/\n+\t\t\t\t\t\t\t\t\t\tif (pcd->ep0state == EP0_IN_STATUS_PHASE) {\n+\t\t\t\t\t\t\t\t\t\t\tep0_out_start(core_if, pcd);\n+\t\t\t\t\t\t\t\t\t\t}\n+\n+\t\t\t\t\t\t\t\t\t\tgoto exit_xfercompl;\n+\t\t\t\t\t\t\t\t\t} else {\n+\t\t\t\t\t\t\t\t\t\t/* Prepare for more setup packets */\n+\t\t\t\t\t\t\t\t\t\tDWC_DEBUGPL(DBG_PCDV,\n+\t\t\t\t\t\t\t\t\t\t\t\"EP0_IDLE SR=1 setup=0 new setup comes 2\\n\");\n+\t\t\t\t\t\t\t\t\t\tep0_out_start(core_if, pcd);\n+\t\t\t\t\t\t\t\t\t}\n+\t\t\t\t\t\t\t\t}\n+\t\t\t\t\t\t\t}\n+\t\t\t\t\t\t}\n+\t\t\t\t\t\tif (core_if->snpsid >= OTG_CORE_REV_2_94a && core_if->dma_enable\n+\t\t\t\t\t\t\t&& core_if->dma_desc_enable == 0) {\n+\t\t\t\t\t\t\tdoepint_data_t doepint_temp = {.d32 = 0};\n+\t\t\t\t\t\t\tdeptsiz0_data_t doeptsize0 = {.d32 = 0 };\n+\t\t\t\t\t\t\tdoepint_temp.d32 = DWC_READ_REG32(&core_if->dev_if->\n+\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tout_ep_regs[ep->dwc_ep.num]->doepint);\n+\t\t\t\t\t\t\tdoeptsize0.d32 = DWC_READ_REG32(&core_if->dev_if->\n+\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tout_ep_regs[ep->dwc_ep.num]->doeptsiz);\n+\t\t\t\t\t\t\tif (pcd->ep0state == EP0_IDLE) {\n+\t\t\t\t\t\t\t\tif (doepint_temp.b.sr) {\n+\t\t\t\t\t\t\t\t\tCLEAR_OUT_EP_INTR(core_if, epnum, sr);\n+\t\t\t\t\t\t\t\t}\n+\t\t\t\t\t\t\t\t\tdoepint.d32 = DWC_READ_REG32(&core_if->dev_if->\n+\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tout_ep_regs[0]->doepint);\n+\t\t\t\t\t\t\t\t\tif (doeptsize0.b.supcnt == 3) {\n+\t\t\t\t\t\t\t\t\t\tDWC_DEBUGPL(DBG_ANY, \"Rolling over!!!!!!!\\n\");\n+\t\t\t\t\t\t\t\t\t\tep->dwc_ep.stp_rollover = 1;\n+\t\t\t\t\t\t\t\t\t}\n+\t\t\t\t\t\t\t\t\tif (doepint.b.setup) {\n+retry:\n+\t\t\t\t\t\t\t\t\t\t/* Already started data stage, clear setup */\n+\t\t\t\t\t\t\t\t\t\tCLEAR_OUT_EP_INTR(core_if, epnum, setup);\n+\t\t\t\t\t\t\t\t\t\tdoepint.b.setup = 0;\n+\t\t\t\t\t\t\t\t\t\thandle_ep0(pcd);\n+\t\t\t\t\t\t\t\t\t\tep->dwc_ep.stp_rollover = 0;\n+\t\t\t\t\t\t\t\t\t\t/* Prepare for more setup packets */\n+\t\t\t\t\t\t\t\t\t\tif (pcd->ep0state == EP0_IN_STATUS_PHASE ||\n+\t\t\t\t\t\t\t\t\t\t\tpcd->ep0state == EP0_IN_DATA_PHASE) {\n+\t\t\t\t\t\t\t\t\t\t\tep0_out_start(core_if, pcd);\n+\t\t\t\t\t\t\t\t\t\t}\n+\t\t\t\t\t\t\t\t\t\tgoto exit_xfercompl;\n+\t\t\t\t\t\t\t\t\t} else {\n+\t\t\t\t\t\t\t\t\t\t/* Prepare for more setup packets */\n+\t\t\t\t\t\t\t\t\t\tDWC_DEBUGPL(DBG_ANY,\n+\t\t\t\t\t\t\t\t\t\t\t\"EP0_IDLE SR=1 setup=0 new setup comes\\n\");\n+\t\t\t\t\t\t\t\t\t\tdoepint.d32 = DWC_READ_REG32(&core_if->dev_if->\n+\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tout_ep_regs[0]->doepint);\n+\t\t\t\t\t\t\t\t\t\tif(doepint.b.setup)\n+\t\t\t\t\t\t\t\t\t\t\tgoto retry;\n+\t\t\t\t\t\t\t\t\t\tep0_out_start(core_if, pcd);\n+\t\t\t\t\t\t\t\t\t}\n+\t\t\t\t\t\t\t} else {\n+\t\t\t\t\t\t\t\tdwc_otg_pcd_request_t *req;\n+\t\t\t\t\t\t\t\tdiepint_data_t diepint0 = {.d32 = 0};\n+\t\t\t\t\t\t\t\tdoepint_data_t doepint_temp = {.d32 = 0};\n+\t\t\t\t\t\t\t\tdepctl_data_t diepctl0;\n+\t\t\t\t\t\t\t\tdiepint0.d32 = DWC_READ_REG32(&core_if->dev_if->\n+\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tin_ep_regs[0]->diepint);\n+\t\t\t\t\t\t\t\tdiepctl0.d32 = DWC_READ_REG32(&core_if->dev_if->\n+\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tin_ep_regs[0]->diepctl);\n+\n+\t\t\t\t\t\t\t\tif (pcd->ep0state == EP0_IN_DATA_PHASE\n+\t\t\t\t\t\t\t\t\t|| pcd->ep0state == EP0_IN_STATUS_PHASE) {\n+\t\t\t\t\t\t\t\t\tif (diepint0.b.xfercompl) {\n+\t\t\t\t\t\t\t\t\t\tDWC_WRITE_REG32(&core_if->dev_if->\n+\t\t\t\t\t\t\t\t\t\t\tin_ep_regs[0]->diepint, diepint0.d32);\n+\t\t\t\t\t\t\t\t\t}\n+\t\t\t\t\t\t\t\t\tif (diepctl0.b.epena) {\n+\t\t\t\t\t\t\t\t\t\tdiepint_data_t diepint = {.d32 = 0};\n+\t\t\t\t\t\t\t\t\t\tdiepctl0.b.snak = 1;\n+\t\t\t\t\t\t\t\t\t\tDWC_WRITE_REG32(&core_if->dev_if->\n+\t\t\t\t\t\t\t\t\t\t\t\t\t\tin_ep_regs[0]->diepctl, diepctl0.d32);\n+\t\t\t\t\t\t\t\t\t\tdo {\n+\t\t\t\t\t\t\t\t\t\t\tdwc_udelay(10);\n+\t\t\t\t\t\t\t\t\t\t\tdiepint.d32 = DWC_READ_REG32(&core_if->dev_if->\n+\t\t\t\t\t\t\t\t\t\t\t\tin_ep_regs[0]->diepint);\n+\t\t\t\t\t\t\t\t\t\t} while (!diepint.b.inepnakeff);\n+\t\t\t\t\t\t\t\t\t\tdiepint.b.inepnakeff = 1;\n+\t\t\t\t\t\t\t\t\t\tDWC_WRITE_REG32(&core_if->dev_if->\n+\t\t\t\t\t\t\t\t\t\t\tin_ep_regs[0]->diepint, diepint.d32);\n+\t\t\t\t\t\t\t\t\t\tdiepctl0.d32 = 0;\n+\t\t\t\t\t\t\t\t\t\tdiepctl0.b.epdis = 1;\n+\t\t\t\t\t\t\t\t\t\tDWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[0]->diepctl,\n+\t\t\t\t\t\t\t\t\t\t\t\t\t\tdiepctl0.d32);\n+\t\t\t\t\t\t\t\t\t\tdo {\n+\t\t\t\t\t\t\t\t\t\t\tdwc_udelay(10);\n+\t\t\t\t\t\t\t\t\t\t\tdiepint.d32 = DWC_READ_REG32(&core_if->dev_if->\n+\t\t\t\t\t\t\t\t\t\t\t\tin_ep_regs[0]->diepint);\n+\t\t\t\t\t\t\t\t\t\t} while (!diepint.b.epdisabled);\n+\t\t\t\t\t\t\t\t\t\tdiepint.b.epdisabled = 1;\n+\t\t\t\t\t\t\t\t\t\tDWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[0]->diepint,\n+\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tdiepint.d32);\n+\t\t\t\t\t\t\t\t\t}\n+\t\t\t\t\t\t\t\t}\n+\t\t\t\t\t\t\t\tdoepint_temp.d32 = DWC_READ_REG32(&core_if->dev_if->\n+\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tout_ep_regs[ep->dwc_ep.num]->doepint);\n+\t\t\t\t\t\t\t\tif (doepint_temp.b.sr) {\n+\t\t\t\t\t\t\t\t\tCLEAR_OUT_EP_INTR(core_if, epnum, sr);\n+\t\t\t\t\t\t\t\t\tif (DWC_CIRCLEQ_EMPTY(&ep->queue)) {\n+\t\t\t\t\t\t\t\t\t\tDWC_DEBUGPL(DBG_PCDV, \"Request queue empty!!\\n\");\n+\t\t\t\t\t\t\t\t\t} else {\n+\t\t\t\t\t\t\t\t\t\tDWC_DEBUGPL(DBG_PCDV, \"complete req!!\\n\");\n+\t\t\t\t\t\t\t\t\t\treq = DWC_CIRCLEQ_FIRST(&ep->queue);\n+\t\t\t\t\t\t\t\t\t\tif (ep->dwc_ep.xfer_count != ep->dwc_ep.total_len &&\n+\t\t\t\t\t\t\t\t\t\t\tpcd->ep0state == EP0_OUT_DATA_PHASE) {\n+\t\t\t\t\t\t\t\t\t\t\t\t/* Read arrived setup packet from req->buf */\n+\t\t\t\t\t\t\t\t\t\t\t\tdwc_memcpy(&pcd->setup_pkt->req,\n+\t\t\t\t\t\t\t\t\t\t\t\t\treq->buf + ep->dwc_ep.xfer_count, 8);\n+\t\t\t\t\t\t\t\t\t\t}\n+\t\t\t\t\t\t\t\t\t\treq->actual = ep->dwc_ep.xfer_count;\n+\t\t\t\t\t\t\t\t\t\tdwc_otg_request_done(ep, req, -ECONNRESET);\n+\t\t\t\t\t\t\t\t\t\tep->dwc_ep.start_xfer_buff = 0;\n+\t\t\t\t\t\t\t\t\t\tep->dwc_ep.xfer_buff = 0;\n+\t\t\t\t\t\t\t\t\t\tep->dwc_ep.xfer_len = 0;\n+\t\t\t\t\t\t\t\t\t}\n+\t\t\t\t\t\t\t\t\tpcd->ep0state = EP0_IDLE;\n+\t\t\t\t\t\t\t\t\tif (doepint.b.setup) {\n+\t\t\t\t\t\t\t\t\t\tDWC_DEBUGPL(DBG_PCDV, \"EP0_IDLE SR=1 setup=1\\n\");\n+\t\t\t\t\t\t\t\t\t\t/* Data stage started, clear setup */\n+\t\t\t\t\t\t\t\t\t\tCLEAR_OUT_EP_INTR(core_if, epnum, setup);\n+\t\t\t\t\t\t\t\t\t\tdoepint.b.setup = 0;\n+\t\t\t\t\t\t\t\t\t\thandle_ep0(pcd);\n+\t\t\t\t\t\t\t\t\t\t/* Prepare for setup packets if ep0in was enabled*/\n+\t\t\t\t\t\t\t\t\t\tif (pcd->ep0state == EP0_IN_STATUS_PHASE) {\n+\t\t\t\t\t\t\t\t\t\t\tep0_out_start(core_if, pcd);\n+\t\t\t\t\t\t\t\t\t\t}\n+\t\t\t\t\t\t\t\t\t\tgoto exit_xfercompl;\n+\t\t\t\t\t\t\t\t\t} else {\n+\t\t\t\t\t\t\t\t\t\t/* Prepare for more setup packets */\n+\t\t\t\t\t\t\t\t\t\tDWC_DEBUGPL(DBG_PCDV,\n+\t\t\t\t\t\t\t\t\t\t\t\"EP0_IDLE SR=1 setup=0 new setup comes 2\\n\");\n+\t\t\t\t\t\t\t\t\t\tep0_out_start(core_if, pcd);\n+\t\t\t\t\t\t\t\t\t}\n+\t\t\t\t\t\t\t\t}\n+\t\t\t\t\t\t\t}\n+\t\t\t\t\t\t}\n+\t\t\t\t\t\tif (core_if->dma_enable == 0 || pcd->ep0state != EP0_IDLE)\n+\t\t\t\t\t\t\thandle_ep0(pcd);\n+exit_xfercompl:\n+\t\t\t\t\t\tDWC_DEBUGPL(DBG_PCDV, \"DOEPINT=%x doepint=%x\\n\",\n+\t\t\t\t\t\t\tdwc_otg_read_dev_out_ep_intr(core_if, dwc_ep), doepint.d32);\n+\t\t\t\t\t} else {\n+\t\t\t\t\tif (core_if->dma_desc_enable == 0\n+\t\t\t\t\t    || pcd->ep0state != EP0_IDLE)\n+\t\t\t\t\t\thandle_ep0(pcd);\n+\t\t\t\t\t}\n+#ifdef DWC_EN_ISOC\n+\t\t\t\t} else if (dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {\n+\t\t\t\t\tif (doepint.b.pktdrpsts == 0) {\n+\t\t\t\t\t\t/* Clear the bit in DOEPINTn for this interrupt */\n+\t\t\t\t\t\tCLEAR_OUT_EP_INTR(core_if,\n+\t\t\t\t\t\t\t\t  epnum,\n+\t\t\t\t\t\t\t\t  xfercompl);\n+\t\t\t\t\t\tcomplete_iso_ep(pcd, ep);\n+\t\t\t\t\t} else {\n+\n+\t\t\t\t\t\tdoepint_data_t doepint = {.d32 = 0 };\n+\t\t\t\t\t\tdoepint.b.xfercompl = 1;\n+\t\t\t\t\t\tdoepint.b.pktdrpsts = 1;\n+\t\t\t\t\t\tDWC_WRITE_REG32\n+\t\t\t\t\t\t    (&core_if->dev_if->out_ep_regs\n+\t\t\t\t\t\t     [epnum]->doepint,\n+\t\t\t\t\t\t     doepint.d32);\n+\t\t\t\t\t\tif (handle_iso_out_pkt_dropped\n+\t\t\t\t\t\t    (core_if, dwc_ep)) {\n+\t\t\t\t\t\t\tcomplete_iso_ep(pcd,\n+\t\t\t\t\t\t\t\t\tep);\n+\t\t\t\t\t\t}\n+\t\t\t\t\t}\n+#endif /* DWC_EN_ISOC */\n+#ifdef DWC_UTE_PER_IO\n+\t\t\t\t} else if (dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {\n+\t\t\t\t\tCLEAR_OUT_EP_INTR(core_if, epnum, xfercompl);\n+\t\t\t\t\tif (!ep->stopped)\n+\t\t\t\t\t\tcomplete_xiso_ep(ep);\n+#endif /* DWC_UTE_PER_IO */\n+\t\t\t\t} else {\n+\t\t\t\t\t/* Clear the bit in DOEPINTn for this interrupt */\n+\t\t\t\t\tCLEAR_OUT_EP_INTR(core_if, epnum,\n+\t\t\t\t\t\t\t  xfercompl);\n+\n+\t\t\t\t\tif (core_if->core_params->dev_out_nak) {\n+\t\t\t\t\t\tDWC_TIMER_CANCEL(pcd->core_if->ep_xfer_timer[epnum]);\n+\t\t\t\t\t\tpcd->core_if->ep_xfer_info[epnum].state = 0;\n+#ifdef DEBUG\n+\t\t\t\t\t\tprint_memory_payload(pcd, dwc_ep);\n+#endif\n+\t\t\t\t\t}\n+\t\t\t\t\tcomplete_ep(ep);\n+\t\t\t\t}\n+\n+\t\t\t}\n+\n+\t\t\t/* Endpoint disable      */\n+\t\t\tif (doepint.b.epdisabled) {\n+\n+\t\t\t\t/* Clear the bit in DOEPINTn for this interrupt */\n+\t\t\t\tCLEAR_OUT_EP_INTR(core_if, epnum, epdisabled);\n+\t\t\t\tif (core_if->core_params->dev_out_nak) {\n+#ifdef DEBUG\n+\t\t\t\t\tprint_memory_payload(pcd, dwc_ep);\n+#endif\n+\t\t\t\t\t/* In case of timeout condition */\n+\t\t\t\t\tif (core_if->ep_xfer_info[epnum].state == 2) {\n+\t\t\t\t\t\tdctl.d32 = DWC_READ_REG32(&core_if->dev_if->\n+\t\t\t\t\t\t\t\t\t\tdev_global_regs->dctl);\n+\t\t\t\t\t\tdctl.b.cgoutnak = 1;\n+\t\t\t\t\t\tDWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl,\n+\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tdctl.d32);\n+\t\t\t\t\t\t/* Unmask goutnakeff interrupt which was masked\n+\t\t\t\t\t\t * during handle nak out interrupt */\n+\t\t\t\t\t\tgintmsk.b.goutnakeff = 1;\n+\t\t\t\t\t\tDWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk,\n+\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t0, gintmsk.d32);\n+\n+\t\t\t\t\t\tcomplete_ep(ep);\n+\t\t\t\t\t}\n+\t\t\t\t}\n+\t\t\t\tif (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC)\n+\t\t\t\t{\n+\t\t\t\t\tdctl_data_t dctl;\n+\t\t\t\t\tgintmsk_data_t intr_mask = {.d32 = 0};\n+\t\t\t\t\tdwc_otg_pcd_request_t *req = 0;\n+\n+\t\t\t\t\tdctl.d32 = DWC_READ_REG32(&core_if->dev_if->\n+\t\t\t\t\t\tdev_global_regs->dctl);\n+\t\t\t\t\tdctl.b.cgoutnak = 1;\n+\t\t\t\t\tDWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl,\n+\t\t\t\t\t\tdctl.d32);\n+\n+\t\t\t\t\tintr_mask.d32 = 0;\n+\t\t\t\t\tintr_mask.b.incomplisoout = 1;\n+\n+\t\t\t\t\t/* Get any pending requests */\n+\t\t\t\t\tif (!DWC_CIRCLEQ_EMPTY(&ep->queue)) {\n+\t\t\t\t\t\treq = DWC_CIRCLEQ_FIRST(&ep->queue);\n+\t\t\t\t\t\tif (!req) {\n+\t\t\t\t\t\t\tDWC_PRINTF(\"complete_ep 0x%p, req = NULL!\\n\", ep);\n+\t\t\t\t\t\t} else {\n+\t\t\t\t\t\t\tdwc_otg_request_done(ep, req, 0);\n+\t\t\t\t\t\t\tstart_next_request(ep);\n+\t\t\t\t\t\t}\n+\t\t\t\t\t} else {\n+\t\t\t\t\t\tDWC_PRINTF(\"complete_ep 0x%p, ep->queue empty!\\n\", ep);\n+\t\t\t\t\t}\n+\t\t\t\t}\n+\t\t\t}\n+\t\t\t/* AHB Error */\n+\t\t\tif (doepint.b.ahberr) {\n+\t\t\t\tDWC_ERROR(\"EP%d OUT AHB Error\\n\", epnum);\n+\t\t\t\tDWC_ERROR(\"EP%d DEPDMA=0x%08x \\n\",\n+\t\t\t\t\t  epnum, core_if->dev_if->out_ep_regs[epnum]->doepdma);\n+\t\t\t\tCLEAR_OUT_EP_INTR(core_if, epnum, ahberr);\n+\t\t\t}\n+\t\t\t/* Setup Phase Done (contorl EPs) */\n+\t\t\tif (doepint.b.setup) {\n+#ifdef DEBUG_EP0\n+\t\t\t\tDWC_DEBUGPL(DBG_PCD, \"EP%d SETUP Done\\n\", epnum);\n+#endif\n+\t\t\t\tCLEAR_OUT_EP_INTR(core_if, epnum, setup);\n+\n+\t\t\t\thandle_ep0(pcd);\n+\t\t\t}\n+\n+\t\t\t/** OUT EP BNA Intr */\n+\t\t\tif (doepint.b.bna) {\n+\t\t\t\tCLEAR_OUT_EP_INTR(core_if, epnum, bna);\n+\t\t\t\tif (core_if->dma_desc_enable) {\n+#ifdef DWC_EN_ISOC\n+\t\t\t\t\tif (dwc_ep->type ==\n+\t\t\t\t\t    DWC_OTG_EP_TYPE_ISOC) {\n+\t\t\t\t\t\t/*\n+\t\t\t\t\t\t * This checking is performed to prevent first \"false\" BNA\n+\t\t\t\t\t\t * handling occuring right after reconnect\n+\t\t\t\t\t\t */\n+\t\t\t\t\t\tif (dwc_ep->next_frame !=\n+\t\t\t\t\t\t    0xffffffff)\n+\t\t\t\t\t\t\tdwc_otg_pcd_handle_iso_bna(ep);\n+\t\t\t\t\t} else\n+#endif\t\t\t\t/* DWC_EN_ISOC */\n+\t\t\t\t\t{\n+\t\t\t\t\t\tdwc_otg_pcd_handle_noniso_bna(ep);\n+\t\t\t\t\t}\n+\t\t\t\t}\n+\t\t\t}\n+\t\t\t/* Babble Interrupt */\n+\t\t\tif (doepint.b.babble) {\n+\t\t\t\tDWC_DEBUGPL(DBG_ANY, \"EP%d OUT Babble\\n\",\n+\t\t\t\t\t    epnum);\n+\t\t\t\thandle_out_ep_babble_intr(pcd, epnum);\n+\n+\t\t\t\tCLEAR_OUT_EP_INTR(core_if, epnum, babble);\n+\t\t\t}\n+\t\t\tif (doepint.b.outtknepdis) {\n+\t\t\t\tDWC_DEBUGPL(DBG_ANY, \"EP%d OUT Token received when EP is \\\n+\t\t\t\t\tdisabled\\n\",epnum);\n+\t\t\t\tif (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) {\n+\t\t\t\t\tdoepmsk_data_t doepmsk = {.d32 = 0};\n+\t\t\t\t\tep->dwc_ep.frame_num = core_if->frame_num;\n+\t\t\t\t\tif (ep->dwc_ep.bInterval > 1) {\n+\t\t\t\t\t\tdepctl_data_t depctl;\n+\t\t\t\t\t\tdepctl.d32 = DWC_READ_REG32(&core_if->dev_if->\n+\t\t\t\t\t\t\t\t\t\t\t\t\tout_ep_regs[epnum]->doepctl);\n+\t\t\t\t\t\tif (ep->dwc_ep.frame_num & 0x1) {\n+\t\t\t\t\t\t\tdepctl.b.setd1pid = 1;\n+\t\t\t\t\t\t\tdepctl.b.setd0pid = 0;\n+\t\t\t\t\t\t} else {\n+\t\t\t\t\t\t\tdepctl.b.setd0pid = 1;\n+\t\t\t\t\t\t\tdepctl.b.setd1pid = 0;\n+\t\t\t\t\t\t}\n+\t\t\t\t\t\tDWC_WRITE_REG32(&core_if->dev_if->\n+\t\t\t\t\t\t\t\t\t\tout_ep_regs[epnum]->doepctl, depctl.d32);\n+\t\t\t\t\t}\n+\t\t\t\t\tstart_next_request(ep);\n+\t\t\t\t\tdoepmsk.b.outtknepdis = 1;\n+\t\t\t\t\tDWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->doepmsk,\n+\t\t\t\t\t\t\t\t doepmsk.d32, 0);\n+\t\t\t\t}\n+\t\t\t\tCLEAR_OUT_EP_INTR(core_if, epnum, outtknepdis);\n+\t\t\t}\n+\n+\t\t\t/* NAK Interrutp */\n+\t\t\tif (doepint.b.nak) {\n+\t\t\t\tDWC_DEBUGPL(DBG_ANY, \"EP%d OUT NAK\\n\", epnum);\n+\t\t\t\thandle_out_ep_nak_intr(pcd, epnum);\n+\n+\t\t\t\tCLEAR_OUT_EP_INTR(core_if, epnum, nak);\n+\t\t\t}\n+\t\t\t/* NYET Interrutp */\n+\t\t\tif (doepint.b.nyet) {\n+\t\t\t\tDWC_DEBUGPL(DBG_ANY, \"EP%d OUT NYET\\n\", epnum);\n+\t\t\t\thandle_out_ep_nyet_intr(pcd, epnum);\n+\n+\t\t\t\tCLEAR_OUT_EP_INTR(core_if, epnum, nyet);\n+\t\t\t}\n+\t\t}\n+\n+\t\tepnum++;\n+\t\tep_intr >>= 1;\n+\t}\n+\n+\treturn 1;\n+\n+#undef CLEAR_OUT_EP_INTR\n+}\n+static int drop_transfer(uint32_t trgt_fr, uint32_t curr_fr, uint8_t frm_overrun)\n+{\n+\tint retval = 0;\n+\tif(!frm_overrun && curr_fr >= trgt_fr)\n+\t\tretval = 1;\n+\telse if (frm_overrun\n+\t\t && (curr_fr >= trgt_fr && ((curr_fr - trgt_fr) < 0x3FFF / 2)))\n+\t\tretval = 1;\n+\treturn retval;\n+}\n+/**\n+ * Incomplete ISO IN Transfer Interrupt.\n+ * This interrupt indicates one of the following conditions occurred\n+ * while transmitting an ISOC transaction.\n+ * - Corrupted IN Token for ISOC EP.\n+ * - Packet not complete in FIFO.\n+ * The follow actions will be taken:\n+ *\t-#\tDetermine the EP\n+ *\t-#\tSet incomplete flag in dwc_ep structure\n+ *\t-#\tDisable EP; when \"Endpoint Disabled\" interrupt is received\n+ *\t\tFlush FIFO\n+ */\n+int32_t dwc_otg_pcd_handle_incomplete_isoc_in_intr(dwc_otg_pcd_t * pcd)\n+{\n+\tgintsts_data_t gintsts;\n+\n+#ifdef DWC_EN_ISOC\n+\tdwc_otg_dev_if_t *dev_if;\n+\tdeptsiz_data_t deptsiz = {.d32 = 0 };\n+\tdepctl_data_t depctl = {.d32 = 0 };\n+\tdsts_data_t dsts = {.d32 = 0 };\n+\tdwc_ep_t *dwc_ep;\n+\tint i;\n+\n+\tdev_if = GET_CORE_IF(pcd)->dev_if;\n+\n+\tfor (i = 1; i <= dev_if->num_in_eps; ++i) {\n+\t\tdwc_ep = &pcd->in_ep[i].dwc_ep;\n+\t\tif (dwc_ep->active && dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {\n+\t\t\tdeptsiz.d32 =\n+\t\t\t    DWC_READ_REG32(&dev_if->in_ep_regs[i]->dieptsiz);\n+\t\t\tdepctl.d32 =\n+\t\t\t    DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl);\n+\n+\t\t\tif (depctl.b.epdis && deptsiz.d32) {\n+\t\t\t\tset_current_pkt_info(GET_CORE_IF(pcd), dwc_ep);\n+\t\t\t\tif (dwc_ep->cur_pkt >= dwc_ep->pkt_cnt) {\n+\t\t\t\t\tdwc_ep->cur_pkt = 0;\n+\t\t\t\t\tdwc_ep->proc_buf_num =\n+\t\t\t\t\t    (dwc_ep->proc_buf_num ^ 1) & 0x1;\n+\n+\t\t\t\t\tif (dwc_ep->proc_buf_num) {\n+\t\t\t\t\t\tdwc_ep->cur_pkt_addr =\n+\t\t\t\t\t\t    dwc_ep->xfer_buff1;\n+\t\t\t\t\t\tdwc_ep->cur_pkt_dma_addr =\n+\t\t\t\t\t\t    dwc_ep->dma_addr1;\n+\t\t\t\t\t} else {\n+\t\t\t\t\t\tdwc_ep->cur_pkt_addr =\n+\t\t\t\t\t\t    dwc_ep->xfer_buff0;\n+\t\t\t\t\t\tdwc_ep->cur_pkt_dma_addr =\n+\t\t\t\t\t\t    dwc_ep->dma_addr0;\n+\t\t\t\t\t}\n+\n+\t\t\t\t}\n+\n+\t\t\t\tdsts.d32 =\n+\t\t\t\t    DWC_READ_REG32(&GET_CORE_IF(pcd)->dev_if->\n+\t\t\t\t\t\t   dev_global_regs->dsts);\n+\t\t\t\tdwc_ep->next_frame = dsts.b.soffn;\n+\n+\t\t\t\tdwc_otg_iso_ep_start_frm_transfer(GET_CORE_IF\n+\t\t\t\t\t\t\t\t  (pcd),\n+\t\t\t\t\t\t\t\t  dwc_ep);\n+\t\t\t}\n+\t\t}\n+\t}\n+\n+#else\n+\tdepctl_data_t depctl = {.d32 = 0 };\n+\tdwc_ep_t *dwc_ep;\n+\tdwc_otg_dev_if_t *dev_if;\n+\tint i;\n+\tdev_if = GET_CORE_IF(pcd)->dev_if;\n+\n+\tDWC_DEBUGPL(DBG_PCD,\"Incomplete ISO IN \\n\");\n+\n+\tfor (i = 1; i <= dev_if->num_in_eps; ++i) {\n+\t\tdwc_ep = &pcd->in_ep[i-1].dwc_ep;\n+\t\tdepctl.d32 =\n+\t\t\tDWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl);\n+\t\tif (depctl.b.epena && dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {\n+\t\t\tif (drop_transfer(dwc_ep->frame_num, GET_CORE_IF(pcd)->frame_num,\n+\t\t\t\t\t\t\tdwc_ep->frm_overrun))\n+\t\t\t{\n+\t\t\t\tdepctl.d32 =\n+\t\t\t\t\tDWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl);\n+\t\t\t\tdepctl.b.snak = 1;\n+\t\t\t\tdepctl.b.epdis = 1;\n+\t\t\t\tDWC_MODIFY_REG32(&dev_if->in_ep_regs[i]->diepctl, depctl.d32, depctl.d32);\n+\t\t\t}\n+\t\t}\n+\t}\n+\n+\t/*intr_mask.b.incomplisoin = 1;\n+\tDWC_MODIFY_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,\n+\t\t\t intr_mask.d32, 0);\t */\n+#endif\t\t\t\t//DWC_EN_ISOC\n+\n+\t/* Clear interrupt */\n+\tgintsts.d32 = 0;\n+\tgintsts.b.incomplisoin = 1;\n+\tDWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,\n+\t\t\tgintsts.d32);\n+\n+\treturn 1;\n+}\n+\n+/**\n+ * Incomplete ISO OUT Transfer Interrupt.\n+ *\n+ * This interrupt indicates that the core has dropped an ISO OUT\n+ * packet. The following conditions can be the cause:\n+ * - FIFO Full, the entire packet would not fit in the FIFO.\n+ * - CRC Error\n+ * - Corrupted Token\n+ * The follow actions will be taken:\n+ *\t-#\tDetermine the EP\n+ *\t-#\tSet incomplete flag in dwc_ep structure\n+ *\t-#\tRead any data from the FIFO\n+ *\t-#\tDisable EP. When \"Endpoint Disabled\" interrupt is received\n+ *\t\tre-enable EP.\n+ */\n+int32_t dwc_otg_pcd_handle_incomplete_isoc_out_intr(dwc_otg_pcd_t * pcd)\n+{\n+\n+\tgintsts_data_t gintsts;\n+\n+#ifdef DWC_EN_ISOC\n+\tdwc_otg_dev_if_t *dev_if;\n+\tdeptsiz_data_t deptsiz = {.d32 = 0 };\n+\tdepctl_data_t depctl = {.d32 = 0 };\n+\tdsts_data_t dsts = {.d32 = 0 };\n+\tdwc_ep_t *dwc_ep;\n+\tint i;\n+\n+\tdev_if = GET_CORE_IF(pcd)->dev_if;\n+\n+\tfor (i = 1; i <= dev_if->num_out_eps; ++i) {\n+\t\tdwc_ep = &pcd->in_ep[i].dwc_ep;\n+\t\tif (pcd->out_ep[i].dwc_ep.active &&\n+\t\t    pcd->out_ep[i].dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) {\n+\t\t\tdeptsiz.d32 =\n+\t\t\t    DWC_READ_REG32(&dev_if->out_ep_regs[i]->doeptsiz);\n+\t\t\tdepctl.d32 =\n+\t\t\t    DWC_READ_REG32(&dev_if->out_ep_regs[i]->doepctl);\n+\n+\t\t\tif (depctl.b.epdis && deptsiz.d32) {\n+\t\t\t\tset_current_pkt_info(GET_CORE_IF(pcd),\n+\t\t\t\t\t\t     &pcd->out_ep[i].dwc_ep);\n+\t\t\t\tif (dwc_ep->cur_pkt >= dwc_ep->pkt_cnt) {\n+\t\t\t\t\tdwc_ep->cur_pkt = 0;\n+\t\t\t\t\tdwc_ep->proc_buf_num =\n+\t\t\t\t\t    (dwc_ep->proc_buf_num ^ 1) & 0x1;\n+\n+\t\t\t\t\tif (dwc_ep->proc_buf_num) {\n+\t\t\t\t\t\tdwc_ep->cur_pkt_addr =\n+\t\t\t\t\t\t    dwc_ep->xfer_buff1;\n+\t\t\t\t\t\tdwc_ep->cur_pkt_dma_addr =\n+\t\t\t\t\t\t    dwc_ep->dma_addr1;\n+\t\t\t\t\t} else {\n+\t\t\t\t\t\tdwc_ep->cur_pkt_addr =\n+\t\t\t\t\t\t    dwc_ep->xfer_buff0;\n+\t\t\t\t\t\tdwc_ep->cur_pkt_dma_addr =\n+\t\t\t\t\t\t    dwc_ep->dma_addr0;\n+\t\t\t\t\t}\n+\n+\t\t\t\t}\n+\n+\t\t\t\tdsts.d32 =\n+\t\t\t\t    DWC_READ_REG32(&GET_CORE_IF(pcd)->dev_if->\n+\t\t\t\t\t\t   dev_global_regs->dsts);\n+\t\t\t\tdwc_ep->next_frame = dsts.b.soffn;\n+\n+\t\t\t\tdwc_otg_iso_ep_start_frm_transfer(GET_CORE_IF\n+\t\t\t\t\t\t\t\t  (pcd),\n+\t\t\t\t\t\t\t\t  dwc_ep);\n+\t\t\t}\n+\t\t}\n+\t}\n+#else\n+\t/** @todo implement ISR */\n+\tgintmsk_data_t intr_mask = {.d32 = 0 };\n+\tdwc_otg_core_if_t *core_if;\n+\tdeptsiz_data_t deptsiz = {.d32 = 0 };\n+\tdepctl_data_t depctl = {.d32 = 0 };\n+\tdctl_data_t dctl = {.d32 = 0 };\n+\tdwc_ep_t *dwc_ep = NULL;\n+\tint i;\n+\tcore_if = GET_CORE_IF(pcd);\n+\n+\tfor (i = 0; i < core_if->dev_if->num_out_eps; ++i) {\n+\t\tdwc_ep = &pcd->out_ep[i].dwc_ep;\n+\t\tdepctl.d32 =\n+\t\t\tDWC_READ_REG32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->doepctl);\n+\t\tif (depctl.b.epena && depctl.b.dpid == (core_if->frame_num & 0x1)) {\n+\t\t\tcore_if->dev_if->isoc_ep = dwc_ep;\n+\t\t\tdeptsiz.d32 =\n+\t\t\t\t\tDWC_READ_REG32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->doeptsiz);\n+\t\t\t\tbreak;\n+\t\t}\n+\t}\n+\tdctl.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl);\n+\tgintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts);\n+\tintr_mask.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintmsk);\n+\n+\tif (!intr_mask.b.goutnakeff) {\n+\t\t/* Unmask it */\n+\t\tintr_mask.b.goutnakeff = 1;\n+\t\tDWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, intr_mask.d32);\n+\t}\n+\tif (!gintsts.b.goutnakeff) {\n+\t\tdctl.b.sgoutnak = 1;\n+\t}\n+\tDWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32);\n+\n+\tdepctl.d32 = DWC_READ_REG32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->doepctl);\n+\tif (depctl.b.epena) {\n+\t\tdepctl.b.epdis = 1;\n+\t\tdepctl.b.snak = 1;\n+\t}\n+\tDWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->doepctl, depctl.d32);\n+\n+\tintr_mask.d32 = 0;\n+\tintr_mask.b.incomplisoout = 1;\n+\n+#endif /* DWC_EN_ISOC */\n+\n+\t/* Clear interrupt */\n+\tgintsts.d32 = 0;\n+\tgintsts.b.incomplisoout = 1;\n+\tDWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,\n+\t\t\tgintsts.d32);\n+\n+\treturn 1;\n+}\n+\n+/**\n+ * This function handles the Global IN NAK Effective interrupt.\n+ *\n+ */\n+int32_t dwc_otg_pcd_handle_in_nak_effective(dwc_otg_pcd_t * pcd)\n+{\n+\tdwc_otg_dev_if_t *dev_if = GET_CORE_IF(pcd)->dev_if;\n+\tdepctl_data_t diepctl = {.d32 = 0 };\n+\tgintmsk_data_t intr_mask = {.d32 = 0 };\n+\tgintsts_data_t gintsts;\n+\tdwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);\n+\tint i;\n+\n+\tDWC_DEBUGPL(DBG_PCD, \"Global IN NAK Effective\\n\");\n+\n+\t/* Disable all active IN EPs */\n+\tfor (i = 0; i <= dev_if->num_in_eps; i++) {\n+\t\tdiepctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl);\n+\t\tif (!(diepctl.b.eptype & 1) && diepctl.b.epena) {\n+\t\t\tif (core_if->start_predict > 0)\n+\t\t\t\tcore_if->start_predict++;\n+\t\t\tdiepctl.b.epdis = 1;\n+\t\t\tdiepctl.b.snak = 1;\n+\t\t\tDWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepctl, diepctl.d32);\n+\t\t}\n+\t}\n+\n+\n+\t/* Disable the Global IN NAK Effective Interrupt */\n+\tintr_mask.b.ginnakeff = 1;\n+\tDWC_MODIFY_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,\n+\t\t\t intr_mask.d32, 0);\n+\n+\t/* Clear interrupt */\n+\tgintsts.d32 = 0;\n+\tgintsts.b.ginnakeff = 1;\n+\tDWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,\n+\t\t\tgintsts.d32);\n+\n+\treturn 1;\n+}\n+\n+/**\n+ * OUT NAK Effective.\n+ *\n+ */\n+int32_t dwc_otg_pcd_handle_out_nak_effective(dwc_otg_pcd_t * pcd)\n+{\n+\tdwc_otg_dev_if_t *dev_if = GET_CORE_IF(pcd)->dev_if;\n+\tgintmsk_data_t intr_mask = {.d32 = 0 };\n+\tgintsts_data_t gintsts;\n+\tdepctl_data_t doepctl;\n+\tint i;\n+\n+\t/* Disable the Global OUT NAK Effective Interrupt */\n+\tintr_mask.b.goutnakeff = 1;\n+\tDWC_MODIFY_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,\n+\t\tintr_mask.d32, 0);\n+\n+\t/* If DEV OUT NAK enabled*/\n+\tif (pcd->core_if->core_params->dev_out_nak) {\n+\t\t/* Run over all out endpoints to determine the ep number on\n+\t\t * which the timeout has happened\n+\t\t */\n+\t\tfor (i = 0; i <= dev_if->num_out_eps; i++) {\n+\t\t\tif ( pcd->core_if->ep_xfer_info[i].state == 2 )\n+\t\t\t\tbreak;\n+\t\t}\n+\t\tif (i > dev_if->num_out_eps) {\n+\t\t\tdctl_data_t dctl;\n+\t\t\tdctl.d32 =\n+\t\t\t    DWC_READ_REG32(&dev_if->dev_global_regs->dctl);\n+\t\t\tdctl.b.cgoutnak = 1;\n+\t\t\tDWC_WRITE_REG32(&dev_if->dev_global_regs->dctl,\n+\t\t\t\tdctl.d32);\n+\t\t\tgoto out;\n+\t\t}\n+\n+\t\t/* Disable the endpoint */\n+\t\tdoepctl.d32 = DWC_READ_REG32(&dev_if->out_ep_regs[i]->doepctl);\n+\t\tif (doepctl.b.epena) {\n+\t\t\tdoepctl.b.epdis = 1;\n+\t\t\tdoepctl.b.snak = 1;\n+\t\t}\n+\t\tDWC_WRITE_REG32(&dev_if->out_ep_regs[i]->doepctl, doepctl.d32);\n+\t\treturn 1;\n+\t}\n+\t/* We come here from Incomplete ISO OUT handler */\n+\tif (dev_if->isoc_ep) {\n+\t\tdwc_ep_t *dwc_ep = (dwc_ep_t *)dev_if->isoc_ep;\n+\t\tuint32_t epnum = dwc_ep->num;\n+\t\tdoepint_data_t doepint;\n+\t\tdoepint.d32 =\n+\t\t    DWC_READ_REG32(&dev_if->out_ep_regs[dwc_ep->num]->doepint);\n+\t\tdev_if->isoc_ep = NULL;\n+\t\tdoepctl.d32 =\n+\t\t    DWC_READ_REG32(&dev_if->out_ep_regs[epnum]->doepctl);\n+\t\tDWC_PRINTF(\"Before disable DOEPCTL = %08x\\n\", doepctl.d32);\n+\t\tif (doepctl.b.epena) {\n+\t\t\tdoepctl.b.epdis = 1;\n+\t\t\tdoepctl.b.snak = 1;\n+\t\t}\n+\t\tDWC_WRITE_REG32(&dev_if->out_ep_regs[epnum]->doepctl,\n+\t\t\t\tdoepctl.d32);\n+\t\treturn 1;\n+\t} else\n+\t\tDWC_PRINTF(\"INTERRUPT Handler not implemented for %s\\n\",\n+\t\t\t   \"Global OUT NAK Effective\\n\");\n+\n+out:\n+\t/* Clear interrupt */\n+\tgintsts.d32 = 0;\n+\tgintsts.b.goutnakeff = 1;\n+\tDWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,\n+\t\t\tgintsts.d32);\n+\n+\treturn 1;\n+}\n+\n+/**\n+ * PCD interrupt handler.\n+ *\n+ * The PCD handles the device interrupts.  Many conditions can cause a\n+ * device interrupt. When an interrupt occurs, the device interrupt\n+ * service routine determines the cause of the interrupt and\n+ * dispatches handling to the appropriate function. These interrupt\n+ * handling functions are described below.\n+ *\n+ * All interrupt registers are processed from LSB to MSB.\n+ *\n+ */\n+int32_t dwc_otg_pcd_handle_intr(dwc_otg_pcd_t * pcd)\n+{\n+\tdwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);\n+#ifdef VERBOSE\n+\tdwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;\n+#endif\n+\tgintsts_data_t gintr_status;\n+\tint32_t retval = 0;\n+\n+\t/* Exit from ISR if core is hibernated */\n+\tif (core_if->hibernation_suspend == 1) {\n+\t\treturn retval;\n+\t}\n+#ifdef VERBOSE\n+\tDWC_DEBUGPL(DBG_ANY, \"%s() gintsts=%08x\t gintmsk=%08x\\n\",\n+\t\t    __func__,\n+\t\t    DWC_READ_REG32(&global_regs->gintsts),\n+\t\t    DWC_READ_REG32(&global_regs->gintmsk));\n+#endif\n+\n+\tif (dwc_otg_is_device_mode(core_if)) {\n+\t\tDWC_SPINLOCK(pcd->lock);\n+#ifdef VERBOSE\n+\t\tDWC_DEBUGPL(DBG_PCDV, \"%s() gintsts=%08x  gintmsk=%08x\\n\",\n+\t\t\t    __func__,\n+\t\t\t    DWC_READ_REG32(&global_regs->gintsts),\n+\t\t\t    DWC_READ_REG32(&global_regs->gintmsk));\n+#endif\n+\n+\t\tgintr_status.d32 = dwc_otg_read_core_intr(core_if);\n+\n+\t\tDWC_DEBUGPL(DBG_PCDV, \"%s: gintsts&gintmsk=%08x\\n\",\n+\t\t\t    __func__, gintr_status.d32);\n+\n+\t\tif (gintr_status.b.sofintr) {\n+\t\t\tretval |= dwc_otg_pcd_handle_sof_intr(pcd);\n+\t\t}\n+\t\tif (gintr_status.b.rxstsqlvl) {\n+\t\t\tretval |=\n+\t\t\t    dwc_otg_pcd_handle_rx_status_q_level_intr(pcd);\n+\t\t}\n+\t\tif (gintr_status.b.nptxfempty) {\n+\t\t\tretval |= dwc_otg_pcd_handle_np_tx_fifo_empty_intr(pcd);\n+\t\t}\n+\t\tif (gintr_status.b.goutnakeff) {\n+\t\t\tretval |= dwc_otg_pcd_handle_out_nak_effective(pcd);\n+\t\t}\n+\t\tif (gintr_status.b.i2cintr) {\n+\t\t\tretval |= dwc_otg_pcd_handle_i2c_intr(pcd);\n+\t\t}\n+\t\tif (gintr_status.b.erlysuspend) {\n+\t\t\tretval |= dwc_otg_pcd_handle_early_suspend_intr(pcd);\n+\t\t}\n+\t\tif (gintr_status.b.usbreset) {\n+\t\t\tretval |= dwc_otg_pcd_handle_usb_reset_intr(pcd);\n+\t\t}\n+\t\tif (gintr_status.b.enumdone) {\n+\t\t\tretval |= dwc_otg_pcd_handle_enum_done_intr(pcd);\n+\t\t}\n+\t\tif (gintr_status.b.isooutdrop) {\n+\t\t\tretval |=\n+\t\t\t    dwc_otg_pcd_handle_isoc_out_packet_dropped_intr\n+\t\t\t    (pcd);\n+\t\t}\n+\t\tif (gintr_status.b.eopframe) {\n+\t\t\tretval |=\n+\t\t\t    dwc_otg_pcd_handle_end_periodic_frame_intr(pcd);\n+\t\t}\n+\t\tif (gintr_status.b.inepint) {\n+\t\t\tif (!core_if->multiproc_int_enable) {\n+\t\t\t\tretval |= dwc_otg_pcd_handle_in_ep_intr(pcd);\n+\t\t\t}\n+\t\t}\n+\t\tif (gintr_status.b.outepintr) {\n+\t\t\tif (!core_if->multiproc_int_enable) {\n+\t\t\t\tretval |= dwc_otg_pcd_handle_out_ep_intr(pcd);\n+\t\t\t}\n+\t\t}\n+\t\tif (gintr_status.b.epmismatch) {\n+\t\t\tretval |= dwc_otg_pcd_handle_ep_mismatch_intr(pcd);\n+\t\t}\n+\t\tif (gintr_status.b.fetsusp) {\n+\t\t\tretval |= dwc_otg_pcd_handle_ep_fetsusp_intr(pcd);\n+\t\t}\n+\t\tif (gintr_status.b.ginnakeff) {\n+\t\t\tretval |= dwc_otg_pcd_handle_in_nak_effective(pcd);\n+\t\t}\n+\t\tif (gintr_status.b.incomplisoin) {\n+\t\t\tretval |=\n+\t\t\t    dwc_otg_pcd_handle_incomplete_isoc_in_intr(pcd);\n+\t\t}\n+\t\tif (gintr_status.b.incomplisoout) {\n+\t\t\tretval |=\n+\t\t\t    dwc_otg_pcd_handle_incomplete_isoc_out_intr(pcd);\n+\t\t}\n+\n+\t\t/* In MPI mode Device Endpoints interrupts are asserted\n+\t\t * without setting outepintr and inepint bits set, so these\n+\t\t * Interrupt handlers are called without checking these bit-fields\n+\t\t */\n+\t\tif (core_if->multiproc_int_enable) {\n+\t\t\tretval |= dwc_otg_pcd_handle_in_ep_intr(pcd);\n+\t\t\tretval |= dwc_otg_pcd_handle_out_ep_intr(pcd);\n+\t\t}\n+#ifdef VERBOSE\n+\t\tDWC_DEBUGPL(DBG_PCDV, \"%s() gintsts=%0x\\n\", __func__,\n+\t\t\t    DWC_READ_REG32(&global_regs->gintsts));\n+#endif\n+\t\tDWC_SPINUNLOCK(pcd->lock);\n+\t}\n+\treturn retval;\n+}\n+\n+#endif /* DWC_HOST_ONLY */\n--- /dev/null\n+++ b/drivers/usb/host/dwc_otg/dwc_otg_pcd_linux.c\n@@ -0,0 +1,1262 @@\n+ /* ==========================================================================\n+  * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd_linux.c $\n+  * $Revision: #21 $\n+  * $Date: 2012/08/10 $\n+  * $Change: 2047372 $\n+  *\n+  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,\n+  * \"Software\") is an Unsupported proprietary work of Synopsys, Inc. unless\n+  * otherwise expressly agreed to in writing between Synopsys and you.\n+  *\n+  * The Software IS NOT an item of Licensed Software or Licensed Product under\n+  * any End User Software License Agreement or Agreement for Licensed Product\n+  * with Synopsys or any supplement thereto. You are permitted to use and\n+  * redistribute this Software in source and binary forms, with or without\n+  * modification, provided that redistributions of source code must retain this\n+  * notice. You may not view, use, disclose, copy or distribute this file or\n+  * any information contained herein except pursuant to this license grant from\n+  * Synopsys. If you do not agree with this notice, including the disclaimer\n+  * below, then you are not authorized to use the Software.\n+  *\n+  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN \"AS IS\" BASIS\n+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n+  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,\n+  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n+  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n+  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n+  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH\n+  * DAMAGE.\n+  * ========================================================================== */\n+#ifndef DWC_HOST_ONLY\n+\n+/** @file\n+ * This file implements the Peripheral Controller Driver.\n+ *\n+ * The Peripheral Controller Driver (PCD) is responsible for\n+ * translating requests from the Function Driver into the appropriate\n+ * actions on the DWC_otg controller. It isolates the Function Driver\n+ * from the specifics of the controller by providing an API to the\n+ * Function Driver.\n+ *\n+ * The Peripheral Controller Driver for Linux will implement the\n+ * Gadget API, so that the existing Gadget drivers can be used.\n+ * (Gadget Driver is the Linux terminology for a Function Driver.)\n+ *\n+ * The Linux Gadget API is defined in the header file\n+ * <code><linux/usb_gadget.h></code>.  The USB EP operations API is\n+ * defined in the structure <code>usb_ep_ops</code> and the USB\n+ * Controller API is defined in the structure\n+ * <code>usb_gadget_ops</code>.\n+ *\n+ */\n+\n+#include \"dwc_otg_os_dep.h\"\n+#include \"dwc_otg_pcd_if.h\"\n+#include \"dwc_otg_pcd.h\"\n+#include \"dwc_otg_driver.h\"\n+#include \"dwc_otg_dbg.h\"\n+\n+extern bool fiq_enable;\n+\n+static struct gadget_wrapper {\n+\tdwc_otg_pcd_t *pcd;\n+\n+\tstruct usb_gadget gadget;\n+\tstruct usb_gadget_driver *driver;\n+\n+\tstruct usb_ep ep0;\n+\tstruct usb_ep in_ep[16];\n+\tstruct usb_ep out_ep[16];\n+\n+} *gadget_wrapper;\n+\n+/* Display the contents of the buffer */\n+extern void dump_msg(const u8 * buf, unsigned int length);\n+/**\n+ * Get the dwc_otg_pcd_ep_t* from usb_ep* pointer - NULL in case\n+ * if the endpoint is not found\n+ */\n+static struct dwc_otg_pcd_ep *ep_from_handle(dwc_otg_pcd_t * pcd, void *handle)\n+{\n+\tint i;\n+\tif (pcd->ep0.priv == handle) {\n+\t\treturn &pcd->ep0;\n+\t}\n+\n+\tfor (i = 0; i < MAX_EPS_CHANNELS - 1; i++) {\n+\t\tif (pcd->in_ep[i].priv == handle)\n+\t\t\treturn &pcd->in_ep[i];\n+\t\tif (pcd->out_ep[i].priv == handle)\n+\t\t\treturn &pcd->out_ep[i];\n+\t}\n+\n+\treturn NULL;\n+}\n+\n+/* USB Endpoint Operations */\n+/*\n+ * The following sections briefly describe the behavior of the Gadget\n+ * API endpoint operations implemented in the DWC_otg driver\n+ * software. Detailed descriptions of the generic behavior of each of\n+ * these functions can be found in the Linux header file\n+ * include/linux/usb_gadget.h.\n+ *\n+ * The Gadget API provides wrapper functions for each of the function\n+ * pointers defined in usb_ep_ops. The Gadget Driver calls the wrapper\n+ * function, which then calls the underlying PCD function. The\n+ * following sections are named according to the wrapper\n+ * functions. Within each section, the corresponding DWC_otg PCD\n+ * function name is specified.\n+ *\n+ */\n+\n+/**\n+ * This function is called by the Gadget Driver for each EP to be\n+ * configured for the current configuration (SET_CONFIGURATION).\n+ *\n+ * This function initializes the dwc_otg_ep_t data structure, and then\n+ * calls dwc_otg_ep_activate.\n+ */\n+static int ep_enable(struct usb_ep *usb_ep,\n+\t\t     const struct usb_endpoint_descriptor *ep_desc)\n+{\n+\tint retval;\n+\n+\tDWC_DEBUGPL(DBG_PCDV, \"%s(%p,%p)\\n\", __func__, usb_ep, ep_desc);\n+\n+\tif (!usb_ep || !ep_desc || ep_desc->bDescriptorType != USB_DT_ENDPOINT) {\n+\t\tDWC_WARN(\"%s, bad ep or descriptor\\n\", __func__);\n+\t\treturn -EINVAL;\n+\t}\n+\tif (usb_ep == &gadget_wrapper->ep0) {\n+\t\tDWC_WARN(\"%s, bad ep(0)\\n\", __func__);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\t/* Check FIFO size? */\n+\tif (!ep_desc->wMaxPacketSize) {\n+\t\tDWC_WARN(\"%s, bad %s maxpacket\\n\", __func__, usb_ep->name);\n+\t\treturn -ERANGE;\n+\t}\n+\n+\tif (!gadget_wrapper->driver ||\n+\t    gadget_wrapper->gadget.speed == USB_SPEED_UNKNOWN) {\n+\t\tDWC_WARN(\"%s, bogus device state\\n\", __func__);\n+\t\treturn -ESHUTDOWN;\n+\t}\n+\n+\t/* Delete after check - MAS */\n+#if 0\n+\tnat = (uint32_t) ep_desc->wMaxPacketSize;\n+\tprintk(KERN_ALERT \"%s: nat (before) =%d\\n\", __func__, nat);\n+\tnat = (nat >> 11) & 0x03;\n+\tprintk(KERN_ALERT \"%s: nat (after) =%d\\n\", __func__, nat);\n+#endif\n+\tretval = dwc_otg_pcd_ep_enable(gadget_wrapper->pcd,\n+\t\t\t\t       (const uint8_t *)ep_desc,\n+\t\t\t\t       (void *)usb_ep);\n+\tif (retval) {\n+\t\tDWC_WARN(\"dwc_otg_pcd_ep_enable failed\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tusb_ep->maxpacket = le16_to_cpu(ep_desc->wMaxPacketSize);\n+\n+\treturn 0;\n+}\n+\n+/**\n+ * This function is called when an EP is disabled due to disconnect or\n+ * change in configuration. Any pending requests will terminate with a\n+ * status of -ESHUTDOWN.\n+ *\n+ * This function modifies the dwc_otg_ep_t data structure for this EP,\n+ * and then calls dwc_otg_ep_deactivate.\n+ */\n+static int ep_disable(struct usb_ep *usb_ep)\n+{\n+\tint retval;\n+\n+\tDWC_DEBUGPL(DBG_PCDV, \"%s(%p)\\n\", __func__, usb_ep);\n+\tif (!usb_ep) {\n+\t\tDWC_DEBUGPL(DBG_PCD, \"%s, %s not enabled\\n\", __func__,\n+\t\t\t    usb_ep ? usb_ep->name : NULL);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tretval = dwc_otg_pcd_ep_disable(gadget_wrapper->pcd, usb_ep);\n+\tif (retval) {\n+\t\tretval = -EINVAL;\n+\t}\n+\n+\treturn retval;\n+}\n+\n+/**\n+ * This function allocates a request object to use with the specified\n+ * endpoint.\n+ *\n+ * @param ep The endpoint to be used with with the request\n+ * @param gfp_flags the GFP_* flags to use.\n+ */\n+static struct usb_request *dwc_otg_pcd_alloc_request(struct usb_ep *ep,\n+\t\t\t\t\t\t     gfp_t gfp_flags)\n+{\n+\tstruct usb_request *usb_req;\n+\n+\tDWC_DEBUGPL(DBG_PCDV, \"%s(%p,%d)\\n\", __func__, ep, gfp_flags);\n+\tif (0 == ep) {\n+\t\tDWC_WARN(\"%s() %s\\n\", __func__, \"Invalid EP!\\n\");\n+\t\treturn 0;\n+\t}\n+\tusb_req = kzalloc(sizeof(*usb_req), gfp_flags);\n+\tif (0 == usb_req) {\n+\t\tDWC_WARN(\"%s() %s\\n\", __func__, \"request allocation failed!\\n\");\n+\t\treturn 0;\n+\t}\n+\tusb_req->dma = DWC_DMA_ADDR_INVALID;\n+\n+\treturn usb_req;\n+}\n+\n+/**\n+ * This function frees a request object.\n+ *\n+ * @param ep The endpoint associated with the request\n+ * @param req The request being freed\n+ */\n+static void dwc_otg_pcd_free_request(struct usb_ep *ep, struct usb_request *req)\n+{\n+\tDWC_DEBUGPL(DBG_PCDV, \"%s(%p,%p)\\n\", __func__, ep, req);\n+\n+\tif (0 == ep || 0 == req) {\n+\t\tDWC_WARN(\"%s() %s\\n\", __func__,\n+\t\t\t \"Invalid ep or req argument!\\n\");\n+\t\treturn;\n+\t}\n+\n+\tkfree(req);\n+}\n+\n+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28)\n+/**\n+ * This function allocates an I/O buffer to be used for a transfer\n+ * to/from the specified endpoint.\n+ *\n+ * @param usb_ep The endpoint to be used with with the request\n+ * @param bytes The desired number of bytes for the buffer\n+ * @param dma Pointer to the buffer's DMA address; must be valid\n+ * @param gfp_flags the GFP_* flags to use.\n+ * @return address of a new buffer or null is buffer could not be allocated.\n+ */\n+static void *dwc_otg_pcd_alloc_buffer(struct usb_ep *usb_ep, unsigned bytes,\n+\t\t\t\t      dma_addr_t * dma, gfp_t gfp_flags)\n+{\n+\tvoid *buf;\n+\tdwc_otg_pcd_t *pcd = 0;\n+\n+\tpcd = gadget_wrapper->pcd;\n+\n+\tDWC_DEBUGPL(DBG_PCDV, \"%s(%p,%d,%p,%0x)\\n\", __func__, usb_ep, bytes,\n+\t\t    dma, gfp_flags);\n+\n+\t/* Check dword alignment */\n+\tif ((bytes & 0x3UL) != 0) {\n+\t\tDWC_WARN(\"%s() Buffer size is not a multiple of\"\n+\t\t\t \"DWORD size (%d)\", __func__, bytes);\n+\t}\n+\n+\tbuf = dma_alloc_coherent(NULL, bytes, dma, gfp_flags);\n+\tWARN_ON(!buf);\n+\n+\t/* Check dword alignment */\n+\tif (((int)buf & 0x3UL) != 0) {\n+\t\tDWC_WARN(\"%s() Buffer is not DWORD aligned (%p)\",\n+\t\t\t __func__, buf);\n+\t}\n+\n+\treturn buf;\n+}\n+\n+/**\n+ * This function frees an I/O buffer that was allocated by alloc_buffer.\n+ *\n+ * @param usb_ep the endpoint associated with the buffer\n+ * @param buf address of the buffer\n+ * @param dma The buffer's DMA address\n+ * @param bytes The number of bytes of the buffer\n+ */\n+static void dwc_otg_pcd_free_buffer(struct usb_ep *usb_ep, void *buf,\n+\t\t\t\t    dma_addr_t dma, unsigned bytes)\n+{\n+\tdwc_otg_pcd_t *pcd = 0;\n+\n+\tpcd = gadget_wrapper->pcd;\n+\n+\tDWC_DEBUGPL(DBG_PCDV, \"%s(%p,%0x,%d)\\n\", __func__, buf, dma, bytes);\n+\n+\tdma_free_coherent(NULL, bytes, buf, dma);\n+}\n+#endif\n+\n+/**\n+ * This function is used to submit an I/O Request to an EP.\n+ *\n+ *\t- When the request completes the request's completion callback\n+ *\t  is called to return the request to the driver.\n+ *\t- An EP, except control EPs, may have multiple requests\n+ *\t  pending.\n+ *\t- Once submitted the request cannot be examined or modified.\n+ *\t- Each request is turned into one or more packets.\n+ *\t- A BULK EP can queue any amount of data; the transfer is\n+ *\t  packetized.\n+ *\t- Zero length Packets are specified with the request 'zero'\n+ *\t  flag.\n+ */\n+static int ep_queue(struct usb_ep *usb_ep, struct usb_request *usb_req,\n+\t\t    gfp_t gfp_flags)\n+{\n+\tdwc_otg_pcd_t *pcd;\n+\tstruct dwc_otg_pcd_ep *ep = NULL;\n+\tint retval = 0, is_isoc_ep = 0;\n+\tdma_addr_t dma_addr = DWC_DMA_ADDR_INVALID;\n+\n+\tDWC_DEBUGPL(DBG_PCDV, \"%s(%p,%p,%d)\\n\",\n+\t\t    __func__, usb_ep, usb_req, gfp_flags);\n+\n+\tif (!usb_req || !usb_req->complete || !usb_req->buf) {\n+\t\tDWC_WARN(\"bad params\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (!usb_ep) {\n+\t\tDWC_WARN(\"bad ep\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tpcd = gadget_wrapper->pcd;\n+\tif (!gadget_wrapper->driver ||\n+\t    gadget_wrapper->gadget.speed == USB_SPEED_UNKNOWN) {\n+\t\tDWC_DEBUGPL(DBG_PCDV, \"gadget.speed=%d\\n\",\n+\t\t\t    gadget_wrapper->gadget.speed);\n+\t\tDWC_WARN(\"bogus device state\\n\");\n+\t\treturn -ESHUTDOWN;\n+\t}\n+\n+\tDWC_DEBUGPL(DBG_PCD, \"%s queue req %p, len %d buf %p\\n\",\n+\t\t    usb_ep->name, usb_req, usb_req->length, usb_req->buf);\n+\n+\tusb_req->status = -EINPROGRESS;\n+\tusb_req->actual = 0;\n+\n+\tep = ep_from_handle(pcd, usb_ep);\n+\tif (ep == NULL)\n+\t\tis_isoc_ep = 0;\n+\telse\n+\t\tis_isoc_ep = (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) ? 1 : 0;\n+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28)\n+\tdma_addr = usb_req->dma;\n+#else\n+\tif (GET_CORE_IF(pcd)->dma_enable) {\n+                dwc_otg_device_t *otg_dev = gadget_wrapper->pcd->otg_dev;\n+                struct device *dev = NULL;\n+\n+                if (otg_dev != NULL)\n+                        dev = DWC_OTG_OS_GETDEV(otg_dev->os_dep);\n+\n+\t\tif (usb_req->length != 0 &&\n+                    usb_req->dma == DWC_DMA_ADDR_INVALID) {\n+                        dma_addr = dma_map_single(dev, usb_req->buf,\n+                                                  usb_req->length,\n+                                                  ep->dwc_ep.is_in ?\n+                                                        DMA_TO_DEVICE:\n+                                                        DMA_FROM_DEVICE);\n+\t\t}\n+\t}\n+#endif\n+\n+#ifdef DWC_UTE_PER_IO\n+\tif (is_isoc_ep == 1) {\n+\t\tretval = dwc_otg_pcd_xiso_ep_queue(pcd, usb_ep, usb_req->buf, dma_addr,\n+\t\t\tusb_req->length, usb_req->zero, usb_req,\n+\t\t\tgfp_flags == GFP_ATOMIC ? 1 : 0, &usb_req->ext_req);\n+\t\tif (retval)\n+\t\t\treturn -EINVAL;\n+\n+\t\treturn 0;\n+\t}\n+#endif\n+\tretval = dwc_otg_pcd_ep_queue(pcd, usb_ep, usb_req->buf, dma_addr,\n+\t\t\t\t      usb_req->length, usb_req->zero, usb_req,\n+\t\t\t\t      gfp_flags == GFP_ATOMIC ? 1 : 0);\n+\tif (retval) {\n+\t\treturn -EINVAL;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+/**\n+ * This function cancels an I/O request from an EP.\n+ */\n+static int ep_dequeue(struct usb_ep *usb_ep, struct usb_request *usb_req)\n+{\n+\tDWC_DEBUGPL(DBG_PCDV, \"%s(%p,%p)\\n\", __func__, usb_ep, usb_req);\n+\n+\tif (!usb_ep || !usb_req) {\n+\t\tDWC_WARN(\"bad argument\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\tif (!gadget_wrapper->driver ||\n+\t    gadget_wrapper->gadget.speed == USB_SPEED_UNKNOWN) {\n+\t\tDWC_WARN(\"bogus device state\\n\");\n+\t\treturn -ESHUTDOWN;\n+\t}\n+\tif (dwc_otg_pcd_ep_dequeue(gadget_wrapper->pcd, usb_ep, usb_req)) {\n+\t\treturn -EINVAL;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+/**\n+ * usb_ep_set_halt stalls an endpoint.\n+ *\n+ * usb_ep_clear_halt clears an endpoint halt and resets its data\n+ * toggle.\n+ *\n+ * Both of these functions are implemented with the same underlying\n+ * function. The behavior depends on the value argument.\n+ *\n+ * @param[in] usb_ep the Endpoint to halt or clear halt.\n+ * @param[in] value\n+ *\t- 0 means clear_halt.\n+ *\t- 1 means set_halt,\n+ *\t- 2 means clear stall lock flag.\n+ *\t- 3 means set  stall lock flag.\n+ */\n+static int ep_halt(struct usb_ep *usb_ep, int value)\n+{\n+\tint retval = 0;\n+\n+\tDWC_DEBUGPL(DBG_PCD, \"HALT %s %d\\n\", usb_ep->name, value);\n+\n+\tif (!usb_ep) {\n+\t\tDWC_WARN(\"bad ep\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tretval = dwc_otg_pcd_ep_halt(gadget_wrapper->pcd, usb_ep, value);\n+\tif (retval == -DWC_E_AGAIN) {\n+\t\treturn -EAGAIN;\n+\t} else if (retval) {\n+\t\tretval = -EINVAL;\n+\t}\n+\n+\treturn retval;\n+}\n+\n+//#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,30))\n+#if 0\n+/**\n+ * ep_wedge: sets the halt feature and ignores clear requests\n+ *\n+ * @usb_ep: the endpoint being wedged\n+ *\n+ * Use this to stall an endpoint and ignore CLEAR_FEATURE(HALT_ENDPOINT)\n+ * requests. If the gadget driver clears the halt status, it will\n+ * automatically unwedge the endpoint.\n+ *\n+ * Returns zero on success, else negative errno. *\n+ * Check usb_ep_set_wedge() at \"usb_gadget.h\" for details\n+ */\n+static int ep_wedge(struct usb_ep *usb_ep)\n+{\n+\tint retval = 0;\n+\n+\tDWC_DEBUGPL(DBG_PCD, \"WEDGE %s\\n\", usb_ep->name);\n+\n+\tif (!usb_ep) {\n+\t\tDWC_WARN(\"bad ep\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tretval = dwc_otg_pcd_ep_wedge(gadget_wrapper->pcd, usb_ep);\n+\tif (retval == -DWC_E_AGAIN) {\n+\t\tretval = -EAGAIN;\n+\t} else if (retval) {\n+\t\tretval = -EINVAL;\n+\t}\n+\n+\treturn retval;\n+}\n+#endif\n+\n+#ifdef DWC_EN_ISOC\n+/**\n+ * This function is used to submit an ISOC Transfer Request to an EP.\n+ *\n+ *\t- Every time a sync period completes the request's completion callback\n+ *\t  is called to provide data to the gadget driver.\n+ *\t- Once submitted the request cannot be modified.\n+ *\t- Each request is turned into periodic data packets untill ISO\n+ *\t  Transfer is stopped..\n+ */\n+static int iso_ep_start(struct usb_ep *usb_ep, struct usb_iso_request *req,\n+\t\t\tgfp_t gfp_flags)\n+{\n+\tint retval = 0;\n+\n+\tif (!req || !req->process_buffer || !req->buf0 || !req->buf1) {\n+\t\tDWC_WARN(\"bad params\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (!usb_ep) {\n+\t\tDWC_PRINTF(\"bad params\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\treq->status = -EINPROGRESS;\n+\n+\tretval =\n+\t    dwc_otg_pcd_iso_ep_start(gadget_wrapper->pcd, usb_ep, req->buf0,\n+\t\t\t\t     req->buf1, req->dma0, req->dma1,\n+\t\t\t\t     req->sync_frame, req->data_pattern_frame,\n+\t\t\t\t     req->data_per_frame,\n+\t\t\t\t     req->\n+\t\t\t\t     flags & USB_REQ_ISO_ASAP ? -1 :\n+\t\t\t\t     req->start_frame, req->buf_proc_intrvl,\n+\t\t\t\t     req, gfp_flags == GFP_ATOMIC ? 1 : 0);\n+\n+\tif (retval) {\n+\t\treturn -EINVAL;\n+\t}\n+\n+\treturn retval;\n+}\n+\n+/**\n+ * This function stops ISO EP Periodic Data Transfer.\n+ */\n+static int iso_ep_stop(struct usb_ep *usb_ep, struct usb_iso_request *req)\n+{\n+\tint retval = 0;\n+\tif (!usb_ep) {\n+\t\tDWC_WARN(\"bad ep\\n\");\n+\t}\n+\n+\tif (!gadget_wrapper->driver ||\n+\t    gadget_wrapper->gadget.speed == USB_SPEED_UNKNOWN) {\n+\t\tDWC_DEBUGPL(DBG_PCDV, \"gadget.speed=%d\\n\",\n+\t\t\t    gadget_wrapper->gadget.speed);\n+\t\tDWC_WARN(\"bogus device state\\n\");\n+\t}\n+\n+\tdwc_otg_pcd_iso_ep_stop(gadget_wrapper->pcd, usb_ep, req);\n+\tif (retval) {\n+\t\tretval = -EINVAL;\n+\t}\n+\n+\treturn retval;\n+}\n+\n+static struct usb_iso_request *alloc_iso_request(struct usb_ep *ep,\n+\t\t\t\t\t\t int packets, gfp_t gfp_flags)\n+{\n+\tstruct usb_iso_request *pReq = NULL;\n+\tuint32_t req_size;\n+\n+\treq_size = sizeof(struct usb_iso_request);\n+\treq_size +=\n+\t    (2 * packets * (sizeof(struct usb_gadget_iso_packet_descriptor)));\n+\n+\tpReq = kmalloc(req_size, gfp_flags);\n+\tif (!pReq) {\n+\t\tDWC_WARN(\"Can't allocate Iso Request\\n\");\n+\t\treturn 0;\n+\t}\n+\tpReq->iso_packet_desc0 = (void *)(pReq + 1);\n+\n+\tpReq->iso_packet_desc1 = pReq->iso_packet_desc0 + packets;\n+\n+\treturn pReq;\n+}\n+\n+static void free_iso_request(struct usb_ep *ep, struct usb_iso_request *req)\n+{\n+\tkfree(req);\n+}\n+\n+static struct usb_isoc_ep_ops dwc_otg_pcd_ep_ops = {\n+\t.ep_ops = {\n+\t\t   .enable = ep_enable,\n+\t\t   .disable = ep_disable,\n+\n+\t\t   .alloc_request = dwc_otg_pcd_alloc_request,\n+\t\t   .free_request = dwc_otg_pcd_free_request,\n+\n+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28)\n+\t\t   .alloc_buffer = dwc_otg_pcd_alloc_buffer,\n+\t\t   .free_buffer = dwc_otg_pcd_free_buffer,\n+#endif\n+\n+\t\t   .queue = ep_queue,\n+\t\t   .dequeue = ep_dequeue,\n+\n+\t\t   .set_halt = ep_halt,\n+\t\t   .fifo_status = 0,\n+\t\t   .fifo_flush = 0,\n+\t\t   },\n+\t.iso_ep_start = iso_ep_start,\n+\t.iso_ep_stop = iso_ep_stop,\n+\t.alloc_iso_request = alloc_iso_request,\n+\t.free_iso_request = free_iso_request,\n+};\n+\n+#else\n+\n+\tint (*enable) (struct usb_ep *ep,\n+\t\tconst struct usb_endpoint_descriptor *desc);\n+\tint (*disable) (struct usb_ep *ep);\n+\n+\tstruct usb_request *(*alloc_request) (struct usb_ep *ep,\n+\t\tgfp_t gfp_flags);\n+\tvoid (*free_request) (struct usb_ep *ep, struct usb_request *req);\n+\n+\tint (*queue) (struct usb_ep *ep, struct usb_request *req,\n+\t\tgfp_t gfp_flags);\n+\tint (*dequeue) (struct usb_ep *ep, struct usb_request *req);\n+\n+\tint (*set_halt) (struct usb_ep *ep, int value);\n+\tint (*set_wedge) (struct usb_ep *ep);\n+\n+\tint (*fifo_status) (struct usb_ep *ep);\n+\tvoid (*fifo_flush) (struct usb_ep *ep);\n+static struct usb_ep_ops dwc_otg_pcd_ep_ops = {\n+\t.enable = ep_enable,\n+\t.disable = ep_disable,\n+\n+\t.alloc_request = dwc_otg_pcd_alloc_request,\n+\t.free_request = dwc_otg_pcd_free_request,\n+\n+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28)\n+\t.alloc_buffer = dwc_otg_pcd_alloc_buffer,\n+\t.free_buffer = dwc_otg_pcd_free_buffer,\n+#else\n+\t/* .set_wedge = ep_wedge, */\n+        .set_wedge = NULL, /* uses set_halt instead */\n+#endif\n+\n+\t.queue = ep_queue,\n+\t.dequeue = ep_dequeue,\n+\n+\t.set_halt = ep_halt,\n+\t.fifo_status = 0,\n+\t.fifo_flush = 0,\n+\n+};\n+\n+#endif /* _EN_ISOC_ */\n+/*\tGadget Operations */\n+/**\n+ * The following gadget operations will be implemented in the DWC_otg\n+ * PCD. Functions in the API that are not described below are not\n+ * implemented.\n+ *\n+ * The Gadget API provides wrapper functions for each of the function\n+ * pointers defined in usb_gadget_ops. The Gadget Driver calls the\n+ * wrapper function, which then calls the underlying PCD function. The\n+ * following sections are named according to the wrapper functions\n+ * (except for ioctl, which doesn't have a wrapper function). Within\n+ * each section, the corresponding DWC_otg PCD function name is\n+ * specified.\n+ *\n+ */\n+\n+/**\n+ *Gets the USB Frame number of the last SOF.\n+ */\n+static int get_frame_number(struct usb_gadget *gadget)\n+{\n+\tstruct gadget_wrapper *d;\n+\n+\tDWC_DEBUGPL(DBG_PCDV, \"%s(%p)\\n\", __func__, gadget);\n+\n+\tif (gadget == 0) {\n+\t\treturn -ENODEV;\n+\t}\n+\n+\td = container_of(gadget, struct gadget_wrapper, gadget);\n+\treturn dwc_otg_pcd_get_frame_number(d->pcd);\n+}\n+\n+#ifdef CONFIG_USB_DWC_OTG_LPM\n+static int test_lpm_enabled(struct usb_gadget *gadget)\n+{\n+\tstruct gadget_wrapper *d;\n+\n+\td = container_of(gadget, struct gadget_wrapper, gadget);\n+\n+\treturn dwc_otg_pcd_is_lpm_enabled(d->pcd);\n+}\n+#endif\n+\n+/**\n+ * Initiates Session Request Protocol (SRP) to wakeup the host if no\n+ * session is in progress. If a session is already in progress, but\n+ * the device is suspended, remote wakeup signaling is started.\n+ *\n+ */\n+static int wakeup(struct usb_gadget *gadget)\n+{\n+\tstruct gadget_wrapper *d;\n+\n+\tDWC_DEBUGPL(DBG_PCDV, \"%s(%p)\\n\", __func__, gadget);\n+\n+\tif (gadget == 0) {\n+\t\treturn -ENODEV;\n+\t} else {\n+\t\td = container_of(gadget, struct gadget_wrapper, gadget);\n+\t}\n+\tdwc_otg_pcd_wakeup(d->pcd);\n+\treturn 0;\n+}\n+\n+static const struct usb_gadget_ops dwc_otg_pcd_ops = {\n+\t.get_frame = get_frame_number,\n+\t.wakeup = wakeup,\n+#ifdef CONFIG_USB_DWC_OTG_LPM\n+\t.lpm_support = test_lpm_enabled,\n+#endif\n+\t// current versions must always be self-powered\n+};\n+\n+static int _setup(dwc_otg_pcd_t * pcd, uint8_t * bytes)\n+{\n+\tint retval = -DWC_E_NOT_SUPPORTED;\n+\tif (gadget_wrapper->driver && gadget_wrapper->driver->setup) {\n+\t\tretval = gadget_wrapper->driver->setup(&gadget_wrapper->gadget,\n+\t\t\t\t\t\t       (struct usb_ctrlrequest\n+\t\t\t\t\t\t\t*)bytes);\n+\t}\n+\n+\tif (retval == -ENOTSUPP) {\n+\t\tretval = -DWC_E_NOT_SUPPORTED;\n+\t} else if (retval < 0) {\n+\t\tretval = -DWC_E_INVALID;\n+\t}\n+\n+\treturn retval;\n+}\n+\n+#ifdef DWC_EN_ISOC\n+static int _isoc_complete(dwc_otg_pcd_t * pcd, void *ep_handle,\n+\t\t\t  void *req_handle, int proc_buf_num)\n+{\n+\tint i, packet_count;\n+\tstruct usb_gadget_iso_packet_descriptor *iso_packet = 0;\n+\tstruct usb_iso_request *iso_req = req_handle;\n+\n+\tif (proc_buf_num) {\n+\t\tiso_packet = iso_req->iso_packet_desc1;\n+\t} else {\n+\t\tiso_packet = iso_req->iso_packet_desc0;\n+\t}\n+\tpacket_count =\n+\t    dwc_otg_pcd_get_iso_packet_count(pcd, ep_handle, req_handle);\n+\tfor (i = 0; i < packet_count; ++i) {\n+\t\tint status;\n+\t\tint actual;\n+\t\tint offset;\n+\t\tdwc_otg_pcd_get_iso_packet_params(pcd, ep_handle, req_handle,\n+\t\t\t\t\t\t  i, &status, &actual, &offset);\n+\t\tswitch (status) {\n+\t\tcase -DWC_E_NO_DATA:\n+\t\t\tstatus = -ENODATA;\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tif (status) {\n+\t\t\t\tDWC_PRINTF(\"unknown status in isoc packet\\n\");\n+\t\t\t}\n+\n+\t\t}\n+\t\tiso_packet[i].status = status;\n+\t\tiso_packet[i].offset = offset;\n+\t\tiso_packet[i].actual_length = actual;\n+\t}\n+\n+\tiso_req->status = 0;\n+\tiso_req->process_buffer(ep_handle, iso_req);\n+\n+\treturn 0;\n+}\n+#endif /* DWC_EN_ISOC */\n+\n+#ifdef DWC_UTE_PER_IO\n+/**\n+ * Copy the contents of the extended request to the Linux usb_request's\n+ * extended part and call the gadget's completion.\n+ *\n+ * @param pcd\t\t\tPointer to the pcd structure\n+ * @param ep_handle\t\tVoid pointer to the usb_ep structure\n+ * @param req_handle\tVoid pointer to the usb_request structure\n+ * @param status\t\tRequest status returned from the portable logic\n+ * @param ereq_port\t\tVoid pointer to the extended request structure\n+ *\t\t\t\t\t\tcreated in the the portable part that contains the\n+ *\t\t\t\t\t\tresults of the processed iso packets.\n+ */\n+static int _xisoc_complete(dwc_otg_pcd_t * pcd, void *ep_handle,\n+\t\t\t   void *req_handle, int32_t status, void *ereq_port)\n+{\n+\tstruct dwc_ute_iso_req_ext *ereqorg = NULL;\n+\tstruct dwc_iso_xreq_port *ereqport = NULL;\n+\tstruct dwc_ute_iso_packet_descriptor *desc_org = NULL;\n+\tint i;\n+\tstruct usb_request *req;\n+\t//struct dwc_ute_iso_packet_descriptor *\n+\t//int status = 0;\n+\n+\treq = (struct usb_request *)req_handle;\n+\tereqorg = &req->ext_req;\n+\tereqport = (struct dwc_iso_xreq_port *)ereq_port;\n+\tdesc_org = ereqorg->per_io_frame_descs;\n+\n+\tif (req && req->complete) {\n+\t\t/* Copy the request data from the portable logic to our request */\n+\t\tfor (i = 0; i < ereqport->pio_pkt_count; i++) {\n+\t\t\tdesc_org[i].actual_length =\n+\t\t\t    ereqport->per_io_frame_descs[i].actual_length;\n+\t\t\tdesc_org[i].status =\n+\t\t\t    ereqport->per_io_frame_descs[i].status;\n+\t\t}\n+\n+\t\tswitch (status) {\n+\t\tcase -DWC_E_SHUTDOWN:\n+\t\t\treq->status = -ESHUTDOWN;\n+\t\t\tbreak;\n+\t\tcase -DWC_E_RESTART:\n+\t\t\treq->status = -ECONNRESET;\n+\t\t\tbreak;\n+\t\tcase -DWC_E_INVALID:\n+\t\t\treq->status = -EINVAL;\n+\t\t\tbreak;\n+\t\tcase -DWC_E_TIMEOUT:\n+\t\t\treq->status = -ETIMEDOUT;\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\treq->status = status;\n+\t\t}\n+\n+\t\t/* And call the gadget's completion */\n+\t\treq->complete(ep_handle, req);\n+\t}\n+\n+\treturn 0;\n+}\n+#endif /* DWC_UTE_PER_IO */\n+\n+static int _complete(dwc_otg_pcd_t * pcd, void *ep_handle,\n+\t\t     void *req_handle, int32_t status, uint32_t actual)\n+{\n+\tstruct usb_request *req = (struct usb_request *)req_handle;\n+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,27)\n+\tstruct dwc_otg_pcd_ep *ep = NULL;\n+#endif\n+\n+\tif (req && req->complete) {\n+\t\tswitch (status) {\n+\t\tcase -DWC_E_SHUTDOWN:\n+\t\t\treq->status = -ESHUTDOWN;\n+\t\t\tbreak;\n+\t\tcase -DWC_E_RESTART:\n+\t\t\treq->status = -ECONNRESET;\n+\t\t\tbreak;\n+\t\tcase -DWC_E_INVALID:\n+\t\t\treq->status = -EINVAL;\n+\t\t\tbreak;\n+\t\tcase -DWC_E_TIMEOUT:\n+\t\t\treq->status = -ETIMEDOUT;\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\treq->status = status;\n+\n+\t\t}\n+\n+\t\treq->actual = actual;\n+\t\tDWC_SPINUNLOCK(pcd->lock);\n+\t\treq->complete(ep_handle, req);\n+\t\tDWC_SPINLOCK(pcd->lock);\n+\t}\n+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,27)\n+\tep = ep_from_handle(pcd, ep_handle);\n+\tif (GET_CORE_IF(pcd)->dma_enable) {\n+                if (req->length != 0) {\n+                        dwc_otg_device_t *otg_dev = gadget_wrapper->pcd->otg_dev;\n+                        struct device *dev = NULL;\n+\n+                        if (otg_dev != NULL)\n+                                  dev = DWC_OTG_OS_GETDEV(otg_dev->os_dep);\n+\n+\t\t\tdma_unmap_single(dev, req->dma, req->length,\n+                                         ep->dwc_ep.is_in ?\n+                                                DMA_TO_DEVICE: DMA_FROM_DEVICE);\n+                }\n+\t}\n+#endif\n+\n+\treturn 0;\n+}\n+\n+static int _connect(dwc_otg_pcd_t * pcd, int speed)\n+{\n+\tgadget_wrapper->gadget.speed = speed;\n+\treturn 0;\n+}\n+\n+static int _disconnect(dwc_otg_pcd_t * pcd)\n+{\n+\tif (gadget_wrapper->driver && gadget_wrapper->driver->disconnect) {\n+\t\tgadget_wrapper->driver->disconnect(&gadget_wrapper->gadget);\n+\t}\n+\treturn 0;\n+}\n+\n+static int _resume(dwc_otg_pcd_t * pcd)\n+{\n+\tif (gadget_wrapper->driver && gadget_wrapper->driver->resume) {\n+\t\tgadget_wrapper->driver->resume(&gadget_wrapper->gadget);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int _suspend(dwc_otg_pcd_t * pcd)\n+{\n+\tif (gadget_wrapper->driver && gadget_wrapper->driver->suspend) {\n+\t\tgadget_wrapper->driver->suspend(&gadget_wrapper->gadget);\n+\t}\n+\treturn 0;\n+}\n+\n+/**\n+ * This function updates the otg values in the gadget structure.\n+ */\n+static int _hnp_changed(dwc_otg_pcd_t * pcd)\n+{\n+\n+\tif (!gadget_wrapper->gadget.is_otg)\n+\t\treturn 0;\n+\n+\tgadget_wrapper->gadget.b_hnp_enable = get_b_hnp_enable(pcd);\n+\tgadget_wrapper->gadget.a_hnp_support = get_a_hnp_support(pcd);\n+\tgadget_wrapper->gadget.a_alt_hnp_support = get_a_alt_hnp_support(pcd);\n+\treturn 0;\n+}\n+\n+static int _reset(dwc_otg_pcd_t * pcd)\n+{\n+\treturn 0;\n+}\n+\n+#ifdef DWC_UTE_CFI\n+static int _cfi_setup(dwc_otg_pcd_t * pcd, void *cfi_req)\n+{\n+\tint retval = -DWC_E_INVALID;\n+\tif (gadget_wrapper->driver->cfi_feature_setup) {\n+\t\tretval =\n+\t\t    gadget_wrapper->driver->\n+\t\t    cfi_feature_setup(&gadget_wrapper->gadget,\n+\t\t\t\t      (struct cfi_usb_ctrlrequest *)cfi_req);\n+\t}\n+\n+\treturn retval;\n+}\n+#endif\n+\n+static const struct dwc_otg_pcd_function_ops fops = {\n+\t.complete = _complete,\n+#ifdef DWC_EN_ISOC\n+\t.isoc_complete = _isoc_complete,\n+#endif\n+\t.setup = _setup,\n+\t.disconnect = _disconnect,\n+\t.connect = _connect,\n+\t.resume = _resume,\n+\t.suspend = _suspend,\n+\t.hnp_changed = _hnp_changed,\n+\t.reset = _reset,\n+#ifdef DWC_UTE_CFI\n+\t.cfi_setup = _cfi_setup,\n+#endif\n+#ifdef DWC_UTE_PER_IO\n+\t.xisoc_complete = _xisoc_complete,\n+#endif\n+};\n+\n+/**\n+ * This function is the top level PCD interrupt handler.\n+ */\n+static irqreturn_t dwc_otg_pcd_irq(int irq, void *dev)\n+{\n+\tdwc_otg_pcd_t *pcd = dev;\n+\tint32_t retval = IRQ_NONE;\n+\n+\tretval = dwc_otg_pcd_handle_intr(pcd);\n+\tif (retval != 0) {\n+\t\tS3C2410X_CLEAR_EINTPEND();\n+\t}\n+\treturn IRQ_RETVAL(retval);\n+}\n+\n+/**\n+ * This function initialized the usb_ep structures to there default\n+ * state.\n+ *\n+ * @param d Pointer on gadget_wrapper.\n+ */\n+void gadget_add_eps(struct gadget_wrapper *d)\n+{\n+\tstatic const char *names[] = {\n+\n+\t\t\"ep0\",\n+\t\t\"ep1in\",\n+\t\t\"ep2in\",\n+\t\t\"ep3in\",\n+\t\t\"ep4in\",\n+\t\t\"ep5in\",\n+\t\t\"ep6in\",\n+\t\t\"ep7in\",\n+\t\t\"ep8in\",\n+\t\t\"ep9in\",\n+\t\t\"ep10in\",\n+\t\t\"ep11in\",\n+\t\t\"ep12in\",\n+\t\t\"ep13in\",\n+\t\t\"ep14in\",\n+\t\t\"ep15in\",\n+\t\t\"ep1out\",\n+\t\t\"ep2out\",\n+\t\t\"ep3out\",\n+\t\t\"ep4out\",\n+\t\t\"ep5out\",\n+\t\t\"ep6out\",\n+\t\t\"ep7out\",\n+\t\t\"ep8out\",\n+\t\t\"ep9out\",\n+\t\t\"ep10out\",\n+\t\t\"ep11out\",\n+\t\t\"ep12out\",\n+\t\t\"ep13out\",\n+\t\t\"ep14out\",\n+\t\t\"ep15out\"\n+\t};\n+\n+\tint i;\n+\tstruct usb_ep *ep;\n+\tint8_t dev_endpoints;\n+\n+\tDWC_DEBUGPL(DBG_PCDV, \"%s\\n\", __func__);\n+\n+\tINIT_LIST_HEAD(&d->gadget.ep_list);\n+\td->gadget.ep0 = &d->ep0;\n+\td->gadget.speed = USB_SPEED_UNKNOWN;\n+\n+\tINIT_LIST_HEAD(&d->gadget.ep0->ep_list);\n+\n+\t/**\n+\t * Initialize the EP0 structure.\n+\t */\n+\tep = &d->ep0;\n+\n+\t/* Init the usb_ep structure. */\n+\tep->name = names[0];\n+\tep->ops = (struct usb_ep_ops *)&dwc_otg_pcd_ep_ops;\n+\n+\t/**\n+\t * @todo NGS: What should the max packet size be set to\n+\t * here?  Before EP type is set?\n+\t */\n+\tep->maxpacket = MAX_PACKET_SIZE;\n+\tdwc_otg_pcd_ep_enable(d->pcd, NULL, ep);\n+\n+\tlist_add_tail(&ep->ep_list, &d->gadget.ep_list);\n+\n+\t/**\n+\t * Initialize the EP structures.\n+\t */\n+\tdev_endpoints = d->pcd->core_if->dev_if->num_in_eps;\n+\n+\tfor (i = 0; i < dev_endpoints; i++) {\n+\t\tep = &d->in_ep[i];\n+\n+\t\t/* Init the usb_ep structure. */\n+\t\tep->name = names[d->pcd->in_ep[i].dwc_ep.num];\n+\t\tep->ops = (struct usb_ep_ops *)&dwc_otg_pcd_ep_ops;\n+\n+\t\t/**\n+\t\t * @todo NGS: What should the max packet size be set to\n+\t\t * here?  Before EP type is set?\n+\t\t */\n+\t\tep->maxpacket = MAX_PACKET_SIZE;\n+\t\tlist_add_tail(&ep->ep_list, &d->gadget.ep_list);\n+\t}\n+\n+\tdev_endpoints = d->pcd->core_if->dev_if->num_out_eps;\n+\n+\tfor (i = 0; i < dev_endpoints; i++) {\n+\t\tep = &d->out_ep[i];\n+\n+\t\t/* Init the usb_ep structure. */\n+\t\tep->name = names[15 + d->pcd->out_ep[i].dwc_ep.num];\n+\t\tep->ops = (struct usb_ep_ops *)&dwc_otg_pcd_ep_ops;\n+\n+\t\t/**\n+\t\t * @todo NGS: What should the max packet size be set to\n+\t\t * here?  Before EP type is set?\n+\t\t */\n+\t\tep->maxpacket = MAX_PACKET_SIZE;\n+\n+\t\tlist_add_tail(&ep->ep_list, &d->gadget.ep_list);\n+\t}\n+\n+\t/* remove ep0 from the list.  There is a ep0 pointer. */\n+\tlist_del_init(&d->ep0.ep_list);\n+\n+\td->ep0.maxpacket = MAX_EP0_SIZE;\n+}\n+\n+/**\n+ * This function releases the Gadget device.\n+ * required by device_unregister().\n+ *\n+ * @todo Should this do something?\tShould it free the PCD?\n+ */\n+static void dwc_otg_pcd_gadget_release(struct device *dev)\n+{\n+\tDWC_DEBUGPL(DBG_PCDV, \"%s(%p)\\n\", __func__, dev);\n+}\n+\n+static struct gadget_wrapper *alloc_wrapper(dwc_bus_dev_t *_dev)\n+{\n+\tstatic char pcd_name[] = \"dwc_otg_pcd\";\n+\tdwc_otg_device_t *otg_dev = DWC_OTG_BUSDRVDATA(_dev);\n+\tstruct gadget_wrapper *d;\n+\tint retval;\n+\n+\td = DWC_ALLOC(sizeof(*d));\n+\tif (d == NULL) {\n+\t\treturn NULL;\n+\t}\n+\n+\tmemset(d, 0, sizeof(*d));\n+\n+\td->gadget.name = pcd_name;\n+\td->pcd = otg_dev->pcd;\n+\n+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30)\n+\tstrcpy(d->gadget.dev.bus_id, \"gadget\");\n+#else\n+\tdev_set_name(&d->gadget.dev, \"%s\", \"gadget\");\n+#endif\n+\n+\td->gadget.dev.parent = &_dev->dev;\n+\td->gadget.dev.release = dwc_otg_pcd_gadget_release;\n+\td->gadget.ops = &dwc_otg_pcd_ops;\n+\td->gadget.max_speed = dwc_otg_pcd_is_dualspeed(otg_dev->pcd) ? USB_SPEED_HIGH:USB_SPEED_FULL;\n+\td->gadget.is_otg = dwc_otg_pcd_is_otg(otg_dev->pcd);\n+\n+\td->driver = 0;\n+\t/* Register the gadget device */\n+\tretval = device_register(&d->gadget.dev);\n+\tif (retval != 0) {\n+\t\tDWC_ERROR(\"device_register failed\\n\");\n+\t\tDWC_FREE(d);\n+\t\treturn NULL;\n+\t}\n+\n+\treturn d;\n+}\n+\n+static void free_wrapper(struct gadget_wrapper *d)\n+{\n+\tif (d->driver) {\n+\t\t/* should have been done already by driver model core */\n+\t\tDWC_WARN(\"driver '%s' is still registered\\n\",\n+\t\t\t d->driver->driver.name);\n+#ifdef CONFIG_USB_GADGET\n+\t\tusb_gadget_unregister_driver(d->driver);\n+#endif\n+\t}\n+\n+\tdevice_unregister(&d->gadget.dev);\n+\tDWC_FREE(d);\n+}\n+\n+/**\n+ * This function initialized the PCD portion of the driver.\n+ *\n+ */\n+int pcd_init(dwc_bus_dev_t *_dev)\n+{\n+\tdwc_otg_device_t *otg_dev = DWC_OTG_BUSDRVDATA(_dev);\n+\tint retval = 0;\n+\n+\tDWC_DEBUGPL(DBG_PCDV, \"%s(%p) otg_dev=%p\\n\", __func__, _dev, otg_dev);\n+\n+\totg_dev->pcd = dwc_otg_pcd_init(otg_dev);\n+\n+\tif (!otg_dev->pcd) {\n+\t\tDWC_ERROR(\"dwc_otg_pcd_init failed\\n\");\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\totg_dev->pcd->otg_dev = otg_dev;\n+\tgadget_wrapper = alloc_wrapper(_dev);\n+\n+\t/*\n+\t * Initialize EP structures\n+\t */\n+\tgadget_add_eps(gadget_wrapper);\n+\t/*\n+\t * Setup interupt handler\n+\t */\n+\tDWC_DEBUGPL(DBG_ANY, \"registering handler for irq%d\\n\",\n+                    otg_dev->os_dep.irq_num);\n+\tretval = request_irq(otg_dev->os_dep.irq_num, dwc_otg_pcd_irq,\n+\t\t\t     IRQF_SHARED, gadget_wrapper->gadget.name,\n+\t\t\t     otg_dev->pcd);\n+\tif (retval != 0) {\n+\t\tDWC_ERROR(\"request of irq%d failed\\n\", otg_dev->os_dep.irq_num);\n+\t\tfree_wrapper(gadget_wrapper);\n+\t\treturn -EBUSY;\n+\t}\n+\n+\tdwc_otg_pcd_start(gadget_wrapper->pcd, &fops);\n+\n+\treturn retval;\n+}\n+\n+/**\n+ * Cleanup the PCD.\n+ */\n+void pcd_remove(dwc_bus_dev_t *_dev)\n+{\n+\tdwc_otg_device_t *otg_dev = DWC_OTG_BUSDRVDATA(_dev);\n+\tdwc_otg_pcd_t *pcd = otg_dev->pcd;\n+\n+\tDWC_DEBUGPL(DBG_PCDV, \"%s(%p) otg_dev %p\\n\", __func__, _dev, otg_dev);\n+\n+\t/*\n+\t * Free the IRQ\n+\t */\n+\tfree_irq(otg_dev->os_dep.irq_num, pcd);\n+\tdwc_otg_pcd_remove(otg_dev->pcd);\n+\tfree_wrapper(gadget_wrapper);\n+\totg_dev->pcd = 0;\n+}\n+\n+#endif /* DWC_HOST_ONLY */\n--- /dev/null\n+++ b/drivers/usb/host/dwc_otg/dwc_otg_regs.h\n@@ -0,0 +1,2550 @@\n+/* ==========================================================================\n+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_regs.h $\n+ * $Revision: #98 $\n+ * $Date: 2012/08/10 $\n+ * $Change: 2047372 $\n+ *\n+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,\n+ * \"Software\") is an Unsupported proprietary work of Synopsys, Inc. unless\n+ * otherwise expressly agreed to in writing between Synopsys and you.\n+ *\n+ * The Software IS NOT an item of Licensed Software or Licensed Product under\n+ * any End User Software License Agreement or Agreement for Licensed Product\n+ * with Synopsys or any supplement thereto. You are permitted to use and\n+ * redistribute this Software in source and binary forms, with or without\n+ * modification, provided that redistributions of source code must retain this\n+ * notice. You may not view, use, disclose, copy or distribute this file or\n+ * any information contained herein except pursuant to this license grant from\n+ * Synopsys. If you do not agree with this notice, including the disclaimer\n+ * below, then you are not authorized to use the Software.\n+ *\n+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN \"AS IS\" BASIS\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,\n+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH\n+ * DAMAGE.\n+ * ========================================================================== */\n+\n+#ifndef __DWC_OTG_REGS_H__\n+#define __DWC_OTG_REGS_H__\n+\n+#include \"dwc_otg_core_if.h\"\n+\n+/**\n+ * @file\n+ *\n+ * This file contains the data structures for accessing the DWC_otg core registers.\n+ *\n+ * The application interfaces with the HS OTG core by reading from and\n+ * writing to the Control and Status Register (CSR) space through the\n+ * AHB Slave interface. These registers are 32 bits wide, and the\n+ * addresses are 32-bit-block aligned.\n+ * CSRs are classified as follows:\n+ * - Core Global Registers\n+ * - Device Mode Registers\n+ * - Device Global Registers\n+ * - Device Endpoint Specific Registers\n+ * - Host Mode Registers\n+ * - Host Global Registers\n+ * - Host Port CSRs\n+ * - Host Channel Specific Registers\n+ *\n+ * Only the Core Global registers can be accessed in both Device and\n+ * Host modes. When the HS OTG core is operating in one mode, either\n+ * Device or Host, the application must not access registers from the\n+ * other mode. When the core switches from one mode to another, the\n+ * registers in the new mode of operation must be reprogrammed as they\n+ * would be after a power-on reset.\n+ */\n+\n+/****************************************************************************/\n+/** DWC_otg Core registers .\n+ * The dwc_otg_core_global_regs structure defines the size\n+ * and relative field offsets for the Core Global registers.\n+ */\n+typedef struct dwc_otg_core_global_regs {\n+\t/** OTG Control and Status Register.  <i>Offset: 000h</i> */\n+\tvolatile uint32_t gotgctl;\n+\t/** OTG Interrupt Register.\t <i>Offset: 004h</i> */\n+\tvolatile uint32_t gotgint;\n+\t/**Core AHB Configuration Register.\t <i>Offset: 008h</i> */\n+\tvolatile uint32_t gahbcfg;\n+\n+#define DWC_GLBINTRMASK\t\t0x0001\n+#define DWC_DMAENABLE\t\t0x0020\n+#define DWC_NPTXEMPTYLVL_EMPTY\t0x0080\n+#define DWC_NPTXEMPTYLVL_HALFEMPTY\t0x0000\n+#define DWC_PTXEMPTYLVL_EMPTY\t0x0100\n+#define DWC_PTXEMPTYLVL_HALFEMPTY\t0x0000\n+\n+\t/**Core USB Configuration Register.\t <i>Offset: 00Ch</i> */\n+\tvolatile uint32_t gusbcfg;\n+\t/**Core Reset Register.\t <i>Offset: 010h</i> */\n+\tvolatile uint32_t grstctl;\n+\t/**Core Interrupt Register.\t <i>Offset: 014h</i> */\n+\tvolatile uint32_t gintsts;\n+\t/**Core Interrupt Mask Register.  <i>Offset: 018h</i> */\n+\tvolatile uint32_t gintmsk;\n+\t/**Receive Status Queue Read Register (Read Only).\t<i>Offset: 01Ch</i> */\n+\tvolatile uint32_t grxstsr;\n+\t/**Receive Status Queue Read & POP Register (Read Only).  <i>Offset: 020h</i>*/\n+\tvolatile uint32_t grxstsp;\n+\t/**Receive FIFO Size Register.\t<i>Offset: 024h</i> */\n+\tvolatile uint32_t grxfsiz;\n+\t/**Non Periodic Transmit FIFO Size Register.  <i>Offset: 028h</i> */\n+\tvolatile uint32_t gnptxfsiz;\n+\t/**Non Periodic Transmit FIFO/Queue Status Register (Read\n+\t * Only). <i>Offset: 02Ch</i> */\n+\tvolatile uint32_t gnptxsts;\n+\t/**I2C Access Register.\t <i>Offset: 030h</i> */\n+\tvolatile uint32_t gi2cctl;\n+\t/**PHY Vendor Control Register.\t <i>Offset: 034h</i> */\n+\tvolatile uint32_t gpvndctl;\n+\t/**General Purpose Input/Output Register.  <i>Offset: 038h</i> */\n+\tvolatile uint32_t ggpio;\n+\t/**User ID Register.  <i>Offset: 03Ch</i> */\n+\tvolatile uint32_t guid;\n+\t/**Synopsys ID Register (Read Only).  <i>Offset: 040h</i> */\n+\tvolatile uint32_t gsnpsid;\n+\t/**User HW Config1 Register (Read Only).  <i>Offset: 044h</i> */\n+\tvolatile uint32_t ghwcfg1;\n+\t/**User HW Config2 Register (Read Only).  <i>Offset: 048h</i> */\n+\tvolatile uint32_t ghwcfg2;\n+#define DWC_SLAVE_ONLY_ARCH 0\n+#define DWC_EXT_DMA_ARCH 1\n+#define DWC_INT_DMA_ARCH 2\n+\n+#define DWC_MODE_HNP_SRP_CAPABLE\t0\n+#define DWC_MODE_SRP_ONLY_CAPABLE\t1\n+#define DWC_MODE_NO_HNP_SRP_CAPABLE\t\t2\n+#define DWC_MODE_SRP_CAPABLE_DEVICE\t\t3\n+#define DWC_MODE_NO_SRP_CAPABLE_DEVICE\t4\n+#define DWC_MODE_SRP_CAPABLE_HOST\t5\n+#define DWC_MODE_NO_SRP_CAPABLE_HOST\t6\n+\n+\t/**User HW Config3 Register (Read Only).  <i>Offset: 04Ch</i> */\n+\tvolatile uint32_t ghwcfg3;\n+\t/**User HW Config4 Register (Read Only).  <i>Offset: 050h</i>*/\n+\tvolatile uint32_t ghwcfg4;\n+\t/** Core LPM Configuration register <i>Offset: 054h</i>*/\n+\tvolatile uint32_t glpmcfg;\n+\t/** Global PowerDn Register <i>Offset: 058h</i> */\n+\tvolatile uint32_t gpwrdn;\n+\t/** Global DFIFO SW Config Register  <i>Offset: 05Ch</i> */\n+\tvolatile uint32_t gdfifocfg;\n+\t/** ADP Control Register  <i>Offset: 060h</i> */\n+\tvolatile uint32_t adpctl;\n+\t/** Reserved  <i>Offset: 064h-0FFh</i> */\n+\tvolatile uint32_t reserved39[39];\n+\t/** Host Periodic Transmit FIFO Size Register. <i>Offset: 100h</i> */\n+\tvolatile uint32_t hptxfsiz;\n+\t/** Device Periodic Transmit FIFO#n Register if dedicated fifos are disabled,\n+\t\totherwise Device Transmit FIFO#n Register.\n+\t * <i>Offset: 104h + (FIFO_Number-1)*04h, 1 <= FIFO Number <= 15 (1<=n<=15).</i> */\n+\tvolatile uint32_t dtxfsiz[15];\n+} dwc_otg_core_global_regs_t;\n+\n+/**\n+ * This union represents the bit fields of the Core OTG Control\n+ * and Status Register (GOTGCTL).  Set the bits using the bit\n+ * fields then write the <i>d32</i> value to the register.\n+ */\n+typedef union gotgctl_data {\n+\t/** raw register data */\n+\tuint32_t d32;\n+\t/** register bits */\n+\tstruct {\n+\t\tunsigned sesreqscs:1;\n+\t\tunsigned sesreq:1;\n+\t\tunsigned vbvalidoven:1;\n+\t\tunsigned vbvalidovval:1;\n+\t\tunsigned avalidoven:1;\n+\t\tunsigned avalidovval:1;\n+\t\tunsigned bvalidoven:1;\n+\t\tunsigned bvalidovval:1;\n+\t\tunsigned hstnegscs:1;\n+\t\tunsigned hnpreq:1;\n+\t\tunsigned hstsethnpen:1;\n+\t\tunsigned devhnpen:1;\n+\t\tunsigned reserved12_15:4;\n+\t\tunsigned conidsts:1;\n+\t\tunsigned dbnctime:1;\n+\t\tunsigned asesvld:1;\n+\t\tunsigned bsesvld:1;\n+\t\tunsigned otgver:1;\n+\t\tunsigned reserved1:1;\n+\t\tunsigned multvalidbc:5;\n+\t\tunsigned chirpen:1;\n+\t\tunsigned reserved28_31:4;\n+\t} b;\n+} gotgctl_data_t;\n+\n+/**\n+ * This union represents the bit fields of the Core OTG Interrupt Register\n+ * (GOTGINT).  Set/clear the bits using the bit fields then write the <i>d32</i>\n+ * value to the register.\n+ */\n+typedef union gotgint_data {\n+\t/** raw register data */\n+\tuint32_t d32;\n+\t/** register bits */\n+\tstruct {\n+\t\t/** Current Mode */\n+\t\tunsigned reserved0_1:2;\n+\n+\t\t/** Session End Detected */\n+\t\tunsigned sesenddet:1;\n+\n+\t\tunsigned reserved3_7:5;\n+\n+\t\t/** Session Request Success Status Change */\n+\t\tunsigned sesreqsucstschng:1;\n+\t\t/** Host Negotiation Success Status Change */\n+\t\tunsigned hstnegsucstschng:1;\n+\n+\t\tunsigned reserved10_16:7;\n+\n+\t\t/** Host Negotiation Detected */\n+\t\tunsigned hstnegdet:1;\n+\t\t/** A-Device Timeout Change */\n+\t\tunsigned adevtoutchng:1;\n+\t\t/** Debounce Done */\n+\t\tunsigned debdone:1;\n+\t\t/** Multi-Valued input changed */\n+\t\tunsigned mvic:1;\n+\n+\t\tunsigned reserved31_21:11;\n+\n+\t} b;\n+} gotgint_data_t;\n+\n+/**\n+ * This union represents the bit fields of the Core AHB Configuration\n+ * Register (GAHBCFG). Set/clear the bits using the bit fields then\n+ * write the <i>d32</i> value to the register.\n+ */\n+typedef union gahbcfg_data {\n+\t/** raw register data */\n+\tuint32_t d32;\n+\t/** register bits */\n+\tstruct {\n+\t\tunsigned glblintrmsk:1;\n+#define DWC_GAHBCFG_GLBINT_ENABLE\t\t1\n+\n+\t\tunsigned hburstlen:4;\n+#define DWC_GAHBCFG_INT_DMA_BURST_SINGLE\t0\n+#define DWC_GAHBCFG_INT_DMA_BURST_INCR\t\t1\n+#define DWC_GAHBCFG_INT_DMA_BURST_INCR4\t\t3\n+#define DWC_GAHBCFG_INT_DMA_BURST_INCR8\t\t5\n+#define DWC_GAHBCFG_INT_DMA_BURST_INCR16\t7\n+\n+\t\tunsigned dmaenable:1;\n+#define DWC_GAHBCFG_DMAENABLE\t\t\t1\n+\t\tunsigned reserved:1;\n+\t\tunsigned nptxfemplvl_txfemplvl:1;\n+\t\tunsigned ptxfemplvl:1;\n+#define DWC_GAHBCFG_TXFEMPTYLVL_EMPTY\t\t1\n+#define DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY\t0\n+\t\tunsigned reserved9_20:12;\n+\t\tunsigned remmemsupp:1;\n+\t\tunsigned notialldmawrit:1;\n+\t\tunsigned ahbsingle:1;\n+\t\tunsigned reserved24_31:8;\n+\t} b;\n+} gahbcfg_data_t;\n+\n+/**\n+ * This union represents the bit fields of the Core USB Configuration\n+ * Register (GUSBCFG). Set the bits using the bit fields then write\n+ * the <i>d32</i> value to the register.\n+ */\n+typedef union gusbcfg_data {\n+\t/** raw register data */\n+\tuint32_t d32;\n+\t/** register bits */\n+\tstruct {\n+\t\tunsigned toutcal:3;\n+\t\tunsigned phyif:1;\n+\t\tunsigned ulpi_utmi_sel:1;\n+\t\tunsigned fsintf:1;\n+\t\tunsigned physel:1;\n+\t\tunsigned ddrsel:1;\n+\t\tunsigned srpcap:1;\n+\t\tunsigned hnpcap:1;\n+\t\tunsigned usbtrdtim:4;\n+\t\tunsigned reserved1:1;\n+\t\tunsigned phylpwrclksel:1;\n+\t\tunsigned otgutmifssel:1;\n+\t\tunsigned ulpi_fsls:1;\n+\t\tunsigned ulpi_auto_res:1;\n+\t\tunsigned ulpi_clk_sus_m:1;\n+\t\tunsigned ulpi_ext_vbus_drv:1;\n+\t\tunsigned ulpi_int_vbus_indicator:1;\n+\t\tunsigned term_sel_dl_pulse:1;\n+\t\tunsigned indicator_complement:1;\n+\t\tunsigned indicator_pass_through:1;\n+\t\tunsigned ulpi_int_prot_dis:1;\n+\t\tunsigned ic_usb_cap:1;\n+\t\tunsigned ic_traffic_pull_remove:1;\n+\t\tunsigned tx_end_delay:1;\n+\t\tunsigned force_host_mode:1;\n+\t\tunsigned force_dev_mode:1;\n+\t\tunsigned reserved31:1;\n+\t} b;\n+} gusbcfg_data_t;\n+\n+/**\n+ * This union represents the bit fields of the Core Reset Register\n+ * (GRSTCTL).  Set/clear the bits using the bit fields then write the\n+ * <i>d32</i> value to the register.\n+ */\n+typedef union grstctl_data {\n+\t/** raw register data */\n+\tuint32_t d32;\n+\t/** register bits */\n+\tstruct {\n+\t\t/** Core Soft Reset (CSftRst) (Device and Host)\n+\t\t *\n+\t\t * The application can flush the control logic in the\n+\t\t * entire core using this bit. This bit resets the\n+\t\t * pipelines in the AHB Clock domain as well as the\n+\t\t * PHY Clock domain.\n+\t\t *\n+\t\t * The state machines are reset to an IDLE state, the\n+\t\t * control bits in the CSRs are cleared, all the\n+\t\t * transmit FIFOs and the receive FIFO are flushed.\n+\t\t *\n+\t\t * The status mask bits that control the generation of\n+\t\t * the interrupt, are cleared, to clear the\n+\t\t * interrupt. The interrupt status bits are not\n+\t\t * cleared, so the application can get the status of\n+\t\t * any events that occurred in the core after it has\n+\t\t * set this bit.\n+\t\t *\n+\t\t * Any transactions on the AHB are terminated as soon\n+\t\t * as possible following the protocol. Any\n+\t\t * transactions on the USB are terminated immediately.\n+\t\t *\n+\t\t * The configuration settings in the CSRs are\n+\t\t * unchanged, so the software doesn't have to\n+\t\t * reprogram these registers (Device\n+\t\t * Configuration/Host Configuration/Core System\n+\t\t * Configuration/Core PHY Configuration).\n+\t\t *\n+\t\t * The application can write to this bit, any time it\n+\t\t * wants to reset the core. This is a self clearing\n+\t\t * bit and the core clears this bit after all the\n+\t\t * necessary logic is reset in the core, which may\n+\t\t * take several clocks, depending on the current state\n+\t\t * of the core.\n+\t\t */\n+\t\tunsigned csftrst:1;\n+\t\t/** Hclk Soft Reset\n+\t\t *\n+\t\t * The application uses this bit to reset the control logic in\n+\t\t * the AHB clock domain. Only AHB clock domain pipelines are\n+\t\t * reset.\n+\t\t */\n+\t\tunsigned hsftrst:1;\n+\t\t/** Host Frame Counter Reset (Host Only)<br>\n+\t\t *\n+\t\t * The application can reset the (micro)frame number\n+\t\t * counter inside the core, using this bit. When the\n+\t\t * (micro)frame counter is reset, the subsequent SOF\n+\t\t * sent out by the core, will have a (micro)frame\n+\t\t * number of 0.\n+\t\t */\n+\t\tunsigned hstfrm:1;\n+\t\t/** In Token Sequence Learning Queue Flush\n+\t\t * (INTknQFlsh) (Device Only)\n+\t\t */\n+\t\tunsigned intknqflsh:1;\n+\t\t/** RxFIFO Flush (RxFFlsh) (Device and Host)\n+\t\t *\n+\t\t * The application can flush the entire Receive FIFO\n+\t\t * using this bit. The application must first\n+\t\t * ensure that the core is not in the middle of a\n+\t\t * transaction. The application should write into\n+\t\t * this bit, only after making sure that neither the\n+\t\t * DMA engine is reading from the RxFIFO nor the MAC\n+\t\t * is writing the data in to the FIFO. The\n+\t\t * application should wait until the bit is cleared\n+\t\t * before performing any other operations. This bit\n+\t\t * will takes 8 clocks (slowest of PHY or AHB clock)\n+\t\t * to clear.\n+\t\t */\n+\t\tunsigned rxfflsh:1;\n+\t\t/** TxFIFO Flush (TxFFlsh) (Device and Host).\n+\t\t *\n+\t\t * This bit is used to selectively flush a single or\n+\t\t * all transmit FIFOs. The application must first\n+\t\t * ensure that the core is not in the middle of a\n+\t\t * transaction. The application should write into\n+\t\t * this bit, only after making sure that neither the\n+\t\t * DMA engine is writing into the TxFIFO nor the MAC\n+\t\t * is reading the data out of the FIFO. The\n+\t\t * application should wait until the core clears this\n+\t\t * bit, before performing any operations. This bit\n+\t\t * will takes 8 clocks (slowest of PHY or AHB clock)\n+\t\t * to clear.\n+\t\t */\n+\t\tunsigned txfflsh:1;\n+\n+\t\t/** TxFIFO Number (TxFNum) (Device and Host).\n+\t\t *\n+\t\t * This is the FIFO number which needs to be flushed,\n+\t\t * using the TxFIFO Flush bit. This field should not\n+\t\t * be changed until the TxFIFO Flush bit is cleared by\n+\t\t * the core.\n+\t\t *\t - 0x0 : Non Periodic TxFIFO Flush\n+\t\t *\t - 0x1 : Periodic TxFIFO #1 Flush in device mode\n+\t\t *\t   or Periodic TxFIFO in host mode\n+\t\t *\t - 0x2 : Periodic TxFIFO #2 Flush in device mode.\n+\t\t *\t - ...\n+\t\t *\t - 0xF : Periodic TxFIFO #15 Flush in device mode\n+\t\t *\t - 0x10: Flush all the Transmit NonPeriodic and\n+\t\t *\t   Transmit Periodic FIFOs in the core\n+\t\t */\n+\t\tunsigned txfnum:5;\n+\t\t/** Reserved */\n+\t\tunsigned reserved11_29:19;\n+\t\t/** DMA Request Signal.\t Indicated DMA request is in\n+\t\t * probress. Used for debug purpose. */\n+\t\tunsigned dmareq:1;\n+\t\t/** AHB Master Idle.  Indicates the AHB Master State\n+\t\t * Machine is in IDLE condition. */\n+\t\tunsigned ahbidle:1;\n+\t} b;\n+} grstctl_t;\n+\n+/**\n+ * This union represents the bit fields of the Core Interrupt Mask\n+ * Register (GINTMSK). Set/clear the bits using the bit fields then\n+ * write the <i>d32</i> value to the register.\n+ */\n+typedef union gintmsk_data {\n+\t/** raw register data */\n+\tuint32_t d32;\n+\t/** register bits */\n+\tstruct {\n+\t\tunsigned reserved0:1;\n+\t\tunsigned modemismatch:1;\n+\t\tunsigned otgintr:1;\n+\t\tunsigned sofintr:1;\n+\t\tunsigned rxstsqlvl:1;\n+\t\tunsigned nptxfempty:1;\n+\t\tunsigned ginnakeff:1;\n+\t\tunsigned goutnakeff:1;\n+\t\tunsigned ulpickint:1;\n+\t\tunsigned i2cintr:1;\n+\t\tunsigned erlysuspend:1;\n+\t\tunsigned usbsuspend:1;\n+\t\tunsigned usbreset:1;\n+\t\tunsigned enumdone:1;\n+\t\tunsigned isooutdrop:1;\n+\t\tunsigned eopframe:1;\n+\t\tunsigned restoredone:1;\n+\t\tunsigned epmismatch:1;\n+\t\tunsigned inepintr:1;\n+\t\tunsigned outepintr:1;\n+\t\tunsigned incomplisoin:1;\n+\t\tunsigned incomplisoout:1;\n+\t\tunsigned fetsusp:1;\n+\t\tunsigned resetdet:1;\n+\t\tunsigned portintr:1;\n+\t\tunsigned hcintr:1;\n+\t\tunsigned ptxfempty:1;\n+\t\tunsigned lpmtranrcvd:1;\n+\t\tunsigned conidstschng:1;\n+\t\tunsigned disconnect:1;\n+\t\tunsigned sessreqintr:1;\n+\t\tunsigned wkupintr:1;\n+\t} b;\n+} gintmsk_data_t;\n+/**\n+ * This union represents the bit fields of the Core Interrupt Register\n+ * (GINTSTS).  Set/clear the bits using the bit fields then write the\n+ * <i>d32</i> value to the register.\n+ */\n+typedef union gintsts_data {\n+\t/** raw register data */\n+\tuint32_t d32;\n+#define DWC_SOF_INTR_MASK 0x0008\n+\t/** register bits */\n+\tstruct {\n+#define DWC_HOST_MODE 1\n+\t\tunsigned curmode:1;\n+\t\tunsigned modemismatch:1;\n+\t\tunsigned otgintr:1;\n+\t\tunsigned sofintr:1;\n+\t\tunsigned rxstsqlvl:1;\n+\t\tunsigned nptxfempty:1;\n+\t\tunsigned ginnakeff:1;\n+\t\tunsigned goutnakeff:1;\n+\t\tunsigned ulpickint:1;\n+\t\tunsigned i2cintr:1;\n+\t\tunsigned erlysuspend:1;\n+\t\tunsigned usbsuspend:1;\n+\t\tunsigned usbreset:1;\n+\t\tunsigned enumdone:1;\n+\t\tunsigned isooutdrop:1;\n+\t\tunsigned eopframe:1;\n+\t\tunsigned restoredone:1;\n+\t\tunsigned epmismatch:1;\n+\t\tunsigned inepint:1;\n+\t\tunsigned outepintr:1;\n+\t\tunsigned incomplisoin:1;\n+\t\tunsigned incomplisoout:1;\n+\t\tunsigned fetsusp:1;\n+\t\tunsigned resetdet:1;\n+\t\tunsigned portintr:1;\n+\t\tunsigned hcintr:1;\n+\t\tunsigned ptxfempty:1;\n+\t\tunsigned lpmtranrcvd:1;\n+\t\tunsigned conidstschng:1;\n+\t\tunsigned disconnect:1;\n+\t\tunsigned sessreqintr:1;\n+\t\tunsigned wkupintr:1;\n+\t} b;\n+} gintsts_data_t;\n+\n+/**\n+ * This union represents the bit fields in the Device Receive Status Read and\n+ * Pop Registers (GRXSTSR, GRXSTSP) Read the register into the <i>d32</i>\n+ * element then read out the bits using the <i>b</i>it elements.\n+ */\n+typedef union device_grxsts_data {\n+\t/** raw register data */\n+\tuint32_t d32;\n+\t/** register bits */\n+\tstruct {\n+\t\tunsigned epnum:4;\n+\t\tunsigned bcnt:11;\n+\t\tunsigned dpid:2;\n+\n+#define DWC_STS_DATA_UPDT\t\t0x2\t// OUT Data Packet\n+#define DWC_STS_XFER_COMP\t\t0x3\t// OUT Data Transfer Complete\n+\n+#define DWC_DSTS_GOUT_NAK\t\t0x1\t// Global OUT NAK\n+#define DWC_DSTS_SETUP_COMP\t\t0x4\t// Setup Phase Complete\n+#define DWC_DSTS_SETUP_UPDT 0x6\t// SETUP Packet\n+\t\tunsigned pktsts:4;\n+\t\tunsigned fn:4;\n+\t\tunsigned reserved25_31:7;\n+\t} b;\n+} device_grxsts_data_t;\n+\n+/**\n+ * This union represents the bit fields in the Host Receive Status Read and\n+ * Pop Registers (GRXSTSR, GRXSTSP) Read the register into the <i>d32</i>\n+ * element then read out the bits using the <i>b</i>it elements.\n+ */\n+typedef union host_grxsts_data {\n+\t/** raw register data */\n+\tuint32_t d32;\n+\t/** register bits */\n+\tstruct {\n+\t\tunsigned chnum:4;\n+\t\tunsigned bcnt:11;\n+\t\tunsigned dpid:2;\n+\n+\t\tunsigned pktsts:4;\n+#define DWC_GRXSTS_PKTSTS_IN\t\t\t  0x2\n+#define DWC_GRXSTS_PKTSTS_IN_XFER_COMP\t  0x3\n+#define DWC_GRXSTS_PKTSTS_DATA_TOGGLE_ERR 0x5\n+#define DWC_GRXSTS_PKTSTS_CH_HALTED\t\t  0x7\n+\n+\t\tunsigned reserved21_31:11;\n+\t} b;\n+} host_grxsts_data_t;\n+\n+/**\n+ * This union represents the bit fields in the FIFO Size Registers (HPTXFSIZ,\n+ * GNPTXFSIZ, DPTXFSIZn, DIEPTXFn). Read the register into the <i>d32</i> element\n+ * then read out the bits using the <i>b</i>it elements.\n+ */\n+typedef union fifosize_data {\n+\t/** raw register data */\n+\tuint32_t d32;\n+\t/** register bits */\n+\tstruct {\n+\t\tunsigned startaddr:16;\n+\t\tunsigned depth:16;\n+\t} b;\n+} fifosize_data_t;\n+\n+/**\n+ * This union represents the bit fields in the Non-Periodic Transmit\n+ * FIFO/Queue Status Register (GNPTXSTS). Read the register into the\n+ * <i>d32</i> element then read out the bits using the <i>b</i>it\n+ * elements.\n+ */\n+typedef union gnptxsts_data {\n+\t/** raw register data */\n+\tuint32_t d32;\n+\t/** register bits */\n+\tstruct {\n+\t\tunsigned nptxfspcavail:16;\n+\t\tunsigned nptxqspcavail:8;\n+\t\t/** Top of the Non-Periodic Transmit Request Queue\n+\t\t *\t- bit 24 - Terminate (Last entry for the selected\n+\t\t *\t  channel/EP)\n+\t\t *\t- bits 26:25 - Token Type\n+\t\t *\t  - 2'b00 - IN/OUT\n+\t\t *\t  - 2'b01 - Zero Length OUT\n+\t\t *\t  - 2'b10 - PING/Complete Split\n+\t\t *\t  - 2'b11 - Channel Halt\n+\t\t *\t- bits 30:27 - Channel/EP Number\n+\t\t */\n+\t\tunsigned nptxqtop_terminate:1;\n+\t\tunsigned nptxqtop_token:2;\n+\t\tunsigned nptxqtop_chnep:4;\n+\t\tunsigned reserved:1;\n+\t} b;\n+} gnptxsts_data_t;\n+\n+/**\n+ * This union represents the bit fields in the Transmit\n+ * FIFO Status Register (DTXFSTS). Read the register into the\n+ * <i>d32</i> element then read out the bits using the <i>b</i>it\n+ * elements.\n+ */\n+typedef union dtxfsts_data {\n+\t/** raw register data */\n+\tuint32_t d32;\n+\t/** register bits */\n+\tstruct {\n+\t\tunsigned txfspcavail:16;\n+\t\tunsigned reserved:16;\n+\t} b;\n+} dtxfsts_data_t;\n+\n+/**\n+ * This union represents the bit fields in the I2C Control Register\n+ * (I2CCTL). Read the register into the <i>d32</i> element then read out the\n+ * bits using the <i>b</i>it elements.\n+ */\n+typedef union gi2cctl_data {\n+\t/** raw register data */\n+\tuint32_t d32;\n+\t/** register bits */\n+\tstruct {\n+\t\tunsigned rwdata:8;\n+\t\tunsigned regaddr:8;\n+\t\tunsigned addr:7;\n+\t\tunsigned i2cen:1;\n+\t\tunsigned ack:1;\n+\t\tunsigned i2csuspctl:1;\n+\t\tunsigned i2cdevaddr:2;\n+\t\tunsigned i2cdatse0:1;\n+\t\tunsigned reserved:1;\n+\t\tunsigned rw:1;\n+\t\tunsigned bsydne:1;\n+\t} b;\n+} gi2cctl_data_t;\n+\n+/**\n+ * This union represents the bit fields in the PHY Vendor Control Register\n+ * (GPVNDCTL). Read the register into the <i>d32</i> element then read out the\n+ * bits using the <i>b</i>it elements.\n+ */\n+typedef union gpvndctl_data {\n+\t/** raw register data */\n+\tuint32_t d32;\n+\t/** register bits */\n+\tstruct {\n+\t\tunsigned regdata:8;\n+\t\tunsigned vctrl:8;\n+\t\tunsigned regaddr16_21:6;\n+\t\tunsigned regwr:1;\n+\t\tunsigned reserved23_24:2;\n+\t\tunsigned newregreq:1;\n+\t\tunsigned vstsbsy:1;\n+\t\tunsigned vstsdone:1;\n+\t\tunsigned reserved28_30:3;\n+\t\tunsigned disulpidrvr:1;\n+\t} b;\n+} gpvndctl_data_t;\n+\n+/**\n+ * This union represents the bit fields in the General Purpose\n+ * Input/Output Register (GGPIO).\n+ * Read the register into the <i>d32</i> element then read out the\n+ * bits using the <i>b</i>it elements.\n+ */\n+typedef union ggpio_data {\n+\t/** raw register data */\n+\tuint32_t d32;\n+\t/** register bits */\n+\tstruct {\n+\t\tunsigned gpi:16;\n+\t\tunsigned gpo:16;\n+\t} b;\n+} ggpio_data_t;\n+\n+/**\n+ * This union represents the bit fields in the User ID Register\n+ * (GUID). Read the register into the <i>d32</i> element then read out the\n+ * bits using the <i>b</i>it elements.\n+ */\n+typedef union guid_data {\n+\t/** raw register data */\n+\tuint32_t d32;\n+\t/** register bits */\n+\tstruct {\n+\t\tunsigned rwdata:32;\n+\t} b;\n+} guid_data_t;\n+\n+/**\n+ * This union represents the bit fields in the Synopsys ID Register\n+ * (GSNPSID). Read the register into the <i>d32</i> element then read out the\n+ * bits using the <i>b</i>it elements.\n+ */\n+typedef union gsnpsid_data {\n+\t/** raw register data */\n+\tuint32_t d32;\n+\t/** register bits */\n+\tstruct {\n+\t\tunsigned rwdata:32;\n+\t} b;\n+} gsnpsid_data_t;\n+\n+/**\n+ * This union represents the bit fields in the User HW Config1\n+ * Register.  Read the register into the <i>d32</i> element then read\n+ * out the bits using the <i>b</i>it elements.\n+ */\n+typedef union hwcfg1_data {\n+\t/** raw register data */\n+\tuint32_t d32;\n+\t/** register bits */\n+\tstruct {\n+\t\tunsigned ep_dir0:2;\n+\t\tunsigned ep_dir1:2;\n+\t\tunsigned ep_dir2:2;\n+\t\tunsigned ep_dir3:2;\n+\t\tunsigned ep_dir4:2;\n+\t\tunsigned ep_dir5:2;\n+\t\tunsigned ep_dir6:2;\n+\t\tunsigned ep_dir7:2;\n+\t\tunsigned ep_dir8:2;\n+\t\tunsigned ep_dir9:2;\n+\t\tunsigned ep_dir10:2;\n+\t\tunsigned ep_dir11:2;\n+\t\tunsigned ep_dir12:2;\n+\t\tunsigned ep_dir13:2;\n+\t\tunsigned ep_dir14:2;\n+\t\tunsigned ep_dir15:2;\n+\t} b;\n+} hwcfg1_data_t;\n+\n+/**\n+ * This union represents the bit fields in the User HW Config2\n+ * Register.  Read the register into the <i>d32</i> element then read\n+ * out the bits using the <i>b</i>it elements.\n+ */\n+typedef union hwcfg2_data {\n+\t/** raw register data */\n+\tuint32_t d32;\n+\t/** register bits */\n+\tstruct {\n+\t\t/* GHWCFG2 */\n+\t\tunsigned op_mode:3;\n+#define DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG 0\n+#define DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG 1\n+#define DWC_HWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE_OTG 2\n+#define DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE 3\n+#define DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE 4\n+#define DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST 5\n+#define DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST 6\n+\n+\t\tunsigned architecture:2;\n+\t\tunsigned point2point:1;\n+\t\tunsigned hs_phy_type:2;\n+#define DWC_HWCFG2_HS_PHY_TYPE_NOT_SUPPORTED 0\n+#define DWC_HWCFG2_HS_PHY_TYPE_UTMI 1\n+#define DWC_HWCFG2_HS_PHY_TYPE_ULPI 2\n+#define DWC_HWCFG2_HS_PHY_TYPE_UTMI_ULPI 3\n+\n+\t\tunsigned fs_phy_type:2;\n+\t\tunsigned num_dev_ep:4;\n+\t\tunsigned num_host_chan:4;\n+\t\tunsigned perio_ep_supported:1;\n+\t\tunsigned dynamic_fifo:1;\n+\t\tunsigned multi_proc_int:1;\n+\t\tunsigned reserved21:1;\n+\t\tunsigned nonperio_tx_q_depth:2;\n+\t\tunsigned host_perio_tx_q_depth:2;\n+\t\tunsigned dev_token_q_depth:5;\n+\t\tunsigned otg_enable_ic_usb:1;\n+\t} b;\n+} hwcfg2_data_t;\n+\n+/**\n+ * This union represents the bit fields in the User HW Config3\n+ * Register.  Read the register into the <i>d32</i> element then read\n+ * out the bits using the <i>b</i>it elements.\n+ */\n+typedef union hwcfg3_data {\n+\t/** raw register data */\n+\tuint32_t d32;\n+\t/** register bits */\n+\tstruct {\n+\t\t/* GHWCFG3 */\n+\t\tunsigned xfer_size_cntr_width:4;\n+\t\tunsigned packet_size_cntr_width:3;\n+\t\tunsigned otg_func:1;\n+\t\tunsigned i2c:1;\n+\t\tunsigned vendor_ctrl_if:1;\n+\t\tunsigned optional_features:1;\n+\t\tunsigned synch_reset_type:1;\n+\t\tunsigned adp_supp:1;\n+\t\tunsigned otg_enable_hsic:1;\n+\t\tunsigned bc_support:1;\n+\t\tunsigned otg_lpm_en:1;\n+\t\tunsigned dfifo_depth:16;\n+\t} b;\n+} hwcfg3_data_t;\n+\n+/**\n+ * This union represents the bit fields in the User HW Config4\n+ * Register.  Read the register into the <i>d32</i> element then read\n+ * out the bits using the <i>b</i>it elements.\n+ */\n+typedef union hwcfg4_data {\n+\t/** raw register data */\n+\tuint32_t d32;\n+\t/** register bits */\n+\tstruct {\n+\t\tunsigned num_dev_perio_in_ep:4;\n+\t\tunsigned power_optimiz:1;\n+\t\tunsigned min_ahb_freq:1;\n+\t\tunsigned hiber:1;\n+\t\tunsigned xhiber:1;\n+\t\tunsigned reserved:6;\n+\t\tunsigned utmi_phy_data_width:2;\n+\t\tunsigned num_dev_mode_ctrl_ep:4;\n+\t\tunsigned iddig_filt_en:1;\n+\t\tunsigned vbus_valid_filt_en:1;\n+\t\tunsigned a_valid_filt_en:1;\n+\t\tunsigned b_valid_filt_en:1;\n+\t\tunsigned session_end_filt_en:1;\n+\t\tunsigned ded_fifo_en:1;\n+\t\tunsigned num_in_eps:4;\n+\t\tunsigned desc_dma:1;\n+\t\tunsigned desc_dma_dyn:1;\n+\t} b;\n+} hwcfg4_data_t;\n+\n+/**\n+ * This union represents the bit fields of the Core LPM Configuration\n+ * Register (GLPMCFG). Set the bits using bit fields then write\n+ * the <i>d32</i> value to the register.\n+ */\n+typedef union glpmctl_data {\n+\t/** raw register data */\n+\tuint32_t d32;\n+\t/** register bits */\n+\tstruct {\n+\t\t/** LPM-Capable (LPMCap) (Device and Host)\n+\t\t * The application uses this bit to control\n+\t\t * the DWC_otg core LPM capabilities.\n+\t\t */\n+\t\tunsigned lpm_cap_en:1;\n+\t\t/** LPM response programmed by application (AppL1Res) (Device)\n+\t\t * Handshake response to LPM token pre-programmed\n+\t\t * by device application software.\n+\t\t */\n+\t\tunsigned appl_resp:1;\n+\t\t/** Host Initiated Resume Duration (HIRD) (Device and Host)\n+\t\t * In Host mode this field indicates the value of HIRD\n+\t\t * to be sent in an LPM transaction.\n+\t\t * In Device mode this field is updated with the\n+\t\t * Received LPM Token HIRD bmAttribute\n+\t\t * when an ACK/NYET/STALL response is sent\n+\t\t * to an LPM transaction.\n+\t\t */\n+\t\tunsigned hird:4;\n+\t\t/** RemoteWakeEnable (bRemoteWake) (Device and Host)\n+\t\t * In Host mode this bit indicates the value of remote\n+\t\t * wake up to be sent in wIndex field of LPM transaction.\n+\t\t * In Device mode this field is updated with the\n+\t\t * Received LPM Token bRemoteWake bmAttribute\n+\t\t * when an ACK/NYET/STALL response is sent\n+\t\t * to an LPM transaction.\n+\t\t */\n+\t\tunsigned rem_wkup_en:1;\n+\t\t/** Enable utmi_sleep_n (EnblSlpM) (Device and Host)\n+\t\t * The application uses this bit to control\n+\t\t * the utmi_sleep_n assertion to the PHY when in L1 state.\n+\t\t */\n+\t\tunsigned en_utmi_sleep:1;\n+\t\t/** HIRD Threshold (HIRD_Thres) (Device and Host)\n+\t\t */\n+\t\tunsigned hird_thres:5;\n+\t\t/** LPM Response (CoreL1Res) (Device and Host)\n+\t\t * In Host mode this bit contains handsake response to\n+\t\t * LPM transaction.\n+\t\t * In Device mode the response of the core to\n+\t\t * LPM transaction received is reflected in these two bits.\n+\t\t\t- 0x0 : ERROR (No handshake response)\n+\t\t\t- 0x1 : STALL\n+\t\t\t- 0x2 : NYET\n+\t\t\t- 0x3 : ACK\n+\t\t */\n+\t\tunsigned lpm_resp:2;\n+\t\t/** Port Sleep Status (SlpSts) (Device and Host)\n+\t\t * This bit is set as long as a Sleep condition\n+\t\t * is present on the USB bus.\n+\t\t */\n+\t\tunsigned prt_sleep_sts:1;\n+\t\t/** Sleep State Resume OK (L1ResumeOK) (Device and Host)\n+\t\t * Indicates that the application or host\n+\t\t * can start resume from Sleep state.\n+\t\t */\n+\t\tunsigned sleep_state_resumeok:1;\n+\t\t/** LPM channel Index (LPM_Chnl_Indx) (Host)\n+\t\t * The channel number on which the LPM transaction\n+\t\t * has to be applied while sending\n+\t\t * an LPM transaction to the local device.\n+\t\t */\n+\t\tunsigned lpm_chan_index:4;\n+\t\t/** LPM Retry Count (LPM_Retry_Cnt) (Host)\n+\t\t * Number host retries that would be performed\n+\t\t * if the device response was not valid response.\n+\t\t */\n+\t\tunsigned retry_count:3;\n+\t\t/** Send LPM Transaction (SndLPM) (Host)\n+\t\t * When set by application software,\n+\t\t * an LPM transaction containing two tokens\n+\t\t * is sent.\n+\t\t */\n+\t\tunsigned send_lpm:1;\n+\t\t/** LPM Retry status (LPM_RetryCnt_Sts) (Host)\n+\t\t * Number of LPM Host Retries still remaining\n+\t\t * to be transmitted for the current LPM sequence\n+\t\t */\n+\t\tunsigned retry_count_sts:3;\n+\t\tunsigned reserved28_29:2;\n+\t\t/** In host mode once this bit is set, the host\n+\t\t * configures to drive the HSIC Idle state on the bus.\n+\t\t * It then waits for the  device to initiate the Connect sequence.\n+\t\t * In device mode once this bit is set, the device waits for\n+\t\t * the HSIC Idle line state on the bus. Upon receving the Idle\n+\t\t * line state, it initiates the HSIC Connect sequence.\n+\t\t */\n+\t\tunsigned hsic_connect:1;\n+\t\t/** This bit overrides and functionally inverts\n+\t\t * the if_select_hsic input port signal.\n+\t\t */\n+\t\tunsigned inv_sel_hsic:1;\n+\t} b;\n+} glpmcfg_data_t;\n+\n+/**\n+ * This union represents the bit fields of the Core ADP Timer, Control and\n+ * Status Register (ADPTIMCTLSTS). Set the bits using bit fields then write\n+ * the <i>d32</i> value to the register.\n+ */\n+typedef union adpctl_data {\n+\t/** raw register data */\n+\tuint32_t d32;\n+\t/** register bits */\n+\tstruct {\n+\t\t/** Probe Discharge (PRB_DSCHG)\n+\t\t *  These bits set the times for TADP_DSCHG.\n+\t\t *  These bits are defined as follows:\n+\t\t *  2'b00 - 4 msec\n+\t\t *  2'b01 - 8 msec\n+\t\t *  2'b10 - 16 msec\n+\t\t *  2'b11 - 32 msec\n+\t\t */\n+\t\tunsigned prb_dschg:2;\n+\t\t/** Probe Delta (PRB_DELTA)\n+\t\t *  These bits set the resolution for RTIM   value.\n+\t\t *  The bits are defined in units of 32 kHz clock cycles as follows:\n+\t\t *  2'b00  -  1 cycles\n+\t\t *  2'b01  -  2 cycles\n+\t\t *  2'b10 -  3 cycles\n+\t\t *  2'b11 - 4 cycles\n+\t\t *  For example if this value is chosen to 2'b01, it means that RTIM\n+\t\t *  increments for every 3(three) 32Khz clock cycles.\n+\t\t */\n+\t\tunsigned prb_delta:2;\n+\t\t/** Probe Period (PRB_PER)\n+\t\t *  These bits sets the TADP_PRD as shown in Figure 4 as follows:\n+\t\t *  2'b00  -  0.625 to 0.925 sec (typical 0.775 sec)\n+\t\t *  2'b01  -  1.25 to 1.85 sec (typical 1.55 sec)\n+\t\t *  2'b10  -  1.9 to 2.6 sec (typical 2.275 sec)\n+\t\t *  2'b11  -  Reserved\n+\t\t */\n+\t\tunsigned prb_per:2;\n+\t\t/** These bits capture the latest time it took for VBUS to ramp from\n+\t\t *  VADP_SINK to VADP_PRB.\n+\t\t *  0x000  -  1 cycles\n+\t\t *  0x001  -  2 cycles\n+\t\t *  0x002  -  3 cycles\n+\t\t *  etc\n+\t\t *  0x7FF  -  2048 cycles\n+\t\t *  A time of 1024 cycles at 32 kHz corresponds to a time of 32 msec.\n+\t\t*/\n+\t\tunsigned rtim:11;\n+\t\t/** Enable Probe (EnaPrb)\n+\t\t *  When programmed to 1'b1, the core performs a probe operation.\n+\t\t *  This bit is valid only if OTG_Ver = 1'b1.\n+\t\t */\n+\t\tunsigned enaprb:1;\n+\t\t/** Enable Sense (EnaSns)\n+\t\t *  When programmed to 1'b1, the core performs a Sense operation.\n+\t\t *  This bit is valid only if OTG_Ver = 1'b1.\n+\t\t */\n+\t\tunsigned enasns:1;\n+\t\t/** ADP Reset (ADPRes)\n+\t\t *  When set, ADP controller is reset.\n+\t\t *  This bit is valid only if OTG_Ver = 1'b1.\n+\t\t */\n+\t\tunsigned adpres:1;\n+\t\t/** ADP Enable (ADPEn)\n+\t\t *  When set, the core performs either ADP probing or sensing\n+\t\t *  based on EnaPrb or EnaSns.\n+\t\t *  This bit is valid only if OTG_Ver = 1'b1.\n+\t\t */\n+\t\tunsigned adpen:1;\n+\t\t/** ADP Probe Interrupt (ADP_PRB_INT)\n+\t\t *  When this bit is set, it means that the VBUS\n+\t\t *  voltage is greater than VADP_PRB or VADP_PRB is reached.\n+\t\t *  This bit is valid only if OTG_Ver = 1'b1.\n+\t\t */\n+\t\tunsigned adp_prb_int:1;\n+\t\t/**\n+\t\t *  ADP Sense Interrupt (ADP_SNS_INT)\n+\t\t *  When this bit is set, it means that the VBUS voltage is greater than\n+\t\t *  VADP_SNS value or VADP_SNS is reached.\n+\t\t *  This bit is valid only if OTG_Ver = 1'b1.\n+\t\t */\n+\t\tunsigned adp_sns_int:1;\n+\t\t/** ADP Tomeout Interrupt (ADP_TMOUT_INT)\n+\t\t *  This bit is relevant only for an ADP probe.\n+\t\t *  When this bit is set, it means that the ramp time has\n+\t\t *  completed ie ADPCTL.RTIM has reached its terminal value\n+\t\t *  of 0x7FF.  This is a debug feature that allows software\n+\t\t *  to read the ramp time after each cycle.\n+\t\t *  This bit is valid only if OTG_Ver = 1'b1.\n+\t\t */\n+\t\tunsigned adp_tmout_int:1;\n+\t\t/** ADP Probe Interrupt Mask (ADP_PRB_INT_MSK)\n+\t\t *  When this bit is set, it unmasks the interrupt due to ADP_PRB_INT.\n+\t\t *  This bit is valid only if OTG_Ver = 1'b1.\n+\t\t */\n+\t\tunsigned adp_prb_int_msk:1;\n+\t\t/** ADP Sense Interrupt Mask (ADP_SNS_INT_MSK)\n+\t\t *  When this bit is set, it unmasks the interrupt due to ADP_SNS_INT.\n+\t\t *  This bit is valid only if OTG_Ver = 1'b1.\n+\t\t */\n+\t\tunsigned adp_sns_int_msk:1;\n+\t\t/** ADP Timoeout Interrupt Mask (ADP_TMOUT_MSK)\n+\t\t *  When this bit is set, it unmasks the interrupt due to ADP_TMOUT_INT.\n+\t\t *  This bit is valid only if OTG_Ver = 1'b1.\n+\t\t */\n+\t\tunsigned adp_tmout_int_msk:1;\n+\t\t/** Access Request\n+\t\t * 2'b00 - Read/Write Valid (updated by the core)\n+\t\t * 2'b01 - Read\n+\t\t * 2'b00 - Write\n+\t\t * 2'b00 - Reserved\n+\t\t */\n+\t\tunsigned ar:2;\n+\t\t /** Reserved */\n+\t\tunsigned reserved29_31:3;\n+\t} b;\n+} adpctl_data_t;\n+\n+////////////////////////////////////////////\n+// Device Registers\n+/**\n+ * Device Global Registers. <i>Offsets 800h-BFFh</i>\n+ *\n+ * The following structures define the size and relative field offsets\n+ * for the Device Mode Registers.\n+ *\n+ * <i>These registers are visible only in Device mode and must not be\n+ * accessed in Host mode, as the results are unknown.</i>\n+ */\n+typedef struct dwc_otg_dev_global_regs {\n+\t/** Device Configuration Register. <i>Offset 800h</i> */\n+\tvolatile uint32_t dcfg;\n+\t/** Device Control Register. <i>Offset: 804h</i> */\n+\tvolatile uint32_t dctl;\n+\t/** Device Status Register (Read Only). <i>Offset: 808h</i> */\n+\tvolatile uint32_t dsts;\n+\t/** Reserved. <i>Offset: 80Ch</i> */\n+\tuint32_t unused;\n+\t/** Device IN Endpoint Common Interrupt Mask\n+\t * Register. <i>Offset: 810h</i> */\n+\tvolatile uint32_t diepmsk;\n+\t/** Device OUT Endpoint Common Interrupt Mask\n+\t * Register. <i>Offset: 814h</i> */\n+\tvolatile uint32_t doepmsk;\n+\t/** Device All Endpoints Interrupt Register.  <i>Offset: 818h</i> */\n+\tvolatile uint32_t daint;\n+\t/** Device All Endpoints Interrupt Mask Register.  <i>Offset:\n+\t * 81Ch</i> */\n+\tvolatile uint32_t daintmsk;\n+\t/** Device IN Token Queue Read Register-1 (Read Only).\n+\t * <i>Offset: 820h</i> */\n+\tvolatile uint32_t dtknqr1;\n+\t/** Device IN Token Queue Read Register-2 (Read Only).\n+\t * <i>Offset: 824h</i> */\n+\tvolatile uint32_t dtknqr2;\n+\t/** Device VBUS\t discharge Register.  <i>Offset: 828h</i> */\n+\tvolatile uint32_t dvbusdis;\n+\t/** Device VBUS Pulse Register.\t <i>Offset: 82Ch</i> */\n+\tvolatile uint32_t dvbuspulse;\n+\t/** Device IN Token Queue Read Register-3 (Read Only). /\n+\t *\tDevice Thresholding control register (Read/Write)\n+\t * <i>Offset: 830h</i> */\n+\tvolatile uint32_t dtknqr3_dthrctl;\n+\t/** Device IN Token Queue Read Register-4 (Read Only). /\n+\t *\tDevice IN EPs empty Inr. Mask Register (Read/Write)\n+\t * <i>Offset: 834h</i> */\n+\tvolatile uint32_t dtknqr4_fifoemptymsk;\n+\t/** Device Each Endpoint Interrupt Register (Read Only). /\n+\t * <i>Offset: 838h</i> */\n+\tvolatile uint32_t deachint;\n+\t/** Device Each Endpoint Interrupt mask Register (Read/Write). /\n+\t * <i>Offset: 83Ch</i> */\n+\tvolatile uint32_t deachintmsk;\n+\t/** Device Each In Endpoint Interrupt mask Register (Read/Write). /\n+\t * <i>Offset: 840h</i> */\n+\tvolatile uint32_t diepeachintmsk[MAX_EPS_CHANNELS];\n+\t/** Device Each Out Endpoint Interrupt mask Register (Read/Write). /\n+\t * <i>Offset: 880h</i> */\n+\tvolatile uint32_t doepeachintmsk[MAX_EPS_CHANNELS];\n+} dwc_otg_device_global_regs_t;\n+\n+/**\n+ * This union represents the bit fields in the Device Configuration\n+ * Register.  Read the register into the <i>d32</i> member then\n+ * set/clear the bits using the <i>b</i>it elements.  Write the\n+ * <i>d32</i> member to the dcfg register.\n+ */\n+typedef union dcfg_data {\n+\t/** raw register data */\n+\tuint32_t d32;\n+\t/** register bits */\n+\tstruct {\n+\t\t/** Device Speed */\n+\t\tunsigned devspd:2;\n+\t\t/** Non Zero Length Status OUT Handshake */\n+\t\tunsigned nzstsouthshk:1;\n+#define DWC_DCFG_SEND_STALL 1\n+\n+\t\tunsigned ena32khzs:1;\n+\t\t/** Device Addresses */\n+\t\tunsigned devaddr:7;\n+\t\t/** Periodic Frame Interval */\n+\t\tunsigned perfrint:2;\n+#define DWC_DCFG_FRAME_INTERVAL_80 0\n+#define DWC_DCFG_FRAME_INTERVAL_85 1\n+#define DWC_DCFG_FRAME_INTERVAL_90 2\n+#define DWC_DCFG_FRAME_INTERVAL_95 3\n+\n+\t\t/** Enable Device OUT NAK for bulk in DDMA mode */\n+\t\tunsigned endevoutnak:1;\n+\n+\t\tunsigned reserved14_17:4;\n+\t\t/** In Endpoint Mis-match count */\n+\t\tunsigned epmscnt:5;\n+\t\t/** Enable Descriptor DMA in Device mode */\n+\t\tunsigned descdma:1;\n+\t\tunsigned perschintvl:2;\n+\t\tunsigned resvalid:6;\n+\t} b;\n+} dcfg_data_t;\n+\n+/**\n+ * This union represents the bit fields in the Device Control\n+ * Register.  Read the register into the <i>d32</i> member then\n+ * set/clear the bits using the <i>b</i>it elements.\n+ */\n+typedef union dctl_data {\n+\t/** raw register data */\n+\tuint32_t d32;\n+\t/** register bits */\n+\tstruct {\n+\t\t/** Remote Wakeup */\n+\t\tunsigned rmtwkupsig:1;\n+\t\t/** Soft Disconnect */\n+\t\tunsigned sftdiscon:1;\n+\t\t/** Global Non-Periodic IN NAK Status */\n+\t\tunsigned gnpinnaksts:1;\n+\t\t/** Global OUT NAK Status */\n+\t\tunsigned goutnaksts:1;\n+\t\t/** Test Control */\n+\t\tunsigned tstctl:3;\n+\t\t/** Set Global Non-Periodic IN NAK */\n+\t\tunsigned sgnpinnak:1;\n+\t\t/** Clear Global Non-Periodic IN NAK */\n+\t\tunsigned cgnpinnak:1;\n+\t\t/** Set Global OUT NAK */\n+\t\tunsigned sgoutnak:1;\n+\t\t/** Clear Global OUT NAK */\n+\t\tunsigned cgoutnak:1;\n+\t\t/** Power-On Programming Done */\n+\t\tunsigned pwronprgdone:1;\n+\t\t/** Reserved */\n+\t\tunsigned reserved:1;\n+\t\t/** Global Multi Count */\n+\t\tunsigned gmc:2;\n+\t\t/** Ignore Frame Number for ISOC EPs */\n+\t\tunsigned ifrmnum:1;\n+\t\t/** NAK on Babble */\n+\t\tunsigned nakonbble:1;\n+\t\t/** Enable Continue on BNA */\n+\t\tunsigned encontonbna:1;\n+\n+\t\tunsigned reserved18_31:14;\n+\t} b;\n+} dctl_data_t;\n+\n+/**\n+ * This union represents the bit fields in the Device Status\n+ * Register.  Read the register into the <i>d32</i> member then\n+ * set/clear the bits using the <i>b</i>it elements.\n+ */\n+typedef union dsts_data {\n+\t/** raw register data */\n+\tuint32_t d32;\n+\t/** register bits */\n+\tstruct {\n+\t\t/** Suspend Status */\n+\t\tunsigned suspsts:1;\n+\t\t/** Enumerated Speed */\n+\t\tunsigned enumspd:2;\n+#define DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ 0\n+#define DWC_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ 1\n+#define DWC_DSTS_ENUMSPD_LS_PHY_6MHZ\t\t   2\n+#define DWC_DSTS_ENUMSPD_FS_PHY_48MHZ\t\t   3\n+\t\t/** Erratic Error */\n+\t\tunsigned errticerr:1;\n+\t\tunsigned reserved4_7:4;\n+\t\t/** Frame or Microframe Number of the received SOF */\n+\t\tunsigned soffn:14;\n+\t\tunsigned reserved22_31:10;\n+\t} b;\n+} dsts_data_t;\n+\n+/**\n+ * This union represents the bit fields in the Device IN EP Interrupt\n+ * Register and the Device IN EP Common Mask Register.\n+ *\n+ * - Read the register into the <i>d32</i> member then set/clear the\n+ *\t bits using the <i>b</i>it elements.\n+ */\n+typedef union diepint_data {\n+\t/** raw register data */\n+\tuint32_t d32;\n+\t/** register bits */\n+\tstruct {\n+\t\t/** Transfer complete mask */\n+\t\tunsigned xfercompl:1;\n+\t\t/** Endpoint disable mask */\n+\t\tunsigned epdisabled:1;\n+\t\t/** AHB Error mask */\n+\t\tunsigned ahberr:1;\n+\t\t/** TimeOUT Handshake mask (non-ISOC EPs) */\n+\t\tunsigned timeout:1;\n+\t\t/** IN Token received with TxF Empty mask */\n+\t\tunsigned intktxfemp:1;\n+\t\t/** IN Token Received with EP mismatch mask */\n+\t\tunsigned intknepmis:1;\n+\t\t/** IN Endpoint NAK Effective mask */\n+\t\tunsigned inepnakeff:1;\n+\t\t/** Reserved */\n+\t\tunsigned emptyintr:1;\n+\n+\t\tunsigned txfifoundrn:1;\n+\n+\t\t/** BNA Interrupt mask */\n+\t\tunsigned bna:1;\n+\n+\t\tunsigned reserved10_12:3;\n+\t\t/** BNA Interrupt mask */\n+\t\tunsigned nak:1;\n+\n+\t\tunsigned reserved14_31:18;\n+\t} b;\n+} diepint_data_t;\n+\n+/**\n+ * This union represents the bit fields in the Device IN EP\n+ * Common/Dedicated Interrupt Mask Register.\n+ */\n+typedef union diepint_data diepmsk_data_t;\n+\n+/**\n+ * This union represents the bit fields in the Device OUT EP Interrupt\n+ * Registerand Device OUT EP Common Interrupt Mask Register.\n+ *\n+ * - Read the register into the <i>d32</i> member then set/clear the\n+ *\t bits using the <i>b</i>it elements.\n+ */\n+typedef union doepint_data {\n+\t/** raw register data */\n+\tuint32_t d32;\n+\t/** register bits */\n+\tstruct {\n+\t\t/** Transfer complete */\n+\t\tunsigned xfercompl:1;\n+\t\t/** Endpoint disable  */\n+\t\tunsigned epdisabled:1;\n+\t\t/** AHB Error */\n+\t\tunsigned ahberr:1;\n+\t\t/** Setup Phase Done (contorl EPs) */\n+\t\tunsigned setup:1;\n+\t\t/** OUT Token Received when Endpoint Disabled */\n+\t\tunsigned outtknepdis:1;\n+\n+\t\tunsigned stsphsercvd:1;\n+\t\t/** Back-to-Back SETUP Packets Received */\n+\t\tunsigned back2backsetup:1;\n+\n+\t\tunsigned reserved7:1;\n+\t\t/** OUT packet Error */\n+\t\tunsigned outpkterr:1;\n+\t\t/** BNA Interrupt */\n+\t\tunsigned bna:1;\n+\n+\t\tunsigned reserved10:1;\n+\t\t/** Packet Drop Status */\n+\t\tunsigned pktdrpsts:1;\n+\t\t/** Babble Interrupt */\n+\t\tunsigned babble:1;\n+\t\t/** NAK Interrupt */\n+\t\tunsigned nak:1;\n+\t\t/** NYET Interrupt */\n+\t\tunsigned nyet:1;\n+\t\t/** Bit indicating setup packet received */\n+\t\tunsigned sr:1;\n+\n+\t\tunsigned reserved16_31:16;\n+\t} b;\n+} doepint_data_t;\n+\n+/**\n+ * This union represents the bit fields in the Device OUT EP\n+ * Common/Dedicated Interrupt Mask Register.\n+ */\n+typedef union doepint_data doepmsk_data_t;\n+\n+/**\n+ * This union represents the bit fields in the Device All EP Interrupt\n+ * and Mask Registers.\n+ * - Read the register into the <i>d32</i> member then set/clear the\n+ *\t bits using the <i>b</i>it elements.\n+ */\n+typedef union daint_data {\n+\t/** raw register data */\n+\tuint32_t d32;\n+\t/** register bits */\n+\tstruct {\n+\t\t/** IN Endpoint bits */\n+\t\tunsigned in:16;\n+\t\t/** OUT Endpoint bits */\n+\t\tunsigned out:16;\n+\t} ep;\n+\tstruct {\n+\t\t/** IN Endpoint bits */\n+\t\tunsigned inep0:1;\n+\t\tunsigned inep1:1;\n+\t\tunsigned inep2:1;\n+\t\tunsigned inep3:1;\n+\t\tunsigned inep4:1;\n+\t\tunsigned inep5:1;\n+\t\tunsigned inep6:1;\n+\t\tunsigned inep7:1;\n+\t\tunsigned inep8:1;\n+\t\tunsigned inep9:1;\n+\t\tunsigned inep10:1;\n+\t\tunsigned inep11:1;\n+\t\tunsigned inep12:1;\n+\t\tunsigned inep13:1;\n+\t\tunsigned inep14:1;\n+\t\tunsigned inep15:1;\n+\t\t/** OUT Endpoint bits */\n+\t\tunsigned outep0:1;\n+\t\tunsigned outep1:1;\n+\t\tunsigned outep2:1;\n+\t\tunsigned outep3:1;\n+\t\tunsigned outep4:1;\n+\t\tunsigned outep5:1;\n+\t\tunsigned outep6:1;\n+\t\tunsigned outep7:1;\n+\t\tunsigned outep8:1;\n+\t\tunsigned outep9:1;\n+\t\tunsigned outep10:1;\n+\t\tunsigned outep11:1;\n+\t\tunsigned outep12:1;\n+\t\tunsigned outep13:1;\n+\t\tunsigned outep14:1;\n+\t\tunsigned outep15:1;\n+\t} b;\n+} daint_data_t;\n+\n+/**\n+ * This union represents the bit fields in the Device IN Token Queue\n+ * Read Registers.\n+ * - Read the register into the <i>d32</i> member.\n+ * - READ-ONLY Register\n+ */\n+typedef union dtknq1_data {\n+\t/** raw register data */\n+\tuint32_t d32;\n+\t/** register bits */\n+\tstruct {\n+\t\t/** In Token Queue Write Pointer */\n+\t\tunsigned intknwptr:5;\n+\t\t/** Reserved */\n+\t\tunsigned reserved05_06:2;\n+\t\t/** write pointer has wrapped. */\n+\t\tunsigned wrap_bit:1;\n+\t\t/** EP Numbers of IN Tokens 0 ... 4 */\n+\t\tunsigned epnums0_5:24;\n+\t} b;\n+} dtknq1_data_t;\n+\n+/**\n+ * This union represents Threshold control Register\n+ * - Read and write the register into the <i>d32</i> member.\n+ * - READ-WRITABLE Register\n+ */\n+typedef union dthrctl_data {\n+\t/** raw register data */\n+\tuint32_t d32;\n+\t/** register bits */\n+\tstruct {\n+\t\t/** non ISO Tx Thr. Enable */\n+\t\tunsigned non_iso_thr_en:1;\n+\t\t/** ISO Tx Thr. Enable */\n+\t\tunsigned iso_thr_en:1;\n+\t\t/** Tx Thr. Length */\n+\t\tunsigned tx_thr_len:9;\n+\t\t/** AHB Threshold ratio */\n+\t\tunsigned ahb_thr_ratio:2;\n+\t\t/** Reserved */\n+\t\tunsigned reserved13_15:3;\n+\t\t/** Rx Thr. Enable */\n+\t\tunsigned rx_thr_en:1;\n+\t\t/** Rx Thr. Length */\n+\t\tunsigned rx_thr_len:9;\n+\t\tunsigned reserved26:1;\n+\t\t/** Arbiter Parking Enable*/\n+\t\tunsigned arbprken:1;\n+\t\t/** Reserved */\n+\t\tunsigned reserved28_31:4;\n+\t} b;\n+} dthrctl_data_t;\n+\n+/**\n+ * Device Logical IN Endpoint-Specific Registers. <i>Offsets\n+ * 900h-AFCh</i>\n+ *\n+ * There will be one set of endpoint registers per logical endpoint\n+ * implemented.\n+ *\n+ * <i>These registers are visible only in Device mode and must not be\n+ * accessed in Host mode, as the results are unknown.</i>\n+ */\n+typedef struct dwc_otg_dev_in_ep_regs {\n+\t/** Device IN Endpoint Control Register. <i>Offset:900h +\n+\t * (ep_num * 20h) + 00h</i> */\n+\tvolatile uint32_t diepctl;\n+\t/** Reserved. <i>Offset:900h + (ep_num * 20h) + 04h</i> */\n+\tuint32_t reserved04;\n+\t/** Device IN Endpoint Interrupt Register. <i>Offset:900h +\n+\t * (ep_num * 20h) + 08h</i> */\n+\tvolatile uint32_t diepint;\n+\t/** Reserved. <i>Offset:900h + (ep_num * 20h) + 0Ch</i> */\n+\tuint32_t reserved0C;\n+\t/** Device IN Endpoint Transfer Size\n+\t * Register. <i>Offset:900h + (ep_num * 20h) + 10h</i> */\n+\tvolatile uint32_t dieptsiz;\n+\t/** Device IN Endpoint DMA Address Register. <i>Offset:900h +\n+\t * (ep_num * 20h) + 14h</i> */\n+\tvolatile uint32_t diepdma;\n+\t/** Device IN Endpoint Transmit FIFO Status Register. <i>Offset:900h +\n+\t * (ep_num * 20h) + 18h</i> */\n+\tvolatile uint32_t dtxfsts;\n+\t/** Device IN Endpoint DMA Buffer Register. <i>Offset:900h +\n+\t * (ep_num * 20h) + 1Ch</i> */\n+\tvolatile uint32_t diepdmab;\n+} dwc_otg_dev_in_ep_regs_t;\n+\n+/**\n+ * Device Logical OUT Endpoint-Specific Registers. <i>Offsets:\n+ * B00h-CFCh</i>\n+ *\n+ * There will be one set of endpoint registers per logical endpoint\n+ * implemented.\n+ *\n+ * <i>These registers are visible only in Device mode and must not be\n+ * accessed in Host mode, as the results are unknown.</i>\n+ */\n+typedef struct dwc_otg_dev_out_ep_regs {\n+\t/** Device OUT Endpoint Control Register. <i>Offset:B00h +\n+\t * (ep_num * 20h) + 00h</i> */\n+\tvolatile uint32_t doepctl;\n+\t/** Reserved. <i>Offset:B00h + (ep_num * 20h) + 04h</i> */\n+\tuint32_t reserved04;\n+\t/** Device OUT Endpoint Interrupt Register. <i>Offset:B00h +\n+\t * (ep_num * 20h) + 08h</i> */\n+\tvolatile uint32_t doepint;\n+\t/** Reserved. <i>Offset:B00h + (ep_num * 20h) + 0Ch</i> */\n+\tuint32_t reserved0C;\n+\t/** Device OUT Endpoint Transfer Size Register. <i>Offset:\n+\t * B00h + (ep_num * 20h) + 10h</i> */\n+\tvolatile uint32_t doeptsiz;\n+\t/** Device OUT Endpoint DMA Address Register. <i>Offset:B00h\n+\t * + (ep_num * 20h) + 14h</i> */\n+\tvolatile uint32_t doepdma;\n+\t/** Reserved. <i>Offset:B00h + \t * (ep_num * 20h) + 18h</i> */\n+\tuint32_t unused;\n+\t/** Device OUT Endpoint DMA Buffer Register. <i>Offset:B00h\n+\t * + (ep_num * 20h) + 1Ch</i> */\n+\tuint32_t doepdmab;\n+} dwc_otg_dev_out_ep_regs_t;\n+\n+/**\n+ * This union represents the bit fields in the Device EP Control\n+ * Register.  Read the register into the <i>d32</i> member then\n+ * set/clear the bits using the <i>b</i>it elements.\n+ */\n+typedef union depctl_data {\n+\t/** raw register data */\n+\tuint32_t d32;\n+\t/** register bits */\n+\tstruct {\n+\t\t/** Maximum Packet Size\n+\t\t * IN/OUT EPn\n+\t\t * IN/OUT EP0 - 2 bits\n+\t\t *\t 2'b00: 64 Bytes\n+\t\t *\t 2'b01: 32\n+\t\t *\t 2'b10: 16\n+\t\t *\t 2'b11: 8 */\n+\t\tunsigned mps:11;\n+#define DWC_DEP0CTL_MPS_64\t 0\n+#define DWC_DEP0CTL_MPS_32\t 1\n+#define DWC_DEP0CTL_MPS_16\t 2\n+#define DWC_DEP0CTL_MPS_8\t 3\n+\n+\t\t/** Next Endpoint\n+\t\t * IN EPn/IN EP0\n+\t\t * OUT EPn/OUT EP0 - reserved */\n+\t\tunsigned nextep:4;\n+\n+\t\t/** USB Active Endpoint */\n+\t\tunsigned usbactep:1;\n+\n+\t\t/** Endpoint DPID (INTR/Bulk IN and OUT endpoints)\n+\t\t * This field contains the PID of the packet going to\n+\t\t * be received or transmitted on this endpoint. The\n+\t\t * application should program the PID of the first\n+\t\t * packet going to be received or transmitted on this\n+\t\t * endpoint , after the endpoint is\n+\t\t * activated. Application use the SetD1PID and\n+\t\t * SetD0PID fields of this register to program either\n+\t\t * D0 or D1 PID.\n+\t\t *\n+\t\t * The encoding for this field is\n+\t\t *\t - 0: D0\n+\t\t *\t - 1: D1\n+\t\t */\n+\t\tunsigned dpid:1;\n+\n+\t\t/** NAK Status */\n+\t\tunsigned naksts:1;\n+\n+\t\t/** Endpoint Type\n+\t\t *\t2'b00: Control\n+\t\t *\t2'b01: Isochronous\n+\t\t *\t2'b10: Bulk\n+\t\t *\t2'b11: Interrupt */\n+\t\tunsigned eptype:2;\n+\n+\t\t/** Snoop Mode\n+\t\t * OUT EPn/OUT EP0\n+\t\t * IN EPn/IN EP0 - reserved */\n+\t\tunsigned snp:1;\n+\n+\t\t/** Stall Handshake */\n+\t\tunsigned stall:1;\n+\n+\t\t/** Tx Fifo Number\n+\t\t * IN EPn/IN EP0\n+\t\t * OUT EPn/OUT EP0 - reserved */\n+\t\tunsigned txfnum:4;\n+\n+\t\t/** Clear NAK */\n+\t\tunsigned cnak:1;\n+\t\t/** Set NAK */\n+\t\tunsigned snak:1;\n+\t\t/** Set DATA0 PID (INTR/Bulk IN and OUT endpoints)\n+\t\t * Writing to this field sets the Endpoint DPID (DPID)\n+\t\t * field in this register to DATA0. Set Even\n+\t\t * (micro)frame (SetEvenFr) (ISO IN and OUT Endpoints)\n+\t\t * Writing to this field sets the Even/Odd\n+\t\t * (micro)frame (EO_FrNum) field to even (micro)\n+\t\t * frame.\n+\t\t */\n+\t\tunsigned setd0pid:1;\n+\t\t/** Set DATA1 PID (INTR/Bulk IN and OUT endpoints)\n+\t\t * Writing to this field sets the Endpoint DPID (DPID)\n+\t\t * field in this register to DATA1 Set Odd\n+\t\t * (micro)frame (SetOddFr) (ISO IN and OUT Endpoints)\n+\t\t * Writing to this field sets the Even/Odd\n+\t\t * (micro)frame (EO_FrNum) field to odd (micro) frame.\n+\t\t */\n+\t\tunsigned setd1pid:1;\n+\n+\t\t/** Endpoint Disable */\n+\t\tunsigned epdis:1;\n+\t\t/** Endpoint Enable */\n+\t\tunsigned epena:1;\n+\t} b;\n+} depctl_data_t;\n+\n+/**\n+ * This union represents the bit fields in the Device EP Transfer\n+ * Size Register.  Read the register into the <i>d32</i> member then\n+ * set/clear the bits using the <i>b</i>it elements.\n+ */\n+typedef union deptsiz_data {\n+\t\t/** raw register data */\n+\tuint32_t d32;\n+\t\t/** register bits */\n+\tstruct {\n+\t\t/** Transfer size */\n+\t\tunsigned xfersize:19;\n+/** Max packet count for EP (pow(2,10)-1) */\n+#define MAX_PKT_CNT 1023\n+\t\t/** Packet Count */\n+\t\tunsigned pktcnt:10;\n+\t\t/** Multi Count - Periodic IN endpoints */\n+\t\tunsigned mc:2;\n+\t\tunsigned reserved:1;\n+\t} b;\n+} deptsiz_data_t;\n+\n+/**\n+ * This union represents the bit fields in the Device EP 0 Transfer\n+ * Size Register.  Read the register into the <i>d32</i> member then\n+ * set/clear the bits using the <i>b</i>it elements.\n+ */\n+typedef union deptsiz0_data {\n+\t\t/** raw register data */\n+\tuint32_t d32;\n+\t\t/** register bits */\n+\tstruct {\n+\t\t/** Transfer size */\n+\t\tunsigned xfersize:7;\n+\t\t\t\t/** Reserved */\n+\t\tunsigned reserved7_18:12;\n+\t\t/** Packet Count */\n+\t\tunsigned pktcnt:2;\n+\t\t\t\t/** Reserved */\n+\t\tunsigned reserved21_28:8;\n+\t\t\t\t/**Setup Packet Count (DOEPTSIZ0 Only) */\n+\t\tunsigned supcnt:2;\n+\t\tunsigned reserved31;\n+\t} b;\n+} deptsiz0_data_t;\n+\n+/////////////////////////////////////////////////\n+// DMA Descriptor Specific Structures\n+//\n+\n+/** Buffer status definitions */\n+\n+#define BS_HOST_READY\t0x0\n+#define BS_DMA_BUSY\t\t0x1\n+#define BS_DMA_DONE\t\t0x2\n+#define BS_HOST_BUSY\t0x3\n+\n+/** Receive/Transmit status definitions */\n+\n+#define RTS_SUCCESS\t\t0x0\n+#define RTS_BUFFLUSH\t0x1\n+#define RTS_RESERVED\t0x2\n+#define RTS_BUFERR\t\t0x3\n+\n+/**\n+ * This union represents the bit fields in the DMA Descriptor\n+ * status quadlet. Read the quadlet into the <i>d32</i> member then\n+ * set/clear the bits using the <i>b</i>it, <i>b_iso_out</i> and\n+ * <i>b_iso_in</i> elements.\n+ */\n+typedef union dev_dma_desc_sts {\n+\t\t/** raw register data */\n+\tuint32_t d32;\n+\t\t/** quadlet bits */\n+\tstruct {\n+\t\t/** Received number of bytes */\n+\t\tunsigned bytes:16;\n+\t\t/** NAK bit - only for OUT EPs */\n+\t\tunsigned nak:1;\n+\t\tunsigned reserved17_22:6;\n+\t\t/** Multiple Transfer - only for OUT EPs */\n+\t\tunsigned mtrf:1;\n+\t\t/** Setup Packet received - only for OUT EPs */\n+\t\tunsigned sr:1;\n+\t\t/** Interrupt On Complete */\n+\t\tunsigned ioc:1;\n+\t\t/** Short Packet */\n+\t\tunsigned sp:1;\n+\t\t/** Last */\n+\t\tunsigned l:1;\n+\t\t/** Receive Status */\n+\t\tunsigned sts:2;\n+\t\t/** Buffer Status */\n+\t\tunsigned bs:2;\n+\t} b;\n+\n+//#ifdef DWC_EN_ISOC\n+\t\t/** iso out quadlet bits */\n+\tstruct {\n+\t\t/** Received number of bytes */\n+\t\tunsigned rxbytes:11;\n+\n+\t\tunsigned reserved11:1;\n+\t\t/** Frame Number */\n+\t\tunsigned framenum:11;\n+\t\t/** Received ISO Data PID */\n+\t\tunsigned pid:2;\n+\t\t/** Interrupt On Complete */\n+\t\tunsigned ioc:1;\n+\t\t/** Short Packet */\n+\t\tunsigned sp:1;\n+\t\t/** Last */\n+\t\tunsigned l:1;\n+\t\t/** Receive Status */\n+\t\tunsigned rxsts:2;\n+\t\t/** Buffer Status */\n+\t\tunsigned bs:2;\n+\t} b_iso_out;\n+\n+\t\t/** iso in quadlet bits */\n+\tstruct {\n+\t\t/** Transmited number of bytes */\n+\t\tunsigned txbytes:12;\n+\t\t/** Frame Number */\n+\t\tunsigned framenum:11;\n+\t\t/** Transmited ISO Data PID */\n+\t\tunsigned pid:2;\n+\t\t/** Interrupt On Complete */\n+\t\tunsigned ioc:1;\n+\t\t/** Short Packet */\n+\t\tunsigned sp:1;\n+\t\t/** Last */\n+\t\tunsigned l:1;\n+\t\t/** Transmit Status */\n+\t\tunsigned txsts:2;\n+\t\t/** Buffer Status */\n+\t\tunsigned bs:2;\n+\t} b_iso_in;\n+//#endif                                /* DWC_EN_ISOC */\n+} dev_dma_desc_sts_t;\n+\n+/**\n+ * DMA Descriptor structure\n+ *\n+ * DMA Descriptor structure contains two quadlets:\n+ * Status quadlet and Data buffer pointer.\n+ */\n+typedef struct dwc_otg_dev_dma_desc {\n+\t/** DMA Descriptor status quadlet */\n+\tdev_dma_desc_sts_t status;\n+\t/** DMA Descriptor data buffer pointer */\n+\tuint32_t buf;\n+} dwc_otg_dev_dma_desc_t;\n+\n+/**\n+ * The dwc_otg_dev_if structure contains information needed to manage\n+ * the DWC_otg controller acting in device mode. It represents the\n+ * programming view of the device-specific aspects of the controller.\n+ */\n+typedef struct dwc_otg_dev_if {\n+\t/** Pointer to device Global registers.\n+\t * Device Global Registers starting at offset 800h\n+\t */\n+\tdwc_otg_device_global_regs_t *dev_global_regs;\n+#define DWC_DEV_GLOBAL_REG_OFFSET 0x800\n+\n+\t/**\n+\t * Device Logical IN Endpoint-Specific Registers 900h-AFCh\n+\t */\n+\tdwc_otg_dev_in_ep_regs_t *in_ep_regs[MAX_EPS_CHANNELS];\n+#define DWC_DEV_IN_EP_REG_OFFSET 0x900\n+#define DWC_EP_REG_OFFSET 0x20\n+\n+\t/** Device Logical OUT Endpoint-Specific Registers B00h-CFCh */\n+\tdwc_otg_dev_out_ep_regs_t *out_ep_regs[MAX_EPS_CHANNELS];\n+#define DWC_DEV_OUT_EP_REG_OFFSET 0xB00\n+\n+\t/* Device configuration information */\n+\tuint8_t speed;\t\t\t\t /**< Device Speed\t0: Unknown, 1: LS, 2:FS, 3: HS */\n+\tuint8_t num_in_eps;\t\t /**< Number # of Tx EP range: 0-15 exept ep0 */\n+\tuint8_t num_out_eps;\t\t /**< Number # of Rx EP range: 0-15 exept ep 0*/\n+\n+\t/** Size of periodic FIFOs (Bytes) */\n+\tuint16_t perio_tx_fifo_size[MAX_PERIO_FIFOS];\n+\n+\t/** Size of Tx FIFOs (Bytes) */\n+\tuint16_t tx_fifo_size[MAX_TX_FIFOS];\n+\n+\t/** Thresholding enable flags and length varaiables **/\n+\tuint16_t rx_thr_en;\n+\tuint16_t iso_tx_thr_en;\n+\tuint16_t non_iso_tx_thr_en;\n+\n+\tuint16_t rx_thr_length;\n+\tuint16_t tx_thr_length;\n+\n+\t/**\n+\t * Pointers to the DMA Descriptors for EP0 Control\n+\t * transfers (virtual and physical)\n+\t */\n+\n+\t/** 2 descriptors for SETUP packets */\n+\tdwc_dma_t dma_setup_desc_addr[2];\n+\tdwc_otg_dev_dma_desc_t *setup_desc_addr[2];\n+\n+\t/** Pointer to Descriptor with latest SETUP packet */\n+\tdwc_otg_dev_dma_desc_t *psetup;\n+\n+\t/** Index of current SETUP handler descriptor */\n+\tuint32_t setup_desc_index;\n+\n+\t/** Descriptor for Data In or Status In phases */\n+\tdwc_dma_t dma_in_desc_addr;\n+\tdwc_otg_dev_dma_desc_t *in_desc_addr;\n+\n+\t/** Descriptor for Data Out or Status Out phases */\n+\tdwc_dma_t dma_out_desc_addr;\n+\tdwc_otg_dev_dma_desc_t *out_desc_addr;\n+\n+\t/** Setup Packet Detected - if set clear NAK when queueing */\n+\tuint32_t spd;\n+\t/** Isoc ep pointer on which incomplete happens */\n+\tvoid *isoc_ep;\n+\n+} dwc_otg_dev_if_t;\n+\n+/////////////////////////////////////////////////\n+// Host Mode Register Structures\n+//\n+/**\n+ * The Host Global Registers structure defines the size and relative\n+ * field offsets for the Host Mode Global Registers.  Host Global\n+ * Registers offsets 400h-7FFh.\n+*/\n+typedef struct dwc_otg_host_global_regs {\n+\t/** Host Configuration Register.   <i>Offset: 400h</i> */\n+\tvolatile uint32_t hcfg;\n+\t/** Host Frame Interval Register.\t<i>Offset: 404h</i> */\n+\tvolatile uint32_t hfir;\n+\t/** Host Frame Number / Frame Remaining Register. <i>Offset: 408h</i> */\n+\tvolatile uint32_t hfnum;\n+\t/** Reserved.\t<i>Offset: 40Ch</i> */\n+\tuint32_t reserved40C;\n+\t/** Host Periodic Transmit FIFO/ Queue Status Register. <i>Offset: 410h</i> */\n+\tvolatile uint32_t hptxsts;\n+\t/** Host All Channels Interrupt Register. <i>Offset: 414h</i> */\n+\tvolatile uint32_t haint;\n+\t/** Host All Channels Interrupt Mask Register. <i>Offset: 418h</i> */\n+\tvolatile uint32_t haintmsk;\n+\t/** Host Frame List Base Address Register . <i>Offset: 41Ch</i> */\n+\tvolatile uint32_t hflbaddr;\n+} dwc_otg_host_global_regs_t;\n+\n+/**\n+ * This union represents the bit fields in the Host Configuration Register.\n+ * Read the register into the <i>d32</i> member then set/clear the bits using\n+ * the <i>b</i>it elements. Write the <i>d32</i> member to the hcfg register.\n+ */\n+typedef union hcfg_data {\n+\t/** raw register data */\n+\tuint32_t d32;\n+\n+\t/** register bits */\n+\tstruct {\n+\t\t/** FS/LS Phy Clock Select */\n+\t\tunsigned fslspclksel:2;\n+#define DWC_HCFG_30_60_MHZ 0\n+#define DWC_HCFG_48_MHZ\t   1\n+#define DWC_HCFG_6_MHZ\t   2\n+\n+\t\t/** FS/LS Only Support */\n+\t\tunsigned fslssupp:1;\n+\t\tunsigned reserved3_6:4;\n+\t\t/** Enable 32-KHz Suspend Mode */\n+\t\tunsigned ena32khzs:1;\n+\t\t/** Resume Validation Periiod */\n+\t\tunsigned resvalid:8;\n+\t\tunsigned reserved16_22:7;\n+\t\t/** Enable Scatter/gather DMA in Host mode */\n+\t\tunsigned descdma:1;\n+\t\t/** Frame List Entries */\n+\t\tunsigned frlisten:2;\n+\t\t/** Enable Periodic Scheduling */\n+\t\tunsigned perschedena:1;\n+\t\tunsigned reserved27_30:4;\n+\t\tunsigned modechtimen:1;\n+\t} b;\n+} hcfg_data_t;\n+\n+/**\n+ * This union represents the bit fields in the Host Frame Remaing/Number\n+ * Register.\n+ */\n+typedef union hfir_data {\n+\t/** raw register data */\n+\tuint32_t d32;\n+\n+\t/** register bits */\n+\tstruct {\n+\t\tunsigned frint:16;\n+\t\tunsigned hfirrldctrl:1;\n+\t\tunsigned reserved:15;\n+\t} b;\n+} hfir_data_t;\n+\n+/**\n+ * This union represents the bit fields in the Host Frame Remaing/Number\n+ * Register.\n+ */\n+typedef union hfnum_data {\n+\t/** raw register data */\n+\tuint32_t d32;\n+\n+\t/** register bits */\n+\tstruct {\n+\t\tunsigned frnum:16;\n+#define DWC_HFNUM_MAX_FRNUM 0x3FFF\n+\t\tunsigned frrem:16;\n+\t} b;\n+} hfnum_data_t;\n+\n+typedef union hptxsts_data {\n+\t/** raw register data */\n+\tuint32_t d32;\n+\n+\t/** register bits */\n+\tstruct {\n+\t\tunsigned ptxfspcavail:16;\n+\t\tunsigned ptxqspcavail:8;\n+\t\t/** Top of the Periodic Transmit Request Queue\n+\t\t *\t- bit 24 - Terminate (last entry for the selected channel)\n+\t\t *\t- bits 26:25 - Token Type\n+\t\t *\t  - 2'b00 - Zero length\n+\t\t *\t  - 2'b01 - Ping\n+\t\t *\t  - 2'b10 - Disable\n+\t\t *\t- bits 30:27 - Channel Number\n+\t\t *\t- bit 31 - Odd/even microframe\n+\t\t */\n+\t\tunsigned ptxqtop_terminate:1;\n+\t\tunsigned ptxqtop_token:2;\n+\t\tunsigned ptxqtop_chnum:4;\n+\t\tunsigned ptxqtop_odd:1;\n+\t} b;\n+} hptxsts_data_t;\n+\n+/**\n+ * This union represents the bit fields in the Host Port Control and Status\n+ * Register. Read the register into the <i>d32</i> member then set/clear the\n+ * bits using the <i>b</i>it elements. Write the <i>d32</i> member to the\n+ * hprt0 register.\n+ */\n+typedef union hprt0_data {\n+\t/** raw register data */\n+\tuint32_t d32;\n+\t/** register bits */\n+\tstruct {\n+\t\tunsigned prtconnsts:1;\n+\t\tunsigned prtconndet:1;\n+\t\tunsigned prtena:1;\n+\t\tunsigned prtenchng:1;\n+\t\tunsigned prtovrcurract:1;\n+\t\tunsigned prtovrcurrchng:1;\n+\t\tunsigned prtres:1;\n+\t\tunsigned prtsusp:1;\n+\t\tunsigned prtrst:1;\n+\t\tunsigned reserved9:1;\n+\t\tunsigned prtlnsts:2;\n+\t\tunsigned prtpwr:1;\n+\t\tunsigned prttstctl:4;\n+\t\tunsigned prtspd:2;\n+#define DWC_HPRT0_PRTSPD_HIGH_SPEED 0\n+#define DWC_HPRT0_PRTSPD_FULL_SPEED 1\n+#define DWC_HPRT0_PRTSPD_LOW_SPEED\t2\n+\t\tunsigned reserved19_31:13;\n+\t} b;\n+} hprt0_data_t;\n+\n+/**\n+ * This union represents the bit fields in the Host All Interrupt\n+ * Register.\n+ */\n+typedef union haint_data {\n+\t/** raw register data */\n+\tuint32_t d32;\n+\t/** register bits */\n+\tstruct {\n+\t\tunsigned ch0:1;\n+\t\tunsigned ch1:1;\n+\t\tunsigned ch2:1;\n+\t\tunsigned ch3:1;\n+\t\tunsigned ch4:1;\n+\t\tunsigned ch5:1;\n+\t\tunsigned ch6:1;\n+\t\tunsigned ch7:1;\n+\t\tunsigned ch8:1;\n+\t\tunsigned ch9:1;\n+\t\tunsigned ch10:1;\n+\t\tunsigned ch11:1;\n+\t\tunsigned ch12:1;\n+\t\tunsigned ch13:1;\n+\t\tunsigned ch14:1;\n+\t\tunsigned ch15:1;\n+\t\tunsigned reserved:16;\n+\t} b;\n+\n+\tstruct {\n+\t\tunsigned chint:16;\n+\t\tunsigned reserved:16;\n+\t} b2;\n+} haint_data_t;\n+\n+/**\n+ * This union represents the bit fields in the Host All Interrupt\n+ * Register.\n+ */\n+typedef union haintmsk_data {\n+\t/** raw register data */\n+\tuint32_t d32;\n+\t/** register bits */\n+\tstruct {\n+\t\tunsigned ch0:1;\n+\t\tunsigned ch1:1;\n+\t\tunsigned ch2:1;\n+\t\tunsigned ch3:1;\n+\t\tunsigned ch4:1;\n+\t\tunsigned ch5:1;\n+\t\tunsigned ch6:1;\n+\t\tunsigned ch7:1;\n+\t\tunsigned ch8:1;\n+\t\tunsigned ch9:1;\n+\t\tunsigned ch10:1;\n+\t\tunsigned ch11:1;\n+\t\tunsigned ch12:1;\n+\t\tunsigned ch13:1;\n+\t\tunsigned ch14:1;\n+\t\tunsigned ch15:1;\n+\t\tunsigned reserved:16;\n+\t} b;\n+\n+\tstruct {\n+\t\tunsigned chint:16;\n+\t\tunsigned reserved:16;\n+\t} b2;\n+} haintmsk_data_t;\n+\n+/**\n+ * Host Channel Specific Registers. <i>500h-5FCh</i>\n+ */\n+typedef struct dwc_otg_hc_regs {\n+\t/** Host Channel 0 Characteristic Register. <i>Offset: 500h + (chan_num * 20h) + 00h</i> */\n+\tvolatile uint32_t hcchar;\n+\t/** Host Channel 0 Split Control Register. <i>Offset: 500h + (chan_num * 20h) + 04h</i> */\n+\tvolatile uint32_t hcsplt;\n+\t/** Host Channel 0 Interrupt Register. <i>Offset: 500h + (chan_num * 20h) + 08h</i> */\n+\tvolatile uint32_t hcint;\n+\t/** Host Channel 0 Interrupt Mask Register. <i>Offset: 500h + (chan_num * 20h) + 0Ch</i> */\n+\tvolatile uint32_t hcintmsk;\n+\t/** Host Channel 0 Transfer Size Register. <i>Offset: 500h + (chan_num * 20h) + 10h</i> */\n+\tvolatile uint32_t hctsiz;\n+\t/** Host Channel 0 DMA Address Register. <i>Offset: 500h + (chan_num * 20h) + 14h</i> */\n+\tvolatile uint32_t hcdma;\n+\tvolatile uint32_t reserved;\n+\t/** Host Channel 0 DMA Buffer Address Register. <i>Offset: 500h + (chan_num * 20h) + 1Ch</i> */\n+\tvolatile uint32_t hcdmab;\n+} dwc_otg_hc_regs_t;\n+\n+/**\n+ * This union represents the bit fields in the Host Channel Characteristics\n+ * Register. Read the register into the <i>d32</i> member then set/clear the\n+ * bits using the <i>b</i>it elements. Write the <i>d32</i> member to the\n+ * hcchar register.\n+ */\n+typedef union hcchar_data {\n+\t/** raw register data */\n+\tuint32_t d32;\n+\n+\t/** register bits */\n+\tstruct {\n+\t\t/** Maximum packet size in bytes */\n+\t\tunsigned mps:11;\n+\n+\t\t/** Endpoint number */\n+\t\tunsigned epnum:4;\n+\n+\t\t/** 0: OUT, 1: IN */\n+\t\tunsigned epdir:1;\n+\n+\t\tunsigned reserved:1;\n+\n+\t\t/** 0: Full/high speed device, 1: Low speed device */\n+\t\tunsigned lspddev:1;\n+\n+\t\t/** 0: Control, 1: Isoc, 2: Bulk, 3: Intr */\n+\t\tunsigned eptype:2;\n+\n+\t\t/** Packets per frame for periodic transfers. 0 is reserved. */\n+\t\tunsigned multicnt:2;\n+\n+\t\t/** Device address */\n+\t\tunsigned devaddr:7;\n+\n+\t\t/**\n+\t\t * Frame to transmit periodic transaction.\n+\t\t * 0: even, 1: odd\n+\t\t */\n+\t\tunsigned oddfrm:1;\n+\n+\t\t/** Channel disable */\n+\t\tunsigned chdis:1;\n+\n+\t\t/** Channel enable */\n+\t\tunsigned chen:1;\n+\t} b;\n+} hcchar_data_t;\n+\n+typedef union hcsplt_data {\n+\t/** raw register data */\n+\tuint32_t d32;\n+\n+\t/** register bits */\n+\tstruct {\n+\t\t/** Port Address */\n+\t\tunsigned prtaddr:7;\n+\n+\t\t/** Hub Address */\n+\t\tunsigned hubaddr:7;\n+\n+\t\t/** Transaction Position */\n+\t\tunsigned xactpos:2;\n+#define DWC_HCSPLIT_XACTPOS_MID 0\n+#define DWC_HCSPLIT_XACTPOS_END 1\n+#define DWC_HCSPLIT_XACTPOS_BEGIN 2\n+#define DWC_HCSPLIT_XACTPOS_ALL 3\n+\n+\t\t/** Do Complete Split */\n+\t\tunsigned compsplt:1;\n+\n+\t\t/** Reserved */\n+\t\tunsigned reserved:14;\n+\n+\t\t/** Split Enble */\n+\t\tunsigned spltena:1;\n+\t} b;\n+} hcsplt_data_t;\n+\n+/**\n+ * This union represents the bit fields in the Host All Interrupt\n+ * Register.\n+ */\n+typedef union hcint_data {\n+\t/** raw register data */\n+\tuint32_t d32;\n+\t/** register bits */\n+\tstruct {\n+\t\t/** Transfer Complete */\n+\t\tunsigned xfercomp:1;\n+\t\t/** Channel Halted */\n+\t\tunsigned chhltd:1;\n+\t\t/** AHB Error */\n+\t\tunsigned ahberr:1;\n+\t\t/** STALL Response Received */\n+\t\tunsigned stall:1;\n+\t\t/** NAK Response Received */\n+\t\tunsigned nak:1;\n+\t\t/** ACK Response Received */\n+\t\tunsigned ack:1;\n+\t\t/** NYET Response Received */\n+\t\tunsigned nyet:1;\n+\t\t/** Transaction Err */\n+\t\tunsigned xacterr:1;\n+\t\t/** Babble Error */\n+\t\tunsigned bblerr:1;\n+\t\t/** Frame Overrun */\n+\t\tunsigned frmovrun:1;\n+\t\t/** Data Toggle Error */\n+\t\tunsigned datatglerr:1;\n+\t\t/** Buffer Not Available (only for DDMA mode) */\n+\t\tunsigned bna:1;\n+\t\t/** Exessive transaction error (only for DDMA mode) */\n+\t\tunsigned xcs_xact:1;\n+\t\t/** Frame List Rollover interrupt */\n+\t\tunsigned frm_list_roll:1;\n+\t\t/** Reserved */\n+\t\tunsigned reserved14_31:18;\n+\t} b;\n+} hcint_data_t;\n+\n+/**\n+ * This union represents the bit fields in the Host Channel Interrupt Mask\n+ * Register. Read the register into the <i>d32</i> member then set/clear the\n+ * bits using the <i>b</i>it elements. Write the <i>d32</i> member to the\n+ * hcintmsk register.\n+ */\n+typedef union hcintmsk_data {\n+\t/** raw register data */\n+\tuint32_t d32;\n+\n+\t/** register bits */\n+\tstruct {\n+\t\tunsigned xfercompl:1;\n+\t\tunsigned chhltd:1;\n+\t\tunsigned ahberr:1;\n+\t\tunsigned stall:1;\n+\t\tunsigned nak:1;\n+\t\tunsigned ack:1;\n+\t\tunsigned nyet:1;\n+\t\tunsigned xacterr:1;\n+\t\tunsigned bblerr:1;\n+\t\tunsigned frmovrun:1;\n+\t\tunsigned datatglerr:1;\n+\t\tunsigned bna:1;\n+\t\tunsigned xcs_xact:1;\n+\t\tunsigned frm_list_roll:1;\n+\t\tunsigned reserved14_31:18;\n+\t} b;\n+} hcintmsk_data_t;\n+\n+/**\n+ * This union represents the bit fields in the Host Channel Transfer Size\n+ * Register. Read the register into the <i>d32</i> member then set/clear the\n+ * bits using the <i>b</i>it elements. Write the <i>d32</i> member to the\n+ * hcchar register.\n+ */\n+\n+typedef union hctsiz_data {\n+\t/** raw register data */\n+\tuint32_t d32;\n+\n+\t/** register bits */\n+\tstruct {\n+\t\t/** Total transfer size in bytes */\n+\t\tunsigned xfersize:19;\n+\n+\t\t/** Data packets to transfer */\n+\t\tunsigned pktcnt:10;\n+\n+\t\t/**\n+\t\t * Packet ID for next data packet\n+\t\t * 0: DATA0\n+\t\t * 1: DATA2\n+\t\t * 2: DATA1\n+\t\t * 3: MDATA (non-Control), SETUP (Control)\n+\t\t */\n+\t\tunsigned pid:2;\n+#define DWC_HCTSIZ_DATA0 0\n+#define DWC_HCTSIZ_DATA1 2\n+#define DWC_HCTSIZ_DATA2 1\n+#define DWC_HCTSIZ_MDATA 3\n+#define DWC_HCTSIZ_SETUP 3\n+\n+\t\t/** Do PING protocol when 1 */\n+\t\tunsigned dopng:1;\n+\t} b;\n+\n+\t/** register bits */\n+\tstruct {\n+\t\t/** Scheduling information */\n+\t\tunsigned schinfo:8;\n+\n+\t\t/** Number of transfer descriptors.\n+\t\t * Max value:\n+\t\t * 64 in general,\n+\t\t * 256 only for HS isochronous endpoint.\n+\t\t */\n+\t\tunsigned ntd:8;\n+\n+\t\t/** Data packets to transfer */\n+\t\tunsigned reserved16_28:13;\n+\n+\t\t/**\n+\t\t * Packet ID for next data packet\n+\t\t * 0: DATA0\n+\t\t * 1: DATA2\n+\t\t * 2: DATA1\n+\t\t * 3: MDATA (non-Control)\n+\t\t */\n+\t\tunsigned pid:2;\n+\n+\t\t/** Do PING protocol when 1 */\n+\t\tunsigned dopng:1;\n+\t} b_ddma;\n+} hctsiz_data_t;\n+\n+/**\n+ * This union represents the bit fields in the Host DMA Address\n+ * Register used in Descriptor DMA mode.\n+ */\n+typedef union hcdma_data {\n+\t/** raw register data */\n+\tuint32_t d32;\n+\t/** register bits */\n+\tstruct {\n+\t\tunsigned reserved0_2:3;\n+\t\t/** Current Transfer Descriptor. Not used for ISOC */\n+\t\tunsigned ctd:8;\n+\t\t/** Start Address of Descriptor List */\n+\t\tunsigned dma_addr:21;\n+\t} b;\n+} hcdma_data_t;\n+\n+/**\n+ * This union represents the bit fields in the DMA Descriptor\n+ * status quadlet for host mode. Read the quadlet into the <i>d32</i> member then\n+ * set/clear the bits using the <i>b</i>it elements.\n+ */\n+typedef union host_dma_desc_sts {\n+\t/** raw register data */\n+\tuint32_t d32;\n+\t/** quadlet bits */\n+\n+\t/* for non-isochronous  */\n+\tstruct {\n+\t\t/** Number of bytes */\n+\t\tunsigned n_bytes:17;\n+\t\t/** QTD offset to jump when Short Packet received - only for IN EPs */\n+\t\tunsigned qtd_offset:6;\n+\t\t/**\n+\t\t * Set to request the core to jump to alternate QTD if\n+\t\t * Short Packet received - only for IN EPs\n+\t\t */\n+\t\tunsigned a_qtd:1;\n+\t\t /**\n+\t\t  * Setup Packet bit. When set indicates that buffer contains\n+\t\t  * setup packet.\n+\t\t  */\n+\t\tunsigned sup:1;\n+\t\t/** Interrupt On Complete */\n+\t\tunsigned ioc:1;\n+\t\t/** End of List */\n+\t\tunsigned eol:1;\n+\t\tunsigned reserved27:1;\n+\t\t/** Rx/Tx Status */\n+\t\tunsigned sts:2;\n+#define DMA_DESC_STS_PKTERR\t1\n+\t\tunsigned reserved30:1;\n+\t\t/** Active Bit */\n+\t\tunsigned a:1;\n+\t} b;\n+\t/* for isochronous */\n+\tstruct {\n+\t\t/** Number of bytes */\n+\t\tunsigned n_bytes:12;\n+\t\tunsigned reserved12_24:13;\n+\t\t/** Interrupt On Complete */\n+\t\tunsigned ioc:1;\n+\t\tunsigned reserved26_27:2;\n+\t\t/** Rx/Tx Status */\n+\t\tunsigned sts:2;\n+\t\tunsigned reserved30:1;\n+\t\t/** Active Bit */\n+\t\tunsigned a:1;\n+\t} b_isoc;\n+} host_dma_desc_sts_t;\n+\n+#define\tMAX_DMA_DESC_SIZE\t\t131071\n+#define MAX_DMA_DESC_NUM_GENERIC\t64\n+#define MAX_DMA_DESC_NUM_HS_ISOC\t256\n+#define MAX_FRLIST_EN_NUM\t\t64\n+/**\n+ * Host-mode DMA Descriptor structure\n+ *\n+ * DMA Descriptor structure contains two quadlets:\n+ * Status quadlet and Data buffer pointer.\n+ */\n+typedef struct dwc_otg_host_dma_desc {\n+\t/** DMA Descriptor status quadlet */\n+\thost_dma_desc_sts_t status;\n+\t/** DMA Descriptor data buffer pointer */\n+\tuint32_t buf;\n+} dwc_otg_host_dma_desc_t;\n+\n+/** OTG Host Interface Structure.\n+ *\n+ * The OTG Host Interface Structure structure contains information\n+ * needed to manage the DWC_otg controller acting in host mode. It\n+ * represents the programming view of the host-specific aspects of the\n+ * controller.\n+ */\n+typedef struct dwc_otg_host_if {\n+\t/** Host Global Registers starting at offset 400h.*/\n+\tdwc_otg_host_global_regs_t *host_global_regs;\n+#define DWC_OTG_HOST_GLOBAL_REG_OFFSET 0x400\n+\n+\t/** Host Port 0 Control and Status Register */\n+\tvolatile uint32_t *hprt0;\n+#define DWC_OTG_HOST_PORT_REGS_OFFSET 0x440\n+\n+\t/** Host Channel Specific Registers at offsets 500h-5FCh. */\n+\tdwc_otg_hc_regs_t *hc_regs[MAX_EPS_CHANNELS];\n+#define DWC_OTG_HOST_CHAN_REGS_OFFSET 0x500\n+#define DWC_OTG_CHAN_REGS_OFFSET 0x20\n+\n+\t/* Host configuration information */\n+\t/** Number of Host Channels (range: 1-16) */\n+\tuint8_t num_host_channels;\n+\t/** Periodic EPs supported (0: no, 1: yes) */\n+\tuint8_t perio_eps_supported;\n+\t/** Periodic Tx FIFO Size (Only 1 host periodic Tx FIFO) */\n+\tuint16_t perio_tx_fifo_size;\n+\n+} dwc_otg_host_if_t;\n+\n+/**\n+ * This union represents the bit fields in the Power and Clock Gating Control\n+ * Register. Read the register into the <i>d32</i> member then set/clear the\n+ * bits using the <i>b</i>it elements.\n+ */\n+typedef union pcgcctl_data {\n+\t/** raw register data */\n+\tuint32_t d32;\n+\n+\t/** register bits */\n+\tstruct {\n+\t\t/** Stop Pclk */\n+\t\tunsigned stoppclk:1;\n+\t\t/** Gate Hclk */\n+\t\tunsigned gatehclk:1;\n+\t\t/** Power Clamp */\n+\t\tunsigned pwrclmp:1;\n+\t\t/** Reset Power Down Modules */\n+\t\tunsigned rstpdwnmodule:1;\n+\t\t/** Reserved */\n+\t\tunsigned reserved:1;\n+\t\t/** Enable Sleep Clock Gating (Enbl_L1Gating) */\n+\t\tunsigned enbl_sleep_gating:1;\n+\t\t/** PHY In Sleep (PhySleep) */\n+\t\tunsigned phy_in_sleep:1;\n+\t\t/** Deep Sleep*/\n+\t\tunsigned deep_sleep:1;\n+\t\tunsigned resetaftsusp:1;\n+\t\tunsigned restoremode:1;\n+\t\tunsigned enbl_extnd_hiber:1;\n+\t\tunsigned extnd_hiber_pwrclmp:1;\n+\t\tunsigned extnd_hiber_switch:1;\n+\t\tunsigned ess_reg_restored:1;\n+\t\tunsigned prt_clk_sel:2;\n+\t\tunsigned port_power:1;\n+\t\tunsigned max_xcvrselect:2;\n+\t\tunsigned max_termsel:1;\n+\t\tunsigned mac_dev_addr:7;\n+\t\tunsigned p2hd_dev_enum_spd:2;\n+\t\tunsigned p2hd_prt_spd:2;\n+\t\tunsigned if_dev_mode:1;\n+\t} b;\n+} pcgcctl_data_t;\n+\n+/**\n+ * This union represents the bit fields in the Global Data FIFO Software\n+ * Configuration Register. Read the register into the <i>d32</i> member then\n+ * set/clear the bits using the <i>b</i>it elements.\n+ */\n+typedef union gdfifocfg_data {\n+\t/* raw register data */\n+\tuint32_t d32;\n+\t/** register bits */\n+\tstruct {\n+\t\t/** OTG Data FIFO depth */\n+\t\tunsigned gdfifocfg:16;\n+\t\t/** Start address of EP info controller */\n+\t\tunsigned epinfobase:16;\n+\t} b;\n+} gdfifocfg_data_t;\n+\n+/**\n+ * This union represents the bit fields in the Global Power Down Register\n+ * Register. Read the register into the <i>d32</i> member then set/clear the\n+ * bits using the <i>b</i>it elements.\n+ */\n+typedef union gpwrdn_data {\n+\t/* raw register data */\n+\tuint32_t d32;\n+\n+\t/** register bits */\n+\tstruct {\n+\t\t/** PMU Interrupt Select */\n+\t\tunsigned pmuintsel:1;\n+\t\t/** PMU Active */\n+\t\tunsigned pmuactv:1;\n+\t\t/** Restore */\n+\t\tunsigned restore:1;\n+\t\t/** Power Down Clamp */\n+\t\tunsigned pwrdnclmp:1;\n+\t\t/** Power Down Reset */\n+\t\tunsigned pwrdnrstn:1;\n+\t\t/** Power Down Switch */\n+\t\tunsigned pwrdnswtch:1;\n+\t\t/** Disable VBUS */\n+\t\tunsigned dis_vbus:1;\n+\t\t/** Line State Change */\n+\t\tunsigned lnstschng:1;\n+\t\t/** Line state change mask */\n+\t\tunsigned lnstchng_msk:1;\n+\t\t/** Reset Detected */\n+\t\tunsigned rst_det:1;\n+\t\t/** Reset Detect mask */\n+\t\tunsigned rst_det_msk:1;\n+\t\t/** Disconnect Detected */\n+\t\tunsigned disconn_det:1;\n+\t\t/** Disconnect Detect mask */\n+\t\tunsigned disconn_det_msk:1;\n+\t\t/** Connect Detected*/\n+\t\tunsigned connect_det:1;\n+\t\t/** Connect Detected Mask*/\n+\t\tunsigned connect_det_msk:1;\n+\t\t/** SRP Detected */\n+\t\tunsigned srp_det:1;\n+\t\t/** SRP Detect mask */\n+\t\tunsigned srp_det_msk:1;\n+\t\t/** Status Change Interrupt */\n+\t\tunsigned sts_chngint:1;\n+\t\t/** Status Change Interrupt Mask */\n+\t\tunsigned sts_chngint_msk:1;\n+\t\t/** Line State */\n+\t\tunsigned linestate:2;\n+\t\t/** Indicates current mode(status of IDDIG signal) */\n+\t\tunsigned idsts:1;\n+\t\t/** B Session Valid signal status*/\n+\t\tunsigned bsessvld:1;\n+\t\t/** ADP Event Detected */\n+\t\tunsigned adp_int:1;\n+\t\t/** Multi Valued ID pin */\n+\t\tunsigned mult_val_id_bc:5;\n+\t\t/** Reserved 24_31 */\n+\t\tunsigned reserved29_31:3;\n+\t} b;\n+} gpwrdn_data_t;\n+\n+#endif\n--- /dev/null\n+++ b/drivers/usb/host/dwc_otg/test/Makefile\n@@ -0,0 +1,16 @@\n+\n+PERL=/usr/bin/perl\n+PL_TESTS=test_sysfs.pl test_mod_param.pl\n+\n+.PHONY : test\n+test : perl_tests\n+\n+perl_tests :\n+\t@echo\n+\t@echo Running perl tests\n+\t@for test in $(PL_TESTS); do \\\n+\t  if $(PERL) ./$$test ; then \\\n+\t    echo \"=======> $$test, PASSED\" ; \\\n+\t  else echo \"=======> $$test, FAILED\" ; \\\n+\t  fi \\\n+\tdone\n--- /dev/null\n+++ b/drivers/usb/host/dwc_otg/test/dwc_otg_test.pm\n@@ -0,0 +1,337 @@\n+package dwc_otg_test;\n+\n+use strict;\n+use Exporter ();\n+\n+use vars qw(@ISA @EXPORT\n+$sysfsdir $paramdir $errors $params\n+);\n+\n+@ISA = qw(Exporter);\n+\n+#\n+# Globals\n+#\n+$sysfsdir = \"/sys/devices/lm0\";\n+$paramdir = \"/sys/module/dwc_otg\";\n+$errors = 0;\n+\n+$params = [\n+\t   {\n+\t    NAME => \"otg_cap\",\n+\t    DEFAULT => 0,\n+\t    ENUM => [],\n+\t    LOW => 0,\n+\t    HIGH => 2\n+\t   },\n+\t   {\n+\t    NAME => \"dma_enable\",\n+\t    DEFAULT => 0,\n+\t    ENUM => [],\n+\t    LOW => 0,\n+\t    HIGH => 1\n+\t   },\n+\t   {\n+\t    NAME => \"dma_burst_size\",\n+\t    DEFAULT => 32,\n+\t    ENUM => [1, 4, 8, 16, 32, 64, 128, 256],\n+\t    LOW => 1,\n+\t    HIGH => 256\n+\t   },\n+\t   {\n+\t    NAME => \"host_speed\",\n+\t    DEFAULT => 0,\n+\t    ENUM => [],\n+\t    LOW => 0,\n+\t    HIGH => 1\n+\t   },\n+\t   {\n+\t    NAME => \"host_support_fs_ls_low_power\",\n+\t    DEFAULT => 0,\n+\t    ENUM => [],\n+\t    LOW => 0,\n+\t    HIGH => 1\n+\t   },\n+\t   {\n+\t    NAME => \"host_ls_low_power_phy_clk\",\n+\t    DEFAULT => 0,\n+\t    ENUM => [],\n+\t    LOW => 0,\n+\t    HIGH => 1\n+\t   },\n+\t   {\n+\t    NAME => \"dev_speed\",\n+\t    DEFAULT => 0,\n+\t    ENUM => [],\n+\t    LOW => 0,\n+\t    HIGH => 1\n+\t   },\n+\t   {\n+\t    NAME => \"enable_dynamic_fifo\",\n+\t    DEFAULT => 1,\n+\t    ENUM => [],\n+\t    LOW => 0,\n+\t    HIGH => 1\n+\t   },\n+\t   {\n+\t    NAME => \"data_fifo_size\",\n+\t    DEFAULT => 8192,\n+\t    ENUM => [],\n+\t    LOW => 32,\n+\t    HIGH => 32768\n+\t   },\n+\t   {\n+\t    NAME => \"dev_rx_fifo_size\",\n+\t    DEFAULT => 1064,\n+\t    ENUM => [],\n+\t    LOW => 16,\n+\t    HIGH => 32768\n+\t   },\n+\t   {\n+\t    NAME => \"dev_nperio_tx_fifo_size\",\n+\t    DEFAULT => 1024,\n+\t    ENUM => [],\n+\t    LOW => 16,\n+\t    HIGH => 32768\n+\t   },\n+\t   {\n+\t    NAME => \"dev_perio_tx_fifo_size_1\",\n+\t    DEFAULT => 256,\n+\t    ENUM => [],\n+\t    LOW => 4,\n+\t    HIGH => 768\n+\t   },\n+\t   {\n+\t    NAME => \"dev_perio_tx_fifo_size_2\",\n+\t    DEFAULT => 256,\n+\t    ENUM => [],\n+\t    LOW => 4,\n+\t    HIGH => 768\n+\t   },\n+\t   {\n+\t    NAME => \"dev_perio_tx_fifo_size_3\",\n+\t    DEFAULT => 256,\n+\t    ENUM => [],\n+\t    LOW => 4,\n+\t    HIGH => 768\n+\t   },\n+\t   {\n+\t    NAME => \"dev_perio_tx_fifo_size_4\",\n+\t    DEFAULT => 256,\n+\t    ENUM => [],\n+\t    LOW => 4,\n+\t    HIGH => 768\n+\t   },\n+\t   {\n+\t    NAME => \"dev_perio_tx_fifo_size_5\",\n+\t    DEFAULT => 256,\n+\t    ENUM => [],\n+\t    LOW => 4,\n+\t    HIGH => 768\n+\t   },\n+\t   {\n+\t    NAME => \"dev_perio_tx_fifo_size_6\",\n+\t    DEFAULT => 256,\n+\t    ENUM => [],\n+\t    LOW => 4,\n+\t    HIGH => 768\n+\t   },\n+\t   {\n+\t    NAME => \"dev_perio_tx_fifo_size_7\",\n+\t    DEFAULT => 256,\n+\t    ENUM => [],\n+\t    LOW => 4,\n+\t    HIGH => 768\n+\t   },\n+\t   {\n+\t    NAME => \"dev_perio_tx_fifo_size_8\",\n+\t    DEFAULT => 256,\n+\t    ENUM => [],\n+\t    LOW => 4,\n+\t    HIGH => 768\n+\t   },\n+\t   {\n+\t    NAME => \"dev_perio_tx_fifo_size_9\",\n+\t    DEFAULT => 256,\n+\t    ENUM => [],\n+\t    LOW => 4,\n+\t    HIGH => 768\n+\t   },\n+\t   {\n+\t    NAME => \"dev_perio_tx_fifo_size_10\",\n+\t    DEFAULT => 256,\n+\t    ENUM => [],\n+\t    LOW => 4,\n+\t    HIGH => 768\n+\t   },\n+\t   {\n+\t    NAME => \"dev_perio_tx_fifo_size_11\",\n+\t    DEFAULT => 256,\n+\t    ENUM => [],\n+\t    LOW => 4,\n+\t    HIGH => 768\n+\t   },\n+\t   {\n+\t    NAME => \"dev_perio_tx_fifo_size_12\",\n+\t    DEFAULT => 256,\n+\t    ENUM => [],\n+\t    LOW => 4,\n+\t    HIGH => 768\n+\t   },\n+\t   {\n+\t    NAME => \"dev_perio_tx_fifo_size_13\",\n+\t    DEFAULT => 256,\n+\t    ENUM => [],\n+\t    LOW => 4,\n+\t    HIGH => 768\n+\t   },\n+\t   {\n+\t    NAME => \"dev_perio_tx_fifo_size_14\",\n+\t    DEFAULT => 256,\n+\t    ENUM => [],\n+\t    LOW => 4,\n+\t    HIGH => 768\n+\t   },\n+\t   {\n+\t    NAME => \"dev_perio_tx_fifo_size_15\",\n+\t    DEFAULT => 256,\n+\t    ENUM => [],\n+\t    LOW => 4,\n+\t    HIGH => 768\n+\t   },\n+\t   {\n+\t    NAME => \"host_rx_fifo_size\",\n+\t    DEFAULT => 1024,\n+\t    ENUM => [],\n+\t    LOW => 16,\n+\t    HIGH => 32768\n+\t   },\n+\t   {\n+\t    NAME => \"host_nperio_tx_fifo_size\",\n+\t    DEFAULT => 1024,\n+\t    ENUM => [],\n+\t    LOW => 16,\n+\t    HIGH => 32768\n+\t   },\n+\t   {\n+\t    NAME => \"host_perio_tx_fifo_size\",\n+\t    DEFAULT => 1024,\n+\t    ENUM => [],\n+\t    LOW => 16,\n+\t    HIGH => 32768\n+\t   },\n+\t   {\n+\t    NAME => \"max_transfer_size\",\n+\t    DEFAULT => 65535,\n+\t    ENUM => [],\n+\t    LOW => 2047,\n+\t    HIGH => 65535\n+\t   },\n+\t   {\n+\t    NAME => \"max_packet_count\",\n+\t    DEFAULT => 511,\n+\t    ENUM => [],\n+\t    LOW => 15,\n+\t    HIGH => 511\n+\t   },\n+\t   {\n+\t    NAME => \"host_channels\",\n+\t    DEFAULT => 12,\n+\t    ENUM => [],\n+\t    LOW => 1,\n+\t    HIGH => 16\n+\t   },\n+\t   {\n+\t    NAME => \"dev_endpoints\",\n+\t    DEFAULT => 6,\n+\t    ENUM => [],\n+\t    LOW => 1,\n+\t    HIGH => 15\n+\t   },\n+\t   {\n+\t    NAME => \"phy_type\",\n+\t    DEFAULT => 1,\n+\t    ENUM => [],\n+\t    LOW => 0,\n+\t    HIGH => 2\n+\t   },\n+\t   {\n+\t    NAME => \"phy_utmi_width\",\n+\t    DEFAULT => 16,\n+\t    ENUM => [8, 16],\n+\t    LOW => 8,\n+\t    HIGH => 16\n+\t   },\n+\t   {\n+\t    NAME => \"phy_ulpi_ddr\",\n+\t    DEFAULT => 0,\n+\t    ENUM => [],\n+\t    LOW => 0,\n+\t    HIGH => 1\n+\t   },\n+\t  ];\n+\n+\n+#\n+#\n+sub check_arch {\n+  $_ = `uname -m`;\n+  chomp;\n+  unless (m/armv4tl/) {\n+    warn \"# \\n# Can't execute on $_.  Run on integrator platform.\\n# \\n\";\n+    return 0;\n+  }\n+  return 1;\n+}\n+\n+#\n+#\n+sub load_module {\n+  my $params = shift;\n+  print \"\\nRemoving Module\\n\";\n+  system \"rmmod dwc_otg\";\n+  print \"Loading Module\\n\";\n+  if ($params ne \"\") {\n+    print \"Module Parameters: $params\\n\";\n+  }\n+  if (system(\"modprobe dwc_otg $params\")) {\n+    warn \"Unable to load module\\n\";\n+    return 0;\n+  }\n+  return 1;\n+}\n+\n+#\n+#\n+sub test_status {\n+  my $arg = shift;\n+\n+  print \"\\n\";\n+\n+  if (defined $arg) {\n+    warn \"WARNING: $arg\\n\";\n+  }\n+\n+  if ($errors > 0) {\n+    warn \"TEST FAILED with $errors errors\\n\";\n+    return 0;\n+  } else {\n+    print \"TEST PASSED\\n\";\n+    return 0 if (defined $arg);\n+  }\n+  return 1;\n+}\n+\n+#\n+#\n+@EXPORT = qw(\n+$sysfsdir\n+$paramdir\n+$params\n+$errors\n+check_arch\n+load_module\n+test_status\n+);\n+\n+1;\n--- /dev/null\n+++ b/drivers/usb/host/dwc_otg/test/test_mod_param.pl\n@@ -0,0 +1,133 @@\n+#!/usr/bin/perl -w\n+#\n+# Run this program on the integrator.\n+#\n+# - Tests module parameter default values.\n+# - Tests setting of valid module parameter values via modprobe.\n+# - Tests invalid module parameter values.\n+# -----------------------------------------------------------------------------\n+use strict;\n+use dwc_otg_test;\n+\n+check_arch() or die;\n+\n+#\n+#\n+sub test {\n+  my ($param,$expected) = @_;\n+  my $value = get($param);\n+\n+  if ($value == $expected) {\n+    print \"$param = $value, okay\\n\";\n+  }\n+\n+  else {\n+    warn \"ERROR: value of $param != $expected, $value\\n\";\n+    $errors ++;\n+  }\n+}\n+\n+#\n+#\n+sub get {\n+  my $param = shift;\n+  my $tmp = `cat $paramdir/$param`;\n+  chomp $tmp;\n+  return $tmp;\n+}\n+\n+#\n+#\n+sub test_main {\n+\n+  print \"\\nTesting Module Parameters\\n\";\n+\n+  load_module(\"\") or die;\n+\n+  # Test initial values\n+  print \"\\nTesting Default Values\\n\";\n+  foreach (@{$params}) {\n+    test ($_->{NAME}, $_->{DEFAULT});\n+  }\n+\n+  # Test low value\n+  print \"\\nTesting Low Value\\n\";\n+  my $cmd_params = \"\";\n+  foreach (@{$params}) {\n+    $cmd_params = $cmd_params . \"$_->{NAME}=$_->{LOW} \";\n+  }\n+  load_module($cmd_params) or die;\n+\n+  foreach (@{$params}) {\n+    test ($_->{NAME}, $_->{LOW});\n+  }\n+\n+  # Test high value\n+  print \"\\nTesting High Value\\n\";\n+  $cmd_params = \"\";\n+  foreach (@{$params}) {\n+    $cmd_params = $cmd_params . \"$_->{NAME}=$_->{HIGH} \";\n+  }\n+  load_module($cmd_params) or die;\n+\n+  foreach (@{$params}) {\n+    test ($_->{NAME}, $_->{HIGH});\n+  }\n+\n+  # Test Enum\n+  print \"\\nTesting Enumerated\\n\";\n+  foreach (@{$params}) {\n+    if (defined $_->{ENUM}) {\n+      my $value;\n+      foreach $value (@{$_->{ENUM}}) {\n+\t$cmd_params = \"$_->{NAME}=$value\";\n+\tload_module($cmd_params) or die;\n+\ttest ($_->{NAME}, $value);\n+      }\n+    }\n+  }\n+\n+  # Test Invalid Values\n+  print \"\\nTesting Invalid Values\\n\";\n+  $cmd_params = \"\";\n+  foreach (@{$params}) {\n+    $cmd_params = $cmd_params . sprintf \"$_->{NAME}=%d \", $_->{LOW}-1;\n+  }\n+  load_module($cmd_params) or die;\n+\n+  foreach (@{$params}) {\n+    test ($_->{NAME}, $_->{DEFAULT});\n+  }\n+\n+  $cmd_params = \"\";\n+  foreach (@{$params}) {\n+    $cmd_params = $cmd_params . sprintf \"$_->{NAME}=%d \", $_->{HIGH}+1;\n+  }\n+  load_module($cmd_params) or die;\n+\n+  foreach (@{$params}) {\n+    test ($_->{NAME}, $_->{DEFAULT});\n+  }\n+\n+  print \"\\nTesting Enumerated\\n\";\n+  foreach (@{$params}) {\n+    if (defined $_->{ENUM}) {\n+      my $value;\n+      foreach $value (@{$_->{ENUM}}) {\n+\t$value = $value + 1;\n+\t$cmd_params = \"$_->{NAME}=$value\";\n+\tload_module($cmd_params) or die;\n+\ttest ($_->{NAME}, $_->{DEFAULT});\n+\t$value = $value - 2;\n+\t$cmd_params = \"$_->{NAME}=$value\";\n+\tload_module($cmd_params) or die;\n+\ttest ($_->{NAME}, $_->{DEFAULT});\n+      }\n+    }\n+  }\n+\n+  test_status() or die;\n+}\n+\n+test_main();\n+0;\n--- /dev/null\n+++ b/drivers/usb/host/dwc_otg/test/test_sysfs.pl\n@@ -0,0 +1,193 @@\n+#!/usr/bin/perl -w\n+#\n+# Run this program on the integrator\n+# - Tests select sysfs attributes.\n+# - Todo ... test more attributes, hnp/srp, buspower/bussuspend, etc.\n+# -----------------------------------------------------------------------------\n+use strict;\n+use dwc_otg_test;\n+\n+check_arch() or die;\n+\n+#\n+#\n+sub test {\n+  my ($attr,$expected) = @_;\n+  my $string = get($attr);\n+\n+  if ($string eq $expected) {\n+    printf(\"$attr = $string, okay\\n\");\n+  }\n+  else {\n+    warn \"ERROR: value of $attr != $expected, $string\\n\";\n+    $errors ++;\n+  }\n+}\n+\n+#\n+#\n+sub set {\n+  my ($reg, $value) = @_;\n+  system \"echo $value > $sysfsdir/$reg\";\n+}\n+\n+#\n+#\n+sub get {\n+  my $attr = shift;\n+  my $string = `cat $sysfsdir/$attr`;\n+  chomp $string;\n+  if ($string =~ m/\\s\\=\\s/) {\n+    my $tmp;\n+    ($tmp, $string) = split /\\s=\\s/, $string;\n+  }\n+  return $string;\n+}\n+\n+#\n+#\n+sub test_main {\n+  print(\"\\nTesting Sysfs Attributes\\n\");\n+\n+  load_module(\"\") or die;\n+\n+  # Test initial values of regoffset/regvalue/guid/gsnpsid\n+  print(\"\\nTesting Default Values\\n\");\n+\n+  test(\"regoffset\", \"0xffffffff\");\n+  test(\"regvalue\", \"invalid offset\");\n+  test(\"guid\", \"0x12345678\");\t# this will fail if it has been changed\n+  test(\"gsnpsid\", \"0x4f54200a\");\n+\n+  # Test operation of regoffset/regvalue\n+  print(\"\\nTesting regoffset\\n\");\n+  set('regoffset', '5a5a5a5a');\n+  test(\"regoffset\", \"0xffffffff\");\n+\n+  set('regoffset', '0');\n+  test(\"regoffset\", \"0x00000000\");\n+\n+  set('regoffset', '40000');\n+  test(\"regoffset\", \"0x00000000\");\n+\n+  set('regoffset', '3ffff');\n+  test(\"regoffset\", \"0x0003ffff\");\n+\n+  set('regoffset', '1');\n+  test(\"regoffset\", \"0x00000001\");\n+\n+  print(\"\\nTesting regvalue\\n\");\n+  set('regoffset', '3c');\n+  test(\"regvalue\", \"0x12345678\");\n+  set('regvalue', '5a5a5a5a');\n+  test(\"regvalue\", \"0x5a5a5a5a\");\n+  set('regvalue','a5a5a5a5');\n+  test(\"regvalue\", \"0xa5a5a5a5\");\n+  set('guid','12345678');\n+\n+  # Test HNP Capable\n+  print(\"\\nTesting HNP Capable bit\\n\");\n+  set('hnpcapable', '1');\n+  test(\"hnpcapable\", \"0x1\");\n+  set('hnpcapable','0');\n+  test(\"hnpcapable\", \"0x0\");\n+\n+  set('regoffset','0c');\n+\n+  my $old = get('gusbcfg');\n+  print(\"setting hnpcapable\\n\");\n+  set('hnpcapable', '1');\n+  test(\"hnpcapable\", \"0x1\");\n+  test('gusbcfg', sprintf \"0x%08x\", (oct ($old) | (1<<9)));\n+  test('regvalue', sprintf \"0x%08x\", (oct ($old) | (1<<9)));\n+\n+  $old = get('gusbcfg');\n+  print(\"clearing hnpcapable\\n\");\n+  set('hnpcapable', '0');\n+  test(\"hnpcapable\", \"0x0\");\n+  test ('gusbcfg', sprintf \"0x%08x\", oct ($old) & (~(1<<9)));\n+  test ('regvalue', sprintf \"0x%08x\", oct ($old) & (~(1<<9)));\n+\n+  # Test SRP Capable\n+  print(\"\\nTesting SRP Capable bit\\n\");\n+  set('srpcapable', '1');\n+  test(\"srpcapable\", \"0x1\");\n+  set('srpcapable','0');\n+  test(\"srpcapable\", \"0x0\");\n+\n+  set('regoffset','0c');\n+\n+  $old = get('gusbcfg');\n+  print(\"setting srpcapable\\n\");\n+  set('srpcapable', '1');\n+  test(\"srpcapable\", \"0x1\");\n+  test('gusbcfg', sprintf \"0x%08x\", (oct ($old) | (1<<8)));\n+  test('regvalue', sprintf \"0x%08x\", (oct ($old) | (1<<8)));\n+\n+  $old = get('gusbcfg');\n+  print(\"clearing srpcapable\\n\");\n+  set('srpcapable', '0');\n+  test(\"srpcapable\", \"0x0\");\n+  test('gusbcfg', sprintf \"0x%08x\", oct ($old) & (~(1<<8)));\n+  test('regvalue', sprintf \"0x%08x\", oct ($old) & (~(1<<8)));\n+\n+  # Test GGPIO\n+  print(\"\\nTesting GGPIO\\n\");\n+  set('ggpio','5a5a5a5a');\n+  test('ggpio','0x5a5a0000');\n+  set('ggpio','a5a5a5a5');\n+  test('ggpio','0xa5a50000');\n+  set('ggpio','11110000');\n+  test('ggpio','0x11110000');\n+  set('ggpio','00001111');\n+  test('ggpio','0x00000000');\n+\n+  # Test DEVSPEED\n+  print(\"\\nTesting DEVSPEED\\n\");\n+  set('regoffset','800');\n+  $old = get('regvalue');\n+  set('devspeed','0');\n+  test('devspeed','0x0');\n+  test('regvalue',sprintf(\"0x%08x\", oct($old) & ~(0x3)));\n+  set('devspeed','1');\n+  test('devspeed','0x1');\n+  test('regvalue',sprintf(\"0x%08x\", oct($old) & ~(0x3) | 1));\n+  set('devspeed','2');\n+  test('devspeed','0x2');\n+  test('regvalue',sprintf(\"0x%08x\", oct($old) & ~(0x3) | 2));\n+  set('devspeed','3');\n+  test('devspeed','0x3');\n+  test('regvalue',sprintf(\"0x%08x\", oct($old) & ~(0x3) | 3));\n+  set('devspeed','4');\n+  test('devspeed','0x0');\n+  test('regvalue',sprintf(\"0x%08x\", oct($old) & ~(0x3)));\n+  set('devspeed','5');\n+  test('devspeed','0x1');\n+  test('regvalue',sprintf(\"0x%08x\", oct($old) & ~(0x3) | 1));\n+\n+\n+  #  mode\tReturns the current mode:0 for device mode1 for host mode\tRead\n+  #  hnp\tInitiate the Host Negotiation Protocol.  Read returns the status.\tRead/Write\n+  #  srp\tInitiate the Session Request Protocol.  Read returns the status.\tRead/Write\n+  #  buspower\tGet or Set the Power State of the bus (0 - Off or 1 - On) \tRead/Write\n+  #  bussuspend\tSuspend the USB bus.\tRead/Write\n+  #  busconnected\tGet the connection status of the bus \tRead\n+\n+  #  gotgctl\tGet or set the Core Control Status Register.\tRead/Write\n+  ##  gusbcfg\tGet or set the Core USB Configuration Register\tRead/Write\n+  #  grxfsiz\tGet or set the Receive FIFO Size Register\tRead/Write\n+  #  gnptxfsiz\tGet or set the non-periodic Transmit Size Register\tRead/Write\n+  #  gpvndctl\tGet or set the PHY Vendor Control Register\tRead/Write\n+  ##  ggpio\tGet the value in the lower 16-bits of the General Purpose IO Register or Set the upper 16 bits.\tRead/Write\n+  ##  guid\tGet or set the value of the User ID Register\tRead/Write\n+  ##  gsnpsid\tGet the value of the Synopsys ID Regester\tRead\n+  ##  devspeed\tGet or set the device speed setting in the DCFG register\tRead/Write\n+  #  enumspeed\tGets the device enumeration Speed.\tRead\n+  #  hptxfsiz\tGet the value of the Host Periodic Transmit FIFO\tRead\n+  #  hprt0\tGet or Set the value in the Host Port Control and Status Register\tRead/Write\n+\n+  test_status(\"TEST NYI\") or die;\n+}\n+\n+test_main();\n+0;\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0041-bcm2708-framebuffer-driver.patch",
    "content": "From 96f18d88062c3fe5754ab031fb5bde7686f6a510 Mon Sep 17 00:00:00 2001\nFrom: popcornmix <popcornmix@gmail.com>\nDate: Wed, 17 Jun 2015 17:06:34 +0100\nSubject: [PATCH] bcm2708 framebuffer driver\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nSigned-off-by: popcornmix <popcornmix@gmail.com>\n\nbcm2708_fb : Implement blanking support using the mailbox property interface\n\nbcm2708_fb: Add pan and vsync controls\n\nbcm2708_fb: DMA acceleration for fb_copyarea\n\nBased on http://www.raspberrypi.org/phpBB3/viewtopic.php?p=62425#p62425\nAlso used Simon's dmaer_master module as a reference for tweaking DMA\nsettings for better performance.\n\nFor now busylooping only. IRQ support might be added later.\nWith non-overclocked Raspberry Pi, the performance is ~360 MB/s\nfor simple copy or ~260 MB/s for two-pass copy (used when dragging\nwindows to the right).\n\nIn the case of using DMA channel 0, the performance improves\nto ~440 MB/s.\n\nFor comparison, VFP optimized CPU copy can only do ~114 MB/s in\nthe same conditions (hindered by reading uncached source buffer).\n\nSigned-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>\n\nbcm2708_fb: report number of dma copies\n\nAdd a counter (exported via debugfs) reporting the\nnumber of dma copies that the framebuffer driver\nhas done, in order to help evaluate different\noptimization strategies.\n\nSigned-off-by: Luke Diamand <luked@broadcom.com>\n\nbcm2708_fb: use IRQ for DMA copies\n\nThe copyarea ioctl() uses DMA to speed things along. This\nwas busy-waiting for completion. This change supports using\nan interrupt instead for larger transfers. For small\ntransfers, busy-waiting is still likely to be faster.\n\nSigned-off-by: Luke Diamand <luke@diamand.org>\n\nbcm2708: Make ioctl logging quieter\n\nvideo: fbdev: bcm2708_fb: Don't panic on error\n\nNo need to panic the kernel if the video driver fails.\nJust print a message and return an error.\n\nSigned-off-by: Noralf Trønnes <noralf@tronnes.org>\n\nfbdev: bcm2708_fb: Add ARCH_BCM2835 support\n\nAdd Device Tree support.\nPass the device to dma_alloc_coherent() in order to get the\ncorrect bus address on ARCH_BCM2835.\nUse the new DMA legacy API header file.\nIncluding <mach/platform.h> is not necessary.\n\nSigned-off-by: Noralf Trønnes <noralf@tronnes.org>\n\nBCM270x_DT: Add bcm2708-fb device\n\nAdd bcm2708-fb to Device Tree and don't add the\nplatform device when booting in DT mode.\n\nSigned-off-by: Noralf Trønnes <noralf@tronnes.org>\n\nCleanup of bcm2708_fb file to kernel coding standards\n\nSome minor change to function - remove a use of\nin_atomic, plus replacing various debug messages\nthat manually specify the function name with\n(\"%s\",.__func__)\n\nSigned-off-by: James Hughes <james.hughes@raspberrypi.org>\n\nvideo: bcm2708_fb: Try allocating on the ARM and passing to VPU\n\nCurrently the VPU allocates the contiguous buffer for the\nframebuffer.\nTry an alternate path first where we use dma_alloc_coherent\nand pass the buffer to the VPU. Should the VPU firmware not\nsupport that path, then free the buffer and revert to the\nold behaviour of using the VPU allocation.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>\n---\n drivers/video/fbdev/Kconfig                |   14 +\n drivers/video/fbdev/Makefile               |    1 +\n drivers/video/fbdev/bcm2708_fb.c           |  920 ++++++++\n drivers/video/logo/logo_linux_clut224.ppm  | 2483 +++++++-------------\n include/soc/bcm2835/raspberrypi-firmware.h |    1 +\n 5 files changed, 1817 insertions(+), 1602 deletions(-)\n create mode 100644 drivers/video/fbdev/bcm2708_fb.c\n\n--- a/drivers/video/fbdev/Kconfig\n+++ b/drivers/video/fbdev/Kconfig\n@@ -219,6 +219,20 @@ config FB_TILEBLITTING\n comment \"Frame buffer hardware drivers\"\n \tdepends on FB\n \n+config FB_BCM2708\n+\ttristate \"BCM2708 framebuffer support\"\n+\tdepends on FB && RASPBERRYPI_FIRMWARE\n+\tselect FB_CFB_FILLRECT\n+\tselect FB_CFB_COPYAREA\n+\tselect FB_CFB_IMAGEBLIT\n+\thelp\n+\t  This framebuffer device driver is for the BCM2708 framebuffer.\n+\n+\t  If you want to compile this as a module (=code which can be\n+\t  inserted into and removed from the running kernel), say M\n+\t  here and read <file:Documentation/kbuild/modules.txt>.  The module\n+\t  will be called bcm2708_fb.\n+\n config FB_GRVGA\n \ttristate \"Aeroflex Gaisler framebuffer support\"\n \tdepends on FB && SPARC\n--- a/drivers/video/fbdev/Makefile\n+++ b/drivers/video/fbdev/Makefile\n@@ -11,6 +11,7 @@ obj-$(CONFIG_FB_MACMODES)      += macmod\n obj-$(CONFIG_FB_WMT_GE_ROPS)   += wmt_ge_rops.o\n \n # Hardware specific drivers go first\n+obj-$(CONFIG_FB_BCM2708)\t  += bcm2708_fb.o\n obj-$(CONFIG_FB_AMIGA)            += amifb.o c2p_planar.o\n obj-$(CONFIG_FB_ARC)              += arcfb.o\n obj-$(CONFIG_FB_CLPS711X)\t  += clps711x-fb.o\n--- /dev/null\n+++ b/drivers/video/fbdev/bcm2708_fb.c\n@@ -0,0 +1,920 @@\n+/*\n+ *  linux/drivers/video/bcm2708_fb.c\n+ *\n+ * Copyright (C) 2010 Broadcom\n+ *\n+ * This file is subject to the terms and conditions of the GNU General Public\n+ * License.  See the file COPYING in the main directory of this archive\n+ * for more details.\n+ *\n+ * Broadcom simple framebuffer driver\n+ *\n+ * This file is derived from cirrusfb.c\n+ * Copyright 1999-2001 Jeff Garzik <jgarzik@pobox.com>\n+ *\n+ */\n+#include <linux/module.h>\n+#include <linux/kernel.h>\n+#include <linux/errno.h>\n+#include <linux/string.h>\n+#include <linux/slab.h>\n+#include <linux/mm.h>\n+#include <linux/fb.h>\n+#include <linux/init.h>\n+#include <linux/interrupt.h>\n+#include <linux/ioport.h>\n+#include <linux/list.h>\n+#include <linux/platform_data/dma-bcm2708.h>\n+#include <linux/platform_device.h>\n+#include <linux/clk.h>\n+#include <linux/printk.h>\n+#include <linux/console.h>\n+#include <linux/debugfs.h>\n+#include <linux/io.h>\n+#include <linux/dma-mapping.h>\n+#include <soc/bcm2835/raspberrypi-firmware.h>\n+\n+//#define BCM2708_FB_DEBUG\n+#define MODULE_NAME \"bcm2708_fb\"\n+\n+#ifdef BCM2708_FB_DEBUG\n+#define print_debug(fmt, ...) pr_debug(\"%s:%s:%d: \" fmt, \\\n+\t\t\tMODULE_NAME, __func__, __LINE__, ##__VA_ARGS__)\n+#else\n+#define print_debug(fmt, ...)\n+#endif\n+\n+/* This is limited to 16 characters when displayed by X startup */\n+static const char *bcm2708_name = \"BCM2708 FB\";\n+\n+#define DRIVER_NAME \"bcm2708_fb\"\n+\n+static int fbwidth = 800;\t/* module parameter */\n+static int fbheight = 480;\t/* module parameter */\n+static int fbdepth = 32;\t/* module parameter */\n+static int fbswap;\t\t/* module parameter */\n+\n+static u32 dma_busy_wait_threshold = 1 << 15;\n+module_param(dma_busy_wait_threshold, int, 0644);\n+MODULE_PARM_DESC(dma_busy_wait_threshold, \"Busy-wait for DMA completion below this area\");\n+\n+struct fb_alloc_tags {\n+\tstruct rpi_firmware_property_tag_header tag1;\n+\tu32 xres, yres;\n+\tstruct rpi_firmware_property_tag_header tag2;\n+\tu32 xres_virtual, yres_virtual;\n+\tstruct rpi_firmware_property_tag_header tag3;\n+\tu32 bpp;\n+\tstruct rpi_firmware_property_tag_header tag4;\n+\tu32 xoffset, yoffset;\n+\tstruct rpi_firmware_property_tag_header tag5;\n+\tu32 base, screen_size;\n+\tstruct rpi_firmware_property_tag_header tag6;\n+\tu32 pitch;\n+};\n+\n+struct bcm2708_fb_stats {\n+\tstruct debugfs_regset32 regset;\n+\tu32 dma_copies;\n+\tu32 dma_irqs;\n+};\n+\n+struct bcm2708_fb {\n+\tstruct fb_info fb;\n+\tstruct platform_device *dev;\n+\tstruct rpi_firmware *fw;\n+\tu32 cmap[16];\n+\tu32 gpu_cmap[256];\n+\tint dma_chan;\n+\tint dma_irq;\n+\tvoid __iomem *dma_chan_base;\n+\tvoid *cb_base;\t\t/* DMA control blocks */\n+\tdma_addr_t cb_handle;\n+\tstruct dentry *debugfs_dir;\n+\twait_queue_head_t dma_waitq;\n+\tstruct bcm2708_fb_stats stats;\n+\tunsigned long fb_bus_address;\n+\tbool disable_arm_alloc;\n+\tunsigned int image_size;\n+\tdma_addr_t dma_addr;\n+\tvoid *cpuaddr;\n+};\n+\n+#define to_bcm2708(info)\tcontainer_of(info, struct bcm2708_fb, fb)\n+\n+static void bcm2708_fb_debugfs_deinit(struct bcm2708_fb *fb)\n+{\n+\tdebugfs_remove_recursive(fb->debugfs_dir);\n+\tfb->debugfs_dir = NULL;\n+}\n+\n+static int bcm2708_fb_debugfs_init(struct bcm2708_fb *fb)\n+{\n+\tstatic struct debugfs_reg32 stats_registers[] = {\n+\t\t{\n+\t\t\t\"dma_copies\",\n+\t\t\toffsetof(struct bcm2708_fb_stats, dma_copies)\n+\t\t},\n+\t\t{\n+\t\t\t\"dma_irqs\",\n+\t\t\toffsetof(struct bcm2708_fb_stats, dma_irqs)\n+\t\t},\n+\t};\n+\n+\tfb->debugfs_dir = debugfs_create_dir(DRIVER_NAME, NULL);\n+\tif (!fb->debugfs_dir) {\n+\t\tpr_warn(\"%s: could not create debugfs entry\\n\",\n+\t\t\t__func__);\n+\t\treturn -EFAULT;\n+\t}\n+\n+\tfb->stats.regset.regs = stats_registers;\n+\tfb->stats.regset.nregs = ARRAY_SIZE(stats_registers);\n+\tfb->stats.regset.base = &fb->stats;\n+\n+\tdebugfs_create_regset32(\"stats\", 0444, fb->debugfs_dir,\n+\t\t\t\t&fb->stats.regset);\n+\treturn 0;\n+}\n+\n+static int bcm2708_fb_set_bitfields(struct fb_var_screeninfo *var)\n+{\n+\tint ret = 0;\n+\n+\tmemset(&var->transp, 0, sizeof(var->transp));\n+\n+\tvar->red.msb_right = 0;\n+\tvar->green.msb_right = 0;\n+\tvar->blue.msb_right = 0;\n+\n+\tswitch (var->bits_per_pixel) {\n+\tcase 1:\n+\tcase 2:\n+\tcase 4:\n+\tcase 8:\n+\t\tvar->red.length = var->bits_per_pixel;\n+\t\tvar->red.offset = 0;\n+\t\tvar->green.length = var->bits_per_pixel;\n+\t\tvar->green.offset = 0;\n+\t\tvar->blue.length = var->bits_per_pixel;\n+\t\tvar->blue.offset = 0;\n+\t\tbreak;\n+\tcase 16:\n+\t\tvar->red.length = 5;\n+\t\tvar->blue.length = 5;\n+\t\t/*\n+\t\t * Green length can be 5 or 6 depending whether\n+\t\t * we're operating in RGB555 or RGB565 mode.\n+\t\t */\n+\t\tif (var->green.length != 5 && var->green.length != 6)\n+\t\t\tvar->green.length = 6;\n+\t\tbreak;\n+\tcase 24:\n+\t\tvar->red.length = 8;\n+\t\tvar->blue.length = 8;\n+\t\tvar->green.length = 8;\n+\t\tbreak;\n+\tcase 32:\n+\t\tvar->red.length = 8;\n+\t\tvar->green.length = 8;\n+\t\tvar->blue.length = 8;\n+\t\tvar->transp.length = 8;\n+\t\tbreak;\n+\tdefault:\n+\t\tret = -EINVAL;\n+\t\tbreak;\n+\t}\n+\n+\t/*\n+\t * >= 16bpp displays have separate colour component bitfields\n+\t * encoded in the pixel data.  Calculate their position from\n+\t * the bitfield length defined above.\n+\t */\n+\tif (ret == 0 && var->bits_per_pixel >= 24 && fbswap) {\n+\t\tvar->blue.offset = 0;\n+\t\tvar->green.offset = var->blue.offset + var->blue.length;\n+\t\tvar->red.offset = var->green.offset + var->green.length;\n+\t\tvar->transp.offset = var->red.offset + var->red.length;\n+\t} else if (ret == 0 && var->bits_per_pixel >= 24) {\n+\t\tvar->red.offset = 0;\n+\t\tvar->green.offset = var->red.offset + var->red.length;\n+\t\tvar->blue.offset = var->green.offset + var->green.length;\n+\t\tvar->transp.offset = var->blue.offset + var->blue.length;\n+\t} else if (ret == 0 && var->bits_per_pixel >= 16) {\n+\t\tvar->blue.offset = 0;\n+\t\tvar->green.offset = var->blue.offset + var->blue.length;\n+\t\tvar->red.offset = var->green.offset + var->green.length;\n+\t\tvar->transp.offset = var->red.offset + var->red.length;\n+\t}\n+\n+\treturn ret;\n+}\n+\n+static int bcm2708_fb_check_var(struct fb_var_screeninfo *var,\n+\t\t\t\tstruct fb_info *info)\n+{\n+\t/* info input, var output */\n+\tprint_debug(\"%s(%p) %dx%d (%dx%d), %d, %d\\n\",\n+\t\t    __func__, info, info->var.xres, info->var.yres,\n+\t\t    info->var.xres_virtual, info->var.yres_virtual,\n+\t\t    (int)info->screen_size, info->var.bits_per_pixel);\n+\tprint_debug(\"%s(%p) %dx%d (%dx%d), %d\\n\", __func__, var, var->xres,\n+\t\t    var->yres, var->xres_virtual, var->yres_virtual,\n+\t\t    var->bits_per_pixel);\n+\n+\tif (!var->bits_per_pixel)\n+\t\tvar->bits_per_pixel = 16;\n+\n+\tif (bcm2708_fb_set_bitfields(var) != 0) {\n+\t\tpr_err(\"%s: invalid bits_per_pixel %d\\n\", __func__,\n+\t\t       var->bits_per_pixel);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (var->xres_virtual < var->xres)\n+\t\tvar->xres_virtual = var->xres;\n+\t/* use highest possible virtual resolution */\n+\tif (var->yres_virtual == -1) {\n+\t\tvar->yres_virtual = 480;\n+\n+\t\tpr_err(\"%s: virtual resolution set to maximum of %dx%d\\n\",\n+\t\t       __func__, var->xres_virtual, var->yres_virtual);\n+\t}\n+\tif (var->yres_virtual < var->yres)\n+\t\tvar->yres_virtual = var->yres;\n+\n+\tif (var->xoffset < 0)\n+\t\tvar->xoffset = 0;\n+\tif (var->yoffset < 0)\n+\t\tvar->yoffset = 0;\n+\n+\t/* truncate xoffset and yoffset to maximum if too high */\n+\tif (var->xoffset > var->xres_virtual - var->xres)\n+\t\tvar->xoffset = var->xres_virtual - var->xres - 1;\n+\tif (var->yoffset > var->yres_virtual - var->yres)\n+\t\tvar->yoffset = var->yres_virtual - var->yres - 1;\n+\n+\treturn 0;\n+}\n+\n+static int bcm2708_fb_set_par(struct fb_info *info)\n+{\n+\tstruct bcm2708_fb *fb = to_bcm2708(info);\n+\tstruct fb_alloc_tags fbinfo = {\n+\t\t.tag1 = { RPI_FIRMWARE_FRAMEBUFFER_SET_PHYSICAL_WIDTH_HEIGHT,\n+\t\t\t  8, 0, },\n+\t\t\t.xres = info->var.xres,\n+\t\t\t.yres = info->var.yres,\n+\t\t.tag2 = { RPI_FIRMWARE_FRAMEBUFFER_SET_VIRTUAL_WIDTH_HEIGHT,\n+\t\t\t  8, 0, },\n+\t\t\t.xres_virtual = info->var.xres_virtual,\n+\t\t\t.yres_virtual = info->var.yres_virtual,\n+\t\t.tag3 = { RPI_FIRMWARE_FRAMEBUFFER_SET_DEPTH, 4, 0 },\n+\t\t\t.bpp = info->var.bits_per_pixel,\n+\t\t.tag4 = { RPI_FIRMWARE_FRAMEBUFFER_SET_VIRTUAL_OFFSET, 8, 0 },\n+\t\t\t.xoffset = info->var.xoffset,\n+\t\t\t.yoffset = info->var.yoffset,\n+\t\t.tag5 = { RPI_FIRMWARE_FRAMEBUFFER_ALLOCATE, 8, 0 },\n+\t\t\t/* base and screen_size will be initialised later */\n+\t\t.tag6 = { RPI_FIRMWARE_FRAMEBUFFER_SET_PITCH, 4, 0 },\n+\t\t\t/* pitch will be initialised later */\n+\t};\n+\tint ret, image_size;\n+\n+\n+\tprint_debug(\"%s(%p) %dx%d (%dx%d), %d, %d\\n\", __func__, info,\n+\t\t    info->var.xres, info->var.yres, info->var.xres_virtual,\n+\t\t    info->var.yres_virtual, (int)info->screen_size,\n+\t\t    info->var.bits_per_pixel);\n+\n+\t/* Try allocating our own buffer. We can specify all the parameters */\n+\timage_size = ((info->var.xres * info->var.yres) *\n+\t\t      info->var.bits_per_pixel) >> 3;\n+\n+\tif (!fb->disable_arm_alloc &&\n+\t    (image_size != fb->image_size || !fb->dma_addr)) {\n+\t\tif (fb->dma_addr) {\n+\t\t\tdma_free_coherent(info->device, fb->image_size,\n+\t\t\t\t\t  fb->cpuaddr, fb->dma_addr);\n+\t\t\tfb->image_size = 0;\n+\t\t\tfb->cpuaddr = NULL;\n+\t\t\tfb->dma_addr = 0;\n+\t\t}\n+\n+\t\tfb->cpuaddr = dma_alloc_coherent(info->device, image_size,\n+\t\t\t\t\t\t &fb->dma_addr, GFP_KERNEL);\n+\n+\t\tif (!fb->cpuaddr) {\n+\t\t\tfb->dma_addr = 0;\n+\t\t\tfb->disable_arm_alloc = true;\n+\t\t} else {\n+\t\t\tfb->image_size = image_size;\n+\t\t}\n+\t}\n+\n+\tif (fb->cpuaddr) {\n+\t\tfbinfo.base = fb->dma_addr;\n+\t\tfbinfo.screen_size = image_size;\n+\t\tfbinfo.pitch = (info->var.xres * info->var.bits_per_pixel) >> 3;\n+\n+\t\tret = rpi_firmware_property_list(fb->fw, &fbinfo,\n+\t\t\t\t\t\t sizeof(fbinfo));\n+\t\tif (ret || fbinfo.base != fb->dma_addr) {\n+\t\t\t/* Firmware either failed, or assigned a different base\n+\t\t\t * address (ie it doesn't support being passed an FB\n+\t\t\t * allocation).\n+\t\t\t * Destroy the allocation, and don't try again.\n+\t\t\t */\n+\t\t\tdma_free_coherent(info->device, fb->image_size,\n+\t\t\t\t\t  fb->cpuaddr, fb->dma_addr);\n+\t\t\tfb->image_size = 0;\n+\t\t\tfb->cpuaddr = NULL;\n+\t\t\tfb->dma_addr = 0;\n+\t\t\tfb->disable_arm_alloc = true;\n+\t\t}\n+\t} else {\n+\t\t/* Our allocation failed - drop into the old scheme of\n+\t\t * allocation by the VPU.\n+\t\t */\n+\t\tret = -ENOMEM;\n+\t}\n+\n+\tif (ret) {\n+\t\t/* Old scheme:\n+\t\t * - FRAMEBUFFER_ALLOCATE passes 0 for base and screen_size.\n+\t\t * - GET_PITCH instead of SET_PITCH.\n+\t\t */\n+\t\tfbinfo.base = 0;\n+\t\tfbinfo.screen_size = 0;\n+\t\tfbinfo.tag6.tag = RPI_FIRMWARE_FRAMEBUFFER_GET_PITCH;\n+\t\tfbinfo.pitch = 0;\n+\n+\t\tret = rpi_firmware_property_list(fb->fw, &fbinfo,\n+\t\t\t\t\t\t sizeof(fbinfo));\n+\t\tif (ret) {\n+\t\t\tdev_err(info->device,\n+\t\t\t\t\"Failed to allocate GPU framebuffer (%d)\\n\",\n+\t\t\t\tret);\n+\t\t\treturn ret;\n+\t\t}\n+\t}\n+\n+\tif (info->var.bits_per_pixel <= 8)\n+\t\tfb->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR;\n+\telse\n+\t\tfb->fb.fix.visual = FB_VISUAL_TRUECOLOR;\n+\n+\tfb->fb.fix.line_length = fbinfo.pitch;\n+\tfbinfo.base |= 0x40000000;\n+\tfb->fb_bus_address = fbinfo.base;\n+\tfbinfo.base &= ~0xc0000000;\n+\tfb->fb.fix.smem_start = fbinfo.base;\n+\tfb->fb.fix.smem_len = fbinfo.pitch * fbinfo.yres_virtual;\n+\tfb->fb.screen_size = fbinfo.screen_size;\n+\n+\tif (!fb->dma_addr) {\n+\t\tif (fb->fb.screen_base)\n+\t\t\tiounmap(fb->fb.screen_base);\n+\n+\t\tfb->fb.screen_base = ioremap_wc(fbinfo.base,\n+\t\t\t\t\t\tfb->fb.screen_size);\n+\t} else {\n+\t\tfb->fb.screen_base = fb->cpuaddr;\n+\t}\n+\n+\tif (!fb->fb.screen_base) {\n+\t\t/* the console may currently be locked */\n+\t\tconsole_trylock();\n+\t\tconsole_unlock();\n+\t\tdev_err(info->device, \"Failed to set screen_base\\n\");\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\tprint_debug(\"%s: start = %p,%p width=%d, height=%d, bpp=%d, pitch=%d size=%d\\n\",\n+\t\t    __func__, (void *)fb->fb.screen_base,\n+\t\t    (void *)fb->fb_bus_address, fbinfo.xres, fbinfo.yres,\n+\t\t    fbinfo.bpp, fbinfo.pitch, (int)fb->fb.screen_size);\n+\n+\treturn 0;\n+}\n+\n+static inline u32 convert_bitfield(int val, struct fb_bitfield *bf)\n+{\n+\tunsigned int mask = (1 << bf->length) - 1;\n+\n+\treturn (val >> (16 - bf->length) & mask) << bf->offset;\n+}\n+\n+static int bcm2708_fb_setcolreg(unsigned int regno, unsigned int red,\n+\t\t\t\tunsigned int green, unsigned int blue,\n+\t\t\t\tunsigned int transp, struct fb_info *info)\n+{\n+\tstruct bcm2708_fb *fb = to_bcm2708(info);\n+\n+\tif (fb->fb.var.bits_per_pixel <= 8) {\n+\t\tif (regno < 256) {\n+\t\t\t/* blue [23:16], green [15:8], red [7:0] */\n+\t\t\tfb->gpu_cmap[regno] = ((red   >> 8) & 0xff) << 0 |\n+\t\t\t\t\t      ((green >> 8) & 0xff) << 8 |\n+\t\t\t\t\t      ((blue  >> 8) & 0xff) << 16;\n+\t\t}\n+\t\t/* Hack: we need to tell GPU the palette has changed, but\n+\t\t * currently bcm2708_fb_set_par takes noticeable time when\n+\t\t * called for every (256) colour\n+\t\t * So just call it for what looks like the last colour in a\n+\t\t * list for now.\n+\t\t */\n+\t\tif (regno == 15 || regno == 255) {\n+\t\t\tstruct packet {\n+\t\t\t\tu32 offset;\n+\t\t\t\tu32 length;\n+\t\t\t\tu32 cmap[256];\n+\t\t\t} *packet;\n+\t\t\tint ret;\n+\n+\t\t\tpacket = kmalloc(sizeof(*packet), GFP_KERNEL);\n+\t\t\tif (!packet)\n+\t\t\t\treturn -ENOMEM;\n+\t\t\tpacket->offset = 0;\n+\t\t\tpacket->length = regno + 1;\n+\t\t\tmemcpy(packet->cmap, fb->gpu_cmap,\n+\t\t\t       sizeof(packet->cmap));\n+\t\t\tret = rpi_firmware_property(fb->fw,\n+\t\t\t\t\t\t    RPI_FIRMWARE_FRAMEBUFFER_SET_PALETTE,\n+\t\t\t\t\t\t    packet,\n+\t\t\t\t\t\t    (2 + packet->length) * sizeof(u32));\n+\t\t\tif (ret || packet->offset)\n+\t\t\t\tdev_err(info->device,\n+\t\t\t\t\t\"Failed to set palette (%d,%u)\\n\",\n+\t\t\t\t\tret, packet->offset);\n+\t\t\tkfree(packet);\n+\t\t}\n+\t} else if (regno < 16) {\n+\t\tfb->cmap[regno] = convert_bitfield(transp, &fb->fb.var.transp) |\n+\t\t\t\t  convert_bitfield(blue, &fb->fb.var.blue) |\n+\t\t\t\t  convert_bitfield(green, &fb->fb.var.green) |\n+\t\t\t\t  convert_bitfield(red, &fb->fb.var.red);\n+\t}\n+\treturn regno > 255;\n+}\n+\n+static int bcm2708_fb_blank(int blank_mode, struct fb_info *info)\n+{\n+\tstruct bcm2708_fb *fb = to_bcm2708(info);\n+\tu32 value;\n+\tint ret;\n+\n+\tswitch (blank_mode) {\n+\tcase FB_BLANK_UNBLANK:\n+\t\tvalue = 0;\n+\t\tbreak;\n+\tcase FB_BLANK_NORMAL:\n+\tcase FB_BLANK_VSYNC_SUSPEND:\n+\tcase FB_BLANK_HSYNC_SUSPEND:\n+\tcase FB_BLANK_POWERDOWN:\n+\t\tvalue = 1;\n+\t\tbreak;\n+\tdefault:\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tret = rpi_firmware_property(fb->fw, RPI_FIRMWARE_FRAMEBUFFER_BLANK,\n+\t\t\t\t    &value, sizeof(value));\n+\tif (ret)\n+\t\tdev_err(info->device, \"%s(%d) failed: %d\\n\", __func__,\n+\t\t\tblank_mode, ret);\n+\n+\treturn ret;\n+}\n+\n+static int bcm2708_fb_pan_display(struct fb_var_screeninfo *var,\n+\t\t\t\t  struct fb_info *info)\n+{\n+\ts32 result;\n+\n+\tinfo->var.xoffset = var->xoffset;\n+\tinfo->var.yoffset = var->yoffset;\n+\tresult = bcm2708_fb_set_par(info);\n+\tif (result != 0)\n+\t\tpr_err(\"%s(%d,%d) returns=%d\\n\", __func__, var->xoffset,\n+\t\t       var->yoffset, result);\n+\treturn result;\n+}\n+\n+static int bcm2708_ioctl(struct fb_info *info, unsigned int cmd, unsigned long arg)\n+{\n+\tstruct bcm2708_fb *fb = to_bcm2708(info);\n+\tu32 dummy = 0;\n+\tint ret;\n+\n+\tswitch (cmd) {\n+\tcase FBIO_WAITFORVSYNC:\n+\t\tret = rpi_firmware_property(fb->fw,\n+\t\t\t\t\t    RPI_FIRMWARE_FRAMEBUFFER_SET_VSYNC,\n+\t\t\t\t\t    &dummy, sizeof(dummy));\n+\t\tbreak;\n+\tdefault:\n+\t\tdev_dbg(info->device, \"Unknown ioctl 0x%x\\n\", cmd);\n+\t\treturn -ENOTTY;\n+\t}\n+\n+\tif (ret)\n+\t\tdev_err(info->device, \"ioctl 0x%x failed (%d)\\n\", cmd, ret);\n+\n+\treturn ret;\n+}\n+static void bcm2708_fb_fillrect(struct fb_info *info,\n+\t\t\t\tconst struct fb_fillrect *rect)\n+{\n+\t/* (is called) print_debug(\"bcm2708_fb_fillrect\\n\"); */\n+\tcfb_fillrect(info, rect);\n+}\n+\n+/* A helper function for configuring dma control block */\n+static void set_dma_cb(struct bcm2708_dma_cb *cb,\n+\t\t       int        burst_size,\n+\t\t       dma_addr_t dst,\n+\t\t       int        dst_stride,\n+\t\t       dma_addr_t src,\n+\t\t       int        src_stride,\n+\t\t       int        w,\n+\t\t       int        h)\n+{\n+\tcb->info = BCM2708_DMA_BURST(burst_size) | BCM2708_DMA_S_WIDTH |\n+\t\t   BCM2708_DMA_S_INC | BCM2708_DMA_D_WIDTH |\n+\t\t   BCM2708_DMA_D_INC | BCM2708_DMA_TDMODE;\n+\tcb->dst = dst;\n+\tcb->src = src;\n+\t/*\n+\t * This is not really obvious from the DMA documentation,\n+\t * but the top 16 bits must be programmmed to \"height -1\"\n+\t * and not \"height\" in 2D mode.\n+\t */\n+\tcb->length = ((h - 1) << 16) | w;\n+\tcb->stride = ((dst_stride - w) << 16) | (u16)(src_stride - w);\n+\tcb->pad[0] = 0;\n+\tcb->pad[1] = 0;\n+}\n+\n+static void bcm2708_fb_copyarea(struct fb_info *info,\n+\t\t\t\tconst struct fb_copyarea *region)\n+{\n+\tstruct bcm2708_fb *fb = to_bcm2708(info);\n+\tstruct bcm2708_dma_cb *cb = fb->cb_base;\n+\tint bytes_per_pixel = (info->var.bits_per_pixel + 7) >> 3;\n+\n+\t/* Channel 0 supports larger bursts and is a bit faster */\n+\tint burst_size = (fb->dma_chan == 0) ? 8 : 2;\n+\tint pixels = region->width * region->height;\n+\n+\t/* Fallback to cfb_copyarea() if we don't like something */\n+\tif (bytes_per_pixel > 4 ||\n+\t    info->var.xres * info->var.yres > 1920 * 1200 ||\n+\t    region->width <= 0 || region->width > info->var.xres ||\n+\t    region->height <= 0 || region->height > info->var.yres ||\n+\t    region->sx < 0 || region->sx >= info->var.xres ||\n+\t    region->sy < 0 || region->sy >= info->var.yres ||\n+\t    region->dx < 0 || region->dx >= info->var.xres ||\n+\t    region->dy < 0 || region->dy >= info->var.yres ||\n+\t    region->sx + region->width > info->var.xres ||\n+\t    region->dx + region->width > info->var.xres ||\n+\t    region->sy + region->height > info->var.yres ||\n+\t    region->dy + region->height > info->var.yres) {\n+\t\tcfb_copyarea(info, region);\n+\t\treturn;\n+\t}\n+\n+\tif (region->dy == region->sy && region->dx > region->sx) {\n+\t\t/*\n+\t\t * A difficult case of overlapped copy. Because DMA can't\n+\t\t * copy individual scanlines in backwards direction, we need\n+\t\t * two-pass processing. We do it by programming a chain of dma\n+\t\t * control blocks in the first 16K part of the buffer and use\n+\t\t * the remaining 48K as the intermediate temporary scratch\n+\t\t * buffer. The buffer size is sufficient to handle up to\n+\t\t * 1920x1200 resolution at 32bpp pixel depth.\n+\t\t */\n+\t\tint y;\n+\t\tdma_addr_t control_block_pa = fb->cb_handle;\n+\t\tdma_addr_t scratchbuf = fb->cb_handle + 16 * 1024;\n+\t\tint scanline_size = bytes_per_pixel * region->width;\n+\t\tint scanlines_per_cb = (64 * 1024 - 16 * 1024) / scanline_size;\n+\n+\t\tfor (y = 0; y < region->height; y += scanlines_per_cb) {\n+\t\t\tdma_addr_t src =\n+\t\t\t\tfb->fb_bus_address +\n+\t\t\t\tbytes_per_pixel * region->sx +\n+\t\t\t\t(region->sy + y) * fb->fb.fix.line_length;\n+\t\t\tdma_addr_t dst =\n+\t\t\t\tfb->fb_bus_address +\n+\t\t\t\tbytes_per_pixel * region->dx +\n+\t\t\t\t(region->dy + y) * fb->fb.fix.line_length;\n+\n+\t\t\tif (region->height - y < scanlines_per_cb)\n+\t\t\t\tscanlines_per_cb = region->height - y;\n+\n+\t\t\tset_dma_cb(cb, burst_size, scratchbuf, scanline_size,\n+\t\t\t\t   src, fb->fb.fix.line_length,\n+\t\t\t\t   scanline_size, scanlines_per_cb);\n+\t\t\tcontrol_block_pa += sizeof(struct bcm2708_dma_cb);\n+\t\t\tcb->next = control_block_pa;\n+\t\t\tcb++;\n+\n+\t\t\tset_dma_cb(cb, burst_size, dst, fb->fb.fix.line_length,\n+\t\t\t\t   scratchbuf, scanline_size,\n+\t\t\t\t   scanline_size, scanlines_per_cb);\n+\t\t\tcontrol_block_pa += sizeof(struct bcm2708_dma_cb);\n+\t\t\tcb->next = control_block_pa;\n+\t\t\tcb++;\n+\t\t}\n+\t\t/* move the pointer back to the last dma control block */\n+\t\tcb--;\n+\t} else {\n+\t\t/* A single dma control block is enough. */\n+\t\tint sy, dy, stride;\n+\n+\t\tif (region->dy <= region->sy) {\n+\t\t\t/* processing from top to bottom */\n+\t\t\tdy = region->dy;\n+\t\t\tsy = region->sy;\n+\t\t\tstride = fb->fb.fix.line_length;\n+\t\t} else {\n+\t\t\t/* processing from bottom to top */\n+\t\t\tdy = region->dy + region->height - 1;\n+\t\t\tsy = region->sy + region->height - 1;\n+\t\t\tstride = -fb->fb.fix.line_length;\n+\t\t}\n+\t\tset_dma_cb(cb, burst_size,\n+\t\t\t   fb->fb_bus_address + dy * fb->fb.fix.line_length +\n+\t\t\t\t\t\t   bytes_per_pixel * region->dx,\n+\t\t\t   stride,\n+\t\t\t   fb->fb_bus_address + sy * fb->fb.fix.line_length +\n+\t\t\t\t\t\t   bytes_per_pixel * region->sx,\n+\t\t\t   stride,\n+\t\t\t   region->width * bytes_per_pixel,\n+\t\t\t   region->height);\n+\t}\n+\n+\t/* end of dma control blocks chain */\n+\tcb->next = 0;\n+\n+\tif (pixels < dma_busy_wait_threshold) {\n+\t\tbcm_dma_start(fb->dma_chan_base, fb->cb_handle);\n+\t\tbcm_dma_wait_idle(fb->dma_chan_base);\n+\t} else {\n+\t\tvoid __iomem *dma_chan = fb->dma_chan_base;\n+\n+\t\tcb->info |= BCM2708_DMA_INT_EN;\n+\t\tbcm_dma_start(fb->dma_chan_base, fb->cb_handle);\n+\t\twhile (bcm_dma_is_busy(dma_chan)) {\n+\t\t\twait_event_interruptible(fb->dma_waitq,\n+\t\t\t\t\t\t !bcm_dma_is_busy(dma_chan));\n+\t\t}\n+\t\tfb->stats.dma_irqs++;\n+\t}\n+\tfb->stats.dma_copies++;\n+}\n+\n+static void bcm2708_fb_imageblit(struct fb_info *info,\n+\t\t\t\t const struct fb_image *image)\n+{\n+\t/* (is called) print_debug(\"bcm2708_fb_imageblit\\n\"); */\n+\tcfb_imageblit(info, image);\n+}\n+\n+static irqreturn_t bcm2708_fb_dma_irq(int irq, void *cxt)\n+{\n+\tstruct bcm2708_fb *fb = cxt;\n+\n+\t/* FIXME: should read status register to check if this is\n+\t * actually interrupting us or not, in case this interrupt\n+\t * ever becomes shared amongst several DMA channels\n+\t *\n+\t * readl(dma_chan_base + BCM2708_DMA_CS) & BCM2708_DMA_IRQ;\n+\t */\n+\n+\t/* acknowledge the interrupt */\n+\twritel(BCM2708_DMA_INT, fb->dma_chan_base + BCM2708_DMA_CS);\n+\n+\twake_up(&fb->dma_waitq);\n+\treturn IRQ_HANDLED;\n+}\n+\n+static struct fb_ops bcm2708_fb_ops = {\n+\t.owner = THIS_MODULE,\n+\t.fb_check_var = bcm2708_fb_check_var,\n+\t.fb_set_par = bcm2708_fb_set_par,\n+\t.fb_setcolreg = bcm2708_fb_setcolreg,\n+\t.fb_blank = bcm2708_fb_blank,\n+\t.fb_fillrect = bcm2708_fb_fillrect,\n+\t.fb_copyarea = bcm2708_fb_copyarea,\n+\t.fb_imageblit = bcm2708_fb_imageblit,\n+\t.fb_pan_display = bcm2708_fb_pan_display,\n+\t.fb_ioctl = bcm2708_ioctl,\n+};\n+\n+static int bcm2708_fb_register(struct bcm2708_fb *fb)\n+{\n+\tint ret;\n+\n+\tfb->fb.fbops = &bcm2708_fb_ops;\n+\tfb->fb.flags = FBINFO_FLAG_DEFAULT | FBINFO_HWACCEL_COPYAREA;\n+\tfb->fb.pseudo_palette = fb->cmap;\n+\n+\tstrncpy(fb->fb.fix.id, bcm2708_name, sizeof(fb->fb.fix.id));\n+\tfb->fb.fix.type = FB_TYPE_PACKED_PIXELS;\n+\tfb->fb.fix.type_aux = 0;\n+\tfb->fb.fix.xpanstep = 1;\n+\tfb->fb.fix.ypanstep = 1;\n+\tfb->fb.fix.ywrapstep = 0;\n+\tfb->fb.fix.accel = FB_ACCEL_NONE;\n+\n+\tfb->fb.var.xres = fbwidth;\n+\tfb->fb.var.yres = fbheight;\n+\tfb->fb.var.xres_virtual = fbwidth;\n+\tfb->fb.var.yres_virtual = fbheight;\n+\tfb->fb.var.bits_per_pixel = fbdepth;\n+\tfb->fb.var.vmode = FB_VMODE_NONINTERLACED;\n+\tfb->fb.var.activate = FB_ACTIVATE_NOW;\n+\tfb->fb.var.nonstd = 0;\n+\tfb->fb.var.height = -1;\t\t/* height of picture in mm    */\n+\tfb->fb.var.width = -1;\t\t/* width of picture in mm    */\n+\tfb->fb.var.accel_flags = 0;\n+\n+\tfb->fb.monspecs.hfmin = 0;\n+\tfb->fb.monspecs.hfmax = 100000;\n+\tfb->fb.monspecs.vfmin = 0;\n+\tfb->fb.monspecs.vfmax = 400;\n+\tfb->fb.monspecs.dclkmin = 1000000;\n+\tfb->fb.monspecs.dclkmax = 100000000;\n+\n+\tbcm2708_fb_set_bitfields(&fb->fb.var);\n+\tinit_waitqueue_head(&fb->dma_waitq);\n+\n+\t/*\n+\t * Allocate colourmap.\n+\t */\n+\n+\tfb_set_var(&fb->fb, &fb->fb.var);\n+\tret = bcm2708_fb_set_par(&fb->fb);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tprint_debug(\"BCM2708FB: registering framebuffer (%dx%d@%d) (%d)\\n\",\n+\t\t    fbwidth, fbheight, fbdepth, fbswap);\n+\n+\tret = register_framebuffer(&fb->fb);\n+\tprint_debug(\"BCM2708FB: register framebuffer (%d)\\n\", ret);\n+\tif (ret == 0)\n+\t\tgoto out;\n+\n+\tprint_debug(\"BCM2708FB: cannot register framebuffer (%d)\\n\", ret);\n+out:\n+\treturn ret;\n+}\n+\n+static int bcm2708_fb_probe(struct platform_device *dev)\n+{\n+\tstruct device_node *fw_np;\n+\tstruct rpi_firmware *fw;\n+\tstruct bcm2708_fb *fb;\n+\tint ret;\n+\n+\tfw_np = of_parse_phandle(dev->dev.of_node, \"firmware\", 0);\n+/* Remove comment when booting without Device Tree is no longer supported\n+ *\tif (!fw_np) {\n+ *\t\tdev_err(&dev->dev, \"Missing firmware node\\n\");\n+ *\t\treturn -ENOENT;\n+ *\t}\n+ */\n+\tfw = rpi_firmware_get(fw_np);\n+\tif (!fw)\n+\t\treturn -EPROBE_DEFER;\n+\n+\tfb = kzalloc(sizeof(*fb), GFP_KERNEL);\n+\tif (!fb) {\n+\t\tret = -ENOMEM;\n+\t\tgoto free_region;\n+\t}\n+\n+\tfb->fw = fw;\n+\tbcm2708_fb_debugfs_init(fb);\n+\n+\tfb->cb_base = dma_alloc_wc(&dev->dev, SZ_64K,\n+\t\t\t\t\t     &fb->cb_handle, GFP_KERNEL);\n+\tif (!fb->cb_base) {\n+\t\tdev_err(&dev->dev, \"cannot allocate DMA CBs\\n\");\n+\t\tret = -ENOMEM;\n+\t\tgoto free_fb;\n+\t}\n+\n+\tpr_info(\"BCM2708FB: allocated DMA memory %pad\\n\", &fb->cb_handle);\n+\n+\tret = bcm_dma_chan_alloc(BCM_DMA_FEATURE_BULK,\n+\t\t\t\t &fb->dma_chan_base, &fb->dma_irq);\n+\tif (ret < 0) {\n+\t\tdev_err(&dev->dev, \"couldn't allocate a DMA channel\\n\");\n+\t\tgoto free_cb;\n+\t}\n+\tfb->dma_chan = ret;\n+\n+\tret = request_irq(fb->dma_irq, bcm2708_fb_dma_irq,\n+\t\t\t  0, \"bcm2708_fb dma\", fb);\n+\tif (ret) {\n+\t\tpr_err(\"%s: failed to request DMA irq\\n\", __func__);\n+\t\tgoto free_dma_chan;\n+\t}\n+\n+\tpr_info(\"BCM2708FB: allocated DMA channel %d\\n\", fb->dma_chan);\n+\n+\tfb->dev = dev;\n+\tfb->fb.device = &dev->dev;\n+\n+\t/* failure here isn't fatal, but we'll fail in vc_mem_copy if\n+\t * fb->gpu is not valid\n+\t */\n+\trpi_firmware_property(fb->fw, RPI_FIRMWARE_GET_VC_MEMORY, &fb->gpu,\n+\t\t\t      sizeof(fb->gpu));\n+\n+\tret = bcm2708_fb_register(fb);\n+\tif (ret == 0) {\n+\t\tplatform_set_drvdata(dev, fb);\n+\t\tgoto out;\n+\t}\n+\n+free_dma_chan:\n+\tbcm_dma_chan_free(fb->dma_chan);\n+free_cb:\n+\tdma_free_wc(&dev->dev, SZ_64K, fb->cb_base, fb->cb_handle);\n+free_fb:\n+\tkfree(fb);\n+free_region:\n+\tdev_err(&dev->dev, \"probe failed, err %d\\n\", ret);\n+out:\n+\treturn ret;\n+}\n+\n+static int bcm2708_fb_remove(struct platform_device *dev)\n+{\n+\tstruct bcm2708_fb *fb = platform_get_drvdata(dev);\n+\n+\tplatform_set_drvdata(dev, NULL);\n+\n+\tif (fb->fb.screen_base)\n+\t\tiounmap(fb->fb.screen_base);\n+\tunregister_framebuffer(&fb->fb);\n+\n+\tdma_free_wc(&dev->dev, SZ_64K, fb->cb_base, fb->cb_handle);\n+\tbcm_dma_chan_free(fb->dma_chan);\n+\n+\tbcm2708_fb_debugfs_deinit(fb);\n+\n+\tfree_irq(fb->dma_irq, fb);\n+\n+\tkfree(fb);\n+\n+\treturn 0;\n+}\n+\n+static const struct of_device_id bcm2708_fb_of_match_table[] = {\n+\t{ .compatible = \"brcm,bcm2708-fb\", },\n+\t{},\n+};\n+MODULE_DEVICE_TABLE(of, bcm2708_fb_of_match_table);\n+\n+static struct platform_driver bcm2708_fb_driver = {\n+\t.probe = bcm2708_fb_probe,\n+\t.remove = bcm2708_fb_remove,\n+\t.driver = {\n+\t\t   .name = DRIVER_NAME,\n+\t\t   .owner = THIS_MODULE,\n+\t\t   .of_match_table = bcm2708_fb_of_match_table,\n+\t\t   },\n+};\n+\n+static int __init bcm2708_fb_init(void)\n+{\n+\treturn platform_driver_register(&bcm2708_fb_driver);\n+}\n+\n+module_init(bcm2708_fb_init);\n+\n+static void __exit bcm2708_fb_exit(void)\n+{\n+\tplatform_driver_unregister(&bcm2708_fb_driver);\n+}\n+\n+module_exit(bcm2708_fb_exit);\n+\n+module_param(fbwidth, int, 0644);\n+module_param(fbheight, int, 0644);\n+module_param(fbdepth, int, 0644);\n+module_param(fbswap, int, 0644);\n+\n+MODULE_DESCRIPTION(\"BCM2708 framebuffer driver\");\n+MODULE_LICENSE(\"GPL\");\n+\n+MODULE_PARM_DESC(fbwidth, \"Width of ARM Framebuffer\");\n+MODULE_PARM_DESC(fbheight, \"Height of ARM Framebuffer\");\n+MODULE_PARM_DESC(fbdepth, \"Bit depth of ARM Framebuffer\");\n+MODULE_PARM_DESC(fbswap, \"Swap order of red and blue in 24 and 32 bit modes\");\n--- a/drivers/video/logo/logo_linux_clut224.ppm\n+++ b/drivers/video/logo/logo_linux_clut224.ppm\n@@ -1,1604 +1,883 @@\n P3\n-# Standard 224-color Linux logo\n-80 80\n+63 80\n 255\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0  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0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0  14  14  14\n- 34  34  34  66  66  66  78  78  78   6   6   6\n-  2   2   6  18  18  18 218 218 218 253 253 253\n-253 253 253 253 253 253 253 253 253 246 246 246\n-226 226 226 231 231 231 246 246 246 253 253 253\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 178 178 178   2   2   6   2   2   6\n-  2   2   6   2   2   6   2   2   6   2   2   6\n-  2   2   6  18  18  18  90  90  90  62  62  62\n- 30  30  30  10  10  10   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0  10  10  10  26  26  26\n- 58  58  58  90  90  90  18  18  18   2   2   6\n-  2   2   6 110 110 110 253 253 253 253 253 253\n-253 253 253 253 253 253 253 253 253 253 253 253\n-250 250 250 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 231 231 231  18  18  18   2   2   6\n-  2   2   6   2   2   6   2   2   6   2   2   6\n-  2   2   6   2   2   6  18  18  18  94  94  94\n- 54  54  54  26  26  26  10  10  10   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   6   6   6  22  22  22  50  50  50\n- 90  90  90  26  26  26   2   2   6   2   2   6\n- 14  14  14 195 195 195 250 250 250 253 253 253\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 253 253 253 253 253 253\n-250 250 250 242 242 242  54  54  54   2   2   6\n-  2   2   6   2   2   6   2   2   6   2   2   6\n-  2   2   6   2   2   6   2   2   6  38  38  38\n- 86  86  86  50  50  50  22  22  22   6   6   6\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  6   6   6  14  14  14  38  38  38  82  82  82\n- 34  34  34   2   2   6   2   2   6   2   2   6\n- 42  42  42 195 195 195 246 246 246 253 253 253\n-253 253 253 253 253 253 253 253 253 250 250 250\n-242 242 242 242 242 242 250 250 250 253 253 253\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 250 250 250 246 246 246 238 238 238\n-226 226 226 231 231 231 101 101 101   6   6   6\n-  2   2   6   2   2   6   2   2   6   2   2   6\n-  2   2   6   2   2   6   2   2   6   2   2   6\n- 38  38  38  82  82  82  42  42  42  14  14  14\n-  6   6   6   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n- 10  10  10  26  26  26  62  62  62  66  66  66\n-  2   2   6   2   2   6   2   2   6   6   6   6\n- 70  70  70 170 170 170 206 206 206 234 234 234\n-246 246 246 250 250 250 250 250 250 238 238 238\n-226 226 226 231 231 231 238 238 238 250 250 250\n-250 250 250 250 250 250 246 246 246 231 231 231\n-214 214 214 206 206 206 202 202 202 202 202 202\n-198 198 198 202 202 202 182 182 182  18  18  18\n-  2   2   6   2   2   6   2   2   6   2   2   6\n-  2   2   6   2   2   6   2   2   6   2   2   6\n-  2   2   6  62  62  62  66  66  66  30  30  30\n- 10  10  10   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n- 14  14  14  42  42  42  82  82  82  18  18  18\n-  2   2   6   2   2   6   2   2   6  10  10  10\n- 94  94  94 182 182 182 218 218 218 242 242 242\n-250 250 250 253 253 253 253 253 253 250 250 250\n-234 234 234 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 253 253 253 246 246 246\n-238 238 238 226 226 226 210 210 210 202 202 202\n-195 195 195 195 195 195 210 210 210 158 158 158\n-  6   6   6  14  14  14  50  50  50  14  14  14\n-  2   2   6   2   2   6   2   2   6   2   2   6\n-  2   2   6   6   6   6  86  86  86  46  46  46\n- 18  18  18   6   6   6   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   6   6   6\n- 22  22  22  54  54  54  70  70  70   2   2   6\n-  2   2   6  10  10  10   2   2   6  22  22  22\n-166 166 166 231 231 231 250 250 250 253 253 253\n-253 253 253 253 253 253 253 253 253 250 250 250\n-242 242 242 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 253 253 253 246 246 246\n-231 231 231 206 206 206 198 198 198 226 226 226\n- 94  94  94   2   2   6   6   6   6  38  38  38\n- 30  30  30   2   2   6   2   2   6   2   2   6\n-  2   2   6   2   2   6  62  62  62  66  66  66\n- 26  26  26  10  10  10   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0  10  10  10\n- 30  30  30  74  74  74  50  50  50   2   2   6\n- 26  26  26  26  26  26   2   2   6 106 106 106\n-238 238 238 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 246 246 246 218 218 218 202 202 202\n-210 210 210  14  14  14   2   2   6   2   2   6\n- 30  30  30  22  22  22   2   2   6   2   2   6\n-  2   2   6   2   2   6  18  18  18  86  86  86\n- 42  42  42  14  14  14   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0  14  14  14\n- 42  42  42  90  90  90  22  22  22   2   2   6\n- 42  42  42   2   2   6  18  18  18 218 218 218\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 250 250 250 221 221 221\n-218 218 218 101 101 101   2   2   6  14  14  14\n- 18  18  18  38  38  38  10  10  10   2   2   6\n-  2   2   6   2   2   6   2   2   6  78  78  78\n- 58  58  58  22  22  22   6   6   6   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   6   6   6  18  18  18\n- 54  54  54  82  82  82   2   2   6  26  26  26\n- 22  22  22   2   2   6 123 123 123 253 253 253\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 253 253 253 250 250 250\n-238 238 238 198 198 198   6   6   6  38  38  38\n- 58  58  58  26  26  26  38  38  38   2   2   6\n-  2   2   6   2   2   6   2   2   6  46  46  46\n- 78  78  78  30  30  30  10  10  10   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0  10  10  10  30  30  30\n- 74  74  74  58  58  58   2   2   6  42  42  42\n-  2   2   6  22  22  22 231 231 231 253 253 253\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 253 253 253 250 250 250\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 246 246 246  46  46  46  38  38  38\n- 42  42  42  14  14  14  38  38  38  14  14  14\n-  2   2   6   2   2   6   2   2   6   6   6   6\n- 86  86  86  46  46  46  14  14  14   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   6   6   6  14  14  14  42  42  42\n- 90  90  90  18  18  18  18  18  18  26  26  26\n-  2   2   6 116 116 116 253 253 253 253 253 253\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 250 250 250 238 238 238\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253  94  94  94   6   6   6\n-  2   2   6   2   2   6  10  10  10  34  34  34\n-  2   2   6   2   2   6   2   2   6   2   2   6\n- 74  74  74  58  58  58  22  22  22   6   6   6\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0  10  10  10  26  26  26  66  66  66\n- 82  82  82   2   2   6  38  38  38   6   6   6\n- 14  14  14 210 210 210 253 253 253 253 253 253\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 246 246 246 242 242 242\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 144 144 144   2   2   6\n-  2   2   6   2   2   6   2   2   6  46  46  46\n-  2   2   6   2   2   6   2   2   6   2   2   6\n- 42  42  42  74  74  74  30  30  30  10  10  10\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  6   6   6  14  14  14  42  42  42  90  90  90\n- 26  26  26   6   6   6  42  42  42   2   2   6\n- 74  74  74 250 250 250 253 253 253 253 253 253\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 242 242 242 242 242 242\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 182 182 182   2   2   6\n-  2   2   6   2   2   6   2   2   6  46  46  46\n-  2   2   6   2   2   6   2   2   6   2   2   6\n- 10  10  10  86  86  86  38  38  38  10  10  10\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n- 10  10  10  26  26  26  66  66  66  82  82  82\n-  2   2   6  22  22  22  18  18  18   2   2   6\n-149 149 149 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 234 234 234 242 242 242\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 206 206 206   2   2   6\n-  2   2   6   2   2   6   2   2   6  38  38  38\n-  2   2   6   2   2   6   2   2   6   2   2   6\n-  6   6   6  86  86  86  46  46  46  14  14  14\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   6   6   6\n- 18  18  18  46  46  46  86  86  86  18  18  18\n-  2   2   6  34  34  34  10  10  10   6   6   6\n-210 210 210 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 234 234 234 242 242 242\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 221 221 221   6   6   6\n-  2   2   6   2   2   6   6   6   6  30  30  30\n-  2   2   6   2   2   6   2   2   6   2   2   6\n-  2   2   6  82  82  82  54  54  54  18  18  18\n-  6   6   6   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0  10  10  10\n- 26  26  26  66  66  66  62  62  62   2   2   6\n-  2   2   6  38  38  38  10  10  10  26  26  26\n-238 238 238 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 231 231 231 238 238 238\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 231 231 231   6   6   6\n-  2   2   6   2   2   6  10  10  10  30  30  30\n-  2   2   6   2   2   6   2   2   6   2   2   6\n-  2   2   6  66  66  66  58  58  58  22  22  22\n-  6   6   6   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0  10  10  10\n- 38  38  38  78  78  78   6   6   6   2   2   6\n-  2   2   6  46  46  46  14  14  14  42  42  42\n-246 246 246 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 231 231 231 242 242 242\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 234 234 234  10  10  10\n-  2   2   6   2   2   6  22  22  22  14  14  14\n-  2   2   6   2   2   6   2   2   6   2   2   6\n-  2   2   6  66  66  66  62  62  62  22  22  22\n-  6   6   6   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   6   6   6  18  18  18\n- 50  50  50  74  74  74   2   2   6   2   2   6\n- 14  14  14  70  70  70  34  34  34  62  62  62\n-250 250 250 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 231 231 231 246 246 246\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 234 234 234  14  14  14\n-  2   2   6   2   2   6  30  30  30   2   2   6\n-  2   2   6   2   2   6   2   2   6   2   2   6\n-  2   2   6  66  66  66  62  62  62  22  22  22\n-  6   6   6   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   6   6   6  18  18  18\n- 54  54  54  62  62  62   2   2   6   2   2   6\n-  2   2   6  30  30  30  46  46  46  70  70  70\n-250 250 250 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 231 231 231 246 246 246\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 226 226 226  10  10  10\n-  2   2   6   6   6   6  30  30  30   2   2   6\n-  2   2   6   2   2   6   2   2   6   2   2   6\n-  2   2   6  66  66  66  58  58  58  22  22  22\n-  6   6   6   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   6   6   6  22  22  22\n- 58  58  58  62  62  62   2   2   6   2   2   6\n-  2   2   6   2   2   6  30  30  30  78  78  78\n-250 250 250 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 231 231 231 246 246 246\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 206 206 206   2   2   6\n- 22  22  22  34  34  34  18  14   6  22  22  22\n- 26  26  26  18  18  18   6   6   6   2   2   6\n-  2   2   6  82  82  82  54  54  54  18  18  18\n-  6   6   6   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   6   6   6  26  26  26\n- 62  62  62 106 106 106  74  54  14 185 133  11\n-210 162  10 121  92   8   6   6   6  62  62  62\n-238 238 238 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 231 231 231 246 246 246\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 158 158 158  18  18  18\n- 14  14  14   2   2   6   2   2   6   2   2   6\n-  6   6   6  18  18  18  66  66  66  38  38  38\n-  6   6   6  94  94  94  50  50  50  18  18  18\n-  6   6   6   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   6   6   6\n- 10  10  10  10  10  10  18  18  18  38  38  38\n- 78  78  78 142 134 106 216 158  10 242 186  14\n-246 190  14 246 190  14 156 118  10  10  10  10\n- 90  90  90 238 238 238 253 253 253 253 253 253\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 231 231 231 250 250 250\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 253 253 253 246 230 190\n-238 204  91 238 204  91 181 142  44  37  26   9\n-  2   2   6   2   2   6   2   2   6   2   2   6\n-  2   2   6   2   2   6  38  38  38  46  46  46\n- 26  26  26 106 106 106  54  54  54  18  18  18\n-  6   6   6   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   6   6   6  14  14  14  22  22  22\n- 30  30  30  38  38  38  50  50  50  70  70  70\n-106 106 106 190 142  34 226 170  11 242 186  14\n-246 190  14 246 190  14 246 190  14 154 114  10\n-  6   6   6  74  74  74 226 226 226 253 253 253\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 231 231 231 250 250 250\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 253 253 253 228 184  62\n-241 196  14 241 208  19 232 195  16  38  30  10\n-  2   2   6   2   2   6   2   2   6   2   2   6\n-  2   2   6   6   6   6  30  30  30  26  26  26\n-203 166  17 154 142  90  66  66  66  26  26  26\n-  6   6   6   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  6   6   6  18  18  18  38  38  38  58  58  58\n- 78  78  78  86  86  86 101 101 101 123 123 123\n-175 146  61 210 150  10 234 174  13 246 186  14\n-246 190  14 246 190  14 246 190  14 238 190  10\n-102  78  10   2   2   6  46  46  46 198 198 198\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 234 234 234 242 242 242\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 253 253 253 224 178  62\n-242 186  14 241 196  14 210 166  10  22  18   6\n-  2   2   6   2   2   6   2   2   6   2   2   6\n-  2   2   6   2   2   6   6   6   6 121  92   8\n-238 202  15 232 195  16  82  82  82  34  34  34\n- 10  10  10   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n- 14  14  14  38  38  38  70  70  70 154 122  46\n-190 142  34 200 144  11 197 138  11 197 138  11\n-213 154  11 226 170  11 242 186  14 246 190  14\n-246 190  14 246 190  14 246 190  14 246 190  14\n-225 175  15  46  32   6   2   2   6  22  22  22\n-158 158 158 250 250 250 253 253 253 253 253 253\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 250 250 250 242 242 242 224 178  62\n-239 182  13 236 186  11 213 154  11  46  32   6\n-  2   2   6   2   2   6   2   2   6   2   2   6\n-  2   2   6   2   2   6  61  42   6 225 175  15\n-238 190  10 236 186  11 112 100  78  42  42  42\n- 14  14  14   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   6   6   6\n- 22  22  22  54  54  54 154 122  46 213 154  11\n-226 170  11 230 174  11 226 170  11 226 170  11\n-236 178  12 242 186  14 246 190  14 246 190  14\n-246 190  14 246 190  14 246 190  14 246 190  14\n-241 196  14 184 144  12  10  10  10   2   2   6\n-  6   6   6 116 116 116 242 242 242 253 253 253\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 231 231 231 198 198 198 214 170  54\n-236 178  12 236 178  12 210 150  10 137  92   6\n- 18  14   6   2   2   6   2   2   6   2   2   6\n-  6   6   6  70  47   6 200 144  11 236 178  12\n-239 182  13 239 182  13 124 112  88  58  58  58\n- 22  22  22   6   6   6   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0  10  10  10\n- 30  30  30  70  70  70 180 133  36 226 170  11\n-239 182  13 242 186  14 242 186  14 246 186  14\n-246 190  14 246 190  14 246 190  14 246 190  14\n-246 190  14 246 190  14 246 190  14 246 190  14\n-246 190  14 232 195  16  98  70   6   2   2   6\n-  2   2   6   2   2   6  66  66  66 221 221 221\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 206 206 206 198 198 198 214 166  58\n-230 174  11 230 174  11 216 158  10 192 133   9\n-163 110   8 116  81   8 102  78  10 116  81   8\n-167 114   7 197 138  11 226 170  11 239 182  13\n-242 186  14 242 186  14 162 146  94  78  78  78\n- 34  34  34  14  14  14   6   6   6   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   6   6   6\n- 30  30  30  78  78  78 190 142  34 226 170  11\n-239 182  13 246 190  14 246 190  14 246 190  14\n-246 190  14 246 190  14 246 190  14 246 190  14\n-246 190  14 246 190  14 246 190  14 246 190  14\n-246 190  14 241 196  14 203 166  17  22  18   6\n-  2   2   6   2   2   6   2   2   6  38  38  38\n-218 218 218 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 253 253 253 253 253 253\n-250 250 250 206 206 206 198 198 198 202 162  69\n-226 170  11 236 178  12 224 166  10 210 150  10\n-200 144  11 197 138  11 192 133   9 197 138  11\n-210 150  10 226 170  11 242 186  14 246 190  14\n-246 190  14 246 186  14 225 175  15 124 112  88\n- 62  62  62  30  30  30  14  14  14   6   6   6\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0  10  10  10\n- 30  30  30  78  78  78 174 135  50 224 166  10\n-239 182  13 246 190  14 246 190  14 246 190  14\n-246 190  14 246 190  14 246 190  14 246 190  14\n-246 190  14 246 190  14 246 190  14 246 190  14\n-246 190  14 246 190  14 241 196  14 139 102  15\n-  2   2   6   2   2   6   2   2   6   2   2   6\n- 78  78  78 250 250 250 253 253 253 253 253 253\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 253 253 253 253 253 253\n-250 250 250 214 214 214 198 198 198 190 150  46\n-219 162  10 236 178  12 234 174  13 224 166  10\n-216 158  10 213 154  11 213 154  11 216 158  10\n-226 170  11 239 182  13 246 190  14 246 190  14\n-246 190  14 246 190  14 242 186  14 206 162  42\n-101 101 101  58  58  58  30  30  30  14  14  14\n-  6   6   6   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0  10  10  10\n- 30  30  30  74  74  74 174 135  50 216 158  10\n-236 178  12 246 190  14 246 190  14 246 190  14\n-246 190  14 246 190  14 246 190  14 246 190  14\n-246 190  14 246 190  14 246 190  14 246 190  14\n-246 190  14 246 190  14 241 196  14 226 184  13\n- 61  42   6   2   2   6   2   2   6   2   2   6\n- 22  22  22 238 238 238 253 253 253 253 253 253\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 226 226 226 187 187 187 180 133  36\n-216 158  10 236 178  12 239 182  13 236 178  12\n-230 174  11 226 170  11 226 170  11 230 174  11\n-236 178  12 242 186  14 246 190  14 246 190  14\n-246 190  14 246 190  14 246 186  14 239 182  13\n-206 162  42 106 106 106  66  66  66  34  34  34\n- 14  14  14   6   6   6   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   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0   0   0   0   0   0   0   0  10  10  10\n- 30  30  30  78  78  78 163 133  67 210 150  10\n-236 178  12 246 186  14 246 190  14 246 190  14\n-246 190  14 246 190  14 246 190  14 246 190  14\n-246 190  14 246 190  14 246 190  14 246 190  14\n-246 190  14 246 190  14 246 190  14 246 190  14\n-241 196  14 215 174  15 190 178 144 253 253 253\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 253 253 253 218 218 218\n- 58  58  58   2   2   6  22  18   6 167 114   7\n-216 158  10 236 178  12 246 186  14 246 190  14\n-246 190  14 246 190  14 246 190  14 246 190  14\n-246 190  14 246 190  14 246 190  14 246 190  14\n-246 190  14 246 190  14 246 190  14 246 190  14\n-246 190  14 246 186  14 242 186  14 190 150  46\n- 54  54  54  22  22  22   6   6   6   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0  14  14  14\n- 38  38  38  86  86  86 180 133  36 213 154  11\n-236 178  12 246 186  14 246 190  14 246 190  14\n-246 190  14 246 190  14 246 190  14 246 190  14\n-246 190  14 246 190  14 246 190  14 246 190  14\n-246 190  14 246 190  14 246 190  14 246 190  14\n-246 190  14 232 195  16 190 146  13 214 214 214\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 250 250 250 170 170 170  26  26  26\n-  2   2   6   2   2   6  37  26   9 163 110   8\n-219 162  10 239 182  13 246 186  14 246 190  14\n-246 190  14 246 190  14 246 190  14 246 190  14\n-246 190  14 246 190  14 246 190  14 246 190  14\n-246 190  14 246 190  14 246 190  14 246 190  14\n-246 186  14 236 178  12 224 166  10 142 122  72\n- 46  46  46  18  18  18   6   6   6   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   6   6   6  18  18  18\n- 50  50  50 109 106  95 192 133   9 224 166  10\n-242 186  14 246 190  14 246 190  14 246 190  14\n-246 190  14 246 190  14 246 190  14 246 190  14\n-246 190  14 246 190  14 246 190  14 246 190  14\n-246 190  14 246 190  14 246 190  14 246 190  14\n-242 186  14 226 184  13 210 162  10 142 110  46\n-226 226 226 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 253 253 253 253 253 253\n-253 253 253 253 253 253 253 253 253 253 253 253\n-198 198 198  66  66  66   2   2   6   2   2   6\n-  2   2   6   2   2   6  50  34   6 156 107  11\n-219 162  10 239 182  13 246 186  14 246 190  14\n-246 190  14 246 190  14 246 190  14 246 190  14\n-246 190  14 246 190  14 246 190  14 246 190  14\n-246 190  14 246 190  14 246 190  14 242 186  14\n-234 174  13 213 154  11 154 122  46  66  66  66\n- 30  30  30  10  10  10   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   6   6   6  22  22  22\n- 58  58  58 154 121  60 206 145  10 234 174  13\n-242 186  14 246 186  14 246 190  14 246 190  14\n-246 190  14 246 190  14 246 190  14 246 190  14\n-246 190  14 246 190  14 246 190  14 246 190  14\n-246 190  14 246 190  14 246 190  14 246 190  14\n-246 186  14 236 178  12 210 162  10 163 110   8\n- 61  42   6 138 138 138 218 218 218 250 250 250\n-253 253 253 253 253 253 253 253 253 250 250 250\n-242 242 242 210 210 210 144 144 144  66  66  66\n-  6   6   6   2   2   6   2   2   6   2   2   6\n-  2   2   6   2   2   6  61  42   6 163 110   8\n-216 158  10 236 178  12 246 190  14 246 190  14\n-246 190  14 246 190  14 246 190  14 246 190  14\n-246 190  14 246 190  14 246 190  14 246 190  14\n-246 190  14 239 182  13 230 174  11 216 158  10\n-190 142  34 124 112  88  70  70  70  38  38  38\n- 18  18  18   6   6   6   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   6   6   6  22  22  22\n- 62  62  62 168 124  44 206 145  10 224 166  10\n-236 178  12 239 182  13 242 186  14 242 186  14\n-246 186  14 246 190  14 246 190  14 246 190  14\n-246 190  14 246 190  14 246 190  14 246 190  14\n-246 190  14 246 190  14 246 190  14 246 190  14\n-246 190  14 236 178  12 216 158  10 175 118   6\n- 80  54   7   2   2   6   6   6   6  30  30  30\n- 54  54  54  62  62  62  50  50  50  38  38  38\n- 14  14  14   2   2   6   2   2   6   2   2   6\n-  2   2   6   2   2   6   2   2   6   2   2   6\n-  2   2   6   6   6   6  80  54   7 167 114   7\n-213 154  11 236 178  12 246 190  14 246 190  14\n-246 190  14 246 190  14 246 190  14 246 190  14\n-246 190  14 242 186  14 239 182  13 239 182  13\n-230 174  11 210 150  10 174 135  50 124 112  88\n- 82  82  82  54  54  54  34  34  34  18  18  18\n-  6   6   6   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   6   6   6  18  18  18\n- 50  50  50 158 118  36 192 133   9 200 144  11\n-216 158  10 219 162  10 224 166  10 226 170  11\n-230 174  11 236 178  12 239 182  13 239 182  13\n-242 186  14 246 186  14 246 190  14 246 190  14\n-246 190  14 246 190  14 246 190  14 246 190  14\n-246 186  14 230 174  11 210 150  10 163 110   8\n-104  69   6  10  10  10   2   2   6   2   2   6\n-  2   2   6   2   2   6   2   2   6   2   2   6\n-  2   2   6   2   2   6   2   2   6   2   2   6\n-  2   2   6   2   2   6   2   2   6   2   2   6\n-  2   2   6   6   6   6  91  60   6 167 114   7\n-206 145  10 230 174  11 242 186  14 246 190  14\n-246 190  14 246 190  14 246 186  14 242 186  14\n-239 182  13 230 174  11 224 166  10 213 154  11\n-180 133  36 124 112  88  86  86  86  58  58  58\n- 38  38  38  22  22  22  10  10  10   6   6   6\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   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0   0   0   0   0   0   0   0   6   6   6\n- 18  18  18  34  34  34  58  58  58  78  78  78\n-101  98  89 124 112  88 142 110  46 156 107  11\n-163 110   8 167 114   7 175 118   6 180 123   7\n-185 133  11 197 138  11 210 150  10 219 162  10\n-226 170  11 236 178  12 236 178  12 234 174  13\n-219 162  10 197 138  11 163 110   8 130  83   6\n- 91  60   6  10  10  10   2   2   6   2   2   6\n- 18  18  18  38  38  38  38  38  38  38  38  38\n- 38  38  38  38  38  38  38  38  38  38  38  38\n- 38  38  38  38  38  38  26  26  26   2   2   6\n-  2   2   6   6   6   6  70  47   6 137  92   6\n-175 118   6 200 144  11 219 162  10 230 174  11\n-234 174  13 230 174  11 219 162  10 210 150  10\n-192 133   9 163 110   8 124 112  88  82  82  82\n- 50  50  50  30  30  30  14  14  14   6   6   6\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   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0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   6   6   6  10  10  10\n- 14  14  14  22  22  22  30  30  30  38  38  38\n- 50  50  50  62  62  62  74  74  74  90  90  90\n-101  98  89 112 100  78 121  87  25 124  80   6\n-137  92   6 152  99   6 152  99   6 152  99   6\n-138  86   6 124  80   6  98  70   6  86  66  30\n-101  98  89  82  82  82  58  58  58  46  46  46\n- 38  38  38  34  34  34  34  34  34  34  34  34\n- 34  34  34  34  34  34  34  34  34  34  34  34\n- 34  34  34  34  34  34  38  38  38  42  42  42\n- 54  54  54  82  82  82  94  86  76  91  60   6\n-134  86   6 156 107  11 167 114   7 175 118   6\n-175 118   6 167 114   7 152  99   6 121  87  25\n-101  98  89  62  62  62  34  34  34  18  18  18\n-  6   6   6   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   0   0   0   0   0   0   0   0   0   0   0\n-  0   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0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0\n+0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0\n+2 0 1  52 5 18  141 13 49  185 17 65  191 17 67  189 17 67\n+189 17 66  188 17 66  188 17 66  189 17 66  191 17 67  187 17 66\n+146 13 51  56 5 19  4 0 1  0 0 0  0 0 0  0 0 0\n+0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0\n+0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0\n+0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0\n+0 0 0  0 0 0  0 0 0\n+0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0\n+0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0\n+0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0\n+0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0\n+0 0 0  0 0 0  14 1 5  68 6 24  131 12 46  166 15 58\n+180 16 63  183 17 64  180 16 63  168 15 59  134 12 47  75 7 26\n+17 2 6  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0\n+0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0\n+0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0\n+0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0\n+0 0 0  0 0 0  0 0 0\n+0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0\n+0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0\n+0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0\n+0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0\n+0 0 0  0 0 0  0 0 0  0 0 0  5 0 2  24 2 8\n+44 4 15  52 5 18  45 4 16  26 2 9  6 1 2  0 0 0\n+0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0\n+0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0\n+0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0\n+0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0\n+0 0 0  0 0 0  0 0 0\n+0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0\n+0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0\n+0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0\n+0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0\n+0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0\n+0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0\n+0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0\n+0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0\n+0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0\n+0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0\n+0 0 0  0 0 0  0 0 0\n+0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0\n+0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0\n+0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0\n+0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0\n+0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0\n+0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0\n+0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0\n+0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0\n+0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0\n+0 0 0  0 0 0  0 0 0  0 0 0  0 0 0  0 0 0\n+0 0 0  0 0 0  0 0 0\n--- a/include/soc/bcm2835/raspberrypi-firmware.h\n+++ b/include/soc/bcm2835/raspberrypi-firmware.h\n@@ -123,6 +123,7 @@ enum rpi_firmware_property_tag {\n \tRPI_FIRMWARE_FRAMEBUFFER_SET_DEPTH =                  0x00048005,\n \tRPI_FIRMWARE_FRAMEBUFFER_SET_PIXEL_ORDER =            0x00048006,\n \tRPI_FIRMWARE_FRAMEBUFFER_SET_ALPHA_MODE =             0x00048007,\n+\tRPI_FIRMWARE_FRAMEBUFFER_SET_PITCH =                  0x00048008,\n \tRPI_FIRMWARE_FRAMEBUFFER_SET_VIRTUAL_OFFSET =         0x00048009,\n \tRPI_FIRMWARE_FRAMEBUFFER_SET_OVERSCAN =               0x0004800a,\n \tRPI_FIRMWARE_FRAMEBUFFER_SET_PALETTE =                0x0004800b,\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0042-Pulled-in-the-multi-frame-buffer-support-from-the-Pi.patch",
    "content": "From 4ac7128970e15d83ef3c2a65e65ca9ee4096c9d1 Mon Sep 17 00:00:00 2001\nFrom: James Hughes <james.hughes@raspberrypi.org>\nDate: Thu, 14 Mar 2019 13:27:54 +0000\nSubject: [PATCH] Pulled in the multi frame buffer support from the Pi3\n repo\n\n---\n drivers/video/fbdev/bcm2708_fb.c           | 457 +++++++++++++++------\n include/soc/bcm2835/raspberrypi-firmware.h |  13 +\n 2 files changed, 337 insertions(+), 133 deletions(-)\n\n--- a/drivers/video/fbdev/bcm2708_fb.c\n+++ b/drivers/video/fbdev/bcm2708_fb.c\n@@ -2,6 +2,7 @@\n  *  linux/drivers/video/bcm2708_fb.c\n  *\n  * Copyright (C) 2010 Broadcom\n+ * Copyright (C) 2018 Raspberry Pi (Trading) Ltd\n  *\n  * This file is subject to the terms and conditions of the GNU General Public\n  * License.  See the file COPYING in the main directory of this archive\n@@ -13,6 +14,7 @@\n  * Copyright 1999-2001 Jeff Garzik <jgarzik@pobox.com>\n  *\n  */\n+\n #include <linux/module.h>\n #include <linux/kernel.h>\n #include <linux/errno.h>\n@@ -33,6 +35,7 @@\n #include <linux/io.h>\n #include <linux/dma-mapping.h>\n #include <soc/bcm2835/raspberrypi-firmware.h>\n+#include <linux/mutex.h>\n \n //#define BCM2708_FB_DEBUG\n #define MODULE_NAME \"bcm2708_fb\"\n@@ -79,64 +82,150 @@ struct bcm2708_fb_stats {\n \tu32 dma_irqs;\n };\n \n+struct vc4_display_settings_t {\n+\tu32 display_num;\n+\tu32 width;\n+\tu32 height;\n+\tu32 depth;\n+\tu32 pitch;\n+\tu32 virtual_width;\n+\tu32 virtual_height;\n+\tu32 virtual_width_offset;\n+\tu32 virtual_height_offset;\n+\tunsigned long fb_bus_address;\n+};\n+\n+struct bcm2708_fb_dev;\n+\n struct bcm2708_fb {\n \tstruct fb_info fb;\n \tstruct platform_device *dev;\n-\tstruct rpi_firmware *fw;\n \tu32 cmap[16];\n \tu32 gpu_cmap[256];\n-\tint dma_chan;\n-\tint dma_irq;\n-\tvoid __iomem *dma_chan_base;\n-\tvoid *cb_base;\t\t/* DMA control blocks */\n-\tdma_addr_t cb_handle;\n \tstruct dentry *debugfs_dir;\n-\twait_queue_head_t dma_waitq;\n-\tstruct bcm2708_fb_stats stats;\n+\tstruct dentry *debugfs_subdir;\n \tunsigned long fb_bus_address;\n-\tbool disable_arm_alloc;\n+\tstruct { u32 base, length; } gpu;\n+\tstruct vc4_display_settings_t display_settings;\n+\tstruct debugfs_regset32 screeninfo_regset;\n+\tstruct bcm2708_fb_dev *fbdev;\n \tunsigned int image_size;\n \tdma_addr_t dma_addr;\n \tvoid *cpuaddr;\n };\n \n+#define MAX_FRAMEBUFFERS 3\n+\n+struct bcm2708_fb_dev {\n+\tint firmware_supports_multifb;\n+\t/* Protects the DMA system from multiple FB access */\n+\tstruct mutex dma_mutex;\n+\tint dma_chan;\n+\tint dma_irq;\n+\tvoid __iomem *dma_chan_base;\n+\twait_queue_head_t dma_waitq;\n+\tbool disable_arm_alloc;\n+\tstruct bcm2708_fb_stats dma_stats;\n+\tvoid *cb_base;\t/* DMA control blocks */\n+\tdma_addr_t cb_handle;\n+\tint instance_count;\n+\tint num_displays;\n+\tstruct rpi_firmware *fw;\n+\tstruct bcm2708_fb displays[MAX_FRAMEBUFFERS];\n+};\n+\n #define to_bcm2708(info)\tcontainer_of(info, struct bcm2708_fb, fb)\n \n static void bcm2708_fb_debugfs_deinit(struct bcm2708_fb *fb)\n {\n-\tdebugfs_remove_recursive(fb->debugfs_dir);\n-\tfb->debugfs_dir = NULL;\n+\tdebugfs_remove_recursive(fb->debugfs_subdir);\n+\tfb->debugfs_subdir = NULL;\n+\n+\tfb->fbdev->instance_count--;\n+\n+\tif (!fb->fbdev->instance_count) {\n+\t\tdebugfs_remove_recursive(fb->debugfs_dir);\n+\t\tfb->debugfs_dir = NULL;\n+\t}\n }\n \n static int bcm2708_fb_debugfs_init(struct bcm2708_fb *fb)\n {\n+\tchar buf[3];\n+\tstruct bcm2708_fb_dev *fbdev = fb->fbdev;\n+\n \tstatic struct debugfs_reg32 stats_registers[] = {\n-\t\t{\n-\t\t\t\"dma_copies\",\n-\t\t\toffsetof(struct bcm2708_fb_stats, dma_copies)\n-\t\t},\n-\t\t{\n-\t\t\t\"dma_irqs\",\n-\t\t\toffsetof(struct bcm2708_fb_stats, dma_irqs)\n-\t\t},\n+\t{\"dma_copies\", offsetof(struct bcm2708_fb_stats, dma_copies)},\n+\t{\"dma_irqs\",   offsetof(struct bcm2708_fb_stats, dma_irqs)},\n \t};\n \n-\tfb->debugfs_dir = debugfs_create_dir(DRIVER_NAME, NULL);\n+\tstatic struct debugfs_reg32 screeninfo[] = {\n+\t{\"width\",\t offsetof(struct fb_var_screeninfo, xres)},\n+\t{\"height\",\t offsetof(struct fb_var_screeninfo, yres)},\n+\t{\"bpp\",\t\t offsetof(struct fb_var_screeninfo, bits_per_pixel)},\n+\t{\"xres_virtual\", offsetof(struct fb_var_screeninfo, xres_virtual)},\n+\t{\"yres_virtual\", offsetof(struct fb_var_screeninfo, yres_virtual)},\n+\t{\"xoffset\",\t offsetof(struct fb_var_screeninfo, xoffset)},\n+\t{\"yoffset\",\t offsetof(struct fb_var_screeninfo, yoffset)},\n+\t};\n+\n+\tfb->debugfs_dir = debugfs_lookup(DRIVER_NAME, NULL);\n+\n+\tif (!fb->debugfs_dir)\n+\t\tfb->debugfs_dir = debugfs_create_dir(DRIVER_NAME, NULL);\n+\n \tif (!fb->debugfs_dir) {\n-\t\tpr_warn(\"%s: could not create debugfs entry\\n\",\n-\t\t\t__func__);\n+\t\tdev_warn(fb->fb.dev, \"%s: could not create debugfs folder\\n\",\n+\t\t\t __func__);\n \t\treturn -EFAULT;\n \t}\n \n-\tfb->stats.regset.regs = stats_registers;\n-\tfb->stats.regset.nregs = ARRAY_SIZE(stats_registers);\n-\tfb->stats.regset.base = &fb->stats;\n+\tsnprintf(buf, sizeof(buf), \"%u\", fb->display_settings.display_num);\n+\n+\tfb->debugfs_subdir = debugfs_create_dir(buf, fb->debugfs_dir);\n \n \tdebugfs_create_regset32(\"stats\", 0444, fb->debugfs_dir,\n \t\t\t\t&fb->stats.regset);\n+\n+\tif (!fb->debugfs_subdir) {\n+\t\tdev_warn(fb->fb.dev, \"%s: could not create debugfs entry %u\\n\",\n+\t\t\t __func__, fb->display_settings.display_num);\n+\t\treturn -EFAULT;\n+\t}\n+\n+\tfbdev->dma_stats.regset.regs = stats_registers;\n+\tfbdev->dma_stats.regset.nregs = ARRAY_SIZE(stats_registers);\n+\tfbdev->dma_stats.regset.base = &fbdev->dma_stats;\n+\n+\tdebugfs_create_regset32(\"dma_stats\", 0444, fb->debugfs_subdir,\n+\t\t\t\t&fbdev->dma_stats.regset);\n+\n+\tfb->screeninfo_regset.regs = screeninfo;\n+\tfb->screeninfo_regset.nregs = ARRAY_SIZE(screeninfo);\n+\tfb->screeninfo_regset.base = &fb->fb.var;\n+\n+\tdebugfs_create_regset32(\"screeninfo\", 0444, fb->debugfs_subdir,\n+\t\t\t\t&fb->screeninfo_regset);\n+\n+\tfbdev->instance_count++;\n+\n \treturn 0;\n }\n \n+static void set_display_num(struct bcm2708_fb *fb)\n+{\n+\tif (fb && fb->fbdev && fb->fbdev->firmware_supports_multifb) {\n+\t\tu32 tmp = fb->display_settings.display_num;\n+\n+\t\tif (rpi_firmware_property(fb->fbdev->fw,\n+\t\t\t\t\t  RPI_FIRMWARE_FRAMEBUFFER_SET_DISPLAY_NUM,\n+\t\t\t\t\t  &tmp,\n+\t\t\t\t\t  sizeof(tmp)))\n+\t\t\tdev_warn_once(fb->fb.dev,\n+\t\t\t\t      \"Set display number call failed. Old GPU firmware?\");\n+\t}\n+}\n+\n static int bcm2708_fb_set_bitfields(struct fb_var_screeninfo *var)\n {\n \tint ret = 0;\n@@ -214,11 +303,11 @@ static int bcm2708_fb_check_var(struct f\n \t\t\t\tstruct fb_info *info)\n {\n \t/* info input, var output */\n-\tprint_debug(\"%s(%p) %dx%d (%dx%d), %d, %d\\n\",\n+\tprint_debug(\"%s(%p) %ux%u (%ux%u), %ul, %u\\n\",\n \t\t    __func__, info, info->var.xres, info->var.yres,\n \t\t    info->var.xres_virtual, info->var.yres_virtual,\n-\t\t    (int)info->screen_size, info->var.bits_per_pixel);\n-\tprint_debug(\"%s(%p) %dx%d (%dx%d), %d\\n\", __func__, var, var->xres,\n+\t\t    info->screen_size, info->var.bits_per_pixel);\n+\tprint_debug(\"%s(%p) %ux%u (%ux%u), %u\\n\", __func__, var, var->xres,\n \t\t    var->yres, var->xres_virtual, var->yres_virtual,\n \t\t    var->bits_per_pixel);\n \n@@ -281,17 +370,24 @@ static int bcm2708_fb_set_par(struct fb_\n \t};\n \tint ret, image_size;\n \n-\n-\tprint_debug(\"%s(%p) %dx%d (%dx%d), %d, %d\\n\", __func__, info,\n+\tprint_debug(\"%s(%p) %dx%d (%dx%d), %d, %d (display %d)\\n\", __func__,\n+\t\t    info,\n \t\t    info->var.xres, info->var.yres, info->var.xres_virtual,\n \t\t    info->var.yres_virtual, (int)info->screen_size,\n-\t\t    info->var.bits_per_pixel);\n+\t\t    info->var.bits_per_pixel, value);\n+\n+\t/* Need to set the display number to act on first\n+\t * Cannot do it in the tag list because on older firmware the call\n+\t * will fail and stop the rest of the list being executed.\n+\t * We can ignore this call failing as the default at other end is 0\n+\t */\n+\tset_display_num(fb);\n \n \t/* Try allocating our own buffer. We can specify all the parameters */\n \timage_size = ((info->var.xres * info->var.yres) *\n \t\t      info->var.bits_per_pixel) >> 3;\n \n-\tif (!fb->disable_arm_alloc &&\n+\tif (!fb->fbdev->disable_arm_alloc &&\n \t    (image_size != fb->image_size || !fb->dma_addr)) {\n \t\tif (fb->dma_addr) {\n \t\t\tdma_free_coherent(info->device, fb->image_size,\n@@ -306,7 +402,7 @@ static int bcm2708_fb_set_par(struct fb_\n \n \t\tif (!fb->cpuaddr) {\n \t\t\tfb->dma_addr = 0;\n-\t\t\tfb->disable_arm_alloc = true;\n+\t\t\tfb->fbdev->disable_arm_alloc = true;\n \t\t} else {\n \t\t\tfb->image_size = image_size;\n \t\t}\n@@ -317,7 +413,7 @@ static int bcm2708_fb_set_par(struct fb_\n \t\tfbinfo.screen_size = image_size;\n \t\tfbinfo.pitch = (info->var.xres * info->var.bits_per_pixel) >> 3;\n \n-\t\tret = rpi_firmware_property_list(fb->fw, &fbinfo,\n+\t\tret = rpi_firmware_property_list(fb->fbdev->fw, &fbinfo,\n \t\t\t\t\t\t sizeof(fbinfo));\n \t\tif (ret || fbinfo.base != fb->dma_addr) {\n \t\t\t/* Firmware either failed, or assigned a different base\n@@ -330,7 +426,7 @@ static int bcm2708_fb_set_par(struct fb_\n \t\t\tfb->image_size = 0;\n \t\t\tfb->cpuaddr = NULL;\n \t\t\tfb->dma_addr = 0;\n-\t\t\tfb->disable_arm_alloc = true;\n+\t\t\tfb->fbdev->disable_arm_alloc = true;\n \t\t}\n \t} else {\n \t\t/* Our allocation failed - drop into the old scheme of\n@@ -349,7 +445,7 @@ static int bcm2708_fb_set_par(struct fb_\n \t\tfbinfo.tag6.tag = RPI_FIRMWARE_FRAMEBUFFER_GET_PITCH;\n \t\tfbinfo.pitch = 0;\n \n-\t\tret = rpi_firmware_property_list(fb->fw, &fbinfo,\n+\t\tret = rpi_firmware_property_list(fb->fbdev->fw, &fbinfo,\n \t\t\t\t\t\t sizeof(fbinfo));\n \t\tif (ret) {\n \t\t\tdev_err(info->device,\n@@ -439,7 +535,10 @@ static int bcm2708_fb_setcolreg(unsigned\n \t\t\tpacket->length = regno + 1;\n \t\t\tmemcpy(packet->cmap, fb->gpu_cmap,\n \t\t\t       sizeof(packet->cmap));\n-\t\t\tret = rpi_firmware_property(fb->fw,\n+\n+\t\t\tset_display_num(fb);\n+\n+\t\t\tret = rpi_firmware_property(fb->fbdev->fw,\n \t\t\t\t\t\t    RPI_FIRMWARE_FRAMEBUFFER_SET_PALETTE,\n \t\t\t\t\t\t    packet,\n \t\t\t\t\t\t    (2 + packet->length) * sizeof(u32));\n@@ -478,8 +577,11 @@ static int bcm2708_fb_blank(int blank_mo\n \t\treturn -EINVAL;\n \t}\n \n-\tret = rpi_firmware_property(fb->fw, RPI_FIRMWARE_FRAMEBUFFER_BLANK,\n+\tset_display_num(fb);\n+\n+\tret = rpi_firmware_property(fb->fbdev->fw, RPI_FIRMWARE_FRAMEBUFFER_BLANK,\n \t\t\t\t    &value, sizeof(value));\n+\n \tif (ret)\n \t\tdev_err(info->device, \"%s(%d) failed: %d\\n\", __func__,\n \t\t\tblank_mode, ret);\n@@ -496,12 +598,14 @@ static int bcm2708_fb_pan_display(struct\n \tinfo->var.yoffset = var->yoffset;\n \tresult = bcm2708_fb_set_par(info);\n \tif (result != 0)\n-\t\tpr_err(\"%s(%d,%d) returns=%d\\n\", __func__, var->xoffset,\n+\t\tpr_err(\"%s(%u,%u) returns=%d\\n\", __func__, var->xoffset,\n \t\t       var->yoffset, result);\n \treturn result;\n }\n \n static int bcm2708_ioctl(struct fb_info *info, unsigned int cmd, unsigned long arg)\n+static int bcm2708_ioctl(struct fb_info *info, unsigned int cmd,\n+\t\t\t unsigned long arg)\n {\n \tstruct bcm2708_fb *fb = to_bcm2708(info);\n \tu32 dummy = 0;\n@@ -509,7 +613,9 @@ static int bcm2708_ioctl(struct fb_info\n \n \tswitch (cmd) {\n \tcase FBIO_WAITFORVSYNC:\n-\t\tret = rpi_firmware_property(fb->fw,\n+\t\tset_display_num(fb);\n+\n+\t\tret = rpi_firmware_property(fb->fbdev->fw,\n \t\t\t\t\t    RPI_FIRMWARE_FRAMEBUFFER_SET_VSYNC,\n \t\t\t\t\t    &dummy, sizeof(dummy));\n \t\tbreak;\n@@ -526,23 +632,22 @@ static int bcm2708_ioctl(struct fb_info\n static void bcm2708_fb_fillrect(struct fb_info *info,\n \t\t\t\tconst struct fb_fillrect *rect)\n {\n-\t/* (is called) print_debug(\"bcm2708_fb_fillrect\\n\"); */\n \tcfb_fillrect(info, rect);\n }\n \n /* A helper function for configuring dma control block */\n static void set_dma_cb(struct bcm2708_dma_cb *cb,\n-\t\t       int        burst_size,\n-\t\t       dma_addr_t dst,\n-\t\t       int        dst_stride,\n-\t\t       dma_addr_t src,\n-\t\t       int        src_stride,\n-\t\t       int        w,\n-\t\t       int        h)\n+\t\tint        burst_size,\n+\t\tdma_addr_t dst,\n+\t\tint        dst_stride,\n+\t\tdma_addr_t src,\n+\t\tint        src_stride,\n+\t\tint        w,\n+\t\tint        h)\n {\n \tcb->info = BCM2708_DMA_BURST(burst_size) | BCM2708_DMA_S_WIDTH |\n-\t\t   BCM2708_DMA_S_INC | BCM2708_DMA_D_WIDTH |\n-\t\t   BCM2708_DMA_D_INC | BCM2708_DMA_TDMODE;\n+\t\tBCM2708_DMA_S_INC | BCM2708_DMA_D_WIDTH |\n+\t\tBCM2708_DMA_D_INC | BCM2708_DMA_TDMODE;\n \tcb->dst = dst;\n \tcb->src = src;\n \t/*\n@@ -560,15 +665,19 @@ static void bcm2708_fb_copyarea(struct f\n \t\t\t\tconst struct fb_copyarea *region)\n {\n \tstruct bcm2708_fb *fb = to_bcm2708(info);\n-\tstruct bcm2708_dma_cb *cb = fb->cb_base;\n+\tstruct bcm2708_fb_dev *fbdev = fb->fbdev;\n+\tstruct bcm2708_dma_cb *cb = fbdev->cb_base;\n \tint bytes_per_pixel = (info->var.bits_per_pixel + 7) >> 3;\n \n \t/* Channel 0 supports larger bursts and is a bit faster */\n-\tint burst_size = (fb->dma_chan == 0) ? 8 : 2;\n+\tint burst_size = (fbdev->dma_chan == 0) ? 8 : 2;\n \tint pixels = region->width * region->height;\n \n-\t/* Fallback to cfb_copyarea() if we don't like something */\n-\tif (bytes_per_pixel > 4 ||\n+\t/* If DMA is currently in use (ie being used on another FB), then\n+\t * rather than wait for it to finish, just use the cfb_copyarea\n+\t */\n+\tif (!mutex_trylock(&fbdev->dma_mutex) ||\n+\t    bytes_per_pixel > 4 ||\n \t    info->var.xres * info->var.yres > 1920 * 1200 ||\n \t    region->width <= 0 || region->width > info->var.xres ||\n \t    region->height <= 0 || region->height > info->var.yres ||\n@@ -595,8 +704,8 @@ static void bcm2708_fb_copyarea(struct f\n \t\t * 1920x1200 resolution at 32bpp pixel depth.\n \t\t */\n \t\tint y;\n-\t\tdma_addr_t control_block_pa = fb->cb_handle;\n-\t\tdma_addr_t scratchbuf = fb->cb_handle + 16 * 1024;\n+\t\tdma_addr_t control_block_pa = fbdev->cb_handle;\n+\t\tdma_addr_t scratchbuf = fbdev->cb_handle + 16 * 1024;\n \t\tint scanline_size = bytes_per_pixel * region->width;\n \t\tint scanlines_per_cb = (64 * 1024 - 16 * 1024) / scanline_size;\n \n@@ -646,10 +755,10 @@ static void bcm2708_fb_copyarea(struct f\n \t\t}\n \t\tset_dma_cb(cb, burst_size,\n \t\t\t   fb->fb_bus_address + dy * fb->fb.fix.line_length +\n-\t\t\t\t\t\t   bytes_per_pixel * region->dx,\n+\t\t\t   bytes_per_pixel * region->dx,\n \t\t\t   stride,\n \t\t\t   fb->fb_bus_address + sy * fb->fb.fix.line_length +\n-\t\t\t\t\t\t   bytes_per_pixel * region->sx,\n+\t\t\t   bytes_per_pixel * region->sx,\n \t\t\t   stride,\n \t\t\t   region->width * bytes_per_pixel,\n \t\t\t   region->height);\n@@ -659,32 +768,33 @@ static void bcm2708_fb_copyarea(struct f\n \tcb->next = 0;\n \n \tif (pixels < dma_busy_wait_threshold) {\n-\t\tbcm_dma_start(fb->dma_chan_base, fb->cb_handle);\n-\t\tbcm_dma_wait_idle(fb->dma_chan_base);\n+\t\tbcm_dma_start(fbdev->dma_chan_base, fbdev->cb_handle);\n+\t\tbcm_dma_wait_idle(fbdev->dma_chan_base);\n \t} else {\n-\t\tvoid __iomem *dma_chan = fb->dma_chan_base;\n+\t\tvoid __iomem *local_dma_chan = fbdev->dma_chan_base;\n \n \t\tcb->info |= BCM2708_DMA_INT_EN;\n-\t\tbcm_dma_start(fb->dma_chan_base, fb->cb_handle);\n-\t\twhile (bcm_dma_is_busy(dma_chan)) {\n-\t\t\twait_event_interruptible(fb->dma_waitq,\n-\t\t\t\t\t\t !bcm_dma_is_busy(dma_chan));\n+\t\tbcm_dma_start(fbdev->dma_chan_base, fbdev->cb_handle);\n+\t\twhile (bcm_dma_is_busy(local_dma_chan)) {\n+\t\t\twait_event_interruptible(fbdev->dma_waitq,\n+\t\t\t\t\t\t !bcm_dma_is_busy(local_dma_chan));\n \t\t}\n-\t\tfb->stats.dma_irqs++;\n+\t\tfbdev->dma_stats.dma_irqs++;\n \t}\n-\tfb->stats.dma_copies++;\n+\tfbdev->dma_stats.dma_copies++;\n+\n+\tmutex_unlock(&fbdev->dma_mutex);\n }\n \n static void bcm2708_fb_imageblit(struct fb_info *info,\n \t\t\t\t const struct fb_image *image)\n {\n-\t/* (is called) print_debug(\"bcm2708_fb_imageblit\\n\"); */\n \tcfb_imageblit(info, image);\n }\n \n static irqreturn_t bcm2708_fb_dma_irq(int irq, void *cxt)\n {\n-\tstruct bcm2708_fb *fb = cxt;\n+\tstruct bcm2708_fb_dev *fbdev = cxt;\n \n \t/* FIXME: should read status register to check if this is\n \t * actually interrupting us or not, in case this interrupt\n@@ -694,9 +804,9 @@ static irqreturn_t bcm2708_fb_dma_irq(in\n \t */\n \n \t/* acknowledge the interrupt */\n-\twritel(BCM2708_DMA_INT, fb->dma_chan_base + BCM2708_DMA_CS);\n+\twritel(BCM2708_DMA_INT, fbdev->dma_chan_base + BCM2708_DMA_CS);\n \n-\twake_up(&fb->dma_waitq);\n+\twake_up(&fbdev->dma_waitq);\n \treturn IRQ_HANDLED;\n }\n \n@@ -729,11 +839,23 @@ static int bcm2708_fb_register(struct bc\n \tfb->fb.fix.ywrapstep = 0;\n \tfb->fb.fix.accel = FB_ACCEL_NONE;\n \n-\tfb->fb.var.xres = fbwidth;\n-\tfb->fb.var.yres = fbheight;\n-\tfb->fb.var.xres_virtual = fbwidth;\n-\tfb->fb.var.yres_virtual = fbheight;\n-\tfb->fb.var.bits_per_pixel = fbdepth;\n+\t/* If we have data from the VC4 on FB's, use that, otherwise use the\n+\t * module parameters\n+\t */\n+\tif (fb->display_settings.width) {\n+\t\tfb->fb.var.xres = fb->display_settings.width;\n+\t\tfb->fb.var.yres = fb->display_settings.height;\n+\t\tfb->fb.var.xres_virtual = fb->fb.var.xres;\n+\t\tfb->fb.var.yres_virtual = fb->fb.var.yres;\n+\t\tfb->fb.var.bits_per_pixel = fb->display_settings.depth;\n+\t} else {\n+\t\tfb->fb.var.xres = fbwidth;\n+\t\tfb->fb.var.yres = fbheight;\n+\t\tfb->fb.var.xres_virtual = fbwidth;\n+\t\tfb->fb.var.yres_virtual = fbheight;\n+\t\tfb->fb.var.bits_per_pixel = fbdepth;\n+\t}\n+\n \tfb->fb.var.vmode = FB_VMODE_NONINTERLACED;\n \tfb->fb.var.activate = FB_ACTIVATE_NOW;\n \tfb->fb.var.nonstd = 0;\n@@ -749,26 +871,23 @@ static int bcm2708_fb_register(struct bc\n \tfb->fb.monspecs.dclkmax = 100000000;\n \n \tbcm2708_fb_set_bitfields(&fb->fb.var);\n-\tinit_waitqueue_head(&fb->dma_waitq);\n \n \t/*\n \t * Allocate colourmap.\n \t */\n-\n \tfb_set_var(&fb->fb, &fb->fb.var);\n+\n \tret = bcm2708_fb_set_par(&fb->fb);\n+\n \tif (ret)\n \t\treturn ret;\n \n-\tprint_debug(\"BCM2708FB: registering framebuffer (%dx%d@%d) (%d)\\n\",\n-\t\t    fbwidth, fbheight, fbdepth, fbswap);\n-\n \tret = register_framebuffer(&fb->fb);\n-\tprint_debug(\"BCM2708FB: register framebuffer (%d)\\n\", ret);\n+\n \tif (ret == 0)\n \t\tgoto out;\n \n-\tprint_debug(\"BCM2708FB: cannot register framebuffer (%d)\\n\", ret);\n+\tdev_warn(fb->fb.dev, \"Unable to register framebuffer (%d)\\n\", ret);\n out:\n \treturn ret;\n }\n@@ -777,10 +896,18 @@ static int bcm2708_fb_probe(struct platf\n {\n \tstruct device_node *fw_np;\n \tstruct rpi_firmware *fw;\n-\tstruct bcm2708_fb *fb;\n-\tint ret;\n+\tint ret, i;\n+\tu32 num_displays;\n+\tstruct bcm2708_fb_dev *fbdev;\n+\tstruct { u32 base, length; } gpu_mem;\n+\n+\tfbdev = devm_kzalloc(&dev->dev, sizeof(*fbdev), GFP_KERNEL);\n+\n+\tif (!fbdev)\n+\t\treturn -ENOMEM;\n \n \tfw_np = of_parse_phandle(dev->dev.of_node, \"firmware\", 0);\n+\n /* Remove comment when booting without Device Tree is no longer supported\n  *\tif (!fw_np) {\n  *\t\tdev_err(&dev->dev, \"Missing firmware node\\n\");\n@@ -788,90 +915,154 @@ static int bcm2708_fb_probe(struct platf\n  *\t}\n  */\n \tfw = rpi_firmware_get(fw_np);\n+\tfbdev->fw = fw;\n+\n \tif (!fw)\n \t\treturn -EPROBE_DEFER;\n \n-\tfb = kzalloc(sizeof(*fb), GFP_KERNEL);\n-\tif (!fb) {\n-\t\tret = -ENOMEM;\n-\t\tgoto free_region;\n+\tret = rpi_firmware_property(fw,\n+\t\t\t\t    RPI_FIRMWARE_FRAMEBUFFER_GET_NUM_DISPLAYS,\n+\t\t\t\t    &num_displays, sizeof(u32));\n+\n+\t/* If we fail to get the number of displays, or it returns 0, then\n+\t * assume old firmware that doesn't have the mailbox call, so just\n+\t * set one display\n+\t */\n+\tif (ret || num_displays == 0) {\n+\t\tnum_displays = 1;\n+\t\tdev_err(&dev->dev,\n+\t\t\t\"Unable to determine number of FB's. Assuming 1\\n\");\n+\t\tret = 0;\n+\t} else {\n+\t\tfbdev->firmware_supports_multifb = 1;\n+\t}\n+\n+\tif (num_displays > MAX_FRAMEBUFFERS) {\n+\t\tdev_warn(&dev->dev,\n+\t\t\t \"More displays reported from firmware than supported in driver (%u vs %u)\",\n+\t\t\t num_displays, MAX_FRAMEBUFFERS);\n+\t\tnum_displays = MAX_FRAMEBUFFERS;\n \t}\n \n-\tfb->fw = fw;\n-\tbcm2708_fb_debugfs_init(fb);\n+\tdev_info(&dev->dev, \"FB found %d display(s)\\n\", num_displays);\n+\n+\t/* Set up the DMA information. Note we have just one set of DMA\n+\t * parameters to work with all the FB's so requires synchronising when\n+\t * being used\n+\t */\n+\n+\tmutex_init(&fbdev->dma_mutex);\n \n-\tfb->cb_base = dma_alloc_wc(&dev->dev, SZ_64K,\n-\t\t\t\t\t     &fb->cb_handle, GFP_KERNEL);\n-\tif (!fb->cb_base) {\n+\tfbdev->cb_base = dma_alloc_wc(&dev->dev, SZ_64K,\n+\t\t\t\t\t\t&fbdev->cb_handle,\n+\t\t\t\t\t\tGFP_KERNEL);\n+\tif (!fbdev->cb_base) {\n \t\tdev_err(&dev->dev, \"cannot allocate DMA CBs\\n\");\n \t\tret = -ENOMEM;\n \t\tgoto free_fb;\n \t}\n \n-\tpr_info(\"BCM2708FB: allocated DMA memory %pad\\n\", &fb->cb_handle);\n-\n \tret = bcm_dma_chan_alloc(BCM_DMA_FEATURE_BULK,\n-\t\t\t\t &fb->dma_chan_base, &fb->dma_irq);\n+\t\t\t\t &fbdev->dma_chan_base,\n+\t\t\t\t &fbdev->dma_irq);\n \tif (ret < 0) {\n-\t\tdev_err(&dev->dev, \"couldn't allocate a DMA channel\\n\");\n+\t\tdev_err(&dev->dev, \"Couldn't allocate a DMA channel\\n\");\n \t\tgoto free_cb;\n \t}\n-\tfb->dma_chan = ret;\n+\tfbdev->dma_chan = ret;\n \n-\tret = request_irq(fb->dma_irq, bcm2708_fb_dma_irq,\n-\t\t\t  0, \"bcm2708_fb dma\", fb);\n+\tret = request_irq(fbdev->dma_irq, bcm2708_fb_dma_irq,\n+\t\t\t  0, \"bcm2708_fb DMA\", fbdev);\n \tif (ret) {\n-\t\tpr_err(\"%s: failed to request DMA irq\\n\", __func__);\n+\t\tdev_err(&dev->dev,\n+\t\t\t\"Failed to request DMA irq\\n\");\n \t\tgoto free_dma_chan;\n \t}\n \n-\tpr_info(\"BCM2708FB: allocated DMA channel %d\\n\", fb->dma_chan);\n+\trpi_firmware_property(fbdev->fw,\n+\t\t\t      RPI_FIRMWARE_GET_VC_MEMORY,\n+\t\t\t      &gpu_mem, sizeof(gpu_mem));\n+\n+\tfor (i = 0; i < num_displays; i++) {\n+\t\tstruct bcm2708_fb *fb = &fbdev->displays[i];\n+\n+\t\tfb->display_settings.display_num = i;\n+\t\tfb->dev = dev;\n+\t\tfb->fb.device = &dev->dev;\n+\t\tfb->fbdev = fbdev;\n+\n+\t\tfb->gpu.base = gpu_mem.base;\n+\t\tfb->gpu.length = gpu_mem.length;\n+\n+\t\tif (fbdev->firmware_supports_multifb) {\n+\t\t\tret = rpi_firmware_property(fw,\n+\t\t\t\t\t\t    RPI_FIRMWARE_FRAMEBUFFER_GET_DISPLAY_SETTINGS,\n+\t\t\t\t\t\t    &fb->display_settings,\n+\t\t\t\t\t\t    GET_DISPLAY_SETTINGS_PAYLOAD_SIZE);\n+\t\t} else {\n+\t\t\tmemset(&fb->display_settings, 0,\n+\t\t\t       sizeof(fb->display_settings));\n+\t\t}\n \n-\tfb->dev = dev;\n-\tfb->fb.device = &dev->dev;\n+\t\tret = bcm2708_fb_register(fb);\n \n-\t/* failure here isn't fatal, but we'll fail in vc_mem_copy if\n-\t * fb->gpu is not valid\n-\t */\n-\trpi_firmware_property(fb->fw, RPI_FIRMWARE_GET_VC_MEMORY, &fb->gpu,\n-\t\t\t      sizeof(fb->gpu));\n+\t\tif (ret == 0) {\n+\t\t\tbcm2708_fb_debugfs_init(fb);\n \n-\tret = bcm2708_fb_register(fb);\n-\tif (ret == 0) {\n-\t\tplatform_set_drvdata(dev, fb);\n-\t\tgoto out;\n+\t\t\tfbdev->num_displays++;\n+\n+\t\t\tdev_info(&dev->dev,\n+\t\t\t\t \"Registered framebuffer for display %u, size %ux%u\\n\",\n+\t\t\t\t fb->display_settings.display_num,\n+\t\t\t\t fb->fb.var.xres,\n+\t\t\t\t fb->fb.var.yres);\n+\t\t} else {\n+\t\t\t// Use this to flag if this FB entry is in use.\n+\t\t\tfb->fbdev = NULL;\n+\t\t}\n+\t}\n+\n+\t// Did we actually successfully create any FB's?\n+\tif (fbdev->num_displays) {\n+\t\tinit_waitqueue_head(&fbdev->dma_waitq);\n+\t\tplatform_set_drvdata(dev, fbdev);\n+\t\treturn ret;\n \t}\n \n free_dma_chan:\n-\tbcm_dma_chan_free(fb->dma_chan);\n+\tbcm_dma_chan_free(fbdev->dma_chan);\n free_cb:\n-\tdma_free_wc(&dev->dev, SZ_64K, fb->cb_base, fb->cb_handle);\n+\tdma_free_wc(&dev->dev, SZ_64K, fbdev->cb_base,\n+\t\t\t      fbdev->cb_handle);\n free_fb:\n-\tkfree(fb);\n-free_region:\n \tdev_err(&dev->dev, \"probe failed, err %d\\n\", ret);\n-out:\n+\n \treturn ret;\n }\n \n static int bcm2708_fb_remove(struct platform_device *dev)\n {\n-\tstruct bcm2708_fb *fb = platform_get_drvdata(dev);\n+\tstruct bcm2708_fb_dev *fbdev = platform_get_drvdata(dev);\n+\tint i;\n \n \tplatform_set_drvdata(dev, NULL);\n \n-\tif (fb->fb.screen_base)\n-\t\tiounmap(fb->fb.screen_base);\n-\tunregister_framebuffer(&fb->fb);\n-\n-\tdma_free_wc(&dev->dev, SZ_64K, fb->cb_base, fb->cb_handle);\n-\tbcm_dma_chan_free(fb->dma_chan);\n-\n-\tbcm2708_fb_debugfs_deinit(fb);\n+\tfor (i = 0; i < fbdev->num_displays; i++) {\n+\t\tif (fbdev->displays[i].fb.screen_base)\n+\t\t\tiounmap(fbdev->displays[i].fb.screen_base);\n+\n+\t\tif (fbdev->displays[i].fbdev) {\n+\t\t\tunregister_framebuffer(&fbdev->displays[i].fb);\n+\t\t\tbcm2708_fb_debugfs_deinit(&fbdev->displays[i]);\n+\t\t}\n+\t}\n \n-\tfree_irq(fb->dma_irq, fb);\n+\tdma_free_wc(&dev->dev, SZ_64K, fbdev->cb_base,\n+\t\t\t      fbdev->cb_handle);\n+\tbcm_dma_chan_free(fbdev->dma_chan);\n+\tfree_irq(fbdev->dma_irq, fbdev);\n \n-\tkfree(fb);\n+\tmutex_destroy(&fbdev->dma_mutex);\n \n \treturn 0;\n }\n@@ -886,10 +1077,10 @@ static struct platform_driver bcm2708_fb\n \t.probe = bcm2708_fb_probe,\n \t.remove = bcm2708_fb_remove,\n \t.driver = {\n-\t\t   .name = DRIVER_NAME,\n-\t\t   .owner = THIS_MODULE,\n-\t\t   .of_match_table = bcm2708_fb_of_match_table,\n-\t\t   },\n+\t\t  .name = DRIVER_NAME,\n+\t\t  .owner = THIS_MODULE,\n+\t\t  .of_match_table = bcm2708_fb_of_match_table,\n+\t\t  },\n };\n \n static int __init bcm2708_fb_init(void)\n--- a/include/soc/bcm2835/raspberrypi-firmware.h\n+++ b/include/soc/bcm2835/raspberrypi-firmware.h\n@@ -106,9 +106,15 @@ enum rpi_firmware_property_tag {\n \tRPI_FIRMWARE_FRAMEBUFFER_GET_VIRTUAL_OFFSET =         0x00040009,\n \tRPI_FIRMWARE_FRAMEBUFFER_GET_OVERSCAN =               0x0004000a,\n \tRPI_FIRMWARE_FRAMEBUFFER_GET_PALETTE =                0x0004000b,\n+\tRPI_FIRMWARE_FRAMEBUFFER_GET_LAYER =                  0x0004000c,\n+\tRPI_FIRMWARE_FRAMEBUFFER_GET_TRANSFORM =              0x0004000d,\n+\tRPI_FIRMWARE_FRAMEBUFFER_GET_VSYNC =                  0x0004000e,\n \tRPI_FIRMWARE_FRAMEBUFFER_GET_TOUCHBUF =               0x0004000f,\n \tRPI_FIRMWARE_FRAMEBUFFER_GET_GPIOVIRTBUF =            0x00040010,\n \tRPI_FIRMWARE_FRAMEBUFFER_RELEASE =                    0x00048001,\n+\tRPI_FIRMWARE_FRAMEBUFFER_SET_DISPLAY_NUM =            0x00048013,\n+\tRPI_FIRMWARE_FRAMEBUFFER_GET_NUM_DISPLAYS =           0x00040013,\n+\tRPI_FIRMWARE_FRAMEBUFFER_GET_DISPLAY_SETTINGS =       0x00040014,\n \tRPI_FIRMWARE_FRAMEBUFFER_TEST_PHYSICAL_WIDTH_HEIGHT = 0x00044003,\n \tRPI_FIRMWARE_FRAMEBUFFER_TEST_VIRTUAL_WIDTH_HEIGHT =  0x00044004,\n \tRPI_FIRMWARE_FRAMEBUFFER_TEST_DEPTH =                 0x00044005,\n@@ -117,6 +123,8 @@ enum rpi_firmware_property_tag {\n \tRPI_FIRMWARE_FRAMEBUFFER_TEST_VIRTUAL_OFFSET =        0x00044009,\n \tRPI_FIRMWARE_FRAMEBUFFER_TEST_OVERSCAN =              0x0004400a,\n \tRPI_FIRMWARE_FRAMEBUFFER_TEST_PALETTE =               0x0004400b,\n+\tRPI_FIRMWARE_FRAMEBUFFER_TEST_LAYER =                 0x0004400c,\n+\tRPI_FIRMWARE_FRAMEBUFFER_TEST_TRANSFORM =             0x0004400d,\n \tRPI_FIRMWARE_FRAMEBUFFER_TEST_VSYNC =                 0x0004400e,\n \tRPI_FIRMWARE_FRAMEBUFFER_SET_PHYSICAL_WIDTH_HEIGHT =  0x00048003,\n \tRPI_FIRMWARE_FRAMEBUFFER_SET_VIRTUAL_WIDTH_HEIGHT =   0x00048004,\n@@ -127,9 +135,12 @@ enum rpi_firmware_property_tag {\n \tRPI_FIRMWARE_FRAMEBUFFER_SET_VIRTUAL_OFFSET =         0x00048009,\n \tRPI_FIRMWARE_FRAMEBUFFER_SET_OVERSCAN =               0x0004800a,\n \tRPI_FIRMWARE_FRAMEBUFFER_SET_PALETTE =                0x0004800b,\n+\n \tRPI_FIRMWARE_FRAMEBUFFER_SET_TOUCHBUF =               0x0004801f,\n \tRPI_FIRMWARE_FRAMEBUFFER_SET_GPIOVIRTBUF =            0x00048020,\n \tRPI_FIRMWARE_FRAMEBUFFER_SET_VSYNC =                  0x0004800e,\n+\tRPI_FIRMWARE_FRAMEBUFFER_SET_LAYER =                  0x0004800c,\n+\tRPI_FIRMWARE_FRAMEBUFFER_SET_TRANSFORM =              0x0004800d,\n \tRPI_FIRMWARE_FRAMEBUFFER_SET_BACKLIGHT =              0x0004800f,\n \n \tRPI_FIRMWARE_VCHIQ_INIT =                             0x00048010,\n@@ -138,6 +149,8 @@ enum rpi_firmware_property_tag {\n \tRPI_FIRMWARE_GET_DMA_CHANNELS =                       0x00060001,\n };\n \n+#define GET_DISPLAY_SETTINGS_PAYLOAD_SIZE 64\n+\n #if IS_ENABLED(CONFIG_RASPBERRYPI_FIRMWARE)\n int rpi_firmware_property(struct rpi_firmware *fw,\n \t\t\t  u32 tag, void *data, size_t len);\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0043-fbdev-add-FBIOCOPYAREA-ioctl.patch",
    "content": "From 6005247285065235845f233077bbeedb19a484c7 Mon Sep 17 00:00:00 2001\nFrom: Siarhei Siamashka <siarhei.siamashka@gmail.com>\nDate: Mon, 17 Jun 2013 13:32:11 +0300\nSubject: [PATCH] fbdev: add FBIOCOPYAREA ioctl\n\nBased on the patch authored by Ali Gholami Rudi at\n    https://lkml.org/lkml/2009/7/13/153\n\nProvide an ioctl for userspace applications, but only if this operation\nis hardware accelerated (otherwide it does not make any sense).\n\nSigned-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>\n\nbcm2708_fb: Add ioctl for reading gpu memory through dma\n\nvideo: bcm2708_fb: Add compat_ioctl support.\n\nWhen using a 64 bit kernel with 32 bit userspace we need\ncompat ioctl handling for FBIODMACOPY as one of the\nparameters is a pointer.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>\n---\n drivers/video/fbdev/bcm2708_fb.c | 170 ++++++++++++++++++++++++++++++-\n drivers/video/fbdev/core/fbmem.c |  35 +++++++\n include/uapi/linux/fb.h          |  12 +++\n 3 files changed, 213 insertions(+), 4 deletions(-)\n\n--- a/drivers/video/fbdev/bcm2708_fb.c\n+++ b/drivers/video/fbdev/bcm2708_fb.c\n@@ -32,8 +32,10 @@\n #include <linux/printk.h>\n #include <linux/console.h>\n #include <linux/debugfs.h>\n+#include <linux/uaccess.h>\n #include <linux/io.h>\n #include <linux/dma-mapping.h>\n+#include <linux/cred.h>\n #include <soc/bcm2835/raspberrypi-firmware.h>\n #include <linux/mutex.h>\n \n@@ -184,9 +186,6 @@ static int bcm2708_fb_debugfs_init(struc\n \n \tfb->debugfs_subdir = debugfs_create_dir(buf, fb->debugfs_dir);\n \n-\tdebugfs_create_regset32(\"stats\", 0444, fb->debugfs_dir,\n-\t\t\t\t&fb->stats.regset);\n-\n \tif (!fb->debugfs_subdir) {\n \t\tdev_warn(fb->fb.dev, \"%s: could not create debugfs entry %u\\n\",\n \t\t\t __func__, fb->display_settings.display_num);\n@@ -603,7 +602,110 @@ static int bcm2708_fb_pan_display(struct\n \treturn result;\n }\n \n-static int bcm2708_ioctl(struct fb_info *info, unsigned int cmd, unsigned long arg)\n+static void dma_memcpy(struct bcm2708_fb *fb, dma_addr_t dst, dma_addr_t src,\n+\t\t       int size)\n+{\n+\tstruct bcm2708_fb_dev *fbdev = fb->fbdev;\n+\tstruct bcm2708_dma_cb *cb = fbdev->cb_base;\n+\tint burst_size = (fbdev->dma_chan == 0) ? 8 : 2;\n+\n+\tcb->info = BCM2708_DMA_BURST(burst_size) | BCM2708_DMA_S_WIDTH |\n+\t\t   BCM2708_DMA_S_INC | BCM2708_DMA_D_WIDTH |\n+\t\t   BCM2708_DMA_D_INC;\n+\tcb->dst = dst;\n+\tcb->src = src;\n+\tcb->length = size;\n+\tcb->stride = 0;\n+\tcb->pad[0] = 0;\n+\tcb->pad[1] = 0;\n+\tcb->next = 0;\n+\n+\t// Not sure what to do if this gets a signal whilst waiting\n+\tif (mutex_lock_interruptible(&fbdev->dma_mutex))\n+\t\treturn;\n+\n+\tif (size < dma_busy_wait_threshold) {\n+\t\tbcm_dma_start(fbdev->dma_chan_base, fbdev->cb_handle);\n+\t\tbcm_dma_wait_idle(fbdev->dma_chan_base);\n+\t} else {\n+\t\tvoid __iomem *local_dma_chan = fbdev->dma_chan_base;\n+\n+\t\tcb->info |= BCM2708_DMA_INT_EN;\n+\t\tbcm_dma_start(fbdev->dma_chan_base, fbdev->cb_handle);\n+\t\twhile (bcm_dma_is_busy(local_dma_chan)) {\n+\t\t\twait_event_interruptible(fbdev->dma_waitq,\n+\t\t\t\t\t\t !bcm_dma_is_busy(local_dma_chan));\n+\t\t}\n+\t\tfbdev->dma_stats.dma_irqs++;\n+\t}\n+\tfbdev->dma_stats.dma_copies++;\n+\n+\tmutex_unlock(&fbdev->dma_mutex);\n+}\n+\n+/* address with no aliases */\n+#define INTALIAS_NORMAL(x) ((x) & ~0xc0000000)\n+/* cache coherent but non-allocating in L1 and L2 */\n+#define INTALIAS_L1L2_NONALLOCATING(x) (((x) & ~0xc0000000) | 0x80000000)\n+\n+static long vc_mem_copy(struct bcm2708_fb *fb, struct fb_dmacopy *ioparam)\n+{\n+\tsize_t size = PAGE_SIZE;\n+\tu32 *buf = NULL;\n+\tdma_addr_t bus_addr;\n+\tlong rc = 0;\n+\tsize_t offset;\n+\n+\t/* restrict this to root user */\n+\tif (!uid_eq(current_euid(), GLOBAL_ROOT_UID)) {\n+\t\trc = -EFAULT;\n+\t\tgoto out;\n+\t}\n+\n+\tif (!fb->gpu.base || !fb->gpu.length) {\n+\t\tpr_err(\"[%s]: Unable to determine gpu memory (%x,%x)\\n\",\n+\t\t       __func__, fb->gpu.base, fb->gpu.length);\n+\t\treturn -EFAULT;\n+\t}\n+\n+\tif (INTALIAS_NORMAL(ioparam->src) < fb->gpu.base ||\n+\t    INTALIAS_NORMAL(ioparam->src) >= fb->gpu.base + fb->gpu.length) {\n+\t\tpr_err(\"[%s]: Invalid memory access %x (%x-%x)\", __func__,\n+\t\t       INTALIAS_NORMAL(ioparam->src), fb->gpu.base,\n+\t\t       fb->gpu.base + fb->gpu.length);\n+\t\treturn -EFAULT;\n+\t}\n+\n+\tbuf = dma_alloc_coherent(fb->fb.device, PAGE_ALIGN(size), &bus_addr,\n+\t\t\t\t GFP_ATOMIC);\n+\tif (!buf) {\n+\t\tpr_err(\"[%s]: failed to dma_alloc_coherent(%zd)\\n\", __func__,\n+\t\t       size);\n+\t\trc = -ENOMEM;\n+\t\tgoto out;\n+\t}\n+\n+\tfor (offset = 0; offset < ioparam->length; offset += size) {\n+\t\tsize_t remaining = ioparam->length - offset;\n+\t\tsize_t s = min(size, remaining);\n+\t\tu8 *p = (u8 *)((uintptr_t)ioparam->src + offset);\n+\t\tu8 *q = (u8 *)ioparam->dst + offset;\n+\n+\t\tdma_memcpy(fb, bus_addr,\n+\t\t\t   INTALIAS_L1L2_NONALLOCATING((dma_addr_t)p), size);\n+\t\tif (copy_to_user(q, buf, s) != 0) {\n+\t\t\tpr_err(\"[%s]: failed to copy-to-user\\n\", __func__);\n+\t\t\trc = -EFAULT;\n+\t\t\tgoto out;\n+\t\t}\n+\t}\n+out:\n+\tif (buf)\n+\t\tdma_free_coherent(fb->fb.device, PAGE_ALIGN(size), buf,\n+\t\t\t\t  bus_addr);\n+\treturn rc;\n+}\n+\n static int bcm2708_ioctl(struct fb_info *info, unsigned int cmd,\n \t\t\t unsigned long arg)\n {\n@@ -619,6 +721,21 @@ static int bcm2708_ioctl(struct fb_info\n \t\t\t\t\t    RPI_FIRMWARE_FRAMEBUFFER_SET_VSYNC,\n \t\t\t\t\t    &dummy, sizeof(dummy));\n \t\tbreak;\n+\n+\tcase FBIODMACOPY:\n+\t{\n+\t\tstruct fb_dmacopy ioparam;\n+\t\t/* Get the parameter data.\n+\t\t */\n+\t\tif (copy_from_user\n+\t\t    (&ioparam, (void *)arg, sizeof(ioparam))) {\n+\t\t\tpr_err(\"[%s]: failed to copy-from-user\\n\", __func__);\n+\t\t\tret = -EFAULT;\n+\t\t\tbreak;\n+\t\t}\n+\t\tret = vc_mem_copy(fb, &ioparam);\n+\t\tbreak;\n+\t}\n \tdefault:\n \t\tdev_dbg(info->device, \"Unknown ioctl 0x%x\\n\", cmd);\n \t\treturn -ENOTTY;\n@@ -629,6 +746,48 @@ static int bcm2708_ioctl(struct fb_info\n \n \treturn ret;\n }\n+\n+#ifdef CONFIG_COMPAT\n+struct fb_dmacopy32 {\n+\tcompat_uptr_t dst;\n+\t__u32 src;\n+\t__u32 length;\n+};\n+\n+#define FBIODMACOPY32\t\t_IOW('z', 0x22, struct fb_dmacopy32)\n+\n+static int bcm2708_compat_ioctl(struct fb_info *info, unsigned int cmd,\n+\t\t\t\tunsigned long arg)\n+{\n+\tstruct bcm2708_fb *fb = to_bcm2708(info);\n+\tint ret;\n+\n+\tswitch (cmd) {\n+\tcase FBIODMACOPY32:\n+\t{\n+\t\tstruct fb_dmacopy32 param32;\n+\t\tstruct fb_dmacopy param;\n+\t\t/* Get the parameter data.\n+\t\t */\n+\t\tif (copy_from_user(&param32, (void *)arg, sizeof(param32))) {\n+\t\t\tpr_err(\"[%s]: failed to copy-from-user\\n\", __func__);\n+\t\t\tret = -EFAULT;\n+\t\t\tbreak;\n+\t\t}\n+\t\tparam.dst = compat_ptr(param32.dst);\n+\t\tparam.src = param32.src;\n+\t\tparam.length = param32.length;\n+\t\tret = vc_mem_copy(fb, &param);\n+\t\tbreak;\n+\t}\n+\tdefault:\n+\t\tret = bcm2708_ioctl(info, cmd, arg);\n+\t\tbreak;\n+\t}\n+\treturn ret;\n+}\n+#endif\n+\n static void bcm2708_fb_fillrect(struct fb_info *info,\n \t\t\t\tconst struct fb_fillrect *rect)\n {\n@@ -821,6 +980,9 @@ static struct fb_ops bcm2708_fb_ops = {\n \t.fb_imageblit = bcm2708_fb_imageblit,\n \t.fb_pan_display = bcm2708_fb_pan_display,\n \t.fb_ioctl = bcm2708_ioctl,\n+#ifdef CONFIG_COMPAT\n+\t.fb_compat_ioctl = bcm2708_compat_ioctl,\n+#endif\n };\n \n static int bcm2708_fb_register(struct bcm2708_fb *fb)\n--- a/drivers/video/fbdev/core/fbmem.c\n+++ b/drivers/video/fbdev/core/fbmem.c\n@@ -1085,6 +1085,30 @@ fb_blank(struct fb_info *info, int blank\n }\n EXPORT_SYMBOL(fb_blank);\n \n+static int fb_copyarea_user(struct fb_info *info,\n+\t\t\t    struct fb_copyarea *copy)\n+{\n+\tint ret = 0;\n+\tlock_fb_info(info);\n+\tif (copy->dx >= info->var.xres ||\n+\t    copy->sx >= info->var.xres ||\n+\t    copy->width > info->var.xres ||\n+\t    copy->dy >= info->var.yres ||\n+\t    copy->sy >= info->var.yres ||\n+\t    copy->height > info->var.yres ||\n+\t    copy->dx + copy->width > info->var.xres ||\n+\t    copy->sx + copy->width > info->var.xres ||\n+\t    copy->dy + copy->height > info->var.yres ||\n+\t    copy->sy + copy->height > info->var.yres) {\n+\t\tret = -EINVAL;\n+\t\tgoto out;\n+\t}\n+\tinfo->fbops->fb_copyarea(info, copy);\n+out:\n+\tunlock_fb_info(info);\n+\treturn ret;\n+}\n+\n static long do_fb_ioctl(struct fb_info *info, unsigned int cmd,\n \t\t\tunsigned long arg)\n {\n@@ -1093,6 +1117,7 @@ static long do_fb_ioctl(struct fb_info *\n \tstruct fb_fix_screeninfo fix;\n \tstruct fb_cmap cmap_from;\n \tstruct fb_cmap_user cmap;\n+\tstruct fb_copyarea copy;\n \tvoid __user *argp = (void __user *)arg;\n \tlong ret = 0;\n \n@@ -1168,6 +1193,15 @@ static long do_fb_ioctl(struct fb_info *\n \t\tunlock_fb_info(info);\n \t\tconsole_unlock();\n \t\tbreak;\n+\tcase FBIOCOPYAREA:\n+\t\tif (info->flags & FBINFO_HWACCEL_COPYAREA) {\n+\t\t\t/* only provide this ioctl if it is accelerated */\n+\t\t\tif (copy_from_user(&copy, argp, sizeof(copy)))\n+\t\t\t\treturn -EFAULT;\n+\t\t\tret = fb_copyarea_user(info, &copy);\n+\t\t\tbreak;\n+\t\t}\n+\t\t/* fall through */\n \tdefault:\n \t\tlock_fb_info(info);\n \t\tfb = info->fbops;\n@@ -1313,6 +1347,7 @@ static long fb_compat_ioctl(struct file\n \tcase FBIOPAN_DISPLAY:\n \tcase FBIOGET_CON2FBMAP:\n \tcase FBIOPUT_CON2FBMAP:\n+\tcase FBIOCOPYAREA:\n \t\targ = (unsigned long) compat_ptr(arg);\n \t\tfallthrough;\n \tcase FBIOBLANK:\n--- a/include/uapi/linux/fb.h\n+++ b/include/uapi/linux/fb.h\n@@ -35,6 +35,12 @@\n #define FBIOPUT_MODEINFO        0x4617\n #define FBIOGET_DISPINFO        0x4618\n #define FBIO_WAITFORVSYNC\t_IOW('F', 0x20, __u32)\n+/*\n+ * HACK: use 'z' in order not to clash with any other ioctl numbers which might\n+ * be concurrently added to the mainline kernel\n+ */\n+#define FBIOCOPYAREA\t\t_IOW('z', 0x21, struct fb_copyarea)\n+#define FBIODMACOPY \t\t_IOW('z', 0x22, struct fb_dmacopy)\n \n #define FB_TYPE_PACKED_PIXELS\t\t0\t/* Packed Pixels\t*/\n #define FB_TYPE_PLANES\t\t\t1\t/* Non interleaved planes */\n@@ -348,6 +354,12 @@ struct fb_copyarea {\n \t__u32 sy;\n };\n \n+struct fb_dmacopy {\n+\tvoid *dst;\n+\t__u32 src;\n+\t__u32 length;\n+};\n+\n struct fb_fillrect {\n \t__u32 dx;\t/* screen-relative */\n \t__u32 dy;\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0044-Speed-up-console-framebuffer-imageblit-function.patch",
    "content": "From cac14f80f1e41f9a977c3cd84b0b3b73740818f8 Mon Sep 17 00:00:00 2001\nFrom: Harm Hanemaaijer <fgenfb@yahoo.com>\nDate: Thu, 20 Jun 2013 20:21:39 +0200\nSubject: [PATCH] Speed up console framebuffer imageblit function\n\nEspecially on platforms with a slower CPU but a relatively high\nframebuffer fill bandwidth, like current ARM devices, the existing\nconsole monochrome imageblit function used to draw console text is\nsuboptimal for common pixel depths such as 16bpp and 32bpp. The existing\ncode is quite general and can deal with several pixel depths. By creating\nspecial case functions for 16bpp and 32bpp, by far the most common pixel\nformats used on modern systems, a significant speed-up is attained\nwhich can be readily felt on ARM-based devices like the Raspberry Pi\nand the Allwinner platform, but should help any platform using the\nfb layer.\n\nThe special case functions allow constant folding, eliminating a number\nof instructions including divide operations, and allow the use of an\nunrolled loop, eliminating instructions with a variable shift size,\nreducing source memory access instructions, and eliminating excessive\nbranching. These unrolled loops also allow much better code optimization\nby the C compiler. The code that selects which optimized variant is used\nis also simplified, eliminating integer divide instructions.\n\nThe speed-up, measured by timing 'cat file.txt' in the console, varies\nbetween 40% and 70%, when testing on the Raspberry Pi and Allwinner\nARM-based platforms, depending on font size and the pixel depth, with\nthe greater benefit for 32bpp.\n\nSigned-off-by: Harm Hanemaaijer <fgenfb@yahoo.com>\n---\n drivers/video/fbdev/core/cfbimgblt.c | 152 ++++++++++++++++++++++++++-\n 1 file changed, 147 insertions(+), 5 deletions(-)\n\n--- a/drivers/video/fbdev/core/cfbimgblt.c\n+++ b/drivers/video/fbdev/core/cfbimgblt.c\n@@ -28,6 +28,11 @@\n  *\n  *  Also need to add code to deal with cards endians that are different than\n  *  the native cpu endians. I also need to deal with MSB position in the word.\n+ *  Modified by Harm Hanemaaijer (fgenfb@yahoo.com) 2013:\n+ *  - Provide optimized versions of fast_imageblit for 16 and 32bpp that are\n+ *    significantly faster than the previous implementation.\n+ *  - Simplify the fast/slow_imageblit selection code, avoiding integer\n+ *    divides.\n  */\n #include <linux/module.h>\n #include <linux/string.h>\n@@ -262,6 +267,133 @@ static inline void fast_imageblit(const\n \t}\n }\t\n \t\n+/*\n+ * Optimized fast_imageblit for bpp == 16. ppw = 2, bit_mask = 3 folded\n+ * into the code, main loop unrolled.\n+ */\n+\n+static inline void fast_imageblit16(const struct fb_image *image,\n+\t\t\t\t    struct fb_info *p, u8 __iomem * dst1,\n+\t\t\t\t    u32 fgcolor, u32 bgcolor)\n+{\n+\tu32 fgx = fgcolor, bgx = bgcolor;\n+\tu32 spitch = (image->width + 7) / 8;\n+\tu32 end_mask, eorx;\n+\tconst char *s = image->data, *src;\n+\tu32 __iomem *dst;\n+\tconst u32 *tab = NULL;\n+\tint i, j, k;\n+\n+\ttab = fb_be_math(p) ? cfb_tab16_be : cfb_tab16_le;\n+\n+\tfgx <<= 16;\n+\tbgx <<= 16;\n+\tfgx |= fgcolor;\n+\tbgx |= bgcolor;\n+\n+\teorx = fgx ^ bgx;\n+\tk = image->width / 2;\n+\n+\tfor (i = image->height; i--;) {\n+\t\tdst = (u32 __iomem *) dst1;\n+\t\tsrc = s;\n+\n+\t\tj = k;\n+\t\twhile (j >= 4) {\n+\t\t\tu8 bits = *src;\n+\t\t\tend_mask = tab[(bits >> 6) & 3];\n+\t\t\tFB_WRITEL((end_mask & eorx) ^ bgx, dst++);\n+\t\t\tend_mask = tab[(bits >> 4) & 3];\n+\t\t\tFB_WRITEL((end_mask & eorx) ^ bgx, dst++);\n+\t\t\tend_mask = tab[(bits >> 2) & 3];\n+\t\t\tFB_WRITEL((end_mask & eorx) ^ bgx, dst++);\n+\t\t\tend_mask = tab[bits & 3];\n+\t\t\tFB_WRITEL((end_mask & eorx) ^ bgx, dst++);\n+\t\t\tsrc++;\n+\t\t\tj -= 4;\n+\t\t}\n+\t\tif (j != 0) {\n+\t\t\tu8 bits = *src;\n+\t\t\tend_mask = tab[(bits >> 6) & 3];\n+\t\t\tFB_WRITEL((end_mask & eorx) ^ bgx, dst++);\n+\t\t\tif (j >= 2) {\n+\t\t\t\tend_mask = tab[(bits >> 4) & 3];\n+\t\t\t\tFB_WRITEL((end_mask & eorx) ^ bgx, dst++);\n+\t\t\t\tif (j == 3) {\n+\t\t\t\t\tend_mask = tab[(bits >> 2) & 3];\n+\t\t\t\t\tFB_WRITEL((end_mask & eorx) ^ bgx, dst);\n+\t\t\t\t}\n+\t\t\t}\n+\t\t}\n+\t\tdst1 += p->fix.line_length;\n+\t\ts += spitch;\n+\t}\n+}\n+\n+/*\n+ * Optimized fast_imageblit for bpp == 32. ppw = 1, bit_mask = 1 folded\n+ * into the code, main loop unrolled.\n+ */\n+\n+static inline void fast_imageblit32(const struct fb_image *image,\n+\t\t\t\t    struct fb_info *p, u8 __iomem * dst1,\n+\t\t\t\t    u32 fgcolor, u32 bgcolor)\n+{\n+\tu32 fgx = fgcolor, bgx = bgcolor;\n+\tu32 spitch = (image->width + 7) / 8;\n+\tu32 end_mask, eorx;\n+\tconst char *s = image->data, *src;\n+\tu32 __iomem *dst;\n+\tconst u32 *tab = NULL;\n+\tint i, j, k;\n+\n+\ttab = cfb_tab32;\n+\n+\teorx = fgx ^ bgx;\n+\tk = image->width;\n+\n+\tfor (i = image->height; i--;) {\n+\t\tdst = (u32 __iomem *) dst1;\n+\t\tsrc = s;\n+\n+\t\tj = k;\n+\t\twhile (j >= 8) {\n+\t\t\tu8 bits = *src;\n+\t\t\tend_mask = tab[(bits >> 7) & 1];\n+\t\t\tFB_WRITEL((end_mask & eorx) ^ bgx, dst++);\n+\t\t\tend_mask = tab[(bits >> 6) & 1];\n+\t\t\tFB_WRITEL((end_mask & eorx) ^ bgx, dst++);\n+\t\t\tend_mask = tab[(bits >> 5) & 1];\n+\t\t\tFB_WRITEL((end_mask & eorx) ^ bgx, dst++);\n+\t\t\tend_mask = tab[(bits >> 4) & 1];\n+\t\t\tFB_WRITEL((end_mask & eorx) ^ bgx, dst++);\n+\t\t\tend_mask = tab[(bits >> 3) & 1];\n+\t\t\tFB_WRITEL((end_mask & eorx) ^ bgx, dst++);\n+\t\t\tend_mask = tab[(bits >> 2) & 1];\n+\t\t\tFB_WRITEL((end_mask & eorx) ^ bgx, dst++);\n+\t\t\tend_mask = tab[(bits >> 1) & 1];\n+\t\t\tFB_WRITEL((end_mask & eorx) ^ bgx, dst++);\n+\t\t\tend_mask = tab[bits & 1];\n+\t\t\tFB_WRITEL((end_mask & eorx) ^ bgx, dst++);\n+\t\t\tsrc++;\n+\t\t\tj -= 8;\n+\t\t}\n+\t\tif (j != 0) {\n+\t\t\tu32 bits = (u32) * src;\n+\t\t\twhile (j > 1) {\n+\t\t\t\tend_mask = tab[(bits >> 7) & 1];\n+\t\t\t\tFB_WRITEL((end_mask & eorx) ^ bgx, dst++);\n+\t\t\t\tbits <<= 1;\n+\t\t\t\tj--;\n+\t\t\t}\n+\t\t\tend_mask = tab[(bits >> 7) & 1];\n+\t\t\tFB_WRITEL((end_mask & eorx) ^ bgx, dst);\n+\t\t}\n+\t\tdst1 += p->fix.line_length;\n+\t\ts += spitch;\n+\t}\n+}\n+\n void cfb_imageblit(struct fb_info *p, const struct fb_image *image)\n {\n \tu32 fgcolor, bgcolor, start_index, bitstart, pitch_index = 0;\n@@ -294,11 +426,21 @@ void cfb_imageblit(struct fb_info *p, co\n \t\t\tbgcolor = image->bg_color;\n \t\t}\t\n \t\t\n-\t\tif (32 % bpp == 0 && !start_index && !pitch_index && \n-\t\t    ((width & (32/bpp-1)) == 0) &&\n-\t\t    bpp >= 8 && bpp <= 32) \t\t\t\n-\t\t\tfast_imageblit(image, p, dst1, fgcolor, bgcolor);\n-\t\telse \n+\t\tif (!start_index && !pitch_index) {\n+\t\t\tif (bpp == 32)\n+\t\t\t\tfast_imageblit32(image, p, dst1, fgcolor,\n+\t\t\t\t\t\t bgcolor);\n+\t\t\telse if (bpp == 16 && (width & 1) == 0)\n+\t\t\t\tfast_imageblit16(image, p, dst1, fgcolor,\n+\t\t\t\t\t\t bgcolor);\n+\t\t\telse if (bpp == 8 && (width & 3) == 0)\n+\t\t\t\tfast_imageblit(image, p, dst1, fgcolor,\n+\t\t\t\t\t       bgcolor);\n+\t\t\telse\n+\t\t\t\tslow_imageblit(image, p, dst1, fgcolor,\n+\t\t\t\t\t       bgcolor,\n+\t\t\t\t\t       start_index, pitch_index);\n+\t\t} else\n \t\t\tslow_imageblit(image, p, dst1, fgcolor, bgcolor,\n \t\t\t\t\tstart_index, pitch_index);\n \t} else\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0045-dmaengine-Add-support-for-BCM2708.patch",
    "content": "From 9ac0f4ce3beaad7700af1e771776d12ae7813f97 Mon Sep 17 00:00:00 2001\nFrom: Florian Meier <florian.meier@koalo.de>\nDate: Fri, 22 Nov 2013 14:22:53 +0100\nSubject: [PATCH] dmaengine: Add support for BCM2708\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nAdd support for DMA controller of BCM2708 as used in the Raspberry Pi.\nCurrently it only supports cyclic DMA.\n\nSigned-off-by: Florian Meier <florian.meier@koalo.de>\n\ndmaengine: expand functionality by supporting scatter/gather transfers sdhci-bcm2708 and dma.c: fix for LITE channels\n\nDMA: fix cyclic LITE length overflow bug\n\ndmaengine: bcm2708: Remove chancnt affectations\n\nMirror bcm2835-dma.c commit 9eba5536a7434c69d8c185d4bd1c70734d92287d:\nchancnt is already filled by dma_async_device_register, which uses the channel\nlist to know how much channels there is.\n\nSince it's already filled, we can safely remove it from the drivers' probe\nfunction.\n\nSigned-off-by: Noralf Trønnes <noralf@tronnes.org>\n\ndmaengine: bcm2708: overwrite dreq only if it is not set\n\ndreq is set when the DMA channel is fetched from Device Tree.\nslave_id is set using dmaengine_slave_config().\nOnly overwrite dreq with slave_id if it is not set.\n\ndreq/slave_id in the cyclic DMA case is not touched, because I don't\nhave hardware to test with.\n\nSigned-off-by: Noralf Trønnes <noralf@tronnes.org>\n\ndmaengine: bcm2708: do device registration in the board file\n\nDon't register the device in the driver. Do it in the board file.\n\nSigned-off-by: Noralf Trønnes <noralf@tronnes.org>\n\ndmaengine: bcm2708: don't restrict DT support to ARCH_BCM2835\n\nBoth ARCH_BCM2835 and ARCH_BCM270x are built with OF now.\nAdd Device Tree support to the non ARCH_BCM2835 case.\nUse the same driver name regardless of architecture.\n\nSigned-off-by: Noralf Trønnes <noralf@tronnes.org>\n\nBCM270x_DT: add bcm2835-dma entry\n\nAdd Device Tree entry for bcm2835-dma.\nThe entry doesn't contain any resources since they are handled\nby the arch/arm/mach-bcm270x/dma.c driver.\nIn non-DT mode, don't add the device in the board file.\n\nSigned-off-by: Noralf Trønnes <noralf@tronnes.org>\n\nbcm2708-dmaengine: Add debug options\n\nBCM270x: Add memory and irq resources to dmaengine device and DT\n\nPrepare for merging of the legacy DMA API arch driver dma.c\nwith bcm2708-dmaengine by adding memory and irq resources both\nto platform file device and Device Tree node.\nDon't use BCM_DMAMAN_DRIVER_NAME so we don't have to include mach/dma.h\n\nSigned-off-by: Noralf Trønnes <noralf@tronnes.org>\n\ndmaengine: bcm2708: Merge with arch dma.c driver and disable dma.c\n\nMerge the legacy DMA API driver with bcm2708-dmaengine.\nThis is done so we can use bcm2708_fb on ARCH_BCM2835 (mailbox\ndriver is also needed).\n\nChanges to the dma.c code:\n- Use BIT() macro.\n- Cutdown some comments to one line.\n- Add mutex to vc_dmaman and use this, since the dev lock is locked\n  during probing of the engine part.\n- Add global g_dmaman variable since drvdata is used by the engine part.\n- Restructure for readability:\n  vc_dmaman_chan_alloc()\n  vc_dmaman_chan_free()\n  bcm_dma_chan_free()\n- Restructure bcm_dma_chan_alloc() to simplify error handling.\n- Use device irq resources instead of hardcoded bcm_dma_irqs table.\n- Remove dev_dmaman_register() and code it directly.\n- Remove dev_dmaman_deregister() and code it directly.\n- Simplify bcm_dmaman_probe() using devm_* functions.\n- Get dmachans from DT if available.\n- Keep 'dma.dmachans' module argument name for backwards compatibility.\n\nMake it available on ARCH_BCM2835 as well.\n\nSigned-off-by: Noralf Trønnes <noralf@tronnes.org>\n\ndmaengine: bcm2708: set residue_granularity field\n\nbcm2708-dmaengine supports residue reporting at burst level\nbut didn't report this via the residue_granularity field.\n\nWithout this field set properly we get playback issues with I2S cards.\n\ndmaengine: bcm2708-dmaengine: Fix memory leak when stopping a running transfer\n\nbcm2708-dmaengine: Use more DMA channels (but not 12)\n\n1) Only the bcm2708_fb drivers uses the legacy DMA API, and\nit requires a BULK-capable channel, so all other types\n(FAST, NORMAL and LITE) can be made available to the regular\nDMA API.\n\n2) DMA channels 11-14 share an interrupt. The driver can't\nhandle this, so don't use channels 12-14 (12 was used, probably\nbecause it appears to have an interrupt, but in reality that\ninterrupt is for activity on ANY channel). This may explain\na lockup encountered when running out of DMA channels.\n\nThe combined effect of this patch is to leave 7 DMA channels\navailable + channel 0 for bcm2708_fb via the legacy API.\n\nSee: https://github.com/raspberrypi/linux/issues/1110\n     https://github.com/raspberrypi/linux/issues/1108\n\ndmaengine: bcm2708: Make legacy API available for bcm2835-dma\n\nbcm2708_fb uses the legacy DMA API, so in order to start using\nbcm2835-dma, bcm2835-dma has to support the legacy API. Make this\npossible by exporting bcm_dmaman_probe() and bcm_dmaman_remove().\n\nSigned-off-by: Noralf Trønnes <noralf@tronnes.org>\n\ndmaengine: bcm2708: Change DT compatible string\n\nBoth bcm2835-dma and bcm2708-dmaengine have the same compatible string.\nSo change compatible to \"brcm,bcm2708-dma\".\n\nSigned-off-by: Noralf Trønnes <noralf@tronnes.org>\n\ndmaengine: bcm2708: Remove driver but keep legacy API\n\nDropping non-DT support means we don't need this driver,\nbut we still need the legacy DMA API.\n\nSigned-off-by: Noralf Trønnes <noralf@tronnes.org>\n\nbcm2708-dmaengine - Fix arm64 portability/build issues\n\ndma-bcm2708: Fix module compilation of CONFIG_DMA_BCM2708\n\nbcm2708-dmaengine.c defines functions like bcm_dma_start which are\ndefined as well in dma-bcm2708.h as inline versions when\nCONFIG_DMA_BCM2708 is not defined. This works fine when\nCONFIG_DMA_BCM2708 is built in, but when it is selected as module build\nfails with redefinition errors because in the build system when\nCONFIG_DMA_BCM2708 is selected as module, the macro becomes\nCONFIG_DMA_BCM2708_MODULE.\n\nThis patch makes the header use CONFIG_DMA_BCM2708_MODULE too when\navailable.\n\nFixes https://github.com/raspberrypi/linux/issues/2056\n\nSigned-off-by: Andrei Gherzan <andrei@gherzan.com>\n---\n drivers/dma/Kconfig                       |   6 +-\n drivers/dma/Makefile                      |   1 +\n drivers/dma/bcm2708-dmaengine.c           | 281 ++++++++++++++++++++++\n include/linux/platform_data/dma-bcm2708.h | 143 +++++++++++\n 4 files changed, 430 insertions(+), 1 deletion(-)\n create mode 100644 drivers/dma/bcm2708-dmaengine.c\n create mode 100644 include/linux/platform_data/dma-bcm2708.h\n\n--- a/drivers/dma/Kconfig\n+++ b/drivers/dma/Kconfig\n@@ -134,7 +134,7 @@ config COH901318\n \n config DMA_BCM2835\n \ttristate \"BCM2835 DMA engine support\"\n-\tdepends on ARCH_BCM2835 || ARCH_BCM2708 || ARCH_BCM2709\n+\tdepends on ARCH_BCM2835\n \tselect DMA_ENGINE\n \tselect DMA_VIRTUAL_CHANNELS\n \n@@ -652,6 +652,10 @@ config UNIPHIER_XDMAC\n \t  UniPhier platform. This DMA controller can transfer data from\n \t  memory to memory, memory to peripheral and peripheral to memory.\n \n+config DMA_BCM2708\n+\ttristate \"BCM2708 DMA legacy API support\"\n+\tdepends on DMA_BCM2835\n+\n config XGENE_DMA\n \ttristate \"APM X-Gene DMA support\"\n \tdepends on ARCH_XGENE || COMPILE_TEST\n--- a/drivers/dma/Makefile\n+++ b/drivers/dma/Makefile\n@@ -21,6 +21,7 @@ obj-$(CONFIG_AT_XDMAC) += at_xdmac.o\n obj-$(CONFIG_AXI_DMAC) += dma-axi-dmac.o\n obj-$(CONFIG_BCM_SBA_RAID) += bcm-sba-raid.o\n obj-$(CONFIG_COH901318) += coh901318.o coh901318_lli.o\n+obj-$(CONFIG_DMA_BCM2708) += bcm2708-dmaengine.o\n obj-$(CONFIG_DMA_BCM2835) += bcm2835-dma.o\n obj-$(CONFIG_DMA_JZ4780) += dma-jz4780.o\n obj-$(CONFIG_DMA_SA11X0) += sa11x0-dma.o\n--- /dev/null\n+++ b/drivers/dma/bcm2708-dmaengine.c\n@@ -0,0 +1,281 @@\n+/*\n+ * BCM2708 legacy DMA API\n+ *\n+ * This program is free software; you can redistribute it and/or modify\n+ * it under the terms of the GNU General Public License as published by\n+ * the Free Software Foundation; either version 2 of the License, or\n+ * (at your option) any later version.\n+ *\n+ * This program is distributed in the hope that it will be useful,\n+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\n+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n+ * GNU General Public License for more details.\n+ */\n+\n+#include <linux/init.h>\n+#include <linux/interrupt.h>\n+#include <linux/list.h>\n+#include <linux/module.h>\n+#include <linux/platform_data/dma-bcm2708.h>\n+#include <linux/platform_device.h>\n+#include <linux/slab.h>\n+#include <linux/io.h>\n+#include <linux/spinlock.h>\n+\n+#include \"virt-dma.h\"\n+\n+#define CACHE_LINE_MASK 31\n+#define DEFAULT_DMACHAN_BITMAP 0x10  /* channel 4 only */\n+\n+/* valid only for channels 0 - 14, 15 has its own base address */\n+#define BCM2708_DMA_CHAN(n)\t((n) << 8) /* base address */\n+#define BCM2708_DMA_CHANIO(dma_base, n) \\\n+\t((void __iomem *)((char *)(dma_base) + BCM2708_DMA_CHAN(n)))\n+\n+struct vc_dmaman {\n+\tvoid __iomem *dma_base;\n+\tu32 chan_available; /* bitmap of available channels */\n+\tu32 has_feature[BCM_DMA_FEATURE_COUNT]; /* bitmap of feature presence */\n+\tstruct mutex lock;\n+};\n+\n+static struct device *dmaman_dev;\t/* we assume there's only one! */\n+static struct vc_dmaman *g_dmaman;\t/* DMA manager */\n+\n+/* DMA Auxiliary Functions */\n+\n+/* A DMA buffer on an arbitrary boundary may separate a cache line into a\n+   section inside the DMA buffer and another section outside it.\n+   Even if we flush DMA buffers from the cache there is always the chance that\n+   during a DMA someone will access the part of a cache line that is outside\n+   the DMA buffer - which will then bring in unwelcome data.\n+   Without being able to dictate our own buffer pools we must insist that\n+   DMA buffers consist of a whole number of cache lines.\n+*/\n+extern int bcm_sg_suitable_for_dma(struct scatterlist *sg_ptr, int sg_len)\n+{\n+\tint i;\n+\n+\tfor (i = 0; i < sg_len; i++) {\n+\t\tif (sg_ptr[i].offset & CACHE_LINE_MASK ||\n+\t\t    sg_ptr[i].length & CACHE_LINE_MASK)\n+\t\t\treturn 0;\n+\t}\n+\n+\treturn 1;\n+}\n+EXPORT_SYMBOL_GPL(bcm_sg_suitable_for_dma);\n+\n+extern void bcm_dma_start(void __iomem *dma_chan_base,\n+\t\t\t  dma_addr_t control_block)\n+{\n+\tdsb(sy);\t/* ARM data synchronization (push) operation */\n+\n+\twritel(control_block, dma_chan_base + BCM2708_DMA_ADDR);\n+\twritel(BCM2708_DMA_ACTIVE, dma_chan_base + BCM2708_DMA_CS);\n+}\n+EXPORT_SYMBOL_GPL(bcm_dma_start);\n+\n+extern void bcm_dma_wait_idle(void __iomem *dma_chan_base)\n+{\n+\tdsb(sy);\n+\n+\t/* ugly busy wait only option for now */\n+\twhile (readl(dma_chan_base + BCM2708_DMA_CS) & BCM2708_DMA_ACTIVE)\n+\t\tcpu_relax();\n+}\n+EXPORT_SYMBOL_GPL(bcm_dma_wait_idle);\n+\n+extern bool bcm_dma_is_busy(void __iomem *dma_chan_base)\n+{\n+\tdsb(sy);\n+\n+\treturn readl(dma_chan_base + BCM2708_DMA_CS) & BCM2708_DMA_ACTIVE;\n+}\n+EXPORT_SYMBOL_GPL(bcm_dma_is_busy);\n+\n+/* Complete an ongoing DMA (assuming its results are to be ignored)\n+   Does nothing if there is no DMA in progress.\n+   This routine waits for the current AXI transfer to complete before\n+   terminating the current DMA. If the current transfer is hung on a DREQ used\n+   by an uncooperative peripheral the AXI transfer may never complete.\tIn this\n+   case the routine times out and return a non-zero error code.\n+   Use of this routine doesn't guarantee that the ongoing or aborted DMA\n+   does not produce an interrupt.\n+*/\n+extern int bcm_dma_abort(void __iomem *dma_chan_base)\n+{\n+\tunsigned long int cs;\n+\tint rc = 0;\n+\n+\tcs = readl(dma_chan_base + BCM2708_DMA_CS);\n+\n+\tif (BCM2708_DMA_ACTIVE & cs) {\n+\t\tlong int timeout = 10000;\n+\n+\t\t/* write 0 to the active bit - pause the DMA */\n+\t\twritel(0, dma_chan_base + BCM2708_DMA_CS);\n+\n+\t\t/* wait for any current AXI transfer to complete */\n+\t\twhile (0 != (cs & BCM2708_DMA_ISPAUSED) && --timeout >= 0)\n+\t\t\tcs = readl(dma_chan_base + BCM2708_DMA_CS);\n+\n+\t\tif (0 != (cs & BCM2708_DMA_ISPAUSED)) {\n+\t\t\t/* we'll un-pause when we set of our next DMA */\n+\t\t\trc = -ETIMEDOUT;\n+\n+\t\t} else if (BCM2708_DMA_ACTIVE & cs) {\n+\t\t\t/* terminate the control block chain */\n+\t\t\twritel(0, dma_chan_base + BCM2708_DMA_NEXTCB);\n+\n+\t\t\t/* abort the whole DMA */\n+\t\t\twritel(BCM2708_DMA_ABORT | BCM2708_DMA_ACTIVE,\n+\t\t\t       dma_chan_base + BCM2708_DMA_CS);\n+\t\t}\n+\t}\n+\n+\treturn rc;\n+}\n+EXPORT_SYMBOL_GPL(bcm_dma_abort);\n+\n+ /* DMA Manager Device Methods */\n+\n+static void vc_dmaman_init(struct vc_dmaman *dmaman, void __iomem *dma_base,\n+\t\t\t   u32 chans_available)\n+{\n+\tdmaman->dma_base = dma_base;\n+\tdmaman->chan_available = chans_available;\n+\tdmaman->has_feature[BCM_DMA_FEATURE_FAST_ORD] = 0x0c;  /* 2 & 3 */\n+\tdmaman->has_feature[BCM_DMA_FEATURE_BULK_ORD] = 0x01;  /* 0 */\n+\tdmaman->has_feature[BCM_DMA_FEATURE_NORMAL_ORD] = 0xfe;  /* 1 to 7 */\n+\tdmaman->has_feature[BCM_DMA_FEATURE_LITE_ORD] = 0x7f00;  /* 8 to 14 */\n+}\n+\n+static int vc_dmaman_chan_alloc(struct vc_dmaman *dmaman,\n+\t\t\t\tunsigned required_feature_set)\n+{\n+\tu32 chans;\n+\tint chan = 0;\n+\tint feature;\n+\n+\tchans = dmaman->chan_available;\n+\tfor (feature = 0; feature < BCM_DMA_FEATURE_COUNT; feature++)\n+\t\t/* select the subset of available channels with the desired\n+\t\t   features */\n+\t\tif (required_feature_set & (1 << feature))\n+\t\t\tchans &= dmaman->has_feature[feature];\n+\n+\tif (!chans)\n+\t\treturn -ENOENT;\n+\n+\t/* return the ordinal of the first channel in the bitmap */\n+\twhile (chans != 0 && (chans & 1) == 0) {\n+\t\tchans >>= 1;\n+\t\tchan++;\n+\t}\n+\t/* claim the channel */\n+\tdmaman->chan_available &= ~(1 << chan);\n+\n+\treturn chan;\n+}\n+\n+static int vc_dmaman_chan_free(struct vc_dmaman *dmaman, int chan)\n+{\n+\tif (chan < 0)\n+\t\treturn -EINVAL;\n+\n+\tif ((1 << chan) & dmaman->chan_available)\n+\t\treturn -EIDRM;\n+\n+\tdmaman->chan_available |= (1 << chan);\n+\n+\treturn 0;\n+}\n+\n+/* DMA Manager Monitor */\n+\n+extern int bcm_dma_chan_alloc(unsigned required_feature_set,\n+\t\t\t      void __iomem **out_dma_base, int *out_dma_irq)\n+{\n+\tstruct vc_dmaman *dmaman = g_dmaman;\n+\tstruct platform_device *pdev = to_platform_device(dmaman_dev);\n+\tstruct resource *r;\n+\tint chan;\n+\n+\tif (!dmaman_dev)\n+\t\treturn -ENODEV;\n+\n+\tmutex_lock(&dmaman->lock);\n+\tchan = vc_dmaman_chan_alloc(dmaman, required_feature_set);\n+\tif (chan < 0)\n+\t\tgoto out;\n+\n+\tr = platform_get_resource(pdev, IORESOURCE_IRQ, (unsigned int)chan);\n+\tif (!r) {\n+\t\tdev_err(dmaman_dev, \"failed to get irq for DMA channel %d\\n\",\n+\t\t\tchan);\n+\t\tvc_dmaman_chan_free(dmaman, chan);\n+\t\tchan = -ENOENT;\n+\t\tgoto out;\n+\t}\n+\n+\t*out_dma_base = BCM2708_DMA_CHANIO(dmaman->dma_base, chan);\n+\t*out_dma_irq = r->start;\n+\tdev_dbg(dmaman_dev,\n+\t\t\"Legacy API allocated channel=%d, base=%p, irq=%i\\n\",\n+\t\tchan, *out_dma_base, *out_dma_irq);\n+\n+out:\n+\tmutex_unlock(&dmaman->lock);\n+\n+\treturn chan;\n+}\n+EXPORT_SYMBOL_GPL(bcm_dma_chan_alloc);\n+\n+extern int bcm_dma_chan_free(int channel)\n+{\n+\tstruct vc_dmaman *dmaman = g_dmaman;\n+\tint rc;\n+\n+\tif (!dmaman_dev)\n+\t\treturn -ENODEV;\n+\n+\tmutex_lock(&dmaman->lock);\n+\trc = vc_dmaman_chan_free(dmaman, channel);\n+\tmutex_unlock(&dmaman->lock);\n+\n+\treturn rc;\n+}\n+EXPORT_SYMBOL_GPL(bcm_dma_chan_free);\n+\n+int bcm_dmaman_probe(struct platform_device *pdev, void __iomem *base,\n+\t\t     u32 chans_available)\n+{\n+\tstruct device *dev = &pdev->dev;\n+\tstruct vc_dmaman *dmaman;\n+\n+\tdmaman = devm_kzalloc(dev, sizeof(*dmaman), GFP_KERNEL);\n+\tif (!dmaman)\n+\t\treturn -ENOMEM;\n+\n+\tmutex_init(&dmaman->lock);\n+\tvc_dmaman_init(dmaman, base, chans_available);\n+\tg_dmaman = dmaman;\n+\tdmaman_dev = dev;\n+\n+\tdev_info(dev, \"DMA legacy API manager, dmachans=0x%x\\n\",\n+\t\t chans_available);\n+\n+\treturn 0;\n+}\n+EXPORT_SYMBOL(bcm_dmaman_probe);\n+\n+int bcm_dmaman_remove(struct platform_device *pdev)\n+{\n+\tdmaman_dev = NULL;\n+\n+\treturn 0;\n+}\n+EXPORT_SYMBOL(bcm_dmaman_remove);\n+\n+MODULE_LICENSE(\"GPL\");\n--- /dev/null\n+++ b/include/linux/platform_data/dma-bcm2708.h\n@@ -0,0 +1,143 @@\n+/*\n+ *  Copyright (C) 2010 Broadcom\n+ *\n+ * This program is free software; you can redistribute it and/or modify\n+ * it under the terms of the GNU General Public License version 2 as\n+ * published by the Free Software Foundation.\n+ */\n+\n+#ifndef _PLAT_BCM2708_DMA_H\n+#define _PLAT_BCM2708_DMA_H\n+\n+/* DMA CS Control and Status bits */\n+#define BCM2708_DMA_ACTIVE\tBIT(0)\n+#define BCM2708_DMA_INT\t\tBIT(2)\n+#define BCM2708_DMA_ISPAUSED\tBIT(4)  /* Pause requested or not active */\n+#define BCM2708_DMA_ISHELD\tBIT(5)  /* Is held by DREQ flow control */\n+#define BCM2708_DMA_ERR\t\tBIT(8)\n+#define BCM2708_DMA_ABORT\tBIT(30) /* stop current CB, go to next, WO */\n+#define BCM2708_DMA_RESET\tBIT(31) /* WO, self clearing */\n+\n+/* DMA control block \"info\" field bits */\n+#define BCM2708_DMA_INT_EN\tBIT(0)\n+#define BCM2708_DMA_TDMODE\tBIT(1)\n+#define BCM2708_DMA_WAIT_RESP\tBIT(3)\n+#define BCM2708_DMA_D_INC\tBIT(4)\n+#define BCM2708_DMA_D_WIDTH\tBIT(5)\n+#define BCM2708_DMA_D_DREQ\tBIT(6)\n+#define BCM2708_DMA_S_INC\tBIT(8)\n+#define BCM2708_DMA_S_WIDTH\tBIT(9)\n+#define BCM2708_DMA_S_DREQ\tBIT(10)\n+\n+#define\tBCM2708_DMA_BURST(x)\t(((x) & 0xf) << 12)\n+#define\tBCM2708_DMA_PER_MAP(x)\t((x) << 16)\n+#define\tBCM2708_DMA_WAITS(x)\t(((x) & 0x1f) << 21)\n+\n+#define BCM2708_DMA_DREQ_EMMC\t11\n+#define BCM2708_DMA_DREQ_SDHOST\t13\n+\n+#define BCM2708_DMA_CS\t\t0x00 /* Control and Status */\n+#define BCM2708_DMA_ADDR\t0x04\n+/* the current control block appears in the following registers - read only */\n+#define BCM2708_DMA_INFO\t0x08\n+#define BCM2708_DMA_SOURCE_AD\t0x0c\n+#define BCM2708_DMA_DEST_AD\t0x10\n+#define BCM2708_DMA_NEXTCB\t0x1C\n+#define BCM2708_DMA_DEBUG\t0x20\n+\n+#define BCM2708_DMA4_CS\t\t(BCM2708_DMA_CHAN(4) + BCM2708_DMA_CS)\n+#define BCM2708_DMA4_ADDR\t(BCM2708_DMA_CHAN(4) + BCM2708_DMA_ADDR)\n+\n+#define BCM2708_DMA_TDMODE_LEN(w, h) ((h) << 16 | (w))\n+\n+/* When listing features we can ask for when allocating DMA channels give\n+   those with higher priority smaller ordinal numbers */\n+#define BCM_DMA_FEATURE_FAST_ORD\t0\n+#define BCM_DMA_FEATURE_BULK_ORD\t1\n+#define BCM_DMA_FEATURE_NORMAL_ORD\t2\n+#define BCM_DMA_FEATURE_LITE_ORD\t3\n+#define BCM_DMA_FEATURE_FAST\t\tBIT(BCM_DMA_FEATURE_FAST_ORD)\n+#define BCM_DMA_FEATURE_BULK\t\tBIT(BCM_DMA_FEATURE_BULK_ORD)\n+#define BCM_DMA_FEATURE_NORMAL\t\tBIT(BCM_DMA_FEATURE_NORMAL_ORD)\n+#define BCM_DMA_FEATURE_LITE\t\tBIT(BCM_DMA_FEATURE_LITE_ORD)\n+#define BCM_DMA_FEATURE_COUNT\t\t4\n+\n+struct bcm2708_dma_cb {\n+\tu32 info;\n+\tu32 src;\n+\tu32 dst;\n+\tu32 length;\n+\tu32 stride;\n+\tu32 next;\n+\tu32 pad[2];\n+};\n+\n+struct scatterlist;\n+struct platform_device;\n+\n+#if defined(CONFIG_DMA_BCM2708) || defined(CONFIG_DMA_BCM2708_MODULE)\n+\n+int bcm_sg_suitable_for_dma(struct scatterlist *sg_ptr, int sg_len);\n+void bcm_dma_start(void __iomem *dma_chan_base, dma_addr_t control_block);\n+void bcm_dma_wait_idle(void __iomem *dma_chan_base);\n+bool bcm_dma_is_busy(void __iomem *dma_chan_base);\n+int bcm_dma_abort(void __iomem *dma_chan_base);\n+\n+/* return channel no or -ve error */\n+int bcm_dma_chan_alloc(unsigned preferred_feature_set,\n+\t\t       void __iomem **out_dma_base, int *out_dma_irq);\n+int bcm_dma_chan_free(int channel);\n+\n+int bcm_dmaman_probe(struct platform_device *pdev, void __iomem *base,\n+\t\t     u32 chans_available);\n+int bcm_dmaman_remove(struct platform_device *pdev);\n+\n+#else /* CONFIG_DMA_BCM2708 */\n+\n+static inline int bcm_sg_suitable_for_dma(struct scatterlist *sg_ptr,\n+\t\t\t\t\t  int sg_len)\n+{\n+\treturn 0;\n+}\n+\n+static inline void bcm_dma_start(void __iomem *dma_chan_base,\n+\t\t\t\t dma_addr_t control_block) { }\n+\n+static inline void bcm_dma_wait_idle(void __iomem *dma_chan_base) { }\n+\n+static inline bool bcm_dma_is_busy(void __iomem *dma_chan_base)\n+{\n+\treturn false;\n+}\n+\n+static inline int bcm_dma_abort(void __iomem *dma_chan_base)\n+{\n+\treturn -EINVAL;\n+}\n+\n+static inline int bcm_dma_chan_alloc(unsigned preferred_feature_set,\n+\t\t\t\t     void __iomem **out_dma_base,\n+\t\t\t\t     int *out_dma_irq)\n+{\n+\treturn -EINVAL;\n+}\n+\n+static inline int bcm_dma_chan_free(int channel)\n+{\n+\treturn -EINVAL;\n+}\n+\n+static inline int bcm_dmaman_probe(struct platform_device *pdev,\n+\t\t\t\t   void __iomem *base, u32 chans_available)\n+{\n+\treturn 0;\n+}\n+\n+static inline int bcm_dmaman_remove(struct platform_device *pdev)\n+{\n+\treturn 0;\n+}\n+\n+#endif /* CONFIG_DMA_BCM2708 || CONFIG_DMA_BCM2708_MODULE */\n+\n+#endif /* _PLAT_BCM2708_DMA_H */\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0046-MMC-added-alternative-MMC-driver.patch",
    "content": "From 364272893877af2ac5f331010d6f6f088c198e31 Mon Sep 17 00:00:00 2001\nFrom: gellert <gellert@raspberrypi.org>\nDate: Fri, 15 Aug 2014 16:35:06 +0100\nSubject: [PATCH] MMC: added alternative MMC driver\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nmmc: Disable CMD23 transfers on all cards\n\nPending wire-level investigation of these types of transfers\nand associated errors on bcm2835-mmc, disable for now. Fallback of\nCMD18/CMD25 transfers will be used automatically by the MMC layer.\n\nReported/Tested-by: Gellert Weisz <gellert@raspberrypi.org>\n\nmmc: bcm2835-mmc: enable DT support for all architectures\n\nBoth ARCH_BCM2835 and ARCH_BCM270x are built with OF now.\nEnable Device Tree support for all architectures.\n\nSigned-off-by: Noralf Trønnes <noralf@tronnes.org>\n\nmmc: bcm2835-mmc: fix probe error handling\n\nProbe error handling is broken in several places.\nSimplify error handling by using device managed functions.\nReplace pr_{err,info} with dev_{err,info}.\n\nSigned-off-by: Noralf Trønnes <noralf@tronnes.org>\n\nbcm2835-mmc: Add locks when accessing sdhost registers\n\nbcm2835-mmc: Add range of debug options for slowing things down\n\nbcm2835-mmc: Add option to disable some delays\n\nbcm2835-mmc: Add option to disable MMC_QUIRK_BLK_NO_CMD23\n\nbcm2835-mmc: Default to disabling MMC_QUIRK_BLK_NO_CMD23\n\nbcm2835-mmc: Adding overclocking option\n\nAllow a different clock speed to be substitued for a requested 50MHz.\nThis option is exposed using the \"overclock_50\" DT parameter.\nNote that the mmc interface is restricted to EVEN integer divisions of\n250MHz, and the highest sensible option is 63 (250/4 = 62.5), the\nnext being 125 (250/2) which is much too high.\n\nUse at your own risk.\n\nbcm2835-mmc: Round up the overclock, so 62 works for 62.5Mhz\n\nAlso only warn once for each overclock setting.\n\nmmc: bcm2835-mmc: Make available on ARCH_BCM2835\n\nMake the bcm2835-mmc driver available for use on ARCH_BCM2835.\n\nSigned-off-by: Noralf Trønnes <noralf@tronnes.org>\n\nBCM270x_DT: add bcm2835-mmc entry\n\nAdd Device Tree entry for bcm2835-mmc.\nIn non-DT mode, don't add the device in the board file.\n\nSigned-off-by: Noralf Trønnes <noralf@tronnes.org>\n\nbcm2835-mmc: Don't overwrite MMC capabilities from DT\n\nbcm2835-mmc: Don't override bus width capabilities from devicetree\n\nTake out the force setting of the MMC_CAP_4_BIT_DATA host capability\nso that the result read from devicetree via mmc_of_parse() is\npreserved.\n\nbcm2835-mmc: Only claim one DMA channel\n\nWith both MMC controllers enabled there are few DMA channels left. The\nbcm2835-mmc driver only uses DMA in one direction at a time, so it\ndoesn't need to claim two channels.\n\nSee: https://github.com/raspberrypi/linux/issues/1327\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.org>\n\nbcm2835-mmc: New timer API\n\nmmc: bcm2835-mmc: Support underclocking\n\nSupport underclocking of the SD bus using the max-frequency DT property\n(which currently has no DT parameter). The sd_overclock parameter\nalready provides another way to achieve the same thing which should be\nequivalent in end result, but it is a bug not to support max-frequency\nas well.\n\nSee: https://github.com/raspberrypi/linux/issues/2350\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.org>\n\nmmc/bcm2835: Recover from MMC_SEND_EXT_CSD\n\nIf the user issues an \"mmc extcsd read\", the SD controller receives\nwhat it thinks is a SEND_IF_COND command with an unexpected data block.\nThe resulting operations leave the FSM stuck in READWAIT, a state which\npersists until the MMC framework resets the controller, by which point\nthe root filesystem is likely to have been unmounted.\n\nA less heavyweight solution is to detect the condition and nudge the\nFSM by asserting the (self-clearing) FORCE_DATA_MODE bit.\n\nN.B. This workaround was essentially discovered by accident and without\na full understanding the inner workings of the controller, so it is\nfortunate that the \"fix\" only modifies error paths.\n\nSee: https://github.com/raspberrypi/linux/issues/2728\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.org>\n\nbcm2835-mmc: Fix DMA channel leak\n\nThe BCM2835 MMC host driver requests a DMA channel on probe but neglects\nto release the channel in the probe error path and on driver unbind.\n\nI'm seeing this happen on every boot of the Compute Module 3: On first\ndriver probe, DMA channel 2 is allocated and then leaked with a \"could\nnot get clk, deferring probe\" message. On second driver probe, channel 4\nis allocated.\n\nFix it.\n\nSigned-off-by: Lukas Wunner <lukas@wunner.de>\nCc: Frank Pavlic <f.pavlic@kunbus.de>\n\nbcm2835-mmc: Fix struct mmc_host leak on probe\n\nThe BCM2835 MMC host driver requests the bus address of the host's\nregister map on probe.  If that fails, the driver leaks the struct\nmmc_host allocated earlier.\n\nFix it.\n\nSigned-off-by: Lukas Wunner <lukas@wunner.de>\nCc: Frank Pavlic <f.pavlic@kunbus.de>\n\nbcm2835-mmc: Fix duplicate free_irq() on remove\n\nThe BCM2835 MMC host driver requests its interrupt as a device-managed\nresource, so the interrupt is automatically freed after the driver is\nunbound.\n\nHowever on driver unbind, bcm2835_mmc_remove() frees the interrupt\nexplicitly to avoid invocation of the interrupt handler after driver\nstructures have been torn down.\n\nThe interrupt is thus freed twice, leading to a WARN splat in\n__free_irq().  Fix by not requesting the interrupt as a device-managed\nresource.\n\nSigned-off-by: Lukas Wunner <lukas@wunner.de>\nCc: Frank Pavlic <f.pavlic@kunbus.de>\n\nbcm2835-mmc: Handle mmc_add_host() errors\n\nThe BCM2835 MMC host driver calls mmc_add_host() but doesn't check its\nreturn value.  Errors occurring in that function are therefore not\nhandled.  Fix it.\n\nSigned-off-by: Lukas Wunner <lukas@wunner.de>\nCc: Frank Pavlic <f.pavlic@kunbus.de>\n\nbcm2835-mmc: Deduplicate reset of driver data on remove\n\nThe BCM2835 MMC host driver sets the device's driver data pointer to\nNULL on ->remove() even though the driver core subsequently does the\nsame in __device_release_driver().  Drop the duplicate assignment.\n\nSigned-off-by: Lukas Wunner <lukas@wunner.de>\nCc: Frank Pavlic <f.pavlic@kunbus.de>\n\nbcm2835_mmc: Remove vestigial threaded IRQ\n\nWith SDIO processing now managed by the MMC framework with a\nworkqueue, the bcm2835_mmc driver no longer needs a threaded\nIRQ.\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.org>\n\nAdd missing dma_unmap_sg calls to free relevant swiotlb bounce buffers.\nThis prevents DMA leaks.\n\nSigned-off-by: Yaroslav Rosomakho <yaroslavros@gmail.com>\n\nLimit max_req_size under arm64 (or any other platform that uses swiotlb) to prevent potential buffer overflow due to bouncing.\n\nSigned-off-by: Yaroslav Rosomakho <yaroslavros@gmail.com>\n---\n drivers/mmc/core/block.c       |   28 +-\n drivers/mmc/core/core.c        |    3 +-\n drivers/mmc/core/quirks.h      |    8 +\n drivers/mmc/host/Kconfig       |   29 +\n drivers/mmc/host/Makefile      |    1 +\n drivers/mmc/host/bcm2835-mmc.c | 1576 ++++++++++++++++++++++++++++++++\n include/linux/mmc/card.h       |    2 +\n 7 files changed, 1643 insertions(+), 4 deletions(-)\n create mode 100644 drivers/mmc/host/bcm2835-mmc.c\n\n--- a/drivers/mmc/core/block.c\n+++ b/drivers/mmc/core/block.c\n@@ -165,6 +165,13 @@ static DEFINE_MUTEX(open_lock);\n module_param(perdev_minors, int, 0444);\n MODULE_PARM_DESC(perdev_minors, \"Minors numbers to allocate per device\");\n \n+/*\n+ * Allow quirks to be overridden for the current card\n+ */\n+static char *card_quirks;\n+module_param(card_quirks, charp, 0644);\n+MODULE_PARM_DESC(card_quirks, \"Force the use of the indicated quirks (a bitfield)\");\n+\n static inline int mmc_blk_part_switch(struct mmc_card *card,\n \t\t\t\t      unsigned int part_type);\n static void mmc_blk_rw_rq_prep(struct mmc_queue_req *mqrq,\n@@ -2897,6 +2904,7 @@ static int mmc_blk_probe(struct mmc_card\n {\n \tstruct mmc_blk_data *md, *part_md;\n \tchar cap_str[10];\n+\tchar quirk_str[24];\n \n \t/*\n \t * Check that the card supports the command class(es) we need.\n@@ -2904,7 +2912,16 @@ static int mmc_blk_probe(struct mmc_card\n \tif (!(card->csd.cmdclass & CCC_BLOCK_READ))\n \t\treturn -ENODEV;\n \n-\tmmc_fixup_device(card, mmc_blk_fixups);\n+\tif (card_quirks) {\n+\t\tunsigned long quirks;\n+\t\tif (kstrtoul(card_quirks, 0, &quirks) == 0)\n+\t\t\tcard->quirks = (unsigned int)quirks;\n+\t\telse\n+\t\t\tpr_err(\"mmc_block: Invalid card_quirks parameter '%s'\\n\",\n+\t\t\t       card_quirks);\n+\t}\n+\telse\n+\t\tmmc_fixup_device(card, mmc_blk_fixups);\n \n \tcard->complete_wq = alloc_workqueue(\"mmc_complete\",\n \t\t\t\t\tWQ_MEM_RECLAIM | WQ_HIGHPRI, 0);\n@@ -2919,9 +2936,14 @@ static int mmc_blk_probe(struct mmc_card\n \n \tstring_get_size((u64)get_capacity(md->disk), 512, STRING_UNITS_2,\n \t\t\tcap_str, sizeof(cap_str));\n-\tpr_info(\"%s: %s %s %s %s\\n\",\n+\tif (card->quirks)\n+\t\tsnprintf(quirk_str, sizeof(quirk_str),\n+\t\t\t \" (quirks 0x%08x)\", card->quirks);\n+\telse\n+\t\tquirk_str[0] = '\\0';\n+\tpr_info(\"%s: %s %s %s%s%s\\n\",\n \t\tmd->disk->disk_name, mmc_card_id(card), mmc_card_name(card),\n-\t\tcap_str, md->read_only ? \"(ro)\" : \"\");\n+\t\tcap_str, md->read_only ? \" (ro)\" : \"\", quirk_str);\n \n \tif (mmc_blk_alloc_parts(card, md))\n \t\tgoto out;\n--- a/drivers/mmc/core/core.c\n+++ b/drivers/mmc/core/core.c\n@@ -1874,7 +1874,8 @@ EXPORT_SYMBOL(mmc_erase);\n \n int mmc_can_erase(struct mmc_card *card)\n {\n-\tif (card->csd.cmdclass & CCC_ERASE && card->erase_size)\n+\tif (card->csd.cmdclass & CCC_ERASE && card->erase_size &&\n+\t    !(card->quirks & MMC_QUIRK_ERASE_BROKEN))\n \t\treturn 1;\n \treturn 0;\n }\n--- a/drivers/mmc/core/quirks.h\n+++ b/drivers/mmc/core/quirks.h\n@@ -99,6 +99,14 @@ static const struct mmc_fixup __maybe_un\n \tMMC_FIXUP(\"V10016\", CID_MANFID_KINGSTON, CID_OEMID_ANY, add_quirk_mmc,\n \t\t  MMC_QUIRK_TRIM_BROKEN),\n \n+\t/*\n+\t *  On some Kingston SD cards, multiple erases of less than 64\n+\t *  sectors can cause corruption.\n+\t */\n+\tMMC_FIXUP(\"SD16G\", 0x41, 0x3432, add_quirk, MMC_QUIRK_ERASE_BROKEN),\n+\tMMC_FIXUP(\"SD32G\", 0x41, 0x3432, add_quirk, MMC_QUIRK_ERASE_BROKEN),\n+\tMMC_FIXUP(\"SD64G\", 0x41, 0x3432, add_quirk, MMC_QUIRK_ERASE_BROKEN),\n+\n \tEND_FIXUP\n };\n \n--- a/drivers/mmc/host/Kconfig\n+++ b/drivers/mmc/host/Kconfig\n@@ -5,6 +5,35 @@\n \n comment \"MMC/SD/SDIO Host Controller Drivers\"\n \n+config MMC_BCM2835_MMC\n+\ttristate \"MMC support on BCM2835\"\n+\tdepends on MACH_BCM2708 || MACH_BCM2709 || ARCH_BCM2835\n+\thelp\n+\t  This selects the MMC Interface on BCM2835.\n+\n+\t  If you have a controller with this interface, say Y or M here.\n+\n+\t  If unsure, say N.\n+\n+config MMC_BCM2835_DMA\n+\tbool \"DMA support on BCM2835 Arasan controller\"\n+\tdepends on MMC_BCM2835_MMC\n+\thelp\n+\t  Enable DMA support on the Arasan SDHCI controller in Broadcom 2708\n+\t  based chips.\n+\n+\t  If unsure, say N.\n+\n+config MMC_BCM2835_PIO_DMA_BARRIER\n+\tint \"Block count limit for PIO transfers\"\n+\tdepends on MMC_BCM2835_MMC && MMC_BCM2835_DMA\n+\trange 0 256\n+\tdefault 2\n+\thelp\n+\t  The inclusive limit in bytes under which PIO will be used instead of DMA\n+\n+\t  If unsure, say 2 here.\n+\n config MMC_DEBUG\n \tbool \"MMC host drivers debugging\"\n \tdepends on MMC != n\n--- a/drivers/mmc/host/Makefile\n+++ b/drivers/mmc/host/Makefile\n@@ -24,6 +24,7 @@ obj-$(CONFIG_MMC_SDHCI_F_SDH30)\t+= sdhci\n obj-$(CONFIG_MMC_SDHCI_MILBEAUT)\t+= sdhci-milbeaut.o\n obj-$(CONFIG_MMC_SDHCI_SPEAR)\t+= sdhci-spear.o\n obj-$(CONFIG_MMC_SDHCI_AM654)\t+= sdhci_am654.o\n+obj-$(CONFIG_MMC_BCM2835_MMC)\t+= bcm2835-mmc.o\n obj-$(CONFIG_MMC_WBSD)\t\t+= wbsd.o\n obj-$(CONFIG_MMC_AU1X)\t\t+= au1xmmc.o\n obj-$(CONFIG_MMC_ALCOR)\t+= alcor.o\n--- /dev/null\n+++ b/drivers/mmc/host/bcm2835-mmc.c\n@@ -0,0 +1,1576 @@\n+/*\n+ * BCM2835 MMC host driver.\n+ *\n+ * Author:      Gellert Weisz <gellert@raspberrypi.org>\n+ *              Copyright 2014\n+ *\n+ * Based on\n+ *  sdhci-bcm2708.c by Broadcom\n+ *  sdhci-bcm2835.c by Stephen Warren and Oleksandr Tymoshenko\n+ *  sdhci.c and sdhci-pci.c by Pierre Ossman\n+ *\n+ * This program is free software; you can redistribute it and/or modify it\n+ * under the terms and conditions of the GNU General Public License,\n+ * version 2, as published by the Free Software Foundation.\n+ *\n+ * This program is distributed in the hope it will be useful, but WITHOUT\n+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n+ * more details.\n+ *\n+ * You should have received a copy of the GNU General Public License\n+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.\n+ */\n+\n+#include <linux/delay.h>\n+#include <linux/module.h>\n+#include <linux/io.h>\n+#include <linux/mmc/mmc.h>\n+#include <linux/mmc/host.h>\n+#include <linux/mmc/sd.h>\n+#include <linux/scatterlist.h>\n+#include <linux/of_address.h>\n+#include <linux/of_irq.h>\n+#include <linux/clk.h>\n+#include <linux/platform_device.h>\n+#include <linux/err.h>\n+#include <linux/blkdev.h>\n+#include <linux/dmaengine.h>\n+#include <linux/dma-mapping.h>\n+#include <linux/of_dma.h>\n+#include <linux/swiotlb.h>\n+\n+#include \"sdhci.h\"\n+\n+\n+#define DRIVER_NAME \"mmc-bcm2835\"\n+\n+#define DBG(f, x...) \\\n+pr_debug(DRIVER_NAME \" [%s()]: \" f, __func__, ## x)\n+\n+#ifndef CONFIG_MMC_BCM2835_DMA\n+ #define FORCE_PIO\n+#endif\n+\n+\n+/* the inclusive limit in bytes under which PIO will be used instead of DMA */\n+#ifdef CONFIG_MMC_BCM2835_PIO_DMA_BARRIER\n+#define PIO_DMA_BARRIER CONFIG_MMC_BCM2835_PIO_DMA_BARRIER\n+#else\n+#define PIO_DMA_BARRIER 00\n+#endif\n+\n+#define MIN_FREQ 400000\n+#define TIMEOUT_VAL 0xE\n+#define BCM2835_SDHCI_WRITE_DELAY(f)\t(((2 * 1000000) / f) + 1)\n+\n+\n+unsigned mmc_debug;\n+unsigned mmc_debug2;\n+\n+struct bcm2835_host {\n+\tspinlock_t\t\t\t\tlock;\n+\n+\tvoid __iomem\t\t\t*ioaddr;\n+\tu32\t\t\t\t\t\tbus_addr;\n+\n+\tstruct mmc_host\t\t\t*mmc;\n+\n+\tu32\t\t\t\t\t\ttimeout;\n+\n+\tint\t\t\t\t\t\tclock;\t/* Current clock speed */\n+\tu8\t\t\t\t\t\tpwr;\t/* Current voltage */\n+\n+\tunsigned int\t\t\tmax_clk;\t\t/* Max possible freq */\n+\tunsigned int\t\t\ttimeout_clk;\t/* Timeout freq (KHz) */\n+\tunsigned int\t\t\tclk_mul;\t\t/* Clock Muliplier value */\n+\n+\tstruct tasklet_struct\tfinish_tasklet;\t\t/* Tasklet structures */\n+\n+\tstruct timer_list\t\ttimer;\t\t\t/* Timer for timeouts */\n+\n+\tstruct sg_mapping_iter\tsg_miter;\t\t/* SG state for PIO */\n+\tunsigned int\t\t\tblocks;\t\t\t/* remaining PIO blocks */\n+\n+\tint\t\t\t\t\t\tirq;\t\t\t/* Device IRQ */\n+\n+\n+\tu32\t\t\t\t\t\tier;\t\t\t/* cached registers */\n+\n+\tstruct mmc_request\t\t*mrq;\t\t\t/* Current request */\n+\tstruct mmc_command\t\t*cmd;\t\t\t/* Current command */\n+\tstruct mmc_data\t\t\t*data;\t\t\t/* Current data request */\n+\tunsigned int\t\t\tdata_early:1;\t\t/* Data finished before cmd */\n+\n+\twait_queue_head_t\t\tbuf_ready_int;\t\t/* Waitqueue for Buffer Read Ready interrupt */\n+\n+\tu32\t\t\t\t\t\tshadow;\n+\n+\t/*DMA part*/\n+\tstruct dma_chan\t\t\t*dma_chan_rxtx;\t\t/* DMA channel for reads and writes */\n+\tstruct dma_slave_config\t\tdma_cfg_rx;\n+\tstruct dma_slave_config\t\tdma_cfg_tx;\n+\tstruct dma_async_tx_descriptor\t*tx_desc;\t/* descriptor */\n+\n+\tbool\t\t\t\t\thave_dma;\n+\tbool\t\t\t\t\tuse_dma;\n+\tbool\t\t\t\t\twait_for_dma;\n+\t/*end of DMA part*/\n+\n+\tint\t\t\t\t\t\tmax_delay;\t/* maximum length of time spent waiting */\n+\n+\tint\t\t\t\t\t\tflags;\t\t\t\t/* Host attributes */\n+#define SDHCI_REQ_USE_DMA\t(1<<2)\t/* Use DMA for this req. */\n+#define SDHCI_DEVICE_DEAD\t(1<<3)\t/* Device unresponsive */\n+#define SDHCI_AUTO_CMD12\t(1<<6)\t/* Auto CMD12 support */\n+#define SDHCI_AUTO_CMD23\t(1<<7)\t/* Auto CMD23 support */\n+#define SDHCI_SDIO_IRQ_ENABLED\t(1<<9)\t/* SDIO irq enabled */\n+\n+\tu32\t\t\t\toverclock_50;\t/* frequency to use when 50MHz is requested (in MHz) */\n+\tu32\t\t\t\tmax_overclock;\t/* Highest reported */\n+};\n+\n+\n+static inline void bcm2835_mmc_writel(struct bcm2835_host *host, u32 val, int reg, int from)\n+{\n+\tunsigned delay;\n+\tlockdep_assert_held_once(&host->lock);\n+\twritel(val, host->ioaddr + reg);\n+\tudelay(BCM2835_SDHCI_WRITE_DELAY(max(host->clock, MIN_FREQ)));\n+\n+\tdelay = ((mmc_debug >> 16) & 0xf) << ((mmc_debug >> 20) & 0xf);\n+\tif (delay && !((1<<from) & mmc_debug2))\n+\t\tudelay(delay);\n+}\n+\n+static inline void mmc_raw_writel(struct bcm2835_host *host, u32 val, int reg)\n+{\n+\tunsigned delay;\n+\tlockdep_assert_held_once(&host->lock);\n+\twritel(val, host->ioaddr + reg);\n+\n+\tdelay = ((mmc_debug >> 24) & 0xf) << ((mmc_debug >> 28) & 0xf);\n+\tif (delay)\n+\t\tudelay(delay);\n+}\n+\n+static inline u32 bcm2835_mmc_readl(struct bcm2835_host *host, int reg)\n+{\n+\tlockdep_assert_held_once(&host->lock);\n+\treturn readl(host->ioaddr + reg);\n+}\n+\n+static inline void bcm2835_mmc_writew(struct bcm2835_host *host, u16 val, int reg)\n+{\n+\tu32 oldval = (reg == SDHCI_COMMAND) ? host->shadow :\n+\t\tbcm2835_mmc_readl(host, reg & ~3);\n+\tu32 word_num = (reg >> 1) & 1;\n+\tu32 word_shift = word_num * 16;\n+\tu32 mask = 0xffff << word_shift;\n+\tu32 newval = (oldval & ~mask) | (val << word_shift);\n+\n+\tif (reg == SDHCI_TRANSFER_MODE)\n+\t\thost->shadow = newval;\n+\telse\n+\t\tbcm2835_mmc_writel(host, newval, reg & ~3, 0);\n+\n+}\n+\n+static inline void bcm2835_mmc_writeb(struct bcm2835_host *host, u8 val, int reg)\n+{\n+\tu32 oldval = bcm2835_mmc_readl(host, reg & ~3);\n+\tu32 byte_num = reg & 3;\n+\tu32 byte_shift = byte_num * 8;\n+\tu32 mask = 0xff << byte_shift;\n+\tu32 newval = (oldval & ~mask) | (val << byte_shift);\n+\n+\tbcm2835_mmc_writel(host, newval, reg & ~3, 1);\n+}\n+\n+\n+static inline u16 bcm2835_mmc_readw(struct bcm2835_host *host, int reg)\n+{\n+\tu32 val = bcm2835_mmc_readl(host, (reg & ~3));\n+\tu32 word_num = (reg >> 1) & 1;\n+\tu32 word_shift = word_num * 16;\n+\tu32 word = (val >> word_shift) & 0xffff;\n+\n+\treturn word;\n+}\n+\n+static inline u8 bcm2835_mmc_readb(struct bcm2835_host *host, int reg)\n+{\n+\tu32 val = bcm2835_mmc_readl(host, (reg & ~3));\n+\tu32 byte_num = reg & 3;\n+\tu32 byte_shift = byte_num * 8;\n+\tu32 byte = (val >> byte_shift) & 0xff;\n+\n+\treturn byte;\n+}\n+\n+static void bcm2835_mmc_unsignal_irqs(struct bcm2835_host *host, u32 clear)\n+{\n+\tu32 ier;\n+\n+\tier = bcm2835_mmc_readl(host, SDHCI_SIGNAL_ENABLE);\n+\tier &= ~clear;\n+\t/* change which requests generate IRQs - makes no difference to\n+\t   the content of SDHCI_INT_STATUS, or the need to acknowledge IRQs */\n+\tbcm2835_mmc_writel(host, ier, SDHCI_SIGNAL_ENABLE, 2);\n+}\n+\n+\n+static void bcm2835_mmc_dumpregs(struct bcm2835_host *host)\n+{\n+\tpr_debug(DRIVER_NAME \": =========== REGISTER DUMP (%s)===========\\n\",\n+\t\tmmc_hostname(host->mmc));\n+\n+\tpr_debug(DRIVER_NAME \": Sys addr: 0x%08x | Version:  0x%08x\\n\",\n+\t\tbcm2835_mmc_readl(host, SDHCI_DMA_ADDRESS),\n+\t\tbcm2835_mmc_readw(host, SDHCI_HOST_VERSION));\n+\tpr_debug(DRIVER_NAME \": Blk size: 0x%08x | Blk cnt:  0x%08x\\n\",\n+\t\tbcm2835_mmc_readw(host, SDHCI_BLOCK_SIZE),\n+\t\tbcm2835_mmc_readw(host, SDHCI_BLOCK_COUNT));\n+\tpr_debug(DRIVER_NAME \": Argument: 0x%08x | Trn mode: 0x%08x\\n\",\n+\t\tbcm2835_mmc_readl(host, SDHCI_ARGUMENT),\n+\t\tbcm2835_mmc_readw(host, SDHCI_TRANSFER_MODE));\n+\tpr_debug(DRIVER_NAME \": Present:  0x%08x | Host ctl: 0x%08x\\n\",\n+\t\tbcm2835_mmc_readl(host, SDHCI_PRESENT_STATE),\n+\t\tbcm2835_mmc_readb(host, SDHCI_HOST_CONTROL));\n+\tpr_debug(DRIVER_NAME \": Power:    0x%08x | Blk gap:  0x%08x\\n\",\n+\t\tbcm2835_mmc_readb(host, SDHCI_POWER_CONTROL),\n+\t\tbcm2835_mmc_readb(host, SDHCI_BLOCK_GAP_CONTROL));\n+\tpr_debug(DRIVER_NAME \": Wake-up:  0x%08x | Clock:    0x%08x\\n\",\n+\t\tbcm2835_mmc_readb(host, SDHCI_WAKE_UP_CONTROL),\n+\t\tbcm2835_mmc_readw(host, SDHCI_CLOCK_CONTROL));\n+\tpr_debug(DRIVER_NAME \": Timeout:  0x%08x | Int stat: 0x%08x\\n\",\n+\t\tbcm2835_mmc_readb(host, SDHCI_TIMEOUT_CONTROL),\n+\t\tbcm2835_mmc_readl(host, SDHCI_INT_STATUS));\n+\tpr_debug(DRIVER_NAME \": Int enab: 0x%08x | Sig enab: 0x%08x\\n\",\n+\t\tbcm2835_mmc_readl(host, SDHCI_INT_ENABLE),\n+\t\tbcm2835_mmc_readl(host, SDHCI_SIGNAL_ENABLE));\n+\tpr_debug(DRIVER_NAME \": AC12 err: 0x%08x | Slot int: 0x%08x\\n\",\n+\t\tbcm2835_mmc_readw(host, SDHCI_AUTO_CMD_STATUS),\n+\t\tbcm2835_mmc_readw(host, SDHCI_SLOT_INT_STATUS));\n+\tpr_debug(DRIVER_NAME \": Caps:     0x%08x | Caps_1:   0x%08x\\n\",\n+\t\tbcm2835_mmc_readl(host, SDHCI_CAPABILITIES),\n+\t\tbcm2835_mmc_readl(host, SDHCI_CAPABILITIES_1));\n+\tpr_debug(DRIVER_NAME \": Cmd:      0x%08x | Max curr: 0x%08x\\n\",\n+\t\tbcm2835_mmc_readw(host, SDHCI_COMMAND),\n+\t\tbcm2835_mmc_readl(host, SDHCI_MAX_CURRENT));\n+\tpr_debug(DRIVER_NAME \": Host ctl2: 0x%08x\\n\",\n+\t\tbcm2835_mmc_readw(host, SDHCI_HOST_CONTROL2));\n+\n+\tpr_debug(DRIVER_NAME \": ===========================================\\n\");\n+}\n+\n+\n+static void bcm2835_mmc_reset(struct bcm2835_host *host, u8 mask)\n+{\n+\tunsigned long timeout;\n+\tunsigned long flags;\n+\n+\tspin_lock_irqsave(&host->lock, flags);\n+\tbcm2835_mmc_writeb(host, mask, SDHCI_SOFTWARE_RESET);\n+\n+\tif (mask & SDHCI_RESET_ALL)\n+\t\thost->clock = 0;\n+\n+\t/* Wait max 100 ms */\n+\ttimeout = 100;\n+\n+\t/* hw clears the bit when it's done */\n+\twhile (bcm2835_mmc_readb(host, SDHCI_SOFTWARE_RESET) & mask) {\n+\t\tif (timeout == 0) {\n+\t\t\tpr_err(\"%s: Reset 0x%x never completed.\\n\",\n+\t\t\t\tmmc_hostname(host->mmc), (int)mask);\n+\t\t\tbcm2835_mmc_dumpregs(host);\n+\t\t\treturn;\n+\t\t}\n+\t\ttimeout--;\n+\t\tspin_unlock_irqrestore(&host->lock, flags);\n+\t\tmdelay(1);\n+\t\tspin_lock_irqsave(&host->lock, flags);\n+\t}\n+\n+\tif (100-timeout > 10 && 100-timeout > host->max_delay) {\n+\t\thost->max_delay = 100-timeout;\n+\t\tpr_warn(\"Warning: MMC controller hung for %d ms\\n\", host->max_delay);\n+\t}\n+\tspin_unlock_irqrestore(&host->lock, flags);\n+}\n+\n+static void bcm2835_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);\n+\n+static void bcm2835_mmc_init(struct bcm2835_host *host, int soft)\n+{\n+\tunsigned long flags;\n+\tif (soft)\n+\t\tbcm2835_mmc_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);\n+\telse\n+\t\tbcm2835_mmc_reset(host, SDHCI_RESET_ALL);\n+\n+\thost->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |\n+\t\t    SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT |\n+\t\t    SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC |\n+\t\t    SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |\n+\t\t    SDHCI_INT_RESPONSE;\n+\n+\tspin_lock_irqsave(&host->lock, flags);\n+\tbcm2835_mmc_writel(host, host->ier, SDHCI_INT_ENABLE, 3);\n+\tbcm2835_mmc_writel(host, host->ier, SDHCI_SIGNAL_ENABLE, 3);\n+\tspin_unlock_irqrestore(&host->lock, flags);\n+\n+\tif (soft) {\n+\t\t/* force clock reconfiguration */\n+\t\thost->clock = 0;\n+\t\tbcm2835_mmc_set_ios(host->mmc, &host->mmc->ios);\n+\t}\n+}\n+\n+\n+\n+static void bcm2835_mmc_finish_data(struct bcm2835_host *host);\n+\n+static void bcm2835_mmc_dma_complete(void *param)\n+{\n+\tstruct bcm2835_host *host = param;\n+\tstruct dma_chan *dma_chan;\n+\tunsigned long flags;\n+\tu32 dir_data;\n+\n+\tspin_lock_irqsave(&host->lock, flags);\n+\n+\thost->use_dma = false;\n+\n+\tif (host->data) {\n+\t\tdma_chan = host->dma_chan_rxtx;\n+\t\tif (host->data->flags & MMC_DATA_WRITE)\n+\t\t\tdir_data = DMA_TO_DEVICE;\n+\t\telse\n+\t\t\tdir_data = DMA_FROM_DEVICE;\n+\t\tdma_unmap_sg(dma_chan->device->dev,\n+\t\t     host->data->sg, host->data->sg_len,\n+\t\t     dir_data);\n+\t\tif (! (host->data->flags & MMC_DATA_WRITE))\n+\t\t\tbcm2835_mmc_finish_data(host);\n+\t} else if (host->wait_for_dma) {\n+\t\thost->wait_for_dma = false;\n+\t\ttasklet_schedule(&host->finish_tasklet);\n+\t}\n+\n+\tspin_unlock_irqrestore(&host->lock, flags);\n+}\n+\n+static void bcm2835_bcm2835_mmc_read_block_pio(struct bcm2835_host *host)\n+{\n+\tunsigned long flags;\n+\tsize_t blksize, len, chunk;\n+\n+\tu32 uninitialized_var(scratch);\n+\tu8 *buf;\n+\n+\tblksize = host->data->blksz;\n+\tchunk = 0;\n+\n+\tlocal_irq_save(flags);\n+\n+\twhile (blksize) {\n+\t\tif (!sg_miter_next(&host->sg_miter))\n+\t\t\tBUG();\n+\n+\t\tlen = min(host->sg_miter.length, blksize);\n+\n+\t\tblksize -= len;\n+\t\thost->sg_miter.consumed = len;\n+\n+\t\tbuf = host->sg_miter.addr;\n+\n+\t\twhile (len) {\n+\t\t\tif (chunk == 0) {\n+\t\t\t\tscratch = bcm2835_mmc_readl(host, SDHCI_BUFFER);\n+\t\t\t\tchunk = 4;\n+\t\t\t}\n+\n+\t\t\t*buf = scratch & 0xFF;\n+\n+\t\t\tbuf++;\n+\t\t\tscratch >>= 8;\n+\t\t\tchunk--;\n+\t\t\tlen--;\n+\t\t}\n+\t}\n+\n+\tsg_miter_stop(&host->sg_miter);\n+\n+\tlocal_irq_restore(flags);\n+}\n+\n+static void bcm2835_bcm2835_mmc_write_block_pio(struct bcm2835_host *host)\n+{\n+\tunsigned long flags;\n+\tsize_t blksize, len, chunk;\n+\tu32 scratch;\n+\tu8 *buf;\n+\n+\tblksize = host->data->blksz;\n+\tchunk = 0;\n+\tchunk = 0;\n+\tscratch = 0;\n+\n+\tlocal_irq_save(flags);\n+\n+\twhile (blksize) {\n+\t\tif (!sg_miter_next(&host->sg_miter))\n+\t\t\tBUG();\n+\n+\t\tlen = min(host->sg_miter.length, blksize);\n+\n+\t\tblksize -= len;\n+\t\thost->sg_miter.consumed = len;\n+\n+\t\tbuf = host->sg_miter.addr;\n+\n+\t\twhile (len) {\n+\t\t\tscratch |= (u32)*buf << (chunk * 8);\n+\n+\t\t\tbuf++;\n+\t\t\tchunk++;\n+\t\t\tlen--;\n+\n+\t\t\tif ((chunk == 4) || ((len == 0) && (blksize == 0))) {\n+\t\t\t\tmmc_raw_writel(host, scratch, SDHCI_BUFFER);\n+\t\t\t\tchunk = 0;\n+\t\t\t\tscratch = 0;\n+\t\t\t}\n+\t\t}\n+\t}\n+\n+\tsg_miter_stop(&host->sg_miter);\n+\n+\tlocal_irq_restore(flags);\n+}\n+\n+\n+static void bcm2835_mmc_transfer_pio(struct bcm2835_host *host)\n+{\n+\tu32 mask;\n+\n+\tBUG_ON(!host->data);\n+\n+\tif (host->blocks == 0)\n+\t\treturn;\n+\n+\tif (host->data->flags & MMC_DATA_READ)\n+\t\tmask = SDHCI_DATA_AVAILABLE;\n+\telse\n+\t\tmask = SDHCI_SPACE_AVAILABLE;\n+\n+\twhile (bcm2835_mmc_readl(host, SDHCI_PRESENT_STATE) & mask) {\n+\n+\t\tif (host->data->flags & MMC_DATA_READ)\n+\t\t\tbcm2835_bcm2835_mmc_read_block_pio(host);\n+\t\telse\n+\t\t\tbcm2835_bcm2835_mmc_write_block_pio(host);\n+\n+\t\thost->blocks--;\n+\n+\t\t/* QUIRK used in sdhci.c removes the 'if' */\n+\t\t/* but it seems this is unnecessary */\n+\t\tif (host->blocks == 0)\n+\t\t\tbreak;\n+\n+\n+\t}\n+}\n+\n+\n+static void bcm2835_mmc_transfer_dma(struct bcm2835_host *host)\n+{\n+\tu32 len, dir_data, dir_slave;\n+\tstruct dma_async_tx_descriptor *desc = NULL;\n+\tstruct dma_chan *dma_chan;\n+\n+\n+\tWARN_ON(!host->data);\n+\n+\tif (!host->data)\n+\t\treturn;\n+\n+\tif (host->blocks == 0)\n+\t\treturn;\n+\n+\tdma_chan = host->dma_chan_rxtx;\n+\tif (host->data->flags & MMC_DATA_READ) {\n+\t\tdir_data = DMA_FROM_DEVICE;\n+\t\tdir_slave = DMA_DEV_TO_MEM;\n+\t} else {\n+\t\tdir_data = DMA_TO_DEVICE;\n+\t\tdir_slave = DMA_MEM_TO_DEV;\n+\t}\n+\n+\t/* The parameters have already been validated, so this will not fail */\n+\t(void)dmaengine_slave_config(dma_chan,\n+\t\t\t\t     (dir_data == DMA_FROM_DEVICE) ?\n+\t\t\t\t     &host->dma_cfg_rx :\n+\t\t\t\t     &host->dma_cfg_tx);\n+\n+\tBUG_ON(!dma_chan->device);\n+\tBUG_ON(!dma_chan->device->dev);\n+\tBUG_ON(!host->data->sg);\n+\n+\tlen = dma_map_sg(dma_chan->device->dev, host->data->sg,\n+\t\t\t host->data->sg_len, dir_data);\n+\tif (len > 0) {\n+\t\tdesc = dmaengine_prep_slave_sg(dma_chan, host->data->sg,\n+\t\t\t\t\t       len, dir_slave,\n+\t\t\t\t\t       DMA_PREP_INTERRUPT | DMA_CTRL_ACK);\n+\t} else {\n+\t\tdev_err(mmc_dev(host->mmc), \"dma_map_sg returned zero length\\n\");\n+\t}\n+\tif (desc) {\n+\t\tunsigned long flags;\n+\t\tspin_lock_irqsave(&host->lock, flags);\n+\t\tbcm2835_mmc_unsignal_irqs(host, SDHCI_INT_DATA_AVAIL |\n+\t\t\t\t\t\t    SDHCI_INT_SPACE_AVAIL);\n+\t\thost->tx_desc = desc;\n+\t\tdesc->callback = bcm2835_mmc_dma_complete;\n+\t\tdesc->callback_param = host;\n+\t\tspin_unlock_irqrestore(&host->lock, flags);\n+\t\tdmaengine_submit(desc);\n+\t\tdma_async_issue_pending(dma_chan);\n+\t} else {\n+\t\tdma_unmap_sg(dma_chan->device->dev, host->data->sg, len, dir_data);\n+\t}\n+\n+}\n+\n+\n+\n+static void bcm2835_mmc_set_transfer_irqs(struct bcm2835_host *host)\n+{\n+\tu32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;\n+\tu32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;\n+\n+\tif (host->use_dma)\n+\t\thost->ier = (host->ier & ~pio_irqs) | dma_irqs;\n+\telse\n+\t\thost->ier = (host->ier & ~dma_irqs) | pio_irqs;\n+\n+\tbcm2835_mmc_writel(host, host->ier, SDHCI_INT_ENABLE, 4);\n+\tbcm2835_mmc_writel(host, host->ier, SDHCI_SIGNAL_ENABLE, 4);\n+}\n+\n+\n+static void bcm2835_mmc_prepare_data(struct bcm2835_host *host, struct mmc_command *cmd)\n+{\n+\tu8 count;\n+\tstruct mmc_data *data = cmd->data;\n+\n+\tWARN_ON(host->data);\n+\n+\tif (data || (cmd->flags & MMC_RSP_BUSY)) {\n+\t\tcount = TIMEOUT_VAL;\n+\t\tbcm2835_mmc_writeb(host, count, SDHCI_TIMEOUT_CONTROL);\n+\t}\n+\n+\tif (!data)\n+\t\treturn;\n+\n+\t/* Sanity checks */\n+\tBUG_ON(data->blksz * data->blocks > 524288);\n+\tBUG_ON(data->blksz > host->mmc->max_blk_size);\n+\tBUG_ON(data->blocks > 65535);\n+\n+\thost->data = data;\n+\thost->data_early = 0;\n+\thost->data->bytes_xfered = 0;\n+\n+\n+\tif (!(host->flags & SDHCI_REQ_USE_DMA)) {\n+\t\tint flags;\n+\n+\t\tflags = SG_MITER_ATOMIC;\n+\t\tif (host->data->flags & MMC_DATA_READ)\n+\t\t\tflags |= SG_MITER_TO_SG;\n+\t\telse\n+\t\t\tflags |= SG_MITER_FROM_SG;\n+\t\tsg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);\n+\t\thost->blocks = data->blocks;\n+\t}\n+\n+\thost->use_dma = host->have_dma && data->blocks > PIO_DMA_BARRIER;\n+\n+\tbcm2835_mmc_set_transfer_irqs(host);\n+\n+\t/* Set the DMA boundary value and block size */\n+\tbcm2835_mmc_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,\n+\t\tdata->blksz), SDHCI_BLOCK_SIZE);\n+\tbcm2835_mmc_writew(host, data->blocks, SDHCI_BLOCK_COUNT);\n+\n+\tBUG_ON(!host->data);\n+}\n+\n+static void bcm2835_mmc_set_transfer_mode(struct bcm2835_host *host,\n+\tstruct mmc_command *cmd)\n+{\n+\tu16 mode;\n+\tstruct mmc_data *data = cmd->data;\n+\n+\tif (data == NULL) {\n+\t\t/* clear Auto CMD settings for no data CMDs */\n+\t\tmode = bcm2835_mmc_readw(host, SDHCI_TRANSFER_MODE);\n+\t\tbcm2835_mmc_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |\n+\t\t\t\tSDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);\n+\t\treturn;\n+\t}\n+\n+\tWARN_ON(!host->data);\n+\n+\tmode = SDHCI_TRNS_BLK_CNT_EN;\n+\n+\tif ((mmc_op_multi(cmd->opcode) || data->blocks > 1)) {\n+\t\tmode |= SDHCI_TRNS_MULTI;\n+\n+\t\t/*\n+\t\t * If we are sending CMD23, CMD12 never gets sent\n+\t\t * on successful completion (so no Auto-CMD12).\n+\t\t */\n+\t\tif (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12))\n+\t\t\tmode |= SDHCI_TRNS_AUTO_CMD12;\n+\t\telse if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {\n+\t\t\tmode |= SDHCI_TRNS_AUTO_CMD23;\n+\t\t\tbcm2835_mmc_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2, 5);\n+\t\t}\n+\t}\n+\n+\tif (data->flags & MMC_DATA_READ)\n+\t\tmode |= SDHCI_TRNS_READ;\n+\tif (host->flags & SDHCI_REQ_USE_DMA)\n+\t\tmode |= SDHCI_TRNS_DMA;\n+\n+\tbcm2835_mmc_writew(host, mode, SDHCI_TRANSFER_MODE);\n+}\n+\n+void bcm2835_mmc_send_command(struct bcm2835_host *host, struct mmc_command *cmd)\n+{\n+\tint flags;\n+\tu32 mask;\n+\tunsigned long timeout;\n+\n+\tWARN_ON(host->cmd);\n+\n+\t/* Wait max 10 ms */\n+\ttimeout = 1000;\n+\n+\tmask = SDHCI_CMD_INHIBIT;\n+\tif ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))\n+\t\tmask |= SDHCI_DATA_INHIBIT;\n+\n+\t/* We shouldn't wait for data inihibit for stop commands, even\n+\t   though they might use busy signaling */\n+\tif (host->mrq->data && (cmd == host->mrq->data->stop))\n+\t\tmask &= ~SDHCI_DATA_INHIBIT;\n+\n+\twhile (bcm2835_mmc_readl(host, SDHCI_PRESENT_STATE) & mask) {\n+\t\tif (timeout == 0) {\n+\t\t\tpr_err(\"%s: Controller never released inhibit bit(s).\\n\",\n+\t\t\t\tmmc_hostname(host->mmc));\n+\t\t\tbcm2835_mmc_dumpregs(host);\n+\t\t\tcmd->error = -EIO;\n+\t\t\ttasklet_schedule(&host->finish_tasklet);\n+\t\t\treturn;\n+\t\t}\n+\t\ttimeout--;\n+\t\tudelay(10);\n+\t}\n+\n+\tif ((1000-timeout)/100 > 1 && (1000-timeout)/100 > host->max_delay) {\n+\t\thost->max_delay = (1000-timeout)/100;\n+\t\tpr_warn(\"Warning: MMC controller hung for %d ms\\n\", host->max_delay);\n+\t}\n+\n+\ttimeout = jiffies;\n+\tif (!cmd->data && cmd->busy_timeout > 9000)\n+\t\ttimeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;\n+\telse\n+\t\ttimeout += 10 * HZ;\n+\tmod_timer(&host->timer, timeout);\n+\n+\thost->cmd = cmd;\n+\thost->use_dma = false;\n+\n+\tbcm2835_mmc_prepare_data(host, cmd);\n+\n+\tbcm2835_mmc_writel(host, cmd->arg, SDHCI_ARGUMENT, 6);\n+\n+\tbcm2835_mmc_set_transfer_mode(host, cmd);\n+\n+\tif ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {\n+\t\tpr_err(\"%s: Unsupported response type!\\n\",\n+\t\t\tmmc_hostname(host->mmc));\n+\t\tcmd->error = -EINVAL;\n+\t\ttasklet_schedule(&host->finish_tasklet);\n+\t\treturn;\n+\t}\n+\n+\tif (!(cmd->flags & MMC_RSP_PRESENT))\n+\t\tflags = SDHCI_CMD_RESP_NONE;\n+\telse if (cmd->flags & MMC_RSP_136)\n+\t\tflags = SDHCI_CMD_RESP_LONG;\n+\telse if (cmd->flags & MMC_RSP_BUSY)\n+\t\tflags = SDHCI_CMD_RESP_SHORT_BUSY;\n+\telse\n+\t\tflags = SDHCI_CMD_RESP_SHORT;\n+\n+\tif (cmd->flags & MMC_RSP_CRC)\n+\t\tflags |= SDHCI_CMD_CRC;\n+\tif (cmd->flags & MMC_RSP_OPCODE)\n+\t\tflags |= SDHCI_CMD_INDEX;\n+\n+\tif (cmd->data)\n+\t\tflags |= SDHCI_CMD_DATA;\n+\n+\tbcm2835_mmc_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);\n+}\n+\n+\n+static void bcm2835_mmc_finish_data(struct bcm2835_host *host)\n+{\n+\tstruct mmc_data *data;\n+\n+\tBUG_ON(!host->data);\n+\n+\tdata = host->data;\n+\thost->data = NULL;\n+\n+\tif (data->error)\n+\t\tdata->bytes_xfered = 0;\n+\telse\n+\t\tdata->bytes_xfered = data->blksz * data->blocks;\n+\n+\t/*\n+\t * Need to send CMD12 if -\n+\t * a) open-ended multiblock transfer (no CMD23)\n+\t * b) error in multiblock transfer\n+\t */\n+\tif (data->stop &&\n+\t    (data->error ||\n+\t     !host->mrq->sbc)) {\n+\n+\t\t/*\n+\t\t * The controller needs a reset of internal state machines\n+\t\t * upon error conditions.\n+\t\t */\n+\t\tif (data->error) {\n+\t\t\tbcm2835_mmc_reset(host, SDHCI_RESET_CMD);\n+\t\t\tbcm2835_mmc_reset(host, SDHCI_RESET_DATA);\n+\t\t}\n+\n+\t\tbcm2835_mmc_send_command(host, data->stop);\n+\t} else if (host->use_dma) {\n+\t\thost->wait_for_dma = true;\n+\t} else {\n+\t\ttasklet_schedule(&host->finish_tasklet);\n+\t}\n+}\n+\n+static void bcm2835_mmc_finish_command(struct bcm2835_host *host)\n+{\n+\tint i;\n+\n+\tBUG_ON(host->cmd == NULL);\n+\n+\tif (host->cmd->flags & MMC_RSP_PRESENT) {\n+\t\tif (host->cmd->flags & MMC_RSP_136) {\n+\t\t\t/* CRC is stripped so we need to do some shifting. */\n+\t\t\tfor (i = 0; i < 4; i++) {\n+\t\t\t\thost->cmd->resp[i] = bcm2835_mmc_readl(host,\n+\t\t\t\t\tSDHCI_RESPONSE + (3-i)*4) << 8;\n+\t\t\t\tif (i != 3)\n+\t\t\t\t\thost->cmd->resp[i] |=\n+\t\t\t\t\t\tbcm2835_mmc_readb(host,\n+\t\t\t\t\t\tSDHCI_RESPONSE + (3-i)*4-1);\n+\t\t\t}\n+\t\t} else {\n+\t\t\thost->cmd->resp[0] = bcm2835_mmc_readl(host, SDHCI_RESPONSE);\n+\t\t}\n+\t}\n+\n+\thost->cmd->error = 0;\n+\n+\t/* Finished CMD23, now send actual command. */\n+\tif (host->cmd == host->mrq->sbc) {\n+\t\thost->cmd = NULL;\n+\t\tbcm2835_mmc_send_command(host, host->mrq->cmd);\n+\n+\t\tif (host->mrq->cmd->data && host->use_dma) {\n+\t\t\t/* DMA transfer starts now, PIO starts after interrupt */\n+\t\t\tbcm2835_mmc_transfer_dma(host);\n+\t\t}\n+\t} else {\n+\n+\t\t/* Processed actual command. */\n+\t\tif (host->data && host->data_early)\n+\t\t\tbcm2835_mmc_finish_data(host);\n+\n+\t\tif (!host->cmd->data)\n+\t\t\ttasklet_schedule(&host->finish_tasklet);\n+\n+\t\thost->cmd = NULL;\n+\t}\n+}\n+\n+\n+static void bcm2835_mmc_timeout_timer(struct timer_list *t)\n+{\n+\tstruct bcm2835_host *host = from_timer(host, t, timer);\n+\tunsigned long flags;\n+\n+\tspin_lock_irqsave(&host->lock, flags);\n+\n+\tif (host->mrq) {\n+\t\tpr_err(\"%s: Timeout waiting for hardware interrupt.\\n\",\n+\t\t\tmmc_hostname(host->mmc));\n+\t\tbcm2835_mmc_dumpregs(host);\n+\n+\t\tif (host->data) {\n+\t\t\thost->data->error = -ETIMEDOUT;\n+\t\t\tbcm2835_mmc_finish_data(host);\n+\t\t} else {\n+\t\t\tif (host->cmd)\n+\t\t\t\thost->cmd->error = -ETIMEDOUT;\n+\t\t\telse\n+\t\t\t\thost->mrq->cmd->error = -ETIMEDOUT;\n+\n+\t\t\ttasklet_schedule(&host->finish_tasklet);\n+\t\t}\n+\t}\n+\n+\tspin_unlock_irqrestore(&host->lock, flags);\n+}\n+\n+\n+static void bcm2835_mmc_enable_sdio_irq_nolock(struct bcm2835_host *host, int enable)\n+{\n+\tif (!(host->flags & SDHCI_DEVICE_DEAD)) {\n+\t\tif (enable)\n+\t\t\thost->ier |= SDHCI_INT_CARD_INT;\n+\t\telse\n+\t\t\thost->ier &= ~SDHCI_INT_CARD_INT;\n+\n+\t\tbcm2835_mmc_writel(host, host->ier, SDHCI_INT_ENABLE, 7);\n+\t\tbcm2835_mmc_writel(host, host->ier, SDHCI_SIGNAL_ENABLE, 7);\n+\t}\n+}\n+\n+static void bcm2835_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)\n+{\n+\tstruct bcm2835_host *host = mmc_priv(mmc);\n+\tunsigned long flags;\n+\n+\tspin_lock_irqsave(&host->lock, flags);\n+\tif (enable)\n+\t\thost->flags |= SDHCI_SDIO_IRQ_ENABLED;\n+\telse\n+\t\thost->flags &= ~SDHCI_SDIO_IRQ_ENABLED;\n+\n+\tbcm2835_mmc_enable_sdio_irq_nolock(host, enable);\n+\tspin_unlock_irqrestore(&host->lock, flags);\n+}\n+\n+static void bcm2835_mmc_cmd_irq(struct bcm2835_host *host, u32 intmask)\n+{\n+\n+\tBUG_ON(intmask == 0);\n+\n+\tif (!host->cmd) {\n+\t\tpr_err(\"%s: Got command interrupt 0x%08x even \"\n+\t\t\t\"though no command operation was in progress.\\n\",\n+\t\t\tmmc_hostname(host->mmc), (unsigned)intmask);\n+\t\tbcm2835_mmc_dumpregs(host);\n+\t\treturn;\n+\t}\n+\n+\tif (intmask & SDHCI_INT_TIMEOUT)\n+\t\thost->cmd->error = -ETIMEDOUT;\n+\telse if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |\n+\t\t\tSDHCI_INT_INDEX)) {\n+\t\t\thost->cmd->error = -EILSEQ;\n+\t}\n+\n+\tif (host->cmd->error) {\n+\t\ttasklet_schedule(&host->finish_tasklet);\n+\t\treturn;\n+\t}\n+\n+\tif (intmask & SDHCI_INT_RESPONSE)\n+\t\tbcm2835_mmc_finish_command(host);\n+\n+}\n+\n+static void bcm2835_mmc_data_irq(struct bcm2835_host *host, u32 intmask)\n+{\n+\tstruct dma_chan *dma_chan;\n+\tu32 dir_data;\n+\n+\tBUG_ON(intmask == 0);\n+\n+\tif (!host->data) {\n+\t\t/*\n+\t\t * The \"data complete\" interrupt is also used to\n+\t\t * indicate that a busy state has ended. See comment\n+\t\t * above in sdhci_cmd_irq().\n+\t\t */\n+\t\tif (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {\n+\t\t\tif (intmask & SDHCI_INT_DATA_END) {\n+\t\t\t\tbcm2835_mmc_finish_command(host);\n+\t\t\t\treturn;\n+\t\t\t}\n+\t\t}\n+\n+\t\tpr_debug(\"%s: Got data interrupt 0x%08x even \"\n+\t\t\t\"though no data operation was in progress.\\n\",\n+\t\t\tmmc_hostname(host->mmc), (unsigned)intmask);\n+\t\tbcm2835_mmc_dumpregs(host);\n+\n+\t\treturn;\n+\t}\n+\n+\tif (intmask & SDHCI_INT_DATA_TIMEOUT)\n+\t\thost->data->error = -ETIMEDOUT;\n+\telse if (intmask & SDHCI_INT_DATA_END_BIT)\n+\t\thost->data->error = -EILSEQ;\n+\telse if ((intmask & SDHCI_INT_DATA_CRC) &&\n+\t\tSDHCI_GET_CMD(bcm2835_mmc_readw(host, SDHCI_COMMAND))\n+\t\t\t!= MMC_BUS_TEST_R)\n+\t\thost->data->error = -EILSEQ;\n+\n+\tif (host->use_dma) {\n+\t\tif  (host->data->flags & MMC_DATA_WRITE) {\n+\t\t\t/* IRQ handled here */\n+\n+\t\t\tdma_chan = host->dma_chan_rxtx;\n+\t\t\tdir_data = DMA_TO_DEVICE;\n+\t\t\tdma_unmap_sg(dma_chan->device->dev,\n+\t\t\t\t host->data->sg, host->data->sg_len,\n+\t\t\t\t dir_data);\n+\n+\t\t\tbcm2835_mmc_finish_data(host);\n+\t\t}\n+\n+\t} else {\n+\t\tif (host->data->error)\n+\t\t\tbcm2835_mmc_finish_data(host);\n+\t\telse {\n+\t\t\tif (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))\n+\t\t\t\tbcm2835_mmc_transfer_pio(host);\n+\n+\t\t\tif (intmask & SDHCI_INT_DATA_END) {\n+\t\t\t\tif (host->cmd) {\n+\t\t\t\t\t/*\n+\t\t\t\t\t * Data managed to finish before the\n+\t\t\t\t\t * command completed. Make sure we do\n+\t\t\t\t\t * things in the proper order.\n+\t\t\t\t\t */\n+\t\t\t\t\thost->data_early = 1;\n+\t\t\t\t} else {\n+\t\t\t\t\tbcm2835_mmc_finish_data(host);\n+\t\t\t\t}\n+\t\t\t}\n+\t\t}\n+\t}\n+}\n+\n+\n+static irqreturn_t bcm2835_mmc_irq(int irq, void *dev_id)\n+{\n+\tirqreturn_t result = IRQ_NONE;\n+\tstruct bcm2835_host *host = dev_id;\n+\tu32 intmask, mask, unexpected = 0;\n+\tint max_loops = 16;\n+\n+\tspin_lock(&host->lock);\n+\n+\tintmask = bcm2835_mmc_readl(host, SDHCI_INT_STATUS);\n+\n+\tif (!intmask || intmask == 0xffffffff) {\n+\t\tresult = IRQ_NONE;\n+\t\tgoto out;\n+\t}\n+\n+\tdo {\n+\t\t/* Clear selected interrupts. */\n+\t\tmask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |\n+\t\t\t\t  SDHCI_INT_BUS_POWER);\n+\t\tbcm2835_mmc_writel(host, mask, SDHCI_INT_STATUS, 8);\n+\n+\n+\t\tif (intmask & SDHCI_INT_CMD_MASK)\n+\t\t\tbcm2835_mmc_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);\n+\n+\t\tif (intmask & SDHCI_INT_DATA_MASK)\n+\t\t\tbcm2835_mmc_data_irq(host, intmask & SDHCI_INT_DATA_MASK);\n+\n+\t\tif (intmask & SDHCI_INT_BUS_POWER)\n+\t\t\tpr_err(\"%s: Card is consuming too much power!\\n\",\n+\t\t\t\tmmc_hostname(host->mmc));\n+\n+\t\tif (intmask & SDHCI_INT_CARD_INT) {\n+\t\t\tbcm2835_mmc_enable_sdio_irq_nolock(host, false);\n+\t\t\tsdio_signal_irq(host->mmc);\n+\t\t}\n+\n+\t\tintmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |\n+\t\t\t     SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |\n+\t\t\t     SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |\n+\t\t\t     SDHCI_INT_CARD_INT);\n+\n+\t\tif (intmask) {\n+\t\t\tunexpected |= intmask;\n+\t\t\tbcm2835_mmc_writel(host, intmask, SDHCI_INT_STATUS, 9);\n+\t\t}\n+\n+\t\tif (result == IRQ_NONE)\n+\t\t\tresult = IRQ_HANDLED;\n+\n+\t\tintmask = bcm2835_mmc_readl(host, SDHCI_INT_STATUS);\n+\t} while (intmask && --max_loops);\n+out:\n+\tspin_unlock(&host->lock);\n+\n+\tif (unexpected) {\n+\t\tpr_err(\"%s: Unexpected interrupt 0x%08x.\\n\",\n+\t\t\t   mmc_hostname(host->mmc), unexpected);\n+\t\tbcm2835_mmc_dumpregs(host);\n+\t}\n+\n+\treturn result;\n+}\n+\n+\n+static void bcm2835_mmc_ack_sdio_irq(struct mmc_host *mmc)\n+{\n+\tstruct bcm2835_host *host = mmc_priv(mmc);\n+\tunsigned long flags;\n+\n+\tspin_lock_irqsave(&host->lock, flags);\n+\tif (host->flags & SDHCI_SDIO_IRQ_ENABLED)\n+\t\tbcm2835_mmc_enable_sdio_irq_nolock(host, true);\n+\tspin_unlock_irqrestore(&host->lock, flags);\n+}\n+\n+void bcm2835_mmc_set_clock(struct bcm2835_host *host, unsigned int clock)\n+{\n+\tint div = 0; /* Initialized for compiler warning */\n+\tint real_div = div, clk_mul = 1;\n+\tu16 clk = 0;\n+\tunsigned long timeout;\n+\tunsigned int input_clock = clock;\n+\n+\tif (host->overclock_50 && (clock == 50000000))\n+\t\tclock = host->overclock_50 * 1000000 + 999999;\n+\n+\thost->mmc->actual_clock = 0;\n+\n+\tbcm2835_mmc_writew(host, 0, SDHCI_CLOCK_CONTROL);\n+\n+\tif (clock == 0)\n+\t\treturn;\n+\n+\t/* Version 3.00 divisors must be a multiple of 2. */\n+\tif (host->max_clk <= clock)\n+\t\tdiv = 1;\n+\telse {\n+\t\tfor (div = 2; div < SDHCI_MAX_DIV_SPEC_300;\n+\t\t\t div += 2) {\n+\t\t\tif ((host->max_clk / div) <= clock)\n+\t\t\t\tbreak;\n+\t\t}\n+\t}\n+\n+\treal_div = div;\n+\tdiv >>= 1;\n+\n+\tif (real_div)\n+\t\tclock = (host->max_clk * clk_mul) / real_div;\n+\thost->mmc->actual_clock = clock;\n+\n+\tif ((clock > input_clock) && (clock > host->max_overclock)) {\n+\t\tpr_warn(\"%s: Overclocking to %dHz\\n\",\n+\t\t\tmmc_hostname(host->mmc), clock);\n+\t\thost->max_overclock = clock;\n+\t}\n+\n+\tclk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;\n+\tclk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)\n+\t\t<< SDHCI_DIVIDER_HI_SHIFT;\n+\tclk |= SDHCI_CLOCK_INT_EN;\n+\tbcm2835_mmc_writew(host, clk, SDHCI_CLOCK_CONTROL);\n+\n+\t/* Wait max 20 ms */\n+\ttimeout = 20;\n+\twhile (!((clk = bcm2835_mmc_readw(host, SDHCI_CLOCK_CONTROL))\n+\t\t& SDHCI_CLOCK_INT_STABLE)) {\n+\t\tif (timeout == 0) {\n+\t\t\tpr_err(\"%s: Internal clock never \"\n+\t\t\t\t\"stabilised.\\n\", mmc_hostname(host->mmc));\n+\t\t\tbcm2835_mmc_dumpregs(host);\n+\t\t\treturn;\n+\t\t}\n+\t\ttimeout--;\n+\t\tmdelay(1);\n+\t}\n+\n+\tif (20-timeout > 10 && 20-timeout > host->max_delay) {\n+\t\thost->max_delay = 20-timeout;\n+\t\tpr_warn(\"Warning: MMC controller hung for %d ms\\n\", host->max_delay);\n+\t}\n+\n+\tclk |= SDHCI_CLOCK_CARD_EN;\n+\tbcm2835_mmc_writew(host, clk, SDHCI_CLOCK_CONTROL);\n+}\n+\n+static void bcm2835_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)\n+{\n+\tstruct bcm2835_host *host;\n+\tunsigned long flags;\n+\n+\thost = mmc_priv(mmc);\n+\n+\tspin_lock_irqsave(&host->lock, flags);\n+\n+\tWARN_ON(host->mrq != NULL);\n+\n+\thost->mrq = mrq;\n+\n+\tif (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))\n+\t\tbcm2835_mmc_send_command(host, mrq->sbc);\n+\telse\n+\t\tbcm2835_mmc_send_command(host, mrq->cmd);\n+\n+\tspin_unlock_irqrestore(&host->lock, flags);\n+\n+\tif (!(mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23)) && mrq->cmd->data && host->use_dma) {\n+\t\t/* DMA transfer starts now, PIO starts after interrupt */\n+\t\tbcm2835_mmc_transfer_dma(host);\n+\t}\n+}\n+\n+\n+static void bcm2835_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)\n+{\n+\n+\tstruct bcm2835_host *host = mmc_priv(mmc);\n+\tunsigned long flags;\n+\tu8 ctrl;\n+\tu16 clk, ctrl_2;\n+\n+\tpr_debug(\"bcm2835_mmc_set_ios: clock %d, pwr %d, bus_width %d, timing %d, vdd %d, drv_type %d\\n\",\n+\t\t ios->clock, ios->power_mode, ios->bus_width,\n+\t\t ios->timing, ios->signal_voltage, ios->drv_type);\n+\n+\tspin_lock_irqsave(&host->lock, flags);\n+\n+\tif (!ios->clock || ios->clock != host->clock) {\n+\t\tbcm2835_mmc_set_clock(host, ios->clock);\n+\t\thost->clock = ios->clock;\n+\t}\n+\n+\tif (host->pwr != SDHCI_POWER_330) {\n+\t\thost->pwr = SDHCI_POWER_330;\n+\t\tbcm2835_mmc_writeb(host, SDHCI_POWER_330 | SDHCI_POWER_ON, SDHCI_POWER_CONTROL);\n+\t}\n+\n+\tctrl = bcm2835_mmc_readb(host, SDHCI_HOST_CONTROL);\n+\n+\t/* set bus width */\n+\tctrl &= ~SDHCI_CTRL_8BITBUS;\n+\tif (ios->bus_width == MMC_BUS_WIDTH_4)\n+\t\tctrl |= SDHCI_CTRL_4BITBUS;\n+\telse\n+\t\tctrl &= ~SDHCI_CTRL_4BITBUS;\n+\n+\tctrl &= ~SDHCI_CTRL_HISPD; /* NO_HISPD_BIT */\n+\n+\n+\tbcm2835_mmc_writeb(host, ctrl, SDHCI_HOST_CONTROL);\n+\t/*\n+\t * We only need to set Driver Strength if the\n+\t * preset value enable is not set.\n+\t */\n+\tctrl_2 = bcm2835_mmc_readw(host, SDHCI_HOST_CONTROL2);\n+\tctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;\n+\tif (ios->drv_type == MMC_SET_DRIVER_TYPE_A)\n+\t\tctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;\n+\telse if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)\n+\t\tctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;\n+\n+\tbcm2835_mmc_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);\n+\n+\t/* Reset SD Clock Enable */\n+\tclk = bcm2835_mmc_readw(host, SDHCI_CLOCK_CONTROL);\n+\tclk &= ~SDHCI_CLOCK_CARD_EN;\n+\tbcm2835_mmc_writew(host, clk, SDHCI_CLOCK_CONTROL);\n+\n+\t/* Re-enable SD Clock */\n+\tbcm2835_mmc_set_clock(host, host->clock);\n+\tbcm2835_mmc_writeb(host, ctrl, SDHCI_HOST_CONTROL);\n+\n+\tspin_unlock_irqrestore(&host->lock, flags);\n+}\n+\n+\n+static struct mmc_host_ops bcm2835_ops = {\n+\t.request = bcm2835_mmc_request,\n+\t.set_ios = bcm2835_mmc_set_ios,\n+\t.enable_sdio_irq = bcm2835_mmc_enable_sdio_irq,\n+\t.ack_sdio_irq = bcm2835_mmc_ack_sdio_irq,\n+};\n+\n+\n+static void bcm2835_mmc_tasklet_finish(unsigned long param)\n+{\n+\tstruct bcm2835_host *host;\n+\tunsigned long flags;\n+\tstruct mmc_request *mrq;\n+\n+\thost = (struct bcm2835_host *)param;\n+\n+\tspin_lock_irqsave(&host->lock, flags);\n+\n+\t/*\n+\t * If this tasklet gets rescheduled while running, it will\n+\t * be run again afterwards but without any active request.\n+\t */\n+\tif (!host->mrq) {\n+\t\tspin_unlock_irqrestore(&host->lock, flags);\n+\t\treturn;\n+\t}\n+\n+\tdel_timer(&host->timer);\n+\n+\tmrq = host->mrq;\n+\n+\t/*\n+\t * The controller needs a reset of internal state machines\n+\t * upon error conditions.\n+\t */\n+\tif (!(host->flags & SDHCI_DEVICE_DEAD) &&\n+\t    ((mrq->cmd && mrq->cmd->error) ||\n+\t\t (mrq->data && (mrq->data->error ||\n+\t\t  (mrq->data->stop && mrq->data->stop->error))))) {\n+\n+\t\tspin_unlock_irqrestore(&host->lock, flags);\n+\t\tbcm2835_mmc_reset(host, SDHCI_RESET_CMD);\n+\t\tbcm2835_mmc_reset(host, SDHCI_RESET_DATA);\n+\t\tspin_lock_irqsave(&host->lock, flags);\n+\t}\n+\n+\thost->mrq = NULL;\n+\thost->cmd = NULL;\n+\thost->data = NULL;\n+\n+\tspin_unlock_irqrestore(&host->lock, flags);\n+\tmmc_request_done(host->mmc, mrq);\n+}\n+\n+\n+\n+static int bcm2835_mmc_add_host(struct bcm2835_host *host)\n+{\n+\tstruct mmc_host *mmc = host->mmc;\n+\tstruct device *dev = mmc->parent;\n+#ifndef FORCE_PIO\n+\tstruct dma_slave_config cfg;\n+#endif\n+\tint ret;\n+\n+\tbcm2835_mmc_reset(host, SDHCI_RESET_ALL);\n+\n+\thost->clk_mul = 0;\n+\n+\tif (!mmc->f_max || mmc->f_max > host->max_clk)\n+\t\tmmc->f_max = host->max_clk;\n+\tmmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;\n+\n+\t/* SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK */\n+\thost->timeout_clk = mmc->f_max / 1000;\n+\tmmc->max_busy_timeout = (1 << 27) / host->timeout_clk;\n+\n+\t/* host controller capabilities */\n+\tmmc->caps |= MMC_CAP_CMD23 | MMC_CAP_NEEDS_POLL |\n+\t\tMMC_CAP_SDIO_IRQ | MMC_CAP_SD_HIGHSPEED |\n+\t\tMMC_CAP_MMC_HIGHSPEED;\n+\n+\tmmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;\n+\n+\thost->flags = SDHCI_AUTO_CMD23;\n+\n+\tdev_info(dev, \"mmc_debug:%x mmc_debug2:%x\\n\", mmc_debug, mmc_debug2);\n+#ifdef FORCE_PIO\n+\tdev_info(dev, \"Forcing PIO mode\\n\");\n+\thost->have_dma = false;\n+#else\n+\tif (IS_ERR_OR_NULL(host->dma_chan_rxtx)) {\n+\t\tdev_err(dev, \"%s: Unable to initialise DMA channel. Falling back to PIO\\n\",\n+\t\t\tDRIVER_NAME);\n+\t\thost->have_dma = false;\n+\t} else {\n+\t\tdev_info(dev, \"DMA channel allocated\");\n+\n+\t\tcfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;\n+\t\tcfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;\n+\t\tcfg.slave_id = 11;\t\t/* DREQ channel */\n+\n+\t\t/* Validate the slave configurations */\n+\n+\t\tcfg.direction = DMA_MEM_TO_DEV;\n+\t\tcfg.src_addr = 0;\n+\t\tcfg.dst_addr = host->bus_addr + SDHCI_BUFFER;\n+\n+\t\tret = dmaengine_slave_config(host->dma_chan_rxtx, &cfg);\n+\n+\t\tif (ret == 0) {\n+\t\t\thost->dma_cfg_tx = cfg;\n+\n+\t\t\tcfg.direction = DMA_DEV_TO_MEM;\n+\t\t\tcfg.src_addr = host->bus_addr + SDHCI_BUFFER;\n+\t\t\tcfg.dst_addr = 0;\n+\n+\t\t\tret = dmaengine_slave_config(host->dma_chan_rxtx, &cfg);\n+\t\t}\n+\n+\t\tif (ret == 0) {\n+\t\t\thost->dma_cfg_rx = cfg;\n+\n+\t\t\thost->have_dma = true;\n+\t\t} else {\n+\t\t\tpr_err(\"%s: unable to configure DMA channel. \"\n+\t\t\t       \"Falling back to PIO\\n\",\n+\t\t\t       mmc_hostname(mmc));\n+\t\t\tdma_release_channel(host->dma_chan_rxtx);\n+\t\t\thost->dma_chan_rxtx = NULL;\n+\t\t\thost->have_dma = false;\n+\t\t}\n+\t}\n+#endif\n+\tmmc->max_segs = 128;\n+\tif (swiotlb_max_segment())\n+\t\tmmc->max_req_size = (1 << IO_TLB_SHIFT) * IO_TLB_SEGSIZE;\n+\telse\n+\t\tmmc->max_req_size = 524288;\n+\tmmc->max_seg_size = mmc->max_req_size;\n+\tmmc->max_blk_size = 512;\n+\tmmc->max_blk_count =  65535;\n+\n+\t/* report supported voltage ranges */\n+\tmmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;\n+\n+\ttasklet_init(&host->finish_tasklet,\n+\t\tbcm2835_mmc_tasklet_finish, (unsigned long)host);\n+\n+\ttimer_setup(&host->timer, bcm2835_mmc_timeout_timer, 0);\n+\tinit_waitqueue_head(&host->buf_ready_int);\n+\n+\tbcm2835_mmc_init(host, 0);\n+\tret = request_irq(host->irq, bcm2835_mmc_irq, IRQF_SHARED,\n+\t\t\t\t   mmc_hostname(mmc), host);\n+\tif (ret) {\n+\t\tdev_err(dev, \"Failed to request IRQ %d: %d\\n\", host->irq, ret);\n+\t\tgoto untasklet;\n+\t}\n+\n+\tret = mmc_add_host(mmc);\n+\tif (ret) {\n+\t\tdev_err(dev, \"could not add MMC host\\n\");\n+\t\tgoto free_irq;\n+\t}\n+\n+\treturn 0;\n+\n+free_irq:\n+\tfree_irq(host->irq, host);\n+untasklet:\n+\ttasklet_kill(&host->finish_tasklet);\n+\n+\treturn ret;\n+}\n+\n+static int bcm2835_mmc_probe(struct platform_device *pdev)\n+{\n+\tstruct device *dev = &pdev->dev;\n+\tstruct device_node *node = dev->of_node;\n+\tstruct clk *clk;\n+\tstruct resource *iomem;\n+\tstruct bcm2835_host *host;\n+\tstruct mmc_host *mmc;\n+\tconst __be32 *addr;\n+\tint ret;\n+\n+\tmmc = mmc_alloc_host(sizeof(*host), dev);\n+\tif (!mmc)\n+\t\treturn -ENOMEM;\n+\n+\tmmc->ops = &bcm2835_ops;\n+\thost = mmc_priv(mmc);\n+\thost->mmc = mmc;\n+\thost->timeout = msecs_to_jiffies(1000);\n+\tspin_lock_init(&host->lock);\n+\n+\tiomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);\n+\thost->ioaddr = devm_ioremap_resource(dev, iomem);\n+\tif (IS_ERR(host->ioaddr)) {\n+\t\tret = PTR_ERR(host->ioaddr);\n+\t\tgoto err;\n+\t}\n+\n+\taddr = of_get_address(node, 0, NULL, NULL);\n+\tif (!addr) {\n+\t\tdev_err(dev, \"could not get DMA-register address\\n\");\n+\t\tret = -ENODEV;\n+\t\tgoto err;\n+\t}\n+\thost->bus_addr = be32_to_cpup(addr);\n+\tpr_debug(\" - ioaddr %lx, iomem->start %lx, bus_addr %lx\\n\",\n+\t\t (unsigned long)host->ioaddr,\n+\t\t (unsigned long)iomem->start,\n+\t\t (unsigned long)host->bus_addr);\n+\n+#ifndef FORCE_PIO\n+\tif (node) {\n+\t\thost->dma_chan_rxtx = dma_request_slave_channel(dev, \"rx-tx\");\n+\t\tif (!host->dma_chan_rxtx)\n+\t\t\thost->dma_chan_rxtx =\n+\t\t\t\tdma_request_slave_channel(dev, \"tx\");\n+\t\tif (!host->dma_chan_rxtx)\n+\t\t\thost->dma_chan_rxtx =\n+\t\t\t\tdma_request_slave_channel(dev, \"rx\");\n+\t} else {\n+\t\tdma_cap_mask_t mask;\n+\n+\t\tdma_cap_zero(mask);\n+\t\t/* we don't care about the channel, any would work */\n+\t\tdma_cap_set(DMA_SLAVE, mask);\n+\t\thost->dma_chan_rxtx = dma_request_channel(mask, NULL, NULL);\n+\t}\n+#endif\n+\tclk = devm_clk_get(dev, NULL);\n+\tif (IS_ERR(clk)) {\n+\t\tret = PTR_ERR(clk);\n+\t\tif (ret == -EPROBE_DEFER)\n+\t\t\tdev_info(dev, \"could not get clk, deferring probe\\n\");\n+\t\telse\n+\t\t\tdev_err(dev, \"could not get clk\\n\");\n+\t\tgoto err;\n+\t}\n+\n+\thost->max_clk = clk_get_rate(clk);\n+\n+\thost->irq = platform_get_irq(pdev, 0);\n+\tif (host->irq <= 0) {\n+\t\tdev_err(dev, \"get IRQ failed\\n\");\n+\t\tret = -EINVAL;\n+\t\tgoto err;\n+\t}\n+\n+\tif (node) {\n+\t\tmmc_of_parse(mmc);\n+\n+\t\t/* Read any custom properties */\n+\t\tof_property_read_u32(node,\n+\t\t\t\t     \"brcm,overclock-50\",\n+\t\t\t\t     &host->overclock_50);\n+\t} else {\n+\t\tmmc->caps |= MMC_CAP_4_BIT_DATA;\n+\t}\n+\n+\tret = bcm2835_mmc_add_host(host);\n+\tif (ret)\n+\t\tgoto err;\n+\n+\tplatform_set_drvdata(pdev, host);\n+\n+\treturn 0;\n+err:\n+\tif (host->dma_chan_rxtx)\n+\t\tdma_release_channel(host->dma_chan_rxtx);\n+\tmmc_free_host(mmc);\n+\n+\treturn ret;\n+}\n+\n+static int bcm2835_mmc_remove(struct platform_device *pdev)\n+{\n+\tstruct bcm2835_host *host = platform_get_drvdata(pdev);\n+\tunsigned long flags;\n+\tint dead;\n+\tu32 scratch;\n+\n+\tdead = 0;\n+\tscratch = bcm2835_mmc_readl(host, SDHCI_INT_STATUS);\n+\tif (scratch == (u32)-1)\n+\t\tdead = 1;\n+\n+\n+\tif (dead) {\n+\t\tspin_lock_irqsave(&host->lock, flags);\n+\n+\t\thost->flags |= SDHCI_DEVICE_DEAD;\n+\n+\t\tif (host->mrq) {\n+\t\t\tpr_err(\"%s: Controller removed during \"\n+\t\t\t\t\" transfer!\\n\", mmc_hostname(host->mmc));\n+\n+\t\t\thost->mrq->cmd->error = -ENOMEDIUM;\n+\t\t\ttasklet_schedule(&host->finish_tasklet);\n+\t\t}\n+\n+\t\tspin_unlock_irqrestore(&host->lock, flags);\n+\t}\n+\n+\tmmc_remove_host(host->mmc);\n+\n+\tif (!dead)\n+\t\tbcm2835_mmc_reset(host, SDHCI_RESET_ALL);\n+\n+\tfree_irq(host->irq, host);\n+\n+\tdel_timer_sync(&host->timer);\n+\n+\ttasklet_kill(&host->finish_tasklet);\n+\n+\tif (host->dma_chan_rxtx)\n+\t\tdma_release_channel(host->dma_chan_rxtx);\n+\n+\tmmc_free_host(host->mmc);\n+\n+\treturn 0;\n+}\n+\n+\n+static const struct of_device_id bcm2835_mmc_match[] = {\n+\t{ .compatible = \"brcm,bcm2835-mmc\" },\n+\t{ }\n+};\n+MODULE_DEVICE_TABLE(of, bcm2835_mmc_match);\n+\n+\n+\n+static struct platform_driver bcm2835_mmc_driver = {\n+\t.probe      = bcm2835_mmc_probe,\n+\t.remove     = bcm2835_mmc_remove,\n+\t.driver     = {\n+\t\t.name\t\t= DRIVER_NAME,\n+\t\t.owner\t\t= THIS_MODULE,\n+\t\t.of_match_table\t= bcm2835_mmc_match,\n+\t},\n+};\n+module_platform_driver(bcm2835_mmc_driver);\n+\n+module_param(mmc_debug, uint, 0644);\n+module_param(mmc_debug2, uint, 0644);\n+MODULE_ALIAS(\"platform:mmc-bcm2835\");\n+MODULE_DESCRIPTION(\"BCM2835 SDHCI driver\");\n+MODULE_LICENSE(\"GPL v2\");\n+MODULE_AUTHOR(\"Gellert Weisz\");\n--- a/include/linux/mmc/card.h\n+++ b/include/linux/mmc/card.h\n@@ -271,6 +271,8 @@ struct mmc_card {\n #define MMC_QUIRK_TRIM_BROKEN\t(1<<12)\t\t/* Skip trim */\n #define MMC_QUIRK_BROKEN_HPI\t(1<<13)\t\t/* Disable broken HPI support */\n \n+#define MMC_QUIRK_ERASE_BROKEN\t(1<<31)\t\t/* Skip erase */\n+\n \tbool\t\t\treenable_cmdq;\t/* Re-enable Command Queue */\n \n \tunsigned int\t\terase_size;\t/* erase size in sectors */\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0047-Adding-bcm2835-sdhost-driver-and-an-overlay-to-enabl.patch",
    "content": "From dd8b26a3df74f3022a6ddc794049a08d7190be3a Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.org>\nDate: Wed, 25 Mar 2015 17:49:47 +0000\nSubject: [PATCH] Adding bcm2835-sdhost driver, and an overlay to\n enable it\n\nBCM2835 has two SD card interfaces. This driver uses the other one.\n\nbcm2835-sdhost: Error handling fix, and code clarification\n\nbcm2835-sdhost: Adding overclocking option\n\nAllow a different clock speed to be substitued for a requested 50MHz.\nThis option is exposed using the \"overclock_50\" DT parameter.\nNote that the sdhost interface is restricted to integer divisions of\ncore_freq, and the highest sensible option for a core_freq of 250MHz\nis 84 (250/3 = 83.3MHz), the next being 125 (250/2) which is much too\nhigh.\n\nUse at your own risk.\n\nbcm2835-sdhost: Round up the overclock, so 62 works for 62.5Mhz\n\nAlso only warn once for each overclock setting.\n\nbcm2835-sdhost: Improve error handling and recovery\n\n1) Expose the hw_reset method to the MMC framework, removing many\n   internal calls by the driver.\n\n2) Reduce overclock setting on error.\n\n3) Increase timeout to cope with high capacity cards.\n\n4) Add properties and parameters to control pio_limit and debug.\n\n5) Reduce messages at probe time.\n\nbcm2835-sdhost: Further improve overclock back-off\n\nbcm2835-sdhost: Clear HBLC for PIO mode\n\nAlso update pio_limit default in overlay README.\n\nbcm2835-sdhost: Add the ERASE capability\n\nSee: https://github.com/raspberrypi/linux/issues/1076\n\nbcm2835-sdhost: Ignore CRC7 for MMC CMD1\n\nIt seems that the sdhost interface returns CRC7 errors for CMD1,\nwhich is the MMC-specific SEND_OP_COND. Returning these errors to\nthe MMC layer causes a downward spiral, but ignoring them seems\nto be harmless.\n\nbcm2835-mmc/sdhost: Remove ARCH_BCM2835 differences\n\nThe bcm2835-mmc driver (and -sdhost driver that copied from it)\ncontains code to handle SDIO interrupts in a threaded interrupt\nhandler rather than waking the MMC framework thread. The change\nfollows a patch from Russell King that adds the facility as the\npreferred way of working.\n\nHowever, the new code path is only present in ARCH_BCM2835\nbuilds, which I have taken to be a way of testing the waters\nrather than making the change across the board; I can't see\nany technical reason why it wouldn't be enabled for MACH_BCM270X\nbuilds. So this patch standardises on the ARCH_BCM2835 code,\nremoving the old code paths.\n\nbcm2835-sdhost: Don't log timeout errors unless debug=1\n\nThe MMC card-discovery process generates timeouts. This is\nexpected behaviour, so reporting it to the user serves no purpose.\nSuppress the reporting of timeout errors unless the debug flag\nis on.\n\nbcm2835-sdhost: Add workaround for odd behaviour on some cards\n\nFor reasons not understood, the sdhost driver fails when reading\nsectors very near the end of some SD cards. The problem could\nbe related to the similar issue that reading the final sector\nof any card as part of a multiple read never completes, and the\nworkaround is an extension of the mechanism introduced to solve\nthat problem which ensures those sectors are always read singly.\n\nbcm2835-sdhost: Major revision\n\nThis is a significant revision of the bcm2835-sdhost driver. It\nimproves on the original in a number of ways:\n\n1) Through the use of CMD23 for reads it appears to avoid problems\n   reading some sectors on certain high speed cards.\n2) Better atomicity to prevent crashes.\n3) Higher performance.\n4) Activity logging included, for easier diagnosis in the event\n   of a problem.\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.org>\n\nbcm2835-sdhost: Restore ATOMIC flag to PIO sg mapping\n\nAllocation problems have been seen in a wireless driver, and\nthis is the only change which might have been responsible.\n\nSQUASH: bcm2835-sdhost: Only claim one DMA channel\n\nWith both MMC controllers enabled there are few DMA channels left. The\nbcm2835-sdhost driver only uses DMA in one direction at a time, so it\ndoesn't need to claim two channels.\n\nSee: https://github.com/raspberrypi/linux/issues/1327\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.org>\n\nbcm2835-sdhost: Workaround for \"slow\" sectors\n\nSome cards have been seen to cause timeouts after certain sectors are\nread. This workaround enforces a minimum delay between the stop after\nreading one of those sectors and a subsequent data command.\n\nUsing CMD23 (SET_BLOCK_COUNT) avoids this problem, so good cards will\nnot be penalised by this workaround.\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.org>\n\nbcm2835-sdhost: Firmware manages the clock divisor\n\nThe bcm2835-sdhost driver hands control of the CDIV clock divisor\nregister to matching firmware, allowing it to adjust to a changing\ncore clock. This removes the need to use the performance governor or\nto enable io_is_busy on the on-demand governor in order to get the\nbest SD performance.\n\nN.B. As SD clocks must be an integer divisor of the core clock, it is\npossible that the SD clock for \"turbo\" mode can be different (even\nlower) than \"normal\" mode.\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.org>\n\nbcm2835-sdhost: Reset the clock in task context\n\nSince reprogramming the clock can now involve a round-trip to the\nfirmware it must not be done at atomic context, and a tasklet\nis not a task.\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.org>\n\nbcm2835-sdhost: Don't exit cmd wait loop on error\n\nThe FAIL flag can be set in the CMD register before command processing\nis complete, leading to spurious \"failed to complete\" errors. This has\nthe effect of promoting harmless CRC7 errors during CMD1 processing\ninto errors that can delay and even prevent booting.\n\nAlso:\n1) Convert the last KERN_ERROR message in the register dumping to\n   KERN_INFO.\n2) Remove an unnecessary reset call from  bcm2835_sdhost_add_host.\n\nSee: https://github.com/raspberrypi/linux/pull/1492\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.org>\n\nbcm2835-sdhost: mmc_card_blockaddr fix\n\nGet the definition of mmc_card_blockaddr from drivers/mmc/core/card.h.\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.org>\n\nbcm2835-sdhost: New timer API\n\nmmc: bcm2835-sdhost: Support underclocking\n\nSupport underclocking of the SD bus in two ways:\n1. using the max-frequency DT property (which currently has no DT\n   parameter), and\n2. using the exiting sd_overclock parameter.\n\nThe two methods differ slightly - in the former the MMC subsystem is\naware of the underclocking, while in the latter it isn't - but the\nend results should be the same.\n\nSee: https://github.com/raspberrypi/linux/issues/2350\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.org>\n\nmmc: bcm2835-sdhost: Add include\n\nhighmem.h (needed for kmap_atomic) is pulled in by one of the other\ninclude files, but only with some CONFIG settings. Make the inclusion\nexplicit to cater for cases where the CONFIG setting is absent.\n\nSee: https://github.com/raspberrypi/linux/issues/2366\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.org>\n\nmmc/bcm2835-sdhost: Recover from MMC_SEND_EXT_CSD\n\nIf the user issues an \"mmc extcsd read\", the SD controller receives\nwhat it thinks is a SEND_IF_COND command with an unexpected data block.\nThe resulting operations leave the FSM stuck in READWAIT, a state which\npersists until the MMC framework resets the controller, by which point\nthe root filesystem is likely to have been unmounted.\n\nA less heavyweight solution is to detect the condition and nudge the\nFSM by asserting the (self-clearing) FORCE_DATA_MODE bit.\n\nN.B. This workaround was essentially discovered by accident and without\na full understanding the inner workings of the controller, so it is\nfortunate that the \"fix\" only modifies error paths.\n\nSee: https://github.com/raspberrypi/linux/issues/2728\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.org>\n\nmmc: bcm2835-sdhost: Fix warnings on arm64\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.org>\n\nbcm2835-sdhost: Allow for sg entries that cross pages\n\nThe dma_complete handling code calculates a virtual address for a page\nthen adds an offset, but if the offset is more than a page and HIGHMEM\nis in use then the summed address could be in an unmapped (or just\nincorrect) page.\n\nThe upstream SDHOST driver allows for this possibility - copy the code\nthat does so.\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.org>\n\nbcm2835-sdhost: Fix DMA channel leak on error/remove\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.org>\n\nmmc: bcm2835-sdhost: Support 64-bit physical addresses\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.org>\n\nbcm2835-sdhost: Replace obsolete struct timeval\n\nstruct timeval has been retired due to the impending linux 32-bit tv_sec\nrollover (only 18 years to go) - timespec64 is the obvious replacement.\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.com>\n---\n drivers/mmc/host/Kconfig          |   10 +\n drivers/mmc/host/Makefile         |    1 +\n drivers/mmc/host/bcm2835-sdhost.c | 2196 +++++++++++++++++++++++++++++\n 3 files changed, 2207 insertions(+)\n create mode 100644 drivers/mmc/host/bcm2835-sdhost.c\n\n--- a/drivers/mmc/host/Kconfig\n+++ b/drivers/mmc/host/Kconfig\n@@ -34,6 +34,16 @@ config MMC_BCM2835_PIO_DMA_BARRIER\n \n \t  If unsure, say 2 here.\n \n+config MMC_BCM2835_SDHOST\n+\ttristate \"Support for the SDHost controller on BCM2708/9\"\n+\tdepends on ARCH_BCM2835\n+\thelp\n+\t  This selects the SDHost controller on BCM2835/6.\n+\n+\t  If you have a controller with this interface, say Y or M here.\n+\n+\t  If unsure, say N.\n+\n config MMC_DEBUG\n \tbool \"MMC host drivers debugging\"\n \tdepends on MMC != n\n--- a/drivers/mmc/host/Makefile\n+++ b/drivers/mmc/host/Makefile\n@@ -25,6 +25,7 @@ obj-$(CONFIG_MMC_SDHCI_MILBEAUT)\t+= sdhc\n obj-$(CONFIG_MMC_SDHCI_SPEAR)\t+= sdhci-spear.o\n obj-$(CONFIG_MMC_SDHCI_AM654)\t+= sdhci_am654.o\n obj-$(CONFIG_MMC_BCM2835_MMC)\t+= bcm2835-mmc.o\n+obj-$(CONFIG_MMC_BCM2835_SDHOST)\t+= bcm2835-sdhost.o\n obj-$(CONFIG_MMC_WBSD)\t\t+= wbsd.o\n obj-$(CONFIG_MMC_AU1X)\t\t+= au1xmmc.o\n obj-$(CONFIG_MMC_ALCOR)\t+= alcor.o\n--- /dev/null\n+++ b/drivers/mmc/host/bcm2835-sdhost.c\n@@ -0,0 +1,2196 @@\n+/*\n+ * BCM2835 SD host driver.\n+ *\n+ * Author:      Phil Elwell <phil@raspberrypi.org>\n+ *              Copyright (C) 2015-2016 Raspberry Pi (Trading) Ltd.\n+ *\n+ * Based on\n+ *  mmc-bcm2835.c by Gellert Weisz\n+ * which is, in turn, based on\n+ *  sdhci-bcm2708.c by Broadcom\n+ *  sdhci-bcm2835.c by Stephen Warren and Oleksandr Tymoshenko\n+ *  sdhci.c and sdhci-pci.c by Pierre Ossman\n+ *\n+ * This program is free software; you can redistribute it and/or modify it\n+ * under the terms and conditions of the GNU General Public License,\n+ * version 2, as published by the Free Software Foundation.\n+ *\n+ * This program is distributed in the hope it will be useful, but WITHOUT\n+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\n+ * more details.\n+ *\n+ * You should have received a copy of the GNU General Public License\n+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.\n+ */\n+\n+#define FIFO_READ_THRESHOLD     4\n+#define FIFO_WRITE_THRESHOLD    4\n+#define ALLOW_CMD23_READ        1\n+#define ALLOW_CMD23_WRITE       0\n+#define ENABLE_LOG              1\n+#define SDDATA_FIFO_PIO_BURST   8\n+#define CMD_DALLY_US            1\n+\n+#include <linux/delay.h>\n+#include <linux/module.h>\n+#include <linux/io.h>\n+#include <linux/mmc/mmc.h>\n+#include <linux/mmc/host.h>\n+#include <linux/mmc/sd.h>\n+#include <linux/mmc/sdio.h>\n+#include <linux/scatterlist.h>\n+#include <linux/of_address.h>\n+#include <linux/of_irq.h>\n+#include <linux/clk.h>\n+#include <linux/platform_device.h>\n+#include <linux/err.h>\n+#include <linux/blkdev.h>\n+#include <linux/dmaengine.h>\n+#include <linux/dma-mapping.h>\n+#include <linux/of_dma.h>\n+#include <linux/time.h>\n+#include <linux/workqueue.h>\n+#include <linux/interrupt.h>\n+#include <linux/highmem.h>\n+#include <soc/bcm2835/raspberrypi-firmware.h>\n+\n+/* For mmc_card_blockaddr */\n+#include \"../core/card.h\"\n+\n+#define DRIVER_NAME \"sdhost-bcm2835\"\n+\n+#define SDCMD  0x00 /* Command to SD card              - 16 R/W */\n+#define SDARG  0x04 /* Argument to SD card             - 32 R/W */\n+#define SDTOUT 0x08 /* Start value for timeout counter - 32 R/W */\n+#define SDCDIV 0x0c /* Start value for clock divider   - 11 R/W */\n+#define SDRSP0 0x10 /* SD card response (31:0)         - 32 R   */\n+#define SDRSP1 0x14 /* SD card response (63:32)        - 32 R   */\n+#define SDRSP2 0x18 /* SD card response (95:64)        - 32 R   */\n+#define SDRSP3 0x1c /* SD card response (127:96)       - 32 R   */\n+#define SDHSTS 0x20 /* SD host status                  - 11 R   */\n+#define SDVDD  0x30 /* SD card power control           -  1 R/W */\n+#define SDEDM  0x34 /* Emergency Debug Mode            - 13 R/W */\n+#define SDHCFG 0x38 /* Host configuration              -  2 R/W */\n+#define SDHBCT 0x3c /* Host byte count (debug)         - 32 R/W */\n+#define SDDATA 0x40 /* Data to/from SD card            - 32 R/W */\n+#define SDHBLC 0x50 /* Host block count (SDIO/SDHC)    -  9 R/W */\n+\n+#define SDCMD_NEW_FLAG                  0x8000\n+#define SDCMD_FAIL_FLAG                 0x4000\n+#define SDCMD_BUSYWAIT                  0x800\n+#define SDCMD_NO_RESPONSE               0x400\n+#define SDCMD_LONG_RESPONSE             0x200\n+#define SDCMD_WRITE_CMD                 0x80\n+#define SDCMD_READ_CMD                  0x40\n+#define SDCMD_CMD_MASK                  0x3f\n+\n+#define SDCDIV_MAX_CDIV                 0x7ff\n+\n+#define SDHSTS_BUSY_IRPT                0x400\n+#define SDHSTS_BLOCK_IRPT               0x200\n+#define SDHSTS_SDIO_IRPT                0x100\n+#define SDHSTS_REW_TIME_OUT             0x80\n+#define SDHSTS_CMD_TIME_OUT             0x40\n+#define SDHSTS_CRC16_ERROR              0x20\n+#define SDHSTS_CRC7_ERROR               0x10\n+#define SDHSTS_FIFO_ERROR               0x08\n+/* Reserved */\n+/* Reserved */\n+#define SDHSTS_DATA_FLAG                0x01\n+\n+#define SDHSTS_TRANSFER_ERROR_MASK      (SDHSTS_CRC7_ERROR|SDHSTS_CRC16_ERROR|SDHSTS_REW_TIME_OUT|SDHSTS_FIFO_ERROR)\n+#define SDHSTS_ERROR_MASK               (SDHSTS_CMD_TIME_OUT|SDHSTS_TRANSFER_ERROR_MASK)\n+\n+#define SDHCFG_BUSY_IRPT_EN     (1<<10)\n+#define SDHCFG_BLOCK_IRPT_EN    (1<<8)\n+#define SDHCFG_SDIO_IRPT_EN     (1<<5)\n+#define SDHCFG_DATA_IRPT_EN     (1<<4)\n+#define SDHCFG_SLOW_CARD        (1<<3)\n+#define SDHCFG_WIDE_EXT_BUS     (1<<2)\n+#define SDHCFG_WIDE_INT_BUS     (1<<1)\n+#define SDHCFG_REL_CMD_LINE     (1<<0)\n+\n+#define SDEDM_FORCE_DATA_MODE   (1<<19)\n+#define SDEDM_CLOCK_PULSE       (1<<20)\n+#define SDEDM_BYPASS            (1<<21)\n+\n+#define SDEDM_WRITE_THRESHOLD_SHIFT 9\n+#define SDEDM_READ_THRESHOLD_SHIFT 14\n+#define SDEDM_THRESHOLD_MASK     0x1f\n+\n+#define SDEDM_FSM_MASK           0xf\n+#define SDEDM_FSM_IDENTMODE      0x0\n+#define SDEDM_FSM_DATAMODE       0x1\n+#define SDEDM_FSM_READDATA       0x2\n+#define SDEDM_FSM_WRITEDATA      0x3\n+#define SDEDM_FSM_READWAIT       0x4\n+#define SDEDM_FSM_READCRC        0x5\n+#define SDEDM_FSM_WRITECRC       0x6\n+#define SDEDM_FSM_WRITEWAIT1     0x7\n+#define SDEDM_FSM_POWERDOWN      0x8\n+#define SDEDM_FSM_POWERUP        0x9\n+#define SDEDM_FSM_WRITESTART1    0xa\n+#define SDEDM_FSM_WRITESTART2    0xb\n+#define SDEDM_FSM_GENPULSES      0xc\n+#define SDEDM_FSM_WRITEWAIT2     0xd\n+#define SDEDM_FSM_STARTPOWDOWN   0xf\n+\n+#define SDDATA_FIFO_WORDS        16\n+\n+#define USE_CMD23_FLAGS          ((ALLOW_CMD23_READ * MMC_DATA_READ) | \\\n+\t\t\t\t  (ALLOW_CMD23_WRITE * MMC_DATA_WRITE))\n+\n+#define MHZ 1000000\n+\n+\n+struct bcm2835_host {\n+\tspinlock_t\t\tlock;\n+\n+\tvoid __iomem\t\t*ioaddr;\n+\tphys_addr_t\t\tbus_addr;\n+\n+\tstruct mmc_host\t\t*mmc;\n+\n+\tu32\t\t\tpio_timeout;\t/* In jiffies */\n+\n+\tint\t\t\tclock;\t\t/* Current clock speed */\n+\n+\tbool\t\t\tslow_card;\t/* Force 11-bit divisor */\n+\n+\tunsigned int\t\tmax_clk;\t/* Max possible freq */\n+\n+\tstruct tasklet_struct\tfinish_tasklet;\t/* Tasklet structures */\n+\n+\tstruct work_struct\tcmd_wait_wq;\t/* Workqueue function */\n+\n+\tstruct timer_list\ttimer;\t\t/* Timer for timeouts */\n+\n+\tstruct sg_mapping_iter\tsg_miter;\t/* SG state for PIO */\n+\tunsigned int\t\tblocks;\t\t/* remaining PIO blocks */\n+\n+\tint\t\t\tirq;\t\t/* Device IRQ */\n+\n+\tu32\t\t\tcmd_quick_poll_retries;\n+\tu32\t\t\tns_per_fifo_word;\n+\n+\t/* cached registers */\n+\tu32\t\t\thcfg;\n+\tu32\t\t\tcdiv;\n+\n+\tstruct mmc_request\t\t*mrq;\t\t\t/* Current request */\n+\tstruct mmc_command\t\t*cmd;\t\t\t/* Current command */\n+\tstruct mmc_data\t\t\t*data;\t\t\t/* Current data request */\n+\tunsigned int\t\t\tdata_complete:1;\t/* Data finished before cmd */\n+\n+\tunsigned int\t\t\tflush_fifo:1;\t\t/* Drain the fifo when finishing */\n+\n+\tunsigned int\t\t\tuse_busy:1;\t\t/* Wait for busy interrupt */\n+\n+\tunsigned int\t\t\tuse_sbc:1;\t\t/* Send CMD23 */\n+\n+\tunsigned int\t\t\tdebug:1;\t\t/* Enable debug output */\n+\tunsigned int\t\t\tfirmware_sets_cdiv:1;\t/* Let the firmware manage the clock */\n+\tunsigned int\t\t\treset_clock:1;\t\t/* Reset the clock fore the next request */\n+\n+\t/*DMA part*/\n+\tstruct dma_chan\t\t\t*dma_chan_rxtx;\t\t/* DMA channel for reads and writes */\n+\tstruct dma_chan\t\t\t*dma_chan;\t\t/* Channel in use */\n+\tstruct dma_slave_config\t\tdma_cfg_rx;\n+\tstruct dma_slave_config\t\tdma_cfg_tx;\n+\tstruct dma_async_tx_descriptor\t*dma_desc;\n+\tu32\t\t\t\tdma_dir;\n+\tu32\t\t\t\tdrain_words;\n+\tstruct page \t\t\t*drain_page;\n+\tu32\t\t\t\tdrain_offset;\n+\n+\tbool\t\t\t\tallow_dma;\n+\tbool\t\t\t\tuse_dma;\n+\t/*end of DMA part*/\n+\n+\tint\t\t\t\tmax_delay;\t/* maximum length of time spent waiting */\n+\tstruct timespec64\t\tstop_time;\t/* when the last stop was issued */\n+\tu32\t\t\t\tdelay_after_stop; /* minimum time between stop and subsequent data transfer */\n+\tu32\t\t\t\tdelay_after_this_stop; /* minimum time between this stop and subsequent data transfer */\n+\tu32\t\t\t\tuser_overclock_50; /* User's preferred frequency to use when 50MHz is requested (in MHz) */\n+\tu32\t\t\t\toverclock_50;\t/* frequency to use when 50MHz is requested (in MHz) */\n+\tu32\t\t\t\toverclock;\t/* Current frequency if overclocked, else zero */\n+\tu32\t\t\t\tpio_limit;\t/* Maximum block count for PIO (0 = always DMA) */\n+\n+\tu32\t\t\t\tsectors;\t/* Cached card size in sectors */\n+};\n+\n+#if ENABLE_LOG\n+\n+struct log_entry_struct {\n+\tchar event[4];\n+\tu32 timestamp;\n+\tu32 param1;\n+\tu32 param2;\n+};\n+\n+typedef struct log_entry_struct LOG_ENTRY_T;\n+\n+LOG_ENTRY_T *sdhost_log_buf;\n+dma_addr_t sdhost_log_addr;\n+static u32 sdhost_log_idx;\n+static spinlock_t log_lock;\n+static void __iomem *timer_base;\n+\n+#define LOG_ENTRIES (256*1)\n+#define LOG_SIZE (sizeof(LOG_ENTRY_T)*LOG_ENTRIES)\n+\n+static void log_init(struct device *dev, u32 bus_to_phys)\n+{\n+\tspin_lock_init(&log_lock);\n+\tsdhost_log_buf = dma_alloc_coherent(dev, LOG_SIZE, &sdhost_log_addr,\n+\t\t\t\t\t     GFP_KERNEL);\n+\tif (sdhost_log_buf) {\n+\t\tpr_info(\"sdhost: log_buf @ %p (%llx)\\n\",\n+\t\t\tsdhost_log_buf, (u64)sdhost_log_addr);\n+\t\ttimer_base = ioremap(bus_to_phys + 0x7e003000, SZ_4K);\n+\t\tif (!timer_base)\n+\t\t\tpr_err(\"sdhost: failed to remap timer\\n\");\n+\t}\n+\telse\n+\t\tpr_err(\"sdhost: failed to allocate log buf\\n\");\n+}\n+\n+static void log_event_impl(const char *event, u32 param1, u32 param2)\n+{\n+\tif (sdhost_log_buf) {\n+\t\tLOG_ENTRY_T *entry;\n+\t\tunsigned long flags;\n+\n+\t\tspin_lock_irqsave(&log_lock, flags);\n+\n+\t\tentry = sdhost_log_buf + sdhost_log_idx;\n+\t\tmemcpy(entry->event, event, 4);\n+\t\tentry->timestamp = (readl(timer_base + 4) & 0x3fffffff) +\n+\t\t\t(smp_processor_id()<<30);\n+\t\tentry->param1 = param1;\n+\t\tentry->param2 = param2;\n+\t\tsdhost_log_idx = (sdhost_log_idx + 1) % LOG_ENTRIES;\n+\n+\t\tspin_unlock_irqrestore(&log_lock, flags);\n+\t}\n+}\n+\n+static void log_dump(void)\n+{\n+\tif (sdhost_log_buf) {\n+\t\tLOG_ENTRY_T *entry;\n+\t\tunsigned long flags;\n+\t\tint idx;\n+\n+\t\tspin_lock_irqsave(&log_lock, flags);\n+\n+\t\tidx = sdhost_log_idx;\n+\t\tdo {\n+\t\t\tentry = sdhost_log_buf + idx;\n+\t\t\tif (entry->event[0] != '\\0')\n+\t\t\t\tpr_info(\"[%08x] %.4s %x %x\\n\",\n+\t\t\t\t       entry->timestamp,\n+\t\t\t\t       entry->event,\n+\t\t\t\t       entry->param1,\n+\t\t\t\t       entry->param2);\n+\t\t\tidx = (idx + 1) % LOG_ENTRIES;\n+\t\t} while (idx != sdhost_log_idx);\n+\n+\t\tspin_unlock_irqrestore(&log_lock, flags);\n+\t}\n+}\n+\n+#define log_event(event, param1, param2) log_event_impl(event, (u32)(uintptr_t)param1, (u32)(uintptr_t)param2)\n+\n+#else\n+\n+#define log_init(x) (void)0\n+#define log_event(event, param1, param2) (void)0\n+#define log_dump() (void)0\n+\n+#endif\n+\n+static inline void bcm2835_sdhost_write(struct bcm2835_host *host, u32 val, int reg)\n+{\n+\twritel(val, host->ioaddr + reg);\n+}\n+\n+static inline u32 bcm2835_sdhost_read(struct bcm2835_host *host, int reg)\n+{\n+\treturn readl(host->ioaddr + reg);\n+}\n+\n+static inline u32 bcm2835_sdhost_read_relaxed(struct bcm2835_host *host, int reg)\n+{\n+\treturn readl_relaxed(host->ioaddr + reg);\n+}\n+\n+static void bcm2835_sdhost_dumpcmd(struct bcm2835_host *host,\n+\t\t\t\t   struct mmc_command *cmd,\n+\t\t\t\t   const char *label)\n+{\n+\tif (cmd)\n+\t\tpr_info(\"%s:%c%s op %d arg 0x%x flags 0x%x - resp %08x %08x %08x %08x, err %d\\n\",\n+\t\t\tmmc_hostname(host->mmc),\n+\t\t\t(cmd == host->cmd) ? '>' : ' ',\n+\t\t\tlabel, cmd->opcode, cmd->arg, cmd->flags,\n+\t\t\tcmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3],\n+\t\t\tcmd->error);\n+}\n+\n+static void bcm2835_sdhost_dumpregs(struct bcm2835_host *host)\n+{\n+\tif (host->mrq)\n+\t{\n+\t\tbcm2835_sdhost_dumpcmd(host, host->mrq->sbc, \"sbc\");\n+\t\tbcm2835_sdhost_dumpcmd(host, host->mrq->cmd, \"cmd\");\n+\t\tif (host->mrq->data)\n+\t\t\tpr_info(\"%s: data blocks %x blksz %x - err %d\\n\",\n+\t\t\t       mmc_hostname(host->mmc),\n+\t\t\t       host->mrq->data->blocks,\n+\t\t\t       host->mrq->data->blksz,\n+\t\t\t       host->mrq->data->error);\n+\t\tbcm2835_sdhost_dumpcmd(host, host->mrq->stop, \"stop\");\n+\t}\n+\n+\tpr_info(\"%s: =========== REGISTER DUMP ===========\\n\",\n+\t\tmmc_hostname(host->mmc));\n+\n+\tpr_info(\"%s: SDCMD  0x%08x\\n\",\n+\t\tmmc_hostname(host->mmc),\n+\t\tbcm2835_sdhost_read(host, SDCMD));\n+\tpr_info(\"%s: SDARG  0x%08x\\n\",\n+\t\tmmc_hostname(host->mmc),\n+\t\tbcm2835_sdhost_read(host, SDARG));\n+\tpr_info(\"%s: SDTOUT 0x%08x\\n\",\n+\t\tmmc_hostname(host->mmc),\n+\t\tbcm2835_sdhost_read(host, SDTOUT));\n+\tpr_info(\"%s: SDCDIV 0x%08x\\n\",\n+\t\tmmc_hostname(host->mmc),\n+\t\tbcm2835_sdhost_read(host, SDCDIV));\n+\tpr_info(\"%s: SDRSP0 0x%08x\\n\",\n+\t\tmmc_hostname(host->mmc),\n+\t\tbcm2835_sdhost_read(host, SDRSP0));\n+\tpr_info(\"%s: SDRSP1 0x%08x\\n\",\n+\t\tmmc_hostname(host->mmc),\n+\t\tbcm2835_sdhost_read(host, SDRSP1));\n+\tpr_info(\"%s: SDRSP2 0x%08x\\n\",\n+\t\tmmc_hostname(host->mmc),\n+\t\tbcm2835_sdhost_read(host, SDRSP2));\n+\tpr_info(\"%s: SDRSP3 0x%08x\\n\",\n+\t\tmmc_hostname(host->mmc),\n+\t\tbcm2835_sdhost_read(host, SDRSP3));\n+\tpr_info(\"%s: SDHSTS 0x%08x\\n\",\n+\t\tmmc_hostname(host->mmc),\n+\t\tbcm2835_sdhost_read(host, SDHSTS));\n+\tpr_info(\"%s: SDVDD  0x%08x\\n\",\n+\t\tmmc_hostname(host->mmc),\n+\t\tbcm2835_sdhost_read(host, SDVDD));\n+\tpr_info(\"%s: SDEDM  0x%08x\\n\",\n+\t\tmmc_hostname(host->mmc),\n+\t\tbcm2835_sdhost_read(host, SDEDM));\n+\tpr_info(\"%s: SDHCFG 0x%08x\\n\",\n+\t\tmmc_hostname(host->mmc),\n+\t\tbcm2835_sdhost_read(host, SDHCFG));\n+\tpr_info(\"%s: SDHBCT 0x%08x\\n\",\n+\t\tmmc_hostname(host->mmc),\n+\t\tbcm2835_sdhost_read(host, SDHBCT));\n+\tpr_info(\"%s: SDHBLC 0x%08x\\n\",\n+\t\tmmc_hostname(host->mmc),\n+\t\tbcm2835_sdhost_read(host, SDHBLC));\n+\n+\tpr_info(\"%s: ===========================================\\n\",\n+\t\tmmc_hostname(host->mmc));\n+}\n+\n+static void bcm2835_sdhost_set_power(struct bcm2835_host *host, bool on)\n+{\n+\tbcm2835_sdhost_write(host, on ? 1 : 0, SDVDD);\n+}\n+\n+static void bcm2835_sdhost_reset_internal(struct bcm2835_host *host)\n+{\n+\tu32 temp;\n+\n+\tif (host->debug)\n+\t\tpr_info(\"%s: reset\\n\", mmc_hostname(host->mmc));\n+\n+\tbcm2835_sdhost_set_power(host, false);\n+\n+\tbcm2835_sdhost_write(host, 0, SDCMD);\n+\tbcm2835_sdhost_write(host, 0, SDARG);\n+\tbcm2835_sdhost_write(host, 0xf00000, SDTOUT);\n+\tbcm2835_sdhost_write(host, 0, SDCDIV);\n+\tbcm2835_sdhost_write(host, 0x7f8, SDHSTS); /* Write 1s to clear */\n+\tbcm2835_sdhost_write(host, 0, SDHCFG);\n+\tbcm2835_sdhost_write(host, 0, SDHBCT);\n+\tbcm2835_sdhost_write(host, 0, SDHBLC);\n+\n+\t/* Limit fifo usage due to silicon bug */\n+\ttemp = bcm2835_sdhost_read(host, SDEDM);\n+\ttemp &= ~((SDEDM_THRESHOLD_MASK<<SDEDM_READ_THRESHOLD_SHIFT) |\n+\t\t  (SDEDM_THRESHOLD_MASK<<SDEDM_WRITE_THRESHOLD_SHIFT));\n+\ttemp |= (FIFO_READ_THRESHOLD << SDEDM_READ_THRESHOLD_SHIFT) |\n+\t\t(FIFO_WRITE_THRESHOLD << SDEDM_WRITE_THRESHOLD_SHIFT);\n+\tbcm2835_sdhost_write(host, temp, SDEDM);\n+\tmdelay(10);\n+\tbcm2835_sdhost_set_power(host, true);\n+\tmdelay(10);\n+\thost->clock = 0;\n+\thost->sectors = 0;\n+\tbcm2835_sdhost_write(host, host->hcfg, SDHCFG);\n+\tbcm2835_sdhost_write(host, SDCDIV_MAX_CDIV, SDCDIV);\n+}\n+\n+static void bcm2835_sdhost_reset(struct mmc_host *mmc)\n+{\n+\tstruct bcm2835_host *host = mmc_priv(mmc);\n+\tunsigned long flags;\n+\tspin_lock_irqsave(&host->lock, flags);\n+\tlog_event(\"RST<\", 0, 0);\n+\n+\tbcm2835_sdhost_reset_internal(host);\n+\n+\tspin_unlock_irqrestore(&host->lock, flags);\n+}\n+\n+static void bcm2835_sdhost_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);\n+\n+static void bcm2835_sdhost_init(struct bcm2835_host *host, int soft)\n+{\n+\tpr_debug(\"bcm2835_sdhost_init(%d)\\n\", soft);\n+\n+\t/* Set interrupt enables */\n+\thost->hcfg = SDHCFG_BUSY_IRPT_EN;\n+\n+\tbcm2835_sdhost_reset_internal(host);\n+\n+\tif (soft) {\n+\t\t/* force clock reconfiguration */\n+\t\thost->clock = 0;\n+\t\tbcm2835_sdhost_set_ios(host->mmc, &host->mmc->ios);\n+\t}\n+}\n+\n+static void bcm2835_sdhost_wait_transfer_complete(struct bcm2835_host *host)\n+{\n+\tint timediff;\n+\tu32 alternate_idle;\n+\tu32 edm;\n+\n+\talternate_idle = (host->mrq->data->flags & MMC_DATA_READ) ?\n+\t\tSDEDM_FSM_READWAIT : SDEDM_FSM_WRITESTART1;\n+\n+\tedm = bcm2835_sdhost_read(host, SDEDM);\n+\n+\tlog_event(\"WTC<\", edm, 0);\n+\n+\ttimediff = 0;\n+\n+\twhile (1) {\n+\t\tu32 fsm = edm & SDEDM_FSM_MASK;\n+\t\tif ((fsm == SDEDM_FSM_IDENTMODE) ||\n+\t\t    (fsm == SDEDM_FSM_DATAMODE))\n+\t\t\tbreak;\n+\t\tif (fsm == alternate_idle) {\n+\t\t\tbcm2835_sdhost_write(host,\n+\t\t\t\t\t     edm | SDEDM_FORCE_DATA_MODE,\n+\t\t\t\t\t     SDEDM);\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\ttimediff++;\n+\t\tif (timediff == 100000) {\n+\t\t\tpr_err(\"%s: wait_transfer_complete - still waiting after %d retries\\n\",\n+\t\t\t       mmc_hostname(host->mmc),\n+\t\t\t       timediff);\n+\t\t\tlog_dump();\n+\t\t\tbcm2835_sdhost_dumpregs(host);\n+\t\t\thost->mrq->data->error = -ETIMEDOUT;\n+\t\t\tlog_event(\"WTC!\", edm, 0);\n+\t\t\treturn;\n+\t\t}\n+\t\tcpu_relax();\n+\t\tedm = bcm2835_sdhost_read(host, SDEDM);\n+\t}\n+\tlog_event(\"WTC>\", edm, 0);\n+}\n+\n+static void bcm2835_sdhost_finish_data(struct bcm2835_host *host);\n+\n+static void bcm2835_sdhost_dma_complete(void *param)\n+{\n+\tstruct bcm2835_host *host = param;\n+\tstruct mmc_data *data = host->data;\n+\tunsigned long flags;\n+\n+\tspin_lock_irqsave(&host->lock, flags);\n+\tlog_event(\"DMA<\", host->data, bcm2835_sdhost_read(host, SDHSTS));\n+\tlog_event(\"DMA \", bcm2835_sdhost_read(host, SDCMD),\n+\t\t  bcm2835_sdhost_read(host, SDEDM));\n+\n+\tif (host->dma_chan) {\n+\t\tdma_unmap_sg(host->dma_chan->device->dev,\n+\t\t\t     data->sg, data->sg_len,\n+\t\t\t     host->dma_dir);\n+\n+\t\thost->dma_chan = NULL;\n+\t}\n+\n+\tif (host->drain_words) {\n+\t\tvoid *page;\n+\t\tu32 *buf;\n+\n+\t\tif (host->drain_offset & PAGE_MASK) {\n+\t\t\thost->drain_page += host->drain_offset >> PAGE_SHIFT;\n+\t\t\thost->drain_offset &= ~PAGE_MASK;\n+\t\t}\n+\n+\t\tpage = kmap_atomic(host->drain_page);\n+\t\tbuf = page + host->drain_offset;\n+\n+\t\twhile (host->drain_words) {\n+\t\t\tu32 edm = bcm2835_sdhost_read(host, SDEDM);\n+\t\t\tif ((edm >> 4) & 0x1f)\n+\t\t\t\t*(buf++) = bcm2835_sdhost_read(host,\n+\t\t\t\t\t\t\t       SDDATA);\n+\t\t\thost->drain_words--;\n+\t\t}\n+\n+\t\tkunmap_atomic(page);\n+\t}\n+\n+\tbcm2835_sdhost_finish_data(host);\n+\n+\tlog_event(\"DMA>\", host->data, 0);\n+\tspin_unlock_irqrestore(&host->lock, flags);\n+}\n+\n+static void bcm2835_sdhost_read_block_pio(struct bcm2835_host *host)\n+{\n+\tunsigned long flags;\n+\tsize_t blksize, len;\n+\tu32 *buf;\n+\tunsigned long wait_max;\n+\n+\tblksize = host->data->blksz;\n+\n+\twait_max = jiffies + msecs_to_jiffies(host->pio_timeout);\n+\n+\tlocal_irq_save(flags);\n+\n+\twhile (blksize) {\n+\t\tint copy_words;\n+\t\tu32 hsts = 0;\n+\n+\t\tif (!sg_miter_next(&host->sg_miter)) {\n+\t\t\thost->data->error = -EINVAL;\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\tlen = min(host->sg_miter.length, blksize);\n+\t\tif (len % 4) {\n+\t\t\thost->data->error = -EINVAL;\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\tblksize -= len;\n+\t\thost->sg_miter.consumed = len;\n+\n+\t\tbuf = (u32 *)host->sg_miter.addr;\n+\n+\t\tcopy_words = len/4;\n+\n+\t\twhile (copy_words) {\n+\t\t\tint burst_words, words;\n+\t\t\tu32 edm;\n+\n+\t\t\tburst_words = SDDATA_FIFO_PIO_BURST;\n+\t\t\tif (burst_words > copy_words)\n+\t\t\t\tburst_words = copy_words;\n+\t\t\tedm = bcm2835_sdhost_read(host, SDEDM);\n+\t\t\twords = ((edm >> 4) & 0x1f);\n+\n+\t\t\tif (words < burst_words) {\n+\t\t\t\tint fsm_state = (edm & SDEDM_FSM_MASK);\n+\t\t\t\tif ((fsm_state != SDEDM_FSM_READDATA) &&\n+\t\t\t\t    (fsm_state != SDEDM_FSM_READWAIT) &&\n+\t\t\t\t    (fsm_state != SDEDM_FSM_READCRC)) {\n+\t\t\t\t\thsts = bcm2835_sdhost_read(host,\n+\t\t\t\t\t\t\t\t   SDHSTS);\n+\t\t\t\t\tpr_info(\"%s: fsm %x, hsts %x\\n\",\n+\t\t\t\t\t       mmc_hostname(host->mmc),\n+\t\t\t\t\t       fsm_state, hsts);\n+\t\t\t\t\tif (hsts & SDHSTS_ERROR_MASK)\n+\t\t\t\t\t\tbreak;\n+\t\t\t\t}\n+\n+\t\t\t\tif (time_after(jiffies, wait_max)) {\n+\t\t\t\t\tpr_err(\"%s: PIO read timeout - EDM %x\\n\",\n+\t\t\t\t\t       mmc_hostname(host->mmc),\n+\t\t\t\t\t       edm);\n+\t\t\t\t\thsts = SDHSTS_REW_TIME_OUT;\n+\t\t\t\t\tbreak;\n+\t\t\t\t}\n+\t\t\t\tndelay((burst_words - words) *\n+\t\t\t\t       host->ns_per_fifo_word);\n+\t\t\t\tcontinue;\n+\t\t\t} else if (words > copy_words) {\n+\t\t\t\twords = copy_words;\n+\t\t\t}\n+\n+\t\t\tcopy_words -= words;\n+\n+\t\t\twhile (words) {\n+\t\t\t\t*(buf++) = bcm2835_sdhost_read(host, SDDATA);\n+\t\t\t\twords--;\n+\t\t\t}\n+\t\t}\n+\n+\t\tif (hsts & SDHSTS_ERROR_MASK)\n+\t\t\tbreak;\n+\t}\n+\n+\tsg_miter_stop(&host->sg_miter);\n+\n+\tlocal_irq_restore(flags);\n+}\n+\n+static void bcm2835_sdhost_write_block_pio(struct bcm2835_host *host)\n+{\n+\tunsigned long flags;\n+\tsize_t blksize, len;\n+\tu32 *buf;\n+\tunsigned long wait_max;\n+\n+\tblksize = host->data->blksz;\n+\n+\twait_max = jiffies + msecs_to_jiffies(host->pio_timeout);\n+\n+\tlocal_irq_save(flags);\n+\n+\twhile (blksize) {\n+\t\tint copy_words;\n+\t\tu32 hsts = 0;\n+\n+\t\tif (!sg_miter_next(&host->sg_miter)) {\n+\t\t\thost->data->error = -EINVAL;\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\tlen = min(host->sg_miter.length, blksize);\n+\t\tif (len % 4) {\n+\t\t\thost->data->error = -EINVAL;\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\tblksize -= len;\n+\t\thost->sg_miter.consumed = len;\n+\n+\t\tbuf = (u32 *)host->sg_miter.addr;\n+\n+\t\tcopy_words = len/4;\n+\n+\t\twhile (copy_words) {\n+\t\t\tint burst_words, words;\n+\t\t\tu32 edm;\n+\n+\t\t\tburst_words = SDDATA_FIFO_PIO_BURST;\n+\t\t\tif (burst_words > copy_words)\n+\t\t\t\tburst_words = copy_words;\n+\t\t\tedm = bcm2835_sdhost_read(host, SDEDM);\n+\t\t\twords = SDDATA_FIFO_WORDS - ((edm >> 4) & 0x1f);\n+\n+\t\t\tif (words < burst_words) {\n+\t\t\t\tint fsm_state = (edm & SDEDM_FSM_MASK);\n+\t\t\t\tif ((fsm_state != SDEDM_FSM_WRITEDATA) &&\n+\t\t\t\t    (fsm_state != SDEDM_FSM_WRITESTART1) &&\n+\t\t\t\t    (fsm_state != SDEDM_FSM_WRITESTART2)) {\n+\t\t\t\t\thsts = bcm2835_sdhost_read(host,\n+\t\t\t\t\t\t\t\t   SDHSTS);\n+\t\t\t\t\tpr_info(\"%s: fsm %x, hsts %x\\n\",\n+\t\t\t\t\t       mmc_hostname(host->mmc),\n+\t\t\t\t\t       fsm_state, hsts);\n+\t\t\t\t\tif (hsts & SDHSTS_ERROR_MASK)\n+\t\t\t\t\t\tbreak;\n+\t\t\t\t}\n+\n+\t\t\t\tif (time_after(jiffies, wait_max)) {\n+\t\t\t\t\tpr_err(\"%s: PIO write timeout - EDM %x\\n\",\n+\t\t\t\t\t       mmc_hostname(host->mmc),\n+\t\t\t\t\t       edm);\n+\t\t\t\t\thsts = SDHSTS_REW_TIME_OUT;\n+\t\t\t\t\tbreak;\n+\t\t\t\t}\n+\t\t\t\tndelay((burst_words - words) *\n+\t\t\t\t       host->ns_per_fifo_word);\n+\t\t\t\tcontinue;\n+\t\t\t} else if (words > copy_words) {\n+\t\t\t\twords = copy_words;\n+\t\t\t}\n+\n+\t\t\tcopy_words -= words;\n+\n+\t\t\twhile (words) {\n+\t\t\t\tbcm2835_sdhost_write(host, *(buf++), SDDATA);\n+\t\t\t\twords--;\n+\t\t\t}\n+\t\t}\n+\n+\t\tif (hsts & SDHSTS_ERROR_MASK)\n+\t\t\tbreak;\n+\t}\n+\n+\tsg_miter_stop(&host->sg_miter);\n+\n+\tlocal_irq_restore(flags);\n+}\n+\n+static void bcm2835_sdhost_transfer_pio(struct bcm2835_host *host)\n+{\n+\tu32 sdhsts;\n+\tbool is_read;\n+\tBUG_ON(!host->data);\n+\tlog_event(\"XFP<\", host->data, host->blocks);\n+\n+\tis_read = (host->data->flags & MMC_DATA_READ) != 0;\n+\tif (is_read)\n+\t\tbcm2835_sdhost_read_block_pio(host);\n+\telse\n+\t\tbcm2835_sdhost_write_block_pio(host);\n+\n+\tsdhsts = bcm2835_sdhost_read(host, SDHSTS);\n+\tif (sdhsts & (SDHSTS_CRC16_ERROR |\n+\t\t      SDHSTS_CRC7_ERROR |\n+\t\t      SDHSTS_FIFO_ERROR)) {\n+\t\tpr_err(\"%s: %s transfer error - HSTS %x\\n\",\n+\t\t       mmc_hostname(host->mmc),\n+\t\t       is_read ? \"read\" : \"write\",\n+\t\t       sdhsts);\n+\t\thost->data->error = -EILSEQ;\n+\t} else if ((sdhsts & (SDHSTS_CMD_TIME_OUT |\n+\t\t\t      SDHSTS_REW_TIME_OUT))) {\n+\t\tpr_err(\"%s: %s timeout error - HSTS %x\\n\",\n+\t\t       mmc_hostname(host->mmc),\n+\t\t       is_read ? \"read\" : \"write\",\n+\t\t       sdhsts);\n+\t\thost->data->error = -ETIMEDOUT;\n+\t}\n+\tlog_event(\"XFP>\", host->data, host->blocks);\n+}\n+\n+static void bcm2835_sdhost_prepare_dma(struct bcm2835_host *host,\n+\tstruct mmc_data *data)\n+{\n+\tint len, dir_data, dir_slave;\n+\tstruct dma_async_tx_descriptor *desc = NULL;\n+\tstruct dma_chan *dma_chan;\n+\n+\tlog_event(\"PRD<\", data, 0);\n+\tpr_debug(\"bcm2835_sdhost_prepare_dma()\\n\");\n+\n+\tdma_chan = host->dma_chan_rxtx;\n+\tif (data->flags & MMC_DATA_READ) {\n+\t\tdir_data = DMA_FROM_DEVICE;\n+\t\tdir_slave = DMA_DEV_TO_MEM;\n+\t} else {\n+\t\tdir_data = DMA_TO_DEVICE;\n+\t\tdir_slave = DMA_MEM_TO_DEV;\n+\t}\n+\tlog_event(\"PRD1\", dma_chan, 0);\n+\n+\tBUG_ON(!dma_chan->device);\n+\tBUG_ON(!dma_chan->device->dev);\n+\tBUG_ON(!data->sg);\n+\n+\t/* The block doesn't manage the FIFO DREQs properly for multi-block\n+\t   transfers, so don't attempt to DMA the final few words.\n+\t   Unfortunately this requires the final sg entry to be trimmed.\n+\t   N.B. This code demands that the overspill is contained in\n+\t   a single sg entry.\n+\t*/\n+\n+\thost->drain_words = 0;\n+\tif ((data->blocks > 1) && (dir_data == DMA_FROM_DEVICE)) {\n+\t\tstruct scatterlist *sg;\n+\t\tu32 len;\n+\t\tint i;\n+\n+\t\tlen = min((u32)(FIFO_READ_THRESHOLD - 1) * 4,\n+\t\t\t  (u32)data->blocks * data->blksz);\n+\n+\t\tfor_each_sg(data->sg, sg, data->sg_len, i) {\n+\t\t\tif (sg_is_last(sg)) {\n+\t\t\t\tBUG_ON(sg->length < len);\n+\t\t\t\tsg->length -= len;\n+\t\t\t\thost->drain_page = sg_page(sg);\n+\t\t\t\thost->drain_offset = sg->offset + sg->length;\n+\t\t\t}\n+\t\t}\n+\t\thost->drain_words = len/4;\n+\t}\n+\n+\t/* The parameters have already been validated, so this will not fail */\n+\t(void)dmaengine_slave_config(dma_chan,\n+\t\t\t\t     (dir_data == DMA_FROM_DEVICE) ?\n+\t\t\t\t     &host->dma_cfg_rx :\n+\t\t\t\t     &host->dma_cfg_tx);\n+\n+\tlen = dma_map_sg(dma_chan->device->dev, data->sg, data->sg_len,\n+\t\t\t dir_data);\n+\n+\tlog_event(\"PRD2\", len, 0);\n+\tif (len > 0)\n+\t\tdesc = dmaengine_prep_slave_sg(dma_chan, data->sg,\n+\t\t\t\t\t       len, dir_slave,\n+\t\t\t\t\t       DMA_PREP_INTERRUPT | DMA_CTRL_ACK);\n+\tlog_event(\"PRD3\", desc, 0);\n+\n+\tif (desc) {\n+\t\tdesc->callback = bcm2835_sdhost_dma_complete;\n+\t\tdesc->callback_param = host;\n+\t\thost->dma_desc = desc;\n+\t\thost->dma_chan = dma_chan;\n+\t\thost->dma_dir = dir_data;\n+\t}\n+\tlog_event(\"PDM>\", data, 0);\n+}\n+\n+static void bcm2835_sdhost_start_dma(struct bcm2835_host *host)\n+{\n+\tlog_event(\"SDMA\", host->data, host->dma_chan);\n+\tdmaengine_submit(host->dma_desc);\n+\tdma_async_issue_pending(host->dma_chan);\n+}\n+\n+static void bcm2835_sdhost_set_transfer_irqs(struct bcm2835_host *host)\n+{\n+\tu32 all_irqs = SDHCFG_DATA_IRPT_EN | SDHCFG_BLOCK_IRPT_EN |\n+\t\tSDHCFG_BUSY_IRPT_EN;\n+\tif (host->dma_desc)\n+\t\thost->hcfg = (host->hcfg & ~all_irqs) |\n+\t\t\tSDHCFG_BUSY_IRPT_EN;\n+\telse\n+\t\thost->hcfg = (host->hcfg & ~all_irqs) |\n+\t\t\tSDHCFG_DATA_IRPT_EN |\n+\t\t\tSDHCFG_BUSY_IRPT_EN;\n+\n+\tbcm2835_sdhost_write(host, host->hcfg, SDHCFG);\n+}\n+\n+static void bcm2835_sdhost_prepare_data(struct bcm2835_host *host, struct mmc_command *cmd)\n+{\n+\tstruct mmc_data *data = cmd->data;\n+\n+\tWARN_ON(host->data);\n+\n+\thost->data = data;\n+\tif (!data)\n+\t\treturn;\n+\n+\t/* Sanity checks */\n+\tBUG_ON(data->blksz * data->blocks > 524288);\n+\tBUG_ON(data->blksz > host->mmc->max_blk_size);\n+\tBUG_ON(data->blocks > 65535);\n+\n+\thost->data_complete = 0;\n+\thost->flush_fifo = 0;\n+\thost->data->bytes_xfered = 0;\n+\n+\tif (!host->sectors && host->mmc->card) {\n+\t\tstruct mmc_card *card = host->mmc->card;\n+\t\tif (!mmc_card_sd(card) && mmc_card_blockaddr(card)) {\n+\t\t\t/*\n+\t\t\t * The EXT_CSD sector count is in number of 512 byte\n+\t\t\t * sectors.\n+\t\t\t */\n+\t\t\thost->sectors = card->ext_csd.sectors;\n+\t\t} else {\n+\t\t\t/*\n+\t\t\t * The CSD capacity field is in units of read_blkbits.\n+\t\t\t * set_capacity takes units of 512 bytes.\n+\t\t\t */\n+\t\t\thost->sectors = card->csd.capacity <<\n+\t\t\t\t(card->csd.read_blkbits - 9);\n+\t\t}\n+\t}\n+\n+\tif (!host->dma_desc) {\n+\t\t/* Use PIO */\n+\t\tint flags = SG_MITER_ATOMIC;\n+\n+\t\tif (data->flags & MMC_DATA_READ)\n+\t\t\tflags |= SG_MITER_TO_SG;\n+\t\telse\n+\t\t\tflags |= SG_MITER_FROM_SG;\n+\t\tsg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);\n+\t\thost->blocks = data->blocks;\n+\t}\n+\n+\tbcm2835_sdhost_set_transfer_irqs(host);\n+\n+\tbcm2835_sdhost_write(host, data->blksz, SDHBCT);\n+\tbcm2835_sdhost_write(host, data->blocks, SDHBLC);\n+\n+\tBUG_ON(!host->data);\n+}\n+\n+bool bcm2835_sdhost_send_command(struct bcm2835_host *host,\n+\t\t\t\t struct mmc_command *cmd)\n+{\n+\tu32 sdcmd, sdhsts;\n+\tunsigned long timeout;\n+\tint delay;\n+\n+\tWARN_ON(host->cmd);\n+\tlog_event(\"CMD<\", cmd->opcode, cmd->arg);\n+\n+\tif (cmd->data)\n+\t\tpr_debug(\"%s: send_command %d 0x%x \"\n+\t\t\t \"(flags 0x%x) - %s %d*%d\\n\",\n+\t\t\t mmc_hostname(host->mmc),\n+\t\t\t cmd->opcode, cmd->arg, cmd->flags,\n+\t\t\t (cmd->data->flags & MMC_DATA_READ) ?\n+\t\t\t \"read\" : \"write\", cmd->data->blocks,\n+\t\t\t cmd->data->blksz);\n+\telse\n+\t\tpr_debug(\"%s: send_command %d 0x%x (flags 0x%x)\\n\",\n+\t\t\t mmc_hostname(host->mmc),\n+\t\t\t cmd->opcode, cmd->arg, cmd->flags);\n+\n+\t/* Wait max 100 ms */\n+\ttimeout = 10000;\n+\n+\twhile (bcm2835_sdhost_read(host, SDCMD) & SDCMD_NEW_FLAG) {\n+\t\tif (timeout == 0) {\n+\t\t\tpr_warn(\"%s: previous command never completed.\\n\",\n+\t\t\t\tmmc_hostname(host->mmc));\n+\t\t\tif (host->debug)\n+\t\t\t\tbcm2835_sdhost_dumpregs(host);\n+\t\t\tcmd->error = -EILSEQ;\n+\t\t\ttasklet_schedule(&host->finish_tasklet);\n+\t\t\treturn false;\n+\t\t}\n+\t\ttimeout--;\n+\t\tudelay(10);\n+\t}\n+\n+\tdelay = (10000 - timeout)/100;\n+\tif (delay > host->max_delay) {\n+\t\thost->max_delay = delay;\n+\t\tpr_warn(\"%s: controller hung for %d ms\\n\",\n+\t\t\t   mmc_hostname(host->mmc),\n+\t\t\t   host->max_delay);\n+\t}\n+\n+\ttimeout = jiffies;\n+\tif (!cmd->data && cmd->busy_timeout > 9000)\n+\t\ttimeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;\n+\telse\n+\t\ttimeout += 10 * HZ;\n+\tmod_timer(&host->timer, timeout);\n+\n+\thost->cmd = cmd;\n+\n+\t/* Clear any error flags */\n+\tsdhsts = bcm2835_sdhost_read(host, SDHSTS);\n+\tif (sdhsts & SDHSTS_ERROR_MASK)\n+\t\tbcm2835_sdhost_write(host, sdhsts, SDHSTS);\n+\n+\tif ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {\n+\t\tpr_err(\"%s: unsupported response type!\\n\",\n+\t\t\tmmc_hostname(host->mmc));\n+\t\tcmd->error = -EINVAL;\n+\t\ttasklet_schedule(&host->finish_tasklet);\n+\t\treturn false;\n+\t}\n+\n+\tbcm2835_sdhost_prepare_data(host, cmd);\n+\n+\tbcm2835_sdhost_write(host, cmd->arg, SDARG);\n+\n+\tsdcmd = cmd->opcode & SDCMD_CMD_MASK;\n+\n+\thost->use_busy = 0;\n+\tif (!(cmd->flags & MMC_RSP_PRESENT)) {\n+\t\tsdcmd |= SDCMD_NO_RESPONSE;\n+\t} else {\n+\t\tif (cmd->flags & MMC_RSP_136)\n+\t\t\tsdcmd |= SDCMD_LONG_RESPONSE;\n+\t\tif (cmd->flags & MMC_RSP_BUSY) {\n+\t\t\tsdcmd |= SDCMD_BUSYWAIT;\n+\t\t\thost->use_busy = 1;\n+\t\t}\n+\t}\n+\n+\tif (cmd->data) {\n+\t\tlog_event(\"CMDD\", cmd->data->blocks, cmd->data->blksz);\n+\t\tif (host->delay_after_this_stop) {\n+\t\t\tstruct timespec64 now;\n+\t\t\tint time_since_stop;\n+\n+\t\t\tktime_get_real_ts64(&now);\n+\t\t\ttime_since_stop = now.tv_sec - host->stop_time.tv_sec;\n+\t\t\tif (time_since_stop < 2) {\n+\t\t\t\t/* Possibly less than one second */\n+\t\t\t\ttime_since_stop = time_since_stop * 1000000 +\n+\t\t\t\t\t(now.tv_nsec - host->stop_time.tv_nsec)/1000;\n+\t\t\t\tif (time_since_stop <\n+\t\t\t\t    host->delay_after_this_stop)\n+\t\t\t\t\tudelay(host->delay_after_this_stop -\n+\t\t\t\t\t       time_since_stop);\n+\t\t\t}\n+\t\t}\n+\n+\t\thost->delay_after_this_stop = host->delay_after_stop;\n+\t\tif ((cmd->data->flags & MMC_DATA_READ) && !host->use_sbc) {\n+\t\t\t/* See if read crosses one of the hazardous sectors */\n+\t\t\tu32 first_blk, last_blk;\n+\n+\t\t\t/* Intentionally include the following sector because\n+\t\t\t   without CMD23/SBC the read may run on. */\n+\t\t\tfirst_blk = host->mrq->cmd->arg;\n+\t\t\tlast_blk = first_blk + cmd->data->blocks;\n+\n+\t\t\tif (((last_blk >= (host->sectors - 64)) &&\n+\t\t\t     (first_blk <= (host->sectors - 64))) ||\n+\t\t\t    ((last_blk >= (host->sectors - 32)) &&\n+\t\t\t     (first_blk <= (host->sectors - 32)))) {\n+\t\t\t\thost->delay_after_this_stop =\n+\t\t\t\t\tmax(250u, host->delay_after_stop);\n+\t\t\t}\n+\t\t}\n+\n+\t\tif (cmd->data->flags & MMC_DATA_WRITE)\n+\t\t\tsdcmd |= SDCMD_WRITE_CMD;\n+\t\tif (cmd->data->flags & MMC_DATA_READ)\n+\t\t\tsdcmd |= SDCMD_READ_CMD;\n+\t}\n+\n+\tbcm2835_sdhost_write(host, sdcmd | SDCMD_NEW_FLAG, SDCMD);\n+\n+\treturn true;\n+}\n+\n+static void bcm2835_sdhost_finish_command(struct bcm2835_host *host,\n+\t\t\t\t\t  unsigned long *irq_flags);\n+static void bcm2835_sdhost_transfer_complete(struct bcm2835_host *host);\n+\n+static void bcm2835_sdhost_finish_data(struct bcm2835_host *host)\n+{\n+\tstruct mmc_data *data;\n+\n+\tdata = host->data;\n+\tBUG_ON(!data);\n+\n+\tlog_event(\"FDA<\", host->mrq, host->cmd);\n+\tpr_debug(\"finish_data(error %d, stop %d, sbc %d)\\n\",\n+\t       data->error, data->stop ? 1 : 0,\n+\t       host->mrq->sbc ? 1 : 0);\n+\n+\thost->hcfg &= ~(SDHCFG_DATA_IRPT_EN | SDHCFG_BLOCK_IRPT_EN);\n+\tbcm2835_sdhost_write(host, host->hcfg, SDHCFG);\n+\n+\tdata->bytes_xfered = data->error ? 0 : (data->blksz * data->blocks);\n+\n+\thost->data_complete = 1;\n+\n+\tif (host->cmd) {\n+\t\t/*\n+\t\t * Data managed to finish before the\n+\t\t * command completed. Make sure we do\n+\t\t * things in the proper order.\n+\t\t */\n+\t\tpr_debug(\"Finished early - HSTS %x\\n\",\n+\t\t\t bcm2835_sdhost_read(host, SDHSTS));\n+\t}\n+\telse\n+\t\tbcm2835_sdhost_transfer_complete(host);\n+\tlog_event(\"FDA>\", host->mrq, host->cmd);\n+}\n+\n+static void bcm2835_sdhost_transfer_complete(struct bcm2835_host *host)\n+{\n+\tstruct mmc_data *data;\n+\n+\tBUG_ON(host->cmd);\n+\tBUG_ON(!host->data);\n+\tBUG_ON(!host->data_complete);\n+\n+\tdata = host->data;\n+\thost->data = NULL;\n+\n+\tlog_event(\"TCM<\", data, data->error);\n+\tpr_debug(\"transfer_complete(error %d, stop %d)\\n\",\n+\t       data->error, data->stop ? 1 : 0);\n+\n+\t/*\n+\t * Need to send CMD12 if -\n+\t * a) open-ended multiblock transfer (no CMD23)\n+\t * b) error in multiblock transfer\n+\t */\n+\tif (host->mrq->stop && (data->error || !host->use_sbc)) {\n+\t\tif (bcm2835_sdhost_send_command(host, host->mrq->stop)) {\n+\t\t\t/* No busy, so poll for completion */\n+\t\t\tif (!host->use_busy)\n+\t\t\t\tbcm2835_sdhost_finish_command(host, NULL);\n+\n+\t\t\tif (host->delay_after_this_stop)\n+\t\t\t\tktime_get_real_ts64(&host->stop_time);\n+\t\t}\n+\t} else {\n+\t\tbcm2835_sdhost_wait_transfer_complete(host);\n+\t\ttasklet_schedule(&host->finish_tasklet);\n+\t}\n+\tlog_event(\"TCM>\", data, 0);\n+}\n+\n+/* If irq_flags is valid, the caller is in a thread context and is allowed\n+   to sleep */\n+static void bcm2835_sdhost_finish_command(struct bcm2835_host *host,\n+\t\t\t\t\t  unsigned long *irq_flags)\n+{\n+\tu32 sdcmd;\n+\tu32 retries;\n+#ifdef DEBUG\n+\tstruct timespec64 before, after;\n+\tint timediff = 0;\n+#endif\n+\n+\tlog_event(\"FCM<\", host->mrq, host->cmd);\n+\tpr_debug(\"finish_command(%x)\\n\", bcm2835_sdhost_read(host, SDCMD));\n+\n+\tBUG_ON(!host->cmd || !host->mrq);\n+\n+\t/* Poll quickly at first */\n+\n+\tretries = host->cmd_quick_poll_retries;\n+\tif (!retries) {\n+\t\t/* Work out how many polls take 1us by timing 10us */\n+\t\tstruct timespec64 start, now;\n+\t\tint us_diff;\n+\n+\t\tretries = 1;\n+\t\tdo {\n+\t\t\tint i;\n+\n+\t\t\tretries *= 2;\n+\n+\t\t\tktime_get_real_ts64(&start);\n+\n+\t\t\tfor (i = 0; i < retries; i++) {\n+\t\t\t\tcpu_relax();\n+\t\t\t\tsdcmd = bcm2835_sdhost_read(host, SDCMD);\n+\t\t\t}\n+\n+\t\t\tktime_get_real_ts64(&now);\n+\t\t\tus_diff = (now.tv_sec - start.tv_sec) * 1000000 +\n+\t\t\t\t(now.tv_nsec - start.tv_nsec)/1000;\n+\t\t} while (us_diff < 10);\n+\n+\t\thost->cmd_quick_poll_retries = ((retries * us_diff + 9)*CMD_DALLY_US)/10 + 1;\n+\t\tretries = 1; // We've already waited long enough this time\n+\t}\n+\n+\tfor (sdcmd = bcm2835_sdhost_read(host, SDCMD);\n+\t     (sdcmd & SDCMD_NEW_FLAG) && retries;\n+\t     retries--) {\n+\t\tcpu_relax();\n+\t\tsdcmd = bcm2835_sdhost_read(host, SDCMD);\n+\t}\n+\n+\tif (!retries) {\n+\t\tunsigned long wait_max;\n+\n+\t\tif (!irq_flags) {\n+\t\t\t/* Schedule the work */\n+\t\t\tlog_event(\"CWWQ\", 0, 0);\n+\t\t\tschedule_work(&host->cmd_wait_wq);\n+\t\t\treturn;\n+\t\t}\n+\n+\t\t/* Wait max 100 ms */\n+\t\twait_max = jiffies + msecs_to_jiffies(100);\n+\t\twhile (time_before(jiffies, wait_max)) {\n+\t\t\tspin_unlock_irqrestore(&host->lock, *irq_flags);\n+\t\t\tusleep_range(1, 10);\n+\t\t\tspin_lock_irqsave(&host->lock, *irq_flags);\n+\t\t\tsdcmd = bcm2835_sdhost_read(host, SDCMD);\n+\t\t\tif (!(sdcmd & SDCMD_NEW_FLAG))\n+\t\t\t\tbreak;\n+\t\t}\n+\t}\n+\n+\t/* Check for errors */\n+\tif (sdcmd & SDCMD_NEW_FLAG) {\n+\t\tif (host->debug) {\n+\t\t\tpr_err(\"%s: command %d never completed.\\n\",\n+\t\t\t       mmc_hostname(host->mmc), host->cmd->opcode);\n+\t\t\tbcm2835_sdhost_dumpregs(host);\n+\t\t}\n+\t\thost->cmd->error = -EILSEQ;\n+\t\ttasklet_schedule(&host->finish_tasklet);\n+\t\treturn;\n+\t} else if (sdcmd & SDCMD_FAIL_FLAG) {\n+\t\tu32 sdhsts = bcm2835_sdhost_read(host, SDHSTS);\n+\n+\t\t/* Clear the errors */\n+\t\tbcm2835_sdhost_write(host, SDHSTS_ERROR_MASK, SDHSTS);\n+\n+\t\tif (host->debug)\n+\t\t\tpr_info(\"%s: error detected - CMD %x, HSTS %03x, EDM %x\\n\",\n+\t\t\t\tmmc_hostname(host->mmc), sdcmd, sdhsts,\n+\t\t\t\tbcm2835_sdhost_read(host, SDEDM));\n+\n+\t\tif ((sdhsts & SDHSTS_CRC7_ERROR) &&\n+\t\t    (host->cmd->opcode == 1)) {\n+\t\t\tif (host->debug)\n+\t\t\t\tpr_info(\"%s: ignoring CRC7 error for CMD1\\n\",\n+\t\t\t\t\tmmc_hostname(host->mmc));\n+\t\t} else {\n+\t\t\tu32 edm, fsm;\n+\n+\t\t\tif (sdhsts & SDHSTS_CMD_TIME_OUT) {\n+\t\t\t\tif (host->debug)\n+\t\t\t\t\tpr_warn(\"%s: command %d timeout\\n\",\n+\t\t\t\t\t       mmc_hostname(host->mmc),\n+\t\t\t\t\t       host->cmd->opcode);\n+\t\t\t\thost->cmd->error = -ETIMEDOUT;\n+\t\t\t} else {\n+\t\t\t\tpr_warn(\"%s: unexpected command %d error\\n\",\n+\t\t\t\t       mmc_hostname(host->mmc),\n+\t\t\t\t       host->cmd->opcode);\n+\t\t\t\thost->cmd->error = -EILSEQ;\n+\t\t\t}\n+\n+\t\t\tedm = readl(host->ioaddr + SDEDM);\n+\t\t\tfsm = edm & SDEDM_FSM_MASK;\n+\t\t\tif (fsm == SDEDM_FSM_READWAIT ||\n+\t\t\t    fsm == SDEDM_FSM_WRITESTART1)\n+\t\t\t\twritel(edm | SDEDM_FORCE_DATA_MODE,\n+\t\t\t\t       host->ioaddr + SDEDM);\n+\t\t\ttasklet_schedule(&host->finish_tasklet);\n+\t\t\treturn;\n+\t\t}\n+\t}\n+\n+\tif (host->cmd->flags & MMC_RSP_PRESENT) {\n+\t\tif (host->cmd->flags & MMC_RSP_136) {\n+\t\t\tint i;\n+\t\t\tfor (i = 0; i < 4; i++)\n+\t\t\t\thost->cmd->resp[3 - i] = bcm2835_sdhost_read(host, SDRSP0 + i*4);\n+\t\t\tpr_debug(\"%s: finish_command %08x %08x %08x %08x\\n\",\n+\t\t\t\t mmc_hostname(host->mmc),\n+\t\t\t\t host->cmd->resp[0], host->cmd->resp[1], host->cmd->resp[2], host->cmd->resp[3]);\n+\t\t\tlog_event(\"RSP \", host->cmd->resp[0], host->cmd->resp[1]);\n+\t\t} else {\n+\t\t\thost->cmd->resp[0] = bcm2835_sdhost_read(host, SDRSP0);\n+\t\t\tpr_debug(\"%s: finish_command %08x\\n\",\n+\t\t\t\t mmc_hostname(host->mmc),\n+\t\t\t\t host->cmd->resp[0]);\n+\t\t\tlog_event(\"RSP \", host->cmd->resp[0], 0);\n+\t\t}\n+\t}\n+\n+\tif (host->cmd == host->mrq->sbc) {\n+\t\t/* Finished CMD23, now send actual command. */\n+\t\thost->cmd = NULL;\n+\t\tif (bcm2835_sdhost_send_command(host, host->mrq->cmd)) {\n+\t\t\tif (host->data && host->dma_desc)\n+\t\t\t\t/* DMA transfer starts now, PIO starts after irq */\n+\t\t\t\tbcm2835_sdhost_start_dma(host);\n+\n+\t\t\tif (!host->use_busy)\n+\t\t\t\tbcm2835_sdhost_finish_command(host, NULL);\n+\t\t}\n+\t} else if (host->cmd == host->mrq->stop) {\n+\t\t/* Finished CMD12 */\n+\t\ttasklet_schedule(&host->finish_tasklet);\n+\t} else {\n+\t\t/* Processed actual command. */\n+\t\thost->cmd = NULL;\n+\t\tif (!host->data)\n+\t\t\ttasklet_schedule(&host->finish_tasklet);\n+\t\telse if (host->data_complete)\n+\t\t\tbcm2835_sdhost_transfer_complete(host);\n+\t}\n+\tlog_event(\"FCM>\", host->mrq, host->cmd);\n+}\n+\n+static void bcm2835_sdhost_timeout(struct timer_list *t)\n+{\n+\tstruct bcm2835_host *host = from_timer(host, t, timer);\n+\tunsigned long flags;\n+\n+\tspin_lock_irqsave(&host->lock, flags);\n+\tlog_event(\"TIM<\", 0, 0);\n+\n+\tif (host->mrq) {\n+\t\tpr_err(\"%s: timeout waiting for hardware interrupt.\\n\",\n+\t\t\tmmc_hostname(host->mmc));\n+\t\tlog_dump();\n+\t\tbcm2835_sdhost_dumpregs(host);\n+\n+\t\tif (host->data) {\n+\t\t\thost->data->error = -ETIMEDOUT;\n+\t\t\tbcm2835_sdhost_finish_data(host);\n+\t\t} else {\n+\t\t\tif (host->cmd)\n+\t\t\t\thost->cmd->error = -ETIMEDOUT;\n+\t\t\telse\n+\t\t\t\thost->mrq->cmd->error = -ETIMEDOUT;\n+\n+\t\t\tpr_debug(\"timeout_timer tasklet_schedule\\n\");\n+\t\t\ttasklet_schedule(&host->finish_tasklet);\n+\t\t}\n+\t}\n+\n+\tspin_unlock_irqrestore(&host->lock, flags);\n+}\n+\n+static void bcm2835_sdhost_busy_irq(struct bcm2835_host *host, u32 intmask)\n+{\n+\tlog_event(\"IRQB\", host->cmd, intmask);\n+\tif (!host->cmd) {\n+\t\tpr_err(\"%s: got command busy interrupt 0x%08x even \"\n+\t\t\t\"though no command operation was in progress.\\n\",\n+\t\t\tmmc_hostname(host->mmc), (unsigned)intmask);\n+\t\tbcm2835_sdhost_dumpregs(host);\n+\t\treturn;\n+\t}\n+\n+\tif (!host->use_busy) {\n+\t\tpr_err(\"%s: got command busy interrupt 0x%08x even \"\n+\t\t\t\"though not expecting one.\\n\",\n+\t\t\tmmc_hostname(host->mmc), (unsigned)intmask);\n+\t\tbcm2835_sdhost_dumpregs(host);\n+\t\treturn;\n+\t}\n+\thost->use_busy = 0;\n+\n+\tif (intmask & SDHSTS_ERROR_MASK)\n+\t{\n+\t\tpr_err(\"sdhost_busy_irq: intmask %x, data %p\\n\", intmask, host->mrq->data);\n+\t\tif (intmask & SDHSTS_CRC7_ERROR)\n+\t\t\thost->cmd->error = -EILSEQ;\n+\t\telse if (intmask & (SDHSTS_CRC16_ERROR |\n+\t\t\t\t    SDHSTS_FIFO_ERROR)) {\n+\t\t\tif (host->mrq->data)\n+\t\t\t\thost->mrq->data->error = -EILSEQ;\n+\t\t\telse\n+\t\t\t\thost->cmd->error = -EILSEQ;\n+\t\t} else if (intmask & SDHSTS_REW_TIME_OUT) {\n+\t\t\tif (host->mrq->data)\n+\t\t\t\thost->mrq->data->error = -ETIMEDOUT;\n+\t\t\telse\n+\t\t\t\thost->cmd->error = -ETIMEDOUT;\n+\t\t} else if (intmask & SDHSTS_CMD_TIME_OUT)\n+\t\t\thost->cmd->error = -ETIMEDOUT;\n+\n+\t\tif (host->debug) {\n+\t\t\tlog_dump();\n+\t\t\tbcm2835_sdhost_dumpregs(host);\n+\t\t}\n+\t}\n+\telse\n+\t\tbcm2835_sdhost_finish_command(host, NULL);\n+}\n+\n+static void bcm2835_sdhost_data_irq(struct bcm2835_host *host, u32 intmask)\n+{\n+\t/* There are no dedicated data/space available interrupt\n+\t   status bits, so it is necessary to use the single shared\n+\t   data/space available FIFO status bits. It is therefore not\n+\t   an error to get here when there is no data transfer in\n+\t   progress. */\n+\tlog_event(\"IRQD\", host->data, intmask);\n+\tif (!host->data)\n+\t\treturn;\n+\n+\tif (intmask & (SDHSTS_CRC16_ERROR |\n+\t\t       SDHSTS_FIFO_ERROR |\n+\t\t       SDHSTS_REW_TIME_OUT)) {\n+\t\tif (intmask & (SDHSTS_CRC16_ERROR |\n+\t\t\t       SDHSTS_FIFO_ERROR))\n+\t\t\thost->data->error = -EILSEQ;\n+\t\telse\n+\t\t\thost->data->error = -ETIMEDOUT;\n+\n+\t\tif (host->debug) {\n+\t\t\tlog_dump();\n+\t\t\tbcm2835_sdhost_dumpregs(host);\n+\t\t}\n+\t}\n+\n+\tif (host->data->error) {\n+\t\tbcm2835_sdhost_finish_data(host);\n+\t} else if (host->data->flags & MMC_DATA_WRITE) {\n+\t\t/* Use the block interrupt for writes after the first block */\n+\t\thost->hcfg &= ~(SDHCFG_DATA_IRPT_EN);\n+\t\thost->hcfg |= SDHCFG_BLOCK_IRPT_EN;\n+\t\tbcm2835_sdhost_write(host, host->hcfg, SDHCFG);\n+\t\tbcm2835_sdhost_transfer_pio(host);\n+\t} else {\n+\t\tbcm2835_sdhost_transfer_pio(host);\n+\t\thost->blocks--;\n+\t\tif ((host->blocks == 0) || host->data->error)\n+\t\t\tbcm2835_sdhost_finish_data(host);\n+\t}\n+}\n+\n+static void bcm2835_sdhost_block_irq(struct bcm2835_host *host, u32 intmask)\n+{\n+\tlog_event(\"IRQK\", host->data, intmask);\n+\tif (!host->data) {\n+\t\tpr_err(\"%s: got block interrupt 0x%08x even \"\n+\t\t\t\"though no data operation was in progress.\\n\",\n+\t\t\tmmc_hostname(host->mmc), (unsigned)intmask);\n+\t\tbcm2835_sdhost_dumpregs(host);\n+\t\treturn;\n+\t}\n+\n+\tif (intmask & (SDHSTS_CRC16_ERROR |\n+\t\t       SDHSTS_FIFO_ERROR |\n+\t\t       SDHSTS_REW_TIME_OUT)) {\n+\t\tif (intmask & (SDHSTS_CRC16_ERROR |\n+\t\t\t       SDHSTS_FIFO_ERROR))\n+\t\t\thost->data->error = -EILSEQ;\n+\t\telse\n+\t\t\thost->data->error = -ETIMEDOUT;\n+\n+\t\tif (host->debug) {\n+\t\t\tlog_dump();\n+\t\t\tbcm2835_sdhost_dumpregs(host);\n+\t\t}\n+\t}\n+\n+\tif (!host->dma_desc) {\n+\t\tBUG_ON(!host->blocks);\n+\t\tif (host->data->error || (--host->blocks == 0)) {\n+\t\t\tbcm2835_sdhost_finish_data(host);\n+\t\t} else {\n+\t\t\tbcm2835_sdhost_transfer_pio(host);\n+\t\t}\n+\t} else if (host->data->flags & MMC_DATA_WRITE) {\n+\t\tbcm2835_sdhost_finish_data(host);\n+\t}\n+}\n+\n+static irqreturn_t bcm2835_sdhost_irq(int irq, void *dev_id)\n+{\n+\tirqreturn_t result = IRQ_NONE;\n+\tstruct bcm2835_host *host = dev_id;\n+\tu32 intmask;\n+\n+\tspin_lock(&host->lock);\n+\n+\tintmask = bcm2835_sdhost_read(host, SDHSTS);\n+\tlog_event(\"IRQ<\", intmask, 0);\n+\n+\tbcm2835_sdhost_write(host,\n+\t\t\t     SDHSTS_BUSY_IRPT |\n+\t\t\t     SDHSTS_BLOCK_IRPT |\n+\t\t\t     SDHSTS_SDIO_IRPT |\n+\t\t\t     SDHSTS_DATA_FLAG,\n+\t\t\t     SDHSTS);\n+\n+\tif (intmask & SDHSTS_BLOCK_IRPT) {\n+\t\tbcm2835_sdhost_block_irq(host, intmask);\n+\t\tresult = IRQ_HANDLED;\n+\t}\n+\n+\tif (intmask & SDHSTS_BUSY_IRPT) {\n+\t\tbcm2835_sdhost_busy_irq(host, intmask);\n+\t\tresult = IRQ_HANDLED;\n+\t}\n+\n+\t/* There is no true data interrupt status bit, so it is\n+\t   necessary to qualify the data flag with the interrupt\n+\t   enable bit */\n+\tif ((intmask & SDHSTS_DATA_FLAG) &&\n+\t    (host->hcfg & SDHCFG_DATA_IRPT_EN)) {\n+\t\tbcm2835_sdhost_data_irq(host, intmask);\n+\t\tresult = IRQ_HANDLED;\n+\t}\n+\n+\tlog_event(\"IRQ>\", bcm2835_sdhost_read(host, SDHSTS), 0);\n+\tspin_unlock(&host->lock);\n+\n+\treturn result;\n+}\n+\n+void bcm2835_sdhost_set_clock(struct bcm2835_host *host, unsigned int clock)\n+{\n+\tint div = 0; /* Initialized for compiler warning */\n+\tunsigned int input_clock = clock;\n+\tunsigned long flags;\n+\n+\tif (host->debug)\n+\t\tpr_info(\"%s: set_clock(%d)\\n\", mmc_hostname(host->mmc), clock);\n+\n+\tif (host->overclock_50 && (clock == 50*MHZ))\n+\t\tclock = host->overclock_50 * MHZ + (MHZ - 1);\n+\n+\t/* The SDCDIV register has 11 bits, and holds (div - 2).\n+\t   But in data mode the max is 50MHz wihout a minimum, and only the\n+\t   bottom 3 bits are used. Since the switch over is automatic (unless\n+\t   we have marked the card as slow...), chosen values have to make\n+\t   sense in both modes.\n+\t   Ident mode must be 100-400KHz, so can range check the requested\n+\t   clock. CMD15 must be used to return to data mode, so this can be\n+\t   monitored.\n+\n+\t   clock 250MHz -> 0->125MHz, 1->83.3MHz, 2->62.5MHz, 3->50.0MHz\n+                           4->41.7MHz, 5->35.7MHz, 6->31.3MHz, 7->27.8MHz\n+\n+\t\t\t 623->400KHz/27.8MHz\n+\t\t\t reset value (507)->491159/50MHz\n+\n+\t   BUT, the 3-bit clock divisor in data mode is too small if the\n+\t   core clock is higher than 250MHz, so instead use the SLOW_CARD\n+\t   configuration bit to force the use of the ident clock divisor\n+\t   at all times.\n+\t*/\n+\n+\thost->mmc->actual_clock = 0;\n+\n+\tif (host->firmware_sets_cdiv) {\n+\t\tu32 msg[3] = { clock, 0, 0 };\n+\n+\t\trpi_firmware_property(rpi_firmware_get(NULL),\n+\t\t\t\t      RPI_FIRMWARE_SET_SDHOST_CLOCK,\n+\t\t\t\t      &msg, sizeof(msg));\n+\n+\t\tclock = max(msg[1], msg[2]);\n+\t\tspin_lock_irqsave(&host->lock, flags);\n+\t} else {\n+\t\tspin_lock_irqsave(&host->lock, flags);\n+\t\tif (clock < 100000) {\n+\t\t\t/* Can't stop the clock, but make it as slow as\n+\t\t\t * possible to show willing\n+\t\t\t */\n+\t\t\thost->cdiv = SDCDIV_MAX_CDIV;\n+\t\t\tbcm2835_sdhost_write(host, host->cdiv, SDCDIV);\n+\t\t\tspin_unlock_irqrestore(&host->lock, flags);\n+\t\t\treturn;\n+\t\t}\n+\n+\t\tdiv = host->max_clk / clock;\n+\t\tif (div < 2)\n+\t\t\tdiv = 2;\n+\t\tif ((host->max_clk / div) > clock)\n+\t\t\tdiv++;\n+\t\tdiv -= 2;\n+\n+\t\tif (div > SDCDIV_MAX_CDIV)\n+\t\t\tdiv = SDCDIV_MAX_CDIV;\n+\n+\t\tclock = host->max_clk / (div + 2);\n+\n+\t\thost->cdiv = div;\n+\t\tbcm2835_sdhost_write(host, host->cdiv, SDCDIV);\n+\n+\t\tif (host->debug)\n+\t\t\tpr_info(\"%s: clock=%d -> max_clk=%d, cdiv=%x \"\n+\t\t\t\t\"(actual clock %d)\\n\",\n+\t\t\t\tmmc_hostname(host->mmc), input_clock,\n+\t\t\t\thost->max_clk, host->cdiv,\n+\t\t\t\tclock);\n+\t}\n+\n+\t/* Calibrate some delays */\n+\n+\thost->ns_per_fifo_word = (1000000000/clock) *\n+\t\t((host->mmc->caps & MMC_CAP_4_BIT_DATA) ? 8 : 32);\n+\n+\tif (input_clock == 50 * MHZ) {\n+\t\tif (clock > input_clock) {\n+\t\t\t/* Save the closest value, to make it easier\n+\t\t\t   to reduce in the event of error */\n+\t\t\thost->overclock_50 = (clock/MHZ);\n+\n+\t\t\tif (clock != host->overclock) {\n+\t\t\t\tpr_info(\"%s: overclocking to %dHz\\n\",\n+\t\t\t\t\tmmc_hostname(host->mmc), clock);\n+\t\t\t\thost->overclock = clock;\n+\t\t\t}\n+\t\t} else if (host->overclock) {\n+\t\t\thost->overclock = 0;\n+\t\t\tif (clock == 50 * MHZ)\n+\t\t\t\tpr_warn(\"%s: cancelling overclock\\n\",\n+\t\t\t\t\tmmc_hostname(host->mmc));\n+\t\t}\n+\t} else if (input_clock == 0) {\n+\t\t/* Reset the preferred overclock when the clock is stopped.\n+\t\t * This always happens during initialisation. */\n+\t\thost->overclock_50 = host->user_overclock_50;\n+\t\thost->overclock = 0;\n+\t}\n+\n+\t/* Set the timeout to 500ms */\n+\tbcm2835_sdhost_write(host, clock/2, SDTOUT);\n+\n+\thost->mmc->actual_clock = clock;\n+\thost->clock = input_clock;\n+\thost->reset_clock = 0;\n+\n+\tspin_unlock_irqrestore(&host->lock, flags);\n+}\n+\n+static void bcm2835_sdhost_request(struct mmc_host *mmc, struct mmc_request *mrq)\n+{\n+\tstruct bcm2835_host *host;\n+\tunsigned long flags;\n+\tu32 edm, fsm;\n+\n+\thost = mmc_priv(mmc);\n+\n+\tif (host->debug) {\n+\t\tstruct mmc_command *cmd = mrq->cmd;\n+\t\tBUG_ON(!cmd);\n+\t\tif (cmd->data)\n+\t\t\tpr_info(\"%s: cmd %d 0x%x (flags 0x%x) - %s %d*%d\\n\",\n+\t\t\t\tmmc_hostname(mmc),\n+\t\t\t\tcmd->opcode, cmd->arg, cmd->flags,\n+\t\t\t\t(cmd->data->flags & MMC_DATA_READ) ?\n+\t\t\t\t\"read\" : \"write\", cmd->data->blocks,\n+\t\t\t\tcmd->data->blksz);\n+\t\telse\n+\t\t\tpr_info(\"%s: cmd %d 0x%x (flags 0x%x)\\n\",\n+\t\t\t\tmmc_hostname(mmc),\n+\t\t\t\tcmd->opcode, cmd->arg, cmd->flags);\n+\t}\n+\n+\t/* Reset the error statuses in case this is a retry */\n+\tif (mrq->sbc)\n+\t\tmrq->sbc->error = 0;\n+\tif (mrq->cmd)\n+\t\tmrq->cmd->error = 0;\n+\tif (mrq->data)\n+\t\tmrq->data->error = 0;\n+\tif (mrq->stop)\n+\t\tmrq->stop->error = 0;\n+\n+\tif (mrq->data && !is_power_of_2(mrq->data->blksz)) {\n+\t\tpr_err(\"%s: unsupported block size (%d bytes)\\n\",\n+\t\t       mmc_hostname(mmc), mrq->data->blksz);\n+\t\tmrq->cmd->error = -EINVAL;\n+\t\tmmc_request_done(mmc, mrq);\n+\t\treturn;\n+\t}\n+\n+\tif (host->use_dma && mrq->data &&\n+\t    (mrq->data->blocks > host->pio_limit))\n+\t\tbcm2835_sdhost_prepare_dma(host, mrq->data);\n+\n+\tif (host->reset_clock)\n+\t    bcm2835_sdhost_set_clock(host, host->clock);\n+\n+\tspin_lock_irqsave(&host->lock, flags);\n+\n+\tWARN_ON(host->mrq != NULL);\n+\thost->mrq = mrq;\n+\n+\tedm = bcm2835_sdhost_read(host, SDEDM);\n+\tfsm = edm & SDEDM_FSM_MASK;\n+\n+\tlog_event(\"REQ<\", mrq, edm);\n+\tif ((fsm != SDEDM_FSM_IDENTMODE) &&\n+\t    (fsm != SDEDM_FSM_DATAMODE)) {\n+\t\tlog_event(\"REQ!\", mrq, edm);\n+\t\tif (host->debug) {\n+\t\t\tpr_warn(\"%s: previous command (%d) not complete (EDM %x)\\n\",\n+\t\t\t       mmc_hostname(host->mmc),\n+\t\t\t       bcm2835_sdhost_read(host, SDCMD) & SDCMD_CMD_MASK,\n+\t\t\t       edm);\n+\t\t\tlog_dump();\n+\t\t\tbcm2835_sdhost_dumpregs(host);\n+\t\t}\n+\t\tmrq->cmd->error = -EILSEQ;\n+\t\ttasklet_schedule(&host->finish_tasklet);\n+\t\tspin_unlock_irqrestore(&host->lock, flags);\n+\t\treturn;\n+\t}\n+\n+\thost->use_sbc = !!mrq->sbc &&\n+\t\t(host->mrq->data->flags & USE_CMD23_FLAGS);\n+\tif (host->use_sbc) {\n+\t\tif (bcm2835_sdhost_send_command(host, mrq->sbc)) {\n+\t\t\tif (!host->use_busy)\n+\t\t\t\tbcm2835_sdhost_finish_command(host, &flags);\n+\t\t}\n+\t} else if (bcm2835_sdhost_send_command(host, mrq->cmd)) {\n+\t\tif (host->data && host->dma_desc)\n+\t\t\t/* DMA transfer starts now, PIO starts after irq */\n+\t\t\tbcm2835_sdhost_start_dma(host);\n+\n+\t\tif (!host->use_busy)\n+\t\t\tbcm2835_sdhost_finish_command(host, &flags);\n+\t}\n+\n+\tlog_event(\"CMD \", mrq->cmd->opcode,\n+\t\t   mrq->data ? (u32)mrq->data->blksz : 0);\n+\n+\tlog_event(\"REQ>\", mrq, 0);\n+\tspin_unlock_irqrestore(&host->lock, flags);\n+}\n+\n+static void bcm2835_sdhost_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)\n+{\n+\n+\tstruct bcm2835_host *host = mmc_priv(mmc);\n+\tunsigned long flags;\n+\n+\tif (host->debug)\n+\t\tpr_info(\"%s: ios clock %d, pwr %d, bus_width %d, \"\n+\t\t\t\"timing %d, vdd %d, drv_type %d\\n\",\n+\t\t\tmmc_hostname(mmc),\n+\t\t\tios->clock, ios->power_mode, ios->bus_width,\n+\t\t\tios->timing, ios->signal_voltage, ios->drv_type);\n+\n+\tspin_lock_irqsave(&host->lock, flags);\n+\n+\tlog_event(\"IOS<\", ios->clock, 0);\n+\n+\t/* set bus width */\n+\thost->hcfg &= ~SDHCFG_WIDE_EXT_BUS;\n+\tif (ios->bus_width == MMC_BUS_WIDTH_4)\n+\t\thost->hcfg |= SDHCFG_WIDE_EXT_BUS;\n+\n+\thost->hcfg |= SDHCFG_WIDE_INT_BUS;\n+\n+\t/* Disable clever clock switching, to cope with fast core clocks */\n+\thost->hcfg |= SDHCFG_SLOW_CARD;\n+\n+\tbcm2835_sdhost_write(host, host->hcfg, SDHCFG);\n+\n+\tspin_unlock_irqrestore(&host->lock, flags);\n+\n+\tif (!ios->clock || ios->clock != host->clock)\n+\t\tbcm2835_sdhost_set_clock(host, ios->clock);\n+}\n+\n+static struct mmc_host_ops bcm2835_sdhost_ops = {\n+\t.request = bcm2835_sdhost_request,\n+\t.set_ios = bcm2835_sdhost_set_ios,\n+\t.hw_reset = bcm2835_sdhost_reset,\n+};\n+\n+static void bcm2835_sdhost_cmd_wait_work(struct work_struct *work)\n+{\n+\tstruct bcm2835_host *host;\n+\tunsigned long flags;\n+\n+\thost = container_of(work, struct bcm2835_host, cmd_wait_wq);\n+\n+\tspin_lock_irqsave(&host->lock, flags);\n+\n+\tlog_event(\"CWK<\", host->cmd, host->mrq);\n+\n+\t/*\n+\t * If this tasklet gets rescheduled while running, it will\n+\t * be run again afterwards but without any active request.\n+\t */\n+\tif (!host->mrq) {\n+\t\tspin_unlock_irqrestore(&host->lock, flags);\n+\t\treturn;\n+\t}\n+\n+\tbcm2835_sdhost_finish_command(host, &flags);\n+\n+\tlog_event(\"CWK>\", host->cmd, 0);\n+\n+\tspin_unlock_irqrestore(&host->lock, flags);\n+}\n+\n+static void bcm2835_sdhost_tasklet_finish(unsigned long param)\n+{\n+\tstruct bcm2835_host *host;\n+\tunsigned long flags;\n+\tstruct mmc_request *mrq;\n+\tstruct dma_chan *terminate_chan = NULL;\n+\n+\thost = (struct bcm2835_host *)param;\n+\n+\tspin_lock_irqsave(&host->lock, flags);\n+\n+\tlog_event(\"TSK<\", host->mrq, 0);\n+\t/*\n+\t * If this tasklet gets rescheduled while running, it will\n+\t * be run again afterwards but without any active request.\n+\t */\n+\tif (!host->mrq) {\n+\t\tspin_unlock_irqrestore(&host->lock, flags);\n+\t\treturn;\n+\t}\n+\n+\tdel_timer(&host->timer);\n+\n+\tmrq = host->mrq;\n+\n+\t/* Drop the overclock after any data corruption, or after any\n+\t * error while overclocked. Ignore errors for status commands,\n+\t * as they are likely when a card is ejected. */\n+\tif (host->overclock) {\n+\t\tif ((mrq->cmd && mrq->cmd->error &&\n+\t\t     (mrq->cmd->opcode != MMC_SEND_STATUS)) ||\n+\t\t    (mrq->data && mrq->data->error) ||\n+\t\t    (mrq->stop && mrq->stop->error) ||\n+\t\t    (mrq->sbc && mrq->sbc->error)) {\n+\t\t\thost->overclock_50--;\n+\t\t\tpr_warn(\"%s: reducing overclock due to errors\\n\",\n+\t\t\t\tmmc_hostname(host->mmc));\n+\t\t\thost->reset_clock = 1;\n+\t\t\tmrq->cmd->error = -ETIMEDOUT;\n+\t\t\tmrq->cmd->retries = 1;\n+\t\t}\n+\t}\n+\n+\thost->mrq = NULL;\n+\thost->cmd = NULL;\n+\thost->data = NULL;\n+\n+\thost->dma_desc = NULL;\n+\tterminate_chan = host->dma_chan;\n+\thost->dma_chan = NULL;\n+\n+\tspin_unlock_irqrestore(&host->lock, flags);\n+\n+\tif (terminate_chan)\n+\t{\n+\t\tint err = dmaengine_terminate_all(terminate_chan);\n+\t\tif (err)\n+\t\t\tpr_err(\"%s: failed to terminate DMA (%d)\\n\",\n+\t\t\t       mmc_hostname(host->mmc), err);\n+\t}\n+\n+\t/* The SDHOST block doesn't report any errors for a disconnected\n+\t   interface. All cards and SDIO devices should report some supported\n+\t   voltage range, so a zero response to SEND_OP_COND, IO_SEND_OP_COND\n+\t   or APP_SEND_OP_COND can be treated as an error. */\n+\tif (((mrq->cmd->opcode == MMC_SEND_OP_COND) ||\n+\t     (mrq->cmd->opcode == SD_IO_SEND_OP_COND) ||\n+\t     (mrq->cmd->opcode == SD_APP_OP_COND)) &&\n+\t    (mrq->cmd->error == 0) &&\n+\t    (mrq->cmd->resp[0] == 0)) {\n+\t\tmrq->cmd->error = -ETIMEDOUT;\n+\t\tif (host->debug)\n+\t\t\tpr_info(\"%s: faking timeout due to zero OCR\\n\",\n+\t\t\t\tmmc_hostname(host->mmc));\n+\t}\n+\n+\tmmc_request_done(host->mmc, mrq);\n+\tlog_event(\"TSK>\", mrq, 0);\n+}\n+\n+int bcm2835_sdhost_add_host(struct bcm2835_host *host)\n+{\n+\tstruct mmc_host *mmc;\n+\tstruct dma_slave_config cfg;\n+\tchar pio_limit_string[20];\n+\tint ret;\n+\n+\tmmc = host->mmc;\n+\n+\tif (!mmc->f_max || mmc->f_max > host->max_clk)\n+\t\tmmc->f_max = host->max_clk;\n+\tmmc->f_min = host->max_clk / SDCDIV_MAX_CDIV;\n+\n+\tmmc->max_busy_timeout =  (~(unsigned int)0)/(mmc->f_max/1000);\n+\n+\tpr_debug(\"f_max %d, f_min %d, max_busy_timeout %d\\n\",\n+\t\t mmc->f_max, mmc->f_min, mmc->max_busy_timeout);\n+\n+\t/* host controller capabilities */\n+\tmmc->caps |=\n+\t\tMMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED |\n+\t\tMMC_CAP_NEEDS_POLL | MMC_CAP_HW_RESET |\n+\t\t((ALLOW_CMD23_READ|ALLOW_CMD23_WRITE) * MMC_CAP_CMD23);\n+\n+\tspin_lock_init(&host->lock);\n+\n+\tif (host->allow_dma) {\n+\t\tif (IS_ERR_OR_NULL(host->dma_chan_rxtx)) {\n+\t\t\tpr_err(\"%s: unable to initialise DMA channel. \"\n+\t\t\t       \"Falling back to PIO\\n\",\n+\t\t\t       mmc_hostname(mmc));\n+\t\t\thost->use_dma = false;\n+\t\t} else {\n+\t\t\tcfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;\n+\t\t\tcfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;\n+\t\t\tcfg.slave_id = 13;\t\t/* DREQ channel */\n+\n+\t\t\t/* Validate the slave configurations */\n+\n+\t\t\tcfg.direction = DMA_MEM_TO_DEV;\n+\t\t\tcfg.src_addr = 0;\n+\t\t\tcfg.dst_addr = host->bus_addr + SDDATA;\n+\n+\t\t\tret = dmaengine_slave_config(host->dma_chan_rxtx, &cfg);\n+\n+\t\t\tif (ret == 0) {\n+\t\t\t\thost->dma_cfg_tx = cfg;\n+\n+\t\t\t\tcfg.direction = DMA_DEV_TO_MEM;\n+\t\t\t\tcfg.src_addr = host->bus_addr + SDDATA;\n+\t\t\t\tcfg.dst_addr = 0;\n+\n+\t\t\t\tret = dmaengine_slave_config(host->dma_chan_rxtx, &cfg);\n+\t\t\t}\n+\n+\t\t\tif (ret == 0) {\n+\t\t\t\thost->dma_cfg_rx = cfg;\n+\n+\t\t\t\thost->use_dma = true;\n+\t\t\t} else {\n+\t\t\t\tpr_err(\"%s: unable to configure DMA channel. \"\n+\t\t\t\t       \"Falling back to PIO\\n\",\n+\t\t\t\t       mmc_hostname(mmc));\n+\t\t\t\tdma_release_channel(host->dma_chan_rxtx);\n+\t\t\t\thost->dma_chan_rxtx = NULL;\n+\t\t\t\thost->use_dma = false;\n+\t\t\t}\n+\t\t}\n+\t} else {\n+\t\thost->use_dma = false;\n+\t}\n+\n+\tmmc->max_segs = 128;\n+\tmmc->max_req_size = 524288;\n+\tmmc->max_seg_size = mmc->max_req_size;\n+\tmmc->max_blk_size = 512;\n+\tmmc->max_blk_count =  65535;\n+\n+\t/* report supported voltage ranges */\n+\tmmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;\n+\n+\ttasklet_init(&host->finish_tasklet,\n+\t\tbcm2835_sdhost_tasklet_finish, (unsigned long)host);\n+\n+\tINIT_WORK(&host->cmd_wait_wq, bcm2835_sdhost_cmd_wait_work);\n+\n+\ttimer_setup(&host->timer, bcm2835_sdhost_timeout, 0);\n+\n+\tbcm2835_sdhost_init(host, 0);\n+\n+\tret = request_irq(host->irq, bcm2835_sdhost_irq, 0 /*IRQF_SHARED*/,\n+\t\t\t\t  mmc_hostname(mmc), host);\n+\tif (ret) {\n+\t\tpr_err(\"%s: failed to request IRQ %d: %d\\n\",\n+\t\t       mmc_hostname(mmc), host->irq, ret);\n+\t\tgoto untasklet;\n+\t}\n+\n+\tmmc_add_host(mmc);\n+\n+\tpio_limit_string[0] = '\\0';\n+\tif (host->use_dma && (host->pio_limit > 0))\n+\t\tsprintf(pio_limit_string, \" (>%d)\", host->pio_limit);\n+\tpr_info(\"%s: %s loaded - DMA %s%s\\n\",\n+\t\tmmc_hostname(mmc), DRIVER_NAME,\n+\t\thost->use_dma ? \"enabled\" : \"disabled\",\n+\t\tpio_limit_string);\n+\n+\treturn 0;\n+\n+untasklet:\n+\ttasklet_kill(&host->finish_tasklet);\n+\n+\treturn ret;\n+}\n+\n+static int bcm2835_sdhost_probe(struct platform_device *pdev)\n+{\n+\tstruct device *dev = &pdev->dev;\n+\tstruct device_node *node = dev->of_node;\n+\tstruct clk *clk;\n+\tstruct resource *iomem;\n+\tstruct bcm2835_host *host;\n+\tstruct mmc_host *mmc;\n+\tconst __be32 *addr;\n+\tu32 msg[3];\n+\tint na;\n+\tint ret;\n+\n+\tpr_debug(\"bcm2835_sdhost_probe\\n\");\n+\tmmc = mmc_alloc_host(sizeof(*host), dev);\n+\tif (!mmc)\n+\t\treturn -ENOMEM;\n+\n+\tmmc->ops = &bcm2835_sdhost_ops;\n+\thost = mmc_priv(mmc);\n+\thost->mmc = mmc;\n+\thost->pio_timeout = msecs_to_jiffies(500);\n+\thost->pio_limit = 1;\n+\thost->max_delay = 1; /* Warn if over 1ms */\n+\thost->allow_dma = 1;\n+\tspin_lock_init(&host->lock);\n+\n+\tiomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);\n+\thost->ioaddr = devm_ioremap_resource(dev, iomem);\n+\tif (IS_ERR(host->ioaddr)) {\n+\t\tret = PTR_ERR(host->ioaddr);\n+\t\tgoto err;\n+\t}\n+\n+\tna = of_n_addr_cells(node);\n+\taddr = of_get_address(node, 0, NULL, NULL);\n+\tif (!addr) {\n+\t\tdev_err(dev, \"could not get DMA-register address\\n\");\n+\t\treturn -ENODEV;\n+\t}\n+\thost->bus_addr = (phys_addr_t)of_read_number(addr, na);\n+\tpr_debug(\" - ioaddr %lx, iomem->start %lx, bus_addr %lx\\n\",\n+\t\t (unsigned long)host->ioaddr,\n+\t\t (unsigned long)iomem->start,\n+\t\t (unsigned long)host->bus_addr);\n+\n+\tif (node) {\n+\t\t/* Read any custom properties */\n+\t\tof_property_read_u32(node,\n+\t\t\t\t     \"brcm,delay-after-stop\",\n+\t\t\t\t     &host->delay_after_stop);\n+\t\tof_property_read_u32(node,\n+\t\t\t\t     \"brcm,overclock-50\",\n+\t\t\t\t     &host->user_overclock_50);\n+\t\tof_property_read_u32(node,\n+\t\t\t\t     \"brcm,pio-limit\",\n+\t\t\t\t     &host->pio_limit);\n+\t\thost->allow_dma =\n+\t\t\t!of_property_read_bool(node, \"brcm,force-pio\");\n+\t\thost->debug = of_property_read_bool(node, \"brcm,debug\");\n+\t}\n+\n+\thost->dma_chan = NULL;\n+\thost->dma_desc = NULL;\n+\n+\t/* Formally recognise the other way of disabling DMA */\n+\tif (host->pio_limit == 0x7fffffff)\n+\t\thost->allow_dma = false;\n+\n+\tif (host->allow_dma) {\n+\t\tif (node) {\n+\t\t\thost->dma_chan_rxtx =\n+\t\t\t\tdma_request_slave_channel(dev, \"rx-tx\");\n+\t\t\tif (!host->dma_chan_rxtx)\n+\t\t\t\thost->dma_chan_rxtx =\n+\t\t\t\t\tdma_request_slave_channel(dev, \"tx\");\n+\t\t\tif (!host->dma_chan_rxtx)\n+\t\t\t\thost->dma_chan_rxtx =\n+\t\t\t\t\tdma_request_slave_channel(dev, \"rx\");\n+\t\t} else {\n+\t\t\tdma_cap_mask_t mask;\n+\n+\t\t\tdma_cap_zero(mask);\n+\t\t\t/* we don't care about the channel, any would work */\n+\t\t\tdma_cap_set(DMA_SLAVE, mask);\n+\t\t\thost->dma_chan_rxtx =\n+\t\t\t\tdma_request_channel(mask, NULL, NULL);\n+\t\t}\n+\t}\n+\n+\tclk = devm_clk_get(dev, NULL);\n+\tif (IS_ERR(clk)) {\n+\t\tret = PTR_ERR(clk);\n+\t\tif (ret == -EPROBE_DEFER)\n+\t\t\tdev_info(dev, \"could not get clk, deferring probe\\n\");\n+\t\telse\n+\t\t\tdev_err(dev, \"could not get clk\\n\");\n+\t\tgoto err;\n+\t}\n+\n+\thost->max_clk = clk_get_rate(clk);\n+\n+\thost->irq = platform_get_irq(pdev, 0);\n+\tif (host->irq <= 0) {\n+\t\tdev_err(dev, \"get IRQ failed\\n\");\n+\t\tret = -EINVAL;\n+\t\tgoto err;\n+\t}\n+\n+\tpr_debug(\" - max_clk %lx, irq %d\\n\",\n+\t\t (unsigned long)host->max_clk,\n+\t\t (int)host->irq);\n+\n+\tlog_init(dev, iomem->start - host->bus_addr);\n+\n+\tif (node)\n+\t\tmmc_of_parse(mmc);\n+\telse\n+\t\tmmc->caps |= MMC_CAP_4_BIT_DATA;\n+\n+\tmsg[0] = 0;\n+\tmsg[1] = ~0;\n+\tmsg[2] = ~0;\n+\n+\trpi_firmware_property(rpi_firmware_get(NULL),\n+\t\t\t      RPI_FIRMWARE_SET_SDHOST_CLOCK,\n+\t\t\t      &msg, sizeof(msg));\n+\n+\thost->firmware_sets_cdiv = (msg[1] != ~0);\n+\n+\tret = bcm2835_sdhost_add_host(host);\n+\tif (ret)\n+\t\tgoto err;\n+\n+\tplatform_set_drvdata(pdev, host);\n+\n+\tpr_debug(\"bcm2835_sdhost_probe -> OK\\n\");\n+\n+\treturn 0;\n+\n+err:\n+\tpr_debug(\"bcm2835_sdhost_probe -> err %d\\n\", ret);\n+\tif (host->dma_chan_rxtx)\n+\t\tdma_release_channel(host->dma_chan_rxtx);\n+\tmmc_free_host(mmc);\n+\n+\treturn ret;\n+}\n+\n+static int bcm2835_sdhost_remove(struct platform_device *pdev)\n+{\n+\tstruct bcm2835_host *host = platform_get_drvdata(pdev);\n+\n+\tpr_debug(\"bcm2835_sdhost_remove\\n\");\n+\n+\tmmc_remove_host(host->mmc);\n+\n+\tbcm2835_sdhost_set_power(host, false);\n+\n+\tfree_irq(host->irq, host);\n+\n+\tdel_timer_sync(&host->timer);\n+\n+\ttasklet_kill(&host->finish_tasklet);\n+\tif (host->dma_chan_rxtx)\n+\t\tdma_release_channel(host->dma_chan_rxtx);\n+\tmmc_free_host(host->mmc);\n+\tplatform_set_drvdata(pdev, NULL);\n+\n+\tpr_debug(\"bcm2835_sdhost_remove - OK\\n\");\n+\treturn 0;\n+}\n+\n+static const struct of_device_id bcm2835_sdhost_match[] = {\n+\t{ .compatible = \"brcm,bcm2835-sdhost\" },\n+\t{ }\n+};\n+MODULE_DEVICE_TABLE(of, bcm2835_sdhost_match);\n+\n+static struct platform_driver bcm2835_sdhost_driver = {\n+\t.probe      = bcm2835_sdhost_probe,\n+\t.remove     = bcm2835_sdhost_remove,\n+\t.driver     = {\n+\t\t.name\t\t= DRIVER_NAME,\n+\t\t.owner\t\t= THIS_MODULE,\n+\t\t.of_match_table\t= bcm2835_sdhost_match,\n+\t},\n+};\n+module_platform_driver(bcm2835_sdhost_driver);\n+\n+MODULE_ALIAS(\"platform:sdhost-bcm2835\");\n+MODULE_DESCRIPTION(\"BCM2835 SDHost driver\");\n+MODULE_LICENSE(\"GPL v2\");\n+MODULE_AUTHOR(\"Phil Elwell\");\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0048-vc_mem-Add-vc_mem-driver-for-querying-firmware-memor.patch",
    "content": "From 156d50d2fb05f132d53927cbf9fad3c9c37e8937 Mon Sep 17 00:00:00 2001\nFrom: popcornmix <popcornmix@gmail.com>\nDate: Fri, 28 Oct 2016 15:36:43 +0100\nSubject: [PATCH] vc_mem: Add vc_mem driver for querying firmware\n memory addresses\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nSigned-off-by: popcornmix <popcornmix@gmail.com>\n\nBCM270x: Move vc_mem\n\nMake the vc_mem module available for ARCH_BCM2835 by moving it.\n\nSigned-off-by: Noralf Trønnes <noralf@tronnes.org>\n\nchar: vc_mem: Fix up compat ioctls for 64bit kernel\n\ncompat_ioctl wasn't defined, so 32bit user/64bit kernel\nalways failed.\nVC_MEM_IOC_MEM_PHYS_ADDR was defined with parameter size\nunsigned long, so the ioctl cmd changes between sizes.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>\n\nchar: vc_mem: Fix all coding style issues.\n\nCleans up all checkpatch errors in vc_mem.c and vc_mem.h\nNo functional change to the code.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>\n---\n drivers/char/broadcom/Kconfig   |  18 ++\n drivers/char/broadcom/Makefile  |   1 +\n drivers/char/broadcom/vc_mem.c  | 375 ++++++++++++++++++++++++++++++++\n include/linux/broadcom/vc_mem.h |  39 ++++\n 4 files changed, 433 insertions(+)\n create mode 100644 drivers/char/broadcom/Kconfig\n create mode 100644 drivers/char/broadcom/Makefile\n create mode 100644 drivers/char/broadcom/vc_mem.c\n create mode 100644 include/linux/broadcom/vc_mem.h\n\n--- /dev/null\n+++ b/drivers/char/broadcom/Kconfig\n@@ -0,0 +1,18 @@\n+#\n+# Broadcom char driver config\n+#\n+\n+menuconfig BRCM_CHAR_DRIVERS\n+\tbool \"Broadcom Char Drivers\"\n+\thelp\n+\t  Broadcom's char drivers\n+\n+if BRCM_CHAR_DRIVERS\n+\n+config BCM2708_VCMEM\n+\tbool \"Videocore Memory\"\n+        default y\n+        help\n+          Helper for videocore memory access and total size allocation.\n+\n+endif\n--- /dev/null\n+++ b/drivers/char/broadcom/Makefile\n@@ -0,0 +1 @@\n+obj-$(CONFIG_BCM2708_VCMEM)\t+= vc_mem.o\n--- /dev/null\n+++ b/drivers/char/broadcom/vc_mem.c\n@@ -0,0 +1,375 @@\n+/*\n+ * Copyright 2010 - 2011 Broadcom Corporation.  All rights reserved.\n+ *\n+ * Unless you and Broadcom execute a separate written software license\n+ * agreement governing use of this software, this software is licensed to you\n+ * under the terms of the GNU General Public License version 2, available at\n+ * http://www.broadcom.com/licenses/GPLv2.php (the \"GPL\").\n+ *\n+ * Notwithstanding the above, under no circumstances may you combine this\n+ * software in any way with any other Broadcom software provided under a\n+ * license other than the GPL, without Broadcom's express prior written\n+ * consent.\n+ */\n+\n+#include <linux/kernel.h>\n+#include <linux/module.h>\n+#include <linux/fs.h>\n+#include <linux/device.h>\n+#include <linux/cdev.h>\n+#include <linux/mm.h>\n+#include <linux/slab.h>\n+#include <linux/debugfs.h>\n+#include <linux/uaccess.h>\n+#include <linux/dma-mapping.h>\n+#include <linux/broadcom/vc_mem.h>\n+\n+#define DRIVER_NAME  \"vc-mem\"\n+\n+/* Device (/dev) related variables */\n+static dev_t vc_mem_devnum;\n+static struct class *vc_mem_class;\n+static struct cdev vc_mem_cdev;\n+static int vc_mem_inited;\n+\n+#ifdef CONFIG_DEBUG_FS\n+static struct dentry *vc_mem_debugfs_entry;\n+#endif\n+\n+/*\n+ * Videocore memory addresses and size\n+ *\n+ * Drivers that wish to know the videocore memory addresses and sizes should\n+ * use these variables instead of the MM_IO_BASE and MM_ADDR_IO defines in\n+ * headers. This allows the other drivers to not be tied down to a a certain\n+ * address/size at compile time.\n+ *\n+ * In the future, the goal is to have the videocore memory virtual address and\n+ * size be calculated at boot time rather than at compile time. The decision of\n+ * where the videocore memory resides and its size would be in the hands of the\n+ * bootloader (and/or kernel). When that happens, the values of these variables\n+ * would be calculated and assigned in the init function.\n+ */\n+/* In the 2835 VC in mapped above ARM, but ARM has full access to VC space */\n+unsigned long mm_vc_mem_phys_addr;\n+EXPORT_SYMBOL(mm_vc_mem_phys_addr);\n+unsigned int mm_vc_mem_size;\n+EXPORT_SYMBOL(mm_vc_mem_size);\n+unsigned int mm_vc_mem_base;\n+EXPORT_SYMBOL(mm_vc_mem_base);\n+\n+static uint phys_addr;\n+static uint mem_size;\n+static uint mem_base;\n+\n+static int\n+vc_mem_open(struct inode *inode, struct file *file)\n+{\n+\t(void)inode;\n+\n+\tpr_debug(\"%s: called file = 0x%p\\n\", __func__, file);\n+\n+\treturn 0;\n+}\n+\n+static int\n+vc_mem_release(struct inode *inode, struct file *file)\n+{\n+\t(void)inode;\n+\n+\tpr_debug(\"%s: called file = 0x%p\\n\", __func__, file);\n+\n+\treturn 0;\n+}\n+\n+static void\n+vc_mem_get_size(void)\n+{\n+}\n+\n+static void\n+vc_mem_get_base(void)\n+{\n+}\n+\n+int\n+vc_mem_get_current_size(void)\n+{\n+\treturn mm_vc_mem_size;\n+}\n+EXPORT_SYMBOL_GPL(vc_mem_get_current_size);\n+\n+static long\n+vc_mem_ioctl(struct file *file, unsigned int cmd, unsigned long arg)\n+{\n+\tint rc = 0;\n+\n+\t(void) cmd;\n+\t(void) arg;\n+\n+\tpr_debug(\"%s: called file = 0x%p, cmd %08x\\n\", __func__, file, cmd);\n+\n+\tswitch (cmd) {\n+\tcase VC_MEM_IOC_MEM_PHYS_ADDR:\n+\t\t{\n+\t\t\tpr_debug(\"%s: VC_MEM_IOC_MEM_PHYS_ADDR=0x%p\\n\",\n+\t\t\t\t__func__, (void *)mm_vc_mem_phys_addr);\n+\n+\t\t\tif (copy_to_user((void *)arg, &mm_vc_mem_phys_addr,\n+\t\t\t\t\t sizeof(mm_vc_mem_phys_addr))) {\n+\t\t\t\trc = -EFAULT;\n+\t\t\t}\n+\t\t\tbreak;\n+\t\t}\n+\tcase VC_MEM_IOC_MEM_SIZE:\n+\t\t{\n+\t\t\t/* Get the videocore memory size first */\n+\t\t\tvc_mem_get_size();\n+\n+\t\t\tpr_debug(\"%s: VC_MEM_IOC_MEM_SIZE=%x\\n\", __func__,\n+\t\t\t\t mm_vc_mem_size);\n+\n+\t\t\tif (copy_to_user((void *)arg, &mm_vc_mem_size,\n+\t\t\t\t\t sizeof(mm_vc_mem_size))) {\n+\t\t\t\trc = -EFAULT;\n+\t\t\t}\n+\t\t\tbreak;\n+\t\t}\n+\tcase VC_MEM_IOC_MEM_BASE:\n+\t\t{\n+\t\t\t/* Get the videocore memory base */\n+\t\t\tvc_mem_get_base();\n+\n+\t\t\tpr_debug(\"%s: VC_MEM_IOC_MEM_BASE=%x\\n\", __func__,\n+\t\t\t\t mm_vc_mem_base);\n+\n+\t\t\tif (copy_to_user((void *)arg, &mm_vc_mem_base,\n+\t\t\t\t\t sizeof(mm_vc_mem_base))) {\n+\t\t\t\trc = -EFAULT;\n+\t\t\t}\n+\t\t\tbreak;\n+\t\t}\n+\tcase VC_MEM_IOC_MEM_LOAD:\n+\t\t{\n+\t\t\t/* Get the videocore memory base */\n+\t\t\tvc_mem_get_base();\n+\n+\t\t\tpr_debug(\"%s: VC_MEM_IOC_MEM_LOAD=%x\\n\", __func__,\n+\t\t\t\tmm_vc_mem_base);\n+\n+\t\t\tif (copy_to_user((void *)arg, &mm_vc_mem_base,\n+\t\t\t\t\t sizeof(mm_vc_mem_base))) {\n+\t\t\t\trc = -EFAULT;\n+\t\t\t}\n+\t\t\tbreak;\n+\t\t}\n+\tdefault:\n+\t\t{\n+\t\t\treturn -ENOTTY;\n+\t\t}\n+\t}\n+\tpr_debug(\"%s: file = 0x%p returning %d\\n\", __func__, file, rc);\n+\n+\treturn rc;\n+}\n+\n+#ifdef CONFIG_COMPAT\n+static long\n+vc_mem_compat_ioctl(struct file *file, unsigned int cmd, unsigned long arg)\n+{\n+\tint rc = 0;\n+\n+\tswitch (cmd) {\n+\tcase VC_MEM_IOC_MEM_PHYS_ADDR32:\n+\t\tpr_debug(\"%s: VC_MEM_IOC_MEM_PHYS_ADDR32=0x%p\\n\",\n+\t\t\t __func__, (void *)mm_vc_mem_phys_addr);\n+\n+\t\t/* This isn't correct, but will cover us for now as\n+\t\t * VideoCore is 32bit only.\n+\t\t */\n+\t\tif (copy_to_user((void *)arg, &mm_vc_mem_phys_addr,\n+\t\t\t\t sizeof(compat_ulong_t)))\n+\t\t\trc = -EFAULT;\n+\n+\t\tbreak;\n+\n+\tdefault:\n+\t\trc = vc_mem_ioctl(file, cmd, arg);\n+\t\tbreak;\n+\t}\n+\n+\treturn rc;\n+}\n+#endif\n+\n+static int\n+vc_mem_mmap(struct file *filp, struct vm_area_struct *vma)\n+{\n+\tint rc = 0;\n+\tunsigned long length = vma->vm_end - vma->vm_start;\n+\tunsigned long offset = vma->vm_pgoff << PAGE_SHIFT;\n+\n+\tpr_debug(\"%s: vm_start = 0x%08lx vm_end = 0x%08lx vm_pgoff = 0x%08lx\\n\",\n+\t\t __func__, (long)vma->vm_start, (long)vma->vm_end,\n+\t\t (long)vma->vm_pgoff);\n+\n+\tif (offset + length > mm_vc_mem_size) {\n+\t\tpr_err(\"%s: length %ld is too big\\n\", __func__, length);\n+\t\treturn -EINVAL;\n+\t}\n+\t/* Do not cache the memory map */\n+\tvma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);\n+\n+\trc = remap_pfn_range(vma, vma->vm_start,\n+\t\t\t     (mm_vc_mem_phys_addr >> PAGE_SHIFT) +\n+\t\t\t     vma->vm_pgoff, length, vma->vm_page_prot);\n+\tif (rc)\n+\t\tpr_err(\"%s: remap_pfn_range failed (rc=%d)\\n\", __func__, rc);\n+\n+\treturn rc;\n+}\n+\n+/* File Operations for the driver. */\n+static const struct file_operations vc_mem_fops = {\n+\t.owner = THIS_MODULE,\n+\t.open = vc_mem_open,\n+\t.release = vc_mem_release,\n+\t.unlocked_ioctl = vc_mem_ioctl,\n+#ifdef CONFIG_COMPAT\n+\t.compat_ioctl = vc_mem_compat_ioctl,\n+#endif\n+\t.mmap = vc_mem_mmap,\n+};\n+\n+#ifdef CONFIG_DEBUG_FS\n+static void vc_mem_debugfs_deinit(void)\n+{\n+\tdebugfs_remove_recursive(vc_mem_debugfs_entry);\n+\tvc_mem_debugfs_entry = NULL;\n+}\n+\n+\n+static int vc_mem_debugfs_init(\n+\tstruct device *dev)\n+{\n+\tvc_mem_debugfs_entry = debugfs_create_dir(DRIVER_NAME, NULL);\n+\tif (!vc_mem_debugfs_entry) {\n+\t\tdev_warn(dev, \"could not create debugfs entry\\n\");\n+\t\treturn -EFAULT;\n+\t}\n+\n+\tdebugfs_create_x32(\"vc_mem_phys_addr\",\n+\t\t\t\t0444,\n+\t\t\t\tvc_mem_debugfs_entry,\n+\t\t\t\t(u32 *)&mm_vc_mem_phys_addr);\n+\tdebugfs_create_x32(\"vc_mem_size\",\n+\t\t\t\t0444,\n+\t\t\t\tvc_mem_debugfs_entry,\n+\t\t\t\t(u32 *)&mm_vc_mem_size);\n+\tdebugfs_create_x32(\"vc_mem_base\",\n+\t\t\t\t0444,\n+\t\t\t\tvc_mem_debugfs_entry,\n+\t\t\t\t(u32 *)&mm_vc_mem_base);\n+\n+\treturn 0;\n+}\n+\n+#endif /* CONFIG_DEBUG_FS */\n+\n+/* Module load/unload functions */\n+\n+static int __init\n+vc_mem_init(void)\n+{\n+\tint rc = -EFAULT;\n+\tstruct device *dev;\n+\n+\tpr_debug(\"%s: called\\n\", __func__);\n+\n+\tmm_vc_mem_phys_addr = phys_addr;\n+\tmm_vc_mem_size = mem_size;\n+\tmm_vc_mem_base = mem_base;\n+\n+\tvc_mem_get_size();\n+\n+\tpr_info(\"vc-mem: phys_addr:0x%08lx mem_base=0x%08x mem_size:0x%08x(%u MiB)\\n\",\n+\t\tmm_vc_mem_phys_addr, mm_vc_mem_base, mm_vc_mem_size,\n+\t\tmm_vc_mem_size / (1024 * 1024));\n+\n+\trc = alloc_chrdev_region(&vc_mem_devnum, 0, 1, DRIVER_NAME);\n+\tif (rc < 0) {\n+\t\tpr_err(\"%s: alloc_chrdev_region failed (rc=%d)\\n\",\n+\t\t       __func__, rc);\n+\t\tgoto out_err;\n+\t}\n+\n+\tcdev_init(&vc_mem_cdev, &vc_mem_fops);\n+\trc = cdev_add(&vc_mem_cdev, vc_mem_devnum, 1);\n+\tif (rc) {\n+\t\tpr_err(\"%s: cdev_add failed (rc=%d)\\n\", __func__, rc);\n+\t\tgoto out_unregister;\n+\t}\n+\n+\tvc_mem_class = class_create(THIS_MODULE, DRIVER_NAME);\n+\tif (IS_ERR(vc_mem_class)) {\n+\t\trc = PTR_ERR(vc_mem_class);\n+\t\tpr_err(\"%s: class_create failed (rc=%d)\\n\", __func__, rc);\n+\t\tgoto out_cdev_del;\n+\t}\n+\n+\tdev = device_create(vc_mem_class, NULL, vc_mem_devnum, NULL,\n+\t\t\t    DRIVER_NAME);\n+\tif (IS_ERR(dev)) {\n+\t\trc = PTR_ERR(dev);\n+\t\tpr_err(\"%s: device_create failed (rc=%d)\\n\", __func__, rc);\n+\t\tgoto out_class_destroy;\n+\t}\n+\n+#ifdef CONFIG_DEBUG_FS\n+\t/* don't fail if the debug entries cannot be created */\n+\tvc_mem_debugfs_init(dev);\n+#endif\n+\n+\tvc_mem_inited = 1;\n+\treturn 0;\n+\n+\tdevice_destroy(vc_mem_class, vc_mem_devnum);\n+\n+out_class_destroy:\n+\tclass_destroy(vc_mem_class);\n+\tvc_mem_class = NULL;\n+\n+out_cdev_del:\n+\tcdev_del(&vc_mem_cdev);\n+\n+out_unregister:\n+\tunregister_chrdev_region(vc_mem_devnum, 1);\n+\n+out_err:\n+\treturn -1;\n+}\n+\n+static void __exit\n+vc_mem_exit(void)\n+{\n+\tpr_debug(\"%s: called\\n\", __func__);\n+\n+\tif (vc_mem_inited) {\n+#if CONFIG_DEBUG_FS\n+\t\tvc_mem_debugfs_deinit();\n+#endif\n+\t\tdevice_destroy(vc_mem_class, vc_mem_devnum);\n+\t\tclass_destroy(vc_mem_class);\n+\t\tcdev_del(&vc_mem_cdev);\n+\t\tunregister_chrdev_region(vc_mem_devnum, 1);\n+\t}\n+}\n+\n+module_init(vc_mem_init);\n+module_exit(vc_mem_exit);\n+MODULE_LICENSE(\"GPL\");\n+MODULE_AUTHOR(\"Broadcom Corporation\");\n+\n+module_param(phys_addr, uint, 0644);\n+module_param(mem_size, uint, 0644);\n+module_param(mem_base, uint, 0644);\n--- /dev/null\n+++ b/include/linux/broadcom/vc_mem.h\n@@ -0,0 +1,39 @@\n+/*\n+ * Copyright 2010 - 2011 Broadcom Corporation.  All rights reserved.\n+ *\n+ * Unless you and Broadcom execute a separate written software license\n+ * agreement governing use of this software, this software is licensed to you\n+ * under the terms of the GNU General Public License version 2, available at\n+ * http://www.broadcom.com/licenses/GPLv2.php (the \"GPL\").\n+ *\n+ * Notwithstanding the above, under no circumstances may you combine this\n+ * software in any way with any other Broadcom software provided under a\n+ * license other than the GPL, without Broadcom's express prior written\n+ * consent.\n+ */\n+\n+#ifndef _VC_MEM_H\n+#define _VC_MEM_H\n+\n+#include <linux/ioctl.h>\n+\n+#define VC_MEM_IOC_MAGIC  'v'\n+\n+#define VC_MEM_IOC_MEM_PHYS_ADDR    _IOR(VC_MEM_IOC_MAGIC, 0, unsigned long)\n+#define VC_MEM_IOC_MEM_SIZE         _IOR(VC_MEM_IOC_MAGIC, 1, unsigned int)\n+#define VC_MEM_IOC_MEM_BASE         _IOR(VC_MEM_IOC_MAGIC, 2, unsigned int)\n+#define VC_MEM_IOC_MEM_LOAD         _IOR(VC_MEM_IOC_MAGIC, 3, unsigned int)\n+\n+#ifdef __KERNEL__\n+#define VC_MEM_TO_ARM_ADDR_MASK 0x3FFFFFFF\n+\n+extern unsigned long mm_vc_mem_phys_addr;\n+extern unsigned int  mm_vc_mem_size;\n+extern int vc_mem_get_current_size(void);\n+#endif\n+\n+#ifdef CONFIG_COMPAT\n+#define VC_MEM_IOC_MEM_PHYS_ADDR32  _IOR(VC_MEM_IOC_MAGIC, 0, compat_ulong_t)\n+#endif\n+\n+#endif  /* _VC_MEM_H */\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0049-Add-dev-gpiomem-device-for-rootless-user-GPIO-access.patch",
    "content": "From 09897ac552d99d483131bcf107866ac2dc51694f Mon Sep 17 00:00:00 2001\nFrom: Luke Wren <luke@raspberrypi.org>\nDate: Fri, 21 Aug 2015 23:14:48 +0100\nSubject: [PATCH] Add /dev/gpiomem device for rootless user GPIO access\n\nSigned-off-by: Luke Wren <luke@raspberrypi.org>\n\nbcm2835-gpiomem: Fix for ARCH_BCM2835 builds\n\nBuild on ARCH_BCM2835, and fail to probe if no IO resource.\n\nSee: https://github.com/raspberrypi/linux/issues/1154\n---\n drivers/char/broadcom/Kconfig           |   8 +\n drivers/char/broadcom/Makefile          |   1 +\n drivers/char/broadcom/bcm2835-gpiomem.c | 258 ++++++++++++++++++++++++\n 3 files changed, 267 insertions(+)\n create mode 100644 drivers/char/broadcom/bcm2835-gpiomem.c\n\n--- a/drivers/char/broadcom/Kconfig\n+++ b/drivers/char/broadcom/Kconfig\n@@ -16,3 +16,11 @@ config BCM2708_VCMEM\n           Helper for videocore memory access and total size allocation.\n \n endif\n+\n+config BCM2835_DEVGPIOMEM\n+\ttristate \"/dev/gpiomem rootless GPIO access via mmap() on the BCM2835\"\n+\tdefault m\n+\thelp\n+\t\tProvides users with root-free access to the GPIO registers\n+\t\ton the 2835. Calling mmap(/dev/gpiomem) will map the GPIO\n+\t\tregister page to the user's pointer.\n--- a/drivers/char/broadcom/Makefile\n+++ b/drivers/char/broadcom/Makefile\n@@ -1 +1,2 @@\n obj-$(CONFIG_BCM2708_VCMEM)\t+= vc_mem.o\n+obj-$(CONFIG_BCM2835_DEVGPIOMEM)+= bcm2835-gpiomem.o\n--- /dev/null\n+++ b/drivers/char/broadcom/bcm2835-gpiomem.c\n@@ -0,0 +1,258 @@\n+/**\n+ * GPIO memory device driver\n+ *\n+ * Creates a chardev /dev/gpiomem which will provide user access to\n+ * the BCM2835's GPIO registers when it is mmap()'d.\n+ * No longer need root for user GPIO access, but without relaxing permissions\n+ * on /dev/mem.\n+ *\n+ * Written by Luke Wren <luke@raspberrypi.org>\n+ * Copyright (c) 2015, Raspberry Pi (Trading) Ltd.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ * 1. Redistributions of source code must retain the above copyright\n+ *    notice, this list of conditions, and the following disclaimer,\n+ *    without modification.\n+ * 2. Redistributions in binary form must reproduce the above copyright\n+ *    notice, this list of conditions and the following disclaimer in the\n+ *    documentation and/or other materials provided with the distribution.\n+ * 3. The names of the above-listed copyright holders may not be used\n+ *    to endorse or promote products derived from this software without\n+ *    specific prior written permission.\n+ *\n+ * ALTERNATIVELY, this software may be distributed under the terms of the\n+ * GNU General Public License (\"GPL\") version 2, as published by the Free\n+ * Software Foundation.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS\n+ * IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,\n+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\n+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR\n+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\n+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\n+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR\n+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\n+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\n+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+#include <linux/kernel.h>\n+#include <linux/module.h>\n+#include <linux/of.h>\n+#include <linux/platform_device.h>\n+#include <linux/mm.h>\n+#include <linux/slab.h>\n+#include <linux/cdev.h>\n+#include <linux/pagemap.h>\n+#include <linux/io.h>\n+\n+#define DEVICE_NAME \"bcm2835-gpiomem\"\n+#define DRIVER_NAME \"gpiomem-bcm2835\"\n+#define DEVICE_MINOR 0\n+\n+struct bcm2835_gpiomem_instance {\n+\tunsigned long gpio_regs_phys;\n+\tstruct device *dev;\n+};\n+\n+static struct cdev bcm2835_gpiomem_cdev;\n+static dev_t bcm2835_gpiomem_devid;\n+static struct class *bcm2835_gpiomem_class;\n+static struct device *bcm2835_gpiomem_dev;\n+static struct bcm2835_gpiomem_instance *inst;\n+\n+\n+/****************************************************************************\n+*\n+*   GPIO mem chardev file ops\n+*\n+***************************************************************************/\n+\n+static int bcm2835_gpiomem_open(struct inode *inode, struct file *file)\n+{\n+\tint dev = iminor(inode);\n+\tint ret = 0;\n+\n+\tif (dev != DEVICE_MINOR) {\n+\t\tdev_err(inst->dev, \"Unknown minor device: %d\", dev);\n+\t\tret = -ENXIO;\n+\t}\n+\treturn ret;\n+}\n+\n+static int bcm2835_gpiomem_release(struct inode *inode, struct file *file)\n+{\n+\tint dev = iminor(inode);\n+\tint ret = 0;\n+\n+\tif (dev != DEVICE_MINOR) {\n+\t\tdev_err(inst->dev, \"Unknown minor device %d\", dev);\n+\t\tret = -ENXIO;\n+\t}\n+\treturn ret;\n+}\n+\n+static const struct vm_operations_struct bcm2835_gpiomem_vm_ops = {\n+#ifdef CONFIG_HAVE_IOREMAP_PROT\n+\t.access = generic_access_phys\n+#endif\n+};\n+\n+static int bcm2835_gpiomem_mmap(struct file *file, struct vm_area_struct *vma)\n+{\n+\t/* Ignore what the user says - they're getting the GPIO regs\n+\t   whether they like it or not! */\n+\tunsigned long gpio_page = inst->gpio_regs_phys >> PAGE_SHIFT;\n+\n+\tvma->vm_page_prot = phys_mem_access_prot(file, gpio_page,\n+\t\t\t\t\t\t PAGE_SIZE,\n+\t\t\t\t\t\t vma->vm_page_prot);\n+\tvma->vm_ops = &bcm2835_gpiomem_vm_ops;\n+\tif (remap_pfn_range(vma, vma->vm_start,\n+\t\t\tgpio_page,\n+\t\t\tPAGE_SIZE,\n+\t\t\tvma->vm_page_prot)) {\n+\t\treturn -EAGAIN;\n+\t}\n+\treturn 0;\n+}\n+\n+static const struct file_operations\n+bcm2835_gpiomem_fops = {\n+\t.owner = THIS_MODULE,\n+\t.open = bcm2835_gpiomem_open,\n+\t.release = bcm2835_gpiomem_release,\n+\t.mmap = bcm2835_gpiomem_mmap,\n+};\n+\n+\n+ /****************************************************************************\n+*\n+*   Probe and remove functions\n+*\n+***************************************************************************/\n+\n+\n+static int bcm2835_gpiomem_probe(struct platform_device *pdev)\n+{\n+\tint err;\n+\tvoid *ptr_err;\n+\tstruct device *dev = &pdev->dev;\n+\tstruct resource *ioresource;\n+\n+\t/* Allocate buffers and instance data */\n+\n+\tinst = kzalloc(sizeof(struct bcm2835_gpiomem_instance), GFP_KERNEL);\n+\n+\tif (!inst) {\n+\t\terr = -ENOMEM;\n+\t\tgoto failed_inst_alloc;\n+\t}\n+\n+\tinst->dev = dev;\n+\n+\tioresource = platform_get_resource(pdev, IORESOURCE_MEM, 0);\n+\tif (ioresource) {\n+\t\tinst->gpio_regs_phys = ioresource->start;\n+\t} else {\n+\t\tdev_err(inst->dev, \"failed to get IO resource\");\n+\t\terr = -ENOENT;\n+\t\tgoto failed_get_resource;\n+\t}\n+\n+\t/* Create character device entries */\n+\n+\terr = alloc_chrdev_region(&bcm2835_gpiomem_devid,\n+\t\t\t\t  DEVICE_MINOR, 1, DEVICE_NAME);\n+\tif (err != 0) {\n+\t\tdev_err(inst->dev, \"unable to allocate device number\");\n+\t\tgoto failed_alloc_chrdev;\n+\t}\n+\tcdev_init(&bcm2835_gpiomem_cdev, &bcm2835_gpiomem_fops);\n+\tbcm2835_gpiomem_cdev.owner = THIS_MODULE;\n+\terr = cdev_add(&bcm2835_gpiomem_cdev, bcm2835_gpiomem_devid, 1);\n+\tif (err != 0) {\n+\t\tdev_err(inst->dev, \"unable to register device\");\n+\t\tgoto failed_cdev_add;\n+\t}\n+\n+\t/* Create sysfs entries */\n+\n+\tbcm2835_gpiomem_class = class_create(THIS_MODULE, DEVICE_NAME);\n+\tptr_err = bcm2835_gpiomem_class;\n+\tif (IS_ERR(ptr_err))\n+\t\tgoto failed_class_create;\n+\n+\tbcm2835_gpiomem_dev = device_create(bcm2835_gpiomem_class, NULL,\n+\t\t\t\t\tbcm2835_gpiomem_devid, NULL,\n+\t\t\t\t\t\"gpiomem\");\n+\tptr_err = bcm2835_gpiomem_dev;\n+\tif (IS_ERR(ptr_err))\n+\t\tgoto failed_device_create;\n+\n+\tdev_info(inst->dev, \"Initialised: Registers at 0x%08lx\",\n+\t\tinst->gpio_regs_phys);\n+\n+\treturn 0;\n+\n+failed_device_create:\n+\tclass_destroy(bcm2835_gpiomem_class);\n+failed_class_create:\n+\tcdev_del(&bcm2835_gpiomem_cdev);\n+\terr = PTR_ERR(ptr_err);\n+failed_cdev_add:\n+\tunregister_chrdev_region(bcm2835_gpiomem_devid, 1);\n+failed_alloc_chrdev:\n+failed_get_resource:\n+\tkfree(inst);\n+failed_inst_alloc:\n+\tdev_err(inst->dev, \"could not load bcm2835_gpiomem\");\n+\treturn err;\n+}\n+\n+static int bcm2835_gpiomem_remove(struct platform_device *pdev)\n+{\n+\tstruct device *dev = inst->dev;\n+\n+\tkfree(inst);\n+\tdevice_destroy(bcm2835_gpiomem_class, bcm2835_gpiomem_devid);\n+\tclass_destroy(bcm2835_gpiomem_class);\n+\tcdev_del(&bcm2835_gpiomem_cdev);\n+\tunregister_chrdev_region(bcm2835_gpiomem_devid, 1);\n+\n+\tdev_info(dev, \"GPIO mem driver removed - OK\");\n+\treturn 0;\n+}\n+\n+ /****************************************************************************\n+*\n+*   Register the driver with device tree\n+*\n+***************************************************************************/\n+\n+static const struct of_device_id bcm2835_gpiomem_of_match[] = {\n+\t{.compatible = \"brcm,bcm2835-gpiomem\",},\n+\t{ /* sentinel */ },\n+};\n+\n+MODULE_DEVICE_TABLE(of, bcm2835_gpiomem_of_match);\n+\n+static struct platform_driver bcm2835_gpiomem_driver = {\n+\t.probe = bcm2835_gpiomem_probe,\n+\t.remove = bcm2835_gpiomem_remove,\n+\t.driver = {\n+\t\t   .name = DRIVER_NAME,\n+\t\t   .owner = THIS_MODULE,\n+\t\t   .of_match_table = bcm2835_gpiomem_of_match,\n+\t\t   },\n+};\n+\n+module_platform_driver(bcm2835_gpiomem_driver);\n+\n+MODULE_ALIAS(\"platform:gpiomem-bcm2835\");\n+MODULE_LICENSE(\"GPL\");\n+MODULE_DESCRIPTION(\"gpiomem driver for accessing GPIO from userspace\");\n+MODULE_AUTHOR(\"Luke Wren <luke@raspberrypi.org>\");\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0050-Add-SMI-driver.patch",
    "content": "From 5d41827cef0a52089040b6edd311e5c0fdae1fc9 Mon Sep 17 00:00:00 2001\nFrom: Luke Wren <wren6991@gmail.com>\nDate: Sat, 5 Sep 2015 01:14:45 +0100\nSubject: [PATCH] Add SMI driver\n\nSigned-off-by: Luke Wren <wren6991@gmail.com>\n\nMISC: bcm2835: smi: use clock manager and fix reload issues\n\nUse clock manager instead of self-made clockmanager.\n\nAlso fix some error paths that showd up during development\n(especially missing release of dma resources on rmmod)\n\nSigned-off-by: Martin Sperl <kernel@martin.sperl.org>\n\nbcm2835_smi: re-add dereference to fix DMA transfers\n---\n .../bindings/misc/brcm,bcm2835-smi-dev.txt    |  17 +\n .../bindings/misc/brcm,bcm2835-smi.txt        |  48 +\n drivers/char/broadcom/Kconfig                 |   9 +\n drivers/char/broadcom/Makefile                |   1 +\n drivers/char/broadcom/bcm2835_smi_dev.c       | 402 ++++++++\n drivers/misc/Kconfig                          |   8 +\n drivers/misc/Makefile                         |   1 +\n drivers/misc/bcm2835_smi.c                    | 955 ++++++++++++++++++\n include/linux/broadcom/bcm2835_smi.h          | 391 +++++++\n 9 files changed, 1832 insertions(+)\n create mode 100644 Documentation/devicetree/bindings/misc/brcm,bcm2835-smi-dev.txt\n create mode 100644 Documentation/devicetree/bindings/misc/brcm,bcm2835-smi.txt\n create mode 100644 drivers/char/broadcom/bcm2835_smi_dev.c\n create mode 100644 drivers/misc/bcm2835_smi.c\n create mode 100644 include/linux/broadcom/bcm2835_smi.h\n\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/misc/brcm,bcm2835-smi-dev.txt\n@@ -0,0 +1,17 @@\n+* Broadcom BCM2835 SMI character device driver.\n+\n+SMI or secondary memory interface is a peripheral specific to certain Broadcom\n+SOCs, and is helpful for talking to things like parallel-interface displays\n+and NAND flashes (in fact, most things with a parallel register interface).\n+\n+This driver adds a character device which provides a user-space interface to\n+an instance of the SMI driver.\n+\n+Required properties:\n+- compatible: \"brcm,bcm2835-smi-dev\"\n+- smi_handle: a phandle to the smi node.\n+\n+Optional properties:\n+- None.\n+\n+\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/misc/brcm,bcm2835-smi.txt\n@@ -0,0 +1,48 @@\n+* Broadcom BCM2835 SMI driver.\n+\n+SMI or secondary memory interface is a peripheral specific to certain Broadcom\n+SOCs, and is helpful for talking to things like parallel-interface displays\n+and NAND flashes (in fact, most things with a parallel register interface).\n+\n+Required properties:\n+- compatible: \"brcm,bcm2835-smi\"\n+- reg: Should contain location and length of SMI registers and SMI clkman regs\n+- interrupts: *the* SMI interrupt.\n+- pinctrl-names: should be \"default\".\n+- pinctrl-0: the phandle of the gpio pin node.\n+- brcm,smi-clock-source: the clock source for clkman\n+- brcm,smi-clock-divisor: the integer clock divisor for clkman\n+- dmas: the dma controller phandle and the DREQ number (4 on a 2835)\n+- dma-names: the name used by the driver to request its channel.\n+  Should be \"rx-tx\".\n+\n+Optional properties:\n+- None.\n+\n+Examples:\n+\n+8 data pin configuration:\n+\n+smi: smi@7e600000 {\n+\tcompatible = \"brcm,bcm2835-smi\";\n+\treg = <0x7e600000 0x44>, <0x7e1010b0 0x8>;\n+\tinterrupts = <2 16>;\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&smi_pins>;\n+\tbrcm,smi-clock-source = <6>;\n+\tbrcm,smi-clock-divisor = <4>;\n+\tdmas = <&dma 4>;\n+\tdma-names = \"rx-tx\";\n+\n+\tstatus = \"okay\";\n+};\n+\n+smi_pins: smi_pins {\n+\tbrcm,pins = <2 3 4 5 6 7 8 9 10 11 12 13 14 15>;\n+\t/* Alt 1: SMI */\n+\tbrcm,function = <5 5 5 5 5 5 5 5 5 5 5 5 5 5>;\n+\t/* /CS, /WE and /OE are pulled high, as they are\n+\t   generally active low signals */\n+\tbrcm,pull = <2 2 2 2 2 2 0 0 0 0 0 0 0 0>;\n+};\n+\n--- a/drivers/char/broadcom/Kconfig\n+++ b/drivers/char/broadcom/Kconfig\n@@ -24,3 +24,12 @@ config BCM2835_DEVGPIOMEM\n \t\tProvides users with root-free access to the GPIO registers\n \t\ton the 2835. Calling mmap(/dev/gpiomem) will map the GPIO\n \t\tregister page to the user's pointer.\n+\n+config BCM2835_SMI_DEV\n+\ttristate \"Character device driver for BCM2835 Secondary Memory Interface\"\n+\tdepends on BCM2835_SMI\n+\tdefault m\n+\thelp\n+\t\tThis driver provides a character device interface (ioctl + read/write) to\n+\t\tBroadcom's Secondary Memory interface. The low-level functionality is provided\n+\t\tby the SMI driver itself.\n--- a/drivers/char/broadcom/Makefile\n+++ b/drivers/char/broadcom/Makefile\n@@ -1,2 +1,3 @@\n obj-$(CONFIG_BCM2708_VCMEM)\t+= vc_mem.o\n obj-$(CONFIG_BCM2835_DEVGPIOMEM)+= bcm2835-gpiomem.o\n+obj-$(CONFIG_BCM2835_SMI_DEV)\t+= bcm2835_smi_dev.o\n--- /dev/null\n+++ b/drivers/char/broadcom/bcm2835_smi_dev.c\n@@ -0,0 +1,402 @@\n+/**\n+ * Character device driver for Broadcom Secondary Memory Interface\n+ *\n+ * Written by Luke Wren <luke@raspberrypi.org>\n+ * Copyright (c) 2015, Raspberry Pi (Trading) Ltd.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ * 1. Redistributions of source code must retain the above copyright\n+ *    notice, this list of conditions, and the following disclaimer,\n+ *    without modification.\n+ * 2. Redistributions in binary form must reproduce the above copyright\n+ *    notice, this list of conditions and the following disclaimer in the\n+ *    documentation and/or other materials provided with the distribution.\n+ * 3. The names of the above-listed copyright holders may not be used\n+ *    to endorse or promote products derived from this software without\n+ *    specific prior written permission.\n+ *\n+ * ALTERNATIVELY, this software may be distributed under the terms of the\n+ * GNU General Public License (\"GPL\") version 2, as published by the Free\n+ * Software Foundation.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS\n+ * IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,\n+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\n+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR\n+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\n+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\n+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR\n+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\n+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\n+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+#include <linux/kernel.h>\n+#include <linux/module.h>\n+#include <linux/of.h>\n+#include <linux/platform_device.h>\n+#include <linux/slab.h>\n+#include <linux/mm.h>\n+#include <linux/pagemap.h>\n+#include <linux/fs.h>\n+#include <linux/cdev.h>\n+#include <linux/fs.h>\n+\n+#include <linux/broadcom/bcm2835_smi.h>\n+\n+#define DEVICE_NAME \"bcm2835-smi-dev\"\n+#define DRIVER_NAME \"smi-dev-bcm2835\"\n+#define DEVICE_MINOR 0\n+\n+static struct cdev bcm2835_smi_cdev;\n+static dev_t bcm2835_smi_devid;\n+static struct class *bcm2835_smi_class;\n+static struct device *bcm2835_smi_dev;\n+\n+struct bcm2835_smi_dev_instance {\n+\tstruct device *dev;\n+};\n+\n+static struct bcm2835_smi_instance *smi_inst;\n+static struct bcm2835_smi_dev_instance *inst;\n+\n+static const char *const ioctl_names[] = {\n+\t\"READ_SETTINGS\",\n+\t\"WRITE_SETTINGS\",\n+\t\"ADDRESS\"\n+};\n+\n+/****************************************************************************\n+*\n+*   SMI chardev file ops\n+*\n+***************************************************************************/\n+static long\n+bcm2835_smi_ioctl(struct file *file, unsigned int cmd, unsigned long arg)\n+{\n+\tlong ret = 0;\n+\n+\tdev_info(inst->dev, \"serving ioctl...\");\n+\n+\tswitch (cmd) {\n+\tcase BCM2835_SMI_IOC_GET_SETTINGS:{\n+\t\tstruct smi_settings *settings;\n+\n+\t\tdev_info(inst->dev, \"Reading SMI settings to user.\");\n+\t\tsettings = bcm2835_smi_get_settings_from_regs(smi_inst);\n+\t\tif (copy_to_user((void *)arg, settings,\n+\t\t\t\t sizeof(struct smi_settings)))\n+\t\t\tdev_err(inst->dev, \"settings copy failed.\");\n+\t\tbreak;\n+\t}\n+\tcase BCM2835_SMI_IOC_WRITE_SETTINGS:{\n+\t\tstruct smi_settings *settings;\n+\n+\t\tdev_info(inst->dev, \"Setting user's SMI settings.\");\n+\t\tsettings = bcm2835_smi_get_settings_from_regs(smi_inst);\n+\t\tif (copy_from_user(settings, (void *)arg,\n+\t\t\t\t   sizeof(struct smi_settings)))\n+\t\t\tdev_err(inst->dev, \"settings copy failed.\");\n+\t\telse\n+\t\t\tbcm2835_smi_set_regs_from_settings(smi_inst);\n+\t\tbreak;\n+\t}\n+\tcase BCM2835_SMI_IOC_ADDRESS:\n+\t\tdev_info(inst->dev, \"SMI address set: 0x%02x\", (int)arg);\n+\t\tbcm2835_smi_set_address(smi_inst, arg);\n+\t\tbreak;\n+\tdefault:\n+\t\tdev_err(inst->dev, \"invalid ioctl cmd: %d\", cmd);\n+\t\tret = -ENOTTY;\n+\t\tbreak;\n+\t}\n+\n+\treturn ret;\n+}\n+\n+static int bcm2835_smi_open(struct inode *inode, struct file *file)\n+{\n+\tint dev = iminor(inode);\n+\n+\tdev_dbg(inst->dev, \"SMI device opened.\");\n+\n+\tif (dev != DEVICE_MINOR) {\n+\t\tdev_err(inst->dev,\n+\t\t\t\"bcm2835_smi_release: Unknown minor device: %d\",\n+\t\t\tdev);\n+\t\treturn -ENXIO;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int bcm2835_smi_release(struct inode *inode, struct file *file)\n+{\n+\tint dev = iminor(inode);\n+\n+\tif (dev != DEVICE_MINOR) {\n+\t\tdev_err(inst->dev,\n+\t\t\t\"bcm2835_smi_release: Unknown minor device %d\", dev);\n+\t\treturn -ENXIO;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static ssize_t dma_bounce_user(\n+\tenum dma_transfer_direction dma_dir,\n+\tchar __user *user_ptr,\n+\tsize_t count,\n+\tstruct bcm2835_smi_bounce_info *bounce)\n+{\n+\tint chunk_size;\n+\tint chunk_no = 0;\n+\tint count_left = count;\n+\n+\twhile (count_left) {\n+\t\tint rv;\n+\t\tvoid *buf;\n+\n+\t\t/* Wait for current chunk to complete: */\n+\t\tif (down_timeout(&bounce->callback_sem,\n+\t\t\tmsecs_to_jiffies(1000))) {\n+\t\t\tdev_err(inst->dev, \"DMA bounce timed out\");\n+\t\t\tcount -= (count_left);\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\tif (bounce->callback_sem.count >= DMA_BOUNCE_BUFFER_COUNT - 1)\n+\t\t\tdev_err(inst->dev, \"WARNING: Ring buffer overflow\");\n+\t\tchunk_size = count_left > DMA_BOUNCE_BUFFER_SIZE ?\n+\t\t\tDMA_BOUNCE_BUFFER_SIZE : count_left;\n+\t\tbuf = bounce->buffer[chunk_no % DMA_BOUNCE_BUFFER_COUNT];\n+\t\tif (dma_dir == DMA_DEV_TO_MEM)\n+\t\t\trv = copy_to_user(user_ptr, buf, chunk_size);\n+\t\telse\n+\t\t\trv = copy_from_user(buf, user_ptr, chunk_size);\n+\t\tif (rv)\n+\t\t\tdev_err(inst->dev, \"copy_*_user() failed!: %d\", rv);\n+\t\tuser_ptr += chunk_size;\n+\t\tcount_left -= chunk_size;\n+\t\tchunk_no++;\n+\t}\n+\treturn count;\n+}\n+\n+static ssize_t\n+bcm2835_read_file(struct file *f, char __user *user_ptr,\n+\t\t  size_t count, loff_t *offs)\n+{\n+\tint odd_bytes;\n+\n+\tdev_dbg(inst->dev, \"User reading %zu bytes from SMI.\", count);\n+\t/* We don't want to DMA a number of bytes % 4 != 0 (32 bit FIFO) */\n+\tif (count > DMA_THRESHOLD_BYTES)\n+\t\todd_bytes = count & 0x3;\n+\telse\n+\t\todd_bytes = count;\n+\tcount -= odd_bytes;\n+\tif (count) {\n+\t\tstruct bcm2835_smi_bounce_info *bounce;\n+\n+\t\tcount = bcm2835_smi_user_dma(smi_inst,\n+\t\t\tDMA_DEV_TO_MEM, user_ptr, count,\n+\t\t\t&bounce);\n+\t\tif (count)\n+\t\t\tcount = dma_bounce_user(DMA_DEV_TO_MEM, user_ptr,\n+\t\t\t\tcount, bounce);\n+\t}\n+\tif (odd_bytes) {\n+\t\t/* Read from FIFO directly if not using DMA */\n+\t\tuint8_t buf[DMA_THRESHOLD_BYTES];\n+\n+\t\tbcm2835_smi_read_buf(smi_inst, buf, odd_bytes);\n+\t\tif (copy_to_user(user_ptr, buf, odd_bytes))\n+\t\t\tdev_err(inst->dev, \"copy_to_user() failed.\");\n+\t\tcount += odd_bytes;\n+\n+\t}\n+\treturn count;\n+}\n+\n+static ssize_t\n+bcm2835_write_file(struct file *f, const char __user *user_ptr,\n+\t\t   size_t count, loff_t *offs)\n+{\n+\tint odd_bytes;\n+\n+\tdev_dbg(inst->dev, \"User writing %zu bytes to SMI.\", count);\n+\tif (count > DMA_THRESHOLD_BYTES)\n+\t\todd_bytes = count & 0x3;\n+\telse\n+\t\todd_bytes = count;\n+\tcount -= odd_bytes;\n+\tif (count) {\n+\t\tstruct bcm2835_smi_bounce_info *bounce;\n+\n+\t\tcount = bcm2835_smi_user_dma(smi_inst,\n+\t\t\tDMA_MEM_TO_DEV, (char __user *)user_ptr, count,\n+\t\t\t&bounce);\n+\t\tif (count)\n+\t\t\tcount = dma_bounce_user(DMA_MEM_TO_DEV,\n+\t\t\t\t(char __user *)user_ptr,\n+\t\t\t\tcount, bounce);\n+\t}\n+\tif (odd_bytes) {\n+\t\tuint8_t buf[DMA_THRESHOLD_BYTES];\n+\n+\t\tif (copy_from_user(buf, user_ptr, odd_bytes))\n+\t\t\tdev_err(inst->dev, \"copy_from_user() failed.\");\n+\t\telse\n+\t\t\tbcm2835_smi_write_buf(smi_inst, buf, odd_bytes);\n+\t\tcount += odd_bytes;\n+\t}\n+\treturn count;\n+}\n+\n+static const struct file_operations\n+bcm2835_smi_fops = {\n+\t.owner = THIS_MODULE,\n+\t.unlocked_ioctl = bcm2835_smi_ioctl,\n+\t.open = bcm2835_smi_open,\n+\t.release = bcm2835_smi_release,\n+\t.read = bcm2835_read_file,\n+\t.write = bcm2835_write_file,\n+};\n+\n+\n+/****************************************************************************\n+*\n+*   bcm2835_smi_probe - called when the driver is loaded.\n+*\n+***************************************************************************/\n+\n+static int bcm2835_smi_dev_probe(struct platform_device *pdev)\n+{\n+\tint err;\n+\tvoid *ptr_err;\n+\tstruct device *dev = &pdev->dev;\n+\tstruct device_node *node = dev->of_node, *smi_node;\n+\n+\tif (!node) {\n+\t\tdev_err(dev, \"No device tree node supplied!\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tsmi_node = of_parse_phandle(node, \"smi_handle\", 0);\n+\n+\tif (!smi_node) {\n+\t\tdev_err(dev, \"No such property: smi_handle\");\n+\t\treturn -ENXIO;\n+\t}\n+\n+\tsmi_inst = bcm2835_smi_get(smi_node);\n+\n+\tif (!smi_inst)\n+\t\treturn -EPROBE_DEFER;\n+\n+\t/* Allocate buffers and instance data */\n+\n+\tinst = devm_kzalloc(dev, sizeof(*inst), GFP_KERNEL);\n+\n+\tif (!inst)\n+\t\treturn -ENOMEM;\n+\n+\tinst->dev = dev;\n+\n+\t/* Create character device entries */\n+\n+\terr = alloc_chrdev_region(&bcm2835_smi_devid,\n+\t\t\t\t  DEVICE_MINOR, 1, DEVICE_NAME);\n+\tif (err != 0) {\n+\t\tdev_err(inst->dev, \"unable to allocate device number\");\n+\t\treturn -ENOMEM;\n+\t}\n+\tcdev_init(&bcm2835_smi_cdev, &bcm2835_smi_fops);\n+\tbcm2835_smi_cdev.owner = THIS_MODULE;\n+\terr = cdev_add(&bcm2835_smi_cdev, bcm2835_smi_devid, 1);\n+\tif (err != 0) {\n+\t\tdev_err(inst->dev, \"unable to register device\");\n+\t\terr = -ENOMEM;\n+\t\tgoto failed_cdev_add;\n+\t}\n+\n+\t/* Create sysfs entries */\n+\n+\tbcm2835_smi_class = class_create(THIS_MODULE, DEVICE_NAME);\n+\tptr_err = bcm2835_smi_class;\n+\tif (IS_ERR(ptr_err))\n+\t\tgoto failed_class_create;\n+\n+\tbcm2835_smi_dev = device_create(bcm2835_smi_class, NULL,\n+\t\t\t\t\tbcm2835_smi_devid, NULL,\n+\t\t\t\t\t\"smi\");\n+\tptr_err = bcm2835_smi_dev;\n+\tif (IS_ERR(ptr_err))\n+\t\tgoto failed_device_create;\n+\n+\tdev_info(inst->dev, \"initialised\");\n+\n+\treturn 0;\n+\n+failed_device_create:\n+\tclass_destroy(bcm2835_smi_class);\n+failed_class_create:\n+\tcdev_del(&bcm2835_smi_cdev);\n+\terr = PTR_ERR(ptr_err);\n+failed_cdev_add:\n+\tunregister_chrdev_region(bcm2835_smi_devid, 1);\n+\tdev_err(dev, \"could not load bcm2835_smi_dev\");\n+\treturn err;\n+}\n+\n+/****************************************************************************\n+*\n+*   bcm2835_smi_remove - called when the driver is unloaded.\n+*\n+***************************************************************************/\n+\n+static int bcm2835_smi_dev_remove(struct platform_device *pdev)\n+{\n+\tdevice_destroy(bcm2835_smi_class, bcm2835_smi_devid);\n+\tclass_destroy(bcm2835_smi_class);\n+\tcdev_del(&bcm2835_smi_cdev);\n+\tunregister_chrdev_region(bcm2835_smi_devid, 1);\n+\n+\tdev_info(inst->dev, \"SMI character dev removed - OK\");\n+\treturn 0;\n+}\n+\n+/****************************************************************************\n+*\n+*   Register the driver with device tree\n+*\n+***************************************************************************/\n+\n+static const struct of_device_id bcm2835_smi_dev_of_match[] = {\n+\t{.compatible = \"brcm,bcm2835-smi-dev\",},\n+\t{ /* sentinel */ },\n+};\n+\n+MODULE_DEVICE_TABLE(of, bcm2835_smi_dev_of_match);\n+\n+static struct platform_driver bcm2835_smi_dev_driver = {\n+\t.probe = bcm2835_smi_dev_probe,\n+\t.remove = bcm2835_smi_dev_remove,\n+\t.driver = {\n+\t\t   .name = DRIVER_NAME,\n+\t\t   .owner = THIS_MODULE,\n+\t\t   .of_match_table = bcm2835_smi_dev_of_match,\n+\t\t   },\n+};\n+\n+module_platform_driver(bcm2835_smi_dev_driver);\n+\n+MODULE_ALIAS(\"platform:smi-dev-bcm2835\");\n+MODULE_LICENSE(\"GPL\");\n+MODULE_DESCRIPTION(\n+\t\"Character device driver for BCM2835's secondary memory interface\");\n+MODULE_AUTHOR(\"Luke Wren <luke@raspberrypi.org>\");\n--- a/drivers/misc/Kconfig\n+++ b/drivers/misc/Kconfig\n@@ -9,6 +9,14 @@ config SENSORS_LIS3LV02D\n \ttristate\n \tdepends on INPUT\n \n+config BCM2835_SMI\n+\ttristate \"Broadcom 283x Secondary Memory Interface driver\"\n+\tdepends on ARCH_BCM2835\n+\tdefault m\n+\thelp\n+\t\tDriver for enabling and using Broadcom's Secondary/Slow Memory Interface.\n+\t\tAppears as /dev/bcm2835_smi. For ioctl interface see drivers/misc/bcm2835_smi.h\n+\n config AD525X_DPOT\n \ttristate \"Analog Devices Digital Potentiometers\"\n \tdepends on (I2C || SPI) && SYSFS\n--- a/drivers/misc/Makefile\n+++ b/drivers/misc/Makefile\n@@ -11,6 +11,7 @@ obj-$(CONFIG_AD525X_DPOT_SPI)\t+= ad525x_\n obj-$(CONFIG_INTEL_MID_PTI)\t+= pti.o\n obj-$(CONFIG_ATMEL_SSC)\t\t+= atmel-ssc.o\n obj-$(CONFIG_ATMEL_TCLIB)\t+= atmel_tclib.o\n+obj-$(CONFIG_BCM2835_SMI)\t+= bcm2835_smi.o\n obj-$(CONFIG_DUMMY_IRQ)\t\t+= dummy-irq.o\n obj-$(CONFIG_ICS932S401)\t+= ics932s401.o\n obj-$(CONFIG_LKDTM)\t\t+= lkdtm/\n--- /dev/null\n+++ b/drivers/misc/bcm2835_smi.c\n@@ -0,0 +1,955 @@\n+/**\n+ * Broadcom Secondary Memory Interface driver\n+ *\n+ * Written by Luke Wren <luke@raspberrypi.org>\n+ * Copyright (c) 2015, Raspberry Pi (Trading) Ltd.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ * 1. Redistributions of source code must retain the above copyright\n+ *    notice, this list of conditions, and the following disclaimer,\n+ *    without modification.\n+ * 2. Redistributions in binary form must reproduce the above copyright\n+ *    notice, this list of conditions and the following disclaimer in the\n+ *    documentation and/or other materials provided with the distribution.\n+ * 3. The names of the above-listed copyright holders may not be used\n+ *    to endorse or promote products derived from this software without\n+ *    specific prior written permission.\n+ *\n+ * ALTERNATIVELY, this software may be distributed under the terms of the\n+ * GNU General Public License (\"GPL\") version 2, as published by the Free\n+ * Software Foundation.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS\n+ * IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,\n+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\n+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR\n+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\n+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\n+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR\n+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\n+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\n+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+#include <linux/clk.h>\n+#include <linux/kernel.h>\n+#include <linux/module.h>\n+#include <linux/of.h>\n+#include <linux/platform_device.h>\n+#include <linux/of_address.h>\n+#include <linux/of_platform.h>\n+#include <linux/mm.h>\n+#include <linux/slab.h>\n+#include <linux/pagemap.h>\n+#include <linux/dma-mapping.h>\n+#include <linux/dmaengine.h>\n+#include <linux/semaphore.h>\n+#include <linux/spinlock.h>\n+#include <linux/io.h>\n+\n+#define BCM2835_SMI_IMPLEMENTATION\n+#include <linux/broadcom/bcm2835_smi.h>\n+\n+#define DRIVER_NAME \"smi-bcm2835\"\n+\n+#define N_PAGES_FROM_BYTES(n) ((n + PAGE_SIZE-1) / PAGE_SIZE)\n+\n+#define DMA_WRITE_TO_MEM true\n+#define DMA_READ_FROM_MEM false\n+\n+struct bcm2835_smi_instance {\n+\tstruct device *dev;\n+\tstruct smi_settings settings;\n+\t__iomem void *smi_regs_ptr;\n+\tdma_addr_t smi_regs_busaddr;\n+\n+\tstruct dma_chan *dma_chan;\n+\tstruct dma_slave_config dma_config;\n+\n+\tstruct bcm2835_smi_bounce_info bounce;\n+\n+\tstruct scatterlist buffer_sgl;\n+\n+\tstruct clk *clk;\n+\n+\t/* Sometimes we are called into in an atomic context (e.g. by\n+\t   JFFS2 + MTD) so we can't use a mutex */\n+\tspinlock_t transaction_lock;\n+};\n+\n+/****************************************************************************\n+*\n+*   SMI peripheral setup\n+*\n+***************************************************************************/\n+\n+static inline void write_smi_reg(struct bcm2835_smi_instance *inst,\n+\tu32 val, unsigned reg)\n+{\n+\twritel(val, inst->smi_regs_ptr + reg);\n+}\n+\n+static inline u32 read_smi_reg(struct bcm2835_smi_instance *inst, unsigned reg)\n+{\n+\treturn readl(inst->smi_regs_ptr + reg);\n+}\n+\n+/* Token-paste macro for e.g SMIDSR_RSTROBE ->  value of SMIDSR_RSTROBE_MASK */\n+#define _CONCAT(x, y) x##y\n+#define CONCAT(x, y) _CONCAT(x, y)\n+\n+#define SET_BIT_FIELD(dest, field, bits) ((dest) = \\\n+\t((dest) & ~CONCAT(field, _MASK)) | (((bits) << CONCAT(field, _OFFS))& \\\n+\t CONCAT(field, _MASK)))\n+#define GET_BIT_FIELD(src, field) (((src) & \\\n+\tCONCAT(field, _MASK)) >> CONCAT(field, _OFFS))\n+\n+static void smi_dump_context_labelled(struct bcm2835_smi_instance *inst,\n+\tconst char *label)\n+{\n+\tdev_err(inst->dev, \"SMI context dump: %s\", label);\n+\tdev_err(inst->dev, \"SMICS:  0x%08x\", read_smi_reg(inst, SMICS));\n+\tdev_err(inst->dev, \"SMIL:   0x%08x\", read_smi_reg(inst, SMIL));\n+\tdev_err(inst->dev, \"SMIDSR: 0x%08x\", read_smi_reg(inst, SMIDSR0));\n+\tdev_err(inst->dev, \"SMIDSW: 0x%08x\", read_smi_reg(inst, SMIDSW0));\n+\tdev_err(inst->dev, \"SMIDC:  0x%08x\", read_smi_reg(inst, SMIDC));\n+\tdev_err(inst->dev, \"SMIFD:  0x%08x\", read_smi_reg(inst, SMIFD));\n+\tdev_err(inst->dev, \" \");\n+}\n+\n+static inline void smi_dump_context(struct bcm2835_smi_instance *inst)\n+{\n+\tsmi_dump_context_labelled(inst, \"\");\n+}\n+\n+static void smi_get_default_settings(struct bcm2835_smi_instance *inst)\n+{\n+\tstruct smi_settings *settings = &inst->settings;\n+\n+\tsettings->data_width = SMI_WIDTH_16BIT;\n+\tsettings->pack_data = true;\n+\n+\tsettings->read_setup_time = 1;\n+\tsettings->read_hold_time = 1;\n+\tsettings->read_pace_time = 1;\n+\tsettings->read_strobe_time = 3;\n+\n+\tsettings->write_setup_time = settings->read_setup_time;\n+\tsettings->write_hold_time = settings->read_hold_time;\n+\tsettings->write_pace_time = settings->read_pace_time;\n+\tsettings->write_strobe_time = settings->read_strobe_time;\n+\n+\tsettings->dma_enable = true;\n+\tsettings->dma_passthrough_enable = false;\n+\tsettings->dma_read_thresh = 0x01;\n+\tsettings->dma_write_thresh = 0x3f;\n+\tsettings->dma_panic_read_thresh = 0x20;\n+\tsettings->dma_panic_write_thresh = 0x20;\n+}\n+\n+void bcm2835_smi_set_regs_from_settings(struct bcm2835_smi_instance *inst)\n+{\n+\tstruct smi_settings *settings = &inst->settings;\n+\tint smidsr_temp = 0, smidsw_temp = 0, smics_temp,\n+\t    smidcs_temp, smidc_temp = 0;\n+\n+\tspin_lock(&inst->transaction_lock);\n+\n+\t/* temporarily disable the peripheral: */\n+\tsmics_temp = read_smi_reg(inst, SMICS);\n+\twrite_smi_reg(inst, 0, SMICS);\n+\tsmidcs_temp = read_smi_reg(inst, SMIDCS);\n+\twrite_smi_reg(inst, 0, SMIDCS);\n+\n+\tif (settings->pack_data)\n+\t\tsmics_temp |= SMICS_PXLDAT;\n+\telse\n+\t\tsmics_temp &= ~SMICS_PXLDAT;\n+\n+\tSET_BIT_FIELD(smidsr_temp, SMIDSR_RWIDTH, settings->data_width);\n+\tSET_BIT_FIELD(smidsr_temp, SMIDSR_RSETUP, settings->read_setup_time);\n+\tSET_BIT_FIELD(smidsr_temp, SMIDSR_RHOLD, settings->read_hold_time);\n+\tSET_BIT_FIELD(smidsr_temp, SMIDSR_RPACE, settings->read_pace_time);\n+\tSET_BIT_FIELD(smidsr_temp, SMIDSR_RSTROBE, settings->read_strobe_time);\n+\twrite_smi_reg(inst, smidsr_temp, SMIDSR0);\n+\n+\tSET_BIT_FIELD(smidsw_temp, SMIDSW_WWIDTH, settings->data_width);\n+\tif (settings->data_width == SMI_WIDTH_8BIT)\n+\t\tsmidsw_temp |= SMIDSW_WSWAP;\n+\telse\n+\t\tsmidsw_temp &= ~SMIDSW_WSWAP;\n+\tSET_BIT_FIELD(smidsw_temp, SMIDSW_WSETUP, settings->write_setup_time);\n+\tSET_BIT_FIELD(smidsw_temp, SMIDSW_WHOLD, settings->write_hold_time);\n+\tSET_BIT_FIELD(smidsw_temp, SMIDSW_WPACE, settings->write_pace_time);\n+\tSET_BIT_FIELD(smidsw_temp, SMIDSW_WSTROBE,\n+\t\t\tsettings->write_strobe_time);\n+\twrite_smi_reg(inst, smidsw_temp, SMIDSW0);\n+\n+\tSET_BIT_FIELD(smidc_temp, SMIDC_REQR, settings->dma_read_thresh);\n+\tSET_BIT_FIELD(smidc_temp, SMIDC_REQW, settings->dma_write_thresh);\n+\tSET_BIT_FIELD(smidc_temp, SMIDC_PANICR,\n+\t\t      settings->dma_panic_read_thresh);\n+\tSET_BIT_FIELD(smidc_temp, SMIDC_PANICW,\n+\t\t      settings->dma_panic_write_thresh);\n+\tif (settings->dma_passthrough_enable) {\n+\t\tsmidc_temp |= SMIDC_DMAP;\n+\t\tsmidsr_temp |= SMIDSR_RDREQ;\n+\t\twrite_smi_reg(inst, smidsr_temp, SMIDSR0);\n+\t\tsmidsw_temp |= SMIDSW_WDREQ;\n+\t\twrite_smi_reg(inst, smidsw_temp, SMIDSW0);\n+\t} else\n+\t\tsmidc_temp &= ~SMIDC_DMAP;\n+\tif (settings->dma_enable)\n+\t\tsmidc_temp |= SMIDC_DMAEN;\n+\telse\n+\t\tsmidc_temp &= ~SMIDC_DMAEN;\n+\n+\twrite_smi_reg(inst, smidc_temp, SMIDC);\n+\n+\t/* re-enable (if was previously enabled) */\n+\twrite_smi_reg(inst, smics_temp, SMICS);\n+\twrite_smi_reg(inst, smidcs_temp, SMIDCS);\n+\n+\tspin_unlock(&inst->transaction_lock);\n+}\n+EXPORT_SYMBOL(bcm2835_smi_set_regs_from_settings);\n+\n+struct smi_settings *bcm2835_smi_get_settings_from_regs\n+\t(struct bcm2835_smi_instance *inst)\n+{\n+\tstruct smi_settings *settings = &inst->settings;\n+\tint smidsr, smidsw, smidc;\n+\n+\tspin_lock(&inst->transaction_lock);\n+\n+\tsmidsr = read_smi_reg(inst, SMIDSR0);\n+\tsmidsw = read_smi_reg(inst, SMIDSW0);\n+\tsmidc = read_smi_reg(inst, SMIDC);\n+\n+\tsettings->pack_data = (read_smi_reg(inst, SMICS) & SMICS_PXLDAT) ?\n+\t    true : false;\n+\n+\tsettings->data_width = GET_BIT_FIELD(smidsr, SMIDSR_RWIDTH);\n+\tsettings->read_setup_time = GET_BIT_FIELD(smidsr, SMIDSR_RSETUP);\n+\tsettings->read_hold_time = GET_BIT_FIELD(smidsr, SMIDSR_RHOLD);\n+\tsettings->read_pace_time = GET_BIT_FIELD(smidsr, SMIDSR_RPACE);\n+\tsettings->read_strobe_time = GET_BIT_FIELD(smidsr, SMIDSR_RSTROBE);\n+\n+\tsettings->write_setup_time = GET_BIT_FIELD(smidsw, SMIDSW_WSETUP);\n+\tsettings->write_hold_time = GET_BIT_FIELD(smidsw, SMIDSW_WHOLD);\n+\tsettings->write_pace_time = GET_BIT_FIELD(smidsw, SMIDSW_WPACE);\n+\tsettings->write_strobe_time = GET_BIT_FIELD(smidsw, SMIDSW_WSTROBE);\n+\n+\tsettings->dma_read_thresh = GET_BIT_FIELD(smidc, SMIDC_REQR);\n+\tsettings->dma_write_thresh = GET_BIT_FIELD(smidc, SMIDC_REQW);\n+\tsettings->dma_panic_read_thresh = GET_BIT_FIELD(smidc, SMIDC_PANICR);\n+\tsettings->dma_panic_write_thresh = GET_BIT_FIELD(smidc, SMIDC_PANICW);\n+\tsettings->dma_passthrough_enable = (smidc & SMIDC_DMAP) ? true : false;\n+\tsettings->dma_enable = (smidc & SMIDC_DMAEN) ? true : false;\n+\n+\tspin_unlock(&inst->transaction_lock);\n+\n+\treturn settings;\n+}\n+EXPORT_SYMBOL(bcm2835_smi_get_settings_from_regs);\n+\n+static inline void smi_set_address(struct bcm2835_smi_instance *inst,\n+\tunsigned int address)\n+{\n+\tint smia_temp = 0, smida_temp = 0;\n+\n+\tSET_BIT_FIELD(smia_temp, SMIA_ADDR, address);\n+\tSET_BIT_FIELD(smida_temp, SMIDA_ADDR, address);\n+\n+\t/* Write to both address registers - user doesn't care whether we're\n+\t   doing programmed or direct transfers. */\n+\twrite_smi_reg(inst, smia_temp, SMIA);\n+\twrite_smi_reg(inst, smida_temp, SMIDA);\n+}\n+\n+static void smi_setup_regs(struct bcm2835_smi_instance *inst)\n+{\n+\n+\tdev_dbg(inst->dev, \"Initialising SMI registers...\");\n+\t/* Disable the peripheral if already enabled */\n+\twrite_smi_reg(inst, 0, SMICS);\n+\twrite_smi_reg(inst, 0, SMIDCS);\n+\n+\tsmi_get_default_settings(inst);\n+\tbcm2835_smi_set_regs_from_settings(inst);\n+\tsmi_set_address(inst, 0);\n+\n+\twrite_smi_reg(inst, read_smi_reg(inst, SMICS) | SMICS_ENABLE, SMICS);\n+\twrite_smi_reg(inst, read_smi_reg(inst, SMIDCS) | SMIDCS_ENABLE,\n+\t\tSMIDCS);\n+}\n+\n+/****************************************************************************\n+*\n+*   Low-level SMI access functions\n+*   Other modules should use the exported higher-level functions e.g.\n+*   bcm2835_smi_write_buf() unless they have a good reason to use these\n+*\n+***************************************************************************/\n+\n+static inline uint32_t smi_read_single_word(struct bcm2835_smi_instance *inst)\n+{\n+\tint timeout = 0;\n+\n+\twrite_smi_reg(inst, SMIDCS_ENABLE, SMIDCS);\n+\twrite_smi_reg(inst, SMIDCS_ENABLE | SMIDCS_START, SMIDCS);\n+\t/* Make sure things happen in the right order...*/\n+\tmb();\n+\twhile (!(read_smi_reg(inst, SMIDCS) & SMIDCS_DONE) &&\n+\t\t++timeout < 10000)\n+\t\t;\n+\tif (timeout < 10000)\n+\t\treturn read_smi_reg(inst, SMIDD);\n+\n+\tdev_err(inst->dev,\n+\t\t\"SMI direct read timed out (is the clock set up correctly?)\");\n+\treturn 0;\n+}\n+\n+static inline void smi_write_single_word(struct bcm2835_smi_instance *inst,\n+\tuint32_t data)\n+{\n+\tint timeout = 0;\n+\n+\twrite_smi_reg(inst, SMIDCS_ENABLE | SMIDCS_WRITE, SMIDCS);\n+\twrite_smi_reg(inst, data, SMIDD);\n+\twrite_smi_reg(inst, SMIDCS_ENABLE | SMIDCS_WRITE | SMIDCS_START,\n+\t\tSMIDCS);\n+\n+\twhile (!(read_smi_reg(inst, SMIDCS) & SMIDCS_DONE) &&\n+\t\t++timeout < 10000)\n+\t\t;\n+\tif (timeout >= 10000)\n+\t\tdev_err(inst->dev,\n+\t\t\"SMI direct write timed out (is the clock set up correctly?)\");\n+}\n+\n+/* Initiates a programmed read into the read FIFO. It is up to the caller to\n+ * read data from the FIFO -  either via paced DMA transfer,\n+ * or polling SMICS_RXD to check whether data is available.\n+ * SMICS_ACTIVE will go low upon completion. */\n+static void smi_init_programmed_read(struct bcm2835_smi_instance *inst,\n+\tint num_transfers)\n+{\n+\tint smics_temp;\n+\n+\t/* Disable the peripheral: */\n+\tsmics_temp = read_smi_reg(inst, SMICS) & ~(SMICS_ENABLE | SMICS_WRITE);\n+\twrite_smi_reg(inst, smics_temp, SMICS);\n+\twhile (read_smi_reg(inst, SMICS) & SMICS_ENABLE)\n+\t\t;\n+\n+\t/* Program the transfer count: */\n+\twrite_smi_reg(inst, num_transfers, SMIL);\n+\n+\t/* re-enable and start: */\n+\tsmics_temp |= SMICS_ENABLE;\n+\twrite_smi_reg(inst, smics_temp, SMICS);\n+\tsmics_temp |= SMICS_CLEAR;\n+\t/* Just to be certain: */\n+\tmb();\n+\twhile (read_smi_reg(inst, SMICS) & SMICS_ACTIVE)\n+\t\t;\n+\twrite_smi_reg(inst, smics_temp, SMICS);\n+\tsmics_temp |= SMICS_START;\n+\twrite_smi_reg(inst, smics_temp, SMICS);\n+}\n+\n+/* Initiates a programmed write sequence, using data from the write FIFO.\n+ * It is up to the caller to initiate a DMA transfer before calling,\n+ * or use another method to keep the write FIFO topped up.\n+ * SMICS_ACTIVE will go low upon completion.\n+ */\n+static void smi_init_programmed_write(struct bcm2835_smi_instance *inst,\n+\tint num_transfers)\n+{\n+\tint smics_temp;\n+\n+\t/* Disable the peripheral: */\n+\tsmics_temp = read_smi_reg(inst, SMICS) & ~SMICS_ENABLE;\n+\twrite_smi_reg(inst, smics_temp, SMICS);\n+\twhile (read_smi_reg(inst, SMICS) & SMICS_ENABLE)\n+\t\t;\n+\n+\t/* Program the transfer count: */\n+\twrite_smi_reg(inst, num_transfers, SMIL);\n+\n+\t/* setup, re-enable and start: */\n+\tsmics_temp |= SMICS_WRITE | SMICS_ENABLE;\n+\twrite_smi_reg(inst, smics_temp, SMICS);\n+\tsmics_temp |= SMICS_START;\n+\twrite_smi_reg(inst, smics_temp, SMICS);\n+}\n+\n+/* Initiate a read and then poll FIFO for data, reading out as it appears. */\n+static void smi_read_fifo(struct bcm2835_smi_instance *inst,\n+\tuint32_t *dest, int n_bytes)\n+{\n+\tif (read_smi_reg(inst, SMICS) & SMICS_RXD) {\n+\t\tsmi_dump_context_labelled(inst,\n+\t\t\t\"WARNING: read FIFO not empty at start of read call.\");\n+\t\twhile (read_smi_reg(inst, SMICS))\n+\t\t\t;\n+\t}\n+\n+\t/* Dispatch the read: */\n+\tif (inst->settings.data_width == SMI_WIDTH_8BIT)\n+\t\tsmi_init_programmed_read(inst, n_bytes);\n+\telse if (inst->settings.data_width == SMI_WIDTH_16BIT)\n+\t\tsmi_init_programmed_read(inst, n_bytes / 2);\n+\telse {\n+\t\tdev_err(inst->dev, \"Unsupported data width for read.\");\n+\t\treturn;\n+\t}\n+\n+\t/* Poll FIFO to keep it empty */\n+\twhile (!(read_smi_reg(inst, SMICS) & SMICS_DONE))\n+\t\tif (read_smi_reg(inst, SMICS) & SMICS_RXD)\n+\t\t\t*dest++ = read_smi_reg(inst, SMID);\n+\n+\t/* Ensure that the FIFO is emptied */\n+\tif (read_smi_reg(inst, SMICS) & SMICS_RXD) {\n+\t\tint fifo_count;\n+\n+\t\tfifo_count = GET_BIT_FIELD(read_smi_reg(inst, SMIFD),\n+\t\t\tSMIFD_FCNT);\n+\t\twhile (fifo_count--)\n+\t\t\t*dest++ = read_smi_reg(inst, SMID);\n+\t}\n+\n+\tif (!(read_smi_reg(inst, SMICS) & SMICS_DONE))\n+\t\tsmi_dump_context_labelled(inst,\n+\t\t\t\"WARNING: transaction finished but done bit not set.\");\n+\n+\tif (read_smi_reg(inst, SMICS) & SMICS_RXD)\n+\t\tsmi_dump_context_labelled(inst,\n+\t\t\t\"WARNING: read FIFO not empty at end of read call.\");\n+\n+}\n+\n+/* Initiate a write, and then keep the FIFO topped up. */\n+static void smi_write_fifo(struct bcm2835_smi_instance *inst,\n+\tuint32_t *src, int n_bytes)\n+{\n+\tint i, timeout = 0;\n+\n+\t/* Empty FIFOs if not already so */\n+\tif (!(read_smi_reg(inst, SMICS) & SMICS_TXE)) {\n+\t\tsmi_dump_context_labelled(inst,\n+\t\t    \"WARNING: write fifo not empty at start of write call.\");\n+\t\twrite_smi_reg(inst, read_smi_reg(inst, SMICS) | SMICS_CLEAR,\n+\t\t\tSMICS);\n+\t}\n+\n+\t/* Initiate the transfer */\n+\tif (inst->settings.data_width == SMI_WIDTH_8BIT)\n+\t\tsmi_init_programmed_write(inst, n_bytes);\n+\telse if (inst->settings.data_width == SMI_WIDTH_16BIT)\n+\t\tsmi_init_programmed_write(inst, n_bytes / 2);\n+\telse {\n+\t\tdev_err(inst->dev, \"Unsupported data width for write.\");\n+\t\treturn;\n+\t}\n+\t/* Fill the FIFO: */\n+\tfor (i = 0; i < (n_bytes - 1) / 4 + 1; ++i) {\n+\t\twhile (!(read_smi_reg(inst, SMICS) & SMICS_TXD))\n+\t\t\t;\n+\t\twrite_smi_reg(inst, *src++, SMID);\n+\t}\n+\t/* Busy wait... */\n+\twhile (!(read_smi_reg(inst, SMICS) & SMICS_DONE) && ++timeout <\n+\t\t1000000)\n+\t\t;\n+\tif (timeout >= 1000000)\n+\t\tsmi_dump_context_labelled(inst,\n+\t\t\t\"Timed out on write operation!\");\n+\tif (!(read_smi_reg(inst, SMICS) & SMICS_TXE))\n+\t\tsmi_dump_context_labelled(inst,\n+\t\t\t\"WARNING: FIFO not empty at end of write operation.\");\n+}\n+\n+/****************************************************************************\n+*\n+*   SMI DMA operations\n+*\n+***************************************************************************/\n+\n+/* Disable SMI and put it into the correct direction before doing DMA setup.\n+   Stops spurious DREQs during setup. Peripheral is re-enabled by init_*() */\n+static void smi_disable(struct bcm2835_smi_instance *inst,\n+\tenum dma_transfer_direction direction)\n+{\n+\tint smics_temp = read_smi_reg(inst, SMICS) & ~SMICS_ENABLE;\n+\n+\tif (direction == DMA_DEV_TO_MEM)\n+\t\tsmics_temp &= ~SMICS_WRITE;\n+\telse\n+\t\tsmics_temp |= SMICS_WRITE;\n+\twrite_smi_reg(inst, smics_temp, SMICS);\n+\twhile (read_smi_reg(inst, SMICS) & SMICS_ACTIVE)\n+\t\t;\n+}\n+\n+static struct scatterlist *smi_scatterlist_from_buffer(\n+\tstruct bcm2835_smi_instance *inst,\n+\tdma_addr_t buf,\n+\tsize_t len,\n+\tstruct scatterlist *sg)\n+{\n+\tsg_init_table(sg, 1);\n+\tsg_dma_address(sg) = buf;\n+\tsg_dma_len(sg) = len;\n+\treturn sg;\n+}\n+\n+static void smi_dma_callback_user_copy(void *param)\n+{\n+\t/* Notify the bottom half that a chunk is ready for user copy */\n+\tstruct bcm2835_smi_instance *inst =\n+\t\t(struct bcm2835_smi_instance *)param;\n+\n+\tup(&inst->bounce.callback_sem);\n+}\n+\n+/* Creates a descriptor, assigns the given callback, and submits the\n+   descriptor to dmaengine. Does not block - can queue up multiple\n+   descriptors and then wait for them all to complete.\n+   sg_len is the number of control blocks, NOT the number of bytes.\n+   dir can be DMA_MEM_TO_DEV or DMA_DEV_TO_MEM.\n+   callback can be NULL - in this case it is not called. */\n+static inline struct dma_async_tx_descriptor *smi_dma_submit_sgl(\n+\tstruct bcm2835_smi_instance *inst,\n+\tstruct scatterlist *sgl,\n+\tsize_t sg_len,\n+\tenum dma_transfer_direction dir,\n+\tdma_async_tx_callback callback)\n+{\n+\tstruct dma_async_tx_descriptor *desc;\n+\n+\tdesc = dmaengine_prep_slave_sg(inst->dma_chan,\n+\t\t\t\t       sgl,\n+\t\t\t\t       sg_len,\n+\t\t\t\t       dir,\n+\t\t\t\t       DMA_PREP_INTERRUPT | DMA_CTRL_ACK |\n+\t\t\t\t       DMA_PREP_FENCE);\n+\tif (!desc) {\n+\t\tdev_err(inst->dev, \"read_sgl: dma slave preparation failed!\");\n+\t\twrite_smi_reg(inst, read_smi_reg(inst, SMICS) & ~SMICS_ACTIVE,\n+\t\t\tSMICS);\n+\t\twhile (read_smi_reg(inst, SMICS) & SMICS_ACTIVE)\n+\t\t\tcpu_relax();\n+\t\twrite_smi_reg(inst, read_smi_reg(inst, SMICS) | SMICS_ACTIVE,\n+\t\t\tSMICS);\n+\t\treturn NULL;\n+\t}\n+\tdesc->callback = callback;\n+\tdesc->callback_param = inst;\n+\tif (dmaengine_submit(desc) < 0)\n+\t\treturn NULL;\n+\treturn desc;\n+}\n+\n+/* NB this function blocks until the transfer is complete */\n+static void\n+smi_dma_read_sgl(struct bcm2835_smi_instance *inst,\n+\tstruct scatterlist *sgl, size_t sg_len, size_t n_bytes)\n+{\n+\tstruct dma_async_tx_descriptor *desc;\n+\n+\t/* Disable SMI and set to read before dispatching DMA - if SMI is in\n+\t * write mode and TX fifo is empty, it will generate a DREQ which may\n+\t * cause the read DMA to complete before the SMI read command is even\n+\t * dispatched! We want to dispatch DMA before SMI read so that reading\n+\t * is gapless, for logic analyser.\n+\t */\n+\n+\tsmi_disable(inst, DMA_DEV_TO_MEM);\n+\n+\tdesc = smi_dma_submit_sgl(inst, sgl, sg_len, DMA_DEV_TO_MEM, NULL);\n+\tdma_async_issue_pending(inst->dma_chan);\n+\n+\tif (inst->settings.data_width == SMI_WIDTH_8BIT)\n+\t\tsmi_init_programmed_read(inst, n_bytes);\n+\telse\n+\t\tsmi_init_programmed_read(inst, n_bytes / 2);\n+\n+\tif (dma_wait_for_async_tx(desc) == DMA_ERROR)\n+\t\tsmi_dump_context_labelled(inst, \"DMA timeout!\");\n+}\n+\n+static void\n+smi_dma_write_sgl(struct bcm2835_smi_instance *inst,\n+\tstruct scatterlist *sgl, size_t sg_len, size_t n_bytes)\n+{\n+\tstruct dma_async_tx_descriptor *desc;\n+\n+\tif (inst->settings.data_width == SMI_WIDTH_8BIT)\n+\t\tsmi_init_programmed_write(inst, n_bytes);\n+\telse\n+\t\tsmi_init_programmed_write(inst, n_bytes / 2);\n+\n+\tdesc = smi_dma_submit_sgl(inst, sgl, sg_len, DMA_MEM_TO_DEV, NULL);\n+\tdma_async_issue_pending(inst->dma_chan);\n+\n+\tif (dma_wait_for_async_tx(desc) == DMA_ERROR)\n+\t\tsmi_dump_context_labelled(inst, \"DMA timeout!\");\n+\telse\n+\t\t/* Wait for SMI to finish our writes */\n+\t\twhile (!(read_smi_reg(inst, SMICS) & SMICS_DONE))\n+\t\t\tcpu_relax();\n+}\n+\n+ssize_t bcm2835_smi_user_dma(\n+\tstruct bcm2835_smi_instance *inst,\n+\tenum dma_transfer_direction dma_dir,\n+\tchar __user *user_ptr, size_t count,\n+\tstruct bcm2835_smi_bounce_info **bounce)\n+{\n+\tint chunk_no = 0, chunk_size, count_left = count;\n+\tstruct scatterlist *sgl;\n+\tvoid (*init_trans_func)(struct bcm2835_smi_instance *, int);\n+\n+\tspin_lock(&inst->transaction_lock);\n+\n+\tif (dma_dir == DMA_DEV_TO_MEM)\n+\t\tinit_trans_func = smi_init_programmed_read;\n+\telse\n+\t\tinit_trans_func = smi_init_programmed_write;\n+\n+\tsmi_disable(inst, dma_dir);\n+\n+\tsema_init(&inst->bounce.callback_sem, 0);\n+\tif (bounce)\n+\t\t*bounce = &inst->bounce;\n+\twhile (count_left) {\n+\t\tchunk_size = count_left > DMA_BOUNCE_BUFFER_SIZE ?\n+\t\t\tDMA_BOUNCE_BUFFER_SIZE : count_left;\n+\t\tif (chunk_size == DMA_BOUNCE_BUFFER_SIZE) {\n+\t\t\tsgl =\n+\t\t\t&inst->bounce.sgl[chunk_no % DMA_BOUNCE_BUFFER_COUNT];\n+\t\t} else {\n+\t\t\tsgl = smi_scatterlist_from_buffer(\n+\t\t\t\tinst,\n+\t\t\t\tinst->bounce.phys[\n+\t\t\t\t\tchunk_no % DMA_BOUNCE_BUFFER_COUNT],\n+\t\t\t\tchunk_size,\n+\t\t\t\t&inst->buffer_sgl);\n+\t\t}\n+\n+\t\tif (!smi_dma_submit_sgl(inst, sgl, 1, dma_dir,\n+\t\t\tsmi_dma_callback_user_copy\n+\t\t)) {\n+\t\t\tdev_err(inst->dev, \"sgl submit failed\");\n+\t\t\tcount = 0;\n+\t\t\tgoto out;\n+\t\t}\n+\t\tcount_left -= chunk_size;\n+\t\tchunk_no++;\n+\t}\n+\tdma_async_issue_pending(inst->dma_chan);\n+\n+\tif (inst->settings.data_width == SMI_WIDTH_8BIT)\n+\t\tinit_trans_func(inst, count);\n+\telse if (inst->settings.data_width == SMI_WIDTH_16BIT)\n+\t\tinit_trans_func(inst, count / 2);\n+out:\n+\tspin_unlock(&inst->transaction_lock);\n+\treturn count;\n+}\n+EXPORT_SYMBOL(bcm2835_smi_user_dma);\n+\n+\n+/****************************************************************************\n+*\n+*   High level buffer transfer functions - for use by other drivers\n+*\n+***************************************************************************/\n+\n+/* Buffer must be physically contiguous - i.e. kmalloc, not vmalloc! */\n+void bcm2835_smi_write_buf(\n+\tstruct bcm2835_smi_instance *inst,\n+\tconst void *buf, size_t n_bytes)\n+{\n+\tint odd_bytes = n_bytes & 0x3;\n+\n+\tn_bytes -= odd_bytes;\n+\n+\tspin_lock(&inst->transaction_lock);\n+\n+\tif (n_bytes > DMA_THRESHOLD_BYTES) {\n+\t\tdma_addr_t phy_addr = dma_map_single(\n+\t\t\tinst->dev,\n+\t\t\t(void *)buf,\n+\t\t\tn_bytes,\n+\t\t\tDMA_MEM_TO_DEV);\n+\t\tstruct scatterlist *sgl =\n+\t\t\tsmi_scatterlist_from_buffer(inst, phy_addr, n_bytes,\n+\t\t\t\t&inst->buffer_sgl);\n+\n+\t\tif (!sgl) {\n+\t\t\tsmi_dump_context_labelled(inst,\n+\t\t\t\"Error: could not create scatterlist for write!\");\n+\t\t\tgoto out;\n+\t\t}\n+\t\tsmi_dma_write_sgl(inst, sgl, 1, n_bytes);\n+\n+\t\tdma_unmap_single\n+\t\t\t(inst->dev, phy_addr, n_bytes, DMA_MEM_TO_DEV);\n+\t} else if (n_bytes) {\n+\t\tsmi_write_fifo(inst, (uint32_t *) buf, n_bytes);\n+\t}\n+\tbuf += n_bytes;\n+\n+\tif (inst->settings.data_width == SMI_WIDTH_8BIT) {\n+\t\twhile (odd_bytes--)\n+\t\t\tsmi_write_single_word(inst, *(uint8_t *) (buf++));\n+\t} else {\n+\t\twhile (odd_bytes >= 2) {\n+\t\t\tsmi_write_single_word(inst, *(uint16_t *)buf);\n+\t\t\tbuf += 2;\n+\t\t\todd_bytes -= 2;\n+\t\t}\n+\t\tif (odd_bytes) {\n+\t\t\t/* Reading an odd number of bytes on a 16 bit bus is\n+\t\t\t   a user bug. It's kinder to fail early and tell them\n+\t\t\t   than to e.g. transparently give them the bottom byte\n+\t\t\t   of a 16 bit transfer. */\n+\t\t\tdev_err(inst->dev,\n+\t\t\"WARNING: odd number of bytes specified for wide transfer.\");\n+\t\t\tdev_err(inst->dev,\n+\t\t\"At least one byte dropped as a result.\");\n+\t\t\tdump_stack();\n+\t\t}\n+\t}\n+out:\n+\tspin_unlock(&inst->transaction_lock);\n+}\n+EXPORT_SYMBOL(bcm2835_smi_write_buf);\n+\n+void bcm2835_smi_read_buf(struct bcm2835_smi_instance *inst,\n+\tvoid *buf, size_t n_bytes)\n+{\n+\n+\t/* SMI is inherently 32-bit, which causes surprising amounts of mess\n+\t   for bytes % 4 != 0. Easiest to avoid this mess altogether\n+\t   by handling remainder separately. */\n+\tint odd_bytes = n_bytes & 0x3;\n+\n+\tspin_lock(&inst->transaction_lock);\n+\tn_bytes -= odd_bytes;\n+\tif (n_bytes > DMA_THRESHOLD_BYTES) {\n+\t\tdma_addr_t phy_addr = dma_map_single(inst->dev,\n+\t\t\t\t\t\t     buf, n_bytes,\n+\t\t\t\t\t\t     DMA_DEV_TO_MEM);\n+\t\tstruct scatterlist *sgl = smi_scatterlist_from_buffer(\n+\t\t\tinst, phy_addr, n_bytes,\n+\t\t\t&inst->buffer_sgl);\n+\t\tif (!sgl) {\n+\t\t\tsmi_dump_context_labelled(inst,\n+\t\t\t\"Error: could not create scatterlist for read!\");\n+\t\t\tgoto out;\n+\t\t}\n+\t\tsmi_dma_read_sgl(inst, sgl, 1, n_bytes);\n+\t\tdma_unmap_single(inst->dev, phy_addr, n_bytes, DMA_DEV_TO_MEM);\n+\t} else if (n_bytes) {\n+\t\tsmi_read_fifo(inst, (uint32_t *)buf, n_bytes);\n+\t}\n+\tbuf += n_bytes;\n+\n+\tif (inst->settings.data_width == SMI_WIDTH_8BIT) {\n+\t\twhile (odd_bytes--)\n+\t\t\t*((uint8_t *) (buf++)) = smi_read_single_word(inst);\n+\t} else {\n+\t\twhile (odd_bytes >= 2) {\n+\t\t\t*(uint16_t *) buf = smi_read_single_word(inst);\n+\t\t\tbuf += 2;\n+\t\t\todd_bytes -= 2;\n+\t\t}\n+\t\tif (odd_bytes) {\n+\t\t\tdev_err(inst->dev,\n+\t\t\"WARNING: odd number of bytes specified for wide transfer.\");\n+\t\t\tdev_err(inst->dev,\n+\t\t\"At least one byte dropped as a result.\");\n+\t\t\tdump_stack();\n+\t\t}\n+\t}\n+out:\n+\tspin_unlock(&inst->transaction_lock);\n+}\n+EXPORT_SYMBOL(bcm2835_smi_read_buf);\n+\n+void bcm2835_smi_set_address(struct bcm2835_smi_instance *inst,\n+\tunsigned int address)\n+{\n+\tspin_lock(&inst->transaction_lock);\n+\tsmi_set_address(inst, address);\n+\tspin_unlock(&inst->transaction_lock);\n+}\n+EXPORT_SYMBOL(bcm2835_smi_set_address);\n+\n+struct bcm2835_smi_instance *bcm2835_smi_get(struct device_node *node)\n+{\n+\tstruct platform_device *pdev;\n+\n+\tif (!node)\n+\t\treturn NULL;\n+\n+\tpdev = of_find_device_by_node(node);\n+\tif (!pdev)\n+\t\treturn NULL;\n+\n+\treturn platform_get_drvdata(pdev);\n+}\n+EXPORT_SYMBOL(bcm2835_smi_get);\n+\n+/****************************************************************************\n+*\n+*   bcm2835_smi_probe - called when the driver is loaded.\n+*\n+***************************************************************************/\n+\n+static int bcm2835_smi_dma_setup(struct bcm2835_smi_instance *inst)\n+{\n+\tint i, rv = 0;\n+\n+\tinst->dma_chan = dma_request_slave_channel(inst->dev, \"rx-tx\");\n+\n+\tinst->dma_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;\n+\tinst->dma_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;\n+\tinst->dma_config.src_addr = inst->smi_regs_busaddr + SMID;\n+\tinst->dma_config.dst_addr = inst->dma_config.src_addr;\n+\t/* Direction unimportant - always overridden by prep_slave_sg */\n+\tinst->dma_config.direction = DMA_DEV_TO_MEM;\n+\tdmaengine_slave_config(inst->dma_chan, &inst->dma_config);\n+\t/* Alloc and map bounce buffers */\n+\tfor (i = 0; i < DMA_BOUNCE_BUFFER_COUNT; ++i) {\n+\t\tinst->bounce.buffer[i] =\n+\t\tdmam_alloc_coherent(inst->dev, DMA_BOUNCE_BUFFER_SIZE,\n+\t\t\t\t&inst->bounce.phys[i],\n+\t\t\t\tGFP_KERNEL);\n+\t\tif (!inst->bounce.buffer[i]) {\n+\t\t\tdev_err(inst->dev, \"Could not allocate buffer!\");\n+\t\t\trv = -ENOMEM;\n+\t\t\tbreak;\n+\t\t}\n+\t\tsmi_scatterlist_from_buffer(\n+\t\t\tinst,\n+\t\t\tinst->bounce.phys[i],\n+\t\t\tDMA_BOUNCE_BUFFER_SIZE,\n+\t\t\t&inst->bounce.sgl[i]\n+\t\t);\n+\t}\n+\n+\treturn rv;\n+}\n+\n+static int bcm2835_smi_probe(struct platform_device *pdev)\n+{\n+\tint err;\n+\tstruct device *dev = &pdev->dev;\n+\tstruct device_node *node = dev->of_node;\n+\tstruct resource *ioresource;\n+\tstruct bcm2835_smi_instance *inst;\n+\tconst __be32 *addr;\n+\n+\t/* We require device tree support */\n+\tif (!node)\n+\t\treturn -EINVAL;\n+\t/* Allocate buffers and instance data */\n+\tinst = devm_kzalloc(dev, sizeof(struct bcm2835_smi_instance),\n+\t\tGFP_KERNEL);\n+\tif (!inst)\n+\t\treturn -ENOMEM;\n+\n+\tinst->dev = dev;\n+\tspin_lock_init(&inst->transaction_lock);\n+\n+\tioresource = platform_get_resource(pdev, IORESOURCE_MEM, 0);\n+\tinst->smi_regs_ptr = devm_ioremap_resource(dev, ioresource);\n+\tif (IS_ERR(inst->smi_regs_ptr)) {\n+\t\terr = PTR_ERR(inst->smi_regs_ptr);\n+\t\tgoto err;\n+\t}\n+\taddr = of_get_address(node, 0, NULL, NULL);\n+\tinst->smi_regs_busaddr = be32_to_cpu(*addr);\n+\n+\terr = bcm2835_smi_dma_setup(inst);\n+\tif (err)\n+\t\tgoto err;\n+\n+\t/* request clock */\n+\tinst->clk = devm_clk_get(dev, NULL);\n+\tif (!inst->clk)\n+\t\tgoto err;\n+\tclk_prepare_enable(inst->clk);\n+\n+\t/* Finally, do peripheral setup */\n+\tsmi_setup_regs(inst);\n+\n+\tplatform_set_drvdata(pdev, inst);\n+\n+\tdev_info(inst->dev, \"initialised\");\n+\n+\treturn 0;\n+err:\n+\tkfree(inst);\n+\treturn err;\n+}\n+\n+/****************************************************************************\n+*\n+*   bcm2835_smi_remove - called when the driver is unloaded.\n+*\n+***************************************************************************/\n+\n+static int bcm2835_smi_remove(struct platform_device *pdev)\n+{\n+\tstruct bcm2835_smi_instance *inst = platform_get_drvdata(pdev);\n+\tstruct device *dev = inst->dev;\n+\n+\tdmaengine_terminate_all(inst->dma_chan);\n+\tdma_release_channel(inst->dma_chan);\n+\n+\tclk_disable_unprepare(inst->clk);\n+\n+\tdev_info(dev, \"SMI device removed - OK\");\n+\treturn 0;\n+}\n+\n+/****************************************************************************\n+*\n+*   Register the driver with device tree\n+*\n+***************************************************************************/\n+\n+static const struct of_device_id bcm2835_smi_of_match[] = {\n+\t{.compatible = \"brcm,bcm2835-smi\",},\n+\t{ /* sentinel */ },\n+};\n+\n+MODULE_DEVICE_TABLE(of, bcm2835_smi_of_match);\n+\n+static struct platform_driver bcm2835_smi_driver = {\n+\t.probe = bcm2835_smi_probe,\n+\t.remove = bcm2835_smi_remove,\n+\t.driver = {\n+\t\t   .name = DRIVER_NAME,\n+\t\t   .owner = THIS_MODULE,\n+\t\t   .of_match_table = bcm2835_smi_of_match,\n+\t\t   },\n+};\n+\n+module_platform_driver(bcm2835_smi_driver);\n+\n+MODULE_ALIAS(\"platform:smi-bcm2835\");\n+MODULE_LICENSE(\"GPL\");\n+MODULE_DESCRIPTION(\"Device driver for BCM2835's secondary memory interface\");\n+MODULE_AUTHOR(\"Luke Wren <luke@raspberrypi.org>\");\n--- /dev/null\n+++ b/include/linux/broadcom/bcm2835_smi.h\n@@ -0,0 +1,391 @@\n+/**\n+ * Declarations and definitions for Broadcom's Secondary Memory Interface\n+ *\n+ * Written by Luke Wren <luke@raspberrypi.org>\n+ * Copyright (c) 2015, Raspberry Pi (Trading) Ltd.\n+ * Copyright (c) 2010-2012 Broadcom. All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ * 1. Redistributions of source code must retain the above copyright\n+ *    notice, this list of conditions, and the following disclaimer,\n+ *    without modification.\n+ * 2. Redistributions in binary form must reproduce the above copyright\n+ *    notice, this list of conditions and the following disclaimer in the\n+ *    documentation and/or other materials provided with the distribution.\n+ * 3. The names of the above-listed copyright holders may not be used\n+ *    to endorse or promote products derived from this software without\n+ *    specific prior written permission.\n+ *\n+ * ALTERNATIVELY, this software may be distributed under the terms of the\n+ * GNU General Public License (\"GPL\") version 2, as published by the Free\n+ * Software Foundation.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS\n+ * IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,\n+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\n+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR\n+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\n+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\n+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR\n+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\n+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\n+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+#ifndef BCM2835_SMI_H\n+#define BCM2835_SMI_H\n+\n+#include <linux/ioctl.h>\n+\n+#ifndef __KERNEL__\n+#include <stdint.h>\n+#include <stdbool.h>\n+#endif\n+\n+#define BCM2835_SMI_IOC_MAGIC 0x1\n+#define BCM2835_SMI_INVALID_HANDLE (~0)\n+\n+/* IOCTLs 0x100...0x1ff are not device-specific - we can use them */\n+#define BCM2835_SMI_IOC_GET_SETTINGS    _IO(BCM2835_SMI_IOC_MAGIC, 0)\n+#define BCM2835_SMI_IOC_WRITE_SETTINGS  _IO(BCM2835_SMI_IOC_MAGIC, 1)\n+#define BCM2835_SMI_IOC_ADDRESS\t _IO(BCM2835_SMI_IOC_MAGIC, 2)\n+#define BCM2835_SMI_IOC_MAX\t     2\n+\n+#define SMI_WIDTH_8BIT 0\n+#define SMI_WIDTH_16BIT 1\n+#define SMI_WIDTH_9BIT 2\n+#define SMI_WIDTH_18BIT 3\n+\n+/* max number of bytes where DMA will not be used */\n+#define DMA_THRESHOLD_BYTES 128\n+#define DMA_BOUNCE_BUFFER_SIZE (1024 * 1024 / 2)\n+#define DMA_BOUNCE_BUFFER_COUNT 3\n+\n+\n+struct smi_settings {\n+\tint data_width;\n+\t/* Whether or not to pack multiple SMI transfers into a\n+\t   single 32 bit FIFO word */\n+\tbool pack_data;\n+\n+\t/* Timing for reads (writes the same but for WE)\n+\t *\n+\t * OE ----------+\t   +--------------------\n+\t *\t\t|\t   |\n+\t *\t\t+----------+\n+\t * SD -<==============================>-----------\n+\t * SA -<=========================================>-\n+\t *    <-setup->  <-strobe ->  <-hold ->  <- pace ->\n+\t */\n+\n+\tint read_setup_time;\n+\tint read_hold_time;\n+\tint read_pace_time;\n+\tint read_strobe_time;\n+\n+\tint write_setup_time;\n+\tint write_hold_time;\n+\tint write_pace_time;\n+\tint write_strobe_time;\n+\n+\tbool dma_enable;\t\t/* DREQs */\n+\tbool dma_passthrough_enable;\t/* External DREQs */\n+\tint dma_read_thresh;\n+\tint dma_write_thresh;\n+\tint dma_panic_read_thresh;\n+\tint dma_panic_write_thresh;\n+};\n+\n+/****************************************************************************\n+*\n+*   Declare exported SMI functions\n+*\n+***************************************************************************/\n+\n+#ifdef __KERNEL__\n+\n+#include <linux/dmaengine.h> /* for enum dma_transfer_direction */\n+#include <linux/of.h>\n+#include <linux/semaphore.h>\n+\n+struct bcm2835_smi_instance;\n+\n+struct bcm2835_smi_bounce_info {\n+\tstruct semaphore callback_sem;\n+\tvoid *buffer[DMA_BOUNCE_BUFFER_COUNT];\n+\tdma_addr_t phys[DMA_BOUNCE_BUFFER_COUNT];\n+\tstruct scatterlist sgl[DMA_BOUNCE_BUFFER_COUNT];\n+};\n+\n+\n+void bcm2835_smi_set_regs_from_settings(struct bcm2835_smi_instance *);\n+\n+struct smi_settings *bcm2835_smi_get_settings_from_regs(\n+\tstruct bcm2835_smi_instance *inst);\n+\n+void bcm2835_smi_write_buf(\n+\tstruct bcm2835_smi_instance *inst,\n+\tconst void *buf,\n+\tsize_t n_bytes);\n+\n+void bcm2835_smi_read_buf(\n+\tstruct bcm2835_smi_instance *inst,\n+\tvoid *buf,\n+\tsize_t n_bytes);\n+\n+void bcm2835_smi_set_address(struct bcm2835_smi_instance *inst,\n+\tunsigned int address);\n+\n+ssize_t bcm2835_smi_user_dma(\n+\tstruct bcm2835_smi_instance *inst,\n+\tenum dma_transfer_direction dma_dir,\n+\tchar __user *user_ptr,\n+\tsize_t count,\n+\tstruct bcm2835_smi_bounce_info **bounce);\n+\n+struct bcm2835_smi_instance *bcm2835_smi_get(struct device_node *node);\n+\n+#endif /* __KERNEL__ */\n+\n+/****************************************************************\n+*\n+*\tImplementation-only declarations\n+*\n+****************************************************************/\n+\n+#ifdef BCM2835_SMI_IMPLEMENTATION\n+\n+/* Clock manager registers for SMI clock: */\n+#define CM_SMI_BASE_ADDRESS ((BCM2708_PERI_BASE) + 0x1010b0)\n+/* Clock manager \"password\" to protect registers from spurious writes */\n+#define CM_PWD (0x5a << 24)\n+\n+#define CM_SMI_CTL\t0x00\n+#define CM_SMI_DIV\t0x04\n+\n+#define CM_SMI_CTL_FLIP (1 << 8)\n+#define CM_SMI_CTL_BUSY (1 << 7)\n+#define CM_SMI_CTL_KILL (1 << 5)\n+#define CM_SMI_CTL_ENAB (1 << 4)\n+#define CM_SMI_CTL_SRC_MASK (0xf)\n+#define CM_SMI_CTL_SRC_OFFS (0)\n+\n+#define CM_SMI_DIV_DIVI_MASK (0xf <<  12)\n+#define CM_SMI_DIV_DIVI_OFFS (12)\n+#define CM_SMI_DIV_DIVF_MASK (0xff << 4)\n+#define CM_SMI_DIV_DIVF_OFFS (4)\n+\n+/* SMI register mapping:*/\n+#define SMI_BASE_ADDRESS ((BCM2708_PERI_BASE) + 0x600000)\n+\n+#define SMICS\t0x00\t/* control + status register\t\t*/\n+#define SMIL\t0x04\t/* length/count (n external txfers)\t*/\n+#define SMIA\t0x08\t/* address register\t\t\t*/\n+#define SMID\t0x0c\t/* data register\t\t\t*/\n+#define SMIDSR0\t0x10\t/* device 0 read settings\t\t*/\n+#define SMIDSW0\t0x14\t/* device 0 write settings\t\t*/\n+#define SMIDSR1\t0x18\t/* device 1 read settings\t\t*/\n+#define SMIDSW1\t0x1c\t/* device 1 write settings\t\t*/\n+#define SMIDSR2\t0x20\t/* device 2 read settings\t\t*/\n+#define SMIDSW2\t0x24\t/* device 2 write settings\t\t*/\n+#define SMIDSR3\t0x28\t/* device 3 read settings\t\t*/\n+#define SMIDSW3\t0x2c\t/* device 3 write settings\t\t*/\n+#define SMIDC\t0x30\t/* DMA control registers\t\t*/\n+#define SMIDCS\t0x34\t/* direct control/status register\t*/\n+#define SMIDA\t0x38\t/* direct address register\t\t*/\n+#define SMIDD\t0x3c\t/* direct data registers\t\t*/\n+#define SMIFD\t0x40\t/* FIFO debug register\t\t\t*/\n+\n+\n+\n+/* Control and Status register bits:\n+ * SMICS_RXF\t: RX fifo full: 1 when RX fifo is full\n+ * SMICS_TXE\t: TX fifo empty: 1 when empty.\n+ * SMICS_RXD\t: RX fifo contains data: 1 when there is data.\n+ * SMICS_TXD\t: TX fifo can accept data: 1 when true.\n+ * SMICS_RXR\t: RX fifo needs reading: 1 when fifo more than 3/4 full, or\n+ *\t\t  when \"DONE\" and fifo not emptied.\n+ * SMICS_TXW\t: TX fifo needs writing: 1 when less than 1/4 full.\n+ * SMICS_AFERR\t: AXI FIFO error: 1 when fifo read when empty or written\n+ *\t\t  when full. Write 1 to clear.\n+ * SMICS_EDREQ\t: 1 when external DREQ received.\n+ * SMICS_PXLDAT\t:  Pixel data:\twrite 1 to enable pixel transfer modes.\n+ * SMICS_SETERR\t: 1 if there was an error writing to setup regs (e.g.\n+ *\t\t  tx was in progress). Write 1 to clear.\n+ * SMICS_PVMODE\t: Set to 1 to enable pixel valve mode.\n+ * SMICS_INTR\t: Set to 1 to enable interrupt on RX.\n+ * SMICS_INTT\t: Set to 1 to enable interrupt on TX.\n+ * SMICS_INTD\t: Set to 1 to enable interrupt on DONE condition.\n+ * SMICS_TEEN\t: Tear effect mode enabled: Programmed transfers will wait\n+ *\t\t  for a TE trigger before writing.\n+ * SMICS_PAD1\t: Padding settings for external transfers. For writes: the\n+ *\t\t  number of bytes initially written to  the TX fifo that\n+ * SMICS_PAD0\t: should be ignored. For reads: the number of bytes that will\n+ *\t\t  be read before the data, and should be dropped.\n+ * SMICS_WRITE\t: Transfer direction: 1 = write to external device, 0 = read\n+ * SMICS_CLEAR\t: Write 1 to clear the FIFOs.\n+ * SMICS_START\t: Write 1 to start the programmed transfer.\n+ * SMICS_ACTIVE\t: Reads as 1 when a programmed transfer is underway.\n+ * SMICS_DONE\t: Reads as 1 when transfer finished. For RX, not set until\n+ *\t\t  FIFO emptied.\n+ * SMICS_ENABLE\t: Set to 1 to enable the SMI peripheral, 0 to disable.\n+ */\n+\n+#define SMICS_RXF\t(1 << 31)\n+#define SMICS_TXE\t(1 << 30)\n+#define SMICS_RXD\t(1 << 29)\n+#define SMICS_TXD\t(1 << 28)\n+#define SMICS_RXR\t(1 << 27)\n+#define SMICS_TXW\t(1 << 26)\n+#define SMICS_AFERR\t(1 << 25)\n+#define SMICS_EDREQ\t(1 << 15)\n+#define SMICS_PXLDAT\t(1 << 14)\n+#define SMICS_SETERR\t(1 << 13)\n+#define SMICS_PVMODE\t(1 << 12)\n+#define SMICS_INTR\t(1 << 11)\n+#define SMICS_INTT\t(1 << 10)\n+#define SMICS_INTD\t(1 << 9)\n+#define SMICS_TEEN\t(1 << 8)\n+#define SMICS_PAD1\t(1 << 7)\n+#define SMICS_PAD0\t(1 << 6)\n+#define SMICS_WRITE\t(1 << 5)\n+#define SMICS_CLEAR\t(1 << 4)\n+#define SMICS_START\t(1 << 3)\n+#define SMICS_ACTIVE\t(1 << 2)\n+#define SMICS_DONE\t(1 << 1)\n+#define SMICS_ENABLE\t(1 << 0)\n+\n+/* Address register bits: */\n+\n+#define SMIA_DEVICE_MASK ((1 << 9) | (1 << 8))\n+#define SMIA_DEVICE_OFFS (8)\n+#define SMIA_ADDR_MASK (0x3f)\t/* bits 5 -> 0 */\n+#define SMIA_ADDR_OFFS (0)\n+\n+/* DMA control register bits:\n+ * SMIDC_DMAEN\t: DMA enable: set 1: DMA requests will be issued.\n+ * SMIDC_DMAP\t: DMA passthrough: when set to 0, top two data pins are used by\n+ *\t\t  SMI as usual. When set to 1, the top two pins are used for\n+ *\t\t  external DREQs: pin 16 read request, 17 write.\n+ * SMIDC_PANIC*\t: Threshold at which DMA will panic during read/write.\n+ * SMIDC_REQ*\t: Threshold at which DMA will generate a DREQ.\n+ */\n+\n+#define SMIDC_DMAEN\t\t(1 << 28)\n+#define SMIDC_DMAP\t\t(1 << 24)\n+#define SMIDC_PANICR_MASK\t(0x3f << 18)\n+#define SMIDC_PANICR_OFFS\t(18)\n+#define SMIDC_PANICW_MASK\t(0x3f << 12)\n+#define SMIDC_PANICW_OFFS\t(12)\n+#define SMIDC_REQR_MASK\t\t(0x3f << 6)\n+#define SMIDC_REQR_OFFS\t\t(6)\n+#define SMIDC_REQW_MASK\t\t(0x3f)\n+#define SMIDC_REQW_OFFS\t\t(0)\n+\n+/* Device settings register bits: same for all 4 (or 3?) device register sets.\n+ * Device read settings:\n+ * SMIDSR_RWIDTH\t: Read transfer width. 00 = 8bit, 01 = 16bit,\n+ *\t\t\t  10 = 18bit, 11 = 9bit.\n+ * SMIDSR_RSETUP\t: Read setup time: number of core cycles between chip\n+ *\t\t\t  select/address and read strobe. Min 1, max 64.\n+ * SMIDSR_MODE68\t: 1 for System 68 mode (i.e. enable + direction pins,\n+ *\t\t\t  rather than OE + WE pin)\n+ * SMIDSR_FSETUP\t: If set to 1, setup time only applies to first\n+ *\t\t\t  transfer after address change.\n+ * SMIDSR_RHOLD\t\t: Number of core cycles between read strobe going\n+ *\t\t\t  inactive and CS/address going inactive. Min 1, max 64\n+ * SMIDSR_RPACEALL\t: When set to 1, this device's RPACE value will always\n+ *\t\t\t  be used for the next transaction, even if it is not\n+ *\t\t\t  to this device.\n+ * SMIDSR_RPACE\t\t: Number of core cycles spent waiting between CS\n+ *\t\t\t  deassert and start of next transfer. Min 1, max 128\n+ * SMIDSR_RDREQ\t\t: 1 = use external DMA request on SD16 to pace reads\n+ *\t\t\t  from device. Must also set DMAP in SMICS.\n+ * SMIDSR_RSTROBE\t: Number of cycles to assert the read strobe.\n+ *\t\t\t  min 1, max 128.\n+ */\n+#define SMIDSR_RWIDTH_MASK\t((1<<31)|(1<<30))\n+#define SMIDSR_RWIDTH_OFFS\t(30)\n+#define SMIDSR_RSETUP_MASK\t(0x3f << 24)\n+#define SMIDSR_RSETUP_OFFS\t(24)\n+#define SMIDSR_MODE68\t\t(1 << 23)\n+#define SMIDSR_FSETUP\t\t(1 << 22)\n+#define SMIDSR_RHOLD_MASK\t(0x3f << 16)\n+#define SMIDSR_RHOLD_OFFS\t(16)\n+#define SMIDSR_RPACEALL\t\t(1 << 15)\n+#define SMIDSR_RPACE_MASK\t(0x7f << 8)\n+#define SMIDSR_RPACE_OFFS\t(8)\n+#define SMIDSR_RDREQ\t\t(1 << 7)\n+#define SMIDSR_RSTROBE_MASK\t(0x7f)\n+#define SMIDSR_RSTROBE_OFFS\t(0)\n+\n+/* Device write settings:\n+ * SMIDSW_WWIDTH\t: Write transfer width. 00 = 8bit, 01 = 16bit,\n+ *\t\t\t  10= 18bit, 11 = 9bit.\n+ * SMIDSW_WSETUP\t: Number of cycles between CS assert and write strobe.\n+ *\t\t\t  Min 1, max 64.\n+ * SMIDSW_WFORMAT\t: Pixel format of input. 0 = 16bit RGB 565,\n+ *\t\t\t  1 = 32bit RGBA 8888\n+ * SMIDSW_WSWAP\t\t: 1 = swap pixel data bits. (Use with SMICS_PXLDAT)\n+ * SMIDSW_WHOLD\t\t: Time between WE deassert and CS deassert. 1 to 64\n+ * SMIDSW_WPACEALL\t: 1: this device's WPACE will be used for the next\n+ *\t\t\t  transfer, regardless of that transfer's device.\n+ * SMIDSW_WPACE\t\t: Cycles between CS deassert and next CS assert.\n+ *\t\t\t  Min 1, max 128\n+ * SMIDSW_WDREQ\t\t: Use external DREQ on pin 17 to pace writes. DMAP must\n+ *\t\t\t  be set in SMICS.\n+ * SMIDSW_WSTROBE\t: Number of cycles to assert the write strobe.\n+ *\t\t\t  Min 1, max 128\n+ */\n+#define SMIDSW_WWIDTH_MASK\t ((1<<31)|(1<<30))\n+#define SMIDSW_WWIDTH_OFFS\t(30)\n+#define SMIDSW_WSETUP_MASK\t(0x3f << 24)\n+#define SMIDSW_WSETUP_OFFS\t(24)\n+#define SMIDSW_WFORMAT\t\t(1 << 23)\n+#define SMIDSW_WSWAP\t\t(1 << 22)\n+#define SMIDSW_WHOLD_MASK\t(0x3f << 16)\n+#define SMIDSW_WHOLD_OFFS\t(16)\n+#define SMIDSW_WPACEALL\t\t(1 << 15)\n+#define SMIDSW_WPACE_MASK\t(0x7f << 8)\n+#define SMIDSW_WPACE_OFFS\t(8)\n+#define SMIDSW_WDREQ\t\t(1 << 7)\n+#define SMIDSW_WSTROBE_MASK\t (0x7f)\n+#define SMIDSW_WSTROBE_OFFS\t (0)\n+\n+/* Direct transfer control + status register\n+ * SMIDCS_WRITE\t: Direction of transfer: 1 -> write, 0 -> read\n+ * SMIDCS_DONE\t: 1 when a transfer has finished. Write 1 to clear.\n+ * SMIDCS_START\t: Write 1 to start a transfer, if one is not already underway.\n+ * SMIDCE_ENABLE: Write 1 to enable SMI in direct mode.\n+ */\n+\n+#define SMIDCS_WRITE\t\t(1 << 3)\n+#define SMIDCS_DONE\t\t(1 << 2)\n+#define SMIDCS_START\t\t(1 << 1)\n+#define SMIDCS_ENABLE\t\t(1 << 0)\n+\n+/* Direct transfer address register\n+ * SMIDA_DEVICE\t: Indicates which of the device settings banks should be used.\n+ * SMIDA_ADDR\t: The value to be asserted on the address pins.\n+ */\n+\n+#define SMIDA_DEVICE_MASK\t((1<<9)|(1<<8))\n+#define SMIDA_DEVICE_OFFS\t(8)\n+#define SMIDA_ADDR_MASK\t\t(0x3f)\n+#define SMIDA_ADDR_OFFS\t\t(0)\n+\n+/* FIFO debug register\n+ * SMIFD_FLVL\t: The high-tide mark of FIFO count during the most recent txfer\n+ * SMIFD_FCNT\t: The current FIFO count.\n+ */\n+#define SMIFD_FLVL_MASK\t\t(0x3f << 8)\n+#define SMIFD_FLVL_OFFS\t\t(8)\n+#define SMIFD_FCNT_MASK\t\t(0x3f)\n+#define SMIFD_FCNT_OFFS\t\t(0)\n+\n+#endif /* BCM2835_SMI_IMPLEMENTATION */\n+\n+#endif /* BCM2835_SMI_H */\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0051-Add-Chris-Boot-s-i2c-driver.patch",
    "content": "From 8e6989f4270ffc86166cbab697b1f539f4cdeb03 Mon Sep 17 00:00:00 2001\nFrom: popcornmix <popcornmix@gmail.com>\nDate: Wed, 17 Jun 2015 15:44:08 +0100\nSubject: [PATCH] Add Chris Boot's i2c driver\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\ni2c-bcm2708: fixed baudrate\n\nFixed issue where the wrong CDIV value was set for baudrates below 3815 Hz (for 250MHz bus clock).\nIn that case the computed CDIV value was more than 0xffff. However the CDIV register width is only 16 bits.\nThis resulted in incorrect setting of CDIV and higher baudrate than intended.\nExample: 3500Hz -> CDIV=0x11704 -> CDIV(16bit)=0x1704 -> 42430Hz\nAfter correction: 3500Hz -> CDIV=0x11704 -> CDIV(16bit)=0xffff -> 3815Hz\nThe correct baudrate is shown in the log after the cdiv > 0xffff correction.\n\nPerform I2C combined transactions when possible\n\nPerform I2C combined transactions whenever possible, within the\nrestrictions of the Broadcomm Serial Controller.\n\nDisable DONE interrupt during TA poll\n\nPrevent interrupt from being triggered if poll is missed and transfer\nstarts and finishes.\n\ni2c: Make combined transactions optional and disabled by default\n\ni2c: bcm2708: add device tree support\n\nAdd DT support to driver and add to .dtsi file.\nSetup pins in .dts file.\ni2c is disabled by default.\n\nSigned-off-by: Noralf Tronnes <notro@tronnes.org>\n\nbcm2708: don't register i2c controllers when using DT\n\nThe devices for the i2c controllers are in the Device Tree.\nOnly register devices when not using DT.\n\nSigned-off-by: Noralf Tronnes <notro@tronnes.org>\n\nI2C: Only register the I2C device for the current board revision\n\ni2c_bcm2708: Fix clock reference counting\n\nFix grabbing lock from atomic context in i2c driver\n\n2 main changes:\n- check for timeouts in the bcm2708_bsc_setup function as indicated by this comment:\n      /* poll for transfer start bit (should only take 1-20 polls) */\n  This implies that the setup function can now fail so account for this everywhere it's called\n- Removed the clk_get_rate call from inside the setup function as it locks a mutex and that's not ok since we call it from under a spin lock.\n\ni2c-bcm2708: When using DT, leave the GPIO setup to pinctrl\n\ni2c-bcm2708: Increase timeouts to allow larger transfers\n\nUse the timeout value provided by the I2C_TIMEOUT ioctl when waiting\nfor completion. The default timeout is 1 second.\n\nSee: https://github.com/raspberrypi/linux/issues/260\n\ni2c-bcm2708/BCM270X_DT: Add support for I2C2\n\nThe third I2C bus (I2C2) is normally reserved for HDMI use. Careless\nuse of this bus can break an attached display - use with caution.\n\nIt is recommended to disable accesses by VideoCore by setting\nhdmi_ignore_edid=1 or hdmi_edid_file=1 in config.txt.\n\nThe interface is disabled by default - enable using the\ni2c2_iknowwhatimdoing DT parameter.\n\nbcm2708-spi: Don't use static pin configuration with DT\n\nAlso remove superfluous error checking - the SPI framework ensures the\nvalidity of the chip_select value.\n\ni2c-bcm2708: Remove non-DT support\n\nSigned-off-by: Noralf Trønnes <noralf@tronnes.org>\n\nSet the BSC_CLKT clock streching timeout to 35ms as per SMBus specs.\n\nFixes i2c_bcm2708: Write to FIFO correctly - v2 (#1574)\n\n* i2c: fix i2c_bcm2708: Clear FIFO before sending data\n\nMake sure FIFO gets cleared before trying to send\ndata in case of a repeated start (COMBINED=Y).\n\n* i2c: fix i2c_bcm2708: Only write to FIFO when not full\n\nCheck if FIFO can accept data before writing.\nTo avoid a peripheral read on the last iteration of a loop,\nboth bcm2708_bsc_fifo_fill and ~drain are changed as well.\n---\n drivers/i2c/busses/Kconfig       |  19 ++\n drivers/i2c/busses/Makefile      |   2 +\n drivers/i2c/busses/i2c-bcm2708.c | 512 +++++++++++++++++++++++++++++++\n 3 files changed, 533 insertions(+)\n create mode 100644 drivers/i2c/busses/i2c-bcm2708.c\n\n--- a/drivers/i2c/busses/Kconfig\n+++ b/drivers/i2c/busses/Kconfig\n@@ -9,6 +9,25 @@ menu \"I2C Hardware Bus support\"\n comment \"PC SMBus host controller drivers\"\n \tdepends on PCI\n \n+config I2C_BCM2708\n+\ttristate \"BCM2708 BSC\"\n+\tdepends on ARCH_BCM2835\n+\thelp\n+\t  Enabling this option will add BSC (Broadcom Serial Controller)\n+\t  support for the BCM2708. BSC is a Broadcom proprietary bus compatible\n+\t  with I2C/TWI/SMBus.\n+\n+config I2C_BCM2708_BAUDRATE\n+\tprompt \"BCM2708 I2C baudrate\"\n+\tdepends on I2C_BCM2708\n+\tint\n+\tdefault 100000\n+\thelp\n+\t  Set the I2C baudrate. This will alter the default value. A\n+\t  different baudrate can be set by using a module parameter as well. If\n+\t  no parameter is provided when loading, this is the value that will be\n+\t  used.\n+\n config I2C_ALI1535\n \ttristate \"ALI 1535\"\n \tdepends on PCI\n--- a/drivers/i2c/busses/Makefile\n+++ b/drivers/i2c/busses/Makefile\n@@ -3,6 +3,8 @@\n # Makefile for the i2c bus drivers.\n #\n \n+obj-$(CONFIG_I2C_BCM2708)\t+= i2c-bcm2708.o\n+\n # ACPI drivers\n obj-$(CONFIG_I2C_SCMI)\t\t+= i2c-scmi.o\n \n--- /dev/null\n+++ b/drivers/i2c/busses/i2c-bcm2708.c\n@@ -0,0 +1,512 @@\n+/*\n+ * Driver for Broadcom BCM2708 BSC Controllers\n+ *\n+ * Copyright (C) 2012 Chris Boot & Frank Buss\n+ *\n+ * This driver is inspired by:\n+ * i2c-ocores.c, by Peter Korsgaard <jacmet@sunsite.dk>\n+ *\n+ * This program is free software; you can redistribute it and/or modify\n+ * it under the terms of the GNU General Public License as published by\n+ * the Free Software Foundation; either version 2 of the License, or\n+ * (at your option) any later version.\n+ *\n+ * This program is distributed in the hope that it will be useful,\n+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\n+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n+ * GNU General Public License for more details.\n+ *\n+ * You should have received a copy of the GNU General Public License\n+ * along with this program; if not, write to the Free Software\n+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.\n+ */\n+\n+#include <linux/kernel.h>\n+#include <linux/module.h>\n+#include <linux/spinlock.h>\n+#include <linux/clk.h>\n+#include <linux/err.h>\n+#include <linux/of.h>\n+#include <linux/platform_device.h>\n+#include <linux/io.h>\n+#include <linux/slab.h>\n+#include <linux/i2c.h>\n+#include <linux/interrupt.h>\n+#include <linux/sched.h>\n+#include <linux/wait.h>\n+\n+/* BSC register offsets */\n+#define BSC_C\t\t\t0x00\n+#define BSC_S\t\t\t0x04\n+#define BSC_DLEN\t\t0x08\n+#define BSC_A\t\t\t0x0c\n+#define BSC_FIFO\t\t0x10\n+#define BSC_DIV\t\t\t0x14\n+#define BSC_DEL\t\t\t0x18\n+#define BSC_CLKT\t\t0x1c\n+\n+/* Bitfields in BSC_C */\n+#define BSC_C_I2CEN\t\t0x00008000\n+#define BSC_C_INTR\t\t0x00000400\n+#define BSC_C_INTT\t\t0x00000200\n+#define BSC_C_INTD\t\t0x00000100\n+#define BSC_C_ST\t\t0x00000080\n+#define BSC_C_CLEAR_1\t\t0x00000020\n+#define BSC_C_CLEAR_2\t\t0x00000010\n+#define BSC_C_READ\t\t0x00000001\n+\n+/* Bitfields in BSC_S */\n+#define BSC_S_CLKT\t\t0x00000200\n+#define BSC_S_ERR\t\t0x00000100\n+#define BSC_S_RXF\t\t0x00000080\n+#define BSC_S_TXE\t\t0x00000040\n+#define BSC_S_RXD\t\t0x00000020\n+#define BSC_S_TXD\t\t0x00000010\n+#define BSC_S_RXR\t\t0x00000008\n+#define BSC_S_TXW\t\t0x00000004\n+#define BSC_S_DONE\t\t0x00000002\n+#define BSC_S_TA\t\t0x00000001\n+\n+#define I2C_WAIT_LOOP_COUNT\t200\n+\n+#define DRV_NAME\t\t\"bcm2708_i2c\"\n+\n+static unsigned int baudrate;\n+module_param(baudrate, uint, S_IRUSR | S_IWUSR | S_IRGRP | S_IWGRP);\n+MODULE_PARM_DESC(baudrate, \"The I2C baudrate\");\n+\n+static bool combined = false;\n+module_param(combined, bool, 0644);\n+MODULE_PARM_DESC(combined, \"Use combined transactions\");\n+\n+struct bcm2708_i2c {\n+\tstruct i2c_adapter adapter;\n+\n+\tspinlock_t lock;\n+\tvoid __iomem *base;\n+\tint irq;\n+\tstruct clk *clk;\n+\tu32 cdiv;\n+\tu32 clk_tout;\n+\n+\tstruct completion done;\n+\n+\tstruct i2c_msg *msg;\n+\tint pos;\n+\tint nmsgs;\n+\tbool error;\n+};\n+\n+static inline u32 bcm2708_rd(struct bcm2708_i2c *bi, unsigned reg)\n+{\n+\treturn readl(bi->base + reg);\n+}\n+\n+static inline void bcm2708_wr(struct bcm2708_i2c *bi, unsigned reg, u32 val)\n+{\n+\twritel(val, bi->base + reg);\n+}\n+\n+static inline void bcm2708_bsc_reset(struct bcm2708_i2c *bi)\n+{\n+\tbcm2708_wr(bi, BSC_C, 0);\n+\tbcm2708_wr(bi, BSC_S, BSC_S_CLKT | BSC_S_ERR | BSC_S_DONE);\n+}\n+\n+static inline void bcm2708_bsc_fifo_drain(struct bcm2708_i2c *bi)\n+{\n+\twhile ((bi->pos < bi->msg->len) && (bcm2708_rd(bi, BSC_S) & BSC_S_RXD))\n+\t\tbi->msg->buf[bi->pos++] = bcm2708_rd(bi, BSC_FIFO);\n+}\n+\n+static inline void bcm2708_bsc_fifo_fill(struct bcm2708_i2c *bi)\n+{\n+\twhile ((bi->pos < bi->msg->len) && (bcm2708_rd(bi, BSC_S) & BSC_S_TXD))\n+\t\tbcm2708_wr(bi, BSC_FIFO, bi->msg->buf[bi->pos++]);\n+}\n+\n+static inline int bcm2708_bsc_setup(struct bcm2708_i2c *bi)\n+{\n+\tu32 cdiv, s, clk_tout;\n+\tu32 c = BSC_C_I2CEN | BSC_C_INTD | BSC_C_ST | BSC_C_CLEAR_1;\n+\tint wait_loops = I2C_WAIT_LOOP_COUNT;\n+\n+\t/* Can't call clk_get_rate as it locks a mutex and here we are spinlocked.\n+\t * Use the value that we cached in the probe.\n+\t */\n+\tcdiv = bi->cdiv;\n+\tclk_tout = bi->clk_tout;\n+\n+\tif (bi->msg->flags & I2C_M_RD)\n+\t\tc |= BSC_C_INTR | BSC_C_READ;\n+\telse\n+\t\tc |= BSC_C_INTT;\n+\n+\tbcm2708_wr(bi, BSC_CLKT, clk_tout);\n+\tbcm2708_wr(bi, BSC_DIV, cdiv);\n+\tbcm2708_wr(bi, BSC_A, bi->msg->addr);\n+\tbcm2708_wr(bi, BSC_DLEN, bi->msg->len);\n+\tif (combined)\n+\t{\n+\t\t/* Do the next two messages meet combined transaction criteria?\n+\t\t   - Current message is a write, next message is a read\n+\t\t   - Both messages to same slave address\n+\t\t   - Write message can fit inside FIFO (16 bytes or less) */\n+\t\tif ( (bi->nmsgs > 1) &&\n+\t\t\t!(bi->msg[0].flags & I2C_M_RD) && (bi->msg[1].flags & I2C_M_RD) &&\n+\t\t\t (bi->msg[0].addr == bi->msg[1].addr) && (bi->msg[0].len <= 16)) {\n+\n+\t\t\t/* Clear FIFO */\n+\t\t\tbcm2708_wr(bi, BSC_C, BSC_C_CLEAR_1);\n+\n+\t\t\t/* Fill FIFO with entire write message (16 byte FIFO) */\n+\t\t\twhile (bi->pos < bi->msg->len) {\n+\t\t\t\tbcm2708_wr(bi, BSC_FIFO, bi->msg->buf[bi->pos++]);\n+\t\t\t}\n+\t\t\t/* Start write transfer (no interrupts, don't clear FIFO) */\n+\t\t\tbcm2708_wr(bi, BSC_C, BSC_C_I2CEN | BSC_C_ST);\n+\n+\t\t\t/* poll for transfer start bit (should only take 1-20 polls) */\n+\t\t\tdo {\n+\t\t\t\ts = bcm2708_rd(bi, BSC_S);\n+\t\t\t} while (!(s & (BSC_S_TA | BSC_S_ERR | BSC_S_CLKT | BSC_S_DONE)) && --wait_loops >= 0);\n+\n+\t\t\t/* did we time out or some error occured? */\n+\t\t\tif (wait_loops < 0 || (s & (BSC_S_ERR | BSC_S_CLKT))) {\n+\t\t\t\treturn -1;\n+\t\t\t}\n+\n+\t\t\t/* Send next read message before the write transfer finishes. */\n+\t\t\tbi->nmsgs--;\n+\t\t\tbi->msg++;\n+\t\t\tbi->pos = 0;\n+\t\t\tbcm2708_wr(bi, BSC_DLEN, bi->msg->len);\n+\t\t\tc = BSC_C_I2CEN | BSC_C_INTD | BSC_C_INTR | BSC_C_ST | BSC_C_READ;\n+\t\t}\n+\t}\n+\tbcm2708_wr(bi, BSC_C, c);\n+\n+\treturn 0;\n+}\n+\n+static irqreturn_t bcm2708_i2c_interrupt(int irq, void *dev_id)\n+{\n+\tstruct bcm2708_i2c *bi = dev_id;\n+\tbool handled = true;\n+\tu32 s;\n+\tint ret;\n+\n+\tspin_lock(&bi->lock);\n+\n+\t/* we may see camera interrupts on the \"other\" I2C channel\n+\t\t   Just return if we've not sent anything */\n+\tif (!bi->nmsgs || !bi->msg) {\n+\t\tgoto early_exit;\n+\t}\n+\n+\ts = bcm2708_rd(bi, BSC_S);\n+\n+\tif (s & (BSC_S_CLKT | BSC_S_ERR)) {\n+\t\tbcm2708_bsc_reset(bi);\n+\t\tbi->error = true;\n+\n+\t\tbi->msg = 0; /* to inform the that all work is done */\n+\t\tbi->nmsgs = 0;\n+\t\t/* wake up our bh */\n+\t\tcomplete(&bi->done);\n+\t} else if (s & BSC_S_DONE) {\n+\t\tbi->nmsgs--;\n+\n+\t\tif (bi->msg->flags & I2C_M_RD) {\n+\t\t\tbcm2708_bsc_fifo_drain(bi);\n+\t\t}\n+\n+\t\tbcm2708_bsc_reset(bi);\n+\n+\t\tif (bi->nmsgs) {\n+\t\t\t/* advance to next message */\n+\t\t\tbi->msg++;\n+\t\t\tbi->pos = 0;\n+\t\t\tret = bcm2708_bsc_setup(bi);\n+\t\t\tif (ret < 0) {\n+\t\t\t\tbcm2708_bsc_reset(bi);\n+\t\t\t\tbi->error = true;\n+\t\t\t\tbi->msg = 0; /* to inform the that all work is done */\n+\t\t\t\tbi->nmsgs = 0;\n+\t\t\t\t/* wake up our bh */\n+\t\t\t\tcomplete(&bi->done);\n+\t\t\t\tgoto early_exit;\n+\t\t\t}\n+\t\t} else {\n+\t\t\tbi->msg = 0; /* to inform the that all work is done */\n+\t\t\tbi->nmsgs = 0;\n+\t\t\t/* wake up our bh */\n+\t\t\tcomplete(&bi->done);\n+\t\t}\n+\t} else if (s & BSC_S_TXW) {\n+\t\tbcm2708_bsc_fifo_fill(bi);\n+\t} else if (s & BSC_S_RXR) {\n+\t\tbcm2708_bsc_fifo_drain(bi);\n+\t} else {\n+\t\thandled = false;\n+\t}\n+\n+early_exit:\n+\tspin_unlock(&bi->lock);\n+\n+\treturn handled ? IRQ_HANDLED : IRQ_NONE;\n+}\n+\n+static int bcm2708_i2c_master_xfer(struct i2c_adapter *adap,\n+\tstruct i2c_msg *msgs, int num)\n+{\n+\tstruct bcm2708_i2c *bi = adap->algo_data;\n+\tunsigned long flags;\n+\tint ret;\n+\n+\tspin_lock_irqsave(&bi->lock, flags);\n+\n+\treinit_completion(&bi->done);\n+\tbi->msg = msgs;\n+\tbi->pos = 0;\n+\tbi->nmsgs = num;\n+\tbi->error = false;\n+\n+\tret = bcm2708_bsc_setup(bi);\n+\n+\tspin_unlock_irqrestore(&bi->lock, flags);\n+\n+\t/* check the result of the setup */\n+\tif (ret < 0)\n+\t{\n+\t\tdev_err(&adap->dev, \"transfer setup timed out\\n\");\n+\t\tgoto error_timeout;\n+\t}\n+\n+\tret = wait_for_completion_timeout(&bi->done, adap->timeout);\n+\tif (ret == 0) {\n+\t\tdev_err(&adap->dev, \"transfer timed out\\n\");\n+\t\tgoto error_timeout;\n+\t}\n+\n+\tret = bi->error ? -EIO : num;\n+\treturn ret;\n+\n+error_timeout:\n+\tspin_lock_irqsave(&bi->lock, flags);\n+\tbcm2708_bsc_reset(bi);\n+\tbi->msg = 0; /* to inform the interrupt handler that there's nothing else to be done */\n+\tbi->nmsgs = 0;\n+\tspin_unlock_irqrestore(&bi->lock, flags);\n+\treturn -ETIMEDOUT;\n+}\n+\n+static u32 bcm2708_i2c_functionality(struct i2c_adapter *adap)\n+{\n+\treturn I2C_FUNC_I2C | /*I2C_FUNC_10BIT_ADDR |*/ I2C_FUNC_SMBUS_EMUL;\n+}\n+\n+static struct i2c_algorithm bcm2708_i2c_algorithm = {\n+\t.master_xfer = bcm2708_i2c_master_xfer,\n+\t.functionality = bcm2708_i2c_functionality,\n+};\n+\n+static int bcm2708_i2c_probe(struct platform_device *pdev)\n+{\n+\tstruct resource *regs;\n+\tint irq, err = -ENOMEM;\n+\tstruct clk *clk;\n+\tstruct bcm2708_i2c *bi;\n+\tstruct i2c_adapter *adap;\n+\tunsigned long bus_hz;\n+\tu32 cdiv, clk_tout;\n+\tu32 baud;\n+\n+\tbaud = CONFIG_I2C_BCM2708_BAUDRATE;\n+\n+\tif (pdev->dev.of_node) {\n+\t\tu32 bus_clk_rate;\n+\t\tpdev->id = of_alias_get_id(pdev->dev.of_node, \"i2c\");\n+\t\tif (pdev->id < 0) {\n+\t\t\tdev_err(&pdev->dev, \"alias is missing\\n\");\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t\tif (!of_property_read_u32(pdev->dev.of_node,\n+\t\t\t\t\t\"clock-frequency\", &bus_clk_rate))\n+\t\t\tbaud = bus_clk_rate;\n+\t\telse\n+\t\t\tdev_warn(&pdev->dev,\n+\t\t\t\t\"Could not read clock-frequency property\\n\");\n+\t}\n+\n+\tif (baudrate)\n+\t\tbaud = baudrate;\n+\n+\tregs = platform_get_resource(pdev, IORESOURCE_MEM, 0);\n+\tif (!regs) {\n+\t\tdev_err(&pdev->dev, \"could not get IO memory\\n\");\n+\t\treturn -ENXIO;\n+\t}\n+\n+\tirq = platform_get_irq(pdev, 0);\n+\tif (irq < 0) {\n+\t\tdev_err(&pdev->dev, \"could not get IRQ\\n\");\n+\t\treturn irq;\n+\t}\n+\n+\tclk = clk_get(&pdev->dev, NULL);\n+\tif (IS_ERR(clk)) {\n+\t\tdev_err(&pdev->dev, \"could not find clk: %ld\\n\", PTR_ERR(clk));\n+\t\treturn PTR_ERR(clk);\n+\t}\n+\n+\terr = clk_prepare_enable(clk);\n+\tif (err) {\n+\t\tdev_err(&pdev->dev, \"could not enable clk: %d\\n\", err);\n+\t\tgoto out_clk_put;\n+\t}\n+\n+\tbi = kzalloc(sizeof(*bi), GFP_KERNEL);\n+\tif (!bi)\n+\t\tgoto out_clk_disable;\n+\n+\tplatform_set_drvdata(pdev, bi);\n+\n+\tadap = &bi->adapter;\n+\tadap->class = I2C_CLASS_HWMON | I2C_CLASS_DDC;\n+\tadap->algo = &bcm2708_i2c_algorithm;\n+\tadap->algo_data = bi;\n+\tadap->dev.parent = &pdev->dev;\n+\tadap->nr = pdev->id;\n+\tstrlcpy(adap->name, dev_name(&pdev->dev), sizeof(adap->name));\n+\tadap->dev.of_node = pdev->dev.of_node;\n+\n+\tswitch (pdev->id) {\n+\tcase 0:\n+\t\tadap->class = I2C_CLASS_HWMON;\n+\t\tbreak;\n+\tcase 1:\n+\t\tadap->class = I2C_CLASS_DDC;\n+\t\tbreak;\n+\tcase 2:\n+\t\tadap->class = I2C_CLASS_DDC;\n+\t\tbreak;\n+\tdefault:\n+\t\tdev_err(&pdev->dev, \"can only bind to BSC 0, 1 or 2\\n\");\n+\t\terr = -ENXIO;\n+\t\tgoto out_free_bi;\n+\t}\n+\n+\tspin_lock_init(&bi->lock);\n+\tinit_completion(&bi->done);\n+\n+\tbi->base = ioremap(regs->start, resource_size(regs));\n+\tif (!bi->base) {\n+\t\tdev_err(&pdev->dev, \"could not remap memory\\n\");\n+\t\tgoto out_free_bi;\n+\t}\n+\n+\tbi->irq = irq;\n+\tbi->clk = clk;\n+\n+\terr = request_irq(irq, bcm2708_i2c_interrupt, IRQF_SHARED,\n+\t\t\tdev_name(&pdev->dev), bi);\n+\tif (err) {\n+\t\tdev_err(&pdev->dev, \"could not request IRQ: %d\\n\", err);\n+\t\tgoto out_iounmap;\n+\t}\n+\n+\tbcm2708_bsc_reset(bi);\n+\n+\terr = i2c_add_numbered_adapter(adap);\n+\tif (err < 0) {\n+\t\tdev_err(&pdev->dev, \"could not add I2C adapter: %d\\n\", err);\n+\t\tgoto out_free_irq;\n+\t}\n+\n+\tbus_hz = clk_get_rate(bi->clk);\n+\tcdiv = bus_hz / baud;\n+\tif (cdiv > 0xffff) {\n+\t\tcdiv = 0xffff;\n+\t\tbaud = bus_hz / cdiv;\n+\t}\n+\n+\tclk_tout = 35/1000*baud; //35ms timeout as per SMBus specs.\n+\tif (clk_tout > 0xffff)\n+\t\tclk_tout = 0xffff;\n+\t\n+\tbi->cdiv = cdiv;\n+\tbi->clk_tout = clk_tout;\n+\n+\tdev_info(&pdev->dev, \"BSC%d Controller at 0x%08lx (irq %d) (baudrate %d)\\n\",\n+\t\tpdev->id, (unsigned long)regs->start, irq, baud);\n+\n+\treturn 0;\n+\n+out_free_irq:\n+\tfree_irq(bi->irq, bi);\n+out_iounmap:\n+\tiounmap(bi->base);\n+out_free_bi:\n+\tkfree(bi);\n+out_clk_disable:\n+\tclk_disable_unprepare(clk);\n+out_clk_put:\n+\tclk_put(clk);\n+\treturn err;\n+}\n+\n+static int bcm2708_i2c_remove(struct platform_device *pdev)\n+{\n+\tstruct bcm2708_i2c *bi = platform_get_drvdata(pdev);\n+\n+\tplatform_set_drvdata(pdev, NULL);\n+\n+\ti2c_del_adapter(&bi->adapter);\n+\tfree_irq(bi->irq, bi);\n+\tiounmap(bi->base);\n+\tclk_disable_unprepare(bi->clk);\n+\tclk_put(bi->clk);\n+\tkfree(bi);\n+\n+\treturn 0;\n+}\n+\n+static const struct of_device_id bcm2708_i2c_of_match[] = {\n+        { .compatible = \"brcm,bcm2708-i2c\" },\n+        {},\n+};\n+MODULE_DEVICE_TABLE(of, bcm2708_i2c_of_match);\n+\n+static struct platform_driver bcm2708_i2c_driver = {\n+\t.driver\t\t= {\n+\t\t.name\t= DRV_NAME,\n+\t\t.owner\t= THIS_MODULE,\n+\t\t.of_match_table = bcm2708_i2c_of_match,\n+\t},\n+\t.probe\t\t= bcm2708_i2c_probe,\n+\t.remove\t\t= bcm2708_i2c_remove,\n+};\n+\n+// module_platform_driver(bcm2708_i2c_driver);\n+\n+\n+static int __init bcm2708_i2c_init(void)\n+{\n+\treturn platform_driver_register(&bcm2708_i2c_driver);\n+}\n+\n+static void __exit bcm2708_i2c_exit(void)\n+{\n+\tplatform_driver_unregister(&bcm2708_i2c_driver);\n+}\n+\n+module_init(bcm2708_i2c_init);\n+module_exit(bcm2708_i2c_exit);\n+\n+\n+\n+MODULE_DESCRIPTION(\"BSC controller driver for Broadcom BCM2708\");\n+MODULE_AUTHOR(\"Chris Boot <bootc@bootc.net>\");\n+MODULE_LICENSE(\"GPL v2\");\n+MODULE_ALIAS(\"platform:\" DRV_NAME);\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0052-char-broadcom-Add-vcio-module.patch",
    "content": "From ee17bae9c9f8fbe02644f13c01c6dd06e9c4bbc3 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Noralf=20Tr=C3=B8nnes?= <noralf@tronnes.org>\nDate: Fri, 26 Jun 2015 14:27:06 +0200\nSubject: [PATCH] char: broadcom: Add vcio module\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nAdd module for accessing the mailbox property channel through\n/dev/vcio. Was previously in bcm2708-vcio.\n\nSigned-off-by: Noralf Trønnes <noralf@tronnes.org>\n\nchar: vcio: Add compat ioctl handling\n\nThere was no compat ioctl handler, so 32 bit userspace on a\n64 bit kernel failed as IOCTL_MBOX_PROPERTY used the size\nof char*.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>\n\nchar: vcio: Fail probe if rpi_firmware is not found.\n\nDevice Tree is now the only supported config mechanism, therefore\nuncomment the block of code that fails the probe if the\nfirmware node can't be found.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>\n---\n drivers/char/broadcom/Kconfig  |   6 +\n drivers/char/broadcom/Makefile |   1 +\n drivers/char/broadcom/vcio.c   | 194 +++++++++++++++++++++++++++++++++\n 3 files changed, 201 insertions(+)\n create mode 100644 drivers/char/broadcom/vcio.c\n\n--- a/drivers/char/broadcom/Kconfig\n+++ b/drivers/char/broadcom/Kconfig\n@@ -15,6 +15,12 @@ config BCM2708_VCMEM\n         help\n           Helper for videocore memory access and total size allocation.\n \n+config BCM_VCIO\n+\ttristate \"Mailbox userspace access\"\n+\tdepends on BCM2835_MBOX\n+\thelp\n+\t  Gives access to the mailbox property channel from userspace.\n+\n endif\n \n config BCM2835_DEVGPIOMEM\n--- a/drivers/char/broadcom/Makefile\n+++ b/drivers/char/broadcom/Makefile\n@@ -1,3 +1,4 @@\n obj-$(CONFIG_BCM2708_VCMEM)\t+= vc_mem.o\n+obj-$(CONFIG_BCM_VCIO)\t\t+= vcio.o\n obj-$(CONFIG_BCM2835_DEVGPIOMEM)+= bcm2835-gpiomem.o\n obj-$(CONFIG_BCM2835_SMI_DEV)\t+= bcm2835_smi_dev.o\n--- /dev/null\n+++ b/drivers/char/broadcom/vcio.c\n@@ -0,0 +1,194 @@\n+/*\n+ *  Copyright (C) 2010 Broadcom\n+ *  Copyright (C) 2015 Noralf Trønnes\n+ *\n+ * This program is free software; you can redistribute it and/or modify\n+ * it under the terms of the GNU General Public License version 2 as\n+ * published by the Free Software Foundation.\n+ *\n+ */\n+\n+#define pr_fmt(fmt) KBUILD_MODNAME \": \" fmt\n+\n+#include <linux/cdev.h>\n+#include <linux/device.h>\n+#include <linux/fs.h>\n+#include <linux/init.h>\n+#include <linux/ioctl.h>\n+#include <linux/module.h>\n+#include <linux/slab.h>\n+#include <linux/uaccess.h>\n+#include <soc/bcm2835/raspberrypi-firmware.h>\n+\n+#define MBOX_CHAN_PROPERTY 8\n+\n+#define VCIO_IOC_MAGIC 100\n+#define IOCTL_MBOX_PROPERTY _IOWR(VCIO_IOC_MAGIC, 0, char *)\n+#ifdef CONFIG_COMPAT\n+#define IOCTL_MBOX_PROPERTY32 _IOWR(VCIO_IOC_MAGIC, 0, compat_uptr_t)\n+#endif\n+\n+static struct {\n+\tdev_t devt;\n+\tstruct cdev cdev;\n+\tstruct class *class;\n+\tstruct rpi_firmware *fw;\n+} vcio;\n+\n+static int vcio_user_property_list(void *user)\n+{\n+\tu32 *buf, size;\n+\tint ret;\n+\n+\t/* The first 32-bit is the size of the buffer */\n+\tif (copy_from_user(&size, user, sizeof(size)))\n+\t\treturn -EFAULT;\n+\n+\tbuf = kmalloc(size, GFP_KERNEL);\n+\tif (!buf)\n+\t\treturn -ENOMEM;\n+\n+\tif (copy_from_user(buf, user, size)) {\n+\t\tkfree(buf);\n+\t\treturn -EFAULT;\n+\t}\n+\n+\t/* Strip off protocol encapsulation */\n+\tret = rpi_firmware_property_list(vcio.fw, &buf[2], size - 12);\n+\tif (ret) {\n+\t\tkfree(buf);\n+\t\treturn ret;\n+\t}\n+\n+\tbuf[1] = RPI_FIRMWARE_STATUS_SUCCESS;\n+\tif (copy_to_user(user, buf, size))\n+\t\tret = -EFAULT;\n+\n+\tkfree(buf);\n+\n+\treturn ret;\n+}\n+\n+static int vcio_device_open(struct inode *inode, struct file *file)\n+{\n+\ttry_module_get(THIS_MODULE);\n+\n+\treturn 0;\n+}\n+\n+static int vcio_device_release(struct inode *inode, struct file *file)\n+{\n+\tmodule_put(THIS_MODULE);\n+\n+\treturn 0;\n+}\n+\n+static long vcio_device_ioctl(struct file *file, unsigned int ioctl_num,\n+\t\t\t      unsigned long ioctl_param)\n+{\n+\tswitch (ioctl_num) {\n+\tcase IOCTL_MBOX_PROPERTY:\n+\t\treturn vcio_user_property_list((void *)ioctl_param);\n+\tdefault:\n+\t\tpr_err(\"unknown ioctl: %x\\n\", ioctl_num);\n+\t\treturn -EINVAL;\n+\t}\n+}\n+\n+#ifdef CONFIG_COMPAT\n+static long vcio_device_compat_ioctl(struct file *file, unsigned int ioctl_num,\n+\t\t\t\t     unsigned long ioctl_param)\n+{\n+\tswitch (ioctl_num) {\n+\tcase IOCTL_MBOX_PROPERTY32:\n+\t\treturn vcio_user_property_list(compat_ptr(ioctl_param));\n+\tdefault:\n+\t\tpr_err(\"unknown ioctl: %x\\n\", ioctl_num);\n+\t\treturn -EINVAL;\n+\t}\n+}\n+#endif\n+\n+const struct file_operations vcio_fops = {\n+\t.unlocked_ioctl = vcio_device_ioctl,\n+#ifdef CONFIG_COMPAT\n+\t.compat_ioctl = vcio_device_compat_ioctl,\n+#endif\n+\t.open = vcio_device_open,\n+\t.release = vcio_device_release,\n+};\n+\n+static int __init vcio_init(void)\n+{\n+\tstruct device_node *np;\n+\tstatic struct device *dev;\n+\tint ret;\n+\n+\tnp = of_find_compatible_node(NULL, NULL,\n+\t\t\t\t     \"raspberrypi,bcm2835-firmware\");\n+\tif (!of_device_is_available(np))\n+\t\treturn -ENODEV;\n+\n+\tvcio.fw = rpi_firmware_get(np);\n+\tif (!vcio.fw)\n+\t\treturn -ENODEV;\n+\n+\tret = alloc_chrdev_region(&vcio.devt, 0, 1, \"vcio\");\n+\tif (ret) {\n+\t\tpr_err(\"failed to allocate device number\\n\");\n+\t\treturn ret;\n+\t}\n+\n+\tcdev_init(&vcio.cdev, &vcio_fops);\n+\tvcio.cdev.owner = THIS_MODULE;\n+\tret = cdev_add(&vcio.cdev, vcio.devt, 1);\n+\tif (ret) {\n+\t\tpr_err(\"failed to register device\\n\");\n+\t\tgoto err_unregister_chardev;\n+\t}\n+\n+\t/*\n+\t * Create sysfs entries\n+\t * 'bcm2708_vcio' is used for backwards compatibility so we don't break\n+\t * userspace. Raspian has a udev rule that changes the permissions.\n+\t */\n+\tvcio.class = class_create(THIS_MODULE, \"bcm2708_vcio\");\n+\tif (IS_ERR(vcio.class)) {\n+\t\tret = PTR_ERR(vcio.class);\n+\t\tpr_err(\"failed to create class\\n\");\n+\t\tgoto err_cdev_del;\n+\t}\n+\n+\tdev = device_create(vcio.class, NULL, vcio.devt, NULL, \"vcio\");\n+\tif (IS_ERR(dev)) {\n+\t\tret = PTR_ERR(dev);\n+\t\tpr_err(\"failed to create device\\n\");\n+\t\tgoto err_class_destroy;\n+\t}\n+\n+\treturn 0;\n+\n+err_class_destroy:\n+\tclass_destroy(vcio.class);\n+err_cdev_del:\n+\tcdev_del(&vcio.cdev);\n+err_unregister_chardev:\n+\tunregister_chrdev_region(vcio.devt, 1);\n+\n+\treturn ret;\n+}\n+module_init(vcio_init);\n+\n+static void __exit vcio_exit(void)\n+{\n+\tdevice_destroy(vcio.class, vcio.devt);\n+\tclass_destroy(vcio.class);\n+\tcdev_del(&vcio.cdev);\n+\tunregister_chrdev_region(vcio.devt, 1);\n+}\n+module_exit(vcio_exit);\n+\n+MODULE_AUTHOR(\"Gray Girling\");\n+MODULE_AUTHOR(\"Noralf Trønnes\");\n+MODULE_DESCRIPTION(\"Mailbox userspace access\");\n+MODULE_LICENSE(\"GPL\");\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0053-firmware-bcm2835-Support-ARCH_BCM270x.patch",
    "content": "From 410ae9727ad520a140b88c7151e0432d58516bc3 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Noralf=20Tr=C3=B8nnes?= <noralf@tronnes.org>\nDate: Fri, 26 Jun 2015 14:25:01 +0200\nSubject: [PATCH] firmware: bcm2835: Support ARCH_BCM270x\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nSupport booting without Device Tree.\nTurn on USB power.\nLoad driver early because of lacking support for deferred probing\nin many drivers.\n\nSigned-off-by: Noralf Trønnes <noralf@tronnes.org>\n\nfirmware: bcm2835: Don't turn on USB power\n\nThe raspberrypi-power driver is now used to turn on USB power.\n\nThis partly reverts commit:\nfirmware: bcm2835: Support ARCH_BCM270x\n\nSigned-off-by: Noralf Trønnes <noralf@tronnes.org>\n---\n drivers/firmware/raspberrypi.c | 19 +++++++++++++++++--\n 1 file changed, 17 insertions(+), 2 deletions(-)\n\n--- a/drivers/firmware/raspberrypi.c\n+++ b/drivers/firmware/raspberrypi.c\n@@ -32,6 +32,8 @@ struct rpi_firmware {\n \tstruct kref consumers;\n };\n \n+static struct platform_device *g_pdev;\n+\n static DEFINE_MUTEX(transaction_lock);\n \n static void response_callback(struct mbox_client *cl, void *msg)\n@@ -272,6 +274,7 @@ static int rpi_firmware_probe(struct pla\n \tkref_init(&fw->consumers);\n \n \tplatform_set_drvdata(pdev, fw);\n+\tg_pdev = pdev;\n \n \trpi_firmware_print_firmware_revision(fw);\n \trpi_register_hwmon_driver(dev, fw);\n@@ -301,6 +304,8 @@ static int rpi_firmware_remove(struct pl\n \n \trpi_firmware_put(fw);\n \n+\tg_pdev = NULL;\n+\n \treturn 0;\n }\n \n@@ -314,7 +319,7 @@ static int rpi_firmware_remove(struct pl\n  */\n struct rpi_firmware *rpi_firmware_get(struct device_node *firmware_node)\n {\n-\tstruct platform_device *pdev = of_find_device_by_node(firmware_node);\n+\tstruct platform_device *pdev = g_pdev;\n \tstruct rpi_firmware *fw;\n \n \tif (!pdev)\n@@ -327,12 +332,9 @@ struct rpi_firmware *rpi_firmware_get(st\n \tif (!kref_get_unless_zero(&fw->consumers))\n \t\tgoto err_put_device;\n \n-\tput_device(&pdev->dev);\n-\n \treturn fw;\n \n err_put_device:\n-\tput_device(&pdev->dev);\n \treturn NULL;\n }\n EXPORT_SYMBOL_GPL(rpi_firmware_get);\n@@ -352,7 +354,18 @@ static struct platform_driver rpi_firmwa\n \t.shutdown\t= rpi_firmware_shutdown,\n \t.remove\t\t= rpi_firmware_remove,\n };\n-module_platform_driver(rpi_firmware_driver);\n+\n+static int __init rpi_firmware_init(void)\n+{\n+\treturn platform_driver_register(&rpi_firmware_driver);\n+}\n+subsys_initcall(rpi_firmware_init);\n+\n+static void __init rpi_firmware_exit(void)\n+{\n+\tplatform_driver_unregister(&rpi_firmware_driver);\n+}\n+module_exit(rpi_firmware_exit);\n \n MODULE_AUTHOR(\"Eric Anholt <eric@anholt.net>\");\n MODULE_DESCRIPTION(\"Raspberry Pi firmware driver\");\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0054-BCM2708-Add-core-Device-Tree-support.patch",
    "content": "From 81589b5e28022d0a4738981f9e5ffb9fadcfaa5b Mon Sep 17 00:00:00 2001\nFrom: notro <notro@tronnes.org>\nDate: Wed, 9 Jul 2014 14:46:08 +0200\nSubject: [PATCH] BCM2708: Add core Device Tree support\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nAdd the bare minimum needed to boot BCM2708 from a Device Tree.\n\nSigned-off-by: Noralf Tronnes <notro@tronnes.org>\n\nBCM2708: DT: change 'axi' nodename to 'soc'\n\nChange DT node named 'axi' to 'soc' so it matches ARCH_BCM2835.\nThe VC4 bootloader fills in certain properties in the 'axi' subtree,\nbut since this is part of an upstreaming effort, the name is changed.\n\nSigned-off-by: Noralf Tronnes notro@tronnes.org\n\nBCM2708_DT: Correct length of the peripheral space\n\nUse dts-dirs feature for overlays.\n\nThe kernel makefiles have a dts-dirs target that is for vendor subdirectories.\n\nUsing this fixes the install_dtbs target, which previously did not install the overlays.\n\nBCM270X_DT: configure I2S DMA channels\n\nSigned-off-by: Matthias Reichl <hias@horus.com>\n\nBCM270X_DT: switch to bcm2835-i2s\n\nI2S soundcard drivers with proper devicetree support (i.e. not linking\nto the cpu_dai/platform via name but to cpu/platform via of_node)\nwill work out of the box without any modifications.\n\nWhen the kernel is compiled without devicetree support the platform\ncode will instantiate the bcm2708-i2s driver and I2S soundcard drivers\nwill link to it via name, as before.\n\nSigned-off-by: Matthias Reichl <hias@horus.com>\n\nSDIO-overlay: add poll_once-boolean parameter\n\nAdd paramter to toggle sdio-device-polling\ndone every second or once at boot-time.\n\nSigned-off-by: Patrick Boettcher <patrick.boettcher@posteo.de>\n\nBCM270X_DT: Make mmc overlay compatible with current firmware\n\nThe original DT overlay logic followed a merge-then-patch procedure,\ni.e. parameters are applied to the loaded overlay before the overlay\nis merged into the base DTB. This sequence has been changed to\npatch-then-merge, in order to support parameterised node names, and\nto protect against bad overlays. As a result, overrides (parameters)\nmust only target labels in the overlay, but the overlay can obviously target nodes in the base DTB.\n\nmmc-overlay.dts (that switches back to the original mmc sdcard\ndriver) is the only overlay violating that rule, and this patch\nfixes it.\n\nbcm270x_dt: Use the sdhost MMC controller by default\n\nThe \"mmc\" overlay reverts to using the other controller.\n\nsquash: Add cprman to dt\n\nBCM270X_DT: Use clk_core for I2C interfaces\n\nBCM270X_DT: Use bcm283x.dtsi, bcm2835.dtsi and bcm2836.dtsi\n\nThe mainline Device Tree files are quite close to downstream now.\nLet's use bcm283x.dtsi, bcm2835.dtsi and bcm2836.dtsi as base files\nfor our dts files.\n\nMainline dts files are based on these files:\n\n          bcm2835-rpi.dtsi\n  bcm2835.dtsi    bcm2836.dtsi\n          bcm283x.dtsi\n\nCurrent downstream are based on these:\n\n  bcm2708.dtsi    bcm2709.dtsi    bcm2710.dtsi\n             bcm2708_common.dtsi\n\nThis patch introduces this dependency:\n\n  bcm2708.dtsi    bcm2709.dtsi\n          bcm2708-rpi.dtsi\n          bcm270x.dtsi\n  bcm2835.dtsi    bcm2836.dtsi\n          bcm283x.dtsi\n\nAnd:\n          bcm2710.dtsi\n          bcm2708-rpi.dtsi\n          bcm270x.dtsi\n          bcm283x.dtsi\n\nbcm270x.dtsi contains the downstream bcm283x.dtsi diff.\nbcm2708-rpi.dtsi is the downstream version of bcm2835-rpi.dtsi.\n\nOther changes:\n- The led node has moved from /soc/leds to /leds. This is not a problem\n  since the label is used to reference it.\n- The clk_osc reg property changes from 6 to 3.\n- The gpu nodes has their interrupt property set in the base file.\n- the clocks label does not point to the /clocks node anymore, but\n  points to the cprman node. This is not a problem since the overlays\n  that use the clock node refer to it directly: target-path = \"/clocks\";\n- some nodes now have 2 labels since mainline and downstream differs in\n  this respect: cprman/clocks, spi0/spi, gpu/vc4.\n- some nodes doesn't have an explicit status = \"okay\" since they're not\n  disabled in the base file: watchdog and random.\n- gpiomem doesn't need an explicit status = \"okay\".\n- bcm2708-rpi-cm.dts got the hpd-gpios property from bcm2708_common.dtsi,\n  it's now set directly in that file.\n- bcm2709-rpi-2-b.dts has the timer node moved from /soc/timer to /timer.\n- Removed clock-frequency property on the bcm{2709,2710}.dtsi timer nodes.\n\nSigned-off-by: Noralf Trønnes <noralf@tronnes.org>\n\nBCM270X_DT: Use raspberrypi-power to turn on USB power\n\nUse the raspberrypi-power driver to turn on USB power.\n\nSigned-off-by: Noralf Trønnes <noralf@tronnes.org>\n\nBCM270X_DT: Add a .dtbo target, use for overlays\n\nChange the filenames and extensions to keep the pre-DDT style of\noverlay (<name>-overlay.dtb) distinct from new ones that use a\ndifferent style of local fixups (<name>.dtbo), and to match other\nplatforms.\n\nThe RPi firmware uses the DDTK trailer atom to choose which type of\noverlay to use for each kernel.\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.org>\n\nBCM270X_DT: Don't generate \"linux,phandle\" props\n\nThe EPAPR standard says to use \"phandle\" properties to store phandles,\nrather than the deprecated \"linux,phandle\" version. By default, dtc\ngenerates both, but adding \"-H epapr\" causes it to only generate\n\"phandle\"s, saving some space and clutter.\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.org>\n\nBCM270X_DT: Add overlay for enc28j60 on SPI2\n\nWorks on SPI2 for compute module\n\nBCM270X_DT: Add midi-uart0 overlay\n\nMIDI requires 31.25kbaud, a baudrate unsupported by Linux. The\nmidi-uart0 overlay configures uart0 (ttyAMA0) to use a fake clock\nso that requesting 38.4kbaud actually gets 31.25kbaud.\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.org>\n\nBCM270X_DT: Add i2c-sensor overlay\n\nThe i2c-sensor overlay is a container for various pressure and\ntemperature sensors, currently bmp085 and bmp280. The standalone\nbmp085_i2c-sensor overlay is now deprecated.\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.org>\n\nBCM270X_DT: overlays/*-overlay.dtb -> overlays/*.dtbo (#1752)\n\nWe now create overlays as .dtbo files.\n\nbuild: support for .dtbo files for dtb overlays\n\nKernel 4.4.6+ on RaspberryPi support .dtbo files for overlays, instead of .dtb.\nPatch the kernel, which has faulty rules to generate .dtbo the way yocto does\n\nSigned-off-by: Herve Jourdain <herve.jourdain@neuf.fr>\nSigned-off-by: Khem Raj <raj.khem@gmail.com>\n\nBCM270X: Drop position requirement for CMA in VC4 overlay.\n\nNo longer necessary since 2aefcd576195a739a7a256099571c9c4a401005f,\nand will probably let peeople that want to choose a larger CMA\nallocation (particularly on pi0/1).\n\nSigned-off-by: Eric Anholt <eric@anholt.net>\n\nBCM270X_DT: RPi Device Tree tidy\n\nUse the upstream sdhost node, add thermal-zones, and factor out some\ncommon elements.\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.org>\n\nkbuild: Silence unhelpful DTC warnings\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.org>\n\nBCM270X_DT: DT build rules no longer arch-specific\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.org>\n---\n .gitignore                                    |    1 +\n arch/arm/boot/dts/Makefile                    |   27 +-\n arch/arm/boot/dts/bcm2708-rpi-b-plus.dts      |  124 +\n arch/arm/boot/dts/bcm2708-rpi-b-rev1.dts      |  127 +\n arch/arm/boot/dts/bcm2708-rpi-b.dts           |  114 +\n arch/arm/boot/dts/bcm2708-rpi-bt.dtsi         |   26 +\n arch/arm/boot/dts/bcm2708-rpi-cm.dts          |   97 +\n arch/arm/boot/dts/bcm2708-rpi-cm.dtsi         |   18 +\n arch/arm/boot/dts/bcm2708-rpi-zero-w.dts      |  163 +\n arch/arm/boot/dts/bcm2708-rpi-zero.dts        |  117 +\n arch/arm/boot/dts/bcm2708-rpi.dtsi            |   36 +\n arch/arm/boot/dts/bcm2708.dtsi                |   12 +\n arch/arm/boot/dts/bcm2709-rpi-2-b.dts         |  124 +\n arch/arm/boot/dts/bcm2709-rpi.dtsi            |    5 +\n arch/arm/boot/dts/bcm2709.dtsi                |   22 +\n arch/arm/boot/dts/bcm270x-rpi.dtsi            |  154 +\n arch/arm/boot/dts/bcm270x.dtsi                |  197 ++\n arch/arm/boot/dts/bcm2710-rpi-2-b.dts         |  124 +\n arch/arm/boot/dts/bcm2710-rpi-3-b-plus.dts    |  196 ++\n arch/arm/boot/dts/bcm2710-rpi-3-b.dts         |  198 ++\n arch/arm/boot/dts/bcm2710-rpi-cm3.dts         |  133 +\n arch/arm/boot/dts/bcm2710.dtsi                |   29 +\n arch/arm/boot/dts/bcm2711-rpi-4-b.dts         |  306 +-\n arch/arm/boot/dts/bcm2711-rpi-cm4.dts         |  609 ++++\n arch/arm/boot/dts/bcm2711-rpi.dtsi            |  201 ++\n arch/arm/boot/dts/bcm2711.dtsi                |   34 +-\n arch/arm/boot/dts/bcm271x-rpi-bt.dtsi         |   26 +\n arch/arm/boot/dts/bcm2835-common.dtsi         |    4 +-\n arch/arm/boot/dts/bcm2835-rpi-a-plus.dts      |    5 +\n arch/arm/boot/dts/bcm2835-rpi-a.dts           |    7 +\n arch/arm/boot/dts/bcm2835-rpi-b-plus.dts      |    5 +\n arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts      |    7 +\n arch/arm/boot/dts/bcm2835-rpi-b.dts           |    7 +\n arch/arm/boot/dts/bcm2835-rpi-cm1-io1.dts     |    5 +\n arch/arm/boot/dts/bcm2835-rpi-zero-w.dts      |    5 +\n arch/arm/boot/dts/bcm2835-rpi-zero.dts        |    5 +\n arch/arm/boot/dts/bcm2835-rpi.dtsi            |   15 +-\n arch/arm/boot/dts/bcm2835.dtsi                |    2 +-\n arch/arm/boot/dts/bcm2836-rpi-2-b.dts         |    5 +\n arch/arm/boot/dts/bcm2837-rpi-3-a-plus.dts    |    5 +\n arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts    |    5 +\n arch/arm/boot/dts/bcm2837-rpi-3-b.dts         |    5 +\n arch/arm/boot/dts/bcm2837-rpi-cm3-io3.dts     |    5 +\n arch/arm/boot/dts/bcm283x-rpi-csi0-2lane.dtsi |    4 +\n arch/arm/boot/dts/bcm283x-rpi-csi1-2lane.dtsi |    4 +\n arch/arm/boot/dts/bcm283x-rpi-csi1-4lane.dtsi |    4 +\n .../boot/dts/bcm283x-rpi-i2c0mux_0_28.dtsi    |    4 +\n .../boot/dts/bcm283x-rpi-i2c0mux_0_44.dtsi    |    4 +\n .../boot/dts/bcm283x-rpi-usb-peripheral.dtsi  |    7 -\n arch/arm/boot/dts/bcm283x.dtsi                |   26 +-\n arch/arm/boot/dts/overlays/Makefile           |  216 ++\n arch/arm/boot/dts/overlays/README             | 3040 +++++++++++++++++\n .../arm/boot/dts/overlays/act-led-overlay.dts |   27 +\n .../boot/dts/overlays/adafruit18-overlay.dts  |   55 +\n .../dts/overlays/adau1977-adc-overlay.dts     |   40 +\n .../dts/overlays/adau7002-simple-overlay.dts  |   52 +\n .../arm/boot/dts/overlays/ads1015-overlay.dts |   98 +\n .../arm/boot/dts/overlays/ads1115-overlay.dts |  103 +\n .../arm/boot/dts/overlays/ads7846-overlay.dts |   89 +\n .../boot/dts/overlays/adv7282m-overlay.dts    |   65 +\n .../boot/dts/overlays/adv728x-m-overlay.dts   |   37 +\n .../overlays/akkordion-iqdacplus-overlay.dts  |   49 +\n .../allo-boss-dac-pcm512x-audio-overlay.dts   |   59 +\n .../dts/overlays/allo-digione-overlay.dts     |   44 +\n .../allo-katana-dac-audio-overlay.dts         |   57 +\n .../allo-piano-dac-pcm512x-audio-overlay.dts  |   54 +\n ...o-piano-dac-plus-pcm512x-audio-overlay.dts |   55 +\n arch/arm/boot/dts/overlays/anyspi-overlay.dts |  205 ++\n .../boot/dts/overlays/apds9960-overlay.dts    |   57 +\n .../boot/dts/overlays/applepi-dac-overlay.dts |   57 +\n .../boot/dts/overlays/at86rf233-overlay.dts   |   57 +\n .../overlays/audioinjector-addons-overlay.dts |   60 +\n ...dioinjector-isolated-soundcard-overlay.dts |   55 +\n .../overlays/audioinjector-ultra-overlay.dts  |   71 +\n .../audioinjector-wm8731-audio-overlay.dts    |   39 +\n .../dts/overlays/audiosense-pi-overlay.dts    |   82 +\n .../boot/dts/overlays/audremap-overlay.dts    |   35 +\n .../boot/dts/overlays/balena-fin-overlay.dts  |  125 +\n arch/arm/boot/dts/overlays/cma-overlay.dts    |   36 +\n arch/arm/boot/dts/overlays/dht11-overlay.dts  |   41 +\n .../dts/overlays/dionaudio-loco-overlay.dts   |   39 +\n .../overlays/dionaudio-loco-v2-overlay.dts    |   49 +\n .../boot/dts/overlays/disable-bt-overlay.dts  |   64 +\n .../dts/overlays/disable-wifi-overlay.dts     |   20 +\n arch/arm/boot/dts/overlays/dpi18-overlay.dts  |   39 +\n arch/arm/boot/dts/overlays/dpi24-overlay.dts  |   39 +\n arch/arm/boot/dts/overlays/draws-overlay.dts  |  208 ++\n .../arm/boot/dts/overlays/dwc-otg-overlay.dts |   14 +\n arch/arm/boot/dts/overlays/dwc2-overlay.dts   |   26 +\n .../boot/dts/overlays/enc28j60-overlay.dts    |   53 +\n .../dts/overlays/enc28j60-spi2-overlay.dts    |   47 +\n .../arm/boot/dts/overlays/exc3000-overlay.dts |   48 +\n .../boot/dts/overlays/fe-pi-audio-overlay.dts |   70 +\n .../boot/dts/overlays/fsm-demo-overlay.dts    |  104 +\n .../boot/dts/overlays/ghost-amp-overlay.dts   |  119 +\n arch/arm/boot/dts/overlays/goodix-overlay.dts |   46 +\n .../googlevoicehat-soundcard-overlay.dts      |   49 +\n .../boot/dts/overlays/gpio-fan-overlay.dts    |   79 +\n .../arm/boot/dts/overlays/gpio-ir-overlay.dts |   49 +\n .../boot/dts/overlays/gpio-ir-tx-overlay.dts  |   36 +\n .../boot/dts/overlays/gpio-key-overlay.dts    |   48 +\n .../overlays/gpio-no-bank0-irq-overlay.dts    |   14 +\n .../boot/dts/overlays/gpio-no-irq-overlay.dts |   14 +\n .../dts/overlays/gpio-poweroff-overlay.dts    |   37 +\n .../dts/overlays/gpio-shutdown-overlay.dts    |   84 +\n .../boot/dts/overlays/hd44780-lcd-overlay.dts |   46 +\n .../hdmi-backlight-hwhack-gpio-overlay.dts    |   47 +\n .../dts/overlays/hifiberry-amp-overlay.dts    |   39 +\n .../dts/overlays/hifiberry-dac-overlay.dts    |   34 +\n .../overlays/hifiberry-dacplus-overlay.dts    |   65 +\n .../overlays/hifiberry-dacplusadc-overlay.dts |   72 +\n .../hifiberry-dacplusadcpro-overlay.dts       |   65 +\n .../overlays/hifiberry-dacplusdsp-overlay.dts |   34 +\n .../overlays/hifiberry-dacplushd-overlay.dts  |  106 +\n .../dts/overlays/hifiberry-digi-overlay.dts   |   41 +\n .../overlays/hifiberry-digi-pro-overlay.dts   |   43 +\n .../boot/dts/overlays/highperi-overlay.dts    |   63 +\n arch/arm/boot/dts/overlays/hy28a-overlay.dts  |   93 +\n .../boot/dts/overlays/hy28b-2017-overlay.dts  |  152 +\n arch/arm/boot/dts/overlays/hy28b-overlay.dts  |  148 +\n .../boot/dts/overlays/i-sabre-q2m-overlay.dts |   39 +\n .../boot/dts/overlays/i2c-bcm2708-overlay.dts |   13 +\n .../boot/dts/overlays/i2c-gpio-overlay.dts    |   47 +\n .../arm/boot/dts/overlays/i2c-mux-overlay.dts |  139 +\n .../dts/overlays/i2c-pwm-pca9685a-overlay.dts |   26 +\n .../dts/overlays/i2c-rtc-gpio-overlay.dts     |  266 ++\n .../arm/boot/dts/overlays/i2c-rtc-overlay.dts |  278 ++\n .../boot/dts/overlays/i2c-sensor-overlay.dts  |  271 ++\n arch/arm/boot/dts/overlays/i2c0-overlay.dts   |   74 +\n arch/arm/boot/dts/overlays/i2c1-overlay.dts   |   44 +\n arch/arm/boot/dts/overlays/i2c3-overlay.dts   |   36 +\n arch/arm/boot/dts/overlays/i2c4-overlay.dts   |   36 +\n arch/arm/boot/dts/overlays/i2c5-overlay.dts   |   36 +\n arch/arm/boot/dts/overlays/i2c6-overlay.dts   |   36 +\n .../dts/overlays/i2s-gpio28-31-overlay.dts    |   18 +\n .../boot/dts/overlays/ilitek251x-overlay.dts  |   45 +\n arch/arm/boot/dts/overlays/imx219-overlay.dts |  119 +\n arch/arm/boot/dts/overlays/imx290-overlay.dts |   32 +\n .../boot/dts/overlays/imx290_327-overlay.dtsi |  145 +\n arch/arm/boot/dts/overlays/imx477-overlay.dts |  119 +\n .../dts/overlays/iqaudio-codec-overlay.dts    |   42 +\n .../boot/dts/overlays/iqaudio-dac-overlay.dts |   46 +\n .../dts/overlays/iqaudio-dacplus-overlay.dts  |   49 +\n .../iqaudio-digi-wm8804-audio-overlay.dts     |   47 +\n .../arm/boot/dts/overlays/irs1125-overlay.dts |   85 +\n .../dts/overlays/jedec-spi-nor-overlay.dts    |  309 ++\n .../dts/overlays/justboom-both-overlay.dts    |   65 +\n .../dts/overlays/justboom-dac-overlay.dts     |   46 +\n .../dts/overlays/justboom-digi-overlay.dts    |   41 +\n .../arm/boot/dts/overlays/ltc294x-overlay.dts |   86 +\n .../boot/dts/overlays/max98357a-overlay.dts   |   84 +\n .../boot/dts/overlays/maxtherm-overlay.dts    |  166 +\n .../boot/dts/overlays/mbed-dac-overlay.dts    |   64 +\n .../boot/dts/overlays/mcp23017-overlay.dts    |   69 +\n .../boot/dts/overlays/mcp23s17-overlay.dts    |  732 ++++\n .../dts/overlays/mcp2515-can0-overlay.dts     |   73 +\n .../dts/overlays/mcp2515-can1-overlay.dts     |   73 +\n .../arm/boot/dts/overlays/mcp3008-overlay.dts |  205 ++\n .../arm/boot/dts/overlays/mcp3202-overlay.dts |  205 ++\n .../arm/boot/dts/overlays/mcp342x-overlay.dts |  164 +\n .../dts/overlays/media-center-overlay.dts     |  134 +\n .../boot/dts/overlays/merus-amp-overlay.dts   |   60 +\n .../boot/dts/overlays/midi-uart0-overlay.dts  |   36 +\n .../boot/dts/overlays/midi-uart1-overlay.dts  |   43 +\n .../boot/dts/overlays/miniuart-bt-overlay.dts |   93 +\n arch/arm/boot/dts/overlays/mmc-overlay.dts    |   46 +\n .../arm/boot/dts/overlays/mpu6050-overlay.dts |   28 +\n .../arm/boot/dts/overlays/mz61581-overlay.dts |  117 +\n arch/arm/boot/dts/overlays/ov5647-overlay.dts |   92 +\n arch/arm/boot/dts/overlays/ov7251-overlay.dts |  111 +\n arch/arm/boot/dts/overlays/ov9281-overlay.dts |  111 +\n arch/arm/boot/dts/overlays/overlay_map.dts    |  141 +\n .../arm/boot/dts/overlays/papirus-overlay.dts |   89 +\n .../arm/boot/dts/overlays/pca953x-overlay.dts |  240 ++\n arch/arm/boot/dts/overlays/pibell-overlay.dts |   81 +\n .../dts/overlays/pifacedigital-overlay.dts    |  144 +\n arch/arm/boot/dts/overlays/piglow-overlay.dts |   97 +\n .../boot/dts/overlays/piscreen-overlay.dts    |  102 +\n .../boot/dts/overlays/piscreen2r-overlay.dts  |  106 +\n .../arm/boot/dts/overlays/pisound-overlay.dts |  120 +\n .../arm/boot/dts/overlays/pitft22-overlay.dts |   69 +\n .../overlays/pitft28-capacitive-overlay.dts   |   91 +\n .../overlays/pitft28-resistive-overlay.dts    |  119 +\n .../overlays/pitft35-resistive-overlay.dts    |  119 +\n .../boot/dts/overlays/pps-gpio-overlay.dts    |   38 +\n .../boot/dts/overlays/pwm-2chan-overlay.dts   |   49 +\n .../boot/dts/overlays/pwm-ir-tx-overlay.dts   |   40 +\n arch/arm/boot/dts/overlays/pwm-overlay.dts    |   45 +\n .../arm/boot/dts/overlays/qca7000-overlay.dts |   55 +\n .../dts/overlays/rotary-encoder-overlay.dts   |   59 +\n .../dts/overlays/rpi-backlight-overlay.dts    |   21 +\n .../overlays/rpi-cirrus-wm5102-overlay.dts    |  172 +\n .../arm/boot/dts/overlays/rpi-dac-overlay.dts |   34 +\n .../boot/dts/overlays/rpi-display-overlay.dts |   91 +\n .../boot/dts/overlays/rpi-ft5406-overlay.dts  |   25 +\n .../arm/boot/dts/overlays/rpi-poe-overlay.dts |   95 +\n .../boot/dts/overlays/rpi-proto-overlay.dts   |   39 +\n .../boot/dts/overlays/rpi-sense-overlay.dts   |   47 +\n arch/arm/boot/dts/overlays/rpi-tv-overlay.dts |   34 +\n .../boot/dts/overlays/rpivid-v4l2-overlay.dts |   61 +\n .../rra-digidac1-wm8741-audio-overlay.dts     |   49 +\n .../boot/dts/overlays/sainsmart18-overlay.dts |   52 +\n .../dts/overlays/sc16is750-i2c-overlay.dts    |   43 +\n .../dts/overlays/sc16is752-i2c-overlay.dts    |   43 +\n .../dts/overlays/sc16is752-spi0-overlay.dts   |   49 +\n .../dts/overlays/sc16is752-spi1-overlay.dts   |   67 +\n arch/arm/boot/dts/overlays/sdhost-overlay.dts |   38 +\n arch/arm/boot/dts/overlays/sdio-overlay.dts   |   77 +\n .../arm/boot/dts/overlays/sdtweak-overlay.dts |   25 +\n .../boot/dts/overlays/sh1106-spi-overlay.dts  |   84 +\n .../arm/boot/dts/overlays/smi-dev-overlay.dts |   20 +\n .../boot/dts/overlays/smi-nand-overlay.dts    |   66 +\n arch/arm/boot/dts/overlays/smi-overlay.dts    |   37 +\n .../dts/overlays/spi-gpio35-39-overlay.dts    |   31 +\n .../dts/overlays/spi-gpio40-45-overlay.dts    |   36 +\n .../arm/boot/dts/overlays/spi-rtc-overlay.dts |   33 +\n .../boot/dts/overlays/spi0-1cs-overlay.dts    |   42 +\n .../boot/dts/overlays/spi0-2cs-overlay.dts    |   37 +\n .../boot/dts/overlays/spi1-1cs-overlay.dts    |   57 +\n .../boot/dts/overlays/spi1-2cs-overlay.dts    |   69 +\n .../boot/dts/overlays/spi1-3cs-overlay.dts    |   81 +\n .../boot/dts/overlays/spi2-1cs-overlay.dts    |   57 +\n .../boot/dts/overlays/spi2-2cs-overlay.dts    |   69 +\n .../boot/dts/overlays/spi2-3cs-overlay.dts    |   81 +\n .../boot/dts/overlays/spi3-1cs-overlay.dts    |   44 +\n .../boot/dts/overlays/spi3-2cs-overlay.dts    |   56 +\n .../boot/dts/overlays/spi4-1cs-overlay.dts    |   44 +\n .../boot/dts/overlays/spi4-2cs-overlay.dts    |   56 +\n .../boot/dts/overlays/spi5-1cs-overlay.dts    |   44 +\n .../boot/dts/overlays/spi5-2cs-overlay.dts    |   56 +\n .../boot/dts/overlays/spi6-1cs-overlay.dts    |   44 +\n .../boot/dts/overlays/spi6-2cs-overlay.dts    |   56 +\n .../arm/boot/dts/overlays/ssd1306-overlay.dts |   36 +\n .../boot/dts/overlays/ssd1306-spi-overlay.dts |   84 +\n .../boot/dts/overlays/ssd1351-spi-overlay.dts |   83 +\n .../dts/overlays/superaudioboard-overlay.dts  |   73 +\n arch/arm/boot/dts/overlays/sx150x-overlay.dts | 1706 +++++++++\n .../dts/overlays/tc358743-audio-overlay.dts   |   52 +\n .../boot/dts/overlays/tc358743-overlay.dts    |  107 +\n .../boot/dts/overlays/tinylcd35-overlay.dts   |  222 ++\n .../boot/dts/overlays/tpm-slb9670-overlay.dts |   44 +\n arch/arm/boot/dts/overlays/uart0-overlay.dts  |   32 +\n arch/arm/boot/dts/overlays/uart1-overlay.dts  |   38 +\n arch/arm/boot/dts/overlays/uart2-overlay.dts  |   27 +\n arch/arm/boot/dts/overlays/uart3-overlay.dts  |   27 +\n arch/arm/boot/dts/overlays/uart4-overlay.dts  |   27 +\n arch/arm/boot/dts/overlays/uart5-overlay.dts  |   27 +\n arch/arm/boot/dts/overlays/udrc-overlay.dts   |  128 +\n .../boot/dts/overlays/upstream-overlay.dts    |  113 +\n .../dts/overlays/upstream-pi4-overlay.dts     |  161 +\n .../dts/overlays/vc4-fkms-v3d-overlay.dts     |   40 +\n .../overlays/vc4-kms-kippah-7inch-overlay.dts |   43 +\n .../boot/dts/overlays/vc4-kms-v3d-overlay.dts |  122 +\n .../dts/overlays/vc4-kms-v3d-pi4-overlay.dts  |  186 +\n arch/arm/boot/dts/overlays/vga666-overlay.dts |   30 +\n .../arm/boot/dts/overlays/w1-gpio-overlay.dts |   40 +\n .../dts/overlays/w1-gpio-pullup-overlay.dts   |   42 +\n arch/arm/boot/dts/overlays/w5500-overlay.dts  |   63 +\n .../arm/boot/dts/overlays/wittypi-overlay.dts |   44 +\n arch/arm64/boot/dts/Makefile                  |    2 +\n arch/arm64/boot/dts/broadcom/Makefile         |   16 +-\n .../boot/dts/broadcom/bcm2710-rpi-2-b.dts     |    3 +\n .../dts/broadcom/bcm2710-rpi-3-b-plus.dts     |    3 +\n .../boot/dts/broadcom/bcm2710-rpi-3-b.dts     |    3 +\n .../boot/dts/broadcom/bcm2710-rpi-cm3.dts     |    3 +\n .../boot/dts/broadcom/bcm2711-rpi-4-b.dts     |    5 +-\n .../dts/broadcom/bcm283x-rpi-csi1-2lane.dtsi  |    1 +\n .../dts/broadcom/bcm283x-rpi-lan7515.dtsi     |    1 +\n arch/arm64/boot/dts/overlays                  |    1 +\n scripts/Makefile.dtbinst                      |    6 +-\n scripts/Makefile.lib                          |   13 +\n 271 files changed, 23898 insertions(+), 31 deletions(-)\n create mode 100644 arch/arm/boot/dts/bcm2708-rpi-b-plus.dts\n create mode 100644 arch/arm/boot/dts/bcm2708-rpi-b-rev1.dts\n create mode 100644 arch/arm/boot/dts/bcm2708-rpi-b.dts\n create mode 100644 arch/arm/boot/dts/bcm2708-rpi-bt.dtsi\n create mode 100644 arch/arm/boot/dts/bcm2708-rpi-cm.dts\n create mode 100644 arch/arm/boot/dts/bcm2708-rpi-cm.dtsi\n create mode 100644 arch/arm/boot/dts/bcm2708-rpi-zero-w.dts\n create mode 100644 arch/arm/boot/dts/bcm2708-rpi-zero.dts\n create mode 100644 arch/arm/boot/dts/bcm2708-rpi.dtsi\n create mode 100644 arch/arm/boot/dts/bcm2708.dtsi\n create mode 100644 arch/arm/boot/dts/bcm2709-rpi-2-b.dts\n create mode 100644 arch/arm/boot/dts/bcm2709-rpi.dtsi\n create mode 100644 arch/arm/boot/dts/bcm2709.dtsi\n create mode 100644 arch/arm/boot/dts/bcm270x-rpi.dtsi\n create mode 100644 arch/arm/boot/dts/bcm270x.dtsi\n create mode 100644 arch/arm/boot/dts/bcm2710-rpi-2-b.dts\n create mode 100644 arch/arm/boot/dts/bcm2710-rpi-3-b-plus.dts\n create mode 100644 arch/arm/boot/dts/bcm2710-rpi-3-b.dts\n create mode 100644 arch/arm/boot/dts/bcm2710-rpi-cm3.dts\n create mode 100644 arch/arm/boot/dts/bcm2710.dtsi\n create mode 100644 arch/arm/boot/dts/bcm2711-rpi-cm4.dts\n create mode 100644 arch/arm/boot/dts/bcm2711-rpi.dtsi\n create mode 100644 arch/arm/boot/dts/bcm271x-rpi-bt.dtsi\n create mode 100644 arch/arm/boot/dts/bcm283x-rpi-csi0-2lane.dtsi\n create mode 100644 arch/arm/boot/dts/bcm283x-rpi-csi1-2lane.dtsi\n create mode 100644 arch/arm/boot/dts/bcm283x-rpi-csi1-4lane.dtsi\n create mode 100644 arch/arm/boot/dts/bcm283x-rpi-i2c0mux_0_28.dtsi\n create mode 100644 arch/arm/boot/dts/bcm283x-rpi-i2c0mux_0_44.dtsi\n delete mode 100644 arch/arm/boot/dts/bcm283x-rpi-usb-peripheral.dtsi\n create mode 100644 arch/arm/boot/dts/overlays/Makefile\n create mode 100644 arch/arm/boot/dts/overlays/README\n create mode 100644 arch/arm/boot/dts/overlays/act-led-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/adafruit18-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/adau1977-adc-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/adau7002-simple-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/ads1015-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/ads1115-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/ads7846-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/adv7282m-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/adv728x-m-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/akkordion-iqdacplus-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/allo-boss-dac-pcm512x-audio-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/allo-digione-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/allo-katana-dac-audio-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/allo-piano-dac-pcm512x-audio-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/allo-piano-dac-plus-pcm512x-audio-overlay.dts\n create mode 100755 arch/arm/boot/dts/overlays/anyspi-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/apds9960-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/applepi-dac-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/at86rf233-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/audioinjector-addons-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/audioinjector-isolated-soundcard-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/audioinjector-ultra-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/audioinjector-wm8731-audio-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/audiosense-pi-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/audremap-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/balena-fin-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/cma-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/dht11-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/dionaudio-loco-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/dionaudio-loco-v2-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/disable-bt-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/disable-wifi-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/dpi18-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/dpi24-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/draws-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/dwc-otg-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/dwc2-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/enc28j60-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/enc28j60-spi2-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/exc3000-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/fe-pi-audio-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/fsm-demo-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/ghost-amp-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/goodix-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/googlevoicehat-soundcard-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/gpio-fan-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/gpio-ir-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/gpio-ir-tx-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/gpio-key-overlay.dts\n create mode 100755 arch/arm/boot/dts/overlays/gpio-no-bank0-irq-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/gpio-no-irq-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/gpio-poweroff-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/gpio-shutdown-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/hd44780-lcd-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/hdmi-backlight-hwhack-gpio-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/hifiberry-amp-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/hifiberry-dac-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/hifiberry-dacplus-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/hifiberry-dacplusadc-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/hifiberry-dacplusadcpro-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/hifiberry-dacplusdsp-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/hifiberry-dacplushd-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/hifiberry-digi-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/hifiberry-digi-pro-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/highperi-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/hy28a-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/hy28b-2017-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/hy28b-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/i-sabre-q2m-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/i2c-bcm2708-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/i2c-gpio-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/i2c-mux-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/i2c-pwm-pca9685a-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/i2c-rtc-gpio-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/i2c-rtc-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/i2c-sensor-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/i2c0-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/i2c1-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/i2c3-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/i2c4-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/i2c5-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/i2c6-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/i2s-gpio28-31-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/ilitek251x-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/imx219-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/imx290-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/imx290_327-overlay.dtsi\n create mode 100644 arch/arm/boot/dts/overlays/imx477-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/iqaudio-codec-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/iqaudio-dac-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/iqaudio-dacplus-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/iqaudio-digi-wm8804-audio-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/irs1125-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/jedec-spi-nor-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/justboom-both-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/justboom-dac-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/justboom-digi-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/ltc294x-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/max98357a-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/maxtherm-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/mbed-dac-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/mcp23017-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/mcp23s17-overlay.dts\n create mode 100755 arch/arm/boot/dts/overlays/mcp2515-can0-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/mcp2515-can1-overlay.dts\n create mode 100755 arch/arm/boot/dts/overlays/mcp3008-overlay.dts\n create mode 100755 arch/arm/boot/dts/overlays/mcp3202-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/mcp342x-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/media-center-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/merus-amp-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/midi-uart0-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/midi-uart1-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/miniuart-bt-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/mmc-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/mpu6050-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/mz61581-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/ov5647-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/ov7251-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/ov9281-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/overlay_map.dts\n create mode 100644 arch/arm/boot/dts/overlays/papirus-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/pca953x-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/pibell-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/pifacedigital-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/piglow-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/piscreen-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/piscreen2r-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/pisound-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/pitft22-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/pitft28-capacitive-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/pitft28-resistive-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/pitft35-resistive-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/pps-gpio-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/pwm-2chan-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/pwm-ir-tx-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/pwm-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/qca7000-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/rotary-encoder-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/rpi-backlight-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/rpi-cirrus-wm5102-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/rpi-dac-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/rpi-display-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/rpi-ft5406-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/rpi-poe-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/rpi-proto-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/rpi-sense-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/rpi-tv-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/rpivid-v4l2-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/rra-digidac1-wm8741-audio-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/sainsmart18-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/sc16is750-i2c-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/sc16is752-i2c-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/sc16is752-spi0-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/sc16is752-spi1-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/sdhost-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/sdio-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/sdtweak-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/sh1106-spi-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/smi-dev-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/smi-nand-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/smi-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/spi-gpio35-39-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/spi-gpio40-45-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/spi-rtc-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/spi0-1cs-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/spi0-2cs-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/spi1-1cs-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/spi1-2cs-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/spi1-3cs-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/spi2-1cs-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/spi2-2cs-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/spi2-3cs-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/spi3-1cs-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/spi3-2cs-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/spi4-1cs-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/spi4-2cs-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/spi5-1cs-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/spi5-2cs-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/spi6-1cs-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/spi6-2cs-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/ssd1306-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/ssd1306-spi-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/ssd1351-spi-overlay.dts\n create mode 100755 arch/arm/boot/dts/overlays/superaudioboard-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/sx150x-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/tc358743-audio-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/tc358743-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/tinylcd35-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/tpm-slb9670-overlay.dts\n create mode 100755 arch/arm/boot/dts/overlays/uart0-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/uart1-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/uart2-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/uart3-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/uart4-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/uart5-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/udrc-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/upstream-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/upstream-pi4-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/vc4-fkms-v3d-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/vc4-kms-kippah-7inch-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/vc4-kms-v3d-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/vc4-kms-v3d-pi4-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/vga666-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/w1-gpio-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/w1-gpio-pullup-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/w5500-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/wittypi-overlay.dts\n create mode 100644 arch/arm64/boot/dts/broadcom/bcm2710-rpi-2-b.dts\n create mode 100644 arch/arm64/boot/dts/broadcom/bcm2710-rpi-3-b-plus.dts\n create mode 100644 arch/arm64/boot/dts/broadcom/bcm2710-rpi-3-b.dts\n create mode 100644 arch/arm64/boot/dts/broadcom/bcm2710-rpi-cm3.dts\n create mode 120000 arch/arm64/boot/dts/broadcom/bcm283x-rpi-csi1-2lane.dtsi\n create mode 120000 arch/arm64/boot/dts/broadcom/bcm283x-rpi-lan7515.dtsi\n create mode 120000 arch/arm64/boot/dts/overlays\n\ndiff --git a/.gitignore b/.gitignore\nindex 67d2f3503128..8b0b16eeca88 100644\n--- a/.gitignore\n+++ b/.gitignore\n@@ -18,6 +18,7 @@\n *.c.[012]*.*\n *.dt.yaml\n *.dtb\n+*.dtbo\n *.dtb.S\n *.dwo\n *.elf\ndiff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile\nindex ce66ffd5a1bb..87241fe26e10 100644\n--- a/arch/arm/boot/dts/Makefile\n+++ b/arch/arm/boot/dts/Makefile\n@@ -1,4 +1,20 @@\n # SPDX-License-Identifier: GPL-2.0\n+\n+dtb-$(CONFIG_ARCH_BCM2835) += \\\n+\tbcm2708-rpi-b.dtb \\\n+\tbcm2708-rpi-b-rev1.dtb \\\n+\tbcm2708-rpi-b-plus.dtb \\\n+\tbcm2708-rpi-cm.dtb \\\n+\tbcm2708-rpi-zero.dtb \\\n+\tbcm2708-rpi-zero-w.dtb \\\n+\tbcm2709-rpi-2-b.dtb \\\n+\tbcm2710-rpi-2-b.dtb \\\n+\tbcm2710-rpi-3-b.dtb \\\n+\tbcm2711-rpi-4-b.dtb \\\n+\tbcm2710-rpi-3-b-plus.dtb \\\n+\tbcm2710-rpi-cm3.dtb \\\n+\tbcm2711-rpi-cm4.dtb\n+\n dtb-$(CONFIG_ARCH_ALPINE) += \\\n \talpine-db.dtb\n dtb-$(CONFIG_MACH_ARTPEC6) += \\\n@@ -92,7 +108,6 @@ dtb-$(CONFIG_ARCH_BCM2835) += \\\n \tbcm2837-rpi-3-b.dtb \\\n \tbcm2837-rpi-3-b-plus.dtb \\\n \tbcm2837-rpi-cm3-io3.dtb \\\n-\tbcm2711-rpi-4-b.dtb \\\n \tbcm2835-rpi-zero.dtb \\\n \tbcm2835-rpi-zero-w.dtb\n dtb-$(CONFIG_ARCH_BCM_5301X) += \\\n@@ -1408,3 +1423,13 @@ dtb-$(CONFIG_ARCH_ASPEED) += \\\n \taspeed-bmc-opp-zaius.dtb \\\n \taspeed-bmc-portwell-neptune.dtb \\\n \taspeed-bmc-quanta-q71l.dtb\n+\n+targets += dtbs dtbs_install\n+targets += $(dtb-y)\n+\n+subdir-y\t:= overlays\n+\n+# Enable fixups to support overlays on BCM2835 platforms\n+ifeq ($(CONFIG_ARCH_BCM2835),y)\n+\tDTC_FLAGS ?= -@\n+endif\ndiff --git a/arch/arm/boot/dts/bcm2708-rpi-b-plus.dts b/arch/arm/boot/dts/bcm2708-rpi-b-plus.dts\nnew file mode 100644\nindex 000000000000..98581eec4bdc\n--- /dev/null\n+++ b/arch/arm/boot/dts/bcm2708-rpi-b-plus.dts\n@@ -0,0 +1,124 @@\n+/dts-v1/;\n+\n+#include \"bcm2708.dtsi\"\n+#include \"bcm2708-rpi.dtsi\"\n+#include \"bcm283x-rpi-smsc9514.dtsi\"\n+#include \"bcm283x-rpi-csi1-2lane.dtsi\"\n+#include \"bcm283x-rpi-i2c0mux_0_28.dtsi\"\n+\n+/ {\n+\tcompatible = \"raspberrypi,model-b-plus\", \"brcm,bcm2835\";\n+\tmodel = \"Raspberry Pi Model B+\";\n+};\n+\n+&gpio {\n+\tspi0_pins: spi0_pins {\n+\t\tbrcm,pins = <9 10 11>;\n+\t\tbrcm,function = <4>; /* alt0 */\n+\t};\n+\n+\tspi0_cs_pins: spi0_cs_pins {\n+\t\tbrcm,pins = <8 7>;\n+\t\tbrcm,function = <1>; /* output */\n+\t};\n+\n+\ti2c0_pins: i2c0 {\n+\t\tbrcm,pins = <0 1>;\n+\t\tbrcm,function = <4>;\n+\t};\n+\n+\ti2c1_pins: i2c1 {\n+\t\tbrcm,pins = <2 3>;\n+\t\tbrcm,function = <4>;\n+\t};\n+\n+\ti2s_pins: i2s {\n+\t\tbrcm,pins = <18 19 20 21>;\n+\t\tbrcm,function = <4>; /* alt0 */\n+\t};\n+\n+\taudio_pins: audio_pins {\n+\t\tbrcm,pins = <40 45>;\n+\t\tbrcm,function = <4>;\n+\t};\n+};\n+\n+&uart0 {\n+\tstatus = \"okay\";\n+};\n+\n+&spi0 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&spi0_pins &spi0_cs_pins>;\n+\tcs-gpios = <&gpio 8 1>, <&gpio 7 1>;\n+\n+\tspidev0: spidev@0{\n+\t\tcompatible = \"spidev\";\n+\t\treg = <0>;\t/* CE0 */\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\tspi-max-frequency = <125000000>;\n+\t};\n+\n+\tspidev1: spidev@1{\n+\t\tcompatible = \"spidev\";\n+\t\treg = <1>;\t/* CE1 */\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\tspi-max-frequency = <125000000>;\n+\t};\n+};\n+\n+&i2c0if {\n+\tclock-frequency = <100000>;\n+};\n+\n+&i2c1 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&i2c1_pins>;\n+\tclock-frequency = <100000>;\n+};\n+\n+&i2c2 {\n+\tclock-frequency = <100000>;\n+};\n+\n+&i2s {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&i2s_pins>;\n+};\n+\n+&leds {\n+\tact_led: act {\n+\t\tlabel = \"led0\";\n+\t\tlinux,default-trigger = \"mmc0\";\n+\t\tgpios = <&gpio 47 0>;\n+\t};\n+\n+\tpwr_led: pwr {\n+\t\tlabel = \"led1\";\n+\t\tlinux,default-trigger = \"input\";\n+\t\tgpios = <&gpio 35 0>;\n+\t};\n+};\n+\n+&hdmi {\n+\thpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>;\n+};\n+\n+&audio {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&audio_pins>;\n+};\n+\n+/ {\n+\t__overrides__ {\n+\t\tact_led_gpio = <&act_led>,\"gpios:4\";\n+\t\tact_led_activelow = <&act_led>,\"gpios:8\";\n+\t\tact_led_trigger = <&act_led>,\"linux,default-trigger\";\n+\n+\t\tpwr_led_gpio = <&pwr_led>,\"gpios:4\";\n+\t\tpwr_led_activelow = <&pwr_led>,\"gpios:8\";\n+\t\tpwr_led_trigger = <&pwr_led>,\"linux,default-trigger\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/bcm2708-rpi-b-rev1.dts b/arch/arm/boot/dts/bcm2708-rpi-b-rev1.dts\nnew file mode 100644\nindex 000000000000..7b554b465b27\n--- /dev/null\n+++ b/arch/arm/boot/dts/bcm2708-rpi-b-rev1.dts\n@@ -0,0 +1,127 @@\n+/dts-v1/;\n+\n+#include \"bcm2708.dtsi\"\n+#include \"bcm2708-rpi.dtsi\"\n+#include \"bcm283x-rpi-smsc9512.dtsi\"\n+#include \"bcm283x-rpi-csi1-2lane.dtsi\"\n+\n+/ {\n+\tcompatible = \"raspberrypi,model-b\", \"brcm,bcm2835\";\n+\tmodel = \"Raspberry Pi Model B\";\n+};\n+\n+&gpio {\n+\tspi0_pins: spi0_pins {\n+\t\tbrcm,pins = <9 10 11>;\n+\t\tbrcm,function = <4>; /* alt0 */\n+\t};\n+\n+\tspi0_cs_pins: spi0_cs_pins {\n+\t\tbrcm,pins = <8 7>;\n+\t\tbrcm,function = <1>; /* output */\n+\t};\n+\n+\ti2c0_pins: i2c0 {\n+\t\tbrcm,pins = <0 1>;\n+\t\tbrcm,function = <4>;\n+\t};\n+\n+\ti2c1_pins: i2c1 {\n+\t\tbrcm,pins = <2 3>;\n+\t\tbrcm,function = <4>;\n+\t};\n+\n+\ti2s_pins: i2s {\n+\t\tbrcm,pins = <28 29 30 31>;\n+\t\tbrcm,function = <6>; /* alt2 */\n+\t};\n+\n+\taudio_pins: audio_pins {\n+\t\tbrcm,pins = <40 45>;\n+\t\tbrcm,function = <4>;\n+\t};\n+};\n+\n+&uart0 {\n+\tstatus = \"okay\";\n+};\n+\n+&spi0 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&spi0_pins &spi0_cs_pins>;\n+\tcs-gpios = <&gpio 8 1>, <&gpio 7 1>;\n+\n+\tspidev0: spidev@0{\n+\t\tcompatible = \"spidev\";\n+\t\treg = <0>;\t/* CE0 */\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\tspi-max-frequency = <125000000>;\n+\t};\n+\n+\tspidev1: spidev@1{\n+\t\tcompatible = \"spidev\";\n+\t\treg = <1>;\t/* CE1 */\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\tspi-max-frequency = <125000000>;\n+\t};\n+};\n+\n+/delete-node/ &i2c0mux;\n+\n+i2c0: &i2c0if {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&i2c0_pins>;\n+\tclock-frequency = <100000>;\n+};\n+\n+i2c_csi_dsi: &i2c1 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&i2c1_pins>;\n+\tclock-frequency = <100000>;\n+};\n+\n+/ {\n+\taliases {\n+\t\ti2c0 = &i2c0;\n+\t};\n+\n+\t__overrides__ {\n+\t\ti2c0 = <&i2c0>, \"status\";\n+\t};\n+};\n+\n+&i2c2 {\n+\tclock-frequency = <100000>;\n+};\n+\n+&i2s {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&i2s_pins>;\n+};\n+\n+&leds {\n+\tact_led: act {\n+\t\tlabel = \"led0\";\n+\t\tlinux,default-trigger = \"mmc0\";\n+\t\tgpios = <&gpio 16 1>;\n+\t};\n+};\n+\n+&hdmi {\n+\thpd-gpios = <&gpio 46 GPIO_ACTIVE_HIGH>;\n+};\n+\n+&audio {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&audio_pins>;\n+};\n+\n+/ {\n+\t__overrides__ {\n+\t\tact_led_gpio = <&act_led>,\"gpios:4\";\n+\t\tact_led_activelow = <&act_led>,\"gpios:8\";\n+\t\tact_led_trigger = <&act_led>,\"linux,default-trigger\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/bcm2708-rpi-b.dts b/arch/arm/boot/dts/bcm2708-rpi-b.dts\nnew file mode 100644\nindex 000000000000..305f1dbde60f\n--- /dev/null\n+++ b/arch/arm/boot/dts/bcm2708-rpi-b.dts\n@@ -0,0 +1,114 @@\n+/dts-v1/;\n+\n+#include \"bcm2708.dtsi\"\n+#include \"bcm2708-rpi.dtsi\"\n+#include \"bcm283x-rpi-smsc9512.dtsi\"\n+#include \"bcm283x-rpi-csi1-2lane.dtsi\"\n+#include \"bcm283x-rpi-i2c0mux_0_28.dtsi\"\n+\n+/ {\n+\tcompatible = \"raspberrypi,model-b\", \"brcm,bcm2835\";\n+\tmodel = \"Raspberry Pi Model B\";\n+};\n+\n+&gpio {\n+\tspi0_pins: spi0_pins {\n+\t\tbrcm,pins = <9 10 11>;\n+\t\tbrcm,function = <4>; /* alt0 */\n+\t};\n+\n+\tspi0_cs_pins: spi0_cs_pins {\n+\t\tbrcm,pins = <8 7>;\n+\t\tbrcm,function = <1>; /* output */\n+\t};\n+\n+\ti2c0_pins: i2c0 {\n+\t\tbrcm,pins = <0 1>;\n+\t\tbrcm,function = <4>;\n+\t};\n+\n+\ti2c1_pins: i2c1 {\n+\t\tbrcm,pins = <2 3>;\n+\t\tbrcm,function = <4>;\n+\t};\n+\n+\ti2s_pins: i2s {\n+\t\tbrcm,pins = <28 29 30 31>;\n+\t\tbrcm,function = <6>; /* alt2 */\n+\t};\n+\n+\taudio_pins: audio_pins {\n+\t\tbrcm,pins = <40 45>;\n+\t\tbrcm,function = <4>;\n+\t};\n+};\n+\n+&uart0 {\n+\tstatus = \"okay\";\n+};\n+\n+&spi0 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&spi0_pins &spi0_cs_pins>;\n+\tcs-gpios = <&gpio 8 1>, <&gpio 7 1>;\n+\n+\tspidev0: spidev@0{\n+\t\tcompatible = \"spidev\";\n+\t\treg = <0>;\t/* CE0 */\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\tspi-max-frequency = <125000000>;\n+\t};\n+\n+\tspidev1: spidev@1{\n+\t\tcompatible = \"spidev\";\n+\t\treg = <1>;\t/* CE1 */\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\tspi-max-frequency = <125000000>;\n+\t};\n+};\n+\n+&i2c0if {\n+\tclock-frequency = <100000>;\n+};\n+\n+&i2c1 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&i2c1_pins>;\n+\tclock-frequency = <100000>;\n+};\n+\n+&i2c2 {\n+\tclock-frequency = <100000>;\n+};\n+\n+&i2s {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&i2s_pins>;\n+};\n+\n+&leds {\n+\tact_led: act {\n+\t\tlabel = \"led0\";\n+\t\tlinux,default-trigger = \"mmc0\";\n+\t\tgpios = <&gpio 16 1>;\n+\t};\n+};\n+\n+&hdmi {\n+\thpd-gpios = <&gpio 46 GPIO_ACTIVE_HIGH>;\n+};\n+\n+&audio {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&audio_pins>;\n+};\n+\n+/ {\n+\t__overrides__ {\n+\t\tact_led_gpio = <&act_led>,\"gpios:4\";\n+\t\tact_led_activelow = <&act_led>,\"gpios:8\";\n+\t\tact_led_trigger = <&act_led>,\"linux,default-trigger\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/bcm2708-rpi-bt.dtsi b/arch/arm/boot/dts/bcm2708-rpi-bt.dtsi\nnew file mode 100644\nindex 000000000000..a18f80af97d3\n--- /dev/null\n+++ b/arch/arm/boot/dts/bcm2708-rpi-bt.dtsi\n@@ -0,0 +1,26 @@\n+// SPDX-License-Identifier: GPL-2.0\n+\n+&uart0 {\n+\tbt: bluetooth {\n+\t\tcompatible = \"brcm,bcm43438-bt\";\n+\t\tmax-speed = <3000000>;\n+\t\tshutdown-gpios = <&gpio 45 GPIO_ACTIVE_HIGH>;\n+\t\tstatus = \"disabled\";\n+\t};\n+};\n+\n+&uart1 {\n+\tminibt: bluetooth {\n+\t\tcompatible = \"brcm,bcm43438-bt\";\n+\t\tmax-speed = <460800>;\n+\t\tshutdown-gpios = <&gpio 45 GPIO_ACTIVE_HIGH>;\n+\t\tstatus = \"disabled\";\n+\t};\n+};\n+\n+/ {\n+\t__overrides__ {\n+\t\tkrnbt = <&bt>,\"status\";\n+\t\tkrnbt_baudrate = <&bt>,\"max-speed:0\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/bcm2708-rpi-cm.dts b/arch/arm/boot/dts/bcm2708-rpi-cm.dts\nnew file mode 100644\nindex 000000000000..93062c4ffad2\n--- /dev/null\n+++ b/arch/arm/boot/dts/bcm2708-rpi-cm.dts\n@@ -0,0 +1,97 @@\n+/dts-v1/;\n+\n+#include \"bcm2708-rpi-cm.dtsi\"\n+#include \"bcm283x-rpi-csi0-2lane.dtsi\"\n+#include \"bcm283x-rpi-csi1-4lane.dtsi\"\n+#include \"bcm283x-rpi-i2c0mux_0_28.dtsi\"\n+\n+/ {\n+\tcompatible = \"raspberrypi,compute-module\", \"brcm,bcm2835\";\n+\tmodel = \"Raspberry Pi Compute Module\";\n+};\n+\n+&uart0 {\n+\tstatus = \"okay\";\n+};\n+\n+&gpio {\n+\tspi0_pins: spi0_pins {\n+\t\tbrcm,pins = <9 10 11>;\n+\t\tbrcm,function = <4>; /* alt0 */\n+\t};\n+\n+\tspi0_cs_pins: spi0_cs_pins {\n+\t\tbrcm,pins = <8 7>;\n+\t\tbrcm,function = <1>; /* output */\n+\t};\n+\n+\ti2c0_pins: i2c0 {\n+\t\tbrcm,pins = <0 1>;\n+\t\tbrcm,function = <4>;\n+\t};\n+\n+\ti2c1_pins: i2c1 {\n+\t\tbrcm,pins = <2 3>;\n+\t\tbrcm,function = <4>;\n+\t};\n+\n+\ti2s_pins: i2s {\n+\t\tbrcm,pins = <18 19 20 21>;\n+\t\tbrcm,function = <4>; /* alt0 */\n+\t};\n+\n+\taudio_pins: audio_pins {\n+\t\tbrcm,pins;\n+\t\tbrcm,function;\n+\t};\n+};\n+\n+&spi0 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&spi0_pins &spi0_cs_pins>;\n+\tcs-gpios = <&gpio 8 1>, <&gpio 7 1>;\n+\n+\tspidev0: spidev@0{\n+\t\tcompatible = \"spidev\";\n+\t\treg = <0>;\t/* CE0 */\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\tspi-max-frequency = <125000000>;\n+\t};\n+\n+\tspidev1: spidev@1{\n+\t\tcompatible = \"spidev\";\n+\t\treg = <1>;\t/* CE1 */\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\tspi-max-frequency = <125000000>;\n+\t};\n+};\n+\n+&i2c0if {\n+\tclock-frequency = <100000>;\n+};\n+\n+&i2c1 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&i2c1_pins>;\n+\tclock-frequency = <100000>;\n+};\n+\n+&i2c2 {\n+\tclock-frequency = <100000>;\n+};\n+\n+&i2s {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&i2s_pins>;\n+};\n+\n+&audio {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&audio_pins>;\n+};\n+\n+&hdmi {\n+\thpd-gpios = <&gpio 46 GPIO_ACTIVE_HIGH>;\n+};\ndiff --git a/arch/arm/boot/dts/bcm2708-rpi-cm.dtsi b/arch/arm/boot/dts/bcm2708-rpi-cm.dtsi\nnew file mode 100644\nindex 000000000000..dce160f420fd\n--- /dev/null\n+++ b/arch/arm/boot/dts/bcm2708-rpi-cm.dtsi\n@@ -0,0 +1,18 @@\n+#include \"bcm2708.dtsi\"\n+#include \"bcm2708-rpi.dtsi\"\n+\n+&leds {\n+\tact_led: act {\n+\t\tlabel = \"led0\";\n+\t\tlinux,default-trigger = \"mmc0\";\n+\t\tgpios = <&gpio 47 0>;\n+\t};\n+};\n+\n+/ {\n+\t__overrides__ {\n+\t\tact_led_gpio = <&act_led>,\"gpios:4\";\n+\t\tact_led_activelow = <&act_led>,\"gpios:8\";\n+\t\tact_led_trigger = <&act_led>,\"linux,default-trigger\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/bcm2708-rpi-zero-w.dts b/arch/arm/boot/dts/bcm2708-rpi-zero-w.dts\nnew file mode 100644\nindex 000000000000..f1bbed9fbf73\n--- /dev/null\n+++ b/arch/arm/boot/dts/bcm2708-rpi-zero-w.dts\n@@ -0,0 +1,163 @@\n+/dts-v1/;\n+\n+#include \"bcm2708.dtsi\"\n+#include \"bcm2708-rpi.dtsi\"\n+#include \"bcm283x-rpi-csi1-2lane.dtsi\"\n+#include \"bcm283x-rpi-i2c0mux_0_28.dtsi\"\n+#include \"bcm2708-rpi-bt.dtsi\"\n+\n+/ {\n+\tcompatible = \"raspberrypi,model-zero-w\", \"brcm,bcm2835\";\n+\tmodel = \"Raspberry Pi Zero W\";\n+\n+\tchosen {\n+\t\tbootargs = \"coherent_pool=1M 8250.nr_uarts=1 snd_bcm2835.enable_compat_alsa=0 snd_bcm2835.enable_hdmi=1 snd_bcm2835.enable_headphones=1\";\n+\t};\n+\n+\taliases {\n+\t\tserial0 = &uart1;\n+\t\tserial1 = &uart0;\n+\t\tmmc1 = &mmcnr;\n+\t};\n+};\n+\n+&gpio {\n+\tspi0_pins: spi0_pins {\n+\t\tbrcm,pins = <9 10 11>;\n+\t\tbrcm,function = <4>; /* alt0 */\n+\t};\n+\n+\tspi0_cs_pins: spi0_cs_pins {\n+\t\tbrcm,pins = <8 7>;\n+\t\tbrcm,function = <1>; /* output */\n+\t};\n+\n+\ti2c0_pins: i2c0 {\n+\t\tbrcm,pins = <0 1>;\n+\t\tbrcm,function = <4>;\n+\t};\n+\n+\ti2c1_pins: i2c1 {\n+\t\tbrcm,pins = <2 3>;\n+\t\tbrcm,function = <4>;\n+\t};\n+\n+\ti2s_pins: i2s {\n+\t\tbrcm,pins = <18 19 20 21>;\n+\t\tbrcm,function = <4>; /* alt0 */\n+\t};\n+\n+\tsdio_pins: sdio_pins {\n+\t\tbrcm,pins = <34 35 36 37 38 39>;\n+\t\tbrcm,function = <7>; /* ALT3 = SD1 */\n+\t\tbrcm,pull = <0 2 2 2 2 2>;\n+\t};\n+\n+\tbt_pins: bt_pins {\n+\t\tbrcm,pins = <43>;\n+\t\tbrcm,function = <4>; /* alt0:GPCLK2 */\n+\t\tbrcm,pull = <0>; /* none */\n+\t};\n+\n+\tuart0_pins: uart0_pins {\n+\t\tbrcm,pins = <30 31 32 33>;\n+\t\tbrcm,function = <7>; /* alt3=UART0 */\n+\t\tbrcm,pull = <2 0 0 2>; /* up none none up */\n+\t};\n+\n+\tuart1_pins: uart1_pins {\n+\t\tbrcm,pins;\n+\t\tbrcm,function;\n+\t\tbrcm,pull;\n+\t};\n+\n+\taudio_pins: audio_pins {\n+\t\tbrcm,pins = <>;\n+\t\tbrcm,function = <>;\n+\t};\n+};\n+\n+&mmcnr {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&sdio_pins>;\n+\tbus-width = <4>;\n+\tstatus = \"okay\";\n+};\n+\n+&uart0 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&uart0_pins &bt_pins>;\n+\tstatus = \"okay\";\n+};\n+\n+&uart1 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&uart1_pins>;\n+\tstatus = \"okay\";\n+};\n+\n+&spi0 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&spi0_pins &spi0_cs_pins>;\n+\tcs-gpios = <&gpio 8 1>, <&gpio 7 1>;\n+\n+\tspidev0: spidev@0{\n+\t\tcompatible = \"spidev\";\n+\t\treg = <0>;\t/* CE0 */\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\tspi-max-frequency = <125000000>;\n+\t};\n+\n+\tspidev1: spidev@1{\n+\t\tcompatible = \"spidev\";\n+\t\treg = <1>;\t/* CE1 */\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\tspi-max-frequency = <125000000>;\n+\t};\n+};\n+\n+&i2c0if {\n+\tclock-frequency = <100000>;\n+};\n+\n+&i2c1 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&i2c1_pins>;\n+\tclock-frequency = <100000>;\n+};\n+\n+&i2c2 {\n+\tclock-frequency = <100000>;\n+};\n+\n+&i2s {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&i2s_pins>;\n+};\n+\n+&leds {\n+\tact_led: act {\n+\t\tlabel = \"led0\";\n+\t\tlinux,default-trigger = \"actpwr\";\n+\t\tgpios = <&gpio 47 GPIO_ACTIVE_LOW>;\n+\t};\n+};\n+\n+&hdmi {\n+\thpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>;\n+};\n+\n+&audio {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&audio_pins>;\n+};\n+\n+/ {\n+\t__overrides__ {\n+\t\tact_led_gpio = <&act_led>,\"gpios:4\";\n+\t\tact_led_activelow = <&act_led>,\"gpios:8\";\n+\t\tact_led_trigger = <&act_led>,\"linux,default-trigger\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/bcm2708-rpi-zero.dts b/arch/arm/boot/dts/bcm2708-rpi-zero.dts\nnew file mode 100644\nindex 000000000000..e7578788b839\n--- /dev/null\n+++ b/arch/arm/boot/dts/bcm2708-rpi-zero.dts\n@@ -0,0 +1,117 @@\n+/dts-v1/;\n+\n+#include \"bcm2708.dtsi\"\n+#include \"bcm2708-rpi.dtsi\"\n+#include \"bcm283x-rpi-csi1-2lane.dtsi\"\n+#include \"bcm283x-rpi-i2c0mux_0_28.dtsi\"\n+\n+/ {\n+\tcompatible = \"raspberrypi,model-zero\", \"brcm,bcm2835\";\n+\tmodel = \"Raspberry Pi Zero\";\n+\n+\tchosen {\n+\t\tbootargs = \"coherent_pool=1M snd_bcm2835.enable_compat_alsa=0 snd_bcm2835.enable_hdmi=1 snd_bcm2835.enable_headphones=1\";\n+\t};\n+};\n+\n+&gpio {\n+\tspi0_pins: spi0_pins {\n+\t\tbrcm,pins = <9 10 11>;\n+\t\tbrcm,function = <4>; /* alt0 */\n+\t};\n+\n+\tspi0_cs_pins: spi0_cs_pins {\n+\t\tbrcm,pins = <8 7>;\n+\t\tbrcm,function = <1>; /* output */\n+\t};\n+\n+\ti2c0_pins: i2c0 {\n+\t\tbrcm,pins = <0 1>;\n+\t\tbrcm,function = <4>;\n+\t};\n+\n+\ti2c1_pins: i2c1 {\n+\t\tbrcm,pins = <2 3>;\n+\t\tbrcm,function = <4>;\n+\t};\n+\n+\ti2s_pins: i2s {\n+\t\tbrcm,pins = <18 19 20 21>;\n+\t\tbrcm,function = <4>; /* alt0 */\n+\t};\n+\n+\taudio_pins: audio_pins {\n+\t\tbrcm,pins = <>;\n+\t\tbrcm,function = <>;\n+\t};\n+};\n+\n+&uart0 {\n+\tstatus = \"okay\";\n+};\n+\n+&spi0 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&spi0_pins &spi0_cs_pins>;\n+\tcs-gpios = <&gpio 8 1>, <&gpio 7 1>;\n+\n+\tspidev0: spidev@0{\n+\t\tcompatible = \"spidev\";\n+\t\treg = <0>;\t/* CE0 */\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\tspi-max-frequency = <125000000>;\n+\t};\n+\n+\tspidev1: spidev@1{\n+\t\tcompatible = \"spidev\";\n+\t\treg = <1>;\t/* CE1 */\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\tspi-max-frequency = <125000000>;\n+\t};\n+};\n+\n+&i2c0if {\n+\tclock-frequency = <100000>;\n+};\n+\n+&i2c1 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&i2c1_pins>;\n+\tclock-frequency = <100000>;\n+};\n+\n+&i2c2 {\n+\tclock-frequency = <100000>;\n+};\n+\n+&i2s {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&i2s_pins>;\n+};\n+\n+&leds {\n+\tact_led: act {\n+\t\tlabel = \"led0\";\n+\t\tlinux,default-trigger = \"actpwr\";\n+\t\tgpios = <&gpio 47 GPIO_ACTIVE_LOW>;\n+\t};\n+};\n+\n+&hdmi {\n+\thpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>;\n+};\n+\n+&audio {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&audio_pins>;\n+};\n+\n+/ {\n+\t__overrides__ {\n+\t\tact_led_gpio = <&act_led>,\"gpios:4\";\n+\t\tact_led_activelow = <&act_led>,\"gpios:8\";\n+\t\tact_led_trigger = <&act_led>,\"linux,default-trigger\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/bcm2708-rpi.dtsi b/arch/arm/boot/dts/bcm2708-rpi.dtsi\nnew file mode 100644\nindex 000000000000..e2458b15d64a\n--- /dev/null\n+++ b/arch/arm/boot/dts/bcm2708-rpi.dtsi\n@@ -0,0 +1,36 @@\n+/* Downstream modifications common to bcm2835, bcm2836, bcm2837 */\n+\n+#include \"bcm2835-rpi.dtsi\"\n+#include \"bcm270x-rpi.dtsi\"\n+\n+/ {\n+\tmemory@0 {\n+\t\tdevice_type = \"memory\";\n+\t\treg = <0x0 0x0>;\n+\t};\n+\n+\taliases {\n+\t\ti2c2 = &i2c2;\n+\t};\n+\n+\t__overrides__ {\n+\t\ti2c2_iknowwhatimdoing = <&i2c2>,\"status\";\n+\t\ti2c2_baudrate = <&i2c2>,\"clock-frequency:0\";\n+\t\tsd_poll_once = <&sdhost>,\"non-removable?\";\n+\t};\n+};\n+\n+&sdhost {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&sdhost_gpio48>;\n+\tstatus = \"okay\";\n+};\n+\n+&hdmi {\n+\tpower-domains = <&power RPI_POWER_DOMAIN_HDMI>;\n+\tstatus = \"disabled\";\n+};\n+\n+&i2c2 {\n+\tstatus = \"disabled\";\n+};\ndiff --git a/arch/arm/boot/dts/bcm2708.dtsi b/arch/arm/boot/dts/bcm2708.dtsi\nnew file mode 100644\nindex 000000000000..36ec4989403f\n--- /dev/null\n+++ b/arch/arm/boot/dts/bcm2708.dtsi\n@@ -0,0 +1,12 @@\n+#include \"bcm2835.dtsi\"\n+#include \"bcm270x.dtsi\"\n+\n+/ {\n+\t__overrides__ {\n+\t\tarm_freq;\n+\t};\n+};\n+\n+&vc4 {\n+\tstatus = \"disabled\";\n+};\ndiff --git a/arch/arm/boot/dts/bcm2709-rpi-2-b.dts b/arch/arm/boot/dts/bcm2709-rpi-2-b.dts\nnew file mode 100644\nindex 000000000000..6b2e3c291d72\n--- /dev/null\n+++ b/arch/arm/boot/dts/bcm2709-rpi-2-b.dts\n@@ -0,0 +1,124 @@\n+/dts-v1/;\n+\n+#include \"bcm2709.dtsi\"\n+#include \"bcm2709-rpi.dtsi\"\n+#include \"bcm283x-rpi-smsc9514.dtsi\"\n+#include \"bcm283x-rpi-csi1-2lane.dtsi\"\n+#include \"bcm283x-rpi-i2c0mux_0_28.dtsi\"\n+\n+/ {\n+\tcompatible = \"raspberrypi,2-model-b\", \"brcm,bcm2836\";\n+\tmodel = \"Raspberry Pi 2 Model B\";\n+};\n+\n+&gpio {\n+\tspi0_pins: spi0_pins {\n+\t\tbrcm,pins = <9 10 11>;\n+\t\tbrcm,function = <4>; /* alt0 */\n+\t};\n+\n+\tspi0_cs_pins: spi0_cs_pins {\n+\t\tbrcm,pins = <8 7>;\n+\t\tbrcm,function = <1>; /* output */\n+\t};\n+\n+\ti2c0_pins: i2c0 {\n+\t\tbrcm,pins = <0 1>;\n+\t\tbrcm,function = <4>;\n+\t};\n+\n+\ti2c1_pins: i2c1 {\n+\t\tbrcm,pins = <2 3>;\n+\t\tbrcm,function = <4>;\n+\t};\n+\n+\ti2s_pins: i2s {\n+\t\tbrcm,pins = <18 19 20 21>;\n+\t\tbrcm,function = <4>; /* alt0 */\n+\t};\n+\n+\taudio_pins: audio_pins {\n+\t\tbrcm,pins = <40 45>;\n+\t\tbrcm,function = <4>;\n+\t};\n+};\n+\n+&uart0 {\n+\tstatus = \"okay\";\n+};\n+\n+&spi0 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&spi0_pins &spi0_cs_pins>;\n+\tcs-gpios = <&gpio 8 1>, <&gpio 7 1>;\n+\n+\tspidev0: spidev@0{\n+\t\tcompatible = \"spidev\";\n+\t\treg = <0>;\t/* CE0 */\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\tspi-max-frequency = <125000000>;\n+\t};\n+\n+\tspidev1: spidev@1{\n+\t\tcompatible = \"spidev\";\n+\t\treg = <1>;\t/* CE1 */\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\tspi-max-frequency = <125000000>;\n+\t};\n+};\n+\n+&i2c0if {\n+\tclock-frequency = <100000>;\n+};\n+\n+&i2c1 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&i2c1_pins>;\n+\tclock-frequency = <100000>;\n+};\n+\n+&i2c2 {\n+\tclock-frequency = <100000>;\n+};\n+\n+&i2s {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&i2s_pins>;\n+};\n+\n+&leds {\n+\tact_led: act {\n+\t\tlabel = \"led0\";\n+\t\tlinux,default-trigger = \"mmc0\";\n+\t\tgpios = <&gpio 47 0>;\n+\t};\n+\n+\tpwr_led: pwr {\n+\t\tlabel = \"led1\";\n+\t\tlinux,default-trigger = \"input\";\n+\t\tgpios = <&gpio 35 0>;\n+\t};\n+};\n+\n+&hdmi {\n+\thpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>;\n+};\n+\n+&audio {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&audio_pins>;\n+};\n+\n+/ {\n+\t__overrides__ {\n+\t\tact_led_gpio = <&act_led>,\"gpios:4\";\n+\t\tact_led_activelow = <&act_led>,\"gpios:8\";\n+\t\tact_led_trigger = <&act_led>,\"linux,default-trigger\";\n+\n+\t\tpwr_led_gpio = <&pwr_led>,\"gpios:4\";\n+\t\tpwr_led_activelow = <&pwr_led>,\"gpios:8\";\n+\t\tpwr_led_trigger = <&pwr_led>,\"linux,default-trigger\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/bcm2709-rpi.dtsi b/arch/arm/boot/dts/bcm2709-rpi.dtsi\nnew file mode 100644\nindex 000000000000..babfa41cd9f7\n--- /dev/null\n+++ b/arch/arm/boot/dts/bcm2709-rpi.dtsi\n@@ -0,0 +1,5 @@\n+#include \"bcm2708-rpi.dtsi\"\n+\n+&vchiq {\n+\tcompatible = \"brcm,bcm2836-vchiq\", \"brcm,bcm2835-vchiq\";\n+};\ndiff --git a/arch/arm/boot/dts/bcm2709.dtsi b/arch/arm/boot/dts/bcm2709.dtsi\nnew file mode 100644\nindex 000000000000..68eafc1b281a\n--- /dev/null\n+++ b/arch/arm/boot/dts/bcm2709.dtsi\n@@ -0,0 +1,22 @@\n+#include \"bcm2836.dtsi\"\n+#include \"bcm270x.dtsi\"\n+\n+/ {\n+\tsoc {\n+\t\tranges = <0x7e000000 0x3f000000 0x01000000>,\n+\t\t         <0x40000000 0x40000000 0x00040000>;\n+\n+\t\t/delete-node/ timer@7e003000;\n+\t};\n+\n+\t__overrides__ {\n+\t\tarm_freq = <&v7_cpu0>, \"clock-frequency:0\",\n+\t\t\t   <&v7_cpu1>, \"clock-frequency:0\",\n+\t\t\t   <&v7_cpu2>, \"clock-frequency:0\",\n+\t\t\t   <&v7_cpu3>, \"clock-frequency:0\";\n+\t};\n+};\n+\n+&vc4 {\n+\tstatus = \"disabled\";\n+};\ndiff --git a/arch/arm/boot/dts/bcm270x-rpi.dtsi b/arch/arm/boot/dts/bcm270x-rpi.dtsi\nnew file mode 100644\nindex 000000000000..68a7e1c09db1\n--- /dev/null\n+++ b/arch/arm/boot/dts/bcm270x-rpi.dtsi\n@@ -0,0 +1,154 @@\n+/* Downstream modifications to bcm2835-rpi.dtsi */\n+\n+/ {\n+\taliases {\n+\t\taudio = &audio;\n+\t\taux = &aux;\n+\t\tsound = &sound;\n+\t\tsoc = &soc;\n+\t\tdma = &dma;\n+\t\tintc = &intc;\n+\t\twatchdog = &watchdog;\n+\t\trandom = &random;\n+\t\tmailbox = &mailbox;\n+\t\tgpio = &gpio;\n+\t\tuart0 = &uart0;\n+\t\tuart1 = &uart1;\n+\t\tsdhost = &sdhost;\n+\t\tmmc = &mmc;\n+\t\tmmc1 = &mmc;\n+\t\tmmc0 = &sdhost;\n+\t\ti2s = &i2s;\n+\t\ti2c0 = &i2c0;\n+\t\ti2c1 = &i2c1;\n+\t\ti2c10 = &i2c_csi_dsi;\n+\t\tspi0 = &spi0;\n+\t\tspi1 = &spi1;\n+\t\tspi2 = &spi2;\n+\t\tusb = &usb;\n+\t\tleds = &leds;\n+\t\tfb = &fb;\n+\t\tthermal = &thermal;\n+\t\taxiperf = &axiperf;\n+\t};\n+\n+\t/* Define these notional regulators for use by overlays */\n+\tvdd_3v3_reg: fixedregulator_3v3 {\n+\t\tcompatible = \"regulator-fixed\";\n+\t\tregulator-always-on;\n+\t\tregulator-max-microvolt = <3300000>;\n+\t\tregulator-min-microvolt = <3300000>;\n+\t\tregulator-name = \"3v3\";\n+\t};\n+\n+\tvdd_5v0_reg: fixedregulator_5v0 {\n+\t\tcompatible = \"regulator-fixed\";\n+\t\tregulator-always-on;\n+\t\tregulator-max-microvolt = <5000000>;\n+\t\tregulator-min-microvolt = <5000000>;\n+\t\tregulator-name = \"5v0\";\n+\t};\n+\n+\tleds: leds {\n+\t\tcompatible = \"gpio-leds\";\n+\t};\n+\n+\tsoc {\n+\t\tgpiomem {\n+\t\t\tcompatible = \"brcm,bcm2835-gpiomem\";\n+\t\t\treg = <0x7e200000 0x1000>;\n+\t\t};\n+\n+\t\tfb: fb {\n+\t\t\tcompatible = \"brcm,bcm2708-fb\";\n+\t\t\tfirmware = <&firmware>;\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\n+\t\tvcsm: vcsm {\n+\t\t\tcompatible = \"raspberrypi,bcm2835-vcsm\";\n+\t\t\tfirmware = <&firmware>;\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\n+\t\t/* External sound card */\n+\t\tsound: sound {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\tcache_line_size;\n+\n+\t\tuart0 = <&uart0>,\"status\";\n+\t\tuart1 = <&uart1>,\"status\";\n+\t\ti2s = <&i2s>,\"status\";\n+\t\tspi = <&spi0>,\"status\";\n+\t\ti2c0 = <&i2c0if>,\"status\",<&i2c0mux>,\"status\";\n+\t\ti2c1 = <&i2c1>,\"status\";\n+\t\ti2c0_baudrate = <&i2c0if>,\"clock-frequency:0\";\n+\t\ti2c1_baudrate = <&i2c1>,\"clock-frequency:0\";\n+\n+\t\taudio = <&audio>,\"status\";\n+\t\twatchdog = <&watchdog>,\"status\";\n+\t\trandom = <&random>,\"status\";\n+\t\tsd_overclock = <&sdhost>,\"brcm,overclock-50:0\";\n+\t\tsd_force_pio = <&sdhost>,\"brcm,force-pio?\";\n+\t\tsd_pio_limit = <&sdhost>,\"brcm,pio-limit:0\";\n+\t\tsd_debug     = <&sdhost>,\"brcm,debug\";\n+\t\tsdio_overclock = <&mmc>,\"brcm,overclock-50:0\",\n+\t\t\t\t <&mmcnr>,\"brcm,overclock-50:0\";\n+\t\taxiperf      = <&axiperf>,\"status\";\n+\t};\n+};\n+\n+&uart0 {\n+\tskip-init;\n+};\n+\n+&uart1 {\n+\tskip-init;\n+};\n+\n+&txp {\n+\tstatus = \"disabled\";\n+};\n+\n+&i2c0if {\n+\tstatus = \"disabled\";\n+};\n+\n+&i2c0mux {\n+\tstatus = \"disabled\";\n+};\n+\n+&i2c1 {\n+\tstatus = \"disabled\";\n+};\n+\n+&clocks {\n+\tfirmware = <&firmware>;\n+};\n+\n+&sdhci {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&emmc_gpio48>;\n+\tbus-width = <4>;\n+};\n+\n+&cpu_thermal {\n+\t/delete-node/ trips;\n+};\n+\n+&vec {\n+\tstatus = \"disabled\";\n+};\n+\n+&vchiq {\n+\t/* Onboard audio */\n+\taudio: bcm2835_audio {\n+\t\tcompatible = \"brcm,bcm2835-audio\";\n+\t\tbrcm,pwm-channels = <8>;\n+\t\tstatus = \"disabled\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/bcm270x.dtsi b/arch/arm/boot/dts/bcm270x.dtsi\nnew file mode 100644\nindex 000000000000..446d4ff64842\n--- /dev/null\n+++ b/arch/arm/boot/dts/bcm270x.dtsi\n@@ -0,0 +1,197 @@\n+/* Downstream bcm283x.dtsi diff */\n+#include <dt-bindings/power/raspberrypi-power.h>\n+\n+/ {\n+\tchosen {\n+\t\tbootargs = \"coherent_pool=1M snd_bcm2835.enable_compat_alsa=0 snd_bcm2835.enable_hdmi=1 snd_bcm2835.enable_headphones=1\";\n+\t\t/delete-property/ stdout-path;\n+\t};\n+\n+\tsoc: soc {\n+\n+\t\twatchdog: watchdog@7e100000 {\n+\t\t\t/* Add label */\n+\t\t};\n+\n+\t\trandom: rng@7e104000 {\n+\t\t\t/* Add label */\n+\t\t};\n+\n+\t\tspi0: spi@7e204000 {\n+\t\t\t/* Add label */\n+\t\t};\n+\n+#ifndef BCM2711\n+\t\tpixelvalve0: pixelvalve@7e206000 {\n+\t\t\t/* Add label */\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tpixelvalve1: pixelvalve@7e207000 {\n+\t\t\t/* Add label */\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+#endif\n+\n+\t\t/delete-node/ sdhci@7e300000;\n+\n+\t\tsdhci: mmc: mmc@7e300000 {\n+\t\t\tcompatible = \"brcm,bcm2835-mmc\", \"brcm,bcm2835-sdhci\";\n+\t\t\treg = <0x7e300000 0x100>;\n+\t\t\tinterrupts = <2 30>;\n+\t\t\tclocks = <&clocks BCM2835_CLOCK_EMMC>;\n+\t\t\tdmas = <&dma 11>;\n+\t\t\tdma-names = \"rx-tx\";\n+\t\t\tbrcm,overclock-50 = <0>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\t/* A clone of mmc but with non-removable set */\n+\t\tmmcnr: mmcnr@7e300000 {\n+\t\t\tcompatible = \"brcm,bcm2835-mmc\", \"brcm,bcm2835-sdhci\";\n+\t\t\treg = <0x7e300000 0x100>;\n+\t\t\tinterrupts = <2 30>;\n+\t\t\tclocks = <&clocks BCM2835_CLOCK_EMMC>;\n+\t\t\tdmas = <&dma 11>;\n+\t\t\tdma-names = \"rx-tx\";\n+\t\t\tbrcm,overclock-50 = <0>;\n+\t\t\tnon-removable;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\thvs: hvs@7e400000 {\n+\t\t\t/* Add label */\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tfirmwarekms: firmwarekms@7e600000 {\n+\t\t\tcompatible = \"raspberrypi,rpi-firmware-kms\";\n+\t\t\t/* SMI interrupt reg */\n+\t\t\treg = <0x7e600000 0x100>;\n+\t\t\tinterrupts = <2 16>;\n+\t\t\tbrcm,firmware = <&firmware>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tsmi: smi@7e600000 {\n+\t\t\tcompatible = \"brcm,bcm2835-smi\";\n+\t\t\treg = <0x7e600000 0x100>;\n+\t\t\tinterrupts = <2 16>;\n+\t\t\tclocks = <&clocks BCM2835_CLOCK_SMI>;\n+\t\t\tassigned-clocks = <&clocks BCM2835_CLOCK_SMI>;\n+\t\t\tassigned-clock-rates = <125000000>;\n+\t\t\tdmas = <&dma 4>;\n+\t\t\tdma-names = \"rx-tx\";\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tcsi0: csi@7e800000 {\n+\t\t\tcompatible = \"brcm,bcm2835-unicam\";\n+\t\t\treg = <0x7e800000 0x800>,\n+\t\t\t      <0x7e802000 0x4>;\n+\t\t\tinterrupts = <2 6>;\n+\t\t\tclocks = <&clocks BCM2835_CLOCK_CAM0>,\n+\t\t\t\t <&firmware_clocks 4>;\n+\t\t\tclock-names = \"lp\", \"vpu\";\n+\t\t\tpower-domains = <&power RPI_POWER_DOMAIN_UNICAM0>;\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\t#clock-cells = <1>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tcsi1: csi@7e801000 {\n+\t\t\tcompatible = \"brcm,bcm2835-unicam\";\n+\t\t\treg = <0x7e801000 0x800>,\n+\t\t\t      <0x7e802004 0x4>;\n+\t\t\tinterrupts = <2 7>;\n+\t\t\tclocks = <&clocks BCM2835_CLOCK_CAM1>,\n+\t\t\t\t <&firmware_clocks 4>;\n+\t\t\tclock-names = \"lp\", \"vpu\";\n+\t\t\tpower-domains = <&power RPI_POWER_DOMAIN_UNICAM1>;\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\t#clock-cells = <1>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+#ifndef BCM2711\n+\t\tpixelvalve2: pixelvalve@7e807000 {\n+\t\t\t/* Add label */\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+#endif\n+\n+\t\thdmi@7e902000 { /* hdmi */\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tusb@7e980000 { /* usb */\n+\t\t\tcompatible = \"brcm,bcm2708-usb\";\n+\t\t\treg = <0x7e980000 0x10000>,\n+\t\t\t      <0x7e006000 0x1000>;\n+\t\t\tinterrupt-names = \"usb\",\n+\t\t\t\t\t  \"soft\";\n+\t\t\tinterrupts = <1 9>,\n+\t\t\t\t     <2 0>;\n+\t\t};\n+\n+#ifndef BCM2711\n+\t\tv3d@7ec00000 { /* vd3 */\n+\t\t\tcompatible = \"brcm,vc4-v3d\";\n+\t\t\tpower-domains = <&power RPI_POWER_DOMAIN_V3D>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+#endif\n+\n+\t\taxiperf: axiperf {\n+\t\t\tcompatible = \"brcm,bcm2835-axiperf\";\n+\t\t\treg = <0x7e009800 0x100>,\n+\t\t\t      <0x7ee08000 0x100>;\n+\t\t\tfirmware = <&firmware>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\tcam0-pwdn-ctrl;\n+\t\tcam0-pwdn;\n+\t\tcam0-led-ctrl;\n+\t\tcam0-led;\n+\t};\n+};\n+\n+&gpio {\n+\tinterrupts = <2 17>, <2 18>;\n+\n+\tdpi_18bit_gpio0: dpi_18bit_gpio0 {\n+\t\tbrcm,pins = <0 1 2 3 4 5 6 7 8 9 10 11\n+\t\t\t     12 13 14 15 16 17 18 19\n+\t\t\t     20 21>;\n+\t\tbrcm,function = <BCM2835_FSEL_ALT2>;\n+\t};\n+};\n+\n+&uart0 {\n+\t/* Enable CTS bug workaround */\n+\tcts-event-workaround;\n+};\n+\n+&i2s {\n+\t#sound-dai-cells = <0>;\n+\tdmas = <&dma 2>, <&dma 3>;\n+\tdma-names = \"tx\", \"rx\";\n+};\n+\n+&sdhost {\n+\tdmas = <&dma (13|(1<<29))>;\n+\tdma-names = \"rx-tx\";\n+\tbus-width = <4>;\n+\tbrcm,overclock-50 = <0>;\n+\tbrcm,pio-limit = <1>;\n+};\n+\n+&spi0 {\n+\tdmas = <&dma 6>, <&dma 7>;\n+\tdma-names = \"tx\", \"rx\";\n+};\ndiff --git a/arch/arm/boot/dts/bcm2710-rpi-2-b.dts b/arch/arm/boot/dts/bcm2710-rpi-2-b.dts\nnew file mode 100644\nindex 000000000000..49cfda63606e\n--- /dev/null\n+++ b/arch/arm/boot/dts/bcm2710-rpi-2-b.dts\n@@ -0,0 +1,124 @@\n+/dts-v1/;\n+\n+#include \"bcm2710.dtsi\"\n+#include \"bcm2709-rpi.dtsi\"\n+#include \"bcm283x-rpi-smsc9514.dtsi\"\n+#include \"bcm283x-rpi-csi1-2lane.dtsi\"\n+#include \"bcm283x-rpi-i2c0mux_0_28.dtsi\"\n+\n+/ {\n+\tcompatible = \"raspberrypi,2-model-b-rev2\", \"brcm,bcm2837\";\n+\tmodel = \"Raspberry Pi 2 Model B rev 1.2\";\n+};\n+\n+&gpio {\n+\tspi0_pins: spi0_pins {\n+\t\tbrcm,pins = <9 10 11>;\n+\t\tbrcm,function = <4>; /* alt0 */\n+\t};\n+\n+\tspi0_cs_pins: spi0_cs_pins {\n+\t\tbrcm,pins = <8 7>;\n+\t\tbrcm,function = <1>; /* output */\n+\t};\n+\n+\ti2c0_pins: i2c0 {\n+\t\tbrcm,pins = <0 1>;\n+\t\tbrcm,function = <4>;\n+\t};\n+\n+\ti2c1_pins: i2c1 {\n+\t\tbrcm,pins = <2 3>;\n+\t\tbrcm,function = <4>;\n+\t};\n+\n+\ti2s_pins: i2s {\n+\t\tbrcm,pins = <18 19 20 21>;\n+\t\tbrcm,function = <4>; /* alt0 */\n+\t};\n+\n+\taudio_pins: audio_pins {\n+\t\tbrcm,pins = <40 45>;\n+\t\tbrcm,function = <4>;\n+\t};\n+};\n+\n+&uart0 {\n+\tstatus = \"okay\";\n+};\n+\n+&spi0 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&spi0_pins &spi0_cs_pins>;\n+\tcs-gpios = <&gpio 8 1>, <&gpio 7 1>;\n+\n+\tspidev0: spidev@0{\n+\t\tcompatible = \"spidev\";\n+\t\treg = <0>;\t/* CE0 */\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\tspi-max-frequency = <125000000>;\n+\t};\n+\n+\tspidev1: spidev@1{\n+\t\tcompatible = \"spidev\";\n+\t\treg = <1>;\t/* CE1 */\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\tspi-max-frequency = <125000000>;\n+\t};\n+};\n+\n+&i2c0if {\n+\tclock-frequency = <100000>;\n+};\n+\n+&i2c1 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&i2c1_pins>;\n+\tclock-frequency = <100000>;\n+};\n+\n+&i2c2 {\n+\tclock-frequency = <100000>;\n+};\n+\n+&i2s {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&i2s_pins>;\n+};\n+\n+&leds {\n+\tact_led: act {\n+\t\tlabel = \"led0\";\n+\t\tlinux,default-trigger = \"mmc0\";\n+\t\tgpios = <&gpio 47 0>;\n+\t};\n+\n+\tpwr_led: pwr {\n+\t\tlabel = \"led1\";\n+\t\tlinux,default-trigger = \"input\";\n+\t\tgpios = <&gpio 35 0>;\n+\t};\n+};\n+\n+&hdmi {\n+\thpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>;\n+};\n+\n+&audio {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&audio_pins>;\n+};\n+\n+/ {\n+\t__overrides__ {\n+\t\tact_led_gpio = <&act_led>,\"gpios:4\";\n+\t\tact_led_activelow = <&act_led>,\"gpios:8\";\n+\t\tact_led_trigger = <&act_led>,\"linux,default-trigger\";\n+\n+\t\tpwr_led_gpio = <&pwr_led>,\"gpios:4\";\n+\t\tpwr_led_activelow = <&pwr_led>,\"gpios:8\";\n+\t\tpwr_led_trigger = <&pwr_led>,\"linux,default-trigger\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/bcm2710-rpi-3-b-plus.dts b/arch/arm/boot/dts/bcm2710-rpi-3-b-plus.dts\nnew file mode 100644\nindex 000000000000..4e4e47100831\n--- /dev/null\n+++ b/arch/arm/boot/dts/bcm2710-rpi-3-b-plus.dts\n@@ -0,0 +1,196 @@\n+/dts-v1/;\n+\n+#include \"bcm2710.dtsi\"\n+#include \"bcm2709-rpi.dtsi\"\n+#include \"bcm283x-rpi-lan7515.dtsi\"\n+#include \"bcm283x-rpi-csi1-2lane.dtsi\"\n+#include \"bcm283x-rpi-i2c0mux_0_44.dtsi\"\n+#include \"bcm271x-rpi-bt.dtsi\"\n+\n+/ {\n+\tcompatible = \"raspberrypi,3-model-b-plus\", \"brcm,bcm2837\";\n+\tmodel = \"Raspberry Pi 3 Model B+\";\n+\n+\tchosen {\n+\t\tbootargs = \"coherent_pool=1M 8250.nr_uarts=1 snd_bcm2835.enable_compat_alsa=0 snd_bcm2835.enable_hdmi=1 snd_bcm2835.enable_headphones=1\";\n+\t};\n+\n+\taliases {\n+\t\tserial0 = &uart1;\n+\t\tserial1 = &uart0;\n+\t\tmmc1 = &mmcnr;\n+\t};\n+};\n+\n+&gpio {\n+\tspi0_pins: spi0_pins {\n+\t\tbrcm,pins = <9 10 11>;\n+\t\tbrcm,function = <4>; /* alt0 */\n+\t};\n+\n+\tspi0_cs_pins: spi0_cs_pins {\n+\t\tbrcm,pins = <8 7>;\n+\t\tbrcm,function = <1>; /* output */\n+\t};\n+\n+\ti2c0_pins: i2c0 {\n+\t\tbrcm,pins = <0 1>;\n+\t\tbrcm,function = <4>;\n+\t};\n+\n+\ti2c1_pins: i2c1 {\n+\t\tbrcm,pins = <2 3>;\n+\t\tbrcm,function = <4>;\n+\t};\n+\n+\ti2s_pins: i2s {\n+\t\tbrcm,pins = <18 19 20 21>;\n+\t\tbrcm,function = <4>; /* alt0 */\n+\t};\n+\n+\tsdio_pins: sdio_pins {\n+\t\tbrcm,pins =     <34 35 36 37 38 39>;\n+\t\tbrcm,function = <7>; // alt3 = SD1\n+\t\tbrcm,pull =     <0 2 2 2 2 2>;\n+\t};\n+\n+\tbt_pins: bt_pins {\n+\t\tbrcm,pins = <43>;\n+\t\tbrcm,function = <4>; /* alt0:GPCLK2 */\n+\t\tbrcm,pull = <0>;\n+\t};\n+\n+\tuart0_pins: uart0_pins {\n+\t\tbrcm,pins = <32 33>;\n+\t\tbrcm,function = <7>; /* alt3=UART0 */\n+\t\tbrcm,pull = <0 2>;\n+\t};\n+\n+\tuart1_pins: uart1_pins {\n+\t\tbrcm,pins;\n+\t\tbrcm,function;\n+\t\tbrcm,pull;\n+\t};\n+\n+\taudio_pins: audio_pins {\n+\t\tbrcm,pins = <40 41>;\n+\t\tbrcm,function = <4>;\n+\t};\n+};\n+\n+&mmcnr {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&sdio_pins>;\n+\tbus-width = <4>;\n+\tstatus = \"okay\";\n+};\n+\n+&firmware {\n+\texpgpio: expgpio {\n+\t\tcompatible = \"raspberrypi,firmware-gpio\";\n+\t\tgpio-controller;\n+\t\t#gpio-cells = <2>;\n+\t\tstatus = \"okay\";\n+\t};\n+};\n+\n+&uart0 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&uart0_pins &bt_pins>;\n+\tstatus = \"okay\";\n+};\n+\n+&uart1 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&uart1_pins>;\n+\tstatus = \"okay\";\n+};\n+\n+&spi0 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&spi0_pins &spi0_cs_pins>;\n+\tcs-gpios = <&gpio 8 1>, <&gpio 7 1>;\n+\n+\tspidev0: spidev@0{\n+\t\tcompatible = \"spidev\";\n+\t\treg = <0>;\t/* CE0 */\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\tspi-max-frequency = <125000000>;\n+\t};\n+\n+\tspidev1: spidev@1{\n+\t\tcompatible = \"spidev\";\n+\t\treg = <1>;\t/* CE1 */\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\tspi-max-frequency = <125000000>;\n+\t};\n+};\n+\n+&i2c0if {\n+\tclock-frequency = <100000>;\n+};\n+\n+&i2c1 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&i2c1_pins>;\n+\tclock-frequency = <100000>;\n+};\n+\n+&i2c2 {\n+\tclock-frequency = <100000>;\n+};\n+\n+&i2s {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&i2s_pins>;\n+};\n+\n+&leds {\n+\tact_led: act {\n+\t\tlabel = \"led0\";\n+\t\tlinux,default-trigger = \"mmc0\";\n+\t\tgpios = <&gpio 29 0>;\n+\t};\n+\n+\tpwr_led: pwr {\n+\t\tlabel = \"led1\";\n+\t\tlinux,default-trigger = \"default-on\";\n+\t\tgpios = <&expgpio 2 GPIO_ACTIVE_LOW>;\n+\t};\n+};\n+\n+&hdmi {\n+\thpd-gpios = <&gpio 28 GPIO_ACTIVE_LOW>;\n+};\n+\n+&audio {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&audio_pins>;\n+};\n+\n+&eth_phy {\n+\tmicrochip,eee-enabled;\n+\tmicrochip,tx-lpi-timer = <600>; /* non-aggressive*/\n+\tmicrochip,downshift-after = <2>;\n+};\n+\n+/ {\n+\t__overrides__ {\n+\t\tact_led_gpio = <&act_led>,\"gpios:4\";\n+\t\tact_led_activelow = <&act_led>,\"gpios:8\";\n+\t\tact_led_trigger = <&act_led>,\"linux,default-trigger\";\n+\n+\t\tpwr_led_gpio = <&pwr_led>,\"gpios:4\";\n+\t\tpwr_led_activelow = <&pwr_led>,\"gpios:8\";\n+\t\tpwr_led_trigger = <&pwr_led>,\"linux,default-trigger\";\n+\n+\t\teee = <&eth_phy>,\"microchip,eee-enabled?\";\n+\t\ttx_lpi_timer = <&eth_phy>,\"microchip,tx-lpi-timer:0\";\n+\t\teth_led0 = <&eth_phy>,\"microchip,led-modes:0\";\n+\t\teth_led1 = <&eth_phy>,\"microchip,led-modes:4\";\n+\t\teth_downshift_after = <&eth_phy>,\"microchip,downshift-after:0\";\n+\t\teth_max_speed = <&eth_phy>,\"max-speed:0\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/bcm2710-rpi-3-b.dts b/arch/arm/boot/dts/bcm2710-rpi-3-b.dts\nnew file mode 100644\nindex 000000000000..8989c00b03e5\n--- /dev/null\n+++ b/arch/arm/boot/dts/bcm2710-rpi-3-b.dts\n@@ -0,0 +1,198 @@\n+/dts-v1/;\n+\n+#include \"bcm2710.dtsi\"\n+#include \"bcm2709-rpi.dtsi\"\n+#include \"bcm283x-rpi-smsc9514.dtsi\"\n+#include \"bcm283x-rpi-csi1-2lane.dtsi\"\n+#include \"bcm283x-rpi-i2c0mux_0_44.dtsi\"\n+#include \"bcm271x-rpi-bt.dtsi\"\n+\n+/ {\n+\tcompatible = \"raspberrypi,3-model-b\", \"brcm,bcm2837\";\n+\tmodel = \"Raspberry Pi 3 Model B\";\n+\n+\tchosen {\n+\t\tbootargs = \"coherent_pool=1M 8250.nr_uarts=1 snd_bcm2835.enable_compat_alsa=0 snd_bcm2835.enable_hdmi=1 snd_bcm2835.enable_headphones=1\";\n+\t};\n+\n+\taliases {\n+\t\tserial0 = &uart1;\n+\t\tserial1 = &uart0;\n+\t\tmmc1 = &mmcnr;\n+\t};\n+};\n+\n+&gpio {\n+\tspi0_pins: spi0_pins {\n+\t\tbrcm,pins = <9 10 11>;\n+\t\tbrcm,function = <4>; /* alt0 */\n+\t};\n+\n+\tspi0_cs_pins: spi0_cs_pins {\n+\t\tbrcm,pins = <8 7>;\n+\t\tbrcm,function = <1>; /* output */\n+\t};\n+\n+\ti2c0_pins: i2c0 {\n+\t\tbrcm,pins = <0 1>;\n+\t\tbrcm,function = <4>;\n+\t};\n+\n+\ti2c1_pins: i2c1 {\n+\t\tbrcm,pins = <2 3>;\n+\t\tbrcm,function = <4>;\n+\t};\n+\n+\ti2s_pins: i2s {\n+\t\tbrcm,pins = <18 19 20 21>;\n+\t\tbrcm,function = <4>; /* alt0 */\n+\t};\n+\n+\tsdio_pins: sdio_pins {\n+\t\tbrcm,pins =     <34 35 36 37 38 39>;\n+\t\tbrcm,function = <7>; // alt3 = SD1\n+\t\tbrcm,pull =     <0 2 2 2 2 2>;\n+\t};\n+\n+\tbt_pins: bt_pins {\n+\t\tbrcm,pins = <43>;\n+\t\tbrcm,function = <4>; /* alt0:GPCLK2 */\n+\t\tbrcm,pull = <0>;\n+\t};\n+\n+\tuart0_pins: uart0_pins {\n+\t\tbrcm,pins = <32 33>;\n+\t\tbrcm,function = <7>; /* alt3=UART0 */\n+\t\tbrcm,pull = <0 2>;\n+\t};\n+\n+\tuart1_pins: uart1_pins {\n+\t\tbrcm,pins;\n+\t\tbrcm,function;\n+\t\tbrcm,pull;\n+\t};\n+\n+\taudio_pins: audio_pins {\n+\t\tbrcm,pins = <40 41>;\n+\t\tbrcm,function = <4>;\n+\t};\n+};\n+\n+&mmcnr {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&sdio_pins>;\n+\tbus-width = <4>;\n+\tstatus = \"okay\";\n+};\n+\n+&soc {\n+\tvirtgpio: virtgpio {\n+\t\tcompatible = \"brcm,bcm2835-virtgpio\";\n+\t\tgpio-controller;\n+\t\t#gpio-cells = <2>;\n+\t\tfirmware = <&firmware>;\n+\t\tstatus = \"okay\";\n+\t};\n+\n+};\n+\n+&firmware {\n+\texpgpio: expgpio {\n+\t\tcompatible = \"raspberrypi,firmware-gpio\";\n+\t\tgpio-controller;\n+\t\t#gpio-cells = <2>;\n+\t\tstatus = \"okay\";\n+\t};\n+};\n+\n+&uart0 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&uart0_pins &bt_pins>;\n+\tstatus = \"okay\";\n+};\n+\n+&uart1 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&uart1_pins>;\n+\tstatus = \"okay\";\n+};\n+\n+&bt {\n+\tmax-speed = <921600>;\n+};\n+\n+&spi0 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&spi0_pins &spi0_cs_pins>;\n+\tcs-gpios = <&gpio 8 1>, <&gpio 7 1>;\n+\n+\tspidev0: spidev@0{\n+\t\tcompatible = \"spidev\";\n+\t\treg = <0>;\t/* CE0 */\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\tspi-max-frequency = <125000000>;\n+\t};\n+\n+\tspidev1: spidev@1{\n+\t\tcompatible = \"spidev\";\n+\t\treg = <1>;\t/* CE1 */\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\tspi-max-frequency = <125000000>;\n+\t};\n+};\n+\n+&i2c0if {\n+\tclock-frequency = <100000>;\n+};\n+\n+&i2c1 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&i2c1_pins>;\n+\tclock-frequency = <100000>;\n+};\n+\n+&i2c2 {\n+\tclock-frequency = <100000>;\n+};\n+\n+&i2s {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&i2s_pins>;\n+};\n+\n+&leds {\n+\tact_led: act {\n+\t\tlabel = \"led0\";\n+\t\tlinux,default-trigger = \"mmc0\";\n+\t\tgpios = <&virtgpio 0 0>;\n+\t};\n+\n+\tpwr_led: pwr {\n+\t\tlabel = \"led1\";\n+\t\tlinux,default-trigger = \"input\";\n+\t\tgpios = <&expgpio 7 0>;\n+\t};\n+};\n+\n+&hdmi {\n+\thpd-gpios = <&expgpio 4 GPIO_ACTIVE_LOW>;\n+};\n+\n+&audio {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&audio_pins>;\n+};\n+\n+/ {\n+\t__overrides__ {\n+\t\tact_led_gpio = <&act_led>,\"gpios:4\";\n+\t\tact_led_activelow = <&act_led>,\"gpios:8\";\n+\t\tact_led_trigger = <&act_led>,\"linux,default-trigger\";\n+\n+\t\tpwr_led_gpio = <&pwr_led>,\"gpios:4\";\n+\t\tpwr_led_activelow = <&pwr_led>,\"gpios:8\";\n+\t\tpwr_led_trigger = <&pwr_led>,\"linux,default-trigger\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/bcm2710-rpi-cm3.dts b/arch/arm/boot/dts/bcm2710-rpi-cm3.dts\nnew file mode 100644\nindex 000000000000..f972979281f5\n--- /dev/null\n+++ b/arch/arm/boot/dts/bcm2710-rpi-cm3.dts\n@@ -0,0 +1,133 @@\n+/dts-v1/;\n+\n+#include \"bcm2710.dtsi\"\n+#include \"bcm2709-rpi.dtsi\"\n+#include \"bcm283x-rpi-csi0-2lane.dtsi\"\n+#include \"bcm283x-rpi-csi1-4lane.dtsi\"\n+#include \"bcm283x-rpi-i2c0mux_0_28.dtsi\"\n+/ {\n+\tcompatible = \"raspberrypi,3-compute-module\", \"brcm,bcm2837\";\n+\tmodel = \"Raspberry Pi Compute Module 3\";\n+};\n+\n+&uart0 {\n+\tstatus = \"okay\";\n+};\n+\n+&gpio {\n+\tspi0_pins: spi0_pins {\n+\t\tbrcm,pins = <9 10 11>;\n+\t\tbrcm,function = <4>; /* alt0 */\n+\t};\n+\n+\tspi0_cs_pins: spi0_cs_pins {\n+\t\tbrcm,pins = <8 7>;\n+\t\tbrcm,function = <1>; /* output */\n+\t};\n+\n+\ti2c0_pins: i2c0 {\n+\t\tbrcm,pins = <0 1>;\n+\t\tbrcm,function = <4>;\n+\t};\n+\n+\ti2c1_pins: i2c1 {\n+\t\tbrcm,pins = <2 3>;\n+\t\tbrcm,function = <4>;\n+\t};\n+\n+\ti2s_pins: i2s {\n+\t\tbrcm,pins = <18 19 20 21>;\n+\t\tbrcm,function = <4>; /* alt0 */\n+\t};\n+\n+\taudio_pins: audio_pins {\n+\t\tbrcm,pins;\n+\t\tbrcm,function;\n+\t};\n+};\n+\n+&soc {\n+\tvirtgpio: virtgpio {\n+\t\tcompatible = \"brcm,bcm2835-virtgpio\";\n+\t\tgpio-controller;\n+\t\t#gpio-cells = <2>;\n+\t\tfirmware = <&firmware>;\n+\t\tstatus = \"okay\";\n+\t};\n+\n+};\n+\n+&firmware {\n+\texpgpio: expgpio {\n+\t\tcompatible = \"raspberrypi,firmware-gpio\";\n+\t\tgpio-controller;\n+\t\t#gpio-cells = <2>;\n+\t\tstatus = \"okay\";\n+\t};\n+};\n+\n+&spi0 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&spi0_pins &spi0_cs_pins>;\n+\tcs-gpios = <&gpio 8 1>, <&gpio 7 1>;\n+\n+\tspidev0: spidev@0{\n+\t\tcompatible = \"spidev\";\n+\t\treg = <0>;\t/* CE0 */\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\tspi-max-frequency = <125000000>;\n+\t};\n+\n+\tspidev1: spidev@1{\n+\t\tcompatible = \"spidev\";\n+\t\treg = <1>;\t/* CE1 */\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\tspi-max-frequency = <125000000>;\n+\t};\n+};\n+\n+&i2c0if {\n+\tclock-frequency = <100000>;\n+};\n+\n+&i2c1 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&i2c1_pins>;\n+\tclock-frequency = <100000>;\n+};\n+\n+&i2c2 {\n+\tclock-frequency = <100000>;\n+};\n+\n+&i2s {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&i2s_pins>;\n+};\n+\n+&leds {\n+\tact_led: act {\n+\t\tlabel = \"led0\";\n+\t\tlinux,default-trigger = \"mmc0\";\n+\t\tgpios = <&virtgpio 0 0>;\n+\t};\n+};\n+\n+&hdmi {\n+\thpd-gpios = <&expgpio 0 GPIO_ACTIVE_LOW>;\n+};\n+\n+&audio {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&audio_pins>;\n+};\n+\n+/ {\n+\t__overrides__ {\n+\t\tact_led_gpio = <&act_led>,\"gpios:4\";\n+\t\tact_led_activelow = <&act_led>,\"gpios:8\";\n+\t\tact_led_trigger = <&act_led>,\"linux,default-trigger\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/bcm2710.dtsi b/arch/arm/boot/dts/bcm2710.dtsi\nnew file mode 100644\nindex 000000000000..4e47480dd933\n--- /dev/null\n+++ b/arch/arm/boot/dts/bcm2710.dtsi\n@@ -0,0 +1,29 @@\n+#include \"bcm2837.dtsi\"\n+#include \"bcm270x.dtsi\"\n+\n+/ {\n+\tcompatible = \"brcm,bcm2837\", \"brcm,bcm2836\";\n+\n+\tarm-pmu {\n+#ifdef RPI364\n+\t\tcompatible = \"arm,armv8-pmuv3\", \"arm,cortex-a7-pmu\";\n+#else\n+\t\tcompatible = \"arm,cortex-a7-pmu\";\n+#endif\n+\t};\n+\n+\tsoc {\n+\t\t/delete-node/ timer@7e003000;\n+\t};\n+\n+\t__overrides__ {\n+\t\tarm_freq = <&cpu0>, \"clock-frequency:0\",\n+\t\t       <&cpu1>, \"clock-frequency:0\",\n+\t\t       <&cpu2>, \"clock-frequency:0\",\n+\t\t       <&cpu3>, \"clock-frequency:0\";\n+\t};\n+};\n+\n+&vc4 {\n+\tstatus = \"disabled\";\n+};\ndiff --git a/arch/arm/boot/dts/bcm2711-rpi-4-b.dts b/arch/arm/boot/dts/bcm2711-rpi-4-b.dts\nindex 5395e8c2484e..3e67c2b634be 100644\n--- a/arch/arm/boot/dts/bcm2711-rpi-4-b.dts\n+++ b/arch/arm/boot/dts/bcm2711-rpi-4-b.dts\n@@ -2,7 +2,6 @@\n /dts-v1/;\n #include \"bcm2711.dtsi\"\n #include \"bcm2835-rpi.dtsi\"\n-#include \"bcm283x-rpi-usb-peripheral.dtsi\"\n \n #include <dt-bindings/reset/raspberrypi,firmware-reset.h>\n \n@@ -95,7 +94,7 @@ expgpio: gpio {\n \t\t\t\t  \"VDD_SD_IO_SEL\",\n \t\t\t\t  \"CAM_GPIO\",\n \t\t\t\t  \"SD_PWR_ON\",\n-\t\t\t\t  \"\";\n+\t\t\t\t  \"SD_OC_N\";\n \t\tstatus = \"okay\";\n \t};\n \n@@ -301,3 +300,306 @@ &vc4 {\n &vec {\n \tstatus = \"disabled\";\n };\n+\n+// =============================================\n+// Downstream rpi- changes\n+\n+#define BCM2711\n+\n+#include \"bcm270x.dtsi\"\n+#include \"bcm271x-rpi-bt.dtsi\"\n+\n+/ {\n+\tsoc {\n+\t\t/delete-node/ pixelvalve@7e807000;\n+\t\t/delete-node/ hdmi@7e902000;\n+\t};\n+};\n+\n+#include \"bcm2711-rpi.dtsi\"\n+#include \"bcm283x-rpi-csi1-2lane.dtsi\"\n+#include \"bcm283x-rpi-i2c0mux_0_44.dtsi\"\n+\n+/ {\n+\tchosen {\n+\t\tbootargs = \"coherent_pool=1M 8250.nr_uarts=1 snd_bcm2835.enable_compat_alsa=0 snd_bcm2835.enable_hdmi=1 snd_bcm2835.enable_headphones=1\";\n+\t};\n+\n+\taliases {\n+\t\tserial0 = &uart1;\n+\t\tserial1 = &uart0;\n+\t\tmmc0 = &emmc2;\n+\t\tmmc1 = &mmcnr;\n+\t\tmmc2 = &sdhost;\n+\t\t/delete-property/ i2c2;\n+\t\ti2c3 = &i2c3;\n+\t\ti2c4 = &i2c4;\n+\t\ti2c5 = &i2c5;\n+\t\ti2c6 = &i2c6;\n+\t\t/delete-property/ intc;\n+\t};\n+\n+\t/delete-node/ wifi-pwrseq;\n+};\n+\n+&mmcnr {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&sdio_pins>;\n+\tbus-width = <4>;\n+\tstatus = \"okay\";\n+};\n+\n+&uart0 {\n+\tpinctrl-0 = <&uart0_pins &bt_pins>;\n+\tstatus = \"okay\";\n+};\n+\n+&uart1 {\n+\tpinctrl-0 = <&uart1_pins>;\n+};\n+\n+&spi0 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&spi0_pins &spi0_cs_pins>;\n+\tcs-gpios = <&gpio 8 1>, <&gpio 7 1>;\n+\n+\tspidev0: spidev@0{\n+\t\tcompatible = \"spidev\";\n+\t\treg = <0>;\t/* CE0 */\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\tspi-max-frequency = <125000000>;\n+\t};\n+\n+\tspidev1: spidev@1{\n+\t\tcompatible = \"spidev\";\n+\t\treg = <1>;\t/* CE1 */\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\tspi-max-frequency = <125000000>;\n+\t};\n+};\n+\n+&gpio {\n+\tspi0_pins: spi0_pins {\n+\t\tbrcm,pins = <9 10 11>;\n+\t\tbrcm,function = <BCM2835_FSEL_ALT0>;\n+\t};\n+\n+\tspi0_cs_pins: spi0_cs_pins {\n+\t\tbrcm,pins = <8 7>;\n+\t\tbrcm,function = <BCM2835_FSEL_GPIO_OUT>;\n+\t};\n+\n+\tspi3_pins: spi3_pins {\n+\t\tbrcm,pins = <1 2 3>;\n+\t\tbrcm,function = <BCM2835_FSEL_ALT3>;\n+\t};\n+\n+\tspi3_cs_pins: spi3_cs_pins {\n+\t\tbrcm,pins = <0 24>;\n+\t\tbrcm,function = <BCM2835_FSEL_GPIO_OUT>;\n+\t};\n+\n+\tspi4_pins: spi4_pins {\n+\t\tbrcm,pins = <5 6 7>;\n+\t\tbrcm,function = <BCM2835_FSEL_ALT3>;\n+\t};\n+\n+\tspi4_cs_pins: spi4_cs_pins {\n+\t\tbrcm,pins = <4 25>;\n+\t\tbrcm,function = <BCM2835_FSEL_GPIO_OUT>;\n+\t};\n+\n+\tspi5_pins: spi5_pins {\n+\t\tbrcm,pins = <13 14 15>;\n+\t\tbrcm,function = <BCM2835_FSEL_ALT3>;\n+\t};\n+\n+\tspi5_cs_pins: spi5_cs_pins {\n+\t\tbrcm,pins = <12 26>;\n+\t\tbrcm,function = <BCM2835_FSEL_GPIO_OUT>;\n+\t};\n+\n+\tspi6_pins: spi6_pins {\n+\t\tbrcm,pins = <19 20 21>;\n+\t\tbrcm,function = <BCM2835_FSEL_ALT3>;\n+\t};\n+\n+\tspi6_cs_pins: spi6_cs_pins {\n+\t\tbrcm,pins = <18 27>;\n+\t\tbrcm,function = <BCM2835_FSEL_GPIO_OUT>;\n+\t};\n+\n+\ti2c0_pins: i2c0 {\n+\t\tbrcm,pins = <0 1>;\n+\t\tbrcm,function = <BCM2835_FSEL_ALT0>;\n+\t\tbrcm,pull = <BCM2835_PUD_UP>;\n+\t};\n+\n+\ti2c1_pins: i2c1 {\n+\t\tbrcm,pins = <2 3>;\n+\t\tbrcm,function = <BCM2835_FSEL_ALT0>;\n+\t\tbrcm,pull = <BCM2835_PUD_UP>;\n+\t};\n+\n+\ti2c3_pins: i2c3 {\n+\t\tbrcm,pins = <4 5>;\n+\t\tbrcm,function = <BCM2835_FSEL_ALT5>;\n+\t\tbrcm,pull = <BCM2835_PUD_UP>;\n+\t};\n+\n+\ti2c4_pins: i2c4 {\n+\t\tbrcm,pins = <8 9>;\n+\t\tbrcm,function = <BCM2835_FSEL_ALT5>;\n+\t\tbrcm,pull = <BCM2835_PUD_UP>;\n+\t};\n+\n+\ti2c5_pins: i2c5 {\n+\t\tbrcm,pins = <12 13>;\n+\t\tbrcm,function = <BCM2835_FSEL_ALT5>;\n+\t\tbrcm,pull = <BCM2835_PUD_UP>;\n+\t};\n+\n+\ti2c6_pins: i2c6 {\n+\t\tbrcm,pins = <22 23>;\n+\t\tbrcm,function = <BCM2835_FSEL_ALT5>;\n+\t\tbrcm,pull = <BCM2835_PUD_UP>;\n+\t};\n+\n+\ti2s_pins: i2s {\n+\t\tbrcm,pins = <18 19 20 21>;\n+\t\tbrcm,function = <BCM2835_FSEL_ALT0>;\n+\t};\n+\n+\tsdio_pins: sdio_pins {\n+\t\tbrcm,pins =     <34 35 36 37 38 39>;\n+\t\tbrcm,function = <BCM2835_FSEL_ALT3>; // alt3 = SD1\n+\t\tbrcm,pull =     <0 2 2 2 2 2>;\n+\t};\n+\n+\tbt_pins: bt_pins {\n+\t\tbrcm,pins = \"-\"; // non-empty to keep btuart happy, //4 = 0\n+\t\t\t\t // to fool pinctrl\n+\t\tbrcm,function = <0>;\n+\t\tbrcm,pull = <2>;\n+\t};\n+\n+\tuart0_pins: uart0_pins {\n+\t\tbrcm,pins = <32 33>;\n+\t\tbrcm,function = <BCM2835_FSEL_ALT3>;\n+\t\tbrcm,pull = <0 2>;\n+\t};\n+\n+\tuart1_pins: uart1_pins {\n+\t\tbrcm,pins;\n+\t\tbrcm,function;\n+\t\tbrcm,pull;\n+\t};\n+\n+\tuart2_pins: uart2_pins {\n+\t\tbrcm,pins = <0 1>;\n+\t\tbrcm,function = <BCM2835_FSEL_ALT4>;\n+\t\tbrcm,pull = <0 2>;\n+\t};\n+\n+\tuart3_pins: uart3_pins {\n+\t\tbrcm,pins = <4 5>;\n+\t\tbrcm,function = <BCM2835_FSEL_ALT4>;\n+\t\tbrcm,pull = <0 2>;\n+\t};\n+\n+\tuart4_pins: uart4_pins {\n+\t\tbrcm,pins = <8 9>;\n+\t\tbrcm,function = <BCM2835_FSEL_ALT4>;\n+\t\tbrcm,pull = <0 2>;\n+\t};\n+\n+\tuart5_pins: uart5_pins {\n+\t\tbrcm,pins = <12 13>;\n+\t\tbrcm,function = <BCM2835_FSEL_ALT4>;\n+\t\tbrcm,pull = <0 2>;\n+\t};\n+};\n+\n+&i2c0if {\n+\tclock-frequency = <100000>;\n+};\n+\n+&i2c1 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&i2c1_pins>;\n+\tclock-frequency = <100000>;\n+};\n+\n+&i2s {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&i2s_pins>;\n+};\n+\n+/ {\n+\t__overrides__ {\n+\t\t/delete-property/ i2c2_baudrate;\n+\t\t/delete-property/ i2c2_iknowwhatimdoing;\n+\t};\n+};\n+\n+// =============================================\n+// Board specific stuff here\n+\n+&sdhost {\n+\tstatus = \"disabled\";\n+};\n+\n+&phy1 {\n+\tled-modes = <0x00 0x08>; /* link/activity link */\n+};\n+\n+&gpio {\n+\taudio_pins: audio_pins {\n+\t\tbrcm,pins = <40 41>;\n+\t\tbrcm,function = <4>;\n+\t};\n+};\n+\n+&leds {\n+\tact_led: act {\n+\t\tlabel = \"led0\";\n+\t\tlinux,default-trigger = \"mmc0\";\n+\t\tgpios = <&gpio 42 GPIO_ACTIVE_HIGH>;\n+\t};\n+\n+\tpwr_led: pwr {\n+\t\tlabel = \"led1\";\n+\t\tlinux,default-trigger = \"default-on\";\n+\t\tgpios = <&expgpio 2 GPIO_ACTIVE_LOW>;\n+\t};\n+};\n+\n+&pwm1 {\n+\tstatus = \"disabled\";\n+};\n+\n+&audio {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&audio_pins>;\n+};\n+\n+/ {\n+\t__overrides__ {\n+\t\tact_led_gpio = <&act_led>,\"gpios:4\";\n+\t\tact_led_activelow = <&act_led>,\"gpios:8\";\n+\t\tact_led_trigger = <&act_led>,\"linux,default-trigger\";\n+\n+\t\tpwr_led_gpio = <&pwr_led>,\"gpios:4\";\n+\t\tpwr_led_activelow = <&pwr_led>,\"gpios:8\";\n+\t\tpwr_led_trigger = <&pwr_led>,\"linux,default-trigger\";\n+\n+\t\teth_led0 = <&phy1>,\"led-modes:0\";\n+\t\teth_led1 = <&phy1>,\"led-modes:4\";\n+\n+\t\tsd_poll_once = <&emmc2>, \"non-removable?\";\n+\t\tspi_dma4 = <&spi0>, \"dmas:0=\", <&dma40>,\n+\t\t\t   <&spi0>, \"dmas:8=\", <&dma40>;\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/bcm2711-rpi-cm4.dts b/arch/arm/boot/dts/bcm2711-rpi-cm4.dts\nnew file mode 100644\nindex 000000000000..0ca3a0126220\n--- /dev/null\n+++ b/arch/arm/boot/dts/bcm2711-rpi-cm4.dts\n@@ -0,0 +1,609 @@\n+// SPDX-License-Identifier: GPL-2.0\n+/dts-v1/;\n+#include \"bcm2711.dtsi\"\n+#include \"bcm2835-rpi.dtsi\"\n+\n+/ {\n+\tcompatible = \"raspberrypi,4-compute-module\", \"brcm,bcm2711\";\n+\tmodel = \"Raspberry Pi Compute Module 4\";\n+\n+\tchosen {\n+\t\t/* 8250 auxiliary UART instead of pl011 */\n+\t\tstdout-path = \"serial1:115200n8\";\n+\t};\n+\n+\t/* Will be filled by the bootloader */\n+\tmemory@0 {\n+\t\tdevice_type = \"memory\";\n+\t\treg = <0 0 0>;\n+\t};\n+\n+\taliases {\n+\t\temmc2bus = &emmc2bus;\n+\t\tethernet0 = &genet;\n+\t\tpcie0 = &pcie0;\n+\t};\n+\n+\tleds {\n+\t\tact {\n+\t\t\tgpios = <&gpio 42 GPIO_ACTIVE_HIGH>;\n+\t\t};\n+\n+\t\tpwr {\n+\t\t\tlabel = \"PWR\";\n+\t\t\tgpios = <&expgpio 2 GPIO_ACTIVE_LOW>;\n+\t\t\tdefault-state = \"keep\";\n+\t\t\tlinux,default-trigger = \"default-on\";\n+\t\t};\n+\t};\n+\n+\twifi_pwrseq: wifi-pwrseq {\n+\t\tcompatible = \"mmc-pwrseq-simple\";\n+\t\treset-gpios = <&expgpio 1 GPIO_ACTIVE_LOW>;\n+\t};\n+\n+\tsd_io_1v8_reg: sd_io_1v8_reg {\n+\t\tcompatible = \"regulator-gpio\";\n+\t\tregulator-name = \"vdd-sd-io\";\n+\t\tregulator-min-microvolt = <1800000>;\n+\t\tregulator-max-microvolt = <3300000>;\n+\t\tregulator-boot-on;\n+\t\tregulator-always-on;\n+\t\tregulator-settling-time-us = <5000>;\n+\t\tgpios = <&expgpio 4 GPIO_ACTIVE_HIGH>;\n+\t\tstates = <1800000 0x1\n+\t\t\t  3300000 0x0>;\n+\t\tstatus = \"okay\";\n+\t};\n+\n+\tsd_vcc_reg: sd_vcc_reg {\n+\t\tcompatible = \"regulator-fixed\";\n+\t\tregulator-name = \"vcc-sd\";\n+\t\tregulator-min-microvolt = <3300000>;\n+\t\tregulator-max-microvolt = <3300000>;\n+\t\tregulator-boot-on;\n+\t\tenable-active-high;\n+\t\tgpio = <&expgpio 6 GPIO_ACTIVE_HIGH>;\n+\t};\n+};\n+\n+&ddc0 {\n+\tstatus = \"okay\";\n+};\n+\n+&ddc1 {\n+\tstatus = \"okay\";\n+};\n+\n+&firmware {\n+\texpgpio: gpio {\n+\t\tcompatible = \"raspberrypi,firmware-gpio\";\n+\t\tgpio-controller;\n+\t\t#gpio-cells = <2>;\n+\t\tgpio-line-names = \"BT_ON\",\n+\t\t\t\t  \"WL_ON\",\n+\t\t\t\t  \"PWR_LED_OFF\",\n+\t\t\t\t  \"ANT1\",\n+\t\t\t\t  \"VDD_SD_IO_SEL\",\n+\t\t\t\t  \"CAM_GPIO\",\n+\t\t\t\t  \"SD_PWR_ON\",\n+\t\t\t\t  \"ANT2\";\n+\t\tstatus = \"okay\";\n+\n+\t\tant1: ant1 {\n+\t\t\tgpio-hog;\n+\t\t\tgpios = <3 GPIO_ACTIVE_HIGH>;\n+\t\t\toutput-high;\n+\t\t};\n+\n+\t\tant2: ant2 {\n+\t\t\tgpio-hog;\n+\t\t\tgpios = <7 GPIO_ACTIVE_HIGH>;\n+\t\t\toutput-low;\n+\t\t};\n+\t};\n+};\n+\n+&gpio {\n+\t/*\n+\t * Parts taken from rpi_SCH_4b_4p0_reduced.pdf and\n+\t * the official GPU firmware DT blob.\n+\t *\n+\t * Legend:\n+\t * \"FOO\" = GPIO line named \"FOO\" on the schematic\n+\t * \"FOO_N\" = GPIO line named \"FOO\" on schematic, active low\n+\t */\n+\tgpio-line-names = \"ID_SDA\",\n+\t\t\t  \"ID_SCL\",\n+\t\t\t  \"SDA1\",\n+\t\t\t  \"SCL1\",\n+\t\t\t  \"GPIO_GCLK\",\n+\t\t\t  \"GPIO5\",\n+\t\t\t  \"GPIO6\",\n+\t\t\t  \"SPI_CE1_N\",\n+\t\t\t  \"SPI_CE0_N\",\n+\t\t\t  \"SPI_MISO\",\n+\t\t\t  \"SPI_MOSI\",\n+\t\t\t  \"SPI_SCLK\",\n+\t\t\t  \"GPIO12\",\n+\t\t\t  \"GPIO13\",\n+\t\t\t  /* Serial port */\n+\t\t\t  \"TXD1\",\n+\t\t\t  \"RXD1\",\n+\t\t\t  \"GPIO16\",\n+\t\t\t  \"GPIO17\",\n+\t\t\t  \"GPIO18\",\n+\t\t\t  \"GPIO19\",\n+\t\t\t  \"GPIO20\",\n+\t\t\t  \"GPIO21\",\n+\t\t\t  \"GPIO22\",\n+\t\t\t  \"GPIO23\",\n+\t\t\t  \"GPIO24\",\n+\t\t\t  \"GPIO25\",\n+\t\t\t  \"GPIO26\",\n+\t\t\t  \"GPIO27\",\n+\t\t\t  \"RGMII_MDIO\",\n+\t\t\t  \"RGMIO_MDC\",\n+\t\t\t  /* Used by BT module */\n+\t\t\t  \"CTS0\",\n+\t\t\t  \"RTS0\",\n+\t\t\t  \"TXD0\",\n+\t\t\t  \"RXD0\",\n+\t\t\t  /* Used by Wifi */\n+\t\t\t  \"SD1_CLK\",\n+\t\t\t  \"SD1_CMD\",\n+\t\t\t  \"SD1_DATA0\",\n+\t\t\t  \"SD1_DATA1\",\n+\t\t\t  \"SD1_DATA2\",\n+\t\t\t  \"SD1_DATA3\",\n+\t\t\t  /* Shared with SPI flash */\n+\t\t\t  \"PWM0_MISO\",\n+\t\t\t  \"PWM1_MOSI\",\n+\t\t\t  \"STATUS_LED_G_CLK\",\n+\t\t\t  \"SPIFLASH_CE_N\",\n+\t\t\t  \"SDA0\",\n+\t\t\t  \"SCL0\",\n+\t\t\t  \"RGMII_RXCLK\",\n+\t\t\t  \"RGMII_RXCTL\",\n+\t\t\t  \"RGMII_RXD0\",\n+\t\t\t  \"RGMII_RXD1\",\n+\t\t\t  \"RGMII_RXD2\",\n+\t\t\t  \"RGMII_RXD3\",\n+\t\t\t  \"RGMII_TXCLK\",\n+\t\t\t  \"RGMII_TXCTL\",\n+\t\t\t  \"RGMII_TXD0\",\n+\t\t\t  \"RGMII_TXD1\",\n+\t\t\t  \"RGMII_TXD2\",\n+\t\t\t  \"RGMII_TXD3\";\n+};\n+\n+&hdmi0 {\n+\tclocks = <&firmware_clocks 13>, <&firmware_clocks 14>, <&dvp 0>, <&clk_27MHz>;\n+\tclock-names = \"hdmi\", \"bvb\", \"audio\", \"cec\";\n+\tstatus = \"okay\";\n+};\n+\n+&hdmi1 {\n+\tclocks = <&firmware_clocks 13>, <&firmware_clocks 14>, <&dvp 1>, <&clk_27MHz>;\n+\tclock-names = \"hdmi\", \"bvb\", \"audio\", \"cec\";\n+\tstatus = \"okay\";\n+};\n+\n+&hvs {\n+\tclocks = <&firmware_clocks 4>;\n+};\n+\n+&pixelvalve0 {\n+\tstatus = \"okay\";\n+};\n+\n+&pixelvalve1 {\n+\tstatus = \"okay\";\n+};\n+\n+&pixelvalve2 {\n+\tstatus = \"okay\";\n+};\n+\n+&pixelvalve4 {\n+\tstatus = \"okay\";\n+};\n+\n+&vc4 {\n+\tstatus = \"okay\";\n+};\n+\n+&vec {\n+\tstatus = \"disabled\";\n+};\n+\n+&pwm1 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pwm1_0_gpio40 &pwm1_1_gpio41>;\n+\tstatus = \"okay\";\n+};\n+\n+/* SDHCI is used to control the SDIO for wireless */\n+&sdhci {\n+\t#address-cells = <1>;\n+\t#size-cells = <0>;\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&emmc_gpio34>;\n+\tbus-width = <4>;\n+\tnon-removable;\n+\tmmc-pwrseq = <&wifi_pwrseq>;\n+\tstatus = \"okay\";\n+\n+\tbrcmf: wifi@1 {\n+\t\treg = <1>;\n+\t\tcompatible = \"brcm,bcm4329-fmac\";\n+\t};\n+};\n+\n+/* EMMC2 is used to drive the EMMC card */\n+&emmc2 {\n+\tbus-width = <8>;\n+\tvqmmc-supply = <&sd_io_1v8_reg>;\n+\tvmmc-supply = <&sd_vcc_reg>;\n+\tbroken-cd;\n+\tstatus = \"okay\";\n+};\n+\n+&genet {\n+\tphy-handle = <&phy1>;\n+\tphy-mode = \"rgmii-rxid\";\n+\tstatus = \"okay\";\n+};\n+\n+&genet_mdio {\n+\tphy1: ethernet-phy@1 {\n+\t\t/* No PHY interrupt */\n+\t\treg = <0x1>;\n+\t};\n+};\n+\n+/* uart0 communicates with the BT module */\n+&uart0 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&uart0_ctsrts_gpio30 &uart0_gpio32>;\n+\tuart-has-rtscts;\n+\tstatus = \"okay\";\n+\n+\tbluetooth {\n+\t\tcompatible = \"brcm,bcm43438-bt\";\n+\t\tmax-speed = <2000000>;\n+\t\tshutdown-gpios = <&expgpio 0 GPIO_ACTIVE_HIGH>;\n+\t};\n+};\n+\n+/* uart1 is mapped to the pin header */\n+&uart1 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&uart1_gpio14>;\n+\tstatus = \"okay\";\n+};\n+\n+&vchiq {\n+\tinterrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;\n+};\n+\n+// =============================================\n+// Downstream rpi- changes\n+\n+#define BCM2711\n+\n+#include \"bcm270x.dtsi\"\n+#include \"bcm271x-rpi-bt.dtsi\"\n+\n+/ {\n+\tsoc {\n+\t\t/delete-node/ pixelvalve@7e807000;\n+\t\t/delete-node/ hdmi@7e902000;\n+\t};\n+};\n+\n+#include \"bcm2711-rpi.dtsi\"\n+#include \"bcm283x-rpi-csi0-2lane.dtsi\"\n+#include \"bcm283x-rpi-csi1-4lane.dtsi\"\n+#include \"bcm283x-rpi-i2c0mux_0_44.dtsi\"\n+\n+/ {\n+\tchosen {\n+\t\tbootargs = \"coherent_pool=1M 8250.nr_uarts=1 snd_bcm2835.enable_compat_alsa=0 snd_bcm2835.enable_hdmi=1 snd_bcm2835.enable_headphones=1\";\n+\t};\n+\n+\taliases {\n+\t\tserial0 = &uart1;\n+\t\tserial1 = &uart0;\n+\t\tmmc0 = &emmc2;\n+\t\tmmc1 = &mmcnr;\n+\t\tmmc2 = &sdhost;\n+\t\t/delete-property/ i2c2;\n+\t\ti2c3 = &i2c3;\n+\t\ti2c4 = &i2c4;\n+\t\ti2c5 = &i2c5;\n+\t\ti2c6 = &i2c6;\n+\t\t/delete-property/ intc;\n+\t};\n+\n+\t/delete-node/ wifi-pwrseq;\n+};\n+\n+&mmcnr {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&sdio_pins>;\n+\tbus-width = <4>;\n+\tstatus = \"okay\";\n+};\n+\n+&uart0 {\n+\tpinctrl-0 = <&uart0_pins &bt_pins>;\n+\tstatus = \"okay\";\n+};\n+\n+&uart1 {\n+\tpinctrl-0 = <&uart1_pins>;\n+};\n+\n+&spi0 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&spi0_pins &spi0_cs_pins>;\n+\tcs-gpios = <&gpio 8 1>, <&gpio 7 1>;\n+\n+\tspidev0: spidev@0{\n+\t\tcompatible = \"spidev\";\n+\t\treg = <0>;\t/* CE0 */\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\tspi-max-frequency = <125000000>;\n+\t};\n+\n+\tspidev1: spidev@1{\n+\t\tcompatible = \"spidev\";\n+\t\treg = <1>;\t/* CE1 */\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\tspi-max-frequency = <125000000>;\n+\t};\n+};\n+\n+&gpio {\n+\tspi0_pins: spi0_pins {\n+\t\tbrcm,pins = <9 10 11>;\n+\t\tbrcm,function = <BCM2835_FSEL_ALT0>;\n+\t};\n+\n+\tspi0_cs_pins: spi0_cs_pins {\n+\t\tbrcm,pins = <8 7>;\n+\t\tbrcm,function = <BCM2835_FSEL_GPIO_OUT>;\n+\t};\n+\n+\tspi3_pins: spi3_pins {\n+\t\tbrcm,pins = <1 2 3>;\n+\t\tbrcm,function = <BCM2835_FSEL_ALT3>;\n+\t};\n+\n+\tspi3_cs_pins: spi3_cs_pins {\n+\t\tbrcm,pins = <0 24>;\n+\t\tbrcm,function = <BCM2835_FSEL_GPIO_OUT>;\n+\t};\n+\n+\tspi4_pins: spi4_pins {\n+\t\tbrcm,pins = <5 6 7>;\n+\t\tbrcm,function = <BCM2835_FSEL_ALT3>;\n+\t};\n+\n+\tspi4_cs_pins: spi4_cs_pins {\n+\t\tbrcm,pins = <4 25>;\n+\t\tbrcm,function = <BCM2835_FSEL_GPIO_OUT>;\n+\t};\n+\n+\tspi5_pins: spi5_pins {\n+\t\tbrcm,pins = <13 14 15>;\n+\t\tbrcm,function = <BCM2835_FSEL_ALT3>;\n+\t};\n+\n+\tspi5_cs_pins: spi5_cs_pins {\n+\t\tbrcm,pins = <12 26>;\n+\t\tbrcm,function = <BCM2835_FSEL_GPIO_OUT>;\n+\t};\n+\n+\tspi6_pins: spi6_pins {\n+\t\tbrcm,pins = <19 20 21>;\n+\t\tbrcm,function = <BCM2835_FSEL_ALT3>;\n+\t};\n+\n+\tspi6_cs_pins: spi6_cs_pins {\n+\t\tbrcm,pins = <18 27>;\n+\t\tbrcm,function = <BCM2835_FSEL_GPIO_OUT>;\n+\t};\n+\n+\ti2c0_pins: i2c0 {\n+\t\tbrcm,pins = <0 1>;\n+\t\tbrcm,function = <BCM2835_FSEL_ALT0>;\n+\t\tbrcm,pull = <BCM2835_PUD_UP>;\n+\t};\n+\n+\ti2c1_pins: i2c1 {\n+\t\tbrcm,pins = <2 3>;\n+\t\tbrcm,function = <BCM2835_FSEL_ALT0>;\n+\t\tbrcm,pull = <BCM2835_PUD_UP>;\n+\t};\n+\n+\ti2c3_pins: i2c3 {\n+\t\tbrcm,pins = <4 5>;\n+\t\tbrcm,function = <BCM2835_FSEL_ALT5>;\n+\t\tbrcm,pull = <BCM2835_PUD_UP>;\n+\t};\n+\n+\ti2c4_pins: i2c4 {\n+\t\tbrcm,pins = <8 9>;\n+\t\tbrcm,function = <BCM2835_FSEL_ALT5>;\n+\t\tbrcm,pull = <BCM2835_PUD_UP>;\n+\t};\n+\n+\ti2c5_pins: i2c5 {\n+\t\tbrcm,pins = <12 13>;\n+\t\tbrcm,function = <BCM2835_FSEL_ALT5>;\n+\t\tbrcm,pull = <BCM2835_PUD_UP>;\n+\t};\n+\n+\ti2c6_pins: i2c6 {\n+\t\tbrcm,pins = <22 23>;\n+\t\tbrcm,function = <BCM2835_FSEL_ALT5>;\n+\t\tbrcm,pull = <BCM2835_PUD_UP>;\n+\t};\n+\n+\ti2s_pins: i2s {\n+\t\tbrcm,pins = <18 19 20 21>;\n+\t\tbrcm,function = <BCM2835_FSEL_ALT0>;\n+\t};\n+\n+\tsdio_pins: sdio_pins {\n+\t\tbrcm,pins =     <34 35 36 37 38 39>;\n+\t\tbrcm,function = <BCM2835_FSEL_ALT3>; // alt3 = SD1\n+\t\tbrcm,pull =     <0 2 2 2 2 2>;\n+\t};\n+\n+\tbt_pins: bt_pins {\n+\t\tbrcm,pins = \"-\"; // non-empty to keep btuart happy, //4 = 0\n+\t\t\t\t // to fool pinctrl\n+\t\tbrcm,function = <0>;\n+\t\tbrcm,pull = <2>;\n+\t};\n+\n+\tuart0_pins: uart0_pins {\n+\t\tbrcm,pins = <32 33>;\n+\t\tbrcm,function = <BCM2835_FSEL_ALT3>;\n+\t\tbrcm,pull = <0 2>;\n+\t};\n+\n+\tuart1_pins: uart1_pins {\n+\t\tbrcm,pins;\n+\t\tbrcm,function;\n+\t\tbrcm,pull;\n+\t};\n+\n+\tuart2_pins: uart2_pins {\n+\t\tbrcm,pins = <0 1>;\n+\t\tbrcm,function = <BCM2835_FSEL_ALT4>;\n+\t\tbrcm,pull = <0 2>;\n+\t};\n+\n+\tuart3_pins: uart3_pins {\n+\t\tbrcm,pins = <4 5>;\n+\t\tbrcm,function = <BCM2835_FSEL_ALT4>;\n+\t\tbrcm,pull = <0 2>;\n+\t};\n+\n+\tuart4_pins: uart4_pins {\n+\t\tbrcm,pins = <8 9>;\n+\t\tbrcm,function = <BCM2835_FSEL_ALT4>;\n+\t\tbrcm,pull = <0 2>;\n+\t};\n+\n+\tuart5_pins: uart5_pins {\n+\t\tbrcm,pins = <12 13>;\n+\t\tbrcm,function = <BCM2835_FSEL_ALT4>;\n+\t\tbrcm,pull = <0 2>;\n+\t};\n+};\n+\n+&i2c0if {\n+\tclock-frequency = <100000>;\n+};\n+\n+&i2c1 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&i2c1_pins>;\n+\tclock-frequency = <100000>;\n+};\n+\n+&i2s {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&i2s_pins>;\n+};\n+\n+/ {\n+\t__overrides__ {\n+\t\t/delete-property/ i2c2_baudrate;\n+\t\t/delete-property/ i2c2_iknowwhatimdoing;\n+\t};\n+};\n+\n+// =============================================\n+// Board specific stuff here\n+\n+&pcie0 {\n+       brcm,enable-l1ss;\n+};\n+\n+&sdhost {\n+\tstatus = \"disabled\";\n+};\n+\n+&phy1 {\n+\tled-modes = <0x00 0x08>; /* link/activity link */\n+};\n+\n+&gpio {\n+\taudio_pins: audio_pins {\n+\t\tbrcm,pins = <40 41>;\n+\t\tbrcm,function = <4>;\n+\t};\n+};\n+\n+&leds {\n+\tact_led: act {\n+\t\tlabel = \"led0\";\n+\t\tlinux,default-trigger = \"mmc0\";\n+\t\tgpios = <&gpio 42 GPIO_ACTIVE_HIGH>;\n+\t};\n+\n+\tpwr_led: pwr {\n+\t\tlabel = \"led1\";\n+\t\tlinux,default-trigger = \"default-on\";\n+\t\tgpios = <&expgpio 2 GPIO_ACTIVE_LOW>;\n+\t};\n+};\n+\n+&pwm1 {\n+\tstatus = \"disabled\";\n+};\n+\n+&audio {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&audio_pins>;\n+};\n+\n+/ {\n+\t__overrides__ {\n+\t\tact_led_gpio = <&act_led>,\"gpios:4\";\n+\t\tact_led_activelow = <&act_led>,\"gpios:8\";\n+\t\tact_led_trigger = <&act_led>,\"linux,default-trigger\";\n+\n+\t\tpwr_led_gpio = <&pwr_led>,\"gpios:4\";\n+\t\tpwr_led_activelow = <&pwr_led>,\"gpios:8\";\n+\t\tpwr_led_trigger = <&pwr_led>,\"linux,default-trigger\";\n+\n+\t\teth_led0 = <&phy1>,\"led-modes:0\";\n+\t\teth_led1 = <&phy1>,\"led-modes:4\";\n+\n+\t\tant1 =  <&ant1>,\"output-high?=on\",\n+\t\t\t<&ant1>, \"output-low?=off\",\n+\t\t\t<&ant2>, \"output-high?=off\",\n+\t\t\t<&ant2>, \"output-low?=on\";\n+\t\tant2 =  <&ant1>,\"output-high?=off\",\n+\t\t\t<&ant1>, \"output-low?=on\",\n+\t\t\t<&ant2>, \"output-high?=on\",\n+\t\t\t<&ant2>, \"output-low?=off\";\n+\t\tnoant = <&ant1>,\"output-high?=off\",\n+\t\t\t<&ant1>, \"output-low?=on\",\n+\t\t\t<&ant2>, \"output-high?=off\",\n+\t\t\t<&ant2>, \"output-low?=on\";\n+\n+\t\tsd_poll_once = <&emmc2>, \"non-removable?\";\n+\t\tspi_dma4 = <&spi0>, \"dmas:0=\", <&dma40>,\n+\t\t\t   <&spi0>, \"dmas:8=\", <&dma40>;\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/bcm2711-rpi.dtsi b/arch/arm/boot/dts/bcm2711-rpi.dtsi\nnew file mode 100644\nindex 000000000000..4f903a787d65\n--- /dev/null\n+++ b/arch/arm/boot/dts/bcm2711-rpi.dtsi\n@@ -0,0 +1,201 @@\n+// SPDX-License-Identifier: GPL-2.0\n+#include \"bcm270x-rpi.dtsi\"\n+\n+/ {\n+\t__overrides__ {\n+\t\tarm_freq;\n+\t};\n+\n+\tv3dbus: v3dbus {\n+\t\tcompatible = \"simple-bus\";\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <2>;\n+\t\tranges = <0x7c500000  0x0 0xfc500000  0x0 0x03300000>,\n+\t\t\t <0x40000000  0x0 0xff800000  0x0 0x00800000>;\n+\t\tdma-ranges = <0x00000000  0x0 0x00000000  0x4 0x00000000>;\n+\n+\t\tv3d: v3d@7ec04000 {\n+\t\t\tcompatible = \"brcm,2711-v3d\";\n+\t\t\treg =\n+\t\t\t    <0x7ec00000  0x0 0x4000>,\n+\t\t\t    <0x7ec04000  0x0 0x4000>;\n+\t\t\treg-names = \"hub\", \"core0\";\n+\n+\t\t\tpower-domains = <&pm BCM2835_POWER_DOMAIN_GRAFX_V3D>;\n+\t\t\tresets = <&pm BCM2835_RESET_V3D>;\n+\t\t\tclocks = <&firmware_clocks 5>;\n+\t\t\tclocks-names = \"v3d\";\n+\t\t\tinterrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\tscb: scb {\n+\t     /* Add a label */\n+\t};\n+};\n+\n+&cma {\n+\t/* Limit cma to the lower 768MB to allow room for HIGHMEM on 32-bit */\n+\talloc-ranges = <0x0 0x00000000 0x30000000>;\n+};\n+\n+&scb {\n+\tranges = <0x0 0x7c000000  0x0 0xfc000000  0x0 0x03800000>,\n+\t\t <0x0 0x40000000  0x0 0xff800000  0x0 0x00800000>,\n+\t\t <0x6 0x00000000  0x6 0x00000000  0x0 0x40000000>,\n+\t\t <0x0 0x00000000  0x0 0x00000000  0x0 0xfc000000>;\n+\tdma-ranges = <0x0 0x00000000  0x0 0x00000000  0x4 0x00000000>;\n+\n+\tdma40: dma@7e007b00 {\n+\t\tcompatible = \"brcm,bcm2711-dma\";\n+\t\treg = <0x0 0x7e007b00  0x0 0x400>;\n+\t\tinterrupts =\n+\t\t\t<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, /* dma4 11 */\n+\t\t\t<GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, /* dma4 12 */\n+\t\t\t<GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, /* dma4 13 */\n+\t\t\t<GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; /* dma4 14 */\n+\t\tinterrupt-names = \"dma11\",\n+\t\t\t\"dma12\",\n+\t\t\t\"dma13\",\n+\t\t\t\"dma14\";\n+\t\t#dma-cells = <1>;\n+\t\tbrcm,dma-channel-mask = <0x7800>;\n+\t};\n+\n+\txhci: xhci@7e9c0000 {\n+\t\tcompatible = \"generic-xhci\";\n+\t\tstatus = \"disabled\";\n+\t\treg = <0x0 0x7e9c0000  0x0 0x100000>;\n+\t\tinterrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;\n+\t\tpower-domains = <&power RPI_POWER_DOMAIN_USB>;\n+\t};\n+\n+\thevc-decoder@7eb00000 {\n+\t\tcompatible = \"raspberrypi,rpivid-hevc-decoder\";\n+\t\treg = <0x0 0x7eb00000  0x0 0x10000>;\n+\t\tstatus = \"okay\";\n+\t};\n+\n+\trpivid-local-intc@7eb10000 {\n+\t\tcompatible = \"raspberrypi,rpivid-local-intc\";\n+\t\treg = <0x0 0x7eb10000  0x0 0x1000>;\n+\t\tstatus = \"okay\";\n+\t\tinterrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;\n+\t};\n+\n+\th264-decoder@7eb20000 {\n+\t\tcompatible = \"raspberrypi,rpivid-h264-decoder\";\n+\t\treg = <0x0 0x7eb20000  0x0 0x10000>;\n+\t\tstatus = \"okay\";\n+\t};\n+\n+\tvp9-decoder@7eb30000 {\n+\t\tcompatible = \"raspberrypi,rpivid-vp9-decoder\";\n+\t\treg = <0x0 0x7eb30000  0x0 0x10000>;\n+\t\tstatus = \"okay\";\n+\t};\n+};\n+\n+&dma40 {\n+\t/* The VPU firmware uses DMA channel 11 for VCHIQ */\n+\tbrcm,dma-channel-mask = <0x7000>;\n+};\n+\n+&vchiq {\n+\tcompatible = \"brcm,bcm2711-vchiq\";\n+};\n+\n+&firmwarekms {\n+\tcompatible = \"raspberrypi,rpi-firmware-kms-2711\";\n+\tinterrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;\n+};\n+\n+&smi {\n+\tinterrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;\n+};\n+\n+&mmc {\n+\tinterrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;\n+};\n+\n+&mmcnr {\n+\tinterrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;\n+};\n+\n+&csi0 {\n+\tinterrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;\n+};\n+\n+&csi1 {\n+\tinterrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;\n+};\n+\n+&random {\n+\tcompatible = \"brcm,bcm2711-rng200\";\n+\tstatus = \"okay\";\n+};\n+\n+&usb {\n+\t/* Enable the FIQ support */\n+\treg = <0x7e980000 0x10000>,\n+\t      <0x7e00b200 0x200>;\n+\tinterrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t     <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;\n+\tstatus = \"disabled\";\n+};\n+\n+&gpio {\n+\tinterrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t     <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;\n+};\n+\n+&emmc2 {\n+\tmmc-ddr-3_3v;\n+};\n+\n+&vc4 {\n+\tstatus = \"disabled\";\n+};\n+\n+&pixelvalve0 {\n+\tstatus = \"disabled\";\n+};\n+\n+&pixelvalve1 {\n+\tstatus = \"disabled\";\n+};\n+\n+&pixelvalve2 {\n+\tstatus = \"disabled\";\n+};\n+\n+&pixelvalve3 {\n+\tstatus = \"disabled\";\n+};\n+\n+&pixelvalve4 {\n+\tstatus = \"disabled\";\n+};\n+\n+&hdmi0 {\n+\tdmas = <&dma (10|(1<<27))>;\n+\tstatus = \"disabled\";\n+};\n+\n+&ddc0 {\n+\tstatus = \"disabled\";\n+};\n+\n+&hdmi1 {\n+\tdmas = <&dma (17|(1<<27))>;\n+\tstatus = \"disabled\";\n+};\n+\n+&ddc1 {\n+\tstatus = \"disabled\";\n+};\n+\n+&dvp {\n+\tstatus = \"disabled\";\n+};\ndiff --git a/arch/arm/boot/dts/bcm2711.dtsi b/arch/arm/boot/dts/bcm2711.dtsi\nindex 3d040f6e2a20..6e0339266027 100644\n--- a/arch/arm/boot/dts/bcm2711.dtsi\n+++ b/arch/arm/boot/dts/bcm2711.dtsi\n@@ -318,7 +318,8 @@ hdmi0: hdmi@7ef00700 {\n \t\t\t      <0x7ef01f00 0x400>,\n \t\t\t      <0x7ef00200 0x80>,\n \t\t\t      <0x7ef04300 0x100>,\n-\t\t\t      <0x7ef20000 0x100>;\n+\t\t\t      <0x7ef20000 0x100>,\n+\t\t\t      <0x7ef00100 0x30>;\n \t\t\treg-names = \"hdmi\",\n \t\t\t\t    \"dvp\",\n \t\t\t\t    \"phy\",\n@@ -327,12 +328,18 @@ hdmi0: hdmi@7ef00700 {\n \t\t\t\t    \"metadata\",\n \t\t\t\t    \"csc\",\n \t\t\t\t    \"cec\",\n-\t\t\t\t    \"hd\";\n+\t\t\t\t    \"hd\",\n+\t\t\t\t    \"intr2\";\n+\t\t\tclocks = <&firmware_clocks 13>,\n+\t\t\t\t <&firmware_clocks 14>,\n+\t\t\t\t <&dvp 0>,\n+\t\t\t\t <&clk_27MHz>;\n \t\t\tclock-names = \"hdmi\", \"bvb\", \"audio\", \"cec\";\n \t\t\tresets = <&dvp 0>;\n \t\t\tddc = <&ddc0>;\n \t\t\tdmas = <&dma 10>;\n \t\t\tdma-names = \"audio-rx\";\n+\t\t\tinterrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;\n \t\t\tstatus = \"disabled\";\n \t\t};\n \n@@ -354,7 +361,8 @@ hdmi1: hdmi@7ef05700 {\n \t\t\t      <0x7ef06f00 0x400>,\n \t\t\t      <0x7ef00280 0x80>,\n \t\t\t      <0x7ef09300 0x100>,\n-\t\t\t      <0x7ef20000 0x100>;\n+\t\t\t      <0x7ef20000 0x100>,\n+\t\t\t      <0x7ef00100 0x30>;\n \t\t\treg-names = \"hdmi\",\n \t\t\t\t    \"dvp\",\n \t\t\t\t    \"phy\",\n@@ -363,12 +371,18 @@ hdmi1: hdmi@7ef05700 {\n \t\t\t\t    \"metadata\",\n \t\t\t\t    \"csc\",\n \t\t\t\t    \"cec\",\n-\t\t\t\t    \"hd\";\n+\t\t\t\t    \"hd\",\n+\t\t\t\t    \"intr2\";\n \t\t\tddc = <&ddc1>;\n \t\t\tclock-names = \"hdmi\", \"bvb\", \"audio\", \"cec\";\n+\t\t\tclocks = <&firmware_clocks 13>,\n+\t\t\t\t <&firmware_clocks 14>,\n+\t\t\t\t <&dvp 0>,\n+\t\t\t\t <&clk_27MHz>;\n \t\t\tresets = <&dvp 1>;\n \t\t\tdmas = <&dma 17>;\n \t\t\tdma-names = \"audio-rx\";\n+\t\t\tinterrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;\n \t\t\tstatus = \"disabled\";\n \t\t};\n \n@@ -468,14 +482,14 @@ cpu3: cpu@3 {\n \tscb {\n \t\tcompatible = \"simple-bus\";\n \t\t#address-cells = <2>;\n-\t\t#size-cells = <1>;\n+\t\t#size-cells = <2>;\n \n-\t\tranges = <0x0 0x7c000000  0x0 0xfc000000  0x03800000>,\n-\t\t\t <0x6 0x00000000  0x6 0x00000000  0x40000000>;\n+\t\tranges = <0x0 0x7c000000  0x0 0xfc000000  0x0 0x03800000>,\n+\t\t\t <0x6 0x00000000  0x6 0x00000000  0x0 0x40000000>;\n \n \t\tpcie0: pcie@7d500000 {\n \t\t\tcompatible = \"brcm,bcm2711-pcie\";\n-\t\t\treg = <0x0 0x7d500000 0x9310>;\n+\t\t\treg = <0x0 0x7d500000  0x0 0x9310>;\n \t\t\tdevice_type = \"pci\";\n \t\t\t#address-cells = <3>;\n \t\t\t#interrupt-cells = <1>;\n@@ -503,7 +517,7 @@ pcie0: pcie@7d500000 {\n \n \t\tgenet: ethernet@7d580000 {\n \t\t\tcompatible = \"brcm,bcm2711-genet-v5\";\n-\t\t\treg = <0x0 0x7d580000 0x10000>;\n+\t\t\treg = <0x0 0x7d580000  0x0 0x10000>;\n \t\t\t#address-cells = <0x1>;\n \t\t\t#size-cells = <0x1>;\n \t\t\tinterrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,\n@@ -1010,7 +1024,7 @@ &cma {\n \talloc-ranges = <0x0 0x00000000 0x40000000>;\n };\n \n-&i2c0 {\n+&i2c0if {\n \tcompatible = \"brcm,bcm2711-i2c\", \"brcm,bcm2835-i2c\";\n \tinterrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;\n };\ndiff --git a/arch/arm/boot/dts/bcm271x-rpi-bt.dtsi b/arch/arm/boot/dts/bcm271x-rpi-bt.dtsi\nnew file mode 100644\nindex 000000000000..6b9b79f74cf3\n--- /dev/null\n+++ b/arch/arm/boot/dts/bcm271x-rpi-bt.dtsi\n@@ -0,0 +1,26 @@\n+// SPDX-License-Identifier: GPL-2.0\n+\n+&uart0 {\n+\tbt: bluetooth {\n+\t\tcompatible = \"brcm,bcm43438-bt\";\n+\t\tmax-speed = <3000000>;\n+\t\tshutdown-gpios = <&expgpio 0 GPIO_ACTIVE_HIGH>;\n+\t\tstatus = \"disabled\";\n+\t};\n+};\n+\n+&uart1 {\n+\tminibt: bluetooth {\n+\t\tcompatible = \"brcm,bcm43438-bt\";\n+\t\tmax-speed = <460800>;\n+\t\tshutdown-gpios = <&expgpio 0 GPIO_ACTIVE_HIGH>;\n+\t\tstatus = \"disabled\";\n+\t};\n+};\n+\n+/ {\n+\t__overrides__ {\n+\t\tkrnbt = <&bt>,\"status\";\n+\t\tkrnbt_baudrate = <&bt>,\"max-speed:0\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/bcm2835-common.dtsi b/arch/arm/boot/dts/bcm2835-common.dtsi\nindex 4119271c979d..bd77ba3a3562 100644\n--- a/arch/arm/boot/dts/bcm2835-common.dtsi\n+++ b/arch/arm/boot/dts/bcm2835-common.dtsi\n@@ -116,12 +116,14 @@ hdmi: hdmi@7e902000 {\n \t\t\tcompatible = \"brcm,bcm2835-hdmi\";\n \t\t\treg = <0x7e902000 0x600>,\n \t\t\t      <0x7e808000 0x100>;\n+\t\t\treg-names = \"hdmi\",\n+\t\t\t\t    \"hd\";\n \t\t\tinterrupts = <2 8>, <2 9>;\n \t\t\tddc = <&i2c2>;\n \t\t\tclocks = <&clocks BCM2835_PLLH_PIX>,\n \t\t\t\t <&clocks BCM2835_CLOCK_HSM>;\n \t\t\tclock-names = \"pixel\", \"hdmi\";\n-\t\t\tdmas = <&dma 17>;\n+\t\t\tdmas = <&dma (17|(1<<27))>;\n \t\t\tdma-names = \"audio-rx\";\n \t\t\tstatus = \"disabled\";\n \t\t};\ndiff --git a/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts b/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts\nindex 40b9405f1a8e..d2384d8e8555 100644\n--- a/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts\n+++ b/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts\n@@ -126,3 +126,8 @@ &uart0 {\n \tpinctrl-0 = <&uart0_gpio14>;\n \tstatus = \"okay\";\n };\n+\n+/* i2c on camera/display connector is gpio 28&29 */\n+&i2c0mux {\n+\tpinctrl-1 = <&i2c0_gpio28>;\n+};\ndiff --git a/arch/arm/boot/dts/bcm2835-rpi-a.dts b/arch/arm/boot/dts/bcm2835-rpi-a.dts\nindex 11edb581dbaf..4ceca674b752 100644\n--- a/arch/arm/boot/dts/bcm2835-rpi-a.dts\n+++ b/arch/arm/boot/dts/bcm2835-rpi-a.dts\n@@ -121,3 +121,10 @@ &uart0 {\n \tpinctrl-0 = <&uart0_gpio14>;\n \tstatus = \"okay\";\n };\n+\n+/* i2c0 on camera/display connector is gpio 0&1. Not exposed on header.\n+ * To avoid having to remap everything, map both ports to gpios 0&1\n+ */\n+&i2c0mux {\n+\tpinctrl-1 = <&i2c0_gpio0>;\n+};\ndiff --git a/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts b/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts\nindex 1b435c64bd9c..8f2d10d82fa1 100644\n--- a/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts\n+++ b/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts\n@@ -128,3 +128,8 @@ &uart0 {\n \tpinctrl-0 = <&uart0_gpio14>;\n \tstatus = \"okay\";\n };\n+\n+/* i2c on camera/display connector is gpio 28&29 */\n+&i2c0mux {\n+\tpinctrl-1 = <&i2c0_gpio28>;\n+};\ndiff --git a/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts b/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts\nindex a23c25c00eea..547c88a3ae9f 100644\n--- a/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts\n+++ b/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts\n@@ -121,3 +121,10 @@ &uart0 {\n \tpinctrl-0 = <&uart0_gpio14>;\n \tstatus = \"okay\";\n };\n+\n+/* i2c0 on camera/display connector is gpio 0&1. Not exposed on header.\n+ * To avoid having to remap everything, map both ports to gpios 0&1\n+ */\n+&i2c0mux {\n+\tpinctrl-1 = <&i2c0_gpio0>;\n+};\ndiff --git a/arch/arm/boot/dts/bcm2835-rpi-b.dts b/arch/arm/boot/dts/bcm2835-rpi-b.dts\nindex 1b63d6b19750..073fc99ef8a2 100644\n--- a/arch/arm/boot/dts/bcm2835-rpi-b.dts\n+++ b/arch/arm/boot/dts/bcm2835-rpi-b.dts\n@@ -116,3 +116,10 @@ &uart0 {\n \tpinctrl-0 = <&uart0_gpio14>;\n \tstatus = \"okay\";\n };\n+\n+/* camera/display connector use BSC1 on GPIOS 2&3.\n+ * To avoid having to remap everything, map both ports to gpios 0&1\n+ */\n+&i2c0mux {\n+\tpinctrl-1 = <&i2c0_gpio0>;\n+};\ndiff --git a/arch/arm/boot/dts/bcm2835-rpi-cm1-io1.dts b/arch/arm/boot/dts/bcm2835-rpi-cm1-io1.dts\nindex a75c882e6575..95564c93a645 100644\n--- a/arch/arm/boot/dts/bcm2835-rpi-cm1-io1.dts\n+++ b/arch/arm/boot/dts/bcm2835-rpi-cm1-io1.dts\n@@ -95,3 +95,8 @@ &uart0 {\n \tpinctrl-0 = <&uart0_gpio14>;\n \tstatus = \"okay\";\n };\n+\n+/* WHAT TO DO HERE? */\n+&i2c0mux {\n+\tpinctrl-1 = <&i2c0_gpio28>;\n+};\ndiff --git a/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts b/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts\nindex 33b2b77aa47d..3ea5c7e6be54 100644\n--- a/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts\n+++ b/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts\n@@ -149,3 +149,8 @@ &uart1 {\n \tpinctrl-0 = <&uart1_gpio14>;\n \tstatus = \"okay\";\n };\n+\n+/* i2c on camera/display connector is gpio 28&29 */\n+&i2c0mux {\n+\tpinctrl-1 = <&i2c0_gpio28>;\n+};\ndiff --git a/arch/arm/boot/dts/bcm2835-rpi-zero.dts b/arch/arm/boot/dts/bcm2835-rpi-zero.dts\nindex 6f9b3a908f28..a0eabab12c99 100644\n--- a/arch/arm/boot/dts/bcm2835-rpi-zero.dts\n+++ b/arch/arm/boot/dts/bcm2835-rpi-zero.dts\n@@ -117,3 +117,8 @@ &uart0 {\n \tpinctrl-0 = <&uart0_gpio14>;\n \tstatus = \"okay\";\n };\n+\n+/* i2c on camera/display connector is gpio 28&29 */\n+&i2c0mux {\n+\tpinctrl-1 = <&i2c0_gpio28>;\n+};\ndiff --git a/arch/arm/boot/dts/bcm2835-rpi.dtsi b/arch/arm/boot/dts/bcm2835-rpi.dtsi\nindex 87ddcad76083..1b16cb9ccb88 100644\n--- a/arch/arm/boot/dts/bcm2835-rpi.dtsi\n+++ b/arch/arm/boot/dts/bcm2835-rpi.dtsi\n@@ -19,6 +19,11 @@ firmware: firmware {\n \n \t\t\tmboxes = <&mailbox>;\n \t\t\tdma-ranges;\n+\n+\t\t\tfirmware_clocks: clocks {\n+\t\t\t\tcompatible = \"raspberrypi,firmware-clocks\";\n+\t\t\t\t#clock-cells = <1>;\n+\t\t\t};\n \t\t};\n \n \t\tpower: power {\n@@ -49,13 +54,17 @@ alt0: alt0 {\n \t};\n };\n \n-&i2c0 {\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&i2c0_gpio0>;\n+&i2c0if {\n \tstatus = \"okay\";\n \tclock-frequency = <100000>;\n };\n \n+&i2c0mux {\n+\tpinctrl-0 = <&i2c0_gpio0>;\n+\t/* pinctrl-1 varies based on platform */\n+\tstatus = \"okay\";\n+};\n+\n &i2c1 {\n \tpinctrl-names = \"default\";\n \tpinctrl-0 = <&i2c1_gpio2>;\ndiff --git a/arch/arm/boot/dts/bcm2835.dtsi b/arch/arm/boot/dts/bcm2835.dtsi\nindex 0549686134ea..2ea891228ea0 100644\n--- a/arch/arm/boot/dts/bcm2835.dtsi\n+++ b/arch/arm/boot/dts/bcm2835.dtsi\n@@ -19,7 +19,7 @@ cpu@0 {\n \n \tsoc {\n \t\tranges = <0x7e000000 0x20000000 0x02000000>;\n-\t\tdma-ranges = <0x40000000 0x00000000 0x20000000>;\n+\t\tdma-ranges = <0x80000000 0x00000000 0x20000000>;\n \t};\n \n \tarm-pmu {\ndiff --git a/arch/arm/boot/dts/bcm2836-rpi-2-b.dts b/arch/arm/boot/dts/bcm2836-rpi-2-b.dts\nindex d8af8eeac7b6..bf22b74359d8 100644\n--- a/arch/arm/boot/dts/bcm2836-rpi-2-b.dts\n+++ b/arch/arm/boot/dts/bcm2836-rpi-2-b.dts\n@@ -128,3 +128,8 @@ &uart0 {\n \tpinctrl-0 = <&uart0_gpio14>;\n \tstatus = \"okay\";\n };\n+\n+/* i2c on camera/display connector is gpio 28&29 */\n+&i2c0mux {\n+\tpinctrl-1 = <&i2c0_gpio28>;\n+};\ndiff --git a/arch/arm/boot/dts/bcm2837-rpi-3-a-plus.dts b/arch/arm/boot/dts/bcm2837-rpi-3-a-plus.dts\nindex 77099a7871b0..9529c0475673 100644\n--- a/arch/arm/boot/dts/bcm2837-rpi-3-a-plus.dts\n+++ b/arch/arm/boot/dts/bcm2837-rpi-3-a-plus.dts\n@@ -178,3 +178,8 @@ &uart1 {\n \tpinctrl-0 = <&uart1_gpio14>;\n \tstatus = \"okay\";\n };\n+\n+/* i2c on camera/display connector is gpio 44&45 */\n+&i2c0mux {\n+\tpinctrl-1 = <&i2c0_gpio44>;\n+};\ndiff --git a/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts b/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts\nindex 61010266ca9a..40cb269aed0f 100644\n--- a/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts\n+++ b/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts\n@@ -181,3 +181,8 @@ &uart1 {\n \tpinctrl-0 = <&uart1_gpio14>;\n \tstatus = \"okay\";\n };\n+\n+/* i2c on camera/display connector is gpio 44&45 */\n+&i2c0mux {\n+\tpinctrl-1 = <&i2c0_gpio44>;\n+};\ndiff --git a/arch/arm/boot/dts/bcm2837-rpi-3-b.dts b/arch/arm/boot/dts/bcm2837-rpi-3-b.dts\nindex dd4a48604097..8f16b6b3fe08 100644\n--- a/arch/arm/boot/dts/bcm2837-rpi-3-b.dts\n+++ b/arch/arm/boot/dts/bcm2837-rpi-3-b.dts\n@@ -174,3 +174,8 @@ &sdhost {\n \tstatus = \"okay\";\n \tbus-width = <4>;\n };\n+\n+/* i2c on camera/display connector is gpio 44&45 */\n+&i2c0mux {\n+\tpinctrl-1 = <&i2c0_gpio44>;\n+};\ndiff --git a/arch/arm/boot/dts/bcm2837-rpi-cm3-io3.dts b/arch/arm/boot/dts/bcm2837-rpi-cm3-io3.dts\nindex 588d9411ceb6..dde209ade51b 100644\n--- a/arch/arm/boot/dts/bcm2837-rpi-cm3-io3.dts\n+++ b/arch/arm/boot/dts/bcm2837-rpi-cm3-io3.dts\n@@ -94,3 +94,8 @@ &uart0 {\n \tpinctrl-0 = <&uart0_gpio14>;\n \tstatus = \"okay\";\n };\n+\n+/* WHAT TO DO HERE? */\n+&i2c0mux {\n+\tpinctrl-1 = <&i2c0_gpio28>;\n+};\ndiff --git a/arch/arm/boot/dts/bcm283x-rpi-csi0-2lane.dtsi b/arch/arm/boot/dts/bcm283x-rpi-csi0-2lane.dtsi\nnew file mode 100644\nindex 000000000000..6e4ce8622b47\n--- /dev/null\n+++ b/arch/arm/boot/dts/bcm283x-rpi-csi0-2lane.dtsi\n@@ -0,0 +1,4 @@\n+// SPDX-License-Identifier: GPL-2.0-only\n+&csi0 {\n+\tbrcm,num-data-lanes = <2>;\n+};\ndiff --git a/arch/arm/boot/dts/bcm283x-rpi-csi1-2lane.dtsi b/arch/arm/boot/dts/bcm283x-rpi-csi1-2lane.dtsi\nnew file mode 100644\nindex 000000000000..6938f4daacdc\n--- /dev/null\n+++ b/arch/arm/boot/dts/bcm283x-rpi-csi1-2lane.dtsi\n@@ -0,0 +1,4 @@\n+// SPDX-License-Identifier: GPL-2.0-only\n+&csi1 {\n+\tbrcm,num-data-lanes = <2>;\n+};\ndiff --git a/arch/arm/boot/dts/bcm283x-rpi-csi1-4lane.dtsi b/arch/arm/boot/dts/bcm283x-rpi-csi1-4lane.dtsi\nnew file mode 100644\nindex 000000000000..b37037437bee\n--- /dev/null\n+++ b/arch/arm/boot/dts/bcm283x-rpi-csi1-4lane.dtsi\n@@ -0,0 +1,4 @@\n+// SPDX-License-Identifier: GPL-2.0-only\n+&csi1 {\n+\tbrcm,num-data-lanes = <4>;\n+};\ndiff --git a/arch/arm/boot/dts/bcm283x-rpi-i2c0mux_0_28.dtsi b/arch/arm/boot/dts/bcm283x-rpi-i2c0mux_0_28.dtsi\nnew file mode 100644\nindex 000000000000..38f0074bce3f\n--- /dev/null\n+++ b/arch/arm/boot/dts/bcm283x-rpi-i2c0mux_0_28.dtsi\n@@ -0,0 +1,4 @@\n+&i2c0mux {\n+\tpinctrl-0 = <&i2c0_gpio0>;\n+\tpinctrl-1 = <&i2c0_gpio28>;\n+};\ndiff --git a/arch/arm/boot/dts/bcm283x-rpi-i2c0mux_0_44.dtsi b/arch/arm/boot/dts/bcm283x-rpi-i2c0mux_0_44.dtsi\nnew file mode 100644\nindex 000000000000..119946d878db\n--- /dev/null\n+++ b/arch/arm/boot/dts/bcm283x-rpi-i2c0mux_0_44.dtsi\n@@ -0,0 +1,4 @@\n+&i2c0mux {\n+\tpinctrl-0 = <&i2c0_gpio0>;\n+\tpinctrl-1 = <&i2c0_gpio44>;\n+};\ndiff --git a/arch/arm/boot/dts/bcm283x-rpi-usb-peripheral.dtsi b/arch/arm/boot/dts/bcm283x-rpi-usb-peripheral.dtsi\ndeleted file mode 100644\nindex 0ff0e9e25327..000000000000\n--- a/arch/arm/boot/dts/bcm283x-rpi-usb-peripheral.dtsi\n+++ /dev/null\n@@ -1,7 +0,0 @@\n-// SPDX-License-Identifier: GPL-2.0\n-&usb {\n-\tdr_mode = \"peripheral\";\n-\tg-rx-fifo-size = <256>;\n-\tg-np-tx-fifo-size = <32>;\n-\tg-tx-fifo-size = <256 256 512 512 512 768 768>;\n-};\ndiff --git a/arch/arm/boot/dts/bcm283x.dtsi b/arch/arm/boot/dts/bcm283x.dtsi\nindex 0f3be55201a5..6d305b8b5ebe 100644\n--- a/arch/arm/boot/dts/bcm283x.dtsi\n+++ b/arch/arm/boot/dts/bcm283x.dtsi\n@@ -334,7 +334,7 @@ spi: spi@7e204000 {\n \t\t\tstatus = \"disabled\";\n \t\t};\n \n-\t\ti2c0: i2c@7e205000 {\n+\t\ti2c0if: i2c@7e205000 {\n \t\t\tcompatible = \"brcm,bcm2835-i2c\";\n \t\t\treg = <0x7e205000 0x200>;\n \t\t\tinterrupts = <2 21>;\n@@ -344,6 +344,30 @@ i2c0: i2c@7e205000 {\n \t\t\tstatus = \"disabled\";\n \t\t};\n \n+\t\ti2c0mux: i2c0mux {\n+\t\t\tcompatible = \"i2c-mux-pinctrl\";\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\ti2c-parent = <&i2c0if>;\n+\n+\t\t\tpinctrl-names = \"i2c0\", \"i2c_csi_dsi\";\n+\n+\t\t\tstatus = \"disabled\";\n+\n+\t\t\ti2c0: i2c@0 {\n+\t\t\t\treg = <0>;\n+\t\t\t\t#address-cells = <1>;\n+\t\t\t\t#size-cells = <0>;\n+\t\t\t};\n+\n+\t\t\ti2c_csi_dsi: i2c@1 {\n+\t\t\t\treg = <1>;\n+\t\t\t\t#address-cells = <1>;\n+\t\t\t\t#size-cells = <0>;\n+\t\t\t};\n+\t\t};\n+\n \t\tdpi: dpi@7e208000 {\n \t\t\tcompatible = \"brcm,bcm2835-dpi\";\n \t\t\treg = <0x7e208000 0x8c>;\ndiff --git a/arch/arm/boot/dts/overlays/Makefile b/arch/arm/boot/dts/overlays/Makefile\nnew file mode 100644\nindex 000000000000..b30568e29526\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/Makefile\n@@ -0,0 +1,216 @@\n+# Overlays for the Raspberry Pi platform\n+\n+dtb-$(CONFIG_ARCH_BCM2835) += overlay_map.dtb\n+\n+dtbo-$(CONFIG_ARCH_BCM2835) += \\\n+\tact-led.dtbo \\\n+\tadafruit18.dtbo \\\n+\tadau1977-adc.dtbo \\\n+\tadau7002-simple.dtbo \\\n+\tads1015.dtbo \\\n+\tads1115.dtbo \\\n+\tads7846.dtbo \\\n+\tadv7282m.dtbo \\\n+\tadv728x-m.dtbo \\\n+\takkordion-iqdacplus.dtbo \\\n+\tallo-boss-dac-pcm512x-audio.dtbo \\\n+\tallo-digione.dtbo \\\n+\tallo-katana-dac-audio.dtbo \\\n+\tallo-piano-dac-pcm512x-audio.dtbo \\\n+\tallo-piano-dac-plus-pcm512x-audio.dtbo \\\n+\tanyspi.dtbo \\\n+\tapds9960.dtbo \\\n+\tapplepi-dac.dtbo \\\n+\tat86rf233.dtbo \\\n+\taudioinjector-addons.dtbo \\\n+\taudioinjector-isolated-soundcard.dtbo \\\n+\taudioinjector-ultra.dtbo \\\n+\taudioinjector-wm8731-audio.dtbo \\\n+\taudiosense-pi.dtbo \\\n+\taudremap.dtbo \\\n+\tbalena-fin.dtbo \\\n+\tcma.dtbo \\\n+\tdht11.dtbo \\\n+\tdionaudio-loco.dtbo \\\n+\tdionaudio-loco-v2.dtbo \\\n+\tdisable-bt.dtbo \\\n+\tdisable-wifi.dtbo \\\n+\tdpi18.dtbo \\\n+\tdpi24.dtbo \\\n+\tdraws.dtbo \\\n+\tdwc-otg.dtbo \\\n+\tdwc2.dtbo \\\n+\tenc28j60.dtbo \\\n+\tenc28j60-spi2.dtbo \\\n+\texc3000.dtbo \\\n+\tfe-pi-audio.dtbo \\\n+\tfsm-demo.dtbo \\\n+\tghost-amp.dtbo \\\n+\tgoodix.dtbo \\\n+\tgooglevoicehat-soundcard.dtbo \\\n+\tgpio-fan.dtbo \\\n+\tgpio-ir.dtbo \\\n+\tgpio-ir-tx.dtbo \\\n+\tgpio-key.dtbo \\\n+\tgpio-no-bank0-irq.dtbo \\\n+\tgpio-no-irq.dtbo \\\n+\tgpio-poweroff.dtbo \\\n+\tgpio-shutdown.dtbo \\\n+\thd44780-lcd.dtbo \\\n+\thdmi-backlight-hwhack-gpio.dtbo \\\n+\thifiberry-amp.dtbo \\\n+\thifiberry-dac.dtbo \\\n+\thifiberry-dacplus.dtbo \\\n+\thifiberry-dacplusadc.dtbo \\\n+\thifiberry-dacplusadcpro.dtbo \\\n+\thifiberry-dacplusdsp.dtbo \\\n+\thifiberry-dacplushd.dtbo \\\n+\thifiberry-digi.dtbo \\\n+\thifiberry-digi-pro.dtbo \\\n+\thighperi.dtbo \\\n+\thy28a.dtbo \\\n+\thy28b.dtbo \\\n+\thy28b-2017.dtbo \\\n+\ti-sabre-q2m.dtbo \\\n+\ti2c-bcm2708.dtbo \\\n+\ti2c-gpio.dtbo \\\n+\ti2c-mux.dtbo \\\n+\ti2c-pwm-pca9685a.dtbo \\\n+\ti2c-rtc.dtbo \\\n+\ti2c-rtc-gpio.dtbo \\\n+\ti2c-sensor.dtbo \\\n+\ti2c0.dtbo \\\n+\ti2c1.dtbo \\\n+\ti2c3.dtbo \\\n+\ti2c4.dtbo \\\n+\ti2c5.dtbo \\\n+\ti2c6.dtbo \\\n+\ti2s-gpio28-31.dtbo \\\n+\tilitek251x.dtbo \\\n+\timx219.dtbo \\\n+\timx290.dtbo \\\n+\timx477.dtbo \\\n+\tiqaudio-codec.dtbo \\\n+\tiqaudio-dac.dtbo \\\n+\tiqaudio-dacplus.dtbo \\\n+\tiqaudio-digi-wm8804-audio.dtbo \\\n+\tirs1125.dtbo \\\n+\tjedec-spi-nor.dtbo \\\n+\tjustboom-both.dtbo \\\n+\tjustboom-dac.dtbo \\\n+\tjustboom-digi.dtbo \\\n+\tltc294x.dtbo \\\n+\tmax98357a.dtbo \\\n+\tmaxtherm.dtbo \\\n+\tmbed-dac.dtbo \\\n+\tmcp23017.dtbo \\\n+\tmcp23s17.dtbo \\\n+\tmcp2515-can0.dtbo \\\n+\tmcp2515-can1.dtbo \\\n+\tmcp3008.dtbo \\\n+\tmcp3202.dtbo \\\n+\tmcp342x.dtbo \\\n+\tmedia-center.dtbo \\\n+\tmerus-amp.dtbo \\\n+\tmidi-uart0.dtbo \\\n+\tmidi-uart1.dtbo \\\n+\tminiuart-bt.dtbo \\\n+\tmmc.dtbo \\\n+\tmpu6050.dtbo \\\n+\tmz61581.dtbo \\\n+\tov5647.dtbo \\\n+\tov7251.dtbo \\\n+\tov9281.dtbo \\\n+\tpapirus.dtbo \\\n+\tpca953x.dtbo \\\n+\tpibell.dtbo \\\n+\tpifacedigital.dtbo \\\n+\tpiglow.dtbo \\\n+\tpiscreen.dtbo \\\n+\tpiscreen2r.dtbo \\\n+\tpisound.dtbo \\\n+\tpitft22.dtbo \\\n+\tpitft28-capacitive.dtbo \\\n+\tpitft28-resistive.dtbo \\\n+\tpitft35-resistive.dtbo \\\n+\tpps-gpio.dtbo \\\n+\tpwm.dtbo \\\n+\tpwm-2chan.dtbo \\\n+\tpwm-ir-tx.dtbo \\\n+\tqca7000.dtbo \\\n+\trotary-encoder.dtbo \\\n+\trpi-backlight.dtbo \\\n+\trpi-cirrus-wm5102.dtbo \\\n+\trpi-dac.dtbo \\\n+\trpi-display.dtbo \\\n+\trpi-ft5406.dtbo \\\n+\trpi-poe.dtbo \\\n+\trpi-proto.dtbo \\\n+\trpi-sense.dtbo \\\n+\trpi-tv.dtbo \\\n+\trpivid-v4l2.dtbo \\\n+\trra-digidac1-wm8741-audio.dtbo \\\n+\tsainsmart18.dtbo \\\n+\tsc16is750-i2c.dtbo \\\n+\tsc16is752-i2c.dtbo \\\n+\tsc16is752-spi0.dtbo \\\n+\tsc16is752-spi1.dtbo \\\n+\tsdhost.dtbo \\\n+\tsdio.dtbo \\\n+\tsdtweak.dtbo \\\n+\tsh1106-spi.dtbo \\\n+\tsmi.dtbo \\\n+\tsmi-dev.dtbo \\\n+\tsmi-nand.dtbo \\\n+\tspi-gpio35-39.dtbo \\\n+\tspi-gpio40-45.dtbo \\\n+\tspi-rtc.dtbo \\\n+\tspi0-1cs.dtbo \\\n+\tspi0-2cs.dtbo \\\n+\tspi1-1cs.dtbo \\\n+\tspi1-2cs.dtbo \\\n+\tspi1-3cs.dtbo \\\n+\tspi2-1cs.dtbo \\\n+\tspi2-2cs.dtbo \\\n+\tspi2-3cs.dtbo \\\n+\tspi3-1cs.dtbo \\\n+\tspi3-2cs.dtbo \\\n+\tspi4-1cs.dtbo \\\n+\tspi4-2cs.dtbo \\\n+\tspi5-1cs.dtbo \\\n+\tspi5-2cs.dtbo \\\n+\tspi6-1cs.dtbo \\\n+\tspi6-2cs.dtbo \\\n+\tssd1306.dtbo \\\n+\tssd1306-spi.dtbo \\\n+\tssd1351-spi.dtbo \\\n+\tsuperaudioboard.dtbo \\\n+\tsx150x.dtbo \\\n+\ttc358743.dtbo \\\n+\ttc358743-audio.dtbo \\\n+\ttinylcd35.dtbo \\\n+\ttpm-slb9670.dtbo \\\n+\tuart0.dtbo \\\n+\tuart1.dtbo \\\n+\tuart2.dtbo \\\n+\tuart3.dtbo \\\n+\tuart4.dtbo \\\n+\tuart5.dtbo \\\n+\tudrc.dtbo \\\n+\tupstream.dtbo \\\n+\tupstream-pi4.dtbo \\\n+\tvc4-fkms-v3d.dtbo \\\n+\tvc4-kms-kippah-7inch.dtbo \\\n+\tvc4-kms-v3d.dtbo \\\n+\tvc4-kms-v3d-pi4.dtbo \\\n+\tvga666.dtbo \\\n+\tw1-gpio.dtbo \\\n+\tw1-gpio-pullup.dtbo \\\n+\tw5500.dtbo \\\n+\twittypi.dtbo\n+\n+targets += dtbs dtbs_install\n+targets += $(dtbo-y)\n+\n+always-y\t:= $(dtbo-y)\n+clean-files\t:= *.dtbo\ndiff --git a/arch/arm/boot/dts/overlays/README b/arch/arm/boot/dts/overlays/README\nnew file mode 100644\nindex 000000000000..eff90baed406\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/README\n@@ -0,0 +1,3040 @@\n+Introduction\n+============\n+\n+This directory contains Device Tree overlays. Device Tree makes it possible\n+to support many hardware configurations with a single kernel and without the\n+need to explicitly load or blacklist kernel modules. Note that this isn't a\n+\"pure\" Device Tree configuration (c.f. MACH_BCM2835) - some on-board devices\n+are still configured by the board support code, but the intention is to\n+eventually reach that goal.\n+\n+On Raspberry Pi, Device Tree usage is controlled from /boot/config.txt. By\n+default, the Raspberry Pi kernel boots with device tree enabled. You can\n+completely disable DT usage (for now) by adding:\n+\n+    device_tree=\n+\n+to your config.txt, which should cause your Pi to revert to the old way of\n+doing things after a reboot.\n+\n+In /boot you will find a .dtb for each base platform. This describes the\n+hardware that is part of the Raspberry Pi board. The loader (start.elf and its\n+siblings) selects the .dtb file appropriate for the platform by name, and reads\n+it into memory. At this point, all of the optional interfaces (i2c, i2s, spi)\n+are disabled, but they can be enabled using Device Tree parameters:\n+\n+    dtparam=i2c=on,i2s=on,spi=on\n+\n+However, this shouldn't be necessary in many use cases because loading an\n+overlay that requires one of those interfaces will cause it to be enabled\n+automatically, and it is advisable to only enable interfaces if they are\n+needed.\n+\n+Configuring additional, optional hardware is done using Device Tree overlays\n+(see below).\n+\n+GPIO numbering uses the hardware pin numbering scheme (aka BCM scheme) and\n+not the physical pin numbers.\n+\n+raspi-config\n+============\n+\n+The Advanced Options section of the raspi-config utility can enable and disable\n+Device Tree use, as well as toggling the I2C and SPI interfaces. Note that it\n+is possible to both enable an interface and blacklist the driver, if for some\n+reason you should want to defer the loading.\n+\n+Modules\n+=======\n+\n+As well as describing the hardware, Device Tree also gives enough information\n+to allow suitable driver modules to be located and loaded, with the corollary\n+that unneeded modules are not loaded. As a result it should be possible to\n+remove lines from /etc/modules, and /etc/modprobe.d/raspi-blacklist.conf can\n+have its contents deleted (or commented out).\n+\n+Using Overlays\n+==============\n+\n+Overlays are loaded using the \"dtoverlay\" config.txt setting. As an example,\n+consider I2C Real Time Clock drivers. In the pre-DT world these would be loaded\n+by writing a magic string comprising a device identifier and an I2C address to\n+a special file in /sys/class/i2c-adapter, having first loaded the driver for\n+the I2C interface and the RTC device - something like this:\n+\n+    modprobe i2c-bcm2835\n+    modprobe rtc-ds1307\n+    echo ds1307 0x68 > /sys/class/i2c-adapter/i2c-1/new_device\n+\n+With DT enabled, this becomes a line in config.txt:\n+\n+    dtoverlay=i2c-rtc,ds1307\n+\n+This causes the file /boot/overlays/i2c-rtc.dtbo to be loaded and a \"node\"\n+describing the DS1307 I2C device to be added to the Device Tree for the Pi. By\n+default it usees address 0x68, but this can be modified with an additional DT\n+parameter:\n+\n+    dtoverlay=i2c-rtc,ds1307,addr=0x68\n+\n+Parameters usually have default values, although certain parameters are\n+mandatory. See the list of overlays below for a description of the parameters\n+and their defaults.\n+\n+The Overlay and Parameter Reference\n+===================================\n+\n+N.B. When editing this file, please preserve the indentation levels to make it\n+simple to parse programmatically. NO HARD TABS.\n+\n+\n+Name:   <The base DTB>\n+Info:   Configures the base Raspberry Pi hardware\n+Load:   <loaded automatically>\n+Params:\n+        ant1                    Select antenna 1 (default). CM4 only.\n+\n+        ant2                    Select antenna 2. CM4 only.\n+\n+        noant                   Disable both antennas. CM4 only.\n+\n+        audio                   Set to \"on\" to enable the onboard ALSA audio\n+                                interface (default \"off\")\n+\n+        axiperf                 Set to \"on\" to enable the AXI bus performance\n+                                monitors.\n+                                See /sys/kernel/debug/raspberrypi_axi_monitor\n+                                for the results.\n+\n+        eee                     Enable Energy Efficient Ethernet support for\n+                                compatible devices (default \"on\"). See also\n+                                \"tx_lpi_timer\". Pi3B+ only.\n+\n+        eth_downshift_after     Set the number of auto-negotiation failures\n+                                after which the 1000Mbps modes are disabled.\n+                                Legal values are 2, 3, 4, 5 and 0, where\n+                                0 means never downshift (default 2). Pi3B+ only.\n+\n+        eth_led0                Set mode of LED0 - amber on Pi3B+ (default \"1\"),\n+                                green on Pi4 (default \"0\").\n+                                The legal values are:\n+\n+                                Pi3B+\n+\n+                                0=link/activity          1=link1000/activity\n+                                2=link100/activity       3=link10/activity\n+                                4=link100/1000/activity  5=link10/1000/activity\n+                                6=link10/100/activity    14=off    15=on\n+\n+                                Pi4\n+\n+                                0=Speed/Activity         1=Speed\n+                                2=Flash activity         3=FDX\n+                                4=Off                    5=On\n+                                6=Alt                    7=Speed/Flash\n+                                8=Link                   9=Activity\n+\n+        eth_led1                Set mode of LED1 - green on Pi3B+ (default \"6\"),\n+                                amber on Pi4 (default \"8\"). See eth_led0 for\n+                                legal values.\n+\n+        eth_max_speed           Set the maximum speed a link is allowed\n+                                to negotiate. Legal values are 10, 100 and\n+                                1000 (default 1000). Pi3B+ only.\n+\n+        i2c_arm                 Set to \"on\" to enable the ARM's i2c interface\n+                                (default \"off\")\n+\n+        i2c_vc                  Set to \"on\" to enable the i2c interface\n+                                usually reserved for the VideoCore processor\n+                                (default \"off\")\n+\n+        i2c                     An alias for i2c_arm\n+\n+        i2c_arm_baudrate        Set the baudrate of the ARM's i2c interface\n+                                (default \"100000\")\n+\n+        i2c_vc_baudrate         Set the baudrate of the VideoCore i2c interface\n+                                (default \"100000\")\n+\n+        i2c_baudrate            An alias for i2c_arm_baudrate\n+\n+        i2s                     Set to \"on\" to enable the i2s interface\n+                                (default \"off\")\n+\n+        krnbt                   Set to \"on\" to enable autoprobing of Bluetooth\n+                                driver without need of hciattach/btattach\n+                                (default \"off\")\n+\n+        krnbt_baudrate          Set the baudrate of the PL011 UART when used\n+                                with krnbt=on\n+\n+        spi                     Set to \"on\" to enable the spi interfaces\n+                                (default \"off\")\n+\n+        spi_dma4                Use to enable 40-bit DMA on spi interfaces\n+                                (the assigned value doesn't matter)\n+                                (2711 only)\n+\n+        random                  Set to \"on\" to enable the hardware random\n+                                number generator (default \"on\")\n+\n+        sd_overclock            Clock (in MHz) to use when the MMC framework\n+                                requests 50MHz\n+\n+        sd_poll_once            Looks for a card once after booting. Useful\n+                                for network booting scenarios to avoid the\n+                                overhead of continuous polling. N.B. Using\n+                                this option restricts the system to using a\n+                                single card per boot (or none at all).\n+                                (default off)\n+\n+        sd_force_pio            Disable DMA support for SD driver (default off)\n+\n+        sd_pio_limit            Number of blocks above which to use DMA for\n+                                SD card (default 1)\n+\n+        sd_debug                Enable debug output from SD driver (default off)\n+\n+        sdio_overclock          Clock (in MHz) to use when the MMC framework\n+                                requests 50MHz for the SDIO/WiFi interface.\n+\n+        tx_lpi_timer            Set the delay in microseconds between going idle\n+                                and entering the low power state (default 600).\n+                                Requires EEE to be enabled - see \"eee\".\n+\n+        uart0                   Set to \"off\" to disable uart0 (default \"on\")\n+\n+        uart1                   Set to \"on\" or \"off\" to enable or disable uart1\n+                                (default varies)\n+\n+        watchdog                Set to \"on\" to enable the hardware watchdog\n+                                (default \"off\")\n+\n+        act_led_trigger         Choose which activity the LED tracks.\n+                                Use \"heartbeat\" for a nice load indicator.\n+                                (default \"mmc\")\n+\n+        act_led_activelow       Set to \"on\" to invert the sense of the LED\n+                                (default \"off\")\n+                                N.B. For Pi 3B, 3B+, 3A+ and 4B, use the act-led\n+                                overlay.\n+\n+        act_led_gpio            Set which GPIO to use for the activity LED\n+                                (in case you want to connect it to an external\n+                                device)\n+                                (default \"16\" on a non-Plus board, \"47\" on a\n+                                Plus or Pi 2)\n+                                N.B. For Pi 3B, 3B+, 3A+ and 4B, use the act-led\n+                                overlay.\n+\n+        pwr_led_trigger\n+        pwr_led_activelow\n+        pwr_led_gpio\n+                                As for act_led_*, but using the PWR LED.\n+                                Not available on Model A/B boards.\n+\n+        N.B. It is recommended to only enable those interfaces that are needed.\n+        Leaving all interfaces enabled can lead to unwanted behaviour (i2c_vc\n+        interfering with Pi Camera, I2S and SPI hogging GPIO pins, etc.)\n+        Note also that i2c, i2c_arm and i2c_vc are aliases for the physical\n+        interfaces i2c0 and i2c1. Use of the numeric variants is still possible\n+        but deprecated because the ARM/VC assignments differ between board\n+        revisions. The same board-specific mapping applies to i2c_baudrate,\n+        and the other i2c baudrate parameters.\n+\n+\n+Name:   act-led\n+Info:   Pi 3B, 3B+, 3A+ and 4B use a GPIO expander to drive the LEDs which can\n+        only be accessed from the VPU. There is a special driver for this with a\n+        separate DT node, which has the unfortunate consequence of breaking the\n+        act_led_gpio and act_led_activelow dtparams.\n+        This overlay changes the GPIO controller back to the standard one and\n+        restores the dtparams.\n+Load:   dtoverlay=act-led,<param>=<val>\n+Params: activelow               Set to \"on\" to invert the sense of the LED\n+                                (default \"off\")\n+\n+        gpio                    Set which GPIO to use for the activity LED\n+                                (in case you want to connect it to an external\n+                                device)\n+                                REQUIRED\n+\n+\n+Name:   adafruit18\n+Info:   Overlay for the SPI-connected Adafruit 1.8\" display (based on the\n+        ST7735R chip). It includes support for the \"green tab\" version.\n+Load:   dtoverlay=adafruit18,<param>=<val>\n+Params: green                   Use the adafruit18_green variant.\n+        rotate                  Display rotation {0,90,180,270}\n+        speed                   SPI bus speed in Hz (default 4000000)\n+        fps                     Display frame rate in Hz\n+        bgr                     Enable BGR mode (default off)\n+        debug                   Debug output level {0-7}\n+        dc_pin                  GPIO pin for D/C (default 24)\n+        reset_pin               GPIO pin for RESET (default 25)\n+        led_pin                 GPIO used to control backlight (default 18)\n+\n+\n+Name:   adau1977-adc\n+Info:   Overlay for activation of ADAU1977 ADC codec over I2C for control\n+        and I2S for data.\n+Load:   dtoverlay=adau1977-adc\n+Params: <None>\n+\n+\n+Name:   adau7002-simple\n+Info:   Overlay for the activation of ADAU7002 stereo PDM to I2S converter.\n+Load:   dtoverlay=adau7002-simple,<param>=<val>\n+Params: card-name               Override the default, \"adau7002\", card name.\n+\n+\n+Name:   ads1015\n+Info:   Overlay for activation of Texas Instruments ADS1015 ADC over I2C\n+Load:   dtoverlay=ads1015,<param>=<val>\n+Params: addr                    I2C bus address of device. Set based on how the\n+                                addr pin is wired. (default=0x48 assumes addr\n+                                is pulled to GND)\n+        cha_enable              Enable virtual channel a. (default=true)\n+        cha_cfg                 Set the configuration for virtual channel a.\n+                                (default=4 configures this channel for the\n+                                voltage at A0 with respect to GND)\n+        cha_datarate            Set the datarate (samples/sec) for this channel.\n+                                (default=4 sets 1600 sps)\n+        cha_gain                Set the gain of the Programmable Gain\n+                                Amplifier for this channel. (default=2 sets the\n+                                full scale of the channel to 2.048 Volts)\n+\n+        Channel (ch) parameters can be set for each enabled channel.\n+        A maximum of 4 channels can be enabled (letters a thru d).\n+        For more information refer to the device datasheet at:\n+        http://www.ti.com/lit/ds/symlink/ads1015.pdf\n+\n+\n+Name:   ads1115\n+Info:   Texas Instruments ADS1115 ADC\n+Load:   dtoverlay=ads1115,<param>[=<val>]\n+Params: addr                    I2C bus address of device. Set based on how the\n+                                addr pin is wired. (default=0x48 assumes addr\n+                                is pulled to GND)\n+        cha_enable              Enable virtual channel a.\n+        cha_cfg                 Set the configuration for virtual channel a.\n+                                (default=4 configures this channel for the\n+                                voltage at A0 with respect to GND)\n+        cha_datarate            Set the datarate (samples/sec) for this channel.\n+                                (default=7 sets 860 sps)\n+        cha_gain                Set the gain of the Programmable Gain\n+                                Amplifier for this channel. (Default 1 sets the\n+                                full scale of the channel to 4.096 Volts)\n+\n+        Channel parameters can be set for each enabled channel.\n+        A maximum of 4 channels can be enabled (letters a thru d).\n+        For more information refer to the device datasheet at:\n+        http://www.ti.com/lit/ds/symlink/ads1115.pdf\n+\n+\n+Name:   ads7846\n+Info:   ADS7846 Touch controller\n+Load:   dtoverlay=ads7846,<param>=<val>\n+Params: cs                      SPI bus Chip Select (default 1)\n+        speed                   SPI bus speed (default 2MHz, max 3.25MHz)\n+        penirq                  GPIO used for PENIRQ. REQUIRED\n+        penirq_pull             Set GPIO pull (default 0=none, 2=pullup)\n+        swapxy                  Swap x and y axis\n+        xmin                    Minimum value on the X axis (default 0)\n+        ymin                    Minimum value on the Y axis (default 0)\n+        xmax                    Maximum value on the X axis (default 4095)\n+        ymax                    Maximum value on the Y axis (default 4095)\n+        pmin                    Minimum reported pressure value (default 0)\n+        pmax                    Maximum reported pressure value (default 65535)\n+        xohms                   Touchpanel sensitivity (X-plate resistance)\n+                                (default 400)\n+\n+        penirq is required and usually xohms (60-100) has to be set as well.\n+        Apart from that, pmax (255) and swapxy are also common.\n+        The rest of the calibration can be done with xinput-calibrator.\n+        See: github.com/notro/fbtft/wiki/FBTFT-on-Raspian\n+        Device Tree binding document:\n+        www.kernel.org/doc/Documentation/devicetree/bindings/input/ads7846.txt\n+\n+\n+Name:   adv7282m\n+Info:   Analog Devices ADV7282M analogue video to CSI2 bridge.\n+        Uses Unicam1, which is the standard camera connector on most Pi\n+        variants.\n+Load:   dtoverlay=adv7282m,<param>=<val>\n+Params: addr                    Overrides the I2C address (default 0x21)\n+\n+\n+Name:   adv728x-m\n+Info:   Analog Devices ADV728[0|1|2]-M analogue video to CSI2 bridges.\n+        This is a wrapper for adv7282m, and defaults to ADV7282M.\n+Load:   dtoverlay=adv728x-m,<param>=<val>\n+Params: addr                    Overrides the I2C address (default 0x21)\n+        adv7280m                Select ADV7280-M.\n+        adv7281m                Select ADV7281-M.\n+        adv7281ma               Select ADV7281-MA.\n+\n+\n+Name:   akkordion-iqdacplus\n+Info:   Configures the Digital Dreamtime Akkordion Music Player (based on the\n+        OEM IQAudIO DAC+ or DAC Zero module).\n+Load:   dtoverlay=akkordion-iqdacplus,<param>=<val>\n+Params: 24db_digital_gain       Allow gain to be applied via the PCM512x codec\n+                                Digital volume control. Enable with\n+                                dtoverlay=akkordion-iqdacplus,24db_digital_gain\n+                                (The default behaviour is that the Digital\n+                                volume control is limited to a maximum of\n+                                0dB. ie. it can attenuate but not provide\n+                                gain. For most users, this will be desired\n+                                as it will prevent clipping. By appending\n+                                the 24db_digital_gain parameter, the Digital\n+                                volume control will allow up to 24dB of\n+                                gain. If this parameter is enabled, it is the\n+                                responsibility of the user to ensure that\n+                                the Digital volume control is set to a value\n+                                that does not result in clipping/distortion!)\n+\n+\n+Name:   allo-boss-dac-pcm512x-audio\n+Info:   Configures the Allo Boss DAC audio cards.\n+Load:   dtoverlay=allo-boss-dac-pcm512x-audio,<param>\n+Params: 24db_digital_gain       Allow gain to be applied via the PCM512x codec\n+                                Digital volume control. Enable with\n+                                \"dtoverlay=allo-boss-dac-pcm512x-audio,\n+                                24db_digital_gain\"\n+                                (The default behaviour is that the Digital\n+                                volume control is limited to a maximum of\n+                                0dB. ie. it can attenuate but not provide\n+                                gain. For most users, this will be desired\n+                                as it will prevent clipping. By appending\n+                                the 24db_digital_gain parameter, the Digital\n+                                volume control will allow up to 24dB of\n+                                gain. If this parameter is enabled, it is the\n+                                responsibility of the user to ensure that\n+                                the Digital volume control is set to a value\n+                                that does not result in clipping/distortion!)\n+        slave                   Force Boss DAC into slave mode, using Pi a\n+                                master for bit clock and frame clock. Enable\n+                                with \"dtoverlay=allo-boss-dac-pcm512x-audio,\n+                                slave\"\n+\n+\n+Name:   allo-digione\n+Info:   Configures the Allo Digione audio card\n+Load:   dtoverlay=allo-digione\n+Params: <None>\n+\n+\n+Name:   allo-katana-dac-audio\n+Info:   Configures the Allo Katana DAC audio card\n+Load:   dtoverlay=allo-katana-dac-audio\n+Params: <None>\n+\n+\n+Name:   allo-piano-dac-pcm512x-audio\n+Info:   Configures the Allo Piano DAC (2.0/2.1) audio cards.\n+        (NB. This initial support is for 2.0 channel audio ONLY! ie. stereo.\n+        The subwoofer outputs on the Piano 2.1 are not currently supported!)\n+Load:   dtoverlay=allo-piano-dac-pcm512x-audio,<param>\n+Params: 24db_digital_gain       Allow gain to be applied via the PCM512x codec\n+                                Digital volume control.\n+                                (The default behaviour is that the Digital\n+                                volume control is limited to a maximum of\n+                                0dB. ie. it can attenuate but not provide\n+                                gain. For most users, this will be desired\n+                                as it will prevent clipping. By appending\n+                                the 24db_digital_gain parameter, the Digital\n+                                volume control will allow up to 24dB of\n+                                gain. If this parameter is enabled, it is the\n+                                responsibility of the user to ensure that\n+                                the Digital volume control is set to a value\n+                                that does not result in clipping/distortion!)\n+\n+\n+Name:   allo-piano-dac-plus-pcm512x-audio\n+Info:   Configures the Allo Piano DAC (2.1) audio cards.\n+Load:   dtoverlay=allo-piano-dac-plus-pcm512x-audio,<param>\n+Params: 24db_digital_gain       Allow gain to be applied via the PCM512x codec\n+                                Digital volume control.\n+                                (The default behaviour is that the Digital\n+                                volume control is limited to a maximum of\n+                                0dB. ie. it can attenuate but not provide\n+                                gain. For most users, this will be desired\n+                                as it will prevent clipping. By appending\n+                                the 24db_digital_gain parameter, the Digital\n+                                volume control will allow up to 24dB of\n+                                gain. If this parameter is enabled, it is the\n+                                responsibility of the user to ensure that\n+                                the Digital volume control is set to a value\n+                                that does not result in clipping/distortion!)\n+        glb_mclk                This option is only with Kali board. If enabled,\n+                                MCLK for Kali is used and PLL is disabled for\n+                                better voice quality. (default Off)\n+\n+\n+Name:   anyspi\n+Info:   Universal device tree overlay for SPI devices\n+\n+        Just specify the SPI address and device name (\"compatible\" property).\n+        This overlay lacks any device-specific parameter support!\n+\n+        For devices on spi1 or spi2, the interfaces should be enabled\n+        with one of the spi1-1/2/3cs and/or spi2-1/2/3cs overlays.\n+\n+        Examples:\n+        1. SPI NOR flash on spi0.1, maximum SPI clock frequency 45MHz:\n+            dtoverlay=anyspi:spi0-1,dev=\"jedec,spi-nor\",speed=45000000\n+        2. MCP3204 ADC on spi1.2, maximum SPI clock frequency 500kHz:\n+            dtoverlay=anyspi:spi1-2,dev=\"microchip,mcp3204\"\n+Load:   dtoverlay=anyspi,<param>=<val>\n+Params: spi<n>-<m>              Configure device at spi<n>, cs<m>\n+                                (boolean, required)\n+        dev                     Set device name to search compatible module\n+                                (string, required)\n+        speed                   Set SPI clock frequency in Hz\n+                                (integer, optional, default 500000)\n+\n+\n+Name:   apds9960\n+Info:   Configures the AVAGO APDS9960 digital proximity, ambient light, RGB and\n+        gesture sensor\n+Load:   dtoverlay=apds9960,<param>=<val>\n+Params: gpiopin                 GPIO used for INT (default 4)\n+        noints                  Disable the interrupt GPIO line.\n+\n+\n+Name:   applepi-dac\n+Info:   Configures the Orchard Audio ApplePi-DAC audio card\n+Load:   dtoverlay=applepi-dac\n+Params: <None>\n+\n+\n+Name:   at86rf233\n+Info:   Configures the Atmel AT86RF233 802.15.4 low-power WPAN transceiver,\n+        connected to spi0.0\n+Load:   dtoverlay=at86rf233,<param>=<val>\n+Params: interrupt               GPIO used for INT (default 23)\n+        reset                   GPIO used for Reset (default 24)\n+        sleep                   GPIO used for Sleep (default 25)\n+        speed                   SPI bus speed in Hz (default 3000000)\n+        trim                    Fine tuning of the internal capacitance\n+                                arrays (0=+0pF, 15=+4.5pF, default 15)\n+\n+\n+Name:   audioinjector-addons\n+Info:   Configures the audioinjector.net audio add on soundcards\n+Load:   dtoverlay=audioinjector-addons,<param>=<val>\n+Params: non-stop-clocks         Keeps the clocks running even when the stream\n+                                is paused or stopped (default off)\n+\n+\n+Name:   audioinjector-isolated-soundcard\n+Info:   Configures the audioinjector.net isolated soundcard\n+Load:   dtoverlay=audioinjector-isolated-soundcard\n+Params: <None>\n+\n+\n+Name:   audioinjector-ultra\n+Info:   Configures the audioinjector.net ultra soundcard\n+Load:   dtoverlay=audioinjector-ultra\n+Params: <None>\n+\n+\n+Name:   audioinjector-wm8731-audio\n+Info:   Configures the audioinjector.net audio add on soundcard\n+Load:   dtoverlay=audioinjector-wm8731-audio\n+Params: <None>\n+\n+\n+Name:   audiosense-pi\n+Info:   Configures the audiosense-pi add on soundcard\n+        For more information refer to\n+        https://gitlab.com/kakar0t/audiosense-pi\n+Load:   dtoverlay=audiosense-pi\n+Params: <None>\n+\n+\n+Name:   audremap\n+Info:   Switches PWM sound output to GPIOs on the 40-pin header\n+Load:   dtoverlay=audremap,<param>=<val>\n+Params: swap_lr                 Reverse the channel allocation, which will also\n+                                swap the audio jack outputs (default off)\n+        enable_jack             Don't switch off the audio jack output\n+                                (default off)\n+        pins_12_13              Select GPIOs 12 & 13 (default)\n+        pins_18_19              Select GPIOs 18 & 19\n+\n+\n+Name:   balena-fin\n+Info:   Overlay that enables WiFi, Bluetooth and the GPIO expander on the\n+        balenaFin carrier board for the Raspberry Pi Compute Module 3/3+ Lite.\n+Load:   dtoverlay=balena-fin\n+Params: <None>\n+\n+\n+Name:   bmp085_i2c-sensor\n+Info:   This overlay is now deprecated - see i2c-sensor\n+Load:   <Deprecated>\n+\n+\n+Name:   cma\n+Info:   Set custom CMA sizes, only use if you know what you are doing, might\n+        clash with other overlays like vc4-fkms-v3d and vc4-kms-v3d.\n+Load:   dtoverlay=cma,<param>=<val>\n+Params: cma-512                 CMA is 512MB (needs 1GB)\n+        cma-448                 CMA is 448MB (needs 1GB)\n+        cma-384                 CMA is 384MB (needs 1GB)\n+        cma-320                 CMA is 320MB (needs 1GB)\n+        cma-256                 CMA is 256MB (needs 1GB)\n+        cma-192                 CMA is 192MB (needs 1GB)\n+        cma-128                 CMA is 128MB\n+        cma-96                  CMA is 96MB\n+        cma-64                  CMA is 64MB\n+        cma-size                CMA size in bytes, 4MB aligned\n+        cma-default             Use upstream's default value\n+\n+\n+Name:   dht11\n+Info:   Overlay for the DHT11/DHT21/DHT22 humidity/temperature sensors\n+        Also sometimes found with the part number(s) AM230x.\n+Load:   dtoverlay=dht11,<param>=<val>\n+Params: gpiopin                 GPIO connected to the sensor's DATA output.\n+                                (default 4)\n+\n+\n+Name:   dionaudio-loco\n+Info:   Configures the Dion Audio LOCO DAC-AMP\n+Load:   dtoverlay=dionaudio-loco\n+Params: <None>\n+\n+\n+Name:   dionaudio-loco-v2\n+Info:   Configures the Dion Audio LOCO-V2 DAC-AMP\n+Load:   dtoverlay=dionaudio-loco-v2,<param>=<val>\n+Params: 24db_digital_gain       Allow gain to be applied via the PCM512x codec\n+                                Digital volume control. Enable with\n+                                \"dtoverlay=hifiberry-dacplus,24db_digital_gain\"\n+                                (The default behaviour is that the Digital\n+                                volume control is limited to a maximum of\n+                                0dB. ie. it can attenuate but not provide\n+                                gain. For most users, this will be desired\n+                                as it will prevent clipping. By appending\n+                                the 24dB_digital_gain parameter, the Digital\n+                                volume control will allow up to 24dB of\n+                                gain. If this parameter is enabled, it is the\n+                                responsibility of the user to ensure that\n+                                the Digital volume control is set to a value\n+                                that does not result in clipping/distortion!)\n+\n+\n+Name:   disable-bt\n+Info:   Disable onboard Bluetooth on Pi 3B, 3B+, 3A+, 4B and Zero W, restoring\n+        UART0/ttyAMA0 over GPIOs 14 & 15.\n+        N.B. To disable the systemd service that initialises the modem so it\n+        doesn't use the UART, use 'sudo systemctl disable hciuart'.\n+Load:   dtoverlay=disable-bt\n+Params: <None>\n+\n+\n+Name:   disable-wifi\n+Info:   Disable onboard WiFi on Pi 3B, 3B+, 3A+, 4B and Zero W.\n+Load:   dtoverlay=disable-wifi\n+Params: <None>\n+\n+\n+Name:   dpi18\n+Info:   Overlay for a generic 18-bit DPI display\n+        This uses GPIOs 0-21 (so no I2C, uart etc.), and activates the output\n+        2-3 seconds after the kernel has started.\n+Load:   dtoverlay=dpi18\n+Params: <None>\n+\n+\n+Name:   dpi24\n+Info:   Overlay for a generic 24-bit DPI display\n+        This uses GPIOs 0-27 (so no I2C, uart etc.), and activates the output\n+        2-3 seconds after the kernel has started.\n+Load:   dtoverlay=dpi24\n+Params: <None>\n+\n+\n+Name:   draws\n+Info:   Configures the NW Digital Radio DRAWS Hat\n+\n+        The board includes an ADC to measure various board values and also\n+        provides two analog user inputs on the expansion header.  The ADC\n+        can be configured for various sample rates and gain values to adjust\n+        the input range.  Tables describing the two parameters follow.\n+\n+        ADC Gain Values:\n+            0 = +/- 6.144V\n+            1 = +/- 4.096V\n+            2 = +/- 2.048V\n+            3 = +/- 1.024V\n+            4 = +/- 0.512V\n+            5 = +/- 0.256V\n+            6 = +/- 0.256V\n+            7 = +/- 0.256V\n+\n+        ADC Datarate Values:\n+            0 = 128sps\n+            1 = 250sps\n+            2 = 490sps\n+            3 = 920sps\n+            4 = 1600sps (default)\n+            5 = 2400sps\n+            6 = 3300sps\n+            7 = 3300sps\n+Load:   dtoverlay=draws,<param>=<val>\n+Params: draws_adc_ch4_gain      Sets the full scale resolution of the ADCs\n+                                input voltage sensor (default 1)\n+\n+        draws_adc_ch4_datarate  Sets the datarate of the ADCs input voltage\n+                                sensor\n+\n+        draws_adc_ch5_gain      Sets the full scale resolution of the ADCs\n+                                5V rail voltage sensor (default 1)\n+\n+        draws_adc_ch5_datarate  Sets the datarate of the ADCs 4V rail voltage\n+                                sensor\n+\n+        draws_adc_ch6_gain      Sets the full scale resolution of the ADCs\n+                                AIN2 input (default 2)\n+\n+        draws_adc_ch6_datarate  Sets the datarate of the ADCs AIN2 input\n+\n+        draws_adc_ch7_gain      Sets the full scale resolution of the ADCs\n+                                AIN3 input (default 2)\n+\n+        draws_adc_ch7_datarate  Sets the datarate of the ADCs AIN3 input\n+\n+        alsaname                Name of the ALSA audio device (default \"draws\")\n+\n+\n+Name:   dwc-otg\n+Info:   Selects the dwc_otg USB controller driver which has fiq support. This\n+        is the default on all except the Pi Zero which defaults to dwc2.\n+Load:   dtoverlay=dwc-otg\n+Params: <None>\n+\n+\n+Name:   dwc2\n+Info:   Selects the dwc2 USB controller driver\n+Load:   dtoverlay=dwc2,<param>=<val>\n+Params: dr_mode                 Dual role mode: \"host\", \"peripheral\" or \"otg\"\n+\n+        g-rx-fifo-size          Size of rx fifo size in gadget mode\n+\n+        g-np-tx-fifo-size       Size of non-periodic tx fifo size in gadget\n+                                mode\n+\n+\n+[ The ds1307-rtc overlay has been deleted. See i2c-rtc. ]\n+\n+\n+Name:   enc28j60\n+Info:   Overlay for the Microchip ENC28J60 Ethernet Controller on SPI0\n+Load:   dtoverlay=enc28j60,<param>=<val>\n+Params: int_pin                 GPIO used for INT (default 25)\n+\n+        speed                   SPI bus speed (default 12000000)\n+\n+\n+Name:   enc28j60-spi2\n+Info:   Overlay for the Microchip ENC28J60 Ethernet Controller on SPI2\n+Load:   dtoverlay=enc28j60-spi2,<param>=<val>\n+Params: int_pin                 GPIO used for INT (default 39)\n+\n+        speed                   SPI bus speed (default 12000000)\n+\n+\n+Name:   exc3000\n+Info:   Enables I2C connected EETI EXC3000 multiple touch controller using\n+        GPIO 4 (pin 7 on GPIO header) for interrupt.\n+Load:   dtoverlay=exc3000,<param>=<val>\n+Params: interrupt               GPIO used for interrupt (default 4)\n+        sizex                   Touchscreen size x (default 4096)\n+        sizey                   Touchscreen size y (default 4096)\n+        invx                    Touchscreen inverted x axis\n+        invy                    Touchscreen inverted y axis\n+        swapxy                  Touchscreen swapped x y axis\n+\n+\n+Name:   fe-pi-audio\n+Info:   Configures the Fe-Pi Audio Sound Card\n+Load:   dtoverlay=fe-pi-audio\n+Params: <None>\n+\n+\n+Name:   fsm-demo\n+Info:   A demonstration of the gpio-fsm driver. The GPIOs are chosen to work\n+        nicely with a \"traffic-light\" display of red, amber and green LEDs on\n+        GPIOs 7, 8 and 25 respectively.\n+Load:   dtoverlay=fsm-demo,<param>=<val>\n+Params: fsm_debug               Enable debug logging (default off)\n+\n+\n+Name:   ghost-amp\n+Info:   An overlay for the Ghost amplifier.\n+Load:   dtoverlay=ghost-amp,<param>=<val>\n+Params: fsm_debug               Enable debug logging of the GPIO FSM (default\n+                                off)\n+\n+\n+Name:   goodix\n+Info:   Enables I2C connected Goodix gt9271 multiple touch controller using\n+        GPIOs 4 and 17 (pins 7 and 11 on GPIO header) for interrupt and reset.\n+Load:   dtoverlay=goodix,<param>=<val>\n+Params: interrupt               GPIO used for interrupt (default 4)\n+        reset                   GPIO used for reset (default 17)\n+\n+\n+Name:   googlevoicehat-soundcard\n+Info:   Configures the Google voiceHAT soundcard\n+Load:   dtoverlay=googlevoicehat-soundcard\n+Params: <None>\n+\n+\n+Name:   gpio-fan\n+Info:   Configure a GPIO pin to control a cooling fan.\n+Load:   dtoverlay=gpio-fan,<param>=<val>\n+Params: gpiopin                 GPIO used to control the fan (default 12)\n+        temp                    Temperature at which the fan switches on, in\n+                                millicelcius (default 55000)\n+\n+\n+Name:   gpio-ir\n+Info:   Use GPIO pin as rc-core style infrared receiver input. The rc-core-\n+        based gpio_ir_recv driver maps received keys directly to a\n+        /dev/input/event* device, all decoding is done by the kernel - LIRC is\n+        not required! The key mapping and other decoding parameters can be\n+        configured by \"ir-keytable\" tool.\n+Load:   dtoverlay=gpio-ir,<param>=<val>\n+Params: gpio_pin                Input pin number. Default is 18.\n+\n+        gpio_pull               Desired pull-up/down state (off, down, up)\n+                                Default is \"up\".\n+\n+        invert                  \"1\" = invert the input (active-low signalling).\n+                                \"0\" = non-inverted input (active-high\n+                                signalling). Default is \"1\".\n+\n+        rc-map-name             Default rc keymap (can also be changed by\n+                                ir-keytable), defaults to \"rc-rc6-mce\"\n+\n+\n+Name:   gpio-ir-tx\n+Info:   Use GPIO pin as bit-banged infrared transmitter output.\n+        This is an alternative to \"pwm-ir-tx\". gpio-ir-tx doesn't require\n+        a PWM so it can be used together with onboard analog audio.\n+Load:   dtoverlay=gpio-ir-tx,<param>=<val>\n+Params: gpio_pin                Output GPIO (default 18)\n+\n+        invert                  \"1\" = invert the output (make it active-low).\n+                                Default is \"0\" (active-high).\n+\n+\n+Name:   gpio-key\n+Info:   This is a generic overlay for activating GPIO keypresses using\n+        the gpio-keys library and this dtoverlay. Multiple keys can be\n+        set up using multiple calls to the overlay for configuring\n+        additional buttons or joysticks. You can see available keycodes\n+        at https://github.com/torvalds/linux/blob/v4.12/include/uapi/\n+        linux/input-event-codes.h#L64\n+Load:   dtoverlay=gpio-key,<param>=<val>\n+Params: gpio                    GPIO pin to trigger on (default 3)\n+        active_low              When this is 1 (active low), a falling\n+                                edge generates a key down event and a\n+                                rising edge generates a key up event.\n+                                When this is 0 (active high), this is\n+                                reversed. The default is 1 (active low)\n+        gpio_pull               Desired pull-up/down state (off, down, up)\n+                                Default is \"up\". Note that the default pin\n+                                (GPIO3) has an external pullup\n+        label                   Set a label for the key\n+        keycode                 Set the key code for the button\n+\n+\n+Name:   gpio-no-bank0-irq\n+Info:   Use this overlay to disable GPIO interrupts for GPIOs in bank 0 (0-27),\n+        which can be useful for UIO drivers.\n+        N.B. Using this overlay will trigger a kernel WARN during booting, but\n+        this can safely be ignored - the system should work as expected.\n+Load:   dtoverlay=gpio-no-bank0-irq\n+Params: <None>\n+\n+\n+Name:   gpio-no-irq\n+Info:   Use this overlay to disable all GPIO interrupts, which can be useful\n+        for user-space GPIO edge detection systems.\n+Load:   dtoverlay=gpio-no-irq\n+Params: <None>\n+\n+\n+Name:   gpio-poweroff\n+Info:   Drives a GPIO high or low on poweroff (including halt). Enabling this\n+        overlay will prevent the ability to boot by driving GPIO3 low.\n+Load:   dtoverlay=gpio-poweroff,<param>=<val>\n+Params: gpiopin                 GPIO for signalling (default 26)\n+\n+        active_low              Set if the power control device requires a\n+                                high->low transition to trigger a power-down.\n+                                Note that this will require the support of a\n+                                custom dt-blob.bin to prevent a power-down\n+                                during the boot process, and that a reboot\n+                                will also cause the pin to go low.\n+        input                   Set if the gpio pin should be configured as\n+                                an input.\n+        export                  Set to export the configured pin to sysfs\n+        timeout_ms              Specify (in ms) how long the kernel waits for\n+                                power-down before issuing a WARN (default 3000).\n+\n+\n+Name:   gpio-shutdown\n+Info:   Initiates a shutdown when GPIO pin changes. The given GPIO pin\n+        is configured as an input key that generates KEY_POWER events.\n+\n+        This event is handled by systemd-logind by initiating a\n+        shutdown. Systemd versions older than 225 need an udev rule\n+        enable listening to the input device:\n+\n+                ACTION!=\"REMOVE\", SUBSYSTEM==\"input\", KERNEL==\"event*\", \\\n+                        SUBSYSTEMS==\"platform\", DRIVERS==\"gpio-keys\", \\\n+                        ATTRS{keys}==\"116\", TAG+=\"power-switch\"\n+\n+        Alternatively this event can be handled also on systems without\n+        systemd, just by traditional SysV init daemon. KEY_POWER event\n+        (keycode 116) needs to be mapped to KeyboardSignal on console\n+        and then kb::kbrequest inittab action which is triggered by\n+        KeyboardSignal from console can be configured to issue system\n+        shutdown. Steps for this configuration are:\n+\n+            Add following lines to the /etc/console-setup/remap.inc file:\n+\n+                # Key Power as special keypress\n+                keycode 116 = KeyboardSignal\n+\n+            Then add following lines to /etc/inittab file:\n+\n+                # Action on special keypress (Key Power)\n+                kb::kbrequest:/sbin/shutdown -t1 -a -h -P now\n+\n+            And finally reload configuration by calling following commands:\n+\n+                # dpkg-reconfigure console-setup\n+                # service console-setup reload\n+                # init q\n+\n+        This overlay only handles shutdown. After shutdown, the system\n+        can be powered up again by driving GPIO3 low. The default\n+        configuration uses GPIO3 with a pullup, so if you connect a\n+        button between GPIO3 and GND (pin 5 and 6 on the 40-pin header),\n+        you get a shutdown and power-up button. Please note that\n+        Raspberry Pi 1 Model B rev 1 uses GPIO1 instead of GPIO3.\n+Load:   dtoverlay=gpio-shutdown,<param>=<val>\n+Params: gpio_pin                GPIO pin to trigger on (default 3)\n+                                For Raspberry Pi 1 Model B rev 1 set this\n+                                explicitly to value 1, e.g.:\n+\n+                                    dtoverlay=gpio-shutdown,gpio_pin=1\n+\n+        active_low              When this is 1 (active low), a falling\n+                                edge generates a key down event and a\n+                                rising edge generates a key up event.\n+                                When this is 0 (active high), this is\n+                                reversed. The default is 1 (active low).\n+\n+        gpio_pull               Desired pull-up/down state (off, down, up)\n+                                Default is \"up\".\n+\n+                                Note that the default pin (GPIO3) has an\n+                                external pullup. Same applies for GPIO1\n+                                on Raspberry Pi 1 Model B rev 1.\n+\n+        debounce                Specify the debounce interval in milliseconds\n+                                (default 100)\n+\n+\n+Name:   hd44780-lcd\n+Info:   Configures an HD44780 compatible LCD display. Uses 4 gpio pins for\n+        data, 2 gpio pins for enable and register select and 1 optional pin\n+        for enabling/disabling the backlight display.\n+Load:   dtoverlay=hd44780-lcd,<param>=<val>\n+Params: pin_d4                  GPIO pin for data pin D4 (default 6)\n+\n+        pin_d5                  GPIO pin for data pin D5 (default 13)\n+\n+        pin_d6                  GPIO pin for data pin D6 (default 19)\n+\n+        pin_d7                  GPIO pin for data pin D7 (default 26)\n+\n+        pin_en                  GPIO pin for \"Enable\" (default 21)\n+\n+        pin_rs                  GPIO pin for \"Register Select\" (default 20)\n+\n+        pin_bl                  Optional pin for enabling/disabling the\n+                                display backlight. (default disabled)\n+\n+        display_height          Height of the display in characters\n+\n+        display_width           Width of the display in characters\n+\n+\n+Name:   hdmi-backlight-hwhack-gpio\n+Info:   Devicetree overlay for GPIO based backlight on/off capability.\n+        Use this if you have one of those HDMI displays whose backlight cannot\n+        be controlled via DPMS over HDMI and plan to do a little soldering to\n+        use an RPi gpio pin for on/off switching. See:\n+        https://www.waveshare.com/wiki/7inch_HDMI_LCD_(C)#Backlight_Control\n+Load:   dtoverlay=hdmi-backlight-hwhack-gpio,<param>=<val>\n+Params: gpio_pin                GPIO pin used (default 17)\n+        active_low              Set this to 1 if the display backlight is\n+                                switched on when the wire goes low.\n+                                Leave the default (value 0) if the backlight\n+                                expects a high to switch it on.\n+\n+\n+Name:   hifiberry-amp\n+Info:   Configures the HifiBerry Amp and Amp+ audio cards\n+Load:   dtoverlay=hifiberry-amp\n+Params: <None>\n+\n+\n+Name:   hifiberry-dac\n+Info:   Configures the HifiBerry DAC audio card\n+Load:   dtoverlay=hifiberry-dac\n+Params: <None>\n+\n+\n+Name:   hifiberry-dacplus\n+Info:   Configures the HifiBerry DAC+ audio card\n+Load:   dtoverlay=hifiberry-dacplus,<param>=<val>\n+Params: 24db_digital_gain       Allow gain to be applied via the PCM512x codec\n+                                Digital volume control. Enable with\n+                                \"dtoverlay=hifiberry-dacplus,24db_digital_gain\"\n+                                (The default behaviour is that the Digital\n+                                volume control is limited to a maximum of\n+                                0dB. ie. it can attenuate but not provide\n+                                gain. For most users, this will be desired\n+                                as it will prevent clipping. By appending\n+                                the 24dB_digital_gain parameter, the Digital\n+                                volume control will allow up to 24dB of\n+                                gain. If this parameter is enabled, it is the\n+                                responsibility of the user to ensure that\n+                                the Digital volume control is set to a value\n+                                that does not result in clipping/distortion!)\n+        slave                   Force DAC+ Pro into slave mode, using Pi as\n+                                master for bit clock and frame clock.\n+        leds_off                If set to 'true' the onboard indicator LEDs\n+                                are switched off at all times.\n+\n+\n+Name:   hifiberry-dacplusadc\n+Info:   Configures the HifiBerry DAC+ADC audio card\n+Load:   dtoverlay=hifiberry-dacplusadc,<param>=<val>\n+Params: 24db_digital_gain       Allow gain to be applied via the PCM512x codec\n+                                Digital volume control. Enable with\n+                                \"dtoverlay=hifiberry-dacplus,24db_digital_gain\"\n+                                (The default behaviour is that the Digital\n+                                volume control is limited to a maximum of\n+                                0dB. ie. it can attenuate but not provide\n+                                gain. For most users, this will be desired\n+                                as it will prevent clipping. By appending\n+                                the 24dB_digital_gain parameter, the Digital\n+                                volume control will allow up to 24dB of\n+                                gain. If this parameter is enabled, it is the\n+                                responsibility of the user to ensure that\n+                                the Digital volume control is set to a value\n+                                that does not result in clipping/distortion!)\n+        slave                   Force DAC+ Pro into slave mode, using Pi as\n+                                master for bit clock and frame clock.\n+        leds_off                If set to 'true' the onboard indicator LEDs\n+                                are switched off at all times.\n+\n+\n+Name:   hifiberry-dacplusadcpro\n+Info:   Configures the HifiBerry DAC+ADC PRO audio card\n+Load:   dtoverlay=hifiberry-dacplusadcpro,<param>=<val>\n+Params: 24db_digital_gain       Allow gain to be applied via the PCM512x codec\n+                                Digital volume control. Enable with\n+                                \"dtoverlay=hifiberry-dacplusadcpro,24db_digital_gain\"\n+                                (The default behaviour is that the Digital\n+                                volume control is limited to a maximum of\n+                                0dB. ie. it can attenuate but not provide\n+                                gain. For most users, this will be desired\n+                                as it will prevent clipping. By appending\n+                                the 24dB_digital_gain parameter, the Digital\n+                                volume control will allow up to 24dB of\n+                                gain. If this parameter is enabled, it is the\n+                                responsibility of the user to ensure that\n+                                the Digital volume control is set to a value\n+                                that does not result in clipping/distortion!)\n+        slave                   Force DAC+ADC Pro into slave mode, using Pi as\n+                                master for bit clock and frame clock.\n+        leds_off                If set to 'true' the onboard indicator LEDs\n+                                are switched off at all times.\n+\n+\n+Name:   hifiberry-dacplusdsp\n+Info:   Configures the HifiBerry DAC+DSP audio card\n+Load:   dtoverlay=hifiberry-dacplusdsp\n+Params: <None>\n+\n+\n+Name:   hifiberry-dacplushd\n+Info:   Configures the HifiBerry DAC+ HD audio card\n+Load:   dtoverlay=hifiberry-dacplushd\n+Params: <None>\n+\n+\n+Name:   hifiberry-digi\n+Info:   Configures the HifiBerry Digi and Digi+ audio card\n+Load:   dtoverlay=hifiberry-digi\n+Params: <None>\n+\n+\n+Name:   hifiberry-digi-pro\n+Info:   Configures the HifiBerry Digi+ Pro audio card\n+Load:   dtoverlay=hifiberry-digi-pro\n+Params: <None>\n+\n+\n+Name:   highperi\n+Info:   Enables \"High Peripheral\" mode\n+Load:   dtoverlay=highperi\n+Params: <None>\n+\n+\n+Name:   hy28a\n+Info:   HY28A - 2.8\" TFT LCD Display Module by HAOYU Electronics\n+        Default values match Texy's display shield\n+Load:   dtoverlay=hy28a,<param>=<val>\n+Params: speed                   Display SPI bus speed\n+\n+        rotate                  Display rotation {0,90,180,270}\n+\n+        fps                     Delay between frame updates\n+\n+        debug                   Debug output level {0-7}\n+\n+        xohms                   Touchpanel sensitivity (X-plate resistance)\n+\n+        resetgpio               GPIO used to reset controller\n+\n+        ledgpio                 GPIO used to control backlight\n+\n+\n+Name:   hy28b\n+Info:   HY28B - 2.8\" TFT LCD Display Module by HAOYU Electronics\n+        Default values match Texy's display shield\n+Load:   dtoverlay=hy28b,<param>=<val>\n+Params: speed                   Display SPI bus speed\n+\n+        rotate                  Display rotation {0,90,180,270}\n+\n+        fps                     Delay between frame updates\n+\n+        debug                   Debug output level {0-7}\n+\n+        xohms                   Touchpanel sensitivity (X-plate resistance)\n+\n+        resetgpio               GPIO used to reset controller\n+\n+        ledgpio                 GPIO used to control backlight\n+\n+\n+Name:   hy28b-2017\n+Info:   HY28B 2017 version - 2.8\" TFT LCD Display Module by HAOYU Electronics\n+        Default values match Texy's display shield\n+Load:   dtoverlay=hy28b-2017,<param>=<val>\n+Params: speed                   Display SPI bus speed\n+\n+        rotate                  Display rotation {0,90,180,270}\n+\n+        fps                     Delay between frame updates\n+\n+        debug                   Debug output level {0-7}\n+\n+        xohms                   Touchpanel sensitivity (X-plate resistance)\n+\n+        resetgpio               GPIO used to reset controller\n+\n+        ledgpio                 GPIO used to control backlight\n+\n+\n+Name:   i-sabre-q2m\n+Info:   Configures the Audiophonics I-SABRE Q2M DAC\n+Load:   dtoverlay=i-sabre-q2m\n+Params: <None>\n+\n+\n+Name:   i2c-bcm2708\n+Info:   Fall back to the i2c_bcm2708 driver for the i2c_arm bus.\n+Load:   dtoverlay=i2c-bcm2708\n+Params: <None>\n+\n+\n+Name:   i2c-gpio\n+Info:   Adds support for software i2c controller on gpio pins\n+Load:   dtoverlay=i2c-gpio,<param>=<val>\n+Params: i2c_gpio_sda            GPIO used for I2C data (default \"23\")\n+\n+        i2c_gpio_scl            GPIO used for I2C clock (default \"24\")\n+\n+        i2c_gpio_delay_us       Clock delay in microseconds\n+                                (default \"2\" = ~100kHz)\n+\n+        bus                     Set to a unique, non-zero value if wanting\n+                                multiple i2c-gpio busses. If set, will be used\n+                                as the preferred bus number (/dev/i2c-<n>). If\n+                                not set, the default value is 0, but the bus\n+                                number will be dynamically assigned - probably\n+                                3.\n+\n+\n+Name:   i2c-mux\n+Info:   Adds support for a number of I2C bus multiplexers on i2c_arm\n+Load:   dtoverlay=i2c-mux,<param>=<val>\n+Params: pca9542                 Select the NXP PCA9542 device\n+\n+        pca9545                 Select the NXP PCA9545 device\n+\n+        pca9548                 Select the NXP PCA9548 device\n+\n+        addr                    Change I2C address of the device (default 0x70)\n+\n+\n+[ The i2c-mux-pca9548a overlay has been deleted. See i2c-mux. ]\n+\n+\n+Name:   i2c-pwm-pca9685a\n+Info:   Adds support for an NXP PCA9685A I2C PWM controller on i2c_arm\n+Load:   dtoverlay=i2c-pwm-pca9685a,<param>=<val>\n+Params: addr                    I2C address of PCA9685A (default 0x40)\n+\n+\n+Name:   i2c-rtc\n+Info:   Adds support for a number of I2C Real Time Clock devices\n+Load:   dtoverlay=i2c-rtc,<param>=<val>\n+Params: abx80x                  Select one of the ABx80x family:\n+                                  AB0801, AB0803, AB0804, AB0805,\n+                                  AB1801, AB1803, AB1804, AB1805\n+\n+        ds1307                  Select the DS1307 device\n+\n+        ds1339                  Select the DS1339 device\n+\n+        ds3231                  Select the DS3231 device\n+\n+        m41t62                  Select the M41T62 device\n+\n+        mcp7940x                Select the MCP7940x device\n+\n+        mcp7941x                Select the MCP7941x device\n+\n+        pcf2127                 Select the PCF2127 device\n+\n+        pcf2129                 Select the PCF2129 device\n+\n+        pcf8523                 Select the PCF8523 device\n+\n+        pcf85363                Select the PCF85363 device\n+\n+        pcf8563                 Select the PCF8563 device\n+\n+        rv1805                  Select the Micro Crystal RV1805 device\n+\n+        rv3028                  Select the Micro Crystal RV3028 device\n+\n+        sd3078                  Select the ZXW Shenzhen whwave SD3078 device\n+\n+        addr                    Sets the address for the RTC. Note that the\n+                                device must be configured to use the specified\n+                                address.\n+\n+        trickle-diode-type      Diode type for trickle charge - \"standard\" or\n+                                \"schottky\" (ABx80x and RV1805 only)\n+\n+        trickle-resistor-ohms   Resistor value for trickle charge (DS1339,\n+                                ABx80x, RV1805, RV3028)\n+\n+        wakeup-source           Specify that the RTC can be used as a wakeup\n+                                source\n+\n+        backup-switchover-mode  Backup power supply switch mode. Must be 0 for\n+                                off or 1 for Vdd < VBackup (RV3028 only)\n+\n+\n+Name:   i2c-rtc-gpio\n+Info:   Adds support for a number of I2C Real Time Clock devices\n+        using the software i2c controller\n+Load:   dtoverlay=i2c-rtc-gpio,<param>=<val>\n+Params: abx80x                  Select one of the ABx80x family:\n+                                  AB0801, AB0803, AB0804, AB0805,\n+                                  AB1801, AB1803, AB1804, AB1805\n+\n+        ds1307                  Select the DS1307 device\n+\n+        ds1339                  Select the DS1339 device\n+\n+        ds3231                  Select the DS3231 device\n+\n+        m41t62                  Select the M41T62 device\n+\n+        mcp7940x                Select the MCP7940x device\n+\n+        mcp7941x                Select the MCP7941x device\n+\n+        pcf2127                 Select the PCF2127 device\n+\n+        pcf2129                 Select the PCF2129 device\n+\n+        pcf8523                 Select the PCF8523 device\n+\n+        pcf8563                 Select the PCF8563 device\n+\n+        rv1805                  Select the Micro Crystal RV1805 device\n+\n+        rv3028                  Select the Micro Crystal RV3028 device\n+\n+        addr                    Sets the address for the RTC. Note that the\n+                                device must be configured to use the specified\n+                                address.\n+\n+        trickle-diode-type      Diode type for trickle charge - \"standard\" or\n+                                \"schottky\" (ABx80x and RV1805 only)\n+\n+        trickle-resistor-ohms   Resistor value for trickle charge (DS1339,\n+                                ABx80x, RV1805, RV3028)\n+\n+        wakeup-source           Specify that the RTC can be used as a wakeup\n+                                source\n+\n+        backup-switchover-mode  Backup power supply switch mode. Must be 0 for\n+                                off or 1 for Vdd < VBackup (RV3028 only)\n+\n+        i2c_gpio_sda            GPIO used for I2C data (default \"23\")\n+\n+        i2c_gpio_scl            GPIO used for I2C clock (default \"24\")\n+\n+        i2c_gpio_delay_us       Clock delay in microseconds\n+                                (default \"2\" = ~100kHz)\n+\n+\n+Name:   i2c-sensor\n+Info:   Adds support for a number of I2C barometric pressure and temperature\n+        sensors on i2c_arm\n+Load:   dtoverlay=i2c-sensor,<param>=<val>\n+Params: addr                    Set the address for the BME280, BME680, BMP280,\n+                                DS1621, HDC100X, LM75, SHT3x or TMP102\n+\n+        bme280                  Select the Bosch Sensortronic BME280\n+                                Valid addresses 0x76-0x77, default 0x76\n+\n+        bme680                  Select the Bosch Sensortronic BME680\n+                                Valid addresses 0x76-0x77, default 0x76\n+\n+        bmp085                  Select the Bosch Sensortronic BMP085\n+\n+        bmp180                  Select the Bosch Sensortronic BMP180\n+\n+        bmp280                  Select the Bosch Sensortronic BMP280\n+                                Valid addresses 0x76-0x77, default 0x76\n+\n+        ds1621                  Select the Dallas Semiconductors DS1621 temp\n+                                sensor. Valid addresses 0x48-0x4f, default 0x48\n+\n+        hdc100x                 Select the Texas Instruments HDC100x temp sensor\n+                                Valid addresses 0x40-0x43, default 0x40\n+\n+        htu21                   Select the HTU21 temperature and humidity sensor\n+\n+        lm75                    Select the Maxim LM75 temperature sensor\n+                                Valid addresses 0x48-0x4f, default 0x4f\n+\n+        lm75addr                Deprecated - use addr parameter instead\n+\n+        max17040                Select the Maxim Integrated MAX17040 battery\n+                                monitor\n+\n+        sht3x                   Select the Sensiron SHT3x temperature and\n+                                humidity sensor. Valid addresses 0x44-0x45,\n+                                default 0x44\n+\n+        si7020                  Select the Silicon Labs Si7013/20/21 humidity/\n+                                temperature sensor\n+\n+        sps30                   Select the Sensirion SPS30 particulate matter\n+                                sensor. Fixed address 0x69.\n+\n+        tmp102                  Select the Texas Instruments TMP102 temp sensor\n+                                Valid addresses 0x48-0x4b, default 0x48\n+\n+        tsl4531                 Select the AMS TSL4531 digital ambient light\n+                                sensor\n+\n+        veml6070                Select the Vishay VEML6070 ultraviolet light\n+                                sensor\n+\n+\n+Name:   i2c0\n+Info:   Change i2c0 pin usage. Not all pin combinations are usable on all\n+        platforms - platforms other then Compute Modules can only use this\n+        to disable transaction combining.\n+        Do NOT use in conjunction with dtparam=i2c_vc=on. From the 5.4 kernel\n+        onwards the base DT includes the use of i2c_mux_pinctrl to expose two\n+        muxings of BSC0 - GPIOs 0&1, and whichever combination is used for the\n+        camera and display connectors. This overlay disables that mux and\n+        configures /dev/i2c0 to point at whichever set of pins is requested.\n+        dtparam=i2c_vc=on will try and enable the mux, so combining the two\n+        will cause conflicts.\n+Load:   dtoverlay=i2c0,<param>=<val>\n+Params: pins_0_1                Use pins 0 and 1 (default)\n+        pins_28_29              Use pins 28 and 29\n+        pins_44_45              Use pins 44 and 45\n+        pins_46_47              Use pins 46 and 47\n+        combine                 Allow transactions to be combined (default\n+                                \"yes\")\n+\n+\n+Name:   i2c0-bcm2708\n+Info:   Deprecated, legacy version of i2c0.\n+Load:   <Deprecated>\n+\n+\n+Name:   i2c1\n+Info:   Change i2c1 pin usage. Not all pin combinations are usable on all\n+        platforms - platforms other then Compute Modules can only use this\n+        to disable transaction combining.\n+Load:   dtoverlay=i2c1,<param>=<val>\n+Params: pins_2_3                Use pins 2 and 3 (default)\n+        pins_44_45              Use pins 44 and 45\n+        combine                 Allow transactions to be combined (default\n+                                \"yes\")\n+\n+\n+Name:   i2c1-bcm2708\n+Info:   Deprecated, legacy version of i2c1.\n+Load:   <Deprecated>\n+\n+\n+Name:   i2c3\n+Info:   Enable the i2c3 bus. BCM2711 only.\n+Load:   dtoverlay=i2c3,<param>\n+Params: pins_2_3                Use GPIOs 2 and 3\n+        pins_4_5                Use GPIOs 4 and 5 (default)\n+        baudrate                Set the baudrate for the interface (default\n+                                \"100000\")\n+\n+\n+Name:   i2c4\n+Info:   Enable the i2c4 bus. BCM2711 only.\n+Load:   dtoverlay=i2c4,<param>\n+Params: pins_6_7                Use GPIOs 6 and 7\n+        pins_8_9                Use GPIOs 8 and 9 (default)\n+        baudrate                Set the baudrate for the interface (default\n+                                \"100000\")\n+\n+\n+Name:   i2c5\n+Info:   Enable the i2c5 bus. BCM2711 only.\n+Load:   dtoverlay=i2c5,<param>\n+Params: pins_10_11              Use GPIOs 10 and 11\n+        pins_12_13              Use GPIOs 12 and 13 (default)\n+        baudrate                Set the baudrate for the interface (default\n+                                \"100000\")\n+\n+\n+Name:   i2c6\n+Info:   Enable the i2c6 bus. BCM2711 only.\n+Load:   dtoverlay=i2c6,<param>\n+Params: pins_0_1                Use GPIOs 0 and 1\n+        pins_22_23              Use GPIOs 22 and 23 (default)\n+        baudrate                Set the baudrate for the interface (default\n+                                \"100000\")\n+\n+\n+Name:   i2s-gpio28-31\n+Info:   move I2S function block to GPIO 28 to 31\n+Load:   dtoverlay=i2s-gpio28-31\n+Params: <None>\n+\n+\n+Name:   ilitek251x\n+Info:   Enables I2C connected Ilitek 251x multiple touch controller using\n+        GPIO 4 (pin 7 on GPIO header) for interrupt.\n+Load:   dtoverlay=ilitek251x,<param>=<val>\n+Params: interrupt               GPIO used for interrupt (default 4)\n+        sizex                   Touchscreen size x, horizontal resolution of\n+                                touchscreen (in pixels)\n+        sizey                   Touchscreen size y, vertical resolution of\n+                                touchscreen (in pixels)\n+\n+\n+Name:   imx219\n+Info:   Sony IMX219 camera module.\n+        Uses Unicam 1, which is the standard camera connector on most Pi\n+        variants.\n+Load:   dtoverlay=imx219,<param>=<val>\n+Params: rotation                Mounting rotation of the camera sensor (0 or\n+                                180, default 180)\n+\n+\n+Name:   imx290\n+Info:   Sony IMX290 camera module.\n+        Uses Unicam 1, which is the standard camera connector on most Pi\n+        variants. NB This currently uses 4 CSI2 data lanes and therefore will\n+        only work on a CM.\n+Load:   dtoverlay=imx290,<param>\n+Params: 4lane                   Enable 4 CSI2 lanes. This requires a Compute\n+                                Module (1, 3, or 4).\n+        clock-frequency         Sets the clock frequency to match that used on\n+                                the board.\n+                                Modules from Vision Components use 37.125MHz\n+                                (the default), whilst those from Innomaker use\n+                                74.25MHz.\n+        mono                    Denote that the module is a mono sensor.\n+\n+\n+Name:   imx477\n+Info:   Sony IMX477 camera module.\n+        Uses Unicam 1, which is the standard camera connector on most Pi\n+        variants.\n+Load:   dtoverlay=imx477,<param>=<val>\n+Params: rotation                Mounting rotation of the camera sensor (0 or\n+                                180, default 180)\n+\n+\n+Name:   iqaudio-codec\n+Info:   Configures the IQaudio Codec audio card\n+Load:   dtoverlay=iqaudio-codec\n+Params: <None>\n+\n+\n+Name:   iqaudio-dac\n+Info:   Configures the IQaudio DAC audio card\n+Load:   dtoverlay=iqaudio-dac,<param>\n+Params: 24db_digital_gain       Allow gain to be applied via the PCM512x codec\n+                                Digital volume control. Enable with\n+                                \"dtoverlay=iqaudio-dac,24db_digital_gain\"\n+                                (The default behaviour is that the Digital\n+                                volume control is limited to a maximum of\n+                                0dB. ie. it can attenuate but not provide\n+                                gain. For most users, this will be desired\n+                                as it will prevent clipping. By appending\n+                                the 24db_digital_gain parameter, the Digital\n+                                volume control will allow up to 24dB of\n+                                gain. If this parameter is enabled, it is the\n+                                responsibility of the user to ensure that\n+                                the Digital volume control is set to a value\n+                                that does not result in clipping/distortion!)\n+\n+\n+Name:   iqaudio-dacplus\n+Info:   Configures the IQaudio DAC+ audio card\n+Load:   dtoverlay=iqaudio-dacplus,<param>=<val>\n+Params: 24db_digital_gain       Allow gain to be applied via the PCM512x codec\n+                                Digital volume control. Enable with\n+                                \"dtoverlay=iqaudio-dacplus,24db_digital_gain\"\n+                                (The default behaviour is that the Digital\n+                                volume control is limited to a maximum of\n+                                0dB. ie. it can attenuate but not provide\n+                                gain. For most users, this will be desired\n+                                as it will prevent clipping. By appending\n+                                the 24db_digital_gain parameter, the Digital\n+                                volume control will allow up to 24dB of\n+                                gain. If this parameter is enabled, it is the\n+                                responsibility of the user to ensure that\n+                                the Digital volume control is set to a value\n+                                that does not result in clipping/distortion!)\n+        auto_mute_amp           If specified, unmute/mute the IQaudIO amp when\n+                                starting/stopping audio playback.\n+        unmute_amp              If specified, unmute the IQaudIO amp once when\n+                                the DAC driver module loads.\n+\n+\n+Name:   iqaudio-digi-wm8804-audio\n+Info:   Configures the IQAudIO Digi WM8804 audio card\n+Load:   dtoverlay=iqaudio-digi-wm8804-audio,<param>=<val>\n+Params: card_name               Override the default, \"IQAudIODigi\", card name.\n+        dai_name                Override the default, \"IQAudIO Digi\", dai name.\n+        dai_stream_name         Override the default, \"IQAudIO Digi HiFi\",\n+                                dai stream name.\n+\n+\n+Name:   irs1125\n+Info:   Infineon irs1125 TOF camera module.\n+        Uses Unicam 1, which is the standard camera connector on most Pi\n+        variants.\n+Load:   dtoverlay=irs1125\n+Params: <None>\n+\n+\n+Name:   jedec-spi-nor\n+Info:   Adds support for JEDEC-compliant SPI NOR flash devices.  (Note: The\n+        \"jedec,spi-nor\" kernel driver was formerly known as \"m25p80\".)\n+Load:   dtoverlay=jedec-spi-nor,<param>=<val>\n+Params: flash-spi<n>-<m>        Enables flash device on SPI<n>, CS#<m>.\n+        flash-fastr-spi<n>-<m>  Enables flash device with fast read capability\n+                                on SPI<n>, CS#<m>.\n+\n+\n+Name:   justboom-both\n+Info:   Simultaneous usage of an justboom-dac and justboom-digi based\n+        card\n+Load:   dtoverlay=justboom-both,<param>=<val>\n+Params: 24db_digital_gain       Allow gain to be applied via the PCM512x codec\n+                                Digital volume control. Enable with\n+                                \"dtoverlay=justboom-dac,24db_digital_gain\"\n+                                (The default behaviour is that the Digital\n+                                volume control is limited to a maximum of\n+                                0dB. ie. it can attenuate but not provide\n+                                gain. For most users, this will be desired\n+                                as it will prevent clipping. By appending\n+                                the 24dB_digital_gain parameter, the Digital\n+                                volume control will allow up to 24dB of\n+                                gain. If this parameter is enabled, it is the\n+                                responsibility of the user to ensure that\n+                                the Digital volume control is set to a value\n+                                that does not result in clipping/distortion!)\n+\n+\n+Name:   justboom-dac\n+Info:   Configures the JustBoom DAC HAT, Amp HAT, DAC Zero and Amp Zero audio\n+        cards\n+Load:   dtoverlay=justboom-dac,<param>=<val>\n+Params: 24db_digital_gain       Allow gain to be applied via the PCM512x codec\n+                                Digital volume control. Enable with\n+                                \"dtoverlay=justboom-dac,24db_digital_gain\"\n+                                (The default behaviour is that the Digital\n+                                volume control is limited to a maximum of\n+                                0dB. ie. it can attenuate but not provide\n+                                gain. For most users, this will be desired\n+                                as it will prevent clipping. By appending\n+                                the 24dB_digital_gain parameter, the Digital\n+                                volume control will allow up to 24dB of\n+                                gain. If this parameter is enabled, it is the\n+                                responsibility of the user to ensure that\n+                                the Digital volume control is set to a value\n+                                that does not result in clipping/distortion!)\n+\n+\n+Name:   justboom-digi\n+Info:   Configures the JustBoom Digi HAT and Digi Zero audio cards\n+Load:   dtoverlay=justboom-digi\n+Params: <None>\n+\n+\n+Name:   lirc-rpi\n+Info:   This overlay has been deprecated and removed - see gpio-ir\n+Load:   <Deprecated>\n+\n+\n+Name:   ltc294x\n+Info:   Adds support for the ltc294x family of battery gauges\n+Load:   dtoverlay=ltc294x,<param>=<val>\n+Params: ltc2941                 Select the ltc2941 device\n+\n+        ltc2942                 Select the ltc2942 device\n+\n+        ltc2943                 Select the ltc2943 device\n+\n+        ltc2944                 Select the ltc2944 device\n+\n+        resistor-sense          The sense resistor value in milli-ohms.\n+                                Can be a 32-bit negative value when the battery\n+                                has been connected to the wrong end of the\n+                                resistor.\n+\n+        prescaler-exponent      Range and accuracy of the gauge. The value is\n+                                programmed into the chip only if it differs\n+                                from the current setting.\n+                                For LTC2941 only:\n+                                - Default value is 128\n+                                - the exponent is in the range 0-7 (default 7)\n+                                See the datasheet for more information.\n+\n+\n+Name:   max98357a\n+Info:   Configures the Maxim MAX98357A I2S DAC\n+Load:   dtoverlay=max98357a,<param>=<val>\n+Params: no-sdmode               Driver does not manage the state of the DAC's\n+                                SD_MODE pin (i.e. chip is always on).\n+        sdmode-pin              integer, GPIO pin connected to the SD_MODE input\n+                                of the DAC (default GPIO4 if parameter omitted).\n+\n+\n+Name:   maxtherm\n+Info:   Configure a MAX6675 or MAX31855 thermocouple as an IIO device.\n+\n+        For devices on spi1 or spi2, the interfaces should be enabled\n+        with one of the spi1-1/2/3cs and/or spi2-1/2/3cs overlays.\n+        The overlay expects to disable the relevant spidev node, so also using\n+        e.g. cs0_spidev=off is unnecessary.\n+\n+        Note:   with the 5.7 kernel (and later) there will also be\n+                overlays for MAX31855E, MAX31855J, MAX31855K,\n+                MAX31885N, MAX31855R, MAX31855S and MAX31855T.\n+\n+        Example:\n+        MAX31855 on /dev/spidev0.0\n+            dtoverlay=maxtherm,spi0-0,max31855\n+\n+Load:   dtoverlay=maxtherm,<param>=<val>\n+Params: spi<n>-<m>              Configure device at spi<n>, cs<m>\n+                                (boolean, required)\n+        max6675                 Enable support for the MAX6675 (default)\n+        max31855                Enable support for the MAX31855\n+        max31855e               Enable support for the MAX31855E\n+        max31855j               Enable support for the MAX31855J\n+        max31855k               Enable support for the MAX31855K\n+        max31855n               Enable support for the MAX31855N\n+        max31855r               Enable support for the MAX31855R\n+        max31855s               Enable support for the MAX31855S\n+        max31855t               Enable support for the MAX31855T\n+\n+\n+Name:   mbed-dac\n+Info:   Configures the mbed AudioCODEC (TLV320AIC23B)\n+Load:   dtoverlay=mbed-dac\n+Params: <None>\n+\n+\n+Name:   mcp23017\n+Info:   Configures the MCP23017 I2C GPIO expander\n+Load:   dtoverlay=mcp23017,<param>=<val>\n+Params: gpiopin                 Gpio pin connected to the INTA output of the\n+                                MCP23017 (default: 4)\n+\n+        addr                    I2C address of the MCP23017 (default: 0x20)\n+\n+        mcp23008                Configure an MCP23008 instead.\n+        noints                  Disable the interrupt GPIO line.\n+\n+\n+Name:   mcp23s17\n+Info:   Configures the MCP23S08/17 SPI GPIO expanders.\n+        If devices are present on SPI1 or SPI2, those interfaces must be enabled\n+        with one of the spi1-1/2/3cs and/or spi2-1/2/3cs overlays.\n+        If interrupts are enabled for a device on a given CS# on a SPI bus, that\n+        device must be the only one present on that SPI bus/CS#.\n+Load:   dtoverlay=mcp23s17,<param>=<val>\n+Params: s08-spi<n>-<m>-present  4-bit integer, bitmap indicating MCP23S08\n+                                devices present on SPI<n>, CS#<m>\n+\n+        s17-spi<n>-<m>-present  8-bit integer, bitmap indicating MCP23S17\n+                                devices present on SPI<n>, CS#<m>\n+\n+        s08-spi<n>-<m>-int-gpio integer, enables interrupts on a single\n+                                MCP23S08 device on SPI<n>, CS#<m>, specifies\n+                                the GPIO pin to which INT output of MCP23S08\n+                                is connected.\n+\n+        s17-spi<n>-<m>-int-gpio integer, enables mirrored interrupts on a\n+                                single MCP23S17 device on SPI<n>, CS#<m>,\n+                                specifies the GPIO pin to which either INTA\n+                                or INTB output of MCP23S17 is connected.\n+\n+\n+Name:   mcp2515-can0\n+Info:   Configures the MCP2515 CAN controller on spi0.0\n+Load:   dtoverlay=mcp2515-can0,<param>=<val>\n+Params: oscillator              Clock frequency for the CAN controller (Hz)\n+\n+        spimaxfrequency         Maximum SPI frequence (Hz)\n+\n+        interrupt               GPIO for interrupt signal\n+\n+\n+Name:   mcp2515-can1\n+Info:   Configures the MCP2515 CAN controller on spi0.1\n+Load:   dtoverlay=mcp2515-can1,<param>=<val>\n+Params: oscillator              Clock frequency for the CAN controller (Hz)\n+\n+        spimaxfrequency         Maximum SPI frequence (Hz)\n+\n+        interrupt               GPIO for interrupt signal\n+\n+\n+Name:   mcp3008\n+Info:   Configures MCP3008 A/D converters\n+        For devices on spi1 or spi2, the interfaces should be enabled\n+        with one of the spi1-1/2/3cs and/or spi2-1/2/3cs overlays.\n+Load:   dtoverlay=mcp3008,<param>[=<val>]\n+Params: spi<n>-<m>-present      boolean, configure device at spi<n>, cs<m>\n+        spi<n>-<m>-speed        integer, set the spi bus speed for this device\n+\n+\n+Name:   mcp3202\n+Info:   Configures MCP3202 A/D converters\n+        For devices on spi1 or spi2, the interfaces should be enabled\n+        with one of the spi1-1/2/3cs and/or spi2-1/2/3cs overlays.\n+Load:   dtoverlay=mcp3202,<param>[=<val>]\n+Params: spi<n>-<m>-present      boolean, configure device at spi<n>, cs<m>\n+        spi<n>-<m>-speed        integer, set the spi bus speed for this device\n+\n+\n+Name:   mcp342x\n+Info:   Overlay for activation of Microchip MCP3421-3428 ADCs over I2C\n+Load:   dtoverlay=mcp342x,<param>=<val>\n+Params: addr                    I2C bus address of device, for devices with\n+                                addresses that are configurable, e.g. by\n+                                hardware links (default=0x68)\n+        mcp3421                 The device is an MCP3421\n+        mcp3422                 The device is an MCP3422\n+        mcp3423                 The device is an MCP3423\n+        mcp3424                 The device is an MCP3424\n+        mcp3425                 The device is an MCP3425\n+        mcp3426                 The device is an MCP3426\n+        mcp3427                 The device is an MCP3427\n+        mcp3428                 The device is an MCP3428\n+\n+\n+Name:   media-center\n+Info:   Media Center HAT - 2.83\" Touch Display + extras by Pi Supply\n+Load:   dtoverlay=media-center,<param>=<val>\n+Params: speed                   Display SPI bus speed\n+        rotate                  Display rotation {0,90,180,270}\n+        fps                     Delay between frame updates\n+        xohms                   Touchpanel sensitivity (X-plate resistance)\n+        swapxy                  Swap x and y axis\n+        backlight               Change backlight GPIO pin {e.g. 12, 18}\n+        gpio_out_pin            GPIO for output (default \"17\")\n+        gpio_in_pin             GPIO for input (default \"18\")\n+        gpio_in_pull            Pull up/down/off on the input pin\n+                                (default \"down\")\n+        sense                   Override the IR receive auto-detection logic:\n+                                 \"0\" = force active-high\n+                                 \"1\" = force active-low\n+                                 \"-1\" = use auto-detection\n+                                (default \"-1\")\n+        softcarrier             Turn the software carrier \"on\" or \"off\"\n+                                (default \"on\")\n+        invert                  \"on\" = invert the output pin (default \"off\")\n+        debug                   \"on\" = enable additional debug messages\n+                                (default \"off\")\n+\n+\n+Name:   merus-amp\n+Info:   Configures the merus-amp audio card\n+Load:   dtoverlay=merus-amp\n+Params: <None>\n+\n+\n+Name:   midi-uart0\n+Info:   Configures UART0 (ttyAMA0) so that a requested 38.4kbaud actually gets\n+        31.25kbaud, the frequency required for MIDI\n+Load:   dtoverlay=midi-uart0\n+Params: <None>\n+\n+\n+Name:   midi-uart1\n+Info:   Configures UART1 (ttyS0) so that a requested 38.4kbaud actually gets\n+        31.25kbaud, the frequency required for MIDI\n+Load:   dtoverlay=midi-uart1\n+Params: <None>\n+\n+\n+Name:   miniuart-bt\n+Info:   Switch the onboard Bluetooth function on Pi 3B, 3B+, 3A+, 4B and Zero W\n+        to use the mini-UART (ttyS0) and restore UART0/ttyAMA0 over GPIOs 14 &\n+        15. Note that this may reduce the maximum usable baudrate.\n+        N.B. It is also necessary to edit /lib/systemd/system/hciuart.service\n+        and replace ttyAMA0 with ttyS0, unless using Raspbian or another\n+        distribution with udev rules that create /dev/serial0 and /dev/serial1,\n+        in which case use /dev/serial1 instead because it will always be\n+        correct. Furthermore, you must also set core_freq and core_freq_min to\n+        the same value in config.txt or the miniuart will not work.\n+Load:   dtoverlay=miniuart-bt,<param>=<val>\n+Params: krnbt                   Set to \"on\" to enable autoprobing of Bluetooth\n+                                driver without need of hciattach/btattach\n+\n+\n+Name:   mmc\n+Info:   Selects the bcm2835-mmc SD/MMC driver, optionally with overclock\n+Load:   dtoverlay=mmc,<param>=<val>\n+Params: overclock_50            Clock (in MHz) to use when the MMC framework\n+                                requests 50MHz\n+\n+\n+Name:   mpu6050\n+Info:   Overlay for i2c connected mpu6050 imu\n+Load:   dtoverlay=mpu6050,<param>=<val>\n+Params: interrupt               GPIO pin for interrupt (default 4)\n+\n+\n+Name:   mz61581\n+Info:   MZ61581 display by Tontec\n+Load:   dtoverlay=mz61581,<param>=<val>\n+Params: speed                   Display SPI bus speed\n+\n+        rotate                  Display rotation {0,90,180,270}\n+\n+        fps                     Delay between frame updates\n+\n+        txbuflen                Transmit buffer length (default 32768)\n+\n+        debug                   Debug output level {0-7}\n+\n+        xohms                   Touchpanel sensitivity (X-plate resistance)\n+\n+\n+Name:   ov5647\n+Info:   Omnivision OV5647 camera module.\n+        Uses Unicam 1, which is the standard camera connector on most Pi\n+        variants.\n+Load:   dtoverlay=ov5647,<param>=<val>\n+Params: rotation                Mounting rotation of the camera sensor (0 or\n+                                180, default 0)\n+\n+\n+Name:   ov7251\n+Info:   Omnivision OV7251 camera module.\n+        Uses Unicam 1, which is the standard camera connector on most Pi\n+        variants.\n+Load:   dtoverlay=ov7251\n+Params: <None>\n+\n+\n+Name:   ov9281\n+Info:   Omnivision OV9281 camera module.\n+        Uses Unicam 1, which is the standard camera connector on most Pi\n+        variants.\n+Load:   dtoverlay=ov9281\n+Params: <None>\n+\n+\n+Name:   papirus\n+Info:   PaPiRus ePaper Screen by Pi Supply (both HAT and pHAT)\n+Load:   dtoverlay=papirus,<param>=<val>\n+Params: panel                   Display panel (required):\n+                                1.44\": e1144cs021\n+                                2.0\":  e2200cs021\n+                                2.7\":  e2271cs021\n+\n+        speed                   Display SPI bus speed\n+\n+\n+Name:   pca953x\n+Info:   TI PCA953x family of I2C GPIO expanders. Default is for NXP PCA9534.\n+Load:   dtoverlay=pca953x,<param>=<val>\n+Params: addr                    I2C address of expander. Default 0x20.\n+        pca6416                 Select the NXP PCA6416 (16 bit)\n+        pca9505                 Select the NXP PCA9505 (40 bit)\n+        pca9535                 Select the NXP PCA9535 (16 bit)\n+        pca9536                 Select the NXP PCA9536 or TI PCA9536 (4 bit)\n+        pca9537                 Select the NXP PCA9537 (4 bit)\n+        pca9538                 Select the NXP PCA9538 (8 bit)\n+        pca9539                 Select the NXP PCA9539 (16 bit)\n+        pca9554                 Select the NXP PCA9554 (8 bit)\n+        pca9555                 Select the NXP PCA9555 (16 bit)\n+        pca9556                 Select the NXP PCA9556 (8 bit)\n+        pca9557                 Select the NXP PCA9557 (8 bit)\n+        pca9574                 Select the NXP PCA9574 (8 bit)\n+        pca9575                 Select the NXP PCA9575 (16 bit)\n+        pca9698                 Select the NXP PCA9698 (40 bit)\n+        pca16416                Select the NXP PCA16416 (16 bit)\n+        pca16524                Select the NXP PCA16524 (24 bit)\n+        pca19555a               Select the NXP PCA19555A (16 bit)\n+        max7310                 Select the Maxim MAX7310 (8 bit)\n+        max7312                 Select the Maxim MAX7312 (16 bit)\n+        max7313                 Select the Maxim MAX7313 (16 bit)\n+        max7315                 Select the Maxim MAX7315 (8 bit)\n+        pca6107                 Select the TI PCA6107 (8 bit)\n+        tca6408                 Select the TI TCA6408 (8 bit)\n+        tca6416                 Select the TI TCA6416 (16 bit)\n+        tca6424                 Select the TI TCA6424 (24 bit)\n+        tca9539                 Select the TI TCA9539 (16 bit)\n+        tca9554                 Select the TI TCA9554 (8 bit)\n+        cat9554                 Select the Onnn CAT9554 (8 bit)\n+        pca9654                 Select the Onnn PCA9654 (8 bit)\n+        xra1202                 Select the Exar XRA1202 (8 bit)\n+\n+\n+[ The pcf2127-rtc overlay has been deleted. See i2c-rtc. ]\n+\n+\n+[ The pcf8523-rtc overlay has been deleted. See i2c-rtc. ]\n+\n+\n+[ The pcf8563-rtc overlay has been deleted. See i2c-rtc. ]\n+\n+\n+Name:   pi3-act-led\n+Info:   This overlay has been renamed act-led, keeping pi3-act-led as an alias\n+        for backwards compatibility.\n+Load:   <Deprecated>\n+\n+\n+Name:   pi3-disable-bt\n+Info:   This overlay has been renamed disable-bt, keeping pi3-disable-bt as an\n+        alias for backwards compatibility.\n+Load:   <Deprecated>\n+\n+\n+Name:   pi3-disable-wifi\n+Info:   This overlay has been renamed disable-wifi, keeping pi3-disable-wifi as\n+        an alias for backwards compatibility.\n+Load:   <Deprecated>\n+\n+\n+Name:   pi3-miniuart-bt\n+Info:   This overlay has been renamed miniuart-bt, keeping pi3-miniuart-bt as\n+        an alias for backwards compatibility.\n+Load:   <Deprecated>\n+\n+\n+Name:   pibell\n+Info:   Configures the pibell audio card.\n+Load:   dtoverlay=pibell,<param>=<val>\n+Params: alsaname                Set the name as it appears in ALSA (default\n+                                \"PiBell\")\n+\n+\n+Name:   pifacedigital\n+Info:   Configures the PiFace Digital mcp23s17 GPIO port expander.\n+Load:   dtoverlay=pifacedigital,<param>=<val>\n+Params: spi-present-mask        8-bit integer, bitmap indicating MCP23S17 SPI0\n+                                CS0 address. PiFace Digital supports addresses\n+                                0-3, which can be configured with JP1 and JP2.\n+\n+\n+Name:   piglow\n+Info:   Configures the PiGlow by pimoroni.com\n+Load:   dtoverlay=piglow\n+Params: <None>\n+\n+\n+Name:   piscreen\n+Info:   PiScreen display by OzzMaker.com\n+Load:   dtoverlay=piscreen,<param>=<val>\n+Params: speed                   Display SPI bus speed\n+\n+        rotate                  Display rotation {0,90,180,270}\n+\n+        fps                     Delay between frame updates\n+\n+        debug                   Debug output level {0-7}\n+\n+        xohms                   Touchpanel sensitivity (X-plate resistance)\n+\n+\n+Name:   piscreen2r\n+Info:   PiScreen 2 with resistive TP display by OzzMaker.com\n+Load:   dtoverlay=piscreen2r,<param>=<val>\n+Params: speed                   Display SPI bus speed\n+\n+        rotate                  Display rotation {0,90,180,270}\n+\n+        fps                     Delay between frame updates\n+\n+        debug                   Debug output level {0-7}\n+\n+        xohms                   Touchpanel sensitivity (X-plate resistance)\n+\n+\n+Name:   pisound\n+Info:   Configures the Blokas Labs pisound card\n+Load:   dtoverlay=pisound\n+Params: <None>\n+\n+\n+Name:   pitft22\n+Info:   Adafruit PiTFT 2.2\" screen\n+Load:   dtoverlay=pitft22,<param>=<val>\n+Params: speed                   Display SPI bus speed\n+\n+        rotate                  Display rotation {0,90,180,270}\n+\n+        fps                     Delay between frame updates\n+\n+        debug                   Debug output level {0-7}\n+\n+\n+Name:   pitft28-capacitive\n+Info:   Adafruit PiTFT 2.8\" capacitive touch screen\n+Load:   dtoverlay=pitft28-capacitive,<param>=<val>\n+Params: speed                   Display SPI bus speed\n+\n+        rotate                  Display rotation {0,90,180,270}\n+\n+        fps                     Delay between frame updates\n+\n+        debug                   Debug output level {0-7}\n+\n+        touch-sizex             Touchscreen size x (default 240)\n+\n+        touch-sizey             Touchscreen size y (default 320)\n+\n+        touch-invx              Touchscreen inverted x axis\n+\n+        touch-invy              Touchscreen inverted y axis\n+\n+        touch-swapxy            Touchscreen swapped x y axis\n+\n+\n+Name:   pitft28-resistive\n+Info:   Adafruit PiTFT 2.8\" resistive touch screen\n+Load:   dtoverlay=pitft28-resistive,<param>=<val>\n+Params: speed                   Display SPI bus speed\n+\n+        rotate                  Display rotation {0,90,180,270}\n+\n+        fps                     Delay between frame updates\n+\n+        debug                   Debug output level {0-7}\n+\n+\n+Name:   pitft35-resistive\n+Info:   Adafruit PiTFT 3.5\" resistive touch screen\n+Load:   dtoverlay=pitft35-resistive,<param>=<val>\n+Params: speed                   Display SPI bus speed\n+\n+        rotate                  Display rotation {0,90,180,270}\n+\n+        fps                     Delay between frame updates\n+\n+        debug                   Debug output level {0-7}\n+\n+\n+Name:   pps-gpio\n+Info:   Configures the pps-gpio (pulse-per-second time signal via GPIO).\n+Load:   dtoverlay=pps-gpio,<param>=<val>\n+Params: gpiopin                 Input GPIO (default \"18\")\n+        assert_falling_edge     When present, assert is indicated by a falling\n+                                edge, rather than by a rising edge (default\n+                                off)\n+        capture_clear           Generate clear events on the trailing edge\n+                                (default off)\n+\n+\n+Name:   pwm\n+Info:   Configures a single PWM channel\n+        Legal pin,function combinations for each channel:\n+          PWM0: 12,4(Alt0) 18,2(Alt5) 40,4(Alt0)            52,5(Alt1)\n+          PWM1: 13,4(Alt0) 19,2(Alt5) 41,4(Alt0) 45,4(Alt0) 53,5(Alt1)\n+        N.B.:\n+          1) Pin 18 is the only one available on all platforms, and\n+             it is the one used by the I2S audio interface.\n+             Pins 12 and 13 might be better choices on an A+, B+ or Pi2.\n+          2) The onboard analogue audio output uses both PWM channels.\n+          3) So be careful mixing audio and PWM.\n+          4) Currently the clock must have been enabled and configured\n+             by other means.\n+Load:   dtoverlay=pwm,<param>=<val>\n+Params: pin                     Output pin (default 18) - see table\n+        func                    Pin function (default 2 = Alt5) - see above\n+        clock                   PWM clock frequency (informational)\n+\n+\n+Name:   pwm-2chan\n+Info:   Configures both PWM channels\n+        Legal pin,function combinations for each channel:\n+          PWM0: 12,4(Alt0) 18,2(Alt5) 40,4(Alt0)            52,5(Alt1)\n+          PWM1: 13,4(Alt0) 19,2(Alt5) 41,4(Alt0) 45,4(Alt0) 53,5(Alt1)\n+        N.B.:\n+          1) Pin 18 is the only one available on all platforms, and\n+             it is the one used by the I2S audio interface.\n+             Pins 12 and 13 might be better choices on an A+, B+ or Pi2.\n+          2) The onboard analogue audio output uses both PWM channels.\n+          3) So be careful mixing audio and PWM.\n+          4) Currently the clock must have been enabled and configured\n+             by other means.\n+Load:   dtoverlay=pwm-2chan,<param>=<val>\n+Params: pin                     Output pin (default 18) - see table\n+        pin2                    Output pin for other channel (default 19)\n+        func                    Pin function (default 2 = Alt5) - see above\n+        func2                   Function for pin2 (default 2 = Alt5)\n+        clock                   PWM clock frequency (informational)\n+\n+\n+Name:   pwm-ir-tx\n+Info:   Use GPIO pin as pwm-assisted infrared transmitter output.\n+        This is an alternative to \"gpio-ir-tx\". pwm-ir-tx makes use\n+        of PWM0 to reduce the CPU load during transmission compared to\n+        gpio-ir-tx which uses bit-banging.\n+        Legal pin,function combinations are:\n+          12,4(Alt0) 18,2(Alt5) 40,4(Alt0) 52,5(Alt1)\n+Load:   dtoverlay=pwm-ir-tx,<param>=<val>\n+Params: gpio_pin                Output GPIO (default 18)\n+\n+        func                    Pin function (default 2 = Alt5)\n+\n+\n+Name:   qca7000\n+Info:   I2SE's Evaluation Board for PLC Stamp micro\n+Load:   dtoverlay=qca7000,<param>=<val>\n+Params: int_pin                 GPIO pin for interrupt signal (default 23)\n+\n+        speed                   SPI bus speed (default 12 MHz)\n+\n+\n+Name:   rotary-encoder\n+Info:   Overlay for GPIO connected rotary encoder.\n+Load:   dtoverlay=rotary-encoder,<param>=<val>\n+Params: pin_a                   GPIO connected to rotary encoder channel A\n+                                (default 4).\n+        pin_b                   GPIO connected to rotary encoder channel B\n+                                (default 17).\n+        relative_axis           register a relative axis rather than an\n+                                absolute one. Relative axis will only\n+                                generate +1/-1 events on the input device,\n+                                hence no steps need to be passed.\n+        linux_axis              the input subsystem axis to map to this\n+                                rotary encoder. Defaults to 0 (ABS_X / REL_X)\n+        rollover                Automatic rollover when the rotary value\n+                                becomes greater than the specified steps or\n+                                smaller than 0. For absolute axis only.\n+        steps-per-period        Number of steps (stable states) per period.\n+                                The values have the following meaning:\n+                                1: Full-period mode (default)\n+                                2: Half-period mode\n+                                4: Quarter-period mode\n+        steps                   Number of steps in a full turnaround of the\n+                                encoder. Only relevant for absolute axis.\n+                                Defaults to 24 which is a typical value for\n+                                such devices.\n+        wakeup                  Boolean, rotary encoder can wake up the\n+                                system.\n+        encoding                String, the method used to encode steps.\n+                                Supported are \"gray\" (the default and more\n+                                common) and \"binary\".\n+\n+\n+Name:   rpi-backlight\n+Info:   Raspberry Pi official display backlight driver\n+Load:   dtoverlay=rpi-backlight\n+Params: <None>\n+\n+\n+Name:   rpi-cirrus-wm5102\n+Info:   Configures the Cirrus Logic Audio Card\n+Load:   dtoverlay=rpi-cirrus-wm5102\n+Params: <None>\n+\n+\n+Name:   rpi-dac\n+Info:   Configures the RPi DAC audio card\n+Load:   dtoverlay=rpi-dac\n+Params: <None>\n+\n+\n+Name:   rpi-display\n+Info:   RPi-Display - 2.8\" Touch Display by Watterott\n+Load:   dtoverlay=rpi-display,<param>=<val>\n+Params: speed                   Display SPI bus speed\n+        rotate                  Display rotation {0,90,180,270}\n+        fps                     Delay between frame updates\n+        debug                   Debug output level {0-7}\n+        xohms                   Touchpanel sensitivity (X-plate resistance)\n+        swapxy                  Swap x and y axis\n+        backlight               Change backlight GPIO pin {e.g. 12, 18}\n+\n+\n+Name:   rpi-ft5406\n+Info:   Official Raspberry Pi display touchscreen\n+Load:   dtoverlay=rpi-ft5406,<param>=<val>\n+Params: touchscreen-size-x      Touchscreen X resolution (default 800)\n+        touchscreen-size-y      Touchscreen Y resolution (default 600);\n+        touchscreen-inverted-x  Invert touchscreen X coordinates (default 0);\n+        touchscreen-inverted-y  Invert touchscreen Y coordinates (default 0);\n+        touchscreen-swapped-x-y Swap X and Y cordinates (default 0);\n+\n+\n+Name:   rpi-poe\n+Info:   Raspberry Pi PoE HAT fan\n+Load:   dtoverlay=rpi-poe,<param>[=<val>]\n+Params: poe_fan_temp0           Temperature (in millicelcius) at which the fan\n+                                turns on (default 40000)\n+        poe_fan_temp0_hyst      Temperature delta (in millicelcius) at which\n+                                the fan turns off (default 2000)\n+        poe_fan_temp1           Temperature (in millicelcius) at which the fan\n+                                speeds up (default 45000)\n+        poe_fan_temp1_hyst      Temperature delta (in millicelcius) at which\n+                                the fan slows down (default 2000)\n+        poe_fan_temp2           Temperature (in millicelcius) at which the fan\n+                                speeds up (default 50000)\n+        poe_fan_temp2_hyst      Temperature delta (in millicelcius) at which\n+                                the fan slows down (default 2000)\n+        poe_fan_temp3           Temperature (in millicelcius) at which the fan\n+                                speeds up (default 55000)\n+        poe_fan_temp3_hyst      Temperature delta (in millicelcius) at which\n+                                the fan slows down (default 5000)\n+\n+\n+Name:   rpi-proto\n+Info:   Configures the RPi Proto audio card\n+Load:   dtoverlay=rpi-proto\n+Params: <None>\n+\n+\n+Name:   rpi-sense\n+Info:   Raspberry Pi Sense HAT\n+Load:   dtoverlay=rpi-sense\n+Params: <None>\n+\n+\n+Name:   rpi-tv\n+Info:   Raspberry Pi TV HAT\n+Load:   dtoverlay=rpi-tv\n+Params: <None>\n+\n+\n+Name:   rpivid-v4l2\n+Info:   Load the V4L2 stateless video decoder driver for the HEVC block,\n+        disabling the memory mapped devices in the process.\n+Load:   dtoverlay=rpivid-v4l2\n+Params: <None>\n+\n+\n+Name:   rra-digidac1-wm8741-audio\n+Info:   Configures the Red Rocks Audio DigiDAC1 soundcard\n+Load:   dtoverlay=rra-digidac1-wm8741-audio\n+Params: <None>\n+\n+\n+Name:   sainsmart18\n+Info:   Overlay for the SPI-connected Sainsmart 1.8\" display (based on the\n+        ST7735R chip).\n+Load:   dtoverlay=sainsmart18,<param>=<val>\n+Params: rotate                  Display rotation {0,90,180,270}\n+        speed                   SPI bus speed in Hz (default 4000000)\n+        fps                     Display frame rate in Hz\n+        bgr                     Enable BGR mode (default off)\n+        debug                   Debug output level {0-7}\n+        dc_pin                  GPIO pin for D/C (default 24)\n+        reset_pin               GPIO pin for RESET (default 25)\n+\n+\n+Name:   sc16is750-i2c\n+Info:   Overlay for the NXP SC16IS750 UART with I2C Interface\n+        Enables the chip on I2C1 at 0x48 (or the \"addr\" parameter value). To\n+        select another address, please refer to table 10 in reference manual.\n+Load:   dtoverlay=sc16is750-i2c,<param>=<val>\n+Params: int_pin                 GPIO used for IRQ (default 24)\n+        addr                    Address (default 0x48)\n+        xtal                    On-board crystal frequency (default 14745600)\n+\n+\n+Name:   sc16is752-i2c\n+Info:   Overlay for the NXP SC16IS752 dual UART with I2C Interface\n+        Enables the chip on I2C1 at 0x48 (or the \"addr\" parameter value). To\n+        select another address, please refer to table 10 in reference manual.\n+Load:   dtoverlay=sc16is752-i2c,<param>=<val>\n+Params: int_pin                 GPIO used for IRQ (default 24)\n+        addr                    Address (default 0x48)\n+        xtal                    On-board crystal frequency (default 14745600)\n+\n+\n+Name:   sc16is752-spi0\n+Info:   Overlay for the NXP SC16IS752 Dual UART with SPI Interface\n+        Enables the chip on SPI0.\n+Load:   dtoverlay=sc16is752-spi0,<param>=<val>\n+Params: int_pin                 GPIO used for IRQ (default 24)\n+        xtal                    On-board crystal frequency (default 14745600)\n+\n+\n+Name:   sc16is752-spi1\n+Info:   Overlay for the NXP SC16IS752 Dual UART with SPI Interface\n+        Enables the chip on SPI1.\n+        N.B.: spi1 is only accessible on devices with a 40pin header, eg:\n+              A+, B+, Zero and PI2 B; as well as the Compute Module.\n+\n+Load:   dtoverlay=sc16is752-spi1,<param>=<val>\n+Params: int_pin                 GPIO used for IRQ (default 24)\n+        xtal                    On-board crystal frequency (default 14745600)\n+\n+\n+Name:   sdhost\n+Info:   Selects the bcm2835-sdhost SD/MMC driver, optionally with overclock.\n+        N.B. This overlay is designed for situations where the mmc driver is\n+        the default, so it disables the other (mmc) interface - this will kill\n+        WiFi on a Pi3. If this isn't what you want, either use the sdtweak\n+        overlay or the new sd_* dtparams of the base DTBs.\n+Load:   dtoverlay=sdhost,<param>=<val>\n+Params: overclock_50            Clock (in MHz) to use when the MMC framework\n+                                requests 50MHz\n+\n+        force_pio               Disable DMA support (default off)\n+\n+        pio_limit               Number of blocks above which to use DMA\n+                                (default 1)\n+\n+        debug                   Enable debug output (default off)\n+\n+\n+Name:   sdio\n+Info:   Selects the bcm2835-sdhost SD/MMC driver, optionally with overclock,\n+        and enables SDIO via GPIOs 22-27. An example of use in 1-bit mode is\n+        \"dtoverlay=sdio,bus_width=1,gpios_22_25\"\n+Load:   dtoverlay=sdio,<param>=<val>\n+Params: sdio_overclock          SDIO Clock (in MHz) to use when the MMC\n+                                framework requests 50MHz\n+\n+        poll_once               Disable SDIO-device polling every second\n+                                (default on: polling once at boot-time)\n+\n+        bus_width               Set the SDIO host bus width (default 4 bits)\n+\n+        gpios_22_25             Select GPIOs 22-25 for 1-bit mode. Must be used\n+                                with bus_width=1. This replaces the sdio-1bit\n+                                overlay, which is now deprecated.\n+\n+        gpios_34_37             Select GPIOs 34-37 for 1-bit mode. Must be used\n+                                with bus_width=1.\n+\n+        gpios_34_39             Select GPIOs 34-39 for 4-bit mode. Must be used\n+                                with bus_width=4 (the default).\n+\n+\n+Name:   sdio-1bit\n+Info:   This overlay is now deprecated. Use\n+        \"dtoverlay=sdio,bus_width=1,gpios_22_25\" instead.\n+Load:   <Deprecated>\n+\n+\n+Name:   sdtweak\n+Info:   Tunes the bcm2835-sdhost SD/MMC driver\n+        N.B. This functionality is now available via the sd_* dtparams in the\n+        base DTB.\n+Load:   dtoverlay=sdtweak,<param>=<val>\n+Params: overclock_50            Clock (in MHz) to use when the MMC framework\n+                                requests 50MHz\n+\n+        force_pio               Disable DMA support (default off)\n+\n+        pio_limit               Number of blocks above which to use DMA\n+                                (default 1)\n+\n+        debug                   Enable debug output (default off)\n+\n+        poll_once               Looks for a card once after booting. Useful\n+                                for network booting scenarios to avoid the\n+                                overhead of continuous polling. N.B. Using\n+                                this option restricts the system to using a\n+                                single card per boot (or none at all).\n+                                (default off)\n+\n+        enable                  Set to off to completely disable the interface\n+                                (default on)\n+\n+\n+Name:   sh1106-spi\n+Info:   Overlay for SH1106 OLED via SPI using fbtft staging driver.\n+Load:   dtoverlay=sh1106-spi,<param>=<val>\n+Params: speed                   SPI bus speed (default 4000000)\n+        rotate                  Display rotation (0, 90, 180 or 270; default 0)\n+        fps                     Delay between frame updates (default 25)\n+        debug                   Debug output level (0-7; default 0)\n+        dc_pin                  GPIO pin for D/C (default 24)\n+        reset_pin               GPIO pin for RESET (default 25)\n+        height                  Display height (32 or 64; default 64)\n+\n+\n+Name:   smi\n+Info:   Enables the Secondary Memory Interface peripheral. Uses GPIOs 2-25!\n+Load:   dtoverlay=smi\n+Params: <None>\n+\n+\n+Name:   smi-dev\n+Info:   Enables the userspace interface for the SMI driver\n+Load:   dtoverlay=smi-dev\n+Params: <None>\n+\n+\n+Name:   smi-nand\n+Info:   Enables access to NAND flash via the SMI interface\n+Load:   dtoverlay=smi-nand\n+Params: <None>\n+\n+\n+Name:   spi-gpio35-39\n+Info:   Move SPI function block to GPIO 35 to 39\n+Load:   dtoverlay=spi-gpio35-39\n+Params: <None>\n+\n+\n+Name:   spi-gpio40-45\n+Info:   Move SPI function block to GPIOs 40 to 45\n+Load:   dtoverlay=spi-gpio40-45\n+Params: <None>\n+\n+\n+Name:   spi-rtc\n+Info:   Adds support for a number of SPI Real Time Clock devices\n+Load:   dtoverlay=spi-rtc,<param>=<val>\n+Params: pcf2123                 Select the PCF2123 device\n+\n+\n+Name:   spi0-1cs\n+Info:   Only use one CS pin for SPI0\n+Load:   dtoverlay=spi0-1cs,<param>=<val>\n+Params: cs0_pin                 GPIO pin for CS0 (default 8)\n+        no_miso                 Don't claim and use the MISO pin (9), freeing\n+                                it for other uses.\n+\n+\n+Name:   spi0-2cs\n+Info:   Change the CS pins for SPI0\n+Load:   dtoverlay=spi0-2cs,<param>=<val>\n+Params: cs0_pin                 GPIO pin for CS0 (default 8)\n+        cs1_pin                 GPIO pin for CS1 (default 7)\n+        no_miso                 Don't claim and use the MISO pin (9), freeing\n+                                it for other uses.\n+\n+\n+Name:   spi0-cs\n+Info:   This overlay has been renamed spi0-2cs, keeping spi0-cs as an\n+        alias for backwards compatibility.\n+Load:   <Deprecated>\n+\n+\n+Name:   spi0-hw-cs\n+Info:   This overlay has been deprecated and removed because it is no longer\n+        necessary and has been seen to prevent spi0 from working.\n+Load:   <Deprecated>\n+\n+\n+Name:   spi1-1cs\n+Info:   Enables spi1 with a single chip select (CS) line and associated spidev\n+        dev node. The gpio pin number for the CS line and spidev device node\n+        creation are configurable.\n+        N.B.: spi1 is only accessible on devices with a 40pin header, eg:\n+              A+, B+, Zero and PI2 B; as well as the Compute Module.\n+Load:   dtoverlay=spi1-1cs,<param>=<val>\n+Params: cs0_pin                 GPIO pin for CS0 (default 18 - BCM SPI1_CE0).\n+        cs0_spidev              Set to 'disabled' to stop the creation of a\n+                                userspace device node /dev/spidev1.0 (default\n+                                is 'okay' or enabled).\n+\n+\n+Name:   spi1-2cs\n+Info:   Enables spi1 with two chip select (CS) lines and associated spidev\n+        dev nodes. The gpio pin numbers for the CS lines and spidev device node\n+        creation are configurable.\n+        N.B.: spi1 is only accessible on devices with a 40pin header, eg:\n+              A+, B+, Zero and PI2 B; as well as the Compute Module.\n+Load:   dtoverlay=spi1-2cs,<param>=<val>\n+Params: cs0_pin                 GPIO pin for CS0 (default 18 - BCM SPI1_CE0).\n+        cs1_pin                 GPIO pin for CS1 (default 17 - BCM SPI1_CE1).\n+        cs0_spidev              Set to 'disabled' to stop the creation of a\n+                                userspace device node /dev/spidev1.0 (default\n+                                is 'okay' or enabled).\n+        cs1_spidev              Set to 'disabled' to stop the creation of a\n+                                userspace device node /dev/spidev1.1 (default\n+                                is 'okay' or enabled).\n+\n+\n+Name:   spi1-3cs\n+Info:   Enables spi1 with three chip select (CS) lines and associated spidev\n+        dev nodes. The gpio pin numbers for the CS lines and spidev device node\n+        creation are configurable.\n+        N.B.: spi1 is only accessible on devices with a 40pin header, eg:\n+              A+, B+, Zero and PI2 B; as well as the Compute Module.\n+Load:   dtoverlay=spi1-3cs,<param>=<val>\n+Params: cs0_pin                 GPIO pin for CS0 (default 18 - BCM SPI1_CE0).\n+        cs1_pin                 GPIO pin for CS1 (default 17 - BCM SPI1_CE1).\n+        cs2_pin                 GPIO pin for CS2 (default 16 - BCM SPI1_CE2).\n+        cs0_spidev              Set to 'disabled' to stop the creation of a\n+                                userspace device node /dev/spidev1.0 (default\n+                                is 'okay' or enabled).\n+        cs1_spidev              Set to 'disabled' to stop the creation of a\n+                                userspace device node /dev/spidev1.1 (default\n+                                is 'okay' or enabled).\n+        cs2_spidev              Set to 'disabled' to stop the creation of a\n+                                userspace device node /dev/spidev1.2 (default\n+                                is 'okay' or enabled).\n+\n+\n+Name:   spi2-1cs\n+Info:   Enables spi2 with a single chip select (CS) line and associated spidev\n+        dev node. The gpio pin number for the CS line and spidev device node\n+        creation are configurable.\n+        N.B.: spi2 is only accessible with the Compute Module.\n+Load:   dtoverlay=spi2-1cs,<param>=<val>\n+Params: cs0_pin                 GPIO pin for CS0 (default 43 - BCM SPI2_CE0).\n+        cs0_spidev              Set to 'disabled' to stop the creation of a\n+                                userspace device node /dev/spidev2.0 (default\n+                                is 'okay' or enabled).\n+\n+\n+Name:   spi2-2cs\n+Info:   Enables spi2 with two chip select (CS) lines and associated spidev\n+        dev nodes. The gpio pin numbers for the CS lines and spidev device node\n+        creation are configurable.\n+        N.B.: spi2 is only accessible with the Compute Module.\n+Load:   dtoverlay=spi2-2cs,<param>=<val>\n+Params: cs0_pin                 GPIO pin for CS0 (default 43 - BCM SPI2_CE0).\n+        cs1_pin                 GPIO pin for CS1 (default 44 - BCM SPI2_CE1).\n+        cs0_spidev              Set to 'disabled' to stop the creation of a\n+                                userspace device node /dev/spidev2.0 (default\n+                                is 'okay' or enabled).\n+        cs1_spidev              Set to 'disabled' to stop the creation of a\n+                                userspace device node /dev/spidev2.1 (default\n+                                is 'okay' or enabled).\n+\n+\n+Name:   spi2-3cs\n+Info:   Enables spi2 with three chip select (CS) lines and associated spidev\n+        dev nodes. The gpio pin numbers for the CS lines and spidev device node\n+        creation are configurable.\n+        N.B.: spi2 is only accessible with the Compute Module.\n+Load:   dtoverlay=spi2-3cs,<param>=<val>\n+Params: cs0_pin                 GPIO pin for CS0 (default 43 - BCM SPI2_CE0).\n+        cs1_pin                 GPIO pin for CS1 (default 44 - BCM SPI2_CE1).\n+        cs2_pin                 GPIO pin for CS2 (default 45 - BCM SPI2_CE2).\n+        cs0_spidev              Set to 'disabled' to stop the creation of a\n+                                userspace device node /dev/spidev2.0 (default\n+                                is 'okay' or enabled).\n+        cs1_spidev              Set to 'disabled' to stop the creation of a\n+                                userspace device node /dev/spidev2.1 (default\n+                                is 'okay' or enabled).\n+        cs2_spidev              Set to 'disabled' to stop the creation of a\n+                                userspace device node /dev/spidev2.2 (default\n+                                is 'okay' or enabled).\n+\n+\n+Name:   spi3-1cs\n+Info:   Enables spi3 with a single chip select (CS) line and associated spidev\n+        dev node. The gpio pin number for the CS line and spidev device node\n+        creation are configurable. BCM2711 only.\n+Load:   dtoverlay=spi3-1cs,<param>=<val>\n+Params: cs0_pin                 GPIO pin for CS0 (default 0 - BCM SPI3_CE0).\n+        cs0_spidev              Set to 'off' to prevent the creation of a\n+                                userspace device node /dev/spidev3.0 (default\n+                                is 'on' or enabled).\n+\n+\n+Name:   spi3-2cs\n+Info:   Enables spi3 with two chip select (CS) lines and associated spidev\n+        dev nodes. The gpio pin numbers for the CS lines and spidev device node\n+        creation are configurable. BCM2711 only.\n+Load:   dtoverlay=spi3-2cs,<param>=<val>\n+Params: cs0_pin                 GPIO pin for CS0 (default 0 - BCM SPI3_CE0).\n+        cs1_pin                 GPIO pin for CS1 (default 24 - BCM SPI3_CE1).\n+        cs0_spidev              Set to 'off' to prevent the creation of a\n+                                userspace device node /dev/spidev3.0 (default\n+                                is 'on' or enabled).\n+        cs1_spidev              Set to 'off' to prevent the creation of a\n+                                userspace device node /dev/spidev3.1 (default\n+                                is 'on' or enabled).\n+\n+\n+Name:   spi4-1cs\n+Info:   Enables spi4 with a single chip select (CS) line and associated spidev\n+        dev node. The gpio pin number for the CS line and spidev device node\n+        creation are configurable. BCM2711 only.\n+Load:   dtoverlay=spi4-1cs,<param>=<val>\n+Params: cs0_pin                 GPIO pin for CS0 (default 4 - BCM SPI4_CE0).\n+        cs0_spidev              Set to 'off' to prevent the creation of a\n+                                userspace device node /dev/spidev4.0 (default\n+                                is 'on' or enabled).\n+\n+\n+Name:   spi4-2cs\n+Info:   Enables spi4 with two chip select (CS) lines and associated spidev\n+        dev nodes. The gpio pin numbers for the CS lines and spidev device node\n+        creation are configurable. BCM2711 only.\n+Load:   dtoverlay=spi4-2cs,<param>=<val>\n+Params: cs0_pin                 GPIO pin for CS0 (default 4 - BCM SPI4_CE0).\n+        cs1_pin                 GPIO pin for CS1 (default 25 - BCM SPI4_CE1).\n+        cs0_spidev              Set to 'off' to prevent the creation of a\n+                                userspace device node /dev/spidev4.0 (default\n+                                is 'on' or enabled).\n+        cs1_spidev              Set to 'off' to prevent the creation of a\n+                                userspace device node /dev/spidev4.1 (default\n+                                is 'on' or enabled).\n+\n+\n+Name:   spi5-1cs\n+Info:   Enables spi5 with a single chip select (CS) line and associated spidev\n+        dev node. The gpio pin numbers for the CS lines and spidev device node\n+        creation are configurable. BCM2711 only.\n+Load:   dtoverlay=spi5-1cs,<param>=<val>\n+Params: cs0_pin                 GPIO pin for CS0 (default 12 - BCM SPI5_CE0).\n+        cs0_spidev              Set to 'off' to prevent the creation of a\n+                                userspace device node /dev/spidev5.0 (default\n+                                is 'on' or enabled).\n+\n+\n+Name:   spi5-2cs\n+Info:   Enables spi5 with two chip select (CS) lines and associated spidev\n+        dev nodes. The gpio pin numbers for the CS lines and spidev device node\n+        creation are configurable. BCM2711 only.\n+Load:   dtoverlay=spi5-2cs,<param>=<val>\n+Params: cs0_pin                 GPIO pin for CS0 (default 12 - BCM SPI5_CE0).\n+        cs1_pin                 GPIO pin for CS1 (default 26 - BCM SPI5_CE1).\n+        cs0_spidev              Set to 'off' to prevent the creation of a\n+                                userspace device node /dev/spidev5.0 (default\n+                                is 'on' or enabled).\n+        cs1_spidev              Set to 'off' to prevent the creation of a\n+                                userspace device node /dev/spidev5.1 (default\n+                                is 'on' or enabled).\n+\n+\n+Name:   spi6-1cs\n+Info:   Enables spi6 with a single chip select (CS) line and associated spidev\n+        dev node. The gpio pin number for the CS line and spidev device node\n+        creation are configurable. BCM2711 only.\n+Load:   dtoverlay=spi6-1cs,<param>=<val>\n+Params: cs0_pin                 GPIO pin for CS0 (default 18 - BCM SPI6_CE0).\n+        cs0_spidev              Set to 'off' to prevent the creation of a\n+                                userspace device node /dev/spidev6.0 (default\n+                                is 'on' or enabled).\n+\n+\n+Name:   spi6-2cs\n+Info:   Enables spi6 with two chip select (CS) lines and associated spidev\n+        dev nodes. The gpio pin numbers for the CS lines and spidev device node\n+        creation are configurable. BCM2711 only.\n+Load:   dtoverlay=spi6-2cs,<param>=<val>\n+Params: cs0_pin                 GPIO pin for CS0 (default 18 - BCM SPI6_CE0).\n+        cs1_pin                 GPIO pin for CS1 (default 27 - BCM SPI6_CE1).\n+        cs0_spidev              Set to 'off' to prevent the creation of a\n+                                userspace device node /dev/spidev6.0 (default\n+                                is 'on' or enabled).\n+        cs1_spidev              Set to 'off' to prevent the creation of a\n+                                userspace device node /dev/spidev6.1 (default\n+                                is 'on' or enabled).\n+\n+\n+Name:   ssd1306\n+Info:   Overlay for activation of SSD1306 over I2C OLED display framebuffer.\n+Load:   dtoverlay=ssd1306,<param>=<val>\n+Params: address                 Location in display memory of first character.\n+                                (default=0)\n+        width                   Width of display. (default=128)\n+        height                  Height of display. (default=64)\n+        offset                  virtual channel a. (default=0)\n+        normal                  Has no effect on displays tested. (default=not\n+                                set)\n+        sequential              Set this if every other scan line is missing.\n+                                (default=not set)\n+        remapped                Set this if display is garbled. (default=not\n+                                set)\n+        inverted                Set this if display is inverted and mirrored.\n+                                (default=not set)\n+\n+        Examples:\n+        Typical usage for 128x64 display: dtoverlay=ssd1306,inverted\n+\n+        Typical usage for 128x32 display: dtoverlay=ssd1306,inverted,sequential\n+\n+        i2c_baudrate=400000 will speed up the display.\n+\n+        i2c_baudrate=1000000 seems to work even though it's not officially\n+        supported by the hardware, and is faster still.\n+\n+        For more information refer to the device datasheet at:\n+        https://cdn-shop.adafruit.com/datasheets/SSD1306.pdf\n+\n+\n+Name:   ssd1306-spi\n+Info:   Overlay for SSD1306 OLED via SPI using fbtft staging driver.\n+Load:   dtoverlay=ssd1306-spi,<param>=<val>\n+Params: speed                   SPI bus speed (default 10000000)\n+        rotate                  Display rotation (0, 90, 180 or 270; default 0)\n+        fps                     Delay between frame updates (default 25)\n+        debug                   Debug output level (0-7; default 0)\n+        dc_pin                  GPIO pin for D/C (default 24)\n+        reset_pin               GPIO pin for RESET (default 25)\n+        height                  Display height (32 or 64; default 64)\n+\n+\n+Name:   ssd1351-spi\n+Info:   Overlay for SSD1351 OLED via SPI using fbtft staging driver.\n+Load:   dtoverlay=ssd1351-spi,<param>=<val>\n+Params: speed                   SPI bus speed (default 4500000)\n+        rotate                  Display rotation (0, 90, 180 or 270; default 0)\n+        fps                     Delay between frame updates (default 25)\n+        debug                   Debug output level (0-7; default 0)\n+        dc_pin                  GPIO pin for D/C (default 24)\n+        reset_pin               GPIO pin for RESET (default 25)\n+\n+\n+Name:   superaudioboard\n+Info:   Configures the SuperAudioBoard sound card\n+Load:   dtoverlay=superaudioboard,<param>=<val>\n+Params: gpiopin                 GPIO pin for codec reset\n+\n+\n+Name:   sx150x\n+Info:   Configures the Semtech SX150X I2C GPIO expanders.\n+Load:   dtoverlay=sx150x,<param>=<val>\n+Params: sx150<x>-<n>-<m>        Enables SX150X device on I2C#<n> with slave\n+                                address <m>. <x> may be 1-9. <n> may be 0 or 1.\n+                                Permissible values of <m> (which is denoted in\n+                                hex) depend on the device variant. For SX1501,\n+                                SX1502, SX1504 and SX1505, <m> may be 20 or 21.\n+                                For SX1503 and SX1506, <m> may be 20. For\n+                                SX1507 and SX1509, <m> may be 3E, 3F, 70 or 71.\n+                                For SX1508, <m> may be 20, 21, 22 or 23.\n+\n+        sx150<x>-<n>-<m>-int-gpio\n+                                Integer, enables interrupts on SX150X device on\n+                                I2C#<n> with slave address <m>, specifies\n+                                the GPIO pin to which NINT output of SX150X is\n+                                connected.\n+\n+\n+Name:   tc358743\n+Info:   Toshiba TC358743 HDMI to CSI-2 bridge chip.\n+        Uses Unicam 1, which is the standard camera connector on most Pi\n+        variants.\n+Load:   dtoverlay=tc358743,<param>=<val>\n+Params: 4lane                   Use 4 lanes (only applicable to Compute Modules\n+                                CAM1 connector).\n+\n+        link-frequency          Set the link frequency. Only values of 297000000\n+                                (574Mbit/s) and 486000000 (972Mbit/s - default)\n+                                are supported by the driver.\n+\n+\n+Name:   tc358743-audio\n+Info:   Used in combination with the tc358743-fast overlay to route the audio\n+        from the TC358743 over I2S to the Pi.\n+        Wiring is LRCK/WFS to GPIO 19, BCK/SCK to GPIO 18, and DATA/SD to GPIO\n+        20.\n+Load:   dtoverlay=tc358743-audio,<param>=<val>\n+Params: card-name               Override the default, \"tc358743\", card name.\n+\n+\n+Name:   tinylcd35\n+Info:   3.5\" Color TFT Display by www.tinylcd.com\n+        Options: Touch, RTC, keypad\n+Load:   dtoverlay=tinylcd35,<param>=<val>\n+Params: speed                   Display SPI bus speed\n+\n+        rotate                  Display rotation {0,90,180,270}\n+\n+        fps                     Delay between frame updates\n+\n+        debug                   Debug output level {0-7}\n+\n+        touch                   Enable touch panel\n+\n+        touchgpio               Touch controller IRQ GPIO\n+\n+        xohms                   Touchpanel: Resistance of X-plate in ohms\n+\n+        rtc-pcf                 PCF8563 Real Time Clock\n+\n+        rtc-ds                  DS1307 Real Time Clock\n+\n+        keypad                  Enable keypad\n+\n+        Examples:\n+            Display with touchpanel, PCF8563 RTC and keypad:\n+                dtoverlay=tinylcd35,touch,rtc-pcf,keypad\n+            Old touch display:\n+                dtoverlay=tinylcd35,touch,touchgpio=3\n+\n+\n+Name:   tpm-slb9670\n+Info:   Enables support for Infineon SLB9670 Trusted Platform Module add-on\n+        boards, which can be used as a secure key storage and hwrng,\n+        available as \"Iridium SLB9670\" by Infineon and \"LetsTrust TPM\" by pi3g.\n+Load:   dtoverlay=tpm-slb9670\n+Params: <None>\n+\n+\n+Name:   uart0\n+Info:   Change the pin usage of uart0\n+Load:   dtoverlay=uart0,<param>=<val>\n+Params: txd0_pin                GPIO pin for TXD0 (14, 32 or 36 - default 14)\n+\n+        rxd0_pin                GPIO pin for RXD0 (15, 33 or 37 - default 15)\n+\n+        pin_func                Alternative pin function - 4(Alt0) for 14&15,\n+                                7(Alt3) for 32&33, 6(Alt2) for 36&37\n+\n+\n+Name:   uart1\n+Info:   Change the pin usage of uart1\n+Load:   dtoverlay=uart1,<param>=<val>\n+Params: txd1_pin                GPIO pin for TXD1 (14, 32 or 40 - default 14)\n+\n+        rxd1_pin                GPIO pin for RXD1 (15, 33 or 41 - default 15)\n+\n+\n+Name:   uart2\n+Info:   Enable uart 2 on GPIOs 0-3. BCM2711 only.\n+Load:   dtoverlay=uart2,<param>\n+Params: ctsrts                  Enable CTS/RTS on GPIOs 2-3 (default off)\n+\n+\n+Name:   uart3\n+Info:   Enable uart 3 on GPIOs 4-7. BCM2711 only.\n+Load:   dtoverlay=uart3,<param>\n+Params: ctsrts                  Enable CTS/RTS on GPIOs 6-7 (default off)\n+\n+\n+Name:   uart4\n+Info:   Enable uart 4 on GPIOs 8-11. BCM2711 only.\n+Load:   dtoverlay=uart4,<param>\n+Params: ctsrts                  Enable CTS/RTS on GPIOs 10-11 (default off)\n+\n+\n+Name:   uart5\n+Info:   Enable uart 5 on GPIOs 12-15. BCM2711 only.\n+Load:   dtoverlay=uart5,<param>\n+Params: ctsrts                  Enable CTS/RTS on GPIOs 14-15 (default off)\n+\n+\n+Name:   udrc\n+Info:   Configures the NW Digital Radio UDRC Hat\n+Load:   dtoverlay=udrc,<param>=<val>\n+Params: alsaname                Name of the ALSA audio device (default \"udrc\")\n+\n+\n+Name:   upstream\n+Info:   Allow usage of downstream .dtb with upstream kernel. Comprises the\n+        vc4-kms-v3d and dwc2 overlays.\n+Load:   dtoverlay=upstream\n+Params: <None>\n+\n+\n+Name:   upstream-aux-interrupt\n+Info:   This overlay has been deprecated and removed because it is no longer\n+        necessary.\n+Load:   <Deprecated>\n+\n+\n+Name:   upstream-pi4\n+Info:   Allow usage of downstream .dtb with upstream kernel on Pi 4. Comprises\n+        the vc4-kms-v3d-pi4 and dwc2 overlays.\n+Load:   dtoverlay=upstream-pi4\n+Params: <None>\n+\n+\n+Name:   vc4-fkms-v3d\n+Info:   Enable Eric Anholt's DRM VC4 V3D driver on top of the dispmanx\n+        display stack.\n+Load:   dtoverlay=vc4-fkms-v3d,<param>\n+Params: cma-512                 CMA is 512MB (needs 1GB)\n+        cma-448                 CMA is 448MB (needs 1GB)\n+        cma-384                 CMA is 384MB (needs 1GB)\n+        cma-320                 CMA is 320MB (needs 1GB)\n+        cma-256                 CMA is 256MB (needs 1GB)\n+        cma-192                 CMA is 192MB (needs 1GB)\n+        cma-128                 CMA is 128MB\n+        cma-96                  CMA is 96MB\n+        cma-64                  CMA is 64MB\n+        cma-size                CMA size in bytes, 4MB aligned\n+        cma-default             Use upstream's default value\n+\n+\n+Name:   vc4-kms-kippah-7inch\n+Info:   Enable the Adafruit DPI Kippah with the 7\" Ontat panel attached.\n+        Requires vc4-kms-v3d to be loaded.\n+Load:   dtoverlay=vc4-kms-kippah-7inch\n+Params: <None>\n+\n+\n+Name:   vc4-kms-v3d\n+Info:   Enable Eric Anholt's DRM VC4 HDMI/HVS/V3D driver.\n+Load:   dtoverlay=vc4-kms-v3d,<param>\n+Params: cma-512                 CMA is 512MB (needs 1GB)\n+        cma-448                 CMA is 448MB (needs 1GB)\n+        cma-384                 CMA is 384MB (needs 1GB)\n+        cma-320                 CMA is 320MB (needs 1GB)\n+        cma-256                 CMA is 256MB (needs 1GB)\n+        cma-192                 CMA is 192MB (needs 1GB)\n+        cma-128                 CMA is 128MB\n+        cma-96                  CMA is 96MB\n+        cma-64                  CMA is 64MB\n+        cma-size                CMA size in bytes, 4MB aligned\n+        cma-default             Use upstream's default value\n+        audio                   Enable or disable audio over HDMI (default \"on\")\n+        noaudio                 Disable all HDMI audio (default \"off\")\n+\n+\n+Name:   vc4-kms-v3d-pi4\n+Info:   Enable Eric Anholt's DRM VC4 HDMI/HVS/V3D driver for Pi4.\n+Load:   dtoverlay=vc4-kms-v3d-pi4,<param>\n+Params: cma-512                 CMA is 512MB\n+        cma-448                 CMA is 448MB\n+        cma-384                 CMA is 384MB\n+        cma-320                 CMA is 320MB\n+        cma-256                 CMA is 256MB\n+        cma-192                 CMA is 192MB\n+        cma-128                 CMA is 128MB\n+        cma-96                  CMA is 96MB\n+        cma-64                  CMA is 64MB\n+        cma-size                CMA size in bytes, 4MB aligned\n+        cma-default             Use upstream's default value\n+        audio                   Enable or disable audio over HDMI0 (default\n+                                \"on\")\n+        audio1                  Enable or disable audio over HDMI1 (default\n+                                \"on\")\n+        noaudio                 Disable all HDMI audio (default \"off\")\n+        composite               Enable the composite output (disables all other\n+                                outputs)\n+\n+\n+Name:   vga666\n+Info:   Overlay for the Fen Logic VGA666 board\n+        This uses GPIOs 2-21 (so no I2C), and activates the output 2-3 seconds\n+        after the kernel has started.\n+Load:   dtoverlay=vga666\n+Params: <None>\n+\n+\n+Name:   w1-gpio\n+Info:   Configures the w1-gpio Onewire interface module.\n+        Use this overlay if you *don't* need a GPIO to drive an external pullup.\n+Load:   dtoverlay=w1-gpio,<param>=<val>\n+Params: gpiopin                 GPIO for I/O (default \"4\")\n+        pullup                  Now enabled by default (ignored)\n+\n+\n+Name:   w1-gpio-pullup\n+Info:   Configures the w1-gpio Onewire interface module.\n+        Use this overlay if you *do* need a GPIO to drive an external pullup.\n+Load:   dtoverlay=w1-gpio-pullup,<param>=<val>\n+Params: gpiopin                 GPIO for I/O (default \"4\")\n+        extpullup               GPIO for external pullup (default \"5\")\n+        pullup                  Now enabled by default (ignored)\n+\n+\n+Name:   w5500\n+Info:   Overlay for the Wiznet W5500 Ethernet Controller on SPI0\n+Load:   dtoverlay=w5500,<param>=<val>\n+Params: int_pin                 GPIO used for INT (default 25)\n+\n+        speed                   SPI bus speed (default 30000000)\n+\n+        cs                      SPI bus Chip Select (default 0)\n+\n+\n+Name:   wittypi\n+Info:   Configures the wittypi RTC module.\n+Load:   dtoverlay=wittypi,<param>=<val>\n+Params: led_gpio                GPIO for LED (default \"17\")\n+        led_trigger             Choose which activity the LED tracks (default\n+                                \"default-on\")\n+\n+\n+Troubleshooting\n+===============\n+\n+If you are experiencing problems that you think are DT-related, enable DT\n+diagnostic output by adding this to /boot/config.txt:\n+\n+    dtdebug=on\n+\n+and rebooting. Then run:\n+\n+    sudo vcdbg log msg\n+\n+and look for relevant messages.\n+\n+Further reading\n+===============\n+\n+This is only meant to be a quick introduction to the subject of Device Tree on\n+Raspberry Pi. There is a more complete explanation here:\n+\n+http://www.raspberrypi.org/documentation/configuration/device-tree.md\ndiff --git a/arch/arm/boot/dts/overlays/act-led-overlay.dts b/arch/arm/boot/dts/overlays/act-led-overlay.dts\nnew file mode 100644\nindex 000000000000..2f4bbb407f89\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/act-led-overlay.dts\n@@ -0,0 +1,27 @@\n+/dts-v1/;\n+/plugin/;\n+\n+/* Pi3 uses a GPIO expander to drive the LEDs which can only be accessed\n+   from the VPU. There is a special driver for this with a separate DT node,\n+   which has the unfortunate consequence of breaking the act_led_gpio and\n+   act_led_activelow dtparams.\n+\n+   This overlay changes the GPIO controller back to the standard one and\n+   restores the dtparams.\n+*/\n+\n+/{\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&act_led>;\n+\t\tfrag0: __overlay__ {\n+\t\t\tgpios = <&gpio 0 0>;\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\tgpio = <&frag0>,\"gpios:4\";\n+\t\tactivelow = <&frag0>,\"gpios:8\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/adafruit18-overlay.dts b/arch/arm/boot/dts/overlays/adafruit18-overlay.dts\nnew file mode 100644\nindex 000000000000..e1ce94a8cd3e\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/adafruit18-overlay.dts\n@@ -0,0 +1,55 @@\n+/*\n+ * Device Tree overlay for Adafruit 1.8\" TFT LCD with ST7735R chip 160x128\n+ */\n+\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&spidev0>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&spi0>;\n+\t\t__overlay__ {\n+\t\t\t/* needed to avoid dtc warning */\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\taf18: adafruit18@0 {\n+\t\t\t\tcompatible = \"fbtft,adafruit18\";\n+\t\t\t\treg = <0>;\n+\t\t\t\tpinctrl-names = \"default\";\n+\t\t\t\tspi-max-frequency = <40000000>;\n+\t\t\t\trotate = <90>;\n+\t\t\t\tbuswidth = <8>;\n+\t\t\t\tfps = <50>;\n+\t\t\t\theight = <160>;\n+\t\t\t\twidth = <128>;\n+\t\t\t\treset-gpios = <&gpio 25 1>;\n+\t\t\t\tdc-gpios = <&gpio 24 0>;\n+\t\t\t\tled-gpios = <&gpio 18 0>;\n+\t\t\t\tdebug = <0>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\tgreen = <&af18>, \"compatible=fbtft,adafruit18_green\";\n+\t\tspeed     = <&af18>,\"spi-max-frequency:0\";\n+\t\trotate    = <&af18>,\"rotate:0\";\n+\t\tfps       = <&af18>,\"fps:0\";\n+\t\tbgr       = <&af18>,\"bgr?\";\n+\t\tdebug     = <&af18>,\"debug:0\";\n+\t\tdc_pin    = <&af18>,\"dc-gpios:4\";\n+\t\treset_pin = <&af18>,\"reset-gpios:4\";\n+\t\tled_pin   = <&af18>,\"led-gpios:4\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/adau1977-adc-overlay.dts b/arch/arm/boot/dts/overlays/adau1977-adc-overlay.dts\nnew file mode 100644\nindex 000000000000..298488e19156\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/adau1977-adc-overlay.dts\n@@ -0,0 +1,40 @@\n+// Definitions for ADAU1977 ADC\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+    \n+\tfragment@0 {\n+        \ttarget = <&i2c>;\n+        \t\n+\t\t__overlay__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\t\t\t\n+\t\t\tadau1977: codec@11 {\n+                        \tcompatible = \"adi,adau1977\";\n+                        \treg = <0x11>;\n+                        \treset-gpios = <&gpio 5 0>;\n+\t\t\t\tAVDD-supply = <&vdd_3v3_reg>;\n+                \t};\n+        \t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&i2s>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&sound>;\n+\t\t__overlay__ {\n+\t\t\tcompatible = \"adi,adau1977-adc\";\n+\t\t\ti2s-controller = <&i2s>;\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/adau7002-simple-overlay.dts b/arch/arm/boot/dts/overlays/adau7002-simple-overlay.dts\nnew file mode 100644\nindex 000000000000..5fed769d2526\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/adau7002-simple-overlay.dts\n@@ -0,0 +1,52 @@\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+    compatible = \"brcm,bcm2835\";\n+\n+    fragment@0 {\n+        target = <&i2s>;\n+        __overlay__ {\n+            status = \"okay\";\n+        };\n+    };\n+\n+    fragment@1 {\n+        target-path = \"/\";\n+        __overlay__ {\n+                adau7002_codec: adau7002-codec {\n+                #sound-dai-cells = <0>;\n+                compatible = \"adi,adau7002\";\n+/*                IOVDD-supply = <&supply>;*/\n+                status = \"okay\";\n+            };\n+        };\n+    };\n+\n+    fragment@2 {\n+        target = <&sound>;\n+            sound_overlay: __overlay__ {\n+            compatible = \"simple-audio-card\";\n+            simple-audio-card,format = \"i2s\";\n+            simple-audio-card,name = \"adau7002\";\n+            simple-audio-card,bitclock-slave = <&dailink0_slave>;\n+            simple-audio-card,frame-slave = <&dailink0_slave>;\n+            simple-audio-card,widgets =\n+                    \"Microphone\", \"Microphone Jack\";\n+            simple-audio-card,routing =\n+                    \"PDM_DAT\", \"Microphone Jack\";\n+            status = \"okay\";\n+            simple-audio-card,cpu {\n+                sound-dai = <&i2s>;\n+            };\n+            dailink0_slave: simple-audio-card,codec {\n+                sound-dai = <&adau7002_codec>;\n+            };\n+        };\n+    };\n+\n+\n+    __overrides__ {\n+        card-name = <&sound_overlay>,\"simple-audio-card,name\";\n+    };\n+};\ndiff --git a/arch/arm/boot/dts/overlays/ads1015-overlay.dts b/arch/arm/boot/dts/overlays/ads1015-overlay.dts\nnew file mode 100644\nindex 000000000000..deeee1228395\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/ads1015-overlay.dts\n@@ -0,0 +1,98 @@\n+/*\n+ * 2016 - Erik Sejr\n+ */\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+    compatible = \"brcm,bcm2835\";\n+    /* ----------- ADS1015 ------------ */\n+    fragment@0 {\n+        target = <&i2c_arm>;\n+        __overlay__ {\n+            #address-cells = <1>;\n+            #size-cells = <0>;\n+            status = \"okay\";\n+            ads1015: ads1015 {\n+                compatible = \"ti,ads1015\";\n+                status = \"okay\";\n+                #address-cells = <1>;\n+                #size-cells = <0>;\n+                reg = <0x48>;\n+            };\n+        };\n+    };\n+\n+    fragment@1 {\n+        target = <&ads1015>;\n+        __overlay__ {\n+            #address-cells = <1>;\n+            #size-cells = <0>;\n+            channel_a: channel_a {\n+                reg = <4>;\n+                ti,gain = <2>;\n+                ti,datarate = <4>;\n+            };\n+        };\n+    };\n+\n+    fragment@2 {\n+        target = <&ads1015>;\n+        __dormant__ {\n+            #address-cells = <1>;\n+            #size-cells = <0>;\n+            channel_b: channel_b {\n+                reg = <5>;\n+                ti,gain = <2>;\n+                ti,datarate = <4>;\n+            };\n+        };\n+    };\n+\n+    fragment@3 {\n+        target = <&ads1015>;\n+        __dormant__ {\n+            #address-cells = <1>;\n+            #size-cells = <0>;\n+            channel_c: channel_c {\n+                reg = <6>;\n+                ti,gain = <2>;\n+                ti,datarate = <4>;\n+            };\n+        };\n+    };\n+\n+    fragment@4 {\n+        target = <&ads1015>;\n+        __dormant__ {\n+            #address-cells = <1>;\n+            #size-cells = <0>;\n+            channel_d: channel_d {\n+                reg = <7>;\n+                ti,gain = <2>;\n+                ti,datarate = <4>;\n+            };\n+        };\n+    };\n+\n+    __overrides__ {\n+        addr =            <&ads1015>,\"reg:0\";\n+        cha_enable =      <0>,\"=1\";\n+        cha_cfg =         <&channel_a>,\"reg:0\";\n+        cha_gain =        <&channel_a>,\"ti,gain:0\";\n+        cha_datarate =    <&channel_a>,\"ti,datarate:0\";\n+        chb_enable =      <0>,\"=2\";\n+        chb_cfg =         <&channel_b>,\"reg:0\";\n+        chb_gain =        <&channel_b>,\"ti,gain:0\";\n+        chb_datarate =    <&channel_b>,\"ti,datarate:0\";\n+        chc_enable =      <0>,\"=3\";\n+        chc_cfg =         <&channel_c>,\"reg:0\";\n+        chc_gain =        <&channel_c>,\"ti,gain:0\";\n+        chc_datarate =    <&channel_c>,\"ti,datarate:0\";\n+        chd_enable =      <0>,\"=4\";\n+        chd_cfg =         <&channel_d>,\"reg:0\";\n+        chd_gain =        <&channel_d>,\"ti,gain:0\";\n+        chd_datarate =    <&channel_d>,\"ti,datarate:0\";\n+   };\n+\n+};\ndiff --git a/arch/arm/boot/dts/overlays/ads1115-overlay.dts b/arch/arm/boot/dts/overlays/ads1115-overlay.dts\nnew file mode 100644\nindex 000000000000..4fc571c2db33\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/ads1115-overlay.dts\n@@ -0,0 +1,103 @@\n+/*\n+ * TI ADS1115 multi-channel ADC overlay\n+ */\n+\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&i2c_arm>;\n+\t\t__overlay__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tads1115: ads1115 {\n+\t\t\t\tcompatible = \"ti,ads1115\";\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t\t#address-cells = <1>;\n+\t\t\t\t#size-cells = <0>;\n+\t\t\t\treg = <0x48>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&ads1115>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tchannel_a: channel_a {\n+\t\t\t\treg = <4>;\n+\t\t\t\tti,gain = <1>;\n+\t\t\t\tti,datarate = <7>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&ads1115>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tchannel_b: channel_b {\n+\t\t\t\treg = <5>;\n+\t\t\t\tti,gain = <1>;\n+\t\t\t\tti,datarate = <7>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@3 {\n+\t\ttarget = <&ads1115>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tchannel_c: channel_c {\n+\t\t\t\treg = <6>;\n+\t\t\t\tti,gain = <1>;\n+\t\t\t\tti,datarate = <7>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@4 {\n+\t\ttarget = <&ads1115>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tchannel_d: channel_d {\n+\t\t\t\treg = <7>;\n+\t\t\t\tti,gain = <1>;\n+\t\t\t\tti,datarate = <7>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\taddr =            <&ads1115>,\"reg:0\";\n+\t\tcha_enable =      <0>,\"=1\";\n+\t\tcha_cfg =         <&channel_a>,\"reg:0\";\n+\t\tcha_gain =        <&channel_a>,\"ti,gain:0\";\n+\t\tcha_datarate =    <&channel_a>,\"ti,datarate:0\";\n+\t\tchb_enable =      <0>,\"=2\";\n+\t\tchb_cfg =         <&channel_b>,\"reg:0\";\n+\t\tchb_gain =        <&channel_b>,\"ti,gain:0\";\n+\t\tchb_datarate =    <&channel_b>,\"ti,datarate:0\";\n+\t\tchc_enable =      <0>,\"=3\";\n+\t\tchc_cfg =         <&channel_c>,\"reg:0\";\n+\t\tchc_gain =        <&channel_c>,\"ti,gain:0\";\n+\t\tchc_datarate =    <&channel_c>,\"ti,datarate:0\";\n+\t\tchd_enable =      <0>,\"=4\";\n+\t\tchd_cfg =         <&channel_d>,\"reg:0\";\n+\t\tchd_gain =        <&channel_d>,\"ti,gain:0\";\n+\t\tchd_datarate =    <&channel_d>,\"ti,datarate:0\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/ads7846-overlay.dts b/arch/arm/boot/dts/overlays/ads7846-overlay.dts\nnew file mode 100644\nindex 000000000000..1c5c9b6bb6ff\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/ads7846-overlay.dts\n@@ -0,0 +1,89 @@\n+/*\n+ * Generic Device Tree overlay for the ADS7846 touch controller\n+ *\n+ */\n+\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&spi0>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&spidev0>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&spidev1>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\tfragment@3 {\n+\t\ttarget = <&gpio>;\n+\t\t__overlay__ {\n+\t\t\tads7846_pins: ads7846_pins {\n+\t\t\t\tbrcm,pins = <255>; /* illegal default value */\n+\t\t\t\tbrcm,function = <0>; /* in */\n+\t\t\t\tbrcm,pull = <0>; /* none */\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@4 {\n+\t\ttarget = <&spi0>;\n+\t\t__overlay__ {\n+\t\t\t/* needed to avoid dtc warning */\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tads7846: ads7846@1 {\n+\t\t\t\tcompatible = \"ti,ads7846\";\n+\t\t\t\treg = <1>;\n+\t\t\t\tpinctrl-names = \"default\";\n+\t\t\t\tpinctrl-0 = <&ads7846_pins>;\n+\n+\t\t\t\tspi-max-frequency = <2000000>;\n+\t\t\t\tinterrupts = <255 2>; /* high-to-low edge triggered */\n+\t\t\t\tinterrupt-parent = <&gpio>;\n+\t\t\t\tpendown-gpio = <&gpio 255 0>;\n+\n+\t\t\t\t/* driver defaults */\n+\t\t\t\tti,x-min = /bits/ 16 <0>;\n+\t\t\t\tti,y-min = /bits/ 16 <0>;\n+\t\t\t\tti,x-max = /bits/ 16 <0x0FFF>;\n+\t\t\t\tti,y-max = /bits/ 16 <0x0FFF>;\n+\t\t\t\tti,pressure-min = /bits/ 16 <0>;\n+\t\t\t\tti,pressure-max = /bits/ 16 <0xFFFF>;\n+\t\t\t\tti,x-plate-ohms = /bits/ 16 <400>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\t__overrides__ {\n+\t\tcs =     <&ads7846>,\"reg:0\";\n+\t\tspeed =  <&ads7846>,\"spi-max-frequency:0\";\n+\t\tpenirq = <&ads7846_pins>,\"brcm,pins:0\", /* REQUIRED */\n+\t\t\t <&ads7846>,\"interrupts:0\",\n+\t\t\t <&ads7846>,\"pendown-gpio:4\";\n+\t\tpenirq_pull = <&ads7846_pins>,\"brcm,pull:0\";\n+\t\tswapxy = <&ads7846>,\"ti,swap-xy?\";\n+\t\txmin =   <&ads7846>,\"ti,x-min;0\";\n+\t\tymin =   <&ads7846>,\"ti,y-min;0\";\n+\t\txmax =   <&ads7846>,\"ti,x-max;0\";\n+\t\tymax =   <&ads7846>,\"ti,y-max;0\";\n+\t\tpmin =   <&ads7846>,\"ti,pressure-min;0\";\n+\t\tpmax =   <&ads7846>,\"ti,pressure-max;0\";\n+\t\txohms =  <&ads7846>,\"ti,x-plate-ohms;0\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/adv7282m-overlay.dts b/arch/arm/boot/dts/overlays/adv7282m-overlay.dts\nnew file mode 100644\nindex 000000000000..5d85dfd0595c\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/adv7282m-overlay.dts\n@@ -0,0 +1,65 @@\n+// SPDX-License-Identifier: GPL-2.0-only\n+// Definitions for Analog Devices ADV7282-M video to CSI2 bridge on VC I2C bus\n+/dts-v1/;\n+/plugin/;\n+\n+/{\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&i2c_csi_dsi>;\n+\t\t__overlay__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tadv728x: adv728x@21 {\n+\t\t\t\tcompatible = \"adi,adv7282-m\";\n+\t\t\t\treg = <0x21>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t\tclock-frequency = <24000000>;\n+\t\t\t\tport {\n+\t\t\t\t\tadv728x_0: endpoint {\n+\t\t\t\t\t\tremote-endpoint = <&csi1_ep>;\n+\t\t\t\t\t\tclock-lanes = <0>;\n+\t\t\t\t\t\tdata-lanes = <1>;\n+\t\t\t\t\t\tlink-frequencies =\n+\t\t\t\t\t\t\t/bits/ 64 <297000000>;\n+\n+\t\t\t\t\t\tmclk-frequency = <12000000>;\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\t\t\t};\n+\t\t};\n+\t};\n+\tfragment@1 {\n+\t\ttarget = <&csi1>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tport {\n+\t\t\t\tcsi1_ep: endpoint {\n+\t\t\t\t\tremote-endpoint = <&adv728x_0>;\n+\t\t\t\t\tdata-lanes = <1>;\n+\t\t\t\t};\n+\t\t\t};\n+\t\t};\n+\t};\n+\tfragment@2 {\n+\t\ttarget = <&i2c0if>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@3 {\n+\t\ttarget = <&i2c0mux>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\taddr =\t\t\t<&adv728x>,\"reg:0\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/adv728x-m-overlay.dts b/arch/arm/boot/dts/overlays/adv728x-m-overlay.dts\nnew file mode 100644\nindex 000000000000..ea392e886984\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/adv728x-m-overlay.dts\n@@ -0,0 +1,37 @@\n+// SPDX-License-Identifier: GPL-2.0-only\n+// Definitions for Analog Devices ADV728[0|1|2]-M video to CSI2 bridges on VC\n+// I2C bus\n+\n+#include \"adv7282m-overlay.dts\"\n+\n+/{\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\t// Fragment numbers deliberately high to avoid conflicts with the\n+\t// included adv7282m overlay file.\n+\n+\tfragment@101 {\n+\t\ttarget = <&adv728x>;\n+\t\t__dormant__ {\n+\t\t\tcompatible = \"adi,adv7280-m\";\n+\t\t};\n+\t};\n+\tfragment@102 {\n+\t\ttarget = <&adv728x>;\n+\t\t__dormant__ {\n+\t\t\tcompatible = \"adi,adv7281-m\";\n+\t\t};\n+\t};\n+\tfragment@103 {\n+\t\ttarget = <&adv728x>;\n+\t\t__dormant__ {\n+\t\t\tcompatible = \"adi,adv7281-ma\";\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\tadv7280m = <0>, \"+101\";\n+\t\tadv7281m = <0>, \"+102\";\n+\t\tadv7281ma = <0>, \"+103\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/akkordion-iqdacplus-overlay.dts b/arch/arm/boot/dts/overlays/akkordion-iqdacplus-overlay.dts\nnew file mode 100644\nindex 000000000000..82f9b3734fb1\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/akkordion-iqdacplus-overlay.dts\n@@ -0,0 +1,49 @@\n+// Definitions for Digital Dreamtime Akkordion using IQaudIO DAC+ or DACZero\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&i2s>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&i2c1>;\n+\t\t__overlay__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tpcm5122@4c {\n+\t\t\t\t#sound-dai-cells = <0>;\n+\t\t\t\tcompatible = \"ti,pcm5122\";\n+\t\t\t\treg = <0x4c>;\n+\t\t\t\tAVDD-supply = <&vdd_3v3_reg>;\n+\t\t\t\tDVDD-supply = <&vdd_3v3_reg>;\n+\t\t\t\tCPVDD-supply = <&vdd_3v3_reg>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&sound>;\n+\t\tfrag2: __overlay__ {\n+\t\t\tcompatible = \"iqaudio,iqaudio-dac\";\n+\t\t\tcard_name = \"Akkordion\";\n+\t\t\tdai_name = \"IQaudIO DAC\";\n+\t\t\tdai_stream_name = \"IQaudIO DAC HiFi\";\n+\t\t\ti2s-controller = <&i2s>;\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\t24db_digital_gain = <&frag2>,\"iqaudio,24db_digital_gain?\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/allo-boss-dac-pcm512x-audio-overlay.dts b/arch/arm/boot/dts/overlays/allo-boss-dac-pcm512x-audio-overlay.dts\nnew file mode 100644\nindex 000000000000..873cb2fab52b\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/allo-boss-dac-pcm512x-audio-overlay.dts\n@@ -0,0 +1,59 @@\n+/*\n+ * Definitions for Allo Boss DAC board\n+ */\n+\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget-path = \"/\";\n+\t\t__overlay__ {\n+\t\t\tboss_osc: boss_osc {\n+\t\t\t\tcompatible = \"allo,dac-clk\";\n+\t\t\t\t#clock-cells = <0>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&i2s>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&i2c1>;\n+\t\t__overlay__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tpcm5122@4d {\n+\t\t\t\t#sound-dai-cells = <0>;\n+\t\t\t\tcompatible = \"ti,pcm5122\";\n+\t\t\t\tclocks = <&boss_osc>;\n+\t\t\t\treg = <0x4d>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@3 {\n+\t\ttarget = <&sound>;\n+\t\tboss_dac: __overlay__ {\n+\t\t\tcompatible = \"allo,boss-dac\";\n+\t\t\ti2s-controller = <&i2s>;\n+\t\t\tmute-gpios = <&gpio 6 1>;\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\t24db_digital_gain = <&boss_dac>,\"allo,24db_digital_gain?\";\n+\t\tslave = <&boss_dac>,\"allo,slave?\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/allo-digione-overlay.dts b/arch/arm/boot/dts/overlays/allo-digione-overlay.dts\nnew file mode 100644\nindex 000000000000..ea018ace34d4\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/allo-digione-overlay.dts\n@@ -0,0 +1,44 @@\n+// Definitions for Allo DigiOne\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&i2s>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&i2c1>;\n+\t\t__overlay__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\twm8804@3b {\n+\t\t\t\t#sound-dai-cells = <0>;\n+\t\t\t\tcompatible = \"wlf,wm8804\";\n+\t\t\t\treg = <0x3b>;\n+\t\t\t\tPVDD-supply = <&vdd_3v3_reg>;\n+\t\t\t\tDVDD-supply = <&vdd_3v3_reg>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t\twlf,reset-gpio = <&gpio 17 0>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&sound>;\n+\t\t__overlay__ {\n+\t\t\tcompatible = \"allo,allo-digione\";\n+\t\t\ti2s-controller = <&i2s>;\n+\t\t\tstatus = \"okay\";\n+\t\t\tclock44-gpio = <&gpio 5 0>;\n+\t\t\tclock48-gpio = <&gpio 6 0>;\n+\t\t};\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/allo-katana-dac-audio-overlay.dts b/arch/arm/boot/dts/overlays/allo-katana-dac-audio-overlay.dts\nnew file mode 100644\nindex 000000000000..b25fd681f09f\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/allo-katana-dac-audio-overlay.dts\n@@ -0,0 +1,57 @@\n+/*\n+ * Definitions for Allo Katana DAC boards\n+ */\n+\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&i2s>;\n+\t\t__overlay__ {\n+\t\t\t#sound-dai-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\t\t\tcpu_port: port {\n+\t\t\t\tcpu_endpoint: endpoint {\n+\t\t\t\t\tremote-endpoint = <&codec_endpoint>;\n+\t\t\t\t\tbitclock-master = <&codec_endpoint>;\n+\t\t\t\t\tframe-master = <&codec_endpoint>;\n+\t\t\t\t\tdai-format = \"i2s\";\n+\t\t\t\t};\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&i2c1>;\n+\t\t__overlay__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tallo-katana-codec@30 {\n+\t\t\t\t#sound-dai-cells = <0>;\n+\t\t\t\tcompatible = \"allo,allo-katana-codec\";\n+\t\t\t\treg = <0x30>;\n+\t\t\t\tport {\n+\t\t\t\t\tcodec_endpoint: endpoint {\n+\t\t\t\t\tremote-endpoint = <&cpu_endpoint>;\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&sound>;\n+\t\tkatana_dac: __overlay__ {\n+\t\t\tcompatible = \"audio-graph-card\";\n+\t\t\tlabel = \"Allo Katana\";\n+\t\t\tdais = <&cpu_port>;\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+};\n+\ndiff --git a/arch/arm/boot/dts/overlays/allo-piano-dac-pcm512x-audio-overlay.dts b/arch/arm/boot/dts/overlays/allo-piano-dac-pcm512x-audio-overlay.dts\nnew file mode 100644\nindex 000000000000..bfc66da6295a\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/allo-piano-dac-pcm512x-audio-overlay.dts\n@@ -0,0 +1,54 @@\n+/*\n+ * Definitions for Allo Piano DAC (2.0/2.1) boards\n+ *\n+ * NB. The Piano DAC 2.1 board contains 2x TI PCM5142 DAC's. One DAC is stereo\n+ * (left/right) and the other provides a subwoofer output, using DSP on the\n+ * chip for digital high/low pass crossover.\n+ * The initial support for this hardware, that doesn't require any codec driver\n+ * modifications, uses only one DAC chip for stereo (left/right) output, the\n+ * chip with 0x4c slave address. The other chip at 0x4d is currently ignored!\n+ */\n+\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&i2s>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&i2c1>;\n+\t\t__overlay__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tpcm5142@4c {\n+\t\t\t\t#sound-dai-cells = <0>;\n+\t\t\t\tcompatible = \"ti,pcm5142\";\n+\t\t\t\treg = <0x4c>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&sound>;\n+\t\tpiano_dac: __overlay__ {\n+\t\t\tcompatible = \"allo,piano-dac\";\n+\t\t\ti2s-controller = <&i2s>;\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\t24db_digital_gain =\n+\t\t\t<&piano_dac>,\"allo,24db_digital_gain?\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/allo-piano-dac-plus-pcm512x-audio-overlay.dts b/arch/arm/boot/dts/overlays/allo-piano-dac-plus-pcm512x-audio-overlay.dts\nnew file mode 100644\nindex 000000000000..374c553db062\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/allo-piano-dac-plus-pcm512x-audio-overlay.dts\n@@ -0,0 +1,55 @@\n+// Definitions for Piano DAC\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&i2s>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&i2c1>;\n+\t\t__overlay__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tallo_pcm5122_4c: pcm5122@4c {\n+\t\t\t\t#sound-dai-cells = <0>;\n+\t\t\t\tcompatible = \"ti,pcm5122\";\n+\t\t\t\treg = <0x4c>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t\tallo_pcm5122_4d: pcm5122@4d {\n+\t\t\t\t#sound-dai-cells = <0>;\n+\t\t\t\tcompatible = \"ti,pcm5122\";\n+\t\t\t\treg = <0x4d>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&sound>;\n+\t\tpiano_dac: __overlay__ {\n+\t\t\tcompatible = \"allo,piano-dac-plus\";\n+\t\t\taudio-codec = <&allo_pcm5122_4c &allo_pcm5122_4d>;\n+\t\t\ti2s-controller = <&i2s>;\n+\t\t\tmute1-gpios = <&gpio 6 1>;\n+\t\t\tmute2-gpios = <&gpio 25 1>;\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\t24db_digital_gain =\n+\t\t\t<&piano_dac>,\"allo,24db_digital_gain?\";\n+\t\tglb_mclk =\n+\t\t\t<&piano_dac>,\"allo,glb_mclk?\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/anyspi-overlay.dts b/arch/arm/boot/dts/overlays/anyspi-overlay.dts\nnew file mode 100755\nindex 000000000000..87523dcca318\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/anyspi-overlay.dts\n@@ -0,0 +1,205 @@\n+/*\n+ * Universal device tree overlay for SPI devices\n+ */\n+\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&spidev0>;\n+\t\t__dormant__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&spidev1>;\n+\t\t__dormant__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget-path = \"spi1/spidev@0\";\n+\t\t__dormant__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\tfragment@3 {\n+\t\ttarget-path = \"spi1/spidev@1\";\n+\t\t__dormant__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\tfragment@4 {\n+\t\ttarget-path = \"spi1/spidev@2\";\n+\t\t__dormant__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\tfragment@5 {\n+\t\ttarget-path = \"spi2/spidev@0\";\n+\t\t__dormant__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\tfragment@6 {\n+\t\ttarget-path = \"spi2/spidev@1\";\n+\t\t__dormant__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\tfragment@7 {\n+\t\ttarget-path = \"spi2/spidev@2\";\n+\t\t__dormant__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\tfragment@8 {\n+\t\ttarget = <&spi0>;\n+\t\t__dormant__ {\n+\t\t\tstatus = \"okay\";\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tanyspi_00: anyspi@0 {\n+\t\t\t\treg = <0>;\n+\t\t\t\tspi-max-frequency = <500000>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@9 {\n+\t\ttarget = <&spi0>;\n+\t\t__dormant__ {\n+\t\t\tstatus = \"okay\";\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tanyspi_01: anyspi@1 {\n+\t\t\t\treg = <1>;\n+\t\t\t\tspi-max-frequency = <500000>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@10 {\n+\t\ttarget = <&spi1>;\n+\t\t__dormant__ {\n+\t\t\tstatus = \"okay\";\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tanyspi_10: anyspi@0 {\n+\t\t\t\treg = <0>;\n+\t\t\t\tspi-max-frequency = <500000>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@11 {\n+\t\ttarget = <&spi1>;\n+\t\t__dormant__ {\n+\t\t\tstatus = \"okay\";\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tanyspi_11: anyspi@1 {\n+\t\t\t\treg = <1>;\n+\t\t\t\tspi-max-frequency = <500000>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@12 {\n+\t\ttarget = <&spi1>;\n+\t\t__dormant__ {\n+\t\t\tstatus = \"okay\";\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tanyspi_12: anyspi@2 {\n+\t\t\t\treg = <2>;\n+\t\t\t\tspi-max-frequency = <500000>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@13 {\n+\t\ttarget = <&spi2>;\n+\t\t__dormant__ {\n+\t\t\tstatus = \"okay\";\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tanyspi_20: anyspi@0 {\n+\t\t\t\treg = <0>;\n+\t\t\t\tspi-max-frequency = <500000>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@14 {\n+\t\ttarget = <&spi2>;\n+\t\t__dormant__ {\n+\t\t\tstatus = \"okay\";\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tanyspi_21: anyspi@1 {\n+\t\t\t\treg = <1>;\n+\t\t\t\tspi-max-frequency = <500000>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@15 {\n+\t\ttarget = <&spi2>;\n+\t\t__dormant__ {\n+\t\t\tstatus = \"okay\";\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tanyspi_22: anyspi@2 {\n+\t\t\t\treg = <2>;\n+\t\t\t\tspi-max-frequency = <500000>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\tspi0-0 = <0>, \"+0+8\";\n+\t\tspi0-1 = <0>, \"+1+9\";\n+\t\tspi1-0 = <0>, \"+2+10\";\n+\t\tspi1-1 = <0>, \"+3+11\";\n+\t\tspi1-2 = <0>, \"+4+12\";\n+\t\tspi2-0 = <0>, \"+5+13\";\n+\t\tspi2-1 = <0>, \"+6+14\";\n+\t\tspi2-2 = <0>, \"+7+15\";\n+\t\tdev = <&anyspi_00>,\"compatible\",\n+\t\t      <&anyspi_01>,\"compatible\",\n+\t\t      <&anyspi_10>,\"compatible\",\n+\t\t      <&anyspi_11>,\"compatible\",\n+\t\t      <&anyspi_12>,\"compatible\",\n+\t\t      <&anyspi_20>,\"compatible\",\n+\t\t      <&anyspi_21>,\"compatible\",\n+\t\t      <&anyspi_22>,\"compatible\";\n+\t\tspeed = <&anyspi_00>, \"spi-max-frequency:0\",\n+\t\t        <&anyspi_01>, \"spi-max-frequency:0\",\n+\t\t        <&anyspi_10>, \"spi-max-frequency:0\",\n+\t\t        <&anyspi_11>, \"spi-max-frequency:0\",\n+\t\t        <&anyspi_12>, \"spi-max-frequency:0\",\n+\t\t        <&anyspi_20>, \"spi-max-frequency:0\",\n+\t\t        <&anyspi_21>, \"spi-max-frequency:0\",\n+\t\t        <&anyspi_22>, \"spi-max-frequency:0\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/apds9960-overlay.dts b/arch/arm/boot/dts/overlays/apds9960-overlay.dts\nnew file mode 100644\nindex 000000000000..c216932278ab\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/apds9960-overlay.dts\n@@ -0,0 +1,57 @@\n+// Definitions for APDS-9960 ambient light and gesture sensor\n+\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&i2c1>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&gpio>;\n+\t\t__overlay__ {\n+\t\t\tapds9960_pins: apds9960_pins@39 {\n+\t\t\t\tbrcm,pins = <4>;\n+\t\t\t\tbrcm,function = <0>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&i2c1>;\n+\t\t__overlay__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tapds9960: apds@39 {\n+\t\t\t\tcompatible = \"avago,apds9960\";\n+\t\t\t\treg = <0x39>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@3 {\n+\t\ttarget = <&i2c1>;\n+\t\t__overlay__ {\n+\t\t\tapds9960_irq: apds@39 {\n+\t\t\t\t#interrupt-cells=<2>;\n+\t\t\t\tinterrupt-parent = <&gpio>;\n+\t\t\t\tinterrupts = <4 1>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\tgpiopin = <&apds9960_pins>,\"brcm,pins:0\",\n+\t\t\t\t<&apds9960_irq>,\"interrupts:0\";\n+\t\tnoints = <0>,\"!1!3\";\n+\t};\n+};\n+\ndiff --git a/arch/arm/boot/dts/overlays/applepi-dac-overlay.dts b/arch/arm/boot/dts/overlays/applepi-dac-overlay.dts\nnew file mode 100644\nindex 000000000000..4769296ec9d6\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/applepi-dac-overlay.dts\n@@ -0,0 +1,57 @@\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+    compatible = \"brcm,bcm2835\";\n+\n+    fragment@0 {\n+        target = <&sound>;\n+        __overlay__ {\n+            compatible = \"simple-audio-card\";\n+            simple-audio-card,name = \"ApplePi-DAC\";\n+\n+            status = \"okay\";\n+\n+            playback_link: simple-audio-card,dai-link@1 {\n+                format = \"i2s\";\n+\n+                p_cpu_dai: cpu {\n+                    sound-dai = <&i2s>;\n+                    dai-tdm-slot-num = <2>;\n+                    dai-tdm-slot-width = <32>;\n+                };\n+\n+                p_codec_dai: codec {\n+                    sound-dai = <&codec_out>;\n+                };\n+            };\n+        };\n+    };\n+\n+    fragment@1 {\n+        target-path = \"/\";\n+        __overlay__ {\n+            codec_out: pcm1794a-codec {\n+                #sound-dai-cells = <0>;\n+                compatible = \"ti,pcm1794a\";\n+                status = \"okay\";\n+            };\n+        };\n+    };\n+\n+    fragment@2 {\n+        target = <&i2s>;\n+        __overlay__ {\n+            #sound-dai-cells = <0>;\n+            status = \"okay\";\n+        };\n+    };\n+};\n+\n+/*\n+   Written by: Leonid Ayzenshtat\n+   Company: Orchard Audio (www.orchardaudio.com)\n+\n+   compile with:\n+   dtc -@ -H epapr -O dtb -o ApplePi-DAC.dtbo -W no-unit_address_vs_reg ApplePi-DAC.dts\n+*/\ndiff --git a/arch/arm/boot/dts/overlays/at86rf233-overlay.dts b/arch/arm/boot/dts/overlays/at86rf233-overlay.dts\nnew file mode 100644\nindex 000000000000..5a3f4571ee78\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/at86rf233-overlay.dts\n@@ -0,0 +1,57 @@\n+/dts-v1/;\n+/plugin/;\n+\n+/* Overlay for Atmel AT86RF233 IEEE 802.15.4 WPAN transceiver on spi0.0 */\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&spi0>;\n+\t\t__overlay__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tlowpan0: at86rf233@0 {\n+\t\t\t\tcompatible = \"atmel,at86rf233\";\n+\t\t\t\treg = <0>;\n+\t\t\t\tinterrupt-parent = <&gpio>;\n+\t\t\t\tinterrupts = <23 4>; /* active high */\n+\t\t\t\treset-gpio = <&gpio 24 1>;\n+\t\t\t\tsleep-gpio = <&gpio 25 1>;\n+\t\t\t\tspi-max-frequency = <3000000>;\n+\t\t\t\txtal-trim = /bits/ 8 <0xf>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&spidev0>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&gpio>;\n+\t\t__overlay__ {\n+\t\t\tlowpan0_pins: lowpan0_pins {\n+\t\t\t\tbrcm,pins = <23 24 25>;\n+\t\t\t\tbrcm,function = <0 1 1>; /* in out out */\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\tinterrupt = <&lowpan0>, \"interrupts:0\",\n+\t\t\t<&lowpan0_pins>, \"brcm,pins:0\";\n+\t\treset     = <&lowpan0>, \"reset-gpio:4\",\n+\t\t\t<&lowpan0_pins>, \"brcm,pins:4\";\n+\t\tsleep     = <&lowpan0>, \"sleep-gpio:4\",\n+\t\t\t<&lowpan0_pins>, \"brcm,pins:8\";\n+\t\tspeed     = <&lowpan0>, \"spi-max-frequency:0\";\n+\t\ttrim      = <&lowpan0>, \"xtal-trim.0\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/audioinjector-addons-overlay.dts b/arch/arm/boot/dts/overlays/audioinjector-addons-overlay.dts\nnew file mode 100644\nindex 000000000000..57a66eac8e9b\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/audioinjector-addons-overlay.dts\n@@ -0,0 +1,60 @@\n+// Definitions for audioinjector.net audio add on soundcard\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&i2s>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget-path = \"/\";\n+\t\t__overlay__ {\n+\t\t\tcs42448_mclk: codec-mclk {\n+\t\t\t\tcompatible = \"fixed-clock\";\n+\t\t\t\t#clock-cells = <0>;\n+\t\t\t\tclock-frequency = <49152000>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&i2c1>;\n+\t\t__overlay__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tcs42448: cs42448@48 {\n+\t\t\t\t#sound-dai-cells = <0>;\n+\t\t\t\tcompatible = \"cirrus,cs42448\";\n+\t\t\t\treg = <0x48>;\n+\t\t\t\tclocks = <&cs42448_mclk>;\n+\t\t\t\tclock-names = \"mclk\";\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@3 {\n+\t\ttarget = <&sound>;\n+\t\tsnd: __overlay__ {\n+\t\t\tcompatible = \"ai,audioinjector-octo-soundcard\";\n+\t\t\tmult-gpios = <&gpio 27 0>, <&gpio 22 0>, <&gpio 23 0>,\n+\t\t\t\t     <&gpio 24 0>;\n+\t\t\treset-gpios = <&gpio 5 0>;\n+\t\t\ti2s-controller = <&i2s>;\n+\t\t\tcodec = <&cs42448>;\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\tnon-stop-clocks = <&snd>, \"non-stop-clocks?\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/audioinjector-isolated-soundcard-overlay.dts b/arch/arm/boot/dts/overlays/audioinjector-isolated-soundcard-overlay.dts\nnew file mode 100644\nindex 000000000000..63e05cf9665d\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/audioinjector-isolated-soundcard-overlay.dts\n@@ -0,0 +1,55 @@\n+// Definitions for audioinjector.net audio isolated soundcard\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&i2s>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget-path = \"/\";\n+\t\t__overlay__ {\n+\t\t\tcs4272_mclk: codec-mclk {\n+\t\t\t\tcompatible = \"fixed-clock\";\n+\t\t\t\t#clock-cells = <0>;\n+\t\t\t\tclock-frequency = <24576000>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&i2c1>;\n+\t\t__overlay__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tcs4272: cs4271@10 {\n+\t\t\t\t#sound-dai-cells = <0>;\n+\t\t\t\tcompatible = \"cirrus,cs4271\";\n+\t\t\t\treg = <0x10>;\n+\t\t\t\treset-gpio = <&gpio 5 0>;\n+\t\t\t\tclocks = <&cs4272_mclk>;\n+\t\t\t\tclock-names = \"mclk\";\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@3 {\n+\t\ttarget = <&sound>;\n+\t\tsnd: __overlay__ {\n+\t\t\tcompatible = \"ai,audioinjector-isolated-soundcard\";\n+\t\t\tmute-gpios = <&gpio 17 0>;\n+\t\t\ti2s-controller = <&i2s>;\n+\t\t\tcodec = <&cs4272>;\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/audioinjector-ultra-overlay.dts b/arch/arm/boot/dts/overlays/audioinjector-ultra-overlay.dts\nnew file mode 100644\nindex 000000000000..fb4a4678a17a\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/audioinjector-ultra-overlay.dts\n@@ -0,0 +1,71 @@\n+// Definitions for audioinjector.net audio add on soundcard\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&i2s>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&i2c1>;\n+\t\t__overlay__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tcs4265: cs4265@4e {\n+\t\t\t\t#sound-dai-cells = <0>;\n+\t\t\t\tcompatible = \"cirrus,cs4265\";\n+\t\t\t\treg = <0x4e>;\n+\t\t\t\treset-gpios = <&gpio 5 0>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&sound>;\n+\t\t__overlay__ {\n+\t\t\tcompatible = \"simple-audio-card\";\n+\t\t\ti2s-controller = <&i2s>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tsimple-audio-card,name = \"audioinjector-ultra\";\n+\n+\t\t\tsimple-audio-card,widgets =\n+\t\t\t\t\"Line\", \"OUTPUTS\",\n+\t\t\t\t\"Line\", \"INPUTS\";\n+\n+\t\t\tsimple-audio-card,routing =\n+\t\t\t\t\"OUTPUTS\",\"LINEOUTL\",\n+\t\t\t\t\"OUTPUTS\",\"LINEOUTR\",\n+\t\t\t\t\"OUTPUTS\",\"SPDIFOUT\",\n+\t\t\t\t\"LINEINL\",\"INPUTS\",\n+\t\t\t\t\"LINEINR\",\"INPUTS\",\n+\t\t\t\t\"MICL\",\"INPUTS\",\n+\t\t\t\t\"MICR\",\"INPUTS\";\n+\n+\t\t\tsimple-audio-card,format = \"i2s\";\n+\n+\t\t\tsimple-audio-card,bitclock-master = <&sound_master>;\n+\t\t\tsimple-audio-card,frame-master = <&sound_master>;\n+\n+\t\t\tsimple-audio-card,cpu {\n+\t\t\t\tsound-dai = <&i2s>;\n+\t\t\t\tdai-tdm-slot-num = <2>;\n+\t\t\t\tdai-tdm-slot-width = <32>;\n+\t\t\t};\n+\n+\t\t\tsound_master: simple-audio-card,codec {\n+\t\t\t\tsound-dai = <&cs4265>;\n+\t\t\t\tsystem-clock-frequency = <12288000>;\n+\t\t\t};\n+\t\t};\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/audioinjector-wm8731-audio-overlay.dts b/arch/arm/boot/dts/overlays/audioinjector-wm8731-audio-overlay.dts\nnew file mode 100644\nindex 000000000000..68f4427d86c3\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/audioinjector-wm8731-audio-overlay.dts\n@@ -0,0 +1,39 @@\n+// Definitions for audioinjector.net audio add on soundcard\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&i2s>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&i2c1>;\n+\t\t__overlay__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\twm8731@1a {\n+\t\t\t\t#sound-dai-cells = <0>;\n+\t\t\t\tcompatible = \"wlf,wm8731\";\n+\t\t\t\treg = <0x1a>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&sound>;\n+\t\t__overlay__ {\n+\t\t\tcompatible = \"ai,audioinjector-pi-soundcard\";\n+\t\t\ti2s-controller = <&i2s>;\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/audiosense-pi-overlay.dts b/arch/arm/boot/dts/overlays/audiosense-pi-overlay.dts\nnew file mode 100644\nindex 000000000000..81af26374d92\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/audiosense-pi-overlay.dts\n@@ -0,0 +1,82 @@\n+// Definitions for audiosense add on soundcard\n+/dts-v1/;\n+/plugin/;\n+#include <dt-bindings/pinctrl/bcm2835.h>\n+#include <dt-bindings/gpio/gpio.h>\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&i2s>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget-path = \"/\";\n+\t\t__overlay__ {\n+\t\t\tcodec_reg_1v8: codec-reg-1v8 {\n+\t\t\t\tcompatible = \"regulator-fixed\";\n+\t\t\t\tregulator-name = \"tlv320aic3204_1v8\";\n+\t\t\t\tregulator-min-microvolt = <1800000>;\n+\t\t\t\tregulator-max-microvolt = <1800000>;\n+\t\t\t\tregulator-always-on;\n+\t\t\t};\n+\n+\t\t\t/* audio external oscillator */\n+\t\t\tcodec_osc: codec_osc {\n+\t\t\t\tcompatible = \"fixed-clock\";\n+\t\t\t\t#clock-cells = <0>;\n+\t\t\t\tclock-frequency = <12000000>;\t/* 12 MHz */\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&gpio>;\n+\t\t__overlay__ {\n+\t\t\tcodec_rst: codec-rst {\n+\t\t\t\tbrcm,pins = <26>;\n+\t\t\t\tbrcm,function = <BCM2835_FSEL_GPIO_OUT>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@3 {\n+\t\ttarget = <&i2c1>;\n+\t\t__overlay__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tcodec: tlv320aic32x4@18 {\n+\t\t\t\t#sound-dai-cells = <0>;\n+\t\t\t\tcompatible = \"ti,tlv320aic32x4\";\n+\t\t\t\treg = <0x18>;\n+\n+\t\t\t\tclocks = <&codec_osc>;\n+\t\t\t\tclock-names = \"mclk\";\n+\n+\t\t\t\tiov-supply = <&vdd_3v3_reg>;\n+\t\t\t\tldoin-supply = <&vdd_3v3_reg>;\n+\n+\t\t\t\tgpio-controller;\n+\t\t\t\t#gpio-cells = <2>;\n+\t\t\t\treset-gpios = <&gpio 26 GPIO_ACTIVE_HIGH>;\n+\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@4 {\n+\t\ttarget = <&sound>;\n+\t\t__overlay__ {\n+\t\t\tcompatible = \"as,audiosense-pi\";\n+\t\t\ti2s-controller = <&i2s>;\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/audremap-overlay.dts b/arch/arm/boot/dts/overlays/audremap-overlay.dts\nnew file mode 100644\nindex 000000000000..d624bb3a3fea\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/audremap-overlay.dts\n@@ -0,0 +1,35 @@\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+        compatible = \"brcm,bcm2835\";\n+\n+        fragment@0 {\n+                target = <&audio_pins>;\n+                frag0: __overlay__ {\n+                };\n+        };\n+\n+\tfragment@1 {\n+                target = <&audio_pins>;\n+                __overlay__ {\n+                        brcm,pins = < 12 13 >;\n+                        brcm,function = < 4 >; /* alt0 alt0 */\n+                };\n+        };\n+\n+\tfragment@2 {\n+\t\ttarget = <&audio_pins>;\n+\t\t__dormant__ {\n+                        brcm,pins = < 18 19 >;\n+                        brcm,function = < 2 >; /* alt5 alt5 */\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\tswap_lr = <&frag0>, \"swap_lr?\";\n+\t\tenable_jack = <&frag0>, \"enable_jack?\";\n+\t\tpins_12_13 = <0>,\"+1-2\";\n+\t\tpins_18_19 = <0>,\"-1+2\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/balena-fin-overlay.dts b/arch/arm/boot/dts/overlays/balena-fin-overlay.dts\nnew file mode 100644\nindex 000000000000..e7ead7cdf5f5\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/balena-fin-overlay.dts\n@@ -0,0 +1,125 @@\n+/dts-v1/;\n+/plugin/;\n+\n+#include <dt-bindings/gpio/gpio.h>\n+\n+/{\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&mmcnr>;\n+\t\t__overlay__ {\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&sdio_pins>;\n+\t\t\tbus-width = <4>;\n+\t\t\tbrcm,overclock-50 = <35>;\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&gpio>;\n+\t\t__overlay__ {\n+\t\t\tsdio_pins: sdio_pins {\n+\t\t\t\tbrcm,pins = <34 35 36 37 38 39>;\n+\t\t\t\tbrcm,function = <7>; /* ALT3 = SD1 */\n+\t\t\t\tbrcm,pull = <0 2 2 2 2 2>;\n+\t\t\t};\n+\n+\t\t\tpower_ctrl_pins: power_ctrl_pins {\n+\t\t\t\tbrcm,pins = <40>;\n+\t\t\t\tbrcm,function = <1>; // out\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget-path = \"/\";\n+\t\t__overlay__ {\n+\t\t\t// We should switch to mmc-pwrseq-sd8787 after making it\n+\t\t\t// compatible with sd8887\n+\t\t\t// Currently that module requires two GPIOs to function since it\n+\t\t\t// targets a slightly different chip\n+\t\t\tpower_ctrl: power_ctrl {\n+\t\t\t\tcompatible = \"gpio-poweroff\";\n+\t\t\t\tgpios = <&gpio 40 1>;\n+\t\t\t\tforce;\n+\t\t\t\tpinctrl-names = \"default\";\n+\t\t\t\tpinctrl-0 = <&power_ctrl_pins>;\n+\t\t\t};\n+\n+\t\t\ti2c_soft: i2c@0 {\n+\t\t\t\tcompatible = \"i2c-gpio\";\n+\t\t\t\tgpios = <&gpio 43 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN) /* sda */\n+\t\t\t\t         &gpio 42 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN) /* scl */>;\n+\t\t\t\ti2c-gpio,delay-us = <5>;\n+\t\t\t\ti2c-gpio,scl-open-drain;\n+\t\t\t\ti2c-gpio,sda-open-drain;\n+\t\t\t\t#address-cells = <1>;\n+\t\t\t\t#size-cells = <0>;\n+\t\t\t};\n+\n+\t\t\tsd8xxx-wlan {\n+\t\t\t\tdrvdbg = <0x6>;\n+\t\t\t\tdrv_mode = <0x1>;\n+\t\t\t\tcfg80211_wext = <0xf>;\n+\t\t\t\tsta_name = \"wlan\";\n+\t\t\t\twfd_name = \"p2p\";\n+\t\t\t\tcal_data_cfg = \"none\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@3 {\n+\t\ttarget = <&i2c_soft>;\n+\t\t__overlay__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tgpio_expander: gpio_expander@20 {\n+\t\t\t\tcompatible = \"nxp,pca9554\";\n+\t\t\t\tgpio-controller;\n+\t\t\t\t#gpio-cells = <2>;\n+\t\t\t\treg = <0x20>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\n+\t\t\t// rtc clock\n+\t\t\tds1307: ds1307@68 {\n+\t\t\t\tcompatible = \"dallas,ds1307\";\n+\t\t\t\treg = <0x68>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\n+\t\t\t// RGB LEDs (>= v1.1.0)\n+\t\t\tpca9633: pca9633@62 {\n+\t\t\t\tcompatible = \"nxp,pca9633\";\n+\t\t\t\treg = <0x62>;\n+\t\t\t\t#address-cells = <1>;\n+\t\t\t\t#size-cells = <0>;\n+\n+\t\t\t\tred@0 {\n+\t\t\t\t\tlabel = \"red\";\n+\t\t\t\t\treg = <0>;\n+\t\t\t\t\tlinux,default-trigger = \"none\";\n+\t\t\t\t};\n+\t\t\t\tgreen@1 {\n+\t\t\t\t\tlabel = \"green\";\n+\t\t\t\t\treg = <1>;\n+\t\t\t\t\tlinux,default-trigger = \"none\";\n+\t\t\t\t};\n+\t\t\t\tblue@2 {\n+\t\t\t\t\tlabel = \"blue\";\n+\t\t\t\t\treg = <2>;\n+\t\t\t\t\tlinux,default-trigger = \"none\";\n+\t\t\t\t};\n+\t\t\t\tunused@3 {\n+\t\t\t\t\tlabel = \"unused\";\n+\t\t\t\t\treg = <3>;\n+\t\t\t\t\tlinux,default-trigger = \"none\";\n+\t\t\t\t};\n+\t\t\t};\n+\t\t};\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/cma-overlay.dts b/arch/arm/boot/dts/overlays/cma-overlay.dts\nnew file mode 100644\nindex 000000000000..1d87c599f909\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/cma-overlay.dts\n@@ -0,0 +1,36 @@\n+/*\n+ * cma.dts\n+ */\n+\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&cma>;\n+\t\tfrag0: __overlay__ {\n+\t\t\t/*\n+\t\t\t * The default size when using this overlay is 256 MB\n+\t\t\t * and should be kept as is for backwards\n+\t\t\t * compatibility.\n+\t\t\t */\n+\t\t\tsize = <0x10000000>;\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\tcma-512 = <&frag0>,\"size:0=\",<0x20000000>;\n+\t\tcma-448 = <&frag0>,\"size:0=\",<0x1c000000>;\n+\t\tcma-384 = <&frag0>,\"size:0=\",<0x18000000>;\n+\t\tcma-320 = <&frag0>,\"size:0=\",<0x14000000>;\n+\t\tcma-256 = <&frag0>,\"size:0=\",<0x10000000>;\n+\t\tcma-192 = <&frag0>,\"size:0=\",<0xC000000>;\n+\t\tcma-128 = <&frag0>,\"size:0=\",<0x8000000>;\n+\t\tcma-96  = <&frag0>,\"size:0=\",<0x6000000>;\n+\t\tcma-64  = <&frag0>,\"size:0=\",<0x4000000>;\n+\t\tcma-size = <&frag0>,\"size:0\"; /* in bytes, 4MB aligned */\n+\t\tcma-default = <0>,\"-0\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/dht11-overlay.dts b/arch/arm/boot/dts/overlays/dht11-overlay.dts\nnew file mode 100644\nindex 000000000000..6feeeb402493\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/dht11-overlay.dts\n@@ -0,0 +1,41 @@\n+/*\n+ * Overlay for the DHT11/21/22 humidity/temperature sensor modules.\n+ */\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget-path = \"/\";\n+\t\t__overlay__ {\n+\n+\t\t\tdht11: dht11@0 {\n+\t\t\t\tcompatible = \"dht11\";\n+\t\t\t\tpinctrl-names = \"default\";\n+\t\t\t\tpinctrl-0 = <&dht11_pins>;\n+\t\t\t\tgpios = <&gpio 4 0>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&gpio>;\n+\t\t__overlay__ {\n+\t\t\tdht11_pins: dht11_pins@0 {\n+\t\t\t\tbrcm,pins = <4>;\n+\t\t\t\tbrcm,function = <0>; // in\n+\t\t\t\tbrcm,pull = <0>; // off\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\tgpiopin = <&dht11_pins>,\"brcm,pins:0\",\n+\t\t\t<&dht11_pins>, \"reg:0\",\n+\t\t\t<&dht11>,\"gpios:4\",\n+\t\t\t<&dht11>,\"reg:0\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/dionaudio-loco-overlay.dts b/arch/arm/boot/dts/overlays/dionaudio-loco-overlay.dts\nnew file mode 100644\nindex 000000000000..d863e5c167cc\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/dionaudio-loco-overlay.dts\n@@ -0,0 +1,39 @@\n+// Definitions for Dion Audio LOCO DAC-AMP\n+\n+/*\n+ * PCM5242 DAC (in hardware mode) and TPA3118 AMP.\n+ */\n+\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&i2s>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget-path = \"/\";\n+\t\t__overlay__ {\n+\t\t\tpcm5102a-codec {\n+\t\t\t\t#sound-dai-cells = <0>;\n+\t\t\t\tcompatible = \"ti,pcm5102a\";\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&sound>;\n+\t\t__overlay__ {\n+\t\t\tcompatible = \"dionaudio,loco-pcm5242-tpa3118\";\n+\t\t\ti2s-controller = <&i2s>;\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/dionaudio-loco-v2-overlay.dts b/arch/arm/boot/dts/overlays/dionaudio-loco-v2-overlay.dts\nnew file mode 100644\nindex 000000000000..dfb8922a654b\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/dionaudio-loco-v2-overlay.dts\n@@ -0,0 +1,49 @@\n+/*\n+ * Definitions for Dion Audio LOCO-V2 DAC-AMP\n+ *  eg. dtoverlay=dionaudio-loco-v2\n+ *\n+ * PCM5242 DAC (in software mode) and TPA3255 AMP.\n+ */\n+\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&sound>;\n+\t\tfrag0: __overlay__ {\n+\t\t\tcompatible = \"dionaudio,dionaudio-loco-v2\";\n+\t\t\ti2s-controller = <&i2s>;\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&i2s>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&i2c1>;\n+\t\t__overlay__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tpcm5122@4c {\n+\t\t\t\t#sound-dai-cells = <0>;\n+\t\t\t\tcompatible = \"ti,pcm5122\";\n+\t\t\t\treg = <0x4d>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\t24db_digital_gain = <&frag0>,\"dionaudio,24db_digital_gain?\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/disable-bt-overlay.dts b/arch/arm/boot/dts/overlays/disable-bt-overlay.dts\nnew file mode 100644\nindex 000000000000..d5a66e5d76a9\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/disable-bt-overlay.dts\n@@ -0,0 +1,64 @@\n+/dts-v1/;\n+/plugin/;\n+\n+/* Disable Bluetooth and restore UART0/ttyAMA0 over GPIOs 14 & 15.\n+   To disable the systemd service that initialises the modem so it doesn't use\n+   the UART:\n+\n+       sudo systemctl disable hciuart\n+*/\n+\n+#include <dt-bindings/gpio/gpio.h>\n+\n+/{\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&uart1>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&uart0>;\n+\t\t__overlay__ {\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&uart0_pins>;\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&bt>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\tfragment@3 {\n+\t\ttarget = <&uart0_pins>;\n+\t\t__overlay__ {\n+\t\t\tbrcm,pins;\n+\t\t\tbrcm,function;\n+\t\t\tbrcm,pull;\n+\t\t};\n+\t};\n+\n+\tfragment@4 {\n+\t\ttarget = <&bt_pins>;\n+\t\t__overlay__ {\n+\t\t\tbrcm,pins;\n+\t\t\tbrcm,function;\n+\t\t\tbrcm,pull;\n+\t\t};\n+\t};\n+\n+\tfragment@5 {\n+\t\ttarget-path = \"/aliases\";\n+\t\t__overlay__ {\n+\t\t\tserial0 = \"/soc/serial@7e201000\";\n+\t\t\tserial1 = \"/soc/serial@7e215040\";\n+\t\t};\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/disable-wifi-overlay.dts b/arch/arm/boot/dts/overlays/disable-wifi-overlay.dts\nnew file mode 100644\nindex 000000000000..75e046463900\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/disable-wifi-overlay.dts\n@@ -0,0 +1,20 @@\n+/dts-v1/;\n+/plugin/;\n+\n+/{\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&mmc>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&mmcnr>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/dpi18-overlay.dts b/arch/arm/boot/dts/overlays/dpi18-overlay.dts\nnew file mode 100644\nindex 000000000000..4abe5be744db\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/dpi18-overlay.dts\n@@ -0,0 +1,39 @@\n+/dts-v1/;\n+/plugin/;\n+\n+/{\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\t// There is no DPI driver module, but we need a platform device\n+\t// node (that doesn't already use pinctrl) to hang the pinctrl\n+\t// reference on - leds will do\n+\n+\tfragment@0 {\n+\t\ttarget = <&fb>;\n+\t\t__overlay__ {\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&dpi18_pins>;\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&vc4>;\n+\t\t__overlay__ {\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&dpi18_pins>;\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&gpio>;\n+\t\t__overlay__ {\n+\t\t\tdpi18_pins: dpi18_pins {\n+\t\t\t\tbrcm,pins = <0 1 2 3 4 5 6 7 8 9 10 11\n+\t\t\t\t\t     12 13 14 15 16 17 18 19 20\n+\t\t\t\t\t     21>;\n+\t\t\t\tbrcm,function = <6>; /* alt2 */\n+\t\t\t\tbrcm,pull = <0>; /* no pull */\n+\t\t\t};\n+\t\t};\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/dpi24-overlay.dts b/arch/arm/boot/dts/overlays/dpi24-overlay.dts\nnew file mode 100644\nindex 000000000000..44335cc81277\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/dpi24-overlay.dts\n@@ -0,0 +1,39 @@\n+/dts-v1/;\n+/plugin/;\n+\n+/{\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\t// There is no DPI driver module, but we need a platform device\n+\t// node (that doesn't already use pinctrl) to hang the pinctrl\n+\t// reference on - leds will do\n+\n+\tfragment@0 {\n+\t\ttarget = <&fb>;\n+\t\t__overlay__ {\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&dpi24_pins>;\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&vc4>;\n+\t\t__overlay__ {\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&dpi24_pins>;\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&gpio>;\n+\t\t__overlay__ {\n+\t\t\tdpi24_pins: dpi24_pins {\n+\t\t\t\tbrcm,pins = <0 1 2 3 4 5 6 7 8 9 10 11\n+\t\t\t\t\t     12 13 14 15 16 17 18 19 20\n+\t\t\t\t\t     21 22 23 24 25 26 27>;\n+\t\t\t\tbrcm,function = <6>; /* alt2 */\n+\t\t\t\tbrcm,pull = <0>; /* no pull */\n+\t\t\t};\n+\t\t};\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/draws-overlay.dts b/arch/arm/boot/dts/overlays/draws-overlay.dts\nnew file mode 100644\nindex 000000000000..d18187d7f343\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/draws-overlay.dts\n@@ -0,0 +1,208 @@\n+#include <dt-bindings/clock/bcm2835.h>\n+/*\n+ * Device tree overlay for the DRAWS Hardware\n+ */\n+\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+    compatible = \"brcm,bcm2835\";\n+    fragment@0 {\n+        target = <&i2s>;\n+        __overlay__ {\n+            status = \"okay\";\n+        };\n+    };\n+\n+    fragment@1 {\n+        target-path = \"/\";\n+        __overlay__ {\n+            regulators {\n+                compatible = \"simple-bus\";\n+                #address-cells = <1>;\n+                #size-cells = <0>;\n+\n+                udrc0_ldoin: udrc0_ldoin {\n+                    compatible = \"regulator-fixed\";\n+                    regulator-name = \"ldoin\";\n+                    regulator-min-microvolt = <3300000>;\n+                    regulator-max-microvolt = <3300000>;\n+                    regulator-always-on;\n+                };\n+\n+                sc16is752_clk: sc16is752_draws_clk {\n+                    compatible = \"fixed-clock\";\n+                    #clock-cells = <0>;\n+                    clock-frequency = <1843200>;\n+                };\n+            };\n+\n+            pps: pps {\n+                compatible = \"pps-gpio\";\n+                pinctrl-names = \"default\";\n+                pinctrl-0 = <&pps_pins>;\n+                gpios = <&gpio 7 0>;\n+                status = \"okay\";\n+            };\n+\n+            iio-hwmon {\n+                compatible = \"iio-hwmon\";\n+                status = \"okay\";\n+                io-channels = <&tla2024 4>, <&tla2024 5>, <&tla2024 6>,\n+                              <&tla2024 7>;\n+            };\n+        };\n+    };\n+\n+    fragment@2 {\n+        target = <&i2c_arm>;\n+        __overlay__ {\n+            #address-cells = <1>;\n+            #size-cells = <0>;\n+            status = \"okay\";\n+\n+            tlv320aic32x4: tlv320aic32x4@18 {\n+                compatible = \"ti,tlv320aic32x4\";\n+                reg = <0x18>;\n+                #sound-dai-cells = <0>;\n+                status = \"okay\";\n+\n+                clocks = <&clocks BCM2835_CLOCK_GP0>;\n+                clock-names = \"mclk\";\n+                assigned-clocks = <&clocks BCM2835_CLOCK_GP0>;\n+                assigned-clock-rates = <25000000>;\n+\n+                pinctrl-names = \"default\";\n+                pinctrl-0 = <&gpclk0_pin &aic3204_reset>;\n+\n+                reset-gpios = <&gpio 13 0>;\n+\n+                iov-supply = <&udrc0_ldoin>;\n+                ldoin-supply = <&udrc0_ldoin>;\n+            };\n+\n+            sc16is752: sc16is752@50 {\n+                compatible = \"nxp,sc16is752\";\n+                reg = <0x50>;\n+                clocks = <&sc16is752_clk>;\n+                interrupt-parent = <&gpio>;\n+                interrupts = <17 2>; /* IRQ_TYPE_EDGE_FALLING */\n+\n+                pinctrl-names = \"default\";\n+                pinctrl-0 = <&sc16is752_irq>;\n+            };\n+\n+            tla2024: tla2024@48 {\n+                compatible = \"ti,ads1015\";\n+                reg = <0x48>;\n+                #address-cells = <1>;\n+                #size-cells = <0>;\n+                #io-channel-cells = <1>;\n+\n+                adc_ch4: channel@4 {\n+                    reg = <4>;\n+                    ti,gain = <1>;\n+                    ti,datarate = <4>;\n+                };\n+\n+                adc_ch5: channel@5 {\n+                    reg = <5>;\n+                    ti,gain = <1>;\n+                    ti,datarate = <4>;\n+                };\n+\n+                adc_ch6: channel@6 {\n+                    reg = <6>;\n+                    ti,gain = <2>;\n+                    ti,datarate = <4>;\n+                };\n+\n+                adc_ch7: channel@7 {\n+                    reg = <7>;\n+                    ti,gain = <2>;\n+                    ti,datarate = <4>;\n+                };\n+            };\n+        };\n+    };\n+\n+    fragment@3 {\n+        target = <&sound>;\n+        snd: __overlay__ {\n+            compatible = \"simple-audio-card\";\n+            i2s-controller = <&i2s>;\n+            status = \"okay\";\n+\n+            simple-audio-card,name = \"draws\";\n+            simple-audio-card,format = \"i2s\";\n+\n+            simple-audio-card,bitclock-master = <&dailink0_master>;\n+            simple-audio-card,frame-master = <&dailink0_master>;\n+\n+            simple-audio-card,widgets =\n+                \"Line\", \"Line In\",\n+                \"Line\", \"Line Out\";\n+\n+            simple-audio-card,routing =\n+                \"IN1_R\", \"Line In\",\n+                \"IN1_L\", \"Line In\",\n+                \"CM_L\", \"Line In\",\n+                \"CM_R\", \"Line In\",\n+                \"Line Out\", \"LOR\",\n+                \"Line Out\", \"LOL\";\n+\n+            dailink0_master: simple-audio-card,cpu {\n+                sound-dai = <&i2s>;\n+            };\n+\n+            simple-audio-card,codec {\n+                sound-dai = <&tlv320aic32x4>;\n+            };\n+        };\n+    };\n+\n+    fragment@4 {\n+        target = <&gpio>;\n+        __overlay__ {\n+            gpclk0_pin: gpclk0_pin {\n+                brcm,pins = <4>;\n+                brcm,function = <4>;\n+            };\n+\n+            aic3204_reset: aic3204_reset {\n+                brcm,pins = <13>;\n+                brcm,function = <1>;\n+                brcm,pull = <1>;\n+            };\n+\n+            aic3204_gpio: aic3204_gpio {\n+                brcm,pins = <26>;\n+            };\n+\n+            sc16is752_irq: sc16is752_irq {\n+                brcm,pins = <17>;\n+                brcm,function = <0>;\n+                brcm,pull = <2>;\n+            };\n+\n+            pps_pins: pps_pins {\n+                brcm,pins = <7>;\n+                brcm,function = <0>;\n+                brcm,pull = <0>;\n+            };\n+        };\n+    };\n+\n+    __overrides__ {\n+        draws_adc_ch4_gain = <&adc_ch4>,\"ti,gain:0\";\n+        draws_adc_ch4_datarate = <&adc_ch4>,\"ti,datarate:0\";\n+        draws_adc_ch5_gain = <&adc_ch5>,\"ti,gain:0\";\n+        draws_adc_ch5_datarate = <&adc_ch5>,\"ti,datarate:0\";\n+        draws_adc_ch6_gain = <&adc_ch6>,\"ti,gain:0\";\n+        draws_adc_ch6_datarate = <&adc_ch6>,\"ti,datarate:0\";\n+        draws_adc_ch7_gain = <&adc_ch7>,\"ti,gain:0\";\n+        draws_adc_ch7_datarate = <&adc_ch7>,\"ti,datarate:0\";\n+        alsaname = <&snd>, \"simple-audio-card,name\";\n+    };\n+};\ndiff --git a/arch/arm/boot/dts/overlays/dwc-otg-overlay.dts b/arch/arm/boot/dts/overlays/dwc-otg-overlay.dts\nnew file mode 100644\nindex 000000000000..78c5e9f85048\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/dwc-otg-overlay.dts\n@@ -0,0 +1,14 @@\n+/dts-v1/;\n+/plugin/;\n+\n+/{\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&usb>;\n+\t\t__overlay__ {\n+\t\t\tcompatible = \"brcm,bcm2708-usb\";\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/dwc2-overlay.dts b/arch/arm/boot/dts/overlays/dwc2-overlay.dts\nnew file mode 100644\nindex 000000000000..0d83e344ad97\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/dwc2-overlay.dts\n@@ -0,0 +1,26 @@\n+/dts-v1/;\n+/plugin/;\n+\n+/{\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&usb>;\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <1>;\n+\t\tdwc2_usb: __overlay__ {\n+\t\t\tcompatible = \"brcm,bcm2835-usb\";\n+\t\t\tdr_mode = \"otg\";\n+\t\t\tg-np-tx-fifo-size = <32>;\n+\t\t\tg-rx-fifo-size = <558>;\n+\t\t\tg-tx-fifo-size = <512 512 512 512 512 256 256>;\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\tdr_mode = <&dwc2_usb>, \"dr_mode\";\n+\t\tg-np-tx-fifo-size = <&dwc2_usb>,\"g-np-tx-fifo-size:0\";\n+\t\tg-rx-fifo-size = <&dwc2_usb>,\"g-rx-fifo-size:0\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/enc28j60-overlay.dts b/arch/arm/boot/dts/overlays/enc28j60-overlay.dts\nnew file mode 100644\nindex 000000000000..7af5c2e607ea\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/enc28j60-overlay.dts\n@@ -0,0 +1,53 @@\n+// Overlay for the Microchip ENC28J60 Ethernet Controller\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&spi0>;\n+\t\t__overlay__ {\n+\t\t\t/* needed to avoid dtc warning */\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\teth1: enc28j60@0{\n+\t\t\t\tcompatible = \"microchip,enc28j60\";\n+\t\t\t\treg = <0>; /* CE0 */\n+\t\t\t\tpinctrl-names = \"default\";\n+\t\t\t\tpinctrl-0 = <&eth1_pins>;\n+\t\t\t\tinterrupt-parent = <&gpio>;\n+\t\t\t\tinterrupts = <25 0x2>; /* falling edge */\n+\t\t\t\tspi-max-frequency = <12000000>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&spidev0>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&gpio>;\n+\t\t__overlay__ {\n+\t\t\teth1_pins: eth1_pins {\n+\t\t\t\tbrcm,pins = <25>;\n+\t\t\t\tbrcm,function = <0>; /* in */\n+\t\t\t\tbrcm,pull = <0>; /* none */\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\tint_pin = <&eth1>, \"interrupts:0\",\n+\t\t          <&eth1_pins>, \"brcm,pins:0\";\n+\t\tspeed   = <&eth1>, \"spi-max-frequency:0\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/enc28j60-spi2-overlay.dts b/arch/arm/boot/dts/overlays/enc28j60-spi2-overlay.dts\nnew file mode 100644\nindex 000000000000..17cb5b8fa485\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/enc28j60-spi2-overlay.dts\n@@ -0,0 +1,47 @@\n+// Overlay for the Microchip ENC28J60 Ethernet Controller - SPI2 Compute Module\n+// Interrupt pin: 39\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&spi2>;\n+\t\t__overlay__ {\n+\t\t\t/* needed to avoid dtc warning */\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\teth1: enc28j60@0{\n+\t\t\t\tcompatible = \"microchip,enc28j60\";\n+\t\t\t\treg = <0>; /* CE0 */\n+\t\t\t\tpinctrl-names = \"default\";\n+\t\t\t\tpinctrl-0 = <&eth1_pins>;\n+\t\t\t\tinterrupt-parent = <&gpio>;\n+\t\t\t\tinterrupts = <39 0x2>; /* falling edge */\n+\t\t\t\tspi-max-frequency = <12000000>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&gpio>;\n+\t\t__overlay__ {\n+\t\t\teth1_pins: eth1_pins {\n+\t\t\t\tbrcm,pins = <39>;\n+\t\t\t\tbrcm,function = <0>; /* in */\n+\t\t\t\tbrcm,pull = <0>; /* none */\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\tint_pin = <&eth1>, \"interrupts:0\",\n+\t\t          <&eth1_pins>, \"brcm,pins:0\";\n+\t\tspeed   = <&eth1>, \"spi-max-frequency:0\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/exc3000-overlay.dts b/arch/arm/boot/dts/overlays/exc3000-overlay.dts\nnew file mode 100644\nindex 000000000000..6f087fb20661\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/exc3000-overlay.dts\n@@ -0,0 +1,48 @@\n+// Device tree overlay for I2C connected EETI EXC3000 multiple touch controller\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&gpio>;\n+\t\t__overlay__ {\n+\t\t\texc3000_pins: exc3000_pins {\n+\t\t\t\tbrcm,pins = <4>; // interrupt\n+\t\t\t\tbrcm,function = <0>; // in\n+\t\t\t\tbrcm,pull = <2>; // pull-up\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&i2c1>;\n+\t\t__overlay__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\texc3000: exc3000@2a {\n+\t\t\t\tcompatible = \"eeti,exc3000\";\n+\t\t\t\treg = <0x2a>;\n+\t\t\t\tpinctrl-names = \"default\";\n+\t\t\t\tpinctrl-0 = <&exc3000_pins>;\n+\t\t\t\tinterrupt-parent = <&gpio>;\n+\t\t\t\tinterrupts = <4 8>; // active low level-sensitive\n+\t\t\t\ttouchscreen-size-x = <4096>;\n+\t\t\t\ttouchscreen-size-y = <4096>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\tinterrupt = <&exc3000_pins>,\"brcm,pins:0\",\n+\t\t\t<&exc3000>,\"interrupts:0\";\n+\t\tsizex = <&exc3000>,\"touchscreen-size-x:0\";\n+\t\tsizey = <&exc3000>,\"touchscreen-size-y:0\";\n+\t\tinvx = <&exc3000>,\"touchscreen-inverted-x?\";\n+\t\tinvy = <&exc3000>,\"touchscreen-inverted-y?\";\n+\t\tswapxy = <&exc3000>,\"touchscreen-swapped-x-y?\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/fe-pi-audio-overlay.dts b/arch/arm/boot/dts/overlays/fe-pi-audio-overlay.dts\nnew file mode 100644\nindex 000000000000..743f14ae5768\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/fe-pi-audio-overlay.dts\n@@ -0,0 +1,70 @@\n+// Definitions for Fe-Pi Audio\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget-path = \"/\";\n+\t\t__overlay__ {\n+\t\t\tsgtl5000_mclk: sgtl5000_mclk {\n+\t\t\t\tcompatible = \"fixed-clock\";\n+\t\t\t\t#clock-cells = <0>;\n+\t\t\t\tclock-frequency = <12288000>;\n+\t\t\t\tclock-output-names = \"sgtl5000-mclk\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&soc>;\n+\t\t__overlay__ {\n+\t\t\treg_1v8: reg_1v8@0 {\n+\t\t\t\tcompatible = \"regulator-fixed\";\n+\t\t\t\tregulator-name = \"1V8\";\n+\t\t\t\tregulator-min-microvolt = <1800000>;\n+\t\t\t\tregulator-max-microvolt = <1800000>;\n+\t\t\t\tregulator-always-on;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&i2c1>;\n+\t\t__overlay__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tsgtl5000@0a {\n+\t\t\t\t#sound-dai-cells = <0>;\n+\t\t\t\tcompatible = \"fsl,sgtl5000\";\n+\t\t\t\treg = <0x0a>;\n+\t\t\t\tclocks = <&sgtl5000_mclk>;\n+\t\t\t\tmicbias-resistor-k-ohms = <2>;\n+\t\t\t\tmicbias-voltage-m-volts = <3000>;\n+\t\t\t\tVDDA-supply = <&vdd_3v3_reg>;\n+\t\t\t\tVDDIO-supply = <&vdd_3v3_reg>;\n+\t\t\t\tVDDD-supply = <&reg_1v8>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@3 {\n+\t\ttarget = <&i2s>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@4 {\n+\t\ttarget = <&sound>;\n+\t\t__overlay__ {\n+\t\t\tcompatible = \"fe-pi,fe-pi-audio\";\n+\t\t\ti2s-controller = <&i2s>;\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/fsm-demo-overlay.dts b/arch/arm/boot/dts/overlays/fsm-demo-overlay.dts\nnew file mode 100644\nindex 000000000000..9e06e388e4d3\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/fsm-demo-overlay.dts\n@@ -0,0 +1,104 @@\n+// Demo overlay for the gpio-fsm driver\n+/dts-v1/;\n+/plugin/;\n+\n+#include <dt-bindings/gpio/gpio-fsm.h>\n+\n+#define BUTTON1 GF_IP(0)\n+#define BUTTON2 GF_SW(0)\n+#define RED   GF_OP(0) // GPIO7\n+#define AMBER GF_OP(1) // GPIO8\n+#define GREEN GF_OP(2) // GPIO25\n+\n+/{\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget-path = \"/\";\n+\t\t__overlay__ {\n+\t\t\tfsm_demo: fsm-demo {\n+\t\t\t\tcompatible = \"rpi,gpio-fsm\";\n+\n+\t\t\t\tdebug = <0>;\n+\t\t\t\tgpio-controller;\n+\t\t\t\t#gpio-cells = <2>;\n+\t\t\t\tnum-soft-gpios = <1>;\n+\t\t\t\tgpio-line-names = \"button2\";\n+\t\t\t\tinput-gpios  = <&gpio 6 1>;  // BUTTON1 (active-low)\n+\t\t\t\toutput-gpios = <&gpio 7 0>,  // RED\n+\t\t\t\t\t       <&gpio 8 0>,  // AMBER\n+\t\t\t\t\t       <&gpio 25 0>; // GREEN\n+\t\t\t\tshutdown-timeout-ms = <2000>;\n+\n+\t\t\t\tstart {\n+\t\t\t\t\tstart_state;\n+\t\t\t\t\tset = <RED 1>, <AMBER 0>, <GREEN 0>;\n+\t\t\t\t\tstart2 = <GF_DELAY 250>;\n+\t\t\t\t};\n+\n+\t\t\t\tstart2 {\n+\t\t\t\t\tset = <RED 0>, <AMBER 1>;\n+\t\t\t\t\tgo = <GF_DELAY 250>;\n+\t\t\t\t};\n+\n+\t\t\t\tgo {\n+\t\t\t\t\tset = <RED 0>, <AMBER 0>, <GREEN 1>;\n+\t\t\t\t\tready_wait = <BUTTON1 0>;\n+\t\t\t\t\tshutdown1 = <GF_SHUTDOWN 0>;\n+\t\t\t\t};\n+\n+\t\t\t\tready_wait {\n+\t\t\t\t\t// Clear the soft GPIO\n+\t\t\t\t\tset = <BUTTON2 0>;\n+\t\t\t\t\tready = <GF_DELAY 1000>;\n+\t\t\t\t\tshutdown1 = <GF_SHUTDOWN 0>;\n+\t\t\t\t};\n+\n+\t\t\t\tready {\n+\t\t\t\t\tstopping = <BUTTON1 1>, <BUTTON2 1>;\n+\t\t\t\t\tshutdown1 = <GF_SHUTDOWN 0>;\n+\t\t\t\t};\n+\n+\t\t\t\tstopping {\n+\t\t\t\t\tset = <GREEN 0>, <AMBER 1>;\n+\t\t\t\t\tstopped = <GF_DELAY 1000>;\n+\t\t\t\t};\n+\n+\t\t\t\tstopped {\n+\t\t\t\t\tset = <AMBER 0>, <RED 1>;\n+\t\t\t\t\tget_set = <GF_DELAY 3000>;\n+\t\t\t\t\tshutdown1 = <GF_SHUTDOWN 0>;\n+\t\t\t\t};\n+\n+\t\t\t\tget_set {\n+\t\t\t\t\tset = <AMBER 1>;\n+\t\t\t\t\tgo = <GF_DELAY 1000>;\n+\t\t\t\t};\n+\n+\t\t\t\tshutdown1 {\n+\t\t\t\t\tset = <RED 0>, <AMBER 0>, <GREEN 1>;\n+\t\t\t\t\tshutdown2 = <GF_SHUTDOWN 250>;\n+\t\t\t\t};\n+\n+\t\t\t\tshutdown2 {\n+\t\t\t\t\tset = <AMBER 1>, <GREEN 0>;\n+\t\t\t\t\tshutdown3 = <GF_SHUTDOWN 250>;\n+\t\t\t\t};\n+\n+\t\t\t\tshutdown3 {\n+\t\t\t\t\tset = <RED 1>, <AMBER 0>;\n+\t\t\t\t\tshutdown4 = <GF_SHUTDOWN 250>;\n+\t\t\t\t};\n+\n+\t\t\t\tshutdown4 {\n+\t\t\t\t\tshutdown_state;\n+\t\t\t\t\tset = <RED 0>;\n+\t\t\t\t};\n+\t\t\t};\n+\t       };\n+        };\n+\n+\t__overrides__ {\n+\t\tfsm_debug = <&fsm_demo>,\"debug:0\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/ghost-amp-overlay.dts b/arch/arm/boot/dts/overlays/ghost-amp-overlay.dts\nnew file mode 100644\nindex 000000000000..afc9f034b5fc\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/ghost-amp-overlay.dts\n@@ -0,0 +1,119 @@\n+// Overlay for the PCM5122-based Ghost amplifier using gpio-fsm\n+/dts-v1/;\n+/plugin/;\n+\n+#include <dt-bindings/gpio/gpio-fsm.h>\n+\n+#define ENABLE GF_SW(0)\n+#define FAULT  GF_IP(0) // GPIO5\n+#define RELAY1 GF_OP(0) // GPIO22\n+#define RELAY2 GF_OP(1) // GPIO23\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&i2s>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&i2c1>;\n+\t\t__overlay__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tpcm5122@4c {\n+\t\t\t\t#sound-dai-cells = <0>;\n+\t\t\t\tcompatible = \"ti,pcm5122\";\n+\t\t\t\treg = <0x4c>;\n+\t\t\t\tAVDD-supply = <&vdd_3v3_reg>;\n+\t\t\t\tDVDD-supply = <&vdd_3v3_reg>;\n+\t\t\t\tCPVDD-supply = <&vdd_3v3_reg>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&sound>;\n+\t\tiqaudio_dac: __overlay__ {\n+\t\t\tcompatible = \"iqaudio,iqaudio-dac\";\n+\t\t\ti2s-controller = <&i2s>;\n+\t\t\tmute-gpios = <&amp 0 0>;\n+\t\t\tiqaudio-dac,auto-mute-amp;\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@3 {\n+\t\ttarget-path = \"/\";\n+\t\t__overlay__ {\n+\t\t\tamp: ghost-amp {\n+\t\t\t\tcompatible = \"rpi,gpio-fsm\";\n+\n+\t\t\t\tdebug = <0>;\n+\t\t\t\tgpio-controller;\n+\t\t\t\t#gpio-cells = <2>;\n+\t\t\t\tnum-soft-gpios = <1>;\n+\t\t\t\tgpio-line-names = \"enable\";\n+\t\t\t\tinput-gpios  = <&gpio 5 1>;  // FAULT (active low)\n+\t\t\t\toutput-gpios = <&gpio 22 0>, // RELAY1\n+\t\t\t\t\t       <&gpio 23 0>; // RELAY2\n+\t\t\t\tshutdown-timeout-ms = <1000>;\n+\n+\t\t\t\tamp_off {\n+\t\t\t\t\tstart_state;\n+\t\t\t\t\tshutdown_state;\n+\n+\t\t\t\t\tset = <RELAY2 0>,\n+\t\t\t\t\t      <RELAY1 0>;\n+\t\t\t\t\tamp_on_1 = <ENABLE 1>;\n+\t\t\t\t\tfault = <FAULT 1>;\n+\t\t\t\t};\n+\n+\t\t\t\tamp_on_1 {\n+\t\t\t\t\tset = <RELAY1 1>;\n+\t\t\t\t\tamp_on = <GF_DELAY 1500>;\n+\t\t\t\t\tamp_off = <ENABLE 0>;\n+\t\t\t\t\tfault = <FAULT 1>;\n+\t\t\t\t};\n+\n+\t\t\t\tamp_on {\n+\t\t\t\t\tset = <RELAY2 1>;\n+\t\t\t\t\tamp_off_wait = <ENABLE 0>;\n+\t\t\t\t\tfault = <FAULT 1>;\n+\t\t\t\t};\n+\n+\t\t\t\tamp_off_wait {\n+\t\t\t\t\tamp_off_1 = <GF_DELAY (30*60*1000)>,\n+\t\t\t\t\t\t    <GF_SHUTDOWN 0>;\n+\t\t\t\t\tamp_on = <ENABLE 1>;\n+\t\t\t\t\tfault = <FAULT 1>;\n+\t\t\t\t};\n+\n+\t\t\t\tamp_off_1 {\n+\t\t\t\t\tset = <RELAY2 0>;\n+\t\t\t\t\tamp_on = <ENABLE 1>;\n+\t\t\t\t\tamp_off = <GF_DELAY 100>;\n+\t\t\t\t\tfault = <FAULT 1>;\n+\t\t\t\t};\n+\n+\t\t\t\t// Keep this a distinct state to prevent\n+\t\t\t\t// changes and for the diagnostic output\n+\t\t\t\tfault {\n+\t\t\t\t\tset = <RELAY2 0>,\n+\t\t\t\t\t      <RELAY1 0>;\n+\t\t\t\t\tshutdown_state;\n+\t\t\t\t};\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\tfsm_debug = <&amp>,\"debug:0\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/goodix-overlay.dts b/arch/arm/boot/dts/overlays/goodix-overlay.dts\nnew file mode 100644\nindex 000000000000..a11d65f81c5e\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/goodix-overlay.dts\n@@ -0,0 +1,46 @@\n+// Device tree overlay for I2C connected Goodix gt9271 multiple touch controller\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&gpio>;\n+\t\t__overlay__ {\n+\t\t\tgoodix_pins: goodix_pins {\n+\t\t\t\tbrcm,pins = <4 17>; // interrupt and reset\n+\t\t\t\tbrcm,function = <0 0>; // in\n+\t\t\t\tbrcm,pull = <2 2>; // pull-up\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&i2c1>;\n+\t\t__overlay__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tgt9271: gt9271@14 {\n+\t\t\t\tcompatible = \"goodix,gt9271\";\n+\t\t\t\treg = <0x14>;\n+\t\t\t\tpinctrl-names = \"default\";\n+\t\t\t\tpinctrl-0 = <&goodix_pins>;\n+\t\t\t\tinterrupt-parent = <&gpio>;\n+\t\t\t\tinterrupts = <4 2>; // high-to-low edge triggered\n+\t\t\t\tirq-gpios = <&gpio 4 0>; // Pin7 on GPIO header\n+\t\t\t\treset-gpios = <&gpio 17 1>; // Pin11 on GPIO header\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\tinterrupt = <&goodix_pins>,\"brcm,pins:0\",\n+\t\t\t<&gt9271>,\"interrupts:0\",\n+\t\t\t<&gt9271>,\"irq-gpios:4\";\n+\t\treset = <&goodix_pins>,\"brcm,pins:4\",\n+\t\t\t<&gt9271>,\"reset-gpios:4\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/googlevoicehat-soundcard-overlay.dts b/arch/arm/boot/dts/overlays/googlevoicehat-soundcard-overlay.dts\nnew file mode 100644\nindex 000000000000..e443be1f9a0e\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/googlevoicehat-soundcard-overlay.dts\n@@ -0,0 +1,49 @@\n+// Definitions for Google voiceHAT v1 soundcard overlay\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&i2s>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&gpio>;\n+\t\t__overlay__ {\n+\t\t\tgooglevoicehat_pins: googlevoicehat_pins {\n+\t\t\t\tbrcm,pins = <16>;\n+\t\t\t\tbrcm,function = <1>; /* out */\n+\t\t\t\tbrcm,pull = <0>; /* up */\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\n+\tfragment@2 {\n+\t\ttarget-path = \"/\";\n+\t\t__overlay__ {\n+\t\t\tvoicehat-codec {\n+\t\t\t\t#sound-dai-cells = <0>;\n+\t\t\t\tcompatible = \"google,voicehat\";\n+\t\t\t\tpinctrl-names = \"default\";\n+\t\t\t\tpinctrl-0 = <&googlevoicehat_pins>;\n+\t\t\t\tsdmode-gpios= <&gpio 16 0>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@3 {\n+\t\ttarget = <&sound>;\n+\t\t__overlay__ {\n+\t\t\tcompatible = \"googlevoicehat,googlevoicehat-soundcard\";\n+\t\t\ti2s-controller = <&i2s>;\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/gpio-fan-overlay.dts b/arch/arm/boot/dts/overlays/gpio-fan-overlay.dts\nnew file mode 100644\nindex 000000000000..77a7bbb41e3b\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/gpio-fan-overlay.dts\n@@ -0,0 +1,79 @@\n+/*\n+ * Overlay for the Raspberry Pi GPIO Fan @ BCM GPIO12.\n+ * References: \n+ *\t- https://www.raspberrypi.org/forums/viewtopic.php?f=107&p=1367135#p1365084\n+ *\n+ * Optional parameters:\n+ *\t- \"gpiopin\"\t- BCM number of the pin driving the fan, default 12 (GPIO12);\n+ * \t- \"temp\"\t- CPU temperature at which fan is started in millicelsius, default 55000;\n+ *\n+ * Requires:\n+ *\t- kernel configurations: CONFIG_SENSORS_GPIO_FAN=m;\n+ *\t- kernel rebuild;\n+ *\t- N-MOSFET connected to gpiopin, 2N7002-[https://en.wikipedia.org/wiki/2N7000];\n+ *\t- DC Fan connected to N-MOSFET Drain terminal, a 12V fan is working fine and quite silently;\n+ *\t  [https://www.tme.eu/en/details/ee40101s1-999-a/dc12v-fans/sunon/ee40101s1-1000u-999/]\n+ *\n+ *                   ┌─────────────────────┐\n+ *                   │Fan negative terminal│\n+ *                   └┬────────────────────┘\n+ *                    │D\n+ *             G   │──┘\n+ * [GPIO12]──────┤ │<─┐  2N7002\n+ *                 │──┤\n+ *                    │S\n+ *                   ─┴─\n+ *                   GND\n+ *\n+ * Build:\n+ * \t- `sudo dtc -W no-unit_address_vs_reg -@ -I dts -O dtb -o /boot/overlays/gpio-fan.dtbo gpio-fan-overlay.dts`\n+ * Activate:\n+ *\t- sudo nano /boot/config.txt add \"dtoverlay=gpio-fan\" or \"dtoverlay=gpio-fan,gpiopin=12,temp=45000\"\n+ *\t or\n+ *\t- sudo sh -c 'printf \"\\n# Enable PI GPIO-Fan Default\\ndtoverlay=gpio-fan\\n\" >> /boot/config.txt'\n+ *\t- sudo sh -c 'printf \"\\n# Enable PI GPIO-Fan Custom\\ndtoverlay=gpio-fan,gpiopin=12,temp=45000\\n\" >> /boot/config.txt'\n+ *\n+ */\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget-path = \"/\";\n+\t\t__overlay__ {\n+\t\t\tfan0: gpio-fan@0 {\n+\t\t\t\tcompatible = \"gpio-fan\";\n+\t\t\t\tgpios = <&gpio 12 0>;\n+\t\t\t\tgpio-fan,speed-map = <0    0>,\n+\t\t\t\t\t\t\t\t\t <5000 1>;\n+\t\t\t\t#cooling-cells = <2>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&cpu_thermal>;\n+\t\tpolling-delay = <2000>;\t/* milliseconds */\n+\t\t__overlay__ {\n+\t\t\ttrips {\n+\t\t\t\tcpu_hot: trip-point@0 {\n+\t\t\t\t\ttemperature = <55000>;\t/* (millicelsius) Fan started at 55°C */\n+\t\t\t\t\thysteresis = <10000>;\t/* (millicelsius) Fan stopped at 45°C */\n+\t\t\t\t\ttype = \"active\";\n+\t\t\t\t};\n+\t\t\t};\n+\t\t\tcooling-maps {\n+\t\t\t\tmap0 {\n+\t\t\t\t\ttrip = <&cpu_hot>;\n+\t\t\t\t\tcooling-device = <&fan0 1 1>;\n+\t\t\t\t};\n+\t\t\t};\n+\t\t};\n+\t};\n+\t__overrides__ {\n+\t\tgpiopin = <&fan0>,\"gpios:4\", <&fan0>,\"brcm,pins:0\";\n+\t\ttemp = <&cpu_hot>,\"temperature:0\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/gpio-ir-overlay.dts b/arch/arm/boot/dts/overlays/gpio-ir-overlay.dts\nnew file mode 100644\nindex 000000000000..162b6ce07dc9\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/gpio-ir-overlay.dts\n@@ -0,0 +1,49 @@\n+// Definitions for ir-gpio module\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+        compatible = \"brcm,bcm2835\";\n+\n+        fragment@0 {\n+                target-path = \"/\";\n+                __overlay__ {\n+                        gpio_ir: ir-receiver@12 {\n+                                compatible = \"gpio-ir-receiver\";\n+                                pinctrl-names = \"default\";\n+                                pinctrl-0 = <&gpio_ir_pins>;\n+\n+                                // pin number, high or low\n+                                gpios = <&gpio 18 1>;\n+\n+                                // parameter for keymap name\n+                                linux,rc-map-name = \"rc-rc6-mce\";\n+\n+                                status = \"okay\";\n+                        };\n+                };\n+        };\n+\n+        fragment@1 {\n+                target = <&gpio>;\n+                __overlay__ {\n+                        gpio_ir_pins: gpio_ir_pins@12 {\n+                                brcm,pins = <18>;                       // pin 18\n+                                brcm,function = <0>;                    // in\n+                                brcm,pull = <2>;                        // up\n+                        };\n+                };\n+        };\n+\n+        __overrides__ {\n+                // parameters\n+                gpio_pin =      <&gpio_ir>,\"gpios:4\",           // pin number\n+                                <&gpio_ir>,\"reg:0\",\n+                                <&gpio_ir_pins>,\"brcm,pins:0\",\n+                                <&gpio_ir_pins>,\"reg:0\";\n+                gpio_pull = <&gpio_ir_pins>,\"brcm,pull:0\";              // pull-up/down state\n+                invert = <&gpio_ir>,\"gpios:8\";                          // 0 = active high input\n+\n+                rc-map-name = <&gpio_ir>,\"linux,rc-map-name\";           // default rc map\n+        };\n+};\ndiff --git a/arch/arm/boot/dts/overlays/gpio-ir-tx-overlay.dts b/arch/arm/boot/dts/overlays/gpio-ir-tx-overlay.dts\nnew file mode 100644\nindex 000000000000..3625431b7560\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/gpio-ir-tx-overlay.dts\n@@ -0,0 +1,36 @@\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&gpio>;\n+\t\t__overlay__ {\n+\t\t\tgpio_ir_tx_pins: gpio_ir_tx_pins@12 {\n+\t\t\t\tbrcm,pins = <18>;\n+\t\t\t\tbrcm,function = <1>;\t// out\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget-path = \"/\";\n+\t\t__overlay__ {\n+\t\t\tgpio_ir_tx: gpio-ir-transmitter@12 {\n+\t\t\t\tcompatible = \"gpio-ir-tx\";\n+\t\t\t\tpinctrl-names = \"default\";\n+\t\t\t\tpinctrl-0 = <&gpio_ir_tx_pins>;\n+\t\t\t\tgpios = <&gpio 18 0>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\tgpio_pin = <&gpio_ir_tx>, \"gpios:4\",           \t// pin number\n+\t\t\t   <&gpio_ir_tx>, \"reg:0\",\n+\t\t\t   <&gpio_ir_tx_pins>, \"brcm,pins:0\",\n+\t\t\t   <&gpio_ir_tx_pins>, \"reg:0\";\n+\t\tinvert = <&gpio_ir_tx>, \"gpios:8\";\t\t// 1 = active low\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/gpio-key-overlay.dts b/arch/arm/boot/dts/overlays/gpio-key-overlay.dts\nnew file mode 100644\nindex 000000000000..2e7253d1d0ab\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/gpio-key-overlay.dts\n@@ -0,0 +1,48 @@\n+// Definitions for gpio-key module\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\t// Configure the gpio pin controller\n+\t\ttarget = <&gpio>;\n+\t\t__overlay__ {\n+\t\t\tpin_state: button_pins@0 {\n+\t\t\t\tbrcm,pins = <3>; // gpio number\n+\t\t\t\tbrcm,function = <0>; // 0 = input, 1 = output\n+\t\t\t\tbrcm,pull = <2>; // 0 = none, 1 = pull down, 2 = pull up\n+\t\t\t};\n+\t\t};\n+\t};\n+\tfragment@1 {\n+\t\ttarget-path = \"/\";\n+\t\t__overlay__ {\n+\t\t\tbutton: button@0 {\n+\t\t\t\tcompatible = \"gpio-keys\";\n+\t\t\t\tpinctrl-names = \"default\";\n+\t\t\t\tpinctrl-0 = <&pin_state>;\n+\t\t\t\tstatus = \"okay\";\n+\n+\t\t\t\tkey: key {\n+\t\t\t\t\tlinux,code = <116>;\n+\t\t\t\t\tgpios = <&gpio 3 1>;\n+\t\t\t\t\tlabel = \"KEY_POWER\";\n+\t\t\t\t};\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\tgpio =       <&key>,\"gpios:4\",\n+\t\t             <&button>,\"reg:0\",\n+\t\t             <&pin_state>,\"brcm,pins:0\",\n+\t\t             <&pin_state>,\"reg:0\";\n+\t\tlabel =      <&key>,\"label\";\n+\t\tkeycode =    <&key>,\"linux,code:0\";\n+\t\tgpio_pull =  <&pin_state>,\"brcm,pull:0\";\n+\t\tactive_low = <&key>,\"gpios:8\";\n+\t};\n+\n+};\ndiff --git a/arch/arm/boot/dts/overlays/gpio-no-bank0-irq-overlay.dts b/arch/arm/boot/dts/overlays/gpio-no-bank0-irq-overlay.dts\nnew file mode 100755\nindex 000000000000..96cbe80820b7\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/gpio-no-bank0-irq-overlay.dts\n@@ -0,0 +1,14 @@\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\t// Configure the gpio pin controller\n+\t\ttarget = <&gpio>;\n+\t\t__overlay__ {\n+\t\t\t    interrupts = <255 255>, <2 18>;\n+\t\t};\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/gpio-no-irq-overlay.dts b/arch/arm/boot/dts/overlays/gpio-no-irq-overlay.dts\nnew file mode 100644\nindex 000000000000..55f9bff3a8f6\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/gpio-no-irq-overlay.dts\n@@ -0,0 +1,14 @@\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\t// Configure the gpio pin controller\n+\t\ttarget = <&gpio>;\n+\t\t__overlay__ {\n+\t\t\t    interrupts;\n+\t\t};\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/gpio-poweroff-overlay.dts b/arch/arm/boot/dts/overlays/gpio-poweroff-overlay.dts\nnew file mode 100644\nindex 000000000000..416aa2bc797a\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/gpio-poweroff-overlay.dts\n@@ -0,0 +1,37 @@\n+// Definitions for gpio-poweroff module\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget-path = \"/\";\n+\t\t__overlay__ {\n+\t\t\tpower_ctrl: power_ctrl {\n+\t\t\t\tcompatible = \"gpio-poweroff\";\n+\t\t\t\tgpios = <&gpio 26 0>;\n+\t\t\t\tforce;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&gpio>;\n+\t\t__overlay__ {\n+\t\t\tpower_ctrl_pins: power_ctrl_pins {\n+\t\t\t\tbrcm,pins = <26>;\n+\t\t\t\tbrcm,function = <1>; // out\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\tgpiopin =       <&power_ctrl>,\"gpios:4\",\n+\t\t\t\t<&power_ctrl_pins>,\"brcm,pins:0\";\n+\t\tactive_low =    <&power_ctrl>,\"gpios:8\";\n+\t\tinput =         <&power_ctrl>,\"input?\";\n+\t\texport =        <&power_ctrl>,\"export?\";\n+\t\ttimeout_ms =    <&power_ctrl>,\"timeout-ms:0\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/gpio-shutdown-overlay.dts b/arch/arm/boot/dts/overlays/gpio-shutdown-overlay.dts\nnew file mode 100644\nindex 000000000000..0a27595143ec\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/gpio-shutdown-overlay.dts\n@@ -0,0 +1,84 @@\n+// Definitions for gpio-poweroff module\n+/dts-v1/;\n+/plugin/;\n+\n+// This overlay sets up an input device that generates KEY_POWER events\n+// when a given GPIO pin changes. It defaults to using GPIO3, which can\n+// also be used to wake up (start) the Rpi again after shutdown.\n+// Raspberry Pi 1 Model B rev 1 can be wake up only by GPIO1 pin, so for\n+// these boards change default GPIO pin to 1 via gpio_pin parameter. Since\n+// wakeup is active-low, this defaults to active-low with a pullup\n+// enabled, but all of this can be changed using overlay parameters (but\n+// note that GPIO3 has an external pullup on at least some boards).\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\t// Configure the gpio pin controller\n+\t\ttarget = <&gpio>;\n+\t\t__overlay__ {\n+\t\t\t// Define a pinctrl state, that sets up the gpio\n+\t\t\t// as an input with a pullup enabled. This does\n+\t\t\t// not take effect by itself, only when referenced\n+\t\t\t// by a \"pinctrl client\", as is done below. See:\n+\t\t\t//   https://www.kernel.org/doc/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt\n+\t\t\t//   https://www.kernel.org/doc/Documentation/devicetree/bindings/pinctrl/brcm,bcm2835-gpio.txt\n+\t\t\tpin_state: shutdown_button_pins {\n+\t\t\t\tbrcm,pins = <3>; // gpio number\n+\t\t\t\tbrcm,function = <0>; // 0 = input, 1 = output\n+\t\t\t\tbrcm,pull = <2>; // 0 = none, 1 = pull down, 2 = pull up\n+\t\t\t};\n+\t\t};\n+\t};\n+\tfragment@1 {\n+\t\t// Add a new device to the /soc devicetree node\n+\t\ttarget-path = \"/soc\";\n+\t\t__overlay__ {\n+\t\t\tshutdown_button {\n+\t\t\t\t// Let the gpio-keys driver handle this device. See:\n+\t\t\t\t// https://www.kernel.org/doc/Documentation/devicetree/bindings/input/gpio-keys.txt\n+\t\t\t\tcompatible = \"gpio-keys\";\n+\n+\t\t\t\t// Declare a single pinctrl state (referencing the one declared above) and name it\n+\t\t\t\t// default, so it is activated automatically.\n+\t\t\t\tpinctrl-names = \"default\";\n+\t\t\t\tpinctrl-0 = <&pin_state>;\n+\n+\t\t\t\t// Enable this device\n+\t\t\t\tstatus = \"okay\";\n+\n+\t\t\t\t// Define a single key, called \"shutdown\" that monitors the gpio and sends KEY_POWER\n+\t\t\t\t// (keycode 116, see\n+\t\t\t\t// https://github.com/torvalds/linux/blob/v4.12/include/uapi/linux/input-event-codes.h#L190)\n+\t\t\t\tbutton: shutdown {\n+\t\t\t\t\tlabel = \"shutdown\";\n+\t\t\t\t\tlinux,code = <116>; // KEY_POWER\n+\t\t\t\t\tgpios = <&gpio 3 1>;\n+\t\t\t\t\tdebounce-interval = <100>; // ms\n+\t\t\t\t};\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t// This defines parameters that can be specified when loading\n+\t// the overlay. Each foo = line specifies one parameter, named\n+\t// foo. The rest of the specification gives properties where the\n+\t// parameter value is inserted into (changing the values above\n+\t// or adding new ones).\n+\t__overrides__ {\n+\t\t// Allow overriding the GPIO number.\n+\t\tgpio_pin = <&button>,\"gpios:4\",\n+\t\t           <&pin_state>,\"brcm,pins:0\";\n+\n+\t\t// Allow changing the internal pullup/down state. 0 = none, 1 = pulldown, 2 = pullup\n+\t\t// Note that GPIO3 and GPIO2 are the I2c pins and have an external pullup (at least\n+\t\t// on some boards). Same applies for GPIO1 on Raspberry Pi 1 Model B rev 1.\n+\t\tgpio_pull = <&pin_state>,\"brcm,pull:0\";\n+\n+\t\t// Allow setting the active_low flag. 0 = active high, 1 = active low\n+\t\tactive_low = <&button>,\"gpios:8\";\n+\t\tdebounce = <&button>,\"debounce-interval:0\";\n+\t};\n+\n+};\ndiff --git a/arch/arm/boot/dts/overlays/hd44780-lcd-overlay.dts b/arch/arm/boot/dts/overlays/hd44780-lcd-overlay.dts\nnew file mode 100644\nindex 000000000000..ee726669ff51\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/hd44780-lcd-overlay.dts\n@@ -0,0 +1,46 @@\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+    compatible = \"brcm,bcm2835\";\n+\n+    fragment@0 {\n+        target-path = \"/\";\n+        __overlay__ {\n+            lcd_screen: auxdisplay {\n+                compatible = \"hit,hd44780\";\n+\n+                data-gpios = <&gpio 6 0>,\n+                             <&gpio 13 0>,\n+                             <&gpio 19 0>,\n+                             <&gpio 26 0>;\n+                enable-gpios = <&gpio 21 0>;\n+                rs-gpios = <&gpio 20 0>;\n+\n+                display-height-chars = <2>;\n+                display-width-chars = <16>;\n+            };\n+\n+        };\n+    };\n+\n+    fragment@1 {\n+       target = <&lcd_screen>;\n+        __dormant__ {\n+            backlight-gpios = <&gpio 12 0>;\n+        };\n+    };\n+\n+    __overrides__ {\n+        pin_d4 = <&lcd_screen>,\"data-gpios:4\";\n+        pin_d5 = <&lcd_screen>,\"data-gpios:16\";\n+        pin_d6 = <&lcd_screen>,\"data-gpios:28\";\n+        pin_d7 = <&lcd_screen>,\"data-gpios:40\";\n+        pin_en = <&lcd_screen>,\"enable-gpios:4\";\n+        pin_rs = <&lcd_screen>,\"rs-gpios:4\";\n+        pin_bl = <0>,\"+1\", <&lcd_screen>,\"backlight-gpios:4\";\n+        display_height = <&lcd_screen>,\"display-height-chars:0\";\n+        display_width = <&lcd_screen>,\"display-width-chars:0\";\n+    };\n+\n+};\ndiff --git a/arch/arm/boot/dts/overlays/hdmi-backlight-hwhack-gpio-overlay.dts b/arch/arm/boot/dts/overlays/hdmi-backlight-hwhack-gpio-overlay.dts\nnew file mode 100644\nindex 000000000000..50b9a2665c80\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/hdmi-backlight-hwhack-gpio-overlay.dts\n@@ -0,0 +1,47 @@\n+/*\n+ * Devicetree overlay for GPIO based backlight on/off capability.\n+ *\n+ * Use this if you have one of those HDMI displays whose backlight cannot be\n+ * controlled via DPMS over HDMI and plan to do a little soldering to use an\n+ * RPi gpio pin for on/off switching.\n+ *\n+ * See: https://www.waveshare.com/wiki/7inch_HDMI_LCD_(C)#Backlight_Control\n+ *\n+ */\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@1 {\n+\t\ttarget = <&gpio>;\n+\t\t__overlay__ {\n+\t\t\thdmi_backlight_hwhack_gpio_pins: hdmi_backlight_hwhack_gpio_pins {\n+\t\t\t\tbrcm,pins = <17>;\n+\t\t\t\tbrcm,function = <1>; /* out */\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget-path = \"/\";\n+\t\t__overlay__ {\n+\t\t\thdmi_backlight_hwhack_gpio: hdmi_backlight_hwhack_gpio {\n+\t\t\t\tcompatible = \"gpio-backlight\";\n+\n+\t\t\t\tpinctrl-names = \"default\";\n+\t\t\t\tpinctrl-0 = <&hdmi_backlight_hwhack_gpio_pins>;\n+\n+\t\t\t\tgpios = <&gpio 17 0>;\n+\t\t\t\tdefault-on;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\tgpio_pin   = <&hdmi_backlight_hwhack_gpio>,\"gpios:4\",\n+\t\t             <&hdmi_backlight_hwhack_gpio_pins>,\"brcm,pins:0\";\n+\t\tactive_low = <&hdmi_backlight_hwhack_gpio>,\"gpios:8\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/hifiberry-amp-overlay.dts b/arch/arm/boot/dts/overlays/hifiberry-amp-overlay.dts\nnew file mode 100644\nindex 000000000000..142518ab348b\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/hifiberry-amp-overlay.dts\n@@ -0,0 +1,39 @@\n+// Definitions for HiFiBerry Amp/Amp+\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&i2s>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&i2c1>;\n+\t\t__overlay__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\ttas5713@1b {\n+\t\t\t\t#sound-dai-cells = <0>;\n+\t\t\t\tcompatible = \"ti,tas5713\";\n+\t\t\t\treg = <0x1b>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&sound>;\n+\t\t__overlay__ {\n+\t\t\tcompatible = \"hifiberry,hifiberry-amp\";\n+\t\t\ti2s-controller = <&i2s>;\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/hifiberry-dac-overlay.dts b/arch/arm/boot/dts/overlays/hifiberry-dac-overlay.dts\nnew file mode 100644\nindex 000000000000..ea8a6c8f36c0\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/hifiberry-dac-overlay.dts\n@@ -0,0 +1,34 @@\n+// Definitions for HiFiBerry DAC\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&i2s>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget-path = \"/\";\n+\t\t__overlay__ {\n+\t\t\tpcm5102a-codec {\n+\t\t\t\t#sound-dai-cells = <0>;\n+\t\t\t\tcompatible = \"ti,pcm5102a\";\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&sound>;\n+\t\t__overlay__ {\n+\t\t\tcompatible = \"hifiberry,hifiberry-dac\";\n+\t\t\ti2s-controller = <&i2s>;\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/hifiberry-dacplus-overlay.dts b/arch/arm/boot/dts/overlays/hifiberry-dacplus-overlay.dts\nnew file mode 100644\nindex 000000000000..ff19015ba656\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/hifiberry-dacplus-overlay.dts\n@@ -0,0 +1,65 @@\n+// Definitions for HiFiBerry DAC+\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget-path = \"/\";\n+\t\t__overlay__ {\n+\t\t\tdacpro_osc: dacpro_osc {\n+\t\t\t\tcompatible = \"hifiberry,dacpro-clk\";\n+\t\t\t\t#clock-cells = <0>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&i2s>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&i2c1>;\n+\t\t__overlay__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tpcm5122@4d {\n+\t\t\t\t#sound-dai-cells = <0>;\n+\t\t\t\tcompatible = \"ti,pcm5122\";\n+\t\t\t\treg = <0x4d>;\n+\t\t\t\tclocks = <&dacpro_osc>;\n+\t\t\t\tAVDD-supply = <&vdd_3v3_reg>;\n+\t\t\t\tDVDD-supply = <&vdd_3v3_reg>;\n+\t\t\t\tCPVDD-supply = <&vdd_3v3_reg>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t\thpamp: hpamp@60 {\n+\t\t\t\tcompatible = \"ti,tpa6130a2\";\n+\t\t\t\treg = <0x60>;\n+\t\t\t\tstatus = \"disabled\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@3 {\n+\t\ttarget = <&sound>;\n+\t\thifiberry_dacplus: __overlay__ {\n+\t\t\tcompatible = \"hifiberry,hifiberry-dacplus\";\n+\t\t\ti2s-controller = <&i2s>;\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\t24db_digital_gain =\n+\t\t\t<&hifiberry_dacplus>,\"hifiberry,24db_digital_gain?\";\n+\t\tslave = <&hifiberry_dacplus>,\"hifiberry-dacplus,slave?\";\n+\t\tleds_off = <&hifiberry_dacplus>,\"hifiberry-dacplus,leds_off?\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/hifiberry-dacplusadc-overlay.dts b/arch/arm/boot/dts/overlays/hifiberry-dacplusadc-overlay.dts\nnew file mode 100644\nindex 000000000000..540563dec10f\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/hifiberry-dacplusadc-overlay.dts\n@@ -0,0 +1,72 @@\n+// Definitions for HiFiBerry DAC+ADC\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget-path = \"/\";\n+\t\t__overlay__ {\n+\t\t\tdacpro_osc: dacpro_osc {\n+\t\t\t\tcompatible = \"hifiberry,dacpro-clk\";\n+\t\t\t\t#clock-cells = <0>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&i2s>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&i2c1>;\n+\t\t__overlay__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tpcm_codec: pcm5122@4d {\n+\t\t\t\t#sound-dai-cells = <0>;\n+\t\t\t\tcompatible = \"ti,pcm5122\";\n+\t\t\t\treg = <0x4d>;\n+\t\t\t\tclocks = <&dacpro_osc>;\n+\t\t\t\tAVDD-supply = <&vdd_3v3_reg>;\n+\t\t\t\tDVDD-supply = <&vdd_3v3_reg>;\n+\t\t\t\tCPVDD-supply = <&vdd_3v3_reg>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@3 {\n+\t\ttarget-path = \"/\";\n+\t\t__overlay__ {\n+\t\t\tdmic {\n+\t\t\t\t#sound-dai-cells = <0>;\n+\t\t\t\tcompatible = \"dmic-codec\";\n+\t\t\t\tnum-channels = <2>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@4 {\n+\t\ttarget = <&sound>;\n+\t\thifiberry_dacplusadc: __overlay__ {\n+\t\t\tcompatible = \"hifiberry,hifiberry-dacplusadc\";\n+\t\t\ti2s-controller = <&i2s>;\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\t24db_digital_gain =\n+\t\t\t<&hifiberry_dacplusadc>,\"hifiberry,24db_digital_gain?\";\n+\t\tslave = <&hifiberry_dacplusadc>,\"hifiberry-dacplusadc,slave?\";\n+\t\tleds_off = <&hifiberry_dacplusadc>,\"hifiberry-dacplusadc,leds_off?\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/hifiberry-dacplusadcpro-overlay.dts b/arch/arm/boot/dts/overlays/hifiberry-dacplusadcpro-overlay.dts\nnew file mode 100644\nindex 000000000000..cafa2ccd7ff7\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/hifiberry-dacplusadcpro-overlay.dts\n@@ -0,0 +1,65 @@\n+// Definitions for HiFiBerry DAC+ADC PRO\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget-path = \"/\";\n+\t\t__overlay__ {\n+\t\t\tdacpro_osc: dacpro_osc {\n+\t\t\t\tcompatible = \"hifiberry,dacpro-clk\";\n+\t\t\t\t#clock-cells = <0>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&i2s>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&i2c1>;\n+\t\t__overlay__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\thb_dac: pcm5122@4d {\n+\t\t\t\t#sound-dai-cells = <0>;\n+\t\t\t\tcompatible = \"ti,pcm5122\";\n+\t\t\t\treg = <0x4d>;\n+\t\t\t\tclocks = <&dacpro_osc>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t\thb_adc: pcm186x@4a {\n+\t\t\t\t#sound-dai-cells = <0>;\n+\t\t\t\tcompatible = \"ti,pcm1863\";\n+\t\t\t\treg = <0x4a>;\n+\t\t\t\tclocks = <&dacpro_osc>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@3 {\n+\t\ttarget = <&sound>;\n+\t\thifiberry_dacplusadcpro: __overlay__ {\n+\t\t\tcompatible = \"hifiberry,hifiberry-dacplusadcpro\";\n+\t\t\taudio-codec = <&hb_dac &hb_adc>;\n+\t\t\ti2s-controller = <&i2s>;\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\t24db_digital_gain =\n+\t\t\t<&hifiberry_dacplusadcpro>,\"hifiberry-dacplusadcpro,24db_digital_gain?\";\n+\t\tslave = <&hifiberry_dacplusadcpro>,\"hifiberry-dacplusadcpro,slave?\";\n+\t\tleds_off = <&hifiberry_dacplusadcpro>,\"hifiberry-dacplusadcpro,leds_off?\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/hifiberry-dacplusdsp-overlay.dts b/arch/arm/boot/dts/overlays/hifiberry-dacplusdsp-overlay.dts\nnew file mode 100644\nindex 000000000000..63432e8b983f\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/hifiberry-dacplusdsp-overlay.dts\n@@ -0,0 +1,34 @@\n+// Definitions for hifiberry DAC+DSP soundcard overlay\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&i2s>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget-path = \"/\";\n+\t\t__overlay__ {\n+\t\t\tdacplusdsp-codec {\n+\t\t\t\t#sound-dai-cells = <0>;\n+\t\t\t\tcompatible = \"hifiberry,dacplusdsp\";\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&sound>;\n+\t\t__overlay__ {\n+\t\t\tcompatible = \"hifiberrydacplusdsp,hifiberrydacplusdsp-soundcard\";\n+\t\t\ti2s-controller = <&i2s>;\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/hifiberry-dacplushd-overlay.dts b/arch/arm/boot/dts/overlays/hifiberry-dacplushd-overlay.dts\nnew file mode 100644\nindex 000000000000..c5583e010339\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/hifiberry-dacplushd-overlay.dts\n@@ -0,0 +1,106 @@\n+// Definitions for HiFiBerry DAC+ HD\n+/dts-v1/;\n+/plugin/;\n+\n+#include <dt-bindings/gpio/gpio.h>\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget-path = \"/\";\n+\t\t__overlay__ {\n+\t\t\tdachd_osc: pll_dachd_osc {\n+\t\t\t\tcompatible = \"hifiberry,dachd-clk\";\n+\t\t\t\t#clock-cells = <0>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&i2s>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&i2c1>;\n+\t\t__overlay__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tpcm1792a@4c {\n+\t\t\t\tcompatible = \"ti,pcm1792a\";\n+\t\t\t\t#sound-dai-cells = <0>;\n+\t\t\t\t#clock-cells = <0>;\n+\t\t\t\tclocks = <&dachd_osc>;\n+\t\t\t\treg = <0x4c>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t\tpll: pll@62 {\n+\t\t\t\tcompatible = \"hifiberry,dachd-clk\";\n+\t\t\t\t#clock-cells = <0>;\n+\t\t\t\treg = <0x62>;\n+\t\t\t\tclocks = <&dachd_osc>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t\tcommon_pll_regs = [\n+\t\t\t\t\t02 53 03 00 07 20 0F 00\n+\t\t\t\t\t10 0D 11 1D 12 0D 13 8C\n+\t\t\t\t\t14 8C 15 8C 16 8C 17 8C\n+\t\t\t\t\t18 2A 1C 00 1D 0F 1F 00\n+\t\t\t\t\t2A 00 2C 00 2F 00 30 00\n+\t\t\t\t\t31 00 32 00 34 00 37 00\n+\t\t\t\t\t38 00 39 00 3A 00 3B 01\n+\t\t\t\t\t3E 00 3F 00 40 00 41 00\n+\t\t\t\t\t5A 00 5B 00 95 00 96 00\n+\t\t\t\t\t97 00 98 00 99 00 9A 00\n+\t\t\t\t\t9B 00 A2 00 A3 00 A4 00\n+\t\t\t\t\tB7 92 ];\n+\t\t\t\t192k_pll_regs = [\n+\t\t\t\t\t1A 0C 1B 35 1E F0 20 09\n+\t\t\t\t\t21 50 2B 02 2D 10 2E 40\n+\t\t\t\t\t33 01 35 22 36 80 3C 22\n+\t\t\t\t\t3D 46 ];\n+\t\t\t\t96k_pll_regs = [\n+\t\t\t\t\t1A 0C 1B 35 1E F0 20 09\n+\t\t\t\t\t21 50 2B 02 2D 10 2E 40\n+\t\t\t\t\t33 01 35 47 36 00 3C 32\n+\t\t\t\t\t3D 46 ];\n+\t\t\t\t48k_pll_regs = [\n+\t\t\t\t\t1A 0C 1B 35 1E F0 20 09\n+\t\t\t\t\t21 50 2B 02 2D 10 2E 40\n+\t\t\t\t\t33 01 35 90 36 00 3C 42\n+\t\t\t\t\t3D 46 ];\n+\t\t\t\t176k4_pll_regs = [\n+\t\t\t\t\t1A 3D 1B 09 1E F3 20 13\n+\t\t\t\t\t21 75 2B 04 2D 11 2E E0\n+\t\t\t\t\t33 02 35 25 36 C0 3C 22\n+\t\t\t\t\t3D 7A ];\n+\t\t\t\t88k2_pll_regs = [\n+\t\t\t\t\t1A 3D 1B 09 1E F3 20 13\n+\t\t\t\t\t21 75 2B 04 2D 11 2E E0\n+\t\t\t\t\t33 01 35 4D 36 80 3C 32\n+\t\t\t\t\t3D 7A ];\n+\t\t\t\t44k1_pll_regs = [\n+\t\t\t\t\t1A 3D 1B 09 1E F3 20 13\n+\t\t\t\t\t21 75 2B 04 2D 11 2E E0\n+\t\t\t\t\t33 01 35 9D 36 00 3C 42\n+\t\t\t\t\t3D 7A ];\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@3 {\n+\t\ttarget = <&sound>;\n+\t\t__overlay__ {\n+\t\t\tcompatible = \"hifiberry,hifiberry-dacplushd\";\n+\t\t\ti2s-controller = <&i2s>;\n+\t\t\tclocks = <&pll 0>;\n+\t\t\treset-gpio = <&gpio 16 GPIO_ACTIVE_LOW>;\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+};\ndiff --git a/arch/arm/boot/dts/overlays/hifiberry-digi-overlay.dts b/arch/arm/boot/dts/overlays/hifiberry-digi-overlay.dts\nnew file mode 100644\nindex 000000000000..a2309a50e8d8\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/hifiberry-digi-overlay.dts\n@@ -0,0 +1,41 @@\n+// Definitions for HiFiBerry Digi\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&i2s>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&i2c1>;\n+\t\t__overlay__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\twm8804@3b {\n+\t\t\t\t#sound-dai-cells = <0>;\n+\t\t\t\tcompatible = \"wlf,wm8804\";\n+\t\t\t\treg = <0x3b>;\n+\t\t\t\tPVDD-supply = <&vdd_3v3_reg>;\n+\t\t\t\tDVDD-supply = <&vdd_3v3_reg>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&sound>;\n+\t\t__overlay__ {\n+\t\t\tcompatible = \"hifiberry,hifiberry-digi\";\n+\t\t\ti2s-controller = <&i2s>;\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/hifiberry-digi-pro-overlay.dts b/arch/arm/boot/dts/overlays/hifiberry-digi-pro-overlay.dts\nnew file mode 100644\nindex 000000000000..83de602e76ba\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/hifiberry-digi-pro-overlay.dts\n@@ -0,0 +1,43 @@\n+// Definitions for HiFiBerry Digi Pro\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&i2s>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&i2c1>;\n+\t\t__overlay__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\twm8804@3b {\n+\t\t\t\t#sound-dai-cells = <0>;\n+\t\t\t\tcompatible = \"wlf,wm8804\";\n+\t\t\t\treg = <0x3b>;\n+\t\t\t\tPVDD-supply = <&vdd_3v3_reg>;\n+\t\t\t\tDVDD-supply = <&vdd_3v3_reg>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&sound>;\n+\t\t__overlay__ {\n+\t\t\tcompatible = \"hifiberry,hifiberry-digi\";\n+\t\t\ti2s-controller = <&i2s>;\n+\t\t\tstatus = \"okay\";\n+\t\t\tclock44-gpio = <&gpio 5 0>;\n+\t\t\tclock48-gpio = <&gpio 6 0>;\n+\t\t};\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/highperi-overlay.dts b/arch/arm/boot/dts/overlays/highperi-overlay.dts\nnew file mode 100644\nindex 000000000000..46cb76c2d34f\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/highperi-overlay.dts\n@@ -0,0 +1,63 @@\n+/*\n+ * highperi.dts\n+ */\n+\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2711\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&soc>;\n+\t\t#address-cells = <2>;\n+\t\t#size-cells = <1>;\n+\n+\t\t__overlay__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <1>;\n+\t\t\tranges = <0x7c000000  0x4 0x7c000000  0x04000000>,\n+\t\t\t\t <0x40000000  0x4 0xc0000000  0x00800000>;\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&scb>;\n+\t\t#address-cells = <2>;\n+\t\t#size-cells = <1>;\n+\n+\t\t__overlay__ {\n+\t\t\t#address-cells = <2>;\n+\t\t\t#size-cells = <2>;\n+\t\t\tranges = <0x0 0x7c000000  0x4 0x7c000000  0x0 0x04000000>,\n+\t\t\t\t <0x0 0x40000000  0x4 0xc0000000  0x0 0x00800000>,\n+\t\t\t\t <0x6 0x00000000  0x6 0x00000000  0x0 0x40000000>;\n+\t\t\tdma-ranges = <0x0 0x00000000  0x0 0x00000000  0x2 0x00000000>;\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&v3dbus>;\n+\t\t#address-cells = <2>;\n+\t\t#size-cells = <1>;\n+\n+\t\t__overlay__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <2>;\n+\t\t\tranges = <0x7c500000  0x4 0x7c500000  0x0 0x03300000>,\n+\t\t\t\t <0x40000000  0x4 0xc0000000  0x0 0x00800000>;\n+\t\t};\n+\t};\n+\n+\tfragment@3 {\n+\t\ttarget = <&emmc2bus>;\n+\t\t#address-cells = <2>;\n+\t\t#size-cells = <1>;\n+\n+\t\t__overlay__ {\n+\t\t\t#address-cells = <2>;\n+\t\t\t#size-cells = <1>;\n+\t\t\tranges = <0x0 0x7e000000  0x4 0x7e000000  0x01800000>;\n+\t\t};\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/hy28a-overlay.dts b/arch/arm/boot/dts/overlays/hy28a-overlay.dts\nnew file mode 100644\nindex 000000000000..5843a5e9c86a\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/hy28a-overlay.dts\n@@ -0,0 +1,93 @@\n+/*\n+ * Device Tree overlay for HY28A display\n+ *\n+ */\n+\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&spi0>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&spidev0>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&spidev1>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\tfragment@3 {\n+\t\ttarget = <&gpio>;\n+\t\t__overlay__ {\n+\t\t\thy28a_pins: hy28a_pins {\n+\t\t\t\tbrcm,pins = <17 25 18>;\n+\t\t\t\tbrcm,function = <0 1 1>; /* in out out */\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@4 {\n+\t\ttarget = <&spi0>;\n+\t\t__overlay__ {\n+\t\t\t/* needed to avoid dtc warning */\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\thy28a: hy28a@0{\n+\t\t\t\tcompatible = \"ilitek,ili9320\";\n+\t\t\t\treg = <0>;\n+\t\t\t\tpinctrl-names = \"default\";\n+\t\t\t\tpinctrl-0 = <&hy28a_pins>;\n+\n+\t\t\t\tspi-max-frequency = <32000000>;\n+\t\t\t\tspi-cpol;\n+\t\t\t\tspi-cpha;\n+\t\t\t\trotate = <270>;\n+\t\t\t\tbgr;\n+\t\t\t\tfps = <50>;\n+\t\t\t\tbuswidth = <8>;\n+\t\t\t\tstartbyte = <0x70>;\n+\t\t\t\treset-gpios = <&gpio 25 1>;\n+\t\t\t\tled-gpios = <&gpio 18 1>;\n+\t\t\t\tdebug = <0>;\n+\t\t\t};\n+\n+\t\t\thy28a_ts: hy28a-ts@1 {\n+\t\t\t\tcompatible = \"ti,ads7846\";\n+\t\t\t\treg = <1>;\n+\n+\t\t\t\tspi-max-frequency = <2000000>;\n+\t\t\t\tinterrupts = <17 2>; /* high-to-low edge triggered */\n+\t\t\t\tinterrupt-parent = <&gpio>;\n+\t\t\t\tpendown-gpio = <&gpio 17 0>;\n+\t\t\t\tti,x-plate-ohms = /bits/ 16 <100>;\n+\t\t\t\tti,pressure-max = /bits/ 16 <255>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\t__overrides__ {\n+\t\tspeed =\t\t<&hy28a>,\"spi-max-frequency:0\";\n+\t\trotate =\t<&hy28a>,\"rotate:0\";\n+\t\tfps =\t\t<&hy28a>,\"fps:0\";\n+\t\tdebug =\t\t<&hy28a>,\"debug:0\";\n+\t\txohms =\t\t<&hy28a_ts>,\"ti,x-plate-ohms;0\";\n+\t\tresetgpio =\t<&hy28a>,\"reset-gpios:4\",\n+\t\t\t\t<&hy28a_pins>, \"brcm,pins:4\";\n+\t\tledgpio =\t<&hy28a>,\"led-gpios:4\",\n+\t\t\t\t<&hy28a_pins>, \"brcm,pins:8\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/hy28b-2017-overlay.dts b/arch/arm/boot/dts/overlays/hy28b-2017-overlay.dts\nnew file mode 100644\nindex 000000000000..95bfb1eadc20\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/hy28b-2017-overlay.dts\n@@ -0,0 +1,152 @@\n+/*\n+ * Device Tree overlay for HY28b display shield by Texy.\n+ * Modified for 2017 version with ILI9325 D chip\n+ */\n+\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&spi0>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&spidev0>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&spidev1>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\tfragment@3 {\n+\t\ttarget = <&gpio>;\n+\t\t__overlay__ {\n+\t\t\thy28b_pins: hy28b_pins {\n+\t\t\t\tbrcm,pins = <17 25 18>;\n+\t\t\t\tbrcm,function = <0 1 1>; /* in out out */\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@4 {\n+\t\ttarget = <&spi0>;\n+\t\t__overlay__ {\n+\t\t\t/* needed to avoid dtc warning */\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\thy28b: hy28b@0{\n+\t\t\t\tcompatible = \"ilitek,ili9325\";\n+\t\t\t\treg = <0>;\n+\t\t\t\tpinctrl-names = \"default\";\n+\t\t\t\tpinctrl-0 = <&hy28b_pins>;\n+\n+\t\t\t\tspi-max-frequency = <48000000>;\n+\t\t\t\tspi-cpol;\n+\t\t\t\tspi-cpha;\n+\t\t\t\trotate = <270>;\n+\t\t\t\tbgr;\n+\t\t\t\tfps = <50>;\n+\t\t\t\tbuswidth = <8>;\n+\t\t\t\tstartbyte = <0x70>;\n+\t\t\t\treset-gpios = <&gpio 25 1>;\n+\t\t\t\tled-gpios = <&gpio 18 1>;\n+\n+\t\t\t\tinit = <0x10000e5 0x78F0\n+\t\t\t\t\t0x1000001 0x0100\n+\t\t\t\t\t0x1000002 0x0700\n+\t\t\t\t        0x1000003 0x1030\n+\t\t\t\t\t0x1000004 0x0000\n+\t\t\t\t\t0x1000008 0x0207\n+\t\t\t\t\t0x1000009 0x0000\n+\t\t\t\t        0x100000a 0x0000\n+\t\t\t\t\t0x100000c 0x0000\n+\t\t\t\t\t0x100000d 0x0000\n+\t\t\t\t\t0x100000f 0x0000\n+\t\t\t\t        0x1000010 0x0000\n+\t\t\t\t\t0x1000011 0x0007\n+\t\t\t\t\t0x1000012 0x0000\n+\t\t\t\t\t0x1000013 0x0000\n+\t\t\t\t\t0x1000007 0x0001\n+\t\t\t\t        0x2000032\n+\t\t\t\t        0x2000032\n+\t\t\t\t        0x2000032\n+\t\t\t\t        0x2000032\n+\t\t\t\t\t0x1000010 0x1090\n+\t\t\t\t\t0x1000011 0x0227\n+\t\t\t\t        0x2000032\n+\t\t\t\t\t0x1000012 0x001f\n+\t\t\t\t        0x2000032\n+\t\t\t\t        0x1000013 0x1500\n+\t\t\t\t\t0x1000029 0x0027\n+\t\t\t\t\t0x100002b 0x000d\n+\t\t\t\t        0x2000032\n+\t\t\t\t        0x1000020 0x0000\n+\t\t\t\t\t0x1000021 0x0000\n+\t\t\t\t        0x2000032\n+\t\t\t\t\t0x1000030 0x0000\n+\t\t\t\t\t0x1000031 0x0707\n+\t\t\t\t\t0x1000032 0x0307\n+\t\t\t\t\t0x1000035 0x0200\n+\t\t\t\t\t0x1000036 0x0008\n+\t\t\t\t\t0x1000037 0x0004\n+\t\t\t\t\t0x1000038 0x0000\n+\t\t\t\t\t0x1000039 0x0707\n+\t\t\t\t\t0x100003c 0x0002\n+\t\t\t\t\t0x100003d 0x1d04\n+\t\t\t\t\t0x1000050 0x0000\n+\t\t\t\t        0x1000051 0x00ef\n+\t\t\t\t\t0x1000052 0x0000\n+\t\t\t\t\t0x1000053 0x013f\n+\t\t\t\t\t0x1000060 0xa700\n+\t\t\t\t        0x1000061 0x0001\n+\t\t\t\t\t0x100006a 0x0000\n+\t\t\t\t\t0x1000080 0x0000\n+\t\t\t\t\t0x1000081 0x0000\n+\t\t\t\t        0x1000082 0x0000\n+\t\t\t\t\t0x1000083 0x0000\n+\t\t\t\t\t0x1000084 0x0000\n+\t\t\t\t\t0x1000085 0x0000\n+\t\t\t\t        0x1000090 0x0010\n+\t\t\t\t\t0x1000092 0x0600\n+\t\t\t\t\t0x1000007 0x0133>;\n+\t\t\t\tdebug = <0>;\n+\t\t\t};\n+\n+\t\t\thy28b_ts: hy28b-ts@1 {\n+\t\t\t\tcompatible = \"ti,ads7846\";\n+\t\t\t\treg = <1>;\n+\n+\t\t\t\tspi-max-frequency = <2000000>;\n+\t\t\t\tinterrupts = <17 2>; /* high-to-low edge triggered */\n+\t\t\t\tinterrupt-parent = <&gpio>;\n+\t\t\t\tpendown-gpio = <&gpio 17 0>;\n+\t\t\t\tti,x-plate-ohms = /bits/ 16 <100>;\n+\t\t\t\tti,pressure-max = /bits/ 16 <255>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\t__overrides__ {\n+\t\tspeed = \t<&hy28b>,\"spi-max-frequency:0\";\n+\t\trotate = \t<&hy28b>,\"rotate:0\";\n+\t\tfps = \t\t<&hy28b>,\"fps:0\";\n+\t\tdebug = \t<&hy28b>,\"debug:0\";\n+\t\txohms =\t\t<&hy28b_ts>,\"ti,x-plate-ohms;0\";\n+\t\tresetgpio =\t<&hy28b>,\"reset-gpios:4\",\n+\t\t\t\t<&hy28b_pins>, \"brcm,pins:4\";\n+\t\tledgpio =\t<&hy28b>,\"led-gpios:4\",\n+\t\t\t\t<&hy28b_pins>, \"brcm,pins:8\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/hy28b-overlay.dts b/arch/arm/boot/dts/overlays/hy28b-overlay.dts\nnew file mode 100644\nindex 000000000000..9edd0848d555\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/hy28b-overlay.dts\n@@ -0,0 +1,148 @@\n+/*\n+ * Device Tree overlay for HY28b display shield by Texy\n+ *\n+ */\n+\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&spi0>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&spidev0>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&spidev1>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\tfragment@3 {\n+\t\ttarget = <&gpio>;\n+\t\t__overlay__ {\n+\t\t\thy28b_pins: hy28b_pins {\n+\t\t\t\tbrcm,pins = <17 25 18>;\n+\t\t\t\tbrcm,function = <0 1 1>; /* in out out */\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@4 {\n+\t\ttarget = <&spi0>;\n+\t\t__overlay__ {\n+\t\t\t/* needed to avoid dtc warning */\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\thy28b: hy28b@0{\n+\t\t\t\tcompatible = \"ilitek,ili9325\";\n+\t\t\t\treg = <0>;\n+\t\t\t\tpinctrl-names = \"default\";\n+\t\t\t\tpinctrl-0 = <&hy28b_pins>;\n+\n+\t\t\t\tspi-max-frequency = <48000000>;\n+\t\t\t\tspi-cpol;\n+\t\t\t\tspi-cpha;\n+\t\t\t\trotate = <270>;\n+\t\t\t\tbgr;\n+\t\t\t\tfps = <50>;\n+\t\t\t\tbuswidth = <8>;\n+\t\t\t\tstartbyte = <0x70>;\n+\t\t\t\treset-gpios = <&gpio 25 1>;\n+\t\t\t\tled-gpios = <&gpio 18 1>;\n+\n+\t\t\t\tgamma = \"04 1F 4 7 7 0 7 7 6 0\\n0F 00 1 7 4 0 0 0 6 7\";\n+\n+\t\t\t\tinit = <0x10000e7 0x0010\n+\t\t\t\t\t0x1000000 0x0001\n+\t\t\t\t\t0x1000001 0x0100\n+\t\t\t\t\t0x1000002 0x0700\n+\t\t\t\t        0x1000003 0x1030\n+\t\t\t\t\t0x1000004 0x0000\n+\t\t\t\t\t0x1000008 0x0207\n+\t\t\t\t\t0x1000009 0x0000\n+\t\t\t\t        0x100000a 0x0000\n+\t\t\t\t\t0x100000c 0x0001\n+\t\t\t\t\t0x100000d 0x0000\n+\t\t\t\t\t0x100000f 0x0000\n+\t\t\t\t        0x1000010 0x0000\n+\t\t\t\t\t0x1000011 0x0007\n+\t\t\t\t\t0x1000012 0x0000\n+\t\t\t\t\t0x1000013 0x0000\n+\t\t\t\t        0x2000032\n+\t\t\t\t\t0x1000010 0x1590\n+\t\t\t\t\t0x1000011 0x0227\n+\t\t\t\t        0x2000032\n+\t\t\t\t\t0x1000012 0x009c\n+\t\t\t\t        0x2000032\n+\t\t\t\t        0x1000013 0x1900\n+\t\t\t\t\t0x1000029 0x0023\n+\t\t\t\t\t0x100002b 0x000e\n+\t\t\t\t        0x2000032\n+\t\t\t\t        0x1000020 0x0000\n+\t\t\t\t\t0x1000021 0x0000\n+\t\t\t\t        0x2000032\n+\t\t\t\t\t0x1000050 0x0000\n+\t\t\t\t        0x1000051 0x00ef\n+\t\t\t\t\t0x1000052 0x0000\n+\t\t\t\t\t0x1000053 0x013f\n+\t\t\t\t\t0x1000060 0xa700\n+\t\t\t\t        0x1000061 0x0001\n+\t\t\t\t\t0x100006a 0x0000\n+\t\t\t\t\t0x1000080 0x0000\n+\t\t\t\t\t0x1000081 0x0000\n+\t\t\t\t        0x1000082 0x0000\n+\t\t\t\t\t0x1000083 0x0000\n+\t\t\t\t\t0x1000084 0x0000\n+\t\t\t\t\t0x1000085 0x0000\n+\t\t\t\t        0x1000090 0x0010\n+\t\t\t\t\t0x1000092 0x0000\n+\t\t\t\t\t0x1000093 0x0003\n+\t\t\t\t\t0x1000095 0x0110\n+\t\t\t\t        0x1000097 0x0000\n+\t\t\t\t\t0x1000098 0x0000\n+\t\t\t\t\t0x1000007 0x0133\n+\t\t\t\t\t0x1000020 0x0000\n+\t\t\t\t        0x1000021 0x0000\n+\t\t\t\t        0x2000064>;\n+\t\t\t\tdebug = <0>;\n+\t\t\t};\n+\n+\t\t\thy28b_ts: hy28b-ts@1 {\n+\t\t\t\tcompatible = \"ti,ads7846\";\n+\t\t\t\treg = <1>;\n+\n+\t\t\t\tspi-max-frequency = <2000000>;\n+\t\t\t\tinterrupts = <17 2>; /* high-to-low edge triggered */\n+\t\t\t\tinterrupt-parent = <&gpio>;\n+\t\t\t\tpendown-gpio = <&gpio 17 0>;\n+\t\t\t\tti,x-plate-ohms = /bits/ 16 <100>;\n+\t\t\t\tti,pressure-max = /bits/ 16 <255>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\t__overrides__ {\n+\t\tspeed = \t<&hy28b>,\"spi-max-frequency:0\";\n+\t\trotate = \t<&hy28b>,\"rotate:0\";\n+\t\tfps = \t\t<&hy28b>,\"fps:0\";\n+\t\tdebug = \t<&hy28b>,\"debug:0\";\n+\t\txohms =\t\t<&hy28b_ts>,\"ti,x-plate-ohms;0\";\n+\t\tresetgpio =\t<&hy28b>,\"reset-gpios:4\",\n+\t\t\t\t<&hy28b_pins>, \"brcm,pins:4\";\n+\t\tledgpio =\t<&hy28b>,\"led-gpios:4\",\n+\t\t\t\t<&hy28b_pins>, \"brcm,pins:8\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/i-sabre-q2m-overlay.dts b/arch/arm/boot/dts/overlays/i-sabre-q2m-overlay.dts\nnew file mode 100644\nindex 000000000000..0c4cff354674\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/i-sabre-q2m-overlay.dts\n@@ -0,0 +1,39 @@\n+// Definitions for I-Sabre Q2M\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&sound>;\n+\t\tfrag0: __overlay__ {\n+\t\t\tcompatible = \"audiophonics,i-sabre-q2m\";\n+\t\t\ti2s-controller = <&i2s>;\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&i2s>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&i2c1>;\n+\t\t__overlay__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\ti-sabre-codec@48 {\n+\t\t\t\t#sound-dai-cells = <0>;\n+\t\t\t\tcompatible = \"audiophonics,i-sabre-codec\";\n+\t\t\t\treg = <0x48>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/i2c-bcm2708-overlay.dts b/arch/arm/boot/dts/overlays/i2c-bcm2708-overlay.dts\nnew file mode 100644\nindex 000000000000..8204b6b3aef8\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/i2c-bcm2708-overlay.dts\n@@ -0,0 +1,13 @@\n+/dts-v1/;\n+/plugin/;\n+\n+/{\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&i2c_arm>;\n+\t\t__overlay__ {\n+\t\t\tcompatible = \"brcm,bcm2708-i2c\";\n+\t\t};\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/i2c-gpio-overlay.dts b/arch/arm/boot/dts/overlays/i2c-gpio-overlay.dts\nnew file mode 100644\nindex 000000000000..63231b5d7c0c\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/i2c-gpio-overlay.dts\n@@ -0,0 +1,47 @@\n+// Overlay for i2c_gpio bitbanging host bus.\n+/dts-v1/;\n+/plugin/;\n+\n+#include <dt-bindings/gpio/gpio.h>\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget-path = \"/\";\n+\n+\t\t__overlay__ {\n+\t\t\ti2c_gpio: i2c@0 {\n+\t\t\t\treg = <0xffffffff>;\n+\t\t\t\tcompatible = \"i2c-gpio\";\n+\t\t\t\tgpios = <&gpio 23 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN) /* sda */\n+\t\t\t\t\t &gpio 24 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN) /* scl */\n+\t\t\t\t\t>;\n+\t\t\t\ti2c-gpio,delay-us = <2>;        /* ~100 kHz */\n+\t\t\t\t#address-cells = <1>;\n+\t\t\t\t#size-cells = <0>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget-path = \"/aliases\";\n+\t\t__overlay__ {\n+\t\t\ti2c_gpio = \"/i2c@0\";\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget-path = \"/__symbols__\";\n+\t\t__overlay__ {\n+\t\t\ti2c_gpio = \"/i2c@0\";\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\ti2c_gpio_sda = <&i2c_gpio>,\"gpios:4\";\n+\t\ti2c_gpio_scl = <&i2c_gpio>,\"gpios:16\";\n+\t\ti2c_gpio_delay_us = <&i2c_gpio>,\"i2c-gpio,delay-us:0\";\n+\t\tbus = <&i2c_gpio>, \"reg:0\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/i2c-mux-overlay.dts b/arch/arm/boot/dts/overlays/i2c-mux-overlay.dts\nnew file mode 100644\nindex 000000000000..112aed91ecb2\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/i2c-mux-overlay.dts\n@@ -0,0 +1,139 @@\n+// Umbrella I2C Mux overlay\n+\n+/dts-v1/;\n+/plugin/;\n+\n+/{\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&i2c_arm>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tpca9542: mux@70 {\n+\t\t\t\tcompatible = \"nxp,pca9542\";\n+\t\t\t\treg = <0x70>;\n+\t\t\t\t#address-cells = <1>;\n+\t\t\t\t#size-cells = <0>;\n+\n+\t\t\t\ti2c@0 {\n+\t\t\t\t\t#address-cells = <1>;\n+\t\t\t\t\t#size-cells = <0>;\n+\t\t\t\t\treg = <0>;\n+\t\t\t\t};\n+\t\t\t\ti2c@1 {\n+\t\t\t\t\t#address-cells = <1>;\n+\t\t\t\t\t#size-cells = <0>;\n+\t\t\t\t\treg = <1>;\n+\t\t\t\t};\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&i2c_arm>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tpca9545: mux@70 {\n+\t\t\t\tcompatible = \"nxp,pca9545\";\n+\t\t\t\treg = <0x70>;\n+\t\t\t\t#address-cells = <1>;\n+\t\t\t\t#size-cells = <0>;\n+\n+\t\t\t\ti2c@0 {\n+\t\t\t\t\t#address-cells = <1>;\n+\t\t\t\t\t#size-cells = <0>;\n+\t\t\t\t\treg = <0>;\n+\t\t\t\t};\n+\t\t\t\ti2c@1 {\n+\t\t\t\t\t#address-cells = <1>;\n+\t\t\t\t\t#size-cells = <0>;\n+\t\t\t\t\treg = <1>;\n+\t\t\t\t};\n+\t\t\t\ti2c@2 {\n+\t\t\t\t\t#address-cells = <1>;\n+\t\t\t\t\t#size-cells = <0>;\n+\t\t\t\t\treg = <2>;\n+\t\t\t\t};\n+\t\t\t\ti2c@3 {\n+\t\t\t\t\t#address-cells = <1>;\n+\t\t\t\t\t#size-cells = <0>;\n+\t\t\t\t\treg = <3>;\n+\t\t\t\t};\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&i2c_arm>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tpca9548: mux@70 {\n+\t\t\t\tcompatible = \"nxp,pca9548\";\n+\t\t\t\treg = <0x70>;\n+\t\t\t\t#address-cells = <1>;\n+\t\t\t\t#size-cells = <0>;\n+\n+\t\t\t\ti2c@0 {\n+\t\t\t\t\t#address-cells = <1>;\n+\t\t\t\t\t#size-cells = <0>;\n+\t\t\t\t\treg = <0>;\n+\t\t\t\t};\n+\t\t\t\ti2c@1 {\n+\t\t\t\t\t#address-cells = <1>;\n+\t\t\t\t\t#size-cells = <0>;\n+\t\t\t\t\treg = <1>;\n+\t\t\t\t};\n+\t\t\t\ti2c@2 {\n+\t\t\t\t\t#address-cells = <1>;\n+\t\t\t\t\t#size-cells = <0>;\n+\t\t\t\t\treg = <2>;\n+\t\t\t\t};\n+\t\t\t\ti2c@3 {\n+\t\t\t\t\t#address-cells = <1>;\n+\t\t\t\t\t#size-cells = <0>;\n+\t\t\t\t\treg = <3>;\n+\t\t\t\t};\n+\t\t\t\ti2c@4 {\n+\t\t\t\t\t#address-cells = <1>;\n+\t\t\t\t\t#size-cells = <0>;\n+\t\t\t\t\treg = <4>;\n+\t\t\t\t};\n+\t\t\t\ti2c@5 {\n+\t\t\t\t\t#address-cells = <1>;\n+\t\t\t\t\t#size-cells = <0>;\n+\t\t\t\t\treg = <5>;\n+\t\t\t\t};\n+\t\t\t\ti2c@6 {\n+\t\t\t\t\t#address-cells = <1>;\n+\t\t\t\t\t#size-cells = <0>;\n+\t\t\t\t\treg = <6>;\n+\t\t\t\t};\n+\t\t\t\ti2c@7 {\n+\t\t\t\t\t#address-cells = <1>;\n+\t\t\t\t\t#size-cells = <0>;\n+\t\t\t\t\treg = <7>;\n+\t\t\t\t};\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\tpca9542 = <0>, \"+0\";\n+\t\tpca9545 = <0>, \"+1\";\n+\t\tpca9548 = <0>, \"+2\";\n+\n+\t\taddr =  <&pca9542>,\"reg:0\",\n+\t\t\t<&pca9545>,\"reg:0\",\n+\t\t\t<&pca9548>,\"reg:0\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/i2c-pwm-pca9685a-overlay.dts b/arch/arm/boot/dts/overlays/i2c-pwm-pca9685a-overlay.dts\nnew file mode 100644\nindex 000000000000..9bb16465a50e\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/i2c-pwm-pca9685a-overlay.dts\n@@ -0,0 +1,26 @@\n+// Definitions for NXP PCA9685A I2C PWM controller on ARM I2C bus.\n+/dts-v1/;\n+/plugin/;\n+\n+/{\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&i2c_arm>;\n+\t\t__overlay__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tpca: pca@40 {\n+\t\t\t\tcompatible = \"nxp,pca9685-pwm\";\n+\t\t\t\t#pwm-cells = <2>;\n+\t\t\t\treg = <0x40>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\t__overrides__ {\n+\t\taddr = <&pca>,\"reg:0\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/i2c-rtc-gpio-overlay.dts b/arch/arm/boot/dts/overlays/i2c-rtc-gpio-overlay.dts\nnew file mode 100644\nindex 000000000000..227e3c0fa1cd\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/i2c-rtc-gpio-overlay.dts\n@@ -0,0 +1,266 @@\n+// Definitions for several I2C based Real Time Clocks\n+// Available through i2c-gpio\n+/dts-v1/;\n+/plugin/;\n+\n+#include <dt-bindings/gpio/gpio.h>\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget-path = \"/\";\n+\t\t__overlay__ {\n+\t\t\ti2c_gpio: i2c-gpio-rtc@0 {\n+\t\t\t\tcompatible = \"i2c-gpio\";\n+\t\t\t\tgpios = <&gpio 23 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN) /* sda */\n+\t\t\t\t\t &gpio 24 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN) /* scl */\n+\t\t\t\t\t>;\n+\t\t\t\ti2c-gpio,delay-us = <2>;        /* ~100 kHz */\n+\t\t\t\t#address-cells = <1>;\n+\t\t\t\t#size-cells = <0>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&i2c_gpio>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tabx80x: abx80x@69 {\n+\t\t\t\tcompatible = \"abracon,abx80x\";\n+\t\t\t\treg = <0x69>;\n+\t\t\t\tabracon,tc-diode = \"standard\";\n+\t\t\t\tabracon,tc-resistor = <0>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&i2c_gpio>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tds1307: ds1307@68 {\n+\t\t\t\tcompatible = \"dallas,ds1307\";\n+\t\t\t\treg = <0x68>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@3 {\n+\t\ttarget = <&i2c_gpio>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tds1339: ds1339@68 {\n+\t\t\t\tcompatible = \"dallas,ds1339\";\n+\t\t\t\ttrickle-resistor-ohms = <0>;\n+\t\t\t\treg = <0x68>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@4 {\n+\t\ttarget = <&i2c_gpio>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tds3231: ds3231@68 {\n+\t\t\t\tcompatible = \"maxim,ds3231\";\n+\t\t\t\treg = <0x68>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@5 {\n+\t\ttarget = <&i2c_gpio>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tmcp7940x: mcp7940x@6f {\n+\t\t\t\tcompatible = \"microchip,mcp7940x\";\n+\t\t\t\treg = <0x6f>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@6 {\n+\t\ttarget = <&i2c_gpio>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tmcp7941x: mcp7941x@6f {\n+\t\t\t\tcompatible = \"microchip,mcp7941x\";\n+\t\t\t\treg = <0x6f>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@7 {\n+\t\ttarget = <&i2c_gpio>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tpcf2127@51 {\n+\t\t\t\tcompatible = \"nxp,pcf2127\";\n+\t\t\t\treg = <0x51>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@8 {\n+\t\ttarget = <&i2c_gpio>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tpcf8523: pcf8523@68 {\n+\t\t\t\tcompatible = \"nxp,pcf8523\";\n+\t\t\t\treg = <0x68>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@9 {\n+\t\ttarget = <&i2c_gpio>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tpcf8563: pcf8563@51 {\n+\t\t\t\tcompatible = \"nxp,pcf8563\";\n+\t\t\t\treg = <0x51>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@10 {\n+\t\ttarget = <&i2c_arm>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tm41t62: m41t62@68 {\n+\t\t\t\tcompatible = \"st,m41t62\";\n+\t\t\t\treg = <0x68>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@11 {\n+\t\ttarget = <&i2c_gpio>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\trv3028: rv3028@52 {\n+\t\t\t\tcompatible = \"microcrystal,rv3028\";\n+\t\t\t\treg = <0x52>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@12 {\n+\t\ttarget = <&i2c_gpio>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tpcf2129@51 {\n+\t\t\t\tcompatible = \"nxp,pcf2129\";\n+\t\t\t\treg = <0x51>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@13 {\n+\t\ttarget = <&i2c_gpio>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\trv1805: rv1805@69 {\n+\t\t\t\tcompatible = \"microcrystal,rv1805\";\n+\t\t\t\treg = <0x69>;\n+\t\t\t\tabracon,tc-diode = \"standard\";\n+\t\t\t\tabracon,tc-resistor = <0>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\tabx80x = <0>,\"+1\";\n+\t\tds1307 = <0>,\"+2\";\n+\t\tds1339 = <0>,\"+3\";\n+\t\tds3231 = <0>,\"+4\";\n+\t\tmcp7940x = <0>,\"+5\";\n+\t\tmcp7941x = <0>,\"+6\";\n+\t\tpcf2127 = <0>,\"+7\";\n+\t\tpcf8523 = <0>,\"+8\";\n+\t\tpcf8563 = <0>,\"+9\";\n+\t\tm41t62 = <0>,\"+10\";\n+\t\trv3028 = <0>,\"+11\";\n+\t\tpcf2129 = <0>,\"+12\";\n+\t\trv1805 = <0>,\"+13\";\n+\n+\t\taddr = <&abx80x>, \"reg:0\",\n+\t\t       <&ds1307>, \"reg:0\",\n+\t\t       <&ds1339>, \"reg:0\",\n+\t\t       <&ds3231>, \"reg:0\",\n+\t\t       <&mcp7940x>, \"reg:0\",\n+\t\t       <&mcp7941x>, \"reg:0\",\n+\t\t       <&pcf8523>, \"reg:0\",\n+\t\t       <&pcf8563>, \"reg:0\",\n+\t\t       <&m41t62>, \"reg:0\",\n+\t\t       <&rv1805>, \"reg:0\";\n+\t\ttrickle-diode-type = <&abx80x>,\"abracon,tc-diode\",\n+\t\t\t\t     <&rv1805>,\"abracon,tc-diode\";\n+\t\ttrickle-resistor-ohms = <&ds1339>,\"trickle-resistor-ohms:0\",\n+\t\t\t\t\t<&abx80x>,\"abracon,tc-resistor:0\",\n+\t\t\t\t\t<&rv3028>,\"trickle-resistor-ohms:0\",\n+\t\t\t\t\t<&rv1805>,\"abracon,tc-resistor:0\";\n+\t\tbackup-switchover-mode = <&rv3028>,\"backup-switchover-mode:0\";\n+\t\twakeup-source = <&ds1339>,\"wakeup-source?\",\n+\t\t\t\t<&ds3231>,\"wakeup-source?\",\n+\t\t\t\t<&mcp7940x>,\"wakeup-source?\",\n+\t\t\t\t<&mcp7941x>,\"wakeup-source?\";\n+\t\ti2c_gpio_sda = <&i2c_gpio>,\"gpios:4\";\n+\t\ti2c_gpio_scl = <&i2c_gpio>,\"gpios:16\";\n+\t\ti2c_gpio_delay_us = <&i2c_gpio>,\"i2c-gpio,delay-us:0\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/i2c-rtc-overlay.dts b/arch/arm/boot/dts/overlays/i2c-rtc-overlay.dts\nnew file mode 100644\nindex 000000000000..735ca303e4fa\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/i2c-rtc-overlay.dts\n@@ -0,0 +1,278 @@\n+// Definitions for several I2C based Real Time Clocks\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&i2c_arm>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tabx80x: abx80x@69 {\n+\t\t\t\tcompatible = \"abracon,abx80x\";\n+\t\t\t\treg = <0x69>;\n+\t\t\t\tabracon,tc-diode = \"standard\";\n+\t\t\t\tabracon,tc-resistor = <0>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&i2c_arm>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tds1307: ds1307@68 {\n+\t\t\t\tcompatible = \"dallas,ds1307\";\n+\t\t\t\treg = <0x68>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&i2c_arm>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tds1339: ds1339@68 {\n+\t\t\t\tcompatible = \"dallas,ds1339\";\n+\t\t\t\ttrickle-resistor-ohms = <0>;\n+\t\t\t\treg = <0x68>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@3 {\n+\t\ttarget = <&i2c_arm>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tds3231: ds3231@68 {\n+\t\t\t\tcompatible = \"maxim,ds3231\";\n+\t\t\t\treg = <0x68>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@4 {\n+\t\ttarget = <&i2c_arm>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tmcp7940x: mcp7940x@6f {\n+\t\t\t\tcompatible = \"microchip,mcp7940x\";\n+\t\t\t\treg = <0x6f>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@5 {\n+\t\ttarget = <&i2c_arm>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tmcp7941x: mcp7941x@6f {\n+\t\t\t\tcompatible = \"microchip,mcp7941x\";\n+\t\t\t\treg = <0x6f>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@6 {\n+\t\ttarget = <&i2c_arm>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tpcf2127@51 {\n+\t\t\t\tcompatible = \"nxp,pcf2127\";\n+\t\t\t\treg = <0x51>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@7 {\n+\t\ttarget = <&i2c_arm>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tpcf8523: pcf8523@68 {\n+\t\t\t\tcompatible = \"nxp,pcf8523\";\n+\t\t\t\treg = <0x68>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@8 {\n+\t\ttarget = <&i2c_arm>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tpcf8563: pcf8563@51 {\n+\t\t\t\tcompatible = \"nxp,pcf8563\";\n+\t\t\t\treg = <0x51>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@9 {\n+\t\ttarget = <&i2c_arm>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tm41t62: m41t62@68 {\n+\t\t\t\tcompatible = \"st,m41t62\";\n+\t\t\t\treg = <0x68>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@10 {\n+\t\ttarget = <&i2c_arm>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\trv3028: rv3028@52 {\n+\t\t\t\tcompatible = \"microcrystal,rv3028\";\n+\t\t\t\treg = <0x52>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@11 {\n+\t\ttarget = <&i2c_arm>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tpcf2129@51 {\n+\t\t\t\tcompatible = \"nxp,pcf2129\";\n+\t\t\t\treg = <0x51>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@12 {\n+\t\ttarget = <&i2c_arm>;\n+\t       __dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tpcf85363@51 {\n+\t\t\t\tcompatible = \"nxp,pcf85363\";\n+\t\t\t\treg = <0x51>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@13 {\n+\t\ttarget = <&i2c_arm>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\trv1805: rv1805@69 {\n+\t\t\t\tcompatible = \"microcrystal,rv1805\";\n+\t\t\t\treg = <0x69>;\n+\t\t\t\tabracon,tc-diode = \"standard\";\n+\t\t\t\tabracon,tc-resistor = <0>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@14 {\n+\t\ttarget = <&i2c_arm>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tsd3078: sd3078@32 {\n+\t\t\t\tcompatible = \"whwave,sd3078\";\n+\t\t\t\treg = <0x32>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\tabx80x = <0>,\"+0\";\n+\t\tds1307 = <0>,\"+1\";\n+\t\tds1339 = <0>,\"+2\";\n+\t\tds3231 = <0>,\"+3\";\n+\t\tmcp7940x = <0>,\"+4\";\n+\t\tmcp7941x = <0>,\"+5\";\n+\t\tpcf2127 = <0>,\"+6\";\n+\t\tpcf8523 = <0>,\"+7\";\n+\t\tpcf8563 = <0>,\"+8\";\n+\t\tm41t62 = <0>,\"+9\";\n+\t\trv3028 = <0>,\"+10\";\n+\t\tpcf2129 = <0>,\"+11\";\n+\t\tpcf85363 = <0>,\"+12\";\n+\t\trv1805 = <0>,\"+13\";\n+\t\tsd3078 = <0>,\"+14\";\n+\n+\t\taddr = <&abx80x>, \"reg:0\",\n+\t\t       <&ds1307>, \"reg:0\",\n+\t\t       <&ds1339>, \"reg:0\",\n+\t\t       <&ds3231>, \"reg:0\",\n+\t\t       <&mcp7940x>, \"reg:0\",\n+\t\t       <&mcp7941x>, \"reg:0\",\n+\t\t       <&pcf8523>, \"reg:0\",\n+\t\t       <&pcf8563>, \"reg:0\",\n+\t\t       <&m41t62>, \"reg:0\",\n+\t\t       <&rv1805>, \"reg:0\";\n+\t\ttrickle-diode-type = <&abx80x>,\"abracon,tc-diode\",\n+\t\t\t\t     <&rv1805>,\"abracon,tc-diode\";\n+\t\ttrickle-resistor-ohms = <&ds1339>,\"trickle-resistor-ohms:0\",\n+\t\t\t\t\t<&abx80x>,\"abracon,tc-resistor:0\",\n+\t\t\t\t\t<&rv3028>,\"trickle-resistor-ohms:0\",\n+\t\t\t\t\t<&rv1805>,\"abracon,tc-resistor:0\";\n+\t\tbackup-switchover-mode = <&rv3028>,\"backup-switchover-mode:0\";\n+\t\twakeup-source = <&ds1339>,\"wakeup-source?\",\n+\t\t\t\t<&ds3231>,\"wakeup-source?\",\n+\t\t\t\t<&mcp7940x>,\"wakeup-source?\",\n+\t\t\t\t<&mcp7941x>,\"wakeup-source?\",\n+\t\t\t\t<&m41t62>,\"wakeup-source?\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/i2c-sensor-overlay.dts b/arch/arm/boot/dts/overlays/i2c-sensor-overlay.dts\nnew file mode 100644\nindex 000000000000..ce97837b0db5\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/i2c-sensor-overlay.dts\n@@ -0,0 +1,271 @@\n+// Definitions for I2C based sensors using the Industrial IO or HWMON interface.\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&i2c_arm>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tbme280: bme280@76 {\n+\t\t\t\tcompatible = \"bosch,bme280\";\n+\t\t\t\treg = <0x76>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&i2c_arm>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tbmp085: bmp085@77 {\n+\t\t\t\tcompatible = \"bosch,bmp085\";\n+\t\t\t\treg = <0x77>;\n+\t\t\t\tdefault-oversampling = <3>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&i2c_arm>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tbmp180: bmp180@77 {\n+\t\t\t\tcompatible = \"bosch,bmp180\";\n+\t\t\t\treg = <0x77>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@3 {\n+\t\ttarget = <&i2c_arm>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tbmp280: bmp280@76 {\n+\t\t\t\tcompatible = \"bosch,bmp280\";\n+\t\t\t\treg = <0x76>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@4 {\n+\t\ttarget = <&i2c_arm>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\thtu21: htu21@40 {\n+\t\t\t\tcompatible = \"htu21\";\n+\t\t\t\treg = <0x40>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@5 {\n+\t\ttarget = <&i2c_arm>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tlm75: lm75@4f {\n+\t\t\t\tcompatible = \"lm75\";\n+\t\t\t\treg = <0x4f>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@6 {\n+\t\ttarget = <&i2c_arm>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tsi7020: si7020@40 {\n+\t\t\t\tcompatible = \"si7020\";\n+\t\t\t\treg = <0x40>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@7 {\n+\t\ttarget = <&i2c_arm>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\ttmp102: tmp102@48 {\n+\t\t\t\tcompatible = \"ti,tmp102\";\n+\t\t\t\treg = <0x48>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@8 {\n+\t\ttarget = <&i2c_arm>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\thdc100x: hdc100x@40 {\n+\t\t\t\tcompatible = \"hdc100x\";\n+\t\t\t\treg = <0x40>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@9 {\n+\t\ttarget = <&i2c_arm>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\ttsl4531: tsl4531@29 {\n+\t\t\t\tcompatible = \"tsl4531\";\n+\t\t\t\treg = <0x29>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@10 {\n+\t\ttarget = <&i2c_arm>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tveml6070: veml6070@38 {\n+\t\t\t\tcompatible = \"veml6070\";\n+\t\t\t\treg = <0x38>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@11 {\n+\t\ttarget = <&i2c_arm>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tsht3x: sht3x@44 {\n+\t\t\t\tcompatible = \"sht3x\";\n+\t\t\t\treg = <0x44>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@12 {\n+\t\ttarget = <&i2c_arm>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tds1621: ds1621@48 {\n+\t\t\t\tcompatible = \"ds1621\";\n+\t\t\t\treg = <0x48>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@13 {\n+\t\ttarget = <&i2c_arm>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tmax17040: max17040@36 {\n+\t\t\t\tcompatible = \"maxim,max17040\";\n+\t\t\t\treg = <0x36>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@14 {\n+\t\ttarget = <&i2c_arm>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tbme680: bme680@76 {\n+\t\t\t\tcompatible = \"bosch,bme680\";\n+\t\t\t\treg = <0x76>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@15 {\n+\t\ttarget = <&i2c_arm>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tsps30: sps30@69 {\n+\t\t\t\tcompatible = \"sensirion,sps30\";\n+\t\t\t\treg = <0x69>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\taddr =  <&bme280>,\"reg:0\", <&bmp280>,\"reg:0\", <&tmp102>,\"reg:0\",\n+\t\t\t<&lm75>,\"reg:0\", <&hdc100x>,\"reg:0\", <&sht3x>,\"reg:0\",\n+\t\t\t<&ds1621>,\"reg:0\", <&bme680>,\"reg:0\";\n+\t\tbme280 = <0>,\"+0\";\n+\t\tbmp085 = <0>,\"+1\";\n+\t\tbmp180 = <0>,\"+2\";\n+\t\tbmp280 = <0>,\"+3\";\n+\t\thtu21 = <0>,\"+4\";\n+\t\tlm75 = <0>,\"+5\";\n+\t\tlm75addr = <&lm75>,\"reg:0\";\n+\t\tsi7020 = <0>,\"+6\";\n+\t\ttmp102 = <0>,\"+7\";\n+\t\thdc100x = <0>,\"+8\";\n+\t\ttsl4531 = <0>,\"+9\";\n+\t\tveml6070 = <0>,\"+10\";\n+\t\tsht3x = <0>,\"+11\";\n+\t\tds1621 = <0>,\"+12\";\n+\t\tmax17040 = <0>,\"+13\";\n+\t\tbme680 = <0>,\"+14\";\n+\t\tsps30 = <0>,\"+15\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/i2c0-overlay.dts b/arch/arm/boot/dts/overlays/i2c0-overlay.dts\nnew file mode 100644\nindex 000000000000..7c6771f84d8e\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/i2c0-overlay.dts\n@@ -0,0 +1,74 @@\n+/dts-v1/;\n+/plugin/;\n+\n+/{\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&i2c0if>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t\tpinctrl-0 = <&i2c0_pins>;\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&i2c0_pins>;\n+\t\tpins1: __overlay__ {\n+\t\t\tbrcm,pins = <0 1>;\n+\t\t\tbrcm,function = <4>; /* alt0 */\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&i2c0_pins>;\n+\t\tpins2: __dormant__ {\n+\t\t\tbrcm,pins = <28 29>;\n+\t\t\tbrcm,function = <4>; /* alt0 */\n+\t\t};\n+\t};\n+\n+\tfragment@3 {\n+\t\ttarget = <&i2c0_pins>;\n+\t\tpins3: __dormant__ {\n+\t\t\tbrcm,pins = <44 45>;\n+\t\t\tbrcm,function = <5>; /* alt1 */\n+\t\t};\n+\t};\n+\n+\tfragment@4 {\n+\t\ttarget = <&i2c0_pins>;\n+\t\tpins4: __dormant__ {\n+\t\t\tbrcm,pins = <46 47>;\n+\t\t\tbrcm,function = <4>; /* alt0 */\n+\t\t};\n+\t};\n+\n+\tfragment@5 {\n+\t\ttarget = <&i2c0>;\n+\t\t__dormant__ {\n+\t\t\tcompatible = \"brcm,bcm2708-i2c\";\n+\t\t};\n+\t};\n+\n+\tfragment@6 {\n+\t\ttarget = <&i2c0mux>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\tfragment@7 {\n+\t\ttarget-path = \"/aliases\";\n+\t\t__overlay__ {\n+\t\t\ti2c0 = \"/soc/i2c@7e205000\";\n+\t\t};\n+\t};\n+\t__overrides__ {\n+\t\tpins_0_1   = <0>,\"+1-2-3-4\";\n+\t\tpins_28_29 = <0>,\"-1+2-3-4\";\n+\t\tpins_44_45 = <0>,\"-1-2+3-4\";\n+\t\tpins_46_47 = <0>,\"-1-2-3+4\";\n+\t\tcombine = <0>, \"!5\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/i2c1-overlay.dts b/arch/arm/boot/dts/overlays/i2c1-overlay.dts\nnew file mode 100644\nindex 000000000000..addaed73e665\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/i2c1-overlay.dts\n@@ -0,0 +1,44 @@\n+/dts-v1/;\n+/plugin/;\n+\n+/{\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&i2c1>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&i2c1_pins>;\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&i2c1_pins>;\n+\t\tpins1: __overlay__ {\n+\t\t\tbrcm,pins = <2 3>;\n+\t\t\tbrcm,function = <4>; /* alt 0 */\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&i2c1_pins>;\n+\t\tpins2: __dormant__ {\n+\t\t\tbrcm,pins = <44 45>;\n+\t\t\tbrcm,function = <6>; /* alt 2 */\n+\t\t};\n+\t};\n+\n+\tfragment@3 {\n+\t\ttarget = <&i2c1>;\n+\t\t__dormant__ {\n+\t\t\tcompatible = \"brcm,bcm2708-i2c\";\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\tpins_2_3   = <0>,\"=1!2\";\n+\t\tpins_44_45 = <0>,\"!1=2\";\n+\t\tcombine = <0>, \"!3\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/i2c3-overlay.dts b/arch/arm/boot/dts/overlays/i2c3-overlay.dts\nnew file mode 100644\nindex 000000000000..e24a1df21f99\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/i2c3-overlay.dts\n@@ -0,0 +1,36 @@\n+/dts-v1/;\n+/plugin/;\n+\n+/{\n+\tcompatible = \"brcm,bcm2711\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&i2c3>;\n+\t\tfrag0: __overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&i2c3_pins>;\n+\t\t\tclock-frequency = <100000>;\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&i2c3_pins>;\n+\t\t__dormant__ {\n+\t\t\tbrcm,pins = <2 3>;\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&i2c3_pins>;\n+\t\t__overlay__ {\n+\t\t\tbrcm,pins = <4 5>;\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\tpins_2_3 = <0>,\"=1!2\";\n+\t\tpins_4_5 = <0>,\"!1=2\";\n+\t\tbaudrate = <&frag0>, \"clock-frequency:0\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/i2c4-overlay.dts b/arch/arm/boot/dts/overlays/i2c4-overlay.dts\nnew file mode 100644\nindex 000000000000..14c7f4d1da4c\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/i2c4-overlay.dts\n@@ -0,0 +1,36 @@\n+/dts-v1/;\n+/plugin/;\n+\n+/{\n+\tcompatible = \"brcm,bcm2711\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&i2c4>;\n+\t\tfrag0: __overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&i2c4_pins>;\n+\t\t\tclock-frequency = <100000>;\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&i2c4_pins>;\n+\t\t__dormant__ {\n+\t\t\tbrcm,pins = <6 7>;\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&i2c4_pins>;\n+\t\t__overlay__ {\n+\t\t\tbrcm,pins = <8 9>;\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\tpins_6_7 = <0>,\"=1!2\";\n+\t\tpins_8_9 = <0>,\"!1=2\";\n+\t\tbaudrate = <&frag0>, \"clock-frequency:0\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/i2c5-overlay.dts b/arch/arm/boot/dts/overlays/i2c5-overlay.dts\nnew file mode 100644\nindex 000000000000..7953621112de\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/i2c5-overlay.dts\n@@ -0,0 +1,36 @@\n+/dts-v1/;\n+/plugin/;\n+\n+/{\n+\tcompatible = \"brcm,bcm2711\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&i2c5>;\n+\t\tfrag0: __overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&i2c5_pins>;\n+\t\t\tclock-frequency = <100000>;\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&i2c5_pins>;\n+\t\t__dormant__ {\n+\t\t\tbrcm,pins = <10 11>;\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&i2c5_pins>;\n+\t\t__overlay__ {\n+\t\t\tbrcm,pins = <12 13>;\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\tpins_10_11 = <0>,\"=1!2\";\n+\t\tpins_12_13 = <0>,\"!1=2\";\n+\t\tbaudrate = <&frag0>, \"clock-frequency:0\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/i2c6-overlay.dts b/arch/arm/boot/dts/overlays/i2c6-overlay.dts\nnew file mode 100644\nindex 000000000000..555305a7ee1f\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/i2c6-overlay.dts\n@@ -0,0 +1,36 @@\n+/dts-v1/;\n+/plugin/;\n+\n+/{\n+\tcompatible = \"brcm,bcm2711\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&i2c6>;\n+\t\tfrag0: __overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&i2c6_pins>;\n+\t\t\tclock-frequency = <100000>;\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&i2c6_pins>;\n+\t\t__dormant__ {\n+\t\t\tbrcm,pins = <0 1>;\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&i2c6_pins>;\n+\t\t__overlay__ {\n+\t\t\tbrcm,pins = <22 23>;\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\tpins_0_1 = <0>,\"=1!2\";\n+\t\tpins_22_23 = <0>,\"!1=2\";\n+\t\tbaudrate = <&frag0>, \"clock-frequency:0\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/i2s-gpio28-31-overlay.dts b/arch/arm/boot/dts/overlays/i2s-gpio28-31-overlay.dts\nnew file mode 100644\nindex 000000000000..cf43094c6ff4\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/i2s-gpio28-31-overlay.dts\n@@ -0,0 +1,18 @@\n+/*\n+ * Device tree overlay to move i2s to gpio 28 to 31 on CM\n+ */\n+\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&i2s_pins>;\n+\t\t__overlay__ {\n+\t\t\tbrcm,pins = <28 29 30 31>;\n+\t\t\tbrcm,function = <6>; /* alt2 */\n+\t\t};\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/ilitek251x-overlay.dts b/arch/arm/boot/dts/overlays/ilitek251x-overlay.dts\nnew file mode 100644\nindex 000000000000..551aba591d26\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/ilitek251x-overlay.dts\n@@ -0,0 +1,45 @@\n+// Device tree overlay for I2C connected Ilitek multiple touch controller\n+/dts-v1/;\n+/plugin/;\n+\n+ / {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+ \tfragment@0 {\n+\t\ttarget = <&gpio>;\n+\t\t__overlay__ {\t\t\n+\t\t\tili251x_pins: ili251x_pins {\n+\t\t\t\tbrcm,pins = <4>; // interrupt\n+\t\t\t\tbrcm,function = <0>; // in\n+\t\t\t\tbrcm,pull = <2>; // pull-up //\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+ \tfragment@1 {\n+\t\ttarget = <&i2c1>;\n+\t\t__overlay__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+ \t\t\tili251x: ili251x@41 {\n+\t\t\t\tcompatible = \"ilitek,ili251x\";\n+\t\t\t\treg = <0x41>;\n+\t\t\t\tpinctrl-names = \"default\";\n+\t\t\t\tpinctrl-0 = <&ili251x_pins>;\n+\t\t\t\tinterrupt-parent = <&gpio>;\n+\t\t\t\tinterrupts = <4 8>; // high-to-low edge triggered\n+\t\t\t\ttouchscreen-size-x = <16384>;\n+\t\t\t\ttouchscreen-size-y = <9600>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+ \t__overrides__ {\n+\t\tinterrupt = <&ili251x_pins>,\"brcm,pins:0\",\n+\t\t\t<&ili251x>,\"interrupts:0\";\n+\t\tsizex = <&ili251x>,\"touchscreen-size-x:0\";\n+\t\tsizey = <&ili251x>,\"touchscreen-size-y:0\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/imx219-overlay.dts b/arch/arm/boot/dts/overlays/imx219-overlay.dts\nnew file mode 100644\nindex 000000000000..3484bde5a9e8\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/imx219-overlay.dts\n@@ -0,0 +1,119 @@\n+// SPDX-License-Identifier: GPL-2.0-only\n+// Definitions for IMX219 camera module on VC I2C bus\n+/dts-v1/;\n+/plugin/;\n+\n+#include <dt-bindings/gpio/gpio.h>\n+\n+/{\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&i2c_csi_dsi>;\n+\t\t__overlay__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\timx219: imx219@10 {\n+\t\t\t\tcompatible = \"sony,imx219\";\n+\t\t\t\treg = <0x10>;\n+\t\t\t\tstatus = \"okay\";\n+\n+\t\t\t\tclocks = <&imx219_clk>;\n+\t\t\t\tclock-names = \"xclk\";\n+\n+\t\t\t\tVANA-supply = <&imx219_vana>;\t/* 2.8v */\n+\t\t\t\tVDIG-supply = <&imx219_vdig>;\t/* 1.8v */\n+\t\t\t\tVDDL-supply = <&imx219_vddl>;\t/* 1.2v */\n+\n+\t\t\t\trotation = <180>;\n+\n+\t\t\t\tport {\n+\t\t\t\t\timx219_0: endpoint {\n+\t\t\t\t\t\tremote-endpoint = <&csi1_ep>;\n+\t\t\t\t\t\tclock-lanes = <0>;\n+\t\t\t\t\t\tdata-lanes = <1 2>;\n+\t\t\t\t\t\tclock-noncontinuous;\n+\t\t\t\t\t\tlink-frequencies =\n+\t\t\t\t\t\t\t/bits/ 64 <297000000>;\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&csi1>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tport {\n+\t\t\t\tcsi1_ep: endpoint {\n+\t\t\t\t\tremote-endpoint = <&imx219_0>;\n+\t\t\t\t\tclock-lanes = <0>;\n+\t\t\t\t\tdata-lanes = <1 2>;\n+\t\t\t\t\tclock-noncontinuous;\n+\t\t\t\t};\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&i2c0if>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@3 {\n+\t\ttarget-path=\"/\";\n+\t\t__overlay__ {\n+\t\t\timx219_vana: fixedregulator@0 {\n+\t\t\t\tcompatible = \"regulator-fixed\";\n+\t\t\t\tregulator-name = \"imx219_vana\";\n+\t\t\t\tregulator-min-microvolt = <2800000>;\n+\t\t\t\tregulator-max-microvolt = <2800000>;\n+\t\t\t\tgpio = <&gpio 41 GPIO_ACTIVE_HIGH>;\n+\t\t\t\tenable-active-high;\n+\t\t\t};\n+\t\t\timx219_vdig: fixedregulator@1 {\n+\t\t\t\tcompatible = \"regulator-fixed\";\n+\t\t\t\tregulator-name = \"imx219_vdig\";\n+\t\t\t\tregulator-min-microvolt = <1800000>;\n+\t\t\t\tregulator-max-microvolt = <1800000>;\n+\t\t\t};\n+\t\t\timx219_vddl: fixedregulator@2 {\n+\t\t\t\tcompatible = \"regulator-fixed\";\n+\t\t\t\tregulator-name = \"imx219_vddl\";\n+\t\t\t\tregulator-min-microvolt = <1200000>;\n+\t\t\t\tregulator-max-microvolt = <1200000>;\n+\t\t\t};\n+\n+\t\t\timx219_clk: camera-clk {\n+\t\t\t\tcompatible = \"fixed-clock\";\n+\t\t\t\t#clock-cells = <0>;\n+\t\t\t\tclock-frequency = <24000000>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@4 {\n+\t\ttarget = <&i2c0mux>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@5 {\n+\t\ttarget-path=\"/__overrides__\";\n+\t\t__overlay__ {\n+\t\t\tcam0-pwdn-ctrl = <&imx219_vana>,\"gpio:0\";\n+\t\t\tcam0-pwdn      = <&imx219_vana>,\"gpio:4\";\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\trotation = <&imx219>,\"rotation:0\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/imx290-overlay.dts b/arch/arm/boot/dts/overlays/imx290-overlay.dts\nnew file mode 100644\nindex 000000000000..e536aa7f9e33\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/imx290-overlay.dts\n@@ -0,0 +1,32 @@\n+// SPDX-License-Identifier: GPL-2.0-only\n+// Definitions for IMX290 camera module on VC I2C bus\n+/dts-v1/;\n+/plugin/;\n+\n+#include <dt-bindings/gpio/gpio.h>\n+#include \"imx290_327-overlay.dtsi\"\n+\n+/{\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\t// Fragment numbers deliberately high to avoid conflicts with the\n+\t// included imx290_327 overlay file.\n+\n+\tfragment@101 {\n+\t\ttarget = <&imx290>;\n+\t\t__overlay__ {\n+\t\t\tcompatible = \"sony,imx290\";\n+\t\t};\n+\t};\n+\n+\tfragment@102 {\n+\t\ttarget = <&imx290>;\n+\t\t__dormant__ {\n+\t\t\tcompatible = \"sony,imx290-mono\";\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\tmono = <0>, \"-101+102\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/imx290_327-overlay.dtsi b/arch/arm/boot/dts/overlays/imx290_327-overlay.dtsi\nnew file mode 100644\nindex 000000000000..8f1dadb13f6a\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/imx290_327-overlay.dtsi\n@@ -0,0 +1,145 @@\n+// SPDX-License-Identifier: GPL-2.0-only\n+// Partial definitions for IMX290 or IMX327 camera module on VC I2C bus\n+// The compatible string should be set in an overlay that then includes this one\n+/dts-v1/;\n+/plugin/;\n+\n+#include <dt-bindings/gpio/gpio.h>\n+\n+/{\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&i2c_csi_dsi>;\n+\t\t__overlay__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\timx290: imx290@1a {\n+\t\t\t\treg = <0x1a>;\n+\t\t\t\tstatus = \"okay\";\n+\n+\t\t\t\tclocks = <&imx290_clk>;\n+\t\t\t\tclock-names = \"xclk\";\n+\t\t\t\tclock-frequency = <37125000>;\n+\n+\t\t\t\tvdda-supply = <&imx290_vdda>;\t/* 2.8v */\n+\t\t\t\tvdddo-supply = <&imx290_vdddo>;\t/* 1.8v */\n+\t\t\t\tvddd-supply = <&imx290_vddd>;\t/* 1.5v */\n+\n+\t\t\t\tport {\n+\t\t\t\t\timx290_0: endpoint {\n+\t\t\t\t\t\tremote-endpoint = <&csi1_ep>;\n+\t\t\t\t\t\tclock-lanes = <0>;\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&csi1>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tport {\n+\t\t\t\tcsi1_ep: endpoint {\n+\t\t\t\t\tremote-endpoint = <&imx290_0>;\n+\t\t\t\t};\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&i2c0if>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@3 {\n+\t\ttarget-path=\"/\";\n+\t\t__overlay__ {\n+\t\t\timx290_vdda: fixedregulator@0 {\n+\t\t\t\tcompatible = \"regulator-fixed\";\n+\t\t\t\tregulator-name = \"imx290_vdda\";\n+\t\t\t\tregulator-min-microvolt = <2800000>;\n+\t\t\t\tregulator-max-microvolt = <2800000>;\n+\t\t\t\tgpio = <&gpio 41 GPIO_ACTIVE_HIGH>;\n+\t\t\t\tenable-active-high;\n+\t\t\t};\n+\t\t\timx290_vdddo: fixedregulator@1 {\n+\t\t\t\tcompatible = \"regulator-fixed\";\n+\t\t\t\tregulator-name = \"imx290_vdddo\";\n+\t\t\t\tregulator-min-microvolt = <1800000>;\n+\t\t\t\tregulator-max-microvolt = <1800000>;\n+\t\t\t};\n+\t\t\timx290_vddd: fixedregulator@2 {\n+\t\t\t\tcompatible = \"regulator-fixed\";\n+\t\t\t\tregulator-name = \"imx290_vddd\";\n+\t\t\t\tregulator-min-microvolt = <1500000>;\n+\t\t\t\tregulator-max-microvolt = <1500000>;\n+\t\t\t};\n+\n+\t\t\timx290_clk: camera-clk {\n+\t\t\t\tcompatible = \"fixed-clock\";\n+\t\t\t\t#clock-cells = <0>;\n+\t\t\t\tclock-frequency = <37125000>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@4 {\n+\t\ttarget = <&i2c0mux>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@5 {\n+\t\ttarget-path=\"/__overrides__\";\n+\t\t__overlay__ {\n+\t\t\tcam0-pwdn-ctrl = <&imx290_vdda>,\"gpio:0\";\n+\t\t\tcam0-pwdn      = <&imx290_vdda>,\"gpio:4\";\n+\t\t};\n+\t};\n+\n+\tfragment@6 {\n+\t\ttarget = <&imx290_0>;\n+\t\t__overlay__ {\n+\t\t\tdata-lanes = <1 2>;\n+\t\t\tlink-frequencies =\n+\t\t\t\t/bits/ 64 <445500000 297000000>;\n+\t\t};\n+\t};\n+\n+\tfragment@7 {\n+\t\ttarget = <&imx290_0>;\n+\t\t__dormant__ {\n+\t\t\tdata-lanes = <1 2 3 4>;\n+\t\t\tlink-frequencies =\n+\t\t\t\t/bits/ 64 <222750000 148500000>;\n+\t\t};\n+\t};\n+\n+\tfragment@8 {\n+\t\ttarget = <&csi1_ep>;\n+\t\t__overlay__ {\n+\t\t\tdata-lanes = <1 2>;\n+\t\t};\n+\t};\n+\n+\tfragment@9 {\n+\t\ttarget = <&csi1_ep>;\n+\t\t__dormant__ {\n+\t\t\tdata-lanes = <1 2 3 4>;\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\t4lane = <0>, \"-6+7-8+9\";\n+\t\tclock-frequency = <&imx290_clk>,\"clock-frequency:0\",\n+\t\t\t\t  <&imx290>,\"clock-frequency:0\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/imx477-overlay.dts b/arch/arm/boot/dts/overlays/imx477-overlay.dts\nnew file mode 100644\nindex 000000000000..1a97eaaf4c82\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/imx477-overlay.dts\n@@ -0,0 +1,119 @@\n+// SPDX-License-Identifier: GPL-2.0-only\n+// Definitions for IMX477 camera module on VC I2C bus\n+/dts-v1/;\n+/plugin/;\n+\n+#include <dt-bindings/gpio/gpio.h>\n+\n+/{\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&i2c_csi_dsi>;\n+\t\t__overlay__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\timx477: imx477@1a {\n+\t\t\t\tcompatible = \"sony,imx477\";\n+\t\t\t\treg = <0x1a>;\n+\t\t\t\tstatus = \"okay\";\n+\n+\t\t\t\tclocks = <&imx477_clk>;\n+\t\t\t\tclock-names = \"xclk\";\n+\n+\t\t\t\tVANA-supply = <&imx477_vana>;\t/* 2.8v */\n+\t\t\t\tVDIG-supply = <&imx477_vdig>;\t/* 1.05v */\n+\t\t\t\tVDDL-supply = <&imx477_vddl>;\t/* 1.8v */\n+\n+\t\t\t\trotation = <180>;\n+\n+\t\t\t\tport {\n+\t\t\t\t\timx477_0: endpoint {\n+\t\t\t\t\t\tremote-endpoint = <&csi1_ep>;\n+\t\t\t\t\t\tclock-lanes = <0>;\n+\t\t\t\t\t\tdata-lanes = <1 2>;\n+\t\t\t\t\t\tclock-noncontinuous;\n+\t\t\t\t\t\tlink-frequencies =\n+\t\t\t\t\t\t\t/bits/ 64 <450000000>;\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&csi1>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tport {\n+\t\t\t\tcsi1_ep: endpoint {\n+\t\t\t\t\tremote-endpoint = <&imx477_0>;\n+\t\t\t\t\tclock-lanes = <0>;\n+\t\t\t\t\tdata-lanes = <1 2>;\n+\t\t\t\t\tclock-noncontinuous;\n+\t\t\t\t};\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&i2c0if>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@3 {\n+\t\ttarget-path=\"/\";\n+\t\t__overlay__ {\n+\t\t\timx477_vana: fixedregulator@0 {\n+\t\t\t\tcompatible = \"regulator-fixed\";\n+\t\t\t\tregulator-name = \"imx477_vana\";\n+\t\t\t\tregulator-min-microvolt = <2800000>;\n+\t\t\t\tregulator-max-microvolt = <2800000>;\n+\t\t\t\tgpio = <&gpio 41 GPIO_ACTIVE_HIGH>;\n+\t\t\t\tenable-active-high;\n+\t\t\t\tstartup-delay-us = <300000>;\n+\t\t\t};\n+\t\t\timx477_vdig: fixedregulator@1 {\n+\t\t\t\tcompatible = \"regulator-fixed\";\n+\t\t\t\tregulator-name = \"imx477_vdig\";\n+\t\t\t\tregulator-min-microvolt = <1050000>;\n+\t\t\t\tregulator-max-microvolt = <1050000>;\n+\t\t\t};\n+\t\t\timx477_vddl: fixedregulator@2 {\n+\t\t\t\tcompatible = \"regulator-fixed\";\n+\t\t\t\tregulator-name = \"imx477_vddl\";\n+\t\t\t\tregulator-min-microvolt = <1800000>;\n+\t\t\t\tregulator-max-microvolt = <1800000>;\n+\t\t\t};\n+\t\t\timx477_clk: camera-clk {\n+\t\t\t\tcompatible = \"fixed-clock\";\n+\t\t\t\t#clock-cells = <0>;\n+\t\t\t\tclock-frequency = <24000000>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@4 {\n+\t\ttarget = <&i2c0mux>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@5 {\n+\t\ttarget-path=\"/__overrides__\";\n+\t\t__overlay__ {\n+\t\t\tcam0-pwdn-ctrl = <&imx477_vana>,\"gpio:0\";\n+\t\t\tcam0-pwdn      = <&imx477_vana>,\"gpio:4\";\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\trotation = <&imx477>,\"rotation:0\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/iqaudio-codec-overlay.dts b/arch/arm/boot/dts/overlays/iqaudio-codec-overlay.dts\nnew file mode 100644\nindex 000000000000..9110f5d34298\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/iqaudio-codec-overlay.dts\n@@ -0,0 +1,42 @@\n+// Definitions for IQaudIO CODEC\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&i2s>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&i2c1>;\n+\t\t__overlay__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tda2713@1a {\n+\t\t\t\t#sound-dai-cells = <0>;\n+\t\t\t\tcompatible = \"dlg,da7213\";\n+\t\t\t\treg = <0x1a>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&sound>;\n+\t\tiqaudio_dac: __overlay__ {\n+\t\t\tcompatible = \"iqaudio,iqaudio-codec\";\n+\t\t\ti2s-controller = <&i2s>;\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/iqaudio-dac-overlay.dts b/arch/arm/boot/dts/overlays/iqaudio-dac-overlay.dts\nnew file mode 100644\nindex 000000000000..24073cadd0ef\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/iqaudio-dac-overlay.dts\n@@ -0,0 +1,46 @@\n+// Definitions for IQaudIO DAC\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&i2s>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&i2c1>;\n+\t\t__overlay__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tpcm5122@4c {\n+\t\t\t\t#sound-dai-cells = <0>;\n+\t\t\t\tcompatible = \"ti,pcm5122\";\n+\t\t\t\treg = <0x4c>;\n+\t\t\t\tAVDD-supply = <&vdd_3v3_reg>;\n+\t\t\t\tDVDD-supply = <&vdd_3v3_reg>;\n+\t\t\t\tCPVDD-supply = <&vdd_3v3_reg>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&sound>;\n+\t\tfrag2: __overlay__ {\n+\t\t\tcompatible = \"iqaudio,iqaudio-dac\";\n+\t\t\ti2s-controller = <&i2s>;\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\t24db_digital_gain = <&frag2>,\"iqaudio,24db_digital_gain?\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/iqaudio-dacplus-overlay.dts b/arch/arm/boot/dts/overlays/iqaudio-dacplus-overlay.dts\nnew file mode 100644\nindex 000000000000..7c70b25e58d7\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/iqaudio-dacplus-overlay.dts\n@@ -0,0 +1,49 @@\n+// Definitions for IQaudIO DAC+\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&i2s>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&i2c1>;\n+\t\t__overlay__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tpcm5122@4c {\n+\t\t\t\t#sound-dai-cells = <0>;\n+\t\t\t\tcompatible = \"ti,pcm5122\";\n+\t\t\t\treg = <0x4c>;\n+\t\t\t\tAVDD-supply = <&vdd_3v3_reg>;\n+\t\t\t\tDVDD-supply = <&vdd_3v3_reg>;\n+\t\t\t\tCPVDD-supply = <&vdd_3v3_reg>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&sound>;\n+\t\tiqaudio_dac: __overlay__ {\n+\t\t\tcompatible = \"iqaudio,iqaudio-dac\";\n+\t\t\ti2s-controller = <&i2s>;\n+\t\t\tmute-gpios = <&gpio 22 0>;\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\t24db_digital_gain = <&iqaudio_dac>,\"iqaudio,24db_digital_gain?\";\n+\t\tauto_mute_amp = <&iqaudio_dac>,\"iqaudio-dac,auto-mute-amp?\";\n+\t\tunmute_amp = <&iqaudio_dac>,\"iqaudio-dac,unmute-amp?\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/iqaudio-digi-wm8804-audio-overlay.dts b/arch/arm/boot/dts/overlays/iqaudio-digi-wm8804-audio-overlay.dts\nnew file mode 100644\nindex 000000000000..ee54095c869b\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/iqaudio-digi-wm8804-audio-overlay.dts\n@@ -0,0 +1,47 @@\n+// Definitions for IQAudIO Digi WM8804 audio board\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&i2s>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&i2c1>;\n+\t\t__overlay__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\twm8804@3b {\n+\t\t\t\t#sound-dai-cells = <0>;\n+\t\t\t\tcompatible = \"wlf,wm8804\";\n+\t\t\t\treg = <0x3b>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t\tDVDD-supply = <&vdd_3v3_reg>;\n+\t\t\t\tPVDD-supply = <&vdd_3v3_reg>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&sound>;\n+\t\twm8804_digi: __overlay__ {\n+\t\t\tcompatible = \"iqaudio,wm8804-digi\";\n+\t\t\ti2s-controller = <&i2s>;\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\tcard_name = <&wm8804_digi>,\"wm8804-digi,card-name\";\n+\t\tdai_name = <&wm8804_digi>,\"wm8804-digi,dai-name\";\n+\t\tdai_stream_name = <&wm8804_digi>,\"wm8804-digi,dai-stream-name\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/irs1125-overlay.dts b/arch/arm/boot/dts/overlays/irs1125-overlay.dts\nnew file mode 100644\nindex 000000000000..e926e18e71fc\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/irs1125-overlay.dts\n@@ -0,0 +1,85 @@\n+// SPDX-License-Identifier: GPL-2.0-only\n+// Definitions for IRS1125 camera module on VC I2C bus\n+/dts-v1/;\n+/plugin/;\n+\n+/{\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&i2c_csi_dsi>;\n+\t\t__overlay__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tirs1125: irs1125@3D {\n+\t\t\t\tcompatible = \"infineon,irs1125\";\n+\t\t\t\treg = <0x3D>;\n+\t\t\t\tstatus = \"okay\";\n+\n+\t\t\t\tpwdn-gpios = <&gpio 5 0>;\n+\t\t\t\tclocks = <&irs1125_clk>;\n+\n+\t\t\t\tport {\n+\t\t\t\t\tirs1125_0: endpoint {\n+\t\t\t\t\t\tremote-endpoint = <&csi1_ep>;\n+\t\t\t\t\t\tclock-lanes = <0>;\n+\t\t\t\t\t\tdata-lanes = <1 2>;\n+\t\t\t\t\t\tclock-noncontinuous;\n+\t\t\t\t\t\tlink-frequencies =\n+\t\t\t\t\t\t\t/bits/ 64 <297000000>;\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&csi1>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tport {\n+\t\t\t\tcsi1_ep: endpoint {\n+\t\t\t\t\tremote-endpoint = <&irs1125_0>;\n+\t\t\t\t\tdata-lanes = <1 2>;\n+\t\t\t\t\tclock-noncontinuous;\n+\t\t\t\t};\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&i2c0if>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@3 {\n+\t\ttarget = <&i2c0mux>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@4 {\n+\t\ttarget-path=\"/__overrides__\";\n+\t\t__overlay__ {\n+\t\t\tcam0-pwdn-ctrl = <&irs1125>,\"pwdn-gpios:0\";\n+\t\t\tcam0-pwdn      = <&irs1125>,\"pwdn-gpios:4\";\n+\t\t};\n+\t};\n+\n+\tfragment@5 {\n+\t\ttarget-path = \"/\";\n+\t\t__overlay__ {\n+\t\t\tirs1125_clk: camera-clk {\n+\t\t\t\tcompatible = \"fixed-clock\";\n+\t\t\t\t#clock-cells = <0>;\n+\t\t\t\tclock-frequency = <26000000>;\n+\t\t\t};\n+\t\t};\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/jedec-spi-nor-overlay.dts b/arch/arm/boot/dts/overlays/jedec-spi-nor-overlay.dts\nnew file mode 100644\nindex 000000000000..585c7dbcdf7f\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/jedec-spi-nor-overlay.dts\n@@ -0,0 +1,309 @@\n+// Overlay for JEDEC SPI-NOR Flash Devices (aka m25p80)\n+\n+// dtparams:\n+//     flash-spi<n>-<m>        - Enables flash device on SPI<n>, CS#<m>.\n+//     flash-fastr-spi<n>-<m>  - Enables flash device with fast read capability on SPI<n>, CS#<m>.\n+//\n+// If devices are present on SPI1 or SPI2, those interfaces must be enabled with one of the spi1-1/2/3cs and/or spi2-1/2/3cs overlays.\n+//\n+// Example: A single flash device with fast read capability on SPI0, CS#0:\n+// dtoverlay=jedec-spi-nor:flash-fastr-spi0-0\n+\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\t// disable spi-dev on spi0.0\n+\tfragment@0 {\n+\t\ttarget = <&spidev0>;\n+\t\t__dormant__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\t// disable spi-dev on spi0.1\n+\tfragment@1 {\n+\t\ttarget = <&spidev1>;\n+\t\t__dormant__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\t// disable spi-dev on spi1.0\n+\tfragment@2 {\n+\t\ttarget-path = \"spi1/spidev@0\";\n+\t\t__dormant__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\t// disable spi-dev on spi1.1\n+\tfragment@3 {\n+\t\ttarget-path = \"spi1/spidev@1\";\n+\t\t__dormant__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\t// disable spi-dev on spi1.2\n+\tfragment@4 {\n+\t\ttarget-path = \"spi1/spidev@2\";\n+\t\t__dormant__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\t// disable spi-dev on spi2.0\n+\tfragment@5 {\n+\t\ttarget-path = \"spi2/spidev@0\";\n+\t\t__dormant__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\t// disable spi-dev on spi2.1\n+\tfragment@6 {\n+\t\ttarget-path = \"spi2/spidev@1\";\n+\t\t__dormant__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\t// disable spi-dev on spi2.2\n+\tfragment@7 {\n+\t\ttarget-path = \"spi2/spidev@2\";\n+\t\t__dormant__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\t// enable flash on spi0.0\n+\tfragment@8 {\n+\t\ttarget = <&spi0>;\n+\t\t__dormant__ {\n+\t\t\tstatus = \"okay\";\n+                        #address-cells = <1>;\n+                        #size-cells = <0>;\n+\t\t\tspi_nor_00: spi_nor@0 {\n+\t\t\t\t#address-cells = <1>;\n+\t\t\t\t#size-cells = <1>;\n+\t\t\t\tcompatible = \"jedec,spi-nor\";\n+\t\t\t\treg = <0>;\n+\t\t\t\tspi-max-frequency = <500000>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t// enable flash on spi0.1\n+\tfragment@9 {\n+\t\ttarget = <&spi0>;\n+\t\t__dormant__ {\n+\t\t\tstatus = \"okay\";\n+                        #address-cells = <1>;\n+                        #size-cells = <0>;\n+\t\t\tspi_nor_01: spi_nor@1 {\n+\t\t\t\t#address-cells = <1>;\n+\t\t\t\t#size-cells = <1>;\n+\t\t\t\tcompatible = \"jedec,spi-nor\";\n+\t\t\t\treg = <1>;\n+\t\t\t\tspi-max-frequency = <500000>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t// enable flash on spi1.0\n+\tfragment@10 {\n+\t\ttarget = <&spi1>;\n+\t\t__dormant__ {\n+\t\t\tstatus = \"okay\";\n+                        #address-cells = <1>;\n+                        #size-cells = <0>;\n+\t\t\tspi_nor_10: spi_nor@0 {\n+\t\t\t\t#address-cells = <1>;\n+\t\t\t\t#size-cells = <1>;\n+\t\t\t\tcompatible = \"jedec,spi-nor\";\n+\t\t\t\treg = <0>;\n+\t\t\t\tspi-max-frequency = <500000>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t// enable flash on spi1.1\n+\tfragment@11 {\n+\t\ttarget = <&spi1>;\n+\t\t__dormant__ {\n+\t\t\tstatus = \"okay\";\n+                        #address-cells = <1>;\n+                        #size-cells = <0>;\n+\t\t\tspi_nor_11: spi_nor@1 {\n+\t\t\t\t#address-cells = <1>;\n+\t\t\t\t#size-cells = <1>;\n+\t\t\t\tcompatible = \"jedec,spi-nor\";\n+\t\t\t\treg = <1>;\n+\t\t\t\tspi-max-frequency = <500000>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t// enable flash on spi1.2\n+\tfragment@12 {\n+\t\ttarget = <&spi1>;\n+\t\t__dormant__ {\n+\t\t\tstatus = \"okay\";\n+                        #address-cells = <1>;\n+                        #size-cells = <0>;\n+\t\t\tspi_nor_12: spi_nor@2 {\n+\t\t\t\t#address-cells = <1>;\n+\t\t\t\t#size-cells = <1>;\n+\t\t\t\tcompatible = \"jedec,spi-nor\";\n+\t\t\t\treg = <2>;\n+\t\t\t\tspi-max-frequency = <500000>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t// enable flash on spi2.0\n+\tfragment@13 {\n+\t\ttarget = <&spi2>;\n+\t\t__dormant__ {\n+\t\t\tstatus = \"okay\";\n+                        #address-cells = <1>;\n+                        #size-cells = <0>;\n+\t\t\tspi_nor_20: spi_nor@0 {\n+\t\t\t\t#address-cells = <1>;\n+\t\t\t\t#size-cells = <1>;\n+\t\t\t\tcompatible = \"jedec,spi-nor\";\n+\t\t\t\treg = <0>;\n+\t\t\t\tspi-max-frequency = <500000>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t// enable flash on spi2.1\n+\tfragment@14 {\n+\t\ttarget = <&spi2>;\n+\t\t__dormant__ {\n+\t\t\tstatus = \"okay\";\n+                        #address-cells = <1>;\n+                        #size-cells = <0>;\n+\t\t\tspi_nor_21: spi_nor@1 {\n+\t\t\t\t#address-cells = <1>;\n+\t\t\t\t#size-cells = <1>;\n+\t\t\t\tcompatible = \"jedec,spi-nor\";\n+\t\t\t\treg = <1>;\n+\t\t\t\tspi-max-frequency = <500000>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t// enable flash on spi2.2\n+\tfragment@15 {\n+\t\ttarget = <&spi2>;\n+\t\t__dormant__ {\n+\t\t\tstatus = \"okay\";\n+                        #address-cells = <1>;\n+                        #size-cells = <0>;\n+\t\t\tspi_nor_22: spi_nor@2 {\n+\t\t\t\t#address-cells = <1>;\n+\t\t\t\t#size-cells = <1>;\n+\t\t\t\tcompatible = \"jedec,spi-nor\";\n+\t\t\t\treg = <2>;\n+\t\t\t\tspi-max-frequency = <500000>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t// Enable fast read for device on spi0.0.\n+\t// Use default active low interrupt signalling.\n+\tfragment@16 {\n+\t\ttarget = <&spi_nor_00>;\n+\t\t__dormant__ {\n+\t\t\tm25p,fast-read;\n+\t\t};\n+\t};\n+\n+\t// Enable fast read for device on spi0.1.\n+\t// Use default active low interrupt signalling.\n+\tfragment@17 {\n+\t\ttarget = <&spi_nor_01>;\n+\t\t__dormant__ {\n+\t\t\tm25p,fast-read;\n+\t\t};\n+\t};\n+\n+\t// Enable fast read for device on spi1.0.\n+\t// Use default active low interrupt signalling.\n+\tfragment@18 {\n+\t\ttarget = <&spi_nor_10>;\n+\t\t__dormant__ {\n+\t\t\tm25p,fast-read;\n+\t\t};\n+\t};\n+\n+\t// Enable fast read for device on spi1.1.\n+\t// Use default active low interrupt signalling.\n+\tfragment@19 {\n+\t\ttarget = <&spi_nor_11>;\n+\t\t__dormant__ {\n+\t\t\tm25p,fast-read;\n+\t\t};\n+\t};\n+\n+\t// Enable fast read for device on spi1.2.\n+\t// Use default active low interrupt signalling.\n+\tfragment@20 {\n+\t\ttarget = <&spi_nor_12>;\n+\t\t__dormant__ {\n+\t\t\tm25p,fast-read;\n+\t\t};\n+\t};\n+\n+\t// Enable fast read for device on spi2.0.\n+\t// Use default active low interrupt signalling.\n+\tfragment@21 {\n+\t\ttarget = <&spi_nor_20>;\n+\t\t__dormant__ {\n+\t\t\tm25p,fast-read;\n+\t\t};\n+\t};\n+\n+\t// Enable fast read for device on spi2.1.\n+\t// Use default active low interrupt signalling.\n+\tfragment@22 {\n+\t\ttarget = <&spi_nor_21>;\n+\t\t__dormant__ {\n+\t\t\tm25p,fast-read;\n+\t\t};\n+\t};\n+\n+\t// Enable fast read for device on spi2.2.\n+\t// Use default active low interrupt signalling.\n+\tfragment@23 {\n+\t\ttarget = <&spi_nor_22>;\n+\t\t__dormant__ {\n+\t\t\tm25p,fast-read;\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\tflash-spi0-0       = <0>,\"+0+8\";\n+\t\tflash-spi0-1       = <0>,\"+1+9\";\n+\t\tflash-spi1-0       = <0>,\"+2+10\";\n+\t\tflash-spi1-1       = <0>,\"+3+11\";\n+\t\tflash-spi1-2       = <0>,\"+4+12\";\n+\t\tflash-spi2-0       = <0>,\"+5+13\";\n+\t\tflash-spi2-1       = <0>,\"+6+14\";\n+\t\tflash-spi2-2       = <0>,\"+7+15\";\n+\t\tflash-fastr-spi0-0 = <0>,\"+0+8+16\";\n+\t\tflash-fastr-spi0-1 = <0>,\"+1+9+17\";\n+\t\tflash-fastr-spi1-0 = <0>,\"+2+10+18\";\n+\t\tflash-fastr-spi1-1 = <0>,\"+3+11+19\";\n+\t\tflash-fastr-spi1-2 = <0>,\"+4+12+20\";\n+\t\tflash-fastr-spi2-0 = <0>,\"+5+13+21\";\n+\t\tflash-fastr-spi2-1 = <0>,\"+6+14+22\";\n+\t\tflash-fastr-spi2-2 = <0>,\"+7+15+23\";\n+\t};\n+};\n+\ndiff --git a/arch/arm/boot/dts/overlays/justboom-both-overlay.dts b/arch/arm/boot/dts/overlays/justboom-both-overlay.dts\nnew file mode 100644\nindex 000000000000..9c42670631c0\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/justboom-both-overlay.dts\n@@ -0,0 +1,65 @@\n+// SPDX-License-Identifier: GPL-2.0\n+// Definitions for JustBoom Both (Digi+DAC)\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&i2s>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&i2c1>;\n+\t\t__overlay__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\twm8804@3b {\n+\t\t\t\t#sound-dai-cells = <0>;\n+\t\t\t\tcompatible = \"wlf,wm8804\";\n+\t\t\t\treg = <0x3b>;\n+\t\t\t\tPVDD-supply = <&vdd_3v3_reg>;\n+\t\t\t\tDVDD-supply = <&vdd_3v3_reg>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&i2c1>;\n+\t\t__overlay__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tpcm5122@4d {\n+\t\t\t\t#sound-dai-cells = <0>;\n+\t\t\t\tcompatible = \"ti,pcm5122\";\n+\t\t\t\treg = <0x4d>;\n+\t\t\t\tAVDD-supply = <&vdd_3v3_reg>;\n+\t\t\t\tDVDD-supply = <&vdd_3v3_reg>;\n+\t\t\t\tCPVDD-supply = <&vdd_3v3_reg>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@3 {\n+\t\ttarget = <&sound>;\n+\t\tfrag3: __overlay__ {\n+\t\t\tcompatible = \"justboom,justboom-both\";\n+\t\t\ti2s-controller = <&i2s>;\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\t24db_digital_gain = <&frag3>,\"justboom,24db_digital_gain?\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/justboom-dac-overlay.dts b/arch/arm/boot/dts/overlays/justboom-dac-overlay.dts\nnew file mode 100644\nindex 000000000000..d00515dca419\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/justboom-dac-overlay.dts\n@@ -0,0 +1,46 @@\n+// Definitions for JustBoom DAC\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&i2s>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&i2c1>;\n+\t\t__overlay__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tpcm5122@4d {\n+\t\t\t\t#sound-dai-cells = <0>;\n+\t\t\t\tcompatible = \"ti,pcm5122\";\n+\t\t\t\treg = <0x4d>;\n+\t\t\t\tAVDD-supply = <&vdd_3v3_reg>;\n+\t\t\t\tDVDD-supply = <&vdd_3v3_reg>;\n+\t\t\t\tCPVDD-supply = <&vdd_3v3_reg>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&sound>;\n+\t\tfrag2: __overlay__ {\n+\t\t\tcompatible = \"justboom,justboom-dac\";\n+\t\t\ti2s-controller = <&i2s>;\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\t24db_digital_gain = <&frag2>,\"justboom,24db_digital_gain?\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/justboom-digi-overlay.dts b/arch/arm/boot/dts/overlays/justboom-digi-overlay.dts\nnew file mode 100644\nindex 000000000000..e73336029c54\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/justboom-digi-overlay.dts\n@@ -0,0 +1,41 @@\n+// Definitions for JustBoom Digi\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&i2s>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&i2c1>;\n+\t\t__overlay__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\twm8804@3b {\n+\t\t\t\t#sound-dai-cells = <0>;\n+\t\t\t\tcompatible = \"wlf,wm8804\";\n+\t\t\t\treg = <0x3b>;\n+\t\t\t\tPVDD-supply = <&vdd_3v3_reg>;\n+\t\t\t\tDVDD-supply = <&vdd_3v3_reg>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&sound>;\n+\t\t__overlay__ {\n+\t\t\tcompatible = \"justboom,justboom-digi\";\n+\t\t\ti2s-controller = <&i2s>;\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/ltc294x-overlay.dts b/arch/arm/boot/dts/overlays/ltc294x-overlay.dts\nnew file mode 100644\nindex 000000000000..6d971f3649ca\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/ltc294x-overlay.dts\n@@ -0,0 +1,86 @@\n+/dts-v1/;\n+/plugin/;\n+\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&i2c_arm>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tltc2941: ltc2941@64 {\n+\t\t\t\tcompatible = \"lltc,ltc2941\";\n+\t\t\t\treg = <0x64>;\n+\t\t\t\tlltc,resistor-sense = <50>;\n+\t\t\t\tlltc,prescaler-exponent = <7>; \n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&i2c_arm>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tltc2942: ltc2942@64 {\n+\t\t\t\tcompatible = \"lltc,ltc2942\";\n+\t\t\t\treg = <0x64>;\n+\t\t\t\tlltc,resistor-sense = <50>;\n+\t\t\t\tlltc,prescaler-exponent = <7>; \n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&i2c_arm>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tltc2943: ltc2943@64 {\n+\t\t\t\tcompatible = \"lltc,ltc2943\";\n+\t\t\t\treg = <0x64>;\n+\t\t\t\tlltc,resistor-sense = <50>;\n+\t\t\t\tlltc,prescaler-exponent = <7>; \n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@3 {\n+\t\ttarget = <&i2c_arm>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tltc2944: ltc2944@64 {\n+\t\t\t\tcompatible = \"lltc,ltc2944\";\n+\t\t\t\treg = <0x64>;\n+\t\t\t\tlltc,resistor-sense = <50>;\n+\t\t\t\tlltc,prescaler-exponent = <7>; \n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\tltc2941 = <0>,\"+0\";\n+\t\tltc2942 = <0>,\"+1\";\n+\t\tltc2943 = <0>,\"+2\";\n+\t\tltc2944 = <0>,\"+3\";\n+\t\tresistor-sense = <&ltc2941>, \"lltc,resistor-sense:0\",\n+\t\t\t         <&ltc2942>, \"lltc,resistor-sense:0\",\n+\t\t\t\t <&ltc2943>, \"lltc,resistor-sense:0\",\n+\t\t\t\t <&ltc2944>, \"lltc,resistor-sense:0\";\n+\t\tprescaler-exponent = <&ltc2941>, \"lltc,prescaler-exponent:0\",\n+\t\t\t         <&ltc2942>, \"lltc,prescaler-exponent:0\",\n+\t\t\t\t <&ltc2943>, \"lltc,prescaler-exponent:0\",\n+\t\t\t\t <&ltc2944>, \"lltc,prescaler-exponent:0\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/max98357a-overlay.dts b/arch/arm/boot/dts/overlays/max98357a-overlay.dts\nnew file mode 100644\nindex 000000000000..9e2afb05b7cb\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/max98357a-overlay.dts\n@@ -0,0 +1,84 @@\n+// Overlay for Maxim MAX98357A audio DAC\n+\n+// dtparams:\n+//     no-sdmode  - SD_MODE pin not managed by driver.\n+//     sdmode-pin - Specify GPIO pin to which SD_MODE is connected (default 4).\n+\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\t/* Enable I2S */\n+\tfragment@0 {\n+\t\ttarget = <&i2s>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\t/* DAC whose SD_MODE pin is managed by driver (via GPIO pin) */\n+\tfragment@1 {\n+\t\ttarget-path = \"/\";\n+\t\t__overlay__ {\n+\t\t\tmax98357a_dac: max98357a {\n+\t\t\t\tcompatible = \"maxim,max98357a\";\n+\t\t\t\t#sound-dai-cells = <0>;\n+\t\t\t\tsdmode-gpios = <&gpio 4 0>;   /* 2nd word overwritten by sdmode-pin parameter */\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t/* DAC whose SD_MODE pin is not managed by driver */\n+\tfragment@2 {\n+\t\ttarget-path = \"/\";\n+\t\t__dormant__ {\n+\t\t\tmax98357a_nsd: max98357a {\n+\t\t\t\tcompatible = \"maxim,max98357a\";\n+\t\t\t\t#sound-dai-cells = <0>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t/* Soundcard connecting I2S to DAC with SD_MODE */\n+\tfragment@3 {\n+\t\ttarget = <&sound>;\n+\t\t__overlay__ {\n+\t\t\tcompatible = \"simple-audio-card\";\n+\t\t\tsimple-audio-card,format = \"i2s\";\n+\t\t\tsimple-audio-card,name = \"MAX98357A\";\n+\t\t\tstatus = \"okay\";\n+\t\t\tsimple-audio-card,cpu {\n+\t\t\t\tsound-dai = <&i2s>;\n+\t\t\t};\n+\t\t\tsimple-audio-card,codec {\n+\t\t\t\tsound-dai = <&max98357a_dac>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t/* Soundcard connecting I2S to DAC without SD_MODE */\n+\tfragment@4 {\n+\t\ttarget = <&sound>;\n+\t\t__dormant__ {\n+\t\t\tcompatible = \"simple-audio-card\";\n+\t\t\tsimple-audio-card,format = \"i2s\";\n+\t\t\tsimple-audio-card,name = \"MAX98357A\";\n+\t\t\tstatus = \"okay\";\n+\t\t\tsimple-audio-card,cpu {\n+\t\t\t\tsound-dai = <&i2s>;\n+\t\t\t};\n+\t\t\tsimple-audio-card,codec {\n+\t\t\t\tsound-dai = <&max98357a_nsd>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\tno-sdmode  = <0>,\"-1+2-3+4\";\n+\t\tsdmode-pin = <&max98357a_dac>,\"sdmode-gpios:4\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/maxtherm-overlay.dts b/arch/arm/boot/dts/overlays/maxtherm-overlay.dts\nnew file mode 100644\nindex 000000000000..34d5727069ec\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/maxtherm-overlay.dts\n@@ -0,0 +1,166 @@\n+/*\n+ * Universal device tree overlay for SPI devices\n+ */\n+\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&spidev0>;\n+\t\t__dormant__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&spidev1>;\n+\t\t__dormant__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget-path = \"spi1/spidev@0\";\n+\t\t__dormant__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\tfragment@3 {\n+\t\ttarget-path = \"spi1/spidev@1\";\n+\t\t__dormant__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\tfragment@4 {\n+\t\ttarget-path = \"spi1/spidev@2\";\n+\t\t__dormant__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\tfragment@5 {\n+\t\ttarget-path = \"spi2/spidev@0\";\n+\t\t__dormant__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\tfragment@6 {\n+\t\ttarget-path = \"spi2/spidev@1\";\n+\t\t__dormant__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\tfragment@7 {\n+\t\ttarget-path = \"spi2/spidev@2\";\n+\t\t__dormant__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\tmaxfrag: fragment@8 {\n+\t\ttarget = <&spi0>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tmax: maxtherm@0 {\n+\t\t\t\tcompatible = \"maxim,max6675\";\n+\t\t\t\treg = <0>;\n+\t\t\t\tspi-max-frequency = <500000>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@9 {\n+\t\ttarget = <&max>;\n+\t\t__dormant__ {\n+\t\t\tcompatible = \"maxim,max31855e\", \"maxim,max31855\";\n+\t\t};\n+\t};\n+\n+\tfragment@10 {\n+\t\ttarget = <&max>;\n+\t\t__dormant__ {\n+\t\t\tcompatible = \"maxim,max31855j\", \"maxim,max31855\";\n+\t\t};\n+\t};\n+\n+\tfragment@11 {\n+\t\ttarget = <&max>;\n+\t\t__dormant__ {\n+\t\t\tcompatible = \"maxim,max31855k\", \"maxim,max31855\";\n+\t\t};\n+\t};\n+\n+\tfragment@12 {\n+\t\ttarget = <&max>;\n+\t\t__dormant__ {\n+\t\t\tcompatible = \"maxim,max31855n\", \"maxim,max31855\";\n+\t\t};\n+\t};\n+\n+\tfragment@13 {\n+\t\ttarget = <&max>;\n+\t\t__dormant__ {\n+\t\t\tcompatible = \"maxim,max31855r\", \"maxim,max31855\";\n+\t\t};\n+\t};\n+\n+\tfragment@14 {\n+\t\ttarget = <&max>;\n+\t\t__dormant__ {\n+\t\t\tcompatible = \"maxim,max31855s\", \"maxim,max31855\";\n+\t\t};\n+\t};\n+\n+\tfragment@15 {\n+\t\ttarget = <&max>;\n+\t\t__dormant__ {\n+\t\t\tcompatible = \"maxim,max31855t\", \"maxim,max31855\";\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\tspi0-0 = <0>, \"+0\",\n+\t\t\t <&maxfrag>,\"target:0=\",<&spi0>,\n+\t\t\t <&max>,\"reg:0=0\";\n+\t\tspi0-1 = <0>, \"+1\",\n+\t\t\t <&maxfrag>,\"target:0=\",<&spi0>,\n+\t\t\t <&max>,\"reg:0=1\";\n+\t\tspi1-0 = <0>, \"+2\",\n+\t\t\t <&maxfrag>,\"target:0=\",<&spi1>,\n+\t\t\t <&max>,\"reg:0=0\";\n+\t\tspi1-1 = <0>, \"+3\",\n+\t\t\t <&maxfrag>,\"target:0=\",<&spi1>,\n+\t\t\t <&max>,\"reg:0=1\";\n+\t\tspi1-2 = <0>, \"+4\",\n+\t\t\t <&maxfrag>,\"target:0=\",<&spi1>,\n+\t\t\t <&max>,\"reg:0=2\";\n+\t\tspi2-0 = <0>, \"+5\",\n+\t\t\t <&maxfrag>,\"target:0=\",<&spi2>,\n+\t\t\t <&max>,\"reg:0=0\";\n+\t\tspi2-1 = <0>, \"+6\",\n+\t\t\t <&maxfrag>,\"target:0=\",<&spi2>,\n+\t\t\t <&max>,\"reg:0=1\";\n+\t\tspi2-2 = <0>, \"+7\",\n+\t\t\t <&maxfrag>,\"target:0=\",<&spi2>,\n+\t\t\t <&max>,\"reg:0=2\";\n+\t\tmax6675 = <&max>,\"compatible=maxim,max6675\";\n+\t\tmax31855 = <&max>,\"compatible=maxim,max31855\";\n+\t\tmax31855e = <0>,\"+9\";\n+\t\tmax31855j = <0>,\"+10\";\n+\t\tmax31855k = <0>,\"+11\";\n+\t\tmax31855n = <0>,\"+12\";\n+\t\tmax31855r = <0>,\"+13\";\n+\t\tmax31855s = <0>,\"+14\";\n+\t\tmax31855t = <0>,\"+15\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/mbed-dac-overlay.dts b/arch/arm/boot/dts/overlays/mbed-dac-overlay.dts\nnew file mode 100644\nindex 000000000000..840dd9b31db4\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/mbed-dac-overlay.dts\n@@ -0,0 +1,64 @@\n+// Definitions for mbed DAC\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&i2s>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&i2c1>;\n+\t\t__overlay__ {\n+\t\t\t#address-cells = <1>;\n+                        #size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\ttlv320aic23: codec@1a {\n+\t\t\t\t#sound-dai-cells = <0>;\n+\t\t\t\treg = <0x1a>;\n+\t\t\t\tcompatible = \"ti,tlv320aic23\";\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&sound>;\n+\t\t__overlay__ {\n+\t\t\tcompatible = \"simple-audio-card\";\n+\t\t\ti2s-controller = <&i2s>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tsimple-audio-card,name = \"mbed-DAC\";\n+\n+\t\t\tsimple-audio-card,widgets =\n+\t\t\t\t\"Microphone\", \"Mic Jack\",\n+\t\t\t\t\"Line\", \"Line In\",\n+\t\t\t\t\"Headphone\", \"Headphone Jack\";\n+\n+\t\t\tsimple-audio-card,routing =\n+\t\t\t\t\"Headphone Jack\", \"LHPOUT\",\n+\t\t\t\t\"Headphone Jack\", \"RHPOUT\",\n+\t\t\t\t\"LLINEIN\", \"Line In\",\n+\t\t\t\t\"RLINEIN\", \"Line In\",\n+\t\t\t\t\"MICIN\", \"Mic Jack\";\n+\n+\t\t\tsimple-audio-card,format = \"i2s\";\n+\n+\t\t\tsimple-audio-card,cpu {\n+\t\t\t\tsound-dai = <&i2s>;\n+\t\t\t};\n+\n+\t\t\tsound_master: simple-audio-card,codec {\n+\t\t\t\tsound-dai = <&tlv320aic23>;\n+\t\t\t\tsystem-clock-frequency = <12288000>;\n+\t\t\t};\n+\t\t};\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/mcp23017-overlay.dts b/arch/arm/boot/dts/overlays/mcp23017-overlay.dts\nnew file mode 100644\nindex 000000000000..c546d8ba7e6d\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/mcp23017-overlay.dts\n@@ -0,0 +1,69 @@\n+// Definitions for MCP23017 Gpio Extender from Microchip Semiconductor\n+\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&i2c1>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&gpio>;\n+\t\t__overlay__ {\n+\t\t\tmcp23017_pins: mcp23017_pins@20 {\n+\t\t\t\tbrcm,pins = <4>;\n+\t\t\t\tbrcm,function = <0>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&i2c1>;\n+\t\t__overlay__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tmcp23017: mcp@20 {\n+\t\t\t\tcompatible = \"microchip,mcp23017\";\n+\t\t\t\treg = <0x20>;\n+\t\t\t\tgpio-controller;\n+\t\t\t\t#gpio-cells = <2>;\n+\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@3 {\n+\t\ttarget = <&mcp23017>;\n+\t\t__dormant__ {\n+\t\t\tcompatible = \"microchip,mcp23008\";\n+\t\t};\n+\t};\n+\n+\tfragment@4 {\n+\t\ttarget = <&mcp23017>;\n+\t\tmcp23017_irq: __overlay__ {\n+\t\t\t#interrupt-cells=<2>;\n+\t\t\tinterrupt-parent = <&gpio>;\n+\t\t\tinterrupts = <4 2>;\n+\t\t\tinterrupt-controller;\n+\t\t\tmicrochip,irq-mirror;\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\tgpiopin = <&mcp23017_pins>,\"brcm,pins:0\",\n+\t\t\t\t<&mcp23017_irq>,\"interrupts:0\";\n+\t\taddr = <&mcp23017>,\"reg:0\", <&mcp23017_pins>,\"reg:0\";\n+\t\tmcp23008 = <0>,\"=3\";\n+\t\tnoints = <0>,\"!1!4\";\n+\t};\n+};\n+\ndiff --git a/arch/arm/boot/dts/overlays/mcp23s17-overlay.dts b/arch/arm/boot/dts/overlays/mcp23s17-overlay.dts\nnew file mode 100644\nindex 000000000000..484d64b225fb\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/mcp23s17-overlay.dts\n@@ -0,0 +1,732 @@\n+// Overlay for MCP23S08/17 GPIO Extenders from Microchip Semiconductor\n+\n+// dtparams:\n+//     s08-spi<n>-<m>-present  - 4-bit integer, bitmap indicating MCP23S08 devices present on SPI<n>, CS#<m>.\n+//     s17-spi<n>-<m>-present  - 8-bit integer, bitmap indicating MCP23S17 devices present on SPI<n>, CS#<m>.\n+//     s08-spi<n>-<m>-int-gpio - integer, enables interrupts on a single MCP23S08 device on SPI<n>, CS#<m>, specifies the GPIO pin to which INT output is connected.\n+//     s17-spi<n>-<m>-int-gpio - integer, enables mirrored interrupts on a single MCP23S17 device on SPI<n>, CS#<m>, specifies the GPIO pin to which either INTA or INTB output is connected.\n+//\n+// If devices are present on SPI1 or SPI2, those interfaces must be enabled with one of the spi1-1/2/3cs and/or spi2-1/2/3cs overlays.\n+// If interrupts are enabled for a device on a given CS# on a SPI bus, that device must be the only one present on that SPI bus/CS#.\n+//\n+// Example 1: A single MCP23S17 device on SPI0, CS#0 with its SPI addr set to 0 and INTA output connected to GPIO25:\n+// dtoverlay=mcp23s17:s17-spi0-0-present=1,s17-spi0-0-int-gpio=25\n+//\n+// Example 2: Two MCP23S08 devices on SPI1, CS#0 with their addrs set to 2 and 3. Three MCP23S17 devices on SPI1, CS#1 with their addrs set to 0, 1 and 7:\n+// dtoverlay=spi1-2cs\n+// dtoverlay=mcp23s17:s08-spi1-0-present=12,s17-spi1-1-present=131\n+\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\t// disable spi-dev on spi0.0\n+\tfragment@0 {\n+\t\ttarget = <&spidev0>;\n+\t\t__dormant__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\t// disable spi-dev on spi0.1\n+\tfragment@1 {\n+\t\ttarget = <&spidev1>;\n+\t\t__dormant__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\t// disable spi-dev on spi1.0\n+\tfragment@2 {\n+\t\ttarget-path = \"spi1/spidev@0\";\n+\t\t__dormant__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\t// disable spi-dev on spi1.1\n+\tfragment@3 {\n+\t\ttarget-path = \"spi1/spidev@1\";\n+\t\t__dormant__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\t// disable spi-dev on spi1.2\n+\tfragment@4 {\n+\t\ttarget-path = \"spi1/spidev@2\";\n+\t\t__dormant__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\t// disable spi-dev on spi2.0\n+\tfragment@5 {\n+\t\ttarget-path = \"spi2/spidev@0\";\n+\t\t__dormant__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\t// disable spi-dev on spi2.1\n+\tfragment@6 {\n+\t\ttarget-path = \"spi2/spidev@1\";\n+\t\t__dormant__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\t// disable spi-dev on spi2.2\n+\tfragment@7 {\n+\t\ttarget-path = \"spi2/spidev@2\";\n+\t\t__dormant__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\t// enable one or more mcp23s08s on spi0.0\n+\tfragment@8 {\n+\t\ttarget = <&spi0>;\n+\t\t__dormant__ {\n+\t\t\tstatus = \"okay\";\n+                        #address-cells = <1>;\n+                        #size-cells = <0>;\n+\t\t\tmcp23s08_00: mcp23s08@0 {\n+\t\t\t\tcompatible = \"microchip,mcp23s08\";\n+  \t\t\t\tgpio-controller;\n+  \t\t\t\t#gpio-cells = <2>;\n+    \t\t\t\tmicrochip,spi-present-mask = <0x00>;  /* overwritten by mcp23s08-spi0-0-present parameter */\n+     \t\t\t\treg = <0>;\n+    \t\t\t\tspi-max-frequency = <500000>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t\t#interrupt-cells=<2>;\n+\t\t\t\tinterrupts = <0 2>;  /* 1st word overwritten by mcp23s08-spi0-0-int-gpio parameter */\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t// enable one or more mcp23s08s on spi0.1\n+\tfragment@9 {\n+\t\ttarget = <&spi0>;\n+\t\t__dormant__ {\n+\t\t\tstatus = \"okay\";\n+                        #address-cells = <1>;\n+                        #size-cells = <0>;\n+\t\t\tmcp23s08_01: mcp23s08@1 {\n+\t\t\t\tcompatible = \"microchip,mcp23s08\";\n+  \t\t\t\tgpio-controller;\n+  \t\t\t\t#gpio-cells = <2>;\n+    \t\t\t\tmicrochip,spi-present-mask = <0x00>;  /* overwritten by mcp23s08-spi0-1-present parameter */\n+     \t\t\t\treg = <1>;\n+    \t\t\t\tspi-max-frequency = <500000>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t\t#interrupt-cells=<2>;\n+\t\t\t\tinterrupts = <0 2>;  /* 1st word overwritten by mcp23s08-spi0-1-int-gpio parameter */\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t// enable one or more mcp23s08s on spi1.0\n+\tfragment@10 {\n+\t\ttarget = <&spi1>;\n+\t\t__dormant__ {\n+\t\t\tstatus = \"okay\";\n+                        #address-cells = <1>;\n+                        #size-cells = <0>;\n+\t\t\tmcp23s08_10: mcp23s08@0 {\n+\t\t\t\tcompatible = \"microchip,mcp23s08\";\n+  \t\t\t\tgpio-controller;\n+  \t\t\t\t#gpio-cells = <2>;\n+    \t\t\t\tmicrochip,spi-present-mask = <0x00>;  /* overwritten by mcp23s08-spi1-0-present parameter */\n+     \t\t\t\treg = <0>;\n+    \t\t\t\tspi-max-frequency = <500000>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t\t#interrupt-cells=<2>;\n+\t\t\t\tinterrupts = <0 2>;  /* 1st word overwritten by mcp23s08-spi1-0-int-gpio parameter */\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t// enable one or more mcp23s08s on spi1.1\n+\tfragment@11 {\n+\t\ttarget = <&spi1>;\n+\t\t__dormant__ {\n+\t\t\tstatus = \"okay\";\n+                        #address-cells = <1>;\n+                        #size-cells = <0>;\n+\t\t\tmcp23s08_11: mcp23s08@1 {\n+\t\t\t\tcompatible = \"microchip,mcp23s08\";\n+  \t\t\t\tgpio-controller;\n+  \t\t\t\t#gpio-cells = <2>;\n+    \t\t\t\tmicrochip,spi-present-mask = <0x00>;  /* overwritten by mcp23s08-spi1-1-present parameter */\n+     \t\t\t\treg = <1>;\n+    \t\t\t\tspi-max-frequency = <500000>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t\t#interrupt-cells=<2>;\n+\t\t\t\tinterrupts = <0 2>;  /* 1st word overwritten by mcp23s08-spi1-1-int-gpio parameter */\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t// enable one or more mcp23s08s on spi1.2\n+\tfragment@12 {\n+\t\ttarget = <&spi1>;\n+\t\t__dormant__ {\n+\t\t\tstatus = \"okay\";\n+                        #address-cells = <1>;\n+                        #size-cells = <0>;\n+\t\t\tmcp23s08_12: mcp23s08@2 {\n+\t\t\t\tcompatible = \"microchip,mcp23s08\";\n+  \t\t\t\tgpio-controller;\n+  \t\t\t\t#gpio-cells = <2>;\n+    \t\t\t\tmicrochip,spi-present-mask = <0x00>;  /* overwritten by mcp23s08-spi1-2-present parameter */\n+     \t\t\t\treg = <2>;\n+    \t\t\t\tspi-max-frequency = <500000>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t\t#interrupt-cells=<2>;\n+\t\t\t\tinterrupts = <0 2>;  /* 1st word overwritten by mcp23s08-spi1-2-int-gpio parameter */\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t// enable one or more mcp23s08s on spi2.0\n+\tfragment@13 {\n+\t\ttarget = <&spi2>;\n+\t\t__dormant__ {\n+\t\t\tstatus = \"okay\";\n+                        #address-cells = <1>;\n+                        #size-cells = <0>;\n+\t\t\tmcp23s08_20: mcp23s08@0 {\n+\t\t\t\tcompatible = \"microchip,mcp23s08\";\n+  \t\t\t\tgpio-controller;\n+  \t\t\t\t#gpio-cells = <2>;\n+    \t\t\t\tmicrochip,spi-present-mask = <0x00>;  /* overwritten by mcp23s08-spi2-0-present parameter */\n+     \t\t\t\treg = <0>;\n+    \t\t\t\tspi-max-frequency = <500000>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t\t#interrupt-cells=<2>;\n+\t\t\t\tinterrupts = <0 2>;  /* 1st word overwritten by mcp23s08-spi2-0-int-gpio parameter */\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t// enable one or more mcp23s08s on spi2.1\n+\tfragment@14 {\n+\t\ttarget = <&spi2>;\n+\t\t__dormant__ {\n+\t\t\tstatus = \"okay\";\n+                        #address-cells = <1>;\n+                        #size-cells = <0>;\n+\t\t\tmcp23s08_21: mcp23s08@1 {\n+\t\t\t\tcompatible = \"microchip,mcp23s08\";\n+  \t\t\t\tgpio-controller;\n+  \t\t\t\t#gpio-cells = <2>;\n+    \t\t\t\tmicrochip,spi-present-mask = <0x00>;  /* overwritten by mcp23s08-spi2-1-present parameter */\n+     \t\t\t\treg = <1>;\n+    \t\t\t\tspi-max-frequency = <500000>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t\t#interrupt-cells=<2>;\n+\t\t\t\tinterrupts = <0 2>;  /* 1st word overwritten by mcp23s08-spi2-1-int-gpio parameter */\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t// enable one or more mcp23s08s on spi2.2\n+\tfragment@15 {\n+\t\ttarget = <&spi2>;\n+\t\t__dormant__ {\n+\t\t\tstatus = \"okay\";\n+                        #address-cells = <1>;\n+                        #size-cells = <0>;\n+\t\t\tmcp23s08_22: mcp23s08@2 {\n+\t\t\t\tcompatible = \"microchip,mcp23s08\";\n+  \t\t\t\tgpio-controller;\n+  \t\t\t\t#gpio-cells = <2>;\n+    \t\t\t\tmicrochip,spi-present-mask = <0x00>;  /* overwritten by mcp23s08-spi2-2-present parameter */\n+     \t\t\t\treg = <2>;\n+    \t\t\t\tspi-max-frequency = <500000>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t\t#interrupt-cells=<2>;\n+\t\t\t\tinterrupts = <0 2>;  /* 1st word overwritten by mcp23s08-spi2-2-int-gpio parameter */\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t// enable one or more mcp23s17s on spi0.0\n+\tfragment@16 {\n+\t\ttarget = <&spi0>;\n+\t\t__dormant__ {\n+\t\t\tstatus = \"okay\";\n+                        #address-cells = <1>;\n+                        #size-cells = <0>;\n+\t\t\tmcp23s17_00: mcp23s17@0 {\n+\t\t\t\tcompatible = \"microchip,mcp23s17\";\n+  \t\t\t\tgpio-controller;\n+  \t\t\t\t#gpio-cells = <2>;\n+    \t\t\t\tmicrochip,spi-present-mask = <0x00>;  /* overwritten by mcp23s17-spi0-0-present parameter */\n+     \t\t\t\treg = <0>;\n+    \t\t\t\tspi-max-frequency = <500000>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t\t#interrupt-cells=<2>;\n+\t\t\t\tinterrupts = <0 2>;  /* 1st word overwritten by mcp23s17-spi0-0-int-gpio parameter */\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t// enable one or more mcp23s17s on spi0.1\n+\tfragment@17 {\n+\t\ttarget = <&spi0>;\n+\t\t__dormant__ {\n+\t\t\tstatus = \"okay\";\n+                        #address-cells = <1>;\n+                        #size-cells = <0>;\n+\t\t\tmcp23s17_01: mcp23s17@1 {\n+\t\t\t\tcompatible = \"microchip,mcp23s17\";\n+  \t\t\t\tgpio-controller;\n+  \t\t\t\t#gpio-cells = <2>;\n+    \t\t\t\tmicrochip,spi-present-mask = <0x00>;  /* overwritten by mcp23s17-spi0-1-present parameter */\n+     \t\t\t\treg = <1>;\n+    \t\t\t\tspi-max-frequency = <500000>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t\t#interrupt-cells=<2>;\n+\t\t\t\tinterrupts = <0 2>;  /* 1st word overwritten by mcp23s17-spi0-1-int-gpio parameter */\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t// enable one or more mcp23s17s on spi1.0\n+\tfragment@18 {\n+\t\ttarget = <&spi1>;\n+\t\t__dormant__ {\n+\t\t\tstatus = \"okay\";\n+                        #address-cells = <1>;\n+                        #size-cells = <0>;\n+\t\t\tmcp23s17_10: mcp23s17@0 {\n+\t\t\t\tcompatible = \"microchip,mcp23s17\";\n+  \t\t\t\tgpio-controller;\n+  \t\t\t\t#gpio-cells = <2>;\n+    \t\t\t\tmicrochip,spi-present-mask = <0x00>;  /* overwritten by mcp23s17-spi1-0-present parameter */\n+     \t\t\t\treg = <0>;\n+    \t\t\t\tspi-max-frequency = <500000>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t\t#interrupt-cells=<2>;\n+\t\t\t\tinterrupts = <0 2>;  /* 1st word overwritten by mcp23s17-spi1-0-int-gpio parameter */\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t// enable one or more mcp23s17s on spi1.1\n+\tfragment@19 {\n+\t\ttarget = <&spi1>;\n+\t\t__dormant__ {\n+\t\t\tstatus = \"okay\";\n+                        #address-cells = <1>;\n+                        #size-cells = <0>;\n+\t\t\tmcp23s17_11: mcp23s17@1 {\n+\t\t\t\tcompatible = \"microchip,mcp23s17\";\n+  \t\t\t\tgpio-controller;\n+  \t\t\t\t#gpio-cells = <2>;\n+    \t\t\t\tmicrochip,spi-present-mask = <0x00>;  /* overwritten by mcp23s17-spi1-1-present parameter */\n+     \t\t\t\treg = <1>;\n+    \t\t\t\tspi-max-frequency = <500000>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t\t#interrupt-cells=<2>;\n+\t\t\t\tinterrupts = <0 2>;  /* 1st word overwritten by mcp23s17-spi1-1-int-gpio parameter */\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t// enable one or more mcp23s17s on spi1.2\n+\tfragment@20 {\n+\t\ttarget = <&spi1>;\n+\t\t__dormant__ {\n+\t\t\tstatus = \"okay\";\n+                        #address-cells = <1>;\n+                        #size-cells = <0>;\n+\t\t\tmcp23s17_12: mcp23s17@2 {\n+\t\t\t\tcompatible = \"microchip,mcp23s17\";\n+  \t\t\t\tgpio-controller;\n+  \t\t\t\t#gpio-cells = <2>;\n+    \t\t\t\tmicrochip,spi-present-mask = <0x00>;  /* overwritten by mcp23s17-spi1-2-present parameter */\n+     \t\t\t\treg = <2>;\n+    \t\t\t\tspi-max-frequency = <500000>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t\t#interrupt-cells=<2>;\n+\t\t\t\tinterrupts = <0 2>;  /* 1st word overwritten by mcp23s17-spi1-2-int-gpio parameter */\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t// enable one or more mcp23s17s on spi2.0\n+\tfragment@21 {\n+\t\ttarget = <&spi2>;\n+\t\t__dormant__ {\n+\t\t\tstatus = \"okay\";\n+                        #address-cells = <1>;\n+                        #size-cells = <0>;\n+\t\t\tmcp23s17_20: mcp23s17@0 {\n+\t\t\t\tcompatible = \"microchip,mcp23s17\";\n+  \t\t\t\tgpio-controller;\n+  \t\t\t\t#gpio-cells = <2>;\n+    \t\t\t\tmicrochip,spi-present-mask = <0x00>;  /* overwritten by mcp23s17-spi2-0-present parameter */\n+     \t\t\t\treg = <0>;\n+    \t\t\t\tspi-max-frequency = <500000>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t\t#interrupt-cells=<2>;\n+\t\t\t\tinterrupts = <0 2>;  /* 1st word overwritten by mcp23s17-spi2-0-int-gpio parameter */\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t// enable one or more mcp23s17s on spi2.1\n+\tfragment@22 {\n+\t\ttarget = <&spi2>;\n+\t\t__dormant__ {\n+\t\t\tstatus = \"okay\";\n+                        #address-cells = <1>;\n+                        #size-cells = <0>;\n+\t\t\tmcp23s17_21: mcp23s17@1 {\n+\t\t\t\tcompatible = \"microchip,mcp23s17\";\n+  \t\t\t\tgpio-controller;\n+  \t\t\t\t#gpio-cells = <2>;\n+    \t\t\t\tmicrochip,spi-present-mask = <0x00>;  /* overwritten by mcp23s17-spi2-1-present parameter */\n+     \t\t\t\treg = <1>;\n+    \t\t\t\tspi-max-frequency = <500000>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t\t#interrupt-cells=<2>;\n+\t\t\t\tinterrupts = <0 2>;  /* 1st word overwritten by mcp23s17-spi2-1-int-gpio parameter */\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t// enable one or more mcp23s17s on spi2.2\n+\tfragment@23 {\n+\t\ttarget = <&spi2>;\n+\t\t__dormant__ {\n+\t\t\tstatus = \"okay\";\n+                        #address-cells = <1>;\n+                        #size-cells = <0>;\n+\t\t\tmcp23s17_22: mcp23s17@2 {\n+\t\t\t\tcompatible = \"microchip,mcp23s17\";\n+  \t\t\t\tgpio-controller;\n+  \t\t\t\t#gpio-cells = <2>;\n+    \t\t\t\tmicrochip,spi-present-mask = <0x00>;  /* overwritten by mcp23s17-spi2-2-present parameter */\n+     \t\t\t\treg = <2>;\n+    \t\t\t\tspi-max-frequency = <500000>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t\t#interrupt-cells=<2>;\n+\t\t\t\tinterrupts = <0 2>;  /* 1st word overwritten by mcp23s17-spi2-2-int-gpio parameter */\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t// Configure GPIO pin connected to INT(A/B) output of mcp23s08/17 on spi0.0 as a input with no pull-up/down\n+\tfragment@24 {\n+\t\ttarget = <&gpio>;\n+\t\t__dormant__ {\n+\t\t\tspi0_0_int_pins: spi0_0_int_pins {\n+\t\t\t\tbrcm,pins = <0>;  /* overwritten by mcp23s08/17-spi0-0-int-gpio parameter */\n+\t\t\t\tbrcm,function = <0>;\n+\t\t\t\tbrcm,pull = <0>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t// Configure GPIO pin connected to INT(A/B) output of mcp23s08/17 on spi0.1 as a input with no pull-up/down\n+\tfragment@25 {\n+\t\ttarget = <&gpio>;\n+\t\t__dormant__ {\n+\t\t\tspi0_1_int_pins: spi0_1_int_pins {\n+\t\t\t\tbrcm,pins = <0>;  /* overwritten by mcp23s08/17-spi0-1-int-gpio parameter */\n+\t\t\t\tbrcm,function = <0>;\n+\t\t\t\tbrcm,pull = <0>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t// Configure GPIO pin connected to INT(A/B) output of mcp23s08/17 on spi1.0 as a input with no pull-up/down\n+\tfragment@26 {\n+\t\ttarget = <&gpio>;\n+\t\t__dormant__ {\n+\t\t\tspi1_0_int_pins: spi1_0_int_pins {\n+\t\t\t\tbrcm,pins = <0>;  /* overwritten by mcp23s08/17-spi1-0-int-gpio parameter */\n+\t\t\t\tbrcm,function = <0>;\n+\t\t\t\tbrcm,pull = <0>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t// Configure GPIO pin connected to INT(A/B) output of mcp23s08/17 on spi1.1 as a input with no pull-up/down\n+\tfragment@27 {\n+\t\ttarget = <&gpio>;\n+\t\t__dormant__ {\n+\t\t\tspi1_1_int_pins: spi1_1_int_pins {\n+\t\t\t\tbrcm,pins = <0>;  /* overwritten by mcp23s08/17-spi1-1-int-gpio parameter */\n+\t\t\t\tbrcm,function = <0>;\n+\t\t\t\tbrcm,pull = <0>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t// Configure GPIO pin connected to INT(A/B) output of mcp23s08/17 on spi1.2 as a input with no pull-up/down\n+\tfragment@28 {\n+\t\ttarget = <&gpio>;\n+\t\t__dormant__ {\n+\t\t\tspi1_2_int_pins: spi1_2_int_pins {\n+\t\t\t\tbrcm,pins = <0>;  /* overwritten by mcp23s08/17-spi1-2-int-gpio parameter */\n+\t\t\t\tbrcm,function = <0>;\n+\t\t\t\tbrcm,pull = <0>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t// Configure GPIO pin connected to INT(A/B) output of mcp23s08/17 on spi2.0 as a input with no pull-up/down\n+\tfragment@29 {\n+\t\ttarget = <&gpio>;\n+\t\t__dormant__ {\n+\t\t\tspi2_0_int_pins: spi2_0_int_pins {\n+\t\t\t\tbrcm,pins = <0>;  /* overwritten by mcp23s08/17-spi2-0-int-gpio parameter */\n+\t\t\t\tbrcm,function = <0>;\n+\t\t\t\tbrcm,pull = <0>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t// Configure GPIO pin connected to INT(A/B) output of mcp23s08/17 on spi2.1 as a input with no pull-up/down\n+\tfragment@30 {\n+\t\ttarget = <&gpio>;\n+\t\t__dormant__ {\n+\t\t\tspi2_1_int_pins: spi2_1_int_pins {\n+\t\t\t\tbrcm,pins = <0>;  /* overwritten by mcp23s08/17-spi2-1-int-gpio parameter */\n+\t\t\t\tbrcm,function = <0>;\n+\t\t\t\tbrcm,pull = <0>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t// Configure GPIO pin connected to INT(A/B) output of mcp23s08/17 on spi2.2 as a input with no pull-up/down\n+\tfragment@31 {\n+\t\ttarget = <&gpio>;\n+\t\t__dormant__ {\n+\t\t\tspi2_2_int_pins: spi2_2_int_pins {\n+\t\t\t\tbrcm,pins = <0>;  /* overwritten by mcp23s08/17-spi2-2-int-gpio parameter */\n+\t\t\t\tbrcm,function = <0>;\n+\t\t\t\tbrcm,pull = <0>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t// Enable interrupts for a mcp23s08 on spi0.0.\n+\t// Use default active low interrupt signalling.\n+\tfragment@32 {\n+\t\ttarget = <&mcp23s08_00>;\n+\t\t__dormant__ {\n+\t\t\tinterrupt-parent = <&gpio>;\n+\t\t\tinterrupt-controller;\n+\t\t};\n+\t};\n+\n+\t// Enable interrupts for a mcp23s08 on spi0.1.\n+\t// Use default active low interrupt signalling.\n+\tfragment@33 {\n+\t\ttarget = <&mcp23s08_01>;\n+\t\t__dormant__ {\n+\t\t\tinterrupt-parent = <&gpio>;\n+\t\t\tinterrupt-controller;\n+\t\t};\n+\t};\n+\n+\t// Enable interrupts for a mcp23s08 on spi1.0.\n+\t// Use default active low interrupt signalling.\n+\tfragment@34 {\n+\t\ttarget = <&mcp23s08_10>;\n+\t\t__dormant__ {\n+\t\t\tinterrupt-parent = <&gpio>;\n+\t\t\tinterrupt-controller;\n+\t\t};\n+\t};\n+\n+\t// Enable interrupts for a mcp23s08 on spi1.1.\n+\t// Use default active low interrupt signalling.\n+\tfragment@35 {\n+\t\ttarget = <&mcp23s08_11>;\n+\t\t__dormant__ {\n+\t\t\tinterrupt-parent = <&gpio>;\n+\t\t\tinterrupt-controller;\n+\t\t};\n+\t};\n+\n+\t// Enable interrupts for a mcp23s08 on spi1.2.\n+\t// Use default active low interrupt signalling.\n+\tfragment@36 {\n+\t\ttarget = <&mcp23s08_12>;\n+\t\t__dormant__ {\n+\t\t\tinterrupt-parent = <&gpio>;\n+\t\t\tinterrupt-controller;\n+\t\t};\n+\t};\n+\n+\t// Enable interrupts for a mcp23s08 on spi2.0.\n+\t// Use default active low interrupt signalling.\n+\tfragment@37 {\n+\t\ttarget = <&mcp23s08_20>;\n+\t\t__dormant__ {\n+\t\t\tinterrupt-parent = <&gpio>;\n+\t\t\tinterrupt-controller;\n+\t\t};\n+\t};\n+\n+\t// Enable interrupts for a mcp23s08 on spi2.1.\n+\t// Use default active low interrupt signalling.\n+\tfragment@38 {\n+\t\ttarget = <&mcp23s08_21>;\n+\t\t__dormant__ {\n+\t\t\tinterrupt-parent = <&gpio>;\n+\t\t\tinterrupt-controller;\n+\t\t};\n+\t};\n+\n+\t// Enable interrupts for a mcp23s08 on spi2.2.\n+\t// Use default active low interrupt signalling.\n+\tfragment@39 {\n+\t\ttarget = <&mcp23s08_22>;\n+\t\t__dormant__ {\n+\t\t\tinterrupt-parent = <&gpio>;\n+\t\t\tinterrupt-controller;\n+\t\t};\n+\t};\n+\n+\t// Enable interrupts for a mcp23s17 on spi0.0.\n+\t// Enable mirroring so that either INTA or INTB output of mcp23s17 can be connected to the GPIO pin.\n+\t// Use default active low interrupt signalling.\n+\tfragment@40 {\n+\t\ttarget = <&mcp23s17_00>;\n+\t\t__dormant__ {\n+\t\t\tinterrupt-parent = <&gpio>;\n+\t\t\tinterrupt-controller;\n+\t\t\tmicrochip,irq-mirror;\n+\t\t};\n+\t};\n+\n+\t// Enable interrupts for a mcp23s17 on spi0.1.\n+\t// Enable mirroring so that either INTA or INTB output of mcp23s17 can be connected to the GPIO pin.\n+\t// Configure INTA/B outputs of mcp23s08/17 as active low.\n+\tfragment@41 {\n+\t\ttarget = <&mcp23s17_01>;\n+\t\t__dormant__ {\n+\t\t\tinterrupt-parent = <&gpio>;\n+\t\t\tinterrupt-controller;\n+\t\t\tmicrochip,irq-mirror;\n+\t\t};\n+\t};\n+\n+\t// Enable interrupts for a mcp23s17 on spi1.0.\n+\t// Enable mirroring so that either INTA or INTB output of mcp23s17 can be connected to the GPIO pin.\n+\t// Configure INTA/B outputs of mcp23s08/17 as active low.\n+\tfragment@42 {\n+\t\ttarget = <&mcp23s17_10>;\n+\t\t__dormant__ {\n+\t\t\tinterrupt-parent = <&gpio>;\n+\t\t\tinterrupt-controller;\n+\t\t\tmicrochip,irq-mirror;\n+\t\t};\n+\t};\n+\n+\t// Enable interrupts for a mcp23s17 on spi1.1.\n+\t// Enable mirroring so that either INTA or INTB output of mcp23s17 can be connected to the GPIO pin.\n+\t// Configure INTA/B outputs of mcp23s08/17 as active low.\n+\tfragment@43 {\n+\t\ttarget = <&mcp23s17_11>;\n+\t\t__dormant__ {\n+\t\t\tinterrupt-parent = <&gpio>;\n+\t\t\tinterrupt-controller;\n+\t\t\tmicrochip,irq-mirror;\n+\t\t};\n+\t};\n+\n+\t// Enable interrupts for a mcp23s17 on spi1.2.\n+\t// Enable mirroring so that either INTA or INTB output of mcp23s17 can be connected to the GPIO pin.\n+\t// Configure INTA/B outputs of mcp23s08/17 as active low.\n+\tfragment@44 {\n+\t\ttarget = <&mcp23s17_12>;\n+\t\t__dormant__ {\n+\t\t\tinterrupt-parent = <&gpio>;\n+\t\t\tinterrupt-controller;\n+\t\t\tmicrochip,irq-mirror;\n+\t\t};\n+\t};\n+\n+\t// Enable interrupts for a mcp23s17 on spi2.0.\n+\t// Enable mirroring so that either INTA or INTB output of mcp23s17 can be connected to the GPIO pin.\n+\t// Configure INTA/B outputs of mcp23s08/17 as active low.\n+\tfragment@45 {\n+\t\ttarget = <&mcp23s17_20>;\n+\t\t__dormant__ {\n+\t\t\tinterrupt-parent = <&gpio>;\n+\t\t\tinterrupt-controller;\n+\t\t\tmicrochip,irq-mirror;\n+\t\t};\n+\t};\n+\n+\t// Enable interrupts for a mcp23s17 on spi2.1.\n+\t// Enable mirroring so that either INTA or INTB output of mcp23s17 can be connected to the GPIO pin.\n+\t// Configure INTA/B outputs of mcp23s08/17 as active low.\n+\tfragment@46 {\n+\t\ttarget = <&mcp23s17_21>;\n+\t\t__dormant__ {\n+\t\t\tinterrupt-parent = <&gpio>;\n+\t\t\tinterrupt-controller;\n+\t\t\tmicrochip,irq-mirror;\n+\t\t};\n+\t};\n+\n+\t// Enable interrupts for a mcp23s17 on spi2.2.\n+\t// Enable mirroring so that either INTA or INTB output of mcp23s17 can be connected to the GPIO pin.\n+\t// Configure INTA/B outputs of mcp23s08/17 as active low.\n+\tfragment@47 {\n+\t\ttarget = <&mcp23s17_22>;\n+\t\t__dormant__ {\n+\t\t\tinterrupt-parent = <&gpio>;\n+\t\t\tinterrupt-controller;\n+\t\t\tmicrochip,irq-mirror;\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\ts08-spi0-0-present = <0>,\"+0+8\",  <&mcp23s08_00>,\"microchip,spi-present-mask:0\";\n+\t\ts08-spi0-1-present = <0>,\"+1+9\",  <&mcp23s08_01>,\"microchip,spi-present-mask:0\";\n+\t\ts08-spi1-0-present = <0>,\"+2+10\", <&mcp23s08_10>,\"microchip,spi-present-mask:0\";\n+\t\ts08-spi1-1-present = <0>,\"+3+11\", <&mcp23s08_11>,\"microchip,spi-present-mask:0\";\n+\t\ts08-spi1-2-present = <0>,\"+4+12\", <&mcp23s08_12>,\"microchip,spi-present-mask:0\";\n+\t\ts08-spi2-0-present = <0>,\"+5+13\", <&mcp23s08_20>,\"microchip,spi-present-mask:0\";\n+\t\ts08-spi2-1-present = <0>,\"+6+14\", <&mcp23s08_21>,\"microchip,spi-present-mask:0\";\n+\t\ts08-spi2-2-present = <0>,\"+7+15\", <&mcp23s08_22>,\"microchip,spi-present-mask:0\";\n+\t\ts17-spi0-0-present = <0>,\"+0+16\", <&mcp23s17_00>,\"microchip,spi-present-mask:0\";\n+\t\ts17-spi0-1-present = <0>,\"+1+17\", <&mcp23s17_01>,\"microchip,spi-present-mask:0\";\n+\t\ts17-spi1-0-present = <0>,\"+2+18\", <&mcp23s17_10>,\"microchip,spi-present-mask:0\";\n+\t\ts17-spi1-1-present = <0>,\"+3+19\", <&mcp23s17_11>,\"microchip,spi-present-mask:0\";\n+\t\ts17-spi1-2-present = <0>,\"+4+20\", <&mcp23s17_12>,\"microchip,spi-present-mask:0\";\n+\t\ts17-spi2-0-present = <0>,\"+5+21\", <&mcp23s17_20>,\"microchip,spi-present-mask:0\";\n+\t\ts17-spi2-1-present = <0>,\"+6+22\", <&mcp23s17_21>,\"microchip,spi-present-mask:0\";\n+\t\ts17-spi2-2-present = <0>,\"+7+23\", <&mcp23s17_22>,\"microchip,spi-present-mask:0\";\n+\t\ts08-spi0-0-int-gpio = <0>,\"+24+32\", <&spi0_0_int_pins>,\"brcm,pins:0\", <&mcp23s08_00>,\"interrupts:0\";\n+\t\ts08-spi0-1-int-gpio = <0>,\"+25+33\", <&spi0_1_int_pins>,\"brcm,pins:0\", <&mcp23s08_01>,\"interrupts:0\";\n+\t\ts08-spi1-0-int-gpio = <0>,\"+26+34\", <&spi1_0_int_pins>,\"brcm,pins:0\", <&mcp23s08_10>,\"interrupts:0\";\n+\t\ts08-spi1-1-int-gpio = <0>,\"+27+35\", <&spi1_1_int_pins>,\"brcm,pins:0\", <&mcp23s08_11>,\"interrupts:0\";\n+\t\ts08-spi1-2-int-gpio = <0>,\"+28+36\", <&spi1_2_int_pins>,\"brcm,pins:0\", <&mcp23s08_12>,\"interrupts:0\";\n+\t\ts08-spi2-0-int-gpio = <0>,\"+29+37\", <&spi2_0_int_pins>,\"brcm,pins:0\", <&mcp23s08_20>,\"interrupts:0\";\n+\t\ts08-spi2-1-int-gpio = <0>,\"+30+38\", <&spi2_1_int_pins>,\"brcm,pins:0\", <&mcp23s08_21>,\"interrupts:0\";\n+\t\ts08-spi2-2-int-gpio = <0>,\"+31+39\", <&spi2_2_int_pins>,\"brcm,pins:0\", <&mcp23s08_22>,\"interrupts:0\";\n+\t\ts17-spi0-0-int-gpio = <0>,\"+24+40\", <&spi0_0_int_pins>,\"brcm,pins:0\", <&mcp23s17_00>,\"interrupts:0\";\n+\t\ts17-spi0-1-int-gpio = <0>,\"+25+41\", <&spi0_1_int_pins>,\"brcm,pins:0\", <&mcp23s17_01>,\"interrupts:0\";\n+\t\ts17-spi1-0-int-gpio = <0>,\"+26+42\", <&spi1_0_int_pins>,\"brcm,pins:0\", <&mcp23s17_10>,\"interrupts:0\";\n+\t\ts17-spi1-1-int-gpio = <0>,\"+27+43\", <&spi1_1_int_pins>,\"brcm,pins:0\", <&mcp23s17_11>,\"interrupts:0\";\n+\t\ts17-spi1-2-int-gpio = <0>,\"+28+44\", <&spi1_2_int_pins>,\"brcm,pins:0\", <&mcp23s17_12>,\"interrupts:0\";\n+\t\ts17-spi2-0-int-gpio = <0>,\"+29+45\", <&spi2_0_int_pins>,\"brcm,pins:0\", <&mcp23s17_20>,\"interrupts:0\";\n+\t\ts17-spi2-1-int-gpio = <0>,\"+30+46\", <&spi2_1_int_pins>,\"brcm,pins:0\", <&mcp23s17_21>,\"interrupts:0\";\n+\t\ts17-spi2-2-int-gpio = <0>,\"+31+47\", <&spi2_2_int_pins>,\"brcm,pins:0\", <&mcp23s17_22>,\"interrupts:0\";\n+\t};\n+};\n+\ndiff --git a/arch/arm/boot/dts/overlays/mcp2515-can0-overlay.dts b/arch/arm/boot/dts/overlays/mcp2515-can0-overlay.dts\nnew file mode 100755\nindex 000000000000..46f143d809cc\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/mcp2515-can0-overlay.dts\n@@ -0,0 +1,73 @@\n+/*\n+ * Device tree overlay for mcp251x/can0 on spi0.0\n+ */\n+\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+    compatible = \"brcm,bcm2835\";\n+    /* disable spi-dev for spi0.0 */\n+    fragment@0 {\n+        target = <&spi0>;\n+        __overlay__ {\n+            status = \"okay\";\n+        };\n+    };\n+\n+    fragment@1 {\n+\ttarget = <&spidev0>;\n+\t__overlay__ {\n+\t    status = \"disabled\";\n+\t};\n+    };\n+\n+    /* the interrupt pin of the can-controller */\n+    fragment@2 {\n+        target = <&gpio>;\n+        __overlay__ {\n+            can0_pins: can0_pins {\n+                brcm,pins = <25>;\n+                brcm,function = <0>; /* input */\n+            };\n+        };\n+    };\n+\n+    /* the clock/oscillator of the can-controller */\n+    fragment@3 {\n+        target-path = \"/\";\n+        __overlay__ {\n+            /* external oscillator of mcp2515 on SPI0.0 */\n+            can0_osc: can0_osc {\n+                compatible = \"fixed-clock\";\n+                #clock-cells = <0>;\n+                clock-frequency  = <16000000>;\n+            };\n+        };\n+    };\n+\n+    /* the spi config of the can-controller itself binding everything together */\n+    fragment@4 {\n+        target = <&spi0>;\n+        __overlay__ {\n+            /* needed to avoid dtc warning */\n+            #address-cells = <1>;\n+            #size-cells = <0>;\n+            can0: mcp2515@0 {\n+                reg = <0>;\n+                compatible = \"microchip,mcp2515\";\n+                pinctrl-names = \"default\";\n+                pinctrl-0 = <&can0_pins>;\n+                spi-max-frequency = <10000000>;\n+                interrupt-parent = <&gpio>;\n+                interrupts = <25 8>; /* IRQ_TYPE_LEVEL_LOW */\n+                clocks = <&can0_osc>;\n+            };\n+        };\n+    };\n+    __overrides__ {\n+        oscillator = <&can0_osc>,\"clock-frequency:0\";\n+        spimaxfrequency = <&can0>,\"spi-max-frequency:0\";\n+        interrupt = <&can0_pins>,\"brcm,pins:0\",<&can0>,\"interrupts:0\";\n+    };\n+};\ndiff --git a/arch/arm/boot/dts/overlays/mcp2515-can1-overlay.dts b/arch/arm/boot/dts/overlays/mcp2515-can1-overlay.dts\nnew file mode 100644\nindex 000000000000..0a8dd576818e\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/mcp2515-can1-overlay.dts\n@@ -0,0 +1,73 @@\n+/*\n+ * Device tree overlay for mcp251x/can1 on spi0.1 edited by petit_miner\n+ */\n+\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+    compatible = \"brcm,bcm2835\";\n+    /* disable spi-dev for spi0.1 */\n+    fragment@0 {\n+        target = <&spi0>;\n+        __overlay__ {\n+            status = \"okay\";\n+        };\n+    };\n+\n+    fragment@1 {\n+\ttarget = <&spidev1>;\n+\t__overlay__ {\n+\t    status = \"disabled\";\n+\t};\n+    };\n+\n+    /* the interrupt pin of the can-controller */\n+    fragment@2 {\n+        target = <&gpio>;\n+        __overlay__ {\n+            can1_pins: can1_pins {\n+                brcm,pins = <25>;\n+                brcm,function = <0>; /* input */\n+            };\n+        };\n+    };\n+\n+    /* the clock/oscillator of the can-controller */\n+    fragment@3 {\n+        target-path = \"/\";\n+        __overlay__ {\n+            /* external oscillator of mcp2515 on spi0.1 */\n+            can1_osc: can1_osc {\n+                compatible = \"fixed-clock\";\n+                #clock-cells = <0>;\n+                clock-frequency  = <16000000>;\n+            };\n+        };\n+    };\n+\n+    /* the spi config of the can-controller itself binding everything together */\n+    fragment@4 {\n+        target = <&spi0>;\n+        __overlay__ {\n+            /* needed to avoid dtc warning */\n+            #address-cells = <1>;\n+            #size-cells = <0>;\n+            can1: mcp2515@1 {\n+                reg = <1>;\n+                compatible = \"microchip,mcp2515\";\n+                pinctrl-names = \"default\";\n+                pinctrl-0 = <&can1_pins>;\n+                spi-max-frequency = <10000000>;\n+                interrupt-parent = <&gpio>;\n+                interrupts = <25 8>; /* IRQ_TYPE_LEVEL_LOW */\n+                clocks = <&can1_osc>;\n+            };\n+        };\n+    };\n+    __overrides__ {\n+        oscillator = <&can1_osc>,\"clock-frequency:0\";\n+        spimaxfrequency = <&can1>,\"spi-max-frequency:0\";\n+        interrupt = <&can1_pins>,\"brcm,pins:0\",<&can1>,\"interrupts:0\";\n+    };\n+};\ndiff --git a/arch/arm/boot/dts/overlays/mcp3008-overlay.dts b/arch/arm/boot/dts/overlays/mcp3008-overlay.dts\nnew file mode 100755\nindex 000000000000..957fdb9310af\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/mcp3008-overlay.dts\n@@ -0,0 +1,205 @@\n+/*\n+ * Device tree overlay for Microchip mcp3008 10-Bit A/D Converters\n+ */\n+\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&spidev0>;\n+\t\t__dormant__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&spidev1>;\n+\t\t__dormant__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget-path = \"spi1/spidev@0\";\n+\t\t__dormant__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\tfragment@3 {\n+\t\ttarget-path = \"spi1/spidev@1\";\n+\t\t__dormant__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\tfragment@4 {\n+\t\ttarget-path = \"spi1/spidev@2\";\n+\t\t__dormant__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\tfragment@5 {\n+\t\ttarget-path = \"spi2/spidev@0\";\n+\t\t__dormant__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\tfragment@6 {\n+\t\ttarget-path = \"spi2/spidev@1\";\n+\t\t__dormant__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\tfragment@7 {\n+\t\ttarget-path = \"spi2/spidev@2\";\n+\t\t__dormant__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\tfragment@8 {\n+\t\ttarget = <&spi0>;\n+\t\t__dormant__ {\n+\t\t\tstatus = \"okay\";\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tmcp3008_00: mcp3008@0 {\n+\t\t\t\tcompatible = \"microchip,mcp3008\";\n+\t\t\t\treg = <0>;\n+\t\t\t\tspi-max-frequency = <1600000>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@9 {\n+\t\ttarget = <&spi0>;\n+\t\t__dormant__ {\n+\t\t\tstatus = \"okay\";\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tmcp3008_01: mcp3008@1 {\n+\t\t\t\tcompatible = \"microchip,mcp3008\";\n+\t\t\t\treg = <1>;\n+\t\t\t\tspi-max-frequency = <1600000>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@10 {\n+\t\ttarget = <&spi1>;\n+\t\t__dormant__ {\n+\t\t\tstatus = \"okay\";\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tmcp3008_10: mcp3008@0 {\n+\t\t\t\tcompatible = \"microchip,mcp3008\";\n+\t\t\t\treg = <0>;\n+\t\t\t\tspi-max-frequency = <1600000>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@11 {\n+\t\ttarget = <&spi1>;\n+\t\t__dormant__ {\n+\t\t\tstatus = \"okay\";\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tmcp3008_11: mcp3008@1 {\n+\t\t\t\tcompatible = \"microchip,mcp3008\";\n+\t\t\t\treg = <1>;\n+\t\t\t\tspi-max-frequency = <1600000>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@12 {\n+\t\ttarget = <&spi1>;\n+\t\t__dormant__ {\n+\t\t\tstatus = \"okay\";\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tmcp3008_12: mcp3008@2 {\n+\t\t\t\tcompatible = \"microchip,mcp3008\";\n+\t\t\t\treg = <2>;\n+\t\t\t\tspi-max-frequency = <1600000>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@13 {\n+\t\ttarget = <&spi2>;\n+\t\t__dormant__ {\n+\t\t\tstatus = \"okay\";\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tmcp3008_20: mcp3008@0 {\n+\t\t\t\tcompatible = \"microchip,mcp3008\";\n+\t\t\t\treg = <0>;\n+\t\t\t\tspi-max-frequency = <1600000>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@14 {\n+\t\ttarget = <&spi2>;\n+\t\t__dormant__ {\n+\t\t\tstatus = \"okay\";\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tmcp3008_21: mcp3008@1 {\n+\t\t\t\tcompatible = \"microchip,mcp3008\";\n+\t\t\t\treg = <1>;\n+\t\t\t\tspi-max-frequency = <1600000>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@15 {\n+\t\ttarget = <&spi2>;\n+\t\t__dormant__ {\n+\t\t\tstatus = \"okay\";\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tmcp3008_22: mcp3008@2 {\n+\t\t\t\tcompatible = \"microchip,mcp3008\";\n+\t\t\t\treg = <2>;\n+\t\t\t\tspi-max-frequency = <1600000>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\tspi0-0-present = <0>, \"+0+8\";\n+\t\tspi0-1-present = <0>, \"+1+9\";\n+\t\tspi1-0-present = <0>, \"+2+10\";\n+\t\tspi1-1-present = <0>, \"+3+11\";\n+\t\tspi1-2-present = <0>, \"+4+12\";\n+\t\tspi2-0-present = <0>, \"+5+13\";\n+\t\tspi2-1-present = <0>, \"+6+14\";\n+\t\tspi2-2-present = <0>, \"+7+15\";\n+\t\tspi0-0-speed = <&mcp3008_00>, \"spi-max-frequency:0\";\n+\t\tspi0-1-speed = <&mcp3008_01>, \"spi-max-frequency:0\";\n+\t\tspi1-0-speed = <&mcp3008_10>, \"spi-max-frequency:0\";\n+\t\tspi1-1-speed = <&mcp3008_11>, \"spi-max-frequency:0\";\n+\t\tspi1-2-speed = <&mcp3008_12>, \"spi-max-frequency:0\";\n+\t\tspi2-0-speed = <&mcp3008_20>, \"spi-max-frequency:0\";\n+\t\tspi2-1-speed = <&mcp3008_21>, \"spi-max-frequency:0\";\n+\t\tspi2-2-speed = <&mcp3008_22>, \"spi-max-frequency:0\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/mcp3202-overlay.dts b/arch/arm/boot/dts/overlays/mcp3202-overlay.dts\nnew file mode 100755\nindex 000000000000..8e4e9f60f285\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/mcp3202-overlay.dts\n@@ -0,0 +1,205 @@\n+/*\n+ * Device tree overlay for Microchip mcp3202 12-Bit A/D Converters\n+ */\n+\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&spidev0>;\n+\t\t__dormant__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&spidev1>;\n+\t\t__dormant__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget-path = \"spi1/spidev@0\";\n+\t\t__dormant__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\tfragment@3 {\n+\t\ttarget-path = \"spi1/spidev@1\";\n+\t\t__dormant__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\tfragment@4 {\n+\t\ttarget-path = \"spi1/spidev@2\";\n+\t\t__dormant__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\tfragment@5 {\n+\t\ttarget-path = \"spi2/spidev@0\";\n+\t\t__dormant__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\tfragment@6 {\n+\t\ttarget-path = \"spi2/spidev@1\";\n+\t\t__dormant__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\tfragment@7 {\n+\t\ttarget-path = \"spi2/spidev@2\";\n+\t\t__dormant__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\tfragment@8 {\n+\t\ttarget = <&spi0>;\n+\t\t__dormant__ {\n+\t\t\tstatus = \"okay\";\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tmcp3202_00: mcp3202@0 {\n+\t\t\t\tcompatible = \"mcp3202\";\n+\t\t\t\treg = <0>;\n+\t\t\t\tspi-max-frequency = <1600000>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@9 {\n+\t\ttarget = <&spi0>;\n+\t\t__dormant__ {\n+\t\t\tstatus = \"okay\";\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tmcp3202_01: mcp3202@1 {\n+\t\t\t\tcompatible = \"mcp3202\";\n+\t\t\t\treg = <1>;\n+\t\t\t\tspi-max-frequency = <1600000>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@10 {\n+\t\ttarget = <&spi1>;\n+\t\t__dormant__ {\n+\t\t\tstatus = \"okay\";\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tmcp3202_10: mcp3202@0 {\n+\t\t\t\tcompatible = \"mcp3202\";\n+\t\t\t\treg = <0>;\n+\t\t\t\tspi-max-frequency = <1600000>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@11 {\n+\t\ttarget = <&spi1>;\n+\t\t__dormant__ {\n+\t\t\tstatus = \"okay\";\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tmcp3202_11: mcp3202@1 {\n+\t\t\t\tcompatible = \"mcp3202\";\n+\t\t\t\treg = <1>;\n+\t\t\t\tspi-max-frequency = <1600000>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@12 {\n+\t\ttarget = <&spi1>;\n+\t\t__dormant__ {\n+\t\t\tstatus = \"okay\";\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tmcp3202_12: mcp3202@2 {\n+\t\t\t\tcompatible = \"mcp3202\";\n+\t\t\t\treg = <2>;\n+\t\t\t\tspi-max-frequency = <1600000>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@13 {\n+\t\ttarget = <&spi2>;\n+\t\t__dormant__ {\n+\t\t\tstatus = \"okay\";\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tmcp3202_20: mcp3202@0 {\n+\t\t\t\tcompatible = \"mcp3202\";\n+\t\t\t\treg = <0>;\n+\t\t\t\tspi-max-frequency = <1600000>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@14 {\n+\t\ttarget = <&spi2>;\n+\t\t__dormant__ {\n+\t\t\tstatus = \"okay\";\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tmcp3202_21: mcp3202@1 {\n+\t\t\t\tcompatible = \"mcp3202\";\n+\t\t\t\treg = <1>;\n+\t\t\t\tspi-max-frequency = <1600000>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@15 {\n+\t\ttarget = <&spi2>;\n+\t\t__dormant__ {\n+\t\t\tstatus = \"okay\";\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tmcp3202_22: mcp3202@2 {\n+\t\t\t\tcompatible = \"mcp3202\";\n+\t\t\t\treg = <2>;\n+\t\t\t\tspi-max-frequency = <1600000>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\tspi0-0-present = <0>, \"+0+8\";\n+\t\tspi0-1-present = <0>, \"+1+9\";\n+\t\tspi1-0-present = <0>, \"+2+10\";\n+\t\tspi1-1-present = <0>, \"+3+11\";\n+\t\tspi1-2-present = <0>, \"+4+12\";\n+\t\tspi2-0-present = <0>, \"+5+13\";\n+\t\tspi2-1-present = <0>, \"+6+14\";\n+\t\tspi2-2-present = <0>, \"+7+15\";\n+\t\tspi0-0-speed = <&mcp3202_00>, \"spi-max-frequency:0\";\n+\t\tspi0-1-speed = <&mcp3202_01>, \"spi-max-frequency:0\";\n+\t\tspi1-0-speed = <&mcp3202_10>, \"spi-max-frequency:0\";\n+\t\tspi1-1-speed = <&mcp3202_11>, \"spi-max-frequency:0\";\n+\t\tspi1-2-speed = <&mcp3202_12>, \"spi-max-frequency:0\";\n+\t\tspi2-0-speed = <&mcp3202_20>, \"spi-max-frequency:0\";\n+\t\tspi2-1-speed = <&mcp3202_21>, \"spi-max-frequency:0\";\n+\t\tspi2-2-speed = <&mcp3202_22>, \"spi-max-frequency:0\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/mcp342x-overlay.dts b/arch/arm/boot/dts/overlays/mcp342x-overlay.dts\nnew file mode 100644\nindex 000000000000..714eca5a4b5e\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/mcp342x-overlay.dts\n@@ -0,0 +1,164 @@\n+// Overlay for MCP3421-8 ADCs from Microchip Semiconductor\n+\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&i2c1>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tmcp3421: mcp@68 {\n+\t\t\t\treg = <0x68>;\n+\t\t\t\tcompatible = \"microchip,mcp3421\";\n+\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&i2c1>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tmcp3422: mcp@68 {\n+\t\t\t\treg = <0x68>;\n+\t\t\t\tcompatible = \"microchip,mcp3422\";\n+\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&i2c1>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tmcp3423: mcp@68 {\n+\t\t\t\treg = <0x68>;\n+\t\t\t\tcompatible = \"microchip,mcp3423\";\n+\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@3 {\n+\t\ttarget = <&i2c1>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tmcp3424: mcp@68 {\n+\t\t\t\treg = <0x68>;\n+\t\t\t\tcompatible = \"microchip,mcp3424\";\n+\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@4 {\n+\t\ttarget = <&i2c1>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tmcp3425: mcp@68 {\n+\t\t\t\treg = <0x68>;\n+\t\t\t\tcompatible = \"microchip,mcp3425\",\"mcp3425\";\n+\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@5 {\n+\t\ttarget = <&i2c1>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tmcp3426: mcp@68 {\n+\t\t\t\treg = <0x68>;\n+\t\t\t\tcompatible = \"microchip,mcp3426\";\n+\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@6 {\n+\t\ttarget = <&i2c1>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tmcp3427: mcp@68 {\n+\t\t\t\treg = <0x68>;\n+\t\t\t\tcompatible = \"microchip,mcp3427\";\n+\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@7 {\n+\t\ttarget = <&i2c1>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tmcp3428: mcp@68 {\n+\t\t\t\treg = <0x68>;\n+\t\t\t\tcompatible = \"microchip,mcp3428\";\n+\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\taddr = <&mcp3421>,\"reg:0\",\n+\t\t       <&mcp3422>,\"reg:0\",\n+\t\t       <&mcp3423>,\"reg:0\",\n+\t\t       <&mcp3424>,\"reg:0\",\n+\t\t       <&mcp3425>,\"reg:0\",\n+\t\t       <&mcp3426>,\"reg:0\",\n+\t\t       <&mcp3427>,\"reg:0\",\n+\t\t       <&mcp3428>,\"reg:0\";\n+\t\tmcp3421 = <0>,\"=0\";\n+\t\tmcp3422 = <0>,\"=1\";\n+\t\tmcp3423 = <0>,\"=2\";\n+\t\tmcp3424 = <0>,\"=3\";\n+\t\tmcp3425 = <0>,\"=4\";\n+\t\tmcp3426 = <0>,\"=5\";\n+\t\tmcp3427 = <0>,\"=6\";\n+\t\tmcp3428 = <0>,\"=7\";\n+\t};\n+};\n+\ndiff --git a/arch/arm/boot/dts/overlays/media-center-overlay.dts b/arch/arm/boot/dts/overlays/media-center-overlay.dts\nnew file mode 100644\nindex 000000000000..1b56963f4f16\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/media-center-overlay.dts\n@@ -0,0 +1,134 @@\n+/*\n+ * Device Tree overlay for Media Center HAT by Pi Supply\n+ *\n+ */\n+\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&spi0>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tspidev@0{\n+\t\t\t\tstatus = \"disabled\";\n+\t\t\t};\n+\n+\t\t\tspidev@1{\n+\t\t\t\tstatus = \"disabled\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&gpio>;\n+\t\t__overlay__ {\n+\t\t\trpi_display_pins: rpi_display_pins {\n+\t\t\t\tbrcm,pins = <12 23 24 25>;\n+\t\t\t\tbrcm,function = <1 1 1 0>; /* out out out in */\n+\t\t\t\tbrcm,pull = <0 0 0 2>; /* - - - up */\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&spi0>;\n+\t\t__overlay__ {\n+\t\t\t/* needed to avoid dtc warning */\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\trpidisplay: rpi-display@0{\n+\t\t\t\tcompatible = \"ilitek,ili9341\";\n+\t\t\t\treg = <0>;\n+\t\t\t\tpinctrl-names = \"default\";\n+\t\t\t\tpinctrl-0 = <&rpi_display_pins>;\n+\n+\t\t\t\tspi-max-frequency = <32000000>;\n+\t\t\t\trotate = <90>;\n+\t\t\t\tbgr;\n+\t\t\t\tfps = <30>;\n+\t\t\t\tbuswidth = <8>;\n+\t\t\t\treset-gpios = <&gpio 23 1>;\n+\t\t\t\tdc-gpios = <&gpio 24 0>;\n+\t\t\t\tled-gpios = <&gpio 12 0>;\n+\t\t\t\tdebug = <0>;\n+\t\t\t};\n+\n+\t\t\trpidisplay_ts: rpi-display-ts@1 {\n+\t\t\t\tcompatible = \"ti,ads7846\";\n+\t\t\t\treg = <1>;\n+\n+\t\t\t\tspi-max-frequency = <2000000>;\n+\t\t\t\tinterrupts = <25 2>; /* high-to-low edge triggered */\n+\t\t\t\tinterrupt-parent = <&gpio>;\n+\t\t\t\tpendown-gpio = <&gpio 25 1>;\n+\t\t\t\tti,x-plate-ohms = /bits/ 16 <60>;\n+\t\t\t\tti,pressure-max = /bits/ 16 <255>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@3 {\n+\t\ttarget-path = \"/\";\n+\t\t__overlay__ {\n+\t\t\tlirc_rpi: lirc_rpi {\n+\t\t\t\tcompatible = \"rpi,lirc-rpi\";\n+\t\t\t\tpinctrl-names = \"default\";\n+\t\t\t\tpinctrl-0 = <&lirc_pins>;\n+\t\t\t\tstatus = \"okay\";\n+\n+\t\t\t\t// Override autodetection of IR receiver circuit\n+\t\t\t\t// (0 = active high, 1 = active low, -1 = no override )\n+\t\t\t\trpi,sense = <0xffffffff>;\n+\n+\t\t\t\t// Software carrier\n+\t\t\t\t// (0 = off, 1 = on)\n+\t\t\t\trpi,softcarrier = <1>;\n+\n+\t\t\t\t// Invert output\n+\t\t\t\t// (0 = off, 1 = on)\n+\t\t\t\trpi,invert = <0>;\n+\n+\t\t\t\t// Enable debugging messages\n+\t\t\t\t// (0 = off, 1 = on)\n+\t\t\t\trpi,debug = <0>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@4 {\n+\t\ttarget = <&gpio>;\n+\t\t__overlay__ {\n+\t\t\tlirc_pins: lirc_pins {\n+\t\t\t\tbrcm,pins = <6 5>;\n+\t\t\t\tbrcm,function = <1 0>; // out in\n+\t\t\t\tbrcm,pull = <0 1>; // off down\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\tspeed =     <&rpidisplay>,\"spi-max-frequency:0\";\n+\t\trotate =    <&rpidisplay>,\"rotate:0\";\n+\t\tfps =       <&rpidisplay>,\"fps:0\";\n+\t\tdebug =     <&rpidisplay>,\"debug:0\", \n+\t\t            <&lirc_rpi>,\"rpi,debug:0\";\n+\t\txohms =     <&rpidisplay_ts>,\"ti,x-plate-ohms;0\";\n+\t\tswapxy =    <&rpidisplay_ts>,\"ti,swap-xy?\";\n+\t\tbacklight = <&rpidisplay>,\"led-gpios:4\",\n+\t\t            <&rpi_display_pins>,\"brcm,pins:0\";\n+\n+\t\tgpio_out_pin =  <&lirc_pins>,\"brcm,pins:0\";\n+\t\tgpio_in_pin =   <&lirc_pins>,\"brcm,pins:4\";\n+\t\tgpio_in_pull =  <&lirc_pins>,\"brcm,pull:4\";\n+\n+\t\tsense =         <&lirc_rpi>,\"rpi,sense:0\";\n+\t\tsoftcarrier =   <&lirc_rpi>,\"rpi,softcarrier:0\";\n+\t\tinvert =        <&lirc_rpi>,\"rpi,invert:0\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/merus-amp-overlay.dts b/arch/arm/boot/dts/overlays/merus-amp-overlay.dts\nnew file mode 100644\nindex 000000000000..4501fbdc253d\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/merus-amp-overlay.dts\n@@ -0,0 +1,60 @@\n+// SPDX-License-Identifier: GPL-2.0-only\n+// Definitions for Infineon Merus-Amp\n+/dts-v1/;\n+/plugin/;\n+#include <dt-bindings/pinctrl/bcm2835.h>\n+#include <dt-bindings/gpio/gpio.h>\n+\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&i2s>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&gpio>;\n+\t\t__overlay__ {\n+\t\t\tmerus_amp_pins: merus_amp_pins {\n+\t\t\t\tbrcm,pins = <23>;\n+\t\t\t\tbrcm,function = <0>; /* in */\n+\t\t\t\tbrcm,pull = <2>; /* up */\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&i2c1>;\n+\t\t__overlay__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tmerus_amp: ma120x0p@20 {\n+\t\t\t\t#sound-dai-cells = <0>;\n+\t\t\t\tcompatible = \"ma,ma120x0p\";\n+\t\t\t\treg = <0x20>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t\tpinctrl-names = \"default\";\n+\t\t\t\tpinctrl-0 = <&merus_amp_pins>;\n+\t\t\t\tenable_gp-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;\n+\t\t\t\tmute_gp-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;\n+\t\t\t\tbooster_gp-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n+\t\t\t\terror_gp-gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@3 {\n+\t\ttarget = <&sound>;\n+\t\t__overlay__ {\n+\t\t\tcompatible = \"merus,merus-amp\";\n+\t\t\ti2s-controller = <&i2s>;\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/midi-uart0-overlay.dts b/arch/arm/boot/dts/overlays/midi-uart0-overlay.dts\nnew file mode 100644\nindex 000000000000..f7e44d29e101\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/midi-uart0-overlay.dts\n@@ -0,0 +1,36 @@\n+/dts-v1/;\n+/plugin/;\n+\n+#include <dt-bindings/clock/bcm2835.h>\n+\n+/*\n+ * Fake a higher clock rate to get a larger divisor, and thereby a lower\n+ * baudrate. The real clock is 48MHz, which we scale so that requesting\n+ * 38.4kHz results in an actual 31.25kHz.\n+ *\n+ *   48000000*38400/31250 = 58982400\n+ */\n+\n+/{\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget-path = \"/\";\n+\t\t__overlay__ {\n+\t\t\tmidi_clk: midi_clk {\n+\t\t\t\tcompatible = \"fixed-clock\";\n+\t\t\t\t#clock-cells = <0>;\n+\t\t\t\tclock-output-names = \"uart0_pclk\";\n+\t\t\t\tclock-frequency = <58982400>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&uart0>;\n+\t\t__overlay__ {\n+\t\t\tclocks = <&midi_clk>,\n+\t\t\t         <&clocks BCM2835_CLOCK_VPU>;\n+\t\t};\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/midi-uart1-overlay.dts b/arch/arm/boot/dts/overlays/midi-uart1-overlay.dts\nnew file mode 100644\nindex 000000000000..e0bc410acbff\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/midi-uart1-overlay.dts\n@@ -0,0 +1,43 @@\n+/dts-v1/;\n+/plugin/;\n+\n+#include <dt-bindings/clock/bcm2835-aux.h>\n+\n+/*\n+ * Fake a higher clock rate to get a larger divisor, and thereby a lower\n+ * baudrate. The real clock is 48MHz, which we scale so that requesting\n+ * 38.4kHz results in an actual 31.25kHz.\n+ *\n+ *   48000000*38400/31250 = 58982400\n+ */\n+\n+/{\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget-path = \"/clocks\";\n+\t\t__overlay__ {\n+\t\t\tmidi_clk: clock@5 {\n+\t\t\t\tcompatible = \"fixed-factor-clock\";\n+\t\t\t\t#clock-cells = <0>;\n+\t\t\t\tclocks = <&aux BCM2835_AUX_CLOCK_UART>;\n+\t\t\t\tclock-mult = <38400>;\n+\t\t\t\tclock-div  = <31250>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&uart1>;\n+\t\t__overlay__ {\n+\t\t\tclocks = <&midi_clk>;\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&aux>;\n+\t\t__overlay__ {\n+\t\t\tclock-output-names = \"aux_uart\", \"aux_spi1\", \"aux_spi2\";\n+\t\t};\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/miniuart-bt-overlay.dts b/arch/arm/boot/dts/overlays/miniuart-bt-overlay.dts\nnew file mode 100644\nindex 000000000000..da49f14a0940\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/miniuart-bt-overlay.dts\n@@ -0,0 +1,93 @@\n+/dts-v1/;\n+/plugin/;\n+\n+/* Switch Pi3 Bluetooth function to use the mini-UART (ttyS0) and restore\n+   UART0/ttyAMA0 over GPIOs 14 & 15. Note that this may reduce the maximum\n+   usable baudrate.\n+\n+   It is also necessary to edit /lib/systemd/system/hciuart.service and\n+   replace ttyAMA0 with ttyS0, unless you have a system with udev rules\n+   that create /dev/serial0 and /dev/serial1, in which case use /dev/serial1\n+   instead because it will always be correct.\n+\n+   If cmdline.txt uses the alias serial0 to refer to the user-accessable port\n+   then the firmware will replace with the appropriate port whether or not\n+   this overlay is used.\n+*/\n+\n+#include <dt-bindings/gpio/gpio.h>\n+\n+/{\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&uart0>;\n+\t\t__overlay__ {\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&uart0_pins>;\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&bt>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&uart1>;\n+\t\t__overlay__ {\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&uart1_pins &bt_pins &fake_bt_cts>;\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@3 {\n+\t\ttarget = <&uart0_pins>;\n+\t\t__overlay__ {\n+\t\t\tbrcm,pins;\n+\t\t\tbrcm,function;\n+\t\t\tbrcm,pull;\n+\t\t};\n+\t};\n+\n+\tfragment@4 {\n+\t\ttarget = <&uart1_pins>;\n+\t\t__overlay__ {\n+\t\t\tbrcm,pins = <32 33>;\n+\t\t\tbrcm,function = <2>; /* alt5=UART1 */\n+\t\t\tbrcm,pull = <0 2>;\n+\t\t};\n+\t};\n+\n+\tfragment@5 {\n+\t\ttarget = <&gpio>;\n+\t\t__overlay__ {\n+\t\t\tfake_bt_cts: fake_bt_cts {\n+\t\t\t\tbrcm,pins = <31>;\n+\t\t\t\tbrcm,function = <1>; /* output */\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@6 {\n+\t\ttarget-path = \"/aliases\";\n+\t\t__overlay__ {\n+\t\t\tserial0 = \"/soc/serial@7e201000\";\n+\t\t\tserial1 = \"/soc/serial@7e215040\";\n+\t\t};\n+\t};\n+\n+\tfragment@7 {\n+\t\ttarget = <&minibt>;\n+\t\tminibt_frag: __overlay__ {\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\tkrnbt = <&minibt_frag>,\"status\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/mmc-overlay.dts b/arch/arm/boot/dts/overlays/mmc-overlay.dts\nnew file mode 100644\nindex 000000000000..c1a2f691aa1e\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/mmc-overlay.dts\n@@ -0,0 +1,46 @@\n+/dts-v1/;\n+/plugin/;\n+\n+/{\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&mmc>;\n+\t\tfrag0: __overlay__ {\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&mmc_pins>;\n+\t\t\tbus-width = <4>;\n+\t\t\tbrcm,overclock-50 = <0>;\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&gpio>;\n+\t\t__overlay__ {\n+\t\t\tmmc_pins: mmc_pins {\n+\t\t\t\tbrcm,pins = <48 49 50 51 52 53>;\n+\t\t\t\tbrcm,function = <7>; /* alt3 */\n+\t\t\t\tbrcm,pull = <0 2 2 2 2 2>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&sdhost>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\tfragment@3 {\n+\t\ttarget = <&mmcnr>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\toverclock_50     = <&frag0>,\"brcm,overclock-50:0\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/mpu6050-overlay.dts b/arch/arm/boot/dts/overlays/mpu6050-overlay.dts\nnew file mode 100644\nindex 000000000000..3109d90562ae\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/mpu6050-overlay.dts\n@@ -0,0 +1,28 @@\n+// Definitions for MPU6050\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+        compatible = \"brcm,bcm2835\";\n+\n+        fragment@0 {\n+                target = <&i2c1>;\n+                __overlay__ {\n+                        #address-cells = <1>;\n+                        #size-cells = <0>;\n+                        status = \"okay\";\n+                        clock-frequency = <400000>;\n+\n+                        mpu6050: mpu6050@68 {\n+                                compatible = \"invensense,mpu6050\";\n+                                reg = <0x68>;\n+                                interrupt-parent = <&gpio>;\n+                                interrupts = <4 1>;\n+                        };\n+                };\n+        };\n+\n+        __overrides__ {\n+                interrupt = <&mpu6050>,\"interrupts:0\";\n+        };\n+};\ndiff --git a/arch/arm/boot/dts/overlays/mz61581-overlay.dts b/arch/arm/boot/dts/overlays/mz61581-overlay.dts\nnew file mode 100644\nindex 000000000000..6e00e8b2ddf2\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/mz61581-overlay.dts\n@@ -0,0 +1,117 @@\n+/*\n+ * Device Tree overlay for MZ61581-PI-EXT 2014.12.28 by Tontec\n+ *\n+ */\n+\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&spi0>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&spidev0>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&spidev1>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\tfragment@3 {\n+\t\ttarget = <&gpio>;\n+\t\t__overlay__ {\n+\t\t\tmz61581_pins: mz61581_pins {\n+\t\t\t\tbrcm,pins = <4 15 18 25>;\n+\t\t\t\tbrcm,function = <0 1 1 1>; /* in out out out */\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@4 {\n+\t\ttarget = <&spi0>;\n+\t\t__overlay__ {\n+\t\t\t/* needed to avoid dtc warning */\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tmz61581: mz61581@0{\n+\t\t\t\tcompatible = \"samsung,s6d02a1\";\n+\t\t\t\treg = <0>;\n+\t\t\t\tpinctrl-names = \"default\";\n+\t\t\t\tpinctrl-0 = <&mz61581_pins>;\n+\n+\t\t\t\tspi-max-frequency = <128000000>;\n+\t\t\t\tspi-cpol;\n+\t\t\t\tspi-cpha;\n+\n+\t\t\t\twidth = <320>;\n+\t\t\t\theight = <480>;\n+\t\t\t\trotate = <270>;\n+\t\t\t\tbgr;\n+\t\t\t\tfps = <30>;\n+\t\t\t\tbuswidth = <8>;\n+\t\t\t\ttxbuflen = <32768>;\n+\n+\t\t\t\treset-gpios = <&gpio 15 1>;\n+\t\t\t\tdc-gpios = <&gpio 25 0>;\n+\t\t\t\tled-gpios = <&gpio 18 0>;\n+\n+\t\t\t\tinit = <0x10000b0 00\n+\t\t\t\t\t0x1000011\n+\t\t\t\t\t0x20000ff\n+\t\t\t\t\t0x10000b3 0x02 0x00 0x00 0x00\n+\t\t\t\t\t0x10000c0 0x13 0x3b 0x00 0x02 0x00 0x01 0x00 0x43\n+\t\t\t\t\t0x10000c1 0x08 0x16 0x08 0x08\n+\t\t\t\t\t0x10000c4 0x11 0x07 0x03 0x03\n+\t\t\t\t\t0x10000c6 0x00\n+\t\t\t\t\t0x10000c8 0x03 0x03 0x13 0x5c 0x03 0x07 0x14 0x08 0x00 0x21 0x08 0x14 0x07 0x53 0x0c 0x13 0x03 0x03 0x21 0x00\n+\t\t\t\t\t0x1000035 0x00\n+\t\t\t\t\t0x1000036 0xa0\n+\t\t\t\t\t0x100003a 0x55\n+\t\t\t\t\t0x1000044 0x00 0x01\n+\t\t\t\t\t0x10000d0 0x07 0x07 0x1d 0x03\n+\t\t\t\t\t0x10000d1 0x03 0x30 0x10\n+\t\t\t\t\t0x10000d2 0x03 0x14 0x04\n+\t\t\t\t\t0x1000029\n+\t\t\t\t\t0x100002c>;\n+\n+\t\t\t\t/* This is a workaround to make sure the init sequence slows down and doesn't fail */\n+\t\t\t\tdebug = <3>;\n+\t\t\t};\n+\n+\t\t\tmz61581_ts: mz61581_ts@1 {\n+\t\t\t\tcompatible = \"ti,ads7846\";\n+\t\t\t\treg = <1>;\n+\n+\t\t\t\tspi-max-frequency = <2000000>;\n+\t\t\t\tinterrupts = <4 2>; /* high-to-low edge triggered */\n+\t\t\t\tinterrupt-parent = <&gpio>;\n+\t\t\t\tpendown-gpio = <&gpio 4 0>;\n+\n+\t\t\t\tti,x-plate-ohms = /bits/ 16 <60>;\n+\t\t\t\tti,pressure-max = /bits/ 16 <255>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\t__overrides__ {\n+\t\tspeed =   <&mz61581>, \"spi-max-frequency:0\";\n+\t\trotate =  <&mz61581>, \"rotate:0\";\n+\t\tfps =     <&mz61581>, \"fps:0\";\n+\t\ttxbuflen = <&mz61581>, \"txbuflen:0\";\n+\t\tdebug =   <&mz61581>, \"debug:0\";\n+\t\txohms =   <&mz61581_ts>,\"ti,x-plate-ohms;0\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/ov5647-overlay.dts b/arch/arm/boot/dts/overlays/ov5647-overlay.dts\nnew file mode 100644\nindex 000000000000..fd1e7a457f69\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/ov5647-overlay.dts\n@@ -0,0 +1,92 @@\n+// SPDX-License-Identifier: GPL-2.0-only\n+// Definitions for OV5647 camera module on VC I2C bus\n+/dts-v1/;\n+/plugin/;\n+\n+/{\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&i2c_csi_dsi>;\n+\t\t__overlay__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tov5647: ov5647@36 {\n+\t\t\t\tcompatible = \"ovti,ov5647\";\n+\t\t\t\treg = <0x36>;\n+\t\t\t\tstatus = \"okay\";\n+\n+\t\t\t\tpwdn-gpios = <&gpio 41 1>, <&gpio 32 1>;\n+\t\t\t\tclocks = <&ov5647_clk>;\n+\n+\t\t\t\trotation = <0>;\n+\n+\t\t\t\tport {\n+\t\t\t\t\tov5647_0: endpoint {\n+\t\t\t\t\t\tremote-endpoint = <&csi1_ep>;\n+\t\t\t\t\t\tclock-lanes = <0>;\n+\t\t\t\t\t\tdata-lanes = <1 2>;\n+\t\t\t\t\t\tclock-noncontinuous;\n+\t\t\t\t\t\tlink-frequencies =\n+\t\t\t\t\t\t\t/bits/ 64 <297000000>;\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&csi1>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tport {\n+\t\t\t\tcsi1_ep: endpoint {\n+\t\t\t\t\tremote-endpoint = <&ov5647_0>;\n+\t\t\t\t\tdata-lanes = <1 2>;\n+\t\t\t\t};\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&i2c0if>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@3 {\n+\t\ttarget = <&i2c0mux>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@4 {\n+\t\ttarget-path=\"/__overrides__\";\n+\t\t__overlay__ {\n+\t\t\tcam0-pwdn-ctrl = <&ov5647>,\"pwdn-gpios:0\";\n+\t\t\tcam0-pwdn      = <&ov5647>,\"pwdn-gpios:4\";\n+\t\t\tcam0-led-ctrl  = <&ov5647>,\"pwdn-gpios:12\";\n+\t\t\tcam0-led       = <&ov5647>,\"pwdn-gpios:16\";\n+\t\t};\n+\t};\n+\n+\tfragment@5 {\n+\t\ttarget-path = \"/\";\n+\t\t__overlay__ {\n+\t\t\tov5647_clk: camera-clk {\n+\t\t\t\tcompatible = \"fixed-clock\";\n+\t\t\t\t#clock-cells = <0>;\n+\t\t\t\tclock-frequency = <25000000>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\trotation = <&ov5647>,\"rotation:0\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/ov7251-overlay.dts b/arch/arm/boot/dts/overlays/ov7251-overlay.dts\nnew file mode 100644\nindex 000000000000..f04eafd4adf9\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/ov7251-overlay.dts\n@@ -0,0 +1,111 @@\n+// SPDX-License-Identifier: GPL-2.0-only\n+// Definitions for OV7251 camera module on VC I2C bus\n+/dts-v1/;\n+/plugin/;\n+\n+#include <dt-bindings/gpio/gpio.h>\n+\n+/{\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&i2c_csi_dsi>;\n+\t\t__overlay__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tov7251: ov7251@60 {\n+\t\t\t\tcompatible = \"ovti,ov7251\";\n+\t\t\t\treg = <0x60>;\n+\t\t\t\tstatus = \"okay\";\n+\n+\t\t\t\tclocks = <&ov7251_clk>;\n+\t\t\t\tclock-names = \"xclk\";\n+\t\t\t\tclock-frequency = <24000000>;\n+\n+\t\t\t\tvdddo-supply = <&ov7251_dovdd>;\n+\t\t\t\tvdda-supply = <&ov7251_avdd>;\n+\t\t\t\tvddd-supply = <&ov7251_dvdd>;\n+\n+\t\t\t\tenable-gpios = <&gpio 41 GPIO_ACTIVE_HIGH>;\n+\n+\t\t\t\tport {\n+\t\t\t\t\tov7251_0: endpoint {\n+\t\t\t\t\t\tremote-endpoint = <&csi1_ep>;\n+\t\t\t\t\t\tclock-lanes = <0>;\n+\t\t\t\t\t\tdata-lanes = <1>;\n+\t\t\t\t\t\tclock-noncontinuous;\n+\t\t\t\t\t\tlink-frequencies =\n+\t\t\t\t\t\t\t/bits/ 64 <456000000>;\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&csi1>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tport {\n+\t\t\t\tcsi1_ep: endpoint {\n+\t\t\t\t\tremote-endpoint = <&ov7251_0>;\n+\t\t\t\t\tdata-lanes = <1>;\n+\t\t\t\t};\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&i2c0if>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@3 {\n+\t\ttarget-path=\"/\";\n+\t\t__overlay__ {\n+\t\t\tov7251_avdd: fixedregulator@0 {\n+\t\t\t\tcompatible = \"regulator-fixed\";\n+\t\t\t\tregulator-name = \"ov7251_avdd\";\n+\t\t\t\tregulator-min-microvolt = <2800000>;\n+\t\t\t\tregulator-max-microvolt = <2800000>;\n+\t\t\t};\n+\t\t\tov7251_dovdd: fixedregulator@1 {\n+\t\t\t\tcompatible = \"regulator-fixed\";\n+\t\t\t\tregulator-name = \"ov7251_dovdd\";\n+\t\t\t\tregulator-min-microvolt = <1800000>;\n+\t\t\t\tregulator-max-microvolt = <1800000>;\n+\t\t\t};\n+\t\t\tov7251_dvdd: fixedregulator@2 {\n+\t\t\t\tcompatible = \"regulator-fixed\";\n+\t\t\t\tregulator-name = \"ov7251_dvdd\";\n+\t\t\t\tregulator-min-microvolt = <1200000>;\n+\t\t\t\tregulator-max-microvolt = <1200000>;\n+\t\t\t};\n+\t\t\tov7251_clk: ov7251-clk {\n+\t\t\t\tcompatible = \"fixed-clock\";\n+\t\t\t\t#clock-cells = <0>;\n+\t\t\t\tclock-frequency = <24000000>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@4 {\n+\t\ttarget = <&i2c0mux>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@5 {\n+\t\ttarget-path=\"/__overrides__\";\n+\t\t__overlay__ {\n+\t\t\tcam0-pwdn-ctrl = <&ov7251>,\"enable-gpios:0\";\n+\t\t\tcam0-pwdn      = <&ov7251>,\"enable-gpios:4\";\n+\t\t};\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/ov9281-overlay.dts b/arch/arm/boot/dts/overlays/ov9281-overlay.dts\nnew file mode 100644\nindex 000000000000..40b298d3dd86\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/ov9281-overlay.dts\n@@ -0,0 +1,111 @@\n+// SPDX-License-Identifier: GPL-2.0-only\n+// Definitions for OV9281 camera module on VC I2C bus\n+/dts-v1/;\n+/plugin/;\n+\n+#include <dt-bindings/gpio/gpio.h>\n+\n+/{\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&i2c_csi_dsi>;\n+\t\t__overlay__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tov9281: ov9281@60 {\n+\t\t\t\tcompatible = \"ovti,ov9281\";\n+\t\t\t\treg = <0x60>;\n+\t\t\t\tstatus = \"okay\";\n+\n+\t\t\t\tclocks = <&ov9281_clk>;\n+\t\t\t\tclock-names = \"xvclk\";\n+\n+\t\t\t\tavdd-supply = <&ov9281_avdd>;\n+\t\t\t\tdovdd-supply = <&ov9281_dovdd>;\n+\t\t\t\tdvdd-supply = <&ov9281_dvdd>;\n+\n+\t\t\t\tport {\n+\t\t\t\t\tov9281_0: endpoint {\n+\t\t\t\t\t\tremote-endpoint = <&csi1_ep>;\n+\t\t\t\t\t\tclock-lanes = <0>;\n+\t\t\t\t\t\tdata-lanes = <1 2>;\n+\t\t\t\t\t\tclock-noncontinuous;\n+\t\t\t\t\t\tlink-frequencies =\n+\t\t\t\t\t\t\t/bits/ 64 <400000000>;\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&csi1>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tport {\n+\t\t\t\tcsi1_ep: endpoint {\n+\t\t\t\t\tremote-endpoint = <&ov9281_0>;\n+\t\t\t\t\tdata-lanes = <1 2>;\n+\t\t\t\t\tclock-noncontinuous;\n+\t\t\t\t};\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&i2c0if>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@3 {\n+\t\ttarget-path=\"/\";\n+\t\t__overlay__ {\n+\t\t\tov9281_avdd: fixedregulator@0 {\n+\t\t\t\tcompatible = \"regulator-fixed\";\n+\t\t\t\tregulator-name = \"ov9281_avdd\";\n+\t\t\t\tregulator-min-microvolt = <2800000>;\n+\t\t\t\tregulator-max-microvolt = <2800000>;\n+\t\t\t\tgpio = <&gpio 41 GPIO_ACTIVE_HIGH>;\n+\t\t\t\tenable-active-high;\n+\t\t\t};\n+\t\t\tov9281_dovdd: fixedregulator@1 {\n+\t\t\t\tcompatible = \"regulator-fixed\";\n+\t\t\t\tregulator-name = \"ov9281_dovdd\";\n+\t\t\t\tregulator-min-microvolt = <1800000>;\n+\t\t\t\tregulator-max-microvolt = <1800000>;\n+\t\t\t};\n+\t\t\tov9281_dvdd: fixedregulator@2 {\n+\t\t\t\tcompatible = \"regulator-fixed\";\n+\t\t\t\tregulator-name = \"ov9281_dvdd\";\n+\t\t\t\tregulator-min-microvolt = <1200000>;\n+\t\t\t\tregulator-max-microvolt = <1200000>;\n+\t\t\t};\n+\t\t\tov9281_clk: ov9281-clk {\n+\t\t\t\tcompatible = \"fixed-clock\";\n+\t\t\t\t#clock-cells = <0>;\n+\t\t\t\tclock-frequency = <24000000>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@4 {\n+\t\ttarget = <&i2c0mux>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@5 {\n+\t\ttarget-path=\"/__overrides__\";\n+\t\t__overlay__ {\n+\t\t\tcam0-pwdn-ctrl = <&ov9281_avdd>,\"gpio:0\";\n+\t\t\tcam0-pwdn      = <&ov9281_avdd>,\"gpio:4\";\n+\t\t};\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/overlay_map.dts b/arch/arm/boot/dts/overlays/overlay_map.dts\nnew file mode 100644\nindex 000000000000..22b0ad1738ec\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/overlay_map.dts\n@@ -0,0 +1,141 @@\n+/dts-v1/;\n+\n+/ {\n+\tbmp085_i2c-sensor {\n+\t\tdeprecated = \"use i2c-sensor,bmp085\";\n+\t};\n+\n+\thighperi {\n+\t\tbcm2711;\n+\t};\n+\n+\ti2c0-bcm2708 {\n+\t\tdeprecated = \"use i2c0\";\n+\t};\n+\n+\ti2c1-bcm2708 {\n+\t\tdeprecated = \"use i2c1\";\n+\t};\n+\n+\ti2c3 {\n+\t\tbcm2711;\n+\t};\n+\n+\ti2c4 {\n+\t\tbcm2711;\n+\t};\n+\n+\ti2c5 {\n+\t\tbcm2711;\n+\t};\n+\n+\ti2c6 {\n+\t\tbcm2711;\n+\t};\n+\n+\tlirc-rpi {\n+\t\tdeprecated = \"use gpio-ir\";\n+\t};\n+\n+\tpi3-act-led {\n+\t\trenamed = \"act-led\";\n+\t};\n+\n+\tpi3-disable-bt {\n+\t\trenamed = \"disable-bt\";\n+\t};\n+\n+\tpi3-disable-wifi {\n+\t\trenamed = \"disable-wifi\";\n+\t};\n+\n+\tpi3-miniuart-bt {\n+\t\trenamed = \"miniuart-bt\";\n+\t};\n+\n+\trpivid-v4l2 {\n+\t\tbcm2711;\n+\t};\n+\n+\tsdio-1bit {\n+\t\tdeprecated = \"use sdio,bus_width=1,gpios_22_25\";\n+\t};\n+\n+\tspi0-cs {\n+\t\trenamed = \"spi0-2cs\";\n+\t};\n+\n+\tspi0-hw-cs {\n+\t\tdeprecated = \"no longer necessary\";\n+\t};\n+\n+\tspi3-1cs {\n+\t\tbcm2711;\n+\t};\n+\n+\tspi3-2cs {\n+\t\tbcm2711;\n+\t};\n+\n+\tspi4-1cs {\n+\t\tbcm2711;\n+\t};\n+\n+\tspi4-2cs {\n+\t\tbcm2711;\n+\t};\n+\n+\tspi5-1cs {\n+\t\tbcm2711;\n+\t};\n+\n+\tspi5-2cs {\n+\t\tbcm2711;\n+\t};\n+\n+\tspi6-1cs {\n+\t\tbcm2711;\n+\t};\n+\n+\tspi6-2cs {\n+\t\tbcm2711;\n+\t};\n+\n+\tuart2 {\n+\t\tbcm2711;\n+\t};\n+\n+\tuart3 {\n+\t\tbcm2711;\n+\t};\n+\n+\tuart4 {\n+\t\tbcm2711;\n+\t};\n+\n+\tuart5 {\n+\t\tbcm2711;\n+\t};\n+\n+\tupstream {\n+\t\tbcm2835;\n+\t\tbcm2711 = \"upstream-pi4\";\n+\t};\n+\n+\tupstream-aux-interrupt {\n+\t\tdeprecated = \"no longer necessary\";\n+\t};\n+\n+\tupstream-pi4 {\n+\t\tbcm2711;\n+\t};\n+\n+\tvc4-kms-v3d {\n+\t\tbcm2835;\n+\t\tbcm2711 = \"vc4-kms-v3d-pi4\";\n+\t};\n+\n+\tvc4-kms-v3d-pi4 {\n+\t\tbcm2711;\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/papirus-overlay.dts b/arch/arm/boot/dts/overlays/papirus-overlay.dts\nnew file mode 100644\nindex 000000000000..7b6bcfd49c86\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/papirus-overlay.dts\n@@ -0,0 +1,89 @@\n+/* PaPiRus ePaper Screen by Pi Supply */\n+\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&i2c_arm>;\n+\t\t__overlay__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tdisplay_temp: lm75@48 {\n+\t\t\t\tcompatible = \"lm75b\";\n+\t\t\t\treg = <0x48>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t\t#thermal-sensor-cells = <0>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget-path = \"/\";\n+\t\t__overlay__ {\n+\t\t\tthermal-zones {\n+\t\t\t\tdisplay {\n+\t\t\t\t\tpolling-delay-passive = <0>;\n+\t\t\t\t\tpolling-delay = <0>;\n+\t\t\t\t\tthermal-sensors = <&display_temp>;\n+\t\t\t\t};\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&spi0>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tspidev@0{\n+\t\t\t\tstatus = \"disabled\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@3 {\n+\t\ttarget = <&gpio>;\n+\t\t__overlay__ {\n+\t\t\trepaper_pins: repaper_pins {\n+\t\t\t\tbrcm,pins = <14 15 23 24 25>;\n+\t\t\t\tbrcm,function = <1 1 1 1 0>; /* out out out out in */\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@4 {\n+\t\ttarget = <&spi0>;\n+\t\t__overlay__ {\n+\t\t\t/* needed to avoid dtc warning */\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\trepaper: repaper@0{\n+\t\t\t\tcompatible = \"not_set\";\n+\t\t\t\treg = <0>;\n+\t\t\t\tpinctrl-names = \"default\";\n+\t\t\t\tpinctrl-0 = <&repaper_pins>;\n+\n+\t\t\t\tspi-max-frequency = <8000000>;\n+\n+\t\t\t\tpanel-on-gpios = <&gpio 23 0>;\n+\t\t\t\tborder-gpios = <&gpio 14 0>;\n+\t\t\t\tdischarge-gpios = <&gpio 15 0>;\n+\t\t\t\treset-gpios = <&gpio 24 0>;\n+\t\t\t\tbusy-gpios = <&gpio 25 0>;\n+\n+\t\t\t\trepaper-thermal-zone = \"display\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\tpanel = <&repaper>, \"compatible\";\n+\t\tspeed = <&repaper>, \"spi-max-frequency:0\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/pca953x-overlay.dts b/arch/arm/boot/dts/overlays/pca953x-overlay.dts\nnew file mode 100644\nindex 000000000000..8b6ee44665ce\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/pca953x-overlay.dts\n@@ -0,0 +1,240 @@\n+// Definitions for NXP PCA953x family of I2C GPIO controllers on ARM I2C bus.\n+/dts-v1/;\n+/plugin/;\n+\n+/{\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&i2c_arm>;\n+\t\t__overlay__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tpca: pca@20 {\n+\t\t\t\tcompatible = \"nxp,pca9534\";\n+\t\t\t\treg = <0x20>;\n+\t\t\t\tgpio-controller;\n+\t\t\t\t#gpio-cells = <2>;\n+\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&pca>;\n+\t\t__dormant__ {\n+\t\t\tcompatible = \"nxp,pca6416\";\n+\t\t};\n+\t};\n+\tfragment@2 {\n+\t\ttarget = <&pca>;\n+\t\t__dormant__ {\n+\t\t\tcompatible = \"nxp,pca9505\";\n+\t\t};\n+\t};\n+\tfragment@3 {\n+\t\ttarget = <&pca>;\n+\t\t__dormant__ {\n+\t\t\tcompatible = \"nxp,pca9535\";\n+\t\t};\n+\t};\n+\tfragment@4 {\n+\t\ttarget = <&pca>;\n+\t\t__dormant__ {\n+\t\t\tcompatible = \"nxp,pca9536\";\n+\t\t};\n+\t};\n+\tfragment@5 {\n+\t\ttarget = <&pca>;\n+\t\t__dormant__ {\n+\t\t\tcompatible = \"nxp,pca9537\";\n+\t\t};\n+\t};\n+\tfragment@6 {\n+\t\ttarget = <&pca>;\n+\t\t__dormant__ {\n+\t\t\tcompatible = \"nxp,pca9538\";\n+\t\t};\n+\t};\n+\tfragment@7 {\n+\t\ttarget = <&pca>;\n+\t\t__dormant__ {\n+\t\t\tcompatible = \"nxp,pca9539\";\n+\t\t};\n+\t};\n+\tfragment@8 {\n+\t\ttarget = <&pca>;\n+\t\t__dormant__ {\n+\t\t\tcompatible = \"nxp,pca9554\";\n+\t\t};\n+\t};\n+\tfragment@9 {\n+\t\ttarget = <&pca>;\n+\t\t__dormant__ {\n+\t\t\tcompatible = \"nxp,pca9555\";\n+\t\t};\n+\t};\n+\tfragment@10 {\n+\t\ttarget = <&pca>;\n+\t\t__dormant__ {\n+\t\t\tcompatible = \"nxp,pca9556\";\n+\t\t};\n+\t};\n+\tfragment@11 {\n+\t\ttarget = <&pca>;\n+\t\t__dormant__ {\n+\t\t\tcompatible = \"nxp,pca9557\";\n+\t\t};\n+\t};\n+\tfragment@12 {\n+\t\ttarget = <&pca>;\n+\t\t__dormant__ {\n+\t\t\tcompatible = \"nxp,pca9574\";\n+\t\t};\n+\t};\n+\tfragment@13 {\n+\t\ttarget = <&pca>;\n+\t\t__dormant__ {\n+\t\t\tcompatible = \"nxp,pca9575\";\n+\t\t};\n+\t};\n+\tfragment@14 {\n+\t\ttarget = <&pca>;\n+\t\t__dormant__ {\n+\t\t\tcompatible = \"nxp,pca9698\";\n+\t\t};\n+\t};\n+\tfragment@15 {\n+\t\ttarget = <&pca>;\n+\t\t__dormant__ {\n+\t\t\tcompatible = \"nxp,pca16416\";\n+\t\t};\n+\t};\n+\tfragment@16 {\n+\t\ttarget = <&pca>;\n+\t\t__dormant__ {\n+\t\t\tcompatible = \"nxp,pca16524\";\n+\t\t};\n+\t};\n+\tfragment@17 {\n+\t\ttarget = <&pca>;\n+\t\t__dormant__ {\n+\t\t\tcompatible = \"nxp,pca19555a\";\n+\t\t};\n+\t};\n+\tfragment@18 {\n+\t\ttarget = <&pca>;\n+\t\t__dormant__ {\n+\t\t\tcompatible = \"maxim,max7310\";\n+\t\t};\n+\t};\n+\tfragment@19 {\n+\t\ttarget = <&pca>;\n+\t\t__dormant__ {\n+\t\t\tcompatible = \"maxim,max7312\";\n+\t\t};\n+\t};\n+\tfragment@20 {\n+\t\ttarget = <&pca>;\n+\t\t__dormant__ {\n+\t\t\tcompatible = \"maxim,max7313\";\n+\t\t};\n+\t};\n+\tfragment@21 {\n+\t\ttarget = <&pca>;\n+\t\t__dormant__ {\n+\t\t\tcompatible = \"maxim,max7315\";\n+\t\t};\n+\t};\n+\tfragment@22 {\n+\t\ttarget = <&pca>;\n+\t\t__dormant__ {\n+\t\t\tcompatible = \"ti,pca6107\";\n+\t\t};\n+\t};\n+\tfragment@23 {\n+\t\ttarget = <&pca>;\n+\t\t__dormant__ {\n+\t\t\tcompatible = \"ti,tca6408\";\n+\t\t};\n+\t};\n+\tfragment@24 {\n+\t\ttarget = <&pca>;\n+\t\t__dormant__ {\n+\t\t\tcompatible = \"ti,tca6416\";\n+\t\t};\n+\t};\n+\tfragment@25 {\n+\t\ttarget = <&pca>;\n+\t\t__dormant__ {\n+\t\t\tcompatible = \"ti,tca6424\";\n+\t\t};\n+\t};\n+\tfragment@26 {\n+\t\ttarget = <&pca>;\n+\t\t__dormant__ {\n+\t\t\tcompatible = \"ti,tca9539\";\n+\t\t};\n+\t};\n+\tfragment@27 {\n+\t\ttarget = <&pca>;\n+\t\t__dormant__ {\n+\t\t\tcompatible = \"ti,tca9554\";\n+\t\t};\n+\t};\n+\tfragment@28 {\n+\t\ttarget = <&pca>;\n+\t\t__dormant__ {\n+\t\t\tcompatible = \"onnn,cat9554\";\n+\t\t};\n+\t};\n+\tfragment@29 {\n+\t\ttarget = <&pca>;\n+\t\t__dormant__ {\n+\t\t\tcompatible = \"onnn,pca9654\";\n+\t\t};\n+\t};\n+\tfragment@30 {\n+\t\ttarget = <&pca>;\n+\t\t__dormant__ {\n+\t\t\tcompatible = \"exar,xra1202\";\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\taddr = <&pca>,\"reg:0\";\n+\t\tpca6416 = <0>, \"+1\";\n+\t\tpca9505 = <0>, \"+2\";\n+\t\tpca9535 = <0>, \"+3\";\n+\t\tpca9536 = <0>, \"+4\";\n+\t\tpca9537 = <0>, \"+5\";\n+\t\tpca9538 = <0>, \"+6\";\n+\t\tpca9539 = <0>, \"+7\";\n+\t\tpca9554 = <0>, \"+8\";\n+\t\tpca9555 = <0>, \"+9\";\n+\t\tpca9556 = <0>, \"+10\";\n+\t\tpca9557 = <0>, \"+11\";\n+\t\tpca9574 = <0>, \"+12\";\n+\t\tpca9575 = <0>, \"+13\";\n+\t\tpca9698 = <0>, \"+14\";\n+\t\tpca16416 = <0>, \"+15\";\n+\t\tpca16524 = <0>, \"+16\";\n+\t\tpca19555a = <0>, \"+17\";\n+\t\tmax7310 = <0>, \"+18\";\n+\t\tmax7312 = <0>, \"+19\";\n+\t\tmax7313 = <0>, \"+20\";\n+\t\tmax7315 = <0>, \"+21\";\n+\t\tpca6107 = <0>, \"+22\";\n+\t\ttca6408 = <0>, \"+23\";\n+\t\ttca6416 = <0>, \"+24\";\n+\t\ttca6424 = <0>, \"+25\";\n+\t\ttca9539 = <0>, \"+26\";\n+\t\ttca9554 = <0>, \"+27\";\n+\t\tcat9554 = <0>, \"+28\";\n+\t\tpca9654 = <0>, \"+29\";\n+\t\txra1202 = <0>, \"+30\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/pibell-overlay.dts b/arch/arm/boot/dts/overlays/pibell-overlay.dts\nnew file mode 100644\nindex 000000000000..9333a9b09772\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/pibell-overlay.dts\n@@ -0,0 +1,81 @@\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+    compatible = \"brcm,bcm2835\";\n+\n+    fragment@0 {\n+        target-path = \"/\";\n+        __overlay__ {\n+            codec_out: spdif-transmitter {\n+                #address-cells = <0>;\n+                #size-cells = <0>;\n+                #sound-dai-cells = <0>;\n+                compatible = \"linux,spdif-dit\";\n+                status = \"okay\";\n+            };\n+\n+            codec_in: card-codec {\n+                #sound-dai-cells = <0>;\n+                compatible = \"invensense,ics43432\";\n+                status = \"okay\";\n+            };\n+        };\n+    };\n+\n+    fragment@1 {\n+        target = <&i2s>;\n+        __overlay__ {\n+            #sound-dai-cells = <0>;\n+            status = \"okay\";\n+        };\n+    };\n+\n+    fragment@2 {\n+        target = <&sound>;\n+        snd: __overlay__ {\n+            compatible = \"simple-audio-card\";\n+            simple-audio-card,name = \"PiBell\";\n+\n+            status=\"okay\";\n+\n+            capture_link: simple-audio-card,dai-link@0 {\n+                format = \"i2s\";\n+\n+                r_cpu_dai: cpu {\n+                    sound-dai = <&i2s>;\n+\n+/* example TDM slot configuration\n+                    dai-tdm-slot-num = <2>;\n+                    dai-tdm-slot-width = <32>;\n+*/\n+                };\n+\n+                r_codec_dai: codec {\n+                    sound-dai = <&codec_in>;\n+                };\n+            };\n+\n+            playback_link: simple-audio-card,dai-link@1 {\n+                format = \"i2s\";\n+\n+                p_cpu_dai: cpu {\n+                    sound-dai = <&i2s>;\n+\n+/* example TDM slot configuration\n+                    dai-tdm-slot-num = <2>;\n+                    dai-tdm-slot-width = <32>;\n+*/\n+                };\n+\n+                p_codec_dai: codec {\n+                    sound-dai = <&codec_out>;\n+                };\n+            };\n+        };\n+    };\n+\n+    __overrides__ {\n+        alsaname = <&snd>, \"simple-audio-card,name\";\n+    };\n+};\ndiff --git a/arch/arm/boot/dts/overlays/pifacedigital-overlay.dts b/arch/arm/boot/dts/overlays/pifacedigital-overlay.dts\nnew file mode 100644\nindex 000000000000..532a858683d6\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/pifacedigital-overlay.dts\n@@ -0,0 +1,144 @@\n+// SPDX-License-Identifier: GPL-2.0-only\n+/*\n+ * PiFace Digital, Device Tree Overlay.\n+ * Copyright (C) 2020 Thomas Preston <thomas.preston@codethink.co.uk>\n+ *\n+ * The PiFace Digital is a convenient breakout board for the Microchip mcp23s17\n+ * SPI GPIO port expander.\n+ *\n+ * The first eight GPIOs 0..7 (bank A) are connected to eight output terminals\n+ * and LEDs, plus two relays on the first two outputs. These output loads are\n+ * active-high.\n+ *\n+ * The next eight GPIOs 8..15 (bank B) are connected to eight input terminals\n+ * with four on-board switches connecting them to ground. Inputs devices are\n+ * therefore expected to bridge terminals to ground, so the mcp23s17 pullups are\n+ * activated for GPIO bank B.\n+ *\n+ * On PiFace Digital, the mcp23s17 is connected to the Raspberry Pi's SPI0 CS0\n+ * bus. Each SPI bus supports up to eight addressable child devices. The PiFace\n+ * Digital only supports addresses 0-4, which can be configured by jumpers JP1\n+ * and JP2.\n+ *\n+ * You can tell the driver about these jumper configurations with the\n+ * spi-present-mask bitmask:\n+ *\n+ *     | JP1 | JP2 | dtoverlay line in /boot/config.txt         |\n+ *     | --- | --- | ------------------------------------------ |\n+ *     |  0  |  0  | dtoverlay=pifacedigital                    |\n+ *     |  0  |  0  | dtoverlay=pifacedigital:spi-present-mask=1 |\n+ *     |  0  |  1  | dtoverlay=pifacedigital:spi-present-mask=2 |\n+ *     |  1  |  0  | dtoverlay=pifacedigital:spi-present-mask=4 |\n+ *     |  1  |  1  | dtoverlay=pifacedigital:spi-present-mask=8 |\n+ *\n+ * # Example\n+ * Set the dtoverlay config in /boot/config.txt and power off the Raspberry Pi:\n+ *\n+ *     $ grep pifacedigital /boot/config.txt\n+ *     dtoverlay=pifacedigital\n+ *     $ sudo systemctl poweroff\n+ *\n+ * Attach the PiFace Digital and power on the Raspberry Pi.\n+ * Then use the libgpiod tools to query the device:\n+ *\n+ *     $ sudo apt install gpiod\n+ *     $ gpiodetect | grep mcp23s17\n+ *     gpiochip2 [mcp23s17.0] (16 lines)\n+ *\n+ * Set GPIO outputs 0, 2 and 5:\n+ *\n+ *     $ gpioset gpiochip2 0=1 2=1 5=1\n+ *\n+ * Get GPIO status (input GPIO 8..15 are high, because they are active-low):\n+ *\n+ *     $ gpioget gpiochip2 {8..15}\n+ *     1 1 1 1 1 1 1 1\n+ *\n+ * And even monitor interrupts:\n+ *\n+ *     $ gpiomon gpiochip2 {8..15}\n+ *     event: FALLING EDGE offset: 11 timestamp: [1597361662.926741667]\n+ *     event:  RISING EDGE offset: 11 timestamp: [1597361663.062555051]\n+ *\n+ */\n+\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\t/* Disable exposing /dev/spidev0.0 */\n+\tfragment@0 {\n+\t\ttarget = <&spidev0>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\t/* Add the PiFace Digital device node to the spi0.0 device. */\n+\tfragment@1 {\n+\t\ttarget = <&spi0>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tpfdigital: pifacedigital@0 {\n+\t\t\t\tcompatible = \"microchip,mcp23s17\";\n+\t\t\t\treg = <0>;\n+\n+\t\t\t\t/* Set devices present with 8-bit mask. */\n+\t\t\t\tmicrochip,spi-present-mask = <0x01>;\n+\t\t\t\tspi-max-frequency = <500000>;\n+\n+\t\t\t\tgpio-controller;\n+\t\t\t\t#gpio-cells = <2>;\n+\n+\t\t\t\t/* This device can pass through interrupts. */\n+\t\t\t\tinterrupt-controller;\n+\t\t\t\t#interrupt-cells = <2>;\n+\n+\t\t\t\t/* INTB is connected to GPIO 25.\n+\t\t\t\t * 0x8 active-low level-sensitive\n+\t\t\t\t */\n+\t\t\t\tinterrupts = <25 0x8>;\n+\t\t\t\tinterrupt-parent = <&gpio>;\n+\n+\t\t\t\t/* Configure pull-ups on bank B GPIOs */\n+\t\t\t\tpinctrl-0 = <&pfdigital_irq &pfdigital_pullups>;\n+\t\t\t\tpinctrl-names = \"default\";\n+\t\t\t\tpfdigital_pullups: pinmux {\n+\t\t\t\t\tpins =\n+\t\t\t\t\t\t\"gpio8\",\n+\t\t\t\t\t\t\"gpio9\",\n+\t\t\t\t\t\t\"gpio10\",\n+\t\t\t\t\t\t\"gpio11\",\n+\t\t\t\t\t\t\"gpio12\",\n+\t\t\t\t\t\t\"gpio13\",\n+\t\t\t\t\t\t\"gpio14\",\n+\t\t\t\t\t\t\"gpio15\";\n+\t\t\t\t\tbias-pull-up;\n+\t\t\t\t};\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t/* PiFace Digital mcp23s17 INTB pin is connected to GPIO 25. The INTB\n+\t * pin is configured active-low (0 on interrupt), so expect to see\n+\t * FALLING_EDGE when inputs are bridged to ground (switch is pressed).\n+\t */\n+\tfragment@3 {\n+\t\ttarget = <&gpio>;\n+\t\t__overlay__ {\n+\t\t\tpfdigital_irq: pifacedigital_irq {\n+\t\t\t\tbrcm,pins = <25>;\n+\t\t\t\tbrcm,function = <0>; /* input */\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\tspi-present-mask = <&pfdigital>, \"microchip,spi-present-mask:0\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/piglow-overlay.dts b/arch/arm/boot/dts/overlays/piglow-overlay.dts\nnew file mode 100644\nindex 000000000000..075bceef158c\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/piglow-overlay.dts\n@@ -0,0 +1,97 @@\n+// Definitions for SN3218 LED driver from Si-En Technology on PiGlow\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&i2c_arm>;\n+\t\t__overlay__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tsn3218@54 {\n+\t\t\t\tcompatible = \"si-en,sn3218\";\n+\t\t\t\treg = <0x54>;\n+\t\t\t\t#address-cells = <1>;\n+\t\t\t\t#size-cells = <0>;\n+\t\t\t\tstatus = \"okay\";\n+\n+\t\t\t\tled@1 {\n+\t\t\t\t\treg = <1>;\n+\t\t\t\t\tlabel = \"piglow:red:led1\";\n+\t\t\t\t};\n+\t\t\t\tled@2 {\n+\t\t\t\t\treg = <2>;\n+\t\t\t\t\tlabel = \"piglow:orange:led2\";\n+\t\t\t\t};\n+\t\t\t\tled@3 {\n+\t\t\t\t\treg = <3>;\n+\t\t\t\t\tlabel = \"piglow:yellow:led3\";\n+\t\t\t\t};\n+\t\t\t\tled@4 {\n+\t\t\t\t\treg = <4>;\n+\t\t\t\t\tlabel = \"piglow:green:led4\";\n+\t\t\t\t};\n+\t\t\t\tled@5 {\n+\t\t\t\t\treg = <5>;\n+\t\t\t\t\tlabel = \"piglow:blue:led5\";\n+\t\t\t\t};\n+\t\t\t\tled@6 {\n+\t\t\t\t\treg = <6>;\n+\t\t\t\t\tlabel = \"piglow:green:led6\";\n+\t\t\t\t};\n+\t\t\t\tled@7 {\n+\t\t\t\t\treg = <7>;\n+\t\t\t\t\tlabel = \"piglow:red:led7\";\n+\t\t\t\t};\n+\t\t\t\tled@8 {\n+\t\t\t\t\treg = <8>;\n+\t\t\t\t\tlabel = \"piglow:orange:led8\";\n+\t\t\t\t};\n+\t\t\t\tled@9 {\n+\t\t\t\t\treg = <9>;\n+\t\t\t\t\tlabel = \"piglow:yellow:led9\";\n+\t\t\t\t};\n+\t\t\t\tled@10 {\n+\t\t\t\t\treg = <10>;\n+\t\t\t\t\tlabel = \"piglow:white:led10\";\n+\t\t\t\t};\n+\t\t\t\tled@11 {\n+\t\t\t\t\treg = <11>;\n+\t\t\t\t\tlabel = \"piglow:white:led11\";\n+\t\t\t\t};\n+\t\t\t\tled@12 {\n+\t\t\t\t\treg = <12>;\n+\t\t\t\t\tlabel = \"piglow:blue:led12\";\n+\t\t\t\t};\n+\t\t\t\tled@13 {\n+\t\t\t\t\treg = <13>;\n+\t\t\t\t\tlabel = \"piglow:white:led13\";\n+\t\t\t\t};\n+\t\t\t\tled@14 {\n+\t\t\t\t\treg = <14>;\n+\t\t\t\t\tlabel = \"piglow:green:led14\";\n+\t\t\t\t};\n+\t\t\t\tled@15 {\n+\t\t\t\t\treg = <15>;\n+\t\t\t\t\tlabel = \"piglow:blue:led15\";\n+\t\t\t\t};\n+\t\t\t\tled@16 {\n+\t\t\t\t\treg = <16>;\n+\t\t\t\t\tlabel = \"piglow:yellow:led16\";\n+\t\t\t\t};\n+\t\t\t\tled@17 {\n+\t\t\t\t\treg = <17>;\n+\t\t\t\t\tlabel = \"piglow:orange:led17\";\n+\t\t\t\t};\n+\t\t\t\tled@18 {\n+\t\t\t\t\treg = <18>;\n+\t\t\t\t\tlabel = \"piglow:red:led18\";\n+\t\t\t\t};\n+\t\t\t};\n+\t\t};\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/piscreen-overlay.dts b/arch/arm/boot/dts/overlays/piscreen-overlay.dts\nnew file mode 100644\nindex 000000000000..1ac75a248fab\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/piscreen-overlay.dts\n@@ -0,0 +1,102 @@\n+/*\n+ * Device Tree overlay for PiScreen 3.5\" display shield by Ozzmaker\n+ *\n+ */\n+\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&spi0>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&spidev0>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&spidev1>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\tfragment@3 {\n+\t\ttarget = <&gpio>;\n+\t\t__overlay__ {\n+\t\t\tpiscreen_pins: piscreen_pins {\n+\t\t\t\tbrcm,pins = <17 25 24 22>;\n+\t\t\t\tbrcm,function = <0 1 1 1>; /* in out out out */\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@4 {\n+\t\ttarget = <&spi0>;\n+\t\t__overlay__ {\n+\t\t\t/* needed to avoid dtc warning */\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tpiscreen: piscreen@0{\n+\t\t\t\tcompatible = \"ilitek,ili9486\";\n+\t\t\t\treg = <0>;\n+\t\t\t\tpinctrl-names = \"default\";\n+\t\t\t\tpinctrl-0 = <&piscreen_pins>;\n+\n+\t\t\t\tspi-max-frequency = <24000000>;\n+\t\t\t\trotate = <270>;\n+\t\t\t\tbgr;\n+\t\t\t\tfps = <30>;\n+\t\t\t\tbuswidth = <8>;\n+\t\t\t\tregwidth = <16>;\n+\t\t\t\treset-gpios = <&gpio 25 1>;\n+\t\t\t\tdc-gpios = <&gpio 24 0>;\n+\t\t\t\tled-gpios = <&gpio 22 0>;\n+\t\t\t\tdebug = <0>;\n+\n+\t\t\t\tinit = <0x10000b0 0x00\n+\t\t\t\t        0x1000011\n+\t\t\t\t\t0x20000ff\n+\t\t\t\t\t0x100003a 0x55\n+\t\t\t\t\t0x1000036 0x28\n+\t\t\t\t\t0x10000c2 0x44\n+\t\t\t\t\t0x10000c5 0x00 0x00 0x00 0x00\n+\t\t\t\t\t0x10000e0 0x0f 0x1f 0x1c 0x0c 0x0f 0x08 0x48 0x98 0x37 0x0a 0x13 0x04 0x11 0x0d 0x00\n+\t\t\t\t\t0x10000e1 0x0f 0x32 0x2e 0x0b 0x0d 0x05 0x47 0x75 0x37 0x06 0x10 0x03 0x24 0x20 0x00\n+\t\t\t\t\t0x10000e2 0x0f 0x32 0x2e 0x0b 0x0d 0x05 0x47 0x75 0x37 0x06 0x10 0x03 0x24 0x20 0x00\n+\t\t\t\t\t0x1000011\n+\t\t\t\t\t0x1000029>;\n+\t\t\t};\n+\n+\t\t\tpiscreen_ts: piscreen-ts@1 {\n+\t\t\t\tcompatible = \"ti,ads7846\";\n+\t\t\t\treg = <1>;\n+\n+\t\t\t\tspi-max-frequency = <2000000>;\n+\t\t\t\tinterrupts = <17 2>; /* high-to-low edge triggered */\n+\t\t\t\tinterrupt-parent = <&gpio>;\n+\t\t\t\tpendown-gpio = <&gpio 17 0>;\n+\t\t\t\tti,swap-xy;\n+\t\t\t\tti,x-plate-ohms = /bits/ 16 <100>;\n+\t\t\t\tti,pressure-max = /bits/ 16 <255>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\t__overrides__ {\n+\t\tspeed =\t\t<&piscreen>,\"spi-max-frequency:0\";\n+\t\trotate =\t<&piscreen>,\"rotate:0\";\n+\t\tfps =\t\t<&piscreen>,\"fps:0\";\n+\t\tdebug =\t\t<&piscreen>,\"debug:0\";\n+\t\txohms =\t\t<&piscreen_ts>,\"ti,x-plate-ohms;0\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/piscreen2r-overlay.dts b/arch/arm/boot/dts/overlays/piscreen2r-overlay.dts\nnew file mode 100644\nindex 000000000000..9d2b51101969\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/piscreen2r-overlay.dts\n@@ -0,0 +1,106 @@\n+ /*\n+ * Device Tree overlay for PiScreen2 3.5\" TFT with resistive touch  by Ozzmaker.com\n+ *\n+ */\n+\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&spi0>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&spidev0>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&spidev1>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\tfragment@3 {\n+\t\ttarget = <&gpio>;\n+\t\t__overlay__ {\n+\t\t\tpiscreen2_pins: piscreen2_pins {\n+\t\t\t\tbrcm,pins = <17 25 24 22>;\n+\t\t\t\tbrcm,function = <0 1 1 1>; /* in out out out */\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@4 {\n+\t\ttarget = <&spi0>;\n+\t\t__overlay__ {\n+\t\t\t/* needed to avoid dtc warning */\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tpiscreen2: piscreen2@0{\n+\t\t\t\tcompatible = \"ilitek,ili9486\";\n+\t\t\t\treg = <0>;\n+\t\t\t\tpinctrl-names = \"default\";\n+\t\t\t\tpinctrl-0 = <&piscreen2_pins>;\n+\t\t\t\tbgr;\n+\t\t\t\tspi-max-frequency = <64000000>;\n+\t\t\t\trotate = <90>;\n+\t\t\t\tfps = <30>;\n+\t\t\t\tbuswidth = <8>;\n+\t\t\t\tregwidth = <16>;\n+\t\t\t\ttxbuflen = <32768>;\n+\t\t\t\treset-gpios = <&gpio 25 1>;\n+\t\t\t\tdc-gpios = <&gpio 24 0>;\n+\t\t\t\tled-gpios = <&gpio 22 0>;\n+\t\t\t\tdebug = <0>;\n+\n+                                init = <0x10000b0 0x00\n+                                        0x1000011\n+                                        0x20000ff\n+                                        0x100003a 0x55\n+                                        0x1000036 0x28\n+                                        0x10000c0 0x11 0x09\n+                                        0x10000c1 0x41\n+                                        0x10000c5 0x00 0x00 0x00 0x00\n+                                        0x10000b6 0x00 0x02\n+                                        0x10000f7 0xa9 0x51 0x2c 0x2\n+                                        0x10000be 0x00 0x04\n+                                        0x10000e9 0x00\n+                                        0x1000011\n+                                        0x1000029>;\n+\n+\t\t\t};\n+\n+\t\t\tpiscreen2_ts: piscreen2-ts@1 {\n+\t\t\t\tcompatible = \"ti,ads7846\";\n+\t\t\t\treg = <1>;\n+\n+\t\t\t\tspi-max-frequency = <2000000>;\n+\t\t\t\tinterrupts = <17 2>; /* high-to-low edge triggered */\n+\t\t\t\tinterrupt-parent = <&gpio>;\n+\t\t\t\tpendown-gpio = <&gpio 17 0>;\n+\t\t\t\tti,swap-xy;\n+\t\t\t\tti,x-plate-ohms = /bits/ 16 <100>;\n+\t\t\t\tti,pressure-max = /bits/ 16 <255>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\t__overrides__ {\n+\t\tspeed =\t\t<&piscreen2>,\"spi-max-frequency:0\";\n+\t\trotate =\t<&piscreen2>,\"rotate:0\";\n+\t\tfps =\t\t<&piscreen2>,\"fps:0\";\n+\t\tdebug =\t\t<&piscreen2>,\"debug:0\";\n+\t\txohms =\t\t<&piscreen2_ts>,\"ti,x-plate-ohms;0\";\n+\t};\n+};\n+\ndiff --git a/arch/arm/boot/dts/overlays/pisound-overlay.dts b/arch/arm/boot/dts/overlays/pisound-overlay.dts\nnew file mode 100644\nindex 000000000000..49efb2b768fb\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/pisound-overlay.dts\n@@ -0,0 +1,120 @@\n+/*\n+ * Pisound Linux kernel module.\n+ * Copyright (C) 2016-2017  Vilniaus Blokas UAB, https://blokas.io/pisound\n+ *\n+ * This program is free software; you can redistribute it and/or\n+ * modify it under the terms of the GNU General Public License\n+ * as published by the Free Software Foundation; version 2 of the\n+ * License.\n+ *\n+ * This program is distributed in the hope that it will be useful,\n+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\n+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n+ * GNU General Public License for more details.\n+ *\n+ * You should have received a copy of the GNU General Public License\n+ * along with this program; if not, write to the Free Software\n+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.\n+ */\n+\n+/dts-v1/;\n+/plugin/;\n+\n+#include <dt-bindings/gpio/gpio.h>\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&spi0>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&spidev0>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&spidev1>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@3 {\n+\t\ttarget = <&spi0>;\n+\t\t__overlay__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tpisound_spi: pisound_spi@0{\n+\t\t\t\tcompatible = \"blokaslabs,pisound-spi\";\n+\t\t\t\treg = <0>;\n+\t\t\t\tpinctrl-names = \"default\";\n+\t\t\t\tpinctrl-0 = <&spi0_pins>;\n+\t\t\t\tspi-max-frequency = <1000000>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@4 {\n+\t\ttarget-path = \"/\";\n+\t\t__overlay__ {\n+\t\t\tpcm5102a-codec {\n+\t\t\t\t#sound-dai-cells = <0>;\n+\t\t\t\tcompatible = \"ti,pcm5102a\";\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@5 {\n+\t\ttarget = <&sound>;\n+\t\t__overlay__ {\n+\t\t\tcompatible = \"blokaslabs,pisound\";\n+\t\t\ti2s-controller = <&i2s>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tpinctrl-0 = <&pisound_button_pins>;\n+\n+\t\t\tosr-gpios =\n+\t\t\t\t<&gpio 13 GPIO_ACTIVE_HIGH>,\n+\t\t\t\t<&gpio 26 GPIO_ACTIVE_HIGH>,\n+\t\t\t\t<&gpio 16 GPIO_ACTIVE_HIGH>;\n+\n+\t\t\treset-gpios =\n+\t\t\t\t<&gpio 12 GPIO_ACTIVE_HIGH>,\n+\t\t\t\t<&gpio 24 GPIO_ACTIVE_HIGH>;\n+\n+\t\t\tdata_available-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;\n+\n+\t\t\tbutton-gpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\t};\n+\n+\tfragment@6 {\n+\t\ttarget = <&gpio>;\n+\t\t__overlay__ {\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&pisound_button_pins>;\n+\n+\t\t\tpisound_button_pins: pisound_button_pins {\n+\t\t\t\tbrcm,pins = <17>;\n+\t\t\t\tbrcm,function = <0>; // Input\n+\t\t\t\tbrcm,pull = <2>; // Pull-Up\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@7 {\n+\t\ttarget = <&i2s>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/pitft22-overlay.dts b/arch/arm/boot/dts/overlays/pitft22-overlay.dts\nnew file mode 100644\nindex 000000000000..589ad13795b1\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/pitft22-overlay.dts\n@@ -0,0 +1,69 @@\n+/*\n+ * Device Tree overlay for pitft by Adafruit\n+ *\n+ */\n+\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+        compatible = \"brcm,bcm2835\";\n+\n+        fragment@0 {\n+                target = <&spi0>;\n+                __overlay__ {\n+                        status = \"okay\";\n+\n+                        spidev@0{\n+                                status = \"disabled\";\n+                        };\n+\n+                        spidev@1{\n+                                status = \"disabled\";\n+                        };\n+                };\n+        };\n+\n+        fragment@1 {\n+                target = <&gpio>;\n+                __overlay__ {\n+                        pitft_pins: pitft_pins {\n+                                brcm,pins = <25>;\n+                                brcm,function = <1>; /* out */\n+                                brcm,pull = <0>; /* none */\n+                        };\n+                };\n+        };\n+\n+        fragment@2 {\n+                target = <&spi0>;\n+                __overlay__ {\n+                        /* needed to avoid dtc warning */\n+                        #address-cells = <1>;\n+                        #size-cells = <0>;\n+\n+                        pitft: pitft@0{\n+                                compatible = \"ilitek,ili9340\";\n+                                reg = <0>;\n+                                pinctrl-names = \"default\";\n+                                pinctrl-0 = <&pitft_pins>;\n+\n+                                spi-max-frequency = <32000000>;\n+                                rotate = <90>;\n+                                fps = <25>;\n+                                bgr;\n+                                buswidth = <8>;\n+                                dc-gpios = <&gpio 25 0>;\n+                                debug = <0>;\n+                        };\n+\n+                };\n+        };\n+\n+        __overrides__ {\n+                speed =   <&pitft>,\"spi-max-frequency:0\";\n+                rotate =  <&pitft>,\"rotate:0\";\n+                fps =     <&pitft>,\"fps:0\";\n+                debug =   <&pitft>,\"debug:0\";\n+        };\n+};\ndiff --git a/arch/arm/boot/dts/overlays/pitft28-capacitive-overlay.dts b/arch/arm/boot/dts/overlays/pitft28-capacitive-overlay.dts\nnew file mode 100644\nindex 000000000000..33901ee1db7a\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/pitft28-capacitive-overlay.dts\n@@ -0,0 +1,91 @@\n+/*\n+ * Device Tree overlay for Adafruit PiTFT 2.8\" capacitive touch screen\n+ *\n+ */\n+\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+        compatible = \"brcm,bcm2835\";\n+\n+        fragment@0 {\n+                target = <&spi0>;\n+                __overlay__ {\n+                        status = \"okay\";\n+                };\n+        };\n+\n+\tfragment@1 {\n+\t\ttarget = <&spidev0>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+        fragment@2 {\n+                target = <&gpio>;\n+                __overlay__ {\n+                        pitft_pins: pitft_pins {\n+                                brcm,pins = <24 25>;\n+                                brcm,function = <0 1>; /* in out */\n+                                brcm,pull = <2 0>; /* pullup none */\n+                        };\n+                };\n+        };\n+\n+        fragment@3 {\n+                target = <&spi0>;\n+                __overlay__ {\n+                        /* needed to avoid dtc warning */\n+                        #address-cells = <1>;\n+                        #size-cells = <0>;\n+\n+                        pitft: pitft@0{\n+                                compatible = \"ilitek,ili9340\";\n+                                reg = <0>;\n+                                pinctrl-names = \"default\";\n+                                pinctrl-0 = <&pitft_pins>;\n+\n+                                spi-max-frequency = <32000000>;\n+                                rotate = <90>;\n+                                fps = <25>;\n+                                bgr;\n+                                buswidth = <8>;\n+                                dc-gpios = <&gpio 25 0>;\n+                                debug = <0>;\n+                        };\n+                };\n+        };\n+\n+        fragment@4 {\n+                target = <&i2c1>;\n+                __overlay__ {\n+                        /* needed to avoid dtc warning */\n+                        #address-cells = <1>;\n+                        #size-cells = <0>;\n+\n+                        ft6236: ft6236@38 {\n+                                compatible = \"focaltech,ft6236\";\n+                                reg = <0x38>;\n+\n+                                interrupt-parent = <&gpio>;\n+                                interrupts = <24 2>;\n+                                touchscreen-size-x = <240>;\n+                                touchscreen-size-y = <320>;\n+                        };\n+                };\n+        };\n+\n+        __overrides__ {\n+                speed =   <&pitft>,\"spi-max-frequency:0\";\n+                rotate =  <&pitft>,\"rotate:0\";\n+                fps =     <&pitft>,\"fps:0\";\n+                debug =   <&pitft>,\"debug:0\";\n+                touch-sizex = <&ft6236>,\"touchscreen-size-x?\";\n+                touch-sizey = <&ft6236>,\"touchscreen-size-y?\";\n+                touch-invx  = <&ft6236>,\"touchscreen-inverted-x?\";\n+                touch-invy  = <&ft6236>,\"touchscreen-inverted-y?\";\n+                touch-swapxy = <&ft6236>,\"touchscreen-swapped-x-y?\";\n+        };\n+};\ndiff --git a/arch/arm/boot/dts/overlays/pitft28-resistive-overlay.dts b/arch/arm/boot/dts/overlays/pitft28-resistive-overlay.dts\nnew file mode 100644\nindex 000000000000..4a4a3f44c29d\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/pitft28-resistive-overlay.dts\n@@ -0,0 +1,119 @@\n+/*\n+ * Device Tree overlay for Adafruit PiTFT 2.8\" resistive touch screen\n+ *\n+ */\n+\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&spi0>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&spidev0>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&spidev1>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\tfragment@3 {\n+\t\ttarget = <&gpio>;\n+\t\t__overlay__ {\n+\t\t\tpitft_pins: pitft_pins {\n+\t\t\t\tbrcm,pins = <24 25>;\n+\t\t\t\tbrcm,function = <0 1>; /* in out */\n+\t\t\t\tbrcm,pull = <2 0>; /* pullup none */\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@4 {\n+\t\ttarget = <&spi0>;\n+\t\t__overlay__ {\n+\t\t\t/* needed to avoid dtc warning */\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tpitft: pitft@0{\n+\t\t\t\tcompatible = \"ilitek,ili9340\";\n+\t\t\t\treg = <0>;\n+\t\t\t\tpinctrl-names = \"default\";\n+\t\t\t\tpinctrl-0 = <&pitft_pins>;\n+\n+\t\t\t\tspi-max-frequency = <32000000>;\n+\t\t\t\trotate = <90>;\n+\t\t\t\tfps = <25>;\n+\t\t\t\tbgr;\n+\t\t\t\tbuswidth = <8>;\n+\t\t\t\tdc-gpios = <&gpio 25 0>;\n+\t\t\t\tdebug = <0>;\n+\t\t\t};\n+\n+\t\t\tpitft_ts@1 {\n+\t\t\t\tcompatible = \"st,stmpe610\";\n+\t\t\t\treg = <1>;\n+\n+\t\t\t\tspi-max-frequency = <500000>;\n+\t\t\t\tirq-gpio = <&gpio 24 0x2>; /* IRQF_TRIGGER_FALLING */\n+\t\t\t\tinterrupts = <24 2>; /* high-to-low edge triggered */\n+\t\t\t\tinterrupt-parent = <&gpio>;\n+\t\t\t\tinterrupt-controller;\n+\n+\t\t\t\tstmpe_touchscreen {\n+\t\t\t\t\tcompatible = \"st,stmpe-ts\";\n+\t\t\t\t\tst,sample-time = <4>;\n+\t\t\t\t\tst,mod-12b = <1>;\n+\t\t\t\t\tst,ref-sel = <0>;\n+\t\t\t\t\tst,adc-freq = <2>;\n+\t\t\t\t\tst,ave-ctrl = <3>;\n+\t\t\t\t\tst,touch-det-delay = <4>;\n+\t\t\t\t\tst,settling = <2>;\n+\t\t\t\t\tst,fraction-z = <7>;\n+\t\t\t\t\tst,i-drive = <0>;\n+\t\t\t\t};\n+\n+\t\t\t\tstmpe_gpio: stmpe_gpio {\n+\t\t\t\t\t#gpio-cells = <2>;\n+\t\t\t\t\tcompatible = \"st,stmpe-gpio\";\n+\t\t\t\t\t/*\n+\t\t\t\t\t * only GPIO2 is wired/available\n+\t\t\t\t\t * and it is wired to the backlight\n+\t\t\t\t\t */\n+\t\t\t\t\tst,norequest-mask = <0x7b>;\n+\t\t\t\t};\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@5 {\n+\t\ttarget-path = \"/soc\";\n+\t\t__overlay__ {\n+\t\t\tbacklight {\n+\t\t\t\tcompatible = \"gpio-backlight\";\n+\t\t\t\tgpios = <&stmpe_gpio 2 0>;\n+\t\t\t\tdefault-on;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\tspeed =   <&pitft>,\"spi-max-frequency:0\";\n+\t\trotate =  <&pitft>,\"rotate:0\";\n+\t\tfps =     <&pitft>,\"fps:0\";\n+\t\tdebug =   <&pitft>,\"debug:0\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/pitft35-resistive-overlay.dts b/arch/arm/boot/dts/overlays/pitft35-resistive-overlay.dts\nnew file mode 100644\nindex 000000000000..37629f18a740\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/pitft35-resistive-overlay.dts\n@@ -0,0 +1,119 @@\n+/*\n+ * Device Tree overlay for Adafruit PiTFT 3.5\" resistive touch screen\n+ *\n+ */\n+\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&spi0>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&spidev0>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&spidev1>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\tfragment@3 {\n+\t\ttarget = <&gpio>;\n+\t\t__overlay__ {\n+\t\t\tpitft_pins: pitft_pins {\n+\t\t\t\tbrcm,pins = <24 25>;\n+\t\t\t\tbrcm,function = <0 1>; /* in out */\n+\t\t\t\tbrcm,pull = <2 0>; /* pullup none */\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@4 {\n+\t\ttarget = <&spi0>;\n+\t\t__overlay__ {\n+\t\t\t/* needed to avoid dtc warning */\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tpitft: pitft@0{\n+\t\t\t\tcompatible = \"himax,hx8357d\", \"adafruit,yx350hv15\";\n+\t\t\t\treg = <0>;\n+\t\t\t\tpinctrl-names = \"default\";\n+\t\t\t\tpinctrl-0 = <&pitft_pins>;\n+\n+\t\t\t\tspi-max-frequency = <32000000>;\n+\t\t\t\trotate = <90>;\n+\t\t\t\tfps = <25>;\n+\t\t\t\tbgr;\n+\t\t\t\tbuswidth = <8>;\n+\t\t\t\tdc-gpios = <&gpio 25 0>;\n+\t\t\t\tdebug = <0>;\n+\t\t\t};\n+\n+\t\t\tpitft_ts@1 {\n+\t\t\t\tcompatible = \"st,stmpe610\";\n+\t\t\t\treg = <1>;\n+\n+\t\t\t\tspi-max-frequency = <500000>;\n+\t\t\t\tirq-gpio = <&gpio 24 0x2>; /* IRQF_TRIGGER_FALLING */\n+\t\t\t\tinterrupts = <24 2>; /* high-to-low edge triggered */\n+\t\t\t\tinterrupt-parent = <&gpio>;\n+\t\t\t\tinterrupt-controller;\n+\n+\t\t\t\tstmpe_touchscreen {\n+\t\t\t\t\tcompatible = \"st,stmpe-ts\";\n+\t\t\t\t\tst,sample-time = <4>;\n+\t\t\t\t\tst,mod-12b = <1>;\n+\t\t\t\t\tst,ref-sel = <0>;\n+\t\t\t\t\tst,adc-freq = <2>;\n+\t\t\t\t\tst,ave-ctrl = <3>;\n+\t\t\t\t\tst,touch-det-delay = <4>;\n+\t\t\t\t\tst,settling = <2>;\n+\t\t\t\t\tst,fraction-z = <7>;\n+\t\t\t\t\tst,i-drive = <0>;\n+\t\t\t\t};\n+\n+\t\t\t\tstmpe_gpio: stmpe_gpio {\n+\t\t\t\t\t#gpio-cells = <2>;\n+\t\t\t\t\tcompatible = \"st,stmpe-gpio\";\n+\t\t\t\t\t/*\n+\t\t\t\t\t * only GPIO2 is wired/available\n+\t\t\t\t\t * and it is wired to the backlight\n+\t\t\t\t\t */\n+\t\t\t\t\tst,norequest-mask = <0x7b>;\n+\t\t\t\t};\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@5 {\n+\t\ttarget-path = \"/soc\";\n+\t\t__overlay__ {\n+\t\t\tbacklight {\n+\t\t\t\tcompatible = \"gpio-backlight\";\n+\t\t\t\tgpios = <&stmpe_gpio 2 0>;\n+\t\t\t\tdefault-on;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\tspeed =   <&pitft>,\"spi-max-frequency:0\";\n+\t\trotate =  <&pitft>,\"rotate:0\";\n+\t\tfps =     <&pitft>,\"fps:0\";\n+\t\tdebug =   <&pitft>,\"debug:0\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/pps-gpio-overlay.dts b/arch/arm/boot/dts/overlays/pps-gpio-overlay.dts\nnew file mode 100644\nindex 000000000000..524a1c1d3670\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/pps-gpio-overlay.dts\n@@ -0,0 +1,38 @@\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\tfragment@0 {\n+\t\ttarget-path = \"/\";\n+\t\t__overlay__ {\n+\t\t\tpps: pps@12 {\n+\t\t\t\tcompatible = \"pps-gpio\";\n+\t\t\t\tpinctrl-names = \"default\";\n+\t\t\t\tpinctrl-0 = <&pps_pins>;\n+\t\t\t\tgpios = <&gpio 18 0>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&gpio>;\n+\t\t__overlay__ {\n+\t\t\tpps_pins: pps_pins@12 {\n+\t\t\t\tbrcm,pins =     <18>;\n+\t\t\t\tbrcm,function = <0>;    // in\n+\t\t\t\tbrcm,pull =     <0>;    // off\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\tgpiopin = <&pps>,\"gpios:4\",\n+\t\t\t  <&pps>,\"reg:0\",\n+\t\t\t  <&pps_pins>,\"brcm,pins:0\",\n+\t\t\t  <&pps_pins>,\"reg:0\";\n+\t\tassert_falling_edge = <&pps>,\"assert-falling-edge?\";\n+\t\tcapture_clear = <&pps>,\"capture-clear?\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/pwm-2chan-overlay.dts b/arch/arm/boot/dts/overlays/pwm-2chan-overlay.dts\nnew file mode 100644\nindex 000000000000..4ddbbfa04065\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/pwm-2chan-overlay.dts\n@@ -0,0 +1,49 @@\n+/dts-v1/;\n+/plugin/;\n+\n+/*\n+This is the 2-channel overlay - only use it if you need both channels.\n+\n+Legal pin,function combinations for each channel:\n+  PWM0: 12,4(Alt0) 18,2(Alt5) 40,4(Alt0)            52,5(Alt1)\n+  PWM1: 13,4(Alt0) 19,2(Alt5) 41,4(Alt0) 45,4(Alt0) 53,5(Alt1)\n+\n+N.B.:\n+  1) Pin 18 is the only one available on all platforms, and\n+     it is the one used by the I2S audio interface.\n+     Pins 12 and 13 might be better choices on an A+, B+ or Pi2.\n+  2) The onboard analogue audio output uses both PWM channels.\n+  3) So be careful mixing audio and PWM.\n+*/\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&gpio>;\n+\t\t__overlay__ {\n+\t\t\tpwm_pins: pwm_pins {\n+\t\t\t\tbrcm,pins = <18 19>;\n+\t\t\t\tbrcm,function = <2 2>; /* Alt5 */\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&pwm>;\n+\t\tfrag1: __overlay__ {\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&pwm_pins>;\n+\t\t\tassigned-clock-rates = <100000000>;\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\tpin   = <&pwm_pins>,\"brcm,pins:0\";\n+\t\tpin2  = <&pwm_pins>,\"brcm,pins:4\";\n+\t\tfunc  = <&pwm_pins>,\"brcm,function:0\";\n+\t\tfunc2 = <&pwm_pins>,\"brcm,function:4\";\n+\t\tclock = <&frag1>,\"assigned-clock-rates:0\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/pwm-ir-tx-overlay.dts b/arch/arm/boot/dts/overlays/pwm-ir-tx-overlay.dts\nnew file mode 100644\nindex 000000000000..119caf746b3b\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/pwm-ir-tx-overlay.dts\n@@ -0,0 +1,40 @@\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&gpio>;\n+\t\t__overlay__ {\n+\t\t\tpwm0_pins: pwm0_pins {\n+\t\t\t\tbrcm,pins = <18>;\n+\t\t\t\tbrcm,function = <2>; /* Alt5 */\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&pwm>;\n+\t\t__overlay__ {\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&pwm0_pins>;\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget-path = \"/\";\n+\t\t__overlay__ {\n+\t\t\tpwm-ir-transmitter {\n+\t\t\t\tcompatible = \"pwm-ir-tx\";\n+\t\t\t\tpwms = <&pwm 0 100>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\tgpio_pin = <&pwm0_pins>, \"brcm,pins:0\";\n+\t\tfunc = <&pwm0_pins>,\"brcm,function:0\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/pwm-overlay.dts b/arch/arm/boot/dts/overlays/pwm-overlay.dts\nnew file mode 100644\nindex 000000000000..92876ab3bc8c\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/pwm-overlay.dts\n@@ -0,0 +1,45 @@\n+/dts-v1/;\n+/plugin/;\n+\n+/*\n+Legal pin,function combinations for each channel:\n+  PWM0: 12,4(Alt0) 18,2(Alt5) 40,4(Alt0)            52,5(Alt1)\n+  PWM1: 13,4(Alt0) 19,2(Alt5) 41,4(Alt0) 45,4(Alt0) 53,5(Alt1)\n+\n+N.B.:\n+  1) Pin 18 is the only one available on all platforms, and\n+     it is the one used by the I2S audio interface.\n+     Pins 12 and 13 might be better choices on an A+, B+ or Pi2.\n+  2) The onboard analogue audio output uses both PWM channels.\n+  3) So be careful mixing audio and PWM.\n+*/\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&gpio>;\n+\t\t__overlay__ {\n+\t\t\tpwm_pins: pwm_pins {\n+\t\t\t\tbrcm,pins = <18>;\n+\t\t\t\tbrcm,function = <2>; /* Alt5 */\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&pwm>;\n+\t\tfrag1: __overlay__ {\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&pwm_pins>;\n+\t\t\tassigned-clock-rates = <100000000>;\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\tpin   = <&pwm_pins>,\"brcm,pins:0\";\n+\t\tfunc  = <&pwm_pins>,\"brcm,function:0\";\n+\t\tclock = <&frag1>,\"assigned-clock-rates:0\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/qca7000-overlay.dts b/arch/arm/boot/dts/overlays/qca7000-overlay.dts\nnew file mode 100644\nindex 000000000000..9a451202a2eb\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/qca7000-overlay.dts\n@@ -0,0 +1,55 @@\n+// Overlay for the Qualcomm Atheros QCA7000 on I2SE's PLC Stamp micro EVK\n+// Visit: https://www.i2se.com/product/plc-stamp-micro-evk for details\n+\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&spidev0>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&spi0>;\n+\t\t__overlay__ {\n+\t\t\t/* needed to avoid dtc warning */\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\teth1: qca7000@0 {\n+\t\t\t\tcompatible = \"qca,qca7000\";\n+\t\t\t\treg = <0>; /* CE0 */\n+\t\t\t\tpinctrl-names = \"default\";\n+\t\t\t\tpinctrl-0 = <&eth1_pins>;\n+\t\t\t\tinterrupt-parent = <&gpio>;\n+\t\t\t\tinterrupts = <23 0x1>; /* rising edge */\n+\t\t\t\tspi-max-frequency = <12000000>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&gpio>;\n+\t\t__overlay__ {\n+\t\t\teth1_pins: eth1_pins {\n+\t\t\t\tbrcm,pins = <23>;\n+\t\t\t\tbrcm,function = <0>; /* in */\n+\t\t\t\tbrcm,pull = <0>; /* none */\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\tint_pin = <&eth1>, \"interrupts:0\",\n+\t\t          <&eth1_pins>, \"brcm,pins:0\";\n+\t\tspeed   = <&eth1>, \"spi-max-frequency:0\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/rotary-encoder-overlay.dts b/arch/arm/boot/dts/overlays/rotary-encoder-overlay.dts\nnew file mode 100644\nindex 000000000000..ea1d952734e9\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/rotary-encoder-overlay.dts\n@@ -0,0 +1,59 @@\n+// Device tree overlay for GPIO connected rotary encoder.\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&gpio>;\n+\t\t__overlay__ {\n+\t\t\trotary_pins: rotary_pins@4 {\n+\t\t\t\tbrcm,pins = <4 17>; /* gpio 4 17 */\n+\t\t\t\tbrcm,function = <0 0>; /* input */\n+\t\t\t\tbrcm,pull = <2 2>; /* pull-up */\n+\t\t\t};\n+\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget-path = \"/\";\n+\t\t__overlay__ {\n+\t\t\trotary: rotary@4 {\n+\t\t\t\tcompatible = \"rotary-encoder\";\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t\tpinctrl-names = \"default\";\n+\t\t\t\tpinctrl-0 = <&rotary_pins>;\n+\t\t\t\tgpios = <&gpio 4 0>, <&gpio 17 0>;\n+\t\t\t\tlinux,axis = <0>; /* REL_X */\n+\t\t\t\trotary-encoder,encoding = \"gray\";\n+\t\t\t\trotary-encoder,steps = <24>; /* 24 default */\n+\t\t\t\trotary-encoder,steps-per-period = <1>; /* corresponds to full period mode. See README */\n+\t\t\t};\n+\t\t};\n+\n+\t};  \n+\n+\t__overrides__ {\n+\t\tpin_a =\t\t    <&rotary>,\"gpios:4\",\n+\t\t\t\t    <&rotary_pins>,\"brcm,pins:0\",\n+\t\t\t\t    /* modify reg values to allow multiple instantiation */\n+\t\t\t\t    <&rotary>,\"reg:0\",\n+\t\t\t\t    <&rotary_pins>,\"reg:0\";\n+\t\tpin_b =\t\t    <&rotary>,\"gpios:16\",\n+\t\t\t\t    <&rotary_pins>,\"brcm,pins:4\";\n+\t\trelative_axis =     <&rotary>,\"rotary-encoder,relative-axis?\";\n+\t\tlinux_axis =        <&rotary>,\"linux,axis:0\";\n+\t\trollover =          <&rotary>,\"rotary-encoder,rollover?\";\n+\t\tsteps-per-period =  <&rotary>,\"rotary-encoder,steps-per-period:0\";\n+\t\tsteps =             <&rotary>,\"rotary-encoder,steps:0\";\n+\t\twakeup =            <&rotary>,\"wakeup-source?\";\n+\t\tencoding =          <&rotary>,\"rotary-encoder,encoding\";\n+                /* legacy parameters*/\n+\t\trotary0_pin_a =     <&rotary>,\"gpios:4\",\n+\t\t                    <&rotary_pins>,\"brcm,pins:0\";\n+\t\trotary0_pin_b =     <&rotary>,\"gpios:16\",\n+\t\t                    <&rotary_pins>,\"brcm,pins:4\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/rpi-backlight-overlay.dts b/arch/arm/boot/dts/overlays/rpi-backlight-overlay.dts\nnew file mode 100644\nindex 000000000000..cac5e44c6ec5\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/rpi-backlight-overlay.dts\n@@ -0,0 +1,21 @@\n+/*\n+ * Devicetree overlay for mailbox-driven Raspberry Pi DSI Display\n+ * backlight controller\n+ */\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget-path = \"/\";\n+\t\t__overlay__ {\n+\t\t\trpi_backlight: rpi_backlight {\n+\t\t\t\tcompatible = \"raspberrypi,rpi-backlight\";\n+\t\t\t\tfirmware = <&firmware>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/rpi-cirrus-wm5102-overlay.dts b/arch/arm/boot/dts/overlays/rpi-cirrus-wm5102-overlay.dts\nnew file mode 100644\nindex 000000000000..ed0c2745399f\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/rpi-cirrus-wm5102-overlay.dts\n@@ -0,0 +1,172 @@\n+// Definitions for the Cirrus Logic Audio Card\n+/dts-v1/;\n+/plugin/;\n+#include <dt-bindings/pinctrl/bcm2835.h>\n+#include <dt-bindings/gpio/gpio.h>\n+#include <dt-bindings/mfd/arizona.h>\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&i2s>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&gpio>;\n+\t\t__overlay__ {\n+\t\t\twlf_5102_pins: wlf_5102_pins {\n+\t\t\t\tbrcm,pins = <17 22 27>;\n+\t\t\t\tbrcm,function = <\n+\t\t\t\t\tBCM2835_FSEL_GPIO_OUT\n+\t\t\t\t\tBCM2835_FSEL_GPIO_OUT\n+\t\t\t\t\tBCM2835_FSEL_GPIO_IN\n+\t\t\t\t>;\n+\t\t\t};\n+\t\t\twlf_8804_pins: wlf_8804_pins {\n+\t\t\t\tbrcm,pins = <8>;\n+\t\t\t\tbrcm,function = <BCM2835_FSEL_GPIO_OUT>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&spi0_cs_pins>;\n+\t\t__overlay__ {\n+\t\t\tbrcm,pins = <7>;\n+\t\t\tbrcm,function = <BCM2835_FSEL_GPIO_OUT>;\n+\t\t};\n+\t};\n+\n+\n+\tfragment@3 {\n+\t\ttarget-path = \"/\";\n+\t\t__overlay__ {\n+\t\t\trpi_cirrus_reg_1v8: rpi_cirrus_reg_1v8 {\n+\t\t\t\tcompatible = \"regulator-fixed\";\n+\t\t\t\tregulator-name = \"RPi-Cirrus 1v8\";\n+\t\t\t\tregulator-min-microvolt = <1800000>;\n+\t\t\t\tregulator-max-microvolt = <1800000>;\n+\t\t\t\tregulator-always-on;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@4 {\n+\t\ttarget = <&spidev0>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\tfragment@5 {\n+\t\ttarget = <&spidev1>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\tfragment@6 {\n+\t\ttarget = <&spi0>;\n+\t\t__overlay__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\t\t\tcs-gpios = <&gpio 7 GPIO_ACTIVE_LOW>;\n+\n+\t\t\twm5102@0{\n+\t\t\t\tcompatible = \"wlf,wm5102\";\n+\t\t\t\treg = <0>;\n+\n+\t\t\t\tpinctrl-names = \"default\";\n+\t\t\t\tpinctrl-0 = <&wlf_5102_pins>;\n+\n+\t\t\t\tspi-max-frequency = <500000>;\n+\n+\t\t\t\tinterrupt-parent = <&gpio>;\n+\t\t\t\tinterrupts = <27 8>;\n+\t\t\t\tinterrupt-controller;\n+\t\t\t\t#interrupt-cells = <2>;\n+\n+\t\t\t\tgpio-controller;\n+\t\t\t\t#gpio-cells = <2>;\n+\n+\t\t\t\tLDOVDD-supply = <&rpi_cirrus_reg_1v8>;\n+\t\t\t\tAVDD-supply = <&rpi_cirrus_reg_1v8>;\n+\t\t\t\tDBVDD1-supply = <&rpi_cirrus_reg_1v8>;\n+\t\t\t\tDBVDD2-supply = <&vdd_3v3_reg>;\n+\t\t\t\tDBVDD3-supply = <&vdd_3v3_reg>;\n+\t\t\t\tCPVDD-supply = <&rpi_cirrus_reg_1v8>;\n+\t\t\t\tSPKVDDL-supply = <&vdd_5v0_reg>;\n+\t\t\t\tSPKVDDR-supply = <&vdd_5v0_reg>;\n+\t\t\t\tDCVDD-supply = <&arizona_ldo1>;\n+\n+\t\t\t\treset-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n+\t\t\t\twlf,ldoena = <&gpio 22 GPIO_ACTIVE_HIGH>;\n+\t\t\t\twlf,gpio-defaults = <\n+\t\t\t\t\tARIZONA_GP_DEFAULT\n+\t\t\t\t\tARIZONA_GP_DEFAULT\n+\t\t\t\t\tARIZONA_GP_DEFAULT\n+\t\t\t\t\tARIZONA_GP_DEFAULT\n+\t\t\t\t\tARIZONA_GP_DEFAULT\n+\t\t\t\t>;\n+\t\t\t\twlf,micd-configs = <0 1 0>;\n+\t\t\t\twlf,dmic-ref = <\n+\t\t\t\t\tARIZONA_DMIC_MICVDD\n+\t\t\t\t\tARIZONA_DMIC_MICBIAS2\n+\t\t\t\t\tARIZONA_DMIC_MICVDD\n+\t\t\t\t\tARIZONA_DMIC_MICVDD\n+\t\t\t\t>;\n+\t\t\t\twlf,inmode = <\n+\t\t\t\t\tARIZONA_INMODE_DIFF\n+\t\t\t\t\tARIZONA_INMODE_DMIC\n+\t\t\t\t\tARIZONA_INMODE_SE\n+\t\t\t\t\tARIZONA_INMODE_DIFF\n+\t\t\t\t>;\n+\t\t\t\tstatus = \"okay\";\n+\n+\t\t\t\tarizona_ldo1: ldo1 {\n+\t\t\t\t\tregulator-name = \"LDO1\";\n+\t\t\t\t\t// default constraints as in\n+\t\t\t\t\t// arizona-ldo1.c\n+\t\t\t\t\tregulator-min-microvolt = <1200000>;\n+\t\t\t\t\tregulator-max-microvolt = <1800000>;\n+\t\t\t\t};\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@7 {\n+\t\ttarget = <&i2c1>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\twm8804@3b {\n+\t\t\t\tcompatible = \"wlf,wm8804\";\n+\t\t\t\treg = <0x3b>;\n+\t\t\t\tstatus = \"okay\";\n+\n+\t\t\t\tpinctrl-names = \"default\";\n+\t\t\t\tpinctrl-0 = <&wlf_8804_pins>;\n+\n+\t\t\t\tPVDD-supply = <&vdd_3v3_reg>;\n+\t\t\t\tDVDD-supply = <&vdd_3v3_reg>;\n+\t\t\t\twlf,reset-gpio = <&gpio 8 GPIO_ACTIVE_HIGH>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@8 {\n+\t\ttarget = <&sound>;\n+\t\t__overlay__ {\n+\t\t\tcompatible = \"wlf,rpi-cirrus\";\n+\t\t\ti2s-controller = <&i2s>;\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/rpi-dac-overlay.dts b/arch/arm/boot/dts/overlays/rpi-dac-overlay.dts\nnew file mode 100644\nindex 000000000000..07a915342702\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/rpi-dac-overlay.dts\n@@ -0,0 +1,34 @@\n+// Definitions for RPi DAC\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&i2s>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget-path = \"/\";\n+\t\t__overlay__ {\n+\t\t\tpcm1794a-codec {\n+\t\t\t\t#sound-dai-cells = <0>;\n+\t\t\t\tcompatible = \"ti,pcm1794a\";\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&sound>;\n+\t\t__overlay__ {\n+\t\t\tcompatible = \"rpi,rpi-dac\";\n+\t\t\ti2s-controller = <&i2s>;\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/rpi-display-overlay.dts b/arch/arm/boot/dts/overlays/rpi-display-overlay.dts\nnew file mode 100644\nindex 000000000000..de87432ff2be\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/rpi-display-overlay.dts\n@@ -0,0 +1,91 @@\n+/*\n+ * Device Tree overlay for rpi-display by Watterott\n+ *\n+ */\n+\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&spi0>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&spidev0>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&spidev1>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\tfragment@3 {\n+\t\ttarget = <&gpio>;\n+\t\t__overlay__ {\n+\t\t\trpi_display_pins: rpi_display_pins {\n+\t\t\t\tbrcm,pins = <18 23 24 25>;\n+\t\t\t\tbrcm,function = <1 1 1 0>; /* out out out in */\n+\t\t\t\tbrcm,pull = <0 0 0 2>; /* - - - up */\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@4 {\n+\t\ttarget = <&spi0>;\n+\t\t__overlay__ {\n+\t\t\t/* needed to avoid dtc warning */\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\trpidisplay: rpi-display@0{\n+\t\t\t\tcompatible = \"ilitek,ili9341\";\n+\t\t\t\treg = <0>;\n+\t\t\t\tpinctrl-names = \"default\";\n+\t\t\t\tpinctrl-0 = <&rpi_display_pins>;\n+\n+\t\t\t\tspi-max-frequency = <32000000>;\n+\t\t\t\trotate = <270>;\n+\t\t\t\tbgr;\n+\t\t\t\tfps = <30>;\n+\t\t\t\tbuswidth = <8>;\n+\t\t\t\treset-gpios = <&gpio 23 1>;\n+\t\t\t\tdc-gpios = <&gpio 24 0>;\n+\t\t\t\tled-gpios = <&gpio 18 0>;\n+\t\t\t\tdebug = <0>;\n+\t\t\t};\n+\n+\t\t\trpidisplay_ts: rpi-display-ts@1 {\n+\t\t\t\tcompatible = \"ti,ads7846\";\n+\t\t\t\treg = <1>;\n+\n+\t\t\t\tspi-max-frequency = <2000000>;\n+\t\t\t\tinterrupts = <25 2>; /* high-to-low edge triggered */\n+\t\t\t\tinterrupt-parent = <&gpio>;\n+\t\t\t\tpendown-gpio = <&gpio 25 1>;\n+\t\t\t\tti,x-plate-ohms = /bits/ 16 <60>;\n+\t\t\t\tti,pressure-max = /bits/ 16 <255>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\t__overrides__ {\n+\t\tspeed =     <&rpidisplay>,\"spi-max-frequency:0\";\n+\t\trotate =    <&rpidisplay>,\"rotate:0\";\n+\t\tfps =       <&rpidisplay>,\"fps:0\";\n+\t\tdebug =     <&rpidisplay>,\"debug:0\";\n+\t\txohms =     <&rpidisplay_ts>,\"ti,x-plate-ohms;0\";\n+\t\tswapxy =    <&rpidisplay_ts>,\"ti,swap-xy?\";\n+\t\tbacklight = <&rpidisplay>,\"led-gpios:4\",\n+\t\t            <&rpi_display_pins>,\"brcm,pins:0\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/rpi-ft5406-overlay.dts b/arch/arm/boot/dts/overlays/rpi-ft5406-overlay.dts\nnew file mode 100644\nindex 000000000000..8483c4f4b2eb\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/rpi-ft5406-overlay.dts\n@@ -0,0 +1,25 @@\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget-path = \"/soc/firmware\";\n+\t\t__overlay__ {\n+\t\t\tts: touchscreen {\n+\t\t\t\tcompatible = \"raspberrypi,firmware-ts\";\n+\t\t\t\ttouchscreen-size-x = <800>;\n+\t\t\t\ttouchscreen-size-y = <480>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\ttouchscreen-size-x = <&ts>,\"touchscreen-size-x:0\";\n+\t\ttouchscreen-size-y = <&ts>,\"touchscreen-size-y:0\";\n+\t\ttouchscreen-inverted-x = <&ts>,\"touchscreen-inverted-x?\";\n+\t\ttouchscreen-inverted-y = <&ts>,\"touchscreen-inverted-y?\";\n+\t\ttouchscreen-swapped-x-y = <&ts>,\"touchscreen-swapped-x-y?\";\n+        };\n+};\ndiff --git a/arch/arm/boot/dts/overlays/rpi-poe-overlay.dts b/arch/arm/boot/dts/overlays/rpi-poe-overlay.dts\nnew file mode 100644\nindex 000000000000..544038b614e1\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/rpi-poe-overlay.dts\n@@ -0,0 +1,95 @@\n+/*\n+ * Overlay for the Raspberry Pi POE HAT.\n+ */\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget-path = \"/\";\n+\t\t__overlay__ {\n+\t\t\tfan0: rpi-poe-fan@0 {\n+\t\t\t\tcompatible = \"raspberrypi,rpi-poe-fan\";\n+\t\t\t\tfirmware = <&firmware>;\n+\t\t\t\tcooling-min-state = <0>;\n+\t\t\t\tcooling-max-state = <4>;\n+\t\t\t\t#cooling-cells = <2>;\n+\t\t\t\tcooling-levels = <0 31 63 150 255>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&cpu_thermal>;\n+\t\t__overlay__ {\n+\t\t\ttrips {\n+\t\t\t\ttrip0: trip0 {\n+\t\t\t\t\ttemperature = <40000>;\n+\t\t\t\t\thysteresis = <2000>;\n+\t\t\t\t\ttype = \"active\";\n+\t\t\t\t};\n+\t\t\t\ttrip1: trip1 {\n+\t\t\t\t\ttemperature = <45000>;\n+\t\t\t\t\thysteresis = <2000>;\n+\t\t\t\t\ttype = \"active\";\n+\t\t\t\t};\n+\t\t\t\ttrip2: trip2 {\n+\t\t\t\t\ttemperature = <50000>;\n+\t\t\t\t\thysteresis = <2000>;\n+\t\t\t\t\ttype = \"active\";\n+\t\t\t\t};\n+\t\t\t\ttrip3: trip3 {\n+\t\t\t\t\ttemperature = <55000>;\n+\t\t\t\t\thysteresis = <5000>;\n+\t\t\t\t\ttype = \"active\";\n+\t\t\t\t};\n+\t\t\t};\n+\t\t\tcooling-maps {\n+\t\t\t\tmap0 {\n+\t\t\t\t\ttrip = <&trip0>;\n+\t\t\t\t\tcooling-device = <&fan0 0 1>;\n+\t\t\t\t};\n+\t\t\t\tmap1 {\n+\t\t\t\t\ttrip = <&trip1>;\n+\t\t\t\t\tcooling-device = <&fan0 1 2>;\n+\t\t\t\t};\n+\t\t\t\tmap2 {\n+\t\t\t\t\ttrip = <&trip2>;\n+\t\t\t\t\tcooling-device = <&fan0 2 3>;\n+\t\t\t\t};\n+\t\t\t\tmap3 {\n+\t\t\t\t\ttrip = <&trip3>;\n+\t\t\t\t\tcooling-device = <&fan0 3 4>;\n+\t\t\t\t};\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget-path = \"/__overrides__\";\n+\t\t__overlay__ {\n+\t\t\tpoe_fan_temp0 =\t\t<&trip0>,\"temperature:0\";\n+\t\t\tpoe_fan_temp0_hyst =\t<&trip0>,\"hysteresis:0\";\n+\t\t\tpoe_fan_temp1 =\t\t<&trip1>,\"temperature:0\";\n+\t\t\tpoe_fan_temp1_hyst =\t<&trip1>,\"hysteresis:0\";\n+\t\t\tpoe_fan_temp2 =\t\t<&trip2>,\"temperature:0\";\n+\t\t\tpoe_fan_temp2_hyst =\t<&trip2>,\"hysteresis:0\";\n+\t\t\tpoe_fan_temp3 =\t\t<&trip3>,\"temperature:0\";\n+\t\t\tpoe_fan_temp3_hyst =\t<&trip3>,\"hysteresis:0\";\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\tpoe_fan_temp0 =\t\t<&trip0>,\"temperature:0\";\n+\t\tpoe_fan_temp0_hyst =\t<&trip0>,\"hysteresis:0\";\n+\t\tpoe_fan_temp1 =\t\t<&trip1>,\"temperature:0\";\n+\t\tpoe_fan_temp1_hyst =\t<&trip1>,\"hysteresis:0\";\n+\t\tpoe_fan_temp2 =\t\t<&trip2>,\"temperature:0\";\n+\t\tpoe_fan_temp2_hyst =\t<&trip2>,\"hysteresis:0\";\n+\t\tpoe_fan_temp3 =\t\t<&trip3>,\"temperature:0\";\n+\t\tpoe_fan_temp3_hyst =\t<&trip3>,\"hysteresis:0\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/rpi-proto-overlay.dts b/arch/arm/boot/dts/overlays/rpi-proto-overlay.dts\nnew file mode 100644\nindex 000000000000..9cda044a0f62\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/rpi-proto-overlay.dts\n@@ -0,0 +1,39 @@\n+// Definitions for Rpi-Proto\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&i2s>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&i2c1>;\n+\t\t__overlay__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\twm8731@1a {\n+\t\t\t\t#sound-dai-cells = <0>;\n+\t\t\t\tcompatible = \"wlf,wm8731\";\n+\t\t\t\treg = <0x1a>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&sound>;\n+\t\t__overlay__ {\n+\t\t\tcompatible = \"rpi,rpi-proto\";\n+\t\t\ti2s-controller = <&i2s>;\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/rpi-sense-overlay.dts b/arch/arm/boot/dts/overlays/rpi-sense-overlay.dts\nnew file mode 100644\nindex 000000000000..89d8d2ea6b2e\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/rpi-sense-overlay.dts\n@@ -0,0 +1,47 @@\n+// rpi-sense HAT\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&i2c1>;\n+\t\t__overlay__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\trpi-sense@46 {\n+\t\t\t\tcompatible = \"rpi,rpi-sense\";\n+\t\t\t\treg = <0x46>;\n+\t\t\t\tkeys-int-gpios = <&gpio 23 1>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\n+\t\t\tlsm9ds1-magn@1c {\n+\t\t\t\tcompatible = \"st,lsm9ds1-magn\";\n+\t\t\t\treg = <0x1c>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\n+\t\t\tlsm9ds1-accel6a {\n+\t\t\t\tcompatible = \"st,lsm9ds1-accel\";\n+\t\t\t\treg = <0x6a>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\n+\t\t\tlps25h-press@5c {\n+\t\t\t\tcompatible = \"st,lps25h-press\";\n+\t\t\t\treg = <0x5c>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\n+\t\t\thts221-humid@5f {\n+\t\t\t\tcompatible = \"st,hts221-humid\", \"st,hts221\";\n+\t\t\t\treg = <0x5f>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/rpi-tv-overlay.dts b/arch/arm/boot/dts/overlays/rpi-tv-overlay.dts\nnew file mode 100644\nindex 000000000000..3c97a545d820\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/rpi-tv-overlay.dts\n@@ -0,0 +1,34 @@\n+// rpi-tv HAT\n+\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&spidev0>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&spi0>;\n+\t\t__overlay__ {\n+\t\t\t/* needed to avoid dtc warning */\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tcxd2880@0 {\n+\t\t\t\tcompatible = \"sony,cxd2880\";\n+\t\t\t\treg = <0>; /* CE0 */\n+\t\t\t\tspi-max-frequency = <50000000>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+};\ndiff --git a/arch/arm/boot/dts/overlays/rpivid-v4l2-overlay.dts b/arch/arm/boot/dts/overlays/rpivid-v4l2-overlay.dts\nnew file mode 100644\nindex 000000000000..0a611b31b9d4\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/rpivid-v4l2-overlay.dts\n@@ -0,0 +1,61 @@\n+// SPDX-License-Identifier: GPL-2.0-only\n+// Definitions for Raspberry Pi video decode engine\n+/dts-v1/;\n+/plugin/;\n+\n+#include <dt-bindings/interrupt-controller/arm-gic.h>\n+\n+/{\n+\tcompatible = \"brcm,bcm2711\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&scb>;\n+\t\t__overlay__ {\n+\t\t\t/* needed to avoid dtc warning */\n+\t\t\t#address-cells = <2>;\n+\t\t\t#size-cells = <2>;\n+\n+\t\t\tcodec@7eb10000 {\n+\t\t\t\tcompatible = \"raspberrypi,rpivid-vid-decoder\";\n+\t\t\t\treg = <0x0 0x7eb10000  0x0 0x1000>,  /* INTC */\n+\t\t\t\t      <0x0 0x7eb00000  0x0 0x10000>; /* HEVC */\n+\t\t\t\treg-names = \"intc\",\n+\t\t\t\t\t    \"hevc\";\n+\n+\t\t\t\tinterrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;\n+\n+\t\t\t\tclocks = <&hevc_clk>;\n+\t\t\t\tclock-names = \"hevc\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&scb>;\n+\t\t__overlay__ {\n+\t\t\thevc-decoder@7eb00000 {\n+\t\t\t\tstatus = \"disabled\";\n+\t\t\t};\n+\t\t\trpivid-local-intc@7eb10000 {\n+\t\t\t\tstatus = \"disabled\";\n+\t\t\t};\n+\t\t\th264-decoder@7eb20000 {\n+\t\t\t\tstatus = \"disabled\";\n+\t\t\t};\n+\t\t\tvp9-decoder@7eb30000 {\n+\t\t\t\tstatus = \"disabled\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget-path = \"/\";\n+\t\t__overlay__ {\n+\t\t\thevc_clk: hevc_clk {\n+\t\t\t\tcompatible = \"fixed-clock\";\n+\t\t\t\t#clock-cells = <0>;\n+\t\t\t\tclock-frequency = <500000000>;\n+\t\t\t};\n+\t\t};\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/rra-digidac1-wm8741-audio-overlay.dts b/arch/arm/boot/dts/overlays/rra-digidac1-wm8741-audio-overlay.dts\nnew file mode 100644\nindex 000000000000..87e9a326eff1\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/rra-digidac1-wm8741-audio-overlay.dts\n@@ -0,0 +1,49 @@\n+// Definitions for RRA DigiDAC1 Audio card\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&i2s>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&i2c1>;\n+\t\t__overlay__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\twm8804@3b {\n+\t\t\t\t#sound-dai-cells = <0>;\n+\t\t\t\tcompatible = \"wlf,wm8804\";\n+\t\t\t\treg = <0x3b>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t\tPVDD-supply = <&vdd_3v3_reg>;\n+\t\t\t\tDVDD-supply = <&vdd_3v3_reg>;\n+\t\t\t};\n+\n+\t\t\twm8742: wm8741@1a {\n+\t\t\t\tcompatible = \"wlf,wm8741\";\n+\t\t\t\treg = <0x1a>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t\tAVDD-supply = <&vdd_5v0_reg>;\n+\t\t\t\tDVDD-supply = <&vdd_3v3_reg>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&sound>;\n+\t\t__overlay__ {\n+\t\t\tcompatible = \"rra,digidac1-soundcard\";\n+\t\t\ti2s-controller = <&i2s>;\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/sainsmart18-overlay.dts b/arch/arm/boot/dts/overlays/sainsmart18-overlay.dts\nnew file mode 100644\nindex 000000000000..c51f1c030a55\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/sainsmart18-overlay.dts\n@@ -0,0 +1,52 @@\n+/*\n+ * Device Tree overlay for the Sainsmart 1.8\" TFT LCD with ST7735R chip 160x128\n+ */\n+\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&spidev0>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&spi0>;\n+\t\t__overlay__ {\n+\t\t\t/* needed to avoid dtc warning */\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tss18: sainsmart18@0 {\n+\t\t\t\tcompatible = \"fbtft,sainsmart18\";\n+\t\t\t\treg = <0>;\n+\t\t\t\tpinctrl-names = \"default\";\n+\t\t\t\tspi-max-frequency = <40000000>;\n+\t\t\t\trotate = <90>;\n+\t\t\t\tbuswidth = <8>;\n+\t\t\t\tfps = <50>;\n+\t\t\t\theight = <160>;\n+\t\t\t\twidth = <128>;\n+\t\t\t\treset-gpios = <&gpio 25 1>;\n+\t\t\t\tdc-gpios = <&gpio 24 0>;\n+\t\t\t\tdebug = <0>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\tspeed     = <&ss18>,\"spi-max-frequency:0\";\n+\t\trotate    = <&ss18>,\"rotate:0\";\n+\t\tfps       = <&ss18>,\"fps:0\";\n+\t\tbgr       = <&ss18>,\"bgr?\";\n+\t\tdebug     = <&ss18>,\"debug:0\";\n+\t\tdc_pin    = <&ss18>,\"dc-gpios:4\";\n+\t\treset_pin = <&ss18>,\"reset-gpios:4\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/sc16is750-i2c-overlay.dts b/arch/arm/boot/dts/overlays/sc16is750-i2c-overlay.dts\nnew file mode 100644\nindex 000000000000..04d74d62897b\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/sc16is750-i2c-overlay.dts\n@@ -0,0 +1,43 @@\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&i2c_arm>;\n+\t\t__overlay__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tsc16is750: sc16is750@48 {\n+\t\t\t\tcompatible = \"nxp,sc16is750\";\n+\t\t\t\treg = <0x48>; /* i2c address */\n+\t\t\t\tclocks = <&sc16is750_clk>;\n+\t\t\t\tinterrupt-parent = <&gpio>;\n+\t\t\t\tinterrupts = <24 2>; /* IRQ_TYPE_EDGE_FALLING */\n+\t\t\t\tgpio-controller;\n+\t\t\t\t#gpio-cells = <2>;\n+\t\t\t\ti2c-max-frequency = <400000>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget-path = \"/\";\n+\t\t__overlay__ {\n+\t\t\tsc16is750_clk: sc16is750_i2c_clk@48 {\n+\t\t\t\tcompatible = \"fixed-clock\";\n+\t\t\t\t#clock-cells = <0>;\n+\t\t\t\tclock-frequency = <14745600>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\tint_pin = <&sc16is750>,\"interrupts:0\";\n+\t\taddr = <&sc16is750>,\"reg:0\", <&sc16is750_clk>,\"name\";\n+\t\txtal = <&sc16is750_clk>,\"clock-frequency:0\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/sc16is752-i2c-overlay.dts b/arch/arm/boot/dts/overlays/sc16is752-i2c-overlay.dts\nnew file mode 100644\nindex 000000000000..da05e981314c\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/sc16is752-i2c-overlay.dts\n@@ -0,0 +1,43 @@\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&i2c_arm>;\n+\t\t__overlay__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tsc16is752: sc16is752@48 {\n+\t\t\t\tcompatible = \"nxp,sc16is752\";\n+\t\t\t\treg = <0x48>; /* i2c address */\n+\t\t\t\tclocks = <&sc16is752_clk>;\n+\t\t\t\tinterrupt-parent = <&gpio>;\n+\t\t\t\tinterrupts = <24 2>; /* IRQ_TYPE_EDGE_FALLING */\n+\t\t\t\tgpio-controller;\n+\t\t\t\t#gpio-cells = <2>;\n+\t\t\t\ti2c-max-frequency = <400000>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget-path = \"/\";\n+\t\t__overlay__ {\n+\t\t\tsc16is752_clk: sc16is752_i2c_clk@48 {\n+\t\t\t\tcompatible = \"fixed-clock\";\n+\t\t\t\t#clock-cells = <0>;\n+\t\t\t\tclock-frequency = <14745600>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\tint_pin = <&sc16is752>,\"interrupts:0\";\n+\t\taddr = <&sc16is752>,\"reg:0\",<&sc16is752_clk>,\"name\";\n+\t\txtal = <&sc16is752_clk>,\"clock-frequency:0\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/sc16is752-spi0-overlay.dts b/arch/arm/boot/dts/overlays/sc16is752-spi0-overlay.dts\nnew file mode 100644\nindex 000000000000..a49a04722b99\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/sc16is752-spi0-overlay.dts\n@@ -0,0 +1,49 @@\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&spi0>;\n+\t\t__overlay__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tsc16is752: sc16is752@0 {\n+\t\t\t\tcompatible = \"nxp,sc16is752\";\n+\t\t\t\treg = <0>; /* CE0 */\n+\t\t\t\tclocks = <&sc16is752_clk>;\n+\t\t\t\tinterrupt-parent = <&gpio>;\n+\t\t\t\tinterrupts = <24 2>; /* IRQ_TYPE_EDGE_FALLING */\n+\t\t\t\tgpio-controller;\n+\t\t\t\t#gpio-cells = <2>;\n+\t\t\t\tspi-max-frequency = <4000000>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&spidev0>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget-path = \"/\";\n+\t\t__overlay__ {\n+\t\t\tsc16is752_clk: sc16is752_spi0_0_clk {\n+\t\t\t\tcompatible = \"fixed-clock\";\n+\t\t\t\t#clock-cells = <0>;\n+\t\t\t\tclock-frequency = <14745600>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\tint_pin = <&sc16is752>,\"interrupts:0\";\n+\t\txtal = <&sc16is752_clk>,\"clock-frequency:0\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/sc16is752-spi1-overlay.dts b/arch/arm/boot/dts/overlays/sc16is752-spi1-overlay.dts\nnew file mode 100644\nindex 000000000000..730c6e8cd614\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/sc16is752-spi1-overlay.dts\n@@ -0,0 +1,67 @@\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&gpio>;\n+\t\t__overlay__ {\n+\t\t\tspi1_pins: spi1_pins {\n+\t\t\t\tbrcm,pins = <19 20 21>;\n+\t\t\t\tbrcm,function = <3>; /* alt4 */\n+\t\t\t};\n+\n+\t\t\tspi1_cs_pins: spi1_cs_pins {\n+\t\t\t\tbrcm,pins = <18>;\n+\t\t\t\tbrcm,function = <1>; /* output */\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&spi1>;\n+\t\t__overlay__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&spi1_pins &spi1_cs_pins>;\n+\t\t\tcs-gpios = <&gpio 18 1>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tsc16is752: sc16is752@0 {\n+\t\t\t\tcompatible = \"nxp,sc16is752\";\n+\t\t\t\treg = <0>; /* CE0 */\n+\t\t\t\tclocks = <&sc16is752_clk>;\n+\t\t\t\tinterrupt-parent = <&gpio>;\n+\t\t\t\tinterrupts = <24 2>; /* IRQ_TYPE_EDGE_FALLING */\n+\t\t\t\tgpio-controller;\n+\t\t\t\t#gpio-cells = <2>;\n+\t\t\t\tspi-max-frequency = <4000000>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&aux>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@3 {\n+\t\ttarget-path = \"/\";\n+\t\t__overlay__ {\n+\t\t\tsc16is752_clk: sc16is752_spi1_0_clk {\n+\t\t\t\tcompatible = \"fixed-clock\";\n+\t\t\t\t#clock-cells = <0>;\n+\t\t\t\tclock-frequency = <14745600>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\tint_pin = <&sc16is752>,\"interrupts:0\";\n+\t\txtal = <&sc16is752_clk>,\"clock-frequency:0\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/sdhost-overlay.dts b/arch/arm/boot/dts/overlays/sdhost-overlay.dts\nnew file mode 100644\nindex 000000000000..0b72b4eeac88\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/sdhost-overlay.dts\n@@ -0,0 +1,38 @@\n+/dts-v1/;\n+/plugin/;\n+\n+/* Provide backwards compatible aliases for the old sdhost dtparams. */\n+\n+/{\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&sdhost>;\n+\t\tfrag0: __overlay__ {\n+\t\t\tbrcm,overclock-50 = <0>;\n+\t\t\tbrcm,pio-limit = <1>;\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&mmc>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&mmcnr>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\toverclock_50     = <&frag0>,\"brcm,overclock-50:0\";\n+\t\tforce_pio        = <&frag0>,\"brcm,force-pio?\";\n+\t\tpio_limit        = <&frag0>,\"brcm,pio-limit:0\";\n+\t\tdebug            = <&frag0>,\"brcm,debug?\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/sdio-overlay.dts b/arch/arm/boot/dts/overlays/sdio-overlay.dts\nnew file mode 100644\nindex 000000000000..873e49056379\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/sdio-overlay.dts\n@@ -0,0 +1,77 @@\n+/dts-v1/;\n+/plugin/;\n+\n+/* Enable SDIO from MMC interface via various GPIO groups */\n+\n+/{\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&mmcnr>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&mmc>;\n+\t\tsdio_ovl: __overlay__ {\n+\t\t\tpinctrl-0 = <&sdio_ovl_pins>;\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tnon-removable;\n+\t\t\tbus-width = <4>;\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&gpio>;\n+\t\t__overlay__ {\n+\t\t\tsdio_ovl_pins: sdio_ovl_pins {\n+\t\t\t\tbrcm,pins = <22 23 24 25 26 27>;\n+\t\t\t\tbrcm,function = <7>; /* ALT3 = SD1 */\n+\t\t\t\tbrcm,pull = <0 2 2 2 2 2>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@3 {\n+\t\ttarget = <&sdio_ovl_pins>;\n+\t\t__dormant__ {\n+\t\t\tbrcm,pins = <22 23 24 25>;\n+\t\t\tbrcm,pull = <0 2 2 2>;\n+\t\t};\n+\t};\n+\n+\tfragment@4 {\n+\t\ttarget = <&sdio_ovl_pins>;\n+\t\t__dormant__ {\n+\t\t\tbrcm,pins = <34 35 36 37>;\n+\t\t\tbrcm,pull = <0 2 2 2>;\n+\t\t};\n+\t};\n+\n+\tfragment@5 {\n+\t\ttarget = <&sdio_ovl_pins>;\n+\t\t__dormant__ {\n+\t\t\tbrcm,pins = <34 35 36 37 38 39>;\n+\t\t\tbrcm,pull = <0 2 2 2 2 2>;\n+\t\t};\n+\t};\n+\n+\tfragment@6 {\n+\t\ttarget-path = \"/aliases\";\n+\t\t__overlay__ {\n+\t\t\tmmc1 = \"/soc/mmc@7e300000\";\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\tpoll_once = <&sdio_ovl>,\"non-removable?\";\n+\t\tbus_width = <&sdio_ovl>,\"bus-width:0\";\n+\t\tsdio_overclock = <&sdio_ovl>,\"brcm,overclock-50:0\";\n+\t\tgpios_22_25 = <0>,\"=3\";\n+\t\tgpios_34_37 = <0>,\"=4\";\n+\t\tgpios_34_39 = <0>,\"=5\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/sdtweak-overlay.dts b/arch/arm/boot/dts/overlays/sdtweak-overlay.dts\nnew file mode 100644\nindex 000000000000..38157d2f9bf3\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/sdtweak-overlay.dts\n@@ -0,0 +1,25 @@\n+/dts-v1/;\n+/plugin/;\n+\n+/* Provide backwards compatible aliases for the old sdhost dtparams. */\n+\n+/{\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&sdhost>;\n+\t\tfrag0: __overlay__ {\n+\t\t\tbrcm,overclock-50 = <0>;\n+\t\t\tbrcm,pio-limit = <1>;\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\toverclock_50     = <&frag0>,\"brcm,overclock-50:0\";\n+\t\tforce_pio        = <&frag0>,\"brcm,force-pio?\";\n+\t\tpio_limit        = <&frag0>,\"brcm,pio-limit:0\";\n+\t\tdebug            = <&frag0>,\"brcm,debug?\";\n+\t\tenable           = <&frag0>,\"status\";\n+\t\tpoll_once        = <&frag0>,\"non-removable?\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/sh1106-spi-overlay.dts b/arch/arm/boot/dts/overlays/sh1106-spi-overlay.dts\nnew file mode 100644\nindex 000000000000..57a0cc9b1741\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/sh1106-spi-overlay.dts\n@@ -0,0 +1,84 @@\n+/*\n+ * Device Tree overlay for SH1106 based SPI OLED display\n+ *\n+ */\n+\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&spi0>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&spidev0>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&spidev1>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\tfragment@3 {\n+\t\ttarget = <&gpio>;\n+\t\t__overlay__ {\n+\t\t\tsh1106_pins: sh1106_pins {\n+                                brcm,pins = <25 24>;\n+                                brcm,function = <1 1>; /* out out */\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@4 {\n+\t\ttarget = <&spi0>;\n+\t\t__overlay__ {\n+\t\t\t/* needed to avoid dtc warning */\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tsh1106: sh1106@0{\n+\t\t\t\tcompatible = \"sinowealth,sh1106\";\n+\t\t\t\treg = <0>;\n+\t\t\t\tpinctrl-names = \"default\";\n+\t\t\t\tpinctrl-0 = <&sh1106_pins>;\n+\n+\t\t\t\tspi-max-frequency = <4000000>;\n+\t\t\t\tbgr = <0>;\n+\t\t\t\tbpp = <1>;\n+\t\t\t\trotate = <0>;\n+\t\t\t\tfps = <25>;\n+\t\t\t\tbuswidth = <8>;\n+\t\t\t\treset-gpios = <&gpio 25 1>;\n+\t\t\t\tdc-gpios = <&gpio 24 0>;\n+\t\t\t\tdebug = <0>;\n+\n+\t\t\t\tsinowealth,height = <64>;\n+\t\t\t\tsinowealth,width = <128>;\n+\t\t\t\tsinowealth,page-offset = <0>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\tspeed     = <&sh1106>,\"spi-max-frequency:0\";\n+\t\trotate    = <&sh1106>,\"rotate:0\";\n+\t\tfps       = <&sh1106>,\"fps:0\";\n+\t\tdebug     = <&sh1106>,\"debug:0\";\n+\t\tdc_pin    = <&sh1106>,\"dc-gpios:4\",\n+\t\t            <&sh1106_pins>,\"brcm,pins:4\";\n+\t\treset_pin = <&sh1106>,\"reset-gpios:4\",\n+\t\t            <&sh1106_pins>,\"brcm,pins:0\";\n+\t\theight    = <&sh1106>,\"sinowealth,height:0\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/smi-dev-overlay.dts b/arch/arm/boot/dts/overlays/smi-dev-overlay.dts\nnew file mode 100644\nindex 000000000000..bafab6c92506\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/smi-dev-overlay.dts\n@@ -0,0 +1,20 @@\n+// Description: Overlay to enable character device interface for SMI.\n+// Author:\tLuke Wren <luke@raspberrypi.org>\n+\n+/dts-v1/;\n+/plugin/;\n+\n+/{\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&soc>;\n+\t\t__overlay__ {\n+\t\t\tsmi_dev {\n+\t\t\t\tcompatible = \"brcm,bcm2835-smi-dev\";\n+\t\t\t\tsmi_handle = <&smi>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/smi-nand-overlay.dts b/arch/arm/boot/dts/overlays/smi-nand-overlay.dts\nnew file mode 100644\nindex 000000000000..ae1e50329d66\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/smi-nand-overlay.dts\n@@ -0,0 +1,66 @@\n+// Description: Overlay to enable NAND flash through\n+// the secondary memory interface\n+// Author:\tLuke Wren\n+\n+/dts-v1/;\n+/plugin/;\n+\n+/{\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&smi>;\n+\t\t__overlay__ {\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&smi_pins>;\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&soc>;\n+\t\t__overlay__ {\n+\t\t\tnand: flash@0 {\n+\t\t\t\tcompatible = \"brcm,bcm2835-smi-nand\";\n+\t\t\t\tsmi_handle = <&smi>;\n+\t\t\t\t#address-cells = <1>;\n+\t\t\t\t#size-cells = <1>;\n+\t\t\t\tstatus = \"okay\";\n+\n+\t\t\t\tpartition@0 {\n+\t\t\t\t\tlabel = \"stage2\";\n+\t\t\t\t\t// 128k\n+\t\t\t\t\treg = <0 0x20000>;\n+\t\t\t\t\tread-only;\n+\t\t\t\t};\n+\t\t\t\tpartition@1 {\n+\t\t\t\t\tlabel = \"firmware\";\n+\t\t\t\t\t// 16M\n+\t\t\t\t\treg = <0x20000 0x1000000>;\n+\t\t\t\t\tread-only;\n+\t\t\t\t};\n+\t\t\t\tpartition@2 {\n+\t\t\t\t\tlabel = \"root\";\n+\t\t\t\t\t// 2G (will need to use 64 bit for >=4G)\n+\t\t\t\t\treg = <0x1020000 0x80000000>;\n+\t\t\t\t};\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&gpio>;\n+\t\t__overlay__ {\n+\t\t\tsmi_pins: smi_pins {\n+\t\t\t\tbrcm,pins = <0 1 2 3 4 5 6 7 8 9 10 11\n+\t\t\t\t\t12 13 14 15>;\n+\t\t\t\t/* Alt 1: SMI */\n+\t\t\t\tbrcm,function = <5 5 5 5 5 5 5 5 5 5 5\n+\t\t\t\t\t5 5 5 5 5>;\n+\t\t\t\t/* /CS, /WE and /OE are pulled high, as they are\n+\t\t\t\t   generally active low signals */\n+\t\t\t\tbrcm,pull = <2 2 2 2 2 2 2 2 0 0 0 0 0 0 0 0>;\n+\t\t\t};\n+\t\t};\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/smi-overlay.dts b/arch/arm/boot/dts/overlays/smi-overlay.dts\nnew file mode 100644\nindex 000000000000..bb8c7830df23\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/smi-overlay.dts\n@@ -0,0 +1,37 @@\n+// Description:\tOverlay to enable the secondary memory interface peripheral\n+// Author:\tLuke Wren\n+\n+/dts-v1/;\n+/plugin/;\n+\n+/{\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&smi>;\n+\t\t__overlay__ {\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&smi_pins>;\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&gpio>;\n+\t\t__overlay__ {\n+\t\t\tsmi_pins: smi_pins {\n+\t\t\t\t/* Don't configure the top two address bits, as\n+\t\t\t\t   these are already used as ID_SD and ID_SC */\n+\t\t\t\tbrcm,pins = <2 3 4 5 6 7 8 9 10 11 12 13 14 15\n+\t\t\t\t\t     16 17 18 19 20 21 22 23 24 25>;\n+\t\t\t\t/* Alt 1: SMI */\n+\t\t\t\tbrcm,function = <5 5 5 5 5 5 5 5 5 5 5 5 5 5 5\n+\t\t\t\t\t\t 5 5 5 5 5 5 5 5 5>;\n+\t\t\t\t/* /CS, /WE and /OE are pulled high, as they are\n+\t\t\t\t   generally active low signals */\n+\t\t\t\tbrcm,pull = <2 2 2 2 2 2 0 0 0 0 0 0 0 0 0 0 0\n+\t\t\t\t\t     0 0 0 0 0 0 0>;\n+\t\t\t};\n+\t\t};\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/spi-gpio35-39-overlay.dts b/arch/arm/boot/dts/overlays/spi-gpio35-39-overlay.dts\nnew file mode 100644\nindex 000000000000..a132b8637c31\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/spi-gpio35-39-overlay.dts\n@@ -0,0 +1,31 @@\n+/*\n+ * Device tree overlay to move spi0 to gpio 35 to 39 on CM\n+ */\n+\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&spi0>;\n+\t\t__overlay__ {\n+\t\t\tcs-gpios = <&gpio 36 1>, <&gpio 35 1>;\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&spi0_cs_pins>;\n+\t\t__overlay__ {\n+\t\t\tbrcm,pins = <36 35>;\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&spi0_pins>;\n+\t\t__overlay__ {\n+\t\t\tbrcm,pins = <37 38 39>;\n+\t\t};\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/spi-gpio40-45-overlay.dts b/arch/arm/boot/dts/overlays/spi-gpio40-45-overlay.dts\nnew file mode 100644\nindex 000000000000..9ebcaf1b5ea0\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/spi-gpio40-45-overlay.dts\n@@ -0,0 +1,36 @@\n+/*\n+ * Boot EEPROM overlay\n+ */\n+\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&spi0>;\n+\t\t__overlay__ {\n+\t\t\tcs-gpios = <&gpio 43 1>, <&gpio 44 1>, <&gpio 45 1>;\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&spi0_cs_pins>;\n+\t\t__overlay__ {\n+\t\t\tbrcm,pins = <45 44 43>;\n+\t\t\tbrcm,function = <1>; /* output */\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&spi0_pins>;\n+\t\t__overlay__ {\n+\t\t\tbrcm,pins = <40 41 42>;\n+\t\t\tbrcm,function = <3>; /* alt4 */\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/spi-rtc-overlay.dts b/arch/arm/boot/dts/overlays/spi-rtc-overlay.dts\nnew file mode 100644\nindex 000000000000..9664afc9845c\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/spi-rtc-overlay.dts\n@@ -0,0 +1,33 @@\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&spidev0>;\n+\t\t__dormant__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&spi0>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\trtc-pcf2123@0 {\n+\t\t\t\tcompatible = \"nxp,rtc-pcf2123\";\n+\t\t\t\tspi-max-frequency = <5000000>;\n+\t\t\t\tspi-cs-high = <1>;\n+\t\t\t\treg = <0>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\tpcf2123 = <0>, \"=0=1\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/spi0-1cs-overlay.dts b/arch/arm/boot/dts/overlays/spi0-1cs-overlay.dts\nnew file mode 100644\nindex 000000000000..e6eb66e2076a\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/spi0-1cs-overlay.dts\n@@ -0,0 +1,42 @@\n+/dts-v1/;\n+/plugin/;\n+\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&spi0_cs_pins>;\n+\t\tfrag0: __overlay__ {\n+\t\t\tbrcm,pins = <8>;\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&spi0>;\n+\t\tfrag1: __overlay__ {\n+\t\t\tcs-gpios = <&gpio 8 1>;\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&spidev1>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\tfragment@3 {\n+\t\ttarget = <&spi0_pins>;\n+\t\t__dormant__ {\n+\t\t\tbrcm,pins = <10 11>;\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\tcs0_pin  = <&frag0>,\"brcm,pins:0\",\n+\t\t\t   <&frag1>,\"cs-gpios:4\";\n+\t\tno_miso = <0>,\"=3\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/spi0-2cs-overlay.dts b/arch/arm/boot/dts/overlays/spi0-2cs-overlay.dts\nnew file mode 100644\nindex 000000000000..df6519537c3a\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/spi0-2cs-overlay.dts\n@@ -0,0 +1,37 @@\n+/dts-v1/;\n+/plugin/;\n+\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&spi0_cs_pins>;\n+\t\tfrag0: __overlay__ {\n+\t\t\tbrcm,pins = <8 7>;\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&spi0>;\n+\t\tfrag1: __overlay__ {\n+\t\t\tcs-gpios = <&gpio 8 1>, <&gpio 7 1>;\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&spi0_pins>;\n+\t\t__dormant__ {\n+\t\t\tbrcm,pins = <10 11>;\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\tcs0_pin  = <&frag0>,\"brcm,pins:0\",\n+\t\t\t   <&frag1>,\"cs-gpios:4\";\n+\t\tcs1_pin  = <&frag0>,\"brcm,pins:4\",\n+\t\t\t   <&frag1>,\"cs-gpios:16\";\n+\t\tno_miso = <0>,\"=2\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/spi1-1cs-overlay.dts b/arch/arm/boot/dts/overlays/spi1-1cs-overlay.dts\nnew file mode 100644\nindex 000000000000..ea2794bc5fd5\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/spi1-1cs-overlay.dts\n@@ -0,0 +1,57 @@\n+/dts-v1/;\n+/plugin/;\n+\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&gpio>;\n+\t\t__overlay__ {\n+\t\t\tspi1_pins: spi1_pins {\n+\t\t\t\tbrcm,pins = <19 20 21>;\n+\t\t\t\tbrcm,function = <3>; /* alt4 */\n+\t\t\t};\n+\n+\t\t\tspi1_cs_pins: spi1_cs_pins {\n+\t\t\t\tbrcm,pins = <18>;\n+\t\t\t\tbrcm,function = <1>; /* output */\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&spi1>;\n+\t\tfrag1: __overlay__ {\n+\t\t\t/* needed to avoid dtc warning */\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&spi1_pins &spi1_cs_pins>;\n+\t\t\tcs-gpios = <&gpio 18 1>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tspidev1_0: spidev@0 {\n+\t\t\t\tcompatible = \"spidev\";\n+\t\t\t\treg = <0>;      /* CE0 */\n+\t\t\t\t#address-cells = <1>;\n+\t\t\t\t#size-cells = <0>;\n+\t\t\t\tspi-max-frequency = <125000000>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&aux>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\tcs0_pin  = <&spi1_cs_pins>,\"brcm,pins:0\",\n+\t\t\t   <&frag1>,\"cs-gpios:4\";\n+\t\tcs0_spidev = <&spidev1_0>,\"status\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/spi1-2cs-overlay.dts b/arch/arm/boot/dts/overlays/spi1-2cs-overlay.dts\nnew file mode 100644\nindex 000000000000..dab34ee79ae2\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/spi1-2cs-overlay.dts\n@@ -0,0 +1,69 @@\n+/dts-v1/;\n+/plugin/;\n+\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&gpio>;\n+\t\t__overlay__ {\n+\t\t\tspi1_pins: spi1_pins {\n+\t\t\t\tbrcm,pins = <19 20 21>;\n+\t\t\t\tbrcm,function = <3>; /* alt4 */\n+\t\t\t};\n+\n+\t\t\tspi1_cs_pins: spi1_cs_pins {\n+\t\t\t\tbrcm,pins = <18 17>;\n+\t\t\t\tbrcm,function = <1>; /* output */\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&spi1>;\n+\t\tfrag1: __overlay__ {\n+\t\t\t/* needed to avoid dtc warning */\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&spi1_pins &spi1_cs_pins>;\n+\t\t\tcs-gpios = <&gpio 18 1>, <&gpio 17 1>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tspidev1_0: spidev@0 {\n+\t\t\t\tcompatible = \"spidev\";\n+\t\t\t\treg = <0>;      /* CE0 */\n+\t\t\t\t#address-cells = <1>;\n+\t\t\t\t#size-cells = <0>;\n+\t\t\t\tspi-max-frequency = <125000000>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\n+\t\t\tspidev1_1: spidev@1 {\n+\t\t\t\tcompatible = \"spidev\";\n+\t\t\t\treg = <1>;      /* CE1 */\n+\t\t\t\t#address-cells = <1>;\n+\t\t\t\t#size-cells = <0>;\n+\t\t\t\tspi-max-frequency = <125000000>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&aux>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\tcs0_pin  = <&spi1_cs_pins>,\"brcm,pins:0\",\n+\t\t\t   <&frag1>,\"cs-gpios:4\";\n+\t\tcs1_pin  = <&spi1_cs_pins>,\"brcm,pins:4\",\n+\t\t\t   <&frag1>,\"cs-gpios:16\";\n+\t\tcs0_spidev = <&spidev1_0>,\"status\";\n+\t\tcs1_spidev = <&spidev1_1>,\"status\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/spi1-3cs-overlay.dts b/arch/arm/boot/dts/overlays/spi1-3cs-overlay.dts\nnew file mode 100644\nindex 000000000000..bc7e7d04324b\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/spi1-3cs-overlay.dts\n@@ -0,0 +1,81 @@\n+/dts-v1/;\n+/plugin/;\n+\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&gpio>;\n+\t\t__overlay__ {\n+\t\t\tspi1_pins: spi1_pins {\n+\t\t\t\tbrcm,pins = <19 20 21>;\n+\t\t\t\tbrcm,function = <3>; /* alt4 */\n+\t\t\t};\n+\n+\t\t\tspi1_cs_pins: spi1_cs_pins {\n+\t\t\t\tbrcm,pins = <18 17 16>;\n+\t\t\t\tbrcm,function = <1>; /* output */\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&spi1>;\n+\t\tfrag1: __overlay__ {\n+\t\t\t/* needed to avoid dtc warning */\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&spi1_pins &spi1_cs_pins>;\n+\t\t\tcs-gpios = <&gpio 18 1>, <&gpio 17 1>, <&gpio 16 1>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tspidev1_0: spidev@0 {\n+\t\t\t\tcompatible = \"spidev\";\n+\t\t\t\treg = <0>;      /* CE0 */\n+\t\t\t\t#address-cells = <1>;\n+\t\t\t\t#size-cells = <0>;\n+\t\t\t\tspi-max-frequency = <125000000>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\n+\t\t\tspidev1_1: spidev@1 {\n+\t\t\t\tcompatible = \"spidev\";\n+\t\t\t\treg = <1>;      /* CE1 */\n+\t\t\t\t#address-cells = <1>;\n+\t\t\t\t#size-cells = <0>;\n+\t\t\t\tspi-max-frequency = <125000000>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\n+\t\t\tspidev1_2: spidev@2 {\n+\t\t\t\tcompatible = \"spidev\";\n+\t\t\t\treg = <2>;      /* CE2 */\n+\t\t\t\t#address-cells = <1>;\n+\t\t\t\t#size-cells = <0>;\n+\t\t\t\tspi-max-frequency = <125000000>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&aux>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\tcs0_pin  = <&spi1_cs_pins>,\"brcm,pins:0\",\n+\t\t\t   <&frag1>,\"cs-gpios:4\";\n+\t\tcs1_pin  = <&spi1_cs_pins>,\"brcm,pins:4\",\n+\t\t\t   <&frag1>,\"cs-gpios:16\";\n+\t\tcs2_pin  = <&spi1_cs_pins>,\"brcm,pins:8\",\n+\t\t\t   <&frag1>,\"cs-gpios:28\";\n+\t\tcs0_spidev = <&spidev1_0>,\"status\";\n+\t\tcs1_spidev = <&spidev1_1>,\"status\";\n+\t\tcs2_spidev = <&spidev1_2>,\"status\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/spi2-1cs-overlay.dts b/arch/arm/boot/dts/overlays/spi2-1cs-overlay.dts\nnew file mode 100644\nindex 000000000000..2a29750462af\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/spi2-1cs-overlay.dts\n@@ -0,0 +1,57 @@\n+/dts-v1/;\n+/plugin/;\n+\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&gpio>;\n+\t\t__overlay__ {\n+\t\t\tspi2_pins: spi2_pins {\n+\t\t\t\tbrcm,pins = <40 41 42>;\n+\t\t\t\tbrcm,function = <3>; /* alt4 */\n+\t\t\t};\n+\n+\t\t\tspi2_cs_pins: spi2_cs_pins {\n+\t\t\t\tbrcm,pins = <43>;\n+\t\t\t\tbrcm,function = <1>; /* output */\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&spi2>;\n+\t\tfrag1: __overlay__ {\n+\t\t\t/* needed to avoid dtc warning */\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&spi2_pins &spi2_cs_pins>;\n+\t\t\tcs-gpios = <&gpio 43 1>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tspidev2_0: spidev@0 {\n+\t\t\t\tcompatible = \"spidev\";\n+\t\t\t\treg = <0>;      /* CE0 */\n+\t\t\t\t#address-cells = <1>;\n+\t\t\t\t#size-cells = <0>;\n+\t\t\t\tspi-max-frequency = <125000000>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&aux>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\tcs0_pin  = <&spi2_cs_pins>,\"brcm,pins:0\",\n+\t\t\t   <&frag1>,\"cs-gpios:4\";\n+\t\tcs0_spidev = <&spidev2_0>,\"status\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/spi2-2cs-overlay.dts b/arch/arm/boot/dts/overlays/spi2-2cs-overlay.dts\nnew file mode 100644\nindex 000000000000..642678fc9ddd\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/spi2-2cs-overlay.dts\n@@ -0,0 +1,69 @@\n+/dts-v1/;\n+/plugin/;\n+\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&gpio>;\n+\t\t__overlay__ {\n+\t\t\tspi2_pins: spi2_pins {\n+\t\t\t\tbrcm,pins = <40 41 42>;\n+\t\t\t\tbrcm,function = <3>; /* alt4 */\n+\t\t\t};\n+\n+\t\t\tspi2_cs_pins: spi2_cs_pins {\n+\t\t\t\tbrcm,pins = <43 44>;\n+\t\t\t\tbrcm,function = <1>; /* output */\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&spi2>;\n+\t\tfrag1: __overlay__ {\n+\t\t\t/* needed to avoid dtc warning */\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&spi2_pins &spi2_cs_pins>;\n+\t\t\tcs-gpios = <&gpio 43 1>, <&gpio 44 1>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tspidev2_0: spidev@0 {\n+\t\t\t\tcompatible = \"spidev\";\n+\t\t\t\treg = <0>;      /* CE0 */\n+\t\t\t\t#address-cells = <1>;\n+\t\t\t\t#size-cells = <0>;\n+\t\t\t\tspi-max-frequency = <125000000>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\n+\t\t\tspidev2_1: spidev@1 {\n+\t\t\t\tcompatible = \"spidev\";\n+\t\t\t\treg = <1>;      /* CE1 */\n+\t\t\t\t#address-cells = <1>;\n+\t\t\t\t#size-cells = <0>;\n+\t\t\t\tspi-max-frequency = <125000000>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&aux>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\tcs0_pin  = <&spi2_cs_pins>,\"brcm,pins:0\",\n+\t\t\t   <&frag1>,\"cs-gpios:4\";\n+\t\tcs1_pin  = <&spi2_cs_pins>,\"brcm,pins:4\",\n+\t\t\t   <&frag1>,\"cs-gpios:16\";\n+\t\tcs0_spidev = <&spidev2_0>,\"status\";\n+\t\tcs1_spidev = <&spidev2_1>,\"status\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/spi2-3cs-overlay.dts b/arch/arm/boot/dts/overlays/spi2-3cs-overlay.dts\nnew file mode 100644\nindex 000000000000..28d40c6c3c37\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/spi2-3cs-overlay.dts\n@@ -0,0 +1,81 @@\n+/dts-v1/;\n+/plugin/;\n+\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&gpio>;\n+\t\t__overlay__ {\n+\t\t\tspi2_pins: spi2_pins {\n+\t\t\t\tbrcm,pins = <40 41 42>;\n+\t\t\t\tbrcm,function = <3>; /* alt4 */\n+\t\t\t};\n+\n+\t\t\tspi2_cs_pins: spi2_cs_pins {\n+\t\t\t\tbrcm,pins = <43 44 45>;\n+\t\t\t\tbrcm,function = <1>; /* output */\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&spi2>;\n+\t\tfrag1: __overlay__ {\n+\t\t\t/* needed to avoid dtc warning */\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&spi2_pins &spi2_cs_pins>;\n+\t\t\tcs-gpios = <&gpio 43 1>, <&gpio 44 1>, <&gpio 45 1>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tspidev2_0: spidev@0 {\n+\t\t\t\tcompatible = \"spidev\";\n+\t\t\t\treg = <0>;      /* CE0 */\n+\t\t\t\t#address-cells = <1>;\n+\t\t\t\t#size-cells = <0>;\n+\t\t\t\tspi-max-frequency = <125000000>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\n+\t\t\tspidev2_1: spidev@1 {\n+\t\t\t\tcompatible = \"spidev\";\n+\t\t\t\treg = <1>;      /* CE1 */\n+\t\t\t\t#address-cells = <1>;\n+\t\t\t\t#size-cells = <0>;\n+\t\t\t\tspi-max-frequency = <125000000>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\n+\t\t\tspidev2_2: spidev@2 {\n+\t\t\t\tcompatible = \"spidev\";\n+\t\t\t\treg = <2>;      /* CE2 */\n+\t\t\t\t#address-cells = <1>;\n+\t\t\t\t#size-cells = <0>;\n+\t\t\t\tspi-max-frequency = <125000000>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&aux>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\tcs0_pin  = <&spi2_cs_pins>,\"brcm,pins:0\",\n+\t\t\t   <&frag1>,\"cs-gpios:4\";\n+\t\tcs1_pin  = <&spi2_cs_pins>,\"brcm,pins:4\",\n+\t\t\t   <&frag1>,\"cs-gpios:16\";\n+\t\tcs2_pin  = <&spi2_cs_pins>,\"brcm,pins:8\",\n+\t\t\t   <&frag1>,\"cs-gpios:28\";\n+\t\tcs0_spidev = <&spidev2_0>,\"status\";\n+\t\tcs1_spidev = <&spidev2_1>,\"status\";\n+\t\tcs2_spidev = <&spidev2_2>,\"status\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/spi3-1cs-overlay.dts b/arch/arm/boot/dts/overlays/spi3-1cs-overlay.dts\nnew file mode 100644\nindex 000000000000..335af8637051\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/spi3-1cs-overlay.dts\n@@ -0,0 +1,44 @@\n+/dts-v1/;\n+/plugin/;\n+\n+\n+/ {\n+\tcompatible = \"brcm,bcm2711\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&spi3_cs_pins>;\n+\t\tfrag0: __overlay__ {\n+\t\t\tbrcm,pins = <0>;\n+\t\t\tbrcm,function = <1>; /* output */\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&spi3>;\n+\t\tfrag1: __overlay__ {\n+\t\t\t/* needed to avoid dtc warning */\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tpinctrl-names = \"default\";\n+\t\t        pinctrl-0 = <&spi3_pins &spi3_cs_pins>;\n+\t\t\tcs-gpios = <&gpio 0 1>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tspidev3_0: spidev@0 {\n+\t\t\t\tcompatible = \"spidev\";\n+\t\t\t\treg = <0>;      /* CE0 */\n+\t\t\t\t#address-cells = <1>;\n+\t\t\t\t#size-cells = <0>;\n+\t\t\t\tspi-max-frequency = <125000000>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\tcs0_pin  = <&frag0>,\"brcm,pins:0\",\n+\t\t\t   <&frag1>,\"cs-gpios:4\";\n+\t\tcs0_spidev = <&spidev3_0>,\"status\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/spi3-2cs-overlay.dts b/arch/arm/boot/dts/overlays/spi3-2cs-overlay.dts\nnew file mode 100644\nindex 000000000000..ce65da27f767\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/spi3-2cs-overlay.dts\n@@ -0,0 +1,56 @@\n+/dts-v1/;\n+/plugin/;\n+\n+\n+/ {\n+\tcompatible = \"brcm,bcm2711\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&spi3_cs_pins>;\n+\t\tfrag0: __overlay__ {\n+\t\t\tbrcm,pins = <0 24>;\n+\t\t\tbrcm,function = <1>; /* output */\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&spi3>;\n+\t\tfrag1: __overlay__ {\n+\t\t\t/* needed to avoid dtc warning */\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tpinctrl-names = \"default\";\n+\t\t        pinctrl-0 = <&spi3_pins &spi3_cs_pins>;\n+\t\t\tcs-gpios = <&gpio 0 1>, <&gpio 24 1>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tspidev3_0: spidev@0 {\n+\t\t\t\tcompatible = \"spidev\";\n+\t\t\t\treg = <0>;      /* CE0 */\n+\t\t\t\t#address-cells = <1>;\n+\t\t\t\t#size-cells = <0>;\n+\t\t\t\tspi-max-frequency = <125000000>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\n+\t\t\tspidev3_1: spidev@1 {\n+\t\t\t\tcompatible = \"spidev\";\n+\t\t\t\treg = <1>;      /* CE1 */\n+\t\t\t\t#address-cells = <1>;\n+\t\t\t\t#size-cells = <0>;\n+\t\t\t\tspi-max-frequency = <125000000>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\tcs0_pin  = <&frag0>,\"brcm,pins:0\",\n+\t\t\t   <&frag1>,\"cs-gpios:4\";\n+\t\tcs1_pin  = <&frag0>,\"brcm,pins:4\",\n+\t\t\t   <&frag1>,\"cs-gpios:16\";\n+\t\tcs0_spidev = <&spidev3_0>,\"status\";\n+\t\tcs1_spidev = <&spidev3_1>,\"status\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/spi4-1cs-overlay.dts b/arch/arm/boot/dts/overlays/spi4-1cs-overlay.dts\nnew file mode 100644\nindex 000000000000..85d70b40352b\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/spi4-1cs-overlay.dts\n@@ -0,0 +1,44 @@\n+/dts-v1/;\n+/plugin/;\n+\n+\n+/ {\n+\tcompatible = \"brcm,bcm2711\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&spi4_cs_pins>;\n+\t\tfrag0: __overlay__ {\n+\t\t\tbrcm,pins = <4>;\n+\t\t\tbrcm,function = <1>; /* output */\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&spi4>;\n+\t\tfrag1: __overlay__ {\n+\t\t\t/* needed to avoid dtc warning */\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tpinctrl-names = \"default\";\n+\t\t        pinctrl-0 = <&spi4_pins &spi4_cs_pins>;\n+\t\t\tcs-gpios = <&gpio 4 1>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tspidev4_0: spidev@0 {\n+\t\t\t\tcompatible = \"spidev\";\n+\t\t\t\treg = <0>;      /* CE0 */\n+\t\t\t\t#address-cells = <1>;\n+\t\t\t\t#size-cells = <0>;\n+\t\t\t\tspi-max-frequency = <125000000>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\tcs0_pin  = <&frag0>,\"brcm,pins:0\",\n+\t\t\t   <&frag1>,\"cs-gpios:4\";\n+\t\tcs0_spidev = <&spidev4_0>,\"status\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/spi4-2cs-overlay.dts b/arch/arm/boot/dts/overlays/spi4-2cs-overlay.dts\nnew file mode 100644\nindex 000000000000..8bc2215a6a7e\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/spi4-2cs-overlay.dts\n@@ -0,0 +1,56 @@\n+/dts-v1/;\n+/plugin/;\n+\n+\n+/ {\n+\tcompatible = \"brcm,bcm2711\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&spi4_cs_pins>;\n+\t\tfrag0: __overlay__ {\n+\t\t\tbrcm,pins = <4 25>;\n+\t\t\tbrcm,function = <1>; /* output */\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&spi4>;\n+\t\tfrag1: __overlay__ {\n+\t\t\t/* needed to avoid dtc warning */\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tpinctrl-names = \"default\";\n+\t\t        pinctrl-0 = <&spi4_pins &spi4_cs_pins>;\n+\t\t\tcs-gpios = <&gpio 4 1>, <&gpio 25 1>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tspidev4_0: spidev@0 {\n+\t\t\t\tcompatible = \"spidev\";\n+\t\t\t\treg = <0>;      /* CE0 */\n+\t\t\t\t#address-cells = <1>;\n+\t\t\t\t#size-cells = <0>;\n+\t\t\t\tspi-max-frequency = <125000000>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\n+\t\t\tspidev4_1: spidev@1 {\n+\t\t\t\tcompatible = \"spidev\";\n+\t\t\t\treg = <1>;      /* CE1 */\n+\t\t\t\t#address-cells = <1>;\n+\t\t\t\t#size-cells = <0>;\n+\t\t\t\tspi-max-frequency = <125000000>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\tcs0_pin  = <&frag0>,\"brcm,pins:0\",\n+\t\t\t   <&frag1>,\"cs-gpios:4\";\n+\t\tcs1_pin  = <&frag0>,\"brcm,pins:4\",\n+\t\t\t   <&frag1>,\"cs-gpios:16\";\n+\t\tcs0_spidev = <&spidev4_0>,\"status\";\n+\t\tcs1_spidev = <&spidev4_1>,\"status\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/spi5-1cs-overlay.dts b/arch/arm/boot/dts/overlays/spi5-1cs-overlay.dts\nnew file mode 100644\nindex 000000000000..c0f8cb8510ee\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/spi5-1cs-overlay.dts\n@@ -0,0 +1,44 @@\n+/dts-v1/;\n+/plugin/;\n+\n+\n+/ {\n+\tcompatible = \"brcm,bcm2711\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&spi5_cs_pins>;\n+\t\tfrag0: __overlay__ {\n+\t\t\tbrcm,pins = <12>;\n+\t\t\tbrcm,function = <1>; /* output */\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&spi5>;\n+\t\tfrag1: __overlay__ {\n+\t\t\t/* needed to avoid dtc warning */\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tpinctrl-names = \"default\";\n+\t\t        pinctrl-0 = <&spi5_pins &spi5_cs_pins>;\n+\t\t\tcs-gpios = <&gpio 12 1>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tspidev5_0: spidev@0 {\n+\t\t\t\tcompatible = \"spidev\";\n+\t\t\t\treg = <0>;      /* CE0 */\n+\t\t\t\t#address-cells = <1>;\n+\t\t\t\t#size-cells = <0>;\n+\t\t\t\tspi-max-frequency = <125000000>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\tcs0_pin  = <&frag0>,\"brcm,pins:0\",\n+\t\t\t   <&frag1>,\"cs-gpios:4\";\n+\t\tcs0_spidev = <&spidev5_0>,\"status\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/spi5-2cs-overlay.dts b/arch/arm/boot/dts/overlays/spi5-2cs-overlay.dts\nnew file mode 100644\nindex 000000000000..7758b9c00b4e\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/spi5-2cs-overlay.dts\n@@ -0,0 +1,56 @@\n+/dts-v1/;\n+/plugin/;\n+\n+\n+/ {\n+\tcompatible = \"brcm,bcm2711\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&spi5_cs_pins>;\n+\t\tfrag0: __overlay__ {\n+\t\t\tbrcm,pins = <12 26>;\n+\t\t\tbrcm,function = <1>; /* output */\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&spi5>;\n+\t\tfrag1: __overlay__ {\n+\t\t\t/* needed to avoid dtc warning */\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tpinctrl-names = \"default\";\n+\t\t        pinctrl-0 = <&spi5_pins &spi5_cs_pins>;\n+\t\t\tcs-gpios = <&gpio 12 1>, <&gpio 26 1>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tspidev5_0: spidev@0 {\n+\t\t\t\tcompatible = \"spidev\";\n+\t\t\t\treg = <0>;      /* CE0 */\n+\t\t\t\t#address-cells = <1>;\n+\t\t\t\t#size-cells = <0>;\n+\t\t\t\tspi-max-frequency = <125000000>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\n+\t\t\tspidev5_1: spidev@1 {\n+\t\t\t\tcompatible = \"spidev\";\n+\t\t\t\treg = <1>;      /* CE1 */\n+\t\t\t\t#address-cells = <1>;\n+\t\t\t\t#size-cells = <0>;\n+\t\t\t\tspi-max-frequency = <125000000>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\tcs0_pin  = <&frag0>,\"brcm,pins:0\",\n+\t\t\t   <&frag1>,\"cs-gpios:4\";\n+\t\tcs1_pin  = <&frag0>,\"brcm,pins:4\",\n+\t\t\t   <&frag1>,\"cs-gpios:16\";\n+\t\tcs0_spidev = <&spidev5_0>,\"status\";\n+\t\tcs1_spidev = <&spidev5_1>,\"status\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/spi6-1cs-overlay.dts b/arch/arm/boot/dts/overlays/spi6-1cs-overlay.dts\nnew file mode 100644\nindex 000000000000..8c8a953eca01\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/spi6-1cs-overlay.dts\n@@ -0,0 +1,44 @@\n+/dts-v1/;\n+/plugin/;\n+\n+\n+/ {\n+\tcompatible = \"brcm,bcm2711\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&spi6_cs_pins>;\n+\t\tfrag0: __overlay__ {\n+\t\t\tbrcm,pins = <18>;\n+\t\t\tbrcm,function = <1>; /* output */\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&spi6>;\n+\t\tfrag1: __overlay__ {\n+\t\t\t/* needed to avoid dtc warning */\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tpinctrl-names = \"default\";\n+\t\t        pinctrl-0 = <&spi6_pins &spi6_cs_pins>;\n+\t\t\tcs-gpios = <&gpio 18 1>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tspidev6_0: spidev@0 {\n+\t\t\t\tcompatible = \"spidev\";\n+\t\t\t\treg = <0>;      /* CE0 */\n+\t\t\t\t#address-cells = <1>;\n+\t\t\t\t#size-cells = <0>;\n+\t\t\t\tspi-max-frequency = <125000000>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\tcs0_pin  = <&frag0>,\"brcm,pins:0\",\n+\t\t\t   <&frag1>,\"cs-gpios:4\";\n+\t\tcs0_spidev = <&spidev6_0>,\"status\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/spi6-2cs-overlay.dts b/arch/arm/boot/dts/overlays/spi6-2cs-overlay.dts\nnew file mode 100644\nindex 000000000000..2ff897f21aed\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/spi6-2cs-overlay.dts\n@@ -0,0 +1,56 @@\n+/dts-v1/;\n+/plugin/;\n+\n+\n+/ {\n+\tcompatible = \"brcm,bcm2711\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&spi6_cs_pins>;\n+\t\tfrag0: __overlay__ {\n+\t\t\tbrcm,pins = <18 27>;\n+\t\t\tbrcm,function = <1>; /* output */\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&spi6>;\n+\t\tfrag1: __overlay__ {\n+\t\t\t/* needed to avoid dtc warning */\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tpinctrl-names = \"default\";\n+\t\t        pinctrl-0 = <&spi6_pins &spi6_cs_pins>;\n+\t\t\tcs-gpios = <&gpio 18 1>, <&gpio 27 1>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tspidev6_0: spidev@0 {\n+\t\t\t\tcompatible = \"spidev\";\n+\t\t\t\treg = <0>;      /* CE0 */\n+\t\t\t\t#address-cells = <1>;\n+\t\t\t\t#size-cells = <0>;\n+\t\t\t\tspi-max-frequency = <125000000>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\n+\t\t\tspidev6_1: spidev@1 {\n+\t\t\t\tcompatible = \"spidev\";\n+\t\t\t\treg = <1>;      /* CE1 */\n+\t\t\t\t#address-cells = <1>;\n+\t\t\t\t#size-cells = <0>;\n+\t\t\t\tspi-max-frequency = <125000000>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\tcs0_pin  = <&frag0>,\"brcm,pins:0\",\n+\t\t\t   <&frag1>,\"cs-gpios:4\";\n+\t\tcs1_pin  = <&frag0>,\"brcm,pins:4\",\n+\t\t\t   <&frag1>,\"cs-gpios:16\";\n+\t\tcs0_spidev = <&spidev6_0>,\"status\";\n+\t\tcs1_spidev = <&spidev6_1>,\"status\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/ssd1306-overlay.dts b/arch/arm/boot/dts/overlays/ssd1306-overlay.dts\nnew file mode 100644\nindex 000000000000..84cf10e489d3\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/ssd1306-overlay.dts\n@@ -0,0 +1,36 @@\n+// Overlay for SSD1306 128x64 and 128x32 OLED displays\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+    compatible = \"brcm,bcm2835\";\n+\n+    fragment@0 {\n+\ttarget = <&i2c1>;\n+\t__overlay__ {\n+\t    status = \"okay\";\n+\n+\t    #address-cells = <1>;\n+\t    #size-cells = <0>;\n+\n+\t    ssd1306: oled@3c{\n+\t\tcompatible = \"solomon,ssd1306fb-i2c\";\n+\t\treg = <0x3c>;\n+\t\tsolomon,width = <128>;\n+\t\tsolomon,height = <64>;\n+\t\tsolomon,page-offset = <0>;\n+\t    };\n+\t};\n+    };\n+\n+    __overrides__ {\n+\taddress = <&ssd1306>,\"reg:0\";\n+\twidth = <&ssd1306>,\"solomon,width:0\";\n+\theight = <&ssd1306>,\"solomon,height:0\";\n+\toffset = <&ssd1306>,\"solomon,page-offset:0\";\n+\tnormal = <&ssd1306>,\"solomon,segment-no-remap?\";\n+\tsequential = <&ssd1306>,\"solomon,com-seq?\";\n+\tremapped = <&ssd1306>,\"solomon,com-lrremap?\";\n+\tinverted = <&ssd1306>,\"solomon,com-invdir?\";\n+    };\n+};\ndiff --git a/arch/arm/boot/dts/overlays/ssd1306-spi-overlay.dts b/arch/arm/boot/dts/overlays/ssd1306-spi-overlay.dts\nnew file mode 100644\nindex 000000000000..ffc90c7cecf6\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/ssd1306-spi-overlay.dts\n@@ -0,0 +1,84 @@\n+/*\n+ * Device Tree overlay for SSD1306 based SPI OLED display\n+ *\n+ */\n+\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&spi0>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&spidev0>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&spidev1>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\tfragment@3 {\n+\t\ttarget = <&gpio>;\n+\t\t__overlay__ {\n+\t\t\tssd1306_pins: ssd1306_pins {\n+                                brcm,pins = <25 24>;\n+                                brcm,function = <1 1>; /* out out */\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@4 {\n+\t\ttarget = <&spi0>;\n+\t\t__overlay__ {\n+\t\t\t/* needed to avoid dtc warning */\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tssd1306: ssd1306@0{\n+\t\t\t\tcompatible = \"solomon,ssd1306\";\n+\t\t\t\treg = <0>;\n+\t\t\t\tpinctrl-names = \"default\";\n+\t\t\t\tpinctrl-0 = <&ssd1306_pins>;\n+\n+\t\t\t\tspi-max-frequency = <10000000>;\n+\t\t\t\tbgr = <0>;\n+\t\t\t\tbpp = <1>;\n+\t\t\t\trotate = <0>;\n+\t\t\t\tfps = <25>;\n+\t\t\t\tbuswidth = <8>;\n+\t\t\t\treset-gpios = <&gpio 25 1>;\n+\t\t\t\tdc-gpios = <&gpio 24 0>;\n+\t\t\t\tdebug = <0>;\n+\n+\t\t\t\tsolomon,height = <64>;\n+\t\t\t\tsolomon,width = <128>;\n+\t\t\t\tsolomon,page-offset = <0>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\tspeed     = <&ssd1306>,\"spi-max-frequency:0\";\n+\t\trotate    = <&ssd1306>,\"rotate:0\";\n+\t\tfps       = <&ssd1306>,\"fps:0\";\n+\t\tdebug     = <&ssd1306>,\"debug:0\";\n+\t\tdc_pin    = <&ssd1306>,\"dc-gpios:4\",\n+\t\t            <&ssd1306_pins>,\"brcm,pins:4\";\n+\t\treset_pin = <&ssd1306>,\"reset-gpios:4\",\n+\t\t            <&ssd1306_pins>,\"brcm,pins:0\";\n+\t\theight    = <&ssd1306>,\"solomon,height:0\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/ssd1351-spi-overlay.dts b/arch/arm/boot/dts/overlays/ssd1351-spi-overlay.dts\nnew file mode 100644\nindex 000000000000..ffc872c60648\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/ssd1351-spi-overlay.dts\n@@ -0,0 +1,83 @@\n+/*\n+ * Device Tree overlay for SSD1351 based SPI OLED display\n+ *\n+ */\n+\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&spi0>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&spidev0>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&spidev1>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\tfragment@3 {\n+\t\ttarget = <&gpio>;\n+\t\t__overlay__ {\n+\t\t\tssd1351_pins: ssd1351_pins {\n+                                brcm,pins = <25 24>;\n+                                brcm,function = <1 1>; /* out out */\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@4 {\n+\t\ttarget = <&spi0>;\n+\t\t__overlay__ {\n+\t\t\t/* needed to avoid dtc warning */\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tssd1351: ssd1351@0{\n+\t\t\t\tcompatible = \"solomon,ssd1351\";\n+\t\t\t\treg = <0>;\n+\t\t\t\tpinctrl-names = \"default\";\n+\t\t\t\tpinctrl-0 = <&ssd1351_pins>;\n+\n+\t\t\t\tspi-max-frequency = <4500000>;\n+\t\t\t\tbgr = <0>;\n+\t\t\t\tbpp = <16>;\n+\t\t\t\trotate = <0>;\n+\t\t\t\tfps = <25>;\n+\t\t\t\tbuswidth = <8>;\n+\t\t\t\treset-gpios = <&gpio 25 1>;\n+\t\t\t\tdc-gpios = <&gpio 24 0>;\n+\t\t\t\tdebug = <0>;\n+\n+\t\t\t\tsolomon,height = <128>;\n+\t\t\t\tsolomon,width = <128>;\n+\t\t\t\tsolomon,page-offset = <0>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\tspeed     = <&ssd1351>,\"spi-max-frequency:0\";\n+\t\trotate    = <&ssd1351>,\"rotate:0\";\n+\t\tfps       = <&ssd1351>,\"fps:0\";\n+\t\tdebug     = <&ssd1351>,\"debug:0\";\n+\t\tdc_pin    = <&ssd1351>,\"dc-gpios:4\",\n+\t\t            <&ssd1351_pins>,\"brcm,pins:4\";\n+\t\treset_pin = <&ssd1351>,\"reset-gpios:4\",\n+\t\t            <&ssd1351_pins>,\"brcm,pins:0\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/superaudioboard-overlay.dts b/arch/arm/boot/dts/overlays/superaudioboard-overlay.dts\nnew file mode 100755\nindex 000000000000..bad61535981e\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/superaudioboard-overlay.dts\n@@ -0,0 +1,73 @@\n+// Definitions for SuperAudioBoard\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&sound>;\n+\t\t__overlay__ {\n+\t\t\tcompatible = \"simple-audio-card\";\n+\t\t\ti2s-controller = <&i2s>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tsimple-audio-card,name = \"SuperAudioBoard\";\n+\n+\t\t\tsimple-audio-card,widgets =\n+\t\t\t\t\"Line\", \"Line In\",\n+\t\t\t\t\"Line\", \"Line Out\";\n+\n+\t\t\tsimple-audio-card,routing =\n+\t\t\t\t\"Line Out\",\"AOUTA+\",\n+\t\t\t\t\"Line Out\",\"AOUTA-\",\n+\t\t\t\t\"Line Out\",\"AOUTB+\",\n+\t\t\t\t\"Line Out\",\"AOUTB-\",\n+\t\t\t\t\"AINA\",\"Line In\",\n+\t\t\t\t\"AINB\",\"Line In\";\n+\n+\t\t\tsimple-audio-card,format = \"i2s\";\n+\n+\t\t\tsimple-audio-card,bitclock-master = <&sound_master>;\n+\t\t\tsimple-audio-card,frame-master = <&sound_master>;\n+\n+\t\t\tsimple-audio-card,cpu {\n+\t\t\t\tsound-dai = <&i2s>;\n+\t\t\t\tdai-tdm-slot-num = <2>;\n+\t\t\t\tdai-tdm-slot-width = <32>;\n+\t\t\t};\n+\n+\t\t\tsound_master: simple-audio-card,codec {\n+\t\t\t\tsound-dai = <&cs4271>;\n+\t\t\t\tsystem-clock-frequency = <24576000>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&i2s>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+    \n+\tfragment@2 {\n+\t\ttarget = <&i2c1>;\n+\t\t__overlay__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tcs4271: cs4271@10 {\n+\t\t\t\t#sound-dai-cells = <0>;\n+\t\t\t\tcompatible = \"cirrus,cs4271\";\n+\t\t\t\treg = <0x10>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t\treset-gpio = <&gpio 26 0>; /* Pin 26, active high */\n+\t\t\t};\n+\t\t};\n+\t};\n+\t__overrides__ {\n+\t\tgpiopin = <&cs4271>,\"reset-gpio:4\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/sx150x-overlay.dts b/arch/arm/boot/dts/overlays/sx150x-overlay.dts\nnew file mode 100644\nindex 000000000000..1d1069345da2\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/sx150x-overlay.dts\n@@ -0,0 +1,1706 @@\n+// Definitions for SX150x I2C GPIO Expanders from Semtech\n+\n+// dtparams:\n+//     sx150<x>-<n>-<m>          - Enables SX150X device on I2C#<n> with slave address <m>. <x> may be 1-9.\n+//                                 <n> may be 0 or 1.  Permissible values of <m> (which is denoted in hex)\n+//                                 depend on the device variant.\n+//                                 For SX1501, SX1502, SX1504 and SX1505, <m> may be 20 or 21.\n+//                                 For SX1503 and SX1506, <m> may be 20.\n+//                                 For SX1507 and SX1509, <m> may be 3E, 3F, 70 or 71.\n+//                                 For SX1508, <m> may be 20, 21, 22 or 23.\n+//     sx150<x>-<n>-<m>-int-gpio - Integer, enables interrupts on SX150X device on I2C#<n> with slave address <m>,\n+//                                 specifies the GPIO pin to which NINT output of SX150X is connected.\n+//\n+//\n+// Example 1: A single SX1505 device on I2C#1 with its slave address set to 0x20 and NINT output connected to GPIO25:\n+// dtoverlay=sx150x:sx1505-1-20,sx1505-1-20-int-gpio=25\n+//\n+// Example 2: Two SX1507 devices on I2C#0 with their slave addresses set to 0x3E and 0x70 (interrupts not used):\n+// dtoverlay=sx150x:sx1507-0-3E,sx1507-0-70\n+\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\t// Enable I2C#0 interface\n+\tfragment@0 {\n+\t\ttarget = <&i2c0>;\n+\t\t__dormant__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\t// Enable I2C#1 interface\n+\tfragment@1 {\n+\t\ttarget = <&i2c1>;\n+\t\t__dormant__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\t// Enable a SX1501 on I2C#0 at slave addr 0x20\n+\tfragment@2 {\n+\t\ttarget = <&i2c0>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tsx1501_0_20: sx150x@20 {\n+\t\t\t\tcompatible = \"semtech,sx1501q\";\n+\t\t\t\treg = <0x20>;\n+\t\t\t\tgpio-controller;\n+\t\t\t\t#gpio-cells = <2>;\n+\t\t\t\t#interrupt-cells = <2>;\n+\t\t\t\tinterrupts = <25 2>; /* 1st word overwritten by sx1501-0-20-int-gpio parameter\n+\t\t\t\t                        2nd word is 2 for falling-edge triggered */\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t// Enable a SX1501 on I2C#1 at slave addr 0x20\n+\tfragment@3 {\n+\t\ttarget = <&i2c1>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tsx1501_1_20: sx150x@20 {\n+\t\t\t\tcompatible = \"semtech,sx1501q\";\n+\t\t\t\treg = <0x20>;\n+\t\t\t\tgpio-controller;\n+\t\t\t\t#gpio-cells = <2>;\n+\t\t\t\t#interrupt-cells = <2>;\n+\t\t\t\tinterrupts = <25 2>; /* 1st word overwritten by sx1501-1-20-int-gpio parameter\n+\t\t\t\t                        2nd word is 2 for falling-edge triggered */\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t// Enable a SX1501 on I2C#0 at slave addr 0x21\n+\tfragment@4 {\n+\t\ttarget = <&i2c0>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tsx1501_0_21: sx150x@21 {\n+\t\t\t\tcompatible = \"semtech,sx1501q\";\n+\t\t\t\treg = <0x21>;\n+\t\t\t\tgpio-controller;\n+\t\t\t\t#gpio-cells = <2>;\n+\t\t\t\t#interrupt-cells = <2>;\n+\t\t\t\tinterrupts = <25 2>; /* 1st word overwritten by sx1501-0-21-int-gpio parameter\n+\t\t\t\t                        2nd word is 2 for falling-edge triggered */\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t// Enable a SX1501 on I2C#1 at slave addr 0x21\n+\tfragment@5 {\n+\t\ttarget = <&i2c1>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tsx1501_1_21: sx150x@21 {\n+\t\t\t\tcompatible = \"semtech,sx1501q\";\n+\t\t\t\treg = <0x21>;\n+\t\t\t\tgpio-controller;\n+\t\t\t\t#gpio-cells = <2>;\n+\t\t\t\t#interrupt-cells = <2>;\n+\t\t\t\tinterrupts = <25 2>; /* 1st word overwritten by sx1501-1-21-int-gpio parameter\n+\t\t\t\t                        2nd word is 2 for falling-edge triggered */\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t// Enable a SX1502 on I2C#0 at slave addr 0x20\n+\tfragment@6 {\n+\t\ttarget = <&i2c0>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tsx1502_0_20: sx150x@20 {\n+\t\t\t\tcompatible = \"semtech,sx1502q\";\n+\t\t\t\treg = <0x20>;\n+\t\t\t\tgpio-controller;\n+\t\t\t\t#gpio-cells = <2>;\n+\t\t\t\t#interrupt-cells = <2>;\n+\t\t\t\tinterrupts = <25 2>; /* 1st word overwritten by sx1502-0-20-int-gpio parameter\n+\t\t\t\t                        2nd word is 2 for falling-edge triggered */\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t// Enable a SX1502 on I2C#1 at slave addr 0x20\n+\tfragment@7 {\n+\t\ttarget = <&i2c1>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tsx1502_1_20: sx150x@20 {\n+\t\t\t\tcompatible = \"semtech,sx1502q\";\n+\t\t\t\treg = <0x20>;\n+\t\t\t\tgpio-controller;\n+\t\t\t\t#gpio-cells = <2>;\n+\t\t\t\t#interrupt-cells = <2>;\n+\t\t\t\tinterrupts = <25 2>; /* 1st word overwritten by sx1502-1-20-int-gpio parameter\n+\t\t\t\t                        2nd word is 2 for falling-edge triggered */\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t// Enable a SX1502 on I2C#0 at slave addr 0x21\n+\tfragment@8 {\n+\t\ttarget = <&i2c0>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tsx1502_0_21: sx150x@21 {\n+\t\t\t\tcompatible = \"semtech,sx1502q\";\n+\t\t\t\treg = <0x21>;\n+\t\t\t\tgpio-controller;\n+\t\t\t\t#gpio-cells = <2>;\n+\t\t\t\t#interrupt-cells = <2>;\n+\t\t\t\tinterrupts = <25 2>; /* 1st word overwritten by sx1502-0-21-int-gpio parameter\n+\t\t\t\t                        2nd word is 2 for falling-edge triggered */\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t// Enable a SX1502 on I2C#1 at slave addr 0x21\n+\tfragment@9 {\n+\t\ttarget = <&i2c1>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tsx1502_1_21: sx150x@21 {\n+\t\t\t\tcompatible = \"semtech,sx1502q\";\n+\t\t\t\treg = <0x21>;\n+\t\t\t\tgpio-controller;\n+\t\t\t\t#gpio-cells = <2>;\n+\t\t\t\t#interrupt-cells = <2>;\n+\t\t\t\tinterrupts = <25 2>; /* 1st word overwritten by sx1501-1-21-int-gpio parameter\n+\t\t\t\t                        2nd word is 2 for falling-edge triggered */\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t// Enable a SX1503 on I2C#0 at slave addr 0x20\n+\tfragment@10 {\n+\t\ttarget = <&i2c0>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tsx1503_0_20: sx150x@20 {\n+\t\t\t\tcompatible = \"semtech,sx1503q\";\n+\t\t\t\treg = <0x20>;\n+\t\t\t\tgpio-controller;\n+\t\t\t\t#gpio-cells = <2>;\n+\t\t\t\t#interrupt-cells = <2>;\n+\t\t\t\tinterrupts = <25 2>; /* 1st word overwritten by sx1503-0-20-int-gpio parameter\n+\t\t\t\t                        2nd word is 2 for falling-edge triggered */\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t// Enable a SX1503 on I2C#1 at slave addr 0x20\n+\tfragment@11 {\n+\t\ttarget = <&i2c1>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tsx1503_1_20: sx150x@20 {\n+\t\t\t\tcompatible = \"semtech,sx1503q\";\n+\t\t\t\treg = <0x20>;\n+\t\t\t\tgpio-controller;\n+\t\t\t\t#gpio-cells = <2>;\n+\t\t\t\t#interrupt-cells = <2>;\n+\t\t\t\tinterrupts = <25 2>; /* 1st word overwritten by sx1503-1-20-int-gpio parameter\n+\t\t\t\t                        2nd word is 2 for falling-edge triggered */\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t// Enable a SX1504 on I2C#0 at slave addr 0x20\n+\tfragment@12 {\n+\t\ttarget = <&i2c0>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tsx1504_0_20: sx150x@20 {\n+\t\t\t\tcompatible = \"semtech,sx1504q\";\n+\t\t\t\treg = <0x20>;\n+\t\t\t\tgpio-controller;\n+\t\t\t\t#gpio-cells = <2>;\n+\t\t\t\t#interrupt-cells = <2>;\n+\t\t\t\tinterrupts = <25 2>; /* 1st word overwritten by sx1504-0-20-int-gpio parameter\n+\t\t\t\t                        2nd word is 2 for falling-edge triggered */\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t// Enable a SX1504 on I2C#1 at slave addr 0x20\n+\tfragment@13 {\n+\t\ttarget = <&i2c1>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tsx1504_1_20: sx150x@20 {\n+\t\t\t\tcompatible = \"semtech,sx1504q\";\n+\t\t\t\treg = <0x20>;\n+\t\t\t\tgpio-controller;\n+\t\t\t\t#gpio-cells = <2>;\n+\t\t\t\t#interrupt-cells = <2>;\n+\t\t\t\tinterrupts = <25 2>; /* 1st word overwritten by sx1504-1-20-int-gpio parameter\n+\t\t\t\t                        2nd word is 2 for falling-edge triggered */\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t// Enable a SX1504 on I2C#0 at slave addr 0x21\n+\tfragment@14 {\n+\t\ttarget = <&i2c0>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tsx1504_0_21: sx150x@21 {\n+\t\t\t\tcompatible = \"semtech,sx1504q\";\n+\t\t\t\treg = <0x21>;\n+\t\t\t\tgpio-controller;\n+\t\t\t\t#gpio-cells = <2>;\n+\t\t\t\t#interrupt-cells = <2>;\n+\t\t\t\tinterrupts = <25 2>; /* 1st word overwritten by sx1504-0-21-int-gpio parameter\n+\t\t\t\t                        2nd word is 2 for falling-edge triggered */\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t// Enable a SX1504 on I2C#1 at slave addr 0x21\n+\tfragment@15 {\n+\t\ttarget = <&i2c1>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tsx1504_1_21: sx150x@21 {\n+\t\t\t\tcompatible = \"semtech,sx1504q\";\n+\t\t\t\treg = <0x21>;\n+\t\t\t\tgpio-controller;\n+\t\t\t\t#gpio-cells = <2>;\n+\t\t\t\t#interrupt-cells = <2>;\n+\t\t\t\tinterrupts = <25 2>; /* 1st word overwritten by sx1504-1-20-int-gpio parameter\n+\t\t\t\t                        2nd word is 2 for falling-edge triggered */\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t// Enable a SX1505 on I2C#0 at slave addr 0x20\n+\tfragment@16 {\n+\t\ttarget = <&i2c0>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tsx1505_0_20: sx150x@20 {\n+\t\t\t\tcompatible = \"semtech,sx1505q\";\n+\t\t\t\treg = <0x20>;\n+\t\t\t\tgpio-controller;\n+\t\t\t\t#gpio-cells = <2>;\n+\t\t\t\t#interrupt-cells = <2>;\n+\t\t\t\tinterrupts = <25 2>; /* 1st word overwritten by sx1505-0-20-int-gpio parameter\n+\t\t\t\t                        2nd word is 2 for falling-edge triggered */\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t// Enable a SX1505 on I2C#1 at slave addr 0x20\n+\tfragment@17 {\n+\t\ttarget = <&i2c1>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tsx1505_1_20: sx150x@20 {\n+\t\t\t\tcompatible = \"semtech,sx1505q\";\n+\t\t\t\treg = <0x20>;\n+\t\t\t\tgpio-controller;\n+\t\t\t\t#gpio-cells = <2>;\n+\t\t\t\t#interrupt-cells = <2>;\n+\t\t\t\tinterrupts = <25 2>; /* 1st word overwritten by sx1505-1-20-int-gpio parameter\n+\t\t\t\t                        2nd word is 2 for falling-edge triggered */\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t// Enable a SX1505 on I2C#0 at slave addr 0x21\n+\tfragment@18 {\n+\t\ttarget = <&i2c0>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tsx1505_0_21: sx150x@21 {\n+\t\t\t\tcompatible = \"semtech,sx1505q\";\n+\t\t\t\treg = <0x21>;\n+\t\t\t\tgpio-controller;\n+\t\t\t\t#gpio-cells = <2>;\n+\t\t\t\t#interrupt-cells = <2>;\n+\t\t\t\tinterrupts = <25 2>; /* 1st word overwritten by sx1505-0-21-int-gpio parameter\n+\t\t\t\t                        2nd word is 2 for falling-edge triggered */\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t// Enable a SX1505 on I2C#1 at slave addr 0x21\n+\tfragment@19 {\n+\t\ttarget = <&i2c1>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tsx1505_1_21: sx150x@21 {\n+\t\t\t\tcompatible = \"semtech,sx1505q\";\n+\t\t\t\treg = <0x21>;\n+\t\t\t\tgpio-controller;\n+\t\t\t\t#gpio-cells = <2>;\n+\t\t\t\t#interrupt-cells = <2>;\n+\t\t\t\tinterrupts = <25 2>; /* 1st word overwritten by sx1505-1-21-int-gpio parameter\n+\t\t\t\t                        2nd word is 2 for falling-edge triggered */\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t// Enable a SX1506 on I2C#0 at slave addr 0x20\n+\tfragment@20 {\n+\t\ttarget = <&i2c0>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tsx1506_0_20: sx150x@20 {\n+\t\t\t\tcompatible = \"semtech,sx1506q\";\n+\t\t\t\treg = <0x20>;\n+\t\t\t\tgpio-controller;\n+\t\t\t\t#gpio-cells = <2>;\n+\t\t\t\t#interrupt-cells = <2>;\n+\t\t\t\tinterrupts = <25 2>; /* 1st word overwritten by sx1506-0-20-int-gpio parameter\n+\t\t\t\t                        2nd word is 2 for falling-edge triggered */\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t// Enable a SX1506 on I2C#1 at slave addr 0x20\n+\tfragment@21 {\n+\t\ttarget = <&i2c1>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tsx1506_1_20: sx150x@20 {\n+\t\t\t\tcompatible = \"semtech,sx1506q\";\n+\t\t\t\treg = <0x20>;\n+\t\t\t\tgpio-controller;\n+\t\t\t\t#gpio-cells = <2>;\n+\t\t\t\t#interrupt-cells = <2>;\n+\t\t\t\tinterrupts = <25 2>; /* 1st word overwritten by sx1506-1-20-int-gpio parameter\n+\t\t\t\t                        2nd word is 2 for falling-edge triggered */\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t// Enable a SX1507 on I2C#0 at slave addr 0x3E\n+\tfragment@22 {\n+\t\ttarget = <&i2c0>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tsx1507_0_3E: sx150x@3E {\n+\t\t\t\tcompatible = \"semtech,sx1507q\";\n+\t\t\t\treg = <0x3E>;\n+\t\t\t\tgpio-controller;\n+\t\t\t\t#gpio-cells = <2>;\n+\t\t\t\t#interrupt-cells = <2>;\n+\t\t\t\tinterrupts = <25 2>; /* 1st word overwritten by sx1507_0_3E-int-gpio parameter\n+\t\t\t\t                        2nd word is 2 for falling-edge triggered */\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t// Enable a SX1507 on I2C#1 at slave addr 0x3E\n+\tfragment@23 {\n+\t\ttarget = <&i2c1>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tsx1507_1_3E: sx150x@3E {\n+\t\t\t\tcompatible = \"semtech,sx1507q\";\n+\t\t\t\treg = <0x3E>;\n+\t\t\t\tgpio-controller;\n+\t\t\t\t#gpio-cells = <2>;\n+\t\t\t\t#interrupt-cells = <2>;\n+\t\t\t\tinterrupts = <25 2>; /* 1st word overwritten by sx1507_1_3E-int-gpio parameter\n+\t\t\t\t                        2nd word is 2 for falling-edge triggered */\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t// Enable a SX1507 on I2C#0 at slave addr 0x3F\n+\tfragment@24 {\n+\t\ttarget = <&i2c0>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tsx1507_0_3F: sx150x@3F {\n+\t\t\t\tcompatible = \"semtech,sx1507q\";\n+\t\t\t\treg = <0x3F>;\n+\t\t\t\tgpio-controller;\n+\t\t\t\t#gpio-cells = <2>;\n+\t\t\t\t#interrupt-cells = <2>;\n+\t\t\t\tinterrupts = <25 2>; /* 1st word overwritten by sx1507_0_3F-int-gpio parameter\n+\t\t\t\t                        2nd word is 2 for falling-edge triggered */\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t// Enable a SX1507 on I2C#1 at slave addr 0x3F\n+\tfragment@25 {\n+\t\ttarget = <&i2c1>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tsx1507_1_3F: sx150x@3F {\n+\t\t\t\tcompatible = \"semtech,sx1507q\";\n+\t\t\t\treg = <0x3F>;\n+\t\t\t\tgpio-controller;\n+\t\t\t\t#gpio-cells = <2>;\n+\t\t\t\t#interrupt-cells = <2>;\n+\t\t\t\tinterrupts = <25 2>; /* 1st word overwritten by sx1507_1_3F-int-gpio parameter\n+\t\t\t\t                        2nd word is 2 for falling-edge triggered */\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t// Enable a SX1507 on I2C#0 at slave addr 0x70\n+\tfragment@26 {\n+\t\ttarget = <&i2c0>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tsx1507_0_70: sx150x@70 {\n+\t\t\t\tcompatible = \"semtech,sx1507q\";\n+\t\t\t\treg = <0x70>;\n+\t\t\t\tgpio-controller;\n+\t\t\t\t#gpio-cells = <2>;\n+\t\t\t\t#interrupt-cells = <2>;\n+\t\t\t\tinterrupts = <25 2>; /* 1st word overwritten by sx1507-0-70-int-gpio parameter\n+\t\t\t\t                        2nd word is 2 for falling-edge triggered */\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t// Enable a SX1507 on I2C#1 at slave addr 0x70\n+\tfragment@27 {\n+\t\ttarget = <&i2c1>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tsx1507_1_70: sx150x@70 {\n+\t\t\t\tcompatible = \"semtech,sx1507q\";\n+\t\t\t\treg = <0x70>;\n+\t\t\t\tgpio-controller;\n+\t\t\t\t#gpio-cells = <2>;\n+\t\t\t\t#interrupt-cells = <2>;\n+\t\t\t\tinterrupts = <25 2>; /* 1st word overwritten by sx1507-1-70-int-gpio parameter\n+\t\t\t\t                        2nd word is 2 for falling-edge triggered */\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t// Enable a SX1507 on I2C#0 at slave addr 0x71\n+\tfragment@28 {\n+\t\ttarget = <&i2c0>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tsx1507_0_71: sx150x@71 {\n+\t\t\t\tcompatible = \"semtech,sx1507q\";\n+\t\t\t\treg = <0x71>;\n+\t\t\t\tgpio-controller;\n+\t\t\t\t#gpio-cells = <2>;\n+\t\t\t\t#interrupt-cells = <2>;\n+\t\t\t\tinterrupts = <25 2>; /* 1st word overwritten by sx1507-0-71-int-gpio parameter\n+\t\t\t\t                        2nd word is 2 for falling-edge triggered */\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t// Enable a SX1507 on I2C#1 at slave addr 0x71\n+\tfragment@29 {\n+\t\ttarget = <&i2c1>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tsx1507_1_71: sx150x@71 {\n+\t\t\t\tcompatible = \"semtech,sx1507q\";\n+\t\t\t\treg = <0x71>;\n+\t\t\t\tgpio-controller;\n+\t\t\t\t#gpio-cells = <2>;\n+\t\t\t\t#interrupt-cells = <2>;\n+\t\t\t\tinterrupts = <25 2>; /* 1st word overwritten by sx1507-1-71-int-gpio parameter\n+\t\t\t\t                        2nd word is 2 for falling-edge triggered */\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t// Enable a SX1508 on I2C#0 at slave addr 0x20\n+\tfragment@30 {\n+\t\ttarget = <&i2c0>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tsx1508_0_20: sx150x@20 {\n+\t\t\t\tcompatible = \"semtech,sx1508q\";\n+\t\t\t\treg = <0x20>;\n+\t\t\t\tgpio-controller;\n+\t\t\t\t#gpio-cells = <2>;\n+\t\t\t\t#interrupt-cells = <2>;\n+\t\t\t\tinterrupts = <25 2>; /* 1st word overwritten by sx1508-0-20-int-gpio parameter\n+\t\t\t\t                        2nd word is 2 for falling-edge triggered */\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t// Enable a SX1508 on I2C#1 at slave addr 0x20\n+\tfragment@31 {\n+\t\ttarget = <&i2c1>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tsx1508_1_20: sx150x@20 {\n+\t\t\t\tcompatible = \"semtech,sx1508q\";\n+\t\t\t\treg = <0x20>;\n+\t\t\t\tgpio-controller;\n+\t\t\t\t#gpio-cells = <2>;\n+\t\t\t\t#interrupt-cells = <2>;\n+\t\t\t\tinterrupts = <25 2>; /* 1st word overwritten by sx1508-1-20-int-gpio parameter\n+\t\t\t\t                        2nd word is 2 for falling-edge triggered */\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t// Enable a SX1508 on I2C#0 at slave addr 0x21\n+\tfragment@32 {\n+\t\ttarget = <&i2c0>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tsx1508_0_21: sx150x@21 {\n+\t\t\t\tcompatible = \"semtech,sx1508q\";\n+\t\t\t\treg = <0x21>;\n+\t\t\t\tgpio-controller;\n+\t\t\t\t#gpio-cells = <2>;\n+\t\t\t\t#interrupt-cells = <2>;\n+\t\t\t\tinterrupts = <25 2>; /* 1st word overwritten by sx1508-0-21-int-gpio parameter\n+\t\t\t\t                        2nd word is 2 for falling-edge triggered */\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t// Enable a SX1508 on I2C#1 at slave addr 0x21\n+\tfragment@33 {\n+\t\ttarget = <&i2c1>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tsx1508_1_21: sx150x@21 {\n+\t\t\t\tcompatible = \"semtech,sx1508q\";\n+\t\t\t\treg = <0x21>;\n+\t\t\t\tgpio-controller;\n+\t\t\t\t#gpio-cells = <2>;\n+\t\t\t\t#interrupt-cells = <2>;\n+\t\t\t\tinterrupts = <25 2>; /* 1st word overwritten by sx1508-1-21-int-gpio parameter\n+\t\t\t\t                        2nd word is 2 for falling-edge triggered */\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t// Enable a SX1508 on I2C#0 at slave addr 0x22\n+\tfragment@34 {\n+\t\ttarget = <&i2c0>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tsx1508_0_22: sx150x@22 {\n+\t\t\t\tcompatible = \"semtech,sx1508q\";\n+\t\t\t\treg = <0x22>;\n+\t\t\t\tgpio-controller;\n+\t\t\t\t#gpio-cells = <2>;\n+\t\t\t\t#interrupt-cells = <2>;\n+\t\t\t\tinterrupts = <25 2>; /* 1st word overwritten by sx1508-0-22-int-gpio parameter\n+\t\t\t\t                        2nd word is 2 for falling-edge triggered */\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t// Enable a SX1508 on I2C#1 at slave addr 0x22\n+\tfragment@35 {\n+\t\ttarget = <&i2c1>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tsx1508_1_22: sx150x@22 {\n+\t\t\t\tcompatible = \"semtech,sx1508q\";\n+\t\t\t\treg = <0x22>;\n+\t\t\t\tgpio-controller;\n+\t\t\t\t#gpio-cells = <2>;\n+\t\t\t\t#interrupt-cells = <2>;\n+\t\t\t\tinterrupts = <25 2>; /* 1st word overwritten by sx1508-1-22-int-gpio parameter\n+\t\t\t\t                        2nd word is 2 for falling-edge triggered */\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t// Enable a SX1508 on I2C#0 at slave addr 0x23\n+\tfragment@36 {\n+\t\ttarget = <&i2c0>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tsx1508_0_23: sx150x@23 {\n+\t\t\t\tcompatible = \"semtech,sx1508q\";\n+\t\t\t\treg = <0x23>;\n+\t\t\t\tgpio-controller;\n+\t\t\t\t#gpio-cells = <2>;\n+\t\t\t\t#interrupt-cells = <2>;\n+\t\t\t\tinterrupts = <25 2>; /* 1st word overwritten by sx1508-0-23-int-gpio parameter\n+\t\t\t\t                        2nd word is 2 for falling-edge triggered */\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t// Enable a SX1508 on I2C#1 at slave addr 0x23\n+\tfragment@37 {\n+\t\ttarget = <&i2c1>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tsx1508_1_23: sx150x@23 {\n+\t\t\t\tcompatible = \"semtech,sx1508q\";\n+\t\t\t\treg = <0x23>;\n+\t\t\t\tgpio-controller;\n+\t\t\t\t#gpio-cells = <2>;\n+\t\t\t\t#interrupt-cells = <2>;\n+\t\t\t\tinterrupts = <25 2>; /* 1st word overwritten by sx1508-1-23-int-gpio parameter\n+\t\t\t\t                        2nd word is 2 for falling-edge triggered */\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t// Enable a SX1509 on I2C#0 at slave addr 0x3E\n+\tfragment@38 {\n+\t\ttarget = <&i2c0>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tsx1509_0_3E: sx150x@3E {\n+\t\t\t\tcompatible = \"semtech,sx1509q\";\n+\t\t\t\treg = <0x3E>;\n+\t\t\t\tgpio-controller;\n+\t\t\t\t#gpio-cells = <2>;\n+\t\t\t\t#interrupt-cells = <2>;\n+\t\t\t\tinterrupts = <25 2>; /* 1st word overwritten by sx1509_0_3E-int-gpio parameter\n+\t\t\t\t                        2nd word is 2 for falling-edge triggered */\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t// Enable a SX1509 on I2C#1 at slave addr 0x3E\n+\tfragment@39 {\n+\t\ttarget = <&i2c1>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tsx1509_1_3E: sx150x@3E {\n+\t\t\t\tcompatible = \"semtech,sx1509q\";\n+\t\t\t\treg = <0x3E>;\n+\t\t\t\tgpio-controller;\n+\t\t\t\t#gpio-cells = <2>;\n+\t\t\t\t#interrupt-cells = <2>;\n+\t\t\t\tinterrupts = <25 2>; /* 1st word overwritten by sx1509_1_3E-int-gpio parameter\n+\t\t\t\t                        2nd word is 2 for falling-edge triggered */\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t// Enable a SX1509 on I2C#0 at slave addr 0x3F\n+\tfragment@40 {\n+\t\ttarget = <&i2c0>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tsx1509_0_3F: sx150x@3F {\n+\t\t\t\tcompatible = \"semtech,sx1509q\";\n+\t\t\t\treg = <0x3F>;\n+\t\t\t\tgpio-controller;\n+\t\t\t\t#gpio-cells = <2>;\n+\t\t\t\t#interrupt-cells = <2>;\n+\t\t\t\tinterrupts = <25 2>; /* 1st word overwritten by sx1509_0_3F-int-gpio parameter\n+\t\t\t\t                        2nd word is 2 for falling-edge triggered */\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t// Enable a SX1509 on I2C#1 at slave addr 0x3F\n+\tfragment@41 {\n+\t\ttarget = <&i2c1>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tsx1509_1_3F: sx150x@3F {\n+\t\t\t\tcompatible = \"semtech,sx1509q\";\n+\t\t\t\treg = <0x3F>;\n+\t\t\t\tgpio-controller;\n+\t\t\t\t#gpio-cells = <2>;\n+\t\t\t\t#interrupt-cells = <2>;\n+\t\t\t\tinterrupts = <25 2>; /* 1st word overwritten by sx1509_1_3F-int-gpio parameter\n+\t\t\t\t                        2nd word is 2 for falling-edge triggered */\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t// Enable a SX1509 on I2C#0 at slave addr 0x70\n+\tfragment@42 {\n+\t\ttarget = <&i2c0>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tsx1509_0_70: sx150x@70 {\n+\t\t\t\tcompatible = \"semtech,sx1509q\";\n+\t\t\t\treg = <0x70>;\n+\t\t\t\tgpio-controller;\n+\t\t\t\t#gpio-cells = <2>;\n+\t\t\t\t#interrupt-cells = <2>;\n+\t\t\t\tinterrupts = <25 2>; /* 1st word overwritten by sx1509-0-70-int-gpio parameter\n+\t\t\t\t                        2nd word is 2 for falling-edge triggered */\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t// Enable a SX1509 on I2C#1 at slave addr 0x70\n+\tfragment@43 {\n+\t\ttarget = <&i2c1>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tsx1509_1_70: sx150x@70 {\n+\t\t\t\tcompatible = \"semtech,sx1509q\";\n+\t\t\t\treg = <0x70>;\n+\t\t\t\tgpio-controller;\n+\t\t\t\t#gpio-cells = <2>;\n+\t\t\t\t#interrupt-cells = <2>;\n+\t\t\t\tinterrupts = <25 2>; /* 1st word overwritten by sx1509-1-70-int-gpio parameter\n+\t\t\t\t                        2nd word is 2 for falling-edge triggered */\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t// Enable a SX1509 on I2C#0 at slave addr 0x71\n+\tfragment@44 {\n+\t\ttarget = <&i2c0>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tsx1509_0_71: sx150x@71 {\n+\t\t\t\tcompatible = \"semtech,sx1509q\";\n+\t\t\t\treg = <0x71>;\n+\t\t\t\tgpio-controller;\n+\t\t\t\t#gpio-cells = <2>;\n+\t\t\t\t#interrupt-cells = <2>;\n+\t\t\t\tinterrupts = <25 2>; /* 1st word overwritten by sx1509-0-71-int-gpio parameter\n+\t\t\t\t                        2nd word is 2 for falling-edge triggered */\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t// Enable a SX1509 on I2C#1 at slave addr 0x71\n+\tfragment@45 {\n+\t\ttarget = <&i2c1>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tsx1509_1_71: sx150x@71 {\n+\t\t\t\tcompatible = \"semtech,sx1509q\";\n+\t\t\t\treg = <0x71>;\n+\t\t\t\tgpio-controller;\n+\t\t\t\t#gpio-cells = <2>;\n+\t\t\t\t#interrupt-cells = <2>;\n+\t\t\t\tinterrupts = <25 2>; /* 1st word overwritten by sx1509-1-71-int-gpio parameter\n+\t\t\t\t                        2nd word is 2 for falling-edge triggered */\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t// Enable interrupts for a SX1501 on I2C#0 at slave addr 0x20\n+\tfragment@46 {\n+\t\ttarget = <&sx1501_0_20>;\n+\t\t__dormant__ {\n+\t\t\tinterrupt-parent = <&gpio>;\n+\t\t\tinterrupt-controller;\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&sx150x_0_20_pins>;\n+\t\t};\n+\t};\n+\n+\t// Enable interrupts for a SX1501 on I2C#1 at slave addr 0x20\n+\tfragment@47 {\n+\t\ttarget = <&sx1501_1_20>;\n+\t\t__dormant__ {\n+\t\t\tinterrupt-parent = <&gpio>;\n+\t\t\tinterrupt-controller;\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&sx150x_1_20_pins>;\n+\t\t};\n+\t};\n+\n+\t// Enable interrupts for a SX1501 on I2C#0 at slave addr 0x21\n+\tfragment@48 {\n+\t\ttarget = <&sx1501_0_21>;\n+\t\t__dormant__ {\n+\t\t\tinterrupt-parent = <&gpio>;\n+\t\t\tinterrupt-controller;\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&sx150x_0_21_pins>;\n+\t\t};\n+\t};\n+\n+\t// Enable interrupts for a SX1501 on I2C#1 at slave addr 0x21\n+\tfragment@49 {\n+\t\ttarget = <&sx1501_1_21>;\n+\t\t__dormant__ {\n+\t\t\tinterrupt-parent = <&gpio>;\n+\t\t\tinterrupt-controller;\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&sx150x_1_21_pins>;\n+\t\t};\n+\t};\n+\n+\t// Enable interrupts for a SX1502 on I2C#0 at slave addr 0x20\n+\tfragment@50 {\n+\t\ttarget = <&sx1502_0_20>;\n+\t\t__dormant__ {\n+\t\t\tinterrupt-parent = <&gpio>;\n+\t\t\tinterrupt-controller;\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&sx150x_0_20_pins>;\n+\t\t};\n+\t};\n+\n+\t// Enable interrupts for a SX1502 on I2C#1 at slave addr 0x20\n+\tfragment@51 {\n+\t\ttarget = <&sx1502_1_20>;\n+\t\t__dormant__ {\n+\t\t\tinterrupt-parent = <&gpio>;\n+\t\t\tinterrupt-controller;\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&sx150x_1_20_pins>;\n+\t\t};\n+\t};\n+\n+\t// Enable interrupts for a SX1502 on I2C#0 at slave addr 0x21\n+\tfragment@52 {\n+\t\ttarget = <&sx1502_0_21>;\n+\t\t__dormant__ {\n+\t\t\tinterrupt-parent = <&gpio>;\n+\t\t\tinterrupt-controller;\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&sx150x_0_21_pins>;\n+\t\t};\n+\t};\n+\n+\t// Enable interrupts for a SX1502 on I2C#1 at slave addr 0x21\n+\tfragment@53 {\n+\t\ttarget = <&sx1502_1_21>;\n+\t\t__dormant__ {\n+\t\t\tinterrupt-parent = <&gpio>;\n+\t\t\tinterrupt-controller;\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&sx150x_1_21_pins>;\n+\t\t};\n+\t};\n+\n+\t// Enable interrupts for a SX1503 on I2C#0 at slave addr 0x20\n+\tfragment@54 {\n+\t\ttarget = <&sx1503_0_20>;\n+\t\t__dormant__ {\n+\t\t\tinterrupt-parent = <&gpio>;\n+\t\t\tinterrupt-controller;\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&sx150x_0_20_pins>;\n+\t\t};\n+\t};\n+\n+\t// Enable interrupts for a SX1503 on I2C#1 at slave addr 0x20\n+\tfragment@55 {\n+\t\ttarget = <&sx1503_1_20>;\n+\t\t__dormant__ {\n+\t\t\tinterrupt-parent = <&gpio>;\n+\t\t\tinterrupt-controller;\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&sx150x_1_20_pins>;\n+\t\t};\n+\t};\n+\n+\t// Enable interrupts for a SX1504 on I2C#0 at slave addr 0x20\n+\tfragment@56 {\n+\t\ttarget = <&sx1504_0_20>;\n+\t\t__dormant__ {\n+\t\t\tinterrupt-parent = <&gpio>;\n+\t\t\tinterrupt-controller;\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&sx150x_0_20_pins>;\n+\t\t};\n+\t};\n+\n+\t// Enable interrupts for a SX1504 on I2C#1 at slave addr 0x20\n+\tfragment@57 {\n+\t\ttarget = <&sx1504_1_20>;\n+\t\t__dormant__ {\n+\t\t\tinterrupt-parent = <&gpio>;\n+\t\t\tinterrupt-controller;\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&sx150x_1_20_pins>;\n+\t\t};\n+\t};\n+\n+\t// Enable interrupts for a SX1504 on I2C#0 at slave addr 0x21\n+\tfragment@58 {\n+\t\ttarget = <&sx1504_0_21>;\n+\t\t__dormant__ {\n+\t\t\tinterrupt-parent = <&gpio>;\n+\t\t\tinterrupt-controller;\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&sx150x_0_21_pins>;\n+\t\t};\n+\t};\n+\n+\t// Enable interrupts for a SX1504 on I2C#1 at slave addr 0x21\n+\tfragment@59 {\n+\t\ttarget = <&sx1504_1_21>;\n+\t\t__dormant__ {\n+\t\t\tinterrupt-parent = <&gpio>;\n+\t\t\tinterrupt-controller;\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&sx150x_1_21_pins>;\n+\t\t};\n+\t};\n+\n+\t// Enable interrupts for a SX1505 on I2C#0 at slave addr 0x20\n+\tfragment@60 {\n+\t\ttarget = <&sx1505_0_20>;\n+\t\t__dormant__ {\n+\t\t\tinterrupt-parent = <&gpio>;\n+\t\t\tinterrupt-controller;\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&sx150x_0_20_pins>;\n+\t\t};\n+\t};\n+\n+\t// Enable interrupts for a SX1505 on I2C#1 at slave addr 0x20\n+\tfragment@61 {\n+\t\ttarget = <&sx1505_1_20>;\n+\t\t__dormant__ {\n+\t\t\tinterrupt-parent = <&gpio>;\n+\t\t\tinterrupt-controller;\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&sx150x_1_20_pins>;\n+\t\t};\n+\t};\n+\n+\t// Enable interrupts for a SX1505 on I2C#0 at slave addr 0x21\n+\tfragment@62 {\n+\t\ttarget = <&sx1505_0_21>;\n+\t\t__dormant__ {\n+\t\t\tinterrupt-parent = <&gpio>;\n+\t\t\tinterrupt-controller;\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&sx150x_0_21_pins>;\n+\t\t};\n+\t};\n+\n+\t// Enable interrupts for a SX1505 on I2C#1 at slave addr 0x21\n+\tfragment@63 {\n+\t\ttarget = <&sx1505_1_21>;\n+\t\t__dormant__ {\n+\t\t\tinterrupt-parent = <&gpio>;\n+\t\t\tinterrupt-controller;\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&sx150x_1_21_pins>;\n+\t\t};\n+\t};\n+\n+\t// Enable interrupts for a SX1506 on I2C#0 at slave addr 0x20\n+\tfragment@64 {\n+\t\ttarget = <&sx1506_0_20>;\n+\t\t__dormant__ {\n+\t\t\tinterrupt-parent = <&gpio>;\n+\t\t\tinterrupt-controller;\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&sx150x_0_20_pins>;\n+\t\t};\n+\t};\n+\n+\t// Enable interrupts for a SX1506 on I2C#1 at slave addr 0x20\n+\tfragment@65 {\n+\t\ttarget = <&sx1506_1_20>;\n+\t\t__dormant__ {\n+\t\t\tinterrupt-parent = <&gpio>;\n+\t\t\tinterrupt-controller;\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&sx150x_1_20_pins>;\n+\t\t};\n+\t};\n+\n+\t// Enable interrupts for a SX1507 on I2C#0 at slave addr 0x3E\n+\tfragment@66 {\n+\t\ttarget = <&sx1507_0_3E>;\n+\t\t__dormant__ {\n+\t\t\tinterrupt-parent = <&gpio>;\n+\t\t\tinterrupt-controller;\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&sx150x_0_3E_pins>;\n+\t\t};\n+\t};\n+\n+\t// Enable interrupts for a SX1507 on I2C#1 at slave addr 0x3E\n+\tfragment@67 {\n+\t\ttarget = <&sx1507_1_3E>;\n+\t\t__dormant__ {\n+\t\t\tinterrupt-parent = <&gpio>;\n+\t\t\tinterrupt-controller;\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&sx150x_1_3E_pins>;\n+\t\t};\n+\t};\n+\n+\t// Enable interrupts for a SX1507 on I2C#0 at slave addr 0x3F\n+\tfragment@68 {\n+\t\ttarget = <&sx1507_0_3F>;\n+\t\t__dormant__ {\n+\t\t\tinterrupt-parent = <&gpio>;\n+\t\t\tinterrupt-controller;\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&sx150x_0_3F_pins>;\n+\t\t};\n+\t};\n+\n+\t// Enable interrupts for a SX1507 on I2C#1 at slave addr 0x3F\n+\tfragment@69 {\n+\t\ttarget = <&sx1507_1_3F>;\n+\t\t__dormant__ {\n+\t\t\tinterrupt-parent = <&gpio>;\n+\t\t\tinterrupt-controller;\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&sx150x_1_3F_pins>;\n+\t\t};\n+\t};\n+\n+\t// Enable interrupts for a SX1507 on I2C#0 at slave addr 0x70\n+\tfragment@70 {\n+\t\ttarget = <&sx1507_0_70>;\n+\t\t__dormant__ {\n+\t\t\tinterrupt-parent = <&gpio>;\n+\t\t\tinterrupt-controller;\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&sx150x_1_70_pins>;\n+\t\t};\n+\t};\n+\n+\t// Enable interrupts for a SX1507 on I2C#1 at slave addr 0x70\n+\tfragment@71 {\n+\t\ttarget = <&sx1507_1_70>;\n+\t\t__dormant__ {\n+\t\t\tinterrupt-parent = <&gpio>;\n+\t\t\tinterrupt-controller;\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&sx150x_1_70_pins>;\n+\t\t};\n+\t};\n+\n+\t// Enable interrupts for a SX1507 on I2C#0 at slave addr 0x71\n+\tfragment@72 {\n+\t\ttarget = <&sx1507_0_71>;\n+\t\t__dormant__ {\n+\t\t\tinterrupt-parent = <&gpio>;\n+\t\t\tinterrupt-controller;\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&sx150x_0_71_pins>;\n+\t\t};\n+\t};\n+\n+\t// Enable interrupts for a SX1507 on I2C#1 at slave addr 0x71\n+\tfragment@73 {\n+\t\ttarget = <&sx1507_1_71>;\n+\t\t__dormant__ {\n+\t\t\tinterrupt-parent = <&gpio>;\n+\t\t\tinterrupt-controller;\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&sx150x_1_71_pins>;\n+\t\t};\n+\t};\n+\n+\t// Enable interrupts for a SX1508 on I2C#0 at slave addr 0x20\n+\tfragment@74 {\n+\t\ttarget = <&sx1508_0_20>;\n+\t\t__dormant__ {\n+\t\t\tinterrupt-parent = <&gpio>;\n+\t\t\tinterrupt-controller;\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&sx150x_0_20_pins>;\n+\t\t};\n+\t};\n+\n+\t// Enable interrupts for a SX1508 on I2C#1 at slave addr 0x20\n+\tfragment@75 {\n+\t\ttarget = <&sx1508_1_20>;\n+\t\t__dormant__ {\n+\t\t\tinterrupt-parent = <&gpio>;\n+\t\t\tinterrupt-controller;\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&sx150x_1_20_pins>;\n+\t\t};\n+\t};\n+\n+\t// Enable interrupts for a SX1508 on I2C#0 at slave addr 0x21\n+\tfragment@76 {\n+\t\ttarget = <&sx1508_0_21>;\n+\t\t__dormant__ {\n+\t\t\tinterrupt-parent = <&gpio>;\n+\t\t\tinterrupt-controller;\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&sx150x_0_21_pins>;\n+\t\t};\n+\t};\n+\n+\t// Enable interrupts for a SX1508 on I2C#1 at slave addr 0x21\n+\tfragment@77 {\n+\t\ttarget = <&sx1508_1_21>;\n+\t\t__dormant__ {\n+\t\t\tinterrupt-parent = <&gpio>;\n+\t\t\tinterrupt-controller;\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&sx150x_1_21_pins>;\n+\t\t};\n+\t};\n+\n+\t// Enable interrupts for a SX1508 on I2C#0 at slave addr 0x22\n+\tfragment@78 {\n+\t\ttarget = <&sx1508_0_22>;\n+\t\t__dormant__ {\n+\t\t\tinterrupt-parent = <&gpio>;\n+\t\t\tinterrupt-controller;\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&sx150x_0_22_pins>;\n+\t\t};\n+\t};\n+\n+\t// Enable interrupts for a SX1508 on I2C#1 at slave addr 0x22\n+\tfragment@79 {\n+\t\ttarget = <&sx1508_1_22>;\n+\t\t__dormant__ {\n+\t\t\tinterrupt-parent = <&gpio>;\n+\t\t\tinterrupt-controller;\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&sx150x_1_22_pins>;\n+\t\t};\n+\t};\n+\n+\t// Enable interrupts for a SX1508 on I2C#0 at slave addr 0x23\n+\tfragment@80 {\n+\t\ttarget = <&sx1508_0_23>;\n+\t\t__dormant__ {\n+\t\t\tinterrupt-parent = <&gpio>;\n+\t\t\tinterrupt-controller;\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&sx150x_0_23_pins>;\n+\t\t};\n+\t};\n+\n+\t// Enable interrupts for a SX1508 on I2C#1 at slave addr 0x23\n+\tfragment@81 {\n+\t\ttarget = <&sx1508_1_23>;\n+\t\t__dormant__ {\n+\t\t\tinterrupt-parent = <&gpio>;\n+\t\t\tinterrupt-controller;\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&sx150x_1_23_pins>;\n+\t\t};\n+\t};\n+\n+\t// Enable interrupts for a SX1509 on I2C#0 at slave addr 0x3E\n+\tfragment@82 {\n+\t\ttarget = <&sx1509_0_3E>;\n+\t\t__dormant__ {\n+\t\t\tinterrupt-parent = <&gpio>;\n+\t\t\tinterrupt-controller;\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&sx150x_0_3E_pins>;\n+\t\t};\n+\t};\n+\n+\t// Enable interrupts for a SX1509 on I2C#1 at slave addr 0x3E\n+\tfragment@83 {\n+\t\ttarget = <&sx1509_1_3E>;\n+\t\t__dormant__ {\n+\t\t\tinterrupt-parent = <&gpio>;\n+\t\t\tinterrupt-controller;\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&sx150x_1_3E_pins>;\n+\t\t};\n+\t};\n+\n+\t// Enable interrupts for a SX1509 on I2C#0 at slave addr 0x3F\n+\tfragment@84 {\n+\t\ttarget = <&sx1509_0_3F>;\n+\t\t__dormant__ {\n+\t\t\tinterrupt-parent = <&gpio>;\n+\t\t\tinterrupt-controller;\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&sx150x_0_3F_pins>;\n+\t\t};\n+\t};\n+\n+\t// Enable interrupts for a SX1509 on I2C#1 at slave addr 0x3F\n+\tfragment@85 {\n+\t\ttarget = <&sx1509_1_3F>;\n+\t\t__dormant__ {\n+\t\t\tinterrupt-parent = <&gpio>;\n+\t\t\tinterrupt-controller;\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&sx150x_1_3F_pins>;\n+\t\t};\n+\t};\n+\n+\t// Enable interrupts for a SX1509 on I2C#0 at slave addr 0x70\n+\tfragment@86 {\n+\t\ttarget = <&sx1509_0_70>;\n+\t\t__dormant__ {\n+\t\t\tinterrupt-parent = <&gpio>;\n+\t\t\tinterrupt-controller;\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&sx150x_0_70_pins>;\n+\t\t};\n+\t};\n+\n+\t// Enable interrupts for a SX1509 on I2C#1 at slave addr 0x70\n+\tfragment@87 {\n+\t\ttarget = <&sx1509_1_70>;\n+\t\t__dormant__ {\n+\t\t\tinterrupt-parent = <&gpio>;\n+\t\t\tinterrupt-controller;\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&sx150x_1_70_pins>;\n+\t\t};\n+\t};\n+\n+\t// Enable interrupts for a SX1509 on I2C#0 at slave addr 0x71\n+\tfragment@88 {\n+\t\ttarget = <&sx1509_0_71>;\n+\t\t__dormant__ {\n+\t\t\tinterrupt-parent = <&gpio>;\n+\t\t\tinterrupt-controller;\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&sx150x_0_71_pins>;\n+\t\t};\n+\t};\n+\n+\t// Enable interrupts for a SX1509 on I2C#1 at slave addr 0x71\n+\tfragment@89 {\n+\t\ttarget = <&sx1509_1_71>;\n+\t\t__dormant__ {\n+\t\t\tinterrupt-parent = <&gpio>;\n+\t\t\tinterrupt-controller;\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&sx150x_1_71_pins>;\n+\t\t};\n+\t};\n+\n+\t// Configure GPIO pin connected to NINT output of a SX150x on I2C#0 interface at slave addr 0x20\n+        // Configure as a input with no pull-up/down\n+\tfragment@90 {\n+\t\ttarget = <&gpio>;\n+\t\t__dormant__ {\n+\t\t\tsx150x_0_20_pins: sx150x_0_20_pins {\n+\t\t\t\tbrcm,pins = <0>;  /* overwritten by sx150x-0-20-int-gpio parameter */\n+\t\t\t\tbrcm,function = <0>;\n+\t\t\t\tbrcm,pull = <0>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t// Configure GPIO pin connected to NINT output of a SX150x on I2C#1 interface at slave addr 0x20\n+        // Configure as a input with no pull-up/down\n+\tfragment@91 {\n+\t\ttarget = <&gpio>;\n+\t\t__dormant__ {\n+\t\t\tsx150x_1_20_pins: sx150x_1_20_pins {\n+\t\t\t\tbrcm,pins = <0>;  /* overwritten by sx150x-1-20-int-gpio parameter */\n+\t\t\t\tbrcm,function = <0>;\n+\t\t\t\tbrcm,pull = <0>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t// Configure GPIO pin connected to NINT output of a SX150x on I2C#0 interface at slave addr 0x21\n+        // Configure as a input with no pull-up/down\n+\tfragment@92 {\n+\t\ttarget = <&gpio>;\n+\t\t__dormant__ {\n+\t\t\tsx150x_0_21_pins: sx150x_0_21_pins {\n+\t\t\t\tbrcm,pins = <0>;  /* overwritten by sx150x-0-21-int-gpio parameter */\n+\t\t\t\tbrcm,function = <0>;\n+\t\t\t\tbrcm,pull = <0>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t// Configure GPIO pin connected to NINT output of a SX150x on I2C#1 interface at slave addr 0x21\n+        // Configure as a input with no pull-up/down\n+\tfragment@93 {\n+\t\ttarget = <&gpio>;\n+\t\t__dormant__ {\n+\t\t\tsx150x_1_21_pins: sx150x_1_21_pins {\n+\t\t\t\tbrcm,pins = <0>;  /* overwritten by sx150x-1-21-int-gpio parameter */\n+\t\t\t\tbrcm,function = <0>;\n+\t\t\t\tbrcm,pull = <0>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t// Configure GPIO pin connected to NINT output of a SX150x on I2C#0 interface at slave addr 0x22\n+        // Configure as a input with no pull-up/down\n+\tfragment@94 {\n+\t\ttarget = <&gpio>;\n+\t\t__dormant__ {\n+\t\t\tsx150x_0_22_pins: sx150x_0_22_pins {\n+\t\t\t\tbrcm,pins = <0>;  /* overwritten by sx150x-0-22-int-gpio parameter */\n+\t\t\t\tbrcm,function = <0>;\n+\t\t\t\tbrcm,pull = <0>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t// Configure GPIO pin connected to NINT output of a SX150x on I2C#1 interface at slave addr 0x22\n+        // Configure as a input with no pull-up/down\n+\tfragment@95 {\n+\t\ttarget = <&gpio>;\n+\t\t__dormant__ {\n+\t\t\tsx150x_1_22_pins: sx150x_1_22_pins {\n+\t\t\t\tbrcm,pins = <0>;  /* overwritten by sx150x-1-22-int-gpio parameter */\n+\t\t\t\tbrcm,function = <0>;\n+\t\t\t\tbrcm,pull = <0>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t// Configure GPIO pin connected to NINT output of a SX150x on I2C#0 interface at slave addr 0x23\n+        // Configure as a input with no pull-up/down\n+\tfragment@96 {\n+\t\ttarget = <&gpio>;\n+\t\t__dormant__ {\n+\t\t\tsx150x_0_23_pins: sx150x_0_23_pins {\n+\t\t\t\tbrcm,pins = <0>;  /* overwritten by sx150x-0-23-int-gpio parameter */\n+\t\t\t\tbrcm,function = <0>;\n+\t\t\t\tbrcm,pull = <0>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t// Configure GPIO pin connected to NINT output of a SX150x on I2C#1 interface at slave addr 0x23\n+        // Configure as a input with no pull-up/down\n+\tfragment@97 {\n+\t\ttarget = <&gpio>;\n+\t\t__dormant__ {\n+\t\t\tsx150x_1_23_pins: sx150x_1_23_pins {\n+\t\t\t\tbrcm,pins = <0>;  /* overwritten by sx150x-1-23-int-gpio parameter */\n+\t\t\t\tbrcm,function = <0>;\n+\t\t\t\tbrcm,pull = <0>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t// Configure GPIO pin connected to NINT output of a SX150x on I2C#0 interface at slave addr 0x3E\n+        // Configure as a input with no pull-up/down\n+\tfragment@98 {\n+\t\ttarget = <&gpio>;\n+\t\t__dormant__ {\n+\t\t\tsx150x_0_3E_pins: sx150x_0_3E_pins {\n+\t\t\t\tbrcm,pins = <0>;  /* overwritten by sx150x-0-3E-int-gpio parameter */\n+\t\t\t\tbrcm,function = <0>;\n+\t\t\t\tbrcm,pull = <0>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t// Configure GPIO pin connected to NINT output of a SX150x on I2C#1 interface at slave addr 0x3E\n+        // Configure as a input with no pull-up/down\n+\tfragment@99 {\n+\t\ttarget = <&gpio>;\n+\t\t__dormant__ {\n+\t\t\tsx150x_1_3E_pins: sx150x_1_3E_pins {\n+\t\t\t\tbrcm,pins = <0>;  /* overwritten by sx150x-1-3E-int-gpio parameter */\n+\t\t\t\tbrcm,function = <0>;\n+\t\t\t\tbrcm,pull = <0>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t// Configure GPIO pin connected to NINT output of a SX150x on I2C#0 interface at slave addr 0x3F\n+        // Configure as a input with no pull-up/down\n+\tfragment@100 {\n+\t\ttarget = <&gpio>;\n+\t\t__dormant__ {\n+\t\t\tsx150x_0_3F_pins: sx150x_0_3F_pins {\n+\t\t\t\tbrcm,pins = <0>;  /* overwritten by sx150x-0-3F-int-gpio parameter */\n+\t\t\t\tbrcm,function = <0>;\n+\t\t\t\tbrcm,pull = <0>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t// Configure GPIO pin connected to NINT output of a SX150x on I2C#1 interface at slave addr 0x3F\n+        // Configure as a input with no pull-up/down\n+\tfragment@101 {\n+\t\ttarget = <&gpio>;\n+\t\t__dormant__ {\n+\t\t\tsx150x_1_3F_pins: sx150x_1_3F_pins {\n+\t\t\t\tbrcm,pins = <0>;  /* overwritten by sx150x-1-3F-int-gpio parameter */\n+\t\t\t\tbrcm,function = <0>;\n+\t\t\t\tbrcm,pull = <0>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t// Configure GPIO pin connected to NINT output of a SX150x on I2C#0 interface at slave addr 0x70\n+        // Configure as a input with no pull-up/down\n+\tfragment@102 {\n+\t\ttarget = <&gpio>;\n+\t\t__dormant__ {\n+\t\t\tsx150x_0_70_pins: sx150x_0_70_pins {\n+\t\t\t\tbrcm,pins = <0>;  /* overwritten by sx150x-0-70-int-gpio parameter */\n+\t\t\t\tbrcm,function = <0>;\n+\t\t\t\tbrcm,pull = <0>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t// Configure GPIO pin connected to NINT output of a SX150x on I2C#1 interface at slave addr 0x70\n+        // Configure as a input with no pull-up/down\n+\tfragment@103 {\n+\t\ttarget = <&gpio>;\n+\t\t__dormant__ {\n+\t\t\tsx150x_1_70_pins: sx150x_1_70_pins {\n+\t\t\t\tbrcm,pins = <0>;  /* overwritten by sx150x-1-70-int-gpio parameter */\n+\t\t\t\tbrcm,function = <0>;\n+\t\t\t\tbrcm,pull = <0>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t// Configure GPIO pin connected to NINT output of a SX150x on I2C#0 interface at slave addr 0x71\n+        // Configure as a input with no pull-up/down\n+\tfragment@104 {\n+\t\ttarget = <&gpio>;\n+\t\t__dormant__ {\n+\t\t\tsx150x_0_71_pins: sx150x_0_71_pins {\n+\t\t\t\tbrcm,pins = <0>;  /* overwritten by sx150x-0-71-int-gpio parameter */\n+\t\t\t\tbrcm,function = <0>;\n+\t\t\t\tbrcm,pull = <0>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t// Configure GPIO pin connected to NINT output of a SX150x on I2C#1 interface at slave addr 0x71\n+        // Configure as a input with no pull-up/down\n+\tfragment@105 {\n+\t\ttarget = <&gpio>;\n+\t\t__dormant__ {\n+\t\t\tsx150x_1_71_pins: sx150x_1_71_pins {\n+\t\t\t\tbrcm,pins = <0>;  /* overwritten by sx150x-1-71-int-gpio parameter */\n+\t\t\t\tbrcm,function = <0>;\n+\t\t\t\tbrcm,pull = <0>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\tsx1501-0-20          = <0>,\"+0+2\";\n+\t\tsx1501-1-20          = <0>,\"+1+3\";\n+\t\tsx1501-0-21          = <0>,\"+0+4\";\n+\t\tsx1501-1-21          = <0>,\"+1+5\";\n+\t\tsx1502-0-20          = <0>,\"+0+6\";\n+\t\tsx1502-1-20          = <0>,\"+1+7\";\n+\t\tsx1502-0-21          = <0>,\"+0+8\";\n+\t\tsx1502-1-21          = <0>,\"+1+9\";\n+\t\tsx1503-0-20          = <0>,\"+0+10\";\n+\t\tsx1503-1-20          = <0>,\"+1+11\";\n+\t\tsx1504-0-20          = <0>,\"+0+12\";\n+\t\tsx1504-1-20          = <0>,\"+1+13\";\n+\t\tsx1504-0-21          = <0>,\"+0+14\";\n+\t\tsx1504-1-21          = <0>,\"+1+15\";\n+\t\tsx1505-0-20          = <0>,\"+0+16\";\n+\t\tsx1505-1-20          = <0>,\"+1+17\";\n+\t\tsx1505-0-21          = <0>,\"+0+18\";\n+\t\tsx1505-1-21          = <0>,\"+1+19\";\n+\t\tsx1506-0-20          = <0>,\"+0+20\";\n+\t\tsx1506-1-20          = <0>,\"+1+21\";\n+\t\tsx1507-0-3E          = <0>,\"+0+22\";\n+\t\tsx1507-1-3E          = <0>,\"+1+23\";\n+\t\tsx1507-0-3F          = <0>,\"+0+24\";\n+\t\tsx1507-1-3F          = <0>,\"+1+25\";\n+\t\tsx1507-0-70          = <0>,\"+0+26\";\n+\t\tsx1507-1-70          = <0>,\"+1+27\";\n+\t\tsx1507-0-71          = <0>,\"+0+28\";\n+\t\tsx1507-1-71          = <0>,\"+1+29\";\n+\t\tsx1508-0-20          = <0>,\"+0+30\";\n+\t\tsx1508-1-20          = <0>,\"+1+31\";\n+\t\tsx1508-0-21          = <0>,\"+0+32\";\n+\t\tsx1508-1-21          = <0>,\"+1+33\";\n+\t\tsx1508-0-22          = <0>,\"+0+34\";\n+\t\tsx1508-1-22          = <0>,\"+1+35\";\n+\t\tsx1508-0-23          = <0>,\"+0+36\";\n+\t\tsx1508-1-23          = <0>,\"+1+37\";\n+\t\tsx1509-0-3E          = <0>,\"+0+38\";\n+\t\tsx1509-1-3E          = <0>,\"+1+39\";\n+\t\tsx1509-0-3F          = <0>,\"+0+40\";\n+\t\tsx1509-1-3F          = <0>,\"+1+41\";\n+\t\tsx1509-0-70          = <0>,\"+0+42\";\n+\t\tsx1509-1-70          = <0>,\"+1+43\";\n+\t\tsx1509-0-71          = <0>,\"+0+44\";\n+\t\tsx1509-1-71          = <0>,\"+1+45\";\n+\t\tsx1501-0-20-int-gpio = <0>,\"+46+90\",  <&sx150x_0_20_pins>,\"brcm,pins:0\", <&sx1501_0_20>,\"interrupts:0\";\n+\t\tsx1501-1-20-int-gpio = <0>,\"+47+91\",  <&sx150x_1_20_pins>,\"brcm,pins:0\", <&sx1501_1_20>,\"interrupts:0\";\n+\t\tsx1501-0-21-int-gpio = <0>,\"+48+92\",  <&sx150x_0_21_pins>,\"brcm,pins:0\", <&sx1501_0_21>,\"interrupts:0\";\n+\t\tsx1501-1-21-int-gpio = <0>,\"+49+93\",  <&sx150x_1_21_pins>,\"brcm,pins:0\", <&sx1501_1_21>,\"interrupts:0\";\n+\t\tsx1502-0-20-int-gpio = <0>,\"+50+90\",  <&sx150x_0_20_pins>,\"brcm,pins:0\", <&sx1502_0_20>,\"interrupts:0\";\n+\t\tsx1502-1-20-int-gpio = <0>,\"+51+91\",  <&sx150x_1_20_pins>,\"brcm,pins:0\", <&sx1502_1_20>,\"interrupts:0\";\n+\t\tsx1502-0-21-int-gpio = <0>,\"+52+92\",  <&sx150x_0_21_pins>,\"brcm,pins:0\", <&sx1502_0_21>,\"interrupts:0\";\n+\t\tsx1502-1-21-int-gpio = <0>,\"+53+93\",  <&sx150x_1_21_pins>,\"brcm,pins:0\", <&sx1502_1_21>,\"interrupts:0\";\n+\t\tsx1503-0-20-int-gpio = <0>,\"+54+90\",  <&sx150x_0_20_pins>,\"brcm,pins:0\", <&sx1503_0_20>,\"interrupts:0\";\n+\t\tsx1503-1-20-int-gpio = <0>,\"+55+91\",  <&sx150x_1_20_pins>,\"brcm,pins:0\", <&sx1503_1_20>,\"interrupts:0\";\n+\t\tsx1504-0-20-int-gpio = <0>,\"+56+90\",  <&sx150x_0_20_pins>,\"brcm,pins:0\", <&sx1504_0_20>,\"interrupts:0\";\n+\t\tsx1504-1-20-int-gpio = <0>,\"+57+91\",  <&sx150x_1_20_pins>,\"brcm,pins:0\", <&sx1504_1_20>,\"interrupts:0\";\n+\t\tsx1504-0-21-int-gpio = <0>,\"+58+92\",  <&sx150x_0_21_pins>,\"brcm,pins:0\", <&sx1504_0_21>,\"interrupts:0\";\n+\t\tsx1504-1-21-int-gpio = <0>,\"+59+93\",  <&sx150x_1_21_pins>,\"brcm,pins:0\", <&sx1504_1_21>,\"interrupts:0\";\n+\t\tsx1505-0-20-int-gpio = <0>,\"+60+90\",  <&sx150x_0_20_pins>,\"brcm,pins:0\", <&sx1505_0_20>,\"interrupts:0\";\n+\t\tsx1505-1-20-int-gpio = <0>,\"+61+91\",  <&sx150x_1_20_pins>,\"brcm,pins:0\", <&sx1505_1_20>,\"interrupts:0\";\n+\t\tsx1505-0-21-int-gpio = <0>,\"+62+92\",  <&sx150x_0_21_pins>,\"brcm,pins:0\", <&sx1505_0_21>,\"interrupts:0\";\n+\t\tsx1505-1-21-int-gpio = <0>,\"+63+93\",  <&sx150x_1_21_pins>,\"brcm,pins:0\", <&sx1505_1_21>,\"interrupts:0\";\n+\t\tsx1506-0-20-int-gpio = <0>,\"+64+90\",  <&sx150x_0_20_pins>,\"brcm,pins:0\", <&sx1506_0_20>,\"interrupts:0\";\n+\t\tsx1506-1-20-int-gpio = <0>,\"+65+91\",  <&sx150x_1_20_pins>,\"brcm,pins:0\", <&sx1506_1_20>,\"interrupts:0\";\n+\t\tsx1507-0-3E-int-gpio = <0>,\"+66+98\",  <&sx150x_0_3E_pins>,\"brcm,pins:0\", <&sx1507_0_3E>,\"interrupts:0\";\n+\t\tsx1507-1-3E-int-gpio = <0>,\"+67+99\",  <&sx150x_1_3E_pins>,\"brcm,pins:0\", <&sx1507_1_3E>,\"interrupts:0\";\n+\t\tsx1507-0-3F-int-gpio = <0>,\"+68+100\", <&sx150x_0_3F_pins>,\"brcm,pins:0\", <&sx1507_0_3F>,\"interrupts:0\";\n+\t\tsx1507-1-3F-int-gpio = <0>,\"+69+101\", <&sx150x_1_3F_pins>,\"brcm,pins:0\", <&sx1507_1_3F>,\"interrupts:0\";\n+\t\tsx1507-0-70-int-gpio = <0>,\"+60+102\", <&sx150x_0_70_pins>,\"brcm,pins:0\", <&sx1507_0_70>,\"interrupts:0\";\n+\t\tsx1507-1-70-int-gpio = <0>,\"+71+103\", <&sx150x_1_70_pins>,\"brcm,pins:0\", <&sx1507_1_70>,\"interrupts:0\";\n+\t\tsx1507-0-71-int-gpio = <0>,\"+72+104\", <&sx150x_0_71_pins>,\"brcm,pins:0\", <&sx1507_0_71>,\"interrupts:0\";\n+\t\tsx1507-1-71-int-gpio = <0>,\"+73+105\", <&sx150x_1_71_pins>,\"brcm,pins:0\", <&sx1507_1_71>,\"interrupts:0\";\n+\t\tsx1508-0-20-int-gpio = <0>,\"+74+90\",  <&sx150x_0_20_pins>,\"brcm,pins:0\", <&sx1508_0_20>,\"interrupts:0\";\n+\t\tsx1508-1-20-int-gpio = <0>,\"+75+91\",  <&sx150x_1_20_pins>,\"brcm,pins:0\", <&sx1508_1_20>,\"interrupts:0\";\n+\t\tsx1508-0-21-int-gpio = <0>,\"+76+92\",  <&sx150x_0_21_pins>,\"brcm,pins:0\", <&sx1508_0_21>,\"interrupts:0\";\n+\t\tsx1508-1-21-int-gpio = <0>,\"+77+93\",  <&sx150x_1_21_pins>,\"brcm,pins:0\", <&sx1508_1_21>,\"interrupts:0\";\n+\t\tsx1508-0-22-int-gpio = <0>,\"+78+94\",  <&sx150x_0_22_pins>,\"brcm,pins:0\", <&sx1508_0_22>,\"interrupts:0\";\n+\t\tsx1508-1-22-int-gpio = <0>,\"+79+95\",  <&sx150x_1_22_pins>,\"brcm,pins:0\", <&sx1508_1_22>,\"interrupts:0\";\n+\t\tsx1508-0-23-int-gpio = <0>,\"+80+96\",  <&sx150x_0_23_pins>,\"brcm,pins:0\", <&sx1508_0_23>,\"interrupts:0\";\n+\t\tsx1508-1-23-int-gpio = <0>,\"+81+97\",  <&sx150x_1_23_pins>,\"brcm,pins:0\", <&sx1508_1_23>,\"interrupts:0\";\n+\t\tsx1509-0-3E-int-gpio = <0>,\"+82+98\",  <&sx150x_0_3E_pins>,\"brcm,pins:0\", <&sx1509_0_3E>,\"interrupts:0\";\n+\t\tsx1509-1-3E-int-gpio = <0>,\"+83+99\",  <&sx150x_1_3E_pins>,\"brcm,pins:0\", <&sx1509_1_3E>,\"interrupts:0\";\n+\t\tsx1509-0-3F-int-gpio = <0>,\"+84+100\", <&sx150x_0_3F_pins>,\"brcm,pins:0\", <&sx1509_0_3F>,\"interrupts:0\";\n+\t\tsx1509-1-3F-int-gpio = <0>,\"+85+101\", <&sx150x_1_3F_pins>,\"brcm,pins:0\", <&sx1509_1_3F>,\"interrupts:0\";\n+\t\tsx1509-0-70-int-gpio = <0>,\"+86+102\", <&sx150x_0_70_pins>,\"brcm,pins:0\", <&sx1509_0_70>,\"interrupts:0\";\n+\t\tsx1509-1-70-int-gpio = <0>,\"+87+103\", <&sx150x_1_70_pins>,\"brcm,pins:0\", <&sx1509_1_70>,\"interrupts:0\";\n+\t\tsx1509-0-71-int-gpio = <0>,\"+88+104\", <&sx150x_0_71_pins>,\"brcm,pins:0\", <&sx1509_0_71>,\"interrupts:0\";\n+\t\tsx1509-1-71-int-gpio = <0>,\"+89+105\", <&sx150x_1_71_pins>,\"brcm,pins:0\", <&sx1509_1_71>,\"interrupts:0\";\n+\t};\n+};\n+\ndiff --git a/arch/arm/boot/dts/overlays/tc358743-audio-overlay.dts b/arch/arm/boot/dts/overlays/tc358743-audio-overlay.dts\nnew file mode 100644\nindex 000000000000..047695bb0c71\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/tc358743-audio-overlay.dts\n@@ -0,0 +1,52 @@\n+// SPDX-License-Identifier: GPL-2.0-only\n+// Definitions to add I2S audio from the Toshiba TC358743 HDMI to CSI2 bridge.\n+// Requires tc358743 overlay to have been loaded to actually function.\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&i2s>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget-path = \"/\";\n+\t\t__overlay__ {\n+\t\t\ttc358743_codec: tc358743-codec {\n+\t\t\t\t#sound-dai-cells = <0>;\n+\t\t\t\tcompatible = \"linux,spdif-dir\";\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&sound>;\n+\t\tsound_overlay: __overlay__ {\n+\t\t\tcompatible = \"simple-audio-card\";\n+\t\t\tsimple-audio-card,format = \"i2s\";\n+\t\t\tsimple-audio-card,name = \"tc358743\";\n+\t\t\tsimple-audio-card,bitclock-master = <&dailink0_slave>;\n+\t\t\tsimple-audio-card,frame-master = <&dailink0_slave>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tsimple-audio-card,cpu {\n+\t\t\t\tsound-dai = <&i2s>;\n+\t\t\t\tdai-tdm-slot-num = <2>;\n+\t\t\t\tdai-tdm-slot-width = <32>;\n+\t\t\t};\n+\t\t\tdailink0_slave: simple-audio-card,codec {\n+\t\t\t\tsound-dai = <&tc358743_codec>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\tcard-name = <&sound_overlay>,\"simple-audio-card,name\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/tc358743-overlay.dts b/arch/arm/boot/dts/overlays/tc358743-overlay.dts\nnew file mode 100644\nindex 000000000000..a1f8af36d2e7\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/tc358743-overlay.dts\n@@ -0,0 +1,107 @@\n+// SPDX-License-Identifier: GPL-2.0-only\n+// Definitions for Toshiba TC358743 HDMI to CSI2 bridge on VC I2C bus\n+/dts-v1/;\n+/plugin/;\n+\n+/{\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&i2c_csi_dsi>;\n+\t\t__overlay__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\ttc358743@0f {\n+\t\t\t\tcompatible = \"toshiba,tc358743\";\n+\t\t\t\treg = <0x0f>;\n+\t\t\t\tstatus = \"okay\";\n+\n+\t\t\t\tclocks = <&tc358743_clk>;\n+\t\t\t\tclock-names = \"refclk\";\n+\n+\t\t\t\tport {\n+\t\t\t\t\ttc358743: endpoint {\n+\t\t\t\t\t\tremote-endpoint = <&csi1_ep>;\n+\t\t\t\t\t\tclock-lanes = <0>;\n+\t\t\t\t\t\tclock-noncontinuous;\n+\t\t\t\t\t\tlink-frequencies =\n+\t\t\t\t\t\t\t/bits/ 64 <486000000>;\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&csi1>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tport {\n+\t\t\t\tcsi1_ep: endpoint {\n+\t\t\t\t\tremote-endpoint = <&tc358743>;\n+\t\t\t\t};\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&tc358743>;\n+\t\t__overlay__ {\n+\t\t\tdata-lanes = <1 2>;\n+\t\t};\n+\t};\n+\n+\tfragment@3 {\n+\t\ttarget = <&tc358743>;\n+\t\t__dormant__ {\n+\t\t\tdata-lanes = <1 2 3 4>;\n+\t\t};\n+\t};\n+\n+\tfragment@4 {\n+\t\ttarget = <&i2c0if>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@5 {\n+\t\ttarget = <&i2c0mux>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@6 {\n+\t\ttarget-path = \"/\";\n+\t\t__overlay__ {\n+\t\t\ttc358743_clk: bridge-clk {\n+\t\t\t\tcompatible = \"fixed-clock\";\n+\t\t\t\t#clock-cells = <0>;\n+\t\t\t\tclock-frequency = <27000000>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@7 {\n+\t\ttarget = <&csi1_ep>;\n+\t\t__overlay__ {\n+\t\t\tdata-lanes = <1 2>;\n+\t\t};\n+\t};\n+\n+\tfragment@8 {\n+\t\ttarget = <&csi1_ep>;\n+\t\t__dormant__ {\n+\t\t\tdata-lanes = <1 2 3 4>;\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\t4lane = <0>, \"-2+3-7+8\";\n+\t\tlink-frequency = <&tc358743>,\"link-frequencies#0\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/tinylcd35-overlay.dts b/arch/arm/boot/dts/overlays/tinylcd35-overlay.dts\nnew file mode 100644\nindex 000000000000..a102b09e3ab5\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/tinylcd35-overlay.dts\n@@ -0,0 +1,222 @@\n+/*\n+ * tinylcd35-overlay.dts\n+ *\n+ * -------------------------------------------------\n+ * www.tinlylcd.com\n+ * -------------------------------------------------\n+ * Device---Driver-----BUS       GPIO's\n+ * display  tinylcd35  spi0.0    25 24 18\n+ * touch    ads7846    spi0.1    5\n+ * rtc      ds1307     i2c1-0068\n+ * rtc      pcf8563    i2c1-0051\n+ * keypad   gpio-keys  --------- 17 22 27 23 28\n+ *\n+ *\n+ * TinyLCD.com 3.5 inch TFT\n+ *\n+ *  Version 001\n+ *  5/3/2015  -- Noralf Trønnes     Initial Device tree framework\n+ *  10/3/2015 -- tinylcd@gmail.com  added ds1307 support.\n+ *\n+ */\n+\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&spi0>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&spidev0>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&spidev1>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\tfragment@3 {\n+\t\ttarget = <&gpio>;\n+\t\t__overlay__ {\n+\t\t\ttinylcd35_pins: tinylcd35_pins {\n+\t\t\t\tbrcm,pins = <25 24 18>;\n+\t\t\t\tbrcm,function = <1>; /* out */\n+\t\t\t};\n+\t\t\ttinylcd35_ts_pins: tinylcd35_ts_pins {\n+\t\t\t\tbrcm,pins = <5>;\n+\t\t\t\tbrcm,function = <0>; /* in */\n+\t\t\t};\n+\t\t\tkeypad_pins: keypad_pins {\n+\t\t\t\tbrcm,pins = <4 17 22 23 27>;\n+\t\t\t\tbrcm,function = <0>; /* in */\n+\t\t\t\tbrcm,pull = <1>; /* down */\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@4 {\n+\t\ttarget = <&spi0>;\n+\t\t__overlay__ {\n+\t\t\t/* needed to avoid dtc warning */\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\ttinylcd35: tinylcd35@0{\n+\t\t\t\tcompatible = \"neosec,tinylcd\";\n+\t\t\t\treg = <0>;\n+\t\t\t\tpinctrl-names = \"default\";\n+\t\t\t\tpinctrl-0 = <&tinylcd35_pins>,\n+\t\t\t\t\t    <&tinylcd35_ts_pins>;\n+\n+\t\t\t\tspi-max-frequency = <48000000>;\n+\t\t\t\trotate = <270>;\n+\t\t\t\tfps = <20>;\n+\t\t\t\tbgr;\n+\t\t\t\tbuswidth = <8>;\n+\t\t\t\treset-gpios = <&gpio 25 1>;\n+\t\t\t\tdc-gpios = <&gpio 24 0>;\n+\t\t\t\tled-gpios = <&gpio 18 0>;\n+\t\t\t\tdebug = <0>;\n+\n+\t\t\t\tinit = <0x10000B0 0x80\n+\t\t\t\t\t0x10000C0 0x0A 0x0A\n+\t\t\t\t\t0x10000C1 0x01 0x01\n+\t\t\t\t\t0x10000C2 0x33\n+\t\t\t\t\t0x10000C5 0x00 0x42 0x80\n+\t\t\t\t\t0x10000B1 0xD0 0x11\n+\t\t\t\t\t0x10000B4 0x02\n+\t\t\t\t\t0x10000B6 0x00 0x22 0x3B\n+\t\t\t\t\t0x10000B7 0x07\n+\t\t\t\t\t0x1000036 0x58\n+\t\t\t\t\t0x10000F0 0x36 0xA5 0xD3\n+\t\t\t\t\t0x10000E5 0x80\n+\t\t\t\t\t0x10000E5 0x01\n+\t\t\t\t\t0x10000B3 0x00\n+\t\t\t\t\t0x10000E5 0x00\n+\t\t\t\t\t0x10000F0 0x36 0xA5 0x53\n+\t\t\t\t\t0x10000E0 0x00 0x35 0x33 0x00 0x00 0x00 0x00 0x35 0x33 0x00 0x00 0x00\n+\t\t\t\t\t0x100003A 0x55\n+\t\t\t\t\t0x1000011\n+\t\t\t\t\t0x2000001\n+\t\t\t\t\t0x1000029>;\n+\t\t\t};\n+\n+\t\t\ttinylcd35_ts: tinylcd35_ts@1 {\n+\t\t\t\tcompatible = \"ti,ads7846\";\n+\t\t\t\treg = <1>;\n+\t\t\t\tstatus = \"disabled\";\n+\n+\t\t\t\tspi-max-frequency = <2000000>;\n+\t\t\t\tinterrupts = <5 2>; /* high-to-low edge triggered */\n+\t\t\t\tinterrupt-parent = <&gpio>;\n+\t\t\t\tpendown-gpio = <&gpio 5 0>;\n+\t\t\t\tti,x-plate-ohms = /bits/ 16 <100>;\n+\t\t\t\tti,pressure-max = /bits/ 16 <255>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t/*  RTC    */\n+\n+\tfragment@5 {\n+\t\ttarget = <&i2c1>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tpcf8563: pcf8563@51 {\n+\t\t\t\tcompatible = \"nxp,pcf8563\";\n+\t\t\t\treg = <0x51>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@6 {\n+\t\ttarget = <&i2c1>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tds1307: ds1307@68 {\n+\t\t\t\tcompatible = \"dallas,ds1307\";\n+\t\t\t\treg = <0x68>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t/*\n+\t * Values for input event code is found under the\n+\t * 'Keys and buttons' heading in include/uapi/linux/input.h\n+\t */\n+\tfragment@7 {\n+\t\ttarget-path = \"/soc\";\n+\t\t__overlay__ {\n+\t\t\tkeypad: keypad {\n+\t\t\t\tcompatible = \"gpio-keys\";\n+\t\t\t\tpinctrl-names = \"default\";\n+\t\t\t\tpinctrl-0 = <&keypad_pins>;\n+\t\t\t\tstatus = \"disabled\";\n+\t\t\t\tautorepeat;\n+\n+\t\t\t\tbutton@17 {\n+\t\t\t\t\tlabel = \"GPIO KEY_UP\";\n+\t\t\t\t\tlinux,code = <103>;\n+\t\t\t\t\tgpios = <&gpio 17 0>;\n+\t\t\t\t};\n+\t\t\t\tbutton@22 {\n+\t\t\t\t\tlabel = \"GPIO KEY_DOWN\";\n+\t\t\t\t\tlinux,code = <108>;\n+\t\t\t\t\tgpios = <&gpio 22 0>;\n+\t\t\t\t};\n+\t\t\t\tbutton@27 {\n+\t\t\t\t\tlabel = \"GPIO KEY_LEFT\";\n+\t\t\t\t\tlinux,code = <105>;\n+\t\t\t\t\tgpios = <&gpio 27 0>;\n+\t\t\t\t};\n+\t\t\t\tbutton@23 {\n+\t\t\t\t\tlabel = \"GPIO KEY_RIGHT\";\n+\t\t\t\t\tlinux,code = <106>;\n+\t\t\t\t\tgpios = <&gpio 23 0>;\n+\t\t\t\t};\n+\t\t\t\tbutton@4 {\n+\t\t\t\t\tlabel = \"GPIO KEY_ENTER\";\n+\t\t\t\t\tlinux,code = <28>;\n+\t\t\t\t\tgpios = <&gpio 4 0>;\n+\t\t\t\t};\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\tspeed =      <&tinylcd35>,\"spi-max-frequency:0\";\n+\t\trotate =     <&tinylcd35>,\"rotate:0\";\n+\t\tfps =        <&tinylcd35>,\"fps:0\";\n+\t\tdebug =      <&tinylcd35>,\"debug:0\";\n+\t\ttouch =      <&tinylcd35_ts>,\"status\";\n+\t\ttouchgpio =  <&tinylcd35_ts_pins>,\"brcm,pins:0\",\n+\t\t\t     <&tinylcd35_ts>,\"interrupts:0\",\n+\t\t\t     <&tinylcd35_ts>,\"pendown-gpio:4\";\n+\t\txohms =      <&tinylcd35_ts>,\"ti,x-plate-ohms;0\";\n+\t\trtc-pcf =    <0>,\"=5\";\n+\t\trtc-ds =     <0>,\"=6\";\n+\t\tkeypad =     <&keypad>,\"status\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/tpm-slb9670-overlay.dts b/arch/arm/boot/dts/overlays/tpm-slb9670-overlay.dts\nnew file mode 100644\nindex 000000000000..e69188503ca3\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/tpm-slb9670-overlay.dts\n@@ -0,0 +1,44 @@\n+/*\n+ * Device Tree overlay for the Infineon SLB9670 Trusted Platform Module add-on\n+ * boards, which can be used as a secure key storage and hwrng.\n+ * available as \"Iridium SLB9670\" by Infineon and \"LetsTrust TPM\" by pi3g.\n+ */\n+\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&spi0>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&spidev1>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&spi0>;\n+\t\t__overlay__ {\n+\t\t\t/* needed to avoid dtc warning */\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tslb9670: slb9670@1 {\n+\t\t\t\tcompatible = \"infineon,slb9670\";\n+\t\t\t\treg = <1>;\t/* CE1 */\n+\t\t\t\t#address-cells = <1>;\n+\t\t\t\t#size-cells = <0>;\n+\t\t\t\tspi-max-frequency = <32000000>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\n+\t\t};\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/uart0-overlay.dts b/arch/arm/boot/dts/overlays/uart0-overlay.dts\nnew file mode 100755\nindex 000000000000..73d563bbaabf\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/uart0-overlay.dts\n@@ -0,0 +1,32 @@\n+/dts-v1/;\n+/plugin/;\n+\n+/{\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&uart0>;\n+\t\t__overlay__ {\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&uart0_pins>;\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&gpio>;\n+\t\t__overlay__ {\n+\t\t\tuart0_pins: uart0_pins {\n+\t\t\t\tbrcm,pins = <14 15>;\n+\t\t\t\tbrcm,function = <4>; /* alt0 */\n+\t\t\t\tbrcm,pull = <0 2>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\ttxd0_pin = <&uart0_pins>,\"brcm,pins:0\";\n+\t\trxd0_pin = <&uart0_pins>,\"brcm,pins:4\";\n+\t\tpin_func = <&uart0_pins>,\"brcm,function:0\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/uart1-overlay.dts b/arch/arm/boot/dts/overlays/uart1-overlay.dts\nnew file mode 100644\nindex 000000000000..986d725a2652\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/uart1-overlay.dts\n@@ -0,0 +1,38 @@\n+/dts-v1/;\n+/plugin/;\n+\n+/{\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&uart1>;\n+\t\t__overlay__ {\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&uart1_pins>;\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&gpio>;\n+\t\t__overlay__ {\n+\t\t\tuart1_pins: uart1_pins {\n+\t\t\t\tbrcm,pins = <14 15>;\n+\t\t\t\tbrcm,function = <2>; /* alt5 */\n+\t\t\t\tbrcm,pull = <0 2>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget-path = \"/chosen\";\n+\t\t__overlay__ {\n+\t\t\tbootargs = \"8250.nr_uarts=1\";\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\ttxd1_pin = <&uart1_pins>,\"brcm,pins:0\";\n+\t\trxd1_pin = <&uart1_pins>,\"brcm,pins:4\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/uart2-overlay.dts b/arch/arm/boot/dts/overlays/uart2-overlay.dts\nnew file mode 100644\nindex 000000000000..9face240aca1\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/uart2-overlay.dts\n@@ -0,0 +1,27 @@\n+/dts-v1/;\n+/plugin/;\n+\n+/{\n+\tcompatible = \"brcm,bcm2711\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&uart2>;\n+\t\t__overlay__ {\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&uart2_pins>;\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&uart2_pins>;\n+\t\t__dormant__ {\n+\t\t\tbrcm,pins = <0 1 2 3>;\n+\t\t\tbrcm,pull = <0 2 2 0>;\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\tctsrts = <0>,\"=1\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/uart3-overlay.dts b/arch/arm/boot/dts/overlays/uart3-overlay.dts\nnew file mode 100644\nindex 000000000000..ae9f9fe5ea1d\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/uart3-overlay.dts\n@@ -0,0 +1,27 @@\n+/dts-v1/;\n+/plugin/;\n+\n+/{\n+\tcompatible = \"brcm,bcm2711\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&uart3>;\n+\t\t__overlay__ {\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&uart3_pins>;\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&uart3_pins>;\n+\t\t__dormant__ {\n+\t\t\tbrcm,pins = <4 5 6 7>;\n+\t\t\tbrcm,pull = <0 2 2 0>;\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\tctsrts = <0>,\"=1\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/uart4-overlay.dts b/arch/arm/boot/dts/overlays/uart4-overlay.dts\nnew file mode 100644\nindex 000000000000..ac004ffbadbf\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/uart4-overlay.dts\n@@ -0,0 +1,27 @@\n+/dts-v1/;\n+/plugin/;\n+\n+/{\n+\tcompatible = \"brcm,bcm2711\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&uart4>;\n+\t\t__overlay__ {\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&uart4_pins>;\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&uart4_pins>;\n+\t\t__dormant__ {\n+\t\t\tbrcm,pins = <8 9 10 11>;\n+\t\t\tbrcm,pull = <0 2 2 0>;\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\tctsrts = <0>,\"=1\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/uart5-overlay.dts b/arch/arm/boot/dts/overlays/uart5-overlay.dts\nnew file mode 100644\nindex 000000000000..04eaf376effe\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/uart5-overlay.dts\n@@ -0,0 +1,27 @@\n+/dts-v1/;\n+/plugin/;\n+\n+/{\n+\tcompatible = \"brcm,bcm2711\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&uart5>;\n+\t\t__overlay__ {\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&uart5_pins>;\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&uart5_pins>;\n+\t\t__dormant__ {\n+\t\t\tbrcm,pins = <12 13 14 15>;\n+\t\t\tbrcm,pull = <0 2 2 0>;\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\tctsrts = <0>,\"=1\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/udrc-overlay.dts b/arch/arm/boot/dts/overlays/udrc-overlay.dts\nnew file mode 100644\nindex 000000000000..ae7c37996894\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/udrc-overlay.dts\n@@ -0,0 +1,128 @@\n+#include <dt-bindings/clock/bcm2835.h>\n+/*\n+ * Device tree overlay for the Universal Digital Radio Controller\n+ */\n+\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+    compatible = \"brcm,bcm2835\";\n+    fragment@0 {\n+        target = <&i2s>;\n+        __overlay__ {\n+            clocks = <&clocks BCM2835_CLOCK_PCM>;\n+            clock-names = \"pcm\";\n+            status = \"okay\";\n+        };\n+    };\n+\n+    fragment@1 {\n+        target-path = \"/\";\n+        __overlay__ {\n+            regulators {\n+                compatible = \"simple-bus\";\n+                #address-cells = <1>;\n+                #size-cells = <0>;\n+\n+                udrc0_ldoin: udrc0_ldoin {\n+                    compatible = \"regulator-fixed\";\n+                    regulator-name = \"ldoin\";\n+                    regulator-min-microvolt = <3300000>;\n+                    regulator-max-microvolt = <3300000>;\n+                    regulator-always-on;\n+                };\n+            };\n+        };\n+    };\n+\n+    fragment@2 {\n+        target = <&i2c1>;\n+        __overlay__ {\n+            #address-cells = <1>;\n+            #size-cells = <0>;\n+            status = \"okay\";\n+            clocks = <&clocks BCM2835_CLOCK_VPU>;\n+            clock-frequency = <400000>;\n+\n+            tlv320aic32x4: tlv320aic32x4@18 {\n+                compatible = \"ti,tlv320aic32x4\";\n+                #sound-dai-cells = <0>;\n+                reg = <0x18>;\n+                status = \"okay\";\n+\n+                clocks = <&clocks BCM2835_CLOCK_GP0>;\n+                clock-names = \"mclk\";\n+                assigned-clocks = <&clocks BCM2835_CLOCK_GP0>;\n+                assigned-clock-rates = <25000000>;\n+\n+                pinctrl-names = \"default\";\n+                pinctrl-0 = <&gpclk0_pin &aic3204_reset>;\n+\n+                reset-gpios = <&gpio 13 0>;\n+\n+                iov-supply = <&udrc0_ldoin>;\n+                ldoin-supply = <&udrc0_ldoin>;\n+            };\n+        };\n+    };\n+\n+    fragment@3 {\n+        target = <&sound>;\n+        snd: __overlay__ {\n+            compatible = \"simple-audio-card\";\n+            i2s-controller = <&i2s>;\n+            status = \"okay\";\n+\n+            simple-audio-card,name = \"udrc\";\n+            simple-audio-card,format = \"i2s\";\n+\n+            simple-audio-card,bitclock-master = <&dailink0_master>;\n+            simple-audio-card,frame-master = <&dailink0_master>;\n+\n+            simple-audio-card,widgets =\n+                \"Line\", \"Line In\",\n+                \"Line\", \"Line Out\";\n+\n+            simple-audio-card,routing =\n+                \"IN1_R\", \"Line In\",\n+                \"IN1_L\", \"Line In\",\n+                \"CM_L\", \"Line In\",\n+                \"CM_R\", \"Line In\",\n+                \"Line Out\", \"LOR\",\n+                \"Line Out\", \"LOL\";\n+\n+            dailink0_master: simple-audio-card,cpu {\n+                sound-dai = <&i2s>;\n+            };\n+\n+            simple-audio-card,codec {\n+                sound-dai = <&tlv320aic32x4>;\n+            };\n+        };\n+    };\n+\n+    fragment@4 {\n+        target = <&gpio>;\n+        __overlay__ {\n+            gpclk0_pin: gpclk0_pin {\n+                brcm,pins = <4>;\n+                brcm,function = <4>;\n+            };\n+\n+            aic3204_reset: aic3204_reset {\n+                brcm,pins = <13>;\n+                brcm,function = <1>;\n+                brcm,pull = <1>;\n+            };\n+\n+            aic3204_gpio: aic3204_gpio {\n+                brcm,pins = <26>;\n+            };\n+        };\n+    };\n+\n+    __overrides__ {\n+        alsaname = <&snd>, \"simple-audio-card,name\";\n+    };\n+};\ndiff --git a/arch/arm/boot/dts/overlays/upstream-overlay.dts b/arch/arm/boot/dts/overlays/upstream-overlay.dts\nnew file mode 100644\nindex 000000000000..2e9dcd4f5f0a\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/upstream-overlay.dts\n@@ -0,0 +1,113 @@\n+// redo: ovmerge -c vc4-kms-v3d-overlay.dts,cma-default dwc2-overlay.dts,dr_mode=otg\n+\n+/dts-v1/;\n+/plugin/;\n+\n+#include <dt-bindings/clock/bcm2835.h>\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\tfragment@0 {\n+\t\ttarget = <&cma>;\n+\t\t__dormant__ {\n+\t\t\tsize = <0x10000000>;\n+\t\t};\n+\t};\n+\tfragment@1 {\n+\t\ttarget = <&i2c2>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\tfragment@2 {\n+\t\ttarget = <&fb>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\tfragment@3 {\n+\t\ttarget = <&pixelvalve0>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\tfragment@4 {\n+\t\ttarget = <&pixelvalve1>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\tfragment@5 {\n+\t\ttarget = <&pixelvalve2>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\tfragment@6 {\n+\t\ttarget = <&hvs>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\tfragment@7 {\n+\t\ttarget = <&hdmi>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\tfragment@8 {\n+\t\ttarget = <&v3d>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\tfragment@9 {\n+\t\ttarget = <&vc4>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\tfragment@10 {\n+\t\ttarget = <&clocks>;\n+\t\t__overlay__ {\n+\t\t\tclaim-clocks = <BCM2835_PLLD_DSI0 BCM2835_PLLD_DSI1 BCM2835_PLLH_AUX BCM2835_PLLH_PIX>;\n+\t\t};\n+\t};\n+\tfragment@11 {\n+\t\ttarget = <&vec>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\tfragment@12 {\n+\t\ttarget = <&txp>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\tfragment@13 {\n+\t\ttarget = <&hdmi>;\n+\t\t__dormant__ {\n+\t\t\tdmas;\n+\t\t};\n+\t};\n+\tfragment@14 {\n+\t\ttarget = <&audio>;\n+\t\t__overlay__ {\n+\t\t\tbrcm,disable-hdmi;\n+\t\t};\n+\t};\n+\tfragment@15 {\n+\t\ttarget = <&usb>;\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <1>;\n+\t\t__overlay__ {\n+\t\t\tcompatible = \"brcm,bcm2835-usb\";\n+\t\t\tdr_mode = \"otg\";\n+\t\t\tg-np-tx-fifo-size = <32>;\n+\t\t\tg-rx-fifo-size = <558>;\n+\t\t\tg-tx-fifo-size = <512 512 512 512 512 256 256>;\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/upstream-pi4-overlay.dts b/arch/arm/boot/dts/overlays/upstream-pi4-overlay.dts\nnew file mode 100644\nindex 000000000000..6195e02bf9ff\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/upstream-pi4-overlay.dts\n@@ -0,0 +1,161 @@\n+// redo: ovmerge -c vc4-kms-v3d-pi4-overlay.dts,cma-default dwc2-overlay.dts,dr_mode=otg\n+\n+/dts-v1/;\n+/plugin/;\n+\n+#include <dt-bindings/clock/bcm2835.h>\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\tfragment@0 {\n+\t\ttarget = <&cma>;\n+\t\t__dormant__ {\n+\t\t\tsize = <0x10000000>;\n+\t\t};\n+\t};\n+\tfragment@1 {\n+\t\ttarget = <&ddc0>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\tfragment@2 {\n+\t\ttarget = <&ddc1>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\tfragment@3 {\n+\t\ttarget = <&hdmi0>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\tfragment@4 {\n+\t\ttarget = <&hdmi1>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\tfragment@5 {\n+\t\ttarget = <&hvs>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\tfragment@6 {\n+\t\ttarget = <&pixelvalve0>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\tfragment@7 {\n+\t\ttarget = <&pixelvalve1>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\tfragment@8 {\n+\t\ttarget = <&pixelvalve2>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\tfragment@9 {\n+\t\ttarget = <&pixelvalve3>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\tfragment@10 {\n+\t\ttarget = <&pixelvalve4>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\tfragment@11 {\n+\t\ttarget = <&v3d>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\tfragment@12 {\n+\t\ttarget = <&vc4>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\tfragment@13 {\n+\t\ttarget = <&txp>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\tfragment@14 {\n+\t\ttarget = <&fb>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\tfragment@15 {\n+\t\ttarget = <&firmwarekms>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\tfragment@16 {\n+\t\ttarget = <&vec>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\tfragment@17 {\n+\t\ttarget = <&hdmi0>;\n+\t\t__dormant__ {\n+\t\t\tdmas;\n+\t\t};\n+\t};\n+\tfragment@18 {\n+\t\ttarget = <&hdmi1>;\n+\t\t__dormant__ {\n+\t\t\tdmas;\n+\t\t};\n+\t};\n+\tfragment@19 {\n+\t\ttarget = <&audio>;\n+\t\t__overlay__ {\n+\t\t\tbrcm,disable-hdmi;\n+\t\t};\n+\t};\n+\tfragment@20 {\n+\t\ttarget = <&dvp>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\tfragment@21 {\n+\t\ttarget = <&pixelvalve3>;\n+\t\t__dormant__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\tfragment@22 {\n+\t\ttarget = <&vec>;\n+\t\t__dormant__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\tfragment@23 {\n+\t\ttarget = <&usb>;\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <1>;\n+\t\t__overlay__ {\n+\t\t\tcompatible = \"brcm,bcm2835-usb\";\n+\t\t\tdr_mode = \"otg\";\n+\t\t\tg-np-tx-fifo-size = <32>;\n+\t\t\tg-rx-fifo-size = <558>;\n+\t\t\tg-tx-fifo-size = <512 512 512 512 512 256 256>;\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/vc4-fkms-v3d-overlay.dts b/arch/arm/boot/dts/overlays/vc4-fkms-v3d-overlay.dts\nnew file mode 100644\nindex 000000000000..ca344492bed8\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/vc4-fkms-v3d-overlay.dts\n@@ -0,0 +1,40 @@\n+/*\n+ * vc4-fkms-v3d-overlay.dts\n+ */\n+\n+/dts-v1/;\n+/plugin/;\n+\n+#include \"cma-overlay.dts\"\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@1 {\n+\t\ttarget = <&fb>;\n+\t\t__overlay__  {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&firmwarekms>;\n+\t\t__overlay__  {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@3 {\n+\t\ttarget = <&v3d>;\n+\t\t__overlay__  {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@4 {\n+\t\ttarget = <&vc4>;\n+\t\t__overlay__  {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/vc4-kms-kippah-7inch-overlay.dts b/arch/arm/boot/dts/overlays/vc4-kms-kippah-7inch-overlay.dts\nnew file mode 100644\nindex 000000000000..b03394844abd\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/vc4-kms-kippah-7inch-overlay.dts\n@@ -0,0 +1,43 @@\n+/*\n+ * vc4-kms-v3d-overlay.dts\n+ */\n+\n+/dts-v1/;\n+/plugin/;\n+\n+#include <dt-bindings/pinctrl/bcm2835.h>\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget-path = \"/\";\n+\t\t__overlay__ {\n+\t\t\tpanel: panel {\n+\t\t\t\tcompatible = \"ontat,yx700wv03\", \"simple-panel\";\n+\n+\t\t\t\tport {\n+\t\t\t\t\tpanel_in: endpoint {\n+\t\t\t\t\t\tremote-endpoint = <&dpi_out>;\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&dpi>;\n+\t\t__overlay__  {\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&dpi_18bit_gpio0>;\n+\n+\t\t\tport {\n+\t\t\t\tdpi_out: endpoint@0 {\n+\t\t\t\t\tremote-endpoint = <&panel_in>;\n+\t\t\t\t};\n+\t\t\t};\n+\t\t};\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/vc4-kms-v3d-overlay.dts b/arch/arm/boot/dts/overlays/vc4-kms-v3d-overlay.dts\nnew file mode 100644\nindex 000000000000..6d34a2bff49b\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/vc4-kms-v3d-overlay.dts\n@@ -0,0 +1,122 @@\n+/*\n+ * vc4-kms-v3d-overlay.dts\n+ */\n+\n+/dts-v1/;\n+/plugin/;\n+\n+#include <dt-bindings/clock/bcm2835.h>\n+\n+#include \"cma-overlay.dts\"\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@1 {\n+\t\ttarget = <&i2c2>;\n+\t\t__overlay__  {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&fb>;\n+\t\t__overlay__  {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\tfragment@3 {\n+\t\ttarget = <&pixelvalve0>;\n+\t\t__overlay__  {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@4 {\n+\t\ttarget = <&pixelvalve1>;\n+\t\t__overlay__  {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@5 {\n+\t\ttarget = <&pixelvalve2>;\n+\t\t__overlay__  {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@6 {\n+\t\ttarget = <&hvs>;\n+\t\t__overlay__  {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@7 {\n+\t\ttarget = <&hdmi>;\n+\t\t__overlay__  {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@8 {\n+\t\ttarget = <&v3d>;\n+\t\t__overlay__  {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@9 {\n+\t\ttarget = <&vc4>;\n+\t\t__overlay__  {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@10 {\n+\t\ttarget = <&clocks>;\n+\t\t__overlay__  {\n+\t\t\tclaim-clocks = <\n+\t\t\t\tBCM2835_PLLD_DSI0\n+\t\t\t\tBCM2835_PLLD_DSI1\n+\t\t\t\tBCM2835_PLLH_AUX\n+\t\t\t\tBCM2835_PLLH_PIX\n+\t\t\t>;\n+\t\t};\n+\t};\n+\n+\tfragment@11 {\n+\t\ttarget = <&vec>;\n+\t\t__overlay__  {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@12 {\n+\t\ttarget = <&txp>;\n+\t\t__overlay__  {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@13 {\n+\t\ttarget = <&hdmi>;\n+\t\t__dormant__  {\n+\t\t\tdmas;\n+\t\t};\n+\t};\n+\n+\tfragment@14 {\n+\t\ttarget = <&audio>;\n+\t\t__overlay__  {\n+\t\t    brcm,disable-hdmi;\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\taudio   = <0>,\"!13\", <0>,\"=14\";\n+\t\tnoaudio = <0>,\"=13\", <0>,\"!14\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/vc4-kms-v3d-pi4-overlay.dts b/arch/arm/boot/dts/overlays/vc4-kms-v3d-pi4-overlay.dts\nnew file mode 100644\nindex 000000000000..f721f12d729d\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/vc4-kms-v3d-pi4-overlay.dts\n@@ -0,0 +1,186 @@\n+/*\n+ * vc4-kms-v3d-pi4-overlay.dts\n+ */\n+\n+/dts-v1/;\n+/plugin/;\n+\n+#include <dt-bindings/clock/bcm2835.h>\n+\n+#include \"cma-overlay.dts\"\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@1 {\n+\t\ttarget = <&ddc0>;\n+\t\t__overlay__  {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&ddc1>;\n+\t\t__overlay__  {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@3 {\n+\t\ttarget = <&hdmi0>;\n+\t\t__overlay__  {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@4 {\n+\t\ttarget = <&hdmi1>;\n+\t\t__overlay__  {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@5 {\n+\t\ttarget = <&hvs>;\n+\t\t__overlay__  {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@6 {\n+\t\ttarget = <&pixelvalve0>;\n+\t\t__overlay__  {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@7 {\n+\t\ttarget = <&pixelvalve1>;\n+\t\t__overlay__  {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@8 {\n+\t\ttarget = <&pixelvalve2>;\n+\t\t__overlay__  {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@9 {\n+\t\ttarget = <&pixelvalve3>;\n+\t\t__overlay__  {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@10 {\n+\t\ttarget = <&pixelvalve4>;\n+\t\t__overlay__  {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@11 {\n+\t\ttarget = <&v3d>;\n+\t\t__overlay__  {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@12 {\n+\t\ttarget = <&vc4>;\n+\t\t__overlay__  {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@13 {\n+\t\ttarget = <&txp>;\n+\t\t__overlay__  {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@14 {\n+\t\ttarget = <&fb>;\n+\t\t__overlay__  {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\tfragment@15 {\n+\t\ttarget = <&firmwarekms>;\n+\t\t__overlay__  {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\tfragment@16 {\n+\t\ttarget = <&vec>;\n+\t\t__overlay__  {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\tfragment@17 {\n+\t\ttarget = <&hdmi0>;\n+\t\t__dormant__  {\n+\t\t\tdmas;\n+\t\t};\n+\t};\n+\n+\tfragment@18 {\n+\t\ttarget = <&hdmi1>;\n+\t\t__dormant__  {\n+\t\t\tdmas;\n+\t\t};\n+\t};\n+\n+\tfragment@19 {\n+\t\ttarget = <&audio>;\n+\t\t__overlay__  {\n+\t\t    brcm,disable-hdmi;\n+\t\t};\n+\t};\n+\n+\tfragment@20 {\n+\t\ttarget = <&dvp>;\n+\t\t__overlay__  {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@21 {\n+\t\ttarget = <&pixelvalve3>;\n+\t\t__dormant__  {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@22 {\n+\t\ttarget = <&vec>;\n+\t\t__dormant__  {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\taudio   = <0>,\"!17\";\n+\t\taudio1   = <0>,\"!18\";\n+\t\tnoaudio = <0>,\"=17\", <0>,\"=18\", <0>,\"!19\";\n+\t\tcomposite = <0>, \"!1\",\n+\t\t\t    <0>, \"!2\",\n+\t\t\t    <0>, \"!3\",\n+\t\t\t    <0>, \"!4\",\n+\t\t\t    <0>, \"!6\",\n+\t\t\t    <0>, \"!7\",\n+\t\t\t    <0>, \"!8\",\n+\t\t\t    <0>, \"!9\",\n+\t\t\t    <0>, \"!10\",\n+\t\t\t    <0>, \"!16\",\n+\t\t\t    <0>, \"=21\",\n+\t\t\t    <0>, \"=22\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/vga666-overlay.dts b/arch/arm/boot/dts/overlays/vga666-overlay.dts\nnew file mode 100644\nindex 000000000000..a4968d180a5d\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/vga666-overlay.dts\n@@ -0,0 +1,30 @@\n+/dts-v1/;\n+/plugin/;\n+\n+/{\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\t// There is no VGA driver module, but we need a platform device\n+\t// node (that doesn't already use pinctrl) to hang the pinctrl\n+\t// reference on - leds will do\n+\n+\tfragment@0 {\n+\t\ttarget = <&leds>;\n+\t\t__overlay__ {\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&vga666_pins>;\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&gpio>;\n+\t\t__overlay__ {\n+\t\t\tvga666_pins: vga666_pins {\n+\t\t\t\tbrcm,pins = <2 3 4 5 6 7 8 9 10 11 12\n+\t\t\t\t\t     13 14 15 16 17 18 19 20 21>;\n+\t\t\t\tbrcm,function = <6>; /* alt2 */\n+\t\t\t\tbrcm,pull = <0>; /* no pull */\n+\t\t\t};\n+\t\t};\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/w1-gpio-overlay.dts b/arch/arm/boot/dts/overlays/w1-gpio-overlay.dts\nnew file mode 100644\nindex 000000000000..f44e325bc1f2\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/w1-gpio-overlay.dts\n@@ -0,0 +1,40 @@\n+// Definitions for w1-gpio module (without external pullup)\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget-path = \"/\";\n+\t\t__overlay__ {\n+\n+\t\t\tw1: onewire@0 {\n+\t\t\t\tcompatible = \"w1-gpio\";\n+\t\t\t\tpinctrl-names = \"default\";\n+\t\t\t\tpinctrl-0 = <&w1_pins>;\n+\t\t\t\tgpios = <&gpio 4 0>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&gpio>;\n+\t\t__overlay__ {\n+\t\t\tw1_pins: w1_pins@0 {\n+\t\t\t\tbrcm,pins = <4>;\n+\t\t\t\tbrcm,function = <0>; // in (initially)\n+\t\t\t\tbrcm,pull = <0>; // off\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\tgpiopin =       <&w1>,\"gpios:4\",\n+\t\t\t\t<&w1>,\"reg:0\",\n+\t\t\t\t<&w1_pins>,\"brcm,pins:0\",\n+\t\t\t\t<&w1_pins>,\"reg:0\";\n+\t\tpullup;\t\t// Silently ignore unneeded parameter\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/w1-gpio-pullup-overlay.dts b/arch/arm/boot/dts/overlays/w1-gpio-pullup-overlay.dts\nnew file mode 100644\nindex 000000000000..953c6a1aeab9\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/w1-gpio-pullup-overlay.dts\n@@ -0,0 +1,42 @@\n+// Definitions for w1-gpio module (with external pullup)\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget-path = \"/\";\n+\t\t__overlay__ {\n+\n+\t\t\tw1: onewire@0 {\n+\t\t\t\tcompatible = \"w1-gpio\";\n+\t\t\t\tpinctrl-names = \"default\";\n+\t\t\t\tpinctrl-0 = <&w1_pins>;\n+\t\t\t\tgpios = <&gpio 4 0>, <&gpio 5 1>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&gpio>;\n+\t\t__overlay__ {\n+\t\t\tw1_pins: w1_pins@0 {\n+\t\t\t\tbrcm,pins = <4 5>;\n+\t\t\t\tbrcm,function = <0 1>; // in out\n+\t\t\t\tbrcm,pull = <0 0>; // off off\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\tgpiopin =       <&w1>,\"gpios:4\",\n+\t\t\t\t<&w1>,\"reg:0\",\n+\t\t\t\t<&w1_pins>,\"brcm,pins:0\",\n+\t\t\t\t<&w1_pins>,\"reg:0\";\n+\t\textpullup =     <&w1>,\"gpios:16\",\n+\t\t\t\t<&w1_pins>,\"brcm,pins:4\";\n+\t\tpullup;\t\t// Silently ignore unneeded parameter\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/w5500-overlay.dts b/arch/arm/boot/dts/overlays/w5500-overlay.dts\nnew file mode 100644\nindex 000000000000..4d3e66296753\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/w5500-overlay.dts\n@@ -0,0 +1,63 @@\n+// Overlay for the Wiznet w5500 Ethernet Controller\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&spidev0>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&spidev1>;\n+\t\t__dormant__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&spi0>;\n+\t\t__overlay__ {\n+\t\t\t/* needed to avoid dtc warning */\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\teth1: w5500@0{\n+\t\t\t\tcompatible = \"wiznet,w5500\";\n+\t\t\t\treg = <0>; /* CE0 */\n+\t\t\t\tpinctrl-names = \"default\";\n+\t\t\t\tpinctrl-0 = <&eth1_pins>;\n+\t\t\t\tinterrupt-parent = <&gpio>;\n+\t\t\t\tinterrupts = <25 0x8>;\n+\t\t\t\tspi-max-frequency = <30000000>;\n+//\t\t\t\tlocal-mac-address = [aa bb cc dd ee ff];\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@3 {\n+\t\ttarget = <&gpio>;\n+\t\t__overlay__ {\n+\t\t\teth1_pins: eth1_pins {\n+\t\t\t\tbrcm,pins = <25>;\n+\t\t\t\tbrcm,function = <0>; /* in */\n+\t\t\t\tbrcm,pull = <0>; /* none */\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\tint_pin = <&eth1>, \"interrupts:0\",\n+\t\t          <&eth1_pins>, \"brcm,pins:0\";\n+\t\tspeed   = <&eth1>, \"spi-max-frequency:0\";\n+\t\tcs      = <&eth1>, \"reg:0\",\n+\t\t\t  <0>, \"!0=1\";\n+\t};\n+};\ndiff --git a/arch/arm/boot/dts/overlays/wittypi-overlay.dts b/arch/arm/boot/dts/overlays/wittypi-overlay.dts\nnew file mode 100644\nindex 000000000000..71ce806186de\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/wittypi-overlay.dts\n@@ -0,0 +1,44 @@\n+/*\n+ * Device Tree overlay for Witty Pi extension board by UUGear\n+ *\n+ */\n+\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&leds>;\n+\t\t__overlay__ {\n+\t\t\tcompatible = \"gpio-leds\";\n+\t\t\twittypi_led: wittypi_led {\n+\t\t\t\tlabel = \"wittypi_led\";\n+\t\t\t\tlinux,default-trigger = \"default-on\";\n+\t\t\t\tgpios = <&gpio 17 0>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&i2c1>;\n+\t\t__overlay__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\trtc: ds1337@68 {\n+\t\t\t\tcompatible = \"dallas,ds1337\";\n+\t\t\t\treg = <0x68>;\n+\t\t\t\twakeup-source;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\tled_gpio =\t<&wittypi_led>,\"gpios:4\";\n+\t\tled_trigger =\t<&wittypi_led>,\"linux,default-trigger\";\n+\t};\n+\n+};\ndiff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile\nindex 9b1170658d60..cc6c25629057 100644\n--- a/arch/arm64/boot/dts/Makefile\n+++ b/arch/arm64/boot/dts/Makefile\n@@ -30,3 +30,5 @@ subdir-y += ti\n subdir-y += toshiba\n subdir-y += xilinx\n subdir-y += zte\n+\n+subdir-y += overlays\ndiff --git a/arch/arm64/boot/dts/broadcom/Makefile b/arch/arm64/boot/dts/broadcom/Makefile\nindex cb7de8d99223..c3eaf8d63ee4 100644\n--- a/arch/arm64/boot/dts/broadcom/Makefile\n+++ b/arch/arm64/boot/dts/broadcom/Makefile\n@@ -1,9 +1,21 @@\n # SPDX-License-Identifier: GPL-2.0\n-dtb-$(CONFIG_ARCH_BCM2835) += bcm2711-rpi-4-b.dtb \\\n-\t\t\t      bcm2837-rpi-3-a-plus.dtb \\\n+dtb-$(CONFIG_ARCH_BCM2835) += bcm2837-rpi-3-a-plus.dtb \\\n \t\t\t      bcm2837-rpi-3-b.dtb \\\n \t\t\t      bcm2837-rpi-3-b-plus.dtb \\\n \t\t\t      bcm2837-rpi-cm3-io3.dtb\n+dtb-$(CONFIG_ARCH_BCM2709) += bcm2710-rpi-2-b.dtb\n+dtb-$(CONFIG_ARCH_BCM2709) += bcm2710-rpi-3-b.dtb\n+dtb-$(CONFIG_ARCH_BCM2835) += bcm2710-rpi-2-b.dtb\n+dtb-$(CONFIG_ARCH_BCM2835) += bcm2710-rpi-3-b.dtb\n+dtb-$(CONFIG_ARCH_BCM2835) += bcm2711-rpi-4-b.dtb\n+dtb-$(CONFIG_ARCH_BCM2835) += bcm2710-rpi-3-b-plus.dtb\n+dtb-$(CONFIG_ARCH_BCM2709) += bcm2710-rpi-cm3.dtb\n+dtb-$(CONFIG_ARCH_BCM2835) += bcm2710-rpi-cm3.dtb\n \n subdir-y\t+= northstar2\n subdir-y\t+= stingray\n+\n+# Enable fixups to support overlays on BCM2835 platforms\n+ifeq ($(CONFIG_ARCH_BCM2835),y)\n+\tDTC_FLAGS ?= -@\n+endif\ndiff --git a/arch/arm64/boot/dts/broadcom/bcm2710-rpi-2-b.dts b/arch/arm64/boot/dts/broadcom/bcm2710-rpi-2-b.dts\nnew file mode 100644\nindex 000000000000..116cdbf94b9b\n--- /dev/null\n+++ b/arch/arm64/boot/dts/broadcom/bcm2710-rpi-2-b.dts\n@@ -0,0 +1,3 @@\n+#define RPI364\n+\n+#include \"../../../../arm/boot/dts/bcm2710-rpi-2-b.dts\"\ndiff --git a/arch/arm64/boot/dts/broadcom/bcm2710-rpi-3-b-plus.dts b/arch/arm64/boot/dts/broadcom/bcm2710-rpi-3-b-plus.dts\nnew file mode 100644\nindex 000000000000..d9242ff77079\n--- /dev/null\n+++ b/arch/arm64/boot/dts/broadcom/bcm2710-rpi-3-b-plus.dts\n@@ -0,0 +1,3 @@\n+#define RPI364\n+\n+#include \"../../../../arm/boot/dts/bcm2710-rpi-3-b-plus.dts\"\ndiff --git a/arch/arm64/boot/dts/broadcom/bcm2710-rpi-3-b.dts b/arch/arm64/boot/dts/broadcom/bcm2710-rpi-3-b.dts\nnew file mode 100644\nindex 000000000000..deb33441da95\n--- /dev/null\n+++ b/arch/arm64/boot/dts/broadcom/bcm2710-rpi-3-b.dts\n@@ -0,0 +1,3 @@\n+#define RPI364\n+\n+#include \"../../../../arm/boot/dts/bcm2710-rpi-3-b.dts\"\ndiff --git a/arch/arm64/boot/dts/broadcom/bcm2710-rpi-cm3.dts b/arch/arm64/boot/dts/broadcom/bcm2710-rpi-cm3.dts\nnew file mode 100644\nindex 000000000000..1c2560017c02\n--- /dev/null\n+++ b/arch/arm64/boot/dts/broadcom/bcm2710-rpi-cm3.dts\n@@ -0,0 +1,3 @@\n+#define RPI364\n+\n+#include \"../../../../arm/boot/dts/bcm2710-rpi-cm3.dts\"\ndiff --git a/arch/arm64/boot/dts/broadcom/bcm2711-rpi-4-b.dts b/arch/arm64/boot/dts/broadcom/bcm2711-rpi-4-b.dts\nindex d24c53682e44..1fd86f81f542 100644\n--- a/arch/arm64/boot/dts/broadcom/bcm2711-rpi-4-b.dts\n+++ b/arch/arm64/boot/dts/broadcom/bcm2711-rpi-4-b.dts\n@@ -1,2 +1,3 @@\n-// SPDX-License-Identifier: GPL-2.0\n-#include \"arm/bcm2711-rpi-4-b.dts\"\n+#define RPI364\n+\n+#include \"../../../../arm/boot/dts/bcm2711-rpi-4-b.dts\"\ndiff --git a/arch/arm64/boot/dts/broadcom/bcm283x-rpi-csi1-2lane.dtsi b/arch/arm64/boot/dts/broadcom/bcm283x-rpi-csi1-2lane.dtsi\nnew file mode 120000\nindex 000000000000..e5c400284467\n--- /dev/null\n+++ b/arch/arm64/boot/dts/broadcom/bcm283x-rpi-csi1-2lane.dtsi\n@@ -0,0 +1 @@\n+../../../../arm/boot/dts/bcm283x-rpi-csi1-2lane.dtsi\n\\ No newline at end of file\ndiff --git a/arch/arm64/boot/dts/broadcom/bcm283x-rpi-lan7515.dtsi b/arch/arm64/boot/dts/broadcom/bcm283x-rpi-lan7515.dtsi\nnew file mode 120000\nindex 000000000000..fc4c05bbe7fd\n--- /dev/null\n+++ b/arch/arm64/boot/dts/broadcom/bcm283x-rpi-lan7515.dtsi\n@@ -0,0 +1 @@\n+../../../../arm/boot/dts/bcm283x-rpi-lan7515.dtsi\n\\ No newline at end of file\ndiff --git a/arch/arm64/boot/dts/overlays b/arch/arm64/boot/dts/overlays\nnew file mode 120000\nindex 000000000000..ded08646b6f6\n--- /dev/null\n+++ b/arch/arm64/boot/dts/overlays\n@@ -0,0 +1 @@\n+../../../arm/boot/dts/overlays\n\\ No newline at end of file\ndiff --git a/scripts/Makefile.dtbinst b/scripts/Makefile.dtbinst\nindex 50d580d77ae9..079b83308011 100644\n--- a/scripts/Makefile.dtbinst\n+++ b/scripts/Makefile.dtbinst\n@@ -18,9 +18,10 @@ include scripts/Kbuild.include\n include $(src)/Makefile\n \n dtbs    := $(addprefix $(dst)/, $(dtb-y) $(if $(CONFIG_OF_ALL_DTBS),$(dtb-)))\n+dtbos   := $(addprefix $(dst)/, $(dtbo-y) $(if $(CONFIG_OF_ALL_DTBS),$(dtb-)))\n subdirs := $(addprefix $(obj)/, $(subdir-y) $(subdir-m))\n \n-__dtbs_install: $(dtbs) $(subdirs)\n+__dtbs_install: $(dtbs) $(dtbos) $(subdirs)\n \t@:\n \n quiet_cmd_dtb_install = INSTALL $@\n@@ -29,6 +30,9 @@ quiet_cmd_dtb_install = INSTALL $@\n $(dst)/%.dtb: $(obj)/%.dtb\n \t$(call cmd,dtb_install)\n \n+$(dst)/%.dtbo: $(obj)/%.dtbo\n+\t$(call cmd,dtb_install)\n+\n PHONY += $(subdirs)\n $(subdirs):\n \t$(Q)$(MAKE) $(dtbinst)=$@ dst=$(patsubst $(obj)/%,$(dst)/%,$@)\ndiff --git a/scripts/Makefile.lib b/scripts/Makefile.lib\nindex 94133708889d..9c0df5bde46c 100644\n--- a/scripts/Makefile.lib\n+++ b/scripts/Makefile.lib\n@@ -281,6 +281,7 @@ DTC_FLAGS += -Wno-interrupt_provider\n ifeq ($(findstring 1,$(KBUILD_EXTRA_WARN)),)\n DTC_FLAGS += -Wno-unit_address_vs_reg \\\n \t-Wno-unit_address_format \\\n+\t-Wno-gpios_property \\\n \t-Wno-avoid_unnecessary_addr_size \\\n \t-Wno-alias_paths \\\n \t-Wno-graph_child_address \\\n@@ -341,6 +342,18 @@ endef\n $(obj)/%.dt.yaml: $(src)/%.dts $(DTC) $(DT_TMP_SCHEMA) FORCE\n \t$(call if_changed_rule,dtc,yaml)\n \n+quiet_cmd_dtco = DTCO    $@\n+cmd_dtco = mkdir -p $(dir ${dtc-tmp}) ; \\\n+\t$(CPP) $(dtc_cpp_flags) -x assembler-with-cpp -o $(dtc-tmp) $< ; \\\n+\t$(DTC) -@ -H epapr -O dtb -o $@ -b 0 \\\n+\t\t-i $(dir $<) $(DTC_FLAGS) \\\n+\t\t-Wno-interrupts_property \\\n+\t\t-d $(depfile).dtc.tmp $(dtc-tmp) ; \\\n+\tcat $(depfile).pre.tmp $(depfile).dtc.tmp > $(depfile)\n+\n+$(obj)/%.dtbo: $(src)/%-overlay.dts FORCE\n+\t$(call if_changed_dep,dtco)\n+\n dtc-tmp = $(subst $(comma),_,$(dot-target).dts.tmp)\n \n # Bzip2\n-- \n2.30.2\n\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0055-BCM270x_DT-Add-pwr_led-and-the-required-input-trigge.patch",
    "content": "From 3bb38201fc6c1aef7709c3c744824db23f06c629 Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.org>\nDate: Fri, 6 Feb 2015 13:50:57 +0000\nSubject: [PATCH] BCM270x_DT: Add pwr_led, and the required \"input\"\n trigger\n\nThe \"input\" trigger makes the associated GPIO an input.  This is to support\nthe Raspberry Pi PWR LED, which is driven by external hardware in normal use.\n\nN.B. pwr_led is not available on Model A or B boards.\n\nleds-gpio: Implement the brightness_get method\n\nThe power LED uses some clever logic that means it is driven\nby a voltage measuring circuit when configured as input, otherwise\nit is driven by the GPIO output value. This patch wires up the\nbrightness_get method for leds-gpio so that user-space can monitor\nthe LED value via /sys/class/gpio/led1/brightness. Using the input\ntrigger this returns an indication of the system power health,\notherwise it is just whatever value the trigger has written most\nrecently.\n\nSee: https://github.com/raspberrypi/linux/issues/1064\n---\n drivers/leds/leds-gpio.c             | 17 ++++++++-\n drivers/leds/trigger/Kconfig         |  7 ++++\n drivers/leds/trigger/Makefile        |  1 +\n drivers/leds/trigger/ledtrig-input.c | 55 ++++++++++++++++++++++++++++\n include/linux/leds.h                 |  3 ++\n 5 files changed, 82 insertions(+), 1 deletion(-)\n create mode 100644 drivers/leds/trigger/ledtrig-input.c\n\n--- a/drivers/leds/leds-gpio.c\n+++ b/drivers/leds/leds-gpio.c\n@@ -46,8 +46,15 @@ static void gpio_led_set(struct led_clas\n \t\tled_dat->platform_gpio_blink_set(led_dat->gpiod, level,\n \t\t\t\t\t\t NULL, NULL);\n \t\tled_dat->blinking = 0;\n+\t} else if (led_dat->cdev.flags & SET_GPIO_INPUT) {\n+\t\tgpiod_direction_input(led_dat->gpiod);\n+\t\tled_dat->cdev.flags &= ~SET_GPIO_INPUT;\n+\t} else if (led_dat->cdev.flags & SET_GPIO_OUTPUT) {\n+\t\tgpiod_direction_output(led_dat->gpiod, level);\n+\t\tled_dat->cdev.flags &= ~SET_GPIO_OUTPUT;\n \t} else {\n-\t\tif (led_dat->can_sleep)\n+\t\tif (led_dat->can_sleep ||\n+\t\t\t(led_dat->cdev.flags & (SET_GPIO_INPUT | SET_GPIO_OUTPUT) ))\n \t\t\tgpiod_set_value_cansleep(led_dat->gpiod, level);\n \t\telse\n \t\t\tgpiod_set_value(led_dat->gpiod, level);\n@@ -61,6 +68,13 @@ static int gpio_led_set_blocking(struct\n \treturn 0;\n }\n \n+static enum led_brightness gpio_led_get(struct led_classdev *led_cdev)\n+{\n+\tstruct gpio_led_data *led_dat =\n+\t\tcontainer_of(led_cdev, struct gpio_led_data, cdev);\n+\treturn gpiod_get_value_cansleep(led_dat->gpiod) ? LED_FULL : LED_OFF;\n+}\n+\n static int gpio_blink_set(struct led_classdev *led_cdev,\n \tunsigned long *delay_on, unsigned long *delay_off)\n {\n@@ -89,6 +103,7 @@ static int create_gpio_led(const struct\n \t\tled_dat->platform_gpio_blink_set = blink_set;\n \t\tled_dat->cdev.blink_set = gpio_blink_set;\n \t}\n+\tled_dat->cdev.brightness_get = gpio_led_get;\n \tif (template->default_state == LEDS_GPIO_DEFSTATE_KEEP) {\n \t\tstate = gpiod_get_value_cansleep(led_dat->gpiod);\n \t\tif (state < 0)\n--- a/drivers/leds/trigger/Kconfig\n+++ b/drivers/leds/trigger/Kconfig\n@@ -114,6 +114,13 @@ config LEDS_TRIGGER_CAMERA\n \t  This enables direct flash/torch on/off by the driver, kernel space.\n \t  If unsure, say Y.\n \n+config LEDS_TRIGGER_INPUT\n+\ttristate \"LED Input Trigger\"\n+\tdepends on LEDS_TRIGGERS\n+\thelp\n+\t  This allows the GPIOs assigned to be LEDs to be initialised to inputs.\n+\t  If unsure, say Y.\n+\n config LEDS_TRIGGER_PANIC\n \tbool \"LED Panic Trigger\"\n \thelp\n--- a/drivers/leds/trigger/Makefile\n+++ b/drivers/leds/trigger/Makefile\n@@ -11,6 +11,7 @@ obj-$(CONFIG_LEDS_TRIGGER_ACTIVITY)\t+= l\n obj-$(CONFIG_LEDS_TRIGGER_DEFAULT_ON)\t+= ledtrig-default-on.o\n obj-$(CONFIG_LEDS_TRIGGER_TRANSIENT)\t+= ledtrig-transient.o\n obj-$(CONFIG_LEDS_TRIGGER_CAMERA)\t+= ledtrig-camera.o\n+obj-$(CONFIG_LEDS_TRIGGER_INPUT)\t+= ledtrig-input.o\n obj-$(CONFIG_LEDS_TRIGGER_PANIC)\t+= ledtrig-panic.o\n obj-$(CONFIG_LEDS_TRIGGER_NETDEV)\t+= ledtrig-netdev.o\n obj-$(CONFIG_LEDS_TRIGGER_PATTERN)\t+= ledtrig-pattern.o\n--- /dev/null\n+++ b/drivers/leds/trigger/ledtrig-input.c\n@@ -0,0 +1,55 @@\n+/*\n+ * Set LED GPIO to Input \"Trigger\"\n+ *\n+ * Copyright 2015 Phil Elwell <phil@raspberrypi.org>\n+ *\n+ * Based on Nick Forbes's ledtrig-default-on.c.\n+ *\n+ * This program is free software; you can redistribute it and/or modify\n+ * it under the terms of the GNU General Public License version 2 as\n+ * published by the Free Software Foundation.\n+ *\n+ */\n+\n+#include <linux/module.h>\n+#include <linux/kernel.h>\n+#include <linux/init.h>\n+#include <linux/leds.h>\n+#include <linux/gpio.h>\n+#include \"../leds.h\"\n+\n+static int input_trig_activate(struct led_classdev *led_cdev)\n+{\n+\tled_cdev->flags |= SET_GPIO_INPUT;\n+\tled_set_brightness(led_cdev, 0);\n+\treturn 0;\n+}\n+\n+static void input_trig_deactivate(struct led_classdev *led_cdev)\n+{\n+\tled_cdev->flags |= SET_GPIO_OUTPUT;\n+\tled_set_brightness(led_cdev, 0);\n+}\n+\n+static struct led_trigger input_led_trigger = {\n+\t.name     = \"input\",\n+\t.activate = input_trig_activate,\n+\t.deactivate = input_trig_deactivate,\n+};\n+\n+static int __init input_trig_init(void)\n+{\n+\treturn led_trigger_register(&input_led_trigger);\n+}\n+\n+static void __exit input_trig_exit(void)\n+{\n+\tled_trigger_unregister(&input_led_trigger);\n+}\n+\n+module_init(input_trig_init);\n+module_exit(input_trig_exit);\n+\n+MODULE_AUTHOR(\"Phil Elwell <phil@raspberrypi.org>\");\n+MODULE_DESCRIPTION(\"Set LED GPIO to Input \\\"trigger\\\"\");\n+MODULE_LICENSE(\"GPL\");\n--- a/include/linux/leds.h\n+++ b/include/linux/leds.h\n@@ -79,6 +79,9 @@ struct led_classdev {\n #define LED_BRIGHT_HW_CHANGED\tBIT(21)\n #define LED_RETAIN_AT_SHUTDOWN\tBIT(22)\n #define LED_INIT_DEFAULT_TRIGGER BIT(23)\n+\t/* Additions for Raspberry Pi PWR LED */\n+#define SET_GPIO_INPUT\t\tBIT(30)\n+#define SET_GPIO_OUTPUT\t\tBIT(31)\n \n \t/* set_brightness_work / blink_timer flags, atomic, private. */\n \tunsigned long\t\twork_flags;\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0056-Added-Device-IDs-for-August-DVB-T-205.patch",
    "content": "From 6bfe5935985ffc3b5365877db6e8b90ba4924540 Mon Sep 17 00:00:00 2001\nFrom: popcornmix <popcornmix@gmail.com>\nDate: Wed, 3 Jul 2013 00:54:08 +0100\nSubject: [PATCH] Added Device IDs for August DVB-T 205\n\n---\n drivers/media/usb/dvb-usb-v2/rtl28xxu.c | 4 ++++\n 1 file changed, 4 insertions(+)\n\n--- a/drivers/media/usb/dvb-usb-v2/rtl28xxu.c\n+++ b/drivers/media/usb/dvb-usb-v2/rtl28xxu.c\n@@ -1953,6 +1953,10 @@ static const struct usb_device_id rtl28x\n \t\t&rtl28xxu_props, \"Compro VideoMate U650F\", NULL) },\n \t{ DVB_USB_DEVICE(USB_VID_KWORLD_2, 0xd394,\n \t\t&rtl28xxu_props, \"MaxMedia HU394-T\", NULL) },\n+\t{ DVB_USB_DEVICE(USB_VID_GTEK, 0xb803 /*USB_PID_AUGUST_DVBT205*/,\n+\t\t&rtl28xxu_props, \"August DVB-T 205\", NULL) },\n+\t{ DVB_USB_DEVICE(USB_VID_GTEK, 0xa803 /*USB_PID_AUGUST_DVBT205*/,\n+\t\t&rtl28xxu_props, \"August DVB-T 205\", NULL) },\n \t{ DVB_USB_DEVICE(USB_VID_LEADTEK, 0x6a03,\n \t\t&rtl28xxu_props, \"Leadtek WinFast DTV Dongle mini\", NULL) },\n \t{ DVB_USB_DEVICE(USB_VID_GTEK, USB_PID_CPYTO_REDI_PC50A,\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0057-Improve-__copy_to_user-and-__copy_from_user-performa.patch",
    "content": "From a013e78cd135c415124496edd439b1031102c33c Mon Sep 17 00:00:00 2001\nFrom: popcornmix <popcornmix@gmail.com>\nDate: Mon, 28 Nov 2016 16:50:04 +0000\nSubject: [PATCH] Improve __copy_to_user and __copy_from_user\n performance\n\nProvide a __copy_from_user that uses memcpy. On BCM2708, use\noptimised memcpy/memmove/memcmp/memset implementations.\n\narch/arm: Add mmiocpy/set aliases for memcpy/set\n\nSee: https://github.com/raspberrypi/linux/issues/1082\n\ncopy_from_user: CPU_SW_DOMAIN_PAN compatibility\n\nThe downstream copy_from_user acceleration must also play nice with\nCONFIG_CPU_SW_DOMAIN_PAN.\n\nSee: https://github.com/raspberrypi/linux/issues/1381\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.org>\n\nFix copy_from_user if BCM2835_FAST_MEMCPY=n\n\nThe change which introduced CONFIG_BCM2835_FAST_MEMCPY unconditionally\nchanged the behaviour of arm_copy_from_user. The page pinning code\nis not safe on ARMv7 if LPAE & high memory is enabled and causes\ncrashes which look like PTE corruption.\n\nMake __copy_from_user_memcpy conditional on CONFIG_2835_FAST_MEMCPY=y\nwhich is really an ARMv6 / Pi1 optimization and not necessary on newer\nARM processors.\n\narm: fix mmap unlocks in uaccess_with_memcpy.c\n\nThis is a regression that was added with the commit 192a4e923ef092924dd013e7326f2ec520ee4783 as of rpi-5.8.y, since that is when the move to the mmap locking API was introduced - d8ed45c5dcd455fc5848d47f86883a1b872ac0d0\n\nThe issue is that when the patch to improve performance for the __copy_to_user and __copy_from_user functions were added for the Raspberry Pi, some of the mmaps were incorrectly mapped to write instead of read. This would cause a verity of issues, and in my case, prevent the booting of a squashfs filesystem on rpi-5.8-y and above. An example of the panic you would see from this can be seen at https://pastebin.com/raw/jBz5xCzL\n\nSigned-off-by: Christian Lamparter <chunkeey@gmail.com>\nSigned-off-by: Christopher Blake <chrisrblake93@gmail.com>\n---\n arch/arm/include/asm/string.h      |   5 +\n arch/arm/include/asm/uaccess.h     |   3 +\n arch/arm/lib/Makefile              |  14 +-\n arch/arm/lib/arm-mem.h             | 159 +++++++++\n arch/arm/lib/copy_from_user.S      |   4 +-\n arch/arm/lib/exports_rpi.c         |  37 +++\n arch/arm/lib/memcmp_rpi.S          | 285 ++++++++++++++++\n arch/arm/lib/memcpy_rpi.S          |  61 ++++\n arch/arm/lib/memcpymove.h          | 506 +++++++++++++++++++++++++++++\n arch/arm/lib/memmove_rpi.S         |  61 ++++\n arch/arm/lib/memset_rpi.S          | 128 ++++++++\n arch/arm/lib/uaccess_with_memcpy.c | 130 +++++++-\n arch/arm/mach-bcm/Kconfig          |   7 +\n 13 files changed, 1394 insertions(+), 6 deletions(-)\n create mode 100644 arch/arm/lib/arm-mem.h\n create mode 100644 arch/arm/lib/exports_rpi.c\n create mode 100644 arch/arm/lib/memcmp_rpi.S\n create mode 100644 arch/arm/lib/memcpy_rpi.S\n create mode 100644 arch/arm/lib/memcpymove.h\n create mode 100644 arch/arm/lib/memmove_rpi.S\n create mode 100644 arch/arm/lib/memset_rpi.S\n\n--- a/arch/arm/include/asm/string.h\n+++ b/arch/arm/include/asm/string.h\n@@ -39,4 +39,9 @@ static inline void *memset64(uint64_t *p\n \treturn __memset64(p, v, n * 8, v >> 32);\n }\n \n+#ifdef CONFIG_BCM2835_FAST_MEMCPY\n+#define __HAVE_ARCH_MEMCMP\n+extern int memcmp(const void *, const void *, size_t);\n+#endif\n+\n #endif\n--- a/arch/arm/include/asm/uaccess.h\n+++ b/arch/arm/include/asm/uaccess.h\n@@ -518,6 +518,9 @@ do {\t\t\t\t\t\t\t\t\t\\\n extern unsigned long __must_check\n arm_copy_from_user(void *to, const void __user *from, unsigned long n);\n \n+extern unsigned long __must_check\n+__copy_from_user_std(void *to, const void __user *from, unsigned long n);\n+\n static inline unsigned long __must_check\n raw_copy_from_user(void *to, const void __user *from, unsigned long n)\n {\n--- a/arch/arm/lib/Makefile\n+++ b/arch/arm/lib/Makefile\n@@ -7,8 +7,8 @@\n \n lib-y\t\t:= changebit.o csumipv6.o csumpartial.o               \\\n \t\t   csumpartialcopy.o csumpartialcopyuser.o clearbit.o \\\n-\t\t   delay.o delay-loop.o findbit.o memchr.o memcpy.o   \\\n-\t\t   memmove.o memset.o setbit.o                        \\\n+\t\t   delay.o delay-loop.o findbit.o memchr.o            \\\n+\t\t   setbit.o                                           \\\n \t\t   strchr.o strrchr.o                                 \\\n \t\t   testchangebit.o testclearbit.o testsetbit.o        \\\n \t\t   ashldi3.o ashrdi3.o lshrdi3.o muldi3.o             \\\n@@ -25,6 +25,16 @@ else\n   lib-y\t+= backtrace.o\n endif\n \n+# Choose optimised implementations for Raspberry Pi\n+ifeq ($(CONFIG_BCM2835_FAST_MEMCPY),y)\n+  CFLAGS_uaccess_with_memcpy.o += -DCOPY_FROM_USER_THRESHOLD=1600\n+  CFLAGS_uaccess_with_memcpy.o += -DCOPY_TO_USER_THRESHOLD=672\n+  obj-$(CONFIG_MODULES) += exports_rpi.o\n+  lib-y        += memcpy_rpi.o memmove_rpi.o memset_rpi.o memcmp_rpi.o\n+else\n+  lib-y        += memcpy.o memmove.o memset.o\n+endif\n+\n # using lib_ here won't override already available weak symbols\n obj-$(CONFIG_UACCESS_WITH_MEMCPY) += uaccess_with_memcpy.o\n \n--- /dev/null\n+++ b/arch/arm/lib/arm-mem.h\n@@ -0,0 +1,159 @@\n+/*\n+Copyright (c) 2013, Raspberry Pi Foundation\n+Copyright (c) 2013, RISC OS Open Ltd\n+All rights reserved.\n+\n+Redistribution and use in source and binary forms, with or without\n+modification, are permitted provided that the following conditions are met:\n+    * Redistributions of source code must retain the above copyright\n+      notice, this list of conditions and the following disclaimer.\n+    * Redistributions in binary form must reproduce the above copyright\n+      notice, this list of conditions and the following disclaimer in the\n+      documentation and/or other materials provided with the distribution.\n+    * Neither the name of the copyright holder nor the\n+      names of its contributors may be used to endorse or promote products\n+      derived from this software without specific prior written permission.\n+\n+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" AND\n+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY\n+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\n+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+*/\n+\n+.macro myfunc fname\n+ .func fname\n+ .global fname\n+fname:\n+.endm\n+\n+.macro preload_leading_step1  backwards, ptr, base\n+/* If the destination is already 16-byte aligned, then we need to preload\n+ * between 0 and prefetch_distance (inclusive) cache lines ahead so there\n+ * are no gaps when the inner loop starts.\n+ */\n+ .if backwards\n+        sub     ptr, base, #1\n+        bic     ptr, ptr, #31\n+ .else\n+        bic     ptr, base, #31\n+ .endif\n+ .set OFFSET, 0\n+ .rept prefetch_distance+1\n+        pld     [ptr, #OFFSET]\n+  .if backwards\n+   .set OFFSET, OFFSET-32\n+  .else\n+   .set OFFSET, OFFSET+32\n+  .endif\n+ .endr\n+.endm\n+\n+.macro preload_leading_step2  backwards, ptr, base, leading_bytes, tmp\n+/* However, if the destination is not 16-byte aligned, we may need to\n+ * preload one more cache line than that. The question we need to ask is:\n+ * are the leading bytes more than the amount by which the source\n+ * pointer will be rounded down for preloading, and if so, by how many\n+ * cache lines?\n+ */\n+ .if backwards\n+/* Here we compare against how many bytes we are into the\n+ * cache line, counting down from the highest such address.\n+ * Effectively, we want to calculate\n+ *     leading_bytes = dst&15\n+ *     cacheline_offset = 31-((src-leading_bytes-1)&31)\n+ *     extra_needed = leading_bytes - cacheline_offset\n+ * and test if extra_needed is <= 0, or rearranging:\n+ *     leading_bytes + (src-leading_bytes-1)&31 <= 31\n+ */\n+        mov     tmp, base, lsl #32-5\n+        sbc     tmp, tmp, leading_bytes, lsl #32-5\n+        adds    tmp, tmp, leading_bytes, lsl #32-5\n+        bcc     61f\n+        pld     [ptr, #-32*(prefetch_distance+1)]\n+ .else\n+/* Effectively, we want to calculate\n+ *     leading_bytes = (-dst)&15\n+ *     cacheline_offset = (src+leading_bytes)&31\n+ *     extra_needed = leading_bytes - cacheline_offset\n+ * and test if extra_needed is <= 0.\n+ */\n+        mov     tmp, base, lsl #32-5\n+        add     tmp, tmp, leading_bytes, lsl #32-5\n+        rsbs    tmp, tmp, leading_bytes, lsl #32-5\n+        bls     61f\n+        pld     [ptr, #32*(prefetch_distance+1)]\n+ .endif\n+61:\n+.endm\n+\n+.macro preload_trailing  backwards, base, remain, tmp\n+        /* We need either 0, 1 or 2 extra preloads */\n+ .if backwards\n+        rsb     tmp, base, #0\n+        mov     tmp, tmp, lsl #32-5\n+ .else\n+        mov     tmp, base, lsl #32-5\n+ .endif\n+        adds    tmp, tmp, remain, lsl #32-5\n+        adceqs  tmp, tmp, #0\n+        /* The instruction above has two effects: ensures Z is only\n+         * set if C was clear (so Z indicates that both shifted quantities\n+         * were 0), and clears C if Z was set (so C indicates that the sum\n+         * of the shifted quantities was greater and not equal to 32) */\n+        beq     82f\n+ .if backwards\n+        sub     tmp, base, #1\n+        bic     tmp, tmp, #31\n+ .else\n+        bic     tmp, base, #31\n+ .endif\n+        bcc     81f\n+ .if backwards\n+        pld     [tmp, #-32*(prefetch_distance+1)]\n+81:\n+        pld     [tmp, #-32*prefetch_distance]\n+ .else\n+        pld     [tmp, #32*(prefetch_distance+2)]\n+81:\n+        pld     [tmp, #32*(prefetch_distance+1)]\n+ .endif\n+82:\n+.endm\n+\n+.macro preload_all    backwards, narrow_case, shift, base, remain, tmp0, tmp1\n+ .if backwards\n+        sub     tmp0, base, #1\n+        bic     tmp0, tmp0, #31\n+        pld     [tmp0]\n+        sub     tmp1, base, remain, lsl #shift\n+ .else\n+        bic     tmp0, base, #31\n+        pld     [tmp0]\n+        add     tmp1, base, remain, lsl #shift\n+        sub     tmp1, tmp1, #1\n+ .endif\n+        bic     tmp1, tmp1, #31\n+        cmp     tmp1, tmp0\n+        beq     92f\n+ .if narrow_case\n+        /* In this case, all the data fits in either 1 or 2 cache lines */\n+        pld     [tmp1]\n+ .else\n+91:\n+  .if backwards\n+        sub     tmp0, tmp0, #32\n+  .else\n+        add     tmp0, tmp0, #32\n+  .endif\n+        cmp     tmp0, tmp1\n+        pld     [tmp0]\n+        bne     91b\n+ .endif\n+92:\n+.endm\n--- a/arch/arm/lib/copy_from_user.S\n+++ b/arch/arm/lib/copy_from_user.S\n@@ -107,7 +107,8 @@\n \n \t.text\n \n-ENTRY(arm_copy_from_user)\n+ENTRY(__copy_from_user_std)\n+WEAK(arm_copy_from_user)\n #ifdef CONFIG_CPU_SPECTRE\n \tget_thread_info r3\n \tldr\tr3, [r3, #TI_ADDR_LIMIT]\n@@ -117,6 +118,7 @@ ENTRY(arm_copy_from_user)\n #include \"copy_template.S\"\n \n ENDPROC(arm_copy_from_user)\n+ENDPROC(__copy_from_user_std)\n \n \t.pushsection .text.fixup,\"ax\"\n \t.align 0\n--- /dev/null\n+++ b/arch/arm/lib/exports_rpi.c\n@@ -0,0 +1,37 @@\n+/**\n+ * Copyright (c) 2014, Raspberry Pi (Trading) Ltd.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ * 1. Redistributions of source code must retain the above copyright\n+ *    notice, this list of conditions, and the following disclaimer,\n+ *    without modification.\n+ * 2. Redistributions in binary form must reproduce the above copyright\n+ *    notice, this list of conditions and the following disclaimer in the\n+ *    documentation and/or other materials provided with the distribution.\n+ * 3. The names of the above-listed copyright holders may not be used\n+ *    to endorse or promote products derived from this software without\n+ *    specific prior written permission.\n+ *\n+ * ALTERNATIVELY, this software may be distributed under the terms of the\n+ * GNU General Public License (\"GPL\") version 2, as published by the Free\n+ * Software Foundation.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS\n+ * IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,\n+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\n+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR\n+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\n+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\n+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR\n+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\n+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\n+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+#include <linux/kernel.h>\n+#include <linux/module.h>\n+\n+EXPORT_SYMBOL(memcmp);\n--- /dev/null\n+++ b/arch/arm/lib/memcmp_rpi.S\n@@ -0,0 +1,285 @@\n+/*\n+Copyright (c) 2013, Raspberry Pi Foundation\n+Copyright (c) 2013, RISC OS Open Ltd\n+All rights reserved.\n+\n+Redistribution and use in source and binary forms, with or without\n+modification, are permitted provided that the following conditions are met:\n+    * Redistributions of source code must retain the above copyright\n+      notice, this list of conditions and the following disclaimer.\n+    * Redistributions in binary form must reproduce the above copyright\n+      notice, this list of conditions and the following disclaimer in the\n+      documentation and/or other materials provided with the distribution.\n+    * Neither the name of the copyright holder nor the\n+      names of its contributors may be used to endorse or promote products\n+      derived from this software without specific prior written permission.\n+\n+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" AND\n+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY\n+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\n+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+*/\n+\n+#include <linux/linkage.h>\n+#include \"arm-mem.h\"\n+\n+/* Prevent the stack from becoming executable */\n+#if defined(__linux__) && defined(__ELF__)\n+.section .note.GNU-stack,\"\",%progbits\n+#endif\n+\n+    .text\n+    .arch armv6\n+    .object_arch armv4\n+    .arm\n+    .altmacro\n+    .p2align 2\n+\n+.macro memcmp_process_head  unaligned\n+ .if unaligned\n+        ldr     DAT0, [S_1], #4\n+        ldr     DAT1, [S_1], #4\n+        ldr     DAT2, [S_1], #4\n+        ldr     DAT3, [S_1], #4\n+ .else\n+        ldmia   S_1!, {DAT0, DAT1, DAT2, DAT3}\n+ .endif\n+        ldmia   S_2!, {DAT4, DAT5, DAT6, DAT7}\n+.endm\n+\n+.macro memcmp_process_tail\n+        cmp     DAT0, DAT4\n+        cmpeq   DAT1, DAT5\n+        cmpeq   DAT2, DAT6\n+        cmpeq   DAT3, DAT7\n+        bne     200f\n+.endm\n+\n+.macro memcmp_leading_31bytes\n+        movs    DAT0, OFF, lsl #31\n+        ldrmib  DAT0, [S_1], #1\n+        ldrcsh  DAT1, [S_1], #2\n+        ldrmib  DAT4, [S_2], #1\n+        ldrcsh  DAT5, [S_2], #2\n+        movpl   DAT0, #0\n+        movcc   DAT1, #0\n+        movpl   DAT4, #0\n+        movcc   DAT5, #0\n+        submi   N, N, #1\n+        subcs   N, N, #2\n+        cmp     DAT0, DAT4\n+        cmpeq   DAT1, DAT5\n+        bne     200f\n+        movs    DAT0, OFF, lsl #29\n+        ldrmi   DAT0, [S_1], #4\n+        ldrcs   DAT1, [S_1], #4\n+        ldrcs   DAT2, [S_1], #4\n+        ldrmi   DAT4, [S_2], #4\n+        ldmcsia S_2!, {DAT5, DAT6}\n+        movpl   DAT0, #0\n+        movcc   DAT1, #0\n+        movcc   DAT2, #0\n+        movpl   DAT4, #0\n+        movcc   DAT5, #0\n+        movcc   DAT6, #0\n+        submi   N, N, #4\n+        subcs   N, N, #8\n+        cmp     DAT0, DAT4\n+        cmpeq   DAT1, DAT5\n+        cmpeq   DAT2, DAT6\n+        bne     200f\n+        tst     OFF, #16\n+        beq     105f\n+        memcmp_process_head  1\n+        sub     N, N, #16\n+        memcmp_process_tail\n+105:\n+.endm\n+\n+.macro memcmp_trailing_15bytes  unaligned\n+        movs    N, N, lsl #29\n+ .if unaligned\n+        ldrcs   DAT0, [S_1], #4\n+        ldrcs   DAT1, [S_1], #4\n+ .else\n+        ldmcsia S_1!, {DAT0, DAT1}\n+ .endif\n+        ldrmi   DAT2, [S_1], #4\n+        ldmcsia S_2!, {DAT4, DAT5}\n+        ldrmi   DAT6, [S_2], #4\n+        movcc   DAT0, #0\n+        movcc   DAT1, #0\n+        movpl   DAT2, #0\n+        movcc   DAT4, #0\n+        movcc   DAT5, #0\n+        movpl   DAT6, #0\n+        cmp     DAT0, DAT4\n+        cmpeq   DAT1, DAT5\n+        cmpeq   DAT2, DAT6\n+        bne     200f\n+        movs    N, N, lsl #2\n+        ldrcsh  DAT0, [S_1], #2\n+        ldrmib  DAT1, [S_1]\n+        ldrcsh  DAT4, [S_2], #2\n+        ldrmib  DAT5, [S_2]\n+        movcc   DAT0, #0\n+        movpl   DAT1, #0\n+        movcc   DAT4, #0\n+        movpl   DAT5, #0\n+        cmp     DAT0, DAT4\n+        cmpeq   DAT1, DAT5\n+        bne     200f\n+.endm\n+\n+.macro memcmp_long_inner_loop  unaligned\n+110:\n+        memcmp_process_head  unaligned\n+        pld     [S_2, #prefetch_distance*32 + 16]\n+        memcmp_process_tail\n+        memcmp_process_head  unaligned\n+        pld     [S_1, OFF]\n+        memcmp_process_tail\n+        subs    N, N, #32\n+        bhs     110b\n+        /* Just before the final (prefetch_distance+1) 32-byte blocks,\n+         * deal with final preloads */\n+        preload_trailing  0, S_1, N, DAT0\n+        preload_trailing  0, S_2, N, DAT0\n+        add     N, N, #(prefetch_distance+2)*32 - 16\n+120:\n+        memcmp_process_head  unaligned\n+        memcmp_process_tail\n+        subs    N, N, #16\n+        bhs     120b\n+        /* Trailing words and bytes */\n+        tst     N, #15\n+        beq     199f\n+        memcmp_trailing_15bytes  unaligned\n+199:    /* Reached end without detecting a difference */\n+        mov     a1, #0\n+        setend  le\n+        pop     {DAT1-DAT6, pc}\n+.endm\n+\n+.macro memcmp_short_inner_loop  unaligned\n+        subs    N, N, #16     /* simplifies inner loop termination */\n+        blo     122f\n+120:\n+        memcmp_process_head  unaligned\n+        memcmp_process_tail\n+        subs    N, N, #16\n+        bhs     120b\n+122:    /* Trailing words and bytes */\n+        tst     N, #15\n+        beq     199f\n+        memcmp_trailing_15bytes  unaligned\n+199:    /* Reached end without detecting a difference */\n+        mov     a1, #0\n+        setend  le\n+        pop     {DAT1-DAT6, pc}\n+.endm\n+\n+/*\n+ * int memcmp(const void *s1, const void *s2, size_t n);\n+ * On entry:\n+ * a1 = pointer to buffer 1\n+ * a2 = pointer to buffer 2\n+ * a3 = number of bytes to compare (as unsigned chars)\n+ * On exit:\n+ * a1 = >0/=0/<0 if s1 >/=/< s2\n+ */\n+\n+.set prefetch_distance, 2\n+\n+ENTRY(memcmp)\n+        S_1     .req    a1\n+        S_2     .req    a2\n+        N       .req    a3\n+        DAT0    .req    a4\n+        DAT1    .req    v1\n+        DAT2    .req    v2\n+        DAT3    .req    v3\n+        DAT4    .req    v4\n+        DAT5    .req    v5\n+        DAT6    .req    v6\n+        DAT7    .req    ip\n+        OFF     .req    lr\n+\n+        push    {DAT1-DAT6, lr}\n+        setend  be /* lowest-addressed bytes are most significant */\n+\n+        /* To preload ahead as we go, we need at least (prefetch_distance+2) 32-byte blocks */\n+        cmp     N, #(prefetch_distance+3)*32 - 1\n+        blo     170f\n+\n+        /* Long case */\n+        /* Adjust N so that the decrement instruction can also test for\n+         * inner loop termination. We want it to stop when there are\n+         * (prefetch_distance+1) complete blocks to go. */\n+        sub     N, N, #(prefetch_distance+2)*32\n+        preload_leading_step1  0, DAT0, S_1\n+        preload_leading_step1  0, DAT1, S_2\n+        tst     S_2, #31\n+        beq     154f\n+        rsb     OFF, S_2, #0 /* no need to AND with 15 here */\n+        preload_leading_step2  0, DAT0, S_1, OFF, DAT2\n+        preload_leading_step2  0, DAT1, S_2, OFF, DAT2\n+        memcmp_leading_31bytes\n+154:    /* Second source now cacheline (32-byte) aligned; we have at\n+         * least one prefetch to go. */\n+        /* Prefetch offset is best selected such that it lies in the\n+         * first 8 of each 32 bytes - but it's just as easy to aim for\n+         * the first one */\n+        and     OFF, S_1, #31\n+        rsb     OFF, OFF, #32*prefetch_distance\n+        tst     S_1, #3\n+        bne     140f\n+        memcmp_long_inner_loop  0\n+140:    memcmp_long_inner_loop  1\n+\n+170:    /* Short case */\n+        teq     N, #0\n+        beq     199f\n+        preload_all 0, 0, 0, S_1, N, DAT0, DAT1\n+        preload_all 0, 0, 0, S_2, N, DAT0, DAT1\n+        tst     S_2, #3\n+        beq     174f\n+172:    subs    N, N, #1\n+        blo     199f\n+        ldrb    DAT0, [S_1], #1\n+        ldrb    DAT4, [S_2], #1\n+        cmp     DAT0, DAT4\n+        bne     200f\n+        tst     S_2, #3\n+        bne     172b\n+174:    /* Second source now 4-byte aligned; we have 0 or more bytes to go */\n+        tst     S_1, #3\n+        bne     140f\n+        memcmp_short_inner_loop  0\n+140:    memcmp_short_inner_loop  1\n+\n+200:    /* Difference found: determine sign. */\n+        movhi   a1, #1\n+        movlo   a1, #-1\n+        setend  le\n+        pop     {DAT1-DAT6, pc}\n+\n+        .unreq  S_1\n+        .unreq  S_2\n+        .unreq  N\n+        .unreq  DAT0\n+        .unreq  DAT1\n+        .unreq  DAT2\n+        .unreq  DAT3\n+        .unreq  DAT4\n+        .unreq  DAT5\n+        .unreq  DAT6\n+        .unreq  DAT7\n+        .unreq  OFF\n+ENDPROC(memcmp)\n--- /dev/null\n+++ b/arch/arm/lib/memcpy_rpi.S\n@@ -0,0 +1,61 @@\n+/*\n+Copyright (c) 2013, Raspberry Pi Foundation\n+Copyright (c) 2013, RISC OS Open Ltd\n+All rights reserved.\n+\n+Redistribution and use in source and binary forms, with or without\n+modification, are permitted provided that the following conditions are met:\n+    * Redistributions of source code must retain the above copyright\n+      notice, this list of conditions and the following disclaimer.\n+    * Redistributions in binary form must reproduce the above copyright\n+      notice, this list of conditions and the following disclaimer in the\n+      documentation and/or other materials provided with the distribution.\n+    * Neither the name of the copyright holder nor the\n+      names of its contributors may be used to endorse or promote products\n+      derived from this software without specific prior written permission.\n+\n+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" AND\n+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY\n+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\n+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+*/\n+\n+#include <linux/linkage.h>\n+#include \"arm-mem.h\"\n+#include \"memcpymove.h\"\n+\n+/* Prevent the stack from becoming executable */\n+#if defined(__linux__) && defined(__ELF__)\n+.section .note.GNU-stack,\"\",%progbits\n+#endif\n+\n+    .text\n+    .arch armv6\n+    .object_arch armv4\n+    .arm\n+    .altmacro\n+    .p2align 2\n+\n+/*\n+ * void *memcpy(void * restrict s1, const void * restrict s2, size_t n);\n+ * On entry:\n+ * a1 = pointer to destination\n+ * a2 = pointer to source\n+ * a3 = number of bytes to copy\n+ * On exit:\n+ * a1 preserved\n+ */\n+\n+.set prefetch_distance, 3\n+\n+ENTRY(mmiocpy)\n+ENTRY(memcpy)\n+        memcpy  0\n+ENDPROC(memcpy)\n+ENDPROC(mmiocpy)\n--- /dev/null\n+++ b/arch/arm/lib/memcpymove.h\n@@ -0,0 +1,506 @@\n+/*\n+Copyright (c) 2013, Raspberry Pi Foundation\n+Copyright (c) 2013, RISC OS Open Ltd\n+All rights reserved.\n+\n+Redistribution and use in source and binary forms, with or without\n+modification, are permitted provided that the following conditions are met:\n+    * Redistributions of source code must retain the above copyright\n+      notice, this list of conditions and the following disclaimer.\n+    * Redistributions in binary form must reproduce the above copyright\n+      notice, this list of conditions and the following disclaimer in the\n+      documentation and/or other materials provided with the distribution.\n+    * Neither the name of the copyright holder nor the\n+      names of its contributors may be used to endorse or promote products\n+      derived from this software without specific prior written permission.\n+\n+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" AND\n+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY\n+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\n+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+*/\n+\n+.macro unaligned_words  backwards, align, use_pld, words, r0, r1, r2, r3, r4, r5, r6, r7, r8\n+ .if words == 1\n+  .if backwards\n+        mov     r1, r0, lsl #32-align*8\n+        ldr     r0, [S, #-4]!\n+        orr     r1, r1, r0, lsr #align*8\n+        str     r1, [D, #-4]!\n+  .else\n+        mov     r0, r1, lsr #align*8\n+        ldr     r1, [S, #4]!\n+        orr     r0, r0, r1, lsl #32-align*8\n+        str     r0, [D], #4\n+  .endif\n+ .elseif words == 2\n+  .if backwards\n+        ldr     r1, [S, #-4]!\n+        mov     r2, r0, lsl #32-align*8\n+        ldr     r0, [S, #-4]!\n+        orr     r2, r2, r1, lsr #align*8\n+        mov     r1, r1, lsl #32-align*8\n+        orr     r1, r1, r0, lsr #align*8\n+        stmdb   D!, {r1, r2}\n+  .else\n+        ldr     r1, [S, #4]!\n+        mov     r0, r2, lsr #align*8\n+        ldr     r2, [S, #4]!\n+        orr     r0, r0, r1, lsl #32-align*8\n+        mov     r1, r1, lsr #align*8\n+        orr     r1, r1, r2, lsl #32-align*8\n+        stmia   D!, {r0, r1}\n+  .endif\n+ .elseif words == 4\n+  .if backwards\n+        ldmdb   S!, {r2, r3}\n+        mov     r4, r0, lsl #32-align*8\n+        ldmdb   S!, {r0, r1}\n+        orr     r4, r4, r3, lsr #align*8\n+        mov     r3, r3, lsl #32-align*8\n+        orr     r3, r3, r2, lsr #align*8\n+        mov     r2, r2, lsl #32-align*8\n+        orr     r2, r2, r1, lsr #align*8\n+        mov     r1, r1, lsl #32-align*8\n+        orr     r1, r1, r0, lsr #align*8\n+        stmdb   D!, {r1, r2, r3, r4}\n+  .else\n+        ldmib   S!, {r1, r2}\n+        mov     r0, r4, lsr #align*8\n+        ldmib   S!, {r3, r4}\n+        orr     r0, r0, r1, lsl #32-align*8\n+        mov     r1, r1, lsr #align*8\n+        orr     r1, r1, r2, lsl #32-align*8\n+        mov     r2, r2, lsr #align*8\n+        orr     r2, r2, r3, lsl #32-align*8\n+        mov     r3, r3, lsr #align*8\n+        orr     r3, r3, r4, lsl #32-align*8\n+        stmia   D!, {r0, r1, r2, r3}\n+  .endif\n+ .elseif words == 8\n+  .if backwards\n+        ldmdb   S!, {r4, r5, r6, r7}\n+        mov     r8, r0, lsl #32-align*8\n+        ldmdb   S!, {r0, r1, r2, r3}\n+   .if use_pld\n+        pld     [S, OFF]\n+   .endif\n+        orr     r8, r8, r7, lsr #align*8\n+        mov     r7, r7, lsl #32-align*8\n+        orr     r7, r7, r6, lsr #align*8\n+        mov     r6, r6, lsl #32-align*8\n+        orr     r6, r6, r5, lsr #align*8\n+        mov     r5, r5, lsl #32-align*8\n+        orr     r5, r5, r4, lsr #align*8\n+        mov     r4, r4, lsl #32-align*8\n+        orr     r4, r4, r3, lsr #align*8\n+        mov     r3, r3, lsl #32-align*8\n+        orr     r3, r3, r2, lsr #align*8\n+        mov     r2, r2, lsl #32-align*8\n+        orr     r2, r2, r1, lsr #align*8\n+        mov     r1, r1, lsl #32-align*8\n+        orr     r1, r1, r0, lsr #align*8\n+        stmdb   D!, {r5, r6, r7, r8}\n+        stmdb   D!, {r1, r2, r3, r4}\n+  .else\n+        ldmib   S!, {r1, r2, r3, r4}\n+        mov     r0, r8, lsr #align*8\n+        ldmib   S!, {r5, r6, r7, r8}\n+   .if use_pld\n+        pld     [S, OFF]\n+   .endif\n+        orr     r0, r0, r1, lsl #32-align*8\n+        mov     r1, r1, lsr #align*8\n+        orr     r1, r1, r2, lsl #32-align*8\n+        mov     r2, r2, lsr #align*8\n+        orr     r2, r2, r3, lsl #32-align*8\n+        mov     r3, r3, lsr #align*8\n+        orr     r3, r3, r4, lsl #32-align*8\n+        mov     r4, r4, lsr #align*8\n+        orr     r4, r4, r5, lsl #32-align*8\n+        mov     r5, r5, lsr #align*8\n+        orr     r5, r5, r6, lsl #32-align*8\n+        mov     r6, r6, lsr #align*8\n+        orr     r6, r6, r7, lsl #32-align*8\n+        mov     r7, r7, lsr #align*8\n+        orr     r7, r7, r8, lsl #32-align*8\n+        stmia   D!, {r0, r1, r2, r3}\n+        stmia   D!, {r4, r5, r6, r7}\n+  .endif\n+ .endif\n+.endm\n+\n+.macro memcpy_leading_15bytes  backwards, align\n+        movs    DAT1, DAT2, lsl #31\n+        sub     N, N, DAT2\n+ .if backwards\n+        ldrmib  DAT0, [S, #-1]!\n+        ldrcsh  DAT1, [S, #-2]!\n+        strmib  DAT0, [D, #-1]!\n+        strcsh  DAT1, [D, #-2]!\n+ .else\n+        ldrmib  DAT0, [S], #1\n+        ldrcsh  DAT1, [S], #2\n+        strmib  DAT0, [D], #1\n+        strcsh  DAT1, [D], #2\n+ .endif\n+        movs    DAT1, DAT2, lsl #29\n+ .if backwards\n+        ldrmi   DAT0, [S, #-4]!\n+  .if align == 0\n+        ldmcsdb S!, {DAT1, DAT2}\n+  .else\n+        ldrcs   DAT2, [S, #-4]!\n+        ldrcs   DAT1, [S, #-4]!\n+  .endif\n+        strmi   DAT0, [D, #-4]!\n+        stmcsdb D!, {DAT1, DAT2}\n+ .else\n+        ldrmi   DAT0, [S], #4\n+  .if align == 0\n+        ldmcsia S!, {DAT1, DAT2}\n+  .else\n+        ldrcs   DAT1, [S], #4\n+        ldrcs   DAT2, [S], #4\n+  .endif\n+        strmi   DAT0, [D], #4\n+        stmcsia D!, {DAT1, DAT2}\n+ .endif\n+.endm\n+\n+.macro memcpy_trailing_15bytes  backwards, align\n+        movs    N, N, lsl #29\n+ .if backwards\n+  .if align == 0\n+        ldmcsdb S!, {DAT0, DAT1}\n+  .else\n+        ldrcs   DAT1, [S, #-4]!\n+        ldrcs   DAT0, [S, #-4]!\n+  .endif\n+        ldrmi   DAT2, [S, #-4]!\n+        stmcsdb D!, {DAT0, DAT1}\n+        strmi   DAT2, [D, #-4]!\n+ .else\n+  .if align == 0\n+        ldmcsia S!, {DAT0, DAT1}\n+  .else\n+        ldrcs   DAT0, [S], #4\n+        ldrcs   DAT1, [S], #4\n+  .endif\n+        ldrmi   DAT2, [S], #4\n+        stmcsia D!, {DAT0, DAT1}\n+        strmi   DAT2, [D], #4\n+ .endif\n+        movs    N, N, lsl #2\n+ .if backwards\n+        ldrcsh  DAT0, [S, #-2]!\n+        ldrmib  DAT1, [S, #-1]\n+        strcsh  DAT0, [D, #-2]!\n+        strmib  DAT1, [D, #-1]\n+ .else\n+        ldrcsh  DAT0, [S], #2\n+        ldrmib  DAT1, [S]\n+        strcsh  DAT0, [D], #2\n+        strmib  DAT1, [D]\n+ .endif\n+.endm\n+\n+.macro memcpy_long_inner_loop  backwards, align\n+ .if align != 0\n+  .if backwards\n+        ldr     DAT0, [S, #-align]!\n+  .else\n+        ldr     LAST, [S, #-align]!\n+  .endif\n+ .endif\n+110:\n+ .if align == 0\n+  .if backwards\n+        ldmdb   S!, {DAT0, DAT1, DAT2, DAT3, DAT4, DAT5, DAT6, LAST}\n+        pld     [S, OFF]\n+        stmdb   D!, {DAT4, DAT5, DAT6, LAST}\n+        stmdb   D!, {DAT0, DAT1, DAT2, DAT3}\n+  .else\n+        ldmia   S!, {DAT0, DAT1, DAT2, DAT3, DAT4, DAT5, DAT6, LAST}\n+        pld     [S, OFF]\n+        stmia   D!, {DAT0, DAT1, DAT2, DAT3}\n+        stmia   D!, {DAT4, DAT5, DAT6, LAST}\n+  .endif\n+ .else\n+        unaligned_words  backwards, align, 1, 8, DAT0, DAT1, DAT2, DAT3, DAT4, DAT5, DAT6, DAT7, LAST\n+ .endif\n+        subs    N, N, #32\n+        bhs     110b\n+        /* Just before the final (prefetch_distance+1) 32-byte blocks, deal with final preloads */\n+        preload_trailing  backwards, S, N, OFF\n+        add     N, N, #(prefetch_distance+2)*32 - 32\n+120:\n+ .if align == 0\n+  .if backwards\n+        ldmdb   S!, {DAT0, DAT1, DAT2, DAT3, DAT4, DAT5, DAT6, LAST}\n+        stmdb   D!, {DAT4, DAT5, DAT6, LAST}\n+        stmdb   D!, {DAT0, DAT1, DAT2, DAT3}\n+  .else\n+        ldmia   S!, {DAT0, DAT1, DAT2, DAT3, DAT4, DAT5, DAT6, LAST}\n+        stmia   D!, {DAT0, DAT1, DAT2, DAT3}\n+        stmia   D!, {DAT4, DAT5, DAT6, LAST}\n+  .endif\n+ .else\n+        unaligned_words  backwards, align, 0, 8, DAT0, DAT1, DAT2, DAT3, DAT4, DAT5, DAT6, DAT7, LAST\n+ .endif\n+        subs    N, N, #32\n+        bhs     120b\n+        tst     N, #16\n+ .if align == 0\n+  .if backwards\n+        ldmnedb S!, {DAT0, DAT1, DAT2, LAST}\n+        stmnedb D!, {DAT0, DAT1, DAT2, LAST}\n+  .else\n+        ldmneia S!, {DAT0, DAT1, DAT2, LAST}\n+        stmneia D!, {DAT0, DAT1, DAT2, LAST}\n+  .endif\n+ .else\n+        beq     130f\n+        unaligned_words  backwards, align, 0, 4, DAT0, DAT1, DAT2, DAT3, LAST\n+130:\n+ .endif\n+        /* Trailing words and bytes */\n+        tst      N, #15\n+        beq      199f\n+ .if align != 0\n+        add     S, S, #align\n+ .endif\n+        memcpy_trailing_15bytes  backwards, align\n+199:\n+        pop     {DAT3, DAT4, DAT5, DAT6, DAT7}\n+        pop     {D, DAT1, DAT2, pc}\n+.endm\n+\n+.macro memcpy_medium_inner_loop  backwards, align\n+120:\n+ .if backwards\n+  .if align == 0\n+        ldmdb   S!, {DAT0, DAT1, DAT2, LAST}\n+  .else\n+        ldr     LAST, [S, #-4]!\n+        ldr     DAT2, [S, #-4]!\n+        ldr     DAT1, [S, #-4]!\n+        ldr     DAT0, [S, #-4]!\n+  .endif\n+        stmdb   D!, {DAT0, DAT1, DAT2, LAST}\n+ .else\n+  .if align == 0\n+        ldmia   S!, {DAT0, DAT1, DAT2, LAST}\n+  .else\n+        ldr     DAT0, [S], #4\n+        ldr     DAT1, [S], #4\n+        ldr     DAT2, [S], #4\n+        ldr     LAST, [S], #4\n+  .endif\n+        stmia   D!, {DAT0, DAT1, DAT2, LAST}\n+ .endif\n+        subs     N, N, #16\n+        bhs      120b\n+        /* Trailing words and bytes */\n+        tst      N, #15\n+        beq      199f\n+        memcpy_trailing_15bytes  backwards, align\n+199:\n+        pop     {D, DAT1, DAT2, pc}\n+.endm\n+\n+.macro memcpy_short_inner_loop  backwards, align\n+        tst     N, #16\n+ .if backwards\n+  .if align == 0\n+        ldmnedb S!, {DAT0, DAT1, DAT2, LAST}\n+  .else\n+        ldrne   LAST, [S, #-4]!\n+        ldrne   DAT2, [S, #-4]!\n+        ldrne   DAT1, [S, #-4]!\n+        ldrne   DAT0, [S, #-4]!\n+  .endif\n+        stmnedb D!, {DAT0, DAT1, DAT2, LAST}\n+ .else\n+  .if align == 0\n+        ldmneia S!, {DAT0, DAT1, DAT2, LAST}\n+  .else\n+        ldrne   DAT0, [S], #4\n+        ldrne   DAT1, [S], #4\n+        ldrne   DAT2, [S], #4\n+        ldrne   LAST, [S], #4\n+  .endif\n+        stmneia D!, {DAT0, DAT1, DAT2, LAST}\n+ .endif\n+        memcpy_trailing_15bytes  backwards, align\n+199:\n+        pop     {D, DAT1, DAT2, pc}\n+.endm\n+\n+.macro memcpy backwards\n+        D       .req    a1\n+        S       .req    a2\n+        N       .req    a3\n+        DAT0    .req    a4\n+        DAT1    .req    v1\n+        DAT2    .req    v2\n+        DAT3    .req    v3\n+        DAT4    .req    v4\n+        DAT5    .req    v5\n+        DAT6    .req    v6\n+        DAT7    .req    sl\n+        LAST    .req    ip\n+        OFF     .req    lr\n+\n+        .cfi_startproc\n+\n+        push    {D, DAT1, DAT2, lr}\n+\n+        .cfi_def_cfa_offset 16\n+        .cfi_rel_offset D, 0\n+        .cfi_undefined  S\n+        .cfi_undefined  N\n+        .cfi_undefined  DAT0\n+        .cfi_rel_offset DAT1, 4\n+        .cfi_rel_offset DAT2, 8\n+        .cfi_undefined  LAST\n+        .cfi_rel_offset lr, 12\n+\n+ .if backwards\n+        add     D, D, N\n+        add     S, S, N\n+ .endif\n+\n+        /* See if we're guaranteed to have at least one 16-byte aligned 16-byte write */\n+        cmp     N, #31\n+        blo     170f\n+        /* To preload ahead as we go, we need at least (prefetch_distance+2) 32-byte blocks */\n+        cmp     N, #(prefetch_distance+3)*32 - 1\n+        blo     160f\n+\n+        /* Long case */\n+        push    {DAT3, DAT4, DAT5, DAT6, DAT7}\n+\n+        .cfi_def_cfa_offset 36\n+        .cfi_rel_offset D, 20\n+        .cfi_rel_offset DAT1, 24\n+        .cfi_rel_offset DAT2, 28\n+        .cfi_rel_offset DAT3, 0\n+        .cfi_rel_offset DAT4, 4\n+        .cfi_rel_offset DAT5, 8\n+        .cfi_rel_offset DAT6, 12\n+        .cfi_rel_offset DAT7, 16\n+        .cfi_rel_offset lr, 32\n+\n+        /* Adjust N so that the decrement instruction can also test for\n+         * inner loop termination. We want it to stop when there are\n+         * (prefetch_distance+1) complete blocks to go. */\n+        sub     N, N, #(prefetch_distance+2)*32\n+        preload_leading_step1  backwards, DAT0, S\n+ .if backwards\n+        /* Bug in GAS: it accepts, but mis-assembles the instruction\n+         * ands    DAT2, D, #60, 2\n+         * which sets DAT2 to the number of leading bytes until destination is aligned and also clears C (sets borrow)\n+         */\n+        .word   0xE210513C\n+        beq     154f\n+ .else\n+        ands    DAT2, D, #15\n+        beq     154f\n+        rsb     DAT2, DAT2, #16 /* number of leading bytes until destination aligned */\n+ .endif\n+        preload_leading_step2  backwards, DAT0, S, DAT2, OFF\n+        memcpy_leading_15bytes backwards, 1\n+154:    /* Destination now 16-byte aligned; we have at least one prefetch as well as at least one 16-byte output block */\n+        /* Prefetch offset is best selected such that it lies in the first 8 of each 32 bytes - but it's just as easy to aim for the first one */\n+ .if backwards\n+        rsb     OFF, S, #3\n+        and     OFF, OFF, #28\n+        sub     OFF, OFF, #32*(prefetch_distance+1)\n+ .else\n+        and     OFF, S, #28\n+        rsb     OFF, OFF, #32*prefetch_distance\n+ .endif\n+        movs    DAT0, S, lsl #31\n+        bhi     157f\n+        bcs     156f\n+        bmi     155f\n+        memcpy_long_inner_loop  backwards, 0\n+155:    memcpy_long_inner_loop  backwards, 1\n+156:    memcpy_long_inner_loop  backwards, 2\n+157:    memcpy_long_inner_loop  backwards, 3\n+\n+        .cfi_def_cfa_offset 16\n+        .cfi_rel_offset D, 0\n+        .cfi_rel_offset DAT1, 4\n+        .cfi_rel_offset DAT2, 8\n+        .cfi_same_value DAT3\n+        .cfi_same_value DAT4\n+        .cfi_same_value DAT5\n+        .cfi_same_value DAT6\n+        .cfi_same_value DAT7\n+        .cfi_rel_offset lr, 12\n+\n+160:    /* Medium case */\n+        preload_all  backwards, 0, 0, S, N, DAT2, OFF\n+        sub     N, N, #16     /* simplifies inner loop termination */\n+ .if backwards\n+        ands    DAT2, D, #15\n+        beq     164f\n+ .else\n+        ands    DAT2, D, #15\n+        beq     164f\n+        rsb     DAT2, DAT2, #16\n+ .endif\n+        memcpy_leading_15bytes backwards, align\n+164:    /* Destination now 16-byte aligned; we have at least one 16-byte output block */\n+        tst     S, #3\n+        bne     140f\n+        memcpy_medium_inner_loop  backwards, 0\n+140:    memcpy_medium_inner_loop  backwards, 1\n+\n+170:    /* Short case, less than 31 bytes, so no guarantee of at least one 16-byte block */\n+        teq     N, #0\n+        beq     199f\n+        preload_all  backwards, 1, 0, S, N, DAT2, LAST\n+        tst     D, #3\n+        beq     174f\n+172:    subs    N, N, #1\n+        blo     199f\n+ .if backwards\n+        ldrb    DAT0, [S, #-1]!\n+        strb    DAT0, [D, #-1]!\n+ .else\n+        ldrb    DAT0, [S], #1\n+        strb    DAT0, [D], #1\n+ .endif\n+        tst     D, #3\n+        bne     172b\n+174:    /* Destination now 4-byte aligned; we have 0 or more output bytes to go */\n+        tst     S, #3\n+        bne     140f\n+        memcpy_short_inner_loop  backwards, 0\n+140:    memcpy_short_inner_loop  backwards, 1\n+\n+        .cfi_endproc\n+\n+        .unreq  D\n+        .unreq  S\n+        .unreq  N\n+        .unreq  DAT0\n+        .unreq  DAT1\n+        .unreq  DAT2\n+        .unreq  DAT3\n+        .unreq  DAT4\n+        .unreq  DAT5\n+        .unreq  DAT6\n+        .unreq  DAT7\n+        .unreq  LAST\n+        .unreq  OFF\n+.endm\n--- /dev/null\n+++ b/arch/arm/lib/memmove_rpi.S\n@@ -0,0 +1,61 @@\n+/*\n+Copyright (c) 2013, Raspberry Pi Foundation\n+Copyright (c) 2013, RISC OS Open Ltd\n+All rights reserved.\n+\n+Redistribution and use in source and binary forms, with or without\n+modification, are permitted provided that the following conditions are met:\n+    * Redistributions of source code must retain the above copyright\n+      notice, this list of conditions and the following disclaimer.\n+    * Redistributions in binary form must reproduce the above copyright\n+      notice, this list of conditions and the following disclaimer in the\n+      documentation and/or other materials provided with the distribution.\n+    * Neither the name of the copyright holder nor the\n+      names of its contributors may be used to endorse or promote products\n+      derived from this software without specific prior written permission.\n+\n+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" AND\n+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY\n+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\n+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+*/\n+\n+#include <linux/linkage.h>\n+#include \"arm-mem.h\"\n+#include \"memcpymove.h\"\n+\n+/* Prevent the stack from becoming executable */\n+#if defined(__linux__) && defined(__ELF__)\n+.section .note.GNU-stack,\"\",%progbits\n+#endif\n+\n+    .text\n+    .arch armv6\n+    .object_arch armv4\n+    .arm\n+    .altmacro\n+    .p2align 2\n+\n+/*\n+ * void *memmove(void *s1, const void *s2, size_t n);\n+ * On entry:\n+ * a1 = pointer to destination\n+ * a2 = pointer to source\n+ * a3 = number of bytes to copy\n+ * On exit:\n+ * a1 preserved\n+ */\n+\n+.set prefetch_distance, 3\n+\n+ENTRY(memmove)\n+        cmp     a2, a1\n+        bpl     memcpy  /* pl works even over -1 - 0 and 0x7fffffff - 0x80000000 boundaries */\n+        memcpy  1\n+ENDPROC(memmove)\n--- /dev/null\n+++ b/arch/arm/lib/memset_rpi.S\n@@ -0,0 +1,128 @@\n+/*\n+Copyright (c) 2013, Raspberry Pi Foundation\n+Copyright (c) 2013, RISC OS Open Ltd\n+All rights reserved.\n+\n+Redistribution and use in source and binary forms, with or without\n+modification, are permitted provided that the following conditions are met:\n+    * Redistributions of source code must retain the above copyright\n+      notice, this list of conditions and the following disclaimer.\n+    * Redistributions in binary form must reproduce the above copyright\n+      notice, this list of conditions and the following disclaimer in the\n+      documentation and/or other materials provided with the distribution.\n+    * Neither the name of the copyright holder nor the\n+      names of its contributors may be used to endorse or promote products\n+      derived from this software without specific prior written permission.\n+\n+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" AND\n+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY\n+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\n+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+*/\n+\n+#include <linux/linkage.h>\n+#include \"arm-mem.h\"\n+\n+/* Prevent the stack from becoming executable */\n+#if defined(__linux__) && defined(__ELF__)\n+.section .note.GNU-stack,\"\",%progbits\n+#endif\n+\n+    .text\n+    .arch armv6\n+    .object_arch armv4\n+    .arm\n+    .altmacro\n+    .p2align 2\n+\n+/*\n+ *  void *memset(void *s, int c, size_t n);\n+ *  On entry:\n+ *  a1 = pointer to buffer to fill\n+ *  a2 = byte pattern to fill with (caller-narrowed)\n+ *  a3 = number of bytes to fill\n+ *  On exit:\n+ *  a1 preserved\n+ */\n+ENTRY(mmioset)\n+ENTRY(memset)\n+ENTRY(__memset32)\n+ENTRY(__memset64)\n+\n+        S       .req    a1\n+        DAT0    .req    a2\n+        N       .req    a3\n+        DAT1    .req    a4\n+        DAT2    .req    ip\n+        DAT3    .req    lr\n+\n+        orr     DAT0, DAT0, DAT0, lsl #8\n+        push    {S, lr}\n+        orr     DAT0, DAT0, DAT0, lsl #16\n+        mov     DAT1, DAT0\n+\n+        /* See if we're guaranteed to have at least one 16-byte aligned 16-byte write */\n+        cmp     N, #31\n+        blo     170f\n+\n+161:    sub     N, N, #16     /* simplifies inner loop termination */\n+        /* Leading words and bytes */\n+        tst     S, #15\n+        beq     164f\n+        rsb     DAT3, S, #0   /* bits 0-3 = number of leading bytes until aligned */\n+        movs    DAT2, DAT3, lsl #31\n+        submi   N, N, #1\n+        strmib  DAT0, [S], #1\n+        subcs   N, N, #2\n+        strcsh  DAT0, [S], #2\n+        movs    DAT2, DAT3, lsl #29\n+        submi   N, N, #4\n+        strmi   DAT0, [S], #4\n+        subcs   N, N, #8\n+        stmcsia S!, {DAT0, DAT1}\n+164:    /* Delayed set up of DAT2 and DAT3 so we could use them as scratch registers above */\n+        mov     DAT2, DAT0\n+        mov     DAT3, DAT0\n+        /* Now the inner loop of 16-byte stores */\n+165:    stmia   S!, {DAT0, DAT1, DAT2, DAT3}\n+        subs    N, N, #16\n+        bhs     165b\n+166:    /* Trailing words and bytes */\n+        movs    N, N, lsl #29\n+        stmcsia S!, {DAT0, DAT1}\n+        strmi   DAT0, [S], #4\n+        movs    N, N, lsl #2\n+        strcsh  DAT0, [S], #2\n+        strmib  DAT0, [S]\n+199:    pop     {S, pc}\n+\n+170:    /* Short case */\n+        mov     DAT2, DAT0\n+        mov     DAT3, DAT0\n+        tst     S, #3\n+        beq     174f\n+172:    subs    N, N, #1\n+        blo     199b\n+        strb    DAT0, [S], #1\n+        tst     S, #3\n+        bne     172b\n+174:    tst     N, #16\n+        stmneia S!, {DAT0, DAT1, DAT2, DAT3}\n+        b       166b\n+\n+        .unreq  S\n+        .unreq  DAT0\n+        .unreq  N\n+        .unreq  DAT1\n+        .unreq  DAT2\n+        .unreq  DAT3\n+ENDPROC(__memset64)\n+ENDPROC(__memset32)\n+ENDPROC(memset)\n+ENDPROC(mmioset)\n--- a/arch/arm/lib/uaccess_with_memcpy.c\n+++ b/arch/arm/lib/uaccess_with_memcpy.c\n@@ -19,6 +19,14 @@\n #include <asm/current.h>\n #include <asm/page.h>\n \n+#ifndef COPY_FROM_USER_THRESHOLD\n+#define COPY_FROM_USER_THRESHOLD 64\n+#endif\n+\n+#ifndef COPY_TO_USER_THRESHOLD\n+#define COPY_TO_USER_THRESHOLD 64\n+#endif\n+\n static int\n pin_page_for_write(const void __user *_addr, pte_t **ptep, spinlock_t **ptlp)\n {\n@@ -43,7 +51,7 @@ pin_page_for_write(const void __user *_a\n \t\treturn 0;\n \n \tpmd = pmd_offset(pud, addr);\n-\tif (unlikely(pmd_none(*pmd)))\n+\tif (unlikely(pmd_none(*pmd) || pmd_bad(*pmd)))\n \t\treturn 0;\n \n \t/*\n@@ -86,7 +94,46 @@ pin_page_for_write(const void __user *_a\n \treturn 1;\n }\n \n-static unsigned long noinline\n+static int\n+pin_page_for_read(const void __user *_addr, pte_t **ptep, spinlock_t **ptlp)\n+{\n+\tunsigned long addr = (unsigned long)_addr;\n+\tpgd_t *pgd;\n+\tp4d_t *p4d;\n+\tpmd_t *pmd;\n+\tpte_t *pte;\n+\tpud_t *pud;\n+\tspinlock_t *ptl;\n+\n+\tpgd = pgd_offset(current->mm, addr);\n+\tif (unlikely(pgd_none(*pgd) || pgd_bad(*pgd)))\n+\t\treturn 0;\n+\n+\tp4d = p4d_offset(pgd, addr);\n+\tif (unlikely(p4d_none(*p4d) || p4d_bad(*p4d)))\n+\t\treturn 0;\n+\n+\tpud = pud_offset(p4d, addr);\n+\tif (unlikely(pud_none(*pud) || pud_bad(*pud)))\n+\t\treturn 0;\n+\n+\tpmd = pmd_offset(pud, addr);\n+\tif (unlikely(pmd_none(*pmd) || pmd_bad(*pmd)))\n+\t\treturn 0;\n+\n+\tpte = pte_offset_map_lock(current->mm, pmd, addr, &ptl);\n+\tif (unlikely(!pte_present(*pte) || !pte_young(*pte))) {\n+\t\tpte_unmap_unlock(pte, ptl);\n+\t\treturn 0;\n+\t}\n+\n+\t*ptep = pte;\n+\t*ptlp = ptl;\n+\n+\treturn 1;\n+}\n+\n+unsigned long noinline\n __copy_to_user_memcpy(void __user *to, const void *from, unsigned long n)\n {\n \tunsigned long ua_flags;\n@@ -139,6 +186,57 @@ out:\n \treturn n;\n }\n \n+unsigned long noinline\n+__copy_from_user_memcpy(void *to, const void __user *from, unsigned long n)\n+{\n+\tunsigned long ua_flags;\n+\tint atomic;\n+\n+\tif (unlikely(uaccess_kernel())) {\n+\t\tmemcpy(to, (const void *)from, n);\n+\t\treturn 0;\n+\t}\n+\n+\t/* the mmap semaphore is taken only if not in an atomic context */\n+\tatomic = in_atomic();\n+\n+\tif (!atomic)\n+\t\tmmap_read_lock(current->mm);\n+\twhile (n) {\n+\t\tpte_t *pte;\n+\t\tspinlock_t *ptl;\n+\t\tint tocopy;\n+\n+\t\twhile (!pin_page_for_read(from, &pte, &ptl)) {\n+\t\t\tchar temp;\n+\t\t\tif (!atomic)\n+\t\t\t\tmmap_read_unlock(current->mm);\n+\t\t\tif (__get_user(temp, (char __user *)from))\n+\t\t\t\tgoto out;\n+\t\t\tif (!atomic)\n+\t\t\t\tmmap_read_lock(current->mm);\n+\t\t}\n+\n+\t\ttocopy = (~(unsigned long)from & ~PAGE_MASK) + 1;\n+\t\tif (tocopy > n)\n+\t\t\ttocopy = n;\n+\n+\t\tua_flags = uaccess_save_and_enable();\n+\t\tmemcpy(to, (const void *)from, tocopy);\n+\t\tuaccess_restore(ua_flags);\n+\t\tto += tocopy;\n+\t\tfrom += tocopy;\n+\t\tn -= tocopy;\n+\n+\t\tpte_unmap_unlock(pte, ptl);\n+\t}\n+\tif (!atomic)\n+\t\tmmap_read_unlock(current->mm);\n+\n+out:\n+\treturn n;\n+}\n+\n unsigned long\n arm_copy_to_user(void __user *to, const void *from, unsigned long n)\n {\n@@ -149,7 +247,7 @@ arm_copy_to_user(void __user *to, const\n \t * With frame pointer disabled, tail call optimization kicks in\n \t * as well making this test almost invisible.\n \t */\n-\tif (n < 64) {\n+\tif (n < COPY_TO_USER_THRESHOLD) {\n \t\tunsigned long ua_flags = uaccess_save_and_enable();\n \t\tn = __copy_to_user_std(to, from, n);\n \t\tuaccess_restore(ua_flags);\n@@ -159,6 +257,32 @@ arm_copy_to_user(void __user *to, const\n \t}\n \treturn n;\n }\n+\n+unsigned long __must_check\n+arm_copy_from_user(void *to, const void __user *from, unsigned long n)\n+{\n+#ifdef CONFIG_BCM2835_FAST_MEMCPY\n+\t/*\n+\t * This test is stubbed out of the main function above to keep\n+\t * the overhead for small copies low by avoiding a large\n+\t * register dump on the stack just to reload them right away.\n+\t * With frame pointer disabled, tail call optimization kicks in\n+\t * as well making this test almost invisible.\n+\t */\n+\tif (n < COPY_TO_USER_THRESHOLD) {\n+\t\tunsigned long ua_flags = uaccess_save_and_enable();\n+\t\tn = __copy_from_user_std(to, from, n);\n+\t\tuaccess_restore(ua_flags);\n+\t} else {\n+\t\tn = __copy_from_user_memcpy(to, from, n);\n+\t}\n+#else\n+\tunsigned long ua_flags = uaccess_save_and_enable();\n+\tn = __copy_from_user_std(to, from, n);\n+\tuaccess_restore(ua_flags);\n+#endif\n+\treturn n;\n+}\n \t\n static unsigned long noinline\n __clear_user_memset(void __user *addr, unsigned long n)\n--- a/arch/arm/mach-bcm/Kconfig\n+++ b/arch/arm/mach-bcm/Kconfig\n@@ -184,6 +184,13 @@ config ARCH_BCM_53573\n \t  The base chip is BCM53573 and there are some packaging modifications\n \t  like BCM47189 and BCM47452.\n \n+config BCM2835_FAST_MEMCPY\n+\tbool \"Enable optimized __copy_to_user and __copy_from_user\"\n+\tdepends on ARCH_BCM2835 && ARCH_MULTI_V6\n+\tdefault y\n+\thelp\n+\t  Optimized versions of __copy_to_user and __copy_from_user for Pi1.\n+\n config ARCH_BCM_63XX\n \tbool \"Broadcom BCM63xx DSL SoC\"\n \tdepends on ARCH_MULTI_V7\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0058-gpio-poweroff-Allow-it-to-work-on-Raspberry-Pi.patch",
    "content": "From 95a7bcf89e17aa8ec8cabc06d47479e1ecb76976 Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.org>\nDate: Thu, 25 Jun 2015 12:16:11 +0100\nSubject: [PATCH] gpio-poweroff: Allow it to work on Raspberry Pi\n\nThe Raspberry Pi firmware manages the power-down and reboot\nprocess. To do this it installs a pm_power_off handler, causing\nthe gpio-poweroff module to abort the probe function.\n\nThis patch introduces a \"force\" DT property that overrides that\nbehaviour, and also adds a DT overlay to enable and control it.\n\nNote that running in an active-low configuration (DT parameter\n\"active_low\") requires a custom dt-blob.bin and probably won't\nallow a reboot without switching off, so an external inversion\nof the trigger signal may be preferable.\n---\n drivers/power/reset/gpio-poweroff.c | 4 +++-\n 1 file changed, 3 insertions(+), 1 deletion(-)\n\n--- a/drivers/power/reset/gpio-poweroff.c\n+++ b/drivers/power/reset/gpio-poweroff.c\n@@ -50,9 +50,11 @@ static int gpio_poweroff_probe(struct pl\n {\n \tbool input = false;\n \tenum gpiod_flags flags;\n+\tbool force = false;\n \n \t/* If a pm_power_off function has already been added, leave it alone */\n-\tif (pm_power_off != NULL) {\n+\tforce = of_property_read_bool(pdev->dev.of_node, \"force\");\n+\tif (!force && (pm_power_off != NULL)) {\n \t\tdev_err(&pdev->dev,\n \t\t\t\"%s: pm_power_off function already registered\\n\",\n \t\t       __func__);\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0059-mfd-Add-Raspberry-Pi-Sense-HAT-core-driver.patch",
    "content": "From cf000173e9ee4a80ac245e5feb042c18c5643d6c Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <pelwell@users.noreply.github.com>\nDate: Tue, 14 Jul 2015 14:32:47 +0100\nSubject: [PATCH] mfd: Add Raspberry Pi Sense HAT core driver\n\nmfd: Add rpi_sense_core of compatible string\n---\n drivers/input/joystick/Kconfig           |   8 +\n drivers/input/joystick/Makefile          |   2 +-\n drivers/input/joystick/rpisense-js.c     | 153 ++++++++++++\n drivers/mfd/Kconfig                      |   8 +\n drivers/mfd/Makefile                     |   1 +\n drivers/mfd/rpisense-core.c              | 165 +++++++++++++\n drivers/video/fbdev/Kconfig              |  13 +\n drivers/video/fbdev/Makefile             |   1 +\n drivers/video/fbdev/rpisense-fb.c        | 293 +++++++++++++++++++++++\n include/linux/mfd/rpisense/core.h        |  47 ++++\n include/linux/mfd/rpisense/framebuffer.h |  32 +++\n include/linux/mfd/rpisense/joystick.h    |  35 +++\n 12 files changed, 757 insertions(+), 1 deletion(-)\n create mode 100644 drivers/input/joystick/rpisense-js.c\n create mode 100644 drivers/mfd/rpisense-core.c\n create mode 100644 drivers/video/fbdev/rpisense-fb.c\n create mode 100644 include/linux/mfd/rpisense/core.h\n create mode 100644 include/linux/mfd/rpisense/framebuffer.h\n create mode 100644 include/linux/mfd/rpisense/joystick.h\n\n--- a/drivers/input/joystick/Kconfig\n+++ b/drivers/input/joystick/Kconfig\n@@ -382,4 +382,12 @@ config JOYSTICK_FSIA6B\n \t  To compile this driver as a module, choose M here: the\n \t  module will be called fsia6b.\n \n+config JOYSTICK_RPISENSE\n+\ttristate \"Raspberry Pi Sense HAT joystick\"\n+\tdepends on GPIOLIB && INPUT\n+\tselect MFD_RPISENSE_CORE\n+\n+\thelp\n+\t  This is the joystick driver for the Raspberry Pi Sense HAT\n+\n endif\n--- a/drivers/input/joystick/Makefile\n+++ b/drivers/input/joystick/Makefile\n@@ -37,4 +37,4 @@ obj-$(CONFIG_JOYSTICK_WARRIOR)\t\t+= warri\n obj-$(CONFIG_JOYSTICK_WALKERA0701)\t+= walkera0701.o\n obj-$(CONFIG_JOYSTICK_XPAD)\t\t+= xpad.o\n obj-$(CONFIG_JOYSTICK_ZHENHUA)\t\t+= zhenhua.o\n-\n+obj-$(CONFIG_JOYSTICK_RPISENSE)\t\t+= rpisense-js.o\n--- /dev/null\n+++ b/drivers/input/joystick/rpisense-js.c\n@@ -0,0 +1,153 @@\n+/*\n+ * Raspberry Pi Sense HAT joystick driver\n+ * http://raspberrypi.org\n+ *\n+ * Copyright (C) 2015 Raspberry Pi\n+ *\n+ * Author: Serge Schneider\n+ *\n+ *  This program is free software; you can redistribute  it and/or modify it\n+ *  under  the terms of  the GNU General  Public License as published by the\n+ *  Free Software Foundation;  either version 2 of the  License, or (at your\n+ *  option) any later version.\n+ *\n+ */\n+\n+#include <linux/module.h>\n+\n+#include <linux/mfd/rpisense/joystick.h>\n+#include <linux/mfd/rpisense/core.h>\n+\n+static struct rpisense *rpisense;\n+static unsigned char keymap[5] = {KEY_DOWN, KEY_RIGHT, KEY_UP, KEY_ENTER, KEY_LEFT,};\n+\n+static void keys_work_fn(struct work_struct *work)\n+{\n+\tint i;\n+\tstatic s32 prev_keys;\n+\tstruct rpisense_js *rpisense_js = &rpisense->joystick;\n+\ts32 keys = rpisense_reg_read(rpisense, RPISENSE_KEYS);\n+\ts32 changes = keys ^ prev_keys;\n+\n+\tprev_keys = keys;\n+\tfor (i = 0; i < 5; i++) {\n+\t\tif (changes & 1) {\n+\t\t\tinput_report_key(rpisense_js->keys_dev,\n+\t\t\t\t\t keymap[i], keys & 1);\n+\t\t}\n+\t\tchanges >>= 1;\n+\t\tkeys >>= 1;\n+\t}\n+\tinput_sync(rpisense_js->keys_dev);\n+}\n+\n+static irqreturn_t keys_irq_handler(int irq, void *pdev)\n+{\n+\tstruct rpisense_js *rpisense_js = &rpisense->joystick;\n+\n+\tschedule_work(&rpisense_js->keys_work_s);\n+\treturn IRQ_HANDLED;\n+}\n+\n+static int rpisense_js_probe(struct platform_device *pdev)\n+{\n+\tint ret;\n+\tint i;\n+\tstruct rpisense_js *rpisense_js;\n+\n+\trpisense = rpisense_get_dev();\n+\trpisense_js = &rpisense->joystick;\n+\n+\tINIT_WORK(&rpisense_js->keys_work_s, keys_work_fn);\n+\n+\trpisense_js->keys_dev = input_allocate_device();\n+\tif (!rpisense_js->keys_dev) {\n+\t\tdev_err(&pdev->dev, \"Could not allocate input device.\\n\");\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\trpisense_js->keys_dev->evbit[0] = BIT_MASK(EV_KEY);\n+\tfor (i = 0; i < ARRAY_SIZE(keymap); i++) {\n+\t\tset_bit(keymap[i],\n+\t\t\trpisense_js->keys_dev->keybit);\n+\t}\n+\n+\trpisense_js->keys_dev->name = \"Raspberry Pi Sense HAT Joystick\";\n+\trpisense_js->keys_dev->phys = \"rpi-sense-joy/input0\";\n+\trpisense_js->keys_dev->id.bustype = BUS_I2C;\n+\trpisense_js->keys_dev->evbit[0] = BIT_MASK(EV_KEY) | BIT_MASK(EV_REP);\n+\trpisense_js->keys_dev->keycode = keymap;\n+\trpisense_js->keys_dev->keycodesize = sizeof(unsigned char);\n+\trpisense_js->keys_dev->keycodemax = ARRAY_SIZE(keymap);\n+\n+\tret = input_register_device(rpisense_js->keys_dev);\n+\tif (ret) {\n+\t\tdev_err(&pdev->dev, \"Could not register input device.\\n\");\n+\t\tgoto err_keys_alloc;\n+\t}\n+\n+\tret = gpiod_direction_input(rpisense_js->keys_desc);\n+\tif (ret) {\n+\t\tdev_err(&pdev->dev, \"Could not set keys-int direction.\\n\");\n+\t\tgoto err_keys_reg;\n+\t}\n+\n+\trpisense_js->keys_irq = gpiod_to_irq(rpisense_js->keys_desc);\n+\tif (rpisense_js->keys_irq < 0) {\n+\t\tdev_err(&pdev->dev, \"Could not determine keys-int IRQ.\\n\");\n+\t\tret = rpisense_js->keys_irq;\n+\t\tgoto err_keys_reg;\n+\t}\n+\n+\tret = devm_request_irq(&pdev->dev, rpisense_js->keys_irq,\n+\t\t\t       keys_irq_handler, IRQF_TRIGGER_RISING,\n+\t\t\t       \"keys\", &pdev->dev);\n+\tif (ret) {\n+\t\tdev_err(&pdev->dev, \"IRQ request failed.\\n\");\n+\t\tgoto err_keys_reg;\n+\t}\n+\treturn 0;\n+err_keys_reg:\n+\tinput_unregister_device(rpisense_js->keys_dev);\n+err_keys_alloc:\n+\tinput_free_device(rpisense_js->keys_dev);\n+\treturn ret;\n+}\n+\n+static int rpisense_js_remove(struct platform_device *pdev)\n+{\n+\tstruct rpisense_js *rpisense_js = &rpisense->joystick;\n+\n+\tinput_unregister_device(rpisense_js->keys_dev);\n+\tinput_free_device(rpisense_js->keys_dev);\n+\treturn 0;\n+}\n+\n+#ifdef CONFIG_OF\n+static const struct of_device_id rpisense_js_id[] = {\n+\t{ .compatible = \"rpi,rpi-sense-js\" },\n+\t{ },\n+};\n+MODULE_DEVICE_TABLE(of, rpisense_js_id);\n+#endif\n+\n+static struct platform_device_id rpisense_js_device_id[] = {\n+\t{ .name = \"rpi-sense-js\" },\n+\t{ },\n+};\n+MODULE_DEVICE_TABLE(platform, rpisense_js_device_id);\n+\n+static struct platform_driver rpisense_js_driver = {\n+\t.probe = rpisense_js_probe,\n+\t.remove = rpisense_js_remove,\n+\t.driver = {\n+\t\t.name = \"rpi-sense-js\",\n+\t\t.owner = THIS_MODULE,\n+\t},\n+};\n+\n+module_platform_driver(rpisense_js_driver);\n+\n+MODULE_DESCRIPTION(\"Raspberry Pi Sense HAT joystick driver\");\n+MODULE_AUTHOR(\"Serge Schneider <serge@raspberrypi.org>\");\n+MODULE_LICENSE(\"GPL\");\n--- a/drivers/mfd/Kconfig\n+++ b/drivers/mfd/Kconfig\n@@ -11,6 +11,14 @@ config MFD_CORE\n \tselect IRQ_DOMAIN\n \tdefault n\n \n+config MFD_RPISENSE_CORE\n+\ttristate \"Raspberry Pi Sense HAT core functions\"\n+\tdepends on I2C\n+\tselect MFD_CORE\n+\thelp\n+\t  This is the core driver for the Raspberry Pi Sense HAT. This provides\n+\t  the necessary functions to communicate with the hardware.\n+\n config MFD_CS5535\n \ttristate \"AMD CS5535 and CS5536 southbridge core functions\"\n \tselect MFD_CORE\n--- a/drivers/mfd/Makefile\n+++ b/drivers/mfd/Makefile\n@@ -263,6 +263,7 @@ obj-$(CONFIG_MFD_ROHM_BD71828)\t+= rohm-b\n obj-$(CONFIG_MFD_ROHM_BD718XX)\t+= rohm-bd718x7.o\n obj-$(CONFIG_MFD_STMFX) \t+= stmfx.o\n obj-$(CONFIG_MFD_KHADAS_MCU) \t+= khadas-mcu.o\n+obj-$(CONFIG_MFD_RPISENSE_CORE)\t+= rpisense-core.o\n \n obj-$(CONFIG_SGI_MFD_IOC3)\t+= ioc3.o\n obj-$(CONFIG_MFD_SIMPLE_MFD_I2C)\t+= simple-mfd-i2c.o\n--- /dev/null\n+++ b/drivers/mfd/rpisense-core.c\n@@ -0,0 +1,165 @@\n+/*\n+ * Raspberry Pi Sense HAT core driver\n+ * http://raspberrypi.org\n+ *\n+ * Copyright (C) 2015 Raspberry Pi\n+ *\n+ * Author: Serge Schneider\n+ *\n+ *  This program is free software; you can redistribute  it and/or modify it\n+ *  under  the terms of  the GNU General  Public License as published by the\n+ *  Free Software Foundation;  either version 2 of the  License, or (at your\n+ *  option) any later version.\n+ *\n+ *  This driver is based on wm8350 implementation.\n+ */\n+\n+#include <linux/module.h>\n+#include <linux/moduleparam.h>\n+#include <linux/err.h>\n+#include <linux/init.h>\n+#include <linux/i2c.h>\n+#include <linux/platform_device.h>\n+#include <linux/mfd/rpisense/core.h>\n+#include <linux/slab.h>\n+\n+static struct rpisense *rpisense;\n+\n+static void rpisense_client_dev_register(struct rpisense *rpisense,\n+\t\t\t\t\t const char *name,\n+\t\t\t\t\t struct platform_device **pdev)\n+{\n+\tint ret;\n+\n+\t*pdev = platform_device_alloc(name, -1);\n+\tif (*pdev == NULL) {\n+\t\tdev_err(rpisense->dev, \"Failed to allocate %s\\n\", name);\n+\t\treturn;\n+\t}\n+\n+\t(*pdev)->dev.parent = rpisense->dev;\n+\tplatform_set_drvdata(*pdev, rpisense);\n+\tret = platform_device_add(*pdev);\n+\tif (ret != 0) {\n+\t\tdev_err(rpisense->dev, \"Failed to register %s: %d\\n\",\n+\t\t\tname, ret);\n+\t\tplatform_device_put(*pdev);\n+\t\t*pdev = NULL;\n+\t}\n+}\n+\n+static int rpisense_probe(struct i2c_client *i2c,\n+\t\t\t       const struct i2c_device_id *id)\n+{\n+\tint ret;\n+\tstruct rpisense_js *rpisense_js;\n+\n+\trpisense = devm_kzalloc(&i2c->dev, sizeof(struct rpisense), GFP_KERNEL);\n+\tif (rpisense == NULL)\n+\t\treturn -ENOMEM;\n+\n+\ti2c_set_clientdata(i2c, rpisense);\n+\trpisense->dev = &i2c->dev;\n+\trpisense->i2c_client = i2c;\n+\n+\tret = rpisense_reg_read(rpisense, RPISENSE_WAI);\n+\tif (ret > 0) {\n+\t\tif (ret != 's')\n+\t\t\treturn -EINVAL;\n+\t} else {\n+\t\treturn ret;\n+\t}\n+\tret = rpisense_reg_read(rpisense, RPISENSE_VER);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\tdev_info(rpisense->dev,\n+\t\t \"Raspberry Pi Sense HAT firmware version %i\\n\", ret);\n+\n+\trpisense_js = &rpisense->joystick;\n+\trpisense_js->keys_desc = devm_gpiod_get(&i2c->dev,\n+\t\t\t\t\t\t\"keys-int\", GPIOD_IN);\n+\tif (IS_ERR(rpisense_js->keys_desc)) {\n+\t\tdev_warn(&i2c->dev, \"Failed to get keys-int descriptor.\\n\");\n+\t\trpisense_js->keys_desc = gpio_to_desc(23);\n+\t\tif (rpisense_js->keys_desc == NULL) {\n+\t\t\tdev_err(&i2c->dev, \"GPIO23 fallback failed.\\n\");\n+\t\t\treturn PTR_ERR(rpisense_js->keys_desc);\n+\t\t}\n+\t}\n+\trpisense_client_dev_register(rpisense, \"rpi-sense-js\",\n+\t\t\t\t     &(rpisense->joystick.pdev));\n+\trpisense_client_dev_register(rpisense, \"rpi-sense-fb\",\n+\t\t\t\t     &(rpisense->framebuffer.pdev));\n+\n+\treturn 0;\n+}\n+\n+static int rpisense_remove(struct i2c_client *i2c)\n+{\n+\tstruct rpisense *rpisense = i2c_get_clientdata(i2c);\n+\n+\tplatform_device_unregister(rpisense->joystick.pdev);\n+\treturn 0;\n+}\n+\n+struct rpisense *rpisense_get_dev(void)\n+{\n+\treturn rpisense;\n+}\n+EXPORT_SYMBOL_GPL(rpisense_get_dev);\n+\n+s32 rpisense_reg_read(struct rpisense *rpisense, int reg)\n+{\n+\tint ret = i2c_smbus_read_byte_data(rpisense->i2c_client, reg);\n+\n+\tif (ret < 0)\n+\t\tdev_err(rpisense->dev, \"Read from reg %d failed\\n\", reg);\n+\t/* Due to the BCM270x I2C clock stretching bug, some values\n+\t * may have MSB set. Clear it to avoid incorrect values.\n+\t * */\n+\treturn ret & 0x7F;\n+}\n+EXPORT_SYMBOL_GPL(rpisense_reg_read);\n+\n+int rpisense_block_write(struct rpisense *rpisense, const char *buf, int count)\n+{\n+\tint ret = i2c_master_send(rpisense->i2c_client, buf, count);\n+\n+\tif (ret < 0)\n+\t\tdev_err(rpisense->dev, \"Block write failed\\n\");\n+\treturn ret;\n+}\n+EXPORT_SYMBOL_GPL(rpisense_block_write);\n+\n+static const struct i2c_device_id rpisense_i2c_id[] = {\n+\t{ \"rpi-sense\", 0 },\n+\t{ }\n+};\n+MODULE_DEVICE_TABLE(i2c, rpisense_i2c_id);\n+\n+#ifdef CONFIG_OF\n+static const struct of_device_id rpisense_core_id[] = {\n+\t{ .compatible = \"rpi,rpi-sense\" },\n+\t{ },\n+};\n+MODULE_DEVICE_TABLE(of, rpisense_core_id);\n+#endif\n+\n+\n+static struct i2c_driver rpisense_driver = {\n+\t.driver = {\n+\t\t   .name = \"rpi-sense\",\n+\t\t   .owner = THIS_MODULE,\n+\t},\n+\t.probe = rpisense_probe,\n+\t.remove = rpisense_remove,\n+\t.id_table = rpisense_i2c_id,\n+};\n+\n+module_i2c_driver(rpisense_driver);\n+\n+MODULE_DESCRIPTION(\"Raspberry Pi Sense HAT core driver\");\n+MODULE_AUTHOR(\"Serge Schneider <serge@raspberrypi.org>\");\n+MODULE_LICENSE(\"GPL\");\n+\n--- a/drivers/video/fbdev/Kconfig\n+++ b/drivers/video/fbdev/Kconfig\n@@ -2250,6 +2250,19 @@ config FB_SM712\n \t  called sm712fb. If you want to compile it as a module, say M\n \t  here and read <file:Documentation/kbuild/modules.rst>.\n \n+config FB_RPISENSE\n+\ttristate \"Raspberry Pi Sense HAT framebuffer\"\n+\tdepends on FB\n+\tselect MFD_RPISENSE_CORE\n+\tselect FB_SYS_FOPS\n+\tselect FB_SYS_FILLRECT\n+\tselect FB_SYS_COPYAREA\n+\tselect FB_SYS_IMAGEBLIT\n+\tselect FB_DEFERRED_IO\n+\n+\thelp\n+\t  This is the framebuffer driver for the Raspberry Pi Sense HAT\n+\n source \"drivers/video/fbdev/omap/Kconfig\"\n source \"drivers/video/fbdev/omap2/Kconfig\"\n source \"drivers/video/fbdev/mmp/Kconfig\"\n--- a/drivers/video/fbdev/Makefile\n+++ b/drivers/video/fbdev/Makefile\n@@ -130,6 +130,7 @@ obj-$(CONFIG_FB_MX3)\t\t  += mx3fb.o\n obj-$(CONFIG_FB_DA8XX)\t\t  += da8xx-fb.o\n obj-$(CONFIG_FB_SSD1307)\t  += ssd1307fb.o\n obj-$(CONFIG_FB_SIMPLE)           += simplefb.o\n+obj-$(CONFIG_FB_RPISENSE)\t  += rpisense-fb.o\n \n # the test framebuffer is last\n obj-$(CONFIG_FB_VIRTUAL)          += vfb.o\n--- /dev/null\n+++ b/drivers/video/fbdev/rpisense-fb.c\n@@ -0,0 +1,293 @@\n+/*\n+ * Raspberry Pi Sense HAT framebuffer driver\n+ * http://raspberrypi.org\n+ *\n+ * Copyright (C) 2015 Raspberry Pi\n+ *\n+ * Author: Serge Schneider\n+ *\n+ *  This program is free software; you can redistribute  it and/or modify it\n+ *  under  the terms of  the GNU General  Public License as published by the\n+ *  Free Software Foundation;  either version 2 of the  License, or (at your\n+ *  option) any later version.\n+ *\n+ */\n+\n+#include <linux/module.h>\n+#include <linux/kernel.h>\n+#include <linux/errno.h>\n+#include <linux/string.h>\n+#include <linux/mm.h>\n+#include <linux/slab.h>\n+#include <linux/uaccess.h>\n+#include <linux/delay.h>\n+#include <linux/fb.h>\n+#include <linux/init.h>\n+\n+#include <linux/mfd/rpisense/framebuffer.h>\n+#include <linux/mfd/rpisense/core.h>\n+\n+static bool lowlight;\n+module_param(lowlight, bool, 0);\n+MODULE_PARM_DESC(lowlight, \"Reduce LED matrix brightness to one third\");\n+\n+static struct rpisense *rpisense;\n+\n+struct rpisense_fb_param {\n+\tchar __iomem *vmem;\n+\tu8 *vmem_work;\n+\tu32 vmemsize;\n+\tu8 *gamma;\n+};\n+\n+static u8 gamma_default[32] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01,\n+\t\t\t       0x02, 0x02, 0x03, 0x03, 0x04, 0x05, 0x06, 0x07,\n+\t\t\t       0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0E, 0x0F, 0x11,\n+\t\t\t       0x12, 0x14, 0x15, 0x17, 0x19, 0x1B, 0x1D, 0x1F,};\n+\n+static u8 gamma_low[32] = {0x00, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,\n+\t\t\t   0x01, 0x01, 0x01, 0x01, 0x01, 0x02, 0x02, 0x02,\n+\t\t\t   0x03, 0x03, 0x03, 0x04, 0x04, 0x05, 0x05, 0x06,\n+\t\t\t   0x06, 0x07, 0x07, 0x08, 0x08, 0x09, 0x0A, 0x0A,};\n+\n+static u8 gamma_user[32];\n+\n+static struct rpisense_fb_param rpisense_fb_param = {\n+\t.vmem = NULL,\n+\t.vmemsize = 128,\n+\t.gamma = gamma_default,\n+};\n+\n+static struct fb_deferred_io rpisense_fb_defio;\n+\n+static struct fb_fix_screeninfo rpisense_fb_fix = {\n+\t.id =\t\t\"RPi-Sense FB\",\n+\t.type =\t\tFB_TYPE_PACKED_PIXELS,\n+\t.visual =\tFB_VISUAL_TRUECOLOR,\n+\t.xpanstep =\t0,\n+\t.ypanstep =\t0,\n+\t.ywrapstep =\t0,\n+\t.accel =\tFB_ACCEL_NONE,\n+\t.line_length =\t16,\n+};\n+\n+static struct fb_var_screeninfo rpisense_fb_var = {\n+\t.xres\t\t= 8,\n+\t.yres\t\t= 8,\n+\t.xres_virtual\t= 8,\n+\t.yres_virtual\t= 8,\n+\t.bits_per_pixel = 16,\n+\t.red\t\t= {11, 5, 0},\n+\t.green\t\t= {5, 6, 0},\n+\t.blue\t\t= {0, 5, 0},\n+};\n+\n+static ssize_t rpisense_fb_write(struct fb_info *info,\n+\t\t\t\t const char __user *buf, size_t count,\n+\t\t\t\t loff_t *ppos)\n+{\n+\tssize_t res = fb_sys_write(info, buf, count, ppos);\n+\n+\tschedule_delayed_work(&info->deferred_work, rpisense_fb_defio.delay);\n+\treturn res;\n+}\n+\n+static void rpisense_fb_fillrect(struct fb_info *info,\n+\t\t\t\t const struct fb_fillrect *rect)\n+{\n+\tsys_fillrect(info, rect);\n+\tschedule_delayed_work(&info->deferred_work, rpisense_fb_defio.delay);\n+}\n+\n+static void rpisense_fb_copyarea(struct fb_info *info,\n+\t\t\t\t const struct fb_copyarea *area)\n+{\n+\tsys_copyarea(info, area);\n+\tschedule_delayed_work(&info->deferred_work, rpisense_fb_defio.delay);\n+}\n+\n+static void rpisense_fb_imageblit(struct fb_info *info,\n+\t\t\t\t  const struct fb_image *image)\n+{\n+\tsys_imageblit(info, image);\n+\tschedule_delayed_work(&info->deferred_work, rpisense_fb_defio.delay);\n+}\n+\n+static void rpisense_fb_deferred_io(struct fb_info *info,\n+\t\t\t\tstruct list_head *pagelist)\n+{\n+\tint i;\n+\tint j;\n+\tu8 *vmem_work = rpisense_fb_param.vmem_work;\n+\tu16 *mem = (u16 *)rpisense_fb_param.vmem;\n+\tu8 *gamma = rpisense_fb_param.gamma;\n+\n+\tvmem_work[0] = 0;\n+\tfor (j = 0; j < 8; j++) {\n+\t\tfor (i = 0; i < 8; i++) {\n+\t\t\tvmem_work[(j * 24) + i + 1] =\n+\t\t\t\tgamma[(mem[(j * 8) + i] >> 11) & 0x1F];\n+\t\t\tvmem_work[(j * 24) + (i + 8) + 1] =\n+\t\t\t\tgamma[(mem[(j * 8) + i] >> 6) & 0x1F];\n+\t\t\tvmem_work[(j * 24) + (i + 16) + 1] =\n+\t\t\t\tgamma[(mem[(j * 8) + i]) & 0x1F];\n+\t\t}\n+\t}\n+\trpisense_block_write(rpisense, vmem_work, 193);\n+}\n+\n+static struct fb_deferred_io rpisense_fb_defio = {\n+\t.delay\t\t= HZ/100,\n+\t.deferred_io\t= rpisense_fb_deferred_io,\n+};\n+\n+static int rpisense_fb_ioctl(struct fb_info *info, unsigned int cmd,\n+\t\t\t     unsigned long arg)\n+{\n+\tswitch (cmd) {\n+\tcase SENSEFB_FBIOGET_GAMMA:\n+\t\tif (copy_to_user((void __user *) arg, rpisense_fb_param.gamma,\n+\t\t\t\t sizeof(u8[32])))\n+\t\t\treturn -EFAULT;\n+\t\treturn 0;\n+\tcase SENSEFB_FBIOSET_GAMMA:\n+\t\tif (copy_from_user(gamma_user, (void __user *)arg,\n+\t\t\t\t   sizeof(u8[32])))\n+\t\t\treturn -EFAULT;\n+\t\trpisense_fb_param.gamma = gamma_user;\n+\t\tschedule_delayed_work(&info->deferred_work,\n+\t\t\t\t      rpisense_fb_defio.delay);\n+\t\treturn 0;\n+\tcase SENSEFB_FBIORESET_GAMMA:\n+\t\tswitch (arg) {\n+\t\tcase 0:\n+\t\t\trpisense_fb_param.gamma = gamma_default;\n+\t\t\tbreak;\n+\t\tcase 1:\n+\t\t\trpisense_fb_param.gamma = gamma_low;\n+\t\t\tbreak;\n+\t\tcase 2:\n+\t\t\trpisense_fb_param.gamma = gamma_user;\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t\tschedule_delayed_work(&info->deferred_work,\n+\t\t\t\t      rpisense_fb_defio.delay);\n+\t\tbreak;\n+\tdefault:\n+\t\treturn -EINVAL;\n+\t}\n+\treturn 0;\n+}\n+\n+static struct fb_ops rpisense_fb_ops = {\n+\t.owner\t\t= THIS_MODULE,\n+\t.fb_read\t= fb_sys_read,\n+\t.fb_write\t= rpisense_fb_write,\n+\t.fb_fillrect\t= rpisense_fb_fillrect,\n+\t.fb_copyarea\t= rpisense_fb_copyarea,\n+\t.fb_imageblit\t= rpisense_fb_imageblit,\n+\t.fb_ioctl\t= rpisense_fb_ioctl,\n+};\n+\n+static int rpisense_fb_probe(struct platform_device *pdev)\n+{\n+\tstruct fb_info *info;\n+\tint ret = -ENOMEM;\n+\tstruct rpisense_fb *rpisense_fb;\n+\n+\trpisense = rpisense_get_dev();\n+\trpisense_fb = &rpisense->framebuffer;\n+\n+\trpisense_fb_param.vmem = vzalloc(rpisense_fb_param.vmemsize);\n+\tif (!rpisense_fb_param.vmem)\n+\t\treturn ret;\n+\n+\trpisense_fb_param.vmem_work = devm_kmalloc(&pdev->dev, 193, GFP_KERNEL);\n+\tif (!rpisense_fb_param.vmem_work)\n+\t\tgoto err_malloc;\n+\n+\tinfo = framebuffer_alloc(0, &pdev->dev);\n+\tif (!info) {\n+\t\tdev_err(&pdev->dev, \"Could not allocate framebuffer.\\n\");\n+\t\tgoto err_malloc;\n+\t}\n+\trpisense_fb->info = info;\n+\n+\trpisense_fb_fix.smem_start = (unsigned long)rpisense_fb_param.vmem;\n+\trpisense_fb_fix.smem_len = rpisense_fb_param.vmemsize;\n+\n+\tinfo->fbops = &rpisense_fb_ops;\n+\tinfo->fix = rpisense_fb_fix;\n+\tinfo->var = rpisense_fb_var;\n+\tinfo->fbdefio = &rpisense_fb_defio;\n+\tinfo->flags = FBINFO_FLAG_DEFAULT | FBINFO_VIRTFB;\n+\tinfo->screen_base = rpisense_fb_param.vmem;\n+\tinfo->screen_size = rpisense_fb_param.vmemsize;\n+\n+\tif (lowlight)\n+\t\trpisense_fb_param.gamma = gamma_low;\n+\n+\tfb_deferred_io_init(info);\n+\n+\tret = register_framebuffer(info);\n+\tif (ret < 0) {\n+\t\tdev_err(&pdev->dev, \"Could not register framebuffer.\\n\");\n+\t\tgoto err_fballoc;\n+\t}\n+\n+\tfb_info(info, \"%s frame buffer device\\n\", info->fix.id);\n+\tschedule_delayed_work(&info->deferred_work, rpisense_fb_defio.delay);\n+\treturn 0;\n+err_fballoc:\n+\tframebuffer_release(info);\n+err_malloc:\n+\tvfree(rpisense_fb_param.vmem);\n+\treturn ret;\n+}\n+\n+static int rpisense_fb_remove(struct platform_device *pdev)\n+{\n+\tstruct rpisense_fb *rpisense_fb = &rpisense->framebuffer;\n+\tstruct fb_info *info = rpisense_fb->info;\n+\n+\tif (info) {\n+\t\tunregister_framebuffer(info);\n+\t\tfb_deferred_io_cleanup(info);\n+\t\tframebuffer_release(info);\n+\t\tvfree(rpisense_fb_param.vmem);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+#ifdef CONFIG_OF\n+static const struct of_device_id rpisense_fb_id[] = {\n+\t{ .compatible = \"rpi,rpi-sense-fb\" },\n+\t{ },\n+};\n+MODULE_DEVICE_TABLE(of, rpisense_fb_id);\n+#endif\n+\n+static struct platform_device_id rpisense_fb_device_id[] = {\n+\t{ .name = \"rpi-sense-fb\" },\n+\t{ },\n+};\n+MODULE_DEVICE_TABLE(platform, rpisense_fb_device_id);\n+\n+static struct platform_driver rpisense_fb_driver = {\n+\t.probe = rpisense_fb_probe,\n+\t.remove = rpisense_fb_remove,\n+\t.driver = {\n+\t\t.name = \"rpi-sense-fb\",\n+\t\t.owner = THIS_MODULE,\n+\t},\n+};\n+\n+module_platform_driver(rpisense_fb_driver);\n+\n+MODULE_DESCRIPTION(\"Raspberry Pi Sense HAT framebuffer driver\");\n+MODULE_AUTHOR(\"Serge Schneider <serge@raspberrypi.org>\");\n+MODULE_LICENSE(\"GPL\");\n+\n--- /dev/null\n+++ b/include/linux/mfd/rpisense/core.h\n@@ -0,0 +1,47 @@\n+/*\n+ * Raspberry Pi Sense HAT core driver\n+ * http://raspberrypi.org\n+ *\n+ * Copyright (C) 2015 Raspberry Pi\n+ *\n+ * Author: Serge Schneider\n+ *\n+ *  This program is free software; you can redistribute  it and/or modify it\n+ *  under  the terms of  the GNU General  Public License as published by the\n+ *  Free Software Foundation;  either version 2 of the  License, or (at your\n+ *  option) any later version.\n+ *\n+ */\n+\n+#ifndef __LINUX_MFD_RPISENSE_CORE_H_\n+#define __LINUX_MFD_RPISENSE_CORE_H_\n+\n+#include <linux/mfd/rpisense/joystick.h>\n+#include <linux/mfd/rpisense/framebuffer.h>\n+\n+/*\n+ * Register values.\n+ */\n+#define RPISENSE_FB\t\t\t0x00\n+#define RPISENSE_WAI\t\t\t0xF0\n+#define RPISENSE_VER\t\t\t0xF1\n+#define RPISENSE_KEYS\t\t\t0xF2\n+#define RPISENSE_EE_WP\t\t\t0xF3\n+\n+#define RPISENSE_ID\t\t\t's'\n+\n+struct rpisense {\n+\tstruct device *dev;\n+\tstruct i2c_client *i2c_client;\n+\n+\t/* Client devices */\n+\tstruct rpisense_js joystick;\n+\tstruct rpisense_fb framebuffer;\n+};\n+\n+struct rpisense *rpisense_get_dev(void);\n+s32 rpisense_reg_read(struct rpisense *rpisense, int reg);\n+int rpisense_reg_write(struct rpisense *rpisense, int reg, u16 val);\n+int rpisense_block_write(struct rpisense *rpisense, const char *buf, int count);\n+\n+#endif\n--- /dev/null\n+++ b/include/linux/mfd/rpisense/framebuffer.h\n@@ -0,0 +1,32 @@\n+/*\n+ * Raspberry Pi Sense HAT framebuffer driver\n+ * http://raspberrypi.org\n+ *\n+ * Copyright (C) 2015 Raspberry Pi\n+ *\n+ * Author: Serge Schneider\n+ *\n+ *  This program is free software; you can redistribute  it and/or modify it\n+ *  under  the terms of  the GNU General  Public License as published by the\n+ *  Free Software Foundation;  either version 2 of the  License, or (at your\n+ *  option) any later version.\n+ *\n+ */\n+\n+#ifndef __LINUX_RPISENSE_FB_H_\n+#define __LINUX_RPISENSE_FB_H_\n+\n+#define SENSEFB_FBIO_IOC_MAGIC 0xF1\n+\n+#define SENSEFB_FBIOGET_GAMMA _IO(SENSEFB_FBIO_IOC_MAGIC, 0)\n+#define SENSEFB_FBIOSET_GAMMA _IO(SENSEFB_FBIO_IOC_MAGIC, 1)\n+#define SENSEFB_FBIORESET_GAMMA _IO(SENSEFB_FBIO_IOC_MAGIC, 2)\n+\n+struct rpisense;\n+\n+struct rpisense_fb {\n+\tstruct platform_device *pdev;\n+\tstruct fb_info *info;\n+};\n+\n+#endif\n--- /dev/null\n+++ b/include/linux/mfd/rpisense/joystick.h\n@@ -0,0 +1,35 @@\n+/*\n+ * Raspberry Pi Sense HAT joystick driver\n+ * http://raspberrypi.org\n+ *\n+ * Copyright (C) 2015 Raspberry Pi\n+ *\n+ * Author: Serge Schneider\n+ *\n+ *  This program is free software; you can redistribute  it and/or modify it\n+ *  under  the terms of  the GNU General  Public License as published by the\n+ *  Free Software Foundation;  either version 2 of the  License, or (at your\n+ *  option) any later version.\n+ *\n+ */\n+\n+#ifndef __LINUX_RPISENSE_JOYSTICK_H_\n+#define __LINUX_RPISENSE_JOYSTICK_H_\n+\n+#include <linux/input.h>\n+#include <linux/interrupt.h>\n+#include <linux/gpio/consumer.h>\n+#include <linux/platform_device.h>\n+\n+struct rpisense;\n+\n+struct rpisense_js {\n+\tstruct platform_device *pdev;\n+\tstruct input_dev *keys_dev;\n+\tstruct gpio_desc *keys_desc;\n+\tstruct work_struct keys_work_s;\n+\tint keys_irq;\n+};\n+\n+\n+#endif\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0060-Add-support-for-all-the-downstream-rpi-sound-card-dr.patch",
    "content": "From 6e520cdc4c898f0d02bbe40e2c466f9694933d9c Mon Sep 17 00:00:00 2001\nFrom: Florian Meier <florian.meier@koalo.de>\nDate: Mon, 25 Jan 2016 15:48:59 +0000\nSubject: [PATCH] Add support for all the downstream rpi sound card\n drivers\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nASoC: Add support for Rpi-DAC\n\nASoC: Add prompt for ICS43432 codec\n\nWithout a prompt string, a config setting can't be included in a\ndefconfig. Give CONFIG_SND_SOC_ICS43432 a prompt so that Pi soundcards\ncan use the driver.\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.org>\n\nAdd IQaudIO Sound Card support for Raspberry Pi\n\nSet a limit of 0dB on Digital Volume Control\n\nThe main volume control in the PCM512x DAC has a range up to\n+24dB. This is dangerously loud and can potentially cause massive\nclipping in the output stages. Therefore this sets a sensible\nlimit of 0dB for this control.\n\nAllow up to 24dB digital gain to be applied when using IQAudIO DAC+\n\n24db_digital_gain DT param can be used to specify that PCM512x\ncodec \"Digital\" volume control should not be limited to 0dB gain,\nand if specified will allow the full 24dB gain.\n\nModify IQAudIO DAC+ ASoC driver to set card/dai config from dt\n\nAdd the ability to set the card name, dai name and dai stream name, from\ndt config.\n\nSigned-off-by: DigitalDreamtime <clive.messer@digitaldreamtime.co.uk>\n\nIQaudIO: auto-mute for AMP+ and DigiAMP+\n\nIQAudIO amplifier mute via GPIO22. Add dt params for \"one-shot\" unmute\nand auto mute.\n\nRevision 2, auto mute implementing HiassofT suggestion to mute/unmute\nusing set_bias_level, rather than startup/shutdown....\n\"By default DAPM waits 5 seconds (pmdown_time) before shutting down\nplayback streams so a close/stop immediately followed by open/start\ndoesn't trigger an amp mute+unmute.\"\n\nTested on both AMP+ (via DAC+) and DigiAMP+, with both options...\n\ndtoverlay=iqaudio-dacplus,unmute_amp\n \"one-shot\" unmute when kernel module loads.\n\ndtoverlay=iqaudio-dacplus,auto_mute_amp\n Unmute amp when ALSA device opened by a client. Mute, with 5 second delay\n when ALSA device closed. (Re-opening the device within the 5 second close\n window, will cancel mute.)\n\nRevision 4, using gpiod.\n\nRevision 5, clean-up formatting before adding mute code.\n - Convert tab plus 4 space formatting to 2x tab\n - Remove '// NOT USED' commented code\n\nRevision 6, don't attempt to \"one-shot\" unmute amp, unless card is\nsuccessfully registered.\n\nSigned-off-by: DigitalDreamtime <clive.messer@digitaldreamtime.co.uk>\n\nASoC: iqaudio-dac: fix S24_LE format\n\nRemove set_bclk_ratio call so 24-bit data is transmitted in\n24 bclk cycles.\n\nSigned-off-by: Matthias Reichl <hias@horus.com>\n\nASoC: iqaudio-dac: use modern dai_link style\n\nSigned-off-by: Matthias Reichl <hias@horus.com>\n\nAdded support for HiFiBerry DAC+\n\nThe driver is based on the HiFiBerry DAC driver. However HiFiBerry DAC+ uses\na different codec chip (PCM5122), therefore a new driver is necessary.\n\nAdd support for the HiFiBerry DAC+ Pro.\n\nThe HiFiBerry DAC+ and DAC+ Pro products both use the existing bcm sound driver with the DAC+ Pro having a special clock device driver representing the two high precision oscillators.\n\nAn addition bug fix is included for the PCM512x codec where by the physical size of the sample frame is used in the calculation of the LRCK divisor as it was found to be wrong when using 24-bit depth sample contained in a little endian 4-byte sample frame.\n\nLimit PCM512x \"Digital\" gain to 0dB by default with HiFiBerry DAC+\n\n24db_digital_gain DT param can be used to specify that PCM512x\ncodec \"Digital\" volume control should not be limited to 0dB gain,\nand if specified will allow the full 24dB gain.\n\nAdd dt param to force HiFiBerry DAC+ Pro into slave mode\n\n\"dtoverlay=hifiberry-dacplus,slave\"\n\nAdd 'slave' param to use HiFiBerry DAC+ Pro in slave mode,\nwith Pi as master for bit and frame clock.\n\nSigned-off-by: DigitalDreamtime <clive.messer@digitaldreamtime.co.uk>\n\nFixed a bug when using 352.8kHz sample rate\n\nSigned-off-by: Daniel Matuschek <daniel@hifiberry.com>\n\nASoC: pcm512x: revert downstream changes\n\nThis partially reverts commit 185ea05465aac8bf02a0d2b2f4289d42c72870b7\nwhich was added by https://github.com/raspberrypi/linux/pull/1152\n\nThe downstream pcm512x changes caused a regression, it broke normal\nuse of the 24bit format with the codec, eg when using simple-audio-card.\n\nThe actual bug with 24bit playback is the incorrect usage\nof physical_width in various drivers in the downstream tree\nwhich causes 24bit data to be transmitted with 32 clock\ncycles. So it's not the pcm512x that needs fixing, it's the\nsoundcard drivers.\n\nSigned-off-by: Matthias Reichl <hias@horus.com>\n\nASoC: hifiberry_dacplus: fix S24_LE format\n\nRemove set_bclk_ratio call so 24-bit data is transmitted in\n24 bclk cycles.\n\nSigned-off-by: Matthias Reichl <hias@horus.com>\n\nASoC: hifiberry_dacplus: transmit S24_LE with 64 BCLK cycles\n\nSigned-off-by: Matthias Reichl <hias@horus.com>\n\nhifiberry_dacplus: switch to snd_soc_dai_set_bclk_ratio\n\nSigned-off-by: Matthias Reichl <hias@horus.com>\n\nASoC: hifiberry_dacplus: use modern dai_link style\n\nSigned-off-by: Hui Wang <hui.wang@canonical.com>\n\nAdd driver for rpi-proto\n\nForward port of 3.10.x driver from https://github.com/koalo\nWe are using a custom board and would like to use rpi 3.18.x\nkernel. Patch works fine for our embedded system.\n\nURL to the audio chip:\nhttp://www.mikroe.com/add-on-boards/audio-voice/audio-codec-proto/\n\nPlayback tested with devicetree enabled.\n\nSigned-off-by: Waldemar Brodkorb <wbrodkorb@conet.de>\n\nASoC: rpi-proto: use modern dai_link style\n\nSigned-off-by: Hui Wang <hui.wang@canonical.com>\n\nAdd Support for JustBoom Audio boards\n\njustboom-dac: Adjust for ALSA API change\n\nAs of 4.4, snd_soc_limit_volume now takes a struct snd_soc_card *\nrather than a struct snd_soc_codec *.\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.org>\n\nASoC: justboom-dac: fix S24_LE format\n\nRemove set_bclk_ratio call so 24-bit data is transmitted in\n24 bclk cycles.\n\nAlso remove hw_params as it's no longer needed.\n\nSigned-off-by: Matthias Reichl <hias@horus.com>\n\nASoC: justboom-dac: use modern dai_link style\n\nSigned-off-by: Matthias Reichl <hias@horus.com>\n\nNew AudioInjector.net Pi soundcard with low jitter audio in and out.\n\nContains the sound/soc/bcm ALSA machine driver and necessary alterations to the Kconfig and Makefile.\nAdds the dts overlay and updates the Makefile and README.\nUpdates the relevant defconfig files to enable building for the Raspberry Pi.\nThanks to Phil Elwell (pelwell) for the review, simple-card concepts and discussion. Thanks to Clive Messer for overlay naming suggestions.\n\nAdded support for headphones, microphone and bclk_ratio settings.\n\nThis patch adds headphone and microphone capability to the Audio Injector sound card. The patch also sets the bit clock ratio for use in the bcm2835-i2s driver. The bcm2835-i2s can't handle an 8 kHz sample rate when the bit clock is at 12 MHz because its register is only 10 bits wide which can't represent the ch2 offset of 1508. For that reason, the rate constraint is added.\n\nASoC: audioinjector-pi-soundcard: use modern dai_link style\n\nSigned-off-by: Hui Wang <hui.wang@canonical.com>\n\nNew driver for RRA DigiDAC1 soundcard using WM8741 + WM8804\n\nASoC: digidac1-soundcard: use modern dai_link style\n\nSigned-off-by: Hui Wang <hui.wang@canonical.com>\n\nAdd support for Dion Audio LOCO DAC-AMP HAT\n\nUsing dedicated machine driver and pcm5102a codec driver.\n\nSigned-off-by: DigitalDreamtime <clive.messer@digitaldreamtime.co.uk>\n\nASoC: dionaudio_loco: use modern dai_link style\n\nSigned-off-by: Hui Wang <hui.wang@canonical.com>\n\nAllo Piano DAC boards: Initial 2 channel (stereo) support (#1645)\n\nAdd initial 2 channel (stereo) support for Allo Piano DAC (2.0/2.1) boards,\nusing allo-piano-dac-pcm512x-audio overlay and allo-piano-dac ALSA ASoC\nmachine driver.\n\nNB. The initial support is 2 channel (stereo) ONLY!\n(The Piano DAC 2.1 will only support 2 channel (stereo) left/right output,\n pending an update to the upstream pcm512x codec driver, which will have\n to be submitted via upstream. With the initial downstream support,\n provided by this patch, the Piano DAC 2.1 subwoofer outputs will\n not function.)\n\nSigned-off-by: Baswaraj K <jaikumar@cem-solutions.net>\nSigned-off-by: Clive Messer <clive.messer@digitaldreamtime.co.uk>\nTested-by: Clive Messer <clive.messer@digitaldreamtime.co.uk>\n\nASoC: allo-piano-dac: fix S24_LE format\n\nRemove set_bclk_ratio call so 24-bit data is transmitted in\n24 bclk cycles.\n\nAlso remove hw_params and ops as they are no longer needed.\n\nSigned-off-by: Matthias Reichl <hias@horus.com>\n\nASoC: allo-piano-dac: use modern dai_link style\n\nSigned-off-by: Hui Wang <hui.wang@canonical.com>\n\nAdd support for Allo Piano DAC 2.1 plus add-on board for Raspberry Pi.\n\nThe Piano DAC 2.1 has support for 4 channels with subwoofer.\n\nSigned-off-by: Baswaraj K <jaikumar@cem-solutions.net>\nReviewed-by: Vijay Kumar B. <vijaykumar@zilogic.com>\nReviewed-by: Raashid Muhammed <raashidmuhammed@zilogic.com>\n\nAdd clock changes and mute gpios (#1938)\n\nAlso improve code style and adhere to ALSA coding conventions.\n\nSigned-off-by: Baswaraj K <jaikumar@cem-solutions.net>\nReviewed-by: Vijay Kumar B. <vijaykumar@zilogic.com>\nReviewed-by: Raashid Muhammed <raashidmuhammed@zilogic.com>\n\nPianoPlus: Dual Mono & Dual Stereo features added (#2069)\n\nallo-piano-dac-plus: Master volume added + fixes\n\nMaster volume added, which controls both DACs volumes.\n\nSee: https://github.com/raspberrypi/linux/pull/2149\n\nAlso fix initial max volume, default mode value, and unmute.\n\nSigned-off-by: allocom <sparky-dev@allo.com>\n\nASoC: allo-piano-dac-plus: fix S24_LE format\n\nRemove set_bclk_ratio call so 24-bit data is transmitted in\n24 bclk cycles.\n\nSigned-off-by: Matthias Reichl <hias@horus.com>\n\nsound: bcm: Fix memset dereference warning\n\nThis warning appears with GCC 6.4.0 from toolchains.bootlin.com:\n\n../sound/soc/bcm/allo-piano-dac-plus.c: In function ‘snd_allo_piano_dac_init’:\n../sound/soc/bcm/allo-piano-dac-plus.c:711:30: warning: argument to ‘sizeof’ in ‘memset’ call is the same expression as the destination; did you mean to dereference it? [-Wsizeof-pointer-memaccess]\n  memset(glb_ptr, 0x00, sizeof(glb_ptr));\n                              ^\n\nSuggested-by: Phil Elwell <phil@raspberrypi.org>\nSigned-off-by: Nathan Chancellor <natechancellor@gmail.com>\n\nASoC: allo-piano-dac-plus: use modern dai_link style\n\nSigned-off-by: Hui Wang <hui.wang@canonical.com>\n\nAdd support for Allo Boss DAC add-on board for Raspberry Pi. (#1924)\n\nSigned-off-by: Baswaraj K <jaikumar@cem-solutions.net>\nReviewed-by: Deepak <deepak@zilogic.com>\nReviewed-by: BabuSubashChandar <babusubashchandar@zilogic.com>\n\nAdd support for new clock rate and mute gpios.\n\nSigned-off-by: Baswaraj K <jaikumar@cem-solutions.net>\nReviewed-by: Deepak <deepak@zilogic.com>\nReviewed-by: BabuSubashChandar <babusubashchandar@zilogic.com>\n\nASoC: allo-boss-dac: fix S24_LE format\n\nRemove set_bclk_ratio call so 24-bit data is transmitted in\n24 bclk cycles.\n\nSigned-off-by: Matthias Reichl <hias@horus.com>\n\nASoC: allo-boss-dac: transmit S24_LE with 64 BCLK cycles\n\nSigned-off-by: Matthias Reichl <hias@horus.com>\n\nallo-boss-dac: switch to snd_soc_dai_set_bclk_ratio\n\nSigned-off-by: Matthias Reichl <hias@horus.com>\n\nASoC: allo-boss-dac: use modern dai_link style\n\nSigned-off-by: Hui Wang <hui.wang@canonical.com>\n\nSupport for Blokas Labs pisound board\n\nPisound dynamic overlay (#1760)\n\nRestructuring pisound-overlay.dts, so it can be loaded and unloaded dynamically using dtoverlay.\n\nPrint a logline when the kernel module is removed.\n\npisound improvements:\n\n* Added a writable sysfs object to enable scripts / user space software\nto blink MIDI activity LEDs for variable duration.\n* Improved hw_param constraints setting.\n* Added compatibility with S16_LE sample format.\n* Exposed some simple placeholder volume controls, so the card appears\nin volumealsa widget.\n\nAdd missing SND_PISOUND selects dependency to SND_RAWMIDI\n\nWithout it the Pisound module fails to compile.\nSee https://github.com/raspberrypi/linux/issues/2366\n\nUpdates for Pisound module code:\n\n\t* Merged 'Fix a warning in DEBUG builds' (1c8b82b).\n\t* Updating some strings and copyright information.\n\t* Fix for handling high load of MIDI input and output.\n\t* Use dual rate oversampling ratio for 96kHz instead of single\n\t  rate one.\n\nSigned-off-by: Giedrius Trainavicius <giedrius@blokas.io>\n\nFixing memset call in pisound.c\n\nSigned-off-by: Giedrius Trainavicius <giedrius@blokas.io>\n\nFix for Pisound's MIDI Input getting blocked for a while in rare cases.\n\nThere was a possible race condition which could lead to Input's FIFO queue\nto be underflown, causing high amount of processing in the worker thread for\nsome period of time.\n\nSigned-off-by: Giedrius Trainavicius <giedrius@blokas.io>\n\nFix for Pisound kernel module in Real Time kernel configuration.\n\nWhen handler of data_available interrupt is fired, queue_work ends up\ngetting called and it can block on a spin lock which is not allowed in\ninterrupt context. The fix was to run the handler from a thread context\ninstead.\n\nPisound: Remove spinlock usage around spi_sync\n\nASoC: pisound: use modern dai_link style\n\nSigned-off-by: Hui Wang <hui.wang@canonical.com>\n\nASoC: pisound: fix the parameter for spi_device_match\n\nSigned-off-by: Hui Wang <hui.wang@canonical.com>\n\nASoC: Add driver for Cirrus Logic Audio Card\n\nNote: due to problems with deferred probing of regulators\nthe following softdep should be added to a modprobe.d file\n\nsoftdep arizona-spi pre: arizona-ldo1\n\nSigned-off-by: Matthias Reichl <hias@horus.com>\n\nASoC: rpi-cirrus: use modern dai_link style\n\nSigned-off-by: Matthias Reichl <hias@horus.com>\n\nsound: Support for Dion Audio LOCO-V2 DAC-AMP HAT\n\nSigned-off-by: Miquel Blauw <info@dionaudio.nl>\n\nASoC: dionaudio_loco-v2: fix S24_LE format\n\nRemove set_bclk_ratio call so 24-bit data is transmitted in\n24 bclk cycles.\n\nAlso remove hw_params and ops as they are no longer needed.\n\nSigned-off-by: Matthias Reichl <hias@horus.com>\n\nASoC: dionaudio_loco-v2: use modern dai_link style\n\nSigned-off-by: Hui Wang <hui.wang@canonical.com>\n\nAdd support for Fe-Pi audio sound card. (#1867)\n\nFe-Pi Audio Sound Card is based on NXP SGTL5000 codec.\nMechanical specification of the board is the same the Raspberry Pi Zero.\n3.5mm jacks for Headphone/Mic, Line In, and Line Out.\n\nSigned-off-by: Henry Kupis <fe-pi@cox.net>\n\nASoC: fe-pi-audio: use modern dai_link style\n\nSigned-off-by: Hui Wang <hui.wang@canonical.com>\n\nAdd support for the AudioInjector.net Octo sound card\n\nAudioInjector Octo: sample rates, regulators, reset\n\nThis patch adds new sample rates to the Audioinjector Octo sound card. The\nnew supported rates are (in kHz) :\n96, 48, 32, 24, 16, 8, 88.2, 44.1, 29.4, 22.05, 14.7\n\nReference the bcm270x DT regulators in the overlay.\n\nThis patch adds a reset GPIO for the AudioInjector.net octo sound card.\n\nAudioinjector octo : Make the playback and capture symmetric\n\nThis patch ensures that the sample rate and channel count of the audioinjector\nocto sound card are symmetric.\n\naudioinjector-octo: Add continuous clock feature\n\nBy user request, add a switch to prevent the clocks being stopped when\nthe stream is paused, stopped or shutdown. Provide access to the switch\nby adding a 'non-stop-clocks' parameter to the audioinjector-addons\noverlay.\n\nSee: https://github.com/raspberrypi/linux/issues/2409\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.org>\n\nsound: Fixes for audioinjector-octo under 4.19\n\n1. Move the DT alias declaration to the I2C shim in the cases\nwhere the shim is enabled. This works around a problem caused by a\n4.19 commit [1] that generates DT/OF uevents for I2C drivers.\n\n2. Fix the diagnostics in an error path of the soundcard driver to\ncorrectly identify the reason for the failure to load.\n\n3. Move the declaration of the clock node in the overlay outside\nthe I2C node to avoid warnings.\n\n4. Sort the overlay nodes so that dependencies are only to earlier\nfragments, in an attempt to get runtime dtoverlay application to\nwork (it still doesn't...)\n\nSee: https://github.com/Audio-Injector/Octo/issues/14\nSigned-off-by: Phil Elwell <phil@raspberrypi.org>\n\n[1] af503716ac14 (\"i2c: core: report OF style module alias for devices registered via OF\")\n\nASoC: audioinjector-octo-soundcard: use modern dai_link style\n\nSigned-off-by: Hui Wang <hui.wang@canonical.com>\n\nDriver support for Google voiceHAT soundcard.\n\nASoC: googlevoicehat-codec: Use correct device when grabbing GPIO\n\nThe fixup for the VoiceHAT in 4.18 incorrectly tried to find the\nsdmode GPIO pin under the card device, not the codec device.\nThis failed, and therefore caused the device probe to fail.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>\n\nASoC: googlevoicehat-codec: Reformat for kernel coding standards\n\nFix all whitespace, indentation, and bracing errors.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>\n\nASoC: googlevoicehat-codec: Make driver function structure const\n\nMake voicehat_component_driver a const structure.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>\n\nASoC: googlevoicehat-codec: Only convert from ms to jiffies once\n\nMinor optimisation and allows to become checkpatch clean.\nA msec value is read out of DT or from a define, and convert once to\njiffies, rather than every time that it is used.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>\n\nDriver and overlay for Allo Katana DAC\n\nAllo Katana DAC: Updated default values\n\nSigned-off-by: Jaikumar <jaikumar@cem-solutions.com>\n\nAdded mute stream func\n\nSigned-off-by: Jaikumar <jaikumar@cem-solutions.net>\n\ncodecs: Correct Katana minimum volume\n\nUpdate Katana minimum volume to get the exact 0.5 dB value in each step.\n\nSigned-off-by: Sudeep Kumar <sudeepkumar@cem-solutions.net>\n\nASoC: Add generic RPI driver for simple soundcards.\n\nThe RPI simple sound card driver provides a generic ALSA SOC card driver\nsupporting a variety of Pi HAT soundcards. The intention is to avoid\nthe duplication of code for cards that can't be fully supported by\nthe soc simple/graph cards but are otherwise almost identical.\n\nThis initial commit adds support for the ADAU1977 ADC, Google VoiceHat,\nHifiBerry AMP, HifiBerry DAC and RPI DAC.\n\nSigned-off-by: Tim Gover <tim.gover@raspberrypi.org>\n\nASoC: Use correct card name in rpi-simple driver\n\nUse the specific card name from drvdata instead of the snd_rpi_simple\n\nrpi-simple-soundcard: Use nicer driver name \"RPi-simple\"\n\nRename the driver from \"RPI simple soundcard\" to \"RPi-simple\" so that\nthe driver name won't be mangled allowing to be used unaltered as the\ncard conf filename.\n\nASoC: rpi-simple-soundcard: use modern dai_link style\n\nSigned-off-by: Hui Wang <hui.wang@canonical.com>\n\nASoC: Add Kconfig and Makefile for sound/soc/bcm\n\nSigned-off-by: popcornmix <popcornmix@gmail.com>\n\nASoC: Create a generic Pi Hat WM8804 driver\n\nReduce the amount of duplicated code by creating a generic driver for\nPi Hat digi cards using the WM8804 codec.\n\nThis replaces the\nAllo DigiOne, Hifiberry Digi/Pro, JustBoom Digi and IQAudIO Digi\ndedicate soundcard drivers with a generic driver.\n\nThere are no significant changes to the runtime behavior of the drivers\nand end users should not have to change any configuration settings\nafter upgrading.\n\nMinor changes\n* Check the return value of snd_soc_component_update_bits\n* Added some pr_debug tracing\n* Various checkpatch tidyups\n* Updated allodigi-one to use use 128FS at > 96 Khz. This appears to\n  be an omission in the original driver code so followed the Hifiberry\n  DAC driver approach.\n\nASoC: rpi-wm8804-soundcard: use modern dai_link style\n\nSigned-off-by: Matthias Reichl <hias@horus.com>\n\nrpi-wm8804-soundcard: drop PWRDN register writes\n\nSince kernel 4.0 the PWRDN register bits are under DAPM\ncontrol from the wm8804 driver.\n\nDrop code that modifies that register to avoid interfering\nwith DAPM.\n\nSigned-off-by: Matthias Reichl <hias@horus.com>\n\nrpi-wm8804-soundcard: configure wm8804 clocks only on rate change\n\nThis should avoid clicks when stopping and immediately afterwards\nstarting a stream with the same samplerate as before.\n\nSigned-off-by: Matthias Reichl <hias@horus.com>\n\nrpi-wm8804-soundcard: Fixed MCLKDIV for Allo Digione\n\nThe Allo Digione board wants a fixed MCLKDIV of 256.\n\nSee: https://github.com/raspberrypi/linux/issues/3296\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.org>\n\nASoC: Add support for AudioSense-Pi add-on soundcard\n\nAudioSense-Pi is a RPi HAT based on a TI's TLV320AIC32x4 stereo codec\n\nThis hardware provides multiple audio I/O capabilities to the RPi.\nThe codec connects to the RPi's SoC through the I2S Bus.\n\nThe following devices can be connected through a 3.5mm jack\n\t1. Line-In: Plain old audio in from mobile phones, PCs, etc.,\n\t2. Mic-In: Connect a microphone\n\t3. Line-Out: Connect the output to a speaker\n\t4. Headphones: Connect a Headphone w or w/o microphones\n\nMultiple Inputs:\n\tIt supports the following combinations\n\t1. Two stereo Line-Inputs and a microphone\n\t2. One stereo Line-Input and two microphones\n\t3. Two stereo Line-Inputs, a microphone and\n\t\tone mono line-input (with h/w hack)\n\t4. One stereo Line-Input, two microphones and\n\t\tone mono line-input (with h/w hack)\n\nMultiple Outputs:\n\tAudio output can be routed to the headphones or\n\t\tspeakers (with additional hardware)\n\nSigned-off-by: b-ak <anur.bhargav@gmail.com>\n\nASoC: audiosense-pi: use modern dai_link style\n\nSigned-off-by: Hui Wang <hui.wang@canonical.com>\n\nAdded driver for the HiFiBerry DAC+ ADC (#2694)\n\nSigned-off-by: Daniel Matuschek <daniel@hifiberry.com>\n\nhifiberry_dacplusadc: switch to snd_soc_dai_set_bclk_ratio\n\nSigned-off-by: Matthias Reichl <hias@horus.com>\n\nASoC: hifiberry_dacplusadc: fix DAI link setup\n\nThe driver only defines a single DAI link and the code that tries\nto setup the second (non-existent) DAI link looks wrong - using dmic\nas a CPU/platform driver doesn't make any sense.\n\nThe DT overlay doesn't define a dmic property, so the code was never\nexecuted (otherwise it would have resulted in a memory corruption).\n\nSo drop the offending code to prevent issues if a dmic property\nshould be added to the DT overlay.\n\nSigned-off-by: Matthias Reichl <hias@horus.com>\n\nASoC: hifiberry_dacplusadc: use modern dai_link style\n\nSigned-off-by: Matthias Reichl <hias@horus.com>\n\nAudiophonics I-Sabre 9038Q2M DAC driver\n\nSigned-off-by: Audiophonics <contact@audiophonics.fr>\n\nASoC: i-sabre-q2m: use modern dai_link style\n\nSigned-off-by: Hui Wang <hui.wang@canonical.com>\n\nAdded IQaudIO Pi-Codec board support (#2969)\n\nAdd support for the IQaudIO Pi-Codec board.\n\nSigned-off-by: Gordon <gordon@iqaudio.com>\n\nFixed 48k timing issue\n\nASoC: iqaudio-codec: use modern dai_link style\n\nSigned-off-by: Hui Wang <hui.wang@canonical.com>\n\nadds the Hifiberry DAC+ADC PRO version\n\nThis adds the driver for the DAC+ADC PRO version of the Hifiberry soundcard with software controlled PCM1863 ADC\nSigned-off-by: Joerg Schambacher joerg@i2audio.com\n\nAdd Hifiberry DAC+DSP soundcard driver (#3224)\n\nAdds the driver for the Hifiberry DAC+DSP. It supports capture and\nplayback depending on the DSP firmware.\n\nSigned-off-by: Joerg Schambacher <joerg@i2audio.com>\n\nAllow simultaneous use of JustBoom DAC and Digi\n\nSigned-off-by: Johannes Krude <johannes@krude.de>\n\nPisound: MIDI communication fixes for scaled down CPU.\n\n* Increased maximum SPI communication speed to avoid running too slow\n  when the CPU is scaled down and losing MIDI data.\n\n* Keep track of buffer usage in millibytes for higher precision.\n\nSigned-off-by: Giedrius Trainavičius <giedrius@blokas.io>\n\nsound: Add the HiFiBerry DAC+HD version\n\nThis adds the driver for the DAC+HD version supporting HiFiBerry's\nPCM179x based DACs. It also adds PLL control for clock generation.\n\nSigned-off-by: Joerg Schambacher <joerg@i2audio.com>\n\nFix master mode settings of HiFiBerry DAC+ADC PRO card (#3424)\n\nThis patch fixes the board DAI setting when in master-mode.\nWrong setting could have caused random pop noise.\n\nSigned-off-by: Joerg Schambacher <joerg@i2audio.com>\n\nadds LED OFF feature to HiFiBerry DAC+ADC PRO sound card\n\nThis adds a DT overlay parameter 'leds_off' which allows\nto switch off the onboard activity LEDs at all times\nwhich has been requested by some users.\n\nSigned-off-by: Joerg Schambacher <joerg@i2audio.com>\n\nadds LED OFF feature to HiFiBerry DAC+ADC sound card\n\nThis adds a DT overlay parameter 'leds_off' which allows\nto switch off the onboard activity LEDs at all times\nwhich has been requested by some users.\n\nSigned-off-by: Joerg Schambacher <joerg@i2audio.com>\n\nadds LED OFF feature to HiFiBerry DAC+/DAC+PRO sound cards\n\nThis adds a DT overlay parameter 'leds_off' which allows\nto switch off the onboard activity LEDs at all times\nwhich has been requested by some users.\n\nSigned-off-by: Joerg Schambacher <joerg@i2audio.com>\n\npisound: Added reading Pisound board hardware revision and exposing it (#3425)\n\npisound: Added reading Pisound board hardware revision and exposing it in kernel log and sysfs file:\n\n/sys/kernel/pisound/hw_version\n\nSigned-off-by: Giedrius <giedrius@blokas.io>\n\nAdded driver for HiFiBerry Amp amplifier add-on board\n\nThe driver contains a low-level hardware driver for the TAS5713 and the\ndrivers for the Raspberry Pi I2S subsystem.\n\nTAS5713: return error if initialisation fails\n\nExisting TAS5713 driver logs errors during initialisation, but does not return\nan error code. Therefore even if initialisation fails, the driver will still be\nloaded, but won't work. This patch fixes this. I2C communication error will now\nreported correctly by a non-zero return code.\n\nHiFiBerry Amp: fix device-tree problems\n\nSome code to load the driver based on device-tree-overlays was missing. This is added by this patch.\n\nAccording to 5713 pdf doc CLOCK_CTRL is a readonly status register, and it behaves so. Remove useless setting\n\nsound: pcm512x-codec: Adding 352.8kHz samplerate support\n\nsound/soc: only first codec is master in multicodec setup\n\nWhen using multiple codecs, at most one codec should generate the master\nclock. All codecs except the first are therefore configured for slave\nmode.\n\nSigned-off-by: Johannes Krude <johannes@krude.de>\n\nASoC: Fix snd_soc_get_pcm_runtime usage\n\nCommit [1] changed the snd_soc_get_pcm_runtime to take a dai_link\npointer instead of a string. Patch up the downstream drivers to use\nthe modified API.\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.com>\n\n[1] 4468189ff307 (\"ASoC: soc-core: find rtd via dai_link pointer at snd_soc_get_pcm_runtime()\")\n\nAdd support for the AudioInjector.net Isolated sound card\n\nThis patch adds support for the Audio Injector Isolated sound card.\n\nSigned-off-by: Matt Flax <flatmax@flatmax.org>\n\nAdd support for merus-amp soundcard and ma120x0p codec\n\nAdd 96KHz rate support to MA120X0P codec and make enable and mute gpio\npins optional.\n\nSigned-off-by: AMuszkat <ariel.muszkat@gmail.com>\n\nFixes a problem with clock settings of HiFiBerry DAC+ADC PRO (#3545)\n\nThis patch fixes a problem of the re-calculation of\ni2s-clock and -parameter settings when only the ADC is activated.\n\nSigned-off-by: Joerg Schambacher <joerg@i2audio.com>\n\nconfigs: Enable the AD193x codecs\n\nSee: https://github.com/raspberrypi/linux/issues/2850\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.org>\n\nSwitch to snd_soc_dai_set_bclk_ratio\nReplaces obsolete function snd_soc_dai_set_tdm_slot\n\nSigned-off-by: Joerg Schambacher <joerg@i2audio.com>\n\nEnhances the DAC+ driver to control the optional headphone amplifier\n\nProbes on the I2C bus for TPA6130A2, if successful, it sets DT-parameter\n'status' from 'disabled' to 'okay' using change_sets to enable\nthe headphone control.\n\nSigned-off-by: Joerg Schambacher joerg@i2audio.com\n---\n .../devicetree/bindings/vendor-prefixes.txt   |  463 ++++++\n .../devicetree/bindings/vendor-prefixes.yaml  |    2 +\n drivers/clk/Kconfig                           |    6 +\n drivers/clk/Makefile                          |    3 +\n drivers/clk/clk-allo-dac.c                    |  161 ++\n drivers/clk/clk-hifiberry-dachd.c             |  333 ++++\n drivers/clk/clk-hifiberry-dacpro.c            |  160 ++\n sound/soc/bcm/Kconfig                         |  274 ++++\n sound/soc/bcm/Makefile                        |   63 +-\n sound/soc/bcm/allo-boss-dac.c                 |  456 ++++++\n sound/soc/bcm/allo-katana-codec.c             |  388 +++++\n sound/soc/bcm/allo-piano-dac-plus.c           |  987 ++++++++++++\n sound/soc/bcm/allo-piano-dac.c                |  122 ++\n .../bcm/audioinjector-isolated-soundcard.c    |  183 +++\n sound/soc/bcm/audioinjector-octo-soundcard.c  |  346 +++++\n sound/soc/bcm/audioinjector-pi-soundcard.c    |  187 +++\n sound/soc/bcm/audiosense-pi.c                 |  248 +++\n sound/soc/bcm/digidac1-soundcard.c            |  421 +++++\n sound/soc/bcm/dionaudio_loco-v2.c             |  117 ++\n sound/soc/bcm/dionaudio_loco.c                |  117 ++\n sound/soc/bcm/fe-pi-audio.c                   |  154 ++\n sound/soc/bcm/googlevoicehat-codec.c          |  214 +++\n sound/soc/bcm/hifiberry_dacplus.c             |  424 +++++\n sound/soc/bcm/hifiberry_dacplusadc.c          |  398 +++++\n sound/soc/bcm/hifiberry_dacplusadcpro.c       |  543 +++++++\n sound/soc/bcm/hifiberry_dacplusdsp.c          |   90 ++\n sound/soc/bcm/hifiberry_dacplushd.c           |  238 +++\n sound/soc/bcm/i-sabre-q2m.c                   |  158 ++\n sound/soc/bcm/iqaudio-codec.c                 |  274 ++++\n sound/soc/bcm/iqaudio-dac.c                   |  223 +++\n sound/soc/bcm/justboom-both.c                 |  266 ++++\n sound/soc/bcm/justboom-dac.c                  |  147 ++\n sound/soc/bcm/pisound.c                       | 1238 +++++++++++++++\n sound/soc/bcm/rpi-cirrus.c                    | 1025 ++++++++++++\n sound/soc/bcm/rpi-proto.c                     |  147 ++\n sound/soc/bcm/rpi-simple-soundcard.c          |  339 ++++\n sound/soc/bcm/rpi-wm8804-soundcard.c          |  410 +++++\n sound/soc/codecs/Kconfig                      |   28 +-\n sound/soc/codecs/Makefile                     |    8 +\n sound/soc/codecs/cs42xx8-i2c.c                |    9 +-\n sound/soc/codecs/cs42xx8.c                    |    2 +\n sound/soc/codecs/i-sabre-codec.c              |  392 +++++\n sound/soc/codecs/i-sabre-codec.h              |   42 +\n sound/soc/codecs/ma120x0p.c                   | 1384 +++++++++++++++++\n sound/soc/codecs/pcm1794a.c                   |   69 +\n sound/soc/codecs/pcm512x.c                    |    2 +-\n sound/soc/codecs/tas5713.c                    |  363 +++++\n sound/soc/codecs/tas5713.h                    |  210 +++\n sound/soc/soc-core.c                          |   10 +-\n 49 files changed, 13837 insertions(+), 7 deletions(-)\n create mode 100644 Documentation/devicetree/bindings/vendor-prefixes.txt\n create mode 100644 drivers/clk/clk-allo-dac.c\n create mode 100644 drivers/clk/clk-hifiberry-dachd.c\n create mode 100644 drivers/clk/clk-hifiberry-dacpro.c\n create mode 100644 sound/soc/bcm/allo-boss-dac.c\n create mode 100644 sound/soc/bcm/allo-katana-codec.c\n create mode 100644 sound/soc/bcm/allo-piano-dac-plus.c\n create mode 100644 sound/soc/bcm/allo-piano-dac.c\n create mode 100644 sound/soc/bcm/audioinjector-isolated-soundcard.c\n create mode 100644 sound/soc/bcm/audioinjector-octo-soundcard.c\n create mode 100644 sound/soc/bcm/audioinjector-pi-soundcard.c\n create mode 100644 sound/soc/bcm/audiosense-pi.c\n create mode 100644 sound/soc/bcm/digidac1-soundcard.c\n create mode 100644 sound/soc/bcm/dionaudio_loco-v2.c\n create mode 100644 sound/soc/bcm/dionaudio_loco.c\n create mode 100644 sound/soc/bcm/fe-pi-audio.c\n create mode 100644 sound/soc/bcm/googlevoicehat-codec.c\n create mode 100644 sound/soc/bcm/hifiberry_dacplus.c\n create mode 100644 sound/soc/bcm/hifiberry_dacplusadc.c\n create mode 100644 sound/soc/bcm/hifiberry_dacplusadcpro.c\n create mode 100644 sound/soc/bcm/hifiberry_dacplusdsp.c\n create mode 100644 sound/soc/bcm/hifiberry_dacplushd.c\n create mode 100644 sound/soc/bcm/i-sabre-q2m.c\n create mode 100644 sound/soc/bcm/iqaudio-codec.c\n create mode 100644 sound/soc/bcm/iqaudio-dac.c\n create mode 100644 sound/soc/bcm/justboom-both.c\n create mode 100644 sound/soc/bcm/justboom-dac.c\n create mode 100644 sound/soc/bcm/pisound.c\n create mode 100644 sound/soc/bcm/rpi-cirrus.c\n create mode 100644 sound/soc/bcm/rpi-proto.c\n create mode 100644 sound/soc/bcm/rpi-simple-soundcard.c\n create mode 100644 sound/soc/bcm/rpi-wm8804-soundcard.c\n create mode 100644 sound/soc/codecs/i-sabre-codec.c\n create mode 100644 sound/soc/codecs/i-sabre-codec.h\n create mode 100644 sound/soc/codecs/ma120x0p.c\n create mode 100644 sound/soc/codecs/pcm1794a.c\n create mode 100644 sound/soc/codecs/tas5713.c\n create mode 100644 sound/soc/codecs/tas5713.h\n\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt\n@@ -0,0 +1,463 @@\n+Device tree binding vendor prefix registry.  Keep list in alphabetical order.\n+\n+This isn't an exhaustive list, but you should add new prefixes to it before\n+using them to avoid name-space collisions.\n+\n+abilis\tAbilis Systems\n+abracon\tAbracon Corporation\n+actions\tActions Semiconductor Co., Ltd.\n+active-semi\tActive-Semi International Inc\n+ad\tAvionic Design GmbH\n+adafruit\tAdafruit Industries, LLC\n+adapteva\tAdapteva, Inc.\n+adaptrum\tAdaptrum, Inc.\n+adh\tAD Holdings Plc.\n+adi\tAnalog Devices, Inc.\n+advantech\tAdvantech Corporation\n+aeroflexgaisler\tAeroflex Gaisler AB\n+al\tAnnapurna Labs\n+allo\tAllo.com\n+allwinner\tAllwinner Technology Co., Ltd.\n+alphascale\tAlphaScale Integrated Circuits Systems, Inc.\n+altr\tAltera Corp.\n+amarula\tAmarula Solutions\n+amazon\tAmazon.com, Inc.\n+amcc\tApplied Micro Circuits Corporation (APM, formally AMCC)\n+amd\tAdvanced Micro Devices (AMD), Inc.\n+amediatech\tShenzhen Amediatech Technology Co., Ltd\n+amlogic\tAmlogic, Inc.\n+ampire\tAmpire Co., Ltd.\n+ams\tAMS AG\n+amstaos\tAMS-Taos Inc.\n+analogix\tAnalogix Semiconductor, Inc.\n+andestech\tAndes Technology Corporation\n+apm\tApplied Micro Circuits Corporation (APM)\n+aptina\tAptina Imaging\n+arasan\tArasan Chip Systems\n+archermind ArcherMind Technology (Nanjing) Co., Ltd.\n+arctic\tArctic Sand\n+aries\tAries Embedded GmbH\n+arm\tARM Ltd.\n+armadeus\tARMadeus Systems SARL\n+arrow\tArrow Electronics\n+artesyn\tArtesyn Embedded Technologies Inc.\n+asahi-kasei\tAsahi Kasei Corp.\n+aspeed\tASPEED Technology Inc.\n+asus\tAsusTek Computer Inc.\n+atlas\tAtlas Scientific LLC\n+atmel\tAtmel Corporation\n+auo\tAU Optronics Corporation\n+auvidea Auvidea GmbH\n+avago\tAvago Technologies\n+avia\tavia semiconductor\n+avic\tShanghai AVIC Optoelectronics Co., Ltd.\n+avnet\tAvnet, Inc.\n+axentia\tAxentia Technologies AB\n+axis\tAxis Communications AB\n+bananapi BIPAI KEJI LIMITED\n+bhf\tBeckhoff Automation GmbH & Co. KG\n+bitmain\tBitmain Technologies\n+blokaslabs\tVilniaus Blokas UAB\n+boe\tBOE Technology Group Co., Ltd.\n+bosch\tBosch Sensortec GmbH\n+boundary\tBoundary Devices Inc.\n+brcm\tBroadcom Corporation\n+buffalo\tBuffalo, Inc.\n+bticino Bticino International\n+calxeda\tCalxeda\n+capella\tCapella Microsystems, Inc\n+cascoda\tCascoda, Ltd.\n+catalyst\tCatalyst Semiconductor, Inc.\n+cavium\tCavium, Inc.\n+cdns\tCadence Design Systems Inc.\n+cdtech\tCDTech(H.K.) Electronics Limited\n+ceva\tCeva, Inc.\n+chipidea\tChipidea, Inc\n+chipone\t\tChipOne\n+chipspark\tChipSPARK\n+chrp\tCommon Hardware Reference Platform\n+chunghwa\tChunghwa Picture Tubes Ltd.\n+ciaa\tComputadora Industrial Abierta Argentina\n+cirrus\tCirrus Logic, Inc.\n+cloudengines\tCloud Engines, Inc.\n+cnm\tChips&Media, Inc.\n+cnxt\tConexant Systems, Inc.\n+compulab\tCompuLab Ltd.\n+cortina\tCortina Systems, Inc.\n+cosmic\tCosmic Circuits\n+crane\tCrane Connectivity Solutions\n+creative\tCreative Technology Ltd\n+crystalfontz\tCrystalfontz America, Inc.\n+csky\tHangzhou C-SKY Microsystems Co., Ltd\n+cubietech\tCubietech, Ltd.\n+cypress\tCypress Semiconductor Corporation\n+cznic\tCZ.NIC, z.s.p.o.\n+dallas\tMaxim Integrated Products (formerly Dallas Semiconductor)\n+dataimage\tDataImage, Inc.\n+davicom\tDAVICOM Semiconductor, Inc.\n+delta\tDelta Electronics, Inc.\n+denx\tDenx Software Engineering\n+devantech\tDevantech, Ltd.\n+dh\tDH electronics GmbH\n+digi\tDigi International Inc.\n+digilent\tDiglent, Inc.\n+dioo\tDioo Microcircuit Co., Ltd\n+dlc\tDLC Display Co., Ltd.\n+dlg\tDialog Semiconductor\n+dlink\tD-Link Corporation\n+dmo\tData Modul AG\n+domintech\tDomintech Co., Ltd.\n+dongwoon\tDongwoon Anatech\n+dptechnics\tDPTechnics\n+dragino\tDragino Technology Co., Limited\n+ea\tEmbedded Artists AB\n+ebs-systart EBS-SYSTART GmbH\n+ebv\tEBV Elektronik\n+eckelmann\tEckelmann AG\n+edt\tEmerging Display Technologies\n+eeti\teGalax_eMPIA Technology Inc\n+elan\tElan Microelectronic Corp.\n+elgin\tElgin S/A.\n+embest\tShenzhen Embest Technology Co., Ltd.\n+emlid\tEmlid, Ltd.\n+emmicro\tEM Microelectronic\n+emtrion\temtrion GmbH\n+endless\tEndless Mobile, Inc.\n+energymicro\tSilicon Laboratories (formerly Energy Micro AS)\n+engicam\tEngicam S.r.l.\n+epcos\tEPCOS AG\n+epfl\tEcole Polytechnique Fédérale de Lausanne\n+epson\tSeiko Epson Corp.\n+est\tESTeem Wireless Modems\n+ettus\tNI Ettus Research\n+eukrea  Eukréa Electromatique\n+everest\tEverest Semiconductor Co. Ltd.\n+everspin\tEverspin Technologies, Inc.\n+exar\tExar Corporation\n+excito\tExcito\n+ezchip\tEZchip Semiconductor\n+facebook\tFacebook\n+fairphone\tFairphone B.V.\n+faraday\tFaraday Technology Corporation\n+fastrax\tFastrax Oy\n+fcs\tFairchild Semiconductor\n+feiyang\tShenzhen Fly Young Technology Co.,LTD.\n+firefly\tFirefly\n+focaltech\tFocalTech Systems Co.,Ltd\n+friendlyarm\tGuangzhou FriendlyARM Computer Tech Co., Ltd\n+fsl\tFreescale Semiconductor\n+fujitsu\tFujitsu Ltd.\n+gateworks\tGateworks Corporation\n+gcw Game Consoles Worldwide\n+ge\tGeneral Electric Company\n+geekbuying\tGeekBuying\n+gef\tGE Fanuc Intelligent Platforms Embedded Systems, Inc.\n+GEFanuc\tGE Fanuc Intelligent Platforms Embedded Systems, Inc.\n+geniatech\tGeniatech, Inc.\n+giantec\tGiantec Semiconductor, Inc.\n+giantplus\tGiantplus Technology Co., Ltd.\n+globalscale\tGlobalscale Technologies, Inc.\n+globaltop\tGlobalTop Technology, Inc.\n+gmt\tGlobal Mixed-mode Technology, Inc.\n+goodix\tShenzhen Huiding Technology Co., Ltd.\n+google\tGoogle, Inc.\n+grinn\tGrinn\n+grmn\tGarmin Limited\n+gumstix\tGumstix, Inc.\n+gw\tGateworks Corporation\n+hannstar\tHannStar Display Corporation\n+haoyu\tHaoyu Microelectronic Co. Ltd.\n+hardkernel\tHardkernel Co., Ltd\n+hideep\tHiDeep Inc.\n+himax\tHimax Technologies, Inc.\n+hisilicon\tHisilicon Limited.\n+hit\tHitachi Ltd.\n+hitex\tHitex Development Tools\n+holt\tHolt Integrated Circuits, Inc.\n+honeywell\tHoneywell\n+hp\tHewlett Packard\n+holtek\tHoltek Semiconductor, Inc.\n+hwacom\tHwaCom Systems Inc.\n+i2se\tI2SE GmbH\n+ibm\tInternational Business Machines (IBM)\n+icplus\tIC Plus Corp.\n+idt\tIntegrated Device Technologies, Inc.\n+ifi\tIngenieurburo Fur Ic-Technologie (I/F/I)\n+ilitek\tILI Technology Corporation (ILITEK)\n+img\tImagination Technologies Ltd.\n+infineon Infineon Technologies\n+inforce\tInforce Computing\n+ingenic\tIngenic Semiconductor\n+innolux\tInnolux Corporation\n+inside-secure\tINSIDE Secure\n+intel\tIntel Corporation\n+intercontrol\tInter Control Group\n+invensense\tInvenSense Inc.\n+inversepath\tInverse Path\n+iom\tIomega Corporation\n+isee\tISEE 2007 S.L.\n+isil\tIntersil\n+issi\tIntegrated Silicon Solutions Inc.\n+itead\tITEAD Intelligent Systems Co.Ltd\n+iwave  iWave Systems Technologies Pvt. Ltd.\n+jdi\tJapan Display Inc.\n+jedec\tJEDEC Solid State Technology Association\n+jianda\tJiandangjing Technology Co., Ltd.\n+karo\tKa-Ro electronics GmbH\n+keithkoep\tKeith & Koep GmbH\n+keymile\tKeymile GmbH\n+khadas\tKhadas\n+kiebackpeter    Kieback & Peter GmbH\n+kinetic Kinetic Technologies\n+kingdisplay\tKing & Display Technology Co., Ltd.\n+kingnovel\tKingnovel Technology Co., Ltd.\n+koe\tKaohsiung Opto-Electronics Inc.\n+kosagi\tSutajio Ko-Usagi PTE Ltd.\n+kyo\tKyocera Corporation\n+lacie\tLaCie\n+laird\tLaird PLC\n+lantiq\tLantiq Semiconductor\n+lattice\tLattice Semiconductor\n+lego\tLEGO Systems A/S\n+lemaker\tShenzhen LeMaker Technology Co., Ltd.\n+lenovo\tLenovo Group Ltd.\n+lg\tLG Corporation\n+libretech\tShenzhen Libre Technology Co., Ltd\n+licheepi\tLichee Pi\n+linaro\tLinaro Limited\n+linksys\tBelkin International, Inc. (Linksys)\n+linux\tLinux-specific binding\n+linx\tLinx Technologies\n+lltc\tLinear Technology Corporation\n+logicpd\tLogic PD, Inc.\n+lsi\tLSI Corp. (LSI Logic)\n+lwn\tLiebherr-Werk Nenzing GmbH\n+macnica\tMacnica Americas\n+marvell\tMarvell Technology Group Ltd.\n+maxim\tMaxim Integrated Products\n+mbvl\tMobiveil Inc.\n+mcube\tmCube\n+meas\tMeasurement Specialties\n+mediatek\tMediaTek Inc.\n+megachips\tMegaChips\n+mele\tShenzhen MeLE Digital Technology Ltd.\n+melexis\tMelexis N.V.\n+melfas\tMELFAS Inc.\n+mellanox\tMellanox Technologies\n+memsic\tMEMSIC Inc.\n+merrii\tMerrii Technology Co., Ltd.\n+micrel\tMicrel Inc.\n+microchip\tMicrochip Technology Inc.\n+microcrystal\tMicro Crystal AG\n+micron\tMicron Technology Inc.\n+mikroe\t\tMikroElektronika d.o.o.\n+minix\tMINIX Technology Ltd.\n+miramems\tMiraMEMS Sensing Technology Co., Ltd.\n+mitsubishi\tMitsubishi Electric Corporation\n+mosaixtech\tMosaix Technologies, Inc.\n+motorola\tMotorola, Inc.\n+moxa\tMoxa Inc.\n+mpl\tMPL AG\n+mqmaker\tmqmaker Inc.\n+mscc\tMicrosemi Corporation\n+msi\tMicro-Star International Co. Ltd.\n+mti\tImagination Technologies Ltd. (formerly MIPS Technologies Inc.)\n+multi-inno\tMulti-Inno Technology Co.,Ltd\n+mundoreader\tMundo Reader S.L.\n+murata\tMurata Manufacturing Co., Ltd.\n+mxicy\tMacronix International Co., Ltd.\n+myir\tMYIR Tech Limited\n+national\tNational Semiconductor\n+nec\tNEC LCD Technologies, Ltd.\n+neonode\t\tNeonode Inc.\n+netgear\tNETGEAR\n+netlogic\tBroadcom Corporation (formerly NetLogic Microsystems)\n+netron-dy\tNetron DY\n+netxeon\t\tShenzhen Netxeon Technology CO., LTD\n+nexbox\tNexbox\n+nextthing\tNext Thing Co.\n+newhaven\tNewhaven Display International\n+ni\tNational Instruments\n+nintendo\tNintendo\n+nlt\tNLT Technologies, Ltd.\n+nokia\tNokia\n+nordic\tNordic Semiconductor\n+novtech NovTech, Inc.\n+nutsboard\tNutsBoard\n+nuvoton\tNuvoton Technology Corporation\n+nvd\tNew Vision Display\n+nvidia\tNVIDIA\n+nxp\tNXP Semiconductors\n+okaya\tOkaya Electric America, Inc.\n+oki\tOki Electric Industry Co., Ltd.\n+olimex\tOLIMEX Ltd.\n+olpc\tOne Laptop Per Child\n+onion\tOnion Corporation\n+onnn\tON Semiconductor Corp.\n+ontat\tOn Tat Industrial Company\n+opalkelly\tOpal Kelly Incorporated\n+opencores\tOpenCores.org\n+openrisc\tOpenRISC.io\n+option\tOption NV\n+oranth\tShenzhen Oranth Technology Co., Ltd.\n+ORCL\tOracle Corporation\n+orisetech\tOrise Technology\n+ortustech\tOrtus Technology Co., Ltd.\n+ovti\tOmniVision Technologies\n+oxsemi\tOxford Semiconductor, Ltd.\n+panasonic\tPanasonic Corporation\n+parade\tParade Technologies Inc.\n+pda\tPrecision Design Associates, Inc.\n+pericom\tPericom Technology Inc.\n+pervasive\tPervasive Displays, Inc.\n+phicomm PHICOMM Co., Ltd.\n+phytec\tPHYTEC Messtechnik GmbH\n+picochip\tPicochip Ltd\n+pine64\tPine64\n+pixcir  PIXCIR MICROELECTRONICS Co., Ltd\n+plantower Plantower Co., Ltd\n+plathome\tPlat'Home Co., Ltd.\n+plda\tPLDA\n+plx\tBroadcom Corporation (formerly PLX Technology)\n+pni\tPNI Sensor Corporation\n+portwell\tPortwell Inc.\n+poslab\tPoslab Technology Co., Ltd.\n+powervr\tPowerVR (deprecated, use img)\n+probox2\tPROBOX2 (by W2COMP Co., Ltd.)\n+pulsedlight\tPulsedLight, Inc\n+qca\tQualcomm Atheros, Inc.\n+qcom\tQualcomm Technologies, Inc\n+qemu\tQEMU, a generic and open source machine emulator and virtualizer\n+qi\tQi Hardware\n+qiaodian\tQiaoDian XianShi Corporation\n+qnap\tQNAP Systems, Inc.\n+radxa\tRadxa\n+raidsonic\tRaidSonic Technology GmbH\n+ralink\tMediatek/Ralink Technology Corp.\n+ramtron\tRamtron International\n+raspberrypi\tRaspberry Pi Foundation\n+raydium\tRaydium Semiconductor Corp.\n+rda\tUnisoc Communications, Inc.\n+realtek Realtek Semiconductor Corp.\n+renesas\tRenesas Electronics Corporation\n+richtek\tRichtek Technology Corporation\n+ricoh\tRicoh Co. Ltd.\n+rikomagic\tRikomagic Tech Corp. Ltd\n+riscv\tRISC-V Foundation\n+rockchip\tFuzhou Rockchip Electronics Co., Ltd\n+rohm\tROHM Semiconductor Co., Ltd\n+roofull\tShenzhen Roofull Technology Co, Ltd\n+samsung\tSamsung Semiconductor\n+samtec\tSamtec/Softing company\n+sancloud\tSancloud Ltd\n+sandisk\tSandisk Corporation\n+sbs\tSmart Battery System\n+schindler\tSchindler\n+seagate\tSeagate Technology PLC\n+semtech\tSemtech Corporation\n+sensirion\tSensirion AG\n+sff\tSmall Form Factor Committee\n+sgd\tSolomon Goldentek Display Corporation\n+sgx\tSGX Sensortech\n+sharp\tSharp Corporation\n+shimafuji\tShimafuji Electric, Inc.\n+si-en\tSi-En Technology Ltd.\n+sifive\tSiFive, Inc.\n+sigma\tSigma Designs, Inc.\n+sii\tSeiko Instruments, Inc.\n+sil\tSilicon Image\n+silabs\tSilicon Laboratories\n+silead\tSilead Inc.\n+silergy\tSilergy Corp.\n+siliconmitus\tSilicon Mitus, Inc.\n+simtek\n+sirf\tSiRF Technology, Inc.\n+sis\tSilicon Integrated Systems Corp.\n+sitronix\tSitronix Technology Corporation\n+skyworks\tSkyworks Solutions, Inc.\n+smsc\tStandard Microsystems Corporation\n+snps\tSynopsys, Inc.\n+socionext\tSocionext Inc.\n+solidrun\tSolidRun\n+solomon        Solomon Systech Limited\n+sony\tSony Corporation\n+spansion\tSpansion Inc.\n+sprd\tSpreadtrum Communications Inc.\n+sst\tSilicon Storage Technology, Inc.\n+st\tSTMicroelectronics\n+starry\tStarry Electronic Technology (ShenZhen) Co., LTD\n+startek\tStartek\n+ste\tST-Ericsson\n+stericsson\tST-Ericsson\n+summit\tSummit microelectronics\n+sunchip\tShenzhen Sunchip Technology Co., Ltd\n+SUNW\tSun Microsystems, Inc\n+swir\tSierra Wireless\n+syna\tSynaptics Inc.\n+synology\tSynology, Inc.\n+tbs\tTBS Technologies\n+tbs-biometrics\tTouchless Biometric Systems AG\n+tcg\tTrusted Computing Group\n+tcl\tToby Churchill Ltd.\n+technexion\tTechNexion\n+technologic\tTechnologic Systems\n+tempo\tTempo Semiconductor\n+techstar\tShenzhen Techstar Electronics Co., Ltd.\n+terasic\tTerasic Inc.\n+thine\tTHine Electronics, Inc.\n+ti\tTexas Instruments\n+tianma\tTianma Micro-electronics Co., Ltd.\n+tlm\tTrusted Logic Mobility\n+tmt\tTecon Microprocessor Technologies, LLC.\n+topeet  Topeet\n+toradex\tToradex AG\n+toshiba\tToshiba Corporation\n+toumaz\tToumaz\n+tpk\tTPK U.S.A. LLC\n+tplink\tTP-LINK Technologies Co., Ltd.\n+tpo\tTPO\n+tronfy\tTronfy\n+tronsmart\tTronsmart\n+truly\tTruly Semiconductors Limited\n+tsd\tTheobroma Systems Design und Consulting GmbH\n+tyan\tTyan Computer Corporation\n+u-blox\tu-blox\n+ucrobotics\tuCRobotics\n+ubnt\tUbiquiti Networks\n+udoo\tUdoo\n+uniwest\tUnited Western Technologies Corp (UniWest)\n+upisemi\tuPI Semiconductor Corp.\n+urt\tUnited Radiant Technology Corporation\n+usi\tUniversal Scientific Industrial Co., Ltd.\n+v3\tV3 Semiconductor\n+vamrs\tVamrs Ltd.\n+variscite\tVariscite Ltd.\n+via\tVIA Technologies, Inc.\n+virtio\tVirtual I/O Device Specification, developed by the OASIS consortium\n+vishay\tVishay Intertechnology, Inc\n+vitesse\tVitesse Semiconductor Corporation\n+vivante\tVivante Corporation\n+vocore VoCore Studio\n+voipac\tVoipac Technologies s.r.o.\n+vot\tVision Optical Technology Co., Ltd.\n+wd\tWestern Digital Corp.\n+wetek\tWeTek Electronics, limited.\n+wexler\tWexler\n+whwave  Shenzhen whwave Electronics, Inc.\n+wi2wi\tWi2Wi, Inc.\n+winbond Winbond Electronics corp.\n+winstar\tWinstar Display Corp.\n+wlf\tWolfson Microelectronics\n+wm\tWondermedia Technologies, Inc.\n+x-powers\tX-Powers\n+xes\tExtreme Engineering Solutions (X-ES)\n+xillybus\tXillybus Ltd.\n+xlnx\tXilinx\n+xunlong\tShenzhen Xunlong Software CO.,Limited\n+ysoft\tY Soft Corporation a.s.\n+zarlink\tZarlink Semiconductor\n+zeitec\tZEITEC Semiconductor Co., LTD.\n+zidoo\tShenzhen Zidoo Technology Co., Ltd.\n+zii\tZodiac Inflight Innovations\n+zte\tZTE Corp.\n+zyxel\tZyXEL Communications Corp.\n--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml\n+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml\n@@ -159,6 +159,8 @@ patternProperties:\n     description: Beckhoff Automation GmbH & Co. KG\n   \"^bitmain,.*\":\n     description: Bitmain Technologies\n+  \"^blokaslabs,.*\":\n+    description: Vilniaus Blokas UAB\n   \"^boe,.*\":\n     description: BOE Technology Group Co., Ltd.\n   \"^bosch,.*\":\n--- a/drivers/clk/Kconfig\n+++ b/drivers/clk/Kconfig\n@@ -86,6 +86,12 @@ config COMMON_CLK_HI655X\n \t  multi-function device has one fixed-rate oscillator, clocked\n \t  at 32KHz.\n \n+config COMMON_CLK_HIFIBERRY_DACPLUSHD\n+\ttristate\n+\n+config COMMON_CLK_HIFIBERRY_DACPRO\n+\ttristate\n+\n config COMMON_CLK_SCMI\n \ttristate \"Clock driver controlled via SCMI interface\"\n \tdepends on ARM_SCMI_PROTOCOL || COMPILE_TEST\n--- a/drivers/clk/Makefile\n+++ b/drivers/clk/Makefile\n@@ -18,6 +18,7 @@ endif\n \n # hardware specific clock types\n # please keep this section sorted lexicographically by file path name\n+obj-$(CONFIG_SND_BCM2708_SOC_ALLO_BOSS_DAC)\t+= clk-allo-dac.o\n obj-$(CONFIG_MACH_ASM9260)\t\t+= clk-asm9260.o\n obj-$(CONFIG_COMMON_CLK_AXI_CLKGEN)\t+= clk-axi-clkgen.o\n obj-$(CONFIG_ARCH_AXXIA)\t\t+= clk-axm5516.o\n@@ -37,6 +38,8 @@ obj-$(CONFIG_MACH_ASPEED_G6)\t\t+= clk-ast\n obj-$(CONFIG_ARCH_HIGHBANK)\t\t+= clk-highbank.o\n obj-$(CONFIG_CLK_HSDK)\t\t\t+= clk-hsdk-pll.o\n obj-$(CONFIG_COMMON_CLK_LOCHNAGAR)\t+= clk-lochnagar.o\n+obj-$(CONFIG_COMMON_CLK_HIFIBERRY_DACPRO)\t+= clk-hifiberry-dacpro.o\n+obj-$(CONFIG_COMMON_CLK_HIFIBERRY_DACPLUSHD)\t+= clk-hifiberry-dachd.o\n obj-$(CONFIG_COMMON_CLK_MAX77686)\t+= clk-max77686.o\n obj-$(CONFIG_COMMON_CLK_MAX9485)\t+= clk-max9485.o\n obj-$(CONFIG_ARCH_MILBEAUT_M10V)\t+= clk-milbeaut.o\n--- /dev/null\n+++ b/drivers/clk/clk-allo-dac.c\n@@ -0,0 +1,161 @@\n+/*\n+ * Clock Driver for Allo DAC\n+ *\n+ * Author:\tBaswaraj K <jaikumar@cem-solutions.net>\n+ *\t\tCopyright 2016\n+ *\t\tbased on code by Stuart MacLean\n+ *\n+ * This program is free software; you can redistribute it and/or\n+ * modify it under the terms of the GNU General Public License\n+ * version 2 as published by the Free Software Foundation.\n+ *\n+ * This program is distributed in the hope that it will be useful, but\n+ * WITHOUT ANY WARRANTY; without even the implied warranty of\n+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\n+ * General Public License for more details.\n+ */\n+\n+#include <linux/clk-provider.h>\n+#include <linux/clkdev.h>\n+#include <linux/kernel.h>\n+#include <linux/module.h>\n+#include <linux/of.h>\n+#include <linux/slab.h>\n+#include <linux/platform_device.h>\n+\n+/* Clock rate of CLK44EN attached to GPIO6 pin */\n+#define CLK_44EN_RATE 45158400UL\n+/* Clock rate of CLK48EN attached to GPIO3 pin */\n+#define CLK_48EN_RATE 49152000UL\n+\n+/**\n+ * struct allo_dac_clk - Common struct to the Allo DAC\n+ * @hw: clk_hw for the common clk framework\n+ * @mode: 0 => CLK44EN, 1 => CLK48EN\n+ */\n+struct clk_allo_hw {\n+\tstruct clk_hw hw;\n+\tuint8_t mode;\n+};\n+\n+#define to_allo_clk(_hw) container_of(_hw, struct clk_allo_hw, hw)\n+\n+static const struct of_device_id clk_allo_dac_dt_ids[] = {\n+\t{ .compatible = \"allo,dac-clk\",},\n+\t{ }\n+};\n+MODULE_DEVICE_TABLE(of, clk_allo_dac_dt_ids);\n+\n+static unsigned long clk_allo_dac_recalc_rate(struct clk_hw *hw,\n+\tunsigned long parent_rate)\n+{\n+\treturn (to_allo_clk(hw)->mode == 0) ? CLK_44EN_RATE :\n+\t\tCLK_48EN_RATE;\n+}\n+\n+static long clk_allo_dac_round_rate(struct clk_hw *hw,\n+\tunsigned long rate, unsigned long *parent_rate)\n+{\n+\tlong actual_rate;\n+\n+\tif (rate <= CLK_44EN_RATE) {\n+\t\tactual_rate = (long)CLK_44EN_RATE;\n+\t} else if (rate >= CLK_48EN_RATE) {\n+\t\tactual_rate = (long)CLK_48EN_RATE;\n+\t} else {\n+\t\tlong diff44Rate = (long)(rate - CLK_44EN_RATE);\n+\t\tlong diff48Rate = (long)(CLK_48EN_RATE - rate);\n+\n+\t\tif (diff44Rate < diff48Rate)\n+\t\t\tactual_rate = (long)CLK_44EN_RATE;\n+\t\telse\n+\t\t\tactual_rate = (long)CLK_48EN_RATE;\n+\t}\n+\treturn actual_rate;\n+}\n+\n+\n+static int clk_allo_dac_set_rate(struct clk_hw *hw,\n+\tunsigned long rate, unsigned long parent_rate)\n+{\n+\tunsigned long actual_rate;\n+\tstruct clk_allo_hw *clk = to_allo_clk(hw);\n+\n+\tactual_rate = (unsigned long)clk_allo_dac_round_rate(hw, rate,\n+\t\t&parent_rate);\n+\tclk->mode = (actual_rate == CLK_44EN_RATE) ? 0 : 1;\n+\treturn 0;\n+}\n+\n+\n+const struct clk_ops clk_allo_dac_rate_ops = {\n+\t.recalc_rate = clk_allo_dac_recalc_rate,\n+\t.round_rate = clk_allo_dac_round_rate,\n+\t.set_rate = clk_allo_dac_set_rate,\n+};\n+\n+static int clk_allo_dac_probe(struct platform_device *pdev)\n+{\n+\tint ret;\n+\tstruct clk_allo_hw *proclk;\n+\tstruct clk *clk;\n+\tstruct device *dev;\n+\tstruct clk_init_data init;\n+\n+\tdev = &pdev->dev;\n+\n+\tproclk = kzalloc(sizeof(struct clk_allo_hw), GFP_KERNEL);\n+\tif (!proclk)\n+\t\treturn -ENOMEM;\n+\n+\tinit.name = \"clk-allo-dac\";\n+\tinit.ops = &clk_allo_dac_rate_ops;\n+\tinit.flags = 0;\n+\tinit.parent_names = NULL;\n+\tinit.num_parents = 0;\n+\n+\tproclk->mode = 0;\n+\tproclk->hw.init = &init;\n+\n+\tclk = devm_clk_register(dev, &proclk->hw);\n+\tif (!IS_ERR(clk)) {\n+\t\tret = of_clk_add_provider(dev->of_node, of_clk_src_simple_get,\n+\t\t\tclk);\n+\t} else {\n+\t\tdev_err(dev, \"Fail to register clock driver\\n\");\n+\t\tkfree(proclk);\n+\t\tret = PTR_ERR(clk);\n+\t}\n+\treturn ret;\n+}\n+\n+static int clk_allo_dac_remove(struct platform_device *pdev)\n+{\n+\tof_clk_del_provider(pdev->dev.of_node);\n+\treturn 0;\n+}\n+\n+static struct platform_driver clk_allo_dac_driver = {\n+\t.probe = clk_allo_dac_probe,\n+\t.remove = clk_allo_dac_remove,\n+\t.driver = {\n+\t\t.name = \"clk-allo-dac\",\n+\t\t.of_match_table = clk_allo_dac_dt_ids,\n+\t},\n+};\n+\n+static int __init clk_allo_dac_init(void)\n+{\n+\treturn platform_driver_register(&clk_allo_dac_driver);\n+}\n+core_initcall(clk_allo_dac_init);\n+\n+static void __exit clk_allo_dac_exit(void)\n+{\n+\tplatform_driver_unregister(&clk_allo_dac_driver);\n+}\n+module_exit(clk_allo_dac_exit);\n+\n+MODULE_DESCRIPTION(\"Allo DAC clock driver\");\n+MODULE_LICENSE(\"GPL v2\");\n+MODULE_ALIAS(\"platform:clk-allo-dac\");\n--- /dev/null\n+++ b/drivers/clk/clk-hifiberry-dachd.c\n@@ -0,0 +1,333 @@\n+// SPDX-License-Identifier: GPL-2.0\n+/*\n+ * Clock Driver for HiFiBerry DAC+ HD\n+ *\n+ * Author: Joerg Schambacher, i2Audio GmbH for HiFiBerry\n+ *         Copyright 2020\n+ *\n+ * This program is free software; you can redistribute it and/or\n+ * modify it under the terms of the GNU General Public License\n+ * version 2 as published by the Free Software Foundation.\n+ *\n+ * This program is distributed in the hope that it will be useful, but\n+ * WITHOUT ANY WARRANTY; without even the implied warranty of\n+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\n+ * General Public License for more details.\n+ */\n+\n+#include <linux/clk-provider.h>\n+#include <linux/clk.h>\n+#include <linux/kernel.h>\n+#include <linux/module.h>\n+#include <linux/of.h>\n+#include <linux/slab.h>\n+#include <linux/platform_device.h>\n+#include <linux/i2c.h>\n+#include <linux/regmap.h>\n+\n+#define NO_PLL_RESET\t\t\t0\n+#define PLL_RESET\t\t\t1\n+#define HIFIBERRY_PLL_MAX_REGISTER\t256\n+#define DEFAULT_RATE\t\t\t44100\n+\n+static struct reg_default hifiberry_pll_reg_defaults[] = {\n+\t{0x02, 0x53}, {0x03, 0x00}, {0x07, 0x20}, {0x0F, 0x00},\n+\t{0x10, 0x0D}, {0x11, 0x1D}, {0x12, 0x0D}, {0x13, 0x8C},\n+\t{0x14, 0x8C}, {0x15, 0x8C}, {0x16, 0x8C}, {0x17, 0x8C},\n+\t{0x18, 0x2A}, {0x1C, 0x00}, {0x1D, 0x0F}, {0x1F, 0x00},\n+\t{0x2A, 0x00}, {0x2C, 0x00}, {0x2F, 0x00}, {0x30, 0x00},\n+\t{0x31, 0x00}, {0x32, 0x00}, {0x34, 0x00}, {0x37, 0x00},\n+\t{0x38, 0x00}, {0x39, 0x00}, {0x3A, 0x00}, {0x3B, 0x01},\n+\t{0x3E, 0x00}, {0x3F, 0x00}, {0x40, 0x00}, {0x41, 0x00},\n+\t{0x5A, 0x00}, {0x5B, 0x00}, {0x95, 0x00}, {0x96, 0x00},\n+\t{0x97, 0x00}, {0x98, 0x00}, {0x99, 0x00}, {0x9A, 0x00},\n+\t{0x9B, 0x00}, {0xA2, 0x00}, {0xA3, 0x00}, {0xA4, 0x00},\n+\t{0xB7, 0x92},\n+\t{0x1A, 0x3D}, {0x1B, 0x09}, {0x1E, 0xF3}, {0x20, 0x13},\n+\t{0x21, 0x75}, {0x2B, 0x04}, {0x2D, 0x11}, {0x2E, 0xE0},\n+\t{0x3D, 0x7A},\n+\t{0x35, 0x9D}, {0x36, 0x00}, {0x3C, 0x42},\n+\t{ 177, 0xAC},\n+};\n+static struct reg_default common_pll_regs[HIFIBERRY_PLL_MAX_REGISTER];\n+static int num_common_pll_regs;\n+static struct reg_default dedicated_192k_pll_regs[HIFIBERRY_PLL_MAX_REGISTER];\n+static int num_dedicated_192k_pll_regs;\n+static struct reg_default dedicated_96k_pll_regs[HIFIBERRY_PLL_MAX_REGISTER];\n+static int num_dedicated_96k_pll_regs;\n+static struct reg_default dedicated_48k_pll_regs[HIFIBERRY_PLL_MAX_REGISTER];\n+static int num_dedicated_48k_pll_regs;\n+static struct reg_default dedicated_176k4_pll_regs[HIFIBERRY_PLL_MAX_REGISTER];\n+static int num_dedicated_176k4_pll_regs;\n+static struct reg_default dedicated_88k2_pll_regs[HIFIBERRY_PLL_MAX_REGISTER];\n+static int num_dedicated_88k2_pll_regs;\n+static struct reg_default dedicated_44k1_pll_regs[HIFIBERRY_PLL_MAX_REGISTER];\n+static int num_dedicated_44k1_pll_regs;\n+\n+/**\n+ * struct clk_hifiberry_drvdata - Common struct to the HiFiBerry DAC HD Clk\n+ * @hw: clk_hw for the common clk framework\n+ */\n+struct clk_hifiberry_drvdata {\n+\tstruct regmap *regmap;\n+\tstruct clk *clk;\n+\tstruct clk_hw hw;\n+\tunsigned long rate;\n+};\n+\n+#define to_hifiberry_clk(_hw) \\\n+\tcontainer_of(_hw, struct clk_hifiberry_drvdata, hw)\n+\n+static int clk_hifiberry_dachd_write_pll_regs(struct regmap *regmap,\n+\t\t\t\tstruct reg_default *regs,\n+\t\t\t\tint num, int do_pll_reset)\n+{\n+\tint i;\n+\tint ret = 0;\n+\tchar pll_soft_reset[] = { 177, 0xAC, };\n+\n+\tfor (i = 0; i < num; i++) {\n+\t\tret |= regmap_write(regmap, regs[i].reg, regs[i].def);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\t}\n+\tif (do_pll_reset) {\n+\t\tret |= regmap_write(regmap, pll_soft_reset[0],\n+\t\t\t\t\t\tpll_soft_reset[1]);\n+\t\tmdelay(10);\n+\t}\n+\treturn ret;\n+}\n+\n+static unsigned long clk_hifiberry_dachd_recalc_rate(struct clk_hw *hw,\n+\tunsigned long parent_rate)\n+{\n+\treturn to_hifiberry_clk(hw)->rate;\n+}\n+\n+static long clk_hifiberry_dachd_round_rate(struct clk_hw *hw,\n+\tunsigned long rate, unsigned long *parent_rate)\n+{\n+\treturn rate;\n+}\n+\n+static int clk_hifiberry_dachd_set_rate(struct clk_hw *hw,\n+\tunsigned long rate, unsigned long parent_rate)\n+{\n+\tint ret;\n+\tstruct clk_hifiberry_drvdata *drvdata = to_hifiberry_clk(hw);\n+\n+\tswitch (rate) {\n+\tcase 44100:\n+\t\tret = clk_hifiberry_dachd_write_pll_regs(drvdata->regmap,\n+\t\t\tdedicated_44k1_pll_regs, num_dedicated_44k1_pll_regs,\n+\t\t\tPLL_RESET);\n+\t\tbreak;\n+\tcase 88200:\n+\t\tret = clk_hifiberry_dachd_write_pll_regs(drvdata->regmap,\n+\t\t\tdedicated_88k2_pll_regs, num_dedicated_88k2_pll_regs,\n+\t\t\tPLL_RESET);\n+\t\tbreak;\n+\tcase 176400:\n+\t\tret = clk_hifiberry_dachd_write_pll_regs(drvdata->regmap,\n+\t\t\tdedicated_176k4_pll_regs, num_dedicated_176k4_pll_regs,\n+\t\t\tPLL_RESET);\n+\t\tbreak;\n+\tcase 48000:\n+\t\tret = clk_hifiberry_dachd_write_pll_regs(drvdata->regmap,\n+\t\t\tdedicated_48k_pll_regs,\tnum_dedicated_48k_pll_regs,\n+\t\t\tPLL_RESET);\n+\t\tbreak;\n+\tcase 96000:\n+\t\tret = clk_hifiberry_dachd_write_pll_regs(drvdata->regmap,\n+\t\t\tdedicated_96k_pll_regs,\tnum_dedicated_96k_pll_regs,\n+\t\t\tPLL_RESET);\n+\t\tbreak;\n+\tcase 192000:\n+\t\tret = clk_hifiberry_dachd_write_pll_regs(drvdata->regmap,\n+\t\t\tdedicated_192k_pll_regs, num_dedicated_192k_pll_regs,\n+\t\t\tPLL_RESET);\n+\t\tbreak;\n+\tdefault:\n+\t\tret = -EINVAL;\n+\t\tbreak;\n+\t}\n+\tto_hifiberry_clk(hw)->rate = rate;\n+\n+\treturn ret;\n+}\n+\n+const struct clk_ops clk_hifiberry_dachd_rate_ops = {\n+\t.recalc_rate = clk_hifiberry_dachd_recalc_rate,\n+\t.round_rate = clk_hifiberry_dachd_round_rate,\n+\t.set_rate = clk_hifiberry_dachd_set_rate,\n+};\n+\n+static int clk_hifiberry_get_prop_values(struct device *dev,\n+\t\t\t\t\tchar *prop_name,\n+\t\t\t\t\tstruct reg_default *regs)\n+{\n+\tint ret;\n+\tint i;\n+\tu8 tmp[2 * HIFIBERRY_PLL_MAX_REGISTER];\n+\n+\tret = of_property_read_variable_u8_array(dev->of_node, prop_name,\n+\t\t\ttmp, 0, 2 * HIFIBERRY_PLL_MAX_REGISTER);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\tif (ret & 1) {\n+\t\tdev_err(dev,\n+\t\t\t\"%s <%s> -> #%i odd number of bytes for reg/val pairs!\",\n+\t\t\t__func__,\n+\t\t\tprop_name,\n+\t\t\tret);\n+\t\treturn -EINVAL;\n+\t}\n+\tret /= 2;\n+\tfor (i = 0; i < ret; i++) {\n+\t\tregs[i].reg = (u32)tmp[2 * i];\n+\t\tregs[i].def = (u32)tmp[2 * i + 1];\n+\t}\n+\treturn ret;\n+}\n+\n+\n+static int clk_hifiberry_dachd_dt_parse(struct device *dev)\n+{\n+\tnum_common_pll_regs = clk_hifiberry_get_prop_values(dev,\n+\t\t\t\t\"common_pll_regs\", common_pll_regs);\n+\tnum_dedicated_44k1_pll_regs = clk_hifiberry_get_prop_values(dev,\n+\t\t\t\t\"44k1_pll_regs\", dedicated_44k1_pll_regs);\n+\tnum_dedicated_88k2_pll_regs = clk_hifiberry_get_prop_values(dev,\n+\t\t\t\t\"88k2_pll_regs\", dedicated_88k2_pll_regs);\n+\tnum_dedicated_176k4_pll_regs = clk_hifiberry_get_prop_values(dev,\n+\t\t\t\t\"176k4_pll_regs\", dedicated_176k4_pll_regs);\n+\tnum_dedicated_48k_pll_regs = clk_hifiberry_get_prop_values(dev,\n+\t\t\t\t\"48k_pll_regs\", dedicated_48k_pll_regs);\n+\tnum_dedicated_96k_pll_regs = clk_hifiberry_get_prop_values(dev,\n+\t\t\t\t\"96k_pll_regs\", dedicated_96k_pll_regs);\n+\tnum_dedicated_192k_pll_regs = clk_hifiberry_get_prop_values(dev,\n+\t\t\t\t\"192k_pll_regs\", dedicated_192k_pll_regs);\n+\treturn 0;\n+}\n+\n+\n+static int clk_hifiberry_dachd_remove(struct device *dev)\n+{\n+\tof_clk_del_provider(dev->of_node);\n+\treturn 0;\n+}\n+\n+const struct regmap_config hifiberry_pll_regmap = {\n+\t.reg_bits = 8,\n+\t.val_bits = 8,\n+\t.max_register = HIFIBERRY_PLL_MAX_REGISTER,\n+\t.reg_defaults = hifiberry_pll_reg_defaults,\n+\t.num_reg_defaults = ARRAY_SIZE(hifiberry_pll_reg_defaults),\n+\t.cache_type = REGCACHE_RBTREE,\n+};\n+EXPORT_SYMBOL_GPL(hifiberry_pll_regmap);\n+\n+\n+static int clk_hifiberry_dachd_i2c_probe(struct i2c_client *i2c,\n+\t\t\t     const struct i2c_device_id *id)\n+{\n+\tstruct clk_hifiberry_drvdata *hdclk;\n+\tint ret = 0;\n+\tstruct clk_init_data init;\n+\tstruct device *dev = &i2c->dev;\n+\tstruct device_node *dev_node = dev->of_node;\n+\tstruct regmap_config config = hifiberry_pll_regmap;\n+\n+\thdclk = devm_kzalloc(&i2c->dev,\n+\t\t\tsizeof(struct clk_hifiberry_drvdata), GFP_KERNEL);\n+\tif (!hdclk)\n+\t\treturn -ENOMEM;\n+\n+\ti2c_set_clientdata(i2c, hdclk);\n+\n+\thdclk->regmap = devm_regmap_init_i2c(i2c, &config);\n+\n+\tif (IS_ERR(hdclk->regmap))\n+\t\treturn PTR_ERR(hdclk->regmap);\n+\n+\t/* start PLL to allow detection of DAC */\n+\tret = clk_hifiberry_dachd_write_pll_regs(hdclk->regmap,\n+\t\t\t\thifiberry_pll_reg_defaults,\n+\t\t\t\tARRAY_SIZE(hifiberry_pll_reg_defaults),\n+\t\t\t\tPLL_RESET);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tclk_hifiberry_dachd_dt_parse(dev);\n+\n+\t/* restart PLL with configs from DTB */\n+\tret = clk_hifiberry_dachd_write_pll_regs(hdclk->regmap, common_pll_regs,\n+\t\t\t\t\tnum_common_pll_regs, PLL_RESET);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tinit.name = \"clk-hifiberry-dachd\";\n+\tinit.ops = &clk_hifiberry_dachd_rate_ops;\n+\tinit.flags = 0;\n+\tinit.parent_names = NULL;\n+\tinit.num_parents = 0;\n+\n+\thdclk->hw.init = &init;\n+\n+\thdclk->clk = devm_clk_register(dev, &hdclk->hw);\n+\tif (IS_ERR(hdclk->clk)) {\n+\t\tdev_err(dev, \"unable to register %s\\n\",\tinit.name);\n+\t\treturn PTR_ERR(hdclk->clk);\n+\t}\n+\n+\tret = of_clk_add_provider(dev_node, of_clk_src_simple_get, hdclk->clk);\n+\tif (ret != 0) {\n+\t\tdev_err(dev, \"Cannot of_clk_add_provider\");\n+\t\treturn ret;\n+\t}\n+\n+\tret = clk_set_rate(hdclk->hw.clk, DEFAULT_RATE);\n+\tif (ret != 0) {\n+\t\tdev_err(dev, \"Cannot set rate : %d\\n\",\tret);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\treturn ret;\n+}\n+\n+static int clk_hifiberry_dachd_i2c_remove(struct i2c_client *i2c)\n+{\n+\tclk_hifiberry_dachd_remove(&i2c->dev);\n+\treturn 0;\n+}\n+\n+static const struct i2c_device_id clk_hifiberry_dachd_i2c_id[] = {\n+\t{ \"dachd-clk\", },\n+\t{ }\n+};\n+MODULE_DEVICE_TABLE(i2c, clk_hifiberry_dachd_i2c_id);\n+\n+static const struct of_device_id clk_hifiberry_dachd_of_match[] = {\n+\t{ .compatible = \"hifiberry,dachd-clk\", },\n+\t{ }\n+};\n+MODULE_DEVICE_TABLE(of, clk_hifiberry_dachd_of_match);\n+\n+static struct i2c_driver clk_hifiberry_dachd_i2c_driver = {\n+\t.probe\t\t= clk_hifiberry_dachd_i2c_probe,\n+\t.remove\t\t= clk_hifiberry_dachd_i2c_remove,\n+\t.id_table\t= clk_hifiberry_dachd_i2c_id,\n+\t.driver\t\t= {\n+\t\t.name\t= \"dachd-clk\",\n+\t\t.of_match_table = of_match_ptr(clk_hifiberry_dachd_of_match),\n+\t},\n+};\n+\n+module_i2c_driver(clk_hifiberry_dachd_i2c_driver);\n+\n+\n+MODULE_DESCRIPTION(\"HiFiBerry DAC+ HD clock driver\");\n+MODULE_AUTHOR(\"Joerg Schambacher <joerg@i2audio.com>\");\n+MODULE_LICENSE(\"GPL v2\");\n+MODULE_ALIAS(\"platform:clk-hifiberry-dachd\");\n--- /dev/null\n+++ b/drivers/clk/clk-hifiberry-dacpro.c\n@@ -0,0 +1,160 @@\n+/*\n+ * Clock Driver for HiFiBerry DAC Pro\n+ *\n+ * Author: Stuart MacLean\n+ *         Copyright 2015\n+ *\n+ * This program is free software; you can redistribute it and/or\n+ * modify it under the terms of the GNU General Public License\n+ * version 2 as published by the Free Software Foundation.\n+ *\n+ * This program is distributed in the hope that it will be useful, but\n+ * WITHOUT ANY WARRANTY; without even the implied warranty of\n+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\n+ * General Public License for more details.\n+ */\n+\n+#include <linux/clk-provider.h>\n+#include <linux/clkdev.h>\n+#include <linux/kernel.h>\n+#include <linux/module.h>\n+#include <linux/of.h>\n+#include <linux/slab.h>\n+#include <linux/platform_device.h>\n+\n+/* Clock rate of CLK44EN attached to GPIO6 pin */\n+#define CLK_44EN_RATE 22579200UL\n+/* Clock rate of CLK48EN attached to GPIO3 pin */\n+#define CLK_48EN_RATE 24576000UL\n+\n+/**\n+ * struct hifiberry_dacpro_clk - Common struct to the HiFiBerry DAC Pro\n+ * @hw: clk_hw for the common clk framework\n+ * @mode: 0 => CLK44EN, 1 => CLK48EN\n+ */\n+struct clk_hifiberry_hw {\n+\tstruct clk_hw hw;\n+\tuint8_t mode;\n+};\n+\n+#define to_hifiberry_clk(_hw) container_of(_hw, struct clk_hifiberry_hw, hw)\n+\n+static const struct of_device_id clk_hifiberry_dacpro_dt_ids[] = {\n+\t{ .compatible = \"hifiberry,dacpro-clk\",},\n+\t{ }\n+};\n+MODULE_DEVICE_TABLE(of, clk_hifiberry_dacpro_dt_ids);\n+\n+static unsigned long clk_hifiberry_dacpro_recalc_rate(struct clk_hw *hw,\n+\tunsigned long parent_rate)\n+{\n+\treturn (to_hifiberry_clk(hw)->mode == 0) ? CLK_44EN_RATE :\n+\t\tCLK_48EN_RATE;\n+}\n+\n+static long clk_hifiberry_dacpro_round_rate(struct clk_hw *hw,\n+\tunsigned long rate, unsigned long *parent_rate)\n+{\n+\tlong actual_rate;\n+\n+\tif (rate <= CLK_44EN_RATE) {\n+\t\tactual_rate = (long)CLK_44EN_RATE;\n+\t} else if (rate >= CLK_48EN_RATE) {\n+\t\tactual_rate = (long)CLK_48EN_RATE;\n+\t} else {\n+\t\tlong diff44Rate = (long)(rate - CLK_44EN_RATE);\n+\t\tlong diff48Rate = (long)(CLK_48EN_RATE - rate);\n+\n+\t\tif (diff44Rate < diff48Rate)\n+\t\t\tactual_rate = (long)CLK_44EN_RATE;\n+\t\telse\n+\t\t\tactual_rate = (long)CLK_48EN_RATE;\n+\t}\n+\treturn actual_rate;\n+}\n+\n+\n+static int clk_hifiberry_dacpro_set_rate(struct clk_hw *hw,\n+\tunsigned long rate, unsigned long parent_rate)\n+{\n+\tunsigned long actual_rate;\n+\tstruct clk_hifiberry_hw *clk = to_hifiberry_clk(hw);\n+\n+\tactual_rate = (unsigned long)clk_hifiberry_dacpro_round_rate(hw, rate,\n+\t\t&parent_rate);\n+\tclk->mode = (actual_rate == CLK_44EN_RATE) ? 0 : 1;\n+\treturn 0;\n+}\n+\n+\n+const struct clk_ops clk_hifiberry_dacpro_rate_ops = {\n+\t.recalc_rate = clk_hifiberry_dacpro_recalc_rate,\n+\t.round_rate = clk_hifiberry_dacpro_round_rate,\n+\t.set_rate = clk_hifiberry_dacpro_set_rate,\n+};\n+\n+static int clk_hifiberry_dacpro_probe(struct platform_device *pdev)\n+{\n+\tint ret;\n+\tstruct clk_hifiberry_hw *proclk;\n+\tstruct clk *clk;\n+\tstruct device *dev;\n+\tstruct clk_init_data init;\n+\n+\tdev = &pdev->dev;\n+\n+\tproclk = kzalloc(sizeof(struct clk_hifiberry_hw), GFP_KERNEL);\n+\tif (!proclk)\n+\t\treturn -ENOMEM;\n+\n+\tinit.name = \"clk-hifiberry-dacpro\";\n+\tinit.ops = &clk_hifiberry_dacpro_rate_ops;\n+\tinit.flags = 0;\n+\tinit.parent_names = NULL;\n+\tinit.num_parents = 0;\n+\n+\tproclk->mode = 0;\n+\tproclk->hw.init = &init;\n+\n+\tclk = devm_clk_register(dev, &proclk->hw);\n+\tif (!IS_ERR(clk)) {\n+\t\tret = of_clk_add_provider(dev->of_node, of_clk_src_simple_get,\n+\t\t\tclk);\n+\t} else {\n+\t\tdev_err(dev, \"Fail to register clock driver\\n\");\n+\t\tkfree(proclk);\n+\t\tret = PTR_ERR(clk);\n+\t}\n+\treturn ret;\n+}\n+\n+static int clk_hifiberry_dacpro_remove(struct platform_device *pdev)\n+{\n+\tof_clk_del_provider(pdev->dev.of_node);\n+\treturn 0;\n+}\n+\n+static struct platform_driver clk_hifiberry_dacpro_driver = {\n+\t.probe = clk_hifiberry_dacpro_probe,\n+\t.remove = clk_hifiberry_dacpro_remove,\n+\t.driver = {\n+\t\t.name = \"clk-hifiberry-dacpro\",\n+\t\t.of_match_table = clk_hifiberry_dacpro_dt_ids,\n+\t},\n+};\n+\n+static int __init clk_hifiberry_dacpro_init(void)\n+{\n+\treturn platform_driver_register(&clk_hifiberry_dacpro_driver);\n+}\n+core_initcall(clk_hifiberry_dacpro_init);\n+\n+static void __exit clk_hifiberry_dacpro_exit(void)\n+{\n+\tplatform_driver_unregister(&clk_hifiberry_dacpro_driver);\n+}\n+module_exit(clk_hifiberry_dacpro_exit);\n+\n+MODULE_DESCRIPTION(\"HiFiBerry DAC Pro clock driver\");\n+MODULE_LICENSE(\"GPL v2\");\n+MODULE_ALIAS(\"platform:clk-hifiberry-dacpro\");\n--- a/sound/soc/bcm/Kconfig\n+++ b/sound/soc/bcm/Kconfig\n@@ -26,3 +26,277 @@ config SND_BCM63XX_I2S_WHISTLER\n \t  DSL/PON chips (bcm63158, bcm63178)\n \n \t  If you don't know what to do here, say N\n+\n+config SND_BCM2708_SOC_GOOGLEVOICEHAT_SOUNDCARD\n+\ttristate \"Support for Google voiceHAT soundcard\"\n+\tdepends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S\n+\tselect SND_SOC_VOICEHAT\n+\tselect SND_RPI_SIMPLE_SOUNDCARD\n+\thelp\n+          Say Y or M if you want to add support for voiceHAT soundcard.\n+\n+config SND_BCM2708_SOC_HIFIBERRY_DAC\n+        tristate \"Support for HifiBerry DAC\"\n+        depends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S\n+        select SND_SOC_PCM5102A\n+        select SND_RPI_SIMPLE_SOUNDCARD\n+        help\n+         Say Y or M if you want to add support for HifiBerry DAC.\n+\n+config SND_BCM2708_SOC_HIFIBERRY_DACPLUS\n+        tristate \"Support for HifiBerry DAC+\"\n+        depends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S\n+        select SND_SOC_PCM512x\n+        select SND_SOC_TPA6130A2\n+        select COMMON_CLK_HIFIBERRY_DACPRO\n+        help\n+         Say Y or M if you want to add support for HifiBerry DAC+.\n+\n+config SND_BCM2708_SOC_HIFIBERRY_DACPLUSHD\n+        tristate \"Support for HifiBerry DAC+ HD\"\n+        depends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S\n+        select SND_SOC_PCM179X_I2C\n+        select COMMON_CLK_HIFIBERRY_DACPLUSHD\n+        help\n+         Say Y or M if you want to add support for HifiBerry DAC+ HD.\n+\n+config SND_BCM2708_SOC_HIFIBERRY_DACPLUSADC\n+        tristate \"Support for HifiBerry DAC+ADC\"\n+        depends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S\n+        select SND_SOC_PCM512x_I2C\n+\tselect SND_SOC_DMIC\n+        select COMMON_CLK_HIFIBERRY_DACPRO\n+        help\n+         Say Y or M if you want to add support for HifiBerry DAC+ADC.\n+\n+config SND_BCM2708_SOC_HIFIBERRY_DACPLUSADCPRO\n+        tristate \"Support for HifiBerry DAC+ADC PRO\"\n+        depends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S\n+        select SND_SOC_PCM512x_I2C\n+\tselect SND_SOC_PCM186X_I2C\n+        select COMMON_CLK_HIFIBERRY_DACPRO\n+        help\n+         Say Y or M if you want to add support for HifiBerry DAC+ADC PRO.\n+\n+config SND_BCM2708_SOC_HIFIBERRY_DACPLUSDSP\n+        tristate \"Support for HifiBerry DAC+DSP\"\n+        depends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S\n+\tselect SND_RPI_SIMPLE_SOUNDCARD\n+        help\n+         Say Y or M if you want to add support for HifiBerry DSP-DAC.\n+\n+config SND_BCM2708_SOC_HIFIBERRY_DIGI\n+        tristate \"Support for HifiBerry Digi\"\n+        depends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S\n+        select SND_SOC_WM8804\n+        help\n+         Say Y or M if you want to add support for HifiBerry Digi S/PDIF output board.\n+\n+config SND_BCM2708_SOC_HIFIBERRY_AMP\n+        tristate \"Support for the HifiBerry Amp\"\n+        depends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S\n+        select SND_SOC_TAS5713\n+        select SND_RPI_SIMPLE_SOUNDCARD\n+        help\n+         Say Y or M if you want to add support for the HifiBerry Amp amplifier board.\n+\n+config SND_BCM2708_SOC_RPI_CIRRUS\n+        tristate \"Support for Cirrus Logic Audio Card\"\n+        depends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S\n+        select SND_SOC_WM5102\n+        select SND_SOC_WM8804\n+        help\n+         Say Y or M if you want to add support for the Wolfson and\n+         Cirrus Logic audio cards.\n+\n+config SND_BCM2708_SOC_RPI_DAC\n+        tristate \"Support for RPi-DAC\"\n+        depends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S\n+        select SND_SOC_PCM1794A\n+        select SND_RPI_SIMPLE_SOUNDCARD\n+        help\n+         Say Y or M if you want to add support for RPi-DAC.\n+\n+config SND_BCM2708_SOC_RPI_PROTO\n+\ttristate \"Support for Rpi-PROTO\"\n+\tdepends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S\n+\tselect SND_SOC_WM8731\n+\thelp\n+\t  Say Y or M if you want to add support for Audio Codec Board PROTO (WM8731).\n+\n+config SND_BCM2708_SOC_JUSTBOOM_BOTH\n+\ttristate \"Support for simultaneous JustBoom Digi and JustBoom DAC\"\n+\tdepends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S\n+\tselect SND_SOC_WM8804\n+\tselect SND_SOC_PCM512x\n+\thelp\n+\t\tSay Y or M if you want to add support for simultaneous\n+\t\tJustBoom Digi and JustBoom DAC.\n+\n+\t\tThis is not the right choice if you only have one but both of\n+\t\tthese cards.\n+\n+config SND_BCM2708_SOC_JUSTBOOM_DAC\n+\ttristate \"Support for JustBoom DAC\"\n+\tdepends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S\n+\tselect SND_SOC_PCM512x\n+\thelp\n+\t  Say Y or M if you want to add support for JustBoom DAC.\n+\n+config SND_BCM2708_SOC_JUSTBOOM_DIGI\n+\ttristate \"Support for JustBoom Digi\"\n+\tdepends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S\n+\tselect SND_SOC_WM8804\n+        select SND_RPI_WM8804_SOUNDCARD\n+\thelp\n+\t  Say Y or M if you want to add support for JustBoom Digi.\n+\n+config SND_BCM2708_SOC_IQAUDIO_CODEC\n+\ttristate \"Support for IQaudIO-CODEC\"\n+\tdepends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S\n+\tselect SND_SOC_DA7213\n+\thelp\n+\t  Say Y or M if you want to add support for IQaudIO-CODEC.\n+\n+config SND_BCM2708_SOC_IQAUDIO_DAC\n+\ttristate \"Support for IQaudIO-DAC\"\n+\tdepends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S\n+\tselect SND_SOC_PCM512x_I2C\n+\thelp\n+\t  Say Y or M if you want to add support for IQaudIO-DAC.\n+\n+config SND_BCM2708_SOC_IQAUDIO_DIGI\n+\ttristate \"Support for IQAudIO Digi\"\n+\tdepends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S\n+\tselect SND_SOC_WM8804\n+\tselect SND_RPI_WM8804_SOUNDCARD\n+\thelp\n+\t  Say Y or M if you want to add support for IQAudIO Digital IO board.\n+\n+config SND_BCM2708_SOC_I_SABRE_Q2M\n+        tristate \"Support for Audiophonics I-Sabre Q2M DAC\"\n+        depends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S\n+        select SND_SOC_I_SABRE_CODEC\n+        help\n+        Say Y or M if you want to add support for Audiophonics I-SABRE Q2M DAC\n+\n+config SND_BCM2708_SOC_ADAU1977_ADC\n+\ttristate \"Support for ADAU1977 ADC\"\n+\tdepends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S\n+\tselect SND_SOC_ADAU1977_I2C\n+\tselect SND_RPI_SIMPLE_SOUNDCARD\n+\thelp\n+\t  Say Y or M if you want to add support for ADAU1977 ADC.\n+\n+config SND_AUDIOINJECTOR_PI_SOUNDCARD\n+\ttristate \"Support for audioinjector.net Pi add on soundcard\"\n+\tdepends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S\n+\tselect SND_SOC_WM8731\n+\thelp\n+\t  Say Y or M if you want to add support for audioinjector.net Pi Hat\n+\n+config SND_AUDIOINJECTOR_OCTO_SOUNDCARD\n+\ttristate \"Support for audioinjector.net Octo channel (Hat) soundcard\"\n+\tdepends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S\n+\tselect SND_SOC_CS42XX8_I2C\n+\thelp\n+\t  Say Y or M if you want to add support for audioinjector.net octo add on\n+\n+config SND_AUDIOINJECTOR_ISOLATED_SOUNDCARD\n+\ttristate \"Support for audioinjector.net isolated DAC and ADC soundcard\"\n+\tdepends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S\n+\tselect SND_SOC_CS4271_I2C\n+\thelp\n+\t  Say Y or M if you want to add support for audioinjector.net isolated soundcard\n+\n+config SND_AUDIOSENSE_PI\n+\ttristate \"Support for AudioSense Add-On Soundcard\"\n+\tdepends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S\n+\tselect SND_SOC_TLV320AIC32X4_I2C\n+\thelp\n+\t  Say Y or M if you want to add support for tlv320aic32x4 add-on\n+\n+config SND_DIGIDAC1_SOUNDCARD\n+        tristate \"Support for Red Rocks Audio DigiDAC1\"\n+        depends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S\n+        select SND_SOC_WM8804\n+        select SND_SOC_WM8741\n+        help\n+         Say Y or M if you want to add support for Red Rocks Audio DigiDAC1 board.\n+\n+config SND_BCM2708_SOC_DIONAUDIO_LOCO\n+\ttristate \"Support for Dion Audio LOCO DAC-AMP\"\n+\tdepends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S\n+\tselect SND_SOC_PCM5102a\n+\thelp\n+\t  Say Y or M if you want to add support for Dion Audio LOCO.\n+\n+config SND_BCM2708_SOC_DIONAUDIO_LOCO_V2\n+\ttristate \"Support for Dion Audio LOCO-V2 DAC-AMP\"\n+\tdepends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S\n+\tselect SND_SOC_PCM5122\n+\thelp\n+\t  Say Y or M if you want to add support for Dion Audio LOCO-V2.\n+\n+config SND_BCM2708_SOC_ALLO_PIANO_DAC\n+\ttristate \"Support for Allo Piano DAC\"\n+\tdepends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S\n+\tselect SND_SOC_PCM512x_I2C\n+\thelp\n+\t  Say Y or M if you want to add support for Allo Piano DAC.\n+\n+config SND_BCM2708_SOC_ALLO_PIANO_DAC_PLUS\n+\ttristate \"Support for Allo Piano DAC Plus\"\n+\tdepends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S\n+\tselect SND_SOC_PCM512x_I2C\n+\thelp\n+\t  Say Y or M if you want to add support for Allo Piano DAC Plus.\n+\n+config SND_BCM2708_SOC_ALLO_BOSS_DAC\n+\ttristate \"Support for Allo Boss DAC\"\n+\tdepends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S\n+\tselect SND_SOC_PCM512x_I2C\n+\thelp\n+\t  Say Y or M if you want to add support for Allo Boss DAC.\n+\n+config SND_BCM2708_SOC_ALLO_DIGIONE\n+\ttristate \"Support for Allo DigiOne\"\n+\tdepends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S\n+\tselect SND_SOC_WM8804\n+\tselect SND_RPI_WM8804_SOUNDCARD\n+\thelp\n+\t  Say Y or M if you want to add support for Allo DigiOne.\n+\n+config SND_BCM2708_SOC_ALLO_KATANA_DAC\n+\ttristate \"Support for Allo Katana DAC\"\n+\tdepends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S\n+\tdepends on I2C\n+\tselect REGMAP_I2C\n+\tselect SND_AUDIO_GRAPH_CARD\n+\thelp\n+\t  Say Y or M if you want to add support for Allo Katana DAC.\n+\n+config SND_BCM2708_SOC_FE_PI_AUDIO\n+\ttristate \"Support for Fe-Pi-Audio\"\n+\tdepends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S\n+\tselect SND_SOC_SGTL5000\n+\thelp\n+\t  Say Y or M if you want to add support for Fe-Pi-Audio.\n+\n+config SND_PISOUND\n+\ttristate \"Support for Blokas Labs pisound\"\n+\tdepends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S\n+\tselect SND_RAWMIDI\n+\thelp\n+\t  Say Y or M if you want to add support for Blokas Labs pisound.\n+\n+config SND_RPI_SIMPLE_SOUNDCARD\n+\ttristate \"Support for Raspberry Pi simple soundcards\"\n+\thelp\n+\t  Say Y or M if you want to add support Raspbery Pi simple soundcards\n+\n+config SND_RPI_WM8804_SOUNDCARD\n+\ttristate \"Support for Raspberry Pi generic WM8804 soundcards\"\n+\thelp\n+\t  Say Y or M if you want to add support for the Raspberry Pi\n+          generic driver for WM8804 based soundcards.\n--- a/sound/soc/bcm/Makefile\n+++ b/sound/soc/bcm/Makefile\n@@ -12,4 +12,65 @@ obj-$(CONFIG_SND_SOC_CYGNUS) += snd-soc-\n # BCM63XX Platform Support\n snd-soc-63xx-objs := bcm63xx-i2s-whistler.o bcm63xx-pcm-whistler.o\n \n-obj-$(CONFIG_SND_BCM63XX_I2S_WHISTLER) += snd-soc-63xx.o\n\\ No newline at end of file\n+obj-$(CONFIG_SND_BCM63XX_I2S_WHISTLER) += snd-soc-63xx.o\n+\n+# Google voiceHAT custom codec support\n+snd-soc-googlevoicehat-codec-objs := googlevoicehat-codec.o\n+\n+# BCM2708 Machine Support\n+snd-soc-hifiberry-dacplus-objs := hifiberry_dacplus.o\n+snd-soc-hifiberry-dacplushd-objs := hifiberry_dacplushd.o\n+snd-soc-hifiberry-dacplusadc-objs := hifiberry_dacplusadc.o\n+snd-soc-hifiberry-dacplusadcpro-objs := hifiberry_dacplusadcpro.o\n+snd-soc-hifiberry-dacplusdsp-objs := hifiberry_dacplusdsp.o\n+snd-soc-justboom-both-objs := justboom-both.o\n+snd-soc-justboom-dac-objs := justboom-dac.o\n+snd-soc-rpi-cirrus-objs := rpi-cirrus.o\n+snd-soc-rpi-proto-objs := rpi-proto.o\n+snd-soc-iqaudio-codec-objs := iqaudio-codec.o\n+snd-soc-iqaudio-dac-objs := iqaudio-dac.o\n+ snd-soc-i-sabre-q2m-objs := i-sabre-q2m.o\n+snd-soc-audioinjector-pi-soundcard-objs := audioinjector-pi-soundcard.o\n+snd-soc-audioinjector-octo-soundcard-objs := audioinjector-octo-soundcard.o\n+snd-soc-audioinjector-isolated-soundcard-objs := audioinjector-isolated-soundcard.o\n+snd-soc-audiosense-pi-objs := audiosense-pi.o\n+snd-soc-digidac1-soundcard-objs := digidac1-soundcard.o\n+snd-soc-dionaudio-loco-objs := dionaudio_loco.o\n+snd-soc-dionaudio-loco-v2-objs := dionaudio_loco-v2.o\n+snd-soc-allo-boss-dac-objs := allo-boss-dac.o\n+snd-soc-allo-piano-dac-objs := allo-piano-dac.o\n+snd-soc-allo-piano-dac-plus-objs := allo-piano-dac-plus.o\n+snd-soc-allo-katana-codec-objs := allo-katana-codec.o\n+snd-soc-pisound-objs := pisound.o\n+snd-soc-fe-pi-audio-objs := fe-pi-audio.o\n+snd-soc-rpi-simple-soundcard-objs := rpi-simple-soundcard.o\n+snd-soc-rpi-wm8804-soundcard-objs := rpi-wm8804-soundcard.o\n+\n+obj-$(CONFIG_SND_BCM2708_SOC_GOOGLEVOICEHAT_SOUNDCARD)  += snd-soc-googlevoicehat-codec.o\n+obj-$(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS) += snd-soc-hifiberry-dacplus.o\n+obj-$(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUSHD) += snd-soc-hifiberry-dacplushd.o\n+obj-$(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUSADC) += snd-soc-hifiberry-dacplusadc.o\n+obj-$(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUSADCPRO) += snd-soc-hifiberry-dacplusadcpro.o\n+obj-$(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUSDSP) += snd-soc-hifiberry-dacplusdsp.o\n+obj-$(CONFIG_SND_BCM2708_SOC_JUSTBOOM_BOTH) += snd-soc-justboom-both.o\n+obj-$(CONFIG_SND_BCM2708_SOC_JUSTBOOM_DAC) += snd-soc-justboom-dac.o\n+obj-$(CONFIG_SND_BCM2708_SOC_RPI_CIRRUS) += snd-soc-rpi-cirrus.o\n+obj-$(CONFIG_SND_BCM2708_SOC_RPI_PROTO) += snd-soc-rpi-proto.o\n+obj-$(CONFIG_SND_BCM2708_SOC_IQAUDIO_CODEC) += snd-soc-iqaudio-codec.o\n+obj-$(CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC) += snd-soc-iqaudio-dac.o\n+obj-$(CONFIG_SND_BCM2708_SOC_I_SABRE_Q2M) += snd-soc-i-sabre-q2m.o\n+obj-$(CONFIG_SND_AUDIOINJECTOR_PI_SOUNDCARD) += snd-soc-audioinjector-pi-soundcard.o\n+obj-$(CONFIG_SND_AUDIOINJECTOR_OCTO_SOUNDCARD) += snd-soc-audioinjector-octo-soundcard.o\n+obj-$(CONFIG_SND_AUDIOINJECTOR_ISOLATED_SOUNDCARD) += snd-soc-audioinjector-isolated-soundcard.o\n+obj-$(CONFIG_SND_AUDIOSENSE_PI) += snd-soc-audiosense-pi.o\n+obj-$(CONFIG_SND_DIGIDAC1_SOUNDCARD) += snd-soc-digidac1-soundcard.o\n+obj-$(CONFIG_SND_BCM2708_SOC_DIONAUDIO_LOCO) += snd-soc-dionaudio-loco.o\n+obj-$(CONFIG_SND_BCM2708_SOC_DIONAUDIO_LOCO_V2) += snd-soc-dionaudio-loco-v2.o\n+obj-$(CONFIG_SND_BCM2708_SOC_ALLO_BOSS_DAC) += snd-soc-allo-boss-dac.o\n+obj-$(CONFIG_SND_BCM2708_SOC_ALLO_PIANO_DAC) += snd-soc-allo-piano-dac.o\n+obj-$(CONFIG_SND_BCM2708_SOC_ALLO_PIANO_DAC_PLUS) += snd-soc-allo-piano-dac-plus.o\n+obj-$(CONFIG_SND_BCM2708_SOC_ALLO_KATANA_DAC) += snd-soc-allo-katana-codec.o\n+obj-$(CONFIG_SND_PISOUND) += snd-soc-pisound.o\n+obj-$(CONFIG_SND_BCM2708_SOC_FE_PI_AUDIO) += snd-soc-fe-pi-audio.o\n+obj-$(CONFIG_SND_RPI_SIMPLE_SOUNDCARD) += snd-soc-rpi-simple-soundcard.o\n+obj-$(CONFIG_SND_RPI_WM8804_SOUNDCARD) += snd-soc-rpi-wm8804-soundcard.o\n--- /dev/null\n+++ b/sound/soc/bcm/allo-boss-dac.c\n@@ -0,0 +1,456 @@\n+/*\n+ * ALSA ASoC Machine Driver for Allo Boss DAC\n+ *\n+ * Author:\tBaswaraj K <jaikumar@cem-solutions.net>\n+ *\t\tCopyright 2017\n+ *\t\tbased on code by Daniel Matuschek,\n+ *\t\t\t\t Stuart MacLean <stuart@hifiberry.com>\n+ *\t\tbased on code by Florian Meier <florian.meier@koalo.de>\n+ *\n+ * This program is free software; you can redistribute it and/or\n+ * modify it under the terms of the GNU General Public License\n+ * version 2 as published by the Free Software Foundation.\n+ *\n+ * This program is distributed in the hope that it will be useful, but\n+ * WITHOUT ANY WARRANTY; without even the implied warranty of\n+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\n+ * General Public License for more details.\n+ */\n+\n+#include <linux/module.h>\n+#include <linux/gpio/consumer.h>\n+#include <linux/platform_device.h>\n+#include <linux/clk.h>\n+#include <linux/delay.h>\n+\n+#include <sound/core.h>\n+#include <sound/pcm.h>\n+#include <sound/pcm_params.h>\n+#include <sound/soc.h>\n+#include \"../codecs/pcm512x.h\"\n+\n+#define ALLO_BOSS_NOCLOCK 0\n+#define ALLO_BOSS_CLK44EN 1\n+#define ALLO_BOSS_CLK48EN 2\n+\n+struct pcm512x_priv {\n+\tstruct regmap *regmap;\n+\tstruct clk *sclk;\n+};\n+\n+static struct gpio_desc *mute_gpio;\n+\n+/* Clock rate of CLK44EN attached to GPIO6 pin */\n+#define CLK_44EN_RATE 45158400UL\n+/* Clock rate of CLK48EN attached to GPIO3 pin */\n+#define CLK_48EN_RATE 49152000UL\n+\n+static bool slave;\n+static bool snd_soc_allo_boss_master;\n+static bool digital_gain_0db_limit = true;\n+\n+static void snd_allo_boss_select_clk(struct snd_soc_component *component,\n+\tint clk_id)\n+{\n+\tswitch (clk_id) {\n+\tcase ALLO_BOSS_NOCLOCK:\n+\t\tsnd_soc_component_update_bits(component, PCM512x_GPIO_CONTROL_1, 0x24, 0x00);\n+\t\tbreak;\n+\tcase ALLO_BOSS_CLK44EN:\n+\t\tsnd_soc_component_update_bits(component, PCM512x_GPIO_CONTROL_1, 0x24, 0x20);\n+\t\tbreak;\n+\tcase ALLO_BOSS_CLK48EN:\n+\t\tsnd_soc_component_update_bits(component, PCM512x_GPIO_CONTROL_1, 0x24, 0x04);\n+\t\tbreak;\n+\t}\n+}\n+\n+static void snd_allo_boss_clk_gpio(struct snd_soc_component *component)\n+{\n+\tsnd_soc_component_update_bits(component, PCM512x_GPIO_EN, 0x24, 0x24);\n+\tsnd_soc_component_update_bits(component, PCM512x_GPIO_OUTPUT_3, 0x0f, 0x02);\n+\tsnd_soc_component_update_bits(component, PCM512x_GPIO_OUTPUT_6, 0x0f, 0x02);\n+}\n+\n+static bool snd_allo_boss_is_sclk(struct snd_soc_component *component)\n+{\n+\tunsigned int sck;\n+\n+\tsck = snd_soc_component_read(component, PCM512x_RATE_DET_4);\n+\treturn (!(sck & 0x40));\n+}\n+\n+static bool snd_allo_boss_is_sclk_sleep(\n+\tstruct snd_soc_component *component)\n+{\n+\tmsleep(2);\n+\treturn snd_allo_boss_is_sclk(component);\n+}\n+\n+static bool snd_allo_boss_is_master_card(struct snd_soc_component *component)\n+{\n+\tbool isClk44EN, isClk48En, isNoClk;\n+\n+\tsnd_allo_boss_clk_gpio(component);\n+\n+\tsnd_allo_boss_select_clk(component, ALLO_BOSS_CLK44EN);\n+\tisClk44EN = snd_allo_boss_is_sclk_sleep(component);\n+\n+\tsnd_allo_boss_select_clk(component, ALLO_BOSS_NOCLOCK);\n+\tisNoClk = snd_allo_boss_is_sclk_sleep(component);\n+\n+\tsnd_allo_boss_select_clk(component, ALLO_BOSS_CLK48EN);\n+\tisClk48En = snd_allo_boss_is_sclk_sleep(component);\n+\n+\treturn (isClk44EN && isClk48En && !isNoClk);\n+}\n+\n+static int snd_allo_boss_clk_for_rate(int sample_rate)\n+{\n+\tint type;\n+\n+\tswitch (sample_rate) {\n+\tcase 11025:\n+\tcase 22050:\n+\tcase 44100:\n+\tcase 88200:\n+\tcase 176400:\n+\tcase 352800:\n+\t\ttype = ALLO_BOSS_CLK44EN;\n+\t\tbreak;\n+\tdefault:\n+\t\ttype = ALLO_BOSS_CLK48EN;\n+\t\tbreak;\n+\t}\n+\treturn type;\n+}\n+\n+static void snd_allo_boss_set_sclk(struct snd_soc_component *component,\n+\tint sample_rate)\n+{\n+\tstruct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);\n+\n+\tif (!IS_ERR(pcm512x->sclk)) {\n+\t\tint ctype;\n+\n+\t\tctype =\tsnd_allo_boss_clk_for_rate(sample_rate);\n+\t\tclk_set_rate(pcm512x->sclk, (ctype == ALLO_BOSS_CLK44EN)\n+\t\t\t\t? CLK_44EN_RATE : CLK_48EN_RATE);\n+\t\tsnd_allo_boss_select_clk(component, ctype);\n+\t}\n+}\n+\n+static int snd_allo_boss_init(struct snd_soc_pcm_runtime *rtd)\n+{\n+\tstruct snd_soc_component *component = asoc_rtd_to_codec(rtd, 0)->component;\n+\tstruct pcm512x_priv *priv = snd_soc_component_get_drvdata(component);\n+\n+\tif (slave)\n+\t\tsnd_soc_allo_boss_master = false;\n+\telse\n+\t\tsnd_soc_allo_boss_master =\n+\t\t\tsnd_allo_boss_is_master_card(component);\n+\n+\tif (snd_soc_allo_boss_master) {\n+\t\tstruct snd_soc_dai_link *dai = rtd->dai_link;\n+\n+\t\tdai->name = \"BossDAC\";\n+\t\tdai->stream_name = \"Boss DAC HiFi [Master]\";\n+\t\tdai->dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF\n+\t\t\t| SND_SOC_DAIFMT_CBM_CFM;\n+\n+\t\tsnd_soc_component_update_bits(component, PCM512x_BCLK_LRCLK_CFG, 0x31, 0x11);\n+\t\tsnd_soc_component_update_bits(component, PCM512x_MASTER_MODE, 0x03, 0x03);\n+\t\tsnd_soc_component_update_bits(component, PCM512x_MASTER_CLKDIV_2, 0x7f, 63);\n+\t\t/*\n+\t\t* Default sclk to CLK_48EN_RATE, otherwise codec\n+\t\t*  pcm512x_dai_startup_master method could call\n+\t\t*  snd_pcm_hw_constraint_ratnums using CLK_44EN/64\n+\t\t*  which will mask 384k sample rate.\n+\t\t*/\n+\t\tif (!IS_ERR(priv->sclk))\n+\t\t\tclk_set_rate(priv->sclk, CLK_48EN_RATE);\n+\t} else {\n+\t\tpriv->sclk = ERR_PTR(-ENOENT);\n+\t}\n+\n+\tsnd_soc_component_update_bits(component, PCM512x_GPIO_EN, 0x08, 0x08);\n+\tsnd_soc_component_update_bits(component, PCM512x_GPIO_OUTPUT_4, 0x0f, 0x02);\n+\tsnd_soc_component_update_bits(component, PCM512x_GPIO_CONTROL_1, 0x08, 0x08);\n+\n+\tif (digital_gain_0db_limit) {\n+\t\tint ret;\n+\t\tstruct snd_soc_card *card = rtd->card;\n+\n+\t\tret = snd_soc_limit_volume(card, \"Digital Playback Volume\",\n+\t\t\t\t207);\n+\t\tif (ret < 0)\n+\t\t\tdev_warn(card->dev, \"Failed to set volume limit: %d\\n\",\n+\t\t\t\t\tret);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int snd_allo_boss_update_rate_den(\n+\tstruct snd_pcm_substream *substream, struct snd_pcm_hw_params *params)\n+{\n+\tstruct snd_soc_pcm_runtime *rtd = substream->private_data;\n+\tstruct snd_soc_component *component = asoc_rtd_to_codec(rtd, 0)->component;\n+\tstruct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);\n+\tstruct snd_ratnum *rats_no_pll;\n+\tunsigned int num = 0, den = 0;\n+\tint err;\n+\n+\trats_no_pll = devm_kzalloc(rtd->dev, sizeof(*rats_no_pll), GFP_KERNEL);\n+\tif (!rats_no_pll)\n+\t\treturn -ENOMEM;\n+\n+\trats_no_pll->num = clk_get_rate(pcm512x->sclk) / 64;\n+\trats_no_pll->den_min = 1;\n+\trats_no_pll->den_max = 128;\n+\trats_no_pll->den_step = 1;\n+\n+\terr = snd_interval_ratnum(hw_param_interval(params,\n+\t\tSNDRV_PCM_HW_PARAM_RATE), 1, rats_no_pll, &num, &den);\n+\tif (err >= 0 && den) {\n+\t\tparams->rate_num = num;\n+\t\tparams->rate_den = den;\n+\t}\n+\n+\tdevm_kfree(rtd->dev, rats_no_pll);\n+\treturn 0;\n+}\n+\n+static void snd_allo_boss_gpio_mute(struct snd_soc_card *card)\n+{\n+\tif (mute_gpio)\n+\t\tgpiod_set_value_cansleep(mute_gpio, 1);\n+}\n+\n+static void snd_allo_boss_gpio_unmute(struct snd_soc_card *card)\n+{\n+\tif (mute_gpio)\n+\t\tgpiod_set_value_cansleep(mute_gpio, 0);\n+}\n+\n+static int snd_allo_boss_set_bias_level(struct snd_soc_card *card,\n+\tstruct snd_soc_dapm_context *dapm, enum snd_soc_bias_level level)\n+{\n+\tstruct snd_soc_pcm_runtime *rtd;\n+\tstruct snd_soc_dai *codec_dai;\n+\n+\trtd = snd_soc_get_pcm_runtime(card, &card->dai_link[0]);\n+\tcodec_dai = asoc_rtd_to_codec(rtd, 0);\n+\n+\tif (dapm->dev != codec_dai->dev)\n+\t\treturn 0;\n+\n+\tswitch (level) {\n+\tcase SND_SOC_BIAS_PREPARE:\n+\t\tif (dapm->bias_level != SND_SOC_BIAS_STANDBY)\n+\t\t\tbreak;\n+\t\t/* UNMUTE DAC */\n+\t\tsnd_allo_boss_gpio_unmute(card);\n+\t\tbreak;\n+\n+\tcase SND_SOC_BIAS_STANDBY:\n+\t\tif (dapm->bias_level != SND_SOC_BIAS_PREPARE)\n+\t\t\tbreak;\n+\t\t/* MUTE DAC */\n+\t\tsnd_allo_boss_gpio_mute(card);\n+\t\tbreak;\n+\n+\tdefault:\n+\t\tbreak;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int snd_allo_boss_hw_params(\n+\tstruct snd_pcm_substream *substream, struct snd_pcm_hw_params *params)\n+{\n+\tint ret = 0;\n+\tstruct snd_soc_pcm_runtime *rtd = substream->private_data;\n+\tint channels = params_channels(params);\n+\tint width = snd_pcm_format_physical_width(params_format(params));\n+\n+\tif (snd_soc_allo_boss_master) {\n+\t\tstruct snd_soc_component *component = asoc_rtd_to_codec(rtd, 0)->component;\n+\n+\t\tsnd_allo_boss_set_sclk(component,\n+\t\t\tparams_rate(params));\n+\n+\t\tret = snd_allo_boss_update_rate_den(\n+\t\t\tsubstream, params);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\t}\n+\n+\tret = snd_soc_dai_set_bclk_ratio(asoc_rtd_to_cpu(rtd, 0), channels * width);\n+\tif (ret)\n+\t\treturn ret;\n+\tret = snd_soc_dai_set_bclk_ratio(asoc_rtd_to_codec(rtd, 0), channels * width);\n+\treturn ret;\n+}\n+\n+static int snd_allo_boss_startup(\n+\tstruct snd_pcm_substream *substream)\n+{\n+\tstruct snd_soc_pcm_runtime *rtd = substream->private_data;\n+\tstruct snd_soc_component *component = asoc_rtd_to_codec(rtd, 0)->component;\n+\tstruct snd_soc_card *card = rtd->card;\n+\n+\tsnd_soc_component_update_bits(component, PCM512x_GPIO_CONTROL_1, 0x08, 0x08);\n+\tsnd_allo_boss_gpio_mute(card);\n+\n+\tif (snd_soc_allo_boss_master) {\n+\t\tstruct pcm512x_priv *priv = snd_soc_component_get_drvdata(component);\n+\t\t/*\n+\t\t * Default sclk to CLK_48EN_RATE, otherwise codec\n+\t\t * pcm512x_dai_startup_master method could call\n+\t\t * snd_pcm_hw_constraint_ratnums using CLK_44EN/64\n+\t\t * which will mask 384k sample rate.\n+\t\t */\n+\t\tif (!IS_ERR(priv->sclk))\n+\t\t\tclk_set_rate(priv->sclk, CLK_48EN_RATE);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static void snd_allo_boss_shutdown(\n+\tstruct snd_pcm_substream *substream)\n+{\n+\tstruct snd_soc_pcm_runtime *rtd = substream->private_data;\n+\tstruct snd_soc_component *component = asoc_rtd_to_codec(rtd, 0)->component;\n+\n+\tsnd_soc_component_update_bits(component, PCM512x_GPIO_CONTROL_1, 0x08, 0x00);\n+}\n+\n+static int snd_allo_boss_prepare(\n+\tstruct snd_pcm_substream *substream)\n+{\n+\tstruct snd_soc_pcm_runtime *rtd = substream->private_data;\n+\tstruct snd_soc_card *card = rtd->card;\n+\n+\tsnd_allo_boss_gpio_unmute(card);\n+\treturn 0;\n+}\n+/* machine stream operations */\n+static struct snd_soc_ops snd_allo_boss_ops = {\n+\t.hw_params = snd_allo_boss_hw_params,\n+\t.startup = snd_allo_boss_startup,\n+\t.shutdown = snd_allo_boss_shutdown,\n+\t.prepare = snd_allo_boss_prepare,\n+};\n+\n+SND_SOC_DAILINK_DEFS(allo_boss,\n+\tDAILINK_COMP_ARRAY(COMP_CPU(\"bcm2708-i2s.0\")),\n+\tDAILINK_COMP_ARRAY(COMP_CODEC(\"pcm512x.1-004d\", \"pcm512x-hifi\")),\n+\tDAILINK_COMP_ARRAY(COMP_PLATFORM(\"bcm2708-i2s.0\")));\n+\n+static struct snd_soc_dai_link snd_allo_boss_dai[] = {\n+{\n+\t.name\t\t= \"Boss DAC\",\n+\t.stream_name\t= \"Boss DAC HiFi\",\n+\t.dai_fmt\t= SND_SOC_DAIFMT_I2S |\n+\t\t\t  SND_SOC_DAIFMT_NB_NF |\n+\t\t\t  SND_SOC_DAIFMT_CBS_CFS,\n+\t.ops\t\t= &snd_allo_boss_ops,\n+\t.init\t\t= snd_allo_boss_init,\n+\tSND_SOC_DAILINK_REG(allo_boss),\n+},\n+};\n+\n+/* audio machine driver */\n+static struct snd_soc_card snd_allo_boss = {\n+\t.name         = \"BossDAC\",\n+\t.owner        = THIS_MODULE,\n+\t.dai_link     = snd_allo_boss_dai,\n+\t.num_links    = ARRAY_SIZE(snd_allo_boss_dai),\n+};\n+\n+static int snd_allo_boss_probe(struct platform_device *pdev)\n+{\n+\tint ret = 0;\n+\n+\tsnd_allo_boss.dev = &pdev->dev;\n+\n+\tif (pdev->dev.of_node) {\n+\t\tstruct device_node *i2s_node;\n+\t\tstruct snd_soc_dai_link *dai;\n+\n+\t\tdai = &snd_allo_boss_dai[0];\n+\t\ti2s_node = of_parse_phandle(pdev->dev.of_node,\n+\t\t\t\t\t    \"i2s-controller\", 0);\n+\n+\t\tif (i2s_node) {\n+\t\t\tdai->cpus->dai_name = NULL;\n+\t\t\tdai->cpus->of_node = i2s_node;\n+\t\t\tdai->platforms->name = NULL;\n+\t\t\tdai->platforms->of_node = i2s_node;\n+\t\t}\n+\n+\t\tdigital_gain_0db_limit = !of_property_read_bool(\n+\t\t\tpdev->dev.of_node, \"allo,24db_digital_gain\");\n+\t\tslave = of_property_read_bool(pdev->dev.of_node,\n+\t\t\t\t\t\t\"allo,slave\");\n+\n+\t\tmute_gpio = devm_gpiod_get_optional(&pdev->dev, \"mute\",\n+\t\t\t\t\t\t\tGPIOD_OUT_LOW);\n+\t\tif (IS_ERR(mute_gpio)) {\n+\t\t\tret = PTR_ERR(mute_gpio);\n+\t\t\tdev_err(&pdev->dev,\n+\t\t\t\t\"failed to get mute gpio: %d\\n\", ret);\n+\t\t\treturn ret;\n+\t\t}\n+\n+\t\tif (mute_gpio)\n+\t\t\tsnd_allo_boss.set_bias_level =\n+\t\t\t\tsnd_allo_boss_set_bias_level;\n+\n+\t\tret = snd_soc_register_card(&snd_allo_boss);\n+\t\tif (ret) {\n+\t\t\tdev_err(&pdev->dev,\n+\t\t\t\t\"snd_soc_register_card() failed: %d\\n\", ret);\n+\t\t\treturn ret;\n+\t\t}\n+\n+\t\tif (mute_gpio)\n+\t\t\tsnd_allo_boss_gpio_mute(&snd_allo_boss);\n+\n+\t\treturn 0;\n+\t}\n+\n+\treturn -EINVAL;\n+}\n+\n+static int snd_allo_boss_remove(struct platform_device *pdev)\n+{\n+\tsnd_allo_boss_gpio_mute(&snd_allo_boss);\n+\treturn snd_soc_unregister_card(&snd_allo_boss);\n+}\n+\n+static const struct of_device_id snd_allo_boss_of_match[] = {\n+\t{ .compatible = \"allo,boss-dac\", },\n+\t{ /* sentinel */ },\n+};\n+MODULE_DEVICE_TABLE(of, snd_allo_boss_of_match);\n+\n+static struct platform_driver snd_allo_boss_driver = {\n+\t.driver = {\n+\t\t.name   = \"snd-allo-boss-dac\",\n+\t\t.owner  = THIS_MODULE,\n+\t\t.of_match_table = snd_allo_boss_of_match,\n+\t},\n+\t.probe          = snd_allo_boss_probe,\n+\t.remove         = snd_allo_boss_remove,\n+};\n+\n+module_platform_driver(snd_allo_boss_driver);\n+\n+MODULE_AUTHOR(\"Baswaraj K <jaikumar@cem-solutions.net>\");\n+MODULE_DESCRIPTION(\"ALSA ASoC Machine Driver for Allo Boss DAC\");\n+MODULE_LICENSE(\"GPL v2\");\n--- /dev/null\n+++ b/sound/soc/bcm/allo-katana-codec.c\n@@ -0,0 +1,388 @@\n+/*\n+ * Driver for the ALLO KATANA CODEC\n+ *\n+ * Author: Jaikumar <jaikumar@cem-solutions.net>\n+ *\t\tCopyright 2018\n+ *\n+ * This program is free software; you can redistribute it and/or\n+ * modify it under the terms of the GNU General Public License\n+ * version 2 as published by the Free Software Foundation.\n+ *\n+ * This program is distributed in the hope that it will be useful, but\n+ * WITHOUT ANY WARRANTY; without even the implied warranty of\n+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\n+ * General Public License for more details.\n+ */\n+\n+\n+#include <linux/init.h>\n+#include <linux/module.h>\n+#include <linux/clk.h>\n+#include <linux/kernel.h>\n+#include <linux/regmap.h>\n+#include <linux/regulator/consumer.h>\n+#include <linux/gcd.h>\n+#include <sound/soc.h>\n+#include <sound/soc-dapm.h>\n+#include <sound/pcm_params.h>\n+#include <sound/tlv.h>\n+#include <linux/i2c.h>\n+\n+\n+#define KATANA_CODEC_CHIP_ID\t\t0x30\n+#define KATANA_CODEC_VIRT_BASE\t\t0x100\n+#define KATANA_CODEC_PAGE\t\t0\n+\n+#define KATANA_CODEC_CHIP_ID_REG\t(KATANA_CODEC_VIRT_BASE + 0)\n+#define KATANA_CODEC_RESET\t\t(KATANA_CODEC_VIRT_BASE + 1)\n+#define KATANA_CODEC_VOLUME_1\t\t(KATANA_CODEC_VIRT_BASE + 2)\n+#define KATANA_CODEC_VOLUME_2\t\t(KATANA_CODEC_VIRT_BASE + 3)\n+#define KATANA_CODEC_MUTE\t\t(KATANA_CODEC_VIRT_BASE + 4)\n+#define KATANA_CODEC_DSP_PROGRAM\t(KATANA_CODEC_VIRT_BASE + 5)\n+#define KATANA_CODEC_DEEMPHASIS\t\t(KATANA_CODEC_VIRT_BASE + 6)\n+#define KATANA_CODEC_DOP\t\t(KATANA_CODEC_VIRT_BASE + 7)\n+#define KATANA_CODEC_FORMAT\t\t(KATANA_CODEC_VIRT_BASE + 8)\n+#define KATANA_CODEC_COMMAND\t\t(KATANA_CODEC_VIRT_BASE + 9)\n+#define KATANA_CODEC_MUTE_STREAM\t(KATANA_CODEC_VIRT_BASE + 10)\n+\n+#define KATANA_CODEC_MAX_REGISTER\t(KATANA_CODEC_VIRT_BASE + 10)\n+\n+#define KATANA_CODEC_FMT\t\t0xff\n+#define KATANA_CODEC_CHAN_MONO\t\t0x00\n+#define KATANA_CODEC_CHAN_STEREO\t0x80\n+#define KATANA_CODEC_ALEN_16\t\t0x10\n+#define KATANA_CODEC_ALEN_24\t\t0x20\n+#define KATANA_CODEC_ALEN_32\t\t0x30\n+#define KATANA_CODEC_RATE_11025\t\t0x01\n+#define KATANA_CODEC_RATE_22050\t\t0x02\n+#define KATANA_CODEC_RATE_32000\t\t0x03\n+#define KATANA_CODEC_RATE_44100\t\t0x04\n+#define KATANA_CODEC_RATE_48000\t\t0x05\n+#define KATANA_CODEC_RATE_88200\t\t0x06\n+#define KATANA_CODEC_RATE_96000\t\t0x07\n+#define KATANA_CODEC_RATE_176400\t0x08\n+#define KATANA_CODEC_RATE_192000\t0x09\n+#define KATANA_CODEC_RATE_352800\t0x0a\n+#define KATANA_CODEC_RATE_384000\t0x0b\n+\n+\n+struct katana_codec_priv {\n+\tstruct regmap *regmap;\n+\tint fmt;\n+};\n+\n+static const struct reg_default katana_codec_reg_defaults[] = {\n+\t{ KATANA_CODEC_RESET,\t\t0x00 },\n+\t{ KATANA_CODEC_VOLUME_1,\t0xF0 },\n+\t{ KATANA_CODEC_VOLUME_2,\t0xF0 },\n+\t{ KATANA_CODEC_MUTE,\t\t0x00 },\n+\t{ KATANA_CODEC_DSP_PROGRAM,\t0x04 },\n+\t{ KATANA_CODEC_DEEMPHASIS,\t0x00 },\n+\t{ KATANA_CODEC_DOP,\t\t0x00 },\n+\t{ KATANA_CODEC_FORMAT,\t\t0xb4 },\n+};\n+\n+static const char * const katana_codec_dsp_program_texts[] = {\n+\t\"Linear Phase Fast Roll-off Filter\",\n+\t\"Linear Phase Slow Roll-off Filter\",\n+\t\"Minimum Phase Fast Roll-off Filter\",\n+\t\"Minimum Phase Slow Roll-off Filter\",\n+\t\"Apodizing Fast Roll-off Filter\",\n+\t\"Corrected Minimum Phase Fast Roll-off Filter\",\n+\t\"Brick Wall Filter\",\n+};\n+\n+static const unsigned int katana_codec_dsp_program_values[] = {\n+\t0,\n+\t1,\n+\t2,\n+\t3,\n+\t4,\n+\t6,\n+\t7,\n+};\n+\n+static SOC_VALUE_ENUM_SINGLE_DECL(katana_codec_dsp_program,\n+\t\t\t\t  KATANA_CODEC_DSP_PROGRAM, 0, 0x07,\n+\t\t\t\t  katana_codec_dsp_program_texts,\n+\t\t\t\t  katana_codec_dsp_program_values);\n+\n+static const char * const katana_codec_deemphasis_texts[] = {\n+\t\"Bypass\",\n+\t\"32kHz\",\n+\t\"44.1kHz\",\n+\t\"48kHz\",\n+};\n+\n+static const unsigned int katana_codec_deemphasis_values[] = {\n+\t0,\n+\t1,\n+\t2,\n+\t3,\n+};\n+\n+static SOC_VALUE_ENUM_SINGLE_DECL(katana_codec_deemphasis,\n+\t\t\t\t  KATANA_CODEC_DEEMPHASIS, 0, 0x03,\n+\t\t\t\t  katana_codec_deemphasis_texts,\n+\t\t\t\t  katana_codec_deemphasis_values);\n+\n+static const SNDRV_CTL_TLVD_DECLARE_DB_MINMAX(master_tlv, -12750, 0);\n+\n+static const struct snd_kcontrol_new katana_codec_controls[] = {\n+\tSOC_DOUBLE_R_TLV(\"Master Playback Volume\", KATANA_CODEC_VOLUME_1,\n+\t\t\tKATANA_CODEC_VOLUME_2, 0, 255, 1, master_tlv),\n+\tSOC_DOUBLE(\"Master Playback Switch\", KATANA_CODEC_MUTE, 0, 0, 1, 1),\n+\tSOC_ENUM(\"DSP Program Route\", katana_codec_dsp_program),\n+\tSOC_ENUM(\"Deemphasis Route\", katana_codec_deemphasis),\n+\tSOC_SINGLE(\"DoP Playback Switch\", KATANA_CODEC_DOP, 0, 1, 1)\n+};\n+\n+static bool katana_codec_readable_register(struct device *dev,\n+\t\t\t\tunsigned int reg)\n+{\n+\tswitch (reg) {\n+\tcase KATANA_CODEC_CHIP_ID_REG:\n+\t\treturn true;\n+\tdefault:\n+\t\treturn reg < 0xff;\n+\t}\n+}\n+\n+static int katana_codec_hw_params(struct snd_pcm_substream *substream,\n+\t\t\t     struct snd_pcm_hw_params *params,\n+\t\t\t     struct snd_soc_dai *dai)\n+{\n+\tstruct snd_soc_component *component = dai->component;\n+\tstruct katana_codec_priv *katana_codec =\n+\t\tsnd_soc_component_get_drvdata(component);\n+\tint fmt = 0;\n+\tint ret;\n+\n+\tdev_dbg(component->card->dev, \"hw_params %u Hz, %u channels, %u bits\\n\",\n+\t\t\tparams_rate(params),\n+\t\t\tparams_channels(params),\n+\t\t\tparams_width(params));\n+\n+\tswitch (katana_codec->fmt & SND_SOC_DAIFMT_MASTER_MASK) {\n+\tcase SND_SOC_DAIFMT_CBM_CFM: // master\n+\t\tif (params_channels(params) == 2)\n+\t\t\tfmt = KATANA_CODEC_CHAN_STEREO;\n+\t\telse\n+\t\t\tfmt = KATANA_CODEC_CHAN_MONO;\n+\n+\t\tswitch (params_width(params)) {\n+\t\tcase 16:\n+\t\t\tfmt |= KATANA_CODEC_ALEN_16;\n+\t\t\tbreak;\n+\t\tcase 24:\n+\t\t\tfmt |= KATANA_CODEC_ALEN_24;\n+\t\t\tbreak;\n+\t\tcase 32:\n+\t\t\tfmt |= KATANA_CODEC_ALEN_32;\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tdev_err(component->card->dev, \"Bad frame size: %d\\n\",\n+\t\t\t\t\tparams_width(params));\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\n+\t\tswitch (params_rate(params)) {\n+\t\tcase 44100:\n+\t\t\tfmt |= KATANA_CODEC_RATE_44100;\n+\t\t\tbreak;\n+\t\tcase 48000:\n+\t\t\tfmt |= KATANA_CODEC_RATE_48000;\n+\t\t\tbreak;\n+\t\tcase 88200:\n+\t\t\tfmt |= KATANA_CODEC_RATE_88200;\n+\t\t\tbreak;\n+\t\tcase 96000:\n+\t\t\tfmt |= KATANA_CODEC_RATE_96000;\n+\t\t\tbreak;\n+\t\tcase 176400:\n+\t\t\tfmt |= KATANA_CODEC_RATE_176400;\n+\t\t\tbreak;\n+\t\tcase 192000:\n+\t\t\tfmt |= KATANA_CODEC_RATE_192000;\n+\t\t\tbreak;\n+\t\tcase 352800:\n+\t\t\tfmt |= KATANA_CODEC_RATE_352800;\n+\t\t\tbreak;\n+\t\tcase 384000:\n+\t\t\tfmt |= KATANA_CODEC_RATE_384000;\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tdev_err(component->card->dev, \"Bad sample rate: %d\\n\",\n+\t\t\t\t\tparams_rate(params));\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\n+\t\tret = regmap_write(katana_codec->regmap, KATANA_CODEC_FORMAT,\n+\t\t\t\t\tfmt);\n+\t\tif (ret != 0) {\n+\t\t\tdev_err(component->card->dev, \"Failed to set format: %d\\n\", ret);\n+\t\t\treturn ret;\n+\t\t}\n+\t\tbreak;\n+\n+\tcase SND_SOC_DAIFMT_CBS_CFS:\n+\t\tbreak;\n+\n+\tdefault:\n+\t\treturn -EINVAL;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int katana_codec_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)\n+{\n+\tstruct snd_soc_component *component = dai->component;\n+\tstruct katana_codec_priv *katana_codec =\n+\t\tsnd_soc_component_get_drvdata(component);\n+\n+\tkatana_codec->fmt = fmt;\n+\n+\treturn 0;\n+}\n+\n+int katana_codec_dai_mute_stream(struct snd_soc_dai *dai, int mute,\n+\t\t\t\t\t\tint stream)\n+{\n+\tstruct snd_soc_component *component = dai->component;\n+\tstruct katana_codec_priv *katana_codec =\n+\t\tsnd_soc_component_get_drvdata(component);\n+\tint ret = 0;\n+\n+\tret = regmap_write(katana_codec->regmap, KATANA_CODEC_MUTE_STREAM,\n+\t\t\t\tmute);\n+\tif (ret != 0) {\n+\t\tdev_err(component->card->dev, \"Failed to set mute: %d\\n\", ret);\n+\t\treturn ret;\n+\t}\n+\treturn ret;\n+}\n+\n+static const struct snd_soc_dai_ops katana_codec_dai_ops = {\n+\t.mute_stream = katana_codec_dai_mute_stream,\n+\t.hw_params = katana_codec_hw_params,\n+\t.set_fmt = katana_codec_set_fmt,\n+};\n+\n+static struct snd_soc_dai_driver katana_codec_dai = {\n+\t.name = \"allo-katana-codec\",\n+\t.playback = {\n+\t\t.stream_name = \"Playback\",\n+\t\t.channels_min = 2,\n+\t\t.channels_max = 2,\n+\t\t.rates = SNDRV_PCM_RATE_CONTINUOUS,\n+\t\t.rate_min = 44100,\n+\t\t.rate_max = 384000,\n+\t\t.formats = SNDRV_PCM_FMTBIT_S16_LE |\n+\t\t\tSNDRV_PCM_FMTBIT_S32_LE\n+\t},\n+\t.ops = &katana_codec_dai_ops,\n+};\n+\n+static struct snd_soc_component_driver katana_codec_component_driver = {\n+\t.idle_bias_on = true,\n+\n+\t.controls\t\t= katana_codec_controls,\n+\t.num_controls\t= ARRAY_SIZE(katana_codec_controls),\n+};\n+\n+static const struct regmap_range_cfg katana_codec_range = {\n+\t.name = \"Pages\", .range_min = KATANA_CODEC_VIRT_BASE,\n+\t.range_max = KATANA_CODEC_MAX_REGISTER,\n+\t.selector_reg = KATANA_CODEC_PAGE,\n+\t.selector_mask = 0xff,\n+\t.window_start = 0, .window_len = 0x100,\n+};\n+\n+const struct regmap_config katana_codec_regmap = {\n+\t.reg_bits = 8,\n+\t.val_bits = 8,\n+\n+\t.ranges = &katana_codec_range,\n+\t.num_ranges = 1,\n+\n+\t.max_register = KATANA_CODEC_MAX_REGISTER,\n+\t.readable_reg = katana_codec_readable_register,\n+\t.reg_defaults = katana_codec_reg_defaults,\n+\t.num_reg_defaults = ARRAY_SIZE(katana_codec_reg_defaults),\n+\t.cache_type = REGCACHE_RBTREE,\n+};\n+\n+static int allo_katana_component_probe(struct i2c_client *i2c,\n+\t\t\t     const struct i2c_device_id *id)\n+{\n+\tstruct regmap *regmap;\n+\tstruct regmap_config config = katana_codec_regmap;\n+\tstruct device *dev = &i2c->dev;\n+\tstruct katana_codec_priv *katana_codec;\n+\tunsigned int chip_id = 0;\n+\tint ret;\n+\n+\tregmap = devm_regmap_init_i2c(i2c, &config);\n+\tif (IS_ERR(regmap))\n+\t\treturn PTR_ERR(regmap);\n+\n+\tkatana_codec = devm_kzalloc(dev, sizeof(struct katana_codec_priv),\n+\t\t\t\t\tGFP_KERNEL);\n+\tif (!katana_codec)\n+\t\treturn -ENOMEM;\n+\n+\tdev_set_drvdata(dev, katana_codec);\n+\tkatana_codec->regmap = regmap;\n+\n+\tret = regmap_read(regmap, KATANA_CODEC_CHIP_ID_REG, &chip_id);\n+\tif ((ret != 0) || (chip_id != KATANA_CODEC_CHIP_ID)) {\n+\t\tdev_err(dev, \"Failed to read Chip or wrong Chip id: %d\\n\", ret);\n+\t\treturn ret;\n+\t}\n+\tregmap_update_bits(regmap, KATANA_CODEC_RESET, 0x01, 0x01);\n+\tmsleep(10);\n+\n+\tret = snd_soc_register_component(dev, &katana_codec_component_driver,\n+\t\t\t\t    &katana_codec_dai, 1);\n+\tif (ret != 0) {\n+\t\tdev_err(dev, \"failed to register codec: %d\\n\", ret);\n+\t\treturn ret;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int allo_katana_component_remove(struct i2c_client *i2c)\n+{\n+\tsnd_soc_unregister_component(&i2c->dev);\n+\treturn 0;\n+}\n+\n+static const struct i2c_device_id allo_katana_component_id[] = {\n+\t{ \"allo-katana-codec\", },\n+\t{ }\n+};\n+MODULE_DEVICE_TABLE(i2c, allo_katana_component_id);\n+\n+static const struct of_device_id allo_katana_codec_of_match[] = {\n+\t{ .compatible = \"allo,allo-katana-codec\", },\n+\t{ }\n+};\n+MODULE_DEVICE_TABLE(of, allo_katana_codec_of_match);\n+\n+static struct i2c_driver allo_katana_component_driver = {\n+\t.probe\t\t= allo_katana_component_probe,\n+\t.remove\t\t= allo_katana_component_remove,\n+\t.id_table\t= allo_katana_component_id,\n+\t.driver\t\t= {\n+\t.name\t\t= \"allo-katana-codec\",\n+\t.of_match_table = allo_katana_codec_of_match,\n+\t},\n+};\n+\n+module_i2c_driver(allo_katana_component_driver);\n+\n+MODULE_DESCRIPTION(\"ASoC Allo Katana Codec Driver\");\n+MODULE_AUTHOR(\"Jaikumar <jaikumar@cem-solutions.net>\");\n+MODULE_LICENSE(\"GPL v2\");\n--- /dev/null\n+++ b/sound/soc/bcm/allo-piano-dac-plus.c\n@@ -0,0 +1,987 @@\n+/*\n+ * ALSA ASoC Machine Driver for Allo Piano DAC Plus Subwoofer\n+ *\n+ * Author:\tBaswaraj K <jaikumar@cem-solutions.net>\n+ *\t\tCopyright 2016\n+ *\t\tbased on code by Daniel Matuschek <info@crazy-audio.com>\n+ *\t\tbased on code by Florian Meier <florian.meier@koalo.de>\n+ *\n+ * This program is free software; you can redistribute it and/or\n+ * modify it under the terms of the GNU General Public License\n+ * version 2 as published by the Free Software Foundation.\n+ *\n+ * This program is distributed in the hope that it will be useful, but\n+ * WITHOUT ANY WARRANTY; without even the implied warranty of\n+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU\n+ * General Public License for more details.\n+ */\n+\n+#include <linux/module.h>\n+#include <linux/platform_device.h>\n+#include <linux/gpio/consumer.h>\n+#include <sound/core.h>\n+#include <sound/pcm.h>\n+#include <sound/pcm_params.h>\n+#include <sound/soc.h>\n+#include <linux/firmware.h>\n+#include <linux/delay.h>\n+#include <sound/tlv.h>\n+#include \"../codecs/pcm512x.h\"\n+\n+#define P_DAC_LEFT_MUTE\t\t0x10\n+#define P_DAC_RIGHT_MUTE\t0x01\n+#define P_DAC_MUTE\t\t0x11\n+#define P_DAC_UNMUTE\t\t0x00\n+#define P_MUTE\t\t\t1\n+#define P_UNMUTE\t\t0\n+\n+struct dsp_code {\n+\tchar i2c_addr;\n+\tchar offset;\n+\tchar val;\n+};\n+\n+struct glb_pool {\n+\tstruct mutex lock;\n+\tunsigned int dual_mode;\n+\tunsigned int set_lowpass;\n+\tunsigned int set_mode;\n+\tunsigned int set_rate;\n+\tunsigned int dsp_page_number;\n+};\n+\n+static bool digital_gain_0db_limit = true;\n+bool glb_mclk;\n+\n+static struct gpio_desc *mute_gpio[2];\n+\n+static const char * const allo_piano_mode_texts[] = {\n+\t\"None\",\n+\t\"2.0\",\n+\t\"2.1\",\n+\t\"2.2\",\n+};\n+\n+static const SOC_ENUM_SINGLE_DECL(allo_piano_mode_enum,\n+\t\t0, 0, allo_piano_mode_texts);\n+\n+static const char * const allo_piano_dual_mode_texts[] = {\n+\t\"None\",\n+\t\"Dual-Mono\",\n+\t\"Dual-Stereo\",\n+};\n+\n+static const SOC_ENUM_SINGLE_DECL(allo_piano_dual_mode_enum,\n+\t\t0, 0, allo_piano_dual_mode_texts);\n+\n+static const char * const allo_piano_dsp_low_pass_texts[] = {\n+\t\"60\",\n+\t\"70\",\n+\t\"80\",\n+\t\"90\",\n+\t\"100\",\n+\t\"110\",\n+\t\"120\",\n+\t\"130\",\n+\t\"140\",\n+\t\"150\",\n+\t\"160\",\n+\t\"170\",\n+\t\"180\",\n+\t\"190\",\n+\t\"200\",\n+};\n+\n+static const SOC_ENUM_SINGLE_DECL(allo_piano_enum,\n+\t\t0, 0, allo_piano_dsp_low_pass_texts);\n+\n+static int __snd_allo_piano_dsp_program(struct snd_soc_pcm_runtime *rtd,\n+\t\tunsigned int mode, unsigned int rate, unsigned int lowpass)\n+{\n+\tconst struct firmware *fw;\n+\tstruct snd_soc_card *card = rtd->card;\n+\tstruct glb_pool *glb_ptr = card->drvdata;\n+\tchar firmware_name[60];\n+\tint ret = 0, dac = 0;\n+\n+\tif (rate <= 46000)\n+\t\trate = 44100;\n+\telse if (rate <= 68000)\n+\t\trate = 48000;\n+\telse if (rate <= 92000)\n+\t\trate = 88200;\n+\telse if (rate <= 136000)\n+\t\trate = 96000;\n+\telse if (rate <= 184000)\n+\t\trate = 176400;\n+\telse\n+\t\trate = 192000;\n+\n+\tif (lowpass > 14)\n+\t\tglb_ptr->set_lowpass = lowpass = 0;\n+\n+\tif (mode > 3)\n+\t\tglb_ptr->set_mode = mode = 0;\n+\n+\tif (mode > 0)\n+\t\tglb_ptr->dual_mode = 0;\n+\n+\t/* same configuration loaded */\n+\tif ((rate == glb_ptr->set_rate) && (lowpass == glb_ptr->set_lowpass)\n+\t\t\t&& (mode == glb_ptr->set_mode))\n+\t\treturn 0;\n+\n+\tswitch (mode) {\n+\tcase 0: /* None */\n+\t\treturn 1;\n+\n+\tcase 1: /* 2.0 */\n+\t\tsnd_soc_component_write(asoc_rtd_to_codec(rtd, 0)->component,\n+\t\t\t\tPCM512x_MUTE, P_DAC_UNMUTE);\n+\t\tsnd_soc_component_write(asoc_rtd_to_codec(rtd, 1)->component,\n+\t\t\t\tPCM512x_MUTE, P_DAC_MUTE);\n+\t\tglb_ptr->set_rate = rate;\n+\t\tglb_ptr->set_mode = mode;\n+\t\tglb_ptr->set_lowpass = lowpass;\n+\t\treturn 1;\n+\n+\tdefault:\n+\t\tsnd_soc_component_write(asoc_rtd_to_codec(rtd, 0)->component,\n+\t\t\t\tPCM512x_MUTE, P_DAC_UNMUTE);\n+\t\tsnd_soc_component_write(asoc_rtd_to_codec(rtd, 1)->component,\n+\t\t\t\tPCM512x_MUTE, P_DAC_UNMUTE);\n+\t}\n+\n+\tfor (dac = 0; dac < rtd->num_codecs; dac++) {\n+\t\tstruct dsp_code *dsp_code_read;\n+\t\tint i = 1;\n+\n+\t\tif (dac == 0) { /* high */\n+\t\t\tsnprintf(firmware_name, sizeof(firmware_name),\n+\t\t\t\t\"allo/piano/2.2/allo-piano-dsp-%d-%d-%d.bin\",\n+\t\t\t\trate, ((lowpass * 10) + 60), dac);\n+\t\t} else { /* low */\n+\t\t\tsnprintf(firmware_name, sizeof(firmware_name),\n+\t\t\t\t\"allo/piano/2.%d/allo-piano-dsp-%d-%d-%d.bin\",\n+\t\t\t\t(mode - 1), rate, ((lowpass * 10) + 60), dac);\n+\t\t}\n+\n+\t\tdev_info(rtd->card->dev, \"Dsp Firmware File Name: %s\\n\",\n+\t\t\t\tfirmware_name);\n+\n+\t\tret = request_firmware(&fw, firmware_name, rtd->card->dev);\n+\t\tif (ret < 0) {\n+\t\t\tdev_err(rtd->card->dev,\n+\t\t\t\t\"Error: Allo Piano Firmware %s missing. %d\\n\",\n+\t\t\t\tfirmware_name, ret);\n+\t\t\tgoto err;\n+\t\t}\n+\n+\t\twhile (i < (fw->size - 1)) {\n+\t\t\tdsp_code_read = (struct dsp_code *)&fw->data[i];\n+\n+\t\t\tif (dsp_code_read->offset == 0) {\n+\t\t\t\tglb_ptr->dsp_page_number = dsp_code_read->val;\n+\t\t\t\tret = snd_soc_component_write(asoc_rtd_to_codec(rtd, dac)->component,\n+\t\t\t\t\t\tPCM512x_PAGE_BASE(0),\n+\t\t\t\t\t\tdsp_code_read->val);\n+\n+\t\t\t} else if (dsp_code_read->offset != 0) {\n+\t\t\t\tret = snd_soc_component_write(asoc_rtd_to_codec(rtd, dac)->component,\n+\t\t\t\t\t(PCM512x_PAGE_BASE(\n+\t\t\t\t\t\tglb_ptr->dsp_page_number) +\n+\t\t\t\t\tdsp_code_read->offset),\n+\t\t\t\t\tdsp_code_read->val);\n+\t\t\t}\n+\t\t\tif (ret < 0) {\n+\t\t\t\tdev_err(rtd->card->dev,\n+\t\t\t\t\t\"Failed to write Register: %d\\n\", ret);\n+\t\t\t\trelease_firmware(fw);\n+\t\t\t\tgoto err;\n+\t\t\t}\n+\t\t\ti = i + 3;\n+\t\t}\n+\t\trelease_firmware(fw);\n+\t}\n+\tglb_ptr->set_rate = rate;\n+\tglb_ptr->set_mode = mode;\n+\tglb_ptr->set_lowpass = lowpass;\n+\treturn 1;\n+\n+err:\n+\treturn ret;\n+}\n+\n+static int snd_allo_piano_dsp_program(struct snd_soc_pcm_runtime *rtd,\n+\t\tunsigned int mode, unsigned int rate, unsigned int lowpass)\n+{\n+\tstruct snd_soc_card *card = rtd->card;\n+\tstruct glb_pool *glb_ptr = card->drvdata;\n+\tint ret = 0;\n+\n+\tmutex_lock(&glb_ptr->lock);\n+\n+\tret = __snd_allo_piano_dsp_program(rtd, mode, rate, lowpass);\n+\n+\tmutex_unlock(&glb_ptr->lock);\n+\n+\treturn ret;\n+}\n+\n+static int snd_allo_piano_dual_mode_get(struct snd_kcontrol *kcontrol,\n+\t\tstruct snd_ctl_elem_value *ucontrol)\n+{\n+\tstruct snd_soc_card *card = snd_kcontrol_chip(kcontrol);\n+\tstruct glb_pool *glb_ptr = card->drvdata;\n+\n+\tucontrol->value.integer.value[0] = glb_ptr->dual_mode;\n+\n+\treturn 0;\n+}\n+\n+static int snd_allo_piano_dual_mode_put(struct snd_kcontrol *kcontrol,\n+\t\tstruct snd_ctl_elem_value *ucontrol)\n+{\n+\tstruct snd_soc_card *card = snd_kcontrol_chip(kcontrol);\n+\tstruct glb_pool *glb_ptr = card->drvdata;\n+\tstruct snd_soc_pcm_runtime *rtd;\n+\tstruct snd_card *snd_card_ptr = card->snd_card;\n+\tstruct snd_kcontrol *kctl;\n+\tstruct soc_mixer_control *mc;\n+\tunsigned int left_val = 0, right_val = 0;\n+\n+\trtd = snd_soc_get_pcm_runtime(card, &card->dai_link[0]);\n+\n+\tif (ucontrol->value.integer.value[0] > 0) {\n+\t\tglb_ptr->dual_mode = ucontrol->value.integer.value[0];\n+\t\tglb_ptr->set_mode = 0;\n+\t} else {\n+\t\tif (glb_ptr->set_mode <= 0) {\n+\t\t\tglb_ptr->dual_mode = 1;\n+\t\t\tglb_ptr->set_mode = 0;\n+\t\t} else {\n+\t\t\tglb_ptr->dual_mode = 0;\n+\t\t\treturn 0;\n+\t\t}\n+\t}\n+\n+\tif (glb_ptr->dual_mode == 1) { // Dual Mono\n+\t\tsnd_soc_component_write(asoc_rtd_to_codec(rtd, 0)->component,\n+\t\t\t\tPCM512x_MUTE, P_DAC_RIGHT_MUTE);\n+\t\tsnd_soc_component_write(asoc_rtd_to_codec(rtd, 1)->component,\n+\t\t\t\tPCM512x_MUTE, P_DAC_LEFT_MUTE);\n+\t\tsnd_soc_component_write(asoc_rtd_to_codec(rtd, 0)->component,\n+\t\t\t\tPCM512x_DIGITAL_VOLUME_3, 0xff);\n+\t\tsnd_soc_component_write(asoc_rtd_to_codec(rtd, 1)->component,\n+\t\t\t\tPCM512x_DIGITAL_VOLUME_2, 0xff);\n+\n+\t\tlist_for_each_entry(kctl, &snd_card_ptr->controls, list) {\n+\t\t\tif (!strncmp(kctl->id.name, \"Digital Playback Volume\",\n+\t\t\t\t\tsizeof(kctl->id.name))) {\n+\t\t\t\tmc = (struct soc_mixer_control *)\n+\t\t\t\t\tkctl->private_value;\n+\t\t\t\tmc->rreg = mc->reg;\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t}\n+\t} else {\n+\t\tleft_val = snd_soc_component_read(asoc_rtd_to_codec(rtd, 0)->component,\n+\t\t\t\t\t\tPCM512x_DIGITAL_VOLUME_2);\n+\t\tright_val = snd_soc_component_read(asoc_rtd_to_codec(rtd, 1)->component,\n+\t\t\t\t\t\tPCM512x_DIGITAL_VOLUME_3);\n+\n+\t\tlist_for_each_entry(kctl, &snd_card_ptr->controls, list) {\n+\t\t\tif (!strncmp(kctl->id.name, \"Digital Playback Volume\",\n+\t\t\t\t\tsizeof(kctl->id.name))) {\n+\t\t\t\tmc = (struct soc_mixer_control *)\n+\t\t\t\t\tkctl->private_value;\n+\t\t\t\tmc->rreg = PCM512x_DIGITAL_VOLUME_3;\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t}\n+\n+\t\tsnd_soc_component_write(asoc_rtd_to_codec(rtd, 0)->component,\n+\t\t\t\tPCM512x_DIGITAL_VOLUME_3, left_val);\n+\t\tsnd_soc_component_write(asoc_rtd_to_codec(rtd, 1)->component,\n+\t\t\t\tPCM512x_DIGITAL_VOLUME_2, right_val);\n+\t\tsnd_soc_component_write(asoc_rtd_to_codec(rtd, 0)->component,\n+\t\t\t\tPCM512x_MUTE, P_DAC_UNMUTE);\n+\t\tsnd_soc_component_write(asoc_rtd_to_codec(rtd, 1)->component,\n+\t\t\t\tPCM512x_MUTE, P_DAC_UNMUTE);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int snd_allo_piano_mode_get(struct snd_kcontrol *kcontrol,\n+\t\tstruct snd_ctl_elem_value *ucontrol)\n+{\n+\tstruct snd_soc_card *card = snd_kcontrol_chip(kcontrol);\n+\tstruct glb_pool *glb_ptr = card->drvdata;\n+\n+\tucontrol->value.integer.value[0] = glb_ptr->set_mode;\n+\treturn 0;\n+}\n+\n+static int snd_allo_piano_mode_put(struct snd_kcontrol *kcontrol,\n+\t\tstruct snd_ctl_elem_value *ucontrol)\n+{\n+\tstruct snd_soc_card *card = snd_kcontrol_chip(kcontrol);\n+\tstruct snd_soc_pcm_runtime *rtd;\n+\tstruct glb_pool *glb_ptr = card->drvdata;\n+\tstruct snd_card *snd_card_ptr = card->snd_card;\n+\tstruct snd_kcontrol *kctl;\n+\tstruct soc_mixer_control *mc;\n+\tunsigned int left_val = 0, right_val = 0;\n+\n+\trtd = snd_soc_get_pcm_runtime(card, &card->dai_link[0]);\n+\n+\tif ((glb_ptr->dual_mode == 1) &&\n+\t\t\t(ucontrol->value.integer.value[0] > 0)) {\n+\t\tleft_val = snd_soc_component_read(asoc_rtd_to_codec(rtd, 0)->component,\n+\t\t\t\t\t\tPCM512x_DIGITAL_VOLUME_2);\n+\t\tright_val = snd_soc_component_read(asoc_rtd_to_codec(rtd, 1)->component,\n+\t\t\t\t\t\tPCM512x_DIGITAL_VOLUME_2);\n+\n+\t\tlist_for_each_entry(kctl, &snd_card_ptr->controls, list) {\n+\t\t\tif (!strncmp(kctl->id.name, \"Digital Playback Volume\",\n+\t\t\t\t\tsizeof(kctl->id.name))) {\n+\t\t\t\tmc = (struct soc_mixer_control *)\n+\t\t\t\t\tkctl->private_value;\n+\t\t\t\tmc->rreg = PCM512x_DIGITAL_VOLUME_3;\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t}\n+\t\tsnd_soc_component_write(asoc_rtd_to_codec(rtd, 0)->component,\n+\t\t\t\tPCM512x_DIGITAL_VOLUME_3, left_val);\n+\t\tsnd_soc_component_write(asoc_rtd_to_codec(rtd, 1)->component,\n+\t\t\t\tPCM512x_DIGITAL_VOLUME_3, right_val);\n+\t}\n+\n+\treturn(snd_allo_piano_dsp_program(rtd,\n+\t\t\t\tucontrol->value.integer.value[0],\n+\t\t\t\tglb_ptr->set_rate, glb_ptr->set_lowpass));\n+}\n+\n+static int snd_allo_piano_lowpass_get(struct snd_kcontrol *kcontrol,\n+\t\tstruct snd_ctl_elem_value *ucontrol)\n+{\n+\tstruct snd_soc_card *card = snd_kcontrol_chip(kcontrol);\n+\tstruct glb_pool *glb_ptr = card->drvdata;\n+\n+\tucontrol->value.integer.value[0] = glb_ptr->set_lowpass;\n+\treturn 0;\n+}\n+\n+static int snd_allo_piano_lowpass_put(struct snd_kcontrol *kcontrol,\n+\t\tstruct snd_ctl_elem_value *ucontrol)\n+{\n+\tstruct snd_soc_card *card = snd_kcontrol_chip(kcontrol);\n+\tstruct snd_soc_pcm_runtime *rtd;\n+\tstruct glb_pool *glb_ptr = card->drvdata;\n+\n+\trtd = snd_soc_get_pcm_runtime(card, &card->dai_link[0]);\n+\treturn(snd_allo_piano_dsp_program(rtd,\n+\t\t\t\tglb_ptr->set_mode, glb_ptr->set_rate,\n+\t\t\t\tucontrol->value.integer.value[0]));\n+}\n+\n+static int pcm512x_get_reg_sub(struct snd_kcontrol *kcontrol,\n+\t\tstruct snd_ctl_elem_value *ucontrol)\n+{\n+\tstruct soc_mixer_control *mc =\n+\t\t(struct soc_mixer_control *)kcontrol->private_value;\n+\tstruct snd_soc_card *card = snd_kcontrol_chip(kcontrol);\n+\tstruct glb_pool *glb_ptr = card->drvdata;\n+\tstruct snd_soc_pcm_runtime *rtd;\n+\tunsigned int left_val = 0;\n+\tunsigned int right_val = 0;\n+\trtd = snd_soc_get_pcm_runtime(card, &card->dai_link[0]);\n+\tright_val = snd_soc_component_read(asoc_rtd_to_codec(rtd, 1)->component,\n+\t\t\tPCM512x_DIGITAL_VOLUME_3);\n+\tif (glb_ptr->dual_mode != 1) {\n+\t\tleft_val = snd_soc_component_read(asoc_rtd_to_codec(rtd, 1)->component,\n+\t\t\t\tPCM512x_DIGITAL_VOLUME_2);\n+\n+\t} else {\n+\t\tleft_val = right_val;\n+\t}\n+\n+\tucontrol->value.integer.value[0] =\n+\t\t\t\t(~(left_val >> mc->shift)) & mc->max;\n+\tucontrol->value.integer.value[1] =\n+\t\t\t\t(~(right_val >> mc->shift)) & mc->max;\n+\n+\treturn 0;\n+}\n+\n+static int pcm512x_set_reg_sub(struct snd_kcontrol *kcontrol,\n+\t\tstruct snd_ctl_elem_value *ucontrol)\n+{\n+\tstruct soc_mixer_control *mc =\n+\t\t(struct soc_mixer_control *)kcontrol->private_value;\n+\tstruct snd_soc_card *card = snd_kcontrol_chip(kcontrol);\n+\tstruct glb_pool *glb_ptr = card->drvdata;\n+\tstruct snd_soc_pcm_runtime *rtd;\n+\tunsigned int left_val = (ucontrol->value.integer.value[0] & mc->max);\n+\tunsigned int right_val = (ucontrol->value.integer.value[1] & mc->max);\n+\tint ret = 0;\n+\n+\trtd = snd_soc_get_pcm_runtime(card, &card->dai_link[0]);\n+\tif (glb_ptr->dual_mode != 1) {\n+\t\tret = snd_soc_component_write(asoc_rtd_to_codec(rtd, 1)->component,\n+\t\t\t\tPCM512x_DIGITAL_VOLUME_2, (~left_val));\n+\t\tif (ret < 0)\n+\t\t\treturn ret;\n+\t}\n+\n+\tif (digital_gain_0db_limit) {\n+\t\tret = snd_soc_limit_volume(card, \"Subwoofer Playback Volume\",\n+\t\t\t\t\t207);\n+\t\tif (ret < 0)\n+\t\t\tdev_warn(card->dev, \"Failed to set volume limit: %d\\n\",\n+\t\t\t\tret);\n+\t}\n+\n+\tret = snd_soc_component_write(asoc_rtd_to_codec(rtd, 1)->component,\n+\t\t\tPCM512x_DIGITAL_VOLUME_3, (~right_val));\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\treturn 1;\n+}\n+\n+static int pcm512x_get_reg_sub_switch(struct snd_kcontrol *kcontrol,\n+\t\tstruct snd_ctl_elem_value *ucontrol)\n+{\n+\tstruct snd_soc_card *card = snd_kcontrol_chip(kcontrol);\n+\tstruct snd_soc_pcm_runtime *rtd;\n+\tint val = 0;\n+\n+\trtd = snd_soc_get_pcm_runtime(card, &card->dai_link[0]);\n+\tval = snd_soc_component_read(asoc_rtd_to_codec(rtd, 1)->component, PCM512x_MUTE);\n+\n+\tucontrol->value.integer.value[0] =\n+\t\t\t(val & P_DAC_LEFT_MUTE) ? P_UNMUTE : P_MUTE;\n+\tucontrol->value.integer.value[1] =\n+\t\t\t(val & P_DAC_RIGHT_MUTE) ? P_UNMUTE : P_MUTE;\n+\n+\treturn val;\n+}\n+\n+static int pcm512x_set_reg_sub_switch(struct snd_kcontrol *kcontrol,\n+\t\tstruct snd_ctl_elem_value *ucontrol)\n+{\n+\tstruct snd_soc_card *card = snd_kcontrol_chip(kcontrol);\n+\tstruct snd_soc_pcm_runtime *rtd;\n+\tstruct glb_pool *glb_ptr = card->drvdata;\n+\tunsigned int left_val = (ucontrol->value.integer.value[0]);\n+\tunsigned int right_val = (ucontrol->value.integer.value[1]);\n+\tint ret = 0;\n+\n+\trtd = snd_soc_get_pcm_runtime(card, &card->dai_link[0]);\n+\tif (glb_ptr->set_mode != 1) {\n+\t\tret = snd_soc_component_write(asoc_rtd_to_codec(rtd, 1)->component, PCM512x_MUTE,\n+\t\t\t\t~((left_val & 0x01)<<4 | (right_val & 0x01)));\n+\t\tif (ret < 0)\n+\t\t\treturn ret;\n+\t}\n+\treturn 1;\n+\n+}\n+\n+static int pcm512x_get_reg_master(struct snd_kcontrol *kcontrol,\n+\t\tstruct snd_ctl_elem_value *ucontrol)\n+{\n+\tstruct soc_mixer_control *mc =\n+\t\t(struct soc_mixer_control *)kcontrol->private_value;\n+\tstruct snd_soc_card *card = snd_kcontrol_chip(kcontrol);\n+\tstruct glb_pool *glb_ptr = card->drvdata;\n+\tstruct snd_soc_pcm_runtime *rtd;\n+\tunsigned int left_val = 0, right_val = 0;\n+\n+\trtd = snd_soc_get_pcm_runtime(card, &card->dai_link[0]);\n+\n+\tleft_val = snd_soc_component_read(asoc_rtd_to_codec(rtd, 0)->component,\n+\t\t\tPCM512x_DIGITAL_VOLUME_2);\n+\n+\tif (glb_ptr->dual_mode == 1) {\n+\t\tright_val = snd_soc_component_read(asoc_rtd_to_codec(rtd, 1)->component,\n+\t\t\t\tPCM512x_DIGITAL_VOLUME_3);\n+\t} else {\n+\t\tright_val = snd_soc_component_read(asoc_rtd_to_codec(rtd, 0)->component,\n+\t\t\t\tPCM512x_DIGITAL_VOLUME_3);\n+\t}\n+\n+\tucontrol->value.integer.value[0] =\n+\t\t(~(left_val  >> mc->shift)) & mc->max;\n+\tucontrol->value.integer.value[1] =\n+\t\t(~(right_val >> mc->shift)) & mc->max;\n+\n+\treturn 0;\n+}\n+\n+static int pcm512x_set_reg_master(struct snd_kcontrol *kcontrol,\n+\t\tstruct snd_ctl_elem_value *ucontrol)\n+{\n+\tstruct soc_mixer_control *mc =\n+\t\t(struct soc_mixer_control *)kcontrol->private_value;\n+\tstruct snd_soc_card *card = snd_kcontrol_chip(kcontrol);\n+\tstruct glb_pool *glb_ptr = card->drvdata;\n+\tstruct snd_soc_pcm_runtime *rtd;\n+\tunsigned int left_val = (ucontrol->value.integer.value[0] & mc->max);\n+\tunsigned int right_val = (ucontrol->value.integer.value[1] & mc->max);\n+\tint ret = 0;\n+\n+\trtd = snd_soc_get_pcm_runtime(card, &card->dai_link[0]);\n+\n+\tif (digital_gain_0db_limit) {\n+\t\tret = snd_soc_limit_volume(card, \"Master Playback Volume\",\n+\t\t\t\t\t207);\n+\t\tif (ret < 0)\n+\t\t\tdev_warn(card->dev, \"Failed to set volume limit: %d\\n\",\n+\t\t\t\tret);\n+\t}\n+\n+\tif (glb_ptr->dual_mode != 1) {\n+\t\tret = snd_soc_component_write(asoc_rtd_to_codec(rtd, 1)->component,\n+\t\t\t\tPCM512x_DIGITAL_VOLUME_2, (~left_val));\n+\t\tif (ret < 0)\n+\t\t\treturn ret;\n+\n+\t\tret = snd_soc_component_write(asoc_rtd_to_codec(rtd, 0)->component,\n+\t\t\t\tPCM512x_DIGITAL_VOLUME_3, (~right_val));\n+\t\tif (ret < 0)\n+\t\t\treturn ret;\n+\n+\t}\n+\n+\tret = snd_soc_component_write(asoc_rtd_to_codec(rtd, 1)->component,\n+\t\t\tPCM512x_DIGITAL_VOLUME_3, (~right_val));\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\tret = snd_soc_component_write(asoc_rtd_to_codec(rtd, 0)->component,\n+\t\t\tPCM512x_DIGITAL_VOLUME_2, (~left_val));\n+\tif (ret < 0)\n+\t\treturn ret;\n+\treturn 1;\n+}\n+\n+static int pcm512x_get_reg_master_switch(struct snd_kcontrol *kcontrol,\n+\t\tstruct snd_ctl_elem_value *ucontrol)\n+{\n+\tstruct snd_soc_card *card = snd_kcontrol_chip(kcontrol);\n+\tstruct glb_pool *glb_ptr = card->drvdata;\n+\tstruct snd_soc_pcm_runtime *rtd;\n+\tint val = 0;\n+\n+\trtd = snd_soc_get_pcm_runtime(card, &card->dai_link[0]);\n+\n+\tval = snd_soc_component_read(asoc_rtd_to_codec(rtd, 0)->component, PCM512x_MUTE);\n+\n+\tucontrol->value.integer.value[0] =\n+\t\t\t(val & P_DAC_LEFT_MUTE) ? P_UNMUTE : P_MUTE;\n+\n+\tif (glb_ptr->dual_mode == 1) {\n+\t\tval = snd_soc_component_read(asoc_rtd_to_codec(rtd, 1)->component, PCM512x_MUTE);\n+\t}\n+\tucontrol->value.integer.value[1] =\n+\t\t\t(val & P_DAC_RIGHT_MUTE) ? P_UNMUTE : P_MUTE;\n+\n+\treturn val;\n+}\n+\n+static int pcm512x_set_reg_master_switch(struct snd_kcontrol *kcontrol,\n+\t\tstruct snd_ctl_elem_value *ucontrol)\n+{\n+\tstruct snd_soc_card *card = snd_kcontrol_chip(kcontrol);\n+\tstruct snd_soc_pcm_runtime *rtd;\n+\tstruct glb_pool *glb_ptr = card->drvdata;\n+\tunsigned int left_val = (ucontrol->value.integer.value[0]);\n+\tunsigned int right_val = (ucontrol->value.integer.value[1]);\n+\tint ret = 0;\n+\n+\trtd = snd_soc_get_pcm_runtime(card, &card->dai_link[0]);\n+\tif (glb_ptr->dual_mode == 1) {\n+\t\tret = snd_soc_component_write(asoc_rtd_to_codec(rtd, 0)->component, PCM512x_MUTE,\n+\t\t\t\t~((left_val & 0x01)<<4));\n+\t\tif (ret < 0)\n+\t\t\treturn ret;\n+\t\tret = snd_soc_component_write(asoc_rtd_to_codec(rtd, 1)->component, PCM512x_MUTE,\n+\t\t\t\t~((right_val & 0x01)));\n+\t\tif (ret < 0)\n+\t\t\treturn ret;\n+\n+\t} else if (glb_ptr->set_mode == 1) {\n+\t\tret = snd_soc_component_write(asoc_rtd_to_codec(rtd, 0)->component, PCM512x_MUTE,\n+\t\t\t\t~((left_val & 0x01)<<4 | (right_val & 0x01)));\n+\t\tif (ret < 0)\n+\t\t\treturn ret;\n+\n+\t} else {\n+\t\tret = snd_soc_component_write(asoc_rtd_to_codec(rtd, 0)->component, PCM512x_MUTE,\n+\t\t\t\t~((left_val & 0x01)<<4 | (right_val & 0x01)));\n+\t\tif (ret < 0)\n+\t\t\treturn ret;\n+\n+\t\tret = snd_soc_component_write(asoc_rtd_to_codec(rtd, 1)->component, PCM512x_MUTE,\n+\t\t\t\t~((left_val & 0x01)<<4 | (right_val & 0x01)));\n+\t\tif (ret < 0)\n+\t\t\treturn ret;\n+\t}\n+\treturn 1;\n+}\n+\n+static const DECLARE_TLV_DB_SCALE(digital_tlv_sub, -10350, 50, 1);\n+static const DECLARE_TLV_DB_SCALE(digital_tlv_master, -10350, 50, 1);\n+\n+static const struct snd_kcontrol_new allo_piano_controls[] = {\n+\tSOC_ENUM_EXT(\"Subwoofer mode Route\",\n+\t\t\tallo_piano_mode_enum,\n+\t\t\tsnd_allo_piano_mode_get,\n+\t\t\tsnd_allo_piano_mode_put),\n+\n+\tSOC_ENUM_EXT(\"Dual Mode Route\",\n+\t\t\tallo_piano_dual_mode_enum,\n+\t\t\tsnd_allo_piano_dual_mode_get,\n+\t\t\tsnd_allo_piano_dual_mode_put),\n+\n+\tSOC_ENUM_EXT(\"Lowpass Route\", allo_piano_enum,\n+\t\t\tsnd_allo_piano_lowpass_get,\n+\t\t\tsnd_allo_piano_lowpass_put),\n+\n+\tSOC_DOUBLE_R_EXT_TLV(\"Subwoofer Playback Volume\",\n+\t\t\tPCM512x_DIGITAL_VOLUME_2,\n+\t\t\tPCM512x_DIGITAL_VOLUME_3, 0, 255, 1,\n+\t\t\tpcm512x_get_reg_sub,\n+\t\t\tpcm512x_set_reg_sub,\n+\t\t\tdigital_tlv_sub),\n+\n+\tSOC_DOUBLE_EXT(\"Subwoofer Playback Switch\",\n+\t\t\tPCM512x_MUTE,\n+\t\t\tPCM512x_RQML_SHIFT,\n+\t\t\tPCM512x_RQMR_SHIFT, 1, 1,\n+\t\t\tpcm512x_get_reg_sub_switch,\n+\t\t\tpcm512x_set_reg_sub_switch),\n+\n+\tSOC_DOUBLE_R_EXT_TLV(\"Master Playback Volume\",\n+\t\t\tPCM512x_DIGITAL_VOLUME_2,\n+\t\t\tPCM512x_DIGITAL_VOLUME_3, 0, 255, 1,\n+\t\t\tpcm512x_get_reg_master,\n+\t\t\tpcm512x_set_reg_master,\n+\t\t\tdigital_tlv_master),\n+\n+\tSOC_DOUBLE_EXT(\"Master Playback Switch\",\n+\t\t\tPCM512x_MUTE,\n+\t\t\tPCM512x_RQML_SHIFT,\n+\t\t\tPCM512x_RQMR_SHIFT, 1, 1,\n+\t\t\tpcm512x_get_reg_master_switch,\n+\t\t\tpcm512x_set_reg_master_switch),\n+};\n+\n+static int snd_allo_piano_dac_init(struct snd_soc_pcm_runtime *rtd)\n+{\n+\tstruct snd_soc_card *card = rtd->card;\n+\tstruct glb_pool *glb_ptr;\n+\n+\tglb_ptr = kzalloc(sizeof(struct glb_pool), GFP_KERNEL);\n+\tif (!glb_ptr)\n+\t\treturn -ENOMEM;\n+\n+\tcard->drvdata = glb_ptr;\n+\tglb_ptr->dual_mode = 2;\n+\tglb_ptr->set_mode = 0;\n+\n+\tmutex_init(&glb_ptr->lock);\n+\n+\tif (digital_gain_0db_limit) {\n+\t\tint ret;\n+\n+\t\tret = snd_soc_limit_volume(card, \"Digital Playback Volume\",\n+\t\t\t\t\t207);\n+\t\tif (ret < 0)\n+\t\t\tdev_warn(card->dev, \"Failed to set volume limit: %d\\n\",\n+\t\t\t\tret);\n+\t}\n+\treturn 0;\n+}\n+\n+static void snd_allo_piano_gpio_mute(struct snd_soc_card *card)\n+{\n+\tif (mute_gpio[0])\n+\t\tgpiod_set_value_cansleep(mute_gpio[0], P_MUTE);\n+\n+\tif (mute_gpio[1])\n+\t\tgpiod_set_value_cansleep(mute_gpio[1], P_MUTE);\n+}\n+\n+static void snd_allo_piano_gpio_unmute(struct snd_soc_card *card)\n+{\n+\tif (mute_gpio[0])\n+\t\tgpiod_set_value_cansleep(mute_gpio[0], P_UNMUTE);\n+\n+\tif (mute_gpio[1])\n+\t\tgpiod_set_value_cansleep(mute_gpio[1], P_UNMUTE);\n+}\n+\n+static int snd_allo_piano_set_bias_level(struct snd_soc_card *card,\n+\tstruct snd_soc_dapm_context *dapm, enum snd_soc_bias_level level)\n+{\n+\tstruct snd_soc_pcm_runtime *rtd;\n+\tstruct snd_soc_dai *codec_dai;\n+\n+\trtd = snd_soc_get_pcm_runtime(card, &card->dai_link[0]);\n+\tcodec_dai = asoc_rtd_to_codec(rtd, 0);\n+\n+\tif (dapm->dev != codec_dai->dev)\n+\t\treturn 0;\n+\n+\tswitch (level) {\n+\tcase SND_SOC_BIAS_PREPARE:\n+\t\tif (dapm->bias_level != SND_SOC_BIAS_STANDBY)\n+\t\t\tbreak;\n+\t\t/* UNMUTE DAC */\n+\t\tsnd_allo_piano_gpio_unmute(card);\n+\t\tbreak;\n+\n+\tcase SND_SOC_BIAS_STANDBY:\n+\t\tif (dapm->bias_level != SND_SOC_BIAS_PREPARE)\n+\t\t\tbreak;\n+\t\t/* MUTE DAC */\n+\t\tsnd_allo_piano_gpio_mute(card);\n+\t\tbreak;\n+\n+\tdefault:\n+\t\tbreak;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int snd_allo_piano_dac_startup(\n+\tstruct snd_pcm_substream *substream)\n+{\n+\tstruct snd_soc_pcm_runtime *rtd = substream->private_data;\n+\tstruct snd_soc_card *card = rtd->card;\n+\n+\tsnd_allo_piano_gpio_mute(card);\n+\n+\treturn 0;\n+}\n+\n+static int snd_allo_piano_dac_hw_params(\n+\t\tstruct snd_pcm_substream *substream,\n+\t\tstruct snd_pcm_hw_params *params)\n+{\n+\tstruct snd_soc_pcm_runtime *rtd = substream->private_data;\n+\tunsigned int rate = params_rate(params);\n+\tstruct snd_soc_card *card = rtd->card;\n+\tstruct glb_pool *glb_ptr = card->drvdata;\n+\tint ret = 0, val = 0, dac;\n+\n+\tfor (dac = 0; (glb_mclk && dac < 2); dac++) {\n+\t\t/* Configure the PLL clock reference for both the Codecs */\n+\t\tval = snd_soc_component_read(asoc_rtd_to_codec(rtd, dac)->component,\n+\t\t\t\t\tPCM512x_RATE_DET_4);\n+\n+\t\tif (val & 0x40) {\n+\t\t\tsnd_soc_component_write(asoc_rtd_to_codec(rtd, dac)->component,\n+\t\t\t\t\tPCM512x_PLL_REF,\n+\t\t\t\t\tPCM512x_SREF_BCK);\n+\n+\t\t\tdev_info(asoc_rtd_to_codec(rtd, dac)->component->dev,\n+\t\t\t\t\"Setting BCLK as input clock & Enable PLL\\n\");\n+\t\t} else {\n+\t\t\tsnd_soc_component_write(asoc_rtd_to_codec(rtd, dac)->component,\n+\t\t\t\t\tPCM512x_PLL_EN,\n+\t\t\t\t\t0x00);\n+\n+\t\t\tsnd_soc_component_write(asoc_rtd_to_codec(rtd, dac)->component,\n+\t\t\t\t\tPCM512x_PLL_REF,\n+\t\t\t\t\tPCM512x_SREF_SCK);\n+\n+\t\t\tdev_info(asoc_rtd_to_codec(rtd, dac)->component->dev,\n+\t\t\t\t\"Setting SCLK as input clock & disabled PLL\\n\");\n+\t\t}\n+\t}\n+\n+\tret = snd_allo_piano_dsp_program(rtd, glb_ptr->set_mode, rate,\n+\t\t\t\t\t\tglb_ptr->set_lowpass);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\treturn ret;\n+}\n+\n+static int snd_allo_piano_dac_prepare(\n+\tstruct snd_pcm_substream *substream)\n+{\n+\tstruct snd_soc_pcm_runtime *rtd = substream->private_data;\n+\tstruct snd_soc_card *card = rtd->card;\n+\n+\tsnd_allo_piano_gpio_unmute(card);\n+\n+\treturn 0;\n+}\n+\n+/* machine stream operations */\n+static struct snd_soc_ops snd_allo_piano_dac_ops = {\n+\t.startup = snd_allo_piano_dac_startup,\n+\t.hw_params = snd_allo_piano_dac_hw_params,\n+\t.prepare = snd_allo_piano_dac_prepare,\n+};\n+\n+static struct snd_soc_dai_link_component allo_piano_2_1_codecs[] = {\n+\t{\n+\t\t.dai_name = \"pcm512x-hifi\",\n+\t},\n+\t{\n+\t\t.dai_name = \"pcm512x-hifi\",\n+\t},\n+};\n+\n+SND_SOC_DAILINK_DEFS(allo_piano_dai_plus,\n+\tDAILINK_COMP_ARRAY(COMP_CPU(\"bcm2708-i2s.0\")),\n+\tDAILINK_COMP_ARRAY(COMP_CODEC(NULL, \"pcm512x-hifi\"),\n+\t\t\t   COMP_CODEC(NULL, \"pcm512x-hifi\")),\n+\tDAILINK_COMP_ARRAY(COMP_PLATFORM(\"bcm2708-i2s.0\")));\n+\n+static struct snd_soc_dai_link snd_allo_piano_dac_dai[] = {\n+\t{\n+\t\t.name\t\t= \"PianoDACPlus\",\n+\t\t.stream_name\t= \"PianoDACPlus\",\n+\t\t.dai_fmt\t= SND_SOC_DAIFMT_I2S |\n+\t\t\t\tSND_SOC_DAIFMT_NB_NF |\n+\t\t\t\tSND_SOC_DAIFMT_CBS_CFS,\n+\t\t.ops\t\t= &snd_allo_piano_dac_ops,\n+\t\t.init\t\t= snd_allo_piano_dac_init,\n+\t\tSND_SOC_DAILINK_REG(allo_piano_dai_plus),\n+\t},\n+};\n+\n+/* audio machine driver */\n+static struct snd_soc_card snd_allo_piano_dac = {\n+\t.name = \"PianoDACPlus\",\n+\t.owner = THIS_MODULE,\n+\t.dai_link = snd_allo_piano_dac_dai,\n+\t.num_links = ARRAY_SIZE(snd_allo_piano_dac_dai),\n+\t.controls = allo_piano_controls,\n+\t.num_controls = ARRAY_SIZE(allo_piano_controls),\n+};\n+\n+static int snd_allo_piano_dac_probe(struct platform_device *pdev)\n+{\n+\tstruct snd_soc_card *card = &snd_allo_piano_dac;\n+\tint ret = 0, i = 0;\n+\n+\tcard->dev = &pdev->dev;\n+\tplatform_set_drvdata(pdev, &snd_allo_piano_dac);\n+\n+\tif (pdev->dev.of_node) {\n+\t\tstruct device_node *i2s_node;\n+\t\tstruct snd_soc_dai_link *dai;\n+\n+\t\tdai = &snd_allo_piano_dac_dai[0];\n+\t\ti2s_node = of_parse_phandle(pdev->dev.of_node,\n+\t\t\t\t\t\t\"i2s-controller\", 0);\n+\t\tif (i2s_node) {\n+\t\t\tfor (i = 0; i < card->num_links; i++) {\n+\t\t\t\tdai->cpus->dai_name = NULL;\n+\t\t\t\tdai->cpus->of_node = i2s_node;\n+\t\t\t\tdai->platforms->name = NULL;\n+\t\t\t\tdai->platforms->of_node = i2s_node;\n+\t\t\t}\n+\t\t}\n+\t\tdigital_gain_0db_limit =\n+\t\t\t!of_property_read_bool(pdev->dev.of_node,\n+\t\t\t\t\t\t\"allo,24db_digital_gain\");\n+\n+\t\tglb_mclk = of_property_read_bool(pdev->dev.of_node,\n+\t\t\t\t\t\t\"allo,glb_mclk\");\n+\n+\t\tallo_piano_2_1_codecs[0].of_node =\n+\t\t\tof_parse_phandle(pdev->dev.of_node, \"audio-codec\", 0);\n+\t\tif (!allo_piano_2_1_codecs[0].of_node) {\n+\t\t\tdev_err(&pdev->dev,\n+\t\t\t\t\"Property 'audio-codec' missing or invalid\\n\");\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\n+\t\tallo_piano_2_1_codecs[1].of_node =\n+\t\t\tof_parse_phandle(pdev->dev.of_node, \"audio-codec\", 1);\n+\t\tif (!allo_piano_2_1_codecs[1].of_node) {\n+\t\t\tdev_err(&pdev->dev,\n+\t\t\t\t\"Property 'audio-codec' missing or invalid\\n\");\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\n+\t\tmute_gpio[0] = devm_gpiod_get_optional(&pdev->dev, \"mute1\",\n+\t\t\t\t\t\t\tGPIOD_OUT_LOW);\n+\t\tif (IS_ERR(mute_gpio[0])) {\n+\t\t\tret = PTR_ERR(mute_gpio[0]);\n+\t\t\tdev_err(&pdev->dev,\n+\t\t\t\t\"failed to get mute1 gpio6: %d\\n\", ret);\n+\t\t\treturn ret;\n+\t\t}\n+\n+\t\tmute_gpio[1] = devm_gpiod_get_optional(&pdev->dev, \"mute2\",\n+\t\t\t\t\t\t\tGPIOD_OUT_LOW);\n+\t\tif (IS_ERR(mute_gpio[1])) {\n+\t\t\tret = PTR_ERR(mute_gpio[1]);\n+\t\t\tdev_err(&pdev->dev,\n+\t\t\t\t\"failed to get mute2 gpio25: %d\\n\", ret);\n+\t\t\treturn ret;\n+\t\t}\n+\n+\t\tif (mute_gpio[0] && mute_gpio[1])\n+\t\t\tsnd_allo_piano_dac.set_bias_level =\n+\t\t\t\tsnd_allo_piano_set_bias_level;\n+\n+\t\tret = snd_soc_register_card(&snd_allo_piano_dac);\n+\t\tif (ret < 0) {\n+\t\t\tdev_err(&pdev->dev,\n+\t\t\t\t\"snd_soc_register_card() failed: %d\\n\", ret);\n+\t\t\treturn ret;\n+\t\t}\n+\n+\t\tif ((mute_gpio[0]) && (mute_gpio[1]))\n+\t\t\tsnd_allo_piano_gpio_mute(&snd_allo_piano_dac);\n+\n+\t\treturn 0;\n+\t}\n+\n+\treturn -EINVAL;\n+}\n+\n+static int snd_allo_piano_dac_remove(struct platform_device *pdev)\n+{\n+\tstruct snd_soc_card *card = platform_get_drvdata(pdev);\n+\n+\tkfree(&card->drvdata);\n+\tsnd_allo_piano_gpio_mute(&snd_allo_piano_dac);\n+\treturn snd_soc_unregister_card(&snd_allo_piano_dac);\n+}\n+\n+static const struct of_device_id snd_allo_piano_dac_of_match[] = {\n+\t{ .compatible = \"allo,piano-dac-plus\", },\n+\t{ /* sentinel */ },\n+};\n+\n+MODULE_DEVICE_TABLE(of, snd_allo_piano_dac_of_match);\n+\n+static struct platform_driver snd_allo_piano_dac_driver = {\n+\t.driver = {\n+\t\t.name = \"snd-allo-piano-dac-plus\",\n+\t\t.owner = THIS_MODULE,\n+\t\t.of_match_table = snd_allo_piano_dac_of_match,\n+\t},\n+\t.probe = snd_allo_piano_dac_probe,\n+\t.remove = snd_allo_piano_dac_remove,\n+};\n+\n+module_platform_driver(snd_allo_piano_dac_driver);\n+\n+MODULE_AUTHOR(\"Baswaraj K <jaikumar@cem-solutions.net>\");\n+MODULE_DESCRIPTION(\"ALSA ASoC Machine Driver for Allo Piano DAC Plus\");\n+MODULE_LICENSE(\"GPL v2\");\n--- /dev/null\n+++ b/sound/soc/bcm/allo-piano-dac.c\n@@ -0,0 +1,122 @@\n+/*\n+ * ALSA ASoC Machine Driver for Allo Piano DAC\n+ *\n+ * Author:\tBaswaraj K <jaikumar@cem-solutions.net>\n+ *\t\tCopyright 2016\n+ *\t\tbased on code by Daniel Matuschek <info@crazy-audio.com>\n+ *\t\tbased on code by Florian Meier <florian.meier@koalo.de>\n+ *\n+ * This program is free software; you can redistribute it and/or\n+ * modify it under the terms of the GNU General Public License\n+ * version 2 as published by the Free Software Foundation.\n+ *\n+ * This program is distributed in the hope that it will be useful, but\n+ * WITHOUT ANY WARRANTY; without even the implied warranty of\n+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\n+ * General Public License for more details.\n+ */\n+\n+#include <linux/module.h>\n+#include <linux/platform_device.h>\n+\n+#include <sound/core.h>\n+#include <sound/pcm.h>\n+#include <sound/pcm_params.h>\n+#include <sound/soc.h>\n+\n+static bool digital_gain_0db_limit = true;\n+\n+static int snd_allo_piano_dac_init(struct snd_soc_pcm_runtime *rtd)\n+{\n+\tif (digital_gain_0db_limit) {\n+\t\tint ret;\n+\t\tstruct snd_soc_card *card = rtd->card;\n+\n+\t\tret = snd_soc_limit_volume(card, \"Digital Playback Volume\",\n+\t\t\t\t\t   207);\n+\t\tif (ret < 0)\n+\t\t\tdev_warn(card->dev, \"Failed to set volume limit: %d\\n\",\n+\t\t\t\t ret);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+SND_SOC_DAILINK_DEFS(allo_piano_dai,\n+\tDAILINK_COMP_ARRAY(COMP_CPU(\"bcm2708-i2s.0\")),\n+\tDAILINK_COMP_ARRAY(COMP_CODEC(\"pcm512x.1-004c\", \"pcm512x-hifi\")),\n+\tDAILINK_COMP_ARRAY(COMP_PLATFORM(\"bcm2708-i2s.0\")));\n+\n+static struct snd_soc_dai_link snd_allo_piano_dac_dai[] = {\n+{\n+\t.name\t\t= \"Piano DAC\",\n+\t.stream_name\t= \"Piano DAC HiFi\",\n+\t.dai_fmt\t= SND_SOC_DAIFMT_I2S |\n+\t\t\t  SND_SOC_DAIFMT_NB_NF |\n+\t\t\t  SND_SOC_DAIFMT_CBS_CFS,\n+\t.init\t\t= snd_allo_piano_dac_init,\n+\tSND_SOC_DAILINK_REG(allo_piano_dai),\n+},\n+};\n+\n+/* audio machine driver */\n+static struct snd_soc_card snd_allo_piano_dac = {\n+\t.name         = \"PianoDAC\",\n+\t.owner        = THIS_MODULE,\n+\t.dai_link     = snd_allo_piano_dac_dai,\n+\t.num_links    = ARRAY_SIZE(snd_allo_piano_dac_dai),\n+};\n+\n+static int snd_allo_piano_dac_probe(struct platform_device *pdev)\n+{\n+\tint ret = 0;\n+\n+\tsnd_allo_piano_dac.dev = &pdev->dev;\n+\n+\tif (pdev->dev.of_node) {\n+\t\tstruct device_node *i2s_node;\n+\t\tstruct snd_soc_dai_link *dai;\n+\n+\t\tdai = &snd_allo_piano_dac_dai[0];\n+\t\ti2s_node = of_parse_phandle(pdev->dev.of_node,\n+\t\t\t\t\t    \"i2s-controller\", 0);\n+\n+\t\tif (i2s_node) {\n+\t\t\tdai->cpus->dai_name = NULL;\n+\t\t\tdai->cpus->of_node = i2s_node;\n+\t\t\tdai->platforms->name = NULL;\n+\t\t\tdai->platforms->of_node = i2s_node;\n+\t\t}\n+\n+\t\tdigital_gain_0db_limit = !of_property_read_bool(\n+\t\t\tpdev->dev.of_node, \"allo,24db_digital_gain\");\n+\t}\n+\n+\tret = devm_snd_soc_register_card(&pdev->dev, &snd_allo_piano_dac);\n+\tif (ret && ret != -EPROBE_DEFER)\n+\t\tdev_err(&pdev->dev,\n+\t\t\t\"snd_soc_register_card() failed: %d\\n\", ret);\n+\n+\treturn ret;\n+}\n+\n+static const struct of_device_id snd_allo_piano_dac_of_match[] = {\n+\t{ .compatible = \"allo,piano-dac\", },\n+\t{ /* sentinel */ },\n+};\n+MODULE_DEVICE_TABLE(of, snd_allo_piano_dac_of_match);\n+\n+static struct platform_driver snd_allo_piano_dac_driver = {\n+\t.driver = {\n+\t\t.name   = \"snd-allo-piano-dac\",\n+\t\t.owner  = THIS_MODULE,\n+\t\t.of_match_table = snd_allo_piano_dac_of_match,\n+\t},\n+\t.probe          = snd_allo_piano_dac_probe,\n+};\n+\n+module_platform_driver(snd_allo_piano_dac_driver);\n+\n+MODULE_AUTHOR(\"Baswaraj K <jaikumar@cem-solutions.net>\");\n+MODULE_DESCRIPTION(\"ALSA ASoC Machine Driver for Allo Piano DAC\");\n+MODULE_LICENSE(\"GPL v2\");\n--- /dev/null\n+++ b/sound/soc/bcm/audioinjector-isolated-soundcard.c\n@@ -0,0 +1,183 @@\n+/*\n+ * ASoC Driver for AudioInjector.net isolated soundcard\n+ *\n+ *  Created on: 20-February-2020\n+ *      Author: flatmax@flatmax.org\n+ *              based on audioinjector-octo-soundcard.c\n+ *\n+ * Copyright (C) 2020 Flatmax Pty. Ltd.\n+ *\n+ * This program is free software; you can redistribute it and/or\n+ * modify it under the terms of the GNU General Public License\n+ * version 2 as published by the Free Software Foundation.\n+ *\n+ * This program is distributed in the hope that it will be useful, but\n+ * WITHOUT ANY WARRANTY; without even the implied warranty of\n+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\n+ * General Public License for more details.\n+ */\n+\n+#include <linux/module.h>\n+#include <linux/types.h>\n+#include <linux/gpio/consumer.h>\n+\n+#include <sound/core.h>\n+#include <sound/soc.h>\n+#include <sound/pcm_params.h>\n+#include <sound/control.h>\n+\n+static struct gpio_desc *mute_gpio;\n+\n+static const unsigned int audioinjector_isolated_rates[] = {\n+\t192000, 96000, 48000, 32000, 24000, 16000, 8000\n+};\n+\n+static struct snd_pcm_hw_constraint_list audioinjector_isolated_constraints = {\n+\t.list = audioinjector_isolated_rates,\n+\t.count = ARRAY_SIZE(audioinjector_isolated_rates),\n+};\n+\n+static int audioinjector_isolated_dai_init(struct snd_soc_pcm_runtime *rtd)\n+{\n+\tint ret=snd_soc_dai_set_sysclk(asoc_rtd_to_codec(rtd, 0), 0, 24576000, 0);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\treturn snd_soc_dai_set_bclk_ratio(asoc_rtd_to_cpu(rtd, 0), 64);\n+}\n+\n+static int audioinjector_isolated_startup(struct snd_pcm_substream *substream)\n+{\n+\tsnd_pcm_hw_constraint_list(substream->runtime, 0,\n+\t\t\t\tSNDRV_PCM_HW_PARAM_RATE, &audioinjector_isolated_constraints);\n+\n+\treturn 0;\n+}\n+\n+static int audioinjector_isolated_trigger(struct snd_pcm_substream *substream,\n+\t\t\t\t\t\t\t\tint cmd){\n+\n+\tswitch (cmd) {\n+\tcase SNDRV_PCM_TRIGGER_STOP:\n+\tcase SNDRV_PCM_TRIGGER_SUSPEND:\n+\tcase SNDRV_PCM_TRIGGER_PAUSE_PUSH:\n+\t\tgpiod_set_value(mute_gpio, 0);\n+\t\tbreak;\n+\tcase SNDRV_PCM_TRIGGER_START:\n+\tcase SNDRV_PCM_TRIGGER_RESUME:\n+\tcase SNDRV_PCM_TRIGGER_PAUSE_RELEASE:\n+\t\tgpiod_set_value(mute_gpio, 1);\n+\t\tbreak;\n+\tdefault:\n+\t\treturn -EINVAL;\n+\t}\n+\treturn 0;\n+}\n+\n+static struct snd_soc_ops audioinjector_isolated_ops = {\n+\t.startup\t= audioinjector_isolated_startup,\n+\t.trigger = audioinjector_isolated_trigger,\n+};\n+\n+SND_SOC_DAILINK_DEFS(audioinjector_isolated,\n+\tDAILINK_COMP_ARRAY(COMP_CPU(\"bcm2708-i2s.0\")),\n+\tDAILINK_COMP_ARRAY(COMP_CODEC(\"cs4271.1-0010\", \"cs4271-hifi\")),\n+\tDAILINK_COMP_ARRAY(COMP_PLATFORM(\"bcm2708-i2s.0\")));\n+\n+static struct snd_soc_dai_link audioinjector_isolated_dai[] = {\n+\t{\n+\t\t.name = \"AudioInjector ISO\",\n+\t\t.stream_name = \"AI-HIFI\",\n+\t\t.ops = &audioinjector_isolated_ops,\n+\t\t.init = audioinjector_isolated_dai_init,\n+\t\t.symmetric_rates = 1,\n+\t\t.symmetric_channels = 1,\n+\t\t.dai_fmt = SND_SOC_DAIFMT_CBM_CFM|SND_SOC_DAIFMT_I2S|SND_SOC_DAIFMT_NB_NF,\n+\t\tSND_SOC_DAILINK_REG(audioinjector_isolated),\n+\t}\n+};\n+\n+static const struct snd_soc_dapm_widget audioinjector_isolated_widgets[] = {\n+\tSND_SOC_DAPM_OUTPUT(\"OUTPUTS\"),\n+\tSND_SOC_DAPM_INPUT(\"INPUTS\"),\n+};\n+\n+static const struct snd_soc_dapm_route audioinjector_isolated_route[] = {\n+\t/* Balanced outputs */\n+\t{\"OUTPUTS\", NULL, \"AOUTA+\"},\n+\t{\"OUTPUTS\", NULL, \"AOUTA-\"},\n+\t{\"OUTPUTS\", NULL, \"AOUTB+\"},\n+\t{\"OUTPUTS\", NULL, \"AOUTB-\"},\n+\n+\t/* Balanced inputs */\n+\t{\"AINA\", NULL, \"INPUTS\"},\n+\t{\"AINB\", NULL, \"INPUTS\"},\n+};\n+\n+static struct snd_soc_card snd_soc_audioinjector_isolated = {\n+\t.name = \"audioinjector-isolated-soundcard\",\n+\t.dai_link = audioinjector_isolated_dai,\n+\t.num_links = ARRAY_SIZE(audioinjector_isolated_dai),\n+\n+\t.dapm_widgets = audioinjector_isolated_widgets,\n+\t.num_dapm_widgets = ARRAY_SIZE(audioinjector_isolated_widgets),\n+\t.dapm_routes = audioinjector_isolated_route,\n+\t.num_dapm_routes = ARRAY_SIZE(audioinjector_isolated_route),\n+};\n+\n+static int audioinjector_isolated_probe(struct platform_device *pdev)\n+{\n+\tstruct snd_soc_card *card = &snd_soc_audioinjector_isolated;\n+\tint ret;\n+\n+\tcard->dev = &pdev->dev;\n+\n+\tif (pdev->dev.of_node) {\n+\t\tstruct snd_soc_dai_link *dai = &audioinjector_isolated_dai[0];\n+\t\tstruct device_node *i2s_node =\n+\t\t\t\t\tof_parse_phandle(pdev->dev.of_node, \"i2s-controller\", 0);\n+\n+\t\tif (i2s_node) {\n+\t\t\tdai->cpus->dai_name = NULL;\n+\t\t\tdai->cpus->of_node = i2s_node;\n+\t\t\tdai->platforms->name = NULL;\n+\t\t\tdai->platforms->of_node = i2s_node;\n+\t\t} else {\n+\t\t\t\tdev_err(&pdev->dev,\n+\t\t\t\t\"i2s-controller missing or invalid in DT\\n\");\n+\t\t\t\treturn -EINVAL;\n+\t\t}\n+\n+\t\tmute_gpio = devm_gpiod_get_optional(&pdev->dev, \"mute\", GPIOD_OUT_LOW);\n+\t\tif (IS_ERR(mute_gpio)){\n+\t\t\tdev_err(&pdev->dev, \"mute gpio not found in dt overlay\\n\");\n+\t\t\treturn PTR_ERR(mute_gpio);\n+\t\t}\n+\t}\n+\n+\tret = devm_snd_soc_register_card(&pdev->dev, card);\n+\tif (ret && ret != -EPROBE_DEFER)\n+\t\tdev_err(&pdev->dev, \"snd_soc_register_card failed (%d)\\n\", ret);\n+\treturn ret;\n+}\n+\n+static const struct of_device_id audioinjector_isolated_of_match[] = {\n+\t{ .compatible = \"ai,audioinjector-isolated-soundcard\", },\n+\t{},\n+};\n+MODULE_DEVICE_TABLE(of, audioinjector_isolated_of_match);\n+\n+static struct platform_driver audioinjector_isolated_driver = {\n+\t.driver\t= {\n+\t\t.name\t\t\t= \"audioinjector-isolated\",\n+\t\t.owner\t\t\t= THIS_MODULE,\n+\t\t.of_match_table = audioinjector_isolated_of_match,\n+\t},\n+\t.probe\t= audioinjector_isolated_probe,\n+};\n+\n+module_platform_driver(audioinjector_isolated_driver);\n+MODULE_AUTHOR(\"Matt Flax <flatmax@flatmax.org>\");\n+MODULE_DESCRIPTION(\"AudioInjector.net isolated Soundcard\");\n+MODULE_LICENSE(\"GPL v2\");\n+MODULE_ALIAS(\"platform:audioinjector-isolated-soundcard\");\n--- /dev/null\n+++ b/sound/soc/bcm/audioinjector-octo-soundcard.c\n@@ -0,0 +1,346 @@\n+/*\n+ * ASoC Driver for AudioInjector Pi octo channel soundcard (hat)\n+ *\n+ *  Created on: 27-October-2016\n+ *      Author: flatmax@flatmax.org\n+ *              based on audioinjector-pi-soundcard.c\n+ *\n+ * Copyright (C) 2016 Flatmax Pty. Ltd.\n+ *\n+ * This program is free software; you can redistribute it and/or\n+ * modify it under the terms of the GNU General Public License\n+ * version 2 as published by the Free Software Foundation.\n+ *\n+ * This program is distributed in the hope that it will be useful, but\n+ * WITHOUT ANY WARRANTY; without even the implied warranty of\n+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\n+ * General Public License for more details.\n+ */\n+\n+#include <linux/module.h>\n+#include <linux/types.h>\n+#include <linux/gpio/consumer.h>\n+\n+#include <sound/core.h>\n+#include <sound/soc.h>\n+#include <sound/pcm_params.h>\n+#include <sound/control.h>\n+\n+static struct gpio_descs *mult_gpios;\n+static struct gpio_desc *codec_rst_gpio;\n+static unsigned int audioinjector_octo_rate;\n+static bool non_stop_clocks;\n+\n+static const unsigned int audioinjector_octo_rates[] = {\n+\t96000, 48000, 32000, 24000, 16000, 8000, 88200, 44100, 29400, 22050, 14700,\n+};\n+\n+static struct snd_pcm_hw_constraint_list audioinjector_octo_constraints = {\n+\t.list = audioinjector_octo_rates,\n+\t.count = ARRAY_SIZE(audioinjector_octo_rates),\n+};\n+\n+static int audioinjector_octo_dai_init(struct snd_soc_pcm_runtime *rtd)\n+{\n+\treturn snd_soc_dai_set_bclk_ratio(asoc_rtd_to_cpu(rtd, 0), 64);\n+}\n+\n+static int audioinjector_octo_startup(struct snd_pcm_substream *substream)\n+{\n+\tstruct snd_soc_pcm_runtime *rtd = substream->private_data;\n+\tasoc_rtd_to_cpu(rtd, 0)->driver->playback.channels_min = 8;\n+\tasoc_rtd_to_cpu(rtd, 0)->driver->playback.channels_max = 8;\n+\tasoc_rtd_to_cpu(rtd, 0)->driver->capture.channels_min = 8;\n+\tasoc_rtd_to_cpu(rtd, 0)->driver->capture.channels_max = 8;\n+\tasoc_rtd_to_codec(rtd, 0)->driver->capture.channels_max = 8;\n+\n+\tsnd_pcm_hw_constraint_list(substream->runtime, 0,\n+\t\t\t\tSNDRV_PCM_HW_PARAM_RATE,\n+\t\t\t\t&audioinjector_octo_constraints);\n+\n+\treturn 0;\n+}\n+\n+static void audioinjector_octo_shutdown(struct snd_pcm_substream *substream)\n+{\n+\tstruct snd_soc_pcm_runtime *rtd = substream->private_data;\n+\tasoc_rtd_to_cpu(rtd, 0)->driver->playback.channels_min = 2;\n+\tasoc_rtd_to_cpu(rtd, 0)->driver->playback.channels_max = 2;\n+\tasoc_rtd_to_cpu(rtd, 0)->driver->capture.channels_min = 2;\n+\tasoc_rtd_to_cpu(rtd, 0)->driver->capture.channels_max = 2;\n+\tasoc_rtd_to_codec(rtd, 0)->driver->capture.channels_max = 6;\n+}\n+\n+static int audioinjector_octo_hw_params(struct snd_pcm_substream *substream,\n+\tstruct snd_pcm_hw_params *params)\n+{\n+\tstruct snd_soc_pcm_runtime *rtd = substream->private_data;\n+\n+\t// set codec DAI configuration\n+\tint ret = snd_soc_dai_set_fmt(asoc_rtd_to_codec(rtd, 0),\n+\t\t\tSND_SOC_DAIFMT_CBS_CFS|SND_SOC_DAIFMT_DSP_A|\n+\t\t\tSND_SOC_DAIFMT_NB_NF);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\t// set cpu DAI configuration\n+\tret = snd_soc_dai_set_fmt(asoc_rtd_to_cpu(rtd, 0),\n+\t\t\tSND_SOC_DAIFMT_CBM_CFM|SND_SOC_DAIFMT_I2S|\n+\t\t\tSND_SOC_DAIFMT_NB_NF);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\taudioinjector_octo_rate = params_rate(params);\n+\n+\t// Set the correct sysclock for the codec\n+\tswitch (audioinjector_octo_rate) {\n+\tcase 96000:\n+\tcase 48000:\n+\t\treturn snd_soc_dai_set_sysclk(asoc_rtd_to_codec(rtd, 0), 0, 49152000,\n+\t\t\t\t\t\t\t\t\t0);\n+\t\tbreak;\n+\tcase 24000:\n+\t\treturn snd_soc_dai_set_sysclk(asoc_rtd_to_codec(rtd, 0), 0, 49152000/2,\n+\t\t\t\t\t\t\t\t\t0);\n+\t\tbreak;\n+\tcase 32000:\n+\tcase 16000:\n+\t\treturn snd_soc_dai_set_sysclk(asoc_rtd_to_codec(rtd, 0), 0, 49152000/3,\n+\t\t\t\t\t\t\t\t\t0);\n+\t\tbreak;\n+\tcase 8000:\n+\t\treturn snd_soc_dai_set_sysclk(asoc_rtd_to_codec(rtd, 0), 0, 49152000/6,\n+\t\t\t\t\t\t\t\t\t0);\n+\t\tbreak;\n+\tcase 88200:\n+\tcase 44100:\n+\t\treturn snd_soc_dai_set_sysclk(asoc_rtd_to_codec(rtd, 0), 0, 45185400,\n+\t\t\t\t\t\t\t\t\t0);\n+\t\tbreak;\n+\tcase 22050:\n+\t\treturn snd_soc_dai_set_sysclk(asoc_rtd_to_codec(rtd, 0), 0, 45185400/2,\n+\t\t\t\t\t\t\t\t\t0);\n+\t\tbreak;\n+\tcase 29400:\n+\tcase 14700:\n+\t\treturn snd_soc_dai_set_sysclk(asoc_rtd_to_codec(rtd, 0), 0, 45185400/3,\n+\t\t\t\t\t\t\t\t\t0);\n+\t\tbreak;\n+\tdefault:\n+\t\treturn -EINVAL;\n+\t}\n+}\n+\n+static int audioinjector_octo_trigger(struct snd_pcm_substream *substream,\n+\t\t\t\t\t\t\t\tint cmd){\n+\tDECLARE_BITMAP(mult, 4);\n+\n+\tmemset(mult, 0, sizeof(mult));\n+\n+\tswitch (cmd) {\n+\tcase SNDRV_PCM_TRIGGER_STOP:\n+\tcase SNDRV_PCM_TRIGGER_SUSPEND:\n+\tcase SNDRV_PCM_TRIGGER_PAUSE_PUSH:\n+\t\tif (!non_stop_clocks)\n+\t\t\tbreak;\n+\t\t/* fall through */\n+\tcase SNDRV_PCM_TRIGGER_START:\n+\tcase SNDRV_PCM_TRIGGER_RESUME:\n+\tcase SNDRV_PCM_TRIGGER_PAUSE_RELEASE:\n+\t\tswitch (audioinjector_octo_rate) {\n+\t\tcase 96000:\n+\t\t\t__assign_bit(3, mult, 1);\n+\t\t\t/* fall through */\n+\t\tcase 88200:\n+\t\t\t__assign_bit(1, mult, 1);\n+\t\t\t__assign_bit(2, mult, 1);\n+\t\t\tbreak;\n+\t\tcase 48000:\n+\t\t\t__assign_bit(3, mult, 1);\n+\t\t\t/* fall through */\n+\t\tcase 44100:\n+\t\t\t__assign_bit(2, mult, 1);\n+\t\t\tbreak;\n+\t\tcase 32000:\n+\t\t\t__assign_bit(3, mult, 1);\n+\t\t\t/* fall through */\n+\t\tcase 29400:\n+\t\t\t__assign_bit(0, mult, 1);\n+\t\t\t__assign_bit(1, mult, 1);\n+\t\t\tbreak;\n+\t\tcase 24000:\n+\t\t\t__assign_bit(3, mult, 1);\n+\t\t\t/* fall through */\n+\t\tcase 22050:\n+\t\t\t__assign_bit(1, mult, 1);\n+\t\t\tbreak;\n+\t\tcase 16000:\n+\t\t\t__assign_bit(3, mult, 1);\n+\t\t\t/* fall through */\n+\t\tcase 14700:\n+\t\t\t__assign_bit(0, mult, 1);\n+\t\t\tbreak;\n+\t\tcase 8000:\n+\t\t\t__assign_bit(3, mult, 1);\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t\tbreak;\n+\tdefault:\n+\t\treturn -EINVAL;\n+\t}\n+\tgpiod_set_array_value_cansleep(mult_gpios->ndescs, mult_gpios->desc,\n+\t\t\t\t       NULL, mult);\n+\n+\treturn 0;\n+}\n+\n+static struct snd_soc_ops audioinjector_octo_ops = {\n+\t.startup\t= audioinjector_octo_startup,\n+\t.shutdown\t= audioinjector_octo_shutdown,\n+\t.hw_params = audioinjector_octo_hw_params,\n+\t.trigger = audioinjector_octo_trigger,\n+};\n+\n+SND_SOC_DAILINK_DEFS(audioinjector_octo,\n+\tDAILINK_COMP_ARRAY(COMP_EMPTY()),\n+\tDAILINK_COMP_ARRAY(COMP_CODEC(NULL, \"cs42448\")),\n+\tDAILINK_COMP_ARRAY(COMP_EMPTY()));\n+\n+static struct snd_soc_dai_link audioinjector_octo_dai[] = {\n+\t{\n+\t\t.name = \"AudioInjector Octo\",\n+\t\t.stream_name = \"AudioInject-HIFI\",\n+\t\t.ops = &audioinjector_octo_ops,\n+\t\t.init = audioinjector_octo_dai_init,\n+\t\t.symmetric_rates = 1,\n+\t\t.symmetric_channels = 1,\n+\t\tSND_SOC_DAILINK_REG(audioinjector_octo),\n+\t},\n+};\n+\n+static const struct snd_soc_dapm_widget audioinjector_octo_widgets[] = {\n+\tSND_SOC_DAPM_OUTPUT(\"OUTPUTS0\"),\n+\tSND_SOC_DAPM_OUTPUT(\"OUTPUTS1\"),\n+\tSND_SOC_DAPM_OUTPUT(\"OUTPUTS2\"),\n+\tSND_SOC_DAPM_OUTPUT(\"OUTPUTS3\"),\n+\tSND_SOC_DAPM_INPUT(\"INPUTS0\"),\n+\tSND_SOC_DAPM_INPUT(\"INPUTS1\"),\n+\tSND_SOC_DAPM_INPUT(\"INPUTS2\"),\n+};\n+\n+static const struct snd_soc_dapm_route audioinjector_octo_route[] = {\n+\t/* Balanced outputs */\n+\t{\"OUTPUTS0\", NULL, \"AOUT1L\"},\n+\t{\"OUTPUTS0\", NULL, \"AOUT1R\"},\n+\t{\"OUTPUTS1\", NULL, \"AOUT2L\"},\n+\t{\"OUTPUTS1\", NULL, \"AOUT2R\"},\n+\t{\"OUTPUTS2\", NULL, \"AOUT3L\"},\n+\t{\"OUTPUTS2\", NULL, \"AOUT3R\"},\n+\t{\"OUTPUTS3\", NULL, \"AOUT4L\"},\n+\t{\"OUTPUTS3\", NULL, \"AOUT4R\"},\n+\n+\t/* Balanced inputs */\n+\t{\"AIN1L\", NULL, \"INPUTS0\"},\n+\t{\"AIN1R\", NULL, \"INPUTS0\"},\n+\t{\"AIN2L\", NULL, \"INPUTS1\"},\n+\t{\"AIN2R\", NULL, \"INPUTS1\"},\n+\t{\"AIN3L\", NULL, \"INPUTS2\"},\n+\t{\"AIN3R\", NULL, \"INPUTS2\"},\n+};\n+\n+static struct snd_soc_card snd_soc_audioinjector_octo = {\n+\t.name = \"audioinjector-octo-soundcard\",\n+\t.dai_link = audioinjector_octo_dai,\n+\t.num_links = ARRAY_SIZE(audioinjector_octo_dai),\n+\n+\t.dapm_widgets = audioinjector_octo_widgets,\n+\t.num_dapm_widgets = ARRAY_SIZE(audioinjector_octo_widgets),\n+\t.dapm_routes = audioinjector_octo_route,\n+\t.num_dapm_routes = ARRAY_SIZE(audioinjector_octo_route),\n+};\n+\n+static int audioinjector_octo_probe(struct platform_device *pdev)\n+{\n+\tstruct snd_soc_card *card = &snd_soc_audioinjector_octo;\n+\tint ret;\n+\n+\tcard->dev = &pdev->dev;\n+\n+\tif (pdev->dev.of_node) {\n+\t\tstruct snd_soc_dai_link *dai = &audioinjector_octo_dai[0];\n+\t\tstruct device_node *i2s_node =\n+\t\t\t\t\tof_parse_phandle(pdev->dev.of_node,\n+\t\t\t\t\t\t\t\"i2s-controller\", 0);\n+\t\tstruct device_node *codec_node =\n+\t\t\t\t\tof_parse_phandle(pdev->dev.of_node,\n+\t\t\t\t\t\t\t\t\"codec\", 0);\n+\n+\t\tmult_gpios = devm_gpiod_get_array_optional(&pdev->dev, \"mult\",\n+\t\t\t\t\t\t\t\tGPIOD_OUT_LOW);\n+\t\tif (IS_ERR(mult_gpios))\n+\t\t\treturn PTR_ERR(mult_gpios);\n+\n+\t\tcodec_rst_gpio = devm_gpiod_get_optional(&pdev->dev, \"reset\",\n+\t\t\t\t\t\t\t\tGPIOD_OUT_LOW);\n+\t\tif (IS_ERR(codec_rst_gpio))\n+\t\t\treturn PTR_ERR(codec_rst_gpio);\n+\n+\t\tnon_stop_clocks = of_property_read_bool(pdev->dev.of_node, \"non-stop-clocks\");\n+\n+\t\tif (codec_rst_gpio)\n+\t\t\tgpiod_set_value(codec_rst_gpio, 1);\n+\t\tmsleep(500);\n+\t\tif (codec_rst_gpio)\n+\t\t\tgpiod_set_value(codec_rst_gpio, 0);\n+\t\tmsleep(500);\n+\t\tif (codec_rst_gpio)\n+\t\t\tgpiod_set_value(codec_rst_gpio, 1);\n+\t\tmsleep(500);\n+\n+\t\tif (i2s_node && codec_node) {\n+\t\t\tdai->cpus->dai_name = NULL;\n+\t\t\tdai->cpus->of_node = i2s_node;\n+\t\t\tdai->platforms->name = NULL;\n+\t\t\tdai->platforms->of_node = i2s_node;\n+\t\t\tdai->codecs->name = NULL;\n+\t\t\tdai->codecs->of_node = codec_node;\n+\t\t} else\n+\t\t\tif (!i2s_node) {\n+\t\t\t\tdev_err(&pdev->dev,\n+\t\t\t\t\"i2s-controller missing or invalid in DT\\n\");\n+\t\t\t\treturn -EINVAL;\n+\t\t\t} else {\n+\t\t\t\tdev_err(&pdev->dev,\n+\t\t\t\t\"Property 'codec' missing or invalid\\n\");\n+\t\t\t\treturn -EINVAL;\n+\t\t\t}\n+\t}\n+\n+\tret = devm_snd_soc_register_card(&pdev->dev, card);\n+\tif (ret != 0)\n+\t\tdev_err(&pdev->dev, \"snd_soc_register_card failed (%d)\\n\", ret);\n+\treturn ret;\n+}\n+\n+static const struct of_device_id audioinjector_octo_of_match[] = {\n+\t{ .compatible = \"ai,audioinjector-octo-soundcard\", },\n+\t{},\n+};\n+MODULE_DEVICE_TABLE(of, audioinjector_octo_of_match);\n+\n+static struct platform_driver audioinjector_octo_driver = {\n+\t.driver\t= {\n+\t\t.name\t\t\t= \"audioinjector-octo\",\n+\t\t.owner\t\t\t= THIS_MODULE,\n+\t\t.of_match_table = audioinjector_octo_of_match,\n+\t},\n+\t.probe\t= audioinjector_octo_probe,\n+};\n+\n+module_platform_driver(audioinjector_octo_driver);\n+MODULE_AUTHOR(\"Matt Flax <flatmax@flatmax.org>\");\n+MODULE_DESCRIPTION(\"AudioInjector.net octo Soundcard\");\n+MODULE_LICENSE(\"GPL v2\");\n+MODULE_ALIAS(\"platform:audioinjector-octo-soundcard\");\n--- /dev/null\n+++ b/sound/soc/bcm/audioinjector-pi-soundcard.c\n@@ -0,0 +1,187 @@\n+/*\n+ * ASoC Driver for AudioInjector Pi add on soundcard\n+ *\n+ *  Created on: 13-May-2016\n+ *      Author: flatmax@flatmax.org\n+ *              based on code by  Cliff Cai <Cliff.Cai@analog.com> for the ssm2602 machine blackfin.\n+ *              with help from Lars-Peter Clausen for simplifying the original code to use the dai_fmt field.\n+ *\t\ti2s_node code taken from the other sound/soc/bcm machine drivers.\n+ *\n+ * Copyright (C) 2016 Flatmax Pty. Ltd.\n+ *\n+ * This program is free software; you can redistribute it and/or\n+ * modify it under the terms of the GNU General Public License\n+ * version 2 as published by the Free Software Foundation.\n+ *\n+ * This program is distributed in the hope that it will be useful, but\n+ * WITHOUT ANY WARRANTY; without even the implied warranty of\n+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\n+ * General Public License for more details.\n+ */\n+\n+#include <linux/module.h>\n+#include <linux/types.h>\n+\n+#include <sound/core.h>\n+#include <sound/soc.h>\n+#include <sound/pcm_params.h>\n+#include <sound/control.h>\n+\n+#include \"../codecs/wm8731.h\"\n+\n+static const unsigned int bcm2835_rates_12000000[] = {\n+\t8000, 16000, 32000, 44100, 48000, 96000, 88200,\n+};\n+\n+static struct snd_pcm_hw_constraint_list bcm2835_constraints_12000000 = {\n+\t.list = bcm2835_rates_12000000,\n+\t.count = ARRAY_SIZE(bcm2835_rates_12000000),\n+};\n+\n+static int snd_audioinjector_pi_soundcard_startup(struct snd_pcm_substream *substream)\n+{\n+\t/* Setup constraints, because there is a 12 MHz XTAL on the board */\n+\tsnd_pcm_hw_constraint_list(substream->runtime, 0,\n+\t\t\t\tSNDRV_PCM_HW_PARAM_RATE,\n+\t\t\t\t&bcm2835_constraints_12000000);\n+\treturn 0;\n+}\n+\n+static int snd_audioinjector_pi_soundcard_hw_params(struct snd_pcm_substream *substream,\n+\t\t\t\t       struct snd_pcm_hw_params *params)\n+{\n+\tstruct snd_soc_pcm_runtime *rtd = substream->private_data;\n+\tstruct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);\n+\n+\tswitch (params_rate(params)){\n+\t\tcase 8000:\n+\t\t\treturn snd_soc_dai_set_bclk_ratio(cpu_dai, 1);\n+\t\tcase 16000:\n+\t\t\treturn snd_soc_dai_set_bclk_ratio(cpu_dai, 750);\n+\t\tcase 32000:\n+\t\t\treturn snd_soc_dai_set_bclk_ratio(cpu_dai, 375);\n+\t\tcase 44100:\n+\t\t\treturn snd_soc_dai_set_bclk_ratio(cpu_dai, 272);\n+\t\tcase 48000:\n+\t\t\treturn snd_soc_dai_set_bclk_ratio(cpu_dai, 250);\n+\t\tcase 88200:\n+\t\t\treturn snd_soc_dai_set_bclk_ratio(cpu_dai, 136);\n+\t\tcase 96000:\n+\t\t\treturn snd_soc_dai_set_bclk_ratio(cpu_dai, 125);\n+\t\tdefault:\n+\t\t\treturn snd_soc_dai_set_bclk_ratio(cpu_dai, 125);\n+\t}\n+}\n+\n+/* machine stream operations */\n+static struct snd_soc_ops snd_audioinjector_pi_soundcard_ops = {\n+\t.startup = snd_audioinjector_pi_soundcard_startup,\n+\t.hw_params = snd_audioinjector_pi_soundcard_hw_params,\n+};\n+\n+static int audioinjector_pi_soundcard_dai_init(struct snd_soc_pcm_runtime *rtd)\n+{\n+\treturn snd_soc_dai_set_sysclk(asoc_rtd_to_codec(rtd, 0), WM8731_SYSCLK_XTAL, 12000000, SND_SOC_CLOCK_IN);\n+}\n+\n+SND_SOC_DAILINK_DEFS(audioinjector_pi,\n+\tDAILINK_COMP_ARRAY(COMP_CPU(\"bcm2708-i2s.0\")),\n+\tDAILINK_COMP_ARRAY(COMP_CODEC(\"wm8731.1-001a\", \"wm8731-hifi\")),\n+\tDAILINK_COMP_ARRAY(COMP_PLATFORM(\"bcm2835-i2s.0\")));\n+\n+static struct snd_soc_dai_link audioinjector_pi_soundcard_dai[] = {\n+\t{\n+\t\t.name = \"AudioInjector audio\",\n+\t\t.stream_name = \"AudioInjector audio\",\n+\t\t.ops = &snd_audioinjector_pi_soundcard_ops,\n+\t\t.init = audioinjector_pi_soundcard_dai_init,\n+\t\t.dai_fmt = SND_SOC_DAIFMT_CBM_CFM|SND_SOC_DAIFMT_I2S|SND_SOC_DAIFMT_NB_NF,\n+\t\tSND_SOC_DAILINK_REG(audioinjector_pi),\n+\t},\n+};\n+\n+static const struct snd_soc_dapm_widget wm8731_dapm_widgets[] = {\n+\tSND_SOC_DAPM_HP(\"Headphone Jack\", NULL),\n+\tSND_SOC_DAPM_SPK(\"Ext Spk\", NULL),\n+\tSND_SOC_DAPM_LINE(\"Line In Jacks\", NULL),\n+\tSND_SOC_DAPM_MIC(\"Microphone\", NULL),\n+};\n+\n+static const struct snd_soc_dapm_route audioinjector_audio_map[] = {\n+\t/* headphone connected to LHPOUT, RHPOUT */\n+\t{\"Headphone Jack\", NULL, \"LHPOUT\"},\n+\t{\"Headphone Jack\", NULL, \"RHPOUT\"},\n+\n+\t/* speaker connected to LOUT, ROUT */\n+\t{\"Ext Spk\", NULL, \"ROUT\"},\n+\t{\"Ext Spk\", NULL, \"LOUT\"},\n+\n+\t/* line inputs */\n+\t{\"Line In Jacks\", NULL, \"Line Input\"},\n+\n+\t/* mic is connected to Mic Jack, with WM8731 Mic Bias */\n+\t{\"Microphone\", NULL, \"Mic Bias\"},\n+};\n+\n+static struct snd_soc_card snd_soc_audioinjector = {\n+\t.name = \"audioinjector-pi-soundcard\",\n+\t.dai_link = audioinjector_pi_soundcard_dai,\n+\t.num_links = ARRAY_SIZE(audioinjector_pi_soundcard_dai),\n+\n+\t.dapm_widgets = wm8731_dapm_widgets,\n+\t.num_dapm_widgets = ARRAY_SIZE(wm8731_dapm_widgets),\n+\t.dapm_routes = audioinjector_audio_map,\n+\t.num_dapm_routes = ARRAY_SIZE(audioinjector_audio_map),\n+};\n+\n+static int audioinjector_pi_soundcard_probe(struct platform_device *pdev)\n+{\n+\tstruct snd_soc_card *card = &snd_soc_audioinjector;\n+\tint ret;\n+\t\n+\tcard->dev = &pdev->dev;\n+\n+\tif (pdev->dev.of_node) {\n+\t\tstruct snd_soc_dai_link *dai = &audioinjector_pi_soundcard_dai[0];\n+\t\tstruct device_node *i2s_node = of_parse_phandle(pdev->dev.of_node,\n+\t\t\t\t\t\t\t\t\"i2s-controller\", 0);\n+\n+\t\tif (i2s_node) {\n+\t\t\tdai->cpus->dai_name = NULL;\n+\t\t\tdai->cpus->of_node = i2s_node;\n+\t\t\tdai->platforms->name = NULL;\n+\t\t\tdai->platforms->of_node = i2s_node;\n+\t\t} else\n+\t\t\tif (!dai->cpus->of_node) {\n+\t\t\t\tdev_err(&pdev->dev, \"Property 'i2s-controller' missing or invalid\\n\");\n+\t\t\t\treturn -EINVAL;\n+\t\t\t}\n+\t}\n+\n+\tif ((ret = devm_snd_soc_register_card(&pdev->dev, card))) {\n+\t\tdev_err(&pdev->dev, \"snd_soc_register_card failed (%d)\\n\", ret);\n+\t}\n+\treturn ret;\n+}\n+\n+static const struct of_device_id audioinjector_pi_soundcard_of_match[] = {\n+\t{ .compatible = \"ai,audioinjector-pi-soundcard\", },\n+\t{},\n+};\n+MODULE_DEVICE_TABLE(of, audioinjector_pi_soundcard_of_match);\n+\n+static struct platform_driver audioinjector_pi_soundcard_driver = {\n+       .driver         = {\n+\t\t.name   = \"audioinjector-stereo\",\n+\t\t.owner  = THIS_MODULE,\n+\t\t.of_match_table = audioinjector_pi_soundcard_of_match,\n+       },\n+       .probe          = audioinjector_pi_soundcard_probe,\n+};\n+\n+module_platform_driver(audioinjector_pi_soundcard_driver);\n+MODULE_AUTHOR(\"Matt Flax <flatmax@flatmax.org>\");\n+MODULE_DESCRIPTION(\"AudioInjector.net Pi Soundcard\");\n+MODULE_LICENSE(\"GPL v2\");\n+MODULE_ALIAS(\"platform:audioinjector-pi-soundcard\");\n+\n--- /dev/null\n+++ b/sound/soc/bcm/audiosense-pi.c\n@@ -0,0 +1,248 @@\n+/*\n+ * ASoC Driver for AudioSense add on soundcard\n+ * Author:\n+ *\tBhargav A K <anur.bhargav@gmail.com>\n+ *\tCopyright 2017\n+ *\n+ * This program is free software; you can redistribute it and/or\n+ * modify it under the terms of the GNU General Public License\n+ * version 2 as published by the Free Software Foundation.\n+ *\n+ * This program is distributed in the hope that it will be useful, but\n+ * WITHOUT ANY WARRANTY; without even the implied warranty of\n+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\n+ * General Public License for more details.\n+ */\n+\n+#include <linux/module.h>\n+#include <linux/platform_device.h>\n+#include <linux/clk.h>\n+#include <linux/i2c.h>\n+#include <sound/core.h>\n+#include <sound/pcm.h>\n+#include <sound/pcm_params.h>\n+#include <sound/soc.h>\n+#include <sound/jack.h>\n+#include <sound/control.h>\n+\n+#include <sound/tlv320aic32x4.h>\n+#include \"../codecs/tlv320aic32x4.h\"\n+\n+#define AIC32X4_SYSCLK_XTAL\t0x00\n+\n+/*\n+ * Setup Codec Sample Rates and Channels\n+ * Supported Rates:\n+ *\t8000, 11025, 16000, 22050, 32000, 44100, 48000, 64000, 88200, 96000,\n+ */\n+static const unsigned int audiosense_pi_rate[] = {\n+\t48000,\n+};\n+\n+static struct snd_pcm_hw_constraint_list audiosense_constraints_rates = {\n+\t.list = audiosense_pi_rate,\n+\t.count = ARRAY_SIZE(audiosense_pi_rate),\n+};\n+\n+static const unsigned int audiosense_pi_channels[] = {\n+\t2,\n+};\n+\n+static struct snd_pcm_hw_constraint_list audiosense_constraints_ch = {\n+\t.count = ARRAY_SIZE(audiosense_pi_channels),\n+\t.list = audiosense_pi_channels,\n+\t.mask = 0,\n+};\n+\n+/* Setup DAPM widgets and paths */\n+static const struct snd_soc_dapm_widget audiosense_pi_dapm_widgets[] = {\n+\tSND_SOC_DAPM_HP(\"Headphone Jack\", NULL),\n+\tSND_SOC_DAPM_LINE(\"Line Out\", NULL),\n+\tSND_SOC_DAPM_LINE(\"Line In\", NULL),\n+\tSND_SOC_DAPM_INPUT(\"CM_L\"),\n+\tSND_SOC_DAPM_INPUT(\"CM_R\"),\n+};\n+\n+static const struct snd_soc_dapm_route audiosense_pi_audio_map[] = {\n+\t/* Line Inputs are connected to\n+\t * (IN1_L | IN1_R)\n+\t * (IN2_L | IN2_R)\n+\t * (IN3_L | IN3_R)\n+\t */\n+\t{\"IN1_L\", NULL, \"Line In\"},\n+\t{\"IN1_R\", NULL, \"Line In\"},\n+\t{\"IN2_L\", NULL, \"Line In\"},\n+\t{\"IN2_R\", NULL, \"Line In\"},\n+\t{\"IN3_L\", NULL, \"Line In\"},\n+\t{\"IN3_R\", NULL, \"Line In\"},\n+\n+\t/* Mic is connected to IN2_L and IN2_R */\n+\t{\"Left ADC\", NULL, \"Mic Bias\"},\n+\t{\"Right ADC\", NULL, \"Mic Bias\"},\n+\n+\t/* Headphone connected to HPL, HPR */\n+\t{\"Headphone Jack\", NULL, \"HPL\"},\n+\t{\"Headphone Jack\", NULL, \"HPR\"},\n+\n+\t/* Speakers connected to LOL and LOR */\n+\t{\"Line Out\", NULL, \"LOL\"},\n+\t{\"Line Out\", NULL, \"LOR\"},\n+};\n+\n+static int audiosense_pi_card_init(struct snd_soc_pcm_runtime *rtd)\n+{\n+\t/* TODO: init of the codec specific dapm data, ignore suspend/resume */\n+\tstruct snd_soc_component *component = asoc_rtd_to_codec(rtd, 0)->component;\n+\n+\tsnd_soc_component_update_bits(component, AIC32X4_MICBIAS, 0x78,\n+\t\t\t\t      AIC32X4_MICBIAS_LDOIN |\n+\t\t\t\t      AIC32X4_MICBIAS_2075V);\n+\tsnd_soc_component_update_bits(component, AIC32X4_PWRCFG, 0x08,\n+\t\t\t\t      AIC32X4_AVDDWEAKDISABLE);\n+\tsnd_soc_component_update_bits(component, AIC32X4_LDOCTL, 0x01,\n+\t\t\t\t      AIC32X4_LDOCTLEN);\n+\n+\treturn 0;\n+}\n+\n+static int audiosense_pi_card_hw_params(\n+\t\tstruct snd_pcm_substream *substream,\n+\t\tstruct snd_pcm_hw_params *params)\n+{\n+\tint ret = 0;\n+\tstruct snd_soc_pcm_runtime *rtd = substream->private_data;\n+\tstruct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);\n+\n+\t/* Set the codec system clock, there is a 12 MHz XTAL on the board */\n+\tret = snd_soc_dai_set_sysclk(codec_dai, AIC32X4_SYSCLK_XTAL,\n+\t\t\t\t     12000000, SND_SOC_CLOCK_IN);\n+\tif (ret) {\n+\t\tdev_err(rtd->card->dev,\n+\t\t\t\"could not set codec driver clock params\\n\");\n+\t\treturn ret;\n+\t}\n+\treturn 0;\n+}\n+\n+static int audiosense_pi_card_startup(struct snd_pcm_substream *substream)\n+{\n+\tstruct snd_pcm_runtime *runtime = substream->runtime;\n+\n+\t/*\n+\t * Set codec to 48Khz Sampling, Stereo I/O and 16 bit audio\n+\t */\n+\truntime->hw.channels_max = 2;\n+\tsnd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,\n+\t\t\t\t   &audiosense_constraints_ch);\n+\n+\truntime->hw.formats = SNDRV_PCM_FMTBIT_S16_LE;\n+\tsnd_pcm_hw_constraint_msbits(runtime, 0, 16, 16);\n+\n+\n+\tsnd_pcm_hw_constraint_list(substream->runtime, 0,\n+\t\t\t\t   SNDRV_PCM_HW_PARAM_RATE,\n+\t\t\t\t   &audiosense_constraints_rates);\n+\treturn 0;\n+}\n+\n+static struct snd_soc_ops audiosense_pi_card_ops = {\n+\t.startup = audiosense_pi_card_startup,\n+\t.hw_params = audiosense_pi_card_hw_params,\n+};\n+\n+SND_SOC_DAILINK_DEFS(audiosense_pi,\n+\tDAILINK_COMP_ARRAY(COMP_CPU(\"bcm2708-i2s.0\")),\n+\tDAILINK_COMP_ARRAY(COMP_CODEC(\"tlv320aic32x4.1-0018\", \"tlv320aic32x4-hifi\")),\n+\tDAILINK_COMP_ARRAY(COMP_PLATFORM(\"bcm2708-i2s.0\")));\n+\n+static struct snd_soc_dai_link audiosense_pi_card_dai[] = {\n+\t{\n+\t\t.name           = \"TLV320AIC3204 Audio\",\n+\t\t.stream_name    = \"TLV320AIC3204 Hifi Audio\",\n+\t\t.dai_fmt        = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |\n+\t\t\tSND_SOC_DAIFMT_CBM_CFM,\n+\t\t.ops            = &audiosense_pi_card_ops,\n+\t\t.init           = audiosense_pi_card_init,\n+\t\tSND_SOC_DAILINK_REG(audiosense_pi),\n+\t},\n+};\n+\n+static struct snd_soc_card audiosense_pi_card = {\n+\t.name\t\t= \"audiosense-pi\",\n+\t.driver_name\t= \"audiosense-pi\",\n+\t.dai_link\t= audiosense_pi_card_dai,\n+\t.owner\t\t= THIS_MODULE,\n+\t.num_links\t= ARRAY_SIZE(audiosense_pi_card_dai),\n+\t.dapm_widgets\t= audiosense_pi_dapm_widgets,\n+\t.num_dapm_widgets = ARRAY_SIZE(audiosense_pi_dapm_widgets),\n+\t.dapm_routes\t= audiosense_pi_audio_map,\n+\t.num_dapm_routes = ARRAY_SIZE(audiosense_pi_audio_map),\n+};\n+\n+static int audiosense_pi_card_probe(struct platform_device *pdev)\n+{\n+\tint ret = 0;\n+\tstruct snd_soc_card *card = &audiosense_pi_card;\n+\tstruct snd_soc_dai_link *dai = &audiosense_pi_card_dai[0];\n+\tstruct device_node *i2s_node = pdev->dev.of_node;\n+\n+\tcard->dev = &pdev->dev;\n+\n+\tif (!dai) {\n+\t\tdev_err(&pdev->dev, \"DAI not found. Missing or Invalid\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\ti2s_node = of_parse_phandle(pdev->dev.of_node, \"i2s-controller\", 0);\n+\tif (!i2s_node) {\n+\t\tdev_err(&pdev->dev,\n+\t\t\t\"Property 'i2s-controller' missing or invalid\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tdai->cpus->dai_name = NULL;\n+\tdai->cpus->of_node = i2s_node;\n+\tdai->platforms->name = NULL;\n+\tdai->platforms->of_node = i2s_node;\n+\n+\tof_node_put(i2s_node);\n+\n+\tret = snd_soc_register_card(card);\n+\tif (ret && ret != -EPROBE_DEFER)\n+\t\tdev_err(&pdev->dev,\n+\t\t\t\"snd_soc_register_card() failed: %d\\n\", ret);\n+\n+\treturn ret;\n+}\n+\n+static int audiosense_pi_card_remove(struct platform_device *pdev)\n+{\n+\tstruct snd_soc_card *card = platform_get_drvdata(pdev);\n+\n+\treturn snd_soc_unregister_card(card);\n+\n+}\n+\n+static const struct of_device_id audiosense_pi_card_of_match[] = {\n+\t{ .compatible = \"as,audiosense-pi\", },\n+\t{},\n+};\n+MODULE_DEVICE_TABLE(of, audiosense_pi_card_of_match);\n+\n+static struct platform_driver audiosense_pi_card_driver = {\n+\t.driver = {\n+\t\t.name = \"audiosense-snd-card\",\n+\t\t.owner = THIS_MODULE,\n+\t\t.of_match_table = audiosense_pi_card_of_match,\n+\t},\n+\t.probe = audiosense_pi_card_probe,\n+\t.remove = audiosense_pi_card_remove,\n+};\n+\n+module_platform_driver(audiosense_pi_card_driver);\n+\n+MODULE_AUTHOR(\"Bhargav AK <anur.bhargav@gmail.com>\");\n+MODULE_DESCRIPTION(\"ASoC Driver for TLV320AIC3204 Audio\");\n+MODULE_LICENSE(\"GPL v2\");\n+MODULE_ALIAS(\"platform:audiosense-pi\");\n+\n--- /dev/null\n+++ b/sound/soc/bcm/digidac1-soundcard.c\n@@ -0,0 +1,421 @@\n+/*\n+ * ASoC Driver for RRA DigiDAC1\n+ * Copyright 2016\n+ * Author: José M. Tasende <vintage@redrocksaudio.es>\n+ * based on the HifiBerry DAC driver by Florian Meier <florian.meier@koalo.de>\n+ * and the Wolfson card driver by Nikesh Oswal, <Nikesh.Oswal@wolfsonmicro.com>\n+ * This program is free software; you can redistribute it and/or\n+ * modify it under the terms of the GNU General Public License\n+ * version 2 as published by the Free Software Foundation.\n+ *\n+ * This program is distributed in the hope that it will be useful, but\n+ * WITHOUT ANY WARRANTY; without even the implied warranty of\n+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\n+ * General Public License for more details.\n+ */\n+\n+#include <linux/module.h>\n+#include <linux/platform_device.h>\n+#include <linux/i2c.h>\n+#include <sound/core.h>\n+#include <sound/pcm.h>\n+#include <sound/pcm_params.h>\n+#include <sound/soc.h>\n+#include <sound/jack.h>\n+#include <sound/soc-dapm.h>\n+#include <sound/tlv.h>\n+#include <linux/regulator/consumer.h>\n+\n+#include \"../codecs/wm8804.h\"\n+#include \"../codecs/wm8741.h\"\n+\n+#define WM8741_NUM_SUPPLIES 2\n+\n+/* codec private data */\n+struct wm8741_priv {\n+\tstruct wm8741_platform_data pdata;\n+\tstruct regmap *regmap;\n+\tstruct regulator_bulk_data supplies[WM8741_NUM_SUPPLIES];\n+\tunsigned int sysclk;\n+\tconst struct snd_pcm_hw_constraint_list *sysclk_constraints;\n+};\n+\n+static int samplerate = 44100;\n+\n+/* New Alsa Controls not exposed by original wm8741 codec driver\t*/\n+/* in actual driver the att. adjustment is wrong because\t\t*/\n+/* this DAC has a coarse attenuation register with 4dB steps\t\t*/\n+/* and a fine level register with 0.125dB steps\t\t\t\t*/\n+/* each register has 32 steps so combining both we have\t1024 steps\t*/\n+/* of 0.125 dB.\t\t\t\t\t\t\t\t*/\n+/* The original level controls from driver are removed at startup\t*/\n+/* and replaced by the corrected ones.\t\t\t\t\t*/\n+/* The same wm8741 driver can be used for wm8741 and wm8742 devices\t*/\n+\n+static const DECLARE_TLV_DB_SCALE(dac_tlv_fine, 0, 13, 0);\n+static const DECLARE_TLV_DB_SCALE(dac_tlv_coarse, -12700, 400, 1);\n+static const char *w8741_dither[4] = {\"Off\", \"RPDF\", \"TPDF\", \"HPDF\"};\n+static const char *w8741_filter[5] = {\n+\t\t\"Type 1\", \"Type 2\", \"Type 3\", \"Type 4\", \"Type 5\"};\n+static const char *w8741_switch[2] = {\"Off\", \"On\"};\n+static const struct soc_enum w8741_enum[] = {\n+SOC_ENUM_SINGLE(WM8741_MODE_CONTROL_2, 0, 4, w8741_dither),/* dithering type */\n+SOC_ENUM_SINGLE(WM8741_FILTER_CONTROL, 0, 5, w8741_filter),/* filter type */\n+SOC_ENUM_SINGLE(WM8741_FORMAT_CONTROL, 6, 2, w8741_switch),/* phase invert */\n+SOC_ENUM_SINGLE(WM8741_VOLUME_CONTROL, 0, 2, w8741_switch),/* volume ramp */\n+SOC_ENUM_SINGLE(WM8741_VOLUME_CONTROL, 3, 2, w8741_switch),/* soft mute */\n+};\n+\n+static const struct snd_kcontrol_new w8741_snd_controls_stereo[] = {\n+SOC_DOUBLE_R_TLV(\"DAC Fine Playback Volume\", WM8741_DACLLSB_ATTENUATION,\n+\t\tWM8741_DACRLSB_ATTENUATION, 0, 31, 1, dac_tlv_fine),\n+SOC_DOUBLE_R_TLV(\"Digital Playback Volume\", WM8741_DACLMSB_ATTENUATION,\n+\t\tWM8741_DACRMSB_ATTENUATION, 0, 31, 1, dac_tlv_coarse),\n+SOC_ENUM(\"DAC Dither\", w8741_enum[0]),\n+SOC_ENUM(\"DAC Digital Filter\", w8741_enum[1]),\n+SOC_ENUM(\"DAC Phase Invert\", w8741_enum[2]),\n+SOC_ENUM(\"DAC Volume Ramp\", w8741_enum[3]),\n+SOC_ENUM(\"DAC Soft Mute\", w8741_enum[4]),\n+};\n+\n+static const struct snd_kcontrol_new w8741_snd_controls_mono_left[] = {\n+SOC_SINGLE_TLV(\"DAC Fine Playback Volume\", WM8741_DACLLSB_ATTENUATION,\n+\t\t0, 31, 0, dac_tlv_fine),\n+SOC_SINGLE_TLV(\"Digital Playback Volume\", WM8741_DACLMSB_ATTENUATION,\n+\t\t0, 31, 1, dac_tlv_coarse),\n+SOC_ENUM(\"DAC Dither\", w8741_enum[0]),\n+SOC_ENUM(\"DAC Digital Filter\", w8741_enum[1]),\n+SOC_ENUM(\"DAC Phase Invert\", w8741_enum[2]),\n+SOC_ENUM(\"DAC Volume Ramp\", w8741_enum[3]),\n+SOC_ENUM(\"DAC Soft Mute\", w8741_enum[4]),\n+};\n+\n+static const struct snd_kcontrol_new w8741_snd_controls_mono_right[] = {\n+SOC_SINGLE_TLV(\"DAC Fine Playback Volume\", WM8741_DACRLSB_ATTENUATION,\n+\t0, 31, 0, dac_tlv_fine),\n+SOC_SINGLE_TLV(\"Digital Playback Volume\", WM8741_DACRMSB_ATTENUATION,\n+\t0, 31, 1, dac_tlv_coarse),\n+SOC_ENUM(\"DAC Dither\", w8741_enum[0]),\n+SOC_ENUM(\"DAC Digital Filter\", w8741_enum[1]),\n+SOC_ENUM(\"DAC Phase Invert\", w8741_enum[2]),\n+SOC_ENUM(\"DAC Volume Ramp\", w8741_enum[3]),\n+SOC_ENUM(\"DAC Soft Mute\", w8741_enum[4]),\n+};\n+\n+static int w8741_add_controls(struct snd_soc_component *component)\n+{\n+\tstruct wm8741_priv *wm8741 = snd_soc_component_get_drvdata(component);\n+\n+\tswitch (wm8741->pdata.diff_mode) {\n+\tcase WM8741_DIFF_MODE_STEREO:\n+\tcase WM8741_DIFF_MODE_STEREO_REVERSED:\n+\t\tsnd_soc_add_component_controls(component,\n+\t\t\t\tw8741_snd_controls_stereo,\n+\t\t\t\tARRAY_SIZE(w8741_snd_controls_stereo));\n+\t\tbreak;\n+\tcase WM8741_DIFF_MODE_MONO_LEFT:\n+\t\tsnd_soc_add_component_controls(component,\n+\t\t\t\tw8741_snd_controls_mono_left,\n+\t\t\t\tARRAY_SIZE(w8741_snd_controls_mono_left));\n+\t\tbreak;\n+\tcase WM8741_DIFF_MODE_MONO_RIGHT:\n+\t\tsnd_soc_add_component_controls(component,\n+\t\t\t\tw8741_snd_controls_mono_right,\n+\t\t\t\tARRAY_SIZE(w8741_snd_controls_mono_right));\n+\t\tbreak;\n+\tdefault:\n+\t\treturn -EINVAL;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int digidac1_soundcard_init(struct snd_soc_pcm_runtime *rtd)\n+{\n+\tstruct snd_soc_component *component = asoc_rtd_to_codec(rtd, 0)->component;\n+\tstruct snd_soc_card *card = rtd->card;\n+\tstruct snd_soc_pcm_runtime *wm8741_rtd;\n+\tstruct snd_soc_component *wm8741_component;\n+\tstruct snd_card *sound_card = card->snd_card;\n+\tstruct snd_kcontrol *kctl;\n+\tint ret;\n+\n+\twm8741_rtd = snd_soc_get_pcm_runtime(card, &card->dai_link[1]);\n+\tif (!wm8741_rtd) {\n+\t\tdev_warn(card->dev, \"digidac1_soundcard_init: couldn't get wm8741 rtd\\n\");\n+\t\treturn -EFAULT;\n+\t}\n+\twm8741_component = asoc_rtd_to_codec(wm8741_rtd, 0)->component;\n+\tret = w8741_add_controls(wm8741_component);\n+\tif (ret < 0)\n+\t\tdev_warn(card->dev, \"Failed to add new wm8741 controls: %d\\n\",\n+\t\tret);\n+\n+\t/* enable TX output */\n+\tsnd_soc_component_update_bits(component, WM8804_PWRDN, 0x4, 0x0);\n+\n+\tkctl = snd_soc_card_get_kcontrol(card,\n+\t\t\"Playback Volume\");\n+\tif (kctl) {\n+\t\tkctl->vd[0].access = SNDRV_CTL_ELEM_ACCESS_READWRITE;\n+\t\tsnd_ctl_remove(sound_card, kctl);\n+\t\t}\n+\tkctl = snd_soc_card_get_kcontrol(card,\n+\t\t\"Fine Playback Volume\");\n+\tif (kctl) {\n+\t\tkctl->vd[0].access = SNDRV_CTL_ELEM_ACCESS_READWRITE;\n+\t\tsnd_ctl_remove(sound_card, kctl);\n+\t\t}\n+\treturn 0;\n+}\n+\n+static int digidac1_soundcard_startup(struct snd_pcm_substream *substream)\n+{\n+\t/* turn on wm8804 digital output */\n+\tstruct snd_soc_pcm_runtime *rtd = substream->private_data;\n+\tstruct snd_soc_component *component = asoc_rtd_to_codec(rtd, 0)->component;\n+\tstruct snd_soc_card *card = rtd->card;\n+\tstruct snd_soc_pcm_runtime *wm8741_rtd;\n+\tstruct snd_soc_component *wm8741_component;\n+\n+\tsnd_soc_component_update_bits(component, WM8804_PWRDN, 0x3c, 0x00);\n+\twm8741_rtd = snd_soc_get_pcm_runtime(card, &card->dai_link[1]);\n+\tif (!wm8741_rtd) {\n+\t\tdev_warn(card->dev, \"digidac1_soundcard_startup: couldn't get WM8741 rtd\\n\");\n+\t\treturn -EFAULT;\n+\t}\n+\twm8741_component = asoc_rtd_to_codec(wm8741_rtd, 0)->component;\n+\n+\t/* latch wm8741 level */\n+\tsnd_soc_component_update_bits(wm8741_component, WM8741_DACLLSB_ATTENUATION,\n+\t\tWM8741_UPDATELL, WM8741_UPDATELL);\n+\tsnd_soc_component_update_bits(wm8741_component, WM8741_DACLMSB_ATTENUATION,\n+\t\tWM8741_UPDATELM, WM8741_UPDATELM);\n+\tsnd_soc_component_update_bits(wm8741_component, WM8741_DACRLSB_ATTENUATION,\n+\t\tWM8741_UPDATERL, WM8741_UPDATERL);\n+\tsnd_soc_component_update_bits(wm8741_component, WM8741_DACRMSB_ATTENUATION,\n+\t\tWM8741_UPDATERM, WM8741_UPDATERM);\n+\n+\treturn 0;\n+}\n+\n+static void digidac1_soundcard_shutdown(struct snd_pcm_substream *substream)\n+{\n+\t/* turn off wm8804 digital output */\n+\tstruct snd_soc_pcm_runtime *rtd = substream->private_data;\n+\tstruct snd_soc_component *component = asoc_rtd_to_codec(rtd, 0)->component;\n+\n+\tsnd_soc_component_update_bits(component, WM8804_PWRDN, 0x3c, 0x3c);\n+}\n+\n+static int digidac1_soundcard_hw_params(struct snd_pcm_substream *substream,\n+\t\t\t\t       struct snd_pcm_hw_params *params)\n+{\n+\tstruct snd_soc_pcm_runtime *rtd = substream->private_data;\n+\tstruct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);\n+\tstruct snd_soc_component *component = asoc_rtd_to_codec(rtd, 0)->component;\n+\tstruct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);\n+\tstruct snd_soc_card *card = rtd->card;\n+\tstruct snd_soc_pcm_runtime *wm8741_rtd;\n+\tstruct snd_soc_component *wm8741_component;\n+\n+\tint sysclk = 27000000;\n+\tlong mclk_freq = 0;\n+\tint mclk_div = 1;\n+\tint sampling_freq = 1;\n+\tint ret;\n+\n+\twm8741_rtd = snd_soc_get_pcm_runtime(card, &card->dai_link[1]);\n+\tif (!wm8741_rtd) {\n+\t\tdev_warn(card->dev, \"digidac1_soundcard_hw_params: couldn't get WM8741 rtd\\n\");\n+\t\treturn -EFAULT;\n+\t}\n+\twm8741_component = asoc_rtd_to_codec(wm8741_rtd, 0)->component;\n+\tsamplerate = params_rate(params);\n+\n+\tif (samplerate <= 96000) {\n+\t\tmclk_freq = samplerate*256;\n+\t\tmclk_div = WM8804_MCLKDIV_256FS;\n+\t} else {\n+\t\tmclk_freq = samplerate*128;\n+\t\tmclk_div = WM8804_MCLKDIV_128FS;\n+\t\t}\n+\n+\tswitch (samplerate) {\n+\tcase 32000:\n+\t\tsampling_freq = 0x03;\n+\t\tbreak;\n+\tcase 44100:\n+\t\tsampling_freq = 0x00;\n+\t\tbreak;\n+\tcase 48000:\n+\t\tsampling_freq = 0x02;\n+\t\tbreak;\n+\tcase 88200:\n+\t\tsampling_freq = 0x08;\n+\t\tbreak;\n+\tcase 96000:\n+\t\tsampling_freq = 0x0a;\n+\t\tbreak;\n+\tcase 176400:\n+\t\tsampling_freq = 0x0c;\n+\t\tbreak;\n+\tcase 192000:\n+\t\tsampling_freq = 0x0e;\n+\t\tbreak;\n+\tdefault:\n+\t\tdev_err(card->dev,\n+\t\t\"Failed to set WM8804 SYSCLK, unsupported samplerate %d\\n\",\n+\t\tsamplerate);\n+\t}\n+\n+\tsnd_soc_dai_set_clkdiv(codec_dai, WM8804_MCLK_DIV, mclk_div);\n+\tsnd_soc_dai_set_pll(codec_dai, 0, 0, sysclk, mclk_freq);\n+\n+\tret = snd_soc_dai_set_sysclk(codec_dai, WM8804_TX_CLKSRC_PLL,\n+\t\tsysclk, SND_SOC_CLOCK_OUT);\n+\tif (ret < 0) {\n+\t\tdev_err(card->dev,\n+\t\t\"Failed to set WM8804 SYSCLK: %d\\n\", ret);\n+\t\treturn ret;\n+\t}\n+\t/* Enable wm8804 TX output */\n+\tsnd_soc_component_update_bits(component, WM8804_PWRDN, 0x4, 0x0);\n+\n+\t/* wm8804 Power on */\n+\tsnd_soc_component_update_bits(component, WM8804_PWRDN, 0x9, 0);\n+\n+\t/* wm8804 set sampling frequency status bits */\n+\tsnd_soc_component_update_bits(component, WM8804_SPDTX4, 0x0f, sampling_freq);\n+\n+\t/* Now update wm8741 registers for the correct oversampling */\n+\tif (samplerate <= 48000)\n+\t\tsnd_soc_component_update_bits(wm8741_component, WM8741_MODE_CONTROL_1,\n+\t\t WM8741_OSR_MASK, 0x00);\n+\telse if (samplerate <= 96000)\n+\t\tsnd_soc_component_update_bits(wm8741_component, WM8741_MODE_CONTROL_1,\n+\t\t WM8741_OSR_MASK, 0x20);\n+\telse\n+\t\tsnd_soc_component_update_bits(wm8741_component, WM8741_MODE_CONTROL_1,\n+\t\t WM8741_OSR_MASK, 0x40);\n+\n+\t/* wm8741 bit size */\n+\tswitch (params_width(params)) {\n+\tcase 16:\n+\t\tsnd_soc_component_update_bits(wm8741_component, WM8741_FORMAT_CONTROL,\n+\t\t WM8741_IWL_MASK, 0x00);\n+\t\tbreak;\n+\tcase 20:\n+\t\tsnd_soc_component_update_bits(wm8741_component, WM8741_FORMAT_CONTROL,\n+\t\t WM8741_IWL_MASK, 0x01);\n+\t\tbreak;\n+\tcase 24:\n+\t\tsnd_soc_component_update_bits(wm8741_component, WM8741_FORMAT_CONTROL,\n+\t\t WM8741_IWL_MASK, 0x02);\n+\t\tbreak;\n+\tcase 32:\n+\t\tsnd_soc_component_update_bits(wm8741_component, WM8741_FORMAT_CONTROL,\n+\t\t WM8741_IWL_MASK, 0x03);\n+\t\tbreak;\n+\tdefault:\n+\t\tdev_dbg(card->dev, \"wm8741_hw_params:    Unsupported bit size param = %d\",\n+\t\t\tparams_width(params));\n+\t\treturn -EINVAL;\n+\t}\n+\n+\treturn snd_soc_dai_set_bclk_ratio(cpu_dai, 64);\n+}\n+/* machine stream operations */\n+static struct snd_soc_ops digidac1_soundcard_ops = {\n+\t.hw_params\t= digidac1_soundcard_hw_params,\n+\t.startup\t= digidac1_soundcard_startup,\n+\t.shutdown\t= digidac1_soundcard_shutdown,\n+};\n+\n+SND_SOC_DAILINK_DEFS(digidac1,\n+\tDAILINK_COMP_ARRAY(COMP_CPU(\"bcm2708-i2s.0\")),\n+\tDAILINK_COMP_ARRAY(COMP_CODEC(\"wm8804.1-003b\", \"wm8804-spdif\")),\n+\tDAILINK_COMP_ARRAY(COMP_PLATFORM(\"bcm2835-i2s.0\")));\n+\n+SND_SOC_DAILINK_DEFS(digidac11,\n+\tDAILINK_COMP_ARRAY(COMP_CPU(\"wm8804-spdif\")),\n+\tDAILINK_COMP_ARRAY(COMP_CODEC(\"wm8741.1-001a\", \"wm8741\")),\n+\tDAILINK_COMP_ARRAY(COMP_EMPTY()));\n+\n+static struct snd_soc_dai_link digidac1_soundcard_dai[] = {\n+\t{\n+\t.name\t\t= \"RRA DigiDAC1\",\n+\t.stream_name\t= \"RRA DigiDAC1 HiFi\",\n+\t.dai_fmt\t= SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |\n+\t\t\t\tSND_SOC_DAIFMT_CBM_CFM,\n+\t.ops\t\t= &digidac1_soundcard_ops,\n+\t.init\t\t= digidac1_soundcard_init,\n+\tSND_SOC_DAILINK_REG(digidac1),\n+\t},\n+\t{\n+\t.name\t\t= \"RRA DigiDAC11\",\n+\t.stream_name\t= \"RRA DigiDAC11 HiFi\",\n+\t.dai_fmt\t= SND_SOC_DAIFMT_I2S\n+\t\t\t| SND_SOC_DAIFMT_NB_NF\n+\t\t\t| SND_SOC_DAIFMT_CBS_CFS,\n+\tSND_SOC_DAILINK_REG(digidac11),\n+\t},\n+};\n+\n+/* audio machine driver */\n+static struct snd_soc_card digidac1_soundcard = {\n+\t.name\t\t= \"digidac1-soundcard\",\n+\t.owner\t\t= THIS_MODULE,\n+\t.dai_link\t= digidac1_soundcard_dai,\n+\t.num_links\t= ARRAY_SIZE(digidac1_soundcard_dai),\n+};\n+\n+static int digidac1_soundcard_probe(struct platform_device *pdev)\n+{\n+\tint ret = 0;\n+\n+\tdigidac1_soundcard.dev = &pdev->dev;\n+\n+\tif (pdev->dev.of_node) {\n+\t\tstruct device_node *i2s_node;\n+\t\tstruct snd_soc_dai_link *dai = &digidac1_soundcard_dai[0];\n+\n+\t\ti2s_node = of_parse_phandle(pdev->dev.of_node,\n+\t\t\t\t\t\"i2s-controller\", 0);\n+\n+\t\tif (i2s_node) {\n+\t\t\tdai->cpus->dai_name = NULL;\n+\t\t\tdai->cpus->of_node = i2s_node;\n+\t\t\tdai->platforms->name = NULL;\n+\t\t\tdai->platforms->of_node = i2s_node;\n+\t\t}\n+\t}\n+\n+\tret = devm_snd_soc_register_card(&pdev->dev, &digidac1_soundcard);\n+\tif (ret && ret != -EPROBE_DEFER)\n+\t\tdev_err(&pdev->dev, \"snd_soc_register_card() failed: %d\\n\",\n+\t\t\tret);\n+\n+\treturn ret;\n+}\n+\n+static const struct of_device_id digidac1_soundcard_of_match[] = {\n+\t{ .compatible = \"rra,digidac1-soundcard\", },\n+\t{},\n+};\n+MODULE_DEVICE_TABLE(of, digidac1_soundcard_of_match);\n+\n+static struct platform_driver digidac1_soundcard_driver = {\n+\t.driver = {\n+\t\t\t.name\t\t= \"digidac1-audio\",\n+\t\t\t.owner\t\t= THIS_MODULE,\n+\t\t\t.of_match_table\t= digidac1_soundcard_of_match,\n+\t},\n+\t.probe\t\t= digidac1_soundcard_probe,\n+};\n+\n+module_platform_driver(digidac1_soundcard_driver);\n+\n+MODULE_AUTHOR(\"José M. Tasende <vintage@redrocksaudio.es>\");\n+MODULE_DESCRIPTION(\"ASoC Driver for RRA DigiDAC1\");\n+MODULE_LICENSE(\"GPL v2\");\n--- /dev/null\n+++ b/sound/soc/bcm/dionaudio_loco-v2.c\n@@ -0,0 +1,117 @@\n+/*\n+ * ASoC Driver for Dion Audio LOCO-V2 DAC-AMP\n+ *\n+ * Author:      Miquel Blauw <info@dionaudio.nl>\n+ *              Copyright 2017\n+ *\n+ * Based on the software of the RPi-DAC writen by Florian Meier\n+ *\n+ * This program is free software; you can redistribute it and/or\n+ * modify it under the terms of the GNU General Public License\n+ * version 2 as published by the Free Software Foundation.\n+ *\n+ * This program is distributed in the hope that it will be useful, but\n+ * WITHOUT ANY WARRANTY; without even the implied warranty of\n+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\n+ * General Public License for more details.\n+ */\n+\n+#include <linux/module.h>\n+#include <linux/platform_device.h>\n+\n+#include <sound/core.h>\n+#include <sound/pcm.h>\n+#include <sound/pcm_params.h>\n+#include <sound/soc.h>\n+#include <sound/jack.h>\n+\n+static bool digital_gain_0db_limit = true;\n+\n+static int snd_rpi_dionaudio_loco_v2_init(struct snd_soc_pcm_runtime *rtd)\n+{\n+\tif (digital_gain_0db_limit) {\n+\t\tint ret;\n+\t\tstruct snd_soc_card *card = rtd->card;\n+\n+\t\tret = snd_soc_limit_volume(card, \"Digital Playback Volume\", 207);\n+\t\tif (ret < 0)\n+\t\t\tdev_warn(card->dev, \"Failed to set volume limit: %d\\n\", ret);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+SND_SOC_DAILINK_DEFS(dionaudio_loco_v2,\n+\tDAILINK_COMP_ARRAY(COMP_CPU(\"bcm2708-i2s.0\")),\n+\tDAILINK_COMP_ARRAY(COMP_CODEC(\"pcm512x.1-004d\", \"pcm512x-hifi\")),\n+\tDAILINK_COMP_ARRAY(COMP_PLATFORM(\"bcm2708-i2s.0\")));\n+\n+static struct snd_soc_dai_link snd_rpi_dionaudio_loco_v2_dai[] = {\n+{\n+\t.name\t\t= \"DionAudio LOCO-V2\",\n+\t.stream_name\t= \"DionAudio LOCO-V2 DAC-AMP\",\n+\t.dai_fmt\t= SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |\n+\t\t\t  SND_SOC_DAIFMT_CBS_CFS,\n+\t.init\t\t= snd_rpi_dionaudio_loco_v2_init,\n+\tSND_SOC_DAILINK_REG(dionaudio_loco_v2),\n+},};\n+\n+/* audio machine driver */\n+static struct snd_soc_card snd_rpi_dionaudio_loco_v2 = {\n+\t.name         = \"Dion Audio LOCO-V2\",\n+\t.dai_link     = snd_rpi_dionaudio_loco_v2_dai,\n+\t.num_links    = ARRAY_SIZE(snd_rpi_dionaudio_loco_v2_dai),\n+};\n+\n+static int snd_rpi_dionaudio_loco_v2_probe(struct platform_device *pdev)\n+{\n+\tint ret = 0;\n+\n+\tsnd_rpi_dionaudio_loco_v2.dev = &pdev->dev;\n+\n+\tif (pdev->dev.of_node) {\n+\t\tstruct device_node *i2s_node;\n+\t\tstruct snd_soc_dai_link *dai =\n+\t\t\t\t\t&snd_rpi_dionaudio_loco_v2_dai[0];\n+\n+\t\ti2s_node = of_parse_phandle(pdev->dev.of_node,\n+\t\t\t\t\t    \"i2s-controller\", 0);\n+\t\tif (i2s_node) {\n+\t\t\tdai->cpus->dai_name = NULL;\n+\t\t\tdai->cpus->of_node = i2s_node;\n+\t\t\tdai->platforms->name = NULL;\n+\t\t\tdai->platforms->of_node = i2s_node;\n+\t\t}\n+\n+\t\tdigital_gain_0db_limit = !of_property_read_bool(\n+\t\t\tpdev->dev.of_node, \"dionaudio,24db_digital_gain\");\n+\t}\n+\n+\tret = devm_snd_soc_register_card(&pdev->dev, &snd_rpi_dionaudio_loco_v2);\n+\tif (ret)\n+\t\tdev_err(&pdev->dev, \"snd_soc_register_card() failed: %d\\n\",\n+\t\t\tret);\n+\n+\treturn ret;\n+}\n+\n+static const struct of_device_id dionaudio_of_match[] = {\n+\t{ .compatible = \"dionaudio,dionaudio-loco-v2\", },\n+\t{},\n+};\n+MODULE_DEVICE_TABLE(of, dionaudio_of_match);\n+\n+static struct platform_driver snd_rpi_dionaudio_loco_v2_driver = {\n+\t.driver = {\n+\t\t.name   = \"snd-rpi-dionaudio-loco-v2\",\n+\t\t.owner  = THIS_MODULE,\n+\t\t.of_match_table = dionaudio_of_match,\n+\t},\n+\t.probe          = snd_rpi_dionaudio_loco_v2_probe,\n+};\n+\n+module_platform_driver(snd_rpi_dionaudio_loco_v2_driver);\n+\n+MODULE_AUTHOR(\"Miquel Blauw <info@dionaudio.nl>\");\n+MODULE_DESCRIPTION(\"ASoC Driver for DionAudio LOCO-V2\");\n+MODULE_LICENSE(\"GPL v2\");\n--- /dev/null\n+++ b/sound/soc/bcm/dionaudio_loco.c\n@@ -0,0 +1,117 @@\n+/*\n+ * ASoC Driver for Dion Audio LOCO DAC-AMP\n+ *\n+ * Author:      Miquel Blauw <info@dionaudio.nl>\n+ *              Copyright 2016\n+ *\n+ * Based on the software of the RPi-DAC writen by Florian Meier\n+ *\n+ * This program is free software; you can redistribute it and/or\n+ * modify it under the terms of the GNU General Public License\n+ * version 2 as published by the Free Software Foundation.\n+ *\n+ * This program is distributed in the hope that it will be useful, but\n+ * WITHOUT ANY WARRANTY; without even the implied warranty of\n+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\n+ * General Public License for more details.\n+ */\n+\n+#include <linux/module.h>\n+#include <linux/platform_device.h>\n+\n+#include <sound/core.h>\n+#include <sound/pcm.h>\n+#include <sound/pcm_params.h>\n+#include <sound/soc.h>\n+#include <sound/jack.h>\n+\n+static int snd_rpi_dionaudio_loco_hw_params(\n+\tstruct snd_pcm_substream *substream, struct snd_pcm_hw_params *params)\n+{\n+\tstruct snd_soc_pcm_runtime *rtd = substream->private_data;\n+\tstruct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);\n+\n+\tunsigned int sample_bits =\n+\t\tsnd_pcm_format_physical_width(params_format(params));\n+\n+\treturn snd_soc_dai_set_bclk_ratio(cpu_dai, sample_bits * 2);\n+}\n+\n+/* machine stream operations */\n+static struct snd_soc_ops snd_rpi_dionaudio_loco_ops = {\n+\t.hw_params = snd_rpi_dionaudio_loco_hw_params,\n+};\n+\n+SND_SOC_DAILINK_DEFS(dionaudio_loco,\n+\tDAILINK_COMP_ARRAY(COMP_CPU(\"bcm2708-i2s.0\")),\n+\tDAILINK_COMP_ARRAY(COMP_CODEC(\"pcm5102a-codec\", \"pcm5102a-hifi\")),\n+\tDAILINK_COMP_ARRAY(COMP_PLATFORM(\"bcm2708-i2s.0\")));\n+\n+static struct snd_soc_dai_link snd_rpi_dionaudio_loco_dai[] = {\n+{\n+\t.name\t\t= \"DionAudio LOCO\",\n+\t.stream_name\t= \"DionAudio LOCO DAC-AMP\",\n+\t.dai_fmt\t= SND_SOC_DAIFMT_I2S |\n+\t\t\t  SND_SOC_DAIFMT_NB_NF |\n+\t\t\t  SND_SOC_DAIFMT_CBS_CFS,\n+\t.ops\t\t= &snd_rpi_dionaudio_loco_ops,\n+\tSND_SOC_DAILINK_REG(dionaudio_loco),\n+},\n+};\n+\n+/* audio machine driver */\n+static struct snd_soc_card snd_rpi_dionaudio_loco = {\n+\t.name\t\t= \"snd_rpi_dionaudio_loco\",\n+\t.dai_link\t= snd_rpi_dionaudio_loco_dai,\n+\t.num_links\t= ARRAY_SIZE(snd_rpi_dionaudio_loco_dai),\n+};\n+\n+static int snd_rpi_dionaudio_loco_probe(struct platform_device *pdev)\n+{\n+\tstruct device_node *np;\n+\tint ret = 0;\n+\n+\tsnd_rpi_dionaudio_loco.dev = &pdev->dev;\n+\n+\tnp = pdev->dev.of_node;\n+\tif (np) {\n+\t\tstruct snd_soc_dai_link *dai = &snd_rpi_dionaudio_loco_dai[0];\n+\t\tstruct device_node *i2s_np;\n+\n+\t\ti2s_np = of_parse_phandle(np, \"i2s-controller\", 0);\n+\t\tif (i2s_np) {\n+\t\t\tdai->cpus->dai_name = NULL;\n+\t\t\tdai->cpus->of_node = i2s_np;\n+\t\t\tdai->platforms->name = NULL;\n+\t\t\tdai->platforms->of_node = i2s_np;\n+\t\t}\n+\t}\n+\n+\tret = devm_snd_soc_register_card(&pdev->dev, &snd_rpi_dionaudio_loco);\n+\tif (ret && ret != -EPROBE_DEFER)\n+\t\tdev_err(&pdev->dev, \"snd_soc_register_card() failed: %d\\n\",\n+\t\t\tret);\n+\n+\treturn ret;\n+}\n+\n+static const struct of_device_id snd_rpi_dionaudio_loco_of_match[] = {\n+\t{ .compatible = \"dionaudio,loco-pcm5242-tpa3118\", },\n+\t{ /* sentinel */ },\n+};\n+MODULE_DEVICE_TABLE(of, snd_rpi_dionaudio_loco_of_match);\n+\n+static struct platform_driver snd_rpi_dionaudio_loco_driver = {\n+\t.driver = {\n+\t\t.name\t\t= \"snd-dionaudio-loco\",\n+\t\t.owner\t\t= THIS_MODULE,\n+\t\t.of_match_table\t= snd_rpi_dionaudio_loco_of_match,\n+\t},\n+\t.probe  = snd_rpi_dionaudio_loco_probe,\n+};\n+\n+module_platform_driver(snd_rpi_dionaudio_loco_driver);\n+\n+MODULE_AUTHOR(\"Miquel Blauw <info@dionaudio.nl>\");\n+MODULE_DESCRIPTION(\"ASoC Driver for DionAudio LOCO\");\n+MODULE_LICENSE(\"GPL v2\");\n--- /dev/null\n+++ b/sound/soc/bcm/fe-pi-audio.c\n@@ -0,0 +1,154 @@\n+/*\n+ * ASoC Driver for Fe-Pi Audio Sound Card\n+ *\n+ * Author:\tHenry Kupis <kuupaz@gmail.com>\n+ *\t\tCopyright 2016\n+ *\t\tbased on code by Florian Meier <florian.meier@koalo.de>\n+ *\t\tbased on code by Shawn Guo <shawn.guo@linaro.org>\n+ *\n+ * This program is free software; you can redistribute it and/or\n+ * modify it under the terms of the GNU General Public License\n+ * version 2 as published by the Free Software Foundation.\n+ *\n+ * This program is distributed in the hope that it will be useful, but\n+ * WITHOUT ANY WARRANTY; without even the implied warranty of\n+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\n+ * General Public License for more details.\n+ */\n+\n+#include <linux/module.h>\n+#include <linux/platform_device.h>\n+#include <linux/io.h>\n+\n+#include <sound/core.h>\n+#include <sound/pcm.h>\n+#include <sound/pcm_params.h>\n+#include <sound/soc.h>\n+#include <sound/jack.h>\n+\n+#include \"../codecs/sgtl5000.h\"\n+\n+static int snd_fe_pi_audio_init(struct snd_soc_pcm_runtime *rtd)\n+{\n+\tstruct snd_soc_card *card = rtd->card;\n+\tstruct snd_soc_component *component = asoc_rtd_to_codec(rtd, 0)->component;\n+\n+\tsnd_soc_dapm_force_enable_pin(&card->dapm, \"LO\");\n+\tsnd_soc_dapm_force_enable_pin(&card->dapm, \"ADC\");\n+\tsnd_soc_dapm_force_enable_pin(&card->dapm, \"DAC\");\n+\tsnd_soc_dapm_force_enable_pin(&card->dapm, \"HP\");\n+\tsnd_soc_component_update_bits(component, SGTL5000_CHIP_ANA_POWER,\n+\t\t\tSGTL5000_VAG_POWERUP, SGTL5000_VAG_POWERUP);\n+\n+\treturn 0;\n+}\n+\n+static int snd_fe_pi_audio_hw_params(struct snd_pcm_substream *substream,\n+\tstruct snd_pcm_hw_params *params)\n+{\n+\tstruct snd_soc_pcm_runtime *rtd = substream->private_data;\n+\tstruct device *dev = rtd->card->dev;\n+\tstruct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);\n+\n+\tint ret;\n+\n+\t/* Set SGTL5000's SYSCLK */\n+\tret = snd_soc_dai_set_sysclk(codec_dai, SGTL5000_SYSCLK, 12288000, SND_SOC_CLOCK_IN);\n+\tif (ret) {\n+\t\tdev_err(dev, \"could not set codec driver clock params\\n\");\n+\t\treturn ret;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+\n+static struct snd_soc_ops snd_fe_pi_audio_ops = {\n+\t.hw_params = snd_fe_pi_audio_hw_params,\n+};\n+\n+SND_SOC_DAILINK_DEFS(fe_pi,\n+\tDAILINK_COMP_ARRAY(COMP_CPU(\"bcm2708-i2s.0\")),\n+\tDAILINK_COMP_ARRAY(COMP_CODEC(\"sgtl5000.1-000a\", \"sgtl5000\")),\n+\tDAILINK_COMP_ARRAY(COMP_PLATFORM(\"bcm2708-i2s.0\")));\n+\n+static struct snd_soc_dai_link snd_fe_pi_audio_dai[] = {\n+\t{\n+\t\t.name\t\t= \"FE-PI\",\n+\t\t.stream_name\t= \"Fe-Pi HiFi\",\n+\t\t.dai_fmt\t= SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |\n+\t\t\t\t\tSND_SOC_DAIFMT_CBM_CFM,\n+\t\t.ops\t\t= &snd_fe_pi_audio_ops,\n+\t\t.init\t\t= snd_fe_pi_audio_init,\n+\t\tSND_SOC_DAILINK_REG(fe_pi),\n+\t},\n+};\n+\n+static const struct snd_soc_dapm_route fe_pi_audio_dapm_routes[] = {\n+\t{\"ADC\", NULL, \"Mic Bias\"},\n+};\n+\n+\n+static struct snd_soc_card fe_pi_audio = {\n+\t.name         = \"Fe-Pi Audio\",\n+\t.owner        = THIS_MODULE,\n+\t.dai_link     = snd_fe_pi_audio_dai,\n+\t.num_links    = ARRAY_SIZE(snd_fe_pi_audio_dai),\n+\n+\t.dapm_routes = fe_pi_audio_dapm_routes,\n+\t.num_dapm_routes = ARRAY_SIZE(fe_pi_audio_dapm_routes),\n+};\n+\n+static int snd_fe_pi_audio_probe(struct platform_device *pdev)\n+{\n+\tint ret = 0;\n+\tstruct snd_soc_card *card = &fe_pi_audio;\n+\tstruct device_node *np = pdev->dev.of_node;\n+\tstruct device_node *i2s_node;\n+\tstruct snd_soc_dai_link *dai = &snd_fe_pi_audio_dai[0];\n+\n+\tfe_pi_audio.dev = &pdev->dev;\n+\n+\ti2s_node = of_parse_phandle(np, \"i2s-controller\", 0);\n+\tif (!i2s_node) {\n+\t\tdev_err(&pdev->dev, \"i2s_node phandle missing or invalid\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tdai->cpus->dai_name = NULL;\n+\tdai->cpus->of_node = i2s_node;\n+\tdai->platforms->name = NULL;\n+\tdai->platforms->of_node = i2s_node;\n+\n+\tof_node_put(i2s_node);\n+\n+\tcard->dev = &pdev->dev;\n+\tplatform_set_drvdata(pdev, card);\n+\n+\tret = devm_snd_soc_register_card(&pdev->dev, card);\n+\tif (ret && ret != -EPROBE_DEFER)\n+\t\tdev_err(&pdev->dev, \"snd_soc_register_card() failed: %d\\n\", ret);\n+\n+\treturn ret;\n+}\n+\n+static const struct of_device_id snd_fe_pi_audio_of_match[] = {\n+\t{ .compatible = \"fe-pi,fe-pi-audio\", },\n+\t{},\n+};\n+MODULE_DEVICE_TABLE(of, snd_fe_pi_audio_of_match);\n+\n+static struct platform_driver snd_fe_pi_audio_driver = {\n+        .driver = {\n+                .name   = \"snd-fe-pi-audio\",\n+                .owner  = THIS_MODULE,\n+                .of_match_table = snd_fe_pi_audio_of_match,\n+        },\n+        .probe          = snd_fe_pi_audio_probe,\n+};\n+\n+module_platform_driver(snd_fe_pi_audio_driver);\n+\n+MODULE_AUTHOR(\"Henry Kupis <fe-pi@cox.net>\");\n+MODULE_DESCRIPTION(\"ASoC Driver for Fe-Pi Audio\");\n+MODULE_LICENSE(\"GPL v2\");\n--- /dev/null\n+++ b/sound/soc/bcm/googlevoicehat-codec.c\n@@ -0,0 +1,214 @@\n+/*\n+ * Driver for the Google voiceHAT audio codec for Raspberry Pi.\n+ *\n+ * Author:\tPeter Malkin <petermalkin@google.com>\n+ *\t\tCopyright 2016\n+ *\n+ * This program is free software; you can redistribute it and/or\n+ * modify it under the terms of the GNU General Public License\n+ * version 2 as published by the Free Software Foundation.\n+ *\n+ * This program is distributed in the hope that it will be useful, but\n+ * WITHOUT ANY WARRANTY; without even the implied warranty of\n+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\n+ * General Public License for more details.\n+ */\n+\n+#include <linux/device.h>\n+#include <linux/err.h>\n+#include <linux/gpio.h>\n+#include <linux/gpio/consumer.h>\n+#include <linux/init.h>\n+#include <linux/kernel.h>\n+#include <linux/mod_devicetable.h>\n+#include <linux/module.h>\n+#include <linux/of.h>\n+#include <linux/platform_device.h>\n+#include <linux/version.h>\n+#include <sound/pcm.h>\n+#include <sound/soc.h>\n+#include <sound/soc-dai.h>\n+#include <sound/soc-dapm.h>\n+\n+#define ICS43432_RATE_MIN_HZ\t7190  /* from data sheet */\n+#define ICS43432_RATE_MAX_HZ\t52800 /* from data sheet */\n+/* Delay in enabling SDMODE after clock settles to remove pop */\n+#define SDMODE_DELAY_MS\t\t5\n+\n+struct voicehat_priv {\n+\tstruct delayed_work enable_sdmode_work;\n+\tstruct gpio_desc *sdmode_gpio;\n+\tunsigned long sdmode_delay_jiffies;\n+};\n+\n+static void voicehat_enable_sdmode_work(struct work_struct *work)\n+{\n+\tstruct voicehat_priv *voicehat = container_of(work,\n+\t\t\t\t\t\t      struct voicehat_priv,\n+\t\t\t\t\t\t      enable_sdmode_work.work);\n+\tgpiod_set_value(voicehat->sdmode_gpio, 1);\n+}\n+\n+static int voicehat_component_probe(struct snd_soc_component *component)\n+{\n+\tstruct voicehat_priv *voicehat =\n+\t\t\t\tsnd_soc_component_get_drvdata(component);\n+\n+\tvoicehat->sdmode_gpio = devm_gpiod_get(component->dev, \"sdmode\",\n+\t\t\t\t\t       GPIOD_OUT_LOW);\n+\tif (IS_ERR(voicehat->sdmode_gpio)) {\n+\t\tdev_err(component->dev, \"Unable to allocate GPIO pin\\n\");\n+\t\treturn PTR_ERR(voicehat->sdmode_gpio);\n+\t}\n+\n+\tINIT_DELAYED_WORK(&voicehat->enable_sdmode_work,\n+\t\t\t  voicehat_enable_sdmode_work);\n+\treturn 0;\n+}\n+\n+static void voicehat_component_remove(struct snd_soc_component *component)\n+{\n+\tstruct voicehat_priv *voicehat =\n+\t\t\t\tsnd_soc_component_get_drvdata(component);\n+\n+\tcancel_delayed_work_sync(&voicehat->enable_sdmode_work);\n+}\n+\n+static const struct snd_soc_dapm_widget voicehat_dapm_widgets[] = {\n+\tSND_SOC_DAPM_OUTPUT(\"Speaker\"),\n+};\n+\n+static const struct snd_soc_dapm_route voicehat_dapm_routes[] = {\n+\t{\"Speaker\", NULL, \"HiFi Playback\"},\n+};\n+\n+static const struct snd_soc_component_driver voicehat_component_driver = {\n+\t.probe = voicehat_component_probe,\n+\t.remove = voicehat_component_remove,\n+\t.dapm_widgets = voicehat_dapm_widgets,\n+\t.num_dapm_widgets = ARRAY_SIZE(voicehat_dapm_widgets),\n+\t.dapm_routes = voicehat_dapm_routes,\n+\t.num_dapm_routes = ARRAY_SIZE(voicehat_dapm_routes),\n+};\n+\n+static int voicehat_daiops_trigger(struct snd_pcm_substream *substream, int cmd,\n+\t\t\t\t   struct snd_soc_dai *dai)\n+{\n+\tstruct snd_soc_component *component = dai->component;\n+\tstruct voicehat_priv *voicehat =\n+\t\t\t\tsnd_soc_component_get_drvdata(component);\n+\n+\tif (voicehat->sdmode_delay_jiffies == 0)\n+\t\treturn 0;\n+\n+\tdev_dbg(dai->dev, \"CMD             %d\", cmd);\n+\tdev_dbg(dai->dev, \"Playback Active %d\", dai->stream_active[SNDRV_PCM_STREAM_PLAYBACK]);\n+\tdev_dbg(dai->dev, \"Capture Active  %d\", dai->stream_active[SNDRV_PCM_STREAM_CAPTURE]);\n+\n+\tswitch (cmd) {\n+\tcase SNDRV_PCM_TRIGGER_START:\n+\tcase SNDRV_PCM_TRIGGER_RESUME:\n+\tcase SNDRV_PCM_TRIGGER_PAUSE_RELEASE:\n+\t\tif (dai->stream_active[SNDRV_PCM_STREAM_PLAYBACK]) {\n+\t\t\tdev_info(dai->dev, \"Enabling audio amp...\\n\");\n+\t\t\tqueue_delayed_work(\n+\t\t\t\tsystem_power_efficient_wq,\n+\t\t\t\t&voicehat->enable_sdmode_work,\n+\t\t\t\tvoicehat->sdmode_delay_jiffies);\n+\t\t}\n+\t\tbreak;\n+\tcase SNDRV_PCM_TRIGGER_STOP:\n+\tcase SNDRV_PCM_TRIGGER_SUSPEND:\n+\tcase SNDRV_PCM_TRIGGER_PAUSE_PUSH:\n+\t\tif (dai->stream_active[SNDRV_PCM_STREAM_PLAYBACK]) {\n+\t\t\tcancel_delayed_work(&voicehat->enable_sdmode_work);\n+\t\t\tdev_info(dai->dev, \"Disabling audio amp...\\n\");\n+\t\t\tgpiod_set_value(voicehat->sdmode_gpio, 0);\n+\t\t}\n+\t\tbreak;\n+\t}\n+\treturn 0;\n+}\n+\n+static const struct snd_soc_dai_ops voicehat_dai_ops = {\n+\t.trigger = voicehat_daiops_trigger,\n+};\n+\n+static struct snd_soc_dai_driver voicehat_dai = {\n+\t.name = \"voicehat-hifi\",\n+\t.capture = {\n+\t\t.stream_name = \"HiFi Capture\",\n+\t\t.channels_min = 2,\n+\t\t.channels_max = 2,\n+\t\t.rates = SNDRV_PCM_RATE_48000,\n+\t\t.formats = SNDRV_PCM_FMTBIT_S32_LE\n+\t},\n+\t.playback = {\n+\t\t.stream_name = \"HiFi Playback\",\n+\t\t.channels_min = 2,\n+\t\t.channels_max = 2,\n+\t\t.rates = SNDRV_PCM_RATE_48000,\n+\t\t.formats = SNDRV_PCM_FMTBIT_S32_LE\n+\t},\n+\t.ops = &voicehat_dai_ops,\n+\t.symmetric_rates = 1\n+};\n+\n+#ifdef CONFIG_OF\n+static const struct of_device_id voicehat_ids[] = {\n+\t\t{ .compatible = \"google,voicehat\", }, {}\n+\t};\n+\tMODULE_DEVICE_TABLE(of, voicehat_ids);\n+#endif\n+\n+static int voicehat_platform_probe(struct platform_device *pdev)\n+{\n+\tstruct voicehat_priv *voicehat;\n+\tunsigned int sdmode_delay;\n+\tint ret;\n+\n+\tvoicehat = devm_kzalloc(&pdev->dev, sizeof(*voicehat), GFP_KERNEL);\n+\tif (!voicehat)\n+\t\treturn -ENOMEM;\n+\n+\tret = device_property_read_u32(&pdev->dev, \"voicehat_sdmode_delay\",\n+\t\t\t\t       &sdmode_delay);\n+\n+\tif (ret) {\n+\t\tsdmode_delay = SDMODE_DELAY_MS;\n+\t\tdev_info(&pdev->dev,\n+\t\t\t \"property 'voicehat_sdmode_delay' not found default 5 mS\");\n+\t} else {\n+\t\tdev_info(&pdev->dev, \"property 'voicehat_sdmode_delay' found delay= %d mS\",\n+\t\t\t sdmode_delay);\n+\t}\n+\tvoicehat->sdmode_delay_jiffies = msecs_to_jiffies(sdmode_delay);\n+\n+\tdev_set_drvdata(&pdev->dev, voicehat);\n+\n+\treturn snd_soc_register_component(&pdev->dev,\n+\t\t\t\t\t  &voicehat_component_driver,\n+\t\t\t\t\t  &voicehat_dai,\n+\t\t\t\t\t  1);\n+}\n+\n+static int voicehat_platform_remove(struct platform_device *pdev)\n+{\n+\tsnd_soc_unregister_component(&pdev->dev);\n+\treturn 0;\n+}\n+\n+static struct platform_driver voicehat_driver = {\n+\t.driver = {\n+\t\t.name = \"voicehat-codec\",\n+\t\t.of_match_table = of_match_ptr(voicehat_ids),\n+\t},\n+\t.probe = voicehat_platform_probe,\n+\t.remove = voicehat_platform_remove,\n+};\n+\n+module_platform_driver(voicehat_driver);\n+\n+MODULE_DESCRIPTION(\"Google voiceHAT Codec driver\");\n+MODULE_AUTHOR(\"Peter Malkin <petermalkin@google.com>\");\n+MODULE_LICENSE(\"GPL v2\");\n--- /dev/null\n+++ b/sound/soc/bcm/hifiberry_dacplus.c\n@@ -0,0 +1,424 @@\n+/*\n+ * ASoC Driver for HiFiBerry DAC+ / DAC Pro\n+ *\n+ * Author:\tDaniel Matuschek, Stuart MacLean <stuart@hifiberry.com>\n+ *\t\tCopyright 2014-2015\n+ *\t\tbased on code by Florian Meier <florian.meier@koalo.de>\n+ *\t\tHeadphone added by Joerg Schambacher, joerg@i2audio.com\n+ *\n+ * This program is free software; you can redistribute it and/or\n+ * modify it under the terms of the GNU General Public License\n+ * version 2 as published by the Free Software Foundation.\n+ *\n+ * This program is distributed in the hope that it will be useful, but\n+ * WITHOUT ANY WARRANTY; without even the implied warranty of\n+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\n+ * General Public License for more details.\n+ */\n+\n+#include <linux/module.h>\n+#include <linux/platform_device.h>\n+#include <linux/kernel.h>\n+#include <linux/clk.h>\n+#include <linux/kernel.h>\n+#include <linux/module.h>\n+#include <linux/of.h>\n+#include <linux/slab.h>\n+#include <linux/delay.h>\n+#include <linux/i2c.h>\n+\n+#include <sound/core.h>\n+#include <sound/pcm.h>\n+#include <sound/pcm_params.h>\n+#include <sound/soc.h>\n+#include <sound/jack.h>\n+\n+#include \"../codecs/pcm512x.h\"\n+\n+#define HIFIBERRY_DACPRO_NOCLOCK 0\n+#define HIFIBERRY_DACPRO_CLK44EN 1\n+#define HIFIBERRY_DACPRO_CLK48EN 2\n+\n+struct pcm512x_priv {\n+\tstruct regmap *regmap;\n+\tstruct clk *sclk;\n+};\n+\n+/* Clock rate of CLK44EN attached to GPIO6 pin */\n+#define CLK_44EN_RATE 22579200UL\n+/* Clock rate of CLK48EN attached to GPIO3 pin */\n+#define CLK_48EN_RATE 24576000UL\n+\n+static bool slave;\n+static bool snd_rpi_hifiberry_is_dacpro;\n+static bool digital_gain_0db_limit = true;\n+static bool leds_off;\n+\n+static void snd_rpi_hifiberry_dacplus_select_clk(struct snd_soc_component *component,\n+\tint clk_id)\n+{\n+\tswitch (clk_id) {\n+\tcase HIFIBERRY_DACPRO_NOCLOCK:\n+\t\tsnd_soc_component_update_bits(component, PCM512x_GPIO_CONTROL_1, 0x24, 0x00);\n+\t\tbreak;\n+\tcase HIFIBERRY_DACPRO_CLK44EN:\n+\t\tsnd_soc_component_update_bits(component, PCM512x_GPIO_CONTROL_1, 0x24, 0x20);\n+\t\tbreak;\n+\tcase HIFIBERRY_DACPRO_CLK48EN:\n+\t\tsnd_soc_component_update_bits(component, PCM512x_GPIO_CONTROL_1, 0x24, 0x04);\n+\t\tbreak;\n+\t}\n+}\n+\n+static void snd_rpi_hifiberry_dacplus_clk_gpio(struct snd_soc_component *component)\n+{\n+\tsnd_soc_component_update_bits(component, PCM512x_GPIO_EN, 0x24, 0x24);\n+\tsnd_soc_component_update_bits(component, PCM512x_GPIO_OUTPUT_3, 0x0f, 0x02);\n+\tsnd_soc_component_update_bits(component, PCM512x_GPIO_OUTPUT_6, 0x0f, 0x02);\n+}\n+\n+static bool snd_rpi_hifiberry_dacplus_is_sclk(struct snd_soc_component *component)\n+{\n+\tunsigned int sck;\n+\n+\tsck = snd_soc_component_read(component, PCM512x_RATE_DET_4);\n+\treturn (!(sck & 0x40));\n+}\n+\n+static bool snd_rpi_hifiberry_dacplus_is_sclk_sleep(\n+\tstruct snd_soc_component *component)\n+{\n+\tmsleep(2);\n+\treturn snd_rpi_hifiberry_dacplus_is_sclk(component);\n+}\n+\n+static bool snd_rpi_hifiberry_dacplus_is_pro_card(struct snd_soc_component *component)\n+{\n+\tbool isClk44EN, isClk48En, isNoClk;\n+\n+\tsnd_rpi_hifiberry_dacplus_clk_gpio(component);\n+\n+\tsnd_rpi_hifiberry_dacplus_select_clk(component, HIFIBERRY_DACPRO_CLK44EN);\n+\tisClk44EN = snd_rpi_hifiberry_dacplus_is_sclk_sleep(component);\n+\n+\tsnd_rpi_hifiberry_dacplus_select_clk(component, HIFIBERRY_DACPRO_NOCLOCK);\n+\tisNoClk = snd_rpi_hifiberry_dacplus_is_sclk_sleep(component);\n+\n+\tsnd_rpi_hifiberry_dacplus_select_clk(component, HIFIBERRY_DACPRO_CLK48EN);\n+\tisClk48En = snd_rpi_hifiberry_dacplus_is_sclk_sleep(component);\n+\n+\treturn (isClk44EN && isClk48En && !isNoClk);\n+}\n+\n+static int snd_rpi_hifiberry_dacplus_clk_for_rate(int sample_rate)\n+{\n+\tint type;\n+\n+\tswitch (sample_rate) {\n+\tcase 11025:\n+\tcase 22050:\n+\tcase 44100:\n+\tcase 88200:\n+\tcase 176400:\n+\tcase 352800:\n+\t\ttype = HIFIBERRY_DACPRO_CLK44EN;\n+\t\tbreak;\n+\tdefault:\n+\t\ttype = HIFIBERRY_DACPRO_CLK48EN;\n+\t\tbreak;\n+\t}\n+\treturn type;\n+}\n+\n+static void snd_rpi_hifiberry_dacplus_set_sclk(struct snd_soc_component *component,\n+\tint sample_rate)\n+{\n+\tstruct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);\n+\n+\tif (!IS_ERR(pcm512x->sclk)) {\n+\t\tint ctype;\n+\n+\t\tctype = snd_rpi_hifiberry_dacplus_clk_for_rate(sample_rate);\n+\t\tclk_set_rate(pcm512x->sclk, (ctype == HIFIBERRY_DACPRO_CLK44EN)\n+\t\t\t? CLK_44EN_RATE : CLK_48EN_RATE);\n+\t\tsnd_rpi_hifiberry_dacplus_select_clk(component, ctype);\n+\t}\n+}\n+\n+static int snd_rpi_hifiberry_dacplus_init(struct snd_soc_pcm_runtime *rtd)\n+{\n+\tstruct snd_soc_component *component = asoc_rtd_to_codec(rtd, 0)->component;\n+\tstruct pcm512x_priv *priv;\n+\n+\tif (slave)\n+\t\tsnd_rpi_hifiberry_is_dacpro = false;\n+\telse\n+\t\tsnd_rpi_hifiberry_is_dacpro =\n+\t\t\t\tsnd_rpi_hifiberry_dacplus_is_pro_card(component);\n+\n+\tif (snd_rpi_hifiberry_is_dacpro) {\n+\t\tstruct snd_soc_dai_link *dai = rtd->dai_link;\n+\n+\t\tdai->name = \"HiFiBerry DAC+ Pro\";\n+\t\tdai->stream_name = \"HiFiBerry DAC+ Pro HiFi\";\n+\t\tdai->dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF\n+\t\t\t| SND_SOC_DAIFMT_CBM_CFM;\n+\n+\t\tsnd_soc_component_update_bits(component, PCM512x_BCLK_LRCLK_CFG, 0x31, 0x11);\n+\t\tsnd_soc_component_update_bits(component, PCM512x_MASTER_MODE, 0x03, 0x03);\n+\t\tsnd_soc_component_update_bits(component, PCM512x_MASTER_CLKDIV_2, 0x7f, 63);\n+\t} else {\n+\t\tpriv = snd_soc_component_get_drvdata(component);\n+\t\tpriv->sclk = ERR_PTR(-ENOENT);\n+\t}\n+\n+\tsnd_soc_component_update_bits(component, PCM512x_GPIO_EN, 0x08, 0x08);\n+\tsnd_soc_component_update_bits(component, PCM512x_GPIO_OUTPUT_4, 0x0f, 0x02);\n+\tif (leds_off)\n+\t\tsnd_soc_component_update_bits(component, PCM512x_GPIO_CONTROL_1, 0x08, 0x00);\n+\telse\n+\t\tsnd_soc_component_update_bits(component, PCM512x_GPIO_CONTROL_1, 0x08, 0x08);\n+\n+\tif (digital_gain_0db_limit) {\n+\t\tint ret;\n+\t\tstruct snd_soc_card *card = rtd->card;\n+\n+\t\tret = snd_soc_limit_volume(card, \"Digital Playback Volume\", 207);\n+\t\tif (ret < 0)\n+\t\t\tdev_warn(card->dev, \"Failed to set volume limit: %d\\n\", ret);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int snd_rpi_hifiberry_dacplus_update_rate_den(\n+\tstruct snd_pcm_substream *substream, struct snd_pcm_hw_params *params)\n+{\n+\tstruct snd_soc_pcm_runtime *rtd = substream->private_data;\n+\tstruct snd_soc_component *component = asoc_rtd_to_codec(rtd, 0)->component;\n+\tstruct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);\n+\tstruct snd_ratnum *rats_no_pll;\n+\tunsigned int num = 0, den = 0;\n+\tint err;\n+\n+\trats_no_pll = devm_kzalloc(rtd->dev, sizeof(*rats_no_pll), GFP_KERNEL);\n+\tif (!rats_no_pll)\n+\t\treturn -ENOMEM;\n+\n+\trats_no_pll->num = clk_get_rate(pcm512x->sclk) / 64;\n+\trats_no_pll->den_min = 1;\n+\trats_no_pll->den_max = 128;\n+\trats_no_pll->den_step = 1;\n+\n+\terr = snd_interval_ratnum(hw_param_interval(params,\n+\t\tSNDRV_PCM_HW_PARAM_RATE), 1, rats_no_pll, &num, &den);\n+\tif (err >= 0 && den) {\n+\t\tparams->rate_num = num;\n+\t\tparams->rate_den = den;\n+\t}\n+\n+\tdevm_kfree(rtd->dev, rats_no_pll);\n+\treturn 0;\n+}\n+\n+static int snd_rpi_hifiberry_dacplus_hw_params(\n+\tstruct snd_pcm_substream *substream, struct snd_pcm_hw_params *params)\n+{\n+\tint ret = 0;\n+\tstruct snd_soc_pcm_runtime *rtd = substream->private_data;\n+\tint channels = params_channels(params);\n+\tint width = 32;\n+\n+\tif (snd_rpi_hifiberry_is_dacpro) {\n+\t\tstruct snd_soc_component *component = asoc_rtd_to_codec(rtd, 0)->component;\n+\n+\t\twidth = snd_pcm_format_physical_width(params_format(params));\n+\n+\t\tsnd_rpi_hifiberry_dacplus_set_sclk(component,\n+\t\t\tparams_rate(params));\n+\n+\t\tret = snd_rpi_hifiberry_dacplus_update_rate_den(\n+\t\t\tsubstream, params);\n+\t}\n+\n+\tret = snd_soc_dai_set_bclk_ratio(asoc_rtd_to_cpu(rtd, 0), channels * width);\n+\tif (ret)\n+\t\treturn ret;\n+\tret = snd_soc_dai_set_bclk_ratio(asoc_rtd_to_codec(rtd, 0), channels * width);\n+\treturn ret;\n+}\n+\n+static int snd_rpi_hifiberry_dacplus_startup(\n+\tstruct snd_pcm_substream *substream)\n+{\n+\tstruct snd_soc_pcm_runtime *rtd = substream->private_data;\n+\tstruct snd_soc_component *component = asoc_rtd_to_codec(rtd, 0)->component;\n+\n+\tif (leds_off)\n+\t\treturn 0;\n+\tsnd_soc_component_update_bits(component, PCM512x_GPIO_CONTROL_1, 0x08, 0x08);\n+\treturn 0;\n+}\n+\n+static void snd_rpi_hifiberry_dacplus_shutdown(\n+\tstruct snd_pcm_substream *substream)\n+{\n+\tstruct snd_soc_pcm_runtime *rtd = substream->private_data;\n+\tstruct snd_soc_component *component = asoc_rtd_to_codec(rtd, 0)->component;\n+\n+\tsnd_soc_component_update_bits(component, PCM512x_GPIO_CONTROL_1, 0x08, 0x00);\n+}\n+\n+/* machine stream operations */\n+static struct snd_soc_ops snd_rpi_hifiberry_dacplus_ops = {\n+\t.hw_params = snd_rpi_hifiberry_dacplus_hw_params,\n+\t.startup = snd_rpi_hifiberry_dacplus_startup,\n+\t.shutdown = snd_rpi_hifiberry_dacplus_shutdown,\n+};\n+\n+SND_SOC_DAILINK_DEFS(rpi_hifiberry_dacplus,\n+\tDAILINK_COMP_ARRAY(COMP_CPU(\"bcm2708-i2s.0\")),\n+\tDAILINK_COMP_ARRAY(COMP_CODEC(\"pcm512x.1-004d\", \"pcm512x-hifi\")),\n+\tDAILINK_COMP_ARRAY(COMP_PLATFORM(\"bcm2708-i2s.0\")));\n+\n+static struct snd_soc_dai_link snd_rpi_hifiberry_dacplus_dai[] = {\n+{\n+\t.name\t\t= \"HiFiBerry DAC+\",\n+\t.stream_name\t= \"HiFiBerry DAC+ HiFi\",\n+\t.dai_fmt\t= SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |\n+\t\t\t\tSND_SOC_DAIFMT_CBS_CFS,\n+\t.ops\t\t= &snd_rpi_hifiberry_dacplus_ops,\n+\t.init\t\t= snd_rpi_hifiberry_dacplus_init,\n+\tSND_SOC_DAILINK_REG(rpi_hifiberry_dacplus),\n+},\n+};\n+\n+/* aux device for optional headphone amp */\n+static struct snd_soc_aux_dev hifiberry_dacplus_aux_devs[] = {\n+\t{\n+\t\t.dlc = {\n+\t\t\t.name = \"tpa6130a2.1-0060\",\n+\t\t},\n+\t},\n+};\n+\n+/* audio machine driver */\n+static struct snd_soc_card snd_rpi_hifiberry_dacplus = {\n+\t.name         = \"snd_rpi_hifiberry_dacplus\",\n+\t.driver_name  = \"HifiberryDacp\",\n+\t.owner        = THIS_MODULE,\n+\t.dai_link     = snd_rpi_hifiberry_dacplus_dai,\n+\t.num_links    = ARRAY_SIZE(snd_rpi_hifiberry_dacplus_dai),\n+};\n+\n+static int hb_hp_detect(void)\n+{\n+\tstruct i2c_adapter *adap = i2c_get_adapter(1);\n+\tint ret;\n+\n+\tstruct i2c_client tpa_i2c_client = {\n+\t\t.addr = 0x60,\n+\t\t.adapter = adap,\n+\t};\n+\n+\tret = i2c_smbus_read_byte(&tpa_i2c_client) >= 0;\n+\ti2c_put_adapter(adap);\n+\treturn ret;\n+};\n+\n+static struct property tpa_enable_prop = {\n+\t       .name = \"status\",\n+\t       .length = 4 + 1, /* length 'okay' + 1 */\n+\t       .value = \"okay\",\n+\t};\n+\n+static int snd_rpi_hifiberry_dacplus_probe(struct platform_device *pdev)\n+{\n+\tint ret = 0;\n+\tstruct snd_soc_card *card = &snd_rpi_hifiberry_dacplus;\n+\tint len;\n+\tstruct device_node *tpa_node;\n+\tstruct property *tpa_prop;\n+\tstruct of_changeset ocs;\n+\n+\t/* probe for head phone amp */\n+\tif (hb_hp_detect()) {\n+\t\tcard->aux_dev = hifiberry_dacplus_aux_devs;\n+\t\tcard->num_aux_devs =\n+\t\t\t\tARRAY_SIZE(hifiberry_dacplus_aux_devs);\n+\t\ttpa_node = of_find_compatible_node(NULL, NULL, \"ti,tpa6130a2\");\n+\t\ttpa_prop = of_find_property(tpa_node, \"status\", &len);\n+\n+\t\tif (strcmp((char *)tpa_prop->value, \"okay\")) {\n+\t\t\t/* and activate headphone using change_sets */\n+\t\t\tdev_info(&pdev->dev, \"activating headphone amplifier\");\n+\t\t\tof_changeset_init(&ocs);\n+\t\t\tret = of_changeset_update_property(&ocs, tpa_node,\n+\t\t\t\t\t\t\t&tpa_enable_prop);\n+\t\t\tif (ret) {\n+\t\t\t\tdev_err(&pdev->dev,\n+\t\t\t\t\"cannot activate headphone amplifier\\n\");\n+\t\t\t\treturn -ENODEV;\n+\t\t\t}\n+\t\t\tret = of_changeset_apply(&ocs);\n+\t\t\tif (ret) {\n+\t\t\t\tdev_err(&pdev->dev,\n+\t\t\t\t\"cannot activate headphone amplifier\\n\");\n+\t\t\t\treturn -ENODEV;\n+\t\t\t}\n+\t\t}\n+\t}\n+\n+\tsnd_rpi_hifiberry_dacplus.dev = &pdev->dev;\n+\tif (pdev->dev.of_node) {\n+\t\tstruct device_node *i2s_node;\n+\t\tstruct snd_soc_dai_link *dai;\n+\n+\t\tdai = &snd_rpi_hifiberry_dacplus_dai[0];\n+\t\ti2s_node = of_parse_phandle(pdev->dev.of_node,\n+\t\t\t\"i2s-controller\", 0);\n+\n+\t\tif (i2s_node) {\n+\t\t\tdai->cpus->dai_name = NULL;\n+\t\t\tdai->cpus->of_node = i2s_node;\n+\t\t\tdai->platforms->name = NULL;\n+\t\t\tdai->platforms->of_node = i2s_node;\n+\t\t}\n+\n+\t\tdigital_gain_0db_limit = !of_property_read_bool(\n+\t\t\tpdev->dev.of_node, \"hifiberry,24db_digital_gain\");\n+\t\tslave = of_property_read_bool(pdev->dev.of_node,\n+\t\t\t\t\t\t\"hifiberry-dacplus,slave\");\n+\t\tleds_off = of_property_read_bool(pdev->dev.of_node,\n+\t\t\t\t\t\t\"hifiberry-dacplus,leds_off\");\n+\t}\n+\n+\tret = devm_snd_soc_register_card(&pdev->dev,\n+\t\t\t&snd_rpi_hifiberry_dacplus);\n+\tif (ret && ret != -EPROBE_DEFER)\n+\t\tdev_err(&pdev->dev,\n+\t\t\t\"snd_soc_register_card() failed: %d\\n\", ret);\n+\n+\treturn ret;\n+}\n+\n+static const struct of_device_id snd_rpi_hifiberry_dacplus_of_match[] = {\n+\t{ .compatible = \"hifiberry,hifiberry-dacplus\", },\n+\t{},\n+};\n+MODULE_DEVICE_TABLE(of, snd_rpi_hifiberry_dacplus_of_match);\n+\n+static struct platform_driver snd_rpi_hifiberry_dacplus_driver = {\n+\t.driver = {\n+\t\t.name   = \"snd-rpi-hifiberry-dacplus\",\n+\t\t.owner  = THIS_MODULE,\n+\t\t.of_match_table = snd_rpi_hifiberry_dacplus_of_match,\n+\t},\n+\t.probe          = snd_rpi_hifiberry_dacplus_probe,\n+};\n+\n+module_platform_driver(snd_rpi_hifiberry_dacplus_driver);\n+\n+MODULE_AUTHOR(\"Daniel Matuschek <daniel@hifiberry.com>\");\n+MODULE_DESCRIPTION(\"ASoC Driver for HiFiBerry DAC+\");\n+MODULE_LICENSE(\"GPL v2\");\n--- /dev/null\n+++ b/sound/soc/bcm/hifiberry_dacplusadc.c\n@@ -0,0 +1,398 @@\n+/*\n+ * ASoC Driver for HiFiBerry DAC+ / DAC Pro with ADC\n+ *\n+ * Author:\tDaniel Matuschek, Stuart MacLean <stuart@hifiberry.com>\n+ *\t\tCopyright 2014-2015\n+ *\t\tbased on code by Florian Meier <florian.meier@koalo.de>\n+ *\t\tADC added by Joerg Schambacher <joscha@schambacher.com>\n+ *\t\tCopyright 2018\n+ *\n+ * This program is free software; you can redistribute it and/or\n+ * modify it under the terms of the GNU General Public License\n+ * version 2 as published by the Free Software Foundation.\n+ *\n+ * This program is distributed in the hope that it will be useful, but\n+ * WITHOUT ANY WARRANTY; without even the implied warranty of\n+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\n+ * General Public License for more details.\n+ */\n+\n+#include <linux/module.h>\n+#include <linux/platform_device.h>\n+#include <linux/kernel.h>\n+#include <linux/clk.h>\n+#include <linux/kernel.h>\n+#include <linux/module.h>\n+#include <linux/of.h>\n+#include <linux/slab.h>\n+#include <linux/delay.h>\n+\n+#include <sound/core.h>\n+#include <sound/pcm.h>\n+#include <sound/pcm_params.h>\n+#include <sound/soc.h>\n+#include <sound/jack.h>\n+\n+#include \"../codecs/pcm512x.h\"\n+\n+#define HIFIBERRY_DACPRO_NOCLOCK 0\n+#define HIFIBERRY_DACPRO_CLK44EN 1\n+#define HIFIBERRY_DACPRO_CLK48EN 2\n+\n+struct platform_device *dmic_codec_dev;\n+\n+struct pcm512x_priv {\n+\tstruct regmap *regmap;\n+\tstruct clk *sclk;\n+};\n+\n+/* Clock rate of CLK44EN attached to GPIO6 pin */\n+#define CLK_44EN_RATE 22579200UL\n+/* Clock rate of CLK48EN attached to GPIO3 pin */\n+#define CLK_48EN_RATE 24576000UL\n+\n+static bool slave;\n+static bool snd_rpi_hifiberry_is_dacpro;\n+static bool digital_gain_0db_limit = true;\n+static bool leds_off;\n+\n+static void snd_rpi_hifiberry_dacplusadc_select_clk(struct snd_soc_component *component,\n+\tint clk_id)\n+{\n+\tswitch (clk_id) {\n+\tcase HIFIBERRY_DACPRO_NOCLOCK:\n+\t\tsnd_soc_component_update_bits(component, PCM512x_GPIO_CONTROL_1, 0x24, 0x00);\n+\t\tbreak;\n+\tcase HIFIBERRY_DACPRO_CLK44EN:\n+\t\tsnd_soc_component_update_bits(component, PCM512x_GPIO_CONTROL_1, 0x24, 0x20);\n+\t\tbreak;\n+\tcase HIFIBERRY_DACPRO_CLK48EN:\n+\t\tsnd_soc_component_update_bits(component, PCM512x_GPIO_CONTROL_1, 0x24, 0x04);\n+\t\tbreak;\n+\t}\n+}\n+\n+static void snd_rpi_hifiberry_dacplusadc_clk_gpio(struct snd_soc_component *component)\n+{\n+\tsnd_soc_component_update_bits(component, PCM512x_GPIO_EN, 0x24, 0x24);\n+\tsnd_soc_component_update_bits(component, PCM512x_GPIO_OUTPUT_3, 0x0f, 0x02);\n+\tsnd_soc_component_update_bits(component, PCM512x_GPIO_OUTPUT_6, 0x0f, 0x02);\n+}\n+\n+static bool snd_rpi_hifiberry_dacplusadc_is_sclk(struct snd_soc_component *component)\n+{\n+\tunsigned int sck;\n+\n+\tsck = snd_soc_component_read(component, PCM512x_RATE_DET_4);\n+\treturn (!(sck & 0x40));\n+}\n+\n+static bool snd_rpi_hifiberry_dacplusadc_is_sclk_sleep(\n+\tstruct snd_soc_component *component)\n+{\n+\tmsleep(2);\n+\treturn snd_rpi_hifiberry_dacplusadc_is_sclk(component);\n+}\n+\n+static bool snd_rpi_hifiberry_dacplusadc_is_pro_card(struct snd_soc_component *component)\n+{\n+\tbool isClk44EN, isClk48En, isNoClk;\n+\n+\tsnd_rpi_hifiberry_dacplusadc_clk_gpio(component);\n+\n+\tsnd_rpi_hifiberry_dacplusadc_select_clk(component, HIFIBERRY_DACPRO_CLK44EN);\n+\tisClk44EN = snd_rpi_hifiberry_dacplusadc_is_sclk_sleep(component);\n+\n+\tsnd_rpi_hifiberry_dacplusadc_select_clk(component, HIFIBERRY_DACPRO_NOCLOCK);\n+\tisNoClk = snd_rpi_hifiberry_dacplusadc_is_sclk_sleep(component);\n+\n+\tsnd_rpi_hifiberry_dacplusadc_select_clk(component, HIFIBERRY_DACPRO_CLK48EN);\n+\tisClk48En = snd_rpi_hifiberry_dacplusadc_is_sclk_sleep(component);\n+\n+\treturn (isClk44EN && isClk48En && !isNoClk);\n+}\n+\n+static int snd_rpi_hifiberry_dacplusadc_clk_for_rate(int sample_rate)\n+{\n+\tint type;\n+\n+\tswitch (sample_rate) {\n+\tcase 11025:\n+\tcase 22050:\n+\tcase 44100:\n+\tcase 88200:\n+\tcase 176400:\n+\tcase 352800:\n+\t\ttype = HIFIBERRY_DACPRO_CLK44EN;\n+\t\tbreak;\n+\tdefault:\n+\t\ttype = HIFIBERRY_DACPRO_CLK48EN;\n+\t\tbreak;\n+\t}\n+\treturn type;\n+}\n+\n+static void snd_rpi_hifiberry_dacplusadc_set_sclk(struct snd_soc_component *component,\n+\tint sample_rate)\n+{\n+\tstruct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);\n+\n+\tif (!IS_ERR(pcm512x->sclk)) {\n+\t\tint ctype;\n+\n+\t\tctype = snd_rpi_hifiberry_dacplusadc_clk_for_rate(sample_rate);\n+\t\tclk_set_rate(pcm512x->sclk, (ctype == HIFIBERRY_DACPRO_CLK44EN)\n+\t\t\t? CLK_44EN_RATE : CLK_48EN_RATE);\n+\t\tsnd_rpi_hifiberry_dacplusadc_select_clk(component, ctype);\n+\t}\n+}\n+\n+static int snd_rpi_hifiberry_dacplusadc_init(struct snd_soc_pcm_runtime *rtd)\n+{\n+\tstruct snd_soc_component *component = asoc_rtd_to_codec(rtd, 0)->component;\n+\tstruct pcm512x_priv *priv;\n+\n+\tif (slave)\n+\t\tsnd_rpi_hifiberry_is_dacpro = false;\n+\telse\n+\t\tsnd_rpi_hifiberry_is_dacpro =\n+\t\t\t\tsnd_rpi_hifiberry_dacplusadc_is_pro_card(component);\n+\n+\tif (snd_rpi_hifiberry_is_dacpro) {\n+\t\tstruct snd_soc_dai_link *dai = rtd->dai_link;\n+\n+\t\tdai->name = \"HiFiBerry ADCDAC+ Pro\";\n+\t\tdai->stream_name = \"HiFiBerry ADCDAC+ Pro HiFi\";\n+\t\tdai->dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF\n+\t\t\t| SND_SOC_DAIFMT_CBM_CFM;\n+\n+\t\tsnd_soc_component_update_bits(component, PCM512x_BCLK_LRCLK_CFG, 0x31, 0x11);\n+\t\tsnd_soc_component_update_bits(component, PCM512x_MASTER_MODE, 0x03, 0x03);\n+\t\tsnd_soc_component_update_bits(component, PCM512x_MASTER_CLKDIV_2, 0x7f, 63);\n+\t} else {\n+\t\tpriv = snd_soc_component_get_drvdata(component);\n+\t\tpriv->sclk = ERR_PTR(-ENOENT);\n+\t}\n+\n+\tsnd_soc_component_update_bits(component, PCM512x_GPIO_EN, 0x08, 0x08);\n+\tsnd_soc_component_update_bits(component, PCM512x_GPIO_OUTPUT_4, 0x0f, 0x02);\n+\tif (leds_off)\n+\t\tsnd_soc_component_update_bits(component, PCM512x_GPIO_CONTROL_1, 0x08, 0x00);\n+\telse\n+\t\tsnd_soc_component_update_bits(component, PCM512x_GPIO_CONTROL_1, 0x08, 0x08);\n+\n+\tif (digital_gain_0db_limit) {\n+\t\tint ret;\n+\t\tstruct snd_soc_card *card = rtd->card;\n+\n+\t\tret = snd_soc_limit_volume(card, \"Digital Playback Volume\", 207);\n+\t\tif (ret < 0)\n+\t\t\tdev_warn(card->dev, \"Failed to set volume limit: %d\\n\", ret);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int snd_rpi_hifiberry_dacplusadc_update_rate_den(\n+\tstruct snd_pcm_substream *substream, struct snd_pcm_hw_params *params)\n+{\n+\tstruct snd_soc_pcm_runtime *rtd = substream->private_data;\n+\tstruct snd_soc_component *component = asoc_rtd_to_codec(rtd, 0)->component;\n+\tstruct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);\n+\tstruct snd_ratnum *rats_no_pll;\n+\tunsigned int num = 0, den = 0;\n+\tint err;\n+\n+\trats_no_pll = devm_kzalloc(rtd->dev, sizeof(*rats_no_pll), GFP_KERNEL);\n+\tif (!rats_no_pll)\n+\t\treturn -ENOMEM;\n+\n+\trats_no_pll->num = clk_get_rate(pcm512x->sclk) / 64;\n+\trats_no_pll->den_min = 1;\n+\trats_no_pll->den_max = 128;\n+\trats_no_pll->den_step = 1;\n+\n+\terr = snd_interval_ratnum(hw_param_interval(params,\n+\t\tSNDRV_PCM_HW_PARAM_RATE), 1, rats_no_pll, &num, &den);\n+\tif (err >= 0 && den) {\n+\t\tparams->rate_num = num;\n+\t\tparams->rate_den = den;\n+\t}\n+\n+\tdevm_kfree(rtd->dev, rats_no_pll);\n+\treturn 0;\n+}\n+\n+static int snd_rpi_hifiberry_dacplusadc_hw_params(\n+\tstruct snd_pcm_substream *substream, struct snd_pcm_hw_params *params)\n+{\n+\tint ret = 0;\n+\tstruct snd_soc_pcm_runtime *rtd = substream->private_data;\n+\tint channels = params_channels(params);\n+\tint width = 32;\n+\n+\tif (snd_rpi_hifiberry_is_dacpro) {\n+\t\tstruct snd_soc_component *component = asoc_rtd_to_codec(rtd, 0)->component;\n+\n+\t\twidth = snd_pcm_format_physical_width(params_format(params));\n+\n+\t\tsnd_rpi_hifiberry_dacplusadc_set_sclk(component,\n+\t\t\tparams_rate(params));\n+\n+\t\tret = snd_rpi_hifiberry_dacplusadc_update_rate_den(\n+\t\t\tsubstream, params);\n+\t}\n+\n+\tret = snd_soc_dai_set_bclk_ratio(asoc_rtd_to_cpu(rtd, 0), channels * width);\n+\tif (ret)\n+\t\treturn ret;\n+\tret = snd_soc_dai_set_bclk_ratio(asoc_rtd_to_codec(rtd, 0), channels * width);\n+\treturn ret;\n+}\n+\n+static int hifiberry_dacplusadc_LED_cnt;\n+\n+static int snd_rpi_hifiberry_dacplusadc_startup(\n+\tstruct snd_pcm_substream *substream)\n+{\n+\tstruct snd_soc_pcm_runtime *rtd = substream->private_data;\n+\tstruct snd_soc_component *component = asoc_rtd_to_codec(rtd, 0)->component;\n+\n+\tif (leds_off)\n+\t\treturn 0;\n+\tsnd_soc_component_update_bits(component, PCM512x_GPIO_CONTROL_1,\n+\t\t\t\t\t 0x08, 0x08);\n+\thifiberry_dacplusadc_LED_cnt++;\n+\treturn 0;\n+}\n+\n+static void snd_rpi_hifiberry_dacplusadc_shutdown(\n+\tstruct snd_pcm_substream *substream)\n+{\n+\tstruct snd_soc_pcm_runtime *rtd = substream->private_data;\n+\tstruct snd_soc_component *component = asoc_rtd_to_codec(rtd, 0)->component;\n+\n+\thifiberry_dacplusadc_LED_cnt--;\n+\tif (!hifiberry_dacplusadc_LED_cnt)\n+\t\tsnd_soc_component_update_bits(component, PCM512x_GPIO_CONTROL_1,\n+\t\t\t\t\t\t 0x08, 0x00);\n+}\n+\n+/* machine stream operations */\n+static struct snd_soc_ops snd_rpi_hifiberry_dacplusadc_ops = {\n+\t.hw_params = snd_rpi_hifiberry_dacplusadc_hw_params,\n+\t.startup = snd_rpi_hifiberry_dacplusadc_startup,\n+\t.shutdown = snd_rpi_hifiberry_dacplusadc_shutdown,\n+};\n+\n+SND_SOC_DAILINK_DEFS(hifi,\n+\tDAILINK_COMP_ARRAY(COMP_CPU(\"bcm2708-i2s.0\")),\n+\tDAILINK_COMP_ARRAY(COMP_CODEC(\"pcm512x.1-004d\", \"pcm512x-hifi\"),\n+\t\t\t   COMP_CODEC(\"dmic-codec\", \"dmic-hifi\")),\n+\tDAILINK_COMP_ARRAY(COMP_PLATFORM(\"bcm2708-i2s.0\")));\n+\n+static struct snd_soc_dai_link snd_rpi_hifiberry_dacplusadc_dai[] = {\n+{\n+\t.name\t\t= \"HiFiBerry DAC+ADC\",\n+\t.stream_name\t= \"HiFiBerry DAC+ADC HiFi\",\n+\t.dai_fmt\t= SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |\n+\t\t\t\tSND_SOC_DAIFMT_CBS_CFS,\n+\t.ops\t\t= &snd_rpi_hifiberry_dacplusadc_ops,\n+\t.init\t\t= snd_rpi_hifiberry_dacplusadc_init,\n+\tSND_SOC_DAILINK_REG(hifi),\n+},\n+};\n+\n+/* audio machine driver */\n+static struct snd_soc_card snd_rpi_hifiberry_dacplusadc = {\n+\t.name         = \"snd_rpi_hifiberry_dacplusadc\",\n+\t.driver_name  = \"HifiberryDacpAdc\",\n+\t.owner        = THIS_MODULE,\n+\t.dai_link     = snd_rpi_hifiberry_dacplusadc_dai,\n+\t.num_links    = ARRAY_SIZE(snd_rpi_hifiberry_dacplusadc_dai),\n+};\n+\n+\n+static int snd_rpi_hifiberry_dacplusadc_probe(struct platform_device *pdev)\n+{\n+\tint ret = 0;\n+\n+\tsnd_rpi_hifiberry_dacplusadc.dev = &pdev->dev;\n+\tif (pdev->dev.of_node) {\n+\t\tstruct device_node *i2s_node;\n+\t\tstruct snd_soc_dai_link *dai;\n+\n+\t\tdai = &snd_rpi_hifiberry_dacplusadc_dai[0];\n+\t\ti2s_node = of_parse_phandle(pdev->dev.of_node,\n+\t\t\t\"i2s-controller\", 0);\n+\t\tif (i2s_node) {\n+\t\t\tdai->cpus->of_node = i2s_node;\n+\t\t\tdai->platforms->of_node = i2s_node;\n+\t\t\tdai->cpus->dai_name = NULL;\n+\t\t\tdai->platforms->name = NULL;\n+\t\t}\n+\t}\n+\tdigital_gain_0db_limit = !of_property_read_bool(\n+\t\tpdev->dev.of_node, \"hifiberry,24db_digital_gain\");\n+\tslave = of_property_read_bool(pdev->dev.of_node,\n+\t\t\t\t\t\"hifiberry-dacplusadc,slave\");\n+\tleds_off = of_property_read_bool(pdev->dev.of_node,\n+\t\t\t\t\t\"hifiberry-dacplusadc,leds_off\");\n+\n+\tret = devm_snd_soc_register_card(&pdev->dev,\n+\t\t\t\t\t\t &snd_rpi_hifiberry_dacplusadc);\n+\tif (ret && ret != -EPROBE_DEFER)\n+\t\tdev_err(&pdev->dev,\n+\t\t\t\"snd_soc_register_card() failed: %d\\n\", ret);\n+\n+\treturn ret;\n+}\n+\n+static const struct of_device_id snd_rpi_hifiberry_dacplusadc_of_match[] = {\n+\t{ .compatible = \"hifiberry,hifiberry-dacplusadc\", },\n+\t{},\n+};\n+\n+MODULE_DEVICE_TABLE(of, snd_rpi_hifiberry_dacplusadc_of_match);\n+\n+static struct platform_driver snd_rpi_hifiberry_dacplusadc_driver = {\n+\t.driver = {\n+\t\t.name   = \"snd-rpi-hifiberry-dacplusadc\",\n+\t\t.owner  = THIS_MODULE,\n+\t\t.of_match_table = snd_rpi_hifiberry_dacplusadc_of_match,\n+\t},\n+\t.probe          = snd_rpi_hifiberry_dacplusadc_probe,\n+};\n+\n+static int __init hifiberry_dacplusadc_init(void)\n+{\n+\tint ret;\n+\n+\tdmic_codec_dev = platform_device_register_simple(\"dmic-codec\", -1, NULL,\n+\t\t\t\t\t\t\t 0);\n+\tif (IS_ERR(dmic_codec_dev)) {\n+\t\tpr_err(\"%s: dmic-codec device registration failed\\n\", __func__);\n+\t\treturn PTR_ERR(dmic_codec_dev);\n+\t}\n+\n+\tret = platform_driver_register(&snd_rpi_hifiberry_dacplusadc_driver);\n+\tif (ret) {\n+\t\tpr_err(\"%s: platform driver registration failed\\n\", __func__);\n+\t\tplatform_device_unregister(dmic_codec_dev);\n+\t}\n+\n+\treturn ret;\n+}\n+module_init(hifiberry_dacplusadc_init);\n+\n+static void __exit hifiberry_dacplusadc_exit(void)\n+{\n+\tplatform_driver_unregister(&snd_rpi_hifiberry_dacplusadc_driver);\n+\tplatform_device_unregister(dmic_codec_dev);\n+}\n+module_exit(hifiberry_dacplusadc_exit);\n+\n+MODULE_AUTHOR(\"Joerg Schambacher <joscha@schambacher.com>\");\n+MODULE_AUTHOR(\"Daniel Matuschek <daniel@hifiberry.com>\");\n+MODULE_DESCRIPTION(\"ASoC Driver for HiFiBerry DAC+ADC\");\n+MODULE_LICENSE(\"GPL v2\");\n--- /dev/null\n+++ b/sound/soc/bcm/hifiberry_dacplusadcpro.c\n@@ -0,0 +1,543 @@\n+/*\n+ * ASoC Driver for HiFiBerry DAC+ / DAC Pro with ADC PRO Version (SW control)\n+ *\n+ * Author:\tDaniel Matuschek, Stuart MacLean <stuart@hifiberry.com>\n+ *\t\tCopyright 2014-2015\n+ *\t\tbased on code by Florian Meier <florian.meier@koalo.de>\n+ *\t\tADC added by Joerg Schambacher <joerg@i2audio.com>\n+ *\t\tCopyright 2018-19\n+ *\n+ * This program is free software; you can redistribute it and/or\n+ * modify it under the terms of the GNU General Public License\n+ * version 2 as published by the Free Software Foundation.\n+ *\n+ * This program is distributed in the hope that it will be useful, but\n+ * WITHOUT ANY WARRANTY; without even the implied warranty of\n+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\n+ * General Public License for more details.\n+ */\n+\n+#include <linux/module.h>\n+#include <linux/platform_device.h>\n+#include <linux/kernel.h>\n+#include <linux/clk.h>\n+#include <linux/kernel.h>\n+#include <linux/module.h>\n+#include <linux/of.h>\n+#include <linux/slab.h>\n+#include <linux/delay.h>\n+\n+#include <sound/core.h>\n+#include <sound/pcm.h>\n+#include <sound/pcm_params.h>\n+#include <sound/soc.h>\n+#include <sound/jack.h>\n+#include <sound/tlv.h>\n+\n+#include \"../codecs/pcm512x.h\"\n+#include \"../codecs/pcm186x.h\"\n+\n+#define HIFIBERRY_DACPRO_NOCLOCK 0\n+#define HIFIBERRY_DACPRO_CLK44EN 1\n+#define HIFIBERRY_DACPRO_CLK48EN 2\n+\n+struct pcm512x_priv {\n+\tstruct regmap *regmap;\n+\tstruct clk *sclk;\n+};\n+\n+/* Clock rate of CLK44EN attached to GPIO6 pin */\n+#define CLK_44EN_RATE 22579200UL\n+/* Clock rate of CLK48EN attached to GPIO3 pin */\n+#define CLK_48EN_RATE 24576000UL\n+\n+static bool slave;\n+static bool snd_rpi_hifiberry_is_dacpro;\n+static bool digital_gain_0db_limit = true;\n+static bool leds_off;\n+\n+static const unsigned int pcm186x_adc_input_channel_sel_value[] = {\n+\t0x00, 0x01, 0x02, 0x03, 0x10\n+};\n+\n+static const char * const pcm186x_adcl_input_channel_sel_text[] = {\n+\t\"No Select\",\n+\t\"VINL1[SE]\",\t\t\t\t\t/* Default for ADCL */\n+\t\"VINL2[SE]\",\n+\t\"VINL2[SE] + VINL1[SE]\",\n+\t\"{VIN1P, VIN1M}[DIFF]\"\n+};\n+\n+static const char * const pcm186x_adcr_input_channel_sel_text[] = {\n+\t\"No Select\",\n+\t\"VINR1[SE]\",\t\t\t\t\t/* Default for ADCR */\n+\t\"VINR2[SE]\",\n+\t\"VINR2[SE] + VINR1[SE]\",\n+\t\"{VIN2P, VIN2M}[DIFF]\"\n+};\n+\n+static const struct soc_enum pcm186x_adc_input_channel_sel[] = {\n+\tSOC_VALUE_ENUM_SINGLE(PCM186X_ADC1_INPUT_SEL_L, 0,\n+\t\t\t      PCM186X_ADC_INPUT_SEL_MASK,\n+\t\t\t      ARRAY_SIZE(pcm186x_adcl_input_channel_sel_text),\n+\t\t\t      pcm186x_adcl_input_channel_sel_text,\n+\t\t\t      pcm186x_adc_input_channel_sel_value),\n+\tSOC_VALUE_ENUM_SINGLE(PCM186X_ADC1_INPUT_SEL_R, 0,\n+\t\t\t      PCM186X_ADC_INPUT_SEL_MASK,\n+\t\t\t      ARRAY_SIZE(pcm186x_adcr_input_channel_sel_text),\n+\t\t\t      pcm186x_adcr_input_channel_sel_text,\n+\t\t\t      pcm186x_adc_input_channel_sel_value),\n+};\n+\n+static const unsigned int pcm186x_mic_bias_sel_value[] = {\n+\t0x00, 0x01, 0x11\n+};\n+\n+static const char * const pcm186x_mic_bias_sel_text[] = {\n+\t\"Mic Bias off\",\n+\t\"Mic Bias on\",\n+\t\"Mic Bias with Bypass Resistor\"\n+};\n+\n+static const struct soc_enum pcm186x_mic_bias_sel[] = {\n+\tSOC_VALUE_ENUM_SINGLE(PCM186X_MIC_BIAS_CTRL, 0,\n+\t\t\t      GENMASK(4, 0),\n+\t\t\t      ARRAY_SIZE(pcm186x_mic_bias_sel_text),\n+\t\t\t      pcm186x_mic_bias_sel_text,\n+\t\t\t      pcm186x_mic_bias_sel_value),\n+};\n+\n+static const unsigned int pcm186x_gain_sel_value[] = {\n+\t0xe8, 0xe9, 0xea, 0xeb, 0xec, 0xed, 0xee, 0xef,\n+\t0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7,\n+\t0xf8, 0xf9, 0xfa, 0xfb, 0xfc, 0xfd, 0xfe, 0xff,\n+\t0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,\n+\t0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,\n+\t0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,\n+\t0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f,\n+\t0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27,\n+\t0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f,\n+\t0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,\n+\t0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f,\n+\t0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47,\n+\t0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f,\n+\t0x50\n+};\n+\n+static const char * const pcm186x_gain_sel_text[] = {\n+\t\"-12.0dB\", \"-11.5dB\", \"-11.0dB\", \"-10.5dB\", \"-10.0dB\", \"-9.5dB\",\n+\t\"-9.0dB\", \"-8.5dB\", \"-8.0dB\", \"-7.5dB\", \"-7.0dB\", \"-6.5dB\",\n+\t\"-6.0dB\", \"-5.5dB\", \"-5.0dB\", \"-4.5dB\", \"-4.0dB\", \"-3.5dB\",\n+\t\"-3.0dB\", \"-2.5dB\", \"-2.0dB\", \"-1.5dB\", \"-1.0dB\", \"-0.5dB\",\n+\t\"0.0dB\", \"0.5dB\", \"1.0dB\", \"1.5dB\", \"2.0dB\", \"2.5dB\",\n+\t\"3.0dB\", \"3.5dB\", \"4.0dB\", \"4.5dB\", \"5.0dB\", \"5.5dB\",\n+\t\"6.0dB\", \"6.5dB\", \"7.0dB\", \"7.5dB\", \"8.0dB\", \"8.5dB\",\n+\t\"9.0dB\", \"9.5dB\", \"10.0dB\", \"10.5dB\", \"11.0dB\", \"11.5dB\",\n+\t\"12.0dB\", \"12.5dB\", \"13.0dB\", \"13.5dB\", \"14.0dB\", \"14.5dB\",\n+\t\"15.0dB\", \"15.5dB\", \"16.0dB\", \"16.5dB\", \"17.0dB\", \"17.5dB\",\n+\t\"18.0dB\", \"18.5dB\", \"19.0dB\", \"19.5dB\", \"20.0dB\", \"20.5dB\",\n+\t\"21.0dB\", \"21.5dB\", \"22.0dB\", \"22.5dB\", \"23.0dB\", \"23.5dB\",\n+\t\"24.0dB\", \"24.5dB\", \"25.0dB\", \"25.5dB\", \"26.0dB\", \"26.5dB\",\n+\t\"27.0dB\", \"27.5dB\", \"28.0dB\", \"28.5dB\", \"29.0dB\", \"29.5dB\",\n+\t\"30.0dB\", \"30.5dB\", \"31.0dB\", \"31.5dB\", \"32.0dB\", \"32.5dB\",\n+\t\"33.0dB\", \"33.5dB\", \"34.0dB\", \"34.5dB\", \"35.0dB\", \"35.5dB\",\n+\t\"36.0dB\", \"36.5dB\", \"37.0dB\", \"37.5dB\", \"38.0dB\", \"38.5dB\",\n+\t\"39.0dB\", \"39.5dB\", \"40.0dB\"};\n+\n+static const struct soc_enum pcm186x_gain_sel[] = {\n+\tSOC_VALUE_ENUM_SINGLE(PCM186X_PGA_VAL_CH1_L, 0,\n+\t\t\t      0xff,\n+\t\t\t      ARRAY_SIZE(pcm186x_gain_sel_text),\n+\t\t\t      pcm186x_gain_sel_text,\n+\t\t\t      pcm186x_gain_sel_value),\n+\tSOC_VALUE_ENUM_SINGLE(PCM186X_PGA_VAL_CH1_R, 0,\n+\t\t\t      0xff,\n+\t\t\t      ARRAY_SIZE(pcm186x_gain_sel_text),\n+\t\t\t      pcm186x_gain_sel_text,\n+\t\t\t      pcm186x_gain_sel_value),\n+};\n+\n+static const struct snd_kcontrol_new pcm1863_snd_controls_card[] = {\n+\tSOC_ENUM(\"ADC Left Input\", pcm186x_adc_input_channel_sel[0]),\n+\tSOC_ENUM(\"ADC Right Input\", pcm186x_adc_input_channel_sel[1]),\n+\tSOC_ENUM(\"ADC Mic Bias\", pcm186x_mic_bias_sel),\n+\tSOC_ENUM(\"PGA Gain Left\", pcm186x_gain_sel[0]),\n+\tSOC_ENUM(\"PGA Gain Right\", pcm186x_gain_sel[1]),\n+};\n+\n+static int pcm1863_add_controls(struct snd_soc_component *component)\n+{\n+\tsnd_soc_add_component_controls(component,\n+\t\t\tpcm1863_snd_controls_card,\n+\t\t\tARRAY_SIZE(pcm1863_snd_controls_card));\n+\treturn 0;\n+}\n+\n+static void snd_rpi_hifiberry_dacplusadcpro_select_clk(\n+\t\t\t\t\tstruct snd_soc_component *component, int clk_id)\n+{\n+\tswitch (clk_id) {\n+\tcase HIFIBERRY_DACPRO_NOCLOCK:\n+\t\tsnd_soc_component_update_bits(component,\n+\t\t\t\tPCM512x_GPIO_CONTROL_1, 0x24, 0x00);\n+\t\tbreak;\n+\tcase HIFIBERRY_DACPRO_CLK44EN:\n+\t\tsnd_soc_component_update_bits(component,\n+\t\t\t\tPCM512x_GPIO_CONTROL_1, 0x24, 0x20);\n+\t\tbreak;\n+\tcase HIFIBERRY_DACPRO_CLK48EN:\n+\t\tsnd_soc_component_update_bits(component,\n+\t\t\t\tPCM512x_GPIO_CONTROL_1, 0x24, 0x04);\n+\t\tbreak;\n+\t}\n+}\n+\n+static void snd_rpi_hifiberry_dacplusadcpro_clk_gpio(struct snd_soc_component *component)\n+{\n+\tsnd_soc_component_update_bits(component, PCM512x_GPIO_EN, 0x24, 0x24);\n+\tsnd_soc_component_update_bits(component, PCM512x_GPIO_OUTPUT_3, 0x0f, 0x02);\n+\tsnd_soc_component_update_bits(component, PCM512x_GPIO_OUTPUT_6, 0x0f, 0x02);\n+}\n+\n+static bool snd_rpi_hifiberry_dacplusadcpro_is_sclk(struct snd_soc_component *component)\n+{\n+\tunsigned int sck;\n+\n+\tsck = snd_soc_component_read(component, PCM512x_RATE_DET_4);\n+\treturn (!(sck & 0x40));\n+}\n+\n+static bool snd_rpi_hifiberry_dacplusadcpro_is_sclk_sleep(\n+\tstruct snd_soc_component *component)\n+{\n+\tmsleep(2);\n+\treturn snd_rpi_hifiberry_dacplusadcpro_is_sclk(component);\n+}\n+\n+static bool snd_rpi_hifiberry_dacplusadcpro_is_pro_card(struct snd_soc_component *component)\n+{\n+\tbool isClk44EN, isClk48En, isNoClk;\n+\n+\tsnd_rpi_hifiberry_dacplusadcpro_clk_gpio(component);\n+\n+\tsnd_rpi_hifiberry_dacplusadcpro_select_clk(component, HIFIBERRY_DACPRO_CLK44EN);\n+\tisClk44EN = snd_rpi_hifiberry_dacplusadcpro_is_sclk_sleep(component);\n+\n+\tsnd_rpi_hifiberry_dacplusadcpro_select_clk(component, HIFIBERRY_DACPRO_NOCLOCK);\n+\tisNoClk = snd_rpi_hifiberry_dacplusadcpro_is_sclk_sleep(component);\n+\n+\tsnd_rpi_hifiberry_dacplusadcpro_select_clk(component, HIFIBERRY_DACPRO_CLK48EN);\n+\tisClk48En = snd_rpi_hifiberry_dacplusadcpro_is_sclk_sleep(component);\n+\n+\treturn (isClk44EN && isClk48En && !isNoClk);\n+}\n+\n+static int snd_rpi_hifiberry_dacplusadcpro_clk_for_rate(int sample_rate)\n+{\n+\tint type;\n+\n+\tswitch (sample_rate) {\n+\tcase 11025:\n+\tcase 22050:\n+\tcase 44100:\n+\tcase 88200:\n+\tcase 176400:\n+\tcase 352800:\n+\t\ttype = HIFIBERRY_DACPRO_CLK44EN;\n+\t\tbreak;\n+\tdefault:\n+\t\ttype = HIFIBERRY_DACPRO_CLK48EN;\n+\t\tbreak;\n+\t}\n+\treturn type;\n+}\n+\n+static void snd_rpi_hifiberry_dacplusadcpro_set_sclk(struct snd_soc_component *component,\n+\tint sample_rate)\n+{\n+\tstruct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);\n+\n+\tif (!IS_ERR(pcm512x->sclk)) {\n+\t\tint ctype;\n+\n+\t\tctype = snd_rpi_hifiberry_dacplusadcpro_clk_for_rate(sample_rate);\n+\t\tclk_set_rate(pcm512x->sclk, (ctype == HIFIBERRY_DACPRO_CLK44EN)\n+\t\t\t? CLK_44EN_RATE : CLK_48EN_RATE);\n+\t\tsnd_rpi_hifiberry_dacplusadcpro_select_clk(component, ctype);\n+\t}\n+}\n+\n+static int snd_rpi_hifiberry_dacplusadcpro_init(struct snd_soc_pcm_runtime *rtd)\n+{\n+\tstruct snd_soc_component *dac = asoc_rtd_to_codec(rtd, 0)->component;\n+\tstruct snd_soc_component *adc = asoc_rtd_to_codec(rtd, 1)->component;\n+\tstruct snd_soc_dai_driver *adc_driver = asoc_rtd_to_codec(rtd, 1)->driver;\n+\tstruct pcm512x_priv *priv;\n+\tint ret;\n+\n+\tif (slave)\n+\t\tsnd_rpi_hifiberry_is_dacpro = false;\n+\telse\n+\t\tsnd_rpi_hifiberry_is_dacpro =\n+\t\t\t\tsnd_rpi_hifiberry_dacplusadcpro_is_pro_card(dac);\n+\n+\tif (snd_rpi_hifiberry_is_dacpro) {\n+\t\tstruct snd_soc_dai_link *dai = rtd->dai_link;\n+\n+\t\tdai->name = \"HiFiBerry DAC+ADC Pro\";\n+\t\tdai->stream_name = \"HiFiBerry DAC+ADC Pro HiFi\";\n+\t\tdai->dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF\n+\t\t\t| SND_SOC_DAIFMT_CBM_CFM;\n+\n+\t\t// set DAC DAI configuration\n+\t\tret = snd_soc_dai_set_fmt(asoc_rtd_to_codec(rtd, 0),\n+\t\t\t\tSND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF\n+\t\t\t| SND_SOC_DAIFMT_CBM_CFM);\n+\t\tif (ret < 0)\n+\t\t\treturn ret;\n+\n+\t\t// set ADC DAI configuration\n+\t\tret = snd_soc_dai_set_fmt(asoc_rtd_to_codec(rtd, 1),\n+\t\t\t\tSND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF\n+\t\t\t| SND_SOC_DAIFMT_CBS_CFS);\n+\t\tif (ret < 0)\n+\t\t\treturn ret;\n+\n+\t\t// set CPU DAI configuration\n+\t\tret = snd_soc_dai_set_fmt(asoc_rtd_to_cpu(rtd, 0),\n+\t\t\tSND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBS_CFS);\n+\t\tif (ret < 0)\n+\t\t\treturn ret;\n+\n+\t\tsnd_soc_component_update_bits(dac, PCM512x_BCLK_LRCLK_CFG, 0x31, 0x11);\n+\t\tsnd_soc_component_update_bits(dac, PCM512x_MASTER_MODE, 0x03, 0x03);\n+\t\tsnd_soc_component_update_bits(dac, PCM512x_MASTER_CLKDIV_2, 0x7f, 63);\n+\t} else {\n+\t\tpriv = snd_soc_component_get_drvdata(dac);\n+\t\tpriv->sclk = ERR_PTR(-ENOENT);\n+\t}\n+\n+\t/* disable 24bit mode as long as I2S module does not have sign extension fixed */\n+\tadc_driver->capture.formats = SNDRV_PCM_FMTBIT_S32_LE | SNDRV_PCM_FMTBIT_S16_LE;\n+\n+\tsnd_soc_component_update_bits(dac, PCM512x_GPIO_EN, 0x08, 0x08);\n+\tsnd_soc_component_update_bits(dac, PCM512x_GPIO_OUTPUT_4, 0x0f, 0x02);\n+\tif (leds_off)\n+\t\tsnd_soc_component_update_bits(dac, PCM512x_GPIO_CONTROL_1, 0x08, 0x00);\n+\telse\n+\t\tsnd_soc_component_update_bits(dac, PCM512x_GPIO_CONTROL_1, 0x08, 0x08);\n+\n+\tret = pcm1863_add_controls(adc);\n+\tif (ret < 0)\n+\t\tdev_warn(rtd->dev, \"Failed to add pcm1863 controls: %d\\n\",\n+\t\tret);\n+\n+\t/* set GPIO2 to output, GPIO3 input */\n+\tsnd_soc_component_write(adc, PCM186X_GPIO3_2_CTRL, 0x00);\n+\tsnd_soc_component_write(adc, PCM186X_GPIO3_2_DIR_CTRL, 0x04);\n+\tif (leds_off)\n+\t\tsnd_soc_component_update_bits(adc, PCM186X_GPIO_IN_OUT, 0x40, 0x00);\n+\telse\n+\t\tsnd_soc_component_update_bits(adc, PCM186X_GPIO_IN_OUT, 0x40, 0x40);\n+\n+\tif (digital_gain_0db_limit) {\n+\t\tint ret;\n+\t\tstruct snd_soc_card *card = rtd->card;\n+\n+\t\tret = snd_soc_limit_volume(card, \"Digital Playback Volume\", 207);\n+\t\tif (ret < 0)\n+\t\t\tdev_warn(card->dev, \"Failed to set volume limit: %d\\n\", ret);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int snd_rpi_hifiberry_dacplusadcpro_update_rate_den(\n+\tstruct snd_pcm_substream *substream, struct snd_pcm_hw_params *params)\n+{\n+\tstruct snd_soc_pcm_runtime *rtd = substream->private_data;\n+\tstruct snd_soc_component *component = asoc_rtd_to_codec(rtd, 0)->component; /* only use DAC */\n+\tstruct pcm512x_priv *pcm512x = snd_soc_component_get_drvdata(component);\n+\tstruct snd_ratnum *rats_no_pll;\n+\tunsigned int num = 0, den = 0;\n+\tint err;\n+\n+\trats_no_pll = devm_kzalloc(rtd->dev, sizeof(*rats_no_pll), GFP_KERNEL);\n+\tif (!rats_no_pll)\n+\t\treturn -ENOMEM;\n+\n+\trats_no_pll->num = clk_get_rate(pcm512x->sclk) / 64;\n+\trats_no_pll->den_min = 1;\n+\trats_no_pll->den_max = 128;\n+\trats_no_pll->den_step = 1;\n+\n+\terr = snd_interval_ratnum(hw_param_interval(params,\n+\t\tSNDRV_PCM_HW_PARAM_RATE), 1, rats_no_pll, &num, &den);\n+\tif (err >= 0 && den) {\n+\t\tparams->rate_num = num;\n+\t\tparams->rate_den = den;\n+\t}\n+\n+\tdevm_kfree(rtd->dev, rats_no_pll);\n+\treturn 0;\n+}\n+\n+static int snd_rpi_hifiberry_dacplusadcpro_hw_params(\n+\tstruct snd_pcm_substream *substream, struct snd_pcm_hw_params *params)\n+{\n+\tint ret = 0;\n+\tstruct snd_soc_pcm_runtime *rtd = substream->private_data;\n+\tint channels = params_channels(params);\n+\tint width = 32;\n+\tstruct snd_soc_component *dac = asoc_rtd_to_codec(rtd, 0)->component;\n+\tstruct snd_soc_dai *dai = asoc_rtd_to_codec(rtd, 0);\n+\tstruct snd_soc_dai_driver *drv = dai->driver;\n+\tconst struct snd_soc_dai_ops *ops = drv->ops;\n+\n+\tif (snd_rpi_hifiberry_is_dacpro) {\n+\t\twidth = snd_pcm_format_physical_width(params_format(params));\n+\n+\t\tsnd_rpi_hifiberry_dacplusadcpro_set_sclk(dac,\n+\t\t\tparams_rate(params));\n+\n+\t\tret = snd_rpi_hifiberry_dacplusadcpro_update_rate_den(\n+\t\t\tsubstream, params);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\t}\n+\n+\tret = snd_soc_dai_set_bclk_ratio(asoc_rtd_to_cpu(rtd, 0), channels * width);\n+\tif (ret)\n+\t\treturn ret;\n+\tret = snd_soc_dai_set_bclk_ratio(asoc_rtd_to_codec(rtd, 0), channels * width);\n+\tif (ret)\n+\t\treturn ret;\n+\tif (snd_rpi_hifiberry_is_dacpro && ops->hw_params)\n+\t\tret = ops->hw_params(substream, params, dai);\n+\treturn ret;\n+}\n+\n+static int snd_rpi_hifiberry_dacplusadcpro_startup(\n+\tstruct snd_pcm_substream *substream)\n+{\n+\tstruct snd_soc_pcm_runtime *rtd = substream->private_data;\n+\tstruct snd_soc_component *dac = asoc_rtd_to_codec(rtd, 0)->component;\n+\tstruct snd_soc_component *adc = asoc_rtd_to_codec(rtd, 1)->component;\n+\n+\tif (leds_off)\n+\t\treturn 0;\n+\t/* switch on respective LED */\n+\tif (!substream->stream)\n+\t\tsnd_soc_component_update_bits(dac, PCM512x_GPIO_CONTROL_1, 0x08, 0x08);\n+\telse\n+\t\tsnd_soc_component_update_bits(adc, PCM186X_GPIO_IN_OUT, 0x40, 0x40);\n+\treturn 0;\n+}\n+\n+static void snd_rpi_hifiberry_dacplusadcpro_shutdown(\n+\tstruct snd_pcm_substream *substream)\n+{\n+\tstruct snd_soc_pcm_runtime *rtd = substream->private_data;\n+\tstruct snd_soc_component *dac = asoc_rtd_to_codec(rtd, 0)->component;\n+\tstruct snd_soc_component *adc = asoc_rtd_to_codec(rtd, 1)->component;\n+\n+\t/* switch off respective LED */\n+\tif (!substream->stream)\n+\t\tsnd_soc_component_update_bits(dac, PCM512x_GPIO_CONTROL_1, 0x08, 0x00);\n+\telse\n+\t\tsnd_soc_component_update_bits(adc, PCM186X_GPIO_IN_OUT, 0x40, 0x00);\n+}\n+\n+\n+/* machine stream operations */\n+static struct snd_soc_ops snd_rpi_hifiberry_dacplusadcpro_ops = {\n+\t.hw_params = snd_rpi_hifiberry_dacplusadcpro_hw_params,\n+\t.startup = snd_rpi_hifiberry_dacplusadcpro_startup,\n+\t.shutdown = snd_rpi_hifiberry_dacplusadcpro_shutdown,\n+};\n+\n+SND_SOC_DAILINK_DEFS(hifi,\n+\tDAILINK_COMP_ARRAY(COMP_CPU(\"bcm2708-i2s.0\")),\n+\tDAILINK_COMP_ARRAY(COMP_CODEC(\"pcm512x.1-004d\", \"pcm512x-hifi\"),\n+\t\t\t   COMP_CODEC(\"pcm186x.1-004a\", \"pcm1863-aif\")),\n+\tDAILINK_COMP_ARRAY(COMP_PLATFORM(\"bcm2708-i2s.0\")));\n+\n+static struct snd_soc_dai_link snd_rpi_hifiberry_dacplusadcpro_dai[] = {\n+{\n+\t.name\t\t= \"HiFiBerry DAC+ADC PRO\",\n+\t.stream_name\t= \"HiFiBerry DAC+ADC PRO HiFi\",\n+\t.dai_fmt\t= SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |\n+\t\t\t\tSND_SOC_DAIFMT_CBS_CFS,\n+\t.ops\t\t= &snd_rpi_hifiberry_dacplusadcpro_ops,\n+\t.init\t\t= snd_rpi_hifiberry_dacplusadcpro_init,\n+\tSND_SOC_DAILINK_REG(hifi),\n+},\n+};\n+\n+/* audio machine driver */\n+static struct snd_soc_card snd_rpi_hifiberry_dacplusadcpro = {\n+\t.name         = \"snd_rpi_hifiberry_dacplusadcpro\",\n+\t.driver_name  = \"HifiberryDacpAdcPro\",\n+\t.owner        = THIS_MODULE,\n+\t.dai_link     = snd_rpi_hifiberry_dacplusadcpro_dai,\n+\t.num_links    = ARRAY_SIZE(snd_rpi_hifiberry_dacplusadcpro_dai),\n+};\n+\n+static int snd_rpi_hifiberry_dacplusadcpro_probe(struct platform_device *pdev)\n+{\n+\tint ret = 0, i = 0;\n+\tstruct snd_soc_card *card = &snd_rpi_hifiberry_dacplusadcpro;\n+\n+\tsnd_rpi_hifiberry_dacplusadcpro.dev = &pdev->dev;\n+\tif (pdev->dev.of_node) {\n+\t\tstruct device_node *i2s_node;\n+\t\tstruct snd_soc_dai_link *dai;\n+\n+\t\tdai = &snd_rpi_hifiberry_dacplusadcpro_dai[0];\n+\t\ti2s_node = of_parse_phandle(pdev->dev.of_node,\n+\t\t\t\"i2s-controller\", 0);\n+\t\tif (i2s_node) {\n+\t\t\tfor (i = 0; i < card->num_links; i++) {\n+\t\t\t\tdai->cpus->dai_name = NULL;\n+\t\t\t\tdai->cpus->of_node = i2s_node;\n+\t\t\t\tdai->platforms->name = NULL;\n+\t\t\t\tdai->platforms->of_node = i2s_node;\n+\t\t\t}\n+\t\t}\n+\t}\n+\tdigital_gain_0db_limit = !of_property_read_bool(\n+\t\tpdev->dev.of_node, \"hifiberry-dacplusadcpro,24db_digital_gain\");\n+\tslave = of_property_read_bool(pdev->dev.of_node,\n+\t\t\t\t\t\"hifiberry-dacplusadcpro,slave\");\n+\tleds_off = of_property_read_bool(pdev->dev.of_node,\n+\t\t\t\t\t\"hifiberry-dacplusadcpro,leds_off\");\n+\tret = snd_soc_register_card(&snd_rpi_hifiberry_dacplusadcpro);\n+\tif (ret && ret != -EPROBE_DEFER)\n+\t\tdev_err(&pdev->dev,\n+\t\t\t\"snd_soc_register_card() failed: %d\\n\", ret);\n+\n+\treturn ret;\n+}\n+\n+static const struct of_device_id snd_rpi_hifiberry_dacplusadcpro_of_match[] = {\n+\t{ .compatible = \"hifiberry,hifiberry-dacplusadcpro\", },\n+\t{},\n+};\n+\n+MODULE_DEVICE_TABLE(of, snd_rpi_hifiberry_dacplusadcpro_of_match);\n+\n+static struct platform_driver snd_rpi_hifiberry_dacplusadcpro_driver = {\n+\t.driver = {\n+\t\t.name   = \"snd-rpi-hifiberry-dacplusadcpro\",\n+\t\t.owner  = THIS_MODULE,\n+\t\t.of_match_table = snd_rpi_hifiberry_dacplusadcpro_of_match,\n+\t},\n+\t.probe          = snd_rpi_hifiberry_dacplusadcpro_probe,\n+};\n+\n+module_platform_driver(snd_rpi_hifiberry_dacplusadcpro_driver);\n+\n+MODULE_AUTHOR(\"Joerg Schambacher <joerg@i2audio.com>\");\n+MODULE_AUTHOR(\"Daniel Matuschek <daniel@hifiberry.com>\");\n+MODULE_DESCRIPTION(\"ASoC Driver for HiFiBerry DAC+ADC\");\n+MODULE_LICENSE(\"GPL v2\");\n--- /dev/null\n+++ b/sound/soc/bcm/hifiberry_dacplusdsp.c\n@@ -0,0 +1,90 @@\n+// SPDX-License-Identifier: GPL-2.0\n+/*\n+ * ASoC Driver for HiFiBerry DAC + DSP\n+ *\n+ * Author:\tJoerg Schambacher <joscha@schambacher.com>\n+ *\t\tCopyright 2018\n+ *\n+ * This program is free software; you can redistribute it and/or\n+ * modify it under the terms of the GNU General Public License\n+ * version 2 as published by the Free Software Foundation.\n+ *\n+ * This program is distributed in the hope that it will be useful, but\n+ * WITHOUT ANY WARRANTY; without even the implied warranty of\n+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\n+ * General Public License for more details.\n+ */\n+\n+#include <linux/init.h>\n+#include <linux/module.h>\n+#include <linux/of.h>\n+#include <linux/platform_device.h>\n+#include <sound/soc.h>\n+\n+static struct snd_soc_component_driver dacplusdsp_component_driver;\n+\n+static struct snd_soc_dai_driver dacplusdsp_dai = {\n+\t.name = \"dacplusdsp-hifi\",\n+\t.capture = {\n+\t\t.stream_name = \"DAC+DSP Capture\",\n+\t\t.channels_min = 2,\n+\t\t.channels_max = 2,\n+\t\t.rates = SNDRV_PCM_RATE_CONTINUOUS,\n+\t\t.formats = SNDRV_PCM_FMTBIT_S16_LE |\n+\t\t\t   SNDRV_PCM_FMTBIT_S24_LE |\n+\t\t\t   SNDRV_PCM_FMTBIT_S32_LE,\n+\t},\n+\t.playback = {\n+\t\t.stream_name = \"DACP+DSP Playback\",\n+\t\t.channels_min = 2,\n+\t\t.channels_max = 2,\n+\t\t.rates = SNDRV_PCM_RATE_CONTINUOUS,\n+\t\t.formats = SNDRV_PCM_FMTBIT_S16_LE |\n+\t\t\t   SNDRV_PCM_FMTBIT_S24_LE |\n+\t\t\t   SNDRV_PCM_FMTBIT_S32_LE,\n+\t},\n+\t.symmetric_rates = 1};\n+\n+#ifdef CONFIG_OF\n+static const struct of_device_id dacplusdsp_ids[] = {\n+\t{\n+\t\t.compatible = \"hifiberry,dacplusdsp\",\n+\t},\n+\t{} };\n+MODULE_DEVICE_TABLE(of, dacplusdsp_ids);\n+#endif\n+\n+static int dacplusdsp_platform_probe(struct platform_device *pdev)\n+{\n+\tint ret;\n+\n+\tret = snd_soc_register_component(&pdev->dev,\n+\t\t\t&dacplusdsp_component_driver, &dacplusdsp_dai, 1);\n+\tif (ret) {\n+\t\tpr_alert(\"snd_soc_register_component failed\\n\");\n+\t\treturn ret;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int dacplusdsp_platform_remove(struct platform_device *pdev)\n+{\n+\tsnd_soc_unregister_component(&pdev->dev);\n+\treturn 0;\n+}\n+\n+static struct platform_driver dacplusdsp_driver = {\n+\t.driver = {\n+\t\t.name = \"hifiberry-dacplusdsp-codec\",\n+\t\t.of_match_table = of_match_ptr(dacplusdsp_ids),\n+\t\t},\n+\t\t.probe = dacplusdsp_platform_probe,\n+\t\t.remove = dacplusdsp_platform_remove,\n+};\n+\n+module_platform_driver(dacplusdsp_driver);\n+\n+MODULE_AUTHOR(\"Joerg Schambacher <joerg@i2audio.com>\");\n+MODULE_DESCRIPTION(\"ASoC Driver for HiFiBerry DAC+DSP\");\n+MODULE_LICENSE(\"GPL v2\");\n--- /dev/null\n+++ b/sound/soc/bcm/hifiberry_dacplushd.c\n@@ -0,0 +1,238 @@\n+// SPDX-License-Identifier: GPL-2.0\n+/*\n+ * ASoC Driver for HiFiBerry DAC+ HD\n+ *\n+ * Author:\tJoerg Schambacher, i2Audio GmbH for HiFiBerry\n+ *\t\tCopyright 2020\n+ *\n+ * This program is free software; you can redistribute it and/or\n+ * modify it under the terms of the GNU General Public License\n+ * version 2 as published by the Free Software Foundation.\n+ *\n+ * This program is distributed in the hope that it will be useful, but\n+ * WITHOUT ANY WARRANTY; without even the implied warranty of\n+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\n+ * General Public License for more details.\n+ */\n+\n+#include <linux/module.h>\n+#include <linux/platform_device.h>\n+#include <linux/kernel.h>\n+#include <linux/delay.h>\n+#include <linux/module.h>\n+#include <linux/of.h>\n+#include <linux/delay.h>\n+#include <linux/gpio.h>\n+#include <linux/gpio/consumer.h>\n+#include <sound/core.h>\n+#include <sound/pcm.h>\n+#include <sound/pcm_params.h>\n+#include <sound/soc.h>\n+#include <linux/i2c.h>\n+#include <linux/clk.h>\n+\n+#include \"../codecs/pcm179x.h\"\n+\n+#define DEFAULT_RATE\t\t44100\n+\n+struct brd_drv_data {\n+\tstruct regmap *regmap;\n+\tstruct clk *sclk;\n+};\n+\n+static struct brd_drv_data drvdata;\n+static struct gpio_desc *reset_gpio;\n+static const unsigned int hb_dacplushd_rates[] = {\n+\t192000, 96000, 48000, 176400, 88200, 44100,\n+};\n+\n+static struct snd_pcm_hw_constraint_list hb_dacplushd_constraints = {\n+\t.list = hb_dacplushd_rates,\n+\t.count = ARRAY_SIZE(hb_dacplushd_rates),\n+};\n+\n+static int snd_rpi_hb_dacplushd_startup(struct snd_pcm_substream *substream)\n+{\n+\t/* constraints for standard sample rates */\n+\tsnd_pcm_hw_constraint_list(substream->runtime, 0,\n+\t\t\t\tSNDRV_PCM_HW_PARAM_RATE,\n+\t\t\t\t&hb_dacplushd_constraints);\n+\treturn 0;\n+}\n+\n+static void snd_rpi_hifiberry_dacplushd_set_sclk(\n+\t\tstruct snd_soc_component *component,\n+\t\tint sample_rate)\n+{\n+\tif (!IS_ERR(drvdata.sclk))\n+\t\tclk_set_rate(drvdata.sclk, sample_rate);\n+}\n+\n+static int snd_rpi_hifiberry_dacplushd_init(struct snd_soc_pcm_runtime *rtd)\n+{\n+\tstruct snd_soc_dai_link *dai = rtd->dai_link;\n+\tstruct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);\n+\n+\tdai->name = \"HiFiBerry DAC+ HD\";\n+\tdai->stream_name = \"HiFiBerry DAC+ HD HiFi\";\n+\tdai->dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF\n+\t\t| SND_SOC_DAIFMT_CBM_CFM;\n+\n+\t/* allow only fixed 32 clock counts per channel */\n+\tsnd_soc_dai_set_bclk_ratio(cpu_dai, 32*2);\n+\n+\treturn 0;\n+}\n+\n+static int snd_rpi_hifiberry_dacplushd_hw_params(\n+\tstruct snd_pcm_substream *substream, struct snd_pcm_hw_params *params)\n+{\n+\tint ret = 0;\n+\tstruct snd_soc_pcm_runtime *rtd = substream->private_data;\n+\n+\tstruct snd_soc_component *component = asoc_rtd_to_codec(rtd, 0)->component;\n+\n+\tsnd_rpi_hifiberry_dacplushd_set_sclk(component, params_rate(params));\n+\treturn ret;\n+}\n+\n+/* machine stream operations */\n+static struct snd_soc_ops snd_rpi_hifiberry_dacplushd_ops = {\n+\t.startup = snd_rpi_hb_dacplushd_startup,\n+\t.hw_params = snd_rpi_hifiberry_dacplushd_hw_params,\n+};\n+\n+SND_SOC_DAILINK_DEFS(hifi,\n+\tDAILINK_COMP_ARRAY(COMP_CPU(\"bcm2708-i2s.0\")),\n+\tDAILINK_COMP_ARRAY(COMP_CODEC(\"pcm179x.1-004c\", \"pcm179x-hifi\")),\n+\tDAILINK_COMP_ARRAY(COMP_PLATFORM(\"bcm2708-i2s.0\")));\n+\n+\n+static struct snd_soc_dai_link snd_rpi_hifiberry_dacplushd_dai[] = {\n+{\n+\t.name\t\t= \"HiFiBerry DAC+ HD\",\n+\t.stream_name\t= \"HiFiBerry DAC+ HD HiFi\",\n+\t.dai_fmt\t= SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |\n+\t\t\t\tSND_SOC_DAIFMT_CBS_CFS,\n+\t.ops\t\t= &snd_rpi_hifiberry_dacplushd_ops,\n+\t.init\t\t= snd_rpi_hifiberry_dacplushd_init,\n+\tSND_SOC_DAILINK_REG(hifi),\n+},\n+};\n+\n+/* audio machine driver */\n+static struct snd_soc_card snd_rpi_hifiberry_dacplushd = {\n+\t.name         = \"snd_rpi_hifiberry_dacplushd\",\n+\t.driver_name  = \"HifiberryDacplusHD\",\n+\t.owner        = THIS_MODULE,\n+\t.dai_link     = snd_rpi_hifiberry_dacplushd_dai,\n+\t.num_links    = ARRAY_SIZE(snd_rpi_hifiberry_dacplushd_dai),\n+};\n+\n+static int snd_rpi_hifiberry_dacplushd_probe(struct platform_device *pdev)\n+{\n+\tint ret = 0;\n+\tstatic int dac_reset_done;\n+\tstruct device *dev = &pdev->dev;\n+\tstruct device_node *dev_node = dev->of_node;\n+\n+\tsnd_rpi_hifiberry_dacplushd.dev = &pdev->dev;\n+\n+\t/* get GPIO and release DAC from RESET */\n+\tif (!dac_reset_done) {\n+\t\treset_gpio = gpiod_get(&pdev->dev, \"reset\", GPIOD_OUT_LOW);\n+\t\tif (IS_ERR(reset_gpio)) {\n+\t\t\tdev_err(&pdev->dev, \"gpiod_get() failed\\n\");\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t\tdac_reset_done = 1;\n+\t}\n+\tif (!IS_ERR(reset_gpio))\n+\t\tgpiod_set_value(reset_gpio, 0);\n+\tmsleep(1);\n+\tif (!IS_ERR(reset_gpio))\n+\t\tgpiod_set_value(reset_gpio, 1);\n+\tmsleep(1);\n+\tif (!IS_ERR(reset_gpio))\n+\t\tgpiod_set_value(reset_gpio, 0);\n+\n+\tif (pdev->dev.of_node) {\n+\t\tstruct device_node *i2s_node;\n+\t\tstruct snd_soc_dai_link *dai;\n+\n+\t\tdai = &snd_rpi_hifiberry_dacplushd_dai[0];\n+\t\ti2s_node = of_parse_phandle(pdev->dev.of_node,\n+\t\t\t\"i2s-controller\", 0);\n+\n+\t\tif (i2s_node) {\n+\t\t\tdai->cpus->of_node = i2s_node;\n+\t\t\tdai->platforms->of_node = i2s_node;\n+\t\t\tdai->cpus->dai_name = NULL;\n+\t\t\tdai->platforms->name = NULL;\n+\t\t} else {\n+\t\t\treturn -EPROBE_DEFER;\n+\t\t}\n+\n+\t}\n+\n+\tret = devm_snd_soc_register_card(&pdev->dev,\n+\t\t\t&snd_rpi_hifiberry_dacplushd);\n+\tif (ret && ret != -EPROBE_DEFER) {\n+\t\tdev_err(&pdev->dev,\n+\t\t\t\"snd_soc_register_card() failed: %d\\n\", ret);\n+\t\treturn ret;\n+\t}\n+\tif (ret == -EPROBE_DEFER)\n+\t\treturn ret;\n+\n+\tdev_set_drvdata(dev, &drvdata);\n+\tif (dev_node == NULL) {\n+\t\tdev_err(&pdev->dev, \"Device tree node not found\\n\");\n+\t\treturn -ENODEV;\n+\t}\n+\n+\tdrvdata.sclk = devm_clk_get(dev, NULL);\n+\tif (IS_ERR(drvdata.sclk)) {\n+\t\tdrvdata.sclk = ERR_PTR(-ENOENT);\n+\t\treturn -ENODEV;\n+\t}\n+\n+\tclk_set_rate(drvdata.sclk, DEFAULT_RATE);\n+\n+\treturn ret;\n+}\n+\n+static int snd_rpi_hifiberry_dacplushd_remove(struct platform_device *pdev)\n+{\n+\tif (IS_ERR(reset_gpio))\n+\t\treturn -EINVAL;\n+\n+\t/* put DAC into RESET and release GPIO */\n+\tgpiod_set_value(reset_gpio, 0);\n+\tgpiod_put(reset_gpio);\n+\n+\treturn 0;\n+}\n+\n+static const struct of_device_id snd_rpi_hifiberry_dacplushd_of_match[] = {\n+\t{ .compatible = \"hifiberry,hifiberry-dacplushd\", },\n+\t{},\n+};\n+\n+MODULE_DEVICE_TABLE(of, snd_rpi_hifiberry_dacplushd_of_match);\n+\n+static struct platform_driver snd_rpi_hifiberry_dacplushd_driver = {\n+\t.driver = {\n+\t\t.name   = \"snd-rpi-hifiberry-dacplushd\",\n+\t\t.owner  = THIS_MODULE,\n+\t\t.of_match_table = snd_rpi_hifiberry_dacplushd_of_match,\n+\t},\n+\t.probe          = snd_rpi_hifiberry_dacplushd_probe,\n+\t.remove\t\t= snd_rpi_hifiberry_dacplushd_remove,\n+};\n+\n+module_platform_driver(snd_rpi_hifiberry_dacplushd_driver);\n+\n+MODULE_AUTHOR(\"Joerg Schambacher <joerg@i2audio.com>\");\n+MODULE_DESCRIPTION(\"ASoC Driver for HiFiBerry DAC+ HD\");\n+MODULE_LICENSE(\"GPL v2\");\n--- /dev/null\n+++ b/sound/soc/bcm/i-sabre-q2m.c\n@@ -0,0 +1,158 @@\n+/*\n+ * ASoC Driver for I-Sabre Q2M\n+ *\n+ * Author: Satoru Kawase\n+ * Modified by: Xiao Qingyong\n+ * Update kernel v4.18+ by : Audiophonics\n+ * \t\tCopyright 2018 Audiophonics\n+ *\n+ * This program is free software; you can redistribute it and/or\n+ * modify it under the terms of the GNU General Public License\n+ * version 2 as published by the Free Software Foundation.\n+ *\n+ * This program is distributed in the hope that it will be useful, but\n+ * WITHOUT ANY WARRANTY; without even the implied warranty of\n+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\n+ * General Public License for more details.\n+ */\n+\n+#include <linux/kernel.h>\n+#include <linux/init.h>\n+#include <linux/module.h>\n+#include <linux/delay.h>\n+#include <linux/fs.h>\n+#include <asm/uaccess.h>\n+#include <sound/core.h>\n+#include <sound/soc.h>\n+#include <sound/pcm.h>\n+#include <sound/pcm_params.h>\n+\n+#include \"../codecs/i-sabre-codec.h\"\n+\n+\n+static int snd_rpi_i_sabre_q2m_init(struct snd_soc_pcm_runtime *rtd)\n+{\n+\tstruct snd_soc_component *component = asoc_rtd_to_codec(rtd, 0)->component;\n+\tunsigned int value;\n+\n+\t/* Device ID */\n+\tvalue = snd_soc_component_read(component, ISABRECODEC_REG_01);\n+\tdev_info(component->card->dev, \"Audiophonics Device ID : %02X\\n\", value);\n+\n+\t/* API revision */\n+\tvalue = snd_soc_component_read(component, ISABRECODEC_REG_02);\n+\tdev_info(component->card->dev, \"Audiophonics API revision : %02X\\n\", value);\n+\n+\treturn 0;\n+}\n+\n+static int snd_rpi_i_sabre_q2m_hw_params(\n+\tstruct snd_pcm_substream *substream, struct snd_pcm_hw_params *params)\n+{\n+\tstruct snd_soc_pcm_runtime *rtd     = substream->private_data;\n+\tstruct snd_soc_dai         *cpu_dai = asoc_rtd_to_cpu(rtd, 0);\n+\tint bclk_ratio;\n+\n+\tbclk_ratio = snd_pcm_format_physical_width(\n+\t\t\tparams_format(params)) * params_channels(params);\n+\treturn snd_soc_dai_set_bclk_ratio(cpu_dai, bclk_ratio);\n+}\n+\n+/* machine stream operations */\n+static struct snd_soc_ops snd_rpi_i_sabre_q2m_ops = {\n+\t.hw_params = snd_rpi_i_sabre_q2m_hw_params,\n+};\n+\n+SND_SOC_DAILINK_DEFS(rpi_i_sabre_q2m,\n+\tDAILINK_COMP_ARRAY(COMP_CPU(\"bcm2708-i2s.0\")),\n+\tDAILINK_COMP_ARRAY(COMP_CODEC(\"i-sabre-codec-i2c.1-0048\", \"i-sabre-codec-dai\")),\n+\tDAILINK_COMP_ARRAY(COMP_PLATFORM(\"bcm2708-i2s.0\")));\n+\n+static struct snd_soc_dai_link snd_rpi_i_sabre_q2m_dai[] = {\n+\t{\n+\t\t.name           = \"I-Sabre Q2M\",\n+\t\t.stream_name    = \"I-Sabre Q2M DAC\",\n+\t\t.dai_fmt        = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF\n+\t\t\t\t\t\t| SND_SOC_DAIFMT_CBS_CFS,\n+\t\t.init           = snd_rpi_i_sabre_q2m_init,\n+\t\t.ops            = &snd_rpi_i_sabre_q2m_ops,\n+\t\tSND_SOC_DAILINK_REG(rpi_i_sabre_q2m),\n+\t}\n+};\n+\n+/* audio machine driver */\n+static struct snd_soc_card snd_rpi_i_sabre_q2m = {\n+\t.name      = \"I-Sabre Q2M DAC\",\n+\t.owner     = THIS_MODULE,\n+\t.dai_link  = snd_rpi_i_sabre_q2m_dai,\n+\t.num_links = ARRAY_SIZE(snd_rpi_i_sabre_q2m_dai)\n+};\n+\n+\n+static int snd_rpi_i_sabre_q2m_probe(struct platform_device *pdev)\n+{\n+\tint ret = 0;\n+\n+\tsnd_rpi_i_sabre_q2m.dev = &pdev->dev;\n+\tif (pdev->dev.of_node) {\n+\t\tstruct device_node *i2s_node;\n+\t\tstruct snd_soc_dai_link *dai;\n+\n+\t\tdai = &snd_rpi_i_sabre_q2m_dai[0];\n+\t\ti2s_node = of_parse_phandle(pdev->dev.of_node,\n+\t\t\t\t\t\t\t\"i2s-controller\", 0);\n+\t\tif (i2s_node) {\n+\t\t\tdai->cpus->dai_name     = NULL;\n+\t\t\tdai->cpus->of_node      = i2s_node;\n+\t\t\tdai->platforms->name    = NULL;\n+\t\t\tdai->platforms->of_node = i2s_node;\n+\t\t} else {\n+\t\t\tdev_err(&pdev->dev,\n+\t\t\t    \"Property 'i2s-controller' missing or invalid\\n\");\n+\t\t\treturn (-EINVAL);\n+\t\t}\n+\n+\t\tdai->name        = \"I-Sabre Q2M\";\n+\t\tdai->stream_name = \"I-Sabre Q2M DAC\";\n+\t\tdai->dai_fmt     = SND_SOC_DAIFMT_I2S\n+\t\t\t\t\t| SND_SOC_DAIFMT_NB_NF\n+\t\t\t\t\t| SND_SOC_DAIFMT_CBS_CFS;\n+\t}\n+\n+\t/* Wait for registering codec driver */\n+\tmdelay(50);\n+\n+\tret = snd_soc_register_card(&snd_rpi_i_sabre_q2m);\n+\tif (ret) {\n+\t\tdev_err(&pdev->dev,\n+\t\t\t\"snd_soc_register_card() failed: %d\\n\", ret);\n+\t}\n+\n+\treturn ret;\n+}\n+\n+static int snd_rpi_i_sabre_q2m_remove(struct platform_device *pdev)\n+{\n+\treturn snd_soc_unregister_card(&snd_rpi_i_sabre_q2m);\n+}\n+\n+static const struct of_device_id snd_rpi_i_sabre_q2m_of_match[] = {\n+\t{ .compatible = \"audiophonics,i-sabre-q2m\", },\n+\t{}\n+};\n+MODULE_DEVICE_TABLE(of, snd_rpi_i_sabre_q2m_of_match);\n+\n+static struct platform_driver snd_rpi_i_sabre_q2m_driver = {\n+\t.driver = {\n+\t\t.name           = \"snd-rpi-i-sabre-q2m\",\n+\t\t.owner          = THIS_MODULE,\n+\t\t.of_match_table = snd_rpi_i_sabre_q2m_of_match,\n+\t},\n+\t.probe  = snd_rpi_i_sabre_q2m_probe,\n+\t.remove = snd_rpi_i_sabre_q2m_remove,\n+};\n+module_platform_driver(snd_rpi_i_sabre_q2m_driver);\n+\n+MODULE_DESCRIPTION(\"ASoC Driver for I-Sabre Q2M\");\n+MODULE_AUTHOR(\"Audiophonics <http://www.audiophonics.fr>\");\n+MODULE_LICENSE(\"GPL\");\n--- /dev/null\n+++ b/sound/soc/bcm/iqaudio-codec.c\n@@ -0,0 +1,274 @@\n+/*\n+ * ASoC Driver for IQaudIO Raspberry Pi Codec board\n+ *\n+ * Author:\tGordon Garrity <gordon@iqaudio.com>\n+ *\t\t(C) Copyright IQaudio Limited, 2017-2019\n+ *\n+ * This program is free software; you can redistribute it and/or\n+ * modify it under the terms of the GNU General Public License\n+ * version 2 as published by the Free Software Foundation.\n+ *\n+ * This program is distributed in the hope that it will be useful, but\n+ * WITHOUT ANY WARRANTY; without even the implied warranty of\n+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\n+ * General Public License for more details.\n+ */\n+\n+#include <linux/module.h>\n+#include <linux/gpio/consumer.h>\n+#include <linux/platform_device.h>\n+\n+#include <sound/core.h>\n+#include <sound/pcm.h>\n+#include <sound/pcm_params.h>\n+#include <sound/soc.h>\n+#include <sound/jack.h>\n+\n+#include <linux/acpi.h>\n+#include <linux/slab.h>\n+#include \"../codecs/da7213.h\"\n+\n+static int pll_out = DA7213_PLL_FREQ_OUT_90316800;\n+\n+static int snd_rpi_iqaudio_pll_control(struct snd_soc_dapm_widget *w,\n+\t\t\t\t       struct snd_kcontrol *k, int  event)\n+{\n+\tint ret = 0;\n+\tstruct snd_soc_dapm_context *dapm = w->dapm;\n+\tstruct snd_soc_card *card = dapm->card;\n+\tstruct snd_soc_pcm_runtime *rtd =\n+\t\tsnd_soc_get_pcm_runtime(card, &card->dai_link[0]);\n+\tstruct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);\n+\n+\tif (SND_SOC_DAPM_EVENT_OFF(event)) {\n+\t\tret = snd_soc_dai_set_pll(codec_dai, 0, DA7213_SYSCLK_MCLK, 0,\n+\t\t\t\t\t  0);\n+\t\tif (ret)\n+\t\t\tdev_err(card->dev, \"Failed to bypass PLL: %d\\n\", ret);\n+\t\t/* Allow PLL time to bypass */\n+\t\tmsleep(100);\n+\t} else if (SND_SOC_DAPM_EVENT_ON(event)) {\n+\t\tret = snd_soc_dai_set_pll(codec_dai, 0, DA7213_SYSCLK_PLL, 0,\n+\t\t\t\t\t  pll_out);\n+\t\tif (ret)\n+\t\t\tdev_err(card->dev, \"Failed to enable PLL: %d\\n\", ret);\n+\t\t/* Allow PLL time to lock */\n+\t\tmsleep(100);\n+\t}\n+\n+\treturn ret;\n+}\n+\n+static int snd_rpi_iqaudio_post_dapm_event(struct snd_soc_dapm_widget *w,\n+                              struct snd_kcontrol *kcontrol,\n+                              int event)\n+{\n+     switch (event) {\n+     case SND_SOC_DAPM_POST_PMU:\n+           /* Delay for mic bias ramp */\n+           msleep(1000);\n+           break;\n+     default:\n+           break;\n+     }\n+\n+     return 0;\n+}\n+\n+static const struct snd_kcontrol_new dapm_controls[] = {\n+\tSOC_DAPM_PIN_SWITCH(\"HP Jack\"),\n+\tSOC_DAPM_PIN_SWITCH(\"MIC Jack\"),\n+\tSOC_DAPM_PIN_SWITCH(\"Onboard MIC\"),\n+\tSOC_DAPM_PIN_SWITCH(\"AUX Jack\"),\n+};\n+\n+static const struct snd_soc_dapm_widget dapm_widgets[] = {\n+\tSND_SOC_DAPM_HP(\"HP Jack\", NULL),\n+\tSND_SOC_DAPM_MIC(\"MIC Jack\", NULL),\n+\tSND_SOC_DAPM_MIC(\"Onboard MIC\", NULL),\n+\tSND_SOC_DAPM_LINE(\"AUX Jack\", NULL),\n+\tSND_SOC_DAPM_SUPPLY(\"PLL Control\", SND_SOC_NOPM, 0, 0,\n+\t\t\t    snd_rpi_iqaudio_pll_control,\n+\t\t\t    SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),\n+\tSND_SOC_DAPM_POST(\"Post Power Up Event\", snd_rpi_iqaudio_post_dapm_event),\n+};\n+\n+static const struct snd_soc_dapm_route audio_map[] = {\n+\t{\"HP Jack\", NULL, \"HPL\"},\n+\t{\"HP Jack\", NULL, \"HPR\"},\n+\t{\"HP Jack\", NULL, \"PLL Control\"},\n+\n+\t{\"AUXR\", NULL, \"AUX Jack\"},\n+\t{\"AUXL\", NULL, \"AUX Jack\"},\n+\t{\"AUX Jack\", NULL, \"PLL Control\"},\n+\n+\t/* Assume Mic1 is linked to Headset and Mic2 to on-board mic */\n+\t{\"MIC1\", NULL, \"MIC Jack\"},\n+\t{\"MIC Jack\", NULL, \"PLL Control\"},\n+\t{\"MIC2\", NULL, \"Onboard MIC\"},\n+\t{\"Onboard MIC\", NULL, \"PLL Control\"},\n+};\n+\n+/* machine stream operations */\n+\n+static int snd_rpi_iqaudio_codec_init(struct snd_soc_pcm_runtime *rtd)\n+{\n+\tstruct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);\n+\tstruct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);\n+\tint ret;\n+\n+\t/*\n+\t * Disable AUX Jack Pin by default to prevent PLL being enabled at\n+\t * startup. This avoids holding the PLL to a fixed SR config for\n+\t * subsequent streams.\n+\t *\n+\t * This pin can still be enabled later, as required by user-space.\n+\t */\n+\tsnd_soc_dapm_disable_pin(&rtd->card->dapm, \"AUX Jack\");\n+\tsnd_soc_dapm_sync(&rtd->card->dapm);\n+\n+\t/* Set bclk ratio to align with codec's BCLK rate */\n+\tret = snd_soc_dai_set_bclk_ratio(cpu_dai, 64);\n+\tif (ret) {\n+\t\tdev_err(rtd->dev, \"Failed to set CPU BLCK ratio\\n\");\n+\t\treturn ret;\n+\t}\n+\n+\t/* Set MCLK frequency to codec, onboard 11.2896MHz clock */\n+\treturn snd_soc_dai_set_sysclk(codec_dai, DA7213_CLKSRC_MCLK, 11289600,\n+\t\t\t\t      SND_SOC_CLOCK_OUT);\n+}\n+\n+static int snd_rpi_iqaudio_codec_hw_params(struct snd_pcm_substream *substream,\n+\t\t\t\t\t   struct snd_pcm_hw_params *params)\n+{\n+\tstruct snd_soc_pcm_runtime *rtd = substream->private_data;\n+\tunsigned int samplerate = params_rate(params);\n+\n+\tswitch (samplerate) {\n+\tcase  8000:\n+\tcase 16000:\n+\tcase 32000:\n+\tcase 48000:\n+\tcase 96000:\n+\t\tpll_out = DA7213_PLL_FREQ_OUT_98304000;\n+\t\treturn 0;\n+\tcase 44100:\n+\tcase 88200:\n+\t\tpll_out = DA7213_PLL_FREQ_OUT_90316800;\n+\t\treturn 0;\n+\tdefault:\n+\t\tdev_err(rtd->dev,\"Unsupported samplerate %d\\n\", samplerate);\n+\t\treturn -EINVAL;\n+\t}\n+}\n+\n+static const struct snd_soc_ops snd_rpi_iqaudio_codec_ops = {\n+\t.hw_params = snd_rpi_iqaudio_codec_hw_params,\n+};\n+\n+SND_SOC_DAILINK_DEFS(rpi_iqaudio,\n+\tDAILINK_COMP_ARRAY(COMP_CPU(\"bcm2708-i2s.0\")),\n+\tDAILINK_COMP_ARRAY(COMP_CODEC(\"da7213.1-001a\", \"da7213-hifi\")),\n+\tDAILINK_COMP_ARRAY(COMP_PLATFORM(\"bcm2835-i2s.0\")));\n+\n+static struct snd_soc_dai_link snd_rpi_iqaudio_codec_dai[] = {\n+{\n+\t.dai_fmt \t\t= SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |\n+\t\t\t\t  SND_SOC_DAIFMT_CBM_CFM,\n+\t.init\t\t\t= snd_rpi_iqaudio_codec_init,\n+\t.ops\t\t\t= &snd_rpi_iqaudio_codec_ops,\n+\t.symmetric_rates\t= 1,\n+\t.symmetric_channels\t= 1,\n+\t.symmetric_samplebits\t= 1,\n+\tSND_SOC_DAILINK_REG(rpi_iqaudio),\n+},\n+};\n+\n+/* audio machine driver */\n+static struct snd_soc_card snd_rpi_iqaudio_codec = {\n+\t.owner\t\t\t= THIS_MODULE,\n+\t.dai_link\t\t= snd_rpi_iqaudio_codec_dai,\n+\t.num_links\t\t= ARRAY_SIZE(snd_rpi_iqaudio_codec_dai),\n+\t.controls\t\t= dapm_controls,\n+\t.num_controls\t\t= ARRAY_SIZE(dapm_controls),\n+\t.dapm_widgets\t\t= dapm_widgets,\n+\t.num_dapm_widgets\t= ARRAY_SIZE(dapm_widgets),\n+\t.dapm_routes\t\t= audio_map,\n+\t.num_dapm_routes\t= ARRAY_SIZE(audio_map),\n+};\n+\n+static int snd_rpi_iqaudio_codec_probe(struct platform_device *pdev)\n+{\n+\tint ret = 0;\n+\n+\tsnd_rpi_iqaudio_codec.dev = &pdev->dev;\n+\n+\tif (pdev->dev.of_node) {\n+\t\tstruct device_node *i2s_node;\n+\t\tstruct snd_soc_card *card = &snd_rpi_iqaudio_codec;\n+\t\tstruct snd_soc_dai_link *dai = &snd_rpi_iqaudio_codec_dai[0];\n+\n+\t\ti2s_node = of_parse_phandle(pdev->dev.of_node,\n+\t\t\t\t\t    \"i2s-controller\", 0);\n+\t\tif (i2s_node) {\n+\t\t\tdai->cpus->dai_name = NULL;\n+\t\t\tdai->cpus->of_node = i2s_node;\n+\t\t\tdai->platforms->name = NULL;\n+\t\t\tdai->platforms->of_node = i2s_node;\n+\t\t}\n+\n+\t\tif (of_property_read_string(pdev->dev.of_node, \"card_name\",\n+\t\t\t\t\t    &card->name))\n+\t\t\tcard->name = \"IQaudIOCODEC\";\n+\n+\t\tif (of_property_read_string(pdev->dev.of_node, \"dai_name\",\n+\t\t\t\t\t    &dai->name))\n+\t\t\tdai->name = \"IQaudIO CODEC\";\n+\n+\t\tif (of_property_read_string(pdev->dev.of_node,\n+\t\t\t\t\t\"dai_stream_name\", &dai->stream_name))\n+\t\t\tdai->stream_name = \"IQaudIO CODEC HiFi v1.2\";\n+\n+\t}\n+\n+\tret = snd_soc_register_card(&snd_rpi_iqaudio_codec);\n+\tif (ret) {\n+\t\tif (ret != -EPROBE_DEFER)\n+\t\t\tdev_err(&pdev->dev,\n+\t\t\t\t\"snd_soc_register_card() failed: %d\\n\", ret);\n+\t\treturn ret;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int snd_rpi_iqaudio_codec_remove(struct platform_device *pdev)\n+{\n+\treturn snd_soc_unregister_card(&snd_rpi_iqaudio_codec);\n+}\n+\n+static const struct of_device_id iqaudio_of_match[] = {\n+\t{ .compatible = \"iqaudio,iqaudio-codec\", },\n+\t{},\n+};\n+\n+MODULE_DEVICE_TABLE(of, iqaudio_of_match);\n+\n+static struct platform_driver snd_rpi_iqaudio_codec_driver = {\n+\t.driver = {\n+\t\t.name   = \"snd-rpi-iqaudio-codec\",\n+\t\t.owner  = THIS_MODULE,\n+\t\t.of_match_table = iqaudio_of_match,\n+\t},\n+\t.probe          = snd_rpi_iqaudio_codec_probe,\n+\t.remove         = snd_rpi_iqaudio_codec_remove,\n+};\n+\n+\n+\n+module_platform_driver(snd_rpi_iqaudio_codec_driver);\n+\n+MODULE_AUTHOR(\"Gordon Garrity <gordon@iqaudio.com>\");\n+MODULE_DESCRIPTION(\"ASoC Driver for IQaudIO CODEC\");\n+MODULE_LICENSE(\"GPL v2\");\n--- /dev/null\n+++ b/sound/soc/bcm/iqaudio-dac.c\n@@ -0,0 +1,223 @@\n+/*\n+ * ASoC Driver for IQaudIO DAC\n+ *\n+ * Author:\tFlorian Meier <florian.meier@koalo.de>\n+ *\t\tCopyright 2013\n+ *\n+ * This program is free software; you can redistribute it and/or\n+ * modify it under the terms of the GNU General Public License\n+ * version 2 as published by the Free Software Foundation.\n+ *\n+ * This program is distributed in the hope that it will be useful, but\n+ * WITHOUT ANY WARRANTY; without even the implied warranty of\n+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\n+ * General Public License for more details.\n+ */\n+\n+#include <linux/module.h>\n+#include <linux/gpio/consumer.h>\n+#include <linux/platform_device.h>\n+\n+#include <sound/core.h>\n+#include <sound/pcm.h>\n+#include <sound/pcm_params.h>\n+#include <sound/soc.h>\n+#include <sound/jack.h>\n+\n+static bool digital_gain_0db_limit = true;\n+\n+static struct gpio_desc *mute_gpio;\n+\n+static int snd_rpi_iqaudio_dac_init(struct snd_soc_pcm_runtime *rtd)\n+{\n+\tif (digital_gain_0db_limit)\n+\t{\n+\t\tint ret;\n+\t\tstruct snd_soc_card *card = rtd->card;\n+\n+\t\tret = snd_soc_limit_volume(card, \"Digital Playback Volume\", 207);\n+\t\tif (ret < 0)\n+\t\t\tdev_warn(card->dev, \"Failed to set volume limit: %d\\n\", ret);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static void snd_rpi_iqaudio_gpio_mute(struct snd_soc_card *card)\n+{\n+\tif (mute_gpio) {\n+\t\tdev_info(card->dev, \"%s: muting amp using GPIO22\\n\",\n+\t\t\t __func__);\n+\t\tgpiod_set_value_cansleep(mute_gpio, 0);\n+\t}\n+}\n+\n+static void snd_rpi_iqaudio_gpio_unmute(struct snd_soc_card *card)\n+{\n+\tif (mute_gpio) {\n+\t\tdev_info(card->dev, \"%s: un-muting amp using GPIO22\\n\",\n+\t\t\t __func__);\n+\t\tgpiod_set_value_cansleep(mute_gpio, 1);\n+\t}\n+}\n+\n+static int snd_rpi_iqaudio_set_bias_level(struct snd_soc_card *card,\n+\tstruct snd_soc_dapm_context *dapm, enum snd_soc_bias_level level)\n+{\n+\tstruct snd_soc_pcm_runtime *rtd;\n+\tstruct snd_soc_dai *codec_dai;\n+\n+\trtd = snd_soc_get_pcm_runtime(card, &card->dai_link[0]);\n+\tcodec_dai = asoc_rtd_to_codec(rtd, 0);\n+\n+\tif (dapm->dev != codec_dai->dev)\n+\t\treturn 0;\n+\n+\tswitch (level) {\n+\tcase SND_SOC_BIAS_PREPARE:\n+\t\tif (dapm->bias_level != SND_SOC_BIAS_STANDBY)\n+\t\t\tbreak;\n+\n+\t\t/* UNMUTE AMP */\n+\t\tsnd_rpi_iqaudio_gpio_unmute(card);\n+\n+\t\tbreak;\n+\tcase SND_SOC_BIAS_STANDBY:\n+\t\tif (dapm->bias_level != SND_SOC_BIAS_PREPARE)\n+\t\t\tbreak;\n+\n+\t\t/* MUTE AMP */\n+\t\tsnd_rpi_iqaudio_gpio_mute(card);\n+\n+\t\tbreak;\n+\tdefault:\n+\t\tbreak;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+SND_SOC_DAILINK_DEFS(hifi,\n+        DAILINK_COMP_ARRAY(COMP_CPU(\"bcm2708-i2s.0\")),\n+        DAILINK_COMP_ARRAY(COMP_CODEC(\"pcm512x.1-004c\", \"pcm512x-hifi\")),\n+        DAILINK_COMP_ARRAY(COMP_PLATFORM(\"bcm2708-i2s.0\")));\n+\n+static struct snd_soc_dai_link snd_rpi_iqaudio_dac_dai[] = {\n+{\n+\t.dai_fmt\t= SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |\n+\t\t\t\tSND_SOC_DAIFMT_CBS_CFS,\n+\t.init\t\t= snd_rpi_iqaudio_dac_init,\n+\tSND_SOC_DAILINK_REG(hifi),\n+},\n+};\n+\n+/* audio machine driver */\n+static struct snd_soc_card snd_rpi_iqaudio_dac = {\n+\t.owner        = THIS_MODULE,\n+\t.dai_link     = snd_rpi_iqaudio_dac_dai,\n+\t.num_links    = ARRAY_SIZE(snd_rpi_iqaudio_dac_dai),\n+};\n+\n+static int snd_rpi_iqaudio_dac_probe(struct platform_device *pdev)\n+{\n+\tint ret = 0;\n+\tbool gpio_unmute = false;\n+\n+\tsnd_rpi_iqaudio_dac.dev = &pdev->dev;\n+\n+\tif (pdev->dev.of_node) {\n+\t\tstruct device_node *i2s_node;\n+\t\tstruct snd_soc_card *card = &snd_rpi_iqaudio_dac;\n+\t\tstruct snd_soc_dai_link *dai = &snd_rpi_iqaudio_dac_dai[0];\n+\t\tbool auto_gpio_mute = false;\n+\n+\t\ti2s_node = of_parse_phandle(pdev->dev.of_node,\n+\t\t\t\t\t    \"i2s-controller\", 0);\n+\t\tif (i2s_node) {\n+\t\t\tdai->cpus->dai_name = NULL;\n+\t\t\tdai->cpus->of_node = i2s_node;\n+\t\t\tdai->platforms->name = NULL;\n+\t\t\tdai->platforms->of_node = i2s_node;\n+\t\t}\n+\n+\t\tdigital_gain_0db_limit = !of_property_read_bool(\n+\t\t\tpdev->dev.of_node, \"iqaudio,24db_digital_gain\");\n+\n+\t\tif (of_property_read_string(pdev->dev.of_node, \"card_name\",\n+\t\t\t\t\t    &card->name))\n+\t\t\tcard->name = \"IQaudIODAC\";\n+\n+\t\tif (of_property_read_string(pdev->dev.of_node, \"dai_name\",\n+\t\t\t\t\t    &dai->name))\n+\t\t\tdai->name = \"IQaudIO DAC\";\n+\n+\t\tif (of_property_read_string(pdev->dev.of_node,\n+\t\t\t\t\t\"dai_stream_name\", &dai->stream_name))\n+\t\t\tdai->stream_name = \"IQaudIO DAC HiFi\";\n+\n+\t\t/* gpio_unmute - one time unmute amp using GPIO */\n+\t\tgpio_unmute = of_property_read_bool(pdev->dev.of_node,\n+\t\t\t\t\t\t    \"iqaudio-dac,unmute-amp\");\n+\n+\t\t/* auto_gpio_mute - mute/unmute amp using GPIO */\n+\t\tauto_gpio_mute = of_property_read_bool(pdev->dev.of_node,\n+\t\t\t\t\t\t\"iqaudio-dac,auto-mute-amp\");\n+\n+\t\tif (auto_gpio_mute || gpio_unmute) {\n+\t\t\tmute_gpio = devm_gpiod_get_optional(&pdev->dev, \"mute\",\n+\t\t\t\t\t\t\t    GPIOD_OUT_LOW);\n+\t\t\tif (IS_ERR(mute_gpio)) {\n+\t\t\t\tret = PTR_ERR(mute_gpio);\n+\t\t\t\tdev_err(&pdev->dev,\n+\t\t\t\t\t\"Failed to get mute gpio: %d\\n\", ret);\n+\t\t\t\treturn ret;\n+\t\t\t}\n+\n+\t\t\tif (auto_gpio_mute && mute_gpio)\n+\t\t\t\tsnd_rpi_iqaudio_dac.set_bias_level =\n+\t\t\t\t\t\tsnd_rpi_iqaudio_set_bias_level;\n+\t\t}\n+\t}\n+\n+\tret = snd_soc_register_card(&snd_rpi_iqaudio_dac);\n+\tif (ret) {\n+\t\tif (ret != -EPROBE_DEFER)\n+\t\t\tdev_err(&pdev->dev,\n+\t\t\t\t\"snd_soc_register_card() failed: %d\\n\", ret);\n+\t\treturn ret;\n+\t}\n+\n+\tif (gpio_unmute && mute_gpio)\n+\t\tsnd_rpi_iqaudio_gpio_unmute(&snd_rpi_iqaudio_dac);\n+\n+\treturn 0;\n+}\n+\n+static int snd_rpi_iqaudio_dac_remove(struct platform_device *pdev)\n+{\n+\tsnd_rpi_iqaudio_gpio_mute(&snd_rpi_iqaudio_dac);\n+\n+\treturn snd_soc_unregister_card(&snd_rpi_iqaudio_dac);\n+}\n+\n+static const struct of_device_id iqaudio_of_match[] = {\n+\t{ .compatible = \"iqaudio,iqaudio-dac\", },\n+\t{},\n+};\n+MODULE_DEVICE_TABLE(of, iqaudio_of_match);\n+\n+static struct platform_driver snd_rpi_iqaudio_dac_driver = {\n+\t.driver = {\n+\t\t.name   = \"snd-rpi-iqaudio-dac\",\n+\t\t.owner  = THIS_MODULE,\n+\t\t.of_match_table = iqaudio_of_match,\n+\t},\n+\t.probe          = snd_rpi_iqaudio_dac_probe,\n+\t.remove         = snd_rpi_iqaudio_dac_remove,\n+};\n+\n+module_platform_driver(snd_rpi_iqaudio_dac_driver);\n+\n+MODULE_AUTHOR(\"Florian Meier <florian.meier@koalo.de>\");\n+MODULE_DESCRIPTION(\"ASoC Driver for IQAudio DAC\");\n+MODULE_LICENSE(\"GPL v2\");\n--- /dev/null\n+++ b/sound/soc/bcm/justboom-both.c\n@@ -0,0 +1,266 @@\n+// SPDX-License-Identifier: GPL-2.0\n+/*\n+ * rpi--wm8804.c -- ALSA SoC Raspberry Pi soundcard.\n+ *\n+ * Authors: Johannes Krude <johannes@krude.de\n+ *\n+ * Driver for when connecting simultaneously justboom-digi and justboom-dac\n+ *\n+ * Based upon code from:\n+ * justboom-digi.c\n+ * by Milan Neskovic <info@justboom.co>\n+ * justboom-dac.c\n+ * by Milan Neskovic <info@justboom.co>\n+ *\n+ * This program is free software; you can redistribute it and/or\n+ * modify it under the terms of the GNU General Public License\n+ * version 2 as published by the Free Software Foundation.\n+ *\n+ * This program is distributed in the hope that it will be useful, but\n+ * WITHOUT ANY WARRANTY; without even the implied warranty of\n+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\n+ * General Public License for more details.\n+ */\n+\n+#include <linux/module.h>\n+#include <linux/platform_device.h>\n+\n+#include <sound/core.h>\n+#include <sound/pcm.h>\n+#include <sound/pcm_params.h>\n+#include <sound/soc.h>\n+#include <sound/jack.h>\n+\n+#include \"../codecs/wm8804.h\"\n+#include \"../codecs/pcm512x.h\"\n+\n+\n+static bool digital_gain_0db_limit = true;\n+\n+static int snd_rpi_justboom_both_init(struct snd_soc_pcm_runtime *rtd)\n+{\n+\tstruct snd_soc_component *digi = asoc_rtd_to_codec(rtd, 0)->component;\n+\tstruct snd_soc_component *dac = asoc_rtd_to_codec(rtd, 1)->component;\n+\n+\t/* enable  TX output */\n+\tsnd_soc_component_update_bits(digi, WM8804_PWRDN, 0x4, 0x0);\n+\n+\tsnd_soc_component_update_bits(dac, PCM512x_GPIO_EN, 0x08, 0x08);\n+\tsnd_soc_component_update_bits(dac, PCM512x_GPIO_OUTPUT_4, 0xf, 0x02);\n+\tsnd_soc_component_update_bits(dac, PCM512x_GPIO_CONTROL_1, 0x08, 0x08);\n+\n+\tif (digital_gain_0db_limit) {\n+\t\tint ret;\n+\t\tstruct snd_soc_card *card = rtd->card;\n+\n+\t\tret = snd_soc_limit_volume(card, \"Digital Playback Volume\",\n+\t\t\t\t\t\t\t\t\t207);\n+\t\tif (ret < 0)\n+\t\t\tdev_warn(card->dev, \"Failed to set volume limit: %d\\n\",\n+\t\t\t\t\t\t\t\t\tret);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int snd_rpi_justboom_both_hw_params(struct snd_pcm_substream *substream,\n+\t\t\t\t       struct snd_pcm_hw_params *params)\n+{\n+\tstruct snd_soc_pcm_runtime *rtd = substream->private_data;\n+\tstruct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);\n+\tstruct snd_soc_component *digi = asoc_rtd_to_codec(rtd, 0)->component;\n+\tstruct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);\n+\n+\tint sysclk = 27000000; /* This is fixed on this board */\n+\n+\tlong mclk_freq    = 0;\n+\tint mclk_div      = 1;\n+\tint sampling_freq = 1;\n+\n+\tint ret;\n+\n+\tint samplerate = params_rate(params);\n+\n+\tif (samplerate <= 96000) {\n+\t\tmclk_freq = samplerate*256;\n+\t\tmclk_div  = WM8804_MCLKDIV_256FS;\n+\t} else {\n+\t\tmclk_freq = samplerate*128;\n+\t\tmclk_div  = WM8804_MCLKDIV_128FS;\n+\t}\n+\n+\tswitch (samplerate) {\n+\tcase 32000:\n+\t\tsampling_freq = 0x03;\n+\t\tbreak;\n+\tcase 44100:\n+\t\tsampling_freq = 0x00;\n+\t\tbreak;\n+\tcase 48000:\n+\t\tsampling_freq = 0x02;\n+\t\tbreak;\n+\tcase 88200:\n+\t\tsampling_freq = 0x08;\n+\t\tbreak;\n+\tcase 96000:\n+\t\tsampling_freq = 0x0a;\n+\t\tbreak;\n+\tcase 176400:\n+\t\tsampling_freq = 0x0c;\n+\t\tbreak;\n+\tcase 192000:\n+\t\tsampling_freq = 0x0e;\n+\t\tbreak;\n+\tdefault:\n+\t\tdev_err(rtd->card->dev,\n+\t\t\"Failed to set WM8804 SYSCLK, unsupported samplerate %d\\n\",\n+\t\tsamplerate);\n+\t}\n+\n+\tsnd_soc_dai_set_clkdiv(codec_dai, WM8804_MCLK_DIV, mclk_div);\n+\tsnd_soc_dai_set_pll(codec_dai, 0, 0, sysclk, mclk_freq);\n+\n+\tret = snd_soc_dai_set_sysclk(codec_dai, WM8804_TX_CLKSRC_PLL,\n+\t\t\t\t\tsysclk, SND_SOC_CLOCK_OUT);\n+\tif (ret < 0) {\n+\t\tdev_err(rtd->card->dev,\n+\t\t\"Failed to set WM8804 SYSCLK: %d\\n\", ret);\n+\t\treturn ret;\n+\t}\n+\n+\t/* Enable TX output */\n+\tsnd_soc_component_update_bits(digi, WM8804_PWRDN, 0x4, 0x0);\n+\n+\t/* Power on */\n+\tsnd_soc_component_update_bits(digi, WM8804_PWRDN, 0x9, 0);\n+\n+\t/* set sampling frequency status bits */\n+\tsnd_soc_component_update_bits(digi, WM8804_SPDTX4, 0x0f, sampling_freq);\n+\n+\treturn snd_soc_dai_set_bclk_ratio(cpu_dai, 64);\n+}\n+\n+static int snd_rpi_justboom_both_startup(struct snd_pcm_substream *substream)\n+{\n+\tstruct snd_soc_pcm_runtime *rtd = substream->private_data;\n+\tstruct snd_soc_component *digi = asoc_rtd_to_codec(rtd, 0)->component;\n+\tstruct snd_soc_component *dac = asoc_rtd_to_codec(rtd, 1)->component;\n+\n+\t/* turn on digital output */\n+\tsnd_soc_component_update_bits(digi, WM8804_PWRDN, 0x3c, 0x00);\n+\n+\tsnd_soc_component_update_bits(dac, PCM512x_GPIO_CONTROL_1, 0x08, 0x08);\n+\n+\treturn 0;\n+}\n+\n+static void snd_rpi_justboom_both_shutdown(struct snd_pcm_substream *substream)\n+{\n+\tstruct snd_soc_pcm_runtime *rtd = substream->private_data;\n+\tstruct snd_soc_component *digi = asoc_rtd_to_codec(rtd, 0)->component;\n+\tstruct snd_soc_component *dac = asoc_rtd_to_codec(rtd, 1)->component;\n+\n+\tsnd_soc_component_update_bits(dac, PCM512x_GPIO_CONTROL_1, 0x08, 0x00);\n+\n+\t/* turn off output */\n+\tsnd_soc_component_update_bits(digi, WM8804_PWRDN, 0x3c, 0x3c);\n+}\n+\n+/* machine stream operations */\n+static struct snd_soc_ops snd_rpi_justboom_both_ops = {\n+\t.hw_params = snd_rpi_justboom_both_hw_params,\n+\t.startup   = snd_rpi_justboom_both_startup,\n+\t.shutdown  = snd_rpi_justboom_both_shutdown,\n+};\n+\n+SND_SOC_DAILINK_DEFS(rpi_justboom_both,\n+\tDAILINK_COMP_ARRAY(COMP_CPU(\"bcm2708-i2s.0\")),\n+\tDAILINK_COMP_ARRAY(COMP_CODEC(\"pcm512x.1-004d\", \"pcm512x-hifi\"),\n+\t\t\t   COMP_CODEC(\"wm8804.1-003b\", \"wm8804-spdif\")),\n+\tDAILINK_COMP_ARRAY(COMP_PLATFORM(\"bcm2708-i2s.0\")));\n+\n+static struct snd_soc_dai_link snd_rpi_justboom_both_dai[] = {\n+{\n+\t.name           = \"JustBoom Digi\",\n+\t.stream_name    = \"JustBoom Digi HiFi\",\n+\t.dai_fmt        = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |\n+\t\t\t\t\tSND_SOC_DAIFMT_CBM_CFM,\n+\t.ops            = &snd_rpi_justboom_both_ops,\n+\t.init           = snd_rpi_justboom_both_init,\n+\tSND_SOC_DAILINK_REG(rpi_justboom_both),\n+},\n+};\n+\n+/* audio machine driver */\n+static struct snd_soc_card snd_rpi_justboom_both = {\n+\t.name             = \"snd_rpi_justboom_both\",\n+\t.driver_name      = \"JustBoomBoth\",\n+\t.owner            = THIS_MODULE,\n+\t.dai_link         = snd_rpi_justboom_both_dai,\n+\t.num_links        = ARRAY_SIZE(snd_rpi_justboom_both_dai),\n+};\n+\n+static int snd_rpi_justboom_both_probe(struct platform_device *pdev)\n+{\n+\tint ret = 0;\n+\tstruct snd_soc_card *card = &snd_rpi_justboom_both;\n+\n+\tsnd_rpi_justboom_both.dev = &pdev->dev;\n+\n+\tif (pdev->dev.of_node) {\n+\t\tstruct device_node *i2s_node;\n+\t\tstruct snd_soc_dai_link *dai = &snd_rpi_justboom_both_dai[0];\n+\n+\t\ti2s_node = of_parse_phandle(pdev->dev.of_node,\n+\t\t\t\t\t    \"i2s-controller\", 0);\n+\n+\t\tif (i2s_node) {\n+\t\t\tint i;\n+\n+\t\t\tfor (i = 0; i < card->num_links; i++) {\n+\t\t\t\tdai->cpus->dai_name = NULL;\n+\t\t\t\tdai->cpus->of_node = i2s_node;\n+\t\t\t\tdai->platforms->name = NULL;\n+\t\t\t\tdai->platforms->of_node = i2s_node;\n+\t\t\t}\n+\t\t}\n+\n+\t\tdigital_gain_0db_limit = !of_property_read_bool(\n+\t\t\tpdev->dev.of_node, \"justboom,24db_digital_gain\");\n+\t}\n+\n+\tret = snd_soc_register_card(card);\n+\tif (ret && ret != -EPROBE_DEFER) {\n+\t\tdev_err(&pdev->dev,\n+\t\t\t\"snd_soc_register_card() failed: %d\\n\", ret);\n+\t}\n+\n+\treturn ret;\n+}\n+\n+static int snd_rpi_justboom_both_remove(struct platform_device *pdev)\n+{\n+\treturn snd_soc_unregister_card(&snd_rpi_justboom_both);\n+}\n+\n+static const struct of_device_id snd_rpi_justboom_both_of_match[] = {\n+\t{ .compatible = \"justboom,justboom-both\", },\n+\t{},\n+};\n+MODULE_DEVICE_TABLE(of, snd_rpi_justboom_both_of_match);\n+\n+static struct platform_driver snd_rpi_justboom_both_driver = {\n+\t.driver = {\n+\t\t.name   = \"snd-rpi-justboom-both\",\n+\t\t.owner  = THIS_MODULE,\n+\t\t.of_match_table = snd_rpi_justboom_both_of_match,\n+\t},\n+\t.probe          = snd_rpi_justboom_both_probe,\n+\t.remove         = snd_rpi_justboom_both_remove,\n+};\n+\n+module_platform_driver(snd_rpi_justboom_both_driver);\n+\n+MODULE_AUTHOR(\"Johannes Krude <johannes@krude.de>\");\n+MODULE_DESCRIPTION(\"ASoC Driver for simultaneous use of JustBoom PI Digi & DAC HAT Sound Cards\");\n+MODULE_LICENSE(\"GPL v2\");\n--- /dev/null\n+++ b/sound/soc/bcm/justboom-dac.c\n@@ -0,0 +1,147 @@\n+/*\n+ * ASoC Driver for JustBoom DAC Raspberry Pi HAT Sound Card\n+ *\n+ * Author:\tMilan Neskovic\n+ *\t\tCopyright 2016\n+ *\t\tbased on code by Daniel Matuschek <info@crazy-audio.com>\n+ *\t\tbased on code by Florian Meier <florian.meier@koalo.de>\n+ *\n+ * This program is free software; you can redistribute it and/or\n+ * modify it under the terms of the GNU General Public License\n+ * version 2 as published by the Free Software Foundation.\n+ *\n+ * This program is distributed in the hope that it will be useful, but\n+ * WITHOUT ANY WARRANTY; without even the implied warranty of\n+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\n+ * General Public License for more details.\n+ */\n+\n+#include <linux/module.h>\n+#include <linux/platform_device.h>\n+\n+#include <sound/core.h>\n+#include <sound/pcm.h>\n+#include <sound/pcm_params.h>\n+#include <sound/soc.h>\n+#include <sound/jack.h>\n+\n+#include \"../codecs/pcm512x.h\"\n+\n+static bool digital_gain_0db_limit = true;\n+\n+static int snd_rpi_justboom_dac_init(struct snd_soc_pcm_runtime *rtd)\n+{\n+\tstruct snd_soc_component *component = asoc_rtd_to_codec(rtd, 0)->component;\n+\tsnd_soc_component_update_bits(component, PCM512x_GPIO_EN, 0x08, 0x08);\n+\tsnd_soc_component_update_bits(component, PCM512x_GPIO_OUTPUT_4, 0xf, 0x02);\n+\tsnd_soc_component_update_bits(component, PCM512x_GPIO_CONTROL_1, 0x08,0x08);\n+\n+\tif (digital_gain_0db_limit)\n+\t{\n+\t\tint ret;\n+\t\tstruct snd_soc_card *card = rtd->card;\n+\n+\t\tret = snd_soc_limit_volume(card, \"Digital Playback Volume\", 207);\n+\t\tif (ret < 0)\n+\t\t\tdev_warn(card->dev, \"Failed to set volume limit: %d\\n\", ret);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int snd_rpi_justboom_dac_startup(struct snd_pcm_substream *substream) {\n+\tstruct snd_soc_pcm_runtime *rtd = substream->private_data;\n+\tstruct snd_soc_component *component = asoc_rtd_to_codec(rtd, 0)->component;\n+\tsnd_soc_component_update_bits(component, PCM512x_GPIO_CONTROL_1, 0x08,0x08);\n+\treturn 0;\n+}\n+\n+static void snd_rpi_justboom_dac_shutdown(struct snd_pcm_substream *substream) {\n+\tstruct snd_soc_pcm_runtime *rtd = substream->private_data;\n+\tstruct snd_soc_component *component = asoc_rtd_to_codec(rtd, 0)->component;\n+\tsnd_soc_component_update_bits(component, PCM512x_GPIO_CONTROL_1, 0x08,0x00);\n+}\n+\n+/* machine stream operations */\n+static struct snd_soc_ops snd_rpi_justboom_dac_ops = {\n+\t.startup = snd_rpi_justboom_dac_startup,\n+\t.shutdown = snd_rpi_justboom_dac_shutdown,\n+};\n+\n+SND_SOC_DAILINK_DEFS(hifi,\n+\tDAILINK_COMP_ARRAY(COMP_CPU(\"bcm2708-i2s.0\")),\n+\tDAILINK_COMP_ARRAY(COMP_CODEC(\"pcm512x.1-004d\", \"pcm512x-hifi\")),\n+\tDAILINK_COMP_ARRAY(COMP_PLATFORM(\"bcm2708-i2s.0\")));\n+\n+static struct snd_soc_dai_link snd_rpi_justboom_dac_dai[] = {\n+{\n+\t.name\t\t= \"JustBoom DAC\",\n+\t.stream_name\t= \"JustBoom DAC HiFi\",\n+\t.dai_fmt\t= SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |\n+\t\t\t\tSND_SOC_DAIFMT_CBS_CFS,\n+\t.ops\t\t= &snd_rpi_justboom_dac_ops,\n+\t.init\t\t= snd_rpi_justboom_dac_init,\n+\tSND_SOC_DAILINK_REG(hifi),\n+},\n+};\n+\n+/* audio machine driver */\n+static struct snd_soc_card snd_rpi_justboom_dac = {\n+\t.name         = \"snd_rpi_justboom_dac\",\n+\t.driver_name  = \"JustBoomDac\",\n+\t.owner        = THIS_MODULE,\n+\t.dai_link     = snd_rpi_justboom_dac_dai,\n+\t.num_links    = ARRAY_SIZE(snd_rpi_justboom_dac_dai),\n+};\n+\n+static int snd_rpi_justboom_dac_probe(struct platform_device *pdev)\n+{\n+\tint ret = 0;\n+\n+\tsnd_rpi_justboom_dac.dev = &pdev->dev;\n+\n+\tif (pdev->dev.of_node) {\n+\t    struct device_node *i2s_node;\n+\t    struct snd_soc_dai_link *dai = &snd_rpi_justboom_dac_dai[0];\n+\t    i2s_node = of_parse_phandle(pdev->dev.of_node,\n+\t\t\t\t\t\"i2s-controller\", 0);\n+\n+\t    if (i2s_node) {\n+\t\t\tdai->cpus->dai_name = NULL;\n+\t\t\tdai->cpus->of_node = i2s_node;\n+\t\t\tdai->platforms->name = NULL;\n+\t\t\tdai->platforms->of_node = i2s_node;\n+\t    }\n+\n+\t    digital_gain_0db_limit = !of_property_read_bool(\n+\t\t\tpdev->dev.of_node, \"justboom,24db_digital_gain\");\n+\t}\n+\n+\tret = devm_snd_soc_register_card(&pdev->dev, &snd_rpi_justboom_dac);\n+\tif (ret && ret != -EPROBE_DEFER)\n+\t\tdev_err(&pdev->dev,\n+\t\t\t\"snd_soc_register_card() failed: %d\\n\", ret);\n+\n+\treturn ret;\n+}\n+\n+static const struct of_device_id snd_rpi_justboom_dac_of_match[] = {\n+\t{ .compatible = \"justboom,justboom-dac\", },\n+\t{},\n+};\n+MODULE_DEVICE_TABLE(of, snd_rpi_justboom_dac_of_match);\n+\n+static struct platform_driver snd_rpi_justboom_dac_driver = {\n+\t.driver = {\n+\t\t.name   = \"snd-rpi-justboom-dac\",\n+\t\t.owner  = THIS_MODULE,\n+\t\t.of_match_table = snd_rpi_justboom_dac_of_match,\n+\t},\n+\t.probe          = snd_rpi_justboom_dac_probe,\n+};\n+\n+module_platform_driver(snd_rpi_justboom_dac_driver);\n+\n+MODULE_AUTHOR(\"Milan Neskovic <info@justboom.co>\");\n+MODULE_DESCRIPTION(\"ASoC Driver for JustBoom PI DAC HAT Sound Card\");\n+MODULE_LICENSE(\"GPL v2\");\n--- /dev/null\n+++ b/sound/soc/bcm/pisound.c\n@@ -0,0 +1,1238 @@\n+/*\n+ * Pisound Linux kernel module.\n+ * Copyright (C) 2016-2020  Vilniaus Blokas UAB, https://blokas.io/pisound\n+ *\n+ * This program is free software; you can redistribute it and/or\n+ * modify it under the terms of the GNU General Public License\n+ * as published by the Free Software Foundation; version 2 of the\n+ * License.\n+ *\n+ * This program is distributed in the hope that it will be useful,\n+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\n+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n+ * GNU General Public License for more details.\n+ *\n+ * You should have received a copy of the GNU General Public License\n+ * along with this program; if not, write to the Free Software\n+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,\n+ * MA  02110-1301, USA.\n+ */\n+\n+#include <linux/init.h>\n+#include <linux/module.h>\n+#include <linux/platform_device.h>\n+#include <linux/gpio.h>\n+#include <linux/kobject.h>\n+#include <linux/sysfs.h>\n+#include <linux/delay.h>\n+#include <linux/spi/spi.h>\n+#include <linux/interrupt.h>\n+#include <linux/kfifo.h>\n+#include <linux/jiffies.h>\n+\n+#include <sound/core.h>\n+#include <sound/pcm.h>\n+#include <sound/pcm_params.h>\n+#include <sound/soc.h>\n+#include <sound/jack.h>\n+#include <sound/rawmidi.h>\n+#include <sound/asequencer.h>\n+#include <sound/control.h>\n+\n+static int pisnd_spi_init(struct device *dev);\n+static void pisnd_spi_uninit(void);\n+\n+static void pisnd_spi_flush(void);\n+static void pisnd_spi_start(void);\n+static uint8_t pisnd_spi_recv(uint8_t *buffer, uint8_t length);\n+\n+typedef void (*pisnd_spi_recv_cb)(void *data);\n+static void pisnd_spi_set_callback(pisnd_spi_recv_cb cb, void *data);\n+\n+static const char *pisnd_spi_get_serial(void);\n+static const char *pisnd_spi_get_id(void);\n+static const char *pisnd_spi_get_fw_version(void);\n+static const char *pisnd_spi_get_hw_version(void);\n+\n+static int pisnd_midi_init(struct snd_card *card);\n+static void pisnd_midi_uninit(void);\n+\n+enum task_e {\n+\tTASK_PROCESS = 0,\n+};\n+\n+static void pisnd_schedule_process(enum task_e task);\n+\n+#define PISOUND_LOG_PREFIX \"pisound: \"\n+\n+#ifdef PISOUND_DEBUG\n+#\tdefine printd(...) pr_alert(PISOUND_LOG_PREFIX __VA_ARGS__)\n+#else\n+#\tdefine printd(...) do {} while (0)\n+#endif\n+\n+#define printe(...) pr_err(PISOUND_LOG_PREFIX __VA_ARGS__)\n+#define printi(...) pr_info(PISOUND_LOG_PREFIX __VA_ARGS__)\n+\n+static struct snd_rawmidi *g_rmidi;\n+static struct snd_rawmidi_substream *g_midi_output_substream;\n+\n+static int pisnd_output_open(struct snd_rawmidi_substream *substream)\n+{\n+\tg_midi_output_substream = substream;\n+\treturn 0;\n+}\n+\n+static int pisnd_output_close(struct snd_rawmidi_substream *substream)\n+{\n+\tg_midi_output_substream = NULL;\n+\treturn 0;\n+}\n+\n+static void pisnd_output_trigger(\n+\tstruct snd_rawmidi_substream *substream,\n+\tint up\n+\t)\n+{\n+\tif (substream != g_midi_output_substream) {\n+\t\tprinte(\"MIDI output trigger called for an unexpected stream!\");\n+\t\treturn;\n+\t}\n+\n+\tif (!up)\n+\t\treturn;\n+\n+\tpisnd_spi_start();\n+}\n+\n+static void pisnd_output_drain(struct snd_rawmidi_substream *substream)\n+{\n+\tpisnd_spi_flush();\n+}\n+\n+static int pisnd_input_open(struct snd_rawmidi_substream *substream)\n+{\n+\treturn 0;\n+}\n+\n+static int pisnd_input_close(struct snd_rawmidi_substream *substream)\n+{\n+\treturn 0;\n+}\n+\n+static void pisnd_midi_recv_callback(void *substream)\n+{\n+\tuint8_t data[128];\n+\tuint8_t n = 0;\n+\n+\twhile ((n = pisnd_spi_recv(data, sizeof(data)))) {\n+\t\tint res = snd_rawmidi_receive(substream, data, n);\n+\t\t(void)res;\n+\t\tprintd(\"midi recv %u bytes, res = %d\\n\", n, res);\n+\t}\n+}\n+\n+static void pisnd_input_trigger(struct snd_rawmidi_substream *substream, int up)\n+{\n+\tif (up) {\n+\t\tpisnd_spi_set_callback(pisnd_midi_recv_callback, substream);\n+\t\tpisnd_schedule_process(TASK_PROCESS);\n+\t} else {\n+\t\tpisnd_spi_set_callback(NULL, NULL);\n+\t}\n+}\n+\n+static struct snd_rawmidi_ops pisnd_output_ops = {\n+\t.open = pisnd_output_open,\n+\t.close = pisnd_output_close,\n+\t.trigger = pisnd_output_trigger,\n+\t.drain = pisnd_output_drain,\n+};\n+\n+static struct snd_rawmidi_ops pisnd_input_ops = {\n+\t.open = pisnd_input_open,\n+\t.close = pisnd_input_close,\n+\t.trigger = pisnd_input_trigger,\n+};\n+\n+static void pisnd_get_port_info(\n+\tstruct snd_rawmidi *rmidi,\n+\tint number,\n+\tstruct snd_seq_port_info *seq_port_info\n+\t)\n+{\n+\tseq_port_info->type =\n+\t\tSNDRV_SEQ_PORT_TYPE_MIDI_GENERIC |\n+\t\tSNDRV_SEQ_PORT_TYPE_HARDWARE |\n+\t\tSNDRV_SEQ_PORT_TYPE_PORT;\n+\tseq_port_info->midi_voices = 0;\n+}\n+\n+static struct snd_rawmidi_global_ops pisnd_global_ops = {\n+\t.get_port_info = pisnd_get_port_info,\n+};\n+\n+static int pisnd_midi_init(struct snd_card *card)\n+{\n+\tint err;\n+\n+\tg_midi_output_substream = NULL;\n+\n+\terr = snd_rawmidi_new(card, \"pisound MIDI\", 0, 1, 1, &g_rmidi);\n+\n+\tif (err < 0) {\n+\t\tprinte(\"snd_rawmidi_new failed: %d\\n\", err);\n+\t\treturn err;\n+\t}\n+\n+\tstrcpy(g_rmidi->name, \"pisound MIDI \");\n+\tstrcat(g_rmidi->name, pisnd_spi_get_serial());\n+\n+\tg_rmidi->info_flags =\n+\t\tSNDRV_RAWMIDI_INFO_OUTPUT |\n+\t\tSNDRV_RAWMIDI_INFO_INPUT |\n+\t\tSNDRV_RAWMIDI_INFO_DUPLEX;\n+\n+\tg_rmidi->ops = &pisnd_global_ops;\n+\n+\tg_rmidi->private_data = (void *)0;\n+\n+\tsnd_rawmidi_set_ops(\n+\t\tg_rmidi,\n+\t\tSNDRV_RAWMIDI_STREAM_OUTPUT,\n+\t\t&pisnd_output_ops\n+\t\t);\n+\n+\tsnd_rawmidi_set_ops(\n+\t\tg_rmidi,\n+\t\tSNDRV_RAWMIDI_STREAM_INPUT,\n+\t\t&pisnd_input_ops\n+\t\t);\n+\n+\treturn 0;\n+}\n+\n+static void pisnd_midi_uninit(void)\n+{\n+}\n+\n+static void *g_recvData;\n+static pisnd_spi_recv_cb g_recvCallback;\n+\n+#define FIFO_SIZE 4096\n+\n+static char g_serial_num[11];\n+static char g_id[25];\n+enum { MAX_VERSION_STR_LEN = 6 };\n+static char g_fw_version[MAX_VERSION_STR_LEN];\n+static char g_hw_version[MAX_VERSION_STR_LEN];\n+\n+static uint8_t g_ledFlashDuration;\n+static bool    g_ledFlashDurationChanged;\n+\n+DEFINE_KFIFO(spi_fifo_in,  uint8_t, FIFO_SIZE);\n+DEFINE_KFIFO(spi_fifo_out, uint8_t, FIFO_SIZE);\n+\n+static struct gpio_desc *data_available;\n+static struct gpio_desc *spi_reset;\n+\n+static struct spi_device *pisnd_spi_device;\n+\n+static struct workqueue_struct *pisnd_workqueue;\n+static struct work_struct pisnd_work_process;\n+\n+static void pisnd_work_handler(struct work_struct *work);\n+\n+static void spi_transfer(const uint8_t *txbuf, uint8_t *rxbuf, int len);\n+static uint16_t spi_transfer16(uint16_t val);\n+\n+static int pisnd_init_workqueues(void)\n+{\n+\tpisnd_workqueue = create_singlethread_workqueue(\"pisnd_workqueue\");\n+\tINIT_WORK(&pisnd_work_process, pisnd_work_handler);\n+\n+\treturn 0;\n+}\n+\n+static void pisnd_uninit_workqueues(void)\n+{\n+\tflush_workqueue(pisnd_workqueue);\n+\tdestroy_workqueue(pisnd_workqueue);\n+\n+\tpisnd_workqueue = NULL;\n+}\n+\n+static bool pisnd_spi_has_more(void)\n+{\n+\treturn gpiod_get_value(data_available);\n+}\n+\n+static void pisnd_schedule_process(enum task_e task)\n+{\n+\tif (pisnd_spi_device != NULL &&\n+\t\tpisnd_workqueue != NULL &&\n+\t\t!work_pending(&pisnd_work_process)\n+\t\t) {\n+\t\tprintd(\"schedule: has more = %d\\n\", pisnd_spi_has_more());\n+\t\tif (task == TASK_PROCESS)\n+\t\t\tqueue_work(pisnd_workqueue, &pisnd_work_process);\n+\t}\n+}\n+\n+static irqreturn_t data_available_interrupt_handler(int irq, void *dev_id)\n+{\n+\tif (irq == gpiod_to_irq(data_available) && pisnd_spi_has_more()) {\n+\t\tprintd(\"schedule from irq\\n\");\n+\t\tpisnd_schedule_process(TASK_PROCESS);\n+\t}\n+\n+\treturn IRQ_HANDLED;\n+}\n+\n+static uint16_t spi_transfer16(uint16_t val)\n+{\n+\tuint8_t txbuf[2];\n+\tuint8_t rxbuf[2];\n+\n+\tif (!pisnd_spi_device) {\n+\t\tprinte(\"pisnd_spi_device null, returning\\n\");\n+\t\treturn 0;\n+\t}\n+\n+\ttxbuf[0] = val >> 8;\n+\ttxbuf[1] = val & 0xff;\n+\n+\tspi_transfer(txbuf, rxbuf, sizeof(txbuf));\n+\n+\tprintd(\"received: %02x%02x\\n\", rxbuf[0], rxbuf[1]);\n+\n+\treturn (rxbuf[0] << 8) | rxbuf[1];\n+}\n+\n+static void spi_transfer(const uint8_t *txbuf, uint8_t *rxbuf, int len)\n+{\n+\tint err;\n+\tstruct spi_transfer transfer;\n+\tstruct spi_message msg;\n+\n+\tmemset(rxbuf, 0, len);\n+\n+\tif (!pisnd_spi_device) {\n+\t\tprinte(\"pisnd_spi_device null, returning\\n\");\n+\t\treturn;\n+\t}\n+\n+\tspi_message_init(&msg);\n+\n+\tmemset(&transfer, 0, sizeof(transfer));\n+\n+\ttransfer.tx_buf = txbuf;\n+\ttransfer.rx_buf = rxbuf;\n+\ttransfer.len = len;\n+\ttransfer.speed_hz = 150000;\n+\ttransfer.delay_usecs = 10;\n+\tspi_message_add_tail(&transfer, &msg);\n+\n+\terr = spi_sync(pisnd_spi_device, &msg);\n+\n+\tif (err < 0) {\n+\t\tprinte(\"spi_sync error %d\\n\", err);\n+\t\treturn;\n+\t}\n+\n+\tprintd(\"hasMore %d\\n\", pisnd_spi_has_more());\n+}\n+\n+static int spi_read_bytes(char *dst, size_t length, uint8_t *bytesRead)\n+{\n+\tuint16_t rx;\n+\tuint8_t size;\n+\tuint8_t i;\n+\n+\tmemset(dst, 0, length);\n+\t*bytesRead = 0;\n+\n+\trx = spi_transfer16(0);\n+\tif (!(rx >> 8))\n+\t\treturn -EINVAL;\n+\n+\tsize = rx & 0xff;\n+\n+\tif (size > length)\n+\t\treturn -EINVAL;\n+\n+\tfor (i = 0; i < size; ++i) {\n+\t\trx = spi_transfer16(0);\n+\t\tif (!(rx >> 8))\n+\t\t\treturn -EINVAL;\n+\n+\t\tdst[i] = rx & 0xff;\n+\t}\n+\n+\t*bytesRead = i;\n+\n+\treturn 0;\n+}\n+\n+static int spi_device_match(struct device *dev, const void *data)\n+{\n+\tstruct spi_device *spi = container_of(dev, struct spi_device, dev);\n+\n+\tprintd(\"      %s %s %dkHz %d bits mode=0x%02X\\n\",\n+\t\tspi->modalias, dev_name(dev), spi->max_speed_hz/1000,\n+\t\tspi->bits_per_word, spi->mode);\n+\n+\tif (strcmp(\"pisound-spi\", spi->modalias) == 0) {\n+\t\tprinti(\"\\tFound!\\n\");\n+\t\treturn 1;\n+\t}\n+\n+\tprinte(\"\\tNot found!\\n\");\n+\treturn 0;\n+}\n+\n+static struct spi_device *pisnd_spi_find_device(void)\n+{\n+\tstruct device *dev;\n+\n+\tprinti(\"Searching for spi device...\\n\");\n+\tdev = bus_find_device(&spi_bus_type, NULL, NULL, spi_device_match);\n+\tif (dev != NULL)\n+\t\treturn container_of(dev, struct spi_device, dev);\n+\telse\n+\t\treturn NULL;\n+}\n+\n+static void pisnd_work_handler(struct work_struct *work)\n+{\n+\tenum { TRANSFER_SIZE = 4 };\n+\tenum { PISOUND_OUTPUT_BUFFER_SIZE_MILLIBYTES = 127 * 1000 };\n+\tenum { MIDI_MILLIBYTES_PER_JIFFIE = (3125 * 1000) / HZ };\n+\tint out_buffer_used_millibytes = 0;\n+\tunsigned long now;\n+\tuint8_t val;\n+\tuint8_t txbuf[TRANSFER_SIZE];\n+\tuint8_t rxbuf[TRANSFER_SIZE];\n+\tuint8_t midibuf[TRANSFER_SIZE];\n+\tint i, n;\n+\tbool had_data;\n+\n+\tunsigned long last_transfer_at = jiffies;\n+\n+\tif (work == &pisnd_work_process) {\n+\t\tif (pisnd_spi_device == NULL)\n+\t\t\treturn;\n+\n+\t\tdo {\n+\t\t\tif (g_midi_output_substream &&\n+\t\t\t\tkfifo_avail(&spi_fifo_out) >= sizeof(midibuf)) {\n+\n+\t\t\t\tn = snd_rawmidi_transmit_peek(\n+\t\t\t\t\tg_midi_output_substream,\n+\t\t\t\t\tmidibuf, sizeof(midibuf)\n+\t\t\t\t);\n+\n+\t\t\t\tif (n > 0) {\n+\t\t\t\t\tfor (i = 0; i < n; ++i)\n+\t\t\t\t\t\tkfifo_put(\n+\t\t\t\t\t\t\t&spi_fifo_out,\n+\t\t\t\t\t\t\tmidibuf[i]\n+\t\t\t\t\t\t\t);\n+\t\t\t\t\tsnd_rawmidi_transmit_ack(\n+\t\t\t\t\t\tg_midi_output_substream,\n+\t\t\t\t\t\ti\n+\t\t\t\t\t\t);\n+\t\t\t\t}\n+\t\t\t}\n+\n+\t\t\thad_data = false;\n+\t\t\tmemset(txbuf, 0, sizeof(txbuf));\n+\t\t\tfor (i = 0; i < sizeof(txbuf) &&\n+\t\t\t\t((out_buffer_used_millibytes+1000 <\n+\t\t\t\tPISOUND_OUTPUT_BUFFER_SIZE_MILLIBYTES) ||\n+\t\t\t\tg_ledFlashDurationChanged);\n+\t\t\t\ti += 2) {\n+\n+\t\t\t\tval = 0;\n+\n+\t\t\t\tif (g_ledFlashDurationChanged) {\n+\t\t\t\t\ttxbuf[i+0] = 0xf0;\n+\t\t\t\t\ttxbuf[i+1] = g_ledFlashDuration;\n+\t\t\t\t\tg_ledFlashDuration = 0;\n+\t\t\t\t\tg_ledFlashDurationChanged = false;\n+\t\t\t\t} else if (kfifo_get(&spi_fifo_out, &val)) {\n+\t\t\t\t\ttxbuf[i+0] = 0x0f;\n+\t\t\t\t\ttxbuf[i+1] = val;\n+\t\t\t\t\tout_buffer_used_millibytes += 1000;\n+\t\t\t\t}\n+\t\t\t}\n+\n+\t\t\tspi_transfer(txbuf, rxbuf, sizeof(txbuf));\n+\t\t\t/* Estimate the Pisound's MIDI output buffer usage, so\n+\t\t\t * that we don't overflow it. Space in the buffer should\n+\t\t\t * be becoming available at the UART MIDI byte transfer\n+\t\t\t * rate.\n+\t\t\t */\n+\t\t\tnow = jiffies;\n+\t\t\tif (now != last_transfer_at) {\n+\t\t\t\tout_buffer_used_millibytes -=\n+\t\t\t\t\t(now - last_transfer_at) *\n+\t\t\t\t\tMIDI_MILLIBYTES_PER_JIFFIE;\n+\t\t\t\tif (out_buffer_used_millibytes < 0)\n+\t\t\t\t\tout_buffer_used_millibytes = 0;\n+\t\t\t\tlast_transfer_at = now;\n+\t\t\t}\n+\n+\t\t\tfor (i = 0; i < sizeof(rxbuf); i += 2) {\n+\t\t\t\tif (rxbuf[i]) {\n+\t\t\t\t\tkfifo_put(&spi_fifo_in, rxbuf[i+1]);\n+\t\t\t\t\tif (kfifo_len(&spi_fifo_in) > 16 &&\n+\t\t\t\t\t\tg_recvCallback)\n+\t\t\t\t\t\tg_recvCallback(g_recvData);\n+\t\t\t\t\thad_data = true;\n+\t\t\t\t}\n+\t\t\t}\n+\t\t} while (had_data\n+\t\t\t|| !kfifo_is_empty(&spi_fifo_out)\n+\t\t\t|| pisnd_spi_has_more()\n+\t\t\t|| g_ledFlashDurationChanged\n+\t\t\t|| out_buffer_used_millibytes != 0\n+\t\t\t);\n+\n+\t\tif (!kfifo_is_empty(&spi_fifo_in) && g_recvCallback)\n+\t\t\tg_recvCallback(g_recvData);\n+\t}\n+}\n+\n+static int pisnd_spi_gpio_init(struct device *dev)\n+{\n+\tspi_reset = gpiod_get_index(dev, \"reset\", 1, GPIOD_ASIS);\n+\tdata_available = gpiod_get_index(dev, \"data_available\", 0, GPIOD_ASIS);\n+\n+\tgpiod_direction_output(spi_reset, 1);\n+\tgpiod_direction_input(data_available);\n+\n+\t/* Reset the slave. */\n+\tgpiod_set_value(spi_reset, false);\n+\tmdelay(1);\n+\tgpiod_set_value(spi_reset, true);\n+\n+\t/* Give time for spi slave to start. */\n+\tmdelay(64);\n+\n+\treturn 0;\n+}\n+\n+static void pisnd_spi_gpio_uninit(void)\n+{\n+\tgpiod_set_value(spi_reset, false);\n+\tgpiod_put(spi_reset);\n+\tspi_reset = NULL;\n+\n+\tgpiod_put(data_available);\n+\tdata_available = NULL;\n+}\n+\n+static int pisnd_spi_gpio_irq_init(struct device *dev)\n+{\n+\treturn request_threaded_irq(\n+\t\tgpiod_to_irq(data_available), NULL,\n+\t\tdata_available_interrupt_handler,\n+\t\tIRQF_TIMER | IRQF_TRIGGER_RISING | IRQF_ONESHOT,\n+\t\t\"data_available_int\",\n+\t\tNULL\n+\t\t);\n+}\n+\n+static void pisnd_spi_gpio_irq_uninit(void)\n+{\n+\tfree_irq(gpiod_to_irq(data_available), NULL);\n+}\n+\n+static int spi_read_info(void)\n+{\n+\tuint16_t tmp;\n+\tuint8_t count;\n+\tuint8_t n;\n+\tuint8_t i;\n+\tuint8_t j;\n+\tchar buffer[257];\n+\tint ret;\n+\tchar *p;\n+\n+\tmemset(g_serial_num, 0, sizeof(g_serial_num));\n+\tmemset(g_fw_version, 0, sizeof(g_fw_version));\n+\tstrcpy(g_hw_version, \"1.0\"); // Assume 1.0 hw version.\n+\tmemset(g_id, 0, sizeof(g_id));\n+\n+\ttmp = spi_transfer16(0);\n+\n+\tif (!(tmp >> 8))\n+\t\treturn -EINVAL;\n+\n+\tcount = tmp & 0xff;\n+\n+\tfor (i = 0; i < count; ++i) {\n+\t\tmemset(buffer, 0, sizeof(buffer));\n+\t\tret = spi_read_bytes(buffer, sizeof(buffer)-1, &n);\n+\n+\t\tif (ret < 0)\n+\t\t\treturn ret;\n+\n+\t\tswitch (i) {\n+\t\tcase 0:\n+\t\t\tif (n != 2)\n+\t\t\t\treturn -EINVAL;\n+\n+\t\t\tsnprintf(\n+\t\t\t\tg_fw_version,\n+\t\t\t\tMAX_VERSION_STR_LEN,\n+\t\t\t\t\"%x.%02x\",\n+\t\t\t\tbuffer[0],\n+\t\t\t\tbuffer[1]\n+\t\t\t\t);\n+\n+\t\t\tg_fw_version[MAX_VERSION_STR_LEN-1] = '\\0';\n+\t\t\tbreak;\n+\t\tcase 3:\n+\t\t\tif (n != 2)\n+\t\t\t\treturn -EINVAL;\n+\n+\t\t\tsnprintf(\n+\t\t\t\tg_hw_version,\n+\t\t\t\tMAX_VERSION_STR_LEN,\n+\t\t\t\t\"%x.%x\",\n+\t\t\t\tbuffer[0],\n+\t\t\t\tbuffer[1]\n+\t\t\t);\n+\n+\t\t\tg_hw_version[MAX_VERSION_STR_LEN-1] = '\\0';\n+\t\t\tbreak;\n+\t\tcase 1:\n+\t\t\tif (n >= sizeof(g_serial_num))\n+\t\t\t\treturn -EINVAL;\n+\n+\t\t\tmemcpy(g_serial_num, buffer, sizeof(g_serial_num));\n+\t\t\tbreak;\n+\t\tcase 2:\n+\t\t\t{\n+\t\t\t\tif (n*2 >= sizeof(g_id))\n+\t\t\t\t\treturn -EINVAL;\n+\n+\t\t\t\tp = g_id;\n+\t\t\t\tfor (j = 0; j < n; ++j)\n+\t\t\t\t\tp += sprintf(p, \"%02x\", buffer[j]);\n+\n+\t\t\t\t*p = '\\0';\n+\t\t\t}\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int pisnd_spi_init(struct device *dev)\n+{\n+\tint ret;\n+\tstruct spi_device *spi;\n+\n+\tmemset(g_serial_num, 0, sizeof(g_serial_num));\n+\tmemset(g_id, 0, sizeof(g_id));\n+\tmemset(g_fw_version, 0, sizeof(g_fw_version));\n+\tmemset(g_hw_version, 0, sizeof(g_hw_version));\n+\n+\tspi = pisnd_spi_find_device();\n+\n+\tif (spi != NULL) {\n+\t\tprintd(\"initializing spi!\\n\");\n+\t\tpisnd_spi_device = spi;\n+\t\tret = spi_setup(pisnd_spi_device);\n+\t} else {\n+\t\tprinte(\"SPI device not found, deferring!\\n\");\n+\t\treturn -EPROBE_DEFER;\n+\t}\n+\n+\tret = pisnd_spi_gpio_init(dev);\n+\n+\tif (ret < 0) {\n+\t\tprinte(\"SPI GPIO init failed: %d\\n\", ret);\n+\t\tspi_dev_put(pisnd_spi_device);\n+\t\tpisnd_spi_device = NULL;\n+\t\tpisnd_spi_gpio_uninit();\n+\t\treturn ret;\n+\t}\n+\n+\tret = spi_read_info();\n+\n+\tif (ret < 0) {\n+\t\tprinte(\"Reading card info failed: %d\\n\", ret);\n+\t\tspi_dev_put(pisnd_spi_device);\n+\t\tpisnd_spi_device = NULL;\n+\t\tpisnd_spi_gpio_uninit();\n+\t\treturn ret;\n+\t}\n+\n+\t/* Flash the LEDs. */\n+\tspi_transfer16(0xf008);\n+\n+\tret = pisnd_spi_gpio_irq_init(dev);\n+\tif (ret < 0) {\n+\t\tprinte(\"SPI irq request failed: %d\\n\", ret);\n+\t\tspi_dev_put(pisnd_spi_device);\n+\t\tpisnd_spi_device = NULL;\n+\t\tpisnd_spi_gpio_irq_uninit();\n+\t\tpisnd_spi_gpio_uninit();\n+\t}\n+\n+\tret = pisnd_init_workqueues();\n+\tif (ret != 0) {\n+\t\tprinte(\"Workqueue initialization failed: %d\\n\", ret);\n+\t\tspi_dev_put(pisnd_spi_device);\n+\t\tpisnd_spi_device = NULL;\n+\t\tpisnd_spi_gpio_irq_uninit();\n+\t\tpisnd_spi_gpio_uninit();\n+\t\tpisnd_uninit_workqueues();\n+\t\treturn ret;\n+\t}\n+\n+\tif (pisnd_spi_has_more()) {\n+\t\tprintd(\"data is available, scheduling from init\\n\");\n+\t\tpisnd_schedule_process(TASK_PROCESS);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static void pisnd_spi_uninit(void)\n+{\n+\tpisnd_uninit_workqueues();\n+\n+\tspi_dev_put(pisnd_spi_device);\n+\tpisnd_spi_device = NULL;\n+\n+\tpisnd_spi_gpio_irq_uninit();\n+\tpisnd_spi_gpio_uninit();\n+}\n+\n+static void pisnd_spi_flash_leds(uint8_t duration)\n+{\n+\tg_ledFlashDuration = duration;\n+\tg_ledFlashDurationChanged = true;\n+\tprintd(\"schedule from spi_flash_leds\\n\");\n+\tpisnd_schedule_process(TASK_PROCESS);\n+}\n+\n+static void pisnd_spi_flush(void)\n+{\n+\twhile (!kfifo_is_empty(&spi_fifo_out)) {\n+\t\tpisnd_spi_start();\n+\t\tflush_workqueue(pisnd_workqueue);\n+\t}\n+}\n+\n+static void pisnd_spi_start(void)\n+{\n+\tprintd(\"schedule from spi_start\\n\");\n+\tpisnd_schedule_process(TASK_PROCESS);\n+}\n+\n+static uint8_t pisnd_spi_recv(uint8_t *buffer, uint8_t length)\n+{\n+\treturn kfifo_out(&spi_fifo_in, buffer, length);\n+}\n+\n+static void pisnd_spi_set_callback(pisnd_spi_recv_cb cb, void *data)\n+{\n+\tg_recvData = data;\n+\tg_recvCallback = cb;\n+}\n+\n+static const char *pisnd_spi_get_serial(void)\n+{\n+\treturn g_serial_num;\n+}\n+\n+static const char *pisnd_spi_get_id(void)\n+{\n+\treturn g_id;\n+}\n+\n+static const char *pisnd_spi_get_fw_version(void)\n+{\n+\treturn g_fw_version;\n+}\n+\n+static const char *pisnd_spi_get_hw_version(void)\n+{\n+\treturn g_hw_version;\n+}\n+\n+static const struct of_device_id pisound_of_match[] = {\n+\t{ .compatible = \"blokaslabs,pisound\", },\n+\t{ .compatible = \"blokaslabs,pisound-spi\", },\n+\t{},\n+};\n+\n+enum {\n+\tSWITCH = 0,\n+\tVOLUME = 1,\n+};\n+\n+static int pisnd_ctl_info(struct snd_kcontrol *kcontrol,\n+\tstruct snd_ctl_elem_info *uinfo)\n+{\n+\tif (kcontrol->private_value == SWITCH) {\n+\t\tuinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;\n+\t\tuinfo->count = 1;\n+\t\tuinfo->value.integer.min = 0;\n+\t\tuinfo->value.integer.max = 1;\n+\t\treturn 0;\n+\t} else if (kcontrol->private_value == VOLUME) {\n+\t\tuinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;\n+\t\tuinfo->count = 1;\n+\t\tuinfo->value.integer.min = 0;\n+\t\tuinfo->value.integer.max = 100;\n+\t\treturn 0;\n+\t}\n+\treturn -EINVAL;\n+}\n+\n+static int pisnd_ctl_get(struct snd_kcontrol *kcontrol,\n+\tstruct snd_ctl_elem_value *ucontrol)\n+{\n+\tif (kcontrol->private_value == SWITCH) {\n+\t\tucontrol->value.integer.value[0] = 1;\n+\t\treturn 0;\n+\t} else if (kcontrol->private_value == VOLUME) {\n+\t\tucontrol->value.integer.value[0] = 100;\n+\t\treturn 0;\n+\t}\n+\n+\treturn -EINVAL;\n+}\n+\n+static struct snd_kcontrol_new pisnd_ctl[] = {\n+\t{\n+\t\t.iface = SNDRV_CTL_ELEM_IFACE_MIXER,\n+\t\t.name = \"PCM Playback Switch\",\n+\t\t.index = 0,\n+\t\t.private_value = SWITCH,\n+\t\t.access = SNDRV_CTL_ELEM_ACCESS_READ,\n+\t\t.info = pisnd_ctl_info,\n+\t\t.get = pisnd_ctl_get,\n+\t},\n+\t{\n+\t\t.iface = SNDRV_CTL_ELEM_IFACE_MIXER,\n+\t\t.name = \"PCM Playback Volume\",\n+\t\t.index = 0,\n+\t\t.private_value = VOLUME,\n+\t\t.access = SNDRV_CTL_ELEM_ACCESS_READ,\n+\t\t.info = pisnd_ctl_info,\n+\t\t.get = pisnd_ctl_get,\n+\t},\n+};\n+\n+static int pisnd_ctl_init(struct snd_card *card)\n+{\n+\tint err, i;\n+\n+\tfor (i = 0; i < ARRAY_SIZE(pisnd_ctl); ++i) {\n+\t\terr = snd_ctl_add(card, snd_ctl_new1(&pisnd_ctl[i], NULL));\n+\t\tif (err < 0)\n+\t\t\treturn err;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int pisnd_ctl_uninit(void)\n+{\n+\treturn 0;\n+}\n+\n+static struct gpio_desc *osr0, *osr1, *osr2;\n+static struct gpio_desc *reset;\n+static struct gpio_desc *button;\n+\n+static int pisnd_hw_params(\n+\tstruct snd_pcm_substream *substream,\n+\tstruct snd_pcm_hw_params *params\n+\t)\n+{\n+\tstruct snd_soc_pcm_runtime *rtd = substream->private_data;\n+\tstruct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);\n+\n+\t/* Pisound runs on fixed 32 clock counts per channel,\n+\t * as generated by the master ADC.\n+\t */\n+\tsnd_soc_dai_set_bclk_ratio(cpu_dai, 32*2);\n+\n+\tprintd(\"rate   = %d\\n\", params_rate(params));\n+\tprintd(\"ch     = %d\\n\", params_channels(params));\n+\tprintd(\"bits   = %u\\n\",\n+\t\tsnd_pcm_format_physical_width(params_format(params)));\n+\tprintd(\"format = %d\\n\", params_format(params));\n+\n+\tgpiod_set_value(reset, false);\n+\n+\tswitch (params_rate(params)) {\n+\tcase 48000:\n+\t\tgpiod_set_value(osr0, true);\n+\t\tgpiod_set_value(osr1, false);\n+\t\tgpiod_set_value(osr2, false);\n+\t\tbreak;\n+\tcase 96000:\n+\t\tgpiod_set_value(osr0, true);\n+\t\tgpiod_set_value(osr1, false);\n+\t\tgpiod_set_value(osr2, true);\n+\t\tbreak;\n+\tcase 192000:\n+\t\tgpiod_set_value(osr0, true);\n+\t\tgpiod_set_value(osr1, true);\n+\t\tgpiod_set_value(osr2, true);\n+\t\tbreak;\n+\tdefault:\n+\t\tprinte(\"Unsupported rate %u!\\n\", params_rate(params));\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tgpiod_set_value(reset, true);\n+\n+\treturn 0;\n+}\n+\n+static unsigned int rates[3] = {\n+\t48000, 96000, 192000\n+};\n+\n+static struct snd_pcm_hw_constraint_list constraints_rates = {\n+\t.count = ARRAY_SIZE(rates),\n+\t.list = rates,\n+\t.mask = 0,\n+};\n+\n+static int pisnd_startup(struct snd_pcm_substream *substream)\n+{\n+\tint err = snd_pcm_hw_constraint_list(\n+\t\tsubstream->runtime,\n+\t\t0,\n+\t\tSNDRV_PCM_HW_PARAM_RATE,\n+\t\t&constraints_rates\n+\t\t);\n+\n+\tif (err < 0)\n+\t\treturn err;\n+\n+\terr = snd_pcm_hw_constraint_single(\n+\t\tsubstream->runtime,\n+\t\tSNDRV_PCM_HW_PARAM_CHANNELS,\n+\t\t2\n+\t\t);\n+\n+\tif (err < 0)\n+\t\treturn err;\n+\n+\terr = snd_pcm_hw_constraint_mask64(\n+\t\tsubstream->runtime,\n+\t\tSNDRV_PCM_HW_PARAM_FORMAT,\n+\t\tSNDRV_PCM_FMTBIT_S16_LE |\n+\t\tSNDRV_PCM_FMTBIT_S24_LE |\n+\t\tSNDRV_PCM_FMTBIT_S32_LE\n+\t\t);\n+\n+\tif (err < 0)\n+\t\treturn err;\n+\n+\treturn 0;\n+}\n+\n+static struct snd_soc_ops pisnd_ops = {\n+\t.startup = pisnd_startup,\n+\t.hw_params = pisnd_hw_params,\n+};\n+\n+SND_SOC_DAILINK_DEFS(pisnd,\n+\tDAILINK_COMP_ARRAY(COMP_CPU(\"bcm2708-i2s.0\")),\n+\tDAILINK_COMP_ARRAY(COMP_DUMMY()),\n+\tDAILINK_COMP_ARRAY(COMP_PLATFORM(\"bcm2708-i2s.0\")));\n+\n+static struct snd_soc_dai_link pisnd_dai[] = {\n+\t{\n+\t\t.name           = \"pisound\",\n+\t\t.stream_name    = \"pisound\",\n+\t\t.dai_fmt        =\n+\t\t\tSND_SOC_DAIFMT_I2S |\n+\t\t\tSND_SOC_DAIFMT_NB_NF |\n+\t\t\tSND_SOC_DAIFMT_CBM_CFM,\n+\t\t.ops            = &pisnd_ops,\n+\t\tSND_SOC_DAILINK_REG(pisnd),\n+\t},\n+};\n+\n+static int pisnd_card_probe(struct snd_soc_card *card)\n+{\n+\tint err = pisnd_midi_init(card->snd_card);\n+\n+\tif (err < 0) {\n+\t\tprinte(\"pisnd_midi_init failed: %d\\n\", err);\n+\t\treturn err;\n+\t}\n+\n+\terr = pisnd_ctl_init(card->snd_card);\n+\tif (err < 0) {\n+\t\tprinte(\"pisnd_ctl_init failed: %d\\n\", err);\n+\t\treturn err;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int pisnd_card_remove(struct snd_soc_card *card)\n+{\n+\tpisnd_ctl_uninit();\n+\tpisnd_midi_uninit();\n+\treturn 0;\n+}\n+\n+static struct snd_soc_card pisnd_card = {\n+\t.name         = \"pisound\",\n+\t.owner        = THIS_MODULE,\n+\t.dai_link     = pisnd_dai,\n+\t.num_links    = ARRAY_SIZE(pisnd_dai),\n+\t.probe        = pisnd_card_probe,\n+\t.remove       = pisnd_card_remove,\n+};\n+\n+static int pisnd_init_gpio(struct device *dev)\n+{\n+\tosr0 = gpiod_get_index(dev, \"osr\", 0, GPIOD_ASIS);\n+\tosr1 = gpiod_get_index(dev, \"osr\", 1, GPIOD_ASIS);\n+\tosr2 = gpiod_get_index(dev, \"osr\", 2, GPIOD_ASIS);\n+\n+\treset = gpiod_get_index(dev, \"reset\", 0, GPIOD_ASIS);\n+\n+\tbutton = gpiod_get_index(dev, \"button\", 0, GPIOD_ASIS);\n+\n+\tgpiod_direction_output(osr0,  1);\n+\tgpiod_direction_output(osr1,  1);\n+\tgpiod_direction_output(osr2,  1);\n+\tgpiod_direction_output(reset, 1);\n+\n+\tgpiod_set_value(reset, false);\n+\tgpiod_set_value(osr0,   true);\n+\tgpiod_set_value(osr1,  false);\n+\tgpiod_set_value(osr2,  false);\n+\tgpiod_set_value(reset,  true);\n+\n+\tgpiod_export(button, false);\n+\n+\treturn 0;\n+}\n+\n+static int pisnd_uninit_gpio(void)\n+{\n+\tint i;\n+\n+\tstruct gpio_desc **gpios[] = {\n+\t\t&osr0, &osr1, &osr2, &reset, &button,\n+\t};\n+\n+\tgpiod_unexport(button);\n+\n+\tfor (i = 0; i < ARRAY_SIZE(gpios); ++i) {\n+\t\tif (*gpios[i] == NULL) {\n+\t\t\tprintd(\"weird, GPIO[%d] is NULL already\\n\", i);\n+\t\t\tcontinue;\n+\t\t}\n+\n+\t\tgpiod_put(*gpios[i]);\n+\t\t*gpios[i] = NULL;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static struct kobject *pisnd_kobj;\n+\n+static ssize_t pisnd_serial_show(\n+\tstruct kobject *kobj,\n+\tstruct kobj_attribute *attr,\n+\tchar *buf\n+\t)\n+{\n+\treturn sprintf(buf, \"%s\\n\", pisnd_spi_get_serial());\n+}\n+\n+static ssize_t pisnd_id_show(\n+\tstruct kobject *kobj,\n+\tstruct kobj_attribute *attr,\n+\tchar *buf\n+\t)\n+{\n+\treturn sprintf(buf, \"%s\\n\", pisnd_spi_get_id());\n+}\n+\n+static ssize_t pisnd_fw_version_show(\n+\tstruct kobject *kobj,\n+\tstruct kobj_attribute *attr,\n+\tchar *buf\n+\t)\n+{\n+\treturn sprintf(buf, \"%s\\n\", pisnd_spi_get_fw_version());\n+}\n+\n+static ssize_t pisnd_hw_version_show(\n+\tstruct kobject *kobj,\n+\tstruct kobj_attribute *attr,\n+\tchar *buf\n+)\n+{\n+\treturn sprintf(buf, \"%s\\n\", pisnd_spi_get_hw_version());\n+}\n+\n+static ssize_t pisnd_led_store(\n+\tstruct kobject *kobj,\n+\tstruct kobj_attribute *attr,\n+\tconst char *buf,\n+\tsize_t length\n+\t)\n+{\n+\tuint32_t timeout;\n+\tint err;\n+\n+\terr = kstrtou32(buf, 10, &timeout);\n+\n+\tif (err == 0 && timeout <= 255)\n+\t\tpisnd_spi_flash_leds(timeout);\n+\n+\treturn length;\n+}\n+\n+static struct kobj_attribute pisnd_serial_attribute =\n+\t__ATTR(serial, 0444, pisnd_serial_show, NULL);\n+static struct kobj_attribute pisnd_id_attribute =\n+\t__ATTR(id, 0444, pisnd_id_show, NULL);\n+static struct kobj_attribute pisnd_fw_version_attribute =\n+\t__ATTR(version, 0444, pisnd_fw_version_show, NULL);\n+static struct kobj_attribute pisnd_hw_version_attribute =\n+__ATTR(hw_version, 0444, pisnd_hw_version_show, NULL);\n+static struct kobj_attribute pisnd_led_attribute =\n+\t__ATTR(led, 0644, NULL, pisnd_led_store);\n+\n+static struct attribute *attrs[] = {\n+\t&pisnd_serial_attribute.attr,\n+\t&pisnd_id_attribute.attr,\n+\t&pisnd_fw_version_attribute.attr,\n+\t&pisnd_hw_version_attribute.attr,\n+\t&pisnd_led_attribute.attr,\n+\tNULL\n+};\n+\n+static struct attribute_group attr_group = { .attrs = attrs };\n+\n+static int pisnd_probe(struct platform_device *pdev)\n+{\n+\tint ret = 0;\n+\tint i;\n+\n+\tret = pisnd_spi_init(&pdev->dev);\n+\tif (ret < 0) {\n+\t\tprinte(\"pisnd_spi_init failed: %d\\n\", ret);\n+\t\treturn ret;\n+\t}\n+\n+\tprinti(\"Detected Pisound card:\\n\");\n+\tprinti(\"\\tSerial:           %s\\n\", pisnd_spi_get_serial());\n+\tprinti(\"\\tFirmware Version: %s\\n\", pisnd_spi_get_fw_version());\n+\tprinti(\"\\tHardware Version: %s\\n\", pisnd_spi_get_hw_version());\n+\tprinti(\"\\tId:               %s\\n\", pisnd_spi_get_id());\n+\n+\tpisnd_kobj = kobject_create_and_add(\"pisound\", kernel_kobj);\n+\tif (!pisnd_kobj) {\n+\t\tpisnd_spi_uninit();\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\tret = sysfs_create_group(pisnd_kobj, &attr_group);\n+\tif (ret < 0) {\n+\t\tpisnd_spi_uninit();\n+\t\tkobject_put(pisnd_kobj);\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\tpisnd_init_gpio(&pdev->dev);\n+\tpisnd_card.dev = &pdev->dev;\n+\n+\tif (pdev->dev.of_node) {\n+\t\tstruct device_node *i2s_node;\n+\n+\t\ti2s_node = of_parse_phandle(\n+\t\t\tpdev->dev.of_node,\n+\t\t\t\"i2s-controller\",\n+\t\t\t0\n+\t\t\t);\n+\n+\t\tfor (i = 0; i < pisnd_card.num_links; ++i) {\n+\t\t\tstruct snd_soc_dai_link *dai = &pisnd_dai[i];\n+\n+\t\t\tif (i2s_node) {\n+\t\t\t\tdai->cpus->dai_name = NULL;\n+\t\t\t\tdai->cpus->of_node = i2s_node;\n+\t\t\t\tdai->platforms->name = NULL;\n+\t\t\t\tdai->platforms->of_node = i2s_node;\n+\t\t\t\tdai->stream_name = pisnd_spi_get_serial();\n+\t\t\t}\n+\t\t}\n+\t}\n+\n+\tret = snd_soc_register_card(&pisnd_card);\n+\n+\tif (ret < 0) {\n+\t\tif (ret != -EPROBE_DEFER)\n+\t\t\tprinte(\"snd_soc_register_card() failed: %d\\n\", ret);\n+\t\tpisnd_uninit_gpio();\n+\t\tkobject_put(pisnd_kobj);\n+\t\tpisnd_spi_uninit();\n+\t}\n+\n+\treturn ret;\n+}\n+\n+static int pisnd_remove(struct platform_device *pdev)\n+{\n+\tprinti(\"Unloading.\\n\");\n+\n+\tif (pisnd_kobj) {\n+\t\tkobject_put(pisnd_kobj);\n+\t\tpisnd_kobj = NULL;\n+\t}\n+\n+\tpisnd_spi_uninit();\n+\n+\t/* Turn off */\n+\tgpiod_set_value(reset, false);\n+\tpisnd_uninit_gpio();\n+\n+\treturn snd_soc_unregister_card(&pisnd_card);\n+}\n+\n+MODULE_DEVICE_TABLE(of, pisound_of_match);\n+\n+static struct platform_driver pisnd_driver = {\n+\t.driver = {\n+\t\t.name           = \"snd-rpi-pisound\",\n+\t\t.owner          = THIS_MODULE,\n+\t\t.of_match_table = pisound_of_match,\n+\t},\n+\t.probe              = pisnd_probe,\n+\t.remove             = pisnd_remove,\n+};\n+\n+module_platform_driver(pisnd_driver);\n+\n+MODULE_AUTHOR(\"Giedrius Trainavicius <giedrius@blokas.io>\");\n+MODULE_DESCRIPTION(\"ASoC Driver for Pisound, https://blokas.io/pisound\");\n+MODULE_LICENSE(\"GPL v2\");\n--- /dev/null\n+++ b/sound/soc/bcm/rpi-cirrus.c\n@@ -0,0 +1,1025 @@\n+/*\n+ * ASoC machine driver for Cirrus Logic Audio Card\n+ * (with WM5102 and WM8804 codecs)\n+ *\n+ * Copyright 2015-2017 Matthias Reichl <hias@horus.com>\n+ *\n+ * Based on rpi-cirrus-sound-pi driver (c) Wolfson / Cirrus Logic Inc.\n+ *\n+ * This program is free software; you can redistribute it and/or modify\n+ * it under the terms of the GNU General Public License version 2 as\n+ * published by the Free Software Foundation.\n+ */\n+\n+#include <linux/module.h>\n+#include <linux/mutex.h>\n+#include <linux/slab.h>\n+#include <linux/list.h>\n+#include <linux/delay.h>\n+#include <sound/pcm_params.h>\n+\n+#include <linux/mfd/arizona/registers.h>\n+\n+#include \"../codecs/wm5102.h\"\n+#include \"../codecs/wm8804.h\"\n+\n+#define WM8804_CLKOUT_HZ 12000000\n+\n+#define RPI_CIRRUS_DEFAULT_RATE 44100\n+#define WM5102_MAX_SYSCLK_1 49152000 /* max sysclk for 4K family */\n+#define WM5102_MAX_SYSCLK_2 45158400 /* max sysclk for 11.025K family */\n+\n+static inline unsigned int calc_sysclk(unsigned int rate)\n+{\n+\treturn (rate % 4000) ? WM5102_MAX_SYSCLK_2 : WM5102_MAX_SYSCLK_1;\n+}\n+\n+enum {\n+\tDAI_WM5102 = 0,\n+\tDAI_WM8804,\n+};\n+\n+struct rpi_cirrus_priv {\n+\t/* mutex for synchronzing FLL1 access with DAPM */\n+\tstruct mutex lock;\n+\tunsigned int card_rate;\n+\tint sync_path_enable;\n+\tint fll1_freq; /* negative means RefClock in spdif rx case */\n+\n+\t/* track hw params/free for substreams */\n+\tunsigned int params_set;\n+\tunsigned int min_rate_idx, max_rate_idx;\n+\tunsigned char iec958_status[4];\n+};\n+\n+/* helper functions */\n+static inline struct snd_soc_pcm_runtime *get_wm5102_runtime(\n+\tstruct snd_soc_card *card) {\n+\treturn snd_soc_get_pcm_runtime(card, &card->dai_link[DAI_WM5102]);\n+}\n+\n+static inline struct snd_soc_pcm_runtime *get_wm8804_runtime(\n+\tstruct snd_soc_card *card) {\n+\treturn snd_soc_get_pcm_runtime(card, &card->dai_link[DAI_WM8804]);\n+}\n+\n+\n+struct rate_info {\n+\tunsigned int value;\n+\tchar *text;\n+};\n+\n+static struct rate_info min_rates[] = {\n+\t{     0, \"off\"},\n+\t{ 32000, \"32kHz\"},\n+\t{ 44100, \"44.1kHz\"}\n+};\n+\n+#define NUM_MIN_RATES ARRAY_SIZE(min_rates)\n+\n+static int rpi_cirrus_min_rate_info(struct snd_kcontrol *kcontrol,\n+\tstruct snd_ctl_elem_info *uinfo)\n+{\n+\tuinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;\n+\tuinfo->count = 1;\n+\tuinfo->value.enumerated.items = NUM_MIN_RATES;\n+\n+\tif (uinfo->value.enumerated.item >= NUM_MIN_RATES)\n+\t\tuinfo->value.enumerated.item = NUM_MIN_RATES - 1;\n+\tstrcpy(uinfo->value.enumerated.name,\n+\t\tmin_rates[uinfo->value.enumerated.item].text);\n+\treturn 0;\n+}\n+\n+static int rpi_cirrus_min_rate_get(struct snd_kcontrol *kcontrol,\n+\tstruct snd_ctl_elem_value *ucontrol)\n+{\n+\tstruct snd_soc_card *card = snd_kcontrol_chip(kcontrol);\n+\tstruct rpi_cirrus_priv *priv = snd_soc_card_get_drvdata(card);\n+\n+\tucontrol->value.enumerated.item[0] = priv->min_rate_idx;\n+\treturn 0;\n+}\n+\n+static int rpi_cirrus_min_rate_put(struct snd_kcontrol *kcontrol,\n+\tstruct snd_ctl_elem_value *ucontrol)\n+{\n+\tstruct snd_soc_card *card = snd_kcontrol_chip(kcontrol);\n+\tstruct rpi_cirrus_priv *priv = snd_soc_card_get_drvdata(card);\n+\tint changed = 0;\n+\n+\tif (priv->min_rate_idx != ucontrol->value.enumerated.item[0]) {\n+\t\tchanged = 1;\n+\t\tpriv->min_rate_idx = ucontrol->value.enumerated.item[0];\n+\t}\n+\n+\treturn changed;\n+}\n+\n+static struct rate_info max_rates[] = {\n+\t{     0, \"off\"},\n+\t{ 48000, \"48kHz\"},\n+\t{ 96000, \"96kHz\"}\n+};\n+\n+#define NUM_MAX_RATES ARRAY_SIZE(max_rates)\n+\n+static int rpi_cirrus_max_rate_info(struct snd_kcontrol *kcontrol,\n+\tstruct snd_ctl_elem_info *uinfo)\n+{\n+\tuinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;\n+\tuinfo->count = 1;\n+\tuinfo->value.enumerated.items = NUM_MAX_RATES;\n+\tif (uinfo->value.enumerated.item >= NUM_MAX_RATES)\n+\t\tuinfo->value.enumerated.item = NUM_MAX_RATES - 1;\n+\tstrcpy(uinfo->value.enumerated.name,\n+\t\tmax_rates[uinfo->value.enumerated.item].text);\n+\treturn 0;\n+}\n+\n+static int rpi_cirrus_max_rate_get(struct snd_kcontrol *kcontrol,\n+\tstruct snd_ctl_elem_value *ucontrol)\n+{\n+\tstruct snd_soc_card *card = snd_kcontrol_chip(kcontrol);\n+\tstruct rpi_cirrus_priv *priv = snd_soc_card_get_drvdata(card);\n+\n+\tucontrol->value.enumerated.item[0] = priv->max_rate_idx;\n+\treturn 0;\n+}\n+\n+static int rpi_cirrus_max_rate_put(struct snd_kcontrol *kcontrol,\n+\tstruct snd_ctl_elem_value *ucontrol)\n+{\n+\tstruct snd_soc_card *card = snd_kcontrol_chip(kcontrol);\n+\tstruct rpi_cirrus_priv *priv = snd_soc_card_get_drvdata(card);\n+\tint changed = 0;\n+\n+\tif (priv->max_rate_idx != ucontrol->value.enumerated.item[0]) {\n+\t\tchanged = 1;\n+\t\tpriv->max_rate_idx = ucontrol->value.enumerated.item[0];\n+\t}\n+\n+\treturn changed;\n+}\n+\n+static int rpi_cirrus_spdif_info(struct snd_kcontrol *kcontrol,\n+\tstruct snd_ctl_elem_info *uinfo)\n+{\n+\tuinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;\n+\tuinfo->count = 1;\n+\treturn 0;\n+}\n+\n+static int rpi_cirrus_spdif_playback_get(struct snd_kcontrol *kcontrol,\n+\tstruct snd_ctl_elem_value *ucontrol)\n+{\n+\tstruct snd_soc_card *card = snd_kcontrol_chip(kcontrol);\n+\tstruct rpi_cirrus_priv *priv = snd_soc_card_get_drvdata(card);\n+\tint i;\n+\n+\tfor (i = 0; i < 4; i++)\n+\t\tucontrol->value.iec958.status[i] = priv->iec958_status[i];\n+\n+\treturn 0;\n+}\n+\n+static int rpi_cirrus_spdif_playback_put(struct snd_kcontrol *kcontrol,\n+\tstruct snd_ctl_elem_value *ucontrol)\n+{\n+\tstruct snd_soc_card *card = snd_kcontrol_chip(kcontrol);\n+\tstruct snd_soc_component *wm8804_component =\n+\t\tasoc_rtd_to_codec(get_wm8804_runtime(card), 0)->component;\n+\tstruct rpi_cirrus_priv *priv = snd_soc_card_get_drvdata(card);\n+\tunsigned char *stat = priv->iec958_status;\n+\tunsigned char *ctrl_stat = ucontrol->value.iec958.status;\n+\tunsigned int mask;\n+\tint i, changed = 0;\n+\n+\tfor (i = 0; i < 4; i++) {\n+\t\tmask = (i == 3) ? 0x3f : 0xff;\n+\t\tif ((ctrl_stat[i] & mask) != (stat[i] & mask)) {\n+\t\t\tchanged = 1;\n+\t\t\tstat[i] = ctrl_stat[i] & mask;\n+\t\t\tsnd_soc_component_update_bits(wm8804_component,\n+\t\t\t\tWM8804_SPDTX1 + i, mask, stat[i]);\n+\t\t}\n+\t}\n+\n+\treturn changed;\n+}\n+\n+static int rpi_cirrus_spdif_mask_get(struct snd_kcontrol *kcontrol,\n+\tstruct snd_ctl_elem_value *ucontrol)\n+{\n+\tucontrol->value.iec958.status[0] = 0xff;\n+\tucontrol->value.iec958.status[1] = 0xff;\n+\tucontrol->value.iec958.status[2] = 0xff;\n+\tucontrol->value.iec958.status[3] = 0x3f;\n+\n+\treturn 0;\n+}\n+\n+static int rpi_cirrus_spdif_capture_get(struct snd_kcontrol *kcontrol,\n+\tstruct snd_ctl_elem_value *ucontrol)\n+{\n+\tstruct snd_soc_card *card = snd_kcontrol_chip(kcontrol);\n+\tstruct snd_soc_component *wm8804_component =\n+\t\tasoc_rtd_to_codec(get_wm8804_runtime(card), 0)->component;\n+\tunsigned int val, mask;\n+\tint i;\n+\n+\tfor (i = 0; i < 4; i++) {\n+\t\tval = snd_soc_component_read(wm8804_component,\n+\t\t\tWM8804_RXCHAN1 + i);\n+\t\tmask = (i == 3) ? 0x3f : 0xff;\n+\t\tucontrol->value.iec958.status[i] = val & mask;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+#define SPDIF_FLAG_CTRL(desc, reg, bit, invert) \\\n+{ \\\n+\t\t.access =  SNDRV_CTL_ELEM_ACCESS_READ \\\n+\t\t\t   | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \\\n+\t\t.iface =   SNDRV_CTL_ELEM_IFACE_MIXER, \\\n+\t\t.name =    SNDRV_CTL_NAME_IEC958(\"\", CAPTURE, NONE) \\\n+\t\t\t\tdesc \" Flag\", \\\n+\t\t.info =    snd_ctl_boolean_mono_info, \\\n+\t\t.get =     rpi_cirrus_spdif_status_flag_get, \\\n+\t\t.private_value = \\\n+\t\t\t(bit) | ((reg) << 8) | ((invert) << 16) \\\n+}\n+\n+static int rpi_cirrus_spdif_status_flag_get(struct snd_kcontrol *kcontrol,\n+\tstruct snd_ctl_elem_value *ucontrol)\n+{\n+\tstruct snd_soc_card *card = snd_kcontrol_chip(kcontrol);\n+\tstruct snd_soc_component *wm8804_component =\n+\t\tasoc_rtd_to_codec(get_wm8804_runtime(card), 0)->component;\n+\n+\tunsigned int bit = kcontrol->private_value & 0xff;\n+\tunsigned int reg = (kcontrol->private_value >> 8) & 0xff;\n+\tunsigned int invert = (kcontrol->private_value >> 16) & 0xff;\n+\tunsigned int val;\n+\tbool flag;\n+\n+\tval = snd_soc_component_read(wm8804_component, reg);\n+\n+\tflag = val & (1 << bit);\n+\n+\tucontrol->value.integer.value[0] = invert ? !flag : flag;\n+\n+\treturn 0;\n+}\n+\n+static const char * const recovered_frequency_texts[] = {\n+\t\"176.4/192 kHz\",\n+\t\"88.2/96 kHz\",\n+\t\"44.1/48 kHz\",\n+\t\"32 kHz\"\n+};\n+\n+#define NUM_RECOVERED_FREQUENCIES \\\n+\tARRAY_SIZE(recovered_frequency_texts)\n+\n+static int rpi_cirrus_recovered_frequency_info(struct snd_kcontrol *kcontrol,\n+\tstruct snd_ctl_elem_info *uinfo)\n+{\n+\tuinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;\n+\tuinfo->count = 1;\n+\tuinfo->value.enumerated.items = NUM_RECOVERED_FREQUENCIES;\n+\tif (uinfo->value.enumerated.item >= NUM_RECOVERED_FREQUENCIES)\n+\t\tuinfo->value.enumerated.item = NUM_RECOVERED_FREQUENCIES - 1;\n+\tstrcpy(uinfo->value.enumerated.name,\n+\t\trecovered_frequency_texts[uinfo->value.enumerated.item]);\n+\treturn 0;\n+}\n+\n+static int rpi_cirrus_recovered_frequency_get(struct snd_kcontrol *kcontrol,\n+\tstruct snd_ctl_elem_value *ucontrol)\n+{\n+\tstruct snd_soc_card *card = snd_kcontrol_chip(kcontrol);\n+\tstruct snd_soc_component *wm8804_component =\n+\t\tasoc_rtd_to_codec(get_wm8804_runtime(card), 0)->component;\n+\tunsigned int val;\n+\n+\tval = snd_soc_component_read(wm8804_component, WM8804_SPDSTAT);\n+\n+\tucontrol->value.enumerated.item[0] = (val >> 4) & 0x03;\n+\treturn 0;\n+}\n+\n+static const struct snd_kcontrol_new rpi_cirrus_controls[] = {\n+\t{\n+\t\t.iface =   SNDRV_CTL_ELEM_IFACE_MIXER,\n+\t\t.name =    \"Min Sample Rate\",\n+\t\t.info =    rpi_cirrus_min_rate_info,\n+\t\t.get =     rpi_cirrus_min_rate_get,\n+\t\t.put =     rpi_cirrus_min_rate_put,\n+\t},\n+\t{\n+\t\t.iface =   SNDRV_CTL_ELEM_IFACE_MIXER,\n+\t\t.name =    \"Max Sample Rate\",\n+\t\t.info =    rpi_cirrus_max_rate_info,\n+\t\t.get =     rpi_cirrus_max_rate_get,\n+\t\t.put =     rpi_cirrus_max_rate_put,\n+\t},\n+\t{\n+\t\t.iface =   SNDRV_CTL_ELEM_IFACE_MIXER,\n+\t\t.name =    SNDRV_CTL_NAME_IEC958(\"\", PLAYBACK, DEFAULT),\n+\t\t.info =    rpi_cirrus_spdif_info,\n+\t\t.get =     rpi_cirrus_spdif_playback_get,\n+\t\t.put =     rpi_cirrus_spdif_playback_put,\n+\t},\n+\t{\n+\t\t.access =  SNDRV_CTL_ELEM_ACCESS_READ\n+\t\t\t   | SNDRV_CTL_ELEM_ACCESS_VOLATILE,\n+\t\t.iface =   SNDRV_CTL_ELEM_IFACE_MIXER,\n+\t\t.name =    SNDRV_CTL_NAME_IEC958(\"\", CAPTURE, DEFAULT),\n+\t\t.info =    rpi_cirrus_spdif_info,\n+\t\t.get =     rpi_cirrus_spdif_capture_get,\n+\t},\n+\t{\n+\t\t.access =  SNDRV_CTL_ELEM_ACCESS_READ,\n+\t\t.iface =   SNDRV_CTL_ELEM_IFACE_MIXER,\n+\t\t.name =    SNDRV_CTL_NAME_IEC958(\"\", PLAYBACK, MASK),\n+\t\t.info =    rpi_cirrus_spdif_info,\n+\t\t.get =     rpi_cirrus_spdif_mask_get,\n+\t},\n+\t{\n+\t\t.access =  SNDRV_CTL_ELEM_ACCESS_READ\n+\t\t\t   | SNDRV_CTL_ELEM_ACCESS_VOLATILE,\n+\t\t.iface =   SNDRV_CTL_ELEM_IFACE_MIXER,\n+\t\t.name =    SNDRV_CTL_NAME_IEC958(\"\", CAPTURE, NONE)\n+\t\t\t\t\"Recovered Frequency\",\n+\t\t.info =    rpi_cirrus_recovered_frequency_info,\n+\t\t.get =     rpi_cirrus_recovered_frequency_get,\n+\t},\n+\tSPDIF_FLAG_CTRL(\"Audio\", WM8804_SPDSTAT, 0, 1),\n+\tSPDIF_FLAG_CTRL(\"Non-PCM\", WM8804_SPDSTAT, 1, 0),\n+\tSPDIF_FLAG_CTRL(\"Copyright\", WM8804_SPDSTAT, 2, 1),\n+\tSPDIF_FLAG_CTRL(\"De-Emphasis\", WM8804_SPDSTAT, 3, 0),\n+\tSPDIF_FLAG_CTRL(\"Lock\", WM8804_SPDSTAT, 6, 1),\n+\tSPDIF_FLAG_CTRL(\"Invalid\", WM8804_INTSTAT, 1, 0),\n+\tSPDIF_FLAG_CTRL(\"TransErr\", WM8804_INTSTAT, 3, 0),\n+};\n+\n+static const char * const linein_micbias_texts[] = {\n+\t\"off\", \"on\",\n+};\n+\n+static SOC_ENUM_SINGLE_VIRT_DECL(linein_micbias_enum,\n+\tlinein_micbias_texts);\n+\n+static const struct snd_kcontrol_new linein_micbias_mux =\n+\tSOC_DAPM_ENUM(\"Route\", linein_micbias_enum);\n+\n+static int rpi_cirrus_spdif_rx_enable_event(struct snd_soc_dapm_widget *w,\n+\tstruct snd_kcontrol *kcontrol, int event);\n+\n+const struct snd_soc_dapm_widget rpi_cirrus_dapm_widgets[] = {\n+\tSND_SOC_DAPM_MIC(\"DMIC\", NULL),\n+\tSND_SOC_DAPM_MIC(\"Headset Mic\", NULL),\n+\tSND_SOC_DAPM_INPUT(\"Line Input\"),\n+\tSND_SOC_DAPM_MIC(\"Line Input with Micbias\", NULL),\n+\tSND_SOC_DAPM_MUX(\"Line Input Micbias\", SND_SOC_NOPM, 0, 0,\n+\t\t&linein_micbias_mux),\n+\tSND_SOC_DAPM_INPUT(\"dummy SPDIF in\"),\n+\tSND_SOC_DAPM_PGA_E(\"dummy SPDIFRX\", SND_SOC_NOPM, 0, 0, NULL, 0,\n+\t\trpi_cirrus_spdif_rx_enable_event,\n+\t\tSND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),\n+\tSND_SOC_DAPM_INPUT(\"Dummy Input\"),\n+\tSND_SOC_DAPM_OUTPUT(\"Dummy Output\"),\n+};\n+\n+const struct snd_soc_dapm_route rpi_cirrus_dapm_routes[] = {\n+\t{ \"IN1L\", NULL, \"Headset Mic\" },\n+\t{ \"IN1R\", NULL, \"Headset Mic\" },\n+\t{ \"Headset Mic\", NULL, \"MICBIAS1\" },\n+\n+\t{ \"IN2L\", NULL, \"DMIC\" },\n+\t{ \"IN2R\", NULL, \"DMIC\" },\n+\t{ \"DMIC\", NULL, \"MICBIAS2\" },\n+\n+\t{ \"IN3L\", NULL, \"Line Input Micbias\" },\n+\t{ \"IN3R\", NULL, \"Line Input Micbias\" },\n+\n+\t{ \"Line Input Micbias\", \"off\", \"Line Input\" },\n+\t{ \"Line Input Micbias\", \"on\", \"Line Input with Micbias\" },\n+\n+\t/* Make sure MICVDD is enabled, otherwise we get noise */\n+\t{ \"Line Input\", NULL, \"MICVDD\" },\n+\t{ \"Line Input with Micbias\", NULL, \"MICBIAS3\" },\n+\n+\t/* Dummy routes to check whether SPDIF RX is enabled or not */\n+\t{\"dummy SPDIFRX\", NULL, \"dummy SPDIF in\"},\n+\t{\"AIFTX\", NULL, \"dummy SPDIFRX\"},\n+\n+\t/*\n+\t * Dummy routes to keep wm5102 from staying off on\n+\t * playback/capture if all mixers are off.\n+\t */\n+\t{ \"Dummy Output\", NULL, \"AIF1RX1\" },\n+\t{ \"Dummy Output\", NULL, \"AIF1RX2\" },\n+\t{ \"AIF1TX1\", NULL, \"Dummy Input\" },\n+\t{ \"AIF1TX2\", NULL, \"Dummy Input\" },\n+};\n+\n+static int rpi_cirrus_clear_flls(struct snd_soc_card *card,\n+\tstruct snd_soc_component *wm5102_component) {\n+\n+\tint ret1, ret2;\n+\n+\tret1 = snd_soc_component_set_pll(wm5102_component,\n+\t\tWM5102_FLL1, ARIZONA_FLL_SRC_NONE, 0, 0);\n+\tret2 = snd_soc_component_set_pll(wm5102_component,\n+\t\tWM5102_FLL1_REFCLK, ARIZONA_FLL_SRC_NONE, 0, 0);\n+\n+\tif (ret1) {\n+\t\tdev_warn(card->dev,\n+\t\t\t\"setting FLL1 to zero failed: %d\\n\", ret1);\n+\t\treturn ret1;\n+\t}\n+\tif (ret2) {\n+\t\tdev_warn(card->dev,\n+\t\t\t\"setting FLL1_REFCLK to zero failed: %d\\n\", ret2);\n+\t\treturn ret2;\n+\t}\n+\treturn 0;\n+}\n+\n+static int rpi_cirrus_set_fll(struct snd_soc_card *card,\n+\tstruct snd_soc_component *wm5102_component, unsigned int clk_freq)\n+{\n+\tint ret = snd_soc_component_set_pll(wm5102_component,\n+\t\tWM5102_FLL1,\n+\t\tARIZONA_CLK_SRC_MCLK1,\n+\t\tWM8804_CLKOUT_HZ,\n+\t\tclk_freq);\n+\tif (ret)\n+\t\tdev_err(card->dev, \"Failed to set FLL1 to %d: %d\\n\",\n+\t\t\tclk_freq, ret);\n+\n+\tusleep_range(1000, 2000);\n+\treturn ret;\n+}\n+\n+static int rpi_cirrus_set_fll_refclk(struct snd_soc_card *card,\n+\tstruct snd_soc_component *wm5102_component,\n+\tunsigned int clk_freq, unsigned int aif2_freq)\n+{\n+\tint ret = snd_soc_component_set_pll(wm5102_component,\n+\t\tWM5102_FLL1_REFCLK,\n+\t\tARIZONA_CLK_SRC_MCLK1,\n+\t\tWM8804_CLKOUT_HZ,\n+\t\tclk_freq);\n+\tif (ret) {\n+\t\tdev_err(card->dev,\n+\t\t\t\"Failed to set FLL1_REFCLK to %d: %d\\n\",\n+\t\t\tclk_freq, ret);\n+\t\treturn ret;\n+\t}\n+\n+\tret = snd_soc_component_set_pll(wm5102_component,\n+\t\tWM5102_FLL1,\n+\t\tARIZONA_CLK_SRC_AIF2BCLK,\n+\t\taif2_freq, clk_freq);\n+\tif (ret)\n+\t\tdev_err(card->dev,\n+\t\t\t\"Failed to set FLL1 with Sync Clock %d to %d: %d\\n\",\n+\t\t\taif2_freq, clk_freq, ret);\n+\n+\tusleep_range(1000, 2000);\n+\treturn ret;\n+}\n+\n+static int rpi_cirrus_spdif_rx_enable_event(struct snd_soc_dapm_widget *w,\n+\tstruct snd_kcontrol *kcontrol, int event)\n+{\n+\tstruct snd_soc_card *card = w->dapm->card;\n+\tstruct rpi_cirrus_priv *priv = snd_soc_card_get_drvdata(card);\n+\tstruct snd_soc_component *wm5102_component =\n+\t\tasoc_rtd_to_codec(get_wm5102_runtime(card), 0)->component;\n+\n+\tunsigned int clk_freq, aif2_freq;\n+\tint ret = 0;\n+\n+\tswitch (event) {\n+\tcase SND_SOC_DAPM_POST_PMU:\n+\t\tmutex_lock(&priv->lock);\n+\n+\t\t/* Enable sync path in case of SPDIF capture use case */\n+\n+\t\tclk_freq = calc_sysclk(priv->card_rate);\n+\t\taif2_freq = 64 * priv->card_rate;\n+\n+\t\tdev_dbg(card->dev,\n+\t\t\t\"spdif_rx: changing FLL1 to use Ref Clock clk: %d spdif: %d\\n\",\n+\t\t\tclk_freq, aif2_freq);\n+\n+\t\tret = rpi_cirrus_clear_flls(card, wm5102_component);\n+\t\tif (ret) {\n+\t\t\tdev_err(card->dev, \"spdif_rx: failed to clear FLLs\\n\");\n+\t\t\tgoto out;\n+\t\t}\n+\n+\t\tret = rpi_cirrus_set_fll_refclk(card, wm5102_component,\n+\t\t\tclk_freq, aif2_freq);\n+\n+\t\tif (ret) {\n+\t\t\tdev_err(card->dev, \"spdif_rx: failed to set FLLs\\n\");\n+\t\t\tgoto out;\n+\t\t}\n+\n+\t\t/* set to negative to indicate we're doing spdif rx */\n+\t\tpriv->fll1_freq = -clk_freq;\n+\t\tpriv->sync_path_enable = 1;\n+\t\tbreak;\n+\n+\tcase SND_SOC_DAPM_POST_PMD:\n+\t\tmutex_lock(&priv->lock);\n+\t\tpriv->sync_path_enable = 0;\n+\t\tbreak;\n+\n+\tdefault:\n+\t\treturn 0;\n+\t}\n+\n+out:\n+\tmutex_unlock(&priv->lock);\n+\treturn ret;\n+}\n+\n+static int rpi_cirrus_set_bias_level(struct snd_soc_card *card,\n+\tstruct snd_soc_dapm_context *dapm,\n+\tenum snd_soc_bias_level level)\n+{\n+\tstruct rpi_cirrus_priv *priv = snd_soc_card_get_drvdata(card);\n+\tstruct snd_soc_pcm_runtime *wm5102_runtime = get_wm5102_runtime(card);\n+\tstruct snd_soc_component *wm5102_component =\n+\t\tasoc_rtd_to_codec(wm5102_runtime, 0)->component;\n+\n+\tint ret = 0;\n+\tunsigned int clk_freq;\n+\n+\tif (dapm->dev != asoc_rtd_to_codec(wm5102_runtime, 0)->dev)\n+\t\treturn 0;\n+\n+\tswitch (level) {\n+\tcase SND_SOC_BIAS_PREPARE:\n+\t\tif (dapm->bias_level == SND_SOC_BIAS_ON)\n+\t\t\tbreak;\n+\n+\t\tmutex_lock(&priv->lock);\n+\n+\t\tif (!priv->sync_path_enable) {\n+\t\t\tclk_freq = calc_sysclk(priv->card_rate);\n+\n+\t\t\tdev_dbg(card->dev,\n+\t\t\t\t\"set_bias: changing FLL1 from %d to %d\\n\",\n+\t\t\t\tpriv->fll1_freq, clk_freq);\n+\n+\t\t\tret = rpi_cirrus_set_fll(card,\n+\t\t\t\twm5102_component, clk_freq);\n+\t\t\tif (ret)\n+\t\t\t\tdev_err(card->dev,\n+\t\t\t\t\t\"set_bias: Failed to set FLL1\\n\");\n+\t\t\telse\n+\t\t\t\tpriv->fll1_freq = clk_freq;\n+\t\t}\n+\t\tmutex_unlock(&priv->lock);\n+\t\tbreak;\n+\tdefault:\n+\t\tbreak;\n+\t}\n+\n+\treturn ret;\n+}\n+\n+static int rpi_cirrus_set_bias_level_post(struct snd_soc_card *card,\n+\tstruct snd_soc_dapm_context *dapm,\n+\tenum snd_soc_bias_level level)\n+{\n+\tstruct rpi_cirrus_priv *priv = snd_soc_card_get_drvdata(card);\n+\tstruct snd_soc_pcm_runtime *wm5102_runtime = get_wm5102_runtime(card);\n+\tstruct snd_soc_component *wm5102_component =\n+\t\tasoc_rtd_to_codec(wm5102_runtime, 0)->component;\n+\n+\tif (dapm->dev != asoc_rtd_to_codec(wm5102_runtime, 0)->dev)\n+\t\treturn 0;\n+\n+\tswitch (level) {\n+\tcase SND_SOC_BIAS_STANDBY:\n+\t\tmutex_lock(&priv->lock);\n+\n+\t\tdev_dbg(card->dev,\n+\t\t\t\"set_bias_post: changing FLL1 from %d to off\\n\",\n+\t\t\t\tpriv->fll1_freq);\n+\n+\t\tif (rpi_cirrus_clear_flls(card, wm5102_component))\n+\t\t\tdev_err(card->dev,\n+\t\t\t\t\"set_bias_post: failed to clear FLLs\\n\");\n+\t\telse\n+\t\t\tpriv->fll1_freq = 0;\n+\n+\t\tmutex_unlock(&priv->lock);\n+\n+\t\tbreak;\n+\tdefault:\n+\t\tbreak;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int rpi_cirrus_set_wm8804_pll(struct snd_soc_card *card,\n+\tstruct snd_soc_dai *wm8804_dai, unsigned int rate)\n+{\n+\tint ret;\n+\n+\t/* use 256fs */\n+\tunsigned int clk_freq = rate * 256;\n+\n+\tret = snd_soc_dai_set_pll(wm8804_dai, 0, 0,\n+\t\tWM8804_CLKOUT_HZ, clk_freq);\n+\tif (ret) {\n+\t\tdev_err(card->dev,\n+\t\t\t\"Failed to set WM8804 PLL to %d: %d\\n\", clk_freq, ret);\n+\t\treturn ret;\n+\t}\n+\n+\t/* Set MCLK as PLL Output */\n+\tret = snd_soc_dai_set_sysclk(wm8804_dai,\n+\t\tWM8804_TX_CLKSRC_PLL, clk_freq, 0);\n+\tif (ret) {\n+\t\tdev_err(card->dev,\n+\t\t\t\"Failed to set MCLK as PLL Output: %d\\n\", ret);\n+\t\treturn ret;\n+\t}\n+\n+\treturn ret;\n+}\n+\n+static int rpi_cirrus_startup(struct snd_pcm_substream *substream)\n+{\n+\tstruct snd_soc_pcm_runtime *rtd = substream->private_data;\n+\tstruct snd_soc_card *card = rtd->card;\n+\tstruct rpi_cirrus_priv *priv = snd_soc_card_get_drvdata(card);\n+\tunsigned int min_rate = min_rates[priv->min_rate_idx].value;\n+\tunsigned int max_rate = max_rates[priv->max_rate_idx].value;\n+\n+\tif (min_rate || max_rate) {\n+\t\tif (max_rate == 0)\n+\t\t\tmax_rate = UINT_MAX;\n+\n+\t\tdev_dbg(card->dev,\n+\t\t\t\"startup: limiting rate to %u-%u\\n\",\n+\t\t\tmin_rate, max_rate);\n+\n+\t\tsnd_pcm_hw_constraint_minmax(substream->runtime,\n+\t\t\tSNDRV_PCM_HW_PARAM_RATE, min_rate, max_rate);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static struct snd_soc_pcm_stream rpi_cirrus_dai_link2_params = {\n+\t.formats = SNDRV_PCM_FMTBIT_S24_LE,\n+\t.channels_min = 2,\n+\t.channels_max = 2,\n+\t.rate_min = RPI_CIRRUS_DEFAULT_RATE,\n+\t.rate_max = RPI_CIRRUS_DEFAULT_RATE,\n+};\n+\n+static int rpi_cirrus_hw_params(struct snd_pcm_substream *substream,\n+\tstruct snd_pcm_hw_params *params)\n+{\n+\tstruct snd_soc_pcm_runtime *rtd = substream->private_data;\n+\tstruct snd_soc_card *card = rtd->card;\n+\tstruct rpi_cirrus_priv *priv = snd_soc_card_get_drvdata(card);\n+\tstruct snd_soc_dai *bcm_i2s_dai = asoc_rtd_to_cpu(rtd, 0);\n+\tstruct snd_soc_component *wm5102_component = asoc_rtd_to_codec(rtd, 0)->component;\n+\tstruct snd_soc_dai *wm8804_dai = asoc_rtd_to_codec(get_wm8804_runtime(card), 0);\n+\n+\tint ret;\n+\n+\tunsigned int width = snd_pcm_format_physical_width(\n+\t\tparams_format(params));\n+\tunsigned int rate = params_rate(params);\n+\tunsigned int clk_freq = calc_sysclk(rate);\n+\n+\tmutex_lock(&priv->lock);\n+\n+\tdev_dbg(card->dev, \"hw_params: setting rate to %d\\n\", rate);\n+\n+\tret = snd_soc_dai_set_bclk_ratio(bcm_i2s_dai, 2 * width);\n+\tif (ret) {\n+\t\tdev_err(card->dev, \"set_bclk_ratio failed: %d\\n\", ret);\n+\t\tgoto out;\n+\t}\n+\n+\tret = snd_soc_dai_set_tdm_slot(asoc_rtd_to_codec(rtd, 0), 0x03, 0x03, 2, width);\n+\tif (ret) {\n+\t\tdev_err(card->dev, \"set_tdm_slot failed: %d\\n\", ret);\n+\t\tgoto out;\n+\t}\n+\n+\t/* WM8804 supports sample rates from 32k only */\n+\tif (rate >= 32000) {\n+\t\tret = rpi_cirrus_set_wm8804_pll(card, wm8804_dai, rate);\n+\t\tif (ret)\n+\t\t\tgoto out;\n+\t}\n+\n+\tret = snd_soc_component_set_sysclk(wm5102_component,\n+\t\tARIZONA_CLK_SYSCLK,\n+\t\tARIZONA_CLK_SRC_FLL1,\n+\t\tclk_freq,\n+\t\tSND_SOC_CLOCK_IN);\n+\tif (ret) {\n+\t\tdev_err(card->dev, \"Failed to set SYSCLK: %d\\n\", ret);\n+\t\tgoto out;\n+\t}\n+\n+\tif ((priv->fll1_freq > 0) && (priv->fll1_freq != clk_freq)) {\n+\t\tdev_dbg(card->dev,\n+\t\t\t\"hw_params: changing FLL1 from %d to %d\\n\",\n+\t\t\tpriv->fll1_freq, clk_freq);\n+\n+\t\tif (rpi_cirrus_clear_flls(card, wm5102_component)) {\n+\t\t\tdev_err(card->dev, \"hw_params: failed to clear FLLs\\n\");\n+\t\t\tgoto out;\n+\t\t}\n+\n+\t\tif (rpi_cirrus_set_fll(card, wm5102_component, clk_freq)) {\n+\t\t\tdev_err(card->dev, \"hw_params: failed to set FLL\\n\");\n+\t\t\tgoto out;\n+\t\t}\n+\n+\t\tpriv->fll1_freq = clk_freq;\n+\t}\n+\n+\tpriv->card_rate = rate;\n+\trpi_cirrus_dai_link2_params.rate_min = rate;\n+\trpi_cirrus_dai_link2_params.rate_max = rate;\n+\n+\tpriv->params_set |= 1 << substream->stream;\n+\n+out:\n+\tmutex_unlock(&priv->lock);\n+\n+\treturn ret;\n+}\n+\n+static int rpi_cirrus_hw_free(struct snd_pcm_substream *substream)\n+{\n+\tstruct snd_soc_pcm_runtime *rtd = substream->private_data;\n+\tstruct snd_soc_card *card = rtd->card;\n+\tstruct rpi_cirrus_priv *priv = snd_soc_card_get_drvdata(card);\n+\tstruct snd_soc_component *wm5102_component = asoc_rtd_to_codec(rtd, 0)->component;\n+\tint ret;\n+\tunsigned int old_params_set = priv->params_set;\n+\n+\tpriv->params_set &= ~(1 << substream->stream);\n+\n+\t/* disable sysclk if this was the last open stream */\n+\tif (priv->params_set == 0 && old_params_set) {\n+\t\tdev_dbg(card->dev,\n+\t\t\t\"hw_free: Setting SYSCLK to Zero\\n\");\n+\n+\t\tret = snd_soc_component_set_sysclk(wm5102_component,\n+\t\t\tARIZONA_CLK_SYSCLK,\n+\t\t\tARIZONA_CLK_SRC_FLL1,\n+\t\t\t0,\n+\t\t\tSND_SOC_CLOCK_IN);\n+\t\tif (ret)\n+\t\t\tdev_err(card->dev,\n+\t\t\t\t\"hw_free: Failed to set SYSCLK to Zero: %d\\n\",\n+\t\t\t\tret);\n+\t}\n+\treturn 0;\n+}\n+\n+static int rpi_cirrus_init_wm5102(struct snd_soc_pcm_runtime *rtd)\n+{\n+\tstruct snd_soc_component *component = asoc_rtd_to_codec(rtd, 0)->component;\n+\tint ret;\n+\n+\t/* no 32kHz input, derive it from sysclk if needed  */\n+\tsnd_soc_component_update_bits(component,\n+\t\t\tARIZONA_CLOCK_32K_1, ARIZONA_CLK_32K_SRC_MASK, 2);\n+\n+\tif (rpi_cirrus_clear_flls(rtd->card, component))\n+\t\tdev_warn(rtd->card->dev,\n+\t\t\t\"init_wm5102: failed to clear FLLs\\n\");\n+\n+\tret = snd_soc_component_set_sysclk(component,\n+\t\tARIZONA_CLK_SYSCLK, ARIZONA_CLK_SRC_FLL1,\n+\t\t0, SND_SOC_CLOCK_IN);\n+\tif (ret) {\n+\t\tdev_err(rtd->card->dev,\n+\t\t\t\"Failed to set SYSCLK to Zero: %d\\n\", ret);\n+\t\treturn ret;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int rpi_cirrus_init_wm8804(struct snd_soc_pcm_runtime *rtd)\n+{\n+\tstruct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);\n+\tstruct snd_soc_component *component = codec_dai->component;\n+\tstruct snd_soc_card *card = rtd->card;\n+\tstruct rpi_cirrus_priv *priv = snd_soc_card_get_drvdata(card);\n+\tunsigned int val, mask;\n+\tint i, ret;\n+\n+\tfor (i = 0; i < 4; i++) {\n+\t\tval = snd_soc_component_read(component,\n+\t\t\tWM8804_SPDTX1 + i);\n+\t\tmask = (i == 3) ? 0x3f : 0xff;\n+\t\tpriv->iec958_status[i] = val & mask;\n+\t}\n+\n+\t/* Setup for 256fs */\n+\tret = snd_soc_dai_set_clkdiv(codec_dai,\n+\t\tWM8804_MCLK_DIV, WM8804_MCLKDIV_256FS);\n+\tif (ret) {\n+\t\tdev_err(card->dev,\n+\t\t\t\"init_wm8804: Failed to set MCLK_DIV to 256fs: %d\\n\",\n+\t\t\tret);\n+\t\treturn ret;\n+\t}\n+\n+\t/* Output OSC on CLKOUT */\n+\tret = snd_soc_dai_set_sysclk(codec_dai,\n+\t\tWM8804_CLKOUT_SRC_OSCCLK, WM8804_CLKOUT_HZ, 0);\n+\tif (ret)\n+\t\tdev_err(card->dev,\n+\t\t\t\"init_wm8804: Failed to set CLKOUT as OSC Frequency: %d\\n\",\n+\t\t\tret);\n+\n+\t/* Init PLL with default samplerate */\n+\tret = rpi_cirrus_set_wm8804_pll(card, codec_dai,\n+\t\tRPI_CIRRUS_DEFAULT_RATE);\n+\tif (ret)\n+\t\tdev_err(card->dev,\n+\t\t\t\"init_wm8804: Failed to setup PLL for %dHz: %d\\n\",\n+\t\t\tRPI_CIRRUS_DEFAULT_RATE, ret);\n+\n+\treturn ret;\n+}\n+\n+static struct snd_soc_ops rpi_cirrus_ops = {\n+\t.startup = rpi_cirrus_startup,\n+\t.hw_params = rpi_cirrus_hw_params,\n+\t.hw_free = rpi_cirrus_hw_free,\n+};\n+\n+SND_SOC_DAILINK_DEFS(wm5102,\n+     DAILINK_COMP_ARRAY(COMP_EMPTY()),\n+     DAILINK_COMP_ARRAY(COMP_CODEC(\"wm5102-codec\", \"wm5102-aif1\")),\n+     DAILINK_COMP_ARRAY(COMP_EMPTY()));\n+\n+SND_SOC_DAILINK_DEFS(wm8804,\n+     DAILINK_COMP_ARRAY(COMP_CPU(\"wm5102-aif2\")),\n+     DAILINK_COMP_ARRAY(COMP_CODEC(\"wm8804.1-003b\", \"wm8804-spdif\")));\n+\n+static struct snd_soc_dai_link rpi_cirrus_dai[] = {\n+\t[DAI_WM5102] = {\n+\t\t.name\t\t= \"WM5102\",\n+\t\t.stream_name\t= \"WM5102 AiFi\",\n+\t\t.dai_fmt\t=   SND_SOC_DAIFMT_I2S\n+\t\t\t\t  | SND_SOC_DAIFMT_NB_NF\n+\t\t\t\t  | SND_SOC_DAIFMT_CBM_CFM,\n+\t\t.ops\t\t= &rpi_cirrus_ops,\n+\t\t.init\t\t= rpi_cirrus_init_wm5102,\n+\t\tSND_SOC_DAILINK_REG(wm5102),\n+\t},\n+\t[DAI_WM8804] = {\n+\t\t.name\t\t= \"WM5102 SPDIF\",\n+\t\t.stream_name\t= \"SPDIF Tx/Rx\",\n+\t\t.dai_fmt\t=   SND_SOC_DAIFMT_I2S\n+\t\t\t\t  | SND_SOC_DAIFMT_NB_NF\n+\t\t\t\t  | SND_SOC_DAIFMT_CBM_CFM,\n+\t\t.ignore_suspend = 1,\n+\t\t.params\t\t= &rpi_cirrus_dai_link2_params,\n+\t\t.init\t\t= rpi_cirrus_init_wm8804,\n+\t\tSND_SOC_DAILINK_REG(wm8804),\n+\t},\n+};\n+\n+\n+static int rpi_cirrus_late_probe(struct snd_soc_card *card)\n+{\n+\tstruct rpi_cirrus_priv *priv = snd_soc_card_get_drvdata(card);\n+\tstruct snd_soc_pcm_runtime *wm5102_runtime = get_wm5102_runtime(card);\n+\tstruct snd_soc_pcm_runtime *wm8804_runtime = get_wm8804_runtime(card);\n+\tint ret;\n+\n+\tdev_dbg(card->dev, \"iec958_bits: %02x %02x %02x %02x\\n\",\n+\t\tpriv->iec958_status[0],\n+\t\tpriv->iec958_status[1],\n+\t\tpriv->iec958_status[2],\n+\t\tpriv->iec958_status[3]);\n+\n+\tret = snd_soc_dai_set_sysclk(\n+\t\tasoc_rtd_to_codec(wm5102_runtime, 0), ARIZONA_CLK_SYSCLK, 0, 0);\n+\tif (ret) {\n+\t\tdev_err(card->dev,\n+\t\t\t\"Failed to set WM5102 codec dai clk domain: %d\\n\", ret);\n+\t\treturn ret;\n+\t}\n+\n+\tret = snd_soc_dai_set_sysclk(\n+\t\tasoc_rtd_to_cpu(wm8804_runtime, 0), ARIZONA_CLK_SYSCLK, 0, 0);\n+\tif (ret)\n+\t\tdev_err(card->dev,\n+\t\t\t\"Failed to set WM8804 codec dai clk domain: %d\\n\", ret);\n+\n+\treturn ret;\n+}\n+\n+/* audio machine driver */\n+static struct snd_soc_card rpi_cirrus_card = {\n+\t.name\t\t\t= \"RPi-Cirrus\",\n+\t.driver_name\t\t= \"RPiCirrus\",\n+\t.owner\t\t\t= THIS_MODULE,\n+\t.dai_link\t\t= rpi_cirrus_dai,\n+\t.num_links\t\t= ARRAY_SIZE(rpi_cirrus_dai),\n+\t.late_probe\t\t= rpi_cirrus_late_probe,\n+\t.controls\t\t= rpi_cirrus_controls,\n+\t.num_controls\t\t= ARRAY_SIZE(rpi_cirrus_controls),\n+\t.dapm_widgets\t\t= rpi_cirrus_dapm_widgets,\n+\t.num_dapm_widgets\t= ARRAY_SIZE(rpi_cirrus_dapm_widgets),\n+\t.dapm_routes\t\t= rpi_cirrus_dapm_routes,\n+\t.num_dapm_routes\t= ARRAY_SIZE(rpi_cirrus_dapm_routes),\n+\t.set_bias_level\t\t= rpi_cirrus_set_bias_level,\n+\t.set_bias_level_post\t= rpi_cirrus_set_bias_level_post,\n+};\n+\n+static int rpi_cirrus_probe(struct platform_device *pdev)\n+{\n+\tint ret = 0;\n+\tstruct rpi_cirrus_priv *priv;\n+\tstruct device_node *i2s_node;\n+\n+\tpriv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);\n+\tif (!priv)\n+\t\treturn -ENOMEM;\n+\n+\tpriv->min_rate_idx = 1; /* min samplerate 32kHz */\n+\tpriv->card_rate = RPI_CIRRUS_DEFAULT_RATE;\n+\n+\tmutex_init(&priv->lock);\n+\n+\tsnd_soc_card_set_drvdata(&rpi_cirrus_card, priv);\n+\n+\tif (!pdev->dev.of_node)\n+\t\treturn -ENODEV;\n+\n+\ti2s_node = of_parse_phandle(\n+\t\t\tpdev->dev.of_node, \"i2s-controller\", 0);\n+\tif (!i2s_node) {\n+\t\tdev_err(&pdev->dev, \"i2s-controller missing in DT\\n\");\n+\t\treturn -ENODEV;\n+\t}\n+\n+\trpi_cirrus_dai[DAI_WM5102].cpus->of_node = i2s_node;\n+\trpi_cirrus_dai[DAI_WM5102].platforms->of_node = i2s_node;\n+\n+\trpi_cirrus_card.dev = &pdev->dev;\n+\n+\tret = devm_snd_soc_register_card(&pdev->dev, &rpi_cirrus_card);\n+\tif (ret) {\n+\t\tif (ret == -EPROBE_DEFER)\n+\t\t\tdev_dbg(&pdev->dev,\n+\t\t\t\t\"register card requested probe deferral\\n\");\n+\t\telse\n+\t\t\tdev_err(&pdev->dev,\n+\t\t\t\t\"Failed to register card: %d\\n\", ret);\n+\t}\n+\n+\treturn ret;\n+}\n+\n+static const struct of_device_id rpi_cirrus_of_match[] = {\n+\t{ .compatible = \"wlf,rpi-cirrus\", },\n+\t{},\n+};\n+MODULE_DEVICE_TABLE(of, rpi_cirrus_of_match);\n+\n+static struct platform_driver rpi_cirrus_driver = {\n+\t.driver\t= {\n+\t\t.name   = \"snd-rpi-cirrus\",\n+\t\t.of_match_table = of_match_ptr(rpi_cirrus_of_match),\n+\t},\n+\t.probe\t= rpi_cirrus_probe,\n+};\n+\n+module_platform_driver(rpi_cirrus_driver);\n+\n+MODULE_AUTHOR(\"Matthias Reichl <hias@horus.com>\");\n+MODULE_DESCRIPTION(\"ASoC driver for Cirrus Logic Audio Card\");\n+MODULE_LICENSE(\"GPL\");\n--- /dev/null\n+++ b/sound/soc/bcm/rpi-proto.c\n@@ -0,0 +1,147 @@\n+/*\n+ * ASoC driver for PROTO AudioCODEC (with a WM8731)\n+ * connected to a Raspberry Pi\n+ *\n+ * Author:      Florian Meier, <koalo@koalo.de>\n+ *\t      Copyright 2013\n+ *\n+ * This program is free software; you can redistribute it and/or modify\n+ * it under the terms of the GNU General Public License version 2 as\n+ * published by the Free Software Foundation.\n+ */\n+\n+#include <linux/module.h>\n+#include <linux/platform_device.h>\n+\n+#include <sound/core.h>\n+#include <sound/pcm.h>\n+#include <sound/soc.h>\n+#include <sound/jack.h>\n+\n+#include \"../codecs/wm8731.h\"\n+\n+static const unsigned int wm8731_rates_12288000[] = {\n+\t8000, 32000, 48000, 96000,\n+};\n+\n+static struct snd_pcm_hw_constraint_list wm8731_constraints_12288000 = {\n+\t.list = wm8731_rates_12288000,\n+\t.count = ARRAY_SIZE(wm8731_rates_12288000),\n+};\n+\n+static int snd_rpi_proto_startup(struct snd_pcm_substream *substream)\n+{\n+\t/* Setup constraints, because there is a 12.288 MHz XTAL on the board */\n+\tsnd_pcm_hw_constraint_list(substream->runtime, 0,\n+\t\t\t\tSNDRV_PCM_HW_PARAM_RATE,\n+\t\t\t\t&wm8731_constraints_12288000);\n+\treturn 0;\n+}\n+\n+static int snd_rpi_proto_hw_params(struct snd_pcm_substream *substream,\n+\t\t\t\t       struct snd_pcm_hw_params *params)\n+{\n+\tstruct snd_soc_pcm_runtime *rtd = substream->private_data;\n+\tstruct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);\n+\tstruct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);\n+\tint sysclk = 12288000; /* This is fixed on this board */\n+\n+\t/* Set proto bclk */\n+\tint ret = snd_soc_dai_set_bclk_ratio(cpu_dai,32*2);\n+\tif (ret < 0){\n+\t\tdev_err(rtd->card->dev,\n+\t\t\t\t\"Failed to set BCLK ratio %d\\n\", ret);\n+\t\treturn ret;\n+\t}\n+\n+\t/* Set proto sysclk */\n+\tret = snd_soc_dai_set_sysclk(codec_dai, WM8731_SYSCLK_XTAL,\n+\t\t\tsysclk, SND_SOC_CLOCK_IN);\n+\tif (ret < 0) {\n+\t\tdev_err(rtd->card->dev,\n+\t\t\t\t\"Failed to set WM8731 SYSCLK: %d\\n\", ret);\n+\t\treturn ret;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+/* machine stream operations */\n+static struct snd_soc_ops snd_rpi_proto_ops = {\n+\t.startup = snd_rpi_proto_startup,\n+\t.hw_params = snd_rpi_proto_hw_params,\n+};\n+\n+SND_SOC_DAILINK_DEFS(rpi_proto,\n+\tDAILINK_COMP_ARRAY(COMP_CPU(\"bcm2708-i2s.0\")),\n+\tDAILINK_COMP_ARRAY(COMP_CODEC(\"wm8731.1-001a\", \"wm8731-hifi\")),\n+\tDAILINK_COMP_ARRAY(COMP_PLATFORM(\"bcm2708-i2s.0\")));\n+\n+static struct snd_soc_dai_link snd_rpi_proto_dai[] = {\n+{\n+\t.name\t\t= \"WM8731\",\n+\t.stream_name\t= \"WM8731 HiFi\",\n+\t.dai_fmt\t= SND_SOC_DAIFMT_I2S\n+\t\t\t\t| SND_SOC_DAIFMT_NB_NF\n+\t\t\t\t| SND_SOC_DAIFMT_CBM_CFM,\n+\t.ops\t\t= &snd_rpi_proto_ops,\n+\tSND_SOC_DAILINK_REG(rpi_proto),\n+},\n+};\n+\n+/* audio machine driver */\n+static struct snd_soc_card snd_rpi_proto = {\n+\t.name\t\t= \"snd_rpi_proto\",\n+\t.owner\t\t= THIS_MODULE,\n+\t.dai_link\t= snd_rpi_proto_dai,\n+\t.num_links\t= ARRAY_SIZE(snd_rpi_proto_dai),\n+};\n+\n+static int snd_rpi_proto_probe(struct platform_device *pdev)\n+{\n+\tint ret = 0;\n+\n+\tsnd_rpi_proto.dev = &pdev->dev;\n+\n+\tif (pdev->dev.of_node) {\n+\t\tstruct device_node *i2s_node;\n+\t\tstruct snd_soc_dai_link *dai = &snd_rpi_proto_dai[0];\n+\t\ti2s_node = of_parse_phandle(pdev->dev.of_node,\n+\t\t\t\t            \"i2s-controller\", 0);\n+\n+\t\tif (i2s_node) {\n+\t\t\tdai->cpus->dai_name = NULL;\n+\t\t\tdai->cpus->of_node = i2s_node;\n+\t\t\tdai->platforms->name = NULL;\n+\t\t\tdai->platforms->of_node = i2s_node;\n+\t\t}\n+\t}\n+\n+\tret = devm_snd_soc_register_card(&pdev->dev, &snd_rpi_proto);\n+\tif (ret && ret != -EPROBE_DEFER)\n+\t\tdev_err(&pdev->dev,\n+\t\t\t\t\"snd_soc_register_card() failed: %d\\n\", ret);\n+\n+\treturn ret;\n+}\n+\n+static const struct of_device_id snd_rpi_proto_of_match[] = {\n+\t{ .compatible = \"rpi,rpi-proto\", },\n+\t{},\n+};\n+MODULE_DEVICE_TABLE(of, snd_rpi_proto_of_match);\n+\n+static struct platform_driver snd_rpi_proto_driver = {\n+\t.driver = {\n+\t\t.name   = \"snd-rpi-proto\",\n+\t\t.owner  = THIS_MODULE,\n+\t\t.of_match_table = snd_rpi_proto_of_match,\n+\t},\n+\t.probe\t  = snd_rpi_proto_probe,\n+};\n+\n+module_platform_driver(snd_rpi_proto_driver);\n+\n+MODULE_AUTHOR(\"Florian Meier\");\n+MODULE_DESCRIPTION(\"ASoC Driver for Raspberry Pi connected to PROTO board (WM8731)\");\n+MODULE_LICENSE(\"GPL\");\n--- /dev/null\n+++ b/sound/soc/bcm/rpi-simple-soundcard.c\n@@ -0,0 +1,339 @@\n+// SPDX-License-Identifier: GPL-2.0\n+/*\n+ * rpi-simple-soundcard.c -- ALSA SoC Raspberry Pi soundcard.\n+ *\n+ * Copyright (C) 2018 Raspberry Pi.\n+ *\n+ * Authors: Tim Gover <tim.gover@raspberrypi.org>\n+ *\n+ * Based on code:\n+ * hifiberry_amp.c, hifiberry_dac.c, rpi-dac.c\n+ * by Florian Meier <florian.meier@koalo.de>\n+ *\n+ * googlevoicehat-soundcard.c\n+ * by Peter Malkin <petermalkin@google.com>\n+ *\n+ * adau1977-adc.c\n+ * by Andrey Grodzovsky <andrey2805@gmail.com>\n+ *\n+ * merus-amp.c\n+ * by Ariel Muszkat <ariel.muszkat@gmail.com>\n+ *\t\tJorgen Kragh Jakobsen <jorgen.kraghjakobsen@infineon.com>\n+ *\n+ * This program is free software; you can redistribute it and/or\n+ * modify it under the terms of the GNU General Public License\n+ * version 2 as published by the Free Software Foundation.\n+ *\n+ * This program is distributed in the hope that it will be useful, but\n+ * WITHOUT ANY WARRANTY; without even the implied warranty of\n+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\n+ * General Public License for more details.\n+ */\n+\n+#include <linux/module.h>\n+#include <linux/platform_device.h>\n+\n+#include <sound/core.h>\n+#include <sound/pcm.h>\n+#include <sound/pcm_params.h>\n+#include <sound/soc.h>\n+\n+/* Parameters for generic RPI functions */\n+struct snd_rpi_simple_drvdata {\n+\tstruct snd_soc_dai_link *dai;\n+\tconst char* card_name;\n+\tunsigned int fixed_bclk_ratio;\n+};\n+\n+static int snd_rpi_simple_init(struct snd_soc_pcm_runtime *rtd)\n+{\n+\tstruct snd_rpi_simple_drvdata *drvdata =\n+\t\tsnd_soc_card_get_drvdata(rtd->card);\n+\tstruct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);\n+\n+\tif (drvdata->fixed_bclk_ratio > 0)\n+\t\treturn snd_soc_dai_set_bclk_ratio(cpu_dai,\n+\t\t\t\tdrvdata->fixed_bclk_ratio);\n+\n+\treturn 0;\n+}\n+\n+static int snd_rpi_simple_hw_params(struct snd_pcm_substream *substream,\n+\t\tstruct snd_pcm_hw_params *params)\n+{\n+\tstruct snd_soc_pcm_runtime *rtd = substream->private_data;\n+\tstruct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);\n+\tstruct snd_rpi_simple_drvdata *drvdata;\n+\tunsigned int sample_bits;\n+\n+\tdrvdata = snd_soc_card_get_drvdata(rtd->card);\n+\n+\tif (drvdata->fixed_bclk_ratio > 0)\n+\t\treturn 0; // BCLK is configured in .init\n+\n+\t/* The simple drivers just set the bclk_ratio to sample_bits * 2 so\n+\t * hard-code this for now. More complex drivers could just replace\n+\t * the hw_params routine.\n+\t */\n+\tsample_bits = snd_pcm_format_physical_width(params_format(params));\n+\treturn snd_soc_dai_set_bclk_ratio(cpu_dai, sample_bits * 2);\n+}\n+\n+static struct snd_soc_ops snd_rpi_simple_ops = {\n+\t.hw_params = snd_rpi_simple_hw_params,\n+};\n+\n+enum adau1977_clk_id {\n+\tADAU1977_SYSCLK,\n+};\n+\n+enum adau1977_sysclk_src {\n+\tADAU1977_SYSCLK_SRC_MCLK,\n+\tADAU1977_SYSCLK_SRC_LRCLK,\n+};\n+\n+static int adau1977_init(struct snd_soc_pcm_runtime *rtd)\n+{\n+\tint ret;\n+\tstruct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);\n+\n+\tret = snd_soc_dai_set_tdm_slot(codec_dai, 0, 0, 0, 0);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\treturn snd_soc_component_set_sysclk(codec_dai->component,\n+\t\t\tADAU1977_SYSCLK, ADAU1977_SYSCLK_SRC_MCLK,\n+\t\t\t11289600, SND_SOC_CLOCK_IN);\n+}\n+\n+SND_SOC_DAILINK_DEFS(adau1977,\n+\tDAILINK_COMP_ARRAY(COMP_EMPTY()),\n+\tDAILINK_COMP_ARRAY(COMP_CODEC(\"adau1977.1-0011\", \"adau1977-hifi\")),\n+\tDAILINK_COMP_ARRAY(COMP_EMPTY()));\n+\n+static struct snd_soc_dai_link snd_rpi_adau1977_dai[] = {\n+\t{\n+\t.name           = \"adau1977\",\n+\t.stream_name    = \"ADAU1977\",\n+\t.init           = adau1977_init,\n+\t.dai_fmt = SND_SOC_DAIFMT_I2S |\n+\t\tSND_SOC_DAIFMT_NB_NF |\n+\t\tSND_SOC_DAIFMT_CBM_CFM,\n+\tSND_SOC_DAILINK_REG(adau1977),\n+\t},\n+};\n+\n+static struct snd_rpi_simple_drvdata drvdata_adau1977 = {\n+\t.card_name = \"snd_rpi_adau1977_adc\",\n+\t.dai       = snd_rpi_adau1977_dai,\n+};\n+\n+SND_SOC_DAILINK_DEFS(gvchat,\n+\tDAILINK_COMP_ARRAY(COMP_EMPTY()),\n+\tDAILINK_COMP_ARRAY(COMP_CODEC(\"voicehat-codec\", \"voicehat-hifi\")),\n+\tDAILINK_COMP_ARRAY(COMP_EMPTY()));\n+\n+static struct snd_soc_dai_link snd_googlevoicehat_soundcard_dai[] = {\n+{\n+\t.name           = \"Google voiceHAT SoundCard\",\n+\t.stream_name    = \"Google voiceHAT SoundCard HiFi\",\n+\t.dai_fmt        =  SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |\n+\t\t\t\tSND_SOC_DAIFMT_CBS_CFS,\n+\tSND_SOC_DAILINK_REG(gvchat),\n+},\n+};\n+\n+static struct snd_rpi_simple_drvdata drvdata_googlevoicehat = {\n+\t.card_name = \"snd_rpi_googlevoicehat_soundcard\",\n+\t.dai       = snd_googlevoicehat_soundcard_dai,\n+};\n+\n+SND_SOC_DAILINK_DEFS(hifiberry_dacplusdsp,\n+\tDAILINK_COMP_ARRAY(COMP_EMPTY()),\n+\tDAILINK_COMP_ARRAY(COMP_CODEC(\"dacplusdsp-codec\", \"dacplusdsp-hifi\")),\n+\tDAILINK_COMP_ARRAY(COMP_EMPTY()));\n+\n+static struct snd_soc_dai_link snd_hifiberrydacplusdsp_soundcard_dai[] = {\n+{\n+\t.name           = \"Hifiberry DAC+DSP SoundCard\",\n+\t.stream_name    = \"Hifiberry DAC+DSP SoundCard HiFi\",\n+\t.dai_fmt        =  SND_SOC_DAIFMT_I2S |\n+\t\t\t   SND_SOC_DAIFMT_NB_NF |\n+\t\t\t   SND_SOC_DAIFMT_CBS_CFS,\n+\tSND_SOC_DAILINK_REG(hifiberry_dacplusdsp),\n+},\n+};\n+\n+static struct snd_rpi_simple_drvdata drvdata_hifiberrydacplusdsp = {\n+\t.card_name = \"snd_rpi_hifiberrydacplusdsp_soundcard\",\n+\t.dai       = snd_hifiberrydacplusdsp_soundcard_dai,\n+};\n+\n+SND_SOC_DAILINK_DEFS(hifiberry_amp,\n+\tDAILINK_COMP_ARRAY(COMP_EMPTY()),\n+\tDAILINK_COMP_ARRAY(COMP_CODEC(\"tas5713.1-001b\", \"tas5713-hifi\")),\n+\tDAILINK_COMP_ARRAY(COMP_EMPTY()));\n+\n+static struct snd_soc_dai_link snd_hifiberry_amp_dai[] = {\n+\t{\n+\t\t.name           = \"HifiBerry AMP\",\n+\t\t.stream_name    = \"HifiBerry AMP HiFi\",\n+\t\t.dai_fmt        = SND_SOC_DAIFMT_I2S |\n+\t\t\t\t\tSND_SOC_DAIFMT_NB_NF |\n+\t\t\t\t\tSND_SOC_DAIFMT_CBS_CFS,\n+\t\tSND_SOC_DAILINK_REG(hifiberry_amp),\n+\t},\n+};\n+\n+static struct snd_rpi_simple_drvdata drvdata_hifiberry_amp = {\n+\t.card_name        = \"snd_rpi_hifiberry_amp\",\n+\t.dai              = snd_hifiberry_amp_dai,\n+\t.fixed_bclk_ratio = 64,\n+};\n+\n+SND_SOC_DAILINK_DEFS(hifiberry_dac,\n+\tDAILINK_COMP_ARRAY(COMP_EMPTY()),\n+\tDAILINK_COMP_ARRAY(COMP_CODEC(\"pcm5102a-codec\", \"pcm5102a-hifi\")),\n+\tDAILINK_COMP_ARRAY(COMP_EMPTY()));\n+\n+static struct snd_soc_dai_link snd_hifiberry_dac_dai[] = {\n+\t{\n+\t\t.name           = \"HifiBerry DAC\",\n+\t\t.stream_name    = \"HifiBerry DAC HiFi\",\n+\t\t.dai_fmt        = SND_SOC_DAIFMT_I2S |\n+\t\t\t\t\tSND_SOC_DAIFMT_NB_NF |\n+\t\t\t\t\tSND_SOC_DAIFMT_CBS_CFS,\n+\t\tSND_SOC_DAILINK_REG(hifiberry_dac),\n+\t},\n+};\n+\n+static struct snd_rpi_simple_drvdata drvdata_hifiberry_dac = {\n+\t.card_name = \"snd_rpi_hifiberry_dac\",\n+\t.dai       = snd_hifiberry_dac_dai,\n+};\n+\n+SND_SOC_DAILINK_DEFS(rpi_dac,\n+\tDAILINK_COMP_ARRAY(COMP_EMPTY()),\n+\tDAILINK_COMP_ARRAY(COMP_CODEC(\"pcm1794a-codec\", \"pcm1794a-hifi\")),\n+\tDAILINK_COMP_ARRAY(COMP_EMPTY()));\n+\n+static struct snd_soc_dai_link snd_rpi_dac_dai[] = {\n+{\n+\t.name\t\t= \"RPi-DAC\",\n+\t.stream_name\t= \"RPi-DAC HiFi\",\n+\t.dai_fmt\t= SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |\n+\t\t\t\tSND_SOC_DAIFMT_CBS_CFS,\n+\tSND_SOC_DAILINK_REG(rpi_dac),\n+},\n+};\n+\n+static struct snd_rpi_simple_drvdata drvdata_rpi_dac = {\n+\t.card_name        = \"snd_rpi_rpi_dac\",\n+\t.dai              = snd_rpi_dac_dai,\n+\t.fixed_bclk_ratio = 64,\n+};\n+\n+SND_SOC_DAILINK_DEFS(merus_amp,\n+\tDAILINK_COMP_ARRAY(COMP_EMPTY()),\n+\tDAILINK_COMP_ARRAY(COMP_CODEC(\"ma120x0p.1-0020\",\"ma120x0p-amp\")),\n+\tDAILINK_COMP_ARRAY(COMP_EMPTY()));\n+\n+static struct snd_soc_dai_link snd_merus_amp_dai[] = {\n+\t{\n+\t\t.name           = \"MerusAmp\",\n+\t\t.stream_name    = \"Merus Audio Amp\",\n+\t\t.dai_fmt        = SND_SOC_DAIFMT_I2S |\n+\t\t\t\t\tSND_SOC_DAIFMT_NB_NF |\n+\t\t\t\t\tSND_SOC_DAIFMT_CBS_CFS,\n+\t\tSND_SOC_DAILINK_REG(merus_amp),\n+\t},\n+};\n+\n+static struct snd_rpi_simple_drvdata drvdata_merus_amp = {\n+\t.card_name        = \"snd_rpi_merus_amp\",\n+\t.dai              = snd_merus_amp_dai,\n+\t.fixed_bclk_ratio = 64,\n+};\n+\n+static const struct of_device_id snd_rpi_simple_of_match[] = {\n+\t{ .compatible = \"adi,adau1977-adc\",\n+\t\t.data = (void *) &drvdata_adau1977 },\n+\t{ .compatible = \"googlevoicehat,googlevoicehat-soundcard\",\n+\t\t.data = (void *) &drvdata_googlevoicehat },\n+\t{ .compatible = \"hifiberrydacplusdsp,hifiberrydacplusdsp-soundcard\",\n+\t\t.data = (void *) &drvdata_hifiberrydacplusdsp },\n+\t{ .compatible = \"hifiberry,hifiberry-amp\",\n+\t\t.data = (void *) &drvdata_hifiberry_amp },\n+\t{ .compatible = \"hifiberry,hifiberry-dac\",\n+\t\t.data = (void *) &drvdata_hifiberry_dac },\n+\t{ .compatible = \"rpi,rpi-dac\", &drvdata_rpi_dac},\n+\t{ .compatible = \"merus,merus-amp\",\n+\t\t.data = (void *) &drvdata_merus_amp },\n+\t{},\n+};\n+\n+static struct snd_soc_card snd_rpi_simple = {\n+\t.driver_name  = \"RPi-simple\",\n+\t.owner        = THIS_MODULE,\n+\t.dai_link     = NULL,\n+\t.num_links    = 1, /* Only a single DAI supported at the moment */\n+};\n+\n+static int snd_rpi_simple_probe(struct platform_device *pdev)\n+{\n+\tint ret = 0;\n+\tconst struct of_device_id *of_id;\n+\n+\tsnd_rpi_simple.dev = &pdev->dev;\n+\tof_id = of_match_node(snd_rpi_simple_of_match, pdev->dev.of_node);\n+\n+\tif (pdev->dev.of_node && of_id->data) {\n+\t\tstruct device_node *i2s_node;\n+\t\tstruct snd_rpi_simple_drvdata *drvdata =\n+\t\t\t(struct snd_rpi_simple_drvdata *) of_id->data;\n+\t\tstruct snd_soc_dai_link *dai = drvdata->dai;\n+\n+\t\tsnd_soc_card_set_drvdata(&snd_rpi_simple, drvdata);\n+\n+\t\t/* More complex drivers might override individual functions */\n+\t\tif (!dai->init)\n+\t\t\tdai->init = snd_rpi_simple_init;\n+\t\tif (!dai->ops)\n+\t\t\tdai->ops = &snd_rpi_simple_ops;\n+\n+\t\tsnd_rpi_simple.name = drvdata->card_name;\n+\n+\t\tsnd_rpi_simple.dai_link = dai;\n+\t\ti2s_node = of_parse_phandle(pdev->dev.of_node,\n+\t\t\t\t\"i2s-controller\", 0);\n+\t\tif (!i2s_node) {\n+\t\t\tpr_err(\"Failed to find i2s-controller DT node\\n\");\n+\t\t\treturn -ENODEV;\n+\t\t}\n+\n+\t\tdai->cpus->of_node = i2s_node;\n+\t\tdai->platforms->of_node = i2s_node;\n+\t}\n+\n+\tret = devm_snd_soc_register_card(&pdev->dev, &snd_rpi_simple);\n+\tif (ret && ret != -EPROBE_DEFER)\n+\t\tdev_err(&pdev->dev, \"Failed to register card %d\\n\", ret);\n+\n+\treturn ret;\n+}\n+\n+static struct platform_driver snd_rpi_simple_driver = {\n+\t.driver = {\n+\t\t.name   = \"snd-rpi-simple\",\n+\t\t.owner  = THIS_MODULE,\n+\t\t.of_match_table = snd_rpi_simple_of_match,\n+\t},\n+\t.probe          = snd_rpi_simple_probe,\n+};\n+MODULE_DEVICE_TABLE(of, snd_rpi_simple_of_match);\n+\n+module_platform_driver(snd_rpi_simple_driver);\n+\n+MODULE_AUTHOR(\"Tim Gover <tim.gover@raspberrypi.org>\");\n+MODULE_DESCRIPTION(\"ASoC Raspberry Pi simple soundcard driver \");\n+MODULE_LICENSE(\"GPL v2\");\n--- /dev/null\n+++ b/sound/soc/bcm/rpi-wm8804-soundcard.c\n@@ -0,0 +1,410 @@\n+// SPDX-License-Identifier: GPL-2.0\n+/*\n+ * rpi--wm8804.c -- ALSA SoC Raspberry Pi soundcard.\n+ *\n+ * Copyright (C) 2018 Raspberry Pi.\n+ *\n+ * Authors: Tim Gover <tim.gover@raspberrypi.org>\n+ *\n+ * Generic driver for Pi Hat WM8804 digi sounds cards\n+ *\n+ * Based upon code from:\n+ * justboom-digi.c\n+ * by Milan Neskovic <info@justboom.co>\n+ *\n+ * iqaudio_digi.c\n+ * by Daniel Matuschek <info@crazy-audio.com>\n+ *\n+ * allo-digione.c\n+ * by Baswaraj <jaikumar@cem-solutions.net>\n+ *\n+ * hifiberry-digi.c\n+ * Daniel Matuschek <info@crazy-audio.com>\n+ *\n+ * This program is free software; you can redistribute it and/or\n+ * modify it under the terms of the GNU General Public License\n+ * version 2 as published by the Free Software Foundation.\n+ *\n+ * This program is distributed in the hope that it will be useful, but\n+ * WITHOUT ANY WARRANTY; without even the implied warranty of\n+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\n+ * General Public License for more details.\n+ */\n+\n+#include <linux/gpio/consumer.h>\n+#include <linux/platform_device.h>\n+#include <linux/module.h>\n+\n+#include <sound/core.h>\n+#include <sound/pcm.h>\n+#include <sound/pcm_params.h>\n+#include <sound/soc.h>\n+\n+#include \"../codecs/wm8804.h\"\n+\n+struct wm8804_clk_cfg {\n+\tunsigned int sysclk_freq;\n+\tunsigned int mclk_freq;\n+\tunsigned int mclk_div;\n+};\n+\n+/* Parameters for generic functions */\n+struct snd_rpi_wm8804_drvdata {\n+\t/* Required - pointer to the DAI structure */\n+\tstruct snd_soc_dai_link *dai;\n+\t/* Required - snd_soc_card name */\n+\tconst char *card_name;\n+\t/* Optional DT node names if card info is defined in DT */\n+\tconst char *card_name_dt;\n+\tconst char *dai_name_dt;\n+\tconst char *dai_stream_name_dt;\n+\t/* Optional probe extension - called prior to register_card */\n+\tint (*probe)(struct platform_device *pdev);\n+};\n+\n+static struct gpio_desc *snd_clk44gpio;\n+static struct gpio_desc *snd_clk48gpio;\n+static int wm8804_samplerate = 0;\n+\n+/* Forward declarations */\n+static struct snd_soc_dai_link snd_allo_digione_dai[];\n+static struct snd_soc_card snd_rpi_wm8804;\n+\n+\n+#define CLK_44EN_RATE 22579200UL\n+#define CLK_48EN_RATE 24576000UL\n+\n+static unsigned int snd_rpi_wm8804_enable_clock(unsigned int samplerate)\n+{\n+\tswitch (samplerate) {\n+\tcase 11025:\n+\tcase 22050:\n+\tcase 44100:\n+\tcase 88200:\n+\tcase 176400:\n+\t\tgpiod_set_value_cansleep(snd_clk44gpio, 1);\n+\t\tgpiod_set_value_cansleep(snd_clk48gpio, 0);\n+\t\treturn CLK_44EN_RATE;\n+\tdefault:\n+\t\tgpiod_set_value_cansleep(snd_clk48gpio, 1);\n+\t\tgpiod_set_value_cansleep(snd_clk44gpio, 0);\n+\t\treturn CLK_48EN_RATE;\n+\t}\n+}\n+\n+static void snd_rpi_wm8804_clk_cfg(unsigned int samplerate,\n+\t\tstruct wm8804_clk_cfg *clk_cfg)\n+{\n+\tclk_cfg->sysclk_freq = 27000000;\n+\n+\tif (samplerate <= 96000 ||\n+\t    snd_rpi_wm8804.dai_link == snd_allo_digione_dai) {\n+\t\tclk_cfg->mclk_freq = samplerate * 256;\n+\t\tclk_cfg->mclk_div = WM8804_MCLKDIV_256FS;\n+\t} else {\n+\t\tclk_cfg->mclk_freq = samplerate * 128;\n+\t\tclk_cfg->mclk_div = WM8804_MCLKDIV_128FS;\n+\t}\n+\n+\tif (!(IS_ERR(snd_clk44gpio) || IS_ERR(snd_clk48gpio)))\n+\t\tclk_cfg->sysclk_freq = snd_rpi_wm8804_enable_clock(samplerate);\n+}\n+\n+static int snd_rpi_wm8804_hw_params(struct snd_pcm_substream *substream,\n+\t\tstruct snd_pcm_hw_params *params)\n+{\n+\tstruct snd_soc_pcm_runtime *rtd = substream->private_data;\n+\tstruct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);\n+\tstruct snd_soc_component *component = asoc_rtd_to_codec(rtd, 0)->component;\n+\tstruct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);\n+\tint sampling_freq = 1;\n+\tint ret;\n+\tstruct wm8804_clk_cfg clk_cfg;\n+\tint samplerate = params_rate(params);\n+\n+\tif (samplerate == wm8804_samplerate)\n+\t\treturn 0;\n+\n+\t/* clear until all clocks are setup properly */\n+\twm8804_samplerate = 0;\n+\n+\tsnd_rpi_wm8804_clk_cfg(samplerate, &clk_cfg);\n+\n+\tpr_debug(\"%s samplerate: %d mclk_freq: %u mclk_div: %u sysclk: %u\\n\",\n+\t\t\t__func__, samplerate, clk_cfg.mclk_freq,\n+\t\t\tclk_cfg.mclk_div, clk_cfg.sysclk_freq);\n+\n+\tswitch (samplerate) {\n+\tcase 32000:\n+\t\tsampling_freq = 0x03;\n+\t\tbreak;\n+\tcase 44100:\n+\t\tsampling_freq = 0x00;\n+\t\tbreak;\n+\tcase 48000:\n+\t\tsampling_freq = 0x02;\n+\t\tbreak;\n+\tcase 88200:\n+\t\tsampling_freq = 0x08;\n+\t\tbreak;\n+\tcase 96000:\n+\t\tsampling_freq = 0x0a;\n+\t\tbreak;\n+\tcase 176400:\n+\t\tsampling_freq = 0x0c;\n+\t\tbreak;\n+\tcase 192000:\n+\t\tsampling_freq = 0x0e;\n+\t\tbreak;\n+\tdefault:\n+\t\tdev_err(rtd->card->dev,\n+\t\t\"Failed to set WM8804 SYSCLK, unsupported samplerate %d\\n\",\n+\t\tsamplerate);\n+\t}\n+\n+\tsnd_soc_dai_set_clkdiv(codec_dai, WM8804_MCLK_DIV, clk_cfg.mclk_div);\n+\tsnd_soc_dai_set_pll(codec_dai, 0, 0,\n+\t\t\tclk_cfg.sysclk_freq, clk_cfg.mclk_freq);\n+\n+\tret = snd_soc_dai_set_sysclk(codec_dai, WM8804_TX_CLKSRC_PLL,\n+\t\t\tclk_cfg.sysclk_freq, SND_SOC_CLOCK_OUT);\n+\tif (ret < 0) {\n+\t\tdev_err(rtd->card->dev,\n+\t\t\"Failed to set WM8804 SYSCLK: %d\\n\", ret);\n+\t\treturn ret;\n+\t}\n+\n+\twm8804_samplerate = samplerate;\n+\n+\t/* set sampling frequency status bits */\n+\tsnd_soc_component_update_bits(component, WM8804_SPDTX4, 0x0f,\n+\t\t\tsampling_freq);\n+\n+\treturn snd_soc_dai_set_bclk_ratio(cpu_dai, 64);\n+}\n+\n+static struct snd_soc_ops snd_rpi_wm8804_ops = {\n+\t.hw_params = snd_rpi_wm8804_hw_params,\n+};\n+\n+SND_SOC_DAILINK_DEFS(justboom_digi,\n+\tDAILINK_COMP_ARRAY(COMP_EMPTY()),\n+\tDAILINK_COMP_ARRAY(COMP_EMPTY()),\n+\tDAILINK_COMP_ARRAY(COMP_EMPTY()));\n+\n+static struct snd_soc_dai_link snd_justboom_digi_dai[] = {\n+{\n+\t.name        = \"JustBoom Digi\",\n+\t.stream_name = \"JustBoom Digi HiFi\",\n+\tSND_SOC_DAILINK_REG(justboom_digi),\n+},\n+};\n+\n+static struct snd_rpi_wm8804_drvdata drvdata_justboom_digi = {\n+\t.card_name            = \"snd_rpi_justboom_digi\",\n+\t.dai                  = snd_justboom_digi_dai,\n+};\n+\n+SND_SOC_DAILINK_DEFS(iqaudio_digi,\n+\tDAILINK_COMP_ARRAY(COMP_EMPTY()),\n+\tDAILINK_COMP_ARRAY(COMP_EMPTY()),\n+\tDAILINK_COMP_ARRAY(COMP_EMPTY()));\n+\n+static struct snd_soc_dai_link snd_iqaudio_digi_dai[] = {\n+{\n+\t.name        = \"IQAudIO Digi\",\n+\t.stream_name = \"IQAudIO Digi HiFi\",\n+\tSND_SOC_DAILINK_REG(iqaudio_digi),\n+},\n+};\n+\n+static struct snd_rpi_wm8804_drvdata drvdata_iqaudio_digi = {\n+\t.card_name          = \"IQAudIODigi\",\n+\t.dai                = snd_iqaudio_digi_dai,\n+\t.card_name_dt       = \"wm8804-digi,card-name\",\n+\t.dai_name_dt        = \"wm8804-digi,dai-name\",\n+\t.dai_stream_name_dt = \"wm8804-digi,dai-stream-name\",\n+};\n+\n+static int snd_allo_digione_probe(struct platform_device *pdev)\n+{\n+\tpr_debug(\"%s\\n\", __func__);\n+\n+\tif (IS_ERR(snd_clk44gpio) || IS_ERR(snd_clk48gpio)) {\n+\t\tdev_err(&pdev->dev, \"devm_gpiod_get() failed\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\treturn 0;\n+}\n+\n+SND_SOC_DAILINK_DEFS(allo_digione,\n+\tDAILINK_COMP_ARRAY(COMP_EMPTY()),\n+\tDAILINK_COMP_ARRAY(COMP_EMPTY()),\n+\tDAILINK_COMP_ARRAY(COMP_EMPTY()));\n+\n+static struct snd_soc_dai_link snd_allo_digione_dai[] = {\n+{\n+\t.name        = \"Allo DigiOne\",\n+\t.stream_name = \"Allo DigiOne HiFi\",\n+\tSND_SOC_DAILINK_REG(allo_digione),\n+},\n+};\n+\n+static struct snd_rpi_wm8804_drvdata drvdata_allo_digione = {\n+\t.card_name = \"snd_allo_digione\",\n+\t.dai       = snd_allo_digione_dai,\n+\t.probe     = snd_allo_digione_probe,\n+};\n+\n+SND_SOC_DAILINK_DEFS(hifiberry_digi,\n+\tDAILINK_COMP_ARRAY(COMP_EMPTY()),\n+\tDAILINK_COMP_ARRAY(COMP_EMPTY()),\n+\tDAILINK_COMP_ARRAY(COMP_EMPTY()));\n+\n+static struct snd_soc_dai_link snd_hifiberry_digi_dai[] = {\n+{\n+\t.name        = \"HifiBerry Digi\",\n+\t.stream_name = \"HifiBerry Digi HiFi\",\n+\tSND_SOC_DAILINK_REG(hifiberry_digi),\n+},\n+};\n+\n+static int snd_hifiberry_digi_probe(struct platform_device *pdev)\n+{\n+\tpr_debug(\"%s\\n\", __func__);\n+\n+\tif (IS_ERR(snd_clk44gpio) || IS_ERR(snd_clk48gpio))\n+\t\treturn 0;\n+\n+\tsnd_hifiberry_digi_dai->name = \"HiFiBerry Digi+ Pro\";\n+\tsnd_hifiberry_digi_dai->stream_name = \"HiFiBerry Digi+ Pro HiFi\";\n+\treturn 0;\n+}\n+\n+static struct snd_rpi_wm8804_drvdata drvdata_hifiberry_digi = {\n+\t.card_name = \"snd_rpi_hifiberry_digi\",\n+\t.dai       = snd_hifiberry_digi_dai,\n+\t.probe     = snd_hifiberry_digi_probe,\n+};\n+\n+static const struct of_device_id snd_rpi_wm8804_of_match[] = {\n+\t{ .compatible = \"justboom,justboom-digi\",\n+\t\t.data = (void *) &drvdata_justboom_digi },\n+\t{ .compatible = \"iqaudio,wm8804-digi\",\n+\t\t.data = (void *) &drvdata_iqaudio_digi },\n+\t{ .compatible = \"allo,allo-digione\",\n+\t\t.data = (void *) &drvdata_allo_digione },\n+\t{ .compatible = \"hifiberry,hifiberry-digi\",\n+\t\t.data = (void *) &drvdata_hifiberry_digi },\n+\t{},\n+};\n+\n+static struct snd_soc_card snd_rpi_wm8804 = {\n+\t.driver_name  = \"RPi-WM8804\",\n+\t.owner        = THIS_MODULE,\n+\t.dai_link     = NULL,\n+\t.num_links    = 1,\n+};\n+\n+static int snd_rpi_wm8804_probe(struct platform_device *pdev)\n+{\n+\tint ret = 0;\n+\tconst struct of_device_id *of_id;\n+\n+\tsnd_rpi_wm8804.dev = &pdev->dev;\n+\tof_id = of_match_node(snd_rpi_wm8804_of_match, pdev->dev.of_node);\n+\n+\tif (pdev->dev.of_node && of_id->data) {\n+\t\tstruct device_node *i2s_node;\n+\t\tstruct snd_rpi_wm8804_drvdata *drvdata =\n+\t\t\t(struct snd_rpi_wm8804_drvdata *) of_id->data;\n+\t\tstruct snd_soc_dai_link *dai = drvdata->dai;\n+\n+\t\tsnd_soc_card_set_drvdata(&snd_rpi_wm8804, drvdata);\n+\n+\t\tif (!dai->ops)\n+\t\t\tdai->ops = &snd_rpi_wm8804_ops;\n+\t\tif (!dai->codecs->dai_name)\n+\t\t\tdai->codecs->dai_name = \"wm8804-spdif\";\n+\t\tif (!dai->codecs->name)\n+\t\t\tdai->codecs->name = \"wm8804.1-003b\";\n+\t\tif (!dai->dai_fmt)\n+\t\t\tdai->dai_fmt = SND_SOC_DAIFMT_I2S |\n+\t\t\t\tSND_SOC_DAIFMT_NB_NF |\n+\t\t\t\tSND_SOC_DAIFMT_CBM_CFM;\n+\n+\t\tsnd_rpi_wm8804.dai_link = dai;\n+\t\ti2s_node = of_parse_phandle(pdev->dev.of_node,\n+\t\t\t\t\"i2s-controller\", 0);\n+\t\tif (!i2s_node) {\n+\t\t\tpr_err(\"Failed to find i2s-controller DT node\\n\");\n+\t\t\treturn -ENODEV;\n+\t\t}\n+\n+\t\tsnd_rpi_wm8804.name = drvdata->card_name;\n+\n+\t\t/* If requested by in drvdata get card & DAI names from DT */\n+\t\tif (drvdata->card_name_dt)\n+\t\t\tof_property_read_string(i2s_node,\n+\t\t\t\t\tdrvdata->card_name_dt,\n+\t\t\t\t\t&snd_rpi_wm8804.name);\n+\n+\t\tif (drvdata->dai_name_dt)\n+\t\t\tof_property_read_string(i2s_node,\n+\t\t\t\t\tdrvdata->dai_name_dt,\n+\t\t\t\t\t&dai->name);\n+\n+\t\tif (drvdata->dai_stream_name_dt)\n+\t\t\tof_property_read_string(i2s_node,\n+\t\t\t\t\tdrvdata->dai_stream_name_dt,\n+\t\t\t\t\t&dai->stream_name);\n+\n+\t\tdai->cpus->of_node = i2s_node;\n+\t\tdai->platforms->of_node = i2s_node;\n+\n+\t\t/*\n+\t\t * clk44gpio and clk48gpio are not required by all cards so\n+\t\t * don't check the error status.\n+\t\t */\n+\t\tsnd_clk44gpio =\n+\t\t\tdevm_gpiod_get(&pdev->dev, \"clock44\", GPIOD_OUT_LOW);\n+\n+\t\tsnd_clk48gpio =\n+\t\t\tdevm_gpiod_get(&pdev->dev, \"clock48\", GPIOD_OUT_LOW);\n+\n+\t\tif (drvdata->probe) {\n+\t\t\tret = drvdata->probe(pdev);\n+\t\t\tif (ret < 0) {\n+\t\t\t\tdev_err(&pdev->dev, \"Custom probe failed %d\\n\",\n+\t\t\t\t\t\tret);\n+\t\t\t\treturn ret;\n+\t\t\t}\n+\t\t}\n+\n+\t\tpr_debug(\"%s card: %s dai: %s stream: %s\\n\", __func__,\n+\t\t\t\tsnd_rpi_wm8804.name,\n+\t\t\t\tdai->name, dai->stream_name);\n+\t}\n+\n+\tret = devm_snd_soc_register_card(&pdev->dev, &snd_rpi_wm8804);\n+\tif (ret && ret != -EPROBE_DEFER)\n+\t\tdev_err(&pdev->dev, \"Failed to register card %d\\n\", ret);\n+\n+\treturn ret;\n+}\n+\n+static struct platform_driver snd_rpi_wm8804_driver = {\n+\t.driver = {\n+\t\t.name           = \"snd-rpi-wm8804\",\n+\t\t.owner          = THIS_MODULE,\n+\t\t.of_match_table = snd_rpi_wm8804_of_match,\n+\t},\n+\t.probe  = snd_rpi_wm8804_probe,\n+};\n+MODULE_DEVICE_TABLE(of, snd_rpi_wm8804_of_match);\n+\n+module_platform_driver(snd_rpi_wm8804_driver);\n+\n+MODULE_AUTHOR(\"Tim Gover <tim.gover@raspberrypi.org>\");\n+MODULE_DESCRIPTION(\"ASoC Raspberry Pi Hat generic digi driver for WM8804 based cards\");\n+MODULE_LICENSE(\"GPL v2\");\n--- a/sound/soc/codecs/Kconfig\n+++ b/sound/soc/codecs/Kconfig\n@@ -100,12 +100,14 @@ config SND_SOC_ALL_CODECS\n \timply SND_SOC_ICS43432\n \timply SND_SOC_INNO_RK3036\n \timply SND_SOC_ISABELLE\n+\timply SND_SOC_I_SABRE_CODEC\n \timply SND_SOC_JZ4740_CODEC\n \timply SND_SOC_JZ4725B_CODEC\n \timply SND_SOC_JZ4770_CODEC\n \timply SND_SOC_LM4857\n \timply SND_SOC_LM49453\n \timply SND_SOC_LOCHNAGAR_SC\n+\timply SND_SOC_MA120X0P\n \timply SND_SOC_MAX98088\n \timply SND_SOC_MAX98090\n \timply SND_SOC_MAX98095\n@@ -142,6 +144,7 @@ config SND_SOC_ALL_CODECS\n \timply SND_SOC_PCM179X_SPI\n \timply SND_SOC_PCM186X_I2C\n \timply SND_SOC_PCM186X_SPI\n+\timply SND_SOC_PCM1794A\n \timply SND_SOC_PCM3008\n \timply SND_SOC_PCM3060_I2C\n \timply SND_SOC_PCM3060_SPI\n@@ -206,6 +209,7 @@ config SND_SOC_ALL_CODECS\n \timply SND_SOC_TLV320ADCX140\n \timply SND_SOC_TLV320AIC23_I2C\n \timply SND_SOC_TLV320AIC23_SPI\n+\timply SND_SOC_TAS5713\n \timply SND_SOC_TLV320AIC26\n \timply SND_SOC_TLV320AIC31XX\n \timply SND_SOC_TLV320AIC32X4_I2C\n@@ -343,12 +347,12 @@ config SND_SOC_AD193X\n \ttristate\n \n config SND_SOC_AD193X_SPI\n-\ttristate\n+\ttristate \"Analog Devices AU193X CODEC - SPI\"\n \tdepends on SPI_MASTER\n \tselect SND_SOC_AD193X\n \n config SND_SOC_AD193X_I2C\n-\ttristate\n+\ttristate \"Analog Devices AU193X CODEC - I2C\"\n \tdepends on I2C\n \tselect SND_SOC_AD193X\n \n@@ -809,7 +813,7 @@ config SND_SOC_HDAC_HDA\n \tselect SND_HDA\n \n config SND_SOC_ICS43432\n-\ttristate\n+\ttristate \"InvenSense ICS43432 I2S microphone codec\"\n \n config SND_SOC_INNO_RK3036\n \ttristate \"Inno codec driver for RK3036 SoC\"\n@@ -830,6 +834,13 @@ config SND_SOC_LOCHNAGAR_SC\n \t  This driver support the sound card functionality of the Cirrus\n \t  Logic Lochnagar audio development board.\n \n+config SND_SOC_MA120X0P\n+\ttristate \"Infineon Merus(TM) MA120X0P Multilevel Class-D Audio amplifiers\"\n+\tdepends on I2C\n+\thelp\n+\t\tEnable support for Infineon MA120X0P Multilevel Class-D audio power\n+\t\tamplifiers.\n+\n config SND_SOC_MADERA\n \ttristate\n \tdefault y if SND_SOC_CS47L15=y\n@@ -1130,6 +1141,10 @@ config SND_SOC_RT5616\n \ttristate \"Realtek RT5616 CODEC\"\n \tdepends on I2C\n \n+config SND_SOC_PCM1794A\n+\ttristate\n+\tdepends on I2C\n+\n config SND_SOC_RT5631\n \ttristate \"Realtek ALC5631/RT5631 CODEC\"\n \tdepends on I2C\n@@ -1351,6 +1366,9 @@ config SND_SOC_TFA9879\n \ttristate \"NXP Semiconductors TFA9879 amplifier\"\n \tdepends on I2C\n \n+config SND_SOC_TAS5713\n+\ttristate\n+\n config SND_SOC_TLV320AIC23\n \ttristate\n \n@@ -1789,4 +1807,8 @@ config SND_SOC_TPA6130A2\n \ttristate \"Texas Instruments TPA6130A2 headphone amplifier\"\n \tdepends on I2C\n \n+config SND_SOC_I_SABRE_CODEC\n+\ttristate \"Audiophonics I-SABRE Codec\"\n+\tdepends on I2C\n+\n endmenu\n--- a/sound/soc/codecs/Makefile\n+++ b/sound/soc/codecs/Makefile\n@@ -96,6 +96,7 @@ snd-soc-hdac-hda-objs := hdac_hda.o\n snd-soc-ics43432-objs := ics43432.o\n snd-soc-inno-rk3036-objs := inno_rk3036.o\n snd-soc-isabelle-objs := isabelle.o\n+snd-soc-i-sabre-codec-objs := i-sabre-codec.o\n snd-soc-jz4740-codec-objs := jz4740.o\n snd-soc-jz4725b-codec-objs := jz4725b.o\n snd-soc-jz4770-codec-objs := jz4770.o\n@@ -103,6 +104,7 @@ snd-soc-l3-objs := l3.o\n snd-soc-lm4857-objs := lm4857.o\n snd-soc-lm49453-objs := lm49453.o\n snd-soc-lochnagar-sc-objs := lochnagar-sc.o\n+snd-soc-ma120x0p-objs := ma120x0p.o\n snd-soc-madera-objs := madera.o\n snd-soc-max9759-objs := max9759.o\n snd-soc-max9768-objs := max9768.o\n@@ -144,6 +146,7 @@ snd-soc-pcm179x-spi-objs := pcm179x-spi.\n snd-soc-pcm186x-objs := pcm186x.o\n snd-soc-pcm186x-i2c-objs := pcm186x-i2c.o\n snd-soc-pcm186x-spi-objs := pcm186x-spi.o\n+snd-soc-pcm1794a-objs := pcm1794a.o\n snd-soc-pcm3008-objs := pcm3008.o\n snd-soc-pcm3060-objs := pcm3060.o\n snd-soc-pcm3060-i2c-objs := pcm3060-i2c.o\n@@ -216,6 +219,7 @@ snd-soc-tas6424-objs := tas6424.o\n snd-soc-tda7419-objs := tda7419.o\n snd-soc-tas2770-objs := tas2770.o\n snd-soc-tfa9879-objs := tfa9879.o\n+snd-soc-tas5713-objs := tas5713.o\n snd-soc-tlv320aic23-objs := tlv320aic23.o\n snd-soc-tlv320aic23-i2c-objs := tlv320aic23-i2c.o\n snd-soc-tlv320aic23-spi-objs := tlv320aic23-spi.o\n@@ -405,6 +409,7 @@ obj-$(CONFIG_SND_SOC_HDAC_HDA) += snd-so\n obj-$(CONFIG_SND_SOC_ICS43432)\t+= snd-soc-ics43432.o\n obj-$(CONFIG_SND_SOC_INNO_RK3036)\t+= snd-soc-inno-rk3036.o\n obj-$(CONFIG_SND_SOC_ISABELLE)\t+= snd-soc-isabelle.o\n+obj-$(CONFIG_SND_SOC_I_SABRE_CODEC)\t+= snd-soc-i-sabre-codec.o\n obj-$(CONFIG_SND_SOC_JZ4740_CODEC)\t+= snd-soc-jz4740-codec.o\n obj-$(CONFIG_SND_SOC_JZ4725B_CODEC)\t+= snd-soc-jz4725b-codec.o\n obj-$(CONFIG_SND_SOC_JZ4770_CODEC)\t+= snd-soc-jz4770-codec.o\n@@ -412,6 +417,7 @@ obj-$(CONFIG_SND_SOC_L3)\t+= snd-soc-l3.o\n obj-$(CONFIG_SND_SOC_LM4857)\t+= snd-soc-lm4857.o\n obj-$(CONFIG_SND_SOC_LM49453)   += snd-soc-lm49453.o\n obj-$(CONFIG_SND_SOC_LOCHNAGAR_SC)\t+= snd-soc-lochnagar-sc.o\n+obj-$(CONFIG_SND_SOC_MA120X0P)   += snd-soc-ma120x0p.o\n obj-$(CONFIG_SND_SOC_MADERA)\t+= snd-soc-madera.o\n obj-$(CONFIG_SND_SOC_MAX9759)\t+= snd-soc-max9759.o\n obj-$(CONFIG_SND_SOC_MAX9768)\t+= snd-soc-max9768.o\n@@ -465,6 +471,7 @@ obj-$(CONFIG_SND_SOC_PCM512x)\t+= snd-soc\n obj-$(CONFIG_SND_SOC_PCM512x_I2C)\t+= snd-soc-pcm512x-i2c.o\n obj-$(CONFIG_SND_SOC_PCM512x_SPI)\t+= snd-soc-pcm512x-spi.o\n obj-$(CONFIG_SND_SOC_RK3328)\t+= snd-soc-rk3328.o\n+obj-$(CONFIG_SND_SOC_PCM1794A)\t+= snd-soc-pcm1794a.o\n obj-$(CONFIG_SND_SOC_RL6231)\t+= snd-soc-rl6231.o\n obj-$(CONFIG_SND_SOC_RL6347A)\t+= snd-soc-rl6347a.o\n obj-$(CONFIG_SND_SOC_RT1011)\t+= snd-soc-rt1011.o\n@@ -526,6 +533,7 @@ obj-$(CONFIG_SND_SOC_TAS6424)\t+= snd-soc\n obj-$(CONFIG_SND_SOC_TDA7419)\t+= snd-soc-tda7419.o\n obj-$(CONFIG_SND_SOC_TAS2770) += snd-soc-tas2770.o\n obj-$(CONFIG_SND_SOC_TFA9879)\t+= snd-soc-tfa9879.o\n+obj-$(CONFIG_SND_SOC_TAS5713)\t+= snd-soc-tas5713.o\n obj-$(CONFIG_SND_SOC_TLV320AIC23)\t+= snd-soc-tlv320aic23.o\n obj-$(CONFIG_SND_SOC_TLV320AIC23_I2C)\t+= snd-soc-tlv320aic23-i2c.o\n obj-$(CONFIG_SND_SOC_TLV320AIC23_SPI)\t+= snd-soc-tlv320aic23-spi.o\n--- a/sound/soc/codecs/cs42xx8-i2c.c\n+++ b/sound/soc/codecs/cs42xx8-i2c.c\n@@ -45,11 +45,18 @@ static struct i2c_device_id cs42xx8_i2c_\n };\n MODULE_DEVICE_TABLE(i2c, cs42xx8_i2c_id);\n \n+const struct of_device_id cs42xx8_i2c_of_match[] = {\n+\t{ .compatible = \"cirrus,cs42448\", .data = &cs42448_data, },\n+\t{ .compatible = \"cirrus,cs42888\", .data = &cs42888_data, },\n+\t{ /* sentinel */ }\n+};\n+MODULE_DEVICE_TABLE(of, cs42xx8_i2c_of_match);\n+\n static struct i2c_driver cs42xx8_i2c_driver = {\n \t.driver = {\n \t\t.name = \"cs42xx8\",\n \t\t.pm = &cs42xx8_pm,\n-\t\t.of_match_table = cs42xx8_of_match,\n+\t\t.of_match_table = cs42xx8_i2c_of_match,\n \t},\n \t.probe = cs42xx8_i2c_probe,\n \t.remove = cs42xx8_i2c_remove,\n--- a/sound/soc/codecs/cs42xx8.c\n+++ b/sound/soc/codecs/cs42xx8.c\n@@ -517,8 +517,10 @@ const struct of_device_id cs42xx8_of_mat\n \t{ .compatible = \"cirrus,cs42888\", .data = &cs42888_data, },\n \t{ /* sentinel */ }\n };\n+#if !IS_ENABLED(CONFIG_SND_SOC_CS42XX8_I2C)\n MODULE_DEVICE_TABLE(of, cs42xx8_of_match);\n EXPORT_SYMBOL_GPL(cs42xx8_of_match);\n+#endif\n \n int cs42xx8_probe(struct device *dev, struct regmap *regmap)\n {\n--- /dev/null\n+++ b/sound/soc/codecs/i-sabre-codec.c\n@@ -0,0 +1,392 @@\n+/*\n+ * Driver for I-Sabre Q2M\n+ *\n+ * Author: Satoru Kawase\n+ * Modified by: Xiao Qingyong\n+ * Modified by: JC BARBAUD (Mute)\n+ * Update kernel v4.18+ by : Audiophonics\n+ * \t\tCopyright 2018 Audiophonics\n+ *\n+ * This program is free software; you can redistribute it and/or\n+ * modify it under the terms of the GNU General Public License\n+ * version 2 as published by the Free Software Foundation.\n+ *\n+ * This program is distributed in the hope that it will be useful, but\n+ * WITHOUT ANY WARRANTY; without even the implied warranty of\n+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\n+ * General Public License for more details.\n+ */\n+\n+\n+#include <linux/init.h>\n+#include <linux/module.h>\n+#include <linux/regmap.h>\n+#include <linux/i2c.h>\n+#include <sound/soc.h>\n+#include <sound/pcm_params.h>\n+#include <sound/tlv.h>\n+\n+#include \"i-sabre-codec.h\"\n+\n+\n+/* I-Sabre Q2M Codec Private Data */\n+struct i_sabre_codec_priv {\n+\tstruct regmap *regmap;\n+\tunsigned int fmt;\n+};\n+\n+\n+/* I-Sabre Q2M Codec Default Register Value */\n+static const struct reg_default i_sabre_codec_reg_defaults[] = {\n+\t{ ISABRECODEC_REG_10, 0x00 },\n+\t{ ISABRECODEC_REG_20, 0x00 },\n+\t{ ISABRECODEC_REG_21, 0x00 },\n+\t{ ISABRECODEC_REG_22, 0x00 },\n+\t{ ISABRECODEC_REG_24, 0x00 },\n+};\n+\n+\n+static bool i_sabre_codec_writeable(struct device *dev, unsigned int reg)\n+{\n+\tswitch (reg) {\n+\tcase ISABRECODEC_REG_10:\n+\tcase ISABRECODEC_REG_20:\n+\tcase ISABRECODEC_REG_21:\n+\tcase ISABRECODEC_REG_22:\n+\tcase ISABRECODEC_REG_24:\n+\t\treturn true;\n+\n+\tdefault:\n+\t\treturn false;\n+\t}\n+}\n+\n+static bool i_sabre_codec_readable(struct device *dev, unsigned int reg)\n+{\n+\tswitch (reg) {\n+\tcase ISABRECODEC_REG_01:\n+\tcase ISABRECODEC_REG_02:\n+\tcase ISABRECODEC_REG_10:\n+\tcase ISABRECODEC_REG_20:\n+\tcase ISABRECODEC_REG_21:\n+\tcase ISABRECODEC_REG_22:\n+\tcase ISABRECODEC_REG_24:\n+\t\treturn true;\n+\n+\tdefault:\n+\t\treturn false;\n+\t}\n+}\n+\n+static bool i_sabre_codec_volatile(struct device *dev, unsigned int reg)\n+{\n+\tswitch (reg) {\n+\tcase ISABRECODEC_REG_01:\n+\tcase ISABRECODEC_REG_02:\n+\t\treturn true;\n+\n+\tdefault:\n+\t\treturn false;\n+\t}\n+}\n+\n+\n+/* Volume Scale */\n+static const DECLARE_TLV_DB_SCALE(volume_tlv, -10000, 100, 0);\n+\n+\n+/* Filter Type */\n+static const char * const fir_filter_type_texts[] = {\n+\t\"brick wall\",\n+\t\"corrected minimum phase fast\",\n+\t\"minimum phase slow\",\n+\t\"minimum phase fast\",\n+\t\"linear phase slow\",\n+\t\"linear phase fast\",\n+\t\"apodizing fast\",\n+};\n+\n+static SOC_ENUM_SINGLE_DECL(i_sabre_fir_filter_type_enum,\n+\t\t\t\tISABRECODEC_REG_22, 0, fir_filter_type_texts);\n+\n+\n+/* I2S / SPDIF Select */\n+static const char * const iis_spdif_sel_texts[] = {\n+\t\"I2S\",\n+\t\"SPDIF\",\n+};\n+\n+static SOC_ENUM_SINGLE_DECL(i_sabre_iis_spdif_sel_enum,\n+\t\t\t\tISABRECODEC_REG_24, 0, iis_spdif_sel_texts);\n+\n+\n+/* Control */\n+static const struct snd_kcontrol_new i_sabre_codec_controls[] = {\n+SOC_SINGLE_RANGE_TLV(\"Digital Playback Volume\", ISABRECODEC_REG_20, 0, 0, 100, 1, volume_tlv),\n+SOC_SINGLE(\"Digital Playback Switch\", ISABRECODEC_REG_21, 0, 1, 1),\n+SOC_ENUM(\"FIR Filter Type\", i_sabre_fir_filter_type_enum),\n+SOC_ENUM(\"I2S/SPDIF Select\", i_sabre_iis_spdif_sel_enum),\n+};\n+\n+\n+static const u32 i_sabre_codec_dai_rates_slave[] = {\n+\t8000, 11025, 16000, 22050, 32000,\n+\t44100, 48000, 64000, 88200, 96000,\n+\t176400, 192000, 352800, 384000,\n+\t705600, 768000, 1411200, 1536000\n+};\n+\n+static const struct snd_pcm_hw_constraint_list constraints_slave = {\n+\t.list  = i_sabre_codec_dai_rates_slave,\n+\t.count = ARRAY_SIZE(i_sabre_codec_dai_rates_slave),\n+};\n+\n+static int i_sabre_codec_dai_startup_slave(\n+\t\tstruct snd_pcm_substream *substream, struct snd_soc_dai *dai)\n+{\n+\tstruct snd_soc_component *component = dai->component;\n+\tint ret;\n+\n+\tret = snd_pcm_hw_constraint_list(substream->runtime,\n+\t\t\t0, SNDRV_PCM_HW_PARAM_RATE, &constraints_slave);\n+\tif (ret != 0) {\n+\t\tdev_err(component->card->dev, \"Failed to setup rates constraints: %d\\n\", ret);\n+\t}\n+\n+\treturn ret;\n+}\n+\n+static int i_sabre_codec_dai_startup(\n+\t\tstruct snd_pcm_substream *substream, struct snd_soc_dai *dai)\n+{\n+\tstruct snd_soc_component      *component = dai->component;\n+\tstruct i_sabre_codec_priv *i_sabre_codec\n+\t\t\t\t\t= snd_soc_component_get_drvdata(component);\n+\n+\tswitch (i_sabre_codec->fmt & SND_SOC_DAIFMT_MASTER_MASK) {\n+\tcase SND_SOC_DAIFMT_CBS_CFS:\n+\t\treturn i_sabre_codec_dai_startup_slave(substream, dai);\n+\n+\tdefault:\n+\t\treturn (-EINVAL);\n+\t}\n+}\n+\n+static int i_sabre_codec_hw_params(\n+\tstruct snd_pcm_substream *substream, struct snd_pcm_hw_params *params,\n+\tstruct snd_soc_dai *dai)\n+{\n+\tstruct snd_soc_component      *component = dai->component;\n+\tstruct i_sabre_codec_priv *i_sabre_codec\n+\t\t\t\t\t= snd_soc_component_get_drvdata(component);\n+\tunsigned int daifmt;\n+\tint format_width;\n+\n+\tdev_dbg(component->card->dev, \"hw_params %u Hz, %u channels\\n\",\n+\t\t\tparams_rate(params), params_channels(params));\n+\n+\t/* Check I2S Format (Bit Size) */\n+\tformat_width = snd_pcm_format_width(params_format(params));\n+\tif ((format_width != 32) && (format_width != 16)) {\n+\t\tdev_err(component->card->dev, \"Bad frame size: %d\\n\",\n+\t\t\t\tsnd_pcm_format_width(params_format(params)));\n+\t\treturn (-EINVAL);\n+\t}\n+\n+\t/* Check Slave Mode */\n+\tdaifmt = i_sabre_codec->fmt & SND_SOC_DAIFMT_MASTER_MASK;\n+\tif (daifmt != SND_SOC_DAIFMT_CBS_CFS) {\n+\t\treturn (-EINVAL);\n+\t}\n+\n+\t/* Notify Sampling Frequency  */\n+\tswitch (params_rate(params))\n+\t{\n+\tcase 44100:\n+\tcase 48000:\n+\tcase 88200:\n+\tcase 96000:\n+\tcase 176400:\n+\tcase 192000:\n+\t\tsnd_soc_component_update_bits(component, ISABRECODEC_REG_10, 0x01, 0x00);\n+\t\tbreak;\n+\n+\tcase 352800:\n+\tcase 384000:\n+\tcase 705600:\n+\tcase 768000:\n+\tcase 1411200:\n+\tcase 1536000:\n+\t\tsnd_soc_component_update_bits(component, ISABRECODEC_REG_10, 0x01, 0x01);\n+\t\tbreak;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int i_sabre_codec_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)\n+{\n+\tstruct snd_soc_component      *component = dai->component;\n+\tstruct i_sabre_codec_priv *i_sabre_codec\n+\t\t\t\t\t= snd_soc_component_get_drvdata(component);\n+\n+\t/* interface format */\n+\tswitch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {\n+\tcase SND_SOC_DAIFMT_I2S:\n+\t\tbreak;\n+\n+\tcase SND_SOC_DAIFMT_RIGHT_J:\n+\tcase SND_SOC_DAIFMT_LEFT_J:\n+\tdefault:\n+\t\treturn (-EINVAL);\n+\t}\n+\n+\t/* clock inversion */\n+\tif ((fmt & SND_SOC_DAIFMT_INV_MASK) != SND_SOC_DAIFMT_NB_NF) {\n+\t\treturn (-EINVAL);\n+\t}\n+\n+\t/* Set Audio Data Format */\n+\ti_sabre_codec->fmt = fmt;\n+\n+\treturn 0;\n+}\n+\n+static int i_sabre_codec_dac_mute(struct snd_soc_dai *dai, int mute, int direction)\n+{\n+\tstruct snd_soc_component *component = dai->component;\n+\n+\tif (mute) {\n+\t\tsnd_soc_component_update_bits(component, ISABRECODEC_REG_21, 0x01, 0x01);\n+\t} else {\n+\t\tsnd_soc_component_update_bits(component, ISABRECODEC_REG_21, 0x01, 0x00);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+\n+static const struct snd_soc_dai_ops i_sabre_codec_dai_ops = {\n+\t.startup      = i_sabre_codec_dai_startup,\n+\t.hw_params    = i_sabre_codec_hw_params,\n+\t.set_fmt      = i_sabre_codec_set_fmt,\n+\t.mute_stream  = i_sabre_codec_dac_mute,\n+};\n+\n+static struct snd_soc_dai_driver i_sabre_codec_dai = {\n+\t.name = \"i-sabre-codec-dai\",\n+\t.playback = {\n+\t\t.stream_name  = \"Playback\",\n+\t\t.channels_min = 2,\n+\t\t.channels_max = 2,\n+\t\t.rates = SNDRV_PCM_RATE_CONTINUOUS,\n+\t\t.rate_min = 8000,\n+\t\t.rate_max = 1536000,\n+\t\t.formats      = SNDRV_PCM_FMTBIT_S16_LE\n+\t\t\t\t| SNDRV_PCM_FMTBIT_S32_LE,\n+\t},\n+\t.ops = &i_sabre_codec_dai_ops,\n+};\n+\n+static struct snd_soc_component_driver i_sabre_codec_codec_driver = {\n+\t\t.controls         = i_sabre_codec_controls,\n+\t\t.num_controls     = ARRAY_SIZE(i_sabre_codec_controls),\n+};\n+\n+\n+static const struct regmap_config i_sabre_codec_regmap = {\n+\t.reg_bits         = 8,\n+\t.val_bits         = 8,\n+\t.max_register     = ISABRECODEC_MAX_REG,\n+\n+\t.reg_defaults     = i_sabre_codec_reg_defaults,\n+\t.num_reg_defaults = ARRAY_SIZE(i_sabre_codec_reg_defaults),\n+\n+\t.writeable_reg    = i_sabre_codec_writeable,\n+\t.readable_reg     = i_sabre_codec_readable,\n+\t.volatile_reg     = i_sabre_codec_volatile,\n+\n+\t.cache_type       = REGCACHE_RBTREE,\n+};\n+\n+\n+static int i_sabre_codec_probe(struct device *dev, struct regmap *regmap)\n+{\n+\tstruct i_sabre_codec_priv *i_sabre_codec;\n+\tint ret;\n+\n+\ti_sabre_codec = devm_kzalloc(dev, sizeof(*i_sabre_codec), GFP_KERNEL);\n+\tif (!i_sabre_codec) {\n+\t\tdev_err(dev, \"devm_kzalloc\");\n+\t\treturn (-ENOMEM);\n+\t}\n+\n+\ti_sabre_codec->regmap = regmap;\n+\n+\tdev_set_drvdata(dev, i_sabre_codec);\n+\n+\tret = snd_soc_register_component(dev,\n+\t\t\t&i_sabre_codec_codec_driver, &i_sabre_codec_dai, 1);\n+\tif (ret != 0) {\n+\t\tdev_err(dev, \"Failed to register CODEC: %d\\n\", ret);\n+\t\treturn ret;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static void i_sabre_codec_remove(struct device *dev)\n+{\n+\tsnd_soc_unregister_component(dev);\n+}\n+\n+\n+static int i_sabre_codec_i2c_probe(\n+\t\tstruct i2c_client *i2c, const struct i2c_device_id *id)\n+{\n+\tstruct regmap *regmap;\n+\n+\tregmap = devm_regmap_init_i2c(i2c, &i_sabre_codec_regmap);\n+\tif (IS_ERR(regmap)) {\n+\t\treturn PTR_ERR(regmap);\n+\t}\n+\n+\treturn i_sabre_codec_probe(&i2c->dev, regmap);\n+}\n+\n+static int i_sabre_codec_i2c_remove(struct i2c_client *i2c)\n+{\n+\ti_sabre_codec_remove(&i2c->dev);\n+\n+\treturn 0;\n+}\n+\n+\n+static const struct i2c_device_id i_sabre_codec_i2c_id[] = {\n+\t{ \"i-sabre-codec\", },\n+\t{ }\n+};\n+MODULE_DEVICE_TABLE(i2c, i_sabre_codec_i2c_id);\n+\n+static const struct of_device_id i_sabre_codec_of_match[] = {\n+\t{ .compatible = \"audiophonics,i-sabre-codec\", },\n+\t{ }\n+};\n+MODULE_DEVICE_TABLE(of, i_sabre_codec_of_match);\n+\n+static struct i2c_driver i_sabre_codec_i2c_driver = {\n+\t.driver = {\n+\t\t.name           = \"i-sabre-codec-i2c\",\n+\t\t.owner          = THIS_MODULE,\n+\t\t.of_match_table = of_match_ptr(i_sabre_codec_of_match),\n+\t},\n+\t.probe    = i_sabre_codec_i2c_probe,\n+\t.remove   = i_sabre_codec_i2c_remove,\n+\t.id_table = i_sabre_codec_i2c_id,\n+};\n+module_i2c_driver(i_sabre_codec_i2c_driver);\n+\n+\n+MODULE_DESCRIPTION(\"ASoC I-Sabre Q2M codec driver\");\n+MODULE_AUTHOR(\"Audiophonics <http://www.audiophonics.fr>\");\n+MODULE_LICENSE(\"GPL\");\n--- /dev/null\n+++ b/sound/soc/codecs/i-sabre-codec.h\n@@ -0,0 +1,42 @@\n+/*\n+ * Driver for I-Sabre Q2M\n+ *\n+ * Author: Satoru Kawase\n+ * Modified by: Xiao Qingyong\n+ *      Copyright 2018 Audiophonics\n+ *\n+ * This program is free software; you can redistribute it and/or\n+ * modify it under the terms of the GNU General Public License\n+ * version 2 as published by the Free Software Foundation.\n+ *\n+ * This program is distributed in the hope that it will be useful, but\n+ * WITHOUT ANY WARRANTY; without even the implied warranty of\n+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\n+ * General Public License for more details.\n+ */\n+\n+#ifndef _SND_SOC_ISABRECODEC\n+#define _SND_SOC_ISABRECODEC\n+\n+\n+/* ISABRECODEC Register Address */\n+#define ISABRECODEC_REG_01\t0x01\t/* Virtual Device ID  :  0x01 = es9038q2m */\n+#define ISABRECODEC_REG_02\t0x02\t/* API revision       :  0x01 = Revision 01 */\n+#define ISABRECODEC_REG_10\t0x10\t/* 0x01 = above 192kHz, 0x00 = otherwise */\n+#define ISABRECODEC_REG_20\t0x20\t/* 0 - 100 (decimal value, 0 = min., 100 = max.) */\n+#define ISABRECODEC_REG_21\t0x21\t/* 0x00 = Mute OFF, 0x01 = Mute ON */\n+#define ISABRECODEC_REG_22\t0x22\t\n+/*\n+   0x00 = brick wall,\n+   0x01 = corrected minimum phase fast,\n+   0x02 = minimum phase slow,\n+   0x03 = minimum phase fast,\n+   0x04 = linear phase slow,\n+   0x05 = linear phase fast,\n+   0x06 = apodizing fast,\n+*/\n+//#define ISABRECODEC_REG_23\t0x23\t/* reserved */\n+#define ISABRECODEC_REG_24\t0x24\t/* 0x00 = I2S, 0x01 = SPDIF */\n+#define ISABRECODEC_MAX_REG\t0x24\t/* Maximum Register Number */\n+\n+#endif /* _SND_SOC_ISABRECODEC */\n--- /dev/null\n+++ b/sound/soc/codecs/ma120x0p.c\n@@ -0,0 +1,1384 @@\n+// SPDX-License-Identifier: GPL-2.0-or-later\n+/*\n+ * ASoC Driver for Infineon Merus(TM) ma120x0p multi-level class-D amplifier\n+ *\n+ * Authors:\tAriel Muszkat <ariel.muszkat@gmail.com>\n+ * Jorgen Kragh Jakobsen <jorgen.kraghjakobsen@infineon.com>\n+ *\n+ * Copyright (C) 2019 Infineon Technologies AG\n+ *\n+ */\n+#include <linux/module.h>\n+#include <linux/moduleparam.h>\n+#include <linux/init.h>\n+#include <linux/delay.h>\n+#include <linux/pm_runtime.h>\n+#include <linux/i2c.h>\n+#include <linux/of_device.h>\n+#include <linux/spi/spi.h>\n+#include <linux/regmap.h>\n+#include <linux/regulator/consumer.h>\n+#include <linux/slab.h>\n+#include <linux/gpio/consumer.h>\n+#include <linux/gpio.h>\n+#include <sound/core.h>\n+#include <sound/pcm.h>\n+#include <sound/pcm_params.h>\n+#include <sound/soc.h>\n+#include <sound/soc-dapm.h>\n+#include <sound/initval.h>\n+#include <sound/tlv.h>\n+#include <linux/interrupt.h>\n+\n+#include <linux/kernel.h>\n+#include <linux/string.h>\n+#include <linux/fs.h>\n+#include <linux/uaccess.h>\n+\n+#ifndef _MA120X0P_\n+#define _MA120X0P_\n+//------------------------------------------------------------------manualPM---\n+// Select Manual PowerMode control\n+#define ma_manualpm__a 0\n+#define ma_manualpm__len 1\n+#define ma_manualpm__mask 0x40\n+#define ma_manualpm__shift 0x06\n+#define ma_manualpm__reset 0x00\n+//--------------------------------------------------------------------pm_man---\n+// manual selected power mode\n+#define ma_pm_man__a 0\n+#define ma_pm_man__len 2\n+#define ma_pm_man__mask 0x30\n+#define ma_pm_man__shift 0x04\n+#define ma_pm_man__reset 0x03\n+//------------------------------------------ ----------------------mthr_1to2---\n+// mod. index threshold value for pm1=>pm2 change.\n+#define ma_mthr_1to2__a 1\n+#define ma_mthr_1to2__len 8\n+#define ma_mthr_1to2__mask 0xff\n+#define ma_mthr_1to2__shift 0x00\n+#define ma_mthr_1to2__reset 0x3c\n+//-----------------------------------------------------------------mthr_2to1---\n+// mod. index threshold value for pm2=>pm1 change.\n+#define ma_mthr_2to1__a 2\n+#define ma_mthr_2to1__len 8\n+#define ma_mthr_2to1__mask 0xff\n+#define ma_mthr_2to1__shift 0x00\n+#define ma_mthr_2to1__reset 0x32\n+//-----------------------------------------------------------------mthr_2to3---\n+// mod. index threshold value for pm2=>pm3 change.\n+#define ma_mthr_2to3__a 3\n+#define ma_mthr_2to3__len 8\n+#define ma_mthr_2to3__mask 0xff\n+#define ma_mthr_2to3__shift 0x00\n+#define ma_mthr_2to3__reset 0x5a\n+//-----------------------------------------------------------------mthr_3to2---\n+// mod. index threshold value for pm3=>pm2 change.\n+#define ma_mthr_3to2__a 4\n+#define ma_mthr_3to2__len 8\n+#define ma_mthr_3to2__mask 0xff\n+#define ma_mthr_3to2__shift 0x00\n+#define ma_mthr_3to2__reset 0x50\n+//-------------------------------------------------------------pwmclkdiv_nom---\n+// pwm default clock divider value\n+#define ma_pwmclkdiv_nom__a 8\n+#define ma_pwmclkdiv_nom__len 8\n+#define ma_pwmclkdiv_nom__mask 0xff\n+#define ma_pwmclkdiv_nom__shift 0x00\n+#define ma_pwmclkdiv_nom__reset 0x26\n+//--------- ----------------------------------------------------ocp_latch_en---\n+// high to use permanently latching level-2 ocp\n+#define ma_ocp_latch_en__a 10\n+#define ma_ocp_latch_en__len 1\n+#define ma_ocp_latch_en__mask 0x02\n+#define ma_ocp_latch_en__shift 0x01\n+#define ma_ocp_latch_en__reset 0x00\n+//---------------------------------------------------------------lf_clamp_en---\n+// high (default) to enable lf int2+3 clamping on clip\n+#define ma_lf_clamp_en__a 10\n+#define ma_lf_clamp_en__len 1\n+#define ma_lf_clamp_en__mask 0x80\n+#define ma_lf_clamp_en__shift 0x07\n+#define ma_lf_clamp_en__reset 0x00\n+//-------------------------------------------------------pmcfg_btl_b.modtype---\n+//\n+#define ma_pmcfg_btl_b__modtype__a 18\n+#define ma_pmcfg_btl_b__modtype__len 2\n+#define ma_pmcfg_btl_b__modtype__mask 0x18\n+#define ma_pmcfg_btl_b__modtype__shift 0x03\n+#define ma_pmcfg_btl_b__modtype__reset 0x02\n+//-------------------------------------------------------pmcfg_btl_b.freqdiv---\n+#define ma_pmcfg_btl_b__freqdiv__a 18\n+#define ma_pmcfg_btl_b__freqdiv__len 2\n+#define ma_pmcfg_btl_b__freqdiv__mask 0x06\n+#define ma_pmcfg_btl_b__freqdiv__shift 0x01\n+#define ma_pmcfg_btl_b__freqdiv__reset 0x01\n+//----------------------------------------------------pmcfg_btl_b.lf_gain_ol---\n+//\n+#define ma_pmcfg_btl_b__lf_gain_ol__a 18\n+#define ma_pmcfg_btl_b__lf_gain_ol__len 1\n+#define ma_pmcfg_btl_b__lf_gain_ol__mask 0x01\n+#define ma_pmcfg_btl_b__lf_gain_ol__shift 0x00\n+#define ma_pmcfg_btl_b__lf_gain_ol__reset 0x01\n+//-------------------------------------------------------pmcfg_btl_c.freqdiv---\n+//\n+#define ma_pmcfg_btl_c__freqdiv__a 19\n+#define ma_pmcfg_btl_c__freqdiv__len 2\n+#define ma_pmcfg_btl_c__freqdiv__mask 0x06\n+#define ma_pmcfg_btl_c__freqdiv__shift 0x01\n+#define ma_pmcfg_btl_c__freqdiv__reset 0x01\n+//-------------------------------------------------------pmcfg_btl_c.modtype---\n+//\n+#define ma_pmcfg_btl_c__modtype__a 19\n+#define ma_pmcfg_btl_c__modtype__len 2\n+#define ma_pmcfg_btl_c__modtype__mask 0x18\n+#define ma_pmcfg_btl_c__modtype__shift 0x03\n+#define ma_pmcfg_btl_c__modtype__reset 0x01\n+//----------------------------------------------------pmcfg_btl_c.lf_gain_ol---\n+//\n+#define ma_pmcfg_btl_c__lf_gain_ol__a 19\n+#define ma_pmcfg_btl_c__lf_gain_ol__len 1\n+#define ma_pmcfg_btl_c__lf_gain_ol__mask 0x01\n+#define ma_pmcfg_btl_c__lf_gain_ol__shift 0x00\n+#define ma_pmcfg_btl_c__lf_gain_ol__reset 0x00\n+//-------------------------------------------------------pmcfg_btl_d.modtype---\n+//\n+#define ma_pmcfg_btl_d__modtype__a 20\n+#define ma_pmcfg_btl_d__modtype__len 2\n+#define ma_pmcfg_btl_d__modtype__mask 0x18\n+#define ma_pmcfg_btl_d__modtype__shift 0x03\n+#define ma_pmcfg_btl_d__modtype__reset 0x02\n+//-------------------------------------------------------pmcfg_btl_d.freqdiv---\n+//\n+#define ma_pmcfg_btl_d__freqdiv__a 20\n+#define ma_pmcfg_btl_d__freqdiv__len 2\n+#define ma_pmcfg_btl_d__freqdiv__mask 0x06\n+#define ma_pmcfg_btl_d__freqdiv__shift 0x01\n+#define ma_pmcfg_btl_d__freqdiv__reset 0x02\n+//----------------------------------------------------pmcfg_btl_d.lf_gain_ol---\n+//\n+#define ma_pmcfg_btl_d__lf_gain_ol__a 20\n+#define ma_pmcfg_btl_d__lf_gain_ol__len 1\n+#define ma_pmcfg_btl_d__lf_gain_ol__mask 0x01\n+#define ma_pmcfg_btl_d__lf_gain_ol__shift 0x00\n+#define ma_pmcfg_btl_d__lf_gain_ol__reset 0x00\n+//------------ -------------------------------------------pmcfg_se_a.modtype---\n+//\n+#define ma_pmcfg_se_a__modtype__a 21\n+#define ma_pmcfg_se_a__modtype__len 2\n+#define ma_pmcfg_se_a__modtype__mask 0x18\n+#define ma_pmcfg_se_a__modtype__shift 0x03\n+#define ma_pmcfg_se_a__modtype__reset 0x01\n+//--------------------------------------------------------pmcfg_se_a.freqdiv---\n+//\n+#define ma_pmcfg_se_a__freqdiv__a 21\n+#define ma_pmcfg_se_a__freqdiv__len 2\n+#define ma_pmcfg_se_a__freqdiv__mask 0x06\n+#define ma_pmcfg_se_a__freqdiv__shift 0x01\n+#define ma_pmcfg_se_a__freqdiv__reset 0x00\n+//-----------------------------------------------------pmcfg_se_a.lf_gain_ol---\n+//\n+#define ma_pmcfg_se_a__lf_gain_ol__a 21\n+#define ma_pmcfg_se_a__lf_gain_ol__len 1\n+#define ma_pmcfg_se_a__lf_gain_ol__mask 0x01\n+#define ma_pmcfg_se_a__lf_gain_ol__shift 0x00\n+#define ma_pmcfg_se_a__lf_gain_ol__reset 0x01\n+//-----------------------------------------------------pmcfg_se_b.lf_gain_ol---\n+//\n+#define ma_pmcfg_se_b__lf_gain_ol__a 22\n+#define ma_pmcfg_se_b__lf_gain_ol__len 1\n+#define ma_pmcfg_se_b__lf_gain_ol__mask 0x01\n+#define ma_pmcfg_se_b__lf_gain_ol__shift 0x00\n+#define ma_pmcfg_se_b__lf_gain_ol__reset 0x00\n+//--------------------------------------------------------pmcfg_se_b.freqdiv---\n+//\n+#define ma_pmcfg_se_b__freqdiv__a 22\n+#define ma_pmcfg_se_b__freqdiv__len 2\n+#define ma_pmcfg_se_b__freqdiv__mask 0x06\n+#define ma_pmcfg_se_b__freqdiv__shift 0x01\n+#define ma_pmcfg_se_b__freqdiv__reset 0x01\n+//--------------------------------------------------------pmcfg_se_b.modtype---\n+//\n+#define ma_pmcfg_se_b__modtype__a 22\n+#define ma_pmcfg_se_b__modtype__len 2\n+#define ma_pmcfg_se_b__modtype__mask 0x18\n+#define ma_pmcfg_se_b__modtype__shift 0x03\n+#define ma_pmcfg_se_b__modtype__reset 0x01\n+//----------------------------------------------------------balwaitcount_pm1---\n+// pm1 balancing period.\n+#define ma_balwaitcount_pm1__a 23\n+#define ma_balwaitcount_pm1__len 8\n+#define ma_balwaitcount_pm1__mask 0xff\n+#define ma_balwaitcount_pm1__shift 0x00\n+#define ma_balwaitcount_pm1__reset 0x14\n+//----------------------------------------------------------balwaitcount_pm2---\n+// pm2 balancing period.\n+#define ma_balwaitcount_pm2__a 24\n+#define ma_balwaitcount_pm2__len 8\n+#define ma_balwaitcount_pm2__mask 0xff\n+#define ma_balwaitcount_pm2__shift 0x00\n+#define ma_balwaitcount_pm2__reset 0x14\n+//----------------------------------------------------------balwaitcount_pm3---\n+// pm3 balancing period.\n+#define ma_balwaitcount_pm3__a 25\n+#define ma_balwaitcount_pm3__len 8\n+#define ma_balwaitcount_pm3__mask 0xff\n+#define ma_balwaitcount_pm3__shift 0x00\n+#define ma_balwaitcount_pm3__reset 0x1a\n+//-------------------------------------------------------------usespread_pm1---\n+// pm1 pwm spread-spectrum mode on/off.\n+#define ma_usespread_pm1__a 26\n+#define ma_usespread_pm1__len 1\n+#define ma_usespread_pm1__mask 0x40\n+#define ma_usespread_pm1__shift 0x06\n+#define ma_usespread_pm1__reset 0x00\n+//---------------------------------------------------------------dtsteps_pm1---\n+// pm1 dead time setting [10ns steps].\n+#define ma_dtsteps_pm1__a 26\n+#define ma_dtsteps_pm1__len 3\n+#define ma_dtsteps_pm1__mask 0x38\n+#define ma_dtsteps_pm1__shift 0x03\n+#define ma_dtsteps_pm1__reset 0x04\n+//---------------------------------------------------------------baltype_pm1---\n+// pm1 balancing sensor scheme.\n+#define ma_baltype_pm1__a 26\n+#define ma_baltype_pm1__len 3\n+#define ma_baltype_pm1__mask 0x07\n+#define ma_baltype_pm1__shift 0x00\n+#define ma_baltype_pm1__reset 0x00\n+//-------------------------------------------------------------usespread_pm2---\n+// pm2 pwm spread-spectrum mode on/off.\n+#define ma_usespread_pm2__a 27\n+#define ma_usespread_pm2__len 1\n+#define ma_usespread_pm2__mask 0x40\n+#define ma_usespread_pm2__shift 0x06\n+#define ma_usespread_pm2__reset 0x00\n+//---------------------------------------------------------------dtsteps_pm2---\n+// pm2 dead time setting [10ns steps].\n+#define ma_dtsteps_pm2__a 27\n+#define ma_dtsteps_pm2__len 3\n+#define ma_dtsteps_pm2__mask 0x38\n+#define ma_dtsteps_pm2__shift 0x03\n+#define ma_dtsteps_pm2__reset 0x03\n+//---------------------------------------------------------------baltype_pm2---\n+// pm2 balancing sensor scheme.\n+#define ma_baltype_pm2__a 27\n+#define ma_baltype_pm2__len 3\n+#define ma_baltype_pm2__mask 0x07\n+#define ma_baltype_pm2__shift 0x00\n+#define ma_baltype_pm2__reset 0x01\n+//-------------------------------------------------------------usespread_pm3---\n+// pm3 pwm spread-spectrum mode on/off.\n+#define ma_usespread_pm3__a 28\n+#define ma_usespread_pm3__len 1\n+#define ma_usespread_pm3__mask 0x40\n+#define ma_usespread_pm3__shift 0x06\n+#define ma_usespread_pm3__reset 0x00\n+//---------------------------------------------------------------dtsteps_pm3---\n+// pm3 dead time setting [10ns steps].\n+#define ma_dtsteps_pm3__a 28\n+#define ma_dtsteps_pm3__len 3\n+#define ma_dtsteps_pm3__mask 0x38\n+#define ma_dtsteps_pm3__shift 0x03\n+#define ma_dtsteps_pm3__reset 0x01\n+//---------------------------------------------------------------baltype_pm3---\n+// pm3 balancing sensor scheme.\n+#define ma_baltype_pm3__a 28\n+#define ma_baltype_pm3__len 3\n+#define ma_baltype_pm3__mask 0x07\n+#define ma_baltype_pm3__shift 0x00\n+#define ma_baltype_pm3__reset 0x03\n+//-----------------------------------------------------------------pmprofile---\n+// pm profile select. valid presets: 0-1-2-3-4. 5=> custom profile.\n+#define ma_pmprofile__a 29\n+#define ma_pmprofile__len 3\n+#define ma_pmprofile__mask 0x07\n+#define ma_pmprofile__shift 0x00\n+#define ma_pmprofile__reset 0x00\n+//-------------------------------------------------------------------pm3_man---\n+// custom profile pm3 contents. 0=>a,  1=>b,  2=>c,  3=>d\n+#define ma_pm3_man__a 30\n+#define ma_pm3_man__len 2\n+#define ma_pm3_man__mask 0x30\n+#define ma_pm3_man__shift 0x04\n+#define ma_pm3_man__reset 0x02\n+//-------------------------------------------------------------------pm2_man---\n+// custom profile pm2 contents. 0=>a,  1=>b,  2=>c,  3=>d\n+#define ma_pm2_man__a 30\n+#define ma_pm2_man__len 2\n+#define ma_pm2_man__mask 0x0c\n+#define ma_pm2_man__shift 0x02\n+#define ma_pm2_man__reset 0x03\n+//-------------------------------------------------------------------pm1_man---\n+// custom profile pm1 contents. 0=>a,  1=>b,  2=>c,  3=>d\n+#define ma_pm1_man__a 30\n+#define ma_pm1_man__len 2\n+#define ma_pm1_man__mask 0x03\n+#define ma_pm1_man__shift 0x00\n+#define ma_pm1_man__reset 0x03\n+//-----------------------------------------------------------ocp_latch_clear---\n+// low-high clears current ocp latched condition.\n+#define ma_ocp_latch_clear__a 32\n+#define ma_ocp_latch_clear__len 1\n+#define ma_ocp_latch_clear__mask 0x80\n+#define ma_ocp_latch_clear__shift 0x07\n+#define ma_ocp_latch_clear__reset 0x00\n+//-------------------------------------------------------------audio_in_mode---\n+// audio input mode; 0-1-2-3-4-5\n+#define ma_audio_in_mode__a 37\n+#define ma_audio_in_mode__len 3\n+#define ma_audio_in_mode__mask 0xe0\n+#define ma_audio_in_mode__shift 0x05\n+#define ma_audio_in_mode__reset 0x00\n+//-----------------------------------------------------------------eh_dcshdn---\n+// high to enable dc protection\n+#define ma_eh_dcshdn__a 38\n+#define ma_eh_dcshdn__len 1\n+#define ma_eh_dcshdn__mask 0x04\n+#define ma_eh_dcshdn__shift 0x02\n+#define ma_eh_dcshdn__reset 0x01\n+//---------------------------------------------------------audio_in_mode_ext---\n+// if set,  audio_in_mode is controlled from audio_in_mode register. if not set\n+//audio_in_mode is set from fuse bank setting\n+#define ma_audio_in_mode_ext__a 39\n+#define ma_audio_in_mode_ext__len 1\n+#define ma_audio_in_mode_ext__mask 0x20\n+#define ma_audio_in_mode_ext__shift 0x05\n+#define ma_audio_in_mode_ext__reset 0x00\n+//------------------------------------------------------------------eh_clear---\n+// flip to clear error registers\n+#define ma_eh_clear__a 45\n+#define ma_eh_clear__len 1\n+#define ma_eh_clear__mask 0x04\n+#define ma_eh_clear__shift 0x02\n+#define ma_eh_clear__reset 0x00\n+//----------------------------------------------------------thermal_compr_en---\n+// enable otw-contr.  input compression?\n+#define ma_thermal_compr_en__a 45\n+#define ma_thermal_compr_en__len 1\n+#define ma_thermal_compr_en__mask 0x20\n+#define ma_thermal_compr_en__shift 0x05\n+#define ma_thermal_compr_en__reset 0x01\n+//---------------------------------------------------------------system_mute---\n+// 1 = mute system,  0 = normal operation\n+#define ma_system_mute__a 45\n+#define ma_system_mute__len 1\n+#define ma_system_mute__mask 0x40\n+#define ma_system_mute__shift 0x06\n+#define ma_system_mute__reset 0x00\n+//------------------------------------------------------thermal_compr_max_db---\n+// audio limiter max thermal reduction\n+#define ma_thermal_compr_max_db__a 46\n+#define ma_thermal_compr_max_db__len 3\n+#define ma_thermal_compr_max_db__mask 0x07\n+#define ma_thermal_compr_max_db__shift 0x00\n+#define ma_thermal_compr_max_db__reset 0x04\n+//---------------------------------------------------------audio_proc_enable---\n+// enable audio proc,  bypass if not enabled\n+#define ma_audio_proc_enable__a 53\n+#define ma_audio_proc_enable__len 1\n+#define ma_audio_proc_enable__mask 0x08\n+#define ma_audio_proc_enable__shift 0x03\n+#define ma_audio_proc_enable__reset 0x00\n+//--------------------------------------------------------audio_proc_release---\n+// 00:slow,  01:normal,  10:fast\n+#define ma_audio_proc_release__a 53\n+#define ma_audio_proc_release__len 2\n+#define ma_audio_proc_release__mask 0x30\n+#define ma_audio_proc_release__shift 0x04\n+#define ma_audio_proc_release__reset 0x00\n+//---------------------------------------------------------audio_proc_attack---\n+// 00:slow,  01:normal,  10:fast\n+#define ma_audio_proc_attack__a 53\n+#define ma_audio_proc_attack__len 2\n+#define ma_audio_proc_attack__mask 0xc0\n+#define ma_audio_proc_attack__shift 0x06\n+#define ma_audio_proc_attack__reset 0x00\n+//----------------------------------------------------------------i2s_format---\n+// i2s basic data format,  000 = std. i2s,  001 = left justified (default)\n+#define ma_i2s_format__a 53\n+#define ma_i2s_format__len 3\n+#define ma_i2s_format__mask 0x07\n+#define ma_i2s_format__shift 0x00\n+#define ma_i2s_format__reset 0x01\n+//--------------------------------------------------audio_proc_limiterenable---\n+// 1: enable limiter,  0: disable limiter\n+#define ma_audio_proc_limiterenable__a 54\n+#define ma_audio_proc_limiterenable__len 1\n+#define ma_audio_proc_limiterenable__mask 0x40\n+#define ma_audio_proc_limiterenable__shift 0x06\n+#define ma_audio_proc_limiterenable__reset 0x00\n+//-----------------------------------------------------------audio_proc_mute---\n+// 1: mute,  0: unmute\n+#define ma_audio_proc_mute__a 54\n+#define ma_audio_proc_mute__len 1\n+#define ma_audio_proc_mute__mask 0x80\n+#define ma_audio_proc_mute__shift 0x07\n+#define ma_audio_proc_mute__reset 0x00\n+//---------------------------------------------------------------i2s_sck_pol---\n+// i2s sck polarity cfg. 0 = rising edge data change\n+#define ma_i2s_sck_pol__a 54\n+#define ma_i2s_sck_pol__len 1\n+#define ma_i2s_sck_pol__mask 0x01\n+#define ma_i2s_sck_pol__shift 0x00\n+#define ma_i2s_sck_pol__reset 0x01\n+//-------------------------------------------------------------i2s_framesize---\n+// i2s word length. 00 = 32bit,  01 = 24bit\n+#define ma_i2s_framesize__a 54\n+#define ma_i2s_framesize__len 2\n+#define ma_i2s_framesize__mask 0x18\n+#define ma_i2s_framesize__shift 0x03\n+#define ma_i2s_framesize__reset 0x00\n+//----------------------------------------------------------------i2s_ws_pol---\n+// i2s ws polarity. 0 = low first\n+#define ma_i2s_ws_pol__a 54\n+#define ma_i2s_ws_pol__len 1\n+#define ma_i2s_ws_pol__mask 0x02\n+#define ma_i2s_ws_pol__shift 0x01\n+#define ma_i2s_ws_pol__reset 0x00\n+//-----------------------------------------------------------------i2s_order---\n+// i2s word bit order. 0 = msb first\n+#define ma_i2s_order__a 54\n+#define ma_i2s_order__len 1\n+#define ma_i2s_order__mask 0x04\n+#define ma_i2s_order__shift 0x02\n+#define ma_i2s_order__reset 0x00\n+//------------------------------------------------------------i2s_rightfirst---\n+// i2s l/r word order; 0 = left first\n+#define ma_i2s_rightfirst__a 54\n+#define ma_i2s_rightfirst__len 1\n+#define ma_i2s_rightfirst__mask 0x20\n+#define ma_i2s_rightfirst__shift 0x05\n+#define ma_i2s_rightfirst__reset 0x00\n+//-------------------------------------------------------------vol_db_master---\n+// master volume db\n+#define ma_vol_db_master__a 64\n+#define ma_vol_db_master__len 8\n+#define ma_vol_db_master__mask 0xff\n+#define ma_vol_db_master__shift 0x00\n+#define ma_vol_db_master__reset 0x18\n+//------------------------------------------------------------vol_lsb_master---\n+// master volume lsb 1/4 steps\n+#define ma_vol_lsb_master__a 65\n+#define ma_vol_lsb_master__len 2\n+#define ma_vol_lsb_master__mask 0x03\n+#define ma_vol_lsb_master__shift 0x00\n+#define ma_vol_lsb_master__reset 0x00\n+//----------------------------------------------------------------vol_db_ch0---\n+// volume channel 0\n+#define ma_vol_db_ch0__a 66\n+#define ma_vol_db_ch0__len 8\n+#define ma_vol_db_ch0__mask 0xff\n+#define ma_vol_db_ch0__shift 0x00\n+#define ma_vol_db_ch0__reset 0x18\n+//----------------------------------------------------------------vol_db_ch1---\n+// volume channel 1\n+#define ma_vol_db_ch1__a 67\n+#define ma_vol_db_ch1__len 8\n+#define ma_vol_db_ch1__mask 0xff\n+#define ma_vol_db_ch1__shift 0x00\n+#define ma_vol_db_ch1__reset 0x18\n+//----------------------------------------------------------------vol_db_ch2---\n+// volume channel 2\n+#define ma_vol_db_ch2__a 68\n+#define ma_vol_db_ch2__len 8\n+#define ma_vol_db_ch2__mask 0xff\n+#define ma_vol_db_ch2__shift 0x00\n+#define ma_vol_db_ch2__reset 0x18\n+//----------------------------------------------------------------vol_db_ch3---\n+// volume channel 3\n+#define ma_vol_db_ch3__a 69\n+#define ma_vol_db_ch3__len 8\n+#define ma_vol_db_ch3__mask 0xff\n+#define ma_vol_db_ch3__shift 0x00\n+#define ma_vol_db_ch3__reset 0x18\n+//---------------------------------------------------------------vol_lsb_ch0---\n+// volume channel 1 - 1/4 steps\n+#define ma_vol_lsb_ch0__a 70\n+#define ma_vol_lsb_ch0__len 2\n+#define ma_vol_lsb_ch0__mask 0x03\n+#define ma_vol_lsb_ch0__shift 0x00\n+#define ma_vol_lsb_ch0__reset 0x00\n+//---------------------------------------------------------------vol_lsb_ch1---\n+// volume channel 3 - 1/4 steps\n+#define ma_vol_lsb_ch1__a 70\n+#define ma_vol_lsb_ch1__len 2\n+#define ma_vol_lsb_ch1__mask 0x0c\n+#define ma_vol_lsb_ch1__shift 0x02\n+#define ma_vol_lsb_ch1__reset 0x00\n+//---------------------------------------------------------------vol_lsb_ch2---\n+// volume channel 2 - 1/4 steps\n+#define ma_vol_lsb_ch2__a 70\n+#define ma_vol_lsb_ch2__len 2\n+#define ma_vol_lsb_ch2__mask 0x30\n+#define ma_vol_lsb_ch2__shift 0x04\n+#define ma_vol_lsb_ch2__reset 0x00\n+//---------------------------------------------------------------vol_lsb_ch3---\n+// volume channel 3 - 1/4 steps\n+#define ma_vol_lsb_ch3__a 70\n+#define ma_vol_lsb_ch3__len 2\n+#define ma_vol_lsb_ch3__mask 0xc0\n+#define ma_vol_lsb_ch3__shift 0x06\n+#define ma_vol_lsb_ch3__reset 0x00\n+//----------------------------------------------------------------thr_db_ch0---\n+// thr_db channel 0\n+#define ma_thr_db_ch0__a 71\n+#define ma_thr_db_ch0__len 8\n+#define ma_thr_db_ch0__mask 0xff\n+#define ma_thr_db_ch0__shift 0x00\n+#define ma_thr_db_ch0__reset 0x18\n+//----------------------------------------------------------------thr_db_ch1---\n+// thr db ch1\n+#define ma_thr_db_ch1__a 72\n+#define ma_thr_db_ch1__len 8\n+#define ma_thr_db_ch1__mask 0xff\n+#define ma_thr_db_ch1__shift 0x00\n+#define ma_thr_db_ch1__reset 0x18\n+//----------------------------------------------------------------thr_db_ch2---\n+// thr db ch2\n+#define ma_thr_db_ch2__a 73\n+#define ma_thr_db_ch2__len 8\n+#define ma_thr_db_ch2__mask 0xff\n+#define ma_thr_db_ch2__shift 0x00\n+#define ma_thr_db_ch2__reset 0x18\n+//----------------------------------------------------------------thr_db_ch3---\n+// threshold db ch3\n+#define ma_thr_db_ch3__a 74\n+#define ma_thr_db_ch3__len 8\n+#define ma_thr_db_ch3__mask 0xff\n+#define ma_thr_db_ch3__shift 0x00\n+#define ma_thr_db_ch3__reset 0x18\n+//---------------------------------------------------------------thr_lsb_ch0---\n+// thr lsb ch0\n+#define ma_thr_lsb_ch0__a 75\n+#define ma_thr_lsb_ch0__len 2\n+#define ma_thr_lsb_ch0__mask 0x03\n+#define ma_thr_lsb_ch0__shift 0x00\n+#define ma_thr_lsb_ch0__reset 0x00\n+//---------------------------------------------------------------thr_lsb_ch1---\n+// thr lsb ch1\n+#define ma_thr_lsb_ch1__a 75\n+#define ma_thr_lsb_ch1__len 2\n+#define ma_thr_lsb_ch1__mask 0x0c\n+#define ma_thr_lsb_ch1__shift 0x02\n+#define ma_thr_lsb_ch1__reset 0x00\n+//---------------------------------------------------------------thr_lsb_ch2---\n+// thr lsb ch2 1/4 db step\n+#define ma_thr_lsb_ch2__a 75\n+#define ma_thr_lsb_ch2__len 2\n+#define ma_thr_lsb_ch2__mask 0x30\n+#define ma_thr_lsb_ch2__shift 0x04\n+#define ma_thr_lsb_ch2__reset 0x00\n+//---------------------------------------------------------------thr_lsb_ch3---\n+// threshold lsb ch3\n+#define ma_thr_lsb_ch3__a 75\n+#define ma_thr_lsb_ch3__len 2\n+#define ma_thr_lsb_ch3__mask 0xc0\n+#define ma_thr_lsb_ch3__shift 0x06\n+#define ma_thr_lsb_ch3__reset 0x00\n+//-----------------------------------------------------------dcu_mon0.pm_mon---\n+// power mode monitor channel 0\n+#define ma_dcu_mon0__pm_mon__a 96\n+#define ma_dcu_mon0__pm_mon__len 2\n+#define ma_dcu_mon0__pm_mon__mask 0x03\n+#define ma_dcu_mon0__pm_mon__shift 0x00\n+#define ma_dcu_mon0__pm_mon__reset 0x00\n+//-----------------------------------------------------dcu_mon0.freqmode_mon---\n+// frequence mode monitor channel 0\n+#define ma_dcu_mon0__freqmode_mon__a 96\n+#define ma_dcu_mon0__freqmode_mon__len 3\n+#define ma_dcu_mon0__freqmode_mon__mask 0x70\n+#define ma_dcu_mon0__freqmode_mon__shift 0x04\n+#define ma_dcu_mon0__freqmode_mon__reset 0x00\n+//-------------------------------------------------------dcu_mon0.pps_passed---\n+// dcu0 pps completion indicator\n+#define ma_dcu_mon0__pps_passed__a 96\n+#define ma_dcu_mon0__pps_passed__len 1\n+#define ma_dcu_mon0__pps_passed__mask 0x80\n+#define ma_dcu_mon0__pps_passed__shift 0x07\n+#define ma_dcu_mon0__pps_passed__reset 0x00\n+//----------------------------------------------------------dcu_mon0.ocp_mon---\n+// ocp monitor channel 0\n+#define ma_dcu_mon0__ocp_mon__a 97\n+#define ma_dcu_mon0__ocp_mon__len 1\n+#define ma_dcu_mon0__ocp_mon__mask 0x01\n+#define ma_dcu_mon0__ocp_mon__shift 0x00\n+#define ma_dcu_mon0__ocp_mon__reset 0x00\n+//--------------------------------------------------------dcu_mon0.vcfly1_ok---\n+// cfly1 protection monitor channel 0.\n+#define ma_dcu_mon0__vcfly1_ok__a 97\n+#define ma_dcu_mon0__vcfly1_ok__len 1\n+#define ma_dcu_mon0__vcfly1_ok__mask 0x02\n+#define ma_dcu_mon0__vcfly1_ok__shift 0x01\n+#define ma_dcu_mon0__vcfly1_ok__reset 0x00\n+//--------------------------------------------------------dcu_mon0.vcfly2_ok---\n+// cfly2 protection monitor channel 0.\n+#define ma_dcu_mon0__vcfly2_ok__a 97\n+#define ma_dcu_mon0__vcfly2_ok__len 1\n+#define ma_dcu_mon0__vcfly2_ok__mask 0x04\n+#define ma_dcu_mon0__vcfly2_ok__shift 0x02\n+#define ma_dcu_mon0__vcfly2_ok__reset 0x00\n+//----------------------------------------------------------dcu_mon0.pvdd_ok---\n+// dcu0 pvdd monitor\n+#define ma_dcu_mon0__pvdd_ok__a 97\n+#define ma_dcu_mon0__pvdd_ok__len 1\n+#define ma_dcu_mon0__pvdd_ok__mask 0x08\n+#define ma_dcu_mon0__pvdd_ok__shift 0x03\n+#define ma_dcu_mon0__pvdd_ok__reset 0x00\n+//-----------------------------------------------------------dcu_mon0.vdd_ok---\n+// dcu0 vdd monitor\n+#define ma_dcu_mon0__vdd_ok__a 97\n+#define ma_dcu_mon0__vdd_ok__len 1\n+#define ma_dcu_mon0__vdd_ok__mask 0x10\n+#define ma_dcu_mon0__vdd_ok__shift 0x04\n+#define ma_dcu_mon0__vdd_ok__reset 0x00\n+//-------------------------------------------------------------dcu_mon0.mute---\n+// dcu0 mute monitor\n+#define ma_dcu_mon0__mute__a 97\n+#define ma_dcu_mon0__mute__len 1\n+#define ma_dcu_mon0__mute__mask 0x20\n+#define ma_dcu_mon0__mute__shift 0x05\n+#define ma_dcu_mon0__mute__reset 0x00\n+//------------------------------------------------------------dcu_mon0.m_mon---\n+// m sense monitor channel 0\n+#define ma_dcu_mon0__m_mon__a 98\n+#define ma_dcu_mon0__m_mon__len 8\n+#define ma_dcu_mon0__m_mon__mask 0xff\n+#define ma_dcu_mon0__m_mon__shift 0x00\n+#define ma_dcu_mon0__m_mon__reset 0x00\n+//-----------------------------------------------------------dcu_mon1.pm_mon---\n+// power mode monitor channel 1\n+#define ma_dcu_mon1__pm_mon__a 100\n+#define ma_dcu_mon1__pm_mon__len 2\n+#define ma_dcu_mon1__pm_mon__mask 0x03\n+#define ma_dcu_mon1__pm_mon__shift 0x00\n+#define ma_dcu_mon1__pm_mon__reset 0x00\n+//-----------------------------------------------------dcu_mon1.freqmode_mon---\n+// frequence mode monitor channel 1\n+#define ma_dcu_mon1__freqmode_mon__a 100\n+#define ma_dcu_mon1__freqmode_mon__len 3\n+#define ma_dcu_mon1__freqmode_mon__mask 0x70\n+#define ma_dcu_mon1__freqmode_mon__shift 0x04\n+#define ma_dcu_mon1__freqmode_mon__reset 0x00\n+//-------------------------------------------------------dcu_mon1.pps_passed---\n+// dcu1 pps completion indicator\n+#define ma_dcu_mon1__pps_passed__a 100\n+#define ma_dcu_mon1__pps_passed__len 1\n+#define ma_dcu_mon1__pps_passed__mask 0x80\n+#define ma_dcu_mon1__pps_passed__shift 0x07\n+#define ma_dcu_mon1__pps_passed__reset 0x00\n+//----------------------------------------------------------dcu_mon1.ocp_mon---\n+// ocp monitor channel 1\n+#define ma_dcu_mon1__ocp_mon__a 101\n+#define ma_dcu_mon1__ocp_mon__len 1\n+#define ma_dcu_mon1__ocp_mon__mask 0x01\n+#define ma_dcu_mon1__ocp_mon__shift 0x00\n+#define ma_dcu_mon1__ocp_mon__reset 0x00\n+//--------------------------------------------------------dcu_mon1.vcfly1_ok---\n+// cfly1 protcetion monitor channel 1\n+#define ma_dcu_mon1__vcfly1_ok__a 101\n+#define ma_dcu_mon1__vcfly1_ok__len 1\n+#define ma_dcu_mon1__vcfly1_ok__mask 0x02\n+#define ma_dcu_mon1__vcfly1_ok__shift 0x01\n+#define ma_dcu_mon1__vcfly1_ok__reset 0x00\n+//--------------------------------------------------------dcu_mon1.vcfly2_ok---\n+// cfly2 protection monitor channel 1\n+#define ma_dcu_mon1__vcfly2_ok__a 101\n+#define ma_dcu_mon1__vcfly2_ok__len 1\n+#define ma_dcu_mon1__vcfly2_ok__mask 0x04\n+#define ma_dcu_mon1__vcfly2_ok__shift 0x02\n+#define ma_dcu_mon1__vcfly2_ok__reset 0x00\n+//----------------------------------------------------------dcu_mon1.pvdd_ok---\n+// dcu1 pvdd monitor\n+#define ma_dcu_mon1__pvdd_ok__a 101\n+#define ma_dcu_mon1__pvdd_ok__len 1\n+#define ma_dcu_mon1__pvdd_ok__mask 0x08\n+#define ma_dcu_mon1__pvdd_ok__shift 0x03\n+#define ma_dcu_mon1__pvdd_ok__reset 0x00\n+//-----------------------------------------------------------dcu_mon1.vdd_ok---\n+// dcu1 vdd monitor\n+#define ma_dcu_mon1__vdd_ok__a 101\n+#define ma_dcu_mon1__vdd_ok__len 1\n+#define ma_dcu_mon1__vdd_ok__mask 0x10\n+#define ma_dcu_mon1__vdd_ok__shift 0x04\n+#define ma_dcu_mon1__vdd_ok__reset 0x00\n+//-------------------------------------------------------------dcu_mon1.mute---\n+// dcu1 mute monitor\n+#define ma_dcu_mon1__mute__a 101\n+#define ma_dcu_mon1__mute__len 1\n+#define ma_dcu_mon1__mute__mask 0x20\n+#define ma_dcu_mon1__mute__shift 0x05\n+#define ma_dcu_mon1__mute__reset 0x00\n+//------------------------------------------------------------dcu_mon1.m_mon---\n+// m sense monitor channel 1\n+#define ma_dcu_mon1__m_mon__a 102\n+#define ma_dcu_mon1__m_mon__len 8\n+#define ma_dcu_mon1__m_mon__mask 0xff\n+#define ma_dcu_mon1__m_mon__shift 0x00\n+#define ma_dcu_mon1__m_mon__reset 0x00\n+//--------------------------------------------------------dcu_mon0.sw_enable---\n+// dcu0 switch enable monitor\n+#define ma_dcu_mon0__sw_enable__a 104\n+#define ma_dcu_mon0__sw_enable__len 1\n+#define ma_dcu_mon0__sw_enable__mask 0x40\n+#define ma_dcu_mon0__sw_enable__shift 0x06\n+#define ma_dcu_mon0__sw_enable__reset 0x00\n+//--------------------------------------------------------dcu_mon1.sw_enable---\n+// dcu1 switch enable monitor\n+#define ma_dcu_mon1__sw_enable__a 104\n+#define ma_dcu_mon1__sw_enable__len 1\n+#define ma_dcu_mon1__sw_enable__mask 0x80\n+#define ma_dcu_mon1__sw_enable__shift 0x07\n+#define ma_dcu_mon1__sw_enable__reset 0x00\n+//------------------------------------------------------------hvboot0_ok_mon---\n+// hvboot0_ok for test/debug\n+#define ma_hvboot0_ok_mon__a 105\n+#define ma_hvboot0_ok_mon__len 1\n+#define ma_hvboot0_ok_mon__mask 0x40\n+#define ma_hvboot0_ok_mon__shift 0x06\n+#define ma_hvboot0_ok_mon__reset 0x00\n+//------------------------------------------------------------hvboot1_ok_mon---\n+// hvboot1_ok for test/debug\n+#define ma_hvboot1_ok_mon__a 105\n+#define ma_hvboot1_ok_mon__len 1\n+#define ma_hvboot1_ok_mon__mask 0x80\n+#define ma_hvboot1_ok_mon__shift 0x07\n+#define ma_hvboot1_ok_mon__reset 0x00\n+//-----------------------------------------------------------------error_acc---\n+// accumulated errors,  at and after triggering\n+#define ma_error_acc__a 109\n+#define ma_error_acc__len 8\n+#define ma_error_acc__mask 0xff\n+#define ma_error_acc__shift 0x00\n+#define ma_error_acc__reset 0x00\n+//-------------------------------------------------------------i2s_data_rate---\n+// detected i2s data rate: 00/01/10 = x1/x2/x4\n+#define ma_i2s_data_rate__a 116\n+#define ma_i2s_data_rate__len 2\n+#define ma_i2s_data_rate__mask 0x03\n+#define ma_i2s_data_rate__shift 0x00\n+#define ma_i2s_data_rate__reset 0x00\n+//---------------------------------------------------------audio_in_mode_mon---\n+// audio input mode monitor\n+#define ma_audio_in_mode_mon__a 116\n+#define ma_audio_in_mode_mon__len 3\n+#define ma_audio_in_mode_mon__mask 0x1c\n+#define ma_audio_in_mode_mon__shift 0x02\n+#define ma_audio_in_mode_mon__reset 0x00\n+//------------------------------------------------------------------msel_mon---\n+// msel[2:0] monitor register\n+#define ma_msel_mon__a 117\n+#define ma_msel_mon__len 3\n+#define ma_msel_mon__mask 0x07\n+#define ma_msel_mon__shift 0x00\n+#define ma_msel_mon__reset 0x00\n+//---------------------------------------------------------------------error---\n+// current error flag monitor reg - for app. ctrl.\n+#define ma_error__a 124\n+#define ma_error__len 8\n+#define ma_error__mask 0xff\n+#define ma_error__shift 0x00\n+#define ma_error__reset 0x00\n+//----------------------------------------------------audio_proc_limiter_mon---\n+// b7-b4: channel 3-0 limiter active\n+#define ma_audio_proc_limiter_mon__a 126\n+#define ma_audio_proc_limiter_mon__len 4\n+#define ma_audio_proc_limiter_mon__mask 0xf0\n+#define ma_audio_proc_limiter_mon__shift 0x04\n+#define ma_audio_proc_limiter_mon__reset 0x00\n+//-------------------------------------------------------audio_proc_clip_mon---\n+// b3-b0: channel 3-0 clipping monitor\n+#define ma_audio_proc_clip_mon__a 126\n+#define ma_audio_proc_clip_mon__len 4\n+#define ma_audio_proc_clip_mon__mask 0x0f\n+#define ma_audio_proc_clip_mon__shift 0x00\n+#define ma_audio_proc_clip_mon__reset 0x00\n+#endif\n+\n+#define SOC_ENUM_ERR(xname, xenum)\\\n+{\t.iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\\\n+\t.access = SNDRV_CTL_ELEM_ACCESS_READ,\\\n+\t.info = snd_soc_info_enum_double,\\\n+\t.get = snd_soc_get_enum_double, .put = snd_soc_put_enum_double,\\\n+\t.private_value = (unsigned long)&(xenum) }\n+\n+static struct i2c_client *i2c;\n+\n+struct ma120x0p_priv {\n+\tstruct regmap *regmap;\n+\tint mclk_div;\n+\tstruct snd_soc_component *component;\n+\tstruct gpio_desc *enable_gpio;\n+\tstruct gpio_desc *mute_gpio;\n+\tstruct gpio_desc *booster_gpio;\n+\tstruct gpio_desc *error_gpio;\n+};\n+\n+static struct ma120x0p_priv *priv_data;\n+\n+//Used to share the IRQ number within this file\n+static unsigned int irqNumber;\n+\n+// Function prototype for the custom IRQ handler function\n+static irqreturn_t ma120x0p_irq_handler(int irq, void *data);\n+\n+//Alsa Controls\n+static const char * const limenable_text[] = {\"Bypassed\", \"Enabled\"};\n+static const char * const limatack_text[] = {\"Slow\", \"Normal\", \"Fast\"};\n+static const char * const limrelease_text[] = {\"Slow\", \"Normal\", \"Fast\"};\n+\n+static const char * const err_flycap_text[] = {\"Ok\", \"Error\"};\n+static const char * const err_overcurr_text[] = {\"Ok\", \"Error\"};\n+static const char * const err_pllerr_text[] = {\"Ok\", \"Error\"};\n+static const char * const err_pvddunder_text[] = {\"Ok\", \"Error\"};\n+static const char * const err_overtempw_text[] = {\"Ok\", \"Error\"};\n+static const char * const err_overtempe_text[] = {\"Ok\", \"Error\"};\n+static const char * const err_pinlowimp_text[] = {\"Ok\", \"Error\"};\n+static const char * const err_dcprot_text[] = {\"Ok\", \"Error\"};\n+\n+static const char * const pwr_mode_prof_text[] = {\"PMF0\", \"PMF1\", \"PMF2\",\n+\"PMF3\", \"PMF4\"};\n+\n+static const struct soc_enum lim_enable_ctrl =\n+\tSOC_ENUM_SINGLE(ma_audio_proc_limiterenable__a,\n+\t\tma_audio_proc_limiterenable__shift,\n+\t\tma_audio_proc_limiterenable__len + 1,\n+\t\tlimenable_text);\n+static const struct soc_enum limatack_ctrl =\n+\tSOC_ENUM_SINGLE(ma_audio_proc_attack__a,\n+\t\tma_audio_proc_attack__shift,\n+\t\tma_audio_proc_attack__len + 1,\n+\t\tlimatack_text);\n+static const struct soc_enum limrelease_ctrl =\n+\tSOC_ENUM_SINGLE(ma_audio_proc_release__a,\n+\t\tma_audio_proc_release__shift,\n+\t\tma_audio_proc_release__len + 1,\n+\t\tlimrelease_text);\n+static const struct soc_enum err_flycap_ctrl =\n+\tSOC_ENUM_SINGLE(ma_error__a, 0, 3, err_flycap_text);\n+static const struct soc_enum err_overcurr_ctrl =\n+\tSOC_ENUM_SINGLE(ma_error__a, 1, 3, err_overcurr_text);\n+static const struct soc_enum err_pllerr_ctrl =\n+\tSOC_ENUM_SINGLE(ma_error__a, 2, 3, err_pllerr_text);\n+static const struct soc_enum err_pvddunder_ctrl =\n+\tSOC_ENUM_SINGLE(ma_error__a, 3, 3, err_pvddunder_text);\n+static const struct soc_enum err_overtempw_ctrl =\n+\tSOC_ENUM_SINGLE(ma_error__a, 4, 3, err_overtempw_text);\n+static const struct soc_enum err_overtempe_ctrl =\n+\tSOC_ENUM_SINGLE(ma_error__a, 5, 3, err_overtempe_text);\n+static const struct soc_enum err_pinlowimp_ctrl =\n+\tSOC_ENUM_SINGLE(ma_error__a, 6, 3, err_pinlowimp_text);\n+static const struct soc_enum err_dcprot_ctrl =\n+\tSOC_ENUM_SINGLE(ma_error__a, 7, 3, err_dcprot_text);\n+static const struct soc_enum pwr_mode_prof_ctrl =\n+\tSOC_ENUM_SINGLE(ma_pmprofile__a, ma_pmprofile__shift, 5,\n+\t\tpwr_mode_prof_text);\n+\n+static const char * const pwr_mode_texts[] = {\n+\t\t\"Dynamic power mode\",\n+\t\t\"Power mode 1\",\n+\t\t\"Power mode 2\",\n+\t\t\"Power mode 3\",\n+\t};\n+\n+static const int pwr_mode_values[] = {\n+\t\t0x10,\n+\t\t0x50,\n+\t\t0x60,\n+\t\t0x70,\n+\t};\n+\n+static const SOC_VALUE_ENUM_SINGLE_DECL(pwr_mode_ctrl,\n+\tma_pm_man__a, 0, 0x70,\n+\tpwr_mode_texts,\n+\tpwr_mode_values);\n+\n+static const DECLARE_TLV_DB_SCALE(ma120x0p_vol_tlv, -5000, 100,  0);\n+static const DECLARE_TLV_DB_SCALE(ma120x0p_lim_tlv, -5000, 100,  0);\n+static const DECLARE_TLV_DB_SCALE(ma120x0p_lr_tlv, -5000, 100,  0);\n+\n+static const struct snd_kcontrol_new ma120x0p_snd_controls[] = {\n+\t//Master Volume\n+\tSOC_SINGLE_RANGE_TLV(\"A.Mstr Vol Volume\",\n+\t\tma_vol_db_master__a, 0, 0x18, 0x4a, 1, ma120x0p_vol_tlv),\n+\n+\t//L-R Volume ch0\n+\tSOC_SINGLE_RANGE_TLV(\"B.L Vol Volume\",\n+\t\tma_vol_db_ch0__a, 0, 0x18, 0x4a, 1, ma120x0p_lr_tlv),\n+\tSOC_SINGLE_RANGE_TLV(\"C.R Vol Volume\",\n+\t\tma_vol_db_ch1__a, 0, 0x18, 0x4a, 1, ma120x0p_lr_tlv),\n+\n+\t//L-R Limiter Threshold ch0-ch1\n+\tSOC_DOUBLE_R_RANGE_TLV(\"D.Lim thresh Volume\",\n+\t\tma_thr_db_ch0__a, ma_thr_db_ch1__a, 0, 0x0e, 0x4a, 1,\n+\t\tma120x0p_lim_tlv),\n+\n+\t//Enum Switches/Selectors\n+\t//SOC_ENUM(\"E.AudioProc Mute\", audioproc_mute_ctrl),\n+\tSOC_ENUM(\"F.Limiter Enable\", lim_enable_ctrl),\n+\tSOC_ENUM(\"G.Limiter Attck\", limatack_ctrl),\n+\tSOC_ENUM(\"H.Limiter Rls\", limrelease_ctrl),\n+\n+\t//Enum Error Monitor (read-only)\n+\tSOC_ENUM_ERR(\"I.Err flycap\", err_flycap_ctrl),\n+\tSOC_ENUM_ERR(\"J.Err overcurr\", err_overcurr_ctrl),\n+\tSOC_ENUM_ERR(\"K.Err pllerr\", err_pllerr_ctrl),\n+\tSOC_ENUM_ERR(\"L.Err pvddunder\", err_pvddunder_ctrl),\n+\tSOC_ENUM_ERR(\"M.Err overtempw\", err_overtempw_ctrl),\n+\tSOC_ENUM_ERR(\"N.Err overtempe\", err_overtempe_ctrl),\n+\tSOC_ENUM_ERR(\"O.Err pinlowimp\", err_pinlowimp_ctrl),\n+\tSOC_ENUM_ERR(\"P.Err dcprot\", err_dcprot_ctrl),\n+\n+\t//Power modes profiles\n+\tSOC_ENUM(\"Q.PM Prof\", pwr_mode_prof_ctrl),\n+\n+\t// Power mode selection (Dynamic,1,2,3)\n+\tSOC_ENUM(\"R.Power Mode\", pwr_mode_ctrl),\n+};\n+\n+//Machine Driver\n+static int ma120x0p_hw_params(struct snd_pcm_substream *substream,\n+\tstruct snd_pcm_hw_params *params, struct snd_soc_dai *dai)\n+{\n+\tu16 blen = 0x00;\n+\n+\tstruct snd_soc_component *component = dai->component;\n+\n+\tpriv_data->component = component;\n+\n+\tswitch (params_format(params)) {\n+\tcase SNDRV_PCM_FORMAT_S16_LE:\n+\t\tblen = 0x10;\n+\t\tbreak;\n+\tcase SNDRV_PCM_FORMAT_S24_LE:\n+\t\tblen = 0x00;\n+\t\tbreak;\n+\tcase SNDRV_PCM_FORMAT_S32_LE:\n+\t\tblen = 0x00;\n+\t\tbreak;\n+\tdefault:\n+\t\tdev_err(dai->dev, \"Unsupported word length: %u\\n\",\n+\t\tparams_format(params));\n+\t\treturn -EINVAL;\n+\t}\n+\n+\t// set word length\n+\tsnd_soc_component_update_bits(component, ma_i2s_framesize__a,\n+\t\tma_i2s_framesize__mask, blen);\n+\n+\treturn 0;\n+}\n+\n+static int ma120x0p_mute_stream(struct snd_soc_dai *dai, int mute, int stream)\n+{\n+\tint val = 0;\n+\n+\tstruct ma120x0p_priv *ma120x0p;\n+\n+\tstruct snd_soc_component *component = dai->component;\n+\n+\tma120x0p = snd_soc_component_get_drvdata(component);\n+\n+\tif (mute)\n+\t\tval = 0;\n+\telse\n+\t\tval = 1;\n+\n+\tgpiod_set_value_cansleep(priv_data->mute_gpio, val);\n+\n+\treturn 0;\n+}\n+\n+static const struct snd_soc_dai_ops ma120x0p_dai_ops = {\n+\t.hw_params\t\t=\tma120x0p_hw_params,\n+\t.mute_stream\t=\tma120x0p_mute_stream,\n+};\n+\n+static struct snd_soc_dai_driver ma120x0p_dai = {\n+\t.name\t\t= \"ma120x0p-amp\",\n+\t.playback\t=\t{\n+\t\t.stream_name\t= \"Playback\",\n+\t\t.channels_min\t= 2,\n+\t\t.channels_max\t= 2,\n+\t\t.rates = SNDRV_PCM_RATE_CONTINUOUS,\n+\t\t.rate_min = 44100,\n+\t\t.rate_max = 96000,\n+\t\t.formats = SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE\n+\t},\n+\t.ops        = &ma120x0p_dai_ops,\n+};\n+\n+//Codec Driver\n+static int ma120x0p_clear_err(struct snd_soc_component *component)\n+{\n+\tint ret = 0;\n+\n+\tstruct ma120x0p_priv *ma120x0p;\n+\n+\tma120x0p = snd_soc_component_get_drvdata(component);\n+\n+\tret = snd_soc_component_update_bits(component,\n+\t\tma_eh_clear__a, ma_eh_clear__mask, 0x00);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\tret = snd_soc_component_update_bits(component,\n+\t\tma_eh_clear__a, ma_eh_clear__mask, 0x04);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\tret = snd_soc_component_update_bits(component,\n+\t\tma_eh_clear__a, ma_eh_clear__mask, 0x00);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\treturn 0;\n+}\n+\n+static void ma120x0p_remove(struct snd_soc_component *component)\n+{\n+\tstruct ma120x0p_priv *ma120x0p;\n+\n+\tma120x0p = snd_soc_component_get_drvdata(component);\n+}\n+\n+static int ma120x0p_probe(struct snd_soc_component *component)\n+{\n+\tstruct ma120x0p_priv *ma120x0p;\n+\n+\tint ret = 0;\n+\n+\ti2c = container_of(component->dev, struct i2c_client, dev);\n+\n+\tma120x0p = snd_soc_component_get_drvdata(component);\n+\n+\t//Reset error\n+\tma120x0p_clear_err(component);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\t// set serial audio format I2S and enable audio processor\n+\tret = snd_soc_component_write(component, ma_i2s_format__a, 0x08);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\t// Enable audio limiter\n+\tret = snd_soc_component_update_bits(component,\n+\t\tma_audio_proc_limiterenable__a,\n+\t\tma_audio_proc_limiterenable__mask, 0x40);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\t// Set lim attack to fast\n+\tret = snd_soc_component_update_bits(component,\n+\t\tma_audio_proc_attack__a, ma_audio_proc_attack__mask, 0x80);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\t// Set lim attack to low\n+\tret = snd_soc_component_update_bits(component,\n+\t\tma_audio_proc_release__a, ma_audio_proc_release__mask, 0x00);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\t// set volume to 0dB\n+\tret = snd_soc_component_write(component, ma_vol_db_master__a, 0x18);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\t// set ch0 lim thresh to -15dB\n+\tret = snd_soc_component_write(component, ma_thr_db_ch0__a, 0x27);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\t// set ch1 lim thresh to -15dB\n+\tret = snd_soc_component_write(component, ma_thr_db_ch1__a, 0x27);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\t//Check for errors\n+\tret = snd_soc_component_test_bits(component, ma_error_acc__a, 0x00, 0);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\tret = snd_soc_component_test_bits(component, ma_error_acc__a, 0x01, 0);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\tret = snd_soc_component_test_bits(component, ma_error_acc__a, 0x02, 0);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\tret = snd_soc_component_test_bits(component, ma_error_acc__a, 0x08, 0);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\tret = snd_soc_component_test_bits(component, ma_error_acc__a, 0x10, 0);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\tret = snd_soc_component_test_bits(component, ma_error_acc__a, 0x20, 0);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\tret = snd_soc_component_test_bits(component, ma_error_acc__a, 0x40, 0);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\tret = snd_soc_component_test_bits(component, ma_error_acc__a, 0x80, 0);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\treturn 0;\n+}\n+\n+static int ma120x0p_set_bias_level(struct snd_soc_component *component,\n+\tenum snd_soc_bias_level level)\n+{\n+\tint ret = 0;\n+\n+\tstruct ma120x0p_priv *ma120x0p;\n+\n+\tma120x0p = snd_soc_component_get_drvdata(component);\n+\n+\tswitch (level) {\n+\tcase SND_SOC_BIAS_ON:\n+\t\tbreak;\n+\n+\tcase SND_SOC_BIAS_PREPARE:\n+\t\tbreak;\n+\n+\tcase SND_SOC_BIAS_STANDBY:\n+\t\tret = gpiod_get_value_cansleep(priv_data->enable_gpio);\n+\t\tif (ret != 0) {\n+\t\t\tdev_err(component->dev, \"Device ma120x0p disabled in STANDBY BIAS: %d\\n\",\n+\t\t\tret);\n+\t\t\treturn ret;\n+\t\t}\n+\t\tbreak;\n+\n+\tcase SND_SOC_BIAS_OFF:\n+\t\tbreak;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static const struct snd_soc_dapm_widget ma120x0p_dapm_widgets[] = {\n+\tSND_SOC_DAPM_OUTPUT(\"OUT_A\"),\n+\tSND_SOC_DAPM_OUTPUT(\"OUT_B\"),\n+};\n+\n+static const struct snd_soc_dapm_route ma120x0p_dapm_routes[] = {\n+\t{ \"OUT_B\",  NULL, \"Playback\" },\n+\t{ \"OUT_A\",  NULL, \"Playback\" },\n+};\n+\n+static const struct snd_soc_component_driver ma120x0p_component_driver = {\n+\t.probe = ma120x0p_probe,\n+\t.remove = ma120x0p_remove,\n+\t.set_bias_level = ma120x0p_set_bias_level,\n+\t.dapm_widgets\t\t= ma120x0p_dapm_widgets,\n+\t.num_dapm_widgets\t= ARRAY_SIZE(ma120x0p_dapm_widgets),\n+\t.dapm_routes\t\t= ma120x0p_dapm_routes,\n+\t.num_dapm_routes\t= ARRAY_SIZE(ma120x0p_dapm_routes),\n+\t.controls = ma120x0p_snd_controls,\n+\t.num_controls = ARRAY_SIZE(ma120x0p_snd_controls),\n+\t.use_pmdown_time\t= 1,\n+\t.endianness\t\t= 1,\n+\t.non_legacy_dai_naming\t= 1,\n+};\n+\n+//I2C Driver\n+static const struct reg_default ma120x0p_reg_defaults[] = {\n+\t{\t0x01,\t0x3c\t},\n+};\n+\n+static bool ma120x0p_reg_volatile(struct device *dev, unsigned int reg)\n+{\n+\tswitch (reg) {\n+\tcase ma_error__a:\n+\t\t\treturn true;\n+\tdefault:\n+\t\t\treturn false;\n+\t}\n+}\n+\n+static const struct of_device_id ma120x0p_of_match[] = {\n+\t{ .compatible = \"ma,ma120x0p\", },\n+\t{ }\n+};\n+\n+MODULE_DEVICE_TABLE(of, ma120x0p_of_match);\n+\n+static struct regmap_config ma120x0p_regmap_config = {\n+\t.reg_bits = 8,\n+\t.val_bits = 8,\n+\n+\t.max_register = 255,\n+\t.volatile_reg = ma120x0p_reg_volatile,\n+\n+\t.cache_type = REGCACHE_RBTREE,\n+\t.reg_defaults = ma120x0p_reg_defaults,\n+\t.num_reg_defaults = ARRAY_SIZE(ma120x0p_reg_defaults),\n+};\n+\n+static int ma120x0p_i2c_probe(struct i2c_client *i2c,\n+\tconst struct i2c_device_id *id)\n+{\n+\tint ret;\n+\n+\tpriv_data = devm_kzalloc(&i2c->dev, sizeof(*priv_data), GFP_KERNEL);\n+\tif (!priv_data)\n+\t\treturn -ENOMEM;\n+\ti2c_set_clientdata(i2c, priv_data);\n+\n+\tpriv_data->regmap = devm_regmap_init_i2c(i2c, &ma120x0p_regmap_config);\n+\tif (IS_ERR(priv_data->regmap)) {\n+\t\tret = PTR_ERR(priv_data->regmap);\n+\t\treturn ret;\n+\t}\n+\n+\t//Startup sequence\n+\n+\t//Make sure the device is muted\n+\tpriv_data->mute_gpio = devm_gpiod_get_optional(&i2c->dev, \"mute_gp\",\n+\t\tGPIOD_OUT_LOW);\n+\tif (IS_ERR(priv_data->mute_gpio)) {\n+\t\tret = PTR_ERR(priv_data->mute_gpio);\n+\t\tdev_err(&i2c->dev, \"Failed to get mute gpio line: %d\\n\", ret);\n+\t\treturn ret;\n+\t}\n+\tmsleep(50);\n+\n+// MA120xx0P devices are usually powered by an integrated boost converter.\n+// An option GPIO control line is provided to enable the booster properly and\n+// in sync with the enable and mute GPIO lines.\n+\tpriv_data->booster_gpio = devm_gpiod_get_optional(&i2c->dev,\n+\t\t\"booster_gp\", GPIOD_OUT_LOW);\n+\tif (IS_ERR(priv_data->booster_gpio)) {\n+\t\tret = PTR_ERR(priv_data->booster_gpio);\n+\t\tdev_err(&i2c->dev,\n+\t\t\"Failed to get booster enable gpio line: %d\\n\", ret);\n+\t\treturn ret;\n+\t}\n+\tmsleep(50);\n+\n+\t//Enable booster and wait 200ms until stable PVDD\n+\tgpiod_set_value_cansleep(priv_data->booster_gpio, 1);\n+\tmsleep(200);\n+\n+\t//Enable ma120x0pp\n+\tpriv_data->enable_gpio = devm_gpiod_get_optional(&i2c->dev,\n+\t\t\"enable_gp\", GPIOD_OUT_LOW);\n+\tif (IS_ERR(priv_data->enable_gpio)) {\n+\t\tret = PTR_ERR(priv_data->enable_gpio);\n+\t\tdev_err(&i2c->dev,\n+\t\t\"Failed to get ma120x0p enable gpio line: %d\\n\", ret);\n+\t\treturn ret;\n+\t}\n+\tmsleep(50);\n+\n+\t//Optional use of ma120x0pp error line as an interrupt trigger to\n+\t//platform GPIO.\n+\t//Get error input gpio ma120x0p\n+\tpriv_data->error_gpio = devm_gpiod_get_optional(&i2c->dev,\n+\t\t \"error_gp\", GPIOD_IN);\n+\tif (IS_ERR(priv_data->error_gpio)) {\n+\t\tret = PTR_ERR(priv_data->error_gpio);\n+\t\tdev_err(&i2c->dev,\n+\t\t\t\"Failed to get ma120x0p error gpio line: %d\\n\", ret);\n+\t\treturn ret;\n+\t}\n+\n+\tif (priv_data->error_gpio != NULL) {\n+\t\tirqNumber = gpiod_to_irq(priv_data->error_gpio);\n+\n+\t\tret = devm_request_threaded_irq(&i2c->dev,\n+\t\t\t irqNumber, ma120x0p_irq_handler,\n+\t\t\t NULL, IRQF_TRIGGER_FALLING,\n+\t\t\t \"ma120x0p\", priv_data);\n+\t\tif (ret != 0)\n+\t\t\tdev_warn(&i2c->dev, \"Failed to request IRQ: %d\\n\",\n+\t\t\t\tret);\n+\t}\n+\n+\tret = devm_snd_soc_register_component(&i2c->dev,\n+\t\t&ma120x0p_component_driver, &ma120x0p_dai, 1);\n+\n+\treturn ret;\n+}\n+\n+static irqreturn_t ma120x0p_irq_handler(int irq, void *data)\n+{\n+\tgpiod_set_value_cansleep(priv_data->mute_gpio, 0);\n+\tgpiod_set_value_cansleep(priv_data->enable_gpio, 1);\n+\treturn IRQ_HANDLED;\n+}\n+\n+static int ma120x0p_i2c_remove(struct i2c_client *i2c)\n+{\n+\tsnd_soc_unregister_component(&i2c->dev);\n+\ti2c_set_clientdata(i2c, NULL);\n+\n+\tgpiod_set_value_cansleep(priv_data->mute_gpio, 0);\n+\tmsleep(30);\n+\tgpiod_set_value_cansleep(priv_data->enable_gpio, 1);\n+\tmsleep(200);\n+\tgpiod_set_value_cansleep(priv_data->booster_gpio, 0);\n+\tmsleep(200);\n+\n+\tkfree(priv_data);\n+\n+\treturn 0;\n+}\n+\n+static void ma120x0p_i2c_shutdown(struct i2c_client *i2c)\n+{\n+\tsnd_soc_unregister_component(&i2c->dev);\n+\ti2c_set_clientdata(i2c, NULL);\n+\n+\tgpiod_set_value_cansleep(priv_data->mute_gpio, 0);\n+\tmsleep(30);\n+\tgpiod_set_value_cansleep(priv_data->enable_gpio, 1);\n+\tmsleep(200);\n+\tgpiod_set_value_cansleep(priv_data->booster_gpio, 0);\n+\tmsleep(200);\n+\n+\tkfree(priv_data);\n+}\n+\n+static const struct i2c_device_id ma120x0p_i2c_id[] = {\n+\t{ \"ma120x0p\", 0 },\n+\t{ }\n+};\n+\n+MODULE_DEVICE_TABLE(i2c, ma120x0p_i2c_id);\n+\n+static struct i2c_driver ma120x0p_i2c_driver = {\n+\t.driver = {\n+\t\t.name = \"ma120x0p\",\n+\t\t.owner = THIS_MODULE,\n+\t\t.of_match_table = ma120x0p_of_match,\n+\t},\n+\t.probe = ma120x0p_i2c_probe,\n+\t.remove = ma120x0p_i2c_remove,\n+\t.shutdown = ma120x0p_i2c_shutdown,\n+\t.id_table = ma120x0p_i2c_id\n+};\n+\n+static int __init ma120x0p_modinit(void)\n+{\n+\tint ret = 0;\n+\n+\tret = i2c_add_driver(&ma120x0p_i2c_driver);\n+\tif (ret != 0) {\n+\t\tpr_err(\"Failed to register MA120X0P I2C driver: %d\\n\", ret);\n+\t\treturn ret;\n+\t}\n+\treturn ret;\n+}\n+module_init(ma120x0p_modinit);\n+\n+static void __exit ma120x0p_exit(void)\n+{\n+\ti2c_del_driver(&ma120x0p_i2c_driver);\n+}\n+module_exit(ma120x0p_exit);\n+\n+MODULE_AUTHOR(\"Ariel Muszkat ariel.muszkat@gmail.com>\");\n+MODULE_DESCRIPTION(\"ASoC driver for ma120x0p\");\n+MODULE_LICENSE(\"GPL v2\");\n--- /dev/null\n+++ b/sound/soc/codecs/pcm1794a.c\n@@ -0,0 +1,69 @@\n+/*\n+ * Driver for the PCM1794A codec\n+ *\n+ * Author:\tFlorian Meier <florian.meier@koalo.de>\n+ *\t\tCopyright 2013\n+ *\n+ * This program is free software; you can redistribute it and/or\n+ * modify it under the terms of the GNU General Public License\n+ * version 2 as published by the Free Software Foundation.\n+ *\n+ * This program is distributed in the hope that it will be useful, but\n+ * WITHOUT ANY WARRANTY; without even the implied warranty of\n+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\n+ * General Public License for more details.\n+ */\n+\n+\n+#include <linux/init.h>\n+#include <linux/module.h>\n+#include <linux/platform_device.h>\n+\n+#include <sound/soc.h>\n+\n+static struct snd_soc_dai_driver pcm1794a_dai = {\n+\t.name = \"pcm1794a-hifi\",\n+\t.playback = {\n+\t\t.channels_min = 2,\n+\t\t.channels_max = 2,\n+\t\t.rates = SNDRV_PCM_RATE_8000_192000,\n+\t\t.formats = SNDRV_PCM_FMTBIT_S16_LE |\n+\t\t\t   SNDRV_PCM_FMTBIT_S24_LE\n+\t},\n+};\n+\n+static struct snd_soc_component_driver soc_component_dev_pcm1794a;\n+\n+static int pcm1794a_probe(struct platform_device *pdev)\n+{\n+\treturn snd_soc_register_component(&pdev->dev, &soc_component_dev_pcm1794a,\n+\t\t\t&pcm1794a_dai, 1);\n+}\n+\n+static int pcm1794a_remove(struct platform_device *pdev)\n+{\n+\tsnd_soc_unregister_component(&pdev->dev);\n+\treturn 0;\n+}\n+\n+static const struct of_device_id pcm1794a_of_match[] = {\n+\t{ .compatible = \"ti,pcm1794a\", },\n+\t{ }\n+};\n+MODULE_DEVICE_TABLE(of, pcm1794a_of_match);\n+\n+static struct platform_driver pcm1794a_component_driver = {\n+\t.probe \t\t= pcm1794a_probe,\n+\t.remove \t= pcm1794a_remove,\n+\t.driver\t\t= {\n+\t\t.name\t= \"pcm1794a-codec\",\n+\t\t.owner\t= THIS_MODULE,\n+\t\t.of_match_table = of_match_ptr(pcm1794a_of_match),\n+\t},\n+};\n+\n+module_platform_driver(pcm1794a_component_driver);\n+\n+MODULE_DESCRIPTION(\"ASoC PCM1794A codec driver\");\n+MODULE_AUTHOR(\"Florian Meier <florian.meier@koalo.de>\");\n+MODULE_LICENSE(\"GPL v2\");\n--- a/sound/soc/codecs/pcm512x.c\n+++ b/sound/soc/codecs/pcm512x.c\n@@ -534,7 +534,7 @@ static unsigned long pcm512x_ncp_target(\n \n static const u32 pcm512x_dai_rates[] = {\n \t8000, 11025, 16000, 22050, 32000, 44100, 48000, 64000,\n-\t88200, 96000, 176400, 192000, 384000,\n+\t88200, 96000, 176400, 192000, 352800, 384000,\n };\n \n static const struct snd_pcm_hw_constraint_list constraints_slave = {\n--- /dev/null\n+++ b/sound/soc/codecs/tas5713.c\n@@ -0,0 +1,363 @@\n+/*\n+ * ASoC Driver for TAS5713\n+ *\n+ * Author:\tSebastian Eickhoff <basti.eickhoff@googlemail.com>\n+ *\t\tCopyright 2014\n+ *\n+ * This program is free software; you can redistribute it and/or\n+ * modify it under the terms of the GNU General Public License\n+ * version 2 as published by the Free Software Foundation.\n+ *\n+ * This program is distributed in the hope that it will be useful, but\n+ * WITHOUT ANY WARRANTY; without even the implied warranty of\n+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\n+ * General Public License for more details.\n+ */\n+\n+#include <linux/module.h>\n+#include <linux/moduleparam.h>\n+#include <linux/init.h>\n+#include <linux/delay.h>\n+#include <linux/pm.h>\n+#include <linux/i2c.h>\n+#include <linux/of_device.h>\n+#include <linux/spi/spi.h>\n+#include <linux/regmap.h>\n+#include <linux/regulator/consumer.h>\n+#include <linux/slab.h>\n+#include <sound/core.h>\n+#include <sound/pcm.h>\n+#include <sound/pcm_params.h>\n+#include <sound/soc.h>\n+#include <sound/initval.h>\n+#include <sound/tlv.h>\n+\n+#include <linux/kernel.h>\n+#include <linux/string.h>\n+#include <linux/fs.h>\n+#include <asm/uaccess.h>\n+\n+#include \"tas5713.h\"\n+\n+\n+static struct i2c_client *i2c;\n+\n+struct tas5713_priv {\n+\tstruct regmap *regmap;\n+\tint mclk_div;\n+\tstruct snd_soc_component *component;\n+};\n+\n+static struct tas5713_priv *priv_data;\n+\n+\n+\n+\n+/*\n+ *    _   _    ___   _      ___         _           _\n+ *   /_\\ | |  / __| /_\\    / __|___ _ _| |_ _ _ ___| |___\n+ *  / _ \\| |__\\__ \\/ _ \\  | (__/ _ \\ ' \\  _| '_/ _ \\ (_-<\n+ * /_/ \\_\\____|___/_/ \\_\\  \\___\\___/_||_\\__|_| \\___/_/__/\n+ *\n+ */\n+\n+static const DECLARE_TLV_DB_SCALE(tas5713_vol_tlv, -10000, 50, 1);\n+\n+\n+static const struct snd_kcontrol_new tas5713_snd_controls[] = {\n+\tSOC_SINGLE_TLV  (\"Master\"    , TAS5713_VOL_MASTER, 0, 248, 1, tas5713_vol_tlv),\n+\tSOC_DOUBLE_R_TLV(\"Channels\"  , TAS5713_VOL_CH1, TAS5713_VOL_CH2, 0, 248, 1, tas5713_vol_tlv)\n+};\n+\n+\n+\n+\n+/*\n+ *  __  __         _    _            ___      _\n+ * |  \\/  |__ _ __| |_ (_)_ _  ___  |   \\ _ _(_)_ _____ _ _\n+ * | |\\/| / _` / _| ' \\| | ' \\/ -_) | |) | '_| \\ V / -_) '_|\n+ * |_|  |_\\__,_\\__|_||_|_|_||_\\___| |___/|_| |_|\\_/\\___|_|\n+ *\n+ */\n+\n+static int tas5713_hw_params(struct snd_pcm_substream *substream,\n+\t\t\t    struct snd_pcm_hw_params *params,\n+\t\t\t    struct snd_soc_dai *dai)\n+{\n+\tu16 blen = 0x00;\n+\n+\tstruct snd_soc_component *component = dai->component;\n+\tpriv_data->component = component;\n+\n+\tswitch (params_format(params)) {\n+\tcase SNDRV_PCM_FORMAT_S16_LE:\n+\t\tblen = 0x03;\n+\t\tbreak;\n+\tcase SNDRV_PCM_FORMAT_S20_3LE:\n+\t\tblen = 0x1;\n+\t\tbreak;\n+\tcase SNDRV_PCM_FORMAT_S24_LE:\n+\t\tblen = 0x04;\n+\t\tbreak;\n+\tcase SNDRV_PCM_FORMAT_S32_LE:\n+\t\tblen = 0x05;\n+\t\tbreak;\n+\tdefault:\n+\t\tdev_err(dai->dev, \"Unsupported word length: %u\\n\",\n+\t\t\tparams_format(params));\n+\t\treturn -EINVAL;\n+\t}\n+\n+\t// set word length\n+\tsnd_soc_component_update_bits(component, TAS5713_SERIAL_DATA_INTERFACE, 0x7, blen);\n+\n+\treturn 0;\n+}\n+\n+\n+static int tas5713_mute_stream(struct snd_soc_dai *dai, int mute, int stream)\n+{\n+\tunsigned int val = 0;\n+\n+\tstruct tas5713_priv *tas5713;\n+\tstruct snd_soc_component *component = dai->component;\n+\ttas5713 = snd_soc_component_get_drvdata(component);\n+\n+\tif (mute) {\n+\t\tval = TAS5713_SOFT_MUTE_ALL;\n+\t}\n+\n+\treturn regmap_write(tas5713->regmap, TAS5713_SOFT_MUTE, val);\n+}\n+\n+\n+static const struct snd_soc_dai_ops tas5713_dai_ops = {\n+\t.hw_params \t\t= tas5713_hw_params,\n+\t.mute_stream\t= tas5713_mute_stream,\n+};\n+\n+\n+static struct snd_soc_dai_driver tas5713_dai = {\n+\t.name\t\t= \"tas5713-hifi\",\n+\t.playback \t= {\n+\t\t.stream_name\t= \"Playback\",\n+\t\t.channels_min\t= 2,\n+\t\t.channels_max\t= 2,\n+\t\t.rates\t\t    = SNDRV_PCM_RATE_8000_48000,\n+\t\t.formats\t    = (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE ),\n+\t},\n+\t.ops        = &tas5713_dai_ops,\n+};\n+\n+\n+\n+\n+/*\n+ *   ___         _          ___      _\n+ *  / __|___  __| |___ __  |   \\ _ _(_)_ _____ _ _\n+ * | (__/ _ \\/ _` / -_) _| | |) | '_| \\ V / -_) '_|\n+ *  \\___\\___/\\__,_\\___\\__| |___/|_| |_|\\_/\\___|_|\n+ *\n+ */\n+\n+static void tas5713_remove(struct snd_soc_component *component)\n+{\n+\tstruct tas5713_priv *tas5713;\n+\n+\ttas5713 = snd_soc_component_get_drvdata(component);\n+}\n+\n+\n+static int tas5713_probe(struct snd_soc_component *component)\n+{\n+\tstruct tas5713_priv *tas5713;\n+\tint i, ret;\n+\n+\ti2c = container_of(component->dev, struct i2c_client, dev);\n+\n+\ttas5713 = snd_soc_component_get_drvdata(component);\n+\n+\t// Reset error\n+\tret = snd_soc_component_write(component, TAS5713_ERROR_STATUS, 0x00);\n+\tif (ret < 0) return ret;\n+\n+\t// Trim oscillator\n+\tret = snd_soc_component_write(component, TAS5713_OSC_TRIM, 0x00);\n+\tif (ret < 0) return ret;\n+\tmsleep(1000);\n+\n+\t// Reset error\n+\tret = snd_soc_component_write(component, TAS5713_ERROR_STATUS, 0x00);\n+\tif (ret < 0) return ret;\n+\n+\t// I2S 24bit\n+\tret = snd_soc_component_write(component, TAS5713_SERIAL_DATA_INTERFACE, 0x05);\n+\tif (ret < 0) return ret;\n+\n+\t// Unmute\n+\tret = snd_soc_component_write(component, TAS5713_SYSTEM_CTRL2, 0x00);\n+\tif (ret < 0) return ret;\n+\tret = snd_soc_component_write(component, TAS5713_SOFT_MUTE, 0x00);\n+\tif (ret < 0) return ret;\n+\n+\t// Set volume to 0db\n+\tret = snd_soc_component_write(component, TAS5713_VOL_MASTER, 0x00);\n+\tif (ret < 0) return ret;\n+\n+\t// Now start programming the default initialization sequence\n+\tfor (i = 0; i < ARRAY_SIZE(tas5713_init_sequence); ++i) {\n+\t\tret = i2c_master_send(i2c,\n+\t\t\t\t     tas5713_init_sequence[i].data,\n+\t\t\t\t     tas5713_init_sequence[i].size);\n+\t\tif (ret < 0) {\n+\t\t\tprintk(KERN_INFO \"TAS5713 CODEC PROBE: InitSeq returns: %d\\n\", ret);\n+\t\t}\n+\t}\n+\n+\t// Unmute\n+\tret = snd_soc_component_write(component, TAS5713_SYSTEM_CTRL2, 0x00);\n+\tif (ret < 0) return ret;\n+\n+\treturn 0;\n+}\n+\n+\n+static struct snd_soc_component_driver soc_codec_dev_tas5713 = {\n+\t.probe = tas5713_probe,\n+\t.remove = tas5713_remove,\n+\t.controls = tas5713_snd_controls,\n+\t.num_controls = ARRAY_SIZE(tas5713_snd_controls),\n+};\n+\n+\n+\n+\n+/*\n+ *   ___ ___ ___   ___      _\n+ *  |_ _|_  ) __| |   \\ _ _(_)_ _____ _ _\n+ *   | | / / (__  | |) | '_| \\ V / -_) '_|\n+ *  |___/___\\___| |___/|_| |_|\\_/\\___|_|\n+ *\n+ */\n+\n+static const struct reg_default tas5713_reg_defaults[] = {\n+\t{ 0x07 ,0x80 },     // R7  - VOL_MASTER    - -40dB\n+\t{ 0x08 ,  30 },     // R8  - VOL_CH1\t   -   0dB\n+\t{ 0x09 ,  30 },     // R9  - VOL_CH2       -   0dB\n+\t{ 0x0A ,0x80 },     // R10 - VOL_HEADPHONE - -40dB\n+};\n+\n+\n+static bool tas5713_reg_volatile(struct device *dev, unsigned int reg)\n+{\n+\tswitch (reg) {\n+\t\tcase TAS5713_DEVICE_ID:\n+\t\tcase TAS5713_ERROR_STATUS:\n+\t\tcase TAS5713_CLOCK_CTRL:\n+\t\t\treturn true;\n+\tdefault:\n+\t\t\treturn false;\n+\t}\n+}\n+\n+\n+static const struct of_device_id tas5713_of_match[] = {\n+\t{ .compatible = \"ti,tas5713\", },\n+\t{ }\n+};\n+MODULE_DEVICE_TABLE(of, tas5713_of_match);\n+\n+\n+static struct regmap_config tas5713_regmap_config = {\n+\t.reg_bits = 8,\n+\t.val_bits = 8,\n+\n+\t.max_register = TAS5713_MAX_REGISTER,\n+\t.volatile_reg = tas5713_reg_volatile,\n+\n+\t.cache_type = REGCACHE_RBTREE,\n+\t.reg_defaults = tas5713_reg_defaults,\n+\t.num_reg_defaults = ARRAY_SIZE(tas5713_reg_defaults),\n+};\n+\n+\n+static int tas5713_i2c_probe(struct i2c_client *i2c,\n+\t\t\t    const struct i2c_device_id *id)\n+{\n+\tint ret;\n+\n+\tpriv_data = devm_kzalloc(&i2c->dev, sizeof *priv_data, GFP_KERNEL);\n+\tif (!priv_data)\n+\t\treturn -ENOMEM;\n+\n+\tpriv_data->regmap = devm_regmap_init_i2c(i2c, &tas5713_regmap_config);\n+\tif (IS_ERR(priv_data->regmap)) {\n+\t\tret = PTR_ERR(priv_data->regmap);\n+\t\treturn ret;\n+\t}\n+\n+\ti2c_set_clientdata(i2c, priv_data);\n+\n+\tret = snd_soc_register_component(&i2c->dev,\n+\t\t\t\t     &soc_codec_dev_tas5713, &tas5713_dai, 1);\n+\n+\treturn ret;\n+}\n+\n+\n+static int tas5713_i2c_remove(struct i2c_client *i2c)\n+{\n+\tsnd_soc_unregister_component(&i2c->dev);\n+\ti2c_set_clientdata(i2c, NULL);\n+\n+\tkfree(priv_data);\n+\n+\treturn 0;\n+}\n+\n+\n+static const struct i2c_device_id tas5713_i2c_id[] = {\n+\t{ \"tas5713\", 0 },\n+\t{ }\n+};\n+\n+MODULE_DEVICE_TABLE(i2c, tas5713_i2c_id);\n+\n+\n+static struct i2c_driver tas5713_i2c_driver = {\n+\t.driver = {\n+\t\t.name = \"tas5713\",\n+\t\t.owner = THIS_MODULE,\n+\t\t.of_match_table = tas5713_of_match,\n+\t},\n+\t.probe = tas5713_i2c_probe,\n+\t.remove = tas5713_i2c_remove,\n+\t.id_table = tas5713_i2c_id\n+};\n+\n+\n+static int __init tas5713_modinit(void)\n+{\n+\tint ret = 0;\n+\n+\tret = i2c_add_driver(&tas5713_i2c_driver);\n+\tif (ret) {\n+\t\tprintk(KERN_ERR \"Failed to register tas5713 I2C driver: %d\\n\",\n+\t\t       ret);\n+\t}\n+\n+\treturn ret;\n+}\n+module_init(tas5713_modinit);\n+\n+\n+static void __exit tas5713_exit(void)\n+{\n+\ti2c_del_driver(&tas5713_i2c_driver);\n+}\n+module_exit(tas5713_exit);\n+\n+\n+MODULE_AUTHOR(\"Sebastian Eickhoff <basti.eickhoff@googlemail.com>\");\n+MODULE_DESCRIPTION(\"ASoC driver for TAS5713\");\n+MODULE_LICENSE(\"GPL v2\");\n--- /dev/null\n+++ b/sound/soc/codecs/tas5713.h\n@@ -0,0 +1,210 @@\n+/*\n+ * ASoC Driver for TAS5713\n+ *\n+ * Author:      Sebastian Eickhoff <basti.eickhoff@googlemail.com>\n+ *              Copyright 2014\n+ *\n+ * This program is free software; you can redistribute it and/or\n+ * modify it under the terms of the GNU General Public License\n+ * version 2 as published by the Free Software Foundation.\n+ *\n+ * This program is distributed in the hope that it will be useful, but\n+ * WITHOUT ANY WARRANTY; without even the implied warranty of\n+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\n+ * General Public License for more details.\n+ */\n+\n+#ifndef _TAS5713_H\n+#define _TAS5713_H\n+\n+\n+// TAS5713 I2C-bus register addresses\n+\n+#define TAS5713_CLOCK_CTRL              0x00\n+#define TAS5713_DEVICE_ID               0x01\n+#define TAS5713_ERROR_STATUS            0x02\n+#define TAS5713_SYSTEM_CTRL1            0x03\n+#define TAS5713_SERIAL_DATA_INTERFACE   0x04\n+#define TAS5713_SYSTEM_CTRL2            0x05\n+#define TAS5713_SOFT_MUTE               0x06\n+#define TAS5713_VOL_MASTER              0x07\n+#define TAS5713_VOL_CH1                 0x08\n+#define TAS5713_VOL_CH2                 0x09\n+#define TAS5713_VOL_HEADPHONE           0x0A\n+#define TAS5713_VOL_CONFIG              0x0E\n+#define TAS5713_MODULATION_LIMIT        0x10\n+#define TAS5713_IC_DLY_CH1              0x11\n+#define TAS5713_IC_DLY_CH2              0x12\n+#define TAS5713_IC_DLY_CH3              0x13\n+#define TAS5713_IC_DLY_CH4              0x14\n+\n+#define TAS5713_START_STOP_PERIOD       0x1A\n+#define TAS5713_OSC_TRIM                0x1B\n+#define TAS5713_BKND_ERR                0x1C\n+\n+#define TAS5713_INPUT_MUX               0x20\n+#define TAS5713_SRC_SELECT_CH4          0x21\n+#define TAS5713_PWM_MUX                 0x25\n+\n+#define TAS5713_CH1_BQ0                 0x29\n+#define TAS5713_CH1_BQ1                 0x2A\n+#define TAS5713_CH1_BQ2                 0x2B\n+#define TAS5713_CH1_BQ3                 0x2C\n+#define TAS5713_CH1_BQ4                 0x2D\n+#define TAS5713_CH1_BQ5                 0x2E\n+#define TAS5713_CH1_BQ6                 0x2F\n+#define TAS5713_CH1_BQ7                 0x58\n+#define TAS5713_CH1_BQ8                 0x59\n+\n+#define TAS5713_CH2_BQ0                 0x30\n+#define TAS5713_CH2_BQ1                 0x31\n+#define TAS5713_CH2_BQ2                 0x32\n+#define TAS5713_CH2_BQ3                 0x33\n+#define TAS5713_CH2_BQ4                 0x34\n+#define TAS5713_CH2_BQ5                 0x35\n+#define TAS5713_CH2_BQ6                 0x36\n+#define TAS5713_CH2_BQ7                 0x5C\n+#define TAS5713_CH2_BQ8                 0x5D\n+\n+#define TAS5713_CH4_BQ0                 0x5A\n+#define TAS5713_CH4_BQ1                 0x5B\n+#define TAS5713_CH3_BQ0                 0x5E\n+#define TAS5713_CH3_BQ1                 0x5F\n+\n+#define TAS5713_DRC1_SOFTENING_FILTER_ALPHA_OMEGA       0x3B\n+#define TAS5713_DRC1_ATTACK_RELEASE_RATE                0x3C\n+#define TAS5713_DRC2_SOFTENING_FILTER_ALPHA_OMEGA       0x3E\n+#define TAS5713_DRC2_ATTACK_RELEASE_RATE                0x3F\n+#define TAS5713_DRC1_ATTACK_RELEASE_THRES               0x40\n+#define TAS5713_DRC2_ATTACK_RELEASE_THRES               0x43\n+#define TAS5713_DRC_CTRL                                0x46\n+\n+#define TAS5713_BANK_SW_CTRL            0x50\n+#define TAS5713_CH1_OUTPUT_MIXER        0x51\n+#define TAS5713_CH2_OUTPUT_MIXER        0x52\n+#define TAS5713_CH1_INPUT_MIXER         0x53\n+#define TAS5713_CH2_INPUT_MIXER         0x54\n+#define TAS5713_OUTPUT_POST_SCALE       0x56\n+#define TAS5713_OUTPUT_PRESCALE         0x57\n+\n+#define TAS5713_IDF_POST_SCALE          0x62\n+\n+#define TAS5713_CH1_INLINE_MIXER        0x70\n+#define TAS5713_CH1_INLINE_DRC_EN_MIXER 0x71\n+#define TAS5713_CH1_R_CHANNEL_MIXER     0x72\n+#define TAS5713_CH1_L_CHANNEL_MIXER     0x73\n+#define TAS5713_CH2_INLINE_MIXER        0x74\n+#define TAS5713_CH2_INLINE_DRC_EN_MIXER 0x75\n+#define TAS5713_CH2_L_CHANNEL_MIXER     0x76\n+#define TAS5713_CH2_R_CHANNEL_MIXER     0x77\n+\n+#define TAS5713_UPDATE_DEV_ADDR_KEY     0xF8\n+#define TAS5713_UPDATE_DEV_ADDR_REG     0xF9\n+\n+#define TAS5713_REGISTER_COUNT          0x46\n+#define TAS5713_MAX_REGISTER            0xF9\n+\n+\n+// Bitmasks for registers\n+#define TAS5713_SOFT_MUTE_ALL           0x07\n+\n+\n+\n+struct tas5713_init_command {\n+        const int size;\n+        const char *const data;\n+};\n+\n+static const struct tas5713_init_command tas5713_init_sequence[] = {\n+\n+        // Trim oscillator\n+    { .size = 2,  .data = \"\\x1B\\x00\" },\n+    // System control register 1 (0x03): block DC\n+    { .size = 2,  .data = \"\\x03\\x80\" },\n+    // Mute everything\n+    { .size = 2,  .data = \"\\x05\\x40\" },\n+    // Modulation limit register (0x10): 97.7%\n+    { .size = 2,  .data = \"\\x10\\x02\" },\n+    // Interchannel delay registers\n+    // (0x11, 0x12, 0x13, and 0x14): BD mode\n+    { .size = 2,  .data = \"\\x11\\xB8\" },\n+    { .size = 2,  .data = \"\\x12\\x60\" },\n+    { .size = 2,  .data = \"\\x13\\xA0\" },\n+    { .size = 2,  .data = \"\\x14\\x48\" },\n+    // PWM shutdown group register (0x19): no shutdown\n+    { .size = 2,  .data = \"\\x19\\x00\" },\n+    // Input multiplexer register (0x20): BD mode\n+    { .size = 2,  .data = \"\\x20\\x00\\x89\\x77\\x72\" },\n+    // PWM output mux register (0x25)\n+    // Channel 1 --> OUTA, channel 1 neg --> OUTB\n+    // Channel 2 --> OUTC, channel 2 neg --> OUTD\n+    { .size = 5,  .data = \"\\x25\\x01\\x02\\x13\\x45\" },\n+    // DRC control (0x46): DRC off\n+    { .size = 5,  .data = \"\\x46\\x00\\x00\\x00\\x00\" },\n+    // BKND_ERR register (0x1C): 299ms reset period\n+    { .size = 2,  .data = \"\\x1C\\x07\" },\n+    // Mute channel 3\n+    { .size = 2,  .data = \"\\x0A\\xFF\" },\n+    // Volume configuration register (0x0E): volume slew 512 steps\n+    { .size = 2,  .data = \"\\x0E\\x90\" },\n+    // Clock control register (0x00): 44/48kHz, MCLK=64xfs\n+    { .size = 2,  .data = \"\\x00\\x60\" },\n+    // Bank switch and eq control (0x50): no bank switching\n+    { .size = 5,  .data = \"\\x50\\x00\\x00\\x00\\x00\" },\n+    // Volume registers (0x07, 0x08, 0x09, 0x0A)\n+    { .size = 2,  .data = \"\\x07\\x20\" },\n+    { .size = 2,  .data = \"\\x08\\x30\" },\n+    { .size = 2,  .data = \"\\x09\\x30\" },\n+    { .size = 2,  .data = \"\\x0A\\xFF\" },\n+    // 0x72, 0x73, 0x76, 0x77 input mixer:\n+    // no intermix between channels\n+    { .size = 5,  .data = \"\\x72\\x00\\x00\\x00\\x00\" },\n+    { .size = 5,  .data = \"\\x73\\x00\\x80\\x00\\x00\" },\n+    { .size = 5,  .data = \"\\x76\\x00\\x00\\x00\\x00\" },\n+    { .size = 5,  .data = \"\\x77\\x00\\x80\\x00\\x00\" },\n+    // 0x70, 0x71, 0x74, 0x75 inline DRC mixer:\n+    // no inline DRC inmix\n+    { .size = 5,  .data = \"\\x70\\x00\\x80\\x00\\x00\" },\n+    { .size = 5,  .data = \"\\x71\\x00\\x00\\x00\\x00\" },\n+    { .size = 5,  .data = \"\\x74\\x00\\x80\\x00\\x00\" },\n+    { .size = 5,  .data = \"\\x75\\x00\\x00\\x00\\x00\" },\n+    // 0x56, 0x57 Output scale\n+    { .size = 5,  .data = \"\\x56\\x00\\x80\\x00\\x00\" },\n+    { .size = 5,  .data = \"\\x57\\x00\\x02\\x00\\x00\" },\n+    // 0x3B, 0x3c\n+    { .size = 9,  .data = \"\\x3B\\x00\\x08\\x00\\x00\\x00\\x78\\x00\\x00\" },\n+    { .size = 9,  .data = \"\\x3C\\x00\\x00\\x01\\x00\\xFF\\xFF\\xFF\\x00\" },\n+    { .size = 9,  .data = \"\\x3E\\x00\\x08\\x00\\x00\\x00\\x78\\x00\\x00\" },\n+    { .size = 9,  .data = \"\\x3F\\x00\\x00\\x01\\x00\\xFF\\xFF\\xFF\\x00\" },\n+    { .size = 9,  .data = \"\\x40\\x00\\x00\\x01\\x00\\xFF\\xFF\\xFF\\x00\" },\n+    { .size = 9,  .data = \"\\x43\\x00\\x00\\x01\\x00\\xFF\\xFF\\xFF\\x00\" },\n+    // 0x51, 0x52: output mixer\n+    { .size = 9,  .data = \"\\x51\\x00\\x80\\x00\\x00\\x00\\x00\\x00\\x00\" },\n+    { .size = 9,  .data = \"\\x52\\x00\\x80\\x00\\x00\\x00\\x00\\x00\\x00\" },\n+    // PEQ defaults\n+    { .size = 21,  .data = \"\\x29\\x00\\x80\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\" },\n+    { .size = 21,  .data = \"\\x2A\\x00\\x80\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\" },\n+    { .size = 21,  .data = \"\\x2B\\x00\\x80\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\" },\n+    { .size = 21,  .data = \"\\x2C\\x00\\x80\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\" },\n+    { .size = 21,  .data = \"\\x2D\\x00\\x80\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\" },\n+    { .size = 21,  .data = \"\\x2E\\x00\\x80\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\" },\n+    { .size = 21,  .data = \"\\x2F\\x00\\x80\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\" },\n+    { .size = 21,  .data = \"\\x30\\x00\\x80\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\" },\n+    { .size = 21,  .data = \"\\x31\\x00\\x80\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\" },\n+    { .size = 21,  .data = \"\\x32\\x00\\x80\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\" },\n+    { .size = 21,  .data = \"\\x33\\x00\\x80\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\" },\n+    { .size = 21,  .data = \"\\x34\\x00\\x80\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\" },\n+    { .size = 21,  .data = \"\\x35\\x00\\x80\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\" },\n+    { .size = 21,  .data = \"\\x36\\x00\\x80\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\" },\n+    { .size = 21,  .data = \"\\x58\\x00\\x80\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\" },\n+    { .size = 21,  .data = \"\\x59\\x00\\x80\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\" },\n+    { .size = 21,  .data = \"\\x5C\\x00\\x80\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\" },\n+    { .size = 21,  .data = \"\\x5D\\x00\\x80\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\" },\n+    { .size = 21,  .data = \"\\x5E\\x00\\x80\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\" },\n+    { .size = 21,  .data = \"\\x5F\\x00\\x80\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\" },\n+    { .size = 21,  .data = \"\\x5A\\x00\\x80\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\" },\n+    { .size = 21,  .data = \"\\x5B\\x00\\x80\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\" },\n+};\n+\n+\n+#endif  /* _TAS5713_H */\n--- a/sound/soc/soc-core.c\n+++ b/sound/soc/soc-core.c\n@@ -1429,7 +1429,15 @@ int snd_soc_runtime_set_dai_fmt(struct s\n \tint ret;\n \n \tfor_each_rtd_codec_dais(rtd, i, codec_dai) {\n-\t\tret = snd_soc_dai_set_fmt(codec_dai, dai_fmt);\n+\t\tunsigned int codec_dai_fmt = dai_fmt;\n+\n+\t\t// there can only be one master when using multiple codecs\n+\t\tif (i && (codec_dai_fmt & SND_SOC_DAIFMT_MASTER_MASK)) {\n+\t\t\tcodec_dai_fmt &= ~SND_SOC_DAIFMT_MASTER_MASK;\n+\t\t\tcodec_dai_fmt |= SND_SOC_DAIFMT_CBS_CFS;\n+\t\t}\n+\n+\t\tret = snd_soc_dai_set_fmt(codec_dai, codec_dai_fmt);\n \t\tif (ret != 0 && ret != -ENOTSUPP) {\n \t\t\tdev_warn(codec_dai->dev,\n \t\t\t\t \"ASoC: Failed to set DAI format: %d\\n\", ret);\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0061-Fixes-a-problem-when-module-probes-before-i2c-module.patch",
    "content": "From 4be98b29d123fc7615ea8404fbda450ec8acb084 Mon Sep 17 00:00:00 2001\nFrom: Joerg Schambacher <joerg@i2audio.com>\nDate: Fri, 16 Oct 2020 15:17:07 +0200\nSubject: [PATCH] Fixes a problem when module probes before i2c module\n is available\n\nThe driver crashed while a NULL pointer returned by i2c_get_adapter()\nhas been used to access the i2c bus functions.\nThe headphone probing function hb_hp_probe() now returns -EPROBE_DEFER\nin case the i2c module has not been loaded yet.\n\nSigned-off-by: Joerg Schambacher <joerg@i2audio.com>\n---\n sound/soc/bcm/hifiberry_dacplus.c | 9 +++++++--\n 1 file changed, 7 insertions(+), 2 deletions(-)\n\n--- a/sound/soc/bcm/hifiberry_dacplus.c\n+++ b/sound/soc/bcm/hifiberry_dacplus.c\n@@ -315,12 +315,14 @@ static int hb_hp_detect(void)\n {\n \tstruct i2c_adapter *adap = i2c_get_adapter(1);\n \tint ret;\n-\n \tstruct i2c_client tpa_i2c_client = {\n \t\t.addr = 0x60,\n \t\t.adapter = adap,\n \t};\n \n+\tif (!adap)\n+\t\treturn -EPROBE_DEFER;\t/* I2C module not yet available */\n+\n \tret = i2c_smbus_read_byte(&tpa_i2c_client) >= 0;\n \ti2c_put_adapter(adap);\n \treturn ret;\n@@ -342,7 +344,10 @@ static int snd_rpi_hifiberry_dacplus_pro\n \tstruct of_changeset ocs;\n \n \t/* probe for head phone amp */\n-\tif (hb_hp_detect()) {\n+\tret = hb_hp_detect();\n+\tif (ret < 0)\n+\t\treturn ret;\n+\tif (ret) {\n \t\tcard->aux_dev = hifiberry_dacplus_aux_devs;\n \t\tcard->num_aux_devs =\n \t\t\t\tARRAY_SIZE(hifiberry_dacplus_aux_devs);\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0062-rpi_display-add-backlight-driver-and-overlay.patch",
    "content": "From 3bbdfc9493655ea9ff7e3c8eeee85f28b0f84369 Mon Sep 17 00:00:00 2001\nFrom: P33M <P33M@github.com>\nDate: Wed, 21 Oct 2015 14:55:21 +0100\nSubject: [PATCH] rpi_display: add backlight driver and overlay\n\nAdd a mailbox-driven backlight controller for the Raspberry Pi DSI\ntouchscreen display. Requires updated GPU firmware to recognise the\nmailbox request.\n\nSigned-off-by: Gordon Hollingworth <gordon@raspberrypi.org>\n\nAdd Raspberry Pi firmware driver to the dependencies of backlight driver\n\nOtherwise the backlight driver fails to build if the firmware\nloading driver is not in the kernel\n\nSigned-off-by: Alex Riesen <alexander.riesen@cetitec.com>\n---\n drivers/video/backlight/Kconfig         |   7 ++\n drivers/video/backlight/Makefile        |   1 +\n drivers/video/backlight/rpi_backlight.c | 119 ++++++++++++++++++++++++\n 3 files changed, 127 insertions(+)\n create mode 100644 drivers/video/backlight/rpi_backlight.c\n\n--- a/drivers/video/backlight/Kconfig\n+++ b/drivers/video/backlight/Kconfig\n@@ -248,6 +248,13 @@ config BACKLIGHT_PWM\n \t  If you have a LCD backlight adjustable by PWM, say Y to enable\n \t  this driver.\n \n+config BACKLIGHT_RPI\n+\ttristate \"Raspberry Pi display firmware driven backlight\"\n+\tdepends on RASPBERRYPI_FIRMWARE\n+\thelp\n+\t  If you have the Raspberry Pi DSI touchscreen display, say Y to\n+\t  enable the mailbox-controlled backlight driver.\n+\n config BACKLIGHT_DA903X\n \ttristate \"Backlight Driver for DA9030/DA9034 using WLED\"\n \tdepends on PMIC_DA903X\n--- a/drivers/video/backlight/Makefile\n+++ b/drivers/video/backlight/Makefile\n@@ -49,6 +49,7 @@ obj-$(CONFIG_BACKLIGHT_PANDORA)\t\t+= pand\n obj-$(CONFIG_BACKLIGHT_PCF50633)\t+= pcf50633-backlight.o\n obj-$(CONFIG_BACKLIGHT_PWM)\t\t+= pwm_bl.o\n obj-$(CONFIG_BACKLIGHT_QCOM_WLED)\t+= qcom-wled.o\n+obj-$(CONFIG_BACKLIGHT_RPI)\t\t\t+= rpi_backlight.o\n obj-$(CONFIG_BACKLIGHT_SAHARA)\t\t+= kb3886_bl.o\n obj-$(CONFIG_BACKLIGHT_SKY81452)\t+= sky81452-backlight.o\n obj-$(CONFIG_BACKLIGHT_TOSA)\t\t+= tosa_bl.o\n--- /dev/null\n+++ b/drivers/video/backlight/rpi_backlight.c\n@@ -0,0 +1,119 @@\n+/*\n+ * rpi_bl.c - Backlight controller through VPU\n+ *\n+ * This program is free software; you can redistribute it and/or modify\n+ * it under the terms of the GNU General Public License version 2 as\n+ * published by the Free Software Foundation.\n+ */\n+\n+#include <linux/backlight.h>\n+#include <linux/err.h>\n+#include <linux/fb.h>\n+#include <linux/gpio.h>\n+#include <linux/init.h>\n+#include <linux/kernel.h>\n+#include <linux/module.h>\n+#include <linux/of.h>\n+#include <linux/of_gpio.h>\n+#include <linux/platform_device.h>\n+#include <linux/slab.h>\n+#include <soc/bcm2835/raspberrypi-firmware.h>\n+\n+struct rpi_backlight {\n+\tstruct device *dev;\n+\tstruct device *fbdev;\n+\tstruct rpi_firmware *fw;\n+};\n+\n+static int rpi_backlight_update_status(struct backlight_device *bl)\n+{\n+\tstruct rpi_backlight *gbl = bl_get_data(bl);\n+\tint brightness = bl->props.brightness;\n+\tint ret;\n+\n+\tif (bl->props.power != FB_BLANK_UNBLANK ||\n+\t    bl->props.fb_blank != FB_BLANK_UNBLANK ||\n+\t    bl->props.state & (BL_CORE_SUSPENDED | BL_CORE_FBBLANK))\n+\t\tbrightness = 0;\n+\n+\tret = rpi_firmware_property(gbl->fw,\n+\t\t\tRPI_FIRMWARE_FRAMEBUFFER_SET_BACKLIGHT,\n+\t\t\t&brightness, sizeof(brightness));\n+\tif (ret) {\n+\t\tdev_err(gbl->dev, \"Failed to set brightness\\n\");\n+\t\treturn ret;\n+\t}\n+\n+\tif (brightness < 0) {\n+\t\tdev_err(gbl->dev, \"Backlight change failed\\n\");\n+\t\treturn -EAGAIN;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static const struct backlight_ops rpi_backlight_ops = {\n+\t.options\t= BL_CORE_SUSPENDRESUME,\n+\t.update_status\t= rpi_backlight_update_status,\n+};\n+\n+static int rpi_backlight_probe(struct platform_device *pdev)\n+{\n+\tstruct backlight_properties props;\n+\tstruct backlight_device *bl;\n+\tstruct rpi_backlight *gbl;\n+\tstruct device_node *fw_node;\n+\n+\tgbl = devm_kzalloc(&pdev->dev, sizeof(*gbl), GFP_KERNEL);\n+\tif (gbl == NULL)\n+\t\treturn -ENOMEM;\n+\n+\tgbl->dev = &pdev->dev;\n+\n+\tfw_node = of_parse_phandle(pdev->dev.of_node, \"firmware\", 0);\n+\tif (!fw_node) {\n+\t\tdev_err(&pdev->dev, \"Missing firmware node\\n\");\n+\t\treturn -ENOENT;\n+\t}\n+\n+\tgbl->fw = rpi_firmware_get(fw_node);\n+\tif (!gbl->fw)\n+\t\treturn -EPROBE_DEFER;\n+\n+\tmemset(&props, 0, sizeof(props));\n+\tprops.type = BACKLIGHT_RAW;\n+\tprops.max_brightness = 255;\n+\tbl = devm_backlight_device_register(&pdev->dev, dev_name(&pdev->dev),\n+\t\t\t\t\t&pdev->dev, gbl, &rpi_backlight_ops,\n+\t\t\t\t\t&props);\n+\tif (IS_ERR(bl)) {\n+\t\tdev_err(&pdev->dev, \"failed to register backlight\\n\");\n+\t\treturn PTR_ERR(bl);\n+\t}\n+\n+\tbl->props.brightness = 255;\n+\tbacklight_update_status(bl);\n+\n+\tplatform_set_drvdata(pdev, bl);\n+\treturn 0;\n+}\n+\n+static const struct of_device_id rpi_backlight_of_match[] = {\n+\t{ .compatible = \"raspberrypi,rpi-backlight\" },\n+\t{ /* sentinel */ }\n+};\n+MODULE_DEVICE_TABLE(of, rpi_backlight_of_match);\n+\n+static struct platform_driver rpi_backlight_driver = {\n+\t.driver\t\t= {\n+\t\t.name\t\t= \"rpi-backlight\",\n+\t\t.of_match_table = of_match_ptr(rpi_backlight_of_match),\n+\t},\n+\t.probe\t\t= rpi_backlight_probe,\n+};\n+\n+module_platform_driver(rpi_backlight_driver);\n+\n+MODULE_AUTHOR(\"Gordon Hollingworth <gordon@raspberrypi.org>\");\n+MODULE_DESCRIPTION(\"Raspberry Pi mailbox based Backlight Driver\");\n+MODULE_LICENSE(\"GPL\");\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0063-bcm2835-virtgpio-Virtual-GPIO-driver.patch",
    "content": "From f82deda879262289568dec22dd43ecc10c265fb6 Mon Sep 17 00:00:00 2001\nFrom: popcornmix <popcornmix@gmail.com>\nDate: Tue, 23 Feb 2016 19:56:04 +0000\nSubject: [PATCH] bcm2835-virtgpio: Virtual GPIO driver\n\nAdd a virtual GPIO driver that uses the firmware mailbox interface to\nrequest that the VPU toggles LEDs.\n---\n drivers/gpio/Kconfig         |   6 +\n drivers/gpio/Makefile        |   1 +\n drivers/gpio/gpio-bcm-virt.c | 214 +++++++++++++++++++++++++++++++++++\n 3 files changed, 221 insertions(+)\n create mode 100644 drivers/gpio/gpio-bcm-virt.c\n\n--- a/drivers/gpio/Kconfig\n+++ b/drivers/gpio/Kconfig\n@@ -193,6 +193,12 @@ config GPIO_BCM_XGS_IPROC\n \thelp\n \t  Say yes here to enable GPIO support for Broadcom XGS iProc SoCs.\n \n+config GPIO_BCM_VIRT\n+\tbool \"Broadcom Virt GPIO\"\n+\tdepends on OF_GPIO && RASPBERRYPI_FIRMWARE && (ARCH_BCM2835 || COMPILE_TEST)\n+\thelp\n+\t  Turn on virtual GPIO support for Broadcom BCM283X chips.\n+\n config GPIO_BRCMSTB\n \ttristate \"BRCMSTB GPIO support\"\n \tdefault y if (ARCH_BRCMSTB || BMIPS_GENERIC)\n--- a/drivers/gpio/Makefile\n+++ b/drivers/gpio/Makefile\n@@ -38,6 +38,7 @@ obj-$(CONFIG_GPIO_ASPEED_SGPIO)\t\t+= gpio\n obj-$(CONFIG_GPIO_ATH79)\t\t+= gpio-ath79.o\n obj-$(CONFIG_GPIO_BCM_KONA)\t\t+= gpio-bcm-kona.o\n obj-$(CONFIG_GPIO_BCM_XGS_IPROC)\t+= gpio-xgs-iproc.o\n+obj-$(CONFIG_GPIO_BCM_VIRT)\t\t+= gpio-bcm-virt.o\n obj-$(CONFIG_GPIO_BD70528)\t\t+= gpio-bd70528.o\n obj-$(CONFIG_GPIO_BD71828)\t\t+= gpio-bd71828.o\n obj-$(CONFIG_GPIO_BD9571MWV)\t\t+= gpio-bd9571mwv.o\n--- /dev/null\n+++ b/drivers/gpio/gpio-bcm-virt.c\n@@ -0,0 +1,214 @@\n+/*\n+ *  brcmvirt GPIO driver\n+ *\n+ *  Copyright (C) 2012,2013 Dom Cobley <popcornmix@gmail.com>\n+ *  Based on gpio-clps711x.c by Alexander Shiyan <shc_work@mail.ru>\n+ *\n+ * This program is free software; you can redistribute it and/or modify\n+ * it under the terms of the GNU General Public License as published by\n+ * the Free Software Foundation; either version 2 of the License, or\n+ * (at your option) any later version.\n+ */\n+\n+#include <linux/err.h>\n+#include <linux/gpio.h>\n+#include <linux/module.h>\n+#include <linux/platform_device.h>\n+#include <linux/dma-mapping.h>\n+#include <soc/bcm2835/raspberrypi-firmware.h>\n+\n+#define MODULE_NAME \"brcmvirt-gpio\"\n+#define NUM_GPIO 2\n+\n+struct brcmvirt_gpio {\n+\tstruct gpio_chip\tgc;\n+\tu32 __iomem\t\t*ts_base;\n+\t/* two packed 16-bit counts of enabled and disables\n+           Allows host to detect a brief enable that was missed */\n+\tu32\t\t\tenables_disables[NUM_GPIO];\n+\tdma_addr_t\t\tbus_addr;\n+};\n+\n+static int brcmvirt_gpio_dir_in(struct gpio_chip *gc, unsigned off)\n+{\n+\tstruct brcmvirt_gpio *gpio;\n+\tgpio = container_of(gc, struct brcmvirt_gpio, gc);\n+\treturn -EINVAL;\n+}\n+\n+static int brcmvirt_gpio_dir_out(struct gpio_chip *gc, unsigned off, int val)\n+{\n+\tstruct brcmvirt_gpio *gpio;\n+\tgpio = container_of(gc, struct brcmvirt_gpio, gc);\n+\treturn 0;\n+}\n+\n+static int brcmvirt_gpio_get(struct gpio_chip *gc, unsigned off)\n+{\n+\tstruct brcmvirt_gpio *gpio;\n+\tunsigned v;\n+\tgpio = container_of(gc, struct brcmvirt_gpio, gc);\n+\tv = readl(gpio->ts_base + off);\n+\treturn (v >> off) & 1;\n+}\n+\n+static void brcmvirt_gpio_set(struct gpio_chip *gc, unsigned off, int val)\n+{\n+\tstruct brcmvirt_gpio *gpio;\n+\tu16 enables, disables;\n+\ts16 diff;\n+\tbool lit;\n+\tgpio = container_of(gc, struct brcmvirt_gpio, gc);\n+\tenables  = gpio->enables_disables[off] >> 16;\n+\tdisables = gpio->enables_disables[off] >>  0;\n+\tdiff = (s16)(enables - disables);\n+\tlit = diff > 0;\n+\tif ((val && lit) || (!val && !lit))\n+\t\treturn;\n+\tif (val)\n+\t\tenables++;\n+\telse\n+\t\tdisables++;\n+\tdiff = (s16)(enables - disables);\n+\tBUG_ON(diff != 0 && diff != 1);\n+\tgpio->enables_disables[off] = (enables << 16) | (disables << 0);\n+\twritel(gpio->enables_disables[off], gpio->ts_base + off);\n+}\n+\n+static int brcmvirt_gpio_probe(struct platform_device *pdev)\n+{\n+\tint err = 0;\n+\tstruct device *dev = &pdev->dev;\n+\tstruct device_node *np = dev->of_node;\n+\tstruct device_node *fw_node;\n+\tstruct rpi_firmware *fw;\n+\tstruct brcmvirt_gpio *ucb;\n+\tu32 gpiovirtbuf;\n+\n+\tfw_node = of_parse_phandle(np, \"firmware\", 0);\n+\tif (!fw_node) {\n+\t\tdev_err(dev, \"Missing firmware node\\n\");\n+\t\treturn -ENOENT;\n+\t}\n+\n+\tfw = rpi_firmware_get(fw_node);\n+\tif (!fw)\n+\t\treturn -EPROBE_DEFER;\n+\n+\tucb = devm_kzalloc(dev, sizeof *ucb, GFP_KERNEL);\n+\tif (!ucb) {\n+\t\terr = -EINVAL;\n+\t\tgoto out;\n+\t}\n+\n+\tucb->ts_base = dma_alloc_coherent(dev, PAGE_SIZE, &ucb->bus_addr, GFP_KERNEL);\n+\tif (!ucb->ts_base) {\n+\t\tpr_err(\"[%s]: failed to dma_alloc_coherent(%ld)\\n\",\n+\t\t\t\t__func__, PAGE_SIZE);\n+\t\terr = -ENOMEM;\n+\t\tgoto out;\n+\t}\n+\n+\tgpiovirtbuf = (u32)ucb->bus_addr;\n+\terr = rpi_firmware_property(fw, RPI_FIRMWARE_FRAMEBUFFER_SET_GPIOVIRTBUF,\n+\t\t\t\t    &gpiovirtbuf, sizeof(gpiovirtbuf));\n+\n+\tif (err || gpiovirtbuf != 0) {\n+\t\tdev_warn(dev, \"Failed to set gpiovirtbuf, trying to get err:%x\\n\", err);\n+\t\tdma_free_coherent(dev, PAGE_SIZE, ucb->ts_base, ucb->bus_addr);\n+\t\tucb->ts_base = 0;\n+\t\tucb->bus_addr = 0;\n+\t}\n+\n+\tif (!ucb->ts_base) {\n+\t\terr = rpi_firmware_property(fw, RPI_FIRMWARE_FRAMEBUFFER_GET_GPIOVIRTBUF,\n+\t\t\t\t\t    &gpiovirtbuf, sizeof(gpiovirtbuf));\n+\n+\t\tif (err) {\n+\t\t\tdev_err(dev, \"Failed to get gpiovirtbuf\\n\");\n+\t\t\tgoto out;\n+\t\t}\n+\n+\t\tif (!gpiovirtbuf) {\n+\t\t\tdev_err(dev, \"No virtgpio buffer\\n\");\n+\t\t\terr = -ENOENT;\n+\t\t\tgoto out;\n+\t\t}\n+\n+\t\t// mmap the physical memory\n+\t\tgpiovirtbuf &= ~0xc0000000;\n+\t\tucb->ts_base = ioremap(gpiovirtbuf, 4096);\n+\t\tif (ucb->ts_base == NULL) {\n+\t\t\tdev_err(dev, \"Failed to map physical address\\n\");\n+\t\t\terr = -ENOENT;\n+\t\t\tgoto out;\n+\t\t}\n+\t\tucb->bus_addr = 0;\n+\t}\n+\tucb->gc.label = MODULE_NAME;\n+\tucb->gc.owner = THIS_MODULE;\n+\t//ucb->gc.dev = dev;\n+\tucb->gc.of_node = np;\n+\tucb->gc.base = 100;\n+\tucb->gc.ngpio = NUM_GPIO;\n+\n+\tucb->gc.direction_input = brcmvirt_gpio_dir_in;\n+\tucb->gc.direction_output = brcmvirt_gpio_dir_out;\n+\tucb->gc.get = brcmvirt_gpio_get;\n+\tucb->gc.set = brcmvirt_gpio_set;\n+\tucb->gc.can_sleep = true;\n+\n+\terr = gpiochip_add(&ucb->gc);\n+\tif (err)\n+\t\tgoto out;\n+\n+\tplatform_set_drvdata(pdev, ucb);\n+\n+\treturn 0;\n+out:\n+\tif (ucb->bus_addr) {\n+\t\tdma_free_coherent(dev, PAGE_SIZE, ucb->ts_base, ucb->bus_addr);\n+\t\tucb->bus_addr = 0;\n+\t\tucb->ts_base = NULL;\n+\t} else if (ucb->ts_base) {\n+\t\tiounmap(ucb->ts_base);\n+\t\tucb->ts_base = NULL;\n+\t}\n+\treturn err;\n+}\n+\n+static int brcmvirt_gpio_remove(struct platform_device *pdev)\n+{\n+\tstruct device *dev = &pdev->dev;\n+\tint err = 0;\n+\tstruct brcmvirt_gpio *ucb = platform_get_drvdata(pdev);\n+\n+\tgpiochip_remove(&ucb->gc);\n+\tif (ucb->bus_addr)\n+\t\tdma_free_coherent(dev, PAGE_SIZE, ucb->ts_base, ucb->bus_addr);\n+\telse if (ucb->ts_base)\n+\t\tiounmap(ucb->ts_base);\n+\treturn err;\n+}\n+\n+static const struct of_device_id __maybe_unused brcmvirt_gpio_ids[] = {\n+\t{ .compatible = \"brcm,bcm2835-virtgpio\" },\n+\t{ }\n+};\n+MODULE_DEVICE_TABLE(of, brcmvirt_gpio_ids);\n+\n+static struct platform_driver brcmvirt_gpio_driver = {\n+\t.driver\t= {\n+\t\t.name\t\t= MODULE_NAME,\n+\t\t.owner\t\t= THIS_MODULE,\n+\t\t.of_match_table\t= of_match_ptr(brcmvirt_gpio_ids),\n+\t},\n+\t.probe\t= brcmvirt_gpio_probe,\n+\t.remove\t= brcmvirt_gpio_remove,\n+};\n+module_platform_driver(brcmvirt_gpio_driver);\n+\n+MODULE_LICENSE(\"GPL\");\n+MODULE_AUTHOR(\"Dom Cobley <popcornmix@gmail.com>\");\n+MODULE_DESCRIPTION(\"brcmvirt GPIO driver\");\n+MODULE_ALIAS(\"platform:brcmvirt-gpio\");\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0064-OF-DT-Overlay-configfs-interface.patch",
    "content": "From 3027a12f910d164be1cb7c028dd178409ace7f0a Mon Sep 17 00:00:00 2001\nFrom: Pantelis Antoniou <pantelis.antoniou@konsulko.com>\nDate: Wed, 3 Dec 2014 13:23:28 +0200\nSubject: [PATCH] OF: DT-Overlay configfs interface\n\nThis is a port of Pantelis Antoniou's v3 port that makes use of the\nnew upstreamed configfs support for binary attributes.\n\nOriginal commit message:\n\nAdd a runtime interface to using configfs for generic device tree overlay\nusage. With it its possible to use device tree overlays without having\nto use a per-platform overlay manager.\n\nPlease see Documentation/devicetree/configfs-overlays.txt for more info.\n\nChanges since v2:\n- Removed ifdef CONFIG_OF_OVERLAY (since for now it's required)\n- Created a documentation entry\n- Slight rewording in Kconfig\n\nChanges since v1:\n- of_resolve() -> of_resolve_phandles().\n\nOriginally-signed-off-by: Pantelis Antoniou <pantelis.antoniou@konsulko.com>\nSigned-off-by: Phil Elwell <phil@raspberrypi.org>\n\nDT configfs: Fix build errors on other platforms\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.org>\n\nDT configfs: fix build error\n\nThere is an error when compiling rpi-4.6.y branch:\n  CC      drivers/of/configfs.o\ndrivers/of/configfs.c:291:21: error: initialization from incompatible pointer type [-Werror=incompatible-pointer-types]\n   .default_groups = of_cfs_def_groups,\n                     ^\ndrivers/of/configfs.c:291:21: note: (near initialization for 'of_cfs_subsys.su_group.default_groups.next')\n\nThe .default_groups is linked list since commit\n1ae1602de028acaa42a0f6ff18d19756f8e825c6.\nThis commit uses configfs_add_default_group to fix this problem.\n\nSigned-off-by: Slawomir Stepien <sst@poczta.fm>\n\nconfigfs: New of_overlay API\n---\n .../devicetree/configfs-overlays.txt          |  31 ++\n drivers/of/Kconfig                            |   7 +\n drivers/of/Makefile                           |   1 +\n drivers/of/configfs.c                         | 310 ++++++++++++++++++\n 4 files changed, 349 insertions(+)\n create mode 100644 Documentation/devicetree/configfs-overlays.txt\n create mode 100644 drivers/of/configfs.c\n\n--- /dev/null\n+++ b/Documentation/devicetree/configfs-overlays.txt\n@@ -0,0 +1,31 @@\n+Howto use the configfs overlay interface.\n+\n+A device-tree configfs entry is created in /config/device-tree/overlays\n+and and it is manipulated using standard file system I/O.\n+Note that this is a debug level interface, for use by developers and\n+not necessarily something accessed by normal users due to the\n+security implications of having direct access to the kernel's device tree.\n+\n+* To create an overlay you mkdir the directory:\n+\n+\t# mkdir /config/device-tree/overlays/foo\n+\n+* Either you echo the overlay firmware file to the path property file.\n+\n+\t# echo foo.dtbo >/config/device-tree/overlays/foo/path\n+\n+* Or you cat the contents of the overlay to the dtbo file\n+\n+\t# cat foo.dtbo >/config/device-tree/overlays/foo/dtbo\n+\n+The overlay file will be applied, and devices will be created/destroyed\n+as required.\n+\n+To remove it simply rmdir the directory.\n+\n+\t# rmdir /config/device-tree/overlays/foo\n+\n+The rationalle of the dual interface (firmware & direct copy) is that each is\n+better suited to different use patterns. The firmware interface is what's\n+intended to be used by hardware managers in the kernel, while the copy interface\n+make sense for developers (since it avoids problems with namespaces).\n--- a/drivers/of/Kconfig\n+++ b/drivers/of/Kconfig\n@@ -100,4 +100,11 @@ config OF_DMA_DEFAULT_COHERENT\n \t# arches should select this if DMA is coherent by default for OF devices\n \tbool\n \n+config OF_CONFIGFS\n+\tbool \"Device Tree Overlay ConfigFS interface\"\n+\tselect CONFIGFS_FS\n+\tselect OF_OVERLAY\n+\thelp\n+\t  Enable a simple user-space driven DT overlay interface.\n+\n endif # OF\n--- a/drivers/of/Makefile\n+++ b/drivers/of/Makefile\n@@ -1,6 +1,7 @@\n # SPDX-License-Identifier: GPL-2.0\n obj-y = base.o device.o platform.o property.o\n obj-$(CONFIG_OF_KOBJ) += kobj.o\n+obj-$(CONFIG_OF_CONFIGFS) += configfs.o\n obj-$(CONFIG_OF_DYNAMIC) += dynamic.o\n obj-$(CONFIG_OF_FLATTREE) += fdt.o\n obj-$(CONFIG_OF_EARLY_FLATTREE) += fdt_address.o\n--- /dev/null\n+++ b/drivers/of/configfs.c\n@@ -0,0 +1,310 @@\n+/*\n+ * Configfs entries for device-tree\n+ *\n+ * Copyright (C) 2013 - Pantelis Antoniou <panto@antoniou-consulting.com>\n+ *\n+ * This program is free software; you can redistribute it and/or\n+ * modify it under the terms of the GNU General Public License\n+ * as published by the Free Software Foundation; either version\n+ * 2 of the License, or (at your option) any later version.\n+ */\n+#include <linux/ctype.h>\n+#include <linux/cpu.h>\n+#include <linux/module.h>\n+#include <linux/of.h>\n+#include <linux/of_fdt.h>\n+#include <linux/spinlock.h>\n+#include <linux/slab.h>\n+#include <linux/proc_fs.h>\n+#include <linux/configfs.h>\n+#include <linux/types.h>\n+#include <linux/stat.h>\n+#include <linux/limits.h>\n+#include <linux/file.h>\n+#include <linux/vmalloc.h>\n+#include <linux/firmware.h>\n+#include <linux/sizes.h>\n+\n+#include \"of_private.h\"\n+\n+struct cfs_overlay_item {\n+\tstruct config_item\titem;\n+\n+\tchar\t\t\tpath[PATH_MAX];\n+\n+\tconst struct firmware\t*fw;\n+\tstruct device_node\t*overlay;\n+\tint\t\t\tov_id;\n+\n+\tvoid\t\t\t*dtbo;\n+\tint\t\t\tdtbo_size;\n+};\n+\n+static int create_overlay(struct cfs_overlay_item *overlay, void *blob)\n+{\n+\tint err;\n+\n+\t/* unflatten the tree */\n+\tof_fdt_unflatten_tree(blob, NULL, &overlay->overlay);\n+\tif (overlay->overlay == NULL) {\n+\t\tpr_err(\"%s: failed to unflatten tree\\n\", __func__);\n+\t\terr = -EINVAL;\n+\t\tgoto out_err;\n+\t}\n+\tpr_debug(\"%s: unflattened OK\\n\", __func__);\n+\n+\t/* mark it as detached */\n+\tof_node_set_flag(overlay->overlay, OF_DETACHED);\n+\n+\t/* perform resolution */\n+\terr = of_resolve_phandles(overlay->overlay);\n+\tif (err != 0) {\n+\t\tpr_err(\"%s: Failed to resolve tree\\n\", __func__);\n+\t\tgoto out_err;\n+\t}\n+\tpr_debug(\"%s: resolved OK\\n\", __func__);\n+\n+\terr = of_overlay_apply(overlay->overlay, &overlay->ov_id);\n+\tif (err < 0) {\n+\t\tpr_err(\"%s: Failed to create overlay (err=%d)\\n\",\n+\t\t\t\t__func__, err);\n+\t\tgoto out_err;\n+\t}\n+\n+out_err:\n+\treturn err;\n+}\n+\n+static inline struct cfs_overlay_item *to_cfs_overlay_item(\n+\t\tstruct config_item *item)\n+{\n+\treturn item ? container_of(item, struct cfs_overlay_item, item) : NULL;\n+}\n+\n+static ssize_t cfs_overlay_item_path_show(struct config_item *item,\n+\t\tchar *page)\n+{\n+\tstruct cfs_overlay_item *overlay = to_cfs_overlay_item(item);\n+\treturn sprintf(page, \"%s\\n\", overlay->path);\n+}\n+\n+static ssize_t cfs_overlay_item_path_store(struct config_item *item,\n+\t\tconst char *page, size_t count)\n+{\n+\tstruct cfs_overlay_item *overlay = to_cfs_overlay_item(item);\n+\tconst char *p = page;\n+\tchar *s;\n+\tint err;\n+\n+\t/* if it's set do not allow changes */\n+\tif (overlay->path[0] != '\\0' || overlay->dtbo_size > 0)\n+\t\treturn -EPERM;\n+\n+\t/* copy to path buffer (and make sure it's always zero terminated */\n+\tcount = snprintf(overlay->path, sizeof(overlay->path) - 1, \"%s\", p);\n+\toverlay->path[sizeof(overlay->path) - 1] = '\\0';\n+\n+\t/* strip trailing newlines */\n+\ts = overlay->path + strlen(overlay->path);\n+\twhile (s > overlay->path && *--s == '\\n')\n+\t\t*s = '\\0';\n+\n+\tpr_debug(\"%s: path is '%s'\\n\", __func__, overlay->path);\n+\n+\terr = request_firmware(&overlay->fw, overlay->path, NULL);\n+\tif (err != 0)\n+\t\tgoto out_err;\n+\n+\terr = create_overlay(overlay, (void *)overlay->fw->data);\n+\tif (err != 0)\n+\t\tgoto out_err;\n+\n+\treturn count;\n+\n+out_err:\n+\n+\trelease_firmware(overlay->fw);\n+\toverlay->fw = NULL;\n+\n+\toverlay->path[0] = '\\0';\n+\treturn err;\n+}\n+\n+static ssize_t cfs_overlay_item_status_show(struct config_item *item,\n+\t\tchar *page)\n+{\n+\tstruct cfs_overlay_item *overlay = to_cfs_overlay_item(item);\n+\n+\treturn sprintf(page, \"%s\\n\",\n+\t\t\toverlay->ov_id >= 0 ? \"applied\" : \"unapplied\");\n+}\n+\n+CONFIGFS_ATTR(cfs_overlay_item_, path);\n+CONFIGFS_ATTR_RO(cfs_overlay_item_, status);\n+\n+static struct configfs_attribute *cfs_overlay_attrs[] = {\n+\t&cfs_overlay_item_attr_path,\n+\t&cfs_overlay_item_attr_status,\n+\tNULL,\n+};\n+\n+ssize_t cfs_overlay_item_dtbo_read(struct config_item *item,\n+\t\tvoid *buf, size_t max_count)\n+{\n+\tstruct cfs_overlay_item *overlay = to_cfs_overlay_item(item);\n+\n+\tpr_debug(\"%s: buf=%p max_count=%zu\\n\", __func__,\n+\t\t\tbuf, max_count);\n+\n+\tif (overlay->dtbo == NULL)\n+\t\treturn 0;\n+\n+\t/* copy if buffer provided */\n+\tif (buf != NULL) {\n+\t\t/* the buffer must be large enough */\n+\t\tif (overlay->dtbo_size > max_count)\n+\t\t\treturn -ENOSPC;\n+\n+\t\tmemcpy(buf, overlay->dtbo, overlay->dtbo_size);\n+\t}\n+\n+\treturn overlay->dtbo_size;\n+}\n+\n+ssize_t cfs_overlay_item_dtbo_write(struct config_item *item,\n+\t\tconst void *buf, size_t count)\n+{\n+\tstruct cfs_overlay_item *overlay = to_cfs_overlay_item(item);\n+\tint err;\n+\n+\t/* if it's set do not allow changes */\n+\tif (overlay->path[0] != '\\0' || overlay->dtbo_size > 0)\n+\t\treturn -EPERM;\n+\n+\t/* copy the contents */\n+\toverlay->dtbo = kmemdup(buf, count, GFP_KERNEL);\n+\tif (overlay->dtbo == NULL)\n+\t\treturn -ENOMEM;\n+\n+\toverlay->dtbo_size = count;\n+\n+\terr = create_overlay(overlay, overlay->dtbo);\n+\tif (err != 0)\n+\t\tgoto out_err;\n+\n+\treturn count;\n+\n+out_err:\n+\tkfree(overlay->dtbo);\n+\toverlay->dtbo = NULL;\n+\toverlay->dtbo_size = 0;\n+\n+\treturn err;\n+}\n+\n+CONFIGFS_BIN_ATTR(cfs_overlay_item_, dtbo, NULL, SZ_1M);\n+\n+static struct configfs_bin_attribute *cfs_overlay_bin_attrs[] = {\n+\t&cfs_overlay_item_attr_dtbo,\n+\tNULL,\n+};\n+\n+static void cfs_overlay_release(struct config_item *item)\n+{\n+\tstruct cfs_overlay_item *overlay = to_cfs_overlay_item(item);\n+\n+\tif (overlay->ov_id >= 0)\n+\t\tof_overlay_remove(&overlay->ov_id);\n+\tif (overlay->fw)\n+\t\trelease_firmware(overlay->fw);\n+\t/* kfree with NULL is safe */\n+\tkfree(overlay->dtbo);\n+\tkfree(overlay);\n+}\n+\n+static struct configfs_item_operations cfs_overlay_item_ops = {\n+\t.release\t= cfs_overlay_release,\n+};\n+\n+static struct config_item_type cfs_overlay_type = {\n+\t.ct_item_ops\t= &cfs_overlay_item_ops,\n+\t.ct_attrs\t= cfs_overlay_attrs,\n+\t.ct_bin_attrs\t= cfs_overlay_bin_attrs,\n+\t.ct_owner\t= THIS_MODULE,\n+};\n+\n+static struct config_item *cfs_overlay_group_make_item(\n+\t\tstruct config_group *group, const char *name)\n+{\n+\tstruct cfs_overlay_item *overlay;\n+\n+\toverlay = kzalloc(sizeof(*overlay), GFP_KERNEL);\n+\tif (!overlay)\n+\t\treturn ERR_PTR(-ENOMEM);\n+\toverlay->ov_id = -1;\n+\n+\tconfig_item_init_type_name(&overlay->item, name, &cfs_overlay_type);\n+\treturn &overlay->item;\n+}\n+\n+static void cfs_overlay_group_drop_item(struct config_group *group,\n+\t\tstruct config_item *item)\n+{\n+\tstruct cfs_overlay_item *overlay = to_cfs_overlay_item(item);\n+\n+\tconfig_item_put(&overlay->item);\n+}\n+\n+static struct configfs_group_operations overlays_ops = {\n+\t.make_item\t= cfs_overlay_group_make_item,\n+\t.drop_item\t= cfs_overlay_group_drop_item,\n+};\n+\n+static struct config_item_type overlays_type = {\n+\t.ct_group_ops   = &overlays_ops,\n+\t.ct_owner       = THIS_MODULE,\n+};\n+\n+static struct configfs_group_operations of_cfs_ops = {\n+\t/* empty - we don't allow anything to be created */\n+};\n+\n+static struct config_item_type of_cfs_type = {\n+\t.ct_group_ops   = &of_cfs_ops,\n+\t.ct_owner       = THIS_MODULE,\n+};\n+\n+struct config_group of_cfs_overlay_group;\n+\n+static struct configfs_subsystem of_cfs_subsys = {\n+\t.su_group = {\n+\t\t.cg_item = {\n+\t\t\t.ci_namebuf = \"device-tree\",\n+\t\t\t.ci_type = &of_cfs_type,\n+\t\t},\n+\t},\n+\t.su_mutex = __MUTEX_INITIALIZER(of_cfs_subsys.su_mutex),\n+};\n+\n+static int __init of_cfs_init(void)\n+{\n+\tint ret;\n+\n+\tpr_info(\"%s\\n\", __func__);\n+\n+\tconfig_group_init(&of_cfs_subsys.su_group);\n+\tconfig_group_init_type_name(&of_cfs_overlay_group, \"overlays\",\n+\t\t\t&overlays_type);\n+\tconfigfs_add_default_group(&of_cfs_overlay_group,\n+\t\t\t&of_cfs_subsys.su_group);\n+\n+\tret = configfs_register_subsystem(&of_cfs_subsys);\n+\tif (ret != 0) {\n+\t\tpr_err(\"%s: failed to register subsys\\n\", __func__);\n+\t\tgoto out;\n+\t}\n+\tpr_info(\"%s: OK\\n\", __func__);\n+out:\n+\treturn ret;\n+}\n+late_initcall(of_cfs_init);\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0065-hci_h5-Don-t-send-conf_req-when-ACTIVE.patch",
    "content": "From 32fe7cc286f4a4d7f5d623ddb9fba10907c2abea Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.org>\nDate: Thu, 17 Dec 2015 13:37:07 +0000\nSubject: [PATCH] hci_h5: Don't send conf_req when ACTIVE\n\nWithout this patch, a modem and kernel can continuously bombard each\nother with conf_req and conf_rsp messages, in a demented game of tag.\n---\n drivers/bluetooth/hci_h5.c | 3 ++-\n 1 file changed, 2 insertions(+), 1 deletion(-)\n\n--- a/drivers/bluetooth/hci_h5.c\n+++ b/drivers/bluetooth/hci_h5.c\n@@ -343,7 +343,8 @@ static void h5_handle_internal_rx(struct\n \t\th5_link_control(hu, conf_req, 3);\n \t} else if (memcmp(data, conf_req, 2) == 0) {\n \t\th5_link_control(hu, conf_rsp, 2);\n-\t\th5_link_control(hu, conf_req, 3);\n+\t\tif (h5->state != H5_ACTIVE)\n+\t\t    h5_link_control(hu, conf_req, 3);\n \t} else if (memcmp(data, conf_rsp, 2) == 0) {\n \t\tif (H5_HDR_LEN(hdr) > 2)\n \t\t\th5->tx_win = (data[2] & 0x07);\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0066-ARM64-Round-Robin-dispatch-IRQs-between-CPUs.patch",
    "content": "From 443eb00795c4da76e3877ae7448697ba14584596 Mon Sep 17 00:00:00 2001\nFrom: Michael Zoran <mzoran@crowfest.net>\nDate: Sat, 14 Jan 2017 21:43:57 -0800\nSubject: [PATCH] ARM64: Round-Robin dispatch IRQs between CPUs.\n\nIRQ-CPU mapping is round robined on ARM64 to increase\nconcurrency and allow multiple interrupts to be serviced\nat a time.  This reduces the need for FIQ.\n\nSigned-off-by: Michael Zoran <mzoran@crowfest.net>\n---\n drivers/irqchip/irq-bcm2835.c | 15 ++++++++++++++-\n drivers/irqchip/irq-bcm2836.c | 21 +++++++++++++++++++++\n 2 files changed, 35 insertions(+), 1 deletion(-)\n\n--- a/drivers/irqchip/irq-bcm2835.c\n+++ b/drivers/irqchip/irq-bcm2835.c\n@@ -154,10 +154,23 @@ static void armctrl_unmask_irq(struct ir\n \t}\n }\n \n+#ifdef CONFIG_ARM64\n+void bcm2836_arm_irqchip_spin_gpu_irq(void);\n+\n+static void armctrl_ack_irq(struct irq_data *d)\n+{\n+\tbcm2836_arm_irqchip_spin_gpu_irq();\n+}\n+\n+#endif\n+\n static struct irq_chip armctrl_chip = {\n \t.name = \"ARMCTRL-level\",\n \t.irq_mask = armctrl_mask_irq,\n-\t.irq_unmask = armctrl_unmask_irq\n+\t.irq_unmask = armctrl_unmask_irq,\n+#ifdef CONFIG_ARM64\n+\t.irq_ack    = armctrl_ack_irq\n+#endif\n };\n \n static int armctrl_xlate(struct irq_domain *d, struct device_node *ctrlr,\n--- a/drivers/irqchip/irq-bcm2836.c\n+++ b/drivers/irqchip/irq-bcm2836.c\n@@ -87,6 +87,27 @@ static void bcm2836_arm_irqchip_unmask_g\n {\n }\n \n+#ifdef CONFIG_ARM64\n+\n+void bcm2836_arm_irqchip_spin_gpu_irq(void)\n+{\n+\tu32 i;\n+\tvoid __iomem *gpurouting = (intc.base + LOCAL_GPU_ROUTING);\n+\tu32 routing_val = readl(gpurouting);\n+\n+\tfor (i = 1; i <= 3; i++) {\n+\t\tu32 new_routing_val = (routing_val + i) & 3;\n+\n+\t\tif (cpu_active(new_routing_val)) {\n+\t\t\twritel(new_routing_val, gpurouting);\n+\t\t\treturn;\n+\t\t}\n+\t}\n+}\n+EXPORT_SYMBOL(bcm2836_arm_irqchip_spin_gpu_irq);\n+\n+#endif\n+\n static struct irq_chip bcm2836_arm_irqchip_gpu = {\n \t.name\t\t= \"bcm2836-gpu\",\n \t.irq_mask\t= bcm2836_arm_irqchip_mask_gpu_irq,\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0067-ARM64-Force-hardware-emulation-of-deprecated-instruc.patch",
    "content": "From b4e6e3b95c4f41b415d9d7fed7f121a1850af042 Mon Sep 17 00:00:00 2001\nFrom: Michael Zoran <mzoran@crowfest.net>\nDate: Sat, 11 Feb 2017 01:18:31 -0800\nSubject: [PATCH] ARM64: Force hardware emulation of deprecated\n instructions.\n\n---\n arch/arm64/kernel/armv8_deprecated.c | 5 +++++\n 1 file changed, 5 insertions(+)\n\n--- a/arch/arm64/kernel/armv8_deprecated.c\n+++ b/arch/arm64/kernel/armv8_deprecated.c\n@@ -182,10 +182,15 @@ static void __init register_insn_emulati\n \n \tswitch (ops->status) {\n \tcase INSN_DEPRECATED:\n+#if 0\n \t\tinsn->current_mode = INSN_EMULATE;\n \t\t/* Disable the HW mode if it was turned on at early boot time */\n \t\trun_all_cpu_set_hw_mode(insn, false);\n+#else\n+\t\tinsn->current_mode = INSN_HW;\n+\t\trun_all_cpu_set_hw_mode(insn, true);\n \t\tinsn->max = INSN_HW;\n+#endif\n \t\tbreak;\n \tcase INSN_OBSOLETE:\n \t\tinsn->current_mode = INSN_UNDEF;\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0068-cache-export-clean-and-invalidate.patch",
    "content": "From c9cb22efe558ee7fb1f30deb19dfe7b7bfe1f369 Mon Sep 17 00:00:00 2001\nFrom: popcornmix <popcornmix@gmail.com>\nDate: Fri, 25 Aug 2017 19:18:13 +0100\nSubject: [PATCH] cache: export clean and invalidate\n\nhack: cache: Fix linker error\n---\n arch/arm/mm/cache-v6.S | 4 ++--\n arch/arm/mm/cache-v7.S | 6 ++++--\n 2 files changed, 6 insertions(+), 4 deletions(-)\n\n--- a/arch/arm/mm/cache-v6.S\n+++ b/arch/arm/mm/cache-v6.S\n@@ -198,7 +198,7 @@ ENTRY(v6_flush_kern_dcache_area)\n  *\t- start   - virtual start address of region\n  *\t- end     - virtual end address of region\n  */\n-v6_dma_inv_range:\n+ENTRY(v6_dma_inv_range)\n #ifdef CONFIG_DMA_CACHE_RWFO\n \tldrb\tr2, [r0]\t\t\t@ read for ownership\n \tstrb\tr2, [r0]\t\t\t@ write for ownership\n@@ -243,7 +243,7 @@ v6_dma_inv_range:\n  *\t- start   - virtual start address of region\n  *\t- end     - virtual end address of region\n  */\n-v6_dma_clean_range:\n+ENTRY(v6_dma_clean_range)\n \tbic\tr0, r0, #D_CACHE_LINE_SIZE - 1\n 1:\n #ifdef CONFIG_DMA_CACHE_RWFO\n--- a/arch/arm/mm/cache-v7.S\n+++ b/arch/arm/mm/cache-v7.S\n@@ -363,7 +363,8 @@ ENDPROC(v7_flush_kern_dcache_area)\n  *\t- start   - virtual start address of region\n  *\t- end     - virtual end address of region\n  */\n-v7_dma_inv_range:\n+ENTRY(b15_dma_inv_range)\n+ENTRY(v7_dma_inv_range)\n \tdcache_line_size r2, r3\n \tsub\tr3, r2, #1\n \ttst\tr0, r3\n@@ -393,7 +394,8 @@ ENDPROC(v7_dma_inv_range)\n  *\t- start   - virtual start address of region\n  *\t- end     - virtual end address of region\n  */\n-v7_dma_clean_range:\n+ENTRY(b15_dma_clean_range)\n+ENTRY(v7_dma_clean_range)\n \tdcache_line_size r2, r3\n \tsub\tr3, r2, #1\n \tbic\tr0, r0, r3\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0069-AXI-performance-monitor-driver-2222.patch",
    "content": "From d9151380fdab4a0f2abcc08d2c344b0eabe48ab9 Mon Sep 17 00:00:00 2001\nFrom: James Hughes <JamesH65@users.noreply.github.com>\nDate: Tue, 14 Nov 2017 15:13:15 +0000\nSubject: [PATCH] AXI performance monitor driver (#2222)\n\nUses the debugfs I/F to provide access to the AXI\nbus performance monitors.\n\nRequires the new mailbox peripheral access for access\nto the VPU performance registers, system bus access\nis done using direct register reads.\n\nSigned-off-by: James Hughes <james.hughes@raspberrypi.org>\n\nraspberrypi_axi_monitor: suppress warning\n\nSuppress the following warning by casting the pointer to and uintptr_t\nbefore to u32:\n\nSigned-off-by: Matteo Croce <mcroce@redhat.com>\n---\n drivers/perf/Kconfig                   |   8 +\n drivers/perf/Makefile                  |   1 +\n drivers/perf/raspberrypi_axi_monitor.c | 637 +++++++++++++++++++++++++\n 3 files changed, 646 insertions(+)\n create mode 100644 drivers/perf/raspberrypi_axi_monitor.c\n\n--- a/drivers/perf/Kconfig\n+++ b/drivers/perf/Kconfig\n@@ -130,6 +130,14 @@ config ARM_SPE_PMU\n \t  Extension, which provides periodic sampling of operations in\n \t  the CPU pipeline and reports this via the perf AUX interface.\n \n+config RPI_AXIPERF\n+        depends on ARCH_BCM2835\n+        tristate \"RaspberryPi AXI Performance monitors\"\n+        default n\n+        help\n+          Say y if you want to use Raspberry Pi AXI performance monitors, m if\n+          you want to build it as a module.\n+\n source \"drivers/perf/hisilicon/Kconfig\"\n \n endmenu\n--- a/drivers/perf/Makefile\n+++ b/drivers/perf/Makefile\n@@ -13,3 +13,4 @@ obj-$(CONFIG_QCOM_L3_PMU) += qcom_l3_pmu\n obj-$(CONFIG_THUNDERX2_PMU) += thunderx2_pmu.o\n obj-$(CONFIG_XGENE_PMU) += xgene_pmu.o\n obj-$(CONFIG_ARM_SPE_PMU) += arm_spe_pmu.o\n+obj-$(CONFIG_RPI_AXIPERF) += raspberrypi_axi_monitor.o\n--- /dev/null\n+++ b/drivers/perf/raspberrypi_axi_monitor.c\n@@ -0,0 +1,637 @@\n+/*\n+ * raspberrypi_axi_monitor.c\n+ *\n+ * Author: james.hughes@raspberrypi.org\n+ *\n+ * Raspberry Pi AXI performance counters.\n+ *\n+ * Copyright (C) 2017 Raspberry Pi Trading Ltd.\n+ *\n+ * This program is free software; you can redistribute it and/or modify\n+ * it under the terms of the GNU General Public License version 2 as\n+ * published by the Free Software Foundation.\n+ */\n+\n+#include <linux/debugfs.h>\n+#include <linux/devcoredump.h>\n+#include <linux/device.h>\n+#include <linux/kthread.h>\n+#include <linux/module.h>\n+#include <linux/netdevice.h>\n+#include <linux/mutex.h>\n+#include <linux/of.h>\n+#include <linux/platform_device.h>\n+\n+#include <soc/bcm2835/raspberrypi-firmware.h>\n+\n+#define NUM_MONITORS 2\n+#define NUM_BUS_WATCHERS_PER_MONITOR 3\n+\n+#define SYSTEM_MONITOR 0\n+#define VPU_MONITOR 1\n+\n+#define MAX_BUSES 16\n+#define DEFAULT_SAMPLE_TIME 100\n+\n+#define NUM_BUS_WATCHER_RESULTS 9\n+\n+struct bus_watcher_data {\n+\tunion\t{\n+\t\tu32 results[NUM_BUS_WATCHER_RESULTS];\n+\t\tstruct {\n+\t\t\tu32 atrans;\n+\t\t\tu32 atwait;\n+\t\t\tu32 amax;\n+\t\t\tu32 wtrans;\n+\t\t\tu32 wtwait;\n+\t\t\tu32 wmax;\n+\t\t\tu32 rtrans;\n+\t\t\tu32 rtwait;\n+\t\t\tu32 rmax;\n+\t\t};\n+\t};\n+};\n+\n+\n+struct rpi_axiperf {\n+\tstruct platform_device *dev;\n+\tstruct dentry *root_folder;\n+\n+\tstruct task_struct *monitor_thread;\n+\tstruct mutex lock;\n+\n+\tstruct rpi_firmware *firmware;\n+\n+\t/* Sample time spent on for each bus */\n+\tint sample_time;\n+\n+\t/* Now storage for the per monitor settings and the resulting\n+\t * performance figures\n+\t */\n+\tstruct {\n+\t\t/* Bit field of buses we want to monitor */\n+\t\tint bus_enabled;\n+\t\t/* Bit field of buses to filter by */\n+\t\tint bus_filter;\n+\t\t/* The current buses being monitored on this monitor */\n+\t\tint current_bus[NUM_BUS_WATCHERS_PER_MONITOR];\n+\t\t/* The last bus monitored on this monitor */\n+\t\tint last_monitored;\n+\n+\t\t/* Set true if this mailbox must use the mailbox interface\n+\t\t * rather than access registers directly.\n+\t\t */\n+\t\tint use_mailbox_interface;\n+\n+\t\t/* Current result values */\n+\t\tstruct bus_watcher_data results[MAX_BUSES];\n+\n+\t\tstruct dentry *debugfs_entry;\n+\t\tvoid __iomem *base_address;\n+\n+\t}  monitor[NUM_MONITORS];\n+\n+};\n+\n+static struct rpi_axiperf *state;\n+\n+/* Two monitors, System and VPU, each with the following register sets.\n+ * Each monitor can only monitor one bus at a time, so we time share them,\n+ * giving each bus 100ms (default, settable via debugfs) of time on its\n+ * associated monitor\n+ * Record results from the three Bus watchers per monitor and push to the sysfs\n+ */\n+\n+/* general registers */\n+const int GEN_CTRL;\n+\n+const int GEN_CTL_ENABLE_BIT\t= BIT(0);\n+const int GEN_CTL_RESET_BIT\t= BIT(1);\n+\n+/* Bus watcher registers */\n+const int BW_PITCH\t\t= 0x40;\n+\n+const int BW0_CTRL\t\t= 0x40;\n+const int BW1_CTRL\t\t= 0x80;\n+const int BW2_CTRL\t\t= 0xc0;\n+\n+const int BW_ATRANS_OFFSET\t= 0x04;\n+const int BW_ATWAIT_OFFSET\t= 0x08;\n+const int BW_AMAX_OFFSET\t= 0x0c;\n+const int BW_WTRANS_OFFSET\t= 0x10;\n+const int BW_WTWAIT_OFFSET\t= 0x14;\n+const int BW_WMAX_OFFSET\t= 0x18;\n+const int BW_RTRANS_OFFSET\t= 0x1c;\n+const int BW_RTWAIT_OFFSET\t= 0x20;\n+const int BW_RMAX_OFFSET\t= 0x24;\n+\n+const int BW_CTRL_RESET_BIT\t= BIT(31);\n+const int BW_CTRL_ENABLE_BIT\t= BIT(30);\n+const int BW_CTRL_ENABLE_ID_FILTER_BIT\t= BIT(29);\n+const int BW_CTRL_LIMIT_HALT_BIT\t= BIT(28);\n+\n+const int BW_CTRL_SOURCE_SHIFT\t= 8;\n+const int BW_CTRL_SOURCE_MASK\t= GENMASK(12, 8); // 5 bits\n+const int BW_CTRL_BUS_WATCH_SHIFT;\n+const int BW_CTRL_BUS_WATCH_MASK = GENMASK(5, 0); // 6 bits\n+const int BW_CTRL_BUS_FILTER_SHIFT = 8;\n+\n+const static char *bus_filter_strings[] = {\n+\t\"\",\n+\t\"CORE0_V\",\n+\t\"ICACHE0\",\n+\t\"DCACHE0\",\n+\t\"CORE1_V\",\n+\t\"ICACHE1\",\n+\t\"DCACHE1\",\n+\t\"L2_MAIN\",\n+\t\"HOST_PORT\",\n+\t\"HOST_PORT2\",\n+\t\"HVS\",\n+\t\"ISP\",\n+\t\"VIDEO_DCT\",\n+\t\"VIDEO_SD2AXI\",\n+\t\"CAM0\",\n+\t\"CAM1\",\n+\t\"DMA0\",\n+\t\"DMA1\",\n+\t\"DMA2_VPU\",\n+\t\"JPEG\",\n+\t\"VIDEO_CME\",\n+\t\"TRANSPOSER\",\n+\t\"VIDEO_FME\",\n+\t\"CCP2TX\",\n+\t\"USB\",\n+\t\"V3D0\",\n+\t\"V3D1\",\n+\t\"V3D2\",\n+\t\"AVE\",\n+\t\"DEBUG\",\n+\t\"CPU\",\n+\t\"M30\"\n+};\n+\n+const int num_bus_filters = ARRAY_SIZE(bus_filter_strings);\n+\n+const static char *system_bus_string[] = {\n+\t\"DMA_L2\",\n+\t\"TRANS\",\n+\t\"JPEG\",\n+\t\"SYSTEM_UC\",\n+\t\"DMA_UC\",\n+\t\"SYSTEM_L2\",\n+\t\"CCP2TX\",\n+\t\"MPHI_RX\",\n+\t\"MPHI_TX\",\n+\t\"HVS\",\n+\t\"H264\",\n+\t\"ISP\",\n+\t\"V3D\",\n+\t\"PERIPHERAL\",\n+\t\"CPU_UC\",\n+\t\"CPU_L2\"\n+};\n+\n+const int num_system_buses = ARRAY_SIZE(system_bus_string);\n+\n+const static char *vpu_bus_string[] = {\n+\t\"VPU1_D_L2\",\n+\t\"VPU0_D_L2\",\n+\t\"VPU1_I_L2\",\n+\t\"VPU0_I_L2\",\n+\t\"SYSTEM_L2\",\n+\t\"L2_FLUSH\",\n+\t\"DMA_L2\",\n+\t\"VPU1_D_UC\",\n+\t\"VPU0_D_UC\",\n+\t\"VPU1_I_UC\",\n+\t\"VPU0_I_UC\",\n+\t\"SYSTEM_UC\",\n+\t\"L2_OUT\",\n+\t\"DMA_UC\",\n+\t\"SDRAM\",\n+\t\"L2_IN\"\n+};\n+\n+const int num_vpu_buses = ARRAY_SIZE(vpu_bus_string);\n+\n+const static char *monitor_name[] = {\n+\t\"System\",\n+\t\"VPU\"\n+};\n+\n+static inline void write_reg(int monitor, int reg, u32 value)\n+{\n+\twritel(value, state->monitor[monitor].base_address + reg);\n+}\n+\n+static inline u32 read_reg(int monitor, u32 reg)\n+{\n+\treturn readl(state->monitor[monitor].base_address + reg);\n+}\n+\n+static void read_bus_watcher(int monitor, int watcher, u32 *results)\n+{\n+\tif (state->monitor[monitor].use_mailbox_interface) {\n+\t\t/* We have 9 results, plus the overheads of start address and\n+\t\t * length So 11 u32 to define\n+\t\t */\n+\t\tu32 tmp[11];\n+\t\tint err;\n+\n+\t\ttmp[0] = (u32)(uintptr_t)(state->monitor[monitor].base_address + watcher\n+\t\t\t\t+ BW_ATRANS_OFFSET);\n+\t\ttmp[1] = NUM_BUS_WATCHER_RESULTS;\n+\n+\t\terr = rpi_firmware_property(state->firmware,\n+\t\t\t\t\t    RPI_FIRMWARE_GET_PERIPH_REG,\n+\t\t\t\t\t    tmp, sizeof(tmp));\n+\n+\t\tif (err < 0 || tmp[1] != NUM_BUS_WATCHER_RESULTS)\n+\t\t\tdev_err_once(&state->dev->dev,\n+\t\t\t\t     \"Failed to read bus watcher\");\n+\t\telse\n+\t\t\tmemcpy(results, &tmp[2],\n+\t\t\t       NUM_BUS_WATCHER_RESULTS * sizeof(u32));\n+\t} else {\n+\t\tint i;\n+\t\tvoid __iomem *addr = state->monitor[monitor].base_address\n+\t\t\t\t+ watcher + BW_ATRANS_OFFSET;\n+\t\tfor (i = 0; i < NUM_BUS_WATCHER_RESULTS; i++, addr += 4)\n+\t\t\t*results++ = readl(addr);\n+\t}\n+}\n+\n+static void set_monitor_control(int monitor, u32 set)\n+{\n+\tif (state->monitor[monitor].use_mailbox_interface) {\n+\t\tu32 tmp[3] = {(u32)(uintptr_t)(state->monitor[monitor].base_address +\n+\t\t\t\tGEN_CTRL), 1, set};\n+\t\tint err = rpi_firmware_property(state->firmware,\n+\t\t\t\t\t\tRPI_FIRMWARE_SET_PERIPH_REG,\n+\t\t\t\t\t\ttmp, sizeof(tmp));\n+\n+\t\tif (err < 0 || tmp[1] != 1)\n+\t\t\tdev_err_once(&state->dev->dev,\n+\t\t\t\t\"Failed to set monitor control\");\n+\t} else\n+\t\twrite_reg(monitor, GEN_CTRL, set);\n+}\n+\n+static void set_bus_watcher_control(int monitor, int watcher, u32 set)\n+{\n+\tif (state->monitor[monitor].use_mailbox_interface) {\n+\t\tu32 tmp[3] = {(u32)(uintptr_t)(state->monitor[monitor].base_address +\n+\t\t\t\t    watcher), 1, set};\n+\t\tint err = rpi_firmware_property(state->firmware,\n+\t\t\t\t\t\tRPI_FIRMWARE_SET_PERIPH_REG,\n+\t\t\t\t\t\ttmp, sizeof(tmp));\n+\t\tif (err < 0 || tmp[1] != 1)\n+\t\t\tdev_err_once(&state->dev->dev,\n+\t\t\t\t\"Failed to set bus watcher control\");\n+\t} else\n+\t\twrite_reg(monitor, watcher, set);\n+}\n+\n+static void monitor(struct rpi_axiperf *state)\n+{\n+\tint monitor, num_buses[NUM_MONITORS];\n+\n+\tmutex_lock(&state->lock);\n+\n+\tfor (monitor = 0; monitor < NUM_MONITORS; monitor++) {\n+\t\ttypeof(state->monitor[0]) *mon = &(state->monitor[monitor]);\n+\n+\t\t/* Anything enabled? */\n+\t\tif (mon->bus_enabled == 0) {\n+\t\t\t/* No, disable all monitoring for this monitor */\n+\t\t\tset_monitor_control(monitor, GEN_CTL_RESET_BIT);\n+\t\t} else {\n+\t\t\tint i;\n+\n+\t\t\t/* Find out how many busses we want to monitor, and\n+\t\t\t * spread our 3 actual monitors over them\n+\t\t\t */\n+\t\t\tnum_buses[monitor] = hweight32(mon->bus_enabled);\n+\t\t\tnum_buses[monitor] = min(num_buses[monitor],\n+\t\t\t\t\t\t NUM_BUS_WATCHERS_PER_MONITOR);\n+\n+\t\t\tfor (i = 0; i < num_buses[monitor]; i++) {\n+\t\t\t\tint bus_control;\n+\n+\t\t\t\tdo {\n+\t\t\t\t\tmon->last_monitored++;\n+\t\t\t\t\tmon->last_monitored &= 0xf;\n+\t\t\t\t} while ((mon->bus_enabled &\n+\t\t\t\t\t (1 << mon->last_monitored)) == 0);\n+\n+\t\t\t\tmon->current_bus[i] = mon->last_monitored;\n+\n+\t\t\t\t/* Reset the counters */\n+\t\t\t\tset_bus_watcher_control(monitor,\n+\t\t\t\t\t\t\tBW0_CTRL +\n+\t\t\t\t\t\t\ti*BW_PITCH,\n+\t\t\t\t\t\t\tBW_CTRL_RESET_BIT);\n+\n+\t\t\t\tbus_control = BW_CTRL_ENABLE_BIT |\n+\t\t\t\t\t\tmon->current_bus[i];\n+\n+\t\t\t\tif (mon->bus_filter) {\n+\t\t\t\t\tbus_control |=\n+\t\t\t\t\t\tBW_CTRL_ENABLE_ID_FILTER_BIT;\n+\t\t\t\t\tbus_control |=\n+\t\t\t\t\t\t((mon->bus_filter & 0x1f)\n+\t\t\t\t\t\t<< BW_CTRL_BUS_FILTER_SHIFT);\n+\t\t\t\t}\n+\n+\t\t\t\t// Start capture\n+\t\t\t\tset_bus_watcher_control(monitor,\n+\t\t\t\t\t\t\tBW0_CTRL + i*BW_PITCH,\n+\t\t\t\t\t\t\tbus_control);\n+\t\t\t}\n+\t\t}\n+\n+\t\t/* start monitoring */\n+\t\tset_monitor_control(monitor, GEN_CTL_ENABLE_BIT);\n+\t}\n+\n+\tmutex_unlock(&state->lock);\n+\n+\tmsleep(state->sample_time);\n+\n+\t/* Now read the results */\n+\n+\tmutex_lock(&state->lock);\n+\tfor (monitor = 0; monitor < NUM_MONITORS; monitor++) {\n+\t\ttypeof(state->monitor[0]) *mon = &(state->monitor[monitor]);\n+\n+\t\t/* Anything enabled? */\n+\t\tif (mon->bus_enabled == 0) {\n+\t\t\t/* No, disable all monitoring for this monitor */\n+\t\t\tset_monitor_control(monitor, 0);\n+\t\t} else {\n+\t\t\tint i;\n+\n+\t\t\tfor (i = 0; i < num_buses[monitor]; i++) {\n+\t\t\t\tint bus = mon->current_bus[i];\n+\n+\t\t\t\tread_bus_watcher(monitor,\n+\t\t\t\t\tBW0_CTRL + i*BW_PITCH,\n+\t\t\t\t\t(u32 *)&mon->results[bus].results);\n+\t\t\t}\n+\t\t}\n+\t}\n+\tmutex_unlock(&state->lock);\n+}\n+\n+static int monitor_thread(void *data)\n+{\n+\tstruct rpi_axiperf *state  = data;\n+\n+\twhile (1) {\n+\t\tmonitor(state);\n+\n+\t\tif (kthread_should_stop())\n+\t\t\treturn 0;\n+\t}\n+\treturn 0;\n+}\n+\n+static ssize_t myreader(struct file *fp, char __user *user_buffer,\n+\t\t\tsize_t count, loff_t *position)\n+{\n+#define INIT_BUFF_SIZE 2048\n+\n+\tint i;\n+\tint idx = (int)(uintptr_t)(fp->private_data);\n+\tint num_buses, cnt;\n+\tchar *string_buffer;\n+\tint buff_size = INIT_BUFF_SIZE;\n+\tchar *p;\n+\ttypeof(state->monitor[0]) *mon = &(state->monitor[idx]);\n+\n+\tif (idx < 0 || idx > NUM_MONITORS)\n+\t\tidx = 0;\n+\n+\tnum_buses = idx == SYSTEM_MONITOR ? num_system_buses : num_vpu_buses;\n+\n+\tstring_buffer = kmalloc(buff_size, GFP_KERNEL);\n+\n+\tif (!string_buffer) {\n+\t\tdev_err(&state->dev->dev,\n+\t\t\t\t\"Failed temporary string allocation\\n\");\n+\t\treturn 0;\n+\t}\n+\n+\tp = string_buffer;\n+\n+\tmutex_lock(&state->lock);\n+\n+\tif (mon->bus_filter) {\n+\t\tint filt = min(mon->bus_filter & 0x1f, num_bus_filters);\n+\n+\t\tcnt = snprintf(p, buff_size,\n+\t\t\t       \"\\nMonitoring transactions from %s only\\n\",\n+\t\t\t       bus_filter_strings[filt]);\n+\t\tp += cnt;\n+\t\tbuff_size -= cnt;\n+\t}\n+\n+\tcnt = snprintf(p, buff_size, \"     Bus   |    Atrans    Atwait      AMax    Wtrans    Wtwait      WMax    Rtrans    Rtwait      RMax\\n\"\n+\t\t\t\t     \"======================================================================================================\\n\");\n+\n+\tif (cnt >= buff_size)\n+\t\tgoto done;\n+\n+\tp += cnt;\n+\tbuff_size -= cnt;\n+\n+\tfor (i = 0; i < num_buses; i++) {\n+\t\tif (mon->bus_enabled & (1 << i)) {\n+#define DIVIDER (1024)\n+\t\t\ttypeof(mon->results[0]) *res = &(mon->results[i]);\n+\n+\t\t\tcnt = snprintf(p, buff_size,\n+\t\t\t\t\t\"%10s | %8uK %8uK %8uK %8uK %8uK %8uK %8uK %8uK %8uK\\n\",\n+\t\t\t\t\tidx == SYSTEM_MONITOR ?\n+\t\t\t\t\t\tsystem_bus_string[i] :\n+\t\t\t\t\t\tvpu_bus_string[i],\n+\t\t\t\t\tres->atrans/DIVIDER,\n+\t\t\t\t\tres->atwait/DIVIDER,\n+\t\t\t\t\tres->amax/DIVIDER,\n+\t\t\t\t\tres->wtrans/DIVIDER,\n+\t\t\t\t\tres->wtwait/DIVIDER,\n+\t\t\t\t\tres->wmax/DIVIDER,\n+\t\t\t\t\tres->rtrans/DIVIDER,\n+\t\t\t\t\tres->rtwait/DIVIDER,\n+\t\t\t\t\tres->rmax/DIVIDER\n+\t\t\t\t\t);\n+\t\t\tif (cnt >= buff_size)\n+\t\t\t\tgoto done;\n+\n+\t\t\tp += cnt;\n+\t\t\tbuff_size -= cnt;\n+\t\t}\n+\t}\n+\n+\tmutex_unlock(&state->lock);\n+\n+done:\n+\n+\t/* did the last string entry exceeed our buffer size? ie out of string\n+\t * buffer space. Null terminate, use what we have.\n+\t */\n+\tif (cnt >= buff_size) {\n+\t\tbuff_size = 0;\n+\t\tstring_buffer[INIT_BUFF_SIZE] = 0;\n+\t}\n+\n+\tcnt = simple_read_from_buffer(user_buffer, count, position,\n+\t\t\t\t      string_buffer,\n+\t\t\t\t      INIT_BUFF_SIZE - buff_size);\n+\n+\tkfree(string_buffer);\n+\n+\treturn cnt;\n+}\n+\n+static ssize_t mywriter(struct file *fp, const char __user *user_buffer,\n+\t\t\tsize_t count, loff_t *position)\n+{\n+\tint idx = (int)(uintptr_t)(fp->private_data);\n+\n+\tif (idx < 0 || idx > NUM_MONITORS)\n+\t\tidx = 0;\n+\n+\t/* At the moment, this does nothing, but in the future it could be\n+\t * used to reset counters etc\n+\t */\n+\treturn count;\n+}\n+\n+static const struct file_operations fops_debug = {\n+\t.read = myreader,\n+\t.write = mywriter,\n+\t.open = simple_open\n+};\n+\n+static int rpi_axiperf_probe(struct platform_device *pdev)\n+{\n+\tint ret = 0, i;\n+\tstruct device *dev = &pdev->dev;\n+\tstruct device_node *np = dev->of_node;\n+\tstruct device_node *fw_node;\n+\n+\tstate = kzalloc(sizeof(struct rpi_axiperf), GFP_KERNEL);\n+\tif (!state)\n+\t\treturn -ENOMEM;\n+\n+\t/* Get the firmware handle for future rpi-firmware-xxx calls */\n+\tfw_node = of_parse_phandle(np, \"firmware\", 0);\n+\tif (!fw_node) {\n+\t\tdev_err(dev, \"Missing firmware node\\n\");\n+\t\treturn -ENOENT;\n+\t}\n+\n+\tstate->firmware = rpi_firmware_get(fw_node);\n+\tif (!state->firmware)\n+\t\treturn -EPROBE_DEFER;\n+\n+\t/* Special case for the VPU monitor, we must use the mailbox interface\n+\t * as it is not accessible from the ARM address space.\n+\t */\n+\tstate->monitor[VPU_MONITOR].use_mailbox_interface = 1;\n+\tstate->monitor[SYSTEM_MONITOR].use_mailbox_interface = 0;\n+\n+\tfor (i = 0; i < NUM_MONITORS; i++) {\n+\t\tif (state->monitor[i].use_mailbox_interface) {\n+\t\t\t of_property_read_u32_index(np, \"reg\", i*2,\n+\t\t\t\t(u32 *)(&state->monitor[i].base_address));\n+\t\t} else {\n+\t\t\tstruct resource *resource =\n+\t\t\t\tplatform_get_resource(pdev, IORESOURCE_MEM, i);\n+\n+\t\t\tstate->monitor[i].base_address =\n+\t\t\t\tdevm_ioremap_resource(&pdev->dev, resource);\n+\t\t}\n+\n+\t\tif (IS_ERR(state->monitor[i].base_address))\n+\t\t\treturn PTR_ERR(state->monitor[i].base_address);\n+\n+\t\t/* Enable all buses by default */\n+\t\tstate->monitor[i].bus_enabled = 0xffff;\n+\t}\n+\n+\tstate->dev = pdev;\n+\tplatform_set_drvdata(pdev, state);\n+\n+\tstate->sample_time = DEFAULT_SAMPLE_TIME;\n+\n+\t/* Set up all the debugfs stuff */\n+\tstate->root_folder = debugfs_create_dir(KBUILD_MODNAME, NULL);\n+\n+\tfor (i = 0; i < NUM_MONITORS; i++) {\n+\t\tstate->monitor[i].debugfs_entry =\n+\t\t\tdebugfs_create_dir(monitor_name[i], state->root_folder);\n+\t\tif (IS_ERR(state->monitor[i].debugfs_entry))\n+\t\t\tstate->monitor[i].debugfs_entry = NULL;\n+\n+\t\tdebugfs_create_file(\"data\", 0444,\n+\t\t\t\t    state->monitor[i].debugfs_entry,\n+\t\t\t\t    (void *)(uintptr_t)i, &fops_debug);\n+\t\tdebugfs_create_u32(\"enable\", 0644,\n+\t\t\t\t   state->monitor[i].debugfs_entry,\n+\t\t\t\t   &state->monitor[i].bus_enabled);\n+\t\tdebugfs_create_u32(\"filter\", 0644,\n+\t\t\t\t   state->monitor[i].debugfs_entry,\n+\t\t\t\t   &state->monitor[i].bus_filter);\n+\t\tdebugfs_create_u32(\"sample_time\", 0644,\n+\t\t\t\t   state->monitor[i].debugfs_entry,\n+\t\t\t\t   &state->sample_time);\n+\t}\n+\n+\tmutex_init(&state->lock);\n+\n+\tstate->monitor_thread = kthread_run(monitor_thread, state,\n+\t\t\t\t\t    \"rpi-axiperfmon\");\n+\n+\treturn ret;\n+\n+}\n+\n+static int rpi_axiperf_remove(struct platform_device *dev)\n+{\n+\tint ret = 0;\n+\n+\tkthread_stop(state->monitor_thread);\n+\n+\tdebugfs_remove_recursive(state->root_folder);\n+\tstate->root_folder = NULL;\n+\n+\treturn ret;\n+}\n+\n+static const struct of_device_id rpi_axiperf_match[] = {\n+\t{\n+\t\t.compatible = \"brcm,bcm2835-axiperf\",\n+\t},\n+\t{},\n+};\n+MODULE_DEVICE_TABLE(of, rpi_axiperf_match);\n+\n+static struct platform_driver rpi_axiperf_driver  = {\n+\t.probe =\trpi_axiperf_probe,\n+\t.remove =\trpi_axiperf_remove,\n+\t.driver = {\n+\t\t.name   = \"rpi-bcm2835-axiperf\",\n+\t\t.of_match_table = of_match_ptr(rpi_axiperf_match),\n+\t},\n+};\n+\n+module_platform_driver(rpi_axiperf_driver);\n+\n+/* Module information */\n+MODULE_AUTHOR(\"James Hughes <james.hughes@raspberrypi.org>\");\n+MODULE_DESCRIPTION(\"RPI AXI Performance monitor driver\");\n+MODULE_LICENSE(\"GPL\");\n+\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0070-ARM-bcm2835-Set-Serial-number-and-Revision.patch",
    "content": "From 65565784e5faad0af487d54f3f92d9d4c9c38e4a Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Noralf=20Tr=C3=B8nnes?= <noralf@tronnes.org>\nDate: Wed, 3 Jun 2015 12:26:13 +0200\nSubject: [PATCH] ARM: bcm2835: Set Serial number and Revision\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nThe VideoCore bootloader passes in Serial number and\nRevision number through Device Tree. Make these available to\nuserspace through /proc/cpuinfo.\n\nMainline status:\n\nThere is a commit in linux-next that standardize passing the serial\nnumber through Device Tree (string: /serial-number):\nARM: 8355/1: arch: Show the serial number from devicetree in cpuinfo\n\nThere was an attempt to do the same with the revision number, but it\ndidn't get in:\n[PATCH v2 1/2] arm: devtree: Set system_rev from DT revision\n\nSigned-off-by: Noralf Trønnes <noralf@tronnes.org>\n---\n arch/arm/mach-bcm/board_bcm2835.c | 14 ++++++++++++++\n 1 file changed, 14 insertions(+)\n\n--- a/arch/arm/mach-bcm/board_bcm2835.c\n+++ b/arch/arm/mach-bcm/board_bcm2835.c\n@@ -6,12 +6,25 @@\n #include <linux/init.h>\n #include <linux/irqchip.h>\n #include <linux/of_address.h>\n+#include <asm/system_info.h>\n \n #include <asm/mach/arch.h>\n #include <asm/mach/map.h>\n \n #include \"platsmp.h\"\n \n+static void __init bcm2835_init(void)\n+{\n+\tstruct device_node *np = of_find_node_by_path(\"/system\");\n+\tu32 val;\n+\tu64 val64;\n+\n+\tif (!of_property_read_u32(np, \"linux,revision\", &val))\n+\t\tsystem_rev = val;\n+\tif (!of_property_read_u64(np, \"linux,serial\", &val64))\n+\t\tsystem_serial_low = val64;\n+}\n+\n static const char * const bcm2835_compat[] = {\n #ifdef CONFIG_ARCH_MULTI_V6\n \t\"brcm,bcm2835\",\n@@ -24,6 +37,7 @@ static const char * const bcm2835_compat\n };\n \n DT_MACHINE_START(BCM2835, \"BCM2835\")\n+\t.init_machine = bcm2835_init,\n \t.dt_compat = bcm2835_compat,\n \t.smp = smp_ops(bcm2836_smp_ops),\n MACHINE_END\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0071-dwc-otg-FIQ-Fix-bad-mode-in-data-abort-handler.patch",
    "content": "From 347167bd9ac2a68870064edd921f2525bd569c6d Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.org>\nDate: Mon, 16 Jul 2018 14:40:13 +0100\nSubject: [PATCH] dwc-otg: FIQ: Fix \"bad mode in data abort handler\"\n\nCreate a semi-static mapping for the USB registers early in the boot\nprocess, before additional kernel threads are started, so all threads\nwill have the mappings from the start. This avoids the need for\ndata aborts to lazily update them.\n\nSee: https://github.com/raspberrypi/linux/issues/2450\n\nSigned-off-by: Floris Bos <bos@je-eigen-domein.nl>\n---\n arch/arm/mach-bcm/board_bcm2835.c | 69 +++++++++++++++++++++++++++++++\n 1 file changed, 69 insertions(+)\n\n--- a/arch/arm/mach-bcm/board_bcm2835.c\n+++ b/arch/arm/mach-bcm/board_bcm2835.c\n@@ -6,6 +6,7 @@\n #include <linux/init.h>\n #include <linux/irqchip.h>\n #include <linux/of_address.h>\n+#include <linux/of_fdt.h>\n #include <asm/system_info.h>\n \n #include <asm/mach/arch.h>\n@@ -13,6 +14,9 @@\n \n #include \"platsmp.h\"\n \n+#define BCM2835_USB_VIRT_BASE   0xf0980000\n+#define BCM2835_USB_VIRT_MPHI   0xf0006000\n+\n static void __init bcm2835_init(void)\n {\n \tstruct device_node *np = of_find_node_by_path(\"/system\");\n@@ -25,6 +29,70 @@ static void __init bcm2835_init(void)\n \t\tsystem_serial_low = val64;\n }\n \n+/*\n+ * We need to map registers that are going to be accessed by the FIQ\n+ * very early, before any kernel threads are spawned. Because if done\n+ * later, the mapping tables are not updated instantly but lazily upon\n+ * first access through a data abort handler. While that is fine\n+ * when executing regular kernel code, if the first access in a specific\n+ * thread happens while running FIQ code this will result in a panic.\n+ *\n+ * For more background see the following old mailing list thread:\n+ * https://www.spinics.net/lists/arm-kernel/msg325250.html\n+ */\n+static int __init bcm2835_map_usb(unsigned long node, const char *uname,\n+\t\t\t\t\tint depth, void *data)\n+{\n+\tstruct map_desc map[2];\n+\tconst __be32 *reg;\n+\tint len;\n+\tunsigned long p2b_offset = *((unsigned long *) data);\n+\n+\tif (!of_flat_dt_is_compatible(node, \"brcm,bcm2708-usb\"))\n+\t\treturn 0;\n+\treg = of_get_flat_dt_prop(node, \"reg\", &len);\n+\tif (!reg || len != (sizeof(unsigned long) * 4))\n+\t\treturn 0;\n+\n+\t/* Use information about the physical addresses of the\n+\t * registers from the device tree, but use legacy\n+\t * iotable_init() static mapping function to map them,\n+\t * as ioremap() is not functional at this stage in boot.\n+\t */\n+\tmap[0].virtual = (unsigned long) BCM2835_USB_VIRT_BASE;\n+\tmap[0].pfn = __phys_to_pfn(be32_to_cpu(reg[0]) - p2b_offset);\n+\tmap[0].length = be32_to_cpu(reg[1]);\n+\tmap[0].type = MT_DEVICE;\n+\tmap[1].virtual = (unsigned long) BCM2835_USB_VIRT_MPHI;\n+\tmap[1].pfn = __phys_to_pfn(be32_to_cpu(reg[2]) - p2b_offset);\n+\tmap[1].length = be32_to_cpu(reg[3]);\n+\tmap[1].type = MT_DEVICE;\n+\t\tiotable_init(map, 2);\n+\n+\treturn 1;\n+}\n+\n+static void __init bcm2835_map_io(void)\n+{\n+\tconst __be32 *ranges;\n+\tint soc, len;\n+\tunsigned long p2b_offset;\n+\n+\tdebug_ll_io_init();\n+\n+\t/* Find out how to map bus to physical address first from soc/ranges */\n+\tsoc = of_get_flat_dt_subnode_by_name(of_get_flat_dt_root(), \"soc\");\n+\tif (soc < 0)\n+\t\treturn;\n+\tranges = of_get_flat_dt_prop(soc, \"ranges\", &len);\n+\tif (!ranges || len < (sizeof(unsigned long) * 3))\n+\t\treturn;\n+\tp2b_offset = be32_to_cpu(ranges[0]) - be32_to_cpu(ranges[1]);\n+\n+\t/* Now search for bcm2708-usb node in device tree */\n+\tof_scan_flat_dt(bcm2835_map_usb, &p2b_offset);\n+}\n+\n static const char * const bcm2835_compat[] = {\n #ifdef CONFIG_ARCH_MULTI_V6\n \t\"brcm,bcm2835\",\n@@ -37,6 +105,7 @@ static const char * const bcm2835_compat\n };\n \n DT_MACHINE_START(BCM2835, \"BCM2835\")\n+\t.map_io = bcm2835_map_io,\n \t.init_machine = bcm2835_init,\n \t.dt_compat = bcm2835_compat,\n \t.smp = smp_ops(bcm2836_smp_ops),\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0072-ARM-Activate-FIQs-to-avoid-__irq_startup-warnings.patch",
    "content": "From 594abebdffdcff606bc445f2661d9a504f180136 Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.org>\nDate: Mon, 11 Dec 2017 09:18:32 +0000\nSubject: [PATCH] ARM: Activate FIQs to avoid __irq_startup warnings\n\nThere is a new test in __irq_startup that the IRQ is activated, which\nhasn't been the case for FIQs since they bypass some of the usual setup.\n\nAugment enable_fiq to include a call to irq_activate to avoid the\nwarning.\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.org>\n---\n arch/arm/kernel/fiq.c | 4 ++++\n 1 file changed, 4 insertions(+)\n\n--- a/arch/arm/kernel/fiq.c\n+++ b/arch/arm/kernel/fiq.c\n@@ -56,6 +56,8 @@\n static unsigned long dfl_fiq_insn;\n static struct pt_regs dfl_fiq_regs;\n \n+extern int irq_activate(struct irq_desc *desc);\n+\n /* Default reacquire function\n  * - we always relinquish FIQ control\n  * - we always reacquire FIQ control\n@@ -140,6 +142,8 @@ static int fiq_start;\n \n void enable_fiq(int fiq)\n {\n+\tstruct irq_desc *desc = irq_to_desc(fiq + fiq_start);\n+\tirq_activate(desc);\n \tenable_irq(fiq + fiq_start);\n }\n \n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0073-raspberrypi-firmware-Export-the-general-transaction-.patch",
    "content": "From 9cf689eda644ccba0c80982cbd821c9163f5de39 Mon Sep 17 00:00:00 2001\nFrom: Eric Anholt <eric@anholt.net>\nDate: Wed, 14 Sep 2016 09:16:19 +0100\nSubject: [PATCH] raspberrypi-firmware: Export the general transaction\n function.\n\nThe vc4-firmware-kms module is going to be doing the MBOX FB call.\n\nSigned-off-by: Eric Anholt <eric@anholt.net>\n---\n drivers/firmware/raspberrypi.c | 3 ++-\n 1 file changed, 2 insertions(+), 1 deletion(-)\n\n--- a/drivers/firmware/raspberrypi.c\n+++ b/drivers/firmware/raspberrypi.c\n@@ -46,7 +46,7 @@ static void response_callback(struct mbo\n  * Sends a request to the firmware through the BCM2835 mailbox driver,\n  * and synchronously waits for the reply.\n  */\n-static int\n+int\n rpi_firmware_transaction(struct rpi_firmware *fw, u32 chan, u32 data)\n {\n \tu32 message = MBOX_MSG(chan, data);\n@@ -71,6 +71,7 @@ rpi_firmware_transaction(struct rpi_firm\n \n \treturn ret;\n }\n+EXPORT_SYMBOL_GPL(rpi_firmware_transaction);\n \n /**\n  * rpi_firmware_property_list - Submit firmware property list\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0074-i2c-gpio-Also-set-bus-numbers-from-reg-property.patch",
    "content": "From 798407c217fee8f4869bf76d9cd2cda16f93e24f Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.org>\nDate: Tue, 20 Feb 2018 10:07:27 +0000\nSubject: [PATCH] i2c-gpio: Also set bus numbers from reg property\n\nI2C busses can be assigned specific bus numbers using aliases in\nDevice Tree - string properties where the name is the alias and the\nvalue is the path to the node. The current DT parameter mechanism\ndoes not allow property names to be derived from a parameter value\nin any way, so it isn't possible to generate unique or matching\naliases for nodes from an overlay that can generate multiple\ninstances, e.g. i2c-gpio.\n\nWork around this limitation (at least temporarily) by allowing\nthe i2c adapter number to be initialised from the \"reg\" property\nif present.\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.org>\n---\n drivers/i2c/busses/i2c-gpio.c | 4 +++-\n 1 file changed, 3 insertions(+), 1 deletion(-)\n\n--- a/drivers/i2c/busses/i2c-gpio.c\n+++ b/drivers/i2c/busses/i2c-gpio.c\n@@ -445,7 +445,9 @@ static int i2c_gpio_probe(struct platfor\n \tadap->dev.parent = dev;\n \tadap->dev.of_node = np;\n \n-\tadap->nr = pdev->id;\n+\tif (pdev->id != PLATFORM_DEVID_NONE || !pdev->dev.of_node ||\n+\t    of_property_read_u32(pdev->dev.of_node, \"reg\", &adap->nr))\n+\t\tadap->nr = pdev->id;\n \tret = i2c_bit_add_numbered_bus(adap);\n \tif (ret)\n \t\treturn ret;\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0075-added-capture_clear-option-to-pps-gpio-via-dtoverlay.patch",
    "content": "From 781bfd769e192aa39ef93fa37c812af444a9cf93 Mon Sep 17 00:00:00 2001\nFrom: hdoverobinson <hdoverobinson@gmail.com>\nDate: Tue, 13 Mar 2018 06:58:39 -0400\nSubject: [PATCH] added capture_clear option to pps-gpio via dtoverlay\n (#2433)\n\n---\n drivers/pps/clients/pps-gpio.c | 2 ++\n 1 file changed, 2 insertions(+)\n\n--- a/drivers/pps/clients/pps-gpio.c\n+++ b/drivers/pps/clients/pps-gpio.c\n@@ -145,6 +145,8 @@ static int pps_gpio_setup(struct platfor\n \n \tif (of_property_read_bool(np, \"assert-falling-edge\"))\n \t\tdata->assert_falling_edge = true;\n+        if (of_property_read_bool(np, \"capture-clear\"))\n+                data->capture_clear = true;\n \treturn 0;\n }\n \n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0076-lan78xx-Read-initial-EEE-status-from-DT.patch",
    "content": "From 1fbf5f72be35918230b0bbdff3bcf44318f1374a Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.org>\nDate: Fri, 9 Mar 2018 12:01:00 +0000\nSubject: [PATCH] lan78xx: Read initial EEE status from DT\n\nAdd two new DT properties:\n* microchip,eee-enabled  - a boolean to enable EEE\n* microchip,tx-lpi-timer - time in microseconds to wait before entering\n                           low power state\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.org>\n---\n drivers/net/usb/lan78xx.c | 16 ++++++++++++++++\n 1 file changed, 16 insertions(+)\n\n--- a/drivers/net/usb/lan78xx.c\n+++ b/drivers/net/usb/lan78xx.c\n@@ -2645,6 +2645,22 @@ static int lan78xx_open(struct net_devic\n \n \tnetif_dbg(dev, ifup, dev->net, \"phy initialised successfully\");\n \n+\tif (of_property_read_bool(dev->udev->dev.of_node,\n+\t\t\t\t  \"microchip,eee-enabled\")) {\n+\t\tstruct ethtool_eee edata;\n+\t\tmemset(&edata, 0, sizeof(edata));\n+\t\tedata.cmd = ETHTOOL_SEEE;\n+\t\tedata.advertised = ADVERTISED_1000baseT_Full |\n+\t\t\t\t   ADVERTISED_100baseT_Full;\n+\t\tedata.eee_enabled = true;\n+\t\tedata.tx_lpi_enabled = true;\n+\t\tif (of_property_read_u32(dev->udev->dev.of_node,\n+\t\t\t\t\t \"microchip,tx-lpi-timer\",\n+\t\t\t\t\t &edata.tx_lpi_timer))\n+\t\t\tedata.tx_lpi_timer = 600; /* non-aggressive */\n+\t\t(void)lan78xx_set_eee(net, &edata);\n+\t}\n+\n \t/* for Link Check */\n \tif (dev->urb_intr) {\n \t\tret = usb_submit_urb(dev->urb_intr, GFP_KERNEL);\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0077-hid-Reduce-default-mouse-polling-interval-to-60Hz.patch",
    "content": "From 32648d9e5440756f571bff70e8c49069dbba5137 Mon Sep 17 00:00:00 2001\nFrom: popcornmix <popcornmix@gmail.com>\nDate: Mon, 14 Jul 2014 22:02:09 +0100\nSubject: [PATCH] hid: Reduce default mouse polling interval to 60Hz\n\nReduces overhead when using X\n---\n drivers/hid/usbhid/hid-core.c | 6 ++++--\n 1 file changed, 4 insertions(+), 2 deletions(-)\n\n--- a/drivers/hid/usbhid/hid-core.c\n+++ b/drivers/hid/usbhid/hid-core.c\n@@ -45,7 +45,7 @@\n  * Module parameters.\n  */\n \n-static unsigned int hid_mousepoll_interval;\n+static unsigned int hid_mousepoll_interval = ~0;\n module_param_named(mousepoll, hid_mousepoll_interval, uint, 0644);\n MODULE_PARM_DESC(mousepoll, \"Polling interval of mice\");\n \n@@ -1114,7 +1114,9 @@ static int usbhid_start(struct hid_devic\n \t\t */\n \t\tswitch (hid->collection->usage) {\n \t\tcase HID_GD_MOUSE:\n-\t\t\tif (hid_mousepoll_interval > 0)\n+\t\t\tif (hid_mousepoll_interval == ~0 && interval < 16)\n+\t\t\t\tinterval = 16;\n+\t\t\telse if (hid_mousepoll_interval != ~0 && hid_mousepoll_interval != 0)\n \t\t\t\tinterval = hid_mousepoll_interval;\n \t\t\tbreak;\n \t\tcase HID_GD_JOYSTICK:\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0078-Add-ability-to-export-gpio-used-by-gpio-poweroff.patch",
    "content": "From a8d5d1b7fbc78132f5def4b8af4f221df83df04e Mon Sep 17 00:00:00 2001\nFrom: Nick Bulleid <nedbulleid@fastmail.com>\nDate: Thu, 10 May 2018 21:57:02 +0100\nSubject: [PATCH] Add ability to export gpio used by gpio-poweroff\n\nSigned-off-by: Nick Bulleid <nedbulleid@fastmail.com>\n\nAdded export feature to gpio-poweroff documentation\n\nSigned-off-by: Nick Bulleid <nedbulleid@fastmail.com>\n---\n .../devicetree/bindings/power/reset/gpio-poweroff.txt    | 1 +\n drivers/power/reset/gpio-poweroff.c                      | 9 +++++++++\n 2 files changed, 10 insertions(+)\n\n--- a/Documentation/devicetree/bindings/power/reset/gpio-poweroff.txt\n+++ b/Documentation/devicetree/bindings/power/reset/gpio-poweroff.txt\n@@ -31,6 +31,7 @@ Optional properties:\n - inactive-delay-ms: Delay (default 100) to wait after driving gpio inactive\n - timeout-ms: Time to wait before asserting a WARN_ON(1). If nothing is\n               specified, 3000 ms is used.\n+- export : Export the GPIO line to the sysfs system\n \n Examples:\n \n--- a/drivers/power/reset/gpio-poweroff.c\n+++ b/drivers/power/reset/gpio-poweroff.c\n@@ -51,6 +51,7 @@ static int gpio_poweroff_probe(struct pl\n \tbool input = false;\n \tenum gpiod_flags flags;\n \tbool force = false;\n+\tbool export = false;\n \n \t/* If a pm_power_off function has already been added, leave it alone */\n \tforce = of_property_read_bool(pdev->dev.of_node, \"force\");\n@@ -76,6 +77,12 @@ static int gpio_poweroff_probe(struct pl\n \tif (IS_ERR(reset_gpio))\n \t\treturn PTR_ERR(reset_gpio);\n \n+\texport = of_property_read_bool(pdev->dev.of_node, \"export\");\n+\tif (export) {\n+\t\tgpiod_export(reset_gpio, false);\n+\t\tgpiod_export_link(&pdev->dev, \"poweroff-gpio\", reset_gpio);\n+\t}\n+\n \tpm_power_off = &gpio_poweroff_do_poweroff;\n \treturn 0;\n }\n@@ -85,6 +92,8 @@ static int gpio_poweroff_remove(struct p\n \tif (pm_power_off == &gpio_poweroff_do_poweroff)\n \t\tpm_power_off = NULL;\n \n+\tgpiod_unexport(reset_gpio);\n+\n \treturn 0;\n }\n \n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0079-firmware-raspberrypi-Notify-firmware-of-a-reboot.patch",
    "content": "From bf6b5dbb7c8423b9d6bdfec21a9122691f2587d9 Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.org>\nDate: Sat, 12 May 2018 21:35:43 +0100\nSubject: [PATCH] firmware/raspberrypi: Notify firmware of a reboot\n\nRegister for reboot notifications, sending RPI_FIRMWARE_NOTIFY_REBOOT\nover the mailbox interface on reception.\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.org>\n---\n drivers/firmware/raspberrypi.c | 40 +++++++++++++++++++++++++++++++++-\n 1 file changed, 39 insertions(+), 1 deletion(-)\n\n--- a/drivers/firmware/raspberrypi.c\n+++ b/drivers/firmware/raspberrypi.c\n@@ -12,6 +12,7 @@\n #include <linux/module.h>\n #include <linux/of_platform.h>\n #include <linux/platform_device.h>\n+#include <linux/reboot.h>\n #include <linux/slab.h>\n #include <soc/bcm2835/raspberrypi-firmware.h>\n \n@@ -180,6 +181,26 @@ int rpi_firmware_property(struct rpi_fir\n }\n EXPORT_SYMBOL_GPL(rpi_firmware_property);\n \n+static int rpi_firmware_notify_reboot(struct notifier_block *nb,\n+\t\t\t\t      unsigned long action,\n+\t\t\t\t      void *data)\n+{\n+\tstruct rpi_firmware *fw;\n+\tstruct platform_device *pdev = g_pdev;\n+\n+\tif (!pdev)\n+\t\treturn 0;\n+\n+\tfw = platform_get_drvdata(pdev);\n+\tif (!fw)\n+\t\treturn 0;\n+\n+\t(void)rpi_firmware_property(fw, RPI_FIRMWARE_NOTIFY_REBOOT,\n+\t\t\t\t    0, 0);\n+\n+\treturn 0;\n+}\n+\n static void\n rpi_firmware_print_firmware_revision(struct rpi_firmware *fw)\n {\n@@ -356,15 +377,32 @@ static struct platform_driver rpi_firmwa\n \t.remove\t\t= rpi_firmware_remove,\n };\n \n+static struct notifier_block rpi_firmware_reboot_notifier = {\n+\t.notifier_call = rpi_firmware_notify_reboot,\n+};\n+\n static int __init rpi_firmware_init(void)\n {\n-\treturn platform_driver_register(&rpi_firmware_driver);\n+\tint ret = register_reboot_notifier(&rpi_firmware_reboot_notifier);\n+\tif (ret)\n+\t\tgoto out1;\n+\tret = platform_driver_register(&rpi_firmware_driver);\n+\tif (ret)\n+\t\tgoto out2;\n+\n+\treturn 0;\n+\n+out2:\n+\tunregister_reboot_notifier(&rpi_firmware_reboot_notifier);\n+out1:\n+\treturn ret;\n }\n subsys_initcall(rpi_firmware_init);\n \n static void __init rpi_firmware_exit(void)\n {\n \tplatform_driver_unregister(&rpi_firmware_driver);\n+\tunregister_reboot_notifier(&rpi_firmware_reboot_notifier);\n }\n module_exit(rpi_firmware_exit);\n \n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0080-irqchip-irq-bcm2835-Calc.-FIQ_START-at-boot-time.patch",
    "content": "From 35a38d723d9cd61be4c39defad4e44b1a6acc4b8 Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.org>\nDate: Thu, 14 Jun 2018 11:21:04 +0100\nSubject: [PATCH] irqchip: irq-bcm2835: Calc. FIQ_START at boot-time\n\nad83c7cb2f37 (\"irqchip/irq-bcm2836: Add support for DT interrupt polarity\")\nchanged the way that the BCM2836/7 local interrupts are mapped; instead\nof being pre-mapped they are now mapped on-demand. A side effect of this\nchange is that the call to irq_of_parse_and_map from armctrl_of_init\ncreates a new mapping, forming a gap between the IRQs and the FIQs. This\n gap breaks the FIQ<->IRQ mapping which up to now has been done by assuming:\n\n1) that the value of FIQ_START is the same as the number of normal IRQs\nthat will be mapped (still true), and\n\n2) that this value is also the offset between an IRQ and its equivalent\nFIQ (which is no longer the case).\n\nRemove both assumptions by measuring the interval between the last IRQ\nand the last FIQ, passing it as the parameter to init_FIQ().\n\nFixes: https://github.com/raspberrypi/linux/issues/2432\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.org>\n---\n drivers/irqchip/irq-bcm2835.c | 8 ++++----\n 1 file changed, 4 insertions(+), 4 deletions(-)\n\n--- a/drivers/irqchip/irq-bcm2835.c\n+++ b/drivers/irqchip/irq-bcm2835.c\n@@ -74,8 +74,6 @@\n #define NR_BANKS\t\t3\n #define IRQS_PER_BANK\t\t32\n #define NUMBER_IRQS\t\tMAKE_HWIRQ(NR_BANKS, 0)\n-#undef FIQ_START\n-#define FIQ_START\t\t(NR_IRQS_BANK0 + MAKE_HWIRQ(NR_BANKS - 1, 0))\n \n static const int reg_pending[] __initconst = { 0x00, 0x04, 0x08 };\n static const int reg_enable[] __initconst = { 0x18, 0x10, 0x14 };\n@@ -203,7 +201,7 @@ static int __init armctrl_of_init(struct\n \t\t\t\t  bool is_2836)\n {\n \tvoid __iomem *base;\n-\tint irq, b, i;\n+\tint irq = 0, last_irq, b, i;\n \tu32 reg;\n \n \tbase = of_iomap(node, 0);\n@@ -243,6 +241,8 @@ static int __init armctrl_of_init(struct\n \t\tpr_err(FW_BUG \"Bootloader left fiq enabled\\n\");\n \t}\n \n+\tlast_irq = irq;\n+\n \tif (is_2836) {\n \t\tint parent_irq = irq_of_parse_and_map(node, 0);\n \n@@ -273,7 +273,7 @@ static int __init armctrl_of_init(struct\n \t\t}\n \t}\n #ifndef CONFIG_ARM64\n-\tinit_FIQ(FIQ_START);\n+\tinit_FIQ(irq - last_irq);\n #endif\n \n \treturn 0;\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0081-of-configfs-Use-of_overlay_fdt_apply-API-call.patch",
    "content": "From 342afb4c37627f9d8e9d5bb07b3182a5c412c75e Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.org>\nDate: Thu, 14 Jun 2018 15:07:26 +0100\nSubject: [PATCH] of: configfs: Use of_overlay_fdt_apply API call\n\nThe published API to the dynamic overlay application mechanism now\ntakes a Flattened Device Tree blob as input so that it can manage the\nlifetime of the unflattened tree. Conveniently, the new API call -\nof_overlay_fdt_apply - is virtually a drop-in replacement for\ncreate_overlay, which can now be deleted.\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.org>\n---\n drivers/of/configfs.c | 47 +++++++------------------------------------\n 1 file changed, 7 insertions(+), 40 deletions(-)\n\n--- a/drivers/of/configfs.c\n+++ b/drivers/of/configfs.c\n@@ -40,41 +40,6 @@ struct cfs_overlay_item {\n \tint\t\t\tdtbo_size;\n };\n \n-static int create_overlay(struct cfs_overlay_item *overlay, void *blob)\n-{\n-\tint err;\n-\n-\t/* unflatten the tree */\n-\tof_fdt_unflatten_tree(blob, NULL, &overlay->overlay);\n-\tif (overlay->overlay == NULL) {\n-\t\tpr_err(\"%s: failed to unflatten tree\\n\", __func__);\n-\t\terr = -EINVAL;\n-\t\tgoto out_err;\n-\t}\n-\tpr_debug(\"%s: unflattened OK\\n\", __func__);\n-\n-\t/* mark it as detached */\n-\tof_node_set_flag(overlay->overlay, OF_DETACHED);\n-\n-\t/* perform resolution */\n-\terr = of_resolve_phandles(overlay->overlay);\n-\tif (err != 0) {\n-\t\tpr_err(\"%s: Failed to resolve tree\\n\", __func__);\n-\t\tgoto out_err;\n-\t}\n-\tpr_debug(\"%s: resolved OK\\n\", __func__);\n-\n-\terr = of_overlay_apply(overlay->overlay, &overlay->ov_id);\n-\tif (err < 0) {\n-\t\tpr_err(\"%s: Failed to create overlay (err=%d)\\n\",\n-\t\t\t\t__func__, err);\n-\t\tgoto out_err;\n-\t}\n-\n-out_err:\n-\treturn err;\n-}\n-\n static inline struct cfs_overlay_item *to_cfs_overlay_item(\n \t\tstruct config_item *item)\n {\n@@ -115,7 +80,8 @@ static ssize_t cfs_overlay_item_path_sto\n \tif (err != 0)\n \t\tgoto out_err;\n \n-\terr = create_overlay(overlay, (void *)overlay->fw->data);\n+\terr = of_overlay_fdt_apply((void *)overlay->fw->data,\n+\t\t\t\t   (u32)overlay->fw->size, &overlay->ov_id);\n \tif (err != 0)\n \t\tgoto out_err;\n \n@@ -136,7 +102,7 @@ static ssize_t cfs_overlay_item_status_s\n \tstruct cfs_overlay_item *overlay = to_cfs_overlay_item(item);\n \n \treturn sprintf(page, \"%s\\n\",\n-\t\t\toverlay->ov_id >= 0 ? \"applied\" : \"unapplied\");\n+\t\t\toverlay->ov_id > 0 ? \"applied\" : \"unapplied\");\n }\n \n CONFIGFS_ATTR(cfs_overlay_item_, path);\n@@ -188,7 +154,8 @@ ssize_t cfs_overlay_item_dtbo_write(stru\n \n \toverlay->dtbo_size = count;\n \n-\terr = create_overlay(overlay, overlay->dtbo);\n+\terr = of_overlay_fdt_apply(overlay->dtbo, overlay->dtbo_size,\n+\t\t\t\t   &overlay->ov_id);\n \tif (err != 0)\n \t\tgoto out_err;\n \n@@ -198,6 +165,7 @@ out_err:\n \tkfree(overlay->dtbo);\n \toverlay->dtbo = NULL;\n \toverlay->dtbo_size = 0;\n+\toverlay->ov_id = 0;\n \n \treturn err;\n }\n@@ -213,7 +181,7 @@ static void cfs_overlay_release(struct c\n {\n \tstruct cfs_overlay_item *overlay = to_cfs_overlay_item(item);\n \n-\tif (overlay->ov_id >= 0)\n+\tif (overlay->ov_id > 0)\n \t\tof_overlay_remove(&overlay->ov_id);\n \tif (overlay->fw)\n \t\trelease_firmware(overlay->fw);\n@@ -241,7 +209,6 @@ static struct config_item *cfs_overlay_g\n \toverlay = kzalloc(sizeof(*overlay), GFP_KERNEL);\n \tif (!overlay)\n \t\treturn ERR_PTR(-ENOMEM);\n-\toverlay->ov_id = -1;\n \n \tconfig_item_init_type_name(&overlay->item, name, &cfs_overlay_type);\n \treturn &overlay->item;\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0082-net-lan78xx-Disable-TCP-Segmentation-Offload-TSO.patch",
    "content": "From 42606db546588b0e0b8084466b9b31ec111640a4 Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.org>\nDate: Wed, 13 Jun 2018 15:21:10 +0100\nSubject: [PATCH] net: lan78xx: Disable TCP Segmentation Offload (TSO)\n\nTSO seems to be having issues when packets are dropped and the\nremote end uses Selective Acknowledge (SACK) to denote that\ndata is missing. The missing data is never resent, so the\nconnection eventually stalls.\n\nThere is a module parameter of enable_tso added to allow\nfurther debugging without forcing a rebuild of the kernel.\n\nhttps://github.com/raspberrypi/linux/issues/2449\nhttps://github.com/raspberrypi/linux/issues/2482\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>\n---\n drivers/net/usb/lan78xx.c | 19 +++++++++++++++++--\n 1 file changed, 17 insertions(+), 2 deletions(-)\n\n--- a/drivers/net/usb/lan78xx.c\n+++ b/drivers/net/usb/lan78xx.c\n@@ -427,6 +427,15 @@ static int msg_level = -1;\n module_param(msg_level, int, 0);\n MODULE_PARM_DESC(msg_level, \"Override default message level\");\n \n+/* TSO seems to be having some issue with Selective Acknowledge (SACK) that\n+ * results in lost data never being retransmitted.\n+ * Disable it by default now, but adds a module parameter to enable it for\n+ * debug purposes (the full cause is not currently understood).\n+ */\n+static bool enable_tso;\n+module_param(enable_tso, bool, 0644);\n+MODULE_PARM_DESC(enable_tso, \"Enables TCP segmentation offload\");\n+\n static int lan78xx_read_reg(struct lan78xx_net *dev, u32 index, u32 *data)\n {\n \tu32 *buf = kmalloc(sizeof(u32), GFP_KERNEL);\n@@ -2927,8 +2936,14 @@ static int lan78xx_bind(struct lan78xx_n\n \tif (DEFAULT_RX_CSUM_ENABLE)\n \t\tdev->net->features |= NETIF_F_RXCSUM;\n \n-\tif (DEFAULT_TSO_CSUM_ENABLE)\n-\t\tdev->net->features |= NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_SG;\n+\tif (DEFAULT_TSO_CSUM_ENABLE) {\n+\t\tdev->net->features |= NETIF_F_SG;\n+\t\t/* Use module parameter to control TCP segmentation offload as\n+\t\t * it appears to cause issues.\n+\t\t */\n+\t\tif (enable_tso)\n+\t\t\tdev->net->features |= NETIF_F_TSO | NETIF_F_TSO6;\n+\t}\n \n \tif (DEFAULT_VLAN_RX_OFFLOAD)\n \t\tdev->net->features |= NETIF_F_HW_VLAN_CTAG_RX;\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0083-lan78xx-Move-enabling-of-EEE-into-PHY-init-code.patch",
    "content": "From c6edee4700821a65c9d94ac8e16b488fc652efd8 Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.org>\nDate: Thu, 5 Apr 2018 14:46:11 +0100\nSubject: [PATCH] lan78xx: Move enabling of EEE into PHY init code\n\nEnable EEE mode as soon as possible after connecting to the PHY, and\nbefore phy_start. This avoids a second link negotiation, which speeds\nup booting and stops the interface failing to become ready.\n\nSee: https://github.com/raspberrypi/linux/issues/2437\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.org>\n---\n drivers/net/usb/lan78xx.c | 32 ++++++++++++++++----------------\n 1 file changed, 16 insertions(+), 16 deletions(-)\n\n--- a/drivers/net/usb/lan78xx.c\n+++ b/drivers/net/usb/lan78xx.c\n@@ -2177,6 +2177,22 @@ static int lan78xx_phy_init(struct lan78\n \tmii_adv_to_linkmode_adv_t(fc, mii_adv);\n \tlinkmode_or(phydev->advertising, fc, phydev->advertising);\n \n+\tif (of_property_read_bool(dev->udev->dev.of_node,\n+\t\t\t\t  \"microchip,eee-enabled\")) {\n+\t\tstruct ethtool_eee edata;\n+\t\tmemset(&edata, 0, sizeof(edata));\n+\t\tedata.cmd = ETHTOOL_SEEE;\n+\t\tedata.advertised = ADVERTISED_1000baseT_Full |\n+\t\t\t\t   ADVERTISED_100baseT_Full;\n+\t\tedata.eee_enabled = true;\n+\t\tedata.tx_lpi_enabled = true;\n+\t\tif (of_property_read_u32(dev->udev->dev.of_node,\n+\t\t\t\t\t \"microchip,tx-lpi-timer\",\n+\t\t\t\t\t &edata.tx_lpi_timer))\n+\t\t\tedata.tx_lpi_timer = 600; /* non-aggressive */\n+\t\t(void)lan78xx_set_eee(dev->net, &edata);\n+\t}\n+\n \tif (phydev->mdio.dev.of_node) {\n \t\tu32 reg;\n \t\tint len;\n@@ -2654,22 +2670,6 @@ static int lan78xx_open(struct net_devic\n \n \tnetif_dbg(dev, ifup, dev->net, \"phy initialised successfully\");\n \n-\tif (of_property_read_bool(dev->udev->dev.of_node,\n-\t\t\t\t  \"microchip,eee-enabled\")) {\n-\t\tstruct ethtool_eee edata;\n-\t\tmemset(&edata, 0, sizeof(edata));\n-\t\tedata.cmd = ETHTOOL_SEEE;\n-\t\tedata.advertised = ADVERTISED_1000baseT_Full |\n-\t\t\t\t   ADVERTISED_100baseT_Full;\n-\t\tedata.eee_enabled = true;\n-\t\tedata.tx_lpi_enabled = true;\n-\t\tif (of_property_read_u32(dev->udev->dev.of_node,\n-\t\t\t\t\t \"microchip,tx-lpi-timer\",\n-\t\t\t\t\t &edata.tx_lpi_timer))\n-\t\t\tedata.tx_lpi_timer = 600; /* non-aggressive */\n-\t\t(void)lan78xx_set_eee(net, &edata);\n-\t}\n-\n \t/* for Link Check */\n \tif (dev->urb_intr) {\n \t\tret = usb_submit_urb(dev->urb_intr, GFP_KERNEL);\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0084-Add-rpi-poe-fan-driver.patch",
    "content": "From 079bce6210d997fda44d6143b4b394173360bef1 Mon Sep 17 00:00:00 2001\nFrom: Serge Schneider <serge@raspberrypi.org>\nDate: Mon, 9 Jul 2018 12:54:25 +0100\nSubject: [PATCH] Add rpi-poe-fan driver\n\nSigned-off-by: Serge Schneider <serge@raspberrypi.org>\n\nPoE HAT driver cleanup\n\n* Fix undeclared variable in rpi_poe_fan_suspend\n* Add SPDX-License-Identifier\n* Expand PoE acronym in Kconfig help\n* Give clearer error message on of_property_count_u32_elems fail\n* Add documentation\n* Add vendor to of_device_id compatible string.\n* Rename m_data_s struct to fw_data_s\n* Fix typos\n\nFixes: #2665\n\nSigned-off-by: Serge Schneider <serge@raspberrypi.org>\n\nrpi-poe-fan: fix def_pwm1 writes\n\nSigned-off-by: Serge Schneider <serge@raspberrypi.org>\n---\n .../devicetree/bindings/hwmon/rpi-poe-fan.txt |  55 +++\n Documentation/hwmon/rpi-poe-fan               |  15 +\n drivers/hwmon/Kconfig                         |  11 +\n drivers/hwmon/Makefile                        |   1 +\n drivers/hwmon/rpi-poe-fan.c                   | 436 ++++++++++++++++++\n 5 files changed, 518 insertions(+)\n create mode 100644 Documentation/devicetree/bindings/hwmon/rpi-poe-fan.txt\n create mode 100644 Documentation/hwmon/rpi-poe-fan\n create mode 100644 drivers/hwmon/rpi-poe-fan.c\n\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/hwmon/rpi-poe-fan.txt\n@@ -0,0 +1,55 @@\n+Bindings for the Raspberry Pi PoE HAT fan\n+\n+Required properties:\n+- compatible\t: \"raspberrypi,rpi-poe-fan\"\n+- firmware\t: Reference to the RPi firmware device node\n+- pwms\t\t: the PWM that is used to control the PWM fan\n+- cooling-levels      : PWM duty cycle values in a range from 0 to 255\n+\t\t\twhich correspond to thermal cooling states\n+\n+Example:\n+\tfan0: rpi-poe-fan@0 {\n+\t\tcompatible = \"raspberrypi,rpi-poe-fan\";\n+\t\tfirmware = <&firmware>;\n+\t\tcooling-min-state = <0>;\n+\t\tcooling-max-state = <3>;\n+\t\t#cooling-cells = <2>;\n+\t\tcooling-levels = <0 50 150 255>;\n+\t\tstatus = \"okay\";\n+\t};\n+\n+\tthermal-zones {\n+\t\tcpu_thermal: cpu-thermal {\n+\t\t\ttrips {\n+\t\t\t\tthreshold: trip-point@0 {\n+\t\t\t\t\ttemperature = <45000>;\n+\t\t\t\t\thysteresis = <5000>;\n+\t\t\t\t\ttype = \"active\";\n+\t\t\t\t};\n+\t\t\t\ttarget: trip-point@1 {\n+\t\t\t\t\ttemperature = <50000>;\n+\t\t\t\t\thysteresis = <2000>;\n+\t\t\t\t\ttype = \"active\";\n+\t\t\t\t};\n+\t\t\t\tcpu_hot: cpu_hot@0 {\n+\t\t\t\t\ttemperature = <55000>;\n+\t\t\t\t\thysteresis = <2000>;\n+\t\t\t\t\ttype = \"active\";\n+\t\t\t\t};\n+\t\t\t};\n+\t\t\tcooling-maps {\n+\t\t\t\tmap0 {\n+\t\t\t\t\ttrip = <&threshold>;\n+\t\t\t\t\tcooling-device = <&fan0 0 1>;\n+\t\t\t\t};\n+\t\t\t\tmap1 {\n+\t\t\t\t\ttrip = <&target>;\n+\t\t\t\t\tcooling-device = <&fan0 1 2>;\n+\t\t\t\t};\n+\t\t\t\tmap2 {\n+\t\t\t\t\ttrip = <&cpu_hot>;\n+\t\t\t\t\tcooling-device = <&fan0 2 3>;\n+\t\t\t\t};\n+\t\t\t};\n+\t\t};\n+\t};\n--- /dev/null\n+++ b/Documentation/hwmon/rpi-poe-fan\n@@ -0,0 +1,15 @@\n+Kernel driver rpi-poe-fan\n+=====================\n+\n+This driver enables the use of the Raspberry Pi PoE HAT fan.\n+\n+Author: Serge Schneider <serge@raspberrypi.org>\n+\n+Description\n+-----------\n+\n+The driver implements a simple interface for driving the Raspberry Pi PoE\n+(Power over Ethernet) HAT fan. The driver passes commands to the Raspberry Pi\n+firmware through the mailbox property interface. The firmware then forwards\n+the commands to the board over I2C on the ID_EEPROM pins. The driver exposes\n+the fan to the user space through the hwmon sysfs interface.\n--- a/drivers/hwmon/Kconfig\n+++ b/drivers/hwmon/Kconfig\n@@ -1489,6 +1489,17 @@ config SENSORS_RASPBERRYPI_HWMON\n \t  This driver can also be built as a module. If so, the module\n \t  will be called raspberrypi-hwmon.\n \n+config SENSORS_RPI_POE_FAN\n+\ttristate \"Raspberry Pi PoE HAT fan\"\n+\tdepends on RASPBERRYPI_FIRMWARE\n+\tdepends on THERMAL || THERMAL=n\n+\thelp\n+\t  If you say yes here you get support for Raspberry Pi PoE (Power over\n+\t  Ethernet) HAT fan.\n+\n+\t  This driver can also be built as a module.  If so, the module\n+\t  will be called rpi-poe-fan.\n+\n config SENSORS_SL28CPLD\n \ttristate \"Kontron sl28cpld hardware monitoring driver\"\n \tdepends on MFD_SL28CPLD || COMPILE_TEST\n--- a/drivers/hwmon/Makefile\n+++ b/drivers/hwmon/Makefile\n@@ -157,6 +157,7 @@ obj-$(CONFIG_SENSORS_PCF8591)\t+= pcf8591\n obj-$(CONFIG_SENSORS_POWR1220)  += powr1220.o\n obj-$(CONFIG_SENSORS_PWM_FAN)\t+= pwm-fan.o\n obj-$(CONFIG_SENSORS_RASPBERRYPI_HWMON)\t+= raspberrypi-hwmon.o\n+obj-$(CONFIG_SENSORS_RPI_POE_FAN)\t+= rpi-poe-fan.o\n obj-$(CONFIG_SENSORS_S3C)\t+= s3c-hwmon.o\n obj-$(CONFIG_SENSORS_SCH56XX_COMMON)+= sch56xx-common.o\n obj-$(CONFIG_SENSORS_SCH5627)\t+= sch5627.o\n--- /dev/null\n+++ b/drivers/hwmon/rpi-poe-fan.c\n@@ -0,0 +1,436 @@\n+// SPDX-License-Identifier: GPL-2.0\n+/*\n+ * rpi-poe-fan.c - Hwmon driver for Raspberry Pi PoE HAT fan.\n+ *\n+ * Copyright (C) 2018 Raspberry Pi (Trading) Ltd.\n+ * Based on pwm-fan.c by Kamil Debski <k.debski@samsung.com>\n+ *\n+ * Author: Serge Schneider <serge@raspberrypi.org>\n+ */\n+\n+#include <linux/hwmon.h>\n+#include <linux/hwmon-sysfs.h>\n+#include <linux/module.h>\n+#include <linux/mutex.h>\n+#include <linux/notifier.h>\n+#include <linux/of.h>\n+#include <linux/platform_device.h>\n+#include <linux/reboot.h>\n+#include <linux/sysfs.h>\n+#include <linux/thermal.h>\n+#include <soc/bcm2835/raspberrypi-firmware.h>\n+\n+#define MAX_PWM 255\n+\n+#define POE_CUR_PWM 0x0\n+#define POE_DEF_PWM 0x1\n+\n+struct rpi_poe_fan_ctx {\n+\tstruct mutex lock;\n+\tstruct rpi_firmware *fw;\n+\tunsigned int pwm_value;\n+\tunsigned int def_pwm_value;\n+\tunsigned int rpi_poe_fan_state;\n+\tunsigned int rpi_poe_fan_max_state;\n+\tunsigned int *rpi_poe_fan_cooling_levels;\n+\tstruct thermal_cooling_device *cdev;\n+\tstruct notifier_block nb;\n+};\n+\n+struct fw_tag_data_s{\n+\tu32 reg;\n+\tu32 val;\n+\tu32 ret;\n+};\n+\n+static int write_reg(struct rpi_firmware *fw, u32 reg, u32 *val){\n+\tstruct fw_tag_data_s fw_tag_data = {\n+\t\t.reg = reg,\n+\t\t.val = *val\n+\t};\n+\tint ret;\n+\tret = rpi_firmware_property(fw, RPI_FIRMWARE_SET_POE_HAT_VAL,\n+\t\t\t\t    &fw_tag_data, sizeof(fw_tag_data));\n+\tif (ret) {\n+\t\treturn ret;\n+\t} else if (fw_tag_data.ret) {\n+\t\treturn -EIO;\n+\t}\n+\treturn 0;\n+}\n+\n+static int read_reg(struct rpi_firmware *fw, u32 reg, u32 *val){\n+\tstruct fw_tag_data_s fw_tag_data = {\n+\t\t.reg = reg,\n+\t};\n+\tint ret;\n+\tret = rpi_firmware_property(fw, RPI_FIRMWARE_GET_POE_HAT_VAL,\n+\t\t\t\t    &fw_tag_data, sizeof(fw_tag_data));\n+\tif (ret) {\n+\t\treturn ret;\n+\t} else if (fw_tag_data.ret) {\n+\t\treturn -EIO;\n+\t}\n+\t*val = fw_tag_data.val;\n+\treturn 0;\n+}\n+\n+static int rpi_poe_reboot(struct notifier_block *nb, unsigned long code,\n+\t\t\t  void *unused)\n+{\n+\tstruct rpi_poe_fan_ctx *ctx = container_of(nb, struct rpi_poe_fan_ctx,\n+\t\t\t\t\t\t   nb);\n+\n+\tif (ctx->pwm_value != ctx->def_pwm_value)\n+\t\twrite_reg(ctx->fw, POE_CUR_PWM, &ctx->def_pwm_value);\n+\n+\treturn NOTIFY_DONE;\n+}\n+\n+static int  __set_pwm(struct rpi_poe_fan_ctx *ctx, u32 pwm)\n+{\n+\tint ret = 0;\n+\n+\tmutex_lock(&ctx->lock);\n+\tif (ctx->pwm_value == pwm)\n+\t\tgoto exit_set_pwm_err;\n+\n+\tret = write_reg(ctx->fw, POE_CUR_PWM, &pwm);\n+\tif (!ret)\n+\t\tctx->pwm_value = pwm;\n+exit_set_pwm_err:\n+\tmutex_unlock(&ctx->lock);\n+\treturn ret;\n+}\n+\n+static int  __set_def_pwm(struct rpi_poe_fan_ctx *ctx, u32 def_pwm)\n+{\n+\tint ret = 0;\n+\tmutex_lock(&ctx->lock);\n+\tif (ctx->def_pwm_value == def_pwm)\n+\t\tgoto exit_set_def_pwm_err;\n+\n+\tret = write_reg(ctx->fw, POE_DEF_PWM, &def_pwm);\n+\tif (!ret)\n+\t\tctx->def_pwm_value = def_pwm;\n+exit_set_def_pwm_err:\n+\tmutex_unlock(&ctx->lock);\n+\treturn ret;\n+}\n+\n+static void rpi_poe_fan_update_state(struct rpi_poe_fan_ctx *ctx,\n+\t\t\t\t     unsigned long pwm)\n+{\n+\tint i;\n+\n+\tfor (i = 0; i < ctx->rpi_poe_fan_max_state; ++i)\n+\t\tif (pwm < ctx->rpi_poe_fan_cooling_levels[i + 1])\n+\t\t\tbreak;\n+\n+\tctx->rpi_poe_fan_state = i;\n+}\n+\n+static ssize_t set_pwm(struct device *dev, struct device_attribute *attr,\n+\t\t       const char *buf, size_t count)\n+{\n+\tstruct rpi_poe_fan_ctx *ctx = dev_get_drvdata(dev);\n+\tunsigned long pwm;\n+\tint ret;\n+\n+\tif (kstrtoul(buf, 10, &pwm) || pwm > MAX_PWM)\n+\t\treturn -EINVAL;\n+\n+\tret = __set_pwm(ctx, pwm);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\trpi_poe_fan_update_state(ctx, pwm);\n+\treturn count;\n+}\n+\n+static ssize_t set_def_pwm(struct device *dev, struct device_attribute *attr,\n+\t\t\t   const char *buf, size_t count)\n+{\n+\tstruct rpi_poe_fan_ctx *ctx = dev_get_drvdata(dev);\n+\tunsigned long def_pwm;\n+\tint ret;\n+\n+\tif (kstrtoul(buf, 10, &def_pwm) || def_pwm > MAX_PWM)\n+\t\treturn -EINVAL;\n+\n+\tret = __set_def_pwm(ctx, def_pwm);\n+\tif (ret)\n+\t\treturn ret;\n+\treturn count;\n+}\n+\n+static ssize_t show_pwm(struct device *dev,\n+\t\t\tstruct device_attribute *attr, char *buf)\n+{\n+\tstruct rpi_poe_fan_ctx *ctx = dev_get_drvdata(dev);\n+\n+\treturn sprintf(buf, \"%u\\n\", ctx->pwm_value);\n+}\n+\n+static ssize_t show_def_pwm(struct device *dev,\n+\t\t\tstruct device_attribute *attr, char *buf)\n+{\n+\tstruct rpi_poe_fan_ctx *ctx = dev_get_drvdata(dev);\n+\n+\treturn sprintf(buf, \"%u\\n\", ctx->def_pwm_value);\n+}\n+\n+\n+static SENSOR_DEVICE_ATTR(pwm1, 0644, show_pwm, set_pwm, 0);\n+static SENSOR_DEVICE_ATTR(def_pwm1, 0644, show_def_pwm, set_def_pwm, 1);\n+\n+static struct attribute *rpi_poe_fan_attrs[] = {\n+\t&sensor_dev_attr_pwm1.dev_attr.attr,\n+\t&sensor_dev_attr_def_pwm1.dev_attr.attr,\n+\tNULL,\n+};\n+\n+ATTRIBUTE_GROUPS(rpi_poe_fan);\n+\n+/* thermal cooling device callbacks */\n+static int rpi_poe_fan_get_max_state(struct thermal_cooling_device *cdev,\n+\t\t\t\t     unsigned long *state)\n+{\n+\tstruct rpi_poe_fan_ctx *ctx = cdev->devdata;\n+\n+\tif (!ctx)\n+\t\treturn -EINVAL;\n+\n+\t*state = ctx->rpi_poe_fan_max_state;\n+\n+\treturn 0;\n+}\n+\n+static int rpi_poe_fan_get_cur_state(struct thermal_cooling_device *cdev,\n+\t\t\t\t     unsigned long *state)\n+{\n+\tstruct rpi_poe_fan_ctx *ctx = cdev->devdata;\n+\n+\tif (!ctx)\n+\t\treturn -EINVAL;\n+\n+\t*state = ctx->rpi_poe_fan_state;\n+\n+\treturn 0;\n+}\n+\n+static int rpi_poe_fan_set_cur_state(struct thermal_cooling_device *cdev,\n+\t\t\t\t     unsigned long state)\n+{\n+\tstruct rpi_poe_fan_ctx *ctx = cdev->devdata;\n+\tint ret;\n+\n+\tif (!ctx || (state > ctx->rpi_poe_fan_max_state))\n+\t\treturn -EINVAL;\n+\n+\tif (state == ctx->rpi_poe_fan_state)\n+\t\treturn 0;\n+\n+\tret = __set_pwm(ctx, ctx->rpi_poe_fan_cooling_levels[state]);\n+\tif (ret) {\n+\t\tdev_err(&cdev->device, \"Cannot set pwm!\\n\");\n+\t\treturn ret;\n+\t}\n+\n+\tctx->rpi_poe_fan_state = state;\n+\n+\treturn ret;\n+}\n+\n+static const struct thermal_cooling_device_ops rpi_poe_fan_cooling_ops = {\n+\t.get_max_state = rpi_poe_fan_get_max_state,\n+\t.get_cur_state = rpi_poe_fan_get_cur_state,\n+\t.set_cur_state = rpi_poe_fan_set_cur_state,\n+};\n+\n+static int rpi_poe_fan_of_get_cooling_data(struct device *dev,\n+\t\t\t\t       struct rpi_poe_fan_ctx *ctx)\n+{\n+\tstruct device_node *np = dev->of_node;\n+\tint num, i, ret;\n+\n+\tif (!of_find_property(np, \"cooling-levels\", NULL))\n+\t\treturn 0;\n+\n+\tret = of_property_count_u32_elems(np, \"cooling-levels\");\n+\tif (ret <= 0) {\n+\t\tdev_err(dev, \"cooling-levels property missing or invalid: %d\\n\",\n+\t\t\tret);\n+\t\treturn ret ? : -EINVAL;\n+\t}\n+\n+\tnum = ret;\n+\tctx->rpi_poe_fan_cooling_levels = devm_kzalloc(dev, num * sizeof(u32),\n+\t\t\t\t\t\t   GFP_KERNEL);\n+\tif (!ctx->rpi_poe_fan_cooling_levels)\n+\t\treturn -ENOMEM;\n+\n+\tret = of_property_read_u32_array(np, \"cooling-levels\",\n+\t\t\t\t\t ctx->rpi_poe_fan_cooling_levels, num);\n+\tif (ret) {\n+\t\tdev_err(dev, \"Property 'cooling-levels' cannot be read!\\n\");\n+\t\treturn ret;\n+\t}\n+\n+\tfor (i = 0; i < num; i++) {\n+\t\tif (ctx->rpi_poe_fan_cooling_levels[i] > MAX_PWM) {\n+\t\t\tdev_err(dev, \"PWM fan state[%d]:%d > %d\\n\", i,\n+\t\t\t\tctx->rpi_poe_fan_cooling_levels[i], MAX_PWM);\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t}\n+\n+\tctx->rpi_poe_fan_max_state = num - 1;\n+\n+\treturn 0;\n+}\n+\n+static int rpi_poe_fan_probe(struct platform_device *pdev)\n+{\n+\tstruct thermal_cooling_device *cdev;\n+\tstruct rpi_poe_fan_ctx *ctx;\n+\tstruct device *hwmon;\n+\tstruct device_node *np = pdev->dev.of_node;\n+\tstruct device_node *fw_node;\n+\tint ret;\n+\n+\tfw_node = of_parse_phandle(np, \"firmware\", 0);\n+\tif (!fw_node) {\n+\t\tdev_err(&pdev->dev, \"Missing firmware node\\n\");\n+\t\treturn -ENOENT;\n+\t}\n+\n+\tctx = devm_kzalloc(&pdev->dev, sizeof(*ctx), GFP_KERNEL);\n+\tif (!ctx)\n+\t\treturn -ENOMEM;\n+\n+\tmutex_init(&ctx->lock);\n+\n+\tctx->fw = rpi_firmware_get(fw_node);\n+\tif (!ctx->fw)\n+\t\treturn -EPROBE_DEFER;\n+\n+\tplatform_set_drvdata(pdev, ctx);\n+\n+\tctx->nb.notifier_call = rpi_poe_reboot;\n+\tret = register_reboot_notifier(&ctx->nb);\n+\tif (ret) {\n+\t\tdev_err(&pdev->dev, \"Failed to register reboot notifier: %i\\n\",\n+\t\t\tret);\n+\t\treturn ret;\n+\t}\n+\tret = read_reg(ctx->fw, POE_DEF_PWM, &ctx->def_pwm_value);\n+\tif (ret) {\n+\t\tdev_err(&pdev->dev, \"Failed to get default PWM value: %i\\n\",\n+\t\t\tret);\n+\t\tgoto err;\n+\t}\n+\tret = read_reg(ctx->fw, POE_CUR_PWM, &ctx->pwm_value);\n+\tif (ret) {\n+\t\tdev_err(&pdev->dev, \"Failed to get current PWM value: %i\\n\",\n+\t\t\tret);\n+\t\tgoto err;\n+\t}\n+\n+\thwmon = devm_hwmon_device_register_with_groups(&pdev->dev, \"rpipoefan\",\n+\t\t\t\t\t\t       ctx, rpi_poe_fan_groups);\n+\tif (IS_ERR(hwmon)) {\n+\t\tdev_err(&pdev->dev, \"Failed to register hwmon device\\n\");\n+\t\tret = PTR_ERR(hwmon);\n+\t\tgoto err;\n+\t}\n+\n+\tret = rpi_poe_fan_of_get_cooling_data(&pdev->dev, ctx);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\trpi_poe_fan_update_state(ctx, ctx->pwm_value);\n+\tif (!IS_ENABLED(CONFIG_THERMAL))\n+\t\treturn 0;\n+\n+\tcdev = thermal_of_cooling_device_register(np,\n+\t\t\t\t\t\t  \"rpi-poe-fan\", ctx,\n+\t\t\t\t\t\t  &rpi_poe_fan_cooling_ops);\n+\tif (IS_ERR(cdev)) {\n+\t\tdev_err(&pdev->dev,\n+\t\t\t\"Failed to register rpi-poe-fan as cooling device\");\n+\t\tret = PTR_ERR(cdev);\n+\t\tgoto err;\n+\t}\n+\tctx->cdev = cdev;\n+\tthermal_cdev_update(cdev);\n+\n+\treturn 0;\n+err:\n+\tunregister_reboot_notifier(&ctx->nb);\n+\treturn ret;\n+}\n+\n+static int rpi_poe_fan_remove(struct platform_device *pdev)\n+{\n+\tstruct rpi_poe_fan_ctx *ctx = platform_get_drvdata(pdev);\n+\tu32 value = ctx->def_pwm_value;\n+\n+\tunregister_reboot_notifier(&ctx->nb);\n+\tthermal_cooling_device_unregister(ctx->cdev);\n+\tif (ctx->pwm_value != value) {\n+\t\twrite_reg(ctx->fw, POE_CUR_PWM, &value);\n+\t}\n+\treturn 0;\n+}\n+\n+#ifdef CONFIG_PM_SLEEP\n+static int rpi_poe_fan_suspend(struct device *dev)\n+{\n+\tstruct rpi_poe_fan_ctx *ctx = dev_get_drvdata(dev);\n+\tu32 value = 0;\n+\tint ret = 0;\n+\n+\tif (ctx->pwm_value != value)\n+\t\tret = write_reg(ctx->fw, POE_CUR_PWM, &value);\n+\treturn ret;\n+}\n+\n+static int rpi_poe_fan_resume(struct device *dev)\n+{\n+\tstruct rpi_poe_fan_ctx *ctx = dev_get_drvdata(dev);\n+\tu32 value = ctx->pwm_value;\n+\tint ret = 0;\n+\n+\tif (value != 0)\n+\t\tret = write_reg(ctx->fw, POE_CUR_PWM, &value);\n+\n+\treturn ret;\n+}\n+#endif\n+\n+static SIMPLE_DEV_PM_OPS(rpi_poe_fan_pm, rpi_poe_fan_suspend,\n+\t\t\t rpi_poe_fan_resume);\n+\n+static const struct of_device_id of_rpi_poe_fan_match[] = {\n+\t{ .compatible = \"raspberrypi,rpi-poe-fan\", },\n+\t{},\n+};\n+MODULE_DEVICE_TABLE(of, of_rpi_poe_fan_match);\n+\n+static struct platform_driver rpi_poe_fan_driver = {\n+\t.probe\t\t= rpi_poe_fan_probe,\n+\t.remove\t\t= rpi_poe_fan_remove,\n+\t.driver\t= {\n+\t\t.name\t\t= \"rpi-poe-fan\",\n+\t\t.pm\t\t= &rpi_poe_fan_pm,\n+\t\t.of_match_table\t= of_rpi_poe_fan_match,\n+\t},\n+};\n+\n+module_platform_driver(rpi_poe_fan_driver);\n+\n+MODULE_AUTHOR(\"Serge Schneider <serge@raspberrypi.org>\");\n+MODULE_ALIAS(\"platform:rpi-poe-fan\");\n+MODULE_DESCRIPTION(\"Raspberry Pi PoE HAT fan driver\");\n+MODULE_LICENSE(\"GPL\");\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0085-cxd2880-CXD2880_SPI_DRV-should-select-DVB_CXD2880-wi.patch",
    "content": "From 5156d25449f1a76a72be090a595ee7e25cb74bc6 Mon Sep 17 00:00:00 2001\nFrom: popcornmix <popcornmix@gmail.com>\nDate: Mon, 17 Sep 2018 17:31:18 +0100\nSubject: [PATCH] cxd2880: CXD2880_SPI_DRV should select DVB_CXD2880\n with MEDIA_SUBDRV_AUTOSELECT\n\n---\n drivers/media/spi/Kconfig | 1 +\n 1 file changed, 1 insertion(+)\n\n--- a/drivers/media/spi/Kconfig\n+++ b/drivers/media/spi/Kconfig\n@@ -25,6 +25,7 @@ menu \"Media SPI Adapters\"\n config CXD2880_SPI_DRV\n \ttristate \"Sony CXD2880 SPI support\"\n \tdepends on DVB_CORE && SPI\n+\tselect DVB_CXD2880 if MEDIA_SUBDRV_AUTOSELECT\n \tdefault m if !MEDIA_SUBDRV_AUTOSELECT\n \thelp\n \t  Choose if you would like to have SPI interface support for Sony CXD2880.\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0086-hwmon-raspberrypi-Prevent-voltage-low-warnings-from-.patch",
    "content": "From f6e40957774cd71b4a8ce2190d94ef8e9b289938 Mon Sep 17 00:00:00 2001\nFrom: Stefan Wahren <stefan.wahren@i2se.com>\nDate: Sat, 6 Oct 2018 16:46:18 +0200\nSubject: [PATCH] hwmon: raspberrypi: Prevent voltage low warnings from\n filling log\n\nAlthough the correct fix for low voltage warnings is to\nimprove the power supply, the current implementation\nof the detection can fill the log if the warning\nhappens freqently. This replaces the logging with\nslightly custom ratelimited logging.\n\nSigned-off-by: James Hughes <james.hughes@raspberrypi.org>\nSigned-off-by: Stefan Wahren <stefan.wahren@i2se.com>\n---\n drivers/hwmon/raspberrypi-hwmon.c | 41 ++++++++++++++++++++++++++++---\n 1 file changed, 37 insertions(+), 4 deletions(-)\n\n--- a/drivers/hwmon/raspberrypi-hwmon.c\n+++ b/drivers/hwmon/raspberrypi-hwmon.c\n@@ -15,6 +15,36 @@\n #include <linux/workqueue.h>\n #include <soc/bcm2835/raspberrypi-firmware.h>\n \n+/*\n+ * This section defines some rate limited logging that prevent\n+ * repeated messages at much lower Hz than the default kernel settings.\n+ * It's usually 5s, this is 5 minutes.\n+ * Burst 3 means you may get three messages 'quickly', before\n+ * the ratelimiting kicks in.\n+ */\n+#define LOCAL_RATELIMIT_INTERVAL (5 * 60 * HZ)\n+#define LOCAL_RATELIMIT_BURST 3\n+\n+#ifdef CONFIG_PRINTK\n+#define printk_ratelimited_local(fmt, ...)\t\\\n+({\t\t\t\t\t\t\\\n+\tstatic DEFINE_RATELIMIT_STATE(_rs,\t\\\n+\t\tLOCAL_RATELIMIT_INTERVAL,\t\\\n+\t\tLOCAL_RATELIMIT_BURST);\t\t\\\n+\t\t\t\t\t\t\\\n+\tif (__ratelimit(&_rs))\t\t\t\\\n+\t\tprintk(fmt, ##__VA_ARGS__);\t\\\n+})\n+#else\n+#define printk_ratelimited_local(fmt, ...)\t\\\n+\tno_printk(fmt, ##__VA_ARGS__)\n+#endif\n+\n+#define pr_crit_ratelimited_local(fmt, ...)              \\\n+\tprintk_ratelimited_local(KERN_CRIT pr_fmt(fmt), ##__VA_ARGS__)\n+#define pr_info_ratelimited_local(fmt, ...)              \\\n+printk_ratelimited_local(KERN_INFO pr_fmt(fmt), ##__VA_ARGS__)\n+\n #define UNDERVOLTAGE_STICKY_BIT\tBIT(16)\n \n struct rpi_hwmon_data {\n@@ -47,10 +77,13 @@ static void rpi_firmware_get_throttled(s\n \tif (new_uv == old_uv)\n \t\treturn;\n \n-\tif (new_uv)\n-\t\tdev_crit(data->hwmon_dev, \"Undervoltage detected!\\n\");\n-\telse\n-\t\tdev_info(data->hwmon_dev, \"Voltage normalised\\n\");\n+\tif (new_uv) {\n+\t\tpr_crit_ratelimited_local(\"Under-voltage detected! (0x%08x)\\n\",\n+\t\t\t\t\t  value);\n+\t} else {\n+\t\tpr_info_ratelimited_local(\"Voltage normalised (0x%08x)\\n\",\n+\t\t\t\t\t  value);\n+\t}\n \n \tsysfs_notify(&data->hwmon_dev->kobj, NULL, \"in0_lcrit_alarm\");\n }\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0087-firmware-raspberrypi-Add-backward-compatible-get_thr.patch",
    "content": "From 1910584831fe065c50efc3c07b8ea08ff90e6f31 Mon Sep 17 00:00:00 2001\nFrom: Stefan Wahren <stefan.wahren@i2se.com>\nDate: Sat, 13 Oct 2018 13:31:21 +0200\nSubject: [PATCH] firmware: raspberrypi: Add backward compatible\n get_throttled\n\nAvoid a hard userspace ABI change by adding a compatible get_throttled\nsysfs entry. Its value is now feed by the GET_THROTTLED requests of the\nnew hwmon driver. The first access to get_throttled will generate\na warning.\n\nSigned-off-by: Stefan Wahren <stefan.wahren@i2se.com>\n---\n drivers/firmware/raspberrypi.c | 33 +++++++++++++++++++++++++++++++++\n 1 file changed, 33 insertions(+)\n\n--- a/drivers/firmware/raspberrypi.c\n+++ b/drivers/firmware/raspberrypi.c\n@@ -29,6 +29,7 @@ struct rpi_firmware {\n \tstruct mbox_chan *chan; /* The property channel. */\n \tstruct completion c;\n \tu32 enabled;\n+\tu32 get_throttled;\n \n \tstruct kref consumers;\n };\n@@ -177,6 +178,12 @@ int rpi_firmware_property(struct rpi_fir\n \n \tkfree(data);\n \n+\tif ((tag == RPI_FIRMWARE_GET_THROTTLED) &&\n+\t     memcmp(&fw->get_throttled, tag_data, sizeof(fw->get_throttled))) {\n+\t\tmemcpy(&fw->get_throttled, tag_data, sizeof(fw->get_throttled));\n+\t\tsysfs_notify(&fw->cl.dev->kobj, NULL, \"get_throttled\");\n+\t}\n+\n \treturn ret;\n }\n EXPORT_SYMBOL_GPL(rpi_firmware_property);\n@@ -201,6 +208,27 @@ static int rpi_firmware_notify_reboot(st\n \treturn 0;\n }\n \n+static ssize_t get_throttled_show(struct device *dev,\n+\t\t\t\t  struct device_attribute *attr, char *buf)\n+{\n+\tstruct rpi_firmware *fw = dev_get_drvdata(dev);\n+\n+\tWARN_ONCE(1, \"deprecated, use hwmon sysfs instead\\n\");\n+\n+\treturn sprintf(buf, \"%x\\n\", fw->get_throttled);\n+}\n+\n+static DEVICE_ATTR_RO(get_throttled);\n+\n+static struct attribute *rpi_firmware_dev_attrs[] = {\n+\t&dev_attr_get_throttled.attr,\n+\tNULL,\n+};\n+\n+static const struct attribute_group rpi_firmware_dev_group = {\n+\t.attrs = rpi_firmware_dev_attrs,\n+};\n+\n static void\n rpi_firmware_print_firmware_revision(struct rpi_firmware *fw)\n {\n@@ -230,6 +258,11 @@ rpi_register_hwmon_driver(struct device\n \n \trpi_hwmon = platform_device_register_data(dev, \"raspberrypi-hwmon\",\n \t\t\t\t\t\t  -1, NULL, 0);\n+\n+\tif (!IS_ERR_OR_NULL(rpi_hwmon)) {\n+\t\tif (devm_device_add_group(dev, &rpi_firmware_dev_group))\n+\t\t\tdev_err(dev, \"Failed to create get_trottled attr\\n\");\n+\t}\n }\n \n static void rpi_register_clk_driver(struct device *dev)\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0088-sc16is7xx-Don-t-spin-if-no-data-received.patch",
    "content": "From 0041d17ed3cd7e4ffc6168164c6020e5dcf7aeb4 Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.org>\nDate: Tue, 6 Nov 2018 12:57:48 +0000\nSubject: [PATCH] sc16is7xx: Don't spin if no data received\n\nSee: https://github.com/raspberrypi/linux/issues/2676\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.org>\n---\n drivers/tty/serial/sc16is7xx.c | 2 ++\n 1 file changed, 2 insertions(+)\n\n--- a/drivers/tty/serial/sc16is7xx.c\n+++ b/drivers/tty/serial/sc16is7xx.c\n@@ -696,6 +696,8 @@ static bool sc16is7xx_port_irq(struct sc\n \t\t\trxlen = sc16is7xx_port_read(port, SC16IS7XX_RXLVL_REG);\n \t\t\tif (rxlen)\n \t\t\t\tsc16is7xx_handle_rx(port, rxlen, iir);\n+\t\t\telse\n+\t\t\t\treturn false;\n \t\t\tbreak;\n \t\tcase SC16IS7XX_IIR_THRI_SRC:\n \t\t\tsc16is7xx_handle_tx(port);\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0089-drivers-thermal-step_wise-add-support-for-hysteresis.patch",
    "content": "From 61e2e6bc4c30ceca12a917de93ffa9645e4944f7 Mon Sep 17 00:00:00 2001\nFrom: Ram Chandrasekar <rkumbako@codeaurora.org>\nDate: Mon, 7 May 2018 11:54:08 -0600\nSubject: [PATCH] drivers: thermal: step_wise: add support for\n hysteresis\n\nStep wise governor increases the mitigation level when the temperature\ngoes above a threshold and will decrease the mitigation when the\ntemperature falls below the threshold. If it were a case, where the\ntemperature hovers around a threshold, the mitigation will be applied\nand removed at every iteration. This reaction to the temperature is\ninefficient for performance.\n\nThe use of hysteresis temperature could avoid this ping-pong of\nmitigation by relaxing the mitigation to happen only when the\ntemperature goes below this lower hysteresis value.\n\nSigned-off-by: Ram Chandrasekar <rkumbako@codeaurora.org>\nSigned-off-by: Lina Iyer <ilina@codeaurora.org>\n---\n drivers/thermal/gov_step_wise.c | 33 +++++++++++++++++++++++----------\n 1 file changed, 23 insertions(+), 10 deletions(-)\n\n--- a/drivers/thermal/gov_step_wise.c\n+++ b/drivers/thermal/gov_step_wise.c\n@@ -24,7 +24,7 @@\n  *       for this trip point\n  *    d. if the trend is THERMAL_TREND_DROP_FULL, use lower limit\n  *       for this trip point\n- * If the temperature is lower than a trip point,\n+ * If the temperature is lower than a hysteresis temperature,\n  *    a. if the trend is THERMAL_TREND_RAISING, do nothing\n  *    b. if the trend is THERMAL_TREND_DROPPING, use lower cooling\n  *       state for this trip point, if the cooling state already\n@@ -115,7 +115,7 @@ static void update_passive_instance(stru\n \n static void thermal_zone_trip_update(struct thermal_zone_device *tz, int trip)\n {\n-\tint trip_temp;\n+\tint trip_temp, hyst_temp;\n \tenum thermal_trip_type trip_type;\n \tenum thermal_trend trend;\n \tstruct thermal_instance *instance;\n@@ -123,22 +123,23 @@ static void thermal_zone_trip_update(str\n \tint old_target;\n \n \tif (trip == THERMAL_TRIPS_NONE) {\n-\t\ttrip_temp = tz->forced_passive;\n+\t\thyst_temp = trip_temp = tz->forced_passive;\n \t\ttrip_type = THERMAL_TRIPS_NONE;\n \t} else {\n \t\ttz->ops->get_trip_temp(tz, trip, &trip_temp);\n+\t\thyst_temp = trip_temp;\n+\t\tif (tz->ops->get_trip_hyst) {\n+\t\t\ttz->ops->get_trip_hyst(tz, trip, &hyst_temp);\n+\t\t\thyst_temp = trip_temp - hyst_temp;\n+\t\t}\n \t\ttz->ops->get_trip_type(tz, trip, &trip_type);\n \t}\n \n \ttrend = get_tz_trend(tz, trip);\n \n-\tif (tz->temperature >= trip_temp) {\n-\t\tthrottle = true;\n-\t\ttrace_thermal_zone_trip(tz, trip, trip_type);\n-\t}\n-\n-\tdev_dbg(&tz->device, \"Trip%d[type=%d,temp=%d]:trend=%d,throttle=%d\\n\",\n-\t\t\t\ttrip, trip_type, trip_temp, trend, throttle);\n+\tdev_dbg(&tz->device,\n+\t\t\"Trip%d[type=%d,temp=%d,hyst=%d]:trend=%d,throttle=%d\\n\",\n+\t\ttrip, trip_type, trip_temp, hyst_temp, trend, throttle);\n \n \tmutex_lock(&tz->lock);\n \n@@ -147,6 +148,18 @@ static void thermal_zone_trip_update(str\n \t\t\tcontinue;\n \n \t\told_target = instance->target;\n+\t\tthrottle = false;\n+\t\t/*\n+\t\t * Lower the mitigation only if the temperature\n+\t\t * goes below the hysteresis temperature.\n+\t\t */\n+\t\tif (tz->temperature >= trip_temp ||\n+\t\t   (tz->temperature >= hyst_temp &&\n+\t\t   old_target != THERMAL_NO_TARGET)) {\n+\t\t\tthrottle = true;\n+\t\t\ttrace_thermal_zone_trip(tz, trip, trip_type);\n+\t\t}\n+\n \t\tinstance->target = get_target_state(instance, trend, throttle);\n \t\tdev_dbg(&instance->cdev->device, \"old_target=%d, target=%d\\n\",\n \t\t\t\t\told_target, (int)instance->target);\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0090-drivers-thermal-step_wise-avoid-throttling-at-hyster.patch",
    "content": "From f220efa380854e2423a47f26acde9355ae016ea3 Mon Sep 17 00:00:00 2001\nFrom: Serge Schneider <serge@raspberrypi.org>\nDate: Tue, 2 Oct 2018 11:14:15 +0100\nSubject: [PATCH] drivers: thermal: step_wise: avoid throttling at\n hysteresis temperature after dropping below it\n\nSigned-off-by: Serge Schneider <serge@raspberrypi.org>\n---\n drivers/thermal/gov_step_wise.c | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/drivers/thermal/gov_step_wise.c\n+++ b/drivers/thermal/gov_step_wise.c\n@@ -155,7 +155,7 @@ static void thermal_zone_trip_update(str\n \t\t */\n \t\tif (tz->temperature >= trip_temp ||\n \t\t   (tz->temperature >= hyst_temp &&\n-\t\t   old_target != THERMAL_NO_TARGET)) {\n+\t\t   old_target == instance->upper)) {\n \t\t\tthrottle = true;\n \t\t\ttrace_thermal_zone_trip(tz, trip, trip_type);\n \t\t}\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0091-Update-issue-templates-2736.patch",
    "content": "From 87b9a65d3f7102400bff69dcc692d238fe1d6203 Mon Sep 17 00:00:00 2001\nFrom: James Hughes <JamesH65@users.noreply.github.com>\nDate: Fri, 2 Nov 2018 11:55:49 +0000\nSubject: [PATCH] Update issue templates (#2736)\n\n---\n .github/ISSUE_TEMPLATE/bug_report.md | 34 ++++++++++++++++++++++++++++\n 1 file changed, 34 insertions(+)\n create mode 100644 .github/ISSUE_TEMPLATE/bug_report.md\n\n--- /dev/null\n+++ b/.github/ISSUE_TEMPLATE/bug_report.md\n@@ -0,0 +1,34 @@\n+---\n+name: Bug report\n+about: Create a report to help us fix your issue\n+\n+---\n+\n+**Is this the right place for my bug report?**\n+This repository contains the Linux kernel used on the Raspberry Pi. If you believe that the issue you are seeing is kernel-related, this is the right place. If not, we have other repositories for the GPU firmware at [github.com/raspberrypi/firmware](https://github.com/raspberrypi/firmware) and Raspberry Pi userland applications at [github.com/raspberrypi/userland](https://github.com/raspberrypi/userland). If you have problems with the Raspbian distribution packages, report them in the [github.com/RPi-Distro/repo](https://github.com/RPi-Distro/repo). If you simply have a question, then [the Raspberry Pi forums](https://www.raspberrypi.org/forums) are the best place to ask it.\n+\n+**Describe the bug**\n+Add a clear and concise description of what you think the bug is.\n+\n+**To reproduce**\n+List the steps required to reproduce the issue.\n+\n+**Expected behaviour**\n+Add a clear and concise description of what you expected to happen.\n+\n+**Actual behaviour**\n+Add a clear and concise description of what actually happened.\n+\n+**System**\n+ Copy and paste the results of the raspinfo command in to this section. Alternatively, copy and paste a pastebin link, or add answers to the following questions:\n+\n+* Which model of Raspberry Pi? e.g. Pi3B+, PiZeroW\n+* Which OS and version (`cat /etc/rpi-issue`)?\n+* Which firmware version (`vcgencmd version`)?\n+* Which kernel version (`uname -a`)?\n+\n+**Logs**\n+If applicable, add the relevant output from `dmesg` or similar.\n+\n+**Additional context**\n+Add any other relevant context for the problem.\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0092-net-lan78xx-Support-auto-downshift-to-100Mb-s.patch",
    "content": "From cbc38ebf8ff6d01cd11270d99762d4216ff4237d Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.org>\nDate: Mon, 26 Nov 2018 19:46:58 +0000\nSubject: [PATCH] net: lan78xx: Support auto-downshift to 100Mb/s\n\nEthernet cables with faulty or missing pairs (specifically pairs C and\nD) allow auto-negotiation to 1000Mbs, but do not support the successful\nestablishment of a link. Add a DT property, \"microchip,downshift-after\",\nto configure the number of auto-negotiation failures after which it\nfalls back to 100Mbs. Valid values are 2, 3, 4, 5 and 0, where 0 means\nnever downshift.\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.org>\n---\n .../bindings/net/microchip,lan78xx.txt        |  3 +++\n drivers/net/phy/microchip.c                   | 27 +++++++++++++++++++\n include/linux/microchipphy.h                  |  8 ++++++\n 3 files changed, 38 insertions(+)\n\n--- a/Documentation/devicetree/bindings/net/microchip,lan78xx.txt\n+++ b/Documentation/devicetree/bindings/net/microchip,lan78xx.txt\n@@ -14,6 +14,9 @@ Optional properties of the embedded PHY:\n - microchip,led-modes: a 0..4 element vector, with each element configuring\n   the operating mode of an LED. Omitted LEDs are turned off. Allowed values\n   are defined in \"include/dt-bindings/net/microchip-lan78xx.h\".\n+- microchip,downshift-after: sets the number of failed auto-negotiation\n+  attempts after which the link is downgraded from 1000BASE-T. Should be one of\n+  2, 3, 4, 5 or 0, where 0 means never downshift.\n \n Example:\n \n--- a/drivers/net/phy/microchip.c\n+++ b/drivers/net/phy/microchip.c\n@@ -217,6 +217,7 @@ static int lan88xx_probe(struct phy_devi\n \tstruct device *dev = &phydev->mdio.dev;\n \tstruct lan88xx_priv *priv;\n \tu32 led_modes[4];\n+\tu32 downshift_after = 0;\n \tint len;\n \n \tpriv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);\n@@ -246,6 +247,32 @@ static int lan88xx_probe(struct phy_devi\n \t\treturn -EINVAL;\n \t}\n \n+\tif (!of_property_read_u32(dev->of_node,\n+\t\t\t\t  \"microchip,downshift-after\",\n+\t\t\t\t  &downshift_after)) {\n+\t\tu32 mask = LAN78XX_PHY_CTRL3_DOWNSHIFT_CTRL_MASK;\n+\t\tu32 val= LAN78XX_PHY_CTRL3_AUTO_DOWNSHIFT;\n+\n+\t\tswitch (downshift_after) {\n+\t\tcase 2:\tval |= LAN78XX_PHY_CTRL3_DOWNSHIFT_CTRL_2;\n+\t\t\tbreak;\n+\t\tcase 3:\tval |= LAN78XX_PHY_CTRL3_DOWNSHIFT_CTRL_3;\n+\t\t\tbreak;\n+\t\tcase 4:\tval |= LAN78XX_PHY_CTRL3_DOWNSHIFT_CTRL_4;\n+\t\t\tbreak;\n+\t\tcase 5:\tval |= LAN78XX_PHY_CTRL3_DOWNSHIFT_CTRL_5;\n+\t\t\tbreak;\n+\t\tcase 0: // Disable completely\n+\t\t\tmask = LAN78XX_PHY_CTRL3_AUTO_DOWNSHIFT;\n+\t\t\tval = 0;\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t\t(void)phy_modify_paged(phydev, 1, LAN78XX_PHY_CTRL3,\n+\t\t\t\t       mask, val);\n+\t}\n+\n \t/* these values can be used to identify internal PHY */\n \tpriv->chip_id = phy_read_mmd(phydev, 3, LAN88XX_MMD3_CHIP_ID);\n \tpriv->chip_rev = phy_read_mmd(phydev, 3, LAN88XX_MMD3_CHIP_REV);\n--- a/include/linux/microchipphy.h\n+++ b/include/linux/microchipphy.h\n@@ -61,6 +61,14 @@\n /* Registers specific to the LAN7800/LAN7850 embedded phy */\n #define LAN78XX_PHY_LED_MODE_SELECT\t\t(0x1D)\n \n+#define LAN78XX_PHY_CTRL3\t\t\t(0x14)\n+#define LAN78XX_PHY_CTRL3_AUTO_DOWNSHIFT\t(0x0010)\n+#define LAN78XX_PHY_CTRL3_DOWNSHIFT_CTRL_MASK\t(0x000c)\n+#define LAN78XX_PHY_CTRL3_DOWNSHIFT_CTRL_2\t(0x0000)\n+#define LAN78XX_PHY_CTRL3_DOWNSHIFT_CTRL_3\t(0x0004)\n+#define LAN78XX_PHY_CTRL3_DOWNSHIFT_CTRL_4\t(0x0008)\n+#define LAN78XX_PHY_CTRL3_DOWNSHIFT_CTRL_5\t(0x000c)\n+\n /* DSP registers */\n #define PHY_ARDENNES_MMD_DEV_3_PHY_CFG\t\t(0x806A)\n #define PHY_ARDENNES_MMD_DEV_3_PHY_CFG_ZD_DLY_EN_\t(0x2000)\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0093-firmware-raspberrypi-Report-the-fw-variant-during-pr.patch",
    "content": "From ab759f3138e5ea798e93003e6ce0ffe66ac2970f Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.org>\nDate: Thu, 10 Jan 2019 17:58:06 +0000\nSubject: [PATCH] firmware: raspberrypi: Report the fw variant during\n probe\n\nThe driver already reported the firmware build date during probe.\nThe mailbox calls have been extended to also report the variant\n 1 = standard start.elf\n 2 = start_x.elf (includes camera stack)\n 3 = start_db.elf (includes assert logging)\n 4 = start_cd.elf (cutdown version for smallest memory footprint).\nLog the variant during probe.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>\n\nfirmware: raspberrypi: Report the fw git hash during probe\n\nThe firmware can now report the git hash from which it was built\nvia the mailbox, so report it during probe.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>\n---\n drivers/firmware/raspberrypi.c             | 40 +++++++++++++++++++++-\n include/soc/bcm2835/raspberrypi-firmware.h |  2 ++\n 2 files changed, 41 insertions(+), 1 deletion(-)\n\n--- a/drivers/firmware/raspberrypi.c\n+++ b/drivers/firmware/raspberrypi.c\n@@ -234,6 +234,15 @@ rpi_firmware_print_firmware_revision(str\n {\n \ttime64_t date_and_time;\n \tu32 packet;\n+\tstatic const char * const variant_strs[] = {\n+\t\t\"unknown\",\n+\t\t\"start\",\n+\t\t\"start_x\",\n+\t\t\"start_db\",\n+\t\t\"start_cd\",\n+\t};\n+\tconst char *variant_str = \"cmd unsupported\";\n+\tu32 variant;\n \tint ret = rpi_firmware_property(fw,\n \t\t\t\t\tRPI_FIRMWARE_GET_FIRMWARE_REVISION,\n \t\t\t\t\t&packet, sizeof(packet));\n@@ -243,7 +252,35 @@ rpi_firmware_print_firmware_revision(str\n \n \t/* This is not compatible with y2038 */\n \tdate_and_time = packet;\n-\tdev_info(fw->cl.dev, \"Attached to firmware from %ptT\\n\", &date_and_time);\n+\n+\tret = rpi_firmware_property(fw, RPI_FIRMWARE_GET_FIRMWARE_VARIANT,\n+\t\t\t\t    &variant, sizeof(variant));\n+\n+\tif (!ret) {\n+\t\tif (variant >= ARRAY_SIZE(variant_strs))\n+\t\t\tvariant = 0;\n+\t\tvariant_str = variant_strs[variant];\n+\t}\n+\n+\tdev_info(fw->cl.dev,\n+\t\t \"Attached to firmware from %ptT, variant %s\\n\",\n+\t\t &date_and_time, variant_str);\n+}\n+\n+static void\n+rpi_firmware_print_firmware_hash(struct rpi_firmware *fw)\n+{\n+\tu32 hash[5];\n+\tint ret = rpi_firmware_property(fw,\n+\t\t\t\t\tRPI_FIRMWARE_GET_FIRMWARE_HASH,\n+\t\t\t\t\thash, sizeof(hash));\n+\n+\tif (ret)\n+\t\treturn;\n+\n+\tdev_info(fw->cl.dev,\n+\t\t \"Firmware hash is %08x%08x%08x%08x%08x\\n\",\n+\t\t hash[0], hash[1], hash[2], hash[3], hash[4]);\n }\n \n static void\n@@ -332,6 +369,7 @@ static int rpi_firmware_probe(struct pla\n \tg_pdev = pdev;\n \n \trpi_firmware_print_firmware_revision(fw);\n+\trpi_firmware_print_firmware_hash(fw);\n \trpi_register_hwmon_driver(dev, fw);\n \trpi_register_clk_driver(dev);\n \n--- a/include/soc/bcm2835/raspberrypi-firmware.h\n+++ b/include/soc/bcm2835/raspberrypi-firmware.h\n@@ -38,6 +38,8 @@ struct rpi_firmware_property_tag_header\n enum rpi_firmware_property_tag {\n \tRPI_FIRMWARE_PROPERTY_END =                           0,\n \tRPI_FIRMWARE_GET_FIRMWARE_REVISION =                  0x00000001,\n+\tRPI_FIRMWARE_GET_FIRMWARE_VARIANT =                   0x00000002,\n+\tRPI_FIRMWARE_GET_FIRMWARE_HASH =                      0x00000003,\n \n \tRPI_FIRMWARE_SET_CURSOR_INFO =                        0x00008010,\n \tRPI_FIRMWARE_SET_CURSOR_STATE =                       0x00008011,\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0094-lan78xx-Debounce-link-events-to-minimize-poll-storm.patch",
    "content": "From a242ba451fd64f0b9f07605ff0d8f6981aa6e955 Mon Sep 17 00:00:00 2001\nFrom: Joshua Emele <jemele@acm.org>\nDate: Wed, 7 Nov 2018 16:07:40 -0800\nSubject: [PATCH] lan78xx: Debounce link events to minimize poll storm\n\nThe bInterval is set to 4 (i.e. 8 microframes => 1ms) and the only bit\nthat the driver pays attention to is \"link was reset\". If there's a\nflapping status bit in that endpoint data, (such as if PHY negotiation\nneeds a few tries to get a stable link) then polling at a slower rate\nwould act as a de-bounce.\n\nSee: https://github.com/raspberrypi/linux/issues/2447\n---\n drivers/net/usb/lan78xx.c | 13 ++++++++++++-\n 1 file changed, 12 insertions(+), 1 deletion(-)\n\n--- a/drivers/net/usb/lan78xx.c\n+++ b/drivers/net/usb/lan78xx.c\n@@ -436,6 +436,11 @@ static bool enable_tso;\n module_param(enable_tso, bool, 0644);\n MODULE_PARM_DESC(enable_tso, \"Enables TCP segmentation offload\");\n \n+#define INT_URB_MICROFRAMES_PER_MS\t8\n+static int int_urb_interval_ms = 8;\n+module_param(int_urb_interval_ms, int, 0);\n+MODULE_PARM_DESC(int_urb_interval_ms, \"Override usb interrupt urb interval\");\n+\n static int lan78xx_read_reg(struct lan78xx_net *dev, u32 index, u32 *data)\n {\n \tu32 *buf = kmalloc(sizeof(u32), GFP_KERNEL);\n@@ -3770,7 +3775,13 @@ static int lan78xx_probe(struct usb_inte\n \tnetdev->max_mtu = MAX_SINGLE_PACKET_SIZE;\n \tnetif_set_gso_max_size(netdev, MAX_SINGLE_PACKET_SIZE - MAX_HEADER);\n \n-\tperiod = ep_intr->desc.bInterval;\n+\tif (int_urb_interval_ms <= 0)\n+\t\tperiod = ep_intr->desc.bInterval;\n+\telse\n+\t\tperiod = int_urb_interval_ms * INT_URB_MICROFRAMES_PER_MS;\n+\n+\tnetif_notice(dev, probe, netdev, \"int urb period %d\\n\", period);\n+\n \tmaxp = usb_maxpacket(dev->udev, dev->pipe_intr, 0);\n \tbuf = kmalloc(maxp, GFP_KERNEL);\n \tif (buf) {\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0095-lan78xx-EEE-support-is-now-a-PHY-property.patch",
    "content": "From b65b1e498059fd4b6299c5327b2fccd002512dba Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.org>\nDate: Tue, 5 Mar 2019 09:51:22 +0000\nSubject: [PATCH] lan78xx: EEE support is now a PHY property\n\nNow that EEE support is a property of the PHY, use the PHY's DT node\nwhen querying the EEE-related properties.\n\nSee: https://github.com/raspberrypi/linux/issues/2882\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.org>\n---\n drivers/net/usb/lan78xx.c | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/drivers/net/usb/lan78xx.c\n+++ b/drivers/net/usb/lan78xx.c\n@@ -2182,7 +2182,7 @@ static int lan78xx_phy_init(struct lan78\n \tmii_adv_to_linkmode_adv_t(fc, mii_adv);\n \tlinkmode_or(phydev->advertising, fc, phydev->advertising);\n \n-\tif (of_property_read_bool(dev->udev->dev.of_node,\n+\tif (of_property_read_bool(phydev->mdio.dev.of_node,\n \t\t\t\t  \"microchip,eee-enabled\")) {\n \t\tstruct ethtool_eee edata;\n \t\tmemset(&edata, 0, sizeof(edata));\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0096-bcm2835-dma-Add-support-for-per-channel-flags.patch",
    "content": "From 1a8d5b7b7503bddd1a78130e2317d16b80fe8cda Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.org>\nDate: Fri, 20 Jul 2018 22:03:41 +0100\nSubject: [PATCH] bcm2835-dma: Add support for per-channel flags\n\nAdd the ability to interpret the high bits of the dreq specifier as\nflags to be included in the DMA_CS register. The motivation for this\nchange is the ability to set the DISDEBUG flag for SD card transfers\nto avoid corruption when using the VPU debugger.\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.org>\n---\n drivers/dma/bcm2835-dma.c | 10 ++++++++--\n 1 file changed, 8 insertions(+), 2 deletions(-)\n\n--- a/drivers/dma/bcm2835-dma.c\n+++ b/drivers/dma/bcm2835-dma.c\n@@ -139,6 +139,10 @@ struct bcm2835_desc {\n #define BCM2835_DMA_S_DREQ\tBIT(10) /* enable SREQ for source */\n #define BCM2835_DMA_S_IGNORE\tBIT(11) /* ignore source reads - read 0 */\n #define BCM2835_DMA_BURST_LENGTH(x) ((x & 15) << 12)\n+#define BCM2835_DMA_CS_FLAGS(x) (x & (BCM2835_DMA_PRIORITY(15) | \\\n+\t\t\t\t      BCM2835_DMA_PANIC_PRIORITY(15) | \\\n+\t\t\t\t      BCM2835_DMA_WAIT_FOR_WRITES | \\\n+\t\t\t\t      BCM2835_DMA_DIS_DEBUG))\n #define BCM2835_DMA_PER_MAP(x)\t((x & 31) << 16) /* REQ source */\n #define BCM2835_DMA_WAIT(x)\t((x & 31) << 21) /* add DMA-wait cycles */\n #define BCM2835_DMA_NO_WIDE_BURSTS BIT(26) /* no 2 beat write bursts */\n@@ -452,7 +456,8 @@ static void bcm2835_dma_start_desc(struc\n \tc->desc = d = to_bcm2835_dma_desc(&vd->tx);\n \n \twritel(d->cb_list[0].paddr, c->chan_base + BCM2835_DMA_ADDR);\n-\twritel(BCM2835_DMA_ACTIVE, c->chan_base + BCM2835_DMA_CS);\n+\twritel(BCM2835_DMA_ACTIVE | BCM2835_DMA_CS_FLAGS(c->dreq),\n+\t       c->chan_base + BCM2835_DMA_CS);\n }\n \n static irqreturn_t bcm2835_dma_callback(int irq, void *data)\n@@ -479,7 +484,8 @@ static irqreturn_t bcm2835_dma_callback(\n \t * if this IRQ handler is threaded.) If the channel is finished, it\n \t * will remain idle despite the ACTIVE flag being set.\n \t */\n-\twritel(BCM2835_DMA_INT | BCM2835_DMA_ACTIVE,\n+\twritel(BCM2835_DMA_INT | BCM2835_DMA_ACTIVE |\n+\t       BCM2835_DMA_CS_FLAGS(c->dreq),\n \t       c->chan_base + BCM2835_DMA_CS);\n \n \td = c->desc;\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0097-rtc-rv3028-Add-backup-switchover-mode-support.patch",
    "content": "From 4aefed16e3964d161d32a4f25db849ac16046b13 Mon Sep 17 00:00:00 2001\nFrom: Phil Howard <phil@gadgetoid.com>\nDate: Fri, 29 Mar 2019 10:53:14 +0000\nSubject: [PATCH] rtc: rv3028: Add backup switchover mode support\n\nSigned-off-by: Phil Howard <phil@pimoroni.com>\n---\n drivers/rtc/rtc-rv3028.c | 17 +++++++++++++++++\n 1 file changed, 17 insertions(+)\n\n--- a/drivers/rtc/rtc-rv3028.c\n+++ b/drivers/rtc/rtc-rv3028.c\n@@ -80,6 +80,7 @@\n \n #define RV3028_BACKUP_TCE\t\tBIT(5)\n #define RV3028_BACKUP_TCR_MASK\t\tGENMASK(1,0)\n+#define RV3028_BACKUP_BSM_MASK\t\t0x0C\n \n #define OFFSET_STEP_PPT\t\t\t953674\n \n@@ -789,6 +790,7 @@ static int rv3028_probe(struct i2c_clien\n \tstruct rv3028_data *rv3028;\n \tint ret, status;\n \tu32 ohms;\n+\tu8 bsm;\n \tstruct nvmem_config nvmem_cfg = {\n \t\t.name = \"rv3028_nvram\",\n \t\t.word_size = 1,\n@@ -860,6 +862,21 @@ static int rv3028_probe(struct i2c_clien\n \tif (ret)\n \t\treturn ret;\n \n+\t/* setup backup switchover mode */\n+\tif (!device_property_read_u8(&client->dev, \"backup-switchover-mode\",\n+\t\t\t\t     &bsm))  {\n+\t\tif (bsm <= 3) {\n+\t\t\tret = regmap_update_bits(rv3028->regmap, RV3028_BACKUP,\n+\t\t\t\tRV3028_BACKUP_BSM_MASK,\n+\t\t\t\t(bsm & 0x03) << 2);\n+\n+\t\t\tif (ret)\n+\t\t\t\treturn ret;\n+\t\t} else {\n+\t\t\tdev_warn(&client->dev, \"invalid backup switchover mode value\\n\");\n+\t\t}\n+\t}\n+\n \t/* setup trickle charger */\n \tif (!device_property_read_u32(&client->dev, \"trickle-resistor-ohms\",\n \t\t\t\t      &ohms)) {\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0098-lan78xx-use-default-alignment-for-rx-buffers.patch",
    "content": "From 4c5342c2a4e2d7fe05d16795e308221b786e862e Mon Sep 17 00:00:00 2001\nFrom: P33M <p33m@github.com>\nDate: Thu, 2 May 2019 11:53:45 +0100\nSubject: [PATCH] lan78xx: use default alignment for rx buffers\n\nThe lan78xx uses a 12-byte hardware rx header, so there is no need\nto allocate SKBs with NET_IP_ALIGN set. Removes alignment faults\nin both dwc_otg and in ipv6 processing.\n---\n drivers/net/usb/lan78xx.c | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/drivers/net/usb/lan78xx.c\n+++ b/drivers/net/usb/lan78xx.c\n@@ -3171,7 +3171,7 @@ static int rx_submit(struct lan78xx_net\n \tsize_t size = dev->rx_urb_size;\n \tint ret = 0;\n \n-\tskb = netdev_alloc_skb_ip_align(dev->net, size);\n+\tskb = netdev_alloc_skb(dev->net, size);\n \tif (!skb) {\n \t\tusb_free_urb(urb);\n \t\treturn -ENOMEM;\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0099-media-ov5647-Add-set_fmt-and-get_fmt-calls.patch",
    "content": "From 3774310df4996e7ce45854ddb47a6cf969295f9d Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.org>\nDate: Wed, 31 Oct 2018 14:55:37 +0000\nSubject: [PATCH] media: ov5647: Add set_fmt and get_fmt calls.\n\nThere's no way to query the subdevice for the supported\nresolutions.\nAdd set_fmt and get_fmt implementations.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>\n---\n drivers/media/i2c/ov5647.c | 22 ++++++++++++++++++++++\n 1 file changed, 22 insertions(+)\n\n--- a/drivers/media/i2c/ov5647.c\n+++ b/drivers/media/i2c/ov5647.c\n@@ -463,8 +463,30 @@ static int ov5647_enum_mbus_code(struct\n \treturn 0;\n }\n \n+static int ov5647_set_get_fmt(struct v4l2_subdev *sd,\n+\t\t\t      struct v4l2_subdev_pad_config *cfg,\n+\t\t\t      struct v4l2_subdev_format *format)\n+{\n+\tstruct v4l2_mbus_framefmt *fmt = &format->format;\n+\n+\tif (format->pad != 0)\n+\t\treturn -EINVAL;\n+\n+\t/* Only one format is supported, so return that */\n+\tmemset(fmt, 0, sizeof(*fmt));\n+\tfmt->code = MEDIA_BUS_FMT_SBGGR8_1X8;\n+\tfmt->colorspace = V4L2_COLORSPACE_SRGB;\n+\tfmt->field = V4L2_FIELD_NONE;\n+\tfmt->width = 640;\n+\tfmt->height = 480;\n+\n+\treturn 0;\n+}\n+\n static const struct v4l2_subdev_pad_ops ov5647_subdev_pad_ops = {\n \t.enum_mbus_code = ov5647_enum_mbus_code,\n+\t.set_fmt =\t  ov5647_set_get_fmt,\n+\t.get_fmt =\t  ov5647_set_get_fmt,\n };\n \n static const struct v4l2_subdev_ops ov5647_subdev_ops = {\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0100-media-ov5647-Add-support-for-PWDN-GPIO.patch",
    "content": "From 4b8d9d9c7f6d8f863669ce97ac299ca542ad6ecc Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.org>\nDate: Wed, 31 Oct 2018 14:56:33 +0000\nSubject: [PATCH] media: ov5647: Add support for PWDN GPIO.\n\nAdd support for an optional GPIO connected to PWDN on the sensor.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>\n---\n drivers/media/i2c/ov5647.c | 28 ++++++++++++++++++++++++++++\n 1 file changed, 28 insertions(+)\n\n--- a/drivers/media/i2c/ov5647.c\n+++ b/drivers/media/i2c/ov5647.c\n@@ -21,6 +21,7 @@\n \n #include <linux/clk.h>\n #include <linux/delay.h>\n+#include <linux/gpio/consumer.h>\n #include <linux/i2c.h>\n #include <linux/init.h>\n #include <linux/io.h>\n@@ -35,6 +36,13 @@\n \n #define SENSOR_NAME \"ov5647\"\n \n+/*\n+ * From the datasheet, \"20ms after PWDN goes low or 20ms after RESETB goes\n+ * high if reset is inserted after PWDN goes high, host can access sensor's\n+ * SCCB to initialize sensor.\"\n+ */\n+#define PWDN_ACTIVE_DELAY_MS\t20\n+\n #define MIPI_CTRL00_CLOCK_LANE_GATE\t\tBIT(5)\n #define MIPI_CTRL00_BUS_IDLE\t\t\tBIT(2)\n #define MIPI_CTRL00_CLOCK_LANE_DISABLE\t\tBIT(0)\n@@ -86,6 +94,7 @@ struct ov5647 {\n \tunsigned int\t\t\theight;\n \tint\t\t\t\tpower_count;\n \tstruct clk\t\t\t*xclk;\n+\tstruct gpio_desc\t\t*pwdn;\n };\n \n static inline struct ov5647 *to_state(struct v4l2_subdev *sd)\n@@ -355,6 +364,11 @@ static int ov5647_sensor_power(struct v4\n \tif (on && !ov5647->power_count)\t{\n \t\tdev_dbg(&client->dev, \"OV5647 power on\\n\");\n \n+\t\tif (ov5647->pwdn) {\n+\t\t\tgpiod_set_value(ov5647->pwdn, 0);\n+\t\t\tmsleep(PWDN_ACTIVE_DELAY_MS);\n+\t\t}\n+\n \t\tret = clk_prepare_enable(ov5647->xclk);\n \t\tif (ret < 0) {\n \t\t\tdev_err(&client->dev, \"clk prepare enable failed\\n\");\n@@ -392,6 +406,8 @@ static int ov5647_sensor_power(struct v4\n \t\t\tdev_dbg(&client->dev, \"soft stby failed\\n\");\n \n \t\tclk_disable_unprepare(ov5647->xclk);\n+\n+\t\tgpiod_set_value(ov5647->pwdn, 1);\n \t}\n \n \t/* Update the power count. */\n@@ -603,6 +619,10 @@ static int ov5647_probe(struct i2c_clien\n \t\treturn -EINVAL;\n \t}\n \n+\t/* Request the power down GPIO asserted */\n+\tsensor->pwdn = devm_gpiod_get_optional(&client->dev, \"pwdn\",\n+\t\t\t\t\t       GPIOD_OUT_HIGH);\n+\n \tmutex_init(&sensor->lock);\n \n \tsd = &sensor->sd;\n@@ -616,7 +636,15 @@ static int ov5647_probe(struct i2c_clien\n \tif (ret < 0)\n \t\tgoto mutex_remove;\n \n+\tif (sensor->pwdn) {\n+\t\tgpiod_set_value(sensor->pwdn, 0);\n+\t\tmsleep(PWDN_ACTIVE_DELAY_MS);\n+\t}\n+\n \tret = ov5647_detect(sd);\n+\n+\tgpiod_set_value(sensor->pwdn, 1);\n+\n \tif (ret < 0)\n \t\tgoto error;\n \n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0101-media-ov5647-Add-support-for-non-continuous-clock-mo.patch",
    "content": "From f8ae99474d8555a30615db821c180a7d56b2e73c Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.org>\nDate: Wed, 31 Oct 2018 14:56:47 +0000\nSubject: [PATCH] media: ov5647: Add support for non-continuous clock\n mode\n\nThe driver was only supporting continuous clock mode\nalthough this was not stated anywhere.\nNon-continuous clock saves a small amount of power and\non some SoCs is easier to interface with.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>\n---\n drivers/media/i2c/ov5647.c | 17 ++++++++++++++---\n 1 file changed, 14 insertions(+), 3 deletions(-)\n\n--- a/drivers/media/i2c/ov5647.c\n+++ b/drivers/media/i2c/ov5647.c\n@@ -44,6 +44,7 @@\n #define PWDN_ACTIVE_DELAY_MS\t20\n \n #define MIPI_CTRL00_CLOCK_LANE_GATE\t\tBIT(5)\n+#define MIPI_CTRL00_LINE_SYNC_ENABLE\t\tBIT(4)\n #define MIPI_CTRL00_BUS_IDLE\t\t\tBIT(2)\n #define MIPI_CTRL00_CLOCK_LANE_DISABLE\t\tBIT(0)\n \n@@ -95,6 +96,7 @@ struct ov5647 {\n \tint\t\t\t\tpower_count;\n \tstruct clk\t\t\t*xclk;\n \tstruct gpio_desc\t\t*pwdn;\n+\tunsigned int\t\t\tflags;\n };\n \n static inline struct ov5647 *to_state(struct v4l2_subdev *sd)\n@@ -269,9 +271,15 @@ static int ov5647_set_virtual_channel(st\n \n static int ov5647_stream_on(struct v4l2_subdev *sd)\n {\n+\tstruct ov5647 *ov5647 = to_state(sd);\n+\tu8 val = MIPI_CTRL00_BUS_IDLE;\n \tint ret;\n \n-\tret = ov5647_write(sd, OV5647_REG_MIPI_CTRL00, MIPI_CTRL00_BUS_IDLE);\n+\tif (ov5647->flags & V4L2_MBUS_CSI2_NONCONTINUOUS_CLOCK)\n+\t\tval |= MIPI_CTRL00_CLOCK_LANE_GATE |\n+\t\t       MIPI_CTRL00_LINE_SYNC_ENABLE;\n+\n+\tret = ov5647_write(sd, OV5647_REG_MIPI_CTRL00, val);\n \tif (ret < 0)\n \t\treturn ret;\n \n@@ -568,7 +576,7 @@ static const struct v4l2_subdev_internal\n \t.open = ov5647_open,\n };\n \n-static int ov5647_parse_dt(struct device_node *np)\n+static int ov5647_parse_dt(struct device_node *np, struct ov5647 *sensor)\n {\n \tstruct v4l2_fwnode_endpoint bus_cfg = { .bus_type = 0 };\n \tstruct device_node *ep;\n@@ -581,6 +589,9 @@ static int ov5647_parse_dt(struct device\n \n \tret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(ep), &bus_cfg);\n \n+\tif (!ret)\n+\t\tsensor->flags = bus_cfg.bus.mipi_csi2.flags;\n+\n \tof_node_put(ep);\n \treturn ret;\n }\n@@ -599,7 +610,7 @@ static int ov5647_probe(struct i2c_clien\n \t\treturn -ENOMEM;\n \n \tif (IS_ENABLED(CONFIG_OF) && np) {\n-\t\tret = ov5647_parse_dt(np);\n+\t\tret = ov5647_parse_dt(np, sensor);\n \t\tif (ret) {\n \t\t\tdev_err(dev, \"DT parsing error: %d\\n\", ret);\n \t\t\treturn ret;\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0102-media-tc358743-Increase-FIFO-level-to-374.patch",
    "content": "From 5dc4761b56cbb0f3aa64e23affd2a65b9b7c350a Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.org>\nDate: Wed, 31 Oct 2018 14:56:59 +0000\nSubject: [PATCH] media: tc358743: Increase FIFO level to 374.\n\nThe existing fixed value of 16 worked for UYVY 720P60 over\n2 lanes at 594MHz, or UYVY 1080P60 over 4 lanes. (RGB888\n1080P60 needs 6 lanes at 594MHz).\nIt doesn't allow for lower resolutions to work as the FIFO\nunderflows.\n\n374 is required for 1080P24-30 UYVY over 2 lanes @ 972Mbit/s, but\n>374 means that the FIFO underflows on 1080P50 UYVY over 2 lanes\n@ 972Mbit/s.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>\n---\n drivers/media/i2c/tc358743.c | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/drivers/media/i2c/tc358743.c\n+++ b/drivers/media/i2c/tc358743.c\n@@ -1950,7 +1950,7 @@ static int tc358743_probe_of(struct tc35\n \tstate->pdata.ddc5v_delay = DDC5V_DELAY_100_MS;\n \tstate->pdata.enable_hdcp = false;\n \t/* A FIFO level of 16 should be enough for 2-lane 720p60 at 594 MHz. */\n-\tstate->pdata.fifo_level = 16;\n+\tstate->pdata.fifo_level = 374;\n \t/*\n \t * The PLL input clock is obtained by dividing refclk by pll_prd.\n \t * It must be between 6 MHz and 40 MHz, lower frequency is better.\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0103-media-tc358743-fix-connected-active-CSI-2-lane-repor.patch",
    "content": "From 5bc5749e4350a09d7b76c84513908f35455b25f1 Mon Sep 17 00:00:00 2001\nFrom: Philipp Zabel <p.zabel@pengutronix.de>\nDate: Thu, 21 Sep 2017 17:30:24 +0200\nSubject: [PATCH] media: tc358743: fix connected/active CSI-2 lane\n reporting\n\ng_mbus_config was supposed to indicate all supported lane numbers, not\nonly the number of those currently in active use. Since the TC358743\ncan dynamically reduce the number of active lanes if the required\nbandwidth allows for it, report all lane numbers up to the connected\nnumber of lanes as supported in pdata mode.\nIn device tree mode, do not report lane count and clock mode at all, as\nthe receiver driver can determine these from the device tree.\n\nTo allow communicating the number of currently active lanes, add a new\nbitfield to the v4l2_mbus_config flags. This is a temporary fix, to be\nused only until a better solution is found.\n\nSigned-off-by: Philipp Zabel <p.zabel@pengutronix.de>\n---\n drivers/media/i2c/tc358743.c  | 14 ++++++++++++--\n include/media/v4l2-mediabus.h |  8 ++++++++\n 2 files changed, 20 insertions(+), 2 deletions(-)\n\n--- a/drivers/media/i2c/tc358743.c\n+++ b/drivers/media/i2c/tc358743.c\n@@ -1609,11 +1609,20 @@ static int tc358743_get_mbus_config(stru\n \t\t\t\t    struct v4l2_mbus_config *cfg)\n {\n \tstruct tc358743_state *state = to_state(sd);\n+\tconst u32 mask = V4L2_MBUS_CSI2_LANE_MASK;\n+\n+\tif (state->csi_lanes_in_use > state->bus.num_data_lanes)\n+\t\treturn -EINVAL;\n \n \tcfg->type = V4L2_MBUS_CSI2_DPHY;\n+\tcfg->flags = (state->csi_lanes_in_use << __ffs(mask)) & mask;\n+\n+\t/* In DT mode, only report the number of active lanes */\n+\tif (sd->dev->of_node)\n+\t\treturn 0;\n \n-\t/* Support for non-continuous CSI-2 clock is missing in the driver */\n-\tcfg->flags = V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;\n+\t/* Support for non-continuous CSI-2 clock is missing in pdate mode */\n+\tcfg->flags |= V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;\n \n \tswitch (state->csi_lanes_in_use) {\n \tcase 1:\n@@ -2056,6 +2065,7 @@ static int tc358743_probe(struct i2c_cli\n \tif (pdata) {\n \t\tstate->pdata = *pdata;\n \t\tstate->bus.flags = V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;\n+\t\tstate->bus.num_data_lanes = 4;\n \t} else {\n \t\terr = tc358743_probe_of(state);\n \t\tif (err == -ENODEV)\n--- a/include/media/v4l2-mediabus.h\n+++ b/include/media/v4l2-mediabus.h\n@@ -92,6 +92,14 @@\n \t\t\t\t\t V4L2_MBUS_CSI2_CHANNEL_1 | \\\n \t\t\t\t\t V4L2_MBUS_CSI2_CHANNEL_2 | \\\n \t\t\t\t\t V4L2_MBUS_CSI2_CHANNEL_3)\n+/*\n+ * Number of lanes in use, 0 == use all available lanes (default)\n+ *\n+ * This is a temporary fix for devices that need to reduce the number of active\n+ * lanes for certain modes, until g_mbus_config() can be replaced with a better\n+ * solution.\n+ */\n+#define V4L2_MBUS_CSI2_LANE_MASK                (0xf << 10)\n \n /**\n  * enum v4l2_mbus_type - media bus type\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0104-media-tc358743-Add-support-for-972Mbit-s-link-freq.patch",
    "content": "From 216cd49e1af96bc615a36cddfad7b5a05e1f7ca2 Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.org>\nDate: Wed, 31 Oct 2018 14:57:21 +0000\nSubject: [PATCH] media: tc358743: Add support for 972Mbit/s link freq.\n\nAdds register setups for running the CSI lanes at 972Mbit/s,\nwhich allows 1080P50 UYVY down 2 lanes.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>\n---\n drivers/media/i2c/tc358743.c | 47 +++++++++++++++++++++++++-----------\n 1 file changed, 33 insertions(+), 14 deletions(-)\n\n--- a/drivers/media/i2c/tc358743.c\n+++ b/drivers/media/i2c/tc358743.c\n@@ -1979,6 +1979,7 @@ static int tc358743_probe_of(struct tc35\n \t/*\n \t * The CSI bps per lane must be between 62.5 Mbps and 1 Gbps.\n \t * The default is 594 Mbps for 4-lane 1080p60 or 2-lane 720p60.\n+\t * 972 Mbps allows 1080P50 UYVY over 2-lane.\n \t */\n \tbps_pr_lane = 2 * endpoint.link_frequencies[0];\n \tif (bps_pr_lane < 62500000U || bps_pr_lane > 1000000000U) {\n@@ -1992,23 +1993,41 @@ static int tc358743_probe_of(struct tc35\n \t\t\t       state->pdata.refclk_hz * state->pdata.pll_prd;\n \n \t/*\n-\t * FIXME: These timings are from REF_02 for 594 Mbps per lane (297 MHz\n-\t * link frequency). In principle it should be possible to calculate\n+\t * FIXME: These timings are from REF_02 for 594 or 972 Mbps per lane\n+\t * (297 MHz or 486 MHz link frequency).\n+\t * In principle it should be possible to calculate\n \t * them based on link frequency and resolution.\n \t */\n-\tif (bps_pr_lane != 594000000U)\n+\tswitch (bps_pr_lane) {\n+\tdefault:\n \t\tdev_warn(dev, \"untested bps per lane: %u bps\\n\", bps_pr_lane);\n-\tstate->pdata.lineinitcnt = 0xe80;\n-\tstate->pdata.lptxtimecnt = 0x003;\n-\t/* tclk-preparecnt: 3, tclk-zerocnt: 20 */\n-\tstate->pdata.tclk_headercnt = 0x1403;\n-\tstate->pdata.tclk_trailcnt = 0x00;\n-\t/* ths-preparecnt: 3, ths-zerocnt: 1 */\n-\tstate->pdata.ths_headercnt = 0x0103;\n-\tstate->pdata.twakeup = 0x4882;\n-\tstate->pdata.tclk_postcnt = 0x008;\n-\tstate->pdata.ths_trailcnt = 0x2;\n-\tstate->pdata.hstxvregcnt = 0;\n+\tcase 594000000U:\n+\t\tstate->pdata.lineinitcnt = 0xe80;\n+\t\tstate->pdata.lptxtimecnt = 0x003;\n+\t\t/* tclk-preparecnt: 3, tclk-zerocnt: 20 */\n+\t\tstate->pdata.tclk_headercnt = 0x1403;\n+\t\tstate->pdata.tclk_trailcnt = 0x00;\n+\t\t/* ths-preparecnt: 3, ths-zerocnt: 1 */\n+\t\tstate->pdata.ths_headercnt = 0x0103;\n+\t\tstate->pdata.twakeup = 0x4882;\n+\t\tstate->pdata.tclk_postcnt = 0x008;\n+\t\tstate->pdata.ths_trailcnt = 0x2;\n+\t\tstate->pdata.hstxvregcnt = 0;\n+\t\tbreak;\n+\tcase 972000000U:\n+\t\tstate->pdata.lineinitcnt = 0x1b58;\n+\t\tstate->pdata.lptxtimecnt = 0x007;\n+\t\t/* tclk-preparecnt: 6, tclk-zerocnt: 40 */\n+\t\tstate->pdata.tclk_headercnt = 0x2806;\n+\t\tstate->pdata.tclk_trailcnt = 0x00;\n+\t\t/* ths-preparecnt: 6, ths-zerocnt: 8 */\n+\t\tstate->pdata.ths_headercnt = 0x0806;\n+\t\tstate->pdata.twakeup = 0x4268;\n+\t\tstate->pdata.tclk_postcnt = 0x008;\n+\t\tstate->pdata.ths_trailcnt = 0x5;\n+\t\tstate->pdata.hstxvregcnt = 0;\n+\t\tbreak;\n+\t}\n \n \tstate->reset_gpio = devm_gpiod_get_optional(dev, \"reset\",\n \t\t\t\t\t\t    GPIOD_OUT_LOW);\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0105-media-tc358743-Check-I2C-succeeded-during-probe.patch",
    "content": "From 58993b47c141a2e0cd57e4b62ae8d07a149a815f Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.org>\nDate: Wed, 31 Oct 2018 14:57:34 +0000\nSubject: [PATCH] media: tc358743: Check I2C succeeded during probe.\n\nThe probe for the TC358743 reads the CHIPID register from\nthe device and compares it to the expected value of 0.\nIf the I2C request fails then that also returns 0, so\nthe driver loads thinking that the device is there.\n\nGenerally I2C communications are reliable so there is\nlimited need to check the return value on every transfer,\ntherefore only amend the one read during probe to check\nfor I2C errors.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>\n---\n drivers/media/i2c/tc358743.c | 27 +++++++++++++++++++++++----\n 1 file changed, 23 insertions(+), 4 deletions(-)\n\n--- a/drivers/media/i2c/tc358743.c\n+++ b/drivers/media/i2c/tc358743.c\n@@ -110,7 +110,7 @@ static inline struct tc358743_state *to_\n \n /* --------------- I2C --------------- */\n \n-static void i2c_rd(struct v4l2_subdev *sd, u16 reg, u8 *values, u32 n)\n+static int i2c_rd(struct v4l2_subdev *sd, u16 reg, u8 *values, u32 n)\n {\n \tstruct tc358743_state *state = to_state(sd);\n \tstruct i2c_client *client = state->i2c_client;\n@@ -136,6 +136,7 @@ static void i2c_rd(struct v4l2_subdev *s\n \t\tv4l2_err(sd, \"%s: reading register 0x%x from 0x%x failed\\n\",\n \t\t\t\t__func__, reg, client->addr);\n \t}\n+\treturn err != ARRAY_SIZE(msgs);\n }\n \n static void i2c_wr(struct v4l2_subdev *sd, u16 reg, u8 *values, u32 n)\n@@ -192,15 +193,24 @@ static void i2c_wr(struct v4l2_subdev *s\n \t}\n }\n \n-static noinline u32 i2c_rdreg(struct v4l2_subdev *sd, u16 reg, u32 n)\n+static noinline u32 i2c_rdreg_err(struct v4l2_subdev *sd, u16 reg, u32 n,\n+\t\t\t\t  int *err)\n {\n+\tint error;\n \t__le32 val = 0;\n \n-\ti2c_rd(sd, reg, (u8 __force *)&val, n);\n+\terror = i2c_rd(sd, reg, (u8 __force *)&val, n);\n+\tif (err)\n+\t\t*err = error;\n \n \treturn le32_to_cpu(val);\n }\n \n+static inline u32 i2c_rdreg(struct v4l2_subdev *sd, u16 reg, u32 n)\n+{\n+\treturn i2c_rdreg_err(sd, reg, n, NULL);\n+}\n+\n static noinline void i2c_wrreg(struct v4l2_subdev *sd, u16 reg, u32 val, u32 n)\n {\n \t__le32 raw = cpu_to_le32(val);\n@@ -229,6 +239,13 @@ static u16 i2c_rd16(struct v4l2_subdev *\n \treturn i2c_rdreg(sd, reg, 2);\n }\n \n+static int i2c_rd16_err(struct v4l2_subdev *sd, u16 reg, u16 *value)\n+{\n+\tint err;\n+\t*value = i2c_rdreg_err(sd, reg, 2, &err);\n+\treturn err;\n+}\n+\n static void i2c_wr16(struct v4l2_subdev *sd, u16 reg, u16 val)\n {\n \ti2c_wrreg(sd, reg, val, 2);\n@@ -2066,6 +2083,7 @@ static int tc358743_probe(struct i2c_cli\n \tstruct tc358743_platform_data *pdata = client->dev.platform_data;\n \tstruct v4l2_subdev *sd;\n \tu16 irq_mask = MASK_HDMI_MSK | MASK_CSI_MSK;\n+\tu16 chipid;\n \tint err;\n \n \tif (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))\n@@ -2098,7 +2116,8 @@ static int tc358743_probe(struct i2c_cli\n \tsd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;\n \n \t/* i2c access */\n-\tif ((i2c_rd16(sd, CHIPID) & MASK_CHIPID) != 0) {\n+\tif (i2c_rd16_err(sd, CHIPID, &chipid) ||\n+\t    (chipid & MASK_CHIPID) != 0) {\n \t\tv4l2_info(sd, \"not a TC358743 on address 0x%x\\n\",\n \t\t\t  client->addr << 1);\n \t\treturn -ENODEV;\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0106-media-adv7180-Default-to-the-first-valid-input.patch",
    "content": "From 461de95d791044faba914125a418cd9141a39f02 Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.org>\nDate: Wed, 31 Oct 2018 14:57:46 +0000\nSubject: [PATCH] media: adv7180: Default to the first valid input\n\nThe hardware default is differential CVBS on AIN1 & 2, which\nisn't very useful.\n\nSelect the first input that is defined as valid for the\nchip variant (typically CVBS_AIN1).\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>\n---\n drivers/media/i2c/adv7180.c | 13 +++++++++++++\n 1 file changed, 13 insertions(+)\n\n--- a/drivers/media/i2c/adv7180.c\n+++ b/drivers/media/i2c/adv7180.c\n@@ -1259,6 +1259,7 @@ static const struct adv7180_chip_info ad\n static int init_device(struct adv7180_state *state)\n {\n \tint ret;\n+\tint i;\n \n \tmutex_lock(&state->mutex);\n \n@@ -1305,6 +1306,18 @@ static int init_device(struct adv7180_st\n \t\t\tgoto out_unlock;\n \t}\n \n+\t/* Select first valid input */\n+\tfor (i = 0; i < 32; i++) {\n+\t\tif (BIT(i) & state->chip_info->valid_input_mask) {\n+\t\t\tret = state->chip_info->select_input(state, i);\n+\n+\t\t\tif (ret == 0) {\n+\t\t\t\tstate->input = i;\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t}\n+\t}\n+\n out_unlock:\n \tmutex_unlock(&state->mutex);\n \n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0107-media-adv7180-Add-YPrPb-support-for-ADV7282M.patch",
    "content": "From befd41654ff575e9ceb699ed03d1b893bbe88867 Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.org>\nDate: Wed, 31 Oct 2018 14:57:56 +0000\nSubject: [PATCH] media: adv7180: Add YPrPb support for ADV7282M\n\nThe ADV7282M can support YPbPr on AIN1-3, but this was\nnot selectable from the driver. Add it to the list of\nsupported input modes.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>\n---\n drivers/media/i2c/adv7180.c | 1 +\n 1 file changed, 1 insertion(+)\n\n--- a/drivers/media/i2c/adv7180.c\n+++ b/drivers/media/i2c/adv7180.c\n@@ -1248,6 +1248,7 @@ static const struct adv7180_chip_info ad\n \t\tBIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |\n \t\tBIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) |\n \t\tBIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) |\n+\t\tBIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3) |\n \t\tBIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) |\n \t\tBIT(ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4) |\n \t\tBIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8),\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0108-media-videodev2-Add-helper-defines-for-printing-FOUR.patch",
    "content": "From 460f1e1402d28105f9f3d6e8b8739dcd89bff18e Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.org>\nDate: Wed, 31 Oct 2018 14:58:08 +0000\nSubject: [PATCH] media: videodev2: Add helper defines for printing\n FOURCCs\n\nNew helper defines that allow printing of a FOURCC using\nprintf(V4L2_FOURCC_CONV, V4L2_FOURCC_CONV_ARGS(fourcc));\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>\n---\n include/uapi/linux/videodev2.h | 5 +++++\n 1 file changed, 5 insertions(+)\n\n--- a/include/uapi/linux/videodev2.h\n+++ b/include/uapi/linux/videodev2.h\n@@ -82,6 +82,11 @@\n \t((__u32)(a) | ((__u32)(b) << 8) | ((__u32)(c) << 16) | ((__u32)(d) << 24))\n #define v4l2_fourcc_be(a, b, c, d)\t(v4l2_fourcc(a, b, c, d) | (1U << 31))\n \n+#define V4L2_FOURCC_CONV \"%c%c%c%c%s\"\n+#define V4L2_FOURCC_CONV_ARGS(fourcc) \\\n+\t(fourcc) & 0x7f, ((fourcc) >> 8) & 0x7f, ((fourcc) >> 16) & 0x7f, \\\n+\t((fourcc) >> 24) & 0x7f, (fourcc) & BIT(31) ? \"-BE\" : \"\"\n+\n /*\n  *\tE N U M S\n  */\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0109-dt-bindings-Document-BCM283x-CSI2-CCP2-receiver.patch",
    "content": "From f62b05e593e28e7ed00d25318bd301bb5470de63 Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.org>\nDate: Wed, 31 Oct 2018 14:59:06 +0000\nSubject: [PATCH] dt-bindings: Document BCM283x CSI2/CCP2 receiver\n\nDocument the DT bindings for the CSI2/CCP2 receiver peripheral\n(known as Unicam) on BCM283x SoCs.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>\nAcked-by: Rob Herring <robh@kernel.org>\n---\n .../bindings/media/bcm2835-unicam.txt         | 85 +++++++++++++++++++\n 1 file changed, 85 insertions(+)\n create mode 100644 Documentation/devicetree/bindings/media/bcm2835-unicam.txt\n\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/media/bcm2835-unicam.txt\n@@ -0,0 +1,85 @@\n+Broadcom BCM283x Camera Interface (Unicam)\n+------------------------------------------\n+\n+The Unicam block on BCM283x SoCs is the receiver for either\n+CSI-2 or CCP2 data from image sensors or similar devices.\n+\n+The main platform using this SoC is the Raspberry Pi family of boards.\n+On the Pi the VideoCore firmware can also control this hardware block,\n+and driving it from two different processors will cause issues.\n+To avoid this, the firmware checks the device tree configuration\n+during boot. If it finds device tree nodes called csi0 or csi1 then\n+it will stop the firmware accessing the block, and it can then\n+safely be used via the device tree binding.\n+\n+Required properties:\n+===================\n+- compatible\t: must be \"brcm,bcm2835-unicam\".\n+- reg\t\t: physical base address and length of the register sets for the\n+\t\t  device.\n+- interrupts\t: should contain the IRQ line for this Unicam instance.\n+- clocks\t: list of clock specifiers, corresponding to entries in\n+\t\t  clock-names property.\n+- clock-names\t: must contain an \"lp\" entry, matching entries in the\n+\t\t  clocks property.\n+\n+Unicam supports a single port node. It should contain one 'port' child node\n+with child 'endpoint' node. Please refer to the bindings defined in\n+Documentation/devicetree/bindings/media/video-interfaces.txt.\n+\n+Within the endpoint node the \"remote-endpoint\" and \"data-lanes\" properties\n+are mandatory.\n+Data lane reordering is not supported so the data lanes must be in order,\n+starting at 1. The number of data lanes should represent the number of\n+usable lanes for the hardware block. That may be limited by either the SoC or\n+how the platform presents the interface, and the lower value must be used.\n+\n+Lane reordering is not supported on the clock lane either, so the optional\n+property \"clock-lane\" will implicitly be <0>.\n+Similarly lane inversion is not supported, therefore \"lane-polarities\" will\n+implicitly be <0 0 0 0 0>.\n+Neither of these values will be checked.\n+\n+Example:\n+\tcsi1: csi1@7e801000 {\n+\t\tcompatible = \"brcm,bcm2835-unicam\";\n+\t\treg = <0x7e801000 0x800>,\n+\t\t      <0x7e802004 0x4>;\n+\t\tinterrupts = <2 7>;\n+\t\tclocks = <&clocks BCM2835_CLOCK_CAM1>;\n+\t\tclock-names = \"lp\";\n+\n+\t\tport {\n+\t\t\tcsi1_ep: endpoint {\n+\t\t\t\tremote-endpoint = <&tc358743_0>;\n+\t\t\t\tdata-lanes = <1 2>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\ti2c0: i2c@7e205000 {\n+\t\ttc358743: csi-hdmi-bridge@0f {\n+\t\t\tcompatible = \"toshiba,tc358743\";\n+\t\t\treg = <0x0f>;\n+\n+\t\t\tclocks = <&tc358743_clk>;\n+\t\t\tclock-names = \"refclk\";\n+\n+\t\t\ttc358743_clk: bridge-clk {\n+\t\t\t\tcompatible = \"fixed-clock\";\n+\t\t\t\t#clock-cells = <0>;\n+\t\t\t\tclock-frequency = <27000000>;\n+\t\t\t};\n+\n+\t\t\tport {\n+\t\t\t\ttc358743_0: endpoint {\n+\t\t\t\t\tremote-endpoint = <&csi1_ep>;\n+\t\t\t\t\tclock-lanes = <0>;\n+\t\t\t\t\tdata-lanes = <1 2>;\n+\t\t\t\t\tclock-noncontinuous;\n+\t\t\t\t\tlink-frequencies =\n+\t\t\t\t\t\t/bits/ 64 <297000000>;\n+\t\t\t\t};\n+\t\t\t};\n+\t\t};\n+\t};\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0110-MAINTAINERS-Add-entry-for-BCM2835-Unicam-driver.patch",
    "content": "From cf4ad61eafe94c2d049bf159b61e3a1c71837d2b Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.org>\nDate: Wed, 31 Oct 2018 14:59:40 +0000\nSubject: [PATCH] MAINTAINERS: Add entry for BCM2835 Unicam driver\n\nAdds entry for the new BCM2835 Unicam (CSI-2 receiver) driver\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>\n---\n MAINTAINERS | 7 +++++++\n 1 file changed, 7 insertions(+)\n\n--- a/MAINTAINERS\n+++ b/MAINTAINERS\n@@ -3418,6 +3418,13 @@ N:\tbcm113*\n N:\tbcm216*\n N:\tkona\n \n+BROADCOM BCM2835 CAMERA DRIVER\n+M:\tDave Stevenson <dave.stevenson@raspberrypi.org>\n+L:\tlinux-media@vger.kernel.org\n+S:\tMaintained\n+F:\tdrivers/media/platform/bcm2835/\n+F:\tDocumentation/devicetree/bindings/media/bcm2835-unicam.txt\n+\n BROADCOM BCM47XX MIPS ARCHITECTURE\n M:\tHauke Mehrtens <hauke@hauke-m.de>\n M:\tRafał Miłecki <zajec5@gmail.com>\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0111-media-tc358743-Return-an-appropriate-colorspace-from.patch",
    "content": "From 56feb06d0ad3092abf74957463b7c2023b7f7c95 Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.org>\nDate: Thu, 22 Nov 2018 17:31:06 +0000\nSubject: [PATCH] media: tc358743: Return an appropriate colorspace\n from tc358743_set_fmt\n\nWhen calling tc358743_set_fmt, the code was calling tc358743_get_fmt\nto choose a valid format. However that sets the colorspace\nbased on what was read back from the chip. When you set the format,\nthen the driver would choose and program the colorspace based\non the format code.\n\nThe result was that if you called try or set format for UYVY\nwhen the current format was RGB3 then you would get told sRGB,\nand try RGB3 when current was UYVY and you would get told\nSMPTE170M.\n\nThe value programmed into the chip is determined by this driver,\ntherefore there is no need to read back the value. Return the\ncolorspace based on the format set/tried instead.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>\n---\n drivers/media/i2c/tc358743.c | 40 +++++++++++++-----------------------\n 1 file changed, 14 insertions(+), 26 deletions(-)\n\n--- a/drivers/media/i2c/tc358743.c\n+++ b/drivers/media/i2c/tc358743.c\n@@ -1691,12 +1691,23 @@ static int tc358743_enum_mbus_code(struc\n \treturn 0;\n }\n \n+static u32 tc358743_g_colorspace(u32 code)\n+{\n+\tswitch (code) {\n+\tcase MEDIA_BUS_FMT_RGB888_1X24:\n+\t\treturn V4L2_COLORSPACE_SRGB;\n+\tcase MEDIA_BUS_FMT_UYVY8_1X16:\n+\t\treturn V4L2_COLORSPACE_SMPTE170M;\n+\tdefault:\n+\t\treturn 0;\n+\t}\n+}\n+\n static int tc358743_get_fmt(struct v4l2_subdev *sd,\n \t\tstruct v4l2_subdev_pad_config *cfg,\n \t\tstruct v4l2_subdev_format *format)\n {\n \tstruct tc358743_state *state = to_state(sd);\n-\tu8 vi_rep = i2c_rd8(sd, VI_REP);\n \n \tif (format->pad != 0)\n \t\treturn -EINVAL;\n@@ -1706,23 +1717,7 @@ static int tc358743_get_fmt(struct v4l2_\n \tformat->format.height = state->timings.bt.height;\n \tformat->format.field = V4L2_FIELD_NONE;\n \n-\tswitch (vi_rep & MASK_VOUT_COLOR_SEL) {\n-\tcase MASK_VOUT_COLOR_RGB_FULL:\n-\tcase MASK_VOUT_COLOR_RGB_LIMITED:\n-\t\tformat->format.colorspace = V4L2_COLORSPACE_SRGB;\n-\t\tbreak;\n-\tcase MASK_VOUT_COLOR_601_YCBCR_LIMITED:\n-\tcase MASK_VOUT_COLOR_601_YCBCR_FULL:\n-\t\tformat->format.colorspace = V4L2_COLORSPACE_SMPTE170M;\n-\t\tbreak;\n-\tcase MASK_VOUT_COLOR_709_YCBCR_FULL:\n-\tcase MASK_VOUT_COLOR_709_YCBCR_LIMITED:\n-\t\tformat->format.colorspace = V4L2_COLORSPACE_REC709;\n-\t\tbreak;\n-\tdefault:\n-\t\tformat->format.colorspace = 0;\n-\t\tbreak;\n-\t}\n+\tformat->format.colorspace = tc358743_g_colorspace(format->format.code);\n \n \treturn 0;\n }\n@@ -1737,18 +1732,11 @@ static int tc358743_set_fmt(struct v4l2_\n \tint ret = tc358743_get_fmt(sd, cfg, format);\n \n \tformat->format.code = code;\n+\tformat->format.colorspace = tc358743_g_colorspace(code);\n \n \tif (ret)\n \t\treturn ret;\n \n-\tswitch (code) {\n-\tcase MEDIA_BUS_FMT_RGB888_1X24:\n-\tcase MEDIA_BUS_FMT_UYVY8_1X16:\n-\t\tbreak;\n-\tdefault:\n-\t\treturn -EINVAL;\n-\t}\n-\n \tif (format->which == V4L2_SUBDEV_FORMAT_TRY)\n \t\treturn 0;\n \n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0112-staging-mmal-vchiq-Avoid-use-of-bool-in-structures.patch",
    "content": "From ec20cd708f7497a77d8832d5e043214b1a414f94 Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.org>\nDate: Mon, 29 Oct 2018 16:20:46 +0000\nSubject: [PATCH] staging: mmal-vchiq: Avoid use of bool in structures\n\nFixes up a checkpatch error \"Avoid using bool structure members\nbecause of possible alignment issues\".\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>\n---\n drivers/staging/vc04_services/vchiq-mmal/mmal-vchiq.c | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/drivers/staging/vc04_services/vchiq-mmal/mmal-vchiq.c\n+++ b/drivers/staging/vc04_services/vchiq-mmal/mmal-vchiq.c\n@@ -1775,7 +1775,7 @@ int vchiq_mmal_component_enable(struct v\n \n \tret = enable_component(instance, component);\n \tif (ret == 0)\n-\t\tcomponent->enabled = true;\n+\t\tcomponent->enabled = 1;\n \n \tmutex_unlock(&instance->vchiq_mutex);\n \n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0113-staging-mmal-vchiq-Add-support-for-event-callbacks.patch",
    "content": "From 9db03c416d385ff601211212e0233a8cf3f42812 Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.org>\nDate: Mon, 24 Sep 2018 18:15:38 +0100\nSubject: [PATCH] staging: mmal-vchiq: Add support for event callbacks.\n\n(Preparation for the codec driver).\nThe codec uses the event mechanism to report things such as\nresolution changes. It is signalled by the cmd field of the buffer\nbeing non-zero.\n\nAdd support for passing this information out to the client.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>\n---\n .../vc04_services/vchiq-mmal/mmal-common.h    |   1 +\n .../vc04_services/vchiq-mmal/mmal-msg.h       |  35 ++++\n .../vc04_services/vchiq-mmal/mmal-vchiq.c     | 170 ++++++++++++++++--\n .../vc04_services/vchiq-mmal/mmal-vchiq.h     |   4 +\n 4 files changed, 196 insertions(+), 14 deletions(-)\n\n--- a/drivers/staging/vc04_services/vchiq-mmal/mmal-common.h\n+++ b/drivers/staging/vc04_services/vchiq-mmal/mmal-common.h\n@@ -50,6 +50,7 @@ struct mmal_buffer {\n \n \tstruct mmal_msg_context *msg_context;\n \n+\tu32 cmd;\t\t/* MMAL command. 0=data. */\n \tunsigned long length;\n \tu32 mmal_flags;\n \ts64 dts;\n--- a/drivers/staging/vc04_services/vchiq-mmal/mmal-msg.h\n+++ b/drivers/staging/vc04_services/vchiq-mmal/mmal-msg.h\n@@ -346,6 +346,41 @@ struct mmal_msg_port_parameter_get_reply\n /* event messages */\n #define MMAL_WORKER_EVENT_SPACE 256\n \n+/* Four CC's for events */\n+#define MMAL_FOURCC(a, b, c, d) ((a) | (b << 8) | (c << 16) | (d << 24))\n+\n+#define MMAL_EVENT_ERROR\t\tMMAL_FOURCC('E', 'R', 'R', 'O')\n+#define MMAL_EVENT_EOS\t\t\tMMAL_FOURCC('E', 'E', 'O', 'S')\n+#define MMAL_EVENT_FORMAT_CHANGED\tMMAL_FOURCC('E', 'F', 'C', 'H')\n+#define MMAL_EVENT_PARAMETER_CHANGED\tMMAL_FOURCC('E', 'P', 'C', 'H')\n+\n+/* Structs for each of the event message payloads */\n+struct mmal_msg_event_eos {\n+\tu32 port_type;\t/**< Type of port that received the end of stream */\n+\tu32 port_index;\t/**< Index of port that received the end of stream */\n+};\n+\n+/** Format changed event data. */\n+struct mmal_msg_event_format_changed {\n+\t/* Minimum size of buffers the port requires */\n+\tu32 buffer_size_min;\n+\t/* Minimum number of buffers the port requires */\n+\tu32 buffer_num_min;\n+\t/* Size of buffers the port recommends for optimal performance.\n+\t * A value of zero means no special recommendation.\n+\t */\n+\tu32 buffer_size_recommended;\n+\t/* Number of buffers the port recommends for optimal\n+\t * performance. A value of zero means no special recommendation.\n+\t */\n+\tu32 buffer_num_recommended;\n+\n+\tu32 es_ptr;\n+\tstruct mmal_es_format format;\n+\tunion mmal_es_specific_format es;\n+\tu8 extradata[MMAL_FORMAT_EXTRADATA_MAX_SIZE];\n+};\n+\n struct mmal_msg_event_to_host {\n \tu32 client_component;\t/* component context */\n \n--- a/drivers/staging/vc04_services/vchiq-mmal/mmal-vchiq.c\n+++ b/drivers/staging/vc04_services/vchiq-mmal/mmal-vchiq.c\n@@ -143,6 +143,8 @@ struct mmal_msg_context {\n \t\t\t/* Presentation and Decode timestamps */\n \t\t\ts64 pts;\n \t\t\ts64 dts;\n+\t\t\t/* MMAL buffer command flag */\n+\t\t\tu32 cmd;\n \n \t\t\tint status;\t/* context status */\n \n@@ -233,18 +235,6 @@ release_msg_context(struct mmal_msg_cont\n \tkfree(msg_context);\n }\n \n-/* deals with receipt of event to host message */\n-static void event_to_host_cb(struct vchiq_mmal_instance *instance,\n-\t\t\t     struct mmal_msg *msg, u32 msg_len)\n-{\n-\tpr_debug(\"unhandled event\\n\");\n-\tpr_debug(\"component:%u port type:%d num:%d cmd:0x%x length:%d\\n\",\n-\t\t msg->u.event_to_host.client_component,\n-\t\t msg->u.event_to_host.port_type,\n-\t\t msg->u.event_to_host.port_num,\n-\t\t msg->u.event_to_host.cmd, msg->u.event_to_host.length);\n-}\n-\n /* workqueue scheduled callback\n  *\n  * we do this because it is important we do not call any other vchiq\n@@ -266,13 +256,18 @@ static void buffer_work_cb(struct work_s\n \tbuffer->mmal_flags = msg_context->u.bulk.mmal_flags;\n \tbuffer->dts = msg_context->u.bulk.dts;\n \tbuffer->pts = msg_context->u.bulk.pts;\n+\tbuffer->cmd = msg_context->u.bulk.cmd;\n \n-\tatomic_dec(&msg_context->u.bulk.port->buffers_with_vpu);\n+\tif (!buffer->cmd)\n+\t\tatomic_dec(&msg_context->u.bulk.port->buffers_with_vpu);\n \n \tmsg_context->u.bulk.port->buffer_cb(msg_context->u.bulk.instance,\n \t\t\t\t\t    msg_context->u.bulk.port,\n \t\t\t\t\t    msg_context->u.bulk.status,\n \t\t\t\t\t    msg_context->u.bulk.buffer);\n+\n+\tif (buffer->cmd)\n+\t\tmutex_unlock(&msg_context->u.bulk.port->event_context_mutex);\n }\n \n /* workqueue scheduled callback to handle receiving buffers\n@@ -350,6 +345,7 @@ static int bulk_receive(struct vchiq_mma\n \tmsg_context->u.bulk.buffer_used = rd_len;\n \tmsg_context->u.bulk.dts = msg->u.buffer_from_host.buffer_header.dts;\n \tmsg_context->u.bulk.pts = msg->u.buffer_from_host.buffer_header.pts;\n+\tmsg_context->u.bulk.cmd = msg->u.buffer_from_host.buffer_header.cmd;\n \n \tqueue_work(msg_context->instance->bulk_wq,\n \t\t   &msg_context->u.bulk.buffer_to_host_work);\n@@ -452,6 +448,103 @@ buffer_from_host(struct vchiq_mmal_insta\n \treturn ret;\n }\n \n+/* deals with receipt of event to host message */\n+static void event_to_host_cb(struct vchiq_mmal_instance *instance,\n+\t\t\t     struct mmal_msg *msg, u32 msg_len)\n+{\n+\t/* FIXME: Not going to work on 64 bit */\n+\tstruct vchiq_mmal_component *component =\n+\t\t(struct vchiq_mmal_component *)msg->u.event_to_host.client_component;\n+\tstruct vchiq_mmal_port *port = NULL;\n+\tstruct mmal_msg_context *msg_context;\n+\tu32 port_num = msg->u.event_to_host.port_num;\n+\n+\tif (msg->u.buffer_from_host.drvbuf.magic == MMAL_MAGIC) {\n+\t\tpr_err(\"%s: MMAL_MSG_TYPE_BUFFER_TO_HOST with bad magic\\n\",\n+\t\t       __func__);\n+\t\treturn;\n+\t}\n+\n+\tswitch (msg->u.event_to_host.port_type) {\n+\tcase MMAL_PORT_TYPE_CONTROL:\n+\t\tif (port_num) {\n+\t\t\tpr_err(\"%s: port_num of %u >= number of ports 1\",\n+\t\t\t       __func__, port_num);\n+\t\t\treturn;\n+\t\t}\n+\t\tport = &component->control;\n+\t\tbreak;\n+\tcase MMAL_PORT_TYPE_INPUT:\n+\t\tif (port_num >= component->inputs) {\n+\t\t\tpr_err(\"%s: port_num of %u >= number of ports %u\",\n+\t\t\t       __func__, port_num,\n+\t\t\t       port_num >= component->inputs);\n+\t\t\treturn;\n+\t\t}\n+\t\tport = &component->input[port_num];\n+\t\tbreak;\n+\tcase MMAL_PORT_TYPE_OUTPUT:\n+\t\tif (port_num >= component->outputs) {\n+\t\t\tpr_err(\"%s: port_num of %u >= number of ports %u\",\n+\t\t\t       __func__, port_num,\n+\t\t\t       port_num >= component->outputs);\n+\t\t\treturn;\n+\t\t}\n+\t\tport = &component->output[port_num];\n+\t\tbreak;\n+\tcase MMAL_PORT_TYPE_CLOCK:\n+\t\tif (port_num >= component->clocks) {\n+\t\t\tpr_err(\"%s: port_num of %u >= number of ports %u\",\n+\t\t\t       __func__, port_num,\n+\t\t\t       port_num >= component->clocks);\n+\t\t\treturn;\n+\t\t}\n+\t\tport = &component->clock[port_num];\n+\t\tbreak;\n+\tdefault:\n+\t\tbreak;\n+\t}\n+\n+\tif (!mutex_trylock(&port->event_context_mutex)) {\n+\t\tpr_err(\"dropping event 0x%x\\n\", msg->u.event_to_host.cmd);\n+\t\treturn;\n+\t}\n+\tmsg_context = port->event_context;\n+\n+\tif (msg->h.status != MMAL_MSG_STATUS_SUCCESS) {\n+\t\t/* message reception had an error */\n+\t\t//pr_warn\n+\t\tpr_err(\"%s: error %d in reply\\n\", __func__, msg->h.status);\n+\n+\t\tmsg_context->u.bulk.status = msg->h.status;\n+\t} else if (msg->u.event_to_host.length > MMAL_WORKER_EVENT_SPACE) {\n+\t\t/* data is not in message, queue a bulk receive */\n+\t\tpr_err(\"%s: payload not in message - bulk receive??! NOT SUPPORTED\\n\",\n+\t\t       __func__);\n+\t\tmsg_context->u.bulk.status = -1;\n+\t} else {\n+\t\tmemcpy(msg_context->u.bulk.buffer->buffer,\n+\t\t       msg->u.event_to_host.data,\n+\t\t       msg->u.event_to_host.length);\n+\n+\t\tmsg_context->u.bulk.buffer_used =\n+\t\t    msg->u.event_to_host.length;\n+\n+\t\tmsg_context->u.bulk.mmal_flags = 0;\n+\t\tmsg_context->u.bulk.dts = MMAL_TIME_UNKNOWN;\n+\t\tmsg_context->u.bulk.pts = MMAL_TIME_UNKNOWN;\n+\t\tmsg_context->u.bulk.cmd = msg->u.event_to_host.cmd;\n+\n+\t\tpr_debug(\"event component:%u port type:%d num:%d cmd:0x%x length:%d\\n\",\n+\t\t\t msg->u.event_to_host.client_component,\n+\t\t\t msg->u.event_to_host.port_type,\n+\t\t\t msg->u.event_to_host.port_num,\n+\t\t\t msg->u.event_to_host.cmd, msg->u.event_to_host.length);\n+\t}\n+\n+\tschedule_work(&msg_context->u.bulk.work);\n+}\n+\n /* deals with receipt of buffer to host message */\n static void buffer_to_host_cb(struct vchiq_mmal_instance *instance,\n \t\t\t      struct mmal_msg *msg, u32 msg_len)\n@@ -1332,6 +1425,7 @@ static int port_disable(struct vchiq_mma\n \t\t\t\tmmalbuf->mmal_flags = 0;\n \t\t\t\tmmalbuf->dts = MMAL_TIME_UNKNOWN;\n \t\t\t\tmmalbuf->pts = MMAL_TIME_UNKNOWN;\n+\t\t\t\tmmalbuf->cmd = 0;\n \t\t\t\tport->buffer_cb(instance,\n \t\t\t\t\t\tport, 0, mmalbuf);\n \t\t\t}\n@@ -1633,6 +1727,43 @@ int mmal_vchi_buffer_cleanup(struct mmal\n }\n EXPORT_SYMBOL_GPL(mmal_vchi_buffer_cleanup);\n \n+static void init_event_context(struct vchiq_mmal_instance *instance,\n+\t\t\t       struct vchiq_mmal_port *port)\n+{\n+\tstruct mmal_msg_context *ctx = get_msg_context(instance);\n+\n+\tmutex_init(&port->event_context_mutex);\n+\n+\tport->event_context = ctx;\n+\tctx->u.bulk.instance = instance;\n+\tctx->u.bulk.port = port;\n+\tctx->u.bulk.buffer =\n+\t\tkzalloc(sizeof(*ctx->u.bulk.buffer), GFP_KERNEL);\n+\tif (!ctx->u.bulk.buffer)\n+\t\tgoto release_msg_context;\n+\tctx->u.bulk.buffer->buffer = kzalloc(MMAL_WORKER_EVENT_SPACE,\n+\t\t\t\t\t     GFP_KERNEL);\n+\tif (!ctx->u.bulk.buffer->buffer)\n+\t\tgoto release_buffer;\n+\n+\tINIT_WORK(&ctx->u.bulk.work, buffer_work_cb);\n+\treturn;\n+\n+release_buffer:\n+\tkfree(ctx->u.bulk.buffer);\n+release_msg_context:\n+\trelease_msg_context(ctx);\n+}\n+\n+static void free_event_context(struct vchiq_mmal_port *port)\n+{\n+\tstruct mmal_msg_context *ctx = port->event_context;\n+\n+\tkfree(ctx->u.bulk.buffer->buffer);\n+\tkfree(ctx->u.bulk.buffer);\n+\trelease_msg_context(ctx);\n+}\n+\n /* Initialise a mmal component and its ports\n  *\n  */\n@@ -1682,6 +1813,7 @@ int vchiq_mmal_component_init(struct vch\n \tret = port_info_get(instance, &component->control);\n \tif (ret < 0)\n \t\tgoto release_component;\n+\tinit_event_context(instance, &component->control);\n \n \tfor (idx = 0; idx < component->inputs; idx++) {\n \t\tcomponent->input[idx].type = MMAL_PORT_TYPE_INPUT;\n@@ -1692,6 +1824,7 @@ int vchiq_mmal_component_init(struct vch\n \t\tret = port_info_get(instance, &component->input[idx]);\n \t\tif (ret < 0)\n \t\t\tgoto release_component;\n+\t\tinit_event_context(instance, &component->input[idx]);\n \t}\n \n \tfor (idx = 0; idx < component->outputs; idx++) {\n@@ -1703,6 +1836,7 @@ int vchiq_mmal_component_init(struct vch\n \t\tret = port_info_get(instance, &component->output[idx]);\n \t\tif (ret < 0)\n \t\t\tgoto release_component;\n+\t\tinit_event_context(instance, &component->output[idx]);\n \t}\n \n \tfor (idx = 0; idx < component->clocks; idx++) {\n@@ -1714,6 +1848,7 @@ int vchiq_mmal_component_init(struct vch\n \t\tret = port_info_get(instance, &component->clock[idx]);\n \t\tif (ret < 0)\n \t\t\tgoto release_component;\n+\t\tinit_event_context(instance, &component->clock[idx]);\n \t}\n \n \t*component_out = component;\n@@ -1739,7 +1874,7 @@ EXPORT_SYMBOL_GPL(vchiq_mmal_component_i\n int vchiq_mmal_component_finalise(struct vchiq_mmal_instance *instance,\n \t\t\t\t  struct vchiq_mmal_component *component)\n {\n-\tint ret;\n+\tint ret, idx;\n \n \tif (mutex_lock_interruptible(&instance->vchiq_mutex))\n \t\treturn -EINTR;\n@@ -1751,6 +1886,13 @@ int vchiq_mmal_component_finalise(struct\n \n \tcomponent->in_use = 0;\n \n+\tfor (idx = 0; idx < component->inputs; idx++)\n+\t\tfree_event_context(&component->input[idx]);\n+\tfor (idx = 0; idx < component->outputs; idx++)\n+\t\tfree_event_context(&component->output[idx]);\n+\tfor (idx = 0; idx < component->clocks; idx++)\n+\t\tfree_event_context(&component->clock[idx]);\n+\n \tmutex_unlock(&instance->vchiq_mutex);\n \n \treturn ret;\n--- a/drivers/staging/vc04_services/vchiq-mmal/mmal-vchiq.h\n+++ b/drivers/staging/vc04_services/vchiq-mmal/mmal-vchiq.h\n@@ -79,6 +79,10 @@ struct vchiq_mmal_port {\n \tvchiq_mmal_buffer_cb buffer_cb;\n \t/* callback context */\n \tvoid *cb_ctx;\n+\n+\t/* ensure serialised use of the one event context structure */\n+\tstruct mutex event_context_mutex;\n+\tstruct mmal_msg_context *event_context;\n };\n \n struct vchiq_mmal_component {\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0114-staging-vc04_services-Support-sending-data-to-MMAL-p.patch",
    "content": "From a15278923fdaa73cdf1bef1ec0f1c973c64dbb43 Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.org>\nDate: Mon, 24 Sep 2018 18:26:02 +0100\nSubject: [PATCH] staging: vc04_services: Support sending data to MMAL\n ports\n\nAdd the ability to send data to ports. This only supports\nzero copy mode as the required bulk transfer setup calls\nare not done.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>\n---\n .../vc04_services/vchiq-mmal/mmal-vchiq.c      | 18 +++++++++++++-----\n 1 file changed, 13 insertions(+), 5 deletions(-)\n\n--- a/drivers/staging/vc04_services/vchiq-mmal/mmal-vchiq.c\n+++ b/drivers/staging/vc04_services/vchiq-mmal/mmal-vchiq.c\n@@ -422,11 +422,19 @@ buffer_from_host(struct vchiq_mmal_insta\n \tm.u.buffer_from_host.buffer_header.data =\n \t\t(u32)(unsigned long)buf->buffer;\n \tm.u.buffer_from_host.buffer_header.alloc_size = buf->buffer_size;\n-\tm.u.buffer_from_host.buffer_header.length = 0;\t/* nothing used yet */\n-\tm.u.buffer_from_host.buffer_header.offset = 0;\t/* no offset */\n-\tm.u.buffer_from_host.buffer_header.flags = 0;\t/* no flags */\n-\tm.u.buffer_from_host.buffer_header.pts = MMAL_TIME_UNKNOWN;\n-\tm.u.buffer_from_host.buffer_header.dts = MMAL_TIME_UNKNOWN;\n+\tif (port->type == MMAL_PORT_TYPE_OUTPUT) {\n+\t\tm.u.buffer_from_host.buffer_header.length = 0;\n+\t\tm.u.buffer_from_host.buffer_header.offset = 0;\n+\t\tm.u.buffer_from_host.buffer_header.flags = 0;\n+\t\tm.u.buffer_from_host.buffer_header.pts = MMAL_TIME_UNKNOWN;\n+\t\tm.u.buffer_from_host.buffer_header.dts = MMAL_TIME_UNKNOWN;\n+\t} else {\n+\t\tm.u.buffer_from_host.buffer_header.length = buf->length;\n+\t\tm.u.buffer_from_host.buffer_header.offset = 0;\n+\t\tm.u.buffer_from_host.buffer_header.flags = buf->mmal_flags;\n+\t\tm.u.buffer_from_host.buffer_header.pts = buf->pts;\n+\t\tm.u.buffer_from_host.buffer_header.dts = buf->dts;\n+\t}\n \n \t/* clear buffer type sepecific data */\n \tmemset(&m.u.buffer_from_host.buffer_header_type_specific, 0,\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0115-media-videobuf2-Allow-exporting-of-a-struct-dmabuf.patch",
    "content": "From 2147f93fd4871833b157834ef708a5b99e8e280b Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.org>\nDate: Mon, 29 Oct 2018 17:57:45 +0000\nSubject: [PATCH] media: videobuf2: Allow exporting of a struct dmabuf\n\nvideobuf2 only allowed exporting a dmabuf as a file descriptor,\nbut there are instances where having the struct dma_buf is\nuseful within the kernel.\n\nSplit the current implementation into two, one step which\nexports a struct dma_buf, and the second which converts that\ninto an fd.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>\n---\n .../media/common/videobuf2/videobuf2-core.c   | 21 ++++++++++++++++---\n include/media/videobuf2-core.h                | 15 +++++++++++++\n 2 files changed, 33 insertions(+), 3 deletions(-)\n\n--- a/drivers/media/common/videobuf2/videobuf2-core.c\n+++ b/drivers/media/common/videobuf2/videobuf2-core.c\n@@ -2140,12 +2140,12 @@ static int __find_plane_by_offset(struct\n \treturn -EINVAL;\n }\n \n-int vb2_core_expbuf(struct vb2_queue *q, int *fd, unsigned int type,\n-\t\tunsigned int index, unsigned int plane, unsigned int flags)\n+int vb2_core_expbuf_dmabuf(struct vb2_queue *q, unsigned int type,\n+\t\t\t   unsigned int index, unsigned int plane,\n+\t\t\t   unsigned int flags, struct dma_buf **dmabuf)\n {\n \tstruct vb2_buffer *vb = NULL;\n \tstruct vb2_plane *vb_plane;\n-\tint ret;\n \tstruct dma_buf *dbuf;\n \n \tif (q->memory != VB2_MEMORY_MMAP) {\n@@ -2195,6 +2195,21 @@ int vb2_core_expbuf(struct vb2_queue *q,\n \t\treturn -EINVAL;\n \t}\n \n+\t*dmabuf = dbuf;\n+\treturn 0;\n+}\n+EXPORT_SYMBOL_GPL(vb2_core_expbuf_dmabuf);\n+\n+int vb2_core_expbuf(struct vb2_queue *q, int *fd, unsigned int type,\n+\t\t    unsigned int index, unsigned int plane, unsigned int flags)\n+{\n+\tstruct dma_buf *dbuf;\n+\tint ret;\n+\n+\tret = vb2_core_expbuf_dmabuf(q, type, index, plane, flags, &dbuf);\n+\tif (ret)\n+\t\treturn ret;\n+\n \tret = dma_buf_fd(dbuf, flags & ~O_ACCMODE);\n \tif (ret < 0) {\n \t\tdprintk(q, 3, \"buffer %d, plane %d failed to export (%d)\\n\",\n--- a/include/media/videobuf2-core.h\n+++ b/include/media/videobuf2-core.h\n@@ -902,6 +902,21 @@ int vb2_core_streamon(struct vb2_queue *\n int vb2_core_streamoff(struct vb2_queue *q, unsigned int type);\n \n /**\n+ * vb2_core_expbuf_dmabuf() - Export a buffer as a dma_buf structure\n+ * @q:         videobuf2 queue\n+ * @type:      buffer type\n+ * @index:     id number of the buffer\n+ * @plane:     index of the plane to be exported, 0 for single plane queues\n+ * @flags:     flags for newly created file, currently only O_CLOEXEC is\n+ *             supported, refer to manual of open syscall for more details\n+ * @dmabuf:    Returns the dmabuf pointer\n+ *\n+ */\n+int vb2_core_expbuf_dmabuf(struct vb2_queue *q, unsigned int type,\n+\t\t\t   unsigned int index, unsigned int plane,\n+\t\t\t   unsigned int flags, struct dma_buf **dmabuf);\n+\n+/**\n  * vb2_core_expbuf() - Export a buffer as a file descriptor.\n  * @q:\t\tpointer to &struct vb2_queue with videobuf2 queue.\n  * @fd:\t\tpointer to the file descriptor associated with DMABUF\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0116-staging-mmal-vchiq-Fix-client_component-for-64-bit-k.patch",
    "content": "From b9154d619c0ae2c8636b9bb3f76fe3daa9dc6d8d Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.org>\nDate: Tue, 22 Jan 2019 12:04:09 +0000\nSubject: [PATCH] staging: mmal-vchiq: Fix client_component for 64 bit\n kernel\n\nThe MMAL client_component field is used with the event\nmechanism to allow the client to identify the component for\nwhich the event is generated.\nThe field is only 32bits in size, therefore we can't use a\npointer to the component in a 64 bit kernel.\n\nComponent handles are already held in an array per VCHI\ninstance, so use the array index as the client_component handle\nto avoid having to create a new IDR for this purpose.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>\n---\n drivers/staging/vc04_services/vchiq-mmal/mmal-vchiq.c | 4 ++--\n 1 file changed, 2 insertions(+), 2 deletions(-)\n\n--- a/drivers/staging/vc04_services/vchiq-mmal/mmal-vchiq.c\n+++ b/drivers/staging/vc04_services/vchiq-mmal/mmal-vchiq.c\n@@ -460,9 +460,9 @@ buffer_from_host(struct vchiq_mmal_insta\n static void event_to_host_cb(struct vchiq_mmal_instance *instance,\n \t\t\t     struct mmal_msg *msg, u32 msg_len)\n {\n-\t/* FIXME: Not going to work on 64 bit */\n+\tint comp_idx = msg->u.event_to_host.client_component;\n \tstruct vchiq_mmal_component *component =\n-\t\t(struct vchiq_mmal_component *)msg->u.event_to_host.client_component;\n+\t\t\t\t\t&instance->component[comp_idx];\n \tstruct vchiq_mmal_port *port = NULL;\n \tstruct mmal_msg_context *msg_context;\n \tu32 port_num = msg->u.event_to_host.port_num;\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0117-clk-clk-bcm2835-Use-zd-when-printing-size_t.patch",
    "content": "From 1ade3c32d515dba5afa50f389d374b19d1b76cdb Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.org>\nDate: Thu, 24 Jan 2019 15:09:28 +0000\nSubject: [PATCH] clk: clk-bcm2835: Use %zd when printing size_t\n\nThe debug text for how many clocks have been registered\nuses \"%d\" with a size_t. Correct it to \"%zd\".\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>\n---\n drivers/clk/bcm/clk-bcm2835.c | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/drivers/clk/bcm/clk-bcm2835.c\n+++ b/drivers/clk/bcm/clk-bcm2835.c\n@@ -2377,7 +2377,7 @@ static int bcm2835_clk_probe(struct plat\n \t\treturn ret;\n \n \t/* note that we have registered all the clocks */\n-\tdev_dbg(dev, \"registered %d clocks\\n\", asize);\n+\tdev_dbg(dev, \"registered %zd clocks\\n\", asize);\n \n \treturn 0;\n }\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0118-media-ov5647-Use-gpiod_set_value_cansleep.patch",
    "content": "From 58f1758adcdbfd1cf556eb3cbb85b88ddcef0840 Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.org>\nDate: Tue, 18 Sep 2018 11:08:51 +0100\nSubject: [PATCH] media: ov5647: Use gpiod_set_value_cansleep\n\nAll calls to the gpio library are in contexts that can sleep,\ntherefore there is no issue with having those GPIOs controlled\nby controllers which require sleeping (eg I2C GPIO expanders).\n\nSwitch to using gpiod_set_value_cansleep instead of gpiod_set_value\nto avoid triggering the warning in gpiolib should the GPIO\ncontroller need to sleep.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>\n---\n drivers/media/i2c/ov5647.c | 8 ++++----\n 1 file changed, 4 insertions(+), 4 deletions(-)\n\n--- a/drivers/media/i2c/ov5647.c\n+++ b/drivers/media/i2c/ov5647.c\n@@ -373,7 +373,7 @@ static int ov5647_sensor_power(struct v4\n \t\tdev_dbg(&client->dev, \"OV5647 power on\\n\");\n \n \t\tif (ov5647->pwdn) {\n-\t\t\tgpiod_set_value(ov5647->pwdn, 0);\n+\t\t\tgpiod_set_value_cansleep(ov5647->pwdn, 0);\n \t\t\tmsleep(PWDN_ACTIVE_DELAY_MS);\n \t\t}\n \n@@ -415,7 +415,7 @@ static int ov5647_sensor_power(struct v4\n \n \t\tclk_disable_unprepare(ov5647->xclk);\n \n-\t\tgpiod_set_value(ov5647->pwdn, 1);\n+\t\tgpiod_set_value_cansleep(ov5647->pwdn, 1);\n \t}\n \n \t/* Update the power count. */\n@@ -648,13 +648,13 @@ static int ov5647_probe(struct i2c_clien\n \t\tgoto mutex_remove;\n \n \tif (sensor->pwdn) {\n-\t\tgpiod_set_value(sensor->pwdn, 0);\n+\t\tgpiod_set_value_cansleep(sensor->pwdn, 0);\n \t\tmsleep(PWDN_ACTIVE_DELAY_MS);\n \t}\n \n \tret = ov5647_detect(sd);\n \n-\tgpiod_set_value(sensor->pwdn, 1);\n+\tgpiod_set_value_cansleep(sensor->pwdn, 1);\n \n \tif (ret < 0)\n \t\tgoto error;\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0119-staging-mmal_vchiq-Add-in-the-Bayer-encoding-formats.patch",
    "content": "From 39b79b302b63d8ba86a0da4d219e5ad2491bac1d Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.org>\nDate: Wed, 13 Feb 2019 12:33:29 +0000\nSubject: [PATCH] staging: mmal_vchiq: Add in the Bayer encoding\n formats\n\nThe list of formats was copied before Bayer support was added.\nThe ISP supports Bayer and is being supported by the bcm2835_codec\ndriver, so add in the encodings for them.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>\n---\n .../vc04_services/vchiq-mmal/mmal-encodings.h | 27 +++++++++++++++++++\n 1 file changed, 27 insertions(+)\n\n--- a/drivers/staging/vc04_services/vchiq-mmal/mmal-encodings.h\n+++ b/drivers/staging/vc04_services/vchiq-mmal/mmal-encodings.h\n@@ -69,6 +69,33 @@\n  */\n #define MMAL_ENCODING_OPAQUE           MMAL_FOURCC('O', 'P', 'Q', 'V')\n \n+/* Bayer formats\n+ * FourCC values copied from V4L2 where defined.\n+ */\n+/* 8 bit per pixel Bayer formats. */\n+#define MMAL_ENCODING_BAYER_SBGGR8     MMAL_FOURCC('B', 'A', '8', '1')\n+#define MMAL_ENCODING_BAYER_SGBRG8     MMAL_FOURCC('G', 'B', 'R', 'G')\n+#define MMAL_ENCODING_BAYER_SGRBG8     MMAL_FOURCC('G', 'R', 'B', 'G')\n+#define MMAL_ENCODING_BAYER_SRGGB8     MMAL_FOURCC('R', 'G', 'G', 'B')\n+\n+/* 10 bit per pixel packed Bayer formats. */\n+#define MMAL_ENCODING_BAYER_SBGGR10P   MMAL_FOURCC('p', 'B', 'A', 'A')\n+#define MMAL_ENCODING_BAYER_SGRBG10P   MMAL_FOURCC('p', 'g', 'A', 'A')\n+#define MMAL_ENCODING_BAYER_SGBRG10P   MMAL_FOURCC('p', 'G', 'A', 'A')\n+#define MMAL_ENCODING_BAYER_SRGGB10P   MMAL_FOURCC('p', 'R', 'A', 'A')\n+\n+/* 12 bit per pixel packed Bayer formats. */\n+#define MMAL_ENCODING_BAYER_SBGGR12P   MMAL_FOURCC('p', 'B', '1', '2')\n+#define MMAL_ENCODING_BAYER_SGRBG12P   MMAL_FOURCC('p', 'g', '1', '2')\n+#define MMAL_ENCODING_BAYER_SGBRG12P   MMAL_FOURCC('p', 'G', '1', '2')\n+#define MMAL_ENCODING_BAYER_SRGGB12P   MMAL_FOURCC('p', 'R', '1', '2')\n+\n+/* 16 bit per pixel Bayer formats. */\n+#define MMAL_ENCODING_BAYER_SBGGR16    MMAL_FOURCC('B', 'G', '1', '6')\n+#define MMAL_ENCODING_BAYER_SGBRG16    MMAL_FOURCC('G', 'B', '1', '6')\n+#define MMAL_ENCODING_BAYER_SGRBG16    MMAL_FOURCC('G', 'R', '1', '6')\n+#define MMAL_ENCODING_BAYER_SRGGB16    MMAL_FOURCC('R', 'G', '1', '6')\n+\n /** An EGL image handle\n  */\n #define MMAL_ENCODING_EGL_IMAGE        MMAL_FOURCC('E', 'G', 'L', 'I')\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0120-staging-mmal-vchiq-Update-mmal_parameters.h-with-rec.patch",
    "content": "From d3356393f78e85eff4b36ad95d86d5f418a87865 Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.org>\nDate: Mon, 18 Feb 2019 15:52:29 +0000\nSubject: [PATCH] staging: mmal-vchiq: Update mmal_parameters.h with\n recently defined params\n\nmmal_parameters.h hasn't been updated to reflect additions made\nover the last few years. Update it to reflect the currently\nsupported parameters.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>\n---\n .../vchiq-mmal/mmal-parameters.h              | 32 ++++++++++++++++++-\n 1 file changed, 31 insertions(+), 1 deletion(-)\n\n--- a/drivers/staging/vc04_services/vchiq-mmal/mmal-parameters.h\n+++ b/drivers/staging/vc04_services/vchiq-mmal/mmal-parameters.h\n@@ -580,7 +580,37 @@ enum mmal_parameter_video_type {\n \tMMAL_PARAMETER_VIDEO_ENCODE_H264_LOW_DELAY_HRD_FLAG,\n \n \t/**< @ref MMAL_PARAMETER_BOOLEAN_T */\n-\tMMAL_PARAMETER_VIDEO_ENCODE_INLINE_HEADER\n+\tMMAL_PARAMETER_VIDEO_ENCODE_INLINE_HEADER,\n+\n+\t/**< Take a @ref MMAL_PARAMETER_BOOLEAN_T. */\n+\tMMAL_PARAMETER_VIDEO_ENCODE_SEI_ENABLE,\n+\n+\t/**< Take a @ref MMAL_PARAMETER_BOOLEAN_T. */\n+\tMMAL_PARAMETER_VIDEO_ENCODE_INLINE_VECTORS,\n+\n+\t/**< Take a @ref MMAL_PARAMETER_VIDEO_RENDER_STATS_T. */\n+\tMMAL_PARAMETER_VIDEO_RENDER_STATS,\n+\n+\t/**< Take a @ref MMAL_PARAMETER_VIDEO_INTERLACE_TYPE_T. */\n+\tMMAL_PARAMETER_VIDEO_INTERLACE_TYPE,\n+\n+\t/**< Takes a @ref MMAL_PARAMETER_BOOLEAN_T */\n+\tMMAL_PARAMETER_VIDEO_INTERPOLATE_TIMESTAMPS,\n+\n+\t/**< Takes a @ref MMAL_PARAMETER_BOOLEAN_T */\n+\tMMAL_PARAMETER_VIDEO_ENCODE_SPS_TIMING,\n+\n+\t/**< Takes a @ref MMAL_PARAMETER_UINT32_T */\n+\tMMAL_PARAMETER_VIDEO_MAX_NUM_CALLBACKS,\n+\n+\t/**< Takes a @ref MMAL_PARAMETER_SOURCE_PATTERN_T */\n+\tMMAL_PARAMETER_VIDEO_SOURCE_PATTERN,\n+\n+\t/**< Takes a @ref MMAL_PARAMETER_BOOLEAN_T */\n+\tMMAL_PARAMETER_VIDEO_ENCODE_SEPARATE_NAL_BUFS,\n+\n+\t/**< Takes a @ref MMAL_PARAMETER_UINT32_T */\n+\tMMAL_PARAMETER_VIDEO_DROPPABLE_PFRAME_LENGTH,\n };\n \n /** Valid mirror modes */\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0121-staging-mmal-vchiq-Free-the-event-context-for-contro.patch",
    "content": "From fd281e20be4590566f0a75d965318685b8562df6 Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.org>\nDate: Wed, 1 May 2019 13:27:23 +0100\nSubject: [PATCH] staging: mmal-vchiq: Free the event context for\n control ports\n\nvchiq_mmal_component_init calls init_event_context for the\ncontrol port, but vchiq_mmal_component_finalise didn't free\nit, causing a memory leak..\n\nAdd the free call.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>\n---\n drivers/staging/vc04_services/vchiq-mmal/mmal-vchiq.c | 2 ++\n 1 file changed, 2 insertions(+)\n\n--- a/drivers/staging/vc04_services/vchiq-mmal/mmal-vchiq.c\n+++ b/drivers/staging/vc04_services/vchiq-mmal/mmal-vchiq.c\n@@ -1901,6 +1901,8 @@ int vchiq_mmal_component_finalise(struct\n \tfor (idx = 0; idx < component->clocks; idx++)\n \t\tfree_event_context(&component->clock[idx]);\n \n+\tfree_event_context(&component->control);\n+\n \tmutex_unlock(&instance->vchiq_mutex);\n \n \treturn ret;\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0122-staging-mmal-vchiq-Fix-memory-leak-in-error-path.patch",
    "content": "From 00dd46a6ddc94ee87db183dfec1e096c159b1d7b Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.org>\nDate: Thu, 2 May 2019 15:50:01 +0100\nSubject: [PATCH] staging: mmal-vchiq: Fix memory leak in error path\n\nOn error, vchiq_mmal_component_init could leave the\nevent context allocated for ports.\nClean them up in the error path.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>\n---\n .../vc04_services/vchiq-mmal/mmal-vchiq.c     | 29 +++++++++++++------\n 1 file changed, 20 insertions(+), 9 deletions(-)\n\n--- a/drivers/staging/vc04_services/vchiq-mmal/mmal-vchiq.c\n+++ b/drivers/staging/vc04_services/vchiq-mmal/mmal-vchiq.c\n@@ -1767,9 +1767,26 @@ static void free_event_context(struct vc\n {\n \tstruct mmal_msg_context *ctx = port->event_context;\n \n+\tif (!ctx)\n+\t\treturn;\n+\n \tkfree(ctx->u.bulk.buffer->buffer);\n \tkfree(ctx->u.bulk.buffer);\n \trelease_msg_context(ctx);\n+\tport->event_context = NULL;\n+}\n+\n+static void release_all_event_contexts(struct vchiq_mmal_component *component)\n+{\n+\tint idx;\n+\n+\tfor (idx = 0; idx < component->inputs; idx++)\n+\t\tfree_event_context(&component->input[idx]);\n+\tfor (idx = 0; idx < component->outputs; idx++)\n+\t\tfree_event_context(&component->output[idx]);\n+\tfor (idx = 0; idx < component->clocks; idx++)\n+\t\tfree_event_context(&component->clock[idx]);\n+\tfree_event_context(&component->control);\n }\n \n /* Initialise a mmal component and its ports\n@@ -1867,6 +1884,7 @@ int vchiq_mmal_component_init(struct vch\n \n release_component:\n \tdestroy_component(instance, component);\n+\trelease_all_event_contexts(component);\n unlock:\n \tif (component)\n \t\tcomponent->in_use = 0;\n@@ -1882,7 +1900,7 @@ EXPORT_SYMBOL_GPL(vchiq_mmal_component_i\n int vchiq_mmal_component_finalise(struct vchiq_mmal_instance *instance,\n \t\t\t\t  struct vchiq_mmal_component *component)\n {\n-\tint ret, idx;\n+\tint ret;\n \n \tif (mutex_lock_interruptible(&instance->vchiq_mutex))\n \t\treturn -EINTR;\n@@ -1894,14 +1912,7 @@ int vchiq_mmal_component_finalise(struct\n \n \tcomponent->in_use = 0;\n \n-\tfor (idx = 0; idx < component->inputs; idx++)\n-\t\tfree_event_context(&component->input[idx]);\n-\tfor (idx = 0; idx < component->outputs; idx++)\n-\t\tfree_event_context(&component->output[idx]);\n-\tfor (idx = 0; idx < component->clocks; idx++)\n-\t\tfree_event_context(&component->clock[idx]);\n-\n-\tfree_event_context(&component->control);\n+\trelease_all_event_contexts(component);\n \n \tmutex_unlock(&instance->vchiq_mutex);\n \n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0123-w1-w1-gpio-Make-GPIO-an-output-for-strong-pullup.patch",
    "content": "From c8ce94db62682da391a3c0d1e148b1a5a959b7e1 Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.org>\nDate: Wed, 12 Jun 2019 17:15:05 +0100\nSubject: [PATCH] w1: w1-gpio: Make GPIO an output for strong pullup\n\nThe logic to drive the data line high to implement a strong pullup\nassumed that the pin was already an output - setting a value does\nnot change an input.\n\nSee: https://github.com/raspberrypi/firmware/issues/1143\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.org>\n---\n drivers/w1/masters/w1-gpio.c | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/drivers/w1/masters/w1-gpio.c\n+++ b/drivers/w1/masters/w1-gpio.c\n@@ -30,7 +30,7 @@ static u8 w1_gpio_set_pullup(void *data,\n \t\t\t * This will OVERRIDE open drain emulation and force-pull\n \t\t\t * the line high for some time.\n \t\t\t */\n-\t\t\tgpiod_set_raw_value(pdata->gpiod, 1);\n+\t\t\tgpiod_direction_output_raw(pdata->gpiod, 1);\n \t\t\tmsleep(pdata->pullup_duration);\n \t\t\t/*\n \t\t\t * This will simply set the line as input since we are doing\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0124-arm-bcm2835-Fix-FIQ-early-ioremap.patch",
    "content": "From 8bf21a7f5449fde59e4c9772db0696b3dc4cfaef Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.org>\nDate: Wed, 20 Feb 2019 08:49:39 +0000\nSubject: [PATCH] arm: bcm2835: Fix FIQ early ioremap\n\nThe ioremapping creates mappings within the vmalloc area. The\nequivalent early function, create_mapping, now checks that the\nrequested explicit virtual address is between VMALLOC_START and\nVMALLOC_END. As there is no reason to have any correlation between\nthe physical and virtual addresses, put the required mappings at\nVMALLOC_START and above.\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.org>\n---\n arch/arm/mach-bcm/board_bcm2835.c | 21 +++++++++++++++------\n 1 file changed, 15 insertions(+), 6 deletions(-)\n\n--- a/arch/arm/mach-bcm/board_bcm2835.c\n+++ b/arch/arm/mach-bcm/board_bcm2835.c\n@@ -5,17 +5,20 @@\n \n #include <linux/init.h>\n #include <linux/irqchip.h>\n+#include <linux/mm.h>\n #include <linux/of_address.h>\n #include <linux/of_fdt.h>\n #include <asm/system_info.h>\n \n #include <asm/mach/arch.h>\n #include <asm/mach/map.h>\n+#include <asm/memory.h>\n+#include <asm/pgtable.h>\n \n #include \"platsmp.h\"\n \n-#define BCM2835_USB_VIRT_BASE   0xf0980000\n-#define BCM2835_USB_VIRT_MPHI   0xf0006000\n+#define BCM2835_USB_VIRT_BASE   (VMALLOC_START)\n+#define BCM2835_USB_VIRT_MPHI   (VMALLOC_START + 0x10000)\n \n static void __init bcm2835_init(void)\n {\n@@ -74,20 +77,26 @@ static int __init bcm2835_map_usb(unsign\n \n static void __init bcm2835_map_io(void)\n {\n-\tconst __be32 *ranges;\n+\tconst __be32 *ranges, *address_cells;\n+\tunsigned long root, addr_cells;\n \tint soc, len;\n \tunsigned long p2b_offset;\n \n \tdebug_ll_io_init();\n \n+\troot = of_get_flat_dt_root();\n \t/* Find out how to map bus to physical address first from soc/ranges */\n-\tsoc = of_get_flat_dt_subnode_by_name(of_get_flat_dt_root(), \"soc\");\n+\tsoc = of_get_flat_dt_subnode_by_name(root, \"soc\");\n \tif (soc < 0)\n \t\treturn;\n+\taddress_cells = of_get_flat_dt_prop(root, \"#address-cells\", &len);\n+\tif (!address_cells || len < (sizeof(unsigned long)))\n+\t\treturn;\n+\taddr_cells = be32_to_cpu(address_cells[0]);\n \tranges = of_get_flat_dt_prop(soc, \"ranges\", &len);\n-\tif (!ranges || len < (sizeof(unsigned long) * 3))\n+\tif (!ranges || len < (sizeof(unsigned long) * (2 + addr_cells)))\n \t\treturn;\n-\tp2b_offset = be32_to_cpu(ranges[0]) - be32_to_cpu(ranges[1]);\n+\tp2b_offset = be32_to_cpu(ranges[0]) - be32_to_cpu(ranges[addr_cells]);\n \n \t/* Now search for bcm2708-usb node in device tree */\n \tof_scan_flat_dt(bcm2835_map_usb, &p2b_offset);\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0125-arm-bcm2835-DMA-can-only-address-1GB.patch",
    "content": "From eac607290fee8b1bcd08c48ac49f089f41a0e696 Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.org>\nDate: Wed, 29 May 2019 15:47:42 +0100\nSubject: [PATCH] arm: bcm2835: DMA can only address 1GB\n\nThe legacy peripherals can only address the first gigabyte of RAM, so\nensure that DMA allocations are restricted to that region.\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.org>\n---\n arch/arm/mach-bcm/board_bcm2835.c | 3 +++\n 1 file changed, 3 insertions(+)\n\n--- a/arch/arm/mach-bcm/board_bcm2835.c\n+++ b/arch/arm/mach-bcm/board_bcm2835.c\n@@ -114,6 +114,9 @@ static const char * const bcm2835_compat\n };\n \n DT_MACHINE_START(BCM2835, \"BCM2835\")\n+#if defined(CONFIG_ZONE_DMA) && defined(CONFIG_ARM_LPAE)\n+\t.dma_zone_size\t= SZ_1G,\n+#endif\n \t.map_io = bcm2835_map_io,\n \t.init_machine = bcm2835_init,\n \t.dt_compat = bcm2835_compat,\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0126-hwrng-iproc-rng200-Add-BCM2838-support.patch",
    "content": "From aae625342e4c3647a1fe7983cac36d658e714602 Mon Sep 17 00:00:00 2001\nFrom: Stefan Wahren <wahrenst@gmx.net>\nDate: Sat, 4 May 2019 17:06:15 +0200\nSubject: [PATCH] hwrng: iproc-rng200: Add BCM2838 support\n\nThe HWRNG on the BCM2838 is compatible to iproc-rng200, so add the\nsupport to this driver instead of bcm2835-rng.\n\nSigned-off-by: Stefan Wahren <wahrenst@gmx.net>\n\nhwrng: iproc-rng200: Correct SoC name\n\nThe Pi 4 SoC is called BCM2711, not BCM2838.\n\nFixes: \"hwrng: iproc-rng200: Add BCM2838 support\"\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.com>\n---\n drivers/char/hw_random/Kconfig        |  2 +-\n drivers/char/hw_random/iproc-rng200.c | 78 +++++++++++++++++++++++++--\n 2 files changed, 76 insertions(+), 4 deletions(-)\n\n--- a/drivers/char/hw_random/Kconfig\n+++ b/drivers/char/hw_random/Kconfig\n@@ -104,7 +104,7 @@ config HW_RANDOM_IPROC_RNG200\n \tdefault HW_RANDOM\n \thelp\n \t  This driver provides kernel-side support for the RNG200\n-\t  hardware found on the Broadcom iProc and STB SoCs.\n+\t  hardware found on the Broadcom iProc, BCM2711 and STB SoCs.\n \n \t  To compile this driver as a module, choose M here: the\n \t  module will be called iproc-rng200\n--- a/drivers/char/hw_random/iproc-rng200.c\n+++ b/drivers/char/hw_random/iproc-rng200.c\n@@ -29,6 +29,7 @@\n #define RNG_CTRL_RNG_RBGEN_MASK\t\t\t\t0x00001FFF\n #define RNG_CTRL_RNG_RBGEN_ENABLE\t\t\t0x00000001\n #define RNG_CTRL_RNG_RBGEN_DISABLE\t\t\t0x00000000\n+#define RNG_CTRL_RNG_DIV_CTRL_SHIFT\t\t\t13\n \n #define RNG_SOFT_RESET_OFFSET\t\t\t\t0x04\n #define RNG_SOFT_RESET\t\t\t\t\t0x00000001\n@@ -36,16 +37,23 @@\n #define RBG_SOFT_RESET_OFFSET\t\t\t\t0x08\n #define RBG_SOFT_RESET\t\t\t\t\t0x00000001\n \n+#define RNG_TOTAL_BIT_COUNT_OFFSET\t\t\t0x0C\n+\n+#define RNG_TOTAL_BIT_COUNT_THRESHOLD_OFFSET\t\t0x10\n+\n #define RNG_INT_STATUS_OFFSET\t\t\t\t0x18\n #define RNG_INT_STATUS_MASTER_FAIL_LOCKOUT_IRQ_MASK\t0x80000000\n #define RNG_INT_STATUS_STARTUP_TRANSITIONS_MET_IRQ_MASK\t0x00020000\n #define RNG_INT_STATUS_NIST_FAIL_IRQ_MASK\t\t0x00000020\n #define RNG_INT_STATUS_TOTAL_BITS_COUNT_IRQ_MASK\t0x00000001\n \n+#define RNG_INT_ENABLE_OFFSET\t\t\t\t0x1C\n+\n #define RNG_FIFO_DATA_OFFSET\t\t\t\t0x20\n \n #define RNG_FIFO_COUNT_OFFSET\t\t\t\t0x24\n #define RNG_FIFO_COUNT_RNG_FIFO_COUNT_MASK\t\t0x000000FF\n+#define RNG_FIFO_COUNT_RNG_FIFO_THRESHOLD_SHIFT\t\t8\n \n struct iproc_rng200_dev {\n \tstruct hwrng rng;\n@@ -166,6 +174,64 @@ static int iproc_rng200_init(struct hwrn\n \treturn 0;\n }\n \n+static int bcm2711_rng200_read(struct hwrng *rng, void *buf, size_t max,\n+\t\t\t       bool wait)\n+{\n+\tstruct iproc_rng200_dev *priv = to_rng_priv(rng);\n+\tu32 max_words = max / sizeof(u32);\n+\tu32 num_words, count, val;\n+\n+\t/* ensure warm up period has elapsed */\n+\twhile (1) {\n+\t\tval = ioread32(priv->base + RNG_TOTAL_BIT_COUNT_OFFSET);\n+\t\tif (val > 16)\n+\t\t\tbreak;\n+\t\tcpu_relax();\n+\t}\n+\n+\t/* ensure fifo is not empty */\n+\twhile (1) {\n+\t\tnum_words = ioread32(priv->base + RNG_FIFO_COUNT_OFFSET) &\n+\t\t\t    RNG_FIFO_COUNT_RNG_FIFO_COUNT_MASK;\n+\t\tif (num_words)\n+\t\t\tbreak;\n+\t\tif (!wait)\n+\t\t\treturn 0;\n+\t\tcpu_relax();\n+\t}\n+\n+\tif (num_words > max_words)\n+\t\tnum_words = max_words;\n+\n+\tfor (count = 0; count < num_words; count++) {\n+\t\t((u32 *)buf)[count] = ioread32(priv->base +\n+\t\t\t\t\t       RNG_FIFO_DATA_OFFSET);\n+\t}\n+\n+\treturn num_words * sizeof(u32);\n+}\n+\n+static int bcm2711_rng200_init(struct hwrng *rng)\n+{\n+\tstruct iproc_rng200_dev *priv = to_rng_priv(rng);\n+\tuint32_t val;\n+\n+\tif (ioread32(priv->base + RNG_CTRL_OFFSET) & RNG_CTRL_RNG_RBGEN_MASK)\n+\t\treturn 0;\n+\n+\t/* initial numbers generated are \"less random\" so will be discarded */\n+\tval = 0x40000;\n+\tiowrite32(val, priv->base + RNG_TOTAL_BIT_COUNT_THRESHOLD_OFFSET);\n+\t/* min fifo count to generate full interrupt */\n+\tval = 2 << RNG_FIFO_COUNT_RNG_FIFO_THRESHOLD_SHIFT;\n+\tiowrite32(val, priv->base + RNG_FIFO_COUNT_OFFSET);\n+\t/* enable the rng - 1Mhz sample rate */\n+\tval = (0x3 << RNG_CTRL_RNG_DIV_CTRL_SHIFT) | RNG_CTRL_RNG_RBGEN_MASK;\n+\tiowrite32(val, priv->base + RNG_CTRL_OFFSET);\n+\n+\treturn 0;\n+}\n+\n static void iproc_rng200_cleanup(struct hwrng *rng)\n {\n \tstruct iproc_rng200_dev *priv = to_rng_priv(rng);\n@@ -195,11 +261,17 @@ static int iproc_rng200_probe(struct pla\n \t\treturn PTR_ERR(priv->base);\n \t}\n \n-\tpriv->rng.name = \"iproc-rng200\";\n-\tpriv->rng.read = iproc_rng200_read;\n-\tpriv->rng.init = iproc_rng200_init;\n+\tpriv->rng.name = pdev->name;\n \tpriv->rng.cleanup = iproc_rng200_cleanup;\n \n+\tif (of_device_is_compatible(dev->of_node, \"brcm,bcm2711-rng200\")) {\n+\t\tpriv->rng.init = bcm2711_rng200_init;\n+\t\tpriv->rng.read = bcm2711_rng200_read;\n+\t} else {\n+\t\tpriv->rng.init = iproc_rng200_init;\n+\t\tpriv->rng.read = iproc_rng200_read;\n+\t}\n+\n \t/* Register driver */\n \tret = devm_hwrng_register(dev, &priv->rng);\n \tif (ret) {\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0127-mmc-sdhci-iproc-Fix-vmmc-regulators-on-iProc.patch",
    "content": "From efc6e571660a0d0ca53fb603cc4f132481e8977f Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.org>\nDate: Fri, 2 Aug 2019 15:20:11 +0100\nSubject: [PATCH] mmc: sdhci-iproc: Fix vmmc regulators on iProc\n\nThe Linux support for controlling card power via regulators appears to\nbe contentious. I would argue that the default behaviour is contrary to\nthe SDHCI spec - turning off the power writes a reserved value to the\nSD Bus Voltage Select field of the Power Control Register, which\nseems to kill the Arasan/iProc controller - but fortunately there is a\nhook in sdhci_ops to override the behaviour. Borrow the implementation\nfrom sdhci_arasan_set_power.\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.org>\n---\n drivers/mmc/host/sdhci-iproc.c | 12 ++++++++++++\n 1 file changed, 12 insertions(+)\n\n--- a/drivers/mmc/host/sdhci-iproc.c\n+++ b/drivers/mmc/host/sdhci-iproc.c\n@@ -190,6 +190,17 @@ static unsigned int sdhci_iproc_bcm2711_\n \treturn 200000;\n }\n \n+static void sdhci_iproc_set_power(struct sdhci_host *host, unsigned char mode,\n+\t\t\t\t  unsigned short vdd)\n+{\n+\tif (!IS_ERR(host->mmc->supply.vmmc)) {\n+\t\tstruct mmc_host *mmc = host->mmc;\n+\n+\t\tmmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);\n+\t}\n+\tsdhci_set_power_noreg(host, mode, vdd);\n+}\n+\n static const struct sdhci_ops sdhci_iproc_ops = {\n \t.set_clock = sdhci_set_clock,\n \t.get_max_clock = sdhci_iproc_get_max_clock,\n@@ -207,6 +218,7 @@ static const struct sdhci_ops sdhci_ipro\n \t.write_b = sdhci_iproc_writeb,\n \t.set_clock = sdhci_set_clock,\n \t.get_max_clock = sdhci_iproc_get_max_clock,\n+\t.set_power = sdhci_iproc_set_power,\n \t.set_bus_width = sdhci_set_bus_width,\n \t.reset = sdhci_reset,\n \t.set_uhs_signaling = sdhci_set_uhs_signaling,\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0128-vchiq-Add-36-bit-address-support.patch",
    "content": "From 4237f040ec6d54ef0b3782415d354e5b9a023873 Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.org>\nDate: Thu, 1 Nov 2018 17:31:37 +0000\nSubject: [PATCH] vchiq: Add 36-bit address support\n\nConditional on a new compatible string, change the pagelist encoding\nsuch that the top 24 bits are the pfn, leaving 8 bits for run length\n(-1).\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.org>\n\nstaging/vchiq_arm: Fix bcm2711 compatible string\n\nFixes: \"vchiq: Add 36-bit address support\"\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.com>\n---\n .../interface/vchiq_arm/vchiq_2835_arm.c      | 90 ++++++++++++++-----\n .../interface/vchiq_arm/vchiq_arm.c           |  6 ++\n .../interface/vchiq_arm/vchiq_arm.h           |  1 +\n 3 files changed, 75 insertions(+), 22 deletions(-)\n\n--- a/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_2835_arm.c\n+++ b/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_2835_arm.c\n@@ -16,6 +16,8 @@\n #include <soc/bcm2835/raspberrypi-firmware.h>\n \n #define TOTAL_SLOTS (VCHIQ_SLOT_ZERO_SLOTS + 2 * 32)\n+#define VC_SAFE(x) (g_use_36bit_addrs ? ((u32)(x) | 0xc0000000) : (u32)(x))\n+#define IS_VC_SAFE(x) (g_use_36bit_addrs ? !((x) & ~0x3fffffffull) : 1)\n \n #include \"vchiq_arm.h\"\n #include \"vchiq_connected.h\"\n@@ -58,6 +60,7 @@ static void __iomem *g_regs;\n  * of 32.\n  */\n static unsigned int g_cache_line_size = 32;\n+static unsigned int g_use_36bit_addrs = 0;\n static unsigned int g_fragments_size;\n static char *g_fragments_base;\n static char *g_free_fragments;\n@@ -100,6 +103,8 @@ int vchiq_platform_init(struct platform_\n \tg_cache_line_size = drvdata->cache_line_size;\n \tg_fragments_size = 2 * g_cache_line_size;\n \n+\tg_use_36bit_addrs = (dev->dma_pfn_offset == 0);\n+\n \t/* Allocate space for the channels in coherent memory */\n \tslot_mem_size = PAGE_ALIGN(TOTAL_SLOTS * VCHIQ_SLOT_SIZE);\n \tfrag_mem_size = PAGE_ALIGN(g_fragments_size * MAX_FRAGMENTS);\n@@ -111,14 +116,21 @@ int vchiq_platform_init(struct platform_\n \t\treturn -ENOMEM;\n \t}\n \n+\tif (!IS_VC_SAFE(slot_phys)) {\n+\t\tdev_err(dev, \"allocated DMA memory %pad is not VC-safe\\n\",\n+\t\t\t&slot_phys);\n+\t\treturn -ENOMEM;\n+\t}\n+\n \tWARN_ON(((unsigned long)slot_mem & (PAGE_SIZE - 1)) != 0);\n+\tchannelbase = VC_SAFE(slot_phys);\n \n \tvchiq_slot_zero = vchiq_init_slots(slot_mem, slot_mem_size);\n \tif (!vchiq_slot_zero)\n \t\treturn -EINVAL;\n \n \tvchiq_slot_zero->platform_data[VCHIQ_PLATFORM_FRAGMENTS_OFFSET_IDX] =\n-\t\t(int)slot_phys + slot_mem_size;\n+\t\tchannelbase + slot_mem_size;\n \tvchiq_slot_zero->platform_data[VCHIQ_PLATFORM_FRAGMENTS_COUNT_IDX] =\n \t\tMAX_FRAGMENTS;\n \n@@ -151,7 +163,6 @@ int vchiq_platform_init(struct platform_\n \t}\n \n \t/* Send the base address of the slots to VideoCore */\n-\tchannelbase = slot_phys;\n \terr = rpi_firmware_property(fw, RPI_FIRMWARE_VCHIQ_INIT,\n \t\t\t\t    &channelbase, sizeof(channelbase));\n \tif (err || channelbase) {\n@@ -229,7 +240,7 @@ vchiq_prepare_bulk_data(struct vchiq_bul\n \tif (!pagelistinfo)\n \t\treturn VCHIQ_ERROR;\n \n-\tbulk->data = pagelistinfo->dma_addr;\n+\tbulk->data = (void *)VC_SAFE(pagelistinfo->dma_addr);\n \n \t/*\n \t * Store the pagelistinfo address in remote_data,\n@@ -447,25 +458,60 @@ create_pagelist(char *buf, char __user *\n \n \t/* Combine adjacent blocks for performance */\n \tk = 0;\n-\tfor_each_sg(scatterlist, sg, dma_buffers, i) {\n-\t\tu32 len = sg_dma_len(sg);\n-\t\tu32 addr = sg_dma_address(sg);\n-\n-\t\t/* Note: addrs is the address + page_count - 1\n-\t\t * The firmware expects blocks after the first to be page-\n-\t\t * aligned and a multiple of the page size\n-\t\t */\n-\t\tWARN_ON(len == 0);\n-\t\tWARN_ON(i && (i != (dma_buffers - 1)) && (len & ~PAGE_MASK));\n-\t\tWARN_ON(i && (addr & ~PAGE_MASK));\n-\t\tif (k > 0 &&\n-\t\t    ((addrs[k - 1] & PAGE_MASK) +\n-\t\t     (((addrs[k - 1] & ~PAGE_MASK) + 1) << PAGE_SHIFT))\n-\t\t    == (addr & PAGE_MASK))\n-\t\t\taddrs[k - 1] += ((len + PAGE_SIZE - 1) >> PAGE_SHIFT);\n-\t\telse\n-\t\t\taddrs[k++] = (addr & PAGE_MASK) |\n-\t\t\t\t(((len + PAGE_SIZE - 1) >> PAGE_SHIFT) - 1);\n+\tif (g_use_36bit_addrs) {\n+\t\tfor_each_sg(scatterlist, sg, dma_buffers, i) {\n+\t\t\tu32 len = sg_dma_len(sg);\n+\t\t\tu64 addr = sg_dma_address(sg);\n+\t\t\tu32 page_id = (u32)((addr >> 4) & ~0xff);\n+\t\t\tu32 sg_pages = (len + PAGE_SIZE - 1) >> PAGE_SHIFT;\n+\n+\t\t\t/* Note: addrs is the address + page_count - 1\n+\t\t\t * The firmware expects blocks after the first to be page-\n+\t\t\t * aligned and a multiple of the page size\n+\t\t\t */\n+\t\t\tWARN_ON(len == 0);\n+\t\t\tWARN_ON(i &&\n+\t\t\t\t(i != (dma_buffers - 1)) && (len & ~PAGE_MASK));\n+\t\t\tWARN_ON(i && (addr & ~PAGE_MASK));\n+\t\t\tWARN_ON(upper_32_bits(addr) > 0xf);\n+\t\t\tif (k > 0 &&\n+\t\t\t    ((addrs[k - 1] & ~0xff) +\n+\t\t\t     (((addrs[k - 1] & 0xff) + 1) << 8)\n+\t\t\t     == page_id)) {\n+\t\t\t\tu32 inc_pages = min(sg_pages,\n+\t\t\t\t\t\t    0xff - (addrs[k - 1] & 0xff));\n+\t\t\t\taddrs[k - 1] += inc_pages;\n+\t\t\t\tpage_id += inc_pages << 8;\n+\t\t\t\tsg_pages -= inc_pages;\n+\t\t\t}\n+\t\t\twhile (sg_pages) {\n+\t\t\t\tu32 inc_pages = min(sg_pages, 0x100u);\n+\t\t\t\taddrs[k++] = page_id | (inc_pages - 1);\n+\t\t\t\tpage_id += inc_pages << 8;\n+\t\t\t\tsg_pages -= inc_pages;\n+\t\t\t}\n+\t\t}\n+\t} else {\n+\t\tfor_each_sg(scatterlist, sg, dma_buffers, i) {\n+\t\t\tu32 len = sg_dma_len(sg);\n+\t\t\tu32 addr = VC_SAFE(sg_dma_address(sg));\n+\t\t\tu32 new_pages = (len + PAGE_SIZE - 1) >> PAGE_SHIFT;\n+\n+\t\t\t/* Note: addrs is the address + page_count - 1\n+\t\t\t * The firmware expects blocks after the first to be page-\n+\t\t\t * aligned and a multiple of the page size\n+\t\t\t */\n+\t\t\tWARN_ON(len == 0);\n+\t\t\tWARN_ON(i && (i != (dma_buffers - 1)) && (len & ~PAGE_MASK));\n+\t\t\tWARN_ON(i && (addr & ~PAGE_MASK));\n+\t\t\tif (k > 0 &&\n+\t\t\t    ((addrs[k - 1] & PAGE_MASK) +\n+\t\t\t     (((addrs[k - 1] & ~PAGE_MASK) + 1) << PAGE_SHIFT))\n+\t\t\t    == (addr & PAGE_MASK))\n+\t\t\t\taddrs[k - 1] += new_pages;\n+\t\t\telse\n+\t\t\t\taddrs[k++] = (addr & PAGE_MASK) | (new_pages - 1);\n+\t\t}\n \t}\n \n \t/* Partial cache lines (fragments) require special measures */\n--- a/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_arm.c\n+++ b/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_arm.c\n@@ -118,6 +118,11 @@ static struct vchiq_drvdata bcm2836_drvd\n \t.cache_line_size = 64,\n };\n \n+static struct vchiq_drvdata bcm2711_drvdata = {\n+\t.cache_line_size = 64,\n+\t.use_36bit_addrs = true,\n+};\n+\n static const char *const ioctl_names[] = {\n \t\"CONNECT\",\n \t\"SHUTDOWN\",\n@@ -2679,6 +2684,7 @@ void vchiq_platform_conn_state_changed(s\n static const struct of_device_id vchiq_of_match[] = {\n \t{ .compatible = \"brcm,bcm2835-vchiq\", .data = &bcm2835_drvdata },\n \t{ .compatible = \"brcm,bcm2836-vchiq\", .data = &bcm2836_drvdata },\n+\t{ .compatible = \"brcm,bcm2711-vchiq\", .data = &bcm2711_drvdata },\n \t{},\n };\n MODULE_DEVICE_TABLE(of, vchiq_of_match);\n--- a/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_arm.h\n+++ b/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_arm.h\n@@ -52,6 +52,7 @@ struct vchiq_arm_state {\n \n struct vchiq_drvdata {\n \tconst unsigned int cache_line_size;\n+\tconst bool use_36bit_addrs;\n \tstruct rpi_firmware *fw;\n };\n \n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0129-bcm2835-pcm.c-Support-multichannel-audio.patch",
    "content": "From 968742728020752788d4b3a6cd75c977db161b46 Mon Sep 17 00:00:00 2001\nFrom: popcornmix <popcornmix@gmail.com>\nDate: Tue, 30 Apr 2019 19:15:30 +0100\nSubject: [PATCH] bcm2835-pcm.c: Support multichannel audio\n\n---\n .../vc04_services/bcm2835-audio/bcm2835-pcm.c   | 17 +++++++++--------\n 1 file changed, 9 insertions(+), 8 deletions(-)\n\n--- a/drivers/staging/vc04_services/bcm2835-audio/bcm2835-pcm.c\n+++ b/drivers/staging/vc04_services/bcm2835-audio/bcm2835-pcm.c\n@@ -14,9 +14,9 @@ static const struct snd_pcm_hardware snd\n \t\t SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_MMAP_VALID |\n \t\t SNDRV_PCM_INFO_SYNC_APPLPTR),\n \t.formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,\n-\t.rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,\n+\t.rates = SNDRV_PCM_RATE_CONTINUOUS |  SNDRV_PCM_RATE_8000_192000,\n \t.rate_min = 8000,\n-\t.rate_max = 48000,\n+\t.rate_max = 192000,\n \t.channels_min = 1,\n \t.channels_max = 2,\n \t.buffer_bytes_max = 128 * 1024,\n@@ -31,15 +31,16 @@ static const struct snd_pcm_hardware snd\n \t\t SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_MMAP_VALID |\n \t\t SNDRV_PCM_INFO_SYNC_APPLPTR),\n \t.formats = SNDRV_PCM_FMTBIT_S16_LE,\n-\t.rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_44100 |\n-\tSNDRV_PCM_RATE_48000,\n+\t.rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\n+\tSNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 |\n+\tSNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000,\n \t.rate_min = 44100,\n-\t.rate_max = 48000,\n+\t.rate_max = 192000,\n \t.channels_min = 2,\n-\t.channels_max = 2,\n-\t.buffer_bytes_max = 128 * 1024,\n+\t.channels_max = 8,\n+\t.buffer_bytes_max = 512 * 1024,\n \t.period_bytes_min = 1 * 1024,\n-\t.period_bytes_max = 128 * 1024,\n+\t.period_bytes_max = 512 * 1024,\n \t.periods_min = 1,\n \t.periods_max = 128,\n };\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0130-bcmgenet-constrain-max-DMA-burst-length.patch",
    "content": "From adfa8e90db935da2b8bdfa9b8e8a3070f6c05818 Mon Sep 17 00:00:00 2001\nFrom: Jonathan Bell <jonathan@raspberrypi.org>\nDate: Wed, 12 Sep 2018 14:44:53 +0100\nSubject: [PATCH] bcmgenet: constrain max DMA burst length\n\n---\n drivers/net/ethernet/broadcom/genet/bcmgenet.h | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/drivers/net/ethernet/broadcom/genet/bcmgenet.h\n+++ b/drivers/net/ethernet/broadcom/genet/bcmgenet.h\n@@ -29,7 +29,7 @@\n #define ENET_PAD\t\t8\n #define ENET_MAX_MTU_SIZE\t(ETH_DATA_LEN + ETH_HLEN + VLAN_HLEN + \\\n \t\t\t\t ENET_BRCM_TAG_LEN + ETH_FCS_LEN + ENET_PAD)\n-#define DMA_MAX_BURST_LENGTH    0x10\n+#define DMA_MAX_BURST_LENGTH    0x08\n \n /* misc. configuration */\n #define MAX_NUM_OF_FS_RULES\t\t16\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0131-bcmgenet-Better-coalescing-parameter-defaults.patch",
    "content": "From c69b192667d50c317bab33e283e7cfce1622e499 Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.org>\nDate: Wed, 27 Mar 2019 13:45:46 +0000\nSubject: [PATCH] bcmgenet: Better coalescing parameter defaults\n\nSet defaults for TX and RX packet coalescing to be equivalent to:\n\n  # ethtool -C eth0 tx-frames 10\n  # ethtool -C eth0 rx-usecs 50\n\nThis may be something we want to set via DT parameters in the\nfuture.\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.org>\n---\n drivers/net/ethernet/broadcom/genet/bcmgenet.c | 7 +++++--\n 1 file changed, 5 insertions(+), 2 deletions(-)\n\n--- a/drivers/net/ethernet/broadcom/genet/bcmgenet.c\n+++ b/drivers/net/ethernet/broadcom/genet/bcmgenet.c\n@@ -2597,7 +2597,7 @@ static void bcmgenet_init_tx_ring(struct\n \n \tbcmgenet_tdma_ring_writel(priv, index, 0, TDMA_PROD_INDEX);\n \tbcmgenet_tdma_ring_writel(priv, index, 0, TDMA_CONS_INDEX);\n-\tbcmgenet_tdma_ring_writel(priv, index, 1, DMA_MBUF_DONE_THRESH);\n+\tbcmgenet_tdma_ring_writel(priv, index, 10, DMA_MBUF_DONE_THRESH);\n \t/* Disable rate control for now */\n \tbcmgenet_tdma_ring_writel(priv, index, flow_period_val,\n \t\t\t\t  TDMA_FLOW_PERIOD);\n@@ -4062,9 +4062,12 @@ static int bcmgenet_probe(struct platfor\n \tnetif_set_real_num_rx_queues(priv->dev, priv->hw_params->rx_queues + 1);\n \n \t/* Set default coalescing parameters */\n-\tfor (i = 0; i < priv->hw_params->rx_queues; i++)\n+\tfor (i = 0; i < priv->hw_params->rx_queues; i++) {\n \t\tpriv->rx_rings[i].rx_max_coalesced_frames = 1;\n+\t\tpriv->rx_rings[i].rx_coalesce_usecs = 50;\n+\t}\n \tpriv->rx_rings[DESC_INDEX].rx_max_coalesced_frames = 1;\n+\tpriv->rx_rings[DESC_INDEX].rx_coalesce_usecs = 50;\n \n \t/* libphy will determine the link state */\n \tnetif_carrier_off(dev);\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0132-net-genet-enable-link-energy-detect-powerdown-for-ex.patch",
    "content": "From 79bf7ef15016f04a100973b6d207d2aa63552898 Mon Sep 17 00:00:00 2001\nFrom: Jonathan Bell <jonathan@raspberrypi.org>\nDate: Tue, 14 May 2019 17:17:59 +0100\nSubject: [PATCH] net: genet: enable link energy detect powerdown for\n external PHYs\n\nThere are several warts surrounding bcmgenet_mii_probe() as this\nfunction is called from ndo_open, but it's calling registration-type\nfunctions. The probe should be called at probe time and refactored\nsuch that the PHY device data can be extracted to limit the scope\nof this flag to Broadcom PHYs.\n\nFor now, pass this flag in as it puts our attached PHY into a low-power\nstate when disconnected.\n\nSigned-off-by: Jonathan Bell <jonathan@raspberrypi.org>\n---\n drivers/net/ethernet/broadcom/genet/bcmmii.c | 2 ++\n 1 file changed, 2 insertions(+)\n\n--- a/drivers/net/ethernet/broadcom/genet/bcmmii.c\n+++ b/drivers/net/ethernet/broadcom/genet/bcmmii.c\n@@ -293,6 +293,8 @@ int bcmgenet_mii_probe(struct net_device\n \t/* Communicate the integrated PHY revision */\n \tif (priv->internal_phy)\n \t\tphy_flags = priv->gphy_rev;\n+\telse\n+\t\tphy_flags = PHY_BRCM_AUTO_PWRDWN_ENABLE;\n \n \t/* Initialize link state variables that bcmgenet_mii_setup() uses */\n \tpriv->old_link = -1;\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0133-spi-bcm2835-enable-shared-interrupt-support.patch",
    "content": "From aac689d308b3f6dff8a8ccbd85f8a32078a92318 Mon Sep 17 00:00:00 2001\nFrom: Martin Sperl <kernel@martin.sperl.org>\nDate: Mon, 13 May 2019 11:05:27 +0000\nSubject: [PATCH] spi: bcm2835: enable shared interrupt support\n\nAdd shared interrupt support for this driver.\n\nSigned-off-by: Martin Sperl <kernel@martin.sperl.org>\n---\n drivers/spi/spi-bcm2835.c | 7 ++++++-\n 1 file changed, 6 insertions(+), 1 deletion(-)\n\n--- a/drivers/spi/spi-bcm2835.c\n+++ b/drivers/spi/spi-bcm2835.c\n@@ -379,6 +379,10 @@ static irqreturn_t bcm2835_spi_interrupt\n \tif (bs->tx_len && cs & BCM2835_SPI_CS_DONE)\n \t\tbcm2835_wr_fifo_blind(bs, BCM2835_SPI_FIFO_SIZE);\n \n+\t/* check if we got interrupt enabled */\n+\tif (!(bcm2835_rd(bs, BCM2835_SPI_CS) & BCM2835_SPI_CS_INTR))\n+\t\treturn IRQ_NONE;\n+\n \t/* Read as many bytes as possible from FIFO */\n \tbcm2835_rd_fifo(bs);\n \t/* Write as many bytes as possible to FIFO */\n@@ -1329,7 +1333,8 @@ static int bcm2835_spi_probe(struct plat\n \tbcm2835_wr(bs, BCM2835_SPI_CS,\n \t\t   BCM2835_SPI_CS_CLEAR_RX | BCM2835_SPI_CS_CLEAR_TX);\n \n-\terr = devm_request_irq(&pdev->dev, bs->irq, bcm2835_spi_interrupt, 0,\n+\terr = devm_request_irq(&pdev->dev, bs->irq, bcm2835_spi_interrupt,\n+\t\t\t       IRQF_SHARED,\n \t\t\t       dev_name(&pdev->dev), bs);\n \tif (err) {\n \t\tdev_err(&pdev->dev, \"could not request IRQ: %d\\n\", err);\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0134-clk-bcm2835-Don-t-wait-for-pllh-lock.patch",
    "content": "From c1fb629fa486608edab88fb4aa9ab54dd2dcb52c Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.org>\nDate: Wed, 23 Jan 2019 16:11:50 +0000\nSubject: [PATCH] clk-bcm2835: Don't wait for pllh lock\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.org>\n---\n drivers/clk/bcm/clk-bcm2835.c | 18 ++++++++++--------\n 1 file changed, 10 insertions(+), 8 deletions(-)\n\n--- a/drivers/clk/bcm/clk-bcm2835.c\n+++ b/drivers/clk/bcm/clk-bcm2835.c\n@@ -644,15 +644,17 @@ static int bcm2835_pll_on(struct clk_hw\n \tspin_unlock(&cprman->regs_lock);\n \n \t/* Wait for the PLL to lock. */\n-\ttimeout = ktime_add_ns(ktime_get(), LOCK_TIMEOUT_NS);\n-\twhile (!(cprman_read(cprman, CM_LOCK) & data->lock_mask)) {\n-\t\tif (ktime_after(ktime_get(), timeout)) {\n-\t\t\tdev_err(cprman->dev, \"%s: couldn't lock PLL\\n\",\n-\t\t\t\tclk_hw_get_name(hw));\n-\t\t\treturn -ETIMEDOUT;\n-\t\t}\n+\tif (strcmp(data->name, \"pllh\")) {\n+\t\ttimeout = ktime_add_ns(ktime_get(), LOCK_TIMEOUT_NS);\n+\t\twhile (!(cprman_read(cprman, CM_LOCK) & data->lock_mask)) {\n+\t\t\tif (ktime_after(ktime_get(), timeout)) {\n+\t\t\t\tdev_err(cprman->dev, \"%s: couldn't lock PLL\\n\",\n+\t\t\t\t\tclk_hw_get_name(hw));\n+\t\t\t\treturn -ETIMEDOUT;\n+\t\t\t}\n \n-\t\tcpu_relax();\n+\t\t\tcpu_relax();\n+\t\t}\n \t}\n \n \tcprman_write(cprman, data->a2w_ctrl_reg,\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0135-soc-bcm-bcm2835-pm-Add-support-for-2711.patch",
    "content": "From ca09b9e400f42e5be7d0646237f6ada07ee6c01c Mon Sep 17 00:00:00 2001\nFrom: Eric Anholt <eric@anholt.net>\nDate: Fri, 11 Jan 2019 17:31:07 -0800\nSubject: [PATCH] soc: bcm: bcm2835-pm: Add support for 2711.\n\nWithout the actual power management part any more, there's a lot less\nto set up for V3D.  We just need to clear the RSTN field for the power\ndomain, and expose the reset controller for toggling it again.\n\nThis is definitely incomplete -- the old ISP and H264 is in the old\nbridge, but since we have no consumers of it I've just done the\nminimum to get V3D working.\n\nSigned-off-by: Eric Anholt <eric@anholt.net>\n---\n drivers/mfd/bcm2835-pm.c        | 11 +++++++++++\n drivers/soc/bcm/bcm2835-power.c | 22 ++++++++++++++++++++++\n include/linux/mfd/bcm2835-pm.h  |  1 +\n 3 files changed, 34 insertions(+)\n\n--- a/drivers/mfd/bcm2835-pm.c\n+++ b/drivers/mfd/bcm2835-pm.c\n@@ -50,6 +50,17 @@ static int bcm2835_pm_probe(struct platf\n \tif (ret)\n \t\treturn ret;\n \n+\t/* Map the ARGON ASB regs if present. */\n+\tres = platform_get_resource(pdev, IORESOURCE_MEM, 2);\n+\tif (res) {\n+\t\tpm->arg_asb = devm_ioremap_resource(dev, res);\n+\t\tif (IS_ERR(pm->arg_asb)) {\n+\t\t\tdev_err(dev, \"Failed to map ARGON ASB: %ld\\n\",\n+\t\t\t\tPTR_ERR(pm->arg_asb));\n+\t\t\treturn PTR_ERR(pm->arg_asb);\n+\t\t}\n+\t}\n+\n \t/* We'll use the presence of the AXI ASB regs in the\n \t * bcm2835-pm binding as the key for whether we can reference\n \t * the full PM register range and support power domains.\n--- a/drivers/soc/bcm/bcm2835-power.c\n+++ b/drivers/soc/bcm/bcm2835-power.c\n@@ -143,6 +143,8 @@ struct bcm2835_power {\n \t/* AXI Async bridge registers. */\n \tvoid __iomem\t\t*asb;\n \n+\tbool is_2711;\n+\n \tstruct genpd_onecell_data pd_xlate;\n \tstruct bcm2835_power_domain domains[BCM2835_POWER_DOMAIN_COUNT];\n \tstruct reset_controller_dev reset;\n@@ -192,6 +194,10 @@ static int bcm2835_power_power_off(struc\n {\n \tstruct bcm2835_power *power = pd->power;\n \n+\t/* 2711 has no power domains above the reset controller. */\n+\tif (power->is_2711)\n+\t\treturn 0;\n+\n \t/* Enable functional isolation */\n \tPM_WRITE(pm_reg, PM_READ(pm_reg) & ~PM_ISFUNC);\n \n@@ -213,6 +219,10 @@ static int bcm2835_power_power_on(struct\n \tint inrush;\n \tbool powok;\n \n+\t/* 2711 has no power domains above the reset controller. */\n+\tif (power->is_2711)\n+\t\treturn 0;\n+\n \t/* If it was already powered on by the fw, leave it that way. */\n \tif (PM_READ(pm_reg) & PM_POWUP)\n \t\treturn 0;\n@@ -627,6 +637,18 @@ static int bcm2835_power_probe(struct pl\n \tpower->base = pm->base;\n \tpower->asb = pm->asb;\n \n+\t/* 2711 hack: the new ARGON ASB took over V3D, which is our\n+\t * only consumer of this driver so far.  The old ASB seems to\n+\t * still be present with ISP and H264 bits but no V3D, but I\n+\t * don't know if that's real or not.  The V3D is in the same\n+\t * place in the new ASB as the old one, so just poke the new\n+\t * one for now.\n+\t */\n+\tif (pm->arg_asb) {\n+\t\tpower->asb = pm->arg_asb;\n+\t\tpower->is_2711 = true;\n+\t}\n+\n \tid = ASB_READ(ASB_AXI_BRDG_ID);\n \tif (id != 0x62726467 /* \"BRDG\" */) {\n \t\tdev_err(dev, \"ASB register ID returned 0x%08x\\n\", id);\n--- a/include/linux/mfd/bcm2835-pm.h\n+++ b/include/linux/mfd/bcm2835-pm.h\n@@ -9,6 +9,7 @@ struct bcm2835_pm {\n \tstruct device *dev;\n \tvoid __iomem *base;\n \tvoid __iomem *asb;\n+\tvoid __iomem *arg_asb;\n };\n \n #endif /* BCM2835_MFD_PM_H */\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0136-clk-bcm2835-Add-support-for-setting-leaf-clock-rates.patch",
    "content": "From a1dcaba80910c0196b6e51111ba3890372067e0e Mon Sep 17 00:00:00 2001\nFrom: Eric Anholt <eric@anholt.net>\nDate: Thu, 2 May 2019 15:11:05 -0700\nSubject: [PATCH] clk: bcm2835: Add support for setting leaf clock\n rates while running.\n\nAs long as you wait for !BUSY, you can do glitch-free updates of clock\nrate while the clock is running.\n\nSigned-off-by: Eric Anholt <eric@anholt.net>\n---\n drivers/clk/bcm/clk-bcm2835.c | 22 +++++++++++++---------\n 1 file changed, 13 insertions(+), 9 deletions(-)\n\n--- a/drivers/clk/bcm/clk-bcm2835.c\n+++ b/drivers/clk/bcm/clk-bcm2835.c\n@@ -1110,15 +1110,19 @@ static int bcm2835_clock_set_rate(struct\n \n \tspin_lock(&cprman->regs_lock);\n \n-\t/*\n-\t * Setting up frac support\n-\t *\n-\t * In principle it is recommended to stop/start the clock first,\n-\t * but as we set CLK_SET_RATE_GATE during registration of the\n-\t * clock this requirement should be take care of by the\n-\t * clk-framework.\n+\tctl = cprman_read(cprman, data->ctl_reg);\n+\n+\t/* If the clock is running, we have to pause clock generation while\n+\t * updating the control and div regs.  This is glitchless (no clock\n+\t * signals generated faster than the rate) but each reg access is two\n+\t * OSC cycles so the clock will slow down for a moment.\n \t */\n-\tctl = cprman_read(cprman, data->ctl_reg) & ~CM_FRAC;\n+\tif (ctl & CM_ENABLE) {\n+\t\tcprman_write(cprman, data->ctl_reg, ctl & ~CM_ENABLE);\n+\t\tbcm2835_clock_wait_busy(clock);\n+\t}\n+\n+\tctl &= ~CM_FRAC;\n \tctl |= (div & CM_DIV_FRAC_MASK) ? CM_FRAC : 0;\n \tcprman_write(cprman, data->ctl_reg, ctl);\n \n@@ -1494,7 +1498,7 @@ static struct clk_hw *bcm2835_register_c\n \t\tinit.ops = &bcm2835_vpu_clock_clk_ops;\n \t} else {\n \t\tinit.ops = &bcm2835_clock_clk_ops;\n-\t\tinit.flags |= CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE;\n+\t\tinit.flags |= CLK_SET_PARENT_GATE;\n \n \t\t/* If the clock wasn't actually enabled at boot, it's not\n \t\t * critical.\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0137-clk-bcm2835-Allow-reparenting-leaf-clocks-while-they.patch",
    "content": "From c6c55ad6f9269c703e8b7f9832640dbc0390238a Mon Sep 17 00:00:00 2001\nFrom: Eric Anholt <eric@anholt.net>\nDate: Thu, 2 May 2019 15:24:04 -0700\nSubject: [PATCH] clk: bcm2835: Allow reparenting leaf clocks while\n they're running.\n\nThis falls under the same \"we can reprogram glitch-free as long as we\npause generation\" rule as updating the div/frac fields.  This can be\nused for runtime reclocking of V3D to manage power leakage.\n\nSigned-off-by: Eric Anholt <eric@anholt.net>\n---\n drivers/clk/bcm/clk-bcm2835.c | 19 ++++++++++++++++---\n 1 file changed, 16 insertions(+), 3 deletions(-)\n\n--- a/drivers/clk/bcm/clk-bcm2835.c\n+++ b/drivers/clk/bcm/clk-bcm2835.c\n@@ -1099,8 +1099,10 @@ static int bcm2835_clock_on(struct clk_h\n \treturn 0;\n }\n \n-static int bcm2835_clock_set_rate(struct clk_hw *hw,\n-\t\t\t\t  unsigned long rate, unsigned long parent_rate)\n+static int bcm2835_clock_set_rate_and_parent(struct clk_hw *hw,\n+\t\t\t\t\t     unsigned long rate,\n+\t\t\t\t\t     unsigned long parent_rate,\n+\t\t\t\t\t     u8 parent)\n {\n \tstruct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);\n \tstruct bcm2835_cprman *cprman = clock->cprman;\n@@ -1122,6 +1124,11 @@ static int bcm2835_clock_set_rate(struct\n \t\tbcm2835_clock_wait_busy(clock);\n \t}\n \n+\tif (parent != 0xff) {\n+\t\tctl &= ~(CM_SRC_MASK << CM_SRC_SHIFT);\n+\t\tctl |= parent << CM_SRC_SHIFT;\n+\t}\n+\n \tctl &= ~CM_FRAC;\n \tctl |= (div & CM_DIV_FRAC_MASK) ? CM_FRAC : 0;\n \tcprman_write(cprman, data->ctl_reg, ctl);\n@@ -1133,6 +1140,12 @@ static int bcm2835_clock_set_rate(struct\n \treturn 0;\n }\n \n+static int bcm2835_clock_set_rate(struct clk_hw *hw,\n+\t\t\t\t  unsigned long rate, unsigned long parent_rate)\n+{\n+\treturn bcm2835_clock_set_rate_and_parent(hw, rate, parent_rate, 0xff);\n+}\n+\n static bool\n bcm2835_clk_is_pllc(struct clk_hw *hw)\n {\n@@ -1316,6 +1329,7 @@ static const struct clk_ops bcm2835_cloc\n \t.unprepare = bcm2835_clock_off,\n \t.recalc_rate = bcm2835_clock_get_rate,\n \t.set_rate = bcm2835_clock_set_rate,\n+\t.set_rate_and_parent = bcm2835_clock_set_rate_and_parent,\n \t.determine_rate = bcm2835_clock_determine_rate,\n \t.set_parent = bcm2835_clock_set_parent,\n \t.get_parent = bcm2835_clock_get_parent,\n@@ -1498,7 +1512,6 @@ static struct clk_hw *bcm2835_register_c\n \t\tinit.ops = &bcm2835_vpu_clock_clk_ops;\n \t} else {\n \t\tinit.ops = &bcm2835_clock_clk_ops;\n-\t\tinit.flags |= CLK_SET_PARENT_GATE;\n \n \t\t/* If the clock wasn't actually enabled at boot, it's not\n \t\t * critical.\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0138-usb-add-plumbing-for-updating-interrupt-endpoint-int.patch",
    "content": "From e1cd62d5163e73d18b4e3083a8a09dfb9c67fd4b Mon Sep 17 00:00:00 2001\nFrom: Jonathan Bell <jonathan@raspberrypi.org>\nDate: Tue, 11 Jun 2019 10:55:00 +0100\nSubject: [PATCH] usb: add plumbing for updating interrupt endpoint\n interval state\n\nxHCI caches device and endpoint data after the interface is configured,\nso an explicit command needs to be issued for any device driver wanting\nto alter the polling interval of an endpoint.\n\nAdd usb_fixup_endpoint() to allow drivers to do this. The fixup must be\ncalled after calculating endpoint bandwidth requirements but before any\nURBs are submitted.\n\nIf polling intervals are shortened, any bandwidth reservations are no\nlonger valid but in practice polling intervals are only ever relaxed.\n\nLimit the scope to interrupt transfers for now.\n\nSigned-off-by: Jonathan Bell <jonathan@raspberrypi.org>\n---\n drivers/usb/core/hcd.c     | 10 ++++++++++\n drivers/usb/core/message.c | 15 +++++++++++++++\n include/linux/usb.h        |  2 ++\n include/linux/usb/hcd.h    |  7 +++++++\n 4 files changed, 34 insertions(+)\n\n--- a/drivers/usb/core/hcd.c\n+++ b/drivers/usb/core/hcd.c\n@@ -1966,6 +1966,16 @@ reset:\n \treturn ret;\n }\n \n+void usb_hcd_fixup_endpoint(struct usb_device *udev,\n+\t\t\t    struct usb_host_endpoint *ep, int interval)\n+{\n+\tstruct usb_hcd *hcd;\n+\n+\thcd = bus_to_hcd(udev->bus);\n+\tif (hcd->driver->fixup_endpoint)\n+\t\thcd->driver->fixup_endpoint(hcd, udev, ep, interval);\n+}\n+\n /* Disables the endpoint: synchronizes with the hcd to make sure all\n  * endpoint state is gone from hardware.  usb_hcd_flush_endpoint() must\n  * have been called previously.  Use for set_configuration, set_interface,\n--- a/drivers/usb/core/message.c\n+++ b/drivers/usb/core/message.c\n@@ -1265,6 +1265,21 @@ static void remove_intf_ep_devs(struct u\n \tintf->ep_devs_created = 0;\n }\n \n+void usb_fixup_endpoint(struct usb_device *dev, int epaddr, int interval)\n+{\n+\tunsigned int epnum = epaddr & USB_ENDPOINT_NUMBER_MASK;\n+\tstruct usb_host_endpoint *ep;\n+\n+\tif (usb_endpoint_out(epaddr))\n+\t\tep = dev->ep_out[epnum];\n+\telse\n+\t\tep = dev->ep_in[epnum];\n+\n+\tif (ep && usb_endpoint_xfer_int(&ep->desc))\n+\t\tusb_hcd_fixup_endpoint(dev, ep, interval);\n+}\n+EXPORT_SYMBOL_GPL(usb_fixup_endpoint);\n+\n /**\n  * usb_disable_endpoint -- Disable an endpoint by address\n  * @dev: the device whose endpoint is being disabled\n--- a/include/linux/usb.h\n+++ b/include/linux/usb.h\n@@ -1838,6 +1838,8 @@ extern int usb_clear_halt(struct usb_dev\n extern int usb_reset_configuration(struct usb_device *dev);\n extern int usb_set_interface(struct usb_device *dev, int ifnum, int alternate);\n extern void usb_reset_endpoint(struct usb_device *dev, unsigned int epaddr);\n+extern void usb_fixup_endpoint(struct usb_device *dev, int epaddr,\n+\t\t\t       int interval);\n \n /* this request isn't really synchronous, but it belongs with the others */\n extern int usb_driver_set_configuration(struct usb_device *udev, int config);\n--- a/include/linux/usb/hcd.h\n+++ b/include/linux/usb/hcd.h\n@@ -382,6 +382,11 @@ struct hc_driver {\n \t\t * or bandwidth constraints.\n \t\t */\n \tvoid\t(*reset_bandwidth)(struct usb_hcd *, struct usb_device *);\n+\t\t/* Override the endpoint-derived interval\n+\t\t * (if there is any cached hardware state).\n+\t\t */\n+\tvoid\t(*fixup_endpoint)(struct usb_hcd *hcd, struct usb_device *udev,\n+\t\t\t\t  struct usb_host_endpoint *ep, int interval);\n \t\t/* Returns the hardware-chosen device address */\n \tint\t(*address_device)(struct usb_hcd *, struct usb_device *udev);\n \t\t/* prepares the hardware to send commands to the device */\n@@ -443,6 +448,8 @@ extern void usb_hcd_unmap_urb_setup_for_\n extern void usb_hcd_unmap_urb_for_dma(struct usb_hcd *, struct urb *);\n extern void usb_hcd_flush_endpoint(struct usb_device *udev,\n \t\tstruct usb_host_endpoint *ep);\n+extern void usb_hcd_fixup_endpoint(struct usb_device *udev,\n+\t\tstruct usb_host_endpoint *ep, int interval);\n extern void usb_hcd_disable_endpoint(struct usb_device *udev,\n \t\tstruct usb_host_endpoint *ep);\n extern void usb_hcd_reset_endpoint(struct usb_device *udev,\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0139-xhci-implement-xhci_fixup_endpoint-for-interval-adju.patch",
    "content": "From 574aabfd5a408bc10da01bb4abe222abc013ea45 Mon Sep 17 00:00:00 2001\nFrom: Jonathan Bell <jonathan@raspberrypi.org>\nDate: Tue, 11 Jun 2019 11:33:39 +0100\nSubject: [PATCH] xhci: implement xhci_fixup_endpoint for interval\n adjustments\n\nMust be called in a non-atomic context, after the endpoint\nhas been registered with the hardware via xhci_add_endpoint\nand before the first URB is submitted for the endpoint.\n\nSigned-off-by: Jonathan Bell <jonathan@raspberrypi.org>\n---\n drivers/usb/host/xhci.c | 98 +++++++++++++++++++++++++++++++++++++++++\n 1 file changed, 98 insertions(+)\n\n--- a/drivers/usb/host/xhci.c\n+++ b/drivers/usb/host/xhci.c\n@@ -1472,6 +1472,103 @@ command_cleanup:\n }\n \n /*\n+ * RPI: Fixup endpoint intervals when requested\n+ * - Check interval versus the (cached) endpoint context\n+ * - set the endpoint interval to the new value\n+ * - force an endpoint configure command\n+ * XXX: bandwidth is not recalculated. We should probably do that.\n+ */\n+static void xhci_fixup_endpoint(struct usb_hcd *hcd, struct usb_device *udev,\n+\t\t\t\tstruct usb_host_endpoint *ep, int interval)\n+{\n+\tstruct xhci_hcd *xhci;\n+\tstruct xhci_ep_ctx *ep_ctx_out, *ep_ctx_in;\n+\tstruct xhci_command *command;\n+\tstruct xhci_input_control_ctx *ctrl_ctx;\n+\tstruct xhci_virt_device *vdev;\n+\tint xhci_interval;\n+\tint ret;\n+\tint ep_index;\n+\tunsigned long flags;\n+\tu32 ep_info_tmp;\n+\n+\txhci = hcd_to_xhci(hcd);\n+\tep_index = xhci_get_endpoint_index(&ep->desc);\n+\n+\t/* FS/LS interval translations */\n+\tif ((udev->speed == USB_SPEED_FULL ||\n+\t     udev->speed == USB_SPEED_LOW))\n+\t\tinterval *= 8;\n+\n+\tmutex_lock(&xhci->mutex);\n+\n+\tspin_lock_irqsave(&xhci->lock, flags);\n+\n+\tvdev = xhci->devs[udev->slot_id];\n+\t/* Get context-derived endpoint interval */\n+\tep_ctx_out = xhci_get_ep_ctx(xhci, vdev->out_ctx, ep_index);\n+\tep_ctx_in = xhci_get_ep_ctx(xhci, vdev->in_ctx, ep_index);\n+\txhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx_out->ep_info));\n+\n+\tif (interval == xhci_interval) {\n+\t\tspin_unlock_irqrestore(&xhci->lock, flags);\n+\t\tmutex_unlock(&xhci->mutex);\n+\t\treturn;\n+\t}\n+\n+\txhci_dbg(xhci, \"Fixup interval=%d xhci_interval=%d\\n\",\n+\t\t interval, xhci_interval);\n+\tcommand = xhci_alloc_command_with_ctx(xhci, true, GFP_ATOMIC);\n+\tif (!command) {\n+\t\t/* Failure here is benign, poll at the original rate */\n+\t\tspin_unlock_irqrestore(&xhci->lock, flags);\n+\t\tmutex_unlock(&xhci->mutex);\n+\t\treturn;\n+\t}\n+\n+\t/* xHCI uses exponents for intervals... */\n+\txhci_interval = fls(interval) - 1;\n+\txhci_interval = clamp_val(xhci_interval, 3, 10);\n+\tep_info_tmp = le32_to_cpu(ep_ctx_out->ep_info);\n+\tep_info_tmp &= ~EP_INTERVAL(255);\n+\tep_info_tmp |= EP_INTERVAL(xhci_interval);\n+\n+\t/* Keep the endpoint context up-to-date while issuing the command. */\n+\txhci_endpoint_copy(xhci, vdev->in_ctx,\n+\t\t\t   vdev->out_ctx, ep_index);\n+\tep_ctx_in->ep_info = cpu_to_le32(ep_info_tmp);\n+\n+\t/*\n+\t * We need to drop the lock, so take an explicit copy\n+\t * of the ep context.\n+\t */\n+\txhci_endpoint_copy(xhci, command->in_ctx, vdev->in_ctx, ep_index);\n+\n+\tctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);\n+\tif (!ctrl_ctx) {\n+\t\txhci_warn(xhci,\n+\t\t\t  \"%s: Could not get input context, bad type.\\n\",\n+\t\t\t  __func__);\n+\t\tspin_unlock_irqrestore(&xhci->lock, flags);\n+\t\txhci_free_command(xhci, command);\n+\t\tmutex_unlock(&xhci->mutex);\n+\t\treturn;\n+\t}\n+\tctrl_ctx->add_flags = xhci_get_endpoint_flag_from_index(ep_index);\n+\tctrl_ctx->drop_flags = 0;\n+\n+\tspin_unlock_irqrestore(&xhci->lock, flags);\n+\n+\tret = xhci_configure_endpoint(xhci, udev, command,\n+\t\t\t\t      false, false);\n+\tif (ret)\n+\t\txhci_warn(xhci, \"%s: Configure endpoint failed: %d\\n\",\n+\t\t\t  __func__, ret);\n+\txhci_free_command(xhci, command);\n+\tmutex_unlock(&xhci->mutex);\n+}\n+\n+/*\n  * non-error returns are a promise to giveback() the urb later\n  * we drop ownership so next owner (or urb unlink) can get it\n  */\n@@ -5378,6 +5475,7 @@ static const struct hc_driver xhci_hc_dr\n \t.endpoint_reset =\txhci_endpoint_reset,\n \t.check_bandwidth =\txhci_check_bandwidth,\n \t.reset_bandwidth =\txhci_reset_bandwidth,\n+\t.fixup_endpoint =\txhci_fixup_endpoint,\n \t.address_device =\txhci_address_device,\n \t.enable_device =\txhci_enable_device,\n \t.update_hub_device =\txhci_update_hub_device,\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0140-usbhid-call-usb_fixup_endpoint-after-mangling-interv.patch",
    "content": "From 39deae2e4d179df6532687902948a84c39bb2f34 Mon Sep 17 00:00:00 2001\nFrom: Jonathan Bell <jonathan@raspberrypi.org>\nDate: Tue, 11 Jun 2019 11:42:03 +0100\nSubject: [PATCH] usbhid: call usb_fixup_endpoint after mangling\n intervals\n\nLets the mousepoll override mechanism work with xhci.\n\nSigned-off-by: Jonathan Bell <jonathan@raspberrypi.org>\n---\n drivers/hid/usbhid/hid-core.c | 1 +\n 1 file changed, 1 insertion(+)\n\n--- a/drivers/hid/usbhid/hid-core.c\n+++ b/drivers/hid/usbhid/hid-core.c\n@@ -1128,6 +1128,7 @@ static int usbhid_start(struct hid_devic\n \t\t\t\tinterval = hid_kbpoll_interval;\n \t\t\tbreak;\n \t\t}\n+\t\tusb_fixup_endpoint(dev, endpoint->bEndpointAddress, interval);\n \n \t\tret = -ENOMEM;\n \t\tif (usb_endpoint_dir_in(endpoint)) {\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0141-arm-bcm2835-Add-bcm2838-compatible-string.patch",
    "content": "From a085d0f6d2eddd876becfbc6b658fd1d6db5cd0b Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.org>\nDate: Tue, 11 Jun 2019 17:38:28 +0100\nSubject: [PATCH] arm: bcm2835: Add bcm2838 compatible string.\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.org>\n---\n arch/arm/mach-bcm/board_bcm2835.c | 1 +\n 1 file changed, 1 insertion(+)\n\n--- a/arch/arm/mach-bcm/board_bcm2835.c\n+++ b/arch/arm/mach-bcm/board_bcm2835.c\n@@ -109,6 +109,7 @@ static const char * const bcm2835_compat\n #ifdef CONFIG_ARCH_MULTI_V7\n \t\"brcm,bcm2836\",\n \t\"brcm,bcm2837\",\n+\t\"brcm,bcm2838\",\n #endif\n \tNULL\n };\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0142-drm-v3d-Add-support-for-2711.patch",
    "content": "From c124b2797bc42c9363345581e233a53d811d72af Mon Sep 17 00:00:00 2001\nFrom: Eric Anholt <eric@anholt.net>\nDate: Thu, 4 Oct 2018 17:22:43 -0700\nSubject: [PATCH] drm/v3d: Add support for 2711.\n\nSigned-off-by: Eric Anholt <eric@anholt.net>\n---\n drivers/gpu/drm/v3d/v3d_drv.c | 1 +\n 1 file changed, 1 insertion(+)\n\n--- a/drivers/gpu/drm/v3d/v3d_drv.c\n+++ b/drivers/gpu/drm/v3d/v3d_drv.c\n@@ -227,6 +227,7 @@ static struct drm_driver v3d_drm_driver\n static const struct of_device_id v3d_of_match[] = {\n \t{ .compatible = \"brcm,7268-v3d\" },\n \t{ .compatible = \"brcm,7278-v3d\" },\n+\t{ .compatible = \"brcm,2711-v3d\" },\n \t{},\n };\n MODULE_DEVICE_TABLE(of, v3d_of_match);\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0143-drm-v3d-Skip-MMU-flush-if-the-device-is-currently-of.patch",
    "content": "From ca945515e1a3be554e654823d6a27403d43318c2 Mon Sep 17 00:00:00 2001\nFrom: Eric Anholt <eric@anholt.net>\nDate: Mon, 14 Jan 2019 12:35:43 -0800\nSubject: [PATCH] drm/v3d: Skip MMU flush if the device is currently\n off.\n\nIf it's off, we know it will be reset on poweron, so the MMU won't\nhave any TLB cached from before this point.  Avoids failed waits for\nMMU flush to reply.\n\nSigned-off-by: Eric Anholt <eric@anholt.net>\n(cherry picked from commit 3ee4e2e0a9e9587eacbb69b067bbc72ab2cdc47b)\n---\n drivers/gpu/drm/v3d/v3d_mmu.c | 13 +++++++++++++\n 1 file changed, 13 insertions(+)\n\n--- a/drivers/gpu/drm/v3d/v3d_mmu.c\n+++ b/drivers/gpu/drm/v3d/v3d_mmu.c\n@@ -18,6 +18,8 @@\n  * each client.  This is not yet implemented.\n  */\n \n+#include <linux/pm_runtime.h>\n+\n #include \"v3d_drv.h\"\n #include \"v3d_regs.h\"\n \n@@ -34,6 +36,14 @@ static int v3d_mmu_flush_all(struct v3d_\n {\n \tint ret;\n \n+\t/* Keep power on the device on until we're done with this\n+\t * call, but skip the flush if the device is off and will be\n+\t * reset when powered back on.\n+\t */\n+\tret = pm_runtime_get_if_in_use(v3d->dev);\n+\tif (ret == 0)\n+\t\treturn 0;\n+\n \t/* Make sure that another flush isn't already running when we\n \t * start this one.\n \t */\n@@ -61,6 +71,9 @@ static int v3d_mmu_flush_all(struct v3d_\n \tif (ret)\n \t\tdev_err(v3d->drm.dev, \"MMUC flush wait idle failed\\n\");\n \n+\tpm_runtime_mark_last_busy(v3d->dev);\n+\tpm_runtime_put_autosuspend(v3d->dev);\n+\n \treturn ret;\n }\n \n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0144-drm-v3d-Hook-up-the-runtime-PM-ops.patch",
    "content": "From e7398ddc64a8540bb016d653ff0bddfc0660f606 Mon Sep 17 00:00:00 2001\nFrom: Eric Anholt <eric@anholt.net>\nDate: Mon, 14 Jan 2019 14:47:57 -0800\nSubject: [PATCH] drm/v3d: Hook up the runtime PM ops.\n\nIn translating the runtime PM code from vc4, I missed the \".pm\"\nassignment to actually connect them up.  Fixes missing MMU setup if\nruntime PM resets V3D.\n\nSigned-off-by: Eric Anholt <eric@anholt.net>\n(cherry picked from commit ca197699af29baa8236c74c53d4904ca8957ee06)\n---\n drivers/gpu/drm/v3d/v3d_drv.c | 3 ++-\n 1 file changed, 2 insertions(+), 1 deletion(-)\n\n--- a/drivers/gpu/drm/v3d/v3d_drv.c\n+++ b/drivers/gpu/drm/v3d/v3d_drv.c\n@@ -70,7 +70,7 @@ static int v3d_runtime_resume(struct dev\n }\n #endif\n \n-static const struct dev_pm_ops v3d_v3d_pm_ops = {\n+static const struct dev_pm_ops v3d_pm_ops = {\n \tSET_RUNTIME_PM_OPS(v3d_runtime_suspend, v3d_runtime_resume, NULL)\n };\n \n@@ -356,6 +356,7 @@ static struct platform_driver v3d_platfo\n \t.driver\t\t= {\n \t\t.name\t= \"v3d\",\n \t\t.of_match_table = v3d_of_match,\n+\t\t.pm = &v3d_pm_ops,\n \t},\n };\n \n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0146-i2c-bcm2835-Set-clock-stretch-timeout-to-35ms.patch",
    "content": "From 930c69b932959ad237347ca02b31bf1e9ebf227a Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.org>\nDate: Fri, 12 Jul 2019 15:38:35 +0100\nSubject: [PATCH] i2c: bcm2835: Set clock-stretch timeout to 35ms\n\nThe BCM2835 I2C blocks have a register to set the clock-stretch\ntimeout - how long the device is allowed to hold SCL low - in bus\ncycles. The current driver doesn't write to the register, therefore\nthe default value of 64 cycles is being used for all devices.\n\nSet the timeout to the value recommended for SMBus - 35ms.\n\nSee: https://github.com/raspberrypi/linux/issues/3064\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.org>\n---\n drivers/i2c/busses/i2c-bcm2835.c | 12 ++++++++++++\n 1 file changed, 12 insertions(+)\n\n--- a/drivers/i2c/busses/i2c-bcm2835.c\n+++ b/drivers/i2c/busses/i2c-bcm2835.c\n@@ -193,6 +193,7 @@ static int clk_bcm2835_i2c_set_rate(stru\n {\n \tstruct clk_bcm2835_i2c *div = to_clk_bcm2835_i2c(hw);\n \tu32 redl, fedl;\n+\tu32 clk_tout;\n \tu32 divider = clk_bcm2835_i2c_calc_divider(rate, parent_rate);\n \n \tif (divider == -EINVAL)\n@@ -216,6 +217,17 @@ static int clk_bcm2835_i2c_set_rate(stru\n \tbcm2835_i2c_writel(div->i2c_dev, BCM2835_I2C_DEL,\n \t\t\t   (fedl << BCM2835_I2C_FEDL_SHIFT) |\n \t\t\t   (redl << BCM2835_I2C_REDL_SHIFT));\n+\n+\t/*\n+\t * Set the clock stretch timeout to the SMBUs-recommended 35ms.\n+\t */\n+\tif (rate > 0xffff*1000/35)\n+\t    clk_tout = 0xffff;\n+\telse\n+\t    clk_tout = 35*rate/1000;\n+\n+\tbcm2835_i2c_writel(div->i2c_dev, BCM2835_I2C_CLKT, clk_tout);\n+\n \treturn 0;\n }\n \n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0147-clk-bcm2835-Avoid-null-pointer-exception.patch",
    "content": "From 17e36f484c42177981279d791cbc55a43c5d5a12 Mon Sep 17 00:00:00 2001\nFrom: popcornmix <popcornmix@gmail.com>\nDate: Tue, 6 Aug 2019 15:23:14 +0100\nSubject: [PATCH] clk-bcm2835: Avoid null pointer exception\n\nclk_desc_array[BCM2835_PLLB] doesn't exist so we dereference null when iterating\n\nSigned-off-by: popcornmix <popcornmix@gmail.com>\n---\n drivers/clk/bcm/clk-bcm2835.c | 8 +++++---\n 1 file changed, 5 insertions(+), 3 deletions(-)\n\n--- a/drivers/clk/bcm/clk-bcm2835.c\n+++ b/drivers/clk/bcm/clk-bcm2835.c\n@@ -2305,9 +2305,11 @@ static bool bcm2835_clk_is_claimed(const\n \tint i;\n \n \tfor (i = 0; i < ARRAY_SIZE(clk_desc_array); i++) {\n-\t\tconst char *clk_name = *(const char **)(clk_desc_array[i].data);\n-\t\tif (!strcmp(name, clk_name))\n-\t\t    return bcm2835_clk_claimed[i];\n+\t\tif (clk_desc_array[i].data) {\n+\t\t\tconst char *clk_name = *(const char **)(clk_desc_array[i].data);\n+\t\t\tif (!strcmp(name, clk_name))\n+\t\t\t\treturn bcm2835_clk_claimed[i];\n+\t\t}\n \t}\n \n \treturn false;\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0148-drm-v3d-HACK-gut-runtime-pm-for-now.patch",
    "content": "From 1480a99bfef66b0c0f07c90436a873937b656ce7 Mon Sep 17 00:00:00 2001\nFrom: Eric Anholt <eric@anholt.net>\nDate: Mon, 14 Jan 2019 15:13:17 -0800\nSubject: [PATCH] drm/v3d: HACK: gut runtime pm for now.\n\nSomething is still unstable -- on starting a new glxgears from an idle\nX11, I get an MMU violation in high addresses.  The CTS also failed\nquite quickly.  With this, CTS progresses for an hour before OOMing\n(allocating some big buffers when my board only has 600MB available to\nLinux)\n\nSigned-off-by: Eric Anholt <eric@anholt.net>\n---\n drivers/gpu/drm/v3d/v3d_debugfs.c | 16 +---------------\n drivers/gpu/drm/v3d/v3d_drv.c     |  9 ---------\n 2 files changed, 1 insertion(+), 24 deletions(-)\n\n--- a/drivers/gpu/drm/v3d/v3d_debugfs.c\n+++ b/drivers/gpu/drm/v3d/v3d_debugfs.c\n@@ -4,7 +4,6 @@\n #include <linux/circ_buf.h>\n #include <linux/ctype.h>\n #include <linux/debugfs.h>\n-#include <linux/pm_runtime.h>\n #include <linux/seq_file.h>\n \n #include <drm/drm_debugfs.h>\n@@ -130,11 +129,8 @@ static int v3d_v3d_debugfs_ident(struct\n \tstruct drm_device *dev = node->minor->dev;\n \tstruct v3d_dev *v3d = to_v3d_dev(dev);\n \tu32 ident0, ident1, ident2, ident3, cores;\n-\tint ret, core;\n+\tint core;\n \n-\tret = pm_runtime_get_sync(v3d->drm.dev);\n-\tif (ret < 0)\n-\t\treturn ret;\n \n \tident0 = V3D_READ(V3D_HUB_IDENT0);\n \tident1 = V3D_READ(V3D_HUB_IDENT1);\n@@ -187,9 +183,6 @@ static int v3d_v3d_debugfs_ident(struct\n \t\t\t   (misccfg & V3D_MISCCFG_OVRTMUOUT) != 0);\n \t}\n \n-\tpm_runtime_mark_last_busy(v3d->drm.dev);\n-\tpm_runtime_put_autosuspend(v3d->drm.dev);\n-\n \treturn 0;\n }\n \n@@ -217,11 +210,6 @@ static int v3d_measure_clock(struct seq_\n \tuint32_t cycles;\n \tint core = 0;\n \tint measure_ms = 1000;\n-\tint ret;\n-\n-\tret = pm_runtime_get_sync(v3d->drm.dev);\n-\tif (ret < 0)\n-\t\treturn ret;\n \n \tif (v3d->ver >= 40) {\n \t\tV3D_CORE_WRITE(core, V3D_V4_PCTR_0_SRC_0_3,\n@@ -245,8 +233,6 @@ static int v3d_measure_clock(struct seq_\n \t\t   cycles / (measure_ms * 1000),\n \t\t   (cycles / (measure_ms * 100)) % 10);\n \n-\tpm_runtime_mark_last_busy(v3d->drm.dev);\n-\tpm_runtime_put_autosuspend(v3d->drm.dev);\n \n \treturn 0;\n }\n--- a/drivers/gpu/drm/v3d/v3d_drv.c\n+++ b/drivers/gpu/drm/v3d/v3d_drv.c\n@@ -79,7 +79,6 @@ static int v3d_get_param_ioctl(struct dr\n {\n \tstruct v3d_dev *v3d = to_v3d_dev(dev);\n \tstruct drm_v3d_get_param *args = data;\n-\tint ret;\n \tstatic const u32 reg_map[] = {\n \t\t[DRM_V3D_PARAM_V3D_UIFCFG] = V3D_HUB_UIFCFG,\n \t\t[DRM_V3D_PARAM_V3D_HUB_IDENT1] = V3D_HUB_IDENT1,\n@@ -105,17 +104,12 @@ static int v3d_get_param_ioctl(struct dr\n \t\tif (args->value != 0)\n \t\t\treturn -EINVAL;\n \n-\t\tret = pm_runtime_get_sync(v3d->drm.dev);\n-\t\tif (ret < 0)\n-\t\t\treturn ret;\n \t\tif (args->param >= DRM_V3D_PARAM_V3D_CORE0_IDENT0 &&\n \t\t    args->param <= DRM_V3D_PARAM_V3D_CORE0_IDENT2) {\n \t\t\targs->value = V3D_CORE_READ(0, offset);\n \t\t} else {\n \t\t\targs->value = V3D_READ(offset);\n \t\t}\n-\t\tpm_runtime_mark_last_busy(v3d->drm.dev);\n-\t\tpm_runtime_put_autosuspend(v3d->drm.dev);\n \t\treturn 0;\n \t}\n \n@@ -308,9 +302,6 @@ static int v3d_platform_drm_probe(struct\n \t\treturn -ENOMEM;\n \t}\n \n-\tpm_runtime_use_autosuspend(dev);\n-\tpm_runtime_set_autosuspend_delay(dev, 50);\n-\tpm_runtime_enable(dev);\n \n \tret = v3d_gem_init(drm);\n \tif (ret)\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0149-drm-v3d-Clock-V3D-down-when-not-in-use.patch",
    "content": "From 6a9c9cba52a98a3ca380d43c5a12ef4fc190276d Mon Sep 17 00:00:00 2001\nFrom: Eric Anholt <eric@anholt.net>\nDate: Thu, 2 May 2019 13:22:53 -0700\nSubject: [PATCH] drm/v3d: Clock V3D down when not in use.\n\nMy various attempts at re-enabling runtime PM have failed, so just\ncrank the clock down when V3D is idle to reduce power consumption.\n\nSigned-off-by: Eric Anholt <eric@anholt.net>\n---\n drivers/gpu/drm/v3d/v3d_drv.c | 18 ++++++++++++\n drivers/gpu/drm/v3d/v3d_drv.h |  6 ++++\n drivers/gpu/drm/v3d/v3d_gem.c | 53 +++++++++++++++++++++++++++++++----\n 3 files changed, 72 insertions(+), 5 deletions(-)\n\n--- a/drivers/gpu/drm/v3d/v3d_drv.c\n+++ b/drivers/gpu/drm/v3d/v3d_drv.c\n@@ -289,6 +289,21 @@ static int v3d_platform_drm_probe(struct\n \t\t}\n \t}\n \n+\tv3d->clk = devm_clk_get(dev, NULL);\n+\tif (IS_ERR(v3d->clk)) {\n+\t\tif (ret != -EPROBE_DEFER)\n+\t\t\tdev_err(dev, \"Failed to get clock\\n\");\n+\t\tgoto dev_free;\n+\t}\n+\tv3d->clk_up_rate = clk_get_rate(v3d->clk);\n+\t/* For downclocking, drop it to the minimum frequency we can get from\n+\t * the CPRMAN clock generator dividing off our parent.  The divider is\n+\t * 4 bits, but ask for just higher than that so that rounding doesn't\n+\t * make cprman reject our rate.\n+\t */\n+\tv3d->clk_down_rate =\n+\t\t(clk_get_rate(clk_get_parent(v3d->clk)) / (1 << 4)) + 10000;\n+\n \tif (v3d->ver < 41) {\n \t\tret = map_regs(v3d, &v3d->gca_regs, \"gca\");\n \t\tif (ret)\n@@ -315,6 +330,9 @@ static int v3d_platform_drm_probe(struct\n \tif (ret)\n \t\tgoto irq_disable;\n \n+\tret = clk_set_rate(v3d->clk, v3d->clk_down_rate);\n+\tWARN_ON_ONCE(ret != 0);\n+\n \treturn 0;\n \n irq_disable:\n--- a/drivers/gpu/drm/v3d/v3d_drv.h\n+++ b/drivers/gpu/drm/v3d/v3d_drv.h\n@@ -51,6 +51,12 @@ struct v3d_dev {\n \tvoid __iomem *bridge_regs;\n \tvoid __iomem *gca_regs;\n \tstruct clk *clk;\n+\tstruct delayed_work clk_down_work;\n+\tunsigned long clk_up_rate, clk_down_rate;\n+\tstruct mutex clk_lock;\n+\tu32 clk_refcount;\n+\tbool clk_up;\n+\n \tstruct reset_control *reset;\n \n \t/* Virtual and DMA addresses of the single shared page table. */\n--- a/drivers/gpu/drm/v3d/v3d_gem.c\n+++ b/drivers/gpu/drm/v3d/v3d_gem.c\n@@ -4,6 +4,7 @@\n #include <linux/device.h>\n #include <linux/dma-mapping.h>\n #include <linux/io.h>\n+#include <linux/clk.h>\n #include <linux/module.h>\n #include <linux/platform_device.h>\n #include <linux/pm_runtime.h>\n@@ -19,6 +20,47 @@\n #include \"v3d_trace.h\"\n \n static void\n+v3d_clock_down_work(struct work_struct *work)\n+{\n+\tstruct v3d_dev *v3d =\n+\t\tcontainer_of(work, struct v3d_dev, clk_down_work.work);\n+\tint ret;\n+\n+\tret = clk_set_rate(v3d->clk, v3d->clk_down_rate);\n+\tv3d->clk_up = false;\n+\tWARN_ON_ONCE(ret != 0);\n+}\n+\n+static void\n+v3d_clock_up_get(struct v3d_dev *v3d)\n+{\n+\tmutex_lock(&v3d->clk_lock);\n+\tif (v3d->clk_refcount++ == 0) {\n+\t\tcancel_delayed_work_sync(&v3d->clk_down_work);\n+\t\tif (!v3d->clk_up)  {\n+\t\t\tint ret;\n+\n+\t\t\tret = clk_set_rate(v3d->clk, v3d->clk_up_rate);\n+\t\t\tWARN_ON_ONCE(ret != 0);\n+\t\t\tv3d->clk_up = true;\n+\t\t}\n+\t}\n+\tmutex_unlock(&v3d->clk_lock);\n+}\n+\n+static void\n+v3d_clock_up_put(struct v3d_dev *v3d)\n+{\n+\tmutex_lock(&v3d->clk_lock);\n+\tif (--v3d->clk_refcount == 0) {\n+\t\tschedule_delayed_work(&v3d->clk_down_work,\n+\t\t\t\t      msecs_to_jiffies(100));\n+\t}\n+\tmutex_unlock(&v3d->clk_lock);\n+}\n+\n+\n+static void\n v3d_init_core(struct v3d_dev *v3d, int core)\n {\n \t/* Set OVRTMUOUT, which means that the texture sampler uniform\n@@ -354,6 +396,7 @@ v3d_job_free(struct kref *ref)\n \tstruct v3d_job *job = container_of(ref, struct v3d_job, refcount);\n \tunsigned long index;\n \tstruct dma_fence *fence;\n+\tstruct v3d_dev *v3d = job->v3d;\n \tint i;\n \n \tfor (i = 0; i < job->bo_count; i++) {\n@@ -367,11 +410,7 @@ v3d_job_free(struct kref *ref)\n \t}\n \txa_destroy(&job->deps);\n \n-\tdma_fence_put(job->irq_fence);\n-\tdma_fence_put(job->done_fence);\n-\n-\tpm_runtime_mark_last_busy(job->v3d->drm.dev);\n-\tpm_runtime_put_autosuspend(job->v3d->drm.dev);\n+\tv3d_clock_up_put(v3d);\n \n \tkfree(job);\n }\n@@ -453,6 +492,7 @@ v3d_job_init(struct v3d_dev *v3d, struct\n \tif (ret)\n \t\tgoto fail;\n \n+\tv3d_clock_up_get(v3d);\n \tkref_init(&job->refcount);\n \n \treturn 0;\n@@ -879,6 +919,9 @@ v3d_gem_init(struct drm_device *dev)\n \tmutex_init(&v3d->sched_lock);\n \tmutex_init(&v3d->cache_clean_lock);\n \n+\tmutex_init(&v3d->clk_lock);\n+\tINIT_DELAYED_WORK(&v3d->clk_down_work, v3d_clock_down_work);\n+\n \t/* Note: We don't allocate address 0.  Various bits of HW\n \t * treat 0 as special, such as the occlusion query counters\n \t * where 0 means \"disabled\".\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0150-drivers-char-add-chardev-for-mmap-ing-the-RPiVid-con.patch",
    "content": "From e264c7d05860aa12664fa3db8bcf8c4cbc20a62e Mon Sep 17 00:00:00 2001\nFrom: Jonathan Bell <jonathan@raspberrypi.org>\nDate: Thu, 9 May 2019 14:30:37 +0100\nSubject: [PATCH] drivers: char: add chardev for mmap'ing the RPiVid\n control registers\n\nBased on the gpiomem driver, allow mapping of the decoder register\nspaces such that userspace can access control/status registers.\nThis driver is intended for use with a custom ffmpeg backend accelerator\nprior to a v4l2 driver being written.\n\nSigned-off-by: Jonathan Bell <jonathan@raspberrypi.org>\n\ndriver: char: rpivid: Destroy the legacy device on remove\n\nThe legacy name support created a new device that was never destroyed.\nIf the driver was unloaded and reloaded, it failed due to the\ndevice already existing.\n\nFixes: \"75f1d14 driver: char: rpivid - also support legacy name\"\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n\ndriver: char: rpivid: Clean up error handling use of ERR_PTR/IS_ERR\n\nThe driver used an unnecessary intermediate void* variable so it\nonly called ERR_PTR once to convert to the error value.\n\nSwitch to converting as the error arises to remove these intermediate\nvariables.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n\ndriver: char: rpivid: Add error handling to the legacy device load\n\nThe return value from device_create for the legacy device was never\nchecked or handled. Add the required error handling.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n\ndriver: char: rpivid: Fix coding style whitespace issues.\n\nMakes checkpatch happier.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n\ndriver: char: rpimem: Add SPDX licence header.\n\nStops checkpatch complaining.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n\ndriver: char: rpivid: Fix access to freed memory\n\nThe error path during probe frees the private memory block, and\nthen promptly dereferences it to log an error message.\n\nUse the base device instead of the pointer to it in the private\nstructure.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n drivers/char/broadcom/Kconfig      |   8 +\n drivers/char/broadcom/Makefile     |   1 +\n drivers/char/broadcom/rpivid-mem.c | 292 +++++++++++++++++++++++++++++\n drivers/mfd/bcm2835-pm.c           |  12 +-\n drivers/soc/bcm/bcm2835-power.c    |   6 +-\n include/linux/mfd/bcm2835-pm.h     |   2 +-\n 6 files changed, 311 insertions(+), 10 deletions(-)\n create mode 100644 drivers/char/broadcom/rpivid-mem.c\n\n--- a/drivers/char/broadcom/Kconfig\n+++ b/drivers/char/broadcom/Kconfig\n@@ -39,3 +39,11 @@ config BCM2835_SMI_DEV\n \t\tThis driver provides a character device interface (ioctl + read/write) to\n \t\tBroadcom's Secondary Memory interface. The low-level functionality is provided\n \t\tby the SMI driver itself.\n+\n+config RPIVID_MEM\n+\ttristate \"Character device driver for the Raspberry Pi RPIVid video decoder hardware\"\n+\tdefault n\n+\thelp\n+\t\tThis driver provides a character device interface for memory-map operations\n+\t\tso userspace tools can access the control and status registers of the\n+\t\tRaspberry Pi RPiVid video decoder hardware.\n--- a/drivers/char/broadcom/Makefile\n+++ b/drivers/char/broadcom/Makefile\n@@ -2,3 +2,4 @@ obj-$(CONFIG_BCM2708_VCMEM)\t+= vc_mem.o\n obj-$(CONFIG_BCM_VCIO)\t\t+= vcio.o\n obj-$(CONFIG_BCM2835_DEVGPIOMEM)+= bcm2835-gpiomem.o\n obj-$(CONFIG_BCM2835_SMI_DEV)\t+= bcm2835_smi_dev.o\n+obj-$(CONFIG_RPIVID_MEM)\t+= rpivid-mem.o\n--- /dev/null\n+++ b/drivers/char/broadcom/rpivid-mem.c\n@@ -0,0 +1,292 @@\n+// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause\n+/**\n+ * rpivid-mem.c - character device access to the RPiVid decoder registers\n+ *\n+ * Based on bcm2835-gpiomem.c. Provides IO memory access to the decoder\n+ * register blocks such that ffmpeg plugins can access the hardware.\n+ *\n+ * Jonathan Bell <jonathan@raspberrypi.org>\n+ * Copyright (c) 2019, Raspberry Pi (Trading) Ltd.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ * 1. Redistributions of source code must retain the above copyright\n+ *    notice, this list of conditions, and the following disclaimer,\n+ *    without modification.\n+ * 2. Redistributions in binary form must reproduce the above copyright\n+ *    notice, this list of conditions and the following disclaimer in the\n+ *    documentation and/or other materials provided with the distribution.\n+ * 3. The names of the above-listed copyright holders may not be used\n+ *    to endorse or promote products derived from this software without\n+ *    specific prior written permission.\n+ *\n+ * ALTERNATIVELY, this software may be distributed under the terms of the\n+ * GNU General Public License (\"GPL\") version 2, as published by the Free\n+ * Software Foundation.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS\n+ * IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,\n+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\n+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR\n+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\n+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\n+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR\n+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\n+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\n+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+#include <linux/kernel.h>\n+#include <linux/module.h>\n+#include <linux/of.h>\n+#include <linux/of_device.h>\n+#include <linux/platform_device.h>\n+#include <linux/mm.h>\n+#include <linux/slab.h>\n+#include <linux/cdev.h>\n+#include <linux/pagemap.h>\n+#include <linux/io.h>\n+\n+#define DRIVER_NAME \"rpivid-mem\"\n+#define DEVICE_MINOR 0\n+\n+struct rpivid_mem_priv {\n+\tdev_t devid;\n+\tstruct class *class;\n+\tstruct cdev rpivid_mem_cdev;\n+\tunsigned long regs_phys;\n+\tunsigned long mem_window_len;\n+\tstruct device *dev;\n+\tconst char *name;\n+};\n+\n+static int rpivid_mem_open(struct inode *inode, struct file *file)\n+{\n+\tint dev = iminor(inode);\n+\tint ret = 0;\n+\tstruct rpivid_mem_priv *priv;\n+\n+\tif (dev != DEVICE_MINOR && dev != DEVICE_MINOR + 1)\n+\t\tret = -ENXIO;\n+\n+\tpriv = container_of(inode->i_cdev, struct rpivid_mem_priv,\n+\t\t\t\trpivid_mem_cdev);\n+\tif (!priv)\n+\t\treturn -EINVAL;\n+\tfile->private_data = priv;\n+\treturn ret;\n+}\n+\n+static int rpivid_mem_release(struct inode *inode, struct file *file)\n+{\n+\tint dev = iminor(inode);\n+\tint ret = 0;\n+\n+\tif (dev != DEVICE_MINOR && dev != DEVICE_MINOR + 1)\n+\t\tret = -ENXIO;\n+\n+\treturn ret;\n+}\n+\n+static const struct vm_operations_struct rpivid_mem_vm_ops = {\n+#ifdef CONFIG_HAVE_IOREMAP_PROT\n+\t.access = generic_access_phys\n+#endif\n+};\n+\n+static int rpivid_mem_mmap(struct file *file, struct vm_area_struct *vma)\n+{\n+\tstruct rpivid_mem_priv *priv;\n+\tunsigned long pages;\n+\n+\tpriv = file->private_data;\n+\tpages = priv->regs_phys >> PAGE_SHIFT;\n+\t/*\n+\t * The address decode is far larger than the actual number of registers.\n+\t * Just map the whole lot in.\n+\t */\n+\tvma->vm_page_prot = phys_mem_access_prot(file, pages,\n+\t\t\t\t\t\t priv->mem_window_len,\n+\t\t\t\t\t\t vma->vm_page_prot);\n+\tvma->vm_ops = &rpivid_mem_vm_ops;\n+\tif (remap_pfn_range(vma, vma->vm_start,\n+\t\t\tpages,\n+\t\t\tpriv->mem_window_len,\n+\t\t\tvma->vm_page_prot)) {\n+\t\treturn -EAGAIN;\n+\t}\n+\treturn 0;\n+}\n+\n+static const struct file_operations\n+rpivid_mem_fops = {\n+\t.owner = THIS_MODULE,\n+\t.open = rpivid_mem_open,\n+\t.release = rpivid_mem_release,\n+\t.mmap = rpivid_mem_mmap,\n+};\n+\n+static const struct of_device_id rpivid_mem_of_match[];\n+static int rpivid_mem_probe(struct platform_device *pdev)\n+{\n+\tint err;\n+\tconst struct of_device_id *id;\n+\tstruct device *dev = &pdev->dev;\n+\tstruct resource *ioresource;\n+\tstruct rpivid_mem_priv *priv;\n+\n+\t/* Allocate buffers and instance data */\n+\n+\tpriv = kzalloc(sizeof(struct rpivid_mem_priv), GFP_KERNEL);\n+\n+\tif (!priv) {\n+\t\terr = -ENOMEM;\n+\t\tgoto failed_inst_alloc;\n+\t}\n+\tplatform_set_drvdata(pdev, priv);\n+\n+\tpriv->dev = dev;\n+\tid = of_match_device(rpivid_mem_of_match, dev);\n+\tif (!id)\n+\t\treturn -EINVAL;\n+\tpriv->name = id->data;\n+\n+\tioresource = platform_get_resource(pdev, IORESOURCE_MEM, 0);\n+\tif (ioresource) {\n+\t\tpriv->regs_phys = ioresource->start;\n+\t\tpriv->mem_window_len = ioresource->end - ioresource->start;\n+\t} else {\n+\t\tdev_err(priv->dev, \"failed to get IO resource\");\n+\t\terr = -ENOENT;\n+\t\tgoto failed_get_resource;\n+\t}\n+\n+\t/* Create character device entries */\n+\n+\terr = alloc_chrdev_region(&priv->devid,\n+\t\t\t\t  DEVICE_MINOR, 2, priv->name);\n+\tif (err != 0) {\n+\t\tdev_err(priv->dev, \"unable to allocate device number\");\n+\t\tgoto failed_alloc_chrdev;\n+\t}\n+\tcdev_init(&priv->rpivid_mem_cdev, &rpivid_mem_fops);\n+\tpriv->rpivid_mem_cdev.owner = THIS_MODULE;\n+\terr = cdev_add(&priv->rpivid_mem_cdev, priv->devid, 2);\n+\tif (err != 0) {\n+\t\tdev_err(priv->dev, \"unable to register device\");\n+\t\tgoto failed_cdev_add;\n+\t}\n+\n+\t/* Create sysfs entries */\n+\n+\tpriv->class = class_create(THIS_MODULE, priv->name);\n+\tif (IS_ERR(priv->class)) {\n+\t\terr = PTR_ERR(priv->class);\n+\t\tgoto failed_class_create;\n+\t}\n+\n+\tdev = device_create(priv->class, NULL, priv->devid, NULL, priv->name);\n+\tif (IS_ERR(dev)) {\n+\t\terr = PTR_ERR(dev);\n+\t\tgoto failed_device_create;\n+\t}\n+\n+\t/* Legacy alias */\n+\t{\n+\t\tchar *oldname = kstrdup(priv->name, GFP_KERNEL);\n+\n+\t\toldname[1] = 'a';\n+\t\toldname[2] = 'r';\n+\t\toldname[3] = 'g';\n+\t\toldname[4] = 'o';\n+\t\toldname[5] = 'n';\n+\t\tdev = device_create(priv->class, NULL, priv->devid + 1, NULL,\n+\t\t\t\t    oldname + 1);\n+\t\tkfree(oldname);\n+\n+\t\tif (IS_ERR(dev)) {\n+\t\t\terr = PTR_ERR(dev);\n+\t\t\tgoto failed_legacy_device_create;\n+\t\t}\n+\t}\n+\n+\tdev_info(priv->dev, \"%s initialised: Registers at 0x%08lx length 0x%08lx\",\n+\t\tpriv->name, priv->regs_phys, priv->mem_window_len);\n+\n+\treturn 0;\n+\n+failed_legacy_device_create:\n+\tdevice_destroy(priv->class, priv->devid);\n+failed_device_create:\n+\tclass_destroy(priv->class);\n+failed_class_create:\n+\tcdev_del(&priv->rpivid_mem_cdev);\n+failed_cdev_add:\n+\tunregister_chrdev_region(priv->devid, 1);\n+failed_alloc_chrdev:\n+failed_get_resource:\n+\tkfree(priv);\n+failed_inst_alloc:\n+\tdev_err(&pdev->dev, \"could not load rpivid_mem\");\n+\treturn err;\n+}\n+\n+static int rpivid_mem_remove(struct platform_device *pdev)\n+{\n+\tstruct device *dev = &pdev->dev;\n+\tstruct rpivid_mem_priv *priv = platform_get_drvdata(pdev);\n+\n+\tdevice_destroy(priv->class, priv->devid + 1);\n+\tdevice_destroy(priv->class, priv->devid);\n+\tclass_destroy(priv->class);\n+\tcdev_del(&priv->rpivid_mem_cdev);\n+\tunregister_chrdev_region(priv->devid, 1);\n+\tkfree(priv);\n+\n+\tdev_info(dev, \"%s driver removed - OK\", priv->name);\n+\treturn 0;\n+}\n+\n+static const struct of_device_id rpivid_mem_of_match[] = {\n+\t{\n+\t\t.compatible = \"raspberrypi,rpivid-hevc-decoder\",\n+\t\t.data = \"rpivid-hevcmem\",\n+\t},\n+\t{\n+\t\t.compatible = \"raspberrypi,rpivid-h264-decoder\",\n+\t\t.data = \"rpivid-h264mem\",\n+\t},\n+\t{\n+\t\t.compatible = \"raspberrypi,rpivid-vp9-decoder\",\n+\t\t.data = \"rpivid-vp9mem\",\n+\t},\n+\t/* The \"intc\" is included as this block of hardware contains the\n+\t * \"frame done\" status flags.\n+\t */\n+\t{\n+\t\t.compatible = \"raspberrypi,rpivid-local-intc\",\n+\t\t.data = \"rpivid-intcmem\",\n+\t},\n+\t{ /* sentinel */ },\n+};\n+\n+MODULE_DEVICE_TABLE(of, rpivid_mem_of_match);\n+\n+static struct platform_driver rpivid_mem_driver = {\n+\t.probe = rpivid_mem_probe,\n+\t.remove = rpivid_mem_remove,\n+\t.driver = {\n+\t\t   .name = DRIVER_NAME,\n+\t\t   .owner = THIS_MODULE,\n+\t\t   .of_match_table = rpivid_mem_of_match,\n+\t\t   },\n+};\n+\n+module_platform_driver(rpivid_mem_driver);\n+\n+MODULE_ALIAS(\"platform:rpivid-mem\");\n+MODULE_LICENSE(\"GPL\");\n+MODULE_DESCRIPTION(\"Driver for accessing RPiVid decoder registers from userspace\");\n+MODULE_AUTHOR(\"Jonathan Bell <jonathan@raspberrypi.org>\");\n--- a/drivers/mfd/bcm2835-pm.c\n+++ b/drivers/mfd/bcm2835-pm.c\n@@ -50,14 +50,14 @@ static int bcm2835_pm_probe(struct platf\n \tif (ret)\n \t\treturn ret;\n \n-\t/* Map the ARGON ASB regs if present. */\n+\t/* Map the RPiVid ASB regs if present. */\n \tres = platform_get_resource(pdev, IORESOURCE_MEM, 2);\n \tif (res) {\n-\t\tpm->arg_asb = devm_ioremap_resource(dev, res);\n-\t\tif (IS_ERR(pm->arg_asb)) {\n-\t\t\tdev_err(dev, \"Failed to map ARGON ASB: %ld\\n\",\n-\t\t\t\tPTR_ERR(pm->arg_asb));\n-\t\t\treturn PTR_ERR(pm->arg_asb);\n+\t\tpm->rpivid_asb = devm_ioremap_resource(dev, res);\n+\t\tif (IS_ERR(pm->rpivid_asb)) {\n+\t\t\tdev_err(dev, \"Failed to map RPiVid ASB: %ld\\n\",\n+\t\t\t\tPTR_ERR(pm->rpivid_asb));\n+\t\t\treturn PTR_ERR(pm->rpivid_asb);\n \t\t}\n \t}\n \n--- a/drivers/soc/bcm/bcm2835-power.c\n+++ b/drivers/soc/bcm/bcm2835-power.c\n@@ -637,15 +637,15 @@ static int bcm2835_power_probe(struct pl\n \tpower->base = pm->base;\n \tpower->asb = pm->asb;\n \n-\t/* 2711 hack: the new ARGON ASB took over V3D, which is our\n+\t/* 2711 hack: the new RPiVid ASB took over V3D, which is our\n \t * only consumer of this driver so far.  The old ASB seems to\n \t * still be present with ISP and H264 bits but no V3D, but I\n \t * don't know if that's real or not.  The V3D is in the same\n \t * place in the new ASB as the old one, so just poke the new\n \t * one for now.\n \t */\n-\tif (pm->arg_asb) {\n-\t\tpower->asb = pm->arg_asb;\n+\tif (pm->rpivid_asb) {\n+\t\tpower->asb = pm->rpivid_asb;\n \t\tpower->is_2711 = true;\n \t}\n \n--- a/include/linux/mfd/bcm2835-pm.h\n+++ b/include/linux/mfd/bcm2835-pm.h\n@@ -9,7 +9,7 @@ struct bcm2835_pm {\n \tstruct device *dev;\n \tvoid __iomem *base;\n \tvoid __iomem *asb;\n-\tvoid __iomem *arg_asb;\n+\tvoid __iomem *rpivid_asb;\n };\n \n #endif /* BCM2835_MFD_PM_H */\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0151-hid-usb-Add-device-quirks-for-Freeway-Airmouse-T3-an.patch",
    "content": "From 25805001705a4b01edec63c6ec63482d16dce8d1 Mon Sep 17 00:00:00 2001\nFrom: Jonathan Bell <jonathan@raspberrypi.org>\nDate: Thu, 1 Aug 2019 16:41:20 +0100\nSubject: [PATCH] hid: usb: Add device quirks for Freeway Airmouse T3\n and MX3\n\nThese wireless mouse/keyboard combo remote control devices specify\nmultiple \"wheel\" events in their report descriptors. The wheel events\nare incorrectly defined and apparently map to accelerometer data, leading\nto spurious mouse scroll events being generated at an extreme rate when\nthe device is moved.\n\nAs a workaround, use HID_QUIRK_INCREMENT_USAGE_ON_DUPLICATE to mask\nfeeding the extra wheel events to the input subsystem.\n\nSee: https://github.com/raspberrypi/firmware/issues/1189\n\nSigned-off-by: Jonathan Bell <jonathan@raspberrypi.org>\n---\n drivers/hid/hid-ids.h    | 6 ++++++\n drivers/hid/hid-quirks.c | 2 ++\n 2 files changed, 8 insertions(+)\n\n--- a/drivers/hid/hid-ids.h\n+++ b/drivers/hid/hid-ids.h\n@@ -221,6 +221,9 @@\n #define USB_VENDOR_ID_BAANTO\t\t0x2453\n #define USB_DEVICE_ID_BAANTO_MT_190W2\t0x0100\n \n+#define USB_VENDOR_ID_BEKEN\t\t0x25a7\n+#define USB_DEVICE_ID_AIRMOUSE_T3\t0x2402\n+\n #define USB_VENDOR_ID_BELKIN\t\t0x050d\n #define USB_DEVICE_ID_FLIP_KVM\t\t0x3201\n \n@@ -1270,6 +1273,9 @@\n #define USB_VENDOR_ID_XAT\t0x2505\n #define USB_DEVICE_ID_XAT_CSR\t0x0220\n \n+#define USB_VENDOR_ID_XENTA\t\t\t0x1d57\n+#define USB_DEVICE_ID_AIRMOUSE_MX3\t\t0xad03\n+\n #define USB_VENDOR_ID_XIN_MO\t\t\t0x16c0\n #define USB_DEVICE_ID_XIN_MO_DUAL_ARCADE\t0x05e1\n #define USB_DEVICE_ID_THT_2P_ARCADE\t\t0x75e1\n--- a/drivers/hid/hid-quirks.c\n+++ b/drivers/hid/hid-quirks.c\n@@ -41,6 +41,7 @@ static const struct hid_device_id hid_qu\n \t{ HID_USB_DEVICE(USB_VENDOR_ID_ATEN, USB_DEVICE_ID_ATEN_CS682), HID_QUIRK_NOGET },\n \t{ HID_USB_DEVICE(USB_VENDOR_ID_ATEN, USB_DEVICE_ID_ATEN_CS692), HID_QUIRK_NOGET },\n \t{ HID_USB_DEVICE(USB_VENDOR_ID_ATEN, USB_DEVICE_ID_ATEN_UC100KM), HID_QUIRK_NOGET },\n+\t{ HID_USB_DEVICE(USB_VENDOR_ID_BEKEN, USB_DEVICE_ID_AIRMOUSE_T3), HID_QUIRK_INCREMENT_USAGE_ON_DUPLICATE },\n \t{ HID_USB_DEVICE(USB_VENDOR_ID_CHICONY, USB_DEVICE_ID_CHICONY_MULTI_TOUCH), HID_QUIRK_MULTI_INPUT },\n \t{ HID_USB_DEVICE(USB_VENDOR_ID_CHICONY, USB_DEVICE_ID_CHICONY_PIXART_USB_OPTICAL_MOUSE), HID_QUIRK_ALWAYS_POLL },\n \t{ HID_USB_DEVICE(USB_VENDOR_ID_CHICONY, USB_DEVICE_ID_CHICONY_PIXART_USB_OPTICAL_MOUSE2), HID_QUIRK_ALWAYS_POLL },\n@@ -195,6 +196,7 @@ static const struct hid_device_id hid_qu\n \t{ HID_USB_DEVICE(USB_VENDOR_ID_WISEGROUP, USB_DEVICE_ID_QUAD_USB_JOYPAD), HID_QUIRK_NOGET | HID_QUIRK_MULTI_INPUT },\n \t{ HID_USB_DEVICE(USB_VENDOR_ID_XIN_MO, USB_DEVICE_ID_XIN_MO_DUAL_ARCADE), HID_QUIRK_MULTI_INPUT },\n \t{ HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_GROUP_AUDIO), HID_QUIRK_NOGET },\n+\t{ HID_USB_DEVICE(USB_VENDOR_ID_XENTA, USB_DEVICE_ID_AIRMOUSE_MX3), HID_QUIRK_INCREMENT_USAGE_ON_DUPLICATE },\n \n \t{ 0 }\n };\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0152-Add-HDMI1-facility-to-the-driver.patch",
    "content": "From 3dbfcfbd3f9a0cae3bb426954ad5fd7d193507cc Mon Sep 17 00:00:00 2001\nFrom: James Hughes <james.hughes@raspberrypi.org>\nDate: Tue, 16 Jul 2019 12:18:21 +0100\nSubject: [PATCH] Add HDMI1 facility to the driver.\n\nFor generic ALSA, all you need is the bcm2835.h change, but\nhave also added structures for IEC958 HDMI. Not sure how to\ntest those.\n---\n .../vc04_services/bcm2835-audio/bcm2835.c     | 29 ++++++++++++++++---\n .../vc04_services/bcm2835-audio/bcm2835.h     |  4 ++-\n 2 files changed, 28 insertions(+), 5 deletions(-)\n\n--- a/drivers/staging/vc04_services/bcm2835-audio/bcm2835.c\n+++ b/drivers/staging/vc04_services/bcm2835-audio/bcm2835.c\n@@ -79,7 +79,11 @@ static int bcm2835_audio_alsa_newpcm(str\n \tif (err)\n \t\treturn err;\n \n-\terr = snd_bcm2835_new_pcm(chip, \"bcm2835 IEC958/HDMI\", 1, 0, 1, true);\n+\terr = snd_bcm2835_new_pcm(chip, \"bcm2835 IEC958/HDMI\", 1, AUDIO_DEST_HDMI0, 1, true);\n+\tif (err)\n+\t\treturn err;\n+\n+\terr = snd_bcm2835_new_pcm(chip, \"bcm2835 IEC958/HDMI1\", 2, AUDIO_DEST_HDMI1, 1, true);\n \tif (err)\n \t\treturn err;\n \n@@ -106,7 +110,7 @@ static struct bcm2835_audio_driver bcm28\n \t.newctl = snd_bcm2835_new_ctl,\n };\n \n-static struct bcm2835_audio_driver bcm2835_audio_hdmi = {\n+static struct bcm2835_audio_driver bcm2835_audio_hdmi0 = {\n \t.driver = {\n \t\t.name = \"bcm2835_hdmi\",\n \t\t.owner = THIS_MODULE,\n@@ -116,7 +120,20 @@ static struct bcm2835_audio_driver bcm28\n \t.minchannels = 1,\n \t.newpcm = bcm2835_audio_simple_newpcm,\n \t.newctl = snd_bcm2835_new_hdmi_ctl,\n-\t.route = AUDIO_DEST_HDMI\n+\t.route = AUDIO_DEST_HDMI0\n+};\n+\n+static struct bcm2835_audio_driver bcm2835_audio_hdmi1 = {\n+\t.driver = {\n+\t\t.name = \"bcm2835_hdmi\",\n+\t\t.owner = THIS_MODULE,\n+\t},\n+\t.shortname = \"bcm2835 HDMI 1\",\n+\t.longname  = \"bcm2835 HDMI 1\",\n+\t.minchannels = 1,\n+\t.newpcm = bcm2835_audio_simple_newpcm,\n+\t.newctl = snd_bcm2835_new_hdmi_ctl,\n+\t.route = AUDIO_DEST_HDMI1\n };\n \n static struct bcm2835_audio_driver bcm2835_audio_headphones = {\n@@ -143,7 +160,11 @@ static struct bcm2835_audio_drivers chil\n \t\t.is_enabled = &enable_compat_alsa,\n \t},\n \t{\n-\t\t.audio_driver = &bcm2835_audio_hdmi,\n+\t\t.audio_driver = &bcm2835_audio_hdmi0,\n+\t\t.is_enabled = &enable_hdmi,\n+\t},\n+\t{\n+\t\t.audio_driver = &bcm2835_audio_hdmi1,\n \t\t.is_enabled = &enable_hdmi,\n \t},\n \t{\n--- a/drivers/staging/vc04_services/bcm2835-audio/bcm2835.h\n+++ b/drivers/staging/vc04_services/bcm2835-audio/bcm2835.h\n@@ -33,7 +33,9 @@ enum {\n enum snd_bcm2835_route {\n \tAUDIO_DEST_AUTO = 0,\n \tAUDIO_DEST_HEADPHONES = 1,\n-\tAUDIO_DEST_HDMI = 2,\n+\tAUDIO_DEST_HDMI = 2,  // for backwards compatibility.\n+\tAUDIO_DEST_HDMI0 = 2,\n+\tAUDIO_DEST_HDMI1 = 3,\n \tAUDIO_DEST_MAX,\n };\n \n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0153-net-bcmgenet-Workaround-2-for-Pi4-Ethernet-fail.patch",
    "content": "From 5d5a886b8ae7d18e6aeb44acd37fc4bd23ca1952 Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.org>\nDate: Fri, 9 Aug 2019 08:51:43 +0100\nSubject: [PATCH] net: bcmgenet: Workaround #2 for Pi4 Ethernet fail\n\nSome combinations of Pi 4Bs and Ethernet switches don't reliably get a\nDCHP-assigned IP address, leaving the unit with a self=assigned 169.254\naddress. In the failure case, the Pi is left able to receive packets\nbut not send them, suggesting that the MAC<->PHY link is getting into\na bad state.\n\nIt has been found empirically that skipping a reset step by the genet\ndriver prevents the failures. No downsides have been discovered yet,\nand unlike the forced renegotiation it doesn't increase the time to\nget an IP address, so the workaround is enabled by default; add\n\n  genet.skip_umac_reset=n\n\nto the command line to disable it.\n\nSee: https://github.com/raspberrypi/linux/issues/3108\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.org>\n---\n drivers/net/ethernet/broadcom/genet/bcmgenet.c | 8 ++++++++\n 1 file changed, 8 insertions(+)\n\n--- a/drivers/net/ethernet/broadcom/genet/bcmgenet.c\n+++ b/drivers/net/ethernet/broadcom/genet/bcmgenet.c\n@@ -67,6 +67,9 @@\n \n /* Forward declarations */\n static void bcmgenet_set_rx_mode(struct net_device *dev);\n+static bool skip_umac_reset = true;\n+module_param(skip_umac_reset, bool, 0444);\n+MODULE_PARM_DESC(skip_umac_reset, \"Skip UMAC reset step\");\n \n static inline void bcmgenet_writel(u32 value, void __iomem *offset)\n {\n@@ -2428,6 +2431,11 @@ static void reset_umac(struct bcmgenet_p\n \tbcmgenet_rbuf_ctrl_set(priv, 0);\n \tudelay(10);\n \n+\tif (skip_umac_reset) {\n+\t\tpr_warn(\"Skipping UMAC reset\\n\");\n+\t\treturn;\n+\t}\n+\n \t/* issue soft reset and disable MAC while updating its registers */\n \tbcmgenet_umac_writel(priv, CMD_SW_RESET, UMAC_CMD);\n \tudelay(2);\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0154-xhci-Use-more-event-ring-segment-table-entries.patch",
    "content": "From 56212428792d53e5d2c741733d5f284331e84c97 Mon Sep 17 00:00:00 2001\nFrom: Jonathan Bell <jonathan@raspberrypi.org>\nDate: Tue, 13 Aug 2019 15:53:29 +0100\nSubject: [PATCH] xhci: Use more event ring segment table entries\n\nUsers have reported log spam created by \"Event Ring Full\" xHC event\nTRBs. These are caused by interrupt latency in conjunction with a very\nbusy set of devices on the bus. The errors are benign, but throughput\nwill suffer as the xHC will pause processing of transfers until the\nevent ring is drained by the kernel. Expand the number of event TRB slots\navailable by increasing the number of event ring segments in the ERST.\n\nControllers have a hardware-defined limit as to the number of ERST\nentries they can process, so make the actual number in use\nmin(ERST_MAX_SEGS, hw_max).\n\nSigned-off-by: Jonathan Bell <jonathan@raspberrypi.org>\n---\n drivers/usb/host/xhci-mem.c | 8 +++++---\n drivers/usb/host/xhci.h     | 4 ++--\n 2 files changed, 7 insertions(+), 5 deletions(-)\n\n--- a/drivers/usb/host/xhci-mem.c\n+++ b/drivers/usb/host/xhci-mem.c\n@@ -2525,9 +2525,11 @@ int xhci_mem_init(struct xhci_hcd *xhci,\n \t * Event ring setup: Allocate a normal ring, but also setup\n \t * the event ring segment table (ERST).  Section 4.9.3.\n \t */\n+\tval2 = 1 << HCS_ERST_MAX(xhci->hcs_params2);\n+\tval2 = min_t(unsigned int, ERST_MAX_SEGS, val2);\n \txhci_dbg_trace(xhci, trace_xhci_dbg_init, \"// Allocating event ring\");\n-\txhci->event_ring = xhci_ring_alloc(xhci, ERST_NUM_SEGS, 1, TYPE_EVENT,\n-\t\t\t\t\t0, flags);\n+\txhci->event_ring = xhci_ring_alloc(xhci, val2, 1, TYPE_EVENT,\n+\t\t\t\t\t   0, flags);\n \tif (!xhci->event_ring)\n \t\tgoto fail;\n \tif (xhci_check_trb_in_td_math(xhci) < 0)\n@@ -2540,7 +2542,7 @@ int xhci_mem_init(struct xhci_hcd *xhci,\n \t/* set ERST count with the number of entries in the segment table */\n \tval = readl(&xhci->ir_set->erst_size);\n \tval &= ERST_SIZE_MASK;\n-\tval |= ERST_NUM_SEGS;\n+\tval |= val2;\n \txhci_dbg_trace(xhci, trace_xhci_dbg_init,\n \t\t\t\"// Write ERST size = %i to ir_set 0 (some bits preserved)\",\n \t\t\tval);\n--- a/drivers/usb/host/xhci.h\n+++ b/drivers/usb/host/xhci.h\n@@ -1656,8 +1656,8 @@ struct urb_priv {\n  * Each segment table entry is 4*32bits long.  1K seems like an ok size:\n  * (1K bytes * 8bytes/bit) / (4*32 bits) = 64 segment entries in the table,\n  * meaning 64 ring segments.\n- * Initial allocated size of the ERST, in number of entries */\n-#define\tERST_NUM_SEGS\t1\n+ * Maximum number of segments in the ERST */\n+#define\tERST_MAX_SEGS\t8\n /* Initial allocated size of the ERST, in number of entries */\n #define\tERST_SIZE\t64\n /* Initial number of event segment rings allocated */\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0155-configs-arm64-bcm2711-Enable-V3D.patch",
    "content": "From d724240a2db99f47c3eb8330960b14a2719ed7cd Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.org>\nDate: Thu, 15 Aug 2019 12:02:34 +0100\nSubject: [PATCH] configs: arm64/bcm2711: Enable V3D\n\nEnable the V3D driver, which depends on BCM2835_POWER.\n\nOriginally submitted by GitHub user 'phire' in a slightly different\nform.\n\nSee: https://github.com/raspberrypi/linux/pull/3063\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.org>\n---\n drivers/gpu/drm/v3d/Kconfig | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/drivers/gpu/drm/v3d/Kconfig\n+++ b/drivers/gpu/drm/v3d/Kconfig\n@@ -1,7 +1,7 @@\n # SPDX-License-Identifier: GPL-2.0-only\n config DRM_V3D\n \ttristate \"Broadcom V3D 3.x and newer\"\n-\tdepends on ARCH_BCM || ARCH_BCMSTB || COMPILE_TEST\n+\tdepends on ARCH_BCM || ARCH_BCMSTB || ARCH_BCM2835 || COMPILE_TEST\n \tdepends on DRM\n \tdepends on COMMON_CLK\n \tdepends on MMU\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0156-arch-arm-Add-model-string-to-cpuinfo.patch",
    "content": "From 5f7b32d4608113927128391620cd80048db52a2e Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.org>\nDate: Tue, 3 Sep 2019 18:16:56 +0100\nSubject: [PATCH] arch/arm: Add model string to cpuinfo\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.org>\n---\n arch/arm/kernel/setup.c | 10 ++++++++++\n 1 file changed, 10 insertions(+)\n\n--- a/arch/arm/kernel/setup.c\n+++ b/arch/arm/kernel/setup.c\n@@ -1255,6 +1255,8 @@ static int c_show(struct seq_file *m, vo\n {\n \tint i, j;\n \tu32 cpuid;\n+\tstruct device_node *np;\n+\tconst char *model;\n \n \tfor_each_online_cpu(i) {\n \t\t/*\n@@ -1314,6 +1316,14 @@ static int c_show(struct seq_file *m, vo\n \tseq_printf(m, \"Revision\\t: %04x\\n\", system_rev);\n \tseq_printf(m, \"Serial\\t\\t: %s\\n\", system_serial);\n \n+\tnp = of_find_node_by_path(\"/\");\n+\tif (np) {\n+\t\tif (!of_property_read_string(np, \"model\",\n+\t\t\t\t\t     &model))\n+\t\t\tseq_printf(m, \"Model\\t\\t: %s\\n\", model);\n+\t\tof_node_put(np);\n+\t}\n+\n \treturn 0;\n }\n \n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0157-arch-arm64-Add-Revision-Serial-Model-to-cpuinfo.patch",
    "content": "From 24f0d858fbabe69c32829edc0e2765b1fa5cc8ec Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.org>\nDate: Tue, 3 Sep 2019 18:17:25 +0100\nSubject: [PATCH] arch/arm64: Add Revision, Serial, Model to cpuinfo\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.org>\n---\n arch/arm64/kernel/cpuinfo.c | 25 +++++++++++++++++++++++++\n 1 file changed, 25 insertions(+)\n\n--- a/arch/arm64/kernel/cpuinfo.c\n+++ b/arch/arm64/kernel/cpuinfo.c\n@@ -17,6 +17,7 @@\n #include <linux/elf.h>\n #include <linux/init.h>\n #include <linux/kernel.h>\n+#include <linux/of_platform.h>\n #include <linux/personality.h>\n #include <linux/preempt.h>\n #include <linux/printk.h>\n@@ -140,6 +141,10 @@ static int c_show(struct seq_file *m, vo\n {\n \tint i, j;\n \tbool compat = personality(current->personality) == PER_LINUX32;\n+\tstruct device_node *np;\n+\tconst char *model;\n+\tconst char *serial;\n+\tu32 revision;\n \n \tfor_each_online_cpu(i) {\n \t\tstruct cpuinfo_arm64 *cpuinfo = &per_cpu(cpu_data, i);\n@@ -200,6 +205,26 @@ static int c_show(struct seq_file *m, vo\n \t\tseq_printf(m, \"CPU revision\\t: %d\\n\\n\", MIDR_REVISION(midr));\n \t}\n \n+\tseq_printf(m, \"Hardware\\t: BCM2835\\n\");\n+\n+\tnp = of_find_node_by_path(\"/system\");\n+\tif (np) {\n+\t\tif (!of_property_read_u32(np, \"linux,revision\", &revision))\n+\t\t\tseq_printf(m, \"Revision\\t: %04x\\n\", revision);\n+\t\tof_node_put(np);\n+\t}\n+\n+\tnp = of_find_node_by_path(\"/\");\n+\tif (np) {\n+\t\tif (!of_property_read_string(np, \"serial-number\",\n+\t\t\t\t\t     &serial))\n+\t\t\tseq_printf(m, \"Serial\\t\\t: %s\\n\", serial);\n+\t\tif (!of_property_read_string(np, \"model\",\n+\t\t\t\t\t     &model))\n+\t\t\tseq_printf(m, \"Model\\t\\t: %s\\n\", model);\n+\t\tof_node_put(np);\n+\t}\n+\n \treturn 0;\n }\n \n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0158-media-dt-bindings-Add-binding-for-the-Sony-IMX219-se.patch",
    "content": "From 4e4be52826939d4baa054e0c859fffd5c9ee7cd6 Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.org>\nDate: Wed, 28 Aug 2019 13:34:30 +0100\nSubject: [PATCH] media: dt-bindings: Add binding for the Sony IMX219\n sensor\n\nThe IMX219 is an 8MPix CSI2 sensor, supporting 2 or 4 data lanes.\nDocument the binding for this device.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>\n---\n .../devicetree/bindings/media/i2c/imx219.txt  | 59 +++++++++++++++++++\n 1 file changed, 59 insertions(+)\n create mode 100644 Documentation/devicetree/bindings/media/i2c/imx219.txt\n\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/media/i2c/imx219.txt\n@@ -0,0 +1,59 @@\n+* Sony 1/4.0-Inch 8Mpixel CMOS Digital Image Sensor\n+\n+The Sony imx219 is a 1/4.0-inch CMOS active pixel digital image sensor with\n+an active array size of 3280H x 2464V. It is programmable through I2C\n+interface. The I2C address is fixed to 0x10 as per sensor data sheet.\n+Image data is sent through MIPI CSI-2, which is configured as either 2 or 4\n+data lanes.\n+\n+Required Properties:\n+- compatible: value should be \"sony,imx219\" for imx219 sensor\n+- reg: I2C bus address of the device\n+- clocks: reference to the xclk input clock.\n+- clock-names: should be \"xclk\".\n+- DOVDD-supply: Digital I/O voltage supply, 1.8 volts\n+- AVDD-supply: Analog voltage supply, 2.8 volts\n+- DVDD-supply: Digital core voltage supply, 1.2 volts\n+\n+Optional Properties:\n+- xclr-gpios: reference to the GPIO connected to the xclr pin, if any. Must be\n+\t      released after all supplies are applied.\n+\t      This is an active high signal to the imx219.\n+\n+The imx219 device node should contain one 'port' child node with\n+an 'endpoint' subnode. For further reading on port node refer to\n+Documentation/devicetree/bindings/media/video-interfaces.txt.\n+\n+Endpoint node required properties for CSI-2 connection are:\n+- remote-endpoint: a phandle to the bus receiver's endpoint node.\n+- clock-lanes: should be set to <0> (clock lane on hardware lane 0)\n+- data-lanes: should be set to <1 2>, or  <1 2 3 4> (two or four lane CSI-2\n+  supported)\n+\n+Example:\n+\tsensor@10 {\n+\t\tcompatible = \"sony,imx219\";\n+\t\treg = <0x10>;\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\tclocks = <&imx219_clk>;\n+\t\tclock-names = \"xclk\";\n+\t\txclr-gpios = <&gpio_sensor 0 0>;\n+\t\tDOVDD-supply = <&vgen4_reg>; /* 1.8v */\n+\t\tAVDD-supply = <&vgen3_reg>;  /* 2.8v */\n+\t\tDVDD-supply = <&vgen2_reg>;  /* 1.2v */\n+\n+\t\timx219_clk: camera-clk {\n+\t\t\tcompatible = \"fixed-clock\";\n+\t\t\t#clock-cells = <0>;\n+\t\t\tclock-frequency = <24000000>;\n+\t\t};\n+\n+\t\tport {\n+\t\t\tsensor_out: endpoint {\n+\t\t\t\tremote-endpoint = <&csiss_in>;\n+\t\t\t\tclock-lanes = <0>;\n+\t\t\t\tdata-lanes = <1 2>;\n+\t\t\t};\n+\t\t};\n+\t};\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0159-v4l2-Add-a-Greyworld-AWB-mode.patch",
    "content": "From 1c6c1ab42e61cdca555c85bdde5677b13b5cd5f3 Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.org>\nDate: Fri, 6 Sep 2019 15:04:51 +0100\nSubject: [PATCH] v4l2: Add a Greyworld AWB mode.\n\nAdds a simple greyworld white balance preset, mainly for use\nwith cameras without an IR filter (eg Raspberry Pi NoIR)\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>\n---\n drivers/media/v4l2-core/v4l2-ctrls.c | 1 +\n include/uapi/linux/v4l2-controls.h   | 1 +\n 2 files changed, 2 insertions(+)\n\n--- a/drivers/media/v4l2-core/v4l2-ctrls.c\n+++ b/drivers/media/v4l2-core/v4l2-ctrls.c\n@@ -275,6 +275,7 @@ const char * const *v4l2_ctrl_get_menu(u\n \t\t\"Flash\",\n \t\t\"Cloudy\",\n \t\t\"Shade\",\n+\t\t\"Greyworld\",\n \t\tNULL,\n \t};\n \tstatic const char * const camera_iso_sensitivity_auto[] = {\n--- a/include/uapi/linux/v4l2-controls.h\n+++ b/include/uapi/linux/v4l2-controls.h\n@@ -886,6 +886,7 @@ enum v4l2_auto_n_preset_white_balance {\n \tV4L2_WHITE_BALANCE_FLASH\t\t= 7,\n \tV4L2_WHITE_BALANCE_CLOUDY\t\t= 8,\n \tV4L2_WHITE_BALANCE_SHADE\t\t= 9,\n+\tV4L2_WHITE_BALANCE_GREYWORLD\t\t= 10,\n };\n \n #define V4L2_CID_WIDE_DYNAMIC_RANGE\t\t(V4L2_CID_CAMERA_CLASS_BASE+21)\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0160-staging-bcm2835-camera-Add-greyworld-AWB-mode.patch",
    "content": "From 827f9e8f76bd2674835026e37aba31b3c3a784e4 Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.org>\nDate: Fri, 6 Sep 2019 15:13:06 +0100\nSubject: [PATCH] staging: bcm2835-camera: Add greyworld AWB mode\n\nThis is mainly used for the NoIR camera which has no IR\nfilter and can completely confuse normal AWB presets.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>\n---\n drivers/staging/vc04_services/bcm2835-camera/controls.c    | 4 ++++\n drivers/staging/vc04_services/vchiq-mmal/mmal-parameters.h | 1 +\n 2 files changed, 5 insertions(+)\n\n--- a/drivers/staging/vc04_services/bcm2835-camera/controls.c\n+++ b/drivers/staging/vc04_services/bcm2835-camera/controls.c\n@@ -474,6 +474,10 @@ static int ctrl_set_awb_mode(struct bm28\n \tcase V4L2_WHITE_BALANCE_SHADE:\n \t\tu32_value = MMAL_PARAM_AWBMODE_SHADE;\n \t\tbreak;\n+\n+\tcase V4L2_WHITE_BALANCE_GREYWORLD:\n+\t\tu32_value = MMAL_PARAM_AWBMODE_GREYWORLD;\n+\t\tbreak;\n \t}\n \n \treturn vchiq_mmal_port_parameter_set(dev->instance, control,\n--- a/drivers/staging/vc04_services/vchiq-mmal/mmal-parameters.h\n+++ b/drivers/staging/vc04_services/vchiq-mmal/mmal-parameters.h\n@@ -313,6 +313,7 @@ enum mmal_parameter_awbmode {\n \tMMAL_PARAM_AWBMODE_INCANDESCENT,\n \tMMAL_PARAM_AWBMODE_FLASH,\n \tMMAL_PARAM_AWBMODE_HORIZON,\n+\tMMAL_PARAM_AWBMODE_GREYWORLD,\n };\n \n enum mmal_parameter_imagefx {\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0161-drm-v3d-Delete-pm_runtime-support.patch",
    "content": "From 194db68e9c6c18c536714859e788de36a146dabb Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.org>\nDate: Wed, 18 Sep 2019 17:22:36 +0100\nSubject: [PATCH] drm/v3d: Delete pm_runtime support\n\nThe pm_runtime was blocking changelist submission, so delete it as a\ntemporary workaround.\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.org>\n---\n drivers/gpu/drm/v3d/v3d_gem.c |  5 -----\n drivers/gpu/drm/v3d/v3d_mmu.c | 11 -----------\n 2 files changed, 16 deletions(-)\n\n--- a/drivers/gpu/drm/v3d/v3d_gem.c\n+++ b/drivers/gpu/drm/v3d/v3d_gem.c\n@@ -478,10 +478,6 @@ v3d_job_init(struct v3d_dev *v3d, struct\n \tjob->v3d = v3d;\n \tjob->free = free;\n \n-\tret = pm_runtime_get_sync(v3d->drm.dev);\n-\tif (ret < 0)\n-\t\treturn ret;\n-\n \txa_init_flags(&job->deps, XA_FLAGS_ALLOC);\n \n \tret = drm_syncobj_find_fence(file_priv, in_sync, 0, 0, &in_fence);\n@@ -498,7 +494,6 @@ v3d_job_init(struct v3d_dev *v3d, struct\n \treturn 0;\n fail:\n \txa_destroy(&job->deps);\n-\tpm_runtime_put_autosuspend(v3d->drm.dev);\n \treturn ret;\n }\n \n--- a/drivers/gpu/drm/v3d/v3d_mmu.c\n+++ b/drivers/gpu/drm/v3d/v3d_mmu.c\n@@ -36,14 +36,6 @@ static int v3d_mmu_flush_all(struct v3d_\n {\n \tint ret;\n \n-\t/* Keep power on the device on until we're done with this\n-\t * call, but skip the flush if the device is off and will be\n-\t * reset when powered back on.\n-\t */\n-\tret = pm_runtime_get_if_in_use(v3d->dev);\n-\tif (ret == 0)\n-\t\treturn 0;\n-\n \t/* Make sure that another flush isn't already running when we\n \t * start this one.\n \t */\n@@ -71,9 +63,6 @@ static int v3d_mmu_flush_all(struct v3d_\n \tif (ret)\n \t\tdev_err(v3d->drm.dev, \"MMUC flush wait idle failed\\n\");\n \n-\tpm_runtime_mark_last_busy(v3d->dev);\n-\tpm_runtime_put_autosuspend(v3d->dev);\n-\n \treturn ret;\n }\n \n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0162-kbuild-Allow-.dtbo-overlays-to-be-built-piecemeal.patch",
    "content": "From 39e3ab3e857a617b982dbeee2037f13edc46f799 Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.org>\nDate: Mon, 23 Sep 2019 09:26:41 +0100\nSubject: [PATCH] kbuild: Allow .dtbo overlays to be built piecemeal\n\nBefore 4.20, it was possible to build an arbitrary overlay by copying\nit to arm/boot/dts/overlays/mytest-overlay.dts and running:\n\n    make ARCH=arm overlays/mytest.dtbo\n\nIn 4.20 the .dtb build rules were centralised, requiring the dowstream\n.dtbo build rules to be changed. They were, enough to support \"make ...\ndtbs\", but not sufficiently to allow this ad-hoc, one-off building of\nindividual files.\n\nAdd the missing makefile rule to support this way of building.\n\nSee: https://github.com/raspberrypi/linux/issues/3250\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.org>\n---\n Makefile | 3 +++\n 1 file changed, 3 insertions(+)\n\n--- a/Makefile\n+++ b/Makefile\n@@ -1354,6 +1354,9 @@ ifneq ($(dtstree),)\n %.dtb: include/config/kernel.release scripts_dtc\n \t$(Q)$(MAKE) $(build)=$(dtstree) $(dtstree)/$@\n \n+%.dtbo: prepare3 scripts_dtc\n+\t$(Q)$(MAKE) $(build)=$(dtstree) $(dtstree)/$@\n+\n PHONY += dtbs dtbs_install dtbs_check\n dtbs: include/config/kernel.release scripts_dtc\n \t$(Q)$(MAKE) $(build)=$(dtstree)\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0163-ARM-bcm-Switch-board-clk-and-pinctrl-to-bcm2711-comp.patch",
    "content": "From 676c69523fd366c0dfac97d2c343f565b563f62d Mon Sep 17 00:00:00 2001\nFrom: Stefan Wahren <wahrenst@gmx.net>\nDate: Thu, 19 Sep 2019 20:45:30 +0200\nSubject: [PATCH] ARM: bcm: Switch board, clk and pinctrl to bcm2711\n compatible\n\nAfter the decision to use bcm2711 compatible for upstream, we should\nswitch all accepted compatibles to bcm2711. So we can boot with\none DTB the down- and the upstream kernel.\n\nSigned-off-by: Stefan Wahren <wahrenst@gmx.net>\n---\n arch/arm/mach-bcm/board_bcm2835.c | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/arch/arm/mach-bcm/board_bcm2835.c\n+++ b/arch/arm/mach-bcm/board_bcm2835.c\n@@ -109,7 +109,7 @@ static const char * const bcm2835_compat\n #ifdef CONFIG_ARCH_MULTI_V7\n \t\"brcm,bcm2836\",\n \t\"brcm,bcm2837\",\n-\t\"brcm,bcm2838\",\n+\t\"brcm,bcm2711\",\n #endif\n \tNULL\n };\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0164-Rename-HDMI-ALSA-device-names-check-for-enable-state.patch",
    "content": "From 8f1af3614dd55e3c725b7f28f68ee6404e5f2e1a Mon Sep 17 00:00:00 2001\nFrom: James Hughes <james.hughes@raspberrypi.org>\nDate: Tue, 24 Sep 2019 18:26:55 +0100\nSubject: [PATCH] Rename HDMI ALSA device names, check for enable state\n\nHDMI Alsa devices renamed to match names used by DRM, to\nHDMI 1 and HDMI 2\n\nCheck for which HDMI devices are connected and only create\ndevices for those that are present.\n\nThe rename of the devices might cause some backwards compatibility\nissues, but since this particular part of the driver needs to be\nspecifically enabled, I suspect the number of people who will see\nthe problem will be very small.\n\nSigned-off-by: James Hughes <james.hughes@raspberrypi.org>\n---\n .../vc04_services/bcm2835-audio/bcm2835.c     | 70 +++++++++++++++++--\n 1 file changed, 63 insertions(+), 7 deletions(-)\n\n--- a/drivers/staging/vc04_services/bcm2835-audio/bcm2835.c\n+++ b/drivers/staging/vc04_services/bcm2835-audio/bcm2835.c\n@@ -9,8 +9,9 @@\n #include <linux/of.h>\n \n #include \"bcm2835.h\"\n+#include <soc/bcm2835/raspberrypi-firmware.h>\n \n-static bool enable_hdmi;\n+static bool enable_hdmi, enable_hdmi0, enable_hdmi1;\n static bool enable_headphones;\n static bool enable_compat_alsa = true;\n \n@@ -115,8 +116,8 @@ static struct bcm2835_audio_driver bcm28\n \t\t.name = \"bcm2835_hdmi\",\n \t\t.owner = THIS_MODULE,\n \t},\n-\t.shortname = \"bcm2835 HDMI\",\n-\t.longname  = \"bcm2835 HDMI\",\n+\t.shortname = \"bcm2835 HDMI 1\",\n+\t.longname  = \"bcm2835 HDMI 1\",\n \t.minchannels = 1,\n \t.newpcm = bcm2835_audio_simple_newpcm,\n \t.newctl = snd_bcm2835_new_hdmi_ctl,\n@@ -128,8 +129,8 @@ static struct bcm2835_audio_driver bcm28\n \t\t.name = \"bcm2835_hdmi\",\n \t\t.owner = THIS_MODULE,\n \t},\n-\t.shortname = \"bcm2835 HDMI 1\",\n-\t.longname  = \"bcm2835 HDMI 1\",\n+\t.shortname = \"bcm2835 HDMI 2\",\n+\t.longname  = \"bcm2835 HDMI 2\",\n \t.minchannels = 1,\n \t.newpcm = bcm2835_audio_simple_newpcm,\n \t.newctl = snd_bcm2835_new_hdmi_ctl,\n@@ -161,11 +162,11 @@ static struct bcm2835_audio_drivers chil\n \t},\n \t{\n \t\t.audio_driver = &bcm2835_audio_hdmi0,\n-\t\t.is_enabled = &enable_hdmi,\n+\t\t.is_enabled = &enable_hdmi0,\n \t},\n \t{\n \t\t.audio_driver = &bcm2835_audio_hdmi1,\n-\t\t.is_enabled = &enable_hdmi,\n+\t\t.is_enabled = &enable_hdmi1,\n \t},\n \t{\n \t\t.audio_driver = &bcm2835_audio_headphones,\n@@ -312,6 +313,53 @@ static int snd_add_child_devices(struct\n \treturn 0;\n }\n \n+static void set_hdmi_enables(struct device *dev)\n+{\n+\tstruct device_node *firmware_node;\n+\tstruct rpi_firmware *firmware;\n+\tu32 num_displays, i, display_id;\n+\tint ret;\n+\n+\tfirmware_node = of_parse_phandle(dev->of_node, \"brcm,firmware\", 0);\n+\tfirmware = rpi_firmware_get(firmware_node);\n+\n+\tif (!firmware)\n+\t\treturn;\n+\n+\tof_node_put(firmware_node);\n+\n+\tret = rpi_firmware_property(firmware,\n+\t\t\t\t    RPI_FIRMWARE_FRAMEBUFFER_GET_NUM_DISPLAYS,\n+\t\t\t\t    &num_displays, sizeof(u32));\n+\n+\tif (ret)\n+\t\treturn;\n+\n+\tfor (i = 0; i < num_displays; i++) {\n+\t\tdisplay_id = i;\n+\t\tret = rpi_firmware_property(firmware,\n+\t\t\t\tRPI_FIRMWARE_FRAMEBUFFER_GET_DISPLAY_ID,\n+\t\t\t\t&display_id, sizeof(display_id));\n+\t\tif (!ret) {\n+\t\t\tif (display_id == 2)\n+\t\t\t\tenable_hdmi0 = true;\n+\t\t\tif (display_id == 7)\n+\t\t\t\tenable_hdmi1 = true;\n+\t\t}\n+\t}\n+\n+\tif (!enable_hdmi0 && enable_hdmi1) {\n+\t\t/* Swap them over and reassign route. This means\n+\t\t * that if we only have one connected, it is always named\n+\t\t *  HDMI1, irrespective of if its on port HDMI0 or HDMI1.\n+\t\t *  This should match with the naming of HDMI ports in DRM\n+\t\t */\n+\t\tenable_hdmi0 = true;\n+\t\tenable_hdmi1 = false;\n+\t\tbcm2835_audio_hdmi0.route = AUDIO_DEST_HDMI1;\n+\t}\n+}\n+\n static int snd_bcm2835_alsa_probe(struct platform_device *pdev)\n {\n \tstruct device *dev = &pdev->dev;\n@@ -332,6 +380,14 @@ static int snd_bcm2835_alsa_probe(struct\n \t\t\t numchans);\n \t}\n \n+\tif (!enable_compat_alsa) {\n+\t\tset_hdmi_enables(dev);\n+\t\t// In this mode, always enable analog output\n+\t\tenable_headphones = true;\n+\t} else {\n+\t\tenable_hdmi0 = enable_hdmi;\n+\t}\n+\n \terr = bcm2835_devm_add_vchi_ctx(dev);\n \tif (err)\n \t\treturn err;\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0165-dt-bindings-Add-binding-for-the-Infineon-IRS1125-sen.patch",
    "content": "From effbf244f11642594a739755285cd16591831b13 Mon Sep 17 00:00:00 2001\nFrom: Markus Proeller <markus.proeller@pieye.org>\nDate: Thu, 10 Oct 2019 19:12:08 +0200\nSubject: [PATCH] dt-bindings: Add binding for the Infineon IRS1125\n sensor\n\nAdds a binding for the Infineon IRS1125 time-of-flight depth\nsensor.\n\nSigned-off-by: Markus Proeller <markus.proeller@pieye.org>\n---\n .../devicetree/bindings/media/i2c/irs1125.txt | 48 +++++++++++++++++++\n 1 file changed, 48 insertions(+)\n create mode 100644 Documentation/devicetree/bindings/media/i2c/irs1125.txt\n\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/media/i2c/irs1125.txt\n@@ -0,0 +1,48 @@\n+* Infineon irs1125 time of flight sensor\n+\n+The Infineon irs1125 is a time of flight digital image sensor with\n+an active array size of 352H x 286V. It is programmable through I2C\n+interface. The I2C address defaults to 0x3D, but can be reconfigured\n+to address 0x3C or 0x41 via I2C commands. Image data is sent through\n+MIPI CSI-2, which is configured as either 1 or 2 data lanes.\n+\n+Required Properties:\n+- compatible: value should be \"infineon,irs1125\" for irs1125 sensor\n+- reg: I2C bus address of the device\n+- clocks: reference to the xclk input clock.\n+- pwdn-gpios: reference to the GPIO connected to the reset pin.\n+\t      This is an active low signal to the iirs1125.\n+\n+The irs1125 device node should contain one 'port' child node with\n+an 'endpoint' subnode. For further reading on port node refer to\n+Documentation/devicetree/bindings/media/video-interfaces.txt.\n+\n+Endpoint node required properties for CSI-2 connection are:\n+- remote-endpoint: a phandle to the bus receiver's endpoint node.\n+- clock-lanes: should be set to <0> (clock lane on hardware lane 0)\n+- data-lanes: should be set to <1> or <1 2> (one or two lane CSI-2\n+  supported)\n+\n+Example:\n+\tsensor@10 {\n+\t\tcompatible = \"infineon,irs1125\";\n+\t\treg = <0x3D>;\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\tclocks = <&irs1125_clk>;\n+\t\tpwdn-gpios = <&gpio 5 0>;\n+\n+\t\tirs1125_clk: camera-clk {\n+\t\t\tcompatible = \"fixed-clock\";\n+\t\t\t#clock-cells = <0>;\n+\t\t\tclock-frequency = <26000000>;\n+\t\t};\n+\n+\t\tport {\n+\t\t\tsensor_out: endpoint {\n+\t\t\t\tremote-endpoint = <&csiss_in>;\n+\t\t\t\tclock-lanes = <0>;\n+\t\t\t\tdata-lanes = <1 2>;\n+\t\t\t};\n+\t\t};\n+\t};\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0166-media-i2c-Add-a-driver-for-the-Infineon-IRS1125-dept.patch",
    "content": "From 21da9db2602925f6584936c167c8ce9b81ab2e0a Mon Sep 17 00:00:00 2001\nFrom: Markus Proeller <markus.proeller@pieye.org>\nDate: Thu, 10 Oct 2019 19:12:36 +0200\nSubject: [PATCH] media: i2c: Add a driver for the Infineon IRS1125\n depth sensor\n\nThe Infineon IRS1125 is a time of flight depth sensor that\nhas a CSI-2 interface.\n\nAdd a V4L2 subdevice driver for this device.\n\nSigned-off-by: Markus Proeller <markus.proeller@pieye.org>\n---\n drivers/media/i2c/Kconfig   |   12 +\n drivers/media/i2c/Makefile  |    1 +\n drivers/media/i2c/irs1125.c | 1112 +++++++++++++++++++++++++++++++++++\n drivers/media/i2c/irs1125.h |   61 ++\n 4 files changed, 1186 insertions(+)\n create mode 100644 drivers/media/i2c/irs1125.c\n create mode 100644 drivers/media/i2c/irs1125.h\n\n--- a/drivers/media/i2c/Kconfig\n+++ b/drivers/media/i2c/Kconfig\n@@ -1060,6 +1060,18 @@ config VIDEO_OV13858\n \t  This is a Video4Linux2 sensor driver for the OmniVision\n \t  OV13858 camera.\n \n+config VIDEO_IRS1125\n+\ttristate \"Infineon IRS1125 sensor support\"\n+\tdepends on I2C && VIDEO_V4L2 && VIDEO_V4L2_SUBDEV_API\n+\tdepends on MEDIA_CAMERA_SUPPORT\n+\tselect V4L2_FWNODE\n+\thelp\n+\t  This is a Video4Linux2 sensor-level driver for the Infineon\n+\t  IRS1125 camera.\n+\n+\t  To compile this driver as a module, choose M here: the\n+\t  module will be called irs1125.\n+\n config VIDEO_VS6624\n \ttristate \"ST VS6624 sensor support\"\n \tdepends on VIDEO_V4L2 && I2C\n--- a/drivers/media/i2c/Makefile\n+++ b/drivers/media/i2c/Makefile\n@@ -84,6 +84,7 @@ obj-$(CONFIG_VIDEO_OV8856) += ov8856.o\n obj-$(CONFIG_VIDEO_OV9640) += ov9640.o\n obj-$(CONFIG_VIDEO_OV9650) += ov9650.o\n obj-$(CONFIG_VIDEO_OV13858) += ov13858.o\n+obj-$(CONFIG_VIDEO_IRS1125) += irs1125.o\n obj-$(CONFIG_VIDEO_MT9M001) += mt9m001.o\n obj-$(CONFIG_VIDEO_MT9M032) += mt9m032.o\n obj-$(CONFIG_VIDEO_MT9M111) += mt9m111.o\n--- /dev/null\n+++ b/drivers/media/i2c/irs1125.c\n@@ -0,0 +1,1112 @@\n+// SPDX-License-Identifier: GPL-2.0\n+/*\n+ * A V4L2 driver for Infineon IRS1125 TOF cameras.\n+ * Copyright (C) 2018, pieye GmbH\n+ *\n+ * Based on V4L2 OmniVision OV5647 Image Sensor driver\n+ * Copyright (C) 2016 Ramiro Oliveira <roliveir@synopsys.com>\n+ *\n+ * DT / fwnode changes, and GPIO control taken from ov5640.c\n+ * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. All Rights Reserved.\n+ * Copyright (C) 2014-2017 Mentor Graphics Inc.\n+ *\n+ */\n+\n+#include \"irs1125.h\"\n+#include <linux/clk.h>\n+#include <linux/delay.h>\n+#include <linux/gpio/consumer.h>\n+#include <linux/i2c.h>\n+#include <linux/init.h>\n+#include <linux/io.h>\n+#include <linux/module.h>\n+#include <linux/of_graph.h>\n+#include <linux/slab.h>\n+#include <linux/videodev2.h>\n+#include <linux/firmware.h>\n+#include <media/v4l2-device.h>\n+#include <media/v4l2-fwnode.h>\n+#include <media/v4l2-image-sizes.h>\n+#include <media/v4l2-mediabus.h>\n+#include <media/v4l2-ctrls.h>\n+\n+#define CHECK_BIT(val, pos) ((val) & BIT(pos))\n+\n+#define SENSOR_NAME \"irs1125\"\n+\n+#define RESET_ACTIVE_DELAY_MS\t 20\n+\n+#define IRS1125_ALTERNATE_FW \"irs1125_af.bin\"\n+\n+#define IRS1125_REG_CSICFG       0xA882\n+#define IRS1125_REG_DESIGN_STEP\t 0xB0AD\n+#define IRS1125_REG_EFUSEVAL2\t 0xB09F\n+#define IRS1125_REG_EFUSEVAL3\t 0xB0A0\n+#define IRS1125_REG_EFUSEVAL4\t 0xB0A1\n+#define IRS1125_REG_DMEM_SHADOW\t 0xC320\n+\n+#define IRS1125_DESIGN_STEP_EXPECTED 0x0a12\n+\n+#define IRS1125_ROW_START_DEF\t\t0\n+#define IRS1125_COLUMN_START_DEF\t0\n+#define IRS1125_WINDOW_HEIGHT_DEF\t 288\n+#define IRS1125_WINDOW_WIDTH_DEF\t352\n+\n+struct regval_list {\n+\tu16 addr;\n+\tu16 data;\n+};\n+\n+struct irs1125 {\n+\tstruct v4l2_subdev sd;\n+\tstruct media_pad pad;\n+\t/* the parsed DT endpoint info */\n+\tstruct v4l2_fwnode_endpoint ep;\n+\n+\tstruct clk *xclk;\n+\tstruct v4l2_ctrl_handler ctrl_handler;\n+\n+\t/* To serialize asynchronus callbacks */\n+\tstruct mutex lock;\n+\n+\t/* image data layout */\n+\tunsigned int num_seq;\n+\n+\t/* reset pin */\n+\tstruct gpio_desc *reset;\n+\n+\t/* V4l2 Controls to grab */\n+\tstruct v4l2_ctrl *ctrl_modplls;\n+\tstruct v4l2_ctrl *ctrl_numseq;\n+\n+\tint power_count;\n+};\n+\n+static inline struct irs1125 *to_state(struct v4l2_subdev *sd)\n+{\n+\treturn container_of(sd, struct irs1125, sd);\n+}\n+\n+static struct regval_list irs1125_26MHz[] = {\n+\t{0xB017, 0x0413},\n+\t{0xB086, 0x3535},\n+\t{0xB0AE, 0xEF02},\n+\t{0xA000, 0x0004},\n+\t{0xFFFF, 100},\n+\n+\t{0xB062, 0x6383},\n+\t{0xB063, 0x55A8},\n+\t{0xB068, 0x7628},\n+\t{0xB069, 0x03E2},\n+\n+\t{0xFFFF, 100},\n+\t{0xB05A, 0x01C5},\n+\t{0xB05C, 0x0206},\n+\t{0xB05D, 0x01C5},\n+\t{0xB05F, 0x0206},\n+\t{0xB016, 0x1335},\n+\t{0xFFFF, 100},\n+\t{0xA893, 0x8261},\n+\t{0xA894, 0x89d8},\n+\t{0xA895, 0x131d},\n+\t{0xA896, 0x4251},\n+\t{0xA897, 0x9D8A},\n+\t{0xA898, 0x0BD8},\n+\t{0xA899, 0x2245},\n+\t{0xA89A, 0xAB9B},\n+\t{0xA89B, 0x03B9},\n+\t{0xA89C, 0x8041},\n+\t{0xA89D, 0xE07E},\n+\t{0xA89E, 0x0307},\n+\t{0xFFFF, 100},\n+\t{0xA88D, 0x0004},\n+\t{0xA800, 0x0E68},\n+\t{0xA801, 0x0000},\n+\t{0xA802, 0x000C},\n+\t{0xA803, 0x0000},\n+\t{0xA804, 0x0E68},\n+\t{0xA805, 0x0000},\n+\t{0xA806, 0x0440},\n+\t{0xA807, 0x0000},\n+\t{0xA808, 0x0E68},\n+\t{0xA809, 0x0000},\n+\t{0xA80A, 0x0884},\n+\t{0xA80B, 0x0000},\n+\t{0xA80C, 0x0E68},\n+\t{0xA80D, 0x0000},\n+\t{0xA80E, 0x0CC8},\n+\t{0xA80F, 0x0000},\n+\t{0xA810, 0x0E68},\n+\t{0xA811, 0x0000},\n+\t{0xA812, 0x2000},\n+\t{0xA813, 0x0000},\n+\t{0xA882, 0x0081},\n+\t{0xA88C, 0x403A},\n+\t{0xA88F, 0x031E},\n+\t{0xA892, 0x0351},\n+\t{0x9813, 0x13FF},\n+\t{0x981B, 0x7608},\n+\n+\t{0xB008, 0x0000},\n+\t{0xB015, 0x1513},\n+\n+\t{0xFFFF, 100}\n+};\n+\n+static struct regval_list irs1125_seq_cfg[] = {\n+\t{0xC3A0, 0x823D},\n+\t{0xC3A1, 0xB13B},\n+\t{0xC3A2, 0x0313},\n+\t{0xC3A3, 0x4659},\n+\t{0xC3A4, 0xC4EC},\n+\t{0xC3A5, 0x03CE},\n+\t{0xC3A6, 0x4259},\n+\t{0xC3A7, 0xC4EC},\n+\t{0xC3A8, 0x03CE},\n+\t{0xC3A9, 0x8839},\n+\t{0xC3AA, 0x89D8},\n+\t{0xC3AB, 0x031D},\n+\n+\t{0xC24C, 0x5529},\n+\t{0xC24D, 0x0000},\n+\t{0xC24E, 0x1200},\n+\t{0xC24F, 0x6CB2},\n+\t{0xC250, 0x0000},\n+\t{0xC251, 0x5529},\n+\t{0xC252, 0x42F4},\n+\t{0xC253, 0xD1AF},\n+\t{0xC254, 0x8A18},\n+\t{0xC255, 0x0002},\n+\t{0xC256, 0x5529},\n+\t{0xC257, 0x6276},\n+\t{0xC258, 0x11A7},\n+\t{0xC259, 0xD907},\n+\t{0xC25A, 0x0000},\n+\t{0xC25B, 0x5529},\n+\t{0xC25C, 0x07E0},\n+\t{0xC25D, 0x7BFE},\n+\t{0xC25E, 0x6402},\n+\t{0xC25F, 0x0019},\n+\n+\t{0xC3AC, 0x0007},\n+\t{0xC3AD, 0xED88},\n+\t{0xC320, 0x003E},\n+\t{0xC321, 0x0000},\n+\t{0xC322, 0x2000},\n+\t{0xC323, 0x0000},\n+\t{0xC324, 0x0271},\n+\t{0xC325, 0x0000},\n+\t{0xC326, 0x000C},\n+\t{0xC327, 0x0000},\n+\t{0xC328, 0x0271},\n+\t{0xC329, 0x0000},\n+\t{0xC32A, 0x0440},\n+\t{0xC32B, 0x0000},\n+\t{0xC32C, 0x0271},\n+\t{0xC32D, 0x0000},\n+\t{0xC32E, 0x0884},\n+\t{0xC32F, 0x0000},\n+\t{0xC330, 0x0271},\n+\t{0xC331, 0x0000},\n+\t{0xC332, 0x0CC8},\n+\t{0xC333, 0x0000},\n+\t{0xA88D, 0x0004},\n+\n+\t{0xA890, 0x0000},\n+\t{0xC219, 0x0002},\n+\t{0xC21A, 0x0000},\n+\t{0xC21B, 0x0000},\n+\t{0xC21C, 0x00CD},\n+\t{0xC21D, 0x0009},\n+\t{0xC21E, 0x00CD},\n+\t{0xC21F, 0x0009},\n+\n+\t{0xA87C, 0x0000},\n+\t{0xC032, 0x0001},\n+\t{0xC034, 0x0000},\n+\t{0xC035, 0x0001},\n+\t{0xC039, 0x0000},\n+\t{0xC401, 0x0002},\n+\n+\t{0xFFFF, 1},\n+\t{0xA87C, 0x0001}\n+};\n+\n+static int irs1125_write(struct v4l2_subdev *sd, u16 reg, u16 val)\n+{\n+\tint ret;\n+\tunsigned char data[4] = { reg >> 8, reg & 0xff, val >> 8, val & 0xff};\n+\tstruct i2c_client *client = v4l2_get_subdevdata(sd);\n+\n+\tret = i2c_master_send(client, data, 4);\n+\tif (ret < 0)\n+\t\tdev_err(&client->dev, \"%s: i2c write error, reg: %x\\n\",\n+\t\t\t__func__, reg);\n+\n+\treturn ret;\n+}\n+\n+static int irs1125_read(struct v4l2_subdev *sd, u16 reg, u16 *val)\n+{\n+\tint ret;\n+\tunsigned char data_w[2] = { reg >> 8, reg & 0xff };\n+\tchar rdval[2];\n+\n+\tstruct i2c_client *client = v4l2_get_subdevdata(sd);\n+\n+\tret = i2c_master_send(client, data_w, 2);\n+\tif (ret < 0) {\n+\t\tdev_dbg(&client->dev, \"%s: i2c write error, reg: %x\\n\",\n+\t\t\t__func__, reg);\n+\t\treturn ret;\n+\t}\n+\n+\tret = i2c_master_recv(client, rdval, 2);\n+\tif (ret < 0)\n+\t\tdev_err(&client->dev, \"%s: i2c read error, reg: %x\\n\",\n+\t\t\t__func__, reg);\n+\n+\t*val = rdval[1] | (rdval[0] << 8);\n+\n+\treturn ret;\n+}\n+\n+static int irs1125_write_array(struct v4l2_subdev *sd,\n+\t\t\t       struct regval_list *regs, int array_size)\n+{\n+\tint i, ret;\n+\n+\tfor (i = 0; i < array_size; i++) {\n+\t\tif (regs[i].addr == 0xFFFF) {\n+\t\t\tmsleep(regs[i].data);\n+\t\t} else {\n+\t\t\tret = irs1125_write(sd, regs[i].addr, regs[i].data);\n+\t\t\tif (ret < 0)\n+\t\t\t\treturn ret;\n+\t\t}\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int irs1125_stream_on(struct v4l2_subdev *sd)\n+{\n+\tint ret;\n+\tstruct irs1125 *irs1125 = to_state(sd);\n+\tstruct i2c_client *client = v4l2_get_subdevdata(sd);\n+\n+\tv4l2_ctrl_grab(irs1125->ctrl_numseq, 1);\n+\tv4l2_ctrl_grab(irs1125->ctrl_modplls, 1);\n+\n+\tret = irs1125_write(sd, 0xC400, 0x0001);\n+\tif (ret < 0) {\n+\t\tdev_err(&client->dev, \"error enabling firmware: %d\", ret);\n+\t\treturn ret;\n+\t}\n+\n+\tmsleep(100);\n+\n+\treturn irs1125_write(sd, 0xA87C, 0x0001);\n+}\n+\n+static int irs1125_stream_off(struct v4l2_subdev *sd)\n+{\n+\tint ret;\n+\tstruct irs1125 *irs1125 = to_state(sd);\n+\tstruct i2c_client *client = v4l2_get_subdevdata(sd);\n+\n+\tv4l2_ctrl_grab(irs1125->ctrl_numseq, 0);\n+\tv4l2_ctrl_grab(irs1125->ctrl_modplls, 0);\n+\n+\tret = irs1125_write(sd, 0xA87C, 0x0000);\n+\tif (ret < 0) {\n+\t\tdev_err(&client->dev, \"error disabling trigger: %d\", ret);\n+\t\treturn ret;\n+\t}\n+\n+\tmsleep(100);\n+\n+\treturn irs1125_write(sd, 0xC400, 0x0002);\n+}\n+\n+static int __sensor_init(struct v4l2_subdev *sd)\n+{\n+\tunsigned int cnt, idx;\n+\tint ret;\n+\tu16 val;\n+\tstruct i2c_client *client = v4l2_get_subdevdata(sd);\n+\tstruct irs1125 *irs1125 = to_state(sd);\n+\tconst struct firmware *fw;\n+\tstruct regval_list *reg_data;\n+\n+\tcnt = 0;\n+\twhile (1) {\n+\t\tret = irs1125_read(sd, 0xC40F, &val);\n+\t\tif (ret < 0) {\n+\t\t\tdev_err(&client->dev, \"read register 0xC40F failed\\n\");\n+\t\t\treturn ret;\n+\t\t}\n+\t\tif (CHECK_BIT(val, 14) == 0)\n+\t\t\tbreak;\n+\n+\t\tif (cnt >= 5) {\n+\t\t\tdev_err(&client->dev, \"timeout waiting for 0xC40F\\n\");\n+\t\t\treturn -EAGAIN;\n+\t\t}\n+\n+\t\tcnt++;\n+\t}\n+\n+\tret = irs1125_write_array(sd, irs1125_26MHz,\n+\t\t\t\t  ARRAY_SIZE(irs1125_26MHz));\n+\tif (ret < 0) {\n+\t\tdev_err(&client->dev, \"write sensor default regs error\\n\");\n+\t\treturn ret;\n+\t}\n+\n+\t/* set CSI-2 number of data lanes */\n+\tif (irs1125->ep.bus.mipi_csi2.num_data_lanes == 1) {\n+\t\tval = 0x0001;\n+\t} else if (irs1125->ep.bus.mipi_csi2.num_data_lanes == 2) {\n+\t\tval = 0x0081;\n+\t} else {\n+\t\tdev_err(&client->dev, \"invalid number of data lanes %d\\n\",\n+\t\t\tirs1125->ep.bus.mipi_csi2.num_data_lanes);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tret = irs1125_write(sd, IRS1125_REG_CSICFG, val);\n+\tif (ret < 0) {\n+\t\tdev_err(&client->dev, \"write sensor csi2 config error\\n\");\n+\t\treturn ret;\n+\t}\n+\n+\t/* request the firmware, this will block and timeout */\n+\tret = request_firmware(&fw, IRS1125_ALTERNATE_FW, &client->dev);\n+\tif (ret) {\n+\t\tdev_err(&client->dev,\n+\t\t\t\"did not find the firmware file '%s' (status %d)\\n\",\n+\t\t\tIRS1125_ALTERNATE_FW, ret);\n+\t\treturn ret;\n+\t}\n+\n+\tif (fw->size % 4) {\n+\t\tdev_err(&client->dev, \"firmware file '%s' invalid\\n\",\n+\t\t\tIRS1125_ALTERNATE_FW);\n+\t\trelease_firmware(fw);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tfor (idx = 0; idx < fw->size; idx += 4)\t{\n+\t\treg_data = (struct regval_list *)&fw->data[idx];\n+\t\tret = irs1125_write(sd, reg_data->addr, reg_data->data);\n+\t\tif (ret < 0) {\n+\t\t\tdev_err(&client->dev, \"firmware write error\\n\");\n+\t\t\trelease_firmware(fw);\n+\t\t\treturn ret;\n+\t\t}\n+\t}\n+\trelease_firmware(fw);\n+\n+\tret = irs1125_write_array(sd, irs1125_seq_cfg,\n+\t\t\t\t  ARRAY_SIZE(irs1125_seq_cfg));\n+\tif (ret < 0) {\n+\t\tdev_err(&client->dev, \"write default sequence failed\\n\");\n+\t\treturn ret;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int irs1125_sensor_power(struct v4l2_subdev *sd, int on)\n+{\n+\tint ret = 0;\n+\tstruct irs1125 *irs1125 = to_state(sd);\n+\tstruct i2c_client *client = v4l2_get_subdevdata(sd);\n+\n+\tmutex_lock(&irs1125->lock);\n+\n+\tif (on && !irs1125->power_count) {\n+\t\tgpiod_set_value_cansleep(irs1125->reset, 1);\n+\t\tmsleep(RESET_ACTIVE_DELAY_MS);\n+\n+\t\tret = clk_prepare_enable(irs1125->xclk);\n+\t\tif (ret < 0) {\n+\t\t\tdev_err(&client->dev, \"clk prepare enable failed\\n\");\n+\t\t\tgoto out;\n+\t\t}\n+\n+\t\tret = __sensor_init(sd);\n+\t\tif (ret < 0) {\n+\t\t\tclk_disable_unprepare(irs1125->xclk);\n+\t\t\tdev_err(&client->dev,\n+\t\t\t\t\"Camera not available, check Power\\n\");\n+\t\t\tgoto out;\n+\t\t}\n+\t} else if (!on && irs1125->power_count == 1) {\n+\t\tgpiod_set_value_cansleep(irs1125->reset, 0);\n+\t}\n+\n+\t/* Update the power count. */\n+\tirs1125->power_count += on ? 1 : -1;\n+\tWARN_ON(irs1125->power_count < 0);\n+\n+out:\n+\tmutex_unlock(&irs1125->lock);\n+\n+\treturn ret;\n+}\n+\n+#ifdef CONFIG_VIDEO_ADV_DEBUG\n+static int irs1125_sensor_get_register(struct v4l2_subdev *sd,\n+\t\t\t\t       struct v4l2_dbg_register *reg)\n+{\n+\tu16 val;\n+\tint ret;\n+\n+\tret = irs1125_read(sd, reg->reg & 0xffff, &val);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\treg->val = val;\n+\treg->size = 1;\n+\n+\treturn 0;\n+}\n+\n+static int irs1125_sensor_set_register(struct v4l2_subdev *sd,\n+\t\t\t\t       const struct v4l2_dbg_register *reg)\n+{\n+\treturn irs1125_write(sd, reg->reg & 0xffff, reg->val & 0xffff);\n+}\n+#endif\n+\n+static const struct v4l2_subdev_core_ops irs1125_subdev_core_ops = {\n+\t.s_power = irs1125_sensor_power,\n+#ifdef CONFIG_VIDEO_ADV_DEBUG\n+\t.g_register = irs1125_sensor_get_register,\n+\t.s_register = irs1125_sensor_set_register,\n+#endif\n+};\n+\n+static int irs1125_s_stream(struct v4l2_subdev *sd, int enable)\n+{\n+\tif (enable)\n+\t\treturn irs1125_stream_on(sd);\n+\telse\n+\t\treturn irs1125_stream_off(sd);\n+}\n+\n+static const struct v4l2_subdev_video_ops irs1125_subdev_video_ops = {\n+\t.s_stream = irs1125_s_stream,\n+};\n+\n+static int irs1125_enum_mbus_code(struct v4l2_subdev *sd,\n+\t\t\t\t  struct v4l2_subdev_pad_config *cfg,\n+\tstruct v4l2_subdev_mbus_code_enum *code)\n+{\n+\tif (code->index > 0)\n+\t\treturn -EINVAL;\n+\n+\tcode->code = MEDIA_BUS_FMT_Y12_1X12;\n+\n+\treturn 0;\n+}\n+\n+static int irs1125_set_get_fmt(struct v4l2_subdev *sd,\n+\t\t\t       struct v4l2_subdev_pad_config *cfg,\n+\t\t\t       struct v4l2_subdev_format *format)\n+{\n+\tstruct v4l2_mbus_framefmt *fmt = &format->format;\n+\tstruct irs1125 *irs1125 = to_state(sd);\n+\n+\tif (format->pad != 0)\n+\t\treturn -EINVAL;\n+\n+\t/* Only one format is supported, so return that */\n+\tmemset(fmt, 0, sizeof(*fmt));\n+\tfmt->code = MEDIA_BUS_FMT_Y12_1X12;\n+\tfmt->colorspace = V4L2_COLORSPACE_RAW;\n+\tfmt->field = V4L2_FIELD_NONE;\n+\tfmt->width = IRS1125_WINDOW_WIDTH_DEF;\n+\tfmt->height = IRS1125_WINDOW_HEIGHT_DEF * irs1125->num_seq;\n+\n+\treturn 0;\n+}\n+\n+static const struct v4l2_subdev_pad_ops irs1125_subdev_pad_ops = {\n+\t.enum_mbus_code = irs1125_enum_mbus_code,\n+\t.set_fmt = irs1125_set_get_fmt,\n+\t.get_fmt = irs1125_set_get_fmt,\n+};\n+\n+static const struct v4l2_subdev_ops irs1125_subdev_ops = {\n+\t.core = &irs1125_subdev_core_ops,\n+\t.video = &irs1125_subdev_video_ops,\n+\t.pad = &irs1125_subdev_pad_ops,\n+};\n+\n+static int irs1125_s_ctrl(struct v4l2_ctrl *ctrl)\n+{\n+\tstruct irs1125 *dev = container_of(ctrl->handler,\n+\t\t\t\t\tstruct irs1125, ctrl_handler);\n+\tstruct i2c_client *client = v4l2_get_subdevdata(&dev->sd);\n+\tint err, i;\n+\tstruct irs1125_mod_pll *mod_cur, *mod_new;\n+\tstruct irs1125_seq_cfg *cfg_cur, *cfg_new;\n+\tu16 addr, val;\n+\n+\terr = 0;\n+\n+\tswitch (ctrl->id) {\n+\tcase IRS1125_CID_SAFE_RECONFIG:\n+\t{\n+\t\tstruct irs1125_illu *illu_cur, *illu_new;\n+\n+\t\tillu_new = (struct irs1125_illu *)ctrl->p_new.p;\n+\t\tillu_cur = (struct irs1125_illu *)ctrl->p_cur.p;\n+\t\tfor (i = 0; i < IRS1125_NUM_SEQ_ENTRIES; i++) {\n+\t\t\tif (illu_cur[i].exposure != illu_new[i].exposure) {\n+\t\t\t\taddr = 0xA850 + i * 2;\n+\t\t\t\tval = illu_new[i].exposure;\n+\t\t\t\terr = irs1125_write(&dev->sd, addr, val);\n+\t\t\t\tif (err < 0)\n+\t\t\t\t\tbreak;\n+\t\t\t}\n+\t\t\tif (illu_cur[i].framerate != illu_new[i].framerate) {\n+\t\t\t\taddr = 0xA851 + i * 2;\n+\t\t\t\tval = illu_new[i].framerate;\n+\t\t\t\terr = irs1125_write(&dev->sd, addr, val);\n+\t\t\t\tif (err < 0)\n+\t\t\t\t\tbreak;\n+\t\t\t}\n+\t\t}\n+\t\tbreak;\n+\t}\n+\tcase IRS1125_CID_MOD_PLL:\n+\t\tmod_new = (struct irs1125_mod_pll *)ctrl->p_new.p;\n+\t\tmod_cur = (struct irs1125_mod_pll *)ctrl->p_cur.p;\n+\t\tfor (i = 0; i < IRS1125_NUM_MOD_PLLS; i++) {\n+\t\t\tif (mod_cur[i].pllcfg1 != mod_new[i].pllcfg1) {\n+\t\t\t\taddr = 0xC3A0 + i * 3;\n+\t\t\t\tval = mod_new[i].pllcfg1;\n+\t\t\t\terr = irs1125_write(&dev->sd, addr, val);\n+\t\t\t\tif (err < 0)\n+\t\t\t\t\tbreak;\n+\t\t\t}\n+\t\t\tif (mod_cur[i].pllcfg2 != mod_new[i].pllcfg2) {\n+\t\t\t\taddr = 0xC3A1 + i * 3;\n+\t\t\t\tval = mod_new[i].pllcfg2;\n+\t\t\t\terr = irs1125_write(&dev->sd, addr, val);\n+\t\t\t\tif (err < 0)\n+\t\t\t\t\tbreak;\n+\t\t\t}\n+\t\t\tif (mod_cur[i].pllcfg3 != mod_new[i].pllcfg3) {\n+\t\t\t\taddr = 0xC3A2 + i * 3;\n+\t\t\t\tval = mod_new[i].pllcfg3;\n+\t\t\t\terr = irs1125_write(&dev->sd, addr, val);\n+\t\t\t\tif (err < 0)\n+\t\t\t\t\tbreak;\n+\t\t\t}\n+\t\t\tif (mod_cur[i].pllcfg4 != mod_new[i].pllcfg4) {\n+\t\t\t\taddr = 0xC24C + i * 5;\n+\t\t\t\tval = mod_new[i].pllcfg4;\n+\t\t\t\terr = irs1125_write(&dev->sd, addr, val);\n+\t\t\t\tif (err < 0)\n+\t\t\t\t\tbreak;\n+\t\t\t}\n+\t\t\tif (mod_cur[i].pllcfg5 != mod_new[i].pllcfg5) {\n+\t\t\t\taddr = 0xC24D + i * 5;\n+\t\t\t\tval = mod_new[i].pllcfg5;\n+\t\t\t\terr = irs1125_write(&dev->sd, addr, val);\n+\t\t\t\tif (err < 0)\n+\t\t\t\t\tbreak;\n+\t\t\t}\n+\t\t\tif (mod_cur[i].pllcfg6 != mod_new[i].pllcfg6) {\n+\t\t\t\taddr = 0xC24E + i * 5;\n+\t\t\t\tval = mod_new[i].pllcfg6;\n+\t\t\t\terr = irs1125_write(&dev->sd, addr, val);\n+\t\t\t\tif (err < 0)\n+\t\t\t\t\tbreak;\n+\t\t\t}\n+\t\t\tif (mod_cur[i].pllcfg7 != mod_new[i].pllcfg7) {\n+\t\t\t\taddr = 0xC24F + i * 5;\n+\t\t\t\tval = mod_new[i].pllcfg7;\n+\t\t\t\terr = irs1125_write(&dev->sd, addr, val);\n+\t\t\t\tif (err < 0)\n+\t\t\t\t\tbreak;\n+\t\t\t}\n+\t\t\tif (mod_cur[i].pllcfg8 != mod_new[i].pllcfg8) {\n+\t\t\t\taddr = 0xC250 + i * 5;\n+\t\t\t\tval = mod_new[i].pllcfg8;\n+\t\t\t\terr = irs1125_write(&dev->sd, addr, val);\n+\t\t\t\tif (err < 0)\n+\t\t\t\t\tbreak;\n+\t\t\t}\n+\t\t}\n+\t\tbreak;\n+\tcase IRS1125_CID_SEQ_CONFIG:\n+\t\tcfg_new = (struct irs1125_seq_cfg *)ctrl->p_new.p;\n+\t\tcfg_cur = (struct irs1125_seq_cfg *)ctrl->p_cur.p;\n+\t\tfor (i = 0; i < IRS1125_NUM_SEQ_ENTRIES; i++) {\n+\t\t\tif (cfg_cur[i].exposure != cfg_new[i].exposure)\t{\n+\t\t\t\taddr = IRS1125_REG_DMEM_SHADOW + i * 4;\n+\t\t\t\tval = cfg_new[i].exposure;\n+\t\t\t\terr = irs1125_write(&dev->sd, addr, val);\n+\t\t\t\tif (err < 0)\n+\t\t\t\t\tbreak;\n+\t\t\t}\n+\t\t\tif (cfg_cur[i].framerate != cfg_new[i].framerate) {\n+\t\t\t\taddr = IRS1125_REG_DMEM_SHADOW + 1 + i * 4;\n+\t\t\t\tval = cfg_new[i].framerate;\n+\t\t\t\terr = irs1125_write(&dev->sd, addr, val);\n+\t\t\t\tif (err < 0)\n+\t\t\t\t\tbreak;\n+\t\t\t}\n+\t\t\tif (cfg_cur[i].ps != cfg_new[i].ps) {\n+\t\t\t\taddr = IRS1125_REG_DMEM_SHADOW + 2 + i * 4;\n+\t\t\t\tval = cfg_new[i].ps;\n+\t\t\t\terr = irs1125_write(&dev->sd, addr, val);\n+\t\t\t\tif (err < 0)\n+\t\t\t\t\tbreak;\n+\t\t\t}\n+\t\t\tif (cfg_cur[i].pll != cfg_new[i].pll) {\n+\t\t\t\taddr = IRS1125_REG_DMEM_SHADOW + 3 + i * 4;\n+\t\t\t\tval = cfg_new[i].pll;\n+\t\t\t\terr = irs1125_write(&dev->sd, addr, val);\n+\t\t\t\tif (err < 0)\n+\t\t\t\t\tbreak;\n+\t\t\t}\n+\t\t}\n+\t\tbreak;\n+\tcase IRS1125_CID_NUM_SEQS:\n+\t\terr = irs1125_write(&dev->sd, 0xA88D, ctrl->val - 1);\n+\t\tif (err >= 0)\n+\t\t\tdev->num_seq = ctrl->val;\n+\t\tbreak;\n+\tcase IRS1125_CID_CONTINUOUS_TRIG:\n+\t\tif (ctrl->val == 0)\n+\t\t\terr = irs1125_write(&dev->sd, 0xA87C, 0);\n+\t\telse\n+\t\t\terr = irs1125_write(&dev->sd, 0xA87C, 1);\n+\t\tbreak;\n+\tcase IRS1125_CID_TRIGGER:\n+\t\tif (ctrl->val != 0) {\n+\t\t\terr = irs1125_write(&dev->sd, 0xA87C, 1);\n+\t\t\tif (err >= 0)\n+\t\t\t\terr = irs1125_write(&dev->sd, 0xA87C, 0);\n+\t\t}\n+\t\tbreak;\n+\tcase IRS1125_CID_RECONFIG:\n+\t\tif (ctrl->val != 0)\n+\t\t\terr = irs1125_write(&dev->sd, 0xA87A, 1);\n+\t\tbreak;\n+\tcase IRS1125_CID_ILLU_ON:\n+\t\tif (ctrl->val == 0)\n+\t\t\terr = irs1125_write(&dev->sd, 0xA892, 0x377);\n+\t\telse\n+\t\t\terr = irs1125_write(&dev->sd, 0xA892, 0x355);\n+\t\tbreak;\n+\tdefault:\n+\t\tbreak;\n+\t}\n+\n+\tif (err < 0)\n+\t\tdev_err(&client->dev, \"Error executing control ID: %d, val %d, err %d\",\n+\t\t\tctrl->id, ctrl->val, err);\n+\telse\n+\t\terr = 0;\n+\n+\treturn err;\n+}\n+\n+static const struct v4l2_ctrl_ops irs1125_ctrl_ops = {\n+\t.s_ctrl = irs1125_s_ctrl,\n+};\n+\n+static const struct v4l2_ctrl_config irs1125_custom_ctrls[] = {\n+\t{\n+\t\t.ops = &irs1125_ctrl_ops,\n+\t\t.id = IRS1125_CID_NUM_SEQS,\n+\t\t.name = \"Change number of sequences\",\n+\t\t.type = V4L2_CTRL_TYPE_INTEGER,\n+\t\t.flags = V4L2_CTRL_FLAG_MODIFY_LAYOUT,\n+\t\t.min = 1,\n+\t\t.max = 20,\n+\t\t.step = 1,\n+\t\t.def = 5,\n+\t}, {\n+\t\t.ops = &irs1125_ctrl_ops,\n+\t\t.id = IRS1125_CID_MOD_PLL,\n+\t\t.name = \"Reconfigure modulation PLLs\",\n+\t\t.type = V4L2_CTRL_TYPE_U16,\n+\t\t.flags = V4L2_CTRL_FLAG_HAS_PAYLOAD,\n+\t\t.min = 0,\n+\t\t.max = U16_MAX,\n+\t\t.step = 1,\n+\t\t.def = 0,\n+\t\t.elem_size = sizeof(u16),\n+\t\t.dims = {sizeof(struct irs1125_mod_pll) / sizeof(u16),\n+\t\t\tIRS1125_NUM_MOD_PLLS}\n+\t}, {\n+\t\t.ops = &irs1125_ctrl_ops,\n+\t\t.id = IRS1125_CID_SAFE_RECONFIG,\n+\t\t.name = \"Change exposure and pause of single seq\",\n+\t\t.type = V4L2_CTRL_TYPE_U16,\n+\t\t.flags = V4L2_CTRL_FLAG_HAS_PAYLOAD,\n+\t\t.min = 0,\n+\t\t.max = U16_MAX,\n+\t\t.step = 1,\n+\t\t.def = 0,\n+\t\t.elem_size = sizeof(u16),\n+\t\t.dims = {sizeof(struct irs1125_illu) / sizeof(u16),\n+\t\t\tIRS1125_NUM_SEQ_ENTRIES}\n+\t}, {\n+\t\t.ops = &irs1125_ctrl_ops,\n+\t\t.id = IRS1125_CID_SEQ_CONFIG,\n+\t\t.name = \"Change sequence settings\",\n+\t\t.type = V4L2_CTRL_TYPE_U16,\n+\t\t.flags = V4L2_CTRL_FLAG_HAS_PAYLOAD,\n+\t\t.min = 0,\n+\t\t.max = U16_MAX,\n+\t\t.step = 1,\n+\t\t.def = 0,\n+\t\t.elem_size = sizeof(u16),\n+\t\t.dims = {sizeof(struct irs1125_seq_cfg) / sizeof(u16),\n+\t\t\tIRS1125_NUM_SEQ_ENTRIES}\n+\t}, {\n+\t\t.ops = &irs1125_ctrl_ops,\n+\t\t.id = IRS1125_CID_CONTINUOUS_TRIG,\n+\t\t.name = \"Enable/disable continuous trigger\",\n+\t\t.type = V4L2_CTRL_TYPE_BOOLEAN,\n+\t\t.flags = V4L2_CTRL_FLAG_EXECUTE_ON_WRITE,\n+\t\t.min = 0,\n+\t\t.max = 1,\n+\t\t.step = 1,\n+\t\t.def = 0\n+\t}, {\n+\t\t.ops = &irs1125_ctrl_ops,\n+\t\t.id = IRS1125_CID_TRIGGER,\n+\t\t.name = \"Capture a single sequence\",\n+\t\t.type = V4L2_CTRL_TYPE_BOOLEAN,\n+\t\t.flags = V4L2_CTRL_FLAG_EXECUTE_ON_WRITE,\n+\t\t.min = 0,\n+\t\t.max = 1,\n+\t\t.step = 1,\n+\t\t.def = 0\n+\t}, {\n+\t\t.ops = &irs1125_ctrl_ops,\n+\t\t.id = IRS1125_CID_RECONFIG,\n+\t\t.name = \"Trigger imager reconfiguration\",\n+\t\t.type = V4L2_CTRL_TYPE_BOOLEAN,\n+\t\t.flags = V4L2_CTRL_FLAG_EXECUTE_ON_WRITE,\n+\t\t.min = 0,\n+\t\t.max = 1,\n+\t\t.step = 1,\n+\t\t.def = 0\n+\t}, {\n+\t\t.ops = &irs1125_ctrl_ops,\n+\t\t.id = IRS1125_CID_ILLU_ON,\n+\t\t.name = \"Turn illu on or off\",\n+\t\t.type = V4L2_CTRL_TYPE_BOOLEAN,\n+\t\t.flags = V4L2_CTRL_FLAG_EXECUTE_ON_WRITE,\n+\t\t.min = 0,\n+\t\t.max = 1,\n+\t\t.step = 1,\n+\t\t.def = 1\n+\t}, {\n+\t\t.ops = &irs1125_ctrl_ops,\n+\t\t.id = IRS1125_CID_IDENT0,\n+\t\t.name = \"Get ident 0 information\",\n+\t\t.type = V4L2_CTRL_TYPE_INTEGER,\n+\t\t.flags = V4L2_CTRL_FLAG_READ_ONLY,\n+\t\t.min = S32_MIN,\n+\t\t.max = S32_MAX,\n+\t\t.step = 1,\n+\t\t.def = 0\n+\t}, {\n+\t\t.ops = &irs1125_ctrl_ops,\n+\t\t.id = IRS1125_CID_IDENT1,\n+\t\t.name = \"Get ident 1 information\",\n+\t\t.type = V4L2_CTRL_TYPE_INTEGER,\n+\t\t.flags = V4L2_CTRL_FLAG_READ_ONLY,\n+\t\t.min = S32_MIN,\n+\t\t.max = S32_MAX,\n+\t\t.step = 1,\n+\t\t.def = 0\n+\t}, {\n+\t\t.ops = &irs1125_ctrl_ops,\n+\t\t.id = IRS1125_CID_IDENT2,\n+\t\t.name = \"Get ident 2 information\",\n+\t\t.type = V4L2_CTRL_TYPE_INTEGER,\n+\t\t.flags = V4L2_CTRL_FLAG_READ_ONLY,\n+\t\t.min = S32_MIN,\n+\t\t.max = S32_MAX,\n+\t\t.step = 1,\n+\t\t.def = 0\n+\t}\n+};\n+\n+static int irs1125_detect(struct v4l2_subdev *sd)\n+{\n+\tu16 read;\n+\tint ret;\n+\tstruct i2c_client *client = v4l2_get_subdevdata(sd);\n+\n+\tret = irs1125_read(sd, IRS1125_REG_DESIGN_STEP, &read);\n+\tif (ret < 0) {\n+\t\tdev_err(&client->dev, \"error reading from i2c\\n\");\n+\t\treturn ret;\n+\t}\n+\n+\tif (read != IRS1125_DESIGN_STEP_EXPECTED) {\n+\t\tdev_err(&client->dev, \"Design step expected 0x%x got 0x%x\",\n+\t\t\tIRS1125_DESIGN_STEP_EXPECTED, read);\n+\t\treturn -ENODEV;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int irs1125_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)\n+{\n+\tstruct v4l2_mbus_framefmt *format =\n+\tv4l2_subdev_get_try_format(sd, fh->pad, 0);\n+\n+\tformat->code = MEDIA_BUS_FMT_Y12_1X12;\n+\tformat->width = IRS1125_WINDOW_WIDTH_DEF;\n+\tformat->height = IRS1125_WINDOW_HEIGHT_DEF;\n+\tformat->field = V4L2_FIELD_NONE;\n+\tformat->colorspace = V4L2_COLORSPACE_RAW;\n+\n+\treturn 0;\n+}\n+\n+static const struct v4l2_subdev_internal_ops irs1125_subdev_internal_ops = {\n+\t.open = irs1125_open,\n+};\n+\n+static int irs1125_ctrls_init(struct irs1125 *sensor, struct device *dev)\n+{\n+\tstruct v4l2_ctrl *ctrl;\n+\tint err, i;\n+\tstruct v4l2_ctrl_handler *hdl;\n+\n+\thdl = &sensor->ctrl_handler;\n+\tv4l2_ctrl_handler_init(hdl, ARRAY_SIZE(irs1125_custom_ctrls));\n+\n+\tfor (i = 0; i < ARRAY_SIZE(irs1125_custom_ctrls); i++)\t{\n+\t\tctrl = v4l2_ctrl_new_custom(hdl, &irs1125_custom_ctrls[i],\n+\t\t\t\t\t    NULL);\n+\t\tif (!ctrl)\n+\t\t\tdev_err(dev, \"Failed to init custom control %s\\n\",\n+\t\t\t\tirs1125_custom_ctrls[i].name);\n+\t\telse if (irs1125_custom_ctrls[i].id == IRS1125_CID_NUM_SEQS)\n+\t\t\tsensor->ctrl_numseq = ctrl;\n+\t\telse if (irs1125_custom_ctrls[i].id == IRS1125_CID_MOD_PLL)\n+\t\t\tsensor->ctrl_modplls = ctrl;\n+\t}\n+\n+\tif (hdl->error)\t{\n+\t\tdev_err(dev, \"Error %d adding controls\\n\", hdl->error);\n+\t\terr = hdl->error;\n+\t\tgoto error_ctrls;\n+\t}\n+\n+\tsensor->sd.ctrl_handler = hdl;\n+\treturn 0;\n+\n+error_ctrls:\n+\tv4l2_ctrl_handler_free(&sensor->ctrl_handler);\n+\treturn -err;\n+}\n+\n+static int irs1125_ident_setup(struct irs1125 *sensor, struct device *dev)\n+{\n+\tint ret;\n+\tstruct v4l2_ctrl *ctrl;\n+\tstruct v4l2_subdev *sd;\n+\tu16 read;\n+\n+\tsd = &sensor->sd;\n+\n+\tctrl = v4l2_ctrl_find(&sensor->ctrl_handler, IRS1125_CID_IDENT0);\n+\tif (!ctrl) {\n+\t\tdev_err(dev, \"could not find device ctrl.\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tret = irs1125_read(sd, IRS1125_REG_EFUSEVAL2, &read);\n+\tif (ret < 0) {\n+\t\tdev_err(dev, \"error reading from i2c\\n\");\n+\t\treturn -EIO;\n+\t}\n+\n+\tv4l2_ctrl_s_ctrl(ctrl, read);\n+\n+\tctrl = v4l2_ctrl_find(&sensor->ctrl_handler, IRS1125_CID_IDENT1);\n+\tif (!ctrl) {\n+\t\tdev_err(dev, \"could not find device ctrl.\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tret = irs1125_read(sd, IRS1125_REG_EFUSEVAL3, &read);\n+\tif (ret < 0) {\n+\t\tdev_err(dev, \"error reading from i2c\\n\");\n+\t\treturn -EIO;\n+\t}\n+\n+\tv4l2_ctrl_s_ctrl(ctrl, read);\n+\n+\tctrl = v4l2_ctrl_find(&sensor->ctrl_handler, IRS1125_CID_IDENT2);\n+\tif (!ctrl) {\n+\t\tdev_err(dev, \"could not find device ctrl.\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tret = irs1125_read(sd, IRS1125_REG_EFUSEVAL4, &read);\n+\tif (ret < 0) {\n+\t\tdev_err(dev, \"error reading from i2c\\n\");\n+\t\treturn -EIO;\n+\t}\n+\tv4l2_ctrl_s_ctrl(ctrl, read & 0xFFFC);\n+\n+\treturn 0;\n+}\n+\n+static int irs1125_probe(struct i2c_client *client,\n+\t\t\t const struct i2c_device_id *id)\n+{\n+\tstruct device *dev = &client->dev;\n+\tstruct irs1125 *sensor;\n+\tint ret;\n+\tstruct fwnode_handle *endpoint;\n+\tu32 xclk_freq;\n+\tint gpio_num;\n+\n+\tsensor = devm_kzalloc(dev, sizeof(*sensor), GFP_KERNEL);\n+\tif (!sensor)\n+\t\treturn -ENOMEM;\n+\n+\tv4l2_i2c_subdev_init(&sensor->sd, client, &irs1125_subdev_ops);\n+\n+\t/* Get CSI2 bus config */\n+\tendpoint = fwnode_graph_get_next_endpoint(dev_fwnode(dev),\n+\t\t\t\t\t\t  NULL);\n+\tif (!endpoint) {\n+\t\tdev_err(dev, \"endpoint node not found\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tret = v4l2_fwnode_endpoint_parse(endpoint, &sensor->ep);\n+\tfwnode_handle_put(endpoint);\n+\tif (ret) {\n+\t\tdev_err(dev, \"Could not parse endpoint\\n\");\n+\t\treturn ret;\n+\t}\n+\n+\t/* get system clock (xclk) */\n+\tsensor->xclk = devm_clk_get(dev, NULL);\n+\tif (IS_ERR(sensor->xclk)) {\n+\t\tdev_err(dev, \"could not get xclk\");\n+\t\treturn PTR_ERR(sensor->xclk);\n+\t}\n+\n+\txclk_freq = clk_get_rate(sensor->xclk);\n+\tif (xclk_freq != 26000000) {\n+\t\tdev_err(dev, \"Unsupported clock frequency: %u\\n\", xclk_freq);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tsensor->num_seq = 5;\n+\n+\t/* Request the power down GPIO */\n+\tsensor->reset = devm_gpiod_get(&client->dev, \"pwdn\",\n+\t\t\t\t       GPIOD_OUT_LOW);\n+\n+\tif (IS_ERR(sensor->reset)) {\n+\t\tdev_err(dev, \"could not get reset\");\n+\t\treturn PTR_ERR(sensor->reset);\n+\t}\n+\n+\tgpio_num = desc_to_gpio(sensor->reset);\n+\n+\tmutex_init(&sensor->lock);\n+\n+\tret = irs1125_ctrls_init(sensor, dev);\n+\tif (ret < 0)\n+\t\tgoto mutex_remove;\n+\n+\tsensor->sd.internal_ops = &irs1125_subdev_internal_ops;\n+\tsensor->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;\n+\tsensor->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;\n+\tsensor->pad.flags = MEDIA_PAD_FL_SOURCE;\n+\tret = media_entity_pads_init(&sensor->sd.entity, 1, &sensor->pad);\n+\tif (ret < 0)\n+\t\tgoto mutex_remove;\n+\n+\tgpiod_set_value_cansleep(sensor->reset, 1);\n+\tmsleep(RESET_ACTIVE_DELAY_MS);\n+\n+\tret = irs1125_detect(&sensor->sd);\n+\tif (ret < 0)\n+\t\tgoto error;\n+\n+\tret = irs1125_ident_setup(sensor, dev);\n+\tif (ret < 0)\n+\t\tgoto error;\n+\n+\tgpiod_set_value_cansleep(sensor->reset, 0);\n+\n+\tret = v4l2_async_register_subdev(&sensor->sd);\n+\tif (ret < 0)\n+\t\tgoto error;\n+\n+\tdev_dbg(dev, \"Infineon IRS1125 camera driver probed\\n\");\n+\n+\treturn 0;\n+\n+error:\n+\tmedia_entity_cleanup(&sensor->sd.entity);\n+mutex_remove:\n+\tmutex_destroy(&sensor->lock);\n+\treturn ret;\n+}\n+\n+static int irs1125_remove(struct i2c_client *client)\n+{\n+\tstruct v4l2_subdev *sd = i2c_get_clientdata(client);\n+\tstruct irs1125 *irs1125 = to_state(sd);\n+\n+\tv4l2_async_unregister_subdev(&irs1125->sd);\n+\tmedia_entity_cleanup(&irs1125->sd.entity);\n+\tv4l2_device_unregister_subdev(sd);\n+\tmutex_destroy(&irs1125->lock);\n+\tv4l2_ctrl_handler_free(&irs1125->ctrl_handler);\n+\n+\treturn 0;\n+}\n+\n+#if IS_ENABLED(CONFIG_OF)\n+static const struct of_device_id irs1125_of_match[] = {\n+\t{ .compatible = \"infineon,irs1125\" },\n+\t{ /* sentinel */ },\n+};\n+MODULE_DEVICE_TABLE(of, irs1125_of_match);\n+#endif\n+\n+static struct i2c_driver irs1125_driver = {\n+\t.driver = {\n+\t\t.of_match_table = of_match_ptr(irs1125_of_match),\n+\t\t.name\t = SENSOR_NAME,\n+\t},\n+\t.probe\t\t= irs1125_probe,\n+\t.remove\t\t= irs1125_remove,\n+};\n+\n+module_i2c_driver(irs1125_driver);\n+\n+MODULE_AUTHOR(\"Markus Proeller <markus.proeller@pieye.org>\");\n+MODULE_DESCRIPTION(\"Infineon irs1125 sensor driver\");\n+MODULE_LICENSE(\"GPL v2\");\n+\n--- /dev/null\n+++ b/drivers/media/i2c/irs1125.h\n@@ -0,0 +1,61 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+/*\n+ * A V4L2 driver for Infineon IRS1125 TOF cameras.\n+ * Copyright (C) 2018, pieye GmbH\n+ *\n+ * Based on V4L2 OmniVision OV5647 Image Sensor driver\n+ * Copyright (C) 2016 Ramiro Oliveira <roliveir@synopsys.com>\n+ *\n+ * DT / fwnode changes, and GPIO control taken from ov5640.c\n+ * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. All Rights Reserved.\n+ * Copyright (C) 2014-2017 Mentor Graphics Inc.\n+ *\n+ */\n+\n+#ifndef IRS1125_H\n+#define IRS1125_H\n+\n+#include <linux/v4l2-controls.h>\n+#include <linux/types.h>\n+\n+#define IRS1125_NUM_SEQ_ENTRIES 20\n+#define IRS1125_NUM_MOD_PLLS 4\n+\n+#define IRS1125_CID_CUSTOM_BASE        (V4L2_CID_USER_BASE | 0xf000)\n+#define IRS1125_CID_SAFE_RECONFIG      (IRS1125_CID_CUSTOM_BASE + 0)\n+#define IRS1125_CID_CONTINUOUS_TRIG    (IRS1125_CID_CUSTOM_BASE + 1)\n+#define IRS1125_CID_TRIGGER            (IRS1125_CID_CUSTOM_BASE + 2)\n+#define IRS1125_CID_RECONFIG           (IRS1125_CID_CUSTOM_BASE + 3)\n+#define IRS1125_CID_ILLU_ON            (IRS1125_CID_CUSTOM_BASE + 4)\n+#define IRS1125_CID_NUM_SEQS           (IRS1125_CID_CUSTOM_BASE + 5)\n+#define IRS1125_CID_MOD_PLL            (IRS1125_CID_CUSTOM_BASE + 6)\n+#define IRS1125_CID_SEQ_CONFIG         (IRS1125_CID_CUSTOM_BASE + 7)\n+#define IRS1125_CID_IDENT0             (IRS1125_CID_CUSTOM_BASE + 8)\n+#define IRS1125_CID_IDENT1             (IRS1125_CID_CUSTOM_BASE + 9)\n+#define IRS1125_CID_IDENT2             (IRS1125_CID_CUSTOM_BASE + 10)\n+\n+struct irs1125_seq_cfg {\n+\t__u16 exposure;\n+\t__u16 framerate;\n+\t__u16 ps;\n+\t__u16 pll;\n+};\n+\n+struct irs1125_illu {\n+\t__u16 exposure;\n+\t__u16 framerate;\n+};\n+\n+struct irs1125_mod_pll {\n+\t__u16 pllcfg1;\n+\t__u16 pllcfg2;\n+\t__u16 pllcfg3;\n+\t__u16 pllcfg4;\n+\t__u16 pllcfg5;\n+\t__u16 pllcfg6;\n+\t__u16 pllcfg7;\n+\t__u16 pllcfg8;\n+};\n+\n+#endif /* IRS1125 */\n+\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0167-drm-v3d-Don-t-clear-MMU-control-bits-on-exception.patch",
    "content": "From 7372f1f8c151f752aa533eaf2b85ad9b21ec9639 Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.org>\nDate: Mon, 11 Nov 2019 14:01:41 +0000\nSubject: [PATCH] drm/v3d: Don't clear MMU control bits on exception\n\nMMU exception conditions are reported in the V3D_MMU_CTRL register as\nwrite-1-to-clear (W1C) bits. The MMU interrupt handling code clears any\nexceptions, but does so by masking out any other bits and writing the\nresult back. There are some important control bits in that register,\nincluding MMU_ENABLE, so a safer approach is to simply write back the\nvalue just read unaltered.\n\nThis patch doesn't remove the cause of the apparent PTE errors, but it\ndoes reduce the impact to just an error in the kernel log.\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.org>\n---\n drivers/gpu/drm/v3d/v3d_irq.c | 5 +----\n 1 file changed, 1 insertion(+), 4 deletions(-)\n\n--- a/drivers/gpu/drm/v3d/v3d_irq.c\n+++ b/drivers/gpu/drm/v3d/v3d_irq.c\n@@ -178,10 +178,7 @@ v3d_hub_irq(int irq, void *arg)\n \t\t};\n \t\tconst char *client = \"?\";\n \n-\t\tV3D_WRITE(V3D_MMU_CTL,\n-\t\t\t  V3D_READ(V3D_MMU_CTL) & (V3D_MMU_CTL_CAP_EXCEEDED |\n-\t\t\t\t\t\t   V3D_MMU_CTL_PT_INVALID |\n-\t\t\t\t\t\t   V3D_MMU_CTL_WRITE_VIOLATION));\n+\t\tV3D_WRITE(V3D_MMU_CTL, V3D_READ(V3D_MMU_CTL));\n \n \t\tif (v3d->ver >= 41) {\n \t\t\taxi_id = axi_id >> 5;\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0168-drm-v3d-Suppress-all-but-the-first-MMU-error.patch",
    "content": "From e5d63db582ac8f702e6647c47e118c7e1b2412a3 Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.org>\nDate: Mon, 11 Nov 2019 20:18:08 +0000\nSubject: [PATCH] drm/v3d: Suppress all but the first MMU error\n\nThe v3d driver currently encounters a lot of MMU PTE exceptions, so\nonly log the first to avoid swamping the kernel log.\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.org>\n---\n drivers/gpu/drm/v3d/v3d_irq.c | 3 +++\n 1 file changed, 3 insertions(+)\n\n--- a/drivers/gpu/drm/v3d/v3d_irq.c\n+++ b/drivers/gpu/drm/v3d/v3d_irq.c\n@@ -177,6 +177,7 @@ v3d_hub_irq(int irq, void *arg)\n \t\t\t\"GMP\",\n \t\t};\n \t\tconst char *client = \"?\";\n+\t\tstatic int logged_error;\n \n \t\tV3D_WRITE(V3D_MMU_CTL, V3D_READ(V3D_MMU_CTL));\n \n@@ -186,6 +187,7 @@ v3d_hub_irq(int irq, void *arg)\n \t\t\t\tclient = v3d41_axi_ids[axi_id];\n \t\t}\n \n+\t\tif (!logged_error)\n \t\tdev_err(v3d->drm.dev, \"MMU error from client %s (%d) at 0x%llx%s%s%s\\n\",\n \t\t\tclient, axi_id, (long long)vio_addr,\n \t\t\t((intsts & V3D_HUB_INT_MMU_WRV) ?\n@@ -194,6 +196,7 @@ v3d_hub_irq(int irq, void *arg)\n \t\t\t \", pte invalid\" : \"\"),\n \t\t\t((intsts & V3D_HUB_INT_MMU_CAP) ?\n \t\t\t \", cap exceeded\" : \"\"));\n+\t\tlogged_error = 1;\n \t\tstatus = IRQ_HANDLED;\n \t}\n \n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0169-drm-v3d-Plug-dma_fence-leak.patch",
    "content": "From 6ae6a3a41d658321aee47577d88cbbbef3ea6b78 Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.org>\nDate: Tue, 12 Nov 2019 16:41:21 +0000\nSubject: [PATCH] drm/v3d: Plug dma_fence leak\n\nThe irq_fence and done_fence are given a reference that is never\nreleased. The necessary dma_fence_put()s seem to have been\ndeleted in error in an earlier commit.\n\nFixes: 0b73676836b2 (\"drm/v3d: Clock V3D down when not in use.\")\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.org>\n---\n drivers/gpu/drm/v3d/v3d_gem.c | 3 +++\n 1 file changed, 3 insertions(+)\n\n--- a/drivers/gpu/drm/v3d/v3d_gem.c\n+++ b/drivers/gpu/drm/v3d/v3d_gem.c\n@@ -410,6 +410,9 @@ v3d_job_free(struct kref *ref)\n \t}\n \txa_destroy(&job->deps);\n \n+\tdma_fence_put(job->irq_fence);\n+\tdma_fence_put(job->done_fence);\n+\n \tv3d_clock_up_put(v3d);\n \n \tkfree(job);\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0170-staging-vchiq_arm-Register-vcsm-cma-as-a-platform-dr.patch",
    "content": "From 9999a14d45012bce466bd52449c3dcbeb1736367 Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Wed, 6 Nov 2019 13:57:48 +0000\nSubject: [PATCH] staging: vchiq_arm: Register vcsm-cma as a platform\n driver\n\nFollowing the same pattern as bcm2835-camera and bcm2835-audio,\nregister the vcsm-cma driver as a platform driver\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n drivers/staging/vc04_services/interface/vchiq_arm/vchiq_arm.c | 3 +++\n 1 file changed, 3 insertions(+)\n\n--- a/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_arm.c\n+++ b/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_arm.c\n@@ -109,6 +109,7 @@ static struct class  *vchiq_class;\n static DEFINE_SPINLOCK(msg_queue_spinlock);\n static struct platform_device *bcm2835_camera;\n static struct platform_device *bcm2835_audio;\n+static struct platform_device *vcsm_cma;\n \n static struct vchiq_drvdata bcm2835_drvdata = {\n \t.cache_line_size = 32,\n@@ -2765,6 +2766,7 @@ static int vchiq_probe(struct platform_d\n \t\tVCHIQ_VERSION, VCHIQ_VERSION_MIN,\n \t\tMAJOR(vchiq_devid), MINOR(vchiq_devid));\n \n+\tvcsm_cma = vchiq_register_child(pdev, \"vcsm-cma\");\n \tbcm2835_camera = vchiq_register_child(pdev, \"bcm2835-camera\");\n \tbcm2835_audio = vchiq_register_child(pdev, \"bcm2835_audio\");\n \n@@ -2781,6 +2783,7 @@ static int vchiq_remove(struct platform_\n {\n \tplatform_device_unregister(bcm2835_audio);\n \tplatform_device_unregister(bcm2835_camera);\n+\tplatform_device_unregister(vcsm_cma);\n \tvchiq_debugfs_deinit();\n \tdevice_destroy(vchiq_class, vchiq_devid);\n \tcdev_del(&vchiq_cdev);\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0171-staging-vchiq_arm-Register-bcm2835-codec-as-a-platfo.patch",
    "content": "From 49d23a9d1982010b7b677f3f5c78ffbf46e39d85 Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Wed, 6 Nov 2019 13:57:58 +0000\nSubject: [PATCH] staging: vchiq_arm: Register bcm2835-codec as a\n platform driver\n\nFollowing the same pattern as bcm2835-camera and bcm2835-audio,\nregister the V4L2 codec driver as a platform driver\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n drivers/staging/vc04_services/interface/vchiq_arm/vchiq_arm.c | 3 +++\n 1 file changed, 3 insertions(+)\n\n--- a/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_arm.c\n+++ b/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_arm.c\n@@ -109,6 +109,7 @@ static struct class  *vchiq_class;\n static DEFINE_SPINLOCK(msg_queue_spinlock);\n static struct platform_device *bcm2835_camera;\n static struct platform_device *bcm2835_audio;\n+static struct platform_device *bcm2835_codec;\n static struct platform_device *vcsm_cma;\n \n static struct vchiq_drvdata bcm2835_drvdata = {\n@@ -2767,6 +2768,7 @@ static int vchiq_probe(struct platform_d\n \t\tMAJOR(vchiq_devid), MINOR(vchiq_devid));\n \n \tvcsm_cma = vchiq_register_child(pdev, \"vcsm-cma\");\n+\tbcm2835_codec = vchiq_register_child(pdev, \"bcm2835-codec\");\n \tbcm2835_camera = vchiq_register_child(pdev, \"bcm2835-camera\");\n \tbcm2835_audio = vchiq_register_child(pdev, \"bcm2835_audio\");\n \n@@ -2783,6 +2785,7 @@ static int vchiq_remove(struct platform_\n {\n \tplatform_device_unregister(bcm2835_audio);\n \tplatform_device_unregister(bcm2835_camera);\n+\tplatform_device_unregister(bcm2835_codec);\n \tplatform_device_unregister(vcsm_cma);\n \tvchiq_debugfs_deinit();\n \tdevice_destroy(vchiq_class, vchiq_devid);\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0172-net-bcmgenet-The-second-IRQ-is-optional.patch",
    "content": "From 7f729e862d5d0f6605874393af075a6aa8e98bd5 Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.org>\nDate: Thu, 14 Nov 2019 11:59:01 +0000\nSubject: [PATCH] net: bcmgenet: The second IRQ is optional\n\nAs of 5.4, the kernel logs errors for absent IRQs unless requested\nwith platform_get_irq_optional.\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.org>\n---\n drivers/gpu/drm/v3d/v3d_irq.c | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/drivers/gpu/drm/v3d/v3d_irq.c\n+++ b/drivers/gpu/drm/v3d/v3d_irq.c\n@@ -217,7 +217,7 @@ v3d_irq_init(struct v3d_dev *v3d)\n \t\tV3D_CORE_WRITE(core, V3D_CTL_INT_CLR, V3D_CORE_IRQS);\n \tV3D_WRITE(V3D_HUB_INT_CLR, V3D_HUB_IRQS);\n \n-\tirq1 = platform_get_irq(v3d_to_pdev(v3d), 1);\n+\tirq1 = platform_get_irq_optional(v3d_to_pdev(v3d), 1);\n \tif (irq1 == -EPROBE_DEFER)\n \t\treturn irq1;\n \tif (irq1 > 0) {\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0173-net-phy-2711-Allow-ethernet-LED-mode-to-be-set-via-d.patch",
    "content": "From 3ab0c4b6aa76a4dedb51c4e800b5b4ba29187c46 Mon Sep 17 00:00:00 2001\nFrom: James Hughes <james.hughes@raspberrypi.org>\nDate: Thu, 31 Oct 2019 14:39:44 +0000\nSubject: [PATCH] net:phy:2711 Allow ethernet LED mode to be set via\n device tree\n\nAdd device tree entries and code to allow the specification of\nthe lighting modes for the LED's on the ethernet connector.\n\nSigned-off-by: James Hughes <james.hughes@raspberrypi.org>\n---\n drivers/net/phy/broadcom.c | 9 +++++++--\n 1 file changed, 7 insertions(+), 2 deletions(-)\n\n--- a/drivers/net/phy/broadcom.c\n+++ b/drivers/net/phy/broadcom.c\n@@ -314,6 +314,9 @@ static void bcm54xx_adjust_rxrefclk(stru\n static int bcm54xx_config_init(struct phy_device *phydev)\n {\n \tint reg, err, val;\n+\tu32 led_modes[] = {BCM_LED_MULTICOLOR_LINK_ACT,\n+\t\t\t   BCM_LED_MULTICOLOR_LINK_ACT};\n+\tstruct device_node *np = phydev->mdio.dev.of_node;\n \n \treg = phy_read(phydev, MII_BCM54XX_ECR);\n \tif (reg < 0)\n@@ -369,6 +372,8 @@ static int bcm54xx_config_init(struct ph\n \n \tbcm54xx_phydsp_config(phydev);\n \n+\tof_property_read_u32_array(np, \"led-modes\", led_modes, 2);\n+\n \t/* Encode link speed into LED1 and LED3 pair (green/amber).\n \t * Also flash these two LEDs on activity. This means configuring\n \t * them for MULTICOLOR and encoding link/activity into them.\n@@ -378,8 +383,8 @@ static int bcm54xx_config_init(struct ph\n \tbcm_phy_write_shadow(phydev, BCM5482_SHD_LEDS1, val);\n \n \tval = BCM_LED_MULTICOLOR_IN_PHASE |\n-\t\tBCM5482_SHD_LEDS1_LED1(BCM_LED_MULTICOLOR_LINK_ACT) |\n-\t\tBCM5482_SHD_LEDS1_LED3(BCM_LED_MULTICOLOR_LINK_ACT);\n+\t\tBCM5482_SHD_LEDS1_LED1(led_modes[0]) |\n+\t\tBCM5482_SHD_LEDS1_LED3(led_modes[1]);\n \tbcm_phy_write_exp(phydev, BCM_EXP_MULTICOLOR, val);\n \n \treturn 0;\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0174-net-phy-2711-Change-the-default-ethernet-LED-actions.patch",
    "content": "From 0534ec9429d41d9a00851444498f11b222d350b8 Mon Sep 17 00:00:00 2001\nFrom: James Hughes <james.hughes@raspberrypi.org>\nDate: Thu, 7 Nov 2019 14:59:59 +0000\nSubject: [PATCH] net:phy:2711 Change the default ethernet LED actions\n\nThis should return default behaviour back to that of previous\nreleases.\n---\n drivers/net/phy/broadcom.c | 6 +-----\n 1 file changed, 1 insertion(+), 5 deletions(-)\n\n--- a/drivers/net/phy/broadcom.c\n+++ b/drivers/net/phy/broadcom.c\n@@ -315,7 +315,7 @@ static int bcm54xx_config_init(struct ph\n {\n \tint reg, err, val;\n \tu32 led_modes[] = {BCM_LED_MULTICOLOR_LINK_ACT,\n-\t\t\t   BCM_LED_MULTICOLOR_LINK_ACT};\n+\t\t\t   BCM_LED_MULTICOLOR_LINK};\n \tstruct device_node *np = phydev->mdio.dev.of_node;\n \n \treg = phy_read(phydev, MII_BCM54XX_ECR);\n@@ -374,10 +374,6 @@ static int bcm54xx_config_init(struct ph\n \n \tof_property_read_u32_array(np, \"led-modes\", led_modes, 2);\n \n-\t/* Encode link speed into LED1 and LED3 pair (green/amber).\n-\t * Also flash these two LEDs on activity. This means configuring\n-\t * them for MULTICOLOR and encoding link/activity into them.\n-\t */\n \tval = BCM5482_SHD_LEDS1_LED1(BCM_LED_SRC_MULTICOLOR1) |\n \t\tBCM5482_SHD_LEDS1_LED3(BCM_LED_SRC_MULTICOLOR1);\n \tbcm_phy_write_shadow(phydev, BCM5482_SHD_LEDS1, val);\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0175-v3d_drv-Handle-missing-clock-more-gracefully.patch",
    "content": "From d26aa66c1e5b8c31547315d5421a83f0dd1eeef5 Mon Sep 17 00:00:00 2001\nFrom: popcornmix <popcornmix@gmail.com>\nDate: Fri, 23 Aug 2019 16:34:38 +0100\nSubject: [PATCH] v3d_drv: Handle missing clock more gracefully\n\nSigned-off-by: popcornmix <popcornmix@gmail.com>\n---\n drivers/gpu/drm/v3d/v3d_drv.c | 8 ++++----\n 1 file changed, 4 insertions(+), 4 deletions(-)\n\n--- a/drivers/gpu/drm/v3d/v3d_drv.c\n+++ b/drivers/gpu/drm/v3d/v3d_drv.c\n@@ -290,10 +290,10 @@ static int v3d_platform_drm_probe(struct\n \t}\n \n \tv3d->clk = devm_clk_get(dev, NULL);\n-\tif (IS_ERR(v3d->clk)) {\n-\t\tif (ret != -EPROBE_DEFER)\n-\t\t\tdev_err(dev, \"Failed to get clock\\n\");\n-\t\tgoto dev_free;\n+\tif (IS_ERR_OR_NULL(v3d->clk)) {\n+\t\tif (PTR_ERR(v3d->clk) != -EPROBE_DEFER)\n+\t\t\tdev_err(dev, \"Failed to get clock (%ld)\\n\", PTR_ERR(v3d->clk));\n+\t\treturn PTR_ERR(v3d->clk);\n \t}\n \tv3d->clk_up_rate = clk_get_rate(v3d->clk);\n \t/* For downclocking, drop it to the minimum frequency we can get from\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0176-v3d_gem-Kick-the-clock-so-firmware-knows-we-are-usin.patch",
    "content": "From a29ca7c68f90f9e59e7bca36b52c738faf7851ad Mon Sep 17 00:00:00 2001\nFrom: popcornmix <popcornmix@gmail.com>\nDate: Thu, 5 Sep 2019 17:59:14 +0100\nSubject: [PATCH] v3d_gem: Kick the clock so firmware knows we are\n using firmware clock interface\n\nSetting the v3d clock to low value allows firmware to handle dvfs in case\nwhere v3d hardware is not being actively used (e.g. console use).\n\nSigned-off-by: popcornmix <popcornmix@gmail.com>\n---\n drivers/gpu/drm/v3d/v3d_gem.c | 4 ++++\n 1 file changed, 4 insertions(+)\n\n--- a/drivers/gpu/drm/v3d/v3d_gem.c\n+++ b/drivers/gpu/drm/v3d/v3d_gem.c\n@@ -920,6 +920,10 @@ v3d_gem_init(struct drm_device *dev)\n \tmutex_init(&v3d->clk_lock);\n \tINIT_DELAYED_WORK(&v3d->clk_down_work, v3d_clock_down_work);\n \n+\t/* kick the clock so firmware knows we are using firmware clock interface */\n+\tv3d_clock_up_get(v3d);\n+\tv3d_clock_up_put(v3d);\n+\n \t/* Note: We don't allocate address 0.  Various bits of HW\n \t * treat 0 as special, such as the occlusion query counters\n \t * where 0 means \"disabled\".\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0177-clk-raspberrypi-Allow-cpufreq-driver-to-also-adjust-.patch",
    "content": "From 9111e23e3749f49ec35e062c3c7e9a46ebbd8642 Mon Sep 17 00:00:00 2001\nFrom: popcornmix <popcornmix@gmail.com>\nDate: Mon, 9 Sep 2019 15:49:56 +0100\nSubject: [PATCH] clk-raspberrypi: Allow cpufreq driver to also adjust\n gpu clocks\n\nFor performance/power it is beneficial to adjust gpu clocks with arm clock.\nThis is how the downstream cpufreq driver works\n\nSigned-off-by: popcornmix <popcornmix@gmail.com>\n---\n drivers/clk/bcm/clk-raspberrypi.c | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/drivers/clk/bcm/clk-raspberrypi.c\n+++ b/drivers/clk/bcm/clk-raspberrypi.c\n@@ -97,7 +97,7 @@ static int raspberrypi_clock_property(st\n \tstruct raspberrypi_firmware_prop msg = {\n \t\t.id = cpu_to_le32(data->id),\n \t\t.val = cpu_to_le32(*val),\n-\t\t.disable_turbo = cpu_to_le32(1),\n+\t\t.disable_turbo = cpu_to_le32(0),\n \t};\n \tint ret;\n \n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0178-clk-bcm2835-Disable-v3d-clock.patch",
    "content": "From dcfed6cdcd38f9b0ca706af74710969aa8082c38 Mon Sep 17 00:00:00 2001\nFrom: popcornmix <popcornmix@gmail.com>\nDate: Tue, 3 Sep 2019 20:28:00 +0100\nSubject: [PATCH] clk-bcm2835: Disable v3d clock\n\nThis is controlled by firmware, see clk-raspberrypi.c\n\nSigned-off-by: popcornmix <popcornmix@gmail.com>\n---\n drivers/clk/bcm/clk-bcm2835.c | 30 ++++++++++++------------------\n 1 file changed, 12 insertions(+), 18 deletions(-)\n\n--- a/drivers/clk/bcm/clk-bcm2835.c\n+++ b/drivers/clk/bcm/clk-bcm2835.c\n@@ -1736,16 +1736,12 @@ static const struct bcm2835_clk_desc clk\n \t\t.hold_mask = CM_PLLA_HOLDCORE,\n \t\t.fixed_divider = 1,\n \t\t.flags = CLK_SET_RATE_PARENT),\n-\t[BCM2835_PLLA_PER]\t= REGISTER_PLL_DIV(\n-\t\tSOC_ALL,\n-\t\t.name = \"plla_per\",\n-\t\t.source_pll = \"plla\",\n-\t\t.cm_reg = CM_PLLA,\n-\t\t.a2w_reg = A2W_PLLA_PER,\n-\t\t.load_mask = CM_PLLA_LOADPER,\n-\t\t.hold_mask = CM_PLLA_HOLDPER,\n-\t\t.fixed_divider = 1,\n-\t\t.flags = CLK_SET_RATE_PARENT),\n+\n+\t/*\n+\t * PLLA_PER is used for gpu clocks. Controlled by firmware, see\n+\t * clk-raspberrypi.c.\n+\t */\n+\n \t[BCM2835_PLLA_DSI0]\t= REGISTER_PLL_DIV(\n \t\tSOC_ALL,\n \t\t.name = \"plla_dsi0\",\n@@ -2046,14 +2042,12 @@ static const struct bcm2835_clk_desc clk\n \t\t.int_bits = 6,\n \t\t.frac_bits = 0,\n \t\t.tcnt_mux = 3),\n-\t[BCM2835_CLOCK_V3D]\t= REGISTER_VPU_CLK(\n-\t\tSOC_ALL,\n-\t\t.name = \"v3d\",\n-\t\t.ctl_reg = CM_V3DCTL,\n-\t\t.div_reg = CM_V3DDIV,\n-\t\t.int_bits = 4,\n-\t\t.frac_bits = 8,\n-\t\t.tcnt_mux = 4),\n+\n+\t/*\n+\t * CLOCK_V3D is used for v3d clock. Controlled by firmware, see\n+\t * clk-raspberrypi.c.\n+\t */\n+\n \t/*\n \t * VPU clock.  This doesn't have an enable bit, since it drives\n \t * the bus for everything else, and is special so it doesn't need\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0179-drm-v3d-Set-dma_mask-as-well-as-coherent_dma_mask.patch",
    "content": "From 0a34bafa5816dd1425550968ff7d3de2dc955e6f Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.org>\nDate: Fri, 22 Nov 2019 16:23:32 +0000\nSubject: [PATCH] drm/v3d: Set dma_mask as well as coherent_dma_mask\n\nBoth coherent_dma_mask and dma_mask act as constraints on allocations\nand bounce buffer usage, so be sure to set dma_mask to the appropriate\nvalue otherwise the effective mask could be incorrect.\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.org>\n---\n drivers/gpu/drm/v3d/v3d_drv.c | 4 ++--\n 1 file changed, 2 insertions(+), 2 deletions(-)\n\n--- a/drivers/gpu/drm/v3d/v3d_drv.c\n+++ b/drivers/gpu/drm/v3d/v3d_drv.c\n@@ -263,8 +263,8 @@ static int v3d_platform_drm_probe(struct\n \t\treturn ret;\n \n \tmmu_debug = V3D_READ(V3D_MMU_DEBUG_INFO);\n-\tdev->coherent_dma_mask =\n-\t\tDMA_BIT_MASK(30 + V3D_GET_FIELD(mmu_debug, V3D_MMU_PA_WIDTH));\n+\tdma_set_mask_and_coherent(dev,\n+\t\tDMA_BIT_MASK(30 + V3D_GET_FIELD(mmu_debug, V3D_MMU_PA_WIDTH)));\n \tv3d->va_width = 30 + V3D_GET_FIELD(mmu_debug, V3D_MMU_VA_WIDTH);\n \n \tident1 = V3D_READ(V3D_HUB_IDENT1);\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0180-staging-vchiq_arm-Set-up-dma-ranges-on-child-devices.patch",
    "content": "From f18a78bd6232ebe254486740eb5f9bbdc4650879 Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.org>\nDate: Tue, 29 Jan 2019 16:13:25 +0000\nSubject: [PATCH] staging: vchiq_arm: Set up dma ranges on child\n devices\n\nThe VCHIQ driver now loads the audio, camera, codec, and vc-sm\ndrivers as platform drivers. However they were not being given\nthe correct DMA configuration.\n\nCall of_dma_configure with the parent (VCHIQ) parameters to be\ninherited by the child.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>\n---\n .../staging/vc04_services/interface/vchiq_arm/vchiq_arm.c   | 6 ++++++\n 1 file changed, 6 insertions(+)\n\n--- a/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_arm.c\n+++ b/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_arm.c\n@@ -2710,6 +2710,12 @@ vchiq_register_child(struct platform_dev\n \t\tchild = NULL;\n \t}\n \n+\t/*\n+\t * We want the dma-ranges etc to be copied from the parent VCHIQ device\n+\t * to be passed on to the children too.\n+\t */\n+\tof_dma_configure(&new_dev->dev, pdev->dev.of_node, true);\n+\n \treturn child;\n }\n \n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0181-staging-vchiq-Use-the-old-dma-controller-for-OF-conf.patch",
    "content": "From d7dbf1141d107ba6df15b04498e5fb88b6b61912 Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.org>\nDate: Tue, 18 Jun 2019 12:15:50 +0100\nSubject: [PATCH] staging: vchiq: Use the old dma controller for OF\n config on platform devices\n\nvchiq on Pi4 is no longer under the soc node, therefore it\ndoesn't get the dma-ranges for the VPU.\n\nSwitch to using the configuration of the old dma controller as\nthat will set the dma-ranges correctly.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>\n---\n .../interface/vchiq_arm/vchiq_arm.c             | 17 ++++++++++++++---\n 1 file changed, 14 insertions(+), 3 deletions(-)\n\n--- a/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_arm.c\n+++ b/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_arm.c\n@@ -2696,6 +2696,7 @@ vchiq_register_child(struct platform_dev\n {\n \tstruct platform_device_info pdevinfo;\n \tstruct platform_device *child;\n+\tstruct device_node *np;\n \n \tmemset(&pdevinfo, 0, sizeof(pdevinfo));\n \n@@ -2711,10 +2712,20 @@ vchiq_register_child(struct platform_dev\n \t}\n \n \t/*\n-\t * We want the dma-ranges etc to be copied from the parent VCHIQ device\n-\t * to be passed on to the children too.\n+\t * We want the dma-ranges etc to be copied from a device with the\n+\t * correct dma-ranges for the VPU.\n+\t * VCHIQ on Pi4 is now under scb which doesn't get those dma-ranges.\n+\t * Take the \"dma\" node as going to be suitable as it sees the world\n+\t * through the same eyes as the VPU.\n \t */\n-\tof_dma_configure(&new_dev->dev, pdev->dev.of_node, true);\n+\tnp = of_find_node_by_path(\"dma\");\n+\tif (!np)\n+\t\tnp = pdev->dev.of_node;\n+\n+\tof_dma_configure(&child->dev, np, true);\n+\n+\tif (np != pdev->dev.of_node)\n+\t\tof_node_put(np);\n \n \treturn child;\n }\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0182-ARM-bcm-Backport-BCM2711-support-from-upstream.patch",
    "content": "From 20534fd2fedd5c3febd239475e64d3dfc7d8400b Mon Sep 17 00:00:00 2001\nFrom: Stefan Wahren <wahrenst@gmx.net>\nDate: Fri, 27 Dec 2019 11:40:56 +0100\nSubject: [PATCH] ARM: bcm: Backport BCM2711 support from upstream\n\nMake the BCM2711 a different machine, but keep it in board_bcm2835.\n\nSigned-off-by: Stefan Wahren <wahrenst@gmx.net>\n---\n arch/arm/mach-bcm/board_bcm2835.c | 17 +++++++++++++++--\n 1 file changed, 15 insertions(+), 2 deletions(-)\n\n--- a/arch/arm/mach-bcm/board_bcm2835.c\n+++ b/arch/arm/mach-bcm/board_bcm2835.c\n@@ -109,17 +109,30 @@ static const char * const bcm2835_compat\n #ifdef CONFIG_ARCH_MULTI_V7\n \t\"brcm,bcm2836\",\n \t\"brcm,bcm2837\",\n-\t\"brcm,bcm2711\",\n #endif\n \tNULL\n };\n \n DT_MACHINE_START(BCM2835, \"BCM2835\")\n+\t.map_io = bcm2835_map_io,\n+\t.init_machine = bcm2835_init,\n+\t.dt_compat = bcm2835_compat,\n+\t.smp = smp_ops(bcm2836_smp_ops),\n+MACHINE_END\n+\n+static const char * const bcm2711_compat[] = {\n+#ifdef CONFIG_ARCH_MULTI_V7\n+\t\"brcm,bcm2711\",\n+#endif\n+\tNULL\n+};\n+\n+DT_MACHINE_START(BCM2711, \"BCM2711\")\n #if defined(CONFIG_ZONE_DMA) && defined(CONFIG_ARM_LPAE)\n \t.dma_zone_size\t= SZ_1G,\n #endif\n \t.map_io = bcm2835_map_io,\n \t.init_machine = bcm2835_init,\n-\t.dt_compat = bcm2835_compat,\n+\t.dt_compat = bcm2711_compat,\n \t.smp = smp_ops(bcm2836_smp_ops),\n MACHINE_END\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0183-Initialise-rpi-firmware-before-clk-bcm2835.patch",
    "content": "From a4dd91006d4fdbd5c0f32e48eb7babc98ebc37f2 Mon Sep 17 00:00:00 2001\nFrom: Luke Hinds <7058938+lukehinds@users.noreply.github.com>\nDate: Wed, 22 Jan 2020 16:03:00 +0000\nSubject: [PATCH] Initialise rpi-firmware before clk-bcm2835\n\nThe IMA (Integrity Measurement Architecture) looks for a TPM (Trusted\nPlatform Module) having been registered when it initialises; otherwise\nit assumes there is no TPM. It has been observed on BCM2835 that IMA\nis initialised before TPM, and that initialising the BCM2835 clock\ndriver before the firmware driver has the effect of reversing this\norder.\n\nChange the firmware driver to initialise at core_initcall, delaying the\nBCM2835 clock driver to postcore_initcall.\n\nSee: https://github.com/raspberrypi/linux/issues/3291\n     https://github.com/raspberrypi/linux/pull/3297\n\nSigned-off-by: Luke Hinds <lhinds@redhat.com>\nCo-authored-by: Phil Elwell <phil@raspberrypi.org>\n---\n drivers/clk/bcm/clk-bcm2835.c  | 2 +-\n drivers/firmware/raspberrypi.c | 2 +-\n 2 files changed, 2 insertions(+), 2 deletions(-)\n\n--- a/drivers/clk/bcm/clk-bcm2835.c\n+++ b/drivers/clk/bcm/clk-bcm2835.c\n@@ -2424,7 +2424,7 @@ static int __init __bcm2835_clk_driver_i\n {\n \treturn platform_driver_register(&bcm2835_clk_driver);\n }\n-core_initcall(__bcm2835_clk_driver_init);\n+postcore_initcall(__bcm2835_clk_driver_init);\n \n MODULE_AUTHOR(\"Eric Anholt <eric@anholt.net>\");\n MODULE_DESCRIPTION(\"BCM2835 clock driver\");\n--- a/drivers/firmware/raspberrypi.c\n+++ b/drivers/firmware/raspberrypi.c\n@@ -468,7 +468,7 @@ out2:\n out1:\n \treturn ret;\n }\n-subsys_initcall(rpi_firmware_init);\n+core_initcall(rpi_firmware_init);\n \n static void __init rpi_firmware_exit(void)\n {\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0184-staging-vchiq_arm-Give-vchiq-children-DT-nodes.patch",
    "content": "From 3e21610821310bfc015bbc8494e0e1f357e5a49e Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.com>\nDate: Mon, 3 Feb 2020 17:30:46 +0000\nSubject: [PATCH] staging: vchiq_arm: Give vchiq children DT nodes\n\nvchiq kernel clients are now instantiated as platform drivers rather\nthan using DT, but the children of the vchiq interface may still\nbenefit from access to DT properties. Give them the option of a\na sub-node of the vchiq parent for configuration and to allow\nthem to be disabled.\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.com>\n---\n .../staging/vc04_services/interface/vchiq_arm/vchiq_arm.c | 8 ++++++++\n 1 file changed, 8 insertions(+)\n\n--- a/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_arm.c\n+++ b/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_arm.c\n@@ -2705,12 +2705,20 @@ vchiq_register_child(struct platform_dev\n \tpdevinfo.id = PLATFORM_DEVID_NONE;\n \tpdevinfo.dma_mask = DMA_BIT_MASK(32);\n \n+\tnp = of_get_child_by_name(pdev->dev.of_node, name);\n+\n+\t/* Skip the child if it is explicitly disabled */\n+\tif (np && !of_device_is_available(np))\n+\t\treturn NULL;\n+\n \tchild = platform_device_register_full(&pdevinfo);\n \tif (IS_ERR(child)) {\n \t\tdev_warn(&pdev->dev, \"%s not registered\\n\", name);\n \t\tchild = NULL;\n \t}\n \n+\tchild->dev.of_node = np;\n+\n \t/*\n \t * We want the dma-ranges etc to be copied from a device with the\n \t * correct dma-ranges for the VPU.\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0185-pinctrl-bcm2835-Remove-gpiochip-on-error.patch",
    "content": "From 0da3ef334d4949431f34fea9f315d967e47a6a73 Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.org>\nDate: Mon, 6 Jan 2020 16:04:30 +0000\nSubject: [PATCH] pinctrl: bcm2835: Remove gpiochip on error\n\nA failure in gpiochip_irqchip_add leads to a leak of a gpiochip. Fix\nthe leak with the use of devm_gpiochip_add_data.\n\nFixes: 85ae9e512f43 (\"pinctrl: bcm2835: switch to GPIOLIB_IRQCHIP\")\nSigned-off-by: Phil Elwell <phil@raspberrypi.org>\n---\n drivers/pinctrl/bcm/pinctrl-bcm2835.c | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/drivers/pinctrl/bcm/pinctrl-bcm2835.c\n+++ b/drivers/pinctrl/bcm/pinctrl-bcm2835.c\n@@ -1318,7 +1318,7 @@ static int bcm2835_pinctrl_probe(struct\n \tgirq->default_type = IRQ_TYPE_NONE;\n \tgirq->handler = handle_level_irq;\n \n-\terr = gpiochip_add_data(&pc->gpio_chip, pc);\n+\terr = devm_gpiochip_add_data(dev, &pc->gpio_chip, pc);\n \tif (err) {\n \t\tdev_err(dev, \"could not add GPIO chip\\n\");\n \t\tgoto out_remove;\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0187-pinctrl-bcm2835-Accept-fewer-than-expected-IRQs.patch",
    "content": "From 9ab71458b5475c7d8d42896721e593f6ef1a5c7a Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.com>\nDate: Tue, 25 Feb 2020 17:38:20 +0000\nSubject: [PATCH] pinctrl: bcm2835: Accept fewer than expected IRQs\n\nThe downstream .dts files only request two GPIO IRQs. Truncate the\narray of parent IRQs when irq_of_parse_and_map returns 0.\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.com>\n---\n drivers/pinctrl/bcm/pinctrl-bcm2835.c | 8 ++++++--\n 1 file changed, 6 insertions(+), 2 deletions(-)\n\n--- a/drivers/pinctrl/bcm/pinctrl-bcm2835.c\n+++ b/drivers/pinctrl/bcm/pinctrl-bcm2835.c\n@@ -1290,9 +1290,13 @@ static int bcm2835_pinctrl_probe(struct\n \t\tchar *name;\n \n \t\tgirq->parents[i] = irq_of_parse_and_map(np, i);\n-\t\tif (!is_7211)\n+\t\tif (!is_7211) {\n+\t\t\tif (!girq->parents[i]) {\n+\t\t\t\tgirq->num_parents = i;\n+\t\t\t\tbreak;\n+\t\t\t}\n \t\t\tcontinue;\n-\n+\t\t}\n \t\t/* Skip over the all banks interrupts */\n \t\tpc->wake_irq[i] = irq_of_parse_and_map(np, i +\n \t\t\t\t\t\t       BCM2835_NUM_IRQS + 1);\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0188-drivers-char-vcio-Use-common-compat-header.patch",
    "content": "From b1c80253689fe3d451d08ec707907b2dca61ddc3 Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.com>\nDate: Mon, 2 Mar 2020 14:40:19 +0000\nSubject: [PATCH] drivers: char: vcio: Use common compat header\n\nThe definition of compat_ptr is now common for most platforms, but\nrequires the inclusion of <linux/compat.h>.\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.com>\n---\n drivers/char/broadcom/vcio.c | 1 +\n 1 file changed, 1 insertion(+)\n\n--- a/drivers/char/broadcom/vcio.c\n+++ b/drivers/char/broadcom/vcio.c\n@@ -18,6 +18,7 @@\n #include <linux/module.h>\n #include <linux/slab.h>\n #include <linux/uaccess.h>\n+#include <linux/compat.h>\n #include <soc/bcm2835/raspberrypi-firmware.h>\n \n #define MBOX_CHAN_PROPERTY 8\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0189-video-fbdev-bcm2708_fb-Use-common-compat-header.patch",
    "content": "From 6dd897b34471d95f9c01d19df06c339fe6fbf38c Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.com>\nDate: Mon, 2 Mar 2020 14:42:23 +0000\nSubject: [PATCH] video: fbdev: bcm2708_fb: Use common compat header\n\nThe definition of compat_ptr is now common for most platforms, but\nrequires the inclusion of <linux/compat.h>.\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.com>\n---\n drivers/video/fbdev/bcm2708_fb.c | 1 +\n 1 file changed, 1 insertion(+)\n\n--- a/drivers/video/fbdev/bcm2708_fb.c\n+++ b/drivers/video/fbdev/bcm2708_fb.c\n@@ -38,6 +38,7 @@\n #include <linux/cred.h>\n #include <soc/bcm2835/raspberrypi-firmware.h>\n #include <linux/mutex.h>\n+#include <linux/compat.h>\n \n //#define BCM2708_FB_DEBUG\n #define MODULE_NAME \"bcm2708_fb\"\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0190-of-overlay-Correct-symbol-path-fixups.patch",
    "content": "From 68e9899b2c99dbe97ecf9008e7e43f5b393f26a3 Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.com>\nDate: Thu, 6 Feb 2020 12:23:15 +0000\nSubject: [PATCH] of: overlay: Correct symbol path fixups\n\nWhen symbols from overlays are added to the live tree their paths must\nbe rebased. The translated symbol is normally the result of joining\nthe fragment-relative path (with a leading \"/\") to the target path\n(either copied directly from the \"target-path\" property or resolved\nfrom the phandle). This translation fails when the target is the root\nnode (a common case for Raspberry Pi overlays) because the resulting\npath starts with a double slash. For example, if target-path is \"/\" and\nthe fragment adds a node called \"newnode\", the label associated with\nthat node will be assigned the path \"//newnode\", which can't be found\nin the tree.\n\nFix the failure case by explicitly replacing a target path of \"/\" with\nan empty string.\n\nFixes: d1651b03c2df (\"of: overlay: add overlay symbols to live device tree\")\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.com>\n---\n drivers/of/overlay.c | 2 ++\n 1 file changed, 2 insertions(+)\n\n--- a/drivers/of/overlay.c\n+++ b/drivers/of/overlay.c\n@@ -245,6 +245,8 @@ static struct property *dup_and_fixup_sy\n \tif (!target_path)\n \t\treturn NULL;\n \ttarget_path_len = strlen(target_path);\n+\tif (!strcmp(target_path, \"/\"))\n+\t\ttarget_path_len = 0;\n \n \tnew_prop = kzalloc(sizeof(*new_prop), GFP_KERNEL);\n \tif (!new_prop)\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0191-dt-bindings-pci-Add-DT-docs-for-Brcmstb-PCIe-device.patch",
    "content": "From 4f65cebc14d6af8b4a9f19426b43b3ae49ee8538 Mon Sep 17 00:00:00 2001\nFrom: Jim Quinlan <jim2101024@gmail.com>\nDate: Mon, 15 Jan 2018 18:28:39 -0500\nSubject: [PATCH] dt-bindings: pci: Add DT docs for Brcmstb PCIe device\n\nThe DT bindings description of the Brcmstb PCIe device is described.  This\nnode can be used by almost all Broadcom settop box chips, using\nARM, ARM64, or MIPS CPU architectures.\n\nSigned-off-by: Jim Quinlan <jim2101024@gmail.com>\n---\n .../devicetree/bindings/pci/brcmstb-pcie.txt  | 59 +++++++++++++++++++\n 1 file changed, 59 insertions(+)\n create mode 100644 Documentation/devicetree/bindings/pci/brcmstb-pcie.txt\n\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/pci/brcmstb-pcie.txt\n@@ -0,0 +1,59 @@\n+Brcmstb PCIe Host Controller Device Tree Bindings\n+\n+Required Properties:\n+- compatible\n+  \"brcm,bcm7425-pcie\" -- for 7425 family MIPS-based SOCs.\n+  \"brcm,bcm7435-pcie\" -- for 7435 family MIPS-based SOCs.\n+  \"brcm,bcm7445-pcie\" -- for 7445 and later ARM based SOCs (not including\n+      the 7278).\n+  \"brcm,bcm7278-pcie\"  -- for 7278 family ARM-based SOCs.\n+\n+- reg -- the register start address and length for the PCIe reg block.\n+- interrupts -- two interrupts are specified; the first interrupt is for\n+     the PCI host controller and the second is for MSI if the built-in\n+     MSI controller is to be used.\n+- interrupt-names -- names of the interrupts (above): \"pcie\" and \"msi\".\n+- #address-cells -- set to <3>.\n+- #size-cells -- set to <2>.\n+- #interrupt-cells: set to <1>.\n+- interrupt-map-mask and interrupt-map, standard PCI properties to define the\n+     mapping of the PCIe interface to interrupt numbers.\n+- ranges: ranges for the PCI memory and I/O regions.\n+- linux,pci-domain -- should be unique per host controller.\n+\n+Optional Properties:\n+- clocks -- phandle of pcie clock.\n+- clock-names -- set to \"sw_pcie\" if clocks is used.\n+- dma-ranges -- Specifies the inbound memory mapping regions when\n+     an \"identity map\" is not possible.\n+- msi-controller -- this property is typically specified to have the\n+     PCIe controller use its internal MSI controller.\n+- msi-parent -- set to use an external MSI interrupt controller.\n+- brcm,enable-ssc -- (boolean) indicates usage of spread-spectrum clocking.\n+- max-link-speed --  (integer) indicates desired generation of link:\n+     1 => 2.5 Gbps (gen1), 2 => 5.0 Gbps (gen2), 3 => 8.0 Gbps (gen3).\n+\n+Example Node:\n+\n+pcie0: pcie@f0460000 {\n+\t\treg = <0x0 0xf0460000 0x0 0x9310>;\n+\t\tinterrupts = <0x0 0x0 0x4>;\n+\t\tcompatible = \"brcm,bcm7445-pcie\";\n+\t\t#address-cells = <3>;\n+\t\t#size-cells = <2>;\n+\t\tranges = <0x02000000 0x00000000 0x00000000 0x00000000 0xc0000000 0x00000000 0x08000000\n+\t\t\t  0x02000000 0x00000000 0x08000000 0x00000000 0xc8000000 0x00000000 0x08000000>;\n+\t\t#interrupt-cells = <1>;\n+\t\tinterrupt-map-mask = <0 0 0 7>;\n+\t\tinterrupt-map = <0 0 0 1 &intc 0 47 3\n+\t\t\t\t 0 0 0 2 &intc 0 48 3\n+\t\t\t\t 0 0 0 3 &intc 0 49 3\n+\t\t\t\t 0 0 0 4 &intc 0 50 3>;\n+\t\tclocks = <&sw_pcie0>;\n+\t\tclock-names = \"sw_pcie\";\n+\t\tmsi-parent = <&pcie0>;  /* use PCIe's internal MSI controller */\n+\t\tmsi-controller;         /* use PCIe's internal MSI controller */\n+\t\tbrcm,ssc;\n+\t\tmax-link-speed = <1>;\n+\t\tlinux,pci-domain = <0>;\n+\t};\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0192-Kbuild-Allow-.dtbo-overlays-to-be-built-adjust.patch",
    "content": "From 45ae2035e05d4519d86f1073a257dea3a920f484 Mon Sep 17 00:00:00 2001\nFrom: Nataliya Korovkina <malus.brandywine@gmail.com>\nDate: Thu, 12 Mar 2020 17:22:53 -0400\nSubject: [PATCH] Kbuild: Allow .dtbo overlays to be built, adjust.\n\nThis is adjustment to commit\nd368ceaacdccd7732dc97d1d7987bdf7149d62e3 \"kbuild: Allow .dtbo overlays to be built piecemeal\"\n\nprepare3 target has gone from mainline tree in branch 5.4.y\n\nSigned-off-by: Nataliya Korovkina <malus.brandywine@gmail.com>\n---\n Makefile | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/Makefile\n+++ b/Makefile\n@@ -1354,7 +1354,7 @@ ifneq ($(dtstree),)\n %.dtb: include/config/kernel.release scripts_dtc\n \t$(Q)$(MAKE) $(build)=$(dtstree) $(dtstree)/$@\n \n-%.dtbo: prepare3 scripts_dtc\n+%.dtbo: include/config/kernel.release scripts_dtc\n \t$(Q)$(MAKE) $(build)=$(dtstree) $(dtstree)/$@\n \n PHONY += dtbs dtbs_install dtbs_check\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0193-bcmgenet-Disable-skip_umac_reset-by-default.patch",
    "content": "From f290455548d9e9ea5f03464d229d08a854a9fb37 Mon Sep 17 00:00:00 2001\nFrom: popcornmix <popcornmix@gmail.com>\nDate: Wed, 1 Apr 2020 11:22:44 +0100\nSubject: [PATCH] bcmgenet: Disable skip_umac_reset by default\n\nPossible fixed upstream by 'net: bcmgenet: keep MAC in reset until PHY is up'\n\nSigned-off-by: popcornmix <popcornmix@gmail.com>\n---\n drivers/net/ethernet/broadcom/genet/bcmgenet.c | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/drivers/net/ethernet/broadcom/genet/bcmgenet.c\n+++ b/drivers/net/ethernet/broadcom/genet/bcmgenet.c\n@@ -67,7 +67,7 @@\n \n /* Forward declarations */\n static void bcmgenet_set_rx_mode(struct net_device *dev);\n-static bool skip_umac_reset = true;\n+static bool skip_umac_reset = false;\n module_param(skip_umac_reset, bool, 0444);\n MODULE_PARM_DESC(skip_umac_reset, \"Skip UMAC reset step\");\n \n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0194-drm-fourcc-Add-packed-10bit-YUV-4-2-0-format.patch",
    "content": "From 1a3319588434a2acfe47a38fcdf6583a3b84ecd3 Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Fri, 24 Jan 2020 14:22:06 +0000\nSubject: [PATCH] drm/fourcc: Add packed 10bit YUV 4:2:0 format\n\nAdds a format that is 3 10bit YUV 4:2:0 samples packed into\na 32bit work (with 2 spare bits).\n\nSupported on Broadcom BCM2711 chips.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n drivers/gpu/drm/drm_fourcc.c  |  3 +++\n include/uapi/drm/drm_fourcc.h | 11 +++++++++++\n 2 files changed, 14 insertions(+)\n\n--- a/drivers/gpu/drm/drm_fourcc.c\n+++ b/drivers/gpu/drm/drm_fourcc.c\n@@ -286,6 +286,9 @@ const struct drm_format_info *__drm_form\n \t\t  .num_planes = 3, .char_per_block = { 2, 2, 2 },\n \t\t  .block_w = { 1, 1, 1 }, .block_h = { 1, 1, 1 }, .hsub = 0,\n \t\t  .vsub = 0, .is_yuv = true },\n+\t\t{ .format = DRM_FORMAT_P030,            .depth = 0,  .num_planes = 2,\n+\t\t  .char_per_block = { 4, 4, 0 }, .block_w = { 3, 0, 0 }, .block_h = { 1, 0, 0 },\n+\t\t  .hsub = 2, .vsub = 2, .is_yuv = true},\n \t};\n \n \tunsigned int i;\n--- a/include/uapi/drm/drm_fourcc.h\n+++ b/include/uapi/drm/drm_fourcc.h\n@@ -288,6 +288,13 @@ extern \"C\" {\n #define DRM_FORMAT_Q401\t\tfourcc_code('Q', '4', '0', '1')\n \n /*\n+ * 2 plane YCbCr MSB aligned, 3 pixels packed into 4 bytes.\n+ * index 0 = Y plane, [31:0] x:Y2:Y1:Y0 2:10:10:10 little endian\n+ * index 1 = Cr:Cb plane, [63:0] x:Cr2:Cb2:Cr1:x:Cb1:Cr0:Cb0 [2:10:10:10:2:10:10:10] little endian\n+ */\n+#define DRM_FORMAT_P030\t\tfourcc_code('P', '0', '3', '0') /* 2x2 subsampled Cr:Cb plane 10 bits per channel packed */\n+\n+/*\n  * 3 plane YCbCr\n  * index 0: Y plane, [7:0] Y\n  * index 1: Cb plane, [7:0] Cb\n@@ -777,6 +784,10 @@ drm_fourcc_canonicalize_nvidia_format_mo\n  * and UV.  Some SAND-using hardware stores UV in a separate tiled\n  * image from Y to reduce the column height, which is not supported\n  * with these modifiers.\n+ *\n+ * The DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT modifier is also\n+ * supported for DRM_FORMAT_P030 where the columns remain as 128 bytes\n+ * wide, but as this is a 10 bpp format that translates to 96 pixels.\n  */\n \n #define DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(v) \\\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0195-media-uapi-hevc-Add-scaling-matrix-control.patch",
    "content": "From e4ae41f35d7d361759b5aa1e1a3e13bafd46f9db Mon Sep 17 00:00:00 2001\nFrom: Jernej Skrabec <jernej.skrabec@siol.net>\nDate: Fri, 13 Dec 2019 17:04:25 +0100\nSubject: [PATCH] media: uapi: hevc: Add scaling matrix control\n\nTaken from https://patchwork.linuxtv.org/patch/60728/\nChanges (mainly documentation) have been requested.\n\nHEVC has a scaling matrix concept. Add support for it.\n\nSigned-off-by: Jernej Skrabec <jernej.skrabec@siol.net>\n---\n .../media/v4l/ext-ctrls-codec.rst             | 41 +++++++++++++++++++\n .../media/v4l/pixfmt-compressed.rst           |  1 +\n drivers/media/v4l2-core/v4l2-ctrls.c          | 10 +++++\n include/media/hevc-ctrls.h                    | 11 +++++\n 4 files changed, 63 insertions(+)\n\n--- a/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst\n+++ b/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst\n@@ -4319,6 +4319,47 @@ enum v4l2_mpeg_video_hevc_size_of_length\n       - ``padding[6]``\n       - Applications and drivers must set this to zero.\n \n+``V4L2_CID_MPEG_VIDEO_HEVC_SCALING_MATRIX (struct)``\n+    Specifies the scaling matrix (as extracted from the bitstream) for\n+    the associated HEVC slice data. The bitstream parameters are\n+    defined according to :ref:`hevc`, section 7.4.5 \"Scaling list\n+    data semantics\". For further documentation, refer to the above\n+    specification, unless there is an explicit comment stating\n+    otherwise.\n+\n+    .. note::\n+\n+       This compound control is not yet part of the public kernel API and\n+       it is expected to change.\n+\n+.. c:type:: v4l2_ctrl_hevc_scaling_matrix\n+\n+.. cssclass:: longtable\n+\n+.. flat-table:: struct v4l2_ctrl_hevc_scaling_matrix\n+    :header-rows:  0\n+    :stub-columns: 0\n+    :widths:       1 1 2\n+\n+    * - __u8\n+      - ``scaling_list_4x4[6][16]``\n+      -\n+    * - __u8\n+      - ``scaling_list_8x8[6][64]``\n+      -\n+    * - __u8\n+      - ``scaling_list_16x16[6][64]``\n+      -\n+    * - __u8\n+      - ``scaling_list_32x32[2][64]``\n+      -\n+    * - __u8\n+      - ``scaling_list_dc_coef_16x16[6]``\n+      -\n+    * - __u8\n+      - ``scaling_list_dc_coef_32x32[2]``\n+      -\n+\n ``V4L2_CID_MPEG_VIDEO_HEVC_DECODE_MODE (enum)``\n     Specifies the decoding mode to use. Currently exposes slice-based and\n     frame-based decoding but new modes might be added later on.\n--- a/Documentation/userspace-api/media/v4l/pixfmt-compressed.rst\n+++ b/Documentation/userspace-api/media/v4l/pixfmt-compressed.rst\n@@ -200,6 +200,7 @@ Compressed Formats\n         * ``V4L2_CID_MPEG_VIDEO_HEVC_SPS``\n         * ``V4L2_CID_MPEG_VIDEO_HEVC_PPS``\n         * ``V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS``\n+        * ``V4L2_CID_MPEG_VIDEO_HEVC_SCALING_MATRIX``\n \tSee the :ref:`associated Codec Control IDs <v4l2-mpeg-hevc>`.\n \tBuffers associated with this pixel format must contain the appropriate\n \tnumber of macroblocks to decode a full corresponding frame.\n--- a/drivers/media/v4l2-core/v4l2-ctrls.c\n+++ b/drivers/media/v4l2-core/v4l2-ctrls.c\n@@ -1022,6 +1022,7 @@ const char *v4l2_ctrl_get_name(u32 id)\n \tcase V4L2_CID_MPEG_VIDEO_HEVC_SPS:\t\t\treturn \"HEVC Sequence Parameter Set\";\n \tcase V4L2_CID_MPEG_VIDEO_HEVC_PPS:\t\t\treturn \"HEVC Picture Parameter Set\";\n \tcase V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS:\t\treturn \"HEVC Slice Parameters\";\n+\tcase V4L2_CID_MPEG_VIDEO_HEVC_SCALING_MATRIX:\t\treturn \"HEVC Scaling Matrix\";\n \tcase V4L2_CID_MPEG_VIDEO_HEVC_DECODE_MODE:\t\treturn \"HEVC Decode Mode\";\n \tcase V4L2_CID_MPEG_VIDEO_HEVC_START_CODE:\t\treturn \"HEVC Start Code\";\n \n@@ -1462,6 +1463,9 @@ void v4l2_ctrl_fill(u32 id, const char *\n \tcase V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS:\n \t\t*type = V4L2_CTRL_TYPE_HEVC_SLICE_PARAMS;\n \t\tbreak;\n+\tcase V4L2_CID_MPEG_VIDEO_HEVC_SCALING_MATRIX:\n+\t\t*type = V4L2_CTRL_TYPE_HEVC_SCALING_MATRIX;\n+\t\tbreak;\n \tcase V4L2_CID_UNIT_CELL_SIZE:\n \t\t*type = V4L2_CTRL_TYPE_AREA;\n \t\t*flags |= V4L2_CTRL_FLAG_READ_ONLY;\n@@ -1935,6 +1939,9 @@ static int std_validate_compound(const s\n \t\tzero_padding(*p_hevc_slice_params);\n \t\tbreak;\n \n+\tcase V4L2_CTRL_TYPE_HEVC_SCALING_MATRIX:\n+\t\tbreak;\n+\n \tcase V4L2_CTRL_TYPE_AREA:\n \t\tarea = p;\n \t\tif (!area->width || !area->height)\n@@ -2645,6 +2652,9 @@ static struct v4l2_ctrl *v4l2_ctrl_new(s\n \tcase V4L2_CTRL_TYPE_HEVC_SLICE_PARAMS:\n \t\telem_size = sizeof(struct v4l2_ctrl_hevc_slice_params);\n \t\tbreak;\n+\tcase V4L2_CTRL_TYPE_HEVC_SCALING_MATRIX:\n+\t\telem_size = sizeof(struct v4l2_ctrl_hevc_scaling_matrix);\n+\t\tbreak;\n \tcase V4L2_CTRL_TYPE_AREA:\n \t\telem_size = sizeof(struct v4l2_area);\n \t\tbreak;\n--- a/include/media/hevc-ctrls.h\n+++ b/include/media/hevc-ctrls.h\n@@ -19,6 +19,7 @@\n #define V4L2_CID_MPEG_VIDEO_HEVC_SPS\t\t(V4L2_CID_MPEG_BASE + 1008)\n #define V4L2_CID_MPEG_VIDEO_HEVC_PPS\t\t(V4L2_CID_MPEG_BASE + 1009)\n #define V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS\t(V4L2_CID_MPEG_BASE + 1010)\n+#define V4L2_CID_MPEG_VIDEO_HEVC_SCALING_MATRIX\t(V4L2_CID_MPEG_BASE + 1011)\n #define V4L2_CID_MPEG_VIDEO_HEVC_DECODE_MODE\t(V4L2_CID_MPEG_BASE + 1015)\n #define V4L2_CID_MPEG_VIDEO_HEVC_START_CODE\t(V4L2_CID_MPEG_BASE + 1016)\n \n@@ -26,6 +27,7 @@\n #define V4L2_CTRL_TYPE_HEVC_SPS 0x0120\n #define V4L2_CTRL_TYPE_HEVC_PPS 0x0121\n #define V4L2_CTRL_TYPE_HEVC_SLICE_PARAMS 0x0122\n+#define V4L2_CTRL_TYPE_HEVC_SCALING_MATRIX 0x0123\n \n enum v4l2_mpeg_video_hevc_decode_mode {\n \tV4L2_MPEG_VIDEO_HEVC_DECODE_MODE_SLICE_BASED,\n@@ -210,4 +212,13 @@ struct v4l2_ctrl_hevc_slice_params {\n \t__u64\tflags;\n };\n \n+struct v4l2_ctrl_hevc_scaling_matrix {\n+\t__u8\tscaling_list_4x4[6][16];\n+\t__u8\tscaling_list_8x8[6][64];\n+\t__u8\tscaling_list_16x16[6][64];\n+\t__u8\tscaling_list_32x32[2][64];\n+\t__u8\tscaling_list_dc_coef_16x16[6];\n+\t__u8\tscaling_list_dc_coef_32x32[2];\n+};\n+\n #endif\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0196-media-uapi-hevc-Add-segment-address-field.patch",
    "content": "From 551676b89a12d9de33618c1c02b749653941fe83 Mon Sep 17 00:00:00 2001\nFrom: Jernej Skrabec <jernej.skrabec@siol.net>\nDate: Fri, 13 Dec 2019 17:04:27 +0100\nSubject: [PATCH] media: uapi: hevc: Add segment address field\n\nFrom https://patchwork.linuxtv.org/patch/60725/\nChanges requested, but mainly docs.\n\nIf HEVC frame consists of multiple slices, segment address has to be\nknown in order to properly decode it.\n\nAdd segment address field to slice parameters.\n\nSigned-off-by: Jernej Skrabec <jernej.skrabec@siol.net>\n---\n Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst | 5 ++++-\n include/media/hevc-ctrls.h                                | 5 ++++-\n 2 files changed, 8 insertions(+), 2 deletions(-)\n\n--- a/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst\n+++ b/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst\n@@ -4111,6 +4111,9 @@ enum v4l2_mpeg_video_hevc_size_of_length\n     * - __u32\n       - ``data_bit_offset``\n       - Offset (in bits) to the video data in the current slice data.\n+    * - __u32\n+      - ``slice_segment_addr``\n+      -\n     * - __u8\n       - ``nal_unit_type``\n       -\n@@ -4188,7 +4191,7 @@ enum v4l2_mpeg_video_hevc_size_of_length\n       - ``num_rps_poc_lt_curr``\n       - The number of reference pictures in the long-term set.\n     * - __u8\n-      - ``padding[7]``\n+      - ``padding[5]``\n       - Applications and drivers must set this to zero.\n     * - struct :c:type:`v4l2_hevc_dpb_entry`\n       - ``dpb[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]``\n--- a/include/media/hevc-ctrls.h\n+++ b/include/media/hevc-ctrls.h\n@@ -168,6 +168,9 @@ struct v4l2_ctrl_hevc_slice_params {\n \t__u32\tbit_size;\n \t__u32\tdata_bit_offset;\n \n+\t/* ISO/IEC 23008-2, ITU-T Rec. H.265: General slice segment header */\n+\t__u32\tslice_segment_addr;\n+\n \t/* ISO/IEC 23008-2, ITU-T Rec. H.265: NAL unit header */\n \t__u8\tnal_unit_type;\n \t__u8\tnuh_temporal_id_plus1;\n@@ -201,7 +204,7 @@ struct v4l2_ctrl_hevc_slice_params {\n \t__u8\tnum_rps_poc_st_curr_after;\n \t__u8\tnum_rps_poc_lt_curr;\n \n-\t__u8\tpadding;\n+\t__u8\tpadding[5];\n \n \t/* ISO/IEC 23008-2, ITU-T Rec. H.265: General slice segment header */\n \tstruct v4l2_hevc_dpb_entry dpb[V4L2_HEVC_DPB_ENTRIES_NUM_MAX];\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0197-media-uapi-Add-hevc-ctrls-for-WPP-decoding.patch",
    "content": "From cfbd02c5469513b6d28d9012b14d70baa44869c5 Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Mon, 23 Mar 2020 19:00:17 +0000\nSubject: [PATCH] media: uapi: Add hevc ctrls for WPP decoding\n\nWPP can allow greater parallelism within the decode, but needs\noffset information to be passed in.\n\nAdds num_entry_point_offsets and entry_point_offset_minus1 to\nv4l2_ctrl_hevc_slice_params.\n\nThis is based on Jernej Skrabec's patches for cedrus which\nimplement the same feature.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n include/media/hevc-ctrls.h | 5 ++++-\n 1 file changed, 4 insertions(+), 1 deletion(-)\n\n--- a/include/media/hevc-ctrls.h\n+++ b/include/media/hevc-ctrls.h\n@@ -170,6 +170,7 @@ struct v4l2_ctrl_hevc_slice_params {\n \n \t/* ISO/IEC 23008-2, ITU-T Rec. H.265: General slice segment header */\n \t__u32\tslice_segment_addr;\n+\t__u32\tnum_entry_point_offsets;\n \n \t/* ISO/IEC 23008-2, ITU-T Rec. H.265: NAL unit header */\n \t__u8\tnal_unit_type;\n@@ -204,7 +205,9 @@ struct v4l2_ctrl_hevc_slice_params {\n \t__u8\tnum_rps_poc_st_curr_after;\n \t__u8\tnum_rps_poc_lt_curr;\n \n-\t__u8\tpadding[5];\n+\t__u8\tpadding;\n+\n+\t__u32\tentry_point_offset_minus1[256];\n \n \t/* ISO/IEC 23008-2, ITU-T Rec. H.265: General slice segment header */\n \tstruct v4l2_hevc_dpb_entry dpb[V4L2_HEVC_DPB_ENTRIES_NUM_MAX];\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0198-media-videodev2.h-Add-a-format-for-column-YUV4-2-0-m.patch",
    "content": "From 3e25101dea3ed13e98339dffbc9410459e617d9a Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Fri, 24 Jan 2020 14:28:21 +0000\nSubject: [PATCH] media: videodev2.h: Add a format for column YUV4:2:0\n modes\n\nSome of the Broadcom codec blocks use a column based YUV4:2:0 image\nformat, so add the documentation and defines for both 8 and 10 bit\nversions.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n .../media/v4l/pixfmt-nv12-col128.rst          | 215 ++++++++++++++++++\n .../userspace-api/media/v4l/pixfmt-nv12.rst   |  14 +-\n .../userspace-api/media/v4l/yuv-formats.rst   |   1 +\n drivers/media/v4l2-core/v4l2-ioctl.c          |   2 +\n include/uapi/linux/videodev2.h                |   4 +\n 5 files changed, 233 insertions(+), 3 deletions(-)\n create mode 100644 Documentation/userspace-api/media/v4l/pixfmt-nv12-col128.rst\n\n--- /dev/null\n+++ b/Documentation/userspace-api/media/v4l/pixfmt-nv12-col128.rst\n@@ -0,0 +1,215 @@\n+.. Permission is granted to copy, distribute and/or modify this\n+.. document under the terms of the GNU Free Documentation License,\n+.. Version 1.1 or any later version published by the Free Software\n+.. Foundation, with no Invariant Sections, no Front-Cover Texts\n+.. and no Back-Cover Texts. A copy of the license is included at\n+.. Documentation/media/uapi/fdl-appendix.rst.\n+..\n+.. TODO: replace it to GFDL-1.1-or-later WITH no-invariant-sections\n+\n+.. _V4L2_PIX_FMT_NV12_COL128:\n+.. _V4L2_PIX_FMT_NV12_10_COL128:\n+\n+********************************************************************************\n+V4L2_PIX_FMT_NV12_COL128, V4L2_PIX_FMT_NV12_10_COL128\n+********************************************************************************\n+\n+\n+V4L2_PIX_FMT_NV21_COL128\n+Formats with ½ horizontal and vertical chroma resolution. This format\n+has two planes - one for luminance and one for chrominance. Chroma\n+samples are interleaved. The difference to ``V4L2_PIX_FMT_NV12`` is the\n+memory layout. The image is split into columns of 128 bytes wide rather than\n+being in raster order.\n+\n+V4L2_PIX_FMT_NV12_10_COL128\n+Follows the same pattern as ``V4L2_PIX_FMT_NV21_COL128`` with 128 byte, but is\n+a 10bit format with 3 10-bit samples being packed into 4 bytes. Each 128 byte\n+wide column therefore contains 96 samples.\n+\n+\n+Description\n+===========\n+\n+This is the two-plane versions of the YUV 4:2:0 format where data is\n+grouped into 128 byte wide columns. The three components are separated into\n+two sub-images or planes. The Y plane has one byte per pixel and pixels\n+are grouped into 128 byte wide columns. The CbCr plane has the same width,\n+in bytes, as the Y plane (and the image), but is half as tall in pixels.\n+The chroma plane is also in 128 byte columns, reflecting 64 Cb and 64 Cr\n+samples.\n+\n+The chroma samples for a column follow the luma samples. If there is any\n+paddding, then that will be reflected via the selection API.\n+The luma height must be a multiple of 2 lines.\n+\n+The normal bytesperline is effectively fixed at 128. However the format\n+requires knowledge of the stride between columns, therefore the bytesperline\n+value has been repurposed to denote the number of 128 byte long lines between\n+the start of each column.\n+\n+**Byte Order.**\n+\n+\n+.. flat-table::\n+    :header-rows:  0\n+    :stub-columns: 0\n+    :widths: 12 12 12 12 12 4 12 12 12 12\n+\n+    * - start + 0:\n+      - Y'\\ :sub:`0,0`\n+      - Y'\\ :sub:`0,1`\n+      - Y'\\ :sub:`0,2`\n+      - Y'\\ :sub:`0,3`\n+      - ...\n+      - Y'\\ :sub:`0,124`\n+      - Y'\\ :sub:`0,125`\n+      - Y'\\ :sub:`0,126`\n+      - Y'\\ :sub:`0,127`\n+    * - start + 128:\n+      - Y'\\ :sub:`1,0`\n+      - Y'\\ :sub:`1,1`\n+      - Y'\\ :sub:`1,2`\n+      - Y'\\ :sub:`1,3`\n+      - ...\n+      - Y'\\ :sub:`1,124`\n+      - Y'\\ :sub:`1,125`\n+      - Y'\\ :sub:`1,126`\n+      - Y'\\ :sub:`1,127`\n+    * - start + 256:\n+      - Y'\\ :sub:`2,0`\n+      - Y'\\ :sub:`2,1`\n+      - Y'\\ :sub:`2,2`\n+      - Y'\\ :sub:`2,3`\n+      - ...\n+      - Y'\\ :sub:`2,124`\n+      - Y'\\ :sub:`2,125`\n+      - Y'\\ :sub:`2,126`\n+      - Y'\\ :sub:`2,127`\n+    * - ...\n+      - ...\n+      - ...\n+      - ...\n+      - ...\n+      - ...\n+      - ...\n+      - ...\n+    * - start + ((height-1) * 128):\n+      - Y'\\ :sub:`height-1,0`\n+      - Y'\\ :sub:`height-1,1`\n+      - Y'\\ :sub:`height-1,2`\n+      - Y'\\ :sub:`height-1,3`\n+      - ...\n+      - Y'\\ :sub:`height-1,124`\n+      - Y'\\ :sub:`height-1,125`\n+      - Y'\\ :sub:`height-1,126`\n+      - Y'\\ :sub:`height-1,127`\n+    * - start + ((height) * 128):\n+      - Cb\\ :sub:`0,0`\n+      - Cr\\ :sub:`0,0`\n+      - Cb\\ :sub:`0,1`\n+      - Cr\\ :sub:`0,1`\n+      - ...\n+      - Cb\\ :sub:`0,62`\n+      - Cr\\ :sub:`0,62`\n+      - Cb\\ :sub:`0,63`\n+      - Cr\\ :sub:`0,63`\n+    * - start + ((height+1) * 128):\n+      - Cb\\ :sub:`1,0`\n+      - Cr\\ :sub:`1,0`\n+      - Cb\\ :sub:`1,1`\n+      - Cr\\ :sub:`1,1`\n+      - ...\n+      - Cb\\ :sub:`1,62`\n+      - Cr\\ :sub:`1,62`\n+      - Cb\\ :sub:`1,63`\n+      - Cr\\ :sub:`1,63`\n+    * - ...\n+      - ...\n+      - ...\n+      - ...\n+      - ...\n+      - ...\n+      - ...\n+      - ...\n+    * - start + ((height+(height/2)-1) * 128):\n+      - Cb\\ :sub:`(height/2)-1,0`\n+      - Cr\\ :sub:`(height/2)-1,0`\n+      - Cb\\ :sub:`(height/2)-1,1`\n+      - Cr\\ :sub:`(height/2)-1,1`\n+      - ...\n+      - Cb\\ :sub:`(height/2)-1,62`\n+      - Cr\\ :sub:`(height/2)-1,62`\n+      - Cb\\ :sub:`(height/2)-1,63`\n+      - Cr\\ :sub:`(height/2)-1,63`\n+    * - start + (bytesperline * 128):\n+      - Y'\\ :sub:`0,128`\n+      - Y'\\ :sub:`0,129`\n+      - Y'\\ :sub:`0,130`\n+      - Y'\\ :sub:`0,131`\n+      - ...\n+      - Y'\\ :sub:`0,252`\n+      - Y'\\ :sub:`0,253`\n+      - Y'\\ :sub:`0,254`\n+      - Y'\\ :sub:`0,255`\n+    * - ...\n+      - ...\n+      - ...\n+      - ...\n+      - ...\n+      - ...\n+      - ...\n+      - ...\n+\n+V4L2_PIX_FMT_NV12_10_COL128 uses the same 128 byte column structure, but\n+encodes 10-bit YUV.\n+3 10-bit values are packed into 4 bytes as bits 9:0, 19:10, and 29:20, with\n+bits 30 & 31 unused. For the luma plane, bits 9:0 are Y0, 19:10 are Y1, and\n+29:20 are Y2. For the chroma plane the samples always come in pairs of Cr\n+and Cb, so it needs to be considered 6 values packed in 8 bytes.\n+\n+Bit-packed representation.\n+\n+.. raw:: latex\n+\n+    \\small\n+\n+.. tabularcolumns:: |p{1.2cm}||p{1.2cm}||p{1.2cm}||p{1.2cm}|p{3.2cm}|p{3.2cm}|\n+\n+.. flat-table::\n+    :header-rows:  0\n+    :stub-columns: 0\n+    :widths: 8 8 8 8\n+\n+    * - Y'\\ :sub:`00[7:0]`\n+      - Y'\\ :sub:`01[5:0] (bits 7--2)` Y'\\ :sub:`00[9:8]`\\ (bits 1--0)\n+      - Y'\\ :sub:`02[3:0] (bits 7--4)` Y'\\ :sub:`01[9:6]`\\ (bits 3--0)\n+      - unused (bits 7--6)` Y'\\ :sub:`02[9:4]`\\ (bits 5--0)\n+\n+.. raw:: latex\n+\n+    \\small\n+\n+.. tabularcolumns:: |p{1.2cm}||p{1.2cm}||p{1.2cm}||p{1.2cm}|p{3.2cm}|p{3.2cm}|\n+\n+.. flat-table::\n+    :header-rows:  0\n+    :stub-columns: 0\n+    :widths: 12 12 12 12 12 12 12 12\n+\n+    * - Cb\\ :sub:`00[7:0]`\n+      - Cr\\ :sub:`00[5:0]`\\ (bits 7--2) Cb\\ :sub:`00[9:8]`\\ (bits 1--0)\n+      - Cb\\ :sub:`01[3:0]`\\ (bits 7--4) Cr\\ :sub:`00[9:6]`\\ (bits 3--0)\n+      - unused (bits 7--6) Cb\\ :sub:`02[9:4]`\\ (bits 5--0)\n+      - Cr\\ :sub:`01[7:0]`\n+      - Cb\\ :sub:`02[5:0]`\\ (bits 7--2) Cr\\ :sub:`01[9:8]`\\ (bits 1--0)\n+      - Cr\\ :sub:`02[3:0]`\\ (bits 7--4) Cb\\ :sub:`02[9:6]`\\ (bits 3--0)\n+      - unused (bits 7--6) Cr\\ :sub:`02[9:4]`\\ (bits 5--0)\n+\n+.. raw:: latex\n+\n+    \\normalsize\n+\n+\n+\n+\n--- a/Documentation/userspace-api/media/v4l/pixfmt-nv12.rst\n+++ b/Documentation/userspace-api/media/v4l/pixfmt-nv12.rst\n@@ -3,9 +3,9 @@\n .. _V4L2-PIX-FMT-NV12:\n .. _V4L2-PIX-FMT-NV21:\n \n-******************************************************\n-V4L2_PIX_FMT_NV12 ('NV12'), V4L2_PIX_FMT_NV21 ('NV21')\n-******************************************************\n+********************************************************************************\n+V4L2_PIX_FMT_NV12 ('NV12'), V4L2_PIX_FMT_NV21 ('NV21'), V4L2_PIX_FMT_NV12_COL128\n+********************************************************************************\n \n \n V4L2_PIX_FMT_NV21\n@@ -31,6 +31,14 @@ with a Cr byte.\n If the Y plane has pad bytes after each row, then the CbCr plane has as\n many pad bytes after its rows.\n \n+``V4L2_PIX_FMT_NV12_COL128`` is the tiled version of\n+``V4L2_PIX_FMT_NV12`` with the image broken down into 128 pixel wide columns of\n+Y followed by the associated combined CbCr plane.\n+The normal bytesperline is effectively fixed at 128. However the format\n+requires knowledge of the stride between columns, therefore the bytesperline\n+value has been repurposed to denote the number of 128 byte long lines between\n+the start of each column.\n+\n **Byte Order.**\n Each cell is one byte.\n \n--- a/Documentation/userspace-api/media/v4l/yuv-formats.rst\n+++ b/Documentation/userspace-api/media/v4l/yuv-formats.rst\n@@ -51,6 +51,7 @@ to brightness information.\n     pixfmt-nv12\n     pixfmt-nv12m\n     pixfmt-nv12mt\n+    pixfmt-nv12-col128\n     pixfmt-nv16\n     pixfmt-nv16m\n     pixfmt-nv24\n--- a/drivers/media/v4l2-core/v4l2-ioctl.c\n+++ b/drivers/media/v4l2-core/v4l2-ioctl.c\n@@ -1343,6 +1343,8 @@ static void v4l_fill_fmtdesc(struct v4l2\n \tcase V4L2_PIX_FMT_NV61M:\tdescr = \"Y/CrCb 4:2:2 (N-C)\"; break;\n \tcase V4L2_PIX_FMT_NV12MT:\tdescr = \"Y/CbCr 4:2:0 (64x32 MB, N-C)\"; break;\n \tcase V4L2_PIX_FMT_NV12MT_16X16:\tdescr = \"Y/CbCr 4:2:0 (16x16 MB, N-C)\"; break;\n+\tcase V4L2_PIX_FMT_NV12_COL128:\tdescr = \"Y/CbCr 4:2:0 (128b cols)\"; break;\n+\tcase V4L2_PIX_FMT_NV12_10_COL128: descr = \"10-bit Y/CbCr 4:2:0 (128b cols)\"; break;\n \tcase V4L2_PIX_FMT_YUV420M:\tdescr = \"Planar YUV 4:2:0 (N-C)\"; break;\n \tcase V4L2_PIX_FMT_YVU420M:\tdescr = \"Planar YVU 4:2:0 (N-C)\"; break;\n \tcase V4L2_PIX_FMT_YUV422M:\tdescr = \"Planar YUV 4:2:2 (N-C)\"; break;\n--- a/include/uapi/linux/videodev2.h\n+++ b/include/uapi/linux/videodev2.h\n@@ -745,6 +745,10 @@ struct v4l2_pix_format {\n #define V4L2_PIX_FMT_INZI     v4l2_fourcc('I', 'N', 'Z', 'I') /* Intel Planar Greyscale 10-bit and Depth 16-bit */\n #define V4L2_PIX_FMT_SUNXI_TILED_NV12 v4l2_fourcc('S', 'T', '1', '2') /* Sunxi Tiled NV12 Format */\n #define V4L2_PIX_FMT_CNF4     v4l2_fourcc('C', 'N', 'F', '4') /* Intel 4-bit packed depth confidence information */\n+#define V4L2_PIX_FMT_NV12_COL128 v4l2_fourcc('N', 'C', '1', '2') /* 12  Y/CbCr 4:2:0 128 pixel wide column */\n+#define V4L2_PIX_FMT_NV12_10_COL128 v4l2_fourcc('N', 'C', '3', '0')\n+\t\t\t\t\t\t\t\t/* Y/CbCr 4:2:0 10bpc, 3x10 packed as 4 bytes in\n+\t\t\t\t\t\t\t\t * a 128 bytes / 96 pixel wide column */\n \n /* 10bit raw bayer packed, 32 bytes for every 25 pixels, last LSB 6 bits unused */\n #define V4L2_PIX_FMT_IPU3_SBGGR10\tv4l2_fourcc('i', 'p', '3', 'b') /* IPU3 packed 10-bit BGGR bayer */\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0199-media-dt-bindings-media-Add-binding-for-the-Raspberr.patch",
    "content": "From 9b6a40e7b71b4f133e1151313b38ba187764a9e9 Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Tue, 17 Mar 2020 10:53:16 +0000\nSubject: [PATCH] media: dt-bindings: media: Add binding for the\n Raspberry PI HEVC decoder\n\nAdds a binding for the HEVC decoder found on the BCM2711 / Raspberry Pi 4.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n .../bindings/media/rpivid_hevc.yaml           | 72 +++++++++++++++++++\n MAINTAINERS                                   |  7 ++\n 2 files changed, 79 insertions(+)\n create mode 100644 Documentation/devicetree/bindings/media/rpivid_hevc.yaml\n\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/media/rpivid_hevc.yaml\n@@ -0,0 +1,72 @@\n+# SPDX-License-Identifier: GPL-2.0-only\n+%YAML 1.2\n+---\n+$id: http://devicetree.org/schemas/media/rpivid_hevc.yaml#\n+$schema: http://devicetree.org/meta-schemas/core.yaml#\n+\n+title: Raspberry Pi HEVC Decoder\n+\n+maintainers:\n+  - Raspberry Pi <kernel-list@raspberrypi.com>\n+\n+description: |-\n+  The Camera Adaptation Layer (CAL) is a key component for image capture\n+  applications. The capture module provides the system interface and the\n+  processing capability to connect CSI2 image-sensor modules to the\n+  DRA72x device.\n+\n+properties:\n+  compatible:\n+    enum:\n+      - raspberrypi,rpivid-vid-decoder\n+\n+  reg:\n+    minItems: 2\n+    items:\n+      - description: The HEVC main register region\n+      - description: The Interrupt controller register region\n+\n+  reg-names:\n+    minItems: 2\n+    items:\n+      - const: hevc\n+      - const: intc\n+\n+  interrupts:\n+    maxItems: 1\n+\n+  clocks:\n+    items:\n+      - description: The HEVC block clock\n+\n+  clock-names:\n+    items:\n+      - const: hevc\n+\n+required:\n+  - compatible\n+  - reg\n+  - reg-names\n+  - interrupts\n+  - clocks\n+\n+additionalProperties: false\n+\n+examples:\n+  - |\n+    #include <dt-bindings/interrupt-controller/arm-gic.h>\n+\n+    video-codec@7eb10000 {\n+        compatible = \"raspberrypi,rpivid-vid-decoder\";\n+        reg = <0x0 0x7eb10000 0x1000>,\t/* INTC */\n+              <0x0 0x7eb00000 0x10000>; /* HEVC */\n+        reg-names = \"intc\",\n+                    \"hevc\";\n+\n+        interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;\n+\n+        clocks = <&clk 0>;\n+        clock-names = \"hevc\";\n+    };\n+\n+...\n--- a/MAINTAINERS\n+++ b/MAINTAINERS\n@@ -3418,6 +3418,13 @@ N:\tbcm113*\n N:\tbcm216*\n N:\tkona\n \n+BROADCOM BCM2711 HEVC DECODER\n+M:\tRaspberry Pi Kernel Maintenance <kernel-list@raspberrypi.com>\n+L:\tlinux-media@vger.kernel.org\n+S:\tMaintained\n+F:\tDocumentation/devicetree/bindings/media/rpivid_hevc.jaml\n+F:\tdrivers/staging/media/rpivid\n+\n BROADCOM BCM2835 CAMERA DRIVER\n M:\tDave Stevenson <dave.stevenson@raspberrypi.org>\n L:\tlinux-media@vger.kernel.org\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0200-staging-media-Add-Raspberry-Pi-V4L2-H265-decoder.patch",
    "content": "From ea6d2c1bdad5a18f0d81ed4923a62f01180e3250 Mon Sep 17 00:00:00 2001\nFrom: John Cox <jc@kynesim.co.uk>\nDate: Thu, 5 Mar 2020 18:30:41 +0000\nSubject: [PATCH] staging: media: Add Raspberry Pi V4L2 H265 decoder\n\nThis driver is for the HEVC/H265 decoder block on the Raspberry\nPi 4, and conforms to the V4L2 stateless decoder API.\n\nSigned-off-by: John Cox <jc@kynesim.co.uk>\n---\n drivers/staging/media/Kconfig               |    2 +\n drivers/staging/media/Makefile              |    1 +\n drivers/staging/media/rpivid/Kconfig        |   16 +\n drivers/staging/media/rpivid/Makefile       |    5 +\n drivers/staging/media/rpivid/rpivid.c       |  432 ++++\n drivers/staging/media/rpivid/rpivid.h       |  181 ++\n drivers/staging/media/rpivid/rpivid_dec.c   |   79 +\n drivers/staging/media/rpivid/rpivid_dec.h   |   19 +\n drivers/staging/media/rpivid/rpivid_h265.c  | 2275 +++++++++++++++++++\n drivers/staging/media/rpivid/rpivid_hw.c    |  321 +++\n drivers/staging/media/rpivid/rpivid_hw.h    |  300 +++\n drivers/staging/media/rpivid/rpivid_video.c |  593 +++++\n drivers/staging/media/rpivid/rpivid_video.h |   30 +\n 13 files changed, 4254 insertions(+)\n create mode 100644 drivers/staging/media/rpivid/Kconfig\n create mode 100644 drivers/staging/media/rpivid/Makefile\n create mode 100644 drivers/staging/media/rpivid/rpivid.c\n create mode 100644 drivers/staging/media/rpivid/rpivid.h\n create mode 100644 drivers/staging/media/rpivid/rpivid_dec.c\n create mode 100644 drivers/staging/media/rpivid/rpivid_dec.h\n create mode 100644 drivers/staging/media/rpivid/rpivid_h265.c\n create mode 100644 drivers/staging/media/rpivid/rpivid_hw.c\n create mode 100644 drivers/staging/media/rpivid/rpivid_hw.h\n create mode 100644 drivers/staging/media/rpivid/rpivid_video.c\n create mode 100644 drivers/staging/media/rpivid/rpivid_video.h\n\n--- a/drivers/staging/media/Kconfig\n+++ b/drivers/staging/media/Kconfig\n@@ -34,6 +34,8 @@ source \"drivers/staging/media/omap4iss/K\n \n source \"drivers/staging/media/rkvdec/Kconfig\"\n \n+source \"drivers/staging/media/rpivid/Kconfig\"\n+\n source \"drivers/staging/media/sunxi/Kconfig\"\n \n source \"drivers/staging/media/tegra-vde/Kconfig\"\n--- a/drivers/staging/media/Makefile\n+++ b/drivers/staging/media/Makefile\n@@ -5,6 +5,7 @@ obj-$(CONFIG_VIDEO_IMX_MEDIA)\t+= imx/\n obj-$(CONFIG_VIDEO_MESON_VDEC)\t+= meson/vdec/\n obj-$(CONFIG_VIDEO_OMAP4)\t+= omap4iss/\n obj-$(CONFIG_VIDEO_ROCKCHIP_VDEC)\t+= rkvdec/\n+obj-$(CONFIG_VIDEO_RPIVID)\t+= rpivid/\n obj-$(CONFIG_VIDEO_SUNXI)\t+= sunxi/\n obj-$(CONFIG_VIDEO_TEGRA)\t+= tegra-video/\n obj-$(CONFIG_TEGRA_VDE)\t\t+= tegra-vde/\n--- /dev/null\n+++ b/drivers/staging/media/rpivid/Kconfig\n@@ -0,0 +1,16 @@\n+# SPDX-License-Identifier: GPL-2.0\n+\n+config VIDEO_RPIVID\n+\ttristate \"Rpi H265 driver\"\n+\tdepends on VIDEO_DEV && VIDEO_V4L2\n+\tdepends on MEDIA_CONTROLLER\n+\tdepends on OF\n+\tdepends on MEDIA_CONTROLLER_REQUEST_API\n+\tselect VIDEOBUF2_DMA_CONTIG\n+\tselect V4L2_MEM2MEM_DEV\n+\thelp\n+\t  Support for the Rpi H265 h/w decoder.\n+\n+\t  To compile this driver as a module, choose M here: the module\n+\t  will be called rpivid-hevc.\n+\n--- /dev/null\n+++ b/drivers/staging/media/rpivid/Makefile\n@@ -0,0 +1,5 @@\n+# SPDX-License-Identifier: GPL-2.0\n+obj-$(CONFIG_VIDEO_RPIVID) += rpivid-hevc.o\n+\n+rpivid-hevc-y = rpivid.o rpivid_video.o rpivid_dec.o \\\n+\t\t rpivid_hw.o rpivid_h265.o\n--- /dev/null\n+++ b/drivers/staging/media/rpivid/rpivid.c\n@@ -0,0 +1,432 @@\n+// SPDX-License-Identifier: GPL-2.0\n+/*\n+ * Raspberry Pi HEVC driver\n+ *\n+ * Copyright (C) 2020 Raspberry Pi (Trading) Ltd\n+ *\n+ * Based on the Cedrus VPU driver, that is:\n+ *\n+ * Copyright (C) 2016 Florent Revest <florent.revest@free-electrons.com>\n+ * Copyright (C) 2018 Paul Kocialkowski <paul.kocialkowski@bootlin.com>\n+ * Copyright (C) 2018 Bootlin\n+ */\n+\n+#include <linux/platform_device.h>\n+#include <linux/module.h>\n+#include <linux/of.h>\n+\n+#include <media/v4l2-device.h>\n+#include <media/v4l2-ioctl.h>\n+#include <media/v4l2-ctrls.h>\n+#include <media/v4l2-mem2mem.h>\n+\n+#include \"rpivid.h\"\n+#include \"rpivid_video.h\"\n+#include \"rpivid_hw.h\"\n+#include \"rpivid_dec.h\"\n+\n+/*\n+ * Default /dev/videoN node number.\n+ * Deliberately avoid the very low numbers as these are often taken by webcams\n+ * etc, and simple apps tend to only go for /dev/video0.\n+ */\n+static int video_nr = 19;\n+module_param(video_nr, int, 0644);\n+MODULE_PARM_DESC(video_nr, \"decoder video device number\");\n+\n+static const struct rpivid_control rpivid_ctrls[] = {\n+\t{\n+\t\t.cfg = {\n+\t\t\t.id\t= V4L2_CID_MPEG_VIDEO_HEVC_SPS,\n+\t\t},\n+\t\t.required\t= true,\n+\t},\n+\t{\n+\t\t.cfg = {\n+\t\t\t.id\t= V4L2_CID_MPEG_VIDEO_HEVC_PPS,\n+\t\t},\n+\t\t.required\t= true,\n+\t},\n+\t{\n+\t\t.cfg = {\n+\t\t\t.id = V4L2_CID_MPEG_VIDEO_HEVC_SCALING_MATRIX,\n+\t\t},\n+\t\t.required\t= false,\n+\t},\n+\t{\n+\t\t.cfg = {\n+\t\t\t.id\t= V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS,\n+\t\t},\n+\t\t.required\t= true,\n+\t},\n+\t{\n+\t\t.cfg = {\n+\t\t\t.id\t= V4L2_CID_MPEG_VIDEO_HEVC_DECODE_MODE,\n+\t\t\t.max\t= V4L2_MPEG_VIDEO_HEVC_DECODE_MODE_SLICE_BASED,\n+\t\t\t.def\t= V4L2_MPEG_VIDEO_HEVC_DECODE_MODE_SLICE_BASED,\n+\t\t},\n+\t\t.required\t= false,\n+\t},\n+\t{\n+\t\t.cfg = {\n+\t\t\t.id\t= V4L2_CID_MPEG_VIDEO_HEVC_START_CODE,\n+\t\t\t.max\t= V4L2_MPEG_VIDEO_HEVC_START_CODE_NONE,\n+\t\t\t.def\t= V4L2_MPEG_VIDEO_HEVC_START_CODE_NONE,\n+\t\t},\n+\t\t.required\t= false,\n+\t},\n+};\n+\n+#define rpivid_ctrls_COUNT\tARRAY_SIZE(rpivid_ctrls)\n+\n+void *rpivid_find_control_data(struct rpivid_ctx *ctx, u32 id)\n+{\n+\tunsigned int i;\n+\n+\tfor (i = 0; ctx->ctrls[i]; i++)\n+\t\tif (ctx->ctrls[i]->id == id)\n+\t\t\treturn ctx->ctrls[i]->p_cur.p;\n+\n+\treturn NULL;\n+}\n+\n+static int rpivid_init_ctrls(struct rpivid_dev *dev, struct rpivid_ctx *ctx)\n+{\n+\tstruct v4l2_ctrl_handler *hdl = &ctx->hdl;\n+\tstruct v4l2_ctrl *ctrl;\n+\tunsigned int ctrl_size;\n+\tunsigned int i;\n+\n+\tv4l2_ctrl_handler_init(hdl, rpivid_ctrls_COUNT);\n+\tif (hdl->error) {\n+\t\tv4l2_err(&dev->v4l2_dev,\n+\t\t\t \"Failed to initialize control handler\\n\");\n+\t\treturn hdl->error;\n+\t}\n+\n+\tctrl_size = sizeof(ctrl) * rpivid_ctrls_COUNT + 1;\n+\n+\tctx->ctrls = kzalloc(ctrl_size, GFP_KERNEL);\n+\tif (!ctx->ctrls)\n+\t\treturn -ENOMEM;\n+\n+\tfor (i = 0; i < rpivid_ctrls_COUNT; i++) {\n+\t\tctrl = v4l2_ctrl_new_custom(hdl, &rpivid_ctrls[i].cfg,\n+\t\t\t\t\t    NULL);\n+\t\tif (hdl->error) {\n+\t\t\tv4l2_err(&dev->v4l2_dev,\n+\t\t\t\t \"Failed to create new custom control id=%#x\\n\",\n+\t\t\t\t rpivid_ctrls[i].cfg.id);\n+\n+\t\t\tv4l2_ctrl_handler_free(hdl);\n+\t\t\tkfree(ctx->ctrls);\n+\t\t\treturn hdl->error;\n+\t\t}\n+\n+\t\tctx->ctrls[i] = ctrl;\n+\t}\n+\n+\tctx->fh.ctrl_handler = hdl;\n+\tv4l2_ctrl_handler_setup(hdl);\n+\n+\treturn 0;\n+}\n+\n+static int rpivid_request_validate(struct media_request *req)\n+{\n+\tstruct media_request_object *obj;\n+\tstruct v4l2_ctrl_handler *parent_hdl, *hdl;\n+\tstruct rpivid_ctx *ctx = NULL;\n+\tstruct v4l2_ctrl *ctrl_test;\n+\tunsigned int count;\n+\tunsigned int i;\n+\n+\tlist_for_each_entry(obj, &req->objects, list) {\n+\t\tstruct vb2_buffer *vb;\n+\n+\t\tif (vb2_request_object_is_buffer(obj)) {\n+\t\t\tvb = container_of(obj, struct vb2_buffer, req_obj);\n+\t\t\tctx = vb2_get_drv_priv(vb->vb2_queue);\n+\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\n+\tif (!ctx)\n+\t\treturn -ENOENT;\n+\n+\tcount = vb2_request_buffer_cnt(req);\n+\tif (!count) {\n+\t\tv4l2_info(&ctx->dev->v4l2_dev,\n+\t\t\t  \"No buffer was provided with the request\\n\");\n+\t\treturn -ENOENT;\n+\t} else if (count > 1) {\n+\t\tv4l2_info(&ctx->dev->v4l2_dev,\n+\t\t\t  \"More than one buffer was provided with the request\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tparent_hdl = &ctx->hdl;\n+\n+\thdl = v4l2_ctrl_request_hdl_find(req, parent_hdl);\n+\tif (!hdl) {\n+\t\tv4l2_info(&ctx->dev->v4l2_dev, \"Missing codec control(s)\\n\");\n+\t\treturn -ENOENT;\n+\t}\n+\n+\tfor (i = 0; i < rpivid_ctrls_COUNT; i++) {\n+\t\tif (!rpivid_ctrls[i].required)\n+\t\t\tcontinue;\n+\n+\t\tctrl_test =\n+\t\t\tv4l2_ctrl_request_hdl_ctrl_find(hdl,\n+\t\t\t\t\t\t\trpivid_ctrls[i].cfg.id);\n+\t\tif (!ctrl_test) {\n+\t\t\tv4l2_info(&ctx->dev->v4l2_dev,\n+\t\t\t\t  \"Missing required codec control\\n\");\n+\t\t\treturn -ENOENT;\n+\t\t}\n+\t}\n+\n+\tv4l2_ctrl_request_hdl_put(hdl);\n+\n+\treturn vb2_request_validate(req);\n+}\n+\n+static int rpivid_open(struct file *file)\n+{\n+\tstruct rpivid_dev *dev = video_drvdata(file);\n+\tstruct rpivid_ctx *ctx = NULL;\n+\tint ret;\n+\n+\tif (mutex_lock_interruptible(&dev->dev_mutex))\n+\t\treturn -ERESTARTSYS;\n+\n+\tctx = kzalloc(sizeof(*ctx), GFP_KERNEL);\n+\tif (!ctx) {\n+\t\tmutex_unlock(&dev->dev_mutex);\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\tv4l2_fh_init(&ctx->fh, video_devdata(file));\n+\tfile->private_data = &ctx->fh;\n+\tctx->dev = dev;\n+\n+\tret = rpivid_init_ctrls(dev, ctx);\n+\tif (ret)\n+\t\tgoto err_free;\n+\n+\tctx->fh.m2m_ctx = v4l2_m2m_ctx_init(dev->m2m_dev, ctx,\n+\t\t\t\t\t    &rpivid_queue_init);\n+\tif (IS_ERR(ctx->fh.m2m_ctx)) {\n+\t\tret = PTR_ERR(ctx->fh.m2m_ctx);\n+\t\tgoto err_ctrls;\n+\t}\n+\n+\t/* The only bit of format info that we can guess now is H265 src\n+\t * Everything else we need more info for\n+\t */\n+\tctx->src_fmt.pixelformat = RPIVID_SRC_PIXELFORMAT_DEFAULT;\n+\trpivid_prepare_src_format(&ctx->src_fmt);\n+\n+\tv4l2_fh_add(&ctx->fh);\n+\n+\tmutex_unlock(&dev->dev_mutex);\n+\n+\treturn 0;\n+\n+err_ctrls:\n+\tv4l2_ctrl_handler_free(&ctx->hdl);\n+err_free:\n+\tkfree(ctx);\n+\tmutex_unlock(&dev->dev_mutex);\n+\n+\treturn ret;\n+}\n+\n+static int rpivid_release(struct file *file)\n+{\n+\tstruct rpivid_dev *dev = video_drvdata(file);\n+\tstruct rpivid_ctx *ctx = container_of(file->private_data,\n+\t\t\t\t\t      struct rpivid_ctx, fh);\n+\n+\tmutex_lock(&dev->dev_mutex);\n+\n+\tv4l2_fh_del(&ctx->fh);\n+\tv4l2_m2m_ctx_release(ctx->fh.m2m_ctx);\n+\n+\tv4l2_ctrl_handler_free(&ctx->hdl);\n+\tkfree(ctx->ctrls);\n+\n+\tv4l2_fh_exit(&ctx->fh);\n+\n+\tkfree(ctx);\n+\n+\tmutex_unlock(&dev->dev_mutex);\n+\n+\treturn 0;\n+}\n+\n+static const struct v4l2_file_operations rpivid_fops = {\n+\t.owner\t\t= THIS_MODULE,\n+\t.open\t\t= rpivid_open,\n+\t.release\t= rpivid_release,\n+\t.poll\t\t= v4l2_m2m_fop_poll,\n+\t.unlocked_ioctl\t= video_ioctl2,\n+\t.mmap\t\t= v4l2_m2m_fop_mmap,\n+};\n+\n+static const struct video_device rpivid_video_device = {\n+\t.name\t\t= RPIVID_NAME,\n+\t.vfl_dir\t= VFL_DIR_M2M,\n+\t.fops\t\t= &rpivid_fops,\n+\t.ioctl_ops\t= &rpivid_ioctl_ops,\n+\t.minor\t\t= -1,\n+\t.release\t= video_device_release_empty,\n+\t.device_caps\t= V4L2_CAP_VIDEO_M2M | V4L2_CAP_STREAMING,\n+};\n+\n+static const struct v4l2_m2m_ops rpivid_m2m_ops = {\n+\t.device_run\t= rpivid_device_run,\n+};\n+\n+static const struct media_device_ops rpivid_m2m_media_ops = {\n+\t.req_validate\t= rpivid_request_validate,\n+\t.req_queue\t= v4l2_m2m_request_queue,\n+};\n+\n+static int rpivid_probe(struct platform_device *pdev)\n+{\n+\tstruct rpivid_dev *dev;\n+\tstruct video_device *vfd;\n+\tint ret;\n+\n+\tdev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);\n+\tif (!dev)\n+\t\treturn -ENOMEM;\n+\n+\tdev->vfd = rpivid_video_device;\n+\tdev->dev = &pdev->dev;\n+\tdev->pdev = pdev;\n+\n+\tret = 0;\n+\tret = rpivid_hw_probe(dev);\n+\tif (ret) {\n+\t\tdev_err(&pdev->dev, \"Failed to probe hardware\\n\");\n+\t\treturn ret;\n+\t}\n+\n+\tdev->dec_ops = &rpivid_dec_ops_h265;\n+\n+\tmutex_init(&dev->dev_mutex);\n+\n+\tret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev);\n+\tif (ret) {\n+\t\tdev_err(&pdev->dev, \"Failed to register V4L2 device\\n\");\n+\t\treturn ret;\n+\t}\n+\n+\tvfd = &dev->vfd;\n+\tvfd->lock = &dev->dev_mutex;\n+\tvfd->v4l2_dev = &dev->v4l2_dev;\n+\n+\tsnprintf(vfd->name, sizeof(vfd->name), \"%s\", rpivid_video_device.name);\n+\tvideo_set_drvdata(vfd, dev);\n+\n+\tdev->m2m_dev = v4l2_m2m_init(&rpivid_m2m_ops);\n+\tif (IS_ERR(dev->m2m_dev)) {\n+\t\tv4l2_err(&dev->v4l2_dev,\n+\t\t\t \"Failed to initialize V4L2 M2M device\\n\");\n+\t\tret = PTR_ERR(dev->m2m_dev);\n+\n+\t\tgoto err_v4l2;\n+\t}\n+\n+\tdev->mdev.dev = &pdev->dev;\n+\tstrscpy(dev->mdev.model, RPIVID_NAME, sizeof(dev->mdev.model));\n+\tstrscpy(dev->mdev.bus_info, \"platform:\" RPIVID_NAME,\n+\t\tsizeof(dev->mdev.bus_info));\n+\n+\tmedia_device_init(&dev->mdev);\n+\tdev->mdev.ops = &rpivid_m2m_media_ops;\n+\tdev->v4l2_dev.mdev = &dev->mdev;\n+\n+\tret = video_register_device(vfd, VFL_TYPE_VIDEO, video_nr);\n+\tif (ret) {\n+\t\tv4l2_err(&dev->v4l2_dev, \"Failed to register video device\\n\");\n+\t\tgoto err_m2m;\n+\t}\n+\n+\tv4l2_info(&dev->v4l2_dev,\n+\t\t  \"Device registered as /dev/video%d\\n\", vfd->num);\n+\n+\tret = v4l2_m2m_register_media_controller(dev->m2m_dev, vfd,\n+\t\t\t\t\t\t MEDIA_ENT_F_PROC_VIDEO_DECODER);\n+\tif (ret) {\n+\t\tv4l2_err(&dev->v4l2_dev,\n+\t\t\t \"Failed to initialize V4L2 M2M media controller\\n\");\n+\t\tgoto err_video;\n+\t}\n+\n+\tret = media_device_register(&dev->mdev);\n+\tif (ret) {\n+\t\tv4l2_err(&dev->v4l2_dev, \"Failed to register media device\\n\");\n+\t\tgoto err_m2m_mc;\n+\t}\n+\n+\tplatform_set_drvdata(pdev, dev);\n+\n+\treturn 0;\n+\n+err_m2m_mc:\n+\tv4l2_m2m_unregister_media_controller(dev->m2m_dev);\n+err_video:\n+\tvideo_unregister_device(&dev->vfd);\n+err_m2m:\n+\tv4l2_m2m_release(dev->m2m_dev);\n+err_v4l2:\n+\tv4l2_device_unregister(&dev->v4l2_dev);\n+\n+\treturn ret;\n+}\n+\n+static int rpivid_remove(struct platform_device *pdev)\n+{\n+\tstruct rpivid_dev *dev = platform_get_drvdata(pdev);\n+\n+\tif (media_devnode_is_registered(dev->mdev.devnode)) {\n+\t\tmedia_device_unregister(&dev->mdev);\n+\t\tv4l2_m2m_unregister_media_controller(dev->m2m_dev);\n+\t\tmedia_device_cleanup(&dev->mdev);\n+\t}\n+\n+\tv4l2_m2m_release(dev->m2m_dev);\n+\tvideo_unregister_device(&dev->vfd);\n+\tv4l2_device_unregister(&dev->v4l2_dev);\n+\n+\trpivid_hw_remove(dev);\n+\n+\treturn 0;\n+}\n+\n+static const struct of_device_id rpivid_dt_match[] = {\n+\t{\n+\t\t.compatible = \"raspberrypi,rpivid-vid-decoder\",\n+\t},\n+\t{ /* sentinel */ }\n+};\n+MODULE_DEVICE_TABLE(of, rpivid_dt_match);\n+\n+static struct platform_driver rpivid_driver = {\n+\t.probe\t\t= rpivid_probe,\n+\t.remove\t\t= rpivid_remove,\n+\t.driver\t\t= {\n+\t\t.name = RPIVID_NAME,\n+\t\t.of_match_table\t= of_match_ptr(rpivid_dt_match),\n+\t},\n+};\n+module_platform_driver(rpivid_driver);\n+\n+MODULE_LICENSE(\"GPL v2\");\n+MODULE_AUTHOR(\"John Cox <jc@kynesim.co.uk>\");\n+MODULE_DESCRIPTION(\"Raspberry Pi HEVC V4L2 driver\");\n--- /dev/null\n+++ b/drivers/staging/media/rpivid/rpivid.h\n@@ -0,0 +1,181 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+/*\n+ * Raspberry Pi HEVC driver\n+ *\n+ * Copyright (C) 2020 Raspberry Pi (Trading) Ltd\n+ *\n+ * Based on the Cedrus VPU driver, that is:\n+ *\n+ * Copyright (C) 2016 Florent Revest <florent.revest@free-electrons.com>\n+ * Copyright (C) 2018 Paul Kocialkowski <paul.kocialkowski@bootlin.com>\n+ * Copyright (C) 2018 Bootlin\n+ */\n+\n+#ifndef _RPIVID_H_\n+#define _RPIVID_H_\n+\n+#include <linux/clk.h>\n+#include <linux/platform_device.h>\n+#include <media/v4l2-ctrls.h>\n+#include <media/v4l2-device.h>\n+#include <media/v4l2-mem2mem.h>\n+#include <media/videobuf2-v4l2.h>\n+#include <media/videobuf2-dma-contig.h>\n+\n+#define OPT_DEBUG_POLL_IRQ  0\n+\n+#define RPIVID_NAME\t\t\t\"rpivid\"\n+\n+#define RPIVID_CAPABILITY_UNTILED\tBIT(0)\n+#define RPIVID_CAPABILITY_H265_DEC\tBIT(1)\n+\n+#define RPIVID_QUIRK_NO_DMA_OFFSET\tBIT(0)\n+\n+#define RPIVID_SRC_PIXELFORMAT_DEFAULT\tV4L2_PIX_FMT_HEVC_SLICE\n+\n+enum rpivid_irq_status {\n+\tRPIVID_IRQ_NONE,\n+\tRPIVID_IRQ_ERROR,\n+\tRPIVID_IRQ_OK,\n+};\n+\n+struct rpivid_control {\n+\tstruct v4l2_ctrl_config cfg;\n+\tunsigned char\t\trequired:1;\n+};\n+\n+struct rpivid_h265_run {\n+\tconst struct v4l2_ctrl_hevc_sps\t\t\t*sps;\n+\tconst struct v4l2_ctrl_hevc_pps\t\t\t*pps;\n+\tconst struct v4l2_ctrl_hevc_slice_params\t*slice_params;\n+\tconst struct v4l2_ctrl_hevc_scaling_matrix\t*scaling_matrix;\n+};\n+\n+struct rpivid_run {\n+\tstruct vb2_v4l2_buffer\t*src;\n+\tstruct vb2_v4l2_buffer\t*dst;\n+\n+\tstruct rpivid_h265_run\th265;\n+};\n+\n+struct rpivid_buffer {\n+\tstruct v4l2_m2m_buffer          m2m_buf;\n+};\n+\n+struct rpivid_dec_state;\n+struct rpivid_dec_env;\n+#define RPIVID_DEC_ENV_COUNT 3\n+\n+struct rpivid_gptr {\n+\tsize_t size;\n+\t__u8 *ptr;\n+\tdma_addr_t addr;\n+\tunsigned long attrs;\n+};\n+\n+struct rpivid_dev;\n+typedef void (*rpivid_irq_callback)(struct rpivid_dev *dev, void *ctx);\n+\n+struct rpivid_q_aux;\n+#define RPIVID_AUX_ENT_COUNT VB2_MAX_FRAME\n+\n+#define RPIVID_P2BUF_COUNT 2\n+\n+struct rpivid_ctx {\n+\tstruct v4l2_fh\t\t\tfh;\n+\tstruct rpivid_dev\t\t*dev;\n+\n+\tstruct v4l2_pix_format\t\tsrc_fmt;\n+\tstruct v4l2_pix_format\t\tdst_fmt;\n+\tint dst_fmt_set;\n+\n+\tstruct v4l2_ctrl_handler\thdl;\n+\tstruct v4l2_ctrl\t\t**ctrls;\n+\n+\t/* Decode state - stateless decoder my *** */\n+\t/* state contains stuff that is only needed in phase0\n+\t * it could be held in dec_env but that would be wasteful\n+\t */\n+\tstruct rpivid_dec_state *state;\n+\tstruct rpivid_dec_env *dec0;\n+\n+\t/* Spinlock protecting dec_free */\n+\tspinlock_t dec_lock;\n+\tstruct rpivid_dec_env *dec_free;\n+\n+\tstruct rpivid_dec_env *dec_pool;\n+\n+\t/* Some of these should be in dev */\n+\tstruct rpivid_gptr bitbufs[1];  /* Will be 2 */\n+\tstruct rpivid_gptr cmdbufs[1];  /* Will be 2 */\n+\tunsigned int p2idx;\n+\tatomic_t p2out;\n+\tstruct rpivid_gptr pu_bufs[RPIVID_P2BUF_COUNT];\n+\tstruct rpivid_gptr coeff_bufs[RPIVID_P2BUF_COUNT];\n+\n+\t/* Spinlock protecting aux_free */\n+\tspinlock_t aux_lock;\n+\tstruct rpivid_q_aux *aux_free;\n+\n+\tstruct rpivid_q_aux *aux_ents[RPIVID_AUX_ENT_COUNT];\n+\n+\tunsigned int colmv_stride;\n+\tunsigned int colmv_picsize;\n+};\n+\n+struct rpivid_dec_ops {\n+\tvoid (*setup)(struct rpivid_ctx *ctx, struct rpivid_run *run);\n+\tint (*start)(struct rpivid_ctx *ctx);\n+\tvoid (*stop)(struct rpivid_ctx *ctx);\n+\tvoid (*trigger)(struct rpivid_ctx *ctx);\n+};\n+\n+struct rpivid_variant {\n+\tunsigned int\tcapabilities;\n+\tunsigned int\tquirks;\n+\tunsigned int\tmod_rate;\n+};\n+\n+struct rpivid_hw_irq_ent;\n+\n+struct rpivid_hw_irq_ctrl {\n+\t/* Spinlock protecting claim and tail */\n+\tspinlock_t lock;\n+\tstruct rpivid_hw_irq_ent *claim;\n+\tstruct rpivid_hw_irq_ent *tail;\n+\n+\t/* Ent for pending irq - also prevents sched */\n+\tstruct rpivid_hw_irq_ent *irq;\n+\t/* Non-zero => do not start a new job - outer layer sched pending */\n+\tint no_sched;\n+\t/* Thread CB requested */\n+\tbool thread_reqed;\n+};\n+\n+struct rpivid_dev {\n+\tstruct v4l2_device\tv4l2_dev;\n+\tstruct video_device\tvfd;\n+\tstruct media_device\tmdev;\n+\tstruct media_pad\tpad[2];\n+\tstruct platform_device\t*pdev;\n+\tstruct device\t\t*dev;\n+\tstruct v4l2_m2m_dev\t*m2m_dev;\n+\tstruct rpivid_dec_ops\t*dec_ops;\n+\n+\t/* Device file mutex */\n+\tstruct mutex\t\tdev_mutex;\n+\n+\tvoid __iomem\t\t*base_irq;\n+\tvoid __iomem\t\t*base_h265;\n+\n+\tstruct clk\t\t*clock;\n+\n+\tstruct rpivid_hw_irq_ctrl ic_active1;\n+\tstruct rpivid_hw_irq_ctrl ic_active2;\n+};\n+\n+extern struct rpivid_dec_ops rpivid_dec_ops_h265;\n+\n+void *rpivid_find_control_data(struct rpivid_ctx *ctx, u32 id);\n+\n+#endif\n--- /dev/null\n+++ b/drivers/staging/media/rpivid/rpivid_dec.c\n@@ -0,0 +1,79 @@\n+// SPDX-License-Identifier: GPL-2.0\n+/*\n+ * Raspberry Pi HEVC driver\n+ *\n+ * Copyright (C) 2020 Raspberry Pi (Trading) Ltd\n+ *\n+ * Based on the Cedrus VPU driver, that is:\n+ *\n+ * Copyright (C) 2016 Florent Revest <florent.revest@free-electrons.com>\n+ * Copyright (C) 2018 Paul Kocialkowski <paul.kocialkowski@bootlin.com>\n+ * Copyright (C) 2018 Bootlin\n+ */\n+\n+#include <media/v4l2-device.h>\n+#include <media/v4l2-ioctl.h>\n+#include <media/v4l2-event.h>\n+#include <media/v4l2-mem2mem.h>\n+\n+#include \"rpivid.h\"\n+#include \"rpivid_dec.h\"\n+\n+void rpivid_device_run(void *priv)\n+{\n+\tstruct rpivid_ctx *ctx = priv;\n+\tstruct rpivid_dev *dev = ctx->dev;\n+\tstruct rpivid_run run = {};\n+\tstruct media_request *src_req;\n+\n+\trun.src = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);\n+\trun.dst = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);\n+\n+\tif (!run.src || !run.dst) {\n+\t\tv4l2_err(&dev->v4l2_dev, \"%s: Missing buffer: src=%p, dst=%p\\n\",\n+\t\t\t __func__, run.src, run.dst);\n+\t\t/* We are stuffed - this probably won't dig us out of our\n+\t\t * current situation but it is better than nothing\n+\t\t */\n+\t\tv4l2_m2m_buf_done_and_job_finish(dev->m2m_dev, ctx->fh.m2m_ctx,\n+\t\t\t\t\t\t VB2_BUF_STATE_ERROR);\n+\t\treturn;\n+\t}\n+\n+\t/* Apply request(s) controls if needed. */\n+\tsrc_req = run.src->vb2_buf.req_obj.req;\n+\n+\tif (src_req)\n+\t\tv4l2_ctrl_request_setup(src_req, &ctx->hdl);\n+\n+\tswitch (ctx->src_fmt.pixelformat) {\n+\tcase V4L2_PIX_FMT_HEVC_SLICE:\n+\t\trun.h265.sps =\n+\t\t\trpivid_find_control_data(ctx,\n+\t\t\t\t\t\t V4L2_CID_MPEG_VIDEO_HEVC_SPS);\n+\t\trun.h265.pps =\n+\t\t\trpivid_find_control_data(ctx,\n+\t\t\t\t\t\t V4L2_CID_MPEG_VIDEO_HEVC_PPS);\n+\t\trun.h265.slice_params =\n+\t\t\trpivid_find_control_data(ctx,\n+\t\t\t\t\t\t V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS);\n+\t\trun.h265.scaling_matrix =\n+\t\t\trpivid_find_control_data(ctx,\n+\t\t\t\t\t\t V4L2_CID_MPEG_VIDEO_HEVC_SCALING_MATRIX);\n+\t\tbreak;\n+\n+\tdefault:\n+\t\tbreak;\n+\t}\n+\n+\tv4l2_m2m_buf_copy_metadata(run.src, run.dst, true);\n+\n+\tdev->dec_ops->setup(ctx, &run);\n+\n+\t/* Complete request(s) controls if needed. */\n+\n+\tif (src_req)\n+\t\tv4l2_ctrl_request_complete(src_req, &ctx->hdl);\n+\n+\tdev->dec_ops->trigger(ctx);\n+}\n--- /dev/null\n+++ b/drivers/staging/media/rpivid/rpivid_dec.h\n@@ -0,0 +1,19 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+/*\n+ * Raspberry Pi HEVC driver\n+ *\n+ * Copyright (C) 2020 Raspberry Pi (Trading) Ltd\n+ *\n+ * Based on the Cedrus VPU driver, that is:\n+ *\n+ * Copyright (C) 2016 Florent Revest <florent.revest@free-electrons.com>\n+ * Copyright (C) 2018 Paul Kocialkowski <paul.kocialkowski@bootlin.com>\n+ * Copyright (C) 2018 Bootlin\n+ */\n+\n+#ifndef _RPIVID_DEC_H_\n+#define _RPIVID_DEC_H_\n+\n+void rpivid_device_run(void *priv);\n+\n+#endif\n--- /dev/null\n+++ b/drivers/staging/media/rpivid/rpivid_h265.c\n@@ -0,0 +1,2275 @@\n+// SPDX-License-Identifier: GPL-2.0-or-later\n+/*\n+ * Raspberry Pi HEVC driver\n+ *\n+ * Copyright (C) 2020 Raspberry Pi (Trading) Ltd\n+ *\n+ * Based on the Cedrus VPU driver, that is:\n+ *\n+ * Copyright (C) 2016 Florent Revest <florent.revest@free-electrons.com>\n+ * Copyright (C) 2018 Paul Kocialkowski <paul.kocialkowski@bootlin.com>\n+ * Copyright (C) 2018 Bootlin\n+ */\n+\n+#include <linux/delay.h>\n+#include <linux/types.h>\n+\n+#include <media/videobuf2-dma-contig.h>\n+\n+#include \"rpivid.h\"\n+#include \"rpivid_hw.h\"\n+\n+#define DEBUG_TRACE_P1_CMD 0\n+#define DEBUG_TRACE_EXECUTION 0\n+\n+#if DEBUG_TRACE_EXECUTION\n+#define xtrace_in(dev_, de_)\\\n+\tv4l2_info(&(dev_)->v4l2_dev, \"%s[%d]: in\\n\",   __func__,\\\n+\t\t  (de_) == NULL ? -1 : (de_)->decode_order)\n+#define xtrace_ok(dev_, de_)\\\n+\tv4l2_info(&(dev_)->v4l2_dev, \"%s[%d]: ok\\n\",   __func__,\\\n+\t\t  (de_) == NULL ? -1 : (de_)->decode_order)\n+#define xtrace_fin(dev_, de_)\\\n+\tv4l2_info(&(dev_)->v4l2_dev, \"%s[%d]: finish\\n\", __func__,\\\n+\t\t  (de_) == NULL ? -1 : (de_)->decode_order)\n+#define xtrace_fail(dev_, de_)\\\n+\tv4l2_info(&(dev_)->v4l2_dev, \"%s[%d]: FAIL\\n\", __func__,\\\n+\t\t  (de_) == NULL ? -1 : (de_)->decode_order)\n+#else\n+#define xtrace_in(dev_, de_)\n+#define xtrace_ok(dev_, de_)\n+#define xtrace_fin(dev_, de_)\n+#define xtrace_fail(dev_, de_)\n+#endif\n+\n+enum hevc_slice_type {\n+\tHEVC_SLICE_B = 0,\n+\tHEVC_SLICE_P = 1,\n+\tHEVC_SLICE_I = 2,\n+};\n+\n+enum hevc_layer { L0 = 0, L1 = 1 };\n+\n+static int gptr_alloc(struct rpivid_dev *const dev, struct rpivid_gptr *gptr,\n+\t\t      size_t size, unsigned long attrs)\n+{\n+\tgptr->size = size;\n+\tgptr->attrs = attrs;\n+\tgptr->addr = 0;\n+\tgptr->ptr = dma_alloc_attrs(dev->dev, gptr->size, &gptr->addr,\n+\t\t\t\t    GFP_KERNEL, gptr->attrs);\n+\treturn !gptr->ptr ? -ENOMEM : 0;\n+}\n+\n+static void gptr_free(struct rpivid_dev *const dev,\n+\t\t      struct rpivid_gptr *const gptr)\n+{\n+\tif (gptr->ptr)\n+\t\tdma_free_attrs(dev->dev, gptr->size, gptr->ptr, gptr->addr,\n+\t\t\t       gptr->attrs);\n+\tgptr->size = 0;\n+\tgptr->ptr = NULL;\n+\tgptr->addr = 0;\n+\tgptr->attrs = 0;\n+}\n+\n+/* Realloc but do not copy */\n+static int gptr_realloc_new(struct rpivid_dev * const dev,\n+\t\t\t    struct rpivid_gptr * const gptr, size_t size)\n+{\n+\tif (size == gptr->size)\n+\t\treturn 0;\n+\n+\tif (gptr->ptr)\n+\t\tdma_free_attrs(dev->dev, gptr->size, gptr->ptr,\n+\t\t\t       gptr->addr, gptr->attrs);\n+\n+\tgptr->addr = 0;\n+\tgptr->size = size;\n+\tgptr->ptr = dma_alloc_attrs(dev->dev, gptr->size,\n+\t\t\t\t    &gptr->addr, GFP_KERNEL, gptr->attrs);\n+\treturn gptr->ptr ? 0 : -ENOMEM;\n+}\n+\n+/* floor(log2(x)) */\n+static unsigned int log2_size(size_t x)\n+{\n+\tunsigned int n = 0;\n+\n+\tif (x & ~0xffff) {\n+\t\tn += 16;\n+\t\tx >>= 16;\n+\t}\n+\tif (x & ~0xff) {\n+\t\tn += 8;\n+\t\tx >>= 8;\n+\t}\n+\tif (x & ~0xf) {\n+\t\tn += 4;\n+\t\tx >>= 4;\n+\t}\n+\tif (x & ~3) {\n+\t\tn += 2;\n+\t\tx >>= 2;\n+\t}\n+\treturn (x & ~1) ? n + 1 : n;\n+}\n+\n+static size_t round_up_size(const size_t x)\n+{\n+\t/* Admit no size < 256 */\n+\tconst unsigned int n = x < 256 ? 8 : log2_size(x) - 1;\n+\n+\treturn x >= (3 << n) ? 4 << n : (3 << n);\n+}\n+\n+static size_t next_size(const size_t x)\n+{\n+\treturn round_up_size(x + 1);\n+}\n+\n+#define NUM_SCALING_FACTORS 4064 /* Not a typo = 0xbe0 + 0x400 */\n+\n+#define AXI_BASE64 0\n+\n+#define PROB_BACKUP ((20 << 12) + (20 << 6) + (0 << 0))\n+#define PROB_RELOAD ((20 << 12) + (20 << 0) + (0 << 6))\n+\n+#define HEVC_MAX_REFS V4L2_HEVC_DPB_ENTRIES_NUM_MAX\n+\n+//////////////////////////////////////////////////////////////////////////////\n+\n+struct rpi_cmd {\n+\tu32 addr;\n+\tu32 data;\n+} __packed;\n+\n+struct rpivid_q_aux {\n+\tunsigned int refcount;\n+\tunsigned int q_index;\n+\tstruct rpivid_q_aux *next;\n+\tstruct rpivid_gptr col;\n+};\n+\n+//////////////////////////////////////////////////////////////////////////////\n+\n+enum rpivid_decode_state {\n+\tRPIVID_DECODE_SLICE_START,\n+\tRPIVID_DECODE_SLICE_CONTINUE,\n+\tRPIVID_DECODE_ERROR_CONTINUE,\n+\tRPIVID_DECODE_ERROR_DONE,\n+\tRPIVID_DECODE_PHASE1,\n+\tRPIVID_DECODE_END,\n+};\n+\n+struct rpivid_dec_env {\n+\tstruct rpivid_ctx *ctx;\n+\tstruct rpivid_dec_env *next;\n+\n+\tenum rpivid_decode_state state;\n+\tunsigned int decode_order;\n+\tint p1_status;\t\t/* P1 status - what to realloc */\n+\n+\tstruct rpivid_dec_env *phase_wait_q_next;\n+\n+\tstruct rpi_cmd *cmd_fifo;\n+\tunsigned int cmd_len, cmd_max;\n+\tunsigned int num_slice_msgs;\n+\tunsigned int pic_width_in_ctbs_y;\n+\tunsigned int pic_height_in_ctbs_y;\n+\tunsigned int dpbno_col;\n+\tu32 reg_slicestart;\n+\tint collocated_from_l0_flag;\n+\tunsigned int wpp_entry_x;\n+\tunsigned int wpp_entry_y;\n+\n+\tu32 rpi_config2;\n+\tu32 rpi_framesize;\n+\tu32 rpi_currpoc;\n+\n+\tstruct vb2_v4l2_buffer *frame_buf; // Detached dest buffer\n+\tunsigned int frame_c_offset;\n+\tunsigned int frame_stride;\n+\tdma_addr_t frame_addr;\n+\tdma_addr_t ref_addrs[16];\n+\tstruct rpivid_q_aux *frame_aux;\n+\tstruct rpivid_q_aux *col_aux;\n+\n+\tdma_addr_t pu_base_vc;\n+\tdma_addr_t coeff_base_vc;\n+\tu32 pu_stride;\n+\tu32 coeff_stride;\n+\n+\tstruct rpivid_gptr *bit_copy_gptr;\n+\tsize_t bit_copy_len;\n+\tstruct rpivid_gptr *cmd_copy_gptr;\n+\n+\tu16 slice_msgs[2 * HEVC_MAX_REFS * 8 + 3];\n+\tu8 scaling_factors[NUM_SCALING_FACTORS];\n+\n+\tstruct rpivid_hw_irq_ent irq_ent;\n+};\n+\n+#define member_size(type, member) sizeof(((type *)0)->member)\n+\n+struct rpivid_dec_state {\n+\tstruct v4l2_ctrl_hevc_sps sps;\n+\tstruct v4l2_ctrl_hevc_pps pps;\n+\n+\t// Helper vars & tables derived from sps/pps\n+\tunsigned int log2_ctb_size; /* log2 width of a CTB */\n+\tunsigned int ctb_width; /* Width in CTBs */\n+\tunsigned int ctb_height; /* Height in CTBs */\n+\tunsigned int ctb_size; /* Pic area in CTBs */\n+\tunsigned int num_tile_columns;\n+\tunsigned int num_tile_rows;\n+\tu8 column_width[member_size(struct v4l2_ctrl_hevc_pps,\n+\t\t\t\t    column_width_minus1)];\n+\tu8 row_height[member_size(struct v4l2_ctrl_hevc_pps,\n+\t\t\t\t  row_height_minus1)];\n+\n+\tint *col_bd;\n+\tint *row_bd;\n+\tint *ctb_addr_rs_to_ts;\n+\tint *ctb_addr_ts_to_rs;\n+\tint *tile_id;\n+\n+\t// Aux starage for DPB\n+\t// Hold refs\n+\tstruct rpivid_q_aux *ref_aux[HEVC_MAX_REFS];\n+\tstruct rpivid_q_aux *frame_aux;\n+\n+\t// Slice vars\n+\tunsigned int slice_idx;\n+\tbool frame_end;\n+\tbool slice_temporal_mvp;  /* Slice flag but constant for frame */\n+\n+\t// Temp vars per run - don't actually need to persist\n+\tu8 *src_buf;\n+\tdma_addr_t src_addr;\n+\tconst struct v4l2_ctrl_hevc_slice_params *sh;\n+\tunsigned int nb_refs[2];\n+\tunsigned int slice_qp;\n+\tunsigned int max_num_merge_cand; // 0 if I-slice\n+\tbool dependent_slice_segment_flag;\n+};\n+\n+static inline int clip_int(const int x, const int lo, const int hi)\n+{\n+\treturn x < lo ? lo : x > hi ? hi : x;\n+}\n+\n+//////////////////////////////////////////////////////////////////////////////\n+// Phase 1 command and bit FIFOs\n+\n+#if DEBUG_TRACE_P1_CMD\n+static int p1_z;\n+#endif\n+\n+// ???? u16 addr - put in u32\n+static int p1_apb_write(struct rpivid_dec_env *const de, const u16 addr,\n+\t\t\tconst u32 data)\n+{\n+\tif (de->cmd_len == de->cmd_max)\n+\t\tde->cmd_fifo =\n+\t\t\tkrealloc(de->cmd_fifo,\n+\t\t\t\t (de->cmd_max *= 2) * sizeof(struct rpi_cmd),\n+\t\t\t\t GFP_KERNEL);\n+\tde->cmd_fifo[de->cmd_len].addr = addr;\n+\tde->cmd_fifo[de->cmd_len].data = data;\n+\n+#if DEBUG_TRACE_P1_CMD\n+\tif (++p1_z < 256) {\n+\t\tv4l2_info(&de->ctx->dev->v4l2_dev, \"[%02x] %x %x\\n\",\n+\t\t\t  de->cmd_len, addr, data);\n+\t}\n+#endif\n+\n+\treturn de->cmd_len++;\n+}\n+\n+static int ctb_to_tile(unsigned int ctb, unsigned int *bd, int num)\n+{\n+\tint i;\n+\n+\tfor (i = 1; ctb >= bd[i]; i++)\n+\t\t; // bd[] has num+1 elements; bd[0]=0;\n+\treturn i - 1;\n+}\n+\n+static int ctb_to_slice_w_h(unsigned int ctb, int ctb_size, int width,\n+\t\t\t    unsigned int *bd, int num)\n+{\n+\tif (ctb < bd[num - 1])\n+\t\treturn ctb_size;\n+\telse if (width % ctb_size)\n+\t\treturn width % ctb_size;\n+\telse\n+\t\treturn ctb_size;\n+}\n+\n+static void aux_q_free(struct rpivid_ctx *const ctx,\n+\t\t       struct rpivid_q_aux *const aq)\n+{\n+\tstruct rpivid_dev *const dev = ctx->dev;\n+\n+\tgptr_free(dev, &aq->col);\n+\tkfree(aq);\n+}\n+\n+static struct rpivid_q_aux *aux_q_alloc(struct rpivid_ctx *const ctx)\n+{\n+\tstruct rpivid_dev *const dev = ctx->dev;\n+\tstruct rpivid_q_aux *const aq = kzalloc(sizeof(*aq), GFP_KERNEL);\n+\n+\tif (!aq)\n+\t\treturn NULL;\n+\n+\taq->refcount = 1;\n+\tif (gptr_alloc(dev, &aq->col, ctx->colmv_picsize,\n+\t\t       DMA_ATTR_FORCE_CONTIGUOUS | DMA_ATTR_NO_KERNEL_MAPPING))\n+\t\tgoto fail;\n+\n+\treturn aq;\n+\n+fail:\n+\tkfree(aq);\n+\treturn NULL;\n+}\n+\n+static struct rpivid_q_aux *aux_q_new(struct rpivid_ctx *const ctx,\n+\t\t\t\t      const unsigned int q_index)\n+{\n+\tstruct rpivid_q_aux *aq;\n+\tunsigned long lockflags;\n+\n+\tspin_lock_irqsave(&ctx->aux_lock, lockflags);\n+\taq = ctx->aux_free;\n+\tif (aq) {\n+\t\tctx->aux_free = aq->next;\n+\t\taq->next = NULL;\n+\t\taq->refcount = 1;\n+\t}\n+\tspin_unlock_irqrestore(&ctx->aux_lock, lockflags);\n+\n+\tif (!aq) {\n+\t\taq = aux_q_alloc(ctx);\n+\t\tif (!aq)\n+\t\t\treturn NULL;\n+\t}\n+\n+\taq->q_index = q_index;\n+\tctx->aux_ents[q_index] = aq;\n+\treturn aq;\n+}\n+\n+static struct rpivid_q_aux *aux_q_ref(struct rpivid_ctx *const ctx,\n+\t\t\t\t      struct rpivid_q_aux *const aq)\n+{\n+\tif (aq) {\n+\t\tunsigned long lockflags;\n+\n+\t\tspin_lock_irqsave(&ctx->aux_lock, lockflags);\n+\n+\t\t++aq->refcount;\n+\n+\t\tspin_unlock_irqrestore(&ctx->aux_lock, lockflags);\n+\t}\n+\treturn aq;\n+}\n+\n+static void aux_q_release(struct rpivid_ctx *const ctx,\n+\t\t\t  struct rpivid_q_aux **const paq)\n+{\n+\tstruct rpivid_q_aux *const aq = *paq;\n+\t*paq = NULL;\n+\n+\tif (aq) {\n+\t\tunsigned long lockflags;\n+\n+\t\tspin_lock_irqsave(&ctx->aux_lock, lockflags);\n+\n+\t\tif (--aq->refcount == 0) {\n+\t\t\taq->next = ctx->aux_free;\n+\t\t\tctx->aux_free = aq;\n+\t\t\tctx->aux_ents[aq->q_index] = NULL;\n+\t\t}\n+\n+\t\tspin_unlock_irqrestore(&ctx->aux_lock, lockflags);\n+\t}\n+}\n+\n+static void aux_q_init(struct rpivid_ctx *const ctx)\n+{\n+\tspin_lock_init(&ctx->aux_lock);\n+\tctx->aux_free = NULL;\n+}\n+\n+static void aux_q_uninit(struct rpivid_ctx *const ctx)\n+{\n+\tstruct rpivid_q_aux *aq;\n+\n+\tctx->colmv_picsize = 0;\n+\tctx->colmv_stride = 0;\n+\twhile ((aq = ctx->aux_free) != NULL) {\n+\t\tctx->aux_free = aq->next;\n+\t\taux_q_free(ctx, aq);\n+\t}\n+}\n+\n+//////////////////////////////////////////////////////////////////////////////\n+\n+/*\n+ * Initialisation process for context variables (CABAC init)\n+ * see H.265 9.3.2.2\n+ *\n+ * N.B. If comparing with FFmpeg note that this h/w uses slightly different\n+ * offsets to FFmpegs array\n+ */\n+\n+/* Actual number of values */\n+#define RPI_PROB_VALS 154U\n+/* Rounded up as we copy words */\n+#define RPI_PROB_ARRAY_SIZE ((154 + 3) & ~3)\n+\n+/* Initialiser values - see tables H.265 9-4 through 9-42 */\n+static const u8 prob_init[3][156] = {\n+\t{\n+\t\t153, 200, 139, 141, 157, 154, 154, 154, 154, 154, 184, 154, 154,\n+\t\t154, 184, 63,  154, 154, 154, 154, 154, 154, 154, 154, 154, 154,\n+\t\t154, 154, 154, 153, 138, 138, 111, 141, 94,  138, 182, 154, 154,\n+\t\t154, 140, 92,  137, 138, 140, 152, 138, 139, 153, 74,  149, 92,\n+\t\t139, 107, 122, 152, 140, 179, 166, 182, 140, 227, 122, 197, 110,\n+\t\t110, 124, 125, 140, 153, 125, 127, 140, 109, 111, 143, 127, 111,\n+\t\t79,  108, 123, 63,  110, 110, 124, 125, 140, 153, 125, 127, 140,\n+\t\t109, 111, 143, 127, 111, 79,  108, 123, 63,  91,  171, 134, 141,\n+\t\t138, 153, 136, 167, 152, 152, 139, 139, 111, 111, 125, 110, 110,\n+\t\t94,  124, 108, 124, 107, 125, 141, 179, 153, 125, 107, 125, 141,\n+\t\t179, 153, 125, 107, 125, 141, 179, 153, 125, 140, 139, 182, 182,\n+\t\t152, 136, 152, 136, 153, 136, 139, 111, 136, 139, 111, 0,   0,\n+\t},\n+\t{\n+\t\t153, 185, 107, 139, 126, 197, 185, 201, 154, 149, 154, 139, 154,\n+\t\t154, 154, 152, 110, 122, 95,  79,  63,  31,  31,  153, 153, 168,\n+\t\t140, 198, 79,  124, 138, 94,  153, 111, 149, 107, 167, 154, 154,\n+\t\t154, 154, 196, 196, 167, 154, 152, 167, 182, 182, 134, 149, 136,\n+\t\t153, 121, 136, 137, 169, 194, 166, 167, 154, 167, 137, 182, 125,\n+\t\t110, 94,  110, 95,  79,  125, 111, 110, 78,  110, 111, 111, 95,\n+\t\t94,  108, 123, 108, 125, 110, 94,  110, 95,  79,  125, 111, 110,\n+\t\t78,  110, 111, 111, 95,  94,  108, 123, 108, 121, 140, 61,  154,\n+\t\t107, 167, 91,  122, 107, 167, 139, 139, 155, 154, 139, 153, 139,\n+\t\t123, 123, 63,  153, 166, 183, 140, 136, 153, 154, 166, 183, 140,\n+\t\t136, 153, 154, 166, 183, 140, 136, 153, 154, 170, 153, 123, 123,\n+\t\t107, 121, 107, 121, 167, 151, 183, 140, 151, 183, 140, 0,   0,\n+\t},\n+\t{\n+\t\t153, 160, 107, 139, 126, 197, 185, 201, 154, 134, 154, 139, 154,\n+\t\t154, 183, 152, 154, 137, 95,  79,  63,  31,  31,  153, 153, 168,\n+\t\t169, 198, 79,  224, 167, 122, 153, 111, 149, 92,  167, 154, 154,\n+\t\t154, 154, 196, 167, 167, 154, 152, 167, 182, 182, 134, 149, 136,\n+\t\t153, 121, 136, 122, 169, 208, 166, 167, 154, 152, 167, 182, 125,\n+\t\t110, 124, 110, 95,  94,  125, 111, 111, 79,  125, 126, 111, 111,\n+\t\t79,  108, 123, 93,  125, 110, 124, 110, 95,  94,  125, 111, 111,\n+\t\t79,  125, 126, 111, 111, 79,  108, 123, 93,  121, 140, 61,  154,\n+\t\t107, 167, 91,  107, 107, 167, 139, 139, 170, 154, 139, 153, 139,\n+\t\t123, 123, 63,  124, 166, 183, 140, 136, 153, 154, 166, 183, 140,\n+\t\t136, 153, 154, 166, 183, 140, 136, 153, 154, 170, 153, 138, 138,\n+\t\t122, 121, 122, 121, 167, 151, 183, 140, 151, 183, 140, 0,   0,\n+\t},\n+};\n+\n+static void write_prob(struct rpivid_dec_env *const de,\n+\t\t       const struct rpivid_dec_state *const s)\n+{\n+\tu8 dst[RPI_PROB_ARRAY_SIZE];\n+\n+\tconst unsigned int init_type =\n+\t\t((s->sh->flags & V4L2_HEVC_SLICE_PARAMS_FLAG_CABAC_INIT) != 0 &&\n+\t\t s->sh->slice_type != HEVC_SLICE_I) ?\n+\t\t\ts->sh->slice_type + 1 :\n+\t\t\t2 - s->sh->slice_type;\n+\tconst u8 *p = prob_init[init_type];\n+\tconst int q = clip_int(s->slice_qp, 0, 51);\n+\tunsigned int i;\n+\n+\tfor (i = 0; i < RPI_PROB_VALS; i++) {\n+\t\tint init_value = p[i];\n+\t\tint m = (init_value >> 4) * 5 - 45;\n+\t\tint n = ((init_value & 15) << 3) - 16;\n+\t\tint pre = 2 * (((m * q) >> 4) + n) - 127;\n+\n+\t\tpre ^= pre >> 31;\n+\t\tif (pre > 124)\n+\t\t\tpre = 124 + (pre & 1);\n+\t\tdst[i] = pre;\n+\t}\n+\tfor (i = RPI_PROB_VALS; i != RPI_PROB_ARRAY_SIZE; ++i)\n+\t\tdst[i] = 0;\n+\n+\tfor (i = 0; i < RPI_PROB_ARRAY_SIZE; i += 4)\n+\t\tp1_apb_write(de, 0x1000 + i,\n+\t\t\t     dst[i] + (dst[i + 1] << 8) + (dst[i + 2] << 16) +\n+\t\t\t\t     (dst[i + 3] << 24));\n+}\n+\n+static void write_scaling_factors(struct rpivid_dec_env *const de)\n+{\n+\tint i;\n+\tconst u8 *p = (u8 *)de->scaling_factors;\n+\n+\tfor (i = 0; i < NUM_SCALING_FACTORS; i += 4, p += 4)\n+\t\tp1_apb_write(de, 0x2000 + i,\n+\t\t\t     p[0] + (p[1] << 8) + (p[2] << 16) + (p[3] << 24));\n+}\n+\n+static inline __u32 dma_to_axi_addr(dma_addr_t a)\n+{\n+\treturn (__u32)(a >> 6);\n+}\n+\n+static void write_bitstream(struct rpivid_dec_env *const de,\n+\t\t\t    const struct rpivid_dec_state *const s)\n+{\n+\t// Note that FFmpeg removes emulation prevention bytes, so this is\n+\t// matched in the configuration here.\n+\t// Whether that is the correct behaviour or not is not clear in the\n+\t// spec.\n+\tconst int rpi_use_emu = 1;\n+\tunsigned int offset = s->sh->data_bit_offset / 8 + 1;\n+\tconst unsigned int len = (s->sh->bit_size + 7) / 8 - offset;\n+\tdma_addr_t addr;\n+\n+\tif (s->src_addr != 0) {\n+\t\taddr = s->src_addr + offset;\n+\t} else {\n+\t\tmemcpy(de->bit_copy_gptr->ptr + de->bit_copy_len,\n+\t\t       s->src_buf + offset, len);\n+\t\taddr = de->bit_copy_gptr->addr + de->bit_copy_len;\n+\t\tde->bit_copy_len += (len + 63) & ~63;\n+\t}\n+\toffset = addr & 63;\n+\n+\tp1_apb_write(de, RPI_BFBASE, dma_to_axi_addr(addr));\n+\tp1_apb_write(de, RPI_BFNUM, len);\n+\tp1_apb_write(de, RPI_BFCONTROL, offset + (1 << 7)); // Stop\n+\tp1_apb_write(de, RPI_BFCONTROL, offset + (rpi_use_emu << 6));\n+}\n+\n+//////////////////////////////////////////////////////////////////////////////\n+\n+static void write_slice(struct rpivid_dec_env *const de,\n+\t\t\tconst struct rpivid_dec_state *const s,\n+\t\t\tconst unsigned int slice_w,\n+\t\t\tconst unsigned int slice_h)\n+{\n+\tu32 u32 = (s->sh->slice_type << 12) +\n+\t\t  (((s->sh->flags &\n+\t\t     V4L2_HEVC_SLICE_PARAMS_FLAG_SLICE_SAO_LUMA) != 0)\n+\t\t   << 14) +\n+\t\t  (((s->sh->flags &\n+\t\t     V4L2_HEVC_SLICE_PARAMS_FLAG_SLICE_SAO_CHROMA) != 0)\n+\t\t   << 15) +\n+\t\t  (slice_w << 17) + (slice_h << 24);\n+\n+\tu32 |= (s->max_num_merge_cand << 0) + (s->nb_refs[L0] << 4) +\n+\t       (s->nb_refs[L1] << 8);\n+\n+\tif (s->sh->slice_type == HEVC_SLICE_B)\n+\t\tu32 |= ((s->sh->flags &\n+\t\t\t V4L2_HEVC_SLICE_PARAMS_FLAG_MVD_L1_ZERO) != 0)\n+\t\t       << 16;\n+\tp1_apb_write(de, RPI_SLICE, u32);\n+}\n+\n+//////////////////////////////////////////////////////////////////////////////\n+// Tiles mode\n+\n+static void new_entry_point(struct rpivid_dec_env *const de,\n+\t\t\t    const struct rpivid_dec_state *const s,\n+\t\t\t    const int do_bte,\n+\t\t\t    const int reset_qp_y, const int ctb_addr_ts)\n+{\n+\tint ctb_col = s->ctb_addr_ts_to_rs[ctb_addr_ts] %\n+\t\t\t\t\t\t\tde->pic_width_in_ctbs_y;\n+\tint ctb_row = s->ctb_addr_ts_to_rs[ctb_addr_ts] /\n+\t\t\t\t\t\t\tde->pic_width_in_ctbs_y;\n+\n+\tint tile_x = ctb_to_tile(ctb_col, s->col_bd, s->num_tile_columns);\n+\tint tile_y = ctb_to_tile(ctb_row, s->row_bd, s->num_tile_rows);\n+\n+\tint endx = s->col_bd[tile_x + 1] - 1;\n+\tint endy = s->row_bd[tile_y + 1] - 1;\n+\n+\tu8 slice_w = ctb_to_slice_w_h(ctb_col, 1 << s->log2_ctb_size,\n+\t\t\t\t      s->sps.pic_width_in_luma_samples,\n+\t\t\t\t      s->col_bd, s->num_tile_columns);\n+\tu8 slice_h = ctb_to_slice_w_h(ctb_row, 1 << s->log2_ctb_size,\n+\t\t\t\t      s->sps.pic_height_in_luma_samples,\n+\t\t\t\t      s->row_bd, s->num_tile_rows);\n+\n+\tp1_apb_write(de, RPI_TILESTART,\n+\t\t     s->col_bd[tile_x] + (s->row_bd[tile_y] << 16));\n+\tp1_apb_write(de, RPI_TILEEND, endx + (endy << 16));\n+\n+\tif (do_bte)\n+\t\tp1_apb_write(de, RPI_BEGINTILEEND, endx + (endy << 16));\n+\n+\twrite_slice(de, s, slice_w, slice_h);\n+\n+\tif (reset_qp_y) {\n+\t\tunsigned int sps_qp_bd_offset =\n+\t\t\t6 * s->sps.bit_depth_luma_minus8;\n+\n+\t\tp1_apb_write(de, RPI_QP, sps_qp_bd_offset + s->slice_qp);\n+\t}\n+\n+\tp1_apb_write(de, RPI_MODE,\n+\t\t     (0xFFFF << 0) + (0x0 << 16) +\n+\t\t\t     ((tile_x == s->num_tile_columns - 1) << 17) +\n+\t\t\t     ((tile_y == s->num_tile_rows - 1) << 18));\n+\n+\tp1_apb_write(de, RPI_CONTROL, (ctb_col << 0) + (ctb_row << 16));\n+}\n+\n+//////////////////////////////////////////////////////////////////////////////\n+\n+static void new_slice_segment(struct rpivid_dec_env *const de,\n+\t\t\t      const struct rpivid_dec_state *const s)\n+{\n+\tconst struct v4l2_ctrl_hevc_sps *const sps = &s->sps;\n+\tconst struct v4l2_ctrl_hevc_pps *const pps = &s->pps;\n+\n+\tp1_apb_write(de,\n+\t\t     RPI_SPS0,\n+\t\t     ((sps->log2_min_luma_coding_block_size_minus3 + 3) << 0) |\n+\t\t     (s->log2_ctb_size << 4) |\n+\t\t     ((sps->log2_min_luma_transform_block_size_minus2 + 2)\n+\t\t\t\t\t\t\t<< 8) |\n+\t\t     ((sps->log2_min_luma_transform_block_size_minus2 + 2 +\n+\t\t       sps->log2_diff_max_min_luma_transform_block_size)\n+\t\t\t\t\t\t<< 12) |\n+\t\t     ((sps->bit_depth_luma_minus8 + 8) << 16) |\n+\t\t     ((sps->bit_depth_chroma_minus8 + 8) << 20) |\n+\t\t     (sps->max_transform_hierarchy_depth_intra << 24) |\n+\t\t     (sps->max_transform_hierarchy_depth_inter << 28));\n+\n+\tp1_apb_write(de,\n+\t\t     RPI_SPS1,\n+\t\t     ((sps->pcm_sample_bit_depth_luma_minus1 + 1) << 0) |\n+\t\t     ((sps->pcm_sample_bit_depth_chroma_minus1 + 1) << 4) |\n+\t\t     ((sps->log2_min_pcm_luma_coding_block_size_minus3 + 3)\n+\t\t\t\t\t\t<< 8) |\n+\t\t     ((sps->log2_min_pcm_luma_coding_block_size_minus3 + 3 +\n+\t\t       sps->log2_diff_max_min_pcm_luma_coding_block_size)\n+\t\t\t\t\t\t<< 12) |\n+\t\t     (((sps->flags & V4L2_HEVC_SPS_FLAG_SEPARATE_COLOUR_PLANE) ?\n+\t\t\t\t0 : sps->chroma_format_idc) << 16) |\n+\t\t     ((!!(sps->flags & V4L2_HEVC_SPS_FLAG_AMP_ENABLED)) << 18) |\n+\t\t     ((!!(sps->flags & V4L2_HEVC_SPS_FLAG_PCM_ENABLED)) << 19) |\n+\t\t     ((!!(sps->flags & V4L2_HEVC_SPS_FLAG_SCALING_LIST_ENABLED))\n+\t\t\t\t\t\t<< 20) |\n+\t\t     ((!!(sps->flags &\n+\t\t\t   V4L2_HEVC_SPS_FLAG_STRONG_INTRA_SMOOTHING_ENABLED))\n+\t\t\t\t\t\t<< 21));\n+\n+\tp1_apb_write(de,\n+\t\t     RPI_PPS,\n+\t\t     ((s->log2_ctb_size - pps->diff_cu_qp_delta_depth) << 0) |\n+\t\t     ((!!(pps->flags & V4L2_HEVC_PPS_FLAG_CU_QP_DELTA_ENABLED))\n+\t\t\t\t\t\t << 4) |\n+\t\t     ((!!(pps->flags &\n+\t\t\t\tV4L2_HEVC_PPS_FLAG_TRANSQUANT_BYPASS_ENABLED))\n+\t\t\t\t\t\t << 5) |\n+\t\t     ((!!(pps->flags & V4L2_HEVC_PPS_FLAG_TRANSFORM_SKIP_ENABLED))\n+\t\t\t\t\t\t << 6) |\n+\t\t     ((!!(pps->flags &\n+\t\t\t\tV4L2_HEVC_PPS_FLAG_SIGN_DATA_HIDING_ENABLED))\n+\t\t\t\t\t\t<< 7) |\n+\t\t     (((pps->pps_cb_qp_offset + s->sh->slice_cb_qp_offset) & 255)\n+\t\t\t\t\t\t<< 8) |\n+\t\t     (((pps->pps_cr_qp_offset + s->sh->slice_cr_qp_offset) & 255)\n+\t\t\t\t\t\t<< 16) |\n+\t\t     ((!!(pps->flags &\n+\t\t\t\tV4L2_HEVC_PPS_FLAG_CONSTRAINED_INTRA_PRED))\n+\t\t\t\t\t\t<< 24));\n+\n+\tif ((sps->flags & V4L2_HEVC_SPS_FLAG_SCALING_LIST_ENABLED) != 0)\n+\t\twrite_scaling_factors(de);\n+\n+\tif (!s->dependent_slice_segment_flag) {\n+\t\tint ctb_col = s->sh->slice_segment_addr %\n+\t\t\t\t\t\t\tde->pic_width_in_ctbs_y;\n+\t\tint ctb_row = s->sh->slice_segment_addr /\n+\t\t\t\t\t\t\tde->pic_width_in_ctbs_y;\n+\n+\t\tde->reg_slicestart = (ctb_col << 0) + (ctb_row << 16);\n+\t}\n+\n+\tp1_apb_write(de, RPI_SLICESTART, de->reg_slicestart);\n+}\n+\n+//////////////////////////////////////////////////////////////////////////////\n+// Slice messages\n+\n+static void msg_slice(struct rpivid_dec_env *const de, const u16 msg)\n+{\n+\tde->slice_msgs[de->num_slice_msgs++] = msg;\n+}\n+\n+static void program_slicecmds(struct rpivid_dec_env *const de,\n+\t\t\t      const int sliceid)\n+{\n+\tint i;\n+\n+\tp1_apb_write(de, RPI_SLICECMDS, de->num_slice_msgs + (sliceid << 8));\n+\n+\tfor (i = 0; i < de->num_slice_msgs; i++)\n+\t\tp1_apb_write(de, 0x4000 + 4 * i, de->slice_msgs[i] & 0xffff);\n+}\n+\n+// NoBackwardPredictionFlag 8.3.5\n+// Simply checks POCs\n+static int has_backward(const struct v4l2_hevc_dpb_entry *const dpb,\n+\t\t\tconst __u8 *const idx, const unsigned int n,\n+\t\t\tconst unsigned int cur_poc)\n+{\n+\tunsigned int i;\n+\n+\tfor (i = 0; i < n; ++i) {\n+\t\t// Compare mod 2^16\n+\t\t// We only get u16 pocs & 8.3.1 says\n+\t\t// \"The bitstream shall not contain data that result in values\n+\t\t//  of DiffPicOrderCnt( picA, picB ) used in the decoding\n+\t\t//  process that are not in the range of −2^15 to 2^15 − 1,\n+\t\t//  inclusive.\"\n+\t\tif (((cur_poc - dpb[idx[i]].pic_order_cnt[0]) & 0x8000) != 0)\n+\t\t\treturn 0;\n+\t}\n+\treturn 1;\n+}\n+\n+static void pre_slice_decode(struct rpivid_dec_env *const de,\n+\t\t\t     const struct rpivid_dec_state *const s)\n+{\n+\tconst struct v4l2_ctrl_hevc_slice_params *const sh = s->sh;\n+\tint weighted_pred_flag, idx;\n+\tu16 cmd_slice;\n+\tunsigned int collocated_from_l0_flag;\n+\n+\tde->num_slice_msgs = 0;\n+\n+\tcmd_slice = 0;\n+\tif (sh->slice_type == HEVC_SLICE_I)\n+\t\tcmd_slice = 1;\n+\tif (sh->slice_type == HEVC_SLICE_P)\n+\t\tcmd_slice = 2;\n+\tif (sh->slice_type == HEVC_SLICE_B)\n+\t\tcmd_slice = 3;\n+\n+\tcmd_slice |= (s->nb_refs[L0] << 2) | (s->nb_refs[L1] << 6) |\n+\t\t     (s->max_num_merge_cand << 11);\n+\n+\tcollocated_from_l0_flag =\n+\t\t!s->slice_temporal_mvp ||\n+\t\tsh->slice_type != HEVC_SLICE_B ||\n+\t\t(sh->flags & V4L2_HEVC_SLICE_PARAMS_FLAG_COLLOCATED_FROM_L0);\n+\tcmd_slice |= collocated_from_l0_flag << 14;\n+\n+\tif (sh->slice_type == HEVC_SLICE_P || sh->slice_type == HEVC_SLICE_B) {\n+\t\t// Flag to say all reference pictures are from the past\n+\t\tconst int no_backward_pred_flag =\n+\t\t\thas_backward(sh->dpb, sh->ref_idx_l0, s->nb_refs[L0],\n+\t\t\t\t     sh->slice_pic_order_cnt) &&\n+\t\t\thas_backward(sh->dpb, sh->ref_idx_l1, s->nb_refs[L1],\n+\t\t\t\t     sh->slice_pic_order_cnt);\n+\t\tcmd_slice |= no_backward_pred_flag << 10;\n+\t\tmsg_slice(de, cmd_slice);\n+\n+\t\tif (s->slice_temporal_mvp) {\n+\t\t\tconst __u8 *const rpl = collocated_from_l0_flag ?\n+\t\t\t\t\t\tsh->ref_idx_l0 : sh->ref_idx_l1;\n+\t\t\tde->dpbno_col = rpl[sh->collocated_ref_idx];\n+\t\t\t//v4l2_info(&de->ctx->dev->v4l2_dev,\n+\t\t\t//\t    \"L0=%d col_ref_idx=%d,\n+\t\t\t//          dpb_no=%d\\n\", collocated_from_l0_flag,\n+\t\t\t//          sh->collocated_ref_idx, de->dpbno_col);\n+\t\t}\n+\n+\t\t// Write reference picture descriptions\n+\t\tweighted_pred_flag =\n+\t\t\tsh->slice_type == HEVC_SLICE_P ?\n+\t\t\t\t!!(s->pps.flags & V4L2_HEVC_PPS_FLAG_WEIGHTED_PRED) :\n+\t\t\t\t!!(s->pps.flags & V4L2_HEVC_PPS_FLAG_WEIGHTED_BIPRED);\n+\n+\t\tfor (idx = 0; idx < s->nb_refs[L0]; ++idx) {\n+\t\t\tunsigned int dpb_no = sh->ref_idx_l0[idx];\n+\t\t\t//v4l2_info(&de->ctx->dev->v4l2_dev,\n+\t\t\t//\t  \"L0[%d]=dpb[%d]\\n\", idx, dpb_no);\n+\n+\t\t\tmsg_slice(de,\n+\t\t\t\t  dpb_no |\n+\t\t\t\t  (sh->dpb[dpb_no].rps ==\n+\t\t\t\t\tV4L2_HEVC_DPB_ENTRY_RPS_LT_CURR ?\n+\t\t\t\t\t\t (1 << 4) : 0) |\n+\t\t\t\t  (weighted_pred_flag ? (3 << 5) : 0));\n+\t\t\tmsg_slice(de, sh->dpb[dpb_no].pic_order_cnt[0]);\n+\n+\t\t\tif (weighted_pred_flag) {\n+\t\t\t\tconst struct v4l2_hevc_pred_weight_table\n+\t\t\t\t\t*const w = &sh->pred_weight_table;\n+\t\t\t\tconst int luma_weight_denom =\n+\t\t\t\t\t(1 << w->luma_log2_weight_denom);\n+\t\t\t\tconst unsigned int chroma_log2_weight_denom =\n+\t\t\t\t\t(w->luma_log2_weight_denom +\n+\t\t\t\t\t w->delta_chroma_log2_weight_denom);\n+\t\t\t\tconst int chroma_weight_denom =\n+\t\t\t\t\t(1 << chroma_log2_weight_denom);\n+\n+\t\t\t\tmsg_slice(de,\n+\t\t\t\t\t  w->luma_log2_weight_denom |\n+\t\t\t\t\t  (((w->delta_luma_weight_l0[idx] +\n+\t\t\t\t\t     luma_weight_denom) & 0x1ff)\n+\t\t\t\t\t\t << 3));\n+\t\t\t\tmsg_slice(de, w->luma_offset_l0[idx] & 0xff);\n+\t\t\t\tmsg_slice(de,\n+\t\t\t\t\t  chroma_log2_weight_denom |\n+\t\t\t\t\t  (((w->delta_chroma_weight_l0[idx][0] +\n+\t\t\t\t\t     chroma_weight_denom) & 0x1ff)\n+\t\t\t\t\t\t   << 3));\n+\t\t\t\tmsg_slice(de,\n+\t\t\t\t\t  w->chroma_offset_l0[idx][0] & 0xff);\n+\t\t\t\tmsg_slice(de,\n+\t\t\t\t\t  chroma_log2_weight_denom |\n+\t\t\t\t\t  (((w->delta_chroma_weight_l0[idx][1] +\n+\t\t\t\t\t     chroma_weight_denom) & 0x1ff)\n+\t\t\t\t\t\t   << 3));\n+\t\t\t\tmsg_slice(de,\n+\t\t\t\t\t  w->chroma_offset_l0[idx][1] & 0xff);\n+\t\t\t}\n+\t\t}\n+\n+\t\tfor (idx = 0; idx < s->nb_refs[L1]; ++idx) {\n+\t\t\tunsigned int dpb_no = sh->ref_idx_l1[idx];\n+\t\t\t//v4l2_info(&de->ctx->dev->v4l2_dev,\n+\t\t\t//          \"L1[%d]=dpb[%d]\\n\", idx, dpb_no);\n+\t\t\tmsg_slice(de,\n+\t\t\t\t  dpb_no |\n+\t\t\t\t  (sh->dpb[dpb_no].rps ==\n+\t\t\t\t\t V4L2_HEVC_DPB_ENTRY_RPS_LT_CURR ?\n+\t\t\t\t\t\t (1 << 4) : 0) |\n+\t\t\t\t\t(weighted_pred_flag ? (3 << 5) : 0));\n+\t\t\tmsg_slice(de, sh->dpb[dpb_no].pic_order_cnt[0]);\n+\t\t\tif (weighted_pred_flag) {\n+\t\t\t\tconst struct v4l2_hevc_pred_weight_table\n+\t\t\t\t\t*const w = &sh->pred_weight_table;\n+\t\t\t\tconst int luma_weight_denom =\n+\t\t\t\t\t(1 << w->luma_log2_weight_denom);\n+\t\t\t\tconst unsigned int chroma_log2_weight_denom =\n+\t\t\t\t\t(w->luma_log2_weight_denom +\n+\t\t\t\t\t w->delta_chroma_log2_weight_denom);\n+\t\t\t\tconst int chroma_weight_denom =\n+\t\t\t\t\t(1 << chroma_log2_weight_denom);\n+\n+\t\t\t\tmsg_slice(de,\n+\t\t\t\t\t  w->luma_log2_weight_denom |\n+\t\t\t\t\t  (((w->delta_luma_weight_l1[idx] +\n+\t\t\t\t\t     luma_weight_denom) & 0x1ff) << 3));\n+\t\t\t\tmsg_slice(de, w->luma_offset_l1[idx] & 0xff);\n+\t\t\t\tmsg_slice(de,\n+\t\t\t\t\t  chroma_log2_weight_denom |\n+\t\t\t\t\t  (((w->delta_chroma_weight_l1[idx][0] +\n+\t\t\t\t\t     chroma_weight_denom) & 0x1ff)\n+\t\t\t\t\t\t\t<< 3));\n+\t\t\t\tmsg_slice(de,\n+\t\t\t\t\t  w->chroma_offset_l1[idx][0] & 0xff);\n+\t\t\t\tmsg_slice(de,\n+\t\t\t\t\t  chroma_log2_weight_denom |\n+\t\t\t\t\t  (((w->delta_chroma_weight_l1[idx][1] +\n+\t\t\t\t\t     chroma_weight_denom) & 0x1ff)\n+\t\t\t\t\t\t   << 3));\n+\t\t\t\tmsg_slice(de,\n+\t\t\t\t\t  w->chroma_offset_l1[idx][1] & 0xff);\n+\t\t\t}\n+\t\t}\n+\t} else {\n+\t\tmsg_slice(de, cmd_slice);\n+\t}\n+\n+\tmsg_slice(de,\n+\t\t  (sh->slice_beta_offset_div2 & 15) |\n+\t\t  ((sh->slice_tc_offset_div2 & 15) << 4) |\n+\t\t  ((sh->flags &\n+\t\t    V4L2_HEVC_SLICE_PARAMS_FLAG_SLICE_DEBLOCKING_FILTER_DISABLED) ?\n+\t\t\t\t\t\t1 << 8 : 0) |\n+\t\t  ((sh->flags &\n+\t\t\t  V4L2_HEVC_SLICE_PARAMS_FLAG_SLICE_LOOP_FILTER_ACROSS_SLICES_ENABLED) ?\n+\t\t\t\t\t\t1 << 9 : 0) |\n+\t\t  ((s->pps.flags &\n+\t\t\t  V4L2_HEVC_PPS_FLAG_LOOP_FILTER_ACROSS_TILES_ENABLED) ?\n+\t\t\t\t\t\t1 << 10 : 0));\n+\n+\tmsg_slice(de, ((sh->slice_cr_qp_offset & 31) << 5) +\n+\t\t       (sh->slice_cb_qp_offset & 31)); // CMD_QPOFF\n+}\n+\n+//////////////////////////////////////////////////////////////////////////////\n+// Write STATUS register with expected end CTU address of previous slice\n+\n+static void end_previous_slice(struct rpivid_dec_env *const de,\n+\t\t\t       const struct rpivid_dec_state *const s,\n+\t\t\t       const int ctb_addr_ts)\n+{\n+\tint last_x =\n+\t\ts->ctb_addr_ts_to_rs[ctb_addr_ts - 1] % de->pic_width_in_ctbs_y;\n+\tint last_y =\n+\t\ts->ctb_addr_ts_to_rs[ctb_addr_ts - 1] / de->pic_width_in_ctbs_y;\n+\n+\tp1_apb_write(de, RPI_STATUS, 1 + (last_x << 5) + (last_y << 18));\n+}\n+\n+static void wpp_pause(struct rpivid_dec_env *const de, int ctb_row)\n+{\n+\tp1_apb_write(de, RPI_STATUS, (ctb_row << 18) + 0x25);\n+\tp1_apb_write(de, RPI_TRANSFER, PROB_BACKUP);\n+\tp1_apb_write(de, RPI_MODE,\n+\t\t     ctb_row == de->pic_height_in_ctbs_y - 1 ?\n+\t\t\t\t\t\t\t0x70000 : 0x30000);\n+\tp1_apb_write(de, RPI_CONTROL, (ctb_row << 16) + 2);\n+}\n+\n+static void wpp_end_previous_slice(struct rpivid_dec_env *const de,\n+\t\t\t\t   const struct rpivid_dec_state *const s,\n+\t\t\t\t   int ctb_addr_ts)\n+{\n+\tint new_x = s->sh->slice_segment_addr % de->pic_width_in_ctbs_y;\n+\tint new_y = s->sh->slice_segment_addr / de->pic_width_in_ctbs_y;\n+\tint last_x =\n+\t\ts->ctb_addr_ts_to_rs[ctb_addr_ts - 1] % de->pic_width_in_ctbs_y;\n+\tint last_y =\n+\t\ts->ctb_addr_ts_to_rs[ctb_addr_ts - 1] / de->pic_width_in_ctbs_y;\n+\n+\tif (de->wpp_entry_x < 2 && (de->wpp_entry_y < new_y || new_x > 2) &&\n+\t    de->pic_width_in_ctbs_y > 2)\n+\t\twpp_pause(de, last_y);\n+\tp1_apb_write(de, RPI_STATUS, 1 + (last_x << 5) + (last_y << 18));\n+\tif (new_x == 2 || (de->pic_width_in_ctbs_y == 2 &&\n+\t\t\t   de->wpp_entry_y < new_y))\n+\t\tp1_apb_write(de, RPI_TRANSFER, PROB_BACKUP);\n+}\n+\n+//////////////////////////////////////////////////////////////////////////////\n+// Wavefront mode\n+\n+static void wpp_entry_point(struct rpivid_dec_env *const de,\n+\t\t\t    const struct rpivid_dec_state *const s,\n+\t\t\t    const int do_bte,\n+\t\t\t    const int reset_qp_y, const int ctb_addr_ts)\n+{\n+\tint ctb_size = 1 << s->log2_ctb_size;\n+\tint ctb_addr_rs = s->ctb_addr_ts_to_rs[ctb_addr_ts];\n+\n+\tint ctb_col = de->wpp_entry_x = ctb_addr_rs % de->pic_width_in_ctbs_y;\n+\tint ctb_row = de->wpp_entry_y = ctb_addr_rs / de->pic_width_in_ctbs_y;\n+\n+\tint endx = de->pic_width_in_ctbs_y - 1;\n+\tint endy = ctb_row;\n+\n+\tu8 slice_w = ctb_to_slice_w_h(ctb_col, ctb_size,\n+\t\t\t\t      s->sps.pic_width_in_luma_samples,\n+\t\t\t\t      s->col_bd, s->num_tile_columns);\n+\tu8 slice_h = ctb_to_slice_w_h(ctb_row, ctb_size,\n+\t\t\t\t      s->sps.pic_height_in_luma_samples,\n+\t\t\t\t      s->row_bd, s->num_tile_rows);\n+\n+\tp1_apb_write(de, RPI_TILESTART, 0);\n+\tp1_apb_write(de, RPI_TILEEND, endx + (endy << 16));\n+\n+\tif (do_bte)\n+\t\tp1_apb_write(de, RPI_BEGINTILEEND, endx + (endy << 16));\n+\n+\twrite_slice(de, s, slice_w,\n+\t\t    ctb_row == de->pic_height_in_ctbs_y - 1 ?\n+\t\t\t\t\t\t\tslice_h : ctb_size);\n+\n+\tif (reset_qp_y) {\n+\t\tunsigned int sps_qp_bd_offset =\n+\t\t\t6 * s->sps.bit_depth_luma_minus8;\n+\n+\t\tp1_apb_write(de, RPI_QP, sps_qp_bd_offset + s->slice_qp);\n+\t}\n+\n+\tp1_apb_write(de, RPI_MODE,\n+\t\t     ctb_row == de->pic_height_in_ctbs_y - 1 ?\n+\t\t\t\t\t\t\t0x60001 : 0x20001);\n+\tp1_apb_write(de, RPI_CONTROL, (ctb_col << 0) + (ctb_row << 16));\n+}\n+\n+//////////////////////////////////////////////////////////////////////////////\n+// Wavefront mode\n+\n+static void wpp_decode_slice(struct rpivid_dec_env *const de,\n+\t\t\t     const struct rpivid_dec_state *const s,\n+\t\t\t     const struct v4l2_ctrl_hevc_slice_params *sh,\n+\t\t\t     int ctb_addr_ts)\n+{\n+\tint i, reset_qp_y = 1;\n+\tint indep = !s->dependent_slice_segment_flag;\n+\tint ctb_col = s->sh->slice_segment_addr % de->pic_width_in_ctbs_y;\n+\n+\tif (ctb_addr_ts)\n+\t\twpp_end_previous_slice(de, s, ctb_addr_ts);\n+\tpre_slice_decode(de, s);\n+\twrite_bitstream(de, s);\n+\tif (ctb_addr_ts == 0 || indep || de->pic_width_in_ctbs_y == 1)\n+\t\twrite_prob(de, s);\n+\telse if (ctb_col == 0)\n+\t\tp1_apb_write(de, RPI_TRANSFER, PROB_RELOAD);\n+\telse\n+\t\treset_qp_y = 0;\n+\tprogram_slicecmds(de, s->slice_idx);\n+\tnew_slice_segment(de, s);\n+\twpp_entry_point(de, s, indep, reset_qp_y, ctb_addr_ts);\n+\n+\tfor (i = 0; i < s->sh->num_entry_point_offsets; i++) {\n+\t\tint ctb_addr_rs = s->ctb_addr_ts_to_rs[ctb_addr_ts];\n+\t\tint ctb_row = ctb_addr_rs / de->pic_width_in_ctbs_y;\n+\t\tint last_x = de->pic_width_in_ctbs_y - 1;\n+\n+\t\tif (de->pic_width_in_ctbs_y > 2)\n+\t\t\twpp_pause(de, ctb_row);\n+\t\tp1_apb_write(de, RPI_STATUS,\n+\t\t\t     (ctb_row << 18) + (last_x << 5) + 2);\n+\t\tif (de->pic_width_in_ctbs_y == 2)\n+\t\t\tp1_apb_write(de, RPI_TRANSFER, PROB_BACKUP);\n+\t\tif (de->pic_width_in_ctbs_y == 1)\n+\t\t\twrite_prob(de, s);\n+\t\telse\n+\t\t\tp1_apb_write(de, RPI_TRANSFER, PROB_RELOAD);\n+\t\tctb_addr_ts += s->column_width[0];\n+\t\twpp_entry_point(de, s, 0, 1, ctb_addr_ts);\n+\t}\n+}\n+\n+//////////////////////////////////////////////////////////////////////////////\n+// Tiles mode\n+\n+static void decode_slice(struct rpivid_dec_env *const de,\n+\t\t\t const struct rpivid_dec_state *const s,\n+\t\t\t const struct v4l2_ctrl_hevc_slice_params *const sh,\n+\t\t\t int ctb_addr_ts)\n+{\n+\tint i, reset_qp_y;\n+\n+\tif (ctb_addr_ts)\n+\t\tend_previous_slice(de, s, ctb_addr_ts);\n+\n+\tpre_slice_decode(de, s);\n+\twrite_bitstream(de, s);\n+\n+#if DEBUG_TRACE_P1_CMD\n+\tif (p1_z < 256) {\n+\t\tv4l2_info(&de->ctx->dev->v4l2_dev,\n+\t\t\t  \"TS=%d, tile=%d/%d, dss=%d, flags=%#llx\\n\",\n+\t\t\t  ctb_addr_ts, s->tile_id[ctb_addr_ts],\n+\t\t\t  s->tile_id[ctb_addr_ts - 1],\n+\t\t\t  s->dependent_slice_segment_flag, sh->flags);\n+\t}\n+#endif\n+\n+\treset_qp_y = ctb_addr_ts == 0 ||\n+\t\t   s->tile_id[ctb_addr_ts] != s->tile_id[ctb_addr_ts - 1] ||\n+\t\t   !s->dependent_slice_segment_flag;\n+\tif (reset_qp_y)\n+\t\twrite_prob(de, s);\n+\n+\tprogram_slicecmds(de, s->slice_idx);\n+\tnew_slice_segment(de, s);\n+\tnew_entry_point(de, s, !s->dependent_slice_segment_flag, reset_qp_y,\n+\t\t\tctb_addr_ts);\n+\n+\tfor (i = 0; i < s->sh->num_entry_point_offsets; i++) {\n+\t\tint ctb_addr_rs = s->ctb_addr_ts_to_rs[ctb_addr_ts];\n+\t\tint ctb_col = ctb_addr_rs % de->pic_width_in_ctbs_y;\n+\t\tint ctb_row = ctb_addr_rs / de->pic_width_in_ctbs_y;\n+\t\tint tile_x = ctb_to_tile(ctb_col, s->col_bd,\n+\t\t\t\t\t s->num_tile_columns - 1);\n+\t\tint tile_y =\n+\t\t\tctb_to_tile(ctb_row, s->row_bd, s->num_tile_rows - 1);\n+\t\tint last_x = s->col_bd[tile_x + 1] - 1;\n+\t\tint last_y = s->row_bd[tile_y + 1] - 1;\n+\n+\t\tp1_apb_write(de, RPI_STATUS,\n+\t\t\t     2 + (last_x << 5) + (last_y << 18));\n+\t\twrite_prob(de, s);\n+\t\tctb_addr_ts += s->column_width[tile_x] * s->row_height[tile_y];\n+\t\tnew_entry_point(de, s, 0, 1, ctb_addr_ts);\n+\t}\n+}\n+\n+//////////////////////////////////////////////////////////////////////////////\n+// Scaling factors\n+\n+static void expand_scaling_list(const unsigned int size_id,\n+\t\t\t\tconst unsigned int matrix_id, u8 *const dst0,\n+\t\t\t\tconst u8 *const src0, uint8_t dc)\n+{\n+\tu8 *d;\n+\tunsigned int x, y;\n+\n+\t// FIXME: matrix_id is unused ?\n+\tswitch (size_id) {\n+\tcase 0:\n+\t\tmemcpy(dst0, src0, 16);\n+\t\tbreak;\n+\tcase 1:\n+\t\tmemcpy(dst0, src0, 64);\n+\t\tbreak;\n+\tcase 2:\n+\t\td = dst0;\n+\n+\t\tfor (y = 0; y != 16; y++) {\n+\t\t\tconst u8 *s = src0 + (y >> 1) * 8;\n+\n+\t\t\tfor (x = 0; x != 8; ++x) {\n+\t\t\t\t*d++ = *s;\n+\t\t\t\t*d++ = *s++;\n+\t\t\t}\n+\t\t}\n+\t\tdst0[0] = dc;\n+\t\tbreak;\n+\tdefault:\n+\t\td = dst0;\n+\n+\t\tfor (y = 0; y != 32; y++) {\n+\t\t\tconst u8 *s = src0 + (y >> 2) * 8;\n+\n+\t\t\tfor (x = 0; x != 8; ++x) {\n+\t\t\t\t*d++ = *s;\n+\t\t\t\t*d++ = *s;\n+\t\t\t\t*d++ = *s;\n+\t\t\t\t*d++ = *s++;\n+\t\t\t}\n+\t\t}\n+\t\tdst0[0] = dc;\n+\t\tbreak;\n+\t}\n+}\n+\n+static void populate_scaling_factors(const struct rpivid_run *const run,\n+\t\t\t\t     struct rpivid_dec_env *const de,\n+\t\t\t\t     const struct rpivid_dec_state *const s)\n+{\n+\tconst struct v4l2_ctrl_hevc_scaling_matrix *const sl =\n+\t\trun->h265.scaling_matrix;\n+\t// Array of constants for scaling factors\n+\tstatic const u32 scaling_factor_offsets[4][6] = {\n+\t\t// MID0    MID1    MID2    MID3    MID4    MID5\n+\t\t// SID0 (4x4)\n+\t\t{ 0x0000, 0x0010, 0x0020, 0x0030, 0x0040, 0x0050 },\n+\t\t// SID1 (8x8)\n+\t\t{ 0x0060, 0x00A0, 0x00E0, 0x0120, 0x0160, 0x01A0 },\n+\t\t// SID2 (16x16)\n+\t\t{ 0x01E0, 0x02E0, 0x03E0, 0x04E0, 0x05E0, 0x06E0 },\n+\t\t// SID3 (32x32)\n+\t\t{ 0x07E0, 0x0BE0, 0x0000, 0x0000, 0x0000, 0x0000 }\n+\t};\n+\n+\tunsigned int mid;\n+\n+\tfor (mid = 0; mid < 6; mid++)\n+\t\texpand_scaling_list(0, mid,\n+\t\t\t\t    de->scaling_factors +\n+\t\t\t\t\t    scaling_factor_offsets[0][mid],\n+\t\t\t\t    sl->scaling_list_4x4[mid], 0);\n+\tfor (mid = 0; mid < 6; mid++)\n+\t\texpand_scaling_list(1, mid,\n+\t\t\t\t    de->scaling_factors +\n+\t\t\t\t\t    scaling_factor_offsets[1][mid],\n+\t\t\t\t    sl->scaling_list_8x8[mid], 0);\n+\tfor (mid = 0; mid < 6; mid++)\n+\t\texpand_scaling_list(2, mid,\n+\t\t\t\t    de->scaling_factors +\n+\t\t\t\t\t    scaling_factor_offsets[2][mid],\n+\t\t\t\t    sl->scaling_list_16x16[mid],\n+\t\t\t\t    sl->scaling_list_dc_coef_16x16[mid]);\n+\tfor (mid = 0; mid < 2; mid += 1)\n+\t\texpand_scaling_list(3, mid,\n+\t\t\t\t    de->scaling_factors +\n+\t\t\t\t\t    scaling_factor_offsets[3][mid],\n+\t\t\t\t    sl->scaling_list_32x32[mid],\n+\t\t\t\t    sl->scaling_list_dc_coef_32x32[mid]);\n+}\n+\n+static void free_ps_info(struct rpivid_dec_state *const s)\n+{\n+\tkfree(s->ctb_addr_rs_to_ts);\n+\ts->ctb_addr_rs_to_ts = NULL;\n+\tkfree(s->ctb_addr_ts_to_rs);\n+\ts->ctb_addr_ts_to_rs = NULL;\n+\tkfree(s->tile_id);\n+\ts->tile_id = NULL;\n+\n+\tkfree(s->col_bd);\n+\ts->col_bd = NULL;\n+\tkfree(s->row_bd);\n+\ts->row_bd = NULL;\n+}\n+\n+static int updated_ps(struct rpivid_dec_state *const s)\n+{\n+\tunsigned int ctb_addr_rs;\n+\tint j, x, y, tile_id;\n+\tunsigned int i;\n+\n+\tfree_ps_info(s);\n+\n+\t// Inferred parameters\n+\ts->log2_ctb_size = s->sps.log2_min_luma_coding_block_size_minus3 + 3 +\n+\t\t\t   s->sps.log2_diff_max_min_luma_coding_block_size;\n+\n+\ts->ctb_width = (s->sps.pic_width_in_luma_samples +\n+\t\t\t(1 << s->log2_ctb_size) - 1) >>\n+\t\t       s->log2_ctb_size;\n+\ts->ctb_height = (s->sps.pic_height_in_luma_samples +\n+\t\t\t (1 << s->log2_ctb_size) - 1) >>\n+\t\t\ts->log2_ctb_size;\n+\ts->ctb_size = s->ctb_width * s->ctb_height;\n+\n+\t// Inferred parameters\n+\n+\tif (!(s->pps.flags & V4L2_HEVC_PPS_FLAG_TILES_ENABLED)) {\n+\t\ts->num_tile_columns = 1;\n+\t\ts->num_tile_rows = 1;\n+\t\ts->column_width[0] = s->ctb_width;\n+\t\ts->row_height[0] = s->ctb_height;\n+\t} else {\n+\t\ts->num_tile_columns = s->pps.num_tile_columns_minus1 + 1;\n+\t\ts->num_tile_rows = s->pps.num_tile_rows_minus1 + 1;\n+\t\tfor (i = 0; i < s->num_tile_columns; ++i)\n+\t\t\ts->column_width[i] = s->pps.column_width_minus1[i] + 1;\n+\t\tfor (i = 0; i < s->num_tile_rows; ++i)\n+\t\t\ts->row_height[i] = s->pps.row_height_minus1[i] + 1;\n+\t}\n+\n+\ts->col_bd = kmalloc((s->num_tile_columns + 1) * sizeof(*s->col_bd),\n+\t\t\t    GFP_KERNEL);\n+\ts->row_bd = kmalloc((s->num_tile_rows + 1) * sizeof(*s->row_bd),\n+\t\t\t    GFP_KERNEL);\n+\n+\ts->col_bd[0] = 0;\n+\tfor (i = 0; i < s->num_tile_columns; i++)\n+\t\ts->col_bd[i + 1] = s->col_bd[i] + s->column_width[i];\n+\n+\ts->row_bd[0] = 0;\n+\tfor (i = 0; i < s->num_tile_rows; i++)\n+\t\ts->row_bd[i + 1] = s->row_bd[i] + s->row_height[i];\n+\n+\ts->ctb_addr_rs_to_ts = kmalloc_array(s->ctb_size,\n+\t\t\t\t\t     sizeof(*s->ctb_addr_rs_to_ts),\n+\t\t\t\t\t     GFP_KERNEL);\n+\ts->ctb_addr_ts_to_rs = kmalloc_array(s->ctb_size,\n+\t\t\t\t\t     sizeof(*s->ctb_addr_ts_to_rs),\n+\t\t\t\t\t     GFP_KERNEL);\n+\ts->tile_id = kmalloc_array(s->ctb_size, sizeof(*s->tile_id),\n+\t\t\t\t   GFP_KERNEL);\n+\n+\tfor (ctb_addr_rs = 0; ctb_addr_rs < s->ctb_size; ctb_addr_rs++) {\n+\t\tint tb_x = ctb_addr_rs % s->ctb_width;\n+\t\tint tb_y = ctb_addr_rs / s->ctb_width;\n+\t\tint tile_x = 0;\n+\t\tint tile_y = 0;\n+\t\tint val = 0;\n+\n+\t\tfor (i = 0; i < s->num_tile_columns; i++) {\n+\t\t\tif (tb_x < s->col_bd[i + 1]) {\n+\t\t\t\ttile_x = i;\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t}\n+\n+\t\tfor (i = 0; i < s->num_tile_rows; i++) {\n+\t\t\tif (tb_y < s->row_bd[i + 1]) {\n+\t\t\t\ttile_y = i;\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t}\n+\n+\t\tfor (i = 0; i < tile_x; i++)\n+\t\t\tval += s->row_height[tile_y] * s->column_width[i];\n+\t\tfor (i = 0; i < tile_y; i++)\n+\t\t\tval += s->ctb_width * s->row_height[i];\n+\n+\t\tval += (tb_y - s->row_bd[tile_y]) * s->column_width[tile_x] +\n+\t\t       tb_x - s->col_bd[tile_x];\n+\n+\t\ts->ctb_addr_rs_to_ts[ctb_addr_rs] = val;\n+\t\ts->ctb_addr_ts_to_rs[val] = ctb_addr_rs;\n+\t}\n+\n+\tfor (j = 0, tile_id = 0; j < s->num_tile_rows; j++)\n+\t\tfor (i = 0; i < s->num_tile_columns; i++, tile_id++)\n+\t\t\tfor (y = s->row_bd[j]; y < s->row_bd[j + 1]; y++)\n+\t\t\t\tfor (x = s->col_bd[i];\n+\t\t\t\t     x < s->col_bd[i + 1];\n+\t\t\t\t     x++)\n+\t\t\t\t\ts->tile_id[s->ctb_addr_rs_to_ts\n+\t\t\t\t\t\t\t   [y * s->ctb_width +\n+\t\t\t\t\t\t\t    x]] = tile_id;\n+\n+\treturn 0;\n+}\n+\n+static int frame_end(struct rpivid_dev *const dev,\n+\t\t     struct rpivid_dec_env *const de,\n+\t\t     const struct rpivid_dec_state *const s)\n+{\n+\tconst unsigned int last_x = s->col_bd[s->num_tile_columns] - 1;\n+\tconst unsigned int last_y = s->row_bd[s->num_tile_rows] - 1;\n+\tsize_t cmd_size;\n+\n+\tif (s->pps.flags & V4L2_HEVC_PPS_FLAG_ENTROPY_CODING_SYNC_ENABLED) {\n+\t\tif (de->wpp_entry_x < 2 && de->pic_width_in_ctbs_y > 2)\n+\t\t\twpp_pause(de, last_y);\n+\t}\n+\tp1_apb_write(de, RPI_STATUS, 1 + (last_x << 5) + (last_y << 18));\n+\n+\t// Copy commands out to dma buf\n+\tcmd_size = de->cmd_len * sizeof(de->cmd_fifo[0]);\n+\n+\tif (!de->cmd_copy_gptr->ptr || cmd_size > de->cmd_copy_gptr->size) {\n+\t\tsize_t cmd_alloc = round_up_size(cmd_size);\n+\n+\t\tif (gptr_realloc_new(dev, de->cmd_copy_gptr, cmd_alloc)) {\n+\t\t\tv4l2_err(&dev->v4l2_dev,\n+\t\t\t\t \"Alloc cmd buffer (%d): FAILED\\n\", cmd_alloc);\n+\t\t\treturn -ENOMEM;\n+\t\t}\n+\t\tv4l2_info(&dev->v4l2_dev, \"Alloc cmd buffer (%d): OK\\n\",\n+\t\t\t  cmd_alloc);\n+\t}\n+\n+\tmemcpy(de->cmd_copy_gptr->ptr, de->cmd_fifo, cmd_size);\n+\treturn 0;\n+}\n+\n+static void setup_colmv(struct rpivid_ctx *const ctx, struct rpivid_run *run,\n+\t\t\tstruct rpivid_dec_state *const s)\n+{\n+\tctx->colmv_stride = ALIGN(s->sps.pic_width_in_luma_samples, 64);\n+\tctx->colmv_picsize = ctx->colmv_stride *\n+\t\t(ALIGN(s->sps.pic_height_in_luma_samples, 64) >> 4);\n+}\n+\n+// Can be called from irq context\n+static struct rpivid_dec_env *dec_env_new(struct rpivid_ctx *const ctx)\n+{\n+\tstruct rpivid_dec_env *de;\n+\tunsigned long lock_flags;\n+\n+\tspin_lock_irqsave(&ctx->dec_lock, lock_flags);\n+\n+\tde = ctx->dec_free;\n+\tif (de) {\n+\t\tctx->dec_free = de->next;\n+\t\tde->next = NULL;\n+\t\tde->state = RPIVID_DECODE_SLICE_START;\n+\t}\n+\n+\tspin_unlock_irqrestore(&ctx->dec_lock, lock_flags);\n+\treturn de;\n+}\n+\n+// Can be called from irq context\n+static void dec_env_delete(struct rpivid_dec_env *const de)\n+{\n+\tstruct rpivid_ctx * const ctx = de->ctx;\n+\tunsigned long lock_flags;\n+\n+\taux_q_release(ctx, &de->frame_aux);\n+\taux_q_release(ctx, &de->col_aux);\n+\n+\tspin_lock_irqsave(&ctx->dec_lock, lock_flags);\n+\n+\tde->state = RPIVID_DECODE_END;\n+\tde->next = ctx->dec_free;\n+\tctx->dec_free = de;\n+\n+\tspin_unlock_irqrestore(&ctx->dec_lock, lock_flags);\n+}\n+\n+static void dec_env_uninit(struct rpivid_ctx *const ctx)\n+{\n+\tunsigned int i;\n+\n+\tif (ctx->dec_pool) {\n+\t\tfor (i = 0; i != RPIVID_DEC_ENV_COUNT; ++i) {\n+\t\t\tstruct rpivid_dec_env *const de = ctx->dec_pool + i;\n+\n+\t\t\tkfree(de->cmd_fifo);\n+\t\t}\n+\n+\t\tkfree(ctx->dec_pool);\n+\t}\n+\n+\tctx->dec_pool = NULL;\n+\tctx->dec_free = NULL;\n+}\n+\n+static int dec_env_init(struct rpivid_ctx *const ctx)\n+{\n+\tunsigned int i;\n+\n+\tctx->dec_pool = kzalloc(sizeof(*ctx->dec_pool) * RPIVID_DEC_ENV_COUNT,\n+\t\t\t\tGFP_KERNEL);\n+\tif (!ctx->dec_pool)\n+\t\treturn -1;\n+\n+\tspin_lock_init(&ctx->dec_lock);\n+\n+\t// Build free chain\n+\tctx->dec_free = ctx->dec_pool;\n+\tfor (i = 0; i != RPIVID_DEC_ENV_COUNT - 1; ++i)\n+\t\tctx->dec_pool[i].next = ctx->dec_pool + i + 1;\n+\n+\t// Fill in other bits\n+\tfor (i = 0; i != RPIVID_DEC_ENV_COUNT; ++i) {\n+\t\tstruct rpivid_dec_env *const de = ctx->dec_pool + i;\n+\n+\t\tde->ctx = ctx;\n+\t\tde->decode_order = i;\n+\t\tde->cmd_max = 1024;\n+\t\tde->cmd_fifo = kmalloc_array(de->cmd_max,\n+\t\t\t\t\t     sizeof(struct rpi_cmd),\n+\t\t\t\t\t     GFP_KERNEL);\n+\t\tif (!de->cmd_fifo)\n+\t\t\tgoto fail;\n+\t}\n+\n+\treturn 0;\n+\n+fail:\n+\tdec_env_uninit(ctx);\n+\treturn -1;\n+}\n+\n+// Assume that we get exactly the same DPB for every slice\n+// it makes no real sense otherwise\n+#if V4L2_HEVC_DPB_ENTRIES_NUM_MAX > 16\n+#error HEVC_DPB_ENTRIES > h/w slots\n+#endif\n+\n+static u32 mk_config2(const struct rpivid_dec_state *const s)\n+{\n+\tconst struct v4l2_ctrl_hevc_sps *const sps = &s->sps;\n+\tconst struct v4l2_ctrl_hevc_pps *const pps = &s->pps;\n+\tu32 c;\n+\t// BitDepthY\n+\tc = (sps->bit_depth_luma_minus8 + 8) << 0;\n+\t // BitDepthC\n+\tc |= (sps->bit_depth_chroma_minus8 + 8) << 4;\n+\t // BitDepthY\n+\tif (sps->bit_depth_luma_minus8)\n+\t\tc |= BIT(8);\n+\t// BitDepthC\n+\tif (sps->bit_depth_chroma_minus8)\n+\t\tc |= BIT(9);\n+\tc |= s->log2_ctb_size << 10;\n+\tif (pps->flags & V4L2_HEVC_PPS_FLAG_CONSTRAINED_INTRA_PRED)\n+\t\tc |= BIT(13);\n+\tif (sps->flags & V4L2_HEVC_SPS_FLAG_STRONG_INTRA_SMOOTHING_ENABLED)\n+\t\tc |= BIT(14);\n+\tif (sps->flags & V4L2_HEVC_SPS_FLAG_SPS_TEMPORAL_MVP_ENABLED)\n+\t\tc |= BIT(15); /* Write motion vectors to external memory */\n+\tc |= (pps->log2_parallel_merge_level_minus2 + 2) << 16;\n+\tif (s->slice_temporal_mvp)\n+\t\tc |= BIT(19);\n+\tif (sps->flags & V4L2_HEVC_SPS_FLAG_PCM_LOOP_FILTER_DISABLED)\n+\t\tc |= BIT(20);\n+\tc |= (pps->pps_cb_qp_offset & 31) << 21;\n+\tc |= (pps->pps_cr_qp_offset & 31) << 26;\n+\treturn c;\n+}\n+\n+static void rpivid_h265_setup(struct rpivid_ctx *ctx, struct rpivid_run *run)\n+{\n+\tstruct rpivid_dev *const dev = ctx->dev;\n+\tconst struct v4l2_ctrl_hevc_slice_params *const sh =\n+\t\t\t\t\t\trun->h265.slice_params;\n+\tconst struct v4l2_hevc_pred_weight_table *pred_weight_table;\n+\tstruct rpivid_q_aux *dpb_q_aux[V4L2_HEVC_DPB_ENTRIES_NUM_MAX];\n+\tstruct rpivid_dec_state *const s = ctx->state;\n+\tstruct vb2_queue *vq;\n+\tstruct rpivid_dec_env *de;\n+\tint ctb_addr_ts;\n+\tunsigned int i;\n+\tint use_aux;\n+\tbool slice_temporal_mvp;\n+\n+\tpred_weight_table = &sh->pred_weight_table;\n+\n+\ts->frame_end =\n+\t\t((run->src->flags & V4L2_BUF_FLAG_M2M_HOLD_CAPTURE_BUF) == 0);\n+\n+\tde = ctx->dec0;\n+\tslice_temporal_mvp = (sh->flags &\n+\t\t   V4L2_HEVC_SLICE_PARAMS_FLAG_SLICE_TEMPORAL_MVP_ENABLED);\n+\n+\tif (de && de->state != RPIVID_DECODE_END) {\n+\t\t++s->slice_idx;\n+\n+\t\tswitch (de->state) {\n+\t\tcase RPIVID_DECODE_SLICE_CONTINUE:\n+\t\t\t// Expected state\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tv4l2_err(&dev->v4l2_dev, \"%s: Unexpected state: %d\\n\",\n+\t\t\t\t __func__, de->state);\n+\t\t/* FALLTHRU */\n+\t\tcase RPIVID_DECODE_ERROR_CONTINUE:\n+\t\t\t// Uncleared error - fail now\n+\t\t\tgoto fail;\n+\t\t}\n+\n+\t\tif (s->slice_temporal_mvp != slice_temporal_mvp) {\n+\t\t\tv4l2_warn(&dev->v4l2_dev,\n+\t\t\t\t  \"Slice Temporal MVP non-constant\\n\");\n+\t\t\tgoto fail;\n+\t\t}\n+\t} else {\n+\t\t/* Frame start */\n+\t\tunsigned int ctb_size_y;\n+\t\tbool sps_changed = false;\n+\n+\t\tif (memcmp(&s->sps, run->h265.sps, sizeof(s->sps)) != 0) {\n+\t\t\t/* SPS changed */\n+\t\t\tv4l2_info(&dev->v4l2_dev, \"SPS changed\\n\");\n+\t\t\tmemcpy(&s->sps, run->h265.sps, sizeof(s->sps));\n+\t\t\tsps_changed = true;\n+\t\t}\n+\t\tif (sps_changed ||\n+\t\t    memcmp(&s->pps, run->h265.pps, sizeof(s->pps)) != 0) {\n+\t\t\t/* SPS changed */\n+\t\t\tv4l2_info(&dev->v4l2_dev, \"PPS changed\\n\");\n+\t\t\tmemcpy(&s->pps, run->h265.pps, sizeof(s->pps));\n+\n+\t\t\t/* Recalc stuff as required */\n+\t\t\tupdated_ps(s);\n+\t\t}\n+\n+\t\tde = dec_env_new(ctx);\n+\t\tif (!de) {\n+\t\t\tv4l2_err(&dev->v4l2_dev,\n+\t\t\t\t \"Failed to find free decode env\\n\");\n+\t\t\tgoto fail;\n+\t\t}\n+\t\tctx->dec0 = de;\n+\n+\t\tctb_size_y =\n+\t\t\t1U << (s->sps.log2_min_luma_coding_block_size_minus3 +\n+\t\t\t       3 +\n+\t\t\t       s->sps.log2_diff_max_min_luma_coding_block_size);\n+\n+\t\tde->pic_width_in_ctbs_y =\n+\t\t\t(s->sps.pic_width_in_luma_samples + ctb_size_y - 1) /\n+\t\t\t\tctb_size_y; // 7-15\n+\t\tde->pic_height_in_ctbs_y =\n+\t\t\t(s->sps.pic_height_in_luma_samples + ctb_size_y - 1) /\n+\t\t\t\tctb_size_y; // 7-17\n+\t\tde->cmd_len = 0;\n+\t\tde->dpbno_col = ~0U;\n+\n+\t\tde->bit_copy_gptr = ctx->bitbufs + 0;\n+\t\tde->bit_copy_len = 0;\n+\t\tde->cmd_copy_gptr = ctx->cmdbufs + 0;\n+\n+\t\tde->frame_c_offset = ctx->dst_fmt.height * 128;\n+\t\tde->frame_stride = ctx->dst_fmt.bytesperline * 128;\n+\t\tde->frame_addr =\n+\t\t\tvb2_dma_contig_plane_dma_addr(&run->dst->vb2_buf, 0);\n+\t\tde->frame_aux = NULL;\n+\n+\t\tif (s->sps.bit_depth_luma_minus8 !=\n+\t\t    s->sps.bit_depth_chroma_minus8) {\n+\t\t\tv4l2_warn(&dev->v4l2_dev,\n+\t\t\t\t  \"Chroma depth (%d) != Luma depth (%d)\\n\",\n+\t\t\t\t  s->sps.bit_depth_chroma_minus8 + 8,\n+\t\t\t\t  s->sps.bit_depth_luma_minus8 + 8);\n+\t\t\tgoto fail;\n+\t\t}\n+\t\tif (s->sps.bit_depth_luma_minus8 == 0) {\n+\t\t\tif (ctx->dst_fmt.pixelformat !=\n+\t\t\t\t\t\tV4L2_PIX_FMT_NV12_COL128) {\n+\t\t\t\tv4l2_err(&dev->v4l2_dev,\n+\t\t\t\t\t \"Pixel format %#x != NV12_COL128 for 8-bit output\",\n+\t\t\t\t\t ctx->dst_fmt.pixelformat);\n+\t\t\t\tgoto fail;\n+\t\t\t}\n+\t\t} else if (s->sps.bit_depth_luma_minus8 == 2) {\n+\t\t\tif (ctx->dst_fmt.pixelformat !=\n+\t\t\t\t\t\tV4L2_PIX_FMT_NV12_10_COL128) {\n+\t\t\t\tv4l2_err(&dev->v4l2_dev,\n+\t\t\t\t\t \"Pixel format %#x != NV12_10_COL128 for 10-bit output\",\n+\t\t\t\t\t ctx->dst_fmt.pixelformat);\n+\t\t\t\tgoto fail;\n+\t\t\t}\n+\t\t} else {\n+\t\t\tv4l2_warn(&dev->v4l2_dev,\n+\t\t\t\t  \"Luma depth (%d) unsupported\\n\",\n+\t\t\t\t  s->sps.bit_depth_luma_minus8 + 8);\n+\t\t\tgoto fail;\n+\t\t}\n+\t\tif (run->dst->vb2_buf.num_planes != 1) {\n+\t\t\tv4l2_warn(&dev->v4l2_dev, \"Capture planes (%d) != 1\\n\",\n+\t\t\t\t  run->dst->vb2_buf.num_planes);\n+\t\t\tgoto fail;\n+\t\t}\n+\t\tif (run->dst->planes[0].length <\n+\t\t    ctx->dst_fmt.sizeimage) {\n+\t\t\tv4l2_warn(&dev->v4l2_dev,\n+\t\t\t\t  \"Capture plane[0] length (%d) < sizeimage (%d)\\n\",\n+\t\t\t\t  run->dst->planes[0].length,\n+\t\t\t\t  ctx->dst_fmt.sizeimage);\n+\t\t\tgoto fail;\n+\t\t}\n+\n+\t\tif (s->sps.pic_width_in_luma_samples > 4096 ||\n+\t\t    s->sps.pic_height_in_luma_samples > 4096) {\n+\t\t\tv4l2_warn(&dev->v4l2_dev,\n+\t\t\t\t  \"Pic dimension (%dx%d) exeeds 4096\\n\",\n+\t\t\t\t  s->sps.pic_width_in_luma_samples,\n+\t\t\t\t  s->sps.pic_height_in_luma_samples);\n+\t\t\tgoto fail;\n+\t\t}\n+\n+\t\t// Fill in ref planes with our address s.t. if we mess\n+\t\t// up refs somehow then we still have a valid address\n+\t\t// entry\n+\t\tfor (i = 0; i != 16; ++i)\n+\t\t\tde->ref_addrs[i] = de->frame_addr;\n+\n+\t\t/*\n+\t\t * Stash initial temporal_mvp flag\n+\t\t * This must be the same for all pic slices (7.4.7.1)\n+\t\t */\n+\t\ts->slice_temporal_mvp = slice_temporal_mvp;\n+\n+\t\t// Phase 2 reg pre-calc\n+\t\tde->rpi_config2 = mk_config2(s);\n+\t\tde->rpi_framesize = (s->sps.pic_height_in_luma_samples << 16) |\n+\t\t\t\t    s->sps.pic_width_in_luma_samples;\n+\t\tde->rpi_currpoc = sh->slice_pic_order_cnt;\n+\n+\t\tif (s->sps.flags &\n+\t\t    V4L2_HEVC_SPS_FLAG_SPS_TEMPORAL_MVP_ENABLED) {\n+\t\t\tsetup_colmv(ctx, run, s);\n+\t\t}\n+\n+\t\ts->slice_idx = 0;\n+\n+\t\tif (sh->slice_segment_addr != 0) {\n+\t\t\tv4l2_warn(&dev->v4l2_dev,\n+\t\t\t\t  \"New frame but segment_addr=%d\\n\",\n+\t\t\t\t  sh->slice_segment_addr);\n+\t\t\tgoto fail;\n+\t\t}\n+\n+\t\t/* Allocate a bitbuf if we need one - don't need one if single\n+\t\t * slice as we can use the src buf directly\n+\t\t */\n+\t\tif (!s->frame_end && !de->bit_copy_gptr->ptr) {\n+\t\t\tconst size_t wxh = s->sps.pic_width_in_luma_samples *\n+\t\t\t\ts->sps.pic_height_in_luma_samples;\n+\t\t\tsize_t bits_alloc;\n+\n+\t\t\t/* Annex A gives a min compression of 2 @ lvl 3.1\n+\t\t\t * (wxh <= 983040) and min 4 thereafter but avoid\n+\t\t\t * the odity of 983041 having a lower limit than\n+\t\t\t * 983040.\n+\t\t\t * Multiply by 3/2 for 4:2:0\n+\t\t\t */\n+\t\t\tbits_alloc = wxh < 983040 ? wxh * 3 / 4 :\n+\t\t\t\twxh < 983040 * 2 ? 983040 * 3 / 4 :\n+\t\t\t\twxh * 3 / 8;\n+\t\t\tbits_alloc = round_up_size(bits_alloc);\n+\n+\t\t\tif (gptr_alloc(dev, de->bit_copy_gptr,\n+\t\t\t\t       bits_alloc,\n+\t\t\t\t       DMA_ATTR_FORCE_CONTIGUOUS) != 0) {\n+\t\t\t\tv4l2_err(&dev->v4l2_dev,\n+\t\t\t\t\t \"Unable to alloc buf (%d) for bit copy\\n\",\n+\t\t\t\t\t bits_alloc);\n+\t\t\t\tgoto fail;\n+\t\t\t}\n+\t\t\tv4l2_info(&dev->v4l2_dev,\n+\t\t\t\t  \"Alloc buf (%d) for bit copy OK\\n\",\n+\t\t\t\t  bits_alloc);\n+\t\t}\n+\t}\n+\n+\t// Pre calc a few things\n+\ts->src_addr =\n+\t\t!s->frame_end ?\n+\t\t\t0 :\n+\t\t\tvb2_dma_contig_plane_dma_addr(&run->src->vb2_buf, 0);\n+\ts->src_buf = s->src_addr != 0 ? NULL :\n+\t\t\t\t\tvb2_plane_vaddr(&run->src->vb2_buf, 0);\n+\tif (!s->src_addr && !s->src_buf) {\n+\t\tv4l2_err(&dev->v4l2_dev, \"Failed to map src buffer\\n\");\n+\t\tgoto fail;\n+\t}\n+\n+\ts->sh = sh;\n+\ts->slice_qp = 26 + s->pps.init_qp_minus26 + s->sh->slice_qp_delta;\n+\ts->max_num_merge_cand = sh->slice_type == HEVC_SLICE_I ?\n+\t\t\t\t\t0 :\n+\t\t\t\t\t(5 - sh->five_minus_max_num_merge_cand);\n+\t// * SH DSS flag invented by me - but clearly needed\n+\ts->dependent_slice_segment_flag =\n+\t\t((sh->flags &\n+\t\t  V4L2_HEVC_SLICE_PARAMS_FLAG_DEPENDENT_SLICE_SEGMENT) != 0);\n+\n+\ts->nb_refs[0] = (sh->slice_type == HEVC_SLICE_I) ?\n+\t\t\t\t0 :\n+\t\t\t\tsh->num_ref_idx_l0_active_minus1 + 1;\n+\ts->nb_refs[1] = (sh->slice_type != HEVC_SLICE_B) ?\n+\t\t\t\t0 :\n+\t\t\t\tsh->num_ref_idx_l1_active_minus1 + 1;\n+\n+\tif (s->sps.flags & V4L2_HEVC_SPS_FLAG_SCALING_LIST_ENABLED)\n+\t\tpopulate_scaling_factors(run, de, s);\n+\n+\tctb_addr_ts = s->ctb_addr_rs_to_ts[sh->slice_segment_addr];\n+\n+\tif ((s->pps.flags & V4L2_HEVC_PPS_FLAG_ENTROPY_CODING_SYNC_ENABLED))\n+\t\twpp_decode_slice(de, s, sh, ctb_addr_ts);\n+\telse\n+\t\tdecode_slice(de, s, sh, ctb_addr_ts);\n+\n+\tif (!s->frame_end)\n+\t\treturn;\n+\n+\t// Frame end\n+\tmemset(dpb_q_aux, 0,\n+\t       sizeof(*dpb_q_aux) * V4L2_HEVC_DPB_ENTRIES_NUM_MAX);\n+\t/*\n+\t * Need Aux ents for all (ref) DPB ents if temporal MV could\n+\t * be enabled for any pic\n+\t * ** At the moment we have aux ents for all pics whether or not\n+\t *    they are ref\n+\t */\n+\tuse_aux = ((s->sps.flags &\n+\t\t  V4L2_HEVC_SPS_FLAG_SPS_TEMPORAL_MVP_ENABLED) != 0);\n+\n+\t// Locate ref frames\n+\t// At least in the current implementation this is constant across all\n+\t// slices. If this changes we will need idx mapping code.\n+\t// Uses sh so here rather than trigger\n+\n+\tvq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);\n+\n+\tif (!vq) {\n+\t\tv4l2_err(&dev->v4l2_dev, \"VQ gone!\\n\");\n+\t\tgoto fail;\n+\t}\n+\n+\t//        v4l2_info(&dev->v4l2_dev, \"rpivid_h265_end of frame\\n\");\n+\tif (frame_end(dev, de, s))\n+\t\tgoto fail;\n+\n+\tfor (i = 0; i < sh->num_active_dpb_entries; ++i) {\n+\t\tint buffer_index =\n+\t\t\tvb2_find_timestamp(vq, sh->dpb[i].timestamp, 0);\n+\t\tstruct vb2_buffer *buf = buffer_index < 0 ?\n+\t\t\t\t\tNULL :\n+\t\t\t\t\tvb2_get_buffer(vq, buffer_index);\n+\n+\t\tif (!buf) {\n+\t\t\tv4l2_warn(&dev->v4l2_dev,\n+\t\t\t\t  \"Missing DPB ent %d, timestamp=%lld, index=%d\\n\",\n+\t\t\t\t  i, (long long)sh->dpb[i].timestamp,\n+\t\t\t\t  buffer_index);\n+\t\t\tcontinue;\n+\t\t}\n+\n+\t\tif (use_aux) {\n+\t\t\tdpb_q_aux[i] = aux_q_ref(ctx,\n+\t\t\t\t\t\t ctx->aux_ents[buffer_index]);\n+\t\t\tif (!dpb_q_aux[i])\n+\t\t\t\tv4l2_warn(&dev->v4l2_dev,\n+\t\t\t\t\t  \"Missing DPB AUX ent %d index=%d\\n\",\n+\t\t\t\t\t  i, buffer_index);\n+\t\t}\n+\n+\t\tde->ref_addrs[i] =\n+\t\t\tvb2_dma_contig_plane_dma_addr(buf, 0);\n+\t}\n+\n+\t// Move DPB from temp\n+\tfor (i = 0; i != V4L2_HEVC_DPB_ENTRIES_NUM_MAX; ++i) {\n+\t\taux_q_release(ctx, &s->ref_aux[i]);\n+\t\ts->ref_aux[i] = dpb_q_aux[i];\n+\t}\n+\t// Unref the old frame aux too - it is either in the DPB or not\n+\t// now\n+\taux_q_release(ctx, &s->frame_aux);\n+\n+\tif (use_aux) {\n+\t\t// New frame so new aux ent\n+\t\t// ??? Do we need this if non-ref ??? can we tell\n+\t\ts->frame_aux = aux_q_new(ctx, run->dst->vb2_buf.index);\n+\n+\t\tif (!s->frame_aux) {\n+\t\t\tv4l2_err(&dev->v4l2_dev,\n+\t\t\t\t \"Failed to obtain aux storage for frame\\n\");\n+\t\t\tgoto fail;\n+\t\t}\n+\n+\t\tde->frame_aux = aux_q_ref(ctx, s->frame_aux);\n+\t}\n+\n+\tif (de->dpbno_col != ~0U) {\n+\t\tif (de->dpbno_col >= sh->num_active_dpb_entries) {\n+\t\t\tv4l2_err(&dev->v4l2_dev,\n+\t\t\t\t \"Col ref index %d >= %d\\n\",\n+\t\t\t\t de->dpbno_col,\n+\t\t\t\t sh->num_active_dpb_entries);\n+\t\t} else {\n+\t\t\t// Standard requires that the col pic is\n+\t\t\t// constant for the duration of the pic\n+\t\t\t// (text of collocated_ref_idx in H265-2 2018\n+\t\t\t// 7.4.7.1)\n+\n+\t\t\t// Spot the collocated ref in passing\n+\t\t\tde->col_aux = aux_q_ref(ctx,\n+\t\t\t\t\t\tdpb_q_aux[de->dpbno_col]);\n+\n+\t\t\tif (!de->col_aux) {\n+\t\t\t\tv4l2_warn(&dev->v4l2_dev,\n+\t\t\t\t\t  \"Missing DPB ent for col\\n\");\n+\t\t\t\t// Probably need to abort if this fails\n+\t\t\t\t// as P2 may explode on bad data\n+\t\t\t\tgoto fail;\n+\t\t\t}\n+\t\t}\n+\t}\n+\n+\tde->state = RPIVID_DECODE_PHASE1;\n+\treturn;\n+\n+fail:\n+\tif (de)\n+\t\t// Actual error reporting happens in Trigger\n+\t\tde->state = s->frame_end ? RPIVID_DECODE_ERROR_DONE :\n+\t\t\t\t\t   RPIVID_DECODE_ERROR_CONTINUE;\n+}\n+\n+//////////////////////////////////////////////////////////////////////////////\n+// Handle PU and COEFF stream overflow\n+\n+// Returns:\n+// -1  Phase 1 decode error\n+//  0  OK\n+// >0  Out of space (bitmask)\n+\n+#define STATUS_COEFF_EXHAUSTED\t8\n+#define STATUS_PU_EXHAUSTED\t16\n+\n+static int check_status(const struct rpivid_dev *const dev)\n+{\n+\tconst u32 cfstatus = apb_read(dev, RPI_CFSTATUS);\n+\tconst u32 cfnum = apb_read(dev, RPI_CFNUM);\n+\tu32 status = apb_read(dev, RPI_STATUS);\n+\n+\t// Handle PU and COEFF stream overflow\n+\n+\t// this is the definition of successful completion of phase 1\n+\t// it assures that status register is zero and all blocks in each tile\n+\t// have completed\n+\tif (cfstatus == cfnum)\n+\t\treturn 0;\t//No error\n+\n+\tstatus &= (STATUS_PU_EXHAUSTED | STATUS_COEFF_EXHAUSTED);\n+\tif (status)\n+\t\treturn status;\n+\n+\treturn -1;\n+}\n+\n+static void cb_phase2(struct rpivid_dev *const dev, void *v)\n+{\n+\tstruct rpivid_dec_env *const de = v;\n+\tstruct rpivid_ctx *const ctx = de->ctx;\n+\n+\txtrace_in(dev, de);\n+\n+\tv4l2_m2m_cap_buf_return(dev->m2m_dev, ctx->fh.m2m_ctx, de->frame_buf,\n+\t\t\t\tVB2_BUF_STATE_DONE);\n+\tde->frame_buf = NULL;\n+\n+\t/* Delete de before finish as finish might immediately trigger a reuse\n+\t * of de\n+\t */\n+\tdec_env_delete(de);\n+\n+\tif (atomic_add_return(-1, &ctx->p2out) >= RPIVID_P2BUF_COUNT - 1) {\n+\t\txtrace_fin(dev, de);\n+\t\tv4l2_m2m_buf_done_and_job_finish(dev->m2m_dev, ctx->fh.m2m_ctx,\n+\t\t\t\t\t\t VB2_BUF_STATE_DONE);\n+\t}\n+\n+\txtrace_ok(dev, de);\n+}\n+\n+static void phase2_claimed(struct rpivid_dev *const dev, void *v)\n+{\n+\tstruct rpivid_dec_env *const de = v;\n+\tunsigned int i;\n+\n+\txtrace_in(dev, de);\n+\n+\tapb_write_vc_addr(dev, RPI_PURBASE, de->pu_base_vc);\n+\tapb_write_vc_len(dev, RPI_PURSTRIDE, de->pu_stride);\n+\tapb_write_vc_addr(dev, RPI_COEFFRBASE, de->coeff_base_vc);\n+\tapb_write_vc_len(dev, RPI_COEFFRSTRIDE, de->coeff_stride);\n+\n+\tapb_write_vc_addr(dev, RPI_OUTYBASE, de->frame_addr);\n+\tapb_write_vc_addr(dev, RPI_OUTCBASE,\n+\t\t\t  de->frame_addr + de->frame_c_offset);\n+\tapb_write_vc_len(dev, RPI_OUTYSTRIDE, de->frame_stride);\n+\tapb_write_vc_len(dev, RPI_OUTCSTRIDE, de->frame_stride);\n+\n+\t//    v4l2_info(&dev->v4l2_dev, \"Frame: Y=%llx, C=%llx, Stride=%x\\n\",\n+\t//              de->frame_addr, de->frame_addr + de->frame_c_offset,\n+\t//              de->frame_stride);\n+\n+\tfor (i = 0; i < 16; i++) {\n+\t\t// Strides are in fact unused but fill in anyway\n+\t\tapb_write_vc_addr(dev, 0x9000 + 16 * i, de->ref_addrs[i]);\n+\t\tapb_write_vc_len(dev, 0x9004 + 16 * i, de->frame_stride);\n+\t\tapb_write_vc_addr(dev, 0x9008 + 16 * i,\n+\t\t\t\t  de->ref_addrs[i] + de->frame_c_offset);\n+\t\tapb_write_vc_len(dev, 0x900C + 16 * i, de->frame_stride);\n+\t}\n+\n+\tapb_write(dev, RPI_CONFIG2, de->rpi_config2);\n+\tapb_write(dev, RPI_FRAMESIZE, de->rpi_framesize);\n+\tapb_write(dev, RPI_CURRPOC, de->rpi_currpoc);\n+\t//    v4l2_info(&dev->v4l2_dev, \"Config2=%#x, FrameSize=%#x, POC=%#x\\n\",\n+\t//    de->rpi_config2, de->rpi_framesize, de->rpi_currpoc);\n+\n+\t// collocated reads/writes\n+\tapb_write_vc_len(dev, RPI_COLSTRIDE,\n+\t\t\t de->ctx->colmv_stride); // Read vals\n+\tapb_write_vc_len(dev, RPI_MVSTRIDE,\n+\t\t\t de->ctx->colmv_stride); // Write vals\n+\tapb_write_vc_addr(dev, RPI_MVBASE,\n+\t\t\t  !de->frame_aux ? 0 : de->frame_aux->col.addr);\n+\tapb_write_vc_addr(dev, RPI_COLBASE,\n+\t\t\t  !de->col_aux ? 0 : de->col_aux->col.addr);\n+\n+\t//v4l2_info(&dev->v4l2_dev,\n+\t//\t   \"Mv=%llx, Col=%llx, Stride=%x, Buf=%llx->%llx\\n\",\n+\t//\t   de->rpi_mvbase, de->rpi_colbase, de->ctx->colmv_stride,\n+\t//\t   de->ctx->colmvbuf.addr, de->ctx->colmvbuf.addr +\n+\t//\t   de->ctx->colmvbuf.size);\n+\n+\trpivid_hw_irq_active2_irq(dev, &de->irq_ent, cb_phase2, de);\n+\n+\tapb_write_final(dev, RPI_NUMROWS, de->pic_height_in_ctbs_y);\n+\n+\txtrace_ok(dev, de);\n+}\n+\n+static void phase1_claimed(struct rpivid_dev *const dev, void *v);\n+\n+static void phase1_thread(struct rpivid_dev *const dev, void *v)\n+{\n+\tstruct rpivid_dec_env *const de = v;\n+\tstruct rpivid_ctx *const ctx = de->ctx;\n+\n+\tstruct rpivid_gptr *const pu_gptr = ctx->pu_bufs + ctx->p2idx;\n+\tstruct rpivid_gptr *const coeff_gptr = ctx->coeff_bufs + ctx->p2idx;\n+\n+\txtrace_in(dev, de);\n+\n+\tif (de->p1_status & STATUS_PU_EXHAUSTED) {\n+\t\tif (gptr_realloc_new(dev, pu_gptr, next_size(pu_gptr->size))) {\n+\t\t\tv4l2_err(&dev->v4l2_dev,\n+\t\t\t\t \"%s: PU realloc (%#x) failed\\n\",\n+\t\t\t\t __func__, pu_gptr->size);\n+\t\t\tgoto fail;\n+\t\t}\n+\t\tv4l2_info(&dev->v4l2_dev, \"%s: PU realloc (%#x) OK\\n\",\n+\t\t\t  __func__, pu_gptr->size);\n+\t}\n+\n+\tif (de->p1_status & STATUS_COEFF_EXHAUSTED) {\n+\t\tif (gptr_realloc_new(dev, coeff_gptr,\n+\t\t\t\t     next_size(coeff_gptr->size))) {\n+\t\t\tv4l2_err(&dev->v4l2_dev,\n+\t\t\t\t \"%s: Coeff realloc (%#x) failed\\n\",\n+\t\t\t\t __func__, coeff_gptr->size);\n+\t\t\tgoto fail;\n+\t\t}\n+\t\tv4l2_info(&dev->v4l2_dev, \"%s: Coeff realloc (%#x) OK\\n\",\n+\t\t\t  __func__, coeff_gptr->size);\n+\t}\n+\n+\tphase1_claimed(dev, de);\n+\txtrace_ok(dev, de);\n+\treturn;\n+\n+fail:\n+\tdec_env_delete(de);\n+\txtrace_fin(dev, de);\n+\tv4l2_m2m_buf_done_and_job_finish(dev->m2m_dev, ctx->fh.m2m_ctx,\n+\t\t\t\t\t VB2_BUF_STATE_ERROR);\n+\txtrace_fail(dev, de);\n+}\n+\n+/* Always called in irq context (this is good) */\n+static void cb_phase1(struct rpivid_dev *const dev, void *v)\n+{\n+\tstruct rpivid_dec_env *const de = v;\n+\tstruct rpivid_ctx *const ctx = de->ctx;\n+\n+\txtrace_in(dev, de);\n+\n+\tde->p1_status = check_status(dev);\n+\tif (de->p1_status != 0) {\n+\t\tv4l2_info(&dev->v4l2_dev, \"%s: Post wait: %#x\\n\",\n+\t\t\t  __func__, de->p1_status);\n+\n+\t\tif (de->p1_status < 0)\n+\t\t\tgoto fail;\n+\n+\t\t/* Need to realloc - push onto a thread rather than IRQ */\n+\t\trpivid_hw_irq_active1_thread(dev, &de->irq_ent,\n+\t\t\t\t\t     phase1_thread, de);\n+\t\treturn;\n+\t}\n+\n+\t/* After the frame-buf is detached it must be returned but from\n+\t * this point onward (phase2_claimed, cb_phase2) there are no error\n+\t * paths so the return at the end of cb_phase2 is all that is needed\n+\t */\n+\tde->frame_buf = v4l2_m2m_cap_buf_detach(dev->m2m_dev, ctx->fh.m2m_ctx);\n+\tif (!de->frame_buf) {\n+\t\tv4l2_err(&dev->v4l2_dev, \"%s: No detached buffer\\n\", __func__);\n+\t\tgoto fail;\n+\t}\n+\n+\tctx->p2idx =\n+\t\t(ctx->p2idx + 1 >= RPIVID_P2BUF_COUNT) ? 0 : ctx->p2idx + 1;\n+\n+\t// Enable the next setup if our Q isn't too big\n+\tif (atomic_add_return(1, &ctx->p2out) < RPIVID_P2BUF_COUNT) {\n+\t\txtrace_fin(dev, de);\n+\t\tv4l2_m2m_buf_done_and_job_finish(dev->m2m_dev, ctx->fh.m2m_ctx,\n+\t\t\t\t\t\t VB2_BUF_STATE_DONE);\n+\t}\n+\n+\trpivid_hw_irq_active2_claim(dev, &de->irq_ent, phase2_claimed, de);\n+\n+\txtrace_ok(dev, de);\n+\treturn;\n+\n+fail:\n+\tdec_env_delete(de);\n+\txtrace_fin(dev, de);\n+\tv4l2_m2m_buf_done_and_job_finish(dev->m2m_dev, ctx->fh.m2m_ctx,\n+\t\t\t\t\t VB2_BUF_STATE_ERROR);\n+\txtrace_fail(dev, de);\n+}\n+\n+static void phase1_claimed(struct rpivid_dev *const dev, void *v)\n+{\n+\tstruct rpivid_dec_env *const de = v;\n+\tstruct rpivid_ctx *const ctx = de->ctx;\n+\n+\tconst struct rpivid_gptr * const pu_gptr = ctx->pu_bufs + ctx->p2idx;\n+\tconst struct rpivid_gptr * const coeff_gptr = ctx->coeff_bufs +\n+\t\t\t\t\t\t      ctx->p2idx;\n+\n+\txtrace_in(dev, de);\n+\n+\tde->pu_base_vc = pu_gptr->addr;\n+\tde->pu_stride =\n+\t\tALIGN_DOWN(pu_gptr->size / de->pic_height_in_ctbs_y, 64);\n+\n+\tde->coeff_base_vc = coeff_gptr->addr;\n+\tde->coeff_stride =\n+\t\tALIGN_DOWN(coeff_gptr->size / de->pic_height_in_ctbs_y, 64);\n+\n+\tapb_write_vc_addr(dev, RPI_PUWBASE, de->pu_base_vc);\n+\tapb_write_vc_len(dev, RPI_PUWSTRIDE, de->pu_stride);\n+\tapb_write_vc_addr(dev, RPI_COEFFWBASE, de->coeff_base_vc);\n+\tapb_write_vc_len(dev, RPI_COEFFWSTRIDE, de->coeff_stride);\n+\n+\t// Trigger command FIFO\n+\tapb_write(dev, RPI_CFNUM, de->cmd_len);\n+\n+\t// Claim irq\n+\trpivid_hw_irq_active1_irq(dev, &de->irq_ent, cb_phase1, de);\n+\n+\t// And start the h/w\n+\tapb_write_vc_addr_final(dev, RPI_CFBASE, de->cmd_copy_gptr->addr);\n+\n+\txtrace_ok(dev, de);\n+}\n+\n+static void dec_state_delete(struct rpivid_ctx *const ctx)\n+{\n+\tunsigned int i;\n+\tstruct rpivid_dec_state *const s = ctx->state;\n+\n+\tif (!s)\n+\t\treturn;\n+\tctx->state = NULL;\n+\n+\tfree_ps_info(s);\n+\n+\tfor (i = 0; i != HEVC_MAX_REFS; ++i)\n+\t\taux_q_release(ctx, &s->ref_aux[i]);\n+\taux_q_release(ctx, &s->frame_aux);\n+\n+\tkfree(s);\n+}\n+\n+static void rpivid_h265_stop(struct rpivid_ctx *ctx)\n+{\n+\tstruct rpivid_dev *const dev = ctx->dev;\n+\tunsigned int i;\n+\n+\tv4l2_info(&dev->v4l2_dev, \"%s\\n\", __func__);\n+\n+\tdec_env_uninit(ctx);\n+\tdec_state_delete(ctx);\n+\n+\t// dec_env & state must be killed before this to release the buffer to\n+\t// the free pool\n+\taux_q_uninit(ctx);\n+\n+\tfor (i = 0; i != ARRAY_SIZE(ctx->bitbufs); ++i)\n+\t\tgptr_free(dev, ctx->bitbufs + i);\n+\tfor (i = 0; i != ARRAY_SIZE(ctx->cmdbufs); ++i)\n+\t\tgptr_free(dev, ctx->cmdbufs + i);\n+\tfor (i = 0; i != ARRAY_SIZE(ctx->pu_bufs); ++i)\n+\t\tgptr_free(dev, ctx->pu_bufs + i);\n+\tfor (i = 0; i != ARRAY_SIZE(ctx->coeff_bufs); ++i)\n+\t\tgptr_free(dev, ctx->coeff_bufs + i);\n+}\n+\n+static int rpivid_h265_start(struct rpivid_ctx *ctx)\n+{\n+\tstruct rpivid_dev *const dev = ctx->dev;\n+\tunsigned int i;\n+\n+\tunsigned int w = ctx->dst_fmt.width;\n+\tunsigned int h = ctx->dst_fmt.height;\n+\tunsigned int wxh;\n+\tsize_t pu_alloc;\n+\tsize_t coeff_alloc;\n+\n+\t// Generate a sanitised WxH for memory alloc\n+\t// Assume HD if unset\n+\tif (w == 0)\n+\t\tw = 1920;\n+\tif (w > 4096)\n+\t\tw = 4096;\n+\tif (h == 0)\n+\t\tw = 1088;\n+\tif (h > 4096)\n+\t\th = 4096;\n+\twxh = w * h;\n+\n+\tv4l2_info(&dev->v4l2_dev, \"%s: (%dx%d)\\n\", __func__,\n+\t\t  ctx->dst_fmt.width, ctx->dst_fmt.height);\n+\n+\tctx->dec0 = NULL;\n+\tctx->state = kzalloc(sizeof(*ctx->state), GFP_KERNEL);\n+\tif (!ctx->state) {\n+\t\tv4l2_err(&dev->v4l2_dev, \"Failed to allocate decode state\\n\");\n+\t\tgoto fail;\n+\t}\n+\n+\tif (dec_env_init(ctx) != 0) {\n+\t\tv4l2_err(&dev->v4l2_dev, \"Failed to allocate decode envs\\n\");\n+\t\tgoto fail;\n+\t}\n+\n+\t// 16k is plenty for most purposes but we will realloc if needed\n+\tfor (i = 0; i != ARRAY_SIZE(ctx->cmdbufs); ++i) {\n+\t\tif (gptr_alloc(dev, ctx->cmdbufs + i, 0x4000,\n+\t\t\t       DMA_ATTR_FORCE_CONTIGUOUS))\n+\t\t\tgoto fail;\n+\t}\n+\n+\t// Finger in the air PU & Coeff alloc\n+\t// Will be realloced if too small\n+\tcoeff_alloc = round_up_size(wxh);\n+\tpu_alloc = round_up_size(wxh / 4);\n+\tfor (i = 0; i != ARRAY_SIZE(ctx->pu_bufs); ++i) {\n+\t\t// Don't actually need a kernel mapping here\n+\t\tif (gptr_alloc(dev, ctx->pu_bufs + i, pu_alloc,\n+\t\t\t       DMA_ATTR_FORCE_CONTIGUOUS |\n+\t\t\t\t\tDMA_ATTR_NO_KERNEL_MAPPING))\n+\t\t\tgoto fail;\n+\t\tif (gptr_alloc(dev, ctx->coeff_bufs + i, coeff_alloc,\n+\t\t\t       DMA_ATTR_FORCE_CONTIGUOUS |\n+\t\t\t\t\tDMA_ATTR_NO_KERNEL_MAPPING))\n+\t\t\tgoto fail;\n+\t}\n+\taux_q_init(ctx);\n+\n+\treturn 0;\n+\n+fail:\n+\trpivid_h265_stop(ctx);\n+\treturn -ENOMEM;\n+}\n+\n+static void rpivid_h265_trigger(struct rpivid_ctx *ctx)\n+{\n+\tstruct rpivid_dev *const dev = ctx->dev;\n+\tstruct rpivid_dec_env *const de = ctx->dec0;\n+\n+\txtrace_in(dev, de);\n+\n+\tswitch (!de ? RPIVID_DECODE_ERROR_CONTINUE : de->state) {\n+\tcase RPIVID_DECODE_SLICE_START:\n+\t\tde->state = RPIVID_DECODE_SLICE_CONTINUE;\n+\t/* FALLTHRU */\n+\tcase RPIVID_DECODE_SLICE_CONTINUE:\n+\t\tv4l2_m2m_buf_done_and_job_finish(dev->m2m_dev, ctx->fh.m2m_ctx,\n+\t\t\t\t\t\t VB2_BUF_STATE_DONE);\n+\t\tbreak;\n+\tdefault:\n+\t\tv4l2_err(&dev->v4l2_dev, \"%s: Unexpected state: %d\\n\", __func__,\n+\t\t\t de->state);\n+\t/* FALLTHRU */\n+\tcase RPIVID_DECODE_ERROR_DONE:\n+\t\tctx->dec0 = NULL;\n+\t\tdec_env_delete(de);\n+\t/* FALLTHRU */\n+\tcase RPIVID_DECODE_ERROR_CONTINUE:\n+\t\txtrace_fin(dev, de);\n+\t\tv4l2_m2m_buf_done_and_job_finish(dev->m2m_dev, ctx->fh.m2m_ctx,\n+\t\t\t\t\t\t VB2_BUF_STATE_ERROR);\n+\t\tbreak;\n+\tcase RPIVID_DECODE_PHASE1:\n+\t\tctx->dec0 = NULL;\n+\t\trpivid_hw_irq_active1_claim(dev, &de->irq_ent, phase1_claimed,\n+\t\t\t\t\t    de);\n+\t\tbreak;\n+\t}\n+\n+\txtrace_ok(dev, de);\n+}\n+\n+struct rpivid_dec_ops rpivid_dec_ops_h265 = {\n+\t.setup = rpivid_h265_setup,\n+\t.start = rpivid_h265_start,\n+\t.stop = rpivid_h265_stop,\n+\t.trigger = rpivid_h265_trigger,\n+};\n--- /dev/null\n+++ b/drivers/staging/media/rpivid/rpivid_hw.c\n@@ -0,0 +1,321 @@\n+// SPDX-License-Identifier: GPL-2.0\n+/*\n+ * Raspberry Pi HEVC driver\n+ *\n+ * Copyright (C) 2020 Raspberry Pi (Trading) Ltd\n+ *\n+ * Based on the Cedrus VPU driver, that is:\n+ *\n+ * Copyright (C) 2016 Florent Revest <florent.revest@free-electrons.com>\n+ * Copyright (C) 2018 Paul Kocialkowski <paul.kocialkowski@bootlin.com>\n+ * Copyright (C) 2018 Bootlin\n+ */\n+#include <linux/clk.h>\n+#include <linux/component.h>\n+#include <linux/dma-mapping.h>\n+#include <linux/interrupt.h>\n+#include <linux/io.h>\n+#include <linux/of_reserved_mem.h>\n+#include <linux/of_device.h>\n+#include <linux/of_platform.h>\n+#include <linux/platform_device.h>\n+#include <linux/regmap.h>\n+#include <linux/reset.h>\n+\n+#include <media/videobuf2-core.h>\n+#include <media/v4l2-mem2mem.h>\n+\n+#include \"rpivid.h\"\n+#include \"rpivid_hw.h\"\n+\n+static void pre_irq(struct rpivid_dev *dev, struct rpivid_hw_irq_ent *ient,\n+\t\t    rpivid_irq_callback cb, void *v,\n+\t\t    struct rpivid_hw_irq_ctrl *ictl)\n+{\n+\tunsigned long flags;\n+\n+\tif (ictl->irq) {\n+\t\tv4l2_err(&dev->v4l2_dev, \"Attempt to claim IRQ when already claimed\\n\");\n+\t\treturn;\n+\t}\n+\n+\tient->cb = cb;\n+\tient->v = v;\n+\n+\t// Not sure this lock is actually required\n+\tspin_lock_irqsave(&ictl->lock, flags);\n+\tictl->irq = ient;\n+\tspin_unlock_irqrestore(&ictl->lock, flags);\n+}\n+\n+static void sched_claim(struct rpivid_dev * const dev,\n+\t\t\tstruct rpivid_hw_irq_ctrl * const ictl)\n+{\n+\tfor (;;) {\n+\t\tstruct rpivid_hw_irq_ent *ient = NULL;\n+\t\tunsigned long flags;\n+\n+\t\tspin_lock_irqsave(&ictl->lock, flags);\n+\n+\t\tif (--ictl->no_sched <= 0) {\n+\t\t\tient = ictl->claim;\n+\t\t\tif (!ictl->irq && ient) {\n+\t\t\t\tictl->claim = ient->next;\n+\t\t\t\tictl->no_sched = 1;\n+\t\t\t}\n+\t\t}\n+\n+\t\tspin_unlock_irqrestore(&ictl->lock, flags);\n+\n+\t\tif (!ient)\n+\t\t\tbreak;\n+\n+\t\tient->cb(dev, ient->v);\n+\t}\n+}\n+\n+/* Should only ever be called from its own IRQ cb so no lock required */\n+static void pre_thread(struct rpivid_dev *dev,\n+\t\t       struct rpivid_hw_irq_ent *ient,\n+\t\t       rpivid_irq_callback cb, void *v,\n+\t\t       struct rpivid_hw_irq_ctrl *ictl)\n+{\n+\tient->cb = cb;\n+\tient->v = v;\n+\tictl->irq = ient;\n+\tictl->thread_reqed = true;\n+\tictl->no_sched++;\n+}\n+\n+// Called in irq context\n+static void do_irq(struct rpivid_dev * const dev,\n+\t\t   struct rpivid_hw_irq_ctrl * const ictl)\n+{\n+\tstruct rpivid_hw_irq_ent *ient;\n+\tunsigned long flags;\n+\n+\tspin_lock_irqsave(&ictl->lock, flags);\n+\tient = ictl->irq;\n+\tif (ient) {\n+\t\tictl->no_sched++;\n+\t\tictl->irq = NULL;\n+\t}\n+\tspin_unlock_irqrestore(&ictl->lock, flags);\n+\n+\tif (ient) {\n+\t\tient->cb(dev, ient->v);\n+\n+\t\tsched_claim(dev, ictl);\n+\t}\n+}\n+\n+static void do_claim(struct rpivid_dev * const dev,\n+\t\t     struct rpivid_hw_irq_ent *ient,\n+\t\t     const rpivid_irq_callback cb, void * const v,\n+\t\t     struct rpivid_hw_irq_ctrl * const ictl)\n+{\n+\tunsigned long flags;\n+\n+\tient->next = NULL;\n+\tient->cb = cb;\n+\tient->v = v;\n+\n+\tspin_lock_irqsave(&ictl->lock, flags);\n+\n+\tif (ictl->claim) {\n+\t\t// If we have a Q then add to end\n+\t\tictl->tail->next = ient;\n+\t\tictl->tail = ient;\n+\t\tient = NULL;\n+\t} else if (ictl->no_sched || ictl->irq) {\n+\t\t// Empty Q but other activity in progress so Q\n+\t\tictl->claim = ient;\n+\t\tictl->tail = ient;\n+\t\tient = NULL;\n+\t} else {\n+\t\t// Nothing else going on - schedule immediately and\n+\t\t// prevent anything else scheduling claims\n+\t\tictl->no_sched = 1;\n+\t}\n+\n+\tspin_unlock_irqrestore(&ictl->lock, flags);\n+\n+\tif (ient) {\n+\t\tient->cb(dev, ient->v);\n+\n+\t\tsched_claim(dev, ictl);\n+\t}\n+}\n+\n+static void ictl_init(struct rpivid_hw_irq_ctrl * const ictl)\n+{\n+\tspin_lock_init(&ictl->lock);\n+\tictl->claim = NULL;\n+\tictl->tail = NULL;\n+\tictl->irq = NULL;\n+\tictl->no_sched = 0;\n+}\n+\n+static void ictl_uninit(struct rpivid_hw_irq_ctrl * const ictl)\n+{\n+\t// Nothing to do\n+}\n+\n+#if !OPT_DEBUG_POLL_IRQ\n+static irqreturn_t rpivid_irq_irq(int irq, void *data)\n+{\n+\tstruct rpivid_dev * const dev = data;\n+\t__u32 ictrl;\n+\n+\tictrl = irq_read(dev, ARG_IC_ICTRL);\n+\tif (!(ictrl & ARG_IC_ICTRL_ALL_IRQ_MASK)) {\n+\t\tv4l2_warn(&dev->v4l2_dev, \"IRQ but no IRQ bits set\\n\");\n+\t\treturn IRQ_NONE;\n+\t}\n+\n+\t// Cancel any/all irqs\n+\tirq_write(dev, ARG_IC_ICTRL, ictrl & ~ARG_IC_ICTRL_SET_ZERO_MASK);\n+\n+\t// Service Active2 before Active1 so Phase 1 can transition to Phase 2\n+\t// without delay\n+\tif (ictrl & ARG_IC_ICTRL_ACTIVE2_INT_SET)\n+\t\tdo_irq(dev, &dev->ic_active2);\n+\tif (ictrl & ARG_IC_ICTRL_ACTIVE1_INT_SET)\n+\t\tdo_irq(dev, &dev->ic_active1);\n+\n+\treturn dev->ic_active1.thread_reqed || dev->ic_active2.thread_reqed ?\n+\t\tIRQ_WAKE_THREAD : IRQ_HANDLED;\n+}\n+\n+static void do_thread(struct rpivid_dev * const dev,\n+\t\t      struct rpivid_hw_irq_ctrl *const ictl)\n+{\n+\tunsigned long flags;\n+\tstruct rpivid_hw_irq_ent *ient = NULL;\n+\n+\tspin_lock_irqsave(&ictl->lock, flags);\n+\n+\tif (ictl->thread_reqed) {\n+\t\tient = ictl->irq;\n+\t\tictl->thread_reqed = false;\n+\t\tictl->irq = NULL;\n+\t}\n+\n+\tspin_unlock_irqrestore(&ictl->lock, flags);\n+\n+\tif (ient) {\n+\t\tient->cb(dev, ient->v);\n+\n+\t\tsched_claim(dev, ictl);\n+\t}\n+}\n+\n+static irqreturn_t rpivid_irq_thread(int irq, void *data)\n+{\n+\tstruct rpivid_dev * const dev = data;\n+\n+\tdo_thread(dev, &dev->ic_active1);\n+\tdo_thread(dev, &dev->ic_active2);\n+\n+\treturn IRQ_HANDLED;\n+}\n+#endif\n+\n+/* May only be called from Active1 CB\n+ * IRQs should not be expected until execution continues in the cb\n+ */\n+void rpivid_hw_irq_active1_thread(struct rpivid_dev *dev,\n+\t\t\t\t  struct rpivid_hw_irq_ent *ient,\n+\t\t\t\t  rpivid_irq_callback thread_cb, void *ctx)\n+{\n+\tpre_thread(dev, ient, thread_cb, ctx, &dev->ic_active1);\n+}\n+\n+void rpivid_hw_irq_active1_claim(struct rpivid_dev *dev,\n+\t\t\t\t struct rpivid_hw_irq_ent *ient,\n+\t\t\t\t rpivid_irq_callback ready_cb, void *ctx)\n+{\n+\tdo_claim(dev, ient, ready_cb, ctx, &dev->ic_active1);\n+}\n+\n+void rpivid_hw_irq_active1_irq(struct rpivid_dev *dev,\n+\t\t\t       struct rpivid_hw_irq_ent *ient,\n+\t\t\t       rpivid_irq_callback irq_cb, void *ctx)\n+{\n+\tpre_irq(dev, ient, irq_cb, ctx, &dev->ic_active1);\n+}\n+\n+void rpivid_hw_irq_active2_claim(struct rpivid_dev *dev,\n+\t\t\t\t struct rpivid_hw_irq_ent *ient,\n+\t\t\t\t rpivid_irq_callback ready_cb, void *ctx)\n+{\n+\tdo_claim(dev, ient, ready_cb, ctx, &dev->ic_active2);\n+}\n+\n+void rpivid_hw_irq_active2_irq(struct rpivid_dev *dev,\n+\t\t\t       struct rpivid_hw_irq_ent *ient,\n+\t\t\t       rpivid_irq_callback irq_cb, void *ctx)\n+{\n+\tpre_irq(dev, ient, irq_cb, ctx, &dev->ic_active2);\n+}\n+\n+int rpivid_hw_probe(struct rpivid_dev *dev)\n+{\n+\tstruct resource *res;\n+\t__u32 irq_stat;\n+\tint irq_dec;\n+\tint ret = 0;\n+\n+\tictl_init(&dev->ic_active1);\n+\tictl_init(&dev->ic_active2);\n+\n+\tres = platform_get_resource_byname(dev->pdev, IORESOURCE_MEM, \"intc\");\n+\tif (!res)\n+\t\treturn -ENODEV;\n+\n+\tdev->base_irq = devm_ioremap(dev->dev, res->start, resource_size(res));\n+\tif (IS_ERR(dev->base_irq))\n+\t\treturn PTR_ERR(dev->base_irq);\n+\n+\tres = platform_get_resource_byname(dev->pdev, IORESOURCE_MEM, \"hevc\");\n+\tif (!res)\n+\t\treturn -ENODEV;\n+\n+\tdev->base_h265 = devm_ioremap(dev->dev, res->start, resource_size(res));\n+\tif (IS_ERR(dev->base_h265))\n+\t\treturn PTR_ERR(dev->base_h265);\n+\n+\tdev->clock = devm_clk_get(&dev->pdev->dev, \"hevc\");\n+\tif (IS_ERR(dev->clock))\n+\t\treturn PTR_ERR(dev->clock);\n+\n+\t// Disable IRQs & reset anything pending\n+\tirq_write(dev, 0,\n+\t\t  ARG_IC_ICTRL_ACTIVE1_EN_SET | ARG_IC_ICTRL_ACTIVE2_EN_SET);\n+\tirq_stat = irq_read(dev, 0);\n+\tirq_write(dev, 0, irq_stat);\n+\n+#if !OPT_DEBUG_POLL_IRQ\n+\tirq_dec = platform_get_irq(dev->pdev, 0);\n+\tif (irq_dec <= 0)\n+\t\treturn irq_dec;\n+\tret = devm_request_threaded_irq(dev->dev, irq_dec,\n+\t\t\t\t\trpivid_irq_irq,\n+\t\t\t\t\trpivid_irq_thread,\n+\t\t\t\t\t0, dev_name(dev->dev), dev);\n+\tif (ret) {\n+\t\tdev_err(dev->dev, \"Failed to request IRQ - %d\\n\", ret);\n+\n+\t\treturn ret;\n+\t}\n+#endif\n+\treturn ret;\n+}\n+\n+void rpivid_hw_remove(struct rpivid_dev *dev)\n+{\n+\t// IRQ auto freed on unload so no need to do it here\n+\tictl_uninit(&dev->ic_active1);\n+\tictl_uninit(&dev->ic_active2);\n+}\n+\n--- /dev/null\n+++ b/drivers/staging/media/rpivid/rpivid_hw.h\n@@ -0,0 +1,300 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+/*\n+ * Raspberry Pi HEVC driver\n+ *\n+ * Copyright (C) 2020 Raspberry Pi (Trading) Ltd\n+ *\n+ * Based on the Cedrus VPU driver, that is:\n+ *\n+ * Copyright (C) 2016 Florent Revest <florent.revest@free-electrons.com>\n+ * Copyright (C) 2018 Paul Kocialkowski <paul.kocialkowski@bootlin.com>\n+ * Copyright (C) 2018 Bootlin\n+ */\n+\n+#ifndef _RPIVID_HW_H_\n+#define _RPIVID_HW_H_\n+\n+struct rpivid_hw_irq_ent {\n+\tstruct rpivid_hw_irq_ent *next;\n+\trpivid_irq_callback cb;\n+\tvoid *v;\n+};\n+\n+/* Phase 1 Register offsets */\n+\n+#define RPI_SPS0 0\n+#define RPI_SPS1 4\n+#define RPI_PPS 8\n+#define RPI_SLICE 12\n+#define RPI_TILESTART 16\n+#define RPI_TILEEND 20\n+#define RPI_SLICESTART 24\n+#define RPI_MODE 28\n+#define RPI_LEFT0 32\n+#define RPI_LEFT1 36\n+#define RPI_LEFT2 40\n+#define RPI_LEFT3 44\n+#define RPI_QP 48\n+#define RPI_CONTROL 52\n+#define RPI_STATUS 56\n+#define RPI_VERSION 60\n+#define RPI_BFBASE 64\n+#define RPI_BFNUM 68\n+#define RPI_BFCONTROL 72\n+#define RPI_BFSTATUS 76\n+#define RPI_PUWBASE 80\n+#define RPI_PUWSTRIDE 84\n+#define RPI_COEFFWBASE 88\n+#define RPI_COEFFWSTRIDE 92\n+#define RPI_SLICECMDS 96\n+#define RPI_BEGINTILEEND 100\n+#define RPI_TRANSFER 104\n+#define RPI_CFBASE 108\n+#define RPI_CFNUM 112\n+#define RPI_CFSTATUS 116\n+\n+/* Phase 2 Register offsets */\n+\n+#define RPI_PURBASE 0x8000\n+#define RPI_PURSTRIDE 0x8004\n+#define RPI_COEFFRBASE 0x8008\n+#define RPI_COEFFRSTRIDE 0x800C\n+#define RPI_NUMROWS 0x8010\n+#define RPI_CONFIG2 0x8014\n+#define RPI_OUTYBASE 0x8018\n+#define RPI_OUTYSTRIDE 0x801C\n+#define RPI_OUTCBASE 0x8020\n+#define RPI_OUTCSTRIDE 0x8024\n+#define RPI_STATUS2 0x8028\n+#define RPI_FRAMESIZE 0x802C\n+#define RPI_MVBASE 0x8030\n+#define RPI_MVSTRIDE 0x8034\n+#define RPI_COLBASE 0x8038\n+#define RPI_COLSTRIDE 0x803C\n+#define RPI_CURRPOC 0x8040\n+\n+/*\n+ * Write a general register value\n+ * Order is unimportant\n+ */\n+static inline void apb_write(const struct rpivid_dev * const dev,\n+\t\t\t     const unsigned int offset, const u32 val)\n+{\n+\twritel_relaxed(val, dev->base_h265 + offset);\n+}\n+\n+/* Write the final register value that actually starts the phase */\n+static inline void apb_write_final(const struct rpivid_dev * const dev,\n+\t\t\t\t   const unsigned int offset, const u32 val)\n+{\n+\twritel(val, dev->base_h265 + offset);\n+}\n+\n+static inline u32 apb_read(const struct rpivid_dev * const dev,\n+\t\t\t   const unsigned int offset)\n+{\n+\treturn readl(dev->base_h265 + offset);\n+}\n+\n+static inline void irq_write(const struct rpivid_dev * const dev,\n+\t\t\t     const unsigned int offset, const u32 val)\n+{\n+\twritel(val, dev->base_irq + offset);\n+}\n+\n+static inline u32 irq_read(const struct rpivid_dev * const dev,\n+\t\t\t   const unsigned int offset)\n+{\n+\treturn readl(dev->base_irq + offset);\n+}\n+\n+static inline void apb_write_vc_addr(const struct rpivid_dev * const dev,\n+\t\t\t\t     const unsigned int offset,\n+\t\t\t\t     const dma_addr_t a)\n+{\n+\tapb_write(dev, offset, (u32)(a >> 6));\n+}\n+\n+static inline void apb_write_vc_addr_final(const struct rpivid_dev * const dev,\n+\t\t\t\t\t   const unsigned int offset,\n+\t\t\t\t\t   const dma_addr_t a)\n+{\n+\tapb_write_final(dev, offset, (u32)(a >> 6));\n+}\n+\n+static inline void apb_write_vc_len(const struct rpivid_dev * const dev,\n+\t\t\t\t    const unsigned int offset,\n+\t\t\t\t    const unsigned int x)\n+{\n+\tapb_write(dev, offset, (x + 63) >> 6);\n+}\n+\n+/* *ARG_IC_ICTRL - Interrupt control for ARGON Core*\n+ * Offset (byte space) = 40'h2b10000\n+ * Physical Address (byte space) = 40'h7eb10000\n+ * Verilog Macro Address = `ARG_IC_REG_START + `ARGON_INTCTRL_ICTRL\n+ * Reset Value = 32'b100x100x_100xxxxx_xxxxxxx0_x100x100\n+ * Access = RW (32-bit only)\n+ * Interrupt control logic for ARGON Core.\n+ */\n+#define ARG_IC_ICTRL 0\n+\n+/* acc=LWC ACTIVE1_INT FIELD ACCESS: LWC\n+ *\n+ * Interrupt 1\n+ * This is set and held when an hevc_active1 interrupt edge is detected\n+ * The polarity of the edge is set by the ACTIVE1_EDGE field\n+ * Write a 1 to this bit to clear down the latched interrupt\n+ * The latched interrupt is only enabled out onto the interrupt line if\n+ * ACTIVE1_EN is set\n+ * Reset value is *0* decimal.\n+ */\n+#define ARG_IC_ICTRL_ACTIVE1_INT_SET\t\tBIT(0)\n+\n+/* ACTIVE1_EDGE Sets the polarity of the interrupt edge detection logic\n+ * This logic detects edges of the hevc_active1 line from the argon core\n+ * 0 = negedge, 1 = posedge\n+ * Reset value is *0* decimal.\n+ */\n+#define ARG_IC_ICTRL_ACTIVE1_EDGE_SET\t\tBIT(1)\n+\n+/* ACTIVE1_EN Enables ACTIVE1_INT out onto the argon interrupt line.\n+ * If this isn't set, the interrupt logic will work but no interrupt will be\n+ * set to the interrupt controller\n+ * Reset value is *1* decimal.\n+ *\n+ * [JC] The above appears to be a lie - if unset then b0 is never set\n+ */\n+#define ARG_IC_ICTRL_ACTIVE1_EN_SET\t\tBIT(2)\n+\n+/* acc=RO ACTIVE1_STATUS FIELD ACCESS: RO\n+ *\n+ * The current status of the hevc_active1 signal\n+ */\n+#define ARG_IC_ICTRL_ACTIVE1_STATUS_SET\t\tBIT(3)\n+\n+/* acc=LWC ACTIVE2_INT FIELD ACCESS: LWC\n+ *\n+ * Interrupt 2\n+ * This is set and held when an hevc_active2 interrupt edge is detected\n+ * The polarity of the edge is set by the ACTIVE2_EDGE field\n+ * Write a 1 to this bit to clear down the latched interrupt\n+ * The latched interrupt is only enabled out onto the interrupt line if\n+ * ACTIVE2_EN is set\n+ * Reset value is *0* decimal.\n+ */\n+#define ARG_IC_ICTRL_ACTIVE2_INT_SET\t\tBIT(4)\n+\n+/* ACTIVE2_EDGE Sets the polarity of the interrupt edge detection logic\n+ * This logic detects edges of the hevc_active2 line from the argon core\n+ * 0 = negedge, 1 = posedge\n+ * Reset value is *0* decimal.\n+ */\n+#define ARG_IC_ICTRL_ACTIVE2_EDGE_SET\t\tBIT(5)\n+\n+/* ACTIVE2_EN Enables ACTIVE2_INT out onto the argon interrupt line.\n+ * If this isn't set, the interrupt logic will work but no interrupt will be\n+ * set to the interrupt controller\n+ * Reset value is *1* decimal.\n+ */\n+#define ARG_IC_ICTRL_ACTIVE2_EN_SET\t\tBIT(6)\n+\n+/* acc=RO ACTIVE2_STATUS FIELD ACCESS: RO\n+ *\n+ * The current status of the hevc_active2 signal\n+ */\n+#define ARG_IC_ICTRL_ACTIVE2_STATUS_SET\t\tBIT(7)\n+\n+/* TEST_INT Forces the argon int high for test purposes.\n+ * Reset value is *0* decimal.\n+ */\n+#define ARG_IC_ICTRL_TEST_INT\t\t\tBIT(8)\n+#define ARG_IC_ICTRL_SPARE\t\t\tBIT(9)\n+\n+/* acc=RO VP9_INTERRUPT_STATUS FIELD ACCESS: RO\n+ *\n+ * The current status of the vp9_interrupt signal\n+ */\n+#define ARG_IC_ICTRL_VP9_INTERRUPT_STATUS\tBIT(10)\n+\n+/* AIO_INT_ENABLE 1 = Or the AIO int in with the Argon int so the VPU can see\n+ * it\n+ * 0 = the AIO int is masked. (It should still be connected to the GIC though).\n+ */\n+#define ARG_IC_ICTRL_AIO_INT_ENABLE\t\tBIT(20)\n+#define ARG_IC_ICTRL_H264_ACTIVE_INT\t\tBIT(21)\n+#define ARG_IC_ICTRL_H264_ACTIVE_EDGE\t\tBIT(22)\n+#define ARG_IC_ICTRL_H264_ACTIVE_EN\t\tBIT(23)\n+#define ARG_IC_ICTRL_H264_ACTIVE_STATUS\t\tBIT(24)\n+#define ARG_IC_ICTRL_H264_INTERRUPT_INT\t\tBIT(25)\n+#define ARG_IC_ICTRL_H264_INTERRUPT_EDGE\tBIT(26)\n+#define ARG_IC_ICTRL_H264_INTERRUPT_EN\t\tBIT(27)\n+\n+/* acc=RO H264_INTERRUPT_STATUS FIELD ACCESS: RO\n+ *\n+ * The current status of the h264_interrupt signal\n+ */\n+#define ARG_IC_ICTRL_H264_INTERRUPT_STATUS\tBIT(28)\n+\n+/* acc=LWC VP9_INTERRUPT_INT FIELD ACCESS: LWC\n+ *\n+ * Interrupt 1\n+ * This is set and held when an vp9_interrupt interrupt edge is detected\n+ * The polarity of the edge is set by the VP9_INTERRUPT_EDGE field\n+ * Write a 1 to this bit to clear down the latched interrupt\n+ * The latched interrupt is only enabled out onto the interrupt line if\n+ * VP9_INTERRUPT_EN is set\n+ * Reset value is *0* decimal.\n+ */\n+#define ARG_IC_ICTRL_VP9_INTERRUPT_INT\t\tBIT(29)\n+\n+/* VP9_INTERRUPT_EDGE Sets the polarity of the interrupt edge detection logic\n+ * This logic detects edges of the vp9_interrupt line from the argon h264 core\n+ * 0 = negedge, 1 = posedge\n+ * Reset value is *0* decimal.\n+ */\n+#define ARG_IC_ICTRL_VP9_INTERRUPT_EDGE\t\tBIT(30)\n+\n+/* VP9_INTERRUPT_EN Enables VP9_INTERRUPT_INT out onto the argon interrupt line.\n+ * If this isn't set, the interrupt logic will work but no interrupt will be\n+ * set to the interrupt controller\n+ * Reset value is *1* decimal.\n+ */\n+#define ARG_IC_ICTRL_VP9_INTERRUPT_EN\t\tBIT(31)\n+\n+/* Bits 19:12, 11 reserved - read ?, write 0 */\n+#define ARG_IC_ICTRL_SET_ZERO_MASK\t\t((0xff << 12) | BIT(11))\n+\n+/* All IRQ bits */\n+#define ARG_IC_ICTRL_ALL_IRQ_MASK   (\\\n+\t\tARG_IC_ICTRL_VP9_INTERRUPT_INT  |\\\n+\t\tARG_IC_ICTRL_H264_INTERRUPT_INT |\\\n+\t\tARG_IC_ICTRL_ACTIVE1_INT_SET    |\\\n+\t\tARG_IC_ICTRL_ACTIVE2_INT_SET)\n+\n+/* Auto release once all CBs called */\n+void rpivid_hw_irq_active1_claim(struct rpivid_dev *dev,\n+\t\t\t\t struct rpivid_hw_irq_ent *ient,\n+\t\t\t\t rpivid_irq_callback ready_cb, void *ctx);\n+/* May only be called in claim cb */\n+void rpivid_hw_irq_active1_irq(struct rpivid_dev *dev,\n+\t\t\t       struct rpivid_hw_irq_ent *ient,\n+\t\t\t       rpivid_irq_callback irq_cb, void *ctx);\n+/* May only be called in irq cb */\n+void rpivid_hw_irq_active1_thread(struct rpivid_dev *dev,\n+\t\t\t\t  struct rpivid_hw_irq_ent *ient,\n+\t\t\t\t  rpivid_irq_callback thread_cb, void *ctx);\n+\n+/* Auto release once all CBs called */\n+void rpivid_hw_irq_active2_claim(struct rpivid_dev *dev,\n+\t\t\t\t struct rpivid_hw_irq_ent *ient,\n+\t\t\t\t rpivid_irq_callback ready_cb, void *ctx);\n+/* May only be called in claim cb */\n+void rpivid_hw_irq_active2_irq(struct rpivid_dev *dev,\n+\t\t\t       struct rpivid_hw_irq_ent *ient,\n+\t\t\t       rpivid_irq_callback irq_cb, void *ctx);\n+\n+int rpivid_hw_probe(struct rpivid_dev *dev);\n+void rpivid_hw_remove(struct rpivid_dev *dev);\n+\n+#endif\n--- /dev/null\n+++ b/drivers/staging/media/rpivid/rpivid_video.c\n@@ -0,0 +1,593 @@\n+// SPDX-License-Identifier: GPL-2.0\n+/*\n+ * Raspberry Pi HEVC driver\n+ *\n+ * Copyright (C) 2020 Raspberry Pi (Trading) Ltd\n+ *\n+ * Based on the Cedrus VPU driver, that is:\n+ *\n+ * Copyright (C) 2016 Florent Revest <florent.revest@free-electrons.com>\n+ * Copyright (C) 2018 Paul Kocialkowski <paul.kocialkowski@bootlin.com>\n+ * Copyright (C) 2018 Bootlin\n+ */\n+\n+#include <media/videobuf2-dma-contig.h>\n+#include <media/v4l2-device.h>\n+#include <media/v4l2-ioctl.h>\n+#include <media/v4l2-event.h>\n+#include <media/v4l2-mem2mem.h>\n+\n+#include \"rpivid.h\"\n+#include \"rpivid_video.h\"\n+#include \"rpivid_dec.h\"\n+\n+#define RPIVID_DECODE_SRC\tBIT(0)\n+#define RPIVID_DECODE_DST\tBIT(1)\n+\n+#define RPIVID_MIN_WIDTH\t16U\n+#define RPIVID_MIN_HEIGHT\t16U\n+#define RPIVID_MAX_WIDTH\t4096U\n+#define RPIVID_MAX_HEIGHT\t4096U\n+\n+static inline struct rpivid_ctx *rpivid_file2ctx(struct file *file)\n+{\n+\treturn container_of(file->private_data, struct rpivid_ctx, fh);\n+}\n+\n+/* constrain x to y,y*2 */\n+static inline unsigned int constrain2x(unsigned int x, unsigned int y)\n+{\n+\treturn (x < y) ?\n+\t\t\ty :\n+\t\t\t(x > y * 2) ? y : x;\n+}\n+\n+int rpivid_prepare_src_format(struct v4l2_pix_format *pix_fmt)\n+{\n+\tif (pix_fmt->pixelformat != V4L2_PIX_FMT_HEVC_SLICE)\n+\t\treturn -EINVAL;\n+\n+\t/* Zero bytes per line for encoded source. */\n+\tpix_fmt->bytesperline = 0;\n+\t/* Choose some minimum size since this can't be 0 */\n+\tpix_fmt->sizeimage = max_t(u32, SZ_1K, pix_fmt->sizeimage);\n+\tpix_fmt->field = V4L2_FIELD_NONE;\n+\treturn 0;\n+}\n+\n+int rpivid_prepare_dst_format(struct v4l2_pix_format *pix_fmt)\n+{\n+\tunsigned int width = pix_fmt->width;\n+\tunsigned int height = pix_fmt->height;\n+\tunsigned int sizeimage = pix_fmt->sizeimage;\n+\tunsigned int bytesperline = pix_fmt->bytesperline;\n+\n+\tswitch (pix_fmt->pixelformat) {\n+\t/* For column formats set bytesperline to column height (stride2) */\n+\tcase V4L2_PIX_FMT_NV12_COL128:\n+\t\t/* Width rounds up to columns */\n+\t\twidth = ALIGN(min(width, RPIVID_MAX_WIDTH), 128);\n+\n+\t\t/* 16 aligned height - not sure we even need that */\n+\t\theight = ALIGN(height, 16);\n+\t\t/* column height\n+\t\t * Accept suggested shape if at least min & < 2 * min\n+\t\t */\n+\t\tbytesperline = constrain2x(bytesperline, height * 3 / 2);\n+\n+\t\t/* image size\n+\t\t * Again allow plausible variation in case added padding is\n+\t\t * required\n+\t\t */\n+\t\tsizeimage = constrain2x(sizeimage, bytesperline * width);\n+\t\tbreak;\n+\n+\tcase V4L2_PIX_FMT_NV12_10_COL128:\n+\t\t/* width in pixels (3 pels = 4 bytes) rounded to 128 byte\n+\t\t * columns\n+\t\t */\n+\t\twidth = ALIGN(((min(width, RPIVID_MAX_WIDTH) + 2) / 3), 32) * 3;\n+\n+\t\t/* 16-aligned height. */\n+\t\theight = ALIGN(height, 16);\n+\n+\t\t/* column height\n+\t\t * Accept suggested shape if at least min & < 2 * min\n+\t\t */\n+\t\tbytesperline = constrain2x(bytesperline, height * 3 / 2);\n+\n+\t\t/* image size\n+\t\t * Again allow plausible variation in case added padding is\n+\t\t * required\n+\t\t */\n+\t\tsizeimage = constrain2x(sizeimage,\n+\t\t\t\t\tbytesperline * width * 4 / 3);\n+\t\tbreak;\n+\n+\tdefault:\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tpix_fmt->width = width;\n+\tpix_fmt->height = height;\n+\n+\tpix_fmt->field = V4L2_FIELD_NONE;\n+\tpix_fmt->bytesperline = bytesperline;\n+\tpix_fmt->sizeimage = sizeimage;\n+\treturn 0;\n+}\n+\n+static int rpivid_querycap(struct file *file, void *priv,\n+\t\t\t   struct v4l2_capability *cap)\n+{\n+\tstrscpy(cap->driver, RPIVID_NAME, sizeof(cap->driver));\n+\tstrscpy(cap->card, RPIVID_NAME, sizeof(cap->card));\n+\tsnprintf(cap->bus_info, sizeof(cap->bus_info),\n+\t\t \"platform:%s\", RPIVID_NAME);\n+\n+\treturn 0;\n+}\n+\n+static int rpivid_enum_fmt_vid_out(struct file *file, void *priv,\n+\t\t\t\t   struct v4l2_fmtdesc *f)\n+{\n+\t// Input formats\n+\n+\t// H.265 Slice only currently\n+\tif (f->index == 0) {\n+\t\tf->pixelformat = V4L2_PIX_FMT_HEVC_SLICE;\n+\t\treturn 0;\n+\t}\n+\n+\treturn -EINVAL;\n+}\n+\n+static int rpivid_hevc_validate_sps(const struct v4l2_ctrl_hevc_sps * const sps)\n+{\n+\tconst unsigned int ctb_log2_size_y =\n+\t\t\tsps->log2_min_luma_coding_block_size_minus3 + 3 +\n+\t\t\tsps->log2_diff_max_min_luma_coding_block_size;\n+\tconst unsigned int min_tb_log2_size_y =\n+\t\t\tsps->log2_min_luma_transform_block_size_minus2 + 2;\n+\tconst unsigned int max_tb_log2_size_y = min_tb_log2_size_y +\n+\t\t\tsps->log2_diff_max_min_luma_transform_block_size;\n+\n+\t/* Local limitations */\n+\tif (sps->pic_width_in_luma_samples < 32 ||\n+\t    sps->pic_width_in_luma_samples > 4096)\n+\t\treturn 0;\n+\tif (sps->pic_height_in_luma_samples < 32 ||\n+\t    sps->pic_height_in_luma_samples > 4096)\n+\t\treturn 0;\n+\tif (!(sps->bit_depth_luma_minus8 == 0 ||\n+\t      sps->bit_depth_luma_minus8 == 2))\n+\t\treturn 0;\n+\tif (sps->bit_depth_luma_minus8 != sps->bit_depth_chroma_minus8)\n+\t\treturn 0;\n+\tif (sps->chroma_format_idc != 1)\n+\t\treturn 0;\n+\n+\t/*  Limits from H.265 7.4.3.2.1 */\n+\tif (sps->log2_max_pic_order_cnt_lsb_minus4 > 12)\n+\t\treturn 0;\n+\tif (sps->sps_max_dec_pic_buffering_minus1 > 15)\n+\t\treturn 0;\n+\tif (sps->sps_max_num_reorder_pics >\n+\t\t\t\tsps->sps_max_dec_pic_buffering_minus1)\n+\t\treturn 0;\n+\tif (ctb_log2_size_y > 6)\n+\t\treturn 0;\n+\tif (max_tb_log2_size_y > 5)\n+\t\treturn 0;\n+\tif (max_tb_log2_size_y > ctb_log2_size_y)\n+\t\treturn 0;\n+\tif (sps->max_transform_hierarchy_depth_inter >\n+\t\t\t\t(ctb_log2_size_y - min_tb_log2_size_y))\n+\t\treturn 0;\n+\tif (sps->max_transform_hierarchy_depth_intra >\n+\t\t\t\t(ctb_log2_size_y - min_tb_log2_size_y))\n+\t\treturn 0;\n+\t/* Check pcm stuff */\n+\tif (sps->num_short_term_ref_pic_sets > 64)\n+\t\treturn 0;\n+\tif (sps->num_long_term_ref_pics_sps > 32)\n+\t\treturn 0;\n+\treturn 1;\n+}\n+\n+static inline int is_sps_set(const struct v4l2_ctrl_hevc_sps * const sps)\n+{\n+\treturn sps && sps->pic_width_in_luma_samples != 0;\n+}\n+\n+static u32 pixelformat_from_sps(const struct v4l2_ctrl_hevc_sps * const sps,\n+\t\t\t\tconst int index)\n+{\n+\tu32 pf = 0;\n+\n+\t// Use width 0 as a signifier of unsetness\n+\tif (!is_sps_set(sps)) {\n+\t\t/* Treat this as an error? For now return both */\n+\t\tif (index == 0)\n+\t\t\tpf = V4L2_PIX_FMT_NV12_COL128;\n+\t\telse if (index == 1)\n+\t\t\tpf = V4L2_PIX_FMT_NV12_10_COL128;\n+\t} else if (index == 0 && rpivid_hevc_validate_sps(sps)) {\n+\t\tif (sps->bit_depth_luma_minus8 == 0)\n+\t\t\tpf = V4L2_PIX_FMT_NV12_COL128;\n+\t\telse if (sps->bit_depth_luma_minus8 == 2)\n+\t\t\tpf = V4L2_PIX_FMT_NV12_10_COL128;\n+\t}\n+\n+\treturn pf;\n+}\n+\n+static struct v4l2_pix_format\n+rpivid_hevc_default_dst_fmt(struct rpivid_ctx * const ctx)\n+{\n+\tconst struct v4l2_ctrl_hevc_sps * const sps =\n+\t\trpivid_find_control_data(ctx, V4L2_CID_MPEG_VIDEO_HEVC_SPS);\n+\tstruct v4l2_pix_format pix_fmt = {\n+\t\t.width = sps->pic_width_in_luma_samples,\n+\t\t.height = sps->pic_height_in_luma_samples,\n+\t\t.pixelformat = pixelformat_from_sps(sps, 0)\n+\t};\n+\n+\trpivid_prepare_dst_format(&pix_fmt);\n+\treturn pix_fmt;\n+}\n+\n+static u32 rpivid_hevc_get_dst_pixelformat(struct rpivid_ctx * const ctx,\n+\t\t\t\t\t   const int index)\n+{\n+\tconst struct v4l2_ctrl_hevc_sps * const sps =\n+\t\trpivid_find_control_data(ctx, V4L2_CID_MPEG_VIDEO_HEVC_SPS);\n+\n+\treturn pixelformat_from_sps(sps, index);\n+}\n+\n+static int rpivid_enum_fmt_vid_cap(struct file *file, void *priv,\n+\t\t\t\t   struct v4l2_fmtdesc *f)\n+{\n+\tstruct rpivid_ctx * const ctx = rpivid_file2ctx(file);\n+\n+\tconst u32 pf = rpivid_hevc_get_dst_pixelformat(ctx, f->index);\n+\n+\tif (pf == 0)\n+\t\treturn -EINVAL;\n+\n+\tf->pixelformat = pf;\n+\treturn 0;\n+}\n+\n+static int rpivid_g_fmt_vid_cap(struct file *file, void *priv,\n+\t\t\t\tstruct v4l2_format *f)\n+{\n+\tstruct rpivid_ctx *ctx = rpivid_file2ctx(file);\n+\n+\tif (!ctx->dst_fmt_set)\n+\t\tctx->dst_fmt = rpivid_hevc_default_dst_fmt(ctx);\n+\tf->fmt.pix = ctx->dst_fmt;\n+\treturn 0;\n+}\n+\n+static int rpivid_g_fmt_vid_out(struct file *file, void *priv,\n+\t\t\t\tstruct v4l2_format *f)\n+{\n+\tstruct rpivid_ctx *ctx = rpivid_file2ctx(file);\n+\n+\tf->fmt.pix = ctx->src_fmt;\n+\treturn 0;\n+}\n+\n+static inline void copy_color(struct v4l2_pix_format *d,\n+\t\t\t      const struct v4l2_pix_format *s)\n+{\n+\td->colorspace   = s->colorspace;\n+\td->xfer_func    = s->xfer_func;\n+\td->ycbcr_enc    = s->ycbcr_enc;\n+\td->quantization = s->quantization;\n+}\n+\n+static int rpivid_try_fmt_vid_cap(struct file *file, void *priv,\n+\t\t\t\t  struct v4l2_format *f)\n+{\n+\tstruct rpivid_ctx *ctx = rpivid_file2ctx(file);\n+\tconst struct v4l2_ctrl_hevc_sps * const sps =\n+\t\trpivid_find_control_data(ctx, V4L2_CID_MPEG_VIDEO_HEVC_SPS);\n+\tu32 pixelformat;\n+\tint i;\n+\n+\t/* Reject format types we don't support */\n+\tif (f->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)\n+\t\treturn -EINVAL;\n+\n+\tfor (i = 0; (pixelformat = pixelformat_from_sps(sps, i)) != 0; i++) {\n+\t\tif (f->fmt.pix.pixelformat == pixelformat)\n+\t\t\tbreak;\n+\t}\n+\n+\t// If we can't use requested fmt then set to default\n+\tif (pixelformat == 0) {\n+\t\tpixelformat = pixelformat_from_sps(sps, 0);\n+\t\t// If we don't have a default then give up\n+\t\tif (pixelformat == 0)\n+\t\t\treturn -EINVAL;\n+\t}\n+\n+\t// We don't have any way of finding out colourspace so believe\n+\t// anything we are told - take anything set in src as a default\n+\tif (f->fmt.pix.colorspace == V4L2_COLORSPACE_DEFAULT)\n+\t\tcopy_color(&f->fmt.pix, &ctx->src_fmt);\n+\n+\tf->fmt.pix.pixelformat = pixelformat;\n+\treturn rpivid_prepare_dst_format(&f->fmt.pix);\n+}\n+\n+static int rpivid_try_fmt_vid_out(struct file *file, void *priv,\n+\t\t\t\t  struct v4l2_format *f)\n+{\n+\tif (f->type != V4L2_BUF_TYPE_VIDEO_OUTPUT)\n+\t\treturn -EINVAL;\n+\n+\tif (rpivid_prepare_src_format(&f->fmt.pix)) {\n+\t\t// Set default src format\n+\t\tf->fmt.pix.pixelformat = RPIVID_SRC_PIXELFORMAT_DEFAULT;\n+\t\trpivid_prepare_src_format(&f->fmt.pix);\n+\t}\n+\treturn 0;\n+}\n+\n+static int rpivid_s_fmt_vid_cap(struct file *file, void *priv,\n+\t\t\t\tstruct v4l2_format *f)\n+{\n+\tstruct rpivid_ctx *ctx = rpivid_file2ctx(file);\n+\tstruct vb2_queue *vq;\n+\tint ret;\n+\n+\tvq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type);\n+\tif (vb2_is_busy(vq))\n+\t\treturn -EBUSY;\n+\n+\tret = rpivid_try_fmt_vid_cap(file, priv, f);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tctx->dst_fmt = f->fmt.pix;\n+\tctx->dst_fmt_set = 1;\n+\n+\treturn 0;\n+}\n+\n+static int rpivid_s_fmt_vid_out(struct file *file, void *priv,\n+\t\t\t\tstruct v4l2_format *f)\n+{\n+\tstruct rpivid_ctx *ctx = rpivid_file2ctx(file);\n+\tstruct vb2_queue *vq;\n+\tint ret;\n+\n+\tvq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type);\n+\tif (vb2_is_busy(vq))\n+\t\treturn -EBUSY;\n+\n+\tret = rpivid_try_fmt_vid_out(file, priv, f);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tctx->src_fmt = f->fmt.pix;\n+\tctx->dst_fmt_set = 0;  // Setting src invalidates dst\n+\n+\tvq->subsystem_flags |=\n+\t\tVB2_V4L2_FL_SUPPORTS_M2M_HOLD_CAPTURE_BUF;\n+\n+\t/* Propagate colorspace information to capture. */\n+\tcopy_color(&ctx->dst_fmt, &f->fmt.pix);\n+\treturn 0;\n+}\n+\n+const struct v4l2_ioctl_ops rpivid_ioctl_ops = {\n+\t.vidioc_querycap\t\t= rpivid_querycap,\n+\n+\t.vidioc_enum_fmt_vid_cap\t= rpivid_enum_fmt_vid_cap,\n+\t.vidioc_g_fmt_vid_cap\t\t= rpivid_g_fmt_vid_cap,\n+\t.vidioc_try_fmt_vid_cap\t\t= rpivid_try_fmt_vid_cap,\n+\t.vidioc_s_fmt_vid_cap\t\t= rpivid_s_fmt_vid_cap,\n+\n+\t.vidioc_enum_fmt_vid_out\t= rpivid_enum_fmt_vid_out,\n+\t.vidioc_g_fmt_vid_out\t\t= rpivid_g_fmt_vid_out,\n+\t.vidioc_try_fmt_vid_out\t\t= rpivid_try_fmt_vid_out,\n+\t.vidioc_s_fmt_vid_out\t\t= rpivid_s_fmt_vid_out,\n+\n+\t.vidioc_reqbufs\t\t\t= v4l2_m2m_ioctl_reqbufs,\n+\t.vidioc_querybuf\t\t= v4l2_m2m_ioctl_querybuf,\n+\t.vidioc_qbuf\t\t\t= v4l2_m2m_ioctl_qbuf,\n+\t.vidioc_dqbuf\t\t\t= v4l2_m2m_ioctl_dqbuf,\n+\t.vidioc_prepare_buf\t\t= v4l2_m2m_ioctl_prepare_buf,\n+\t.vidioc_create_bufs\t\t= v4l2_m2m_ioctl_create_bufs,\n+\t.vidioc_expbuf\t\t\t= v4l2_m2m_ioctl_expbuf,\n+\n+\t.vidioc_streamon\t\t= v4l2_m2m_ioctl_streamon,\n+\t.vidioc_streamoff\t\t= v4l2_m2m_ioctl_streamoff,\n+\n+\t.vidioc_try_decoder_cmd\t\t= v4l2_m2m_ioctl_stateless_try_decoder_cmd,\n+\t.vidioc_decoder_cmd\t\t= v4l2_m2m_ioctl_stateless_decoder_cmd,\n+\n+\t.vidioc_subscribe_event\t\t= v4l2_ctrl_subscribe_event,\n+\t.vidioc_unsubscribe_event\t= v4l2_event_unsubscribe,\n+};\n+\n+static int rpivid_queue_setup(struct vb2_queue *vq, unsigned int *nbufs,\n+\t\t\t      unsigned int *nplanes, unsigned int sizes[],\n+\t\t\t      struct device *alloc_devs[])\n+{\n+\tstruct rpivid_ctx *ctx = vb2_get_drv_priv(vq);\n+\tstruct v4l2_pix_format *pix_fmt;\n+\n+\tif (V4L2_TYPE_IS_OUTPUT(vq->type))\n+\t\tpix_fmt = &ctx->src_fmt;\n+\telse\n+\t\tpix_fmt = &ctx->dst_fmt;\n+\n+\tif (*nplanes) {\n+\t\tif (sizes[0] < pix_fmt->sizeimage)\n+\t\t\treturn -EINVAL;\n+\t} else {\n+\t\tsizes[0] = pix_fmt->sizeimage;\n+\t\t*nplanes = 1;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static void rpivid_queue_cleanup(struct vb2_queue *vq, u32 state)\n+{\n+\tstruct rpivid_ctx *ctx = vb2_get_drv_priv(vq);\n+\tstruct vb2_v4l2_buffer *vbuf;\n+\n+\tfor (;;) {\n+\t\tif (V4L2_TYPE_IS_OUTPUT(vq->type))\n+\t\t\tvbuf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);\n+\t\telse\n+\t\t\tvbuf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);\n+\n+\t\tif (!vbuf)\n+\t\t\treturn;\n+\n+\t\tv4l2_ctrl_request_complete(vbuf->vb2_buf.req_obj.req,\n+\t\t\t\t\t   &ctx->hdl);\n+\t\tv4l2_m2m_buf_done(vbuf, state);\n+\t}\n+}\n+\n+static int rpivid_buf_out_validate(struct vb2_buffer *vb)\n+{\n+\tstruct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);\n+\n+\tvbuf->field = V4L2_FIELD_NONE;\n+\treturn 0;\n+}\n+\n+static int rpivid_buf_prepare(struct vb2_buffer *vb)\n+{\n+\tstruct vb2_queue *vq = vb->vb2_queue;\n+\tstruct rpivid_ctx *ctx = vb2_get_drv_priv(vq);\n+\tstruct v4l2_pix_format *pix_fmt;\n+\n+\tif (V4L2_TYPE_IS_OUTPUT(vq->type))\n+\t\tpix_fmt = &ctx->src_fmt;\n+\telse\n+\t\tpix_fmt = &ctx->dst_fmt;\n+\n+\tif (vb2_plane_size(vb, 0) < pix_fmt->sizeimage)\n+\t\treturn -EINVAL;\n+\n+\tvb2_set_plane_payload(vb, 0, pix_fmt->sizeimage);\n+\n+\treturn 0;\n+}\n+\n+static int rpivid_start_streaming(struct vb2_queue *vq, unsigned int count)\n+{\n+\tstruct rpivid_ctx *ctx = vb2_get_drv_priv(vq);\n+\tstruct rpivid_dev *dev = ctx->dev;\n+\tint ret = 0;\n+\n+\tif (ctx->src_fmt.pixelformat != V4L2_PIX_FMT_HEVC_SLICE)\n+\t\treturn -EINVAL;\n+\n+\tif (V4L2_TYPE_IS_OUTPUT(vq->type) && dev->dec_ops->start)\n+\t\tret = dev->dec_ops->start(ctx);\n+\n+\tret = clk_set_rate(dev->clock, 500 * 1000 * 1000);\n+\tif (ret) {\n+\t\tdev_err(dev->dev, \"Failed to set clock rate\\n\");\n+\t\tgoto out;\n+\t}\n+\n+\tret = clk_prepare_enable(dev->clock);\n+\tif (ret)\n+\t\tdev_err(dev->dev, \"Failed to enable clock\\n\");\n+\n+out:\n+\tif (ret)\n+\t\trpivid_queue_cleanup(vq, VB2_BUF_STATE_QUEUED);\n+\n+\treturn ret;\n+}\n+\n+static void rpivid_stop_streaming(struct vb2_queue *vq)\n+{\n+\tstruct rpivid_ctx *ctx = vb2_get_drv_priv(vq);\n+\tstruct rpivid_dev *dev = ctx->dev;\n+\n+\tif (V4L2_TYPE_IS_OUTPUT(vq->type) && dev->dec_ops->stop)\n+\t\tdev->dec_ops->stop(ctx);\n+\n+\trpivid_queue_cleanup(vq, VB2_BUF_STATE_ERROR);\n+\n+\tclk_disable_unprepare(dev->clock);\n+}\n+\n+static void rpivid_buf_queue(struct vb2_buffer *vb)\n+{\n+\tstruct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);\n+\tstruct rpivid_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);\n+\n+\tv4l2_m2m_buf_queue(ctx->fh.m2m_ctx, vbuf);\n+}\n+\n+static void rpivid_buf_request_complete(struct vb2_buffer *vb)\n+{\n+\tstruct rpivid_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);\n+\n+\tv4l2_ctrl_request_complete(vb->req_obj.req, &ctx->hdl);\n+}\n+\n+static struct vb2_ops rpivid_qops = {\n+\t.queue_setup\t\t= rpivid_queue_setup,\n+\t.buf_prepare\t\t= rpivid_buf_prepare,\n+\t.buf_queue\t\t= rpivid_buf_queue,\n+\t.buf_out_validate\t= rpivid_buf_out_validate,\n+\t.buf_request_complete\t= rpivid_buf_request_complete,\n+\t.start_streaming\t= rpivid_start_streaming,\n+\t.stop_streaming\t\t= rpivid_stop_streaming,\n+\t.wait_prepare\t\t= vb2_ops_wait_prepare,\n+\t.wait_finish\t\t= vb2_ops_wait_finish,\n+};\n+\n+int rpivid_queue_init(void *priv, struct vb2_queue *src_vq,\n+\t\t      struct vb2_queue *dst_vq)\n+{\n+\tstruct rpivid_ctx *ctx = priv;\n+\tint ret;\n+\n+\tsrc_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT;\n+\tsrc_vq->io_modes = VB2_MMAP | VB2_DMABUF;\n+\tsrc_vq->drv_priv = ctx;\n+\tsrc_vq->buf_struct_size = sizeof(struct rpivid_buffer);\n+\tsrc_vq->min_buffers_needed = 1;\n+\tsrc_vq->ops = &rpivid_qops;\n+\tsrc_vq->mem_ops = &vb2_dma_contig_memops;\n+\tsrc_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;\n+\tsrc_vq->lock = &ctx->dev->dev_mutex;\n+\tsrc_vq->dev = ctx->dev->dev;\n+\tsrc_vq->supports_requests = true;\n+\tsrc_vq->requires_requests = true;\n+\n+\tret = vb2_queue_init(src_vq);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tdst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;\n+\tdst_vq->io_modes = VB2_MMAP | VB2_DMABUF;\n+\tdst_vq->drv_priv = ctx;\n+\tdst_vq->buf_struct_size = sizeof(struct rpivid_buffer);\n+\tdst_vq->min_buffers_needed = 1;\n+\tdst_vq->ops = &rpivid_qops;\n+\tdst_vq->mem_ops = &vb2_dma_contig_memops;\n+\tdst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;\n+\tdst_vq->lock = &ctx->dev->dev_mutex;\n+\tdst_vq->dev = ctx->dev->dev;\n+\n+\treturn vb2_queue_init(dst_vq);\n+}\n--- /dev/null\n+++ b/drivers/staging/media/rpivid/rpivid_video.h\n@@ -0,0 +1,30 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+/*\n+ * Raspberry Pi HEVC driver\n+ *\n+ * Copyright (C) 2020 Raspberry Pi (Trading) Ltd\n+ *\n+ * Based on the Cedrus VPU driver, that is:\n+ *\n+ * Copyright (C) 2016 Florent Revest <florent.revest@free-electrons.com>\n+ * Copyright (C) 2018 Paul Kocialkowski <paul.kocialkowski@bootlin.com>\n+ * Copyright (C) 2018 Bootlin\n+ */\n+\n+#ifndef _RPIVID_VIDEO_H_\n+#define _RPIVID_VIDEO_H_\n+\n+struct rpivid_format {\n+\tu32\t\tpixelformat;\n+\tu32\t\tdirections;\n+\tunsigned int\tcapabilities;\n+};\n+\n+extern const struct v4l2_ioctl_ops rpivid_ioctl_ops;\n+\n+int rpivid_queue_init(void *priv, struct vb2_queue *src_vq,\n+\t\t      struct vb2_queue *dst_vq);\n+int rpivid_prepare_src_format(struct v4l2_pix_format *pix_fmt);\n+int rpivid_prepare_dst_format(struct v4l2_pix_format *pix_fmt);\n+\n+#endif\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0201-mmc-sdhci-Silence-MMC-warnings.patch",
    "content": "From 966a8df34ba0d98908dd381f27f6cfd615b3cb74 Mon Sep 17 00:00:00 2001\nFrom: Maxime Ripard <maxime@cerno.tech>\nDate: Fri, 6 Dec 2019 13:05:27 +0100\nSubject: [PATCH] mmc: sdhci: Silence MMC warnings\n\nWhen the MMC isn't plugged in, the driver will spam the console which is\npretty annoying when using NFS.\n\nSigned-off-by: Maxime Ripard <maxime@cerno.tech>\n---\n drivers/mmc/host/sdhci.c | 6 +++---\n 1 file changed, 3 insertions(+), 3 deletions(-)\n\n--- a/drivers/mmc/host/sdhci.c\n+++ b/drivers/mmc/host/sdhci.c\n@@ -41,7 +41,7 @@\n \tpr_debug(\"%s: \" DRIVER_NAME \": \" f, mmc_hostname(host->mmc), ## x)\n \n #define SDHCI_DUMP(f, x...) \\\n-\tpr_err(\"%s: \" DRIVER_NAME \": \" f, mmc_hostname(host->mmc), ## x)\n+\tpr_debug(\"%s: \" DRIVER_NAME \": \" f, mmc_hostname(host->mmc), ## x)\n \n #define MAX_TUNING_LOOP 40\n \n@@ -3145,7 +3145,7 @@ static void sdhci_timeout_timer(struct t\n \tspin_lock_irqsave(&host->lock, flags);\n \n \tif (host->cmd && !sdhci_data_line_cmd(host->cmd)) {\n-\t\tpr_err(\"%s: Timeout waiting for hardware cmd interrupt.\\n\",\n+\t\tpr_debug(\"%s: Timeout waiting for hardware cmd interrupt.\\n\",\n \t\t       mmc_hostname(host->mmc));\n \t\tsdhci_dumpregs(host);\n \n@@ -3167,7 +3167,7 @@ static void sdhci_timeout_data_timer(str\n \n \tif (host->data || host->data_cmd ||\n \t    (host->cmd && sdhci_data_line_cmd(host->cmd))) {\n-\t\tpr_err(\"%s: Timeout waiting for hardware interrupt.\\n\",\n+\t\tpr_debug(\"%s: Timeout waiting for hardware interrupt.\\n\",\n \t\t       mmc_hostname(host->mmc));\n \t\tsdhci_dumpregs(host);\n \n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0202-dt-bindings-clock-Add-a-binding-for-the-RPi-Firmware.patch",
    "content": "From 5567ea58dd5814de7dd1c9756ab985fd0f753bce Mon Sep 17 00:00:00 2001\nFrom: Maxime Ripard <maxime@cerno.tech>\nDate: Thu, 13 Feb 2020 17:51:09 +0100\nSubject: [PATCH] dt-bindings: clock: Add a binding for the RPi\n Firmware clocks\n\nThe firmare running on the RPi VideoCore can be used to discover and\nchange the various clocks running in the BCM2711. Since devices will\nneed to use them through the DT, let's add a pretty simple binding.\n\nCc: Michael Turquette <mturquette@baylibre.com>\nCc: Stephen Boyd <sboyd@kernel.org>\nCc: Rob Herring <robh+dt@kernel.org>\nCc: linux-clk@vger.kernel.org\nCc: devicetree@vger.kernel.org\nSigned-off-by: Maxime Ripard <maxime@cerno.tech>\n---\n .../clock/raspberrypi,firmware-clocks.yaml    | 39 +++++++++++++++++++\n 1 file changed, 39 insertions(+)\n create mode 100644 Documentation/devicetree/bindings/clock/raspberrypi,firmware-clocks.yaml\n\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/clock/raspberrypi,firmware-clocks.yaml\n@@ -0,0 +1,39 @@\n+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)\n+%YAML 1.2\n+---\n+$id: http://devicetree.org/schemas/clock/raspberrypi,firmware-clocks.yaml#\n+$schema: http://devicetree.org/meta-schemas/core.yaml#\n+\n+title: RaspberryPi Firmware Clocks Device Tree Bindings\n+\n+maintainers:\n+  - Maxime Ripard <mripard@kernel.org>\n+\n+properties:\n+  \"#clock-cells\":\n+    const: 1\n+\n+  compatible:\n+    const: raspberrypi,firmware-clocks\n+\n+  raspberrypi,firmware:\n+    $ref: /schemas/types.yaml#/definitions/phandle\n+    description: >\n+      Phandle to the mailbox node to communicate with the firmware.\n+\n+required:\n+  - \"#clock-cells\"\n+  - compatible\n+  - raspberrypi,firmware\n+\n+additionalProperties: false\n+\n+examples:\n+  - |\n+    firmware_clocks: firmware-clocks {\n+        compatible = \"raspberrypi,firmware-clocks\";\n+        raspberrypi,firmware = <&firmware>;\n+        #clock-cells = <1>;\n+    };\n+\n+...\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0203-dt-bindings-display-vc4-hdmi-Add-BCM2711-HDMI-contro.patch",
    "content": "From 2cbd6432676b68e210f9ff4a1c1dd5d5463a6d6b Mon Sep 17 00:00:00 2001\nFrom: Maxime Ripard <maxime@cerno.tech>\nDate: Thu, 13 Feb 2020 16:45:24 +0100\nSubject: [PATCH] dt-bindings: display: vc4: hdmi: Add BCM2711 HDMI\n controllers bindings\n\nThe HDMI controllers found in the BCM2711 SoC need some adjustments to the\nbindings, especially since the registers have been shuffled around in more\nregister ranges.\n\nCc: Rob Herring <robh+dt@kernel.org>\nCc: devicetree@vger.kernel.org\nSigned-off-by: Maxime Ripard <maxime@cerno.tech>\n---\n .../bindings/display/brcm,bcm2835-hdmi.yaml   | 118 ++++++++++++++++--\n 1 file changed, 109 insertions(+), 9 deletions(-)\n\n--- a/Documentation/devicetree/bindings/display/brcm,bcm2835-hdmi.yaml\n+++ b/Documentation/devicetree/bindings/display/brcm,bcm2835-hdmi.yaml\n@@ -11,24 +11,58 @@ maintainers:\n \n properties:\n   compatible:\n-    const: brcm,bcm2835-hdmi\n+    enum:\n+      - brcm,bcm2835-hdmi\n+      - brcm,bcm2711-hdmi0\n+      - brcm,bcm2711-hdmi1\n \n   reg:\n+    oneOf:\n+      - items:\n+        - description: HDMI register range\n+        - description: HD register range\n+\n+      - items:\n+        - description: HDMI controller register range\n+        - description: DVP register range\n+        - description: HDMI PHY register range\n+        - description: Rate Manager register range\n+        - description: Packet RAM register range\n+        - description: Metadata RAM register range\n+        - description: CSC register range\n+        - description: CEC register range\n+        - description: HD register range\n+\n+  reg-names:\n     items:\n-      - description: HDMI register range\n-      - description: HD register range\n+      - const: hdmi\n+      - const: dvp\n+      - const: phy\n+      - const: rm\n+      - const: packet\n+      - const: metadata\n+      - const: csc\n+      - const: cec\n+      - const: hd\n \n   interrupts:\n     minItems: 2\n \n   clocks:\n-    items:\n-      - description: The pixel clock\n-      - description: The HDMI state machine clock\n+    oneOf:\n+      - items:\n+        - description: The pixel clock\n+        - description: The HDMI state machine clock\n+\n+      - items:\n+        - description: The HDMI state machine clock\n \n   clock-names:\n-    items:\n-      - const: pixel\n+    oneOf:\n+      - items:\n+        - const: pixel\n+        - const: hdmi\n+\n       - const: hdmi\n \n   ddc:\n@@ -50,15 +84,54 @@ properties:\n   dma-names:\n     const: audio-rx\n \n+  resets:\n+    maxItems: 1\n+\n required:\n   - compatible\n   - reg\n-  - interrupts\n   - clocks\n   - ddc\n \n additionalProperties: false\n \n+if:\n+  properties:\n+    compatible:\n+      contains:\n+        enum:\n+          - brcm,bcm2711-hdmi0\n+          - brcm,bcm2711-hdmi1\n+\n+then:\n+  properties:\n+    reg:\n+      minItems: 9\n+\n+    clocks:\n+      maxItems: 1\n+\n+    clock-names:\n+      maxItems: 1\n+\n+  required:\n+    - reg-names\n+    - resets\n+\n+else:\n+  properties:\n+    reg:\n+      maxItems: 2\n+\n+    clocks:\n+      minItems: 2\n+\n+    clock-names:\n+      minItems: 2\n+\n+  required:\n+    - interrupts\n+\n examples:\n   - |\n     #include <dt-bindings/clock/bcm2835.h>\n@@ -76,4 +149,31 @@ examples:\n         clock-names = \"pixel\", \"hdmi\";\n     };\n \n+  - |\n+    hdmi0: hdmi@7ef00700 {\n+        compatible = \"brcm,bcm2711-hdmi0\";\n+        reg = <0x7ef00700 0x300>,\n+              <0x7ef00300 0x200>,\n+              <0x7ef00f00 0x80>,\n+              <0x7ef00f80 0x80>,\n+              <0x7ef01b00 0x200>,\n+              <0x7ef01f00 0x400>,\n+              <0x7ef00200 0x80>,\n+              <0x7ef04300 0x100>,\n+              <0x7ef20000 0x100>;\n+        reg-names = \"hdmi\",\n+                    \"dvp\",\n+                    \"phy\",\n+                    \"rm\",\n+                    \"packet\",\n+                    \"metadata\",\n+                    \"csc\",\n+                    \"cec\",\n+                    \"hd\";\n+        clocks = <&firmware_clocks 13>;\n+        clock-names = \"hdmi\";\n+        resets = <&dvp 0>;\n+        ddc = <&ddc0>;\n+    };\n+\n ...\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0204-drm-Checking-of-the-pitch-is-only-valid-for-linear-f.patch",
    "content": "From c24a6aef5b7ef24fb5c6f83ada015b06bcc3c665 Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Mon, 27 Jan 2020 10:22:44 +0000\nSubject: [PATCH] drm: Checking of the pitch is only valid for linear\n formats\n\nframebuffer_check was computing a minimum pitch value and ensuring\nthat the provided value was greater than this.\nThat check is only valid if the format is linear.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n drivers/gpu/drm/drm_framebuffer.c | 16 ++++++++++------\n 1 file changed, 10 insertions(+), 6 deletions(-)\n\n--- a/drivers/gpu/drm/drm_framebuffer.c\n+++ b/drivers/gpu/drm/drm_framebuffer.c\n@@ -217,12 +217,16 @@ static int framebuffer_check(struct drm_\n \t\tif (min_pitch > UINT_MAX)\n \t\t\treturn -ERANGE;\n \n-\t\tif ((uint64_t) height * r->pitches[i] + r->offsets[i] > UINT_MAX)\n-\t\t\treturn -ERANGE;\n+\t\tif (r->modifier[i] == DRM_FORMAT_MOD_LINEAR) {\n+\t\t\tif ((uint64_t)height * r->pitches[i] + r->offsets[i] >\n+\t\t\t\t\t\t\t\tUINT_MAX)\n+\t\t\t\treturn -ERANGE;\n \n-\t\tif (block_size && r->pitches[i] < min_pitch) {\n-\t\t\tDRM_DEBUG_KMS(\"bad pitch %u for plane %d\\n\", r->pitches[i], i);\n-\t\t\treturn -EINVAL;\n+\t\t\tif (block_size && r->pitches[i] < min_pitch) {\n+\t\t\t\tDRM_DEBUG_KMS(\"bad pitch %u for plane %d\\n\",\n+\t\t\t\t\t      r->pitches[i], i);\n+\t\t\t\treturn -EINVAL;\n+\t\t\t}\n \t\t}\n \n \t\tif (r->modifier[i] && !(r->flags & DRM_MODE_FB_MODIFIERS)) {\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0205-overlays-Fix-dtc-warnings-in-i2c-gpio.patch",
    "content": "From 987af76904b945d39b90e6a5294f8f2f691fb8fb Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.com>\nDate: Wed, 8 Apr 2020 11:59:39 +0100\nSubject: [PATCH] overlays: Fix dtc warnings in i2c-gpio\n\nBetter late than never.\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.com>\n---\n arch/arm/boot/dts/overlays/i2c-gpio-overlay.dts | 3 +++\n 1 file changed, 3 insertions(+)\n\n--- a/arch/arm/boot/dts/overlays/i2c-gpio-overlay.dts\n+++ b/arch/arm/boot/dts/overlays/i2c-gpio-overlay.dts\n@@ -11,6 +11,9 @@\n \t\ttarget-path = \"/\";\n \n \t\t__overlay__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n \t\t\ti2c_gpio: i2c@0 {\n \t\t\t\treg = <0xffffffff>;\n \t\t\t\tcompatible = \"i2c-gpio\";\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0206-driver-char-rpivid-Remove-legacy-name-support.patch",
    "content": "From 8967fee444367746114e366fd48331e56f0d36d6 Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.com>\nDate: Mon, 20 Apr 2020 22:18:52 +0100\nSubject: [PATCH] driver: char: rpivid: Remove legacy name support\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.com>\n---\n drivers/char/broadcom/rpivid-mem.c | 22 ----------------------\n 1 file changed, 22 deletions(-)\n\n--- a/drivers/char/broadcom/rpivid-mem.c\n+++ b/drivers/char/broadcom/rpivid-mem.c\n@@ -193,32 +193,11 @@ static int rpivid_mem_probe(struct platf\n \t\tgoto failed_device_create;\n \t}\n \n-\t/* Legacy alias */\n-\t{\n-\t\tchar *oldname = kstrdup(priv->name, GFP_KERNEL);\n-\n-\t\toldname[1] = 'a';\n-\t\toldname[2] = 'r';\n-\t\toldname[3] = 'g';\n-\t\toldname[4] = 'o';\n-\t\toldname[5] = 'n';\n-\t\tdev = device_create(priv->class, NULL, priv->devid + 1, NULL,\n-\t\t\t\t    oldname + 1);\n-\t\tkfree(oldname);\n-\n-\t\tif (IS_ERR(dev)) {\n-\t\t\terr = PTR_ERR(dev);\n-\t\t\tgoto failed_legacy_device_create;\n-\t\t}\n-\t}\n-\n \tdev_info(priv->dev, \"%s initialised: Registers at 0x%08lx length 0x%08lx\",\n \t\tpriv->name, priv->regs_phys, priv->mem_window_len);\n \n \treturn 0;\n \n-failed_legacy_device_create:\n-\tdevice_destroy(priv->class, priv->devid);\n failed_device_create:\n \tclass_destroy(priv->class);\n failed_class_create:\n@@ -238,7 +217,6 @@ static int rpivid_mem_remove(struct plat\n \tstruct device *dev = &pdev->dev;\n \tstruct rpivid_mem_priv *priv = platform_get_drvdata(pdev);\n \n-\tdevice_destroy(priv->class, priv->devid + 1);\n \tdevice_destroy(priv->class, priv->devid);\n \tclass_destroy(priv->class);\n \tcdev_del(&priv->rpivid_mem_cdev);\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0207-spi-Force-CS_HIGH-if-GPIO-descriptors-are-used.patch",
    "content": "From 4b6c8cda93174f36754f549498c133ccaeaa2218 Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.com>\nDate: Fri, 17 Apr 2020 10:46:19 +0100\nSubject: [PATCH] spi: Force CS_HIGH if GPIO descriptors are used\n\nCommit f3186dd87669 (\"spi: Optionally use GPIO descriptors for CS GPIOs\")\namended of_spi_parse_dt() to always set SPI_CS_HIGH for SPI slaves whose\nChip Select is defined by a \"cs-gpios\" devicetree property.\n\nThis change breaks drivers whose probe functions set the mode field of\nthe spi_device because in doing so they clear the SPI_CS_HIGH flag.\n\nFix by setting SPI_CS_HIGH in spi_setup (under the same conditions as\nin of_spi_parse_dt()).\n\nSee also: 83b2a8fe43bd (\"spi: spidev: Fix CS polarity if GPIO descriptors are used\")\n\nFixes: f3186dd87669 (\"spi: Optionally use GPIO descriptors for CS GPIOs\")\nSigned-off-by: Phil Elwell <phil@raspberrypi.com>\n\nSQUASH: spi: Demote SPI_CS_HIGH warning to KERN_DEBUG\n\nThis warning is unavoidable from a client's perspective and\ndoesn't indicate anything wrong (just surprising).\n\nSQUASH with \"spi: use_gpio_descriptor fixup moved to spi_setup\"\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.com>\n---\n drivers/spi/spi.c | 9 +++++++++\n 1 file changed, 9 insertions(+)\n\n--- a/drivers/spi/spi.c\n+++ b/drivers/spi/spi.c\n@@ -3338,6 +3338,7 @@ static int __spi_validate_bits_per_word(\n  */\n int spi_setup(struct spi_device *spi)\n {\n+\tstruct spi_controller *ctlr = spi->controller;\n \tunsigned\tbad_bits, ugly_bits;\n \tint\t\tstatus;\n \n@@ -3355,6 +3356,14 @@ int spi_setup(struct spi_device *spi)\n \t\t(SPI_TX_DUAL | SPI_TX_QUAD | SPI_TX_OCTAL |\n \t\t SPI_RX_DUAL | SPI_RX_QUAD | SPI_RX_OCTAL)))\n \t\treturn -EINVAL;\n+\n+\tif (ctlr->use_gpio_descriptors && ctlr->cs_gpiods &&\n+\t    ctlr->cs_gpiods[spi->chip_select] && !(spi->mode & SPI_CS_HIGH)) {\n+\t\tdev_dbg(&spi->dev,\n+\t\t\t\"setup: forcing CS_HIGH (use_gpio_descriptors)\\n\");\n+\t\tspi->mode |= SPI_CS_HIGH;\n+\t}\n+\n \t/* help drivers fail *cleanly* when they need options\n \t * that aren't supported with their current controller\n \t * SPI_CS_WORD has a fallback software implementation,\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0208-driver-char-rpivid-Don-t-map-more-than-wanted.patch",
    "content": "From 7b7873548f21f42e6d3032d038d3e8b2c2b22939 Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.com>\nDate: Tue, 21 Apr 2020 11:30:23 +0100\nSubject: [PATCH] driver: char: rpivid: Don't map more than wanted\n\nLimit mappings to the permitted range, but don't map more than asked\nfor otherwise we walk off the end of the allocated VMA.\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.com>\n---\n drivers/char/broadcom/rpivid-mem.c | 12 ++++++------\n 1 file changed, 6 insertions(+), 6 deletions(-)\n\n--- a/drivers/char/broadcom/rpivid-mem.c\n+++ b/drivers/char/broadcom/rpivid-mem.c\n@@ -100,6 +100,7 @@ static int rpivid_mem_mmap(struct file *\n {\n \tstruct rpivid_mem_priv *priv;\n \tunsigned long pages;\n+\tunsigned long len;\n \n \tpriv = file->private_data;\n \tpages = priv->regs_phys >> PAGE_SHIFT;\n@@ -107,14 +108,13 @@ static int rpivid_mem_mmap(struct file *\n \t * The address decode is far larger than the actual number of registers.\n \t * Just map the whole lot in.\n \t */\n-\tvma->vm_page_prot = phys_mem_access_prot(file, pages,\n-\t\t\t\t\t\t priv->mem_window_len,\n+\tlen = min(vma->vm_end - vma->vm_start, priv->mem_window_len);\n+\tvma->vm_page_prot = phys_mem_access_prot(file, pages, len,\n \t\t\t\t\t\t vma->vm_page_prot);\n \tvma->vm_ops = &rpivid_mem_vm_ops;\n \tif (remap_pfn_range(vma, vma->vm_start,\n-\t\t\tpages,\n-\t\t\tpriv->mem_window_len,\n-\t\t\tvma->vm_page_prot)) {\n+\t\t\t    pages, len,\n+\t\t\t    vma->vm_page_prot)) {\n \t\treturn -EAGAIN;\n \t}\n \treturn 0;\n@@ -156,7 +156,7 @@ static int rpivid_mem_probe(struct platf\n \tioresource = platform_get_resource(pdev, IORESOURCE_MEM, 0);\n \tif (ioresource) {\n \t\tpriv->regs_phys = ioresource->start;\n-\t\tpriv->mem_window_len = ioresource->end - ioresource->start;\n+\t\tpriv->mem_window_len = (ioresource->end + 1) - ioresource->start;\n \t} else {\n \t\tdev_err(priv->dev, \"failed to get IO resource\");\n \t\terr = -ENOENT;\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0209-media-bcm2835-unicam-Driver-for-CCP2-CSI2-camera-int.patch",
    "content": "From cbbd6cbf9376ae582e1141f41a0011341cac0fc5 Mon Sep 17 00:00:00 2001\nFrom: Naushir Patuck <naush@raspberrypi.com>\nDate: Wed, 1 Apr 2020 08:39:49 +0100\nSubject: [PATCH] media: bcm2835-unicam: Driver for CCP2/CSI2 camera\n interface\n\nAdd driver for the Unicam camera receiver block on\nBCM283x processors.\n\nThis commit is made up of a series of changes cherry-picked from the\nrpi-4.19.y branch.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\nSigned-off-by: Naushir Patuck <naush@raspberrypi.com>\n---\n MAINTAINERS                                   |    2 +-\n drivers/media/platform/Kconfig                |    1 +\n drivers/media/platform/Makefile               |    2 +\n drivers/media/platform/bcm2835/Kconfig        |   14 +\n drivers/media/platform/bcm2835/Makefile       |    3 +\n .../media/platform/bcm2835/bcm2835-unicam.c   | 2369 +++++++++++++++++\n .../media/platform/bcm2835/vc4-regs-unicam.h  |  253 ++\n 7 files changed, 2643 insertions(+), 1 deletion(-)\n create mode 100644 drivers/media/platform/bcm2835/Kconfig\n create mode 100644 drivers/media/platform/bcm2835/Makefile\n create mode 100644 drivers/media/platform/bcm2835/bcm2835-unicam.c\n create mode 100644 drivers/media/platform/bcm2835/vc4-regs-unicam.h\n\n--- a/MAINTAINERS\n+++ b/MAINTAINERS\n@@ -3426,7 +3426,7 @@ F:\tDocumentation/devicetree/bindings/med\n F:\tdrivers/staging/media/rpivid\n \n BROADCOM BCM2835 CAMERA DRIVER\n-M:\tDave Stevenson <dave.stevenson@raspberrypi.org>\n+M:\tRaspberry Pi Kernel Maintenance <kernel-list@raspberrypi.com>\n L:\tlinux-media@vger.kernel.org\n S:\tMaintained\n F:\tdrivers/media/platform/bcm2835/\n--- a/drivers/media/platform/Kconfig\n+++ b/drivers/media/platform/Kconfig\n@@ -152,6 +152,7 @@ source \"drivers/media/platform/am437x/Kc\n source \"drivers/media/platform/xilinx/Kconfig\"\n source \"drivers/media/platform/rcar-vin/Kconfig\"\n source \"drivers/media/platform/atmel/Kconfig\"\n+source \"drivers/media/platform/bcm2835/Kconfig\"\n source \"drivers/media/platform/sunxi/Kconfig\"\n \n config VIDEO_TI_CAL\n--- a/drivers/media/platform/Makefile\n+++ b/drivers/media/platform/Makefile\n@@ -79,4 +79,6 @@ obj-$(CONFIG_VIDEO_QCOM_CAMSS)\t\t+= qcom/\n \n obj-$(CONFIG_VIDEO_QCOM_VENUS)\t\t+= qcom/venus/\n \n+obj-y\t\t\t\t\t+= bcm2835/\n+\n obj-y\t\t\t\t\t+= sunxi/\n--- /dev/null\n+++ b/drivers/media/platform/bcm2835/Kconfig\n@@ -0,0 +1,14 @@\n+# Broadcom VideoCore4 V4L2 camera support\n+\n+config VIDEO_BCM2835_UNICAM\n+\ttristate \"Broadcom BCM2835 Unicam video capture driver\"\n+\tdepends on VIDEO_V4L2 && VIDEO_V4L2_SUBDEV_API && MEDIA_CONTROLLER\n+\tdepends on ARCH_BCM2835 || COMPILE_TEST\n+\tselect VIDEOBUF2_DMA_CONTIG\n+\tselect V4L2_FWNODE\n+\thelp\n+\t  Say Y here to enable V4L2 subdevice for CSI2 receiver.\n+\t  This is a V4L2 subdevice that interfaces directly to the VC4 peripheral.\n+\n+\t   To compile this driver as a module, choose M here. The module\n+\t   will be called bcm2835-unicam.\n--- /dev/null\n+++ b/drivers/media/platform/bcm2835/Makefile\n@@ -0,0 +1,3 @@\n+# Makefile for BCM2835 Unicam driver\n+\n+obj-$(CONFIG_VIDEO_BCM2835_UNICAM) += bcm2835-unicam.o\n--- /dev/null\n+++ b/drivers/media/platform/bcm2835/bcm2835-unicam.c\n@@ -0,0 +1,2369 @@\n+// SPDX-License-Identifier: GPL-2.0-only\n+/*\n+ * BCM2835 Unicam Capture Driver\n+ *\n+ * Copyright (C) 2017-2020 - Raspberry Pi (Trading) Ltd.\n+ *\n+ * Dave Stevenson <dave.stevenson@raspberrypi.com>\n+ *\n+ * Based on TI am437x driver by\n+ *   Benoit Parrot <bparrot@ti.com>\n+ *   Lad, Prabhakar <prabhakar.csengg@gmail.com>\n+ *\n+ * and TI CAL camera interface driver by\n+ *    Benoit Parrot <bparrot@ti.com>\n+ *\n+ *\n+ * There are two camera drivers in the kernel for BCM283x - this one\n+ * and bcm2835-camera (currently in staging).\n+ *\n+ * This driver directly controls the Unicam peripheral - there is no\n+ * involvement with the VideoCore firmware. Unicam receives CSI-2 or\n+ * CCP2 data and writes it into SDRAM.\n+ * The only potential processing options are to repack Bayer data into an\n+ * alternate format, and applying windowing.\n+ * The repacking does not shift the data, so can repack V4L2_PIX_FMT_Sxxxx10P\n+ * to V4L2_PIX_FMT_Sxxxx10, or V4L2_PIX_FMT_Sxxxx12P to V4L2_PIX_FMT_Sxxxx12,\n+ * but not generically up to V4L2_PIX_FMT_Sxxxx16. The driver will add both\n+ * formats where the relevant formats are defined, and will automatically\n+ * configure the repacking as required.\n+ * Support for windowing may be added later.\n+ *\n+ * It should be possible to connect this driver to any sensor with a\n+ * suitable output interface and V4L2 subdevice driver.\n+ *\n+ * bcm2835-camera uses the VideoCore firmware to control the sensor,\n+ * Unicam, ISP, and all tuner control loops. Fully processed frames are\n+ * delivered to the driver by the firmware. It only has sensor drivers\n+ * for Omnivision OV5647, and Sony IMX219 sensors.\n+ *\n+ * The two drivers are mutually exclusive for the same Unicam instance.\n+ * The VideoCore firmware checks the device tree configuration during boot.\n+ * If it finds device tree nodes called csi0 or csi1 it will block the\n+ * firmware from accessing the peripheral, and bcm2835-camera will\n+ * not be able to stream data.\n+ */\n+\n+#include <linux/clk.h>\n+#include <linux/delay.h>\n+#include <linux/device.h>\n+#include <linux/err.h>\n+#include <linux/init.h>\n+#include <linux/interrupt.h>\n+#include <linux/io.h>\n+#include <linux/module.h>\n+#include <linux/of_device.h>\n+#include <linux/of_graph.h>\n+#include <linux/pinctrl/consumer.h>\n+#include <linux/platform_device.h>\n+#include <linux/pm_runtime.h>\n+#include <linux/slab.h>\n+#include <linux/uaccess.h>\n+#include <linux/videodev2.h>\n+\n+#include <media/v4l2-common.h>\n+#include <media/v4l2-ctrls.h>\n+#include <media/v4l2-dev.h>\n+#include <media/v4l2-device.h>\n+#include <media/v4l2-dv-timings.h>\n+#include <media/v4l2-event.h>\n+#include <media/v4l2-ioctl.h>\n+#include <media/v4l2-fwnode.h>\n+#include <media/videobuf2-dma-contig.h>\n+\n+#include \"vc4-regs-unicam.h\"\n+\n+#define UNICAM_MODULE_NAME\t\"unicam\"\n+#define UNICAM_VERSION\t\t\"0.1.0\"\n+\n+static int debug;\n+module_param(debug, int, 0644);\n+MODULE_PARM_DESC(debug, \"Debug level 0-3\");\n+\n+#define unicam_dbg(level, dev, fmt, arg...)\t\\\n+\t\tv4l2_dbg(level, debug, &(dev)->v4l2_dev, fmt, ##arg)\n+#define unicam_info(dev, fmt, arg...)\t\\\n+\t\tv4l2_info(&(dev)->v4l2_dev, fmt, ##arg)\n+#define unicam_err(dev, fmt, arg...)\t\\\n+\t\tv4l2_err(&(dev)->v4l2_dev, fmt, ##arg)\n+\n+/* To protect against a dodgy sensor driver never returning an error from\n+ * enum_mbus_code, set a maximum index value to be used.\n+ */\n+#define MAX_ENUM_MBUS_CODE\t128\n+\n+/*\n+ * Stride is a 16 bit register, but also has to be a multiple of 32.\n+ */\n+#define BPL_ALIGNMENT\t\t32\n+#define MAX_BYTESPERLINE\t((1 << 16) - BPL_ALIGNMENT)\n+/*\n+ * Max width is therefore determined by the max stride divided by\n+ * the number of bits per pixel. Take 32bpp as a\n+ * worst case.\n+ * No imposed limit on the height, so adopt a square image for want\n+ * of anything better.\n+ */\n+#define MAX_WIDTH\t(MAX_BYTESPERLINE / 4)\n+#define MAX_HEIGHT\tMAX_WIDTH\n+/* Define a nominal minimum image size */\n+#define MIN_WIDTH\t16\n+#define MIN_HEIGHT\t16\n+\n+/*\n+ * struct unicam_fmt - Unicam media bus format information\n+ * @pixelformat: V4L2 pixel format FCC identifier. 0 if n/a.\n+ * @repacked_fourcc: V4L2 pixel format FCC identifier if the data is expanded\n+ * out to 16bpp. 0 if n/a.\n+ * @code: V4L2 media bus format code.\n+ * @depth: Bits per pixel as delivered from the source.\n+ * @csi_dt: CSI data type.\n+ * @check_variants: Flag to denote that there are multiple mediabus formats\n+ *\t\tstill in the list that could match this V4L2 format.\n+ */\n+struct unicam_fmt {\n+\tu32\tfourcc;\n+\tu32\trepacked_fourcc;\n+\tu32\tcode;\n+\tu8\tdepth;\n+\tu8\tcsi_dt;\n+\tu8\tcheck_variants;\n+};\n+\n+static const struct unicam_fmt formats[] = {\n+\t/* YUV Formats */\n+\t{\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_YUYV,\n+\t\t.code\t\t= MEDIA_BUS_FMT_YUYV8_2X8,\n+\t\t.depth\t\t= 16,\n+\t\t.csi_dt\t\t= 0x1e,\n+\t\t.check_variants = 1,\n+\t}, {\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_UYVY,\n+\t\t.code\t\t= MEDIA_BUS_FMT_UYVY8_2X8,\n+\t\t.depth\t\t= 16,\n+\t\t.csi_dt\t\t= 0x1e,\n+\t\t.check_variants = 1,\n+\t}, {\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_YVYU,\n+\t\t.code\t\t= MEDIA_BUS_FMT_YVYU8_2X8,\n+\t\t.depth\t\t= 16,\n+\t\t.csi_dt\t\t= 0x1e,\n+\t\t.check_variants = 1,\n+\t}, {\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_VYUY,\n+\t\t.code\t\t= MEDIA_BUS_FMT_VYUY8_2X8,\n+\t\t.depth\t\t= 16,\n+\t\t.csi_dt\t\t= 0x1e,\n+\t\t.check_variants = 1,\n+\t}, {\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_YUYV,\n+\t\t.code\t\t= MEDIA_BUS_FMT_YUYV8_1X16,\n+\t\t.depth\t\t= 16,\n+\t\t.csi_dt\t\t= 0x1e,\n+\t}, {\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_UYVY,\n+\t\t.code\t\t= MEDIA_BUS_FMT_UYVY8_1X16,\n+\t\t.depth\t\t= 16,\n+\t\t.csi_dt\t\t= 0x1e,\n+\t}, {\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_YVYU,\n+\t\t.code\t\t= MEDIA_BUS_FMT_YVYU8_1X16,\n+\t\t.depth\t\t= 16,\n+\t\t.csi_dt\t\t= 0x1e,\n+\t}, {\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_VYUY,\n+\t\t.code\t\t= MEDIA_BUS_FMT_VYUY8_1X16,\n+\t\t.depth\t\t= 16,\n+\t\t.csi_dt\t\t= 0x1e,\n+\t}, {\n+\t/* RGB Formats */\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_RGB565, /* gggbbbbb rrrrrggg */\n+\t\t.code\t\t= MEDIA_BUS_FMT_RGB565_2X8_LE,\n+\t\t.depth\t\t= 16,\n+\t\t.csi_dt\t\t= 0x22,\n+\t}, {\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_RGB565X, /* rrrrrggg gggbbbbb */\n+\t\t.code\t\t= MEDIA_BUS_FMT_RGB565_2X8_BE,\n+\t\t.depth\t\t= 16,\n+\t\t.csi_dt\t\t= 0x22\n+\t}, {\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_RGB555, /* gggbbbbb arrrrrgg */\n+\t\t.code\t\t= MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE,\n+\t\t.depth\t\t= 16,\n+\t\t.csi_dt\t\t= 0x21,\n+\t}, {\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_RGB555X, /* arrrrrgg gggbbbbb */\n+\t\t.code\t\t= MEDIA_BUS_FMT_RGB555_2X8_PADHI_BE,\n+\t\t.depth\t\t= 16,\n+\t\t.csi_dt\t\t= 0x21,\n+\t}, {\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_RGB24, /* rgb */\n+\t\t.code\t\t= MEDIA_BUS_FMT_RGB888_1X24,\n+\t\t.depth\t\t= 24,\n+\t\t.csi_dt\t\t= 0x24,\n+\t}, {\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_BGR24, /* bgr */\n+\t\t.code\t\t= MEDIA_BUS_FMT_BGR888_1X24,\n+\t\t.depth\t\t= 24,\n+\t\t.csi_dt\t\t= 0x24,\n+\t}, {\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_RGB32, /* argb */\n+\t\t.code\t\t= MEDIA_BUS_FMT_ARGB8888_1X32,\n+\t\t.depth\t\t= 32,\n+\t\t.csi_dt\t\t= 0x0,\n+\t}, {\n+\t/* Bayer Formats */\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_SBGGR8,\n+\t\t.code\t\t= MEDIA_BUS_FMT_SBGGR8_1X8,\n+\t\t.depth\t\t= 8,\n+\t\t.csi_dt\t\t= 0x2a,\n+\t}, {\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_SGBRG8,\n+\t\t.code\t\t= MEDIA_BUS_FMT_SGBRG8_1X8,\n+\t\t.depth\t\t= 8,\n+\t\t.csi_dt\t\t= 0x2a,\n+\t}, {\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_SGRBG8,\n+\t\t.code\t\t= MEDIA_BUS_FMT_SGRBG8_1X8,\n+\t\t.depth\t\t= 8,\n+\t\t.csi_dt\t\t= 0x2a,\n+\t}, {\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_SRGGB8,\n+\t\t.code\t\t= MEDIA_BUS_FMT_SRGGB8_1X8,\n+\t\t.depth\t\t= 8,\n+\t\t.csi_dt\t\t= 0x2a,\n+\t}, {\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_SBGGR10P,\n+\t\t.repacked_fourcc = V4L2_PIX_FMT_SBGGR10,\n+\t\t.code\t\t= MEDIA_BUS_FMT_SBGGR10_1X10,\n+\t\t.depth\t\t= 10,\n+\t\t.csi_dt\t\t= 0x2b,\n+\t}, {\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_SGBRG10P,\n+\t\t.repacked_fourcc = V4L2_PIX_FMT_SGBRG10,\n+\t\t.code\t\t= MEDIA_BUS_FMT_SGBRG10_1X10,\n+\t\t.depth\t\t= 10,\n+\t\t.csi_dt\t\t= 0x2b,\n+\t}, {\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_SGRBG10P,\n+\t\t.repacked_fourcc = V4L2_PIX_FMT_SGRBG10,\n+\t\t.code\t\t= MEDIA_BUS_FMT_SGRBG10_1X10,\n+\t\t.depth\t\t= 10,\n+\t\t.csi_dt\t\t= 0x2b,\n+\t}, {\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_SRGGB10P,\n+\t\t.repacked_fourcc = V4L2_PIX_FMT_SRGGB10,\n+\t\t.code\t\t= MEDIA_BUS_FMT_SRGGB10_1X10,\n+\t\t.depth\t\t= 10,\n+\t\t.csi_dt\t\t= 0x2b,\n+\t}, {\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_SBGGR12P,\n+\t\t.repacked_fourcc = V4L2_PIX_FMT_SBGGR12,\n+\t\t.code\t\t= MEDIA_BUS_FMT_SBGGR12_1X12,\n+\t\t.depth\t\t= 12,\n+\t\t.csi_dt\t\t= 0x2c,\n+\t}, {\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_SGBRG12P,\n+\t\t.repacked_fourcc = V4L2_PIX_FMT_SGBRG12,\n+\t\t.code\t\t= MEDIA_BUS_FMT_SGBRG12_1X12,\n+\t\t.depth\t\t= 12,\n+\t\t.csi_dt\t\t= 0x2c,\n+\t}, {\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_SGRBG12P,\n+\t\t.repacked_fourcc = V4L2_PIX_FMT_SGRBG12,\n+\t\t.code\t\t= MEDIA_BUS_FMT_SGRBG12_1X12,\n+\t\t.depth\t\t= 12,\n+\t\t.csi_dt\t\t= 0x2c,\n+\t}, {\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_SRGGB12P,\n+\t\t.repacked_fourcc = V4L2_PIX_FMT_SRGGB12,\n+\t\t.code\t\t= MEDIA_BUS_FMT_SRGGB12_1X12,\n+\t\t.depth\t\t= 12,\n+\t\t.csi_dt\t\t= 0x2c,\n+\t}, {\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_SBGGR14P,\n+\t\t.code\t\t= MEDIA_BUS_FMT_SBGGR14_1X14,\n+\t\t.depth\t\t= 14,\n+\t\t.csi_dt\t\t= 0x2d,\n+\t}, {\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_SGBRG14P,\n+\t\t.code\t\t= MEDIA_BUS_FMT_SGBRG14_1X14,\n+\t\t.depth\t\t= 14,\n+\t\t.csi_dt\t\t= 0x2d,\n+\t}, {\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_SGRBG14P,\n+\t\t.code\t\t= MEDIA_BUS_FMT_SGRBG14_1X14,\n+\t\t.depth\t\t= 14,\n+\t\t.csi_dt\t\t= 0x2d,\n+\t}, {\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_SRGGB14P,\n+\t\t.code\t\t= MEDIA_BUS_FMT_SRGGB14_1X14,\n+\t\t.depth\t\t= 14,\n+\t\t.csi_dt\t\t= 0x2d,\n+\t}, {\n+\t/*\n+\t * 16 bit Bayer formats could be supported, but there is no CSI2\n+\t * data_type defined for raw 16, and no sensors that produce it at\n+\t * present.\n+\t */\n+\n+\t/* Greyscale formats */\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_GREY,\n+\t\t.code\t\t= MEDIA_BUS_FMT_Y8_1X8,\n+\t\t.depth\t\t= 8,\n+\t\t.csi_dt\t\t= 0x2a,\n+\t}, {\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_Y10P,\n+\t\t.repacked_fourcc = V4L2_PIX_FMT_Y10,\n+\t\t.code\t\t= MEDIA_BUS_FMT_Y10_1X10,\n+\t\t.depth\t\t= 10,\n+\t\t.csi_dt\t\t= 0x2b,\n+\t}, {\n+\t\t/* NB There is no packed V4L2 fourcc for this format. */\n+\t\t.repacked_fourcc = V4L2_PIX_FMT_Y12,\n+\t\t.code\t\t= MEDIA_BUS_FMT_Y12_1X12,\n+\t\t.depth\t\t= 12,\n+\t\t.csi_dt\t\t= 0x2c,\n+\t},\n+};\n+\n+struct unicam_dmaqueue {\n+\tstruct list_head\tactive;\n+};\n+\n+struct unicam_buffer {\n+\tstruct vb2_v4l2_buffer vb;\n+\tstruct list_head list;\n+};\n+\n+struct unicam_cfg {\n+\t/* peripheral base address */\n+\tvoid __iomem *base;\n+\t/* clock gating base address */\n+\tvoid __iomem *clk_gate_base;\n+};\n+\n+#define MAX_POSSIBLE_PIX_FMTS (ARRAY_SIZE(formats))\n+\n+struct unicam_device {\n+\t/* V4l2 specific parameters */\n+\t/* Identifies video device for this channel */\n+\tstruct video_device video_dev;\n+\tstruct v4l2_ctrl_handler ctrl_handler;\n+\n+\tstruct v4l2_fwnode_endpoint endpoint;\n+\n+\tstruct v4l2_async_subdev asd;\n+\n+\t/* unicam cfg */\n+\tstruct unicam_cfg cfg;\n+\t/* clock handle */\n+\tstruct clk *clock;\n+\t/* V4l2 device */\n+\tstruct v4l2_device v4l2_dev;\n+\tstruct media_device mdev;\n+\tstruct media_pad pad;\n+\n+\t/* parent device */\n+\tstruct platform_device *pdev;\n+\t/* subdevice async Notifier */\n+\tstruct v4l2_async_notifier notifier;\n+\tunsigned int sequence;\n+\n+\t/* ptr to  sub device */\n+\tstruct v4l2_subdev *sensor;\n+\t/* Pad config for the sensor */\n+\tstruct v4l2_subdev_pad_config *sensor_config;\n+\t/* current input at the sub device */\n+\tint current_input;\n+\n+\t/* Pointer pointing to current v4l2_buffer */\n+\tstruct unicam_buffer *cur_frm;\n+\t/* Pointer pointing to next v4l2_buffer */\n+\tstruct unicam_buffer *next_frm;\n+\n+\t/* video capture */\n+\tconst struct unicam_fmt\t*fmt;\n+\t/* Used to store current pixel format */\n+\tstruct v4l2_format v_fmt;\n+\t/* Used to store current mbus frame format */\n+\tstruct v4l2_mbus_framefmt m_fmt;\n+\n+\tunsigned int virtual_channel;\n+\tenum v4l2_mbus_type bus_type;\n+\t/*\n+\t * Stores bus.mipi_csi2.flags for CSI2 sensors, or\n+\t * bus.mipi_csi1.strobe for CCP2.\n+\t */\n+\tunsigned int bus_flags;\n+\tunsigned int max_data_lanes;\n+\tunsigned int active_data_lanes;\n+\n+\tstruct v4l2_rect crop;\n+\n+\t/* Currently selected input on subdev */\n+\tint input;\n+\n+\t/* Buffer queue used in video-buf */\n+\tstruct vb2_queue buffer_queue;\n+\t/* Queue of filled frames */\n+\tstruct unicam_dmaqueue dma_queue;\n+\t/* IRQ lock for DMA queue */\n+\tspinlock_t dma_queue_lock;\n+\t/* lock used to access this structure */\n+\tstruct mutex lock;\n+\t/* Flag to denote that we are processing buffers */\n+\tint streaming;\n+};\n+\n+/* Hardware access */\n+#define clk_write(dev, val) writel((val) | 0x5a000000, (dev)->clk_gate_base)\n+#define clk_read(dev) readl((dev)->clk_gate_base)\n+\n+#define reg_read(dev, offset) readl((dev)->base + (offset))\n+#define reg_write(dev, offset, val) writel(val, (dev)->base + (offset))\n+\n+#define reg_read_field(dev, offset, mask) get_field(reg_read((dev), (offset), \\\n+\t\t\t\t\t\t    mask))\n+\n+static inline int get_field(u32 value, u32 mask)\n+{\n+\treturn (value & mask) >> __ffs(mask);\n+}\n+\n+static inline void set_field(u32 *valp, u32 field, u32 mask)\n+{\n+\tu32 val = *valp;\n+\n+\tval &= ~mask;\n+\tval |= (field << __ffs(mask)) & mask;\n+\t*valp = val;\n+}\n+\n+static inline void reg_write_field(struct unicam_cfg *dev, u32 offset,\n+\t\t\t\t   u32 field, u32 mask)\n+{\n+\tu32 val = reg_read((dev), (offset));\n+\n+\tset_field(&val, field, mask);\n+\treg_write((dev), (offset), val);\n+}\n+\n+/* Power management functions */\n+static inline int unicam_runtime_get(struct unicam_device *dev)\n+{\n+\treturn pm_runtime_get_sync(&dev->pdev->dev);\n+}\n+\n+static inline void unicam_runtime_put(struct unicam_device *dev)\n+{\n+\tpm_runtime_put_sync(&dev->pdev->dev);\n+}\n+\n+/* Format setup functions */\n+static const struct unicam_fmt *find_format_by_code(u32 code)\n+{\n+\tunsigned int i;\n+\n+\tfor (i = 0; i < ARRAY_SIZE(formats); i++) {\n+\t\tif (formats[i].code == code)\n+\t\t\treturn &formats[i];\n+\t}\n+\n+\treturn NULL;\n+}\n+\n+static int check_mbus_format(struct unicam_device *dev,\n+\t\t\t     const struct unicam_fmt *format)\n+{\n+\tstruct v4l2_subdev_mbus_code_enum mbus_code;\n+\tint ret = 0;\n+\tint i;\n+\n+\tfor (i = 0; !ret && i < MAX_ENUM_MBUS_CODE; i++) {\n+\t\tmemset(&mbus_code, 0, sizeof(mbus_code));\n+\t\tmbus_code.index = i;\n+\t\tmbus_code.which = V4L2_SUBDEV_FORMAT_ACTIVE;\n+\n+\t\tret = v4l2_subdev_call(dev->sensor, pad, enum_mbus_code,\n+\t\t\t\t       NULL, &mbus_code);\n+\n+\t\tif (!ret && mbus_code.code == format->code)\n+\t\t\treturn 1;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static const struct unicam_fmt *find_format_by_pix(struct unicam_device *dev,\n+\t\t\t\t\t\t   u32 pixelformat)\n+{\n+\tunsigned int i;\n+\n+\tfor (i = 0; i < ARRAY_SIZE(formats); i++) {\n+\t\tif (formats[i].fourcc == pixelformat ||\n+\t\t    formats[i].repacked_fourcc == pixelformat) {\n+\t\t\tif (formats[i].check_variants &&\n+\t\t\t    !check_mbus_format(dev, &formats[i]))\n+\t\t\t\tcontinue;\n+\t\t\treturn &formats[i];\n+\t\t}\n+\t}\n+\n+\treturn NULL;\n+}\n+\n+static inline unsigned int bytes_per_line(u32 width,\n+\t\t\t\t\t  const struct unicam_fmt *fmt,\n+\t\t\t\t\t  u32 v4l2_fourcc)\n+{\n+\tif (v4l2_fourcc == fmt->repacked_fourcc)\n+\t\t/* Repacking always goes to 16bpp */\n+\t\treturn ALIGN(width << 1, BPL_ALIGNMENT);\n+\telse\n+\t\treturn ALIGN((width * fmt->depth) >> 3, BPL_ALIGNMENT);\n+}\n+\n+static int __subdev_get_format(struct unicam_device *dev,\n+\t\t\t       struct v4l2_mbus_framefmt *fmt)\n+{\n+\tstruct v4l2_subdev_format sd_fmt = {\n+\t\t.which = V4L2_SUBDEV_FORMAT_ACTIVE,\n+\t};\n+\tint ret;\n+\n+\tret = v4l2_subdev_call(dev->sensor, pad, get_fmt, dev->sensor_config,\n+\t\t\t       &sd_fmt);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\t*fmt = sd_fmt.format;\n+\n+\tunicam_dbg(1, dev, \"%s %dx%d code:%04x\\n\", __func__,\n+\t\t   fmt->width, fmt->height, fmt->code);\n+\n+\treturn 0;\n+}\n+\n+static int __subdev_set_format(struct unicam_device *dev,\n+\t\t\t       struct v4l2_mbus_framefmt *fmt)\n+{\n+\tstruct v4l2_subdev_format sd_fmt = {\n+\t\t.which = V4L2_SUBDEV_FORMAT_ACTIVE,\n+\t};\n+\tint ret;\n+\n+\tsd_fmt.format = *fmt;\n+\n+\tret = v4l2_subdev_call(dev->sensor, pad, set_fmt, dev->sensor_config,\n+\t\t\t       &sd_fmt);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\tunicam_dbg(1, dev, \"%s %dx%d code:%04x\\n\", __func__,\n+\t\t   fmt->width, fmt->height, fmt->code);\n+\n+\treturn 0;\n+}\n+\n+static int unicam_calc_format_size_bpl(struct unicam_device *dev,\n+\t\t\t\t       const struct unicam_fmt *fmt,\n+\t\t\t\t       struct v4l2_format *f)\n+{\n+\tunsigned int min_bytesperline;\n+\n+\tv4l_bound_align_image(&f->fmt.pix.width, MIN_WIDTH, MAX_WIDTH, 2,\n+\t\t\t      &f->fmt.pix.height, MIN_HEIGHT, MAX_HEIGHT, 0,\n+\t\t\t      0);\n+\n+\tmin_bytesperline = bytes_per_line(f->fmt.pix.width, fmt,\n+\t\t\t\t\t  f->fmt.pix.pixelformat);\n+\n+\tif (f->fmt.pix.bytesperline > min_bytesperline &&\n+\t    f->fmt.pix.bytesperline <= MAX_BYTESPERLINE)\n+\t\tf->fmt.pix.bytesperline = ALIGN(f->fmt.pix.bytesperline,\n+\t\t\t\t\t\tBPL_ALIGNMENT);\n+\telse\n+\t\tf->fmt.pix.bytesperline = min_bytesperline;\n+\n+\tf->fmt.pix.sizeimage = f->fmt.pix.height * f->fmt.pix.bytesperline;\n+\n+\tunicam_dbg(3, dev, \"%s: fourcc: %08X size: %dx%d bpl:%d img_size:%d\\n\",\n+\t\t   __func__,\n+\t\t   f->fmt.pix.pixelformat,\n+\t\t   f->fmt.pix.width, f->fmt.pix.height,\n+\t\t   f->fmt.pix.bytesperline, f->fmt.pix.sizeimage);\n+\n+\treturn 0;\n+}\n+\n+static int unicam_reset_format(struct unicam_device *dev)\n+{\n+\tstruct v4l2_mbus_framefmt mbus_fmt;\n+\tint ret;\n+\n+\tret = __subdev_get_format(dev, &mbus_fmt);\n+\tif (ret) {\n+\t\tunicam_err(dev, \"Failed to get_format - ret %d\\n\", ret);\n+\t\treturn ret;\n+\t}\n+\n+\tif (mbus_fmt.code != dev->fmt->code) {\n+\t\tunicam_err(dev, \"code mismatch - fmt->code %08x, mbus_fmt.code %08x\\n\",\n+\t\t\t   dev->fmt->code, mbus_fmt.code);\n+\t\treturn ret;\n+\t}\n+\n+\tv4l2_fill_pix_format(&dev->v_fmt.fmt.pix, &mbus_fmt);\n+\tdev->v_fmt.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;\n+\n+\tunicam_calc_format_size_bpl(dev, dev->fmt, &dev->v_fmt);\n+\n+\tdev->m_fmt = mbus_fmt;\n+\n+\treturn 0;\n+}\n+\n+static void unicam_wr_dma_addr(struct unicam_device *dev, dma_addr_t dmaaddr)\n+{\n+\t/*\n+\t * dmaaddr should be a 32-bit address with the top two bits set to 0x3\n+\t * to signify uncached access through the Videocore memory controller.\n+\t */\n+\tBUG_ON((dmaaddr >> 30) != 0x3);\n+\n+\treg_write(&dev->cfg, UNICAM_IBSA0, dmaaddr);\n+\treg_write(&dev->cfg, UNICAM_IBEA0,\n+\t\t  dmaaddr + dev->v_fmt.fmt.pix.sizeimage);\n+}\n+\n+static inline unsigned int unicam_get_lines_done(struct unicam_device *dev)\n+{\n+\tdma_addr_t start_addr, cur_addr;\n+\tunsigned int stride = dev->v_fmt.fmt.pix.bytesperline;\n+\tstruct unicam_buffer *frm = dev->cur_frm;\n+\n+\tif (!frm)\n+\t\treturn 0;\n+\n+\tstart_addr = vb2_dma_contig_plane_dma_addr(&frm->vb.vb2_buf, 0);\n+\tcur_addr = reg_read(&dev->cfg, UNICAM_IBWP);\n+\treturn (unsigned int)(cur_addr - start_addr) / stride;\n+}\n+\n+static inline void unicam_schedule_next_buffer(struct unicam_device *dev)\n+{\n+\tstruct unicam_dmaqueue *dma_q = &dev->dma_queue;\n+\tstruct unicam_buffer *buf;\n+\tdma_addr_t addr;\n+\n+\tbuf = list_entry(dma_q->active.next, struct unicam_buffer, list);\n+\tdev->next_frm = buf;\n+\tlist_del(&buf->list);\n+\n+\taddr = vb2_dma_contig_plane_dma_addr(&buf->vb.vb2_buf, 0);\n+\tunicam_wr_dma_addr(dev, addr);\n+}\n+\n+static inline void unicam_process_buffer_complete(struct unicam_device *dev)\n+{\n+\tdev->cur_frm->vb.field = dev->m_fmt.field;\n+\tdev->cur_frm->vb.sequence = dev->sequence++;\n+\n+\tvb2_buffer_done(&dev->cur_frm->vb.vb2_buf, VB2_BUF_STATE_DONE);\n+\tdev->cur_frm = dev->next_frm;\n+}\n+\n+/*\n+ * unicam_isr : ISR handler for unicam capture\n+ * @irq: irq number\n+ * @dev_id: dev_id ptr\n+ *\n+ * It changes status of the captured buffer, takes next buffer from the queue\n+ * and sets its address in unicam registers\n+ */\n+static irqreturn_t unicam_isr(int irq, void *dev)\n+{\n+\tstruct unicam_device *unicam = (struct unicam_device *)dev;\n+\tstruct unicam_cfg *cfg = &unicam->cfg;\n+\tstruct unicam_dmaqueue *dma_q = &unicam->dma_queue;\n+\tunsigned int lines_done = unicam_get_lines_done(dev);\n+\tunsigned int sequence = unicam->sequence;\n+\tint ista, sta;\n+\n+\t/*\n+\t * Don't service interrupts if not streaming.\n+\t * Avoids issues if the VPU should enable the\n+\t * peripheral without the kernel knowing (that\n+\t * shouldn't happen, but causes issues if it does).\n+\t */\n+\tif (!unicam->streaming)\n+\t\treturn IRQ_HANDLED;\n+\n+\tsta = reg_read(cfg, UNICAM_STA);\n+\t/* Write value back to clear the interrupts */\n+\treg_write(cfg, UNICAM_STA, sta);\n+\n+\tista = reg_read(cfg, UNICAM_ISTA);\n+\t/* Write value back to clear the interrupts */\n+\treg_write(cfg, UNICAM_ISTA, ista);\n+\n+\tunicam_dbg(3, unicam, \"ISR: ISTA: 0x%X, STA: 0x%X, sequence %d, lines done %d\",\n+\t\t   ista, sta, sequence, lines_done);\n+\n+\tif (!(sta && (UNICAM_IS | UNICAM_PI0)))\n+\t\treturn IRQ_HANDLED;\n+\n+\tif (ista & UNICAM_FSI) {\n+\t\t/*\n+\t\t * Timestamp is to be when the first data byte was captured,\n+\t\t * aka frame start.\n+\t\t */\n+\t\tif (unicam->cur_frm)\n+\t\t\tunicam->cur_frm->vb.vb2_buf.timestamp = ktime_get_ns();\n+\t}\n+\tif (ista & UNICAM_FEI || sta & UNICAM_PI0) {\n+\t\t/*\n+\t\t * Ensure we have swapped buffers already as we can't\n+\t\t * stop the peripheral. Overwrite the frame we've just\n+\t\t * captured instead.\n+\t\t */\n+\t\tif (unicam->cur_frm && unicam->cur_frm != unicam->next_frm)\n+\t\t\tunicam_process_buffer_complete(unicam);\n+\t}\n+\n+\t/* Cannot swap buffer at frame end, there may be a race condition\n+\t * where the HW does not actually swap it if the new frame has\n+\t * already started.\n+\t */\n+\tif (ista & (UNICAM_FSI | UNICAM_LCI) && !(ista & UNICAM_FEI)) {\n+\t\tspin_lock(&unicam->dma_queue_lock);\n+\t\tif (!list_empty(&dma_q->active) &&\n+\t\t    unicam->cur_frm == unicam->next_frm)\n+\t\t\tunicam_schedule_next_buffer(unicam);\n+\t\tspin_unlock(&unicam->dma_queue_lock);\n+\t}\n+\n+\tif (reg_read(&unicam->cfg, UNICAM_ICTL) & UNICAM_FCM) {\n+\t\t/* Switch out of trigger mode if selected */\n+\t\treg_write_field(&unicam->cfg, UNICAM_ICTL, 1, UNICAM_TFC);\n+\t\treg_write_field(&unicam->cfg, UNICAM_ICTL, 0, UNICAM_FCM);\n+\t}\n+\treturn IRQ_HANDLED;\n+}\n+\n+static int unicam_querycap(struct file *file, void *priv,\n+\t\t\t   struct v4l2_capability *cap)\n+{\n+\tstruct unicam_device *dev = video_drvdata(file);\n+\n+\tstrlcpy(cap->driver, UNICAM_MODULE_NAME, sizeof(cap->driver));\n+\tstrlcpy(cap->card, UNICAM_MODULE_NAME, sizeof(cap->card));\n+\n+\tsnprintf(cap->bus_info, sizeof(cap->bus_info),\n+\t\t \"platform:%s\", dev->v4l2_dev.name);\n+\n+\treturn 0;\n+}\n+\n+static int unicam_enum_fmt_vid_cap(struct file *file, void  *priv,\n+\t\t\t\t   struct v4l2_fmtdesc *f)\n+{\n+\tstruct unicam_device *dev = video_drvdata(file);\n+\tstruct v4l2_subdev_mbus_code_enum mbus_code;\n+\tconst struct unicam_fmt *fmt = NULL;\n+\tint index = 0;\n+\tint ret = 0;\n+\tint i;\n+\n+\tfor (i = 0; !ret && i < MAX_ENUM_MBUS_CODE; i++) {\n+\t\tmemset(&mbus_code, 0, sizeof(mbus_code));\n+\t\tmbus_code.index = i;\n+\n+\t\tret = v4l2_subdev_call(dev->sensor, pad, enum_mbus_code,\n+\t\t\t\t       NULL, &mbus_code);\n+\t\tif (ret < 0) {\n+\t\t\tunicam_dbg(2, dev,\n+\t\t\t\t   \"subdev->enum_mbus_code idx %d returned %d - index invalid\\n\",\n+\t\t\t\t   i, ret);\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\n+\t\tfmt = find_format_by_code(mbus_code.code);\n+\t\tif (fmt) {\n+\t\t\tif (fmt->fourcc) {\n+\t\t\t\tif (index == f->index) {\n+\t\t\t\t\tf->pixelformat = fmt->fourcc;\n+\t\t\t\t\tbreak;\n+\t\t\t\t}\n+\t\t\t\tindex++;\n+\t\t\t}\n+\t\t\tif (fmt->repacked_fourcc) {\n+\t\t\t\tif (index == f->index) {\n+\t\t\t\t\tf->pixelformat = fmt->repacked_fourcc;\n+\t\t\t\t\tbreak;\n+\t\t\t\t}\n+\t\t\t\tindex++;\n+\t\t\t}\n+\t\t}\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int unicam_g_fmt_vid_cap(struct file *file, void *priv,\n+\t\t\t\tstruct v4l2_format *f)\n+{\n+\tstruct unicam_device *dev = video_drvdata(file);\n+\n+\t*f = dev->v_fmt;\n+\n+\treturn 0;\n+}\n+\n+static\n+const struct unicam_fmt *get_first_supported_format(struct unicam_device *dev)\n+{\n+\tstruct v4l2_subdev_mbus_code_enum mbus_code;\n+\tconst struct unicam_fmt *fmt = NULL;\n+\tint ret;\n+\tint j;\n+\n+\tfor (j = 0; ret != -EINVAL && ret != -ENOIOCTLCMD; ++j) {\n+\t\tmemset(&mbus_code, 0, sizeof(mbus_code));\n+\t\tmbus_code.index = j;\n+\t\tret = v4l2_subdev_call(dev->sensor, pad, enum_mbus_code, NULL,\n+\t\t\t\t       &mbus_code);\n+\t\tif (ret < 0) {\n+\t\t\tunicam_dbg(2, dev,\n+\t\t\t\t   \"subdev->enum_mbus_code idx %d returned %d - continue\\n\",\n+\t\t\t\t   j, ret);\n+\t\t\tcontinue;\n+\t\t}\n+\n+\t\tunicam_dbg(2, dev, \"subdev %s: code: 0x%08x idx: %d\\n\",\n+\t\t\t   dev->sensor->name, mbus_code.code, j);\n+\n+\t\tfmt = find_format_by_code(mbus_code.code);\n+\t\tunicam_dbg(2, dev, \"fmt 0x%08x returned as %p, V4L2 FOURCC 0x%08x, csi_dt 0x%02x\\n\",\n+\t\t\t   mbus_code.code, fmt, fmt ? fmt->fourcc : 0,\n+\t\t\t   fmt ? fmt->csi_dt : 0);\n+\t\tif (fmt)\n+\t\t\treturn fmt;\n+\t}\n+\n+\treturn NULL;\n+}\n+\n+static int unicam_try_fmt_vid_cap(struct file *file, void *priv,\n+\t\t\t\t  struct v4l2_format *f)\n+{\n+\tstruct unicam_device *dev = video_drvdata(file);\n+\tstruct v4l2_subdev_format sd_fmt = {\n+\t\t.which = V4L2_SUBDEV_FORMAT_TRY,\n+\t};\n+\tstruct v4l2_mbus_framefmt *mbus_fmt = &sd_fmt.format;\n+\tconst struct unicam_fmt *fmt;\n+\tint ret;\n+\n+\tfmt = find_format_by_pix(dev, f->fmt.pix.pixelformat);\n+\tif (!fmt) {\n+\t\t/* Pixel format not supported by unicam. Choose the first\n+\t\t * supported format, and let the sensor choose something else.\n+\t\t */\n+\t\tunicam_dbg(3, dev, \"Fourcc format (0x%08x) not found. Use first format.\\n\",\n+\t\t\t   f->fmt.pix.pixelformat);\n+\n+\t\tfmt = &formats[0];\n+\t\tf->fmt.pix.pixelformat = fmt->fourcc;\n+\t}\n+\n+\tv4l2_fill_mbus_format(mbus_fmt, &f->fmt.pix, fmt->code);\n+\t/*\n+\t * No support for receiving interlaced video, so never\n+\t * request it from the sensor subdev.\n+\t */\n+\tmbus_fmt->field = V4L2_FIELD_NONE;\n+\n+\tret = v4l2_subdev_call(dev->sensor, pad, set_fmt, dev->sensor_config,\n+\t\t\t       &sd_fmt);\n+\tif (ret && ret != -ENOIOCTLCMD && ret != -ENODEV)\n+\t\treturn ret;\n+\n+\tif (mbus_fmt->field != V4L2_FIELD_NONE)\n+\t\tunicam_info(dev, \"Sensor trying to send interlaced video - results may be unpredictable\\n\");\n+\n+\tv4l2_fill_pix_format(&f->fmt.pix, &sd_fmt.format);\n+\tif (mbus_fmt->code != fmt->code) {\n+\t\t/* Sensor has returned an alternate format */\n+\t\tfmt = find_format_by_code(mbus_fmt->code);\n+\t\tif (!fmt) {\n+\t\t\t/* The alternate format is one unicam can't support.\n+\t\t\t * Find the first format that is supported by both, and\n+\t\t\t * then set that.\n+\t\t\t */\n+\t\t\tfmt = get_first_supported_format(dev);\n+\t\t\tmbus_fmt->code = fmt->code;\n+\n+\t\t\tret = v4l2_subdev_call(dev->sensor, pad, set_fmt,\n+\t\t\t\t\t       dev->sensor_config, &sd_fmt);\n+\t\t\tif (ret && ret != -ENOIOCTLCMD && ret != -ENODEV)\n+\t\t\t\treturn ret;\n+\n+\t\t\tif (mbus_fmt->field != V4L2_FIELD_NONE)\n+\t\t\t\tunicam_info(dev, \"Sensor trying to send interlaced video - results may be unpredictable\\n\");\n+\n+\t\t\tv4l2_fill_pix_format(&f->fmt.pix, &sd_fmt.format);\n+\n+\t\t\tif (mbus_fmt->code != fmt->code) {\n+\t\t\t\t/* We've set a format that the sensor reports\n+\t\t\t\t * as being supported, but it refuses to set it.\n+\t\t\t\t * Not much else we can do.\n+\t\t\t\t * Assume that the sensor driver may accept the\n+\t\t\t\t * format when it is set (rather than tried).\n+\t\t\t\t */\n+\t\t\t\tunicam_err(dev, \"Sensor won't accept default format, and Unicam can't support sensor default\\n\");\n+\t\t\t}\n+\t\t}\n+\n+\t\tif (fmt->fourcc)\n+\t\t\tf->fmt.pix.pixelformat = fmt->fourcc;\n+\t\telse\n+\t\t\tf->fmt.pix.pixelformat = fmt->repacked_fourcc;\n+\t}\n+\n+\treturn unicam_calc_format_size_bpl(dev, fmt, f);\n+}\n+\n+static int unicam_s_fmt_vid_cap(struct file *file, void *priv,\n+\t\t\t\tstruct v4l2_format *f)\n+{\n+\tstruct unicam_device *dev = video_drvdata(file);\n+\tstruct vb2_queue *q = &dev->buffer_queue;\n+\tstruct v4l2_mbus_framefmt mbus_fmt = {0};\n+\tconst struct unicam_fmt *fmt;\n+\tint ret;\n+\n+\tif (vb2_is_busy(q))\n+\t\treturn -EBUSY;\n+\n+\tret = unicam_try_fmt_vid_cap(file, priv, f);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\tfmt = find_format_by_pix(dev, f->fmt.pix.pixelformat);\n+\tif (!fmt) {\n+\t\t/* Unknown pixel format - adopt a default.\n+\t\t * This shouldn't happen as try_fmt should have resolved any\n+\t\t * issues first.\n+\t\t */\n+\t\tfmt = get_first_supported_format(dev);\n+\t\tif (!fmt)\n+\t\t\t/* It shouldn't be possible to get here with no\n+\t\t\t * supported formats\n+\t\t\t */\n+\t\t\treturn -EINVAL;\n+\t\tf->fmt.pix.pixelformat = fmt->fourcc;\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tv4l2_fill_mbus_format(&mbus_fmt, &f->fmt.pix, fmt->code);\n+\n+\tret = __subdev_set_format(dev, &mbus_fmt);\n+\tif (ret) {\n+\t\tunicam_dbg(3, dev, \"%s __subdev_set_format failed %d\\n\",\n+\t\t\t   __func__, ret);\n+\t\treturn ret;\n+\t}\n+\n+\t/* Just double check nothing has gone wrong */\n+\tif (mbus_fmt.code != fmt->code) {\n+\t\tunicam_dbg(3, dev,\n+\t\t\t   \"%s subdev changed format on us, this should not happen\\n\",\n+\t\t\t   __func__);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tdev->fmt = fmt;\n+\tdev->v_fmt.fmt.pix.pixelformat = f->fmt.pix.pixelformat;\n+\tdev->v_fmt.fmt.pix.bytesperline = f->fmt.pix.bytesperline;\n+\tunicam_reset_format(dev);\n+\n+\tunicam_dbg(3, dev, \"%s %dx%d, mbus_fmt 0x%08X, V4L2 pix 0x%08X.\\n\",\n+\t\t   __func__, dev->v_fmt.fmt.pix.width,\n+\t\t   dev->v_fmt.fmt.pix.height, mbus_fmt.code,\n+\t\t   dev->v_fmt.fmt.pix.pixelformat);\n+\n+\t*f = dev->v_fmt;\n+\n+\treturn 0;\n+}\n+\n+static int unicam_queue_setup(struct vb2_queue *vq,\n+\t\t\t      unsigned int *nbuffers,\n+\t\t\t      unsigned int *nplanes,\n+\t\t\t      unsigned int sizes[],\n+\t\t\t      struct device *alloc_devs[])\n+{\n+\tstruct unicam_device *dev = vb2_get_drv_priv(vq);\n+\tunsigned int size = dev->v_fmt.fmt.pix.sizeimage;\n+\n+\tif (vq->num_buffers + *nbuffers < 3)\n+\t\t*nbuffers = 3 - vq->num_buffers;\n+\n+\tif (*nplanes) {\n+\t\tif (sizes[0] < size) {\n+\t\t\tunicam_err(dev, \"sizes[0] %i < size %u\\n\", sizes[0],\n+\t\t\t\t   size);\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t\tsize = sizes[0];\n+\t}\n+\n+\t*nplanes = 1;\n+\tsizes[0] = size;\n+\n+\treturn 0;\n+}\n+\n+static int unicam_buffer_prepare(struct vb2_buffer *vb)\n+{\n+\tstruct unicam_device *dev = vb2_get_drv_priv(vb->vb2_queue);\n+\tstruct unicam_buffer *buf = container_of(vb, struct unicam_buffer,\n+\t\t\t\t\t      vb.vb2_buf);\n+\tunsigned long size;\n+\n+\tif (WARN_ON(!dev->fmt))\n+\t\treturn -EINVAL;\n+\n+\tsize = dev->v_fmt.fmt.pix.sizeimage;\n+\tif (vb2_plane_size(vb, 0) < size) {\n+\t\tunicam_err(dev, \"data will not fit into plane (%lu < %lu)\\n\",\n+\t\t\t   vb2_plane_size(vb, 0), size);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tvb2_set_plane_payload(&buf->vb.vb2_buf, 0, size);\n+\treturn 0;\n+}\n+\n+static void unicam_buffer_queue(struct vb2_buffer *vb)\n+{\n+\tstruct unicam_device *dev = vb2_get_drv_priv(vb->vb2_queue);\n+\tstruct unicam_buffer *buf = container_of(vb, struct unicam_buffer,\n+\t\t\t\t\t      vb.vb2_buf);\n+\tstruct unicam_dmaqueue *dma_queue = &dev->dma_queue;\n+\tunsigned long flags = 0;\n+\n+\tspin_lock_irqsave(&dev->dma_queue_lock, flags);\n+\tlist_add_tail(&buf->list, &dma_queue->active);\n+\tspin_unlock_irqrestore(&dev->dma_queue_lock, flags);\n+}\n+\n+static void unicam_set_packing_config(struct unicam_device *dev)\n+{\n+\tint pack, unpack;\n+\tu32 val;\n+\n+\tif (dev->v_fmt.fmt.pix.pixelformat == dev->fmt->fourcc) {\n+\t\tunpack = UNICAM_PUM_NONE;\n+\t\tpack = UNICAM_PPM_NONE;\n+\t} else {\n+\t\tswitch (dev->fmt->depth) {\n+\t\tcase 8:\n+\t\t\tunpack = UNICAM_PUM_UNPACK8;\n+\t\t\tbreak;\n+\t\tcase 10:\n+\t\t\tunpack = UNICAM_PUM_UNPACK10;\n+\t\t\tbreak;\n+\t\tcase 12:\n+\t\t\tunpack = UNICAM_PUM_UNPACK12;\n+\t\t\tbreak;\n+\t\tcase 14:\n+\t\t\tunpack = UNICAM_PUM_UNPACK14;\n+\t\t\tbreak;\n+\t\tcase 16:\n+\t\t\tunpack = UNICAM_PUM_UNPACK16;\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tunpack = UNICAM_PUM_NONE;\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\t/* Repacking is always to 16bpp */\n+\t\tpack = UNICAM_PPM_PACK16;\n+\t}\n+\n+\tval = 0;\n+\tset_field(&val, unpack, UNICAM_PUM_MASK);\n+\tset_field(&val, pack, UNICAM_PPM_MASK);\n+\treg_write(&dev->cfg, UNICAM_IPIPE, val);\n+}\n+\n+static void unicam_cfg_image_id(struct unicam_device *dev)\n+{\n+\tstruct unicam_cfg *cfg = &dev->cfg;\n+\n+\tif (dev->bus_type == V4L2_MBUS_CSI2_DPHY) {\n+\t\t/* CSI2 mode */\n+\t\treg_write(cfg, UNICAM_IDI0,\n+\t\t\t  (dev->virtual_channel << 6) | dev->fmt->csi_dt);\n+\t} else {\n+\t\t/* CCP2 mode */\n+\t\treg_write(cfg, UNICAM_IDI0, (0x80 | dev->fmt->csi_dt));\n+\t}\n+}\n+\n+static void unicam_start_rx(struct unicam_device *dev, unsigned long addr)\n+{\n+\tstruct unicam_cfg *cfg = &dev->cfg;\n+\tint line_int_freq = dev->v_fmt.fmt.pix.height >> 2;\n+\tunsigned int i;\n+\tu32 val;\n+\n+\tif (line_int_freq < 128)\n+\t\tline_int_freq = 128;\n+\n+\t/* Enable lane clocks */\n+\tval = 1;\n+\tfor (i = 0; i < dev->active_data_lanes; i++)\n+\t\tval = val << 2 | 1;\n+\tclk_write(cfg, val);\n+\n+\t/* Basic init */\n+\treg_write(cfg, UNICAM_CTRL, UNICAM_MEM);\n+\n+\t/* Enable analogue control, and leave in reset. */\n+\tval = UNICAM_AR;\n+\tset_field(&val, 7, UNICAM_CTATADJ_MASK);\n+\tset_field(&val, 7, UNICAM_PTATADJ_MASK);\n+\treg_write(cfg, UNICAM_ANA, val);\n+\tusleep_range(1000, 2000);\n+\n+\t/* Come out of reset */\n+\treg_write_field(cfg, UNICAM_ANA, 0, UNICAM_AR);\n+\n+\t/* Peripheral reset */\n+\treg_write_field(cfg, UNICAM_CTRL, 1, UNICAM_CPR);\n+\treg_write_field(cfg, UNICAM_CTRL, 0, UNICAM_CPR);\n+\n+\treg_write_field(cfg, UNICAM_CTRL, 0, UNICAM_CPE);\n+\n+\t/* Enable Rx control. */\n+\tval = reg_read(cfg, UNICAM_CTRL);\n+\tif (dev->bus_type == V4L2_MBUS_CSI2_DPHY) {\n+\t\tset_field(&val, UNICAM_CPM_CSI2, UNICAM_CPM_MASK);\n+\t\tset_field(&val, UNICAM_DCM_STROBE, UNICAM_DCM_MASK);\n+\t} else {\n+\t\tset_field(&val, UNICAM_CPM_CCP2, UNICAM_CPM_MASK);\n+\t\tset_field(&val, dev->bus_flags, UNICAM_DCM_MASK);\n+\t}\n+\t/* Packet framer timeout */\n+\tset_field(&val, 0xf, UNICAM_PFT_MASK);\n+\tset_field(&val, 128, UNICAM_OET_MASK);\n+\treg_write(cfg, UNICAM_CTRL, val);\n+\n+\treg_write(cfg, UNICAM_IHWIN, 0);\n+\treg_write(cfg, UNICAM_IVWIN, 0);\n+\n+\t/* AXI bus access QoS setup */\n+\tval = reg_read(&dev->cfg, UNICAM_PRI);\n+\tset_field(&val, 0, UNICAM_BL_MASK);\n+\tset_field(&val, 0, UNICAM_BS_MASK);\n+\tset_field(&val, 0xe, UNICAM_PP_MASK);\n+\tset_field(&val, 8, UNICAM_NP_MASK);\n+\tset_field(&val, 2, UNICAM_PT_MASK);\n+\tset_field(&val, 1, UNICAM_PE);\n+\treg_write(cfg, UNICAM_PRI, val);\n+\n+\treg_write_field(cfg, UNICAM_ANA, 0, UNICAM_DDL);\n+\n+\t/* Always start in trigger frame capture mode (UNICAM_FCM set) */\n+\tval = UNICAM_FSIE | UNICAM_FEIE | UNICAM_FCM;\n+\tset_field(&val,  line_int_freq, UNICAM_LCIE_MASK);\n+\treg_write(cfg, UNICAM_ICTL, val);\n+\treg_write(cfg, UNICAM_STA, UNICAM_STA_MASK_ALL);\n+\treg_write(cfg, UNICAM_ISTA, UNICAM_ISTA_MASK_ALL);\n+\n+\t/* tclk_term_en */\n+\treg_write_field(cfg, UNICAM_CLT, 2, UNICAM_CLT1_MASK);\n+\t/* tclk_settle */\n+\treg_write_field(cfg, UNICAM_CLT, 6, UNICAM_CLT2_MASK);\n+\t/* td_term_en */\n+\treg_write_field(cfg, UNICAM_DLT, 2, UNICAM_DLT1_MASK);\n+\t/* ths_settle */\n+\treg_write_field(cfg, UNICAM_DLT, 6, UNICAM_DLT2_MASK);\n+\t/* trx_enable */\n+\treg_write_field(cfg, UNICAM_DLT, 0, UNICAM_DLT3_MASK);\n+\n+\treg_write_field(cfg, UNICAM_CTRL, 0, UNICAM_SOE);\n+\n+\t/* Packet compare setup - required to avoid missing frame ends */\n+\tval = 0;\n+\tset_field(&val, 1, UNICAM_PCE);\n+\tset_field(&val, 1, UNICAM_GI);\n+\tset_field(&val, 1, UNICAM_CPH);\n+\tset_field(&val, 0, UNICAM_PCVC_MASK);\n+\tset_field(&val, 1, UNICAM_PCDT_MASK);\n+\treg_write(cfg, UNICAM_CMP0, val);\n+\n+\t/* Enable clock lane and set up terminations */\n+\tval = 0;\n+\tif (dev->bus_type == V4L2_MBUS_CSI2_DPHY) {\n+\t\t/* CSI2 */\n+\t\tset_field(&val, 1, UNICAM_CLE);\n+\t\tset_field(&val, 1, UNICAM_CLLPE);\n+\t\tif (dev->bus_flags & V4L2_MBUS_CSI2_CONTINUOUS_CLOCK) {\n+\t\t\tset_field(&val, 1, UNICAM_CLTRE);\n+\t\t\tset_field(&val, 1, UNICAM_CLHSE);\n+\t\t}\n+\t} else {\n+\t\t/* CCP2 */\n+\t\tset_field(&val, 1, UNICAM_CLE);\n+\t\tset_field(&val, 1, UNICAM_CLHSE);\n+\t\tset_field(&val, 1, UNICAM_CLTRE);\n+\t}\n+\treg_write(cfg, UNICAM_CLK, val);\n+\n+\t/*\n+\t * Enable required data lanes with appropriate terminations.\n+\t * The same value needs to be written to UNICAM_DATn registers for\n+\t * the active lanes, and 0 for inactive ones.\n+\t */\n+\tval = 0;\n+\tif (dev->bus_type == V4L2_MBUS_CSI2_DPHY) {\n+\t\t/* CSI2 */\n+\t\tset_field(&val, 1, UNICAM_DLE);\n+\t\tset_field(&val, 1, UNICAM_DLLPE);\n+\t\tif (dev->bus_flags & V4L2_MBUS_CSI2_CONTINUOUS_CLOCK) {\n+\t\t\tset_field(&val, 1, UNICAM_DLTRE);\n+\t\t\tset_field(&val, 1, UNICAM_DLHSE);\n+\t\t}\n+\t} else {\n+\t\t/* CCP2 */\n+\t\tset_field(&val, 1, UNICAM_DLE);\n+\t\tset_field(&val, 1, UNICAM_DLHSE);\n+\t\tset_field(&val, 1, UNICAM_DLTRE);\n+\t}\n+\treg_write(cfg, UNICAM_DAT0, val);\n+\n+\tif (dev->active_data_lanes == 1)\n+\t\tval = 0;\n+\treg_write(cfg, UNICAM_DAT1, val);\n+\n+\tif (dev->max_data_lanes > 2) {\n+\t\t/*\n+\t\t * Registers UNICAM_DAT2 and UNICAM_DAT3 only valid if the\n+\t\t * instance supports more than 2 data lanes.\n+\t\t */\n+\t\tif (dev->active_data_lanes == 2)\n+\t\t\tval = 0;\n+\t\treg_write(cfg, UNICAM_DAT2, val);\n+\n+\t\tif (dev->active_data_lanes == 3)\n+\t\t\tval = 0;\n+\t\treg_write(cfg, UNICAM_DAT3, val);\n+\t}\n+\n+\treg_write(&dev->cfg, UNICAM_IBLS, dev->v_fmt.fmt.pix.bytesperline);\n+\tunicam_wr_dma_addr(dev, addr);\n+\tunicam_set_packing_config(dev);\n+\tunicam_cfg_image_id(dev);\n+\n+\t/* Disabled embedded data */\n+\tval = 0;\n+\tset_field(&val, 0, UNICAM_EDL_MASK);\n+\treg_write(cfg, UNICAM_DCS, val);\n+\n+\tval = reg_read(cfg, UNICAM_MISC);\n+\tset_field(&val, 1, UNICAM_FL0);\n+\tset_field(&val, 1, UNICAM_FL1);\n+\treg_write(cfg, UNICAM_MISC, val);\n+\n+\t/* Enable peripheral */\n+\treg_write_field(cfg, UNICAM_CTRL, 1, UNICAM_CPE);\n+\n+\t/* Load image pointers */\n+\treg_write_field(cfg, UNICAM_ICTL, 1, UNICAM_LIP_MASK);\n+\n+\t/*\n+\t * Enable trigger only for the first frame to\n+\t * sync correctly to the FS from the source.\n+\t */\n+\treg_write_field(cfg, UNICAM_ICTL, 1, UNICAM_TFC);\n+}\n+\n+static void unicam_disable(struct unicam_device *dev)\n+{\n+\tstruct unicam_cfg *cfg = &dev->cfg;\n+\n+\t/* Analogue lane control disable */\n+\treg_write_field(cfg, UNICAM_ANA, 1, UNICAM_DDL);\n+\n+\t/* Stop the output engine */\n+\treg_write_field(cfg, UNICAM_CTRL, 1, UNICAM_SOE);\n+\n+\t/* Disable the data lanes. */\n+\treg_write(cfg, UNICAM_DAT0, 0);\n+\treg_write(cfg, UNICAM_DAT1, 0);\n+\n+\tif (dev->max_data_lanes > 2) {\n+\t\treg_write(cfg, UNICAM_DAT2, 0);\n+\t\treg_write(cfg, UNICAM_DAT3, 0);\n+\t}\n+\n+\t/* Peripheral reset */\n+\treg_write_field(cfg, UNICAM_CTRL, 1, UNICAM_CPR);\n+\tusleep_range(50, 100);\n+\treg_write_field(cfg, UNICAM_CTRL, 0, UNICAM_CPR);\n+\n+\t/* Disable peripheral */\n+\treg_write_field(cfg, UNICAM_CTRL, 0, UNICAM_CPE);\n+\n+\t/* Disable all lane clocks */\n+\tclk_write(cfg, 0);\n+}\n+\n+static int unicam_start_streaming(struct vb2_queue *vq, unsigned int count)\n+{\n+\tstruct unicam_device *dev = vb2_get_drv_priv(vq);\n+\tstruct unicam_dmaqueue *dma_q = &dev->dma_queue;\n+\tstruct unicam_buffer *buf, *tmp;\n+\tunsigned long addr = 0;\n+\tunsigned long flags;\n+\tint ret;\n+\n+\tspin_lock_irqsave(&dev->dma_queue_lock, flags);\n+\tbuf = list_entry(dma_q->active.next, struct unicam_buffer, list);\n+\tdev->cur_frm = buf;\n+\tdev->next_frm = buf;\n+\tlist_del(&buf->list);\n+\tspin_unlock_irqrestore(&dev->dma_queue_lock, flags);\n+\n+\taddr = vb2_dma_contig_plane_dma_addr(&dev->cur_frm->vb.vb2_buf, 0);\n+\tdev->sequence = 0;\n+\n+\tret = unicam_runtime_get(dev);\n+\tif (ret < 0) {\n+\t\tunicam_dbg(3, dev, \"unicam_runtime_get failed\\n\");\n+\t\tgoto err_release_buffers;\n+\t}\n+\n+\tdev->active_data_lanes = dev->max_data_lanes;\n+\tif (dev->bus_type == V4L2_MBUS_CSI2_DPHY &&\n+\t    v4l2_subdev_has_op(dev->sensor, video, g_mbus_config)) {\n+\t\tstruct v4l2_mbus_config mbus_config;\n+\n+\t\tret = v4l2_subdev_call(dev->sensor, video, g_mbus_config,\n+\t\t\t\t       &mbus_config);\n+\t\tif (ret < 0) {\n+\t\t\tunicam_dbg(3, dev, \"g_mbus_config failed\\n\");\n+\t\t\tgoto err_pm_put;\n+\t\t}\n+\n+\t\tdev->active_data_lanes =\n+\t\t\t(mbus_config.flags & V4L2_MBUS_CSI2_LANE_MASK) >>\n+\t\t\t\t\t__ffs(V4L2_MBUS_CSI2_LANE_MASK);\n+\t\tif (!dev->active_data_lanes)\n+\t\t\tdev->active_data_lanes = dev->max_data_lanes;\n+\t}\n+\tif (dev->active_data_lanes > dev->max_data_lanes) {\n+\t\tunicam_err(dev, \"Device has requested %u data lanes, which is >%u configured in DT\\n\",\n+\t\t\t   dev->active_data_lanes, dev->max_data_lanes);\n+\t\tret = -EINVAL;\n+\t\tgoto err_pm_put;\n+\t}\n+\n+\tunicam_dbg(1, dev, \"Running with %u data lanes\\n\",\n+\t\t   dev->active_data_lanes);\n+\n+\tret = clk_set_rate(dev->clock, 100 * 1000 * 1000);\n+\tif (ret) {\n+\t\tunicam_err(dev, \"failed to set up clock\\n\");\n+\t\tgoto err_pm_put;\n+\t}\n+\n+\tret = clk_prepare_enable(dev->clock);\n+\tif (ret) {\n+\t\tunicam_err(dev, \"Failed to enable CSI clock: %d\\n\", ret);\n+\t\tgoto err_pm_put;\n+\t}\n+\tdev->streaming = 1;\n+\n+\tunicam_start_rx(dev, addr);\n+\n+\tret = v4l2_subdev_call(dev->sensor, video, s_stream, 1);\n+\tif (ret < 0) {\n+\t\tunicam_err(dev, \"stream on failed in subdev\\n\");\n+\t\tgoto err_disable_unicam;\n+\t}\n+\n+\treturn 0;\n+\n+err_disable_unicam:\n+\tunicam_disable(dev);\n+\tclk_disable_unprepare(dev->clock);\n+err_pm_put:\n+\tunicam_runtime_put(dev);\n+err_release_buffers:\n+\tlist_for_each_entry_safe(buf, tmp, &dma_q->active, list) {\n+\t\tlist_del(&buf->list);\n+\t\tvb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_QUEUED);\n+\t}\n+\tif (dev->cur_frm != dev->next_frm)\n+\t\tvb2_buffer_done(&dev->next_frm->vb.vb2_buf,\n+\t\t\t\tVB2_BUF_STATE_QUEUED);\n+\tvb2_buffer_done(&dev->cur_frm->vb.vb2_buf, VB2_BUF_STATE_QUEUED);\n+\tdev->next_frm = NULL;\n+\tdev->cur_frm = NULL;\n+\n+\treturn ret;\n+}\n+\n+static void unicam_stop_streaming(struct vb2_queue *vq)\n+{\n+\tstruct unicam_device *dev = vb2_get_drv_priv(vq);\n+\tstruct unicam_dmaqueue *dma_q = &dev->dma_queue;\n+\tstruct unicam_buffer *buf, *tmp;\n+\tunsigned long flags;\n+\n+\tif (v4l2_subdev_call(dev->sensor, video, s_stream, 0) < 0)\n+\t\tunicam_err(dev, \"stream off failed in subdev\\n\");\n+\n+\tunicam_disable(dev);\n+\n+\t/* Release all active buffers */\n+\tspin_lock_irqsave(&dev->dma_queue_lock, flags);\n+\tlist_for_each_entry_safe(buf, tmp, &dma_q->active, list) {\n+\t\tlist_del(&buf->list);\n+\t\tvb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);\n+\t}\n+\n+\tif (dev->cur_frm == dev->next_frm) {\n+\t\tvb2_buffer_done(&dev->cur_frm->vb.vb2_buf, VB2_BUF_STATE_ERROR);\n+\t} else {\n+\t\tvb2_buffer_done(&dev->cur_frm->vb.vb2_buf, VB2_BUF_STATE_ERROR);\n+\t\tvb2_buffer_done(&dev->next_frm->vb.vb2_buf,\n+\t\t\t\tVB2_BUF_STATE_ERROR);\n+\t}\n+\tdev->cur_frm = NULL;\n+\tdev->next_frm = NULL;\n+\tspin_unlock_irqrestore(&dev->dma_queue_lock, flags);\n+\n+\tclk_disable_unprepare(dev->clock);\n+\tunicam_runtime_put(dev);\n+}\n+\n+static int unicam_enum_input(struct file *file, void *priv,\n+\t\t\t     struct v4l2_input *inp)\n+{\n+\tstruct unicam_device *dev = video_drvdata(file);\n+\n+\tif (inp->index != 0)\n+\t\treturn -EINVAL;\n+\n+\tinp->type = V4L2_INPUT_TYPE_CAMERA;\n+\tif (v4l2_subdev_has_op(dev->sensor, video, s_dv_timings)) {\n+\t\tinp->capabilities = V4L2_IN_CAP_DV_TIMINGS;\n+\t\tinp->std = 0;\n+\t} else if (v4l2_subdev_has_op(dev->sensor, video, s_std)) {\n+\t\tinp->capabilities = V4L2_IN_CAP_STD;\n+\t\tif (v4l2_subdev_call(dev->sensor, video, g_tvnorms, &inp->std)\n+\t\t\t\t\t< 0)\n+\t\t\tinp->std = V4L2_STD_ALL;\n+\t} else {\n+\t\tinp->capabilities = 0;\n+\t\tinp->std = 0;\n+\t}\n+\tsprintf(inp->name, \"Camera 0\");\n+\treturn 0;\n+}\n+\n+static int unicam_g_input(struct file *file, void *priv, unsigned int *i)\n+{\n+\t*i = 0;\n+\n+\treturn 0;\n+}\n+\n+static int unicam_s_input(struct file *file, void *priv, unsigned int i)\n+{\n+\t/*\n+\t * FIXME: Ideally we would like to be able to query the source\n+\t * subdevice for information over the input connectors it supports,\n+\t * and map that through in to a call to video_ops->s_routing.\n+\t * There is no infrastructure support for defining that within\n+\t * devicetree at present. Until that is implemented we can't\n+\t * map a user physical connector number to s_routing input number.\n+\t */\n+\tif (i > 0)\n+\t\treturn -EINVAL;\n+\n+\treturn 0;\n+}\n+\n+static int unicam_querystd(struct file *file, void *priv,\n+\t\t\t   v4l2_std_id *std)\n+{\n+\tstruct unicam_device *dev = video_drvdata(file);\n+\n+\treturn v4l2_subdev_call(dev->sensor, video, querystd, std);\n+}\n+\n+static int unicam_g_std(struct file *file, void *priv, v4l2_std_id *std)\n+{\n+\tstruct unicam_device *dev = video_drvdata(file);\n+\n+\treturn v4l2_subdev_call(dev->sensor, video, g_std, std);\n+}\n+\n+static int unicam_s_std(struct file *file, void *priv, v4l2_std_id std)\n+{\n+\tstruct unicam_device *dev = video_drvdata(file);\n+\tint ret;\n+\tv4l2_std_id current_std;\n+\n+\tret = v4l2_subdev_call(dev->sensor, video, g_std, &current_std);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tif (std == current_std)\n+\t\treturn 0;\n+\n+\tif (vb2_is_busy(&dev->buffer_queue))\n+\t\treturn -EBUSY;\n+\n+\tret = v4l2_subdev_call(dev->sensor, video, s_std, std);\n+\n+\t/* Force recomputation of bytesperline */\n+\tdev->v_fmt.fmt.pix.bytesperline = 0;\n+\n+\tunicam_reset_format(dev);\n+\n+\treturn ret;\n+}\n+\n+static int unicam_s_edid(struct file *file, void *priv, struct v4l2_edid *edid)\n+{\n+\tstruct unicam_device *dev = video_drvdata(file);\n+\n+\treturn v4l2_subdev_call(dev->sensor, pad, set_edid, edid);\n+}\n+\n+static int unicam_g_edid(struct file *file, void *priv, struct v4l2_edid *edid)\n+{\n+\tstruct unicam_device *dev = video_drvdata(file);\n+\n+\treturn v4l2_subdev_call(dev->sensor, pad, get_edid, edid);\n+}\n+\n+static int unicam_enum_framesizes(struct file *file, void *priv,\n+\t\t\t\t  struct v4l2_frmsizeenum *fsize)\n+{\n+\tstruct unicam_device *dev = video_drvdata(file);\n+\tconst struct unicam_fmt *fmt;\n+\tstruct v4l2_subdev_frame_size_enum fse;\n+\tint ret;\n+\n+\t/* check for valid format */\n+\tfmt = find_format_by_pix(dev, fsize->pixel_format);\n+\tif (!fmt) {\n+\t\tunicam_dbg(3, dev, \"Invalid pixel code: %x\\n\",\n+\t\t\t   fsize->pixel_format);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tfse.index = fsize->index;\n+\tfse.pad = 0;\n+\tfse.code = fmt->code;\n+\n+\tret = v4l2_subdev_call(dev->sensor, pad, enum_frame_size, NULL, &fse);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tunicam_dbg(1, dev, \"%s: index: %d code: %x W:[%d,%d] H:[%d,%d]\\n\",\n+\t\t   __func__, fse.index, fse.code, fse.min_width, fse.max_width,\n+\t\t   fse.min_height, fse.max_height);\n+\n+\tfsize->type = V4L2_FRMSIZE_TYPE_DISCRETE;\n+\tfsize->discrete.width = fse.max_width;\n+\tfsize->discrete.height = fse.max_height;\n+\n+\treturn 0;\n+}\n+\n+static int unicam_enum_frameintervals(struct file *file, void *priv,\n+\t\t\t\t      struct v4l2_frmivalenum *fival)\n+{\n+\tstruct unicam_device *dev = video_drvdata(file);\n+\tconst struct unicam_fmt *fmt;\n+\tstruct v4l2_subdev_frame_interval_enum fie = {\n+\t\t.index = fival->index,\n+\t\t.width = fival->width,\n+\t\t.height = fival->height,\n+\t\t.which = V4L2_SUBDEV_FORMAT_ACTIVE,\n+\t};\n+\tint ret;\n+\n+\tfmt = find_format_by_pix(dev, fival->pixel_format);\n+\tif (!fmt)\n+\t\treturn -EINVAL;\n+\n+\tfie.code = fmt->code;\n+\tret = v4l2_subdev_call(dev->sensor, pad, enum_frame_interval,\n+\t\t\t       NULL, &fie);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tfival->type = V4L2_FRMIVAL_TYPE_DISCRETE;\n+\tfival->discrete = fie.interval;\n+\n+\treturn 0;\n+}\n+\n+static int unicam_g_parm(struct file *file, void *fh, struct v4l2_streamparm *a)\n+{\n+\tstruct unicam_device *dev = video_drvdata(file);\n+\n+\treturn v4l2_g_parm_cap(video_devdata(file), dev->sensor, a);\n+}\n+\n+static int unicam_s_parm(struct file *file, void *fh, struct v4l2_streamparm *a)\n+{\n+\tstruct unicam_device *dev = video_drvdata(file);\n+\n+\treturn v4l2_s_parm_cap(video_devdata(file), dev->sensor, a);\n+}\n+\n+static int unicam_g_dv_timings(struct file *file, void *priv,\n+\t\t\t       struct v4l2_dv_timings *timings)\n+{\n+\tstruct unicam_device *dev = video_drvdata(file);\n+\n+\treturn v4l2_subdev_call(dev->sensor, video, g_dv_timings, timings);\n+}\n+\n+static int unicam_s_dv_timings(struct file *file, void *priv,\n+\t\t\t       struct v4l2_dv_timings *timings)\n+{\n+\tstruct unicam_device *dev = video_drvdata(file);\n+\tstruct v4l2_dv_timings current_timings;\n+\tint ret;\n+\n+\tret = v4l2_subdev_call(dev->sensor, video, g_dv_timings,\n+\t\t\t       &current_timings);\n+\n+\tif (v4l2_match_dv_timings(timings, &current_timings, 0, false))\n+\t\treturn 0;\n+\n+\tif (vb2_is_busy(&dev->buffer_queue))\n+\t\treturn -EBUSY;\n+\n+\tret = v4l2_subdev_call(dev->sensor, video, s_dv_timings, timings);\n+\n+\t/* Force recomputation of bytesperline */\n+\tdev->v_fmt.fmt.pix.bytesperline = 0;\n+\n+\tunicam_reset_format(dev);\n+\n+\treturn ret;\n+}\n+\n+static int unicam_query_dv_timings(struct file *file, void *priv,\n+\t\t\t\t   struct v4l2_dv_timings *timings)\n+{\n+\tstruct unicam_device *dev = video_drvdata(file);\n+\n+\treturn v4l2_subdev_call(dev->sensor, video, query_dv_timings, timings);\n+}\n+\n+static int unicam_enum_dv_timings(struct file *file, void *priv,\n+\t\t\t\t  struct v4l2_enum_dv_timings *timings)\n+{\n+\tstruct unicam_device *dev = video_drvdata(file);\n+\n+\treturn v4l2_subdev_call(dev->sensor, pad, enum_dv_timings, timings);\n+}\n+\n+static int unicam_dv_timings_cap(struct file *file, void *priv,\n+\t\t\t\t struct v4l2_dv_timings_cap *cap)\n+{\n+\tstruct unicam_device *dev = video_drvdata(file);\n+\n+\treturn v4l2_subdev_call(dev->sensor, pad, dv_timings_cap, cap);\n+}\n+\n+static int unicam_subscribe_event(struct v4l2_fh *fh,\n+\t\t\t\t  const struct v4l2_event_subscription *sub)\n+{\n+\tswitch (sub->type) {\n+\tcase V4L2_EVENT_SOURCE_CHANGE:\n+\t\treturn v4l2_event_subscribe(fh, sub, 4, NULL);\n+\t}\n+\n+\treturn v4l2_ctrl_subscribe_event(fh, sub);\n+}\n+\n+static int unicam_log_status(struct file *file, void *fh)\n+{\n+\tstruct unicam_device *dev = video_drvdata(file);\n+\tstruct unicam_cfg *cfg = &dev->cfg;\n+\tu32 reg;\n+\n+\t/* status for sub devices */\n+\tv4l2_device_call_all(&dev->v4l2_dev, 0, core, log_status);\n+\n+\tunicam_info(dev, \"-----Receiver status-----\\n\");\n+\tunicam_info(dev, \"V4L2 width/height:   %ux%u\\n\",\n+\t\t    dev->v_fmt.fmt.pix.width, dev->v_fmt.fmt.pix.height);\n+\tunicam_info(dev, \"Mediabus format:     %08x\\n\", dev->fmt->code);\n+\tunicam_info(dev, \"V4L2 format:         %08x\\n\",\n+\t\t    dev->v_fmt.fmt.pix.pixelformat);\n+\treg = reg_read(&dev->cfg, UNICAM_IPIPE);\n+\tunicam_info(dev, \"Unpacking/packing:   %u / %u\\n\",\n+\t\t    get_field(reg, UNICAM_PUM_MASK),\n+\t\t    get_field(reg, UNICAM_PPM_MASK));\n+\tunicam_info(dev, \"----Live data----\\n\");\n+\tunicam_info(dev, \"Programmed stride:   %4u\\n\",\n+\t\t    reg_read(cfg, UNICAM_IBLS));\n+\tunicam_info(dev, \"Detected resolution: %ux%u\\n\",\n+\t\t    reg_read(cfg, UNICAM_IHSTA),\n+\t\t    reg_read(cfg, UNICAM_IVSTA));\n+\tunicam_info(dev, \"Write pointer:       %08x\\n\",\n+\t\t    reg_read(cfg, UNICAM_IBWP));\n+\n+\treturn 0;\n+}\n+\n+static void unicam_notify(struct v4l2_subdev *sd,\n+\t\t\t  unsigned int notification, void *arg)\n+{\n+\tstruct unicam_device *dev =\n+\t\tcontainer_of(sd->v4l2_dev, struct unicam_device, v4l2_dev);\n+\n+\tswitch (notification) {\n+\tcase V4L2_DEVICE_NOTIFY_EVENT:\n+\t\tv4l2_event_queue(&dev->video_dev, arg);\n+\t\tbreak;\n+\tdefault:\n+\t\tbreak;\n+\t}\n+}\n+\n+static const struct vb2_ops unicam_video_qops = {\n+\t.wait_prepare\t\t= vb2_ops_wait_prepare,\n+\t.wait_finish\t\t= vb2_ops_wait_finish,\n+\t.queue_setup\t\t= unicam_queue_setup,\n+\t.buf_prepare\t\t= unicam_buffer_prepare,\n+\t.buf_queue\t\t= unicam_buffer_queue,\n+\t.start_streaming\t= unicam_start_streaming,\n+\t.stop_streaming\t\t= unicam_stop_streaming,\n+};\n+\n+/*\n+ * unicam_open : This function is based on the v4l2_fh_open helper function.\n+ * It has been augmented to handle sensor subdevice power management,\n+ */\n+static int unicam_open(struct file *file)\n+{\n+\tstruct unicam_device *dev = video_drvdata(file);\n+\tint ret;\n+\n+\tmutex_lock(&dev->lock);\n+\n+\tret = v4l2_fh_open(file);\n+\tif (ret) {\n+\t\tunicam_err(dev, \"v4l2_fh_open failed\\n\");\n+\t\tgoto unlock;\n+\t}\n+\n+\tif (!v4l2_fh_is_singular_file(file))\n+\t\tgoto unlock;\n+\n+\tret = v4l2_subdev_call(dev->sensor, core, s_power, 1);\n+\tif (ret < 0 && ret != -ENOIOCTLCMD) {\n+\t\tv4l2_fh_release(file);\n+\t\tgoto unlock;\n+\t}\n+\n+\tret = 0;\n+\n+unlock:\n+\tmutex_unlock(&dev->lock);\n+\treturn ret;\n+}\n+\n+static int unicam_release(struct file *file)\n+{\n+\tstruct unicam_device *dev = video_drvdata(file);\n+\tstruct v4l2_subdev *sd = dev->sensor;\n+\tbool fh_singular;\n+\tint ret;\n+\n+\tmutex_lock(&dev->lock);\n+\n+\tfh_singular = v4l2_fh_is_singular_file(file);\n+\n+\tret = _vb2_fop_release(file, NULL);\n+\n+\tif (fh_singular)\n+\t\tv4l2_subdev_call(sd, core, s_power, 0);\n+\n+\tmutex_unlock(&dev->lock);\n+\n+\treturn ret;\n+}\n+\n+/* unicam capture driver file operations */\n+static const struct v4l2_file_operations unicam_fops = {\n+\t.owner\t\t= THIS_MODULE,\n+\t.open           = unicam_open,\n+\t.release        = unicam_release,\n+\t.read\t\t= vb2_fop_read,\n+\t.poll\t\t= vb2_fop_poll,\n+\t.unlocked_ioctl\t= video_ioctl2,\n+\t.mmap\t\t= vb2_fop_mmap,\n+};\n+\n+/* unicam capture ioctl operations */\n+static const struct v4l2_ioctl_ops unicam_ioctl_ops = {\n+\t.vidioc_querycap\t\t= unicam_querycap,\n+\t.vidioc_enum_fmt_vid_cap\t= unicam_enum_fmt_vid_cap,\n+\t.vidioc_g_fmt_vid_cap\t\t= unicam_g_fmt_vid_cap,\n+\t.vidioc_s_fmt_vid_cap\t\t= unicam_s_fmt_vid_cap,\n+\t.vidioc_try_fmt_vid_cap\t\t= unicam_try_fmt_vid_cap,\n+\n+\t.vidioc_enum_input\t\t= unicam_enum_input,\n+\t.vidioc_g_input\t\t\t= unicam_g_input,\n+\t.vidioc_s_input\t\t\t= unicam_s_input,\n+\n+\t.vidioc_querystd\t\t= unicam_querystd,\n+\t.vidioc_s_std\t\t\t= unicam_s_std,\n+\t.vidioc_g_std\t\t\t= unicam_g_std,\n+\n+\t.vidioc_g_edid\t\t\t= unicam_g_edid,\n+\t.vidioc_s_edid\t\t\t= unicam_s_edid,\n+\n+\t.vidioc_enum_framesizes\t\t= unicam_enum_framesizes,\n+\t.vidioc_enum_frameintervals\t= unicam_enum_frameintervals,\n+\n+\t.vidioc_g_parm\t\t\t= unicam_g_parm,\n+\t.vidioc_s_parm\t\t\t= unicam_s_parm,\n+\n+\t.vidioc_s_dv_timings\t\t= unicam_s_dv_timings,\n+\t.vidioc_g_dv_timings\t\t= unicam_g_dv_timings,\n+\t.vidioc_query_dv_timings\t= unicam_query_dv_timings,\n+\t.vidioc_enum_dv_timings\t\t= unicam_enum_dv_timings,\n+\t.vidioc_dv_timings_cap\t\t= unicam_dv_timings_cap,\n+\n+\t.vidioc_reqbufs\t\t\t= vb2_ioctl_reqbufs,\n+\t.vidioc_create_bufs\t\t= vb2_ioctl_create_bufs,\n+\t.vidioc_prepare_buf\t\t= vb2_ioctl_prepare_buf,\n+\t.vidioc_querybuf\t\t= vb2_ioctl_querybuf,\n+\t.vidioc_qbuf\t\t\t= vb2_ioctl_qbuf,\n+\t.vidioc_dqbuf\t\t\t= vb2_ioctl_dqbuf,\n+\t.vidioc_expbuf\t\t\t= vb2_ioctl_expbuf,\n+\t.vidioc_streamon\t\t= vb2_ioctl_streamon,\n+\t.vidioc_streamoff\t\t= vb2_ioctl_streamoff,\n+\n+\t.vidioc_log_status\t\t= unicam_log_status,\n+\t.vidioc_subscribe_event\t\t= unicam_subscribe_event,\n+\t.vidioc_unsubscribe_event\t= v4l2_event_unsubscribe,\n+};\n+\n+static int\n+unicam_async_bound(struct v4l2_async_notifier *notifier,\n+\t\t   struct v4l2_subdev *subdev,\n+\t\t   struct v4l2_async_subdev *asd)\n+{\n+\tstruct unicam_device *unicam = container_of(notifier->v4l2_dev,\n+\t\t\t\t\t       struct unicam_device, v4l2_dev);\n+\n+\tif (unicam->sensor) {\n+\t\tunicam_info(unicam, \"Rejecting subdev %s (Already set!!)\",\n+\t\t\t    subdev->name);\n+\t\treturn 0;\n+\t}\n+\n+\tunicam->sensor = subdev;\n+\tunicam_dbg(1, unicam, \"Using sensor %s for capture\\n\", subdev->name);\n+\n+\treturn 0;\n+}\n+\n+static int unicam_probe_complete(struct unicam_device *unicam)\n+{\n+\tstruct video_device *vdev;\n+\tstruct vb2_queue *q;\n+\tstruct v4l2_mbus_framefmt mbus_fmt = {0};\n+\tconst struct unicam_fmt *fmt;\n+\tint ret;\n+\n+\tv4l2_set_subdev_hostdata(unicam->sensor, unicam);\n+\n+\tunicam->v4l2_dev.notify = unicam_notify;\n+\n+\tunicam->sensor_config = v4l2_subdev_alloc_pad_config(unicam->sensor);\n+\tif (!unicam->sensor_config)\n+\t\treturn -ENOMEM;\n+\n+\tret = __subdev_get_format(unicam, &mbus_fmt);\n+\tif (ret) {\n+\t\tunicam_err(unicam, \"Failed to get_format - ret %d\\n\", ret);\n+\t\treturn ret;\n+\t}\n+\n+\tfmt = find_format_by_code(mbus_fmt.code);\n+\tif (!fmt) {\n+\t\t/* Find the first format that the sensor and unicam both\n+\t\t * support\n+\t\t */\n+\t\tfmt = get_first_supported_format(unicam);\n+\n+\t\tif (!fmt)\n+\t\t\t/* No compatible formats */\n+\t\t\treturn -EINVAL;\n+\n+\t\tmbus_fmt.code = fmt->code;\n+\t\tret = __subdev_set_format(unicam, &mbus_fmt);\n+\t\tif (ret)\n+\t\t\treturn -EINVAL;\n+\t}\n+\tif (mbus_fmt.field != V4L2_FIELD_NONE) {\n+\t\t/* Interlaced not supported - disable it now. */\n+\t\tmbus_fmt.field = V4L2_FIELD_NONE;\n+\t\tret = __subdev_set_format(unicam, &mbus_fmt);\n+\t\tif (ret)\n+\t\t\treturn -EINVAL;\n+\t}\n+\n+\tunicam->fmt = fmt;\n+\tif (fmt->fourcc)\n+\t\tunicam->v_fmt.fmt.pix.pixelformat = fmt->fourcc;\n+\telse\n+\t\tunicam->v_fmt.fmt.pix.pixelformat = fmt->repacked_fourcc;\n+\n+\t/* Read current subdev format */\n+\tunicam_reset_format(unicam);\n+\n+\tif (v4l2_subdev_has_op(unicam->sensor, video, s_std)) {\n+\t\tv4l2_std_id tvnorms;\n+\n+\t\tif (WARN_ON(!v4l2_subdev_has_op(unicam->sensor, video,\n+\t\t\t\t\t\tg_tvnorms)))\n+\t\t\t/*\n+\t\t\t * Subdevice should not advertise s_std but not\n+\t\t\t * g_tvnorms\n+\t\t\t */\n+\t\t\treturn -EINVAL;\n+\n+\t\tret = v4l2_subdev_call(unicam->sensor, video,\n+\t\t\t\t       g_tvnorms, &tvnorms);\n+\t\tif (WARN_ON(ret))\n+\t\t\treturn -EINVAL;\n+\t\tunicam->video_dev.tvnorms |= tvnorms;\n+\t}\n+\n+\tspin_lock_init(&unicam->dma_queue_lock);\n+\tmutex_init(&unicam->lock);\n+\n+\t/* Add controls from the subdevice */\n+\tret = v4l2_ctrl_add_handler(&unicam->ctrl_handler,\n+\t\t\t\t    unicam->sensor->ctrl_handler, NULL, true);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\tq = &unicam->buffer_queue;\n+\tq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;\n+\tq->io_modes = VB2_MMAP | VB2_DMABUF | VB2_READ;\n+\tq->drv_priv = unicam;\n+\tq->ops = &unicam_video_qops;\n+\tq->mem_ops = &vb2_dma_contig_memops;\n+\tq->buf_struct_size = sizeof(struct unicam_buffer);\n+\tq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;\n+\tq->lock = &unicam->lock;\n+\tq->min_buffers_needed = 2;\n+\tq->dev = &unicam->pdev->dev;\n+\n+\tret = vb2_queue_init(q);\n+\tif (ret) {\n+\t\tunicam_err(unicam, \"vb2_queue_init() failed\\n\");\n+\t\treturn ret;\n+\t}\n+\n+\tINIT_LIST_HEAD(&unicam->dma_queue.active);\n+\n+\tvdev = &unicam->video_dev;\n+\tstrlcpy(vdev->name, UNICAM_MODULE_NAME, sizeof(vdev->name));\n+\tvdev->release = video_device_release_empty;\n+\tvdev->fops = &unicam_fops;\n+\tvdev->ioctl_ops = &unicam_ioctl_ops;\n+\tvdev->v4l2_dev = &unicam->v4l2_dev;\n+\tvdev->vfl_dir = VFL_DIR_RX;\n+\tvdev->queue = q;\n+\tvdev->lock = &unicam->lock;\n+\tvdev->device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING |\n+\t\t\t    V4L2_CAP_READWRITE;\n+\n+\t/* If the source has no controls then remove our ctrl handler. */\n+\tif (list_empty(&unicam->ctrl_handler.ctrls))\n+\t\tunicam->v4l2_dev.ctrl_handler = NULL;\n+\n+\tvideo_set_drvdata(vdev, unicam);\n+\tvdev->entity.flags |= MEDIA_ENT_FL_DEFAULT;\n+\n+\tif (!v4l2_subdev_has_op(unicam->sensor, video, s_std)) {\n+\t\tv4l2_disable_ioctl(&unicam->video_dev, VIDIOC_S_STD);\n+\t\tv4l2_disable_ioctl(&unicam->video_dev, VIDIOC_G_STD);\n+\t\tv4l2_disable_ioctl(&unicam->video_dev, VIDIOC_ENUMSTD);\n+\t}\n+\tif (!v4l2_subdev_has_op(unicam->sensor, video, querystd))\n+\t\tv4l2_disable_ioctl(&unicam->video_dev, VIDIOC_QUERYSTD);\n+\tif (!v4l2_subdev_has_op(unicam->sensor, video, s_dv_timings)) {\n+\t\tv4l2_disable_ioctl(&unicam->video_dev, VIDIOC_S_EDID);\n+\t\tv4l2_disable_ioctl(&unicam->video_dev, VIDIOC_G_EDID);\n+\t\tv4l2_disable_ioctl(&unicam->video_dev, VIDIOC_DV_TIMINGS_CAP);\n+\t\tv4l2_disable_ioctl(&unicam->video_dev, VIDIOC_G_DV_TIMINGS);\n+\t\tv4l2_disable_ioctl(&unicam->video_dev, VIDIOC_S_DV_TIMINGS);\n+\t\tv4l2_disable_ioctl(&unicam->video_dev, VIDIOC_ENUM_DV_TIMINGS);\n+\t\tv4l2_disable_ioctl(&unicam->video_dev, VIDIOC_QUERY_DV_TIMINGS);\n+\t}\n+\tif (!v4l2_subdev_has_op(unicam->sensor, pad, enum_frame_interval))\n+\t\tv4l2_disable_ioctl(&unicam->video_dev,\n+\t\t\t\t   VIDIOC_ENUM_FRAMEINTERVALS);\n+\tif (!v4l2_subdev_has_op(unicam->sensor, video, g_frame_interval))\n+\t\tv4l2_disable_ioctl(&unicam->video_dev, VIDIOC_G_PARM);\n+\tif (!v4l2_subdev_has_op(unicam->sensor, video, s_frame_interval))\n+\t\tv4l2_disable_ioctl(&unicam->video_dev, VIDIOC_S_PARM);\n+\n+\tif (!v4l2_subdev_has_op(unicam->sensor, pad, enum_frame_size))\n+\t\tv4l2_disable_ioctl(&unicam->video_dev, VIDIOC_ENUM_FRAMESIZES);\n+\n+\tret = video_register_device(vdev, VFL_TYPE_VIDEO, -1);\n+\tif (ret) {\n+\t\tunicam_err(unicam, \"Unable to register video device.\\n\");\n+\t\treturn ret;\n+\t}\n+\n+\tret = v4l2_device_register_ro_subdev_nodes(&unicam->v4l2_dev);\n+\tif (ret) {\n+\t\tunicam_err(unicam,\n+\t\t\t   \"Unable to register subdev nodes.\\n\");\n+\t\tvideo_unregister_device(&unicam->video_dev);\n+\t\treturn ret;\n+\t}\n+\n+\tret = media_create_pad_link(&unicam->sensor->entity, 0,\n+\t\t\t\t    &unicam->video_dev.entity, 0,\n+\t\t\t\t    MEDIA_LNK_FL_ENABLED |\n+\t\t\t\t    MEDIA_LNK_FL_IMMUTABLE);\n+\tif (ret) {\n+\t\tunicam_err(unicam, \"Unable to create pad links.\\n\");\n+\t\tvideo_unregister_device(&unicam->video_dev);\n+\t\treturn ret;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int unicam_async_complete(struct v4l2_async_notifier *notifier)\n+{\n+\tstruct unicam_device *unicam = container_of(notifier->v4l2_dev,\n+\t\t\t\t\tstruct unicam_device, v4l2_dev);\n+\n+\treturn unicam_probe_complete(unicam);\n+}\n+\n+static const struct v4l2_async_notifier_operations unicam_async_ops = {\n+\t.bound = unicam_async_bound,\n+\t.complete = unicam_async_complete,\n+};\n+\n+static int of_unicam_connect_subdevs(struct unicam_device *dev)\n+{\n+\tstruct platform_device *pdev = dev->pdev;\n+\tstruct device_node *parent, *ep_node = NULL, *remote_ep = NULL,\n+\t\t\t*sensor_node = NULL;\n+\tstruct v4l2_fwnode_endpoint *ep;\n+\tstruct v4l2_async_subdev *asd;\n+\tunsigned int peripheral_data_lanes;\n+\tint ret = -EINVAL;\n+\tunsigned int lane;\n+\n+\tparent = pdev->dev.of_node;\n+\n+\tasd = &dev->asd;\n+\tep = &dev->endpoint;\n+\n+\tep_node = of_graph_get_next_endpoint(parent, NULL);\n+\tif (!ep_node) {\n+\t\tunicam_dbg(3, dev, \"can't get next endpoint\\n\");\n+\t\tgoto cleanup_exit;\n+\t}\n+\n+\tunicam_dbg(3, dev, \"ep_node is %s\\n\", ep_node->name);\n+\n+\tv4l2_fwnode_endpoint_parse(of_fwnode_handle(ep_node), ep);\n+\n+\tfor (lane = 0; lane < ep->bus.mipi_csi2.num_data_lanes; lane++) {\n+\t\tif (ep->bus.mipi_csi2.data_lanes[lane] != lane + 1) {\n+\t\t\tunicam_err(dev, \"Local endpoint - data lane reordering not supported\\n\");\n+\t\t\tgoto cleanup_exit;\n+\t\t}\n+\t}\n+\n+\tperipheral_data_lanes = ep->bus.mipi_csi2.num_data_lanes;\n+\n+\tsensor_node = of_graph_get_remote_port_parent(ep_node);\n+\tif (!sensor_node) {\n+\t\tunicam_dbg(3, dev, \"can't get remote parent\\n\");\n+\t\tgoto cleanup_exit;\n+\t}\n+\tunicam_dbg(3, dev, \"sensor_node is %s\\n\", sensor_node->name);\n+\tasd->match_type = V4L2_ASYNC_MATCH_FWNODE;\n+\tasd->match.fwnode = of_fwnode_handle(sensor_node);\n+\n+\tremote_ep = of_graph_get_remote_endpoint(ep_node);\n+\tif (!remote_ep) {\n+\t\tunicam_dbg(3, dev, \"can't get remote-endpoint\\n\");\n+\t\tgoto cleanup_exit;\n+\t}\n+\tunicam_dbg(3, dev, \"remote_ep is %s\\n\", remote_ep->name);\n+\tv4l2_fwnode_endpoint_parse(of_fwnode_handle(remote_ep), ep);\n+\tunicam_dbg(3, dev, \"parsed remote_ep to endpoint. nr_of_link_frequencies %u, bus_type %u\\n\",\n+\t\t   ep->nr_of_link_frequencies, ep->bus_type);\n+\n+\tswitch (ep->bus_type) {\n+\tcase V4L2_MBUS_CSI2_DPHY:\n+\t\tif (ep->bus.mipi_csi2.num_data_lanes >\n+\t\t\t\tperipheral_data_lanes) {\n+\t\t\tunicam_err(dev, \"Subdevice %s wants too many data lanes (%u > %u)\\n\",\n+\t\t\t\t   sensor_node->name,\n+\t\t\t\t   ep->bus.mipi_csi2.num_data_lanes,\n+\t\t\t\t   peripheral_data_lanes);\n+\t\t\tgoto cleanup_exit;\n+\t\t}\n+\t\tfor (lane = 0;\n+\t\t     lane < ep->bus.mipi_csi2.num_data_lanes;\n+\t\t     lane++) {\n+\t\t\tif (ep->bus.mipi_csi2.data_lanes[lane] != lane + 1) {\n+\t\t\t\tunicam_err(dev, \"Subdevice %s - incompatible data lane config\\n\",\n+\t\t\t\t\t   sensor_node->name);\n+\t\t\t\tgoto cleanup_exit;\n+\t\t\t}\n+\t\t}\n+\t\tdev->max_data_lanes = ep->bus.mipi_csi2.num_data_lanes;\n+\t\tdev->bus_flags = ep->bus.mipi_csi2.flags;\n+\t\tbreak;\n+\tcase V4L2_MBUS_CCP2:\n+\t\tif (ep->bus.mipi_csi1.clock_lane != 0 ||\n+\t\t    ep->bus.mipi_csi1.data_lane != 1) {\n+\t\t\tunicam_err(dev, \"Subdevice %s incompatible lane config\\n\",\n+\t\t\t\t   sensor_node->name);\n+\t\t\tgoto cleanup_exit;\n+\t\t}\n+\t\tdev->max_data_lanes = 1;\n+\t\tdev->bus_flags = ep->bus.mipi_csi1.strobe;\n+\t\tbreak;\n+\tdefault:\n+\t\t/* Unsupported bus type */\n+\t\tunicam_err(dev, \"sub-device %s is not a CSI2 or CCP2 device %d\\n\",\n+\t\t\t   sensor_node->name, ep->bus_type);\n+\t\tgoto cleanup_exit;\n+\t}\n+\n+\t/* Store bus type - CSI2 or CCP2 */\n+\tdev->bus_type = ep->bus_type;\n+\tunicam_dbg(3, dev, \"bus_type is %d\\n\", dev->bus_type);\n+\n+\t/* Store Virtual Channel number */\n+\tdev->virtual_channel = ep->base.id;\n+\n+\tunicam_dbg(3, dev, \"v4l2-endpoint: %s\\n\",\n+\t\t   dev->bus_type == V4L2_MBUS_CSI2_DPHY ? \"CSI2\" : \"CCP2\");\n+\tunicam_dbg(3, dev, \"Virtual Channel=%d\\n\", dev->virtual_channel);\n+\tif (dev->bus_type == V4L2_MBUS_CSI2_DPHY)\n+\t\tunicam_dbg(3, dev, \"flags=0x%08x\\n\", ep->bus.mipi_csi2.flags);\n+\tunicam_dbg(3, dev, \"num_data_lanes=%d\\n\", dev->max_data_lanes);\n+\n+\tunicam_dbg(1, dev, \"found sub-device %s\\n\", sensor_node->name);\n+\n+\tv4l2_async_notifier_init(&dev->notifier);\n+\n+\tret = v4l2_async_notifier_add_subdev(&dev->notifier, asd);\n+\tif (ret) {\n+\t\tunicam_err(dev, \"Error adding subdevice - ret %d\\n\", ret);\n+\t\tgoto cleanup_exit;\n+\t}\n+\n+\tdev->notifier.ops = &unicam_async_ops;\n+\tret = v4l2_async_notifier_register(&dev->v4l2_dev,\n+\t\t\t\t\t   &dev->notifier);\n+\tif (ret) {\n+\t\tunicam_err(dev, \"Error registering async notifier - ret %d\\n\",\n+\t\t\t   ret);\n+\t\tret = -EINVAL;\n+\t}\n+\n+cleanup_exit:\n+\tif (remote_ep)\n+\t\tof_node_put(remote_ep);\n+\tif (sensor_node)\n+\t\tof_node_put(sensor_node);\n+\tif (ep_node)\n+\t\tof_node_put(ep_node);\n+\n+\treturn ret;\n+}\n+\n+static int unicam_probe(struct platform_device *pdev)\n+{\n+\tstruct unicam_cfg *unicam_cfg;\n+\tstruct unicam_device *unicam;\n+\tstruct v4l2_ctrl_handler *hdl;\n+\tstruct resource\t*res;\n+\tint ret;\n+\n+\tunicam = devm_kzalloc(&pdev->dev, sizeof(*unicam), GFP_KERNEL);\n+\tif (!unicam)\n+\t\treturn -ENOMEM;\n+\n+\tunicam->pdev = pdev;\n+\tunicam_cfg = &unicam->cfg;\n+\n+\tres = platform_get_resource(pdev, IORESOURCE_MEM, 0);\n+\tunicam_cfg->base = devm_ioremap_resource(&pdev->dev, res);\n+\tif (IS_ERR(unicam_cfg->base)) {\n+\t\tunicam_err(unicam, \"Failed to get main io block\\n\");\n+\t\treturn PTR_ERR(unicam_cfg->base);\n+\t}\n+\n+\tres = platform_get_resource(pdev, IORESOURCE_MEM, 1);\n+\tunicam_cfg->clk_gate_base = devm_ioremap_resource(&pdev->dev, res);\n+\tif (IS_ERR(unicam_cfg->clk_gate_base)) {\n+\t\tunicam_err(unicam, \"Failed to get 2nd io block\\n\");\n+\t\treturn PTR_ERR(unicam_cfg->clk_gate_base);\n+\t}\n+\n+\tunicam->clock = devm_clk_get(&pdev->dev, \"lp\");\n+\tif (IS_ERR(unicam->clock)) {\n+\t\tunicam_err(unicam, \"Failed to get clock\\n\");\n+\t\treturn PTR_ERR(unicam->clock);\n+\t}\n+\n+\tret = platform_get_irq(pdev, 0);\n+\tif (ret <= 0) {\n+\t\tdev_err(&pdev->dev, \"No IRQ resource\\n\");\n+\t\treturn -ENODEV;\n+\t}\n+\n+\tret = devm_request_irq(&pdev->dev, ret, unicam_isr, 0,\n+\t\t\t       \"unicam_capture0\", unicam);\n+\tif (ret) {\n+\t\tdev_err(&pdev->dev, \"Unable to request interrupt\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tunicam->mdev.dev = &pdev->dev;\n+\tstrscpy(unicam->mdev.model, UNICAM_MODULE_NAME,\n+\t\tsizeof(unicam->mdev.model));\n+\tstrscpy(unicam->mdev.serial, \"\", sizeof(unicam->mdev.serial));\n+\tsnprintf(unicam->mdev.bus_info, sizeof(unicam->mdev.bus_info),\n+\t\t \"platform:%s %s\",\n+\t\t pdev->dev.driver->name, dev_name(&pdev->dev));\n+\tunicam->mdev.hw_revision = 1;\n+\n+\tmedia_entity_pads_init(&unicam->video_dev.entity, 1, &unicam->pad);\n+\tmedia_device_init(&unicam->mdev);\n+\n+\tunicam->v4l2_dev.mdev = &unicam->mdev;\n+\n+\tret = v4l2_device_register(&pdev->dev, &unicam->v4l2_dev);\n+\tif (ret) {\n+\t\tunicam_err(unicam,\n+\t\t\t   \"Unable to register v4l2 device.\\n\");\n+\t\tgoto media_cleanup;\n+\t}\n+\n+\tret = media_device_register(&unicam->mdev);\n+\tif (ret < 0) {\n+\t\tunicam_err(unicam,\n+\t\t\t   \"Unable to register media-controller device.\\n\");\n+\t\tgoto probe_out_v4l2_unregister;\n+\t}\n+\n+\t/* Reserve space for the controls */\n+\thdl = &unicam->ctrl_handler;\n+\tret = v4l2_ctrl_handler_init(hdl, 16);\n+\tif (ret < 0)\n+\t\tgoto media_unregister;\n+\tunicam->v4l2_dev.ctrl_handler = hdl;\n+\n+\t/* set the driver data in platform device */\n+\tplatform_set_drvdata(pdev, unicam);\n+\n+\tret = of_unicam_connect_subdevs(unicam);\n+\tif (ret) {\n+\t\tdev_err(&pdev->dev, \"Failed to connect subdevs\\n\");\n+\t\tgoto free_hdl;\n+\t}\n+\n+\t/* Enable the block power domain */\n+\tpm_runtime_enable(&pdev->dev);\n+\n+\treturn 0;\n+\n+free_hdl:\n+\tv4l2_ctrl_handler_free(hdl);\n+media_unregister:\n+\tmedia_device_unregister(&unicam->mdev);\n+probe_out_v4l2_unregister:\n+\tv4l2_device_unregister(&unicam->v4l2_dev);\n+media_cleanup:\n+\tmedia_device_cleanup(&unicam->mdev);\n+\n+\treturn ret;\n+}\n+\n+static int unicam_remove(struct platform_device *pdev)\n+{\n+\tstruct unicam_device *unicam = platform_get_drvdata(pdev);\n+\n+\tunicam_dbg(2, unicam, \"%s\\n\", __func__);\n+\n+\tpm_runtime_disable(&pdev->dev);\n+\n+\tv4l2_async_notifier_unregister(&unicam->notifier);\n+\tv4l2_ctrl_handler_free(&unicam->ctrl_handler);\n+\tv4l2_device_unregister(&unicam->v4l2_dev);\n+\tvideo_unregister_device(&unicam->video_dev);\n+\tif (unicam->sensor_config)\n+\t\tv4l2_subdev_free_pad_config(unicam->sensor_config);\n+\tmedia_device_unregister(&unicam->mdev);\n+\tmedia_device_cleanup(&unicam->mdev);\n+\n+\treturn 0;\n+}\n+\n+static const struct of_device_id unicam_of_match[] = {\n+\t{ .compatible = \"brcm,bcm2835-unicam\", },\n+\t{ /* sentinel */ },\n+};\n+MODULE_DEVICE_TABLE(of, unicam_of_match);\n+\n+static struct platform_driver unicam_driver = {\n+\t.probe\t\t= unicam_probe,\n+\t.remove\t\t= unicam_remove,\n+\t.driver = {\n+\t\t.name\t= UNICAM_MODULE_NAME,\n+\t\t.of_match_table = of_match_ptr(unicam_of_match),\n+\t},\n+};\n+\n+module_platform_driver(unicam_driver);\n+\n+MODULE_AUTHOR(\"Dave Stevenson <dave.stevenson@raspberrypi.com>\");\n+MODULE_DESCRIPTION(\"BCM2835 Unicam driver\");\n+MODULE_LICENSE(\"GPL\");\n+MODULE_VERSION(UNICAM_VERSION);\n--- /dev/null\n+++ b/drivers/media/platform/bcm2835/vc4-regs-unicam.h\n@@ -0,0 +1,253 @@\n+/* SPDX-License-Identifier: GPL-2.0-only */\n+\n+/*\n+ * Copyright (C) 2017-2020 Raspberry Pi Trading.\n+ * Dave Stevenson <dave.stevenson@raspberrypi.com>\n+ */\n+\n+#ifndef VC4_REGS_UNICAM_H\n+#define VC4_REGS_UNICAM_H\n+\n+/*\n+ * The following values are taken from files found within the code drop\n+ * made by Broadcom for the BCM21553 Graphics Driver, predominantly in\n+ * brcm_usrlib/dag/vmcsx/vcinclude/hardware_vc4.h.\n+ * They have been modified to be only the register offset.\n+ */\n+#define UNICAM_CTRL\t0x000\n+#define UNICAM_STA\t0x004\n+#define UNICAM_ANA\t0x008\n+#define UNICAM_PRI\t0x00c\n+#define UNICAM_CLK\t0x010\n+#define UNICAM_CLT\t0x014\n+#define UNICAM_DAT0\t0x018\n+#define UNICAM_DAT1\t0x01c\n+#define UNICAM_DAT2\t0x020\n+#define UNICAM_DAT3\t0x024\n+#define UNICAM_DLT\t0x028\n+#define UNICAM_CMP0\t0x02c\n+#define UNICAM_CMP1\t0x030\n+#define UNICAM_CAP0\t0x034\n+#define UNICAM_CAP1\t0x038\n+#define UNICAM_ICTL\t0x100\n+#define UNICAM_ISTA\t0x104\n+#define UNICAM_IDI0\t0x108\n+#define UNICAM_IPIPE\t0x10c\n+#define UNICAM_IBSA0\t0x110\n+#define UNICAM_IBEA0\t0x114\n+#define UNICAM_IBLS\t0x118\n+#define UNICAM_IBWP\t0x11c\n+#define UNICAM_IHWIN\t0x120\n+#define UNICAM_IHSTA\t0x124\n+#define UNICAM_IVWIN\t0x128\n+#define UNICAM_IVSTA\t0x12c\n+#define UNICAM_ICC\t0x130\n+#define UNICAM_ICS\t0x134\n+#define UNICAM_IDC\t0x138\n+#define UNICAM_IDPO\t0x13c\n+#define UNICAM_IDCA\t0x140\n+#define UNICAM_IDCD\t0x144\n+#define UNICAM_IDS\t0x148\n+#define UNICAM_DCS\t0x200\n+#define UNICAM_DBSA0\t0x204\n+#define UNICAM_DBEA0\t0x208\n+#define UNICAM_DBWP\t0x20c\n+#define UNICAM_DBCTL\t0x300\n+#define UNICAM_IBSA1\t0x304\n+#define UNICAM_IBEA1\t0x308\n+#define UNICAM_IDI1\t0x30c\n+#define UNICAM_DBSA1\t0x310\n+#define UNICAM_DBEA1\t0x314\n+#define UNICAM_MISC\t0x400\n+\n+/*\n+ * The following bitmasks are from the kernel released by Broadcom\n+ * for Android - https://android.googlesource.com/kernel/bcm/\n+ * The Rhea, Hawaii, and Java chips all contain the same VideoCore4\n+ * Unicam block as BCM2835, as defined in eg\n+ * arch/arm/mach-rhea/include/mach/rdb_A0/brcm_rdb_cam.h and similar.\n+ * Values reworked to use the kernel BIT and GENMASK macros.\n+ *\n+ * Some of the bit mnenomics have been amended to match the datasheet.\n+ */\n+/* UNICAM_CTRL Register */\n+#define UNICAM_CPE\t\tBIT(0)\n+#define UNICAM_MEM\t\tBIT(1)\n+#define UNICAM_CPR\t\tBIT(2)\n+#define UNICAM_CPM_MASK\t\tGENMASK(3, 3)\n+#define UNICAM_CPM_CSI2\t\t0\n+#define UNICAM_CPM_CCP2\t\t1\n+#define UNICAM_SOE\t\tBIT(4)\n+#define UNICAM_DCM_MASK\t\tGENMASK(5, 5)\n+#define UNICAM_DCM_STROBE\t0\n+#define UNICAM_DCM_DATA\t\t1\n+#define UNICAM_SLS\t\tBIT(6)\n+#define UNICAM_PFT_MASK\t\tGENMASK(11, 8)\n+#define UNICAM_OET_MASK\t\tGENMASK(20, 12)\n+\n+/* UNICAM_STA Register */\n+#define UNICAM_SYN\t\tBIT(0)\n+#define UNICAM_CS\t\tBIT(1)\n+#define UNICAM_SBE\t\tBIT(2)\n+#define UNICAM_PBE\t\tBIT(3)\n+#define UNICAM_HOE\t\tBIT(4)\n+#define UNICAM_PLE\t\tBIT(5)\n+#define UNICAM_SSC\t\tBIT(6)\n+#define UNICAM_CRCE\t\tBIT(7)\n+#define UNICAM_OES\t\tBIT(8)\n+#define UNICAM_IFO\t\tBIT(9)\n+#define UNICAM_OFO\t\tBIT(10)\n+#define UNICAM_BFO\t\tBIT(11)\n+#define UNICAM_DL\t\tBIT(12)\n+#define UNICAM_PS\t\tBIT(13)\n+#define UNICAM_IS\t\tBIT(14)\n+#define UNICAM_PI0\t\tBIT(15)\n+#define UNICAM_PI1\t\tBIT(16)\n+#define UNICAM_FSI_S\t\tBIT(17)\n+#define UNICAM_FEI_S\t\tBIT(18)\n+#define UNICAM_LCI_S\t\tBIT(19)\n+#define UNICAM_BUF0_RDY\t\tBIT(20)\n+#define UNICAM_BUF0_NO\t\tBIT(21)\n+#define UNICAM_BUF1_RDY\t\tBIT(22)\n+#define UNICAM_BUF1_NO\t\tBIT(23)\n+#define UNICAM_DI\t\tBIT(24)\n+\n+#define UNICAM_STA_MASK_ALL \\\n+\t\t(UNICAM_DL + \\\n+\t\tUNICAM_SBE + \\\n+\t\tUNICAM_PBE + \\\n+\t\tUNICAM_HOE + \\\n+\t\tUNICAM_PLE + \\\n+\t\tUNICAM_SSC + \\\n+\t\tUNICAM_CRCE + \\\n+\t\tUNICAM_IFO + \\\n+\t\tUNICAM_OFO + \\\n+\t\tUNICAM_PS + \\\n+\t\tUNICAM_PI0 + \\\n+\t\tUNICAM_PI1)\n+\n+/* UNICAM_ANA Register */\n+#define UNICAM_APD\t\tBIT(0)\n+#define UNICAM_BPD\t\tBIT(1)\n+#define UNICAM_AR\t\tBIT(2)\n+#define UNICAM_DDL\t\tBIT(3)\n+#define UNICAM_CTATADJ_MASK\tGENMASK(7, 4)\n+#define UNICAM_PTATADJ_MASK\tGENMASK(11, 8)\n+\n+/* UNICAM_PRI Register */\n+#define UNICAM_PE\t\tBIT(0)\n+#define UNICAM_PT_MASK\t\tGENMASK(2, 1)\n+#define UNICAM_NP_MASK\t\tGENMASK(7, 4)\n+#define UNICAM_PP_MASK\t\tGENMASK(11, 8)\n+#define UNICAM_BS_MASK\t\tGENMASK(15, 12)\n+#define UNICAM_BL_MASK\t\tGENMASK(17, 16)\n+\n+/* UNICAM_CLK Register */\n+#define UNICAM_CLE\t\tBIT(0)\n+#define UNICAM_CLPD\t\tBIT(1)\n+#define UNICAM_CLLPE\t\tBIT(2)\n+#define UNICAM_CLHSE\t\tBIT(3)\n+#define UNICAM_CLTRE\t\tBIT(4)\n+#define UNICAM_CLAC_MASK\tGENMASK(8, 5)\n+#define UNICAM_CLSTE\t\tBIT(29)\n+\n+/* UNICAM_CLT Register */\n+#define UNICAM_CLT1_MASK\tGENMASK(7, 0)\n+#define UNICAM_CLT2_MASK\tGENMASK(15, 8)\n+\n+/* UNICAM_DATn Registers */\n+#define UNICAM_DLE\t\tBIT(0)\n+#define UNICAM_DLPD\t\tBIT(1)\n+#define UNICAM_DLLPE\t\tBIT(2)\n+#define UNICAM_DLHSE\t\tBIT(3)\n+#define UNICAM_DLTRE\t\tBIT(4)\n+#define UNICAM_DLSM\t\tBIT(5)\n+#define UNICAM_DLFO\t\tBIT(28)\n+#define UNICAM_DLSTE\t\tBIT(29)\n+\n+#define UNICAM_DAT_MASK_ALL (UNICAM_DLSTE + UNICAM_DLFO)\n+\n+/* UNICAM_DLT Register */\n+#define UNICAM_DLT1_MASK\tGENMASK(7, 0)\n+#define UNICAM_DLT2_MASK\tGENMASK(15, 8)\n+#define UNICAM_DLT3_MASK\tGENMASK(23, 16)\n+\n+/* UNICAM_ICTL Register */\n+#define UNICAM_FSIE\t\tBIT(0)\n+#define UNICAM_FEIE\t\tBIT(1)\n+#define UNICAM_IBOB\t\tBIT(2)\n+#define UNICAM_FCM\t\tBIT(3)\n+#define UNICAM_TFC\t\tBIT(4)\n+#define UNICAM_LIP_MASK\t\tGENMASK(6, 5)\n+#define UNICAM_LCIE_MASK\tGENMASK(28, 16)\n+\n+/* UNICAM_IDI0/1 Register */\n+#define UNICAM_ID0_MASK\t\tGENMASK(7, 0)\n+#define UNICAM_ID1_MASK\t\tGENMASK(15, 8)\n+#define UNICAM_ID2_MASK\t\tGENMASK(23, 16)\n+#define UNICAM_ID3_MASK\t\tGENMASK(31, 24)\n+\n+/* UNICAM_ISTA Register */\n+#define UNICAM_FSI\t\tBIT(0)\n+#define UNICAM_FEI\t\tBIT(1)\n+#define UNICAM_LCI\t\tBIT(2)\n+\n+#define UNICAM_ISTA_MASK_ALL (UNICAM_FSI + UNICAM_FEI + UNICAM_LCI)\n+\n+/* UNICAM_IPIPE Register */\n+#define UNICAM_PUM_MASK\t\tGENMASK(2, 0)\n+\t\t/* Unpacking modes */\n+\t\t#define UNICAM_PUM_NONE\t\t0\n+\t\t#define UNICAM_PUM_UNPACK6\t1\n+\t\t#define UNICAM_PUM_UNPACK7\t2\n+\t\t#define UNICAM_PUM_UNPACK8\t3\n+\t\t#define UNICAM_PUM_UNPACK10\t4\n+\t\t#define UNICAM_PUM_UNPACK12\t5\n+\t\t#define UNICAM_PUM_UNPACK14\t6\n+\t\t#define UNICAM_PUM_UNPACK16\t7\n+#define UNICAM_DDM_MASK\t\tGENMASK(6, 3)\n+#define UNICAM_PPM_MASK\t\tGENMASK(9, 7)\n+\t\t/* Packing modes */\n+\t\t#define UNICAM_PPM_NONE\t\t0\n+\t\t#define UNICAM_PPM_PACK8\t1\n+\t\t#define UNICAM_PPM_PACK10\t2\n+\t\t#define UNICAM_PPM_PACK12\t3\n+\t\t#define UNICAM_PPM_PACK14\t4\n+\t\t#define UNICAM_PPM_PACK16\t5\n+#define UNICAM_DEM_MASK\t\tGENMASK(11, 10)\n+#define UNICAM_DEBL_MASK\tGENMASK(14, 12)\n+#define UNICAM_ICM_MASK\t\tGENMASK(16, 15)\n+#define UNICAM_IDM_MASK\t\tGENMASK(17, 17)\n+\n+/* UNICAM_ICC Register */\n+#define UNICAM_ICFL_MASK\tGENMASK(4, 0)\n+#define UNICAM_ICFH_MASK\tGENMASK(9, 5)\n+#define UNICAM_ICST_MASK\tGENMASK(12, 10)\n+#define UNICAM_ICLT_MASK\tGENMASK(15, 13)\n+#define UNICAM_ICLL_MASK\tGENMASK(31, 16)\n+\n+/* UNICAM_DCS Register */\n+#define UNICAM_DIE\t\tBIT(0)\n+#define UNICAM_DIM\t\tBIT(1)\n+#define UNICAM_DBOB\t\tBIT(3)\n+#define UNICAM_FDE\t\tBIT(4)\n+#define UNICAM_LDP\t\tBIT(5)\n+#define UNICAM_EDL_MASK\t\tGENMASK(15, 8)\n+\n+/* UNICAM_DBCTL Register */\n+#define UNICAM_DBEN\t\tBIT(0)\n+#define UNICAM_BUF0_IE\t\tBIT(1)\n+#define UNICAM_BUF1_IE\t\tBIT(2)\n+\n+/* UNICAM_CMP[0,1] register */\n+#define UNICAM_PCE\t\tBIT(31)\n+#define UNICAM_GI\t\tBIT(9)\n+#define UNICAM_CPH\t\tBIT(8)\n+#define UNICAM_PCVC_MASK\tGENMASK(7, 6)\n+#define UNICAM_PCDT_MASK\tGENMASK(5, 0)\n+\n+/* UNICAM_MISC register */\n+#define UNICAM_FL0\t\tBIT(6)\n+#define UNICAM_FL1\t\tBIT(9)\n+\n+#endif\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0210-media-uapi-v4l2-core-Add-sensor-ancillary-data-V4L2-.patch",
    "content": "From 2f43e72bd136b5e69dbc6453555d8c5fecbb9d3a Mon Sep 17 00:00:00 2001\nFrom: Naushir Patuck <naush@raspberrypi.com>\nDate: Wed, 1 Apr 2020 08:46:29 +0100\nSubject: [PATCH] media: uapi: v4l2-core: Add sensor ancillary data\n V4L2 foucc type.\n\nAdd V4L2_META_FMT_SENSOR_DATA format 4CC.\n\nThis new format will be used by the BCM2835 Unicam device to return\nout camera sensor embedded data.\n\nSigned-off-by: Naushir Patuck <naush@raspberrypi.com>\n---\n .../userspace-api/media/v4l/meta-formats.rst  |  1 +\n .../media/v4l/pixfmt-meta-sensor-data.rst     | 32 +++++++++++++++++++\n drivers/media/v4l2-core/v4l2-ioctl.c          |  1 +\n include/uapi/linux/videodev2.h                |  1 +\n 4 files changed, 35 insertions(+)\n create mode 100644 Documentation/userspace-api/media/v4l/pixfmt-meta-sensor-data.rst\n\n--- a/Documentation/userspace-api/media/v4l/meta-formats.rst\n+++ b/Documentation/userspace-api/media/v4l/meta-formats.rst\n@@ -15,6 +15,7 @@ These formats are used for the :ref:`met\n     pixfmt-meta-d4xx\n     pixfmt-meta-intel-ipu3\n     pixfmt-meta-rkisp1\n+    pixfmt-meta-sensor-data\n     pixfmt-meta-uvc\n     pixfmt-meta-vsp1-hgo\n     pixfmt-meta-vsp1-hgt\n--- /dev/null\n+++ b/Documentation/userspace-api/media/v4l/pixfmt-meta-sensor-data.rst\n@@ -0,0 +1,32 @@\n+.. Permission is granted to copy, distribute and/or modify this\n+.. document under the terms of the GNU Free Documentation License,\n+.. Version 1.1 or any later version published by the Free Software\n+.. Foundation, with no Invariant Sections, no Front-Cover Texts\n+.. and no Back-Cover Texts. A copy of the license is included at\n+.. Documentation/media/uapi/fdl-appendix.rst.\n+..\n+.. TODO: replace it to GFDL-1.1-or-later WITH no-invariant-sections\n+\n+.. _v4l2-meta-fmt-sensor-data:\n+\n+***********************************\n+V4L2_META_FMT_SENSOR_DATA  ('SENS')\n+***********************************\n+\n+Sensor Ancillary Metadata\n+\n+Description\n+===========\n+\n+This format describes ancillary data generated by a camera sensor and\n+transmitted over a stream on the camera bus. Sensor vendors generally have their\n+own custom format for this ancillary data. Some vendors follow a generic\n+CSI-2/SMIA embedded data format as described in the `CSI-2 specification.\n+<https://mipi.org/specifications/csi-2>`_\n+\n+The size of the embedded buffer is defined as a single line with a pixel width\n+width specified in bytes. This is obtained by a call to the\n+:c:type:`VIDIOC_SUBDEV_G_FMT` ioctl on the sensor subdevice where the ``pad``\n+field in :c:type:`v4l2_subdev_format` is set to 1.  Note that this size is fixed\n+and cannot be modified with a call to :c:type:`VIDIOC_SUBDEV_S_FMT`.\n+\n--- a/drivers/media/v4l2-core/v4l2-ioctl.c\n+++ b/drivers/media/v4l2-core/v4l2-ioctl.c\n@@ -1422,6 +1422,7 @@ static void v4l_fill_fmtdesc(struct v4l2\n \tcase V4L2_META_FMT_UVC:\t\tdescr = \"UVC Payload Header Metadata\"; break;\n \tcase V4L2_META_FMT_D4XX:\tdescr = \"Intel D4xx UVC Metadata\"; break;\n \tcase V4L2_META_FMT_VIVID:       descr = \"Vivid Metadata\"; break;\n+\tcase V4L2_META_FMT_SENSOR_DATA:\tdescr = \"Sensor Ancillary Metadata\"; break;\n \n \tdefault:\n \t\t/* Compressed formats */\n--- a/include/uapi/linux/videodev2.h\n+++ b/include/uapi/linux/videodev2.h\n@@ -778,6 +778,7 @@ struct v4l2_pix_format {\n #define V4L2_META_FMT_UVC         v4l2_fourcc('U', 'V', 'C', 'H') /* UVC Payload Header metadata */\n #define V4L2_META_FMT_D4XX        v4l2_fourcc('D', '4', 'X', 'X') /* D4XX Payload Header metadata */\n #define V4L2_META_FMT_VIVID\t  v4l2_fourcc('V', 'I', 'V', 'D') /* Vivid Metadata */\n+#define V4L2_META_FMT_SENSOR_DATA v4l2_fourcc('S', 'E', 'N', 'S') /* Sensor Ancillary metadata */\n \n /* priv field value to indicates that subsequent fields are valid. */\n #define V4L2_PIX_FMT_PRIV_MAGIC\t\t0xfeedcafe\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0211-media-uapi-Add-MEDIA_BUS_FMT_SENSOR_DATA-media-bus-f.patch",
    "content": "From 6c8bd941bfcbb6fc4f6b4f8261aa03f280e80f20 Mon Sep 17 00:00:00 2001\nFrom: Naushir Patuck <naush@raspberrypi.com>\nDate: Tue, 21 Jan 2020 14:06:47 +0000\nSubject: [PATCH] media: uapi: Add MEDIA_BUS_FMT_SENSOR_DATA media bus\n format\n\nThis patch adds MEDIA_BUS_FMT_SENSOR_DATA used by the bcm2835-unicam\ndriver to support CSI-2 embedded data streams from camera sensors.\n\nSigned-off-by: Naushir Patuck <naush@raspberrypi.com>\n---\n .../media/v4l/subdev-formats.rst              | 33 +++++++++++++++++++\n include/uapi/linux/media-bus-format.h         |  3 ++\n 2 files changed, 36 insertions(+)\n\n--- a/Documentation/userspace-api/media/v4l/subdev-formats.rst\n+++ b/Documentation/userspace-api/media/v4l/subdev-formats.rst\n@@ -7899,3 +7899,36 @@ formats.\n       - 0x5001\n       - Interleaved raw UYVY and JPEG image format with embedded meta-data\n \tused by Samsung S3C73MX camera sensors.\n+\n+\n+\n+.. _v4l2-mbus-sensor-data:\n+\n+Sensor Ancillary Metadata Formats\n+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^\n+\n+This section lists ancillary data generated by a camera sensor and\n+transmitted over a stream on the camera bus.\n+\n+The following table lists the existing sensor ancillary metadata formats:\n+\n+\n+.. _v4l2-mbus-pixelcode-sensor-metadata:\n+\n+.. tabularcolumns:: |p{8.0cm}|p{1.4cm}|p{7.7cm}|\n+\n+.. flat-table:: Sensor ancillary metadata formats\n+    :header-rows:  1\n+    :stub-columns: 0\n+\n+    * - Identifier\n+      - Code\n+      - Comments\n+    * .. _MEDIA_BUS_FMT_SENSOR_DATA:\n+\n+      - MEDIA_BUS_FMT_SENSOR_DATA\n+      - 0x7001\n+      - Sensor vendor specific ancillary metadata. Some vendors follow a generic\n+        CSI-2/SMIA embedded data format as described in the `CSI-2 specification.\n+\t<https://mipi.org/specifications/csi-2>`_\n+\n--- a/include/uapi/linux/media-bus-format.h\n+++ b/include/uapi/linux/media-bus-format.h\n@@ -156,4 +156,7 @@\n /* HSV - next is\t0x6002 */\n #define MEDIA_BUS_FMT_AHSV8888_1X32\t\t0x6001\n \n+/* Sensor ancillary metadata formats - next is 0x7002 */\n+#define MEDIA_BUS_FMT_SENSOR_DATA\t\t0x7001\n+\n #endif /* __LINUX_MEDIA_BUS_FORMAT_H */\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0212-media-bcm2835-unicam-Add-support-for-mulitple-device.patch",
    "content": "From bc7cac66c7c590d64fb4d4597f3bb661f7a0893f Mon Sep 17 00:00:00 2001\nFrom: Naushir Patuck <naush@raspberrypi.com>\nDate: Tue, 7 Apr 2020 10:42:14 +0100\nSubject: [PATCH] media: bcm2835-unicam: Add support for mulitple\n device nodes.\n\nMove device node specific state out of the device state structure and\ninto a new node structure.  This separation will be needed for future\nchanges where we will add an embedded data node to the driver to work\nalongside the existing image data node.\n\nCurrently only use a single image node, so this commit does not add\nany functional changes.\n\nSigned-off-by: Naushir Patuck <naush@raspberrypi.com>\n---\n .../media/platform/bcm2835/bcm2835-unicam.c   | 484 ++++++++++--------\n 1 file changed, 283 insertions(+), 201 deletions(-)\n\n--- a/drivers/media/platform/bcm2835/bcm2835-unicam.c\n+++ b/drivers/media/platform/bcm2835/bcm2835-unicam.c\n@@ -109,7 +109,8 @@ MODULE_PARM_DESC(debug, \"Debug level 0-3\n /* Define a nominal minimum image size */\n #define MIN_WIDTH\t16\n #define MIN_HEIGHT\t16\n-\n+/* Maximum number of simulataneous streams Uncaim can handle. */\n+#define MAX_NODES\t2\n /*\n  * struct unicam_fmt - Unicam media bus format information\n  * @pixelformat: V4L2 pixel format FCC identifier. 0 if n/a.\n@@ -346,11 +347,37 @@ struct unicam_cfg {\n \n #define MAX_POSSIBLE_PIX_FMTS (ARRAY_SIZE(formats))\n \n-struct unicam_device {\n-\t/* V4l2 specific parameters */\n+struct unicam_node {\n+\tbool registered;\n+\tunsigned int pad_id;\n+\t/* Pointer pointing to current v4l2_buffer */\n+\tstruct unicam_buffer *cur_frm;\n+\t/* Pointer pointing to next v4l2_buffer */\n+\tstruct unicam_buffer *next_frm;\n+\t/* video capture */\n+\tconst struct unicam_fmt *fmt;\n+\t/* Used to store current pixel format */\n+\tstruct v4l2_format v_fmt;\n+\t/* Used to store current mbus frame format */\n+\tstruct v4l2_mbus_framefmt m_fmt;\n+\t/* Buffer queue used in video-buf */\n+\tstruct vb2_queue buffer_queue;\n+\t/* Queue of filled frames */\n+\tstruct unicam_dmaqueue dma_queue;\n+\t/* IRQ lock for DMA queue */\n+\tspinlock_t dma_queue_lock;\n+\t/* lock used to access this structure */\n+\tstruct mutex lock;\n \t/* Identifies video device for this channel */\n \tstruct video_device video_dev;\n+\t/* Pointer to the parent handle */\n+\tstruct unicam_device *dev;\n+\tstruct media_pad pad;\n \tstruct v4l2_ctrl_handler ctrl_handler;\n+};\n+\n+struct unicam_device {\n+\t/* V4l2 specific parameters */\n \n \tstruct v4l2_fwnode_endpoint endpoint;\n \n@@ -363,7 +390,6 @@ struct unicam_device {\n \t/* V4l2 device */\n \tstruct v4l2_device v4l2_dev;\n \tstruct media_device mdev;\n-\tstruct media_pad pad;\n \n \t/* parent device */\n \tstruct platform_device *pdev;\n@@ -378,18 +404,6 @@ struct unicam_device {\n \t/* current input at the sub device */\n \tint current_input;\n \n-\t/* Pointer pointing to current v4l2_buffer */\n-\tstruct unicam_buffer *cur_frm;\n-\t/* Pointer pointing to next v4l2_buffer */\n-\tstruct unicam_buffer *next_frm;\n-\n-\t/* video capture */\n-\tconst struct unicam_fmt\t*fmt;\n-\t/* Used to store current pixel format */\n-\tstruct v4l2_format v_fmt;\n-\t/* Used to store current mbus frame format */\n-\tstruct v4l2_mbus_framefmt m_fmt;\n-\n \tunsigned int virtual_channel;\n \tenum v4l2_mbus_type bus_type;\n \t/*\n@@ -401,20 +415,10 @@ struct unicam_device {\n \tunsigned int active_data_lanes;\n \n \tstruct v4l2_rect crop;\n-\n-\t/* Currently selected input on subdev */\n-\tint input;\n-\n-\t/* Buffer queue used in video-buf */\n-\tstruct vb2_queue buffer_queue;\n-\t/* Queue of filled frames */\n-\tstruct unicam_dmaqueue dma_queue;\n-\t/* IRQ lock for DMA queue */\n-\tspinlock_t dma_queue_lock;\n-\t/* lock used to access this structure */\n-\tstruct mutex lock;\n \t/* Flag to denote that we are processing buffers */\n \tint streaming;\n+\n+\tstruct unicam_node node[MAX_NODES];\n };\n \n /* Hardware access */\n@@ -526,10 +530,11 @@ static inline unsigned int bytes_per_lin\n }\n \n static int __subdev_get_format(struct unicam_device *dev,\n-\t\t\t       struct v4l2_mbus_framefmt *fmt)\n+\t\t\t       struct v4l2_mbus_framefmt *fmt, int pad_id)\n {\n \tstruct v4l2_subdev_format sd_fmt = {\n \t\t.which = V4L2_SUBDEV_FORMAT_ACTIVE,\n+\t\t.pad = pad_id\n \t};\n \tint ret;\n \n@@ -598,29 +603,30 @@ static int unicam_calc_format_size_bpl(s\n \treturn 0;\n }\n \n-static int unicam_reset_format(struct unicam_device *dev)\n+static int unicam_reset_format(struct unicam_node *node)\n {\n+\tstruct unicam_device *dev = node->dev;\n \tstruct v4l2_mbus_framefmt mbus_fmt;\n \tint ret;\n \n-\tret = __subdev_get_format(dev, &mbus_fmt);\n+\tret = __subdev_get_format(dev, &mbus_fmt, node->pad_id);\n \tif (ret) {\n \t\tunicam_err(dev, \"Failed to get_format - ret %d\\n\", ret);\n \t\treturn ret;\n \t}\n \n-\tif (mbus_fmt.code != dev->fmt->code) {\n+\tif (mbus_fmt.code != dev->node[0].fmt->code) {\n \t\tunicam_err(dev, \"code mismatch - fmt->code %08x, mbus_fmt.code %08x\\n\",\n-\t\t\t   dev->fmt->code, mbus_fmt.code);\n+\t\t\t   dev->node[0].fmt->code, mbus_fmt.code);\n \t\treturn ret;\n \t}\n \n-\tv4l2_fill_pix_format(&dev->v_fmt.fmt.pix, &mbus_fmt);\n-\tdev->v_fmt.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;\n+\tv4l2_fill_pix_format(&dev->node[0].v_fmt.fmt.pix, &mbus_fmt);\n+\tdev->node[0].v_fmt.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;\n \n-\tunicam_calc_format_size_bpl(dev, dev->fmt, &dev->v_fmt);\n+\tunicam_calc_format_size_bpl(dev, dev->node[0].fmt, &dev->node[0].v_fmt);\n \n-\tdev->m_fmt = mbus_fmt;\n+\tdev->node[0].m_fmt = mbus_fmt;\n \n \treturn 0;\n }\n@@ -635,14 +641,14 @@ static void unicam_wr_dma_addr(struct un\n \n \treg_write(&dev->cfg, UNICAM_IBSA0, dmaaddr);\n \treg_write(&dev->cfg, UNICAM_IBEA0,\n-\t\t  dmaaddr + dev->v_fmt.fmt.pix.sizeimage);\n+\t\t  dmaaddr + dev->node[0].v_fmt.fmt.pix.sizeimage);\n }\n \n static inline unsigned int unicam_get_lines_done(struct unicam_device *dev)\n {\n \tdma_addr_t start_addr, cur_addr;\n-\tunsigned int stride = dev->v_fmt.fmt.pix.bytesperline;\n-\tstruct unicam_buffer *frm = dev->cur_frm;\n+\tunsigned int stride = dev->node[0].v_fmt.fmt.pix.bytesperline;\n+\tstruct unicam_buffer *frm = dev->node[0].cur_frm;\n \n \tif (!frm)\n \t\treturn 0;\n@@ -654,12 +660,12 @@ static inline unsigned int unicam_get_li\n \n static inline void unicam_schedule_next_buffer(struct unicam_device *dev)\n {\n-\tstruct unicam_dmaqueue *dma_q = &dev->dma_queue;\n+\tstruct unicam_dmaqueue *dma_q = &dev->node[0].dma_queue;\n \tstruct unicam_buffer *buf;\n \tdma_addr_t addr;\n \n \tbuf = list_entry(dma_q->active.next, struct unicam_buffer, list);\n-\tdev->next_frm = buf;\n+\tdev->node[0].next_frm = buf;\n \tlist_del(&buf->list);\n \n \taddr = vb2_dma_contig_plane_dma_addr(&buf->vb.vb2_buf, 0);\n@@ -668,11 +674,11 @@ static inline void unicam_schedule_next_\n \n static inline void unicam_process_buffer_complete(struct unicam_device *dev)\n {\n-\tdev->cur_frm->vb.field = dev->m_fmt.field;\n-\tdev->cur_frm->vb.sequence = dev->sequence++;\n+\tdev->node[0].cur_frm->vb.field = dev->node[0].m_fmt.field;\n+\tdev->node[0].cur_frm->vb.sequence = dev->sequence++;\n \n-\tvb2_buffer_done(&dev->cur_frm->vb.vb2_buf, VB2_BUF_STATE_DONE);\n-\tdev->cur_frm = dev->next_frm;\n+\tvb2_buffer_done(&dev->node[0].cur_frm->vb.vb2_buf, VB2_BUF_STATE_DONE);\n+\tdev->node[0].cur_frm = dev->node[0].next_frm;\n }\n \n /*\n@@ -687,7 +693,7 @@ static irqreturn_t unicam_isr(int irq, v\n {\n \tstruct unicam_device *unicam = (struct unicam_device *)dev;\n \tstruct unicam_cfg *cfg = &unicam->cfg;\n-\tstruct unicam_dmaqueue *dma_q = &unicam->dma_queue;\n+\tstruct unicam_dmaqueue *dma_q = &unicam->node[0].dma_queue;\n \tunsigned int lines_done = unicam_get_lines_done(dev);\n \tunsigned int sequence = unicam->sequence;\n \tint ista, sta;\n@@ -720,8 +726,9 @@ static irqreturn_t unicam_isr(int irq, v\n \t\t * Timestamp is to be when the first data byte was captured,\n \t\t * aka frame start.\n \t\t */\n-\t\tif (unicam->cur_frm)\n-\t\t\tunicam->cur_frm->vb.vb2_buf.timestamp = ktime_get_ns();\n+\t\tif (unicam->node[0].cur_frm)\n+\t\t\tunicam->node[0].cur_frm->vb.vb2_buf.timestamp =\n+\t\t\t\tktime_get_ns();\n \t}\n \tif (ista & UNICAM_FEI || sta & UNICAM_PI0) {\n \t\t/*\n@@ -729,7 +736,8 @@ static irqreturn_t unicam_isr(int irq, v\n \t\t * stop the peripheral. Overwrite the frame we've just\n \t\t * captured instead.\n \t\t */\n-\t\tif (unicam->cur_frm && unicam->cur_frm != unicam->next_frm)\n+\t\tif (unicam->node[0].cur_frm &&\n+\t\t    unicam->node[0].cur_frm != unicam->node[0].next_frm)\n \t\t\tunicam_process_buffer_complete(unicam);\n \t}\n \n@@ -738,11 +746,11 @@ static irqreturn_t unicam_isr(int irq, v\n \t * already started.\n \t */\n \tif (ista & (UNICAM_FSI | UNICAM_LCI) && !(ista & UNICAM_FEI)) {\n-\t\tspin_lock(&unicam->dma_queue_lock);\n+\t\tspin_lock(&unicam->node[0].dma_queue_lock);\n \t\tif (!list_empty(&dma_q->active) &&\n-\t\t    unicam->cur_frm == unicam->next_frm)\n+\t\t    unicam->node[0].cur_frm == unicam->node[0].next_frm)\n \t\t\tunicam_schedule_next_buffer(unicam);\n-\t\tspin_unlock(&unicam->dma_queue_lock);\n+\t\tspin_unlock(&unicam->node[0].dma_queue_lock);\n \t}\n \n \tif (reg_read(&unicam->cfg, UNICAM_ICTL) & UNICAM_FCM) {\n@@ -756,7 +764,8 @@ static irqreturn_t unicam_isr(int irq, v\n static int unicam_querycap(struct file *file, void *priv,\n \t\t\t   struct v4l2_capability *cap)\n {\n-\tstruct unicam_device *dev = video_drvdata(file);\n+\tstruct unicam_node *node = video_drvdata(file);\n+\tstruct unicam_device *dev = node->dev;\n \n \tstrlcpy(cap->driver, UNICAM_MODULE_NAME, sizeof(cap->driver));\n \tstrlcpy(cap->card, UNICAM_MODULE_NAME, sizeof(cap->card));\n@@ -770,7 +779,8 @@ static int unicam_querycap(struct file *\n static int unicam_enum_fmt_vid_cap(struct file *file, void  *priv,\n \t\t\t\t   struct v4l2_fmtdesc *f)\n {\n-\tstruct unicam_device *dev = video_drvdata(file);\n+\tstruct unicam_node *node = video_drvdata(file);\n+\tstruct unicam_device *dev = node->dev;\n \tstruct v4l2_subdev_mbus_code_enum mbus_code;\n \tconst struct unicam_fmt *fmt = NULL;\n \tint index = 0;\n@@ -815,9 +825,9 @@ static int unicam_enum_fmt_vid_cap(struc\n static int unicam_g_fmt_vid_cap(struct file *file, void *priv,\n \t\t\t\tstruct v4l2_format *f)\n {\n-\tstruct unicam_device *dev = video_drvdata(file);\n+\tstruct unicam_node *node = video_drvdata(file);\n \n-\t*f = dev->v_fmt;\n+\t*f = node->v_fmt;\n \n \treturn 0;\n }\n@@ -859,9 +869,11 @@ const struct unicam_fmt *get_first_suppo\n static int unicam_try_fmt_vid_cap(struct file *file, void *priv,\n \t\t\t\t  struct v4l2_format *f)\n {\n-\tstruct unicam_device *dev = video_drvdata(file);\n+\tstruct unicam_node *node = video_drvdata(file);\n+\tstruct unicam_device *dev = node->dev;\n \tstruct v4l2_subdev_format sd_fmt = {\n \t\t.which = V4L2_SUBDEV_FORMAT_TRY,\n+\t\t.pad = 0\n \t};\n \tstruct v4l2_mbus_framefmt *mbus_fmt = &sd_fmt.format;\n \tconst struct unicam_fmt *fmt;\n@@ -939,8 +951,9 @@ static int unicam_try_fmt_vid_cap(struct\n static int unicam_s_fmt_vid_cap(struct file *file, void *priv,\n \t\t\t\tstruct v4l2_format *f)\n {\n-\tstruct unicam_device *dev = video_drvdata(file);\n-\tstruct vb2_queue *q = &dev->buffer_queue;\n+\tstruct unicam_node *node = video_drvdata(file);\n+\tstruct unicam_device *dev = node->dev;\n+\tstruct vb2_queue *q = &node->buffer_queue;\n \tstruct v4l2_mbus_framefmt mbus_fmt = {0};\n \tconst struct unicam_fmt *fmt;\n \tint ret;\n@@ -985,17 +998,18 @@ static int unicam_s_fmt_vid_cap(struct f\n \t\treturn -EINVAL;\n \t}\n \n-\tdev->fmt = fmt;\n-\tdev->v_fmt.fmt.pix.pixelformat = f->fmt.pix.pixelformat;\n-\tdev->v_fmt.fmt.pix.bytesperline = f->fmt.pix.bytesperline;\n-\tunicam_reset_format(dev);\n-\n-\tunicam_dbg(3, dev, \"%s %dx%d, mbus_fmt 0x%08X, V4L2 pix 0x%08X.\\n\",\n-\t\t   __func__, dev->v_fmt.fmt.pix.width,\n-\t\t   dev->v_fmt.fmt.pix.height, mbus_fmt.code,\n-\t\t   dev->v_fmt.fmt.pix.pixelformat);\n+\tnode->fmt = fmt;\n+\tnode->v_fmt.fmt.pix.pixelformat = f->fmt.pix.pixelformat;\n+\tnode->v_fmt.fmt.pix.bytesperline = f->fmt.pix.bytesperline;\n+\tunicam_reset_format(node);\n+\n+\tunicam_dbg(3, dev,\n+\t\t   \"%s %dx%d, mbus_fmt 0x%08X, V4L2 pix 0x%08X.\\n\",\n+\t\t   __func__, node->v_fmt.fmt.pix.width,\n+\t\t   node->v_fmt.fmt.pix.height, mbus_fmt.code,\n+\t\t   node->v_fmt.fmt.pix.pixelformat);\n \n-\t*f = dev->v_fmt;\n+\t*f = node->v_fmt;\n \n \treturn 0;\n }\n@@ -1006,8 +1020,9 @@ static int unicam_queue_setup(struct vb2\n \t\t\t      unsigned int sizes[],\n \t\t\t      struct device *alloc_devs[])\n {\n-\tstruct unicam_device *dev = vb2_get_drv_priv(vq);\n-\tunsigned int size = dev->v_fmt.fmt.pix.sizeimage;\n+\tstruct unicam_node *node = vb2_get_drv_priv(vq);\n+\tstruct unicam_device *dev = node->dev;\n+\tunsigned int size = node->v_fmt.fmt.pix.sizeimage;\n \n \tif (vq->num_buffers + *nbuffers < 3)\n \t\t*nbuffers = 3 - vq->num_buffers;\n@@ -1029,15 +1044,16 @@ static int unicam_queue_setup(struct vb2\n \n static int unicam_buffer_prepare(struct vb2_buffer *vb)\n {\n-\tstruct unicam_device *dev = vb2_get_drv_priv(vb->vb2_queue);\n+\tstruct unicam_node *node = vb2_get_drv_priv(vb->vb2_queue);\n+\tstruct unicam_device *dev = node->dev;\n \tstruct unicam_buffer *buf = container_of(vb, struct unicam_buffer,\n \t\t\t\t\t      vb.vb2_buf);\n \tunsigned long size;\n \n-\tif (WARN_ON(!dev->fmt))\n+\tif (WARN_ON(!node->fmt))\n \t\treturn -EINVAL;\n \n-\tsize = dev->v_fmt.fmt.pix.sizeimage;\n+\tsize = node->v_fmt.fmt.pix.sizeimage;\n \tif (vb2_plane_size(vb, 0) < size) {\n \t\tunicam_err(dev, \"data will not fit into plane (%lu < %lu)\\n\",\n \t\t\t   vb2_plane_size(vb, 0), size);\n@@ -1050,15 +1066,15 @@ static int unicam_buffer_prepare(struct\n \n static void unicam_buffer_queue(struct vb2_buffer *vb)\n {\n-\tstruct unicam_device *dev = vb2_get_drv_priv(vb->vb2_queue);\n+\tstruct unicam_node *node = vb2_get_drv_priv(vb->vb2_queue);\n \tstruct unicam_buffer *buf = container_of(vb, struct unicam_buffer,\n \t\t\t\t\t      vb.vb2_buf);\n-\tstruct unicam_dmaqueue *dma_queue = &dev->dma_queue;\n+\tstruct unicam_dmaqueue *dma_queue = &node->dma_queue;\n \tunsigned long flags = 0;\n \n-\tspin_lock_irqsave(&dev->dma_queue_lock, flags);\n+\tspin_lock_irqsave(&node->dma_queue_lock, flags);\n \tlist_add_tail(&buf->list, &dma_queue->active);\n-\tspin_unlock_irqrestore(&dev->dma_queue_lock, flags);\n+\tspin_unlock_irqrestore(&node->dma_queue_lock, flags);\n }\n \n static void unicam_set_packing_config(struct unicam_device *dev)\n@@ -1066,11 +1082,12 @@ static void unicam_set_packing_config(st\n \tint pack, unpack;\n \tu32 val;\n \n-\tif (dev->v_fmt.fmt.pix.pixelformat == dev->fmt->fourcc) {\n+\tif (dev->node[0].v_fmt.fmt.pix.pixelformat ==\n+\t    dev->node[0].fmt->fourcc) {\n \t\tunpack = UNICAM_PUM_NONE;\n \t\tpack = UNICAM_PPM_NONE;\n \t} else {\n-\t\tswitch (dev->fmt->depth) {\n+\t\tswitch (dev->node[0].fmt->depth) {\n \t\tcase 8:\n \t\t\tunpack = UNICAM_PUM_UNPACK8;\n \t\t\tbreak;\n@@ -1108,17 +1125,17 @@ static void unicam_cfg_image_id(struct u\n \tif (dev->bus_type == V4L2_MBUS_CSI2_DPHY) {\n \t\t/* CSI2 mode */\n \t\treg_write(cfg, UNICAM_IDI0,\n-\t\t\t  (dev->virtual_channel << 6) | dev->fmt->csi_dt);\n+\t\t\t(dev->virtual_channel << 6) | dev->node[0].fmt->csi_dt);\n \t} else {\n \t\t/* CCP2 mode */\n-\t\treg_write(cfg, UNICAM_IDI0, (0x80 | dev->fmt->csi_dt));\n+\t\treg_write(cfg, UNICAM_IDI0, (0x80 | dev->node[0].fmt->csi_dt));\n \t}\n }\n \n static void unicam_start_rx(struct unicam_device *dev, unsigned long addr)\n {\n \tstruct unicam_cfg *cfg = &dev->cfg;\n-\tint line_int_freq = dev->v_fmt.fmt.pix.height >> 2;\n+\tint line_int_freq = dev->node[0].v_fmt.fmt.pix.height >> 2;\n \tunsigned int i;\n \tu32 val;\n \n@@ -1266,7 +1283,8 @@ static void unicam_start_rx(struct unica\n \t\treg_write(cfg, UNICAM_DAT3, val);\n \t}\n \n-\treg_write(&dev->cfg, UNICAM_IBLS, dev->v_fmt.fmt.pix.bytesperline);\n+\treg_write(&dev->cfg, UNICAM_IBLS,\n+\t\t  dev->node[0].v_fmt.fmt.pix.bytesperline);\n \tunicam_wr_dma_addr(dev, addr);\n \tunicam_set_packing_config(dev);\n \tunicam_cfg_image_id(dev);\n@@ -1327,21 +1345,22 @@ static void unicam_disable(struct unicam\n \n static int unicam_start_streaming(struct vb2_queue *vq, unsigned int count)\n {\n-\tstruct unicam_device *dev = vb2_get_drv_priv(vq);\n-\tstruct unicam_dmaqueue *dma_q = &dev->dma_queue;\n+\tstruct unicam_node *node = vb2_get_drv_priv(vq);\n+\tstruct unicam_device *dev = node->dev;\n+\tstruct unicam_dmaqueue *dma_q = &node->dma_queue;\n \tstruct unicam_buffer *buf, *tmp;\n \tunsigned long addr = 0;\n \tunsigned long flags;\n \tint ret;\n \n-\tspin_lock_irqsave(&dev->dma_queue_lock, flags);\n+\tspin_lock_irqsave(&node->dma_queue_lock, flags);\n \tbuf = list_entry(dma_q->active.next, struct unicam_buffer, list);\n-\tdev->cur_frm = buf;\n-\tdev->next_frm = buf;\n+\tnode->cur_frm = buf;\n+\tnode->next_frm = buf;\n \tlist_del(&buf->list);\n-\tspin_unlock_irqrestore(&dev->dma_queue_lock, flags);\n+\tspin_unlock_irqrestore(&node->dma_queue_lock, flags);\n \n-\taddr = vb2_dma_contig_plane_dma_addr(&dev->cur_frm->vb.vb2_buf, 0);\n+\taddr = vb2_dma_contig_plane_dma_addr(&node->cur_frm->vb.vb2_buf, 0);\n \tdev->sequence = 0;\n \n \tret = unicam_runtime_get(dev);\n@@ -1411,20 +1430,21 @@ err_release_buffers:\n \t\tlist_del(&buf->list);\n \t\tvb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_QUEUED);\n \t}\n-\tif (dev->cur_frm != dev->next_frm)\n-\t\tvb2_buffer_done(&dev->next_frm->vb.vb2_buf,\n+\tif (node->cur_frm != node->next_frm)\n+\t\tvb2_buffer_done(&node->next_frm->vb.vb2_buf,\n \t\t\t\tVB2_BUF_STATE_QUEUED);\n-\tvb2_buffer_done(&dev->cur_frm->vb.vb2_buf, VB2_BUF_STATE_QUEUED);\n-\tdev->next_frm = NULL;\n-\tdev->cur_frm = NULL;\n+\tvb2_buffer_done(&node->cur_frm->vb.vb2_buf, VB2_BUF_STATE_QUEUED);\n+\tnode->next_frm = NULL;\n+\tnode->cur_frm = NULL;\n \n \treturn ret;\n }\n \n static void unicam_stop_streaming(struct vb2_queue *vq)\n {\n-\tstruct unicam_device *dev = vb2_get_drv_priv(vq);\n-\tstruct unicam_dmaqueue *dma_q = &dev->dma_queue;\n+\tstruct unicam_node *node = vb2_get_drv_priv(vq);\n+\tstruct unicam_device *dev = node->dev;\n+\tstruct unicam_dmaqueue *dma_q = &node->dma_queue;\n \tstruct unicam_buffer *buf, *tmp;\n \tunsigned long flags;\n \n@@ -1434,22 +1454,24 @@ static void unicam_stop_streaming(struct\n \tunicam_disable(dev);\n \n \t/* Release all active buffers */\n-\tspin_lock_irqsave(&dev->dma_queue_lock, flags);\n+\tspin_lock_irqsave(&node->dma_queue_lock, flags);\n \tlist_for_each_entry_safe(buf, tmp, &dma_q->active, list) {\n \t\tlist_del(&buf->list);\n \t\tvb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);\n \t}\n \n-\tif (dev->cur_frm == dev->next_frm) {\n-\t\tvb2_buffer_done(&dev->cur_frm->vb.vb2_buf, VB2_BUF_STATE_ERROR);\n+\tif (node->cur_frm == node->next_frm) {\n+\t\tvb2_buffer_done(&node->cur_frm->vb.vb2_buf,\n+\t\t\t\tVB2_BUF_STATE_ERROR);\n \t} else {\n-\t\tvb2_buffer_done(&dev->cur_frm->vb.vb2_buf, VB2_BUF_STATE_ERROR);\n-\t\tvb2_buffer_done(&dev->next_frm->vb.vb2_buf,\n+\t\tvb2_buffer_done(&node->cur_frm->vb.vb2_buf,\n+\t\t\t\tVB2_BUF_STATE_ERROR);\n+\t\tvb2_buffer_done(&node->next_frm->vb.vb2_buf,\n \t\t\t\tVB2_BUF_STATE_ERROR);\n \t}\n-\tdev->cur_frm = NULL;\n-\tdev->next_frm = NULL;\n-\tspin_unlock_irqrestore(&dev->dma_queue_lock, flags);\n+\tnode->cur_frm = NULL;\n+\tnode->next_frm = NULL;\n+\tspin_unlock_irqrestore(&node->dma_queue_lock, flags);\n \n \tclk_disable_unprepare(dev->clock);\n \tunicam_runtime_put(dev);\n@@ -1458,7 +1480,8 @@ static void unicam_stop_streaming(struct\n static int unicam_enum_input(struct file *file, void *priv,\n \t\t\t     struct v4l2_input *inp)\n {\n-\tstruct unicam_device *dev = video_drvdata(file);\n+\tstruct unicam_node *node = video_drvdata(file);\n+\tstruct unicam_device *dev = node->dev;\n \n \tif (inp->index != 0)\n \t\treturn -EINVAL;\n@@ -1506,21 +1529,24 @@ static int unicam_s_input(struct file *f\n static int unicam_querystd(struct file *file, void *priv,\n \t\t\t   v4l2_std_id *std)\n {\n-\tstruct unicam_device *dev = video_drvdata(file);\n+\tstruct unicam_node *node = video_drvdata(file);\n+\tstruct unicam_device *dev = node->dev;\n \n \treturn v4l2_subdev_call(dev->sensor, video, querystd, std);\n }\n \n static int unicam_g_std(struct file *file, void *priv, v4l2_std_id *std)\n {\n-\tstruct unicam_device *dev = video_drvdata(file);\n+\tstruct unicam_node *node = video_drvdata(file);\n+\tstruct unicam_device *dev = node->dev;\n \n \treturn v4l2_subdev_call(dev->sensor, video, g_std, std);\n }\n \n static int unicam_s_std(struct file *file, void *priv, v4l2_std_id std)\n {\n-\tstruct unicam_device *dev = video_drvdata(file);\n+\tstruct unicam_node *node = video_drvdata(file);\n+\tstruct unicam_device *dev = node->dev;\n \tint ret;\n \tv4l2_std_id current_std;\n \n@@ -1531,29 +1557,31 @@ static int unicam_s_std(struct file *fil\n \tif (std == current_std)\n \t\treturn 0;\n \n-\tif (vb2_is_busy(&dev->buffer_queue))\n+\tif (vb2_is_busy(&node->buffer_queue))\n \t\treturn -EBUSY;\n \n \tret = v4l2_subdev_call(dev->sensor, video, s_std, std);\n \n \t/* Force recomputation of bytesperline */\n-\tdev->v_fmt.fmt.pix.bytesperline = 0;\n+\tnode->v_fmt.fmt.pix.bytesperline = 0;\n \n-\tunicam_reset_format(dev);\n+\tunicam_reset_format(node);\n \n \treturn ret;\n }\n \n static int unicam_s_edid(struct file *file, void *priv, struct v4l2_edid *edid)\n {\n-\tstruct unicam_device *dev = video_drvdata(file);\n+\tstruct unicam_node *node = video_drvdata(file);\n+\tstruct unicam_device *dev = node->dev;\n \n \treturn v4l2_subdev_call(dev->sensor, pad, set_edid, edid);\n }\n \n static int unicam_g_edid(struct file *file, void *priv, struct v4l2_edid *edid)\n {\n-\tstruct unicam_device *dev = video_drvdata(file);\n+\tstruct unicam_node *node = video_drvdata(file);\n+\tstruct unicam_device *dev = node->dev;\n \n \treturn v4l2_subdev_call(dev->sensor, pad, get_edid, edid);\n }\n@@ -1561,7 +1589,8 @@ static int unicam_g_edid(struct file *fi\n static int unicam_enum_framesizes(struct file *file, void *priv,\n \t\t\t\t  struct v4l2_frmsizeenum *fsize)\n {\n-\tstruct unicam_device *dev = video_drvdata(file);\n+\tstruct unicam_node *node = video_drvdata(file);\n+\tstruct unicam_device *dev = node->dev;\n \tconst struct unicam_fmt *fmt;\n \tstruct v4l2_subdev_frame_size_enum fse;\n \tint ret;\n@@ -1596,7 +1625,8 @@ static int unicam_enum_framesizes(struct\n static int unicam_enum_frameintervals(struct file *file, void *priv,\n \t\t\t\t      struct v4l2_frmivalenum *fival)\n {\n-\tstruct unicam_device *dev = video_drvdata(file);\n+\tstruct unicam_node *node = video_drvdata(file);\n+\tstruct unicam_device *dev = node->dev;\n \tconst struct unicam_fmt *fmt;\n \tstruct v4l2_subdev_frame_interval_enum fie = {\n \t\t.index = fival->index,\n@@ -1624,14 +1654,16 @@ static int unicam_enum_frameintervals(st\n \n static int unicam_g_parm(struct file *file, void *fh, struct v4l2_streamparm *a)\n {\n-\tstruct unicam_device *dev = video_drvdata(file);\n+\tstruct unicam_node *node = video_drvdata(file);\n+\tstruct unicam_device *dev = node->dev;\n \n \treturn v4l2_g_parm_cap(video_devdata(file), dev->sensor, a);\n }\n \n static int unicam_s_parm(struct file *file, void *fh, struct v4l2_streamparm *a)\n {\n-\tstruct unicam_device *dev = video_drvdata(file);\n+\tstruct unicam_node *node = video_drvdata(file);\n+\tstruct unicam_device *dev = node->dev;\n \n \treturn v4l2_s_parm_cap(video_devdata(file), dev->sensor, a);\n }\n@@ -1639,7 +1671,8 @@ static int unicam_s_parm(struct file *fi\n static int unicam_g_dv_timings(struct file *file, void *priv,\n \t\t\t       struct v4l2_dv_timings *timings)\n {\n-\tstruct unicam_device *dev = video_drvdata(file);\n+\tstruct unicam_node *node = video_drvdata(file);\n+\tstruct unicam_device *dev = node->dev;\n \n \treturn v4l2_subdev_call(dev->sensor, video, g_dv_timings, timings);\n }\n@@ -1647,7 +1680,8 @@ static int unicam_g_dv_timings(struct fi\n static int unicam_s_dv_timings(struct file *file, void *priv,\n \t\t\t       struct v4l2_dv_timings *timings)\n {\n-\tstruct unicam_device *dev = video_drvdata(file);\n+\tstruct unicam_node *node = video_drvdata(file);\n+\tstruct unicam_device *dev = node->dev;\n \tstruct v4l2_dv_timings current_timings;\n \tint ret;\n \n@@ -1657,15 +1691,15 @@ static int unicam_s_dv_timings(struct fi\n \tif (v4l2_match_dv_timings(timings, &current_timings, 0, false))\n \t\treturn 0;\n \n-\tif (vb2_is_busy(&dev->buffer_queue))\n+\tif (vb2_is_busy(&node->buffer_queue))\n \t\treturn -EBUSY;\n \n \tret = v4l2_subdev_call(dev->sensor, video, s_dv_timings, timings);\n \n \t/* Force recomputation of bytesperline */\n-\tdev->v_fmt.fmt.pix.bytesperline = 0;\n+\tnode->v_fmt.fmt.pix.bytesperline = 0;\n \n-\tunicam_reset_format(dev);\n+\tunicam_reset_format(node);\n \n \treturn ret;\n }\n@@ -1673,7 +1707,8 @@ static int unicam_s_dv_timings(struct fi\n static int unicam_query_dv_timings(struct file *file, void *priv,\n \t\t\t\t   struct v4l2_dv_timings *timings)\n {\n-\tstruct unicam_device *dev = video_drvdata(file);\n+\tstruct unicam_node *node = video_drvdata(file);\n+\tstruct unicam_device *dev = node->dev;\n \n \treturn v4l2_subdev_call(dev->sensor, video, query_dv_timings, timings);\n }\n@@ -1681,7 +1716,8 @@ static int unicam_query_dv_timings(struc\n static int unicam_enum_dv_timings(struct file *file, void *priv,\n \t\t\t\t  struct v4l2_enum_dv_timings *timings)\n {\n-\tstruct unicam_device *dev = video_drvdata(file);\n+\tstruct unicam_node *node = video_drvdata(file);\n+\tstruct unicam_device *dev = node->dev;\n \n \treturn v4l2_subdev_call(dev->sensor, pad, enum_dv_timings, timings);\n }\n@@ -1689,7 +1725,8 @@ static int unicam_enum_dv_timings(struct\n static int unicam_dv_timings_cap(struct file *file, void *priv,\n \t\t\t\t struct v4l2_dv_timings_cap *cap)\n {\n-\tstruct unicam_device *dev = video_drvdata(file);\n+\tstruct unicam_node *node = video_drvdata(file);\n+\tstruct unicam_device *dev = node->dev;\n \n \treturn v4l2_subdev_call(dev->sensor, pad, dv_timings_cap, cap);\n }\n@@ -1707,7 +1744,8 @@ static int unicam_subscribe_event(struct\n \n static int unicam_log_status(struct file *file, void *fh)\n {\n-\tstruct unicam_device *dev = video_drvdata(file);\n+\tstruct unicam_node *node = video_drvdata(file);\n+\tstruct unicam_device *dev = node->dev;\n \tstruct unicam_cfg *cfg = &dev->cfg;\n \tu32 reg;\n \n@@ -1716,10 +1754,10 @@ static int unicam_log_status(struct file\n \n \tunicam_info(dev, \"-----Receiver status-----\\n\");\n \tunicam_info(dev, \"V4L2 width/height:   %ux%u\\n\",\n-\t\t    dev->v_fmt.fmt.pix.width, dev->v_fmt.fmt.pix.height);\n-\tunicam_info(dev, \"Mediabus format:     %08x\\n\", dev->fmt->code);\n+\t\t    node->v_fmt.fmt.pix.width, node->v_fmt.fmt.pix.height);\n+\tunicam_info(dev, \"Mediabus format:     %08x\\n\", node->fmt->code);\n \tunicam_info(dev, \"V4L2 format:         %08x\\n\",\n-\t\t    dev->v_fmt.fmt.pix.pixelformat);\n+\t\t    node->v_fmt.fmt.pix.pixelformat);\n \treg = reg_read(&dev->cfg, UNICAM_IPIPE);\n \tunicam_info(dev, \"Unpacking/packing:   %u / %u\\n\",\n \t\t    get_field(reg, UNICAM_PUM_MASK),\n@@ -1744,7 +1782,7 @@ static void unicam_notify(struct v4l2_su\n \n \tswitch (notification) {\n \tcase V4L2_DEVICE_NOTIFY_EVENT:\n-\t\tv4l2_event_queue(&dev->video_dev, arg);\n+\t\tv4l2_event_queue(&dev->node[0].video_dev, arg);\n \t\tbreak;\n \tdefault:\n \t\tbreak;\n@@ -1767,10 +1805,11 @@ static const struct vb2_ops unicam_video\n  */\n static int unicam_open(struct file *file)\n {\n-\tstruct unicam_device *dev = video_drvdata(file);\n+\tstruct unicam_node *node = video_drvdata(file);\n+\tstruct unicam_device *dev = node->dev;\n \tint ret;\n \n-\tmutex_lock(&dev->lock);\n+\tmutex_lock(&node->lock);\n \n \tret = v4l2_fh_open(file);\n \tif (ret) {\n@@ -1790,18 +1829,19 @@ static int unicam_open(struct file *file\n \tret = 0;\n \n unlock:\n-\tmutex_unlock(&dev->lock);\n+\tmutex_unlock(&node->lock);\n \treturn ret;\n }\n \n static int unicam_release(struct file *file)\n {\n-\tstruct unicam_device *dev = video_drvdata(file);\n+\tstruct unicam_node *node = video_drvdata(file);\n+\tstruct unicam_device *dev = node->dev;\n \tstruct v4l2_subdev *sd = dev->sensor;\n \tbool fh_singular;\n \tint ret;\n \n-\tmutex_lock(&dev->lock);\n+\tmutex_lock(&node->lock);\n \n \tfh_singular = v4l2_fh_is_singular_file(file);\n \n@@ -1810,7 +1850,7 @@ static int unicam_release(struct file *f\n \tif (fh_singular)\n \t\tv4l2_subdev_call(sd, core, s_power, 0);\n \n-\tmutex_unlock(&dev->lock);\n+\tmutex_unlock(&node->lock);\n \n \treturn ret;\n }\n@@ -1892,7 +1932,8 @@ unicam_async_bound(struct v4l2_async_not\n \treturn 0;\n }\n \n-static int unicam_probe_complete(struct unicam_device *unicam)\n+static int register_node(struct unicam_device *unicam, struct unicam_node *node,\n+\t\t\t enum v4l2_buf_type type, int pad_id)\n {\n \tstruct video_device *vdev;\n \tstruct vb2_queue *q;\n@@ -1900,15 +1941,7 @@ static int unicam_probe_complete(struct\n \tconst struct unicam_fmt *fmt;\n \tint ret;\n \n-\tv4l2_set_subdev_hostdata(unicam->sensor, unicam);\n-\n-\tunicam->v4l2_dev.notify = unicam_notify;\n-\n-\tunicam->sensor_config = v4l2_subdev_alloc_pad_config(unicam->sensor);\n-\tif (!unicam->sensor_config)\n-\t\treturn -ENOMEM;\n-\n-\tret = __subdev_get_format(unicam, &mbus_fmt);\n+\tret = __subdev_get_format(unicam, &mbus_fmt, pad_id);\n \tif (ret) {\n \t\tunicam_err(unicam, \"Failed to get_format - ret %d\\n\", ret);\n \t\treturn ret;\n@@ -1938,14 +1971,15 @@ static int unicam_probe_complete(struct\n \t\t\treturn -EINVAL;\n \t}\n \n-\tunicam->fmt = fmt;\n+\tnode->pad_id = pad_id;\n+\tnode->fmt = fmt;\n \tif (fmt->fourcc)\n-\t\tunicam->v_fmt.fmt.pix.pixelformat = fmt->fourcc;\n+\t\tnode->v_fmt.fmt.pix.pixelformat = fmt->fourcc;\n \telse\n-\t\tunicam->v_fmt.fmt.pix.pixelformat = fmt->repacked_fourcc;\n+\t\tnode->v_fmt.fmt.pix.pixelformat = fmt->repacked_fourcc;\n \n \t/* Read current subdev format */\n-\tunicam_reset_format(unicam);\n+\tunicam_reset_format(node);\n \n \tif (v4l2_subdev_has_op(unicam->sensor, video, s_std)) {\n \t\tv4l2_std_id tvnorms;\n@@ -1962,27 +1996,30 @@ static int unicam_probe_complete(struct\n \t\t\t\t       g_tvnorms, &tvnorms);\n \t\tif (WARN_ON(ret))\n \t\t\treturn -EINVAL;\n-\t\tunicam->video_dev.tvnorms |= tvnorms;\n+\t\tnode->video_dev.tvnorms |= tvnorms;\n \t}\n \n-\tspin_lock_init(&unicam->dma_queue_lock);\n-\tmutex_init(&unicam->lock);\n+\tspin_lock_init(&node->dma_queue_lock);\n+\tmutex_init(&node->lock);\n \n-\t/* Add controls from the subdevice */\n-\tret = v4l2_ctrl_add_handler(&unicam->ctrl_handler,\n-\t\t\t\t    unicam->sensor->ctrl_handler, NULL, true);\n-\tif (ret < 0)\n-\t\treturn ret;\n+\tif (type == V4L2_BUF_TYPE_VIDEO_CAPTURE) {\n+\t\t/* Add controls from the subdevice */\n+\t\tret = v4l2_ctrl_add_handler(&node->ctrl_handler,\n+\t\t\t\t\t    unicam->sensor->ctrl_handler, NULL,\n+\t\t\t\t\t    true);\n+\t\tif (ret < 0)\n+\t\t\treturn ret;\n+\t}\n \n-\tq = &unicam->buffer_queue;\n-\tq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;\n+\tq = &node->buffer_queue;\n+\tq->type = type;\n \tq->io_modes = VB2_MMAP | VB2_DMABUF | VB2_READ;\n-\tq->drv_priv = unicam;\n+\tq->drv_priv = node;\n \tq->ops = &unicam_video_qops;\n \tq->mem_ops = &vb2_dma_contig_memops;\n \tq->buf_struct_size = sizeof(struct unicam_buffer);\n \tq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;\n-\tq->lock = &unicam->lock;\n+\tq->lock = &node->lock;\n \tq->min_buffers_needed = 2;\n \tq->dev = &unicam->pdev->dev;\n \n@@ -1992,9 +2029,9 @@ static int unicam_probe_complete(struct\n \t\treturn ret;\n \t}\n \n-\tINIT_LIST_HEAD(&unicam->dma_queue.active);\n+\tINIT_LIST_HEAD(&node->dma_queue.active);\n \n-\tvdev = &unicam->video_dev;\n+\tvdev = &node->video_dev;\n \tstrlcpy(vdev->name, UNICAM_MODULE_NAME, sizeof(vdev->name));\n \tvdev->release = video_device_release_empty;\n \tvdev->fops = &unicam_fops;\n@@ -2002,69 +2039,113 @@ static int unicam_probe_complete(struct\n \tvdev->v4l2_dev = &unicam->v4l2_dev;\n \tvdev->vfl_dir = VFL_DIR_RX;\n \tvdev->queue = q;\n-\tvdev->lock = &unicam->lock;\n+\tvdev->lock = &node->lock;\n \tvdev->device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING |\n \t\t\t    V4L2_CAP_READWRITE;\n-\n \t/* If the source has no controls then remove our ctrl handler. */\n-\tif (list_empty(&unicam->ctrl_handler.ctrls))\n+\tif (list_empty(&node->ctrl_handler.ctrls))\n \t\tunicam->v4l2_dev.ctrl_handler = NULL;\n \n-\tvideo_set_drvdata(vdev, unicam);\n+\tnode->dev = unicam;\n+\tvideo_set_drvdata(vdev, node);\n \tvdev->entity.flags |= MEDIA_ENT_FL_DEFAULT;\n \n \tif (!v4l2_subdev_has_op(unicam->sensor, video, s_std)) {\n-\t\tv4l2_disable_ioctl(&unicam->video_dev, VIDIOC_S_STD);\n-\t\tv4l2_disable_ioctl(&unicam->video_dev, VIDIOC_G_STD);\n-\t\tv4l2_disable_ioctl(&unicam->video_dev, VIDIOC_ENUMSTD);\n+\t\tv4l2_disable_ioctl(&node->video_dev, VIDIOC_S_STD);\n+\t\tv4l2_disable_ioctl(&node->video_dev, VIDIOC_G_STD);\n+\t\tv4l2_disable_ioctl(&node->video_dev, VIDIOC_ENUMSTD);\n \t}\n \tif (!v4l2_subdev_has_op(unicam->sensor, video, querystd))\n-\t\tv4l2_disable_ioctl(&unicam->video_dev, VIDIOC_QUERYSTD);\n+\t\tv4l2_disable_ioctl(&node->video_dev, VIDIOC_QUERYSTD);\n \tif (!v4l2_subdev_has_op(unicam->sensor, video, s_dv_timings)) {\n-\t\tv4l2_disable_ioctl(&unicam->video_dev, VIDIOC_S_EDID);\n-\t\tv4l2_disable_ioctl(&unicam->video_dev, VIDIOC_G_EDID);\n-\t\tv4l2_disable_ioctl(&unicam->video_dev, VIDIOC_DV_TIMINGS_CAP);\n-\t\tv4l2_disable_ioctl(&unicam->video_dev, VIDIOC_G_DV_TIMINGS);\n-\t\tv4l2_disable_ioctl(&unicam->video_dev, VIDIOC_S_DV_TIMINGS);\n-\t\tv4l2_disable_ioctl(&unicam->video_dev, VIDIOC_ENUM_DV_TIMINGS);\n-\t\tv4l2_disable_ioctl(&unicam->video_dev, VIDIOC_QUERY_DV_TIMINGS);\n+\t\tv4l2_disable_ioctl(&node->video_dev, VIDIOC_S_EDID);\n+\t\tv4l2_disable_ioctl(&node->video_dev, VIDIOC_G_EDID);\n+\t\tv4l2_disable_ioctl(&node->video_dev, VIDIOC_DV_TIMINGS_CAP);\n+\t\tv4l2_disable_ioctl(&node->video_dev, VIDIOC_G_DV_TIMINGS);\n+\t\tv4l2_disable_ioctl(&node->video_dev, VIDIOC_S_DV_TIMINGS);\n+\t\tv4l2_disable_ioctl(&node->video_dev, VIDIOC_ENUM_DV_TIMINGS);\n+\t\tv4l2_disable_ioctl(&node->video_dev, VIDIOC_QUERY_DV_TIMINGS);\n \t}\n \tif (!v4l2_subdev_has_op(unicam->sensor, pad, enum_frame_interval))\n-\t\tv4l2_disable_ioctl(&unicam->video_dev,\n+\t\tv4l2_disable_ioctl(&node->video_dev,\n \t\t\t\t   VIDIOC_ENUM_FRAMEINTERVALS);\n \tif (!v4l2_subdev_has_op(unicam->sensor, video, g_frame_interval))\n-\t\tv4l2_disable_ioctl(&unicam->video_dev, VIDIOC_G_PARM);\n+\t\tv4l2_disable_ioctl(&node->video_dev, VIDIOC_G_PARM);\n \tif (!v4l2_subdev_has_op(unicam->sensor, video, s_frame_interval))\n-\t\tv4l2_disable_ioctl(&unicam->video_dev, VIDIOC_S_PARM);\n+\t\tv4l2_disable_ioctl(&node->video_dev, VIDIOC_S_PARM);\n \n \tif (!v4l2_subdev_has_op(unicam->sensor, pad, enum_frame_size))\n-\t\tv4l2_disable_ioctl(&unicam->video_dev, VIDIOC_ENUM_FRAMESIZES);\n+\t\tv4l2_disable_ioctl(&node->video_dev, VIDIOC_ENUM_FRAMESIZES);\n \n \tret = video_register_device(vdev, VFL_TYPE_VIDEO, -1);\n \tif (ret) {\n \t\tunicam_err(unicam, \"Unable to register video device.\\n\");\n \t\treturn ret;\n \t}\n+\tnode->registered = true;\n \n-\tret = v4l2_device_register_ro_subdev_nodes(&unicam->v4l2_dev);\n+\tret = media_create_pad_link(&unicam->sensor->entity,\n+\t\t\t\t    0, &node->video_dev.entity, 0,\n+\t\t\t\t    MEDIA_LNK_FL_ENABLED |\n+\t\t\t\t    MEDIA_LNK_FL_IMMUTABLE);\n+\tif (ret)\n+\t\tunicam_err(unicam, \"Unable to create pad links.\\n\");\n+\n+\treturn ret;\n+}\n+\n+static void unregister_nodes(struct unicam_device *unicam)\n+{\n+\tif (unicam->node[0].registered) {\n+\t\tvideo_unregister_device(&unicam->node[0].video_dev);\n+\t\tunicam->node[0].registered = false;\n+\t}\n+\tif (unicam->node[1].registered) {\n+\t\tvideo_unregister_device(&unicam->node[1].video_dev);\n+\t\tunicam->node[1].registered = false;\n+\t}\n+}\n+\n+static int unicam_probe_complete(struct unicam_device *unicam)\n+{\n+\tint ret;\n+\n+\tv4l2_set_subdev_hostdata(unicam->sensor, unicam);\n+\n+\tunicam->v4l2_dev.notify = unicam_notify;\n+\n+\tunicam->sensor_config = v4l2_subdev_alloc_pad_config(unicam->sensor);\n+\tif (!unicam->sensor_config)\n+\t\treturn -ENOMEM;\n+\n+\tret = register_node(unicam, &unicam->node[0],\n+\t\t\t    V4L2_BUF_TYPE_VIDEO_CAPTURE, 0);\n \tif (ret) {\n-\t\tunicam_err(unicam,\n-\t\t\t   \"Unable to register subdev nodes.\\n\");\n-\t\tvideo_unregister_device(&unicam->video_dev);\n-\t\treturn ret;\n+\t\tunicam_err(unicam, \"Unable to register subdev node 0.\\n\");\n+\t\tgoto unregister;\n+\t}\n+\tif (unicam->sensor->entity.num_pads >= 2) {\n+\t\tret = register_node(unicam, &unicam->node[1],\n+\t\t\t\t    V4L2_BUF_TYPE_META_CAPTURE, 1);\n+\t\tif (ret) {\n+\t\t\tunicam_err(unicam,\n+\t\t\t\t   \"Unable to register subdev node 1.\\n\");\n+\t\t\tgoto unregister;\n+\t\t}\n \t}\n \n-\tret = media_create_pad_link(&unicam->sensor->entity, 0,\n-\t\t\t\t    &unicam->video_dev.entity, 0,\n-\t\t\t\t    MEDIA_LNK_FL_ENABLED |\n-\t\t\t\t    MEDIA_LNK_FL_IMMUTABLE);\n+\tret = v4l2_device_register_ro_subdev_nodes(&unicam->v4l2_dev);\n \tif (ret) {\n-\t\tunicam_err(unicam, \"Unable to create pad links.\\n\");\n-\t\tvideo_unregister_device(&unicam->video_dev);\n-\t\treturn ret;\n+\t\tunicam_err(unicam, \"Unable to register subdev nodes.\\n\");\n+\t\tgoto unregister;\n \t}\n \n \treturn 0;\n+\n+unregister:\n+\tunregister_nodes(unicam);\n+\n+\treturn ret;\n }\n \n static int unicam_async_complete(struct v4l2_async_notifier *notifier)\n@@ -2274,7 +2355,8 @@ static int unicam_probe(struct platform_\n \t\t pdev->dev.driver->name, dev_name(&pdev->dev));\n \tunicam->mdev.hw_revision = 1;\n \n-\tmedia_entity_pads_init(&unicam->video_dev.entity, 1, &unicam->pad);\n+\tmedia_entity_pads_init(&unicam->node[0].video_dev.entity, 1,\n+\t\t\t       &unicam->node[0].pad);\n \tmedia_device_init(&unicam->mdev);\n \n \tunicam->v4l2_dev.mdev = &unicam->mdev;\n@@ -2294,7 +2376,7 @@ static int unicam_probe(struct platform_\n \t}\n \n \t/* Reserve space for the controls */\n-\thdl = &unicam->ctrl_handler;\n+\thdl = &unicam->node[0].ctrl_handler;\n \tret = v4l2_ctrl_handler_init(hdl, 16);\n \tif (ret < 0)\n \t\tgoto media_unregister;\n@@ -2335,9 +2417,9 @@ static int unicam_remove(struct platform\n \tpm_runtime_disable(&pdev->dev);\n \n \tv4l2_async_notifier_unregister(&unicam->notifier);\n-\tv4l2_ctrl_handler_free(&unicam->ctrl_handler);\n+\tv4l2_ctrl_handler_free(&unicam->node[0].ctrl_handler);\n \tv4l2_device_unregister(&unicam->v4l2_dev);\n-\tvideo_unregister_device(&unicam->video_dev);\n+\tunregister_nodes(unicam);\n \tif (unicam->sensor_config)\n \t\tv4l2_subdev_free_pad_config(unicam->sensor_config);\n \tmedia_device_unregister(&unicam->mdev);\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0213-media-bcm2835-unicam-Add-embedded-data-node.patch",
    "content": "From 0dae2f81f08fc6f8641e10b99c61e73314553d79 Mon Sep 17 00:00:00 2001\nFrom: Naushir Patuck <naush@raspberrypi.com>\nDate: Thu, 16 Apr 2020 11:35:41 +0100\nSubject: [PATCH] media: bcm2835-unicam: Add embedded data node.\n\nThis patch adds a new node in the bcm2835-unicam driver to support\nCSI-2 embedded data streams.  The subdevice is queried to see if\nembedded data is available from the sensor.\n\nSigned-off-by: Naushir Patuck <naush@raspberrypi.com>\n---\n .../media/platform/bcm2835/bcm2835-unicam.c   | 667 +++++++++++++-----\n 1 file changed, 474 insertions(+), 193 deletions(-)\n\n--- a/drivers/media/platform/bcm2835/bcm2835-unicam.c\n+++ b/drivers/media/platform/bcm2835/bcm2835-unicam.c\n@@ -109,8 +109,15 @@ MODULE_PARM_DESC(debug, \"Debug level 0-3\n /* Define a nominal minimum image size */\n #define MIN_WIDTH\t16\n #define MIN_HEIGHT\t16\n-/* Maximum number of simulataneous streams Uncaim can handle. */\n-#define MAX_NODES\t2\n+/* Default size of the embedded buffer */\n+#define UNICAM_EMBEDDED_SIZE\t8192\n+\n+enum pad_types {\n+\tIMAGE_PAD,\n+\tMETADATA_PAD,\n+\tMAX_NODES\n+};\n+\n /*\n  * struct unicam_fmt - Unicam media bus format information\n  * @pixelformat: V4L2 pixel format FCC identifier. 0 if n/a.\n@@ -327,6 +334,12 @@ static const struct unicam_fmt formats[]\n \t\t.depth\t\t= 12,\n \t\t.csi_dt\t\t= 0x2c,\n \t},\n+\t/* Embedded data format */\n+\t{\n+\t\t.fourcc\t\t= V4L2_META_FMT_SENSOR_DATA,\n+\t\t.code\t\t= MEDIA_BUS_FMT_SENSOR_DATA,\n+\t\t.depth\t\t= 8,\n+\t}\n };\n \n struct unicam_dmaqueue {\n@@ -348,7 +361,9 @@ struct unicam_cfg {\n #define MAX_POSSIBLE_PIX_FMTS (ARRAY_SIZE(formats))\n \n struct unicam_node {\n-\tbool registered;\n+\tint registered;\n+\tint open;\n+\tint streaming;\n \tunsigned int pad_id;\n \t/* Pointer pointing to current v4l2_buffer */\n \tstruct unicam_buffer *cur_frm;\n@@ -374,6 +389,7 @@ struct unicam_node {\n \tstruct unicam_device *dev;\n \tstruct media_pad pad;\n \tstruct v4l2_ctrl_handler ctrl_handler;\n+\tunsigned int embedded_lines;\n };\n \n struct unicam_device {\n@@ -401,8 +417,6 @@ struct unicam_device {\n \tstruct v4l2_subdev *sensor;\n \t/* Pad config for the sensor */\n \tstruct v4l2_subdev_pad_config *sensor_config;\n-\t/* current input at the sub device */\n-\tint current_input;\n \n \tunsigned int virtual_channel;\n \tenum v4l2_mbus_type bus_type;\n@@ -413,10 +427,7 @@ struct unicam_device {\n \tunsigned int bus_flags;\n \tunsigned int max_data_lanes;\n \tunsigned int active_data_lanes;\n-\n-\tstruct v4l2_rect crop;\n-\t/* Flag to denote that we are processing buffers */\n-\tint streaming;\n+\tbool sensor_embedded_data;\n \n \tstruct unicam_node node[MAX_NODES];\n };\n@@ -488,6 +499,7 @@ static int check_mbus_format(struct unic\n \tfor (i = 0; !ret && i < MAX_ENUM_MBUS_CODE; i++) {\n \t\tmemset(&mbus_code, 0, sizeof(mbus_code));\n \t\tmbus_code.index = i;\n+\t\tmbus_code.pad = IMAGE_PAD;\n \t\tmbus_code.which = V4L2_SUBDEV_FORMAT_ACTIVE;\n \n \t\tret = v4l2_subdev_call(dev->sensor, pad, enum_mbus_code,\n@@ -552,10 +564,11 @@ static int __subdev_get_format(struct un\n }\n \n static int __subdev_set_format(struct unicam_device *dev,\n-\t\t\t       struct v4l2_mbus_framefmt *fmt)\n+\t\t\t       struct v4l2_mbus_framefmt *fmt, int pad_id)\n {\n \tstruct v4l2_subdev_format sd_fmt = {\n \t\t.which = V4L2_SUBDEV_FORMAT_ACTIVE,\n+\t\t.pad = pad_id\n \t};\n \tint ret;\n \n@@ -566,8 +579,12 @@ static int __subdev_set_format(struct un\n \tif (ret < 0)\n \t\treturn ret;\n \n-\tunicam_dbg(1, dev, \"%s %dx%d code:%04x\\n\", __func__,\n-\t\t   fmt->width, fmt->height, fmt->code);\n+\tif (pad_id == IMAGE_PAD)\n+\t\tunicam_dbg(1, dev, \"%s %dx%d code:%04x\\n\", __func__, fmt->width,\n+\t\t\t   fmt->height, fmt->code);\n+\telse\n+\t\tunicam_dbg(1, dev, \"%s Embedded data code:%04x\\n\", __func__,\n+\t\t\t   sd_fmt.format.code);\n \n \treturn 0;\n }\n@@ -609,46 +626,70 @@ static int unicam_reset_format(struct un\n \tstruct v4l2_mbus_framefmt mbus_fmt;\n \tint ret;\n \n-\tret = __subdev_get_format(dev, &mbus_fmt, node->pad_id);\n-\tif (ret) {\n-\t\tunicam_err(dev, \"Failed to get_format - ret %d\\n\", ret);\n-\t\treturn ret;\n-\t}\n+\tif (dev->sensor_embedded_data || node->pad_id != METADATA_PAD) {\n+\t\tret = __subdev_get_format(dev, &mbus_fmt, node->pad_id);\n+\t\tif (ret) {\n+\t\t\tunicam_err(dev, \"Failed to get_format - ret %d\\n\", ret);\n+\t\t\treturn ret;\n+\t\t}\n \n-\tif (mbus_fmt.code != dev->node[0].fmt->code) {\n-\t\tunicam_err(dev, \"code mismatch - fmt->code %08x, mbus_fmt.code %08x\\n\",\n-\t\t\t   dev->node[0].fmt->code, mbus_fmt.code);\n-\t\treturn ret;\n+\t\tif (mbus_fmt.code != node->fmt->code) {\n+\t\t\tunicam_err(dev, \"code mismatch - fmt->code %08x, mbus_fmt.code %08x\\n\",\n+\t\t\t\t   node->fmt->code, mbus_fmt.code);\n+\t\t\treturn ret;\n+\t\t}\n \t}\n \n-\tv4l2_fill_pix_format(&dev->node[0].v_fmt.fmt.pix, &mbus_fmt);\n-\tdev->node[0].v_fmt.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;\n-\n-\tunicam_calc_format_size_bpl(dev, dev->node[0].fmt, &dev->node[0].v_fmt);\n-\n-\tdev->node[0].m_fmt = mbus_fmt;\n+\tif (node->pad_id == IMAGE_PAD) {\n+\t\tv4l2_fill_pix_format(&node->v_fmt.fmt.pix, &mbus_fmt);\n+\t\tnode->v_fmt.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;\n+\t\tunicam_calc_format_size_bpl(dev, node->fmt, &node->v_fmt);\n+\t} else {\n+\t\tnode->v_fmt.type = V4L2_BUF_TYPE_META_CAPTURE;\n+\t\tnode->v_fmt.fmt.meta.dataformat = V4L2_META_FMT_SENSOR_DATA;\n+\t\tif (dev->sensor_embedded_data) {\n+\t\t\tnode->v_fmt.fmt.meta.buffersize =\n+\t\t\t\t\tmbus_fmt.width * mbus_fmt.height;\n+\t\t\tnode->embedded_lines = mbus_fmt.height;\n+\t\t} else {\n+\t\t\tnode->v_fmt.fmt.meta.buffersize = UNICAM_EMBEDDED_SIZE;\n+\t\t\tnode->embedded_lines = 1;\n+\t\t}\n+\t}\n \n+\tnode->m_fmt = mbus_fmt;\n \treturn 0;\n }\n \n-static void unicam_wr_dma_addr(struct unicam_device *dev, dma_addr_t dmaaddr)\n+static void unicam_wr_dma_addr(struct unicam_device *dev, dma_addr_t dmaaddr,\n+\t\t\t       int pad_id)\n {\n+\tdma_addr_t endaddr;\n+\n \t/*\n \t * dmaaddr should be a 32-bit address with the top two bits set to 0x3\n \t * to signify uncached access through the Videocore memory controller.\n \t */\n \tBUG_ON((dmaaddr >> 30) != 0x3);\n \n-\treg_write(&dev->cfg, UNICAM_IBSA0, dmaaddr);\n-\treg_write(&dev->cfg, UNICAM_IBEA0,\n-\t\t  dmaaddr + dev->node[0].v_fmt.fmt.pix.sizeimage);\n+\tif (pad_id == IMAGE_PAD) {\n+\t\tendaddr = dmaaddr +\n+\t\t\t  dev->node[IMAGE_PAD].v_fmt.fmt.pix.sizeimage;\n+\t\treg_write(&dev->cfg, UNICAM_IBSA0, dmaaddr);\n+\t\treg_write(&dev->cfg, UNICAM_IBEA0, endaddr);\n+\t} else {\n+\t\tendaddr = dmaaddr +\n+\t\t\t  dev->node[METADATA_PAD].v_fmt.fmt.meta.buffersize;\n+\t\treg_write(&dev->cfg, UNICAM_DBSA0, dmaaddr);\n+\t\treg_write(&dev->cfg, UNICAM_DBEA0, endaddr);\n+\t}\n }\n \n static inline unsigned int unicam_get_lines_done(struct unicam_device *dev)\n {\n \tdma_addr_t start_addr, cur_addr;\n-\tunsigned int stride = dev->node[0].v_fmt.fmt.pix.bytesperline;\n-\tstruct unicam_buffer *frm = dev->node[0].cur_frm;\n+\tunsigned int stride = dev->node[IMAGE_PAD].v_fmt.fmt.pix.bytesperline;\n+\tstruct unicam_buffer *frm = dev->node[IMAGE_PAD].cur_frm;\n \n \tif (!frm)\n \t\treturn 0;\n@@ -658,27 +699,51 @@ static inline unsigned int unicam_get_li\n \treturn (unsigned int)(cur_addr - start_addr) / stride;\n }\n \n-static inline void unicam_schedule_next_buffer(struct unicam_device *dev)\n+static inline void unicam_schedule_next_buffer(struct unicam_node *node)\n {\n-\tstruct unicam_dmaqueue *dma_q = &dev->node[0].dma_queue;\n+\tstruct unicam_device *dev = node->dev;\n+\tstruct unicam_dmaqueue *dma_q = &node->dma_queue;\n \tstruct unicam_buffer *buf;\n \tdma_addr_t addr;\n \n \tbuf = list_entry(dma_q->active.next, struct unicam_buffer, list);\n-\tdev->node[0].next_frm = buf;\n+\tnode->next_frm = buf;\n \tlist_del(&buf->list);\n \n \taddr = vb2_dma_contig_plane_dma_addr(&buf->vb.vb2_buf, 0);\n-\tunicam_wr_dma_addr(dev, addr);\n+\tunicam_wr_dma_addr(dev, addr, node->pad_id);\n }\n \n-static inline void unicam_process_buffer_complete(struct unicam_device *dev)\n+static inline void unicam_process_buffer_complete(struct unicam_node *node,\n+\t\t\t\t\t\t  unsigned int sequence)\n {\n-\tdev->node[0].cur_frm->vb.field = dev->node[0].m_fmt.field;\n-\tdev->node[0].cur_frm->vb.sequence = dev->sequence++;\n+\tnode->cur_frm->vb.field = node->m_fmt.field;\n+\tnode->cur_frm->vb.sequence = sequence;\n+\n+\tvb2_buffer_done(&node->cur_frm->vb.vb2_buf, VB2_BUF_STATE_DONE);\n+\tnode->cur_frm = node->next_frm;\n+}\n \n-\tvb2_buffer_done(&dev->node[0].cur_frm->vb.vb2_buf, VB2_BUF_STATE_DONE);\n-\tdev->node[0].cur_frm = dev->node[0].next_frm;\n+static int unicam_num_nodes_streaming(struct unicam_device *dev)\n+{\n+\treturn dev->node[IMAGE_PAD].streaming +\n+\t       dev->node[METADATA_PAD].streaming;\n+}\n+\n+static int unicam_all_nodes_streaming(struct unicam_device *dev)\n+{\n+\tint ret;\n+\n+\tret = dev->node[IMAGE_PAD].open && dev->node[IMAGE_PAD].streaming;\n+\tret &= !dev->node[METADATA_PAD].open ||\n+\t       dev->node[METADATA_PAD].streaming;\n+\treturn ret;\n+}\n+\n+static int unicam_all_nodes_disabled(struct unicam_device *dev)\n+{\n+\treturn !dev->node[IMAGE_PAD].streaming &&\n+\t       !dev->node[METADATA_PAD].streaming;\n }\n \n /*\n@@ -693,10 +758,12 @@ static irqreturn_t unicam_isr(int irq, v\n {\n \tstruct unicam_device *unicam = (struct unicam_device *)dev;\n \tstruct unicam_cfg *cfg = &unicam->cfg;\n-\tstruct unicam_dmaqueue *dma_q = &unicam->node[0].dma_queue;\n \tunsigned int lines_done = unicam_get_lines_done(dev);\n \tunsigned int sequence = unicam->sequence;\n+\tint num_nodes_streaming = unicam_num_nodes_streaming(dev);\n \tint ista, sta;\n+\tu64 ts;\n+\tint i;\n \n \t/*\n \t * Don't service interrupts if not streaming.\n@@ -704,7 +771,7 @@ static irqreturn_t unicam_isr(int irq, v\n \t * peripheral without the kernel knowing (that\n \t * shouldn't happen, but causes issues if it does).\n \t */\n-\tif (!unicam->streaming)\n+\tif (unicam_all_nodes_disabled(unicam))\n \t\treturn IRQ_HANDLED;\n \n \tsta = reg_read(cfg, UNICAM_STA);\n@@ -726,9 +793,12 @@ static irqreturn_t unicam_isr(int irq, v\n \t\t * Timestamp is to be when the first data byte was captured,\n \t\t * aka frame start.\n \t\t */\n-\t\tif (unicam->node[0].cur_frm)\n-\t\t\tunicam->node[0].cur_frm->vb.vb2_buf.timestamp =\n-\t\t\t\tktime_get_ns();\n+\t\tts = ktime_get_ns();\n+\t\tfor (i = 0; i < num_nodes_streaming; i++) {\n+\t\t\tif (unicam->node[i].cur_frm)\n+\t\t\t\tunicam->node[i].cur_frm->vb.vb2_buf.timestamp =\n+\t\t\t\t\t\t\t\tts;\n+\t\t}\n \t}\n \tif (ista & UNICAM_FEI || sta & UNICAM_PI0) {\n \t\t/*\n@@ -736,9 +806,13 @@ static irqreturn_t unicam_isr(int irq, v\n \t\t * stop the peripheral. Overwrite the frame we've just\n \t\t * captured instead.\n \t\t */\n-\t\tif (unicam->node[0].cur_frm &&\n-\t\t    unicam->node[0].cur_frm != unicam->node[0].next_frm)\n-\t\t\tunicam_process_buffer_complete(unicam);\n+\t\tfor (i = 0; i < num_nodes_streaming; i++) {\n+\t\t\tif (unicam->node[i].cur_frm &&\n+\t\t\t    unicam->node[i].cur_frm != unicam->node[i].next_frm)\n+\t\t\t\tunicam_process_buffer_complete(&unicam->node[i],\n+\t\t\t\t\t\t\t       sequence);\n+\t\t}\n+\t\tunicam->sequence++;\n \t}\n \n \t/* Cannot swap buffer at frame end, there may be a race condition\n@@ -746,11 +820,13 @@ static irqreturn_t unicam_isr(int irq, v\n \t * already started.\n \t */\n \tif (ista & (UNICAM_FSI | UNICAM_LCI) && !(ista & UNICAM_FEI)) {\n-\t\tspin_lock(&unicam->node[0].dma_queue_lock);\n-\t\tif (!list_empty(&dma_q->active) &&\n-\t\t    unicam->node[0].cur_frm == unicam->node[0].next_frm)\n-\t\t\tunicam_schedule_next_buffer(unicam);\n-\t\tspin_unlock(&unicam->node[0].dma_queue_lock);\n+\t\tfor (i = 0; i < num_nodes_streaming; i++) {\n+\t\t\tspin_lock(&unicam->node[i].dma_queue_lock);\n+\t\t\tif (!list_empty(&unicam->node[i].dma_queue.active) &&\n+\t\t\t    unicam->node[i].cur_frm == unicam->node[i].next_frm)\n+\t\t\t\tunicam_schedule_next_buffer(&unicam->node[i]);\n+\t\t\tspin_unlock(&unicam->node[i].dma_queue_lock);\n+\t\t}\n \t}\n \n \tif (reg_read(&unicam->cfg, UNICAM_ICTL) & UNICAM_FCM) {\n@@ -773,6 +849,15 @@ static int unicam_querycap(struct file *\n \tsnprintf(cap->bus_info, sizeof(cap->bus_info),\n \t\t \"platform:%s\", dev->v4l2_dev.name);\n \n+\tcap->capabilities = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING |\n+\t\t\t    V4L2_CAP_READWRITE | V4L2_CAP_DEVICE_CAPS |\n+\t\t\t    V4L2_CAP_META_CAPTURE;\n+\n+\tif (node->pad_id == IMAGE_PAD)\n+\t\tcap->device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING;\n+\telse\n+\t\tcap->device_caps = V4L2_CAP_META_CAPTURE | V4L2_CAP_STREAMING;\n+\n \treturn 0;\n }\n \n@@ -787,9 +872,14 @@ static int unicam_enum_fmt_vid_cap(struc\n \tint ret = 0;\n \tint i;\n \n+\tif (node->pad_id == METADATA_PAD)\n+\t\treturn -EINVAL;\n+\n \tfor (i = 0; !ret && i < MAX_ENUM_MBUS_CODE; i++) {\n \t\tmemset(&mbus_code, 0, sizeof(mbus_code));\n \t\tmbus_code.index = i;\n+\t\tmbus_code.pad = IMAGE_PAD;\n+\t\tmbus_code.which = V4L2_SUBDEV_FORMAT_ACTIVE;\n \n \t\tret = v4l2_subdev_call(dev->sensor, pad, enum_mbus_code,\n \t\t\t\t       NULL, &mbus_code);\n@@ -827,6 +917,9 @@ static int unicam_g_fmt_vid_cap(struct f\n {\n \tstruct unicam_node *node = video_drvdata(file);\n \n+\tif (node->pad_id == METADATA_PAD)\n+\t\treturn -EINVAL;\n+\n \t*f = node->v_fmt;\n \n \treturn 0;\n@@ -843,6 +936,9 @@ const struct unicam_fmt *get_first_suppo\n \tfor (j = 0; ret != -EINVAL && ret != -ENOIOCTLCMD; ++j) {\n \t\tmemset(&mbus_code, 0, sizeof(mbus_code));\n \t\tmbus_code.index = j;\n+\t\tmbus_code.pad = IMAGE_PAD;\n+\t\tmbus_code.which = V4L2_SUBDEV_FORMAT_ACTIVE;\n+\n \t\tret = v4l2_subdev_call(dev->sensor, pad, enum_mbus_code, NULL,\n \t\t\t\t       &mbus_code);\n \t\tif (ret < 0) {\n@@ -873,12 +969,15 @@ static int unicam_try_fmt_vid_cap(struct\n \tstruct unicam_device *dev = node->dev;\n \tstruct v4l2_subdev_format sd_fmt = {\n \t\t.which = V4L2_SUBDEV_FORMAT_TRY,\n-\t\t.pad = 0\n+\t\t.pad = IMAGE_PAD\n \t};\n \tstruct v4l2_mbus_framefmt *mbus_fmt = &sd_fmt.format;\n \tconst struct unicam_fmt *fmt;\n \tint ret;\n \n+\tif (node->pad_id == METADATA_PAD)\n+\t\treturn -EINVAL;\n+\n \tfmt = find_format_by_pix(dev, f->fmt.pix.pixelformat);\n \tif (!fmt) {\n \t\t/* Pixel format not supported by unicam. Choose the first\n@@ -983,7 +1082,7 @@ static int unicam_s_fmt_vid_cap(struct f\n \n \tv4l2_fill_mbus_format(&mbus_fmt, &f->fmt.pix, fmt->code);\n \n-\tret = __subdev_set_format(dev, &mbus_fmt);\n+\tret = __subdev_set_format(dev, &mbus_fmt, node->pad_id);\n \tif (ret) {\n \t\tunicam_dbg(3, dev, \"%s __subdev_set_format failed %d\\n\",\n \t\t\t   __func__, ret);\n@@ -1014,6 +1113,106 @@ static int unicam_s_fmt_vid_cap(struct f\n \treturn 0;\n }\n \n+static int unicam_enum_fmt_meta_cap(struct file *file, void *priv,\n+\t\t\t\t    struct v4l2_fmtdesc *f)\n+{\n+\tstruct unicam_node *node = video_drvdata(file);\n+\tstruct unicam_device *dev = node->dev;\n+\tstruct v4l2_subdev_mbus_code_enum mbus_code;\n+\tconst struct unicam_fmt *fmt = NULL;\n+\tint ret = 0;\n+\n+\tif (node->pad_id != METADATA_PAD || f->index != 0)\n+\t\treturn -EINVAL;\n+\n+\tif (dev->sensor_embedded_data) {\n+\t\tmemset(&mbus_code, 0, sizeof(mbus_code));\n+\t\tmbus_code.index = f->index;\n+\t\tmbus_code.which = V4L2_SUBDEV_FORMAT_ACTIVE;\n+\t\tmbus_code.pad = METADATA_PAD;\n+\n+\t\tret = v4l2_subdev_call(dev->sensor, pad, enum_mbus_code, NULL,\n+\t\t\t\t       &mbus_code);\n+\t\tif (ret < 0) {\n+\t\t\tunicam_dbg(2, dev,\n+\t\t\t\t   \"subdev->enum_mbus_code idx 0 returned %d - index invalid\\n\",\n+\t\t\t\t   ret);\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t} else {\n+\t\tmbus_code.code = MEDIA_BUS_FMT_SENSOR_DATA;\n+\t}\n+\n+\tfmt = find_format_by_code(mbus_code.code);\n+\tif (fmt)\n+\t\tf->pixelformat = fmt->fourcc;\n+\n+\treturn 0;\n+}\n+\n+static int unicam_g_fmt_meta_cap(struct file *file, void *priv,\n+\t\t\t\t struct v4l2_format *f)\n+{\n+\tstruct unicam_node *node = video_drvdata(file);\n+\n+\tif (node->pad_id != METADATA_PAD)\n+\t\treturn -EINVAL;\n+\n+\t*f = node->v_fmt;\n+\n+\treturn 0;\n+}\n+\n+static int unicam_try_fmt_meta_cap(struct file *file, void *priv,\n+\t\t\t\t   struct v4l2_format *f)\n+{\n+\tstruct unicam_node *node = video_drvdata(file);\n+\n+\tif (node->pad_id != METADATA_PAD)\n+\t\treturn -EINVAL;\n+\n+\t*f = node->v_fmt;\n+\n+\treturn 0;\n+}\n+\n+static int unicam_s_fmt_meta_cap(struct file *file, void *priv,\n+\t\t\t\t struct v4l2_format *f)\n+{\n+\tstruct unicam_node *node = video_drvdata(file);\n+\tstruct unicam_device *dev = node->dev;\n+\tstruct v4l2_mbus_framefmt mbus_fmt = { 0 };\n+\tconst struct unicam_fmt *fmt;\n+\tint ret;\n+\n+\tif (node->pad_id == IMAGE_PAD)\n+\t\treturn -EINVAL;\n+\n+\tif (dev->sensor_embedded_data) {\n+\t\tfmt = find_format_by_pix(dev, f->fmt.meta.dataformat);\n+\t\tif (!fmt) {\n+\t\t\tunicam_err(dev, \"unknown format: V4L2 pix 0x%08x\\n\",\n+\t\t\t\t   f->fmt.meta.dataformat);\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t\tmbus_fmt.code = fmt->code;\n+\t\tret = __subdev_set_format(dev, &mbus_fmt, node->pad_id);\n+\t\tif (ret) {\n+\t\t\tunicam_dbg(3, dev, \"%s __subdev_set_format failed %d\\n\",\n+\t\t\t\t   __func__, ret);\n+\t\t\treturn ret;\n+\t\t}\n+\t}\n+\n+\t*f = node->v_fmt;\n+\n+\tunicam_dbg(3, dev, \"%s size %d, V4L2 pix 0x%08x\\n\",\n+\t\t   __func__, node->v_fmt.fmt.meta.buffersize,\n+\t\t   node->v_fmt.fmt.meta.dataformat);\n+\n+\treturn 0;\n+}\n+\n static int unicam_queue_setup(struct vb2_queue *vq,\n \t\t\t      unsigned int *nbuffers,\n \t\t\t      unsigned int *nplanes,\n@@ -1022,7 +1221,9 @@ static int unicam_queue_setup(struct vb2\n {\n \tstruct unicam_node *node = vb2_get_drv_priv(vq);\n \tstruct unicam_device *dev = node->dev;\n-\tunsigned int size = node->v_fmt.fmt.pix.sizeimage;\n+\tunsigned int size = node->pad_id == IMAGE_PAD ?\n+\t\t\t\t    node->v_fmt.fmt.pix.sizeimage :\n+\t\t\t\t    node->v_fmt.fmt.meta.buffersize;\n \n \tif (vq->num_buffers + *nbuffers < 3)\n \t\t*nbuffers = 3 - vq->num_buffers;\n@@ -1053,7 +1254,8 @@ static int unicam_buffer_prepare(struct\n \tif (WARN_ON(!node->fmt))\n \t\treturn -EINVAL;\n \n-\tsize = node->v_fmt.fmt.pix.sizeimage;\n+\tsize = node->pad_id == IMAGE_PAD ? node->v_fmt.fmt.pix.sizeimage :\n+\t\t\t\t\t   node->v_fmt.fmt.meta.buffersize;\n \tif (vb2_plane_size(vb, 0) < size) {\n \t\tunicam_err(dev, \"data will not fit into plane (%lu < %lu)\\n\",\n \t\t\t   vb2_plane_size(vb, 0), size);\n@@ -1082,12 +1284,12 @@ static void unicam_set_packing_config(st\n \tint pack, unpack;\n \tu32 val;\n \n-\tif (dev->node[0].v_fmt.fmt.pix.pixelformat ==\n-\t    dev->node[0].fmt->fourcc) {\n+\tif (dev->node[IMAGE_PAD].v_fmt.fmt.pix.pixelformat ==\n+\t    dev->node[IMAGE_PAD].fmt->fourcc) {\n \t\tunpack = UNICAM_PUM_NONE;\n \t\tpack = UNICAM_PPM_NONE;\n \t} else {\n-\t\tswitch (dev->node[0].fmt->depth) {\n+\t\tswitch (dev->node[IMAGE_PAD].fmt->depth) {\n \t\tcase 8:\n \t\t\tunpack = UNICAM_PUM_UNPACK8;\n \t\t\tbreak;\n@@ -1125,17 +1327,31 @@ static void unicam_cfg_image_id(struct u\n \tif (dev->bus_type == V4L2_MBUS_CSI2_DPHY) {\n \t\t/* CSI2 mode */\n \t\treg_write(cfg, UNICAM_IDI0,\n-\t\t\t(dev->virtual_channel << 6) | dev->node[0].fmt->csi_dt);\n+\t\t\t  (dev->virtual_channel << 6) |\n+\t\t\t\t\t      dev->node[IMAGE_PAD].fmt->csi_dt);\n \t} else {\n \t\t/* CCP2 mode */\n-\t\treg_write(cfg, UNICAM_IDI0, (0x80 | dev->node[0].fmt->csi_dt));\n+\t\treg_write(cfg, UNICAM_IDI0,\n+\t\t\t  0x80 | dev->node[IMAGE_PAD].fmt->csi_dt);\n \t}\n }\n \n-static void unicam_start_rx(struct unicam_device *dev, unsigned long addr)\n+static void unicam_enable_ed(struct unicam_device *dev)\n+{\n+\tstruct unicam_cfg *cfg = &dev->cfg;\n+\tu32 val = reg_read(cfg, UNICAM_DCS);\n+\n+\tset_field(&val, 2, UNICAM_EDL_MASK);\n+\t/* Do not wrap at the end of the embedded data buffer */\n+\tset_field(&val, 0, UNICAM_DBOB);\n+\n+\treg_write(cfg, UNICAM_DCS, val);\n+}\n+\n+static void unicam_start_rx(struct unicam_device *dev, dma_addr_t *addr)\n {\n \tstruct unicam_cfg *cfg = &dev->cfg;\n-\tint line_int_freq = dev->node[0].v_fmt.fmt.pix.height >> 2;\n+\tint line_int_freq = dev->node[IMAGE_PAD].v_fmt.fmt.pix.height >> 2;\n \tunsigned int i;\n \tu32 val;\n \n@@ -1284,27 +1500,31 @@ static void unicam_start_rx(struct unica\n \t}\n \n \treg_write(&dev->cfg, UNICAM_IBLS,\n-\t\t  dev->node[0].v_fmt.fmt.pix.bytesperline);\n-\tunicam_wr_dma_addr(dev, addr);\n+\t\t  dev->node[IMAGE_PAD].v_fmt.fmt.pix.bytesperline);\n+\tunicam_wr_dma_addr(dev, addr[IMAGE_PAD], IMAGE_PAD);\n \tunicam_set_packing_config(dev);\n \tunicam_cfg_image_id(dev);\n \n-\t/* Disabled embedded data */\n-\tval = 0;\n-\tset_field(&val, 0, UNICAM_EDL_MASK);\n-\treg_write(cfg, UNICAM_DCS, val);\n-\n \tval = reg_read(cfg, UNICAM_MISC);\n \tset_field(&val, 1, UNICAM_FL0);\n \tset_field(&val, 1, UNICAM_FL1);\n \treg_write(cfg, UNICAM_MISC, val);\n \n+\tif (dev->node[METADATA_PAD].streaming && dev->sensor_embedded_data) {\n+\t\tunicam_enable_ed(dev);\n+\t\tunicam_wr_dma_addr(dev, addr[METADATA_PAD], METADATA_PAD);\n+\t}\n+\n \t/* Enable peripheral */\n \treg_write_field(cfg, UNICAM_CTRL, 1, UNICAM_CPE);\n \n \t/* Load image pointers */\n \treg_write_field(cfg, UNICAM_ICTL, 1, UNICAM_LIP_MASK);\n \n+\t/* Load embedded data buffer pointers if needed */\n+\tif (dev->node[METADATA_PAD].streaming && dev->sensor_embedded_data)\n+\t\treg_write_field(cfg, UNICAM_DCS, 1, UNICAM_LDP);\n+\n \t/*\n \t * Enable trigger only for the first frame to\n \t * sync correctly to the FS from the source.\n@@ -1339,6 +1559,9 @@ static void unicam_disable(struct unicam\n \t/* Disable peripheral */\n \treg_write_field(cfg, UNICAM_CTRL, 0, UNICAM_CPE);\n \n+\t/* Clear ED setup */\n+\treg_write(cfg, UNICAM_DCS, 0);\n+\n \t/* Disable all lane clocks */\n \tclk_write(cfg, 0);\n }\n@@ -1347,26 +1570,23 @@ static int unicam_start_streaming(struct\n {\n \tstruct unicam_node *node = vb2_get_drv_priv(vq);\n \tstruct unicam_device *dev = node->dev;\n-\tstruct unicam_dmaqueue *dma_q = &node->dma_queue;\n-\tstruct unicam_buffer *buf, *tmp;\n-\tunsigned long addr = 0;\n+\tstruct unicam_buffer *buf;\n+\tdma_addr_t buffer_addr[MAX_NODES] = { 0 };\n+\tint num_nodes_streaming;\n \tunsigned long flags;\n-\tint ret;\n+\tint ret, i;\n \n-\tspin_lock_irqsave(&node->dma_queue_lock, flags);\n-\tbuf = list_entry(dma_q->active.next, struct unicam_buffer, list);\n-\tnode->cur_frm = buf;\n-\tnode->next_frm = buf;\n-\tlist_del(&buf->list);\n-\tspin_unlock_irqrestore(&node->dma_queue_lock, flags);\n+\tnode->streaming = 1;\n+\tif (!unicam_all_nodes_streaming(dev)) {\n+\t\tunicam_dbg(3, dev, \"Not all nodes are streaming yet.\");\n+\t\treturn 0;\n+\t}\n \n-\taddr = vb2_dma_contig_plane_dma_addr(&node->cur_frm->vb.vb2_buf, 0);\n \tdev->sequence = 0;\n-\n \tret = unicam_runtime_get(dev);\n \tif (ret < 0) {\n \t\tunicam_dbg(3, dev, \"unicam_runtime_get failed\\n\");\n-\t\tgoto err_release_buffers;\n+\t\treturn ret;\n \t}\n \n \tdev->active_data_lanes = dev->max_data_lanes;\n@@ -1388,7 +1608,7 @@ static int unicam_start_streaming(struct\n \t\t\tdev->active_data_lanes = dev->max_data_lanes;\n \t}\n \tif (dev->active_data_lanes > dev->max_data_lanes) {\n-\t\tunicam_err(dev, \"Device has requested %u data lanes, which is >%u configured in DT\\n\",\n+\t\tunicam_err(dev,\t\"Device has requested %u data lanes, which is >%u configured in DT\\n\",\n \t\t\t   dev->active_data_lanes, dev->max_data_lanes);\n \t\tret = -EINVAL;\n \t\tgoto err_pm_put;\n@@ -1408,9 +1628,22 @@ static int unicam_start_streaming(struct\n \t\tunicam_err(dev, \"Failed to enable CSI clock: %d\\n\", ret);\n \t\tgoto err_pm_put;\n \t}\n-\tdev->streaming = 1;\n \n-\tunicam_start_rx(dev, addr);\n+\tnum_nodes_streaming = unicam_num_nodes_streaming(dev);\n+\tfor (i = 0; i < num_nodes_streaming; i++) {\n+\t\tspin_lock_irqsave(&dev->node[i].dma_queue_lock, flags);\n+\t\tbuf = list_entry(dev->node[i].dma_queue.active.next,\n+\t\t\t\t struct unicam_buffer, list);\n+\t\tdev->node[i].cur_frm = buf;\n+\t\tdev->node[i].next_frm = buf;\n+\t\tlist_del(&buf->list);\n+\t\tspin_unlock_irqrestore(&dev->node[i].dma_queue_lock, flags);\n+\t\tbuffer_addr[i] =\n+\t\tvb2_dma_contig_plane_dma_addr(&dev->node[i].cur_frm->vb.vb2_buf,\n+\t\t\t\t\t      0);\n+\t}\n+\n+\tunicam_start_rx(dev, buffer_addr);\n \n \tret = v4l2_subdev_call(dev->sensor, video, s_stream, 1);\n \tif (ret < 0) {\n@@ -1421,21 +1654,11 @@ static int unicam_start_streaming(struct\n \treturn 0;\n \n err_disable_unicam:\n+\tnode->streaming = 0;\n \tunicam_disable(dev);\n \tclk_disable_unprepare(dev->clock);\n err_pm_put:\n \tunicam_runtime_put(dev);\n-err_release_buffers:\n-\tlist_for_each_entry_safe(buf, tmp, &dma_q->active, list) {\n-\t\tlist_del(&buf->list);\n-\t\tvb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_QUEUED);\n-\t}\n-\tif (node->cur_frm != node->next_frm)\n-\t\tvb2_buffer_done(&node->next_frm->vb.vb2_buf,\n-\t\t\t\tVB2_BUF_STATE_QUEUED);\n-\tvb2_buffer_done(&node->cur_frm->vb.vb2_buf, VB2_BUF_STATE_QUEUED);\n-\tnode->next_frm = NULL;\n-\tnode->cur_frm = NULL;\n \n \treturn ret;\n }\n@@ -1448,33 +1671,47 @@ static void unicam_stop_streaming(struct\n \tstruct unicam_buffer *buf, *tmp;\n \tunsigned long flags;\n \n-\tif (v4l2_subdev_call(dev->sensor, video, s_stream, 0) < 0)\n-\t\tunicam_err(dev, \"stream off failed in subdev\\n\");\n+\tnode->streaming = 0;\n \n-\tunicam_disable(dev);\n+\tif (node->pad_id == IMAGE_PAD) {\n+\t\t/* Stop streaming the sensor and disable the peripheral.\n+\t\t * We cannot continue streaming embedded data with the\n+\t\t * image pad disabled.\n+\t\t */\n+\t\tif (v4l2_subdev_call(dev->sensor, video, s_stream, 0) < 0)\n+\t\t\tunicam_err(dev, \"stream off failed in subdev\\n\");\n \n-\t/* Release all active buffers */\n+\t\tunicam_disable(dev);\n+\t\tclk_disable_unprepare(dev->clock);\n+\t\tunicam_runtime_put(dev);\n+\n+\t} else if (node->pad_id == METADATA_PAD) {\n+\t\t/* Null out the embedded data buffer address so the HW does\n+\t\t * not use it.  This is only really needed if the embedded data\n+\t\t * pad is disabled before the image pad.  The 0x3 in the top two\n+\t\t * bits signifies uncached accesses through the Videocore\n+\t\t * memory controller.\n+\t\t */\n+\t\tunicam_wr_dma_addr(dev, 0xc0000000, METADATA_PAD);\n+\t}\n+\n+\t/* Clear all queued buffers for the node */\n \tspin_lock_irqsave(&node->dma_queue_lock, flags);\n \tlist_for_each_entry_safe(buf, tmp, &dma_q->active, list) {\n \t\tlist_del(&buf->list);\n \t\tvb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);\n \t}\n \n-\tif (node->cur_frm == node->next_frm) {\n-\t\tvb2_buffer_done(&node->cur_frm->vb.vb2_buf,\n-\t\t\t\tVB2_BUF_STATE_ERROR);\n-\t} else {\n+\tif (node->cur_frm)\n \t\tvb2_buffer_done(&node->cur_frm->vb.vb2_buf,\n \t\t\t\tVB2_BUF_STATE_ERROR);\n+\tif (node->next_frm && node->cur_frm != node->next_frm)\n \t\tvb2_buffer_done(&node->next_frm->vb.vb2_buf,\n \t\t\t\tVB2_BUF_STATE_ERROR);\n-\t}\n+\n \tnode->cur_frm = NULL;\n \tnode->next_frm = NULL;\n \tspin_unlock_irqrestore(&node->dma_queue_lock, flags);\n-\n-\tclk_disable_unprepare(dev->clock);\n-\tunicam_runtime_put(dev);\n }\n \n static int unicam_enum_input(struct file *file, void *priv,\n@@ -1595,17 +1832,23 @@ static int unicam_enum_framesizes(struct\n \tstruct v4l2_subdev_frame_size_enum fse;\n \tint ret;\n \n-\t/* check for valid format */\n-\tfmt = find_format_by_pix(dev, fsize->pixel_format);\n-\tif (!fmt) {\n-\t\tunicam_dbg(3, dev, \"Invalid pixel code: %x\\n\",\n-\t\t\t   fsize->pixel_format);\n-\t\treturn -EINVAL;\n+\tif (node->pad_id == IMAGE_PAD) {\n+\t\t/* check for valid format */\n+\t\tfmt = find_format_by_pix(dev, fsize->pixel_format);\n+\t\tif (!fmt) {\n+\t\t\tunicam_dbg(3, dev, \"Invalid pixel code: %x\\n\",\n+\t\t\t\t   fsize->pixel_format);\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t\tfse.code = fmt->code;\n+\t} else {\n+\t\t/* This pad is for embedded data, so just set the format */\n+\t\tfse.code = MEDIA_BUS_FMT_SENSOR_DATA;\n \t}\n \n+\tfse.which = V4L2_SUBDEV_FORMAT_ACTIVE;\n \tfse.index = fsize->index;\n-\tfse.pad = 0;\n-\tfse.code = fmt->code;\n+\tfse.pad = node->pad_id;\n \n \tret = v4l2_subdev_call(dev->sensor, pad, enum_frame_size, NULL, &fse);\n \tif (ret)\n@@ -1782,7 +2025,7 @@ static void unicam_notify(struct v4l2_su\n \n \tswitch (notification) {\n \tcase V4L2_DEVICE_NOTIFY_EVENT:\n-\t\tv4l2_event_queue(&dev->node[0].video_dev, arg);\n+\t\tv4l2_event_queue(&dev->node[IMAGE_PAD].video_dev, arg);\n \t\tbreak;\n \tdefault:\n \t\tbreak;\n@@ -1826,6 +2069,7 @@ static int unicam_open(struct file *file\n \t\tgoto unlock;\n \t}\n \n+\tnode->open++;\n \tret = 0;\n \n unlock:\n@@ -1850,6 +2094,10 @@ static int unicam_release(struct file *f\n \tif (fh_singular)\n \t\tv4l2_subdev_call(sd, core, s_power, 0);\n \n+\tif (node->streaming)\n+\t\tunicam_stop_streaming(&node->buffer_queue);\n+\n+\tnode->open--;\n \tmutex_unlock(&node->lock);\n \n \treturn ret;\n@@ -1874,6 +2122,11 @@ static const struct v4l2_ioctl_ops unica\n \t.vidioc_s_fmt_vid_cap\t\t= unicam_s_fmt_vid_cap,\n \t.vidioc_try_fmt_vid_cap\t\t= unicam_try_fmt_vid_cap,\n \n+\t.vidioc_enum_fmt_meta_cap\t= unicam_enum_fmt_meta_cap,\n+\t.vidioc_g_fmt_meta_cap\t\t= unicam_g_fmt_meta_cap,\n+\t.vidioc_s_fmt_meta_cap\t\t= unicam_s_fmt_meta_cap,\n+\t.vidioc_try_fmt_meta_cap\t= unicam_try_fmt_meta_cap,\n+\n \t.vidioc_enum_input\t\t= unicam_enum_input,\n \t.vidioc_g_input\t\t\t= unicam_g_input,\n \t.vidioc_s_input\t\t\t= unicam_s_input,\n@@ -1941,42 +2194,53 @@ static int register_node(struct unicam_d\n \tconst struct unicam_fmt *fmt;\n \tint ret;\n \n-\tret = __subdev_get_format(unicam, &mbus_fmt, pad_id);\n-\tif (ret) {\n-\t\tunicam_err(unicam, \"Failed to get_format - ret %d\\n\", ret);\n-\t\treturn ret;\n-\t}\n-\n-\tfmt = find_format_by_code(mbus_fmt.code);\n-\tif (!fmt) {\n-\t\t/* Find the first format that the sensor and unicam both\n-\t\t * support\n-\t\t */\n-\t\tfmt = get_first_supported_format(unicam);\n+\tif (unicam->sensor_embedded_data || pad_id != METADATA_PAD) {\n+\t\tret = __subdev_get_format(unicam, &mbus_fmt, pad_id);\n+\t\tif (ret) {\n+\t\t\tunicam_err(unicam, \"Failed to get_format - ret %d\\n\",\n+\t\t\t\t   ret);\n+\t\t\treturn ret;\n+\t\t}\n \n-\t\tif (!fmt)\n-\t\t\t/* No compatible formats */\n-\t\t\treturn -EINVAL;\n+\t\tfmt = find_format_by_code(mbus_fmt.code);\n+\t\tif (!fmt) {\n+\t\t\t/* Find the first format that the sensor and unicam both\n+\t\t\t * support\n+\t\t\t */\n+\t\t\tfmt = get_first_supported_format(unicam);\n \n-\t\tmbus_fmt.code = fmt->code;\n-\t\tret = __subdev_set_format(unicam, &mbus_fmt);\n-\t\tif (ret)\n-\t\t\treturn -EINVAL;\n-\t}\n-\tif (mbus_fmt.field != V4L2_FIELD_NONE) {\n-\t\t/* Interlaced not supported - disable it now. */\n-\t\tmbus_fmt.field = V4L2_FIELD_NONE;\n-\t\tret = __subdev_set_format(unicam, &mbus_fmt);\n-\t\tif (ret)\n-\t\t\treturn -EINVAL;\n+\t\t\tif (!fmt)\n+\t\t\t\t/* No compatible formats */\n+\t\t\t\treturn -EINVAL;\n+\n+\t\t\tmbus_fmt.code = fmt->code;\n+\t\t\tret = __subdev_set_format(unicam, &mbus_fmt, pad_id);\n+\t\t\tif (ret)\n+\t\t\t\treturn -EINVAL;\n+\t\t}\n+\t\tif (mbus_fmt.field != V4L2_FIELD_NONE) {\n+\t\t\t/* Interlaced not supported - disable it now. */\n+\t\t\tmbus_fmt.field = V4L2_FIELD_NONE;\n+\t\t\tret = __subdev_set_format(unicam, &mbus_fmt, pad_id);\n+\t\t\tif (ret)\n+\t\t\t\treturn -EINVAL;\n+\t\t}\n+\t} else {\n+\t\t/* Fix this node format as embedded data. */\n+\t\tfmt = find_format_by_code(MEDIA_BUS_FMT_SENSOR_DATA);\n \t}\n \n+\tnode->dev = unicam;\n \tnode->pad_id = pad_id;\n \tnode->fmt = fmt;\n-\tif (fmt->fourcc)\n-\t\tnode->v_fmt.fmt.pix.pixelformat = fmt->fourcc;\n-\telse\n+\tif (fmt->fourcc) {\n+\t\tif (fmt->fourcc != V4L2_META_FMT_SENSOR_DATA)\n+\t\t\tnode->v_fmt.fmt.pix.pixelformat = fmt->fourcc;\n+\t\telse\n+\t\t\tnode->v_fmt.fmt.meta.dataformat = fmt->fourcc;\n+\t} else {\n \t\tnode->v_fmt.fmt.pix.pixelformat = fmt->repacked_fourcc;\n+\t}\n \n \t/* Read current subdev format */\n \tunicam_reset_format(node);\n@@ -2002,13 +2266,21 @@ static int register_node(struct unicam_d\n \tspin_lock_init(&node->dma_queue_lock);\n \tmutex_init(&node->lock);\n \n-\tif (type == V4L2_BUF_TYPE_VIDEO_CAPTURE) {\n+\tvdev = &node->video_dev;\n+\tif (pad_id == IMAGE_PAD) {\n \t\t/* Add controls from the subdevice */\n \t\tret = v4l2_ctrl_add_handler(&node->ctrl_handler,\n \t\t\t\t\t    unicam->sensor->ctrl_handler, NULL,\n \t\t\t\t\t    true);\n \t\tif (ret < 0)\n \t\t\treturn ret;\n+\n+\t\t/*\n+\t\t * If the sensor subdevice has any controls, associate the node\n+\t\t *  with the ctrl handler to allow access from userland.\n+\t\t */\n+\t\tif (!list_empty(&node->ctrl_handler.ctrls))\n+\t\t\tvdev->ctrl_handler = &node->ctrl_handler;\n \t}\n \n \tq = &node->buffer_queue;\n@@ -2031,8 +2303,6 @@ static int register_node(struct unicam_d\n \n \tINIT_LIST_HEAD(&node->dma_queue.active);\n \n-\tvdev = &node->video_dev;\n-\tstrlcpy(vdev->name, UNICAM_MODULE_NAME, sizeof(vdev->name));\n \tvdev->release = video_device_release_empty;\n \tvdev->fops = &unicam_fops;\n \tvdev->ioctl_ops = &unicam_ioctl_ops;\n@@ -2040,24 +2310,28 @@ static int register_node(struct unicam_d\n \tvdev->vfl_dir = VFL_DIR_RX;\n \tvdev->queue = q;\n \tvdev->lock = &node->lock;\n-\tvdev->device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING |\n-\t\t\t    V4L2_CAP_READWRITE;\n-\t/* If the source has no controls then remove our ctrl handler. */\n-\tif (list_empty(&node->ctrl_handler.ctrls))\n-\t\tunicam->v4l2_dev.ctrl_handler = NULL;\n+\tvdev->device_caps = (pad_id == IMAGE_PAD) ?\n+\t\t\t    (V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING) :\n+\t\t\t    (V4L2_CAP_META_CAPTURE | V4L2_CAP_STREAMING);\n+\n+\t/* Define the device names */\n+\tsnprintf(vdev->name, sizeof(vdev->name), \"%s-%s\", UNICAM_MODULE_NAME,\n+\t\t node->pad_id == IMAGE_PAD ? \"image\" : \"embedded\");\n \n-\tnode->dev = unicam;\n \tvideo_set_drvdata(vdev, node);\n \tvdev->entity.flags |= MEDIA_ENT_FL_DEFAULT;\n \n-\tif (!v4l2_subdev_has_op(unicam->sensor, video, s_std)) {\n+\tif (node->pad_id == METADATA_PAD ||\n+\t    !v4l2_subdev_has_op(unicam->sensor, video, s_std)) {\n \t\tv4l2_disable_ioctl(&node->video_dev, VIDIOC_S_STD);\n \t\tv4l2_disable_ioctl(&node->video_dev, VIDIOC_G_STD);\n \t\tv4l2_disable_ioctl(&node->video_dev, VIDIOC_ENUMSTD);\n \t}\n-\tif (!v4l2_subdev_has_op(unicam->sensor, video, querystd))\n+\tif (node->pad_id == METADATA_PAD ||\n+\t    !v4l2_subdev_has_op(unicam->sensor, video, querystd))\n \t\tv4l2_disable_ioctl(&node->video_dev, VIDIOC_QUERYSTD);\n-\tif (!v4l2_subdev_has_op(unicam->sensor, video, s_dv_timings)) {\n+\tif (node->pad_id == METADATA_PAD ||\n+\t    !v4l2_subdev_has_op(unicam->sensor, video, s_dv_timings)) {\n \t\tv4l2_disable_ioctl(&node->video_dev, VIDIOC_S_EDID);\n \t\tv4l2_disable_ioctl(&node->video_dev, VIDIOC_G_EDID);\n \t\tv4l2_disable_ioctl(&node->video_dev, VIDIOC_DV_TIMINGS_CAP);\n@@ -2066,15 +2340,19 @@ static int register_node(struct unicam_d\n \t\tv4l2_disable_ioctl(&node->video_dev, VIDIOC_ENUM_DV_TIMINGS);\n \t\tv4l2_disable_ioctl(&node->video_dev, VIDIOC_QUERY_DV_TIMINGS);\n \t}\n-\tif (!v4l2_subdev_has_op(unicam->sensor, pad, enum_frame_interval))\n+\tif (node->pad_id == METADATA_PAD ||\n+\t    !v4l2_subdev_has_op(unicam->sensor, pad, enum_frame_interval))\n \t\tv4l2_disable_ioctl(&node->video_dev,\n \t\t\t\t   VIDIOC_ENUM_FRAMEINTERVALS);\n-\tif (!v4l2_subdev_has_op(unicam->sensor, video, g_frame_interval))\n+\tif (node->pad_id == METADATA_PAD ||\n+\t    !v4l2_subdev_has_op(unicam->sensor, video, g_frame_interval))\n \t\tv4l2_disable_ioctl(&node->video_dev, VIDIOC_G_PARM);\n-\tif (!v4l2_subdev_has_op(unicam->sensor, video, s_frame_interval))\n+\tif (node->pad_id == METADATA_PAD ||\n+\t    !v4l2_subdev_has_op(unicam->sensor, video, s_frame_interval))\n \t\tv4l2_disable_ioctl(&node->video_dev, VIDIOC_S_PARM);\n \n-\tif (!v4l2_subdev_has_op(unicam->sensor, pad, enum_frame_size))\n+\tif (node->pad_id == METADATA_PAD ||\n+\t    !v4l2_subdev_has_op(unicam->sensor, pad, enum_frame_size))\n \t\tv4l2_disable_ioctl(&node->video_dev, VIDIOC_ENUM_FRAMESIZES);\n \n \tret = video_register_device(vdev, VFL_TYPE_VIDEO, -1);\n@@ -2082,27 +2360,29 @@ static int register_node(struct unicam_d\n \t\tunicam_err(unicam, \"Unable to register video device.\\n\");\n \t\treturn ret;\n \t}\n-\tnode->registered = true;\n+\tnode->registered = 1;\n \n-\tret = media_create_pad_link(&unicam->sensor->entity,\n-\t\t\t\t    0, &node->video_dev.entity, 0,\n-\t\t\t\t    MEDIA_LNK_FL_ENABLED |\n-\t\t\t\t    MEDIA_LNK_FL_IMMUTABLE);\n-\tif (ret)\n-\t\tunicam_err(unicam, \"Unable to create pad links.\\n\");\n+\tif (unicam->sensor_embedded_data) {\n+\t\tret = media_create_pad_link(&unicam->sensor->entity, pad_id,\n+\t\t\t\t\t    &node->video_dev.entity, 0,\n+\t\t\t\t\t    MEDIA_LNK_FL_ENABLED |\n+\t\t\t\t\t    MEDIA_LNK_FL_IMMUTABLE);\n+\t\tif (ret)\n+\t\t\tunicam_err(unicam, \"Unable to create pad links.\\n\");\n+\t}\n \n \treturn ret;\n }\n \n static void unregister_nodes(struct unicam_device *unicam)\n {\n-\tif (unicam->node[0].registered) {\n-\t\tvideo_unregister_device(&unicam->node[0].video_dev);\n-\t\tunicam->node[0].registered = false;\n-\t}\n-\tif (unicam->node[1].registered) {\n-\t\tvideo_unregister_device(&unicam->node[1].video_dev);\n-\t\tunicam->node[1].registered = false;\n+\tif (unicam->node[IMAGE_PAD].registered) {\n+\t\tvideo_unregister_device(&unicam->node[IMAGE_PAD].video_dev);\n+\t\tunicam->node[IMAGE_PAD].registered = 0;\n+\t}\n+\tif (unicam->node[METADATA_PAD].registered) {\n+\t\tvideo_unregister_device(&unicam->node[METADATA_PAD].video_dev);\n+\t\tunicam->node[METADATA_PAD].registered = 0;\n \t}\n }\n \n@@ -2118,20 +2398,20 @@ static int unicam_probe_complete(struct\n \tif (!unicam->sensor_config)\n \t\treturn -ENOMEM;\n \n-\tret = register_node(unicam, &unicam->node[0],\n-\t\t\t    V4L2_BUF_TYPE_VIDEO_CAPTURE, 0);\n+\tunicam->sensor_embedded_data = (unicam->sensor->entity.num_pads >= 2);\n+\n+\tret = register_node(unicam, &unicam->node[IMAGE_PAD],\n+\t\t\t    V4L2_BUF_TYPE_VIDEO_CAPTURE, IMAGE_PAD);\n \tif (ret) {\n \t\tunicam_err(unicam, \"Unable to register subdev node 0.\\n\");\n \t\tgoto unregister;\n \t}\n-\tif (unicam->sensor->entity.num_pads >= 2) {\n-\t\tret = register_node(unicam, &unicam->node[1],\n-\t\t\t\t    V4L2_BUF_TYPE_META_CAPTURE, 1);\n-\t\tif (ret) {\n-\t\t\tunicam_err(unicam,\n-\t\t\t\t   \"Unable to register subdev node 1.\\n\");\n-\t\t\tgoto unregister;\n-\t\t}\n+\n+\tret = register_node(unicam, &unicam->node[METADATA_PAD],\n+\t\t\t    V4L2_BUF_TYPE_META_CAPTURE, METADATA_PAD);\n+\tif (ret) {\n+\t\tunicam_err(unicam, \"Unable to register subdev node 1.\\n\");\n+\t\tgoto unregister;\n \t}\n \n \tret = v4l2_device_register_ro_subdev_nodes(&unicam->v4l2_dev);\n@@ -2355,8 +2635,10 @@ static int unicam_probe(struct platform_\n \t\t pdev->dev.driver->name, dev_name(&pdev->dev));\n \tunicam->mdev.hw_revision = 1;\n \n-\tmedia_entity_pads_init(&unicam->node[0].video_dev.entity, 1,\n-\t\t\t       &unicam->node[0].pad);\n+\tmedia_entity_pads_init(&unicam->node[IMAGE_PAD].video_dev.entity, 1,\n+\t\t\t       &unicam->node[IMAGE_PAD].pad);\n+\tmedia_entity_pads_init(&unicam->node[METADATA_PAD].video_dev.entity, 1,\n+\t\t\t       &unicam->node[METADATA_PAD].pad);\n \tmedia_device_init(&unicam->mdev);\n \n \tunicam->v4l2_dev.mdev = &unicam->mdev;\n@@ -2376,11 +2658,10 @@ static int unicam_probe(struct platform_\n \t}\n \n \t/* Reserve space for the controls */\n-\thdl = &unicam->node[0].ctrl_handler;\n+\thdl = &unicam->node[IMAGE_PAD].ctrl_handler;\n \tret = v4l2_ctrl_handler_init(hdl, 16);\n \tif (ret < 0)\n \t\tgoto media_unregister;\n-\tunicam->v4l2_dev.ctrl_handler = hdl;\n \n \t/* set the driver data in platform device */\n \tplatform_set_drvdata(pdev, unicam);\n@@ -2417,7 +2698,7 @@ static int unicam_remove(struct platform\n \tpm_runtime_disable(&pdev->dev);\n \n \tv4l2_async_notifier_unregister(&unicam->notifier);\n-\tv4l2_ctrl_handler_free(&unicam->node[0].ctrl_handler);\n+\tv4l2_ctrl_handler_free(&unicam->node[IMAGE_PAD].ctrl_handler);\n \tv4l2_device_unregister(&unicam->v4l2_dev);\n \tunregister_nodes(unicam);\n \tif (unicam->sensor_config)\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0214-media-bcm2835-unicam-Use-dummy-buffer-if-none-have-b.patch",
    "content": "From 43f17e232abec4960a2edd6f245d6e1e0058a858 Mon Sep 17 00:00:00 2001\nFrom: Naushir Patuck <naush@raspberrypi.com>\nDate: Thu, 2 Apr 2020 16:08:51 +0100\nSubject: [PATCH] media: bcm2835-unicam: Use dummy buffer if none have\n been queued\n\nIf no buffer has been queued by a userland application, we use an\ninternal dummy buffer for the hardware to spin in. This will allow\nthe driver to release the existing userland buffer back to the\napplication for processing.\n\nSigned-off-by: Naushir Patuck <naush@raspberrypi.com>\n---\n .../media/platform/bcm2835/bcm2835-unicam.c   | 160 ++++++++++++------\n 1 file changed, 110 insertions(+), 50 deletions(-)\n\n--- a/drivers/media/platform/bcm2835/bcm2835-unicam.c\n+++ b/drivers/media/platform/bcm2835/bcm2835-unicam.c\n@@ -47,6 +47,7 @@\n #include <linux/clk.h>\n #include <linux/delay.h>\n #include <linux/device.h>\n+#include <linux/dma-mapping.h>\n #include <linux/err.h>\n #include <linux/init.h>\n #include <linux/interrupt.h>\n@@ -112,6 +113,12 @@ MODULE_PARM_DESC(debug, \"Debug level 0-3\n /* Default size of the embedded buffer */\n #define UNICAM_EMBEDDED_SIZE\t8192\n \n+/*\n+ * Size of the dummy buffer. Can be any size really, but the DMA\n+ * allocation works in units of page sizes.\n+ */\n+#define DUMMY_BUF_SIZE\t(PAGE_SIZE)\n+\n enum pad_types {\n \tIMAGE_PAD,\n \tMETADATA_PAD,\n@@ -390,6 +397,12 @@ struct unicam_node {\n \tstruct media_pad pad;\n \tstruct v4l2_ctrl_handler ctrl_handler;\n \tunsigned int embedded_lines;\n+\t/*\n+\t * Dummy buffer intended to be used by unicam\n+\t * if we have no other queued buffers to swap to.\n+\t */\n+\tvoid *dummy_buf_cpu_addr;\n+\tdma_addr_t dummy_buf_dma_addr;\n };\n \n struct unicam_device {\n@@ -661,27 +674,24 @@ static int unicam_reset_format(struct un\n \treturn 0;\n }\n \n-static void unicam_wr_dma_addr(struct unicam_device *dev, dma_addr_t dmaaddr,\n-\t\t\t       int pad_id)\n+static void unicam_wr_dma_addr(struct unicam_cfg *cfg, dma_addr_t dmaaddr,\n+\t\t\t       unsigned int buffer_size, int pad_id)\n {\n-\tdma_addr_t endaddr;\n+\tdma_addr_t endaddr = dmaaddr + buffer_size;\n \n \t/*\n-\t * dmaaddr should be a 32-bit address with the top two bits set to 0x3\n-\t * to signify uncached access through the Videocore memory controller.\n+\t * dmaaddr and endaddr should be a 32-bit address with the top two bits\n+\t * set to 0x3 to signify uncached access through the Videocore memory\n+\t * controller.\n \t */\n-\tBUG_ON((dmaaddr >> 30) != 0x3);\n+\tBUG_ON((dmaaddr >> 30) != 0x3 && (endaddr >> 30) != 0x3);\n \n \tif (pad_id == IMAGE_PAD) {\n-\t\tendaddr = dmaaddr +\n-\t\t\t  dev->node[IMAGE_PAD].v_fmt.fmt.pix.sizeimage;\n-\t\treg_write(&dev->cfg, UNICAM_IBSA0, dmaaddr);\n-\t\treg_write(&dev->cfg, UNICAM_IBEA0, endaddr);\n+\t\treg_write(cfg, UNICAM_IBSA0, dmaaddr);\n+\t\treg_write(cfg, UNICAM_IBEA0, endaddr);\n \t} else {\n-\t\tendaddr = dmaaddr +\n-\t\t\t  dev->node[METADATA_PAD].v_fmt.fmt.meta.buffersize;\n-\t\treg_write(&dev->cfg, UNICAM_DBSA0, dmaaddr);\n-\t\treg_write(&dev->cfg, UNICAM_DBEA0, endaddr);\n+\t\treg_write(cfg, UNICAM_DBSA0, dmaaddr);\n+\t\treg_write(cfg, UNICAM_DBEA0, endaddr);\n \t}\n }\n \n@@ -704,6 +714,7 @@ static inline void unicam_schedule_next_\n \tstruct unicam_device *dev = node->dev;\n \tstruct unicam_dmaqueue *dma_q = &node->dma_queue;\n \tstruct unicam_buffer *buf;\n+\tunsigned int size;\n \tdma_addr_t addr;\n \n \tbuf = list_entry(dma_q->active.next, struct unicam_buffer, list);\n@@ -711,7 +722,23 @@ static inline void unicam_schedule_next_\n \tlist_del(&buf->list);\n \n \taddr = vb2_dma_contig_plane_dma_addr(&buf->vb.vb2_buf, 0);\n-\tunicam_wr_dma_addr(dev, addr, node->pad_id);\n+\tsize = (node->pad_id == IMAGE_PAD) ?\n+\t\t\tdev->node[IMAGE_PAD].v_fmt.fmt.pix.sizeimage :\n+\t\t\tdev->node[METADATA_PAD].v_fmt.fmt.meta.buffersize;\n+\n+\tunicam_wr_dma_addr(&dev->cfg, addr, size, node->pad_id);\n+}\n+\n+static inline void unicam_schedule_dummy_buffer(struct unicam_node *node)\n+{\n+\tstruct unicam_device *dev = node->dev;\n+\tdma_addr_t addr = node->dummy_buf_dma_addr;\n+\n+\tunicam_dbg(3, dev, \"Scheduling dummy buffer for node %d\\n\",\n+\t\t   node->pad_id);\n+\n+\tunicam_wr_dma_addr(&dev->cfg, addr, DUMMY_BUF_SIZE, node->pad_id);\n+\tnode->next_frm = NULL;\n }\n \n static inline void unicam_process_buffer_complete(struct unicam_node *node,\n@@ -721,7 +748,6 @@ static inline void unicam_process_buffer\n \tnode->cur_frm->vb.sequence = sequence;\n \n \tvb2_buffer_done(&node->cur_frm->vb.vb2_buf, VB2_BUF_STATE_DONE);\n-\tnode->cur_frm = node->next_frm;\n }\n \n static int unicam_num_nodes_streaming(struct unicam_device *dev)\n@@ -788,6 +814,28 @@ static irqreturn_t unicam_isr(int irq, v\n \tif (!(sta && (UNICAM_IS | UNICAM_PI0)))\n \t\treturn IRQ_HANDLED;\n \n+\t/*\n+\t * We must run the frame end handler first. If we have a valid next_frm\n+\t * and we get a simultaneout FE + FS interrupt, running the FS handler\n+\t * first would null out the next_frm ptr and we would have lost the\n+\t * buffer forever.\n+\t */\n+\tif (ista & UNICAM_FEI || sta & UNICAM_PI0) {\n+\t\t/*\n+\t\t * Ensure we have swapped buffers already as we can't\n+\t\t * stop the peripheral. If no buffer is available, use a\n+\t\t * dummy buffer to dump out frames until we get a new buffer\n+\t\t * to use.\n+\t\t */\n+\t\tfor (i = 0; i < num_nodes_streaming; i++) {\n+\t\t\tif (unicam->node[i].cur_frm)\n+\t\t\t\tunicam_process_buffer_complete(&unicam->node[i],\n+\t\t\t\t\t\t\t       sequence);\n+\t\t\tunicam->node[i].cur_frm = unicam->node[i].next_frm;\n+\t\t}\n+\t\tunicam->sequence++;\n+\t}\n+\n \tif (ista & UNICAM_FSI) {\n \t\t/*\n \t\t * Timestamp is to be when the first data byte was captured,\n@@ -798,24 +846,16 @@ static irqreturn_t unicam_isr(int irq, v\n \t\t\tif (unicam->node[i].cur_frm)\n \t\t\t\tunicam->node[i].cur_frm->vb.vb2_buf.timestamp =\n \t\t\t\t\t\t\t\tts;\n+\t\t\t/*\n+\t\t\t * Set the next frame output to go to a dummy frame\n+\t\t\t * if we have not managed to obtain another frame\n+\t\t\t * from the queue.\n+\t\t\t */\n+\t\t\tunicam_schedule_dummy_buffer(&unicam->node[i]);\n \t\t}\n \t}\n-\tif (ista & UNICAM_FEI || sta & UNICAM_PI0) {\n-\t\t/*\n-\t\t * Ensure we have swapped buffers already as we can't\n-\t\t * stop the peripheral. Overwrite the frame we've just\n-\t\t * captured instead.\n-\t\t */\n-\t\tfor (i = 0; i < num_nodes_streaming; i++) {\n-\t\t\tif (unicam->node[i].cur_frm &&\n-\t\t\t    unicam->node[i].cur_frm != unicam->node[i].next_frm)\n-\t\t\t\tunicam_process_buffer_complete(&unicam->node[i],\n-\t\t\t\t\t\t\t       sequence);\n-\t\t}\n-\t\tunicam->sequence++;\n-\t}\n-\n-\t/* Cannot swap buffer at frame end, there may be a race condition\n+\t/*\n+\t * Cannot swap buffer at frame end, there may be a race condition\n \t * where the HW does not actually swap it if the new frame has\n \t * already started.\n \t */\n@@ -823,7 +863,7 @@ static irqreturn_t unicam_isr(int irq, v\n \t\tfor (i = 0; i < num_nodes_streaming; i++) {\n \t\t\tspin_lock(&unicam->node[i].dma_queue_lock);\n \t\t\tif (!list_empty(&unicam->node[i].dma_queue.active) &&\n-\t\t\t    unicam->node[i].cur_frm == unicam->node[i].next_frm)\n+\t\t\t    !unicam->node[i].next_frm)\n \t\t\t\tunicam_schedule_next_buffer(&unicam->node[i]);\n \t\t\tspin_unlock(&unicam->node[i].dma_queue_lock);\n \t\t}\n@@ -1352,7 +1392,7 @@ static void unicam_start_rx(struct unica\n {\n \tstruct unicam_cfg *cfg = &dev->cfg;\n \tint line_int_freq = dev->node[IMAGE_PAD].v_fmt.fmt.pix.height >> 2;\n-\tunsigned int i;\n+\tunsigned int size, i;\n \tu32 val;\n \n \tif (line_int_freq < 128)\n@@ -1413,7 +1453,7 @@ static void unicam_start_rx(struct unica\n \treg_write_field(cfg, UNICAM_ANA, 0, UNICAM_DDL);\n \n \t/* Always start in trigger frame capture mode (UNICAM_FCM set) */\n-\tval = UNICAM_FSIE | UNICAM_FEIE | UNICAM_FCM;\n+\tval = UNICAM_FSIE | UNICAM_FEIE | UNICAM_FCM | UNICAM_IBOB;\n \tset_field(&val,  line_int_freq, UNICAM_LCIE_MASK);\n \treg_write(cfg, UNICAM_ICTL, val);\n \treg_write(cfg, UNICAM_STA, UNICAM_STA_MASK_ALL);\n@@ -1501,7 +1541,8 @@ static void unicam_start_rx(struct unica\n \n \treg_write(&dev->cfg, UNICAM_IBLS,\n \t\t  dev->node[IMAGE_PAD].v_fmt.fmt.pix.bytesperline);\n-\tunicam_wr_dma_addr(dev, addr[IMAGE_PAD], IMAGE_PAD);\n+\tsize = dev->node[IMAGE_PAD].v_fmt.fmt.pix.sizeimage;\n+\tunicam_wr_dma_addr(&dev->cfg, addr[IMAGE_PAD], size, IMAGE_PAD);\n \tunicam_set_packing_config(dev);\n \tunicam_cfg_image_id(dev);\n \n@@ -1511,8 +1552,10 @@ static void unicam_start_rx(struct unica\n \treg_write(cfg, UNICAM_MISC, val);\n \n \tif (dev->node[METADATA_PAD].streaming && dev->sensor_embedded_data) {\n+\t\tsize = dev->node[METADATA_PAD].v_fmt.fmt.meta.buffersize;\n \t\tunicam_enable_ed(dev);\n-\t\tunicam_wr_dma_addr(dev, addr[METADATA_PAD], METADATA_PAD);\n+\t\tunicam_wr_dma_addr(&dev->cfg, addr[METADATA_PAD], size,\n+\t\t\t\t   METADATA_PAD);\n \t}\n \n \t/* Enable peripheral */\n@@ -1686,13 +1729,14 @@ static void unicam_stop_streaming(struct\n \t\tunicam_runtime_put(dev);\n \n \t} else if (node->pad_id == METADATA_PAD) {\n-\t\t/* Null out the embedded data buffer address so the HW does\n-\t\t * not use it.  This is only really needed if the embedded data\n-\t\t * pad is disabled before the image pad.  The 0x3 in the top two\n-\t\t * bits signifies uncached accesses through the Videocore\n-\t\t * memory controller.\n+\t\t/* Allow the hardware to spin in the dummy buffer.\n+\t\t * This is only really needed if the embedded data pad is\n+\t\t * disabled before the image pad.  The 0x3 in the top two bits\n+\t\t * signifies uncached accesses through the Videocore memory\n+\t\t * controller.\n \t\t */\n-\t\tunicam_wr_dma_addr(dev, 0xc0000000, METADATA_PAD);\n+\t\tunicam_wr_dma_addr(&dev->cfg, node->dummy_buf_dma_addr,\n+\t\t\t\t   DUMMY_BUF_SIZE, METADATA_PAD);\n \t}\n \n \t/* Clear all queued buffers for the node */\n@@ -2321,6 +2365,15 @@ static int register_node(struct unicam_d\n \tvideo_set_drvdata(vdev, node);\n \tvdev->entity.flags |= MEDIA_ENT_FL_DEFAULT;\n \n+\tnode->dummy_buf_cpu_addr = dma_alloc_coherent(&unicam->pdev->dev,\n+\t\t\t\t\t\t      DUMMY_BUF_SIZE,\n+\t\t\t\t\t\t      &node->dummy_buf_dma_addr,\n+\t\t\t\t\t\t      GFP_ATOMIC);\n+\tif (!node->dummy_buf_cpu_addr) {\n+\t\tunicam_err(unicam, \"Unable to allocate dummy buffer.\\n\");\n+\t\treturn -ENOMEM;\n+\t}\n+\n \tif (node->pad_id == METADATA_PAD ||\n \t    !v4l2_subdev_has_op(unicam->sensor, video, s_std)) {\n \t\tv4l2_disable_ioctl(&node->video_dev, VIDIOC_S_STD);\n@@ -2376,13 +2429,20 @@ static int register_node(struct unicam_d\n \n static void unregister_nodes(struct unicam_device *unicam)\n {\n-\tif (unicam->node[IMAGE_PAD].registered) {\n-\t\tvideo_unregister_device(&unicam->node[IMAGE_PAD].video_dev);\n-\t\tunicam->node[IMAGE_PAD].registered = 0;\n-\t}\n-\tif (unicam->node[METADATA_PAD].registered) {\n-\t\tvideo_unregister_device(&unicam->node[METADATA_PAD].video_dev);\n-\t\tunicam->node[METADATA_PAD].registered = 0;\n+\tstruct unicam_node *node;\n+\tint i;\n+\n+\tfor (i = 0; i < MAX_NODES; i++) {\n+\t\tnode = &unicam->node[i];\n+\t\tif (node->dummy_buf_cpu_addr) {\n+\t\t\tdma_free_coherent(&unicam->pdev->dev, DUMMY_BUF_SIZE,\n+\t\t\t\t\t  node->dummy_buf_cpu_addr,\n+\t\t\t\t\t  node->dummy_buf_dma_addr);\n+\t\t}\n+\t\tif (node->registered) {\n+\t\t\tvideo_unregister_device(&node->video_dev);\n+\t\t\tnode->registered = 0;\n+\t\t}\n \t}\n }\n \n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0215-media-bcm2835-unicam-Disable-event-related-ioctls-on.patch",
    "content": "From 62bd5b64e0213e0b2cf0d0e65e7b0a30399b5e36 Mon Sep 17 00:00:00 2001\nFrom: Laurent Pinchart <laurent.pinchart@ideasonboard.com>\nDate: Tue, 24 Mar 2020 23:13:02 +0200\nSubject: [PATCH] media: bcm2835-unicam: Disable event-related ioctls\n on metadata node\n\nThe unicam driver supports both the SOURCE_CHANGE and CTRL events. Both\nevents are only generated on the image video node, so the event-related\nioctls are useless on the medatada node. Disable them.\n\nSigned-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>\nReviewed-by: Jacopo Mondi <jacopo@jmondi.org>\nReviewed-by: Naushir Patuck <naush@raspberrypi.com>\n---\n drivers/media/platform/bcm2835/bcm2835-unicam.c | 5 +++++\n 1 file changed, 5 insertions(+)\n\n--- a/drivers/media/platform/bcm2835/bcm2835-unicam.c\n+++ b/drivers/media/platform/bcm2835/bcm2835-unicam.c\n@@ -2374,6 +2374,11 @@ static int register_node(struct unicam_d\n \t\treturn -ENOMEM;\n \t}\n \n+\tif (node->pad_id == METADATA_PAD) {\n+\t\tv4l2_disable_ioctl(vdev, VIDIOC_DQEVENT);\n+\t\tv4l2_disable_ioctl(vdev, VIDIOC_SUBSCRIBE_EVENT);\n+\t\tv4l2_disable_ioctl(vdev, VIDIOC_UNSUBSCRIBE_EVENT);\n+\t}\n \tif (node->pad_id == METADATA_PAD ||\n \t    !v4l2_subdev_has_op(unicam->sensor, video, s_std)) {\n \t\tv4l2_disable_ioctl(&node->video_dev, VIDIOC_S_STD);\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0216-media-bcm2835-unicam-Add-support-for-the-FRAME_SYNC-.patch",
    "content": "From 6195ecf605368d29a9ef684da387a6929845f925 Mon Sep 17 00:00:00 2001\nFrom: Laurent Pinchart <laurent.pinchart@ideasonboard.com>\nDate: Tue, 24 Mar 2020 23:13:02 +0200\nSubject: [PATCH] media: bcm2835-unicam: Add support for the FRAME_SYNC\n event\n\nThe FRAME_SYNC event is useful for userspace image processing algorithms\nto program the camera sensor as early as possible after frame start.\nSupport it.\n\nSigned-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>\nReviewed-by: Kieran Bingham <kieran.bingham@ideasonboard.com>\nReviewed-by: Jacopo Mondi <jacopo@jmondi.org>\nReviewed-by: Naushir Patuck <naush@raspberrypi.com>\n---\n drivers/media/platform/bcm2835/bcm2835-unicam.c | 14 ++++++++++++++\n 1 file changed, 14 insertions(+)\n\n--- a/drivers/media/platform/bcm2835/bcm2835-unicam.c\n+++ b/drivers/media/platform/bcm2835/bcm2835-unicam.c\n@@ -772,6 +772,16 @@ static int unicam_all_nodes_disabled(str\n \t       !dev->node[METADATA_PAD].streaming;\n }\n \n+static void unicam_queue_event_sof(struct unicam_device *unicam)\n+{\n+\tstruct v4l2_event event = {\n+\t\t.type = V4L2_EVENT_FRAME_SYNC,\n+\t\t.u.frame_sync.frame_sequence = unicam->sequence,\n+\t};\n+\n+\tv4l2_event_queue(&unicam->node[IMAGE_PAD].video_dev, &event);\n+}\n+\n /*\n  * unicam_isr : ISR handler for unicam capture\n  * @irq: irq number\n@@ -853,6 +863,8 @@ static irqreturn_t unicam_isr(int irq, v\n \t\t\t */\n \t\t\tunicam_schedule_dummy_buffer(&unicam->node[i]);\n \t\t}\n+\n+\t\tunicam_queue_event_sof(unicam);\n \t}\n \t/*\n \t * Cannot swap buffer at frame end, there may be a race condition\n@@ -2022,6 +2034,8 @@ static int unicam_subscribe_event(struct\n \t\t\t\t  const struct v4l2_event_subscription *sub)\n {\n \tswitch (sub->type) {\n+\tcase V4L2_EVENT_FRAME_SYNC:\n+\t\treturn v4l2_event_subscribe(fh, sub, 2, NULL);\n \tcase V4L2_EVENT_SOURCE_CHANGE:\n \t\treturn v4l2_event_subscribe(fh, sub, 4, NULL);\n \t}\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0217-media-imx219-Advertise-embedded-data-node-on-media-p.patch",
    "content": "From fde54dfff6652b153af9fab8114b27510b0fe8b4 Mon Sep 17 00:00:00 2001\nFrom: Naushir Patuck <naush@raspberrypi.com>\nDate: Thu, 12 Mar 2020 14:09:38 +0000\nSubject: [PATCH] media: imx219: Advertise embedded data node on media\n pad 1\n\nThis commit updates the imx219 driver to adverise support for embedded\ndata streams.  This can then be used by the bcm2835-unicam driver, which\nhas recently been updated to expose the embedded data stream to\nuserland.\n\nThe imx219 sensor subdevice overloads the media pad to differentiate\nbetween image stream (pad 0) and embedded data stream (pad 1) when\nperforming the v4l2_subdev_pad_ops functions.\n\nSigned-off-by: Naushir Patuck <naush@raspberrypi.com>\n---\n drivers/media/i2c/imx219.c | 226 +++++++++++++++++++++++++------------\n 1 file changed, 155 insertions(+), 71 deletions(-)\n\n--- a/drivers/media/i2c/imx219.c\n+++ b/drivers/media/i2c/imx219.c\n@@ -118,6 +118,16 @@\n #define IMX219_PIXEL_ARRAY_WIDTH\t3280U\n #define IMX219_PIXEL_ARRAY_HEIGHT\t2464U\n \n+/* Embedded metadata stream structure */\n+#define IMX219_EMBEDDED_LINE_WIDTH 16384\n+#define IMX219_NUM_EMBEDDED_LINES 1\n+\n+enum pad_types {\n+\tIMAGE_PAD,\n+\tMETADATA_PAD,\n+\tNUM_PADS\n+};\n+\n struct imx219_reg {\n \tu16 address;\n \tu8 val;\n@@ -536,7 +546,7 @@ static const struct imx219_mode supporte\n \n struct imx219 {\n \tstruct v4l2_subdev sd;\n-\tstruct media_pad pad;\n+\tstruct media_pad pad[NUM_PADS];\n \n \tstruct v4l2_mbus_framefmt fmt;\n \n@@ -685,18 +695,26 @@ static void imx219_set_default_format(st\n static int imx219_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)\n {\n \tstruct imx219 *imx219 = to_imx219(sd);\n-\tstruct v4l2_mbus_framefmt *try_fmt =\n-\t\tv4l2_subdev_get_try_format(sd, fh->pad, 0);\n+\tstruct v4l2_mbus_framefmt *try_fmt_img =\n+\t\tv4l2_subdev_get_try_format(sd, fh->pad, IMAGE_PAD);\n+\tstruct v4l2_mbus_framefmt *try_fmt_meta =\n+\t\tv4l2_subdev_get_try_format(sd, fh->pad, METADATA_PAD);\n \tstruct v4l2_rect *try_crop;\n \n \tmutex_lock(&imx219->mutex);\n \n-\t/* Initialize try_fmt */\n-\ttry_fmt->width = supported_modes[0].width;\n-\ttry_fmt->height = supported_modes[0].height;\n-\ttry_fmt->code = imx219_get_format_code(imx219,\n-\t\t\t\t\t       MEDIA_BUS_FMT_SRGGB10_1X10);\n-\ttry_fmt->field = V4L2_FIELD_NONE;\n+\t/* Initialize try_fmt for the image pad */\n+\ttry_fmt_img->width = supported_modes[0].width;\n+\ttry_fmt_img->height = supported_modes[0].height;\n+\ttry_fmt_img->code = imx219_get_format_code(imx219,\n+\t\t\t\t\t\t   MEDIA_BUS_FMT_SRGGB10_1X10);\n+\ttry_fmt_img->field = V4L2_FIELD_NONE;\n+\n+\t/* Initialize try_fmt for the embedded metadata pad */\n+\ttry_fmt_meta->width = IMX219_EMBEDDED_LINE_WIDTH;\n+\ttry_fmt_meta->height = IMX219_NUM_EMBEDDED_LINES;\n+\ttry_fmt_meta->code = MEDIA_BUS_FMT_SENSOR_DATA;\n+\ttry_fmt_meta->field = V4L2_FIELD_NONE;\n \n \t/* Initialize try_crop rectangle. */\n \ttry_crop = v4l2_subdev_get_try_crop(sd, fh->pad, 0);\n@@ -805,10 +823,21 @@ static int imx219_enum_mbus_code(struct\n {\n \tstruct imx219 *imx219 = to_imx219(sd);\n \n-\tif (code->index >= (ARRAY_SIZE(codes) / 4))\n+\tif (code->pad >= NUM_PADS)\n \t\treturn -EINVAL;\n \n-\tcode->code = imx219_get_format_code(imx219, codes[code->index * 4]);\n+\tif (code->pad == IMAGE_PAD) {\n+\t\tif (code->index >= (ARRAY_SIZE(codes) / 4))\n+\t\t\treturn -EINVAL;\n+\n+\t\tcode->code = imx219_get_format_code(imx219,\n+\t\t\t\t\t\t    codes[code->index * 4]);\n+\t} else {\n+\t\tif (code->index > 0)\n+\t\t\treturn -EINVAL;\n+\n+\t\tcode->code = MEDIA_BUS_FMT_SENSOR_DATA;\n+\t}\n \n \treturn 0;\n }\n@@ -819,16 +848,29 @@ static int imx219_enum_frame_size(struct\n {\n \tstruct imx219 *imx219 = to_imx219(sd);\n \n-\tif (fse->index >= ARRAY_SIZE(supported_modes))\n+\tif (fse->pad >= NUM_PADS)\n \t\treturn -EINVAL;\n \n-\tif (fse->code != imx219_get_format_code(imx219, fse->code))\n-\t\treturn -EINVAL;\n+\tif (fse->pad == IMAGE_PAD) {\n+\t\tif (fse->index >= ARRAY_SIZE(supported_modes))\n+\t\t\treturn -EINVAL;\n+\n+\t\tif (fse->code != imx219_get_format_code(imx219, fse->code))\n+\t\t\treturn -EINVAL;\n+\n+\t\tfse->min_width = supported_modes[fse->index].width;\n+\t\tfse->max_width = fse->min_width;\n+\t\tfse->min_height = supported_modes[fse->index].height;\n+\t\tfse->max_height = fse->min_height;\n+\t} else {\n+\t\tif (fse->code != MEDIA_BUS_FMT_SENSOR_DATA || fse->index > 0)\n+\t\t\treturn -EINVAL;\n \n-\tfse->min_width = supported_modes[fse->index].width;\n-\tfse->max_width = fse->min_width;\n-\tfse->min_height = supported_modes[fse->index].height;\n-\tfse->max_height = fse->min_height;\n+\t\tfse->min_width = IMX219_EMBEDDED_LINE_WIDTH;\n+\t\tfse->max_width = fse->min_width;\n+\t\tfse->min_height = IMX219_NUM_EMBEDDED_LINES;\n+\t\tfse->max_height = fse->min_height;\n+\t}\n \n \treturn 0;\n }\n@@ -843,9 +885,9 @@ static void imx219_reset_colorspace(stru\n \tfmt->xfer_func = V4L2_MAP_XFER_FUNC_DEFAULT(fmt->colorspace);\n }\n \n-static void imx219_update_pad_format(struct imx219 *imx219,\n-\t\t\t\t     const struct imx219_mode *mode,\n-\t\t\t\t     struct v4l2_subdev_format *fmt)\n+static void imx219_update_image_pad_format(struct imx219 *imx219,\n+\t\t\t\t\t   const struct imx219_mode *mode,\n+\t\t\t\t\t   struct v4l2_subdev_format *fmt)\n {\n \tfmt->format.width = mode->width;\n \tfmt->format.height = mode->height;\n@@ -853,20 +895,38 @@ static void imx219_update_pad_format(str\n \timx219_reset_colorspace(&fmt->format);\n }\n \n+static void imx219_update_metadata_pad_format(struct v4l2_subdev_format *fmt)\n+{\n+\tfmt->format.width = IMX219_EMBEDDED_LINE_WIDTH;\n+\tfmt->format.height = IMX219_NUM_EMBEDDED_LINES;\n+\tfmt->format.code = MEDIA_BUS_FMT_SENSOR_DATA;\n+\tfmt->format.field = V4L2_FIELD_NONE;\n+}\n+\n static int __imx219_get_pad_format(struct imx219 *imx219,\n \t\t\t\t   struct v4l2_subdev_pad_config *cfg,\n \t\t\t\t   struct v4l2_subdev_format *fmt)\n {\n+\tif (fmt->pad >= NUM_PADS)\n+\t\treturn -EINVAL;\n+\n \tif (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {\n \t\tstruct v4l2_mbus_framefmt *try_fmt =\n \t\t\tv4l2_subdev_get_try_format(&imx219->sd, cfg, fmt->pad);\n \t\t/* update the code which could change due to vflip or hflip: */\n-\t\ttry_fmt->code = imx219_get_format_code(imx219, try_fmt->code);\n+\t\ttry_fmt->code = fmt->pad == IMAGE_PAD ?\n+\t\t\t\timx219_get_format_code(imx219, try_fmt->code) :\n+\t\t\t\tMEDIA_BUS_FMT_SENSOR_DATA;\n \t\tfmt->format = *try_fmt;\n \t} else {\n-\t\timx219_update_pad_format(imx219, imx219->mode, fmt);\n-\t\tfmt->format.code = imx219_get_format_code(imx219,\n-\t\t\t\t\t\t\t  imx219->fmt.code);\n+\t\tif (fmt->pad == IMAGE_PAD) {\n+\t\t\timx219_update_image_pad_format(imx219, imx219->mode,\n+\t\t\t\t\t\t       fmt);\n+\t\t\tfmt->format.code = imx219_get_format_code(imx219,\n+\t\t\t\t\t\t\t      imx219->fmt.code);\n+\t\t} else {\n+\t\t\timx219_update_metadata_pad_format(fmt);\n+\t\t}\n \t}\n \n \treturn 0;\n@@ -896,51 +956,74 @@ static int imx219_set_pad_format(struct\n \tint exposure_max, exposure_def, hblank;\n \tunsigned int i;\n \n-\tmutex_lock(&imx219->mutex);\n-\n-\tfor (i = 0; i < ARRAY_SIZE(codes); i++)\n-\t\tif (codes[i] == fmt->format.code)\n-\t\t\tbreak;\n-\tif (i >= ARRAY_SIZE(codes))\n-\t\ti = 0;\n+\tif (fmt->pad >= NUM_PADS)\n+\t\treturn -EINVAL;\n \n-\t/* Bayer order varies with flips */\n-\tfmt->format.code = imx219_get_format_code(imx219, codes[i]);\n+\tmutex_lock(&imx219->mutex);\n \n-\tmode = v4l2_find_nearest_size(supported_modes,\n-\t\t\t\t      ARRAY_SIZE(supported_modes),\n-\t\t\t\t      width, height,\n-\t\t\t\t      fmt->format.width, fmt->format.height);\n-\timx219_update_pad_format(imx219, mode, fmt);\n-\tif (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {\n-\t\tframefmt = v4l2_subdev_get_try_format(sd, cfg, fmt->pad);\n-\t\t*framefmt = fmt->format;\n-\t} else if (imx219->mode != mode ||\n-\t\t   imx219->fmt.code != fmt->format.code) {\n-\t\timx219->fmt = fmt->format;\n-\t\timx219->mode = mode;\n-\t\t/* Update limits and set FPS to default */\n-\t\t__v4l2_ctrl_modify_range(imx219->vblank, IMX219_VBLANK_MIN,\n-\t\t\t\t\t IMX219_VTS_MAX - mode->height, 1,\n-\t\t\t\t\t mode->vts_def - mode->height);\n-\t\t__v4l2_ctrl_s_ctrl(imx219->vblank,\n-\t\t\t\t   mode->vts_def - mode->height);\n-\t\t/* Update max exposure while meeting expected vblanking */\n-\t\texposure_max = mode->vts_def - 4;\n-\t\texposure_def = (exposure_max < IMX219_EXPOSURE_DEFAULT) ?\n-\t\t\texposure_max : IMX219_EXPOSURE_DEFAULT;\n-\t\t__v4l2_ctrl_modify_range(imx219->exposure,\n-\t\t\t\t\t imx219->exposure->minimum,\n-\t\t\t\t\t exposure_max, imx219->exposure->step,\n-\t\t\t\t\t exposure_def);\n-\t\t/*\n-\t\t * Currently PPL is fixed to IMX219_PPL_DEFAULT, so hblank\n-\t\t * depends on mode->width only, and is not changeble in any\n-\t\t * way other than changing the mode.\n-\t\t */\n-\t\thblank = IMX219_PPL_DEFAULT - mode->width;\n-\t\t__v4l2_ctrl_modify_range(imx219->hblank, hblank, hblank, 1,\n-\t\t\t\t\t hblank);\n+\tif (fmt->pad == IMAGE_PAD) {\n+\t\tfor (i = 0; i < ARRAY_SIZE(codes); i++)\n+\t\t\tif (codes[i] == fmt->format.code)\n+\t\t\t\tbreak;\n+\t\tif (i >= ARRAY_SIZE(codes))\n+\t\t\ti = 0;\n+\n+\t\t/* Bayer order varies with flips */\n+\t\tfmt->format.code = imx219_get_format_code(imx219, codes[i]);\n+\n+\t\tmode = v4l2_find_nearest_size(supported_modes,\n+\t\t\t\t\t      ARRAY_SIZE(supported_modes),\n+\t\t\t\t\t      width, height,\n+\t\t\t\t\t      fmt->format.width,\n+\t\t\t\t\t      fmt->format.height);\n+\t\timx219_update_image_pad_format(imx219, mode, fmt);\n+\t\tif (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {\n+\t\t\tframefmt = v4l2_subdev_get_try_format(sd, cfg,\n+\t\t\t\t\t\t\t      fmt->pad);\n+\t\t\t*framefmt = fmt->format;\n+\t\t} else if (imx219->mode != mode ||\n+\t\t\timx219->fmt.code != fmt->format.code) {\n+\t\t\timx219->fmt = fmt->format;\n+\t\t\timx219->mode = mode;\n+\t\t\t/* Update limits and set FPS to default */\n+\t\t\t__v4l2_ctrl_modify_range(imx219->vblank,\n+\t\t\t\t\t\t IMX219_VBLANK_MIN,\n+\t\t\t\t\t\t IMX219_VTS_MAX - mode->height,\n+\t\t\t\t\t\t 1,\n+\t\t\t\t\t\t mode->vts_def - mode->height);\n+\t\t\t__v4l2_ctrl_s_ctrl(imx219->vblank,\n+\t\t\t\t\t   mode->vts_def - mode->height);\n+\t\t\t/*\n+\t\t\t * Update max exposure while meeting\n+\t\t\t * expected vblanking\n+\t\t\t */\n+\t\t\texposure_max = mode->vts_def - 4;\n+\t\t\texposure_def =\n+\t\t\t\t(exposure_max < IMX219_EXPOSURE_DEFAULT) ?\n+\t\t\t\t\texposure_max : IMX219_EXPOSURE_DEFAULT;\n+\t\t\t__v4l2_ctrl_modify_range(imx219->exposure,\n+\t\t\t\t\t\t imx219->exposure->minimum,\n+\t\t\t\t\t\t exposure_max,\n+\t\t\t\t\t\t imx219->exposure->step,\n+\t\t\t\t\t\t exposure_def);\n+\t\t\t/*\n+\t\t\t * Currently PPL is fixed to IMX219_PPL_DEFAULT, so\n+\t\t\t * hblank depends on mode->width only, and is not\n+\t\t\t * changeble in any way other than changing the mode.\n+\t\t\t */\n+\t\t\thblank = IMX219_PPL_DEFAULT - mode->width;\n+\t\t\t__v4l2_ctrl_modify_range(imx219->hblank, hblank, hblank,\n+\t\t\t\t\t\t 1, hblank);\n+\t\t}\n+\t} else {\n+\t\tif (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {\n+\t\t\tframefmt = v4l2_subdev_get_try_format(sd, cfg,\n+\t\t\t\t\t\t\t      fmt->pad);\n+\t\t\t*framefmt = fmt->format;\n+\t\t} else {\n+\t\t\t/* Only one embedded data mode is supported */\n+\t\t\timx219_update_metadata_pad_format(fmt);\n+\t\t}\n \t}\n \n \tmutex_unlock(&imx219->mutex);\n@@ -1511,13 +1594,14 @@ static int imx219_probe(struct i2c_clien\n \timx219->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;\n \timx219->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;\n \n-\t/* Initialize source pad */\n-\timx219->pad.flags = MEDIA_PAD_FL_SOURCE;\n+\t/* Initialize source pads */\n+\timx219->pad[IMAGE_PAD].flags = MEDIA_PAD_FL_SOURCE;\n+\timx219->pad[METADATA_PAD].flags = MEDIA_PAD_FL_SOURCE;\n \n \t/* Initialize default format */\n \timx219_set_default_format(imx219);\n \n-\tret = media_entity_pads_init(&imx219->sd.entity, 1, &imx219->pad);\n+\tret = media_entity_pads_init(&imx219->sd.entity, NUM_PADS, imx219->pad);\n \tif (ret) {\n \t\tdev_err(dev, \"failed to init entity pads: %d\\n\", ret);\n \t\tgoto error_handler_free;\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0218-media-bcm2835-unicam-Re-fetch-mbus-code-from-subdev-.patch",
    "content": "From e2eb4940fd6b819d4db64e2822a2ffca7ee0a7f3 Mon Sep 17 00:00:00 2001\nFrom: Naushir Patuck <naush@raspberrypi.com>\nDate: Tue, 21 Apr 2020 16:26:03 +0100\nSubject: [PATCH] media: bcm2835-unicam: Re-fetch mbus code from subdev\n on a g_fmt call\n\nThe sensor subdevice may change the Bayer order if a H/V flip is\nrequested after a s_fmt call.  Unicam g_fmt must call the subdev get_fmt\nin case this has happened and return out the correct format 4cc.\n\nSigned-off-by: Naushir Patuck <naush@raspberrypi.com>\n---\n .../media/platform/bcm2835/bcm2835-unicam.c   | 21 ++++++++++++++++++-\n 1 file changed, 20 insertions(+), 1 deletion(-)\n\n--- a/drivers/media/platform/bcm2835/bcm2835-unicam.c\n+++ b/drivers/media/platform/bcm2835/bcm2835-unicam.c\n@@ -967,11 +967,30 @@ static int unicam_enum_fmt_vid_cap(struc\n static int unicam_g_fmt_vid_cap(struct file *file, void *priv,\n \t\t\t\tstruct v4l2_format *f)\n {\n+\tstruct v4l2_mbus_framefmt mbus_fmt = {0};\n \tstruct unicam_node *node = video_drvdata(file);\n+\tstruct unicam_device *dev = node->dev;\n+\tconst struct unicam_fmt *fmt = NULL;\n+\tint ret;\n \n-\tif (node->pad_id == METADATA_PAD)\n+\tif (node->pad_id != IMAGE_PAD)\n \t\treturn -EINVAL;\n \n+\t/*\n+\t * If a flip has occurred in the sensor, the fmt code might have\n+\t * changed. So we will need to re-fetch the format from the subdevice.\n+\t */\n+\tret = __subdev_get_format(dev, &mbus_fmt, node->pad_id);\n+\tif (ret)\n+\t\treturn -EINVAL;\n+\n+\t/* Find the V4L2 format from mbus code. We must match a known format. */\n+\tfmt = find_format_by_code(mbus_fmt.code);\n+\tif (!fmt)\n+\t\treturn -EINVAL;\n+\n+\tnode->fmt = fmt;\n+\tnode->v_fmt.fmt.pix.pixelformat = fmt->fourcc;\n \t*f = node->v_fmt;\n \n \treturn 0;\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0219-media-uapi-v4l2-core-Add-ISP-statistics-output-V4L2-.patch",
    "content": "From 4e9d4f3927e2e9b5fae5fefe4faf82d5ecfc86cd Mon Sep 17 00:00:00 2001\nFrom: Naushir Patuck <naush@raspberrypi.com>\nDate: Thu, 23 Apr 2020 10:20:26 +0100\nSubject: [PATCH] media: uapi: v4l2-core: Add ISP statistics output\n V4L2 fourcc type\n\nAdd V4L2_META_FMT_BCM2835_ISP_STATS V4L2 format type.\n\nThis new format will be used by the BCM2835 ISP device to return\nout ISP statistics for 3A.\n\nSigned-off-by: Naushir Patuck <naush@raspberrypi.com>\n---\n .../userspace-api/media/v4l/meta-formats.rst  |  1 +\n .../v4l/pixfmt-meta-bcm2835-isp-stats.rst     | 41 +++++++++++++++++++\n drivers/media/v4l2-core/v4l2-ioctl.c          |  1 +\n include/uapi/linux/videodev2.h                |  1 +\n 4 files changed, 44 insertions(+)\n create mode 100644 Documentation/userspace-api/media/v4l/pixfmt-meta-bcm2835-isp-stats.rst\n\n--- a/Documentation/userspace-api/media/v4l/meta-formats.rst\n+++ b/Documentation/userspace-api/media/v4l/meta-formats.rst\n@@ -12,6 +12,7 @@ These formats are used for the :ref:`met\n .. toctree::\n     :maxdepth: 1\n \n+    pixfmt-meta-bcm2835-isp-stats\n     pixfmt-meta-d4xx\n     pixfmt-meta-intel-ipu3\n     pixfmt-meta-rkisp1\n--- /dev/null\n+++ b/Documentation/userspace-api/media/v4l/pixfmt-meta-bcm2835-isp-stats.rst\n@@ -0,0 +1,41 @@\n+.. Permission is granted to copy, distribute and/or modify this\n+.. document under the terms of the GNU Free Documentation License,\n+.. Version 1.1 or any later version published by the Free Software\n+.. Foundation, with no Invariant Sections, no Front-Cover Texts\n+.. and no Back-Cover Texts. A copy of the license is included at\n+.. Documentation/media/uapi/fdl-appendix.rst.\n+..\n+.. TODO: replace it to GFDL-1.1-or-later WITH no-invariant-sections\n+\n+.. _v4l2-meta-fmt-bcm2835-isp-stats:\n+\n+*****************************************\n+V4L2_META_FMT_BCM2835_ISP_STATS  ('BSTA')\n+*****************************************\n+\n+BCM2835 ISP Statistics\n+\n+Description\n+===========\n+\n+The BCM2835 ISP hardware calculate image statistics for an input Bayer frame.\n+These statistics are obtained from the \"bcm2835-isp0-capture3\" device node\n+using the :c:type:`v4l2_meta_format` interface. They are formatted as described\n+by the :c:type:`bcm2835_isp_stats` structure below.\n+\n+.. code-block:: c\n+\n+\t#define DEFAULT_AWB_REGIONS_X 16\n+\t#define DEFAULT_AWB_REGIONS_Y 12\n+\n+\t#define NUM_HISTOGRAMS 2\n+\t#define NUM_HISTOGRAM_BINS 128\n+\t#define AWB_REGIONS (DEFAULT_AWB_REGIONS_X * DEFAULT_AWB_REGIONS_Y)\n+\t#define FLOATING_REGIONS 16\n+\t#define AGC_REGIONS 16\n+\t#define FOCUS_REGIONS 12\n+\n+.. kernel-doc:: include/uapi/linux/bcm2835-isp.h\n+   :functions: bcm2835_isp_stats_hist bcm2835_isp_stats_region\n+\t             bcm2835_isp_stats_focus bcm2835_isp_stats\n+\n--- a/drivers/media/v4l2-core/v4l2-ioctl.c\n+++ b/drivers/media/v4l2-core/v4l2-ioctl.c\n@@ -1423,6 +1423,7 @@ static void v4l_fill_fmtdesc(struct v4l2\n \tcase V4L2_META_FMT_D4XX:\tdescr = \"Intel D4xx UVC Metadata\"; break;\n \tcase V4L2_META_FMT_VIVID:       descr = \"Vivid Metadata\"; break;\n \tcase V4L2_META_FMT_SENSOR_DATA:\tdescr = \"Sensor Ancillary Metadata\"; break;\n+\tcase V4L2_META_FMT_BCM2835_ISP_STATS: descr = \"BCM2835 ISP Image Statistics\"; break;\n \n \tdefault:\n \t\t/* Compressed formats */\n--- a/include/uapi/linux/videodev2.h\n+++ b/include/uapi/linux/videodev2.h\n@@ -779,6 +779,7 @@ struct v4l2_pix_format {\n #define V4L2_META_FMT_D4XX        v4l2_fourcc('D', '4', 'X', 'X') /* D4XX Payload Header metadata */\n #define V4L2_META_FMT_VIVID\t  v4l2_fourcc('V', 'I', 'V', 'D') /* Vivid Metadata */\n #define V4L2_META_FMT_SENSOR_DATA v4l2_fourcc('S', 'E', 'N', 'S') /* Sensor Ancillary metadata */\n+#define V4L2_META_FMT_BCM2835_ISP_STATS v4l2_fourcc('B', 'S', 'T', 'A') /* BCM2835 ISP image statistics output */\n \n /* priv field value to indicates that subsequent fields are valid. */\n #define V4L2_PIX_FMT_PRIV_MAGIC\t\t0xfeedcafe\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0220-media-uapi-v4l-ctrls-Add-CID-base-for-the-bcm2835-is.patch",
    "content": "From 1dccb28000e0b12b5796a682f1995bdf0f38f7e5 Mon Sep 17 00:00:00 2001\nFrom: Naushir Patuck <naush@raspberrypi.com>\nDate: Tue, 21 Apr 2020 15:06:19 +0100\nSubject: [PATCH] media: uapi: v4l-ctrls: Add CID base for the\n bcm2835-isp driver\n\nWe are reserving controls for the new bcm2835-isp driver.\n\nSigned-off-by: Naushir Patuck <naush@raspberrypi.com>\n---\n .../admin-guide/media/bcm2835-isp.rst         | 127 ++++++++++++++++++\n .../userspace-api/media/drivers/index.rst     |   1 +\n include/uapi/linux/v4l2-controls.h            |   4 +\n 3 files changed, 132 insertions(+)\n create mode 100644 Documentation/admin-guide/media/bcm2835-isp.rst\n\n--- /dev/null\n+++ b/Documentation/admin-guide/media/bcm2835-isp.rst\n@@ -0,0 +1,127 @@\n+.. SPDX-License-Identifier: GPL-2.0\n+\n+BCM2835 ISP Driver\n+==================\n+\n+Introduction\n+------------\n+\n+The BCM2835 Image Sensor Pipeline (ISP) is a fixed function hardware pipeline\n+for performing image processing operations.  Images are fed to the input\n+of the ISP through memory frame buffers.  These images may be in various YUV,\n+RGB, or Bayer formats.  A typical use case would have Bayer images obtained from\n+an image sensor by the BCM2835 Unicam peripheral, written to a memory\n+frame buffer, and finally fed into the input of the ISP.  Two concurrent output\n+images may be generated in YUV or RGB format at different resolutions.\n+Statistics output is also generated for Bayer input images.\n+\n+The bcm2835-isp driver exposes the following media pads as V4L2 device nodes:\n+\n+.. tabularcolumns:: |l|l|l|l|\n+\n+.. cssclass: longtable\n+\n+.. flat-table::\n+\n+    * - *Pad*\n+      - *Direction*\n+      - *Purpose*\n+      - *Formats*\n+\n+    * - \"bcm2835-isp0-output0\"\n+      - sink\n+      - Accepts Bayer, RGB or YUV format frame buffers as input to the ISP HW\n+        pipeline.\n+      - :ref:`RAW8 <V4L2-PIX-FMT-SRGGB8>`,\n+        :ref:`RAW10P <V4L2-PIX-FMT-SRGGB10P>`,\n+        :ref:`RAW12P <V4L2-PIX-FMT-SRGGB12P>`,\n+        :ref:`RAW14P <V4L2-PIX-FMT-SRGGB14P>`,\n+        :ref:`RAW16 <V4L2-PIX-FMT-SRGGB16>`,\n+        :ref:`RGB24/BGR24 <V4L2-PIX-FMT-RGB24>`,\n+        :ref:`YUYV <V4L2-PIX-FMT-YUYV>`,\n+        :ref:`YVYU <V4L2-PIX-FMT-YVYU>`,\n+        :ref:`UYVY <V4L2-PIX-FMT-UYVY>`,\n+        :ref:`VYUY <V4L2-PIX-FMT-VYUY>`,\n+        :ref:`YUV420/YVU420 <V4L2-PIX-FMT-YUV420>`\n+\n+    * - \"bcm2835-isp0-capture1\"\n+      - source\n+      - High resolution YUV or RGB processed output from the ISP.\n+      - :ref:`RGB565 <V4L2-PIX-FMT-RGB565>`,\n+        :ref:`RGB24/BGR24 <V4L2-PIX-FMT-RGB24>`,\n+        :ref:`ABGR32 <V4L2-PIX-FMT-ABGR32>`,\n+        :ref:`YUYV <V4L2-PIX-FMT-YUYV>`,\n+        :ref:`YVYU <V4L2-PIX-FMT-YVYU>`,\n+        :ref:`UYVY <V4L2-PIX-FMT-UYVY>`,\n+        :ref:`VYUY <V4L2-PIX-FMT-VYUY>`.\n+        :ref:`YUV420/YVU420 <V4L2-PIX-FMT-YUV420>`,\n+        :ref:`NV12/NV21 <V4L2-PIX-FMT-NV12>`,\n+\n+    * - \"bcm2835-isp0-capture2\"\n+      - source\n+      - Low resolution YUV processed output from the ISP. The output of\n+        this pad cannot have a resolution larger than the \"bcm2835-isp0-capture1\" pad in any dimension.\n+      - :ref:`YUYV <V4L2-PIX-FMT-YUYV>`,\n+        :ref:`YVYU <V4L2-PIX-FMT-YVYU>`,\n+        :ref:`UYVY <V4L2-PIX-FMT-UYVY>`,\n+        :ref:`VYUY <V4L2-PIX-FMT-VYUY>`.\n+        :ref:`YUV420/YVU420 <V4L2-PIX-FMT-YUV420>`,\n+        :ref:`NV12/NV21 <V4L2-PIX-FMT-NV12>`,\n+\n+    * - \"bcm2835-isp0-capture1\"\n+      - source\n+      - Image statistics calculated from the input image provided on the\n+        \"bcm2835-isp0-output0\" pad.  Statistics are only available for Bayer\n+        format input images.\n+      - :ref:`v4l2-meta-fmt-bcm2835-isp-stats`.\n+\n+Pipeline Configuration\n+----------------------\n+\n+The ISP pipeline can be configure through user-space by calling\n+:ref:`VIDIOC_S_EXT_CTRLS <VIDIOC_G_EXT_CTRLS>` on the “bcm2835-isp0-output0”\n+node with the appropriate parameters as shown in the table below.\n+\n+.. tabularcolumns:: |p{2cm}|p{5.0cm}|\n+\n+.. cssclass: longtable\n+\n+.. flat-table::\n+\n+    * - *id*\n+      - *Parameter*\n+\n+    * - ``V4L2_CID_USER_BCM2835_ISP_CC_MATRIX``\n+      - struct :c:type:`bcm2835_isp_custom_ccm`\n+\n+    * - ``V4L2_CID_USER_BCM2835_ISP_LENS_SHADING``\n+      - struct :c:type:`bcm2835_isp_lens_shading`\n+\n+    * - ``V4L2_CID_USER_BCM2835_ISP_BLACK_LEVEL``\n+      - struct :c:type:`bcm2835_isp_black_level`\n+\n+    * - ``V4L2_CID_USER_BCM2835_ISP_GEQ``\n+      - struct :c:type:`bcm2835_isp_geq`\n+\n+    * - ``V4L2_CID_USER_BCM2835_ISP_GAMMA``\n+      - struct :c:type:`bcm2835_isp_gamma`\n+\n+    * - ``V4L2_CID_USER_BCM2835_ISP_DENOISE``\n+      - struct :c:type:`bcm2835_isp_denoise`\n+\n+    * - ``V4L2_CID_USER_BCM2835_ISP_SHARPEN``\n+      - struct :c:type:`bcm2835_isp_sharpen`\n+\n+    * - ``V4L2_CID_USER_BCM2835_ISP_DPC``\n+      - struct :c:type:`bcm2835_isp_dpc`\n+\n+++++++++++++++++++++++++\n+Configuration Parameters\n+++++++++++++++++++++++++\n+\n+.. kernel-doc:: include/uapi/linux/bcm2835-isp.h\n+   :functions: bcm2835_isp_rational bcm2835_isp_ccm bcm2835_isp_custom_ccm\n+                bcm2835_isp_gain_format bcm2835_isp_lens_shading\n+                bcm2835_isp_black_level bcm2835_isp_geq bcm2835_isp_gamma\n+                bcm2835_isp_denoise bcm2835_isp_sharpen\n+                bcm2835_isp_dpc_mode bcm2835_isp_dpc\n--- a/Documentation/userspace-api/media/drivers/index.rst\n+++ b/Documentation/userspace-api/media/drivers/index.rst\n@@ -33,6 +33,7 @@ For more details see the file COPYING in\n \n \tcx2341x-uapi\n \timx-uapi\n+\tbcm2835-isp\n \tmax2175\n \tmeye-uapi\n \tomap3isp-uapi\n--- a/include/uapi/linux/v4l2-controls.h\n+++ b/include/uapi/linux/v4l2-controls.h\n@@ -198,6 +198,10 @@ enum v4l2_colorfx {\n  */\n #define V4L2_CID_USER_ATMEL_ISC_BASE\t\t(V4L2_CID_USER_BASE + 0x10c0)\n \n+/* The base for the bcm2835-isp driver controls.\n+ * We reserve 16 controls for this driver. */\n+#define V4L2_CID_USER_BCM2835_ISP_BASE\t\t(V4L2_CID_USER_BASE + 0x10e0)\n+\n /* MPEG-class control IDs */\n /* The MPEG controls are applicable to all codec controls\n  * and the 'MPEG' part of the define is historical */\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0221-staging-vchiq-Load-bcm2835_isp-driver-from-vchiq.patch",
    "content": "From c05548e7942540ef85c096853d56114816e92a39 Mon Sep 17 00:00:00 2001\nFrom: Naushir Patuck <naush@raspberrypi.com>\nDate: Wed, 22 Apr 2020 08:32:32 +0100\nSubject: [PATCH] staging: vchiq: Load bcm2835_isp driver from vchiq\n\nbcmn2835_isp is a platform driver dependent on vchiq,\ntherefore add the load/unload functions for it to vchiq.\n\nSigned-off-by: Naushir Patuck <naush@raspberrypi.com>\n---\n drivers/staging/vc04_services/interface/vchiq_arm/vchiq_arm.c | 3 +++\n 1 file changed, 3 insertions(+)\n\n--- a/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_arm.c\n+++ b/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_arm.c\n@@ -111,6 +111,7 @@ static struct platform_device *bcm2835_c\n static struct platform_device *bcm2835_audio;\n static struct platform_device *bcm2835_codec;\n static struct platform_device *vcsm_cma;\n+static struct platform_device *bcm2835_isp;\n \n static struct vchiq_drvdata bcm2835_drvdata = {\n \t.cache_line_size = 32,\n@@ -2796,6 +2797,7 @@ static int vchiq_probe(struct platform_d\n \tbcm2835_codec = vchiq_register_child(pdev, \"bcm2835-codec\");\n \tbcm2835_camera = vchiq_register_child(pdev, \"bcm2835-camera\");\n \tbcm2835_audio = vchiq_register_child(pdev, \"bcm2835_audio\");\n+\tbcm2835_isp = vchiq_register_child(pdev, \"bcm2835-isp\");\n \n \treturn 0;\n \n@@ -2808,6 +2810,7 @@ failed_platform_init:\n \n static int vchiq_remove(struct platform_device *pdev)\n {\n+\tplatform_device_unregister(bcm2835_isp);\n \tplatform_device_unregister(bcm2835_audio);\n \tplatform_device_unregister(bcm2835_camera);\n \tplatform_device_unregister(bcm2835_codec);\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0222-bcm2835-dma-Add-proper-40-bit-DMA-support.patch",
    "content": "From e53a536e7a182f97adf5394c4ef621a30adf6543 Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.org>\nDate: Thu, 4 Apr 2019 13:33:47 +0100\nSubject: [PATCH] bcm2835-dma: Add proper 40-bit DMA support\n\nBCM2711 has 4 DMA channels with a 40-bit address range, allowing them\nto access the full 4GB of memory on a Pi 4.\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.org>\n---\n drivers/dma/bcm2835-dma.c | 485 ++++++++++++++++++++++++++++++++------\n 1 file changed, 412 insertions(+), 73 deletions(-)\n\n--- a/drivers/dma/bcm2835-dma.c\n+++ b/drivers/dma/bcm2835-dma.c\n@@ -38,6 +38,11 @@\n #define BCM2835_DMA_MAX_DMA_CHAN_SUPPORTED 14\n #define BCM2835_DMA_CHAN_NAME_SIZE 8\n #define BCM2835_DMA_BULK_MASK  BIT(0)\n+#define BCM2711_DMA_MEMCPY_CHAN 14\n+\n+struct bcm2835_dma_cfg_data {\n+\tu32\tchan_40bit_mask;\n+};\n \n /**\n  * struct bcm2835_dmadev - BCM2835 DMA controller\n@@ -50,6 +55,7 @@ struct bcm2835_dmadev {\n \tstruct dma_device ddev;\n \tvoid __iomem *base;\n \tdma_addr_t zero_page;\n+\tconst struct bcm2835_dma_cfg_data *cfg_data;\n };\n \n struct bcm2835_dma_cb {\n@@ -62,6 +68,17 @@ struct bcm2835_dma_cb {\n \tuint32_t pad[2];\n };\n \n+struct bcm2711_dma40_scb {\n+\tuint32_t ti;\n+\tuint32_t src;\n+\tuint32_t srci;\n+\tuint32_t dst;\n+\tuint32_t dsti;\n+\tuint32_t len;\n+\tuint32_t next_cb;\n+\tuint32_t rsvd;\n+};\n+\n struct bcm2835_cb_entry {\n \tstruct bcm2835_dma_cb *cb;\n \tdma_addr_t paddr;\n@@ -82,6 +99,7 @@ struct bcm2835_chan {\n \tunsigned int irq_flags;\n \n \tbool is_lite_channel;\n+\tbool is_40bit_channel;\n };\n \n struct bcm2835_desc {\n@@ -171,13 +189,118 @@ struct bcm2835_desc {\n #define BCM2835_DMA_DATA_TYPE_S128\t16\n \n /* Valid only for channels 0 - 14, 15 has its own base address */\n-#define BCM2835_DMA_CHAN(n)\t((n) << 8) /* Base address */\n+#define BCM2835_DMA_CHAN_SIZE\t0x100\n+#define BCM2835_DMA_CHAN(n)\t((n) * BCM2835_DMA_CHAN_SIZE) /* Base address */\n #define BCM2835_DMA_CHANIO(base, n) ((base) + BCM2835_DMA_CHAN(n))\n \n /* the max dma length for different channels */\n #define MAX_DMA_LEN SZ_1G\n #define MAX_LITE_DMA_LEN (SZ_64K - 4)\n \n+/* 40-bit DMA support */\n+#define BCM2711_DMA40_CS\t0x00\n+#define BCM2711_DMA40_CB\t0x04\n+#define BCM2711_DMA40_DEBUG\t0x0c\n+#define BCM2711_DMA40_TI\t0x10\n+#define BCM2711_DMA40_SRC\t0x14\n+#define BCM2711_DMA40_SRCI\t0x18\n+#define BCM2711_DMA40_DEST\t0x1c\n+#define BCM2711_DMA40_DESTI\t0x20\n+#define BCM2711_DMA40_LEN\t0x24\n+#define BCM2711_DMA40_NEXT_CB\t0x28\n+#define BCM2711_DMA40_DEBUG2\t0x2c\n+\n+#define BCM2711_DMA40_ACTIVE\t\tBIT(0)\n+#define BCM2711_DMA40_END\t\tBIT(1)\n+#define BCM2711_DMA40_INT\t\tBIT(2)\n+#define BCM2711_DMA40_DREQ\t\tBIT(3)  /* DREQ state */\n+#define BCM2711_DMA40_RD_PAUSED\t\tBIT(4)  /* Reading is paused */\n+#define BCM2711_DMA40_WR_PAUSED\t\tBIT(5)  /* Writing is paused */\n+#define BCM2711_DMA40_DREQ_PAUSED\tBIT(6)  /* Is paused by DREQ flow control */\n+#define BCM2711_DMA40_WAITING_FOR_WRITES BIT(7)  /* Waiting for last write */\n+#define BCM2711_DMA40_ERR\t\tBIT(10)\n+#define BCM2711_DMA40_QOS(x)\t\t(((x) & 0x1f) << 16)\n+#define BCM2711_DMA40_PANIC_QOS(x)\t(((x) & 0x1f) << 20)\n+#define BCM2711_DMA40_WAIT_FOR_WRITES\tBIT(28)\n+#define BCM2711_DMA40_DISDEBUG\t\tBIT(29)\n+#define BCM2711_DMA40_ABORT\t\tBIT(30)\n+#define BCM2711_DMA40_HALT\t\tBIT(31)\n+#define BCM2711_DMA40_CS_FLAGS(x) (x & (BCM2711_DMA40_QOS(15) | \\\n+\t\t\t\t\tBCM2711_DMA40_PANIC_QOS(15) | \\\n+\t\t\t\t\tBCM2711_DMA40_WAIT_FOR_WRITES |\t\\\n+\t\t\t\t\tBCM2711_DMA40_DISDEBUG))\n+\n+/* Transfer information bits */\n+#define BCM2711_DMA40_INTEN\t\tBIT(0)\n+#define BCM2711_DMA40_TDMODE\t\tBIT(1) /* 2D-Mode */\n+#define BCM2711_DMA40_WAIT_RESP\t\tBIT(2) /* wait for AXI write to be acked */\n+#define BCM2711_DMA40_WAIT_RD_RESP\tBIT(3) /* wait for AXI read to complete */\n+#define BCM2711_DMA40_PER_MAP(x)\t((x & 31) << 9) /* REQ source */\n+#define BCM2711_DMA40_S_DREQ\t\tBIT(14) /* enable SREQ for source */\n+#define BCM2711_DMA40_D_DREQ\t\tBIT(15) /* enable DREQ for destination */\n+#define BCM2711_DMA40_S_WAIT(x)\t\t((x & 0xff) << 16) /* add DMA read-wait cycles */\n+#define BCM2711_DMA40_D_WAIT(x)\t\t((x & 0xff) << 24) /* add DMA write-wait cycles */\n+\n+/* debug register bits */\n+#define BCM2711_DMA40_DEBUG_WRITE_ERR\t\tBIT(0)\n+#define BCM2711_DMA40_DEBUG_FIFO_ERR\t\tBIT(1)\n+#define BCM2711_DMA40_DEBUG_READ_ERR\t\tBIT(2)\n+#define BCM2711_DMA40_DEBUG_READ_CB_ERR\t\tBIT(3)\n+#define BCM2711_DMA40_DEBUG_IN_ON_ERR\t\tBIT(8)\n+#define BCM2711_DMA40_DEBUG_ABORT_ON_ERR\tBIT(9)\n+#define BCM2711_DMA40_DEBUG_HALT_ON_ERR\t\tBIT(10)\n+#define BCM2711_DMA40_DEBUG_DISABLE_CLK_GATE\tBIT(11)\n+#define BCM2711_DMA40_DEBUG_RSTATE_SHIFT\t14\n+#define BCM2711_DMA40_DEBUG_RSTATE_BITS\t\t4\n+#define BCM2711_DMA40_DEBUG_WSTATE_SHIFT\t18\n+#define BCM2711_DMA40_DEBUG_WSTATE_BITS\t\t4\n+#define BCM2711_DMA40_DEBUG_RESET\t\tBIT(23)\n+#define BCM2711_DMA40_DEBUG_ID_SHIFT\t\t24\n+#define BCM2711_DMA40_DEBUG_ID_BITS\t\t4\n+#define BCM2711_DMA40_DEBUG_VERSION_SHIFT\t28\n+#define BCM2711_DMA40_DEBUG_VERSION_BITS\t4\n+\n+/* Valid only for channels 0 - 3 (11 - 14) */\n+#define BCM2711_DMA40_CHAN(n)\t(((n) + 11) << 8) /* Base address */\n+#define BCM2711_DMA40_CHANIO(base, n) ((base) + BCM2711_DMA_CHAN(n))\n+\n+/* the max dma length for different channels */\n+#define MAX_DMA40_LEN SZ_1G\n+\n+#define BCM2711_DMA40_BURST_LEN(x)\t((min(x,16) - 1) << 8)\n+#define BCM2711_DMA40_INC\t\tBIT(12)\n+#define BCM2711_DMA40_SIZE_32\t\t(0 << 13)\n+#define BCM2711_DMA40_SIZE_64\t\t(1 << 13)\n+#define BCM2711_DMA40_SIZE_128\t\t(2 << 13)\n+#define BCM2711_DMA40_SIZE_256\t\t(3 << 13)\n+#define BCM2711_DMA40_IGNORE\t\tBIT(15)\n+#define BCM2711_DMA40_STRIDE(x)\t\t((x) << 16) /* For 2D mode */\n+\n+#define BCM2711_DMA40_MEMCPY_FLAGS \\\n+\t(BCM2711_DMA40_QOS(0) | \\\n+\t BCM2711_DMA40_PANIC_QOS(0) | \\\n+\t BCM2711_DMA40_WAIT_FOR_WRITES | \\\n+\t BCM2711_DMA40_DISDEBUG)\n+\n+#define BCM2711_DMA40_MEMCPY_XFER_INFO \\\n+\t(BCM2711_DMA40_SIZE_128 | \\\n+\t BCM2711_DMA40_INC | \\\n+\t BCM2711_DMA40_BURST_LEN(16))\n+\n+struct bcm2835_dmadev *memcpy_parent;\n+static void __iomem *memcpy_chan;\n+static struct bcm2711_dma40_scb *memcpy_scb;\n+static dma_addr_t memcpy_scb_dma;\n+DEFINE_SPINLOCK(memcpy_lock);\n+\n+static const struct bcm2835_dma_cfg_data bcm2835_dma_cfg = {\n+\t.chan_40bit_mask = 0,\n+};\n+\n+static const struct bcm2835_dma_cfg_data bcm2711_dma_cfg = {\n+\t.chan_40bit_mask = BIT(11) | BIT(12) | BIT(13) | BIT(14),\n+};\n+\n static inline size_t bcm2835_dma_max_frame_length(struct bcm2835_chan *c)\n {\n \t/* lite and normal channels have different max frame length */\n@@ -207,6 +330,32 @@ static inline struct bcm2835_desc *to_bc\n \treturn container_of(t, struct bcm2835_desc, vd.tx);\n }\n \n+static inline uint32_t to_bcm2711_ti(uint32_t info)\n+{\n+\treturn ((info & BCM2835_DMA_INT_EN) ? BCM2711_DMA40_INTEN : 0) |\n+\t\t((info & BCM2835_DMA_WAIT_RESP) ? BCM2711_DMA40_WAIT_RESP : 0) |\n+\t\t((info & BCM2835_DMA_S_DREQ) ?\n+\t\t (BCM2711_DMA40_S_DREQ | BCM2711_DMA40_WAIT_RD_RESP) : 0) |\n+\t\t((info & BCM2835_DMA_D_DREQ) ? BCM2711_DMA40_D_DREQ : 0) |\n+\t\tBCM2711_DMA40_PER_MAP((info >> 16) & 0x1f);\n+}\n+\n+static inline uint32_t to_bcm2711_srci(uint32_t info)\n+{\n+\treturn ((info & BCM2835_DMA_S_INC) ? BCM2711_DMA40_INC : 0);\n+}\n+\n+static inline uint32_t to_bcm2711_dsti(uint32_t info)\n+{\n+\treturn ((info & BCM2835_DMA_D_INC) ? BCM2711_DMA40_INC : 0);\n+}\n+\n+static inline uint32_t to_bcm2711_cbaddr(dma_addr_t addr)\n+{\n+\tBUG_ON(addr & 0x1f);\n+\treturn (addr >> 5);\n+}\n+\n static void bcm2835_dma_free_cb_chain(struct bcm2835_desc *desc)\n {\n \tsize_t i;\n@@ -225,45 +374,53 @@ static void bcm2835_dma_desc_free(struct\n }\n \n static void bcm2835_dma_create_cb_set_length(\n-\tstruct bcm2835_chan *chan,\n+\tstruct bcm2835_chan *c,\n \tstruct bcm2835_dma_cb *control_block,\n \tsize_t len,\n \tsize_t period_len,\n \tsize_t *total_len,\n \tu32 finalextrainfo)\n {\n-\tsize_t max_len = bcm2835_dma_max_frame_length(chan);\n+\tsize_t max_len = bcm2835_dma_max_frame_length(c);\n+\tuint32_t cb_len;\n \n \t/* set the length taking lite-channel limitations into account */\n-\tcontrol_block->length = min_t(u32, len, max_len);\n+\tcb_len = min_t(u32, len, max_len);\n \n-\t/* finished if we have no period_length */\n-\tif (!period_len)\n-\t\treturn;\n+\tif (period_len) {\n+\t\t/*\n+\t\t * period_len means: that we need to generate\n+\t\t * transfers that are terminating at every\n+\t\t * multiple of period_len - this is typically\n+\t\t * used to set the interrupt flag in info\n+\t\t * which is required during cyclic transfers\n+\t\t */\n \n-\t/*\n-\t * period_len means: that we need to generate\n-\t * transfers that are terminating at every\n-\t * multiple of period_len - this is typically\n-\t * used to set the interrupt flag in info\n-\t * which is required during cyclic transfers\n-\t */\n+\t\t/* have we filled in period_length yet? */\n+\t\tif (*total_len + cb_len < period_len) {\n+\t\t\t/* update number of bytes in this period so far */\n+\t\t\t*total_len += cb_len;\n+\t\t} else {\n+\t\t\t/* calculate the length that remains to reach period_len */\n+\t\t\tcb_len = period_len - *total_len;\n \n-\t/* have we filled in period_length yet? */\n-\tif (*total_len + control_block->length < period_len) {\n-\t\t/* update number of bytes in this period so far */\n-\t\t*total_len += control_block->length;\n-\t\treturn;\n+\t\t\t/* reset total_length for next period */\n+\t\t\t*total_len = 0;\n+\t\t}\n \t}\n \n-\t/* calculate the length that remains to reach period_length */\n-\tcontrol_block->length = period_len - *total_len;\n-\n-\t/* reset total_length for next period */\n-\t*total_len = 0;\n-\n-\t/* add extrainfo bits in info */\n-\tcontrol_block->info |= finalextrainfo;\n+\tif (c->is_40bit_channel) {\n+\t\tstruct bcm2711_dma40_scb *scb =\n+\t\t\t(struct bcm2711_dma40_scb *)control_block;\n+\n+\t\tscb->len = cb_len;\n+\t\t/* add extrainfo bits to ti */\n+\t\tscb->ti |= to_bcm2711_ti(finalextrainfo);\n+\t} else {\n+\t\tcontrol_block->length = cb_len;\n+\t\t/* add extrainfo bits to info */\n+\t\tcontrol_block->info |= finalextrainfo;\n+\t}\n }\n \n static inline size_t bcm2835_dma_count_frames_for_sg(\n@@ -286,7 +443,7 @@ static inline size_t bcm2835_dma_count_f\n /**\n  * bcm2835_dma_create_cb_chain - create a control block and fills data in\n  *\n- * @chan:           the @dma_chan for which we run this\n+ * @c:              the @bcm2835_chan for which we run this\n  * @direction:      the direction in which we transfer\n  * @cyclic:         it is a cyclic transfer\n  * @info:           the default info bits to apply per controlblock\n@@ -304,12 +461,11 @@ static inline size_t bcm2835_dma_count_f\n  * @gfp:            the GFP flag to use for allocation\n  */\n static struct bcm2835_desc *bcm2835_dma_create_cb_chain(\n-\tstruct dma_chan *chan, enum dma_transfer_direction direction,\n+\tstruct bcm2835_chan *c, enum dma_transfer_direction direction,\n \tbool cyclic, u32 info, u32 finalextrainfo, size_t frames,\n \tdma_addr_t src, dma_addr_t dst, size_t buf_len,\n \tsize_t period_len, gfp_t gfp)\n {\n-\tstruct bcm2835_chan *c = to_bcm2835_dma_chan(chan);\n \tsize_t len = buf_len, total_len;\n \tsize_t frame;\n \tstruct bcm2835_desc *d;\n@@ -341,11 +497,23 @@ static struct bcm2835_desc *bcm2835_dma_\n \n \t\t/* fill in the control block */\n \t\tcontrol_block = cb_entry->cb;\n-\t\tcontrol_block->info = info;\n-\t\tcontrol_block->src = src;\n-\t\tcontrol_block->dst = dst;\n-\t\tcontrol_block->stride = 0;\n-\t\tcontrol_block->next = 0;\n+\t\tif (c->is_40bit_channel) {\n+\t\t\tstruct bcm2711_dma40_scb *scb =\n+\t\t\t\t(struct bcm2711_dma40_scb *)control_block;\n+\t\t\tscb->ti = to_bcm2711_ti(info);\n+\t\t\tscb->src = lower_32_bits(src);\n+\t\t\tscb->srci= upper_32_bits(src) | to_bcm2711_srci(info);\n+\t\t\tscb->dst = lower_32_bits(dst);\n+\t\t\tscb->dsti = upper_32_bits(dst) | to_bcm2711_dsti(info);\n+\t\t\tscb->next_cb = 0;\n+\t\t} else {\n+\t\t\tcontrol_block->info = info;\n+\t\t\tcontrol_block->src = src;\n+\t\t\tcontrol_block->dst = dst;\n+\t\t\tcontrol_block->stride = 0;\n+\t\t\tcontrol_block->next = 0;\n+\t\t}\n+\n \t\t/* set up length in control_block if requested */\n \t\tif (buf_len) {\n \t\t\t/* calculate length honoring period_length */\n@@ -359,7 +527,11 @@ static struct bcm2835_desc *bcm2835_dma_\n \t\t}\n \n \t\t/* link this the last controlblock */\n-\t\tif (frame)\n+\t\tif (frame && c->is_40bit_channel)\n+\t\t\t((struct bcm2711_dma40_scb *)\n+\t\t\t d->cb_list[frame - 1].cb)->next_cb =\n+\t\t\t\tto_bcm2711_cbaddr(cb_entry->paddr);\n+\t\tif (frame && !c->is_40bit_channel)\n \t\t\td->cb_list[frame - 1].cb->next = cb_entry->paddr;\n \n \t\t/* update src and dst and length */\n@@ -369,11 +541,21 @@ static struct bcm2835_desc *bcm2835_dma_\n \t\t\tdst += control_block->length;\n \n \t\t/* Length of total transfer */\n-\t\td->size += control_block->length;\n+\t\tif (c->is_40bit_channel)\n+\t\t\td->size += ((struct bcm2711_dma40_scb *)control_block)->len;\n+\t\telse\n+\t\t\td->size += control_block->length;\n \t}\n \n \t/* the last frame requires extra flags */\n-\td->cb_list[d->frames - 1].cb->info |= finalextrainfo;\n+\tif (c->is_40bit_channel) {\n+\t\tstruct bcm2711_dma40_scb *scb =\n+\t\t\t(struct bcm2711_dma40_scb *)d->cb_list[d->frames-1].cb;\n+\n+\t\tscb->ti |= to_bcm2711_ti(finalextrainfo);\n+\t} else {\n+\t\td->cb_list[d->frames - 1].cb->info |= finalextrainfo;\n+\t}\n \n \t/* detect a size missmatch */\n \tif (buf_len && (d->size != buf_len))\n@@ -387,13 +569,12 @@ error_cb:\n }\n \n static void bcm2835_dma_fill_cb_chain_with_sg(\n-\tstruct dma_chan *chan,\n+\tstruct bcm2835_chan *c,\n \tenum dma_transfer_direction direction,\n \tstruct bcm2835_cb_entry *cb,\n \tstruct scatterlist *sgl,\n \tunsigned int sg_len)\n {\n-\tstruct bcm2835_chan *c = to_bcm2835_dma_chan(chan);\n \tsize_t len, max_len;\n \tunsigned int i;\n \tdma_addr_t addr;\n@@ -401,14 +582,35 @@ static void bcm2835_dma_fill_cb_chain_wi\n \n \tmax_len = bcm2835_dma_max_frame_length(c);\n \tfor_each_sg(sgl, sgent, sg_len, i) {\n-\t\tfor (addr = sg_dma_address(sgent), len = sg_dma_len(sgent);\n-\t\t     len > 0;\n-\t\t     addr += cb->cb->length, len -= cb->cb->length, cb++) {\n-\t\t\tif (direction == DMA_DEV_TO_MEM)\n-\t\t\t\tcb->cb->dst = addr;\n-\t\t\telse\n-\t\t\t\tcb->cb->src = addr;\n-\t\t\tcb->cb->length = min(len, max_len);\n+\t\tif (c->is_40bit_channel) {\n+\t\t\tstruct bcm2711_dma40_scb *scb;\n+\n+\t\t\tfor (addr = sg_dma_address(sgent),\n+\t\t\t\t     len = sg_dma_len(sgent);\n+\t\t\t\t     len > 0;\n+\t\t\t     addr += scb->len, len -= scb->len, cb++) {\n+\t\t\t\tscb = (struct bcm2711_dma40_scb *)cb->cb;\n+\t\t\t\tif (direction == DMA_DEV_TO_MEM) {\n+\t\t\t\t\tscb->dst = lower_32_bits(addr);\n+\t\t\t\t\tscb->dsti = upper_32_bits(addr) | BCM2711_DMA40_INC;\n+\t\t\t\t} else {\n+\t\t\t\t\tscb->src = lower_32_bits(addr);\n+\t\t\t\t\tscb->srci = upper_32_bits(addr) | BCM2711_DMA40_INC;\n+\t\t\t\t}\n+\t\t\t\tscb->len = min(len, max_len);\n+\t\t\t}\n+\t\t} else {\n+\t\t\tfor (addr = sg_dma_address(sgent),\n+\t\t\t\t     len = sg_dma_len(sgent);\n+\t\t\t     len > 0;\n+\t\t\t     addr += cb->cb->length, len -= cb->cb->length,\n+\t\t\t     cb++) {\n+\t\t\t\tif (direction == DMA_DEV_TO_MEM)\n+\t\t\t\t\tcb->cb->dst = addr;\n+\t\t\t\telse\n+\t\t\t\t\tcb->cb->src = addr;\n+\t\t\t\tcb->cb->length = min(len, max_len);\n+\t\t\t}\n \t\t}\n \t}\n }\n@@ -417,6 +619,10 @@ static void bcm2835_dma_abort(struct bcm\n {\n \tvoid __iomem *chan_base = c->chan_base;\n \tlong int timeout = 10000;\n+\tu32 wait_mask = BCM2835_DMA_WAITING_FOR_WRITES;\n+\n+\tif (c->is_40bit_channel)\n+\t\twait_mask = BCM2711_DMA40_WAITING_FOR_WRITES;\n \n \t/*\n \t * A zero control block address means the channel is idle.\n@@ -429,8 +635,7 @@ static void bcm2835_dma_abort(struct bcm\n \twritel(0, chan_base + BCM2835_DMA_CS);\n \n \t/* Wait for any current AXI transfer to complete */\n-\twhile ((readl(chan_base + BCM2835_DMA_CS) &\n-\t\tBCM2835_DMA_WAITING_FOR_WRITES) && --timeout)\n+\twhile ((readl(chan_base + BCM2835_DMA_CS) & wait_mask) && --timeout)\n \t\tcpu_relax();\n \n \t/* Peripheral might be stuck and fail to signal AXI write responses */\n@@ -455,9 +660,16 @@ static void bcm2835_dma_start_desc(struc\n \n \tc->desc = d = to_bcm2835_dma_desc(&vd->tx);\n \n-\twritel(d->cb_list[0].paddr, c->chan_base + BCM2835_DMA_ADDR);\n-\twritel(BCM2835_DMA_ACTIVE | BCM2835_DMA_CS_FLAGS(c->dreq),\n-\t       c->chan_base + BCM2835_DMA_CS);\n+\tif (c->is_40bit_channel) {\n+\t\twritel(to_bcm2711_cbaddr(d->cb_list[0].paddr),\n+\t\t       c->chan_base + BCM2711_DMA40_CB);\n+\t\twritel(BCM2711_DMA40_ACTIVE | BCM2711_DMA40_CS_FLAGS(c->dreq),\n+\t\t       c->chan_base + BCM2711_DMA40_CS);\n+\t} else {\n+\t\twritel(d->cb_list[0].paddr, c->chan_base + BCM2835_DMA_ADDR);\n+\t\twritel(BCM2835_DMA_ACTIVE | BCM2835_DMA_CS_FLAGS(c->dreq),\n+\t\t       c->chan_base + BCM2835_DMA_CS);\n+\t}\n }\n \n static irqreturn_t bcm2835_dma_callback(int irq, void *data)\n@@ -484,8 +696,7 @@ static irqreturn_t bcm2835_dma_callback(\n \t * if this IRQ handler is threaded.) If the channel is finished, it\n \t * will remain idle despite the ACTIVE flag being set.\n \t */\n-\twritel(BCM2835_DMA_INT | BCM2835_DMA_ACTIVE |\n-\t       BCM2835_DMA_CS_FLAGS(c->dreq),\n+\twritel(BCM2835_DMA_INT | BCM2835_DMA_ACTIVE,\n \t       c->chan_base + BCM2835_DMA_CS);\n \n \td = c->desc;\n@@ -588,9 +799,17 @@ static enum dma_status bcm2835_dma_tx_st\n \t\tstruct bcm2835_desc *d = c->desc;\n \t\tdma_addr_t pos;\n \n-\t\tif (d->dir == DMA_MEM_TO_DEV)\n+\t\tif (d->dir == DMA_MEM_TO_DEV && c->is_40bit_channel)\n+\t\t\tpos = readl(c->chan_base + BCM2711_DMA40_SRC) +\n+\t\t\t\t((readl(c->chan_base + BCM2711_DMA40_SRCI) &\n+\t\t\t\t  0xff) << 8);\n+\t\telse if (d->dir == DMA_MEM_TO_DEV && !c->is_40bit_channel)\n \t\t\tpos = readl(c->chan_base + BCM2835_DMA_SOURCE_AD);\n-\t\telse if (d->dir == DMA_DEV_TO_MEM)\n+\t\telse if (d->dir == DMA_DEV_TO_MEM && c->is_40bit_channel)\n+\t\t\tpos = readl(c->chan_base + BCM2711_DMA40_DEST) +\n+\t\t\t\t((readl(c->chan_base + BCM2711_DMA40_DESTI) &\n+\t\t\t\t  0xff) << 8);\n+\t\telse if (d->dir == DMA_DEV_TO_MEM && !c->is_40bit_channel)\n \t\t\tpos = readl(c->chan_base + BCM2835_DMA_DEST_AD);\n \t\telse\n \t\t\tpos = 0;\n@@ -636,7 +855,7 @@ static struct dma_async_tx_descriptor *b\n \tframes = bcm2835_dma_frames_for_length(len, max_len);\n \n \t/* allocate the CB chain - this also fills in the pointers */\n-\td = bcm2835_dma_create_cb_chain(chan, DMA_MEM_TO_MEM, false,\n+\td = bcm2835_dma_create_cb_chain(c, DMA_MEM_TO_MEM, false,\n \t\t\t\t\tinfo, extra, frames,\n \t\t\t\t\tsrc, dst, len, 0, GFP_KERNEL);\n \tif (!d)\n@@ -671,11 +890,21 @@ static struct dma_async_tx_descriptor *b\n \t\tif (c->cfg.src_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES)\n \t\t\treturn NULL;\n \t\tsrc = c->cfg.src_addr;\n+\t\t/*\n+\t\t * One would think it ought to be possible to get the physical\n+\t\t * to dma address mapping information from the dma-ranges DT\n+\t\t * property, but I've not found a way yet that doesn't involve\n+\t\t * open-coding the whole thing.\n+\t\t */\n+\t\tif (c->is_40bit_channel)\n+\t\t    src |= 0x400000000ull;\n \t\tinfo |= BCM2835_DMA_S_DREQ | BCM2835_DMA_D_INC;\n \t} else {\n \t\tif (c->cfg.dst_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES)\n \t\t\treturn NULL;\n \t\tdst = c->cfg.dst_addr;\n+\t\tif (c->is_40bit_channel)\n+\t\t    dst |= 0x400000000ull;\n \t\tinfo |= BCM2835_DMA_D_DREQ | BCM2835_DMA_S_INC;\n \t}\n \n@@ -683,7 +912,7 @@ static struct dma_async_tx_descriptor *b\n \tframes = bcm2835_dma_count_frames_for_sg(c, sgl, sg_len);\n \n \t/* allocate the CB chain */\n-\td = bcm2835_dma_create_cb_chain(chan, direction, false,\n+\td = bcm2835_dma_create_cb_chain(c, direction, false,\n \t\t\t\t\tinfo, extra,\n \t\t\t\t\tframes, src, dst, 0, 0,\n \t\t\t\t\tGFP_NOWAIT);\n@@ -691,7 +920,7 @@ static struct dma_async_tx_descriptor *b\n \t\treturn NULL;\n \n \t/* fill in frames with scatterlist pointers */\n-\tbcm2835_dma_fill_cb_chain_with_sg(chan, direction, d->cb_list,\n+\tbcm2835_dma_fill_cb_chain_with_sg(c, direction, d->cb_list,\n \t\t\t\t\t  sgl, sg_len);\n \n \treturn vchan_tx_prep(&c->vc, &d->vd, flags);\n@@ -745,12 +974,16 @@ static struct dma_async_tx_descriptor *b\n \t\tif (c->cfg.src_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES)\n \t\t\treturn NULL;\n \t\tsrc = c->cfg.src_addr;\n+\t\tif (c->is_40bit_channel)\n+\t\t    src |= 0x400000000ull;\n \t\tdst = buf_addr;\n \t\tinfo |= BCM2835_DMA_S_DREQ | BCM2835_DMA_D_INC;\n \t} else {\n \t\tif (c->cfg.dst_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES)\n \t\t\treturn NULL;\n \t\tdst = c->cfg.dst_addr;\n+\t\tif (c->is_40bit_channel)\n+\t\t    dst |= 0x400000000ull;\n \t\tsrc = buf_addr;\n \t\tinfo |= BCM2835_DMA_D_DREQ | BCM2835_DMA_S_INC;\n \n@@ -770,7 +1003,7 @@ static struct dma_async_tx_descriptor *b\n \t * note that we need to use GFP_NOWAIT, as the ALSA i2s dmaengine\n \t * implementation calls prep_dma_cyclic with interrupts disabled.\n \t */\n-\td = bcm2835_dma_create_cb_chain(chan, direction, true,\n+\td = bcm2835_dma_create_cb_chain(c, direction, true,\n \t\t\t\t\tinfo, extra,\n \t\t\t\t\tframes, src, dst, buf_len,\n \t\t\t\t\tperiod_len, GFP_NOWAIT);\n@@ -778,7 +1011,12 @@ static struct dma_async_tx_descriptor *b\n \t\treturn NULL;\n \n \t/* wrap around into a loop */\n-\td->cb_list[d->frames - 1].cb->next = d->cb_list[0].paddr;\n+\tif (c->is_40bit_channel)\n+\t\t((struct bcm2711_dma40_scb *)\n+\t\t d->cb_list[frames - 1].cb)->next_cb =\n+\t\t\tto_bcm2711_cbaddr(d->cb_list[0].paddr);\n+\telse\n+\t\td->cb_list[d->frames - 1].cb->next = d->cb_list[0].paddr;\n \n \treturn vchan_tx_prep(&c->vc, &d->vd, flags);\n }\n@@ -839,9 +1077,11 @@ static int bcm2835_dma_chan_init(struct\n \tc->irq_number = irq;\n \tc->irq_flags = irq_flags;\n \n-\t/* check in DEBUG register if this is a LITE channel */\n-\tif (readl(c->chan_base + BCM2835_DMA_DEBUG) &\n-\t\tBCM2835_DMA_DEBUG_LITE)\n+\t/* check for 40bit and lite channels */\n+\tif (d->cfg_data->chan_40bit_mask & BIT(chan_id))\n+\t\tc->is_40bit_channel = true;\n+\telse if (readl(c->chan_base + BCM2835_DMA_DEBUG) &\n+\t\t BCM2835_DMA_DEBUG_LITE)\n \t\tc->is_lite_channel = true;\n \n \treturn 0;\n@@ -861,8 +1101,58 @@ static void bcm2835_dma_free(struct bcm2\n \t\t\t     DMA_TO_DEVICE, DMA_ATTR_SKIP_CPU_SYNC);\n }\n \n+int bcm2711_dma40_memcpy_init(void)\n+{\n+\tif (!memcpy_parent)\n+\t\treturn -EPROBE_DEFER;\n+\n+\tif (!memcpy_chan)\n+\t\treturn -EINVAL;\n+\n+\tif (!memcpy_scb)\n+\t\treturn -ENOMEM;\n+\n+\treturn 0;\n+}\n+EXPORT_SYMBOL(bcm2711_dma40_memcpy_init);\n+\n+void bcm2711_dma40_memcpy(dma_addr_t dst, dma_addr_t src, size_t size)\n+{\n+\tstruct bcm2711_dma40_scb *scb = memcpy_scb;\n+\tunsigned long flags;\n+\n+\tif (!scb) {\n+\t\tpr_err(\"bcm2711_dma40_memcpy not initialised!\\n\");\n+\t\treturn;\n+\t}\n+\n+\tspin_lock_irqsave(&memcpy_lock, flags);\n+\n+\tscb->ti = 0;\n+\tscb->src = lower_32_bits(src);\n+\tscb->srci = upper_32_bits(src) | BCM2711_DMA40_MEMCPY_XFER_INFO;\n+\tscb->dst = lower_32_bits(dst);\n+\tscb->dsti = upper_32_bits(dst) | BCM2711_DMA40_MEMCPY_XFER_INFO;\n+\tscb->len = size;\n+\tscb->next_cb = 0;\n+\n+\twritel((u32)(memcpy_scb_dma >> 5), memcpy_chan + BCM2711_DMA40_CB);\n+\twritel(BCM2711_DMA40_MEMCPY_FLAGS + BCM2711_DMA40_ACTIVE,\n+\t       memcpy_chan + BCM2711_DMA40_CS);\n+\n+\t/* Poll for completion */\n+\twhile (!(readl(memcpy_chan + BCM2711_DMA40_CS) & BCM2711_DMA40_END))\n+\t\tcpu_relax();\n+\n+\twritel(BCM2711_DMA40_END, memcpy_chan + BCM2711_DMA40_CS);\n+\n+\tspin_unlock_irqrestore(&memcpy_lock, flags);\n+}\n+EXPORT_SYMBOL(bcm2711_dma40_memcpy);\n+\n static const struct of_device_id bcm2835_dma_of_match[] = {\n-\t{ .compatible = \"brcm,bcm2835-dma\", },\n+\t{ .compatible = \"brcm,bcm2835-dma\", .data = &bcm2835_dma_cfg },\n+\t{ .compatible = \"brcm,bcm2711-dma\", .data = &bcm2711_dma_cfg },\n \t{},\n };\n MODULE_DEVICE_TABLE(of, bcm2835_dma_of_match);\n@@ -894,6 +1184,8 @@ static int bcm2835_dma_probe(struct plat\n \tint irq_flags;\n \tuint32_t chans_available;\n \tchar chan_name[BCM2835_DMA_CHAN_NAME_SIZE];\n+\tconst struct of_device_id *of_id;\n+\tint chan_count, chan_start, chan_end;\n \n \tif (!pdev->dev.dma_mask)\n \t\tpdev->dev.dma_mask = &pdev->dev.coherent_dma_mask;\n@@ -914,9 +1206,13 @@ static int bcm2835_dma_probe(struct plat\n \tbase = devm_ioremap_resource(&pdev->dev, res);\n \tif (IS_ERR(base))\n \t\treturn PTR_ERR(base);\n-\trc = bcm_dmaman_probe(pdev, base, BCM2835_DMA_BULK_MASK);\n-\tif (rc)\n-\t\tdev_err(&pdev->dev, \"Failed to initialize the legacy API\\n\");\n+\n+\t/* The set of channels can be split across multiple instances. */\n+\tchan_start = ((u32)(uintptr_t)base / BCM2835_DMA_CHAN_SIZE) & 0xf;\n+\tbase -= BCM2835_DMA_CHAN(chan_start);\n+\tchan_count = resource_size(res) / BCM2835_DMA_CHAN_SIZE;\n+\tchan_end = min(chan_start + chan_count,\n+\t\t\t BCM2835_DMA_MAX_DMA_CHAN_SUPPORTED + 1);\n \n \tod->base = base;\n \n@@ -953,6 +1249,14 @@ static int bcm2835_dma_probe(struct plat\n \t\treturn -ENOMEM;\n \t}\n \n+\tof_id = of_match_node(bcm2835_dma_of_match, pdev->dev.of_node);\n+\tif (!of_id) {\n+\t\tdev_err(&pdev->dev, \"Failed to match compatible string\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tod->cfg_data = of_id->data;\n+\n \t/* Request DMA channel mask from device tree */\n \tif (of_property_read_u32(pdev->dev.of_node,\n \t\t\t\"brcm,dma-channel-mask\",\n@@ -962,11 +1266,34 @@ static int bcm2835_dma_probe(struct plat\n \t\tgoto err_no_dma;\n \t}\n \n-\t/* Channel 0 is used by the legacy API */\n-\tchans_available &= ~BCM2835_DMA_BULK_MASK;\n+\t/* One channel is reserved for the legacy API */\n+\tif (chans_available & BCM2835_DMA_BULK_MASK) {\n+\t\trc = bcm_dmaman_probe(pdev, base,\n+\t\t\t\t      chans_available & BCM2835_DMA_BULK_MASK);\n+\t\tif (rc)\n+\t\t\tdev_err(&pdev->dev,\n+\t\t\t\t\"Failed to initialize the legacy API\\n\");\n+\n+\t\tchans_available &= ~BCM2835_DMA_BULK_MASK;\n+\t}\n+\n+\t/* And possibly one for the 40-bit DMA memcpy API */\n+\tif (chans_available & od->cfg_data->chan_40bit_mask &\n+\t    BIT(BCM2711_DMA_MEMCPY_CHAN)) {\n+\t\tmemcpy_parent = od;\n+\t\tmemcpy_chan = BCM2835_DMA_CHANIO(base, BCM2711_DMA_MEMCPY_CHAN);\n+\t\tmemcpy_scb = dma_alloc_coherent(memcpy_parent->ddev.dev,\n+\t\t\t\t\t\tsizeof(*memcpy_scb),\n+\t\t\t\t\t\t&memcpy_scb_dma, GFP_KERNEL);\n+\t\tif (!memcpy_scb)\n+\t\t\tdev_warn(&pdev->dev,\n+\t\t\t\t \"Failed to allocated memcpy scb\\n\");\n+\n+\t\tchans_available &= ~BIT(BCM2711_DMA_MEMCPY_CHAN);\n+\t}\n \n \t/* get irqs for each channel that we support */\n-\tfor (i = 0; i <= BCM2835_DMA_MAX_DMA_CHAN_SUPPORTED; i++) {\n+\tfor (i = chan_start; i < chan_end; i++) {\n \t\t/* skip masked out channels */\n \t\tif (!(chans_available & (1 << i))) {\n \t\t\tirq[i] = -1;\n@@ -989,13 +1316,17 @@ static int bcm2835_dma_probe(struct plat\n \t\tirq[i] = platform_get_irq(pdev, i < 11 ? i : 11);\n \t}\n \n+\tchan_count = 0;\n+\n \t/* get irqs for each channel */\n-\tfor (i = 0; i <= BCM2835_DMA_MAX_DMA_CHAN_SUPPORTED; i++) {\n+\tfor (i = chan_start; i < chan_end; i++) {\n \t\t/* skip channels without irq */\n \t\tif (irq[i] < 0)\n \t\t\tcontinue;\n \n \t\t/* check if there are other channels that also use this irq */\n+\t\t/* FIXME: This will fail if interrupts are shared across\n+\t\t   instances */\n \t\tirq_flags = 0;\n \t\tfor (j = 0; j <= BCM2835_DMA_MAX_DMA_CHAN_SUPPORTED; j++)\n \t\t\tif ((i != j) && (irq[j] == irq[i])) {\n@@ -1007,9 +1338,10 @@ static int bcm2835_dma_probe(struct plat\n \t\trc = bcm2835_dma_chan_init(od, i, irq[i], irq_flags);\n \t\tif (rc)\n \t\t\tgoto err_no_dma;\n+\t\tchan_count++;\n \t}\n \n-\tdev_dbg(&pdev->dev, \"Initialized %i DMA channels\\n\", i);\n+\tdev_dbg(&pdev->dev, \"Initialized %i DMA channels\\n\", chan_count);\n \n \t/* Device-tree DMA controller registration */\n \trc = of_dma_controller_register(pdev->dev.of_node,\n@@ -1041,6 +1373,13 @@ static int bcm2835_dma_remove(struct pla\n \n \tbcm_dmaman_remove(pdev);\n \tdma_async_device_unregister(&od->ddev);\n+\tif (memcpy_parent == od) {\n+\t\tdma_free_coherent(&pdev->dev, sizeof(*memcpy_scb), memcpy_scb,\n+\t\t\t\t  memcpy_scb_dma);\n+\t\tmemcpy_parent = NULL;\n+\t\tmemcpy_scb = NULL;\n+\t\tmemcpy_chan = NULL;\n+\t}\n \tbcm2835_dma_free(od);\n \n \treturn 0;\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0223-overlays-Make-the-i2c-gpio-overlay-safe-again.patch",
    "content": "From 4721459bb386bf32b2295b947f38b91cdd97929b Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.com>\nDate: Fri, 1 May 2020 17:56:13 +0100\nSubject: [PATCH] overlays: Make the i2c-gpio overlay safe again\n\nLike many overlays, the i2c-gpio overlay goes to efforts to avoid\ngenerating warnings about #address-cells and #size-cells not\nbeing defined, which it does by defining them. Unfortunately this\nis fatal if they don't match what the system requires, and the\nrecent switch to #size-cells = 2 on 2711 made i2c-gpio very\ndangerous.\n\nIn the absence of the knowledge of a clean way to fix this, just delete\nthe declarations and suffer the warnings.\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.com>\n---\n arch/arm/boot/dts/overlays/i2c-gpio-overlay.dts | 3 ---\n 1 file changed, 3 deletions(-)\n\n--- a/arch/arm/boot/dts/overlays/i2c-gpio-overlay.dts\n+++ b/arch/arm/boot/dts/overlays/i2c-gpio-overlay.dts\n@@ -11,9 +11,6 @@\n \t\ttarget-path = \"/\";\n \n \t\t__overlay__ {\n-\t\t\t#address-cells = <1>;\n-\t\t\t#size-cells = <0>;\n-\n \t\t\ti2c_gpio: i2c@0 {\n \t\t\t\treg = <0xffffffff>;\n \t\t\t\tcompatible = \"i2c-gpio\";\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0224-media-i2c-imx219-Declare-that-the-driver-can-create-.patch",
    "content": "From 8a251d243fa3931f3b03677f4f58ceb728f42e99 Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Mon, 20 Apr 2020 11:01:21 +0100\nSubject: [PATCH] media: i2c: imx219: Declare that the driver can\n create events\n\nThe flag V4L2_SUBDEV_FL_HAS_EVENTS is required if the subdev can\ngenerate events. It can create events from the ctrl handler, therefore\nthis is required.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n drivers/media/i2c/imx219.c | 3 ++-\n 1 file changed, 2 insertions(+), 1 deletion(-)\n\n--- a/drivers/media/i2c/imx219.c\n+++ b/drivers/media/i2c/imx219.c\n@@ -1591,7 +1591,8 @@ static int imx219_probe(struct i2c_clien\n \n \t/* Initialize subdev */\n \timx219->sd.internal_ops = &imx219_internal_ops;\n-\timx219->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;\n+\timx219->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |\n+\t\t\t    V4L2_SUBDEV_FL_HAS_EVENTS;\n \timx219->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;\n \n \t/* Initialize source pads */\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0225-media-ov5647-Fix-return-codes-from-ov5647_write-ov56.patch",
    "content": "From 0a17f217911f989cd58df868f902b488088a1398 Mon Sep 17 00:00:00 2001\nFrom: David Plowman <david.plowman@raspberrypi.org>\nDate: Wed, 15 Jan 2020 13:40:38 +0000\nSubject: [PATCH] media: ov5647: Fix return codes from\n ov5647_write/ov5647_read functions.\n\nPreviously they were returning positive non-zero codes for success,\nwhich were getting passed up the call stack. Since release 4.19,\ndo_dentry_open (fs/open.c) has been catching these and flagging an\nerror. (So this driver has been broken since that date.)\n\nFixes: 3c2472a [media] media: i2c: Add support for OV5647 sensor\nSigned-off-by: David Plowman <david.plowman@raspberrypi.org>\nSigned-off-by: Naushir Patuck <naush@raspberrypi.com>\n---\n drivers/media/i2c/ov5647.c | 30 +++++++++++++++++++++++++++---\n 1 file changed, 27 insertions(+), 3 deletions(-)\n\n--- a/drivers/media/i2c/ov5647.c\n+++ b/drivers/media/i2c/ov5647.c\n@@ -214,9 +214,18 @@ static int ov5647_write(struct v4l2_subd\n \tstruct i2c_client *client = v4l2_get_subdevdata(sd);\n \n \tret = i2c_master_send(client, data, 3);\n-\tif (ret < 0)\n+\t/*\n+\t * Writing the wrong number of bytes also needs to be flagged as an\n+\t * error. Success needs to produce a 0 return code.\n+\t */\n+\tif (ret == 3) {\n+\t\tret = 0;\n+\t} else {\n \t\tdev_dbg(&client->dev, \"%s: i2c write error, reg: %x\\n\",\n \t\t\t\t__func__, reg);\n+\t\tif (ret >= 0)\n+\t\t\tret = -EINVAL;\n+\t}\n \n \treturn ret;\n }\n@@ -228,16 +237,31 @@ static int ov5647_read(struct v4l2_subde\n \tstruct i2c_client *client = v4l2_get_subdevdata(sd);\n \n \tret = i2c_master_send(client, data_w, 2);\n-\tif (ret < 0) {\n+\t/*\n+\t * A negative return code, or sending the wrong number of bytes, both\n+\t * count as an error.\n+\t */\n+\tif (ret != 2) {\n \t\tdev_dbg(&client->dev, \"%s: i2c write error, reg: %x\\n\",\n \t\t\t__func__, reg);\n+\t\tif (ret >= 0)\n+\t\t\tret = -EINVAL;\n \t\treturn ret;\n \t}\n \n \tret = i2c_master_recv(client, val, 1);\n-\tif (ret < 0)\n+\t/*\n+\t * The only return value indicating success is 1. Anything else, even\n+\t * a non-negative value, indicates something went wrong.\n+\t */\n+\tif (ret == 1) {\n+\t\tret = 0;\n+\t} else {\n \t\tdev_dbg(&client->dev, \"%s: i2c read error, reg: %x\\n\",\n \t\t\t\t__func__, reg);\n+\t\tif (ret >= 0)\n+\t\t\tret = -EINVAL;\n+\t}\n \n \treturn ret;\n }\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0226-media-ov5647-Add-basic-support-for-multiple-sensor-m.patch",
    "content": "From c3535af52b9f641565db400aab050298b786fcf3 Mon Sep 17 00:00:00 2001\nFrom: David Plowman <david.plowman@raspberrypi.com>\nDate: Wed, 29 Jan 2020 15:30:53 +0000\nSubject: [PATCH] media: ov5647: Add basic support for multiple sensor\n modes.\n\nSpecifically:\n\nAdded a structure ov5647_mode and a list of supported_modes (though no\nactual new modes as yet). The state object points to the \"current mode\".\n\nov5647_enum_mbus_code, ov5647_enum_frame_size, ov5647_set_fmt and\nov5647_get_fmt all needed upgrading to cope with multiple modes.\n\n__sensor_init (which writes all the registers) is now called by\nov5647_stream_on (once the mode is known) rather than by\nov5647_sensor_power.\n\nSigned-off-by: David Plowman <david.plowman@raspberrypi.com>\nSigned-off-by: Naushir Patuck <naush@raspberrypi.com>\n---\n drivers/media/i2c/ov5647.c | 268 ++++++++++++++++++++++++++++---------\n 1 file changed, 202 insertions(+), 66 deletions(-)\n\n--- a/drivers/media/i2c/ov5647.c\n+++ b/drivers/media/i2c/ov5647.c\n@@ -86,13 +86,17 @@ struct regval_list {\n \tu8 data;\n };\n \n+struct ov5647_mode {\n+\tstruct v4l2_mbus_framefmt\tformat;\n+\tstruct regval_list\t\t*reg_list;\n+\tunsigned int\t\t\tnum_regs;\n+};\n+\n struct ov5647 {\n \tstruct v4l2_subdev\t\tsd;\n \tstruct media_pad\t\tpad;\n \tstruct mutex\t\t\tlock;\n-\tstruct v4l2_mbus_framefmt\tformat;\n-\tunsigned int\t\t\twidth;\n-\tunsigned int\t\t\theight;\n+\tconst struct ov5647_mode\t*mode;\n \tint\t\t\t\tpower_count;\n \tstruct clk\t\t\t*xclk;\n \tstruct gpio_desc\t\t*pwdn;\n@@ -207,6 +211,32 @@ static struct regval_list ov5647_640x480\n \t{0x0100, 0x01},\n };\n \n+static struct ov5647_mode supported_modes_8bit[] = {\n+\t/*\n+\t * Original 8-bit VGA mode\n+\t * Uncentred crop (top left quarter) from 2x2 binned 1296x972 image.\n+\t */\n+\t{\n+\t\t{\n+\t\t\t.code = MEDIA_BUS_FMT_SBGGR8_1X8,\n+\t\t\t.colorspace = V4L2_COLORSPACE_SRGB,\n+\t\t\t.field = V4L2_FIELD_NONE,\n+\t\t\t.width = 640,\n+\t\t\t.height = 480\n+\t\t},\n+\t\tov5647_640x480,\n+\t\tARRAY_SIZE(ov5647_640x480)\n+\t},\n+\t/* more modes below here... */\n+};\n+\n+static struct ov5647_mode supported_modes_10bit[] = {\n+\t/* no 10-bit modes yet */\n+};\n+\n+/* Use original 8-bit VGA mode as default. */\n+#define OV5647_DEFAULT_MODE (&supported_modes_8bit[0])\n+\n static int ov5647_write(struct v4l2_subdev *sd, u16 reg, u8 val)\n {\n \tint ret;\n@@ -293,12 +323,55 @@ static int ov5647_set_virtual_channel(st\n \treturn ov5647_write(sd, OV5647_REG_MIPI_CTRL14, channel_id | (channel << 6));\n }\n \n+static int __sensor_init(struct v4l2_subdev *sd)\n+{\n+\tint ret;\n+\tu8 resetval, rdval;\n+\tstruct i2c_client *client = v4l2_get_subdevdata(sd);\n+\tstruct ov5647 *state = to_state(sd);\n+\n+\tret = ov5647_read(sd, OV5647_SW_STANDBY, &rdval);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\tret = ov5647_write_array(sd, state->mode->reg_list,\n+\t\t\t\t state->mode->num_regs);\n+\tif (ret < 0) {\n+\t\tdev_err(&client->dev, \"write sensor default regs error\\n\");\n+\t\treturn ret;\n+\t}\n+\n+\tret = ov5647_set_virtual_channel(sd, 0);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\tret = ov5647_read(sd, OV5647_SW_STANDBY, &resetval);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\tif (!(resetval & 0x01)) {\n+\t\tdev_err(&client->dev, \"Device was in SW standby\");\n+\t\tret = ov5647_write(sd, OV5647_SW_STANDBY, 0x01);\n+\t\tif (ret < 0)\n+\t\t\treturn ret;\n+\t}\n+\n+\treturn 0;\n+}\n+\n static int ov5647_stream_on(struct v4l2_subdev *sd)\n {\n+\tstruct i2c_client *client = v4l2_get_subdevdata(sd);\n \tstruct ov5647 *ov5647 = to_state(sd);\n \tu8 val = MIPI_CTRL00_BUS_IDLE;\n \tint ret;\n \n+\tret = __sensor_init(sd);\n+\tif (ret < 0) {\n+\t\tdev_err(&client->dev, \"sensor_init failed\\n\");\n+\t\treturn ret;\n+\t}\n+\n \tif (ov5647->flags & V4L2_MBUS_CSI2_NONCONTINUOUS_CLOCK)\n \t\tval |= MIPI_CTRL00_CLOCK_LANE_GATE |\n \t\t       MIPI_CTRL00_LINE_SYNC_ENABLE;\n@@ -347,44 +420,6 @@ static int set_sw_standby(struct v4l2_su\n \treturn ov5647_write(sd, OV5647_SW_STANDBY, rdval);\n }\n \n-static int __sensor_init(struct v4l2_subdev *sd)\n-{\n-\tint ret;\n-\tu8 resetval, rdval;\n-\tstruct i2c_client *client = v4l2_get_subdevdata(sd);\n-\n-\tret = ov5647_read(sd, OV5647_SW_STANDBY, &rdval);\n-\tif (ret < 0)\n-\t\treturn ret;\n-\n-\tret = ov5647_write_array(sd, ov5647_640x480,\n-\t\t\t\t\tARRAY_SIZE(ov5647_640x480));\n-\tif (ret < 0) {\n-\t\tdev_err(&client->dev, \"write sensor default regs error\\n\");\n-\t\treturn ret;\n-\t}\n-\n-\tret = ov5647_set_virtual_channel(sd, 0);\n-\tif (ret < 0)\n-\t\treturn ret;\n-\n-\tret = ov5647_read(sd, OV5647_SW_STANDBY, &resetval);\n-\tif (ret < 0)\n-\t\treturn ret;\n-\n-\tif (!(resetval & 0x01)) {\n-\t\tdev_err(&client->dev, \"Device was in SW standby\");\n-\t\tret = ov5647_write(sd, OV5647_SW_STANDBY, 0x01);\n-\t\tif (ret < 0)\n-\t\t\treturn ret;\n-\t}\n-\n-\t/*\n-\t * stream off to make the clock lane into LP-11 state.\n-\t */\n-\treturn ov5647_stream_off(sd);\n-}\n-\n static int ov5647_sensor_power(struct v4l2_subdev *sd, int on)\n {\n \tint ret = 0;\n@@ -408,7 +443,7 @@ static int ov5647_sensor_power(struct v4\n \t\t}\n \n \t\tret = ov5647_write_array(sd, sensor_oe_enable_regs,\n-\t\t\t\tARRAY_SIZE(sensor_oe_enable_regs));\n+\t\t\t\t\t ARRAY_SIZE(sensor_oe_enable_regs));\n \t\tif (ret < 0) {\n \t\t\tclk_disable_unprepare(ov5647->xclk);\n \t\t\tdev_err(&client->dev,\n@@ -416,7 +451,10 @@ static int ov5647_sensor_power(struct v4\n \t\t\tgoto out;\n \t\t}\n \n-\t\tret = __sensor_init(sd);\n+\t\t/*\n+\t\t * Ensure streaming off to make clock lane go into LP-11 state.\n+\t\t */\n+\t\tret = ov5647_stream_off(sd);\n \t\tif (ret < 0) {\n \t\t\tclk_disable_unprepare(ov5647->xclk);\n \t\t\tdev_err(&client->dev,\n@@ -427,7 +465,7 @@ static int ov5647_sensor_power(struct v4\n \t\tdev_dbg(&client->dev, \"OV5647 power off\\n\");\n \n \t\tret = ov5647_write_array(sd, sensor_oe_disable_regs,\n-\t\t\t\tARRAY_SIZE(sensor_oe_disable_regs));\n+\t\t\t\t\t ARRAY_SIZE(sensor_oe_disable_regs));\n \n \t\tif (ret < 0)\n \t\t\tdev_dbg(&client->dev, \"disable oe failed\\n\");\n@@ -489,10 +527,19 @@ static const struct v4l2_subdev_core_ops\n \n static int ov5647_s_stream(struct v4l2_subdev *sd, int enable)\n {\n+\tstruct ov5647 *state = to_state(sd);\n+\tint ret = 0;\n+\n+\tmutex_lock(&state->lock);\n+\n \tif (enable)\n-\t\treturn ov5647_stream_on(sd);\n+\t\tret = ov5647_stream_on(sd);\n \telse\n-\t\treturn ov5647_stream_off(sd);\n+\t\tret = ov5647_stream_off(sd);\n+\n+\tmutex_unlock(&state->lock);\n+\n+\treturn ret;\n }\n \n static const struct v4l2_subdev_video_ops ov5647_subdev_video_ops = {\n@@ -503,38 +550,127 @@ static int ov5647_enum_mbus_code(struct\n \t\t\t\tstruct v4l2_subdev_pad_config *cfg,\n \t\t\t\tstruct v4l2_subdev_mbus_code_enum *code)\n {\n-\tif (code->index > 0)\n+\tif (code->index == 0 && ARRAY_SIZE(supported_modes_8bit))\n+\t\tcode->code = MEDIA_BUS_FMT_SBGGR8_1X8;\n+\telse if (code->index == 0 && ARRAY_SIZE(supported_modes_8bit) == 0 &&\n+\t\t ARRAY_SIZE(supported_modes_10bit))\n+\t\tcode->code = MEDIA_BUS_FMT_SBGGR10_1X10;\n+\telse if (code->index == 1 && ARRAY_SIZE(supported_modes_8bit) &&\n+\t\t ARRAY_SIZE(supported_modes_10bit))\n+\t\tcode->code = MEDIA_BUS_FMT_SBGGR10_1X10;\n+\telse\n \t\treturn -EINVAL;\n \n-\tcode->code = MEDIA_BUS_FMT_SBGGR8_1X8;\n+\treturn 0;\n+}\n+\n+static int ov5647_enum_frame_size(struct v4l2_subdev *sd,\n+\t\t\t\t  struct v4l2_subdev_pad_config *cfg,\n+\t\t\t\t  struct v4l2_subdev_frame_size_enum *fse)\n+{\n+\tstruct ov5647_mode *mode = NULL;\n+\n+\tif (fse->code == MEDIA_BUS_FMT_SBGGR8_1X8) {\n+\t\tif (fse->index >= ARRAY_SIZE(supported_modes_8bit))\n+\t\t\treturn -EINVAL;\n+\t\tmode = &supported_modes_8bit[fse->index];\n+\t} else if (fse->code == MEDIA_BUS_FMT_SBGGR10_1X10) {\n+\t\tif (fse->index >= ARRAY_SIZE(supported_modes_10bit))\n+\t\t\treturn -EINVAL;\n+\t\tmode = &supported_modes_10bit[fse->index];\n+\t} else {\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tfse->min_width = mode->format.width;\n+\tfse->max_width = fse->min_width;\n+\tfse->min_height = mode->format.height;\n+\tfse->max_height = fse->min_height;\n+\n+\treturn 0;\n+}\n+\n+static int ov5647_set_fmt(struct v4l2_subdev *sd,\n+\t\t\t  struct v4l2_subdev_pad_config *cfg,\n+\t\t\t  struct v4l2_subdev_format *format)\n+{\n+\tstruct v4l2_mbus_framefmt *fmt = &format->format;\n+\tstruct ov5647 *state = to_state(sd);\n+\tstruct v4l2_mbus_framefmt *framefmt;\n+\tconst struct ov5647_mode *mode_8bit, *mode_10bit, *mode = NULL;\n+\n+\tif (format->pad != 0)\n+\t\treturn -EINVAL;\n+\n+\tmutex_lock(&state->lock);\n+\n+\t/*\n+\t * Try to respect any given pixel format, otherwise try for a 10-bit\n+\t * mode.\n+\t */\n+\tmode_8bit = v4l2_find_nearest_size(supported_modes_8bit,\n+\t\t\t\t\t   ARRAY_SIZE(supported_modes_8bit),\n+\t\t\t\t\t   format.width, format.height,\n+\t\t\t\t\t   format->format.width,\n+\t\t\t\t\t   format->format.height);\n+\tmode_10bit = v4l2_find_nearest_size(supported_modes_10bit,\n+\t\t\t\t\t    ARRAY_SIZE(supported_modes_10bit),\n+\t\t\t\t\t    format.width, format.height,\n+\t\t\t\t\t    format->format.width,\n+\t\t\t\t\t    format->format.height);\n+\tif (format->format.code == MEDIA_BUS_FMT_SBGGR8_1X8 && mode_8bit)\n+\t\tmode = mode_8bit;\n+\telse if (format->format.code == MEDIA_BUS_FMT_SBGGR10_1X10 &&\n+\t\t mode_10bit)\n+\t\tmode = mode_10bit;\n+\telse if (mode_10bit)\n+\t\tmode = mode_10bit;\n+\telse\n+\t\tmode = mode_8bit;\n+\n+\tif (!mode)\n+\t\treturn -EINVAL;\n+\n+\t*fmt = mode->format;\n+\tif (format->which == V4L2_SUBDEV_FORMAT_TRY) {\n+\t\tframefmt = v4l2_subdev_get_try_format(sd, cfg, format->pad);\n+\t\t*framefmt = format->format;\n+\t} else {\n+\t\tstate->mode = mode;\n+\t}\n+\n+\tmutex_unlock(&state->lock);\n \n \treturn 0;\n }\n \n-static int ov5647_set_get_fmt(struct v4l2_subdev *sd,\n-\t\t\t      struct v4l2_subdev_pad_config *cfg,\n-\t\t\t      struct v4l2_subdev_format *format)\n+static int ov5647_get_fmt(struct v4l2_subdev *sd,\n+\t\t\t  struct v4l2_subdev_pad_config *cfg,\n+\t\t\t  struct v4l2_subdev_format *format)\n {\n \tstruct v4l2_mbus_framefmt *fmt = &format->format;\n+\tstruct ov5647 *state = to_state(sd);\n \n \tif (format->pad != 0)\n \t\treturn -EINVAL;\n \n-\t/* Only one format is supported, so return that */\n-\tmemset(fmt, 0, sizeof(*fmt));\n-\tfmt->code = MEDIA_BUS_FMT_SBGGR8_1X8;\n-\tfmt->colorspace = V4L2_COLORSPACE_SRGB;\n-\tfmt->field = V4L2_FIELD_NONE;\n-\tfmt->width = 640;\n-\tfmt->height = 480;\n+\tmutex_lock(&state->lock);\n+\n+\tif (format->which == V4L2_SUBDEV_FORMAT_TRY)\n+\t\t*fmt = *v4l2_subdev_get_try_format(sd, cfg, format->pad);\n+\telse\n+\t\t*fmt = state->mode->format;\n+\n+\tmutex_unlock(&state->lock);\n \n \treturn 0;\n }\n \n static const struct v4l2_subdev_pad_ops ov5647_subdev_pad_ops = {\n \t.enum_mbus_code = ov5647_enum_mbus_code,\n-\t.set_fmt =\t  ov5647_set_get_fmt,\n-\t.get_fmt =\t  ov5647_set_get_fmt,\n+\t.set_fmt =\t  ov5647_set_fmt,\n+\t.get_fmt =\t  ov5647_get_fmt,\n+\t.enum_frame_size = ov5647_enum_frame_size,\n };\n \n static const struct v4l2_subdev_ops ov5647_subdev_ops = {\n@@ -580,18 +716,15 @@ static int ov5647_open(struct v4l2_subde\n \t\t\t\tv4l2_subdev_get_try_format(sd, fh->pad, 0);\n \tstruct v4l2_rect *crop =\n \t\t\t\tv4l2_subdev_get_try_crop(sd, fh->pad, 0);\n+\tstruct ov5647 *state = to_state(sd);\n \n \tcrop->left = OV5647_COLUMN_START_DEF;\n \tcrop->top = OV5647_ROW_START_DEF;\n \tcrop->width = OV5647_WINDOW_WIDTH_DEF;\n \tcrop->height = OV5647_WINDOW_HEIGHT_DEF;\n \n-\tformat->code = MEDIA_BUS_FMT_SBGGR8_1X8;\n-\n-\tformat->width = OV5647_WINDOW_WIDTH_DEF;\n-\tformat->height = OV5647_WINDOW_HEIGHT_DEF;\n-\tformat->field = V4L2_FIELD_NONE;\n-\tformat->colorspace = V4L2_COLORSPACE_SRGB;\n+\t/* Set the default format to the same as the sensor. */\n+\t*format = state->mode->format;\n \n \treturn 0;\n }\n@@ -660,6 +793,9 @@ static int ov5647_probe(struct i2c_clien\n \n \tmutex_init(&sensor->lock);\n \n+\t/* Set the default mode before we init the subdev */\n+\tsensor->mode = OV5647_DEFAULT_MODE;\n+\n \tsd = &sensor->sd;\n \tv4l2_i2c_subdev_init(sd, client, &ov5647_subdev_ops);\n \tsensor->sd.internal_ops = &ov5647_subdev_internal_ops;\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0227-media-ov5647-Add-V4L2-controls-for-analogue-gain-exp.patch",
    "content": "From 0c212ccaa2e790de8eb43b2766767f2713f93915 Mon Sep 17 00:00:00 2001\nFrom: David Plowman <david.plowman@raspberrypi.com>\nDate: Wed, 29 Jan 2020 15:31:23 +0000\nSubject: [PATCH] media: ov5647: Add V4L2 controls for analogue gain,\n exposure and AWB\n\nAdded basic v4l2_ctrl_handler infrastructure (there was none\npreviously).\n\nAdded controls to let AWB/AEC/AGC run in the sensor's auto mode or\nmanually. Also controls to set exposure (in lines) and analogue gain\n(as a register code) from user code.\n\nAlso delete registers (just the one) from the VGA mode register set\nthat are now controlled by the new V4L2 controls.\n\nSigned-off-by: David Plowman <david.plowman@raspberrypi.com>\nSigned-off-by: Naushir Patuck <naush@raspberrypi.com>\n---\n drivers/media/i2c/ov5647.c | 175 ++++++++++++++++++++++++++++++++++++-\n 1 file changed, 174 insertions(+), 1 deletion(-)\n\n--- a/drivers/media/i2c/ov5647.c\n+++ b/drivers/media/i2c/ov5647.c\n@@ -29,11 +29,13 @@\n #include <linux/of_graph.h>\n #include <linux/slab.h>\n #include <linux/videodev2.h>\n+#include <media/v4l2-ctrls.h>\n #include <media/v4l2-device.h>\n #include <media/v4l2-fwnode.h>\n #include <media/v4l2-image-sizes.h>\n #include <media/v4l2-mediabus.h>\n \n+\n #define SENSOR_NAME \"ov5647\"\n \n /*\n@@ -53,9 +55,16 @@\n #define OV5647_REG_CHIPID_H\t\t0x300A\n #define OV5647_REG_CHIPID_L\t\t0x300B\n #define OV5640_REG_PAD_OUT\t\t0x300D\n+#define OV5647_REG_EXP_HI\t\t0x3500\n+#define OV5647_REG_EXP_MID\t\t0x3501\n+#define OV5647_REG_EXP_LO\t\t0x3502\n+#define OV5647_REG_AEC_AGC\t\t0x3503\n+#define OV5647_REG_GAIN_HI\t\t0x350A\n+#define OV5647_REG_GAIN_LO\t\t0x350B\n #define OV5647_REG_FRAME_OFF_NUMBER\t0x4202\n #define OV5647_REG_MIPI_CTRL00\t\t0x4800\n #define OV5647_REG_MIPI_CTRL14\t\t0x4814\n+#define OV5647_REG_AWB\t\t\t0x5001\n \n #define REG_TERM 0xfffe\n #define VAL_TERM 0xfe\n@@ -101,6 +110,7 @@ struct ov5647 {\n \tstruct clk\t\t\t*xclk;\n \tstruct gpio_desc\t\t*pwdn;\n \tunsigned int\t\t\tflags;\n+\tstruct v4l2_ctrl_handler\tctrls;\n };\n \n static inline struct ov5647 *to_state(struct v4l2_subdev *sd)\n@@ -135,7 +145,6 @@ static struct regval_list ov5647_640x480\n \t{0x3612, 0x59},\n \t{0x3618, 0x00},\n \t{0x5000, 0x06},\n-\t{0x5001, 0x01},\n \t{0x5002, 0x41},\n \t{0x5003, 0x08},\n \t{0x5a00, 0x08},\n@@ -372,6 +381,11 @@ static int ov5647_stream_on(struct v4l2_\n \t\treturn ret;\n \t}\n \n+\t/* Apply customized values from user when stream starts */\n+\tret =  __v4l2_ctrl_handler_setup(sd->ctrl_handler);\n+\tif (ret)\n+\t\treturn ret;\n+\n \tif (ov5647->flags & V4L2_MBUS_CSI2_NONCONTINUOUS_CLOCK)\n \t\tval |= MIPI_CTRL00_CLOCK_LANE_GATE |\n \t\t       MIPI_CTRL00_LINE_SYNC_ENABLE;\n@@ -753,6 +767,120 @@ static int ov5647_parse_dt(struct device\n \treturn ret;\n }\n \n+static int ov5647_s_auto_white_balance(struct v4l2_subdev *sd, u32 val)\n+{\n+\t/* non-zero turns on AWB */\n+\treturn ov5647_write(sd, OV5647_REG_AWB, val ? 1 : 0);\n+}\n+\n+static int ov5647_s_autogain(struct v4l2_subdev *sd, u32 val)\n+{\n+\tint ret;\n+\tu8 reg;\n+\n+\t/* non-zero turns on AGC by clearing bit 1 */\n+\tret = ov5647_read(sd, OV5647_REG_AEC_AGC, &reg);\n+\tif (ret == 0)\n+\t\tret = ov5647_write(sd, OV5647_REG_AEC_AGC,\n+\t\t\t\t   val ? reg & ~2 : reg | 2);\n+\n+\treturn ret;\n+}\n+\n+static int ov5647_s_exposure_auto(struct v4l2_subdev *sd, u32 val)\n+{\n+\tint ret;\n+\tu8 reg;\n+\n+\t/* Everything except V4L2_EXPOSURE_MANUAL turns on AEC by\n+\t * clearing bit 0\n+\t */\n+\tret = ov5647_read(sd, OV5647_REG_AEC_AGC, &reg);\n+\tif (ret == 0)\n+\t\tret = ov5647_write(sd, OV5647_REG_AEC_AGC,\n+\t\t\t\t   val == V4L2_EXPOSURE_MANUAL ?\n+\t\t\t\t   reg | 1 : reg & ~1);\n+\n+\treturn ret;\n+}\n+\n+static int ov5647_s_analogue_gain(struct v4l2_subdev *sd, u32 val)\n+{\n+\tint ret;\n+\n+\t/* 10 bits of gain, 2 in the high register */\n+\tret = ov5647_write(sd, OV5647_REG_GAIN_HI, (val >> 8) & 3);\n+\tif (ret == 0)\n+\t\tret = ov5647_write(sd, OV5647_REG_GAIN_LO, val & 0xff);\n+\n+\treturn ret;\n+}\n+\n+static int ov5647_s_exposure(struct v4l2_subdev *sd, u32 val)\n+{\n+\tint ret;\n+\n+\t/* Sensor has 20 bits, but the bottom 4 bits are fractions of a line\n+\t * which we leave as zero (and don't receive in \"val\").\n+\t */\n+\tret = ov5647_write(sd, OV5647_REG_EXP_HI, (val >> 12) & 0xf);\n+\tif (ret == 0)\n+\t\tov5647_write(sd, OV5647_REG_EXP_MID, (val >> 4) & 0xff);\n+\tif (ret == 0)\n+\t\tov5647_write(sd, OV5647_REG_EXP_LO, (val & 0xf) << 4);\n+\n+\treturn ret;\n+}\n+\n+static int ov5647_s_ctrl(struct v4l2_ctrl *ctrl)\n+{\n+\tstruct ov5647 *state = container_of(ctrl->handler,\n+\t\t\t\t\t     struct ov5647, ctrls);\n+\tstruct v4l2_subdev *sd = &state->sd;\n+\tstruct i2c_client *client = v4l2_get_subdevdata(sd);\n+\tint ret = 0;\n+\n+\t/* v4l2_ctrl_lock() locks our own mutex */\n+\n+\t/*\n+\t * If the device is not powered up by the host driver do\n+\t * not apply any controls to H/W at this time. Instead\n+\t * the controls will be restored right after power-up.\n+\t */\n+\tif (state->power_count == 0)\n+\t\treturn 0;\n+\n+\tswitch (ctrl->id) {\n+\tcase V4L2_CID_AUTO_WHITE_BALANCE:\n+\t\tret = ov5647_s_auto_white_balance(sd, ctrl->val);\n+\t\tbreak;\n+\tcase V4L2_CID_AUTOGAIN:\n+\t\tret = ov5647_s_autogain(sd, ctrl->val);\n+\t\tbreak;\n+\tcase V4L2_CID_EXPOSURE_AUTO:\n+\t\tret = ov5647_s_exposure_auto(sd, ctrl->val);\n+\t\tbreak;\n+\tcase V4L2_CID_ANALOGUE_GAIN:\n+\t\tret = ov5647_s_analogue_gain(sd, ctrl->val);\n+\t\tbreak;\n+\tcase V4L2_CID_EXPOSURE:\n+\t\tret = ov5647_s_exposure(sd, ctrl->val);\n+\t\tbreak;\n+\tdefault:\n+\t\tdev_info(&client->dev,\n+\t\t\t \"ctrl(id:0x%x,val:0x%x) is not handled\\n\",\n+\t\t\t ctrl->id, ctrl->val);\n+\t\tret = -EINVAL;\n+\t\tbreak;\n+\t}\n+\n+\treturn ret;\n+}\n+\n+static const struct v4l2_ctrl_ops ov5647_ctrl_ops = {\n+\t.s_ctrl = ov5647_s_ctrl,\n+};\n+\n static int ov5647_probe(struct i2c_client *client)\n {\n \tstruct device *dev = &client->dev;\n@@ -761,6 +889,7 @@ static int ov5647_probe(struct i2c_clien\n \tstruct v4l2_subdev *sd;\n \tstruct device_node *np = client->dev.of_node;\n \tu32 xclk_freq;\n+\tstruct v4l2_ctrl *ctrl;\n \n \tsensor = devm_kzalloc(dev, sizeof(*sensor), GFP_KERNEL);\n \tif (!sensor)\n@@ -793,6 +922,48 @@ static int ov5647_probe(struct i2c_clien\n \n \tmutex_init(&sensor->lock);\n \n+\t/* Initialise controls. */\n+\tv4l2_ctrl_handler_init(&sensor->ctrls, 3);\n+\tv4l2_ctrl_new_std(&sensor->ctrls, &ov5647_ctrl_ops,\n+\t\t\t  V4L2_CID_AUTOGAIN,\n+\t\t\t  0,  /* min */\n+\t\t\t  1,  /* max */\n+\t\t\t  1,  /* step */\n+\t\t\t  1); /* default */\n+\tv4l2_ctrl_new_std(&sensor->ctrls, &ov5647_ctrl_ops,\n+\t\t\t  V4L2_CID_AUTO_WHITE_BALANCE,\n+\t\t\t  0,  /* min */\n+\t\t\t  1,  /* max */\n+\t\t\t  1,  /* step */\n+\t\t\t  1); /* default */\n+\tv4l2_ctrl_new_std_menu(&sensor->ctrls, &ov5647_ctrl_ops,\n+\t\t\t       V4L2_CID_EXPOSURE_AUTO,\n+\t\t\t       V4L2_EXPOSURE_MANUAL,  /* max */\n+\t\t\t       0,                     /* skip_mask */\n+\t\t\t       V4L2_EXPOSURE_AUTO);   /* default */\n+\tctrl = v4l2_ctrl_new_std(&sensor->ctrls, &ov5647_ctrl_ops,\n+\t\t\t\t V4L2_CID_EXPOSURE,\n+\t\t\t\t 4,     /* min lines */\n+\t\t\t\t 65535, /* max lines (4+8+4 bits)*/\n+\t\t\t\t 1,     /* step */\n+\t\t\t\t 1000); /* default number of lines */\n+\tctrl->flags |= V4L2_CTRL_FLAG_EXECUTE_ON_WRITE;\n+\tctrl = v4l2_ctrl_new_std(&sensor->ctrls, &ov5647_ctrl_ops,\n+\t\t\t\t V4L2_CID_ANALOGUE_GAIN,\n+\t\t\t\t 16,   /* min, 16 = 1.0x */\n+\t\t\t\t 1023, /* max (10 bits) */\n+\t\t\t\t 1,    /* step */\n+\t\t\t\t 32);  /* default, 32 = 2.0x */\n+\tctrl->flags |= V4L2_CTRL_FLAG_EXECUTE_ON_WRITE;\n+\n+\tif (sensor->ctrls.error) {\n+\t\tret = sensor->ctrls.error;\n+\t\tdev_err(&client->dev, \"%s control init failed (%d)\\n\",\n+\t\t\t__func__, ret);\n+\t\tgoto error;\n+\t}\n+\tsensor->sd.ctrl_handler = &sensor->ctrls;\n+\n \t/* Set the default mode before we init the subdev */\n \tsensor->mode = OV5647_DEFAULT_MODE;\n \n@@ -828,6 +999,7 @@ static int ov5647_probe(struct i2c_clien\n error:\n \tmedia_entity_cleanup(&sd->entity);\n mutex_remove:\n+\tv4l2_ctrl_handler_free(&sensor->ctrls);\n \tmutex_destroy(&sensor->lock);\n \treturn ret;\n }\n@@ -839,6 +1011,7 @@ static int ov5647_remove(struct i2c_clie\n \n \tv4l2_async_unregister_subdev(&ov5647->sd);\n \tmedia_entity_cleanup(&ov5647->sd.entity);\n+\tv4l2_ctrl_handler_free(&ov5647->ctrls);\n \tv4l2_device_unregister_subdev(sd);\n \tmutex_destroy(&ov5647->lock);\n \n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0228-media-ov5647-Add-extra-10-bit-sensor-modes.patch",
    "content": "From 004f4065edbb817a54121937514eb94159ecce69 Mon Sep 17 00:00:00 2001\nFrom: David Plowman <david.plowman@raspberrypi.com>\nDate: Wed, 29 Jan 2020 15:31:28 +0000\nSubject: [PATCH] media: ov5647: Add extra 10-bit sensor modes.\n\nThe 8-bit VGA mode remains, we add the following 10-bit modes:\n\nMode 0: 2592x1944 full resolution.\n\nMode 1: 1920x1080 full resolution, but centre-cropped.\n(This mode achieves 30fps, mode 0 does not.)\n\nMode 2: 1296x972 full field-of-view 2x2 binned mode.\n\nMode 3: VGA full field of view mode.\n\nSigned-off-by: David Plowman <david.plowman@raspberrypi.com>\nSigned-off-by: Naushir Patuck <naush@raspberrypi.com>\n---\n drivers/media/i2c/ov5647.c | 463 ++++++++++++++++++++++++++++++++++++-\n 1 file changed, 452 insertions(+), 11 deletions(-)\n\n--- a/drivers/media/i2c/ov5647.c\n+++ b/drivers/media/i2c/ov5647.c\n@@ -111,6 +111,7 @@ struct ov5647 {\n \tstruct gpio_desc\t\t*pwdn;\n \tunsigned int\t\t\tflags;\n \tstruct v4l2_ctrl_handler\tctrls;\n+\tbool\t\t\t\twrite_mode_regs;\n };\n \n static inline struct ov5647 *to_state(struct v4l2_subdev *sd)\n@@ -130,7 +131,7 @@ static struct regval_list sensor_oe_enab\n \t{0x3002, 0xe4},\n };\n \n-static struct regval_list ov5647_640x480[] = {\n+static struct regval_list ov5647_640x480_8bit[] = {\n \t{0x0100, 0x00},\n \t{0x0103, 0x01},\n \t{0x3034, 0x08},\n@@ -220,9 +221,378 @@ static struct regval_list ov5647_640x480\n \t{0x0100, 0x01},\n };\n \n+static struct regval_list ov5647_2592x1944_10bit[] = {\n+\t{0x0100, 0x00},\n+\t{0x0103, 0x01},\n+\t{0x3034, 0x1a},\n+\t{0x3035, 0x21},\n+\t{0x3036, 0x69},\n+\t{0x303c, 0x11},\n+\t{0x3106, 0xf5},\n+\t{0x3821, 0x06},\n+\t{0x3820, 0x00},\n+\t{0x3827, 0xec},\n+\t{0x370c, 0x03},\n+\t{0x3612, 0x5b},\n+\t{0x3618, 0x04},\n+\t{0x5000, 0x06},\n+\t{0x5002, 0x41},\n+\t{0x5003, 0x08},\n+\t{0x5a00, 0x08},\n+\t{0x3000, 0x00},\n+\t{0x3001, 0x00},\n+\t{0x3002, 0x00},\n+\t{0x3016, 0x08},\n+\t{0x3017, 0xe0},\n+\t{0x3018, 0x44},\n+\t{0x301c, 0xf8},\n+\t{0x301d, 0xf0},\n+\t{0x3a18, 0x00},\n+\t{0x3a19, 0xf8},\n+\t{0x3c01, 0x80},\n+\t{0x3b07, 0x0c},\n+\t{0x380c, 0x0b},\n+\t{0x380d, 0x1c},\n+\t{0x380e, 0x07},\n+\t{0x380f, 0xb0},\n+\t{0x3814, 0x11},\n+\t{0x3815, 0x11},\n+\t{0x3708, 0x64},\n+\t{0x3709, 0x12},\n+\t{0x3808, 0x0a},\n+\t{0x3809, 0x20},\n+\t{0x380a, 0x07},\n+\t{0x380b, 0x98},\n+\t{0x3800, 0x00},\n+\t{0x3801, 0x00},\n+\t{0x3802, 0x00},\n+\t{0x3803, 0x00},\n+\t{0x3804, 0x0a},\n+\t{0x3805, 0x3f},\n+\t{0x3806, 0x07},\n+\t{0x3807, 0xa3},\n+\t{0x3811, 0x10},\n+\t{0x3813, 0x06},\n+\t{0x3630, 0x2e},\n+\t{0x3632, 0xe2},\n+\t{0x3633, 0x23},\n+\t{0x3634, 0x44},\n+\t{0x3636, 0x06},\n+\t{0x3620, 0x64},\n+\t{0x3621, 0xe0},\n+\t{0x3600, 0x37},\n+\t{0x3704, 0xa0},\n+\t{0x3703, 0x5a},\n+\t{0x3715, 0x78},\n+\t{0x3717, 0x01},\n+\t{0x3731, 0x02},\n+\t{0x370b, 0x60},\n+\t{0x3705, 0x1a},\n+\t{0x3f05, 0x02},\n+\t{0x3f06, 0x10},\n+\t{0x3f01, 0x0a},\n+\t{0x3a08, 0x01},\n+\t{0x3a09, 0x28},\n+\t{0x3a0a, 0x00},\n+\t{0x3a0b, 0xf6},\n+\t{0x3a0d, 0x08},\n+\t{0x3a0e, 0x06},\n+\t{0x3a0f, 0x58},\n+\t{0x3a10, 0x50},\n+\t{0x3a1b, 0x58},\n+\t{0x3a1e, 0x50},\n+\t{0x3a11, 0x60},\n+\t{0x3a1f, 0x28},\n+\t{0x4001, 0x02},\n+\t{0x4004, 0x04},\n+\t{0x4000, 0x09},\n+\t{0x4837, 0x19},\n+\t{0x4800, 0x24},\n+\t{0x3503, 0x03},\n+\t{0x0100, 0x01},\n+};\n+\n+static struct regval_list ov5647_1080p30_10bit[] = {\n+\t{0x0100, 0x00},\n+\t{0x0103, 0x01},\n+\t{0x3034, 0x1a},\n+\t{0x3035, 0x21},\n+\t{0x3036, 0x62},\n+\t{0x303c, 0x11},\n+\t{0x3106, 0xf5},\n+\t{0x3821, 0x06},\n+\t{0x3820, 0x00},\n+\t{0x3827, 0xec},\n+\t{0x370c, 0x03},\n+\t{0x3612, 0x5b},\n+\t{0x3618, 0x04},\n+\t{0x5000, 0x06},\n+\t{0x5002, 0x41},\n+\t{0x5003, 0x08},\n+\t{0x5a00, 0x08},\n+\t{0x3000, 0x00},\n+\t{0x3001, 0x00},\n+\t{0x3002, 0x00},\n+\t{0x3016, 0x08},\n+\t{0x3017, 0xe0},\n+\t{0x3018, 0x44},\n+\t{0x301c, 0xf8},\n+\t{0x301d, 0xf0},\n+\t{0x3a18, 0x00},\n+\t{0x3a19, 0xf8},\n+\t{0x3c01, 0x80},\n+\t{0x3b07, 0x0c},\n+\t{0x380c, 0x09},\n+\t{0x380d, 0x70},\n+\t{0x380e, 0x04},\n+\t{0x380f, 0x50},\n+\t{0x3814, 0x11},\n+\t{0x3815, 0x11},\n+\t{0x3708, 0x64},\n+\t{0x3709, 0x12},\n+\t{0x3808, 0x07},\n+\t{0x3809, 0x80},\n+\t{0x380a, 0x04},\n+\t{0x380b, 0x38},\n+\t{0x3800, 0x01},\n+\t{0x3801, 0x5c},\n+\t{0x3802, 0x01},\n+\t{0x3803, 0xb2},\n+\t{0x3804, 0x08},\n+\t{0x3805, 0xe3},\n+\t{0x3806, 0x05},\n+\t{0x3807, 0xf1},\n+\t{0x3811, 0x04},\n+\t{0x3813, 0x02},\n+\t{0x3630, 0x2e},\n+\t{0x3632, 0xe2},\n+\t{0x3633, 0x23},\n+\t{0x3634, 0x44},\n+\t{0x3636, 0x06},\n+\t{0x3620, 0x64},\n+\t{0x3621, 0xe0},\n+\t{0x3600, 0x37},\n+\t{0x3704, 0xa0},\n+\t{0x3703, 0x5a},\n+\t{0x3715, 0x78},\n+\t{0x3717, 0x01},\n+\t{0x3731, 0x02},\n+\t{0x370b, 0x60},\n+\t{0x3705, 0x1a},\n+\t{0x3f05, 0x02},\n+\t{0x3f06, 0x10},\n+\t{0x3f01, 0x0a},\n+\t{0x3a08, 0x01},\n+\t{0x3a09, 0x4b},\n+\t{0x3a0a, 0x01},\n+\t{0x3a0b, 0x13},\n+\t{0x3a0d, 0x04},\n+\t{0x3a0e, 0x03},\n+\t{0x3a0f, 0x58},\n+\t{0x3a10, 0x50},\n+\t{0x3a1b, 0x58},\n+\t{0x3a1e, 0x50},\n+\t{0x3a11, 0x60},\n+\t{0x3a1f, 0x28},\n+\t{0x4001, 0x02},\n+\t{0x4004, 0x04},\n+\t{0x4000, 0x09},\n+\t{0x4837, 0x19},\n+\t{0x4800, 0x34},\n+\t{0x3503, 0x03},\n+\t{0x0100, 0x01},\n+};\n+\n+static struct regval_list ov5647_2x2binned_10bit[] = {\n+\t{0x0100, 0x00},\n+\t{0x0103, 0x01},\n+\t{0x3034, 0x1A},\n+\t{0x3035, 0x21},\n+\t{0x3036, 0x62},\n+\t{0x303C, 0x11},\n+\t{0x3106, 0xF5},\n+\t{0x3827, 0xEC},\n+\t{0x370C, 0x03},\n+\t{0x3612, 0x59},\n+\t{0x3618, 0x00},\n+\t{0x5000, 0x06},\n+\t{0x5002, 0x41},\n+\t{0x5003, 0x08},\n+\t{0x5A00, 0x08},\n+\t{0x3000, 0x00},\n+\t{0x3001, 0x00},\n+\t{0x3002, 0x00},\n+\t{0x3016, 0x08},\n+\t{0x3017, 0xE0},\n+\t{0x3018, 0x44},\n+\t{0x301C, 0xF8},\n+\t{0x301D, 0xF0},\n+\t{0x3A18, 0x00},\n+\t{0x3A19, 0xF8},\n+\t{0x3C01, 0x80},\n+\t{0x3B07, 0x0C},\n+\t{0x3800, 0x00},\n+\t{0x3801, 0x00},\n+\t{0x3802, 0x00},\n+\t{0x3803, 0x00},\n+\t{0x3804, 0x0A},\n+\t{0x3805, 0x3F},\n+\t{0x3806, 0x07},\n+\t{0x3807, 0xA3},\n+\t{0x3808, 0x05},\n+\t{0x3809, 0x10},\n+\t{0x380A, 0x03},\n+\t{0x380B, 0xCC},\n+\t{0x380C, 0x07},\n+\t{0x380D, 0x68},\n+\t{0x3811, 0x0c},\n+\t{0x3813, 0x06},\n+\t{0x3814, 0x31},\n+\t{0x3815, 0x31},\n+\t{0x3630, 0x2E},\n+\t{0x3632, 0xE2},\n+\t{0x3633, 0x23},\n+\t{0x3634, 0x44},\n+\t{0x3636, 0x06},\n+\t{0x3620, 0x64},\n+\t{0x3621, 0xE0},\n+\t{0x3600, 0x37},\n+\t{0x3704, 0xA0},\n+\t{0x3703, 0x5A},\n+\t{0x3715, 0x78},\n+\t{0x3717, 0x01},\n+\t{0x3731, 0x02},\n+\t{0x370B, 0x60},\n+\t{0x3705, 0x1A},\n+\t{0x3F05, 0x02},\n+\t{0x3F06, 0x10},\n+\t{0x3F01, 0x0A},\n+\t{0x3A08, 0x01},\n+\t{0x3A09, 0x28},\n+\t{0x3A0A, 0x00},\n+\t{0x3A0B, 0xF6},\n+\t{0x3A0D, 0x08},\n+\t{0x3A0E, 0x06},\n+\t{0x3A0F, 0x58},\n+\t{0x3A10, 0x50},\n+\t{0x3A1B, 0x58},\n+\t{0x3A1E, 0x50},\n+\t{0x3A11, 0x60},\n+\t{0x3A1F, 0x28},\n+\t{0x4001, 0x02},\n+\t{0x4004, 0x04},\n+\t{0x4000, 0x09},\n+\t{0x4837, 0x16},\n+\t{0x4800, 0x24},\n+\t{0x3503, 0x03},\n+\t{0x3820, 0x41},\n+\t{0x3821, 0x07},\n+\t{0x380E, 0x05},\n+\t{0x380F, 0x9B},\n+\t{0x350A, 0x00},\n+\t{0x350B, 0x10},\n+\t{0x3500, 0x00},\n+\t{0x3501, 0x1A},\n+\t{0x3502, 0xF0},\n+\t{0x3212, 0xA0},\n+\t{0x0100, 0x01},\n+};\n+\n+static struct regval_list ov5647_640x480_10bit[] = {\n+\t{0x0100, 0x00},\n+\t{0x0103, 0x01},\n+\t{0x3035, 0x11},\n+\t{0x3036, 0x46},\n+\t{0x303c, 0x11},\n+\t{0x3821, 0x07},\n+\t{0x3820, 0x41},\n+\t{0x370c, 0x03},\n+\t{0x3612, 0x59},\n+\t{0x3618, 0x00},\n+\t{0x5000, 0x06},\n+\t{0x5003, 0x08},\n+\t{0x5a00, 0x08},\n+\t{0x3000, 0xff},\n+\t{0x3001, 0xff},\n+\t{0x3002, 0xff},\n+\t{0x301d, 0xf0},\n+\t{0x3a18, 0x00},\n+\t{0x3a19, 0xf8},\n+\t{0x3c01, 0x80},\n+\t{0x3b07, 0x0c},\n+\t{0x380c, 0x07},\n+\t{0x380d, 0x3c},\n+\t{0x380e, 0x01},\n+\t{0x380f, 0xf8},\n+\t{0x3814, 0x35},\n+\t{0x3815, 0x35},\n+\t{0x3708, 0x64},\n+\t{0x3709, 0x52},\n+\t{0x3808, 0x02},\n+\t{0x3809, 0x80},\n+\t{0x380a, 0x01},\n+\t{0x380b, 0xe0},\n+\t{0x3800, 0x00},\n+\t{0x3801, 0x10},\n+\t{0x3802, 0x00},\n+\t{0x3803, 0x00},\n+\t{0x3804, 0x0a},\n+\t{0x3805, 0x2f},\n+\t{0x3806, 0x07},\n+\t{0x3807, 0x9f},\n+\t{0x3630, 0x2e},\n+\t{0x3632, 0xe2},\n+\t{0x3633, 0x23},\n+\t{0x3634, 0x44},\n+\t{0x3620, 0x64},\n+\t{0x3621, 0xe0},\n+\t{0x3600, 0x37},\n+\t{0x3704, 0xa0},\n+\t{0x3703, 0x5a},\n+\t{0x3715, 0x78},\n+\t{0x3717, 0x01},\n+\t{0x3731, 0x02},\n+\t{0x370b, 0x60},\n+\t{0x3705, 0x1a},\n+\t{0x3f05, 0x02},\n+\t{0x3f06, 0x10},\n+\t{0x3f01, 0x0a},\n+\t{0x3a08, 0x01},\n+\t{0x3a09, 0x2e},\n+\t{0x3a0a, 0x00},\n+\t{0x3a0b, 0xfb},\n+\t{0x3a0d, 0x02},\n+\t{0x3a0e, 0x01},\n+\t{0x3a0f, 0x58},\n+\t{0x3a10, 0x50},\n+\t{0x3a1b, 0x58},\n+\t{0x3a1e, 0x50},\n+\t{0x3a11, 0x60},\n+\t{0x3a1f, 0x28},\n+\t{0x4001, 0x02},\n+\t{0x4004, 0x02},\n+\t{0x4000, 0x09},\n+\t{0x3000, 0x00},\n+\t{0x3001, 0x00},\n+\t{0x3002, 0x00},\n+\t{0x3017, 0xe0},\n+\t{0x301c, 0xfc},\n+\t{0x3636, 0x06},\n+\t{0x3016, 0x08},\n+\t{0x3827, 0xec},\n+\t{0x3018, 0x44},\n+\t{0x3035, 0x21},\n+\t{0x3106, 0xf5},\n+\t{0x3034, 0x1a},\n+\t{0x301c, 0xf8},\n+\t{0x4800, 0x34},\n+\t{0x3503, 0x03},\n+\t{0x0100, 0x01},\n+};\n+\n static struct ov5647_mode supported_modes_8bit[] = {\n \t/*\n-\t * Original 8-bit VGA mode\n+\t * MODE 0: Original 8-bit VGA mode.\n \t * Uncentred crop (top left quarter) from 2x2 binned 1296x972 image.\n \t */\n \t{\n@@ -233,14 +603,70 @@ static struct ov5647_mode supported_mode\n \t\t\t.width = 640,\n \t\t\t.height = 480\n \t\t},\n-\t\tov5647_640x480,\n-\t\tARRAY_SIZE(ov5647_640x480)\n+\t\tov5647_640x480_8bit,\n+\t\tARRAY_SIZE(ov5647_640x480_8bit)\n \t},\n-\t/* more modes below here... */\n };\n \n static struct ov5647_mode supported_modes_10bit[] = {\n-\t/* no 10-bit modes yet */\n+\t/*\n+\t * MODE 0: 2592x1944 full resolution full FOV 10-bit mode.\n+\t */\n+\t{\n+\t\t{\n+\t\t\t.code = MEDIA_BUS_FMT_SBGGR10_1X10,\n+\t\t\t.colorspace = V4L2_COLORSPACE_SRGB,\n+\t\t\t.field = V4L2_FIELD_NONE,\n+\t\t\t.width = 2592,\n+\t\t\t.height = 1944\n+\t\t},\n+\t\tov5647_2592x1944_10bit,\n+\t\tARRAY_SIZE(ov5647_2592x1944_10bit)\n+\t},\n+\t/*\n+\t * MODE 1: 1080p30 10-bit mode.\n+\t * Full resolution centre-cropped down to 1080p.\n+\t */\n+\t{\n+\t\t{\n+\t\t\t.code = MEDIA_BUS_FMT_SBGGR10_1X10,\n+\t\t\t.colorspace = V4L2_COLORSPACE_SRGB,\n+\t\t\t.field = V4L2_FIELD_NONE,\n+\t\t\t.width = 1920,\n+\t\t\t.height = 1080\n+\t\t},\n+\t\tov5647_1080p30_10bit,\n+\t\tARRAY_SIZE(ov5647_1080p30_10bit)\n+\t},\n+\t/*\n+\t * MODE 2: 2x2 binned full FOV 10-bit mode.\n+\t */\n+\t{\n+\t\t{\n+\t\t\t.code = MEDIA_BUS_FMT_SBGGR10_1X10,\n+\t\t\t.colorspace = V4L2_COLORSPACE_SRGB,\n+\t\t\t.field = V4L2_FIELD_NONE,\n+\t\t\t.width = 1296,\n+\t\t\t.height = 972\n+\t\t},\n+\t\tov5647_2x2binned_10bit,\n+\t\tARRAY_SIZE(ov5647_2x2binned_10bit)\n+\t},\n+\t/*\n+\t * MODE 3: 10-bit VGA full FOV mode 60fps.\n+\t * 2x2 binned and subsampled down to VGA.\n+\t */\n+\t{\n+\t\t{\n+\t\t\t.code = MEDIA_BUS_FMT_SBGGR10_1X10,\n+\t\t\t.colorspace = V4L2_COLORSPACE_SRGB,\n+\t\t\t.field = V4L2_FIELD_NONE,\n+\t\t\t.width = 640,\n+\t\t\t.height = 480\n+\t\t},\n+\t\tov5647_640x480_10bit,\n+\t\tARRAY_SIZE(ov5647_640x480_10bit)\n+\t},\n };\n \n /* Use original 8-bit VGA mode as default. */\n@@ -343,11 +769,14 @@ static int __sensor_init(struct v4l2_sub\n \tif (ret < 0)\n \t\treturn ret;\n \n-\tret = ov5647_write_array(sd, state->mode->reg_list,\n-\t\t\t\t state->mode->num_regs);\n-\tif (ret < 0) {\n-\t\tdev_err(&client->dev, \"write sensor default regs error\\n\");\n-\t\treturn ret;\n+\tif (state->write_mode_regs) {\n+\t\tret = ov5647_write_array(sd, state->mode->reg_list,\n+\t\t\t\t\t state->mode->num_regs);\n+\t\tif (ret < 0) {\n+\t\t\tdev_err(&client->dev, \"write sensor default regs error\\n\");\n+\t\t\treturn ret;\n+\t\t}\n+\t\tstate->write_mode_regs = false;\n \t}\n \n \tret = ov5647_set_virtual_channel(sd, 0);\n@@ -475,6 +904,9 @@ static int ov5647_sensor_power(struct v4\n \t\t\t\t\"Camera not available, check Power\\n\");\n \t\t\tgoto out;\n \t\t}\n+\n+\t\t/* Write out the register set over I2C on stream-on. */\n+\t\tov5647->write_mode_regs = true;\n \t} else if (!on && ov5647->power_count == 1) {\n \t\tdev_dbg(&client->dev, \"OV5647 power off\\n\");\n \n@@ -650,6 +1082,12 @@ static int ov5647_set_fmt(struct v4l2_su\n \t\tframefmt = v4l2_subdev_get_try_format(sd, cfg, format->pad);\n \t\t*framefmt = format->format;\n \t} else {\n+\t\t/*\n+\t\t * If we have changed modes, write the I2C register list on\n+\t\t * a stream_on().\n+\t\t */\n+\t\tif (state->mode != mode)\n+\t\t\tstate->write_mode_regs = true;\n \t\tstate->mode = mode;\n \t}\n \n@@ -967,6 +1405,9 @@ static int ov5647_probe(struct i2c_clien\n \t/* Set the default mode before we init the subdev */\n \tsensor->mode = OV5647_DEFAULT_MODE;\n \n+\t/* Write out the register set over I2C on stream-on. */\n+\tsensor->write_mode_regs = true;\n+\n \tsd = &sensor->sd;\n \tv4l2_i2c_subdev_init(sd, client, &ov5647_subdev_ops);\n \tsensor->sd.internal_ops = &ov5647_subdev_internal_ops;\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0229-media-ov5647-change-defaults-to-better-match-raw-cam.patch",
    "content": "From aab5d5842d718544ef906dc8cc5c221e6121160f Mon Sep 17 00:00:00 2001\nFrom: David Plowman <david.plowman@raspberrypi.com>\nDate: Wed, 29 Jan 2020 15:31:32 +0000\nSubject: [PATCH] media: ov5647: change defaults to better match raw\n camera applications.\n\nSpecifically:\n\n* AWB is now off by default.\n\n* AEC/AGC is also off by default.\n\n* The default mode is changed to the 10-bit 2x2 binned mode.\n\nAWB and AEC/AGC can be re-enabled using the usual V4L2 controls. The\noriginal 8-bit mode will be respected if an application requests the\n8-bit format.\n\nSigned-off-by: David Plowman <david.plowman@raspberrypi.com>\nSigned-off-by: Naushir Patuck <naush@raspberrypi.com>\n---\n drivers/media/i2c/ov5647.c | 10 +++++-----\n 1 file changed, 5 insertions(+), 5 deletions(-)\n\n--- a/drivers/media/i2c/ov5647.c\n+++ b/drivers/media/i2c/ov5647.c\n@@ -669,8 +669,8 @@ static struct ov5647_mode supported_mode\n \t},\n };\n \n-/* Use original 8-bit VGA mode as default. */\n-#define OV5647_DEFAULT_MODE (&supported_modes_8bit[0])\n+/* Use 2x2 binned 10-bit mode as default. */\n+#define OV5647_DEFAULT_MODE (&supported_modes_10bit[2])\n \n static int ov5647_write(struct v4l2_subdev *sd, u16 reg, u8 val)\n {\n@@ -1367,18 +1367,18 @@ static int ov5647_probe(struct i2c_clien\n \t\t\t  0,  /* min */\n \t\t\t  1,  /* max */\n \t\t\t  1,  /* step */\n-\t\t\t  1); /* default */\n+\t\t\t  0); /* default */\n \tv4l2_ctrl_new_std(&sensor->ctrls, &ov5647_ctrl_ops,\n \t\t\t  V4L2_CID_AUTO_WHITE_BALANCE,\n \t\t\t  0,  /* min */\n \t\t\t  1,  /* max */\n \t\t\t  1,  /* step */\n-\t\t\t  1); /* default */\n+\t\t\t  0); /* default */\n \tv4l2_ctrl_new_std_menu(&sensor->ctrls, &ov5647_ctrl_ops,\n \t\t\t       V4L2_CID_EXPOSURE_AUTO,\n \t\t\t       V4L2_EXPOSURE_MANUAL,  /* max */\n \t\t\t       0,                     /* skip_mask */\n-\t\t\t       V4L2_EXPOSURE_AUTO);   /* default */\n+\t\t\t       V4L2_EXPOSURE_MANUAL); /* default */\n \tctrl = v4l2_ctrl_new_std(&sensor->ctrls, &ov5647_ctrl_ops,\n \t\t\t\t V4L2_CID_EXPOSURE,\n \t\t\t\t 4,     /* min lines */\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0230-media-i2c-ov5647-Add-support-for-g_selection-to-refl.patch",
    "content": "From 450dc10dd858314fcb5e18942b6e5260e3478f10 Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Wed, 29 Apr 2020 11:46:07 +0100\nSubject: [PATCH] media: i2c: ov5647: Add support for g_selection to\n reflect cropping/binning\n\nIn order to apply lens shading correctly the client needs to know how\neach mode crops or scales the image compared to the full sensor array.\nImplement this (based on the imx219 equivalent).\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n drivers/media/i2c/ov5647.c | 119 ++++++++++++++++++++++++++++++-------\n 1 file changed, 96 insertions(+), 23 deletions(-)\n\n--- a/drivers/media/i2c/ov5647.c\n+++ b/drivers/media/i2c/ov5647.c\n@@ -70,25 +70,14 @@\n #define VAL_TERM 0xfe\n #define REG_DLY  0xffff\n \n-#define OV5647_ROW_START\t\t0x01\n-#define OV5647_ROW_START_MIN\t\t0\n-#define OV5647_ROW_START_MAX\t\t2004\n-#define OV5647_ROW_START_DEF\t\t54\n-\n-#define OV5647_COLUMN_START\t\t0x02\n-#define OV5647_COLUMN_START_MIN\t\t0\n-#define OV5647_COLUMN_START_MAX\t\t2750\n-#define OV5647_COLUMN_START_DEF\t\t16\n-\n-#define OV5647_WINDOW_HEIGHT\t\t0x03\n-#define OV5647_WINDOW_HEIGHT_MIN\t2\n-#define OV5647_WINDOW_HEIGHT_MAX\t2006\n-#define OV5647_WINDOW_HEIGHT_DEF\t1944\n-\n-#define OV5647_WINDOW_WIDTH\t\t0x04\n-#define OV5647_WINDOW_WIDTH_MIN\t\t2\n-#define OV5647_WINDOW_WIDTH_MAX\t\t2752\n-#define OV5647_WINDOW_WIDTH_DEF\t\t2592\n+/* OV5647 native and active pixel array size */\n+#define OV5647_NATIVE_WIDTH\t\t2624U\n+#define OV5647_NATIVE_HEIGHT\t\t1956U\n+\n+#define OV5647_PIXEL_ARRAY_LEFT\t\t16U\n+#define OV5647_PIXEL_ARRAY_TOP\t\t16U\n+#define OV5647_PIXEL_ARRAY_WIDTH\t2592U\n+#define OV5647_PIXEL_ARRAY_HEIGHT\t1944U\n \n struct regval_list {\n \tu16 addr;\n@@ -97,6 +86,9 @@ struct regval_list {\n \n struct ov5647_mode {\n \tstruct v4l2_mbus_framefmt\tformat;\n+\t/* Analog crop rectangle. */\n+\tstruct v4l2_rect crop;\n+\n \tstruct regval_list\t\t*reg_list;\n \tunsigned int\t\t\tnum_regs;\n };\n@@ -603,6 +595,12 @@ static struct ov5647_mode supported_mode\n \t\t\t.width = 640,\n \t\t\t.height = 480\n \t\t},\n+\t\t.crop = {\n+\t\t\t.left = 0,\n+\t\t\t.top = 0,\n+\t\t\t.width = 1280,\n+\t\t\t.height = 960,\n+\t\t},\n \t\tov5647_640x480_8bit,\n \t\tARRAY_SIZE(ov5647_640x480_8bit)\n \t},\n@@ -620,6 +618,12 @@ static struct ov5647_mode supported_mode\n \t\t\t.width = 2592,\n \t\t\t.height = 1944\n \t\t},\n+\t\t.crop = {\n+\t\t\t.left = 0,\n+\t\t\t.top = 0,\n+\t\t\t.width = 2592,\n+\t\t\t.height = 1944\n+\t\t},\n \t\tov5647_2592x1944_10bit,\n \t\tARRAY_SIZE(ov5647_2592x1944_10bit)\n \t},\n@@ -635,6 +639,12 @@ static struct ov5647_mode supported_mode\n \t\t\t.width = 1920,\n \t\t\t.height = 1080\n \t\t},\n+\t\t.crop = {\n+\t\t\t.left = 348,\n+\t\t\t.top = 434,\n+\t\t\t.width = 1928,\n+\t\t\t.height = 1080,\n+\t\t},\n \t\tov5647_1080p30_10bit,\n \t\tARRAY_SIZE(ov5647_1080p30_10bit)\n \t},\n@@ -649,6 +659,12 @@ static struct ov5647_mode supported_mode\n \t\t\t.width = 1296,\n \t\t\t.height = 972\n \t\t},\n+\t\t.crop = {\n+\t\t\t.left = 0,\n+\t\t\t.top = 0,\n+\t\t\t.width = 2592,\n+\t\t\t.height = 1944,\n+\t\t},\n \t\tov5647_2x2binned_10bit,\n \t\tARRAY_SIZE(ov5647_2x2binned_10bit)\n \t},\n@@ -664,6 +680,12 @@ static struct ov5647_mode supported_mode\n \t\t\t.width = 640,\n \t\t\t.height = 480\n \t\t},\n+\t\t.crop = {\n+\t\t\t.left = 16,\n+\t\t\t.top = 0,\n+\t\t\t.width = 2560,\n+\t\t\t.height = 1920,\n+\t\t},\n \t\tov5647_640x480_10bit,\n \t\tARRAY_SIZE(ov5647_640x480_10bit)\n \t},\n@@ -971,6 +993,56 @@ static const struct v4l2_subdev_core_ops\n #endif\n };\n \n+static const struct v4l2_rect *\n+__ov5647_get_pad_crop(struct ov5647 *ov5647, struct v4l2_subdev_pad_config *cfg,\n+\t\t      unsigned int pad, enum v4l2_subdev_format_whence which)\n+{\n+\tswitch (which) {\n+\tcase V4L2_SUBDEV_FORMAT_TRY:\n+\t\treturn v4l2_subdev_get_try_crop(&ov5647->sd, cfg, pad);\n+\tcase V4L2_SUBDEV_FORMAT_ACTIVE:\n+\t\treturn &ov5647->mode->crop;\n+\t}\n+\n+\treturn NULL;\n+}\n+\n+static int ov5647_get_selection(struct v4l2_subdev *sd,\n+\t\t\t\tstruct v4l2_subdev_pad_config *cfg,\n+\t\t\t\tstruct v4l2_subdev_selection *sel)\n+{\n+\tswitch (sel->target) {\n+\tcase V4L2_SEL_TGT_CROP: {\n+\t\tstruct ov5647 *state = to_state(sd);\n+\n+\t\tmutex_lock(&state->lock);\n+\t\tsel->r = *__ov5647_get_pad_crop(state, cfg, sel->pad,\n+\t\t\t\t\t\tsel->which);\n+\t\tmutex_unlock(&state->lock);\n+\n+\t\treturn 0;\n+\t}\n+\n+\tcase V4L2_SEL_TGT_NATIVE_SIZE:\n+\t\tsel->r.top = 0;\n+\t\tsel->r.left = 0;\n+\t\tsel->r.width = OV5647_NATIVE_WIDTH;\n+\t\tsel->r.height = OV5647_NATIVE_HEIGHT;\n+\n+\t\treturn 0;\n+\n+\tcase V4L2_SEL_TGT_CROP_DEFAULT:\n+\t\tsel->r.top = OV5647_PIXEL_ARRAY_TOP;\n+\t\tsel->r.left = OV5647_PIXEL_ARRAY_LEFT;\n+\t\tsel->r.width = OV5647_PIXEL_ARRAY_WIDTH;\n+\t\tsel->r.height = OV5647_PIXEL_ARRAY_HEIGHT;\n+\n+\t\treturn 0;\n+\t}\n+\n+\treturn -EINVAL;\n+}\n+\n static int ov5647_s_stream(struct v4l2_subdev *sd, int enable)\n {\n \tstruct ov5647 *state = to_state(sd);\n@@ -1122,6 +1194,7 @@ static const struct v4l2_subdev_pad_ops\n \t.enum_mbus_code = ov5647_enum_mbus_code,\n \t.set_fmt =\t  ov5647_set_fmt,\n \t.get_fmt =\t  ov5647_get_fmt,\n+\t.get_selection =  ov5647_get_selection,\n \t.enum_frame_size = ov5647_enum_frame_size,\n };\n \n@@ -1170,10 +1243,10 @@ static int ov5647_open(struct v4l2_subde\n \t\t\t\tv4l2_subdev_get_try_crop(sd, fh->pad, 0);\n \tstruct ov5647 *state = to_state(sd);\n \n-\tcrop->left = OV5647_COLUMN_START_DEF;\n-\tcrop->top = OV5647_ROW_START_DEF;\n-\tcrop->width = OV5647_WINDOW_WIDTH_DEF;\n-\tcrop->height = OV5647_WINDOW_HEIGHT_DEF;\n+\tcrop->left = OV5647_PIXEL_ARRAY_LEFT;\n+\tcrop->top = OV5647_PIXEL_ARRAY_TOP;\n+\tcrop->width = OV5647_PIXEL_ARRAY_WIDTH;\n+\tcrop->height = OV5647_PIXEL_ARRAY_HEIGHT;\n \n \t/* Set the default format to the same as the sensor. */\n \t*format = state->mode->format;\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0231-media-i2c-ov5467-Fixup-error-path-to-release-mutex.patch",
    "content": "From 5c462e56efdb4de0e3b785082d8adae675ccaefd Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Wed, 29 Apr 2020 11:50:52 +0100\nSubject: [PATCH] media: i2c: ov5467: Fixup error path to release mutex\n\n\"87f3ab9 media: ov5647: Add basic support for multiple sensor modes.\"\nadded a return path ov5647_set_fmt that didn't release the device\nmutex that it had claimed.\nRelease the mutex.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n drivers/media/i2c/ov5647.c | 4 +++-\n 1 file changed, 3 insertions(+), 1 deletion(-)\n\n--- a/drivers/media/i2c/ov5647.c\n+++ b/drivers/media/i2c/ov5647.c\n@@ -1146,8 +1146,10 @@ static int ov5647_set_fmt(struct v4l2_su\n \telse\n \t\tmode = mode_8bit;\n \n-\tif (!mode)\n+\tif (!mode) {\n+\t\tmutex_unlock(&state->lock);\n \t\treturn -EINVAL;\n+\t}\n \n \t*fmt = mode->format;\n \tif (format->which == V4L2_SUBDEV_FORMAT_TRY) {\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0232-media-i2c-ov5647-Support-V4L2_CID_PIXEL_RATE.patch",
    "content": "From 5cb8892104a869adaf76d40629b5a0230d32edd0 Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Wed, 29 Apr 2020 12:25:13 +0100\nSubject: [PATCH] media: i2c: ov5647: Support V4L2_CID_PIXEL_RATE\n\nClients need to know the pixel rate in order to compute exposure\nand frame rate values.\nAdvertise it.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n drivers/media/i2c/ov5647.c | 31 +++++++++++++++++++++++++++----\n 1 file changed, 27 insertions(+), 4 deletions(-)\n\n--- a/drivers/media/i2c/ov5647.c\n+++ b/drivers/media/i2c/ov5647.c\n@@ -89,6 +89,8 @@ struct ov5647_mode {\n \t/* Analog crop rectangle. */\n \tstruct v4l2_rect crop;\n \n+\tu64 pixel_rate;\n+\n \tstruct regval_list\t\t*reg_list;\n \tunsigned int\t\t\tnum_regs;\n };\n@@ -103,6 +105,7 @@ struct ov5647 {\n \tstruct gpio_desc\t\t*pwdn;\n \tunsigned int\t\t\tflags;\n \tstruct v4l2_ctrl_handler\tctrls;\n+\tstruct v4l2_ctrl\t\t*pixel_rate;\n \tbool\t\t\t\twrite_mode_regs;\n };\n \n@@ -601,6 +604,7 @@ static struct ov5647_mode supported_mode\n \t\t\t.width = 1280,\n \t\t\t.height = 960,\n \t\t},\n+\t\t.pixel_rate = 77291670,\n \t\tov5647_640x480_8bit,\n \t\tARRAY_SIZE(ov5647_640x480_8bit)\n \t},\n@@ -624,6 +628,7 @@ static struct ov5647_mode supported_mode\n \t\t\t.width = 2592,\n \t\t\t.height = 1944\n \t\t},\n+\t\t.pixel_rate = 87500000,\n \t\tov5647_2592x1944_10bit,\n \t\tARRAY_SIZE(ov5647_2592x1944_10bit)\n \t},\n@@ -645,6 +650,7 @@ static struct ov5647_mode supported_mode\n \t\t\t.width = 1928,\n \t\t\t.height = 1080,\n \t\t},\n+\t\t.pixel_rate = 81666700,\n \t\tov5647_1080p30_10bit,\n \t\tARRAY_SIZE(ov5647_1080p30_10bit)\n \t},\n@@ -665,6 +671,7 @@ static struct ov5647_mode supported_mode\n \t\t\t.width = 2592,\n \t\t\t.height = 1944,\n \t\t},\n+\t\t.pixel_rate = 81666700,\n \t\tov5647_2x2binned_10bit,\n \t\tARRAY_SIZE(ov5647_2x2binned_10bit)\n \t},\n@@ -686,6 +693,7 @@ static struct ov5647_mode supported_mode\n \t\t\t.width = 2560,\n \t\t\t.height = 1920,\n \t\t},\n+\t\t.pixel_rate = 55000000,\n \t\tov5647_640x480_10bit,\n \t\tARRAY_SIZE(ov5647_640x480_10bit)\n \t},\n@@ -1163,6 +1171,11 @@ static int ov5647_set_fmt(struct v4l2_su\n \t\tif (state->mode != mode)\n \t\t\tstate->write_mode_regs = true;\n \t\tstate->mode = mode;\n+\n+\t\t__v4l2_ctrl_modify_range(state->pixel_rate,\n+\t\t\t\t\t mode->pixel_rate,\n+\t\t\t\t\t mode->pixel_rate, 1,\n+\t\t\t\t\t mode->pixel_rate);\n \t}\n \n \tmutex_unlock(&state->lock);\n@@ -1379,6 +1392,9 @@ static int ov5647_s_ctrl(struct v4l2_ctr\n \tcase V4L2_CID_EXPOSURE:\n \t\tret = ov5647_s_exposure(sd, ctrl->val);\n \t\tbreak;\n+\tcase V4L2_CID_PIXEL_RATE:\n+\t\t/* Read-only, but we adjust it based on mode. */\n+\t\tbreak;\n \tdefault:\n \t\tdev_info(&client->dev,\n \t\t\t \"ctrl(id:0x%x,val:0x%x) is not handled\\n\",\n@@ -1436,7 +1452,7 @@ static int ov5647_probe(struct i2c_clien\n \tmutex_init(&sensor->lock);\n \n \t/* Initialise controls. */\n-\tv4l2_ctrl_handler_init(&sensor->ctrls, 3);\n+\tv4l2_ctrl_handler_init(&sensor->ctrls, 6);\n \tv4l2_ctrl_new_std(&sensor->ctrls, &ov5647_ctrl_ops,\n \t\t\t  V4L2_CID_AUTOGAIN,\n \t\t\t  0,  /* min */\n@@ -1469,6 +1485,16 @@ static int ov5647_probe(struct i2c_clien\n \t\t\t\t 32);  /* default, 32 = 2.0x */\n \tctrl->flags |= V4L2_CTRL_FLAG_EXECUTE_ON_WRITE;\n \n+\t/* Set the default mode before we init the subdev */\n+\tsensor->mode = OV5647_DEFAULT_MODE;\n+\n+\t/* By default, PIXEL_RATE is read only, but it does change per mode */\n+\tsensor->pixel_rate = v4l2_ctrl_new_std(&sensor->ctrls, &ov5647_ctrl_ops,\n+\t\t\t\t\t       V4L2_CID_PIXEL_RATE,\n+\t\t\t\t\t       sensor->mode->pixel_rate,\n+\t\t\t\t\t       sensor->mode->pixel_rate, 1,\n+\t\t\t\t\t       sensor->mode->pixel_rate);\n+\n \tif (sensor->ctrls.error) {\n \t\tret = sensor->ctrls.error;\n \t\tdev_err(&client->dev, \"%s control init failed (%d)\\n\",\n@@ -1477,9 +1503,6 @@ static int ov5647_probe(struct i2c_clien\n \t}\n \tsensor->sd.ctrl_handler = &sensor->ctrls;\n \n-\t/* Set the default mode before we init the subdev */\n-\tsensor->mode = OV5647_DEFAULT_MODE;\n-\n \t/* Write out the register set over I2C on stream-on. */\n \tsensor->write_mode_regs = true;\n \n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0233-media-i2c-ov5647-Set-V4L2_SUBDEV_FL_HAS_EVENTS-flag.patch",
    "content": "From 29e3826878f43cd88414824be055cf5fcd57ab23 Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Wed, 29 Apr 2020 17:25:56 +0100\nSubject: [PATCH] media: i2c: ov5647: Set V4L2_SUBDEV_FL_HAS_EVENTS\n flag\n\nThe ov5647 subdev can generate control events, therefore set\nthe V4L2_SUBDEV_FL_HAS_EVENTS flag.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n drivers/media/i2c/ov5647.c | 29 +++++++++++++++++++++++++++--\n 1 file changed, 27 insertions(+), 2 deletions(-)\n\n--- a/drivers/media/i2c/ov5647.c\n+++ b/drivers/media/i2c/ov5647.c\n@@ -90,6 +90,8 @@ struct ov5647_mode {\n \tstruct v4l2_rect crop;\n \n \tu64 pixel_rate;\n+\t/* HTS as defined in the register set (0x380C/0x380D) */\n+\tint hts;\n \n \tstruct regval_list\t\t*reg_list;\n \tunsigned int\t\t\tnum_regs;\n@@ -106,6 +108,7 @@ struct ov5647 {\n \tunsigned int\t\t\tflags;\n \tstruct v4l2_ctrl_handler\tctrls;\n \tstruct v4l2_ctrl\t\t*pixel_rate;\n+\tstruct v4l2_ctrl\t\t*hblank;\n \tbool\t\t\t\twrite_mode_regs;\n };\n \n@@ -605,6 +608,7 @@ static struct ov5647_mode supported_mode\n \t\t\t.height = 960,\n \t\t},\n \t\t.pixel_rate = 77291670,\n+\t\t.hts = 1896,\n \t\tov5647_640x480_8bit,\n \t\tARRAY_SIZE(ov5647_640x480_8bit)\n \t},\n@@ -629,6 +633,7 @@ static struct ov5647_mode supported_mode\n \t\t\t.height = 1944\n \t\t},\n \t\t.pixel_rate = 87500000,\n+\t\t.hts = 2844,\n \t\tov5647_2592x1944_10bit,\n \t\tARRAY_SIZE(ov5647_2592x1944_10bit)\n \t},\n@@ -651,6 +656,7 @@ static struct ov5647_mode supported_mode\n \t\t\t.height = 1080,\n \t\t},\n \t\t.pixel_rate = 81666700,\n+\t\t.hts = 2416,\n \t\tov5647_1080p30_10bit,\n \t\tARRAY_SIZE(ov5647_1080p30_10bit)\n \t},\n@@ -672,6 +678,7 @@ static struct ov5647_mode supported_mode\n \t\t\t.height = 1944,\n \t\t},\n \t\t.pixel_rate = 81666700,\n+\t\t.hts = 1896,\n \t\tov5647_2x2binned_10bit,\n \t\tARRAY_SIZE(ov5647_2x2binned_10bit)\n \t},\n@@ -694,6 +701,7 @@ static struct ov5647_mode supported_mode\n \t\t\t.height = 1920,\n \t\t},\n \t\t.pixel_rate = 55000000,\n+\t\t.hts = 1852,\n \t\tov5647_640x480_10bit,\n \t\tARRAY_SIZE(ov5647_640x480_10bit)\n \t},\n@@ -1168,6 +1176,8 @@ static int ov5647_set_fmt(struct v4l2_su\n \t\t * If we have changed modes, write the I2C register list on\n \t\t * a stream_on().\n \t\t */\n+\t\tint hblank;\n+\n \t\tif (state->mode != mode)\n \t\t\tstate->write_mode_regs = true;\n \t\tstate->mode = mode;\n@@ -1176,6 +1186,9 @@ static int ov5647_set_fmt(struct v4l2_su\n \t\t\t\t\t mode->pixel_rate,\n \t\t\t\t\t mode->pixel_rate, 1,\n \t\t\t\t\t mode->pixel_rate);\n+\t\thblank = mode->hts - mode->format.width;\n+\t\t__v4l2_ctrl_modify_range(state->hblank, hblank, hblank, 1,\n+\t\t\t\t\t hblank);\n \t}\n \n \tmutex_unlock(&state->lock);\n@@ -1395,6 +1408,9 @@ static int ov5647_s_ctrl(struct v4l2_ctr\n \tcase V4L2_CID_PIXEL_RATE:\n \t\t/* Read-only, but we adjust it based on mode. */\n \t\tbreak;\n+\tcase V4L2_CID_HBLANK:\n+\t\t/* Read-only, but we adjust it based on mode. */\n+\t\tbreak;\n \tdefault:\n \t\tdev_info(&client->dev,\n \t\t\t \"ctrl(id:0x%x,val:0x%x) is not handled\\n\",\n@@ -1419,6 +1435,7 @@ static int ov5647_probe(struct i2c_clien\n \tstruct device_node *np = client->dev.of_node;\n \tu32 xclk_freq;\n \tstruct v4l2_ctrl *ctrl;\n+\tint hblank;\n \n \tsensor = devm_kzalloc(dev, sizeof(*sensor), GFP_KERNEL);\n \tif (!sensor)\n@@ -1452,7 +1469,7 @@ static int ov5647_probe(struct i2c_clien\n \tmutex_init(&sensor->lock);\n \n \t/* Initialise controls. */\n-\tv4l2_ctrl_handler_init(&sensor->ctrls, 6);\n+\tv4l2_ctrl_handler_init(&sensor->ctrls, 7);\n \tv4l2_ctrl_new_std(&sensor->ctrls, &ov5647_ctrl_ops,\n \t\t\t  V4L2_CID_AUTOGAIN,\n \t\t\t  0,  /* min */\n@@ -1495,6 +1512,13 @@ static int ov5647_probe(struct i2c_clien\n \t\t\t\t\t       sensor->mode->pixel_rate, 1,\n \t\t\t\t\t       sensor->mode->pixel_rate);\n \n+\t/* By default, HBLANK is read only, but it does change per mode */\n+\thblank = sensor->mode->hts - sensor->mode->format.width;\n+\tsensor->hblank = v4l2_ctrl_new_std(&sensor->ctrls, &ov5647_ctrl_ops,\n+\t\t\t\t\t   V4L2_CID_HBLANK, hblank, hblank, 1,\n+\t\t\t\t\t   hblank);\n+\tsensor->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;\n+\n \tif (sensor->ctrls.error) {\n \t\tret = sensor->ctrls.error;\n \t\tdev_err(&client->dev, \"%s control init failed (%d)\\n\",\n@@ -1509,7 +1533,8 @@ static int ov5647_probe(struct i2c_clien\n \tsd = &sensor->sd;\n \tv4l2_i2c_subdev_init(sd, client, &ov5647_subdev_ops);\n \tsensor->sd.internal_ops = &ov5647_subdev_internal_ops;\n-\tsensor->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;\n+\tsensor->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |\n+\t\t\t    V4L2_SUBDEV_FL_HAS_EVENTS;\n \n \tsensor->pad.flags = MEDIA_PAD_FL_SOURCE;\n \tsd->entity.function = MEDIA_ENT_F_CAM_SENSOR;\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0234-media-i2c-ov5647-Add-support-for-V4L2_CID_VBLANK.patch",
    "content": "From 95a10a4709eea202f3ce833fdeb9b30c17d80148 Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Wed, 29 Apr 2020 21:39:58 +0100\nSubject: [PATCH] media: i2c: ov5647: Add support for V4L2_CID_VBLANK\n\nAdds vblank control to allow for frame rate control.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n drivers/media/i2c/ov5647.c | 65 ++++++++++++++++++++++++++++++++------\n 1 file changed, 55 insertions(+), 10 deletions(-)\n\n--- a/drivers/media/i2c/ov5647.c\n+++ b/drivers/media/i2c/ov5647.c\n@@ -61,6 +61,8 @@\n #define OV5647_REG_AEC_AGC\t\t0x3503\n #define OV5647_REG_GAIN_HI\t\t0x350A\n #define OV5647_REG_GAIN_LO\t\t0x350B\n+#define OV5647_REG_VTS_HI\t\t0x380e\n+#define OV5647_REG_VTS_LO\t\t0x380f\n #define OV5647_REG_FRAME_OFF_NUMBER\t0x4202\n #define OV5647_REG_MIPI_CTRL00\t\t0x4800\n #define OV5647_REG_MIPI_CTRL14\t\t0x4814\n@@ -79,6 +81,9 @@\n #define OV5647_PIXEL_ARRAY_WIDTH\t2592U\n #define OV5647_PIXEL_ARRAY_HEIGHT\t1944U\n \n+#define OV5647_VBLANK_MIN\t\t4\n+#define OV5647_VTS_MAX\t\t\t32767\n+\n struct regval_list {\n \tu16 addr;\n \tu8 data;\n@@ -92,6 +97,8 @@ struct ov5647_mode {\n \tu64 pixel_rate;\n \t/* HTS as defined in the register set (0x380C/0x380D) */\n \tint hts;\n+\t/* Default VTS value for this mode */\n+\tint vts_def;\n \n \tstruct regval_list\t\t*reg_list;\n \tunsigned int\t\t\tnum_regs;\n@@ -109,6 +116,7 @@ struct ov5647 {\n \tstruct v4l2_ctrl_handler\tctrls;\n \tstruct v4l2_ctrl\t\t*pixel_rate;\n \tstruct v4l2_ctrl\t\t*hblank;\n+\tstruct v4l2_ctrl\t\t*vblank;\n \tbool\t\t\t\twrite_mode_regs;\n };\n \n@@ -161,8 +169,6 @@ static struct regval_list ov5647_640x480\n \t{0x3b07, 0x0c},\n \t{0x380c, 0x07},\n \t{0x380d, 0x68},\n-\t{0x380e, 0x03},\n-\t{0x380f, 0xd8},\n \t{0x3814, 0x31},\n \t{0x3815, 0x31},\n \t{0x3708, 0x64},\n@@ -251,8 +257,6 @@ static struct regval_list ov5647_2592x19\n \t{0x3b07, 0x0c},\n \t{0x380c, 0x0b},\n \t{0x380d, 0x1c},\n-\t{0x380e, 0x07},\n-\t{0x380f, 0xb0},\n \t{0x3814, 0x11},\n \t{0x3815, 0x11},\n \t{0x3708, 0x64},\n@@ -342,8 +346,6 @@ static struct regval_list ov5647_1080p30\n \t{0x3b07, 0x0c},\n \t{0x380c, 0x09},\n \t{0x380d, 0x70},\n-\t{0x380e, 0x04},\n-\t{0x380f, 0x50},\n \t{0x3814, 0x11},\n \t{0x3815, 0x11},\n \t{0x3708, 0x64},\n@@ -485,8 +487,6 @@ static struct regval_list ov5647_2x2binn\n \t{0x3503, 0x03},\n \t{0x3820, 0x41},\n \t{0x3821, 0x07},\n-\t{0x380E, 0x05},\n-\t{0x380F, 0x9B},\n \t{0x350A, 0x00},\n \t{0x350B, 0x10},\n \t{0x3500, 0x00},\n@@ -520,8 +520,6 @@ static struct regval_list ov5647_640x480\n \t{0x3b07, 0x0c},\n \t{0x380c, 0x07},\n \t{0x380d, 0x3c},\n-\t{0x380e, 0x01},\n-\t{0x380f, 0xf8},\n \t{0x3814, 0x35},\n \t{0x3815, 0x35},\n \t{0x3708, 0x64},\n@@ -609,6 +607,7 @@ static struct ov5647_mode supported_mode\n \t\t},\n \t\t.pixel_rate = 77291670,\n \t\t.hts = 1896,\n+\t\t.vts_def = 0x3d8,\n \t\tov5647_640x480_8bit,\n \t\tARRAY_SIZE(ov5647_640x480_8bit)\n \t},\n@@ -634,6 +633,7 @@ static struct ov5647_mode supported_mode\n \t\t},\n \t\t.pixel_rate = 87500000,\n \t\t.hts = 2844,\n+\t\t.vts_def = 0x7b0,\n \t\tov5647_2592x1944_10bit,\n \t\tARRAY_SIZE(ov5647_2592x1944_10bit)\n \t},\n@@ -657,6 +657,7 @@ static struct ov5647_mode supported_mode\n \t\t},\n \t\t.pixel_rate = 81666700,\n \t\t.hts = 2416,\n+\t\t.vts_def = 0x450,\n \t\tov5647_1080p30_10bit,\n \t\tARRAY_SIZE(ov5647_1080p30_10bit)\n \t},\n@@ -679,6 +680,7 @@ static struct ov5647_mode supported_mode\n \t\t},\n \t\t.pixel_rate = 81666700,\n \t\t.hts = 1896,\n+\t\t.vts_def = 0x59b,\n \t\tov5647_2x2binned_10bit,\n \t\tARRAY_SIZE(ov5647_2x2binned_10bit)\n \t},\n@@ -702,6 +704,7 @@ static struct ov5647_mode supported_mode\n \t\t},\n \t\t.pixel_rate = 55000000,\n \t\t.hts = 1852,\n+\t\t.vts_def = 0x1f8,\n \t\tov5647_640x480_10bit,\n \t\tARRAY_SIZE(ov5647_640x480_10bit)\n \t},\n@@ -710,6 +713,29 @@ static struct ov5647_mode supported_mode\n /* Use 2x2 binned 10-bit mode as default. */\n #define OV5647_DEFAULT_MODE (&supported_modes_10bit[2])\n \n+static int ov5647_write16(struct v4l2_subdev *sd, u16 reg, u16 val)\n+{\n+\tint ret;\n+\tunsigned char data[4] = { reg >> 8, reg & 0xff, val >> 8, val & 0xff};\n+\tstruct i2c_client *client = v4l2_get_subdevdata(sd);\n+\n+\tret = i2c_master_send(client, data, 4);\n+\t/*\n+\t * Writing the wrong number of bytes also needs to be flagged as an\n+\t * error. Success needs to produce a 0 return code.\n+\t */\n+\tif (ret == 4) {\n+\t\tret = 0;\n+\t} else {\n+\t\tdev_dbg(&client->dev, \"%s: i2c write error, reg: %x\\n\",\n+\t\t\t__func__, reg);\n+\t\tif (ret >= 0)\n+\t\t\tret = -EINVAL;\n+\t}\n+\n+\treturn ret;\n+}\n+\n static int ov5647_write(struct v4l2_subdev *sd, u16 reg, u8 val)\n {\n \tint ret;\n@@ -1189,6 +1215,14 @@ static int ov5647_set_fmt(struct v4l2_su\n \t\thblank = mode->hts - mode->format.width;\n \t\t__v4l2_ctrl_modify_range(state->hblank, hblank, hblank, 1,\n \t\t\t\t\t hblank);\n+\n+\t\t__v4l2_ctrl_modify_range(state->vblank,\n+\t\t\t\t\t OV5647_VBLANK_MIN,\n+\t\t\t\t\t OV5647_VTS_MAX - mode->format.height,\n+\t\t\t\t\t 1,\n+\t\t\t\t\t mode->vts_def - mode->format.height);\n+\t\t__v4l2_ctrl_s_ctrl(state->vblank,\n+\t\t\t\t   mode->vts_def - mode->format.height);\n \t}\n \n \tmutex_unlock(&state->lock);\n@@ -1411,6 +1445,10 @@ static int ov5647_s_ctrl(struct v4l2_ctr\n \tcase V4L2_CID_HBLANK:\n \t\t/* Read-only, but we adjust it based on mode. */\n \t\tbreak;\n+\tcase V4L2_CID_VBLANK:\n+\t\tret = ov5647_write16(sd, OV5647_REG_VTS_HI,\n+\t\t\t\t     state->mode->format.height + ctrl->val);\n+\t\tbreak;\n \tdefault:\n \t\tdev_info(&client->dev,\n \t\t\t \"ctrl(id:0x%x,val:0x%x) is not handled\\n\",\n@@ -1519,6 +1557,13 @@ static int ov5647_probe(struct i2c_clien\n \t\t\t\t\t   hblank);\n \tsensor->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;\n \n+\tsensor->vblank = v4l2_ctrl_new_std(&sensor->ctrls, &ov5647_ctrl_ops,\n+\t\t\t\t\t   V4L2_CID_VBLANK, OV5647_VBLANK_MIN,\n+\t\t\t\t\t   OV5647_VTS_MAX -\n+\t\t\t\t\t\tsensor->mode->format.height, 1,\n+\t\t\t\t\t   sensor->mode->vts_def -\n+\t\t\t\t\t\tsensor->mode->format.height);\n+\n \tif (sensor->ctrls.error) {\n \t\tret = sensor->ctrls.error;\n \t\tdev_err(&client->dev, \"%s control init failed (%d)\\n\",\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0235-media-i2c-ov5647-Neither-analogue-gain-nor-exposure-.patch",
    "content": "From 05a1c88d9b8dd344edfce3eaa00a3cac866cf3ad Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Wed, 29 Apr 2020 21:47:25 +0100\nSubject: [PATCH] media: i2c: ov5647: Neither analogue gain nor\n exposure need EXECUTE_ON_WRITE\n\nThe controls for analogue gain and exposure were defined with\nV4L2_CTRL_FLAG_EXECUTE_ON_WRITE. This is not required as we only need\nto send changes to the sensor.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n drivers/media/i2c/ov5647.c | 27 ++++++++++++---------------\n 1 file changed, 12 insertions(+), 15 deletions(-)\n\n--- a/drivers/media/i2c/ov5647.c\n+++ b/drivers/media/i2c/ov5647.c\n@@ -1472,7 +1472,6 @@ static int ov5647_probe(struct i2c_clien\n \tstruct v4l2_subdev *sd;\n \tstruct device_node *np = client->dev.of_node;\n \tu32 xclk_freq;\n-\tstruct v4l2_ctrl *ctrl;\n \tint hblank;\n \n \tsensor = devm_kzalloc(dev, sizeof(*sensor), GFP_KERNEL);\n@@ -1525,20 +1524,18 @@ static int ov5647_probe(struct i2c_clien\n \t\t\t       V4L2_EXPOSURE_MANUAL,  /* max */\n \t\t\t       0,                     /* skip_mask */\n \t\t\t       V4L2_EXPOSURE_MANUAL); /* default */\n-\tctrl = v4l2_ctrl_new_std(&sensor->ctrls, &ov5647_ctrl_ops,\n-\t\t\t\t V4L2_CID_EXPOSURE,\n-\t\t\t\t 4,     /* min lines */\n-\t\t\t\t 65535, /* max lines (4+8+4 bits)*/\n-\t\t\t\t 1,     /* step */\n-\t\t\t\t 1000); /* default number of lines */\n-\tctrl->flags |= V4L2_CTRL_FLAG_EXECUTE_ON_WRITE;\n-\tctrl = v4l2_ctrl_new_std(&sensor->ctrls, &ov5647_ctrl_ops,\n-\t\t\t\t V4L2_CID_ANALOGUE_GAIN,\n-\t\t\t\t 16,   /* min, 16 = 1.0x */\n-\t\t\t\t 1023, /* max (10 bits) */\n-\t\t\t\t 1,    /* step */\n-\t\t\t\t 32);  /* default, 32 = 2.0x */\n-\tctrl->flags |= V4L2_CTRL_FLAG_EXECUTE_ON_WRITE;\n+\tv4l2_ctrl_new_std(&sensor->ctrls, &ov5647_ctrl_ops,\n+\t\t\t  V4L2_CID_EXPOSURE,\n+\t\t\t  4,     /* min lines */\n+\t\t\t  65535, /* max lines (4+8+4 bits)*/\n+\t\t\t  1,     /* step */\n+\t\t\t  1000); /* default number of lines */\n+\tv4l2_ctrl_new_std(&sensor->ctrls, &ov5647_ctrl_ops,\n+\t\t\t  V4L2_CID_ANALOGUE_GAIN,\n+\t\t\t  16,   /* min, 16 = 1.0x */\n+\t\t\t  1023, /* max (10 bits) */\n+\t\t\t  1,    /* step */\n+\t\t\t  32);  /* default, 32 = 2.0x */\n \n \t/* Set the default mode before we init the subdev */\n \tsensor->mode = OV5647_DEFAULT_MODE;\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0236-media-i2c-ov5647-Use-member-names-in-mode-tables.patch",
    "content": "From 1073eef3ada930c9c35b2b0da30828cfe1ea4024 Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Wed, 29 Apr 2020 22:11:01 +0100\nSubject: [PATCH] media: i2c: ov5647: Use member names in mode tables\n\nTo make adding new members to the mode structures easier, use\nthe member names in the initialisers.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n drivers/media/i2c/ov5647.c | 30 +++++++++++++++---------------\n 1 file changed, 15 insertions(+), 15 deletions(-)\n\n--- a/drivers/media/i2c/ov5647.c\n+++ b/drivers/media/i2c/ov5647.c\n@@ -592,7 +592,7 @@ static struct ov5647_mode supported_mode\n \t * Uncentred crop (top left quarter) from 2x2 binned 1296x972 image.\n \t */\n \t{\n-\t\t{\n+\t\t.format = {\n \t\t\t.code = MEDIA_BUS_FMT_SBGGR8_1X8,\n \t\t\t.colorspace = V4L2_COLORSPACE_SRGB,\n \t\t\t.field = V4L2_FIELD_NONE,\n@@ -608,8 +608,8 @@ static struct ov5647_mode supported_mode\n \t\t.pixel_rate = 77291670,\n \t\t.hts = 1896,\n \t\t.vts_def = 0x3d8,\n-\t\tov5647_640x480_8bit,\n-\t\tARRAY_SIZE(ov5647_640x480_8bit)\n+\t\t.reg_list = ov5647_640x480_8bit,\n+\t\t.num_regs = ARRAY_SIZE(ov5647_640x480_8bit)\n \t},\n };\n \n@@ -618,7 +618,7 @@ static struct ov5647_mode supported_mode\n \t * MODE 0: 2592x1944 full resolution full FOV 10-bit mode.\n \t */\n \t{\n-\t\t{\n+\t\t.format = {\n \t\t\t.code = MEDIA_BUS_FMT_SBGGR10_1X10,\n \t\t\t.colorspace = V4L2_COLORSPACE_SRGB,\n \t\t\t.field = V4L2_FIELD_NONE,\n@@ -634,15 +634,15 @@ static struct ov5647_mode supported_mode\n \t\t.pixel_rate = 87500000,\n \t\t.hts = 2844,\n \t\t.vts_def = 0x7b0,\n-\t\tov5647_2592x1944_10bit,\n-\t\tARRAY_SIZE(ov5647_2592x1944_10bit)\n+\t\t.reg_list = ov5647_2592x1944_10bit,\n+\t\t.num_regs = ARRAY_SIZE(ov5647_2592x1944_10bit)\n \t},\n \t/*\n \t * MODE 1: 1080p30 10-bit mode.\n \t * Full resolution centre-cropped down to 1080p.\n \t */\n \t{\n-\t\t{\n+\t\t.format = {\n \t\t\t.code = MEDIA_BUS_FMT_SBGGR10_1X10,\n \t\t\t.colorspace = V4L2_COLORSPACE_SRGB,\n \t\t\t.field = V4L2_FIELD_NONE,\n@@ -658,14 +658,14 @@ static struct ov5647_mode supported_mode\n \t\t.pixel_rate = 81666700,\n \t\t.hts = 2416,\n \t\t.vts_def = 0x450,\n-\t\tov5647_1080p30_10bit,\n-\t\tARRAY_SIZE(ov5647_1080p30_10bit)\n+\t\t.reg_list = ov5647_1080p30_10bit,\n+\t\t.num_regs = ARRAY_SIZE(ov5647_1080p30_10bit)\n \t},\n \t/*\n \t * MODE 2: 2x2 binned full FOV 10-bit mode.\n \t */\n \t{\n-\t\t{\n+\t\t.format = {\n \t\t\t.code = MEDIA_BUS_FMT_SBGGR10_1X10,\n \t\t\t.colorspace = V4L2_COLORSPACE_SRGB,\n \t\t\t.field = V4L2_FIELD_NONE,\n@@ -681,15 +681,15 @@ static struct ov5647_mode supported_mode\n \t\t.pixel_rate = 81666700,\n \t\t.hts = 1896,\n \t\t.vts_def = 0x59b,\n-\t\tov5647_2x2binned_10bit,\n-\t\tARRAY_SIZE(ov5647_2x2binned_10bit)\n+\t\t.reg_list = ov5647_2x2binned_10bit,\n+\t\t.num_regs = ARRAY_SIZE(ov5647_2x2binned_10bit)\n \t},\n \t/*\n \t * MODE 3: 10-bit VGA full FOV mode 60fps.\n \t * 2x2 binned and subsampled down to VGA.\n \t */\n \t{\n-\t\t{\n+\t\t.format = {\n \t\t\t.code = MEDIA_BUS_FMT_SBGGR10_1X10,\n \t\t\t.colorspace = V4L2_COLORSPACE_SRGB,\n \t\t\t.field = V4L2_FIELD_NONE,\n@@ -705,8 +705,8 @@ static struct ov5647_mode supported_mode\n \t\t.pixel_rate = 55000000,\n \t\t.hts = 1852,\n \t\t.vts_def = 0x1f8,\n-\t\tov5647_640x480_10bit,\n-\t\tARRAY_SIZE(ov5647_640x480_10bit)\n+\t\t.reg_list = ov5647_640x480_10bit,\n+\t\t.num_regs = ARRAY_SIZE(ov5647_640x480_10bit)\n \t},\n };\n \n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0237-media-i2c-ov5647-Advertise-the-correct-exposure-rang.patch",
    "content": "From 7048b8678ac96eb512adfb18990eff0c9b8109f5 Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Thu, 30 Apr 2020 11:03:00 +0100\nSubject: [PATCH] media: i2c: ov5647: Advertise the correct exposure\n range\n\nExposure is clipped by the VTS of the mode, so needs to be updated as\nand when this is changed.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n drivers/media/i2c/ov5647.c | 47 +++++++++++++++++++++++++++++++-------\n 1 file changed, 39 insertions(+), 8 deletions(-)\n\n--- a/drivers/media/i2c/ov5647.c\n+++ b/drivers/media/i2c/ov5647.c\n@@ -84,6 +84,11 @@\n #define OV5647_VBLANK_MIN\t\t4\n #define OV5647_VTS_MAX\t\t\t32767\n \n+#define OV5647_EXPOSURE_MIN\t\t4\n+#define OV5647_EXPOSURE_STEP\t\t1\n+#define OV5647_EXPOSURE_DEFAULT\t\t1000\n+#define OV5647_EXPOSURE_MAX\t\t65535\n+\n struct regval_list {\n \tu16 addr;\n \tu8 data;\n@@ -117,6 +122,7 @@ struct ov5647 {\n \tstruct v4l2_ctrl\t\t*pixel_rate;\n \tstruct v4l2_ctrl\t\t*hblank;\n \tstruct v4l2_ctrl\t\t*vblank;\n+\tstruct v4l2_ctrl\t\t*exposure;\n \tbool\t\t\t\twrite_mode_regs;\n };\n \n@@ -1202,7 +1208,7 @@ static int ov5647_set_fmt(struct v4l2_su\n \t\t * If we have changed modes, write the I2C register list on\n \t\t * a stream_on().\n \t\t */\n-\t\tint hblank;\n+\t\tint exposure_max, exposure_def, hblank;\n \n \t\tif (state->mode != mode)\n \t\t\tstate->write_mode_regs = true;\n@@ -1223,6 +1229,15 @@ static int ov5647_set_fmt(struct v4l2_su\n \t\t\t\t\t mode->vts_def - mode->format.height);\n \t\t__v4l2_ctrl_s_ctrl(state->vblank,\n \t\t\t\t   mode->vts_def - mode->format.height);\n+\n+\t\texposure_max = mode->vts_def - 4;\n+\t\texposure_def = (exposure_max < OV5647_EXPOSURE_DEFAULT) ?\n+\t\t\t\t\texposure_max : OV5647_EXPOSURE_DEFAULT;\n+\t\t__v4l2_ctrl_modify_range(state->exposure,\n+\t\t\t\t\t state->exposure->minimum,\n+\t\t\t\t\t exposure_max,\n+\t\t\t\t\t state->exposure->step,\n+\t\t\t\t\t exposure_def);\n \t}\n \n \tmutex_unlock(&state->lock);\n@@ -1415,6 +1430,19 @@ static int ov5647_s_ctrl(struct v4l2_ctr\n \n \t/* v4l2_ctrl_lock() locks our own mutex */\n \n+\tif (ctrl->id == V4L2_CID_VBLANK) {\n+\t\tint exposure_max, exposure_def;\n+\n+\t\t/* Update max exposure while meeting expected vblanking */\n+\t\texposure_max = state->mode->format.height + ctrl->val - 4;\n+\t\texposure_def = (exposure_max < OV5647_EXPOSURE_DEFAULT) ?\n+\t\t\texposure_max : OV5647_EXPOSURE_DEFAULT;\n+\t\t__v4l2_ctrl_modify_range(state->exposure,\n+\t\t\t\t\t state->exposure->minimum,\n+\t\t\t\t\t exposure_max, state->exposure->step,\n+\t\t\t\t\t exposure_def);\n+\t}\n+\n \t/*\n \t * If the device is not powered up by the host driver do\n \t * not apply any controls to H/W at this time. Instead\n@@ -1472,7 +1500,7 @@ static int ov5647_probe(struct i2c_clien\n \tstruct v4l2_subdev *sd;\n \tstruct device_node *np = client->dev.of_node;\n \tu32 xclk_freq;\n-\tint hblank;\n+\tint hblank, exposure_max, exposure_def;\n \n \tsensor = devm_kzalloc(dev, sizeof(*sensor), GFP_KERNEL);\n \tif (!sensor)\n@@ -1525,12 +1553,6 @@ static int ov5647_probe(struct i2c_clien\n \t\t\t       0,                     /* skip_mask */\n \t\t\t       V4L2_EXPOSURE_MANUAL); /* default */\n \tv4l2_ctrl_new_std(&sensor->ctrls, &ov5647_ctrl_ops,\n-\t\t\t  V4L2_CID_EXPOSURE,\n-\t\t\t  4,     /* min lines */\n-\t\t\t  65535, /* max lines (4+8+4 bits)*/\n-\t\t\t  1,     /* step */\n-\t\t\t  1000); /* default number of lines */\n-\tv4l2_ctrl_new_std(&sensor->ctrls, &ov5647_ctrl_ops,\n \t\t\t  V4L2_CID_ANALOGUE_GAIN,\n \t\t\t  16,   /* min, 16 = 1.0x */\n \t\t\t  1023, /* max (10 bits) */\n@@ -1540,6 +1562,15 @@ static int ov5647_probe(struct i2c_clien\n \t/* Set the default mode before we init the subdev */\n \tsensor->mode = OV5647_DEFAULT_MODE;\n \n+\texposure_max = sensor->mode->vts_def - 4;\n+\texposure_def = (exposure_max < OV5647_EXPOSURE_DEFAULT) ?\n+\t\texposure_max : OV5647_EXPOSURE_DEFAULT;\n+\tsensor->exposure = v4l2_ctrl_new_std(&sensor->ctrls, &ov5647_ctrl_ops,\n+\t\t\t\t\t     V4L2_CID_EXPOSURE,\n+\t\t\t\t\t     OV5647_EXPOSURE_MIN, exposure_max,\n+\t\t\t\t\t     OV5647_EXPOSURE_STEP,\n+\t\t\t\t\t     exposure_def);\n+\n \t/* By default, PIXEL_RATE is read only, but it does change per mode */\n \tsensor->pixel_rate = v4l2_ctrl_new_std(&sensor->ctrls, &ov5647_ctrl_ops,\n \t\t\t\t\t       V4L2_CID_PIXEL_RATE,\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0238-media-bcm2835-unicam-Add-support-for-VIDIOC_-S-G-_SE.patch",
    "content": "From c4b4c783173ae54db7f9f656b25b45f7719f068d Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Wed, 29 Apr 2020 16:45:02 +0100\nSubject: [PATCH] media: bcm2835-unicam: Add support for\n VIDIOC_[S|G]_SELECTION\n\nSensors are now reflecting cropping and scaling parameters through\nthe selection API, therefore Unicam needs to forward the requests\nthrough to the subdev.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n .../media/platform/bcm2835/bcm2835-unicam.c   | 44 +++++++++++++++++++\n 1 file changed, 44 insertions(+)\n\n--- a/drivers/media/platform/bcm2835/bcm2835-unicam.c\n+++ b/drivers/media/platform/bcm2835/bcm2835-unicam.c\n@@ -1898,6 +1898,39 @@ static int unicam_g_edid(struct file *fi\n \treturn v4l2_subdev_call(dev->sensor, pad, get_edid, edid);\n }\n \n+static int unicam_s_selection(struct file *file, void *priv,\n+\t\t\t      struct v4l2_selection *sel)\n+{\n+\tstruct unicam_node *node = video_drvdata(file);\n+\tstruct unicam_device *dev = node->dev;\n+\tstruct v4l2_subdev_selection sdsel = {\n+\t\t.which = V4L2_SUBDEV_FORMAT_ACTIVE,\n+\t\t.target = sel->target,\n+\t\t.flags = sel->flags,\n+\t\t.r = sel->r,\n+\t};\n+\n+\treturn v4l2_subdev_call(dev->sensor, pad, set_selection, NULL, &sdsel);\n+}\n+\n+static int unicam_g_selection(struct file *file, void *priv,\n+\t\t\t      struct v4l2_selection *sel)\n+{\n+\tstruct unicam_node *node = video_drvdata(file);\n+\tstruct unicam_device *dev = node->dev;\n+\tstruct v4l2_subdev_selection sdsel = {\n+\t\t.which = V4L2_SUBDEV_FORMAT_ACTIVE,\n+\t\t.target = sel->target,\n+\t};\n+\tint ret;\n+\n+\tret = v4l2_subdev_call(dev->sensor, pad, get_selection, NULL, &sdsel);\n+\tif (!ret)\n+\t\tsel->r = sdsel.r;\n+\n+\treturn ret;\n+}\n+\n static int unicam_enum_framesizes(struct file *file, void *priv,\n \t\t\t\t  struct v4l2_frmsizeenum *fsize)\n {\n@@ -2218,6 +2251,9 @@ static const struct v4l2_ioctl_ops unica\n \t.vidioc_enum_framesizes\t\t= unicam_enum_framesizes,\n \t.vidioc_enum_frameintervals\t= unicam_enum_frameintervals,\n \n+\t.vidioc_g_selection\t\t= unicam_g_selection,\n+\t.vidioc_s_selection\t\t= unicam_s_selection,\n+\n \t.vidioc_g_parm\t\t\t= unicam_g_parm,\n \t.vidioc_s_parm\t\t\t= unicam_s_parm,\n \n@@ -2446,6 +2482,14 @@ static int register_node(struct unicam_d\n \t    !v4l2_subdev_has_op(unicam->sensor, pad, enum_frame_size))\n \t\tv4l2_disable_ioctl(&node->video_dev, VIDIOC_ENUM_FRAMESIZES);\n \n+\tif (node->pad_id == METADATA_PAD ||\n+\t    !v4l2_subdev_has_op(unicam->sensor, pad, set_selection))\n+\t\tv4l2_disable_ioctl(&node->video_dev, VIDIOC_S_SELECTION);\n+\n+\tif (node->pad_id == METADATA_PAD ||\n+\t    !v4l2_subdev_has_op(unicam->sensor, pad, get_selection))\n+\t\tv4l2_disable_ioctl(&node->video_dev, VIDIOC_G_SELECTION);\n+\n \tret = video_register_device(vdev, VFL_TYPE_VIDEO, -1);\n \tif (ret) {\n \t\tunicam_err(unicam, \"Unable to register video device.\\n\");\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0239-media-bcm2835-unicam-Do-not-stop-streaming-in-unicam.patch",
    "content": "From 533e6df1f7cc3aa022319f4419b3a38e7b76ce16 Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Wed, 29 Apr 2020 22:05:09 +0100\nSubject: [PATCH] media: bcm2835-unicam: Do not stop streaming in\n unicam_release\n\nunicam_release calls _vb2_fop_release, which will call stop_streaming\nif that particular node was streaming. Calling it unconditionally (as\nthe code was) means that if a second handle was opened eg to alter\na setting, on closing that connection it also stopped Unicam.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n drivers/media/platform/bcm2835/bcm2835-unicam.c | 3 ---\n 1 file changed, 3 deletions(-)\n\n--- a/drivers/media/platform/bcm2835/bcm2835-unicam.c\n+++ b/drivers/media/platform/bcm2835/bcm2835-unicam.c\n@@ -2204,9 +2204,6 @@ static int unicam_release(struct file *f\n \tif (fh_singular)\n \t\tv4l2_subdev_call(sd, core, s_power, 0);\n \n-\tif (node->streaming)\n-\t\tunicam_stop_streaming(&node->buffer_queue);\n-\n \tnode->open--;\n \tmutex_unlock(&node->lock);\n \n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0240-media-bcm2835-unicam-Fix-reference-counting-in-unica.patch",
    "content": "From 0d2110a5d2764c80179590e707929d0e6dda0c6d Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Thu, 30 Apr 2020 09:52:50 +0100\nSubject: [PATCH] media: bcm2835-unicam: Fix reference counting in\n unicam_open\n\nThe reference counting of node->open was only incremented after\na check that the node was v4l2_fh_is_singular_file, which resulted\nin the counting going wrong and s_power not being called at an\nappropriate time.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n drivers/media/platform/bcm2835/bcm2835-unicam.c | 4 +++-\n 1 file changed, 3 insertions(+), 1 deletion(-)\n\n--- a/drivers/media/platform/bcm2835/bcm2835-unicam.c\n+++ b/drivers/media/platform/bcm2835/bcm2835-unicam.c\n@@ -2170,16 +2170,18 @@ static int unicam_open(struct file *file\n \t\tgoto unlock;\n \t}\n \n+\tnode->open++;\n+\n \tif (!v4l2_fh_is_singular_file(file))\n \t\tgoto unlock;\n \n \tret = v4l2_subdev_call(dev->sensor, core, s_power, 1);\n \tif (ret < 0 && ret != -ENOIOCTLCMD) {\n \t\tv4l2_fh_release(file);\n+\t\tnode->open--;\n \t\tgoto unlock;\n \t}\n \n-\tnode->open++;\n \tret = 0;\n \n unlock:\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0241-media-i2c-tc358743-Fix-fallthrough-warning.patch",
    "content": "From 973e92cd9ff33dcf24492457e5bae6554f938e23 Mon Sep 17 00:00:00 2001\nFrom: Jacko Dirks <jdirks.linuxdev@gmail.com>\nDate: Tue, 5 May 2020 14:28:14 +0200\nSubject: [PATCH] media: i2c: tc358743: Fix fallthrough warning\n\nSigned-off-by: Jacko Dirks <jdirks.linuxdev@gmail.com>\n---\n drivers/media/i2c/tc358743.c | 1 +\n 1 file changed, 1 insertion(+)\n\n--- a/drivers/media/i2c/tc358743.c\n+++ b/drivers/media/i2c/tc358743.c\n@@ -2006,6 +2006,7 @@ static int tc358743_probe_of(struct tc35\n \tswitch (bps_pr_lane) {\n \tdefault:\n \t\tdev_warn(dev, \"untested bps per lane: %u bps\\n\", bps_pr_lane);\n+\t\t/* fall through */\n \tcase 594000000U:\n \t\tstate->pdata.lineinitcnt = 0xe80;\n \t\tstate->pdata.lptxtimecnt = 0x003;\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0242-media-bcm2835-unicam-Fix-uninitialized-warning.patch",
    "content": "From 3f024ccec9f9b661a5a7e37760fbc2558095a0a8 Mon Sep 17 00:00:00 2001\nFrom: Jacko Dirks <jdirks.linuxdev@gmail.com>\nDate: Tue, 5 May 2020 14:33:31 +0200\nSubject: [PATCH] media: bcm2835: unicam: Fix uninitialized warning\n\nSigned-off-by: Jacko Dirks <jdirks.linuxdev@gmail.com>\n---\n drivers/media/platform/bcm2835/bcm2835-unicam.c | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/drivers/media/platform/bcm2835/bcm2835-unicam.c\n+++ b/drivers/media/platform/bcm2835/bcm2835-unicam.c\n@@ -1001,7 +1001,7 @@ const struct unicam_fmt *get_first_suppo\n {\n \tstruct v4l2_subdev_mbus_code_enum mbus_code;\n \tconst struct unicam_fmt *fmt = NULL;\n-\tint ret;\n+\tint ret = 0;\n \tint j;\n \n \tfor (j = 0; ret != -EINVAL && ret != -ENOIOCTLCMD; ++j) {\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0243-video-bcm2708_fb-Disable-FB-if-no-displays-found.patch",
    "content": "From 927defe02be209d870171b385673c58b6dfa6964 Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.com>\nDate: Tue, 5 May 2020 19:45:41 +0100\nSubject: [PATCH] video: bcm2708_fb: Disable FB if no displays found\n\nIf the firmware hasn't detected a display, the driver would assume\none display was available, but because it had failed to retrieve the\ndisplay size it would try to allocate a zero-sized buffer.\n\nAvoid the allocation failure by bailing out early if no display is\nfound.\n\nSee: https://github.com/raspberrypi/linux/issues/3598\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.com>\n---\n drivers/video/fbdev/bcm2708_fb.c | 5 ++---\n 1 file changed, 2 insertions(+), 3 deletions(-)\n\n--- a/drivers/video/fbdev/bcm2708_fb.c\n+++ b/drivers/video/fbdev/bcm2708_fb.c\n@@ -1092,10 +1092,9 @@ static int bcm2708_fb_probe(struct platf\n \t * set one display\n \t */\n \tif (ret || num_displays == 0) {\n-\t\tnum_displays = 1;\n \t\tdev_err(&dev->dev,\n-\t\t\t\"Unable to determine number of FB's. Assuming 1\\n\");\n-\t\tret = 0;\n+\t\t\t\"Unable to determine number of FBs. Disabling driver.\\n\");\n+\t\treturn -ENOENT;\n \t} else {\n \t\tfbdev->firmware_supports_multifb = 1;\n \t}\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0244-dt-bindings-media-i2c-Add-IMX477-CMOS-sensor-binding.patch",
    "content": "From f312f497a22b3a69640d628277f5c56238860bc3 Mon Sep 17 00:00:00 2001\nFrom: Naushir Patuck <naush@raspberrypi.com>\nDate: Thu, 7 May 2020 15:50:54 +0100\nSubject: [PATCH] dt-bindings: media: i2c: Add IMX477 CMOS sensor\n binding\n\nAdd YAML device tree binding for IMX477 CMOS image sensor.\n\nSigned-off-by: Naushir Patuck <naush@raspberrypi.com>\n---\n .../devicetree/bindings/media/i2c/imx477.yaml | 113 ++++++++++++++++++\n 1 file changed, 113 insertions(+)\n create mode 100644 Documentation/devicetree/bindings/media/i2c/imx477.yaml\n\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/media/i2c/imx477.yaml\n@@ -0,0 +1,113 @@\n+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)\n+%YAML 1.2\n+---\n+$id: http://devicetree.org/schemas/media/i2c/imx477.yaml#\n+$schema: http://devicetree.org/meta-schemas/core.yaml#\n+\n+title: Sony 1/2.3-Inch 12Mpixel CMOS Digital Image Sensor\n+\n+maintainers:\n+  - Naushir Patuck <naush@raspberypi.com>\n+\n+description: |-\n+  The Sony IMX477 is a 1/2.3-inch CMOS active pixel digital image sensor\n+  with an active array size of 4056H x 3040V. It is programmable through\n+  I2C interface. The I2C address is fixed to 0x1A as per sensor data sheet.\n+  Image data is sent through MIPI CSI-2, which is configured as either 2 or\n+  4 data lanes.\n+\n+properties:\n+  compatible:\n+    const: sony,imx477\n+\n+  reg:\n+    description: I2C device address\n+    maxItems: 1\n+\n+  clocks:\n+    maxItems: 1\n+\n+  VDIG-supply:\n+    description:\n+      Digital I/O voltage supply, 1.05 volts\n+\n+  VANA-supply:\n+    description:\n+      Analog voltage supply, 2.8 volts\n+\n+  VDDL-supply:\n+    description:\n+      Digital core voltage supply, 1.8 volts\n+\n+  reset-gpios:\n+    description: |-\n+      Reference to the GPIO connected to the xclr pin, if any.\n+      Must be released (set high) after all all supplies and INCK are applied.\n+\n+  # See ../video-interfaces.txt for more details\n+  port:\n+    type: object\n+    properties:\n+      endpoint:\n+        type: object\n+        properties:\n+          data-lanes:\n+            description: |-\n+              The sensor supports either two-lane, or four-lane operation.\n+              For two-lane operation the property must be set to <1 2>.\n+            items:\n+              - const: 1\n+              - const: 2\n+\n+          clock-noncontinuous:\n+            type: boolean\n+            description: |-\n+              MIPI CSI-2 clock is non-continuous if this property is present,\n+              otherwise it's continuous.\n+\n+          link-frequencies:\n+            allOf:\n+              - $ref: /schemas/types.yaml#/definitions/uint64-array\n+            description:\n+              Allowed data bus frequencies.\n+\n+        required:\n+          - link-frequencies\n+\n+required:\n+  - compatible\n+  - reg\n+  - clocks\n+  - VANA-supply\n+  - VDIG-supply\n+  - VDDL-supply\n+  - port\n+\n+additionalProperties: false\n+\n+examples:\n+  - |\n+    i2c0 {\n+        #address-cells = <1>;\n+        #size-cells = <0>;\n+\n+        imx477: sensor@10 {\n+            compatible = \"sony,imx477\";\n+            reg = <0x1a>;\n+            clocks = <&imx477_clk>;\n+            VANA-supply = <&imx477_vana>;   /* 2.8v */\n+            VDIG-supply = <&imx477_vdig>;   /* 1.05v */\n+            VDDL-supply = <&imx477_vddl>;   /* 1.8v */\n+\n+            port {\n+                imx477_0: endpoint {\n+                    remote-endpoint = <&csi1_ep>;\n+                    data-lanes = <1 2>;\n+                    clock-noncontinuous;\n+                    link-frequencies = /bits/ 64 <450000000>;\n+                };\n+            };\n+        };\n+    };\n+\n+...\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0245-media-bcm2835-unicam-Always-service-interrupts.patch",
    "content": "From 320838e297c604a51ae37e6e55983c880ced9f42 Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Wed, 13 May 2020 18:28:27 +0100\nSubject: [PATCH] media: bcm2835-unicam: Always service interrupts\n\nFrom when bringing up the driver, there was a check in the isr\nto ignore interrupts (claiming them handled) should the driver\nnot be streaming.\n\nThe VPU now will not register a camera driver if it finds a\nCSI2 node enabled in device tree, therefore this flawed check is\nredundant.\n\nhttps://github.com/raspberrypi/linux/issues/3602\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n drivers/media/platform/bcm2835/bcm2835-unicam.c | 15 ---------------\n 1 file changed, 15 deletions(-)\n\n--- a/drivers/media/platform/bcm2835/bcm2835-unicam.c\n+++ b/drivers/media/platform/bcm2835/bcm2835-unicam.c\n@@ -766,12 +766,6 @@ static int unicam_all_nodes_streaming(st\n \treturn ret;\n }\n \n-static int unicam_all_nodes_disabled(struct unicam_device *dev)\n-{\n-\treturn !dev->node[IMAGE_PAD].streaming &&\n-\t       !dev->node[METADATA_PAD].streaming;\n-}\n-\n static void unicam_queue_event_sof(struct unicam_device *unicam)\n {\n \tstruct v4l2_event event = {\n@@ -801,15 +795,6 @@ static irqreturn_t unicam_isr(int irq, v\n \tu64 ts;\n \tint i;\n \n-\t/*\n-\t * Don't service interrupts if not streaming.\n-\t * Avoids issues if the VPU should enable the\n-\t * peripheral without the kernel knowing (that\n-\t * shouldn't happen, but causes issues if it does).\n-\t */\n-\tif (unicam_all_nodes_disabled(unicam))\n-\t\treturn IRQ_HANDLED;\n-\n \tsta = reg_read(cfg, UNICAM_STA);\n \t/* Write value back to clear the interrupts */\n \treg_write(cfg, UNICAM_STA, sta);\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0246-sc16is7xx-Fix-for-hardware-flow-control.patch",
    "content": "From 287fbc1b38d530aef3bc66420db7591808ff9969 Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.com>\nDate: Wed, 13 May 2020 20:10:15 +0100\nSubject: [PATCH] sc16is7xx: Fix for hardware flow control\n\nThe SC16IS7XX hardware flow control is mishandled by the driver in\na number of ways:\n\n  1. The set_baud method accidentally clears it when setting EFR bit.\n  2. Even though hardware flow control is enabled, it isn't indicated\n     back to the serial framework.\n  3. Applying the flow control clears the EFR bit.\n  4. The CTS support is not indicated in the return from\n     sc16is7xx_get_mctrl.\n\nAddress all of those issues using a mixture of patches found on the\nlinked pages.\n\nSee: https://github.com/raspberrypi/linux/issues/2542\nSee: https://www.spinics.net/lists/linux-serial/msg21794.html\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.com>\n---\n drivers/tty/serial/sc16is7xx.c | 14 ++++++++++----\n 1 file changed, 10 insertions(+), 4 deletions(-)\n\n--- a/drivers/tty/serial/sc16is7xx.c\n+++ b/drivers/tty/serial/sc16is7xx.c\n@@ -523,8 +523,9 @@ static int sc16is7xx_set_baud(struct uar\n \n \t/* Enable enhanced features */\n \tregcache_cache_bypass(s->regmap, true);\n-\tsc16is7xx_port_write(port, SC16IS7XX_EFR_REG,\n-\t\t\t     SC16IS7XX_EFR_ENABLE_BIT);\n+\tsc16is7xx_port_update(port, SC16IS7XX_EFR_REG,\n+\t\t\t      SC16IS7XX_EFR_ENABLE_BIT,\n+\t\t\t      SC16IS7XX_EFR_ENABLE_BIT);\n \tregcache_cache_bypass(s->regmap, false);\n \n \t/* Put LCR back to the normal mode */\n@@ -842,7 +843,7 @@ static unsigned int sc16is7xx_get_mctrl(\n \t/* DCD and DSR are not wired and CTS/RTS is handled automatically\n \t * so just indicate DSR and CAR asserted\n \t */\n-\treturn TIOCM_DSR | TIOCM_CAR;\n+\treturn TIOCM_DSR | TIOCM_CAR | TIOCM_RI | TIOCM_CTS;\n }\n \n static void sc16is7xx_set_mctrl(struct uart_port *port, unsigned int mctrl)\n@@ -929,14 +930,19 @@ static void sc16is7xx_set_termios(struct\n \tregcache_cache_bypass(s->regmap, true);\n \tsc16is7xx_port_write(port, SC16IS7XX_XON1_REG, termios->c_cc[VSTART]);\n \tsc16is7xx_port_write(port, SC16IS7XX_XOFF1_REG, termios->c_cc[VSTOP]);\n-\tif (termios->c_cflag & CRTSCTS)\n+\tif (termios->c_cflag & CRTSCTS) {\n \t\tflow |= SC16IS7XX_EFR_AUTOCTS_BIT |\n \t\t\tSC16IS7XX_EFR_AUTORTS_BIT;\n+\t\tport->status |= UPSTAT_AUTOCTS;\n+\t};\n \tif (termios->c_iflag & IXON)\n \t\tflow |= SC16IS7XX_EFR_SWFLOW3_BIT;\n \tif (termios->c_iflag & IXOFF)\n \t\tflow |= SC16IS7XX_EFR_SWFLOW1_BIT;\n \n+\t/* Always set enable enhanced */\n+\tflow |= SC16IS7XX_EFR_ENABLE_BIT;\n+\n \tsc16is7xx_port_write(port, SC16IS7XX_EFR_REG, flow);\n \tregcache_cache_bypass(s->regmap, false);\n \n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0247-staging-vc04_services-mmal-vchiq-Update-parameters-l.patch",
    "content": "From c50cbae8ecdd826ce9b710ce405ff8b459b0b781 Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Fri, 15 May 2020 13:42:10 +0100\nSubject: [PATCH] staging: vc04_services: mmal-vchiq: Update parameters\n list\n\nAdds in a couple of new MMAL parameter defines.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n drivers/staging/vc04_services/vchiq-mmal/mmal-parameters.h | 6 ++++++\n 1 file changed, 6 insertions(+)\n\n--- a/drivers/staging/vc04_services/vchiq-mmal/mmal-parameters.h\n+++ b/drivers/staging/vc04_services/vchiq-mmal/mmal-parameters.h\n@@ -612,6 +612,12 @@ enum mmal_parameter_video_type {\n \n \t/**< Takes a @ref MMAL_PARAMETER_UINT32_T */\n \tMMAL_PARAMETER_VIDEO_DROPPABLE_PFRAME_LENGTH,\n+\n+\t/**< Take a @ref MMAL_PARAMETER_VIDEO_STALL_T */\n+\tMMAL_PARAMETER_VIDEO_STALL_THRESHOLD,\n+\n+\t/**< Take a @ref MMAL_PARAMETER_BOOLEAN_T */\n+\tMMAL_PARAMETER_VIDEO_ENCODE_HEADERS_WITH_FRAME,\n };\n \n /** Valid mirror modes */\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0248-staging-vc04_services-bcm2835-camera-Request-headers.patch",
    "content": "From 1f0594a0dedb69f45c414fb05683921ef79b65b9 Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Fri, 15 May 2020 13:48:59 +0100\nSubject: [PATCH] staging:vc04_services: bcm2835-camera: Request\n headers with I-frame\n\nV4L2 wishes to have the codec header bytes in the same buffer as the\nfirst encoded frame, so it does become 1-in 1-out for encoding.\nThe firmware now has an option to do this, so enable it.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n .../staging/vc04_services/bcm2835-camera/bcm2835-camera.c   | 6 ++++++\n 1 file changed, 6 insertions(+)\n\n--- a/drivers/staging/vc04_services/bcm2835-camera/bcm2835-camera.c\n+++ b/drivers/staging/vc04_services/bcm2835-camera/bcm2835-camera.c\n@@ -1734,6 +1734,12 @@ static int mmal_init(struct bm2835_mmal_\n \t\t\t\t\t      MMAL_PARAMETER_MINIMISE_FRAGMENTATION,\n \t\t\t\t\t      &enable,\n \t\t\t\t\t      sizeof(enable));\n+\n+\t\t/* Enable inserting headers into the first frame */\n+\t\tvchiq_mmal_port_parameter_set(dev->instance,\n+\t\t\t\t\t      &dev->component[COMP_VIDEO_ENCODE]->control,\n+\t\t\t\t\t      MMAL_PARAMETER_VIDEO_ENCODE_HEADERS_WITH_FRAME,\n+\t\t\t\t\t      &enable, sizeof(enable));\n \t}\n \tret = bm2835_mmal_set_all_camera_controls(dev);\n \tif (ret < 0) {\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0250-media-bcm2835-unicam-Retain-packing-information-on-G.patch",
    "content": "From 9e8d2ff820bdc215ea0d06feb3fd95960cbeda6f Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Tue, 19 May 2020 11:46:47 +0100\nSubject: [PATCH] media: bcm2835-unicam: Retain packing information on\n G_FMT\n\nThe change to retrieve the pixel format always on g_fmt didn't\ncheck whether the native or unpacked version of the format\nhad been requested, and always returned the packed one.\nCorrect this so that the packing setting is retained whereever\npossible.\n\nFixes \"9d59e89 media: bcm2835-unicam: Re-fetch mbus code from subdev\non a g_fmt call\"\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n .../media/platform/bcm2835/bcm2835-unicam.c   | 19 +++++++++++++++++--\n 1 file changed, 17 insertions(+), 2 deletions(-)\n\n--- a/drivers/media/platform/bcm2835/bcm2835-unicam.c\n+++ b/drivers/media/platform/bcm2835/bcm2835-unicam.c\n@@ -974,8 +974,23 @@ static int unicam_g_fmt_vid_cap(struct f\n \tif (!fmt)\n \t\treturn -EINVAL;\n \n-\tnode->fmt = fmt;\n-\tnode->v_fmt.fmt.pix.pixelformat = fmt->fourcc;\n+\tif (node->fmt != fmt) {\n+\t\t/*\n+\t\t * The sensor format has changed so the pixelformat needs to\n+\t\t * be updated. Try and retain the packed/unpacked choice if\n+\t\t * at all possible.\n+\t\t */\n+\t\tif (node->fmt->repacked_fourcc ==\n+\t\t\t\t\t\tnode->v_fmt.fmt.pix.pixelformat)\n+\t\t\t/* Using the repacked format */\n+\t\t\tnode->v_fmt.fmt.pix.pixelformat = fmt->repacked_fourcc;\n+\t\telse\n+\t\t\t/* Using the native format */\n+\t\t\tnode->v_fmt.fmt.pix.pixelformat = fmt->fourcc;\n+\n+\t\tnode->fmt = fmt;\n+\t}\n+\n \t*f = node->v_fmt;\n \n \treturn 0;\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0251-zswap-Defer-zswap-initialisation.patch",
    "content": "From 164ec4ae01c28cd627d085c19f5e1c631b4cccff Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.com>\nDate: Tue, 5 May 2020 15:23:32 +0100\nSubject: [PATCH] zswap: Defer zswap initialisation\n\nEnabling zswap support in the kernel configuration costs about 1.5MB\nof RAM, even when zswap is not enabled at runtime. This cost can be\nreduced significantly by deferring initialisation (including pool\ncreation) until the \"enabled\" parameter is set to true. There is a\nsmall cost to this in that some initialisation code has to remain in\nmemory after the init phase, just in case they are needed later,\nbut the total size increase is negligible.\n\nSee: https://github.com/raspberrypi/linux/pull/3432\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.com>\n---\n mm/zswap.c | 53 +++++++++++++++++++++++++++++------------------------\n 1 file changed, 29 insertions(+), 24 deletions(-)\n\n--- a/mm/zswap.c\n+++ b/mm/zswap.c\n@@ -592,8 +592,9 @@ error:\n \treturn NULL;\n }\n \n-static __init struct zswap_pool *__zswap_pool_create_fallback(void)\n+static bool zswap_try_pool_create(void)\n {\n+\tstruct zswap_pool *pool;\n \tbool has_comp, has_zpool;\n \n \thas_comp = crypto_has_comp(zswap_compressor, 0, 0);\n@@ -629,9 +630,21 @@ static __init struct zswap_pool *__zswap\n \t}\n \n \tif (!has_comp || !has_zpool)\n-\t\treturn NULL;\n+\t\treturn false;\n+\n+\tpool = zswap_pool_create(zswap_zpool_type, zswap_compressor);\n \n-\treturn zswap_pool_create(zswap_zpool_type, zswap_compressor);\n+\tif (pool) {\n+\t\tpr_info(\"loaded using pool %s/%s\\n\", pool->tfm_name,\n+\t\t\tzpool_get_type(pool->zpool));\n+\t\tlist_add(&pool->list, &zswap_pools);\n+\t\tzswap_has_pool = true;\n+\t} else {\n+\t\tpr_err(\"pool creation failed\\n\");\n+\t\tzswap_enabled = false;\n+\t}\n+\n+\treturn zswap_enabled;\n }\n \n static void zswap_pool_destroy(struct zswap_pool *pool)\n@@ -804,16 +817,19 @@ static int zswap_zpool_param_set(const c\n static int zswap_enabled_param_set(const char *val,\n \t\t\t\t   const struct kernel_param *kp)\n {\n+\tint ret;\n+\n \tif (zswap_init_failed) {\n \t\tpr_err(\"can't enable, initialization failed\\n\");\n \t\treturn -ENODEV;\n \t}\n-\tif (!zswap_has_pool && zswap_init_started) {\n-\t\tpr_err(\"can't enable, no pool configured\\n\");\n-\t\treturn -ENODEV;\n-\t}\n \n-\treturn param_set_bool(val, kp);\n+\tret = param_set_bool(val, kp);\n+\tif (!ret && zswap_enabled && zswap_init_started && !zswap_has_pool)\n+\t\tif (!zswap_try_pool_create())\n+\t\t\tret = -ENODEV;\n+\n+\treturn ret;\n }\n \n /*********************************\n@@ -1314,7 +1330,6 @@ static void __exit zswap_debugfs_exit(vo\n **********************************/\n static int __init init_zswap(void)\n {\n-\tstruct zswap_pool *pool;\n \tint ret;\n \n \tzswap_init_started = true;\n@@ -1338,29 +1353,19 @@ static int __init init_zswap(void)\n \tif (ret)\n \t\tgoto hp_fail;\n \n-\tpool = __zswap_pool_create_fallback();\n-\tif (pool) {\n-\t\tpr_info(\"loaded using pool %s/%s\\n\", pool->tfm_name,\n-\t\t\tzpool_get_type(pool->zpool));\n-\t\tlist_add(&pool->list, &zswap_pools);\n-\t\tzswap_has_pool = true;\n-\t} else {\n-\t\tpr_err(\"pool creation failed\\n\");\n-\t\tzswap_enabled = false;\n-\t}\n-\n \tshrink_wq = create_workqueue(\"zswap-shrink\");\n \tif (!shrink_wq)\n-\t\tgoto fallback_fail;\n+\t\tgoto hp_fail;\n \n \tfrontswap_register_ops(&zswap_frontswap_ops);\n \tif (zswap_debugfs_init())\n \t\tpr_warn(\"debugfs initialization failed\\n\");\n+\n+\tif (zswap_enabled)\n+\t\tzswap_try_pool_create();\n+\n \treturn 0;\n \n-fallback_fail:\n-\tif (pool)\n-\t\tzswap_pool_destroy(pool);\n hp_fail:\n \tcpuhp_remove_state(CPUHP_MM_ZSWP_MEM_PREPARE);\n dstmem_fail:\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0252-SQUASH-pinctrl-bcm2835-Set-base-for-bcm2711-GPIO-to-.patch",
    "content": "From abc82e964df6c13999cff7b148b12efb255f19aa Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.com>\nDate: Fri, 22 May 2020 11:35:33 +0100\nSubject: [PATCH] SQUASH: pinctrl: bcm2835: Set base for bcm2711 GPIO\n to 0\n\nWithout this patch GPIOs don't seem to work properly, primarily\nnoticeable as broken LEDs.\n\nSquash with \"pinctrl-bcm2835: Set base to 0 give expected gpio numbering\"\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.com>\n---\n drivers/pinctrl/bcm/pinctrl-bcm2835.c | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/drivers/pinctrl/bcm/pinctrl-bcm2835.c\n+++ b/drivers/pinctrl/bcm/pinctrl-bcm2835.c\n@@ -378,7 +378,7 @@ static const struct gpio_chip bcm2711_gp\n \t.get = bcm2835_gpio_get,\n \t.set = bcm2835_gpio_set,\n \t.set_config = gpiochip_generic_config,\n-\t.base = -1,\n+\t.base = 0,\n \t.ngpio = BCM2711_NUM_GPIOS,\n \t.can_sleep = false,\n };\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0253-staging-vchiq_arm-Clean-up-40-bit-DMA-support.patch",
    "content": "From 461092c036303037c0efe37002079ce6e9ed8ba5 Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.com>\nDate: Wed, 20 May 2020 16:36:33 +0100\nSubject: [PATCH] staging: vchiq_arm: Clean up 40-bit DMA support\n\nManage the split between addresses for the VPU and addresses for the\n40-bit DMA controller with a dedicated DMA device pointer that on non-\nBCM2711 platforms is the same as the main VCHIQ device. This allows\nthe VCHIQ node to stay in the usual place in the DT, and removes the\nugly VC_SAFE macros.\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.com>\n\nstaging: vchiq_arm: Use g_dma_dev for dma_unmap_sg\n\nCommit \"staging: vchiq_arm: Clean up 40-bit DMA support\" failed to\nchange one of the calls to dma_unmap_sg to pass in g_dma_dev (rather\nthan g_dev). Correct that oversight.\n\nSee: https://github.com/raspberrypi/linux/issues/3647\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.com>\n---\n .../interface/vchiq_arm/vchiq_2835_arm.c      | 42 ++++++++++++-------\n .../interface/vchiq_arm/vchiq_arm.c           | 14 -------\n 2 files changed, 27 insertions(+), 29 deletions(-)\n\n--- a/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_2835_arm.c\n+++ b/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_2835_arm.c\n@@ -16,8 +16,6 @@\n #include <soc/bcm2835/raspberrypi-firmware.h>\n \n #define TOTAL_SLOTS (VCHIQ_SLOT_ZERO_SLOTS + 2 * 32)\n-#define VC_SAFE(x) (g_use_36bit_addrs ? ((u32)(x) | 0xc0000000) : (u32)(x))\n-#define IS_VC_SAFE(x) (g_use_36bit_addrs ? !((x) & ~0x3fffffffull) : 1)\n \n #include \"vchiq_arm.h\"\n #include \"vchiq_connected.h\"\n@@ -66,6 +64,7 @@ static char *g_fragments_base;\n static char *g_free_fragments;\n static struct semaphore g_free_fragments_sema;\n static struct device *g_dev;\n+static struct device *g_dma_dev;\n \n static DEFINE_SEMAPHORE(g_free_fragments_mutex);\n \n@@ -82,6 +81,7 @@ free_pagelist(struct vchiq_pagelist_info\n int vchiq_platform_init(struct platform_device *pdev, struct vchiq_state *state)\n {\n \tstruct device *dev = &pdev->dev;\n+\tstruct device *dma_dev = NULL;\n \tstruct vchiq_drvdata *drvdata = platform_get_drvdata(pdev);\n \tstruct rpi_firmware *fw = drvdata->fw;\n \tstruct vchiq_slot_zero *vchiq_slot_zero;\n@@ -103,7 +103,23 @@ int vchiq_platform_init(struct platform_\n \tg_cache_line_size = drvdata->cache_line_size;\n \tg_fragments_size = 2 * g_cache_line_size;\n \n-\tg_use_36bit_addrs = (dev->dma_pfn_offset == 0);\n+\tif (drvdata->use_36bit_addrs) {\n+\t\tstruct device_node *dma_node =\n+\t\t\tof_find_compatible_node(NULL, NULL, \"brcm,bcm2711-dma\");\n+\n+\t\tif (dma_node) {\n+\t\t\tstruct platform_device *pdev;\n+\n+\t\t\tpdev = of_find_device_by_node(dma_node);\n+\t\t\tif (pdev)\n+\t\t\t\tdma_dev = &pdev->dev;\n+\t\t\tof_node_put(dma_node);\n+\t\t\tg_use_36bit_addrs = true;\n+\t\t} else {\n+\t\t\tdev_err(dev, \"40-bit DMA controller not found\\n\");\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t}\n \n \t/* Allocate space for the channels in coherent memory */\n \tslot_mem_size = PAGE_ALIGN(TOTAL_SLOTS * VCHIQ_SLOT_SIZE);\n@@ -116,14 +132,8 @@ int vchiq_platform_init(struct platform_\n \t\treturn -ENOMEM;\n \t}\n \n-\tif (!IS_VC_SAFE(slot_phys)) {\n-\t\tdev_err(dev, \"allocated DMA memory %pad is not VC-safe\\n\",\n-\t\t\t&slot_phys);\n-\t\treturn -ENOMEM;\n-\t}\n-\n \tWARN_ON(((unsigned long)slot_mem & (PAGE_SIZE - 1)) != 0);\n-\tchannelbase = VC_SAFE(slot_phys);\n+\tchannelbase = slot_phys;\n \n \tvchiq_slot_zero = vchiq_init_slots(slot_mem, slot_mem_size);\n \tif (!vchiq_slot_zero)\n@@ -171,6 +181,8 @@ int vchiq_platform_init(struct platform_\n \t}\n \n \tg_dev = dev;\n+\tg_dma_dev = dma_dev ?: dev;\n+\n \tvchiq_log_info(vchiq_arm_log_level,\n \t\t\"vchiq_init - done (slots %pK, phys %pad)\",\n \t\tvchiq_slot_zero, &slot_phys);\n@@ -240,7 +252,7 @@ vchiq_prepare_bulk_data(struct vchiq_bul\n \tif (!pagelistinfo)\n \t\treturn VCHIQ_ERROR;\n \n-\tbulk->data = (void *)VC_SAFE(pagelistinfo->dma_addr);\n+\tbulk->data = pagelistinfo->dma_addr;\n \n \t/*\n \t * Store the pagelistinfo address in remote_data,\n@@ -295,7 +307,7 @@ static void\n cleanup_pagelistinfo(struct vchiq_pagelist_info *pagelistinfo)\n {\n \tif (pagelistinfo->scatterlist_mapped) {\n-\t\tdma_unmap_sg(g_dev, pagelistinfo->scatterlist,\n+\t\tdma_unmap_sg(g_dma_dev, pagelistinfo->scatterlist,\n \t\t\t     pagelistinfo->num_pages, pagelistinfo->dma_dir);\n \t}\n \n@@ -444,7 +456,7 @@ create_pagelist(char *buf, char __user *\n \t\tcount -= len;\n \t}\n \n-\tdma_buffers = dma_map_sg(g_dev,\n+\tdma_buffers = dma_map_sg(g_dma_dev,\n \t\t\t\t scatterlist,\n \t\t\t\t num_pages,\n \t\t\t\t pagelistinfo->dma_dir);\n@@ -494,7 +506,7 @@ create_pagelist(char *buf, char __user *\n \t} else {\n \t\tfor_each_sg(scatterlist, sg, dma_buffers, i) {\n \t\t\tu32 len = sg_dma_len(sg);\n-\t\t\tu32 addr = VC_SAFE(sg_dma_address(sg));\n+\t\t\tu32 addr = sg_dma_address(sg);\n \t\t\tu32 new_pages = (len + PAGE_SIZE - 1) >> PAGE_SHIFT;\n \n \t\t\t/* Note: addrs is the address + page_count - 1\n@@ -555,7 +567,7 @@ free_pagelist(struct vchiq_pagelist_info\n \t * NOTE: dma_unmap_sg must be called before the\n \t * cpu can touch any of the data/pages.\n \t */\n-\tdma_unmap_sg(g_dev, pagelistinfo->scatterlist,\n+\tdma_unmap_sg(g_dma_dev, pagelistinfo->scatterlist,\n \t\t     pagelistinfo->num_pages, pagelistinfo->dma_dir);\n \tpagelistinfo->scatterlist_mapped = 0;\n \n--- a/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_arm.c\n+++ b/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_arm.c\n@@ -2720,22 +2720,8 @@ vchiq_register_child(struct platform_dev\n \n \tchild->dev.of_node = np;\n \n-\t/*\n-\t * We want the dma-ranges etc to be copied from a device with the\n-\t * correct dma-ranges for the VPU.\n-\t * VCHIQ on Pi4 is now under scb which doesn't get those dma-ranges.\n-\t * Take the \"dma\" node as going to be suitable as it sees the world\n-\t * through the same eyes as the VPU.\n-\t */\n-\tnp = of_find_node_by_path(\"dma\");\n-\tif (!np)\n-\t\tnp = pdev->dev.of_node;\n-\n \tof_dma_configure(&child->dev, np, true);\n \n-\tif (np != pdev->dev.of_node)\n-\t\tof_node_put(np);\n-\n \treturn child;\n }\n \n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0254-media-bcm2835-unicam-change-minimum-number-of-vb2_qu.patch",
    "content": "From f858ff156427e99d5abeebc80c666caab33b3637 Mon Sep 17 00:00:00 2001\nFrom: David Plowman <david.plowman@raspberrypi.com>\nDate: Thu, 28 May 2020 11:09:48 +0100\nSubject: [PATCH] media: bcm2835-unicam: change minimum number of\n vb2_queue buffers to 1\n\nSince the unicam driver was modified to write to a dummy buffer when no\nuser-supplied buffer is available, it can now write to and return a\nbuffer even when there's only a single one. Enable this by changing the\nmin_buffers_needed in the vb2_queue; it will be useful for enabling\nstill captures without allocating more memory than absolutely necessary.\n\nSigned-off-by: David Plowman <david.plowman@raspberrypi.com>\n---\n drivers/media/platform/bcm2835/bcm2835-unicam.c | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/drivers/media/platform/bcm2835/bcm2835-unicam.c\n+++ b/drivers/media/platform/bcm2835/bcm2835-unicam.c\n@@ -2404,7 +2404,7 @@ static int register_node(struct unicam_d\n \tq->buf_struct_size = sizeof(struct unicam_buffer);\n \tq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;\n \tq->lock = &node->lock;\n-\tq->min_buffers_needed = 2;\n+\tq->min_buffers_needed = 1;\n \tq->dev = &unicam->pdev->dev;\n \n \tret = vb2_queue_init(q);\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0255-snd_bcm2835-disable-HDMI-audio-when-vc4-is-used-3640.patch",
    "content": "From d9d1244f8aa9d776073e2a12e0cb9542d89bd3cb Mon Sep 17 00:00:00 2001\nFrom: Hristo Venev <hristo@venev.name>\nDate: Fri, 5 Jun 2020 09:22:49 +0000\nSubject: [PATCH] snd_bcm2835: disable HDMI audio when vc4 is used\n (#3640)\n\nThings don't work too well when both the vc4 driver and the firmware\ndriver are trying to control the same audio output:\n\n[  763.569406] bcm2835_audio bcm2835_audio: vchi message timeout, msg=5\n\nHence, when the vc4 HDMI driver is used, let it control audio. This is done\nby introducing a new device tree property to the audio node, and\nextending the vc4-kms-v3d overlays to set it appropriately.\n\nSigned-off-by: Hristo Venev <hristo@venev.name>\n---\n drivers/staging/vc04_services/bcm2835-audio/bcm2835.c | 4 +++-\n 1 file changed, 3 insertions(+), 1 deletion(-)\n\n--- a/drivers/staging/vc04_services/bcm2835-audio/bcm2835.c\n+++ b/drivers/staging/vc04_services/bcm2835-audio/bcm2835.c\n@@ -381,7 +381,9 @@ static int snd_bcm2835_alsa_probe(struct\n \t}\n \n \tif (!enable_compat_alsa) {\n-\t\tset_hdmi_enables(dev);\n+\t\tif (!of_property_read_bool(dev->of_node, \"brcm,disable-hdmi\"))\n+\t\t\tset_hdmi_enables(dev);\n+\n \t\t// In this mode, always enable analog output\n \t\tenable_headphones = true;\n \t} else {\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0256-gpiolib-Don-t-prevent-IRQ-usage-of-output-GPIOs.patch",
    "content": "From 205dc5dbd2b1978f5c75daa0afabf0cf15c8e1fe Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.org>\nDate: Tue, 24 Apr 2018 14:42:27 +0100\nSubject: [PATCH] gpiolib: Don't prevent IRQ usage of output GPIOs\n\nUpstream Linux deems using output GPIOs to generate IRQs as a bogus\nuse case, even though the BCM2835 GPIO controller is capable of doing\nso. A number of users would like to make use of this facility, so\ndisable the checks.\n\nSee: https://github.com/raspberrypi/linux/issues/2527\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.org>\n---\n drivers/gpio/gpiolib.c | 10 ++++++----\n 1 file changed, 6 insertions(+), 4 deletions(-)\n\n--- a/drivers/gpio/gpiolib.c\n+++ b/drivers/gpio/gpiolib.c\n@@ -51,6 +51,8 @@\n #define\textra_checks\t0\n #endif\n \n+#define dont_test_bit(b,d) (0)\n+\n /* Device and char device-related information */\n static DEFINE_IDA(gpio_ida);\n static dev_t gpio_devt;\n@@ -2463,8 +2465,8 @@ int gpiod_direction_output(struct gpio_d\n \t\tvalue = !!value;\n \n \t/* GPIOs used for enabled IRQs shall not be set as output */\n-\tif (test_bit(FLAG_USED_AS_IRQ, &desc->flags) &&\n-\t    test_bit(FLAG_IRQ_IS_ENABLED, &desc->flags)) {\n+\tif (dont_test_bit(FLAG_USED_AS_IRQ, &desc->flags) &&\n+\t    dont_test_bit(FLAG_IRQ_IS_ENABLED, &desc->flags)) {\n \t\tgpiod_err(desc,\n \t\t\t  \"%s: tried to set a GPIO tied to an IRQ as output\\n\",\n \t\t\t  __func__);\n@@ -3279,8 +3281,8 @@ int gpiochip_lock_as_irq(struct gpio_chi\n \t}\n \n \t/* To be valid for IRQ the line needs to be input or open drain */\n-\tif (test_bit(FLAG_IS_OUT, &desc->flags) &&\n-\t    !test_bit(FLAG_OPEN_DRAIN, &desc->flags)) {\n+\tif (dont_test_bit(FLAG_IS_OUT, &desc->flags) &&\n+\t    !dont_test_bit(FLAG_OPEN_DRAIN, &desc->flags)) {\n \t\tchip_err(gc,\n \t\t\t \"%s: tried to flag a GPIO set as output for IRQ\\n\",\n \t\t\t __func__);\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0257-PCI-brcmstb-Add-DT-property-to-control-L1SS.patch",
    "content": "From 9bb199ebcdb864f9ec5df0e168df4a25820482ea Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.com>\nDate: Thu, 11 Jun 2020 09:57:03 +0100\nSubject: [PATCH] PCI: brcmstb: Add DT property to control L1SS\n\nThe BRCM PCIe block has controls to enable control of the CLKREQ#\nsignal by the L1SS, and to gate the refclk with the CLKREQ# input.\nThese controls are mutually exclusive - the upstream code sets the\nlatter, but some use cases require the former.\n\nAdd a Device Tree property - brcm,enable-l1ss - to switch to the\nL1SS configuration.\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.com>\n---\n drivers/pci/controller/pcie-brcmstb.c | 30 ++++++++++++++++++++-------\n 1 file changed, 23 insertions(+), 7 deletions(-)\n\n--- a/drivers/pci/controller/pcie-brcmstb.c\n+++ b/drivers/pci/controller/pcie-brcmstb.c\n@@ -114,8 +114,9 @@\n \t\tPCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI + ((win) * 8)\n \n #define PCIE_MISC_HARD_PCIE_HARD_DEBUG\t\t\t\t\t0x4204\n-#define  PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK\t0x2\n-#define  PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK\t\t0x08000000\n+#define  PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK\tBIT(1)\n+#define  PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_L1SS_ENABLE_MASK\t\tBIT(21)\n+#define  PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK\t\tBIT(27)\n \n \n #define PCIE_INTR2_CPU_BASE\t\t0x4300\n@@ -276,6 +277,7 @@ struct brcm_pcie {\n \tstruct clk\t\t*clk;\n \tstruct device_node\t*np;\n \tbool\t\t\tssc;\n+\tbool\t\t\tl1ss;\n \tint\t\t\tgen;\n \tu64\t\t\tmsi_target_addr;\n \tstruct brcm_msi\t\t*msi;\n@@ -1025,12 +1027,25 @@ static int brcm_pcie_setup(struct brcm_p\n \t\tPCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK);\n \twritel(tmp, base + PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1);\n \n-\t/*\n-\t * Refclk from RC should be gated with CLKREQ# input when ASPM L0s,L1\n-\t * is enabled => setting the CLKREQ_DEBUG_ENABLE field to 1.\n-\t */\n \ttmp = readl(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);\n-\ttmp |= PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK;\n+\tif (pcie->l1ss) {\n+\t\t/*\n+\t\t * Enable CLKREQ# signalling include L1 Substate control of\n+\t\t * the CLKREQ# signal and the external reference clock buffer.\n+\t\t * meet requirement for Endpoints that require CLKREQ#\n+\t\t * assertion to clock active within 400ns.\n+\t\t */\n+\t\ttmp &= ~PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK;\n+\t\ttmp |= PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_L1SS_ENABLE_MASK;\n+\t} else {\n+\t\t/*\n+\t\t * Refclk from RC should be gated with CLKREQ# input when\n+\t\t * ASPM L0s,L1 is enabled => setting the CLKREQ_DEBUG_ENABLE\n+\t\t * field to 1.\n+\t\t */\n+\t\ttmp &= ~PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_L1SS_ENABLE_MASK;\n+\t\ttmp |= PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK;\n+\t}\n \twritel(tmp, base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);\n \n \treturn 0;\n@@ -1251,6 +1266,7 @@ static int brcm_pcie_probe(struct platfo\n \tpcie->gen = (ret < 0) ? 0 : ret;\n \n \tpcie->ssc = of_property_read_bool(np, \"brcm,enable-ssc\");\n+\tpcie->l1ss = of_property_read_bool(np, \"brcm,enable-l1ss\");\n \n \tret = clk_prepare_enable(pcie->clk);\n \tif (ret) {\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0258-media-irs1125-Using-i2c_transfer-for-ic2-reads.patch",
    "content": "From 1123bcc35585a13cc25c6802f8d3968d185d7f9a Mon Sep 17 00:00:00 2001\nFrom: Markus Proeller <markus.proeller@pieye.org>\nDate: Tue, 16 Jun 2020 13:24:31 +0200\nSubject: [PATCH] media: irs1125: Using i2c_transfer for ic2 reads\n\nReading data over i2c is done by using i2c_transfer to ensure that this\noperation can't be interrupted.\n\nSigned-off-by: Markus Proeller <markus.proeller@pieye.org>\n---\n drivers/media/i2c/irs1125.c | 37 ++++++++++++++++++++++---------------\n 1 file changed, 22 insertions(+), 15 deletions(-)\n\n--- a/drivers/media/i2c/irs1125.c\n+++ b/drivers/media/i2c/irs1125.c\n@@ -248,27 +248,34 @@ static int irs1125_write(struct v4l2_sub\n \n static int irs1125_read(struct v4l2_subdev *sd, u16 reg, u16 *val)\n {\n-\tint ret;\n-\tunsigned char data_w[2] = { reg >> 8, reg & 0xff };\n-\tchar rdval[2];\n-\n \tstruct i2c_client *client = v4l2_get_subdevdata(sd);\n+\tstruct i2c_msg msgs[2];\n+\tu8 addr_buf[2] = { reg >> 8, reg & 0xff };\n+\tu8 data_buf[2] = { 0, };\n+\tint ret;\n \n-\tret = i2c_master_send(client, data_w, 2);\n-\tif (ret < 0) {\n-\t\tdev_dbg(&client->dev, \"%s: i2c write error, reg: %x\\n\",\n-\t\t\t__func__, reg);\n+\t/* Write register address */\n+\tmsgs[0].addr = client->addr;\n+\tmsgs[0].flags = 0;\n+\tmsgs[0].len = ARRAY_SIZE(addr_buf);\n+\tmsgs[0].buf = addr_buf;\n+\n+\t/* Read data from register */\n+\tmsgs[1].addr = client->addr;\n+\tmsgs[1].flags = I2C_M_RD;\n+\tmsgs[1].len = 2;\n+\tmsgs[1].buf = data_buf;\n+\n+\tret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));\n+\tif (ret != ARRAY_SIZE(msgs)) {\n+\t\tif (ret >= 0)\n+\t\t\tret = -EIO;\n \t\treturn ret;\n \t}\n \n-\tret = i2c_master_recv(client, rdval, 2);\n-\tif (ret < 0)\n-\t\tdev_err(&client->dev, \"%s: i2c read error, reg: %x\\n\",\n-\t\t\t__func__, reg);\n-\n-\t*val = rdval[1] | (rdval[0] << 8);\n+\t*val = data_buf[1] | (data_buf[0] << 8);\n \n-\treturn ret;\n+\treturn 0;\n }\n \n static int irs1125_write_array(struct v4l2_subdev *sd,\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0259-media-irs1125-Refactoring-and-debug-messages.patch",
    "content": "From 77ec8aff3939654e3c5fadff77252f0c0c4cb685 Mon Sep 17 00:00:00 2001\nFrom: Markus Proeller <markus.proeller@pieye.org>\nDate: Tue, 16 Jun 2020 13:27:42 +0200\nSubject: [PATCH] media: irs1125: Refactoring and debug messages\n\nChanged some variable names to comply with checkpatch --strict mode.\nDebug messages added.\n\nSigned-off-by: Markus Proeller <markus.proeller@pieye.org>\n---\n drivers/media/i2c/irs1125.c | 36 ++++++++++++++++++++----------------\n 1 file changed, 20 insertions(+), 16 deletions(-)\n\n--- a/drivers/media/i2c/irs1125.c\n+++ b/drivers/media/i2c/irs1125.c\n@@ -15,6 +15,7 @@\n #include \"irs1125.h\"\n #include <linux/clk.h>\n #include <linux/delay.h>\n+#include <linux/firmware.h>\n #include <linux/gpio/consumer.h>\n #include <linux/i2c.h>\n #include <linux/init.h>\n@@ -22,13 +23,13 @@\n #include <linux/module.h>\n #include <linux/of_graph.h>\n #include <linux/slab.h>\n+#include <linux/types.h>\n #include <linux/videodev2.h>\n-#include <linux/firmware.h>\n+#include <media/v4l2-ctrls.h>\n #include <media/v4l2-device.h>\n #include <media/v4l2-fwnode.h>\n #include <media/v4l2-image-sizes.h>\n #include <media/v4l2-mediabus.h>\n-#include <media/v4l2-ctrls.h>\n \n #define CHECK_BIT(val, pos) ((val) & BIT(pos))\n \n@@ -38,18 +39,19 @@\n \n #define IRS1125_ALTERNATE_FW \"irs1125_af.bin\"\n \n-#define IRS1125_REG_CSICFG       0xA882\n-#define IRS1125_REG_DESIGN_STEP\t 0xB0AD\n-#define IRS1125_REG_EFUSEVAL2\t 0xB09F\n-#define IRS1125_REG_EFUSEVAL3\t 0xB0A0\n-#define IRS1125_REG_EFUSEVAL4\t 0xB0A1\n-#define IRS1125_REG_DMEM_SHADOW\t 0xC320\n+#define IRS1125_REG_SAFE_RECONFIG\t0xA850\n+#define IRS1125_REG_CSICFG\t\t0xA882\n+#define IRS1125_REG_DESIGN_STEP\t\t0xB0AD\n+#define IRS1125_REG_EFUSEVAL2\t\t0xB09F\n+#define IRS1125_REG_EFUSEVAL3\t\t0xB0A0\n+#define IRS1125_REG_EFUSEVAL4\t\t0xB0A1\n+#define IRS1125_REG_DMEM_SHADOW\t\t0xC320\n \n-#define IRS1125_DESIGN_STEP_EXPECTED 0x0a12\n+#define IRS1125_DESIGN_STEP_EXPECTED\t0x0a12\n \n #define IRS1125_ROW_START_DEF\t\t0\n #define IRS1125_COLUMN_START_DEF\t0\n-#define IRS1125_WINDOW_HEIGHT_DEF\t 288\n+#define IRS1125_WINDOW_HEIGHT_DEF\t288\n #define IRS1125_WINDOW_WIDTH_DEF\t352\n \n struct regval_list {\n@@ -87,7 +89,7 @@ static inline struct irs1125 *to_state(s\n \treturn container_of(sd, struct irs1125, sd);\n }\n \n-static struct regval_list irs1125_26MHz[] = {\n+static struct regval_list irs1125_26mhz[] = {\n \t{0xB017, 0x0413},\n \t{0xB086, 0x3535},\n \t{0xB0AE, 0xEF02},\n@@ -153,7 +155,7 @@ static struct regval_list irs1125_26MHz[\n \t{0xFFFF, 100}\n };\n \n-static struct regval_list irs1125_seq_cfg[] = {\n+static struct regval_list irs1125_seq_cfg_init[] = {\n \t{0xC3A0, 0x823D},\n \t{0xC3A1, 0xB13B},\n \t{0xC3A2, 0x0313},\n@@ -243,6 +245,7 @@ static int irs1125_write(struct v4l2_sub\n \t\tdev_err(&client->dev, \"%s: i2c write error, reg: %x\\n\",\n \t\t\t__func__, reg);\n \n+\tdev_dbg(&client->dev, \"write addr 0x%04x, val 0x%04x\\n\", reg, val);\n \treturn ret;\n }\n \n@@ -364,8 +367,8 @@ static int __sensor_init(struct v4l2_sub\n \t\tcnt++;\n \t}\n \n-\tret = irs1125_write_array(sd, irs1125_26MHz,\n-\t\t\t\t  ARRAY_SIZE(irs1125_26MHz));\n+\tret = irs1125_write_array(sd, irs1125_26mhz,\n+\t\t\t\t  ARRAY_SIZE(irs1125_26mhz));\n \tif (ret < 0) {\n \t\tdev_err(&client->dev, \"write sensor default regs error\\n\");\n \t\treturn ret;\n@@ -415,8 +418,8 @@ static int __sensor_init(struct v4l2_sub\n \t}\n \trelease_firmware(fw);\n \n-\tret = irs1125_write_array(sd, irs1125_seq_cfg,\n-\t\t\t\t  ARRAY_SIZE(irs1125_seq_cfg));\n+\tret = irs1125_write_array(sd, irs1125_seq_cfg_init,\n+\t\t\t\t  ARRAY_SIZE(irs1125_seq_cfg_init));\n \tif (ret < 0) {\n \t\tdev_err(&client->dev, \"write default sequence failed\\n\");\n \t\treturn ret;\n@@ -1037,6 +1040,7 @@ static int irs1125_probe(struct i2c_clie\n \t}\n \n \tgpio_num = desc_to_gpio(sensor->reset);\n+\tdev_dbg(&client->dev, \"reset on GPIO num %d\\n\", gpio_num);\n \n \tmutex_init(&sensor->lock);\n \n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0260-media-irs1125-Atomic-access-to-imager-reconfiguratio.patch",
    "content": "From aa2af4f9994e6209e4b01d259ae67afb5c87e459 Mon Sep 17 00:00:00 2001\nFrom: Markus Proeller <markus.proeller@pieye.org>\nDate: Tue, 16 Jun 2020 13:31:36 +0200\nSubject: [PATCH] media: irs1125: Atomic access to imager\n reconfiguration\n\nInstead of changing the exposure and framerate settings for all sequences,\nthey can be changed for every sequence individually now. Therefore the\nIRS1125_CID_SAFE_RECONFIG ctrl has been removed and replaced by\nIRS1125_CID_SAFE_RECONFIG_S<seq_num>_EXPO and *_FRAME ctrls.\n\nThe consistency check in the sequence ctrl IRS1125_CID_SEQ_CONFIG\nis removed.\n\nSigned-off-by: Markus Proeller <markus.proeller@pieye.org>\n---\n drivers/media/i2c/irs1125.c | 224 ++++++++++++++++++++++++------------\n drivers/media/i2c/irs1125.h |  68 ++++++++---\n 2 files changed, 204 insertions(+), 88 deletions(-)\n\n--- a/drivers/media/i2c/irs1125.c\n+++ b/drivers/media/i2c/irs1125.c\n@@ -89,6 +89,52 @@ static inline struct irs1125 *to_state(s\n \treturn container_of(sd, struct irs1125, sd);\n }\n \n+static const char *expo_ctrl_names[IRS1125_NUM_SEQ_ENTRIES] = {\n+\t\"safe reconfiguration of exposure of sequence 0\",\n+\t\"safe reconfiguration of exposure of sequence 1\",\n+\t\"safe reconfiguration of exposure of sequence 2\",\n+\t\"safe reconfiguration of exposure of sequence 3\",\n+\t\"safe reconfiguration of exposure of sequence 4\",\n+\t\"safe reconfiguration of exposure of sequence 5\",\n+\t\"safe reconfiguration of exposure of sequence 6\",\n+\t\"safe reconfiguration of exposure of sequence 7\",\n+\t\"safe reconfiguration of exposure of sequence 8\",\n+\t\"safe reconfiguration of exposure of sequence 9\",\n+\t\"safe reconfiguration of exposure of sequence 10\",\n+\t\"safe reconfiguration of exposure of sequence 11\",\n+\t\"safe reconfiguration of exposure of sequence 12\",\n+\t\"safe reconfiguration of exposure of sequence 13\",\n+\t\"safe reconfiguration of exposure of sequence 14\",\n+\t\"safe reconfiguration of exposure of sequence 15\",\n+\t\"safe reconfiguration of exposure of sequence 16\",\n+\t\"safe reconfiguration of exposure of sequence 17\",\n+\t\"safe reconfiguration of exposure of sequence 18\",\n+\t\"safe reconfiguration of exposure of sequence 19\",\n+};\n+\n+static const char *frame_ctrl_names[IRS1125_NUM_SEQ_ENTRIES] = {\n+\t\"safe reconfiguration of framerate of sequence 0\",\n+\t\"safe reconfiguration of framerate of sequence 1\",\n+\t\"safe reconfiguration of framerate of sequence 2\",\n+\t\"safe reconfiguration of framerate of sequence 3\",\n+\t\"safe reconfiguration of framerate of sequence 4\",\n+\t\"safe reconfiguration of framerate of sequence 5\",\n+\t\"safe reconfiguration of framerate of sequence 6\",\n+\t\"safe reconfiguration of framerate of sequence 7\",\n+\t\"safe reconfiguration of framerate of sequence 8\",\n+\t\"safe reconfiguration of framerate of sequence 9\",\n+\t\"safe reconfiguration of framerate of sequence 10\",\n+\t\"safe reconfiguration of framerate of sequence 11\",\n+\t\"safe reconfiguration of framerate of sequence 12\",\n+\t\"safe reconfiguration of framerate of sequence 13\",\n+\t\"safe reconfiguration of framerate of sequence 14\",\n+\t\"safe reconfiguration of framerate of sequence 15\",\n+\t\"safe reconfiguration of framerate of sequence 16\",\n+\t\"safe reconfiguration of framerate of sequence 17\",\n+\t\"safe reconfiguration of framerate of sequence 18\",\n+\t\"safe reconfiguration of framerate of sequence 19\",\n+};\n+\n static struct regval_list irs1125_26mhz[] = {\n \t{0xB017, 0x0413},\n \t{0xB086, 0x3535},\n@@ -561,36 +607,57 @@ static int irs1125_s_ctrl(struct v4l2_ct\n \tstruct irs1125 *dev = container_of(ctrl->handler,\n \t\t\t\t\tstruct irs1125, ctrl_handler);\n \tstruct i2c_client *client = v4l2_get_subdevdata(&dev->sd);\n-\tint err, i;\n \tstruct irs1125_mod_pll *mod_cur, *mod_new;\n-\tstruct irs1125_seq_cfg *cfg_cur, *cfg_new;\n \tu16 addr, val;\n-\n-\terr = 0;\n+\tint err = 0, i;\n \n \tswitch (ctrl->id) {\n-\tcase IRS1125_CID_SAFE_RECONFIG:\n-\t{\n-\t\tstruct irs1125_illu *illu_cur, *illu_new;\n-\n-\t\tillu_new = (struct irs1125_illu *)ctrl->p_new.p;\n-\t\tillu_cur = (struct irs1125_illu *)ctrl->p_cur.p;\n-\t\tfor (i = 0; i < IRS1125_NUM_SEQ_ENTRIES; i++) {\n-\t\t\tif (illu_cur[i].exposure != illu_new[i].exposure) {\n-\t\t\t\taddr = 0xA850 + i * 2;\n-\t\t\t\tval = illu_new[i].exposure;\n-\t\t\t\terr = irs1125_write(&dev->sd, addr, val);\n-\t\t\t\tif (err < 0)\n-\t\t\t\t\tbreak;\n-\t\t\t}\n-\t\t\tif (illu_cur[i].framerate != illu_new[i].framerate) {\n-\t\t\t\taddr = 0xA851 + i * 2;\n-\t\t\t\tval = illu_new[i].framerate;\n-\t\t\t\terr = irs1125_write(&dev->sd, addr, val);\n-\t\t\t\tif (err < 0)\n-\t\t\t\t\tbreak;\n-\t\t\t}\n-\t\t}\n+\tcase IRS1125_CID_SAFE_RECONFIG_S0_EXPO:\n+\tcase IRS1125_CID_SAFE_RECONFIG_S0_FRAME:\n+\tcase IRS1125_CID_SAFE_RECONFIG_S1_EXPO:\n+\tcase IRS1125_CID_SAFE_RECONFIG_S1_FRAME:\n+\tcase IRS1125_CID_SAFE_RECONFIG_S2_EXPO:\n+\tcase IRS1125_CID_SAFE_RECONFIG_S2_FRAME:\n+\tcase IRS1125_CID_SAFE_RECONFIG_S3_EXPO:\n+\tcase IRS1125_CID_SAFE_RECONFIG_S3_FRAME:\n+\tcase IRS1125_CID_SAFE_RECONFIG_S4_EXPO:\n+\tcase IRS1125_CID_SAFE_RECONFIG_S4_FRAME:\n+\tcase IRS1125_CID_SAFE_RECONFIG_S5_EXPO:\n+\tcase IRS1125_CID_SAFE_RECONFIG_S5_FRAME:\n+\tcase IRS1125_CID_SAFE_RECONFIG_S6_EXPO:\n+\tcase IRS1125_CID_SAFE_RECONFIG_S6_FRAME:\n+\tcase IRS1125_CID_SAFE_RECONFIG_S7_EXPO:\n+\tcase IRS1125_CID_SAFE_RECONFIG_S7_FRAME:\n+\tcase IRS1125_CID_SAFE_RECONFIG_S8_EXPO:\n+\tcase IRS1125_CID_SAFE_RECONFIG_S8_FRAME:\n+\tcase IRS1125_CID_SAFE_RECONFIG_S9_EXPO:\n+\tcase IRS1125_CID_SAFE_RECONFIG_S9_FRAME:\n+\tcase IRS1125_CID_SAFE_RECONFIG_S10_EXPO:\n+\tcase IRS1125_CID_SAFE_RECONFIG_S10_FRAME:\n+\tcase IRS1125_CID_SAFE_RECONFIG_S11_EXPO:\n+\tcase IRS1125_CID_SAFE_RECONFIG_S11_FRAME:\n+\tcase IRS1125_CID_SAFE_RECONFIG_S12_EXPO:\n+\tcase IRS1125_CID_SAFE_RECONFIG_S12_FRAME:\n+\tcase IRS1125_CID_SAFE_RECONFIG_S13_EXPO:\n+\tcase IRS1125_CID_SAFE_RECONFIG_S13_FRAME:\n+\tcase IRS1125_CID_SAFE_RECONFIG_S14_EXPO:\n+\tcase IRS1125_CID_SAFE_RECONFIG_S14_FRAME:\n+\tcase IRS1125_CID_SAFE_RECONFIG_S15_EXPO:\n+\tcase IRS1125_CID_SAFE_RECONFIG_S15_FRAME:\n+\tcase IRS1125_CID_SAFE_RECONFIG_S16_EXPO:\n+\tcase IRS1125_CID_SAFE_RECONFIG_S16_FRAME:\n+\tcase IRS1125_CID_SAFE_RECONFIG_S17_EXPO:\n+\tcase IRS1125_CID_SAFE_RECONFIG_S17_FRAME:\n+\tcase IRS1125_CID_SAFE_RECONFIG_S18_EXPO:\n+\tcase IRS1125_CID_SAFE_RECONFIG_S18_FRAME:\n+\tcase IRS1125_CID_SAFE_RECONFIG_S19_EXPO:\n+\tcase IRS1125_CID_SAFE_RECONFIG_S19_FRAME: {\n+\t\tunsigned int offset = ctrl->id -\n+\t\t\tIRS1125_CID_SAFE_RECONFIG_S0_EXPO;\n+\n+\t\terr = irs1125_write(&dev->sd,\n+\t\t\t\t    IRS1125_REG_SAFE_RECONFIG + offset,\n+\t\t\t\t    ctrl->val);\n \t\tbreak;\n \t}\n \tcase IRS1125_CID_MOD_PLL:\n@@ -655,40 +722,40 @@ static int irs1125_s_ctrl(struct v4l2_ct\n \t\t\t}\n \t\t}\n \t\tbreak;\n-\tcase IRS1125_CID_SEQ_CONFIG:\n+\tcase IRS1125_CID_SEQ_CONFIG: {\n+\t\tstruct irs1125_seq_cfg *cfg_new;\n+\n \t\tcfg_new = (struct irs1125_seq_cfg *)ctrl->p_new.p;\n-\t\tcfg_cur = (struct irs1125_seq_cfg *)ctrl->p_cur.p;\n \t\tfor (i = 0; i < IRS1125_NUM_SEQ_ENTRIES; i++) {\n-\t\t\tif (cfg_cur[i].exposure != cfg_new[i].exposure)\t{\n-\t\t\t\taddr = IRS1125_REG_DMEM_SHADOW + i * 4;\n-\t\t\t\tval = cfg_new[i].exposure;\n-\t\t\t\terr = irs1125_write(&dev->sd, addr, val);\n-\t\t\t\tif (err < 0)\n-\t\t\t\t\tbreak;\n-\t\t\t}\n-\t\t\tif (cfg_cur[i].framerate != cfg_new[i].framerate) {\n-\t\t\t\taddr = IRS1125_REG_DMEM_SHADOW + 1 + i * 4;\n-\t\t\t\tval = cfg_new[i].framerate;\n-\t\t\t\terr = irs1125_write(&dev->sd, addr, val);\n-\t\t\t\tif (err < 0)\n-\t\t\t\t\tbreak;\n-\t\t\t}\n-\t\t\tif (cfg_cur[i].ps != cfg_new[i].ps) {\n-\t\t\t\taddr = IRS1125_REG_DMEM_SHADOW + 2 + i * 4;\n-\t\t\t\tval = cfg_new[i].ps;\n-\t\t\t\terr = irs1125_write(&dev->sd, addr, val);\n-\t\t\t\tif (err < 0)\n-\t\t\t\t\tbreak;\n-\t\t\t}\n-\t\t\tif (cfg_cur[i].pll != cfg_new[i].pll) {\n-\t\t\t\taddr = IRS1125_REG_DMEM_SHADOW + 3 + i * 4;\n-\t\t\t\tval = cfg_new[i].pll;\n-\t\t\t\terr = irs1125_write(&dev->sd, addr, val);\n-\t\t\t\tif (err < 0)\n-\t\t\t\t\tbreak;\n-\t\t\t}\n+\t\t\tunsigned int seq_offset = i * 4;\n+\t\t\tu16 addr, val;\n+\n+\t\t\taddr = IRS1125_REG_DMEM_SHADOW + seq_offset;\n+\t\t\tval = cfg_new[i].exposure;\n+\t\t\terr = irs1125_write(&dev->sd, addr, val);\n+\t\t\tif (err < 0)\n+\t\t\t\tbreak;\n+\n+\t\t\taddr = IRS1125_REG_DMEM_SHADOW + 1 + seq_offset;\n+\t\t\tval = cfg_new[i].framerate;\n+\t\t\terr = irs1125_write(&dev->sd, addr, val);\n+\t\t\tif (err < 0)\n+\t\t\t\tbreak;\n+\n+\t\t\taddr = IRS1125_REG_DMEM_SHADOW + 2 + seq_offset;\n+\t\t\tval = cfg_new[i].ps;\n+\t\t\terr = irs1125_write(&dev->sd, addr, val);\n+\t\t\tif (err < 0)\n+\t\t\t\tbreak;\n+\n+\t\t\taddr = IRS1125_REG_DMEM_SHADOW + 3 + seq_offset;\n+\t\t\tval = cfg_new[i].pll;\n+\t\t\terr = irs1125_write(&dev->sd, addr, val);\n+\t\t\tif (err < 0)\n+\t\t\t\tbreak;\n \t\t}\n \t\tbreak;\n+\t}\n \tcase IRS1125_CID_NUM_SEQS:\n \t\terr = irs1125_write(&dev->sd, 0xA88D, ctrl->val - 1);\n \t\tif (err >= 0)\n@@ -760,19 +827,6 @@ static const struct v4l2_ctrl_config irs\n \t\t\tIRS1125_NUM_MOD_PLLS}\n \t}, {\n \t\t.ops = &irs1125_ctrl_ops,\n-\t\t.id = IRS1125_CID_SAFE_RECONFIG,\n-\t\t.name = \"Change exposure and pause of single seq\",\n-\t\t.type = V4L2_CTRL_TYPE_U16,\n-\t\t.flags = V4L2_CTRL_FLAG_HAS_PAYLOAD,\n-\t\t.min = 0,\n-\t\t.max = U16_MAX,\n-\t\t.step = 1,\n-\t\t.def = 0,\n-\t\t.elem_size = sizeof(u16),\n-\t\t.dims = {sizeof(struct irs1125_illu) / sizeof(u16),\n-\t\t\tIRS1125_NUM_SEQ_ENTRIES}\n-\t}, {\n-\t\t.ops = &irs1125_ctrl_ops,\n \t\t.id = IRS1125_CID_SEQ_CONFIG,\n \t\t.name = \"Change sequence settings\",\n \t\t.type = V4L2_CTRL_TYPE_U16,\n@@ -900,9 +954,16 @@ static int irs1125_ctrls_init(struct irs\n {\n \tstruct v4l2_ctrl *ctrl;\n \tint err, i;\n-\tstruct v4l2_ctrl_handler *hdl;\n+\tstruct v4l2_ctrl_handler *hdl = &sensor->ctrl_handler;\n+\tstruct v4l2_ctrl_config ctrl_cfg = {\n+\t\t.ops = &irs1125_ctrl_ops,\n+\t\t.type = V4L2_CTRL_TYPE_INTEGER,\n+\t\t.min = 0,\n+\t\t.max = U16_MAX,\n+\t\t.step = 1,\n+\t\t.def = 0x1000\n+\t};\n \n-\thdl = &sensor->ctrl_handler;\n \tv4l2_ctrl_handler_init(hdl, ARRAY_SIZE(irs1125_custom_ctrls));\n \n \tfor (i = 0; i < ARRAY_SIZE(irs1125_custom_ctrls); i++)\t{\n@@ -923,6 +984,27 @@ static int irs1125_ctrls_init(struct irs\n \t\tgoto error_ctrls;\n \t}\n \n+\tfor (i = 0; i < IRS1125_NUM_SEQ_ENTRIES; i++) {\n+\t\tctrl_cfg.name = expo_ctrl_names[i];\n+\t\tctrl_cfg.id = IRS1125_CID_SAFE_RECONFIG_S0_EXPO + i * 2;\n+\t\tctrl = v4l2_ctrl_new_custom(hdl, &ctrl_cfg,\n+\t\t\t\t\t    NULL);\n+\t\tif (!ctrl)\n+\t\t\tdev_err(dev, \"Failed to init exposure control %s\\n\",\n+\t\t\t\tctrl_cfg.name);\n+\t}\n+\n+\tctrl_cfg.def = 0;\n+\tfor (i = 0; i < IRS1125_NUM_SEQ_ENTRIES; i++) {\n+\t\tctrl_cfg.name = frame_ctrl_names[i];\n+\t\tctrl_cfg.id = IRS1125_CID_SAFE_RECONFIG_S0_FRAME + i * 2;\n+\t\tctrl = v4l2_ctrl_new_custom(hdl, &ctrl_cfg,\n+\t\t\t\t\t    NULL);\n+\t\tif (!ctrl)\n+\t\t\tdev_err(dev, \"Failed to init framerate control %s\\n\",\n+\t\t\t\tctrl_cfg.name);\n+\t}\n+\n \tsensor->sd.ctrl_handler = hdl;\n \treturn 0;\n \n--- a/drivers/media/i2c/irs1125.h\n+++ b/drivers/media/i2c/irs1125.h\n@@ -21,18 +21,57 @@\n #define IRS1125_NUM_SEQ_ENTRIES 20\n #define IRS1125_NUM_MOD_PLLS 4\n \n-#define IRS1125_CID_CUSTOM_BASE        (V4L2_CID_USER_BASE | 0xf000)\n-#define IRS1125_CID_SAFE_RECONFIG      (IRS1125_CID_CUSTOM_BASE + 0)\n-#define IRS1125_CID_CONTINUOUS_TRIG    (IRS1125_CID_CUSTOM_BASE + 1)\n-#define IRS1125_CID_TRIGGER            (IRS1125_CID_CUSTOM_BASE + 2)\n-#define IRS1125_CID_RECONFIG           (IRS1125_CID_CUSTOM_BASE + 3)\n-#define IRS1125_CID_ILLU_ON            (IRS1125_CID_CUSTOM_BASE + 4)\n-#define IRS1125_CID_NUM_SEQS           (IRS1125_CID_CUSTOM_BASE + 5)\n-#define IRS1125_CID_MOD_PLL            (IRS1125_CID_CUSTOM_BASE + 6)\n-#define IRS1125_CID_SEQ_CONFIG         (IRS1125_CID_CUSTOM_BASE + 7)\n-#define IRS1125_CID_IDENT0             (IRS1125_CID_CUSTOM_BASE + 8)\n-#define IRS1125_CID_IDENT1             (IRS1125_CID_CUSTOM_BASE + 9)\n-#define IRS1125_CID_IDENT2             (IRS1125_CID_CUSTOM_BASE + 10)\n+#define IRS1125_CID_CUSTOM_BASE\t\t\t(V4L2_CID_USER_BASE | 0xf000)\n+#define IRS1125_CID_CONTINUOUS_TRIG\t\t(IRS1125_CID_CUSTOM_BASE + 1)\n+#define IRS1125_CID_TRIGGER\t\t\t(IRS1125_CID_CUSTOM_BASE + 2)\n+#define IRS1125_CID_RECONFIG\t\t\t(IRS1125_CID_CUSTOM_BASE + 3)\n+#define IRS1125_CID_ILLU_ON\t\t\t(IRS1125_CID_CUSTOM_BASE + 4)\n+#define IRS1125_CID_NUM_SEQS\t\t\t(IRS1125_CID_CUSTOM_BASE + 5)\n+#define IRS1125_CID_MOD_PLL\t\t\t(IRS1125_CID_CUSTOM_BASE + 6)\n+#define IRS1125_CID_SEQ_CONFIG\t\t\t(IRS1125_CID_CUSTOM_BASE + 7)\n+#define IRS1125_CID_IDENT0\t\t\t(IRS1125_CID_CUSTOM_BASE + 8)\n+#define IRS1125_CID_IDENT1\t\t\t(IRS1125_CID_CUSTOM_BASE + 9)\n+#define IRS1125_CID_IDENT2\t\t\t(IRS1125_CID_CUSTOM_BASE + 10)\n+#define IRS1125_CID_SAFE_RECONFIG_S0_EXPO\t(IRS1125_CID_CUSTOM_BASE + 11)\n+#define IRS1125_CID_SAFE_RECONFIG_S0_FRAME\t(IRS1125_CID_CUSTOM_BASE + 12)\n+#define IRS1125_CID_SAFE_RECONFIG_S1_EXPO\t(IRS1125_CID_CUSTOM_BASE + 13)\n+#define IRS1125_CID_SAFE_RECONFIG_S1_FRAME\t(IRS1125_CID_CUSTOM_BASE + 14)\n+#define IRS1125_CID_SAFE_RECONFIG_S2_EXPO\t(IRS1125_CID_CUSTOM_BASE + 15)\n+#define IRS1125_CID_SAFE_RECONFIG_S2_FRAME\t(IRS1125_CID_CUSTOM_BASE + 16)\n+#define IRS1125_CID_SAFE_RECONFIG_S3_EXPO\t(IRS1125_CID_CUSTOM_BASE + 17)\n+#define IRS1125_CID_SAFE_RECONFIG_S3_FRAME\t(IRS1125_CID_CUSTOM_BASE + 18)\n+#define IRS1125_CID_SAFE_RECONFIG_S4_EXPO\t(IRS1125_CID_CUSTOM_BASE + 19)\n+#define IRS1125_CID_SAFE_RECONFIG_S4_FRAME\t(IRS1125_CID_CUSTOM_BASE + 20)\n+#define IRS1125_CID_SAFE_RECONFIG_S5_EXPO\t(IRS1125_CID_CUSTOM_BASE + 21)\n+#define IRS1125_CID_SAFE_RECONFIG_S5_FRAME\t(IRS1125_CID_CUSTOM_BASE + 22)\n+#define IRS1125_CID_SAFE_RECONFIG_S6_EXPO\t(IRS1125_CID_CUSTOM_BASE + 23)\n+#define IRS1125_CID_SAFE_RECONFIG_S6_FRAME\t(IRS1125_CID_CUSTOM_BASE + 24)\n+#define IRS1125_CID_SAFE_RECONFIG_S7_EXPO\t(IRS1125_CID_CUSTOM_BASE + 25)\n+#define IRS1125_CID_SAFE_RECONFIG_S7_FRAME\t(IRS1125_CID_CUSTOM_BASE + 26)\n+#define IRS1125_CID_SAFE_RECONFIG_S8_EXPO\t(IRS1125_CID_CUSTOM_BASE + 27)\n+#define IRS1125_CID_SAFE_RECONFIG_S8_FRAME\t(IRS1125_CID_CUSTOM_BASE + 28)\n+#define IRS1125_CID_SAFE_RECONFIG_S9_EXPO\t(IRS1125_CID_CUSTOM_BASE + 29)\n+#define IRS1125_CID_SAFE_RECONFIG_S9_FRAME\t(IRS1125_CID_CUSTOM_BASE + 30)\n+#define IRS1125_CID_SAFE_RECONFIG_S10_EXPO\t(IRS1125_CID_CUSTOM_BASE + 31)\n+#define IRS1125_CID_SAFE_RECONFIG_S10_FRAME\t(IRS1125_CID_CUSTOM_BASE + 32)\n+#define IRS1125_CID_SAFE_RECONFIG_S11_EXPO\t(IRS1125_CID_CUSTOM_BASE + 33)\n+#define IRS1125_CID_SAFE_RECONFIG_S11_FRAME\t(IRS1125_CID_CUSTOM_BASE + 34)\n+#define IRS1125_CID_SAFE_RECONFIG_S12_EXPO\t(IRS1125_CID_CUSTOM_BASE + 35)\n+#define IRS1125_CID_SAFE_RECONFIG_S12_FRAME\t(IRS1125_CID_CUSTOM_BASE + 36)\n+#define IRS1125_CID_SAFE_RECONFIG_S13_EXPO\t(IRS1125_CID_CUSTOM_BASE + 37)\n+#define IRS1125_CID_SAFE_RECONFIG_S13_FRAME\t(IRS1125_CID_CUSTOM_BASE + 38)\n+#define IRS1125_CID_SAFE_RECONFIG_S14_EXPO\t(IRS1125_CID_CUSTOM_BASE + 39)\n+#define IRS1125_CID_SAFE_RECONFIG_S14_FRAME\t(IRS1125_CID_CUSTOM_BASE + 40)\n+#define IRS1125_CID_SAFE_RECONFIG_S15_EXPO\t(IRS1125_CID_CUSTOM_BASE + 41)\n+#define IRS1125_CID_SAFE_RECONFIG_S15_FRAME\t(IRS1125_CID_CUSTOM_BASE + 42)\n+#define IRS1125_CID_SAFE_RECONFIG_S16_EXPO\t(IRS1125_CID_CUSTOM_BASE + 43)\n+#define IRS1125_CID_SAFE_RECONFIG_S16_FRAME\t(IRS1125_CID_CUSTOM_BASE + 44)\n+#define IRS1125_CID_SAFE_RECONFIG_S17_EXPO\t(IRS1125_CID_CUSTOM_BASE + 45)\n+#define IRS1125_CID_SAFE_RECONFIG_S17_FRAME\t(IRS1125_CID_CUSTOM_BASE + 46)\n+#define IRS1125_CID_SAFE_RECONFIG_S18_EXPO\t(IRS1125_CID_CUSTOM_BASE + 47)\n+#define IRS1125_CID_SAFE_RECONFIG_S18_FRAME\t(IRS1125_CID_CUSTOM_BASE + 48)\n+#define IRS1125_CID_SAFE_RECONFIG_S19_EXPO\t(IRS1125_CID_CUSTOM_BASE + 49)\n+#define IRS1125_CID_SAFE_RECONFIG_S19_FRAME\t(IRS1125_CID_CUSTOM_BASE + 50)\n \n struct irs1125_seq_cfg {\n \t__u16 exposure;\n@@ -41,11 +80,6 @@ struct irs1125_seq_cfg {\n \t__u16 pll;\n };\n \n-struct irs1125_illu {\n-\t__u16 exposure;\n-\t__u16 framerate;\n-};\n-\n struct irs1125_mod_pll {\n \t__u16 pllcfg1;\n \t__u16 pllcfg2;\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0261-media-irs1125-Keep-HW-in-sync-after-imager-reset.patch",
    "content": "From 60794484c063805631e50b5a4fbc81538d51944e Mon Sep 17 00:00:00 2001\nFrom: Markus Proeller <markus.proeller@pieye.org>\nDate: Tue, 16 Jun 2020 13:33:56 +0200\nSubject: [PATCH] media: irs1125: Keep HW in sync after imager reset\n\nWhen closing the video device, the irs1125 is put in power down state.\nTo keep V4L2 ctrls and the HW in sync, v4l2_ctrl_handler_setup is\ncalled after power up.\n\nThe compound ctrl IRS1125_CID_MOD_PLL however has a default value\nof all zeros, which puts the imager into a non responding state.\nThus, this ctrl is not written by the driver into HW after power up.\nThe userspace has to take care to write senseful data.\n\nSigned-off-by: Markus Proeller <markus.proeller@pieye.org>\n---\n drivers/media/i2c/irs1125.c | 121 +++++++++++++++++-------------------\n 1 file changed, 58 insertions(+), 63 deletions(-)\n\n--- a/drivers/media/i2c/irs1125.c\n+++ b/drivers/media/i2c/irs1125.c\n@@ -82,6 +82,7 @@ struct irs1125 {\n \tstruct v4l2_ctrl *ctrl_numseq;\n \n \tint power_count;\n+\tbool mod_pll_init;\n };\n \n static inline struct irs1125 *to_state(struct v4l2_subdev *sd)\n@@ -276,8 +277,7 @@ static struct regval_list irs1125_seq_cf\n \t{0xC039, 0x0000},\n \t{0xC401, 0x0002},\n \n-\t{0xFFFF, 1},\n-\t{0xA87C, 0x0001}\n+\t{0xFFFF, 1}\n };\n \n static int irs1125_write(struct v4l2_subdev *sd, u16 reg, u16 val)\n@@ -471,7 +471,11 @@ static int __sensor_init(struct v4l2_sub\n \t\treturn ret;\n \t}\n \n-\treturn 0;\n+\tirs1125->mod_pll_init = true;\n+\tv4l2_ctrl_handler_setup(&irs1125->ctrl_handler);\n+\tirs1125->mod_pll_init = false;\n+\n+\treturn irs1125_write(sd, 0xA87C, 0x0001);\n }\n \n static int irs1125_sensor_power(struct v4l2_subdev *sd, int on)\n@@ -607,8 +611,6 @@ static int irs1125_s_ctrl(struct v4l2_ct\n \tstruct irs1125 *dev = container_of(ctrl->handler,\n \t\t\t\t\tstruct irs1125, ctrl_handler);\n \tstruct i2c_client *client = v4l2_get_subdevdata(&dev->sd);\n-\tstruct irs1125_mod_pll *mod_cur, *mod_new;\n-\tu16 addr, val;\n \tint err = 0, i;\n \n \tswitch (ctrl->id) {\n@@ -660,68 +662,61 @@ static int irs1125_s_ctrl(struct v4l2_ct\n \t\t\t\t    ctrl->val);\n \t\tbreak;\n \t}\n-\tcase IRS1125_CID_MOD_PLL:\n+\tcase IRS1125_CID_MOD_PLL: {\n+\t\tstruct irs1125_mod_pll *mod_new;\n+\n+\t\tif (dev->mod_pll_init)\n+\t\t\tbreak;\n+\n \t\tmod_new = (struct irs1125_mod_pll *)ctrl->p_new.p;\n-\t\tmod_cur = (struct irs1125_mod_pll *)ctrl->p_cur.p;\n \t\tfor (i = 0; i < IRS1125_NUM_MOD_PLLS; i++) {\n-\t\t\tif (mod_cur[i].pllcfg1 != mod_new[i].pllcfg1) {\n-\t\t\t\taddr = 0xC3A0 + i * 3;\n-\t\t\t\tval = mod_new[i].pllcfg1;\n-\t\t\t\terr = irs1125_write(&dev->sd, addr, val);\n-\t\t\t\tif (err < 0)\n-\t\t\t\t\tbreak;\n-\t\t\t}\n-\t\t\tif (mod_cur[i].pllcfg2 != mod_new[i].pllcfg2) {\n-\t\t\t\taddr = 0xC3A1 + i * 3;\n-\t\t\t\tval = mod_new[i].pllcfg2;\n-\t\t\t\terr = irs1125_write(&dev->sd, addr, val);\n-\t\t\t\tif (err < 0)\n-\t\t\t\t\tbreak;\n-\t\t\t}\n-\t\t\tif (mod_cur[i].pllcfg3 != mod_new[i].pllcfg3) {\n-\t\t\t\taddr = 0xC3A2 + i * 3;\n-\t\t\t\tval = mod_new[i].pllcfg3;\n-\t\t\t\terr = irs1125_write(&dev->sd, addr, val);\n-\t\t\t\tif (err < 0)\n-\t\t\t\t\tbreak;\n-\t\t\t}\n-\t\t\tif (mod_cur[i].pllcfg4 != mod_new[i].pllcfg4) {\n-\t\t\t\taddr = 0xC24C + i * 5;\n-\t\t\t\tval = mod_new[i].pllcfg4;\n-\t\t\t\terr = irs1125_write(&dev->sd, addr, val);\n-\t\t\t\tif (err < 0)\n-\t\t\t\t\tbreak;\n-\t\t\t}\n-\t\t\tif (mod_cur[i].pllcfg5 != mod_new[i].pllcfg5) {\n-\t\t\t\taddr = 0xC24D + i * 5;\n-\t\t\t\tval = mod_new[i].pllcfg5;\n-\t\t\t\terr = irs1125_write(&dev->sd, addr, val);\n-\t\t\t\tif (err < 0)\n-\t\t\t\t\tbreak;\n-\t\t\t}\n-\t\t\tif (mod_cur[i].pllcfg6 != mod_new[i].pllcfg6) {\n-\t\t\t\taddr = 0xC24E + i * 5;\n-\t\t\t\tval = mod_new[i].pllcfg6;\n-\t\t\t\terr = irs1125_write(&dev->sd, addr, val);\n-\t\t\t\tif (err < 0)\n-\t\t\t\t\tbreak;\n-\t\t\t}\n-\t\t\tif (mod_cur[i].pllcfg7 != mod_new[i].pllcfg7) {\n-\t\t\t\taddr = 0xC24F + i * 5;\n-\t\t\t\tval = mod_new[i].pllcfg7;\n-\t\t\t\terr = irs1125_write(&dev->sd, addr, val);\n-\t\t\t\tif (err < 0)\n-\t\t\t\t\tbreak;\n-\t\t\t}\n-\t\t\tif (mod_cur[i].pllcfg8 != mod_new[i].pllcfg8) {\n-\t\t\t\taddr = 0xC250 + i * 5;\n-\t\t\t\tval = mod_new[i].pllcfg8;\n-\t\t\t\terr = irs1125_write(&dev->sd, addr, val);\n-\t\t\t\tif (err < 0)\n-\t\t\t\t\tbreak;\n-\t\t\t}\n+\t\t\tunsigned int pll_offset, ssc_offset;\n+\n+\t\t\tpll_offset = i * 3;\n+\t\t\tssc_offset = i * 5;\n+\n+\t\t\terr = irs1125_write(&dev->sd, 0xC3A0 + pll_offset,\n+\t\t\t\t\t    mod_new[i].pllcfg1);\n+\t\t\tif (err < 0)\n+\t\t\t\tbreak;\n+\n+\t\t\terr = irs1125_write(&dev->sd, 0xC3A1 + pll_offset,\n+\t\t\t\t\t    mod_new[i].pllcfg2);\n+\t\t\tif (err < 0)\n+\t\t\t\tbreak;\n+\n+\t\t\terr = irs1125_write(&dev->sd, 0xC3A2 + pll_offset,\n+\t\t\t\t\t    mod_new[i].pllcfg3);\n+\t\t\tif (err < 0)\n+\t\t\t\tbreak;\n+\n+\t\t\terr = irs1125_write(&dev->sd, 0xC24C + ssc_offset,\n+\t\t\t\t\t    mod_new[i].pllcfg4);\n+\t\t\tif (err < 0)\n+\t\t\t\tbreak;\n+\n+\t\t\terr = irs1125_write(&dev->sd, 0xC24D + ssc_offset,\n+\t\t\t\t\t    mod_new[i].pllcfg5);\n+\t\t\tif (err < 0)\n+\t\t\t\tbreak;\n+\n+\t\t\terr = irs1125_write(&dev->sd, 0xC24E + ssc_offset,\n+\t\t\t\t\t    mod_new[i].pllcfg6);\n+\t\t\tif (err < 0)\n+\t\t\t\tbreak;\n+\n+\t\t\terr = irs1125_write(&dev->sd, 0xC24F + ssc_offset,\n+\t\t\t\t\t    mod_new[i].pllcfg7);\n+\t\t\tif (err < 0)\n+\t\t\t\tbreak;\n+\n+\t\t\terr = irs1125_write(&dev->sd, 0xC250 + ssc_offset,\n+\t\t\t\t\t    mod_new[i].pllcfg8);\n+\t\t\tif (err < 0)\n+\t\t\t\tbreak;\n \t\t}\n \t\tbreak;\n+\t}\n \tcase IRS1125_CID_SEQ_CONFIG: {\n \t\tstruct irs1125_seq_cfg *cfg_new;\n \n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0262-staging-bcm2835-audio-Add-missing-MODULE_ALIAS.patch",
    "content": "From 0465c9ffbf41667c8553d18ace95d2be2f2f4b00 Mon Sep 17 00:00:00 2001\nFrom: Maxim Mikityanskiy <maxtram95@gmail.com>\nDate: Sat, 20 Jun 2020 15:40:00 +0300\nSubject: [PATCH] staging: bcm2835-audio: Add missing MODULE_ALIAS\n\nCommit 8353fe6f1e0f (\"Revert \"staging: bcm2835-audio: Drop DT\ndependency\"\") reverts the upstream change and makes bcm2835-audio use\ndevice tree again, however, it also removes the MODULE_ALIAS for the\nplatform device. This MODULE_ALIAS is needed, because VCHIQ registers\nbcm2835-audio as a child platform device since commit 25c7597af20d\n(\"staging: vchiq_arm: Register a platform device for audio\"), and this\nmechanism is adopted also in the downstream kernel.\n\nThis commit puts back that MODULE_ALIAS to make bcm2835-audio\nautoprobing work again. The rest of VCHIQ children have their\nMODULE_ALIASes in place.\n\nFixes: 8353fe6f1e0f (\"Revert \"staging: bcm2835-audio: Drop DT dependency\"\")\nSigned-off-by: Maxim Mikityanskiy <maxtram95@gmail.com>\n---\n drivers/staging/vc04_services/bcm2835-audio/bcm2835.c | 1 +\n 1 file changed, 1 insertion(+)\n\n--- a/drivers/staging/vc04_services/bcm2835-audio/bcm2835.c\n+++ b/drivers/staging/vc04_services/bcm2835-audio/bcm2835.c\n@@ -438,3 +438,4 @@ module_platform_driver(bcm2835_alsa_driv\n MODULE_AUTHOR(\"Dom Cobley\");\n MODULE_DESCRIPTION(\"Alsa driver for BCM2835 chip\");\n MODULE_LICENSE(\"GPL\");\n+MODULE_ALIAS(\"platform:bcm2835_audio\");\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0263-drivers-media-Remove-the-downstream-version-of-bcm28.patch",
    "content": "From e1690f8e0f8ac07021dd5e6b53bf6df2c9cf0ae2 Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Tue, 23 Jun 2020 10:05:57 +0100\nSubject: [PATCH] drivers: media: Remove the downstream version of\n bcm2835-unicam\n\nAbout to be replaced by the upstream version.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n drivers/media/platform/bcm2835/Kconfig        |   14 -\n drivers/media/platform/bcm2835/Makefile       |    3 -\n .../media/platform/bcm2835/bcm2835-unicam.c   | 2873 -----------------\n .../media/platform/bcm2835/vc4-regs-unicam.h  |  253 --\n 4 files changed, 3143 deletions(-)\n delete mode 100644 drivers/media/platform/bcm2835/Kconfig\n delete mode 100644 drivers/media/platform/bcm2835/Makefile\n delete mode 100644 drivers/media/platform/bcm2835/bcm2835-unicam.c\n delete mode 100644 drivers/media/platform/bcm2835/vc4-regs-unicam.h\n\n--- a/drivers/media/platform/bcm2835/Kconfig\n+++ /dev/null\n@@ -1,14 +0,0 @@\n-# Broadcom VideoCore4 V4L2 camera support\n-\n-config VIDEO_BCM2835_UNICAM\n-\ttristate \"Broadcom BCM2835 Unicam video capture driver\"\n-\tdepends on VIDEO_V4L2 && VIDEO_V4L2_SUBDEV_API && MEDIA_CONTROLLER\n-\tdepends on ARCH_BCM2835 || COMPILE_TEST\n-\tselect VIDEOBUF2_DMA_CONTIG\n-\tselect V4L2_FWNODE\n-\thelp\n-\t  Say Y here to enable V4L2 subdevice for CSI2 receiver.\n-\t  This is a V4L2 subdevice that interfaces directly to the VC4 peripheral.\n-\n-\t   To compile this driver as a module, choose M here. The module\n-\t   will be called bcm2835-unicam.\n--- a/drivers/media/platform/bcm2835/Makefile\n+++ /dev/null\n@@ -1,3 +0,0 @@\n-# Makefile for BCM2835 Unicam driver\n-\n-obj-$(CONFIG_VIDEO_BCM2835_UNICAM) += bcm2835-unicam.o\n--- a/drivers/media/platform/bcm2835/bcm2835-unicam.c\n+++ /dev/null\n@@ -1,2873 +0,0 @@\n-// SPDX-License-Identifier: GPL-2.0-only\n-/*\n- * BCM2835 Unicam Capture Driver\n- *\n- * Copyright (C) 2017-2020 - Raspberry Pi (Trading) Ltd.\n- *\n- * Dave Stevenson <dave.stevenson@raspberrypi.com>\n- *\n- * Based on TI am437x driver by\n- *   Benoit Parrot <bparrot@ti.com>\n- *   Lad, Prabhakar <prabhakar.csengg@gmail.com>\n- *\n- * and TI CAL camera interface driver by\n- *    Benoit Parrot <bparrot@ti.com>\n- *\n- *\n- * There are two camera drivers in the kernel for BCM283x - this one\n- * and bcm2835-camera (currently in staging).\n- *\n- * This driver directly controls the Unicam peripheral - there is no\n- * involvement with the VideoCore firmware. Unicam receives CSI-2 or\n- * CCP2 data and writes it into SDRAM.\n- * The only potential processing options are to repack Bayer data into an\n- * alternate format, and applying windowing.\n- * The repacking does not shift the data, so can repack V4L2_PIX_FMT_Sxxxx10P\n- * to V4L2_PIX_FMT_Sxxxx10, or V4L2_PIX_FMT_Sxxxx12P to V4L2_PIX_FMT_Sxxxx12,\n- * but not generically up to V4L2_PIX_FMT_Sxxxx16. The driver will add both\n- * formats where the relevant formats are defined, and will automatically\n- * configure the repacking as required.\n- * Support for windowing may be added later.\n- *\n- * It should be possible to connect this driver to any sensor with a\n- * suitable output interface and V4L2 subdevice driver.\n- *\n- * bcm2835-camera uses the VideoCore firmware to control the sensor,\n- * Unicam, ISP, and all tuner control loops. Fully processed frames are\n- * delivered to the driver by the firmware. It only has sensor drivers\n- * for Omnivision OV5647, and Sony IMX219 sensors.\n- *\n- * The two drivers are mutually exclusive for the same Unicam instance.\n- * The VideoCore firmware checks the device tree configuration during boot.\n- * If it finds device tree nodes called csi0 or csi1 it will block the\n- * firmware from accessing the peripheral, and bcm2835-camera will\n- * not be able to stream data.\n- */\n-\n-#include <linux/clk.h>\n-#include <linux/delay.h>\n-#include <linux/device.h>\n-#include <linux/dma-mapping.h>\n-#include <linux/err.h>\n-#include <linux/init.h>\n-#include <linux/interrupt.h>\n-#include <linux/io.h>\n-#include <linux/module.h>\n-#include <linux/of_device.h>\n-#include <linux/of_graph.h>\n-#include <linux/pinctrl/consumer.h>\n-#include <linux/platform_device.h>\n-#include <linux/pm_runtime.h>\n-#include <linux/slab.h>\n-#include <linux/uaccess.h>\n-#include <linux/videodev2.h>\n-\n-#include <media/v4l2-common.h>\n-#include <media/v4l2-ctrls.h>\n-#include <media/v4l2-dev.h>\n-#include <media/v4l2-device.h>\n-#include <media/v4l2-dv-timings.h>\n-#include <media/v4l2-event.h>\n-#include <media/v4l2-ioctl.h>\n-#include <media/v4l2-fwnode.h>\n-#include <media/videobuf2-dma-contig.h>\n-\n-#include \"vc4-regs-unicam.h\"\n-\n-#define UNICAM_MODULE_NAME\t\"unicam\"\n-#define UNICAM_VERSION\t\t\"0.1.0\"\n-\n-static int debug;\n-module_param(debug, int, 0644);\n-MODULE_PARM_DESC(debug, \"Debug level 0-3\");\n-\n-#define unicam_dbg(level, dev, fmt, arg...)\t\\\n-\t\tv4l2_dbg(level, debug, &(dev)->v4l2_dev, fmt, ##arg)\n-#define unicam_info(dev, fmt, arg...)\t\\\n-\t\tv4l2_info(&(dev)->v4l2_dev, fmt, ##arg)\n-#define unicam_err(dev, fmt, arg...)\t\\\n-\t\tv4l2_err(&(dev)->v4l2_dev, fmt, ##arg)\n-\n-/* To protect against a dodgy sensor driver never returning an error from\n- * enum_mbus_code, set a maximum index value to be used.\n- */\n-#define MAX_ENUM_MBUS_CODE\t128\n-\n-/*\n- * Stride is a 16 bit register, but also has to be a multiple of 32.\n- */\n-#define BPL_ALIGNMENT\t\t32\n-#define MAX_BYTESPERLINE\t((1 << 16) - BPL_ALIGNMENT)\n-/*\n- * Max width is therefore determined by the max stride divided by\n- * the number of bits per pixel. Take 32bpp as a\n- * worst case.\n- * No imposed limit on the height, so adopt a square image for want\n- * of anything better.\n- */\n-#define MAX_WIDTH\t(MAX_BYTESPERLINE / 4)\n-#define MAX_HEIGHT\tMAX_WIDTH\n-/* Define a nominal minimum image size */\n-#define MIN_WIDTH\t16\n-#define MIN_HEIGHT\t16\n-/* Default size of the embedded buffer */\n-#define UNICAM_EMBEDDED_SIZE\t8192\n-\n-/*\n- * Size of the dummy buffer. Can be any size really, but the DMA\n- * allocation works in units of page sizes.\n- */\n-#define DUMMY_BUF_SIZE\t(PAGE_SIZE)\n-\n-enum pad_types {\n-\tIMAGE_PAD,\n-\tMETADATA_PAD,\n-\tMAX_NODES\n-};\n-\n-/*\n- * struct unicam_fmt - Unicam media bus format information\n- * @pixelformat: V4L2 pixel format FCC identifier. 0 if n/a.\n- * @repacked_fourcc: V4L2 pixel format FCC identifier if the data is expanded\n- * out to 16bpp. 0 if n/a.\n- * @code: V4L2 media bus format code.\n- * @depth: Bits per pixel as delivered from the source.\n- * @csi_dt: CSI data type.\n- * @check_variants: Flag to denote that there are multiple mediabus formats\n- *\t\tstill in the list that could match this V4L2 format.\n- */\n-struct unicam_fmt {\n-\tu32\tfourcc;\n-\tu32\trepacked_fourcc;\n-\tu32\tcode;\n-\tu8\tdepth;\n-\tu8\tcsi_dt;\n-\tu8\tcheck_variants;\n-};\n-\n-static const struct unicam_fmt formats[] = {\n-\t/* YUV Formats */\n-\t{\n-\t\t.fourcc\t\t= V4L2_PIX_FMT_YUYV,\n-\t\t.code\t\t= MEDIA_BUS_FMT_YUYV8_2X8,\n-\t\t.depth\t\t= 16,\n-\t\t.csi_dt\t\t= 0x1e,\n-\t\t.check_variants = 1,\n-\t}, {\n-\t\t.fourcc\t\t= V4L2_PIX_FMT_UYVY,\n-\t\t.code\t\t= MEDIA_BUS_FMT_UYVY8_2X8,\n-\t\t.depth\t\t= 16,\n-\t\t.csi_dt\t\t= 0x1e,\n-\t\t.check_variants = 1,\n-\t}, {\n-\t\t.fourcc\t\t= V4L2_PIX_FMT_YVYU,\n-\t\t.code\t\t= MEDIA_BUS_FMT_YVYU8_2X8,\n-\t\t.depth\t\t= 16,\n-\t\t.csi_dt\t\t= 0x1e,\n-\t\t.check_variants = 1,\n-\t}, {\n-\t\t.fourcc\t\t= V4L2_PIX_FMT_VYUY,\n-\t\t.code\t\t= MEDIA_BUS_FMT_VYUY8_2X8,\n-\t\t.depth\t\t= 16,\n-\t\t.csi_dt\t\t= 0x1e,\n-\t\t.check_variants = 1,\n-\t}, {\n-\t\t.fourcc\t\t= V4L2_PIX_FMT_YUYV,\n-\t\t.code\t\t= MEDIA_BUS_FMT_YUYV8_1X16,\n-\t\t.depth\t\t= 16,\n-\t\t.csi_dt\t\t= 0x1e,\n-\t}, {\n-\t\t.fourcc\t\t= V4L2_PIX_FMT_UYVY,\n-\t\t.code\t\t= MEDIA_BUS_FMT_UYVY8_1X16,\n-\t\t.depth\t\t= 16,\n-\t\t.csi_dt\t\t= 0x1e,\n-\t}, {\n-\t\t.fourcc\t\t= V4L2_PIX_FMT_YVYU,\n-\t\t.code\t\t= MEDIA_BUS_FMT_YVYU8_1X16,\n-\t\t.depth\t\t= 16,\n-\t\t.csi_dt\t\t= 0x1e,\n-\t}, {\n-\t\t.fourcc\t\t= V4L2_PIX_FMT_VYUY,\n-\t\t.code\t\t= MEDIA_BUS_FMT_VYUY8_1X16,\n-\t\t.depth\t\t= 16,\n-\t\t.csi_dt\t\t= 0x1e,\n-\t}, {\n-\t/* RGB Formats */\n-\t\t.fourcc\t\t= V4L2_PIX_FMT_RGB565, /* gggbbbbb rrrrrggg */\n-\t\t.code\t\t= MEDIA_BUS_FMT_RGB565_2X8_LE,\n-\t\t.depth\t\t= 16,\n-\t\t.csi_dt\t\t= 0x22,\n-\t}, {\n-\t\t.fourcc\t\t= V4L2_PIX_FMT_RGB565X, /* rrrrrggg gggbbbbb */\n-\t\t.code\t\t= MEDIA_BUS_FMT_RGB565_2X8_BE,\n-\t\t.depth\t\t= 16,\n-\t\t.csi_dt\t\t= 0x22\n-\t}, {\n-\t\t.fourcc\t\t= V4L2_PIX_FMT_RGB555, /* gggbbbbb arrrrrgg */\n-\t\t.code\t\t= MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE,\n-\t\t.depth\t\t= 16,\n-\t\t.csi_dt\t\t= 0x21,\n-\t}, {\n-\t\t.fourcc\t\t= V4L2_PIX_FMT_RGB555X, /* arrrrrgg gggbbbbb */\n-\t\t.code\t\t= MEDIA_BUS_FMT_RGB555_2X8_PADHI_BE,\n-\t\t.depth\t\t= 16,\n-\t\t.csi_dt\t\t= 0x21,\n-\t}, {\n-\t\t.fourcc\t\t= V4L2_PIX_FMT_RGB24, /* rgb */\n-\t\t.code\t\t= MEDIA_BUS_FMT_RGB888_1X24,\n-\t\t.depth\t\t= 24,\n-\t\t.csi_dt\t\t= 0x24,\n-\t}, {\n-\t\t.fourcc\t\t= V4L2_PIX_FMT_BGR24, /* bgr */\n-\t\t.code\t\t= MEDIA_BUS_FMT_BGR888_1X24,\n-\t\t.depth\t\t= 24,\n-\t\t.csi_dt\t\t= 0x24,\n-\t}, {\n-\t\t.fourcc\t\t= V4L2_PIX_FMT_RGB32, /* argb */\n-\t\t.code\t\t= MEDIA_BUS_FMT_ARGB8888_1X32,\n-\t\t.depth\t\t= 32,\n-\t\t.csi_dt\t\t= 0x0,\n-\t}, {\n-\t/* Bayer Formats */\n-\t\t.fourcc\t\t= V4L2_PIX_FMT_SBGGR8,\n-\t\t.code\t\t= MEDIA_BUS_FMT_SBGGR8_1X8,\n-\t\t.depth\t\t= 8,\n-\t\t.csi_dt\t\t= 0x2a,\n-\t}, {\n-\t\t.fourcc\t\t= V4L2_PIX_FMT_SGBRG8,\n-\t\t.code\t\t= MEDIA_BUS_FMT_SGBRG8_1X8,\n-\t\t.depth\t\t= 8,\n-\t\t.csi_dt\t\t= 0x2a,\n-\t}, {\n-\t\t.fourcc\t\t= V4L2_PIX_FMT_SGRBG8,\n-\t\t.code\t\t= MEDIA_BUS_FMT_SGRBG8_1X8,\n-\t\t.depth\t\t= 8,\n-\t\t.csi_dt\t\t= 0x2a,\n-\t}, {\n-\t\t.fourcc\t\t= V4L2_PIX_FMT_SRGGB8,\n-\t\t.code\t\t= MEDIA_BUS_FMT_SRGGB8_1X8,\n-\t\t.depth\t\t= 8,\n-\t\t.csi_dt\t\t= 0x2a,\n-\t}, {\n-\t\t.fourcc\t\t= V4L2_PIX_FMT_SBGGR10P,\n-\t\t.repacked_fourcc = V4L2_PIX_FMT_SBGGR10,\n-\t\t.code\t\t= MEDIA_BUS_FMT_SBGGR10_1X10,\n-\t\t.depth\t\t= 10,\n-\t\t.csi_dt\t\t= 0x2b,\n-\t}, {\n-\t\t.fourcc\t\t= V4L2_PIX_FMT_SGBRG10P,\n-\t\t.repacked_fourcc = V4L2_PIX_FMT_SGBRG10,\n-\t\t.code\t\t= MEDIA_BUS_FMT_SGBRG10_1X10,\n-\t\t.depth\t\t= 10,\n-\t\t.csi_dt\t\t= 0x2b,\n-\t}, {\n-\t\t.fourcc\t\t= V4L2_PIX_FMT_SGRBG10P,\n-\t\t.repacked_fourcc = V4L2_PIX_FMT_SGRBG10,\n-\t\t.code\t\t= MEDIA_BUS_FMT_SGRBG10_1X10,\n-\t\t.depth\t\t= 10,\n-\t\t.csi_dt\t\t= 0x2b,\n-\t}, {\n-\t\t.fourcc\t\t= V4L2_PIX_FMT_SRGGB10P,\n-\t\t.repacked_fourcc = V4L2_PIX_FMT_SRGGB10,\n-\t\t.code\t\t= MEDIA_BUS_FMT_SRGGB10_1X10,\n-\t\t.depth\t\t= 10,\n-\t\t.csi_dt\t\t= 0x2b,\n-\t}, {\n-\t\t.fourcc\t\t= V4L2_PIX_FMT_SBGGR12P,\n-\t\t.repacked_fourcc = V4L2_PIX_FMT_SBGGR12,\n-\t\t.code\t\t= MEDIA_BUS_FMT_SBGGR12_1X12,\n-\t\t.depth\t\t= 12,\n-\t\t.csi_dt\t\t= 0x2c,\n-\t}, {\n-\t\t.fourcc\t\t= V4L2_PIX_FMT_SGBRG12P,\n-\t\t.repacked_fourcc = V4L2_PIX_FMT_SGBRG12,\n-\t\t.code\t\t= MEDIA_BUS_FMT_SGBRG12_1X12,\n-\t\t.depth\t\t= 12,\n-\t\t.csi_dt\t\t= 0x2c,\n-\t}, {\n-\t\t.fourcc\t\t= V4L2_PIX_FMT_SGRBG12P,\n-\t\t.repacked_fourcc = V4L2_PIX_FMT_SGRBG12,\n-\t\t.code\t\t= MEDIA_BUS_FMT_SGRBG12_1X12,\n-\t\t.depth\t\t= 12,\n-\t\t.csi_dt\t\t= 0x2c,\n-\t}, {\n-\t\t.fourcc\t\t= V4L2_PIX_FMT_SRGGB12P,\n-\t\t.repacked_fourcc = V4L2_PIX_FMT_SRGGB12,\n-\t\t.code\t\t= MEDIA_BUS_FMT_SRGGB12_1X12,\n-\t\t.depth\t\t= 12,\n-\t\t.csi_dt\t\t= 0x2c,\n-\t}, {\n-\t\t.fourcc\t\t= V4L2_PIX_FMT_SBGGR14P,\n-\t\t.code\t\t= MEDIA_BUS_FMT_SBGGR14_1X14,\n-\t\t.depth\t\t= 14,\n-\t\t.csi_dt\t\t= 0x2d,\n-\t}, {\n-\t\t.fourcc\t\t= V4L2_PIX_FMT_SGBRG14P,\n-\t\t.code\t\t= MEDIA_BUS_FMT_SGBRG14_1X14,\n-\t\t.depth\t\t= 14,\n-\t\t.csi_dt\t\t= 0x2d,\n-\t}, {\n-\t\t.fourcc\t\t= V4L2_PIX_FMT_SGRBG14P,\n-\t\t.code\t\t= MEDIA_BUS_FMT_SGRBG14_1X14,\n-\t\t.depth\t\t= 14,\n-\t\t.csi_dt\t\t= 0x2d,\n-\t}, {\n-\t\t.fourcc\t\t= V4L2_PIX_FMT_SRGGB14P,\n-\t\t.code\t\t= MEDIA_BUS_FMT_SRGGB14_1X14,\n-\t\t.depth\t\t= 14,\n-\t\t.csi_dt\t\t= 0x2d,\n-\t}, {\n-\t/*\n-\t * 16 bit Bayer formats could be supported, but there is no CSI2\n-\t * data_type defined for raw 16, and no sensors that produce it at\n-\t * present.\n-\t */\n-\n-\t/* Greyscale formats */\n-\t\t.fourcc\t\t= V4L2_PIX_FMT_GREY,\n-\t\t.code\t\t= MEDIA_BUS_FMT_Y8_1X8,\n-\t\t.depth\t\t= 8,\n-\t\t.csi_dt\t\t= 0x2a,\n-\t}, {\n-\t\t.fourcc\t\t= V4L2_PIX_FMT_Y10P,\n-\t\t.repacked_fourcc = V4L2_PIX_FMT_Y10,\n-\t\t.code\t\t= MEDIA_BUS_FMT_Y10_1X10,\n-\t\t.depth\t\t= 10,\n-\t\t.csi_dt\t\t= 0x2b,\n-\t}, {\n-\t\t/* NB There is no packed V4L2 fourcc for this format. */\n-\t\t.repacked_fourcc = V4L2_PIX_FMT_Y12,\n-\t\t.code\t\t= MEDIA_BUS_FMT_Y12_1X12,\n-\t\t.depth\t\t= 12,\n-\t\t.csi_dt\t\t= 0x2c,\n-\t},\n-\t/* Embedded data format */\n-\t{\n-\t\t.fourcc\t\t= V4L2_META_FMT_SENSOR_DATA,\n-\t\t.code\t\t= MEDIA_BUS_FMT_SENSOR_DATA,\n-\t\t.depth\t\t= 8,\n-\t}\n-};\n-\n-struct unicam_dmaqueue {\n-\tstruct list_head\tactive;\n-};\n-\n-struct unicam_buffer {\n-\tstruct vb2_v4l2_buffer vb;\n-\tstruct list_head list;\n-};\n-\n-struct unicam_cfg {\n-\t/* peripheral base address */\n-\tvoid __iomem *base;\n-\t/* clock gating base address */\n-\tvoid __iomem *clk_gate_base;\n-};\n-\n-#define MAX_POSSIBLE_PIX_FMTS (ARRAY_SIZE(formats))\n-\n-struct unicam_node {\n-\tint registered;\n-\tint open;\n-\tint streaming;\n-\tunsigned int pad_id;\n-\t/* Pointer pointing to current v4l2_buffer */\n-\tstruct unicam_buffer *cur_frm;\n-\t/* Pointer pointing to next v4l2_buffer */\n-\tstruct unicam_buffer *next_frm;\n-\t/* video capture */\n-\tconst struct unicam_fmt *fmt;\n-\t/* Used to store current pixel format */\n-\tstruct v4l2_format v_fmt;\n-\t/* Used to store current mbus frame format */\n-\tstruct v4l2_mbus_framefmt m_fmt;\n-\t/* Buffer queue used in video-buf */\n-\tstruct vb2_queue buffer_queue;\n-\t/* Queue of filled frames */\n-\tstruct unicam_dmaqueue dma_queue;\n-\t/* IRQ lock for DMA queue */\n-\tspinlock_t dma_queue_lock;\n-\t/* lock used to access this structure */\n-\tstruct mutex lock;\n-\t/* Identifies video device for this channel */\n-\tstruct video_device video_dev;\n-\t/* Pointer to the parent handle */\n-\tstruct unicam_device *dev;\n-\tstruct media_pad pad;\n-\tstruct v4l2_ctrl_handler ctrl_handler;\n-\tunsigned int embedded_lines;\n-\t/*\n-\t * Dummy buffer intended to be used by unicam\n-\t * if we have no other queued buffers to swap to.\n-\t */\n-\tvoid *dummy_buf_cpu_addr;\n-\tdma_addr_t dummy_buf_dma_addr;\n-};\n-\n-struct unicam_device {\n-\t/* V4l2 specific parameters */\n-\n-\tstruct v4l2_fwnode_endpoint endpoint;\n-\n-\tstruct v4l2_async_subdev asd;\n-\n-\t/* unicam cfg */\n-\tstruct unicam_cfg cfg;\n-\t/* clock handle */\n-\tstruct clk *clock;\n-\t/* V4l2 device */\n-\tstruct v4l2_device v4l2_dev;\n-\tstruct media_device mdev;\n-\n-\t/* parent device */\n-\tstruct platform_device *pdev;\n-\t/* subdevice async Notifier */\n-\tstruct v4l2_async_notifier notifier;\n-\tunsigned int sequence;\n-\n-\t/* ptr to  sub device */\n-\tstruct v4l2_subdev *sensor;\n-\t/* Pad config for the sensor */\n-\tstruct v4l2_subdev_pad_config *sensor_config;\n-\n-\tunsigned int virtual_channel;\n-\tenum v4l2_mbus_type bus_type;\n-\t/*\n-\t * Stores bus.mipi_csi2.flags for CSI2 sensors, or\n-\t * bus.mipi_csi1.strobe for CCP2.\n-\t */\n-\tunsigned int bus_flags;\n-\tunsigned int max_data_lanes;\n-\tunsigned int active_data_lanes;\n-\tbool sensor_embedded_data;\n-\n-\tstruct unicam_node node[MAX_NODES];\n-};\n-\n-/* Hardware access */\n-#define clk_write(dev, val) writel((val) | 0x5a000000, (dev)->clk_gate_base)\n-#define clk_read(dev) readl((dev)->clk_gate_base)\n-\n-#define reg_read(dev, offset) readl((dev)->base + (offset))\n-#define reg_write(dev, offset, val) writel(val, (dev)->base + (offset))\n-\n-#define reg_read_field(dev, offset, mask) get_field(reg_read((dev), (offset), \\\n-\t\t\t\t\t\t    mask))\n-\n-static inline int get_field(u32 value, u32 mask)\n-{\n-\treturn (value & mask) >> __ffs(mask);\n-}\n-\n-static inline void set_field(u32 *valp, u32 field, u32 mask)\n-{\n-\tu32 val = *valp;\n-\n-\tval &= ~mask;\n-\tval |= (field << __ffs(mask)) & mask;\n-\t*valp = val;\n-}\n-\n-static inline void reg_write_field(struct unicam_cfg *dev, u32 offset,\n-\t\t\t\t   u32 field, u32 mask)\n-{\n-\tu32 val = reg_read((dev), (offset));\n-\n-\tset_field(&val, field, mask);\n-\treg_write((dev), (offset), val);\n-}\n-\n-/* Power management functions */\n-static inline int unicam_runtime_get(struct unicam_device *dev)\n-{\n-\treturn pm_runtime_get_sync(&dev->pdev->dev);\n-}\n-\n-static inline void unicam_runtime_put(struct unicam_device *dev)\n-{\n-\tpm_runtime_put_sync(&dev->pdev->dev);\n-}\n-\n-/* Format setup functions */\n-static const struct unicam_fmt *find_format_by_code(u32 code)\n-{\n-\tunsigned int i;\n-\n-\tfor (i = 0; i < ARRAY_SIZE(formats); i++) {\n-\t\tif (formats[i].code == code)\n-\t\t\treturn &formats[i];\n-\t}\n-\n-\treturn NULL;\n-}\n-\n-static int check_mbus_format(struct unicam_device *dev,\n-\t\t\t     const struct unicam_fmt *format)\n-{\n-\tstruct v4l2_subdev_mbus_code_enum mbus_code;\n-\tint ret = 0;\n-\tint i;\n-\n-\tfor (i = 0; !ret && i < MAX_ENUM_MBUS_CODE; i++) {\n-\t\tmemset(&mbus_code, 0, sizeof(mbus_code));\n-\t\tmbus_code.index = i;\n-\t\tmbus_code.pad = IMAGE_PAD;\n-\t\tmbus_code.which = V4L2_SUBDEV_FORMAT_ACTIVE;\n-\n-\t\tret = v4l2_subdev_call(dev->sensor, pad, enum_mbus_code,\n-\t\t\t\t       NULL, &mbus_code);\n-\n-\t\tif (!ret && mbus_code.code == format->code)\n-\t\t\treturn 1;\n-\t}\n-\n-\treturn 0;\n-}\n-\n-static const struct unicam_fmt *find_format_by_pix(struct unicam_device *dev,\n-\t\t\t\t\t\t   u32 pixelformat)\n-{\n-\tunsigned int i;\n-\n-\tfor (i = 0; i < ARRAY_SIZE(formats); i++) {\n-\t\tif (formats[i].fourcc == pixelformat ||\n-\t\t    formats[i].repacked_fourcc == pixelformat) {\n-\t\t\tif (formats[i].check_variants &&\n-\t\t\t    !check_mbus_format(dev, &formats[i]))\n-\t\t\t\tcontinue;\n-\t\t\treturn &formats[i];\n-\t\t}\n-\t}\n-\n-\treturn NULL;\n-}\n-\n-static inline unsigned int bytes_per_line(u32 width,\n-\t\t\t\t\t  const struct unicam_fmt *fmt,\n-\t\t\t\t\t  u32 v4l2_fourcc)\n-{\n-\tif (v4l2_fourcc == fmt->repacked_fourcc)\n-\t\t/* Repacking always goes to 16bpp */\n-\t\treturn ALIGN(width << 1, BPL_ALIGNMENT);\n-\telse\n-\t\treturn ALIGN((width * fmt->depth) >> 3, BPL_ALIGNMENT);\n-}\n-\n-static int __subdev_get_format(struct unicam_device *dev,\n-\t\t\t       struct v4l2_mbus_framefmt *fmt, int pad_id)\n-{\n-\tstruct v4l2_subdev_format sd_fmt = {\n-\t\t.which = V4L2_SUBDEV_FORMAT_ACTIVE,\n-\t\t.pad = pad_id\n-\t};\n-\tint ret;\n-\n-\tret = v4l2_subdev_call(dev->sensor, pad, get_fmt, dev->sensor_config,\n-\t\t\t       &sd_fmt);\n-\tif (ret < 0)\n-\t\treturn ret;\n-\n-\t*fmt = sd_fmt.format;\n-\n-\tunicam_dbg(1, dev, \"%s %dx%d code:%04x\\n\", __func__,\n-\t\t   fmt->width, fmt->height, fmt->code);\n-\n-\treturn 0;\n-}\n-\n-static int __subdev_set_format(struct unicam_device *dev,\n-\t\t\t       struct v4l2_mbus_framefmt *fmt, int pad_id)\n-{\n-\tstruct v4l2_subdev_format sd_fmt = {\n-\t\t.which = V4L2_SUBDEV_FORMAT_ACTIVE,\n-\t\t.pad = pad_id\n-\t};\n-\tint ret;\n-\n-\tsd_fmt.format = *fmt;\n-\n-\tret = v4l2_subdev_call(dev->sensor, pad, set_fmt, dev->sensor_config,\n-\t\t\t       &sd_fmt);\n-\tif (ret < 0)\n-\t\treturn ret;\n-\n-\tif (pad_id == IMAGE_PAD)\n-\t\tunicam_dbg(1, dev, \"%s %dx%d code:%04x\\n\", __func__, fmt->width,\n-\t\t\t   fmt->height, fmt->code);\n-\telse\n-\t\tunicam_dbg(1, dev, \"%s Embedded data code:%04x\\n\", __func__,\n-\t\t\t   sd_fmt.format.code);\n-\n-\treturn 0;\n-}\n-\n-static int unicam_calc_format_size_bpl(struct unicam_device *dev,\n-\t\t\t\t       const struct unicam_fmt *fmt,\n-\t\t\t\t       struct v4l2_format *f)\n-{\n-\tunsigned int min_bytesperline;\n-\n-\tv4l_bound_align_image(&f->fmt.pix.width, MIN_WIDTH, MAX_WIDTH, 2,\n-\t\t\t      &f->fmt.pix.height, MIN_HEIGHT, MAX_HEIGHT, 0,\n-\t\t\t      0);\n-\n-\tmin_bytesperline = bytes_per_line(f->fmt.pix.width, fmt,\n-\t\t\t\t\t  f->fmt.pix.pixelformat);\n-\n-\tif (f->fmt.pix.bytesperline > min_bytesperline &&\n-\t    f->fmt.pix.bytesperline <= MAX_BYTESPERLINE)\n-\t\tf->fmt.pix.bytesperline = ALIGN(f->fmt.pix.bytesperline,\n-\t\t\t\t\t\tBPL_ALIGNMENT);\n-\telse\n-\t\tf->fmt.pix.bytesperline = min_bytesperline;\n-\n-\tf->fmt.pix.sizeimage = f->fmt.pix.height * f->fmt.pix.bytesperline;\n-\n-\tunicam_dbg(3, dev, \"%s: fourcc: %08X size: %dx%d bpl:%d img_size:%d\\n\",\n-\t\t   __func__,\n-\t\t   f->fmt.pix.pixelformat,\n-\t\t   f->fmt.pix.width, f->fmt.pix.height,\n-\t\t   f->fmt.pix.bytesperline, f->fmt.pix.sizeimage);\n-\n-\treturn 0;\n-}\n-\n-static int unicam_reset_format(struct unicam_node *node)\n-{\n-\tstruct unicam_device *dev = node->dev;\n-\tstruct v4l2_mbus_framefmt mbus_fmt;\n-\tint ret;\n-\n-\tif (dev->sensor_embedded_data || node->pad_id != METADATA_PAD) {\n-\t\tret = __subdev_get_format(dev, &mbus_fmt, node->pad_id);\n-\t\tif (ret) {\n-\t\t\tunicam_err(dev, \"Failed to get_format - ret %d\\n\", ret);\n-\t\t\treturn ret;\n-\t\t}\n-\n-\t\tif (mbus_fmt.code != node->fmt->code) {\n-\t\t\tunicam_err(dev, \"code mismatch - fmt->code %08x, mbus_fmt.code %08x\\n\",\n-\t\t\t\t   node->fmt->code, mbus_fmt.code);\n-\t\t\treturn ret;\n-\t\t}\n-\t}\n-\n-\tif (node->pad_id == IMAGE_PAD) {\n-\t\tv4l2_fill_pix_format(&node->v_fmt.fmt.pix, &mbus_fmt);\n-\t\tnode->v_fmt.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;\n-\t\tunicam_calc_format_size_bpl(dev, node->fmt, &node->v_fmt);\n-\t} else {\n-\t\tnode->v_fmt.type = V4L2_BUF_TYPE_META_CAPTURE;\n-\t\tnode->v_fmt.fmt.meta.dataformat = V4L2_META_FMT_SENSOR_DATA;\n-\t\tif (dev->sensor_embedded_data) {\n-\t\t\tnode->v_fmt.fmt.meta.buffersize =\n-\t\t\t\t\tmbus_fmt.width * mbus_fmt.height;\n-\t\t\tnode->embedded_lines = mbus_fmt.height;\n-\t\t} else {\n-\t\t\tnode->v_fmt.fmt.meta.buffersize = UNICAM_EMBEDDED_SIZE;\n-\t\t\tnode->embedded_lines = 1;\n-\t\t}\n-\t}\n-\n-\tnode->m_fmt = mbus_fmt;\n-\treturn 0;\n-}\n-\n-static void unicam_wr_dma_addr(struct unicam_cfg *cfg, dma_addr_t dmaaddr,\n-\t\t\t       unsigned int buffer_size, int pad_id)\n-{\n-\tdma_addr_t endaddr = dmaaddr + buffer_size;\n-\n-\t/*\n-\t * dmaaddr and endaddr should be a 32-bit address with the top two bits\n-\t * set to 0x3 to signify uncached access through the Videocore memory\n-\t * controller.\n-\t */\n-\tBUG_ON((dmaaddr >> 30) != 0x3 && (endaddr >> 30) != 0x3);\n-\n-\tif (pad_id == IMAGE_PAD) {\n-\t\treg_write(cfg, UNICAM_IBSA0, dmaaddr);\n-\t\treg_write(cfg, UNICAM_IBEA0, endaddr);\n-\t} else {\n-\t\treg_write(cfg, UNICAM_DBSA0, dmaaddr);\n-\t\treg_write(cfg, UNICAM_DBEA0, endaddr);\n-\t}\n-}\n-\n-static inline unsigned int unicam_get_lines_done(struct unicam_device *dev)\n-{\n-\tdma_addr_t start_addr, cur_addr;\n-\tunsigned int stride = dev->node[IMAGE_PAD].v_fmt.fmt.pix.bytesperline;\n-\tstruct unicam_buffer *frm = dev->node[IMAGE_PAD].cur_frm;\n-\n-\tif (!frm)\n-\t\treturn 0;\n-\n-\tstart_addr = vb2_dma_contig_plane_dma_addr(&frm->vb.vb2_buf, 0);\n-\tcur_addr = reg_read(&dev->cfg, UNICAM_IBWP);\n-\treturn (unsigned int)(cur_addr - start_addr) / stride;\n-}\n-\n-static inline void unicam_schedule_next_buffer(struct unicam_node *node)\n-{\n-\tstruct unicam_device *dev = node->dev;\n-\tstruct unicam_dmaqueue *dma_q = &node->dma_queue;\n-\tstruct unicam_buffer *buf;\n-\tunsigned int size;\n-\tdma_addr_t addr;\n-\n-\tbuf = list_entry(dma_q->active.next, struct unicam_buffer, list);\n-\tnode->next_frm = buf;\n-\tlist_del(&buf->list);\n-\n-\taddr = vb2_dma_contig_plane_dma_addr(&buf->vb.vb2_buf, 0);\n-\tsize = (node->pad_id == IMAGE_PAD) ?\n-\t\t\tdev->node[IMAGE_PAD].v_fmt.fmt.pix.sizeimage :\n-\t\t\tdev->node[METADATA_PAD].v_fmt.fmt.meta.buffersize;\n-\n-\tunicam_wr_dma_addr(&dev->cfg, addr, size, node->pad_id);\n-}\n-\n-static inline void unicam_schedule_dummy_buffer(struct unicam_node *node)\n-{\n-\tstruct unicam_device *dev = node->dev;\n-\tdma_addr_t addr = node->dummy_buf_dma_addr;\n-\n-\tunicam_dbg(3, dev, \"Scheduling dummy buffer for node %d\\n\",\n-\t\t   node->pad_id);\n-\n-\tunicam_wr_dma_addr(&dev->cfg, addr, DUMMY_BUF_SIZE, node->pad_id);\n-\tnode->next_frm = NULL;\n-}\n-\n-static inline void unicam_process_buffer_complete(struct unicam_node *node,\n-\t\t\t\t\t\t  unsigned int sequence)\n-{\n-\tnode->cur_frm->vb.field = node->m_fmt.field;\n-\tnode->cur_frm->vb.sequence = sequence;\n-\n-\tvb2_buffer_done(&node->cur_frm->vb.vb2_buf, VB2_BUF_STATE_DONE);\n-}\n-\n-static int unicam_num_nodes_streaming(struct unicam_device *dev)\n-{\n-\treturn dev->node[IMAGE_PAD].streaming +\n-\t       dev->node[METADATA_PAD].streaming;\n-}\n-\n-static int unicam_all_nodes_streaming(struct unicam_device *dev)\n-{\n-\tint ret;\n-\n-\tret = dev->node[IMAGE_PAD].open && dev->node[IMAGE_PAD].streaming;\n-\tret &= !dev->node[METADATA_PAD].open ||\n-\t       dev->node[METADATA_PAD].streaming;\n-\treturn ret;\n-}\n-\n-static void unicam_queue_event_sof(struct unicam_device *unicam)\n-{\n-\tstruct v4l2_event event = {\n-\t\t.type = V4L2_EVENT_FRAME_SYNC,\n-\t\t.u.frame_sync.frame_sequence = unicam->sequence,\n-\t};\n-\n-\tv4l2_event_queue(&unicam->node[IMAGE_PAD].video_dev, &event);\n-}\n-\n-/*\n- * unicam_isr : ISR handler for unicam capture\n- * @irq: irq number\n- * @dev_id: dev_id ptr\n- *\n- * It changes status of the captured buffer, takes next buffer from the queue\n- * and sets its address in unicam registers\n- */\n-static irqreturn_t unicam_isr(int irq, void *dev)\n-{\n-\tstruct unicam_device *unicam = (struct unicam_device *)dev;\n-\tstruct unicam_cfg *cfg = &unicam->cfg;\n-\tunsigned int lines_done = unicam_get_lines_done(dev);\n-\tunsigned int sequence = unicam->sequence;\n-\tint num_nodes_streaming = unicam_num_nodes_streaming(dev);\n-\tint ista, sta;\n-\tu64 ts;\n-\tint i;\n-\n-\tsta = reg_read(cfg, UNICAM_STA);\n-\t/* Write value back to clear the interrupts */\n-\treg_write(cfg, UNICAM_STA, sta);\n-\n-\tista = reg_read(cfg, UNICAM_ISTA);\n-\t/* Write value back to clear the interrupts */\n-\treg_write(cfg, UNICAM_ISTA, ista);\n-\n-\tunicam_dbg(3, unicam, \"ISR: ISTA: 0x%X, STA: 0x%X, sequence %d, lines done %d\",\n-\t\t   ista, sta, sequence, lines_done);\n-\n-\tif (!(sta && (UNICAM_IS | UNICAM_PI0)))\n-\t\treturn IRQ_HANDLED;\n-\n-\t/*\n-\t * We must run the frame end handler first. If we have a valid next_frm\n-\t * and we get a simultaneout FE + FS interrupt, running the FS handler\n-\t * first would null out the next_frm ptr and we would have lost the\n-\t * buffer forever.\n-\t */\n-\tif (ista & UNICAM_FEI || sta & UNICAM_PI0) {\n-\t\t/*\n-\t\t * Ensure we have swapped buffers already as we can't\n-\t\t * stop the peripheral. If no buffer is available, use a\n-\t\t * dummy buffer to dump out frames until we get a new buffer\n-\t\t * to use.\n-\t\t */\n-\t\tfor (i = 0; i < num_nodes_streaming; i++) {\n-\t\t\tif (unicam->node[i].cur_frm)\n-\t\t\t\tunicam_process_buffer_complete(&unicam->node[i],\n-\t\t\t\t\t\t\t       sequence);\n-\t\t\tunicam->node[i].cur_frm = unicam->node[i].next_frm;\n-\t\t}\n-\t\tunicam->sequence++;\n-\t}\n-\n-\tif (ista & UNICAM_FSI) {\n-\t\t/*\n-\t\t * Timestamp is to be when the first data byte was captured,\n-\t\t * aka frame start.\n-\t\t */\n-\t\tts = ktime_get_ns();\n-\t\tfor (i = 0; i < num_nodes_streaming; i++) {\n-\t\t\tif (unicam->node[i].cur_frm)\n-\t\t\t\tunicam->node[i].cur_frm->vb.vb2_buf.timestamp =\n-\t\t\t\t\t\t\t\tts;\n-\t\t\t/*\n-\t\t\t * Set the next frame output to go to a dummy frame\n-\t\t\t * if we have not managed to obtain another frame\n-\t\t\t * from the queue.\n-\t\t\t */\n-\t\t\tunicam_schedule_dummy_buffer(&unicam->node[i]);\n-\t\t}\n-\n-\t\tunicam_queue_event_sof(unicam);\n-\t}\n-\t/*\n-\t * Cannot swap buffer at frame end, there may be a race condition\n-\t * where the HW does not actually swap it if the new frame has\n-\t * already started.\n-\t */\n-\tif (ista & (UNICAM_FSI | UNICAM_LCI) && !(ista & UNICAM_FEI)) {\n-\t\tfor (i = 0; i < num_nodes_streaming; i++) {\n-\t\t\tspin_lock(&unicam->node[i].dma_queue_lock);\n-\t\t\tif (!list_empty(&unicam->node[i].dma_queue.active) &&\n-\t\t\t    !unicam->node[i].next_frm)\n-\t\t\t\tunicam_schedule_next_buffer(&unicam->node[i]);\n-\t\t\tspin_unlock(&unicam->node[i].dma_queue_lock);\n-\t\t}\n-\t}\n-\n-\tif (reg_read(&unicam->cfg, UNICAM_ICTL) & UNICAM_FCM) {\n-\t\t/* Switch out of trigger mode if selected */\n-\t\treg_write_field(&unicam->cfg, UNICAM_ICTL, 1, UNICAM_TFC);\n-\t\treg_write_field(&unicam->cfg, UNICAM_ICTL, 0, UNICAM_FCM);\n-\t}\n-\treturn IRQ_HANDLED;\n-}\n-\n-static int unicam_querycap(struct file *file, void *priv,\n-\t\t\t   struct v4l2_capability *cap)\n-{\n-\tstruct unicam_node *node = video_drvdata(file);\n-\tstruct unicam_device *dev = node->dev;\n-\n-\tstrlcpy(cap->driver, UNICAM_MODULE_NAME, sizeof(cap->driver));\n-\tstrlcpy(cap->card, UNICAM_MODULE_NAME, sizeof(cap->card));\n-\n-\tsnprintf(cap->bus_info, sizeof(cap->bus_info),\n-\t\t \"platform:%s\", dev->v4l2_dev.name);\n-\n-\tcap->capabilities = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING |\n-\t\t\t    V4L2_CAP_READWRITE | V4L2_CAP_DEVICE_CAPS |\n-\t\t\t    V4L2_CAP_META_CAPTURE;\n-\n-\tif (node->pad_id == IMAGE_PAD)\n-\t\tcap->device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING;\n-\telse\n-\t\tcap->device_caps = V4L2_CAP_META_CAPTURE | V4L2_CAP_STREAMING;\n-\n-\treturn 0;\n-}\n-\n-static int unicam_enum_fmt_vid_cap(struct file *file, void  *priv,\n-\t\t\t\t   struct v4l2_fmtdesc *f)\n-{\n-\tstruct unicam_node *node = video_drvdata(file);\n-\tstruct unicam_device *dev = node->dev;\n-\tstruct v4l2_subdev_mbus_code_enum mbus_code;\n-\tconst struct unicam_fmt *fmt = NULL;\n-\tint index = 0;\n-\tint ret = 0;\n-\tint i;\n-\n-\tif (node->pad_id == METADATA_PAD)\n-\t\treturn -EINVAL;\n-\n-\tfor (i = 0; !ret && i < MAX_ENUM_MBUS_CODE; i++) {\n-\t\tmemset(&mbus_code, 0, sizeof(mbus_code));\n-\t\tmbus_code.index = i;\n-\t\tmbus_code.pad = IMAGE_PAD;\n-\t\tmbus_code.which = V4L2_SUBDEV_FORMAT_ACTIVE;\n-\n-\t\tret = v4l2_subdev_call(dev->sensor, pad, enum_mbus_code,\n-\t\t\t\t       NULL, &mbus_code);\n-\t\tif (ret < 0) {\n-\t\t\tunicam_dbg(2, dev,\n-\t\t\t\t   \"subdev->enum_mbus_code idx %d returned %d - index invalid\\n\",\n-\t\t\t\t   i, ret);\n-\t\t\treturn -EINVAL;\n-\t\t}\n-\n-\t\tfmt = find_format_by_code(mbus_code.code);\n-\t\tif (fmt) {\n-\t\t\tif (fmt->fourcc) {\n-\t\t\t\tif (index == f->index) {\n-\t\t\t\t\tf->pixelformat = fmt->fourcc;\n-\t\t\t\t\tbreak;\n-\t\t\t\t}\n-\t\t\t\tindex++;\n-\t\t\t}\n-\t\t\tif (fmt->repacked_fourcc) {\n-\t\t\t\tif (index == f->index) {\n-\t\t\t\t\tf->pixelformat = fmt->repacked_fourcc;\n-\t\t\t\t\tbreak;\n-\t\t\t\t}\n-\t\t\t\tindex++;\n-\t\t\t}\n-\t\t}\n-\t}\n-\n-\treturn 0;\n-}\n-\n-static int unicam_g_fmt_vid_cap(struct file *file, void *priv,\n-\t\t\t\tstruct v4l2_format *f)\n-{\n-\tstruct v4l2_mbus_framefmt mbus_fmt = {0};\n-\tstruct unicam_node *node = video_drvdata(file);\n-\tstruct unicam_device *dev = node->dev;\n-\tconst struct unicam_fmt *fmt = NULL;\n-\tint ret;\n-\n-\tif (node->pad_id != IMAGE_PAD)\n-\t\treturn -EINVAL;\n-\n-\t/*\n-\t * If a flip has occurred in the sensor, the fmt code might have\n-\t * changed. So we will need to re-fetch the format from the subdevice.\n-\t */\n-\tret = __subdev_get_format(dev, &mbus_fmt, node->pad_id);\n-\tif (ret)\n-\t\treturn -EINVAL;\n-\n-\t/* Find the V4L2 format from mbus code. We must match a known format. */\n-\tfmt = find_format_by_code(mbus_fmt.code);\n-\tif (!fmt)\n-\t\treturn -EINVAL;\n-\n-\tif (node->fmt != fmt) {\n-\t\t/*\n-\t\t * The sensor format has changed so the pixelformat needs to\n-\t\t * be updated. Try and retain the packed/unpacked choice if\n-\t\t * at all possible.\n-\t\t */\n-\t\tif (node->fmt->repacked_fourcc ==\n-\t\t\t\t\t\tnode->v_fmt.fmt.pix.pixelformat)\n-\t\t\t/* Using the repacked format */\n-\t\t\tnode->v_fmt.fmt.pix.pixelformat = fmt->repacked_fourcc;\n-\t\telse\n-\t\t\t/* Using the native format */\n-\t\t\tnode->v_fmt.fmt.pix.pixelformat = fmt->fourcc;\n-\n-\t\tnode->fmt = fmt;\n-\t}\n-\n-\t*f = node->v_fmt;\n-\n-\treturn 0;\n-}\n-\n-static\n-const struct unicam_fmt *get_first_supported_format(struct unicam_device *dev)\n-{\n-\tstruct v4l2_subdev_mbus_code_enum mbus_code;\n-\tconst struct unicam_fmt *fmt = NULL;\n-\tint ret = 0;\n-\tint j;\n-\n-\tfor (j = 0; ret != -EINVAL && ret != -ENOIOCTLCMD; ++j) {\n-\t\tmemset(&mbus_code, 0, sizeof(mbus_code));\n-\t\tmbus_code.index = j;\n-\t\tmbus_code.pad = IMAGE_PAD;\n-\t\tmbus_code.which = V4L2_SUBDEV_FORMAT_ACTIVE;\n-\n-\t\tret = v4l2_subdev_call(dev->sensor, pad, enum_mbus_code, NULL,\n-\t\t\t\t       &mbus_code);\n-\t\tif (ret < 0) {\n-\t\t\tunicam_dbg(2, dev,\n-\t\t\t\t   \"subdev->enum_mbus_code idx %d returned %d - continue\\n\",\n-\t\t\t\t   j, ret);\n-\t\t\tcontinue;\n-\t\t}\n-\n-\t\tunicam_dbg(2, dev, \"subdev %s: code: 0x%08x idx: %d\\n\",\n-\t\t\t   dev->sensor->name, mbus_code.code, j);\n-\n-\t\tfmt = find_format_by_code(mbus_code.code);\n-\t\tunicam_dbg(2, dev, \"fmt 0x%08x returned as %p, V4L2 FOURCC 0x%08x, csi_dt 0x%02x\\n\",\n-\t\t\t   mbus_code.code, fmt, fmt ? fmt->fourcc : 0,\n-\t\t\t   fmt ? fmt->csi_dt : 0);\n-\t\tif (fmt)\n-\t\t\treturn fmt;\n-\t}\n-\n-\treturn NULL;\n-}\n-\n-static int unicam_try_fmt_vid_cap(struct file *file, void *priv,\n-\t\t\t\t  struct v4l2_format *f)\n-{\n-\tstruct unicam_node *node = video_drvdata(file);\n-\tstruct unicam_device *dev = node->dev;\n-\tstruct v4l2_subdev_format sd_fmt = {\n-\t\t.which = V4L2_SUBDEV_FORMAT_TRY,\n-\t\t.pad = IMAGE_PAD\n-\t};\n-\tstruct v4l2_mbus_framefmt *mbus_fmt = &sd_fmt.format;\n-\tconst struct unicam_fmt *fmt;\n-\tint ret;\n-\n-\tif (node->pad_id == METADATA_PAD)\n-\t\treturn -EINVAL;\n-\n-\tfmt = find_format_by_pix(dev, f->fmt.pix.pixelformat);\n-\tif (!fmt) {\n-\t\t/* Pixel format not supported by unicam. Choose the first\n-\t\t * supported format, and let the sensor choose something else.\n-\t\t */\n-\t\tunicam_dbg(3, dev, \"Fourcc format (0x%08x) not found. Use first format.\\n\",\n-\t\t\t   f->fmt.pix.pixelformat);\n-\n-\t\tfmt = &formats[0];\n-\t\tf->fmt.pix.pixelformat = fmt->fourcc;\n-\t}\n-\n-\tv4l2_fill_mbus_format(mbus_fmt, &f->fmt.pix, fmt->code);\n-\t/*\n-\t * No support for receiving interlaced video, so never\n-\t * request it from the sensor subdev.\n-\t */\n-\tmbus_fmt->field = V4L2_FIELD_NONE;\n-\n-\tret = v4l2_subdev_call(dev->sensor, pad, set_fmt, dev->sensor_config,\n-\t\t\t       &sd_fmt);\n-\tif (ret && ret != -ENOIOCTLCMD && ret != -ENODEV)\n-\t\treturn ret;\n-\n-\tif (mbus_fmt->field != V4L2_FIELD_NONE)\n-\t\tunicam_info(dev, \"Sensor trying to send interlaced video - results may be unpredictable\\n\");\n-\n-\tv4l2_fill_pix_format(&f->fmt.pix, &sd_fmt.format);\n-\tif (mbus_fmt->code != fmt->code) {\n-\t\t/* Sensor has returned an alternate format */\n-\t\tfmt = find_format_by_code(mbus_fmt->code);\n-\t\tif (!fmt) {\n-\t\t\t/* The alternate format is one unicam can't support.\n-\t\t\t * Find the first format that is supported by both, and\n-\t\t\t * then set that.\n-\t\t\t */\n-\t\t\tfmt = get_first_supported_format(dev);\n-\t\t\tmbus_fmt->code = fmt->code;\n-\n-\t\t\tret = v4l2_subdev_call(dev->sensor, pad, set_fmt,\n-\t\t\t\t\t       dev->sensor_config, &sd_fmt);\n-\t\t\tif (ret && ret != -ENOIOCTLCMD && ret != -ENODEV)\n-\t\t\t\treturn ret;\n-\n-\t\t\tif (mbus_fmt->field != V4L2_FIELD_NONE)\n-\t\t\t\tunicam_info(dev, \"Sensor trying to send interlaced video - results may be unpredictable\\n\");\n-\n-\t\t\tv4l2_fill_pix_format(&f->fmt.pix, &sd_fmt.format);\n-\n-\t\t\tif (mbus_fmt->code != fmt->code) {\n-\t\t\t\t/* We've set a format that the sensor reports\n-\t\t\t\t * as being supported, but it refuses to set it.\n-\t\t\t\t * Not much else we can do.\n-\t\t\t\t * Assume that the sensor driver may accept the\n-\t\t\t\t * format when it is set (rather than tried).\n-\t\t\t\t */\n-\t\t\t\tunicam_err(dev, \"Sensor won't accept default format, and Unicam can't support sensor default\\n\");\n-\t\t\t}\n-\t\t}\n-\n-\t\tif (fmt->fourcc)\n-\t\t\tf->fmt.pix.pixelformat = fmt->fourcc;\n-\t\telse\n-\t\t\tf->fmt.pix.pixelformat = fmt->repacked_fourcc;\n-\t}\n-\n-\treturn unicam_calc_format_size_bpl(dev, fmt, f);\n-}\n-\n-static int unicam_s_fmt_vid_cap(struct file *file, void *priv,\n-\t\t\t\tstruct v4l2_format *f)\n-{\n-\tstruct unicam_node *node = video_drvdata(file);\n-\tstruct unicam_device *dev = node->dev;\n-\tstruct vb2_queue *q = &node->buffer_queue;\n-\tstruct v4l2_mbus_framefmt mbus_fmt = {0};\n-\tconst struct unicam_fmt *fmt;\n-\tint ret;\n-\n-\tif (vb2_is_busy(q))\n-\t\treturn -EBUSY;\n-\n-\tret = unicam_try_fmt_vid_cap(file, priv, f);\n-\tif (ret < 0)\n-\t\treturn ret;\n-\n-\tfmt = find_format_by_pix(dev, f->fmt.pix.pixelformat);\n-\tif (!fmt) {\n-\t\t/* Unknown pixel format - adopt a default.\n-\t\t * This shouldn't happen as try_fmt should have resolved any\n-\t\t * issues first.\n-\t\t */\n-\t\tfmt = get_first_supported_format(dev);\n-\t\tif (!fmt)\n-\t\t\t/* It shouldn't be possible to get here with no\n-\t\t\t * supported formats\n-\t\t\t */\n-\t\t\treturn -EINVAL;\n-\t\tf->fmt.pix.pixelformat = fmt->fourcc;\n-\t\treturn -EINVAL;\n-\t}\n-\n-\tv4l2_fill_mbus_format(&mbus_fmt, &f->fmt.pix, fmt->code);\n-\n-\tret = __subdev_set_format(dev, &mbus_fmt, node->pad_id);\n-\tif (ret) {\n-\t\tunicam_dbg(3, dev, \"%s __subdev_set_format failed %d\\n\",\n-\t\t\t   __func__, ret);\n-\t\treturn ret;\n-\t}\n-\n-\t/* Just double check nothing has gone wrong */\n-\tif (mbus_fmt.code != fmt->code) {\n-\t\tunicam_dbg(3, dev,\n-\t\t\t   \"%s subdev changed format on us, this should not happen\\n\",\n-\t\t\t   __func__);\n-\t\treturn -EINVAL;\n-\t}\n-\n-\tnode->fmt = fmt;\n-\tnode->v_fmt.fmt.pix.pixelformat = f->fmt.pix.pixelformat;\n-\tnode->v_fmt.fmt.pix.bytesperline = f->fmt.pix.bytesperline;\n-\tunicam_reset_format(node);\n-\n-\tunicam_dbg(3, dev,\n-\t\t   \"%s %dx%d, mbus_fmt 0x%08X, V4L2 pix 0x%08X.\\n\",\n-\t\t   __func__, node->v_fmt.fmt.pix.width,\n-\t\t   node->v_fmt.fmt.pix.height, mbus_fmt.code,\n-\t\t   node->v_fmt.fmt.pix.pixelformat);\n-\n-\t*f = node->v_fmt;\n-\n-\treturn 0;\n-}\n-\n-static int unicam_enum_fmt_meta_cap(struct file *file, void *priv,\n-\t\t\t\t    struct v4l2_fmtdesc *f)\n-{\n-\tstruct unicam_node *node = video_drvdata(file);\n-\tstruct unicam_device *dev = node->dev;\n-\tstruct v4l2_subdev_mbus_code_enum mbus_code;\n-\tconst struct unicam_fmt *fmt = NULL;\n-\tint ret = 0;\n-\n-\tif (node->pad_id != METADATA_PAD || f->index != 0)\n-\t\treturn -EINVAL;\n-\n-\tif (dev->sensor_embedded_data) {\n-\t\tmemset(&mbus_code, 0, sizeof(mbus_code));\n-\t\tmbus_code.index = f->index;\n-\t\tmbus_code.which = V4L2_SUBDEV_FORMAT_ACTIVE;\n-\t\tmbus_code.pad = METADATA_PAD;\n-\n-\t\tret = v4l2_subdev_call(dev->sensor, pad, enum_mbus_code, NULL,\n-\t\t\t\t       &mbus_code);\n-\t\tif (ret < 0) {\n-\t\t\tunicam_dbg(2, dev,\n-\t\t\t\t   \"subdev->enum_mbus_code idx 0 returned %d - index invalid\\n\",\n-\t\t\t\t   ret);\n-\t\t\treturn -EINVAL;\n-\t\t}\n-\t} else {\n-\t\tmbus_code.code = MEDIA_BUS_FMT_SENSOR_DATA;\n-\t}\n-\n-\tfmt = find_format_by_code(mbus_code.code);\n-\tif (fmt)\n-\t\tf->pixelformat = fmt->fourcc;\n-\n-\treturn 0;\n-}\n-\n-static int unicam_g_fmt_meta_cap(struct file *file, void *priv,\n-\t\t\t\t struct v4l2_format *f)\n-{\n-\tstruct unicam_node *node = video_drvdata(file);\n-\n-\tif (node->pad_id != METADATA_PAD)\n-\t\treturn -EINVAL;\n-\n-\t*f = node->v_fmt;\n-\n-\treturn 0;\n-}\n-\n-static int unicam_try_fmt_meta_cap(struct file *file, void *priv,\n-\t\t\t\t   struct v4l2_format *f)\n-{\n-\tstruct unicam_node *node = video_drvdata(file);\n-\n-\tif (node->pad_id != METADATA_PAD)\n-\t\treturn -EINVAL;\n-\n-\t*f = node->v_fmt;\n-\n-\treturn 0;\n-}\n-\n-static int unicam_s_fmt_meta_cap(struct file *file, void *priv,\n-\t\t\t\t struct v4l2_format *f)\n-{\n-\tstruct unicam_node *node = video_drvdata(file);\n-\tstruct unicam_device *dev = node->dev;\n-\tstruct v4l2_mbus_framefmt mbus_fmt = { 0 };\n-\tconst struct unicam_fmt *fmt;\n-\tint ret;\n-\n-\tif (node->pad_id == IMAGE_PAD)\n-\t\treturn -EINVAL;\n-\n-\tif (dev->sensor_embedded_data) {\n-\t\tfmt = find_format_by_pix(dev, f->fmt.meta.dataformat);\n-\t\tif (!fmt) {\n-\t\t\tunicam_err(dev, \"unknown format: V4L2 pix 0x%08x\\n\",\n-\t\t\t\t   f->fmt.meta.dataformat);\n-\t\t\treturn -EINVAL;\n-\t\t}\n-\t\tmbus_fmt.code = fmt->code;\n-\t\tret = __subdev_set_format(dev, &mbus_fmt, node->pad_id);\n-\t\tif (ret) {\n-\t\t\tunicam_dbg(3, dev, \"%s __subdev_set_format failed %d\\n\",\n-\t\t\t\t   __func__, ret);\n-\t\t\treturn ret;\n-\t\t}\n-\t}\n-\n-\t*f = node->v_fmt;\n-\n-\tunicam_dbg(3, dev, \"%s size %d, V4L2 pix 0x%08x\\n\",\n-\t\t   __func__, node->v_fmt.fmt.meta.buffersize,\n-\t\t   node->v_fmt.fmt.meta.dataformat);\n-\n-\treturn 0;\n-}\n-\n-static int unicam_queue_setup(struct vb2_queue *vq,\n-\t\t\t      unsigned int *nbuffers,\n-\t\t\t      unsigned int *nplanes,\n-\t\t\t      unsigned int sizes[],\n-\t\t\t      struct device *alloc_devs[])\n-{\n-\tstruct unicam_node *node = vb2_get_drv_priv(vq);\n-\tstruct unicam_device *dev = node->dev;\n-\tunsigned int size = node->pad_id == IMAGE_PAD ?\n-\t\t\t\t    node->v_fmt.fmt.pix.sizeimage :\n-\t\t\t\t    node->v_fmt.fmt.meta.buffersize;\n-\n-\tif (vq->num_buffers + *nbuffers < 3)\n-\t\t*nbuffers = 3 - vq->num_buffers;\n-\n-\tif (*nplanes) {\n-\t\tif (sizes[0] < size) {\n-\t\t\tunicam_err(dev, \"sizes[0] %i < size %u\\n\", sizes[0],\n-\t\t\t\t   size);\n-\t\t\treturn -EINVAL;\n-\t\t}\n-\t\tsize = sizes[0];\n-\t}\n-\n-\t*nplanes = 1;\n-\tsizes[0] = size;\n-\n-\treturn 0;\n-}\n-\n-static int unicam_buffer_prepare(struct vb2_buffer *vb)\n-{\n-\tstruct unicam_node *node = vb2_get_drv_priv(vb->vb2_queue);\n-\tstruct unicam_device *dev = node->dev;\n-\tstruct unicam_buffer *buf = container_of(vb, struct unicam_buffer,\n-\t\t\t\t\t      vb.vb2_buf);\n-\tunsigned long size;\n-\n-\tif (WARN_ON(!node->fmt))\n-\t\treturn -EINVAL;\n-\n-\tsize = node->pad_id == IMAGE_PAD ? node->v_fmt.fmt.pix.sizeimage :\n-\t\t\t\t\t   node->v_fmt.fmt.meta.buffersize;\n-\tif (vb2_plane_size(vb, 0) < size) {\n-\t\tunicam_err(dev, \"data will not fit into plane (%lu < %lu)\\n\",\n-\t\t\t   vb2_plane_size(vb, 0), size);\n-\t\treturn -EINVAL;\n-\t}\n-\n-\tvb2_set_plane_payload(&buf->vb.vb2_buf, 0, size);\n-\treturn 0;\n-}\n-\n-static void unicam_buffer_queue(struct vb2_buffer *vb)\n-{\n-\tstruct unicam_node *node = vb2_get_drv_priv(vb->vb2_queue);\n-\tstruct unicam_buffer *buf = container_of(vb, struct unicam_buffer,\n-\t\t\t\t\t      vb.vb2_buf);\n-\tstruct unicam_dmaqueue *dma_queue = &node->dma_queue;\n-\tunsigned long flags = 0;\n-\n-\tspin_lock_irqsave(&node->dma_queue_lock, flags);\n-\tlist_add_tail(&buf->list, &dma_queue->active);\n-\tspin_unlock_irqrestore(&node->dma_queue_lock, flags);\n-}\n-\n-static void unicam_set_packing_config(struct unicam_device *dev)\n-{\n-\tint pack, unpack;\n-\tu32 val;\n-\n-\tif (dev->node[IMAGE_PAD].v_fmt.fmt.pix.pixelformat ==\n-\t    dev->node[IMAGE_PAD].fmt->fourcc) {\n-\t\tunpack = UNICAM_PUM_NONE;\n-\t\tpack = UNICAM_PPM_NONE;\n-\t} else {\n-\t\tswitch (dev->node[IMAGE_PAD].fmt->depth) {\n-\t\tcase 8:\n-\t\t\tunpack = UNICAM_PUM_UNPACK8;\n-\t\t\tbreak;\n-\t\tcase 10:\n-\t\t\tunpack = UNICAM_PUM_UNPACK10;\n-\t\t\tbreak;\n-\t\tcase 12:\n-\t\t\tunpack = UNICAM_PUM_UNPACK12;\n-\t\t\tbreak;\n-\t\tcase 14:\n-\t\t\tunpack = UNICAM_PUM_UNPACK14;\n-\t\t\tbreak;\n-\t\tcase 16:\n-\t\t\tunpack = UNICAM_PUM_UNPACK16;\n-\t\t\tbreak;\n-\t\tdefault:\n-\t\t\tunpack = UNICAM_PUM_NONE;\n-\t\t\tbreak;\n-\t\t}\n-\n-\t\t/* Repacking is always to 16bpp */\n-\t\tpack = UNICAM_PPM_PACK16;\n-\t}\n-\n-\tval = 0;\n-\tset_field(&val, unpack, UNICAM_PUM_MASK);\n-\tset_field(&val, pack, UNICAM_PPM_MASK);\n-\treg_write(&dev->cfg, UNICAM_IPIPE, val);\n-}\n-\n-static void unicam_cfg_image_id(struct unicam_device *dev)\n-{\n-\tstruct unicam_cfg *cfg = &dev->cfg;\n-\n-\tif (dev->bus_type == V4L2_MBUS_CSI2_DPHY) {\n-\t\t/* CSI2 mode */\n-\t\treg_write(cfg, UNICAM_IDI0,\n-\t\t\t  (dev->virtual_channel << 6) |\n-\t\t\t\t\t      dev->node[IMAGE_PAD].fmt->csi_dt);\n-\t} else {\n-\t\t/* CCP2 mode */\n-\t\treg_write(cfg, UNICAM_IDI0,\n-\t\t\t  0x80 | dev->node[IMAGE_PAD].fmt->csi_dt);\n-\t}\n-}\n-\n-static void unicam_enable_ed(struct unicam_device *dev)\n-{\n-\tstruct unicam_cfg *cfg = &dev->cfg;\n-\tu32 val = reg_read(cfg, UNICAM_DCS);\n-\n-\tset_field(&val, 2, UNICAM_EDL_MASK);\n-\t/* Do not wrap at the end of the embedded data buffer */\n-\tset_field(&val, 0, UNICAM_DBOB);\n-\n-\treg_write(cfg, UNICAM_DCS, val);\n-}\n-\n-static void unicam_start_rx(struct unicam_device *dev, dma_addr_t *addr)\n-{\n-\tstruct unicam_cfg *cfg = &dev->cfg;\n-\tint line_int_freq = dev->node[IMAGE_PAD].v_fmt.fmt.pix.height >> 2;\n-\tunsigned int size, i;\n-\tu32 val;\n-\n-\tif (line_int_freq < 128)\n-\t\tline_int_freq = 128;\n-\n-\t/* Enable lane clocks */\n-\tval = 1;\n-\tfor (i = 0; i < dev->active_data_lanes; i++)\n-\t\tval = val << 2 | 1;\n-\tclk_write(cfg, val);\n-\n-\t/* Basic init */\n-\treg_write(cfg, UNICAM_CTRL, UNICAM_MEM);\n-\n-\t/* Enable analogue control, and leave in reset. */\n-\tval = UNICAM_AR;\n-\tset_field(&val, 7, UNICAM_CTATADJ_MASK);\n-\tset_field(&val, 7, UNICAM_PTATADJ_MASK);\n-\treg_write(cfg, UNICAM_ANA, val);\n-\tusleep_range(1000, 2000);\n-\n-\t/* Come out of reset */\n-\treg_write_field(cfg, UNICAM_ANA, 0, UNICAM_AR);\n-\n-\t/* Peripheral reset */\n-\treg_write_field(cfg, UNICAM_CTRL, 1, UNICAM_CPR);\n-\treg_write_field(cfg, UNICAM_CTRL, 0, UNICAM_CPR);\n-\n-\treg_write_field(cfg, UNICAM_CTRL, 0, UNICAM_CPE);\n-\n-\t/* Enable Rx control. */\n-\tval = reg_read(cfg, UNICAM_CTRL);\n-\tif (dev->bus_type == V4L2_MBUS_CSI2_DPHY) {\n-\t\tset_field(&val, UNICAM_CPM_CSI2, UNICAM_CPM_MASK);\n-\t\tset_field(&val, UNICAM_DCM_STROBE, UNICAM_DCM_MASK);\n-\t} else {\n-\t\tset_field(&val, UNICAM_CPM_CCP2, UNICAM_CPM_MASK);\n-\t\tset_field(&val, dev->bus_flags, UNICAM_DCM_MASK);\n-\t}\n-\t/* Packet framer timeout */\n-\tset_field(&val, 0xf, UNICAM_PFT_MASK);\n-\tset_field(&val, 128, UNICAM_OET_MASK);\n-\treg_write(cfg, UNICAM_CTRL, val);\n-\n-\treg_write(cfg, UNICAM_IHWIN, 0);\n-\treg_write(cfg, UNICAM_IVWIN, 0);\n-\n-\t/* AXI bus access QoS setup */\n-\tval = reg_read(&dev->cfg, UNICAM_PRI);\n-\tset_field(&val, 0, UNICAM_BL_MASK);\n-\tset_field(&val, 0, UNICAM_BS_MASK);\n-\tset_field(&val, 0xe, UNICAM_PP_MASK);\n-\tset_field(&val, 8, UNICAM_NP_MASK);\n-\tset_field(&val, 2, UNICAM_PT_MASK);\n-\tset_field(&val, 1, UNICAM_PE);\n-\treg_write(cfg, UNICAM_PRI, val);\n-\n-\treg_write_field(cfg, UNICAM_ANA, 0, UNICAM_DDL);\n-\n-\t/* Always start in trigger frame capture mode (UNICAM_FCM set) */\n-\tval = UNICAM_FSIE | UNICAM_FEIE | UNICAM_FCM | UNICAM_IBOB;\n-\tset_field(&val,  line_int_freq, UNICAM_LCIE_MASK);\n-\treg_write(cfg, UNICAM_ICTL, val);\n-\treg_write(cfg, UNICAM_STA, UNICAM_STA_MASK_ALL);\n-\treg_write(cfg, UNICAM_ISTA, UNICAM_ISTA_MASK_ALL);\n-\n-\t/* tclk_term_en */\n-\treg_write_field(cfg, UNICAM_CLT, 2, UNICAM_CLT1_MASK);\n-\t/* tclk_settle */\n-\treg_write_field(cfg, UNICAM_CLT, 6, UNICAM_CLT2_MASK);\n-\t/* td_term_en */\n-\treg_write_field(cfg, UNICAM_DLT, 2, UNICAM_DLT1_MASK);\n-\t/* ths_settle */\n-\treg_write_field(cfg, UNICAM_DLT, 6, UNICAM_DLT2_MASK);\n-\t/* trx_enable */\n-\treg_write_field(cfg, UNICAM_DLT, 0, UNICAM_DLT3_MASK);\n-\n-\treg_write_field(cfg, UNICAM_CTRL, 0, UNICAM_SOE);\n-\n-\t/* Packet compare setup - required to avoid missing frame ends */\n-\tval = 0;\n-\tset_field(&val, 1, UNICAM_PCE);\n-\tset_field(&val, 1, UNICAM_GI);\n-\tset_field(&val, 1, UNICAM_CPH);\n-\tset_field(&val, 0, UNICAM_PCVC_MASK);\n-\tset_field(&val, 1, UNICAM_PCDT_MASK);\n-\treg_write(cfg, UNICAM_CMP0, val);\n-\n-\t/* Enable clock lane and set up terminations */\n-\tval = 0;\n-\tif (dev->bus_type == V4L2_MBUS_CSI2_DPHY) {\n-\t\t/* CSI2 */\n-\t\tset_field(&val, 1, UNICAM_CLE);\n-\t\tset_field(&val, 1, UNICAM_CLLPE);\n-\t\tif (dev->bus_flags & V4L2_MBUS_CSI2_CONTINUOUS_CLOCK) {\n-\t\t\tset_field(&val, 1, UNICAM_CLTRE);\n-\t\t\tset_field(&val, 1, UNICAM_CLHSE);\n-\t\t}\n-\t} else {\n-\t\t/* CCP2 */\n-\t\tset_field(&val, 1, UNICAM_CLE);\n-\t\tset_field(&val, 1, UNICAM_CLHSE);\n-\t\tset_field(&val, 1, UNICAM_CLTRE);\n-\t}\n-\treg_write(cfg, UNICAM_CLK, val);\n-\n-\t/*\n-\t * Enable required data lanes with appropriate terminations.\n-\t * The same value needs to be written to UNICAM_DATn registers for\n-\t * the active lanes, and 0 for inactive ones.\n-\t */\n-\tval = 0;\n-\tif (dev->bus_type == V4L2_MBUS_CSI2_DPHY) {\n-\t\t/* CSI2 */\n-\t\tset_field(&val, 1, UNICAM_DLE);\n-\t\tset_field(&val, 1, UNICAM_DLLPE);\n-\t\tif (dev->bus_flags & V4L2_MBUS_CSI2_CONTINUOUS_CLOCK) {\n-\t\t\tset_field(&val, 1, UNICAM_DLTRE);\n-\t\t\tset_field(&val, 1, UNICAM_DLHSE);\n-\t\t}\n-\t} else {\n-\t\t/* CCP2 */\n-\t\tset_field(&val, 1, UNICAM_DLE);\n-\t\tset_field(&val, 1, UNICAM_DLHSE);\n-\t\tset_field(&val, 1, UNICAM_DLTRE);\n-\t}\n-\treg_write(cfg, UNICAM_DAT0, val);\n-\n-\tif (dev->active_data_lanes == 1)\n-\t\tval = 0;\n-\treg_write(cfg, UNICAM_DAT1, val);\n-\n-\tif (dev->max_data_lanes > 2) {\n-\t\t/*\n-\t\t * Registers UNICAM_DAT2 and UNICAM_DAT3 only valid if the\n-\t\t * instance supports more than 2 data lanes.\n-\t\t */\n-\t\tif (dev->active_data_lanes == 2)\n-\t\t\tval = 0;\n-\t\treg_write(cfg, UNICAM_DAT2, val);\n-\n-\t\tif (dev->active_data_lanes == 3)\n-\t\t\tval = 0;\n-\t\treg_write(cfg, UNICAM_DAT3, val);\n-\t}\n-\n-\treg_write(&dev->cfg, UNICAM_IBLS,\n-\t\t  dev->node[IMAGE_PAD].v_fmt.fmt.pix.bytesperline);\n-\tsize = dev->node[IMAGE_PAD].v_fmt.fmt.pix.sizeimage;\n-\tunicam_wr_dma_addr(&dev->cfg, addr[IMAGE_PAD], size, IMAGE_PAD);\n-\tunicam_set_packing_config(dev);\n-\tunicam_cfg_image_id(dev);\n-\n-\tval = reg_read(cfg, UNICAM_MISC);\n-\tset_field(&val, 1, UNICAM_FL0);\n-\tset_field(&val, 1, UNICAM_FL1);\n-\treg_write(cfg, UNICAM_MISC, val);\n-\n-\tif (dev->node[METADATA_PAD].streaming && dev->sensor_embedded_data) {\n-\t\tsize = dev->node[METADATA_PAD].v_fmt.fmt.meta.buffersize;\n-\t\tunicam_enable_ed(dev);\n-\t\tunicam_wr_dma_addr(&dev->cfg, addr[METADATA_PAD], size,\n-\t\t\t\t   METADATA_PAD);\n-\t}\n-\n-\t/* Enable peripheral */\n-\treg_write_field(cfg, UNICAM_CTRL, 1, UNICAM_CPE);\n-\n-\t/* Load image pointers */\n-\treg_write_field(cfg, UNICAM_ICTL, 1, UNICAM_LIP_MASK);\n-\n-\t/* Load embedded data buffer pointers if needed */\n-\tif (dev->node[METADATA_PAD].streaming && dev->sensor_embedded_data)\n-\t\treg_write_field(cfg, UNICAM_DCS, 1, UNICAM_LDP);\n-\n-\t/*\n-\t * Enable trigger only for the first frame to\n-\t * sync correctly to the FS from the source.\n-\t */\n-\treg_write_field(cfg, UNICAM_ICTL, 1, UNICAM_TFC);\n-}\n-\n-static void unicam_disable(struct unicam_device *dev)\n-{\n-\tstruct unicam_cfg *cfg = &dev->cfg;\n-\n-\t/* Analogue lane control disable */\n-\treg_write_field(cfg, UNICAM_ANA, 1, UNICAM_DDL);\n-\n-\t/* Stop the output engine */\n-\treg_write_field(cfg, UNICAM_CTRL, 1, UNICAM_SOE);\n-\n-\t/* Disable the data lanes. */\n-\treg_write(cfg, UNICAM_DAT0, 0);\n-\treg_write(cfg, UNICAM_DAT1, 0);\n-\n-\tif (dev->max_data_lanes > 2) {\n-\t\treg_write(cfg, UNICAM_DAT2, 0);\n-\t\treg_write(cfg, UNICAM_DAT3, 0);\n-\t}\n-\n-\t/* Peripheral reset */\n-\treg_write_field(cfg, UNICAM_CTRL, 1, UNICAM_CPR);\n-\tusleep_range(50, 100);\n-\treg_write_field(cfg, UNICAM_CTRL, 0, UNICAM_CPR);\n-\n-\t/* Disable peripheral */\n-\treg_write_field(cfg, UNICAM_CTRL, 0, UNICAM_CPE);\n-\n-\t/* Clear ED setup */\n-\treg_write(cfg, UNICAM_DCS, 0);\n-\n-\t/* Disable all lane clocks */\n-\tclk_write(cfg, 0);\n-}\n-\n-static int unicam_start_streaming(struct vb2_queue *vq, unsigned int count)\n-{\n-\tstruct unicam_node *node = vb2_get_drv_priv(vq);\n-\tstruct unicam_device *dev = node->dev;\n-\tstruct unicam_buffer *buf;\n-\tdma_addr_t buffer_addr[MAX_NODES] = { 0 };\n-\tint num_nodes_streaming;\n-\tunsigned long flags;\n-\tint ret, i;\n-\n-\tnode->streaming = 1;\n-\tif (!unicam_all_nodes_streaming(dev)) {\n-\t\tunicam_dbg(3, dev, \"Not all nodes are streaming yet.\");\n-\t\treturn 0;\n-\t}\n-\n-\tdev->sequence = 0;\n-\tret = unicam_runtime_get(dev);\n-\tif (ret < 0) {\n-\t\tunicam_dbg(3, dev, \"unicam_runtime_get failed\\n\");\n-\t\treturn ret;\n-\t}\n-\n-\tdev->active_data_lanes = dev->max_data_lanes;\n-\tif (dev->bus_type == V4L2_MBUS_CSI2_DPHY &&\n-\t    v4l2_subdev_has_op(dev->sensor, video, g_mbus_config)) {\n-\t\tstruct v4l2_mbus_config mbus_config;\n-\n-\t\tret = v4l2_subdev_call(dev->sensor, video, g_mbus_config,\n-\t\t\t\t       &mbus_config);\n-\t\tif (ret < 0) {\n-\t\t\tunicam_dbg(3, dev, \"g_mbus_config failed\\n\");\n-\t\t\tgoto err_pm_put;\n-\t\t}\n-\n-\t\tdev->active_data_lanes =\n-\t\t\t(mbus_config.flags & V4L2_MBUS_CSI2_LANE_MASK) >>\n-\t\t\t\t\t__ffs(V4L2_MBUS_CSI2_LANE_MASK);\n-\t\tif (!dev->active_data_lanes)\n-\t\t\tdev->active_data_lanes = dev->max_data_lanes;\n-\t}\n-\tif (dev->active_data_lanes > dev->max_data_lanes) {\n-\t\tunicam_err(dev,\t\"Device has requested %u data lanes, which is >%u configured in DT\\n\",\n-\t\t\t   dev->active_data_lanes, dev->max_data_lanes);\n-\t\tret = -EINVAL;\n-\t\tgoto err_pm_put;\n-\t}\n-\n-\tunicam_dbg(1, dev, \"Running with %u data lanes\\n\",\n-\t\t   dev->active_data_lanes);\n-\n-\tret = clk_set_rate(dev->clock, 100 * 1000 * 1000);\n-\tif (ret) {\n-\t\tunicam_err(dev, \"failed to set up clock\\n\");\n-\t\tgoto err_pm_put;\n-\t}\n-\n-\tret = clk_prepare_enable(dev->clock);\n-\tif (ret) {\n-\t\tunicam_err(dev, \"Failed to enable CSI clock: %d\\n\", ret);\n-\t\tgoto err_pm_put;\n-\t}\n-\n-\tnum_nodes_streaming = unicam_num_nodes_streaming(dev);\n-\tfor (i = 0; i < num_nodes_streaming; i++) {\n-\t\tspin_lock_irqsave(&dev->node[i].dma_queue_lock, flags);\n-\t\tbuf = list_entry(dev->node[i].dma_queue.active.next,\n-\t\t\t\t struct unicam_buffer, list);\n-\t\tdev->node[i].cur_frm = buf;\n-\t\tdev->node[i].next_frm = buf;\n-\t\tlist_del(&buf->list);\n-\t\tspin_unlock_irqrestore(&dev->node[i].dma_queue_lock, flags);\n-\t\tbuffer_addr[i] =\n-\t\tvb2_dma_contig_plane_dma_addr(&dev->node[i].cur_frm->vb.vb2_buf,\n-\t\t\t\t\t      0);\n-\t}\n-\n-\tunicam_start_rx(dev, buffer_addr);\n-\n-\tret = v4l2_subdev_call(dev->sensor, video, s_stream, 1);\n-\tif (ret < 0) {\n-\t\tunicam_err(dev, \"stream on failed in subdev\\n\");\n-\t\tgoto err_disable_unicam;\n-\t}\n-\n-\treturn 0;\n-\n-err_disable_unicam:\n-\tnode->streaming = 0;\n-\tunicam_disable(dev);\n-\tclk_disable_unprepare(dev->clock);\n-err_pm_put:\n-\tunicam_runtime_put(dev);\n-\n-\treturn ret;\n-}\n-\n-static void unicam_stop_streaming(struct vb2_queue *vq)\n-{\n-\tstruct unicam_node *node = vb2_get_drv_priv(vq);\n-\tstruct unicam_device *dev = node->dev;\n-\tstruct unicam_dmaqueue *dma_q = &node->dma_queue;\n-\tstruct unicam_buffer *buf, *tmp;\n-\tunsigned long flags;\n-\n-\tnode->streaming = 0;\n-\n-\tif (node->pad_id == IMAGE_PAD) {\n-\t\t/* Stop streaming the sensor and disable the peripheral.\n-\t\t * We cannot continue streaming embedded data with the\n-\t\t * image pad disabled.\n-\t\t */\n-\t\tif (v4l2_subdev_call(dev->sensor, video, s_stream, 0) < 0)\n-\t\t\tunicam_err(dev, \"stream off failed in subdev\\n\");\n-\n-\t\tunicam_disable(dev);\n-\t\tclk_disable_unprepare(dev->clock);\n-\t\tunicam_runtime_put(dev);\n-\n-\t} else if (node->pad_id == METADATA_PAD) {\n-\t\t/* Allow the hardware to spin in the dummy buffer.\n-\t\t * This is only really needed if the embedded data pad is\n-\t\t * disabled before the image pad.  The 0x3 in the top two bits\n-\t\t * signifies uncached accesses through the Videocore memory\n-\t\t * controller.\n-\t\t */\n-\t\tunicam_wr_dma_addr(&dev->cfg, node->dummy_buf_dma_addr,\n-\t\t\t\t   DUMMY_BUF_SIZE, METADATA_PAD);\n-\t}\n-\n-\t/* Clear all queued buffers for the node */\n-\tspin_lock_irqsave(&node->dma_queue_lock, flags);\n-\tlist_for_each_entry_safe(buf, tmp, &dma_q->active, list) {\n-\t\tlist_del(&buf->list);\n-\t\tvb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);\n-\t}\n-\n-\tif (node->cur_frm)\n-\t\tvb2_buffer_done(&node->cur_frm->vb.vb2_buf,\n-\t\t\t\tVB2_BUF_STATE_ERROR);\n-\tif (node->next_frm && node->cur_frm != node->next_frm)\n-\t\tvb2_buffer_done(&node->next_frm->vb.vb2_buf,\n-\t\t\t\tVB2_BUF_STATE_ERROR);\n-\n-\tnode->cur_frm = NULL;\n-\tnode->next_frm = NULL;\n-\tspin_unlock_irqrestore(&node->dma_queue_lock, flags);\n-}\n-\n-static int unicam_enum_input(struct file *file, void *priv,\n-\t\t\t     struct v4l2_input *inp)\n-{\n-\tstruct unicam_node *node = video_drvdata(file);\n-\tstruct unicam_device *dev = node->dev;\n-\n-\tif (inp->index != 0)\n-\t\treturn -EINVAL;\n-\n-\tinp->type = V4L2_INPUT_TYPE_CAMERA;\n-\tif (v4l2_subdev_has_op(dev->sensor, video, s_dv_timings)) {\n-\t\tinp->capabilities = V4L2_IN_CAP_DV_TIMINGS;\n-\t\tinp->std = 0;\n-\t} else if (v4l2_subdev_has_op(dev->sensor, video, s_std)) {\n-\t\tinp->capabilities = V4L2_IN_CAP_STD;\n-\t\tif (v4l2_subdev_call(dev->sensor, video, g_tvnorms, &inp->std)\n-\t\t\t\t\t< 0)\n-\t\t\tinp->std = V4L2_STD_ALL;\n-\t} else {\n-\t\tinp->capabilities = 0;\n-\t\tinp->std = 0;\n-\t}\n-\tsprintf(inp->name, \"Camera 0\");\n-\treturn 0;\n-}\n-\n-static int unicam_g_input(struct file *file, void *priv, unsigned int *i)\n-{\n-\t*i = 0;\n-\n-\treturn 0;\n-}\n-\n-static int unicam_s_input(struct file *file, void *priv, unsigned int i)\n-{\n-\t/*\n-\t * FIXME: Ideally we would like to be able to query the source\n-\t * subdevice for information over the input connectors it supports,\n-\t * and map that through in to a call to video_ops->s_routing.\n-\t * There is no infrastructure support for defining that within\n-\t * devicetree at present. Until that is implemented we can't\n-\t * map a user physical connector number to s_routing input number.\n-\t */\n-\tif (i > 0)\n-\t\treturn -EINVAL;\n-\n-\treturn 0;\n-}\n-\n-static int unicam_querystd(struct file *file, void *priv,\n-\t\t\t   v4l2_std_id *std)\n-{\n-\tstruct unicam_node *node = video_drvdata(file);\n-\tstruct unicam_device *dev = node->dev;\n-\n-\treturn v4l2_subdev_call(dev->sensor, video, querystd, std);\n-}\n-\n-static int unicam_g_std(struct file *file, void *priv, v4l2_std_id *std)\n-{\n-\tstruct unicam_node *node = video_drvdata(file);\n-\tstruct unicam_device *dev = node->dev;\n-\n-\treturn v4l2_subdev_call(dev->sensor, video, g_std, std);\n-}\n-\n-static int unicam_s_std(struct file *file, void *priv, v4l2_std_id std)\n-{\n-\tstruct unicam_node *node = video_drvdata(file);\n-\tstruct unicam_device *dev = node->dev;\n-\tint ret;\n-\tv4l2_std_id current_std;\n-\n-\tret = v4l2_subdev_call(dev->sensor, video, g_std, &current_std);\n-\tif (ret)\n-\t\treturn ret;\n-\n-\tif (std == current_std)\n-\t\treturn 0;\n-\n-\tif (vb2_is_busy(&node->buffer_queue))\n-\t\treturn -EBUSY;\n-\n-\tret = v4l2_subdev_call(dev->sensor, video, s_std, std);\n-\n-\t/* Force recomputation of bytesperline */\n-\tnode->v_fmt.fmt.pix.bytesperline = 0;\n-\n-\tunicam_reset_format(node);\n-\n-\treturn ret;\n-}\n-\n-static int unicam_s_edid(struct file *file, void *priv, struct v4l2_edid *edid)\n-{\n-\tstruct unicam_node *node = video_drvdata(file);\n-\tstruct unicam_device *dev = node->dev;\n-\n-\treturn v4l2_subdev_call(dev->sensor, pad, set_edid, edid);\n-}\n-\n-static int unicam_g_edid(struct file *file, void *priv, struct v4l2_edid *edid)\n-{\n-\tstruct unicam_node *node = video_drvdata(file);\n-\tstruct unicam_device *dev = node->dev;\n-\n-\treturn v4l2_subdev_call(dev->sensor, pad, get_edid, edid);\n-}\n-\n-static int unicam_s_selection(struct file *file, void *priv,\n-\t\t\t      struct v4l2_selection *sel)\n-{\n-\tstruct unicam_node *node = video_drvdata(file);\n-\tstruct unicam_device *dev = node->dev;\n-\tstruct v4l2_subdev_selection sdsel = {\n-\t\t.which = V4L2_SUBDEV_FORMAT_ACTIVE,\n-\t\t.target = sel->target,\n-\t\t.flags = sel->flags,\n-\t\t.r = sel->r,\n-\t};\n-\n-\treturn v4l2_subdev_call(dev->sensor, pad, set_selection, NULL, &sdsel);\n-}\n-\n-static int unicam_g_selection(struct file *file, void *priv,\n-\t\t\t      struct v4l2_selection *sel)\n-{\n-\tstruct unicam_node *node = video_drvdata(file);\n-\tstruct unicam_device *dev = node->dev;\n-\tstruct v4l2_subdev_selection sdsel = {\n-\t\t.which = V4L2_SUBDEV_FORMAT_ACTIVE,\n-\t\t.target = sel->target,\n-\t};\n-\tint ret;\n-\n-\tret = v4l2_subdev_call(dev->sensor, pad, get_selection, NULL, &sdsel);\n-\tif (!ret)\n-\t\tsel->r = sdsel.r;\n-\n-\treturn ret;\n-}\n-\n-static int unicam_enum_framesizes(struct file *file, void *priv,\n-\t\t\t\t  struct v4l2_frmsizeenum *fsize)\n-{\n-\tstruct unicam_node *node = video_drvdata(file);\n-\tstruct unicam_device *dev = node->dev;\n-\tconst struct unicam_fmt *fmt;\n-\tstruct v4l2_subdev_frame_size_enum fse;\n-\tint ret;\n-\n-\tif (node->pad_id == IMAGE_PAD) {\n-\t\t/* check for valid format */\n-\t\tfmt = find_format_by_pix(dev, fsize->pixel_format);\n-\t\tif (!fmt) {\n-\t\t\tunicam_dbg(3, dev, \"Invalid pixel code: %x\\n\",\n-\t\t\t\t   fsize->pixel_format);\n-\t\t\treturn -EINVAL;\n-\t\t}\n-\t\tfse.code = fmt->code;\n-\t} else {\n-\t\t/* This pad is for embedded data, so just set the format */\n-\t\tfse.code = MEDIA_BUS_FMT_SENSOR_DATA;\n-\t}\n-\n-\tfse.which = V4L2_SUBDEV_FORMAT_ACTIVE;\n-\tfse.index = fsize->index;\n-\tfse.pad = node->pad_id;\n-\n-\tret = v4l2_subdev_call(dev->sensor, pad, enum_frame_size, NULL, &fse);\n-\tif (ret)\n-\t\treturn ret;\n-\n-\tunicam_dbg(1, dev, \"%s: index: %d code: %x W:[%d,%d] H:[%d,%d]\\n\",\n-\t\t   __func__, fse.index, fse.code, fse.min_width, fse.max_width,\n-\t\t   fse.min_height, fse.max_height);\n-\n-\tfsize->type = V4L2_FRMSIZE_TYPE_DISCRETE;\n-\tfsize->discrete.width = fse.max_width;\n-\tfsize->discrete.height = fse.max_height;\n-\n-\treturn 0;\n-}\n-\n-static int unicam_enum_frameintervals(struct file *file, void *priv,\n-\t\t\t\t      struct v4l2_frmivalenum *fival)\n-{\n-\tstruct unicam_node *node = video_drvdata(file);\n-\tstruct unicam_device *dev = node->dev;\n-\tconst struct unicam_fmt *fmt;\n-\tstruct v4l2_subdev_frame_interval_enum fie = {\n-\t\t.index = fival->index,\n-\t\t.width = fival->width,\n-\t\t.height = fival->height,\n-\t\t.which = V4L2_SUBDEV_FORMAT_ACTIVE,\n-\t};\n-\tint ret;\n-\n-\tfmt = find_format_by_pix(dev, fival->pixel_format);\n-\tif (!fmt)\n-\t\treturn -EINVAL;\n-\n-\tfie.code = fmt->code;\n-\tret = v4l2_subdev_call(dev->sensor, pad, enum_frame_interval,\n-\t\t\t       NULL, &fie);\n-\tif (ret)\n-\t\treturn ret;\n-\n-\tfival->type = V4L2_FRMIVAL_TYPE_DISCRETE;\n-\tfival->discrete = fie.interval;\n-\n-\treturn 0;\n-}\n-\n-static int unicam_g_parm(struct file *file, void *fh, struct v4l2_streamparm *a)\n-{\n-\tstruct unicam_node *node = video_drvdata(file);\n-\tstruct unicam_device *dev = node->dev;\n-\n-\treturn v4l2_g_parm_cap(video_devdata(file), dev->sensor, a);\n-}\n-\n-static int unicam_s_parm(struct file *file, void *fh, struct v4l2_streamparm *a)\n-{\n-\tstruct unicam_node *node = video_drvdata(file);\n-\tstruct unicam_device *dev = node->dev;\n-\n-\treturn v4l2_s_parm_cap(video_devdata(file), dev->sensor, a);\n-}\n-\n-static int unicam_g_dv_timings(struct file *file, void *priv,\n-\t\t\t       struct v4l2_dv_timings *timings)\n-{\n-\tstruct unicam_node *node = video_drvdata(file);\n-\tstruct unicam_device *dev = node->dev;\n-\n-\treturn v4l2_subdev_call(dev->sensor, video, g_dv_timings, timings);\n-}\n-\n-static int unicam_s_dv_timings(struct file *file, void *priv,\n-\t\t\t       struct v4l2_dv_timings *timings)\n-{\n-\tstruct unicam_node *node = video_drvdata(file);\n-\tstruct unicam_device *dev = node->dev;\n-\tstruct v4l2_dv_timings current_timings;\n-\tint ret;\n-\n-\tret = v4l2_subdev_call(dev->sensor, video, g_dv_timings,\n-\t\t\t       &current_timings);\n-\n-\tif (v4l2_match_dv_timings(timings, &current_timings, 0, false))\n-\t\treturn 0;\n-\n-\tif (vb2_is_busy(&node->buffer_queue))\n-\t\treturn -EBUSY;\n-\n-\tret = v4l2_subdev_call(dev->sensor, video, s_dv_timings, timings);\n-\n-\t/* Force recomputation of bytesperline */\n-\tnode->v_fmt.fmt.pix.bytesperline = 0;\n-\n-\tunicam_reset_format(node);\n-\n-\treturn ret;\n-}\n-\n-static int unicam_query_dv_timings(struct file *file, void *priv,\n-\t\t\t\t   struct v4l2_dv_timings *timings)\n-{\n-\tstruct unicam_node *node = video_drvdata(file);\n-\tstruct unicam_device *dev = node->dev;\n-\n-\treturn v4l2_subdev_call(dev->sensor, video, query_dv_timings, timings);\n-}\n-\n-static int unicam_enum_dv_timings(struct file *file, void *priv,\n-\t\t\t\t  struct v4l2_enum_dv_timings *timings)\n-{\n-\tstruct unicam_node *node = video_drvdata(file);\n-\tstruct unicam_device *dev = node->dev;\n-\n-\treturn v4l2_subdev_call(dev->sensor, pad, enum_dv_timings, timings);\n-}\n-\n-static int unicam_dv_timings_cap(struct file *file, void *priv,\n-\t\t\t\t struct v4l2_dv_timings_cap *cap)\n-{\n-\tstruct unicam_node *node = video_drvdata(file);\n-\tstruct unicam_device *dev = node->dev;\n-\n-\treturn v4l2_subdev_call(dev->sensor, pad, dv_timings_cap, cap);\n-}\n-\n-static int unicam_subscribe_event(struct v4l2_fh *fh,\n-\t\t\t\t  const struct v4l2_event_subscription *sub)\n-{\n-\tswitch (sub->type) {\n-\tcase V4L2_EVENT_FRAME_SYNC:\n-\t\treturn v4l2_event_subscribe(fh, sub, 2, NULL);\n-\tcase V4L2_EVENT_SOURCE_CHANGE:\n-\t\treturn v4l2_event_subscribe(fh, sub, 4, NULL);\n-\t}\n-\n-\treturn v4l2_ctrl_subscribe_event(fh, sub);\n-}\n-\n-static int unicam_log_status(struct file *file, void *fh)\n-{\n-\tstruct unicam_node *node = video_drvdata(file);\n-\tstruct unicam_device *dev = node->dev;\n-\tstruct unicam_cfg *cfg = &dev->cfg;\n-\tu32 reg;\n-\n-\t/* status for sub devices */\n-\tv4l2_device_call_all(&dev->v4l2_dev, 0, core, log_status);\n-\n-\tunicam_info(dev, \"-----Receiver status-----\\n\");\n-\tunicam_info(dev, \"V4L2 width/height:   %ux%u\\n\",\n-\t\t    node->v_fmt.fmt.pix.width, node->v_fmt.fmt.pix.height);\n-\tunicam_info(dev, \"Mediabus format:     %08x\\n\", node->fmt->code);\n-\tunicam_info(dev, \"V4L2 format:         %08x\\n\",\n-\t\t    node->v_fmt.fmt.pix.pixelformat);\n-\treg = reg_read(&dev->cfg, UNICAM_IPIPE);\n-\tunicam_info(dev, \"Unpacking/packing:   %u / %u\\n\",\n-\t\t    get_field(reg, UNICAM_PUM_MASK),\n-\t\t    get_field(reg, UNICAM_PPM_MASK));\n-\tunicam_info(dev, \"----Live data----\\n\");\n-\tunicam_info(dev, \"Programmed stride:   %4u\\n\",\n-\t\t    reg_read(cfg, UNICAM_IBLS));\n-\tunicam_info(dev, \"Detected resolution: %ux%u\\n\",\n-\t\t    reg_read(cfg, UNICAM_IHSTA),\n-\t\t    reg_read(cfg, UNICAM_IVSTA));\n-\tunicam_info(dev, \"Write pointer:       %08x\\n\",\n-\t\t    reg_read(cfg, UNICAM_IBWP));\n-\n-\treturn 0;\n-}\n-\n-static void unicam_notify(struct v4l2_subdev *sd,\n-\t\t\t  unsigned int notification, void *arg)\n-{\n-\tstruct unicam_device *dev =\n-\t\tcontainer_of(sd->v4l2_dev, struct unicam_device, v4l2_dev);\n-\n-\tswitch (notification) {\n-\tcase V4L2_DEVICE_NOTIFY_EVENT:\n-\t\tv4l2_event_queue(&dev->node[IMAGE_PAD].video_dev, arg);\n-\t\tbreak;\n-\tdefault:\n-\t\tbreak;\n-\t}\n-}\n-\n-static const struct vb2_ops unicam_video_qops = {\n-\t.wait_prepare\t\t= vb2_ops_wait_prepare,\n-\t.wait_finish\t\t= vb2_ops_wait_finish,\n-\t.queue_setup\t\t= unicam_queue_setup,\n-\t.buf_prepare\t\t= unicam_buffer_prepare,\n-\t.buf_queue\t\t= unicam_buffer_queue,\n-\t.start_streaming\t= unicam_start_streaming,\n-\t.stop_streaming\t\t= unicam_stop_streaming,\n-};\n-\n-/*\n- * unicam_open : This function is based on the v4l2_fh_open helper function.\n- * It has been augmented to handle sensor subdevice power management,\n- */\n-static int unicam_open(struct file *file)\n-{\n-\tstruct unicam_node *node = video_drvdata(file);\n-\tstruct unicam_device *dev = node->dev;\n-\tint ret;\n-\n-\tmutex_lock(&node->lock);\n-\n-\tret = v4l2_fh_open(file);\n-\tif (ret) {\n-\t\tunicam_err(dev, \"v4l2_fh_open failed\\n\");\n-\t\tgoto unlock;\n-\t}\n-\n-\tnode->open++;\n-\n-\tif (!v4l2_fh_is_singular_file(file))\n-\t\tgoto unlock;\n-\n-\tret = v4l2_subdev_call(dev->sensor, core, s_power, 1);\n-\tif (ret < 0 && ret != -ENOIOCTLCMD) {\n-\t\tv4l2_fh_release(file);\n-\t\tnode->open--;\n-\t\tgoto unlock;\n-\t}\n-\n-\tret = 0;\n-\n-unlock:\n-\tmutex_unlock(&node->lock);\n-\treturn ret;\n-}\n-\n-static int unicam_release(struct file *file)\n-{\n-\tstruct unicam_node *node = video_drvdata(file);\n-\tstruct unicam_device *dev = node->dev;\n-\tstruct v4l2_subdev *sd = dev->sensor;\n-\tbool fh_singular;\n-\tint ret;\n-\n-\tmutex_lock(&node->lock);\n-\n-\tfh_singular = v4l2_fh_is_singular_file(file);\n-\n-\tret = _vb2_fop_release(file, NULL);\n-\n-\tif (fh_singular)\n-\t\tv4l2_subdev_call(sd, core, s_power, 0);\n-\n-\tnode->open--;\n-\tmutex_unlock(&node->lock);\n-\n-\treturn ret;\n-}\n-\n-/* unicam capture driver file operations */\n-static const struct v4l2_file_operations unicam_fops = {\n-\t.owner\t\t= THIS_MODULE,\n-\t.open           = unicam_open,\n-\t.release        = unicam_release,\n-\t.read\t\t= vb2_fop_read,\n-\t.poll\t\t= vb2_fop_poll,\n-\t.unlocked_ioctl\t= video_ioctl2,\n-\t.mmap\t\t= vb2_fop_mmap,\n-};\n-\n-/* unicam capture ioctl operations */\n-static const struct v4l2_ioctl_ops unicam_ioctl_ops = {\n-\t.vidioc_querycap\t\t= unicam_querycap,\n-\t.vidioc_enum_fmt_vid_cap\t= unicam_enum_fmt_vid_cap,\n-\t.vidioc_g_fmt_vid_cap\t\t= unicam_g_fmt_vid_cap,\n-\t.vidioc_s_fmt_vid_cap\t\t= unicam_s_fmt_vid_cap,\n-\t.vidioc_try_fmt_vid_cap\t\t= unicam_try_fmt_vid_cap,\n-\n-\t.vidioc_enum_fmt_meta_cap\t= unicam_enum_fmt_meta_cap,\n-\t.vidioc_g_fmt_meta_cap\t\t= unicam_g_fmt_meta_cap,\n-\t.vidioc_s_fmt_meta_cap\t\t= unicam_s_fmt_meta_cap,\n-\t.vidioc_try_fmt_meta_cap\t= unicam_try_fmt_meta_cap,\n-\n-\t.vidioc_enum_input\t\t= unicam_enum_input,\n-\t.vidioc_g_input\t\t\t= unicam_g_input,\n-\t.vidioc_s_input\t\t\t= unicam_s_input,\n-\n-\t.vidioc_querystd\t\t= unicam_querystd,\n-\t.vidioc_s_std\t\t\t= unicam_s_std,\n-\t.vidioc_g_std\t\t\t= unicam_g_std,\n-\n-\t.vidioc_g_edid\t\t\t= unicam_g_edid,\n-\t.vidioc_s_edid\t\t\t= unicam_s_edid,\n-\n-\t.vidioc_enum_framesizes\t\t= unicam_enum_framesizes,\n-\t.vidioc_enum_frameintervals\t= unicam_enum_frameintervals,\n-\n-\t.vidioc_g_selection\t\t= unicam_g_selection,\n-\t.vidioc_s_selection\t\t= unicam_s_selection,\n-\n-\t.vidioc_g_parm\t\t\t= unicam_g_parm,\n-\t.vidioc_s_parm\t\t\t= unicam_s_parm,\n-\n-\t.vidioc_s_dv_timings\t\t= unicam_s_dv_timings,\n-\t.vidioc_g_dv_timings\t\t= unicam_g_dv_timings,\n-\t.vidioc_query_dv_timings\t= unicam_query_dv_timings,\n-\t.vidioc_enum_dv_timings\t\t= unicam_enum_dv_timings,\n-\t.vidioc_dv_timings_cap\t\t= unicam_dv_timings_cap,\n-\n-\t.vidioc_reqbufs\t\t\t= vb2_ioctl_reqbufs,\n-\t.vidioc_create_bufs\t\t= vb2_ioctl_create_bufs,\n-\t.vidioc_prepare_buf\t\t= vb2_ioctl_prepare_buf,\n-\t.vidioc_querybuf\t\t= vb2_ioctl_querybuf,\n-\t.vidioc_qbuf\t\t\t= vb2_ioctl_qbuf,\n-\t.vidioc_dqbuf\t\t\t= vb2_ioctl_dqbuf,\n-\t.vidioc_expbuf\t\t\t= vb2_ioctl_expbuf,\n-\t.vidioc_streamon\t\t= vb2_ioctl_streamon,\n-\t.vidioc_streamoff\t\t= vb2_ioctl_streamoff,\n-\n-\t.vidioc_log_status\t\t= unicam_log_status,\n-\t.vidioc_subscribe_event\t\t= unicam_subscribe_event,\n-\t.vidioc_unsubscribe_event\t= v4l2_event_unsubscribe,\n-};\n-\n-static int\n-unicam_async_bound(struct v4l2_async_notifier *notifier,\n-\t\t   struct v4l2_subdev *subdev,\n-\t\t   struct v4l2_async_subdev *asd)\n-{\n-\tstruct unicam_device *unicam = container_of(notifier->v4l2_dev,\n-\t\t\t\t\t       struct unicam_device, v4l2_dev);\n-\n-\tif (unicam->sensor) {\n-\t\tunicam_info(unicam, \"Rejecting subdev %s (Already set!!)\",\n-\t\t\t    subdev->name);\n-\t\treturn 0;\n-\t}\n-\n-\tunicam->sensor = subdev;\n-\tunicam_dbg(1, unicam, \"Using sensor %s for capture\\n\", subdev->name);\n-\n-\treturn 0;\n-}\n-\n-static int register_node(struct unicam_device *unicam, struct unicam_node *node,\n-\t\t\t enum v4l2_buf_type type, int pad_id)\n-{\n-\tstruct video_device *vdev;\n-\tstruct vb2_queue *q;\n-\tstruct v4l2_mbus_framefmt mbus_fmt = {0};\n-\tconst struct unicam_fmt *fmt;\n-\tint ret;\n-\n-\tif (unicam->sensor_embedded_data || pad_id != METADATA_PAD) {\n-\t\tret = __subdev_get_format(unicam, &mbus_fmt, pad_id);\n-\t\tif (ret) {\n-\t\t\tunicam_err(unicam, \"Failed to get_format - ret %d\\n\",\n-\t\t\t\t   ret);\n-\t\t\treturn ret;\n-\t\t}\n-\n-\t\tfmt = find_format_by_code(mbus_fmt.code);\n-\t\tif (!fmt) {\n-\t\t\t/* Find the first format that the sensor and unicam both\n-\t\t\t * support\n-\t\t\t */\n-\t\t\tfmt = get_first_supported_format(unicam);\n-\n-\t\t\tif (!fmt)\n-\t\t\t\t/* No compatible formats */\n-\t\t\t\treturn -EINVAL;\n-\n-\t\t\tmbus_fmt.code = fmt->code;\n-\t\t\tret = __subdev_set_format(unicam, &mbus_fmt, pad_id);\n-\t\t\tif (ret)\n-\t\t\t\treturn -EINVAL;\n-\t\t}\n-\t\tif (mbus_fmt.field != V4L2_FIELD_NONE) {\n-\t\t\t/* Interlaced not supported - disable it now. */\n-\t\t\tmbus_fmt.field = V4L2_FIELD_NONE;\n-\t\t\tret = __subdev_set_format(unicam, &mbus_fmt, pad_id);\n-\t\t\tif (ret)\n-\t\t\t\treturn -EINVAL;\n-\t\t}\n-\t} else {\n-\t\t/* Fix this node format as embedded data. */\n-\t\tfmt = find_format_by_code(MEDIA_BUS_FMT_SENSOR_DATA);\n-\t}\n-\n-\tnode->dev = unicam;\n-\tnode->pad_id = pad_id;\n-\tnode->fmt = fmt;\n-\tif (fmt->fourcc) {\n-\t\tif (fmt->fourcc != V4L2_META_FMT_SENSOR_DATA)\n-\t\t\tnode->v_fmt.fmt.pix.pixelformat = fmt->fourcc;\n-\t\telse\n-\t\t\tnode->v_fmt.fmt.meta.dataformat = fmt->fourcc;\n-\t} else {\n-\t\tnode->v_fmt.fmt.pix.pixelformat = fmt->repacked_fourcc;\n-\t}\n-\n-\t/* Read current subdev format */\n-\tunicam_reset_format(node);\n-\n-\tif (v4l2_subdev_has_op(unicam->sensor, video, s_std)) {\n-\t\tv4l2_std_id tvnorms;\n-\n-\t\tif (WARN_ON(!v4l2_subdev_has_op(unicam->sensor, video,\n-\t\t\t\t\t\tg_tvnorms)))\n-\t\t\t/*\n-\t\t\t * Subdevice should not advertise s_std but not\n-\t\t\t * g_tvnorms\n-\t\t\t */\n-\t\t\treturn -EINVAL;\n-\n-\t\tret = v4l2_subdev_call(unicam->sensor, video,\n-\t\t\t\t       g_tvnorms, &tvnorms);\n-\t\tif (WARN_ON(ret))\n-\t\t\treturn -EINVAL;\n-\t\tnode->video_dev.tvnorms |= tvnorms;\n-\t}\n-\n-\tspin_lock_init(&node->dma_queue_lock);\n-\tmutex_init(&node->lock);\n-\n-\tvdev = &node->video_dev;\n-\tif (pad_id == IMAGE_PAD) {\n-\t\t/* Add controls from the subdevice */\n-\t\tret = v4l2_ctrl_add_handler(&node->ctrl_handler,\n-\t\t\t\t\t    unicam->sensor->ctrl_handler, NULL,\n-\t\t\t\t\t    true);\n-\t\tif (ret < 0)\n-\t\t\treturn ret;\n-\n-\t\t/*\n-\t\t * If the sensor subdevice has any controls, associate the node\n-\t\t *  with the ctrl handler to allow access from userland.\n-\t\t */\n-\t\tif (!list_empty(&node->ctrl_handler.ctrls))\n-\t\t\tvdev->ctrl_handler = &node->ctrl_handler;\n-\t}\n-\n-\tq = &node->buffer_queue;\n-\tq->type = type;\n-\tq->io_modes = VB2_MMAP | VB2_DMABUF | VB2_READ;\n-\tq->drv_priv = node;\n-\tq->ops = &unicam_video_qops;\n-\tq->mem_ops = &vb2_dma_contig_memops;\n-\tq->buf_struct_size = sizeof(struct unicam_buffer);\n-\tq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;\n-\tq->lock = &node->lock;\n-\tq->min_buffers_needed = 1;\n-\tq->dev = &unicam->pdev->dev;\n-\n-\tret = vb2_queue_init(q);\n-\tif (ret) {\n-\t\tunicam_err(unicam, \"vb2_queue_init() failed\\n\");\n-\t\treturn ret;\n-\t}\n-\n-\tINIT_LIST_HEAD(&node->dma_queue.active);\n-\n-\tvdev->release = video_device_release_empty;\n-\tvdev->fops = &unicam_fops;\n-\tvdev->ioctl_ops = &unicam_ioctl_ops;\n-\tvdev->v4l2_dev = &unicam->v4l2_dev;\n-\tvdev->vfl_dir = VFL_DIR_RX;\n-\tvdev->queue = q;\n-\tvdev->lock = &node->lock;\n-\tvdev->device_caps = (pad_id == IMAGE_PAD) ?\n-\t\t\t    (V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING) :\n-\t\t\t    (V4L2_CAP_META_CAPTURE | V4L2_CAP_STREAMING);\n-\n-\t/* Define the device names */\n-\tsnprintf(vdev->name, sizeof(vdev->name), \"%s-%s\", UNICAM_MODULE_NAME,\n-\t\t node->pad_id == IMAGE_PAD ? \"image\" : \"embedded\");\n-\n-\tvideo_set_drvdata(vdev, node);\n-\tvdev->entity.flags |= MEDIA_ENT_FL_DEFAULT;\n-\n-\tnode->dummy_buf_cpu_addr = dma_alloc_coherent(&unicam->pdev->dev,\n-\t\t\t\t\t\t      DUMMY_BUF_SIZE,\n-\t\t\t\t\t\t      &node->dummy_buf_dma_addr,\n-\t\t\t\t\t\t      GFP_ATOMIC);\n-\tif (!node->dummy_buf_cpu_addr) {\n-\t\tunicam_err(unicam, \"Unable to allocate dummy buffer.\\n\");\n-\t\treturn -ENOMEM;\n-\t}\n-\n-\tif (node->pad_id == METADATA_PAD) {\n-\t\tv4l2_disable_ioctl(vdev, VIDIOC_DQEVENT);\n-\t\tv4l2_disable_ioctl(vdev, VIDIOC_SUBSCRIBE_EVENT);\n-\t\tv4l2_disable_ioctl(vdev, VIDIOC_UNSUBSCRIBE_EVENT);\n-\t}\n-\tif (node->pad_id == METADATA_PAD ||\n-\t    !v4l2_subdev_has_op(unicam->sensor, video, s_std)) {\n-\t\tv4l2_disable_ioctl(&node->video_dev, VIDIOC_S_STD);\n-\t\tv4l2_disable_ioctl(&node->video_dev, VIDIOC_G_STD);\n-\t\tv4l2_disable_ioctl(&node->video_dev, VIDIOC_ENUMSTD);\n-\t}\n-\tif (node->pad_id == METADATA_PAD ||\n-\t    !v4l2_subdev_has_op(unicam->sensor, video, querystd))\n-\t\tv4l2_disable_ioctl(&node->video_dev, VIDIOC_QUERYSTD);\n-\tif (node->pad_id == METADATA_PAD ||\n-\t    !v4l2_subdev_has_op(unicam->sensor, video, s_dv_timings)) {\n-\t\tv4l2_disable_ioctl(&node->video_dev, VIDIOC_S_EDID);\n-\t\tv4l2_disable_ioctl(&node->video_dev, VIDIOC_G_EDID);\n-\t\tv4l2_disable_ioctl(&node->video_dev, VIDIOC_DV_TIMINGS_CAP);\n-\t\tv4l2_disable_ioctl(&node->video_dev, VIDIOC_G_DV_TIMINGS);\n-\t\tv4l2_disable_ioctl(&node->video_dev, VIDIOC_S_DV_TIMINGS);\n-\t\tv4l2_disable_ioctl(&node->video_dev, VIDIOC_ENUM_DV_TIMINGS);\n-\t\tv4l2_disable_ioctl(&node->video_dev, VIDIOC_QUERY_DV_TIMINGS);\n-\t}\n-\tif (node->pad_id == METADATA_PAD ||\n-\t    !v4l2_subdev_has_op(unicam->sensor, pad, enum_frame_interval))\n-\t\tv4l2_disable_ioctl(&node->video_dev,\n-\t\t\t\t   VIDIOC_ENUM_FRAMEINTERVALS);\n-\tif (node->pad_id == METADATA_PAD ||\n-\t    !v4l2_subdev_has_op(unicam->sensor, video, g_frame_interval))\n-\t\tv4l2_disable_ioctl(&node->video_dev, VIDIOC_G_PARM);\n-\tif (node->pad_id == METADATA_PAD ||\n-\t    !v4l2_subdev_has_op(unicam->sensor, video, s_frame_interval))\n-\t\tv4l2_disable_ioctl(&node->video_dev, VIDIOC_S_PARM);\n-\n-\tif (node->pad_id == METADATA_PAD ||\n-\t    !v4l2_subdev_has_op(unicam->sensor, pad, enum_frame_size))\n-\t\tv4l2_disable_ioctl(&node->video_dev, VIDIOC_ENUM_FRAMESIZES);\n-\n-\tif (node->pad_id == METADATA_PAD ||\n-\t    !v4l2_subdev_has_op(unicam->sensor, pad, set_selection))\n-\t\tv4l2_disable_ioctl(&node->video_dev, VIDIOC_S_SELECTION);\n-\n-\tif (node->pad_id == METADATA_PAD ||\n-\t    !v4l2_subdev_has_op(unicam->sensor, pad, get_selection))\n-\t\tv4l2_disable_ioctl(&node->video_dev, VIDIOC_G_SELECTION);\n-\n-\tret = video_register_device(vdev, VFL_TYPE_VIDEO, -1);\n-\tif (ret) {\n-\t\tunicam_err(unicam, \"Unable to register video device.\\n\");\n-\t\treturn ret;\n-\t}\n-\tnode->registered = 1;\n-\n-\tif (unicam->sensor_embedded_data) {\n-\t\tret = media_create_pad_link(&unicam->sensor->entity, pad_id,\n-\t\t\t\t\t    &node->video_dev.entity, 0,\n-\t\t\t\t\t    MEDIA_LNK_FL_ENABLED |\n-\t\t\t\t\t    MEDIA_LNK_FL_IMMUTABLE);\n-\t\tif (ret)\n-\t\t\tunicam_err(unicam, \"Unable to create pad links.\\n\");\n-\t}\n-\n-\treturn ret;\n-}\n-\n-static void unregister_nodes(struct unicam_device *unicam)\n-{\n-\tstruct unicam_node *node;\n-\tint i;\n-\n-\tfor (i = 0; i < MAX_NODES; i++) {\n-\t\tnode = &unicam->node[i];\n-\t\tif (node->dummy_buf_cpu_addr) {\n-\t\t\tdma_free_coherent(&unicam->pdev->dev, DUMMY_BUF_SIZE,\n-\t\t\t\t\t  node->dummy_buf_cpu_addr,\n-\t\t\t\t\t  node->dummy_buf_dma_addr);\n-\t\t}\n-\t\tif (node->registered) {\n-\t\t\tvideo_unregister_device(&node->video_dev);\n-\t\t\tnode->registered = 0;\n-\t\t}\n-\t}\n-}\n-\n-static int unicam_probe_complete(struct unicam_device *unicam)\n-{\n-\tint ret;\n-\n-\tv4l2_set_subdev_hostdata(unicam->sensor, unicam);\n-\n-\tunicam->v4l2_dev.notify = unicam_notify;\n-\n-\tunicam->sensor_config = v4l2_subdev_alloc_pad_config(unicam->sensor);\n-\tif (!unicam->sensor_config)\n-\t\treturn -ENOMEM;\n-\n-\tunicam->sensor_embedded_data = (unicam->sensor->entity.num_pads >= 2);\n-\n-\tret = register_node(unicam, &unicam->node[IMAGE_PAD],\n-\t\t\t    V4L2_BUF_TYPE_VIDEO_CAPTURE, IMAGE_PAD);\n-\tif (ret) {\n-\t\tunicam_err(unicam, \"Unable to register subdev node 0.\\n\");\n-\t\tgoto unregister;\n-\t}\n-\n-\tret = register_node(unicam, &unicam->node[METADATA_PAD],\n-\t\t\t    V4L2_BUF_TYPE_META_CAPTURE, METADATA_PAD);\n-\tif (ret) {\n-\t\tunicam_err(unicam, \"Unable to register subdev node 1.\\n\");\n-\t\tgoto unregister;\n-\t}\n-\n-\tret = v4l2_device_register_ro_subdev_nodes(&unicam->v4l2_dev);\n-\tif (ret) {\n-\t\tunicam_err(unicam, \"Unable to register subdev nodes.\\n\");\n-\t\tgoto unregister;\n-\t}\n-\n-\treturn 0;\n-\n-unregister:\n-\tunregister_nodes(unicam);\n-\n-\treturn ret;\n-}\n-\n-static int unicam_async_complete(struct v4l2_async_notifier *notifier)\n-{\n-\tstruct unicam_device *unicam = container_of(notifier->v4l2_dev,\n-\t\t\t\t\tstruct unicam_device, v4l2_dev);\n-\n-\treturn unicam_probe_complete(unicam);\n-}\n-\n-static const struct v4l2_async_notifier_operations unicam_async_ops = {\n-\t.bound = unicam_async_bound,\n-\t.complete = unicam_async_complete,\n-};\n-\n-static int of_unicam_connect_subdevs(struct unicam_device *dev)\n-{\n-\tstruct platform_device *pdev = dev->pdev;\n-\tstruct device_node *parent, *ep_node = NULL, *remote_ep = NULL,\n-\t\t\t*sensor_node = NULL;\n-\tstruct v4l2_fwnode_endpoint *ep;\n-\tstruct v4l2_async_subdev *asd;\n-\tunsigned int peripheral_data_lanes;\n-\tint ret = -EINVAL;\n-\tunsigned int lane;\n-\n-\tparent = pdev->dev.of_node;\n-\n-\tasd = &dev->asd;\n-\tep = &dev->endpoint;\n-\n-\tep_node = of_graph_get_next_endpoint(parent, NULL);\n-\tif (!ep_node) {\n-\t\tunicam_dbg(3, dev, \"can't get next endpoint\\n\");\n-\t\tgoto cleanup_exit;\n-\t}\n-\n-\tunicam_dbg(3, dev, \"ep_node is %s\\n\", ep_node->name);\n-\n-\tv4l2_fwnode_endpoint_parse(of_fwnode_handle(ep_node), ep);\n-\n-\tfor (lane = 0; lane < ep->bus.mipi_csi2.num_data_lanes; lane++) {\n-\t\tif (ep->bus.mipi_csi2.data_lanes[lane] != lane + 1) {\n-\t\t\tunicam_err(dev, \"Local endpoint - data lane reordering not supported\\n\");\n-\t\t\tgoto cleanup_exit;\n-\t\t}\n-\t}\n-\n-\tperipheral_data_lanes = ep->bus.mipi_csi2.num_data_lanes;\n-\n-\tsensor_node = of_graph_get_remote_port_parent(ep_node);\n-\tif (!sensor_node) {\n-\t\tunicam_dbg(3, dev, \"can't get remote parent\\n\");\n-\t\tgoto cleanup_exit;\n-\t}\n-\tunicam_dbg(3, dev, \"sensor_node is %s\\n\", sensor_node->name);\n-\tasd->match_type = V4L2_ASYNC_MATCH_FWNODE;\n-\tasd->match.fwnode = of_fwnode_handle(sensor_node);\n-\n-\tremote_ep = of_graph_get_remote_endpoint(ep_node);\n-\tif (!remote_ep) {\n-\t\tunicam_dbg(3, dev, \"can't get remote-endpoint\\n\");\n-\t\tgoto cleanup_exit;\n-\t}\n-\tunicam_dbg(3, dev, \"remote_ep is %s\\n\", remote_ep->name);\n-\tv4l2_fwnode_endpoint_parse(of_fwnode_handle(remote_ep), ep);\n-\tunicam_dbg(3, dev, \"parsed remote_ep to endpoint. nr_of_link_frequencies %u, bus_type %u\\n\",\n-\t\t   ep->nr_of_link_frequencies, ep->bus_type);\n-\n-\tswitch (ep->bus_type) {\n-\tcase V4L2_MBUS_CSI2_DPHY:\n-\t\tif (ep->bus.mipi_csi2.num_data_lanes >\n-\t\t\t\tperipheral_data_lanes) {\n-\t\t\tunicam_err(dev, \"Subdevice %s wants too many data lanes (%u > %u)\\n\",\n-\t\t\t\t   sensor_node->name,\n-\t\t\t\t   ep->bus.mipi_csi2.num_data_lanes,\n-\t\t\t\t   peripheral_data_lanes);\n-\t\t\tgoto cleanup_exit;\n-\t\t}\n-\t\tfor (lane = 0;\n-\t\t     lane < ep->bus.mipi_csi2.num_data_lanes;\n-\t\t     lane++) {\n-\t\t\tif (ep->bus.mipi_csi2.data_lanes[lane] != lane + 1) {\n-\t\t\t\tunicam_err(dev, \"Subdevice %s - incompatible data lane config\\n\",\n-\t\t\t\t\t   sensor_node->name);\n-\t\t\t\tgoto cleanup_exit;\n-\t\t\t}\n-\t\t}\n-\t\tdev->max_data_lanes = ep->bus.mipi_csi2.num_data_lanes;\n-\t\tdev->bus_flags = ep->bus.mipi_csi2.flags;\n-\t\tbreak;\n-\tcase V4L2_MBUS_CCP2:\n-\t\tif (ep->bus.mipi_csi1.clock_lane != 0 ||\n-\t\t    ep->bus.mipi_csi1.data_lane != 1) {\n-\t\t\tunicam_err(dev, \"Subdevice %s incompatible lane config\\n\",\n-\t\t\t\t   sensor_node->name);\n-\t\t\tgoto cleanup_exit;\n-\t\t}\n-\t\tdev->max_data_lanes = 1;\n-\t\tdev->bus_flags = ep->bus.mipi_csi1.strobe;\n-\t\tbreak;\n-\tdefault:\n-\t\t/* Unsupported bus type */\n-\t\tunicam_err(dev, \"sub-device %s is not a CSI2 or CCP2 device %d\\n\",\n-\t\t\t   sensor_node->name, ep->bus_type);\n-\t\tgoto cleanup_exit;\n-\t}\n-\n-\t/* Store bus type - CSI2 or CCP2 */\n-\tdev->bus_type = ep->bus_type;\n-\tunicam_dbg(3, dev, \"bus_type is %d\\n\", dev->bus_type);\n-\n-\t/* Store Virtual Channel number */\n-\tdev->virtual_channel = ep->base.id;\n-\n-\tunicam_dbg(3, dev, \"v4l2-endpoint: %s\\n\",\n-\t\t   dev->bus_type == V4L2_MBUS_CSI2_DPHY ? \"CSI2\" : \"CCP2\");\n-\tunicam_dbg(3, dev, \"Virtual Channel=%d\\n\", dev->virtual_channel);\n-\tif (dev->bus_type == V4L2_MBUS_CSI2_DPHY)\n-\t\tunicam_dbg(3, dev, \"flags=0x%08x\\n\", ep->bus.mipi_csi2.flags);\n-\tunicam_dbg(3, dev, \"num_data_lanes=%d\\n\", dev->max_data_lanes);\n-\n-\tunicam_dbg(1, dev, \"found sub-device %s\\n\", sensor_node->name);\n-\n-\tv4l2_async_notifier_init(&dev->notifier);\n-\n-\tret = v4l2_async_notifier_add_subdev(&dev->notifier, asd);\n-\tif (ret) {\n-\t\tunicam_err(dev, \"Error adding subdevice - ret %d\\n\", ret);\n-\t\tgoto cleanup_exit;\n-\t}\n-\n-\tdev->notifier.ops = &unicam_async_ops;\n-\tret = v4l2_async_notifier_register(&dev->v4l2_dev,\n-\t\t\t\t\t   &dev->notifier);\n-\tif (ret) {\n-\t\tunicam_err(dev, \"Error registering async notifier - ret %d\\n\",\n-\t\t\t   ret);\n-\t\tret = -EINVAL;\n-\t}\n-\n-cleanup_exit:\n-\tif (remote_ep)\n-\t\tof_node_put(remote_ep);\n-\tif (sensor_node)\n-\t\tof_node_put(sensor_node);\n-\tif (ep_node)\n-\t\tof_node_put(ep_node);\n-\n-\treturn ret;\n-}\n-\n-static int unicam_probe(struct platform_device *pdev)\n-{\n-\tstruct unicam_cfg *unicam_cfg;\n-\tstruct unicam_device *unicam;\n-\tstruct v4l2_ctrl_handler *hdl;\n-\tstruct resource\t*res;\n-\tint ret;\n-\n-\tunicam = devm_kzalloc(&pdev->dev, sizeof(*unicam), GFP_KERNEL);\n-\tif (!unicam)\n-\t\treturn -ENOMEM;\n-\n-\tunicam->pdev = pdev;\n-\tunicam_cfg = &unicam->cfg;\n-\n-\tres = platform_get_resource(pdev, IORESOURCE_MEM, 0);\n-\tunicam_cfg->base = devm_ioremap_resource(&pdev->dev, res);\n-\tif (IS_ERR(unicam_cfg->base)) {\n-\t\tunicam_err(unicam, \"Failed to get main io block\\n\");\n-\t\treturn PTR_ERR(unicam_cfg->base);\n-\t}\n-\n-\tres = platform_get_resource(pdev, IORESOURCE_MEM, 1);\n-\tunicam_cfg->clk_gate_base = devm_ioremap_resource(&pdev->dev, res);\n-\tif (IS_ERR(unicam_cfg->clk_gate_base)) {\n-\t\tunicam_err(unicam, \"Failed to get 2nd io block\\n\");\n-\t\treturn PTR_ERR(unicam_cfg->clk_gate_base);\n-\t}\n-\n-\tunicam->clock = devm_clk_get(&pdev->dev, \"lp\");\n-\tif (IS_ERR(unicam->clock)) {\n-\t\tunicam_err(unicam, \"Failed to get clock\\n\");\n-\t\treturn PTR_ERR(unicam->clock);\n-\t}\n-\n-\tret = platform_get_irq(pdev, 0);\n-\tif (ret <= 0) {\n-\t\tdev_err(&pdev->dev, \"No IRQ resource\\n\");\n-\t\treturn -ENODEV;\n-\t}\n-\n-\tret = devm_request_irq(&pdev->dev, ret, unicam_isr, 0,\n-\t\t\t       \"unicam_capture0\", unicam);\n-\tif (ret) {\n-\t\tdev_err(&pdev->dev, \"Unable to request interrupt\\n\");\n-\t\treturn -EINVAL;\n-\t}\n-\n-\tunicam->mdev.dev = &pdev->dev;\n-\tstrscpy(unicam->mdev.model, UNICAM_MODULE_NAME,\n-\t\tsizeof(unicam->mdev.model));\n-\tstrscpy(unicam->mdev.serial, \"\", sizeof(unicam->mdev.serial));\n-\tsnprintf(unicam->mdev.bus_info, sizeof(unicam->mdev.bus_info),\n-\t\t \"platform:%s %s\",\n-\t\t pdev->dev.driver->name, dev_name(&pdev->dev));\n-\tunicam->mdev.hw_revision = 1;\n-\n-\tmedia_entity_pads_init(&unicam->node[IMAGE_PAD].video_dev.entity, 1,\n-\t\t\t       &unicam->node[IMAGE_PAD].pad);\n-\tmedia_entity_pads_init(&unicam->node[METADATA_PAD].video_dev.entity, 1,\n-\t\t\t       &unicam->node[METADATA_PAD].pad);\n-\tmedia_device_init(&unicam->mdev);\n-\n-\tunicam->v4l2_dev.mdev = &unicam->mdev;\n-\n-\tret = v4l2_device_register(&pdev->dev, &unicam->v4l2_dev);\n-\tif (ret) {\n-\t\tunicam_err(unicam,\n-\t\t\t   \"Unable to register v4l2 device.\\n\");\n-\t\tgoto media_cleanup;\n-\t}\n-\n-\tret = media_device_register(&unicam->mdev);\n-\tif (ret < 0) {\n-\t\tunicam_err(unicam,\n-\t\t\t   \"Unable to register media-controller device.\\n\");\n-\t\tgoto probe_out_v4l2_unregister;\n-\t}\n-\n-\t/* Reserve space for the controls */\n-\thdl = &unicam->node[IMAGE_PAD].ctrl_handler;\n-\tret = v4l2_ctrl_handler_init(hdl, 16);\n-\tif (ret < 0)\n-\t\tgoto media_unregister;\n-\n-\t/* set the driver data in platform device */\n-\tplatform_set_drvdata(pdev, unicam);\n-\n-\tret = of_unicam_connect_subdevs(unicam);\n-\tif (ret) {\n-\t\tdev_err(&pdev->dev, \"Failed to connect subdevs\\n\");\n-\t\tgoto free_hdl;\n-\t}\n-\n-\t/* Enable the block power domain */\n-\tpm_runtime_enable(&pdev->dev);\n-\n-\treturn 0;\n-\n-free_hdl:\n-\tv4l2_ctrl_handler_free(hdl);\n-media_unregister:\n-\tmedia_device_unregister(&unicam->mdev);\n-probe_out_v4l2_unregister:\n-\tv4l2_device_unregister(&unicam->v4l2_dev);\n-media_cleanup:\n-\tmedia_device_cleanup(&unicam->mdev);\n-\n-\treturn ret;\n-}\n-\n-static int unicam_remove(struct platform_device *pdev)\n-{\n-\tstruct unicam_device *unicam = platform_get_drvdata(pdev);\n-\n-\tunicam_dbg(2, unicam, \"%s\\n\", __func__);\n-\n-\tpm_runtime_disable(&pdev->dev);\n-\n-\tv4l2_async_notifier_unregister(&unicam->notifier);\n-\tv4l2_ctrl_handler_free(&unicam->node[IMAGE_PAD].ctrl_handler);\n-\tv4l2_device_unregister(&unicam->v4l2_dev);\n-\tunregister_nodes(unicam);\n-\tif (unicam->sensor_config)\n-\t\tv4l2_subdev_free_pad_config(unicam->sensor_config);\n-\tmedia_device_unregister(&unicam->mdev);\n-\tmedia_device_cleanup(&unicam->mdev);\n-\n-\treturn 0;\n-}\n-\n-static const struct of_device_id unicam_of_match[] = {\n-\t{ .compatible = \"brcm,bcm2835-unicam\", },\n-\t{ /* sentinel */ },\n-};\n-MODULE_DEVICE_TABLE(of, unicam_of_match);\n-\n-static struct platform_driver unicam_driver = {\n-\t.probe\t\t= unicam_probe,\n-\t.remove\t\t= unicam_remove,\n-\t.driver = {\n-\t\t.name\t= UNICAM_MODULE_NAME,\n-\t\t.of_match_table = of_match_ptr(unicam_of_match),\n-\t},\n-};\n-\n-module_platform_driver(unicam_driver);\n-\n-MODULE_AUTHOR(\"Dave Stevenson <dave.stevenson@raspberrypi.com>\");\n-MODULE_DESCRIPTION(\"BCM2835 Unicam driver\");\n-MODULE_LICENSE(\"GPL\");\n-MODULE_VERSION(UNICAM_VERSION);\n--- a/drivers/media/platform/bcm2835/vc4-regs-unicam.h\n+++ /dev/null\n@@ -1,253 +0,0 @@\n-/* SPDX-License-Identifier: GPL-2.0-only */\n-\n-/*\n- * Copyright (C) 2017-2020 Raspberry Pi Trading.\n- * Dave Stevenson <dave.stevenson@raspberrypi.com>\n- */\n-\n-#ifndef VC4_REGS_UNICAM_H\n-#define VC4_REGS_UNICAM_H\n-\n-/*\n- * The following values are taken from files found within the code drop\n- * made by Broadcom for the BCM21553 Graphics Driver, predominantly in\n- * brcm_usrlib/dag/vmcsx/vcinclude/hardware_vc4.h.\n- * They have been modified to be only the register offset.\n- */\n-#define UNICAM_CTRL\t0x000\n-#define UNICAM_STA\t0x004\n-#define UNICAM_ANA\t0x008\n-#define UNICAM_PRI\t0x00c\n-#define UNICAM_CLK\t0x010\n-#define UNICAM_CLT\t0x014\n-#define UNICAM_DAT0\t0x018\n-#define UNICAM_DAT1\t0x01c\n-#define UNICAM_DAT2\t0x020\n-#define UNICAM_DAT3\t0x024\n-#define UNICAM_DLT\t0x028\n-#define UNICAM_CMP0\t0x02c\n-#define UNICAM_CMP1\t0x030\n-#define UNICAM_CAP0\t0x034\n-#define UNICAM_CAP1\t0x038\n-#define UNICAM_ICTL\t0x100\n-#define UNICAM_ISTA\t0x104\n-#define UNICAM_IDI0\t0x108\n-#define UNICAM_IPIPE\t0x10c\n-#define UNICAM_IBSA0\t0x110\n-#define UNICAM_IBEA0\t0x114\n-#define UNICAM_IBLS\t0x118\n-#define UNICAM_IBWP\t0x11c\n-#define UNICAM_IHWIN\t0x120\n-#define UNICAM_IHSTA\t0x124\n-#define UNICAM_IVWIN\t0x128\n-#define UNICAM_IVSTA\t0x12c\n-#define UNICAM_ICC\t0x130\n-#define UNICAM_ICS\t0x134\n-#define UNICAM_IDC\t0x138\n-#define UNICAM_IDPO\t0x13c\n-#define UNICAM_IDCA\t0x140\n-#define UNICAM_IDCD\t0x144\n-#define UNICAM_IDS\t0x148\n-#define UNICAM_DCS\t0x200\n-#define UNICAM_DBSA0\t0x204\n-#define UNICAM_DBEA0\t0x208\n-#define UNICAM_DBWP\t0x20c\n-#define UNICAM_DBCTL\t0x300\n-#define UNICAM_IBSA1\t0x304\n-#define UNICAM_IBEA1\t0x308\n-#define UNICAM_IDI1\t0x30c\n-#define UNICAM_DBSA1\t0x310\n-#define UNICAM_DBEA1\t0x314\n-#define UNICAM_MISC\t0x400\n-\n-/*\n- * The following bitmasks are from the kernel released by Broadcom\n- * for Android - https://android.googlesource.com/kernel/bcm/\n- * The Rhea, Hawaii, and Java chips all contain the same VideoCore4\n- * Unicam block as BCM2835, as defined in eg\n- * arch/arm/mach-rhea/include/mach/rdb_A0/brcm_rdb_cam.h and similar.\n- * Values reworked to use the kernel BIT and GENMASK macros.\n- *\n- * Some of the bit mnenomics have been amended to match the datasheet.\n- */\n-/* UNICAM_CTRL Register */\n-#define UNICAM_CPE\t\tBIT(0)\n-#define UNICAM_MEM\t\tBIT(1)\n-#define UNICAM_CPR\t\tBIT(2)\n-#define UNICAM_CPM_MASK\t\tGENMASK(3, 3)\n-#define UNICAM_CPM_CSI2\t\t0\n-#define UNICAM_CPM_CCP2\t\t1\n-#define UNICAM_SOE\t\tBIT(4)\n-#define UNICAM_DCM_MASK\t\tGENMASK(5, 5)\n-#define UNICAM_DCM_STROBE\t0\n-#define UNICAM_DCM_DATA\t\t1\n-#define UNICAM_SLS\t\tBIT(6)\n-#define UNICAM_PFT_MASK\t\tGENMASK(11, 8)\n-#define UNICAM_OET_MASK\t\tGENMASK(20, 12)\n-\n-/* UNICAM_STA Register */\n-#define UNICAM_SYN\t\tBIT(0)\n-#define UNICAM_CS\t\tBIT(1)\n-#define UNICAM_SBE\t\tBIT(2)\n-#define UNICAM_PBE\t\tBIT(3)\n-#define UNICAM_HOE\t\tBIT(4)\n-#define UNICAM_PLE\t\tBIT(5)\n-#define UNICAM_SSC\t\tBIT(6)\n-#define UNICAM_CRCE\t\tBIT(7)\n-#define UNICAM_OES\t\tBIT(8)\n-#define UNICAM_IFO\t\tBIT(9)\n-#define UNICAM_OFO\t\tBIT(10)\n-#define UNICAM_BFO\t\tBIT(11)\n-#define UNICAM_DL\t\tBIT(12)\n-#define UNICAM_PS\t\tBIT(13)\n-#define UNICAM_IS\t\tBIT(14)\n-#define UNICAM_PI0\t\tBIT(15)\n-#define UNICAM_PI1\t\tBIT(16)\n-#define UNICAM_FSI_S\t\tBIT(17)\n-#define UNICAM_FEI_S\t\tBIT(18)\n-#define UNICAM_LCI_S\t\tBIT(19)\n-#define UNICAM_BUF0_RDY\t\tBIT(20)\n-#define UNICAM_BUF0_NO\t\tBIT(21)\n-#define UNICAM_BUF1_RDY\t\tBIT(22)\n-#define UNICAM_BUF1_NO\t\tBIT(23)\n-#define UNICAM_DI\t\tBIT(24)\n-\n-#define UNICAM_STA_MASK_ALL \\\n-\t\t(UNICAM_DL + \\\n-\t\tUNICAM_SBE + \\\n-\t\tUNICAM_PBE + \\\n-\t\tUNICAM_HOE + \\\n-\t\tUNICAM_PLE + \\\n-\t\tUNICAM_SSC + \\\n-\t\tUNICAM_CRCE + \\\n-\t\tUNICAM_IFO + \\\n-\t\tUNICAM_OFO + \\\n-\t\tUNICAM_PS + \\\n-\t\tUNICAM_PI0 + \\\n-\t\tUNICAM_PI1)\n-\n-/* UNICAM_ANA Register */\n-#define UNICAM_APD\t\tBIT(0)\n-#define UNICAM_BPD\t\tBIT(1)\n-#define UNICAM_AR\t\tBIT(2)\n-#define UNICAM_DDL\t\tBIT(3)\n-#define UNICAM_CTATADJ_MASK\tGENMASK(7, 4)\n-#define UNICAM_PTATADJ_MASK\tGENMASK(11, 8)\n-\n-/* UNICAM_PRI Register */\n-#define UNICAM_PE\t\tBIT(0)\n-#define UNICAM_PT_MASK\t\tGENMASK(2, 1)\n-#define UNICAM_NP_MASK\t\tGENMASK(7, 4)\n-#define UNICAM_PP_MASK\t\tGENMASK(11, 8)\n-#define UNICAM_BS_MASK\t\tGENMASK(15, 12)\n-#define UNICAM_BL_MASK\t\tGENMASK(17, 16)\n-\n-/* UNICAM_CLK Register */\n-#define UNICAM_CLE\t\tBIT(0)\n-#define UNICAM_CLPD\t\tBIT(1)\n-#define UNICAM_CLLPE\t\tBIT(2)\n-#define UNICAM_CLHSE\t\tBIT(3)\n-#define UNICAM_CLTRE\t\tBIT(4)\n-#define UNICAM_CLAC_MASK\tGENMASK(8, 5)\n-#define UNICAM_CLSTE\t\tBIT(29)\n-\n-/* UNICAM_CLT Register */\n-#define UNICAM_CLT1_MASK\tGENMASK(7, 0)\n-#define UNICAM_CLT2_MASK\tGENMASK(15, 8)\n-\n-/* UNICAM_DATn Registers */\n-#define UNICAM_DLE\t\tBIT(0)\n-#define UNICAM_DLPD\t\tBIT(1)\n-#define UNICAM_DLLPE\t\tBIT(2)\n-#define UNICAM_DLHSE\t\tBIT(3)\n-#define UNICAM_DLTRE\t\tBIT(4)\n-#define UNICAM_DLSM\t\tBIT(5)\n-#define UNICAM_DLFO\t\tBIT(28)\n-#define UNICAM_DLSTE\t\tBIT(29)\n-\n-#define UNICAM_DAT_MASK_ALL (UNICAM_DLSTE + UNICAM_DLFO)\n-\n-/* UNICAM_DLT Register */\n-#define UNICAM_DLT1_MASK\tGENMASK(7, 0)\n-#define UNICAM_DLT2_MASK\tGENMASK(15, 8)\n-#define UNICAM_DLT3_MASK\tGENMASK(23, 16)\n-\n-/* UNICAM_ICTL Register */\n-#define UNICAM_FSIE\t\tBIT(0)\n-#define UNICAM_FEIE\t\tBIT(1)\n-#define UNICAM_IBOB\t\tBIT(2)\n-#define UNICAM_FCM\t\tBIT(3)\n-#define UNICAM_TFC\t\tBIT(4)\n-#define UNICAM_LIP_MASK\t\tGENMASK(6, 5)\n-#define UNICAM_LCIE_MASK\tGENMASK(28, 16)\n-\n-/* UNICAM_IDI0/1 Register */\n-#define UNICAM_ID0_MASK\t\tGENMASK(7, 0)\n-#define UNICAM_ID1_MASK\t\tGENMASK(15, 8)\n-#define UNICAM_ID2_MASK\t\tGENMASK(23, 16)\n-#define UNICAM_ID3_MASK\t\tGENMASK(31, 24)\n-\n-/* UNICAM_ISTA Register */\n-#define UNICAM_FSI\t\tBIT(0)\n-#define UNICAM_FEI\t\tBIT(1)\n-#define UNICAM_LCI\t\tBIT(2)\n-\n-#define UNICAM_ISTA_MASK_ALL (UNICAM_FSI + UNICAM_FEI + UNICAM_LCI)\n-\n-/* UNICAM_IPIPE Register */\n-#define UNICAM_PUM_MASK\t\tGENMASK(2, 0)\n-\t\t/* Unpacking modes */\n-\t\t#define UNICAM_PUM_NONE\t\t0\n-\t\t#define UNICAM_PUM_UNPACK6\t1\n-\t\t#define UNICAM_PUM_UNPACK7\t2\n-\t\t#define UNICAM_PUM_UNPACK8\t3\n-\t\t#define UNICAM_PUM_UNPACK10\t4\n-\t\t#define UNICAM_PUM_UNPACK12\t5\n-\t\t#define UNICAM_PUM_UNPACK14\t6\n-\t\t#define UNICAM_PUM_UNPACK16\t7\n-#define UNICAM_DDM_MASK\t\tGENMASK(6, 3)\n-#define UNICAM_PPM_MASK\t\tGENMASK(9, 7)\n-\t\t/* Packing modes */\n-\t\t#define UNICAM_PPM_NONE\t\t0\n-\t\t#define UNICAM_PPM_PACK8\t1\n-\t\t#define UNICAM_PPM_PACK10\t2\n-\t\t#define UNICAM_PPM_PACK12\t3\n-\t\t#define UNICAM_PPM_PACK14\t4\n-\t\t#define UNICAM_PPM_PACK16\t5\n-#define UNICAM_DEM_MASK\t\tGENMASK(11, 10)\n-#define UNICAM_DEBL_MASK\tGENMASK(14, 12)\n-#define UNICAM_ICM_MASK\t\tGENMASK(16, 15)\n-#define UNICAM_IDM_MASK\t\tGENMASK(17, 17)\n-\n-/* UNICAM_ICC Register */\n-#define UNICAM_ICFL_MASK\tGENMASK(4, 0)\n-#define UNICAM_ICFH_MASK\tGENMASK(9, 5)\n-#define UNICAM_ICST_MASK\tGENMASK(12, 10)\n-#define UNICAM_ICLT_MASK\tGENMASK(15, 13)\n-#define UNICAM_ICLL_MASK\tGENMASK(31, 16)\n-\n-/* UNICAM_DCS Register */\n-#define UNICAM_DIE\t\tBIT(0)\n-#define UNICAM_DIM\t\tBIT(1)\n-#define UNICAM_DBOB\t\tBIT(3)\n-#define UNICAM_FDE\t\tBIT(4)\n-#define UNICAM_LDP\t\tBIT(5)\n-#define UNICAM_EDL_MASK\t\tGENMASK(15, 8)\n-\n-/* UNICAM_DBCTL Register */\n-#define UNICAM_DBEN\t\tBIT(0)\n-#define UNICAM_BUF0_IE\t\tBIT(1)\n-#define UNICAM_BUF1_IE\t\tBIT(2)\n-\n-/* UNICAM_CMP[0,1] register */\n-#define UNICAM_PCE\t\tBIT(31)\n-#define UNICAM_GI\t\tBIT(9)\n-#define UNICAM_CPH\t\tBIT(8)\n-#define UNICAM_PCVC_MASK\tGENMASK(7, 6)\n-#define UNICAM_PCDT_MASK\tGENMASK(5, 0)\n-\n-/* UNICAM_MISC register */\n-#define UNICAM_FL0\t\tBIT(6)\n-#define UNICAM_FL1\t\tBIT(9)\n-\n-#endif\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0264-media-bcm2835-unicam-Driver-for-CCP2-CSI2-camera-int.patch",
    "content": "From ad386ab52fe80a35042a1a0d0eef0c87d2419dfc Mon Sep 17 00:00:00 2001\nFrom: Naushir Patuck <naush@raspberrypi.com>\nDate: Mon, 4 May 2020 12:25:41 +0300\nSubject: [PATCH] media: bcm2835-unicam: Driver for CCP2/CSI2 camera\n interface\n\nAdd a driver for the Unicam camera receiver block on BCM283x processors.\nCompared to the bcm2835-camera driver present in staging, this driver\nhandles the Unicam block only (CSI-2 receiver), and doesn't depend on\nthe VC4 firmware running on the VPU.\n\nThe commit is made up of a series of changes cherry-picked from the\nrpi-5.4.y branch of https://github.com/raspberrypi/linux/ with\nadditional enhancements, forward-ported to the mainline kernel.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\nSigned-off-by: Naushir Patuck <naush@raspberrypi.com>\nSigned-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>\nReported-by: kbuild test robot <lkp@intel.com>\n---\n MAINTAINERS                                   |    2 +-\n drivers/media/platform/bcm2835/Kconfig        |   15 +\n drivers/media/platform/bcm2835/Makefile       |    3 +\n .../media/platform/bcm2835/bcm2835-unicam.c   | 2825 +++++++++++++++++\n .../media/platform/bcm2835/vc4-regs-unicam.h  |  253 ++\n 5 files changed, 3097 insertions(+), 1 deletion(-)\n create mode 100644 drivers/media/platform/bcm2835/Kconfig\n create mode 100644 drivers/media/platform/bcm2835/Makefile\n create mode 100644 drivers/media/platform/bcm2835/bcm2835-unicam.c\n create mode 100644 drivers/media/platform/bcm2835/vc4-regs-unicam.h\n\n--- a/MAINTAINERS\n+++ b/MAINTAINERS\n@@ -3430,7 +3430,7 @@ M:\tRaspberry Pi Kernel Maintenance <kern\n L:\tlinux-media@vger.kernel.org\n S:\tMaintained\n F:\tdrivers/media/platform/bcm2835/\n-F:\tDocumentation/devicetree/bindings/media/bcm2835-unicam.txt\n+F:\tDocumentation/devicetree/bindings/media/brcm,bcm2835-unicam.yaml\n \n BROADCOM BCM47XX MIPS ARCHITECTURE\n M:\tHauke Mehrtens <hauke@hauke-m.de>\n--- /dev/null\n+++ b/drivers/media/platform/bcm2835/Kconfig\n@@ -0,0 +1,15 @@\n+# Broadcom VideoCore4 V4L2 camera support\n+\n+config VIDEO_BCM2835_UNICAM\n+\ttristate \"Broadcom BCM2835 Unicam video capture driver\"\n+\tdepends on VIDEO_V4L2 && VIDEO_V4L2_SUBDEV_API && MEDIA_CONTROLLER\n+\tdepends on ARCH_BCM2835 || COMPILE_TEST\n+\tselect VIDEOBUF2_DMA_CONTIG\n+\tselect V4L2_FWNODE\n+\thelp\n+\t  Say Y here to enable support for the BCM2835 CSI-2 receiver. This is a\n+\t  V4L2 driver that controls the CSI-2 receiver directly, independently\n+\t  from the VC4 firmware.\n+\n+\t  To compile this driver as a module, choose M here. The module will be\n+\t  called bcm2835-unicam.\n--- /dev/null\n+++ b/drivers/media/platform/bcm2835/Makefile\n@@ -0,0 +1,3 @@\n+# Makefile for BCM2835 Unicam driver\n+\n+obj-$(CONFIG_VIDEO_BCM2835_UNICAM) += bcm2835-unicam.o\n--- /dev/null\n+++ b/drivers/media/platform/bcm2835/bcm2835-unicam.c\n@@ -0,0 +1,2825 @@\n+// SPDX-License-Identifier: GPL-2.0-only\n+/*\n+ * BCM2835 Unicam Capture Driver\n+ *\n+ * Copyright (C) 2017-2020 - Raspberry Pi (Trading) Ltd.\n+ *\n+ * Dave Stevenson <dave.stevenson@raspberrypi.com>\n+ *\n+ * Based on TI am437x driver by\n+ *   Benoit Parrot <bparrot@ti.com>\n+ *   Lad, Prabhakar <prabhakar.csengg@gmail.com>\n+ *\n+ * and TI CAL camera interface driver by\n+ *    Benoit Parrot <bparrot@ti.com>\n+ *\n+ *\n+ * There are two camera drivers in the kernel for BCM283x - this one\n+ * and bcm2835-camera (currently in staging).\n+ *\n+ * This driver directly controls the Unicam peripheral - there is no\n+ * involvement with the VideoCore firmware. Unicam receives CSI-2 or\n+ * CCP2 data and writes it into SDRAM.\n+ * The only potential processing options are to repack Bayer data into an\n+ * alternate format, and applying windowing.\n+ * The repacking does not shift the data, so can repack V4L2_PIX_FMT_Sxxxx10P\n+ * to V4L2_PIX_FMT_Sxxxx10, or V4L2_PIX_FMT_Sxxxx12P to V4L2_PIX_FMT_Sxxxx12,\n+ * but not generically up to V4L2_PIX_FMT_Sxxxx16. The driver will add both\n+ * formats where the relevant formats are defined, and will automatically\n+ * configure the repacking as required.\n+ * Support for windowing may be added later.\n+ *\n+ * It should be possible to connect this driver to any sensor with a\n+ * suitable output interface and V4L2 subdevice driver.\n+ *\n+ * bcm2835-camera uses the VideoCore firmware to control the sensor,\n+ * Unicam, ISP, and all tuner control loops. Fully processed frames are\n+ * delivered to the driver by the firmware. It only has sensor drivers\n+ * for Omnivision OV5647, and Sony IMX219 sensors.\n+ *\n+ * The two drivers are mutually exclusive for the same Unicam instance.\n+ * The VideoCore firmware checks the device tree configuration during boot.\n+ * If it finds device tree nodes called csi0 or csi1 it will block the\n+ * firmware from accessing the peripheral, and bcm2835-camera will\n+ * not be able to stream data.\n+ */\n+\n+#include <linux/clk.h>\n+#include <linux/delay.h>\n+#include <linux/device.h>\n+#include <linux/dma-mapping.h>\n+#include <linux/err.h>\n+#include <linux/init.h>\n+#include <linux/interrupt.h>\n+#include <linux/io.h>\n+#include <linux/module.h>\n+#include <linux/of_device.h>\n+#include <linux/of_graph.h>\n+#include <linux/pinctrl/consumer.h>\n+#include <linux/platform_device.h>\n+#include <linux/pm_runtime.h>\n+#include <linux/slab.h>\n+#include <linux/uaccess.h>\n+#include <linux/videodev2.h>\n+\n+#include <media/v4l2-common.h>\n+#include <media/v4l2-ctrls.h>\n+#include <media/v4l2-dev.h>\n+#include <media/v4l2-device.h>\n+#include <media/v4l2-dv-timings.h>\n+#include <media/v4l2-event.h>\n+#include <media/v4l2-ioctl.h>\n+#include <media/v4l2-fwnode.h>\n+#include <media/videobuf2-dma-contig.h>\n+\n+#include \"vc4-regs-unicam.h\"\n+\n+#define UNICAM_MODULE_NAME\t\"unicam\"\n+#define UNICAM_VERSION\t\t\"0.1.0\"\n+\n+static int debug;\n+module_param(debug, int, 0644);\n+MODULE_PARM_DESC(debug, \"Debug level 0-3\");\n+\n+#define unicam_dbg(level, dev, fmt, arg...)\t\\\n+\t\tv4l2_dbg(level, debug, &(dev)->v4l2_dev, fmt, ##arg)\n+#define unicam_info(dev, fmt, arg...)\t\\\n+\t\tv4l2_info(&(dev)->v4l2_dev, fmt, ##arg)\n+#define unicam_err(dev, fmt, arg...)\t\\\n+\t\tv4l2_err(&(dev)->v4l2_dev, fmt, ##arg)\n+\n+/*\n+ * To protect against a dodgy sensor driver never returning an error from\n+ * enum_mbus_code, set a maximum index value to be used.\n+ */\n+#define MAX_ENUM_MBUS_CODE\t128\n+\n+/*\n+ * Stride is a 16 bit register, but also has to be a multiple of 32.\n+ */\n+#define BPL_ALIGNMENT\t\t32\n+#define MAX_BYTESPERLINE\t((1 << 16) - BPL_ALIGNMENT)\n+/*\n+ * Max width is therefore determined by the max stride divided by\n+ * the number of bits per pixel. Take 32bpp as a\n+ * worst case.\n+ * No imposed limit on the height, so adopt a square image for want\n+ * of anything better.\n+ */\n+#define MAX_WIDTH\t\t(MAX_BYTESPERLINE / 4)\n+#define MAX_HEIGHT\t\tMAX_WIDTH\n+/* Define a nominal minimum image size */\n+#define MIN_WIDTH\t\t16\n+#define MIN_HEIGHT\t\t16\n+/* Default size of the embedded buffer */\n+#define UNICAM_EMBEDDED_SIZE\t8192\n+\n+/*\n+ * Size of the dummy buffer. Can be any size really, but the DMA\n+ * allocation works in units of page sizes.\n+ */\n+#define DUMMY_BUF_SIZE\t\t(PAGE_SIZE)\n+\n+enum pad_types {\n+\tIMAGE_PAD,\n+\tMETADATA_PAD,\n+\tMAX_NODES\n+};\n+\n+/*\n+ * struct unicam_fmt - Unicam media bus format information\n+ * @pixelformat: V4L2 pixel format FCC identifier. 0 if n/a.\n+ * @repacked_fourcc: V4L2 pixel format FCC identifier if the data is expanded\n+ * out to 16bpp. 0 if n/a.\n+ * @code: V4L2 media bus format code.\n+ * @depth: Bits per pixel as delivered from the source.\n+ * @csi_dt: CSI data type.\n+ * @check_variants: Flag to denote that there are multiple mediabus formats\n+ *\t\tstill in the list that could match this V4L2 format.\n+ */\n+struct unicam_fmt {\n+\tu32\tfourcc;\n+\tu32\trepacked_fourcc;\n+\tu32\tcode;\n+\tu8\tdepth;\n+\tu8\tcsi_dt;\n+\tu8\tcheck_variants;\n+};\n+\n+static const struct unicam_fmt formats[] = {\n+\t/* YUV Formats */\n+\t{\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_YUYV,\n+\t\t.code\t\t= MEDIA_BUS_FMT_YUYV8_2X8,\n+\t\t.depth\t\t= 16,\n+\t\t.csi_dt\t\t= 0x1e,\n+\t\t.check_variants = 1,\n+\t}, {\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_UYVY,\n+\t\t.code\t\t= MEDIA_BUS_FMT_UYVY8_2X8,\n+\t\t.depth\t\t= 16,\n+\t\t.csi_dt\t\t= 0x1e,\n+\t\t.check_variants = 1,\n+\t}, {\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_YVYU,\n+\t\t.code\t\t= MEDIA_BUS_FMT_YVYU8_2X8,\n+\t\t.depth\t\t= 16,\n+\t\t.csi_dt\t\t= 0x1e,\n+\t\t.check_variants = 1,\n+\t}, {\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_VYUY,\n+\t\t.code\t\t= MEDIA_BUS_FMT_VYUY8_2X8,\n+\t\t.depth\t\t= 16,\n+\t\t.csi_dt\t\t= 0x1e,\n+\t\t.check_variants = 1,\n+\t}, {\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_YUYV,\n+\t\t.code\t\t= MEDIA_BUS_FMT_YUYV8_1X16,\n+\t\t.depth\t\t= 16,\n+\t\t.csi_dt\t\t= 0x1e,\n+\t}, {\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_UYVY,\n+\t\t.code\t\t= MEDIA_BUS_FMT_UYVY8_1X16,\n+\t\t.depth\t\t= 16,\n+\t\t.csi_dt\t\t= 0x1e,\n+\t}, {\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_YVYU,\n+\t\t.code\t\t= MEDIA_BUS_FMT_YVYU8_1X16,\n+\t\t.depth\t\t= 16,\n+\t\t.csi_dt\t\t= 0x1e,\n+\t}, {\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_VYUY,\n+\t\t.code\t\t= MEDIA_BUS_FMT_VYUY8_1X16,\n+\t\t.depth\t\t= 16,\n+\t\t.csi_dt\t\t= 0x1e,\n+\t}, {\n+\t/* RGB Formats */\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_RGB565, /* gggbbbbb rrrrrggg */\n+\t\t.code\t\t= MEDIA_BUS_FMT_RGB565_2X8_LE,\n+\t\t.depth\t\t= 16,\n+\t\t.csi_dt\t\t= 0x22,\n+\t}, {\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_RGB565X, /* rrrrrggg gggbbbbb */\n+\t\t.code\t\t= MEDIA_BUS_FMT_RGB565_2X8_BE,\n+\t\t.depth\t\t= 16,\n+\t\t.csi_dt\t\t= 0x22\n+\t}, {\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_RGB555, /* gggbbbbb arrrrrgg */\n+\t\t.code\t\t= MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE,\n+\t\t.depth\t\t= 16,\n+\t\t.csi_dt\t\t= 0x21,\n+\t}, {\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_RGB555X, /* arrrrrgg gggbbbbb */\n+\t\t.code\t\t= MEDIA_BUS_FMT_RGB555_2X8_PADHI_BE,\n+\t\t.depth\t\t= 16,\n+\t\t.csi_dt\t\t= 0x21,\n+\t}, {\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_RGB24, /* rgb */\n+\t\t.code\t\t= MEDIA_BUS_FMT_RGB888_1X24,\n+\t\t.depth\t\t= 24,\n+\t\t.csi_dt\t\t= 0x24,\n+\t}, {\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_BGR24, /* bgr */\n+\t\t.code\t\t= MEDIA_BUS_FMT_BGR888_1X24,\n+\t\t.depth\t\t= 24,\n+\t\t.csi_dt\t\t= 0x24,\n+\t}, {\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_RGB32, /* argb */\n+\t\t.code\t\t= MEDIA_BUS_FMT_ARGB8888_1X32,\n+\t\t.depth\t\t= 32,\n+\t\t.csi_dt\t\t= 0x0,\n+\t}, {\n+\t/* Bayer Formats */\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_SBGGR8,\n+\t\t.code\t\t= MEDIA_BUS_FMT_SBGGR8_1X8,\n+\t\t.depth\t\t= 8,\n+\t\t.csi_dt\t\t= 0x2a,\n+\t}, {\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_SGBRG8,\n+\t\t.code\t\t= MEDIA_BUS_FMT_SGBRG8_1X8,\n+\t\t.depth\t\t= 8,\n+\t\t.csi_dt\t\t= 0x2a,\n+\t}, {\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_SGRBG8,\n+\t\t.code\t\t= MEDIA_BUS_FMT_SGRBG8_1X8,\n+\t\t.depth\t\t= 8,\n+\t\t.csi_dt\t\t= 0x2a,\n+\t}, {\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_SRGGB8,\n+\t\t.code\t\t= MEDIA_BUS_FMT_SRGGB8_1X8,\n+\t\t.depth\t\t= 8,\n+\t\t.csi_dt\t\t= 0x2a,\n+\t}, {\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_SBGGR10P,\n+\t\t.repacked_fourcc = V4L2_PIX_FMT_SBGGR10,\n+\t\t.code\t\t= MEDIA_BUS_FMT_SBGGR10_1X10,\n+\t\t.depth\t\t= 10,\n+\t\t.csi_dt\t\t= 0x2b,\n+\t}, {\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_SGBRG10P,\n+\t\t.repacked_fourcc = V4L2_PIX_FMT_SGBRG10,\n+\t\t.code\t\t= MEDIA_BUS_FMT_SGBRG10_1X10,\n+\t\t.depth\t\t= 10,\n+\t\t.csi_dt\t\t= 0x2b,\n+\t}, {\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_SGRBG10P,\n+\t\t.repacked_fourcc = V4L2_PIX_FMT_SGRBG10,\n+\t\t.code\t\t= MEDIA_BUS_FMT_SGRBG10_1X10,\n+\t\t.depth\t\t= 10,\n+\t\t.csi_dt\t\t= 0x2b,\n+\t}, {\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_SRGGB10P,\n+\t\t.repacked_fourcc = V4L2_PIX_FMT_SRGGB10,\n+\t\t.code\t\t= MEDIA_BUS_FMT_SRGGB10_1X10,\n+\t\t.depth\t\t= 10,\n+\t\t.csi_dt\t\t= 0x2b,\n+\t}, {\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_SBGGR12P,\n+\t\t.repacked_fourcc = V4L2_PIX_FMT_SBGGR12,\n+\t\t.code\t\t= MEDIA_BUS_FMT_SBGGR12_1X12,\n+\t\t.depth\t\t= 12,\n+\t\t.csi_dt\t\t= 0x2c,\n+\t}, {\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_SGBRG12P,\n+\t\t.repacked_fourcc = V4L2_PIX_FMT_SGBRG12,\n+\t\t.code\t\t= MEDIA_BUS_FMT_SGBRG12_1X12,\n+\t\t.depth\t\t= 12,\n+\t\t.csi_dt\t\t= 0x2c,\n+\t}, {\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_SGRBG12P,\n+\t\t.repacked_fourcc = V4L2_PIX_FMT_SGRBG12,\n+\t\t.code\t\t= MEDIA_BUS_FMT_SGRBG12_1X12,\n+\t\t.depth\t\t= 12,\n+\t\t.csi_dt\t\t= 0x2c,\n+\t}, {\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_SRGGB12P,\n+\t\t.repacked_fourcc = V4L2_PIX_FMT_SRGGB12,\n+\t\t.code\t\t= MEDIA_BUS_FMT_SRGGB12_1X12,\n+\t\t.depth\t\t= 12,\n+\t\t.csi_dt\t\t= 0x2c,\n+\t}, {\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_SBGGR14P,\n+\t\t.code\t\t= MEDIA_BUS_FMT_SBGGR14_1X14,\n+\t\t.depth\t\t= 14,\n+\t\t.csi_dt\t\t= 0x2d,\n+\t}, {\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_SGBRG14P,\n+\t\t.code\t\t= MEDIA_BUS_FMT_SGBRG14_1X14,\n+\t\t.depth\t\t= 14,\n+\t\t.csi_dt\t\t= 0x2d,\n+\t}, {\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_SGRBG14P,\n+\t\t.code\t\t= MEDIA_BUS_FMT_SGRBG14_1X14,\n+\t\t.depth\t\t= 14,\n+\t\t.csi_dt\t\t= 0x2d,\n+\t}, {\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_SRGGB14P,\n+\t\t.code\t\t= MEDIA_BUS_FMT_SRGGB14_1X14,\n+\t\t.depth\t\t= 14,\n+\t\t.csi_dt\t\t= 0x2d,\n+\t}, {\n+\t/*\n+\t * 16 bit Bayer formats could be supported, but there is no CSI2\n+\t * data_type defined for raw 16, and no sensors that produce it at\n+\t * present.\n+\t */\n+\n+\t/* Greyscale formats */\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_GREY,\n+\t\t.code\t\t= MEDIA_BUS_FMT_Y8_1X8,\n+\t\t.depth\t\t= 8,\n+\t\t.csi_dt\t\t= 0x2a,\n+\t}, {\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_Y10P,\n+\t\t.repacked_fourcc = V4L2_PIX_FMT_Y10,\n+\t\t.code\t\t= MEDIA_BUS_FMT_Y10_1X10,\n+\t\t.depth\t\t= 10,\n+\t\t.csi_dt\t\t= 0x2b,\n+\t}, {\n+\t\t/* NB There is no packed V4L2 fourcc for this format. */\n+\t\t.repacked_fourcc = V4L2_PIX_FMT_Y12,\n+\t\t.code\t\t= MEDIA_BUS_FMT_Y12_1X12,\n+\t\t.depth\t\t= 12,\n+\t\t.csi_dt\t\t= 0x2c,\n+\t},\n+\t/* Embedded data format */\n+\t{\n+\t\t.fourcc\t\t= V4L2_META_FMT_SENSOR_DATA,\n+\t\t.code\t\t= MEDIA_BUS_FMT_SENSOR_DATA,\n+\t\t.depth\t\t= 8,\n+\t}\n+};\n+\n+struct unicam_buffer {\n+\tstruct vb2_v4l2_buffer vb;\n+\tstruct list_head list;\n+};\n+\n+static inline struct unicam_buffer *to_unicam_buffer(struct vb2_buffer *vb)\n+{\n+\treturn container_of(vb, struct unicam_buffer, vb.vb2_buf);\n+}\n+\n+struct unicam_node {\n+\tbool registered;\n+\tint open;\n+\tbool streaming;\n+\tunsigned int pad_id;\n+\t/* Pointer pointing to current v4l2_buffer */\n+\tstruct unicam_buffer *cur_frm;\n+\t/* Pointer pointing to next v4l2_buffer */\n+\tstruct unicam_buffer *next_frm;\n+\t/* video capture */\n+\tconst struct unicam_fmt *fmt;\n+\t/* Used to store current pixel format */\n+\tstruct v4l2_format v_fmt;\n+\t/* Used to store current mbus frame format */\n+\tstruct v4l2_mbus_framefmt m_fmt;\n+\t/* Buffer queue used in video-buf */\n+\tstruct vb2_queue buffer_queue;\n+\t/* Queue of filled frames */\n+\tstruct list_head dma_queue;\n+\t/* IRQ lock for DMA queue */\n+\tspinlock_t dma_queue_lock;\n+\t/* lock used to access this structure */\n+\tstruct mutex lock;\n+\t/* Identifies video device for this channel */\n+\tstruct video_device video_dev;\n+\t/* Pointer to the parent handle */\n+\tstruct unicam_device *dev;\n+\tstruct media_pad pad;\n+\tunsigned int embedded_lines;\n+\t/*\n+\t * Dummy buffer intended to be used by unicam\n+\t * if we have no other queued buffers to swap to.\n+\t */\n+\tvoid *dummy_buf_cpu_addr;\n+\tdma_addr_t dummy_buf_dma_addr;\n+};\n+\n+struct unicam_device {\n+\tstruct kref kref;\n+\n+\t/* V4l2 specific parameters */\n+\tstruct v4l2_async_subdev asd;\n+\n+\t/* peripheral base address */\n+\tvoid __iomem *base;\n+\t/* clock gating base address */\n+\tvoid __iomem *clk_gate_base;\n+\t/* clock handle */\n+\tstruct clk *clock;\n+\t/* V4l2 device */\n+\tstruct v4l2_device v4l2_dev;\n+\tstruct media_device mdev;\n+\n+\t/* parent device */\n+\tstruct platform_device *pdev;\n+\t/* subdevice async Notifier */\n+\tstruct v4l2_async_notifier notifier;\n+\tunsigned int sequence;\n+\n+\t/* ptr to  sub device */\n+\tstruct v4l2_subdev *sensor;\n+\t/* Pad config for the sensor */\n+\tstruct v4l2_subdev_pad_config *sensor_config;\n+\n+\tenum v4l2_mbus_type bus_type;\n+\t/*\n+\t * Stores bus.mipi_csi2.flags for CSI2 sensors, or\n+\t * bus.mipi_csi1.strobe for CCP2.\n+\t */\n+\tunsigned int bus_flags;\n+\tunsigned int max_data_lanes;\n+\tunsigned int active_data_lanes;\n+\tbool sensor_embedded_data;\n+\n+\tstruct unicam_node node[MAX_NODES];\n+\tstruct v4l2_ctrl_handler ctrl_handler;\n+};\n+\n+static inline struct unicam_device *\n+to_unicam_device(struct v4l2_device *v4l2_dev)\n+{\n+\treturn container_of(v4l2_dev, struct unicam_device, v4l2_dev);\n+}\n+\n+/* Hardware access */\n+static inline void clk_write(struct unicam_device *dev, u32 val)\n+{\n+\twritel(val | 0x5a000000, dev->clk_gate_base);\n+}\n+\n+static inline u32 reg_read(struct unicam_device *dev, u32 offset)\n+{\n+\treturn readl(dev->base + offset);\n+}\n+\n+static inline void reg_write(struct unicam_device *dev, u32 offset, u32 val)\n+{\n+\twritel(val, dev->base + offset);\n+}\n+\n+static inline int get_field(u32 value, u32 mask)\n+{\n+\treturn (value & mask) >> __ffs(mask);\n+}\n+\n+static inline void set_field(u32 *valp, u32 field, u32 mask)\n+{\n+\tu32 val = *valp;\n+\n+\tval &= ~mask;\n+\tval |= (field << __ffs(mask)) & mask;\n+\t*valp = val;\n+}\n+\n+static inline u32 reg_read_field(struct unicam_device *dev, u32 offset,\n+\t\t\t\t u32 mask)\n+{\n+\treturn get_field(reg_read(dev, offset), mask);\n+}\n+\n+static inline void reg_write_field(struct unicam_device *dev, u32 offset,\n+\t\t\t\t   u32 field, u32 mask)\n+{\n+\tu32 val = reg_read(dev, offset);\n+\n+\tset_field(&val, field, mask);\n+\treg_write(dev, offset, val);\n+}\n+\n+/* Power management functions */\n+static inline int unicam_runtime_get(struct unicam_device *dev)\n+{\n+\treturn pm_runtime_get_sync(&dev->pdev->dev);\n+}\n+\n+static inline void unicam_runtime_put(struct unicam_device *dev)\n+{\n+\tpm_runtime_put_sync(&dev->pdev->dev);\n+}\n+\n+/* Format setup functions */\n+static const struct unicam_fmt *find_format_by_code(u32 code)\n+{\n+\tunsigned int i;\n+\n+\tfor (i = 0; i < ARRAY_SIZE(formats); i++) {\n+\t\tif (formats[i].code == code)\n+\t\t\treturn &formats[i];\n+\t}\n+\n+\treturn NULL;\n+}\n+\n+static int check_mbus_format(struct unicam_device *dev,\n+\t\t\t     const struct unicam_fmt *format)\n+{\n+\tunsigned int i;\n+\tint ret = 0;\n+\n+\tfor (i = 0; !ret && i < MAX_ENUM_MBUS_CODE; i++) {\n+\t\tstruct v4l2_subdev_mbus_code_enum mbus_code = {\n+\t\t\t.index = i,\n+\t\t\t.pad = IMAGE_PAD,\n+\t\t\t.which = V4L2_SUBDEV_FORMAT_ACTIVE,\n+\t\t};\n+\n+\t\tret = v4l2_subdev_call(dev->sensor, pad, enum_mbus_code,\n+\t\t\t\t       NULL, &mbus_code);\n+\n+\t\tif (!ret && mbus_code.code == format->code)\n+\t\t\treturn 1;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static const struct unicam_fmt *find_format_by_pix(struct unicam_device *dev,\n+\t\t\t\t\t\t   u32 pixelformat)\n+{\n+\tunsigned int i;\n+\n+\tfor (i = 0; i < ARRAY_SIZE(formats); i++) {\n+\t\tif (formats[i].fourcc == pixelformat ||\n+\t\t    formats[i].repacked_fourcc == pixelformat) {\n+\t\t\tif (formats[i].check_variants &&\n+\t\t\t    !check_mbus_format(dev, &formats[i]))\n+\t\t\t\tcontinue;\n+\t\t\treturn &formats[i];\n+\t\t}\n+\t}\n+\n+\treturn NULL;\n+}\n+\n+static inline unsigned int bytes_per_line(u32 width,\n+\t\t\t\t\t  const struct unicam_fmt *fmt,\n+\t\t\t\t\t  u32 v4l2_fourcc)\n+{\n+\tif (v4l2_fourcc == fmt->repacked_fourcc)\n+\t\t/* Repacking always goes to 16bpp */\n+\t\treturn ALIGN(width << 1, BPL_ALIGNMENT);\n+\telse\n+\t\treturn ALIGN((width * fmt->depth) >> 3, BPL_ALIGNMENT);\n+}\n+\n+static int __subdev_get_format(struct unicam_device *dev,\n+\t\t\t       struct v4l2_mbus_framefmt *fmt, int pad_id)\n+{\n+\tstruct v4l2_subdev_format sd_fmt = {\n+\t\t.which = V4L2_SUBDEV_FORMAT_ACTIVE,\n+\t\t.pad = pad_id\n+\t};\n+\tint ret;\n+\n+\tret = v4l2_subdev_call(dev->sensor, pad, get_fmt, dev->sensor_config,\n+\t\t\t       &sd_fmt);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\t*fmt = sd_fmt.format;\n+\n+\tunicam_dbg(1, dev, \"%s %dx%d code:%04x\\n\", __func__,\n+\t\t   fmt->width, fmt->height, fmt->code);\n+\n+\treturn 0;\n+}\n+\n+static int __subdev_set_format(struct unicam_device *dev,\n+\t\t\t       struct v4l2_mbus_framefmt *fmt, int pad_id)\n+{\n+\tstruct v4l2_subdev_format sd_fmt = {\n+\t\t.which = V4L2_SUBDEV_FORMAT_ACTIVE,\n+\t\t.pad = pad_id\n+\t};\n+\tint ret;\n+\n+\tsd_fmt.format = *fmt;\n+\n+\tret = v4l2_subdev_call(dev->sensor, pad, set_fmt, dev->sensor_config,\n+\t\t\t       &sd_fmt);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\t*fmt = sd_fmt.format;\n+\n+\tif (pad_id == IMAGE_PAD)\n+\t\tunicam_dbg(1, dev, \"%s %dx%d code:%04x\\n\", __func__, fmt->width,\n+\t\t\t   fmt->height, fmt->code);\n+\telse\n+\t\tunicam_dbg(1, dev, \"%s Embedded data code:%04x\\n\", __func__,\n+\t\t\t   sd_fmt.format.code);\n+\n+\treturn 0;\n+}\n+\n+static int unicam_calc_format_size_bpl(struct unicam_device *dev,\n+\t\t\t\t       const struct unicam_fmt *fmt,\n+\t\t\t\t       struct v4l2_format *f)\n+{\n+\tunsigned int min_bytesperline;\n+\n+\tv4l_bound_align_image(&f->fmt.pix.width, MIN_WIDTH, MAX_WIDTH, 2,\n+\t\t\t      &f->fmt.pix.height, MIN_HEIGHT, MAX_HEIGHT, 0,\n+\t\t\t      0);\n+\n+\tmin_bytesperline = bytes_per_line(f->fmt.pix.width, fmt,\n+\t\t\t\t\t  f->fmt.pix.pixelformat);\n+\n+\tif (f->fmt.pix.bytesperline > min_bytesperline &&\n+\t    f->fmt.pix.bytesperline <= MAX_BYTESPERLINE)\n+\t\tf->fmt.pix.bytesperline = ALIGN(f->fmt.pix.bytesperline,\n+\t\t\t\t\t\tBPL_ALIGNMENT);\n+\telse\n+\t\tf->fmt.pix.bytesperline = min_bytesperline;\n+\n+\tf->fmt.pix.sizeimage = f->fmt.pix.height * f->fmt.pix.bytesperline;\n+\n+\tunicam_dbg(3, dev, \"%s: fourcc: %08X size: %dx%d bpl:%d img_size:%d\\n\",\n+\t\t   __func__,\n+\t\t   f->fmt.pix.pixelformat,\n+\t\t   f->fmt.pix.width, f->fmt.pix.height,\n+\t\t   f->fmt.pix.bytesperline, f->fmt.pix.sizeimage);\n+\n+\treturn 0;\n+}\n+\n+static int unicam_reset_format(struct unicam_node *node)\n+{\n+\tstruct unicam_device *dev = node->dev;\n+\tstruct v4l2_mbus_framefmt mbus_fmt;\n+\tint ret;\n+\n+\tif (dev->sensor_embedded_data || node->pad_id != METADATA_PAD) {\n+\t\tret = __subdev_get_format(dev, &mbus_fmt, node->pad_id);\n+\t\tif (ret) {\n+\t\t\tunicam_err(dev, \"Failed to get_format - ret %d\\n\", ret);\n+\t\t\treturn ret;\n+\t\t}\n+\n+\t\tif (mbus_fmt.code != node->fmt->code) {\n+\t\t\tunicam_err(dev, \"code mismatch - fmt->code %08x, mbus_fmt.code %08x\\n\",\n+\t\t\t\t   node->fmt->code, mbus_fmt.code);\n+\t\t\treturn ret;\n+\t\t}\n+\t}\n+\n+\tif (node->pad_id == IMAGE_PAD) {\n+\t\tv4l2_fill_pix_format(&node->v_fmt.fmt.pix, &mbus_fmt);\n+\t\tnode->v_fmt.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;\n+\t\tunicam_calc_format_size_bpl(dev, node->fmt, &node->v_fmt);\n+\t} else {\n+\t\tnode->v_fmt.type = V4L2_BUF_TYPE_META_CAPTURE;\n+\t\tnode->v_fmt.fmt.meta.dataformat = V4L2_META_FMT_SENSOR_DATA;\n+\t\tif (dev->sensor_embedded_data) {\n+\t\t\tnode->v_fmt.fmt.meta.buffersize =\n+\t\t\t\t\tmbus_fmt.width * mbus_fmt.height;\n+\t\t\tnode->embedded_lines = mbus_fmt.height;\n+\t\t} else {\n+\t\t\tnode->v_fmt.fmt.meta.buffersize = UNICAM_EMBEDDED_SIZE;\n+\t\t\tnode->embedded_lines = 1;\n+\t\t}\n+\t}\n+\n+\tnode->m_fmt = mbus_fmt;\n+\treturn 0;\n+}\n+\n+static void unicam_wr_dma_addr(struct unicam_device *dev, dma_addr_t dmaaddr,\n+\t\t\t       unsigned int buffer_size, int pad_id)\n+{\n+\tdma_addr_t endaddr = dmaaddr + buffer_size;\n+\n+\t/*\n+\t * dmaaddr and endaddr should be a 32-bit address with the top two bits\n+\t * set to 0x3 to signify uncached access through the Videocore memory\n+\t * controller.\n+\t */\n+\tWARN_ON((dmaaddr >> 30) != 0x3 || (endaddr >> 30) != 0x3);\n+\n+\tif (pad_id == IMAGE_PAD) {\n+\t\treg_write(dev, UNICAM_IBSA0, dmaaddr);\n+\t\treg_write(dev, UNICAM_IBEA0, endaddr);\n+\t} else {\n+\t\treg_write(dev, UNICAM_DBSA0, dmaaddr);\n+\t\treg_write(dev, UNICAM_DBEA0, endaddr);\n+\t}\n+}\n+\n+static inline unsigned int unicam_get_lines_done(struct unicam_device *dev)\n+{\n+\tdma_addr_t start_addr, cur_addr;\n+\tunsigned int stride = dev->node[IMAGE_PAD].v_fmt.fmt.pix.bytesperline;\n+\tstruct unicam_buffer *frm = dev->node[IMAGE_PAD].cur_frm;\n+\n+\tif (!frm)\n+\t\treturn 0;\n+\n+\tstart_addr = vb2_dma_contig_plane_dma_addr(&frm->vb.vb2_buf, 0);\n+\tcur_addr = reg_read(dev, UNICAM_IBWP);\n+\treturn (unsigned int)(cur_addr - start_addr) / stride;\n+}\n+\n+static inline void unicam_schedule_next_buffer(struct unicam_node *node)\n+{\n+\tstruct unicam_device *dev = node->dev;\n+\tstruct unicam_buffer *buf;\n+\tunsigned int size;\n+\tdma_addr_t addr;\n+\n+\tbuf = list_first_entry(&node->dma_queue, struct unicam_buffer, list);\n+\tnode->next_frm = buf;\n+\tlist_del(&buf->list);\n+\n+\taddr = vb2_dma_contig_plane_dma_addr(&buf->vb.vb2_buf, 0);\n+\tsize = (node->pad_id == IMAGE_PAD) ?\n+\t\t\tnode->v_fmt.fmt.pix.sizeimage :\n+\t\t\tnode->v_fmt.fmt.meta.buffersize;\n+\n+\tunicam_wr_dma_addr(dev, addr, size, node->pad_id);\n+}\n+\n+static inline void unicam_schedule_dummy_buffer(struct unicam_node *node)\n+{\n+\tstruct unicam_device *dev = node->dev;\n+\n+\tunicam_dbg(3, dev, \"Scheduling dummy buffer for node %d\\n\",\n+\t\t   node->pad_id);\n+\n+\tunicam_wr_dma_addr(dev, node->dummy_buf_dma_addr, DUMMY_BUF_SIZE,\n+\t\t\t   node->pad_id);\n+\tnode->next_frm = NULL;\n+}\n+\n+static inline void unicam_process_buffer_complete(struct unicam_node *node,\n+\t\t\t\t\t\t  unsigned int sequence)\n+{\n+\tnode->cur_frm->vb.field = node->m_fmt.field;\n+\tnode->cur_frm->vb.sequence = sequence;\n+\n+\tvb2_buffer_done(&node->cur_frm->vb.vb2_buf, VB2_BUF_STATE_DONE);\n+}\n+\n+static bool unicam_all_nodes_streaming(struct unicam_device *dev)\n+{\n+\tbool ret;\n+\n+\tret = dev->node[IMAGE_PAD].open && dev->node[IMAGE_PAD].streaming;\n+\tret &= !dev->node[METADATA_PAD].open ||\n+\t       dev->node[METADATA_PAD].streaming;\n+\treturn ret;\n+}\n+\n+static bool unicam_all_nodes_disabled(struct unicam_device *dev)\n+{\n+\treturn !dev->node[IMAGE_PAD].streaming &&\n+\t       !dev->node[METADATA_PAD].streaming;\n+}\n+\n+static void unicam_queue_event_sof(struct unicam_device *unicam)\n+{\n+\tstruct v4l2_event event = {\n+\t\t.type = V4L2_EVENT_FRAME_SYNC,\n+\t\t.u.frame_sync.frame_sequence = unicam->sequence,\n+\t};\n+\n+\tv4l2_event_queue(&unicam->node[IMAGE_PAD].video_dev, &event);\n+}\n+\n+/*\n+ * unicam_isr : ISR handler for unicam capture\n+ * @irq: irq number\n+ * @dev_id: dev_id ptr\n+ *\n+ * It changes status of the captured buffer, takes next buffer from the queue\n+ * and sets its address in unicam registers\n+ */\n+static irqreturn_t unicam_isr(int irq, void *dev)\n+{\n+\tstruct unicam_device *unicam = dev;\n+\tunsigned int lines_done = unicam_get_lines_done(dev);\n+\tunsigned int sequence = unicam->sequence;\n+\tunsigned int i;\n+\tu32 ista, sta;\n+\tu64 ts;\n+\n+\t/*\n+\t * Don't service interrupts if not streaming.\n+\t * Avoids issues if the VPU should enable the\n+\t * peripheral without the kernel knowing (that\n+\t * shouldn't happen, but causes issues if it does).\n+\t */\n+\tif (unicam_all_nodes_disabled(unicam))\n+\t\treturn IRQ_NONE;\n+\n+\tsta = reg_read(unicam, UNICAM_STA);\n+\t/* Write value back to clear the interrupts */\n+\treg_write(unicam, UNICAM_STA, sta);\n+\n+\tista = reg_read(unicam, UNICAM_ISTA);\n+\t/* Write value back to clear the interrupts */\n+\treg_write(unicam, UNICAM_ISTA, ista);\n+\n+\tunicam_dbg(3, unicam, \"ISR: ISTA: 0x%X, STA: 0x%X, sequence %d, lines done %d\",\n+\t\t   ista, sta, sequence, lines_done);\n+\n+\tif (!(sta & (UNICAM_IS | UNICAM_PI0)))\n+\t\treturn IRQ_HANDLED;\n+\n+\t/*\n+\t * We must run the frame end handler first. If we have a valid next_frm\n+\t * and we get a simultaneout FE + FS interrupt, running the FS handler\n+\t * first would null out the next_frm ptr and we would have lost the\n+\t * buffer forever.\n+\t */\n+\tif (ista & UNICAM_FEI || sta & UNICAM_PI0) {\n+\t\t/*\n+\t\t * Ensure we have swapped buffers already as we can't\n+\t\t * stop the peripheral. If no buffer is available, use a\n+\t\t * dummy buffer to dump out frames until we get a new buffer\n+\t\t * to use.\n+\t\t */\n+\t\tfor (i = 0; i < ARRAY_SIZE(unicam->node); i++) {\n+\t\t\tif (!unicam->node[i].streaming)\n+\t\t\t\tcontinue;\n+\n+\t\t\tif (unicam->node[i].cur_frm)\n+\t\t\t\tunicam_process_buffer_complete(&unicam->node[i],\n+\t\t\t\t\t\t\t       sequence);\n+\t\t\tunicam->node[i].cur_frm = unicam->node[i].next_frm;\n+\t\t}\n+\t\tunicam->sequence++;\n+\t}\n+\n+\tif (ista & UNICAM_FSI) {\n+\t\t/*\n+\t\t * Timestamp is to be when the first data byte was captured,\n+\t\t * aka frame start.\n+\t\t */\n+\t\tts = ktime_get_ns();\n+\t\tfor (i = 0; i < ARRAY_SIZE(unicam->node); i++) {\n+\t\t\tif (!unicam->node[i].streaming)\n+\t\t\t\tcontinue;\n+\n+\t\t\tif (unicam->node[i].cur_frm)\n+\t\t\t\tunicam->node[i].cur_frm->vb.vb2_buf.timestamp =\n+\t\t\t\t\t\t\t\tts;\n+\t\t\t/*\n+\t\t\t * Set the next frame output to go to a dummy frame\n+\t\t\t * if we have not managed to obtain another frame\n+\t\t\t * from the queue.\n+\t\t\t */\n+\t\t\tunicam_schedule_dummy_buffer(&unicam->node[i]);\n+\t\t}\n+\n+\t\tunicam_queue_event_sof(unicam);\n+\t}\n+\n+\t/*\n+\t * Cannot swap buffer at frame end, there may be a race condition\n+\t * where the HW does not actually swap it if the new frame has\n+\t * already started.\n+\t */\n+\tif (ista & (UNICAM_FSI | UNICAM_LCI) && !(ista & UNICAM_FEI)) {\n+\t\tfor (i = 0; i < ARRAY_SIZE(unicam->node); i++) {\n+\t\t\tif (!unicam->node[i].streaming)\n+\t\t\t\tcontinue;\n+\n+\t\t\tspin_lock(&unicam->node[i].dma_queue_lock);\n+\t\t\tif (!list_empty(&unicam->node[i].dma_queue) &&\n+\t\t\t    !unicam->node[i].next_frm)\n+\t\t\t\tunicam_schedule_next_buffer(&unicam->node[i]);\n+\t\t\tspin_unlock(&unicam->node[i].dma_queue_lock);\n+\t\t}\n+\t}\n+\n+\tif (reg_read(unicam, UNICAM_ICTL) & UNICAM_FCM) {\n+\t\t/* Switch out of trigger mode if selected */\n+\t\treg_write_field(unicam, UNICAM_ICTL, 1, UNICAM_TFC);\n+\t\treg_write_field(unicam, UNICAM_ICTL, 0, UNICAM_FCM);\n+\t}\n+\treturn IRQ_HANDLED;\n+}\n+\n+static int unicam_querycap(struct file *file, void *priv,\n+\t\t\t   struct v4l2_capability *cap)\n+{\n+\tstruct unicam_node *node = video_drvdata(file);\n+\tstruct unicam_device *dev = node->dev;\n+\n+\tstrlcpy(cap->driver, UNICAM_MODULE_NAME, sizeof(cap->driver));\n+\tstrlcpy(cap->card, UNICAM_MODULE_NAME, sizeof(cap->card));\n+\n+\tsnprintf(cap->bus_info, sizeof(cap->bus_info),\n+\t\t \"platform:%s\", dev_name(&dev->pdev->dev));\n+\n+\tcap->capabilities |= V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_META_CAPTURE;\n+\n+\treturn 0;\n+}\n+\n+static int unicam_enum_fmt_vid_cap(struct file *file, void  *priv,\n+\t\t\t\t   struct v4l2_fmtdesc *f)\n+{\n+\tstruct unicam_node *node = video_drvdata(file);\n+\tstruct unicam_device *dev = node->dev;\n+\tunsigned int index = 0;\n+\tunsigned int i;\n+\tint ret = 0;\n+\n+\tif (node->pad_id != IMAGE_PAD)\n+\t\treturn -EINVAL;\n+\n+\tfor (i = 0; !ret && i < MAX_ENUM_MBUS_CODE; i++) {\n+\t\tstruct v4l2_subdev_mbus_code_enum mbus_code = {\n+\t\t\t.index = i,\n+\t\t\t.pad = IMAGE_PAD,\n+\t\t\t.which = V4L2_SUBDEV_FORMAT_ACTIVE,\n+\t\t};\n+\t\tconst struct unicam_fmt *fmt;\n+\n+\t\tret = v4l2_subdev_call(dev->sensor, pad, enum_mbus_code,\n+\t\t\t\t       NULL, &mbus_code);\n+\t\tif (ret < 0) {\n+\t\t\tunicam_dbg(2, dev,\n+\t\t\t\t   \"subdev->enum_mbus_code idx %d returned %d - index invalid\\n\",\n+\t\t\t\t   i, ret);\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\n+\t\tfmt = find_format_by_code(mbus_code.code);\n+\t\tif (fmt) {\n+\t\t\tif (fmt->fourcc) {\n+\t\t\t\tif (index == f->index) {\n+\t\t\t\t\tf->pixelformat = fmt->fourcc;\n+\t\t\t\t\tbreak;\n+\t\t\t\t}\n+\t\t\t\tindex++;\n+\t\t\t}\n+\t\t\tif (fmt->repacked_fourcc) {\n+\t\t\t\tif (index == f->index) {\n+\t\t\t\t\tf->pixelformat = fmt->repacked_fourcc;\n+\t\t\t\t\tbreak;\n+\t\t\t\t}\n+\t\t\t\tindex++;\n+\t\t\t}\n+\t\t}\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int unicam_g_fmt_vid_cap(struct file *file, void *priv,\n+\t\t\t\tstruct v4l2_format *f)\n+{\n+\tstruct v4l2_mbus_framefmt mbus_fmt = {0};\n+\tstruct unicam_node *node = video_drvdata(file);\n+\tstruct unicam_device *dev = node->dev;\n+\tconst struct unicam_fmt *fmt = NULL;\n+\tint ret;\n+\n+\tif (node->pad_id != IMAGE_PAD)\n+\t\treturn -EINVAL;\n+\n+\t/*\n+\t * If a flip has occurred in the sensor, the fmt code might have\n+\t * changed. So we will need to re-fetch the format from the subdevice.\n+\t */\n+\tret = __subdev_get_format(dev, &mbus_fmt, node->pad_id);\n+\tif (ret)\n+\t\treturn -EINVAL;\n+\n+\t/* Find the V4L2 format from mbus code. We must match a known format. */\n+\tfmt = find_format_by_code(mbus_fmt.code);\n+\tif (!fmt)\n+\t\treturn -EINVAL;\n+\n+\tnode->fmt = fmt;\n+\tnode->v_fmt.fmt.pix.pixelformat = fmt->fourcc;\n+\t*f = node->v_fmt;\n+\n+\treturn 0;\n+}\n+\n+static\n+const struct unicam_fmt *get_first_supported_format(struct unicam_device *dev)\n+{\n+\tstruct v4l2_subdev_mbus_code_enum mbus_code;\n+\tconst struct unicam_fmt *fmt = NULL;\n+\tunsigned int i;\n+\tint ret;\n+\n+\tfor (i = 0; ret != -EINVAL && ret != -ENOIOCTLCMD; ++i) {\n+\t\tmemset(&mbus_code, 0, sizeof(mbus_code));\n+\t\tmbus_code.index = i;\n+\t\tmbus_code.pad = IMAGE_PAD;\n+\t\tmbus_code.which = V4L2_SUBDEV_FORMAT_ACTIVE;\n+\n+\t\tret = v4l2_subdev_call(dev->sensor, pad, enum_mbus_code, NULL,\n+\t\t\t\t       &mbus_code);\n+\t\tif (ret < 0) {\n+\t\t\tunicam_dbg(2, dev,\n+\t\t\t\t   \"subdev->enum_mbus_code idx %u returned %d - continue\\n\",\n+\t\t\t\t   i, ret);\n+\t\t\tcontinue;\n+\t\t}\n+\n+\t\tunicam_dbg(2, dev, \"subdev %s: code: 0x%08x idx: %u\\n\",\n+\t\t\t   dev->sensor->name, mbus_code.code, i);\n+\n+\t\tfmt = find_format_by_code(mbus_code.code);\n+\t\tunicam_dbg(2, dev, \"fmt 0x%08x returned as %p, V4L2 FOURCC 0x%08x, csi_dt 0x%02x\\n\",\n+\t\t\t   mbus_code.code, fmt, fmt ? fmt->fourcc : 0,\n+\t\t\t   fmt ? fmt->csi_dt : 0);\n+\t\tif (fmt)\n+\t\t\treturn fmt;\n+\t}\n+\n+\treturn NULL;\n+}\n+\n+static int unicam_try_fmt_vid_cap(struct file *file, void *priv,\n+\t\t\t\t  struct v4l2_format *f)\n+{\n+\tstruct unicam_node *node = video_drvdata(file);\n+\tstruct unicam_device *dev = node->dev;\n+\tstruct v4l2_subdev_format sd_fmt = {\n+\t\t.which = V4L2_SUBDEV_FORMAT_TRY,\n+\t\t.pad = IMAGE_PAD\n+\t};\n+\tstruct v4l2_mbus_framefmt *mbus_fmt = &sd_fmt.format;\n+\tconst struct unicam_fmt *fmt;\n+\tint ret;\n+\n+\tif (node->pad_id != IMAGE_PAD)\n+\t\treturn -EINVAL;\n+\n+\tfmt = find_format_by_pix(dev, f->fmt.pix.pixelformat);\n+\tif (!fmt) {\n+\t\t/*\n+\t\t * Pixel format not supported by unicam. Choose the first\n+\t\t * supported format, and let the sensor choose something else.\n+\t\t */\n+\t\tunicam_dbg(3, dev, \"Fourcc format (0x%08x) not found. Use first format.\\n\",\n+\t\t\t   f->fmt.pix.pixelformat);\n+\n+\t\tfmt = &formats[0];\n+\t\tf->fmt.pix.pixelformat = fmt->fourcc;\n+\t}\n+\n+\tv4l2_fill_mbus_format(mbus_fmt, &f->fmt.pix, fmt->code);\n+\t/*\n+\t * No support for receiving interlaced video, so never\n+\t * request it from the sensor subdev.\n+\t */\n+\tmbus_fmt->field = V4L2_FIELD_NONE;\n+\n+\tret = v4l2_subdev_call(dev->sensor, pad, set_fmt, dev->sensor_config,\n+\t\t\t       &sd_fmt);\n+\tif (ret && ret != -ENOIOCTLCMD && ret != -ENODEV)\n+\t\treturn ret;\n+\n+\tif (mbus_fmt->field != V4L2_FIELD_NONE)\n+\t\tunicam_info(dev, \"Sensor trying to send interlaced video - results may be unpredictable\\n\");\n+\n+\tv4l2_fill_pix_format(&f->fmt.pix, &sd_fmt.format);\n+\tif (mbus_fmt->code != fmt->code) {\n+\t\t/* Sensor has returned an alternate format */\n+\t\tfmt = find_format_by_code(mbus_fmt->code);\n+\t\tif (!fmt) {\n+\t\t\t/*\n+\t\t\t * The alternate format is one unicam can't support.\n+\t\t\t * Find the first format that is supported by both, and\n+\t\t\t * then set that.\n+\t\t\t */\n+\t\t\tfmt = get_first_supported_format(dev);\n+\t\t\tmbus_fmt->code = fmt->code;\n+\n+\t\t\tret = v4l2_subdev_call(dev->sensor, pad, set_fmt,\n+\t\t\t\t\t       dev->sensor_config, &sd_fmt);\n+\t\t\tif (ret && ret != -ENOIOCTLCMD && ret != -ENODEV)\n+\t\t\t\treturn ret;\n+\n+\t\t\tif (mbus_fmt->field != V4L2_FIELD_NONE)\n+\t\t\t\tunicam_info(dev, \"Sensor trying to send interlaced video - results may be unpredictable\\n\");\n+\n+\t\t\tv4l2_fill_pix_format(&f->fmt.pix, &sd_fmt.format);\n+\n+\t\t\tif (mbus_fmt->code != fmt->code) {\n+\t\t\t\t/*\n+\t\t\t\t * We've set a format that the sensor reports\n+\t\t\t\t * as being supported, but it refuses to set it.\n+\t\t\t\t * Not much else we can do.\n+\t\t\t\t * Assume that the sensor driver may accept the\n+\t\t\t\t * format when it is set (rather than tried).\n+\t\t\t\t */\n+\t\t\t\tunicam_err(dev, \"Sensor won't accept default format, and Unicam can't support sensor default\\n\");\n+\t\t\t}\n+\t\t}\n+\n+\t\tif (fmt->fourcc)\n+\t\t\tf->fmt.pix.pixelformat = fmt->fourcc;\n+\t\telse\n+\t\t\tf->fmt.pix.pixelformat = fmt->repacked_fourcc;\n+\t}\n+\n+\treturn unicam_calc_format_size_bpl(dev, fmt, f);\n+}\n+\n+static int unicam_s_fmt_vid_cap(struct file *file, void *priv,\n+\t\t\t\tstruct v4l2_format *f)\n+{\n+\tstruct unicam_node *node = video_drvdata(file);\n+\tstruct unicam_device *dev = node->dev;\n+\tstruct vb2_queue *q = &node->buffer_queue;\n+\tstruct v4l2_mbus_framefmt mbus_fmt = {0};\n+\tconst struct unicam_fmt *fmt;\n+\tint ret;\n+\n+\tif (vb2_is_busy(q))\n+\t\treturn -EBUSY;\n+\n+\tret = unicam_try_fmt_vid_cap(file, priv, f);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\tfmt = find_format_by_pix(dev, f->fmt.pix.pixelformat);\n+\tif (!fmt) {\n+\t\t/*\n+\t\t * Unknown pixel format - adopt a default.\n+\t\t * This shouldn't happen as try_fmt should have resolved any\n+\t\t * issues first.\n+\t\t */\n+\t\tfmt = get_first_supported_format(dev);\n+\t\tif (!fmt)\n+\t\t\t/*\n+\t\t\t * It shouldn't be possible to get here with no\n+\t\t\t * supported formats\n+\t\t\t */\n+\t\t\treturn -EINVAL;\n+\t\tf->fmt.pix.pixelformat = fmt->fourcc;\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tv4l2_fill_mbus_format(&mbus_fmt, &f->fmt.pix, fmt->code);\n+\n+\tret = __subdev_set_format(dev, &mbus_fmt, node->pad_id);\n+\tif (ret) {\n+\t\tunicam_dbg(3, dev, \"%s __subdev_set_format failed %d\\n\",\n+\t\t\t   __func__, ret);\n+\t\treturn ret;\n+\t}\n+\n+\t/* Just double check nothing has gone wrong */\n+\tif (mbus_fmt.code != fmt->code) {\n+\t\tunicam_dbg(3, dev,\n+\t\t\t   \"%s subdev changed format on us, this should not happen\\n\",\n+\t\t\t   __func__);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tnode->fmt = fmt;\n+\tnode->v_fmt.fmt.pix.pixelformat = f->fmt.pix.pixelformat;\n+\tnode->v_fmt.fmt.pix.bytesperline = f->fmt.pix.bytesperline;\n+\tunicam_reset_format(node);\n+\n+\tunicam_dbg(3, dev,\n+\t\t   \"%s %dx%d, mbus_fmt 0x%08X, V4L2 pix 0x%08X.\\n\",\n+\t\t   __func__, node->v_fmt.fmt.pix.width,\n+\t\t   node->v_fmt.fmt.pix.height, mbus_fmt.code,\n+\t\t   node->v_fmt.fmt.pix.pixelformat);\n+\n+\t*f = node->v_fmt;\n+\n+\treturn 0;\n+}\n+\n+static int unicam_enum_fmt_meta_cap(struct file *file, void *priv,\n+\t\t\t\t    struct v4l2_fmtdesc *f)\n+{\n+\tstruct unicam_node *node = video_drvdata(file);\n+\tstruct unicam_device *dev = node->dev;\n+\tconst struct unicam_fmt *fmt;\n+\tu32 code;\n+\tint ret = 0;\n+\n+\tif (node->pad_id != METADATA_PAD || f->index != 0)\n+\t\treturn -EINVAL;\n+\n+\tif (dev->sensor_embedded_data) {\n+\t\tstruct v4l2_subdev_mbus_code_enum mbus_code = {\n+\t\t\t.index = f->index,\n+\t\t\t.which = V4L2_SUBDEV_FORMAT_ACTIVE,\n+\t\t\t.pad = METADATA_PAD,\n+\t\t};\n+\n+\t\tret = v4l2_subdev_call(dev->sensor, pad, enum_mbus_code, NULL,\n+\t\t\t\t       &mbus_code);\n+\t\tif (ret < 0) {\n+\t\t\tunicam_dbg(2, dev,\n+\t\t\t\t   \"subdev->enum_mbus_code idx 0 returned %d - index invalid\\n\",\n+\t\t\t\t   ret);\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\n+\t\tcode = mbus_code.code;\n+\t} else {\n+\t\tcode = MEDIA_BUS_FMT_SENSOR_DATA;\n+\t}\n+\n+\tfmt = find_format_by_code(code);\n+\tif (fmt)\n+\t\tf->pixelformat = fmt->fourcc;\n+\n+\treturn 0;\n+}\n+\n+static int unicam_g_fmt_meta_cap(struct file *file, void *priv,\n+\t\t\t\t struct v4l2_format *f)\n+{\n+\tstruct unicam_node *node = video_drvdata(file);\n+\n+\tif (node->pad_id != METADATA_PAD)\n+\t\treturn -EINVAL;\n+\n+\t*f = node->v_fmt;\n+\n+\treturn 0;\n+}\n+\n+static int unicam_queue_setup(struct vb2_queue *vq,\n+\t\t\t      unsigned int *nbuffers,\n+\t\t\t      unsigned int *nplanes,\n+\t\t\t      unsigned int sizes[],\n+\t\t\t      struct device *alloc_devs[])\n+{\n+\tstruct unicam_node *node = vb2_get_drv_priv(vq);\n+\tstruct unicam_device *dev = node->dev;\n+\tunsigned int size = node->pad_id == IMAGE_PAD ?\n+\t\t\t\t    node->v_fmt.fmt.pix.sizeimage :\n+\t\t\t\t    node->v_fmt.fmt.meta.buffersize;\n+\n+\tif (vq->num_buffers + *nbuffers < 3)\n+\t\t*nbuffers = 3 - vq->num_buffers;\n+\n+\tif (*nplanes) {\n+\t\tif (sizes[0] < size) {\n+\t\t\tunicam_err(dev, \"sizes[0] %i < size %u\\n\", sizes[0],\n+\t\t\t\t   size);\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t\tsize = sizes[0];\n+\t}\n+\n+\t*nplanes = 1;\n+\tsizes[0] = size;\n+\n+\treturn 0;\n+}\n+\n+static int unicam_buffer_prepare(struct vb2_buffer *vb)\n+{\n+\tstruct unicam_node *node = vb2_get_drv_priv(vb->vb2_queue);\n+\tstruct unicam_device *dev = node->dev;\n+\tstruct unicam_buffer *buf = to_unicam_buffer(vb);\n+\tunsigned long size;\n+\n+\tif (WARN_ON(!node->fmt))\n+\t\treturn -EINVAL;\n+\n+\tsize = node->pad_id == IMAGE_PAD ? node->v_fmt.fmt.pix.sizeimage :\n+\t\t\t\t\t   node->v_fmt.fmt.meta.buffersize;\n+\tif (vb2_plane_size(vb, 0) < size) {\n+\t\tunicam_err(dev, \"data will not fit into plane (%lu < %lu)\\n\",\n+\t\t\t   vb2_plane_size(vb, 0), size);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tvb2_set_plane_payload(&buf->vb.vb2_buf, 0, size);\n+\treturn 0;\n+}\n+\n+static void unicam_buffer_queue(struct vb2_buffer *vb)\n+{\n+\tstruct unicam_node *node = vb2_get_drv_priv(vb->vb2_queue);\n+\tstruct unicam_buffer *buf = to_unicam_buffer(vb);\n+\tunsigned long flags;\n+\n+\tspin_lock_irqsave(&node->dma_queue_lock, flags);\n+\tlist_add_tail(&buf->list, &node->dma_queue);\n+\tspin_unlock_irqrestore(&node->dma_queue_lock, flags);\n+}\n+\n+static void unicam_set_packing_config(struct unicam_device *dev)\n+{\n+\tu32 pack, unpack;\n+\tu32 val;\n+\n+\tif (dev->node[IMAGE_PAD].v_fmt.fmt.pix.pixelformat ==\n+\t    dev->node[IMAGE_PAD].fmt->fourcc) {\n+\t\tunpack = UNICAM_PUM_NONE;\n+\t\tpack = UNICAM_PPM_NONE;\n+\t} else {\n+\t\tswitch (dev->node[IMAGE_PAD].fmt->depth) {\n+\t\tcase 8:\n+\t\t\tunpack = UNICAM_PUM_UNPACK8;\n+\t\t\tbreak;\n+\t\tcase 10:\n+\t\t\tunpack = UNICAM_PUM_UNPACK10;\n+\t\t\tbreak;\n+\t\tcase 12:\n+\t\t\tunpack = UNICAM_PUM_UNPACK12;\n+\t\t\tbreak;\n+\t\tcase 14:\n+\t\t\tunpack = UNICAM_PUM_UNPACK14;\n+\t\t\tbreak;\n+\t\tcase 16:\n+\t\t\tunpack = UNICAM_PUM_UNPACK16;\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tunpack = UNICAM_PUM_NONE;\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\t/* Repacking is always to 16bpp */\n+\t\tpack = UNICAM_PPM_PACK16;\n+\t}\n+\n+\tval = 0;\n+\tset_field(&val, unpack, UNICAM_PUM_MASK);\n+\tset_field(&val, pack, UNICAM_PPM_MASK);\n+\treg_write(dev, UNICAM_IPIPE, val);\n+}\n+\n+static void unicam_cfg_image_id(struct unicam_device *dev)\n+{\n+\tif (dev->bus_type == V4L2_MBUS_CSI2_DPHY) {\n+\t\t/* CSI2 mode, hardcode VC 0 for now. */\n+\t\treg_write(dev, UNICAM_IDI0,\n+\t\t\t  (0 << 6) | dev->node[IMAGE_PAD].fmt->csi_dt);\n+\t} else {\n+\t\t/* CCP2 mode */\n+\t\treg_write(dev, UNICAM_IDI0,\n+\t\t\t  0x80 | dev->node[IMAGE_PAD].fmt->csi_dt);\n+\t}\n+}\n+\n+static void unicam_enable_ed(struct unicam_device *dev)\n+{\n+\tu32 val = reg_read(dev, UNICAM_DCS);\n+\n+\tset_field(&val, 2, UNICAM_EDL_MASK);\n+\t/* Do not wrap at the end of the embedded data buffer */\n+\tset_field(&val, 0, UNICAM_DBOB);\n+\n+\treg_write(dev, UNICAM_DCS, val);\n+}\n+\n+static void unicam_start_rx(struct unicam_device *dev, dma_addr_t *addr)\n+{\n+\tint line_int_freq = dev->node[IMAGE_PAD].v_fmt.fmt.pix.height >> 2;\n+\tunsigned int size, i;\n+\tu32 val;\n+\n+\tif (line_int_freq < 128)\n+\t\tline_int_freq = 128;\n+\n+\t/* Enable lane clocks */\n+\tval = 1;\n+\tfor (i = 0; i < dev->active_data_lanes; i++)\n+\t\tval = val << 2 | 1;\n+\tclk_write(dev, val);\n+\n+\t/* Basic init */\n+\treg_write(dev, UNICAM_CTRL, UNICAM_MEM);\n+\n+\t/* Enable analogue control, and leave in reset. */\n+\tval = UNICAM_AR;\n+\tset_field(&val, 7, UNICAM_CTATADJ_MASK);\n+\tset_field(&val, 7, UNICAM_PTATADJ_MASK);\n+\treg_write(dev, UNICAM_ANA, val);\n+\tusleep_range(1000, 2000);\n+\n+\t/* Come out of reset */\n+\treg_write_field(dev, UNICAM_ANA, 0, UNICAM_AR);\n+\n+\t/* Peripheral reset */\n+\treg_write_field(dev, UNICAM_CTRL, 1, UNICAM_CPR);\n+\treg_write_field(dev, UNICAM_CTRL, 0, UNICAM_CPR);\n+\n+\treg_write_field(dev, UNICAM_CTRL, 0, UNICAM_CPE);\n+\n+\t/* Enable Rx control. */\n+\tval = reg_read(dev, UNICAM_CTRL);\n+\tif (dev->bus_type == V4L2_MBUS_CSI2_DPHY) {\n+\t\tset_field(&val, UNICAM_CPM_CSI2, UNICAM_CPM_MASK);\n+\t\tset_field(&val, UNICAM_DCM_STROBE, UNICAM_DCM_MASK);\n+\t} else {\n+\t\tset_field(&val, UNICAM_CPM_CCP2, UNICAM_CPM_MASK);\n+\t\tset_field(&val, dev->bus_flags, UNICAM_DCM_MASK);\n+\t}\n+\t/* Packet framer timeout */\n+\tset_field(&val, 0xf, UNICAM_PFT_MASK);\n+\tset_field(&val, 128, UNICAM_OET_MASK);\n+\treg_write(dev, UNICAM_CTRL, val);\n+\n+\treg_write(dev, UNICAM_IHWIN, 0);\n+\treg_write(dev, UNICAM_IVWIN, 0);\n+\n+\t/* AXI bus access QoS setup */\n+\tval = reg_read(dev, UNICAM_PRI);\n+\tset_field(&val, 0, UNICAM_BL_MASK);\n+\tset_field(&val, 0, UNICAM_BS_MASK);\n+\tset_field(&val, 0xe, UNICAM_PP_MASK);\n+\tset_field(&val, 8, UNICAM_NP_MASK);\n+\tset_field(&val, 2, UNICAM_PT_MASK);\n+\tset_field(&val, 1, UNICAM_PE);\n+\treg_write(dev, UNICAM_PRI, val);\n+\n+\treg_write_field(dev, UNICAM_ANA, 0, UNICAM_DDL);\n+\n+\t/* Always start in trigger frame capture mode (UNICAM_FCM set) */\n+\tval = UNICAM_FSIE | UNICAM_FEIE | UNICAM_FCM | UNICAM_IBOB;\n+\tset_field(&val, line_int_freq, UNICAM_LCIE_MASK);\n+\treg_write(dev, UNICAM_ICTL, val);\n+\treg_write(dev, UNICAM_STA, UNICAM_STA_MASK_ALL);\n+\treg_write(dev, UNICAM_ISTA, UNICAM_ISTA_MASK_ALL);\n+\n+\t/* tclk_term_en */\n+\treg_write_field(dev, UNICAM_CLT, 2, UNICAM_CLT1_MASK);\n+\t/* tclk_settle */\n+\treg_write_field(dev, UNICAM_CLT, 6, UNICAM_CLT2_MASK);\n+\t/* td_term_en */\n+\treg_write_field(dev, UNICAM_DLT, 2, UNICAM_DLT1_MASK);\n+\t/* ths_settle */\n+\treg_write_field(dev, UNICAM_DLT, 6, UNICAM_DLT2_MASK);\n+\t/* trx_enable */\n+\treg_write_field(dev, UNICAM_DLT, 0, UNICAM_DLT3_MASK);\n+\n+\treg_write_field(dev, UNICAM_CTRL, 0, UNICAM_SOE);\n+\n+\t/* Packet compare setup - required to avoid missing frame ends */\n+\tval = 0;\n+\tset_field(&val, 1, UNICAM_PCE);\n+\tset_field(&val, 1, UNICAM_GI);\n+\tset_field(&val, 1, UNICAM_CPH);\n+\tset_field(&val, 0, UNICAM_PCVC_MASK);\n+\tset_field(&val, 1, UNICAM_PCDT_MASK);\n+\treg_write(dev, UNICAM_CMP0, val);\n+\n+\t/* Enable clock lane and set up terminations */\n+\tval = 0;\n+\tif (dev->bus_type == V4L2_MBUS_CSI2_DPHY) {\n+\t\t/* CSI2 */\n+\t\tset_field(&val, 1, UNICAM_CLE);\n+\t\tset_field(&val, 1, UNICAM_CLLPE);\n+\t\tif (dev->bus_flags & V4L2_MBUS_CSI2_CONTINUOUS_CLOCK) {\n+\t\t\tset_field(&val, 1, UNICAM_CLTRE);\n+\t\t\tset_field(&val, 1, UNICAM_CLHSE);\n+\t\t}\n+\t} else {\n+\t\t/* CCP2 */\n+\t\tset_field(&val, 1, UNICAM_CLE);\n+\t\tset_field(&val, 1, UNICAM_CLHSE);\n+\t\tset_field(&val, 1, UNICAM_CLTRE);\n+\t}\n+\treg_write(dev, UNICAM_CLK, val);\n+\n+\t/*\n+\t * Enable required data lanes with appropriate terminations.\n+\t * The same value needs to be written to UNICAM_DATn registers for\n+\t * the active lanes, and 0 for inactive ones.\n+\t */\n+\tval = 0;\n+\tif (dev->bus_type == V4L2_MBUS_CSI2_DPHY) {\n+\t\t/* CSI2 */\n+\t\tset_field(&val, 1, UNICAM_DLE);\n+\t\tset_field(&val, 1, UNICAM_DLLPE);\n+\t\tif (dev->bus_flags & V4L2_MBUS_CSI2_CONTINUOUS_CLOCK) {\n+\t\t\tset_field(&val, 1, UNICAM_DLTRE);\n+\t\t\tset_field(&val, 1, UNICAM_DLHSE);\n+\t\t}\n+\t} else {\n+\t\t/* CCP2 */\n+\t\tset_field(&val, 1, UNICAM_DLE);\n+\t\tset_field(&val, 1, UNICAM_DLHSE);\n+\t\tset_field(&val, 1, UNICAM_DLTRE);\n+\t}\n+\treg_write(dev, UNICAM_DAT0, val);\n+\n+\tif (dev->active_data_lanes == 1)\n+\t\tval = 0;\n+\treg_write(dev, UNICAM_DAT1, val);\n+\n+\tif (dev->max_data_lanes > 2) {\n+\t\t/*\n+\t\t * Registers UNICAM_DAT2 and UNICAM_DAT3 only valid if the\n+\t\t * instance supports more than 2 data lanes.\n+\t\t */\n+\t\tif (dev->active_data_lanes == 2)\n+\t\t\tval = 0;\n+\t\treg_write(dev, UNICAM_DAT2, val);\n+\n+\t\tif (dev->active_data_lanes == 3)\n+\t\t\tval = 0;\n+\t\treg_write(dev, UNICAM_DAT3, val);\n+\t}\n+\n+\treg_write(dev, UNICAM_IBLS,\n+\t\t  dev->node[IMAGE_PAD].v_fmt.fmt.pix.bytesperline);\n+\tsize = dev->node[IMAGE_PAD].v_fmt.fmt.pix.sizeimage;\n+\tunicam_wr_dma_addr(dev, addr[IMAGE_PAD], size, IMAGE_PAD);\n+\tunicam_set_packing_config(dev);\n+\tunicam_cfg_image_id(dev);\n+\n+\tval = reg_read(dev, UNICAM_MISC);\n+\tset_field(&val, 1, UNICAM_FL0);\n+\tset_field(&val, 1, UNICAM_FL1);\n+\treg_write(dev, UNICAM_MISC, val);\n+\n+\tif (dev->node[METADATA_PAD].streaming && dev->sensor_embedded_data) {\n+\t\tsize = dev->node[METADATA_PAD].v_fmt.fmt.meta.buffersize;\n+\t\tunicam_enable_ed(dev);\n+\t\tunicam_wr_dma_addr(dev, addr[METADATA_PAD], size, METADATA_PAD);\n+\t}\n+\n+\t/* Enable peripheral */\n+\treg_write_field(dev, UNICAM_CTRL, 1, UNICAM_CPE);\n+\n+\t/* Load image pointers */\n+\treg_write_field(dev, UNICAM_ICTL, 1, UNICAM_LIP_MASK);\n+\n+\t/* Load embedded data buffer pointers if needed */\n+\tif (dev->node[METADATA_PAD].streaming && dev->sensor_embedded_data)\n+\t\treg_write_field(dev, UNICAM_DCS, 1, UNICAM_LDP);\n+\n+\t/*\n+\t * Enable trigger only for the first frame to\n+\t * sync correctly to the FS from the source.\n+\t */\n+\treg_write_field(dev, UNICAM_ICTL, 1, UNICAM_TFC);\n+}\n+\n+static void unicam_disable(struct unicam_device *dev)\n+{\n+\t/* Analogue lane control disable */\n+\treg_write_field(dev, UNICAM_ANA, 1, UNICAM_DDL);\n+\n+\t/* Stop the output engine */\n+\treg_write_field(dev, UNICAM_CTRL, 1, UNICAM_SOE);\n+\n+\t/* Disable the data lanes. */\n+\treg_write(dev, UNICAM_DAT0, 0);\n+\treg_write(dev, UNICAM_DAT1, 0);\n+\n+\tif (dev->max_data_lanes > 2) {\n+\t\treg_write(dev, UNICAM_DAT2, 0);\n+\t\treg_write(dev, UNICAM_DAT3, 0);\n+\t}\n+\n+\t/* Peripheral reset */\n+\treg_write_field(dev, UNICAM_CTRL, 1, UNICAM_CPR);\n+\tusleep_range(50, 100);\n+\treg_write_field(dev, UNICAM_CTRL, 0, UNICAM_CPR);\n+\n+\t/* Disable peripheral */\n+\treg_write_field(dev, UNICAM_CTRL, 0, UNICAM_CPE);\n+\n+\t/* Clear ED setup */\n+\treg_write(dev, UNICAM_DCS, 0);\n+\n+\t/* Disable all lane clocks */\n+\tclk_write(dev, 0);\n+}\n+\n+static void unicam_return_buffers(struct unicam_node *node)\n+{\n+\tstruct unicam_buffer *buf, *tmp;\n+\tunsigned long flags;\n+\n+\tspin_lock_irqsave(&node->dma_queue_lock, flags);\n+\tlist_for_each_entry_safe(buf, tmp, &node->dma_queue, list) {\n+\t\tlist_del(&buf->list);\n+\t\tvb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);\n+\t}\n+\n+\tif (node->cur_frm)\n+\t\tvb2_buffer_done(&node->cur_frm->vb.vb2_buf,\n+\t\t\t\tVB2_BUF_STATE_ERROR);\n+\tif (node->next_frm && node->cur_frm != node->next_frm)\n+\t\tvb2_buffer_done(&node->next_frm->vb.vb2_buf,\n+\t\t\t\tVB2_BUF_STATE_ERROR);\n+\n+\tnode->cur_frm = NULL;\n+\tnode->next_frm = NULL;\n+\tspin_unlock_irqrestore(&node->dma_queue_lock, flags);\n+}\n+\n+static int unicam_start_streaming(struct vb2_queue *vq, unsigned int count)\n+{\n+\tstruct unicam_node *node = vb2_get_drv_priv(vq);\n+\tstruct unicam_device *dev = node->dev;\n+\tdma_addr_t buffer_addr[MAX_NODES] = { 0 };\n+\tunsigned long flags;\n+\tunsigned int i;\n+\tint ret;\n+\n+\tnode->streaming = true;\n+\tif (!unicam_all_nodes_streaming(dev)) {\n+\t\tunicam_dbg(3, dev, \"Not all nodes are streaming yet.\");\n+\t\treturn 0;\n+\t}\n+\n+\tdev->sequence = 0;\n+\tret = unicam_runtime_get(dev);\n+\tif (ret < 0) {\n+\t\tunicam_dbg(3, dev, \"unicam_runtime_get failed\\n\");\n+\t\tgoto err_streaming;\n+\t}\n+\n+\t/*\n+\t * TODO: Retrieve the number of active data lanes from the connected\n+\t * subdevice.\n+\t */\n+\tdev->active_data_lanes = dev->max_data_lanes;\n+\n+\tret = clk_set_rate(dev->clock, 100 * 1000 * 1000);\n+\tif (ret) {\n+\t\tunicam_err(dev, \"failed to set up clock\\n\");\n+\t\tgoto err_pm_put;\n+\t}\n+\n+\tret = clk_prepare_enable(dev->clock);\n+\tif (ret) {\n+\t\tunicam_err(dev, \"Failed to enable CSI clock: %d\\n\", ret);\n+\t\tgoto err_pm_put;\n+\t}\n+\n+\tfor (i = 0; i < ARRAY_SIZE(dev->node); i++) {\n+\t\tstruct unicam_buffer *buf;\n+\n+\t\tif (!dev->node[i].streaming)\n+\t\t\tcontinue;\n+\n+\t\tspin_lock_irqsave(&dev->node[i].dma_queue_lock, flags);\n+\t\tbuf = list_first_entry(&dev->node[i].dma_queue,\n+\t\t\t\t       struct unicam_buffer, list);\n+\t\tdev->node[i].cur_frm = buf;\n+\t\tdev->node[i].next_frm = buf;\n+\t\tlist_del(&buf->list);\n+\t\tspin_unlock_irqrestore(&dev->node[i].dma_queue_lock, flags);\n+\n+\t\tbuffer_addr[i] =\n+\t\t\tvb2_dma_contig_plane_dma_addr(&buf->vb.vb2_buf, 0);\n+\t}\n+\n+\tunicam_start_rx(dev, buffer_addr);\n+\n+\tret = v4l2_subdev_call(dev->sensor, video, s_stream, 1);\n+\tif (ret < 0) {\n+\t\tunicam_err(dev, \"stream on failed in subdev\\n\");\n+\t\tgoto err_disable_unicam;\n+\t}\n+\n+\treturn 0;\n+\n+err_disable_unicam:\n+\tunicam_disable(dev);\n+\tclk_disable_unprepare(dev->clock);\n+err_pm_put:\n+\tunicam_runtime_put(dev);\n+err_streaming:\n+\tunicam_return_buffers(node);\n+\tnode->streaming = false;\n+\n+\treturn ret;\n+}\n+\n+static void unicam_stop_streaming(struct vb2_queue *vq)\n+{\n+\tstruct unicam_node *node = vb2_get_drv_priv(vq);\n+\tstruct unicam_device *dev = node->dev;\n+\n+\tnode->streaming = false;\n+\n+\tif (node->pad_id == IMAGE_PAD) {\n+\t\t/*\n+\t\t * Stop streaming the sensor and disable the peripheral.\n+\t\t * We cannot continue streaming embedded data with the\n+\t\t * image pad disabled.\n+\t\t */\n+\t\tif (v4l2_subdev_call(dev->sensor, video, s_stream, 0) < 0)\n+\t\t\tunicam_err(dev, \"stream off failed in subdev\\n\");\n+\n+\t\tunicam_disable(dev);\n+\t\tclk_disable_unprepare(dev->clock);\n+\t\tunicam_runtime_put(dev);\n+\n+\t} else if (node->pad_id == METADATA_PAD) {\n+\t\t/*\n+\t\t * Allow the hardware to spin in the dummy buffer.\n+\t\t * This is only really needed if the embedded data pad is\n+\t\t * disabled before the image pad.\n+\t\t */\n+\t\tunicam_wr_dma_addr(dev, node->dummy_buf_dma_addr,\n+\t\t\t\t   DUMMY_BUF_SIZE, METADATA_PAD);\n+\t}\n+\n+\t/* Clear all queued buffers for the node */\n+\tunicam_return_buffers(node);\n+}\n+\n+static int unicam_enum_input(struct file *file, void *priv,\n+\t\t\t     struct v4l2_input *inp)\n+{\n+\tstruct unicam_node *node = video_drvdata(file);\n+\tstruct unicam_device *dev = node->dev;\n+\n+\tif (inp->index != 0)\n+\t\treturn -EINVAL;\n+\n+\tinp->type = V4L2_INPUT_TYPE_CAMERA;\n+\tif (v4l2_subdev_has_op(dev->sensor, video, s_dv_timings)) {\n+\t\tinp->capabilities = V4L2_IN_CAP_DV_TIMINGS;\n+\t\tinp->std = 0;\n+\t} else if (v4l2_subdev_has_op(dev->sensor, video, s_std)) {\n+\t\tinp->capabilities = V4L2_IN_CAP_STD;\n+\t\tif (v4l2_subdev_call(dev->sensor, video, g_tvnorms, &inp->std)\n+\t\t\t\t\t< 0)\n+\t\t\tinp->std = V4L2_STD_ALL;\n+\t} else {\n+\t\tinp->capabilities = 0;\n+\t\tinp->std = 0;\n+\t}\n+\tsprintf(inp->name, \"Camera 0\");\n+\treturn 0;\n+}\n+\n+static int unicam_g_input(struct file *file, void *priv, unsigned int *i)\n+{\n+\t*i = 0;\n+\n+\treturn 0;\n+}\n+\n+static int unicam_s_input(struct file *file, void *priv, unsigned int i)\n+{\n+\t/*\n+\t * FIXME: Ideally we would like to be able to query the source\n+\t * subdevice for information over the input connectors it supports,\n+\t * and map that through in to a call to video_ops->s_routing.\n+\t * There is no infrastructure support for defining that within\n+\t * devicetree at present. Until that is implemented we can't\n+\t * map a user physical connector number to s_routing input number.\n+\t */\n+\tif (i > 0)\n+\t\treturn -EINVAL;\n+\n+\treturn 0;\n+}\n+\n+static int unicam_querystd(struct file *file, void *priv,\n+\t\t\t   v4l2_std_id *std)\n+{\n+\tstruct unicam_node *node = video_drvdata(file);\n+\tstruct unicam_device *dev = node->dev;\n+\n+\treturn v4l2_subdev_call(dev->sensor, video, querystd, std);\n+}\n+\n+static int unicam_g_std(struct file *file, void *priv, v4l2_std_id *std)\n+{\n+\tstruct unicam_node *node = video_drvdata(file);\n+\tstruct unicam_device *dev = node->dev;\n+\n+\treturn v4l2_subdev_call(dev->sensor, video, g_std, std);\n+}\n+\n+static int unicam_s_std(struct file *file, void *priv, v4l2_std_id std)\n+{\n+\tstruct unicam_node *node = video_drvdata(file);\n+\tstruct unicam_device *dev = node->dev;\n+\tint ret;\n+\tv4l2_std_id current_std;\n+\n+\tret = v4l2_subdev_call(dev->sensor, video, g_std, &current_std);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tif (std == current_std)\n+\t\treturn 0;\n+\n+\tif (vb2_is_busy(&node->buffer_queue))\n+\t\treturn -EBUSY;\n+\n+\tret = v4l2_subdev_call(dev->sensor, video, s_std, std);\n+\n+\t/* Force recomputation of bytesperline */\n+\tnode->v_fmt.fmt.pix.bytesperline = 0;\n+\n+\tunicam_reset_format(node);\n+\n+\treturn ret;\n+}\n+\n+static int unicam_s_edid(struct file *file, void *priv, struct v4l2_edid *edid)\n+{\n+\tstruct unicam_node *node = video_drvdata(file);\n+\tstruct unicam_device *dev = node->dev;\n+\n+\treturn v4l2_subdev_call(dev->sensor, pad, set_edid, edid);\n+}\n+\n+static int unicam_g_edid(struct file *file, void *priv, struct v4l2_edid *edid)\n+{\n+\tstruct unicam_node *node = video_drvdata(file);\n+\tstruct unicam_device *dev = node->dev;\n+\n+\treturn v4l2_subdev_call(dev->sensor, pad, get_edid, edid);\n+}\n+\n+static int unicam_s_selection(struct file *file, void *priv,\n+\t\t\t      struct v4l2_selection *sel)\n+{\n+\tstruct unicam_node *node = video_drvdata(file);\n+\tstruct unicam_device *dev = node->dev;\n+\tstruct v4l2_subdev_selection sdsel = {\n+\t\t.which = V4L2_SUBDEV_FORMAT_ACTIVE,\n+\t\t.target = sel->target,\n+\t\t.flags = sel->flags,\n+\t\t.r = sel->r,\n+\t};\n+\n+\treturn v4l2_subdev_call(dev->sensor, pad, set_selection, NULL, &sdsel);\n+}\n+\n+static int unicam_g_selection(struct file *file, void *priv,\n+\t\t\t      struct v4l2_selection *sel)\n+{\n+\tstruct unicam_node *node = video_drvdata(file);\n+\tstruct unicam_device *dev = node->dev;\n+\tstruct v4l2_subdev_selection sdsel = {\n+\t\t.which = V4L2_SUBDEV_FORMAT_ACTIVE,\n+\t\t.target = sel->target,\n+\t};\n+\tint ret;\n+\n+\tret = v4l2_subdev_call(dev->sensor, pad, get_selection, NULL, &sdsel);\n+\tif (!ret)\n+\t\tsel->r = sdsel.r;\n+\n+\treturn ret;\n+}\n+\n+static int unicam_enum_framesizes(struct file *file, void *priv,\n+\t\t\t\t  struct v4l2_frmsizeenum *fsize)\n+{\n+\tstruct unicam_node *node = video_drvdata(file);\n+\tstruct unicam_device *dev = node->dev;\n+\tconst struct unicam_fmt *fmt;\n+\tstruct v4l2_subdev_frame_size_enum fse;\n+\tint ret;\n+\n+\t/* check for valid format */\n+\tfmt = find_format_by_pix(dev, fsize->pixel_format);\n+\tif (!fmt) {\n+\t\tunicam_dbg(3, dev, \"Invalid pixel code: %x\\n\",\n+\t\t\t   fsize->pixel_format);\n+\t\treturn -EINVAL;\n+\t}\n+\tfse.code = fmt->code;\n+\n+\tfse.which = V4L2_SUBDEV_FORMAT_ACTIVE;\n+\tfse.index = fsize->index;\n+\tfse.pad = node->pad_id;\n+\n+\tret = v4l2_subdev_call(dev->sensor, pad, enum_frame_size, NULL, &fse);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tunicam_dbg(1, dev, \"%s: index: %d code: %x W:[%d,%d] H:[%d,%d]\\n\",\n+\t\t   __func__, fse.index, fse.code, fse.min_width, fse.max_width,\n+\t\t   fse.min_height, fse.max_height);\n+\n+\tfsize->type = V4L2_FRMSIZE_TYPE_DISCRETE;\n+\tfsize->discrete.width = fse.max_width;\n+\tfsize->discrete.height = fse.max_height;\n+\n+\treturn 0;\n+}\n+\n+static int unicam_enum_frameintervals(struct file *file, void *priv,\n+\t\t\t\t      struct v4l2_frmivalenum *fival)\n+{\n+\tstruct unicam_node *node = video_drvdata(file);\n+\tstruct unicam_device *dev = node->dev;\n+\tconst struct unicam_fmt *fmt;\n+\tstruct v4l2_subdev_frame_interval_enum fie = {\n+\t\t.index = fival->index,\n+\t\t.width = fival->width,\n+\t\t.height = fival->height,\n+\t\t.which = V4L2_SUBDEV_FORMAT_ACTIVE,\n+\t};\n+\tint ret;\n+\n+\tfmt = find_format_by_pix(dev, fival->pixel_format);\n+\tif (!fmt)\n+\t\treturn -EINVAL;\n+\n+\tfie.code = fmt->code;\n+\tret = v4l2_subdev_call(dev->sensor, pad, enum_frame_interval,\n+\t\t\t       NULL, &fie);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tfival->type = V4L2_FRMIVAL_TYPE_DISCRETE;\n+\tfival->discrete = fie.interval;\n+\n+\treturn 0;\n+}\n+\n+static int unicam_g_parm(struct file *file, void *fh, struct v4l2_streamparm *a)\n+{\n+\tstruct unicam_node *node = video_drvdata(file);\n+\tstruct unicam_device *dev = node->dev;\n+\n+\treturn v4l2_g_parm_cap(video_devdata(file), dev->sensor, a);\n+}\n+\n+static int unicam_s_parm(struct file *file, void *fh, struct v4l2_streamparm *a)\n+{\n+\tstruct unicam_node *node = video_drvdata(file);\n+\tstruct unicam_device *dev = node->dev;\n+\n+\treturn v4l2_s_parm_cap(video_devdata(file), dev->sensor, a);\n+}\n+\n+static int unicam_g_dv_timings(struct file *file, void *priv,\n+\t\t\t       struct v4l2_dv_timings *timings)\n+{\n+\tstruct unicam_node *node = video_drvdata(file);\n+\tstruct unicam_device *dev = node->dev;\n+\n+\treturn v4l2_subdev_call(dev->sensor, video, g_dv_timings, timings);\n+}\n+\n+static int unicam_s_dv_timings(struct file *file, void *priv,\n+\t\t\t       struct v4l2_dv_timings *timings)\n+{\n+\tstruct unicam_node *node = video_drvdata(file);\n+\tstruct unicam_device *dev = node->dev;\n+\tstruct v4l2_dv_timings current_timings;\n+\tint ret;\n+\n+\tret = v4l2_subdev_call(dev->sensor, video, g_dv_timings,\n+\t\t\t       &current_timings);\n+\n+\tif (v4l2_match_dv_timings(timings, &current_timings, 0, false))\n+\t\treturn 0;\n+\n+\tif (vb2_is_busy(&node->buffer_queue))\n+\t\treturn -EBUSY;\n+\n+\tret = v4l2_subdev_call(dev->sensor, video, s_dv_timings, timings);\n+\n+\t/* Force recomputation of bytesperline */\n+\tnode->v_fmt.fmt.pix.bytesperline = 0;\n+\n+\tunicam_reset_format(node);\n+\n+\treturn ret;\n+}\n+\n+static int unicam_query_dv_timings(struct file *file, void *priv,\n+\t\t\t\t   struct v4l2_dv_timings *timings)\n+{\n+\tstruct unicam_node *node = video_drvdata(file);\n+\tstruct unicam_device *dev = node->dev;\n+\n+\treturn v4l2_subdev_call(dev->sensor, video, query_dv_timings, timings);\n+}\n+\n+static int unicam_enum_dv_timings(struct file *file, void *priv,\n+\t\t\t\t  struct v4l2_enum_dv_timings *timings)\n+{\n+\tstruct unicam_node *node = video_drvdata(file);\n+\tstruct unicam_device *dev = node->dev;\n+\n+\treturn v4l2_subdev_call(dev->sensor, pad, enum_dv_timings, timings);\n+}\n+\n+static int unicam_dv_timings_cap(struct file *file, void *priv,\n+\t\t\t\t struct v4l2_dv_timings_cap *cap)\n+{\n+\tstruct unicam_node *node = video_drvdata(file);\n+\tstruct unicam_device *dev = node->dev;\n+\n+\treturn v4l2_subdev_call(dev->sensor, pad, dv_timings_cap, cap);\n+}\n+\n+static int unicam_subscribe_event(struct v4l2_fh *fh,\n+\t\t\t\t  const struct v4l2_event_subscription *sub)\n+{\n+\tswitch (sub->type) {\n+\tcase V4L2_EVENT_FRAME_SYNC:\n+\t\treturn v4l2_event_subscribe(fh, sub, 2, NULL);\n+\tcase V4L2_EVENT_SOURCE_CHANGE:\n+\t\treturn v4l2_event_subscribe(fh, sub, 4, NULL);\n+\t}\n+\n+\treturn v4l2_ctrl_subscribe_event(fh, sub);\n+}\n+\n+static int unicam_log_status(struct file *file, void *fh)\n+{\n+\tstruct unicam_node *node = video_drvdata(file);\n+\tstruct unicam_device *dev = node->dev;\n+\tu32 reg;\n+\n+\t/* status for sub devices */\n+\tv4l2_device_call_all(&dev->v4l2_dev, 0, core, log_status);\n+\n+\tunicam_info(dev, \"-----Receiver status-----\\n\");\n+\tunicam_info(dev, \"V4L2 width/height:   %ux%u\\n\",\n+\t\t    node->v_fmt.fmt.pix.width, node->v_fmt.fmt.pix.height);\n+\tunicam_info(dev, \"Mediabus format:     %08x\\n\", node->fmt->code);\n+\tunicam_info(dev, \"V4L2 format:         %08x\\n\",\n+\t\t    node->v_fmt.fmt.pix.pixelformat);\n+\treg = reg_read(dev, UNICAM_IPIPE);\n+\tunicam_info(dev, \"Unpacking/packing:   %u / %u\\n\",\n+\t\t    get_field(reg, UNICAM_PUM_MASK),\n+\t\t    get_field(reg, UNICAM_PPM_MASK));\n+\tunicam_info(dev, \"----Live data----\\n\");\n+\tunicam_info(dev, \"Programmed stride:   %4u\\n\",\n+\t\t    reg_read(dev, UNICAM_IBLS));\n+\tunicam_info(dev, \"Detected resolution: %ux%u\\n\",\n+\t\t    reg_read(dev, UNICAM_IHSTA),\n+\t\t    reg_read(dev, UNICAM_IVSTA));\n+\tunicam_info(dev, \"Write pointer:       %08x\\n\",\n+\t\t    reg_read(dev, UNICAM_IBWP));\n+\n+\treturn 0;\n+}\n+\n+static void unicam_notify(struct v4l2_subdev *sd,\n+\t\t\t  unsigned int notification, void *arg)\n+{\n+\tstruct unicam_device *dev = to_unicam_device(sd->v4l2_dev);\n+\n+\tswitch (notification) {\n+\tcase V4L2_DEVICE_NOTIFY_EVENT:\n+\t\tv4l2_event_queue(&dev->node[IMAGE_PAD].video_dev, arg);\n+\t\tbreak;\n+\tdefault:\n+\t\tbreak;\n+\t}\n+}\n+\n+static const struct vb2_ops unicam_video_qops = {\n+\t.wait_prepare\t\t= vb2_ops_wait_prepare,\n+\t.wait_finish\t\t= vb2_ops_wait_finish,\n+\t.queue_setup\t\t= unicam_queue_setup,\n+\t.buf_prepare\t\t= unicam_buffer_prepare,\n+\t.buf_queue\t\t= unicam_buffer_queue,\n+\t.start_streaming\t= unicam_start_streaming,\n+\t.stop_streaming\t\t= unicam_stop_streaming,\n+};\n+\n+/*\n+ * unicam_v4l2_open : This function is based on the v4l2_fh_open helper\n+ * function. It has been augmented to handle sensor subdevice power management,\n+ */\n+static int unicam_v4l2_open(struct file *file)\n+{\n+\tstruct unicam_node *node = video_drvdata(file);\n+\tstruct unicam_device *dev = node->dev;\n+\tint ret;\n+\n+\tmutex_lock(&node->lock);\n+\n+\tret = v4l2_fh_open(file);\n+\tif (ret) {\n+\t\tunicam_err(dev, \"v4l2_fh_open failed\\n\");\n+\t\tgoto unlock;\n+\t}\n+\n+\tnode->open++;\n+\n+\tif (!v4l2_fh_is_singular_file(file))\n+\t\tgoto unlock;\n+\n+\tret = v4l2_subdev_call(dev->sensor, core, s_power, 1);\n+\tif (ret < 0 && ret != -ENOIOCTLCMD) {\n+\t\tv4l2_fh_release(file);\n+\t\tnode->open--;\n+\t\tgoto unlock;\n+\t}\n+\n+\tret = 0;\n+\n+unlock:\n+\tmutex_unlock(&node->lock);\n+\treturn ret;\n+}\n+\n+static int unicam_v4l2_release(struct file *file)\n+{\n+\tstruct unicam_node *node = video_drvdata(file);\n+\tstruct unicam_device *dev = node->dev;\n+\tstruct v4l2_subdev *sd = dev->sensor;\n+\tbool fh_singular;\n+\tint ret;\n+\n+\tmutex_lock(&node->lock);\n+\n+\tfh_singular = v4l2_fh_is_singular_file(file);\n+\n+\tret = _vb2_fop_release(file, NULL);\n+\n+\tif (fh_singular)\n+\t\tv4l2_subdev_call(sd, core, s_power, 0);\n+\n+\tnode->open--;\n+\tmutex_unlock(&node->lock);\n+\n+\treturn ret;\n+}\n+\n+/* unicam capture driver file operations */\n+static const struct v4l2_file_operations unicam_fops = {\n+\t.owner\t\t= THIS_MODULE,\n+\t.open\t\t= unicam_v4l2_open,\n+\t.release\t= unicam_v4l2_release,\n+\t.read\t\t= vb2_fop_read,\n+\t.poll\t\t= vb2_fop_poll,\n+\t.unlocked_ioctl\t= video_ioctl2,\n+\t.mmap\t\t= vb2_fop_mmap,\n+};\n+\n+/* unicam capture ioctl operations */\n+static const struct v4l2_ioctl_ops unicam_ioctl_ops = {\n+\t.vidioc_querycap\t\t= unicam_querycap,\n+\t.vidioc_enum_fmt_vid_cap\t= unicam_enum_fmt_vid_cap,\n+\t.vidioc_g_fmt_vid_cap\t\t= unicam_g_fmt_vid_cap,\n+\t.vidioc_s_fmt_vid_cap\t\t= unicam_s_fmt_vid_cap,\n+\t.vidioc_try_fmt_vid_cap\t\t= unicam_try_fmt_vid_cap,\n+\n+\t.vidioc_enum_fmt_meta_cap\t= unicam_enum_fmt_meta_cap,\n+\t.vidioc_g_fmt_meta_cap\t\t= unicam_g_fmt_meta_cap,\n+\t.vidioc_s_fmt_meta_cap\t\t= unicam_g_fmt_meta_cap,\n+\t.vidioc_try_fmt_meta_cap\t= unicam_g_fmt_meta_cap,\n+\n+\t.vidioc_enum_input\t\t= unicam_enum_input,\n+\t.vidioc_g_input\t\t\t= unicam_g_input,\n+\t.vidioc_s_input\t\t\t= unicam_s_input,\n+\n+\t.vidioc_querystd\t\t= unicam_querystd,\n+\t.vidioc_s_std\t\t\t= unicam_s_std,\n+\t.vidioc_g_std\t\t\t= unicam_g_std,\n+\n+\t.vidioc_g_edid\t\t\t= unicam_g_edid,\n+\t.vidioc_s_edid\t\t\t= unicam_s_edid,\n+\n+\t.vidioc_enum_framesizes\t\t= unicam_enum_framesizes,\n+\t.vidioc_enum_frameintervals\t= unicam_enum_frameintervals,\n+\n+\t.vidioc_g_selection\t\t= unicam_g_selection,\n+\t.vidioc_s_selection\t\t= unicam_s_selection,\n+\n+\t.vidioc_g_parm\t\t\t= unicam_g_parm,\n+\t.vidioc_s_parm\t\t\t= unicam_s_parm,\n+\n+\t.vidioc_s_dv_timings\t\t= unicam_s_dv_timings,\n+\t.vidioc_g_dv_timings\t\t= unicam_g_dv_timings,\n+\t.vidioc_query_dv_timings\t= unicam_query_dv_timings,\n+\t.vidioc_enum_dv_timings\t\t= unicam_enum_dv_timings,\n+\t.vidioc_dv_timings_cap\t\t= unicam_dv_timings_cap,\n+\n+\t.vidioc_reqbufs\t\t\t= vb2_ioctl_reqbufs,\n+\t.vidioc_create_bufs\t\t= vb2_ioctl_create_bufs,\n+\t.vidioc_prepare_buf\t\t= vb2_ioctl_prepare_buf,\n+\t.vidioc_querybuf\t\t= vb2_ioctl_querybuf,\n+\t.vidioc_qbuf\t\t\t= vb2_ioctl_qbuf,\n+\t.vidioc_dqbuf\t\t\t= vb2_ioctl_dqbuf,\n+\t.vidioc_expbuf\t\t\t= vb2_ioctl_expbuf,\n+\t.vidioc_streamon\t\t= vb2_ioctl_streamon,\n+\t.vidioc_streamoff\t\t= vb2_ioctl_streamoff,\n+\n+\t.vidioc_log_status\t\t= unicam_log_status,\n+\t.vidioc_subscribe_event\t\t= unicam_subscribe_event,\n+\t.vidioc_unsubscribe_event\t= v4l2_event_unsubscribe,\n+};\n+\n+static int\n+unicam_async_bound(struct v4l2_async_notifier *notifier,\n+\t\t   struct v4l2_subdev *subdev,\n+\t\t   struct v4l2_async_subdev *asd)\n+{\n+\tstruct unicam_device *unicam = to_unicam_device(notifier->v4l2_dev);\n+\n+\tif (unicam->sensor) {\n+\t\tunicam_info(unicam, \"Rejecting subdev %s (Already set!!)\",\n+\t\t\t    subdev->name);\n+\t\treturn 0;\n+\t}\n+\n+\tunicam->sensor = subdev;\n+\tunicam_dbg(1, unicam, \"Using sensor %s for capture\\n\", subdev->name);\n+\n+\treturn 0;\n+}\n+\n+static void unicam_release(struct kref *kref)\n+{\n+\tstruct unicam_device *unicam =\n+\t\tcontainer_of(kref, struct unicam_device, kref);\n+\n+\tv4l2_ctrl_handler_free(&unicam->ctrl_handler);\n+\tmedia_device_cleanup(&unicam->mdev);\n+\n+\tif (unicam->sensor_config)\n+\t\tv4l2_subdev_free_pad_config(unicam->sensor_config);\n+\n+\tkfree(unicam);\n+}\n+\n+static void unicam_put(struct unicam_device *unicam)\n+{\n+\tkref_put(&unicam->kref, unicam_release);\n+}\n+\n+static void unicam_get(struct unicam_device *unicam)\n+{\n+\tkref_get(&unicam->kref);\n+}\n+\n+static void unicam_node_release(struct video_device *vdev)\n+{\n+\tstruct unicam_node *node = video_get_drvdata(vdev);\n+\n+\tunicam_put(node->dev);\n+}\n+\n+static int register_node(struct unicam_device *unicam, struct unicam_node *node,\n+\t\t\t enum v4l2_buf_type type, int pad_id)\n+{\n+\tstruct video_device *vdev;\n+\tstruct vb2_queue *q;\n+\tstruct v4l2_mbus_framefmt mbus_fmt = {0};\n+\tconst struct unicam_fmt *fmt;\n+\tint ret;\n+\n+\tif (pad_id == IMAGE_PAD) {\n+\t\tret = __subdev_get_format(unicam, &mbus_fmt, pad_id);\n+\t\tif (ret) {\n+\t\t\tunicam_err(unicam, \"Failed to get_format - ret %d\\n\",\n+\t\t\t\t   ret);\n+\t\t\treturn ret;\n+\t\t}\n+\n+\t\tfmt = find_format_by_code(mbus_fmt.code);\n+\t\tif (!fmt) {\n+\t\t\t/*\n+\t\t\t * Find the first format that the sensor and unicam both\n+\t\t\t * support\n+\t\t\t */\n+\t\t\tfmt = get_first_supported_format(unicam);\n+\n+\t\t\tif (!fmt)\n+\t\t\t\t/* No compatible formats */\n+\t\t\t\treturn -EINVAL;\n+\n+\t\t\tmbus_fmt.code = fmt->code;\n+\t\t\tret = __subdev_set_format(unicam, &mbus_fmt, pad_id);\n+\t\t\tif (ret)\n+\t\t\t\treturn -EINVAL;\n+\t\t}\n+\t\tif (mbus_fmt.field != V4L2_FIELD_NONE) {\n+\t\t\t/* Interlaced not supported - disable it now. */\n+\t\t\tmbus_fmt.field = V4L2_FIELD_NONE;\n+\t\t\tret = __subdev_set_format(unicam, &mbus_fmt, pad_id);\n+\t\t\tif (ret)\n+\t\t\t\treturn -EINVAL;\n+\t\t}\n+\n+\t\tnode->v_fmt.fmt.pix.pixelformat = fmt->fourcc ? fmt->fourcc\n+\t\t\t\t\t\t: fmt->repacked_fourcc;\n+\t} else {\n+\t\t/* Fix this node format as embedded data. */\n+\t\tfmt = find_format_by_code(MEDIA_BUS_FMT_SENSOR_DATA);\n+\t\tnode->v_fmt.fmt.meta.dataformat = fmt->fourcc;\n+\t}\n+\n+\tnode->dev = unicam;\n+\tnode->pad_id = pad_id;\n+\tnode->fmt = fmt;\n+\n+\t/* Read current subdev format */\n+\tunicam_reset_format(node);\n+\n+\tif (v4l2_subdev_has_op(unicam->sensor, video, s_std)) {\n+\t\tv4l2_std_id tvnorms;\n+\n+\t\tif (WARN_ON(!v4l2_subdev_has_op(unicam->sensor, video,\n+\t\t\t\t\t\tg_tvnorms)))\n+\t\t\t/*\n+\t\t\t * Subdevice should not advertise s_std but not\n+\t\t\t * g_tvnorms\n+\t\t\t */\n+\t\t\treturn -EINVAL;\n+\n+\t\tret = v4l2_subdev_call(unicam->sensor, video,\n+\t\t\t\t       g_tvnorms, &tvnorms);\n+\t\tif (WARN_ON(ret))\n+\t\t\treturn -EINVAL;\n+\t\tnode->video_dev.tvnorms |= tvnorms;\n+\t}\n+\n+\tspin_lock_init(&node->dma_queue_lock);\n+\tmutex_init(&node->lock);\n+\n+\tvdev = &node->video_dev;\n+\tif (pad_id == IMAGE_PAD) {\n+\t\t/* Add controls from the subdevice */\n+\t\tret = v4l2_ctrl_add_handler(&unicam->ctrl_handler,\n+\t\t\t\t\t    unicam->sensor->ctrl_handler, NULL,\n+\t\t\t\t\t    true);\n+\t\tif (ret < 0)\n+\t\t\treturn ret;\n+\n+\t\t/*\n+\t\t * If the sensor subdevice has any controls, associate the node\n+\t\t *  with the ctrl handler to allow access from userland.\n+\t\t */\n+\t\tif (!list_empty(&unicam->ctrl_handler.ctrls))\n+\t\t\tvdev->ctrl_handler = &unicam->ctrl_handler;\n+\t}\n+\n+\tq = &node->buffer_queue;\n+\tq->type = type;\n+\tq->io_modes = VB2_MMAP | VB2_DMABUF | VB2_READ;\n+\tq->drv_priv = node;\n+\tq->ops = &unicam_video_qops;\n+\tq->mem_ops = &vb2_dma_contig_memops;\n+\tq->buf_struct_size = sizeof(struct unicam_buffer);\n+\tq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;\n+\tq->lock = &node->lock;\n+\tq->min_buffers_needed = 2;\n+\tq->dev = &unicam->pdev->dev;\n+\n+\tret = vb2_queue_init(q);\n+\tif (ret) {\n+\t\tunicam_err(unicam, \"vb2_queue_init() failed\\n\");\n+\t\treturn ret;\n+\t}\n+\n+\tINIT_LIST_HEAD(&node->dma_queue);\n+\n+\tvdev->release = unicam_node_release;\n+\tvdev->fops = &unicam_fops;\n+\tvdev->ioctl_ops = &unicam_ioctl_ops;\n+\tvdev->v4l2_dev = &unicam->v4l2_dev;\n+\tvdev->vfl_dir = VFL_DIR_RX;\n+\tvdev->queue = q;\n+\tvdev->lock = &node->lock;\n+\tvdev->device_caps = (pad_id == IMAGE_PAD) ?\n+\t\t\t    (V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING) :\n+\t\t\t    (V4L2_CAP_META_CAPTURE | V4L2_CAP_STREAMING);\n+\n+\t/* Define the device names */\n+\tsnprintf(vdev->name, sizeof(vdev->name), \"%s-%s\", UNICAM_MODULE_NAME,\n+\t\t pad_id == IMAGE_PAD ? \"image\" : \"embedded\");\n+\n+\tvideo_set_drvdata(vdev, node);\n+\tif (pad_id == IMAGE_PAD)\n+\t\tvdev->entity.flags |= MEDIA_ENT_FL_DEFAULT;\n+\tnode->pad.flags = MEDIA_PAD_FL_SINK;\n+\tmedia_entity_pads_init(&vdev->entity, 1, &node->pad);\n+\n+\tnode->dummy_buf_cpu_addr = dma_alloc_coherent(&unicam->pdev->dev,\n+\t\t\t\t\t\t      DUMMY_BUF_SIZE,\n+\t\t\t\t\t\t      &node->dummy_buf_dma_addr,\n+\t\t\t\t\t\t      GFP_KERNEL);\n+\tif (!node->dummy_buf_cpu_addr) {\n+\t\tunicam_err(unicam, \"Unable to allocate dummy buffer.\\n\");\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\tif (pad_id == METADATA_PAD) {\n+\t\tv4l2_disable_ioctl(vdev, VIDIOC_DQEVENT);\n+\t\tv4l2_disable_ioctl(vdev, VIDIOC_SUBSCRIBE_EVENT);\n+\t\tv4l2_disable_ioctl(vdev, VIDIOC_UNSUBSCRIBE_EVENT);\n+\t}\n+\tif (pad_id == METADATA_PAD ||\n+\t    !v4l2_subdev_has_op(unicam->sensor, video, s_std)) {\n+\t\tv4l2_disable_ioctl(&node->video_dev, VIDIOC_S_STD);\n+\t\tv4l2_disable_ioctl(&node->video_dev, VIDIOC_G_STD);\n+\t\tv4l2_disable_ioctl(&node->video_dev, VIDIOC_ENUMSTD);\n+\t}\n+\tif (pad_id == METADATA_PAD ||\n+\t    !v4l2_subdev_has_op(unicam->sensor, video, querystd))\n+\t\tv4l2_disable_ioctl(&node->video_dev, VIDIOC_QUERYSTD);\n+\tif (pad_id == METADATA_PAD ||\n+\t    !v4l2_subdev_has_op(unicam->sensor, video, s_dv_timings)) {\n+\t\tv4l2_disable_ioctl(&node->video_dev, VIDIOC_S_EDID);\n+\t\tv4l2_disable_ioctl(&node->video_dev, VIDIOC_G_EDID);\n+\t\tv4l2_disable_ioctl(&node->video_dev, VIDIOC_DV_TIMINGS_CAP);\n+\t\tv4l2_disable_ioctl(&node->video_dev, VIDIOC_G_DV_TIMINGS);\n+\t\tv4l2_disable_ioctl(&node->video_dev, VIDIOC_S_DV_TIMINGS);\n+\t\tv4l2_disable_ioctl(&node->video_dev, VIDIOC_ENUM_DV_TIMINGS);\n+\t\tv4l2_disable_ioctl(&node->video_dev, VIDIOC_QUERY_DV_TIMINGS);\n+\t}\n+\tif (pad_id == METADATA_PAD ||\n+\t    !v4l2_subdev_has_op(unicam->sensor, pad, enum_frame_interval))\n+\t\tv4l2_disable_ioctl(&node->video_dev,\n+\t\t\t\t   VIDIOC_ENUM_FRAMEINTERVALS);\n+\tif (pad_id == METADATA_PAD ||\n+\t    !v4l2_subdev_has_op(unicam->sensor, video, g_frame_interval))\n+\t\tv4l2_disable_ioctl(&node->video_dev, VIDIOC_G_PARM);\n+\tif (pad_id == METADATA_PAD ||\n+\t    !v4l2_subdev_has_op(unicam->sensor, video, s_frame_interval))\n+\t\tv4l2_disable_ioctl(&node->video_dev, VIDIOC_S_PARM);\n+\n+\tif (pad_id == METADATA_PAD ||\n+\t    !v4l2_subdev_has_op(unicam->sensor, pad, enum_frame_size))\n+\t\tv4l2_disable_ioctl(&node->video_dev, VIDIOC_ENUM_FRAMESIZES);\n+\n+\tif (node->pad_id == METADATA_PAD ||\n+\t    !v4l2_subdev_has_op(unicam->sensor, pad, set_selection))\n+\t\tv4l2_disable_ioctl(&node->video_dev, VIDIOC_S_SELECTION);\n+\n+\tif (node->pad_id == METADATA_PAD ||\n+\t    !v4l2_subdev_has_op(unicam->sensor, pad, get_selection))\n+\t\tv4l2_disable_ioctl(&node->video_dev, VIDIOC_G_SELECTION);\n+\n+\tret = video_register_device(vdev, VFL_TYPE_VIDEO, -1);\n+\tif (ret) {\n+\t\tunicam_err(unicam, \"Unable to register video device %s\\n\",\n+\t\t\t   vdev->name);\n+\t\treturn ret;\n+\t}\n+\n+\t/*\n+\t * Acquire a reference to unicam, which will be released when the video\n+\t * device will be unregistered and userspace will have closed all open\n+\t * file handles.\n+\t */\n+\tunicam_get(unicam);\n+\tnode->registered = true;\n+\n+\tif (pad_id != METADATA_PAD || unicam->sensor_embedded_data) {\n+\t\tret = media_create_pad_link(&unicam->sensor->entity, pad_id,\n+\t\t\t\t\t    &node->video_dev.entity, 0,\n+\t\t\t\t\t    MEDIA_LNK_FL_ENABLED |\n+\t\t\t\t\t    MEDIA_LNK_FL_IMMUTABLE);\n+\t\tif (ret)\n+\t\t\tunicam_err(unicam, \"Unable to create pad link for %s\\n\",\n+\t\t\t\t   vdev->name);\n+\t}\n+\n+\treturn ret;\n+}\n+\n+static void unregister_nodes(struct unicam_device *unicam)\n+{\n+\tunsigned int i;\n+\n+\tfor (i = 0; i < ARRAY_SIZE(unicam->node); i++) {\n+\t\tstruct unicam_node *node = &unicam->node[i];\n+\n+\t\tif (node->dummy_buf_cpu_addr) {\n+\t\t\tdma_free_coherent(&unicam->pdev->dev, DUMMY_BUF_SIZE,\n+\t\t\t\t\t  node->dummy_buf_cpu_addr,\n+\t\t\t\t\t  node->dummy_buf_dma_addr);\n+\t\t}\n+\n+\t\tif (node->registered) {\n+\t\t\tnode->registered = false;\n+\t\t\tvideo_unregister_device(&node->video_dev);\n+\t\t}\n+\t}\n+}\n+\n+static int unicam_probe_complete(struct unicam_device *unicam)\n+{\n+\tint ret;\n+\n+\tunicam->v4l2_dev.notify = unicam_notify;\n+\n+\tunicam->sensor_config = v4l2_subdev_alloc_pad_config(unicam->sensor);\n+\tif (!unicam->sensor_config)\n+\t\treturn -ENOMEM;\n+\n+\tunicam->sensor_embedded_data = (unicam->sensor->entity.num_pads >= 2);\n+\n+\tret = register_node(unicam, &unicam->node[IMAGE_PAD],\n+\t\t\t    V4L2_BUF_TYPE_VIDEO_CAPTURE, IMAGE_PAD);\n+\tif (ret) {\n+\t\tunicam_err(unicam, \"Unable to register image video device.\\n\");\n+\t\tgoto unregister;\n+\t}\n+\n+\tret = register_node(unicam, &unicam->node[METADATA_PAD],\n+\t\t\t    V4L2_BUF_TYPE_META_CAPTURE, METADATA_PAD);\n+\tif (ret) {\n+\t\tunicam_err(unicam, \"Unable to register metadata video device.\\n\");\n+\t\tgoto unregister;\n+\t}\n+\n+\tret = v4l2_device_register_ro_subdev_nodes(&unicam->v4l2_dev);\n+\tif (ret) {\n+\t\tunicam_err(unicam, \"Unable to register subdev nodes.\\n\");\n+\t\tgoto unregister;\n+\t}\n+\n+\t/*\n+\t * Release the initial reference, all references are now owned by the\n+\t * video devices.\n+\t */\n+\tunicam_put(unicam);\n+\treturn 0;\n+\n+unregister:\n+\tunregister_nodes(unicam);\n+\tunicam_put(unicam);\n+\n+\treturn ret;\n+}\n+\n+static int unicam_async_complete(struct v4l2_async_notifier *notifier)\n+{\n+\tstruct unicam_device *unicam = to_unicam_device(notifier->v4l2_dev);\n+\n+\treturn unicam_probe_complete(unicam);\n+}\n+\n+static const struct v4l2_async_notifier_operations unicam_async_ops = {\n+\t.bound = unicam_async_bound,\n+\t.complete = unicam_async_complete,\n+};\n+\n+static int of_unicam_connect_subdevs(struct unicam_device *dev)\n+{\n+\tstruct platform_device *pdev = dev->pdev;\n+\tstruct v4l2_fwnode_endpoint ep = { 0 };\n+\tstruct device_node *ep_node;\n+\tstruct device_node *sensor_node;\n+\tunsigned int lane;\n+\tint ret = -EINVAL;\n+\n+\tif (of_property_read_u32(pdev->dev.of_node, \"brcm,num-data-lanes\",\n+\t\t\t\t &dev->max_data_lanes) < 0) {\n+\t\tunicam_err(dev, \"number of data lanes not set\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\t/* Get the local endpoint and remote device. */\n+\tep_node = of_graph_get_next_endpoint(pdev->dev.of_node, NULL);\n+\tif (!ep_node) {\n+\t\tunicam_dbg(3, dev, \"can't get next endpoint\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tunicam_dbg(3, dev, \"ep_node is %pOF\\n\", ep_node);\n+\n+\tsensor_node = of_graph_get_remote_port_parent(ep_node);\n+\tif (!sensor_node) {\n+\t\tunicam_dbg(3, dev, \"can't get remote parent\\n\");\n+\t\tgoto cleanup_exit;\n+\t}\n+\n+\tunicam_dbg(1, dev, \"found subdevice %pOF\\n\", sensor_node);\n+\n+\t/* Parse the local endpoint and validate its configuration. */\n+\tv4l2_fwnode_endpoint_parse(of_fwnode_handle(ep_node), &ep);\n+\n+\tunicam_dbg(3, dev, \"parsed local endpoint, bus_type %u\\n\",\n+\t\t   ep.bus_type);\n+\n+\tdev->bus_type = ep.bus_type;\n+\n+\tswitch (ep.bus_type) {\n+\tcase V4L2_MBUS_CSI2_DPHY:\n+\t\tswitch (ep.bus.mipi_csi2.num_data_lanes) {\n+\t\tcase 1:\n+\t\tcase 2:\n+\t\tcase 4:\n+\t\t\tbreak;\n+\n+\t\tdefault:\n+\t\t\tunicam_err(dev, \"subdevice %pOF: %u data lanes not supported\\n\",\n+\t\t\t\t   sensor_node,\n+\t\t\t\t   ep.bus.mipi_csi2.num_data_lanes);\n+\t\t\tgoto cleanup_exit;\n+\t\t}\n+\n+\t\tfor (lane = 0; lane < ep.bus.mipi_csi2.num_data_lanes; lane++) {\n+\t\t\tif (ep.bus.mipi_csi2.data_lanes[lane] != lane + 1) {\n+\t\t\t\tunicam_err(dev, \"subdevice %pOF: data lanes reordering not supported\\n\",\n+\t\t\t\t\t   sensor_node);\n+\t\t\t\tgoto cleanup_exit;\n+\t\t\t}\n+\t\t}\n+\n+\t\tif (ep.bus.mipi_csi2.num_data_lanes > dev->max_data_lanes) {\n+\t\t\tunicam_err(dev, \"subdevice requires %u data lanes when %u are supported\\n\",\n+\t\t\t\t   ep.bus.mipi_csi2.num_data_lanes,\n+\t\t\t\t   dev->max_data_lanes);\n+\t\t}\n+\n+\t\tdev->max_data_lanes = ep.bus.mipi_csi2.num_data_lanes;\n+\t\tdev->bus_flags = ep.bus.mipi_csi2.flags;\n+\n+\t\tbreak;\n+\n+\tcase V4L2_MBUS_CCP2:\n+\t\tif (ep.bus.mipi_csi1.clock_lane != 0 ||\n+\t\t    ep.bus.mipi_csi1.data_lane != 1) {\n+\t\t\tunicam_err(dev, \"subdevice %pOF: unsupported lanes configuration\\n\",\n+\t\t\t\t   sensor_node);\n+\t\t\tgoto cleanup_exit;\n+\t\t}\n+\n+\t\tdev->max_data_lanes = 1;\n+\t\tdev->bus_flags = ep.bus.mipi_csi1.strobe;\n+\t\tbreak;\n+\n+\tdefault:\n+\t\t/* Unsupported bus type */\n+\t\tunicam_err(dev, \"subdevice %pOF: unsupported bus type %u\\n\",\n+\t\t\t   sensor_node, ep.bus_type);\n+\t\tgoto cleanup_exit;\n+\t}\n+\n+\tunicam_dbg(3, dev, \"subdevice %pOF: %s bus, %u data lanes, flags=0x%08x\\n\",\n+\t\t   sensor_node,\n+\t\t   dev->bus_type == V4L2_MBUS_CSI2_DPHY ? \"CSI-2\" : \"CCP2\",\n+\t\t   dev->max_data_lanes, dev->bus_flags);\n+\n+\t/* Initialize and register the async notifier. */\n+\tv4l2_async_notifier_init(&dev->notifier);\n+\tdev->notifier.ops = &unicam_async_ops;\n+\n+\tdev->asd.match_type = V4L2_ASYNC_MATCH_FWNODE;\n+\tdev->asd.match.fwnode = of_fwnode_handle(sensor_node);\n+\tret = v4l2_async_notifier_add_subdev(&dev->notifier, &dev->asd);\n+\tif (ret) {\n+\t\tunicam_err(dev, \"Error adding subdevice: %d\\n\", ret);\n+\t\tgoto cleanup_exit;\n+\t}\n+\n+\tret = v4l2_async_notifier_register(&dev->v4l2_dev, &dev->notifier);\n+\tif (ret) {\n+\t\tunicam_err(dev, \"Error registering async notifier: %d\\n\", ret);\n+\t\tret = -EINVAL;\n+\t}\n+\n+cleanup_exit:\n+\tof_node_put(sensor_node);\n+\tof_node_put(ep_node);\n+\n+\treturn ret;\n+}\n+\n+static int unicam_probe(struct platform_device *pdev)\n+{\n+\tstruct unicam_device *unicam;\n+\tint ret;\n+\n+\tunicam = kzalloc(sizeof(*unicam), GFP_KERNEL);\n+\tif (!unicam)\n+\t\treturn -ENOMEM;\n+\n+\tkref_init(&unicam->kref);\n+\tunicam->pdev = pdev;\n+\n+\tunicam->base = devm_platform_ioremap_resource(pdev, 0);\n+\tif (IS_ERR(unicam->base)) {\n+\t\tunicam_err(unicam, \"Failed to get main io block\\n\");\n+\t\tret = PTR_ERR(unicam->base);\n+\t\tgoto err_unicam_put;\n+\t}\n+\n+\tunicam->clk_gate_base = devm_platform_ioremap_resource(pdev, 1);\n+\tif (IS_ERR(unicam->clk_gate_base)) {\n+\t\tunicam_err(unicam, \"Failed to get 2nd io block\\n\");\n+\t\tret = PTR_ERR(unicam->clk_gate_base);\n+\t\tgoto err_unicam_put;\n+\t}\n+\n+\tunicam->clock = devm_clk_get(&pdev->dev, \"lp\");\n+\tif (IS_ERR(unicam->clock)) {\n+\t\tunicam_err(unicam, \"Failed to get clock\\n\");\n+\t\tret = PTR_ERR(unicam->clock);\n+\t\tgoto err_unicam_put;\n+\t}\n+\n+\tret = platform_get_irq(pdev, 0);\n+\tif (ret <= 0) {\n+\t\tdev_err(&pdev->dev, \"No IRQ resource\\n\");\n+\t\tret = -EINVAL;\n+\t\tgoto err_unicam_put;\n+\t}\n+\n+\tret = devm_request_irq(&pdev->dev, ret, unicam_isr, 0,\n+\t\t\t       \"unicam_capture0\", unicam);\n+\tif (ret) {\n+\t\tdev_err(&pdev->dev, \"Unable to request interrupt\\n\");\n+\t\tret = -EINVAL;\n+\t\tgoto err_unicam_put;\n+\t}\n+\n+\tunicam->mdev.dev = &pdev->dev;\n+\tstrscpy(unicam->mdev.model, UNICAM_MODULE_NAME,\n+\t\tsizeof(unicam->mdev.model));\n+\tstrscpy(unicam->mdev.serial, \"\", sizeof(unicam->mdev.serial));\n+\tsnprintf(unicam->mdev.bus_info, sizeof(unicam->mdev.bus_info),\n+\t\t \"platform:%s\", dev_name(&pdev->dev));\n+\tunicam->mdev.hw_revision = 0;\n+\n+\tmedia_device_init(&unicam->mdev);\n+\n+\tunicam->v4l2_dev.mdev = &unicam->mdev;\n+\n+\tret = v4l2_device_register(&pdev->dev, &unicam->v4l2_dev);\n+\tif (ret) {\n+\t\tunicam_err(unicam,\n+\t\t\t   \"Unable to register v4l2 device.\\n\");\n+\t\tgoto err_unicam_put;\n+\t}\n+\n+\tret = media_device_register(&unicam->mdev);\n+\tif (ret < 0) {\n+\t\tunicam_err(unicam,\n+\t\t\t   \"Unable to register media-controller device.\\n\");\n+\t\tgoto err_v4l2_unregister;\n+\t}\n+\n+\t/* Reserve space for the controls */\n+\tret = v4l2_ctrl_handler_init(&unicam->ctrl_handler, 16);\n+\tif (ret < 0)\n+\t\tgoto err_media_unregister;\n+\n+\t/* set the driver data in platform device */\n+\tplatform_set_drvdata(pdev, unicam);\n+\n+\tret = of_unicam_connect_subdevs(unicam);\n+\tif (ret) {\n+\t\tdev_err(&pdev->dev, \"Failed to connect subdevs\\n\");\n+\t\tgoto err_media_unregister;\n+\t}\n+\n+\t/* Enable the block power domain */\n+\tpm_runtime_enable(&pdev->dev);\n+\n+\treturn 0;\n+\n+err_media_unregister:\n+\tmedia_device_unregister(&unicam->mdev);\n+err_v4l2_unregister:\n+\tv4l2_device_unregister(&unicam->v4l2_dev);\n+err_unicam_put:\n+\tunicam_put(unicam);\n+\n+\treturn ret;\n+}\n+\n+static int unicam_remove(struct platform_device *pdev)\n+{\n+\tstruct unicam_device *unicam = platform_get_drvdata(pdev);\n+\n+\tunicam_dbg(2, unicam, \"%s\\n\", __func__);\n+\n+\tv4l2_async_notifier_unregister(&unicam->notifier);\n+\tv4l2_device_unregister(&unicam->v4l2_dev);\n+\tmedia_device_unregister(&unicam->mdev);\n+\tunregister_nodes(unicam);\n+\n+\tpm_runtime_disable(&pdev->dev);\n+\n+\treturn 0;\n+}\n+\n+static const struct of_device_id unicam_of_match[] = {\n+\t{ .compatible = \"brcm,bcm2835-unicam\", },\n+\t{ /* sentinel */ },\n+};\n+MODULE_DEVICE_TABLE(of, unicam_of_match);\n+\n+static struct platform_driver unicam_driver = {\n+\t.probe\t\t= unicam_probe,\n+\t.remove\t\t= unicam_remove,\n+\t.driver = {\n+\t\t.name\t= UNICAM_MODULE_NAME,\n+\t\t.of_match_table = of_match_ptr(unicam_of_match),\n+\t},\n+};\n+\n+module_platform_driver(unicam_driver);\n+\n+MODULE_AUTHOR(\"Dave Stevenson <dave.stevenson@raspberrypi.com>\");\n+MODULE_DESCRIPTION(\"BCM2835 Unicam driver\");\n+MODULE_LICENSE(\"GPL\");\n+MODULE_VERSION(UNICAM_VERSION);\n--- /dev/null\n+++ b/drivers/media/platform/bcm2835/vc4-regs-unicam.h\n@@ -0,0 +1,253 @@\n+/* SPDX-License-Identifier: GPL-2.0-only */\n+\n+/*\n+ * Copyright (C) 2017-2020 Raspberry Pi Trading.\n+ * Dave Stevenson <dave.stevenson@raspberrypi.com>\n+ */\n+\n+#ifndef VC4_REGS_UNICAM_H\n+#define VC4_REGS_UNICAM_H\n+\n+/*\n+ * The following values are taken from files found within the code drop\n+ * made by Broadcom for the BCM21553 Graphics Driver, predominantly in\n+ * brcm_usrlib/dag/vmcsx/vcinclude/hardware_vc4.h.\n+ * They have been modified to be only the register offset.\n+ */\n+#define UNICAM_CTRL\t0x000\n+#define UNICAM_STA\t0x004\n+#define UNICAM_ANA\t0x008\n+#define UNICAM_PRI\t0x00c\n+#define UNICAM_CLK\t0x010\n+#define UNICAM_CLT\t0x014\n+#define UNICAM_DAT0\t0x018\n+#define UNICAM_DAT1\t0x01c\n+#define UNICAM_DAT2\t0x020\n+#define UNICAM_DAT3\t0x024\n+#define UNICAM_DLT\t0x028\n+#define UNICAM_CMP0\t0x02c\n+#define UNICAM_CMP1\t0x030\n+#define UNICAM_CAP0\t0x034\n+#define UNICAM_CAP1\t0x038\n+#define UNICAM_ICTL\t0x100\n+#define UNICAM_ISTA\t0x104\n+#define UNICAM_IDI0\t0x108\n+#define UNICAM_IPIPE\t0x10c\n+#define UNICAM_IBSA0\t0x110\n+#define UNICAM_IBEA0\t0x114\n+#define UNICAM_IBLS\t0x118\n+#define UNICAM_IBWP\t0x11c\n+#define UNICAM_IHWIN\t0x120\n+#define UNICAM_IHSTA\t0x124\n+#define UNICAM_IVWIN\t0x128\n+#define UNICAM_IVSTA\t0x12c\n+#define UNICAM_ICC\t0x130\n+#define UNICAM_ICS\t0x134\n+#define UNICAM_IDC\t0x138\n+#define UNICAM_IDPO\t0x13c\n+#define UNICAM_IDCA\t0x140\n+#define UNICAM_IDCD\t0x144\n+#define UNICAM_IDS\t0x148\n+#define UNICAM_DCS\t0x200\n+#define UNICAM_DBSA0\t0x204\n+#define UNICAM_DBEA0\t0x208\n+#define UNICAM_DBWP\t0x20c\n+#define UNICAM_DBCTL\t0x300\n+#define UNICAM_IBSA1\t0x304\n+#define UNICAM_IBEA1\t0x308\n+#define UNICAM_IDI1\t0x30c\n+#define UNICAM_DBSA1\t0x310\n+#define UNICAM_DBEA1\t0x314\n+#define UNICAM_MISC\t0x400\n+\n+/*\n+ * The following bitmasks are from the kernel released by Broadcom\n+ * for Android - https://android.googlesource.com/kernel/bcm/\n+ * The Rhea, Hawaii, and Java chips all contain the same VideoCore4\n+ * Unicam block as BCM2835, as defined in eg\n+ * arch/arm/mach-rhea/include/mach/rdb_A0/brcm_rdb_cam.h and similar.\n+ * Values reworked to use the kernel BIT and GENMASK macros.\n+ *\n+ * Some of the bit mnenomics have been amended to match the datasheet.\n+ */\n+/* UNICAM_CTRL Register */\n+#define UNICAM_CPE\t\tBIT(0)\n+#define UNICAM_MEM\t\tBIT(1)\n+#define UNICAM_CPR\t\tBIT(2)\n+#define UNICAM_CPM_MASK\t\tGENMASK(3, 3)\n+#define UNICAM_CPM_CSI2\t\t0\n+#define UNICAM_CPM_CCP2\t\t1\n+#define UNICAM_SOE\t\tBIT(4)\n+#define UNICAM_DCM_MASK\t\tGENMASK(5, 5)\n+#define UNICAM_DCM_STROBE\t0\n+#define UNICAM_DCM_DATA\t\t1\n+#define UNICAM_SLS\t\tBIT(6)\n+#define UNICAM_PFT_MASK\t\tGENMASK(11, 8)\n+#define UNICAM_OET_MASK\t\tGENMASK(20, 12)\n+\n+/* UNICAM_STA Register */\n+#define UNICAM_SYN\t\tBIT(0)\n+#define UNICAM_CS\t\tBIT(1)\n+#define UNICAM_SBE\t\tBIT(2)\n+#define UNICAM_PBE\t\tBIT(3)\n+#define UNICAM_HOE\t\tBIT(4)\n+#define UNICAM_PLE\t\tBIT(5)\n+#define UNICAM_SSC\t\tBIT(6)\n+#define UNICAM_CRCE\t\tBIT(7)\n+#define UNICAM_OES\t\tBIT(8)\n+#define UNICAM_IFO\t\tBIT(9)\n+#define UNICAM_OFO\t\tBIT(10)\n+#define UNICAM_BFO\t\tBIT(11)\n+#define UNICAM_DL\t\tBIT(12)\n+#define UNICAM_PS\t\tBIT(13)\n+#define UNICAM_IS\t\tBIT(14)\n+#define UNICAM_PI0\t\tBIT(15)\n+#define UNICAM_PI1\t\tBIT(16)\n+#define UNICAM_FSI_S\t\tBIT(17)\n+#define UNICAM_FEI_S\t\tBIT(18)\n+#define UNICAM_LCI_S\t\tBIT(19)\n+#define UNICAM_BUF0_RDY\t\tBIT(20)\n+#define UNICAM_BUF0_NO\t\tBIT(21)\n+#define UNICAM_BUF1_RDY\t\tBIT(22)\n+#define UNICAM_BUF1_NO\t\tBIT(23)\n+#define UNICAM_DI\t\tBIT(24)\n+\n+#define UNICAM_STA_MASK_ALL \\\n+\t\t(UNICAM_DL + \\\n+\t\tUNICAM_SBE + \\\n+\t\tUNICAM_PBE + \\\n+\t\tUNICAM_HOE + \\\n+\t\tUNICAM_PLE + \\\n+\t\tUNICAM_SSC + \\\n+\t\tUNICAM_CRCE + \\\n+\t\tUNICAM_IFO + \\\n+\t\tUNICAM_OFO + \\\n+\t\tUNICAM_PS + \\\n+\t\tUNICAM_PI0 + \\\n+\t\tUNICAM_PI1)\n+\n+/* UNICAM_ANA Register */\n+#define UNICAM_APD\t\tBIT(0)\n+#define UNICAM_BPD\t\tBIT(1)\n+#define UNICAM_AR\t\tBIT(2)\n+#define UNICAM_DDL\t\tBIT(3)\n+#define UNICAM_CTATADJ_MASK\tGENMASK(7, 4)\n+#define UNICAM_PTATADJ_MASK\tGENMASK(11, 8)\n+\n+/* UNICAM_PRI Register */\n+#define UNICAM_PE\t\tBIT(0)\n+#define UNICAM_PT_MASK\t\tGENMASK(2, 1)\n+#define UNICAM_NP_MASK\t\tGENMASK(7, 4)\n+#define UNICAM_PP_MASK\t\tGENMASK(11, 8)\n+#define UNICAM_BS_MASK\t\tGENMASK(15, 12)\n+#define UNICAM_BL_MASK\t\tGENMASK(17, 16)\n+\n+/* UNICAM_CLK Register */\n+#define UNICAM_CLE\t\tBIT(0)\n+#define UNICAM_CLPD\t\tBIT(1)\n+#define UNICAM_CLLPE\t\tBIT(2)\n+#define UNICAM_CLHSE\t\tBIT(3)\n+#define UNICAM_CLTRE\t\tBIT(4)\n+#define UNICAM_CLAC_MASK\tGENMASK(8, 5)\n+#define UNICAM_CLSTE\t\tBIT(29)\n+\n+/* UNICAM_CLT Register */\n+#define UNICAM_CLT1_MASK\tGENMASK(7, 0)\n+#define UNICAM_CLT2_MASK\tGENMASK(15, 8)\n+\n+/* UNICAM_DATn Registers */\n+#define UNICAM_DLE\t\tBIT(0)\n+#define UNICAM_DLPD\t\tBIT(1)\n+#define UNICAM_DLLPE\t\tBIT(2)\n+#define UNICAM_DLHSE\t\tBIT(3)\n+#define UNICAM_DLTRE\t\tBIT(4)\n+#define UNICAM_DLSM\t\tBIT(5)\n+#define UNICAM_DLFO\t\tBIT(28)\n+#define UNICAM_DLSTE\t\tBIT(29)\n+\n+#define UNICAM_DAT_MASK_ALL (UNICAM_DLSTE + UNICAM_DLFO)\n+\n+/* UNICAM_DLT Register */\n+#define UNICAM_DLT1_MASK\tGENMASK(7, 0)\n+#define UNICAM_DLT2_MASK\tGENMASK(15, 8)\n+#define UNICAM_DLT3_MASK\tGENMASK(23, 16)\n+\n+/* UNICAM_ICTL Register */\n+#define UNICAM_FSIE\t\tBIT(0)\n+#define UNICAM_FEIE\t\tBIT(1)\n+#define UNICAM_IBOB\t\tBIT(2)\n+#define UNICAM_FCM\t\tBIT(3)\n+#define UNICAM_TFC\t\tBIT(4)\n+#define UNICAM_LIP_MASK\t\tGENMASK(6, 5)\n+#define UNICAM_LCIE_MASK\tGENMASK(28, 16)\n+\n+/* UNICAM_IDI0/1 Register */\n+#define UNICAM_ID0_MASK\t\tGENMASK(7, 0)\n+#define UNICAM_ID1_MASK\t\tGENMASK(15, 8)\n+#define UNICAM_ID2_MASK\t\tGENMASK(23, 16)\n+#define UNICAM_ID3_MASK\t\tGENMASK(31, 24)\n+\n+/* UNICAM_ISTA Register */\n+#define UNICAM_FSI\t\tBIT(0)\n+#define UNICAM_FEI\t\tBIT(1)\n+#define UNICAM_LCI\t\tBIT(2)\n+\n+#define UNICAM_ISTA_MASK_ALL (UNICAM_FSI + UNICAM_FEI + UNICAM_LCI)\n+\n+/* UNICAM_IPIPE Register */\n+#define UNICAM_PUM_MASK\t\tGENMASK(2, 0)\n+\t\t/* Unpacking modes */\n+\t\t#define UNICAM_PUM_NONE\t\t0\n+\t\t#define UNICAM_PUM_UNPACK6\t1\n+\t\t#define UNICAM_PUM_UNPACK7\t2\n+\t\t#define UNICAM_PUM_UNPACK8\t3\n+\t\t#define UNICAM_PUM_UNPACK10\t4\n+\t\t#define UNICAM_PUM_UNPACK12\t5\n+\t\t#define UNICAM_PUM_UNPACK14\t6\n+\t\t#define UNICAM_PUM_UNPACK16\t7\n+#define UNICAM_DDM_MASK\t\tGENMASK(6, 3)\n+#define UNICAM_PPM_MASK\t\tGENMASK(9, 7)\n+\t\t/* Packing modes */\n+\t\t#define UNICAM_PPM_NONE\t\t0\n+\t\t#define UNICAM_PPM_PACK8\t1\n+\t\t#define UNICAM_PPM_PACK10\t2\n+\t\t#define UNICAM_PPM_PACK12\t3\n+\t\t#define UNICAM_PPM_PACK14\t4\n+\t\t#define UNICAM_PPM_PACK16\t5\n+#define UNICAM_DEM_MASK\t\tGENMASK(11, 10)\n+#define UNICAM_DEBL_MASK\tGENMASK(14, 12)\n+#define UNICAM_ICM_MASK\t\tGENMASK(16, 15)\n+#define UNICAM_IDM_MASK\t\tGENMASK(17, 17)\n+\n+/* UNICAM_ICC Register */\n+#define UNICAM_ICFL_MASK\tGENMASK(4, 0)\n+#define UNICAM_ICFH_MASK\tGENMASK(9, 5)\n+#define UNICAM_ICST_MASK\tGENMASK(12, 10)\n+#define UNICAM_ICLT_MASK\tGENMASK(15, 13)\n+#define UNICAM_ICLL_MASK\tGENMASK(31, 16)\n+\n+/* UNICAM_DCS Register */\n+#define UNICAM_DIE\t\tBIT(0)\n+#define UNICAM_DIM\t\tBIT(1)\n+#define UNICAM_DBOB\t\tBIT(3)\n+#define UNICAM_FDE\t\tBIT(4)\n+#define UNICAM_LDP\t\tBIT(5)\n+#define UNICAM_EDL_MASK\t\tGENMASK(15, 8)\n+\n+/* UNICAM_DBCTL Register */\n+#define UNICAM_DBEN\t\tBIT(0)\n+#define UNICAM_BUF0_IE\t\tBIT(1)\n+#define UNICAM_BUF1_IE\t\tBIT(2)\n+\n+/* UNICAM_CMP[0,1] register */\n+#define UNICAM_PCE\t\tBIT(31)\n+#define UNICAM_GI\t\tBIT(9)\n+#define UNICAM_CPH\t\tBIT(8)\n+#define UNICAM_PCVC_MASK\tGENMASK(7, 6)\n+#define UNICAM_PCDT_MASK\tGENMASK(5, 0)\n+\n+/* UNICAM_MISC register */\n+#define UNICAM_FL0\t\tBIT(6)\n+#define UNICAM_FL1\t\tBIT(9)\n+\n+#endif\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0265-media-bcm2835-unicam-Add-support-for-get_mbus_config.patch",
    "content": "From 80a9aa25edc6144c3d6d3aaf9f731240d8868714 Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Tue, 23 Jun 2020 14:32:51 +0100\nSubject: [PATCH] media: bcm2835-unicam: Add support for\n get_mbus_config to set num lanes\n\nUse the get_mbus_config pad subdev call to allow a source to use\nfewer than the number of CSI2 lanes defined in device tree.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n .../media/platform/bcm2835/bcm2835-unicam.c   | 31 ++++++++++++++++---\n 1 file changed, 27 insertions(+), 4 deletions(-)\n\n--- a/drivers/media/platform/bcm2835/bcm2835-unicam.c\n+++ b/drivers/media/platform/bcm2835/bcm2835-unicam.c\n@@ -1639,12 +1639,35 @@ static int unicam_start_streaming(struct\n \t\tgoto err_streaming;\n \t}\n \n-\t/*\n-\t * TODO: Retrieve the number of active data lanes from the connected\n-\t * subdevice.\n-\t */\n \tdev->active_data_lanes = dev->max_data_lanes;\n \n+\tif (dev->bus_type == V4L2_MBUS_CSI2_DPHY) {\n+\t\tstruct v4l2_mbus_config mbus_config = { 0 };\n+\n+\t\tret = v4l2_subdev_call(dev->sensor, pad, get_mbus_config,\n+\t\t\t\t       0, &mbus_config);\n+\t\tif (ret < 0 && ret != -ENOIOCTLCMD) {\n+\t\t\tunicam_dbg(3, dev, \"g_mbus_config failed\\n\");\n+\t\t\tgoto err_pm_put;\n+\t\t}\n+\n+\t\tdev->active_data_lanes =\n+\t\t\t(mbus_config.flags & V4L2_MBUS_CSI2_LANE_MASK) >>\n+\t\t\t\t\t__ffs(V4L2_MBUS_CSI2_LANE_MASK);\n+\t\tif (!dev->active_data_lanes)\n+\t\t\tdev->active_data_lanes = dev->max_data_lanes;\n+\t\tif (dev->active_data_lanes > dev->max_data_lanes) {\n+\t\t\tunicam_err(dev, \"Device has requested %u data lanes, which is >%u configured in DT\\n\",\n+\t\t\t\t   dev->active_data_lanes,\n+\t\t\t\t   dev->max_data_lanes);\n+\t\t\tret = -EINVAL;\n+\t\t\tgoto err_pm_put;\n+\t\t}\n+\t}\n+\n+\tunicam_dbg(1, dev, \"Running with %u data lanes\\n\",\n+\t\t   dev->active_data_lanes);\n+\n \tret = clk_set_rate(dev->clock, 100 * 1000 * 1000);\n \tif (ret) {\n \t\tunicam_err(dev, \"failed to set up clock\\n\");\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0266-media-bcm2835-unicam-Avoid-gcc-warning-over-0-on-end.patch",
    "content": "From 03a0144820fa1e5b832b8086a82d99b37b7152a1 Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Fri, 26 Jun 2020 15:53:44 +0100\nSubject: [PATCH] media: bcm2835-unicam: Avoid gcc warning over {0} on\n endpoint\n\nOlder gcc versions object to = { 0 } initialisation if the first\nelemtn in the structure is a substructure.\n\nUse = { } to avoid this compiler warning.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n drivers/media/platform/bcm2835/bcm2835-unicam.c | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/drivers/media/platform/bcm2835/bcm2835-unicam.c\n+++ b/drivers/media/platform/bcm2835/bcm2835-unicam.c\n@@ -2586,7 +2586,7 @@ static const struct v4l2_async_notifier_\n static int of_unicam_connect_subdevs(struct unicam_device *dev)\n {\n \tstruct platform_device *pdev = dev->pdev;\n-\tstruct v4l2_fwnode_endpoint ep = { 0 };\n+\tstruct v4l2_fwnode_endpoint ep = { };\n \tstruct device_node *ep_node;\n \tstruct device_node *sensor_node;\n \tunsigned int lane;\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0267-media-i2c-imx290-set-the-format-before-VIDIOC_SUBDEV.patch",
    "content": "From 79d340a54b121610b1d2c5061e8fd1991c6bb1ab Mon Sep 17 00:00:00 2001\nFrom: Andrey Konovalov <andrey.konovalov@linaro.org>\nDate: Fri, 12 Jun 2020 15:53:46 +0200\nSubject: [PATCH] media: i2c: imx290: set the format before\n VIDIOC_SUBDEV_G_FMT is called\n\nCommit d46cfdc86c30d5ec768924f0b1e2683c8d20b671 upstream.\n\nWith the current driver 'media-ctl -p' issued right after the imx290 driver\nis loaded prints:\npad0: Source\n             [fmt:unknown/0x0]\n\nThe format value of zero is due to the current_format field of the imx290\nstruct not being initialized yet.\n\nAs imx290_entity_init_cfg() calls imx290_set_fmt(), the current_mode field\nis also initialized, so the line which set current_mode to a default value\nin driver's probe() function is no longer needed.\n\nSigned-off-by: Andrey Konovalov <andrey.konovalov@linaro.org>\nReviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>\nSigned-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>\nSigned-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>\n---\n drivers/media/i2c/imx290.c | 3 +++\n 1 file changed, 3 insertions(+)\n\n--- a/drivers/media/i2c/imx290.c\n+++ b/drivers/media/i2c/imx290.c\n@@ -1091,6 +1091,9 @@ static int imx290_probe(struct i2c_clien\n \t\tgoto free_ctrl;\n \t}\n \n+\t/* Initialize the frame format (this also sets imx290->current_mode) */\n+\timx290_entity_init_cfg(&imx290->sd, NULL);\n+\n \tret = v4l2_async_register_subdev(&imx290->sd);\n \tif (ret < 0) {\n \t\tdev_err(dev, \"Could not register v4l2 device\\n\");\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0268-media-i2c-imx290-Add-support-for-74.25MHz-clock.patch",
    "content": "From 4af1d6fb5bdf21e25a0e3819eb1184d33c4b192e Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Thu, 25 Jun 2020 08:28:51 +0100\nSubject: [PATCH] media: i2c: imx290: Add support for 74.25MHz clock\n\nThe existing driver only supported a clock of 37.125MHz, but the\nsensor also supports 74.25MHz.\n\nAdd the relevant register modifications to support this alternate\nclock frequency.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n drivers/media/i2c/imx290.c | 119 ++++++++++++++++++++++++++++++-------\n 1 file changed, 97 insertions(+), 22 deletions(-)\n\n--- a/drivers/media/i2c/imx290.c\n+++ b/drivers/media/i2c/imx290.c\n@@ -1,6 +1,10 @@\n // SPDX-License-Identifier: GPL-2.0\n /*\n- * Sony IMX290 CMOS Image Sensor Driver\n+ * Sony IMX290/327 CMOS Image Sensor Driver\n+ *\n+ * The IMX290 and IMX327 are very similar 1920x1080 1/2.8 CMOS image sensors.\n+ * IMX327 can support up to 60fps, whilst IMX290 support up to 120fps (only\n+ * 10bit and when connected over 4 CSI-2 lanes).\n  *\n  * Copyright (C) 2019 FRAMOS GmbH.\n  *\n@@ -22,6 +26,11 @@\n #include <media/v4l2-fwnode.h>\n #include <media/v4l2-subdev.h>\n \n+enum imx290_clk_index {\n+\tCLK_37_125,\n+\tCLK_74_25,\n+};\n+\n #define IMX290_STANDBY 0x3000\n #define IMX290_REGHOLD 0x3001\n #define IMX290_XMSTA 0x3002\n@@ -60,11 +69,16 @@ struct imx290_mode {\n \n \tconst struct imx290_regval *data;\n \tu32 data_size;\n+\n+\t/* Clock setup can vary. Index as enum imx290_clk_index */\n+\tconst struct imx290_regval *clk_data[2];\n+\tu32 clk_size;\n };\n \n struct imx290 {\n \tstruct device *dev;\n \tstruct clk *xclk;\n+\tu32 xclk_freq;\n \tstruct regmap *regmap;\n \tu8 nlanes;\n \tu8 bpp;\n@@ -116,8 +130,6 @@ static const struct imx290_regval imx290\n \t{ 0x3018, 0x65 },\n \t{ 0x3019, 0x04 },\n \t{ 0x301a, 0x00 },\n-\t{ 0x3444, 0x20 },\n-\t{ 0x3445, 0x25 },\n \t{ 0x303a, 0x0c },\n \t{ 0x3040, 0x00 },\n \t{ 0x3041, 0x00 },\n@@ -171,6 +183,30 @@ static const struct imx290_regval imx290\n \t{ 0x33b3, 0x04 },\n };\n \n+static const struct imx290_regval imx290_37_125mhz_clock_1080p[] = {\n+\t{ 0x305c, 0x18 },\n+\t{ 0x305d, 0x03 },\n+\t{ 0x305e, 0x20 },\n+\t{ 0x305f, 0x01 },\n+\t{ 0x315e, 0x1a },\n+\t{ 0x3164, 0x1a },\n+\t{ 0x3444, 0x20 },\n+\t{ 0x3445, 0x25 },\n+\t{ 0x3480, 0x49 },\n+};\n+\n+static const struct imx290_regval imx290_74_250mhz_clock_1080p[] = {\n+\t{ 0x305c, 0x0c },\n+\t{ 0x305d, 0x03 },\n+\t{ 0x305e, 0x10 },\n+\t{ 0x305f, 0x01 },\n+\t{ 0x315e, 0x1b },\n+\t{ 0x3164, 0x1b },\n+\t{ 0x3444, 0x40 },\n+\t{ 0x3445, 0x4a },\n+\t{ 0x3480, 0x92 },\n+};\n+\n static const struct imx290_regval imx290_1080p_settings[] = {\n \t/* mode settings */\n \t{ 0x3007, 0x00 },\n@@ -182,13 +218,6 @@ static const struct imx290_regval imx290\n \t{ 0x3419, 0x04 },\n \t{ 0x3012, 0x64 },\n \t{ 0x3013, 0x00 },\n-\t{ 0x305c, 0x18 },\n-\t{ 0x305d, 0x03 },\n-\t{ 0x305e, 0x20 },\n-\t{ 0x305f, 0x01 },\n-\t{ 0x315e, 0x1a },\n-\t{ 0x3164, 0x1a },\n-\t{ 0x3480, 0x49 },\n \t/* data rate settings */\n \t{ 0x3405, 0x10 },\n \t{ 0x3446, 0x57 },\n@@ -209,6 +238,30 @@ static const struct imx290_regval imx290\n \t{ 0x3455, 0x00 },\n };\n \n+static const struct imx290_regval imx290_37_125mhz_clock_720p[] = {\n+\t{ 0x305c, 0x20 },\n+\t{ 0x305d, 0x00 },\n+\t{ 0x305e, 0x20 },\n+\t{ 0x305f, 0x01 },\n+\t{ 0x315e, 0x1a },\n+\t{ 0x3164, 0x1a },\n+\t{ 0x3444, 0x20 },\n+\t{ 0x3445, 0x25 },\n+\t{ 0x3480, 0x49 },\n+};\n+\n+static const struct imx290_regval imx290_74_250mhz_clock_720p[] = {\n+\t{ 0x305c, 0x10 },\n+\t{ 0x305d, 0x00 },\n+\t{ 0x305e, 0x10 },\n+\t{ 0x305f, 0x01 },\n+\t{ 0x315e, 0x1b },\n+\t{ 0x3164, 0x1b },\n+\t{ 0x3444, 0x40 },\n+\t{ 0x3445, 0x4a },\n+\t{ 0x3480, 0x92 },\n+};\n+\n static const struct imx290_regval imx290_720p_settings[] = {\n \t/* mode settings */\n \t{ 0x3007, 0x10 },\n@@ -220,13 +273,6 @@ static const struct imx290_regval imx290\n \t{ 0x3419, 0x02 },\n \t{ 0x3012, 0x64 },\n \t{ 0x3013, 0x00 },\n-\t{ 0x305c, 0x20 },\n-\t{ 0x305d, 0x00 },\n-\t{ 0x305e, 0x20 },\n-\t{ 0x305f, 0x01 },\n-\t{ 0x315e, 0x1a },\n-\t{ 0x3164, 0x1a },\n-\t{ 0x3480, 0x49 },\n \t/* data rate settings */\n \t{ 0x3405, 0x10 },\n \t{ 0x3446, 0x4f },\n@@ -312,6 +358,11 @@ static const struct imx290_mode imx290_m\n \t\t.link_freq_index = FREQ_INDEX_1080P,\n \t\t.data = imx290_1080p_settings,\n \t\t.data_size = ARRAY_SIZE(imx290_1080p_settings),\n+\t\t.clk_data = {\n+\t\t\t[CLK_37_125] = imx290_37_125mhz_clock_1080p,\n+\t\t\t[CLK_74_25] = imx290_74_250mhz_clock_1080p,\n+\t\t},\n+\t\t.clk_size = ARRAY_SIZE(imx290_37_125mhz_clock_1080p),\n \t},\n \t{\n \t\t.width = 1280,\n@@ -320,6 +371,11 @@ static const struct imx290_mode imx290_m\n \t\t.link_freq_index = FREQ_INDEX_720P,\n \t\t.data = imx290_720p_settings,\n \t\t.data_size = ARRAY_SIZE(imx290_720p_settings),\n+\t\t.clk_data = {\n+\t\t\t[CLK_37_125] = imx290_37_125mhz_clock_1080p,\n+\t\t\t[CLK_74_25] = imx290_74_250mhz_clock_1080p,\n+\t\t},\n+\t\t.clk_size = ARRAY_SIZE(imx290_37_125mhz_clock_1080p),\n \t},\n };\n \n@@ -331,6 +387,11 @@ static const struct imx290_mode imx290_m\n \t\t.link_freq_index = FREQ_INDEX_1080P,\n \t\t.data = imx290_1080p_settings,\n \t\t.data_size = ARRAY_SIZE(imx290_1080p_settings),\n+\t\t.clk_data = {\n+\t\t\t[CLK_37_125] = imx290_37_125mhz_clock_720p,\n+\t\t\t[CLK_74_25] = imx290_74_250mhz_clock_720p,\n+\t\t},\n+\t\t.clk_size = ARRAY_SIZE(imx290_37_125mhz_clock_720p),\n \t},\n \t{\n \t\t.width = 1280,\n@@ -339,6 +400,11 @@ static const struct imx290_mode imx290_m\n \t\t.link_freq_index = FREQ_INDEX_720P,\n \t\t.data = imx290_720p_settings,\n \t\t.data_size = ARRAY_SIZE(imx290_720p_settings),\n+\t\t.clk_data = {\n+\t\t\t[CLK_37_125] = imx290_37_125mhz_clock_720p,\n+\t\t\t[CLK_74_25] = imx290_74_250mhz_clock_720p,\n+\t\t},\n+\t\t.clk_size = ARRAY_SIZE(imx290_37_125mhz_clock_720p),\n \t},\n };\n \n@@ -712,6 +778,8 @@ static int imx290_set_hmax(struct imx290\n /* Start streaming */\n static int imx290_start_streaming(struct imx290 *imx290)\n {\n+\tenum imx290_clk_index clk_idx = imx290->xclk_freq == 37125000 ?\n+\t\t\t\t\tCLK_37_125 : CLK_74_25;\n \tint ret;\n \n \t/* Set init register settings */\n@@ -723,6 +791,14 @@ static int imx290_start_streaming(struct\n \t\treturn ret;\n \t}\n \n+\tret = imx290_set_register_array(imx290,\n+\t\t\t\t\timx290->current_mode->clk_data[clk_idx],\n+\t\t\t\t\timx290->current_mode->clk_size);\n+\tif (ret < 0) {\n+\t\tdev_err(imx290->dev, \"Could not set clock registers\\n\");\n+\t\treturn ret;\n+\t}\n+\n \t/* Apply the register values related to current frame format */\n \tret = imx290_write_current_format(imx290);\n \tif (ret < 0) {\n@@ -939,7 +1015,6 @@ static int imx290_probe(struct i2c_clien\n \t\t.bus_type = V4L2_MBUS_CSI2_DPHY\n \t};\n \tstruct imx290 *imx290;\n-\tu32 xclk_freq;\n \ts64 fq;\n \tint ret;\n \n@@ -1003,21 +1078,21 @@ static int imx290_probe(struct i2c_clien\n \t}\n \n \tret = fwnode_property_read_u32(dev_fwnode(dev), \"clock-frequency\",\n-\t\t\t\t       &xclk_freq);\n+\t\t\t\t       &imx290->xclk_freq);\n \tif (ret) {\n \t\tdev_err(dev, \"Could not get xclk frequency\\n\");\n \t\tgoto free_err;\n \t}\n \n \t/* external clock must be 37.125 MHz */\n-\tif (xclk_freq != 37125000) {\n+\tif (imx290->xclk_freq != 37125000 && imx290->xclk_freq != 74250000) {\n \t\tdev_err(dev, \"External clock frequency %u is not supported\\n\",\n-\t\t\txclk_freq);\n+\t\t\timx290->xclk_freq);\n \t\tret = -EINVAL;\n \t\tgoto free_err;\n \t}\n \n-\tret = clk_set_rate(imx290->xclk, xclk_freq);\n+\tret = clk_set_rate(imx290->xclk, imx290->xclk_freq);\n \tif (ret) {\n \t\tdev_err(dev, \"Could not set xclk frequency\\n\");\n \t\tgoto free_err;\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0269-media-i2c-imx290-Correct-range-for-V4L2_CID_GAIN-to-.patch",
    "content": "From 5b95bb7b2d6b1a866c3ddd752bdbcfa09b0657b0 Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Thu, 11 Jun 2020 13:41:43 +0100\nSubject: [PATCH] media: i2c: imx290: Correct range for V4L2_CID_GAIN\n to 0-238\n\nThe datasheet lists the gain as being 0.0 to 72.0dB in 0.3dB steps, which\nmakes 238 steps total.\nCorrect the 0-72 range defined in the driver.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n drivers/media/i2c/imx290.c | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/drivers/media/i2c/imx290.c\n+++ b/drivers/media/i2c/imx290.c\n@@ -1124,7 +1124,7 @@ static int imx290_probe(struct i2c_clien\n \tv4l2_ctrl_handler_init(&imx290->ctrls, 4);\n \n \tv4l2_ctrl_new_std(&imx290->ctrls, &imx290_ctrl_ops,\n-\t\t\t  V4L2_CID_GAIN, 0, 72, 1, 0);\n+\t\t\t  V4L2_CID_GAIN, 0, 238, 1, 0);\n \n \timx290->link_freq =\n \t\tv4l2_ctrl_new_int_menu(&imx290->ctrls, &imx290_ctrl_ops,\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0270-media-i2c-imx290-Convert-HMAX-setting-into-V4L2_CID_.patch",
    "content": "From a3359aca41e5942a74f803ce8837ef24456db2d5 Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Thu, 11 Jun 2020 14:36:40 +0100\nSubject: [PATCH] media: i2c: imx290: Convert HMAX setting into\n V4L2_CID_HBLANK\n\nUserspace needs to know HBLANK if it is to work out exposure times\nand frame rates, therefore convert it to map onto V4L2_CID_HBLANK\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n drivers/media/i2c/imx290.c | 66 +++++++++++++++++++++++++-------------\n 1 file changed, 44 insertions(+), 22 deletions(-)\n\n--- a/drivers/media/i2c/imx290.c\n+++ b/drivers/media/i2c/imx290.c\n@@ -40,6 +40,9 @@ enum imx290_clk_index {\n #define IMX290_GAIN 0x3014\n #define IMX290_HMAX_LOW 0x301c\n #define IMX290_HMAX_HIGH 0x301d\n+#define IMX290_HMAX_MIN_2LANE 4400 /* Min of 4400 pixels = 30fps */\n+#define IMX290_HMAX_MIN_4LANE 2200 /* Min of 2200 pixels = 60fps */\n+#define IMX290_HMAX_MAX 0xffff\n #define IMX290_PGCTRL 0x308c\n #define IMX290_PHY_LANE_NUM 0x3407\n #define IMX290_CSI_LANE_MODE 0x3443\n@@ -82,6 +85,7 @@ struct imx290 {\n \tstruct regmap *regmap;\n \tu8 nlanes;\n \tu8 bpp;\n+\tu16 hmax_min;\n \n \tstruct v4l2_subdev sd;\n \tstruct media_pad pad;\n@@ -94,6 +98,7 @@ struct imx290 {\n \tstruct v4l2_ctrl_handler ctrls;\n \tstruct v4l2_ctrl *link_freq;\n \tstruct v4l2_ctrl *pixel_rate;\n+\tstruct v4l2_ctrl *hblank;\n \n \tstruct mutex lock;\n };\n@@ -518,6 +523,26 @@ static int imx290_set_gain(struct imx290\n \treturn ret;\n }\n \n+static int imx290_set_hmax(struct imx290 *imx290, u32 val)\n+{\n+\tu32 hmax = val + imx290->current_mode->width;\n+\tint ret;\n+\n+\tret = imx290_write_reg(imx290, IMX290_HMAX_LOW, (hmax & 0xff));\n+\tif (ret) {\n+\t\tdev_err(imx290->dev, \"Error setting HMAX register\\n\");\n+\t\treturn ret;\n+\t}\n+\n+\tret = imx290_write_reg(imx290, IMX290_HMAX_HIGH, ((hmax >> 8) & 0xff));\n+\tif (ret) {\n+\t\tdev_err(imx290->dev, \"Error setting HMAX register\\n\");\n+\t\treturn ret;\n+\t}\n+\n+\treturn 0;\n+}\n+\n /* Stop streaming */\n static int imx290_stop_streaming(struct imx290 *imx290)\n {\n@@ -546,6 +571,9 @@ static int imx290_set_ctrl(struct v4l2_c\n \tcase V4L2_CID_GAIN:\n \t\tret = imx290_set_gain(imx290, ctrl->val);\n \t\tbreak;\n+\tcase V4L2_CID_HBLANK:\n+\t\tret = imx290_set_hmax(imx290, ctrl->val);\n+\t\tbreak;\n \tcase V4L2_CID_TEST_PATTERN:\n \t\tif (ctrl->val) {\n \t\t\timx290_write_reg(imx290, IMX290_BLKLEVEL_LOW, 0x00);\n@@ -702,6 +730,12 @@ static int imx290_set_fmt(struct v4l2_su\n \t\tif (imx290->pixel_rate)\n \t\t\t__v4l2_ctrl_s_ctrl_int64(imx290->pixel_rate,\n \t\t\t\t\t\t imx290_calc_pixel_rate(imx290));\n+\n+\t\tif (imx290->hblank)\n+\t\t\t__v4l2_ctrl_modify_range(imx290->hblank,\n+\t\t\t\t\t\t imx290->hmax_min - mode->width,\n+\t\t\t\t\t\t IMX290_HMAX_MAX - mode->width,\n+\t\t\t\t\t\t 1, mode->hmax - mode->width);\n \t}\n \n \t*format = fmt->format;\n@@ -756,25 +790,6 @@ static int imx290_write_current_format(s\n \treturn 0;\n }\n \n-static int imx290_set_hmax(struct imx290 *imx290, u32 val)\n-{\n-\tint ret;\n-\n-\tret = imx290_write_reg(imx290, IMX290_HMAX_LOW, (val & 0xff));\n-\tif (ret) {\n-\t\tdev_err(imx290->dev, \"Error setting HMAX register\\n\");\n-\t\treturn ret;\n-\t}\n-\n-\tret = imx290_write_reg(imx290, IMX290_HMAX_HIGH, ((val >> 8) & 0xff));\n-\tif (ret) {\n-\t\tdev_err(imx290->dev, \"Error setting HMAX register\\n\");\n-\t\treturn ret;\n-\t}\n-\n-\treturn 0;\n-}\n-\n /* Start streaming */\n static int imx290_start_streaming(struct imx290 *imx290)\n {\n@@ -813,9 +828,6 @@ static int imx290_start_streaming(struct\n \t\tdev_err(imx290->dev, \"Could not set current mode\\n\");\n \t\treturn ret;\n \t}\n-\tret = imx290_set_hmax(imx290, imx290->current_mode->hmax);\n-\tif (ret < 0)\n-\t\treturn ret;\n \n \t/* Apply customized values from user */\n \tret = v4l2_ctrl_handler_setup(imx290->sd.ctrl_handler);\n@@ -1014,6 +1026,7 @@ static int imx290_probe(struct i2c_clien\n \tstruct v4l2_fwnode_endpoint ep = {\n \t\t.bus_type = V4L2_MBUS_CSI2_DPHY\n \t};\n+\tconst struct imx290_mode *mode;\n \tstruct imx290 *imx290;\n \ts64 fq;\n \tint ret;\n@@ -1052,6 +1065,8 @@ static int imx290_probe(struct i2c_clien\n \t\tret = -EINVAL;\n \t\tgoto free_err;\n \t}\n+\timx290->hmax_min = (imx290->nlanes == 2) ? IMX290_HMAX_MIN_2LANE :\n+\t\t\t\t\t\t IMX290_HMAX_MIN_4LANE;\n \n \tdev_dbg(dev, \"Using %u data lanes\\n\", imx290->nlanes);\n \n@@ -1126,6 +1141,13 @@ static int imx290_probe(struct i2c_clien\n \tv4l2_ctrl_new_std(&imx290->ctrls, &imx290_ctrl_ops,\n \t\t\t  V4L2_CID_GAIN, 0, 238, 1, 0);\n \n+\tmode = imx290->current_mode;\n+\timx290->hblank = v4l2_ctrl_new_std(&imx290->ctrls, &imx290_ctrl_ops,\n+\t\t\t\t\t   V4L2_CID_HBLANK,\n+\t\t\t\t\t   imx290->hmax_min - mode->width,\n+\t\t\t\t\t   IMX290_HMAX_MAX - mode->width, 1,\n+\t\t\t\t\t   mode->hmax - mode->width);\n+\n \timx290->link_freq =\n \t\tv4l2_ctrl_new_int_menu(&imx290->ctrls, &imx290_ctrl_ops,\n \t\t\t\t       V4L2_CID_LINK_FREQ,\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0271-media-i2c-imx290-Add-support-for-V4L2_CID_VBLANK.patch",
    "content": "From e8ad74c090f54cf8ce845b627e4312b6166059fd Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Thu, 11 Jun 2020 18:09:12 +0100\nSubject: [PATCH] media: i2c: imx290: Add support for V4L2_CID_VBLANK\n\nIn order to calculate framerate and durations userspace needs\nthe vertical blanking information. This can be configurable,\nand indeed the datasheet lists different values for VBLANK for\nthe 1080p and 720p modes.\n\nAdd the new control, and adopt the datasheet values for each mode.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n drivers/media/i2c/imx290.c | 38 ++++++++++++++++++++++++++++++++++++--\n 1 file changed, 36 insertions(+), 2 deletions(-)\n\n--- a/drivers/media/i2c/imx290.c\n+++ b/drivers/media/i2c/imx290.c\n@@ -38,6 +38,8 @@ enum imx290_clk_index {\n #define IMX290_BLKLEVEL_LOW 0x300a\n #define IMX290_BLKLEVEL_HIGH 0x300b\n #define IMX290_GAIN 0x3014\n+#define IMX290_VMAX_LOW 0x3018\n+#define IMX290_VMAX_MAX 0x3fff\n #define IMX290_HMAX_LOW 0x301c\n #define IMX290_HMAX_HIGH 0x301d\n #define IMX290_HMAX_MIN_2LANE 4400 /* Min of 4400 pixels = 30fps */\n@@ -68,6 +70,7 @@ struct imx290_mode {\n \tu32 width;\n \tu32 height;\n \tu32 hmax;\n+\tu32 vmax;\n \tu8 link_freq_index;\n \n \tconst struct imx290_regval *data;\n@@ -99,6 +102,7 @@ struct imx290 {\n \tstruct v4l2_ctrl *link_freq;\n \tstruct v4l2_ctrl *pixel_rate;\n \tstruct v4l2_ctrl *hblank;\n+\tstruct v4l2_ctrl *vblank;\n \n \tstruct mutex lock;\n };\n@@ -132,8 +136,6 @@ static const char * const imx290_test_pa\n \n static const struct imx290_regval imx290_global_init_settings[] = {\n \t{ 0x3007, 0x00 },\n-\t{ 0x3018, 0x65 },\n-\t{ 0x3019, 0x04 },\n \t{ 0x301a, 0x00 },\n \t{ 0x303a, 0x0c },\n \t{ 0x3040, 0x00 },\n@@ -360,6 +362,7 @@ static const struct imx290_mode imx290_m\n \t\t.width = 1920,\n \t\t.height = 1080,\n \t\t.hmax = 0x1130,\n+\t\t.vmax = 0x0465,\n \t\t.link_freq_index = FREQ_INDEX_1080P,\n \t\t.data = imx290_1080p_settings,\n \t\t.data_size = ARRAY_SIZE(imx290_1080p_settings),\n@@ -373,6 +376,7 @@ static const struct imx290_mode imx290_m\n \t\t.width = 1280,\n \t\t.height = 720,\n \t\t.hmax = 0x19c8,\n+\t\t.vmax = 0x02ee,\n \t\t.link_freq_index = FREQ_INDEX_720P,\n \t\t.data = imx290_720p_settings,\n \t\t.data_size = ARRAY_SIZE(imx290_720p_settings),\n@@ -389,6 +393,7 @@ static const struct imx290_mode imx290_m\n \t\t.width = 1920,\n \t\t.height = 1080,\n \t\t.hmax = 0x0898,\n+\t\t.vmax = 0x0465,\n \t\t.link_freq_index = FREQ_INDEX_1080P,\n \t\t.data = imx290_1080p_settings,\n \t\t.data_size = ARRAY_SIZE(imx290_1080p_settings),\n@@ -402,6 +407,7 @@ static const struct imx290_mode imx290_m\n \t\t.width = 1280,\n \t\t.height = 720,\n \t\t.hmax = 0x0ce4,\n+\t\t.vmax = 0x02ee,\n \t\t.link_freq_index = FREQ_INDEX_720P,\n \t\t.data = imx290_720p_settings,\n \t\t.data_size = ARRAY_SIZE(imx290_720p_settings),\n@@ -543,6 +549,19 @@ static int imx290_set_hmax(struct imx290\n \treturn 0;\n }\n \n+static int imx290_set_vmax(struct imx290 *imx290, u32 val)\n+{\n+\tu32 vmax = val + imx290->current_mode->height;\n+\tint ret;\n+\n+\tret = imx290_write_buffered_reg(imx290, IMX290_VMAX_LOW, 3,\n+\t\t\t\t\tvmax);\n+\tif (ret)\n+\t\tdev_err(imx290->dev, \"Unable to write vmax\\n\");\n+\n+\treturn ret;\n+}\n+\n /* Stop streaming */\n static int imx290_stop_streaming(struct imx290 *imx290)\n {\n@@ -574,6 +593,9 @@ static int imx290_set_ctrl(struct v4l2_c\n \tcase V4L2_CID_HBLANK:\n \t\tret = imx290_set_hmax(imx290, ctrl->val);\n \t\tbreak;\n+\tcase V4L2_CID_VBLANK:\n+\t\tret = imx290_set_vmax(imx290, ctrl->val);\n+\t\tbreak;\n \tcase V4L2_CID_TEST_PATTERN:\n \t\tif (ctrl->val) {\n \t\t\timx290_write_reg(imx290, IMX290_BLKLEVEL_LOW, 0x00);\n@@ -736,6 +758,12 @@ static int imx290_set_fmt(struct v4l2_su\n \t\t\t\t\t\t imx290->hmax_min - mode->width,\n \t\t\t\t\t\t IMX290_HMAX_MAX - mode->width,\n \t\t\t\t\t\t 1, mode->hmax - mode->width);\n+\t\tif (imx290->vblank)\n+\t\t\t__v4l2_ctrl_modify_range(imx290->vblank,\n+\t\t\t\t\t\t mode->vmax - mode->height,\n+\t\t\t\t\t\t IMX290_VMAX_MAX - mode->height,\n+\t\t\t\t\t\t 1,\n+\t\t\t\t\t\t mode->vmax - mode->height);\n \t}\n \n \t*format = fmt->format;\n@@ -1148,6 +1176,12 @@ static int imx290_probe(struct i2c_clien\n \t\t\t\t\t   IMX290_HMAX_MAX - mode->width, 1,\n \t\t\t\t\t   mode->hmax - mode->width);\n \n+\timx290->vblank = v4l2_ctrl_new_std(&imx290->ctrls, &imx290_ctrl_ops,\n+\t\t\t\t\t   V4L2_CID_VBLANK,\n+\t\t\t\t\t   mode->vmax - mode->height,\n+\t\t\t\t\t   IMX290_VMAX_MAX - mode->height, 1,\n+\t\t\t\t\t   mode->vmax - mode->height);\n+\n \timx290->link_freq =\n \t\tv4l2_ctrl_new_int_menu(&imx290->ctrls, &imx290_ctrl_ops,\n \t\t\t\t       V4L2_CID_LINK_FREQ,\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0272-media-i2c-imx290-Add-exposure-control-to-the-driver.patch",
    "content": "From 3802436037a2df9a85eee1e2917521c02e2263b7 Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Thu, 11 Jun 2020 18:19:13 +0100\nSubject: [PATCH] media: i2c: imx290: Add exposure control to the\n driver.\n\nAdds support for V4L2_CID_EXPOSURE so that userspace can control\nthe sensor exposure time.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n drivers/media/i2c/imx290.c | 35 +++++++++++++++++++++++++++++++++++\n 1 file changed, 35 insertions(+)\n\n--- a/drivers/media/i2c/imx290.c\n+++ b/drivers/media/i2c/imx290.c\n@@ -45,6 +45,10 @@ enum imx290_clk_index {\n #define IMX290_HMAX_MIN_2LANE 4400 /* Min of 4400 pixels = 30fps */\n #define IMX290_HMAX_MIN_4LANE 2200 /* Min of 2200 pixels = 60fps */\n #define IMX290_HMAX_MAX 0xffff\n+\n+#define IMX290_EXPOSURE_MIN 2\n+#define IMX290_EXPOSURE_STEP 1\n+#define IMX290_EXPOSURE_LOW 0x3020\n #define IMX290_PGCTRL 0x308c\n #define IMX290_PHY_LANE_NUM 0x3407\n #define IMX290_CSI_LANE_MODE 0x3443\n@@ -103,6 +107,7 @@ struct imx290 {\n \tstruct v4l2_ctrl *pixel_rate;\n \tstruct v4l2_ctrl *hblank;\n \tstruct v4l2_ctrl *vblank;\n+\tstruct v4l2_ctrl *exposure;\n \n \tstruct mutex lock;\n };\n@@ -529,6 +534,20 @@ static int imx290_set_gain(struct imx290\n \treturn ret;\n }\n \n+static int imx290_set_exposure(struct imx290 *imx290, u32 value)\n+{\n+\tu32 exposure = (imx290->current_mode->height + imx290->vblank->val) -\n+\t\t\t\t\t\tvalue;\n+\tint ret;\n+\n+\tret = imx290_write_buffered_reg(imx290, IMX290_EXPOSURE_LOW, 3,\n+\t\t\t\t\texposure);\n+\tif (ret)\n+\t\tdev_err(imx290->dev, \"Unable to write exposure\\n\");\n+\n+\treturn ret;\n+}\n+\n static int imx290_set_hmax(struct imx290 *imx290, u32 val)\n {\n \tu32 hmax = val + imx290->current_mode->width;\n@@ -590,6 +609,9 @@ static int imx290_set_ctrl(struct v4l2_c\n \tcase V4L2_CID_GAIN:\n \t\tret = imx290_set_gain(imx290, ctrl->val);\n \t\tbreak;\n+\tcase V4L2_CID_EXPOSURE:\n+\t\tret = imx290_set_exposure(imx290, ctrl->val);\n+\t\tbreak;\n \tcase V4L2_CID_HBLANK:\n \t\tret = imx290_set_hmax(imx290, ctrl->val);\n \t\tbreak;\n@@ -764,6 +786,12 @@ static int imx290_set_fmt(struct v4l2_su\n \t\t\t\t\t\t IMX290_VMAX_MAX - mode->height,\n \t\t\t\t\t\t 1,\n \t\t\t\t\t\t mode->vmax - mode->height);\n+\t\tif (imx290->exposure)\n+\t\t\t__v4l2_ctrl_modify_range(imx290->exposure,\n+\t\t\t\t\t\t mode->vmax - mode->height,\n+\t\t\t\t\t\t mode->vmax - 4,\n+\t\t\t\t\t\t IMX290_EXPOSURE_STEP,\n+\t\t\t\t\t\t mode->vmax - 4);\n \t}\n \n \t*format = fmt->format;\n@@ -1182,6 +1210,13 @@ static int imx290_probe(struct i2c_clien\n \t\t\t\t\t   IMX290_VMAX_MAX - mode->height, 1,\n \t\t\t\t\t   mode->vmax - mode->height);\n \n+\timx290->exposure = v4l2_ctrl_new_std(&imx290->ctrls, &imx290_ctrl_ops,\n+\t\t\t\t\t     V4L2_CID_EXPOSURE,\n+\t\t\t\t\t     IMX290_EXPOSURE_MIN,\n+\t\t\t\t\t     mode->vmax - 4,\n+\t\t\t\t\t     IMX290_EXPOSURE_STEP,\n+\t\t\t\t\t     mode->vmax - 4);\n+\n \timx290->link_freq =\n \t\tv4l2_ctrl_new_int_menu(&imx290->ctrls, &imx290_ctrl_ops,\n \t\t\t\t       V4L2_CID_LINK_FREQ,\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0273-media-i2c-imx290-Add-H-and-V-flip-controls.patch",
    "content": "From ab78051da1ad984c5b424c1e75f487d2a2f2c026 Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Thu, 11 Jun 2020 18:34:16 +0100\nSubject: [PATCH] media: i2c: imx290: Add H and V flip controls\n\nThe sensor supports horizontal and vertical flips, so support them\nthrough V4L2_CID_HFLIP and V4L2_CID_VFLIP.\n\nThis sensor does NOT change the Bayer order when changing the\ndirection of readout, therefore no special handling is required for\nthat.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n drivers/media/i2c/imx290.c | 22 ++++++++++++++++++++++\n 1 file changed, 22 insertions(+)\n\n--- a/drivers/media/i2c/imx290.c\n+++ b/drivers/media/i2c/imx290.c\n@@ -34,6 +34,7 @@ enum imx290_clk_index {\n #define IMX290_STANDBY 0x3000\n #define IMX290_REGHOLD 0x3001\n #define IMX290_XMSTA 0x3002\n+#define IMX290_FLIP_WINMODE 0x3007\n #define IMX290_FR_FDG_SEL 0x3009\n #define IMX290_BLKLEVEL_LOW 0x300a\n #define IMX290_BLKLEVEL_HIGH 0x300b\n@@ -107,6 +108,8 @@ struct imx290 {\n \tstruct v4l2_ctrl *pixel_rate;\n \tstruct v4l2_ctrl *hblank;\n \tstruct v4l2_ctrl *vblank;\n+\tstruct v4l2_ctrl *hflip;\n+\tstruct v4l2_ctrl *vflip;\n \tstruct v4l2_ctrl *exposure;\n \n \tstruct mutex lock;\n@@ -600,6 +603,7 @@ static int imx290_set_ctrl(struct v4l2_c\n \tstruct imx290 *imx290 = container_of(ctrl->handler,\n \t\t\t\t\t     struct imx290, ctrls);\n \tint ret = 0;\n+\tu8 val;\n \n \t/* V4L2 controls values will be applied only when power is already up */\n \tif (!pm_runtime_get_if_in_use(imx290->dev))\n@@ -618,6 +622,16 @@ static int imx290_set_ctrl(struct v4l2_c\n \tcase V4L2_CID_VBLANK:\n \t\tret = imx290_set_vmax(imx290, ctrl->val);\n \t\tbreak;\n+\tcase V4L2_CID_HFLIP:\n+\tcase V4L2_CID_VFLIP:\n+\t\t/* WINMODE is in bits [6:4], so need to read-modify-write */\n+\t\tret = imx290_read_reg(imx290, IMX290_FLIP_WINMODE, &val);\n+\t\tif (ret)\n+\t\t\tbreak;\n+\t\tval &= ~0x03;\n+\t\tval |= imx290->vflip->val | (imx290->hflip->val << 1);\n+\t\tret = imx290_write_reg(imx290, IMX290_FLIP_WINMODE, val);\n+\t\tbreak;\n \tcase V4L2_CID_TEST_PATTERN:\n \t\tif (ctrl->val) {\n \t\t\timx290_write_reg(imx290, IMX290_BLKLEVEL_LOW, 0x00);\n@@ -924,6 +938,9 @@ static int imx290_set_stream(struct v4l2\n \t\timx290_stop_streaming(imx290);\n \t\tpm_runtime_put(imx290->dev);\n \t}\n+\t/* vflip and hflip cannot change during streaming */\n+\t__v4l2_ctrl_grab(imx290->vflip, enable);\n+\t__v4l2_ctrl_grab(imx290->hflip, enable);\n \n unlock_and_return:\n \n@@ -1217,6 +1234,11 @@ static int imx290_probe(struct i2c_clien\n \t\t\t\t\t     IMX290_EXPOSURE_STEP,\n \t\t\t\t\t     mode->vmax - 4);\n \n+\timx290->hflip = v4l2_ctrl_new_std(&imx290->ctrls, &imx290_ctrl_ops,\n+\t\t\t\t\t  V4L2_CID_HFLIP, 0, 1, 1, 0);\n+\timx290->vflip = v4l2_ctrl_new_std(&imx290->ctrls, &imx290_ctrl_ops,\n+\t\t\t\t\t  V4L2_CID_VFLIP, 0, 1, 1, 0);\n+\n \timx290->link_freq =\n \t\tv4l2_ctrl_new_int_menu(&imx290->ctrls, &imx290_ctrl_ops,\n \t\t\t\t       V4L2_CID_LINK_FREQ,\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0274-media-dt-bindings-media-i2c-Add-mono-version-to-IMX2.patch",
    "content": "From 5e67752c725fa06d0e2455dac19fbef93e313eb7 Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Thu, 25 Jun 2020 16:52:14 +0100\nSubject: [PATCH] media: dt-bindings: media: i2c: Add mono version to\n IMX290 bindings\n\nThe IMX290 module is available as either monochrome or colour and\nthe variant is not detectable at runtime.\n\nAdd a new compatible string for the monochrome version.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n Documentation/devicetree/bindings/media/i2c/imx290.txt | 7 ++++---\n 1 file changed, 4 insertions(+), 3 deletions(-)\n\n--- a/Documentation/devicetree/bindings/media/i2c/imx290.txt\n+++ b/Documentation/devicetree/bindings/media/i2c/imx290.txt\n@@ -1,13 +1,14 @@\n * Sony IMX290 1/2.8-Inch CMOS Image Sensor\n \n The Sony IMX290 is a 1/2.8-Inch CMOS Solid-state image sensor with\n-Square Pixel for Color Cameras. It is programmable through I2C and 4-wire\n-interfaces. The sensor output is available via CMOS logic parallel SDR output,\n+Square Pixel for Color or Monochrome Cameras. It is programmable through I2C\n+and 4-wire interfaces.\n+The sensor output is available via CMOS logic parallel SDR output,\n Low voltage LVDS DDR output and CSI-2 serial data output. The CSI-2 bus is the\n default. No bindings have been defined for the other busses.\n \n Required Properties:\n-- compatible: Should be \"sony,imx290\"\n+- compatible: Should be \"sony,imx290\", or \"sony,imx290-mono\"\n - reg: I2C bus address of the device\n - clocks: Reference to the xclk clock.\n - clock-names: Should be \"xclk\".\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0275-media-i2c-imx290-Add-support-for-the-mono-sensor-var.patch",
    "content": "From 550fc1298f6a4726e3944944561a047b3e04b134 Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Thu, 25 Jun 2020 17:03:11 +0100\nSubject: [PATCH] media : i2c: imx290: Add support for the mono sensor\n variant.\n\nThe IMX290 module is available as either mono or colour (Bayer).\n\nUpdate the driver so that it can advertise the correct mono\nformats instead of the colour ones.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n drivers/media/i2c/imx290.c | 58 +++++++++++++++++++++++++++-----------\n 1 file changed, 41 insertions(+), 17 deletions(-)\n\n--- a/drivers/media/i2c/imx290.c\n+++ b/drivers/media/i2c/imx290.c\n@@ -1,10 +1,12 @@\n // SPDX-License-Identifier: GPL-2.0\n /*\n- * Sony IMX290/327 CMOS Image Sensor Driver\n+ * Sony IMX290 & IMX327 CMOS Image Sensor Driver\n  *\n  * The IMX290 and IMX327 are very similar 1920x1080 1/2.8 CMOS image sensors.\n- * IMX327 can support up to 60fps, whilst IMX290 support up to 120fps (only\n- * 10bit and when connected over 4 CSI-2 lanes).\n+ * IMX327 can support up to 60fps, whilst IMX290 can support up to 120fps, but\n+ * only 10bit and when connected over 4 CSI-2 lanes.\n+ * The modules don't appear to have a mechanism to identify whether the mono or\n+ * colour variant is connected, therefore it is done via compatible string.\n  *\n  * Copyright (C) 2019 FRAMOS GmbH.\n  *\n@@ -17,6 +19,7 @@\n #include <linux/gpio/consumer.h>\n #include <linux/i2c.h>\n #include <linux/module.h>\n+#include <linux/of_device.h>\n #include <linux/pm_runtime.h>\n #include <linux/regmap.h>\n #include <linux/regulator/consumer.h>\n@@ -95,6 +98,8 @@ struct imx290 {\n \tu8 bpp;\n \tu16 hmax_min;\n \n+\tconst struct imx290_pixfmt *formats;\n+\n \tstruct v4l2_subdev sd;\n \tstruct media_pad pad;\n \tstruct v4l2_mbus_framefmt current_format;\n@@ -120,11 +125,18 @@ struct imx290_pixfmt {\n \tu8 bpp;\n };\n \n-static const struct imx290_pixfmt imx290_formats[] = {\n+#define IMX290_NUM_FORMATS 2\n+\n+static const struct imx290_pixfmt imx290_colour_formats[IMX290_NUM_FORMATS] = {\n \t{ MEDIA_BUS_FMT_SRGGB10_1X10, 10 },\n \t{ MEDIA_BUS_FMT_SRGGB12_1X12, 12 },\n };\n \n+static const struct imx290_pixfmt imx290_mono_formats[IMX290_NUM_FORMATS] = {\n+\t{ MEDIA_BUS_FMT_Y10_1X10, 10 },\n+\t{ MEDIA_BUS_FMT_Y12_1X12, 12 },\n+};\n+\n static const struct regmap_config imx290_regmap_config = {\n \t.reg_bits = 16,\n \t.val_bits = 8,\n@@ -671,10 +683,12 @@ static int imx290_enum_mbus_code(struct\n \t\t\t\t struct v4l2_subdev_pad_config *cfg,\n \t\t\t\t struct v4l2_subdev_mbus_code_enum *code)\n {\n-\tif (code->index >= ARRAY_SIZE(imx290_formats))\n+\tconst struct imx290 *imx290 = to_imx290(sd);\n+\n+\tif (code->index >= IMX290_NUM_FORMATS)\n \t\treturn -EINVAL;\n \n-\tcode->code = imx290_formats[code->index].code;\n+\tcode->code = imx290->formats[code->index].code;\n \n \treturn 0;\n }\n@@ -686,8 +700,8 @@ static int imx290_enum_frame_size(struct\n \tconst struct imx290 *imx290 = to_imx290(sd);\n \tconst struct imx290_mode *imx290_modes = imx290_modes_ptr(imx290);\n \n-\tif ((fse->code != imx290_formats[0].code) &&\n-\t    (fse->code != imx290_formats[1].code))\n+\tif (fse->code != imx290->formats[0].code &&\n+\t    fse->code != imx290->formats[1].code)\n \t\treturn -EINVAL;\n \n \tif (fse->index >= imx290_modes_num(imx290))\n@@ -765,14 +779,14 @@ static int imx290_set_fmt(struct v4l2_su\n \tfmt->format.width = mode->width;\n \tfmt->format.height = mode->height;\n \n-\tfor (i = 0; i < ARRAY_SIZE(imx290_formats); i++)\n-\t\tif (imx290_formats[i].code == fmt->format.code)\n+\tfor (i = 0; i < IMX290_NUM_FORMATS; i++)\n+\t\tif (imx290->formats[i].code == fmt->format.code)\n \t\t\tbreak;\n \n-\tif (i >= ARRAY_SIZE(imx290_formats))\n+\tif (i >= IMX290_NUM_FORMATS)\n \t\ti = 0;\n \n-\tfmt->format.code = imx290_formats[i].code;\n+\tfmt->format.code = imx290->formats[i].code;\n \tfmt->format.field = V4L2_FIELD_NONE;\n \n \tif (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {\n@@ -780,7 +794,7 @@ static int imx290_set_fmt(struct v4l2_su\n \t} else {\n \t\tformat = &imx290->current_format;\n \t\timx290->current_mode = mode;\n-\t\timx290->bpp = imx290_formats[i].bpp;\n+\t\timx290->bpp = imx290->formats[i].bpp;\n \n \t\tif (imx290->link_freq)\n \t\t\t__v4l2_ctrl_s_ctrl(imx290->link_freq,\n@@ -835,6 +849,7 @@ static int imx290_write_current_format(s\n \n \tswitch (imx290->current_format.code) {\n \tcase MEDIA_BUS_FMT_SRGGB10_1X10:\n+\tcase MEDIA_BUS_FMT_Y10_1X10:\n \t\tret = imx290_set_register_array(imx290, imx290_10bit_settings,\n \t\t\t\t\t\tARRAY_SIZE(\n \t\t\t\t\t\t\timx290_10bit_settings));\n@@ -844,6 +859,7 @@ static int imx290_write_current_format(s\n \t\t}\n \t\tbreak;\n \tcase MEDIA_BUS_FMT_SRGGB12_1X12:\n+\tcase MEDIA_BUS_FMT_Y12_1X12:\n \t\tret = imx290_set_register_array(imx290, imx290_12bit_settings,\n \t\t\t\t\t\tARRAY_SIZE(\n \t\t\t\t\t\t\timx290_12bit_settings));\n@@ -1091,6 +1107,12 @@ static s64 imx290_check_link_freqs(const\n \treturn 0;\n }\n \n+static const struct of_device_id imx290_of_match[] = {\n+\t{ .compatible = \"sony,imx290\", .data = imx290_colour_formats },\n+\t{ .compatible = \"sony,imx290-mono\", .data = imx290_mono_formats },\n+\t{ /* sentinel */ }\n+};\n+\n static int imx290_probe(struct i2c_client *client)\n {\n \tstruct device *dev = &client->dev;\n@@ -1099,6 +1121,7 @@ static int imx290_probe(struct i2c_clien\n \tstruct v4l2_fwnode_endpoint ep = {\n \t\t.bus_type = V4L2_MBUS_CSI2_DPHY\n \t};\n+\tconst struct of_device_id *match;\n \tconst struct imx290_mode *mode;\n \tstruct imx290 *imx290;\n \ts64 fq;\n@@ -1115,6 +1138,11 @@ static int imx290_probe(struct i2c_clien\n \t\treturn -ENODEV;\n \t}\n \n+\tmatch = of_match_device(imx290_of_match, dev);\n+\tif (!match)\n+\t\treturn -ENODEV;\n+\timx290->formats = (const struct imx290_pixfmt *)match->data;\n+\n \tendpoint = fwnode_graph_get_next_endpoint(dev_fwnode(dev), NULL);\n \tif (!endpoint) {\n \t\tdev_err(dev, \"Endpoint node not found\\n\");\n@@ -1333,10 +1361,6 @@ static int imx290_remove(struct i2c_clie\n \treturn 0;\n }\n \n-static const struct of_device_id imx290_of_match[] = {\n-\t{ .compatible = \"sony,imx290\" },\n-\t{ /* sentinel */ }\n-};\n MODULE_DEVICE_TABLE(of, imx290_of_match);\n \n static struct i2c_driver imx290_i2c_driver = {\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0276-media-i2c-imx290-Switch-set_hmax-to-use-imx290_write.patch",
    "content": "From 4e0e8f87b81ed1dfa9876e0ce4492cc8f64c935a Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Fri, 26 Jun 2020 18:11:49 +0100\nSubject: [PATCH] media: i2c: imx290: Switch set_hmax to use\n imx290_write_buffered_reg\n\nimx290_set_hmax was using two independent writes to set up hmax,\nwhen all other multi-register writes were using imx290_write_buffered_reg\nwhich claims the group hold first.\n\nSwitch imx290_set_hmax to using imx290_write_buffered_reg too.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n drivers/media/i2c/imx290.c | 15 ++++-----------\n 1 file changed, 4 insertions(+), 11 deletions(-)\n\n--- a/drivers/media/i2c/imx290.c\n+++ b/drivers/media/i2c/imx290.c\n@@ -568,19 +568,12 @@ static int imx290_set_hmax(struct imx290\n \tu32 hmax = val + imx290->current_mode->width;\n \tint ret;\n \n-\tret = imx290_write_reg(imx290, IMX290_HMAX_LOW, (hmax & 0xff));\n-\tif (ret) {\n+\tret = imx290_write_buffered_reg(imx290, IMX290_HMAX_LOW, 2,\n+\t\t\t\t\thmax);\n+\tif (ret)\n \t\tdev_err(imx290->dev, \"Error setting HMAX register\\n\");\n-\t\treturn ret;\n-\t}\n \n-\tret = imx290_write_reg(imx290, IMX290_HMAX_HIGH, ((hmax >> 8) & 0xff));\n-\tif (ret) {\n-\t\tdev_err(imx290->dev, \"Error setting HMAX register\\n\");\n-\t\treturn ret;\n-\t}\n-\n-\treturn 0;\n+\treturn ret;\n }\n \n static int imx290_set_vmax(struct imx290 *imx290, u32 val)\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0277-serial-8250-bcm2835aux-defer-if-clock-is-zero.patch",
    "content": "From e3af8dd4ba4fc1ae6260823dfb3a82236471c353 Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.com>\nDate: Thu, 2 Jul 2020 13:53:20 +0100\nSubject: [PATCH] serial: 8250: bcm2835aux - defer if clock is zero\n\nSee: https://github.com/raspberrypi/linux/issues/3700\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.com>\n---\n drivers/tty/serial/8250/8250_bcm2835aux.c | 7 +++++++\n 1 file changed, 7 insertions(+)\n\n--- a/drivers/tty/serial/8250/8250_bcm2835aux.c\n+++ b/drivers/tty/serial/8250/8250_bcm2835aux.c\n@@ -148,6 +148,13 @@ static int bcm2835aux_serial_probe(struc\n \t */\n \tup.port.uartclk = clk_get_rate(data->clk) * 2;\n \n+\t/* The clock is only queried at probe time, which means we get one shot\n+\t * at this. A zero clock is never going to work and is almost certainly\n+\t * due to a parent not being ready, so prefer to defer.\n+\t */\n+\tif (!up.port.uartclk)\n+\t    return -EPROBE_DEFER;\n+\n \t/* register the port */\n \tret = serial8250_register_8250_port(&up);\n \tif (ret < 0) {\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0278-media-Add-a-pixel-format-for-MIPI-packed-12bit-luma-.patch",
    "content": "From 85e4a24a7f8fd96cc765c038bbae601ca69daa39 Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Thu, 7 May 2020 16:59:03 +0100\nSubject: [PATCH] media: Add a pixel format for MIPI packed 12bit luma\n only.\n\nThis is the format used by monochrome 12bit image sensors.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n .../userspace-api/media/v4l/pixfmt-y12p.rst   | 45 +++++++++++++++++++\n .../userspace-api/media/v4l/yuv-formats.rst   |  1 +\n drivers/media/v4l2-core/v4l2-ioctl.c          |  1 +\n include/uapi/linux/videodev2.h                |  1 +\n 4 files changed, 48 insertions(+)\n create mode 100644 Documentation/userspace-api/media/v4l/pixfmt-y12p.rst\n\n--- /dev/null\n+++ b/Documentation/userspace-api/media/v4l/pixfmt-y12p.rst\n@@ -0,0 +1,45 @@\n+.. Permission is granted to copy, distribute and/or modify this\n+.. document under the terms of the GNU Free Documentation License,\n+.. Version 1.1 or any later version published by the Free Software\n+.. Foundation, with no Invariant Sections, no Front-Cover Texts\n+.. and no Back-Cover Texts. A copy of the license is included at\n+.. Documentation/media/uapi/fdl-appendix.rst.\n+..\n+.. TODO: replace it to GFDL-1.1-or-later WITH no-invariant-sections\n+\n+.. _V4L2-PIX-FMT-Y12P:\n+\n+******************************\n+V4L2_PIX_FMT_Y12P ('Y12P')\n+******************************\n+\n+Grey-scale image as a MIPI RAW12 packed array\n+\n+\n+Description\n+===========\n+\n+This is a packed grey-scale image format with a depth of 12 bits per\n+pixel. Two consecutive pixels are packed into 3 bytes. The first 2 bytes\n+contain the 8 high order bits of the pixels, and the 3rd byte contains the 4\n+least significants bits of each pixel, in the same order.\n+\n+**Byte Order.**\n+Each cell is one byte.\n+\n+.. tabularcolumns:: |p{2.2cm}|p{1.2cm}|p{1.2cm}|p{3.1cm}|\n+\n+\n+.. flat-table::\n+    :header-rows:  0\n+    :stub-columns: 0\n+    :widths:       2 1 1 1\n+\n+\n+    -  -  start + 0:\n+       -  Y'\\ :sub:`00high`\n+       -  Y'\\ :sub:`01high`\n+       -  Y'\\ :sub:`01low`\\ (bits 7--4)\n+\n+          Y'\\ :sub:`00low`\\ (bits 3--0)\n+\n--- a/Documentation/userspace-api/media/v4l/yuv-formats.rst\n+++ b/Documentation/userspace-api/media/v4l/yuv-formats.rst\n@@ -28,6 +28,7 @@ to brightness information.\n     pixfmt-grey\n     pixfmt-y10\n     pixfmt-y12\n+    pixfmt-y12p\n     pixfmt-y14\n     pixfmt-y10b\n     pixfmt-y10p\n--- a/drivers/media/v4l2-core/v4l2-ioctl.c\n+++ b/drivers/media/v4l2-core/v4l2-ioctl.c\n@@ -1301,6 +1301,7 @@ static void v4l_fill_fmtdesc(struct v4l2\n \tcase V4L2_PIX_FMT_Y16_BE:\tdescr = \"16-bit Greyscale BE\"; break;\n \tcase V4L2_PIX_FMT_Y10BPACK:\tdescr = \"10-bit Greyscale (Packed)\"; break;\n \tcase V4L2_PIX_FMT_Y10P:\t\tdescr = \"10-bit Greyscale (MIPI Packed)\"; break;\n+\tcase V4L2_PIX_FMT_Y12P:\t\tdescr = \"12-bit Greyscale (MIPI Packed)\"; break;\n \tcase V4L2_PIX_FMT_Y8I:\t\tdescr = \"Interleaved 8-bit Greyscale\"; break;\n \tcase V4L2_PIX_FMT_Y12I:\t\tdescr = \"Interleaved 12-bit Greyscale\"; break;\n \tcase V4L2_PIX_FMT_Z16:\t\tdescr = \"16-bit Depth\"; break;\n--- a/include/uapi/linux/videodev2.h\n+++ b/include/uapi/linux/videodev2.h\n@@ -580,6 +580,7 @@ struct v4l2_pix_format {\n /* Grey bit-packed formats */\n #define V4L2_PIX_FMT_Y10BPACK    v4l2_fourcc('Y', '1', '0', 'B') /* 10  Greyscale bit-packed */\n #define V4L2_PIX_FMT_Y10P    v4l2_fourcc('Y', '1', '0', 'P') /* 10  Greyscale, MIPI RAW10 packed */\n+#define V4L2_PIX_FMT_Y12P    v4l2_fourcc('Y', '1', '2', 'P') /* 12  Greyscale, MIPI RAW12 packed */\n \n /* Palette formats */\n #define V4L2_PIX_FMT_PAL8    v4l2_fourcc('P', 'A', 'L', '8') /*  8  8-bit palette */\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0279-media-Add-a-pixel-format-for-MIPI-packed-14bit-luma-.patch",
    "content": "From e3da593c79ce8e7ab7072fe1551fc1e8b5494eab Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Thu, 25 Jun 2020 17:51:03 +0100\nSubject: [PATCH] media: Add a pixel format for MIPI packed 14bit luma\n only.\n\nThis is the format used by monochrome 14bit image sensors.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n .../userspace-api/media/v4l/pixfmt-y14p.rst   | 54 +++++++++++++++++++\n .../userspace-api/media/v4l/yuv-formats.rst   |  1 +\n drivers/media/v4l2-core/v4l2-ioctl.c          |  1 +\n include/uapi/linux/videodev2.h                |  1 +\n 4 files changed, 57 insertions(+)\n create mode 100644 Documentation/userspace-api/media/v4l/pixfmt-y14p.rst\n\n--- /dev/null\n+++ b/Documentation/userspace-api/media/v4l/pixfmt-y14p.rst\n@@ -0,0 +1,54 @@\n+.. Permission is granted to copy, distribute and/or modify this\n+.. document under the terms of the GNU Free Documentation License,\n+.. Version 1.1 or any later version published by the Free Software\n+.. Foundation, with no Invariant Sections, no Front-Cover Texts\n+.. and no Back-Cover Texts. A copy of the license is included at\n+.. Documentation/media/uapi/fdl-appendix.rst.\n+..\n+.. TODO: replace it to GFDL-1.1-or-later WITH no-invariant-sections\n+\n+.. _V4L2-PIX-FMT-Y14P:\n+\n+**************************\n+V4L2_PIX_FMT_Y14P ('Y14P')\n+**************************\n+\n+Grey-scale image as a MIPI RAW14 packed array\n+\n+\n+Description\n+===========\n+\n+This is a packed grey-scale image format with a depth of 14 bits per\n+pixel. Every four consecutive samples are packed into seven bytes. Each\n+of the first four bytes contain the eight high order bits of the pixels,\n+and the three following bytes contains the six least significants bits of\n+each pixel, in the same order.\n+\n+**Byte Order.**\n+Each cell is one byte.\n+\n+.. tabularcolumns:: |p{1.8cm}|p{1.0cm}|p{1.0cm}|p{1.0cm}|p{1.1cm}|p{3.3cm}|p{3.3cm}|p{3.3cm}|\n+\n+.. flat-table::\n+    :header-rows:  0\n+    :stub-columns: 0\n+    :widths:       2 1 1 1 1 3 3 3\n+\n+\n+    -  -  start + 0:\n+       -  Y'\\ :sub:`00high`\n+       -  Y'\\ :sub:`01high`\n+       -  Y'\\ :sub:`02high`\n+       -  Y'\\ :sub:`03high`\n+       -  Y'\\ :sub:`01low bits 1--0`\\ (bits 7--6)\n+\n+\t  Y'\\ :sub:`00low bits 5--0`\\ (bits 5--0)\n+\n+       -  Y'\\ :sub:`02low bits 3--0`\\ (bits 7--4)\n+\n+\t  Y'\\ :sub:`01low bits 5--2`\\ (bits 3--0)\n+\n+       -  Y'\\ :sub:`03low bits 5--0`\\ (bits 7--2)\n+\n+\t  Y'\\ :sub:`02low bits 5--4`\\ (bits 1--0)\n--- a/Documentation/userspace-api/media/v4l/yuv-formats.rst\n+++ b/Documentation/userspace-api/media/v4l/yuv-formats.rst\n@@ -30,6 +30,7 @@ to brightness information.\n     pixfmt-y12\n     pixfmt-y12p\n     pixfmt-y14\n+    pixfmt-y14p\n     pixfmt-y10b\n     pixfmt-y10p\n     pixfmt-y16\n--- a/drivers/media/v4l2-core/v4l2-ioctl.c\n+++ b/drivers/media/v4l2-core/v4l2-ioctl.c\n@@ -1302,6 +1302,7 @@ static void v4l_fill_fmtdesc(struct v4l2\n \tcase V4L2_PIX_FMT_Y10BPACK:\tdescr = \"10-bit Greyscale (Packed)\"; break;\n \tcase V4L2_PIX_FMT_Y10P:\t\tdescr = \"10-bit Greyscale (MIPI Packed)\"; break;\n \tcase V4L2_PIX_FMT_Y12P:\t\tdescr = \"12-bit Greyscale (MIPI Packed)\"; break;\n+\tcase V4L2_PIX_FMT_Y14P:\t\tdescr = \"14-bit Greyscale (MIPI Packed)\"; break;\n \tcase V4L2_PIX_FMT_Y8I:\t\tdescr = \"Interleaved 8-bit Greyscale\"; break;\n \tcase V4L2_PIX_FMT_Y12I:\t\tdescr = \"Interleaved 12-bit Greyscale\"; break;\n \tcase V4L2_PIX_FMT_Z16:\t\tdescr = \"16-bit Depth\"; break;\n--- a/include/uapi/linux/videodev2.h\n+++ b/include/uapi/linux/videodev2.h\n@@ -581,6 +581,7 @@ struct v4l2_pix_format {\n #define V4L2_PIX_FMT_Y10BPACK    v4l2_fourcc('Y', '1', '0', 'B') /* 10  Greyscale bit-packed */\n #define V4L2_PIX_FMT_Y10P    v4l2_fourcc('Y', '1', '0', 'P') /* 10  Greyscale, MIPI RAW10 packed */\n #define V4L2_PIX_FMT_Y12P    v4l2_fourcc('Y', '1', '2', 'P') /* 12  Greyscale, MIPI RAW12 packed */\n+#define V4L2_PIX_FMT_Y14P    v4l2_fourcc('Y', '1', '4', 'P') /* 14  Greyscale, MIPI RAW12 packed */\n \n /* Palette formats */\n #define V4L2_PIX_FMT_PAL8    v4l2_fourcc('P', 'A', 'L', '8') /*  8  8-bit palette */\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0280-media-bcm2835-unicam-Add-support-for-12bit-mono-pack.patch",
    "content": "From 8fc548dd572d72cda45ffc52f12f42c93049029e Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Thu, 25 Jun 2020 17:53:32 +0100\nSubject: [PATCH] media: bcm2835-unicam: Add support for 12bit mono\n packed format\n\nNow that V4L2_PIX_FMT_Y12P is defined, allow passing raw 12bit\nmono packed data through the peripheral.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n drivers/media/platform/bcm2835/bcm2835-unicam.c | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/drivers/media/platform/bcm2835/bcm2835-unicam.c\n+++ b/drivers/media/platform/bcm2835/bcm2835-unicam.c\n@@ -336,7 +336,7 @@ static const struct unicam_fmt formats[]\n \t\t.depth\t\t= 10,\n \t\t.csi_dt\t\t= 0x2b,\n \t}, {\n-\t\t/* NB There is no packed V4L2 fourcc for this format. */\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_Y12P,\n \t\t.repacked_fourcc = V4L2_PIX_FMT_Y12,\n \t\t.code\t\t= MEDIA_BUS_FMT_Y12_1X12,\n \t\t.depth\t\t= 12,\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0281-media-bcm2835-unicam-Add-support-for-14bit-mono-sour.patch",
    "content": "From dd3b1e96b9d27f26a0aedc2eb5eae08ba1a4ef48 Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Thu, 25 Jun 2020 18:03:47 +0100\nSubject: [PATCH] media: bcm2835-unicam: Add support for 14bit mono\n sources\n\nNow that V4L2_PIX_FMT_Y14 and V4L2_PIX_FMT_Y14P are defined,\nallow passing 14bit mono data through the peripheral.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n drivers/media/platform/bcm2835/bcm2835-unicam.c | 6 ++++++\n 1 file changed, 6 insertions(+)\n\n--- a/drivers/media/platform/bcm2835/bcm2835-unicam.c\n+++ b/drivers/media/platform/bcm2835/bcm2835-unicam.c\n@@ -341,6 +341,12 @@ static const struct unicam_fmt formats[]\n \t\t.code\t\t= MEDIA_BUS_FMT_Y12_1X12,\n \t\t.depth\t\t= 12,\n \t\t.csi_dt\t\t= 0x2c,\n+\t}, {\n+\t\t.fourcc\t\t= V4L2_PIX_FMT_Y14P,\n+\t\t.repacked_fourcc = V4L2_PIX_FMT_Y14,\n+\t\t.code\t\t= MEDIA_BUS_FMT_Y14_1X14,\n+\t\t.depth\t\t= 14,\n+\t\t.csi_dt\t\t= 0x2d,\n \t},\n \t/* Embedded data format */\n \t{\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0282-media-bcm2835-unicam-Add-support-for-unpacked-14bit-.patch",
    "content": "From bdc34f2e9bd66e717888a1867e540a6b4f85b55d Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Wed, 1 Jul 2020 10:57:57 +0100\nSubject: [PATCH] media: bcm2835-unicam: Add support for unpacked 14bit\n Bayer formats\n\nNow that the 14bit non-packed Bayer formats are defined, add them\ninto the supported formats lookup table.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n drivers/media/platform/bcm2835/bcm2835-unicam.c | 4 ++++\n 1 file changed, 4 insertions(+)\n\n--- a/drivers/media/platform/bcm2835/bcm2835-unicam.c\n+++ b/drivers/media/platform/bcm2835/bcm2835-unicam.c\n@@ -299,21 +299,25 @@ static const struct unicam_fmt formats[]\n \t\t.csi_dt\t\t= 0x2c,\n \t}, {\n \t\t.fourcc\t\t= V4L2_PIX_FMT_SBGGR14P,\n+\t\t.repacked_fourcc = V4L2_PIX_FMT_SBGGR14,\n \t\t.code\t\t= MEDIA_BUS_FMT_SBGGR14_1X14,\n \t\t.depth\t\t= 14,\n \t\t.csi_dt\t\t= 0x2d,\n \t}, {\n \t\t.fourcc\t\t= V4L2_PIX_FMT_SGBRG14P,\n+\t\t.repacked_fourcc = V4L2_PIX_FMT_SGBRG14,\n \t\t.code\t\t= MEDIA_BUS_FMT_SGBRG14_1X14,\n \t\t.depth\t\t= 14,\n \t\t.csi_dt\t\t= 0x2d,\n \t}, {\n \t\t.fourcc\t\t= V4L2_PIX_FMT_SGRBG14P,\n+\t\t.repacked_fourcc = V4L2_PIX_FMT_SGRBG14,\n \t\t.code\t\t= MEDIA_BUS_FMT_SGRBG14_1X14,\n \t\t.depth\t\t= 14,\n \t\t.csi_dt\t\t= 0x2d,\n \t}, {\n \t\t.fourcc\t\t= V4L2_PIX_FMT_SRGGB14P,\n+\t\t.repacked_fourcc = V4L2_PIX_FMT_SRGGB14,\n \t\t.code\t\t= MEDIA_BUS_FMT_SRGGB14_1X14,\n \t\t.depth\t\t= 14,\n \t\t.csi_dt\t\t= 0x2d,\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0283-bcm2835-dma-Add-NO_WAIT_RESP-flag.patch",
    "content": "From 33528413733fa956913cfe139dcd3ddd550839e4 Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.com>\nDate: Wed, 1 Jul 2020 20:28:27 +0100\nSubject: [PATCH] bcm2835-dma: Add NO_WAIT_RESP flag\n\nUse bit 27 of the dreq value (the second cell of the DT DMA descriptor)\nto request that the WAIT_RESP bit is not set.\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.com>\n---\n drivers/dma/bcm2835-dma.c | 11 ++++++++---\n 1 file changed, 8 insertions(+), 3 deletions(-)\n\n--- a/drivers/dma/bcm2835-dma.c\n+++ b/drivers/dma/bcm2835-dma.c\n@@ -165,6 +165,11 @@ struct bcm2835_desc {\n #define BCM2835_DMA_WAIT(x)\t((x & 31) << 21) /* add DMA-wait cycles */\n #define BCM2835_DMA_NO_WIDE_BURSTS BIT(26) /* no 2 beat write bursts */\n \n+/* A fake bit to request that the driver doesn't set the WAIT_RESP bit. */\n+#define BCM2835_DMA_NO_WAIT_RESP BIT(27)\n+#define WAIT_RESP(x) ((x & BCM2835_DMA_NO_WAIT_RESP) ? \\\n+\t\t      0 : BCM2835_DMA_WAIT_RESP)\n+\n /* debug register bits */\n #define BCM2835_DMA_DEBUG_LAST_NOT_SET_ERR\tBIT(0)\n #define BCM2835_DMA_DEBUG_FIFO_ERR\t\tBIT(1)\n@@ -843,7 +848,7 @@ static struct dma_async_tx_descriptor *b\n \tstruct bcm2835_chan *c = to_bcm2835_dma_chan(chan);\n \tstruct bcm2835_desc *d;\n \tu32 info = BCM2835_DMA_D_INC | BCM2835_DMA_S_INC;\n-\tu32 extra = BCM2835_DMA_INT_EN | BCM2835_DMA_WAIT_RESP;\n+\tu32 extra = BCM2835_DMA_INT_EN | WAIT_RESP(c->dreq);\n \tsize_t max_len = bcm2835_dma_max_frame_length(c);\n \tsize_t frames;\n \n@@ -873,7 +878,7 @@ static struct dma_async_tx_descriptor *b\n \tstruct bcm2835_chan *c = to_bcm2835_dma_chan(chan);\n \tstruct bcm2835_desc *d;\n \tdma_addr_t src = 0, dst = 0;\n-\tu32 info = BCM2835_DMA_WAIT_RESP;\n+\tu32 info = WAIT_RESP(c->dreq);\n \tu32 extra = BCM2835_DMA_INT_EN;\n \tsize_t frames;\n \n@@ -935,7 +940,7 @@ static struct dma_async_tx_descriptor *b\n \tstruct bcm2835_chan *c = to_bcm2835_dma_chan(chan);\n \tstruct bcm2835_desc *d;\n \tdma_addr_t src, dst;\n-\tu32 info = BCM2835_DMA_WAIT_RESP;\n+\tu32 info = WAIT_RESP(c->dreq);\n \tu32 extra = 0;\n \tsize_t max_len = bcm2835_dma_max_frame_length(c);\n \tsize_t frames;\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0284-media-i2c-add-ov9281-driver.patch",
    "content": "From 63ef88ff48e864eed44d25e6edd61c743e6efd30 Mon Sep 17 00:00:00 2001\nFrom: Zefa Chen <zefa.chen@rock-chips.com>\nDate: Fri, 17 May 2019 18:23:03 +0800\nSubject: [PATCH] media: i2c: add ov9281 driver.\n\nChange-Id: I7b77250bbc56d2f861450cf77271ad15f9b88ab1\nSigned-off-by: Zefa Chen <zefa.chen@rock-chips.com>\n---\n drivers/media/i2c/Kconfig  |   11 +\n drivers/media/i2c/Makefile |    1 +\n drivers/media/i2c/ov9281.c | 1171 ++++++++++++++++++++++++++++++++++++\n 3 files changed, 1183 insertions(+)\n create mode 100644 drivers/media/i2c/ov9281.c\n\n--- a/drivers/media/i2c/Kconfig\n+++ b/drivers/media/i2c/Kconfig\n@@ -1040,6 +1040,17 @@ config VIDEO_OV9640\n \t  This is a Video4Linux2 sensor driver for the OmniVision\n \t  OV9640 camera sensor.\n \n+config VIDEO_OV9281\n+\ttristate \"OmniVision OV9281 sensor support\"\n+\tdepends on I2C && VIDEO_V4L2\n+\tdepends on MEDIA_CAMERA_SUPPORT\n+\thelp\n+\t  This is a Video4Linux2 sensor-level driver for the OmniVision\n+\t  OV9281 camera.\n+\n+\t  To compile this driver as a module, choose M here: the\n+\t  module will be called ov9281.\n+\n config VIDEO_OV9650\n \ttristate \"OmniVision OV9650/OV9652 sensor support\"\n \tdepends on I2C && VIDEO_V4L2\n--- a/drivers/media/i2c/Makefile\n+++ b/drivers/media/i2c/Makefile\n@@ -81,6 +81,7 @@ obj-$(CONFIG_VIDEO_OV7670) += ov7670.o\n obj-$(CONFIG_VIDEO_OV772X) += ov772x.o\n obj-$(CONFIG_VIDEO_OV7740) += ov7740.o\n obj-$(CONFIG_VIDEO_OV8856) += ov8856.o\n+obj-$(CONFIG_VIDEO_OV9281) += ov9281.o\n obj-$(CONFIG_VIDEO_OV9640) += ov9640.o\n obj-$(CONFIG_VIDEO_OV9650) += ov9650.o\n obj-$(CONFIG_VIDEO_OV13858) += ov13858.o\n--- /dev/null\n+++ b/drivers/media/i2c/ov9281.c\n@@ -0,0 +1,1171 @@\n+// SPDX-License-Identifier: GPL-2.0\n+/*\n+ * ov9281 driver\n+ *\n+ * Copyright (C) 2017 Fuzhou Rockchip Electronics Co., Ltd.\n+ */\n+\n+#include <linux/clk.h>\n+#include <linux/device.h>\n+#include <linux/delay.h>\n+#include <linux/gpio/consumer.h>\n+#include <linux/i2c.h>\n+#include <linux/module.h>\n+#include <linux/pm_runtime.h>\n+#include <linux/regulator/consumer.h>\n+#include <linux/sysfs.h>\n+#include <linux/slab.h>\n+#include <linux/rk-camera-module.h>\n+#include <media/media-entity.h>\n+#include <media/v4l2-async.h>\n+#include <media/v4l2-ctrls.h>\n+#include <media/v4l2-subdev.h>\n+#include <linux/pinctrl/consumer.h>\n+\n+#define DRIVER_VERSION\t\t\tKERNEL_VERSION(0, 0x01, 0x0)\n+\n+#ifndef V4L2_CID_DIGITAL_GAIN\n+#define V4L2_CID_DIGITAL_GAIN\t\tV4L2_CID_GAIN\n+#endif\n+\n+#define OV9281_LINK_FREQ_400MHZ\t\t400000000\n+/* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */\n+#define OV9281_PIXEL_RATE\t\t(OV9281_LINK_FREQ_400MHZ * 2 * 2 / 10)\n+#define OV9281_XVCLK_FREQ\t\t24000000\n+\n+#define CHIP_ID\t\t\t\t0x9281\n+#define OV9281_REG_CHIP_ID\t\t0x300a\n+\n+#define OV9281_REG_CTRL_MODE\t\t0x0100\n+#define OV9281_MODE_SW_STANDBY\t\t0x0\n+#define OV9281_MODE_STREAMING\t\tBIT(0)\n+\n+#define OV9281_REG_EXPOSURE\t\t0x3500\n+#define\tOV9281_EXPOSURE_MIN\t\t4\n+#define\tOV9281_EXPOSURE_STEP\t\t1\n+#define OV9281_VTS_MAX\t\t\t0x7fff\n+\n+#define OV9281_REG_GAIN_H\t\t0x3508\n+#define OV9281_REG_GAIN_L\t\t0x3509\n+#define OV9281_GAIN_H_MASK\t\t0x07\n+#define OV9281_GAIN_H_SHIFT\t\t8\n+#define OV9281_GAIN_L_MASK\t\t0xff\n+#define OV9281_GAIN_MIN\t\t\t0x10\n+#define OV9281_GAIN_MAX\t\t\t0xf8\n+#define OV9281_GAIN_STEP\t\t1\n+#define OV9281_GAIN_DEFAULT\t\t0x10\n+\n+#define OV9281_REG_TEST_PATTERN\t\t0x5e00\n+#define OV9281_TEST_PATTERN_ENABLE\t0x80\n+#define OV9281_TEST_PATTERN_DISABLE\t0x0\n+\n+#define OV9281_REG_VTS\t\t\t0x380e\n+\n+#define REG_NULL\t\t\t0xFFFF\n+\n+#define OV9281_REG_VALUE_08BIT\t\t1\n+#define OV9281_REG_VALUE_16BIT\t\t2\n+#define OV9281_REG_VALUE_24BIT\t\t3\n+\n+#define OV9281_LANES\t\t\t2\n+#define OV9281_BITS_PER_SAMPLE\t\t10\n+\n+#define OF_CAMERA_PINCTRL_STATE_DEFAULT\t\"rockchip,camera_default\"\n+#define OF_CAMERA_PINCTRL_STATE_SLEEP\t\"rockchip,camera_sleep\"\n+\n+#define OV9281_NAME\t\t\t\"ov9281\"\n+\n+static const char * const ov9281_supply_names[] = {\n+\t\"avdd\",\t\t/* Analog power */\n+\t\"dovdd\",\t/* Digital I/O power */\n+\t\"dvdd\",\t\t/* Digital core power */\n+};\n+\n+#define OV9281_NUM_SUPPLIES ARRAY_SIZE(ov9281_supply_names)\n+\n+struct regval {\n+\tu16 addr;\n+\tu8 val;\n+};\n+\n+struct ov9281_mode {\n+\tu32 width;\n+\tu32 height;\n+\tu32 max_fps;\n+\tu32 hts_def;\n+\tu32 vts_def;\n+\tu32 exp_def;\n+\tconst struct regval *reg_list;\n+};\n+\n+struct ov9281 {\n+\tstruct i2c_client\t*client;\n+\tstruct clk\t\t*xvclk;\n+\tstruct gpio_desc\t*reset_gpio;\n+\tstruct gpio_desc\t*pwdn_gpio;\n+\tstruct regulator_bulk_data supplies[OV9281_NUM_SUPPLIES];\n+\n+\tstruct pinctrl\t\t*pinctrl;\n+\tstruct pinctrl_state\t*pins_default;\n+\tstruct pinctrl_state\t*pins_sleep;\n+\n+\tstruct v4l2_subdev\tsubdev;\n+\tstruct media_pad\tpad;\n+\tstruct v4l2_ctrl_handler ctrl_handler;\n+\tstruct v4l2_ctrl\t*exposure;\n+\tstruct v4l2_ctrl\t*anal_gain;\n+\tstruct v4l2_ctrl\t*digi_gain;\n+\tstruct v4l2_ctrl\t*hblank;\n+\tstruct v4l2_ctrl\t*vblank;\n+\tstruct v4l2_ctrl\t*test_pattern;\n+\tstruct mutex\t\tmutex;\n+\tbool\t\t\tstreaming;\n+\tbool\t\t\tpower_on;\n+\tconst struct ov9281_mode *cur_mode;\n+\tu32\t\t\tmodule_index;\n+\tconst char\t\t*module_facing;\n+\tconst char\t\t*module_name;\n+\tconst char\t\t*len_name;\n+};\n+\n+#define to_ov9281(sd) container_of(sd, struct ov9281, subdev)\n+\n+/*\n+ * Xclk 24Mhz\n+ */\n+static const struct regval ov9281_global_regs[] = {\n+\t{REG_NULL, 0x00},\n+};\n+\n+/*\n+ * Xclk 24Mhz\n+ * max_framerate 120fps\n+ * mipi_datarate per lane 800Mbps\n+ */\n+static const struct regval ov9281_1280x800_regs[] = {\n+\t{0x0103, 0x01},\n+\t{0x0302, 0x32},\n+\t{0x030d, 0x50},\n+\t{0x030e, 0x02},\n+\t{0x3001, 0x00},\n+\t{0x3004, 0x00},\n+\t{0x3005, 0x00},\n+\t{0x3006, 0x04},\n+\t{0x3011, 0x0a},\n+\t{0x3013, 0x18},\n+\t{0x3022, 0x01},\n+\t{0x3023, 0x00},\n+\t{0x302c, 0x00},\n+\t{0x302f, 0x00},\n+\t{0x3030, 0x04},\n+\t{0x3039, 0x32},\n+\t{0x303a, 0x00},\n+\t{0x303f, 0x01},\n+\t{0x3500, 0x00},\n+\t{0x3501, 0x2a},\n+\t{0x3502, 0x90},\n+\t{0x3503, 0x08},\n+\t{0x3505, 0x8c},\n+\t{0x3507, 0x03},\n+\t{0x3508, 0x00},\n+\t{0x3509, 0x10},\n+\t{0x3610, 0x80},\n+\t{0x3611, 0xa0},\n+\t{0x3620, 0x6f},\n+\t{0x3632, 0x56},\n+\t{0x3633, 0x78},\n+\t{0x3662, 0x05},\n+\t{0x3666, 0x00},\n+\t{0x366f, 0x5a},\n+\t{0x3680, 0x84},\n+\t{0x3712, 0x80},\n+\t{0x372d, 0x22},\n+\t{0x3731, 0x80},\n+\t{0x3732, 0x30},\n+\t{0x3778, 0x00},\n+\t{0x377d, 0x22},\n+\t{0x3788, 0x02},\n+\t{0x3789, 0xa4},\n+\t{0x378a, 0x00},\n+\t{0x378b, 0x4a},\n+\t{0x3799, 0x20},\n+\t{0x3800, 0x00},\n+\t{0x3801, 0x00},\n+\t{0x3802, 0x00},\n+\t{0x3803, 0x00},\n+\t{0x3804, 0x05},\n+\t{0x3805, 0x0f},\n+\t{0x3806, 0x03},\n+\t{0x3807, 0x2f},\n+\t{0x3808, 0x05},\n+\t{0x3809, 0x00},\n+\t{0x380a, 0x03},\n+\t{0x380b, 0x20},\n+\t{0x380c, 0x02},\n+\t{0x380d, 0xd8},\n+\t{0x380e, 0x03},\n+\t{0x380f, 0x8e},\n+\t{0x3810, 0x00},\n+\t{0x3811, 0x08},\n+\t{0x3812, 0x00},\n+\t{0x3813, 0x08},\n+\t{0x3814, 0x11},\n+\t{0x3815, 0x11},\n+\t{0x3820, 0x40},\n+\t{0x3821, 0x00},\n+\t{0x3881, 0x42},\n+\t{0x38b1, 0x00},\n+\t{0x3920, 0xff},\n+\t{0x4003, 0x40},\n+\t{0x4008, 0x04},\n+\t{0x4009, 0x0b},\n+\t{0x400c, 0x00},\n+\t{0x400d, 0x07},\n+\t{0x4010, 0x40},\n+\t{0x4043, 0x40},\n+\t{0x4307, 0x30},\n+\t{0x4317, 0x00},\n+\t{0x4501, 0x00},\n+\t{0x4507, 0x00},\n+\t{0x4509, 0x00},\n+\t{0x450a, 0x08},\n+\t{0x4601, 0x04},\n+\t{0x470f, 0x00},\n+\t{0x4f07, 0x00},\n+\t{0x4800, 0x00},\n+\t{0x5000, 0x9f},\n+\t{0x5001, 0x00},\n+\t{0x5e00, 0x00},\n+\t{0x5d00, 0x07},\n+\t{0x5d01, 0x00},\n+\t{REG_NULL, 0x00},\n+};\n+\n+static const struct ov9281_mode supported_modes[] = {\n+\t{\n+\t\t.width = 1280,\n+\t\t.height = 800,\n+\t\t.max_fps = 120,\n+\t\t.exp_def = 0x0320,\n+\t\t.hts_def = 0x0b60,//0x2d8*4\n+\t\t.vts_def = 0x038e,\n+\t\t.reg_list = ov9281_1280x800_regs,\n+\t},\n+};\n+\n+static const s64 link_freq_menu_items[] = {\n+\tOV9281_LINK_FREQ_400MHZ\n+};\n+\n+static const char * const ov9281_test_pattern_menu[] = {\n+\t\"Disabled\",\n+\t\"Vertical Color Bar Type 1\",\n+\t\"Vertical Color Bar Type 2\",\n+\t\"Vertical Color Bar Type 3\",\n+\t\"Vertical Color Bar Type 4\"\n+};\n+\n+/* Write registers up to 4 at a time */\n+static int ov9281_write_reg(struct i2c_client *client, u16 reg,\n+\t\t\t    u32 len, u32 val)\n+{\n+\tu32 buf_i, val_i;\n+\tu8 buf[6];\n+\tu8 *val_p;\n+\t__be32 val_be;\n+\n+\tif (len > 4)\n+\t\treturn -EINVAL;\n+\n+\tbuf[0] = reg >> 8;\n+\tbuf[1] = reg & 0xff;\n+\n+\tval_be = cpu_to_be32(val);\n+\tval_p = (u8 *)&val_be;\n+\tbuf_i = 2;\n+\tval_i = 4 - len;\n+\n+\twhile (val_i < 4)\n+\t\tbuf[buf_i++] = val_p[val_i++];\n+\n+\tif (i2c_master_send(client, buf, len + 2) != len + 2)\n+\t\treturn -EIO;\n+\n+\treturn 0;\n+}\n+\n+static int ov9281_write_array(struct i2c_client *client,\n+\t\t\t      const struct regval *regs)\n+{\n+\tu32 i;\n+\tint ret = 0;\n+\n+\tfor (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++)\n+\t\tret = ov9281_write_reg(client, regs[i].addr,\n+\t\t\t\t       OV9281_REG_VALUE_08BIT, regs[i].val);\n+\n+\treturn ret;\n+}\n+\n+/* Read registers up to 4 at a time */\n+static int ov9281_read_reg(struct i2c_client *client, u16 reg, unsigned int len,\n+\t\t\t   u32 *val)\n+{\n+\tstruct i2c_msg msgs[2];\n+\tu8 *data_be_p;\n+\t__be32 data_be = 0;\n+\t__be16 reg_addr_be = cpu_to_be16(reg);\n+\tint ret;\n+\n+\tif (len > 4 || !len)\n+\t\treturn -EINVAL;\n+\n+\tdata_be_p = (u8 *)&data_be;\n+\t/* Write register address */\n+\tmsgs[0].addr = client->addr;\n+\tmsgs[0].flags = 0;\n+\tmsgs[0].len = 2;\n+\tmsgs[0].buf = (u8 *)&reg_addr_be;\n+\n+\t/* Read data from register */\n+\tmsgs[1].addr = client->addr;\n+\tmsgs[1].flags = I2C_M_RD;\n+\tmsgs[1].len = len;\n+\tmsgs[1].buf = &data_be_p[4 - len];\n+\n+\tret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));\n+\tif (ret != ARRAY_SIZE(msgs))\n+\t\treturn -EIO;\n+\n+\t*val = be32_to_cpu(data_be);\n+\n+\treturn 0;\n+}\n+\n+static int ov9281_get_reso_dist(const struct ov9281_mode *mode,\n+\t\t\t\tstruct v4l2_mbus_framefmt *framefmt)\n+{\n+\treturn abs(mode->width - framefmt->width) +\n+\t       abs(mode->height - framefmt->height);\n+}\n+\n+static const struct ov9281_mode *\n+ov9281_find_best_fit(struct v4l2_subdev_format *fmt)\n+{\n+\tstruct v4l2_mbus_framefmt *framefmt = &fmt->format;\n+\tint dist;\n+\tint cur_best_fit = 0;\n+\tint cur_best_fit_dist = -1;\n+\tunsigned int i;\n+\n+\tfor (i = 0; i < ARRAY_SIZE(supported_modes); i++) {\n+\t\tdist = ov9281_get_reso_dist(&supported_modes[i], framefmt);\n+\t\tif (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {\n+\t\t\tcur_best_fit_dist = dist;\n+\t\t\tcur_best_fit = i;\n+\t\t}\n+\t}\n+\n+\treturn &supported_modes[cur_best_fit];\n+}\n+\n+static int ov9281_set_fmt(struct v4l2_subdev *sd,\n+\t\t\t  struct v4l2_subdev_pad_config *cfg,\n+\t\t\t  struct v4l2_subdev_format *fmt)\n+{\n+\tstruct ov9281 *ov9281 = to_ov9281(sd);\n+\tconst struct ov9281_mode *mode;\n+\ts64 h_blank, vblank_def;\n+\n+\tmutex_lock(&ov9281->mutex);\n+\n+\tmode = ov9281_find_best_fit(fmt);\n+\tfmt->format.code = MEDIA_BUS_FMT_Y10_1X10;\n+\tfmt->format.width = mode->width;\n+\tfmt->format.height = mode->height;\n+\tfmt->format.field = V4L2_FIELD_NONE;\n+\tif (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {\n+#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API\n+\t\t*v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;\n+#else\n+\t\tmutex_unlock(&ov9281->mutex);\n+\t\treturn -ENOTTY;\n+#endif\n+\t} else {\n+\t\tov9281->cur_mode = mode;\n+\t\th_blank = mode->hts_def - mode->width;\n+\t\t__v4l2_ctrl_modify_range(ov9281->hblank, h_blank,\n+\t\t\t\t\t h_blank, 1, h_blank);\n+\t\tvblank_def = mode->vts_def - mode->height;\n+\t\t__v4l2_ctrl_modify_range(ov9281->vblank, vblank_def,\n+\t\t\t\t\t OV9281_VTS_MAX - mode->height,\n+\t\t\t\t\t 1, vblank_def);\n+\t}\n+\n+\tmutex_unlock(&ov9281->mutex);\n+\n+\treturn 0;\n+}\n+\n+static int ov9281_get_fmt(struct v4l2_subdev *sd,\n+\t\t\t  struct v4l2_subdev_pad_config *cfg,\n+\t\t\t  struct v4l2_subdev_format *fmt)\n+{\n+\tstruct ov9281 *ov9281 = to_ov9281(sd);\n+\tconst struct ov9281_mode *mode = ov9281->cur_mode;\n+\n+\tmutex_lock(&ov9281->mutex);\n+\tif (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {\n+#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API\n+\t\tfmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);\n+#else\n+\t\tmutex_unlock(&ov9281->mutex);\n+\t\treturn -ENOTTY;\n+#endif\n+\t} else {\n+\t\tfmt->format.width = mode->width;\n+\t\tfmt->format.height = mode->height;\n+\t\tfmt->format.code = MEDIA_BUS_FMT_Y10_1X10;\n+\t\tfmt->format.field = V4L2_FIELD_NONE;\n+\t}\n+\tmutex_unlock(&ov9281->mutex);\n+\n+\treturn 0;\n+}\n+\n+static int ov9281_enum_mbus_code(struct v4l2_subdev *sd,\n+\t\t\t\t struct v4l2_subdev_pad_config *cfg,\n+\t\t\t\t struct v4l2_subdev_mbus_code_enum *code)\n+{\n+\tif (code->index != 0)\n+\t\treturn -EINVAL;\n+\tcode->code = MEDIA_BUS_FMT_Y10_1X10;\n+\n+\treturn 0;\n+}\n+\n+static int ov9281_enum_frame_sizes(struct v4l2_subdev *sd,\n+\t\t\t\t   struct v4l2_subdev_pad_config *cfg,\n+\t\t\t\t   struct v4l2_subdev_frame_size_enum *fse)\n+{\n+\tif (fse->index >= ARRAY_SIZE(supported_modes))\n+\t\treturn -EINVAL;\n+\n+\tif (fse->code != MEDIA_BUS_FMT_Y10_1X10)\n+\t\treturn -EINVAL;\n+\n+\tfse->min_width  = supported_modes[fse->index].width;\n+\tfse->max_width  = supported_modes[fse->index].width;\n+\tfse->max_height = supported_modes[fse->index].height;\n+\tfse->min_height = supported_modes[fse->index].height;\n+\n+\treturn 0;\n+}\n+\n+static int ov9281_enable_test_pattern(struct ov9281 *ov9281, u32 pattern)\n+{\n+\tu32 val;\n+\n+\tif (pattern)\n+\t\tval = (pattern - 1) | OV9281_TEST_PATTERN_ENABLE;\n+\telse\n+\t\tval = OV9281_TEST_PATTERN_DISABLE;\n+\n+\treturn ov9281_write_reg(ov9281->client, OV9281_REG_TEST_PATTERN,\n+\t\t\t\tOV9281_REG_VALUE_08BIT, val);\n+}\n+\n+static int OV9281_g_frame_interval(struct v4l2_subdev *sd,\n+\t\t\t\t   struct v4l2_subdev_frame_interval *fi)\n+{\n+\tstruct ov9281 *ov9281 = to_ov9281(sd);\n+\tconst struct ov9281_mode *mode = ov9281->cur_mode;\n+\n+\tmutex_lock(&ov9281->mutex);\n+\tfi->interval.numerator = 10000;\n+\tfi->interval.denominator = mode->max_fps * 10000;\n+\tmutex_unlock(&ov9281->mutex);\n+\n+\treturn 0;\n+}\n+\n+static void ov9281_get_module_inf(struct ov9281 *ov9281,\n+\t\t\t\t  struct rkmodule_inf *inf)\n+{\n+\tmemset(inf, 0, sizeof(*inf));\n+\tstrlcpy(inf->base.sensor, OV9281_NAME, sizeof(inf->base.sensor));\n+\tstrlcpy(inf->base.module, ov9281->module_name,\n+\t\tsizeof(inf->base.module));\n+\tstrlcpy(inf->base.lens, ov9281->len_name, sizeof(inf->base.lens));\n+}\n+\n+static long ov9281_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)\n+{\n+\tstruct ov9281 *ov9281 = to_ov9281(sd);\n+\tlong ret = 0;\n+\n+\tswitch (cmd) {\n+\tcase RKMODULE_GET_MODULE_INFO:\n+\t\tov9281_get_module_inf(ov9281, (struct rkmodule_inf *)arg);\n+\t\tbreak;\n+\tdefault:\n+\t\tret = -ENOIOCTLCMD;\n+\t\tbreak;\n+\t}\n+\n+\treturn ret;\n+}\n+\n+#ifdef CONFIG_COMPAT\n+static long ov9281_compat_ioctl32(struct v4l2_subdev *sd,\n+\t\t\t\t  unsigned int cmd, unsigned long arg)\n+{\n+\tvoid __user *up = compat_ptr(arg);\n+\tstruct rkmodule_inf *inf;\n+\tstruct rkmodule_awb_cfg *cfg;\n+\tlong ret;\n+\n+\tswitch (cmd) {\n+\tcase RKMODULE_GET_MODULE_INFO:\n+\t\tinf = kzalloc(sizeof(*inf), GFP_KERNEL);\n+\t\tif (!inf) {\n+\t\t\tret = -ENOMEM;\n+\t\t\treturn ret;\n+\t\t}\n+\n+\t\tret = ov9281_ioctl(sd, cmd, inf);\n+\t\tif (!ret)\n+\t\t\tret = copy_to_user(up, inf, sizeof(*inf));\n+\t\tkfree(inf);\n+\t\tbreak;\n+\tcase RKMODULE_AWB_CFG:\n+\t\tcfg = kzalloc(sizeof(*cfg), GFP_KERNEL);\n+\t\tif (!cfg) {\n+\t\t\tret = -ENOMEM;\n+\t\t\treturn ret;\n+\t\t}\n+\n+\t\tret = copy_from_user(cfg, up, sizeof(*cfg));\n+\t\tif (!ret)\n+\t\t\tret = ov9281_ioctl(sd, cmd, cfg);\n+\t\tkfree(cfg);\n+\t\tbreak;\n+\tdefault:\n+\t\tret = -ENOIOCTLCMD;\n+\t\tbreak;\n+\t}\n+\n+\treturn ret;\n+}\n+#endif\n+\n+static int __ov9281_start_stream(struct ov9281 *ov9281)\n+{\n+\tint ret;\n+\n+\tret = ov9281_write_array(ov9281->client, ov9281->cur_mode->reg_list);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\t/* In case these controls are set before streaming */\n+\tmutex_unlock(&ov9281->mutex);\n+\tret = v4l2_ctrl_handler_setup(&ov9281->ctrl_handler);\n+\tmutex_lock(&ov9281->mutex);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\treturn ov9281_write_reg(ov9281->client, OV9281_REG_CTRL_MODE,\n+\t\t\t\tOV9281_REG_VALUE_08BIT, OV9281_MODE_STREAMING);\n+}\n+\n+static int __ov9281_stop_stream(struct ov9281 *ov9281)\n+{\n+\treturn ov9281_write_reg(ov9281->client, OV9281_REG_CTRL_MODE,\n+\t\t\t\tOV9281_REG_VALUE_08BIT, OV9281_MODE_SW_STANDBY);\n+}\n+\n+static int ov9281_s_stream(struct v4l2_subdev *sd, int on)\n+{\n+\tstruct ov9281 *ov9281 = to_ov9281(sd);\n+\tstruct i2c_client *client = ov9281->client;\n+\tint ret = 0;\n+\n+\tmutex_lock(&ov9281->mutex);\n+\ton = !!on;\n+\tif (on == ov9281->streaming)\n+\t\tgoto unlock_and_return;\n+\n+\tif (on) {\n+\t\tret = pm_runtime_get_sync(&client->dev);\n+\t\tif (ret < 0) {\n+\t\t\tpm_runtime_put_noidle(&client->dev);\n+\t\t\tgoto unlock_and_return;\n+\t\t}\n+\n+\t\tret = __ov9281_start_stream(ov9281);\n+\t\tif (ret) {\n+\t\t\tv4l2_err(sd, \"start stream failed while write regs\\n\");\n+\t\t\tpm_runtime_put(&client->dev);\n+\t\t\tgoto unlock_and_return;\n+\t\t}\n+\t} else {\n+\t\t__ov9281_stop_stream(ov9281);\n+\t\tpm_runtime_put(&client->dev);\n+\t}\n+\n+\tov9281->streaming = on;\n+\n+unlock_and_return:\n+\tmutex_unlock(&ov9281->mutex);\n+\n+\treturn ret;\n+}\n+\n+static int ov9281_s_power(struct v4l2_subdev *sd, int on)\n+{\n+\tstruct ov9281 *ov9281 = to_ov9281(sd);\n+\tstruct i2c_client *client = ov9281->client;\n+\tint ret = 0;\n+\n+\tmutex_lock(&ov9281->mutex);\n+\n+\t/* If the power state is not modified - no work to do. */\n+\tif (ov9281->power_on == !!on)\n+\t\tgoto unlock_and_return;\n+\n+\tif (on) {\n+\t\tret = pm_runtime_get_sync(&client->dev);\n+\t\tif (ret < 0) {\n+\t\t\tpm_runtime_put_noidle(&client->dev);\n+\t\t\tgoto unlock_and_return;\n+\t\t}\n+\t\tret = ov9281_write_array(ov9281->client, ov9281_global_regs);\n+\t\tif (ret) {\n+\t\t\tv4l2_err(sd, \"could not set init registers\\n\");\n+\t\t\tpm_runtime_put_noidle(&client->dev);\n+\t\t\tgoto unlock_and_return;\n+\t\t}\n+\t\tov9281->power_on = true;\n+\t} else {\n+\t\tpm_runtime_put(&client->dev);\n+\t\tov9281->power_on = false;\n+\t}\n+\n+unlock_and_return:\n+\tmutex_unlock(&ov9281->mutex);\n+\n+\treturn ret;\n+}\n+\n+/* Calculate the delay in us by clock rate and clock cycles */\n+static inline u32 ov9281_cal_delay(u32 cycles)\n+{\n+\treturn DIV_ROUND_UP(cycles, OV9281_XVCLK_FREQ / 1000 / 1000);\n+}\n+\n+static int __ov9281_power_on(struct ov9281 *ov9281)\n+{\n+\tint ret;\n+\tu32 delay_us;\n+\tstruct device *dev = &ov9281->client->dev;\n+\n+\tif (!IS_ERR_OR_NULL(ov9281->pins_default)) {\n+\t\tret = pinctrl_select_state(ov9281->pinctrl,\n+\t\t\t\t\t   ov9281->pins_default);\n+\t\tif (ret < 0)\n+\t\t\tdev_err(dev, \"could not set pins\\n\");\n+\t}\n+\n+\tret = clk_prepare_enable(ov9281->xvclk);\n+\tif (ret < 0) {\n+\t\tdev_err(dev, \"Failed to enable xvclk\\n\");\n+\t\treturn ret;\n+\t}\n+\n+\tif (!IS_ERR(ov9281->reset_gpio))\n+\t\tgpiod_set_value_cansleep(ov9281->reset_gpio, 0);\n+\n+\tret = regulator_bulk_enable(OV9281_NUM_SUPPLIES, ov9281->supplies);\n+\tif (ret < 0) {\n+\t\tdev_err(dev, \"Failed to enable regulators\\n\");\n+\t\tgoto disable_clk;\n+\t}\n+\n+\tif (!IS_ERR(ov9281->reset_gpio))\n+\t\tgpiod_set_value_cansleep(ov9281->reset_gpio, 1);\n+\n+\tusleep_range(500, 1000);\n+\tif (!IS_ERR(ov9281->pwdn_gpio))\n+\t\tgpiod_set_value_cansleep(ov9281->pwdn_gpio, 1);\n+\n+\t/* 8192 cycles prior to first SCCB transaction */\n+\tdelay_us = ov9281_cal_delay(8192);\n+\tusleep_range(delay_us, delay_us * 2);\n+\n+\treturn 0;\n+\n+disable_clk:\n+\tclk_disable_unprepare(ov9281->xvclk);\n+\n+\treturn ret;\n+}\n+\n+static void __ov9281_power_off(struct ov9281 *ov9281)\n+{\n+\tint ret;\n+\tstruct device *dev = &ov9281->client->dev;\n+\n+\tif (!IS_ERR(ov9281->pwdn_gpio))\n+\t\tgpiod_set_value_cansleep(ov9281->pwdn_gpio, 0);\n+\tclk_disable_unprepare(ov9281->xvclk);\n+\tif (!IS_ERR(ov9281->reset_gpio))\n+\t\tgpiod_set_value_cansleep(ov9281->reset_gpio, 0);\n+\tif (!IS_ERR_OR_NULL(ov9281->pins_sleep)) {\n+\t\tret = pinctrl_select_state(ov9281->pinctrl,\n+\t\t\t\t\t   ov9281->pins_sleep);\n+\t\tif (ret < 0)\n+\t\t\tdev_dbg(dev, \"could not set pins\\n\");\n+\t}\n+\tregulator_bulk_disable(OV9281_NUM_SUPPLIES, ov9281->supplies);\n+}\n+\n+static int ov9281_runtime_resume(struct device *dev)\n+{\n+\tstruct i2c_client *client = to_i2c_client(dev);\n+\tstruct v4l2_subdev *sd = i2c_get_clientdata(client);\n+\tstruct ov9281 *ov9281 = to_ov9281(sd);\n+\n+\treturn __ov9281_power_on(ov9281);\n+}\n+\n+static int ov9281_runtime_suspend(struct device *dev)\n+{\n+\tstruct i2c_client *client = to_i2c_client(dev);\n+\tstruct v4l2_subdev *sd = i2c_get_clientdata(client);\n+\tstruct ov9281 *ov9281 = to_ov9281(sd);\n+\n+\t__ov9281_power_off(ov9281);\n+\n+\treturn 0;\n+}\n+\n+#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API\n+static int ov9281_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)\n+{\n+\tstruct ov9281 *ov9281 = to_ov9281(sd);\n+\tstruct v4l2_mbus_framefmt *try_fmt =\n+\t\t\t\tv4l2_subdev_get_try_format(sd, fh->pad, 0);\n+\tconst struct ov9281_mode *def_mode = &supported_modes[0];\n+\n+\tmutex_lock(&ov9281->mutex);\n+\t/* Initialize try_fmt */\n+\ttry_fmt->width = def_mode->width;\n+\ttry_fmt->height = def_mode->height;\n+\ttry_fmt->code = MEDIA_BUS_FMT_Y10_1X10;\n+\ttry_fmt->field = V4L2_FIELD_NONE;\n+\n+\tmutex_unlock(&ov9281->mutex);\n+\t/* No crop or compose */\n+\n+\treturn 0;\n+}\n+#endif\n+\n+static const struct dev_pm_ops ov9281_pm_ops = {\n+\tSET_RUNTIME_PM_OPS(ov9281_runtime_suspend,\n+\t\t\t   ov9281_runtime_resume, NULL)\n+};\n+\n+#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API\n+static const struct v4l2_subdev_internal_ops ov9281_internal_ops = {\n+\t.open = ov9281_open,\n+};\n+#endif\n+\n+static const struct v4l2_subdev_core_ops ov9281_core_ops = {\n+\t.s_power = ov9281_s_power,\n+\t.ioctl = ov9281_ioctl,\n+#ifdef CONFIG_COMPAT\n+\t.compat_ioctl32 = ov9281_compat_ioctl32,\n+#endif\n+};\n+\n+static const struct v4l2_subdev_video_ops ov9281_video_ops = {\n+\t.s_stream = ov9281_s_stream,\n+\t.g_frame_interval = OV9281_g_frame_interval,\n+};\n+\n+static const struct v4l2_subdev_pad_ops ov9281_pad_ops = {\n+\t.enum_mbus_code = ov9281_enum_mbus_code,\n+\t.enum_frame_size = ov9281_enum_frame_sizes,\n+\t.get_fmt = ov9281_get_fmt,\n+\t.set_fmt = ov9281_set_fmt,\n+};\n+\n+static const struct v4l2_subdev_ops ov9281_subdev_ops = {\n+\t.core\t= &ov9281_core_ops,\n+\t.video\t= &ov9281_video_ops,\n+\t.pad\t= &ov9281_pad_ops,\n+};\n+\n+static int ov9281_set_ctrl(struct v4l2_ctrl *ctrl)\n+{\n+\tstruct ov9281 *ov9281 = container_of(ctrl->handler,\n+\t\t\t\t\t     struct ov9281, ctrl_handler);\n+\tstruct i2c_client *client = ov9281->client;\n+\ts64 max;\n+\tint ret = 0;\n+\n+\t/* Propagate change of current control to all related controls */\n+\tswitch (ctrl->id) {\n+\tcase V4L2_CID_VBLANK:\n+\t\t/* Update max exposure while meeting expected vblanking */\n+\t\tmax = ov9281->cur_mode->height + ctrl->val - 4;\n+\t\t__v4l2_ctrl_modify_range(ov9281->exposure,\n+\t\t\t\t\t ov9281->exposure->minimum, max,\n+\t\t\t\t\t ov9281->exposure->step,\n+\t\t\t\t\t ov9281->exposure->default_value);\n+\t\tbreak;\n+\t}\n+\n+\tif (pm_runtime_get(&client->dev) <= 0)\n+\t\treturn 0;\n+\n+\tswitch (ctrl->id) {\n+\tcase V4L2_CID_EXPOSURE:\n+\t\t/* 4 least significant bits of expsoure are fractional part */\n+\t\tret = ov9281_write_reg(ov9281->client, OV9281_REG_EXPOSURE,\n+\t\t\t\t       OV9281_REG_VALUE_24BIT, ctrl->val << 4);\n+\t\tbreak;\n+\tcase V4L2_CID_ANALOGUE_GAIN:\n+\t\tret = ov9281_write_reg(ov9281->client, OV9281_REG_GAIN_H,\n+\t\t\t\t       OV9281_REG_VALUE_08BIT,\n+\t\t\t\t       (ctrl->val >> OV9281_GAIN_H_SHIFT) & OV9281_GAIN_H_MASK);\n+\t\tret |= ov9281_write_reg(ov9281->client, OV9281_REG_GAIN_L,\n+\t\t\t\t       OV9281_REG_VALUE_08BIT,\n+\t\t\t\t       ctrl->val & OV9281_GAIN_L_MASK);\n+\t\tbreak;\n+\tcase V4L2_CID_VBLANK:\n+\t\tret = ov9281_write_reg(ov9281->client, OV9281_REG_VTS,\n+\t\t\t\t       OV9281_REG_VALUE_16BIT,\n+\t\t\t\t       ctrl->val + ov9281->cur_mode->height);\n+\t\tbreak;\n+\tcase V4L2_CID_TEST_PATTERN:\n+\t\tret = ov9281_enable_test_pattern(ov9281, ctrl->val);\n+\t\tbreak;\n+\tdefault:\n+\t\tdev_warn(&client->dev, \"%s Unhandled id:0x%x, val:0x%x\\n\",\n+\t\t\t __func__, ctrl->id, ctrl->val);\n+\t\tbreak;\n+\t}\n+\n+\tpm_runtime_put(&client->dev);\n+\n+\treturn ret;\n+}\n+\n+static const struct v4l2_ctrl_ops ov9281_ctrl_ops = {\n+\t.s_ctrl = ov9281_set_ctrl,\n+};\n+\n+static int ov9281_initialize_controls(struct ov9281 *ov9281)\n+{\n+\tconst struct ov9281_mode *mode;\n+\tstruct v4l2_ctrl_handler *handler;\n+\tstruct v4l2_ctrl *ctrl;\n+\ts64 exposure_max, vblank_def;\n+\tu32 h_blank;\n+\tint ret;\n+\n+\thandler = &ov9281->ctrl_handler;\n+\tmode = ov9281->cur_mode;\n+\tret = v4l2_ctrl_handler_init(handler, 8);\n+\tif (ret)\n+\t\treturn ret;\n+\thandler->lock = &ov9281->mutex;\n+\n+\tctrl = v4l2_ctrl_new_int_menu(handler, NULL, V4L2_CID_LINK_FREQ,\n+\t\t\t\t      0, 0, link_freq_menu_items);\n+\tif (ctrl)\n+\t\tctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY;\n+\n+\tv4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE,\n+\t\t\t  0, OV9281_PIXEL_RATE, 1, OV9281_PIXEL_RATE);\n+\n+\th_blank = mode->hts_def - mode->width;\n+\tov9281->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,\n+\t\t\t\th_blank, h_blank, 1, h_blank);\n+\tif (ov9281->hblank)\n+\t\tov9281->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;\n+\n+\tvblank_def = mode->vts_def - mode->height;\n+\tov9281->vblank = v4l2_ctrl_new_std(handler, &ov9281_ctrl_ops,\n+\t\t\t\tV4L2_CID_VBLANK, vblank_def,\n+\t\t\t\tOV9281_VTS_MAX - mode->height,\n+\t\t\t\t1, vblank_def);\n+\n+\texposure_max = mode->vts_def - 4;\n+\tov9281->exposure = v4l2_ctrl_new_std(handler, &ov9281_ctrl_ops,\n+\t\t\t\tV4L2_CID_EXPOSURE, OV9281_EXPOSURE_MIN,\n+\t\t\t\texposure_max, OV9281_EXPOSURE_STEP,\n+\t\t\t\tmode->exp_def);\n+\n+\tov9281->anal_gain = v4l2_ctrl_new_std(handler, &ov9281_ctrl_ops,\n+\t\t\t\tV4L2_CID_ANALOGUE_GAIN, OV9281_GAIN_MIN,\n+\t\t\t\tOV9281_GAIN_MAX, OV9281_GAIN_STEP,\n+\t\t\t\tOV9281_GAIN_DEFAULT);\n+\n+\tov9281->test_pattern = v4l2_ctrl_new_std_menu_items(handler,\n+\t\t\t\t&ov9281_ctrl_ops, V4L2_CID_TEST_PATTERN,\n+\t\t\t\tARRAY_SIZE(ov9281_test_pattern_menu) - 1,\n+\t\t\t\t0, 0, ov9281_test_pattern_menu);\n+\n+\tif (handler->error) {\n+\t\tret = handler->error;\n+\t\tdev_err(&ov9281->client->dev,\n+\t\t\t\"Failed to init controls(%d)\\n\", ret);\n+\t\tgoto err_free_handler;\n+\t}\n+\n+\tov9281->subdev.ctrl_handler = handler;\n+\n+\treturn 0;\n+\n+err_free_handler:\n+\tv4l2_ctrl_handler_free(handler);\n+\n+\treturn ret;\n+}\n+\n+static int ov9281_check_sensor_id(struct ov9281 *ov9281,\n+\t\t\t\t  struct i2c_client *client)\n+{\n+\tstruct device *dev = &ov9281->client->dev;\n+\tu32 id = 0;\n+\tint ret;\n+\n+\tret = ov9281_read_reg(client, OV9281_REG_CHIP_ID,\n+\t\t\t      OV9281_REG_VALUE_16BIT, &id);\n+\tif (id != CHIP_ID) {\n+\t\tdev_err(dev, \"Unexpected sensor id(%06x), ret(%d)\\n\", id, ret);\n+\t\treturn -ENODEV;\n+\t}\n+\n+\tdev_info(dev, \"Detected OV%06x sensor\\n\", CHIP_ID);\n+\n+\treturn 0;\n+}\n+\n+static int ov9281_configure_regulators(struct ov9281 *ov9281)\n+{\n+\tunsigned int i;\n+\n+\tfor (i = 0; i < OV9281_NUM_SUPPLIES; i++)\n+\t\tov9281->supplies[i].supply = ov9281_supply_names[i];\n+\n+\treturn devm_regulator_bulk_get(&ov9281->client->dev,\n+\t\t\t\t       OV9281_NUM_SUPPLIES,\n+\t\t\t\t       ov9281->supplies);\n+}\n+\n+static int ov9281_probe(struct i2c_client *client,\n+\t\t\tconst struct i2c_device_id *id)\n+{\n+\tstruct device *dev = &client->dev;\n+\tstruct device_node *node = dev->of_node;\n+\tstruct ov9281 *ov9281;\n+\tstruct v4l2_subdev *sd;\n+\tchar facing[2];\n+\tint ret;\n+\n+\tdev_info(dev, \"driver version: %02x.%02x.%02x\",\n+\t\tDRIVER_VERSION >> 16,\n+\t\t(DRIVER_VERSION & 0xff00) >> 8,\n+\t\tDRIVER_VERSION & 0x00ff);\n+\n+\tov9281 = devm_kzalloc(dev, sizeof(*ov9281), GFP_KERNEL);\n+\tif (!ov9281)\n+\t\treturn -ENOMEM;\n+\n+\tret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,\n+\t\t\t\t   &ov9281->module_index);\n+\tret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,\n+\t\t\t\t       &ov9281->module_facing);\n+\tret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,\n+\t\t\t\t       &ov9281->module_name);\n+\tret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,\n+\t\t\t\t       &ov9281->len_name);\n+\tif (ret) {\n+\t\tdev_err(dev, \"could not get module information!\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tov9281->client = client;\n+\tov9281->cur_mode = &supported_modes[0];\n+\n+\tov9281->xvclk = devm_clk_get(dev, \"xvclk\");\n+\tif (IS_ERR(ov9281->xvclk)) {\n+\t\tdev_err(dev, \"Failed to get xvclk\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\tret = clk_set_rate(ov9281->xvclk, OV9281_XVCLK_FREQ);\n+\tif (ret < 0) {\n+\t\tdev_err(dev, \"Failed to set xvclk rate (24MHz)\\n\");\n+\t\treturn ret;\n+\t}\n+\tif (clk_get_rate(ov9281->xvclk) != OV9281_XVCLK_FREQ)\n+\t\tdev_warn(dev, \"xvclk mismatched, modes are based on 24MHz\\n\");\n+\n+\tov9281->reset_gpio = devm_gpiod_get(dev, \"reset\", GPIOD_OUT_LOW);\n+\tif (IS_ERR(ov9281->reset_gpio))\n+\t\tdev_warn(dev, \"Failed to get reset-gpios\\n\");\n+\n+\tov9281->pwdn_gpio = devm_gpiod_get(dev, \"pwdn\", GPIOD_OUT_LOW);\n+\tif (IS_ERR(ov9281->pwdn_gpio))\n+\t\tdev_warn(dev, \"Failed to get pwdn-gpios\\n\");\n+\n+\tov9281->pinctrl = devm_pinctrl_get(dev);\n+\tif (!IS_ERR(ov9281->pinctrl)) {\n+\t\tov9281->pins_default =\n+\t\t\tpinctrl_lookup_state(ov9281->pinctrl,\n+\t\t\t\t\t     OF_CAMERA_PINCTRL_STATE_DEFAULT);\n+\t\tif (IS_ERR(ov9281->pins_default))\n+\t\t\tdev_err(dev, \"could not get default pinstate\\n\");\n+\n+\t\tov9281->pins_sleep =\n+\t\t\tpinctrl_lookup_state(ov9281->pinctrl,\n+\t\t\t\t\t     OF_CAMERA_PINCTRL_STATE_SLEEP);\n+\t\tif (IS_ERR(ov9281->pins_sleep))\n+\t\t\tdev_err(dev, \"could not get sleep pinstate\\n\");\n+\t} else {\n+\t\tdev_err(dev, \"no pinctrl\\n\");\n+\t}\n+\n+\tret = ov9281_configure_regulators(ov9281);\n+\tif (ret) {\n+\t\tdev_err(dev, \"Failed to get power regulators\\n\");\n+\t\treturn ret;\n+\t}\n+\n+\tmutex_init(&ov9281->mutex);\n+\n+\tsd = &ov9281->subdev;\n+\tv4l2_i2c_subdev_init(sd, client, &ov9281_subdev_ops);\n+\tret = ov9281_initialize_controls(ov9281);\n+\tif (ret)\n+\t\tgoto err_destroy_mutex;\n+\n+\tret = __ov9281_power_on(ov9281);\n+\tif (ret)\n+\t\tgoto err_free_handler;\n+\n+\tret = ov9281_check_sensor_id(ov9281, client);\n+\tif (ret)\n+\t\tgoto err_power_off;\n+\n+#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API\n+\tsd->internal_ops = &ov9281_internal_ops;\n+\tsd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;\n+#endif\n+#if defined(CONFIG_MEDIA_CONTROLLER)\n+\tov9281->pad.flags = MEDIA_PAD_FL_SOURCE;\n+\tsd->entity.type = MEDIA_ENT_T_V4L2_SUBDEV_SENSOR;\n+\tret = media_entity_init(&sd->entity, 1, &ov9281->pad, 0);\n+\tif (ret < 0)\n+\t\tgoto err_power_off;\n+#endif\n+\n+\tmemset(facing, 0, sizeof(facing));\n+\tif (strcmp(ov9281->module_facing, \"back\") == 0)\n+\t\tfacing[0] = 'b';\n+\telse\n+\t\tfacing[0] = 'f';\n+\n+\tsnprintf(sd->name, sizeof(sd->name), \"m%02d_%s_%s %s\",\n+\t\t ov9281->module_index, facing,\n+\t\t OV9281_NAME, dev_name(sd->dev));\n+\tret = v4l2_async_register_subdev_sensor_common(sd);\n+\tif (ret) {\n+\t\tdev_err(dev, \"v4l2 async register subdev failed\\n\");\n+\t\tgoto err_clean_entity;\n+\t}\n+\n+\tpm_runtime_set_active(dev);\n+\tpm_runtime_enable(dev);\n+\tpm_runtime_idle(dev);\n+\n+\treturn 0;\n+\n+err_clean_entity:\n+#if defined(CONFIG_MEDIA_CONTROLLER)\n+\tmedia_entity_cleanup(&sd->entity);\n+#endif\n+err_power_off:\n+\t__ov9281_power_off(ov9281);\n+err_free_handler:\n+\tv4l2_ctrl_handler_free(&ov9281->ctrl_handler);\n+err_destroy_mutex:\n+\tmutex_destroy(&ov9281->mutex);\n+\n+\treturn ret;\n+}\n+\n+static int ov9281_remove(struct i2c_client *client)\n+{\n+\tstruct v4l2_subdev *sd = i2c_get_clientdata(client);\n+\tstruct ov9281 *ov9281 = to_ov9281(sd);\n+\n+\tv4l2_async_unregister_subdev(sd);\n+#if defined(CONFIG_MEDIA_CONTROLLER)\n+\tmedia_entity_cleanup(&sd->entity);\n+#endif\n+\tv4l2_ctrl_handler_free(&ov9281->ctrl_handler);\n+\tmutex_destroy(&ov9281->mutex);\n+\n+\tpm_runtime_disable(&client->dev);\n+\tif (!pm_runtime_status_suspended(&client->dev))\n+\t\t__ov9281_power_off(ov9281);\n+\tpm_runtime_set_suspended(&client->dev);\n+\n+\treturn 0;\n+}\n+\n+#if IS_ENABLED(CONFIG_OF)\n+static const struct of_device_id ov9281_of_match[] = {\n+\t{ .compatible = \"ovti,ov9281\" },\n+\t{},\n+};\n+MODULE_DEVICE_TABLE(of, ov9281_of_match);\n+#endif\n+\n+static const struct i2c_device_id ov9281_match_id[] = {\n+\t{ \"ovti,ov9281\", 0 },\n+\t{ },\n+};\n+\n+static struct i2c_driver ov9281_i2c_driver = {\n+\t.driver = {\n+\t\t.name = OV9281_NAME,\n+\t\t.pm = &ov9281_pm_ops,\n+\t\t.of_match_table = of_match_ptr(ov9281_of_match),\n+\t},\n+\t.probe\t\t= &ov9281_probe,\n+\t.remove\t\t= &ov9281_remove,\n+\t.id_table\t= ov9281_match_id,\n+};\n+\n+static int __init sensor_mod_init(void)\n+{\n+\treturn i2c_add_driver(&ov9281_i2c_driver);\n+}\n+\n+static void __exit sensor_mod_exit(void)\n+{\n+\ti2c_del_driver(&ov9281_i2c_driver);\n+}\n+\n+device_initcall_sync(sensor_mod_init);\n+module_exit(sensor_mod_exit);\n+\n+MODULE_DESCRIPTION(\"OmniVision ov9281 sensor driver\");\n+MODULE_LICENSE(\"GPL v2\");\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0285-media-i2c-ov9281-fix-mclk-issue-when-probe-multiple-.patch",
    "content": "From ecaf713a6535e49f1eb4374f6241421e8e61d407 Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Tue, 14 Apr 2020 15:47:09 +0100\nSubject: [PATCH] media: i2c: ov9281: fix mclk issue when probe\n multiple camera.\n\nTakes the ov9281 part only from the Rockchip's patch.\n\nChange-Id: I30e833baf2c1bb07d6d87ddb3b00759ab45a90e4\nSigned-off-by: Zefa Chen <zefa.chen@rock-chips.com>\n---\n drivers/media/i2c/ov9281.c | 16 ++++++++--------\n 1 file changed, 8 insertions(+), 8 deletions(-)\n\n--- a/drivers/media/i2c/ov9281.c\n+++ b/drivers/media/i2c/ov9281.c\n@@ -3,6 +3,7 @@\n  * ov9281 driver\n  *\n  * Copyright (C) 2017 Fuzhou Rockchip Electronics Co., Ltd.\n+ * V0.0X01.0X02 fix mclk issue when probe multiple camera.\n  */\n \n #include <linux/clk.h>\n@@ -22,7 +23,7 @@\n #include <media/v4l2-subdev.h>\n #include <linux/pinctrl/consumer.h>\n \n-#define DRIVER_VERSION\t\t\tKERNEL_VERSION(0, 0x01, 0x0)\n+#define DRIVER_VERSION\t\t\tKERNEL_VERSION(0, 0x01, 0x2)\n \n #ifndef V4L2_CID_DIGITAL_GAIN\n #define V4L2_CID_DIGITAL_GAIN\t\tV4L2_CID_GAIN\n@@ -676,6 +677,12 @@ static int __ov9281_power_on(struct ov92\n \t\t\tdev_err(dev, \"could not set pins\\n\");\n \t}\n \n+\tret = clk_set_rate(ov9281->xvclk, OV9281_XVCLK_FREQ);\n+\tif (ret < 0)\n+\t\tdev_warn(dev, \"Failed to set xvclk rate (24MHz)\\n\");\n+\tif (clk_get_rate(ov9281->xvclk) != OV9281_XVCLK_FREQ)\n+\t\tdev_warn(dev, \"xvclk mismatched, modes are based on 24MHz\\n\");\n+\n \tret = clk_prepare_enable(ov9281->xvclk);\n \tif (ret < 0) {\n \t\tdev_err(dev, \"Failed to enable xvclk\\n\");\n@@ -1008,13 +1015,6 @@ static int ov9281_probe(struct i2c_clien\n \t\tdev_err(dev, \"Failed to get xvclk\\n\");\n \t\treturn -EINVAL;\n \t}\n-\tret = clk_set_rate(ov9281->xvclk, OV9281_XVCLK_FREQ);\n-\tif (ret < 0) {\n-\t\tdev_err(dev, \"Failed to set xvclk rate (24MHz)\\n\");\n-\t\treturn ret;\n-\t}\n-\tif (clk_get_rate(ov9281->xvclk) != OV9281_XVCLK_FREQ)\n-\t\tdev_warn(dev, \"xvclk mismatched, modes are based on 24MHz\\n\");\n \n \tov9281->reset_gpio = devm_gpiod_get(dev, \"reset\", GPIOD_OUT_LOW);\n \tif (IS_ERR(ov9281->reset_gpio))\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0286-media-i2c-ov9281-add-enum_frame_interval-function-fo.patch",
    "content": "From ffb4500f4c368183fb71ce20698eb4bd25bc0ed7 Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Tue, 14 Apr 2020 15:51:50 +0100\nSubject: [PATCH] media: i2c: ov9281: add enum_frame_interval function\n for iq tool 2.2 and hal3\n\nAdds the ov9281 parts of the Rockchip patch adding enum_frame_interval to\na large number of drivers.\n\nChange-Id: I03344cd6cf278dd7c18fce8e97479089ef185a5c\nSigned-off-by: Zefa Chen <zefa.chen@rock-chips.com>\n---\n drivers/media/i2c/ov9281.c | 31 ++++++++++++++++++++++++++-----\n 1 file changed, 26 insertions(+), 5 deletions(-)\n\n--- a/drivers/media/i2c/ov9281.c\n+++ b/drivers/media/i2c/ov9281.c\n@@ -4,6 +4,7 @@\n  *\n  * Copyright (C) 2017 Fuzhou Rockchip Electronics Co., Ltd.\n  * V0.0X01.0X02 fix mclk issue when probe multiple camera.\n+ * V0.0X01.0X03 add enum_frame_interval function.\n  */\n \n #include <linux/clk.h>\n@@ -23,7 +24,7 @@\n #include <media/v4l2-subdev.h>\n #include <linux/pinctrl/consumer.h>\n \n-#define DRIVER_VERSION\t\t\tKERNEL_VERSION(0, 0x01, 0x2)\n+#define DRIVER_VERSION\t\t\tKERNEL_VERSION(0, 0x01, 0x3)\n \n #ifndef V4L2_CID_DIGITAL_GAIN\n #define V4L2_CID_DIGITAL_GAIN\t\tV4L2_CID_GAIN\n@@ -92,7 +93,7 @@ struct regval {\n struct ov9281_mode {\n \tu32 width;\n \tu32 height;\n-\tu32 max_fps;\n+\tstruct v4l2_fract max_fps;\n \tu32 hts_def;\n \tu32 vts_def;\n \tu32 exp_def;\n@@ -246,7 +247,10 @@ static const struct ov9281_mode supporte\n \t{\n \t\t.width = 1280,\n \t\t.height = 800,\n-\t\t.max_fps = 120,\n+\t\t.max_fps = {\n+\t\t\t.numerator = 10000,\n+\t\t\t.denominator = 1200000,\n+\t\t},\n \t\t.exp_def = 0x0320,\n \t\t.hts_def = 0x0b60,//0x2d8*4\n \t\t.vts_def = 0x038e,\n@@ -483,8 +487,7 @@ static int OV9281_g_frame_interval(struc\n \tconst struct ov9281_mode *mode = ov9281->cur_mode;\n \n \tmutex_lock(&ov9281->mutex);\n-\tfi->interval.numerator = 10000;\n-\tfi->interval.denominator = mode->max_fps * 10000;\n+\tfi->interval = mode->max_fps;\n \tmutex_unlock(&ov9281->mutex);\n \n \treturn 0;\n@@ -778,6 +781,23 @@ static int ov9281_open(struct v4l2_subde\n }\n #endif\n \n+static int\n+ov9281_enum_frame_interval(struct v4l2_subdev *sd,\n+\t\t\t   struct v4l2_subdev_pad_config *cfg,\n+\t\t\t   struct v4l2_subdev_frame_interval_enum *fie)\n+{\n+\tif (fie->index >= ARRAY_SIZE(supported_modes))\n+\t\treturn -EINVAL;\n+\n+\tif (fie->code != MEDIA_BUS_FMT_Y10_1X10)\n+\t\treturn -EINVAL;\n+\n+\tfie->width = supported_modes[fie->index].width;\n+\tfie->height = supported_modes[fie->index].height;\n+\tfie->interval = supported_modes[fie->index].max_fps;\n+\treturn 0;\n+}\n+\n static const struct dev_pm_ops ov9281_pm_ops = {\n \tSET_RUNTIME_PM_OPS(ov9281_runtime_suspend,\n \t\t\t   ov9281_runtime_resume, NULL)\n@@ -805,6 +825,7 @@ static const struct v4l2_subdev_video_op\n static const struct v4l2_subdev_pad_ops ov9281_pad_ops = {\n \t.enum_mbus_code = ov9281_enum_mbus_code,\n \t.enum_frame_size = ov9281_enum_frame_sizes,\n+\t.enum_frame_interval = ov9281_enum_frame_interval,\n \t.get_fmt = ov9281_get_fmt,\n \t.set_fmt = ov9281_set_fmt,\n };\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0287-media-i2c-ov9281-Fixup-for-recent-kernel-releases-an.patch",
    "content": "From a73ced40f7ca1b0735e5d0d1c45087e02023a618 Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Tue, 14 Apr 2020 16:12:33 +0100\nSubject: [PATCH] media: i2c: ov9281: Fixup for recent kernel releases,\n and remove custom code\n\nThe Rockchip driver was based on a 4.4 kernel, and had several custom\nRockchip parts.\n\nUpdate to 5.4 kernel APIs, with the relevant controls required by\nlibcamera, and remove custom Rockchip parts.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n drivers/media/i2c/ov9281.c | 361 +++++++++++++------------------------\n 1 file changed, 122 insertions(+), 239 deletions(-)\n\n--- a/drivers/media/i2c/ov9281.c\n+++ b/drivers/media/i2c/ov9281.c\n@@ -1,6 +1,11 @@\n // SPDX-License-Identifier: GPL-2.0\n /*\n- * ov9281 driver\n+ * Omnivision OV9281 1280x800 global shutter image sensor driver\n+ *\n+ * This driver has been taken from\n+ * https://github.com/rockchip-linux/kernel/blob/develop-4.4/drivers/media/i2c/ov9281.c\n+ * cleaned up, made to compile against mainline kernels instead of the Rockchip\n+ * vendor kernel, and the relevant controls added to work with libcamera.\n  *\n  * Copyright (C) 2017 Fuzhou Rockchip Electronics Co., Ltd.\n  * V0.0X01.0X02 fix mclk issue when probe multiple camera.\n@@ -17,22 +22,18 @@\n #include <linux/regulator/consumer.h>\n #include <linux/sysfs.h>\n #include <linux/slab.h>\n-#include <linux/rk-camera-module.h>\n #include <media/media-entity.h>\n #include <media/v4l2-async.h>\n #include <media/v4l2-ctrls.h>\n #include <media/v4l2-subdev.h>\n-#include <linux/pinctrl/consumer.h>\n-\n-#define DRIVER_VERSION\t\t\tKERNEL_VERSION(0, 0x01, 0x3)\n-\n-#ifndef V4L2_CID_DIGITAL_GAIN\n-#define V4L2_CID_DIGITAL_GAIN\t\tV4L2_CID_GAIN\n-#endif\n \n #define OV9281_LINK_FREQ_400MHZ\t\t400000000\n+#define OV9281_LANES\t\t\t2\n+#define OV9281_BITS_PER_SAMPLE\t\t10\n+\n /* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */\n-#define OV9281_PIXEL_RATE\t\t(OV9281_LINK_FREQ_400MHZ * 2 * 2 / 10)\n+#define OV9281_PIXEL_RATE\t\t(OV9281_LINK_FREQ_400MHZ * 2 * \\\n+\t\t\t\t\t OV9281_LANES / OV9281_BITS_PER_SAMPLE)\n #define OV9281_XVCLK_FREQ\t\t24000000\n \n #define CHIP_ID\t\t\t\t0x9281\n@@ -63,18 +64,24 @@\n \n #define OV9281_REG_VTS\t\t\t0x380e\n \n+/*\n+ * OV9281 native and active pixel array size.\n+ * Datasheet not available to confirm these values, so assume there are no\n+ * border pixels.\n+ */\n+#define OV9281_NATIVE_WIDTH\t\t1280U\n+#define OV9281_NATIVE_HEIGHT\t\t800U\n+#define OV9281_PIXEL_ARRAY_LEFT\t\t0U\n+#define OV9281_PIXEL_ARRAY_TOP\t\t0U\n+#define OV9281_PIXEL_ARRAY_WIDTH\t1280U\n+#define OV9281_PIXEL_ARRAY_HEIGHT\t800U\n+\n #define REG_NULL\t\t\t0xFFFF\n \n #define OV9281_REG_VALUE_08BIT\t\t1\n #define OV9281_REG_VALUE_16BIT\t\t2\n #define OV9281_REG_VALUE_24BIT\t\t3\n \n-#define OV9281_LANES\t\t\t2\n-#define OV9281_BITS_PER_SAMPLE\t\t10\n-\n-#define OF_CAMERA_PINCTRL_STATE_DEFAULT\t\"rockchip,camera_default\"\n-#define OF_CAMERA_PINCTRL_STATE_SLEEP\t\"rockchip,camera_sleep\"\n-\n #define OV9281_NAME\t\t\t\"ov9281\"\n \n static const char * const ov9281_supply_names[] = {\n@@ -93,10 +100,10 @@ struct regval {\n struct ov9281_mode {\n \tu32 width;\n \tu32 height;\n-\tstruct v4l2_fract max_fps;\n \tu32 hts_def;\n \tu32 vts_def;\n \tu32 exp_def;\n+\tstruct v4l2_rect crop;\n \tconst struct regval *reg_list;\n };\n \n@@ -107,10 +114,6 @@ struct ov9281 {\n \tstruct gpio_desc\t*pwdn_gpio;\n \tstruct regulator_bulk_data supplies[OV9281_NUM_SUPPLIES];\n \n-\tstruct pinctrl\t\t*pinctrl;\n-\tstruct pinctrl_state\t*pins_default;\n-\tstruct pinctrl_state\t*pins_sleep;\n-\n \tstruct v4l2_subdev\tsubdev;\n \tstruct media_pad\tpad;\n \tstruct v4l2_ctrl_handler ctrl_handler;\n@@ -124,23 +127,12 @@ struct ov9281 {\n \tbool\t\t\tstreaming;\n \tbool\t\t\tpower_on;\n \tconst struct ov9281_mode *cur_mode;\n-\tu32\t\t\tmodule_index;\n-\tconst char\t\t*module_facing;\n-\tconst char\t\t*module_name;\n-\tconst char\t\t*len_name;\n };\n \n #define to_ov9281(sd) container_of(sd, struct ov9281, subdev)\n \n /*\n  * Xclk 24Mhz\n- */\n-static const struct regval ov9281_global_regs[] = {\n-\t{REG_NULL, 0x00},\n-};\n-\n-/*\n- * Xclk 24Mhz\n  * max_framerate 120fps\n  * mipi_datarate per lane 800Mbps\n  */\n@@ -247,13 +239,15 @@ static const struct ov9281_mode supporte\n \t{\n \t\t.width = 1280,\n \t\t.height = 800,\n-\t\t.max_fps = {\n-\t\t\t.numerator = 10000,\n-\t\t\t.denominator = 1200000,\n-\t\t},\n \t\t.exp_def = 0x0320,\n-\t\t.hts_def = 0x0b60,//0x2d8*4\n+\t\t.hts_def = 0x05b0,\t/* 0x2d8*2 */\n \t\t.vts_def = 0x038e,\n+\t\t.crop = {\n+\t\t\t.left = 0,\n+\t\t\t.top = 0,\n+\t\t\t.width = 1280,\n+\t\t\t.height = 800\n+\t\t},\n \t\t.reg_list = ov9281_1280x800_regs,\n \t},\n };\n@@ -389,22 +383,28 @@ static int ov9281_set_fmt(struct v4l2_su\n \tfmt->format.width = mode->width;\n \tfmt->format.height = mode->height;\n \tfmt->format.field = V4L2_FIELD_NONE;\n+\tfmt->format.colorspace = V4L2_COLORSPACE_SRGB;\n+\tfmt->format.ycbcr_enc =\n+\t\t\tV4L2_MAP_YCBCR_ENC_DEFAULT(fmt->format.colorspace);\n+\tfmt->format.quantization =\n+\t\tV4L2_MAP_QUANTIZATION_DEFAULT(true, fmt->format.colorspace,\n+\t\t\t\t\t      fmt->format.ycbcr_enc);\n+\tfmt->format.xfer_func =\n+\t\tV4L2_MAP_XFER_FUNC_DEFAULT(fmt->format.colorspace);\n+\n \tif (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {\n-#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API\n \t\t*v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;\n-#else\n-\t\tmutex_unlock(&ov9281->mutex);\n-\t\treturn -ENOTTY;\n-#endif\n \t} else {\n \t\tov9281->cur_mode = mode;\n \t\th_blank = mode->hts_def - mode->width;\n \t\t__v4l2_ctrl_modify_range(ov9281->hblank, h_blank,\n \t\t\t\t\t h_blank, 1, h_blank);\n+\t\t__v4l2_ctrl_s_ctrl(ov9281->hblank, h_blank);\n \t\tvblank_def = mode->vts_def - mode->height;\n \t\t__v4l2_ctrl_modify_range(ov9281->vblank, vblank_def,\n \t\t\t\t\t OV9281_VTS_MAX - mode->height,\n \t\t\t\t\t 1, vblank_def);\n+\t\t__v4l2_ctrl_s_ctrl(ov9281->vblank, vblank_def);\n \t}\n \n \tmutex_unlock(&ov9281->mutex);\n@@ -421,17 +421,21 @@ static int ov9281_get_fmt(struct v4l2_su\n \n \tmutex_lock(&ov9281->mutex);\n \tif (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {\n-#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API\n \t\tfmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);\n-#else\n-\t\tmutex_unlock(&ov9281->mutex);\n-\t\treturn -ENOTTY;\n-#endif\n \t} else {\n \t\tfmt->format.width = mode->width;\n \t\tfmt->format.height = mode->height;\n \t\tfmt->format.code = MEDIA_BUS_FMT_Y10_1X10;\n \t\tfmt->format.field = V4L2_FIELD_NONE;\n+\t\tfmt->format.colorspace = V4L2_COLORSPACE_SRGB;\n+\t\tfmt->format.ycbcr_enc =\n+\t\t\tV4L2_MAP_YCBCR_ENC_DEFAULT(fmt->format.colorspace);\n+\t\tfmt->format.quantization =\n+\t\t\tV4L2_MAP_QUANTIZATION_DEFAULT(true,\n+\t\t\t\t\t\t      fmt->format.colorspace,\n+\t\t\t\t\t\t      fmt->format.ycbcr_enc);\n+\t\tfmt->format.xfer_func =\n+\t\t\tV4L2_MAP_XFER_FUNC_DEFAULT(fmt->format.colorspace);\n \t}\n \tmutex_unlock(&ov9281->mutex);\n \n@@ -442,7 +446,7 @@ static int ov9281_enum_mbus_code(struct\n \t\t\t\t struct v4l2_subdev_pad_config *cfg,\n \t\t\t\t struct v4l2_subdev_mbus_code_enum *code)\n {\n-\tif (code->index != 0)\n+\tif (code->index)\n \t\treturn -EINVAL;\n \tcode->code = MEDIA_BUS_FMT_Y10_1X10;\n \n@@ -480,88 +484,56 @@ static int ov9281_enable_test_pattern(st\n \t\t\t\tOV9281_REG_VALUE_08BIT, val);\n }\n \n-static int OV9281_g_frame_interval(struct v4l2_subdev *sd,\n-\t\t\t\t   struct v4l2_subdev_frame_interval *fi)\n-{\n-\tstruct ov9281 *ov9281 = to_ov9281(sd);\n-\tconst struct ov9281_mode *mode = ov9281->cur_mode;\n-\n-\tmutex_lock(&ov9281->mutex);\n-\tfi->interval = mode->max_fps;\n-\tmutex_unlock(&ov9281->mutex);\n+static const struct v4l2_rect *\n+__ov9281_get_pad_crop(struct ov9281 *ov9281, struct v4l2_subdev_pad_config *cfg,\n+\t\t      unsigned int pad, enum v4l2_subdev_format_whence which)\n+{\n+\tswitch (which) {\n+\tcase V4L2_SUBDEV_FORMAT_TRY:\n+\t\treturn v4l2_subdev_get_try_crop(&ov9281->subdev, cfg, pad);\n+\tcase V4L2_SUBDEV_FORMAT_ACTIVE:\n+\t\treturn &ov9281->cur_mode->crop;\n+\t}\n \n-\treturn 0;\n+\treturn NULL;\n }\n \n-static void ov9281_get_module_inf(struct ov9281 *ov9281,\n-\t\t\t\t  struct rkmodule_inf *inf)\n+static int ov9281_get_selection(struct v4l2_subdev *sd,\n+\t\t\t\tstruct v4l2_subdev_pad_config *cfg,\n+\t\t\t\tstruct v4l2_subdev_selection *sel)\n {\n-\tmemset(inf, 0, sizeof(*inf));\n-\tstrlcpy(inf->base.sensor, OV9281_NAME, sizeof(inf->base.sensor));\n-\tstrlcpy(inf->base.module, ov9281->module_name,\n-\t\tsizeof(inf->base.module));\n-\tstrlcpy(inf->base.lens, ov9281->len_name, sizeof(inf->base.lens));\n-}\n+\tswitch (sel->target) {\n+\tcase V4L2_SEL_TGT_CROP: {\n+\t\tstruct ov9281 *ov9281 = to_ov9281(sd);\n \n-static long ov9281_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)\n-{\n-\tstruct ov9281 *ov9281 = to_ov9281(sd);\n-\tlong ret = 0;\n+\t\tmutex_lock(&ov9281->mutex);\n+\t\tsel->r = *__ov9281_get_pad_crop(ov9281, cfg, sel->pad,\n+\t\t\t\t\t\tsel->which);\n+\t\tmutex_unlock(&ov9281->mutex);\n \n-\tswitch (cmd) {\n-\tcase RKMODULE_GET_MODULE_INFO:\n-\t\tov9281_get_module_inf(ov9281, (struct rkmodule_inf *)arg);\n-\t\tbreak;\n-\tdefault:\n-\t\tret = -ENOIOCTLCMD;\n-\t\tbreak;\n+\t\treturn 0;\n \t}\n \n-\treturn ret;\n-}\n+\tcase V4L2_SEL_TGT_NATIVE_SIZE:\n+\t\tsel->r.top = 0;\n+\t\tsel->r.left = 0;\n+\t\tsel->r.width = OV9281_NATIVE_WIDTH;\n+\t\tsel->r.height = OV9281_NATIVE_HEIGHT;\n \n-#ifdef CONFIG_COMPAT\n-static long ov9281_compat_ioctl32(struct v4l2_subdev *sd,\n-\t\t\t\t  unsigned int cmd, unsigned long arg)\n-{\n-\tvoid __user *up = compat_ptr(arg);\n-\tstruct rkmodule_inf *inf;\n-\tstruct rkmodule_awb_cfg *cfg;\n-\tlong ret;\n-\n-\tswitch (cmd) {\n-\tcase RKMODULE_GET_MODULE_INFO:\n-\t\tinf = kzalloc(sizeof(*inf), GFP_KERNEL);\n-\t\tif (!inf) {\n-\t\t\tret = -ENOMEM;\n-\t\t\treturn ret;\n-\t\t}\n+\t\treturn 0;\n \n-\t\tret = ov9281_ioctl(sd, cmd, inf);\n-\t\tif (!ret)\n-\t\t\tret = copy_to_user(up, inf, sizeof(*inf));\n-\t\tkfree(inf);\n-\t\tbreak;\n-\tcase RKMODULE_AWB_CFG:\n-\t\tcfg = kzalloc(sizeof(*cfg), GFP_KERNEL);\n-\t\tif (!cfg) {\n-\t\t\tret = -ENOMEM;\n-\t\t\treturn ret;\n-\t\t}\n+\tcase V4L2_SEL_TGT_CROP_DEFAULT:\n+\tcase V4L2_SEL_TGT_CROP_BOUNDS:\n+\t\tsel->r.top = OV9281_PIXEL_ARRAY_TOP;\n+\t\tsel->r.left = OV9281_PIXEL_ARRAY_LEFT;\n+\t\tsel->r.width = OV9281_PIXEL_ARRAY_WIDTH;\n+\t\tsel->r.height = OV9281_PIXEL_ARRAY_HEIGHT;\n \n-\t\tret = copy_from_user(cfg, up, sizeof(*cfg));\n-\t\tif (!ret)\n-\t\t\tret = ov9281_ioctl(sd, cmd, cfg);\n-\t\tkfree(cfg);\n-\t\tbreak;\n-\tdefault:\n-\t\tret = -ENOIOCTLCMD;\n-\t\tbreak;\n+\t\treturn 0;\n \t}\n \n-\treturn ret;\n+\treturn -EINVAL;\n }\n-#endif\n \n static int __ov9281_start_stream(struct ov9281 *ov9281)\n {\n@@ -643,12 +615,6 @@ static int ov9281_s_power(struct v4l2_su\n \t\t\tpm_runtime_put_noidle(&client->dev);\n \t\t\tgoto unlock_and_return;\n \t\t}\n-\t\tret = ov9281_write_array(ov9281->client, ov9281_global_regs);\n-\t\tif (ret) {\n-\t\t\tv4l2_err(sd, \"could not set init registers\\n\");\n-\t\t\tpm_runtime_put_noidle(&client->dev);\n-\t\t\tgoto unlock_and_return;\n-\t\t}\n \t\tov9281->power_on = true;\n \t} else {\n \t\tpm_runtime_put(&client->dev);\n@@ -673,18 +639,12 @@ static int __ov9281_power_on(struct ov92\n \tu32 delay_us;\n \tstruct device *dev = &ov9281->client->dev;\n \n-\tif (!IS_ERR_OR_NULL(ov9281->pins_default)) {\n-\t\tret = pinctrl_select_state(ov9281->pinctrl,\n-\t\t\t\t\t   ov9281->pins_default);\n-\t\tif (ret < 0)\n-\t\t\tdev_err(dev, \"could not set pins\\n\");\n-\t}\n-\n \tret = clk_set_rate(ov9281->xvclk, OV9281_XVCLK_FREQ);\n \tif (ret < 0)\n \t\tdev_warn(dev, \"Failed to set xvclk rate (24MHz)\\n\");\n \tif (clk_get_rate(ov9281->xvclk) != OV9281_XVCLK_FREQ)\n-\t\tdev_warn(dev, \"xvclk mismatched, modes are based on 24MHz\\n\");\n+\t\tdev_warn(dev, \"xvclk mismatched, modes are based on 24MHz - rate is %lu\\n\",\n+\t\t\t clk_get_rate(ov9281->xvclk));\n \n \tret = clk_prepare_enable(ov9281->xvclk);\n \tif (ret < 0) {\n@@ -722,20 +682,11 @@ disable_clk:\n \n static void __ov9281_power_off(struct ov9281 *ov9281)\n {\n-\tint ret;\n-\tstruct device *dev = &ov9281->client->dev;\n-\n \tif (!IS_ERR(ov9281->pwdn_gpio))\n \t\tgpiod_set_value_cansleep(ov9281->pwdn_gpio, 0);\n \tclk_disable_unprepare(ov9281->xvclk);\n \tif (!IS_ERR(ov9281->reset_gpio))\n \t\tgpiod_set_value_cansleep(ov9281->reset_gpio, 0);\n-\tif (!IS_ERR_OR_NULL(ov9281->pins_sleep)) {\n-\t\tret = pinctrl_select_state(ov9281->pinctrl,\n-\t\t\t\t\t   ov9281->pins_sleep);\n-\t\tif (ret < 0)\n-\t\t\tdev_dbg(dev, \"could not set pins\\n\");\n-\t}\n \tregulator_bulk_disable(OV9281_NUM_SUPPLIES, ov9281->supplies);\n }\n \n@@ -759,7 +710,6 @@ static int ov9281_runtime_suspend(struct\n \treturn 0;\n }\n \n-#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API\n static int ov9281_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)\n {\n \tstruct ov9281 *ov9281 = to_ov9281(sd);\n@@ -773,61 +723,42 @@ static int ov9281_open(struct v4l2_subde\n \ttry_fmt->height = def_mode->height;\n \ttry_fmt->code = MEDIA_BUS_FMT_Y10_1X10;\n \ttry_fmt->field = V4L2_FIELD_NONE;\n+\ttry_fmt->colorspace = V4L2_COLORSPACE_SRGB;\n+\ttry_fmt->ycbcr_enc = V4L2_MAP_YCBCR_ENC_DEFAULT(try_fmt->colorspace);\n+\ttry_fmt->quantization =\n+\t\tV4L2_MAP_QUANTIZATION_DEFAULT(true, try_fmt->colorspace,\n+\t\t\t\t\t      try_fmt->ycbcr_enc);\n+\ttry_fmt->xfer_func = V4L2_MAP_XFER_FUNC_DEFAULT(try_fmt->colorspace);\n \n \tmutex_unlock(&ov9281->mutex);\n \t/* No crop or compose */\n \n \treturn 0;\n }\n-#endif\n-\n-static int\n-ov9281_enum_frame_interval(struct v4l2_subdev *sd,\n-\t\t\t   struct v4l2_subdev_pad_config *cfg,\n-\t\t\t   struct v4l2_subdev_frame_interval_enum *fie)\n-{\n-\tif (fie->index >= ARRAY_SIZE(supported_modes))\n-\t\treturn -EINVAL;\n-\n-\tif (fie->code != MEDIA_BUS_FMT_Y10_1X10)\n-\t\treturn -EINVAL;\n-\n-\tfie->width = supported_modes[fie->index].width;\n-\tfie->height = supported_modes[fie->index].height;\n-\tfie->interval = supported_modes[fie->index].max_fps;\n-\treturn 0;\n-}\n \n static const struct dev_pm_ops ov9281_pm_ops = {\n \tSET_RUNTIME_PM_OPS(ov9281_runtime_suspend,\n \t\t\t   ov9281_runtime_resume, NULL)\n };\n \n-#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API\n static const struct v4l2_subdev_internal_ops ov9281_internal_ops = {\n \t.open = ov9281_open,\n };\n-#endif\n \n static const struct v4l2_subdev_core_ops ov9281_core_ops = {\n \t.s_power = ov9281_s_power,\n-\t.ioctl = ov9281_ioctl,\n-#ifdef CONFIG_COMPAT\n-\t.compat_ioctl32 = ov9281_compat_ioctl32,\n-#endif\n };\n \n static const struct v4l2_subdev_video_ops ov9281_video_ops = {\n \t.s_stream = ov9281_s_stream,\n-\t.g_frame_interval = OV9281_g_frame_interval,\n };\n \n static const struct v4l2_subdev_pad_ops ov9281_pad_ops = {\n \t.enum_mbus_code = ov9281_enum_mbus_code,\n \t.enum_frame_size = ov9281_enum_frame_sizes,\n-\t.enum_frame_interval = ov9281_enum_frame_interval,\n \t.get_fmt = ov9281_get_fmt,\n \t.set_fmt = ov9281_set_fmt,\n+\t.get_selection = ov9281_get_selection,\n };\n \n static const struct v4l2_subdev_ops ov9281_subdev_ops = {\n@@ -868,7 +799,8 @@ static int ov9281_set_ctrl(struct v4l2_c\n \tcase V4L2_CID_ANALOGUE_GAIN:\n \t\tret = ov9281_write_reg(ov9281->client, OV9281_REG_GAIN_H,\n \t\t\t\t       OV9281_REG_VALUE_08BIT,\n-\t\t\t\t       (ctrl->val >> OV9281_GAIN_H_SHIFT) & OV9281_GAIN_H_MASK);\n+\t\t\t\t       (ctrl->val >> OV9281_GAIN_H_SHIFT) &\n+\t\t\t\t\t\t\tOV9281_GAIN_H_MASK);\n \t\tret |= ov9281_write_reg(ov9281->client, OV9281_REG_GAIN_L,\n \t\t\t\t       OV9281_REG_VALUE_08BIT,\n \t\t\t\t       ctrl->val & OV9281_GAIN_L_MASK);\n@@ -922,31 +854,34 @@ static int ov9281_initialize_controls(st\n \n \th_blank = mode->hts_def - mode->width;\n \tov9281->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,\n-\t\t\t\th_blank, h_blank, 1, h_blank);\n+\t\t\t\t\t   h_blank, h_blank, 1, h_blank);\n \tif (ov9281->hblank)\n \t\tov9281->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;\n \n \tvblank_def = mode->vts_def - mode->height;\n \tov9281->vblank = v4l2_ctrl_new_std(handler, &ov9281_ctrl_ops,\n-\t\t\t\tV4L2_CID_VBLANK, vblank_def,\n-\t\t\t\tOV9281_VTS_MAX - mode->height,\n-\t\t\t\t1, vblank_def);\n+\t\t\t\t\t   V4L2_CID_VBLANK, vblank_def,\n+\t\t\t\t\t   OV9281_VTS_MAX - mode->height, 1,\n+\t\t\t\t\t   vblank_def);\n \n \texposure_max = mode->vts_def - 4;\n \tov9281->exposure = v4l2_ctrl_new_std(handler, &ov9281_ctrl_ops,\n-\t\t\t\tV4L2_CID_EXPOSURE, OV9281_EXPOSURE_MIN,\n-\t\t\t\texposure_max, OV9281_EXPOSURE_STEP,\n-\t\t\t\tmode->exp_def);\n+\t\t\t\t\t     V4L2_CID_EXPOSURE,\n+\t\t\t\t\t     OV9281_EXPOSURE_MIN, exposure_max,\n+\t\t\t\t\t     OV9281_EXPOSURE_STEP,\n+\t\t\t\t\t     mode->exp_def);\n \n \tov9281->anal_gain = v4l2_ctrl_new_std(handler, &ov9281_ctrl_ops,\n-\t\t\t\tV4L2_CID_ANALOGUE_GAIN, OV9281_GAIN_MIN,\n-\t\t\t\tOV9281_GAIN_MAX, OV9281_GAIN_STEP,\n-\t\t\t\tOV9281_GAIN_DEFAULT);\n-\n-\tov9281->test_pattern = v4l2_ctrl_new_std_menu_items(handler,\n-\t\t\t\t&ov9281_ctrl_ops, V4L2_CID_TEST_PATTERN,\n-\t\t\t\tARRAY_SIZE(ov9281_test_pattern_menu) - 1,\n-\t\t\t\t0, 0, ov9281_test_pattern_menu);\n+\t\t\t\t\t      V4L2_CID_ANALOGUE_GAIN,\n+\t\t\t\t\t      OV9281_GAIN_MIN, OV9281_GAIN_MAX,\n+\t\t\t\t\t      OV9281_GAIN_STEP,\n+\t\t\t\t\t      OV9281_GAIN_DEFAULT);\n+\n+\tov9281->test_pattern =\n+\t\tv4l2_ctrl_new_std_menu_items(handler, &ov9281_ctrl_ops,\n+\t\t\t\t\t     V4L2_CID_TEST_PATTERN,\n+\t\t\t\t\t     ARRAY_SIZE(ov9281_test_pattern_menu) - 1,\n+\t\t\t\t\t     0, 0, ov9281_test_pattern_menu);\n \n \tif (handler->error) {\n \t\tret = handler->error;\n@@ -1000,34 +935,14 @@ static int ov9281_probe(struct i2c_clien\n \t\t\tconst struct i2c_device_id *id)\n {\n \tstruct device *dev = &client->dev;\n-\tstruct device_node *node = dev->of_node;\n \tstruct ov9281 *ov9281;\n \tstruct v4l2_subdev *sd;\n-\tchar facing[2];\n \tint ret;\n \n-\tdev_info(dev, \"driver version: %02x.%02x.%02x\",\n-\t\tDRIVER_VERSION >> 16,\n-\t\t(DRIVER_VERSION & 0xff00) >> 8,\n-\t\tDRIVER_VERSION & 0x00ff);\n-\n \tov9281 = devm_kzalloc(dev, sizeof(*ov9281), GFP_KERNEL);\n \tif (!ov9281)\n \t\treturn -ENOMEM;\n \n-\tret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,\n-\t\t\t\t   &ov9281->module_index);\n-\tret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,\n-\t\t\t\t       &ov9281->module_facing);\n-\tret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,\n-\t\t\t\t       &ov9281->module_name);\n-\tret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,\n-\t\t\t\t       &ov9281->len_name);\n-\tif (ret) {\n-\t\tdev_err(dev, \"could not get module information!\\n\");\n-\t\treturn -EINVAL;\n-\t}\n-\n \tov9281->client = client;\n \tov9281->cur_mode = &supported_modes[0];\n \n@@ -1037,31 +952,15 @@ static int ov9281_probe(struct i2c_clien\n \t\treturn -EINVAL;\n \t}\n \n-\tov9281->reset_gpio = devm_gpiod_get(dev, \"reset\", GPIOD_OUT_LOW);\n+\tov9281->reset_gpio = devm_gpiod_get_optional(dev, \"reset\",\n+\t\t\t\t\t\t     GPIOD_OUT_LOW);\n \tif (IS_ERR(ov9281->reset_gpio))\n \t\tdev_warn(dev, \"Failed to get reset-gpios\\n\");\n \n-\tov9281->pwdn_gpio = devm_gpiod_get(dev, \"pwdn\", GPIOD_OUT_LOW);\n+\tov9281->pwdn_gpio = devm_gpiod_get_optional(dev, \"pwdn\", GPIOD_OUT_LOW);\n \tif (IS_ERR(ov9281->pwdn_gpio))\n \t\tdev_warn(dev, \"Failed to get pwdn-gpios\\n\");\n \n-\tov9281->pinctrl = devm_pinctrl_get(dev);\n-\tif (!IS_ERR(ov9281->pinctrl)) {\n-\t\tov9281->pins_default =\n-\t\t\tpinctrl_lookup_state(ov9281->pinctrl,\n-\t\t\t\t\t     OF_CAMERA_PINCTRL_STATE_DEFAULT);\n-\t\tif (IS_ERR(ov9281->pins_default))\n-\t\t\tdev_err(dev, \"could not get default pinstate\\n\");\n-\n-\t\tov9281->pins_sleep =\n-\t\t\tpinctrl_lookup_state(ov9281->pinctrl,\n-\t\t\t\t\t     OF_CAMERA_PINCTRL_STATE_SLEEP);\n-\t\tif (IS_ERR(ov9281->pins_sleep))\n-\t\t\tdev_err(dev, \"could not get sleep pinstate\\n\");\n-\t} else {\n-\t\tdev_err(dev, \"no pinctrl\\n\");\n-\t}\n-\n \tret = ov9281_configure_regulators(ov9281);\n \tif (ret) {\n \t\tdev_err(dev, \"Failed to get power regulators\\n\");\n@@ -1084,26 +983,16 @@ static int ov9281_probe(struct i2c_clien\n \tif (ret)\n \t\tgoto err_power_off;\n \n-#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API\n \tsd->internal_ops = &ov9281_internal_ops;\n \tsd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;\n-#endif\n-#if defined(CONFIG_MEDIA_CONTROLLER)\n+\n \tov9281->pad.flags = MEDIA_PAD_FL_SOURCE;\n-\tsd->entity.type = MEDIA_ENT_T_V4L2_SUBDEV_SENSOR;\n-\tret = media_entity_init(&sd->entity, 1, &ov9281->pad, 0);\n+\tsd->entity.function = MEDIA_ENT_F_CAM_SENSOR;\n+\tret = media_entity_pads_init(&sd->entity, 1, &ov9281->pad);\n \tif (ret < 0)\n \t\tgoto err_power_off;\n-#endif\n-\n-\tmemset(facing, 0, sizeof(facing));\n-\tif (strcmp(ov9281->module_facing, \"back\") == 0)\n-\t\tfacing[0] = 'b';\n-\telse\n-\t\tfacing[0] = 'f';\n \n-\tsnprintf(sd->name, sizeof(sd->name), \"m%02d_%s_%s %s\",\n-\t\t ov9281->module_index, facing,\n+\tsnprintf(sd->name, sizeof(sd->name), \"m%s %s\",\n \t\t OV9281_NAME, dev_name(sd->dev));\n \tret = v4l2_async_register_subdev_sensor_common(sd);\n \tif (ret) {\n@@ -1118,9 +1007,7 @@ static int ov9281_probe(struct i2c_clien\n \treturn 0;\n \n err_clean_entity:\n-#if defined(CONFIG_MEDIA_CONTROLLER)\n \tmedia_entity_cleanup(&sd->entity);\n-#endif\n err_power_off:\n \t__ov9281_power_off(ov9281);\n err_free_handler:\n@@ -1137,9 +1024,7 @@ static int ov9281_remove(struct i2c_clie\n \tstruct ov9281 *ov9281 = to_ov9281(sd);\n \n \tv4l2_async_unregister_subdev(sd);\n-#if defined(CONFIG_MEDIA_CONTROLLER)\n \tmedia_entity_cleanup(&sd->entity);\n-#endif\n \tv4l2_ctrl_handler_free(&ov9281->ctrl_handler);\n \tmutex_destroy(&ov9281->mutex);\n \n@@ -1151,13 +1036,11 @@ static int ov9281_remove(struct i2c_clie\n \treturn 0;\n }\n \n-#if IS_ENABLED(CONFIG_OF)\n static const struct of_device_id ov9281_of_match[] = {\n \t{ .compatible = \"ovti,ov9281\" },\n \t{},\n };\n MODULE_DEVICE_TABLE(of, ov9281_of_match);\n-#endif\n \n static const struct i2c_device_id ov9281_match_id[] = {\n \t{ \"ovti,ov9281\", 0 },\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0288-media-i2c-ov9281-Read-chip-ID-via-2-reads.patch",
    "content": "From e5bf123ed1069795286e5caa8f2a67bb5977691c Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Mon, 6 Jul 2020 17:51:32 +0100\nSubject: [PATCH] media: i2c: ov9281: Read chip ID via 2 reads\n\nVision Components have made an OV9281 module which blocks reading\nback the majority of registers to comply with NDAs, and in doing\nso doesn't allow auto-increment register reading as used when\nreading the chip ID.\n\nUse two reads and manually combine the results.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n drivers/media/i2c/ov9281.c | 14 +++++++++-----\n 1 file changed, 9 insertions(+), 5 deletions(-)\n\n--- a/drivers/media/i2c/ov9281.c\n+++ b/drivers/media/i2c/ov9281.c\n@@ -904,13 +904,17 @@ static int ov9281_check_sensor_id(struct\n \t\t\t\t  struct i2c_client *client)\n {\n \tstruct device *dev = &ov9281->client->dev;\n-\tu32 id = 0;\n+\tu32 id = 0, id_msb;\n \tint ret;\n \n-\tret = ov9281_read_reg(client, OV9281_REG_CHIP_ID,\n-\t\t\t      OV9281_REG_VALUE_16BIT, &id);\n-\tif (id != CHIP_ID) {\n-\t\tdev_err(dev, \"Unexpected sensor id(%06x), ret(%d)\\n\", id, ret);\n+\tret = ov9281_read_reg(client, OV9281_REG_CHIP_ID + 1,\n+\t\t\t      OV9281_REG_VALUE_08BIT, &id);\n+\tif (!ret)\n+\t\tret = ov9281_read_reg(client, OV9281_REG_CHIP_ID,\n+\t\t\t\t      OV9281_REG_VALUE_08BIT, &id_msb);\n+\tid |= (id_msb << 8);\n+\tif (ret || id != CHIP_ID) {\n+\t\tdev_err(dev, \"Unexpected sensor id(%04x), ret(%d)\\n\", id, ret);\n \t\treturn -ENODEV;\n \t}\n \n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0289-media-i2c-imx290-Explicitly-set-v-h-blank-on-mode-ch.patch",
    "content": "From f7ff6542ad9cdee4a1e67a0243f7dcc93cceb08a Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Tue, 7 Jul 2020 10:31:53 +0100\nSubject: [PATCH] media: i2c: imx290: Explicitly set v&h blank on mode\n change\n\n__v4l2_ctrl_modify_range only updates the current value should\nit be invalid within the new range. That can leave modes producing\nodd frame rates.\n\nExplicitly update the HBLANK and VBLANK values so that on mode\nchange we revert to the default frame rate for the mode.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n drivers/media/i2c/imx290.c | 10 ++++++++--\n 1 file changed, 8 insertions(+), 2 deletions(-)\n\n--- a/drivers/media/i2c/imx290.c\n+++ b/drivers/media/i2c/imx290.c\n@@ -796,17 +796,23 @@ static int imx290_set_fmt(struct v4l2_su\n \t\t\t__v4l2_ctrl_s_ctrl_int64(imx290->pixel_rate,\n \t\t\t\t\t\t imx290_calc_pixel_rate(imx290));\n \n-\t\tif (imx290->hblank)\n+\t\tif (imx290->hblank) {\n \t\t\t__v4l2_ctrl_modify_range(imx290->hblank,\n \t\t\t\t\t\t imx290->hmax_min - mode->width,\n \t\t\t\t\t\t IMX290_HMAX_MAX - mode->width,\n \t\t\t\t\t\t 1, mode->hmax - mode->width);\n-\t\tif (imx290->vblank)\n+\t\t\t__v4l2_ctrl_s_ctrl(imx290->hblank,\n+\t\t\t\t\t   mode->hmax - mode->width);\n+\t\t}\n+\t\tif (imx290->vblank) {\n \t\t\t__v4l2_ctrl_modify_range(imx290->vblank,\n \t\t\t\t\t\t mode->vmax - mode->height,\n \t\t\t\t\t\t IMX290_VMAX_MAX - mode->height,\n \t\t\t\t\t\t 1,\n \t\t\t\t\t\t mode->vmax - mode->height);\n+\t\t\t__v4l2_ctrl_s_ctrl(imx290->vblank,\n+\t\t\t\t\t   mode->vmax - mode->height);\n+\t\t}\n \t\tif (imx290->exposure)\n \t\t\t__v4l2_ctrl_modify_range(imx290->exposure,\n \t\t\t\t\t\t mode->vmax - mode->height,\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0290-media-i2c-imx290-Add-support-for-g_selection-to-repo.patch",
    "content": "From ee95eb32c4202a2d290af6c754806ef3bdfb3fda Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Tue, 7 Jul 2020 11:23:48 +0100\nSubject: [PATCH] media: i2c: imx290: Add support for g_selection to\n report cropping\n\nUserspace needs to know the cropping arrangements for each mode,\nso expose this through g_selection.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n drivers/media/i2c/imx290.c | 84 ++++++++++++++++++++++++++++++++++++++\n 1 file changed, 84 insertions(+)\n\n--- a/drivers/media/i2c/imx290.c\n+++ b/drivers/media/i2c/imx290.c\n@@ -61,6 +61,13 @@ enum imx290_clk_index {\n #define IMX290_PGCTRL_THRU BIT(1)\n #define IMX290_PGCTRL_MODE(n) ((n) << 4)\n \n+#define IMX290_NATIVE_WIDTH\t\t1945U\n+#define IMX290_NATIVE_HEIGHT\t\t1109U\n+#define IMX290_PIXEL_ARRAY_LEFT\t\t4U\n+#define IMX290_PIXEL_ARRAY_TOP\t\t12U\n+#define IMX290_PIXEL_ARRAY_WIDTH\t1937U\n+#define IMX290_PIXEL_ARRAY_HEIGHT\t1097U\n+\n static const char * const imx290_supply_name[] = {\n \t\"vdda\",\n \t\"vddd\",\n@@ -80,6 +87,7 @@ struct imx290_mode {\n \tu32 hmax;\n \tu32 vmax;\n \tu8 link_freq_index;\n+\tstruct v4l2_rect crop;\n \n \tconst struct imx290_regval *data;\n \tu32 data_size;\n@@ -384,6 +392,12 @@ static const struct imx290_mode imx290_m\n \t\t.hmax = 0x1130,\n \t\t.vmax = 0x0465,\n \t\t.link_freq_index = FREQ_INDEX_1080P,\n+\t\t.crop = {\n+\t\t\t.left = 4 + 8,\n+\t\t\t.top = 12 + 8,\n+\t\t\t.width = 1920,\n+\t\t\t.height = 1080,\n+\t\t},\n \t\t.data = imx290_1080p_settings,\n \t\t.data_size = ARRAY_SIZE(imx290_1080p_settings),\n \t\t.clk_data = {\n@@ -398,6 +412,12 @@ static const struct imx290_mode imx290_m\n \t\t.hmax = 0x19c8,\n \t\t.vmax = 0x02ee,\n \t\t.link_freq_index = FREQ_INDEX_720P,\n+\t\t.crop = {\n+\t\t\t.left = 4 + 8 + 320,\n+\t\t\t.top = 12 + 8 + 180,\n+\t\t\t.width = 1280,\n+\t\t\t.height = 720,\n+\t\t},\n \t\t.data = imx290_720p_settings,\n \t\t.data_size = ARRAY_SIZE(imx290_720p_settings),\n \t\t.clk_data = {\n@@ -415,6 +435,12 @@ static const struct imx290_mode imx290_m\n \t\t.hmax = 0x0898,\n \t\t.vmax = 0x0465,\n \t\t.link_freq_index = FREQ_INDEX_1080P,\n+\t\t.crop = {\n+\t\t\t.left = 4 + 8,\n+\t\t\t.top = 12 + 8,\n+\t\t\t.width = 1920,\n+\t\t\t.height = 1080,\n+\t\t},\n \t\t.data = imx290_1080p_settings,\n \t\t.data_size = ARRAY_SIZE(imx290_1080p_settings),\n \t\t.clk_data = {\n@@ -429,6 +455,12 @@ static const struct imx290_mode imx290_m\n \t\t.hmax = 0x0ce4,\n \t\t.vmax = 0x02ee,\n \t\t.link_freq_index = FREQ_INDEX_720P,\n+\t\t.crop = {\n+\t\t\t.left = 4 + 8 + 320,\n+\t\t\t.top = 12 + 8 + 180,\n+\t\t\t.width = 1280,\n+\t\t\t.height = 720,\n+\t\t},\n \t\t.data = imx290_720p_settings,\n \t\t.data_size = ARRAY_SIZE(imx290_720p_settings),\n \t\t.clk_data = {\n@@ -875,6 +907,57 @@ static int imx290_write_current_format(s\n \treturn 0;\n }\n \n+static const struct v4l2_rect *\n+__imx290_get_pad_crop(struct imx290 *imx290, struct v4l2_subdev_pad_config *cfg,\n+\t\t      unsigned int pad, enum v4l2_subdev_format_whence which)\n+{\n+\tswitch (which) {\n+\tcase V4L2_SUBDEV_FORMAT_TRY:\n+\t\treturn v4l2_subdev_get_try_crop(&imx290->sd, cfg, pad);\n+\tcase V4L2_SUBDEV_FORMAT_ACTIVE:\n+\t\treturn &imx290->current_mode->crop;\n+\t}\n+\n+\treturn NULL;\n+}\n+\n+static int imx290_get_selection(struct v4l2_subdev *sd,\n+\t\t\t\tstruct v4l2_subdev_pad_config *cfg,\n+\t\t\t\tstruct v4l2_subdev_selection *sel)\n+{\n+\tswitch (sel->target) {\n+\tcase V4L2_SEL_TGT_CROP: {\n+\t\tstruct imx290 *imx290 = to_imx290(sd);\n+\n+\t\tmutex_lock(&imx290->lock);\n+\t\tsel->r = *__imx290_get_pad_crop(imx290, cfg, sel->pad,\n+\t\t\t\t\t\tsel->which);\n+\t\tmutex_unlock(&imx290->lock);\n+\n+\t\treturn 0;\n+\t}\n+\n+\tcase V4L2_SEL_TGT_NATIVE_SIZE:\n+\t\tsel->r.top = 0;\n+\t\tsel->r.left = 0;\n+\t\tsel->r.width = IMX290_NATIVE_WIDTH;\n+\t\tsel->r.height = IMX290_NATIVE_HEIGHT;\n+\n+\t\treturn 0;\n+\n+\tcase V4L2_SEL_TGT_CROP_DEFAULT:\n+\tcase V4L2_SEL_TGT_CROP_BOUNDS:\n+\t\tsel->r.top = IMX290_PIXEL_ARRAY_TOP;\n+\t\tsel->r.left = IMX290_PIXEL_ARRAY_LEFT;\n+\t\tsel->r.width = IMX290_PIXEL_ARRAY_WIDTH;\n+\t\tsel->r.height = IMX290_PIXEL_ARRAY_HEIGHT;\n+\n+\t\treturn 0;\n+\t}\n+\n+\treturn -EINVAL;\n+}\n+\n /* Start streaming */\n static int imx290_start_streaming(struct imx290 *imx290)\n {\n@@ -1073,6 +1156,7 @@ static const struct v4l2_subdev_pad_ops\n \t.enum_frame_size = imx290_enum_frame_size,\n \t.get_fmt = imx290_get_fmt,\n \t.set_fmt = imx290_set_fmt,\n+\t.get_selection = imx290_get_selection,\n };\n \n static const struct v4l2_subdev_ops imx290_subdev_ops = {\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0291-media-i2c-imx290-Set-the-colorspace-fields-in-the-fo.patch",
    "content": "From b6eaf8158d0e2053680dc72e45d2a4e7d0617312 Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Tue, 7 Jul 2020 11:51:26 +0100\nSubject: [PATCH] media: i2c: imx290: Set the colorspace fields in the\n format\n\nThe colorspace fields were left untouched in imx290_set_fmt\nwhich lead to a v4l2-compliance failure.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n drivers/media/i2c/imx290.c | 8 ++++++++\n 1 file changed, 8 insertions(+)\n\n--- a/drivers/media/i2c/imx290.c\n+++ b/drivers/media/i2c/imx290.c\n@@ -813,6 +813,14 @@ static int imx290_set_fmt(struct v4l2_su\n \n \tfmt->format.code = imx290->formats[i].code;\n \tfmt->format.field = V4L2_FIELD_NONE;\n+\tfmt->format.colorspace = V4L2_COLORSPACE_SRGB;\n+\tfmt->format.ycbcr_enc =\n+\t\t\tV4L2_MAP_YCBCR_ENC_DEFAULT(fmt->format.colorspace);\n+\tfmt->format.quantization =\n+\t\tV4L2_MAP_QUANTIZATION_DEFAULT(true, fmt->format.colorspace,\n+\t\t\t\t\t      fmt->format.ycbcr_enc);\n+\tfmt->format.xfer_func =\n+\t\tV4L2_MAP_XFER_FUNC_DEFAULT(fmt->format.colorspace);\n \n \tif (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {\n \t\tformat = v4l2_subdev_get_try_format(sd, cfg, fmt->pad);\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0292-media-bcm2835-unicam-Reinstate-V4L2_CAP_READWRITE-in.patch",
    "content": "From 615ab5f76328d089d64d46ea0676efe407e6b9c5 Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Tue, 7 Jul 2020 14:23:40 +0100\nSubject: [PATCH] media: bcm2835-unicam: Reinstate V4L2_CAP_READWRITE\n in the caps\n\nv4l2-compliance throws a failure if the device doesn't advertise\nV4L2_CAP_READWRITE but allows read or write operations.\nWe do support read, so reinstate the flag.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n drivers/media/platform/bcm2835/bcm2835-unicam.c | 4 ++--\n 1 file changed, 2 insertions(+), 2 deletions(-)\n\n--- a/drivers/media/platform/bcm2835/bcm2835-unicam.c\n+++ b/drivers/media/platform/bcm2835/bcm2835-unicam.c\n@@ -2418,8 +2418,8 @@ static int register_node(struct unicam_d\n \tvdev->queue = q;\n \tvdev->lock = &node->lock;\n \tvdev->device_caps = (pad_id == IMAGE_PAD) ?\n-\t\t\t    (V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING) :\n-\t\t\t    (V4L2_CAP_META_CAPTURE | V4L2_CAP_STREAMING);\n+\t\t\t\tV4L2_CAP_VIDEO_CAPTURE : V4L2_CAP_META_CAPTURE;\n+\tvdev->device_caps |= V4L2_CAP_READWRITE | V4L2_CAP_STREAMING;\n \n \t/* Define the device names */\n \tsnprintf(vdev->name, sizeof(vdev->name), \"%s-%s\", UNICAM_MODULE_NAME,\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0293-media-bcm2835-unicam-Ensure-type-is-VIDEO_CAPTURE-in.patch",
    "content": "From c1dc0c0bcda6de7374a46d99a73f855603d366a5 Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Tue, 7 Jul 2020 14:52:43 +0100\nSubject: [PATCH] media: bcm2835-unicam: Ensure type is VIDEO_CAPTURE\n in [g|s]_selection\n\n[g|s]_selection pass in a buffer type that needs to be validated\nbefore passing on to the sensor subdev.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n drivers/media/platform/bcm2835/bcm2835-unicam.c | 6 ++++++\n 1 file changed, 6 insertions(+)\n\n--- a/drivers/media/platform/bcm2835/bcm2835-unicam.c\n+++ b/drivers/media/platform/bcm2835/bcm2835-unicam.c\n@@ -1885,6 +1885,9 @@ static int unicam_s_selection(struct fil\n \t\t.r = sel->r,\n \t};\n \n+\tif (sel->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)\n+\t\treturn -EINVAL;\n+\n \treturn v4l2_subdev_call(dev->sensor, pad, set_selection, NULL, &sdsel);\n }\n \n@@ -1899,6 +1902,9 @@ static int unicam_g_selection(struct fil\n \t};\n \tint ret;\n \n+\tif (sel->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)\n+\t\treturn -EINVAL;\n+\n \tret = v4l2_subdev_call(dev->sensor, pad, get_selection, NULL, &sdsel);\n \tif (!ret)\n \t\tsel->r = sdsel.r;\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0294-media-bcm2835-unicam-Set-VPU-min-clock-freq-to-250Mh.patch",
    "content": "From d839c8936020f393c5536d83b783198217243e8d Mon Sep 17 00:00:00 2001\nFrom: Naushir Patuck <naush@raspberrypi.com>\nDate: Mon, 11 May 2020 13:02:22 +0100\nSubject: [PATCH] media: bcm2835: unicam: Set VPU min clock freq to\n 250Mhz.\n\nWhen streaming with Unicam, the VPU must have a clock frequency of at\nleast 250Mhz.  Otherwise, the input fifos could overrun, causing\nimage corruption.\n\nSigned-off-by: Naushir Patuck <naush@raspberrypi.com>\n---\n .../media/platform/bcm2835/bcm2835-unicam.c   | 49 +++++++++++++++++--\n 1 file changed, 44 insertions(+), 5 deletions(-)\n\n--- a/drivers/media/platform/bcm2835/bcm2835-unicam.c\n+++ b/drivers/media/platform/bcm2835/bcm2835-unicam.c\n@@ -89,6 +89,11 @@ MODULE_PARM_DESC(debug, \"Debug level 0-3\n \t\tv4l2_err(&(dev)->v4l2_dev, fmt, ##arg)\n \n /*\n+ * Unicam must request a minimum of 250Mhz from the VPU clock.\n+ * Otherwise the input FIFOs overrun and cause image corruption.\n+ */\n+#define MIN_VPU_CLOCK_RATE (250 * 1000 * 1000)\n+/*\n  * To protect against a dodgy sensor driver never returning an error from\n  * enum_mbus_code, set a maximum index value to be used.\n  */\n@@ -417,8 +422,10 @@ struct unicam_device {\n \tvoid __iomem *base;\n \t/* clock gating base address */\n \tvoid __iomem *clk_gate_base;\n-\t/* clock handle */\n+\t/* lp clock handle */\n \tstruct clk *clock;\n+\t/* vpu clock handle */\n+\tstruct clk *vpu_clock;\n \t/* V4l2 device */\n \tstruct v4l2_device v4l2_dev;\n \tstruct media_device mdev;\n@@ -1678,16 +1685,28 @@ static int unicam_start_streaming(struct\n \tunicam_dbg(1, dev, \"Running with %u data lanes\\n\",\n \t\t   dev->active_data_lanes);\n \n-\tret = clk_set_rate(dev->clock, 100 * 1000 * 1000);\n+\tret = clk_set_min_rate(dev->vpu_clock, MIN_VPU_CLOCK_RATE);\n+\tif (ret) {\n+\t\tunicam_err(dev, \"failed to set up VPU clock\\n\");\n+\t\tgoto err_pm_put;\n+\t}\n+\n+\tret = clk_prepare_enable(dev->vpu_clock);\n \tif (ret) {\n-\t\tunicam_err(dev, \"failed to set up clock\\n\");\n+\t\tunicam_err(dev, \"Failed to enable VPU clock: %d\\n\", ret);\n \t\tgoto err_pm_put;\n \t}\n \n+\tret = clk_set_rate(dev->clock, 100 * 1000 * 1000);\n+\tif (ret) {\n+\t\tunicam_err(dev, \"failed to set up CSI clock\\n\");\n+\t\tgoto err_vpu_clock;\n+\t}\n+\n \tret = clk_prepare_enable(dev->clock);\n \tif (ret) {\n \t\tunicam_err(dev, \"Failed to enable CSI clock: %d\\n\", ret);\n-\t\tgoto err_pm_put;\n+\t\tgoto err_vpu_clock;\n \t}\n \n \tfor (i = 0; i < ARRAY_SIZE(dev->node); i++) {\n@@ -1721,6 +1740,11 @@ static int unicam_start_streaming(struct\n err_disable_unicam:\n \tunicam_disable(dev);\n \tclk_disable_unprepare(dev->clock);\n+err_vpu_clock:\n+\tret = clk_set_min_rate(dev->vpu_clock, 0);\n+\tif (ret)\n+\t\tunicam_err(dev, \"failed to reset the VPU clock\\n\");\n+\tclk_disable_unprepare(dev->vpu_clock);\n err_pm_put:\n \tunicam_runtime_put(dev);\n err_streaming:\n@@ -1738,6 +1762,8 @@ static void unicam_stop_streaming(struct\n \tnode->streaming = false;\n \n \tif (node->pad_id == IMAGE_PAD) {\n+\t\tint ret;\n+\n \t\t/*\n \t\t * Stop streaming the sensor and disable the peripheral.\n \t\t * We cannot continue streaming embedded data with the\n@@ -1747,6 +1773,12 @@ static void unicam_stop_streaming(struct\n \t\t\tunicam_err(dev, \"stream off failed in subdev\\n\");\n \n \t\tunicam_disable(dev);\n+\n+\t\tret = clk_set_min_rate(dev->vpu_clock, 0);\n+\t\tif (ret)\n+\t\t\tunicam_err(dev, \"failed to reset the min VPU clock\\n\");\n+\n+\t\tclk_disable_unprepare(dev->vpu_clock);\n \t\tclk_disable_unprepare(dev->clock);\n \t\tunicam_runtime_put(dev);\n \n@@ -2750,11 +2782,18 @@ static int unicam_probe(struct platform_\n \n \tunicam->clock = devm_clk_get(&pdev->dev, \"lp\");\n \tif (IS_ERR(unicam->clock)) {\n-\t\tunicam_err(unicam, \"Failed to get clock\\n\");\n+\t\tunicam_err(unicam, \"Failed to get lp clock\\n\");\n \t\tret = PTR_ERR(unicam->clock);\n \t\tgoto err_unicam_put;\n \t}\n \n+\tunicam->vpu_clock = devm_clk_get(&pdev->dev, \"vpu\");\n+\tif (IS_ERR(unicam->vpu_clock)) {\n+\t\tunicam_err(unicam, \"Failed to get vpu clock\\n\");\n+\t\tret = PTR_ERR(unicam->vpu_clock);\n+\t\tgoto err_unicam_put;\n+\t}\n+\n \tret = platform_get_irq(pdev, 0);\n \tif (ret <= 0) {\n \t\tdev_err(&pdev->dev, \"No IRQ resource\\n\");\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0295-dt-bindings-bcm2835-unicam-Update-documentation-with.patch",
    "content": "From 45ae6757ee8379bc04e718591b23e45fae4c968c Mon Sep 17 00:00:00 2001\nFrom: Naushir Patuck <naush@raspberrypi.com>\nDate: Mon, 11 May 2020 13:06:27 +0100\nSubject: [PATCH] dt-bindings: bcm2835-unicam: Update documentation\n with new clock params\n\nUpdate the documentation to reflect the new \"VPU\" clock needed\nby the bcm2835-unicam driver.\n\nSigned-off-by: Naushir Patuck <naush@raspberrypi.com>\n---\n .../devicetree/bindings/media/bcm2835-unicam.txt          | 8 ++++----\n 1 file changed, 4 insertions(+), 4 deletions(-)\n\n--- a/Documentation/devicetree/bindings/media/bcm2835-unicam.txt\n+++ b/Documentation/devicetree/bindings/media/bcm2835-unicam.txt\n@@ -20,7 +20,7 @@ Required properties:\n - interrupts\t: should contain the IRQ line for this Unicam instance.\n - clocks\t: list of clock specifiers, corresponding to entries in\n \t\t  clock-names property.\n-- clock-names\t: must contain an \"lp\" entry, matching entries in the\n+- clock-names\t: must contain \"lp\" and \"vpu\" entries, matching entries in the\n \t\t  clocks property.\n \n Unicam supports a single port node. It should contain one 'port' child node\n@@ -46,9 +46,9 @@ Example:\n \t\treg = <0x7e801000 0x800>,\n \t\t      <0x7e802004 0x4>;\n \t\tinterrupts = <2 7>;\n-\t\tclocks = <&clocks BCM2835_CLOCK_CAM1>;\n-\t\tclock-names = \"lp\";\n-\n+\t\tclocks = <&clocks BCM2835_CLOCK_CAM1>,\n+\t\t\t <&firmware_clocks 4>;\n+\t\tclock-names = \"lp\", \"vpu\";\n \t\tport {\n \t\t\tcsi1_ep: endpoint {\n \t\t\t\tremote-endpoint = <&tc358743_0>;\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0296-media-i2c-ov5647-Parse-and-register-properties.patch",
    "content": "From 0f0998ed9620f676ee78eb6f606b0b2fa118bf68 Mon Sep 17 00:00:00 2001\nFrom: Laurent Pinchart <laurent.pinchart@ideasonboard.com>\nDate: Sat, 4 Jul 2020 01:45:08 +0300\nSubject: [PATCH] media: i2c: ov5647: Parse and register properties\n\nParse device properties and register controls for them using the V4L2\nfwnode properties helpers.\n\nSigned-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>\n---\n drivers/media/i2c/ov5647.c | 13 ++++++++++++-\n 1 file changed, 12 insertions(+), 1 deletion(-)\n\n--- a/drivers/media/i2c/ov5647.c\n+++ b/drivers/media/i2c/ov5647.c\n@@ -1501,6 +1501,7 @@ static int ov5647_probe(struct i2c_clien\n \tstruct device_node *np = client->dev.of_node;\n \tu32 xclk_freq;\n \tint hblank, exposure_max, exposure_def;\n+\tstruct v4l2_fwnode_device_properties props;\n \n \tsensor = devm_kzalloc(dev, sizeof(*sensor), GFP_KERNEL);\n \tif (!sensor)\n@@ -1534,7 +1535,7 @@ static int ov5647_probe(struct i2c_clien\n \tmutex_init(&sensor->lock);\n \n \t/* Initialise controls. */\n-\tv4l2_ctrl_handler_init(&sensor->ctrls, 7);\n+\tv4l2_ctrl_handler_init(&sensor->ctrls, 9);\n \tv4l2_ctrl_new_std(&sensor->ctrls, &ov5647_ctrl_ops,\n \t\t\t  V4L2_CID_AUTOGAIN,\n \t\t\t  0,  /* min */\n@@ -1598,6 +1599,16 @@ static int ov5647_probe(struct i2c_clien\n \t\t\t__func__, ret);\n \t\tgoto error;\n \t}\n+\n+\tret = v4l2_fwnode_device_parse(&client->dev, &props);\n+\tif (ret)\n+\t\tgoto error;\n+\n+\tret = v4l2_ctrl_new_fwnode_properties(&sensor->ctrls, &ov5647_ctrl_ops,\n+\t\t\t\t\t      &props);\n+\tif (ret)\n+\t\tgoto error;\n+\n \tsensor->sd.ctrl_handler = &sensor->ctrls;\n \n \t/* Write out the register set over I2C on stream-on. */\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0297-leds-Add-the-actpwr-trigger.patch",
    "content": "From 136ae921cea7e7a189ee99d126253631f880ded0 Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.com>\nDate: Mon, 13 Jul 2020 10:33:19 +0100\nSubject: [PATCH] leds: Add the actpwr trigger\n\nThe actpwr trigger is a meta trigger that cycles between an inverted\nmmc0 and default-on. It is written in a way that could fairly easily\nbe generalised to support alternative sets of source triggers.\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.com>\n---\n drivers/leds/trigger/Kconfig          |  11 ++\n drivers/leds/trigger/Makefile         |   1 +\n drivers/leds/trigger/ledtrig-actpwr.c | 190 ++++++++++++++++++++++++++\n 3 files changed, 202 insertions(+)\n create mode 100644 drivers/leds/trigger/ledtrig-actpwr.c\n\n--- a/drivers/leds/trigger/Kconfig\n+++ b/drivers/leds/trigger/Kconfig\n@@ -151,4 +151,15 @@ config LEDS_TRIGGER_AUDIO\n \t  the audio mute and mic-mute changes.\n \t  If unsure, say N\n \n+config LEDS_TRIGGER_ACTPWR\n+\ttristate \"ACT/PWR Input Trigger\"\n+\tdepends on LEDS_TRIGGERS\n+\thelp\n+\t  This trigger is intended for platforms that have one software-\n+\t  controllable LED and no dedicated activity or power LEDs, hence the\n+\t  need to make the one LED perform both functions. It cycles between\n+\t  default-on and an inverted mmc0 every 500ms, guaranteeing that it is\n+\t  on for at least half of the time.\n+\t  If unsure, say N.\n+\n endif # LEDS_TRIGGERS\n--- a/drivers/leds/trigger/Makefile\n+++ b/drivers/leds/trigger/Makefile\n@@ -16,3 +16,4 @@ obj-$(CONFIG_LEDS_TRIGGER_PANIC)\t+= ledt\n obj-$(CONFIG_LEDS_TRIGGER_NETDEV)\t+= ledtrig-netdev.o\n obj-$(CONFIG_LEDS_TRIGGER_PATTERN)\t+= ledtrig-pattern.o\n obj-$(CONFIG_LEDS_TRIGGER_AUDIO)\t+= ledtrig-audio.o\n+obj-$(CONFIG_LEDS_TRIGGER_ACTPWR)\t+= ledtrig-actpwr.o\n--- /dev/null\n+++ b/drivers/leds/trigger/ledtrig-actpwr.c\n@@ -0,0 +1,190 @@\n+// SPDX-License-Identifier: GPL-2.0\n+/*\n+ * Activity/power trigger\n+ *\n+ * Copyright (C) 2020 Raspberry Pi (Trading) Ltd.\n+ *\n+ * Based on Atsushi Nemoto's ledtrig-heartbeat.c, although there may be\n+ * nothing left of the original now.\n+ */\n+\n+#include <linux/module.h>\n+#include <linux/kernel.h>\n+#include <linux/init.h>\n+#include <linux/timer.h>\n+#include <linux/leds.h>\n+#include \"../leds.h\"\n+\n+enum {\n+\tTRIG_ACT,\n+\tTRIG_PWR,\n+\n+\tTRIG_COUNT\n+};\n+\n+struct actpwr_trig_src {\n+\tconst char *name;\n+\tint interval;\n+\tbool invert;\n+};\n+\n+struct actpwr_vled {\n+\tstruct led_classdev cdev;\n+\tstruct actpwr_trig_data *parent;\n+\tenum led_brightness value;\n+\tunsigned int interval;\n+\tbool invert;\n+};\n+\n+struct actpwr_trig_data {\n+\tstruct led_trigger trig;\n+\tstruct actpwr_vled virt_leds[TRIG_COUNT];\n+\tstruct actpwr_vled *active;\n+\tstruct timer_list timer;\n+\tint next_active;\n+};\n+\n+static int actpwr_trig_activate(struct led_classdev *led_cdev);\n+static void actpwr_trig_deactivate(struct led_classdev *led_cdev);\n+\n+static const struct actpwr_trig_src actpwr_trig_sources[TRIG_COUNT] = {\n+\t[TRIG_ACT] = { \"mmc0\", 500, true },\n+\t[TRIG_PWR] = { \"default-on\", 500, false },\n+};\n+\n+static struct actpwr_trig_data actpwr_data = {\n+\t{\n+\t\t.name     = \"actpwr\",\n+\t\t.activate = actpwr_trig_activate,\n+\t\t.deactivate = actpwr_trig_deactivate,\n+\t}\n+};\n+\n+static void actpwr_brightness_set(struct led_classdev *led_cdev,\n+\t\t\t\t  enum led_brightness value)\n+{\n+\tstruct actpwr_vled *vled = container_of(led_cdev, struct actpwr_vled,\n+\t\t\t\t\t       cdev);\n+\tstruct actpwr_trig_data *trig = vled->parent;\n+\n+\tif (vled->invert)\n+\t\tvalue = !value;\n+\tvled->value = value;\n+\n+\tif (vled == trig->active)\n+\t\tled_trigger_event(&trig->trig, value);\n+}\n+\n+static int actpwr_brightness_set_blocking(struct led_classdev *led_cdev,\n+\t\t\t\t\t  enum led_brightness value)\n+{\n+\tactpwr_brightness_set(led_cdev, value);\n+\treturn 0;\n+}\n+\n+static enum led_brightness actpwr_brightness_get(struct led_classdev *led_cdev)\n+{\n+\tstruct actpwr_vled *vled = container_of(led_cdev, struct actpwr_vled,\n+\t\t\t\t\t      cdev);\n+\n+\treturn vled->value;\n+}\n+\n+static void actpwr_trig_cycle(struct timer_list *t)\n+{\n+\tstruct actpwr_trig_data *trig  = &actpwr_data;\n+\tstruct actpwr_vled *active;\n+\n+\tactive = &trig->virt_leds[trig->next_active];\n+\ttrig->active = active;\n+\ttrig->next_active = (trig->next_active + 1) % TRIG_COUNT;\n+\n+\tled_trigger_event(&trig->trig, active->value);\n+\n+\tmod_timer(&trig->timer, jiffies + msecs_to_jiffies(active->interval));\n+}\n+\n+static int actpwr_trig_activate(struct led_classdev *led_cdev)\n+{\n+\tstruct actpwr_trig_data *trig  = &actpwr_data;\n+\n+\t/* Start the timer if this is the first LED */\n+\tif (!trig->active)\n+\t\tactpwr_trig_cycle(&trig->timer);\n+\telse\n+\t\tled_set_brightness_nosleep(led_cdev, trig->active->value);\n+\n+\treturn 0;\n+}\n+\n+static void actpwr_trig_deactivate(struct led_classdev *led_cdev)\n+{\n+\tstruct actpwr_trig_data *trig  = &actpwr_data;\n+\n+\tif (list_empty(&trig->trig.led_cdevs)) {\n+\t\tdel_timer_sync(&trig->timer);\n+\t\ttrig->active = NULL;\n+\t}\n+}\n+\n+static int __init actpwr_trig_init(void)\n+{\n+\tstruct actpwr_trig_data *trig  = &actpwr_data;\n+\tint ret = 0;\n+\tint i;\n+\n+\ttimer_setup(&trig->timer, actpwr_trig_cycle, 0);\n+\n+\t/* Register one \"LED\" for each source trigger */\n+\tfor (i = 0; i < TRIG_COUNT; i++)\n+\t{\n+\t\tstruct actpwr_vled *vled = &trig->virt_leds[i];\n+\t\tstruct led_classdev *cdev = &vled->cdev;\n+\t\tconst struct actpwr_trig_src *src = &actpwr_trig_sources[i];\n+\n+\t\tvled->parent = trig;\n+\t\tvled->interval = src->interval;\n+\t\tvled->invert = src->invert;\n+\t\tcdev->name = src->name;\n+\t\tcdev->brightness_set = actpwr_brightness_set;\n+\t\tcdev->brightness_set_blocking = actpwr_brightness_set_blocking;\n+\t\tcdev->brightness_get = actpwr_brightness_get;\n+\t\tcdev->default_trigger = src->name;\n+\t\tret = led_classdev_register(NULL, cdev);\n+\t\tif (ret)\n+\t\t\tgoto error_classdev;\n+\t}\n+\n+\tret = led_trigger_register(&trig->trig);\n+\tif (ret)\n+\t\tgoto error_classdev;\n+\n+\treturn 0;\n+\n+error_classdev:\n+\twhile (i > 0)\n+\t{\n+\t\ti--;\n+\t\tled_classdev_unregister(&trig->virt_leds[i].cdev);\n+\t}\n+\n+\treturn ret;\n+}\n+\n+static void __exit actpwr_trig_exit(void)\n+{\n+\tint i;\n+\n+\tled_trigger_unregister(&actpwr_data.trig);\n+\tfor (i = 0; i < TRIG_COUNT; i++)\n+\t{\n+\t\tled_classdev_unregister(&actpwr_data.virt_leds[i].cdev);\n+\t}\n+}\n+\n+module_init(actpwr_trig_init);\n+module_exit(actpwr_trig_exit);\n+\n+MODULE_AUTHOR(\"Phil Elwell <phil@raspberrypi.com>\");\n+MODULE_DESCRIPTION(\"ACT/PWR LED trigger\");\n+MODULE_LICENSE(\"GPL v2\");\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0298-staging-vchiq_arm-children-inherit-DMA-config.patch",
    "content": "From e2e8b2dfdfda27958a276c719fda8b162f229bc8 Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.com>\nDate: Tue, 21 Jul 2020 17:34:09 +0100\nSubject: [PATCH] staging: vchiq_arm: children inherit DMA config\n\nAlthough it is no longer necessary for vchiq's children to have a\ndifferent DMA configuration to the parent, they do still need to\nexplicitly to have their DMA configuration set - to be that of the\nparent.\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.com>\n---\n .../vc04_services/interface/vchiq_arm/vchiq_arm.c      | 10 ++++++++++\n 1 file changed, 10 insertions(+)\n\n--- a/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_arm.c\n+++ b/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_arm.c\n@@ -2720,8 +2720,18 @@ vchiq_register_child(struct platform_dev\n \n \tchild->dev.of_node = np;\n \n+\t/*\n+\t * We want the dma-ranges etc to be copied from the parent VCHIQ device\n+\t * to be passed on to the children without a node of their own.\n+\t */\n+\tif (!np)\n+\t\tnp = pdev->dev.of_node;\n+\n \tof_dma_configure(&child->dev, np, true);\n \n+\tif (np != pdev->dev.of_node)\n+\t\tof_node_put(np);\n+\n \treturn child;\n }\n \n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0299-bcm2835-dma-Advertise-the-full-DMA-range.patch",
    "content": "From 0aa2706c9c452213c352400a41e4878c09995153 Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.com>\nDate: Wed, 22 Jul 2020 17:59:31 +0100\nSubject: [PATCH] bcm2835-dma: Advertise the full DMA range\n\nUnless the DMA mask is set wider than 32 bits, DMA mapping will use a\nbounce buffer.\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.com>\n---\n drivers/dma/bcm2835-dma.c | 18 +++++++++++++++---\n 1 file changed, 15 insertions(+), 3 deletions(-)\n\n--- a/drivers/dma/bcm2835-dma.c\n+++ b/drivers/dma/bcm2835-dma.c\n@@ -41,6 +41,7 @@\n #define BCM2711_DMA_MEMCPY_CHAN 14\n \n struct bcm2835_dma_cfg_data {\n+\tu64\tdma_mask;\n \tu32\tchan_40bit_mask;\n };\n \n@@ -300,10 +301,12 @@ DEFINE_SPINLOCK(memcpy_lock);\n \n static const struct bcm2835_dma_cfg_data bcm2835_dma_cfg = {\n \t.chan_40bit_mask = 0,\n+\t.dma_mask = DMA_BIT_MASK(32),\n };\n \n static const struct bcm2835_dma_cfg_data bcm2711_dma_cfg = {\n \t.chan_40bit_mask = BIT(11) | BIT(12) | BIT(13) | BIT(14),\n+\t.dma_mask = DMA_BIT_MASK(36),\n };\n \n static inline size_t bcm2835_dma_max_frame_length(struct bcm2835_chan *c)\n@@ -1180,6 +1183,8 @@ static struct dma_chan *bcm2835_dma_xlat\n \n static int bcm2835_dma_probe(struct platform_device *pdev)\n {\n+\tconst struct bcm2835_dma_cfg_data *cfg_data;\n+\tconst struct of_device_id *of_id;\n \tstruct bcm2835_dmadev *od;\n \tstruct resource *res;\n \tvoid __iomem *base;\n@@ -1189,13 +1194,20 @@ static int bcm2835_dma_probe(struct plat\n \tint irq_flags;\n \tuint32_t chans_available;\n \tchar chan_name[BCM2835_DMA_CHAN_NAME_SIZE];\n-\tconst struct of_device_id *of_id;\n \tint chan_count, chan_start, chan_end;\n \n+\tof_id = of_match_node(bcm2835_dma_of_match, pdev->dev.of_node);\n+\tif (!of_id) {\n+\t\tdev_err(&pdev->dev, \"Failed to match compatible string\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tcfg_data = of_id->data;\n+\n \tif (!pdev->dev.dma_mask)\n \t\tpdev->dev.dma_mask = &pdev->dev.coherent_dma_mask;\n \n-\trc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));\n+\trc = dma_set_mask_and_coherent(&pdev->dev, cfg_data->dma_mask);\n \tif (rc) {\n \t\tdev_err(&pdev->dev, \"Unable to set DMA mask\\n\");\n \t\treturn rc;\n@@ -1260,7 +1272,7 @@ static int bcm2835_dma_probe(struct plat\n \t\treturn -EINVAL;\n \t}\n \n-\tod->cfg_data = of_id->data;\n+\tod->cfg_data = cfg_data;\n \n \t/* Request DMA channel mask from device tree */\n \tif (of_property_read_u32(pdev->dev.of_node,\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0300-ARM-proc-v7-Force-misalignment-of-early-stmia.patch",
    "content": "From 9e5b2debe12d4e840a7d3ec0cf22b215396ed46e Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.com>\nDate: Wed, 29 Jul 2020 13:47:55 +0100\nSubject: [PATCH] ARM: proc-v7: Force misalignment of early stmia\n\nIn an attempt to prevent the problem of CPUn not starting, explicitly\nmisalign the scratch space used to save registers acros the cache\ninvalidation.\n\nNotes:\nAt this stage in the boot process the core is running with its cache\ndisabled. Before enabling the cache its contents must be explicitly\ninvalidated, a process that requires quite a few registers that the\ncaller must preserve. Evidence suggests that something is writing a\nblock of zeroes over that space at a time when all other cores should\nbe idle, possibly some kind of write-combiner, and the misalignment is\ndesigned to disrupt any write-coalescing.\n\nIn truth, I don't understand why this patch works, and when the failure\nis so random it is hard to be certain that this isn't just rolling the\ndice again. One interesting test would be to change the \"addeq r12, #4\"s\nto \"addeq r12, #0\"s determine see if the offset itself is significant or\njust the additional code.\n\nSee: https://github.com/Hexxeh/rpi-firmware/issues/232\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.com>\n---\n arch/arm/mm/proc-v7.S | 6 +++++-\n 1 file changed, 5 insertions(+), 1 deletion(-)\n\n--- a/arch/arm/mm/proc-v7.S\n+++ b/arch/arm/mm/proc-v7.S\n@@ -287,6 +287,8 @@ __v7_ca17mp_setup:\n \tmov\tr10, #0\n 1:\tadr\tr0, __v7_setup_stack_ptr\n \tldr\tr12, [r0]\n+\ttst\tr12, #0x1f\n+\taddeq\tr12, r12, #4\n \tadd\tr12, r12, r0\t\t\t@ the local stack\n \tstmia\tr12, {r1-r6, lr}\t\t@ v7_invalidate_l1 touches r0-r6\n \tbl      v7_invalidate_l1\n@@ -474,6 +476,8 @@ __v7_setup:\n \tadr\tr0, __v7_setup_stack_ptr\n \tldr\tr12, [r0]\n \tadd\tr12, r12, r0\t\t\t@ the local stack\n+\ttst\tr12, #0x1f\n+\taddeq\tr12, r12, #4\n \tstmia\tr12, {r1-r6, lr}\t\t@ v7_invalidate_l1 touches r0-r6\n \tbl      v7_invalidate_l1\n \tldmia\tr12, {r1-r6, lr}\n@@ -557,7 +561,7 @@ ENDPROC(__v7_setup)\n \t.bss\n \t.align\t2\n __v7_setup_stack:\n-\t.space\t4 * 7\t\t\t\t@ 7 registers\n+\t.space\t4 * 8\t\t\t\t@ 7 registers + 1 spare\n \n \t__INITDATA\n \n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0301-media-bcm2835-unicam-Select-MEDIA_CONTROLLER-and-VID.patch",
    "content": "From 37e99c4779131e96caf9083b68dad151ef8a9219 Mon Sep 17 00:00:00 2001\nFrom: Hristo Venev <hristo@venev.name>\nDate: Wed, 19 Aug 2020 17:02:22 +0300\nSubject: [PATCH] media: bcm2835: unicam: Select MEDIA_CONTROLLER and\n VIDEO_V4L2_SUBDEV_API\n\nThat is what almost all other drivers appear to be doing.\n\nSigned-off-by: Hristo Venev <hristo@venev.name>\n---\n drivers/media/platform/bcm2835/Kconfig | 4 +++-\n 1 file changed, 3 insertions(+), 1 deletion(-)\n\n--- a/drivers/media/platform/bcm2835/Kconfig\n+++ b/drivers/media/platform/bcm2835/Kconfig\n@@ -2,8 +2,10 @@\n \n config VIDEO_BCM2835_UNICAM\n \ttristate \"Broadcom BCM2835 Unicam video capture driver\"\n-\tdepends on VIDEO_V4L2 && VIDEO_V4L2_SUBDEV_API && MEDIA_CONTROLLER\n+\tdepends on VIDEO_V4L2\n \tdepends on ARCH_BCM2835 || COMPILE_TEST\n+\tselect VIDEO_V4L2_SUBDEV_API\n+\tselect MEDIA_CONTROLLER\n \tselect VIDEOBUF2_DMA_CONTIG\n \tselect V4L2_FWNODE\n \thelp\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0302-staging-media-rpivid-Select-MEDIA_CONTROLLER-and-MED.patch",
    "content": "From 09cc3528a822ee9d1f7be9e19af760b5e60f1c8f Mon Sep 17 00:00:00 2001\nFrom: Hristo Venev <hristo@venev.name>\nDate: Wed, 19 Aug 2020 17:05:53 +0300\nSubject: [PATCH] staging: media: rpivid: Select MEDIA_CONTROLLER and\n MEDIA_CONTROLLER_REQUEST_API\n\nMEDIA_CONTROLLER_REQUEST_API is a hidden option. If rpivid depends on it,\nthe user would need to first enable another driver that selects\nMEDIA_CONTROLLER_REQUEST_API, and only then rpivid would become available.\n\nBy selecting it instead of depending on it, it becomes possible to enable\nrpivid without having to enable other potentially unnecessary drivers.\n\nSigned-off-by: Hristo Venev <hristo@venev.name>\n---\n drivers/staging/media/rpivid/Kconfig | 4 ++--\n 1 file changed, 2 insertions(+), 2 deletions(-)\n\n--- a/drivers/staging/media/rpivid/Kconfig\n+++ b/drivers/staging/media/rpivid/Kconfig\n@@ -3,9 +3,9 @@\n config VIDEO_RPIVID\n \ttristate \"Rpi H265 driver\"\n \tdepends on VIDEO_DEV && VIDEO_V4L2\n-\tdepends on MEDIA_CONTROLLER\n \tdepends on OF\n-\tdepends on MEDIA_CONTROLLER_REQUEST_API\n+\tselect MEDIA_CONTROLLER\n+\tselect MEDIA_CONTROLLER_REQUEST_API\n \tselect VIDEOBUF2_DMA_CONTIG\n \tselect V4L2_MEM2MEM_DEV\n \thelp\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0303-media-bcm2835-unicam-Drop-WARN-on-uing-direct-cache-.patch",
    "content": "From b8f093d573b6de5ca22642c60abfe3f49fdfed6b Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Thu, 27 Aug 2020 16:30:26 +0100\nSubject: [PATCH] media: bcm2835-unicam: Drop WARN on uing direct cache\n alias\n\nPi 0&1 pass all ARM accesses through the VPU L2 cache, therefore\nthe dma-ranges property sets the cache alias bits to other\nthan the direct alias, hence this WARN was firing.\n\nIt was overprotective coding, so assume that everything is OK\nwith the dma-ranges, and remove the WARN.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n drivers/media/platform/bcm2835/bcm2835-unicam.c | 7 -------\n 1 file changed, 7 deletions(-)\n\n--- a/drivers/media/platform/bcm2835/bcm2835-unicam.c\n+++ b/drivers/media/platform/bcm2835/bcm2835-unicam.c\n@@ -709,13 +709,6 @@ static void unicam_wr_dma_addr(struct un\n {\n \tdma_addr_t endaddr = dmaaddr + buffer_size;\n \n-\t/*\n-\t * dmaaddr and endaddr should be a 32-bit address with the top two bits\n-\t * set to 0x3 to signify uncached access through the Videocore memory\n-\t * controller.\n-\t */\n-\tWARN_ON((dmaaddr >> 30) != 0x3 || (endaddr >> 30) != 0x3);\n-\n \tif (pad_id == IMAGE_PAD) {\n \t\treg_write(dev, UNICAM_IBSA0, dmaaddr);\n \t\treg_write(dev, UNICAM_IBEA0, endaddr);\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0304-media-i2c-tc358743-Only-allow-supported-pixel-fmts-i.patch",
    "content": "From d542ce00f99420cce4ccaa9cb79e3a216c5ae583 Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Fri, 10 Jul 2020 12:40:50 +0100\nSubject: [PATCH] media: i2c: tc358743: Only allow supported pixel fmts\n in set_fmt\n\nFix commit \"media: tc358743: Return an appropriate colorspace from\ntc358743_set_fmt\" to ensure that the format passed in to set_fmt\nis checked to be valid, and reset to the current format if not.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n drivers/media/i2c/tc358743.c | 6 ++++--\n 1 file changed, 4 insertions(+), 2 deletions(-)\n\n--- a/drivers/media/i2c/tc358743.c\n+++ b/drivers/media/i2c/tc358743.c\n@@ -1731,8 +1731,10 @@ static int tc358743_set_fmt(struct v4l2_\n \tu32 code = format->format.code; /* is overwritten by get_fmt */\n \tint ret = tc358743_get_fmt(sd, cfg, format);\n \n-\tformat->format.code = code;\n-\tformat->format.colorspace = tc358743_g_colorspace(code);\n+\tif (code == MEDIA_BUS_FMT_RGB888_1X24 ||\n+\t    code == MEDIA_BUS_FMT_UYVY8_1X16)\n+\t\tformat->format.code = code;\n+\tformat->format.colorspace = tc358743_g_colorspace(format->format.code);\n \n \tif (ret)\n \t\treturn ret;\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0305-media-i2c-ov9281-Add-support-for-8-bit-readout.patch",
    "content": "From 071d66e19764cb2019e95cb44d08a1848e688f12 Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Tue, 7 Jul 2020 18:29:10 +0100\nSubject: [PATCH] media: i2c: ov9281: Add support for 8 bit readout\n\nThe sensor supports 8 bit mode as well as 10bit, so add the\nrelevant code to allow selection of this.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n drivers/media/i2c/ov9281.c | 66 ++++++++++++++++++++++++++++++--------\n 1 file changed, 52 insertions(+), 14 deletions(-)\n\n--- a/drivers/media/i2c/ov9281.c\n+++ b/drivers/media/i2c/ov9281.c\n@@ -29,11 +29,12 @@\n \n #define OV9281_LINK_FREQ_400MHZ\t\t400000000\n #define OV9281_LANES\t\t\t2\n-#define OV9281_BITS_PER_SAMPLE\t\t10\n \n /* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */\n-#define OV9281_PIXEL_RATE\t\t(OV9281_LINK_FREQ_400MHZ * 2 * \\\n-\t\t\t\t\t OV9281_LANES / OV9281_BITS_PER_SAMPLE)\n+#define OV9281_PIXEL_RATE_10BIT\t\t(OV9281_LINK_FREQ_400MHZ * 2 * \\\n+\t\t\t\t\t OV9281_LANES / 10)\n+#define OV9281_PIXEL_RATE_8BIT\t\t(OV9281_LINK_FREQ_400MHZ * 2 * \\\n+\t\t\t\t\t OV9281_LANES / 8)\n #define OV9281_XVCLK_FREQ\t\t24000000\n \n #define CHIP_ID\t\t\t\t0x9281\n@@ -122,24 +123,25 @@ struct ov9281 {\n \tstruct v4l2_ctrl\t*digi_gain;\n \tstruct v4l2_ctrl\t*hblank;\n \tstruct v4l2_ctrl\t*vblank;\n+\tstruct v4l2_ctrl\t*pixel_rate;\n \tstruct v4l2_ctrl\t*test_pattern;\n \tstruct mutex\t\tmutex;\n \tbool\t\t\tstreaming;\n \tbool\t\t\tpower_on;\n \tconst struct ov9281_mode *cur_mode;\n+\tu32\t\t\tcode;\n };\n \n #define to_ov9281(sd) container_of(sd, struct ov9281, subdev)\n \n /*\n  * Xclk 24Mhz\n- * max_framerate 120fps\n+ * max_framerate 120fps for 10 bit, 144fps for 8 bit.\n  * mipi_datarate per lane 800Mbps\n  */\n static const struct regval ov9281_1280x800_regs[] = {\n \t{0x0103, 0x01},\n \t{0x0302, 0x32},\n-\t{0x030d, 0x50},\n \t{0x030e, 0x02},\n \t{0x3001, 0x00},\n \t{0x3004, 0x00},\n@@ -168,7 +170,6 @@ static const struct regval ov9281_1280x8\n \t{0x3620, 0x6f},\n \t{0x3632, 0x56},\n \t{0x3633, 0x78},\n-\t{0x3662, 0x05},\n \t{0x3666, 0x00},\n \t{0x366f, 0x5a},\n \t{0x3680, 0x84},\n@@ -235,6 +236,18 @@ static const struct regval ov9281_1280x8\n \t{REG_NULL, 0x00},\n };\n \n+static const struct regval op_10bit[] = {\n+\t{0x030d, 0x50},\n+\t{0x3662, 0x05},\n+\t{REG_NULL, 0x00},\n+};\n+\n+static const struct regval op_8bit[] = {\n+\t{0x030d, 0x60},\n+\t{0x3662, 0x07},\n+\t{REG_NULL, 0x00},\n+};\n+\n static const struct ov9281_mode supported_modes[] = {\n \t{\n \t\t.width = 1280,\n@@ -374,12 +387,13 @@ static int ov9281_set_fmt(struct v4l2_su\n {\n \tstruct ov9281 *ov9281 = to_ov9281(sd);\n \tconst struct ov9281_mode *mode;\n-\ts64 h_blank, vblank_def;\n+\ts64 h_blank, vblank_def, pixel_rate;\n \n \tmutex_lock(&ov9281->mutex);\n \n \tmode = ov9281_find_best_fit(fmt);\n-\tfmt->format.code = MEDIA_BUS_FMT_Y10_1X10;\n+\tif (fmt->format.code != MEDIA_BUS_FMT_Y8_1X8)\n+\t\tfmt->format.code = MEDIA_BUS_FMT_Y10_1X10;\n \tfmt->format.width = mode->width;\n \tfmt->format.height = mode->height;\n \tfmt->format.field = V4L2_FIELD_NONE;\n@@ -396,6 +410,7 @@ static int ov9281_set_fmt(struct v4l2_su\n \t\t*v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;\n \t} else {\n \t\tov9281->cur_mode = mode;\n+\t\tov9281->code = fmt->format.code;\n \t\th_blank = mode->hts_def - mode->width;\n \t\t__v4l2_ctrl_modify_range(ov9281->hblank, h_blank,\n \t\t\t\t\t h_blank, 1, h_blank);\n@@ -405,6 +420,11 @@ static int ov9281_set_fmt(struct v4l2_su\n \t\t\t\t\t OV9281_VTS_MAX - mode->height,\n \t\t\t\t\t 1, vblank_def);\n \t\t__v4l2_ctrl_s_ctrl(ov9281->vblank, vblank_def);\n+\n+\t\tpixel_rate = (fmt->format.code == MEDIA_BUS_FMT_Y10_1X10) ?\n+\t\t\tOV9281_PIXEL_RATE_10BIT : OV9281_PIXEL_RATE_8BIT;\n+\t\t__v4l2_ctrl_modify_range(ov9281->pixel_rate, pixel_rate,\n+\t\t\t\t\t pixel_rate, 1, pixel_rate);\n \t}\n \n \tmutex_unlock(&ov9281->mutex);\n@@ -425,7 +445,7 @@ static int ov9281_get_fmt(struct v4l2_su\n \t} else {\n \t\tfmt->format.width = mode->width;\n \t\tfmt->format.height = mode->height;\n-\t\tfmt->format.code = MEDIA_BUS_FMT_Y10_1X10;\n+\t\tfmt->format.code = ov9281->code;\n \t\tfmt->format.field = V4L2_FIELD_NONE;\n \t\tfmt->format.colorspace = V4L2_COLORSPACE_SRGB;\n \t\tfmt->format.ycbcr_enc =\n@@ -446,9 +466,16 @@ static int ov9281_enum_mbus_code(struct\n \t\t\t\t struct v4l2_subdev_pad_config *cfg,\n \t\t\t\t struct v4l2_subdev_mbus_code_enum *code)\n {\n-\tif (code->index)\n+\tswitch (code->index) {\n+\tdefault:\n \t\treturn -EINVAL;\n-\tcode->code = MEDIA_BUS_FMT_Y10_1X10;\n+\tcase 0:\n+\t\tcode->code = MEDIA_BUS_FMT_Y10_1X10;\n+\t\tbreak;\n+\tcase 1:\n+\t\tcode->code = MEDIA_BUS_FMT_Y8_1X8;\n+\t\tbreak;\n+\t}\n \n \treturn 0;\n }\n@@ -460,7 +487,8 @@ static int ov9281_enum_frame_sizes(struc\n \tif (fse->index >= ARRAY_SIZE(supported_modes))\n \t\treturn -EINVAL;\n \n-\tif (fse->code != MEDIA_BUS_FMT_Y10_1X10)\n+\tif (fse->code != MEDIA_BUS_FMT_Y10_1X10 &&\n+\t    fse->code != MEDIA_BUS_FMT_Y8_1X8)\n \t\treturn -EINVAL;\n \n \tfse->min_width  = supported_modes[fse->index].width;\n@@ -543,6 +571,13 @@ static int __ov9281_start_stream(struct\n \tif (ret)\n \t\treturn ret;\n \n+\tif (ov9281->code == MEDIA_BUS_FMT_Y10_1X10)\n+\t\tret = ov9281_write_array(ov9281->client, op_10bit);\n+\telse\n+\t\tret = ov9281_write_array(ov9281->client, op_8bit);\n+\tif (ret)\n+\t\treturn ret;\n+\n \t/* In case these controls are set before streaming */\n \tmutex_unlock(&ov9281->mutex);\n \tret = v4l2_ctrl_handler_setup(&ov9281->ctrl_handler);\n@@ -849,8 +884,11 @@ static int ov9281_initialize_controls(st\n \tif (ctrl)\n \t\tctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY;\n \n-\tv4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE,\n-\t\t\t  0, OV9281_PIXEL_RATE, 1, OV9281_PIXEL_RATE);\n+\tov9281->pixel_rate = v4l2_ctrl_new_std(handler, NULL,\n+\t\t\t\t\t       V4L2_CID_PIXEL_RATE,\n+\t\t\t\t\t       OV9281_PIXEL_RATE_10BIT,\n+\t\t\t\t\t       OV9281_PIXEL_RATE_10BIT, 1,\n+\t\t\t\t\t       OV9281_PIXEL_RATE_10BIT);\n \n \th_blank = mode->hts_def - mode->width;\n \tov9281->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0306-bcm2835-mmc-uninitialized_var-is-no-more.patch",
    "content": "From 99c87c4c80fb0dd24f6849d0846c0c4a418903a9 Mon Sep 17 00:00:00 2001\nFrom: popcornmix <popcornmix@gmail.com>\nDate: Thu, 3 Sep 2020 14:02:21 +0100\nSubject: [PATCH] bcm2835-mmc: uninitialized_var is no more\n\n---\n drivers/mmc/host/bcm2835-mmc.c | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/drivers/mmc/host/bcm2835-mmc.c\n+++ b/drivers/mmc/host/bcm2835-mmc.c\n@@ -367,7 +367,7 @@ static void bcm2835_bcm2835_mmc_read_blo\n \tunsigned long flags;\n \tsize_t blksize, len, chunk;\n \n-\tu32 uninitialized_var(scratch);\n+\tu32 scratch = 0;\n \tu8 *buf;\n \n \tblksize = host->data->blksz;\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0307-dwc_otg-whitelist_table-is-now-productlist_table.patch",
    "content": "From 1ecaa185ff343a783c147b17dd85482c507d2d9e Mon Sep 17 00:00:00 2001\nFrom: popcornmix <popcornmix@gmail.com>\nDate: Thu, 3 Sep 2020 14:02:41 +0100\nSubject: [PATCH] dwc_otg: whitelist_table is now productlist_table\n\n---\n drivers/usb/core/otg_productlist.h | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/drivers/usb/core/otg_productlist.h\n+++ b/drivers/usb/core/otg_productlist.h\n@@ -139,7 +139,7 @@ static int is_targeted(struct usb_device\n \t\t/* NOTE: can't use usb_match_id() since interface caches\n \t\t * aren't set up yet. this is cut/paste from that code.\n \t\t */\n-\t\tfor (id = whitelist_table; id->match_flags; id++) {\n+\t\tfor (id = productlist_table; id->match_flags; id++) {\n #ifdef DEBUG\n \t\t\tdev_dbg(&dev->dev,\n \t\t\t\t\"ID: V:%04x P:%04x DC:%04x SC:%04x PR:%04x \\n\",\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0308-vchiq_2835_arm-Implement-a-DMA-pool-for-small-bulk-t.patch",
    "content": "From afbc6c9f890bd3d877451138b2ffd5bd19bfdf61 Mon Sep 17 00:00:00 2001\nFrom: detule <ogjoneski@gmail.com>\nDate: Tue, 2 Oct 2018 04:10:08 -0400\nSubject: [PATCH] vchiq_2835_arm: Implement a DMA pool for small bulk\n transfers (#2699)\n\nDuring a bulk transfer we request a DMA allocation to hold the\nscatter-gather list.  Most of the time, this allocation is small\n(<< PAGE_SIZE), however it can be requested at a high enough frequency\nto cause fragmentation and/or stress the CMA allocator (think time\nspent in compaction here, or during allocations elsewhere).\n\nImplement a pool to serve up small DMA allocations, falling back\nto a coherent allocation if the request is greater than\nVCHIQ_DMA_POOL_SIZE.\n\nSigned-off-by: Oliver Gjoneski <ogjoneski@gmail.com>\n---\n .../interface/vchiq_arm/vchiq_2835_arm.c      | 36 ++++++++++++++++---\n 1 file changed, 32 insertions(+), 4 deletions(-)\n\n--- a/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_2835_arm.c\n+++ b/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_2835_arm.c\n@@ -7,6 +7,7 @@\n #include <linux/interrupt.h>\n #include <linux/pagemap.h>\n #include <linux/dma-mapping.h>\n+#include <linux/dmapool.h>\n #include <linux/io.h>\n #include <linux/platform_device.h>\n #include <linux/uaccess.h>\n@@ -29,6 +30,8 @@\n #define BELL0\t0x00\n #define BELL2\t0x08\n \n+#define VCHIQ_DMA_POOL_SIZE PAGE_SIZE\n+\n struct vchiq_2835_state {\n \tint inited;\n \tstruct vchiq_arm_state arm_state;\n@@ -38,6 +41,7 @@ struct vchiq_pagelist_info {\n \tstruct pagelist *pagelist;\n \tsize_t pagelist_buffer_size;\n \tdma_addr_t dma_addr;\n+\tbool is_from_pool;\n \tenum dma_data_direction dma_dir;\n \tunsigned int num_pages;\n \tunsigned int pages_need_release;\n@@ -58,6 +62,7 @@ static void __iomem *g_regs;\n  * of 32.\n  */\n static unsigned int g_cache_line_size = 32;\n+static struct dma_pool *g_dma_pool;\n static unsigned int g_use_36bit_addrs = 0;\n static unsigned int g_fragments_size;\n static char *g_fragments_base;\n@@ -182,6 +187,13 @@ int vchiq_platform_init(struct platform_\n \n \tg_dev = dev;\n \tg_dma_dev = dma_dev ?: dev;\n+\tg_dma_pool = dmam_pool_create(\"vchiq_scatter_pool\", dev,\n+\t\t\t\t      VCHIQ_DMA_POOL_SIZE, g_cache_line_size,\n+\t\t\t\t      0);\n+\tif (!g_dma_pool) {\n+\t\tdev_err(dev, \"failed to create dma pool\");\n+\t\treturn -ENOMEM;\n+\t}\n \n \tvchiq_log_info(vchiq_arm_log_level,\n \t\t\"vchiq_init - done (slots %pK, phys %pad)\",\n@@ -314,8 +326,14 @@ cleanup_pagelistinfo(struct vchiq_pageli\n \tif (pagelistinfo->pages_need_release)\n \t\tunpin_user_pages(pagelistinfo->pages, pagelistinfo->num_pages);\n \n-\tdma_free_coherent(g_dev, pagelistinfo->pagelist_buffer_size,\n-\t\t\t  pagelistinfo->pagelist, pagelistinfo->dma_addr);\n+\tif (pagelistinfo->is_from_pool) {\n+\t\tdma_pool_free(g_dma_pool, pagelistinfo->pagelist,\n+\t\t\t      pagelistinfo->dma_addr);\n+\t} else {\n+\t\tdma_free_coherent(g_dev, pagelistinfo->pagelist_buffer_size,\n+\t\t\t\t  pagelistinfo->pagelist,\n+\t\t\t\t  pagelistinfo->dma_addr);\n+\t}\n }\n \n /* There is a potential problem with partial cache lines (pages?)\n@@ -336,6 +354,7 @@ create_pagelist(char *buf, char __user *\n \tu32 *addrs;\n \tunsigned int num_pages, offset, i, k;\n \tint actual_pages;\n+\tbool is_from_pool;\n \tsize_t pagelist_size;\n \tstruct scatterlist *scatterlist, *sg;\n \tint dma_buffers;\n@@ -365,8 +384,16 @@ create_pagelist(char *buf, char __user *\n \t/* Allocate enough storage to hold the page pointers and the page\n \t * list\n \t */\n-\tpagelist = dma_alloc_coherent(g_dev, pagelist_size, &dma_addr,\n-\t\t\t\t      GFP_KERNEL);\n+\tif (pagelist_size > VCHIQ_DMA_POOL_SIZE) {\n+\t\tpagelist = dma_alloc_coherent(g_dev,\n+\t\t\t\t\t       pagelist_size,\n+\t\t\t\t\t       &dma_addr,\n+\t\t\t\t\t       GFP_KERNEL);\n+\t\tis_from_pool = false;\n+\t} else {\n+\t\tpagelist = dma_pool_alloc(g_dma_pool, GFP_KERNEL, &dma_addr);\n+\t\tis_from_pool = true;\n+\t}\n \n \tvchiq_log_trace(vchiq_arm_log_level, \"%s - %pK\", __func__, pagelist);\n \n@@ -387,6 +414,7 @@ create_pagelist(char *buf, char __user *\n \tpagelistinfo->pagelist = pagelist;\n \tpagelistinfo->pagelist_buffer_size = pagelist_size;\n \tpagelistinfo->dma_addr = dma_addr;\n+\tpagelistinfo->is_from_pool = is_from_pool;\n \tpagelistinfo->dma_dir =  (type == PAGELIST_WRITE) ?\n \t\t\t\t  DMA_TO_DEVICE : DMA_FROM_DEVICE;\n \tpagelistinfo->num_pages = num_pages;\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0309-include-firmware-Add-enum-for-RPI_FIRMWARE_FRAMEBUFF.patch",
    "content": "From 80025c80d57bdd265e47d1bfe62e68f54ca672d5 Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Thu, 3 Sep 2020 17:09:07 +0100\nSubject: [PATCH] include/firmware: Add enum for\n RPI_FIRMWARE_FRAMEBUFFER_GET_DISPLAY_ID\n\nUsed by audio and FKMS.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n include/soc/bcm2835/raspberrypi-firmware.h | 1 +\n 1 file changed, 1 insertion(+)\n\n--- a/include/soc/bcm2835/raspberrypi-firmware.h\n+++ b/include/soc/bcm2835/raspberrypi-firmware.h\n@@ -114,6 +114,7 @@ enum rpi_firmware_property_tag {\n \tRPI_FIRMWARE_FRAMEBUFFER_GET_TOUCHBUF =               0x0004000f,\n \tRPI_FIRMWARE_FRAMEBUFFER_GET_GPIOVIRTBUF =            0x00040010,\n \tRPI_FIRMWARE_FRAMEBUFFER_RELEASE =                    0x00048001,\n+\tRPI_FIRMWARE_FRAMEBUFFER_GET_DISPLAY_ID =             0x00040016,\n \tRPI_FIRMWARE_FRAMEBUFFER_SET_DISPLAY_NUM =            0x00048013,\n \tRPI_FIRMWARE_FRAMEBUFFER_GET_NUM_DISPLAYS =           0x00040013,\n \tRPI_FIRMWARE_FRAMEBUFFER_GET_DISPLAY_SETTINGS =       0x00040014,\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0310-vc4_hdmi-Remove-cec_available-flag-as-always-support.patch",
    "content": "From 8dda85398458dc330758ef5e1408d66995ffa068 Mon Sep 17 00:00:00 2001\nFrom: Dom Cobley <popcornmix@gmail.com>\nDate: Thu, 7 May 2020 18:16:09 +0100\nSubject: [PATCH] vc4_hdmi: Remove cec_available flag as always\n supported\n\nSigned-off-by: Dom Cobley <popcornmix@gmail.com>\n---\n drivers/gpu/drm/vc4/vc4_hdmi.c | 4 ----\n drivers/gpu/drm/vc4/vc4_hdmi.h | 3 ---\n 2 files changed, 7 deletions(-)\n\n--- a/drivers/gpu/drm/vc4/vc4_hdmi.c\n+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c\n@@ -1493,9 +1493,6 @@ static int vc4_hdmi_cec_init(struct vc4_\n \tu32 value;\n \tint ret;\n \n-\tif (!vc4_hdmi->variant->cec_available)\n-\t\treturn 0;\n-\n \tvc4_hdmi->cec_adap = cec_allocate_adapter(&vc4_hdmi_cec_adap_ops,\n \t\t\t\t\t\t  vc4_hdmi, \"vc4\",\n \t\t\t\t\t\t  CEC_CAP_DEFAULTS |\n@@ -1928,7 +1925,6 @@ static const struct vc4_hdmi_variant bcm\n \t.debugfs_name\t\t= \"hdmi_regs\",\n \t.card_name\t\t= \"vc4-hdmi\",\n \t.max_pixel_clock\t= 162000000,\n-\t.cec_available\t\t= true,\n \t.registers\t\t= vc4_hdmi_fields,\n \t.num_registers\t\t= ARRAY_SIZE(vc4_hdmi_fields),\n \n--- a/drivers/gpu/drm/vc4/vc4_hdmi.h\n+++ b/drivers/gpu/drm/vc4/vc4_hdmi.h\n@@ -43,9 +43,6 @@ struct vc4_hdmi_variant {\n \t/* Filename to expose the registers in debugfs */\n \tconst char *debugfs_name;\n \n-\t/* Set to true when the CEC support is available */\n-\tbool cec_available;\n-\n \t/* Maximum pixel clock supported by the controller (in Hz) */\n \tunsigned long long max_pixel_clock;\n \n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0311-drm-vc4-Adopt-the-dma-configuration-from-the-HVS-or-.patch",
    "content": "From d57ee5afedf0b1b9a9afb29357c484acda5a40af Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Tue, 19 May 2020 14:54:28 +0100\nSubject: [PATCH] drm/vc4: Adopt the dma configuration from the HVS or\n V3D component\n\nvc4_drv isn't necessarily under the /soc node in DT as it is a\nvirtual device, but it is the one that does the allocations.\nThe DMA addresses are consumed by primarily the HVS or V3D, and\nthose require VideoCore cache alias address mapping, and so will be\nunder /soc.\n\nDuring probe find the a suitable device node for HVS or V3D,\nand adopt the DMA configuration of that node.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n drivers/gpu/drm/vc4/vc4_drv.c | 18 ++++++++++++++++++\n 1 file changed, 18 insertions(+)\n\n--- a/drivers/gpu/drm/vc4/vc4_drv.c\n+++ b/drivers/gpu/drm/vc4/vc4_drv.c\n@@ -246,6 +246,14 @@ static void vc4_match_add_drivers(struct\n \t}\n }\n \n+const struct of_device_id vc4_dma_range_matches[] = {\n+\t{ .compatible = \"brcm,bcm2835-hvs\" },\n+\t{ .compatible = \"brcm,bcm2835-v3d\" },\n+\t{ .compatible = \"brcm,cygnus-v3d\" },\n+\t{ .compatible = \"brcm,vc4-v3d\" },\n+\t{}\n+};\n+\n static int vc4_drm_bind(struct device *dev)\n {\n \tstruct platform_device *pdev = to_platform_device(dev);\n@@ -263,6 +271,16 @@ static int vc4_drm_bind(struct device *d\n \t\tvc4_drm_driver.driver_features &= ~DRIVER_RENDER;\n \tof_node_put(node);\n \n+\tnode = of_find_matching_node_and_match(NULL, vc4_dma_range_matches,\n+\t\t\t\t\t       NULL);\n+\tif (node) {\n+\t\tret = of_dma_configure(dev, node, true);\n+\t\tof_node_put(node);\n+\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\t}\n+\n \tvc4 = devm_drm_dev_alloc(dev, &vc4_drm_driver, struct vc4_dev, base);\n \tif (IS_ERR(vc4))\n \t\treturn PTR_ERR(vc4);\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0313-vc4_hdmi-Set-HDMI_MAI_FMT.patch",
    "content": "From 80ba4d12d096a8f7855835ee54dc17d1e3a0d31a Mon Sep 17 00:00:00 2001\nFrom: popcornmix <popcornmix@gmail.com>\nDate: Tue, 10 Mar 2020 22:21:15 +0000\nSubject: [PATCH] vc4_hdmi: Set HDMI_MAI_FMT\n\nThe hardware uses this for generating the right audio\ndata island packets when using formats other than PCM\n\nSigned-off-by: Dom Cobley <popcornmix@gmail.com>\n---\n drivers/gpu/drm/vc4/vc4_hdmi.c | 48 ++++++++++++++++++++++++++++++++++\n drivers/gpu/drm/vc4/vc4_regs.h | 30 +++++++++++++++++++++\n 2 files changed, 78 insertions(+)\n\n--- a/drivers/gpu/drm/vc4/vc4_hdmi.c\n+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c\n@@ -991,6 +991,44 @@ static void vc4_hdmi_audio_shutdown(stru\n \tvc4_hdmi->audio.substream = NULL;\n }\n \n+static int sample_rate_to_mai_fmt(int samplerate)\n+{\n+\tswitch (samplerate) {\n+\tcase 8000:\n+\t\treturn VC4_HDMI_MAI_SAMPLE_RATE_8000;\n+\tcase 11025:\n+\t\treturn VC4_HDMI_MAI_SAMPLE_RATE_11025;\n+\tcase 12000:\n+\t\treturn VC4_HDMI_MAI_SAMPLE_RATE_12000;\n+\tcase 16000:\n+\t\treturn VC4_HDMI_MAI_SAMPLE_RATE_16000;\n+\tcase 22050:\n+\t\treturn VC4_HDMI_MAI_SAMPLE_RATE_22050;\n+\tcase 24000:\n+\t\treturn VC4_HDMI_MAI_SAMPLE_RATE_24000;\n+\tcase 32000:\n+\t\treturn VC4_HDMI_MAI_SAMPLE_RATE_32000;\n+\tcase 44100:\n+\t\treturn VC4_HDMI_MAI_SAMPLE_RATE_44100;\n+\tcase 48000:\n+\t\treturn VC4_HDMI_MAI_SAMPLE_RATE_48000;\n+\tcase 64000:\n+\t\treturn VC4_HDMI_MAI_SAMPLE_RATE_64000;\n+\tcase 88200:\n+\t\treturn VC4_HDMI_MAI_SAMPLE_RATE_88200;\n+\tcase 96000:\n+\t\treturn VC4_HDMI_MAI_SAMPLE_RATE_96000;\n+\tcase 128000:\n+\t\treturn VC4_HDMI_MAI_SAMPLE_RATE_128000;\n+\tcase 176400:\n+\t\treturn VC4_HDMI_MAI_SAMPLE_RATE_176400;\n+\tcase 192000:\n+\t\treturn VC4_HDMI_MAI_SAMPLE_RATE_192000;\n+\tdefault:\n+\t\treturn VC4_HDMI_MAI_SAMPLE_RATE_NOT_INDICATED;\n+\t}\n+}\n+\n /* HDMI audio codec callbacks */\n static int vc4_hdmi_audio_hw_params(struct snd_pcm_substream *substream,\n \t\t\t\t    struct snd_pcm_hw_params *params,\n@@ -1001,6 +1039,8 @@ static int vc4_hdmi_audio_hw_params(stru\n \tstruct device *dev = &vc4_hdmi->pdev->dev;\n \tu32 audio_packet_config, channel_mask;\n \tu32 channel_map;\n+\tu32 mai_audio_format;\n+\tu32 mai_sample_rate;\n \n \tif (substream != vc4_hdmi->audio.substream)\n \t\treturn -EINVAL;\n@@ -1021,6 +1061,14 @@ static int vc4_hdmi_audio_hw_params(stru\n \n \tvc4_hdmi_audio_set_mai_clock(vc4_hdmi);\n \n+\tmai_sample_rate = sample_rate_to_mai_fmt(vc4_hdmi->audio.samplerate);\n+\tmai_audio_format = VC4_HDMI_MAI_FORMAT_PCM;\n+\tHDMI_WRITE(HDMI_MAI_FMT,\n+\t\t   VC4_SET_FIELD(mai_sample_rate,\n+\t\t\t\t VC4_HDMI_MAI_FORMAT_SAMPLE_RATE) |\n+\t\t   VC4_SET_FIELD(mai_audio_format,\n+\t\t\t\t VC4_HDMI_MAI_FORMAT_AUDIO_FORMAT));\n+\n \t/* The B frame identifier should match the value used by alsa-lib (8) */\n \taudio_packet_config =\n \t\tVC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT |\n--- a/drivers/gpu/drm/vc4/vc4_regs.h\n+++ b/drivers/gpu/drm/vc4/vc4_regs.h\n@@ -516,6 +516,36 @@\n # define VC4_HDMI_AUDIO_PACKET_CEA_MASK_MASK\t\t\tVC4_MASK(7, 0)\n # define VC4_HDMI_AUDIO_PACKET_CEA_MASK_SHIFT\t\t\t0\n \n+# define VC4_HDMI_MAI_FORMAT_AUDIO_FORMAT_MASK\t\tVC4_MASK(23, 16)\n+# define VC4_HDMI_MAI_FORMAT_AUDIO_FORMAT_SHIFT\t\t16\n+\n+enum {\n+\tVC4_HDMI_MAI_FORMAT_PCM = 2,\n+\tVC4_HDMI_MAI_FORMAT_HBR = 200,\n+};\n+\n+# define VC4_HDMI_MAI_FORMAT_SAMPLE_RATE_MASK\t\tVC4_MASK(15, 8)\n+# define VC4_HDMI_MAI_FORMAT_SAMPLE_RATE_SHIFT\t\t8\n+\n+enum {\n+\tVC4_HDMI_MAI_SAMPLE_RATE_NOT_INDICATED = 0,\n+\tVC4_HDMI_MAI_SAMPLE_RATE_8000 = 1,\n+\tVC4_HDMI_MAI_SAMPLE_RATE_11025 = 2,\n+\tVC4_HDMI_MAI_SAMPLE_RATE_12000 = 3,\n+\tVC4_HDMI_MAI_SAMPLE_RATE_16000 = 4,\n+\tVC4_HDMI_MAI_SAMPLE_RATE_22050 = 5,\n+\tVC4_HDMI_MAI_SAMPLE_RATE_24000 = 6,\n+\tVC4_HDMI_MAI_SAMPLE_RATE_32000 = 7,\n+\tVC4_HDMI_MAI_SAMPLE_RATE_44100 = 8,\n+\tVC4_HDMI_MAI_SAMPLE_RATE_48000 = 9,\n+\tVC4_HDMI_MAI_SAMPLE_RATE_64000 = 10,\n+\tVC4_HDMI_MAI_SAMPLE_RATE_88200 = 11,\n+\tVC4_HDMI_MAI_SAMPLE_RATE_96000 = 12,\n+\tVC4_HDMI_MAI_SAMPLE_RATE_128000 = 13,\n+\tVC4_HDMI_MAI_SAMPLE_RATE_176400 = 14,\n+\tVC4_HDMI_MAI_SAMPLE_RATE_192000 = 15,\n+};\n+\n # define VC4_HDMI_RAM_PACKET_ENABLE\t\tBIT(16)\n \n /* When set, the CTS_PERIOD counts based on MAI bus sync pulse instead\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0314-drm-vc4-add-iec958-controls-to-vc4_hdmi.patch",
    "content": "From 29e5bf9305e98a57a895d6806fafa6e67f257fd8 Mon Sep 17 00:00:00 2001\nFrom: Matthias Reichl <hias@horus.com>\nDate: Tue, 17 Mar 2020 12:12:22 +0100\nSubject: [PATCH] drm/vc4: add iec958 controls to vc4_hdmi\n\nAlthough vc4 get an IEC958 formatted stream passed in from userspace\nthe driver needs the info from the channel status bits to properly\nset up the hardware, eg for HBR passthrough.\n\nAdd iec958 controls so the channel status bits can be passed in\nfrom userspace.\n\nSigned-off-by: Matthias Reichl <hias@horus.com>\n---\n drivers/gpu/drm/vc4/vc4_hdmi.c | 60 ++++++++++++++++++++++++++++++++++\n drivers/gpu/drm/vc4/vc4_hdmi.h |  2 ++\n 2 files changed, 62 insertions(+)\n\n--- a/drivers/gpu/drm/vc4/vc4_hdmi.c\n+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c\n@@ -44,6 +44,7 @@\n #include <linux/pm_runtime.h>\n #include <linux/rational.h>\n #include <linux/reset.h>\n+#include <sound/asoundef.h>\n #include <sound/dmaengine_pcm.h>\n #include <sound/pcm_drm_eld.h>\n #include <sound/pcm_params.h>\n@@ -1182,6 +1183,47 @@ static int vc4_hdmi_audio_eld_ctl_get(st\n \treturn 0;\n }\n \n+static int vc4_spdif_info(struct snd_kcontrol *kcontrol,\n+\t\t\t  struct snd_ctl_elem_info *uinfo)\n+{\n+\tuinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;\n+\tuinfo->count = 1;\n+\treturn 0;\n+}\n+\n+static int vc4_spdif_playback_get(struct snd_kcontrol *kcontrol,\n+\t\t\t\t  struct snd_ctl_elem_value *ucontrol)\n+{\n+\tstruct snd_soc_component *component = snd_kcontrol_chip(kcontrol);\n+\tstruct vc4_hdmi *vc4_hdmi = snd_component_to_hdmi(component);\n+\n+\tmemcpy(ucontrol->value.iec958.status, vc4_hdmi->audio.iec_status,\n+\t       sizeof(vc4_hdmi->audio.iec_status));\n+\n+\treturn 0;\n+}\n+\n+static int vc4_spdif_playback_put(struct snd_kcontrol *kcontrol,\n+\t\t\t\t  struct snd_ctl_elem_value *ucontrol)\n+{\n+\tstruct snd_soc_component *component = snd_kcontrol_chip(kcontrol);\n+\tstruct vc4_hdmi *vc4_hdmi = snd_component_to_hdmi(component);\n+\n+\tmemcpy(vc4_hdmi->audio.iec_status, ucontrol->value.iec958.status,\n+\t       sizeof(vc4_hdmi->audio.iec_status));\n+\n+\treturn 0;\n+}\n+\n+static int vc4_spdif_mask_get(struct snd_kcontrol *kcontrol,\n+\t\t\t      struct snd_ctl_elem_value *ucontrol)\n+{\n+\tmemset(ucontrol->value.iec958.status, 0xff,\n+\t       sizeof_field(struct vc4_hdmi_audio, iec_status));\n+\n+\treturn 0;\n+}\n+\n static const struct snd_kcontrol_new vc4_hdmi_audio_controls[] = {\n \t{\n \t\t.access = SNDRV_CTL_ELEM_ACCESS_READ |\n@@ -1191,6 +1233,19 @@ static const struct snd_kcontrol_new vc4\n \t\t.info = vc4_hdmi_audio_eld_ctl_info,\n \t\t.get = vc4_hdmi_audio_eld_ctl_get,\n \t},\n+\t{\n+\t\t.iface =   SNDRV_CTL_ELEM_IFACE_MIXER,\n+\t\t.name =    SNDRV_CTL_NAME_IEC958(\"\", PLAYBACK, DEFAULT),\n+\t\t.info =    vc4_spdif_info,\n+\t\t.get =     vc4_spdif_playback_get,\n+\t\t.put =     vc4_spdif_playback_put,\n+\t},\n+\t{\n+\t\t.iface =   SNDRV_CTL_ELEM_IFACE_MIXER,\n+\t\t.name =    SNDRV_CTL_NAME_IEC958(\"\", PLAYBACK, MASK),\n+\t\t.info =    vc4_spdif_info,\n+\t\t.get =     vc4_spdif_mask_get,\n+\t},\n };\n \n static const struct snd_soc_dapm_widget vc4_hdmi_audio_widgets[] = {\n@@ -1311,6 +1366,11 @@ static int vc4_hdmi_audio_init(struct vc\n \tvc4_hdmi->audio.dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;\n \tvc4_hdmi->audio.dma_data.maxburst = 2;\n \n+\tvc4_hdmi->audio.iec_status[0] = IEC958_AES0_CON_NOT_COPYRIGHT;\n+\tvc4_hdmi->audio.iec_status[1] =\n+\t\tIEC958_AES1_CON_ORIGINAL | IEC958_AES1_CON_PCM_CODER;\n+\tvc4_hdmi->audio.iec_status[3] = IEC958_AES3_CON_FS_48000;\n+\n \tret = devm_snd_dmaengine_pcm_register(dev, &pcm_conf, 0);\n \tif (ret) {\n \t\tdev_err(dev, \"Could not register PCM component: %d\\n\", ret);\n--- a/drivers/gpu/drm/vc4/vc4_hdmi.h\n+++ b/drivers/gpu/drm/vc4/vc4_hdmi.h\n@@ -107,6 +107,8 @@ struct vc4_hdmi_audio {\n \tstruct snd_pcm_substream *substream;\n \n \tbool streaming;\n+\n+\tunsigned char iec_status[4];\n };\n \n /* General HDMI hardware state. */\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0315-drm-vc4-move-setup-from-hw_params-to-prepare.patch",
    "content": "From 7b6cfdfc74c7e9c00060a0c4146a6358b261f7db Mon Sep 17 00:00:00 2001\nFrom: Matthias Reichl <hias@horus.com>\nDate: Thu, 19 Mar 2020 20:00:35 +0100\nSubject: [PATCH] drm/vc4: move setup from hw_params to prepare\n\nConfiguring HDMI audio registers in prepare allows us to take\nIEC958 bits into account which are set by the alsa hook after\nthe hw_params call.\n\nSigned-off-by: Matthias Reichl <hias@horus.com>\n---\n drivers/gpu/drm/vc4/vc4_hdmi.c | 20 +++++++++++---------\n 1 file changed, 11 insertions(+), 9 deletions(-)\n\n--- a/drivers/gpu/drm/vc4/vc4_hdmi.c\n+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c\n@@ -1031,9 +1031,8 @@ static int sample_rate_to_mai_fmt(int sa\n }\n \n /* HDMI audio codec callbacks */\n-static int vc4_hdmi_audio_hw_params(struct snd_pcm_substream *substream,\n-\t\t\t\t    struct snd_pcm_hw_params *params,\n-\t\t\t\t    struct snd_soc_dai *dai)\n+static int vc4_hdmi_audio_prepare(struct snd_pcm_substream *substream,\n+\t\t\t\t  struct snd_soc_dai *dai)\n {\n \tstruct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai);\n \tstruct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;\n@@ -1046,12 +1045,15 @@ static int vc4_hdmi_audio_hw_params(stru\n \tif (substream != vc4_hdmi->audio.substream)\n \t\treturn -EINVAL;\n \n-\tdev_dbg(dev, \"%s: %u Hz, %d bit, %d channels\\n\", __func__,\n-\t\tparams_rate(params), params_width(params),\n-\t\tparams_channels(params));\n+\tdev_dbg(dev, \"%s: %u Hz, %d bit, %d channels AES0=%02x\\n\",\n+\t\t__func__,\n+\t\tsubstream->runtime->rate,\n+\t\tsnd_pcm_format_width(substream->runtime->format),\n+\t\tsubstream->runtime->channels,\n+\t\tvc4_hdmi->audio.iec_status[0]);\n \n-\tvc4_hdmi->audio.channels = params_channels(params);\n-\tvc4_hdmi->audio.samplerate = params_rate(params);\n+\tvc4_hdmi->audio.channels = substream->runtime->channels;\n+\tvc4_hdmi->audio.samplerate = substream->runtime->rate;\n \n \tHDMI_WRITE(HDMI_MAI_CTL,\n \t\t   VC4_HD_MAI_CTL_RESET |\n@@ -1273,7 +1275,7 @@ static const struct snd_soc_component_dr\n static const struct snd_soc_dai_ops vc4_hdmi_audio_dai_ops = {\n \t.startup = vc4_hdmi_audio_startup,\n \t.shutdown = vc4_hdmi_audio_shutdown,\n-\t.hw_params = vc4_hdmi_audio_hw_params,\n+\t.prepare = vc4_hdmi_audio_prepare,\n \t.set_fmt = vc4_hdmi_audio_set_fmt,\n \t.trigger = vc4_hdmi_audio_trigger,\n };\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0316-drm-vc4-enable-HBR-MAI-format-on-HBR-streams.patch",
    "content": "From 465b5e6889b1af1c9c061751a0ee234a27644030 Mon Sep 17 00:00:00 2001\nFrom: Dom Cobley <popcornmix@gmail.com>\nDate: Fri, 10 Jul 2020 11:51:16 +0100\nSubject: [PATCH] drm/vc4: enable HBR MAI format on HBR streams\n\nSigned-off-by: Matthias Reichl <hias@horus.com>\n---\n drivers/gpu/drm/vc4/vc4_hdmi.c | 6 +++++-\n 1 file changed, 5 insertions(+), 1 deletion(-)\n\n--- a/drivers/gpu/drm/vc4/vc4_hdmi.c\n+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c\n@@ -1065,7 +1065,11 @@ static int vc4_hdmi_audio_prepare(struct\n \tvc4_hdmi_audio_set_mai_clock(vc4_hdmi);\n \n \tmai_sample_rate = sample_rate_to_mai_fmt(vc4_hdmi->audio.samplerate);\n-\tmai_audio_format = VC4_HDMI_MAI_FORMAT_PCM;\n+\tif (vc4_hdmi->audio.iec_status[0] & IEC958_AES0_NONAUDIO &&\n+\t    vc4_hdmi->audio.channels == 8)\n+\t\tmai_audio_format = VC4_HDMI_MAI_FORMAT_HBR;\n+\telse\n+\t\tmai_audio_format = VC4_HDMI_MAI_FORMAT_PCM;\n \tHDMI_WRITE(HDMI_MAI_FMT,\n \t\t   VC4_SET_FIELD(mai_sample_rate,\n \t\t\t\t VC4_HDMI_MAI_FORMAT_SAMPLE_RATE) |\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0317-vc4_hdmi-Remove-firmware-logic-for-MAI-threshold-set.patch",
    "content": "From 3c398513990aa0edc5b9ebfbdd2395623562c6e4 Mon Sep 17 00:00:00 2001\nFrom: Dom Cobley <popcornmix@gmail.com>\nDate: Thu, 25 Jun 2020 18:48:40 +0100\nSubject: [PATCH] vc4_hdmi: Remove firmware logic for MAI threshold\n setting\n\nThis was a workaround for bugs in hardware on earlier Pi models\nand wasn't totally successful.\n\nIt makes audio quality worse on a Pi4 at the higher sample rates\n\nSigned-off-by: Dom Cobley <popcornmix@gmail.com>\n---\n drivers/gpu/drm/vc4/vc4_hdmi.c | 22 ++++++----------------\n 1 file changed, 6 insertions(+), 16 deletions(-)\n\n--- a/drivers/gpu/drm/vc4/vc4_hdmi.c\n+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c\n@@ -1086,22 +1086,12 @@ static int vc4_hdmi_audio_prepare(struct\n \taudio_packet_config |= VC4_SET_FIELD(channel_mask,\n \t\t\t\t\t     VC4_HDMI_AUDIO_PACKET_CEA_MASK);\n \n-\t/* Set the MAI threshold.  This logic mimics the firmware's. */\n-\tif (vc4_hdmi->audio.samplerate > 96000) {\n-\t\tHDMI_WRITE(HDMI_MAI_THR,\n-\t\t\t   VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQHIGH) |\n-\t\t\t   VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQLOW));\n-\t} else if (vc4_hdmi->audio.samplerate > 48000) {\n-\t\tHDMI_WRITE(HDMI_MAI_THR,\n-\t\t\t   VC4_SET_FIELD(0x14, VC4_HD_MAI_THR_DREQHIGH) |\n-\t\t\t   VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQLOW));\n-\t} else {\n-\t\tHDMI_WRITE(HDMI_MAI_THR,\n-\t\t\t   VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICHIGH) |\n-\t\t\t   VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICLOW) |\n-\t\t\t   VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQHIGH) |\n-\t\t\t   VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQLOW));\n-\t}\n+\t/* Set the MAI threshold */\n+\tHDMI_WRITE(HDMI_MAI_THR,\n+\t\t   VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICHIGH) |\n+\t\t   VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICLOW) |\n+\t\t   VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQHIGH) |\n+\t\t   VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQLOW));\n \n \tHDMI_WRITE(HDMI_MAI_CONFIG,\n \t\t   VC4_HDMI_MAI_CONFIG_BIT_REVERSE |\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0318-vc_hdmi-Set-VC4_HDMI_MAI_CONFIG_FORMAT_REVERSE.patch",
    "content": "From f4a590c59a65381a0b9aa045e5fc493b3dbb5945 Mon Sep 17 00:00:00 2001\nFrom: Dom Cobley <popcornmix@gmail.com>\nDate: Tue, 30 Jun 2020 11:23:49 +0100\nSubject: [PATCH] vc_hdmi: Set VC4_HDMI_MAI_CONFIG_FORMAT_REVERSE\n\nWithout this bit set, HDMI_MAI_FORMAT doesn't pick up\nthe format and samplerate from DVP_CFG_MAI0_FMT and you\ncan't get HDMI_HDMI_13_AUDIO_STATUS_1 to indicate HBR mode\n\nSigned-off-by: Dom Cobley <popcornmix@gmail.com>\n---\n drivers/gpu/drm/vc4/vc4_hdmi.c | 1 +\n 1 file changed, 1 insertion(+)\n\n--- a/drivers/gpu/drm/vc4/vc4_hdmi.c\n+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c\n@@ -1095,6 +1095,7 @@ static int vc4_hdmi_audio_prepare(struct\n \n \tHDMI_WRITE(HDMI_MAI_CONFIG,\n \t\t   VC4_HDMI_MAI_CONFIG_BIT_REVERSE |\n+\t\t   VC4_HDMI_MAI_CONFIG_FORMAT_REVERSE |\n \t\t   VC4_SET_FIELD(channel_mask, VC4_HDMI_MAI_CHANNEL_MASK));\n \n \tchannel_map = vc4_hdmi->variant->channel_map(vc4_hdmi, channel_mask);\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0319-drm-vc4-Add-support-for-DRM_FORMAT_P030-to-vc4-plane.patch",
    "content": "From 286cf26ca3f6628a82c8c37e7059585c8389b82a Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Fri, 24 Jan 2020 14:25:41 +0000\nSubject: [PATCH] drm/vc4: Add support for DRM_FORMAT_P030 to vc4\n planes\n\nThis currently doesn't handle non-zero source rectangles correctly,\nbut add support for DRM_FORMAT_P030 with DRM_FORMAT_MOD_BROADCOM_SAND128\nmodifier to planes when running on HVS5.\n\nWIP still for source cropping SAND/P030 formats\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n drivers/gpu/drm/vc4/vc4_plane.c | 79 ++++++++++++++++++++++++---------\n 1 file changed, 57 insertions(+), 22 deletions(-)\n\n--- a/drivers/gpu/drm/vc4/vc4_plane.c\n+++ b/drivers/gpu/drm/vc4/vc4_plane.c\n@@ -33,6 +33,7 @@ static const struct hvs_format {\n \tu32 hvs; /* HVS_FORMAT_* */\n \tu32 pixel_order;\n \tu32 pixel_order_hvs5;\n+\tbool hvs5_only;\n } hvs_formats[] = {\n \t{\n \t\t.drm = DRM_FORMAT_XRGB8888,\n@@ -128,6 +129,12 @@ static const struct hvs_format {\n \t\t.hvs = HVS_PIXEL_FORMAT_YCBCR_YUV422_2PLANE,\n \t\t.pixel_order = HVS_PIXEL_ORDER_XYCRCB,\n \t},\n+\t{\n+\t\t.drm = DRM_FORMAT_P030,\n+\t\t.hvs = HVS_PIXEL_FORMAT_YCBCR_10BIT,\n+\t\t.pixel_order = HVS_PIXEL_ORDER_XYCBCR,\n+\t\t.hvs5_only = true,\n+\t},\n };\n \n static const struct hvs_format *vc4_get_hvs_format(u32 drm_format)\n@@ -769,27 +776,33 @@ static int vc4_plane_mode_set(struct drm\n \t\tuint32_t param = fourcc_mod_broadcom_param(fb->modifier);\n \t\tu32 tile_w, tile, x_off, pix_per_tile;\n \n-\t\thvs_format = HVS_PIXEL_FORMAT_H264;\n-\n-\t\tswitch (base_format_mod) {\n-\t\tcase DRM_FORMAT_MOD_BROADCOM_SAND64:\n-\t\t\ttiling = SCALER_CTL0_TILING_64B;\n-\t\t\ttile_w = 64;\n-\t\t\tbreak;\n-\t\tcase DRM_FORMAT_MOD_BROADCOM_SAND128:\n+\t\tif (fb->format->format == DRM_FORMAT_P030) {\n+\t\t\thvs_format = HVS_PIXEL_FORMAT_YCBCR_10BIT;\n \t\t\ttiling = SCALER_CTL0_TILING_128B;\n-\t\t\ttile_w = 128;\n-\t\t\tbreak;\n-\t\tcase DRM_FORMAT_MOD_BROADCOM_SAND256:\n-\t\t\ttiling = SCALER_CTL0_TILING_256B_OR_T;\n-\t\t\ttile_w = 256;\n-\t\t\tbreak;\n-\t\tdefault:\n-\t\t\tbreak;\n-\t\t}\n+\t\t\ttile_w = 96;\n+\t\t} else {\n+\t\t\thvs_format = HVS_PIXEL_FORMAT_H264;\n \n+\t\t\tswitch (base_format_mod) {\n+\t\t\tcase DRM_FORMAT_MOD_BROADCOM_SAND64:\n+\t\t\t\ttiling = SCALER_CTL0_TILING_64B;\n+\t\t\t\ttile_w = 64;\n+\t\t\t\tbreak;\n+\t\t\tcase DRM_FORMAT_MOD_BROADCOM_SAND128:\n+\t\t\t\ttiling = SCALER_CTL0_TILING_128B;\n+\t\t\t\ttile_w = 128;\n+\t\t\t\tbreak;\n+\t\t\tcase DRM_FORMAT_MOD_BROADCOM_SAND256:\n+\t\t\t\ttiling = SCALER_CTL0_TILING_256B_OR_T;\n+\t\t\t\ttile_w = 256;\n+\t\t\t\tbreak;\n+\t\t\tdefault:\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t}\n \t\tif (param > SCALER_TILE_HEIGHT_MASK) {\n-\t\t\tDRM_DEBUG_KMS(\"SAND height too large (%d)\\n\", param);\n+\t\t\tDRM_DEBUG_KMS(\"SAND height too large (%d)\\n\",\n+\t\t\t\t      param);\n \t\t\treturn -EINVAL;\n \t\t}\n \n@@ -799,6 +812,13 @@ static int vc4_plane_mode_set(struct drm\n \n \t\t/* Adjust the base pointer to the first pixel to be scanned\n \t\t * out.\n+\t\t *\n+\t\t * For P030, y_ptr [31:4] is the 128bit word for the start pixel\n+\t\t * y_ptr [3:0] is the pixel (0-11) contained within that 128bit\n+\t\t * word that should be taken as the first pixel.\n+\t\t * Ditto uv_ptr [31:4] vs [3:0], however [3:0] contains the\n+\t\t * element within the 128bit word, eg for pixel 3 the value\n+\t\t * should be 6.\n \t\t */\n \t\tfor (i = 0; i < num_planes; i++) {\n \t\t\tvc4_state->offsets[i] += param * tile_w * tile;\n@@ -960,7 +980,8 @@ static int vc4_plane_mode_set(struct drm\n \n \t/* Pitch word 1/2 */\n \tfor (i = 1; i < num_planes; i++) {\n-\t\tif (hvs_format != HVS_PIXEL_FORMAT_H264) {\n+\t\tif (hvs_format != HVS_PIXEL_FORMAT_H264 &&\n+\t\t    hvs_format != HVS_PIXEL_FORMAT_YCBCR_10BIT) {\n \t\t\tvc4_dlist_write(vc4_state,\n \t\t\t\t\tVC4_SET_FIELD(fb->pitches[i],\n \t\t\t\t\t\t      SCALER_SRC_PITCH));\n@@ -1320,6 +1341,13 @@ static bool vc4_format_mod_supported(str\n \t\tdefault:\n \t\t\treturn false;\n \t\t}\n+\tcase DRM_FORMAT_P030:\n+\t\tswitch (fourcc_mod_broadcom_mod(modifier)) {\n+\t\tcase DRM_FORMAT_MOD_BROADCOM_SAND128:\n+\t\t\treturn true;\n+\t\tdefault:\n+\t\t\treturn false;\n+\t\t}\n \tcase DRM_FORMAT_RGBX1010102:\n \tcase DRM_FORMAT_BGRX1010102:\n \tcase DRM_FORMAT_RGBA1010102:\n@@ -1352,8 +1380,11 @@ struct drm_plane *vc4_plane_init(struct\n \tstruct drm_plane *plane = NULL;\n \tstruct vc4_plane *vc4_plane;\n \tu32 formats[ARRAY_SIZE(hvs_formats)];\n+\tint num_formats = 0;\n \tint ret = 0;\n \tunsigned i;\n+\tbool hvs5 = of_device_is_compatible(dev->dev->of_node,\n+\t\t\t\t\t    \"brcm,bcm2711-vc5\");\n \tstatic const uint64_t modifiers[] = {\n \t\tDRM_FORMAT_MOD_BROADCOM_VC4_T_TILED,\n \t\tDRM_FORMAT_MOD_BROADCOM_SAND128,\n@@ -1368,13 +1399,17 @@ struct drm_plane *vc4_plane_init(struct\n \tif (!vc4_plane)\n \t\treturn ERR_PTR(-ENOMEM);\n \n-\tfor (i = 0; i < ARRAY_SIZE(hvs_formats); i++)\n-\t\tformats[i] = hvs_formats[i].drm;\n+\tfor (i = 0; i < ARRAY_SIZE(hvs_formats); i++) {\n+\t\tif (!hvs_formats[i].hvs5_only || hvs5) {\n+\t\t\tformats[num_formats] = hvs_formats[i].drm;\n+\t\t\tnum_formats++;\n+\t\t}\n+\t}\n \n \tplane = &vc4_plane->base;\n \tret = drm_universal_plane_init(dev, plane, 0,\n \t\t\t\t       &vc4_plane_funcs,\n-\t\t\t\t       formats, ARRAY_SIZE(formats),\n+\t\t\t\t       formats, num_formats,\n \t\t\t\t       modifiers, type, NULL);\n \tif (ret)\n \t\treturn ERR_PTR(ret);\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0320-drm-vc4-Add-support-for-YUV-color-encodings-and-rang.patch",
    "content": "From 9582109f14a5e357c6287b5ab658293e8359fa47 Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.org>\nDate: Tue, 17 Sep 2019 18:28:17 +0100\nSubject: [PATCH] drm/vc4: Add support for YUV color encodings and\n ranges\n\nThe BT601/BT709 color encoding and limited vs full\nrange properties were not being exposed, defaulting\nalways to BT601 limited range.\n\nExpose the parameters and set the registers appropriately.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>\n---\n drivers/gpu/drm/vc4/vc4_plane.c | 72 +++++++++++++++++++++++++++++++--\n drivers/gpu/drm/vc4/vc4_regs.h  |  3 ++\n 2 files changed, 72 insertions(+), 3 deletions(-)\n\n--- a/drivers/gpu/drm/vc4/vc4_plane.c\n+++ b/drivers/gpu/drm/vc4/vc4_plane.c\n@@ -628,6 +628,53 @@ static int vc4_plane_allocate_lbm(struct\n \treturn 0;\n }\n \n+/* The colorspace conversion matrices are held in 3 entries in the dlist.\n+ * Create an array of them, with entries for each full and limited mode, and\n+ * each supported colorspace.\n+ */\n+#define VC4_LIMITED_RANGE\t0\n+#define VC4_FULL_RANGE\t\t1\n+\n+static const u32 colorspace_coeffs[2][DRM_COLOR_ENCODING_MAX][3] = {\n+\t{\n+\t\t/* Limited range */\n+\t\t{\n+\t\t\t/* BT601 */\n+\t\t\tSCALER_CSC0_ITR_R_601_5,\n+\t\t\tSCALER_CSC1_ITR_R_601_5,\n+\t\t\tSCALER_CSC2_ITR_R_601_5,\n+\t\t}, {\n+\t\t\t/* BT709 */\n+\t\t\tSCALER_CSC0_ITR_R_709_3,\n+\t\t\tSCALER_CSC1_ITR_R_709_3,\n+\t\t\tSCALER_CSC2_ITR_R_709_3,\n+\t\t}, {\n+\t\t\t/* BT2020. Not supported yet - copy 601 */\n+\t\t\tSCALER_CSC0_ITR_R_601_5,\n+\t\t\tSCALER_CSC1_ITR_R_601_5,\n+\t\t\tSCALER_CSC2_ITR_R_601_5,\n+\t\t}\n+\t}, {\n+\t\t/* Full range */\n+\t\t{\n+\t\t\t/* JFIF */\n+\t\t\tSCALER_CSC0_JPEG_JFIF,\n+\t\t\tSCALER_CSC1_JPEG_JFIF,\n+\t\t\tSCALER_CSC2_JPEG_JFIF,\n+\t\t}, {\n+\t\t\t/* BT709 */\n+\t\t\tSCALER_CSC0_ITR_R_709_3_FR,\n+\t\t\tSCALER_CSC1_ITR_R_709_3_FR,\n+\t\t\tSCALER_CSC2_ITR_R_709_3_FR,\n+\t\t}, {\n+\t\t\t/* BT2020. Not supported yet - copy JFIF */\n+\t\t\tSCALER_CSC0_JPEG_JFIF,\n+\t\t\tSCALER_CSC1_JPEG_JFIF,\n+\t\t\tSCALER_CSC2_JPEG_JFIF,\n+\t\t}\n+\t}\n+};\n+\n /* Writes out a full display list for an active plane to the plane's\n  * private dlist state.\n  */\n@@ -992,9 +1039,20 @@ static int vc4_plane_mode_set(struct drm\n \n \t/* Colorspace conversion words */\n \tif (vc4_state->is_yuv) {\n-\t\tvc4_dlist_write(vc4_state, SCALER_CSC0_ITR_R_601_5);\n-\t\tvc4_dlist_write(vc4_state, SCALER_CSC1_ITR_R_601_5);\n-\t\tvc4_dlist_write(vc4_state, SCALER_CSC2_ITR_R_601_5);\n+\t\tenum drm_color_encoding color_encoding = state->color_encoding;\n+\t\tenum drm_color_range color_range = state->color_range;\n+\t\tconst u32 *ccm;\n+\n+\t\tif (color_encoding >= DRM_COLOR_ENCODING_MAX)\n+\t\t\tcolor_encoding = DRM_COLOR_YCBCR_BT601;\n+\t\tif (color_range >= DRM_COLOR_RANGE_MAX)\n+\t\t\tcolor_range = DRM_COLOR_YCBCR_LIMITED_RANGE;\n+\n+\t\tccm = colorspace_coeffs[color_range][color_encoding];\n+\n+\t\tvc4_dlist_write(vc4_state, ccm[0]);\n+\t\tvc4_dlist_write(vc4_state, ccm[1]);\n+\t\tvc4_dlist_write(vc4_state, ccm[2]);\n \t}\n \n \tvc4_state->lbm_offset = 0;\n@@ -1423,6 +1481,14 @@ struct drm_plane *vc4_plane_init(struct\n \t\t\t\t\t   DRM_MODE_REFLECT_X |\n \t\t\t\t\t   DRM_MODE_REFLECT_Y);\n \n+\tdrm_plane_create_color_properties(plane,\n+\t\t\t\t\t  BIT(DRM_COLOR_YCBCR_BT601) |\n+\t\t\t\t\t  BIT(DRM_COLOR_YCBCR_BT709),\n+\t\t\t\t\t  BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) |\n+\t\t\t\t\t  BIT(DRM_COLOR_YCBCR_FULL_RANGE),\n+\t\t\t\t\t  DRM_COLOR_YCBCR_BT709,\n+\t\t\t\t\t  DRM_COLOR_YCBCR_LIMITED_RANGE);\n+\n \treturn plane;\n }\n \n--- a/drivers/gpu/drm/vc4/vc4_regs.h\n+++ b/drivers/gpu/drm/vc4/vc4_regs.h\n@@ -976,6 +976,7 @@ enum hvs_pixel_format {\n #define SCALER_CSC0_ITR_R_601_5\t\t\t0x00f00000\n #define SCALER_CSC0_ITR_R_709_3\t\t\t0x00f00000\n #define SCALER_CSC0_JPEG_JFIF\t\t\t0x00000000\n+#define SCALER_CSC0_ITR_R_709_3_FR\t\t0x00000000\n \n /* S2.8 contribution of Cb to Green */\n #define SCALER_CSC1_COEF_CB_GRN_MASK\t\tVC4_MASK(31, 22)\n@@ -992,6 +993,7 @@ enum hvs_pixel_format {\n #define SCALER_CSC1_ITR_R_601_5\t\t\t0xe73304a8\n #define SCALER_CSC1_ITR_R_709_3\t\t\t0xf2b784a8\n #define SCALER_CSC1_JPEG_JFIF\t\t\t0xea34a400\n+#define SCALER_CSC1_ITR_R_709_3_FR\t\t0xe23d0400\n \n /* S2.8 contribution of Cb to Red */\n #define SCALER_CSC2_COEF_CB_RED_MASK\t\tVC4_MASK(29, 20)\n@@ -1005,6 +1007,7 @@ enum hvs_pixel_format {\n #define SCALER_CSC2_ITR_R_601_5\t\t\t0x00066204\n #define SCALER_CSC2_ITR_R_709_3\t\t\t0x00072a1c\n #define SCALER_CSC2_JPEG_JFIF\t\t\t0x000599c5\n+#define SCALER_CSC2_ITR_R_709_3_FR\t\t0x00064ddb\n \n #define SCALER_TPZ0_VERT_RECALC\t\t\tBIT(31)\n #define SCALER_TPZ0_SCALE_MASK\t\t\tVC4_MASK(28, 8)\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0321-drm-vc4-Add-firmware-kms-mode.patch",
    "content": "From 0f304a905699ed05a418ac1cd98bcec6f2220a89 Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Mon, 7 Sep 2020 17:32:27 +0100\nSubject: [PATCH] drm/vc4: Add firmware-kms mode\n\nThis is a squash of all firmware-kms related patches from previous\nbranches, up to and including\n\"drm/vc4: Set the possible crtcs mask correctly for planes with FKMS\"\nplus a couple of minor fixups for the 5.9 branch.\nPlease refer to earlier branches for full history.\n\nThis patch includes work by Eric Anholt, James Hughes, Phil Elwell,\nDave Stevenson, Dom Cobley, and Jonathon Bell.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n\ndrm/vc4: Fixup firmware-kms after \"drm/atomic: Pass the full state to CRTC atomic enable/disable\"\n\nPrototype for those calls changed, so amend fkms (which isn't\nupstream) to match.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n drivers/gpu/drm/vc4/Makefile               |    1 +\n drivers/gpu/drm/vc4/vc4_drv.c              |   15 +-\n drivers/gpu/drm/vc4/vc4_drv.h              |    8 +\n drivers/gpu/drm/vc4/vc4_firmware_kms.c     | 1958 ++++++++++++++++++++\n drivers/gpu/drm/vc4/vc4_kms.c              |   27 +-\n drivers/gpu/drm/vc4/vc_image_types.h       |  175 ++\n include/soc/bcm2835/raspberrypi-firmware.h |    6 +\n 7 files changed, 2177 insertions(+), 13 deletions(-)\n create mode 100644 drivers/gpu/drm/vc4/vc4_firmware_kms.c\n create mode 100644 drivers/gpu/drm/vc4/vc_image_types.h\n\n--- a/drivers/gpu/drm/vc4/Makefile\n+++ b/drivers/gpu/drm/vc4/Makefile\n@@ -9,6 +9,7 @@ vc4-y := \\\n \tvc4_dpi.o \\\n \tvc4_dsi.o \\\n \tvc4_fence.o \\\n+\tvc4_firmware_kms.o \\\n \tvc4_kms.o \\\n \tvc4_gem.o \\\n \tvc4_hdmi.o \\\n--- a/drivers/gpu/drm/vc4/vc4_drv.c\n+++ b/drivers/gpu/drm/vc4/vc4_drv.c\n@@ -307,9 +307,11 @@ static int vc4_drm_bind(struct device *d\n \tif (ret)\n \t\treturn ret;\n \n-\tret = vc4_plane_create_additional_planes(drm);\n-\tif (ret)\n-\t\tgoto unbind_all;\n+\tif (!vc4->firmware_kms) {\n+\t\tret = vc4_plane_create_additional_planes(drm);\n+\t\tif (ret)\n+\t\t\tgoto unbind_all;\n+\t}\n \n \tdrm_fb_helper_remove_conflicting_framebuffers(NULL, \"vc4drmfb\", false);\n \n@@ -317,8 +319,10 @@ static int vc4_drm_bind(struct device *d\n \tif (ret < 0)\n \t\tgoto unbind_all;\n \n-\tdrm_for_each_crtc(crtc, drm)\n-\t\tvc4_crtc_disable_at_boot(crtc);\n+\tif (!vc4->firmware_kms) {\n+\t\tdrm_for_each_crtc(crtc, drm)\n+\t\t\tvc4_crtc_disable_at_boot(crtc);\n+\t}\n \n \tret = drm_dev_register(drm, 0);\n \tif (ret < 0)\n@@ -356,6 +360,7 @@ static struct platform_driver *const com\n \t&vc4_hvs_driver,\n \t&vc4_txp_driver,\n \t&vc4_crtc_driver,\n+\t&vc4_firmware_kms_driver,\n \t&vc4_v3d_driver,\n };\n \n--- a/drivers/gpu/drm/vc4/vc4_drv.h\n+++ b/drivers/gpu/drm/vc4/vc4_drv.h\n@@ -74,12 +74,17 @@ struct vc4_perfmon {\n struct vc4_dev {\n \tstruct drm_device base;\n \n+\tbool firmware_kms;\n+\tstruct rpi_firmware *firmware;\n+\n+\tstruct vc4_hdmi *hdmi;\n \tstruct vc4_hvs *hvs;\n \tstruct vc4_v3d *v3d;\n \tstruct vc4_dpi *dpi;\n \tstruct vc4_dsi *dsi1;\n \tstruct vc4_vec *vec;\n \tstruct vc4_txp *txp;\n+\tstruct vc4_fkms *fkms;\n \n \tstruct vc4_hang_state *hang_state;\n \n@@ -877,6 +882,9 @@ extern struct platform_driver vc4_dsi_dr\n /* vc4_fence.c */\n extern const struct dma_fence_ops vc4_fence_ops;\n \n+/* vc4_firmware_kms.c */\n+extern struct platform_driver vc4_firmware_kms_driver;\n+\n /* vc4_gem.c */\n int vc4_gem_init(struct drm_device *dev);\n int vc4_submit_cl_ioctl(struct drm_device *dev, void *data,\n--- /dev/null\n+++ b/drivers/gpu/drm/vc4/vc4_firmware_kms.c\n@@ -0,0 +1,1958 @@\n+// SPDX-License-Identifier: GPL-2.0-only\n+/*\n+ * Copyright (C) 2016 Broadcom\n+ *\n+ * This program is free software; you can redistribute it and/or modify\n+ * it under the terms of the GNU General Public License version 2 as\n+ * published by the Free Software Foundation.\n+ */\n+\n+/**\n+ * DOC: VC4 firmware KMS module.\n+ *\n+ * As a hack to get us from the current closed source driver world\n+ * toward a totally open stack, implement KMS on top of the Raspberry\n+ * Pi's firmware display stack.\n+ */\n+\n+#include <drm/drm_atomic_helper.h>\n+#include <drm/drm_crtc_helper.h>\n+#include <drm/drm_drv.h>\n+#include <drm/drm_fb_cma_helper.h>\n+#include <drm/drm_fourcc.h>\n+#include <drm/drm_gem_framebuffer_helper.h>\n+#include <drm/drm_plane_helper.h>\n+#include <drm/drm_probe_helper.h>\n+#include <drm/drm_vblank.h>\n+\n+#include <linux/component.h>\n+#include <linux/clk.h>\n+#include <linux/debugfs.h>\n+#include <linux/module.h>\n+\n+#include <soc/bcm2835/raspberrypi-firmware.h>\n+\n+#include \"vc4_drv.h\"\n+#include \"vc4_regs.h\"\n+#include \"vc_image_types.h\"\n+\n+int fkms_max_refresh_rate = 85;\n+module_param(fkms_max_refresh_rate, int, 0644);\n+MODULE_PARM_DESC(fkms_max_refresh_rate, \"Max supported refresh rate\");\n+\n+struct get_display_cfg {\n+\tu32  max_pixel_clock[2];  //Max pixel clock for each display\n+};\n+\n+struct vc4_fkms {\n+\tstruct get_display_cfg cfg;\n+\tbool bcm2711;\n+};\n+\n+#define PLANES_PER_CRTC\t\t8\n+\n+struct set_plane {\n+\tu8 display;\n+\tu8 plane_id;\n+\tu8 vc_image_type;\n+\ts8 layer;\n+\n+\tu16 width;\n+\tu16 height;\n+\n+\tu16 pitch;\n+\tu16 vpitch;\n+\n+\tu32 src_x;\t/* 16p16 */\n+\tu32 src_y;\t/* 16p16 */\n+\n+\tu32 src_w;\t/* 16p16 */\n+\tu32 src_h;\t/* 16p16 */\n+\n+\ts16 dst_x;\n+\ts16 dst_y;\n+\n+\tu16 dst_w;\n+\tu16 dst_h;\n+\n+\tu8 alpha;\n+\tu8 num_planes;\n+\tu8 is_vu;\n+\tu8 color_encoding;\n+\n+\tu32 planes[4];  /* DMA address of each plane */\n+\n+\tu32 transform;\n+};\n+\n+/* Values for the transform field */\n+#define TRANSFORM_NO_ROTATE\t0\n+#define TRANSFORM_ROTATE_180\tBIT(1)\n+#define TRANSFORM_FLIP_HRIZ\tBIT(16)\n+#define TRANSFORM_FLIP_VERT\tBIT(17)\n+\n+struct mailbox_set_plane {\n+\tstruct rpi_firmware_property_tag_header tag;\n+\tstruct set_plane plane;\n+};\n+\n+struct mailbox_blank_display {\n+\tstruct rpi_firmware_property_tag_header tag1;\n+\tu32 display;\n+\tstruct rpi_firmware_property_tag_header tag2;\n+\tu32 blank;\n+};\n+\n+struct mailbox_display_pwr {\n+\tstruct rpi_firmware_property_tag_header tag1;\n+\tu32 display;\n+\tu32 state;\n+};\n+\n+struct mailbox_get_edid {\n+\tstruct rpi_firmware_property_tag_header tag1;\n+\tu32 block;\n+\tu32 display_number;\n+\tu8 edid[128];\n+};\n+\n+struct set_timings {\n+\tu8 display;\n+\tu8 padding;\n+\tu16 video_id_code;\n+\n+\tu32 clock;\t\t/* in kHz */\n+\n+\tu16 hdisplay;\n+\tu16 hsync_start;\n+\n+\tu16 hsync_end;\n+\tu16 htotal;\n+\n+\tu16 hskew;\n+\tu16 vdisplay;\n+\n+\tu16 vsync_start;\n+\tu16 vsync_end;\n+\n+\tu16 vtotal;\n+\tu16 vscan;\n+\n+\tu16 vrefresh;\n+\tu16 padding2;\n+\n+\tu32 flags;\n+#define  TIMINGS_FLAGS_H_SYNC_POS\tBIT(0)\n+#define  TIMINGS_FLAGS_H_SYNC_NEG\t0\n+#define  TIMINGS_FLAGS_V_SYNC_POS\tBIT(1)\n+#define  TIMINGS_FLAGS_V_SYNC_NEG\t0\n+#define  TIMINGS_FLAGS_INTERLACE\tBIT(2)\n+\n+#define TIMINGS_FLAGS_ASPECT_MASK\tGENMASK(7, 4)\n+#define TIMINGS_FLAGS_ASPECT_NONE\t(0 << 4)\n+#define TIMINGS_FLAGS_ASPECT_4_3\t(1 << 4)\n+#define TIMINGS_FLAGS_ASPECT_16_9\t(2 << 4)\n+#define TIMINGS_FLAGS_ASPECT_64_27\t(3 << 4)\n+#define TIMINGS_FLAGS_ASPECT_256_135\t(4 << 4)\n+\n+/* Limited range RGB flag. Not set corresponds to full range. */\n+#define TIMINGS_FLAGS_RGB_LIMITED\tBIT(8)\n+/* DVI monitor, therefore disable infoframes. Not set corresponds to HDMI. */\n+#define TIMINGS_FLAGS_DVI\t\tBIT(9)\n+/* Double clock */\n+#define TIMINGS_FLAGS_DBL_CLK\t\tBIT(10)\n+};\n+\n+struct mailbox_set_mode {\n+\tstruct rpi_firmware_property_tag_header tag1;\n+\tstruct set_timings timings;\n+};\n+\n+static const struct vc_image_format {\n+\tu32 drm;\t/* DRM_FORMAT_* */\n+\tu32 vc_image;\t/* VC_IMAGE_* */\n+\tu32 is_vu;\n+} vc_image_formats[] = {\n+\t{\n+\t\t.drm = DRM_FORMAT_XRGB8888,\n+\t\t.vc_image = VC_IMAGE_XRGB8888,\n+\t},\n+\t{\n+\t\t.drm = DRM_FORMAT_ARGB8888,\n+\t\t.vc_image = VC_IMAGE_ARGB8888,\n+\t},\n+/*\n+ *\tFIXME: Need to resolve which DRM format goes to which vc_image format\n+ *\tfor the remaining RGBA and RGBX formats.\n+ *\t{\n+ *\t\t.drm = DRM_FORMAT_ABGR8888,\n+ *\t\t.vc_image = VC_IMAGE_RGBA8888,\n+ *\t},\n+ *\t{\n+ *\t\t.drm = DRM_FORMAT_XBGR8888,\n+ *\t\t.vc_image = VC_IMAGE_RGBA8888,\n+ *\t},\n+ */\n+\t{\n+\t\t.drm = DRM_FORMAT_RGB565,\n+\t\t.vc_image = VC_IMAGE_RGB565,\n+\t},\n+\t{\n+\t\t.drm = DRM_FORMAT_RGB888,\n+\t\t.vc_image = VC_IMAGE_BGR888,\n+\t},\n+\t{\n+\t\t.drm = DRM_FORMAT_BGR888,\n+\t\t.vc_image = VC_IMAGE_RGB888,\n+\t},\n+\t{\n+\t\t.drm = DRM_FORMAT_YUV422,\n+\t\t.vc_image = VC_IMAGE_YUV422PLANAR,\n+\t},\n+\t{\n+\t\t.drm = DRM_FORMAT_YUV420,\n+\t\t.vc_image = VC_IMAGE_YUV420,\n+\t},\n+\t{\n+\t\t.drm = DRM_FORMAT_YVU420,\n+\t\t.vc_image = VC_IMAGE_YUV420,\n+\t\t.is_vu = 1,\n+\t},\n+\t{\n+\t\t.drm = DRM_FORMAT_NV12,\n+\t\t.vc_image = VC_IMAGE_YUV420SP,\n+\t},\n+\t{\n+\t\t.drm = DRM_FORMAT_NV21,\n+\t\t.vc_image = VC_IMAGE_YUV420SP,\n+\t\t.is_vu = 1,\n+\t},\n+\t{\n+\t\t.drm = DRM_FORMAT_P030,\n+\t\t.vc_image = VC_IMAGE_YUV10COL,\n+\t},\n+};\n+\n+static const struct vc_image_format *vc4_get_vc_image_fmt(u32 drm_format)\n+{\n+\tunsigned int i;\n+\n+\tfor (i = 0; i < ARRAY_SIZE(vc_image_formats); i++) {\n+\t\tif (vc_image_formats[i].drm == drm_format)\n+\t\t\treturn &vc_image_formats[i];\n+\t}\n+\n+\treturn NULL;\n+}\n+\n+/* The firmware delivers a vblank interrupt to us through the SMI\n+ * hardware, which has only this one register.\n+ */\n+#define SMICS 0x0\n+#define SMIDSW0 0x14\n+#define SMIDSW1 0x1C\n+#define SMICS_INTERRUPTS (BIT(9) | BIT(10) | BIT(11))\n+\n+/* Flag to denote that the firmware is giving multiple display callbacks */\n+#define SMI_NEW 0xabcd0000\n+\n+#define vc4_crtc vc4_kms_crtc\n+#define to_vc4_crtc to_vc4_kms_crtc\n+struct vc4_crtc {\n+\tstruct drm_crtc base;\n+\tstruct drm_encoder *encoder;\n+\tstruct drm_connector *connector;\n+\tvoid __iomem *regs;\n+\n+\tstruct drm_pending_vblank_event *event;\n+\tbool vblank_enabled;\n+\tu32 display_number;\n+\tu32 display_type;\n+};\n+\n+static inline struct vc4_crtc *to_vc4_crtc(struct drm_crtc *crtc)\n+{\n+\treturn container_of(crtc, struct vc4_crtc, base);\n+}\n+\n+struct vc4_fkms_encoder {\n+\tstruct drm_encoder base;\n+\tbool hdmi_monitor;\n+\tbool rgb_range_selectable;\n+\tint display_num;\n+};\n+\n+static inline struct vc4_fkms_encoder *\n+to_vc4_fkms_encoder(struct drm_encoder *encoder)\n+{\n+\treturn container_of(encoder, struct vc4_fkms_encoder, base);\n+}\n+\n+/* \"Broadcast RGB\" property.\n+ * Allows overriding of HDMI full or limited range RGB\n+ */\n+#define VC4_BROADCAST_RGB_AUTO 0\n+#define VC4_BROADCAST_RGB_FULL 1\n+#define VC4_BROADCAST_RGB_LIMITED 2\n+\n+/* VC4 FKMS connector KMS struct */\n+struct vc4_fkms_connector {\n+\tstruct drm_connector base;\n+\n+\t/* Since the connector is attached to just the one encoder,\n+\t * this is the reference to it so we can do the best_encoder()\n+\t * hook.\n+\t */\n+\tstruct drm_encoder *encoder;\n+\tstruct vc4_dev *vc4_dev;\n+\tu32 display_number;\n+\tu32 display_type;\n+\n+\tstruct drm_property *broadcast_rgb_property;\n+};\n+\n+static inline struct vc4_fkms_connector *\n+to_vc4_fkms_connector(struct drm_connector *connector)\n+{\n+\treturn container_of(connector, struct vc4_fkms_connector, base);\n+}\n+\n+/* VC4 FKMS connector state */\n+struct vc4_fkms_connector_state {\n+\tstruct drm_connector_state base;\n+\n+\tint broadcast_rgb;\n+};\n+\n+#define to_vc4_fkms_connector_state(x) \\\n+\t\t\tcontainer_of(x, struct vc4_fkms_connector_state, base)\n+\n+static u32 vc4_get_display_type(u32 display_number)\n+{\n+\tconst u32 display_types[] = {\n+\t\t/* The firmware display (DispmanX) IDs map to specific types in\n+\t\t * a fixed manner.\n+\t\t */\n+\t\tDRM_MODE_ENCODER_DSI,\t/* MAIN_LCD - DSI or DPI */\n+\t\tDRM_MODE_ENCODER_DSI,\t/* AUX_LCD */\n+\t\tDRM_MODE_ENCODER_TMDS,\t/* HDMI0 */\n+\t\tDRM_MODE_ENCODER_TVDAC,\t/* VEC */\n+\t\tDRM_MODE_ENCODER_NONE,\t/* FORCE_LCD */\n+\t\tDRM_MODE_ENCODER_NONE,\t/* FORCE_TV */\n+\t\tDRM_MODE_ENCODER_NONE,\t/* FORCE_OTHER */\n+\t\tDRM_MODE_ENCODER_TMDS,\t/* HDMI1 */\n+\t\tDRM_MODE_ENCODER_NONE,\t/* FORCE_TV2 */\n+\t};\n+\treturn display_number > ARRAY_SIZE(display_types) - 1 ?\n+\t\t\tDRM_MODE_ENCODER_NONE : display_types[display_number];\n+}\n+\n+/* Firmware's structure for making an FB mbox call. */\n+struct fbinfo_s {\n+\tu32 xres, yres, xres_virtual, yres_virtual;\n+\tu32 pitch, bpp;\n+\tu32 xoffset, yoffset;\n+\tu32 base;\n+\tu32 screen_size;\n+\tu16 cmap[256];\n+};\n+\n+struct vc4_fkms_plane {\n+\tstruct drm_plane base;\n+\tstruct fbinfo_s *fbinfo;\n+\tdma_addr_t fbinfo_bus_addr;\n+\tu32 pitch;\n+\tstruct mailbox_set_plane mb;\n+};\n+\n+static inline struct vc4_fkms_plane *to_vc4_fkms_plane(struct drm_plane *plane)\n+{\n+\treturn (struct vc4_fkms_plane *)plane;\n+}\n+\n+static int vc4_plane_set_blank(struct drm_plane *plane, bool blank)\n+{\n+\tstruct vc4_dev *vc4 = to_vc4_dev(plane->dev);\n+\tstruct vc4_fkms_plane *vc4_plane = to_vc4_fkms_plane(plane);\n+\tstruct mailbox_set_plane blank_mb = {\n+\t\t.tag = { RPI_FIRMWARE_SET_PLANE, sizeof(struct set_plane), 0 },\n+\t\t.plane = {\n+\t\t\t.display = vc4_plane->mb.plane.display,\n+\t\t\t.plane_id = vc4_plane->mb.plane.plane_id,\n+\t\t}\n+\t};\n+\tstatic const char * const plane_types[] = {\n+\t\t\t\t\t\t\t\"overlay\",\n+\t\t\t\t\t\t\t\"primary\",\n+\t\t\t\t\t\t\t\"cursor\"\n+\t\t\t\t\t\t  };\n+\tint ret;\n+\n+\tDRM_DEBUG_ATOMIC(\"[PLANE:%d:%s] %s plane %s\",\n+\t\t\t plane->base.id, plane->name, plane_types[plane->type],\n+\t\t\t blank ? \"blank\" : \"unblank\");\n+\n+\tif (blank)\n+\t\tret = rpi_firmware_property_list(vc4->firmware, &blank_mb,\n+\t\t\t\t\t\t sizeof(blank_mb));\n+\telse\n+\t\tret = rpi_firmware_property_list(vc4->firmware, &vc4_plane->mb,\n+\t\t\t\t\t\t sizeof(vc4_plane->mb));\n+\n+\tWARN_ONCE(ret, \"%s: firmware call failed. Please update your firmware\",\n+\t\t  __func__);\n+\treturn ret;\n+}\n+\n+static void vc4_fkms_crtc_get_margins(struct drm_crtc_state *state,\n+\t\t\t\t      unsigned int *left, unsigned int *right,\n+\t\t\t\t      unsigned int *top, unsigned int *bottom)\n+{\n+\tstruct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);\n+\tstruct drm_connector_state *conn_state;\n+\tstruct drm_connector *conn;\n+\tint i;\n+\n+\t*left = vc4_state->margins.left;\n+\t*right = vc4_state->margins.right;\n+\t*top = vc4_state->margins.top;\n+\t*bottom = vc4_state->margins.bottom;\n+\n+\t/* We have to interate over all new connector states because\n+\t * vc4_fkms_crtc_get_margins() might be called before\n+\t * vc4_fkms_crtc_atomic_check() which means margins info in\n+\t * vc4_crtc_state might be outdated.\n+\t */\n+\tfor_each_new_connector_in_state(state->state, conn, conn_state, i) {\n+\t\tif (conn_state->crtc != state->crtc)\n+\t\t\tcontinue;\n+\n+\t\t*left = conn_state->tv.margins.left;\n+\t\t*right = conn_state->tv.margins.right;\n+\t\t*top = conn_state->tv.margins.top;\n+\t\t*bottom = conn_state->tv.margins.bottom;\n+\t\tbreak;\n+\t}\n+}\n+\n+static int vc4_fkms_margins_adj(struct drm_plane_state *pstate,\n+\t\t\t\tstruct set_plane *plane)\n+{\n+\tunsigned int left, right, top, bottom;\n+\tint adjhdisplay, adjvdisplay;\n+\tstruct drm_crtc_state *crtc_state;\n+\n+\tcrtc_state = drm_atomic_get_new_crtc_state(pstate->state,\n+\t\t\t\t\t\t   pstate->crtc);\n+\n+\tvc4_fkms_crtc_get_margins(crtc_state, &left, &right, &top, &bottom);\n+\n+\tif (!left && !right && !top && !bottom)\n+\t\treturn 0;\n+\n+\tif (left + right >= crtc_state->mode.hdisplay ||\n+\t    top + bottom >= crtc_state->mode.vdisplay)\n+\t\treturn -EINVAL;\n+\n+\tadjhdisplay = crtc_state->mode.hdisplay - (left + right);\n+\tplane->dst_x = DIV_ROUND_CLOSEST(plane->dst_x * adjhdisplay,\n+\t\t\t\t\t (int)crtc_state->mode.hdisplay);\n+\tplane->dst_x += left;\n+\tif (plane->dst_x > (int)(crtc_state->mode.hdisplay - left))\n+\t\tplane->dst_x = crtc_state->mode.hdisplay - left;\n+\n+\tadjvdisplay = crtc_state->mode.vdisplay - (top + bottom);\n+\tplane->dst_y = DIV_ROUND_CLOSEST(plane->dst_y * adjvdisplay,\n+\t\t\t\t\t (int)crtc_state->mode.vdisplay);\n+\tplane->dst_y += top;\n+\tif (plane->dst_y > (int)(crtc_state->mode.vdisplay - top))\n+\t\tplane->dst_y = crtc_state->mode.vdisplay - top;\n+\n+\tplane->dst_w = DIV_ROUND_CLOSEST(plane->dst_w * adjhdisplay,\n+\t\t\t\t\t crtc_state->mode.hdisplay);\n+\tplane->dst_h = DIV_ROUND_CLOSEST(plane->dst_h * adjvdisplay,\n+\t\t\t\t\t crtc_state->mode.vdisplay);\n+\n+\tif (!plane->dst_w || !plane->dst_h)\n+\t\treturn -EINVAL;\n+\n+\treturn 0;\n+}\n+\n+static void vc4_plane_atomic_update(struct drm_plane *plane,\n+\t\t\t\t    struct drm_plane_state *old_state)\n+{\n+\tstruct drm_plane_state *state = plane->state;\n+\n+\t/*\n+\t * Do NOT set now, as we haven't checked if the crtc is active or not.\n+\t * Set from vc4_plane_set_blank instead.\n+\t *\n+\t * If the CRTC is on (or going to be on) and we're enabled,\n+\t * then unblank.  Otherwise, stay blank until CRTC enable.\n+\t */\n+\tif (state->crtc->state->active)\n+\t\tvc4_plane_set_blank(plane, false);\n+}\n+\n+static void vc4_plane_atomic_disable(struct drm_plane *plane,\n+\t\t\t\t     struct drm_plane_state *old_state)\n+{\n+\tstruct drm_plane_state *state = plane->state;\n+\tstruct vc4_fkms_plane *vc4_plane = to_vc4_fkms_plane(plane);\n+\n+\tDRM_DEBUG_ATOMIC(\"[PLANE:%d:%s] plane disable %dx%d@%d +%d,%d\\n\",\n+\t\t\t plane->base.id, plane->name,\n+\t\t\t state->crtc_w,\n+\t\t\t state->crtc_h,\n+\t\t\t vc4_plane->mb.plane.vc_image_type,\n+\t\t\t state->crtc_x,\n+\t\t\t state->crtc_y);\n+\tvc4_plane_set_blank(plane, true);\n+}\n+\n+static bool plane_enabled(struct drm_plane_state *state)\n+{\n+\treturn state->fb && state->crtc;\n+}\n+\n+static int vc4_plane_to_mb(struct drm_plane *plane,\n+\t\t\t   struct mailbox_set_plane *mb,\n+\t\t\t   struct drm_plane_state *state)\n+{\n+\tstruct drm_framebuffer *fb = state->fb;\n+\tstruct drm_gem_cma_object *bo = drm_fb_cma_get_gem_obj(fb, 0);\n+\tconst struct drm_format_info *drm_fmt = fb->format;\n+\tconst struct vc_image_format *vc_fmt =\n+\t\t\t\t\tvc4_get_vc_image_fmt(drm_fmt->format);\n+\tint num_planes = fb->format->num_planes;\n+\tunsigned int rotation;\n+\n+\tmb->plane.vc_image_type = vc_fmt->vc_image;\n+\tmb->plane.width = fb->width;\n+\tmb->plane.height = fb->height;\n+\tmb->plane.pitch = fb->pitches[0];\n+\tmb->plane.src_w = state->src_w;\n+\tmb->plane.src_h = state->src_h;\n+\tmb->plane.src_x = state->src_x;\n+\tmb->plane.src_y = state->src_y;\n+\tmb->plane.dst_w = state->crtc_w;\n+\tmb->plane.dst_h = state->crtc_h;\n+\tmb->plane.dst_x = state->crtc_x;\n+\tmb->plane.dst_y = state->crtc_y;\n+\tmb->plane.alpha = state->alpha >> 8;\n+\tmb->plane.layer = state->normalized_zpos ?\n+\t\t\t\t\tstate->normalized_zpos : -127;\n+\tmb->plane.num_planes = num_planes;\n+\tmb->plane.is_vu = vc_fmt->is_vu;\n+\tmb->plane.planes[0] = bo->paddr + fb->offsets[0];\n+\n+\trotation = drm_rotation_simplify(state->rotation,\n+\t\t\t\t\t DRM_MODE_ROTATE_0 |\n+\t\t\t\t\t DRM_MODE_REFLECT_X |\n+\t\t\t\t\t DRM_MODE_REFLECT_Y);\n+\n+\tmb->plane.transform = TRANSFORM_NO_ROTATE;\n+\tif (rotation & DRM_MODE_REFLECT_X)\n+\t\tmb->plane.transform |= TRANSFORM_FLIP_HRIZ;\n+\tif (rotation & DRM_MODE_REFLECT_Y)\n+\t\tmb->plane.transform |= TRANSFORM_FLIP_VERT;\n+\n+\tvc4_fkms_margins_adj(state, &mb->plane);\n+\n+\tif (num_planes > 1) {\n+\t\t/* Assume this must be YUV */\n+\t\t/* Makes assumptions on the stride for the chroma planes as we\n+\t\t * can't easily plumb in non-standard pitches.\n+\t\t */\n+\t\tmb->plane.planes[1] = bo->paddr + fb->offsets[1];\n+\t\tif (num_planes > 2)\n+\t\t\tmb->plane.planes[2] = bo->paddr + fb->offsets[2];\n+\t\telse\n+\t\t\tmb->plane.planes[2] = 0;\n+\n+\t\t/* Special case the YUV420 with U and V as line interleaved\n+\t\t * planes as we have special handling for that case.\n+\t\t */\n+\t\tif (num_planes == 3 &&\n+\t\t    (fb->offsets[2] - fb->offsets[1]) == fb->pitches[1])\n+\t\t\tmb->plane.vc_image_type = VC_IMAGE_YUV420_S;\n+\n+\t\tswitch (state->color_encoding) {\n+\t\tdefault:\n+\t\tcase DRM_COLOR_YCBCR_BT601:\n+\t\t\tif (state->color_range == DRM_COLOR_YCBCR_LIMITED_RANGE)\n+\t\t\t\tmb->plane.color_encoding =\n+\t\t\t\t\t\tVC_IMAGE_YUVINFO_CSC_ITUR_BT601;\n+\t\t\telse\n+\t\t\t\tmb->plane.color_encoding =\n+\t\t\t\t\t\tVC_IMAGE_YUVINFO_CSC_JPEG_JFIF;\n+\t\t\tbreak;\n+\t\tcase DRM_COLOR_YCBCR_BT709:\n+\t\t\t/* Currently no support for a full range BT709 */\n+\t\t\tmb->plane.color_encoding =\n+\t\t\t\t\t\tVC_IMAGE_YUVINFO_CSC_ITUR_BT709;\n+\t\t\tbreak;\n+\t\tcase DRM_COLOR_YCBCR_BT2020:\n+\t\t\t/* Currently no support for a full range BT2020 */\n+\t\t\tmb->plane.color_encoding =\n+\t\t\t\t\tVC_IMAGE_YUVINFO_CSC_REC_2020;\n+\t\t\tbreak;\n+\t\t}\n+\t} else {\n+\t\tmb->plane.planes[1] = 0;\n+\t\tmb->plane.planes[2] = 0;\n+\t}\n+\tmb->plane.planes[3] = 0;\n+\n+\tswitch (fourcc_mod_broadcom_mod(fb->modifier)) {\n+\tcase DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED:\n+\t\tswitch (mb->plane.vc_image_type) {\n+\t\tcase VC_IMAGE_XRGB8888:\n+\t\t\tmb->plane.vc_image_type = VC_IMAGE_TF_RGBX32;\n+\t\t\tbreak;\n+\t\tcase VC_IMAGE_ARGB8888:\n+\t\t\tmb->plane.vc_image_type = VC_IMAGE_TF_RGBA32;\n+\t\t\tbreak;\n+\t\tcase VC_IMAGE_RGB565:\n+\t\t\tmb->plane.vc_image_type = VC_IMAGE_TF_RGB565;\n+\t\t\tbreak;\n+\t\t}\n+\t\tbreak;\n+\tcase DRM_FORMAT_MOD_BROADCOM_SAND128:\n+\t\tswitch (mb->plane.vc_image_type) {\n+\t\tcase VC_IMAGE_YUV420SP:\n+\t\t\tmb->plane.vc_image_type = VC_IMAGE_YUV_UV;\n+\t\t\tbreak;\n+\t\t/* VC_IMAGE_YUV10COL could be included in here, but it is only\n+\t\t * valid as a SAND128 format, so the table at the top will have\n+\t\t * already set the correct format.\n+\t\t */\n+\t\t}\n+\t\t/* Note that the column pitch is passed across in lines, not\n+\t\t * bytes.\n+\t\t */\n+\t\tmb->plane.pitch = fourcc_mod_broadcom_param(fb->modifier);\n+\t\tbreak;\n+\t}\n+\n+\tDRM_DEBUG_ATOMIC(\"[PLANE:%d:%s] plane update %dx%d@%d +dst(%d,%d, %d,%d) +src(%d,%d, %d,%d) 0x%08x/%08x/%08x/%d, alpha %u zpos %u\\n\",\n+\t\t\t plane->base.id, plane->name,\n+\t\t\t mb->plane.width,\n+\t\t\t mb->plane.height,\n+\t\t\t mb->plane.vc_image_type,\n+\t\t\t state->crtc_x,\n+\t\t\t state->crtc_y,\n+\t\t\t state->crtc_w,\n+\t\t\t state->crtc_h,\n+\t\t\t mb->plane.src_x,\n+\t\t\t mb->plane.src_y,\n+\t\t\t mb->plane.src_w,\n+\t\t\t mb->plane.src_h,\n+\t\t\t mb->plane.planes[0],\n+\t\t\t mb->plane.planes[1],\n+\t\t\t mb->plane.planes[2],\n+\t\t\t fb->pitches[0],\n+\t\t\t state->alpha,\n+\t\t\t state->normalized_zpos);\n+\n+\treturn 0;\n+}\n+\n+static int vc4_plane_atomic_check(struct drm_plane *plane,\n+\t\t\t\t  struct drm_plane_state *state)\n+{\n+\tstruct vc4_fkms_plane *vc4_plane = to_vc4_fkms_plane(plane);\n+\n+\tif (!plane_enabled(state))\n+\t\treturn 0;\n+\n+\treturn vc4_plane_to_mb(plane, &vc4_plane->mb, state);\n+}\n+\n+/* Called during init to allocate the plane's atomic state. */\n+static void vc4_plane_reset(struct drm_plane *plane)\n+{\n+\tstruct vc4_plane_state *vc4_state;\n+\n+\tWARN_ON(plane->state);\n+\n+\tvc4_state = kzalloc(sizeof(*vc4_state), GFP_KERNEL);\n+\tif (!vc4_state)\n+\t\treturn;\n+\n+\t__drm_atomic_helper_plane_reset(plane, &vc4_state->base);\n+}\n+\n+static void vc4_plane_destroy(struct drm_plane *plane)\n+{\n+\tdrm_plane_cleanup(plane);\n+}\n+\n+static bool vc4_fkms_format_mod_supported(struct drm_plane *plane,\n+\t\t\t\t\t  uint32_t format,\n+\t\t\t\t\t  uint64_t modifier)\n+{\n+\t/* Support T_TILING for RGB formats only. */\n+\tswitch (format) {\n+\tcase DRM_FORMAT_XRGB8888:\n+\tcase DRM_FORMAT_ARGB8888:\n+\tcase DRM_FORMAT_RGB565:\n+\t\tswitch (modifier) {\n+\t\tcase DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED:\n+\t\tcase DRM_FORMAT_MOD_LINEAR:\n+\t\t\treturn true;\n+\t\tdefault:\n+\t\t\treturn false;\n+\t\t}\n+\tcase DRM_FORMAT_NV12:\n+\t\tswitch (fourcc_mod_broadcom_mod(modifier)) {\n+\t\tcase DRM_FORMAT_MOD_LINEAR:\n+\t\tcase DRM_FORMAT_MOD_BROADCOM_SAND128:\n+\t\t\treturn true;\n+\t\tdefault:\n+\t\t\treturn false;\n+\t\t}\n+\tcase DRM_FORMAT_P030:\n+\t\tswitch (fourcc_mod_broadcom_mod(modifier)) {\n+\t\tcase DRM_FORMAT_MOD_BROADCOM_SAND128:\n+\t\t\treturn true;\n+\t\tdefault:\n+\t\t\treturn false;\n+\t\t}\n+\tcase DRM_FORMAT_NV21:\n+\tcase DRM_FORMAT_RGB888:\n+\tcase DRM_FORMAT_BGR888:\n+\tcase DRM_FORMAT_YUV422:\n+\tcase DRM_FORMAT_YUV420:\n+\tcase DRM_FORMAT_YVU420:\n+\tdefault:\n+\t\treturn (modifier == DRM_FORMAT_MOD_LINEAR);\n+\t}\n+}\n+\n+static struct drm_plane_state *vc4_plane_duplicate_state(struct drm_plane *plane)\n+{\n+\tstruct vc4_plane_state *vc4_state;\n+\n+\tif (WARN_ON(!plane->state))\n+\t\treturn NULL;\n+\n+\tvc4_state = kzalloc(sizeof(*vc4_state), GFP_KERNEL);\n+\tif (!vc4_state)\n+\t\treturn NULL;\n+\n+\t__drm_atomic_helper_plane_duplicate_state(plane, &vc4_state->base);\n+\n+\treturn &vc4_state->base;\n+}\n+\n+static const struct drm_plane_funcs vc4_plane_funcs = {\n+\t.update_plane = drm_atomic_helper_update_plane,\n+\t.disable_plane = drm_atomic_helper_disable_plane,\n+\t.destroy = vc4_plane_destroy,\n+\t.set_property = NULL,\n+\t.reset = vc4_plane_reset,\n+\t.atomic_duplicate_state = vc4_plane_duplicate_state,\n+\t.atomic_destroy_state = drm_atomic_helper_plane_destroy_state,\n+\t.format_mod_supported = vc4_fkms_format_mod_supported,\n+};\n+\n+static const struct drm_plane_helper_funcs vc4_plane_helper_funcs = {\n+\t.prepare_fb = drm_gem_fb_prepare_fb,\n+\t.cleanup_fb = NULL,\n+\t.atomic_check = vc4_plane_atomic_check,\n+\t.atomic_update = vc4_plane_atomic_update,\n+\t.atomic_disable = vc4_plane_atomic_disable,\n+};\n+\n+static struct drm_plane *vc4_fkms_plane_init(struct drm_device *dev,\n+\t\t\t\t\t     enum drm_plane_type type,\n+\t\t\t\t\t     u8 display_num,\n+\t\t\t\t\t     u8 plane_id)\n+{\n+\tstruct drm_plane *plane = NULL;\n+\tstruct vc4_fkms_plane *vc4_plane;\n+\tu32 formats[ARRAY_SIZE(vc_image_formats)];\n+\tunsigned int default_zpos = 0;\n+\tu32 num_formats = 0;\n+\tint ret = 0;\n+\tstatic const uint64_t modifiers[] = {\n+\t\tDRM_FORMAT_MOD_LINEAR,\n+\t\t/* VC4_T_TILED should come after linear, because we\n+\t\t * would prefer to scan out linear (less bus traffic).\n+\t\t */\n+\t\tDRM_FORMAT_MOD_BROADCOM_VC4_T_TILED,\n+\t\tDRM_FORMAT_MOD_BROADCOM_SAND128,\n+\t\tDRM_FORMAT_MOD_INVALID,\n+\t};\n+\tint i;\n+\n+\tvc4_plane = devm_kzalloc(dev->dev, sizeof(*vc4_plane),\n+\t\t\t\t GFP_KERNEL);\n+\tif (!vc4_plane) {\n+\t\tret = -ENOMEM;\n+\t\tgoto fail;\n+\t}\n+\n+\tfor (i = 0; i < ARRAY_SIZE(vc_image_formats); i++)\n+\t\tformats[num_formats++] = vc_image_formats[i].drm;\n+\n+\tplane = &vc4_plane->base;\n+\tret = drm_universal_plane_init(dev, plane, 0,\n+\t\t\t\t       &vc4_plane_funcs,\n+\t\t\t\t       formats, num_formats, modifiers,\n+\t\t\t\t       type, NULL);\n+\n+\t/* FIXME: Do we need to be checking return values from all these calls?\n+\t */\n+\tdrm_plane_helper_add(plane, &vc4_plane_helper_funcs);\n+\n+\tdrm_plane_create_alpha_property(plane);\n+\tdrm_plane_create_rotation_property(plane, DRM_MODE_ROTATE_0,\n+\t\t\t\t\t   DRM_MODE_ROTATE_0 |\n+\t\t\t\t\t   DRM_MODE_ROTATE_180 |\n+\t\t\t\t\t   DRM_MODE_REFLECT_X |\n+\t\t\t\t\t   DRM_MODE_REFLECT_Y);\n+\tdrm_plane_create_color_properties(plane,\n+\t\t\t\t\t  BIT(DRM_COLOR_YCBCR_BT601) |\n+\t\t\t\t\t  BIT(DRM_COLOR_YCBCR_BT709) |\n+\t\t\t\t\t  BIT(DRM_COLOR_YCBCR_BT2020),\n+\t\t\t\t\t  BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) |\n+\t\t\t\t\t  BIT(DRM_COLOR_YCBCR_FULL_RANGE),\n+\t\t\t\t\t  DRM_COLOR_YCBCR_BT709,\n+\t\t\t\t\t  DRM_COLOR_YCBCR_LIMITED_RANGE);\n+\n+\t/*\n+\t * Default frame buffer setup is with FB on -127, and raspistill etc\n+\t * tend to drop overlays on layer 2. Cursor plane was on layer +127.\n+\t *\n+\t * For F-KMS the mailbox call allows for a s8.\n+\t * Remap zpos 0 to -127 for the background layer, but leave all the\n+\t * other layers as requested by KMS.\n+\t */\n+\tswitch (type) {\n+\tdefault:\n+\tcase DRM_PLANE_TYPE_PRIMARY:\n+\t\tdefault_zpos = 0;\n+\t\tbreak;\n+\tcase DRM_PLANE_TYPE_OVERLAY:\n+\t\tdefault_zpos = 1;\n+\t\tbreak;\n+\tcase DRM_PLANE_TYPE_CURSOR:\n+\t\tdefault_zpos = 2;\n+\t\tbreak;\n+\t}\n+\tdrm_plane_create_zpos_property(plane, default_zpos, 0, 127);\n+\n+\t/* Prepare the static elements of the mailbox structure */\n+\tvc4_plane->mb.tag.tag = RPI_FIRMWARE_SET_PLANE;\n+\tvc4_plane->mb.tag.buf_size = sizeof(struct set_plane);\n+\tvc4_plane->mb.tag.req_resp_size = 0;\n+\tvc4_plane->mb.plane.display = display_num;\n+\tvc4_plane->mb.plane.plane_id = plane_id;\n+\tvc4_plane->mb.plane.layer = default_zpos ? default_zpos : -127;\n+\n+\treturn plane;\n+fail:\n+\tif (plane)\n+\t\tvc4_plane_destroy(plane);\n+\n+\treturn ERR_PTR(ret);\n+}\n+\n+static void vc4_crtc_mode_set_nofb(struct drm_crtc *crtc)\n+{\n+\tstruct drm_device *dev = crtc->dev;\n+\tstruct vc4_dev *vc4 = to_vc4_dev(dev);\n+\tstruct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);\n+\tstruct drm_display_mode *mode = &crtc->state->adjusted_mode;\n+\tstruct vc4_fkms_encoder *vc4_encoder =\n+\t\t\t\t\tto_vc4_fkms_encoder(vc4_crtc->encoder);\n+\tstruct mailbox_set_mode mb = {\n+\t\t.tag1 = { RPI_FIRMWARE_SET_TIMING,\n+\t\t\t  sizeof(struct set_timings), 0},\n+\t};\n+\tunion hdmi_infoframe frame;\n+\tint ret;\n+\n+\tret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, vc4_crtc->connector, mode);\n+\tif (ret < 0) {\n+\t\tDRM_ERROR(\"couldn't fill AVI infoframe\\n\");\n+\t\treturn;\n+\t}\n+\n+\tDRM_DEBUG_KMS(\"Setting mode for display num %u mode name %s, clk %d, h(disp %d, start %d, end %d, total %d, skew %d) v(disp %d, start %d, end %d, total %d, scan %d), vrefresh %d, par %u, flags 0x%04x\\n\",\n+\t\t      vc4_crtc->display_number, mode->name, mode->clock,\n+\t\t      mode->hdisplay, mode->hsync_start, mode->hsync_end,\n+\t\t      mode->htotal, mode->hskew, mode->vdisplay,\n+\t\t      mode->vsync_start, mode->vsync_end, mode->vtotal,\n+\t\t      mode->vscan, drm_mode_vrefresh(mode),\n+\t\t      mode->picture_aspect_ratio, mode->flags);\n+\tmb.timings.display = vc4_crtc->display_number;\n+\n+\tmb.timings.clock = mode->clock;\n+\tmb.timings.hdisplay = mode->hdisplay;\n+\tmb.timings.hsync_start = mode->hsync_start;\n+\tmb.timings.hsync_end = mode->hsync_end;\n+\tmb.timings.htotal = mode->htotal;\n+\tmb.timings.hskew = mode->hskew;\n+\tmb.timings.vdisplay = mode->vdisplay;\n+\tmb.timings.vsync_start = mode->vsync_start;\n+\tmb.timings.vsync_end = mode->vsync_end;\n+\tmb.timings.vtotal = mode->vtotal;\n+\tmb.timings.vscan = mode->vscan;\n+\tmb.timings.vrefresh = drm_mode_vrefresh(mode);\n+\tmb.timings.flags = 0;\n+\tif (mode->flags & DRM_MODE_FLAG_PHSYNC)\n+\t\tmb.timings.flags |= TIMINGS_FLAGS_H_SYNC_POS;\n+\tif (mode->flags & DRM_MODE_FLAG_PVSYNC)\n+\t\tmb.timings.flags |= TIMINGS_FLAGS_V_SYNC_POS;\n+\n+\tswitch (frame.avi.picture_aspect) {\n+\tdefault:\n+\tcase HDMI_PICTURE_ASPECT_NONE:\n+\t\tmb.timings.flags |= TIMINGS_FLAGS_ASPECT_NONE;\n+\t\tbreak;\n+\tcase HDMI_PICTURE_ASPECT_4_3:\n+\t\tmb.timings.flags |= TIMINGS_FLAGS_ASPECT_4_3;\n+\t\tbreak;\n+\tcase HDMI_PICTURE_ASPECT_16_9:\n+\t\tmb.timings.flags |= TIMINGS_FLAGS_ASPECT_16_9;\n+\t\tbreak;\n+\tcase HDMI_PICTURE_ASPECT_64_27:\n+\t\tmb.timings.flags |= TIMINGS_FLAGS_ASPECT_64_27;\n+\t\tbreak;\n+\tcase HDMI_PICTURE_ASPECT_256_135:\n+\t\tmb.timings.flags |= TIMINGS_FLAGS_ASPECT_256_135;\n+\t\tbreak;\n+\t}\n+\n+\tif (mode->flags & DRM_MODE_FLAG_INTERLACE)\n+\t\tmb.timings.flags |= TIMINGS_FLAGS_INTERLACE;\n+\tif (mode->flags & DRM_MODE_FLAG_DBLCLK)\n+\t\tmb.timings.flags |= TIMINGS_FLAGS_DBL_CLK;\n+\n+\tmb.timings.video_id_code = frame.avi.video_code;\n+\n+\tif (!vc4_encoder->hdmi_monitor) {\n+\t\tmb.timings.flags |= TIMINGS_FLAGS_DVI;\n+\t} else {\n+\t\tstruct vc4_fkms_connector_state *conn_state =\n+\t\t\tto_vc4_fkms_connector_state(vc4_crtc->connector->state);\n+\n+\t\tif (conn_state->broadcast_rgb == VC4_BROADCAST_RGB_AUTO) {\n+\t\t\t/* See CEA-861-E - 5.1 Default Encoding Parameters */\n+\t\t\tif (drm_default_rgb_quant_range(mode) ==\n+\t\t\t\t\tHDMI_QUANTIZATION_RANGE_LIMITED)\n+\t\t\t\tmb.timings.flags |= TIMINGS_FLAGS_RGB_LIMITED;\n+\t\t} else {\n+\t\t\tif (conn_state->broadcast_rgb ==\n+\t\t\t\t\t\tVC4_BROADCAST_RGB_LIMITED)\n+\t\t\t\tmb.timings.flags |= TIMINGS_FLAGS_RGB_LIMITED;\n+\n+\t\t\t/* If not using the default range, then do not provide\n+\t\t\t * a VIC as the HDMI spec requires that we do not\n+\t\t\t * signal the opposite of the defined range in the AVI\n+\t\t\t * infoframe.\n+\t\t\t */\n+\t\t\tif (!!(mb.timings.flags & TIMINGS_FLAGS_RGB_LIMITED) !=\n+\t\t\t    (drm_default_rgb_quant_range(mode) ==\n+\t\t\t\t\tHDMI_QUANTIZATION_RANGE_LIMITED))\n+\t\t\t\tmb.timings.video_id_code = 0;\n+\t\t}\n+\t}\n+\n+\t/*\n+\t * FIXME: To implement\n+\t * switch(mode->flag & DRM_MODE_FLAG_3D_MASK) {\n+\t * case DRM_MODE_FLAG_3D_NONE:\n+\t * case DRM_MODE_FLAG_3D_FRAME_PACKING:\n+\t * case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE:\n+\t * case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE:\n+\t * case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL:\n+\t * case DRM_MODE_FLAG_3D_L_DEPTH:\n+\t * case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH:\n+\t * case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM:\n+\t * case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF:\n+\t * }\n+\t */\n+\n+\tret = rpi_firmware_property_list(vc4->firmware, &mb, sizeof(mb));\n+}\n+\n+static void vc4_crtc_disable(struct drm_crtc *crtc,\n+\t\t\t     struct drm_atomic_state *state)\n+{\n+\tstruct drm_device *dev = crtc->dev;\n+\tstruct drm_plane *plane;\n+\n+\tDRM_DEBUG_KMS(\"[CRTC:%d] vblanks off.\\n\",\n+\t\t      crtc->base.id);\n+\tdrm_crtc_vblank_off(crtc);\n+\n+\t/* Always turn the planes off on CRTC disable. In DRM, planes\n+\t * are enabled/disabled through the update/disable hooks\n+\t * above, and the CRTC enable/disable independently controls\n+\t * whether anything scans out at all, but the firmware doesn't\n+\t * give us a CRTC-level control for that.\n+\t */\n+\n+\tdrm_atomic_crtc_for_each_plane(plane, crtc)\n+\t\tvc4_plane_atomic_disable(plane, plane->state);\n+\n+\t/*\n+\t * Make sure we issue a vblank event after disabling the CRTC if\n+\t * someone was waiting it.\n+\t */\n+\tif (crtc->state->event) {\n+\t\tunsigned long flags;\n+\n+\t\tspin_lock_irqsave(&dev->event_lock, flags);\n+\t\tdrm_crtc_send_vblank_event(crtc, crtc->state->event);\n+\t\tcrtc->state->event = NULL;\n+\t\tspin_unlock_irqrestore(&dev->event_lock, flags);\n+\t}\n+}\n+\n+static void vc4_crtc_consume_event(struct drm_crtc *crtc)\n+{\n+\tstruct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);\n+\tstruct drm_device *dev = crtc->dev;\n+\tunsigned long flags;\n+\n+\tif (!crtc->state->event)\n+\t\treturn;\n+\n+\tcrtc->state->event->pipe = drm_crtc_index(crtc);\n+\n+\tWARN_ON(drm_crtc_vblank_get(crtc) != 0);\n+\n+\tspin_lock_irqsave(&dev->event_lock, flags);\n+\tvc4_crtc->event = crtc->state->event;\n+\tcrtc->state->event = NULL;\n+\tspin_unlock_irqrestore(&dev->event_lock, flags);\n+}\n+\n+static void vc4_crtc_enable(struct drm_crtc *crtc,\n+\t\t\t    struct drm_atomic_state *state)\n+{\n+\tstruct drm_plane *plane;\n+\n+\tDRM_DEBUG_KMS(\"[CRTC:%d] vblanks on.\\n\",\n+\t\t      crtc->base.id);\n+\tdrm_crtc_vblank_on(crtc);\n+\tvc4_crtc_consume_event(crtc);\n+\n+\t/* Unblank the planes (if they're supposed to be displayed). */\n+\tdrm_atomic_crtc_for_each_plane(plane, crtc)\n+\t\tif (plane->state->fb)\n+\t\t\tvc4_plane_set_blank(plane, plane->state->visible);\n+}\n+\n+static enum drm_mode_status\n+vc4_crtc_mode_valid(struct drm_crtc *crtc, const struct drm_display_mode *mode)\n+{\n+\tstruct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);\n+\tstruct drm_device *dev = crtc->dev;\n+\tstruct vc4_dev *vc4 = to_vc4_dev(dev);\n+\tstruct vc4_fkms *fkms = vc4->fkms;\n+\n+\t/* Do not allow doublescan modes from user space */\n+\tif (mode->flags & DRM_MODE_FLAG_DBLSCAN) {\n+\t\tDRM_DEBUG_KMS(\"[CRTC:%d] Doublescan mode rejected.\\n\",\n+\t\t\t      crtc->base.id);\n+\t\treturn MODE_NO_DBLESCAN;\n+\t}\n+\n+\t/* Disable refresh rates > defined threshold (default 85Hz) as limited\n+\t * gain from them\n+\t */\n+\tif (drm_mode_vrefresh(mode) > fkms_max_refresh_rate)\n+\t\treturn MODE_BAD_VVALUE;\n+\n+\t/* Limit the pixel clock based on the HDMI clock limits from the\n+\t * firmware\n+\t */\n+\tswitch (vc4_crtc->display_number) {\n+\tcase 2:\t/* HDMI0 */\n+\t\tif (fkms->cfg.max_pixel_clock[0] &&\n+\t\t    mode->clock > fkms->cfg.max_pixel_clock[0])\n+\t\t\treturn MODE_CLOCK_HIGH;\n+\t\tbreak;\n+\tcase 7:\t/* HDMI1 */\n+\t\tif (fkms->cfg.max_pixel_clock[1] &&\n+\t\t    mode->clock > fkms->cfg.max_pixel_clock[1])\n+\t\t\treturn MODE_CLOCK_HIGH;\n+\t\tbreak;\n+\t}\n+\n+\t/* Pi4 can't generate odd horizontal timings on HDMI, so reject modes\n+\t * that would set them.\n+\t */\n+\tif (fkms->bcm2711 &&\n+\t    (vc4_crtc->display_number == 2 || vc4_crtc->display_number == 7) &&\n+\t    !(mode->flags & DRM_MODE_FLAG_DBLCLK) &&\n+\t    ((mode->hdisplay |\t\t\t\t/* active */\n+\t      (mode->hsync_start - mode->hdisplay) |\t/* front porch */\n+\t      (mode->hsync_end - mode->hsync_start) |\t/* sync pulse */\n+\t      (mode->htotal - mode->hsync_end)) & 1))\t/* back porch */ {\n+\t\tDRM_DEBUG_KMS(\"[CRTC:%d] Odd timing rejected %u %u %u %u.\\n\",\n+\t\t\t      crtc->base.id, mode->hdisplay, mode->hsync_start,\n+\t\t\t      mode->hsync_end, mode->htotal);\n+\t\treturn MODE_H_ILLEGAL;\n+\t}\n+\n+\treturn MODE_OK;\n+}\n+\n+static int vc4_crtc_atomic_check(struct drm_crtc *crtc,\n+\t\t\t\t struct drm_crtc_state *state)\n+{\n+\tstruct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);\n+\tstruct drm_connector *conn;\n+\tstruct drm_connector_state *conn_state;\n+\tint i;\n+\n+\tDRM_DEBUG_KMS(\"[CRTC:%d] crtc_atomic_check.\\n\", crtc->base.id);\n+\n+\tfor_each_new_connector_in_state(state->state, conn, conn_state, i) {\n+\t\tif (conn_state->crtc != crtc)\n+\t\t\tcontinue;\n+\n+\t\tvc4_state->margins.left = conn_state->tv.margins.left;\n+\t\tvc4_state->margins.right = conn_state->tv.margins.right;\n+\t\tvc4_state->margins.top = conn_state->tv.margins.top;\n+\t\tvc4_state->margins.bottom = conn_state->tv.margins.bottom;\n+\t\tbreak;\n+\t}\n+\treturn 0;\n+}\n+\n+static void vc4_crtc_atomic_flush(struct drm_crtc *crtc,\n+\t\t\t\t  struct drm_crtc_state *old_state)\n+{\n+\tDRM_DEBUG_KMS(\"[CRTC:%d] crtc_atomic_flush.\\n\",\n+\t\t      crtc->base.id);\n+\tif (crtc->state->active && old_state->active && crtc->state->event)\n+\t\tvc4_crtc_consume_event(crtc);\n+}\n+\n+static void vc4_crtc_handle_page_flip(struct vc4_crtc *vc4_crtc)\n+{\n+\tstruct drm_crtc *crtc = &vc4_crtc->base;\n+\tstruct drm_device *dev = crtc->dev;\n+\tunsigned long flags;\n+\n+\tspin_lock_irqsave(&dev->event_lock, flags);\n+\tif (vc4_crtc->event) {\n+\t\tdrm_crtc_send_vblank_event(crtc, vc4_crtc->event);\n+\t\tvc4_crtc->event = NULL;\n+\t\tdrm_crtc_vblank_put(crtc);\n+\t}\n+\tspin_unlock_irqrestore(&dev->event_lock, flags);\n+}\n+\n+static irqreturn_t vc4_crtc_irq_handler(int irq, void *data)\n+{\n+\tstruct vc4_crtc **crtc_list = data;\n+\tint i;\n+\tu32 stat = readl(crtc_list[0]->regs + SMICS);\n+\tirqreturn_t ret = IRQ_NONE;\n+\tu32 chan;\n+\n+\tif (stat & SMICS_INTERRUPTS) {\n+\t\twritel(0, crtc_list[0]->regs + SMICS);\n+\n+\t\tchan = readl(crtc_list[0]->regs + SMIDSW0);\n+\n+\t\tif ((chan & 0xFFFF0000) != SMI_NEW) {\n+\t\t\t/* Older firmware. Treat the one interrupt as vblank/\n+\t\t\t * complete for all crtcs.\n+\t\t\t */\n+\t\t\tfor (i = 0; crtc_list[i]; i++) {\n+\t\t\t\tif (crtc_list[i]->vblank_enabled)\n+\t\t\t\t\tdrm_crtc_handle_vblank(&crtc_list[i]->base);\n+\t\t\t\tvc4_crtc_handle_page_flip(crtc_list[i]);\n+\t\t\t}\n+\t\t} else {\n+\t\t\tif (chan & 1) {\n+\t\t\t\twritel(SMI_NEW, crtc_list[0]->regs + SMIDSW0);\n+\t\t\t\tif (crtc_list[0]->vblank_enabled)\n+\t\t\t\t\tdrm_crtc_handle_vblank(&crtc_list[0]->base);\n+\t\t\t\tvc4_crtc_handle_page_flip(crtc_list[0]);\n+\t\t\t}\n+\n+\t\t\tif (crtc_list[1]) {\n+\t\t\t\t/* Check for the secondary display too */\n+\t\t\t\tchan = readl(crtc_list[0]->regs + SMIDSW1);\n+\n+\t\t\t\tif (chan & 1) {\n+\t\t\t\t\twritel(SMI_NEW, crtc_list[0]->regs + SMIDSW1);\n+\n+\t\t\t\t\tif (crtc_list[1]->vblank_enabled)\n+\t\t\t\t\t\tdrm_crtc_handle_vblank(&crtc_list[1]->base);\n+\t\t\t\t\tvc4_crtc_handle_page_flip(crtc_list[1]);\n+\t\t\t\t}\n+\t\t\t}\n+\t\t}\n+\n+\t\tret = IRQ_HANDLED;\n+\t}\n+\n+\treturn ret;\n+}\n+\n+static int vc4_fkms_page_flip(struct drm_crtc *crtc,\n+\t\t\t      struct drm_framebuffer *fb,\n+\t\t\t      struct drm_pending_vblank_event *event,\n+\t\t\t      uint32_t flags,\n+\t\t\t      struct drm_modeset_acquire_ctx *ctx)\n+{\n+\tif (flags & DRM_MODE_PAGE_FLIP_ASYNC) {\n+\t\tDRM_ERROR(\"Async flips aren't allowed\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\treturn drm_atomic_helper_page_flip(crtc, fb, event, flags, ctx);\n+}\n+\n+static struct drm_crtc_state *\n+vc4_fkms_crtc_duplicate_state(struct drm_crtc *crtc)\n+{\n+\tstruct vc4_crtc_state *vc4_state, *old_vc4_state;\n+\n+\tvc4_state = kzalloc(sizeof(*vc4_state), GFP_KERNEL);\n+\tif (!vc4_state)\n+\t\treturn NULL;\n+\n+\told_vc4_state = to_vc4_crtc_state(crtc->state);\n+\tvc4_state->margins = old_vc4_state->margins;\n+\n+\t__drm_atomic_helper_crtc_duplicate_state(crtc, &vc4_state->base);\n+\treturn &vc4_state->base;\n+}\n+\n+static void\n+vc4_fkms_crtc_reset(struct drm_crtc *crtc)\n+{\n+\tif (crtc->state)\n+\t\t__drm_atomic_helper_crtc_destroy_state(crtc->state);\n+\n+\tcrtc->state = kzalloc(sizeof(*crtc->state), GFP_KERNEL);\n+\tif (crtc->state)\n+\t\tcrtc->state->crtc = crtc;\n+}\n+\n+static int vc4_fkms_enable_vblank(struct drm_crtc *crtc)\n+{\n+\tstruct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);\n+\n+\tDRM_DEBUG_KMS(\"[CRTC:%d] enable_vblank.\\n\",\n+\t\t      crtc->base.id);\n+\tvc4_crtc->vblank_enabled = true;\n+\n+\treturn 0;\n+}\n+\n+static void vc4_fkms_disable_vblank(struct drm_crtc *crtc)\n+{\n+\tstruct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);\n+\n+\tDRM_DEBUG_KMS(\"[CRTC:%d] disable_vblank.\\n\",\n+\t\t      crtc->base.id);\n+\tvc4_crtc->vblank_enabled = false;\n+}\n+\n+static const struct drm_crtc_funcs vc4_crtc_funcs = {\n+\t.set_config = drm_atomic_helper_set_config,\n+\t.destroy = drm_crtc_cleanup,\n+\t.page_flip = vc4_fkms_page_flip,\n+\t.set_property = NULL,\n+\t.cursor_set = NULL, /* handled by drm_mode_cursor_universal */\n+\t.cursor_move = NULL, /* handled by drm_mode_cursor_universal */\n+\t.reset = vc4_fkms_crtc_reset,\n+\t.atomic_duplicate_state = vc4_fkms_crtc_duplicate_state,\n+\t.atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,\n+\t.enable_vblank = vc4_fkms_enable_vblank,\n+\t.disable_vblank = vc4_fkms_disable_vblank,\n+};\n+\n+static const struct drm_crtc_helper_funcs vc4_crtc_helper_funcs = {\n+\t.mode_set_nofb = vc4_crtc_mode_set_nofb,\n+\t.mode_valid = vc4_crtc_mode_valid,\n+\t.atomic_check = vc4_crtc_atomic_check,\n+\t.atomic_flush = vc4_crtc_atomic_flush,\n+\t.atomic_enable = vc4_crtc_enable,\n+\t.atomic_disable = vc4_crtc_disable,\n+};\n+\n+static const struct of_device_id vc4_firmware_kms_dt_match[] = {\n+\t{ .compatible = \"raspberrypi,rpi-firmware-kms\" },\n+\t{ .compatible = \"raspberrypi,rpi-firmware-kms-2711\",\n+\t  .data = (void *)1 },\n+\t{}\n+};\n+\n+static enum drm_connector_status\n+vc4_fkms_connector_detect(struct drm_connector *connector, bool force)\n+{\n+\tDRM_DEBUG_KMS(\"connector detect.\\n\");\n+\treturn connector_status_connected;\n+}\n+\n+/* Queries the firmware to populate a drm_mode structure for this display */\n+static int vc4_fkms_get_fw_mode(struct vc4_fkms_connector *fkms_connector,\n+\t\t\t\tstruct drm_display_mode *mode)\n+{\n+\tstruct vc4_dev *vc4 = fkms_connector->vc4_dev;\n+\tstruct set_timings timings = { 0 };\n+\tint ret;\n+\n+\ttimings.display = fkms_connector->display_number;\n+\n+\tret = rpi_firmware_property(vc4->firmware,\n+\t\t\t\t    RPI_FIRMWARE_GET_DISPLAY_TIMING, &timings,\n+\t\t\t\t    sizeof(timings));\n+\tif (ret || !timings.clock)\n+\t\t/* No mode returned - abort */\n+\t\treturn -1;\n+\n+\t/* Equivalent to DRM_MODE macro. */\n+\tmemset(mode, 0, sizeof(*mode));\n+\tstrncpy(mode->name, \"FIXED_MODE\", sizeof(mode->name));\n+\tmode->status = 0;\n+\tmode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;\n+\tmode->clock = timings.clock;\n+\tmode->hdisplay = timings.hdisplay;\n+\tmode->hsync_start = timings.hsync_start;\n+\tmode->hsync_end = timings.hsync_end;\n+\tmode->htotal = timings.htotal;\n+\tmode->hskew = 0;\n+\tmode->vdisplay = timings.vdisplay;\n+\tmode->vsync_start = timings.vsync_start;\n+\tmode->vsync_end = timings.vsync_end;\n+\tmode->vtotal = timings.vtotal;\n+\tmode->vscan = timings.vscan;\n+\n+\tif (timings.flags & TIMINGS_FLAGS_H_SYNC_POS)\n+\t\tmode->flags |= DRM_MODE_FLAG_PHSYNC;\n+\telse\n+\t\tmode->flags |= DRM_MODE_FLAG_NHSYNC;\n+\n+\tif (timings.flags & TIMINGS_FLAGS_V_SYNC_POS)\n+\t\tmode->flags |= DRM_MODE_FLAG_PVSYNC;\n+\telse\n+\t\tmode->flags |= DRM_MODE_FLAG_NVSYNC;\n+\n+\tif (timings.flags & TIMINGS_FLAGS_INTERLACE)\n+\t\tmode->flags |= DRM_MODE_FLAG_INTERLACE;\n+\n+\treturn 0;\n+}\n+\n+static int vc4_fkms_get_edid_block(void *data, u8 *buf, unsigned int block,\n+\t\t\t\t   size_t len)\n+{\n+\tstruct vc4_fkms_connector *fkms_connector =\n+\t\t\t\t\t(struct vc4_fkms_connector *)data;\n+\tstruct vc4_dev *vc4 = fkms_connector->vc4_dev;\n+\tstruct mailbox_get_edid mb = {\n+\t\t.tag1 = { RPI_FIRMWARE_GET_EDID_BLOCK_DISPLAY,\n+\t\t\t  128 + 8, 0 },\n+\t\t.block = block,\n+\t\t.display_number = fkms_connector->display_number,\n+\t};\n+\tint ret = 0;\n+\n+\tret = rpi_firmware_property_list(vc4->firmware, &mb, sizeof(mb));\n+\n+\tif (!ret)\n+\t\tmemcpy(buf, mb.edid, len);\n+\n+\treturn ret;\n+}\n+\n+static int vc4_fkms_connector_get_modes(struct drm_connector *connector)\n+{\n+\tstruct vc4_fkms_connector *fkms_connector =\n+\t\t\t\t\tto_vc4_fkms_connector(connector);\n+\tstruct drm_encoder *encoder = fkms_connector->encoder;\n+\tstruct vc4_fkms_encoder *vc4_encoder = to_vc4_fkms_encoder(encoder);\n+\tstruct drm_display_mode fw_mode;\n+\tstruct drm_display_mode *mode;\n+\tstruct edid *edid;\n+\tint num_modes;\n+\n+\tif (!vc4_fkms_get_fw_mode(fkms_connector, &fw_mode)) {\n+\t\tdrm_mode_debug_printmodeline(&fw_mode);\n+\t\tmode = drm_mode_duplicate(connector->dev,\n+\t\t\t\t\t  &fw_mode);\n+\t\tdrm_mode_probed_add(connector, mode);\n+\t\tnum_modes = 1;\t/* 1 mode */\n+\t} else {\n+\t\tedid = drm_do_get_edid(connector, vc4_fkms_get_edid_block,\n+\t\t\t\t       fkms_connector);\n+\n+\t\t/* FIXME: Can we do CEC?\n+\t\t * cec_s_phys_addr_from_edid(vc4->hdmi->cec_adap, edid);\n+\t\t * if (!edid)\n+\t\t *\treturn -ENODEV;\n+\t\t */\n+\n+\t\tvc4_encoder->hdmi_monitor = drm_detect_hdmi_monitor(edid);\n+\n+\t\tdrm_connector_update_edid_property(connector, edid);\n+\t\tnum_modes = drm_add_edid_modes(connector, edid);\n+\t\tkfree(edid);\n+\t}\n+\n+\treturn num_modes;\n+}\n+\n+/* This is the DSI panel resolution. Use this as a default should the firmware\n+ * not respond to our request for the timings.\n+ */\n+static const struct drm_display_mode lcd_mode = {\n+\tDRM_MODE(\"800x480\", DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,\n+\t\t 25979400 / 1000,\n+\t\t 800, 800 + 1, 800 + 1 + 2, 800 + 1 + 2 + 46, 0,\n+\t\t 480, 480 + 7, 480 + 7 + 2, 480 + 7 + 2 + 21, 0,\n+\t\t 0)\n+};\n+\n+static int vc4_fkms_lcd_connector_get_modes(struct drm_connector *connector)\n+{\n+\tstruct vc4_fkms_connector *fkms_connector =\n+\t\t\t\t\tto_vc4_fkms_connector(connector);\n+\tstruct drm_display_mode *mode;\n+\tstruct drm_display_mode fw_mode;\n+\n+\tif (!vc4_fkms_get_fw_mode(fkms_connector, &fw_mode) && fw_mode.clock)\n+\t\tmode = drm_mode_duplicate(connector->dev,\n+\t\t\t\t\t  &fw_mode);\n+\telse\n+\t\tmode = drm_mode_duplicate(connector->dev,\n+\t\t\t\t\t  &lcd_mode);\n+\n+\tif (!mode) {\n+\t\tDRM_ERROR(\"Failed to create a new display mode\\n\");\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\tdrm_mode_probed_add(connector, mode);\n+\n+\t/* We have one mode */\n+\treturn 1;\n+}\n+\n+static struct drm_encoder *\n+vc4_fkms_connector_best_encoder(struct drm_connector *connector)\n+{\n+\tstruct vc4_fkms_connector *fkms_connector =\n+\t\tto_vc4_fkms_connector(connector);\n+\tDRM_DEBUG_KMS(\"best_connector.\\n\");\n+\treturn fkms_connector->encoder;\n+}\n+\n+static void vc4_fkms_connector_destroy(struct drm_connector *connector)\n+{\n+\tDRM_DEBUG_KMS(\"[CONNECTOR:%d] destroy.\\n\",\n+\t\t      connector->base.id);\n+\tdrm_connector_unregister(connector);\n+\tdrm_connector_cleanup(connector);\n+}\n+\n+/**\n+ * vc4_connector_duplicate_state - duplicate connector state\n+ * @connector: digital connector\n+ *\n+ * Allocates and returns a copy of the connector state (both common and\n+ * digital connector specific) for the specified connector.\n+ *\n+ * Returns: The newly allocated connector state, or NULL on failure.\n+ */\n+struct drm_connector_state *\n+vc4_connector_duplicate_state(struct drm_connector *connector)\n+{\n+\tstruct vc4_fkms_connector_state *state;\n+\n+\tstate = kmemdup(connector->state, sizeof(*state), GFP_KERNEL);\n+\tif (!state)\n+\t\treturn NULL;\n+\n+\t__drm_atomic_helper_connector_duplicate_state(connector, &state->base);\n+\treturn &state->base;\n+}\n+\n+/**\n+ * vc4_connector_atomic_get_property - hook for connector->atomic_get_property.\n+ * @connector: Connector to get the property for.\n+ * @state: Connector state to retrieve the property from.\n+ * @property: Property to retrieve.\n+ * @val: Return value for the property.\n+ *\n+ * Returns the atomic property value for a digital connector.\n+ */\n+int vc4_connector_atomic_get_property(struct drm_connector *connector,\n+\t\t\t\t      const struct drm_connector_state *state,\n+\t\t\t\t      struct drm_property *property,\n+\t\t\t\t      uint64_t *val)\n+{\n+\tstruct vc4_fkms_connector *fkms_connector =\n+\t\t\t\t\tto_vc4_fkms_connector(connector);\n+\tstruct vc4_fkms_connector_state *vc4_conn_state =\n+\t\t\t\t\tto_vc4_fkms_connector_state(state);\n+\n+\tif (property == fkms_connector->broadcast_rgb_property) {\n+\t\t*val = vc4_conn_state->broadcast_rgb;\n+\t} else {\n+\t\tDRM_DEBUG_ATOMIC(\"Unknown property [PROP:%d:%s]\\n\",\n+\t\t\t\t property->base.id, property->name);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+/**\n+ * vc4_connector_atomic_set_property - hook for connector->atomic_set_property.\n+ * @connector: Connector to set the property for.\n+ * @state: Connector state to set the property on.\n+ * @property: Property to set.\n+ * @val: New value for the property.\n+ *\n+ * Sets the atomic property value for a digital connector.\n+ */\n+int vc4_connector_atomic_set_property(struct drm_connector *connector,\n+\t\t\t\t      struct drm_connector_state *state,\n+\t\t\t\t      struct drm_property *property,\n+\t\t\t\t      uint64_t val)\n+{\n+\tstruct vc4_fkms_connector *fkms_connector =\n+\t\t\t\t\tto_vc4_fkms_connector(connector);\n+\tstruct vc4_fkms_connector_state *vc4_conn_state =\n+\t\t\t\t\tto_vc4_fkms_connector_state(state);\n+\n+\tif (property == fkms_connector->broadcast_rgb_property) {\n+\t\tvc4_conn_state->broadcast_rgb = val;\n+\t\treturn 0;\n+\t}\n+\n+\tDRM_DEBUG_ATOMIC(\"Unknown property [PROP:%d:%s]\\n\",\n+\t\t\t property->base.id, property->name);\n+\treturn -EINVAL;\n+}\n+\n+static void vc4_hdmi_connector_reset(struct drm_connector *connector)\n+{\n+\tdrm_atomic_helper_connector_reset(connector);\n+\tdrm_atomic_helper_connector_tv_reset(connector);\n+}\n+\n+static const struct drm_connector_funcs vc4_fkms_connector_funcs = {\n+\t.detect = vc4_fkms_connector_detect,\n+\t.fill_modes = drm_helper_probe_single_connector_modes,\n+\t.destroy = vc4_fkms_connector_destroy,\n+\t.reset = vc4_hdmi_connector_reset,\n+\t.atomic_duplicate_state = vc4_connector_duplicate_state,\n+\t.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,\n+\t.atomic_get_property = vc4_connector_atomic_get_property,\n+\t.atomic_set_property = vc4_connector_atomic_set_property,\n+};\n+\n+static const struct drm_connector_helper_funcs vc4_fkms_connector_helper_funcs = {\n+\t.get_modes = vc4_fkms_connector_get_modes,\n+\t.best_encoder = vc4_fkms_connector_best_encoder,\n+};\n+\n+static const struct drm_connector_helper_funcs vc4_fkms_lcd_conn_helper_funcs = {\n+\t.get_modes = vc4_fkms_lcd_connector_get_modes,\n+\t.best_encoder = vc4_fkms_connector_best_encoder,\n+};\n+\n+static const struct drm_prop_enum_list broadcast_rgb_names[] = {\n+\t{ VC4_BROADCAST_RGB_AUTO, \"Automatic\" },\n+\t{ VC4_BROADCAST_RGB_FULL, \"Full\" },\n+\t{ VC4_BROADCAST_RGB_LIMITED, \"Limited 16:235\" },\n+};\n+\n+static void\n+vc4_attach_broadcast_rgb_property(struct vc4_fkms_connector *fkms_connector)\n+{\n+\tstruct drm_device *dev = fkms_connector->base.dev;\n+\tstruct drm_property *prop;\n+\n+\tprop = fkms_connector->broadcast_rgb_property;\n+\tif (!prop) {\n+\t\tprop = drm_property_create_enum(dev, DRM_MODE_PROP_ENUM,\n+\t\t\t\t\t\t\"Broadcast RGB\",\n+\t\t\t\t\t\tbroadcast_rgb_names,\n+\t\t\t\t\t\tARRAY_SIZE(broadcast_rgb_names));\n+\t\tif (!prop)\n+\t\t\treturn;\n+\n+\t\tfkms_connector->broadcast_rgb_property = prop;\n+\t}\n+\n+\tdrm_object_attach_property(&fkms_connector->base.base, prop, 0);\n+}\n+\n+static struct drm_connector *\n+vc4_fkms_connector_init(struct drm_device *dev, struct drm_encoder *encoder,\n+\t\t\tu32 display_num)\n+{\n+\tstruct drm_connector *connector = NULL;\n+\tstruct vc4_fkms_connector *fkms_connector;\n+\tstruct vc4_fkms_connector_state *conn_state = NULL;\n+\tstruct vc4_dev *vc4_dev = to_vc4_dev(dev);\n+\tint ret = 0;\n+\n+\tDRM_DEBUG_KMS(\"connector_init, display_num %u\\n\", display_num);\n+\n+\tfkms_connector = devm_kzalloc(dev->dev, sizeof(*fkms_connector),\n+\t\t\t\t      GFP_KERNEL);\n+\tif (!fkms_connector)\n+\t\treturn ERR_PTR(-ENOMEM);\n+\n+\t/*\n+\t * Allocate enough memory to hold vc4_fkms_connector_state,\n+\t */\n+\tconn_state = kzalloc(sizeof(*conn_state), GFP_KERNEL);\n+\tif (!conn_state) {\n+\t\tkfree(fkms_connector);\n+\t\treturn ERR_PTR(-ENOMEM);\n+\t}\n+\n+\tconnector = &fkms_connector->base;\n+\n+\tfkms_connector->encoder = encoder;\n+\tfkms_connector->display_number = display_num;\n+\tfkms_connector->display_type = vc4_get_display_type(display_num);\n+\tfkms_connector->vc4_dev = vc4_dev;\n+\n+\t__drm_atomic_helper_connector_reset(connector,\n+\t\t\t\t\t    &conn_state->base);\n+\n+\tif (fkms_connector->display_type == DRM_MODE_ENCODER_DSI) {\n+\t\tdrm_connector_init(dev, connector, &vc4_fkms_connector_funcs,\n+\t\t\t\t   DRM_MODE_CONNECTOR_DSI);\n+\t\tdrm_connector_helper_add(connector,\n+\t\t\t\t\t &vc4_fkms_lcd_conn_helper_funcs);\n+\t\tconnector->interlace_allowed = 0;\n+\t} else if (fkms_connector->display_type == DRM_MODE_ENCODER_TVDAC) {\n+\t\tdrm_connector_init(dev, connector, &vc4_fkms_connector_funcs,\n+\t\t\t\t   DRM_MODE_CONNECTOR_Composite);\n+\t\tdrm_connector_helper_add(connector,\n+\t\t\t\t\t &vc4_fkms_lcd_conn_helper_funcs);\n+\t\tconnector->interlace_allowed = 1;\n+\t} else {\n+\t\tdrm_connector_init(dev, connector, &vc4_fkms_connector_funcs,\n+\t\t\t\t   DRM_MODE_CONNECTOR_HDMIA);\n+\t\tdrm_connector_helper_add(connector,\n+\t\t\t\t\t &vc4_fkms_connector_helper_funcs);\n+\t\tconnector->interlace_allowed = 1;\n+\t}\n+\n+\tret = drm_mode_create_tv_margin_properties(dev);\n+\tif (ret)\n+\t\tgoto fail;\n+\n+\tdrm_connector_attach_tv_margin_properties(connector);\n+\n+\tconnector->polled = (DRM_CONNECTOR_POLL_CONNECT |\n+\t\t\t     DRM_CONNECTOR_POLL_DISCONNECT);\n+\n+\tconnector->doublescan_allowed = 0;\n+\n+\tvc4_attach_broadcast_rgb_property(fkms_connector);\n+\n+\tdrm_connector_attach_encoder(connector, encoder);\n+\n+\treturn connector;\n+\n+ fail:\n+\tif (connector)\n+\t\tvc4_fkms_connector_destroy(connector);\n+\n+\treturn ERR_PTR(ret);\n+}\n+\n+static void vc4_fkms_encoder_destroy(struct drm_encoder *encoder)\n+{\n+\tDRM_DEBUG_KMS(\"Encoder_destroy\\n\");\n+\tdrm_encoder_cleanup(encoder);\n+}\n+\n+static const struct drm_encoder_funcs vc4_fkms_encoder_funcs = {\n+\t.destroy = vc4_fkms_encoder_destroy,\n+};\n+\n+static void vc4_fkms_display_power(struct drm_encoder *encoder, bool power)\n+{\n+\tstruct vc4_fkms_encoder *vc4_encoder = to_vc4_fkms_encoder(encoder);\n+\tstruct vc4_dev *vc4 = to_vc4_dev(encoder->dev);\n+\n+\tstruct mailbox_display_pwr pwr = {\n+\t\t.tag1 = {RPI_FIRMWARE_SET_DISPLAY_POWER, 8, 0, },\n+\t\t.display = vc4_encoder->display_num,\n+\t\t.state = power ? 1 : 0,\n+\t};\n+\n+\trpi_firmware_property_list(vc4->firmware, &pwr, sizeof(pwr));\n+}\n+\n+static void vc4_fkms_encoder_enable(struct drm_encoder *encoder)\n+{\n+\tvc4_fkms_display_power(encoder, true);\n+\tDRM_DEBUG_KMS(\"Encoder_enable\\n\");\n+}\n+\n+static void vc4_fkms_encoder_disable(struct drm_encoder *encoder)\n+{\n+\tvc4_fkms_display_power(encoder, false);\n+\tDRM_DEBUG_KMS(\"Encoder_disable\\n\");\n+}\n+\n+static const struct drm_encoder_helper_funcs vc4_fkms_encoder_helper_funcs = {\n+\t.enable = vc4_fkms_encoder_enable,\n+\t.disable = vc4_fkms_encoder_disable,\n+};\n+\n+static int vc4_fkms_create_screen(struct device *dev, struct drm_device *drm,\n+\t\t\t\t  int display_idx, int display_ref,\n+\t\t\t\t  struct vc4_crtc **ret_crtc)\n+{\n+\tstruct vc4_dev *vc4 = to_vc4_dev(drm);\n+\tstruct vc4_crtc *vc4_crtc;\n+\tstruct vc4_fkms_encoder *vc4_encoder;\n+\tstruct drm_crtc *crtc;\n+\tstruct drm_plane *destroy_plane, *temp;\n+\tstruct mailbox_blank_display blank = {\n+\t\t.tag1 = {RPI_FIRMWARE_FRAMEBUFFER_SET_DISPLAY_NUM, 4, 0, },\n+\t\t.display = display_idx,\n+\t\t.tag2 = { RPI_FIRMWARE_FRAMEBUFFER_BLANK, 4, 0, },\n+\t\t.blank = 1,\n+\t};\n+\tstruct drm_plane *planes[PLANES_PER_CRTC];\n+\tint ret, i;\n+\n+\tvc4_crtc = devm_kzalloc(dev, sizeof(*vc4_crtc), GFP_KERNEL);\n+\tif (!vc4_crtc)\n+\t\treturn -ENOMEM;\n+\tcrtc = &vc4_crtc->base;\n+\n+\tvc4_crtc->display_number = display_ref;\n+\tvc4_crtc->display_type = vc4_get_display_type(display_ref);\n+\n+\t/* Blank the firmware provided framebuffer */\n+\trpi_firmware_property_list(vc4->firmware, &blank, sizeof(blank));\n+\n+\tfor (i = 0; i < PLANES_PER_CRTC; i++) {\n+\t\tplanes[i] = vc4_fkms_plane_init(drm,\n+\t\t\t\t\t\t(i == 0) ?\n+\t\t\t\t\t\t  DRM_PLANE_TYPE_PRIMARY :\n+\t\t\t\t\t\t  (i == PLANES_PER_CRTC - 1) ?\n+\t\t\t\t\t\t\tDRM_PLANE_TYPE_CURSOR :\n+\t\t\t\t\t\t\tDRM_PLANE_TYPE_OVERLAY,\n+\t\t\t\t\t\tdisplay_ref,\n+\t\t\t\t\t\ti + (display_idx * PLANES_PER_CRTC)\n+\t\t\t\t\t       );\n+\t\tif (IS_ERR(planes[i])) {\n+\t\t\tdev_err(dev, \"failed to construct plane %u\\n\", i);\n+\t\t\tret = PTR_ERR(planes[i]);\n+\t\t\tgoto err;\n+\t\t}\n+\t}\n+\n+\tdrm_crtc_init_with_planes(drm, crtc, planes[0],\n+\t\t\t\t  planes[PLANES_PER_CRTC - 1], &vc4_crtc_funcs,\n+\t\t\t\t  NULL);\n+\tdrm_crtc_helper_add(crtc, &vc4_crtc_helper_funcs);\n+\n+\t/* Update the possible_crtcs mask for the overlay plane(s) */\n+\tfor (i = 1; i < (PLANES_PER_CRTC - 1); i++)\n+\t\tplanes[i]->possible_crtcs = drm_crtc_mask(crtc);\n+\n+\tvc4_encoder = devm_kzalloc(dev, sizeof(*vc4_encoder), GFP_KERNEL);\n+\tif (!vc4_encoder)\n+\t\treturn -ENOMEM;\n+\tvc4_crtc->encoder = &vc4_encoder->base;\n+\n+\tvc4_encoder->display_num = display_ref;\n+\tvc4_encoder->base.possible_crtcs |= drm_crtc_mask(crtc);\n+\n+\tdrm_encoder_init(drm, &vc4_encoder->base, &vc4_fkms_encoder_funcs,\n+\t\t\t vc4_crtc->display_type, NULL);\n+\tdrm_encoder_helper_add(&vc4_encoder->base,\n+\t\t\t       &vc4_fkms_encoder_helper_funcs);\n+\n+\tvc4_crtc->connector = vc4_fkms_connector_init(drm, &vc4_encoder->base,\n+\t\t\t\t\t\t      display_ref);\n+\tif (IS_ERR(vc4_crtc->connector)) {\n+\t\tret = PTR_ERR(vc4_crtc->connector);\n+\t\tgoto err_destroy_encoder;\n+\t}\n+\n+\t*ret_crtc = vc4_crtc;\n+\n+\treturn 0;\n+\n+err_destroy_encoder:\n+\tvc4_fkms_encoder_destroy(vc4_crtc->encoder);\n+\tlist_for_each_entry_safe(destroy_plane, temp,\n+\t\t\t\t &drm->mode_config.plane_list, head) {\n+\t\tif (destroy_plane->possible_crtcs == 1 << drm_crtc_index(crtc))\n+\t\t\tdestroy_plane->funcs->destroy(destroy_plane);\n+\t}\n+err:\n+\treturn ret;\n+}\n+\n+static int vc4_fkms_bind(struct device *dev, struct device *master, void *data)\n+{\n+\tstruct platform_device *pdev = to_platform_device(dev);\n+\tstruct drm_device *drm = dev_get_drvdata(master);\n+\tstruct vc4_dev *vc4 = to_vc4_dev(drm);\n+\tstruct device_node *firmware_node;\n+\tconst struct of_device_id *match;\n+\tstruct vc4_crtc **crtc_list;\n+\tu32 num_displays, display_num;\n+\tstruct vc4_fkms *fkms;\n+\tint ret;\n+\tu32 display_id;\n+\n+\tvc4->firmware_kms = true;\n+\n+\tfkms = devm_kzalloc(dev, sizeof(*fkms), GFP_KERNEL);\n+\tif (!fkms)\n+\t\treturn -ENOMEM;\n+\n+\tmatch = of_match_device(vc4_firmware_kms_dt_match, dev);\n+\tif (!match)\n+\t\treturn -ENODEV;\n+\tif (match->data)\n+\t\tfkms->bcm2711 = true;\n+\n+\tfirmware_node = of_parse_phandle(dev->of_node, \"brcm,firmware\", 0);\n+\tvc4->firmware = rpi_firmware_get(firmware_node);\n+\tif (!vc4->firmware) {\n+\t\tDRM_DEBUG(\"Failed to get Raspberry Pi firmware reference.\\n\");\n+\t\treturn -EPROBE_DEFER;\n+\t}\n+\tof_node_put(firmware_node);\n+\n+\tret = rpi_firmware_property(vc4->firmware,\n+\t\t\t\t    RPI_FIRMWARE_FRAMEBUFFER_GET_NUM_DISPLAYS,\n+\t\t\t\t    &num_displays, sizeof(u32));\n+\n+\t/* If we fail to get the number of displays, then\n+\t * assume old firmware that doesn't have the mailbox call, so just\n+\t * set one display\n+\t */\n+\tif (ret) {\n+\t\tnum_displays = 1;\n+\t\tDRM_WARN(\"Unable to determine number of displays - assuming 1\\n\");\n+\t\tret = 0;\n+\t}\n+\n+\tret = rpi_firmware_property(vc4->firmware,\n+\t\t\t\t    RPI_FIRMWARE_GET_DISPLAY_CFG,\n+\t\t\t\t    &fkms->cfg, sizeof(fkms->cfg));\n+\n+\tif (ret)\n+\t\treturn -EINVAL;\n+\t/* The firmware works in Hz. This will be compared against kHz, so div\n+\t * 1000 now rather than multiple times later.\n+\t */\n+\tfkms->cfg.max_pixel_clock[0] /= 1000;\n+\tfkms->cfg.max_pixel_clock[1] /= 1000;\n+\n+\t/* Allocate a list, with space for a NULL on the end */\n+\tcrtc_list = devm_kzalloc(dev, sizeof(crtc_list) * (num_displays + 1),\n+\t\t\t\t GFP_KERNEL);\n+\tif (!crtc_list)\n+\t\treturn -ENOMEM;\n+\n+\tfor (display_num = 0; display_num < num_displays; display_num++) {\n+\t\tdisplay_id = display_num;\n+\t\tret = rpi_firmware_property(vc4->firmware,\n+\t\t\t\t\t    RPI_FIRMWARE_FRAMEBUFFER_GET_DISPLAY_ID,\n+\t\t\t\t\t    &display_id, sizeof(display_id));\n+\t\t/* FIXME: Determine the correct error handling here.\n+\t\t * Should we fail to create the one \"screen\" but keep the\n+\t\t * others, or fail the whole thing?\n+\t\t */\n+\t\tif (ret)\n+\t\t\tDRM_ERROR(\"Failed to get display id %u\\n\", display_num);\n+\n+\t\tret = vc4_fkms_create_screen(dev, drm, display_num, display_id,\n+\t\t\t\t\t     &crtc_list[display_num]);\n+\t\tif (ret)\n+\t\t\tDRM_ERROR(\"Oh dear, failed to create display %u\\n\",\n+\t\t\t\t  display_num);\n+\t}\n+\n+\tif (num_displays > 0) {\n+\t\t/* Map the SMI interrupt reg */\n+\t\tcrtc_list[0]->regs = vc4_ioremap_regs(pdev, 0);\n+\t\tif (IS_ERR(crtc_list[0]->regs))\n+\t\t\tDRM_ERROR(\"Oh dear, failed to map registers\\n\");\n+\n+\t\twritel(0, crtc_list[0]->regs + SMICS);\n+\t\tret = devm_request_irq(dev, platform_get_irq(pdev, 0),\n+\t\t\t\t       vc4_crtc_irq_handler, 0,\n+\t\t\t\t       \"vc4 firmware kms\", crtc_list);\n+\t\tif (ret)\n+\t\t\tDRM_ERROR(\"Oh dear, failed to register IRQ\\n\");\n+\t} else {\n+\t\tDRM_WARN(\"No displays found. Consider forcing hotplug if HDMI is attached\\n\");\n+\t}\n+\n+\tvc4->fkms = fkms;\n+\n+\tplatform_set_drvdata(pdev, crtc_list);\n+\n+\treturn 0;\n+}\n+\n+static void vc4_fkms_unbind(struct device *dev, struct device *master,\n+\t\t\t    void *data)\n+{\n+\tstruct platform_device *pdev = to_platform_device(dev);\n+\tstruct vc4_crtc **crtc_list = dev_get_drvdata(dev);\n+\tint i;\n+\n+\tfor (i = 0; crtc_list[i]; i++) {\n+\t\tvc4_fkms_connector_destroy(crtc_list[i]->connector);\n+\t\tvc4_fkms_encoder_destroy(crtc_list[i]->encoder);\n+\t\tdrm_crtc_cleanup(&crtc_list[i]->base);\n+\t}\n+\n+\tplatform_set_drvdata(pdev, NULL);\n+}\n+\n+static const struct component_ops vc4_fkms_ops = {\n+\t.bind   = vc4_fkms_bind,\n+\t.unbind = vc4_fkms_unbind,\n+};\n+\n+static int vc4_fkms_probe(struct platform_device *pdev)\n+{\n+\treturn component_add(&pdev->dev, &vc4_fkms_ops);\n+}\n+\n+static int vc4_fkms_remove(struct platform_device *pdev)\n+{\n+\tcomponent_del(&pdev->dev, &vc4_fkms_ops);\n+\treturn 0;\n+}\n+\n+struct platform_driver vc4_firmware_kms_driver = {\n+\t.probe = vc4_fkms_probe,\n+\t.remove = vc4_fkms_remove,\n+\t.driver = {\n+\t\t.name = \"vc4_firmware_kms\",\n+\t\t.of_match_table = vc4_firmware_kms_dt_match,\n+\t},\n+};\n--- a/drivers/gpu/drm/vc4/vc4_kms.c\n+++ b/drivers/gpu/drm/vc4/vc4_kms.c\n@@ -154,6 +154,9 @@ vc4_ctm_commit(struct vc4_dev *vc4, stru\n \tstruct vc4_ctm_state *ctm_state = to_vc4_ctm_state(vc4->ctm_manager.state);\n \tstruct drm_color_ctm *ctm = ctm_state->ctm;\n \n+\tif (vc4->firmware_kms)\n+\t\treturn;\n+\n \tif (ctm_state->fifo) {\n \t\tHVS_WRITE(SCALER_OLEDCOEF2,\n \t\t\t  VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[0]),\n@@ -315,14 +318,14 @@ vc4_atomic_complete_commit(struct drm_at\n \tfor_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {\n \t\tstruct vc4_crtc_state *vc4_crtc_state;\n \n-\t\tif (!new_crtc_state->commit)\n+\t\tif (!new_crtc_state->commit || vc4->firmware_kms)\n \t\t\tcontinue;\n \n \t\tvc4_crtc_state = to_vc4_crtc_state(new_crtc_state);\n \t\tvc4_hvs_mask_underrun(dev, vc4_crtc_state->assigned_channel);\n \t}\n \n-\tif (vc4->hvs->hvs5)\n+\tif (vc4->hvs && vc4->hvs->hvs5)\n \t\tclk_set_min_rate(hvs->core_clk, 500000000);\n \n \tdrm_atomic_helper_wait_for_fences(dev, state, false);\n@@ -333,10 +336,12 @@ vc4_atomic_complete_commit(struct drm_at\n \n \tvc4_ctm_commit(vc4, state);\n \n-\tif (vc4->hvs->hvs5)\n-\t\tvc5_hvs_pv_muxing_commit(vc4, state);\n-\telse\n-\t\tvc4_hvs_pv_muxing_commit(vc4, state);\n+\tif (!vc4->firmware_kms) {\n+\t\tif (vc4->hvs->hvs5)\n+\t\t\tvc5_hvs_pv_muxing_commit(vc4, state);\n+\t\telse\n+\t\t\tvc4_hvs_pv_muxing_commit(vc4, state);\n+\t}\n \n \tdrm_atomic_helper_commit_planes(dev, state, 0);\n \n@@ -352,7 +357,7 @@ vc4_atomic_complete_commit(struct drm_at\n \n \tdrm_atomic_helper_commit_cleanup_done(state);\n \n-\tif (vc4->hvs->hvs5)\n+\tif (vc4->hvs && vc4->hvs->hvs5)\n \t\tclk_set_min_rate(hvs->core_clk, 0);\n \n \tdrm_atomic_state_put(state);\n@@ -413,7 +418,8 @@ static int vc4_atomic_commit(struct drm_\n \t * drm_atomic_helper_setup_commit() from auto-completing\n \t * commit->flip_done.\n \t */\n-\tstate->legacy_cursor_update = false;\n+\tif (!vc4->firmware_kms)\n+\t\tstate->legacy_cursor_update = false;\n \tret = drm_atomic_helper_setup_commit(state, nonblock);\n \tif (ret)\n \t\treturn ret;\n@@ -778,6 +784,7 @@ static int vc4_hvs_channels_obj_init(str\n static int vc4_pv_muxing_atomic_check(struct drm_device *dev,\n \t\t\t\t      struct drm_atomic_state *state)\n {\n+\tstruct vc4_dev *vc4 = to_vc4_dev(state->dev);\n \tstruct vc4_hvs_state *hvs_new_state;\n \tstruct drm_crtc_state *old_crtc_state, *new_crtc_state;\n \tstruct drm_crtc *crtc;\n@@ -795,6 +802,9 @@ static int vc4_pv_muxing_atomic_check(st\n \t\tstruct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);\n \t\tunsigned int matching_channels;\n \n+\t\tif (vc4->firmware_kms)\n+\t\t\tcontinue;\n+\n \t\t/* Nothing to do here, let's skip it */\n \t\tif (old_crtc_state->enable == new_crtc_state->enable)\n \t\t\tcontinue;\n@@ -913,6 +923,7 @@ int vc4_kms_load(struct drm_device *dev)\n \tdev->mode_config.preferred_depth = 24;\n \tdev->mode_config.async_page_flip = true;\n \tdev->mode_config.allow_fb_modifiers = true;\n+\tdev->mode_config.normalize_zpos = true;\n \n \tret = vc4_ctm_obj_init(vc4);\n \tif (ret)\n--- /dev/null\n+++ b/drivers/gpu/drm/vc4/vc_image_types.h\n@@ -0,0 +1,175 @@\n+\n+/*\n+ * Copyright (c) 2012, Broadcom Europe Ltd\n+ *\n+ * Values taken from vc_image_types.h released by Broadcom at\n+ * https://github.com/raspberrypi/userland/blob/master/interface/vctypes/vc_image_types.h\n+ * and vc_image_structs.h at\n+ * https://github.com/raspberrypi/userland/blob/master/interface/vctypes/vc_image_structs.h\n+ *\n+ * This program is free software; you can redistribute it and/or modify\n+ * it under the terms of the GNU General Public License version 2 as\n+ * published by the Free Software Foundation.\n+ */\n+\n+enum {\n+\tVC_IMAGE_MIN = 0, //bounds for error checking\n+\n+\tVC_IMAGE_RGB565 = 1,\n+\tVC_IMAGE_1BPP,\n+\tVC_IMAGE_YUV420,\n+\tVC_IMAGE_48BPP,\n+\tVC_IMAGE_RGB888,\n+\tVC_IMAGE_8BPP,\n+\t/* 4bpp palettised image */\n+\tVC_IMAGE_4BPP,\n+\t/* A separated format of 16 colour/light shorts followed by 16 z\n+\t * values\n+\t */\n+\tVC_IMAGE_3D32,\n+\t/* 16 colours followed by 16 z values */\n+\tVC_IMAGE_3D32B,\n+\t/* A separated format of 16 material/colour/light shorts followed by\n+\t * 16 z values\n+\t */\n+\tVC_IMAGE_3D32MAT,\n+\t/* 32 bit format containing 18 bits of 6.6.6 RGB, 9 bits per short */\n+\tVC_IMAGE_RGB2X9,\n+\t/* 32-bit format holding 18 bits of 6.6.6 RGB */\n+\tVC_IMAGE_RGB666,\n+\t/* 4bpp palettised image with embedded palette */\n+\tVC_IMAGE_PAL4_OBSOLETE,\n+\t/* 8bpp palettised image with embedded palette */\n+\tVC_IMAGE_PAL8_OBSOLETE,\n+\t/* RGB888 with an alpha byte after each pixel */\n+\tVC_IMAGE_RGBA32,\n+\t/* a line of Y (32-byte padded), a line of U (16-byte padded), and a\n+\t * line of V (16-byte padded)\n+\t */\n+\tVC_IMAGE_YUV422,\n+\t/* RGB565 with a transparent patch */\n+\tVC_IMAGE_RGBA565,\n+\t/* Compressed (4444) version of RGBA32 */\n+\tVC_IMAGE_RGBA16,\n+\t/* VCIII codec format */\n+\tVC_IMAGE_YUV_UV,\n+\t/* VCIII T-format RGBA8888 */\n+\tVC_IMAGE_TF_RGBA32,\n+\t/* VCIII T-format RGBx8888 */\n+\tVC_IMAGE_TF_RGBX32,\n+\t/* VCIII T-format float */\n+\tVC_IMAGE_TF_FLOAT,\n+\t/* VCIII T-format RGBA4444 */\n+\tVC_IMAGE_TF_RGBA16,\n+\t/* VCIII T-format RGB5551 */\n+\tVC_IMAGE_TF_RGBA5551,\n+\t/* VCIII T-format RGB565 */\n+\tVC_IMAGE_TF_RGB565,\n+\t/* VCIII T-format 8-bit luma and 8-bit alpha */\n+\tVC_IMAGE_TF_YA88,\n+\t/* VCIII T-format 8 bit generic sample */\n+\tVC_IMAGE_TF_BYTE,\n+\t/* VCIII T-format 8-bit palette */\n+\tVC_IMAGE_TF_PAL8,\n+\t/* VCIII T-format 4-bit palette */\n+\tVC_IMAGE_TF_PAL4,\n+\t/* VCIII T-format Ericsson Texture Compressed */\n+\tVC_IMAGE_TF_ETC1,\n+\t/* RGB888 with R & B swapped */\n+\tVC_IMAGE_BGR888,\n+\t/* RGB888 with R & B swapped, but with no pitch, i.e. no padding after\n+\t * each row of pixels\n+\t */\n+\tVC_IMAGE_BGR888_NP,\n+\t/* Bayer image, extra defines which variant is being used */\n+\tVC_IMAGE_BAYER,\n+\t/* General wrapper for codec images e.g. JPEG from camera */\n+\tVC_IMAGE_CODEC,\n+\t/* VCIII codec format */\n+\tVC_IMAGE_YUV_UV32,\n+\t/* VCIII T-format 8-bit luma */\n+\tVC_IMAGE_TF_Y8,\n+\t/* VCIII T-format 8-bit alpha */\n+\tVC_IMAGE_TF_A8,\n+\t/* VCIII T-format 16-bit generic sample */\n+\tVC_IMAGE_TF_SHORT,\n+\t/* VCIII T-format 1bpp black/white */\n+\tVC_IMAGE_TF_1BPP,\n+\tVC_IMAGE_OPENGL,\n+\t/* VCIII-B0 HVS YUV 4:4:4 interleaved samples */\n+\tVC_IMAGE_YUV444I,\n+\t/* Y, U, & V planes separately (VC_IMAGE_YUV422 has them interleaved on\n+\t * a per line basis)\n+\t */\n+\tVC_IMAGE_YUV422PLANAR,\n+\t/* 32bpp with 8bit alpha at MS byte, with R, G, B (LS byte) */\n+\tVC_IMAGE_ARGB8888,\n+\t/* 32bpp with 8bit unused at MS byte, with R, G, B (LS byte) */\n+\tVC_IMAGE_XRGB8888,\n+\n+\t/* interleaved 8 bit samples of Y, U, Y, V (4 flavours) */\n+\tVC_IMAGE_YUV422YUYV,\n+\tVC_IMAGE_YUV422YVYU,\n+\tVC_IMAGE_YUV422UYVY,\n+\tVC_IMAGE_YUV422VYUY,\n+\n+\t/* 32bpp like RGBA32 but with unused alpha */\n+\tVC_IMAGE_RGBX32,\n+\t/* 32bpp, corresponding to RGBA with unused alpha */\n+\tVC_IMAGE_RGBX8888,\n+\t/* 32bpp, corresponding to BGRA with unused alpha */\n+\tVC_IMAGE_BGRX8888,\n+\n+\t/* Y as a plane, then UV byte interleaved in plane with same pitch,\n+\t * half height\n+\t */\n+\tVC_IMAGE_YUV420SP,\n+\n+\t/* Y, U, & V planes separately 4:4:4 */\n+\tVC_IMAGE_YUV444PLANAR,\n+\n+\t/* T-format 8-bit U - same as TF_Y8 buf from U plane */\n+\tVC_IMAGE_TF_U8,\n+\t/* T-format 8-bit U - same as TF_Y8 buf from V plane */\n+\tVC_IMAGE_TF_V8,\n+\n+\t/* YUV4:2:0 planar, 16bit values */\n+\tVC_IMAGE_YUV420_16,\n+\t/* YUV4:2:0 codec format, 16bit values */\n+\tVC_IMAGE_YUV_UV_16,\n+\t/* YUV4:2:0 with U,V in side-by-side format */\n+\tVC_IMAGE_YUV420_S,\n+\t/* 10-bit YUV 420 column image format */\n+\tVC_IMAGE_YUV10COL,\n+\t/* 32-bpp, 10-bit R/G/B, 2-bit Alpha */\n+\tVC_IMAGE_RGBA1010102,\n+\n+\tVC_IMAGE_MAX,     /* bounds for error checking */\n+\tVC_IMAGE_FORCE_ENUM_16BIT = 0xffff,\n+};\n+\n+enum {\n+\t/* Unknown or unset - defaults to BT601 interstitial */\n+\tVC_IMAGE_YUVINFO_UNSPECIFIED    = 0,\n+\n+\t/* colour-space conversions data [4 bits] */\n+\n+\t/* ITU-R BT.601-5 [SDTV] (compatible with VideoCore-II) */\n+\tVC_IMAGE_YUVINFO_CSC_ITUR_BT601      = 1,\n+\t/* ITU-R BT.709-3 [HDTV] */\n+\tVC_IMAGE_YUVINFO_CSC_ITUR_BT709      = 2,\n+\t/* JPEG JFIF */\n+\tVC_IMAGE_YUVINFO_CSC_JPEG_JFIF       = 3,\n+\t/* Title 47 Code of Federal Regulations (2003) 73.682 (a) (20) */\n+\tVC_IMAGE_YUVINFO_CSC_FCC             = 4,\n+\t/* Society of Motion Picture and Television Engineers 240M (1999) */\n+\tVC_IMAGE_YUVINFO_CSC_SMPTE_240M      = 5,\n+\t/* ITU-R BT.470-2 System M */\n+\tVC_IMAGE_YUVINFO_CSC_ITUR_BT470_2_M  = 6,\n+\t/* ITU-R BT.470-2 System B,G */\n+\tVC_IMAGE_YUVINFO_CSC_ITUR_BT470_2_BG = 7,\n+\t/* JPEG JFIF, but with 16..255 luma */\n+\tVC_IMAGE_YUVINFO_CSC_JPEG_JFIF_Y16_255 = 8,\n+\t/* Rec 2020 */\n+\tVC_IMAGE_YUVINFO_CSC_REC_2020        = 9,\n+};\n--- a/include/soc/bcm2835/raspberrypi-firmware.h\n+++ b/include/soc/bcm2835/raspberrypi-firmware.h\n@@ -75,6 +75,7 @@ enum rpi_firmware_property_tag {\n \tRPI_FIRMWARE_GET_DISPMANX_RESOURCE_MEM_HANDLE =       0x00030014,\n \tRPI_FIRMWARE_GET_EDID_BLOCK =                         0x00030020,\n \tRPI_FIRMWARE_GET_CUSTOMER_OTP =                       0x00030021,\n+\tRPI_FIRMWARE_GET_EDID_BLOCK_DISPLAY =                 0x00030023,\n \tRPI_FIRMWARE_GET_DOMAIN_STATE =                       0x00030030,\n \tRPI_FIRMWARE_GET_THROTTLED =                          0x00030046,\n \tRPI_FIRMWARE_GET_CLOCK_MEASURED =                     0x00030047,\n@@ -148,6 +149,11 @@ enum rpi_firmware_property_tag {\n \n \tRPI_FIRMWARE_VCHIQ_INIT =                             0x00048010,\n \n+\tRPI_FIRMWARE_SET_PLANE =                              0x00048015,\n+\tRPI_FIRMWARE_GET_DISPLAY_TIMING =                     0x00040017,\n+\tRPI_FIRMWARE_SET_TIMING =                             0x00048017,\n+\tRPI_FIRMWARE_GET_DISPLAY_CFG =                        0x00040018,\n+\tRPI_FIRMWARE_SET_DISPLAY_POWER =\t\t      0x00048019,\n \tRPI_FIRMWARE_GET_COMMAND_LINE =                       0x00050001,\n \tRPI_FIRMWARE_GET_DMA_CHANNELS =                       0x00060001,\n };\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0322-drm-vc4-Add-FKMS-as-an-acceptable-node-for-dma-range.patch",
    "content": "From 169f0a14f21a95194c5de355ce9a95d36aa97bef Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Tue, 19 May 2020 16:20:30 +0100\nSubject: [PATCH] drm/vc4: Add FKMS as an acceptable node for dma\n ranges.\n\nUnder FKMS, the firmware (via FKMS) also requires the VideoCore cache\naliases for image planes, as defined by the dma-ranges under /soc.\n\nAdd rpi-firmware-kms to the list of acceptable nodes to look for\nto copy dma config from.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n drivers/gpu/drm/vc4/vc4_drv.c | 1 +\n 1 file changed, 1 insertion(+)\n\n--- a/drivers/gpu/drm/vc4/vc4_drv.c\n+++ b/drivers/gpu/drm/vc4/vc4_drv.c\n@@ -248,6 +248,7 @@ static void vc4_match_add_drivers(struct\n \n const struct of_device_id vc4_dma_range_matches[] = {\n \t{ .compatible = \"brcm,bcm2835-hvs\" },\n+\t{ .compatible = \"raspberrypi,rpi-firmware-kms\" },\n \t{ .compatible = \"brcm,bcm2835-v3d\" },\n \t{ .compatible = \"brcm,cygnus-v3d\" },\n \t{ .compatible = \"brcm,vc4-v3d\" },\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0323-media-i2c-Add-driver-for-Sony-IMX477-sensor.patch",
    "content": "From 93582ca03e35b453e6da5c50a80339f5d00c3f05 Mon Sep 17 00:00:00 2001\nFrom: Naushir Patuck <naush@raspberrypi.com>\nDate: Fri, 8 May 2020 10:00:12 +0100\nSubject: [PATCH] media: i2c: Add driver for Sony IMX477 sensor\n\nAdds a driver for the 12MPix Sony IMX477 CSI2 sensor.\nWhilst the sensor supports 2 or 4 CSI2 data lanes, this driver\ncurrently only supports 2 lanes.\n\nThe following Bayer modes are currently available:\n\n4056x3040 12-bit @ 10fps\n2028x1520 12-bit (binned) @ 40fps\n2028x1050 12-bit (cropped/binned) @ 50fps\n1012x760 10-bit (scaled) @ 120 fps\n\nSigned-off-by: Naushir Patuck <naush@raspberrypi.com>\n---\n MAINTAINERS                |    8 +\n drivers/media/i2c/Kconfig  |   11 +\n drivers/media/i2c/Makefile |    1 +\n drivers/media/i2c/imx477.c | 2191 ++++++++++++++++++++++++++++++++++++\n 4 files changed, 2211 insertions(+)\n create mode 100644 drivers/media/i2c/imx477.c\n\n--- a/MAINTAINERS\n+++ b/MAINTAINERS\n@@ -16346,6 +16346,14 @@ S:\tMaintained\n T:\tgit git://linuxtv.org/media_tree.git\n F:\tdrivers/media/i2c/imx355.c\n \n+SONY IMX477 SENSOR DRIVER\n+M:\tRaspberry Pi Kernel Maintenance <kernel-list@raspberrypi.com>\n+L:\tlinux-media@vger.kernel.org\n+S:\tMaintained\n+T:\tgit git://linuxtv.org/media_tree.git\n+F:\tDocumentation/devicetree/bindings/media/i2c/imx477.yaml\n+F:\tdrivers/media/i2c/imx477.c\n+\n SONY MEMORYSTICK SUBSYSTEM\n M:\tMaxim Levitsky <maximlevitsky@gmail.com>\n M:\tAlex Dubov <oakad@yahoo.com>\n--- a/drivers/media/i2c/Kconfig\n+++ b/drivers/media/i2c/Kconfig\n@@ -801,6 +801,17 @@ config VIDEO_IMX290\n \t  To compile this driver as a module, choose M here: the\n \t  module will be called imx290.\n \n+config VIDEO_IMX477\n+\ttristate \"Sony IMX477 sensor support\"\n+\tdepends on I2C && VIDEO_V4L2 && VIDEO_V4L2_SUBDEV_API\n+\tdepends on MEDIA_CAMERA_SUPPORT\n+\thelp\n+\t  This is a Video4Linux2 sensor driver for the Sony\n+\t  IMX477 camera.\n+\n+\t  To compile this driver as a module, choose M here: the\n+\t  module will be called imx477.\n+\n config VIDEO_IMX319\n \ttristate \"Sony IMX319 sensor support\"\n \tdepends on I2C && VIDEO_V4L2\n--- a/drivers/media/i2c/Makefile\n+++ b/drivers/media/i2c/Makefile\n@@ -119,6 +119,7 @@ obj-$(CONFIG_VIDEO_IMX219)\t+= imx219.o\n obj-$(CONFIG_VIDEO_IMX258)\t+= imx258.o\n obj-$(CONFIG_VIDEO_IMX274)\t+= imx274.o\n obj-$(CONFIG_VIDEO_IMX290)\t+= imx290.o\n+obj-$(CONFIG_VIDEO_IMX477)\t+= imx477.o\n obj-$(CONFIG_VIDEO_IMX319)\t+= imx319.o\n obj-$(CONFIG_VIDEO_IMX355)\t+= imx355.o\n obj-$(CONFIG_VIDEO_MAX9286)\t+= max9286.o\n--- /dev/null\n+++ b/drivers/media/i2c/imx477.c\n@@ -0,0 +1,2191 @@\n+// SPDX-License-Identifier: GPL-2.0\n+/*\n+ * A V4L2 driver for Sony IMX477 cameras.\n+ * Copyright (C) 2020, Raspberry Pi (Trading) Ltd\n+ *\n+ * Based on Sony imx219 camera driver\n+ * Copyright (C) 2019-2020 Raspberry Pi (Trading) Ltd\n+ */\n+#include <asm/unaligned.h>\n+#include <linux/clk.h>\n+#include <linux/delay.h>\n+#include <linux/gpio/consumer.h>\n+#include <linux/i2c.h>\n+#include <linux/module.h>\n+#include <linux/pm_runtime.h>\n+#include <linux/regulator/consumer.h>\n+#include <media/v4l2-ctrls.h>\n+#include <media/v4l2-device.h>\n+#include <media/v4l2-event.h>\n+#include <media/v4l2-fwnode.h>\n+#include <media/v4l2-mediabus.h>\n+\n+#define IMX477_REG_VALUE_08BIT\t\t1\n+#define IMX477_REG_VALUE_16BIT\t\t2\n+\n+/* Chip ID */\n+#define IMX477_REG_CHIP_ID\t\t0x0016\n+#define IMX477_CHIP_ID\t\t\t0x0477\n+\n+#define IMX477_REG_MODE_SELECT\t\t0x0100\n+#define IMX477_MODE_STANDBY\t\t0x00\n+#define IMX477_MODE_STREAMING\t\t0x01\n+\n+#define IMX477_REG_ORIENTATION\t\t0x101\n+\n+#define IMX477_XCLK_FREQ\t\t24000000\n+\n+#define IMX477_DEFAULT_LINK_FREQ\t450000000\n+\n+/* Pixel rate is fixed at 840MHz for all the modes */\n+#define IMX477_PIXEL_RATE\t\t840000000\n+\n+/* V_TIMING internal */\n+#define IMX477_REG_FRAME_LENGTH\t\t0x0340\n+#define IMX477_FRAME_LENGTH_MAX\t\t0xffdc\n+\n+/* Exposure control */\n+#define IMX477_REG_EXPOSURE\t\t0x0202\n+#define IMX477_EXPOSURE_OFFSET\t\t22\n+#define IMX477_EXPOSURE_MIN\t\t20\n+#define IMX477_EXPOSURE_STEP\t\t1\n+#define IMX477_EXPOSURE_DEFAULT\t\t0x640\n+#define IMX477_EXPOSURE_MAX\t\t(IMX477_FRAME_LENGTH_MAX - \\\n+\t\t\t\t\t IMX477_EXPOSURE_OFFSET)\n+\n+/* Analog gain control */\n+#define IMX477_REG_ANALOG_GAIN\t\t0x0204\n+#define IMX477_ANA_GAIN_MIN\t\t0\n+#define IMX477_ANA_GAIN_MAX\t\t978\n+#define IMX477_ANA_GAIN_STEP\t\t1\n+#define IMX477_ANA_GAIN_DEFAULT\t\t0x0\n+\n+/* Digital gain control */\n+#define IMX477_REG_DIGITAL_GAIN\t\t0x020e\n+#define IMX477_DGTL_GAIN_MIN\t\t0x0100\n+#define IMX477_DGTL_GAIN_MAX\t\t0xffff\n+#define IMX477_DGTL_GAIN_DEFAULT\t0x0100\n+#define IMX477_DGTL_GAIN_STEP\t\t1\n+\n+/* Test Pattern Control */\n+#define IMX477_REG_TEST_PATTERN\t\t0x0600\n+#define IMX477_TEST_PATTERN_DISABLE\t0\n+#define IMX477_TEST_PATTERN_SOLID_COLOR\t1\n+#define IMX477_TEST_PATTERN_COLOR_BARS\t2\n+#define IMX477_TEST_PATTERN_GREY_COLOR\t3\n+#define IMX477_TEST_PATTERN_PN9\t\t4\n+\n+/* Test pattern colour components */\n+#define IMX477_REG_TEST_PATTERN_R\t0x0602\n+#define IMX477_REG_TEST_PATTERN_GR\t0x0604\n+#define IMX477_REG_TEST_PATTERN_B\t0x0606\n+#define IMX477_REG_TEST_PATTERN_GB\t0x0608\n+#define IMX477_TEST_PATTERN_COLOUR_MIN\t0\n+#define IMX477_TEST_PATTERN_COLOUR_MAX\t0x0fff\n+#define IMX477_TEST_PATTERN_COLOUR_STEP\t1\n+#define IMX477_TEST_PATTERN_R_DEFAULT\tIMX477_TEST_PATTERN_COLOUR_MAX\n+#define IMX477_TEST_PATTERN_GR_DEFAULT\t0\n+#define IMX477_TEST_PATTERN_B_DEFAULT\t0\n+#define IMX477_TEST_PATTERN_GB_DEFAULT\t0\n+\n+/* Embedded metadata stream structure */\n+#define IMX477_EMBEDDED_LINE_WIDTH 16384\n+#define IMX477_NUM_EMBEDDED_LINES 1\n+\n+enum pad_types {\n+\tIMAGE_PAD,\n+\tMETADATA_PAD,\n+\tNUM_PADS\n+};\n+\n+/* IMX477 native and active pixel array size. */\n+#define IMX477_NATIVE_WIDTH\t\t4072U\n+#define IMX477_NATIVE_HEIGHT\t\t3176U\n+#define IMX477_PIXEL_ARRAY_LEFT\t\t8U\n+#define IMX477_PIXEL_ARRAY_TOP\t\t16U\n+#define IMX477_PIXEL_ARRAY_WIDTH\t4056U\n+#define IMX477_PIXEL_ARRAY_HEIGHT\t3040U\n+\n+struct imx477_reg {\n+\tu16 address;\n+\tu8 val;\n+};\n+\n+struct imx477_reg_list {\n+\tunsigned int num_of_regs;\n+\tconst struct imx477_reg *regs;\n+};\n+\n+/* Mode : resolution and related config&values */\n+struct imx477_mode {\n+\t/* Frame width */\n+\tunsigned int width;\n+\n+\t/* Frame height */\n+\tunsigned int height;\n+\n+\t/* H-timing in pixels */\n+\tunsigned int line_length_pix;\n+\n+\t/* Analog crop rectangle. */\n+\tstruct v4l2_rect crop;\n+\n+\t/* Highest possible framerate. */\n+\tstruct v4l2_fract timeperframe_min;\n+\n+\t/* Default framerate. */\n+\tstruct v4l2_fract timeperframe_default;\n+\n+\t/* Default register values */\n+\tstruct imx477_reg_list reg_list;\n+};\n+\n+static const struct imx477_reg mode_common_regs[] = {\n+\t{0x0136, 0x18},\n+\t{0x0137, 0x00},\n+\t{0xe000, 0x00},\n+\t{0xe07a, 0x01},\n+\t{0x0808, 0x02},\n+\t{0x4ae9, 0x18},\n+\t{0x4aea, 0x08},\n+\t{0xf61c, 0x04},\n+\t{0xf61e, 0x04},\n+\t{0x4ae9, 0x21},\n+\t{0x4aea, 0x80},\n+\t{0x38a8, 0x1f},\n+\t{0x38a9, 0xff},\n+\t{0x38aa, 0x1f},\n+\t{0x38ab, 0xff},\n+\t{0x55d4, 0x00},\n+\t{0x55d5, 0x00},\n+\t{0x55d6, 0x07},\n+\t{0x55d7, 0xff},\n+\t{0x55e8, 0x07},\n+\t{0x55e9, 0xff},\n+\t{0x55ea, 0x00},\n+\t{0x55eb, 0x00},\n+\t{0x574c, 0x07},\n+\t{0x574d, 0xff},\n+\t{0x574e, 0x00},\n+\t{0x574f, 0x00},\n+\t{0x5754, 0x00},\n+\t{0x5755, 0x00},\n+\t{0x5756, 0x07},\n+\t{0x5757, 0xff},\n+\t{0x5973, 0x04},\n+\t{0x5974, 0x01},\n+\t{0x5d13, 0xc3},\n+\t{0x5d14, 0x58},\n+\t{0x5d15, 0xa3},\n+\t{0x5d16, 0x1d},\n+\t{0x5d17, 0x65},\n+\t{0x5d18, 0x8c},\n+\t{0x5d1a, 0x06},\n+\t{0x5d1b, 0xa9},\n+\t{0x5d1c, 0x45},\n+\t{0x5d1d, 0x3a},\n+\t{0x5d1e, 0xab},\n+\t{0x5d1f, 0x15},\n+\t{0x5d21, 0x0e},\n+\t{0x5d22, 0x52},\n+\t{0x5d23, 0xaa},\n+\t{0x5d24, 0x7d},\n+\t{0x5d25, 0x57},\n+\t{0x5d26, 0xa8},\n+\t{0x5d37, 0x5a},\n+\t{0x5d38, 0x5a},\n+\t{0x5d77, 0x7f},\n+\t{0x7b75, 0x0e},\n+\t{0x7b76, 0x0b},\n+\t{0x7b77, 0x08},\n+\t{0x7b78, 0x0a},\n+\t{0x7b79, 0x47},\n+\t{0x7b7c, 0x00},\n+\t{0x7b7d, 0x00},\n+\t{0x8d1f, 0x00},\n+\t{0x8d27, 0x00},\n+\t{0x9004, 0x03},\n+\t{0x9200, 0x50},\n+\t{0x9201, 0x6c},\n+\t{0x9202, 0x71},\n+\t{0x9203, 0x00},\n+\t{0x9204, 0x71},\n+\t{0x9205, 0x01},\n+\t{0x9371, 0x6a},\n+\t{0x9373, 0x6a},\n+\t{0x9375, 0x64},\n+\t{0x991a, 0x00},\n+\t{0x996b, 0x8c},\n+\t{0x996c, 0x64},\n+\t{0x996d, 0x50},\n+\t{0x9a4c, 0x0d},\n+\t{0x9a4d, 0x0d},\n+\t{0xa001, 0x0a},\n+\t{0xa003, 0x0a},\n+\t{0xa005, 0x0a},\n+\t{0xa006, 0x01},\n+\t{0xa007, 0xc0},\n+\t{0xa009, 0xc0},\n+\t{0x3d8a, 0x01},\n+\t{0x4421, 0x04},\n+\t{0x7b3b, 0x01},\n+\t{0x7b4c, 0x00},\n+\t{0x9905, 0x00},\n+\t{0x9907, 0x00},\n+\t{0x9909, 0x00},\n+\t{0x990b, 0x00},\n+\t{0x9944, 0x3c},\n+\t{0x9947, 0x3c},\n+\t{0x994a, 0x8c},\n+\t{0x994b, 0x50},\n+\t{0x994c, 0x1b},\n+\t{0x994d, 0x8c},\n+\t{0x994e, 0x50},\n+\t{0x994f, 0x1b},\n+\t{0x9950, 0x8c},\n+\t{0x9951, 0x1b},\n+\t{0x9952, 0x0a},\n+\t{0x9953, 0x8c},\n+\t{0x9954, 0x1b},\n+\t{0x9955, 0x0a},\n+\t{0x9a13, 0x04},\n+\t{0x9a14, 0x04},\n+\t{0x9a19, 0x00},\n+\t{0x9a1c, 0x04},\n+\t{0x9a1d, 0x04},\n+\t{0x9a26, 0x05},\n+\t{0x9a27, 0x05},\n+\t{0x9a2c, 0x01},\n+\t{0x9a2d, 0x03},\n+\t{0x9a2f, 0x05},\n+\t{0x9a30, 0x05},\n+\t{0x9a41, 0x00},\n+\t{0x9a46, 0x00},\n+\t{0x9a47, 0x00},\n+\t{0x9c17, 0x35},\n+\t{0x9c1d, 0x31},\n+\t{0x9c29, 0x50},\n+\t{0x9c3b, 0x2f},\n+\t{0x9c41, 0x6b},\n+\t{0x9c47, 0x2d},\n+\t{0x9c4d, 0x40},\n+\t{0x9c6b, 0x00},\n+\t{0x9c71, 0xc8},\n+\t{0x9c73, 0x32},\n+\t{0x9c75, 0x04},\n+\t{0x9c7d, 0x2d},\n+\t{0x9c83, 0x40},\n+\t{0x9c94, 0x3f},\n+\t{0x9c95, 0x3f},\n+\t{0x9c96, 0x3f},\n+\t{0x9c97, 0x00},\n+\t{0x9c98, 0x00},\n+\t{0x9c99, 0x00},\n+\t{0x9c9a, 0x3f},\n+\t{0x9c9b, 0x3f},\n+\t{0x9c9c, 0x3f},\n+\t{0x9ca0, 0x0f},\n+\t{0x9ca1, 0x0f},\n+\t{0x9ca2, 0x0f},\n+\t{0x9ca3, 0x00},\n+\t{0x9ca4, 0x00},\n+\t{0x9ca5, 0x00},\n+\t{0x9ca6, 0x1e},\n+\t{0x9ca7, 0x1e},\n+\t{0x9ca8, 0x1e},\n+\t{0x9ca9, 0x00},\n+\t{0x9caa, 0x00},\n+\t{0x9cab, 0x00},\n+\t{0x9cac, 0x09},\n+\t{0x9cad, 0x09},\n+\t{0x9cae, 0x09},\n+\t{0x9cbd, 0x50},\n+\t{0x9cbf, 0x50},\n+\t{0x9cc1, 0x50},\n+\t{0x9cc3, 0x40},\n+\t{0x9cc5, 0x40},\n+\t{0x9cc7, 0x40},\n+\t{0x9cc9, 0x0a},\n+\t{0x9ccb, 0x0a},\n+\t{0x9ccd, 0x0a},\n+\t{0x9d17, 0x35},\n+\t{0x9d1d, 0x31},\n+\t{0x9d29, 0x50},\n+\t{0x9d3b, 0x2f},\n+\t{0x9d41, 0x6b},\n+\t{0x9d47, 0x42},\n+\t{0x9d4d, 0x5a},\n+\t{0x9d6b, 0x00},\n+\t{0x9d71, 0xc8},\n+\t{0x9d73, 0x32},\n+\t{0x9d75, 0x04},\n+\t{0x9d7d, 0x42},\n+\t{0x9d83, 0x5a},\n+\t{0x9d94, 0x3f},\n+\t{0x9d95, 0x3f},\n+\t{0x9d96, 0x3f},\n+\t{0x9d97, 0x00},\n+\t{0x9d98, 0x00},\n+\t{0x9d99, 0x00},\n+\t{0x9d9a, 0x3f},\n+\t{0x9d9b, 0x3f},\n+\t{0x9d9c, 0x3f},\n+\t{0x9d9d, 0x1f},\n+\t{0x9d9e, 0x1f},\n+\t{0x9d9f, 0x1f},\n+\t{0x9da0, 0x0f},\n+\t{0x9da1, 0x0f},\n+\t{0x9da2, 0x0f},\n+\t{0x9da3, 0x00},\n+\t{0x9da4, 0x00},\n+\t{0x9da5, 0x00},\n+\t{0x9da6, 0x1e},\n+\t{0x9da7, 0x1e},\n+\t{0x9da8, 0x1e},\n+\t{0x9da9, 0x00},\n+\t{0x9daa, 0x00},\n+\t{0x9dab, 0x00},\n+\t{0x9dac, 0x09},\n+\t{0x9dad, 0x09},\n+\t{0x9dae, 0x09},\n+\t{0x9dc9, 0x0a},\n+\t{0x9dcb, 0x0a},\n+\t{0x9dcd, 0x0a},\n+\t{0x9e17, 0x35},\n+\t{0x9e1d, 0x31},\n+\t{0x9e29, 0x50},\n+\t{0x9e3b, 0x2f},\n+\t{0x9e41, 0x6b},\n+\t{0x9e47, 0x2d},\n+\t{0x9e4d, 0x40},\n+\t{0x9e6b, 0x00},\n+\t{0x9e71, 0xc8},\n+\t{0x9e73, 0x32},\n+\t{0x9e75, 0x04},\n+\t{0x9e94, 0x0f},\n+\t{0x9e95, 0x0f},\n+\t{0x9e96, 0x0f},\n+\t{0x9e97, 0x00},\n+\t{0x9e98, 0x00},\n+\t{0x9e99, 0x00},\n+\t{0x9ea0, 0x0f},\n+\t{0x9ea1, 0x0f},\n+\t{0x9ea2, 0x0f},\n+\t{0x9ea3, 0x00},\n+\t{0x9ea4, 0x00},\n+\t{0x9ea5, 0x00},\n+\t{0x9ea6, 0x3f},\n+\t{0x9ea7, 0x3f},\n+\t{0x9ea8, 0x3f},\n+\t{0x9ea9, 0x00},\n+\t{0x9eaa, 0x00},\n+\t{0x9eab, 0x00},\n+\t{0x9eac, 0x09},\n+\t{0x9ead, 0x09},\n+\t{0x9eae, 0x09},\n+\t{0x9ec9, 0x0a},\n+\t{0x9ecb, 0x0a},\n+\t{0x9ecd, 0x0a},\n+\t{0x9f17, 0x35},\n+\t{0x9f1d, 0x31},\n+\t{0x9f29, 0x50},\n+\t{0x9f3b, 0x2f},\n+\t{0x9f41, 0x6b},\n+\t{0x9f47, 0x42},\n+\t{0x9f4d, 0x5a},\n+\t{0x9f6b, 0x00},\n+\t{0x9f71, 0xc8},\n+\t{0x9f73, 0x32},\n+\t{0x9f75, 0x04},\n+\t{0x9f94, 0x0f},\n+\t{0x9f95, 0x0f},\n+\t{0x9f96, 0x0f},\n+\t{0x9f97, 0x00},\n+\t{0x9f98, 0x00},\n+\t{0x9f99, 0x00},\n+\t{0x9f9a, 0x2f},\n+\t{0x9f9b, 0x2f},\n+\t{0x9f9c, 0x2f},\n+\t{0x9f9d, 0x00},\n+\t{0x9f9e, 0x00},\n+\t{0x9f9f, 0x00},\n+\t{0x9fa0, 0x0f},\n+\t{0x9fa1, 0x0f},\n+\t{0x9fa2, 0x0f},\n+\t{0x9fa3, 0x00},\n+\t{0x9fa4, 0x00},\n+\t{0x9fa5, 0x00},\n+\t{0x9fa6, 0x1e},\n+\t{0x9fa7, 0x1e},\n+\t{0x9fa8, 0x1e},\n+\t{0x9fa9, 0x00},\n+\t{0x9faa, 0x00},\n+\t{0x9fab, 0x00},\n+\t{0x9fac, 0x09},\n+\t{0x9fad, 0x09},\n+\t{0x9fae, 0x09},\n+\t{0x9fc9, 0x0a},\n+\t{0x9fcb, 0x0a},\n+\t{0x9fcd, 0x0a},\n+\t{0xa14b, 0xff},\n+\t{0xa151, 0x0c},\n+\t{0xa153, 0x50},\n+\t{0xa155, 0x02},\n+\t{0xa157, 0x00},\n+\t{0xa1ad, 0xff},\n+\t{0xa1b3, 0x0c},\n+\t{0xa1b5, 0x50},\n+\t{0xa1b9, 0x00},\n+\t{0xa24b, 0xff},\n+\t{0xa257, 0x00},\n+\t{0xa2ad, 0xff},\n+\t{0xa2b9, 0x00},\n+\t{0xb21f, 0x04},\n+\t{0xb35c, 0x00},\n+\t{0xb35e, 0x08},\n+\t{0x0112, 0x0c},\n+\t{0x0113, 0x0c},\n+\t{0x0114, 0x01},\n+\t{0x0350, 0x00},\n+\t{0xbcf1, 0x02},\n+\t{0x3ff9, 0x01},\n+};\n+\n+/* 12 mpix 10fps */\n+static const struct imx477_reg mode_4056x3040_regs[] = {\n+\t{0x0342, 0x5d},\n+\t{0x0343, 0xc0},\n+\t{0x0344, 0x00},\n+\t{0x0345, 0x00},\n+\t{0x0346, 0x00},\n+\t{0x0347, 0x00},\n+\t{0x0348, 0x0f},\n+\t{0x0349, 0xd7},\n+\t{0x034a, 0x0b},\n+\t{0x034b, 0xdf},\n+\t{0x00e3, 0x00},\n+\t{0x00e4, 0x00},\n+\t{0x00fc, 0x0a},\n+\t{0x00fd, 0x0a},\n+\t{0x00fe, 0x0a},\n+\t{0x00ff, 0x0a},\n+\t{0x0220, 0x00},\n+\t{0x0221, 0x11},\n+\t{0x0381, 0x01},\n+\t{0x0383, 0x01},\n+\t{0x0385, 0x01},\n+\t{0x0387, 0x01},\n+\t{0x0900, 0x00},\n+\t{0x0901, 0x11},\n+\t{0x0902, 0x02},\n+\t{0x3140, 0x02},\n+\t{0x3c00, 0x00},\n+\t{0x3c01, 0x03},\n+\t{0x3c02, 0xa2},\n+\t{0x3f0d, 0x01},\n+\t{0x5748, 0x07},\n+\t{0x5749, 0xff},\n+\t{0x574a, 0x00},\n+\t{0x574b, 0x00},\n+\t{0x7b75, 0x0a},\n+\t{0x7b76, 0x0c},\n+\t{0x7b77, 0x07},\n+\t{0x7b78, 0x06},\n+\t{0x7b79, 0x3c},\n+\t{0x7b53, 0x01},\n+\t{0x9369, 0x5a},\n+\t{0x936b, 0x55},\n+\t{0x936d, 0x28},\n+\t{0x9304, 0x00},\n+\t{0x9305, 0x00},\n+\t{0x9e9a, 0x2f},\n+\t{0x9e9b, 0x2f},\n+\t{0x9e9c, 0x2f},\n+\t{0x9e9d, 0x00},\n+\t{0x9e9e, 0x00},\n+\t{0x9e9f, 0x00},\n+\t{0xa2a9, 0x60},\n+\t{0xa2b7, 0x00},\n+\t{0x0401, 0x00},\n+\t{0x0404, 0x00},\n+\t{0x0405, 0x10},\n+\t{0x0408, 0x00},\n+\t{0x0409, 0x00},\n+\t{0x040a, 0x00},\n+\t{0x040b, 0x00},\n+\t{0x040c, 0x0f},\n+\t{0x040d, 0xd8},\n+\t{0x040e, 0x0b},\n+\t{0x040f, 0xe0},\n+\t{0x034c, 0x0f},\n+\t{0x034d, 0xd8},\n+\t{0x034e, 0x0b},\n+\t{0x034f, 0xe0},\n+\t{0x0301, 0x05},\n+\t{0x0303, 0x02},\n+\t{0x0305, 0x04},\n+\t{0x0306, 0x01},\n+\t{0x0307, 0x5e},\n+\t{0x0309, 0x0c},\n+\t{0x030b, 0x02},\n+\t{0x030d, 0x02},\n+\t{0x030e, 0x00},\n+\t{0x030f, 0x96},\n+\t{0x0310, 0x01},\n+\t{0x0820, 0x07},\n+\t{0x0821, 0x08},\n+\t{0x0822, 0x00},\n+\t{0x0823, 0x00},\n+\t{0x080a, 0x00},\n+\t{0x080b, 0x7f},\n+\t{0x080c, 0x00},\n+\t{0x080d, 0x4f},\n+\t{0x080e, 0x00},\n+\t{0x080f, 0x77},\n+\t{0x0810, 0x00},\n+\t{0x0811, 0x5f},\n+\t{0x0812, 0x00},\n+\t{0x0813, 0x57},\n+\t{0x0814, 0x00},\n+\t{0x0815, 0x4f},\n+\t{0x0816, 0x01},\n+\t{0x0817, 0x27},\n+\t{0x0818, 0x00},\n+\t{0x0819, 0x3f},\n+\t{0xe04c, 0x00},\n+\t{0xe04d, 0x7f},\n+\t{0xe04e, 0x00},\n+\t{0xe04f, 0x1f},\n+\t{0x3e20, 0x01},\n+\t{0x3e37, 0x00},\n+\t{0x3f50, 0x00},\n+\t{0x3f56, 0x02},\n+\t{0x3f57, 0xae},\n+};\n+\n+/* 2x2 binned. 40fps */\n+static const struct imx477_reg mode_2028x1520_regs[] = {\n+\t{0x0342, 0x31},\n+\t{0x0343, 0xc4},\n+\t{0x0344, 0x00},\n+\t{0x0345, 0x00},\n+\t{0x0346, 0x00},\n+\t{0x0347, 0x00},\n+\t{0x0348, 0x0f},\n+\t{0x0349, 0xd7},\n+\t{0x034a, 0x0b},\n+\t{0x034b, 0xdf},\n+\t{0x0220, 0x00},\n+\t{0x0221, 0x11},\n+\t{0x0381, 0x01},\n+\t{0x0383, 0x01},\n+\t{0x0385, 0x01},\n+\t{0x0387, 0x01},\n+\t{0x0900, 0x01},\n+\t{0x0901, 0x12},\n+\t{0x0902, 0x02},\n+\t{0x3140, 0x02},\n+\t{0x3c00, 0x00},\n+\t{0x3c01, 0x03},\n+\t{0x3c02, 0xa2},\n+\t{0x3f0d, 0x01},\n+\t{0x5748, 0x07},\n+\t{0x5749, 0xff},\n+\t{0x574a, 0x00},\n+\t{0x574b, 0x00},\n+\t{0x7b53, 0x01},\n+\t{0x9369, 0x73},\n+\t{0x936b, 0x64},\n+\t{0x936d, 0x5f},\n+\t{0x9304, 0x00},\n+\t{0x9305, 0x00},\n+\t{0x9e9a, 0x2f},\n+\t{0x9e9b, 0x2f},\n+\t{0x9e9c, 0x2f},\n+\t{0x9e9d, 0x00},\n+\t{0x9e9e, 0x00},\n+\t{0x9e9f, 0x00},\n+\t{0xa2a9, 0x60},\n+\t{0xa2b7, 0x00},\n+\t{0x0401, 0x01},\n+\t{0x0404, 0x00},\n+\t{0x0405, 0x20},\n+\t{0x0408, 0x00},\n+\t{0x0409, 0x00},\n+\t{0x040a, 0x00},\n+\t{0x040b, 0x00},\n+\t{0x040c, 0x0f},\n+\t{0x040d, 0xd8},\n+\t{0x040e, 0x0b},\n+\t{0x040f, 0xe0},\n+\t{0x034c, 0x07},\n+\t{0x034d, 0xec},\n+\t{0x034e, 0x05},\n+\t{0x034f, 0xf0},\n+\t{0x0301, 0x05},\n+\t{0x0303, 0x02},\n+\t{0x0305, 0x04},\n+\t{0x0306, 0x01},\n+\t{0x0307, 0x5e},\n+\t{0x0309, 0x0c},\n+\t{0x030b, 0x02},\n+\t{0x030d, 0x02},\n+\t{0x030e, 0x00},\n+\t{0x030f, 0x96},\n+\t{0x0310, 0x01},\n+\t{0x0820, 0x07},\n+\t{0x0821, 0x08},\n+\t{0x0822, 0x00},\n+\t{0x0823, 0x00},\n+\t{0x080a, 0x00},\n+\t{0x080b, 0x7f},\n+\t{0x080c, 0x00},\n+\t{0x080d, 0x4f},\n+\t{0x080e, 0x00},\n+\t{0x080f, 0x77},\n+\t{0x0810, 0x00},\n+\t{0x0811, 0x5f},\n+\t{0x0812, 0x00},\n+\t{0x0813, 0x57},\n+\t{0x0814, 0x00},\n+\t{0x0815, 0x4f},\n+\t{0x0816, 0x01},\n+\t{0x0817, 0x27},\n+\t{0x0818, 0x00},\n+\t{0x0819, 0x3f},\n+\t{0xe04c, 0x00},\n+\t{0xe04d, 0x7f},\n+\t{0xe04e, 0x00},\n+\t{0xe04f, 0x1f},\n+\t{0x3e20, 0x01},\n+\t{0x3e37, 0x00},\n+\t{0x3f50, 0x00},\n+\t{0x3f56, 0x01},\n+\t{0x3f57, 0x6c},\n+};\n+\n+/* 1080p cropped mode */\n+static const struct imx477_reg mode_2028x1080_regs[] = {\n+\t{0x0342, 0x31},\n+\t{0x0343, 0xc4},\n+\t{0x0344, 0x00},\n+\t{0x0345, 0x00},\n+\t{0x0346, 0x01},\n+\t{0x0347, 0xb8},\n+\t{0x0348, 0x0f},\n+\t{0x0349, 0xd7},\n+\t{0x034a, 0x0a},\n+\t{0x034b, 0x27},\n+\t{0x0220, 0x00},\n+\t{0x0221, 0x11},\n+\t{0x0381, 0x01},\n+\t{0x0383, 0x01},\n+\t{0x0385, 0x01},\n+\t{0x0387, 0x01},\n+\t{0x0900, 0x01},\n+\t{0x0901, 0x12},\n+\t{0x0902, 0x02},\n+\t{0x3140, 0x02},\n+\t{0x3c00, 0x00},\n+\t{0x3c01, 0x03},\n+\t{0x3c02, 0xa2},\n+\t{0x3f0d, 0x01},\n+\t{0x5748, 0x07},\n+\t{0x5749, 0xff},\n+\t{0x574a, 0x00},\n+\t{0x574b, 0x00},\n+\t{0x7b53, 0x01},\n+\t{0x9369, 0x73},\n+\t{0x936b, 0x64},\n+\t{0x936d, 0x5f},\n+\t{0x9304, 0x00},\n+\t{0x9305, 0x00},\n+\t{0x9e9a, 0x2f},\n+\t{0x9e9b, 0x2f},\n+\t{0x9e9c, 0x2f},\n+\t{0x9e9d, 0x00},\n+\t{0x9e9e, 0x00},\n+\t{0x9e9f, 0x00},\n+\t{0xa2a9, 0x60},\n+\t{0xa2b7, 0x00},\n+\t{0x0401, 0x01},\n+\t{0x0404, 0x00},\n+\t{0x0405, 0x20},\n+\t{0x0408, 0x00},\n+\t{0x0409, 0x00},\n+\t{0x040a, 0x00},\n+\t{0x040b, 0x00},\n+\t{0x040c, 0x0f},\n+\t{0x040d, 0xd8},\n+\t{0x040e, 0x04},\n+\t{0x040f, 0x38},\n+\t{0x034c, 0x07},\n+\t{0x034d, 0xec},\n+\t{0x034e, 0x04},\n+\t{0x034f, 0x38},\n+\t{0x0301, 0x05},\n+\t{0x0303, 0x02},\n+\t{0x0305, 0x04},\n+\t{0x0306, 0x01},\n+\t{0x0307, 0x5e},\n+\t{0x0309, 0x0c},\n+\t{0x030b, 0x02},\n+\t{0x030d, 0x02},\n+\t{0x030e, 0x00},\n+\t{0x030f, 0x96},\n+\t{0x0310, 0x01},\n+\t{0x0820, 0x07},\n+\t{0x0821, 0x08},\n+\t{0x0822, 0x00},\n+\t{0x0823, 0x00},\n+\t{0x080a, 0x00},\n+\t{0x080b, 0x7f},\n+\t{0x080c, 0x00},\n+\t{0x080d, 0x4f},\n+\t{0x080e, 0x00},\n+\t{0x080f, 0x77},\n+\t{0x0810, 0x00},\n+\t{0x0811, 0x5f},\n+\t{0x0812, 0x00},\n+\t{0x0813, 0x57},\n+\t{0x0814, 0x00},\n+\t{0x0815, 0x4f},\n+\t{0x0816, 0x01},\n+\t{0x0817, 0x27},\n+\t{0x0818, 0x00},\n+\t{0x0819, 0x3f},\n+\t{0xe04c, 0x00},\n+\t{0xe04d, 0x7f},\n+\t{0xe04e, 0x00},\n+\t{0xe04f, 0x1f},\n+\t{0x3e20, 0x01},\n+\t{0x3e37, 0x00},\n+\t{0x3f50, 0x00},\n+\t{0x3f56, 0x01},\n+\t{0x3f57, 0x6c},\n+};\n+\n+/* 4x4 binned. 120fps */\n+static const struct imx477_reg mode_1012x760_regs[] = {\n+\t{0x420b, 0x01},\n+\t{0x990c, 0x00},\n+\t{0x990d, 0x08},\n+\t{0x9956, 0x8c},\n+\t{0x9957, 0x64},\n+\t{0x9958, 0x50},\n+\t{0x9a48, 0x06},\n+\t{0x9a49, 0x06},\n+\t{0x9a4a, 0x06},\n+\t{0x9a4b, 0x06},\n+\t{0x9a4c, 0x06},\n+\t{0x9a4d, 0x06},\n+\t{0x0112, 0x0a},\n+\t{0x0113, 0x0a},\n+\t{0x0114, 0x01},\n+\t{0x0342, 0x14},\n+\t{0x0343, 0x60},\n+\t{0x0344, 0x00},\n+\t{0x0345, 0x00},\n+\t{0x0346, 0x00},\n+\t{0x0347, 0x00},\n+\t{0x0348, 0x0f},\n+\t{0x0349, 0xd3},\n+\t{0x034a, 0x0b},\n+\t{0x034b, 0xdf},\n+\t{0x00e3, 0x00},\n+\t{0x00e4, 0x00},\n+\t{0x00fc, 0x0a},\n+\t{0x00fd, 0x0a},\n+\t{0x00fe, 0x0a},\n+\t{0x00ff, 0x0a},\n+\t{0x0220, 0x00},\n+\t{0x0221, 0x11},\n+\t{0x0381, 0x01},\n+\t{0x0383, 0x01},\n+\t{0x0385, 0x01},\n+\t{0x0387, 0x03},\n+\t{0x0900, 0x01},\n+\t{0x0901, 0x22},\n+\t{0x0902, 0x02},\n+\t{0x3140, 0x02},\n+\t{0x3c00, 0x00},\n+\t{0x3c01, 0x01},\n+\t{0x3c02, 0x9c},\n+\t{0x3f0d, 0x00},\n+\t{0x5748, 0x00},\n+\t{0x5749, 0x00},\n+\t{0x574a, 0x00},\n+\t{0x574b, 0xa4},\n+\t{0x7b75, 0x0e},\n+\t{0x7b76, 0x09},\n+\t{0x7b77, 0x08},\n+\t{0x7b78, 0x06},\n+\t{0x7b79, 0x34},\n+\t{0x7b53, 0x00},\n+\t{0x9369, 0x73},\n+\t{0x936b, 0x64},\n+\t{0x936d, 0x5f},\n+\t{0x9304, 0x03},\n+\t{0x9305, 0x80},\n+\t{0x9e9a, 0x3f},\n+\t{0x9e9b, 0x3f},\n+\t{0x9e9c, 0x3f},\n+\t{0x9e9d, 0x27},\n+\t{0x9e9e, 0x27},\n+\t{0x9e9f, 0x27},\n+\t{0xa2a9, 0x27},\n+\t{0xa2b7, 0x03},\n+\t{0x0401, 0x01},\n+\t{0x0404, 0x00},\n+\t{0x0405, 0x20},\n+\t{0x0408, 0x00},\n+\t{0x0409, 0x00},\n+\t{0x040a, 0x00},\n+\t{0x040b, 0x00},\n+\t{0x040c, 0x07},\n+\t{0x040d, 0xea},\n+\t{0x040e, 0x02},\n+\t{0x040f, 0xf8},\n+\t{0x034c, 0x03},\n+\t{0x034d, 0xf4},\n+\t{0x034e, 0x02},\n+\t{0x034f, 0xf8},\n+\t{0x0301, 0x05},\n+\t{0x0303, 0x02},\n+\t{0x0305, 0x02},\n+\t{0x0306, 0x00},\n+\t{0x0307, 0xaf},\n+\t{0x0309, 0x0a},\n+\t{0x030b, 0x02},\n+\t{0x030d, 0x02},\n+\t{0x030e, 0x00},\n+\t{0x030f, 0x96},\n+\t{0x0310, 0x01},\n+\t{0x0820, 0x07},\n+\t{0x0821, 0x08},\n+\t{0x0822, 0x00},\n+\t{0x0823, 0x00},\n+\t{0x080a, 0x00},\n+\t{0x080b, 0x6f},\n+\t{0x080c, 0x00},\n+\t{0x080d, 0x3f},\n+\t{0x080e, 0x00},\n+\t{0x080f, 0xff},\n+\t{0x0810, 0x00},\n+\t{0x0811, 0x4f},\n+\t{0x0812, 0x00},\n+\t{0x0813, 0x47},\n+\t{0x0814, 0x00},\n+\t{0x0815, 0x37},\n+\t{0x0816, 0x00},\n+\t{0x0817, 0xe7},\n+\t{0x0818, 0x00},\n+\t{0x0819, 0x2f},\n+\t{0xe04c, 0x00},\n+\t{0xe04d, 0x5f},\n+\t{0xe04e, 0x00},\n+\t{0xe04f, 0x1f},\n+\t{0x3e20, 0x01},\n+\t{0x3e37, 0x00},\n+\t{0x3f50, 0x00},\n+\t{0x3f56, 0x00},\n+\t{0x3f57, 0x96},\n+};\n+\n+/* Mode configs */\n+static const struct imx477_mode supported_modes_12bit[] = {\n+\t{\n+\t\t/* 12MPix 10fps mode */\n+\t\t.width = 4056,\n+\t\t.height = 3040,\n+\t\t.line_length_pix = 0x5dc0,\n+\t\t.crop = {\n+\t\t\t.left = 0,\n+\t\t\t.top = 0,\n+\t\t\t.width = 4056,\n+\t\t\t.height = 3040,\n+\t\t},\n+\t\t.timeperframe_min = {\n+\t\t\t.numerator = 100,\n+\t\t\t.denominator = 1000\n+\t\t},\n+\t\t.timeperframe_default = {\n+\t\t\t.numerator = 100,\n+\t\t\t.denominator = 1000\n+\t\t},\n+\t\t.reg_list = {\n+\t\t\t.num_of_regs = ARRAY_SIZE(mode_4056x3040_regs),\n+\t\t\t.regs = mode_4056x3040_regs,\n+\t\t},\n+\t},\n+\t{\n+\t\t/* 2x2 binned 40fps mode */\n+\t\t.width = 2028,\n+\t\t.height = 1520,\n+\t\t.line_length_pix = 0x31c4,\n+\t\t.crop = {\n+\t\t\t.left = 0,\n+\t\t\t.top = 0,\n+\t\t\t.width = 4056,\n+\t\t\t.height = 3040,\n+\t\t},\n+\t\t.timeperframe_min = {\n+\t\t\t.numerator = 100,\n+\t\t\t.denominator = 4000\n+\t\t},\n+\t\t.timeperframe_default = {\n+\t\t\t.numerator = 100,\n+\t\t\t.denominator = 3000\n+\t\t},\n+\t\t.reg_list = {\n+\t\t\t.num_of_regs = ARRAY_SIZE(mode_2028x1520_regs),\n+\t\t\t.regs = mode_2028x1520_regs,\n+\t\t},\n+\t},\n+\t{\n+\t\t/* 1080p 50fps cropped mode */\n+\t\t.width = 2028,\n+\t\t.height = 1080,\n+\t\t.line_length_pix = 0x31c4,\n+\t\t.crop = {\n+\t\t\t.left = 0,\n+\t\t\t.top = 440,\n+\t\t\t.width = 4056,\n+\t\t\t.height = 2600,\n+\t\t},\n+\t\t.timeperframe_min = {\n+\t\t\t.numerator = 100,\n+\t\t\t.denominator = 5000\n+\t\t},\n+\t\t.timeperframe_default = {\n+\t\t\t.numerator = 100,\n+\t\t\t.denominator = 3000\n+\t\t},\n+\t\t.reg_list = {\n+\t\t\t.num_of_regs = ARRAY_SIZE(mode_2028x1080_regs),\n+\t\t\t.regs = mode_2028x1080_regs,\n+\t\t},\n+\t}\n+};\n+\n+static const struct imx477_mode supported_modes_10bit[] = {\n+\t{\n+\t\t/* 720P 120fps. 4x4 binned */\n+\t\t.width = 1012,\n+\t\t.height = 760,\n+\t\t.line_length_pix = 0x1460,\n+\t\t.crop = {\n+\t\t\t/*\n+\t\t\t * FIXME: the analog crop rectangle is actually\n+\t\t\t * programmed with a horizontal displacement of 0\n+\t\t\t * pixels, not 4. It gets shrunk after going through\n+\t\t\t * the scaler. Move this information to the compose\n+\t\t\t * rectangle once the driver is expanded to represent\n+\t\t\t * its processing blocks with multiple subdevs.\n+\t\t\t */\n+\t\t\t.left = 4,\n+\t\t\t.top = 0,\n+\t\t\t.width = 4052,\n+\t\t\t.height = 3040,\n+\t\t},\n+\t\t.timeperframe_min = {\n+\t\t\t.numerator = 100,\n+\t\t\t.denominator = 12000\n+\t\t},\n+\t\t.timeperframe_default = {\n+\t\t\t.numerator = 100,\n+\t\t\t.denominator = 60000\n+\t\t},\n+\t\t.reg_list = {\n+\t\t\t.num_of_regs = ARRAY_SIZE(mode_1012x760_regs),\n+\t\t\t.regs = mode_1012x760_regs,\n+\t\t}\n+\t}\n+};\n+\n+/*\n+ * The supported formats.\n+ * This table MUST contain 4 entries per format, to cover the various flip\n+ * combinations in the order\n+ * - no flip\n+ * - h flip\n+ * - v flip\n+ * - h&v flips\n+ */\n+static const u32 codes[] = {\n+\t/* 12-bit modes. */\n+\tMEDIA_BUS_FMT_SRGGB12_1X12,\n+\tMEDIA_BUS_FMT_SGRBG12_1X12,\n+\tMEDIA_BUS_FMT_SGBRG12_1X12,\n+\tMEDIA_BUS_FMT_SBGGR12_1X12,\n+\t/* 10-bit modes. */\n+\tMEDIA_BUS_FMT_SRGGB10_1X10,\n+\tMEDIA_BUS_FMT_SGRBG10_1X10,\n+\tMEDIA_BUS_FMT_SGBRG10_1X10,\n+\tMEDIA_BUS_FMT_SBGGR10_1X10,\n+};\n+\n+static const char * const imx477_test_pattern_menu[] = {\n+\t\"Disabled\",\n+\t\"Color Bars\",\n+\t\"Solid Color\",\n+\t\"Grey Color Bars\",\n+\t\"PN9\"\n+};\n+\n+static const int imx477_test_pattern_val[] = {\n+\tIMX477_TEST_PATTERN_DISABLE,\n+\tIMX477_TEST_PATTERN_COLOR_BARS,\n+\tIMX477_TEST_PATTERN_SOLID_COLOR,\n+\tIMX477_TEST_PATTERN_GREY_COLOR,\n+\tIMX477_TEST_PATTERN_PN9,\n+};\n+\n+/* regulator supplies */\n+static const char * const imx477_supply_name[] = {\n+\t/* Supplies can be enabled in any order */\n+\t\"VANA\",  /* Analog (2.8V) supply */\n+\t\"VDIG\",  /* Digital Core (1.05V) supply */\n+\t\"VDDL\",  /* IF (1.8V) supply */\n+};\n+\n+#define IMX477_NUM_SUPPLIES ARRAY_SIZE(imx477_supply_name)\n+\n+/*\n+ * Initialisation delay between XCLR low->high and the moment when the sensor\n+ * can start capture (i.e. can leave software standby), given by T7 in the\n+ * datasheet is 8ms.  This does include I2C setup time as well.\n+ *\n+ * Note, that delay between XCLR low->high and reading the CCI ID register (T6\n+ * in the datasheet) is much smaller - 600us.\n+ */\n+#define IMX477_XCLR_MIN_DELAY_US\t8000\n+#define IMX477_XCLR_DELAY_RANGE_US\t1000\n+\n+struct imx477 {\n+\tstruct v4l2_subdev sd;\n+\tstruct media_pad pad[NUM_PADS];\n+\n+\tstruct v4l2_mbus_framefmt fmt;\n+\n+\tstruct clk *xclk;\n+\tu32 xclk_freq;\n+\n+\tstruct gpio_desc *reset_gpio;\n+\tstruct regulator_bulk_data supplies[IMX477_NUM_SUPPLIES];\n+\n+\tstruct v4l2_ctrl_handler ctrl_handler;\n+\t/* V4L2 Controls */\n+\tstruct v4l2_ctrl *pixel_rate;\n+\tstruct v4l2_ctrl *exposure;\n+\tstruct v4l2_ctrl *vflip;\n+\tstruct v4l2_ctrl *hflip;\n+\tstruct v4l2_ctrl *vblank;\n+\tstruct v4l2_ctrl *hblank;\n+\n+\t/* Current mode */\n+\tconst struct imx477_mode *mode;\n+\n+\t/*\n+\t * Mutex for serialized access:\n+\t * Protect sensor module set pad format and start/stop streaming safely.\n+\t */\n+\tstruct mutex mutex;\n+\n+\t/* Streaming on/off */\n+\tbool streaming;\n+\n+\t/* Rewrite common registers on stream on? */\n+\tbool common_regs_written;\n+};\n+\n+static inline struct imx477 *to_imx477(struct v4l2_subdev *_sd)\n+{\n+\treturn container_of(_sd, struct imx477, sd);\n+}\n+\n+static inline void get_mode_table(unsigned int code,\n+\t\t\t\t  const struct imx477_mode **mode_list,\n+\t\t\t\t  unsigned int *num_modes)\n+{\n+\tswitch (code) {\n+\t/* 12-bit */\n+\tcase MEDIA_BUS_FMT_SRGGB12_1X12:\n+\tcase MEDIA_BUS_FMT_SGRBG12_1X12:\n+\tcase MEDIA_BUS_FMT_SGBRG12_1X12:\n+\tcase MEDIA_BUS_FMT_SBGGR12_1X12:\n+\t\t*mode_list = supported_modes_12bit;\n+\t\t*num_modes = ARRAY_SIZE(supported_modes_12bit);\n+\t\tbreak;\n+\t/* 10-bit */\n+\tcase MEDIA_BUS_FMT_SRGGB10_1X10:\n+\tcase MEDIA_BUS_FMT_SGRBG10_1X10:\n+\tcase MEDIA_BUS_FMT_SGBRG10_1X10:\n+\tcase MEDIA_BUS_FMT_SBGGR10_1X10:\n+\t\t*mode_list = supported_modes_10bit;\n+\t\t*num_modes = ARRAY_SIZE(supported_modes_10bit);\n+\t\tbreak;\n+\tdefault:\n+\t\t*mode_list = NULL;\n+\t\t*num_modes = 0;\n+\t}\n+}\n+\n+/* Read registers up to 2 at a time */\n+static int imx477_read_reg(struct imx477 *imx477, u16 reg, u32 len, u32 *val)\n+{\n+\tstruct i2c_client *client = v4l2_get_subdevdata(&imx477->sd);\n+\tstruct i2c_msg msgs[2];\n+\tu8 addr_buf[2] = { reg >> 8, reg & 0xff };\n+\tu8 data_buf[4] = { 0, };\n+\tint ret;\n+\n+\tif (len > 4)\n+\t\treturn -EINVAL;\n+\n+\t/* Write register address */\n+\tmsgs[0].addr = client->addr;\n+\tmsgs[0].flags = 0;\n+\tmsgs[0].len = ARRAY_SIZE(addr_buf);\n+\tmsgs[0].buf = addr_buf;\n+\n+\t/* Read data from register */\n+\tmsgs[1].addr = client->addr;\n+\tmsgs[1].flags = I2C_M_RD;\n+\tmsgs[1].len = len;\n+\tmsgs[1].buf = &data_buf[4 - len];\n+\n+\tret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));\n+\tif (ret != ARRAY_SIZE(msgs))\n+\t\treturn -EIO;\n+\n+\t*val = get_unaligned_be32(data_buf);\n+\n+\treturn 0;\n+}\n+\n+/* Write registers up to 2 at a time */\n+static int imx477_write_reg(struct imx477 *imx477, u16 reg, u32 len, u32 val)\n+{\n+\tstruct i2c_client *client = v4l2_get_subdevdata(&imx477->sd);\n+\tu8 buf[6];\n+\n+\tif (len > 4)\n+\t\treturn -EINVAL;\n+\n+\tput_unaligned_be16(reg, buf);\n+\tput_unaligned_be32(val << (8 * (4 - len)), buf + 2);\n+\tif (i2c_master_send(client, buf, len + 2) != len + 2)\n+\t\treturn -EIO;\n+\n+\treturn 0;\n+}\n+\n+/* Write a list of registers */\n+static int imx477_write_regs(struct imx477 *imx477,\n+\t\t\t     const struct imx477_reg *regs, u32 len)\n+{\n+\tstruct i2c_client *client = v4l2_get_subdevdata(&imx477->sd);\n+\tunsigned int i;\n+\tint ret;\n+\n+\tfor (i = 0; i < len; i++) {\n+\t\tret = imx477_write_reg(imx477, regs[i].address, 1, regs[i].val);\n+\t\tif (ret) {\n+\t\t\tdev_err_ratelimited(&client->dev,\n+\t\t\t\t\t    \"Failed to write reg 0x%4.4x. error = %d\\n\",\n+\t\t\t\t\t    regs[i].address, ret);\n+\n+\t\t\treturn ret;\n+\t\t}\n+\t}\n+\n+\treturn 0;\n+}\n+\n+/* Get bayer order based on flip setting. */\n+static u32 imx477_get_format_code(struct imx477 *imx477, u32 code)\n+{\n+\tunsigned int i;\n+\n+\tlockdep_assert_held(&imx477->mutex);\n+\n+\tfor (i = 0; i < ARRAY_SIZE(codes); i++)\n+\t\tif (codes[i] == code)\n+\t\t\tbreak;\n+\n+\tif (i >= ARRAY_SIZE(codes))\n+\t\ti = 0;\n+\n+\ti = (i & ~3) | (imx477->vflip->val ? 2 : 0) |\n+\t    (imx477->hflip->val ? 1 : 0);\n+\n+\treturn codes[i];\n+}\n+\n+static void imx477_set_default_format(struct imx477 *imx477)\n+{\n+\tstruct v4l2_mbus_framefmt *fmt = &imx477->fmt;\n+\n+\t/* Set default mode to max resolution */\n+\timx477->mode = &supported_modes_12bit[0];\n+\n+\tfmt->code = MEDIA_BUS_FMT_SRGGB12_1X12;\n+\tfmt->colorspace = V4L2_COLORSPACE_SRGB;\n+\tfmt->ycbcr_enc = V4L2_MAP_YCBCR_ENC_DEFAULT(fmt->colorspace);\n+\tfmt->quantization = V4L2_MAP_QUANTIZATION_DEFAULT(true,\n+\t\t\t\t\t\t\t  fmt->colorspace,\n+\t\t\t\t\t\t\t  fmt->ycbcr_enc);\n+\tfmt->xfer_func = V4L2_MAP_XFER_FUNC_DEFAULT(fmt->colorspace);\n+\tfmt->width = imx477->mode->width;\n+\tfmt->height = imx477->mode->height;\n+\tfmt->field = V4L2_FIELD_NONE;\n+}\n+\n+static int imx477_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)\n+{\n+\tstruct imx477 *imx477 = to_imx477(sd);\n+\tstruct v4l2_mbus_framefmt *try_fmt_img =\n+\t\tv4l2_subdev_get_try_format(sd, fh->pad, IMAGE_PAD);\n+\tstruct v4l2_mbus_framefmt *try_fmt_meta =\n+\t\tv4l2_subdev_get_try_format(sd, fh->pad, METADATA_PAD);\n+\tstruct v4l2_rect *try_crop;\n+\n+\tmutex_lock(&imx477->mutex);\n+\n+\t/* Initialize try_fmt for the image pad */\n+\ttry_fmt_img->width = supported_modes_12bit[0].width;\n+\ttry_fmt_img->height = supported_modes_12bit[0].height;\n+\ttry_fmt_img->code = imx477_get_format_code(imx477,\n+\t\t\t\t\t\t   MEDIA_BUS_FMT_SRGGB12_1X12);\n+\ttry_fmt_img->field = V4L2_FIELD_NONE;\n+\n+\t/* Initialize try_fmt for the embedded metadata pad */\n+\ttry_fmt_meta->width = IMX477_EMBEDDED_LINE_WIDTH;\n+\ttry_fmt_meta->height = IMX477_NUM_EMBEDDED_LINES;\n+\ttry_fmt_meta->code = MEDIA_BUS_FMT_SENSOR_DATA;\n+\ttry_fmt_meta->field = V4L2_FIELD_NONE;\n+\n+\t/* Initialize try_crop */\n+\ttry_crop = v4l2_subdev_get_try_crop(sd, fh->pad, IMAGE_PAD);\n+\ttry_crop->left = IMX477_PIXEL_ARRAY_LEFT;\n+\ttry_crop->top = IMX477_PIXEL_ARRAY_TOP;\n+\ttry_crop->width = IMX477_PIXEL_ARRAY_WIDTH;\n+\ttry_crop->height = IMX477_PIXEL_ARRAY_HEIGHT;\n+\n+\tmutex_unlock(&imx477->mutex);\n+\n+\treturn 0;\n+}\n+\n+static int imx477_set_ctrl(struct v4l2_ctrl *ctrl)\n+{\n+\tstruct imx477 *imx477 =\n+\t\tcontainer_of(ctrl->handler, struct imx477, ctrl_handler);\n+\tstruct i2c_client *client = v4l2_get_subdevdata(&imx477->sd);\n+\tint ret = 0;\n+\n+\tif (ctrl->id == V4L2_CID_VBLANK) {\n+\t\tint exposure_max, exposure_def;\n+\n+\t\t/* Update max exposure while meeting expected vblanking */\n+\t\texposure_max = imx477->mode->height + ctrl->val -\n+\t\t\t\t\t\t\tIMX477_EXPOSURE_OFFSET;\n+\t\texposure_def = min(exposure_max, imx477->exposure->val);\n+\t\t__v4l2_ctrl_modify_range(imx477->exposure,\n+\t\t\t\t\t imx477->exposure->minimum,\n+\t\t\t\t\t exposure_max, imx477->exposure->step,\n+\t\t\t\t\t exposure_def);\n+\t}\n+\n+\t/*\n+\t * Applying V4L2 control value only happens\n+\t * when power is up for streaming\n+\t */\n+\tif (pm_runtime_get_if_in_use(&client->dev) == 0)\n+\t\treturn 0;\n+\n+\tswitch (ctrl->id) {\n+\tcase V4L2_CID_ANALOGUE_GAIN:\n+\t\tret = imx477_write_reg(imx477, IMX477_REG_ANALOG_GAIN,\n+\t\t\t\t       IMX477_REG_VALUE_16BIT, ctrl->val);\n+\t\tbreak;\n+\tcase V4L2_CID_EXPOSURE:\n+\t\tret = imx477_write_reg(imx477, IMX477_REG_EXPOSURE,\n+\t\t\t\t       IMX477_REG_VALUE_16BIT, ctrl->val);\n+\t\tbreak;\n+\tcase V4L2_CID_DIGITAL_GAIN:\n+\t\tret = imx477_write_reg(imx477, IMX477_REG_DIGITAL_GAIN,\n+\t\t\t\t       IMX477_REG_VALUE_16BIT, ctrl->val);\n+\t\tbreak;\n+\tcase V4L2_CID_TEST_PATTERN:\n+\t\tret = imx477_write_reg(imx477, IMX477_REG_TEST_PATTERN,\n+\t\t\t\t       IMX477_REG_VALUE_16BIT,\n+\t\t\t\t       imx477_test_pattern_val[ctrl->val]);\n+\t\tbreak;\n+\tcase V4L2_CID_TEST_PATTERN_RED:\n+\t\tret = imx477_write_reg(imx477, IMX477_REG_TEST_PATTERN_R,\n+\t\t\t\t       IMX477_REG_VALUE_16BIT, ctrl->val);\n+\t\tbreak;\n+\tcase V4L2_CID_TEST_PATTERN_GREENR:\n+\t\tret = imx477_write_reg(imx477, IMX477_REG_TEST_PATTERN_GR,\n+\t\t\t\t       IMX477_REG_VALUE_16BIT, ctrl->val);\n+\t\tbreak;\n+\tcase V4L2_CID_TEST_PATTERN_BLUE:\n+\t\tret = imx477_write_reg(imx477, IMX477_REG_TEST_PATTERN_B,\n+\t\t\t\t       IMX477_REG_VALUE_16BIT, ctrl->val);\n+\t\tbreak;\n+\tcase V4L2_CID_TEST_PATTERN_GREENB:\n+\t\tret = imx477_write_reg(imx477, IMX477_REG_TEST_PATTERN_GB,\n+\t\t\t\t       IMX477_REG_VALUE_16BIT, ctrl->val);\n+\t\tbreak;\n+\tcase V4L2_CID_HFLIP:\n+\tcase V4L2_CID_VFLIP:\n+\t\tret = imx477_write_reg(imx477, IMX477_REG_ORIENTATION, 1,\n+\t\t\t\t       imx477->hflip->val |\n+\t\t\t\t       imx477->vflip->val << 1);\n+\t\tbreak;\n+\tcase V4L2_CID_VBLANK:\n+\t\tret = imx477_write_reg(imx477, IMX477_REG_FRAME_LENGTH,\n+\t\t\t\t       IMX477_REG_VALUE_16BIT,\n+\t\t\t\t       imx477->mode->height + ctrl->val);\n+\t\tbreak;\n+\tdefault:\n+\t\tdev_info(&client->dev,\n+\t\t\t \"ctrl(id:0x%x,val:0x%x) is not handled\\n\",\n+\t\t\t ctrl->id, ctrl->val);\n+\t\tret = -EINVAL;\n+\t\tbreak;\n+\t}\n+\n+\tpm_runtime_put(&client->dev);\n+\n+\treturn ret;\n+}\n+\n+static const struct v4l2_ctrl_ops imx477_ctrl_ops = {\n+\t.s_ctrl = imx477_set_ctrl,\n+};\n+\n+static int imx477_enum_mbus_code(struct v4l2_subdev *sd,\n+\t\t\t\t struct v4l2_subdev_pad_config *cfg,\n+\t\t\t\t struct v4l2_subdev_mbus_code_enum *code)\n+{\n+\tstruct imx477 *imx477 = to_imx477(sd);\n+\n+\tif (code->pad >= NUM_PADS)\n+\t\treturn -EINVAL;\n+\n+\tif (code->pad == IMAGE_PAD) {\n+\t\tif (code->index >= (ARRAY_SIZE(codes) / 4))\n+\t\t\treturn -EINVAL;\n+\n+\t\tcode->code = imx477_get_format_code(imx477,\n+\t\t\t\t\t\t    codes[code->index * 4]);\n+\t} else {\n+\t\tif (code->index > 0)\n+\t\t\treturn -EINVAL;\n+\n+\t\tcode->code = MEDIA_BUS_FMT_SENSOR_DATA;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int imx477_enum_frame_size(struct v4l2_subdev *sd,\n+\t\t\t\t  struct v4l2_subdev_pad_config *cfg,\n+\t\t\t\t  struct v4l2_subdev_frame_size_enum *fse)\n+{\n+\tstruct imx477 *imx477 = to_imx477(sd);\n+\n+\tif (fse->pad >= NUM_PADS)\n+\t\treturn -EINVAL;\n+\n+\tif (fse->pad == IMAGE_PAD) {\n+\t\tconst struct imx477_mode *mode_list;\n+\t\tunsigned int num_modes;\n+\n+\t\tget_mode_table(fse->code, &mode_list, &num_modes);\n+\n+\t\tif (fse->index >= num_modes)\n+\t\t\treturn -EINVAL;\n+\n+\t\tif (fse->code != imx477_get_format_code(imx477, fse->code))\n+\t\t\treturn -EINVAL;\n+\n+\t\tfse->min_width = mode_list[fse->index].width;\n+\t\tfse->max_width = fse->min_width;\n+\t\tfse->min_height = mode_list[fse->index].height;\n+\t\tfse->max_height = fse->min_height;\n+\t} else {\n+\t\tif (fse->code != MEDIA_BUS_FMT_SENSOR_DATA || fse->index > 0)\n+\t\t\treturn -EINVAL;\n+\n+\t\tfse->min_width = IMX477_EMBEDDED_LINE_WIDTH;\n+\t\tfse->max_width = fse->min_width;\n+\t\tfse->min_height = IMX477_NUM_EMBEDDED_LINES;\n+\t\tfse->max_height = fse->min_height;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static void imx477_reset_colorspace(struct v4l2_mbus_framefmt *fmt)\n+{\n+\tfmt->colorspace = V4L2_COLORSPACE_SRGB;\n+\tfmt->ycbcr_enc = V4L2_MAP_YCBCR_ENC_DEFAULT(fmt->colorspace);\n+\tfmt->quantization = V4L2_MAP_QUANTIZATION_DEFAULT(true,\n+\t\t\t\t\t\t\t  fmt->colorspace,\n+\t\t\t\t\t\t\t  fmt->ycbcr_enc);\n+\tfmt->xfer_func = V4L2_MAP_XFER_FUNC_DEFAULT(fmt->colorspace);\n+}\n+\n+static void imx477_update_image_pad_format(struct imx477 *imx477,\n+\t\t\t\t\t   const struct imx477_mode *mode,\n+\t\t\t\t\t   struct v4l2_subdev_format *fmt)\n+{\n+\tfmt->format.width = mode->width;\n+\tfmt->format.height = mode->height;\n+\tfmt->format.field = V4L2_FIELD_NONE;\n+\timx477_reset_colorspace(&fmt->format);\n+}\n+\n+static void imx477_update_metadata_pad_format(struct v4l2_subdev_format *fmt)\n+{\n+\tfmt->format.width = IMX477_EMBEDDED_LINE_WIDTH;\n+\tfmt->format.height = IMX477_NUM_EMBEDDED_LINES;\n+\tfmt->format.code = MEDIA_BUS_FMT_SENSOR_DATA;\n+\tfmt->format.field = V4L2_FIELD_NONE;\n+}\n+\n+static int imx477_get_pad_format(struct v4l2_subdev *sd,\n+\t\t\t\t struct v4l2_subdev_pad_config *cfg,\n+\t\t\t\t struct v4l2_subdev_format *fmt)\n+{\n+\tstruct imx477 *imx477 = to_imx477(sd);\n+\n+\tif (fmt->pad >= NUM_PADS)\n+\t\treturn -EINVAL;\n+\n+\tmutex_lock(&imx477->mutex);\n+\n+\tif (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {\n+\t\tstruct v4l2_mbus_framefmt *try_fmt =\n+\t\t\tv4l2_subdev_get_try_format(&imx477->sd, cfg, fmt->pad);\n+\t\t/* update the code which could change due to vflip or hflip: */\n+\t\ttry_fmt->code = fmt->pad == IMAGE_PAD ?\n+\t\t\t\timx477_get_format_code(imx477, try_fmt->code) :\n+\t\t\t\tMEDIA_BUS_FMT_SENSOR_DATA;\n+\t\tfmt->format = *try_fmt;\n+\t} else {\n+\t\tif (fmt->pad == IMAGE_PAD) {\n+\t\t\timx477_update_image_pad_format(imx477, imx477->mode,\n+\t\t\t\t\t\t       fmt);\n+\t\t\tfmt->format.code =\n+\t\t\t       imx477_get_format_code(imx477, imx477->fmt.code);\n+\t\t} else {\n+\t\t\timx477_update_metadata_pad_format(fmt);\n+\t\t}\n+\t}\n+\n+\tmutex_unlock(&imx477->mutex);\n+\treturn 0;\n+}\n+\n+static\n+unsigned int imx477_get_frame_length(const struct imx477_mode *mode,\n+\t\t\t\t     const struct v4l2_fract *timeperframe)\n+{\n+\tu64 frame_length;\n+\n+\tframe_length = (u64)timeperframe->numerator * IMX477_PIXEL_RATE;\n+\tdo_div(frame_length,\n+\t       (u64)timeperframe->denominator * mode->line_length_pix);\n+\n+\tif (WARN_ON(frame_length > IMX477_FRAME_LENGTH_MAX))\n+\t\tframe_length = IMX477_FRAME_LENGTH_MAX;\n+\n+\treturn max_t(unsigned int, frame_length, mode->height);\n+}\n+\n+static void imx477_set_framing_limits(struct imx477 *imx477)\n+{\n+\tconst struct imx477_mode *mode = imx477->mode;\n+\tunsigned int frm_length_min, frm_length_default;\n+\tunsigned int exposure_max, exposure_def, hblank;\n+\n+\tfrm_length_min = imx477_get_frame_length(mode, &mode->timeperframe_min);\n+\tfrm_length_default =\n+\t\t     imx477_get_frame_length(mode, &mode->timeperframe_default);\n+\n+\t/* Update limits and set FPS to default */\n+\t__v4l2_ctrl_modify_range(imx477->vblank, frm_length_min - mode->height,\n+\t\t\t\t IMX477_FRAME_LENGTH_MAX - mode->height,\n+\t\t\t\t 1, frm_length_default - mode->height);\n+\t__v4l2_ctrl_s_ctrl(imx477->vblank, frm_length_default - mode->height);\n+\n+\t/* Update max exposure while meeting expected vblanking */\n+\texposure_max = IMX477_FRAME_LENGTH_MAX - IMX477_EXPOSURE_OFFSET;\n+\texposure_def = frm_length_default - mode->height -\n+\t\t\t\t\t    IMX477_EXPOSURE_OFFSET;\n+\t__v4l2_ctrl_modify_range(imx477->exposure, imx477->exposure->minimum,\n+\t\t\t\t exposure_max, imx477->exposure->step,\n+\t\t\t\t exposure_def);\n+\t/*\n+\t * Currently PPL is fixed to the mode specified value, so hblank\n+\t * depends on mode->width only, and is not changeable in any\n+\t * way other than changing the mode.\n+\t */\n+\thblank = mode->line_length_pix - mode->width;\n+\t__v4l2_ctrl_modify_range(imx477->hblank, hblank, hblank, 1, hblank);\n+}\n+\n+static int imx477_set_pad_format(struct v4l2_subdev *sd,\n+\t\t\t\t struct v4l2_subdev_pad_config *cfg,\n+\t\t\t\t struct v4l2_subdev_format *fmt)\n+{\n+\tstruct v4l2_mbus_framefmt *framefmt;\n+\tconst struct imx477_mode *mode;\n+\tstruct imx477 *imx477 = to_imx477(sd);\n+\n+\tif (fmt->pad >= NUM_PADS)\n+\t\treturn -EINVAL;\n+\n+\tmutex_lock(&imx477->mutex);\n+\n+\tif (fmt->pad == IMAGE_PAD) {\n+\t\tconst struct imx477_mode *mode_list;\n+\t\tunsigned int num_modes;\n+\n+\t\t/* Bayer order varies with flips */\n+\t\tfmt->format.code = imx477_get_format_code(imx477,\n+\t\t\t\t\t\t\t  fmt->format.code);\n+\n+\t\tget_mode_table(fmt->format.code, &mode_list, &num_modes);\n+\n+\t\tmode = v4l2_find_nearest_size(mode_list,\n+\t\t\t\t\t      num_modes,\n+\t\t\t\t\t      width, height,\n+\t\t\t\t\t      fmt->format.width,\n+\t\t\t\t\t      fmt->format.height);\n+\t\timx477_update_image_pad_format(imx477, mode, fmt);\n+\t\tif (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {\n+\t\t\tframefmt = v4l2_subdev_get_try_format(sd, cfg,\n+\t\t\t\t\t\t\t      fmt->pad);\n+\t\t\t*framefmt = fmt->format;\n+\t\t} else {\n+\t\t\timx477->mode = mode;\n+\t\t\timx477_set_framing_limits(imx477);\n+\t\t}\n+\t} else {\n+\t\tif (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {\n+\t\t\tframefmt = v4l2_subdev_get_try_format(sd, cfg,\n+\t\t\t\t\t\t\t      fmt->pad);\n+\t\t\t*framefmt = fmt->format;\n+\t\t} else {\n+\t\t\t/* Only one embedded data mode is supported */\n+\t\t\timx477_update_metadata_pad_format(fmt);\n+\t\t}\n+\t}\n+\n+\tmutex_unlock(&imx477->mutex);\n+\n+\treturn 0;\n+}\n+\n+static const struct v4l2_rect *\n+__imx477_get_pad_crop(struct imx477 *imx477, struct v4l2_subdev_pad_config *cfg,\n+\t\t      unsigned int pad, enum v4l2_subdev_format_whence which)\n+{\n+\tswitch (which) {\n+\tcase V4L2_SUBDEV_FORMAT_TRY:\n+\t\treturn v4l2_subdev_get_try_crop(&imx477->sd, cfg, pad);\n+\tcase V4L2_SUBDEV_FORMAT_ACTIVE:\n+\t\treturn &imx477->mode->crop;\n+\t}\n+\n+\treturn NULL;\n+}\n+\n+static int imx477_get_selection(struct v4l2_subdev *sd,\n+\t\t\t\tstruct v4l2_subdev_pad_config *cfg,\n+\t\t\t\tstruct v4l2_subdev_selection *sel)\n+{\n+\tswitch (sel->target) {\n+\tcase V4L2_SEL_TGT_CROP: {\n+\t\tstruct imx477 *imx477 = to_imx477(sd);\n+\n+\t\tmutex_lock(&imx477->mutex);\n+\t\tsel->r = *__imx477_get_pad_crop(imx477, cfg, sel->pad,\n+\t\t\t\t\t\tsel->which);\n+\t\tmutex_unlock(&imx477->mutex);\n+\n+\t\treturn 0;\n+\t}\n+\n+\tcase V4L2_SEL_TGT_NATIVE_SIZE:\n+\t\tsel->r.left = 0;\n+\t\tsel->r.top = 0;\n+\t\tsel->r.width = IMX477_NATIVE_WIDTH;\n+\t\tsel->r.height = IMX477_NATIVE_HEIGHT;\n+\n+\t\treturn 0;\n+\n+\tcase V4L2_SEL_TGT_CROP_DEFAULT:\n+\t\tsel->r.left = IMX477_PIXEL_ARRAY_LEFT;\n+\t\tsel->r.top = IMX477_PIXEL_ARRAY_TOP;\n+\t\tsel->r.width = IMX477_PIXEL_ARRAY_WIDTH;\n+\t\tsel->r.height = IMX477_PIXEL_ARRAY_HEIGHT;\n+\n+\t\treturn 0;\n+\t}\n+\n+\treturn -EINVAL;\n+}\n+\n+/* Start streaming */\n+static int imx477_start_streaming(struct imx477 *imx477)\n+{\n+\tstruct i2c_client *client = v4l2_get_subdevdata(&imx477->sd);\n+\tconst struct imx477_reg_list *reg_list;\n+\tint ret;\n+\n+\tif (!imx477->common_regs_written) {\n+\t\tret = imx477_write_regs(imx477, mode_common_regs,\n+\t\t\t\t\tARRAY_SIZE(mode_common_regs));\n+\t\tif (ret) {\n+\t\t\tdev_err(&client->dev, \"%s failed to set common settings\\n\",\n+\t\t\t\t__func__);\n+\t\t\treturn ret;\n+\t\t}\n+\t\timx477->common_regs_written = true;\n+\t}\n+\n+\t/* Apply default values of current mode */\n+\treg_list = &imx477->mode->reg_list;\n+\tret = imx477_write_regs(imx477, reg_list->regs, reg_list->num_of_regs);\n+\tif (ret) {\n+\t\tdev_err(&client->dev, \"%s failed to set mode\\n\", __func__);\n+\t\treturn ret;\n+\t}\n+\n+\t/* Apply customized values from user */\n+\tret =  __v4l2_ctrl_handler_setup(imx477->sd.ctrl_handler);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\t/* set stream on register */\n+\treturn imx477_write_reg(imx477, IMX477_REG_MODE_SELECT,\n+\t\t\t\tIMX477_REG_VALUE_08BIT, IMX477_MODE_STREAMING);\n+}\n+\n+/* Stop streaming */\n+static void imx477_stop_streaming(struct imx477 *imx477)\n+{\n+\tstruct i2c_client *client = v4l2_get_subdevdata(&imx477->sd);\n+\tint ret;\n+\n+\t/* set stream off register */\n+\tret = imx477_write_reg(imx477, IMX477_REG_MODE_SELECT,\n+\t\t\t       IMX477_REG_VALUE_08BIT, IMX477_MODE_STANDBY);\n+\tif (ret)\n+\t\tdev_err(&client->dev, \"%s failed to set stream\\n\", __func__);\n+}\n+\n+static int imx477_set_stream(struct v4l2_subdev *sd, int enable)\n+{\n+\tstruct imx477 *imx477 = to_imx477(sd);\n+\tstruct i2c_client *client = v4l2_get_subdevdata(sd);\n+\tint ret = 0;\n+\n+\tmutex_lock(&imx477->mutex);\n+\tif (imx477->streaming == enable) {\n+\t\tmutex_unlock(&imx477->mutex);\n+\t\treturn 0;\n+\t}\n+\n+\tif (enable) {\n+\t\tret = pm_runtime_get_sync(&client->dev);\n+\t\tif (ret < 0) {\n+\t\t\tpm_runtime_put_noidle(&client->dev);\n+\t\t\tgoto err_unlock;\n+\t\t}\n+\n+\t\t/*\n+\t\t * Apply default & customized values\n+\t\t * and then start streaming.\n+\t\t */\n+\t\tret = imx477_start_streaming(imx477);\n+\t\tif (ret)\n+\t\t\tgoto err_rpm_put;\n+\t} else {\n+\t\timx477_stop_streaming(imx477);\n+\t\tpm_runtime_put(&client->dev);\n+\t}\n+\n+\timx477->streaming = enable;\n+\n+\t/* vflip and hflip cannot change during streaming */\n+\t__v4l2_ctrl_grab(imx477->vflip, enable);\n+\t__v4l2_ctrl_grab(imx477->hflip, enable);\n+\n+\tmutex_unlock(&imx477->mutex);\n+\n+\treturn ret;\n+\n+err_rpm_put:\n+\tpm_runtime_put(&client->dev);\n+err_unlock:\n+\tmutex_unlock(&imx477->mutex);\n+\n+\treturn ret;\n+}\n+\n+/* Power/clock management functions */\n+static int imx477_power_on(struct device *dev)\n+{\n+\tstruct i2c_client *client = to_i2c_client(dev);\n+\tstruct v4l2_subdev *sd = i2c_get_clientdata(client);\n+\tstruct imx477 *imx477 = to_imx477(sd);\n+\tint ret;\n+\n+\tret = regulator_bulk_enable(IMX477_NUM_SUPPLIES,\n+\t\t\t\t    imx477->supplies);\n+\tif (ret) {\n+\t\tdev_err(&client->dev, \"%s: failed to enable regulators\\n\",\n+\t\t\t__func__);\n+\t\treturn ret;\n+\t}\n+\n+\tret = clk_prepare_enable(imx477->xclk);\n+\tif (ret) {\n+\t\tdev_err(&client->dev, \"%s: failed to enable clock\\n\",\n+\t\t\t__func__);\n+\t\tgoto reg_off;\n+\t}\n+\n+\tgpiod_set_value_cansleep(imx477->reset_gpio, 1);\n+\tusleep_range(IMX477_XCLR_MIN_DELAY_US,\n+\t\t     IMX477_XCLR_MIN_DELAY_US + IMX477_XCLR_DELAY_RANGE_US);\n+\n+\treturn 0;\n+\n+reg_off:\n+\tregulator_bulk_disable(IMX477_NUM_SUPPLIES, imx477->supplies);\n+\treturn ret;\n+}\n+\n+static int imx477_power_off(struct device *dev)\n+{\n+\tstruct i2c_client *client = to_i2c_client(dev);\n+\tstruct v4l2_subdev *sd = i2c_get_clientdata(client);\n+\tstruct imx477 *imx477 = to_imx477(sd);\n+\n+\tgpiod_set_value_cansleep(imx477->reset_gpio, 0);\n+\tregulator_bulk_disable(IMX477_NUM_SUPPLIES, imx477->supplies);\n+\tclk_disable_unprepare(imx477->xclk);\n+\n+\t/* Force reprogramming of the common registers when powered up again. */\n+\timx477->common_regs_written = false;\n+\n+\treturn 0;\n+}\n+\n+static int __maybe_unused imx477_suspend(struct device *dev)\n+{\n+\tstruct i2c_client *client = to_i2c_client(dev);\n+\tstruct v4l2_subdev *sd = i2c_get_clientdata(client);\n+\tstruct imx477 *imx477 = to_imx477(sd);\n+\n+\tif (imx477->streaming)\n+\t\timx477_stop_streaming(imx477);\n+\n+\treturn 0;\n+}\n+\n+static int __maybe_unused imx477_resume(struct device *dev)\n+{\n+\tstruct i2c_client *client = to_i2c_client(dev);\n+\tstruct v4l2_subdev *sd = i2c_get_clientdata(client);\n+\tstruct imx477 *imx477 = to_imx477(sd);\n+\tint ret;\n+\n+\tif (imx477->streaming) {\n+\t\tret = imx477_start_streaming(imx477);\n+\t\tif (ret)\n+\t\t\tgoto error;\n+\t}\n+\n+\treturn 0;\n+\n+error:\n+\timx477_stop_streaming(imx477);\n+\timx477->streaming = 0;\n+\treturn ret;\n+}\n+\n+static int imx477_get_regulators(struct imx477 *imx477)\n+{\n+\tstruct i2c_client *client = v4l2_get_subdevdata(&imx477->sd);\n+\tunsigned int i;\n+\n+\tfor (i = 0; i < IMX477_NUM_SUPPLIES; i++)\n+\t\timx477->supplies[i].supply = imx477_supply_name[i];\n+\n+\treturn devm_regulator_bulk_get(&client->dev,\n+\t\t\t\t       IMX477_NUM_SUPPLIES,\n+\t\t\t\t       imx477->supplies);\n+}\n+\n+/* Verify chip ID */\n+static int imx477_identify_module(struct imx477 *imx477)\n+{\n+\tstruct i2c_client *client = v4l2_get_subdevdata(&imx477->sd);\n+\tint ret;\n+\tu32 val;\n+\n+\tret = imx477_read_reg(imx477, IMX477_REG_CHIP_ID,\n+\t\t\t      IMX477_REG_VALUE_16BIT, &val);\n+\tif (ret) {\n+\t\tdev_err(&client->dev, \"failed to read chip id %x, with error %d\\n\",\n+\t\t\tIMX477_CHIP_ID, ret);\n+\t\treturn ret;\n+\t}\n+\n+\tif (val != IMX477_CHIP_ID) {\n+\t\tdev_err(&client->dev, \"chip id mismatch: %x!=%x\\n\",\n+\t\t\tIMX477_CHIP_ID, val);\n+\t\tret = -EINVAL;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static const struct v4l2_subdev_core_ops imx477_core_ops = {\n+\t.subscribe_event = v4l2_ctrl_subdev_subscribe_event,\n+\t.unsubscribe_event = v4l2_event_subdev_unsubscribe,\n+};\n+\n+static const struct v4l2_subdev_video_ops imx477_video_ops = {\n+\t.s_stream = imx477_set_stream,\n+};\n+\n+static const struct v4l2_subdev_pad_ops imx477_pad_ops = {\n+\t.enum_mbus_code = imx477_enum_mbus_code,\n+\t.get_fmt = imx477_get_pad_format,\n+\t.set_fmt = imx477_set_pad_format,\n+\t.get_selection = imx477_get_selection,\n+\t.enum_frame_size = imx477_enum_frame_size,\n+};\n+\n+static const struct v4l2_subdev_ops imx477_subdev_ops = {\n+\t.core = &imx477_core_ops,\n+\t.video = &imx477_video_ops,\n+\t.pad = &imx477_pad_ops,\n+};\n+\n+static const struct v4l2_subdev_internal_ops imx477_internal_ops = {\n+\t.open = imx477_open,\n+};\n+\n+/* Initialize control handlers */\n+static int imx477_init_controls(struct imx477 *imx477)\n+{\n+\tstruct v4l2_ctrl_handler *ctrl_hdlr;\n+\tstruct i2c_client *client = v4l2_get_subdevdata(&imx477->sd);\n+\tunsigned int i;\n+\tint ret;\n+\n+\tctrl_hdlr = &imx477->ctrl_handler;\n+\tret = v4l2_ctrl_handler_init(ctrl_hdlr, 14);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tmutex_init(&imx477->mutex);\n+\tctrl_hdlr->lock = &imx477->mutex;\n+\n+\t/* By default, PIXEL_RATE is read only */\n+\timx477->pixel_rate = v4l2_ctrl_new_std(ctrl_hdlr, &imx477_ctrl_ops,\n+\t\t\t\t\t       V4L2_CID_PIXEL_RATE,\n+\t\t\t\t\t       IMX477_PIXEL_RATE,\n+\t\t\t\t\t       IMX477_PIXEL_RATE, 1,\n+\t\t\t\t\t       IMX477_PIXEL_RATE);\n+\n+\t/*\n+\t * Create the controls here, but mode specific limits are setup\n+\t * in the imx477_set_framing_limits() call below.\n+\t */\n+\timx477->vblank = v4l2_ctrl_new_std(ctrl_hdlr, &imx477_ctrl_ops,\n+\t\t\t\t\t   V4L2_CID_VBLANK, 0, 0xffff, 1, 0);\n+\timx477->hblank = v4l2_ctrl_new_std(ctrl_hdlr, &imx477_ctrl_ops,\n+\t\t\t\t\t   V4L2_CID_HBLANK, 0, 0xffff, 1, 0);\n+\n+\t/* HBLANK is read-only for now, but does change with mode. */\n+\tif (imx477->hblank)\n+\t\timx477->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;\n+\n+\timx477->exposure = v4l2_ctrl_new_std(ctrl_hdlr, &imx477_ctrl_ops,\n+\t\t\t\t\t     V4L2_CID_EXPOSURE,\n+\t\t\t\t\t     IMX477_EXPOSURE_MIN,\n+\t\t\t\t\t     IMX477_EXPOSURE_MAX,\n+\t\t\t\t\t     IMX477_EXPOSURE_STEP,\n+\t\t\t\t\t     IMX477_EXPOSURE_DEFAULT);\n+\n+\tv4l2_ctrl_new_std(ctrl_hdlr, &imx477_ctrl_ops, V4L2_CID_ANALOGUE_GAIN,\n+\t\t\t  IMX477_ANA_GAIN_MIN, IMX477_ANA_GAIN_MAX,\n+\t\t\t  IMX477_ANA_GAIN_STEP, IMX477_ANA_GAIN_DEFAULT);\n+\n+\tv4l2_ctrl_new_std(ctrl_hdlr, &imx477_ctrl_ops, V4L2_CID_DIGITAL_GAIN,\n+\t\t\t  IMX477_DGTL_GAIN_MIN, IMX477_DGTL_GAIN_MAX,\n+\t\t\t  IMX477_DGTL_GAIN_STEP, IMX477_DGTL_GAIN_DEFAULT);\n+\n+\timx477->hflip = v4l2_ctrl_new_std(ctrl_hdlr, &imx477_ctrl_ops,\n+\t\t\t\t\t  V4L2_CID_HFLIP, 0, 1, 1, 0);\n+\tif (imx477->hflip)\n+\t\timx477->hflip->flags |= V4L2_CTRL_FLAG_MODIFY_LAYOUT;\n+\n+\timx477->vflip = v4l2_ctrl_new_std(ctrl_hdlr, &imx477_ctrl_ops,\n+\t\t\t\t\t  V4L2_CID_VFLIP, 0, 1, 1, 0);\n+\tif (imx477->vflip)\n+\t\timx477->vflip->flags |= V4L2_CTRL_FLAG_MODIFY_LAYOUT;\n+\n+\tv4l2_ctrl_new_std_menu_items(ctrl_hdlr, &imx477_ctrl_ops,\n+\t\t\t\t     V4L2_CID_TEST_PATTERN,\n+\t\t\t\t     ARRAY_SIZE(imx477_test_pattern_menu) - 1,\n+\t\t\t\t     0, 0, imx477_test_pattern_menu);\n+\tfor (i = 0; i < 4; i++) {\n+\t\t/*\n+\t\t * The assumption is that\n+\t\t * V4L2_CID_TEST_PATTERN_GREENR == V4L2_CID_TEST_PATTERN_RED + 1\n+\t\t * V4L2_CID_TEST_PATTERN_BLUE   == V4L2_CID_TEST_PATTERN_RED + 2\n+\t\t * V4L2_CID_TEST_PATTERN_GREENB == V4L2_CID_TEST_PATTERN_RED + 3\n+\t\t */\n+\t\tv4l2_ctrl_new_std(ctrl_hdlr, &imx477_ctrl_ops,\n+\t\t\t\t  V4L2_CID_TEST_PATTERN_RED + i,\n+\t\t\t\t  IMX477_TEST_PATTERN_COLOUR_MIN,\n+\t\t\t\t  IMX477_TEST_PATTERN_COLOUR_MAX,\n+\t\t\t\t  IMX477_TEST_PATTERN_COLOUR_STEP,\n+\t\t\t\t  IMX477_TEST_PATTERN_COLOUR_MAX);\n+\t\t/* The \"Solid color\" pattern is white by default */\n+\t}\n+\n+\tif (ctrl_hdlr->error) {\n+\t\tret = ctrl_hdlr->error;\n+\t\tdev_err(&client->dev, \"%s control init failed (%d)\\n\",\n+\t\t\t__func__, ret);\n+\t\tgoto error;\n+\t}\n+\n+\timx477->sd.ctrl_handler = ctrl_hdlr;\n+\n+\t/* Setup exposure and frame/line length limits. */\n+\timx477_set_framing_limits(imx477);\n+\n+\treturn 0;\n+\n+error:\n+\tv4l2_ctrl_handler_free(ctrl_hdlr);\n+\tmutex_destroy(&imx477->mutex);\n+\n+\treturn ret;\n+}\n+\n+static void imx477_free_controls(struct imx477 *imx477)\n+{\n+\tv4l2_ctrl_handler_free(imx477->sd.ctrl_handler);\n+\tmutex_destroy(&imx477->mutex);\n+}\n+\n+static int imx477_check_hwcfg(struct device *dev)\n+{\n+\tstruct fwnode_handle *endpoint;\n+\tstruct v4l2_fwnode_endpoint ep_cfg = {\n+\t\t.bus_type = V4L2_MBUS_CSI2_DPHY\n+\t};\n+\tint ret = -EINVAL;\n+\n+\tendpoint = fwnode_graph_get_next_endpoint(dev_fwnode(dev), NULL);\n+\tif (!endpoint) {\n+\t\tdev_err(dev, \"endpoint node not found\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (v4l2_fwnode_endpoint_alloc_parse(endpoint, &ep_cfg)) {\n+\t\tdev_err(dev, \"could not parse endpoint\\n\");\n+\t\tgoto error_out;\n+\t}\n+\n+\t/* Check the number of MIPI CSI2 data lanes */\n+\tif (ep_cfg.bus.mipi_csi2.num_data_lanes != 2) {\n+\t\tdev_err(dev, \"only 2 data lanes are currently supported\\n\");\n+\t\tgoto error_out;\n+\t}\n+\n+\t/* Check the link frequency set in device tree */\n+\tif (!ep_cfg.nr_of_link_frequencies) {\n+\t\tdev_err(dev, \"link-frequency property not found in DT\\n\");\n+\t\tgoto error_out;\n+\t}\n+\n+\tif (ep_cfg.nr_of_link_frequencies != 1 ||\n+\t    ep_cfg.link_frequencies[0] != IMX477_DEFAULT_LINK_FREQ) {\n+\t\tdev_err(dev, \"Link frequency not supported: %lld\\n\",\n+\t\t\tep_cfg.link_frequencies[0]);\n+\t\tgoto error_out;\n+\t}\n+\n+\tret = 0;\n+\n+error_out:\n+\tv4l2_fwnode_endpoint_free(&ep_cfg);\n+\tfwnode_handle_put(endpoint);\n+\n+\treturn ret;\n+}\n+\n+static int imx477_probe(struct i2c_client *client)\n+{\n+\tstruct device *dev = &client->dev;\n+\tstruct imx477 *imx477;\n+\tint ret;\n+\n+\timx477 = devm_kzalloc(&client->dev, sizeof(*imx477), GFP_KERNEL);\n+\tif (!imx477)\n+\t\treturn -ENOMEM;\n+\n+\tv4l2_i2c_subdev_init(&imx477->sd, client, &imx477_subdev_ops);\n+\n+\t/* Check the hardware configuration in device tree */\n+\tif (imx477_check_hwcfg(dev))\n+\t\treturn -EINVAL;\n+\n+\t/* Get system clock (xclk) */\n+\timx477->xclk = devm_clk_get(dev, NULL);\n+\tif (IS_ERR(imx477->xclk)) {\n+\t\tdev_err(dev, \"failed to get xclk\\n\");\n+\t\treturn PTR_ERR(imx477->xclk);\n+\t}\n+\n+\timx477->xclk_freq = clk_get_rate(imx477->xclk);\n+\tif (imx477->xclk_freq != IMX477_XCLK_FREQ) {\n+\t\tdev_err(dev, \"xclk frequency not supported: %d Hz\\n\",\n+\t\t\timx477->xclk_freq);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tret = imx477_get_regulators(imx477);\n+\tif (ret) {\n+\t\tdev_err(dev, \"failed to get regulators\\n\");\n+\t\treturn ret;\n+\t}\n+\n+\t/* Request optional enable pin */\n+\timx477->reset_gpio = devm_gpiod_get_optional(dev, \"reset\",\n+\t\t\t\t\t\t     GPIOD_OUT_HIGH);\n+\n+\t/*\n+\t * The sensor must be powered for imx477_identify_module()\n+\t * to be able to read the CHIP_ID register\n+\t */\n+\tret = imx477_power_on(dev);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = imx477_identify_module(imx477);\n+\tif (ret)\n+\t\tgoto error_power_off;\n+\n+\t/* Initialize default format */\n+\timx477_set_default_format(imx477);\n+\n+\t/* Enable runtime PM and turn off the device */\n+\tpm_runtime_set_active(dev);\n+\tpm_runtime_enable(dev);\n+\tpm_runtime_idle(dev);\n+\n+\t/* This needs the pm runtime to be registered. */\n+\tret = imx477_init_controls(imx477);\n+\tif (ret)\n+\t\tgoto error_power_off;\n+\n+\t/* Initialize subdev */\n+\timx477->sd.internal_ops = &imx477_internal_ops;\n+\timx477->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |\n+\t\t\t    V4L2_SUBDEV_FL_HAS_EVENTS;\n+\timx477->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;\n+\n+\t/* Initialize source pads */\n+\timx477->pad[IMAGE_PAD].flags = MEDIA_PAD_FL_SOURCE;\n+\timx477->pad[METADATA_PAD].flags = MEDIA_PAD_FL_SOURCE;\n+\n+\tret = media_entity_pads_init(&imx477->sd.entity, NUM_PADS, imx477->pad);\n+\tif (ret) {\n+\t\tdev_err(dev, \"failed to init entity pads: %d\\n\", ret);\n+\t\tgoto error_handler_free;\n+\t}\n+\n+\tret = v4l2_async_register_subdev_sensor_common(&imx477->sd);\n+\tif (ret < 0) {\n+\t\tdev_err(dev, \"failed to register sensor sub-device: %d\\n\", ret);\n+\t\tgoto error_media_entity;\n+\t}\n+\n+\treturn 0;\n+\n+error_media_entity:\n+\tmedia_entity_cleanup(&imx477->sd.entity);\n+\n+error_handler_free:\n+\timx477_free_controls(imx477);\n+\n+error_power_off:\n+\tpm_runtime_disable(&client->dev);\n+\tpm_runtime_set_suspended(&client->dev);\n+\timx477_power_off(&client->dev);\n+\n+\treturn ret;\n+}\n+\n+static int imx477_remove(struct i2c_client *client)\n+{\n+\tstruct v4l2_subdev *sd = i2c_get_clientdata(client);\n+\tstruct imx477 *imx477 = to_imx477(sd);\n+\n+\tv4l2_async_unregister_subdev(sd);\n+\tmedia_entity_cleanup(&sd->entity);\n+\timx477_free_controls(imx477);\n+\n+\tpm_runtime_disable(&client->dev);\n+\tif (!pm_runtime_status_suspended(&client->dev))\n+\t\timx477_power_off(&client->dev);\n+\tpm_runtime_set_suspended(&client->dev);\n+\n+\treturn 0;\n+}\n+\n+static const struct of_device_id imx477_dt_ids[] = {\n+\t{ .compatible = \"sony,imx477\" },\n+\t{ /* sentinel */ }\n+};\n+MODULE_DEVICE_TABLE(of, imx477_dt_ids);\n+\n+static const struct dev_pm_ops imx477_pm_ops = {\n+\tSET_SYSTEM_SLEEP_PM_OPS(imx477_suspend, imx477_resume)\n+\tSET_RUNTIME_PM_OPS(imx477_power_off, imx477_power_on, NULL)\n+};\n+\n+static struct i2c_driver imx477_i2c_driver = {\n+\t.driver = {\n+\t\t.name = \"imx477\",\n+\t\t.of_match_table\t= imx477_dt_ids,\n+\t\t.pm = &imx477_pm_ops,\n+\t},\n+\t.probe_new = imx477_probe,\n+\t.remove = imx477_remove,\n+};\n+\n+module_i2c_driver(imx477_i2c_driver);\n+\n+MODULE_AUTHOR(\"Naushir Patuck <naush@raspberrypi.com>\");\n+MODULE_DESCRIPTION(\"Sony IMX477 sensor driver\");\n+MODULE_LICENSE(\"GPL v2\");\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0324-media-i2c-imx477-Add-support-for-adaptive-frame-cont.patch",
    "content": "From bb77f5ad580f08b0b60579370ad176a23960364a Mon Sep 17 00:00:00 2001\nFrom: Naushir Patuck <naush@raspberrypi.com>\nDate: Fri, 8 May 2020 09:41:17 +0100\nSubject: [PATCH] media: i2c: imx477: Add support for adaptive frame\n control\n\nUse V4L2_CID_EXPOSURE_AUTO_PRIORITY to control if the driver should\nautomatically adjust the sensor frame length based on exposure time,\nallowing variable frame rates and longer exposures.\n\nSigned-off-by: Naushir Patuck <naush@raspberrypi.com>\n---\n drivers/media/i2c/imx477.c | 113 +++++++++++++++++++++++++++++--------\n 1 file changed, 91 insertions(+), 22 deletions(-)\n\n--- a/drivers/media/i2c/imx477.c\n+++ b/drivers/media/i2c/imx477.c\n@@ -1082,6 +1082,8 @@ struct imx477 {\n \tstruct v4l2_ctrl *hflip;\n \tstruct v4l2_ctrl *vblank;\n \tstruct v4l2_ctrl *hblank;\n+\t/* This ctrl allows automatic variable framerate */\n+\tstruct v4l2_ctrl *exposure_auto;\n \n \t/* Current mode */\n \tconst struct imx477_mode *mode;\n@@ -1278,6 +1280,72 @@ static int imx477_open(struct v4l2_subde\n \treturn 0;\n }\n \n+static int imx477_set_exposure(struct imx477 *imx477, unsigned int val)\n+{\n+\tint ret;\n+\n+\tret = imx477_write_reg(imx477, IMX477_REG_EXPOSURE,\n+\t\t\t       IMX477_REG_VALUE_16BIT, val);\n+\n+\t/* Setup the frame length in the case of auto framerate mode. */\n+\tif (imx477->exposure_auto->val) {\n+\t\tunsigned int frame_length, frame_length_max, frame_length_min;\n+\n+\t\tframe_length_min = imx477->vblank->minimum +\n+\t\t\t\t   imx477->mode->height;\n+\t\tframe_length_max = imx477->vblank->maximum +\n+\t\t\t\t   imx477->mode->height;\n+\t\tframe_length = max(frame_length_min,\n+\t\t\t\t   val + IMX477_EXPOSURE_OFFSET);\n+\t\tframe_length = min(frame_length_max, frame_length);\n+\t\tret += imx477_write_reg(imx477, IMX477_REG_FRAME_LENGTH,\n+\t\t\t\t\tIMX477_REG_VALUE_16BIT, frame_length);\n+\t}\n+\n+\treturn ret;\n+}\n+\n+static void imx477_adjust_exposure_range(struct imx477 *imx477,\n+\t\t\t\t\t struct v4l2_ctrl *ctrl)\n+{\n+\tint exposure_max, exposure_def;\n+\n+\tif (ctrl->id == V4L2_CID_VBLANK || !ctrl->val) {\n+\t\t/*\n+\t\t * Either VBLANK has been changed or auto framerate\n+\t\t * adjusting has been disabled. Honour the VBLANK limits\n+\t\t * when setting exposure.\n+\t\t */\n+\t\texposure_max = imx477->mode->height + imx477->vblank->val -\n+\t\t\t\t\t\t      IMX477_EXPOSURE_OFFSET;\n+\n+\t\tif (ctrl->id == V4L2_CID_EXPOSURE_AUTO_PRIORITY) {\n+\t\t\t/*\n+\t\t\t * Allow VBLANK adjustments since the driver is not\n+\t\t\t * handling frame length control automatically.\n+\t\t\t */\n+\t\t\t__v4l2_ctrl_grab(imx477->vblank, false);\n+\t\t}\n+\t} else {\n+\t\t/*\n+\t\t * Auto framerate adjusting has been enabled. VBLANK\n+\t\t * ctrl has been disabled and exposure can ramp up\n+\t\t * to the maximum allowable value.\n+\t\t */\n+\t\texposure_max = IMX477_EXPOSURE_MAX;\n+\t\t/*\n+\t\t * Do not allow VBLANK adjustments if the driver is\n+\t\t * handling it frame length control automatically.\n+\t\t */\n+\t\t__v4l2_ctrl_grab(imx477->vblank, true);\n+\t}\n+\n+\texposure_def = min(exposure_max, imx477->exposure->val);\n+\t__v4l2_ctrl_modify_range(imx477->exposure, imx477->exposure->minimum,\n+\t\t\t\t exposure_max, imx477->exposure->step,\n+\t\t\t\t exposure_def);\n+}\n+\n static int imx477_set_ctrl(struct v4l2_ctrl *ctrl)\n {\n \tstruct imx477 *imx477 =\n@@ -1285,17 +1353,13 @@ static int imx477_set_ctrl(struct v4l2_c\n \tstruct i2c_client *client = v4l2_get_subdevdata(&imx477->sd);\n \tint ret = 0;\n \n-\tif (ctrl->id == V4L2_CID_VBLANK) {\n-\t\tint exposure_max, exposure_def;\n-\n-\t\t/* Update max exposure while meeting expected vblanking */\n-\t\texposure_max = imx477->mode->height + ctrl->val -\n-\t\t\t\t\t\t\tIMX477_EXPOSURE_OFFSET;\n-\t\texposure_def = min(exposure_max, imx477->exposure->val);\n-\t\t__v4l2_ctrl_modify_range(imx477->exposure,\n-\t\t\t\t\t imx477->exposure->minimum,\n-\t\t\t\t\t exposure_max, imx477->exposure->step,\n-\t\t\t\t\t exposure_def);\n+\tif (ctrl->id == V4L2_CID_VBLANK ||\n+\t    ctrl->id == V4L2_CID_EXPOSURE_AUTO_PRIORITY) {\n+\t\t/*\n+\t\t * These controls may change the limits of usable exposure,\n+\t\t * so check and adjust if necessary.\n+\t\t */\n+\t\timx477_adjust_exposure_range(imx477, ctrl);\n \t}\n \n \t/*\n@@ -1311,8 +1375,14 @@ static int imx477_set_ctrl(struct v4l2_c\n \t\t\t\t       IMX477_REG_VALUE_16BIT, ctrl->val);\n \t\tbreak;\n \tcase V4L2_CID_EXPOSURE:\n-\t\tret = imx477_write_reg(imx477, IMX477_REG_EXPOSURE,\n-\t\t\t\t       IMX477_REG_VALUE_16BIT, ctrl->val);\n+\t\tret = imx477_set_exposure(imx477, ctrl->val);\n+\t\tbreak;\n+\tcase V4L2_CID_EXPOSURE_AUTO_PRIORITY:\n+\t\t/*\n+\t\t * imx477_set_exposure() will recalculate the frame length\n+\t\t * to adjust the framerate to match the exposure.\n+\t\t */\n+\t\tret = imx477_set_exposure(imx477, imx477->exposure->val);\n \t\tbreak;\n \tcase V4L2_CID_DIGITAL_GAIN:\n \t\tret = imx477_write_reg(imx477, IMX477_REG_DIGITAL_GAIN,\n@@ -1510,9 +1580,8 @@ unsigned int imx477_get_frame_length(con\n \n static void imx477_set_framing_limits(struct imx477 *imx477)\n {\n+\tunsigned int frm_length_min, frm_length_default, hblank;\n \tconst struct imx477_mode *mode = imx477->mode;\n-\tunsigned int frm_length_min, frm_length_default;\n-\tunsigned int exposure_max, exposure_def, hblank;\n \n \tfrm_length_min = imx477_get_frame_length(mode, &mode->timeperframe_min);\n \tfrm_length_default =\n@@ -1522,15 +1591,10 @@ static void imx477_set_framing_limits(st\n \t__v4l2_ctrl_modify_range(imx477->vblank, frm_length_min - mode->height,\n \t\t\t\t IMX477_FRAME_LENGTH_MAX - mode->height,\n \t\t\t\t 1, frm_length_default - mode->height);\n+\n+\t/* Setting this will adjust the exposure limits as well. */\n \t__v4l2_ctrl_s_ctrl(imx477->vblank, frm_length_default - mode->height);\n \n-\t/* Update max exposure while meeting expected vblanking */\n-\texposure_max = IMX477_FRAME_LENGTH_MAX - IMX477_EXPOSURE_OFFSET;\n-\texposure_def = frm_length_default - mode->height -\n-\t\t\t\t\t    IMX477_EXPOSURE_OFFSET;\n-\t__v4l2_ctrl_modify_range(imx477->exposure, imx477->exposure->minimum,\n-\t\t\t\t exposure_max, imx477->exposure->step,\n-\t\t\t\t exposure_def);\n \t/*\n \t * Currently PPL is fixed to the mode specified value, so hblank\n \t * depends on mode->width only, and is not changeable in any\n@@ -1939,6 +2003,11 @@ static int imx477_init_controls(struct i\n \t\t\t  IMX477_DGTL_GAIN_MIN, IMX477_DGTL_GAIN_MAX,\n \t\t\t  IMX477_DGTL_GAIN_STEP, IMX477_DGTL_GAIN_DEFAULT);\n \n+\timx477->exposure_auto =\n+\t\t\tv4l2_ctrl_new_std(ctrl_hdlr, &imx477_ctrl_ops,\n+\t\t\t\t\t  V4L2_CID_EXPOSURE_AUTO_PRIORITY,\n+\t\t\t\t\t  0, 1, 1, 0);\n+\n \timx477->hflip = v4l2_ctrl_new_std(ctrl_hdlr, &imx477_ctrl_ops,\n \t\t\t\t\t  V4L2_CID_HFLIP, 0, 1, 1, 0);\n \tif (imx477->hflip)\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0325-media-i2c-imx477-Return-correct-result-on-sensor-id-.patch",
    "content": "From 15f2ddb7175008d14b25b7ab2eb71b487a497327 Mon Sep 17 00:00:00 2001\nFrom: Naushir Patuck <naush@raspberrypi.com>\nDate: Tue, 19 May 2020 16:56:33 +0100\nSubject: [PATCH] media: i2c: imx477: Return correct result on sensor\n id verification\n\nThe test should return -EIO if the register read id does not match\nthe expected sensor id.\n\nSigned-off-by: Naushir Patuck <naush@raspberrypi.com>\n---\n drivers/media/i2c/imx477.c | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/drivers/media/i2c/imx477.c\n+++ b/drivers/media/i2c/imx477.c\n@@ -1919,7 +1919,7 @@ static int imx477_identify_module(struct\n \tif (val != IMX477_CHIP_ID) {\n \t\tdev_err(&client->dev, \"chip id mismatch: %x!=%x\\n\",\n \t\t\tIMX477_CHIP_ID, val);\n-\t\tret = -EINVAL;\n+\t\treturn -EIO;\n \t}\n \n \treturn 0;\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0326-media-i2c-imx477-Parse-and-register-properties.patch",
    "content": "From 2a968d0a82efc2018f1831adbcbfa093f8032c87 Mon Sep 17 00:00:00 2001\nFrom: Laurent Pinchart <laurent.pinchart@ideasonboard.com>\nDate: Sat, 4 Jul 2020 01:45:08 +0300\nSubject: [PATCH] media: i2c: imx477: Parse and register properties\n\nParse device properties and register controls for them using the V4L2\nfwnode properties helpers.\n\nSigned-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>\n---\n drivers/media/i2c/imx477.c | 12 +++++++++++-\n 1 file changed, 11 insertions(+), 1 deletion(-)\n\n--- a/drivers/media/i2c/imx477.c\n+++ b/drivers/media/i2c/imx477.c\n@@ -1957,11 +1957,12 @@ static int imx477_init_controls(struct i\n {\n \tstruct v4l2_ctrl_handler *ctrl_hdlr;\n \tstruct i2c_client *client = v4l2_get_subdevdata(&imx477->sd);\n+\tstruct v4l2_fwnode_device_properties props;\n \tunsigned int i;\n \tint ret;\n \n \tctrl_hdlr = &imx477->ctrl_handler;\n-\tret = v4l2_ctrl_handler_init(ctrl_hdlr, 14);\n+\tret = v4l2_ctrl_handler_init(ctrl_hdlr, 16);\n \tif (ret)\n \t\treturn ret;\n \n@@ -2045,6 +2046,15 @@ static int imx477_init_controls(struct i\n \t\tgoto error;\n \t}\n \n+\tret = v4l2_fwnode_device_parse(&client->dev, &props);\n+\tif (ret)\n+\t\tgoto error;\n+\n+\tret = v4l2_ctrl_new_fwnode_properties(ctrl_hdlr, &imx477_ctrl_ops,\n+\t\t\t\t\t      &props);\n+\tif (ret)\n+\t\tgoto error;\n+\n \timx477->sd.ctrl_handler = ctrl_hdlr;\n \n \t/* Setup exposure and frame/line length limits. */\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0327-media-bcm2835-unicam-Always-service-interrupts.patch",
    "content": "From 3b1b2e000ea9430f6ccf588cb920bd8615701e1d Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Wed, 13 May 2020 18:28:27 +0100\nSubject: [PATCH] media: bcm2835-unicam: Always service interrupts\n\nFrom when bringing up the driver, there was a check in the isr\nto ignore interrupts (claiming them handled) should the driver\nnot be streaming.\n\nThe VPU now will not register a camera driver if it finds a\nCSI2 node enabled in device tree, therefore this flawed check is\nredundant.\n\nhttps://github.com/raspberrypi/linux/issues/3602\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n drivers/media/platform/bcm2835/bcm2835-unicam.c | 15 ---------------\n 1 file changed, 15 deletions(-)\n\n--- a/drivers/media/platform/bcm2835/bcm2835-unicam.c\n+++ b/drivers/media/platform/bcm2835/bcm2835-unicam.c\n@@ -782,12 +782,6 @@ static bool unicam_all_nodes_streaming(s\n \treturn ret;\n }\n \n-static bool unicam_all_nodes_disabled(struct unicam_device *dev)\n-{\n-\treturn !dev->node[IMAGE_PAD].streaming &&\n-\t       !dev->node[METADATA_PAD].streaming;\n-}\n-\n static void unicam_queue_event_sof(struct unicam_device *unicam)\n {\n \tstruct v4l2_event event = {\n@@ -815,15 +809,6 @@ static irqreturn_t unicam_isr(int irq, v\n \tu32 ista, sta;\n \tu64 ts;\n \n-\t/*\n-\t * Don't service interrupts if not streaming.\n-\t * Avoids issues if the VPU should enable the\n-\t * peripheral without the kernel knowing (that\n-\t * shouldn't happen, but causes issues if it does).\n-\t */\n-\tif (unicam_all_nodes_disabled(unicam))\n-\t\treturn IRQ_NONE;\n-\n \tsta = reg_read(unicam, UNICAM_STA);\n \t/* Write value back to clear the interrupts */\n \treg_write(unicam, UNICAM_STA, sta);\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0328-media-bcm2835-unicam-Fix-uninitialized-warning.patch",
    "content": "From 0524a77793eceb9d7c34d2833bdeec9f9cdb3825 Mon Sep 17 00:00:00 2001\nFrom: Jacko Dirks <jdirks.linuxdev@gmail.com>\nDate: Tue, 5 May 2020 14:33:31 +0200\nSubject: [PATCH] media: bcm2835: unicam: Fix uninitialized warning\n\nSigned-off-by: Jacko Dirks <jdirks.linuxdev@gmail.com>\n---\n drivers/media/platform/bcm2835/bcm2835-unicam.c | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/drivers/media/platform/bcm2835/bcm2835-unicam.c\n+++ b/drivers/media/platform/bcm2835/bcm2835-unicam.c\n@@ -1004,7 +1004,7 @@ const struct unicam_fmt *get_first_suppo\n \tstruct v4l2_subdev_mbus_code_enum mbus_code;\n \tconst struct unicam_fmt *fmt = NULL;\n \tunsigned int i;\n-\tint ret;\n+\tint ret = 0;\n \n \tfor (i = 0; ret != -EINVAL && ret != -ENOIOCTLCMD; ++i) {\n \t\tmemset(&mbus_code, 0, sizeof(mbus_code));\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0329-media-bcm2835-unicam-Fixup-review-comments-from-Hans.patch",
    "content": "From a658f8a9151c5852d590c998c2b806581509afbb Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Tue, 23 Jun 2020 15:14:05 +0100\nSubject: [PATCH] media: bcm2835-unicam: Fixup review comments from\n Hans.\n\nUpdates the driver based on the upstream review comments from\nHans Verkuil at https://patchwork.linuxtv.org/patch/63531/\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n drivers/media/platform/bcm2835/Kconfig        | 12 ++--\n .../media/platform/bcm2835/bcm2835-unicam.c   | 70 ++++++++-----------\n 2 files changed, 39 insertions(+), 43 deletions(-)\n\n--- a/drivers/media/platform/bcm2835/Kconfig\n+++ b/drivers/media/platform/bcm2835/Kconfig\n@@ -1,7 +1,7 @@\n # Broadcom VideoCore4 V4L2 camera support\n \n config VIDEO_BCM2835_UNICAM\n-\ttristate \"Broadcom BCM2835 Unicam video capture driver\"\n+\ttristate \"Broadcom BCM283x/BCM271x Unicam video capture driver\"\n \tdepends on VIDEO_V4L2\n \tdepends on ARCH_BCM2835 || COMPILE_TEST\n \tselect VIDEO_V4L2_SUBDEV_API\n@@ -9,9 +9,13 @@ config VIDEO_BCM2835_UNICAM\n \tselect VIDEOBUF2_DMA_CONTIG\n \tselect V4L2_FWNODE\n \thelp\n-\t  Say Y here to enable support for the BCM2835 CSI-2 receiver. This is a\n-\t  V4L2 driver that controls the CSI-2 receiver directly, independently\n-\t  from the VC4 firmware.\n+\t  Say Y here to enable support for the BCM283x/BCM271x CSI-2 receiver.\n+\t  This is a V4L2 driver that controls the CSI-2 receiver directly,\n+\t  independently from the VC4 firmware.\n+\t  This driver is mutually exclusive with the use of bcm2835-camera. The\n+\t  firmware will disable all access to the peripheral from within the\n+\t  firmware if it finds a DT node using it, and bcm2835-camera will\n+\t  therefore fail to probe.\n \n \t  To compile this driver as a module, choose M here. The module will be\n \t  called bcm2835-unicam.\n--- a/drivers/media/platform/bcm2835/bcm2835-unicam.c\n+++ b/drivers/media/platform/bcm2835/bcm2835-unicam.c\n@@ -1,6 +1,6 @@\n // SPDX-License-Identifier: GPL-2.0-only\n /*\n- * BCM2835 Unicam Capture Driver\n+ * BCM283x / BCM271x Unicam Capture Driver\n  *\n  * Copyright (C) 2017-2020 - Raspberry Pi (Trading) Ltd.\n  *\n@@ -571,9 +571,8 @@ static const struct unicam_fmt *find_for\n \treturn NULL;\n }\n \n-static inline unsigned int bytes_per_line(u32 width,\n-\t\t\t\t\t  const struct unicam_fmt *fmt,\n-\t\t\t\t\t  u32 v4l2_fourcc)\n+static unsigned int bytes_per_line(u32 width, const struct unicam_fmt *fmt,\n+\t\t\t\t   u32 v4l2_fourcc)\n {\n \tif (v4l2_fourcc == fmt->repacked_fourcc)\n \t\t/* Repacking always goes to 16bpp */\n@@ -718,7 +717,7 @@ static void unicam_wr_dma_addr(struct un\n \t}\n }\n \n-static inline unsigned int unicam_get_lines_done(struct unicam_device *dev)\n+static unsigned int unicam_get_lines_done(struct unicam_device *dev)\n {\n \tdma_addr_t start_addr, cur_addr;\n \tunsigned int stride = dev->node[IMAGE_PAD].v_fmt.fmt.pix.bytesperline;\n@@ -732,7 +731,7 @@ static inline unsigned int unicam_get_li\n \treturn (unsigned int)(cur_addr - start_addr) / stride;\n }\n \n-static inline void unicam_schedule_next_buffer(struct unicam_node *node)\n+static void unicam_schedule_next_buffer(struct unicam_node *node)\n {\n \tstruct unicam_device *dev = node->dev;\n \tstruct unicam_buffer *buf;\n@@ -751,7 +750,7 @@ static inline void unicam_schedule_next_\n \tunicam_wr_dma_addr(dev, addr, size, node->pad_id);\n }\n \n-static inline void unicam_schedule_dummy_buffer(struct unicam_node *node)\n+static void unicam_schedule_dummy_buffer(struct unicam_node *node)\n {\n \tstruct unicam_device *dev = node->dev;\n \n@@ -763,8 +762,8 @@ static inline void unicam_schedule_dummy\n \tnode->next_frm = NULL;\n }\n \n-static inline void unicam_process_buffer_complete(struct unicam_node *node,\n-\t\t\t\t\t\t  unsigned int sequence)\n+static void unicam_process_buffer_complete(struct unicam_node *node,\n+\t\t\t\t\t   unsigned int sequence)\n {\n \tnode->cur_frm->vb.field = node->m_fmt.field;\n \tnode->cur_frm->vb.sequence = sequence;\n@@ -772,16 +771,6 @@ static inline void unicam_process_buffer\n \tvb2_buffer_done(&node->cur_frm->vb.vb2_buf, VB2_BUF_STATE_DONE);\n }\n \n-static bool unicam_all_nodes_streaming(struct unicam_device *dev)\n-{\n-\tbool ret;\n-\n-\tret = dev->node[IMAGE_PAD].open && dev->node[IMAGE_PAD].streaming;\n-\tret &= !dev->node[METADATA_PAD].open ||\n-\t       dev->node[METADATA_PAD].streaming;\n-\treturn ret;\n-}\n-\n static void unicam_queue_event_sof(struct unicam_device *unicam)\n {\n \tstruct v4l2_event event = {\n@@ -904,8 +893,8 @@ static int unicam_querycap(struct file *\n \tstruct unicam_node *node = video_drvdata(file);\n \tstruct unicam_device *dev = node->dev;\n \n-\tstrlcpy(cap->driver, UNICAM_MODULE_NAME, sizeof(cap->driver));\n-\tstrlcpy(cap->card, UNICAM_MODULE_NAME, sizeof(cap->card));\n+\tstrscpy(cap->driver, UNICAM_MODULE_NAME, sizeof(cap->driver));\n+\tstrscpy(cap->card, UNICAM_MODULE_NAME, sizeof(cap->card));\n \n \tsnprintf(cap->bus_info, sizeof(cap->bus_info),\n \t\t \"platform:%s\", dev_name(&dev->pdev->dev));\n@@ -998,8 +987,8 @@ static int unicam_g_fmt_vid_cap(struct f\n \treturn 0;\n }\n \n-static\n-const struct unicam_fmt *get_first_supported_format(struct unicam_device *dev)\n+static const struct unicam_fmt *\n+get_first_supported_format(struct unicam_device *dev)\n {\n \tstruct v4l2_subdev_mbus_code_enum mbus_code;\n \tconst struct unicam_fmt *fmt = NULL;\n@@ -1589,7 +1578,8 @@ static void unicam_disable(struct unicam\n \tclk_write(dev, 0);\n }\n \n-static void unicam_return_buffers(struct unicam_node *node)\n+static void unicam_return_buffers(struct unicam_node *node,\n+\t\t\t\t  enum vb2_buffer_state state)\n {\n \tstruct unicam_buffer *buf, *tmp;\n \tunsigned long flags;\n@@ -1597,15 +1587,15 @@ static void unicam_return_buffers(struct\n \tspin_lock_irqsave(&node->dma_queue_lock, flags);\n \tlist_for_each_entry_safe(buf, tmp, &node->dma_queue, list) {\n \t\tlist_del(&buf->list);\n-\t\tvb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);\n+\t\tvb2_buffer_done(&buf->vb.vb2_buf, state);\n \t}\n \n \tif (node->cur_frm)\n \t\tvb2_buffer_done(&node->cur_frm->vb.vb2_buf,\n-\t\t\t\tVB2_BUF_STATE_ERROR);\n+\t\t\t\tstate);\n \tif (node->next_frm && node->cur_frm != node->next_frm)\n \t\tvb2_buffer_done(&node->next_frm->vb.vb2_buf,\n-\t\t\t\tVB2_BUF_STATE_ERROR);\n+\t\t\t\tstate);\n \n \tnode->cur_frm = NULL;\n \tnode->next_frm = NULL;\n@@ -1622,7 +1612,13 @@ static int unicam_start_streaming(struct\n \tint ret;\n \n \tnode->streaming = true;\n-\tif (!unicam_all_nodes_streaming(dev)) {\n+\tif (!(dev->node[IMAGE_PAD].open && dev->node[IMAGE_PAD].streaming &&\n+\t      (!dev->node[METADATA_PAD].open ||\n+\t       dev->node[METADATA_PAD].streaming))) {\n+\t\t/*\n+\t\t * Metadata pad must be enabled before image pad if it is\n+\t\t * wanted.\n+\t\t */\n \t\tunicam_dbg(3, dev, \"Not all nodes are streaming yet.\");\n \t\treturn 0;\n \t}\n@@ -1726,7 +1722,7 @@ err_vpu_clock:\n err_pm_put:\n \tunicam_runtime_put(dev);\n err_streaming:\n-\tunicam_return_buffers(node);\n+\tunicam_return_buffers(node, VB2_BUF_STATE_QUEUED);\n \tnode->streaming = false;\n \n \treturn ret;\n@@ -1771,7 +1767,7 @@ static void unicam_stop_streaming(struct\n \t}\n \n \t/* Clear all queued buffers for the node */\n-\tunicam_return_buffers(node);\n+\tunicam_return_buffers(node, VB2_BUF_STATE_ERROR);\n }\n \n static int unicam_enum_input(struct file *file, void *priv,\n@@ -1789,14 +1785,13 @@ static int unicam_enum_input(struct file\n \t\tinp->std = 0;\n \t} else if (v4l2_subdev_has_op(dev->sensor, video, s_std)) {\n \t\tinp->capabilities = V4L2_IN_CAP_STD;\n-\t\tif (v4l2_subdev_call(dev->sensor, video, g_tvnorms, &inp->std)\n-\t\t\t\t\t< 0)\n+\t\tif (v4l2_subdev_call(dev->sensor, video, g_tvnorms, &inp->std) < 0)\n \t\t\tinp->std = V4L2_STD_ALL;\n \t} else {\n \t\tinp->capabilities = 0;\n \t\tinp->std = 0;\n \t}\n-\tsprintf(inp->name, \"Camera 0\");\n+\tsnprintf(inp->name, sizeof(inp->name), \"Camera 0\");\n \treturn 0;\n }\n \n@@ -2025,6 +2020,9 @@ static int unicam_s_dv_timings(struct fi\n \tret = v4l2_subdev_call(dev->sensor, video, g_dv_timings,\n \t\t\t       &current_timings);\n \n+\tif (ret < 0)\n+\t\treturn ret;\n+\n \tif (v4l2_match_dv_timings(timings, &current_timings, 0, false))\n \t\treturn 0;\n \n@@ -2455,12 +2453,6 @@ static int register_node(struct unicam_d\n \t\tunicam_err(unicam, \"Unable to allocate dummy buffer.\\n\");\n \t\treturn -ENOMEM;\n \t}\n-\n-\tif (pad_id == METADATA_PAD) {\n-\t\tv4l2_disable_ioctl(vdev, VIDIOC_DQEVENT);\n-\t\tv4l2_disable_ioctl(vdev, VIDIOC_SUBSCRIBE_EVENT);\n-\t\tv4l2_disable_ioctl(vdev, VIDIOC_UNSUBSCRIBE_EVENT);\n-\t}\n \tif (pad_id == METADATA_PAD ||\n \t    !v4l2_subdev_has_op(unicam->sensor, video, s_std)) {\n \t\tv4l2_disable_ioctl(&node->video_dev, VIDIOC_S_STD);\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0330-media-bcm2835-unicam-Retain-packing-information-on-G.patch",
    "content": "From bbdb89fbe61de5bacbb44ab919548fb84f1426d2 Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Tue, 19 May 2020 11:46:47 +0100\nSubject: [PATCH] media: bcm2835-unicam: Retain packing information on\n G_FMT\n\nThe change to retrieve the pixel format always on g_fmt didn't\ncheck whether the native or unpacked version of the format\nhad been requested, and always returned the packed one.\nCorrect this so that the packing setting is retained whereever\npossible.\n\nFixes \"9d59e89 media: bcm2835-unicam: Re-fetch mbus code from subdev\non a g_fmt call\"\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n .../media/platform/bcm2835/bcm2835-unicam.c   | 19 +++++++++++++++++--\n 1 file changed, 17 insertions(+), 2 deletions(-)\n\n--- a/drivers/media/platform/bcm2835/bcm2835-unicam.c\n+++ b/drivers/media/platform/bcm2835/bcm2835-unicam.c\n@@ -980,8 +980,23 @@ static int unicam_g_fmt_vid_cap(struct f\n \tif (!fmt)\n \t\treturn -EINVAL;\n \n-\tnode->fmt = fmt;\n-\tnode->v_fmt.fmt.pix.pixelformat = fmt->fourcc;\n+\tif (node->fmt != fmt) {\n+\t\t/*\n+\t\t * The sensor format has changed so the pixelformat needs to\n+\t\t * be updated. Try and retain the packed/unpacked choice if\n+\t\t * at all possible.\n+\t\t */\n+\t\tif (node->fmt->repacked_fourcc ==\n+\t\t\t\t\t\tnode->v_fmt.fmt.pix.pixelformat)\n+\t\t\t/* Using the repacked format */\n+\t\t\tnode->v_fmt.fmt.pix.pixelformat = fmt->repacked_fourcc;\n+\t\telse\n+\t\t\t/* Using the native format */\n+\t\t\tnode->v_fmt.fmt.pix.pixelformat = fmt->fourcc;\n+\n+\t\tnode->fmt = fmt;\n+\t}\n+\n \t*f = node->v_fmt;\n \n \treturn 0;\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0331-media-bcm2835-unicam-change-minimum-number-of-vb2_qu.patch",
    "content": "From a450dcfff0fb6882228bef9242a0c1afcef6337a Mon Sep 17 00:00:00 2001\nFrom: David Plowman <david.plowman@raspberrypi.com>\nDate: Thu, 28 May 2020 11:09:48 +0100\nSubject: [PATCH] media: bcm2835-unicam: change minimum number of\n vb2_queue buffers to 1\n\nSince the unicam driver was modified to write to a dummy buffer when no\nuser-supplied buffer is available, it can now write to and return a\nbuffer even when there's only a single one. Enable this by changing the\nmin_buffers_needed in the vb2_queue; it will be useful for enabling\nstill captures without allocating more memory than absolutely necessary.\n\nSigned-off-by: David Plowman <david.plowman@raspberrypi.com>\n---\n drivers/media/platform/bcm2835/bcm2835-unicam.c | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/drivers/media/platform/bcm2835/bcm2835-unicam.c\n+++ b/drivers/media/platform/bcm2835/bcm2835-unicam.c\n@@ -2428,7 +2428,7 @@ static int register_node(struct unicam_d\n \tq->buf_struct_size = sizeof(struct unicam_buffer);\n \tq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;\n \tq->lock = &node->lock;\n-\tq->min_buffers_needed = 2;\n+\tq->min_buffers_needed = 1;\n \tq->dev = &unicam->pdev->dev;\n \n \tret = vb2_queue_init(q);\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0332-staging-fbtft-Add-support-for-display-variants.patch",
    "content": "From 809abb2cd0f810ee0a94add2e5a038c78825915d Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.com>\nDate: Tue, 1 Sep 2020 18:15:27 +0100\nSubject: [PATCH] staging/fbtft: Add support for display variants\n\nDisplay variants are intended as a replacement for the now-deleted\nfbtft_device drivers. Drivers can register additional compatible\nstrings with a custom callback that can make the required changes\nto the fbtft_display structure.\n\nStart the ball rolling by adding adafruit18, adafruit18_green and\nsainsmart18 displays.\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.com>\n---\n drivers/staging/fbtft/fb_st7735r.c | 38 +++++++++++++++++++++++++++++-\n drivers/staging/fbtft/fbtft-core.c | 16 ++++++++++++-\n drivers/staging/fbtft/fbtft.h      | 28 +++++++++++++++++-----\n 3 files changed, 74 insertions(+), 8 deletions(-)\n\n--- a/drivers/staging/fbtft/fb_st7735r.c\n+++ b/drivers/staging/fbtft/fb_st7735r.c\n@@ -16,6 +16,10 @@\n #define DEFAULT_GAMMA   \"0F 1A 0F 18 2F 28 20 22 1F 1B 23 37 00 07 02 10\\n\" \\\n \t\t\t\"0F 1B 0F 17 33 2C 29 2E 30 30 39 3F 00 07 03 10\"\n \n+#define ADAFRUIT18_GAMMA \\\n+\t\t\t\"02 1c 07 12 37 32 29 2d 29 25 2B 39 00 01 03 10\\n\" \\\n+\t\t\t\"03 1d 07 06 2E 2C 29 2D 2E 2E 37 3F 00 00 02 10\"\n+\n static const s16 default_init_sequence[] = {\n \t-1, MIPI_DCS_SOFT_RESET,\n \t-2, 150,                               /* delay */\n@@ -94,6 +98,14 @@ static void set_addr_win(struct fbtft_pa\n \twrite_reg(par, MIPI_DCS_WRITE_MEMORY_START);\n }\n \n+static void adafruit18_green_tab_set_addr_win(struct fbtft_par *par,\n+\t\t\t\t\t      int xs, int ys, int xe, int ye)\n+{\n+\twrite_reg(par, 0x2A, 0, xs + 2, 0, xe + 2);\n+\twrite_reg(par, 0x2B, 0, ys + 1, 0, ye + 1);\n+\twrite_reg(par, 0x2C);\n+}\n+\n #define MY BIT(7)\n #define MX BIT(6)\n #define MV BIT(5)\n@@ -174,12 +186,36 @@ static struct fbtft_display display = {\n \t},\n };\n \n-FBTFT_REGISTER_DRIVER(DRVNAME, \"sitronix,st7735r\", &display);\n+int variant_adafruit18(struct fbtft_display *display)\n+{\n+\tdisplay->gamma = ADAFRUIT18_GAMMA;\n+\treturn 0;\n+}\n+\n+int variant_adafruit18_green(struct fbtft_display *display)\n+{\n+\tdisplay->gamma = ADAFRUIT18_GAMMA;\n+\tdisplay->fbtftops.set_addr_win = adafruit18_green_tab_set_addr_win;\n+\treturn 0;\n+}\n+\n+FBTFT_REGISTER_DRIVER_START(&display)\n+FBTFT_COMPATIBLE(\"sitronix,st7735r\")\n+FBTFT_COMPATIBLE(\"fbtft,sainsmart18\")\n+FBTFT_VARIANT_COMPATIBLE(\"fbtft,adafruit18\", variant_adafruit18)\n+FBTFT_VARIANT_COMPATIBLE(\"fbtft,adafruit18_green\", variant_adafruit18_green)\n+FBTFT_REGISTER_DRIVER_END(DRVNAME, &display);\n \n MODULE_ALIAS(\"spi:\" DRVNAME);\n MODULE_ALIAS(\"platform:\" DRVNAME);\n MODULE_ALIAS(\"spi:st7735r\");\n MODULE_ALIAS(\"platform:st7735r\");\n+MODULE_ALIAS(\"spi:sainsmart18\");\n+MODULE_ALIAS(\"platform:sainsmart\");\n+MODULE_ALIAS(\"spi:adafruit18\");\n+MODULE_ALIAS(\"platform:adafruit18\");\n+MODULE_ALIAS(\"spi:adafruit18_green\");\n+MODULE_ALIAS(\"platform:adafruit18_green\");\n \n MODULE_DESCRIPTION(\"FB driver for the ST7735R LCD Controller\");\n MODULE_AUTHOR(\"Noralf Tronnes\");\n--- a/drivers/staging/fbtft/fbtft-core.c\n+++ b/drivers/staging/fbtft/fbtft-core.c\n@@ -24,6 +24,8 @@\n #include <linux/platform_device.h>\n #include <linux/property.h>\n #include <linux/spinlock.h>\n+#include <linux/of.h>\n+#include <linux/of_device.h>\n \n #include <video/mipi_display.h>\n \n@@ -1187,6 +1189,7 @@ static struct fbtft_platform_data *fbtft\n  * @display: Display properties\n  * @sdev: SPI device\n  * @pdev: Platform device\n+ * @dt_ids: Compatible string table\n  *\n  * Allocates, initializes and registers a framebuffer\n  *\n@@ -1196,12 +1199,15 @@ static struct fbtft_platform_data *fbtft\n  */\n int fbtft_probe_common(struct fbtft_display *display,\n \t\t       struct spi_device *sdev,\n-\t\t       struct platform_device *pdev)\n+\t\t       struct platform_device *pdev,\n+\t\t       const struct of_device_id *dt_ids)\n {\n \tstruct device *dev;\n \tstruct fb_info *info;\n \tstruct fbtft_par *par;\n \tstruct fbtft_platform_data *pdata;\n+\tconst struct of_device_id *match;\n+\tint (*variant)(struct fbtft_display *);\n \tint ret;\n \n \tif (sdev)\n@@ -1217,6 +1223,14 @@ int fbtft_probe_common(struct fbtft_disp\n \t\tpdata = fbtft_properties_read(dev);\n \t\tif (IS_ERR(pdata))\n \t\t\treturn PTR_ERR(pdata);\n+\t\tmatch = of_match_device(dt_ids, dev);\n+\t\tif (match && match->data) {\n+\t\t\t/* apply the variant */\n+\t\t\tvariant = match->data;\n+\t\t\tret = (*variant)(display);\n+\t\t\tif (ret)\n+\t\t\t\treturn ret;\n+\t\t}\n \t}\n \n \tinfo = fbtft_framebuffer_alloc(display, dev, pdata);\n--- a/drivers/staging/fbtft/fbtft.h\n+++ b/drivers/staging/fbtft/fbtft.h\n@@ -251,7 +251,8 @@ void fbtft_register_backlight(struct fbt\n void fbtft_unregister_backlight(struct fbtft_par *par);\n int fbtft_init_display(struct fbtft_par *par);\n int fbtft_probe_common(struct fbtft_display *display, struct spi_device *sdev,\n-\t\t       struct platform_device *pdev);\n+\t\t       struct platform_device *pdev,\n+\t\t       const struct of_device_id *dt_ids);\n int fbtft_remove_common(struct device *dev, struct fb_info *info);\n \n /* fbtft-io.c */\n@@ -272,11 +273,13 @@ void fbtft_write_reg8_bus9(struct fbtft_\n void fbtft_write_reg16_bus8(struct fbtft_par *par, int len, ...);\n void fbtft_write_reg16_bus16(struct fbtft_par *par, int len, ...);\n \n-#define FBTFT_REGISTER_DRIVER(_name, _compatible, _display)                \\\n+#define FBTFT_REGISTER_DRIVER_START(_display)                              \\\n+\t\t\t\t\t\t\t\t\t   \\\n+static const struct of_device_id dt_ids[];                                 \\\n \t\t\t\t\t\t\t\t\t   \\\n static int fbtft_driver_probe_spi(struct spi_device *spi)                  \\\n {                                                                          \\\n-\treturn fbtft_probe_common(_display, spi, NULL);                    \\\n+\treturn fbtft_probe_common(_display, spi, NULL, dt_ids);\t           \\\n }                                                                          \\\n \t\t\t\t\t\t\t\t\t   \\\n static int fbtft_driver_remove_spi(struct spi_device *spi)                 \\\n@@ -288,7 +291,7 @@ static int fbtft_driver_remove_spi(struc\n \t\t\t\t\t\t\t\t\t   \\\n static int fbtft_driver_probe_pdev(struct platform_device *pdev)           \\\n {                                                                          \\\n-\treturn fbtft_probe_common(_display, NULL, pdev);                   \\\n+\treturn fbtft_probe_common(_display, NULL, pdev, dt_ids);           \\\n }                                                                          \\\n \t\t\t\t\t\t\t\t\t   \\\n static int fbtft_driver_remove_pdev(struct platform_device *pdev)          \\\n@@ -298,8 +301,16 @@ static int fbtft_driver_remove_pdev(stru\n \treturn fbtft_remove_common(&pdev->dev, info);                      \\\n }                                                                          \\\n \t\t\t\t\t\t\t\t\t   \\\n-static const struct of_device_id dt_ids[] = {                              \\\n-\t{ .compatible = _compatible },                                     \\\n+static const struct of_device_id dt_ids[] = {\n+\n+#define FBTFT_COMPATIBLE(_compatible)                                      \\\n+\t{ .compatible = _compatible },\n+\n+#define FBTFT_VARIANT_COMPATIBLE(_compatible, _variant)                    \\\n+\t{ .compatible = _compatible, .data = _variant },\n+\n+#define FBTFT_REGISTER_DRIVER_END(_name, _display)                         \\\n+\t\t\t\t\t\t\t\t\t   \\\n \t{},                                                                \\\n };                                                                         \\\n \t\t\t\t\t\t\t\t\t   \\\n@@ -347,6 +358,11 @@ static void __exit fbtft_driver_module_e\n module_init(fbtft_driver_module_init);                                     \\\n module_exit(fbtft_driver_module_exit);\n \n+#define FBTFT_REGISTER_DRIVER(_name, _compatible, _display)                \\\n+\tFBTFT_REGISTER_DRIVER_START(_display)                              \\\n+\tFBTFT_COMPATIBLE(_compatible)                                      \\\n+\tFBTFT_REGISTER_DRIVER_END(_name, _display)\n+\n /* Debug macros */\n \n /* shorthand debug levels */\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0333-rpivid_h265-Fix-width-height-typo.patch",
    "content": "From 283636090484d4047e38a870194c212aeb197ebd Mon Sep 17 00:00:00 2001\nFrom: popcornmix <popcornmix@gmail.com>\nDate: Mon, 21 Sep 2020 14:02:44 +0100\nSubject: [PATCH] rpivid_h265: Fix width/height typo\n\nSigned-off-by: popcornmix <popcornmix@gmail.com>\n---\n drivers/staging/media/rpivid/rpivid_h265.c | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/drivers/staging/media/rpivid/rpivid_h265.c\n+++ b/drivers/staging/media/rpivid/rpivid_h265.c\n@@ -2178,7 +2178,7 @@ static int rpivid_h265_start(struct rpiv\n \tif (w > 4096)\n \t\tw = 4096;\n \tif (h == 0)\n-\t\tw = 1088;\n+\t\th = 1088;\n \tif (h > 4096)\n \t\th = 4096;\n \twxh = w * h;\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0334-net-bcmgenet-Reset-RBUF-on-first-open.patch",
    "content": "From eccfde35476213d30a67dedb63f007e7ae8da78c Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.com>\nDate: Fri, 25 Sep 2020 15:07:23 +0100\nSubject: [PATCH] net: bcmgenet: Reset RBUF on first open\n\nIf the RBUF logic is not reset when the kernel starts then there\nmay be some data left over from any network boot loader. If the\n64-byte packet headers are enabled then this can be fatal.\n\nExtend bcmgenet_dma_disable to do perform the reset, but not when\ncalled from bcmgenet_resume in order to preserve a wake packet.\n\nN.B. This different handling of resume is just based on a hunch -\nwhy else wouldn't one reset the RBUF as well as the TBUF? If this\nisn't the case then it's easy to change the patch to make the RBUF\nreset unconditional.\n\nSee: https://github.com/raspberrypi/linux/issues/3850\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.com>\n---\n drivers/net/ethernet/broadcom/genet/bcmgenet.c | 16 ++++++++++++----\n 1 file changed, 12 insertions(+), 4 deletions(-)\n\n--- a/drivers/net/ethernet/broadcom/genet/bcmgenet.c\n+++ b/drivers/net/ethernet/broadcom/genet/bcmgenet.c\n@@ -3246,7 +3246,7 @@ static void bcmgenet_get_hw_addr(struct\n }\n \n /* Returns a reusable dma control register value */\n-static u32 bcmgenet_dma_disable(struct bcmgenet_priv *priv)\n+static u32 bcmgenet_dma_disable(struct bcmgenet_priv *priv, bool flush_rx)\n {\n \tunsigned int i;\n \tu32 reg;\n@@ -3271,6 +3271,14 @@ static u32 bcmgenet_dma_disable(struct b\n \tudelay(10);\n \tbcmgenet_umac_writel(priv, 0, UMAC_TX_FLUSH);\n \n+\tif (flush_rx) {\n+\t    reg = bcmgenet_rbuf_ctrl_get(priv);\n+\t    bcmgenet_rbuf_ctrl_set(priv, reg | BIT(0));\n+\t    udelay(10);\n+\t    bcmgenet_rbuf_ctrl_set(priv, reg);\n+\t    udelay(10);\n+\t}\n+\n \treturn dma_ctrl;\n }\n \n@@ -3334,8 +3342,8 @@ static int bcmgenet_open(struct net_devi\n \n \tbcmgenet_set_hw_addr(priv, dev->dev_addr);\n \n-\t/* Disable RX/TX DMA and flush TX queues */\n-\tdma_ctrl = bcmgenet_dma_disable(priv);\n+\t/* Disable RX/TX DMA and flush TX and RX queues */\n+\tdma_ctrl = bcmgenet_dma_disable(priv, true);\n \n \t/* Reinitialize TDMA and RDMA and SW housekeeping */\n \tret = bcmgenet_init_dma(priv);\n@@ -4191,7 +4199,7 @@ static int bcmgenet_resume(struct device\n \t\t\tbcmgenet_hfb_create_rxnfc_filter(priv, rule);\n \n \t/* Disable RX/TX DMA and flush TX queues */\n-\tdma_ctrl = bcmgenet_dma_disable(priv);\n+\tdma_ctrl = bcmgenet_dma_disable(priv, false);\n \n \t/* Reinitialize TDMA and RDMA and SW housekeeping */\n \tret = bcmgenet_init_dma(priv);\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0335-char-Add-broadcom-char-drivers-back-to-build-files.patch",
    "content": "From a0dab30b7061e7b56a5bd74f03bafb8e97d52135 Mon Sep 17 00:00:00 2001\nFrom: popcornmix <popcornmix@gmail.com>\nDate: Mon, 28 Sep 2020 20:23:30 +0100\nSubject: [PATCH] char: Add broadcom char drivers back to build files\n\nSee: https://github.com/raspberrypi/linux/issues/3875\nSigned-off-by: popcornmix <popcornmix@gmail.com>\n---\n drivers/char/Kconfig  | 2 ++\n drivers/char/Makefile | 1 +\n 2 files changed, 3 insertions(+)\n\n--- a/drivers/char/Kconfig\n+++ b/drivers/char/Kconfig\n@@ -5,6 +5,8 @@\n \n menu \"Character devices\"\n \n+source \"drivers/char/broadcom/Kconfig\"\n+\n source \"drivers/tty/Kconfig\"\n \n config TTY_PRINTK\n--- a/drivers/char/Makefile\n+++ b/drivers/char/Makefile\n@@ -47,3 +47,4 @@ obj-$(CONFIG_PS3_FLASH)\t\t+= ps3flash.o\n obj-$(CONFIG_XILLYBUS)\t\t+= xillybus/\n obj-$(CONFIG_POWERNV_OP_PANEL)\t+= powernv-op-panel.o\n obj-$(CONFIG_ADI)\t\t+= adi.o\n+obj-$(CONFIG_BRCM_CHAR_DRIVERS) += broadcom/\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0336-dwc_otg-initialise-sched_frame-for-periodic-QHs-that.patch",
    "content": "From bdc90a7b7ee57434a37adcfcb07f98309cb3426b Mon Sep 17 00:00:00 2001\nFrom: Jonathan Bell <jonathan@raspberrypi.org>\nDate: Wed, 7 Oct 2020 15:09:29 +0100\nSubject: [PATCH] dwc_otg: initialise sched_frame for periodic QHs that\n were parked\n\nIf a periodic QH has no remaining QTDs, then it is removed from all\nperiodic schedules. When re-adding, initialise the sched_frame and\nstart_split_frame from the current value of the frame counter.\n\nSee https://bugs.launchpad.net/raspbian/+bug/1819560\nand\n https://github.com/raspberrypi/linux/issues/3883\n\nSigned-off-by: Jonathan Bell <jonathan@raspberrypi.com>\n---\n drivers/usb/host/dwc_otg/dwc_otg_hcd_queue.c | 4 ++++\n 1 file changed, 4 insertions(+)\n\n--- a/drivers/usb/host/dwc_otg/dwc_otg_hcd_queue.c\n+++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd_queue.c\n@@ -689,7 +689,11 @@ int dwc_otg_hcd_qh_add(dwc_otg_hcd_t * h\n \t\t\t\t     &qh->qh_list_entry);\n \t\t//hcd->fiq_state->kick_np_queues = 1;\n \t} else {\n+\t\t/* If the QH wasn't in a schedule, then sched_frame is stale. */\n+\t\tqh->sched_frame = dwc_frame_num_inc(dwc_otg_hcd_get_frame_number(hcd),\n+\t\t\t\t\t\t\tSCHEDULE_SLOP);\n \t\tstatus = schedule_periodic(hcd, qh);\n+\t\tqh->start_split_frame = qh->sched_frame;\n \t\tif ( !hcd->periodic_qh_count ) {\n \t\t\tintr_mask.b.sofintr = 1;\n \t\t\tif (fiq_enable) {\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0337-staging-bcm2835-camera-Replace-deprecated-V4L2_PIX_F.patch",
    "content": "From 5ce4d307cbdf38c5c5e9abc6397ab72336cc2ca3 Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Thu, 8 Oct 2020 15:35:14 +0100\nSubject: [PATCH] staging: bcm2835-camera: Replace deprecated\n V4L2_PIX_FMT_BGR32\n\nV4L2_PIX_FMT_BGR32 is deprecated as it is ambiguous over where\nthe alpha byte is. Cheese/GStreamer appear to get it wrong for\none, and qv4l2 gets red and blue swapped.\n\nSwap to the newer V4L2_PIX_FMT_BGRX32 format.\n\nhttps://www.raspberrypi.org/forums/viewtopic.php?f=38&t=267736&p=1738912\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n drivers/staging/vc04_services/bcm2835-camera/bcm2835-camera.c | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/drivers/staging/vc04_services/bcm2835-camera/bcm2835-camera.c\n+++ b/drivers/staging/vc04_services/bcm2835-camera/bcm2835-camera.c\n@@ -178,7 +178,7 @@ static struct mmal_fmt formats[] = {\n \t\t.ybbp = 1,\n \t\t.remove_padding = 1,\n \t}, {\n-\t\t.fourcc = V4L2_PIX_FMT_BGR32,\n+\t\t.fourcc = V4L2_PIX_FMT_BGRX32,\n \t\t.mmal = MMAL_ENCODING_BGRA,\n \t\t.depth = 32,\n \t\t.mmal_component = COMP_CAMERA,\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0338-staging-vc04_services-Add-new-vc-sm-cma-driver.patch",
    "content": "From 253337e15008d614c846d07a44493008a7b803b5 Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Thu, 8 Oct 2020 18:49:52 +0100\nSubject: [PATCH] staging: vc04_services: Add new vc-sm-cma driver\n\nAdd Broadcom VideoCore Shared Memory support.\n\nThis new driver allows contiguous memory blocks to be imported\ninto the VideoCore VPU memory map, and manages the lifetime of\nthose objects, only releasing the source dmabuf once the VPU has\nconfirmed it has finished with it.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n drivers/staging/vc04_services/Kconfig         |    2 +\n drivers/staging/vc04_services/Makefile        |    1 +\n .../include/linux/broadcom/vc_sm_cma_ioctl.h  |  114 ++\n .../staging/vc04_services/vc-sm-cma/Kconfig   |   10 +\n .../staging/vc04_services/vc-sm-cma/Makefile  |   12 +\n drivers/staging/vc04_services/vc-sm-cma/TODO  |    1 +\n .../staging/vc04_services/vc-sm-cma/vc_sm.c   | 1725 +++++++++++++++++\n .../staging/vc04_services/vc-sm-cma/vc_sm.h   |   84 +\n .../vc04_services/vc-sm-cma/vc_sm_cma_vchi.c  |  503 +++++\n .../vc04_services/vc-sm-cma/vc_sm_cma_vchi.h  |   63 +\n .../vc04_services/vc-sm-cma/vc_sm_defs.h      |  297 +++\n .../vc04_services/vc-sm-cma/vc_sm_knl.h       |   28 +\n 12 files changed, 2840 insertions(+)\n create mode 100644 drivers/staging/vc04_services/include/linux/broadcom/vc_sm_cma_ioctl.h\n create mode 100644 drivers/staging/vc04_services/vc-sm-cma/Kconfig\n create mode 100644 drivers/staging/vc04_services/vc-sm-cma/Makefile\n create mode 100644 drivers/staging/vc04_services/vc-sm-cma/TODO\n create mode 100644 drivers/staging/vc04_services/vc-sm-cma/vc_sm.c\n create mode 100644 drivers/staging/vc04_services/vc-sm-cma/vc_sm.h\n create mode 100644 drivers/staging/vc04_services/vc-sm-cma/vc_sm_cma_vchi.c\n create mode 100644 drivers/staging/vc04_services/vc-sm-cma/vc_sm_cma_vchi.h\n create mode 100644 drivers/staging/vc04_services/vc-sm-cma/vc_sm_defs.h\n create mode 100644 drivers/staging/vc04_services/vc-sm-cma/vc_sm_knl.h\n\n--- a/drivers/staging/vc04_services/Kconfig\n+++ b/drivers/staging/vc04_services/Kconfig\n@@ -23,6 +23,8 @@ source \"drivers/staging/vc04_services/bc\n \n source \"drivers/staging/vc04_services/bcm2835-camera/Kconfig\"\n \n+source \"drivers/staging/vc04_services/vc-sm-cma/Kconfig\"\n+\n source \"drivers/staging/vc04_services/vchiq-mmal/Kconfig\"\n \n endif\n--- a/drivers/staging/vc04_services/Makefile\n+++ b/drivers/staging/vc04_services/Makefile\n@@ -11,6 +11,7 @@ vchiq-objs := \\\n obj-$(CONFIG_SND_BCM2835)\t\t+= bcm2835-audio/\n obj-$(CONFIG_VIDEO_BCM2835)\t\t+= bcm2835-camera/\n obj-$(CONFIG_BCM2835_VCHIQ_MMAL)\t+= vchiq-mmal/\n+obj-$(CONFIG_BCM_VC_SM_CMA)\t\t+= vc-sm-cma/\n \n ccflags-y += -I $(srctree)/$(src)/include  -D__VCCOREVER__=0x04000000\n \n--- /dev/null\n+++ b/drivers/staging/vc04_services/include/linux/broadcom/vc_sm_cma_ioctl.h\n@@ -0,0 +1,114 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+\n+/*\n+ * Copyright 2019 Raspberry Pi (Trading) Ltd.  All rights reserved.\n+ *\n+ * Based on vmcs_sm_ioctl.h Copyright Broadcom Corporation.\n+ */\n+\n+#ifndef __VC_SM_CMA_IOCTL_H\n+#define __VC_SM_CMA_IOCTL_H\n+\n+/* ---- Include Files ---------------------------------------------------- */\n+\n+#if defined(__KERNEL__)\n+#include <linux/types.h>\t/* Needed for standard types */\n+#else\n+#include <stdint.h>\n+#endif\n+\n+#include <linux/ioctl.h>\n+\n+/* ---- Constants and Types ---------------------------------------------- */\n+\n+#define VC_SM_CMA_RESOURCE_NAME               32\n+#define VC_SM_CMA_RESOURCE_NAME_DEFAULT       \"sm-host-resource\"\n+\n+/* Type define used to create unique IOCTL number */\n+#define VC_SM_CMA_MAGIC_TYPE                  'J'\n+\n+/* IOCTL commands on /dev/vc-sm-cma */\n+enum vc_sm_cma_cmd_e {\n+\tVC_SM_CMA_CMD_ALLOC = 0x5A,\t/* Start at 0x5A arbitrarily */\n+\n+\tVC_SM_CMA_CMD_IMPORT_DMABUF,\n+\n+\tVC_SM_CMA_CMD_CLEAN_INVALID2,\n+\n+\tVC_SM_CMA_CMD_LAST\t/* Do not delete */\n+};\n+\n+/* Cache type supported, conveniently matches the user space definition in\n+ * user-vcsm.h.\n+ */\n+enum vc_sm_cma_cache_e {\n+\tVC_SM_CMA_CACHE_NONE,\n+\tVC_SM_CMA_CACHE_HOST,\n+\tVC_SM_CMA_CACHE_VC,\n+\tVC_SM_CMA_CACHE_BOTH,\n+};\n+\n+/* IOCTL Data structures */\n+struct vc_sm_cma_ioctl_alloc {\n+\t/* user -> kernel */\n+\t__u32 size;\n+\t__u32 num;\n+\t__u32 cached;\t\t/* enum vc_sm_cma_cache_e */\n+\t__u32 pad;\n+\t__u8 name[VC_SM_CMA_RESOURCE_NAME];\n+\n+\t/* kernel -> user */\n+\t__s32 handle;\n+\t__u32 vc_handle;\n+\t__u64 dma_addr;\n+};\n+\n+struct vc_sm_cma_ioctl_import_dmabuf {\n+\t/* user -> kernel */\n+\t__s32 dmabuf_fd;\n+\t__u32 cached;\t\t/* enum vc_sm_cma_cache_e */\n+\t__u8 name[VC_SM_CMA_RESOURCE_NAME];\n+\n+\t/* kernel -> user */\n+\t__s32 handle;\n+\t__u32 vc_handle;\n+\t__u32 size;\n+\t__u32 pad;\n+\t__u64 dma_addr;\n+};\n+\n+/*\n+ * Cache functions to be set to struct vc_sm_cma_ioctl_clean_invalid2\n+ * invalidate_mode.\n+ */\n+#define VC_SM_CACHE_OP_NOP       0x00\n+#define VC_SM_CACHE_OP_INV       0x01\n+#define VC_SM_CACHE_OP_CLEAN     0x02\n+#define VC_SM_CACHE_OP_FLUSH     0x03\n+\n+struct vc_sm_cma_ioctl_clean_invalid2 {\n+\t__u32 op_count;\n+\t__u32 pad;\n+\tstruct vc_sm_cma_ioctl_clean_invalid_block {\n+\t\t__u32 invalidate_mode;\n+\t\t__u32 block_count;\n+\t\tvoid *  __user start_address;\n+\t\t__u32 block_size;\n+\t\t__u32 inter_block_stride;\n+\t} s[0];\n+};\n+\n+/* IOCTL numbers */\n+#define VC_SM_CMA_IOCTL_MEM_ALLOC\\\n+\t_IOR(VC_SM_CMA_MAGIC_TYPE, VC_SM_CMA_CMD_ALLOC,\\\n+\t struct vc_sm_cma_ioctl_alloc)\n+\n+#define VC_SM_CMA_IOCTL_MEM_IMPORT_DMABUF\\\n+\t_IOR(VC_SM_CMA_MAGIC_TYPE, VC_SM_CMA_CMD_IMPORT_DMABUF,\\\n+\t struct vc_sm_cma_ioctl_import_dmabuf)\n+\n+#define VC_SM_CMA_IOCTL_MEM_CLEAN_INVALID2\\\n+\t_IOR(VC_SM_CMA_MAGIC_TYPE, VC_SM_CMA_CMD_CLEAN_INVALID2,\\\n+\t struct vc_sm_cma_ioctl_clean_invalid2)\n+\n+#endif /* __VC_SM_CMA_IOCTL_H */\n--- /dev/null\n+++ b/drivers/staging/vc04_services/vc-sm-cma/Kconfig\n@@ -0,0 +1,10 @@\n+config BCM_VC_SM_CMA\n+\ttristate \"VideoCore Shared Memory (CMA) driver\"\n+\tselect BCM2835_VCHIQ\n+\tselect RBTREE\n+\tselect DMA_SHARED_BUFFER\n+\thelp\n+\t  Say Y here to enable the shared memory interface that\n+\t  supports sharing dmabufs with VideoCore.\n+\t  This operates over the VCHIQ interface to a service\n+\t  running on VideoCore.\n--- /dev/null\n+++ b/drivers/staging/vc04_services/vc-sm-cma/Makefile\n@@ -0,0 +1,12 @@\n+ccflags-y += \\\n+\t-I$(srctree)/$(src)/../ \\\n+\t-I$(srctree)/$(src)/../interface/vchiq_arm\\\n+\t-I$(srctree)/$(src)/../include\n+\n+ccflags-y += \\\n+\t-D__VCCOREVER__=0\n+\n+vc-sm-cma-$(CONFIG_BCM_VC_SM_CMA) := \\\n+\tvc_sm.o vc_sm_cma_vchi.o\n+\n+obj-$(CONFIG_BCM_VC_SM_CMA) += vc-sm-cma.o\n--- /dev/null\n+++ b/drivers/staging/vc04_services/vc-sm-cma/TODO\n@@ -0,0 +1 @@\n+No currently outstanding tasks except some clean-up.\n--- /dev/null\n+++ b/drivers/staging/vc04_services/vc-sm-cma/vc_sm.c\n@@ -0,0 +1,1725 @@\n+// SPDX-License-Identifier: GPL-2.0\n+/*\n+ * VideoCore Shared Memory driver using CMA.\n+ *\n+ * Copyright: 2018, Raspberry Pi (Trading) Ltd\n+ * Dave Stevenson <dave.stevenson@raspberrypi.org>\n+ *\n+ * Based on vmcs_sm driver from Broadcom Corporation for some API,\n+ * and taking some code for buffer allocation and dmabuf handling from\n+ * videobuf2.\n+ *\n+ *\n+ * This driver has 3 main uses:\n+ * 1) Allocating buffers for the kernel or userspace that can be shared with the\n+ *    VPU.\n+ * 2) Importing dmabufs from elsewhere for sharing with the VPU.\n+ * 3) Allocating buffers for use by the VPU.\n+ *\n+ * In the first and second cases the native handle is a dmabuf. Releasing the\n+ * resource inherently comes from releasing the dmabuf, and this will trigger\n+ * unmapping on the VPU. The underlying allocation and our buffer structure are\n+ * retained until the VPU has confirmed that it has finished with it.\n+ *\n+ * For the VPU allocations the VPU is responsible for triggering the release,\n+ * and therefore the released message decrements the dma_buf refcount (with the\n+ * VPU mapping having already been marked as released).\n+ */\n+\n+/* ---- Include Files ----------------------------------------------------- */\n+#include <linux/cdev.h>\n+#include <linux/device.h>\n+#include <linux/debugfs.h>\n+#include <linux/dma-mapping.h>\n+#include <linux/dma-buf.h>\n+#include <linux/errno.h>\n+#include <linux/fs.h>\n+#include <linux/kernel.h>\n+#include <linux/list.h>\n+#include <linux/miscdevice.h>\n+#include <linux/module.h>\n+#include <linux/mm.h>\n+#include <linux/of_device.h>\n+#include <linux/platform_device.h>\n+#include <linux/proc_fs.h>\n+#include <linux/slab.h>\n+#include <linux/seq_file.h>\n+#include <linux/syscalls.h>\n+#include <linux/types.h>\n+#include <asm/cacheflush.h>\n+\n+#include \"vchiq_connected.h\"\n+#include \"vc_sm_cma_vchi.h\"\n+\n+#include \"vc_sm.h\"\n+#include \"vc_sm_knl.h\"\n+#include <linux/broadcom/vc_sm_cma_ioctl.h>\n+\n+/* ---- Private Constants and Types --------------------------------------- */\n+\n+#define DEVICE_NAME\t\t\"vcsm-cma\"\n+#define DEVICE_MINOR\t\t0\n+\n+#define VC_SM_RESOURCE_NAME_DEFAULT       \"sm-host-resource\"\n+\n+#define VC_SM_DIR_ROOT_NAME\t\"vcsm-cma\"\n+#define VC_SM_STATE\t\t\"state\"\n+\n+/* Private file data associated with each opened device. */\n+struct vc_sm_privdata_t {\n+\tpid_t pid;                      /* PID of creator. */\n+\n+\tint restart_sys;\t\t/* Tracks restart on interrupt. */\n+\tenum vc_sm_msg_type int_action;\t/* Interrupted action. */\n+\tu32 int_trans_id;\t\t/* Interrupted transaction. */\n+};\n+\n+typedef int (*VC_SM_SHOW) (struct seq_file *s, void *v);\n+struct sm_pde_t {\n+\tVC_SM_SHOW show;          /* Debug fs function hookup. */\n+\tstruct dentry *dir_entry; /* Debug fs directory entry. */\n+\tvoid *priv_data;          /* Private data */\n+};\n+\n+/* Global state information. */\n+struct sm_state_t {\n+\tstruct platform_device *pdev;\n+\n+\tstruct miscdevice misc_dev;\n+\n+\tstruct sm_instance *sm_handle;\t/* Handle for videocore service. */\n+\n+\tspinlock_t kernelid_map_lock;\t/* Spinlock protecting kernelid_map */\n+\tstruct idr kernelid_map;\n+\n+\tstruct mutex map_lock;          /* Global map lock. */\n+\tstruct list_head buffer_list;\t/* List of buffer. */\n+\n+\tstruct vc_sm_privdata_t *data_knl;  /* Kernel internal data tracking. */\n+\tstruct vc_sm_privdata_t *vpu_allocs; /* All allocations from the VPU */\n+\tstruct dentry *dir_root;\t/* Debug fs entries root. */\n+\tstruct sm_pde_t dir_state;\t/* Debug fs entries state sub-tree. */\n+\n+\tbool require_released_callback;\t/* VPU will send a released msg when it\n+\t\t\t\t\t * has finished with a resource.\n+\t\t\t\t\t */\n+\tu32 int_trans_id;\t\t/* Interrupted transaction. */\n+};\n+\n+struct vc_sm_dma_buf_attachment {\n+\tstruct device *dev;\n+\tstruct sg_table sg_table;\n+\tstruct list_head list;\n+\tenum dma_data_direction\tdma_dir;\n+};\n+\n+/* ---- Private Variables ----------------------------------------------- */\n+\n+static struct sm_state_t *sm_state;\n+static int sm_inited;\n+\n+/* ---- Private Function Prototypes -------------------------------------- */\n+\n+/* ---- Private Functions ------------------------------------------------ */\n+\n+static int get_kernel_id(struct vc_sm_buffer *buffer)\n+{\n+\tint handle;\n+\n+\tspin_lock(&sm_state->kernelid_map_lock);\n+\thandle = idr_alloc(&sm_state->kernelid_map, buffer, 0, 0, GFP_KERNEL);\n+\tspin_unlock(&sm_state->kernelid_map_lock);\n+\n+\treturn handle;\n+}\n+\n+static struct vc_sm_buffer *lookup_kernel_id(int handle)\n+{\n+\treturn idr_find(&sm_state->kernelid_map, handle);\n+}\n+\n+static void free_kernel_id(int handle)\n+{\n+\tspin_lock(&sm_state->kernelid_map_lock);\n+\tidr_remove(&sm_state->kernelid_map, handle);\n+\tspin_unlock(&sm_state->kernelid_map_lock);\n+}\n+\n+static int vc_sm_cma_seq_file_show(struct seq_file *s, void *v)\n+{\n+\tstruct sm_pde_t *sm_pde;\n+\n+\tsm_pde = (struct sm_pde_t *)(s->private);\n+\n+\tif (sm_pde && sm_pde->show)\n+\t\tsm_pde->show(s, v);\n+\n+\treturn 0;\n+}\n+\n+static int vc_sm_cma_single_open(struct inode *inode, struct file *file)\n+{\n+\treturn single_open(file, vc_sm_cma_seq_file_show, inode->i_private);\n+}\n+\n+static const struct file_operations vc_sm_cma_debug_fs_fops = {\n+\t.open = vc_sm_cma_single_open,\n+\t.read = seq_read,\n+\t.llseek = seq_lseek,\n+\t.release = single_release,\n+};\n+\n+static int vc_sm_cma_global_state_show(struct seq_file *s, void *v)\n+{\n+\tstruct vc_sm_buffer *resource = NULL;\n+\tint resource_count = 0;\n+\n+\tif (!sm_state)\n+\t\treturn 0;\n+\n+\tseq_printf(s, \"\\nVC-ServiceHandle     %p\\n\", sm_state->sm_handle);\n+\n+\t/* Log all applicable mapping(s). */\n+\n+\tmutex_lock(&sm_state->map_lock);\n+\tseq_puts(s, \"\\nResources\\n\");\n+\tif (!list_empty(&sm_state->buffer_list)) {\n+\t\tlist_for_each_entry(resource, &sm_state->buffer_list,\n+\t\t\t\t    global_buffer_list) {\n+\t\t\tresource_count++;\n+\n+\t\t\tseq_printf(s, \"\\nResource                %p\\n\",\n+\t\t\t\t   resource);\n+\t\t\tseq_printf(s, \"           NAME         %s\\n\",\n+\t\t\t\t   resource->name);\n+\t\t\tseq_printf(s, \"           SIZE         %zu\\n\",\n+\t\t\t\t   resource->size);\n+\t\t\tseq_printf(s, \"           DMABUF       %p\\n\",\n+\t\t\t\t   resource->dma_buf);\n+\t\t\tif (resource->imported) {\n+\t\t\t\tseq_printf(s, \"           ATTACH       %p\\n\",\n+\t\t\t\t\t   resource->import.attach);\n+\t\t\t\tseq_printf(s, \"           SGT          %p\\n\",\n+\t\t\t\t\t   resource->import.sgt);\n+\t\t\t} else {\n+\t\t\t\tseq_printf(s, \"           SGT          %p\\n\",\n+\t\t\t\t\t   resource->alloc.sg_table);\n+\t\t\t}\n+\t\t\tseq_printf(s, \"           DMA_ADDR     %pad\\n\",\n+\t\t\t\t   &resource->dma_addr);\n+\t\t\tseq_printf(s, \"           VC_HANDLE     %08x\\n\",\n+\t\t\t\t   resource->vc_handle);\n+\t\t\tseq_printf(s, \"           VC_MAPPING    %d\\n\",\n+\t\t\t\t   resource->vpu_state);\n+\t\t}\n+\t}\n+\tseq_printf(s, \"\\n\\nTotal resource count:   %d\\n\\n\", resource_count);\n+\n+\tmutex_unlock(&sm_state->map_lock);\n+\n+\treturn 0;\n+}\n+\n+/*\n+ * Adds a buffer to the private data list which tracks all the allocated\n+ * data.\n+ */\n+static void vc_sm_add_resource(struct vc_sm_privdata_t *privdata,\n+\t\t\t       struct vc_sm_buffer *buffer)\n+{\n+\tmutex_lock(&sm_state->map_lock);\n+\tlist_add(&buffer->global_buffer_list, &sm_state->buffer_list);\n+\tmutex_unlock(&sm_state->map_lock);\n+\n+\tpr_debug(\"[%s]: added buffer %p (name %s, size %zu)\\n\",\n+\t\t __func__, buffer, buffer->name, buffer->size);\n+}\n+\n+/*\n+ * Cleans up imported dmabuf.\n+ */\n+static void vc_sm_clean_up_dmabuf(struct vc_sm_buffer *buffer)\n+{\n+\tif (!buffer->imported)\n+\t\treturn;\n+\n+\t/* Handle cleaning up imported dmabufs */\n+\tmutex_lock(&buffer->lock);\n+\tif (buffer->import.sgt) {\n+\t\tdma_buf_unmap_attachment(buffer->import.attach,\n+\t\t\t\t\t buffer->import.sgt,\n+\t\t\t\t\t DMA_BIDIRECTIONAL);\n+\t\tbuffer->import.sgt = NULL;\n+\t}\n+\tif (buffer->import.attach) {\n+\t\tdma_buf_detach(buffer->dma_buf, buffer->import.attach);\n+\t\tbuffer->import.attach = NULL;\n+\t}\n+\tmutex_unlock(&buffer->lock);\n+}\n+\n+/*\n+ * Instructs VPU to decrement the refcount on a buffer.\n+ */\n+static void vc_sm_vpu_free(struct vc_sm_buffer *buffer)\n+{\n+\tif (buffer->vc_handle && buffer->vpu_state == VPU_MAPPED) {\n+\t\tstruct vc_sm_free_t free = { buffer->vc_handle, 0 };\n+\t\tint status = vc_sm_cma_vchi_free(sm_state->sm_handle, &free,\n+\t\t\t\t\t     &sm_state->int_trans_id);\n+\t\tif (status != 0 && status != -EINTR) {\n+\t\t\tpr_err(\"[%s]: failed to free memory on videocore (status: %u, trans_id: %u)\\n\",\n+\t\t\t       __func__, status, sm_state->int_trans_id);\n+\t\t}\n+\n+\t\tif (sm_state->require_released_callback) {\n+\t\t\t/* Need to wait for the VPU to confirm the free. */\n+\n+\t\t\t/* Retain a reference on this until the VPU has\n+\t\t\t * released it\n+\t\t\t */\n+\t\t\tbuffer->vpu_state = VPU_UNMAPPING;\n+\t\t} else {\n+\t\t\tbuffer->vpu_state = VPU_NOT_MAPPED;\n+\t\t\tbuffer->vc_handle = 0;\n+\t\t}\n+\t}\n+}\n+\n+/*\n+ * Release an allocation.\n+ * All refcounting is done via the dma buf object.\n+ *\n+ * Must be called with the mutex held. The function will either release the\n+ * mutex (if defering the release) or destroy it. The caller must therefore not\n+ * reuse the buffer on return.\n+ */\n+static void vc_sm_release_resource(struct vc_sm_buffer *buffer)\n+{\n+\tpr_debug(\"[%s]: buffer %p (name %s, size %zu), imported %u\\n\",\n+\t\t __func__, buffer, buffer->name, buffer->size,\n+\t\t buffer->imported);\n+\n+\tif (buffer->vc_handle) {\n+\t\t/* We've sent the unmap request but not had the response. */\n+\t\tpr_debug(\"[%s]: Waiting for VPU unmap response on %p\\n\",\n+\t\t\t __func__, buffer);\n+\t\tgoto defer;\n+\t}\n+\tif (buffer->in_use) {\n+\t\t/* dmabuf still in use - we await the release */\n+\t\tpr_debug(\"[%s]: buffer %p is still in use\\n\", __func__, buffer);\n+\t\tgoto defer;\n+\t}\n+\n+\t/* Release the allocation (whether imported dmabuf or CMA allocation) */\n+\tif (buffer->imported) {\n+\t\tif (buffer->import.dma_buf)\n+\t\t\tdma_buf_put(buffer->import.dma_buf);\n+\t\telse\n+\t\t\tpr_err(\"%s: Imported dmabuf already been put for buf %p\\n\",\n+\t\t\t       __func__, buffer);\n+\t\tbuffer->import.dma_buf = NULL;\n+\t} else {\n+\t\tdma_free_coherent(&sm_state->pdev->dev, buffer->size,\n+\t\t\t\t  buffer->cookie, buffer->dma_addr);\n+\t}\n+\n+\t/* Free our buffer. Start by removing it from the list */\n+\tmutex_lock(&sm_state->map_lock);\n+\tlist_del(&buffer->global_buffer_list);\n+\tmutex_unlock(&sm_state->map_lock);\n+\n+\tpr_debug(\"%s: Release our allocation - done\\n\", __func__);\n+\tmutex_unlock(&buffer->lock);\n+\n+\tmutex_destroy(&buffer->lock);\n+\n+\tkfree(buffer);\n+\treturn;\n+\n+defer:\n+\tmutex_unlock(&buffer->lock);\n+}\n+\n+/* Create support for private data tracking. */\n+static struct vc_sm_privdata_t *vc_sm_cma_create_priv_data(pid_t id)\n+{\n+\tchar alloc_name[32];\n+\tstruct vc_sm_privdata_t *file_data = NULL;\n+\n+\t/* Allocate private structure. */\n+\tfile_data = kzalloc(sizeof(*file_data), GFP_KERNEL);\n+\n+\tif (!file_data)\n+\t\treturn NULL;\n+\n+\tsnprintf(alloc_name, sizeof(alloc_name), \"%d\", id);\n+\n+\tfile_data->pid = id;\n+\n+\treturn file_data;\n+}\n+\n+/* Dma buf operations for use with our own allocations */\n+\n+static int vc_sm_dma_buf_attach(struct dma_buf *dmabuf,\n+\t\t\t\tstruct dma_buf_attachment *attachment)\n+\n+{\n+\tstruct vc_sm_dma_buf_attachment *a;\n+\tstruct sg_table *sgt;\n+\tstruct vc_sm_buffer *buf = dmabuf->priv;\n+\tstruct scatterlist *rd, *wr;\n+\tint ret, i;\n+\n+\ta = kzalloc(sizeof(*a), GFP_KERNEL);\n+\tif (!a)\n+\t\treturn -ENOMEM;\n+\n+\tpr_debug(\"%s dmabuf %p attachment %p\\n\", __func__, dmabuf, attachment);\n+\n+\tmutex_lock(&buf->lock);\n+\n+\tINIT_LIST_HEAD(&a->list);\n+\n+\tsgt = &a->sg_table;\n+\n+\t/* Copy the buf->base_sgt scatter list to the attachment, as we can't\n+\t * map the same scatter list to multiple attachments at the same time.\n+\t */\n+\tret = sg_alloc_table(sgt, buf->alloc.sg_table->orig_nents, GFP_KERNEL);\n+\tif (ret) {\n+\t\tkfree(a);\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\trd = buf->alloc.sg_table->sgl;\n+\twr = sgt->sgl;\n+\tfor (i = 0; i < sgt->orig_nents; ++i) {\n+\t\tsg_set_page(wr, sg_page(rd), rd->length, rd->offset);\n+\t\trd = sg_next(rd);\n+\t\twr = sg_next(wr);\n+\t}\n+\n+\ta->dma_dir = DMA_NONE;\n+\tattachment->priv = a;\n+\n+\tlist_add(&a->list, &buf->attachments);\n+\tmutex_unlock(&buf->lock);\n+\n+\treturn 0;\n+}\n+\n+static void vc_sm_dma_buf_detach(struct dma_buf *dmabuf,\n+\t\t\t\t struct dma_buf_attachment *attachment)\n+{\n+\tstruct vc_sm_dma_buf_attachment *a = attachment->priv;\n+\tstruct vc_sm_buffer *buf = dmabuf->priv;\n+\tstruct sg_table *sgt;\n+\n+\tpr_debug(\"%s dmabuf %p attachment %p\\n\", __func__, dmabuf, attachment);\n+\tif (!a)\n+\t\treturn;\n+\n+\tsgt = &a->sg_table;\n+\n+\t/* release the scatterlist cache */\n+\tif (a->dma_dir != DMA_NONE)\n+\t\tdma_unmap_sg(attachment->dev, sgt->sgl, sgt->orig_nents,\n+\t\t\t     a->dma_dir);\n+\tsg_free_table(sgt);\n+\n+\tmutex_lock(&buf->lock);\n+\tlist_del(&a->list);\n+\tmutex_unlock(&buf->lock);\n+\n+\tkfree(a);\n+}\n+\n+static struct sg_table *vc_sm_map_dma_buf(struct dma_buf_attachment *attachment,\n+\t\t\t\t\t  enum dma_data_direction direction)\n+{\n+\tstruct vc_sm_dma_buf_attachment *a = attachment->priv;\n+\t/* stealing dmabuf mutex to serialize map/unmap operations */\n+\tstruct mutex *lock = &attachment->dmabuf->lock;\n+\tstruct sg_table *table;\n+\n+\tmutex_lock(lock);\n+\tpr_debug(\"%s attachment %p\\n\", __func__, attachment);\n+\ttable = &a->sg_table;\n+\n+\t/* return previously mapped sg table */\n+\tif (a->dma_dir == direction) {\n+\t\tmutex_unlock(lock);\n+\t\treturn table;\n+\t}\n+\n+\t/* release any previous cache */\n+\tif (a->dma_dir != DMA_NONE) {\n+\t\tdma_unmap_sg(attachment->dev, table->sgl, table->orig_nents,\n+\t\t\t     a->dma_dir);\n+\t\ta->dma_dir = DMA_NONE;\n+\t}\n+\n+\t/* mapping to the client with new direction */\n+\ttable->nents = dma_map_sg(attachment->dev, table->sgl,\n+\t\t\t\t  table->orig_nents, direction);\n+\tif (!table->nents) {\n+\t\tpr_err(\"failed to map scatterlist\\n\");\n+\t\tmutex_unlock(lock);\n+\t\treturn ERR_PTR(-EIO);\n+\t}\n+\n+\ta->dma_dir = direction;\n+\tmutex_unlock(lock);\n+\n+\tpr_debug(\"%s attachment %p\\n\", __func__, attachment);\n+\treturn table;\n+}\n+\n+static void vc_sm_unmap_dma_buf(struct dma_buf_attachment *attachment,\n+\t\t\t\tstruct sg_table *table,\n+\t\t\t\tenum dma_data_direction direction)\n+{\n+\tpr_debug(\"%s attachment %p\\n\", __func__, attachment);\n+\tdma_unmap_sg(attachment->dev, table->sgl, table->nents, direction);\n+}\n+\n+static int vc_sm_dmabuf_mmap(struct dma_buf *dmabuf, struct vm_area_struct *vma)\n+{\n+\tstruct vc_sm_buffer *buf = dmabuf->priv;\n+\tint ret;\n+\n+\tpr_debug(\"%s dmabuf %p, buf %p, vm_start %08lX\\n\", __func__, dmabuf,\n+\t\t buf, vma->vm_start);\n+\n+\tmutex_lock(&buf->lock);\n+\n+\t/* now map it to userspace */\n+\tvma->vm_pgoff = 0;\n+\n+\tret = dma_mmap_coherent(&sm_state->pdev->dev, vma, buf->cookie,\n+\t\t\t\tbuf->dma_addr, buf->size);\n+\n+\tif (ret) {\n+\t\tpr_err(\"Remapping memory failed, error: %d\\n\", ret);\n+\t\treturn ret;\n+\t}\n+\n+\tvma->vm_flags |= VM_DONTEXPAND | VM_DONTDUMP;\n+\n+\tmutex_unlock(&buf->lock);\n+\n+\tif (ret)\n+\t\tpr_err(\"%s: failure mapping buffer to userspace\\n\",\n+\t\t       __func__);\n+\n+\treturn ret;\n+}\n+\n+static void vc_sm_dma_buf_release(struct dma_buf *dmabuf)\n+{\n+\tstruct vc_sm_buffer *buffer;\n+\n+\tif (!dmabuf)\n+\t\treturn;\n+\n+\tbuffer = (struct vc_sm_buffer *)dmabuf->priv;\n+\n+\tmutex_lock(&buffer->lock);\n+\n+\tpr_debug(\"%s dmabuf %p, buffer %p\\n\", __func__, dmabuf, buffer);\n+\n+\tbuffer->in_use = 0;\n+\n+\t/* Unmap on the VPU */\n+\tvc_sm_vpu_free(buffer);\n+\tpr_debug(\"%s vpu_free done\\n\", __func__);\n+\n+\t/* Unmap our dma_buf object (the vc_sm_buffer remains until released\n+\t * on the VPU).\n+\t */\n+\tvc_sm_clean_up_dmabuf(buffer);\n+\tpr_debug(\"%s clean_up dmabuf done\\n\", __func__);\n+\n+\t/* buffer->lock will be destroyed by vc_sm_release_resource if finished\n+\t * with, otherwise unlocked. Do NOT unlock here.\n+\t */\n+\tvc_sm_release_resource(buffer);\n+\tpr_debug(\"%s done\\n\", __func__);\n+}\n+\n+static int vc_sm_dma_buf_begin_cpu_access(struct dma_buf *dmabuf,\n+\t\t\t\t\t  enum dma_data_direction direction)\n+{\n+\tstruct vc_sm_buffer *buf;\n+\tstruct vc_sm_dma_buf_attachment *a;\n+\n+\tif (!dmabuf)\n+\t\treturn -EFAULT;\n+\n+\tbuf = dmabuf->priv;\n+\tif (!buf)\n+\t\treturn -EFAULT;\n+\n+\tmutex_lock(&buf->lock);\n+\n+\tlist_for_each_entry(a, &buf->attachments, list) {\n+\t\tdma_sync_sg_for_cpu(a->dev, a->sg_table.sgl,\n+\t\t\t\t    a->sg_table.nents, direction);\n+\t}\n+\tmutex_unlock(&buf->lock);\n+\n+\treturn 0;\n+}\n+\n+static int vc_sm_dma_buf_end_cpu_access(struct dma_buf *dmabuf,\n+\t\t\t\t\tenum dma_data_direction direction)\n+{\n+\tstruct vc_sm_buffer *buf;\n+\tstruct vc_sm_dma_buf_attachment *a;\n+\n+\tif (!dmabuf)\n+\t\treturn -EFAULT;\n+\tbuf = dmabuf->priv;\n+\tif (!buf)\n+\t\treturn -EFAULT;\n+\n+\tmutex_lock(&buf->lock);\n+\n+\tlist_for_each_entry(a, &buf->attachments, list) {\n+\t\tdma_sync_sg_for_device(a->dev, a->sg_table.sgl,\n+\t\t\t\t       a->sg_table.nents, direction);\n+\t}\n+\tmutex_unlock(&buf->lock);\n+\n+\treturn 0;\n+}\n+\n+static const struct dma_buf_ops dma_buf_ops = {\n+\t.map_dma_buf = vc_sm_map_dma_buf,\n+\t.unmap_dma_buf = vc_sm_unmap_dma_buf,\n+\t.mmap = vc_sm_dmabuf_mmap,\n+\t.release = vc_sm_dma_buf_release,\n+\t.attach = vc_sm_dma_buf_attach,\n+\t.detach = vc_sm_dma_buf_detach,\n+\t.begin_cpu_access = vc_sm_dma_buf_begin_cpu_access,\n+\t.end_cpu_access = vc_sm_dma_buf_end_cpu_access,\n+};\n+\n+/* Dma_buf operations for chaining through to an imported dma_buf */\n+\n+static\n+int vc_sm_import_dma_buf_attach(struct dma_buf *dmabuf,\n+\t\t\t\tstruct dma_buf_attachment *attachment)\n+{\n+\tstruct vc_sm_buffer *buf = dmabuf->priv;\n+\n+\tif (!buf->imported)\n+\t\treturn -EINVAL;\n+\treturn buf->import.dma_buf->ops->attach(buf->import.dma_buf,\n+\t\t\t\t\t\tattachment);\n+}\n+\n+static\n+void vc_sm_import_dma_buf_detatch(struct dma_buf *dmabuf,\n+\t\t\t\t  struct dma_buf_attachment *attachment)\n+{\n+\tstruct vc_sm_buffer *buf = dmabuf->priv;\n+\n+\tif (!buf->imported)\n+\t\treturn;\n+\tbuf->import.dma_buf->ops->detach(buf->import.dma_buf, attachment);\n+}\n+\n+static\n+struct sg_table *vc_sm_import_map_dma_buf(struct dma_buf_attachment *attachment,\n+\t\t\t\t\t  enum dma_data_direction direction)\n+{\n+\tstruct vc_sm_buffer *buf = attachment->dmabuf->priv;\n+\n+\tif (!buf->imported)\n+\t\treturn NULL;\n+\treturn buf->import.dma_buf->ops->map_dma_buf(attachment,\n+\t\t\t\t\t\t     direction);\n+}\n+\n+static\n+void vc_sm_import_unmap_dma_buf(struct dma_buf_attachment *attachment,\n+\t\t\t\tstruct sg_table *table,\n+\t\t\t\tenum dma_data_direction direction)\n+{\n+\tstruct vc_sm_buffer *buf = attachment->dmabuf->priv;\n+\n+\tif (!buf->imported)\n+\t\treturn;\n+\tbuf->import.dma_buf->ops->unmap_dma_buf(attachment, table, direction);\n+}\n+\n+static\n+int vc_sm_import_dmabuf_mmap(struct dma_buf *dmabuf, struct vm_area_struct *vma)\n+{\n+\tstruct vc_sm_buffer *buf = dmabuf->priv;\n+\n+\tpr_debug(\"%s: mmap dma_buf %p, buf %p, imported db %p\\n\", __func__,\n+\t\t dmabuf, buf, buf->import.dma_buf);\n+\tif (!buf->imported) {\n+\t\tpr_err(\"%s: mmap dma_buf %p- not an imported buffer\\n\",\n+\t\t       __func__, dmabuf);\n+\t\treturn -EINVAL;\n+\t}\n+\treturn buf->import.dma_buf->ops->mmap(buf->import.dma_buf, vma);\n+}\n+\n+static\n+void vc_sm_import_dma_buf_release(struct dma_buf *dmabuf)\n+{\n+\tstruct vc_sm_buffer *buf = dmabuf->priv;\n+\n+\tpr_debug(\"%s: Relasing dma_buf %p\\n\", __func__, dmabuf);\n+\tmutex_lock(&buf->lock);\n+\tif (!buf->imported)\n+\t\treturn;\n+\n+\tbuf->in_use = 0;\n+\n+\tvc_sm_vpu_free(buf);\n+\n+\tvc_sm_release_resource(buf);\n+}\n+\n+static\n+int vc_sm_import_dma_buf_begin_cpu_access(struct dma_buf *dmabuf,\n+\t\t\t\t\t  enum dma_data_direction direction)\n+{\n+\tstruct vc_sm_buffer *buf = dmabuf->priv;\n+\n+\tif (!buf->imported)\n+\t\treturn -EINVAL;\n+\treturn buf->import.dma_buf->ops->begin_cpu_access(buf->import.dma_buf,\n+\t\t\t\t\t\t\t  direction);\n+}\n+\n+static\n+int vc_sm_import_dma_buf_end_cpu_access(struct dma_buf *dmabuf,\n+\t\t\t\t\tenum dma_data_direction direction)\n+{\n+\tstruct vc_sm_buffer *buf = dmabuf->priv;\n+\n+\tif (!buf->imported)\n+\t\treturn -EINVAL;\n+\treturn buf->import.dma_buf->ops->end_cpu_access(buf->import.dma_buf,\n+\t\t\t\t\t\t\t  direction);\n+}\n+\n+static const struct dma_buf_ops dma_buf_import_ops = {\n+\t.map_dma_buf = vc_sm_import_map_dma_buf,\n+\t.unmap_dma_buf = vc_sm_import_unmap_dma_buf,\n+\t.mmap = vc_sm_import_dmabuf_mmap,\n+\t.release = vc_sm_import_dma_buf_release,\n+\t.attach = vc_sm_import_dma_buf_attach,\n+\t.detach = vc_sm_import_dma_buf_detatch,\n+\t.begin_cpu_access = vc_sm_import_dma_buf_begin_cpu_access,\n+\t.end_cpu_access = vc_sm_import_dma_buf_end_cpu_access,\n+};\n+\n+/* Import a dma_buf to be shared with VC. */\n+int\n+vc_sm_cma_import_dmabuf_internal(struct vc_sm_privdata_t *private,\n+\t\t\t\t struct dma_buf *dma_buf,\n+\t\t\t\t int fd,\n+\t\t\t\t struct dma_buf **imported_buf)\n+{\n+\tDEFINE_DMA_BUF_EXPORT_INFO(exp_info);\n+\tstruct vc_sm_buffer *buffer = NULL;\n+\tstruct vc_sm_import import = { };\n+\tstruct vc_sm_import_result result = { };\n+\tstruct dma_buf_attachment *attach = NULL;\n+\tstruct sg_table *sgt = NULL;\n+\tdma_addr_t dma_addr;\n+\tint ret = 0;\n+\tint status;\n+\n+\t/* Setup our allocation parameters */\n+\tpr_debug(\"%s: importing dma_buf %p/fd %d\\n\", __func__, dma_buf, fd);\n+\n+\tif (fd < 0)\n+\t\tget_dma_buf(dma_buf);\n+\telse\n+\t\tdma_buf = dma_buf_get(fd);\n+\n+\tif (!dma_buf)\n+\t\treturn -EINVAL;\n+\n+\tattach = dma_buf_attach(dma_buf, &sm_state->pdev->dev);\n+\tif (IS_ERR(attach)) {\n+\t\tret = PTR_ERR(attach);\n+\t\tgoto error;\n+\t}\n+\n+\tsgt = dma_buf_map_attachment(attach, DMA_BIDIRECTIONAL);\n+\tif (IS_ERR(sgt)) {\n+\t\tret = PTR_ERR(sgt);\n+\t\tgoto error;\n+\t}\n+\n+\t/* Verify that the address block is contiguous */\n+\tif (sgt->nents != 1) {\n+\t\tret = -ENOMEM;\n+\t\tgoto error;\n+\t}\n+\n+\t/* Allocate local buffer to track this allocation. */\n+\tbuffer = kzalloc(sizeof(*buffer), GFP_KERNEL);\n+\tif (!buffer) {\n+\t\tret = -ENOMEM;\n+\t\tgoto error;\n+\t}\n+\n+\timport.type = VC_SM_ALLOC_NON_CACHED;\n+\tdma_addr = sg_dma_address(sgt->sgl);\n+\timport.addr = (u32)dma_addr;\n+\tif ((import.addr & 0xC0000000) != 0xC0000000) {\n+\t\tpr_err(\"%s: Expecting an uncached alias for dma_addr %pad\\n\",\n+\t\t       __func__, &dma_addr);\n+\t\timport.addr |= 0xC0000000;\n+\t}\n+\timport.size = sg_dma_len(sgt->sgl);\n+\timport.allocator = current->tgid;\n+\timport.kernel_id = get_kernel_id(buffer);\n+\n+\tmemcpy(import.name, VC_SM_RESOURCE_NAME_DEFAULT,\n+\t       sizeof(VC_SM_RESOURCE_NAME_DEFAULT));\n+\n+\tpr_debug(\"[%s]: attempt to import \\\"%s\\\" data - type %u, addr %pad, size %u.\\n\",\n+\t\t __func__, import.name, import.type, &dma_addr, import.size);\n+\n+\t/* Allocate the videocore buffer. */\n+\tstatus = vc_sm_cma_vchi_import(sm_state->sm_handle, &import, &result,\n+\t\t\t\t       &sm_state->int_trans_id);\n+\tif (status == -EINTR) {\n+\t\tpr_debug(\"[%s]: requesting import memory action restart (trans_id: %u)\\n\",\n+\t\t\t __func__, sm_state->int_trans_id);\n+\t\tret = -ERESTARTSYS;\n+\t\tprivate->restart_sys = -EINTR;\n+\t\tprivate->int_action = VC_SM_MSG_TYPE_IMPORT;\n+\t\tgoto error;\n+\t} else if (status || !result.res_handle) {\n+\t\tpr_debug(\"[%s]: failed to import memory on videocore (status: %u, trans_id: %u)\\n\",\n+\t\t\t __func__, status, sm_state->int_trans_id);\n+\t\tret = -ENOMEM;\n+\t\tgoto error;\n+\t}\n+\n+\tmutex_init(&buffer->lock);\n+\tINIT_LIST_HEAD(&buffer->attachments);\n+\tmemcpy(buffer->name, import.name,\n+\t       min(sizeof(buffer->name), sizeof(import.name) - 1));\n+\n+\t/* Keep track of the buffer we created. */\n+\tbuffer->private = private;\n+\tbuffer->vc_handle = result.res_handle;\n+\tbuffer->size = import.size;\n+\tbuffer->vpu_state = VPU_MAPPED;\n+\n+\tbuffer->imported = 1;\n+\tbuffer->import.dma_buf = dma_buf;\n+\n+\tbuffer->import.attach = attach;\n+\tbuffer->import.sgt = sgt;\n+\tbuffer->dma_addr = dma_addr;\n+\tbuffer->in_use = 1;\n+\tbuffer->kernel_id = import.kernel_id;\n+\n+\t/*\n+\t * We're done - we need to export a new dmabuf chaining through most\n+\t * functions, but enabling us to release our own internal references\n+\t * here.\n+\t */\n+\texp_info.ops = &dma_buf_import_ops;\n+\texp_info.size = import.size;\n+\texp_info.flags = O_RDWR;\n+\texp_info.priv = buffer;\n+\n+\tbuffer->dma_buf = dma_buf_export(&exp_info);\n+\tif (IS_ERR(buffer->dma_buf)) {\n+\t\tret = PTR_ERR(buffer->dma_buf);\n+\t\tgoto error;\n+\t}\n+\n+\tvc_sm_add_resource(private, buffer);\n+\n+\t*imported_buf = buffer->dma_buf;\n+\n+\treturn 0;\n+\n+error:\n+\tif (result.res_handle) {\n+\t\tstruct vc_sm_free_t free = { result.res_handle, 0 };\n+\n+\t\tvc_sm_cma_vchi_free(sm_state->sm_handle, &free,\n+\t\t\t\t    &sm_state->int_trans_id);\n+\t}\n+\tfree_kernel_id(import.kernel_id);\n+\tkfree(buffer);\n+\tif (sgt)\n+\t\tdma_buf_unmap_attachment(attach, sgt, DMA_BIDIRECTIONAL);\n+\tif (attach)\n+\t\tdma_buf_detach(dma_buf, attach);\n+\tdma_buf_put(dma_buf);\n+\treturn ret;\n+}\n+\n+static int vc_sm_cma_vpu_alloc(u32 size, u32 align, const char *name,\n+\t\t\t       u32 mem_handle, struct vc_sm_buffer **ret_buffer)\n+{\n+\tDEFINE_DMA_BUF_EXPORT_INFO(exp_info);\n+\tstruct vc_sm_buffer *buffer = NULL;\n+\tstruct sg_table *sgt;\n+\tint aligned_size;\n+\tint ret = 0;\n+\n+\t/* Align to the user requested align */\n+\taligned_size = ALIGN(size, align);\n+\t/* and then to a page boundary */\n+\taligned_size = PAGE_ALIGN(aligned_size);\n+\n+\tif (!aligned_size)\n+\t\treturn -EINVAL;\n+\n+\t/* Allocate local buffer to track this allocation. */\n+\tbuffer = kzalloc(sizeof(*buffer), GFP_KERNEL);\n+\tif (!buffer)\n+\t\treturn -ENOMEM;\n+\n+\tmutex_init(&buffer->lock);\n+\t/* Acquire the mutex as vc_sm_release_resource will release it in the\n+\t * error path.\n+\t */\n+\tmutex_lock(&buffer->lock);\n+\n+\tbuffer->cookie = dma_alloc_coherent(&sm_state->pdev->dev,\n+\t\t\t\t\t    aligned_size, &buffer->dma_addr,\n+\t\t\t\t\t    GFP_KERNEL);\n+\tif (!buffer->cookie) {\n+\t\tpr_err(\"[%s]: dma_alloc_coherent alloc of %d bytes failed\\n\",\n+\t\t       __func__, aligned_size);\n+\t\tret = -ENOMEM;\n+\t\tgoto error;\n+\t}\n+\n+\tpr_debug(\"[%s]: alloc of %d bytes success\\n\",\n+\t\t __func__, aligned_size);\n+\n+\tsgt = kmalloc(sizeof(*sgt), GFP_KERNEL);\n+\tif (!sgt) {\n+\t\tret = -ENOMEM;\n+\t\tgoto error;\n+\t}\n+\n+\tret = dma_get_sgtable(&sm_state->pdev->dev, sgt, buffer->cookie,\n+\t\t\t      buffer->dma_addr, buffer->size);\n+\tif (ret < 0) {\n+\t\tpr_err(\"failed to get scatterlist from DMA API\\n\");\n+\t\tkfree(sgt);\n+\t\tret = -ENOMEM;\n+\t\tgoto error;\n+\t}\n+\tbuffer->alloc.sg_table = sgt;\n+\n+\tINIT_LIST_HEAD(&buffer->attachments);\n+\n+\tmemcpy(buffer->name, name,\n+\t       min(sizeof(buffer->name), strlen(name)));\n+\n+\texp_info.ops = &dma_buf_ops;\n+\texp_info.size = aligned_size;\n+\texp_info.flags = O_RDWR;\n+\texp_info.priv = buffer;\n+\n+\tbuffer->dma_buf = dma_buf_export(&exp_info);\n+\tif (IS_ERR(buffer->dma_buf)) {\n+\t\tret = PTR_ERR(buffer->dma_buf);\n+\t\tgoto error;\n+\t}\n+\tbuffer->dma_addr = (u32)sg_dma_address(buffer->alloc.sg_table->sgl);\n+\tif ((buffer->dma_addr & 0xC0000000) != 0xC0000000) {\n+\t\tpr_warn_once(\"%s: Expecting an uncached alias for dma_addr %pad\\n\",\n+\t\t\t     __func__, &buffer->dma_addr);\n+\t\tbuffer->dma_addr |= 0xC0000000;\n+\t}\n+\tbuffer->private = sm_state->vpu_allocs;\n+\n+\tbuffer->vc_handle = mem_handle;\n+\tbuffer->vpu_state = VPU_MAPPED;\n+\tbuffer->vpu_allocated = 1;\n+\tbuffer->size = size;\n+\t/*\n+\t * Create an ID that will be passed along with our message so\n+\t * that when we service the release reply, we can look up which\n+\t * resource is being released.\n+\t */\n+\tbuffer->kernel_id = get_kernel_id(buffer);\n+\n+\tvc_sm_add_resource(sm_state->vpu_allocs, buffer);\n+\n+\tmutex_unlock(&buffer->lock);\n+\n+\t*ret_buffer = buffer;\n+\treturn 0;\n+error:\n+\tif (buffer)\n+\t\tvc_sm_release_resource(buffer);\n+\treturn ret;\n+}\n+\n+static void\n+vc_sm_vpu_event(struct sm_instance *instance, struct vc_sm_result_t *reply,\n+\t\tint reply_len)\n+{\n+\tswitch (reply->trans_id & ~0x80000000) {\n+\tcase VC_SM_MSG_TYPE_CLIENT_VERSION:\n+\t{\n+\t\t/* Acknowledge that the firmware supports the version command */\n+\t\tpr_debug(\"%s: firmware acked version msg. Require release cb\\n\",\n+\t\t\t __func__);\n+\t\tsm_state->require_released_callback = true;\n+\t}\n+\tbreak;\n+\tcase VC_SM_MSG_TYPE_RELEASED:\n+\t{\n+\t\tstruct vc_sm_released *release = (struct vc_sm_released *)reply;\n+\t\tstruct vc_sm_buffer *buffer =\n+\t\t\t\t\tlookup_kernel_id(release->kernel_id);\n+\t\tif (!buffer) {\n+\t\t\tpr_err(\"%s: VC released a buffer that is already released, kernel_id %d\\n\",\n+\t\t\t       __func__, release->kernel_id);\n+\t\t\tbreak;\n+\t\t}\n+\t\tmutex_lock(&buffer->lock);\n+\n+\t\tpr_debug(\"%s: Released addr %08x, size %u, id %08x, mem_handle %08x\\n\",\n+\t\t\t __func__, release->addr, release->size,\n+\t\t\t release->kernel_id, release->vc_handle);\n+\n+\t\tbuffer->vc_handle = 0;\n+\t\tbuffer->vpu_state = VPU_NOT_MAPPED;\n+\t\tfree_kernel_id(release->kernel_id);\n+\n+\t\tif (buffer->vpu_allocated) {\n+\t\t\t/* VPU allocation, so release the dmabuf which will\n+\t\t\t * trigger the clean up.\n+\t\t\t */\n+\t\t\tmutex_unlock(&buffer->lock);\n+\t\t\tdma_buf_put(buffer->dma_buf);\n+\t\t} else {\n+\t\t\tvc_sm_release_resource(buffer);\n+\t\t}\n+\t}\n+\tbreak;\n+\tcase VC_SM_MSG_TYPE_VC_MEM_REQUEST:\n+\t{\n+\t\tstruct vc_sm_buffer *buffer = NULL;\n+\t\tstruct vc_sm_vc_mem_request *req =\n+\t\t\t\t\t(struct vc_sm_vc_mem_request *)reply;\n+\t\tstruct vc_sm_vc_mem_request_result reply;\n+\t\tint ret;\n+\n+\t\tpr_debug(\"%s: Request %u bytes of memory, align %d name %s, trans_id %08x\\n\",\n+\t\t\t __func__, req->size, req->align, req->name,\n+\t\t\t req->trans_id);\n+\t\tret = vc_sm_cma_vpu_alloc(req->size, req->align, req->name,\n+\t\t\t\t\t  req->vc_handle, &buffer);\n+\n+\t\treply.trans_id = req->trans_id;\n+\t\tif (!ret) {\n+\t\t\treply.addr = buffer->dma_addr;\n+\t\t\treply.kernel_id = buffer->kernel_id;\n+\t\t\tpr_debug(\"%s: Allocated resource buffer %p, addr %pad\\n\",\n+\t\t\t\t __func__, buffer, &buffer->dma_addr);\n+\t\t} else {\n+\t\t\tpr_err(\"%s: Allocation failed size %u, name %s, vc_handle %u\\n\",\n+\t\t\t       __func__, req->size, req->name, req->vc_handle);\n+\t\t\treply.addr = 0;\n+\t\t\treply.kernel_id = 0;\n+\t\t}\n+\t\tvc_sm_vchi_client_vc_mem_req_reply(sm_state->sm_handle, &reply,\n+\t\t\t\t\t\t   &sm_state->int_trans_id);\n+\t\tbreak;\n+\t}\n+\tbreak;\n+\tdefault:\n+\t\tpr_err(\"%s: Unknown vpu cmd %x\\n\", __func__, reply->trans_id);\n+\t\tbreak;\n+\t}\n+}\n+\n+/* Userspace handling */\n+/*\n+ * Open the device.  Creates a private state to help track all allocation\n+ * associated with this device.\n+ */\n+static int vc_sm_cma_open(struct inode *inode, struct file *file)\n+{\n+\t/* Make sure the device was started properly. */\n+\tif (!sm_state) {\n+\t\tpr_err(\"[%s]: invalid device\\n\", __func__);\n+\t\treturn -EPERM;\n+\t}\n+\n+\tfile->private_data = vc_sm_cma_create_priv_data(current->tgid);\n+\tif (!file->private_data) {\n+\t\tpr_err(\"[%s]: failed to create data tracker\\n\", __func__);\n+\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+/*\n+ * Close the vcsm-cma device.\n+ * All allocations are file descriptors to the dmabuf objects, so we will get\n+ * the clean up request on those as those are cleaned up.\n+ */\n+static int vc_sm_cma_release(struct inode *inode, struct file *file)\n+{\n+\tstruct vc_sm_privdata_t *file_data =\n+\t    (struct vc_sm_privdata_t *)file->private_data;\n+\tint ret = 0;\n+\n+\t/* Make sure the device was started properly. */\n+\tif (!sm_state || !file_data) {\n+\t\tpr_err(\"[%s]: invalid device\\n\", __func__);\n+\t\tret = -EPERM;\n+\t\tgoto out;\n+\t}\n+\n+\tpr_debug(\"[%s]: using private data %p\\n\", __func__, file_data);\n+\n+\t/* Terminate the private data. */\n+\tkfree(file_data);\n+\n+out:\n+\treturn ret;\n+}\n+\n+/*\n+ * Allocate a shared memory handle and block.\n+ * Allocation is from CMA, and then imported into the VPU mappings.\n+ */\n+int vc_sm_cma_ioctl_alloc(struct vc_sm_privdata_t *private,\n+\t\t\t  struct vc_sm_cma_ioctl_alloc *ioparam)\n+{\n+\tDEFINE_DMA_BUF_EXPORT_INFO(exp_info);\n+\tstruct vc_sm_buffer *buffer = NULL;\n+\tstruct vc_sm_import import = { 0 };\n+\tstruct vc_sm_import_result result = { 0 };\n+\tstruct dma_buf *dmabuf = NULL;\n+\tstruct sg_table *sgt;\n+\tint aligned_size;\n+\tint ret = 0;\n+\tint status;\n+\tint fd = -1;\n+\n+\taligned_size = PAGE_ALIGN(ioparam->size);\n+\n+\tif (!aligned_size)\n+\t\treturn -EINVAL;\n+\n+\t/* Allocate local buffer to track this allocation. */\n+\tbuffer = kzalloc(sizeof(*buffer), GFP_KERNEL);\n+\tif (!buffer) {\n+\t\tret = -ENOMEM;\n+\t\tgoto error;\n+\t}\n+\n+\tbuffer->cookie = dma_alloc_coherent(&sm_state->pdev->dev,\n+\t\t\t\t\t    aligned_size,\n+\t\t\t\t\t    &buffer->dma_addr,\n+\t\t\t\t\t    GFP_KERNEL);\n+\tif (!buffer->cookie) {\n+\t\tpr_err(\"[%s]: dma_alloc_coherent alloc of %d bytes failed\\n\",\n+\t\t       __func__, aligned_size);\n+\t\tret = -ENOMEM;\n+\t\tgoto error;\n+\t}\n+\n+\timport.type = VC_SM_ALLOC_NON_CACHED;\n+\timport.allocator = current->tgid;\n+\n+\tif (*ioparam->name)\n+\t\tmemcpy(import.name, ioparam->name, sizeof(import.name) - 1);\n+\telse\n+\t\tmemcpy(import.name, VC_SM_RESOURCE_NAME_DEFAULT,\n+\t\t       sizeof(VC_SM_RESOURCE_NAME_DEFAULT));\n+\n+\tmutex_init(&buffer->lock);\n+\tINIT_LIST_HEAD(&buffer->attachments);\n+\tmemcpy(buffer->name, import.name,\n+\t       min(sizeof(buffer->name), sizeof(import.name) - 1));\n+\n+\texp_info.ops = &dma_buf_ops;\n+\texp_info.size = aligned_size;\n+\texp_info.flags = O_RDWR;\n+\texp_info.priv = buffer;\n+\n+\tdmabuf = dma_buf_export(&exp_info);\n+\tif (IS_ERR(dmabuf)) {\n+\t\tret = PTR_ERR(dmabuf);\n+\t\tgoto error;\n+\t}\n+\tbuffer->dma_buf = dmabuf;\n+\n+\timport.addr = buffer->dma_addr;\n+\timport.size = aligned_size;\n+\timport.kernel_id = get_kernel_id(buffer);\n+\n+\t/* Wrap it into a videocore buffer. */\n+\tstatus = vc_sm_cma_vchi_import(sm_state->sm_handle, &import, &result,\n+\t\t\t\t       &sm_state->int_trans_id);\n+\tif (status == -EINTR) {\n+\t\tpr_debug(\"[%s]: requesting import memory action restart (trans_id: %u)\\n\",\n+\t\t\t __func__, sm_state->int_trans_id);\n+\t\tret = -ERESTARTSYS;\n+\t\tprivate->restart_sys = -EINTR;\n+\t\tprivate->int_action = VC_SM_MSG_TYPE_IMPORT;\n+\t\tgoto error;\n+\t} else if (status || !result.res_handle) {\n+\t\tpr_err(\"[%s]: failed to import memory on videocore (status: %u, trans_id: %u)\\n\",\n+\t\t       __func__, status, sm_state->int_trans_id);\n+\t\tret = -ENOMEM;\n+\t\tgoto error;\n+\t}\n+\n+\t/* Keep track of the buffer we created. */\n+\tbuffer->private = private;\n+\tbuffer->vc_handle = result.res_handle;\n+\tbuffer->size = import.size;\n+\tbuffer->vpu_state = VPU_MAPPED;\n+\tbuffer->kernel_id = import.kernel_id;\n+\n+\tsgt = kmalloc(sizeof(*sgt), GFP_KERNEL);\n+\tif (!sgt) {\n+\t\tret = -ENOMEM;\n+\t\tgoto error;\n+\t}\n+\n+\tret = dma_get_sgtable(&sm_state->pdev->dev, sgt, buffer->cookie,\n+\t\t\t      buffer->dma_addr, buffer->size);\n+\tif (ret < 0) {\n+\t\t/* FIXME: error handling */\n+\t\tpr_err(\"failed to get scatterlist from DMA API\\n\");\n+\t\tkfree(sgt);\n+\t\tret = -ENOMEM;\n+\t\tgoto error;\n+\t}\n+\tbuffer->alloc.sg_table = sgt;\n+\n+\tfd = dma_buf_fd(dmabuf, O_CLOEXEC);\n+\tif (fd < 0)\n+\t\tgoto error;\n+\n+\tvc_sm_add_resource(private, buffer);\n+\n+\tpr_debug(\"[%s]: Added resource as fd %d, buffer %p, private %p, dma_addr %pad\\n\",\n+\t\t __func__, fd, buffer, private, &buffer->dma_addr);\n+\n+\t/* We're done */\n+\tioparam->handle = fd;\n+\tioparam->vc_handle = buffer->vc_handle;\n+\tioparam->dma_addr = buffer->dma_addr;\n+\treturn 0;\n+\n+error:\n+\tpr_err(\"[%s]: something failed - cleanup. ret %d\\n\", __func__, ret);\n+\n+\tif (dmabuf) {\n+\t\t/* dmabuf has been exported, therefore allow dmabuf cleanup to\n+\t\t * deal with this\n+\t\t */\n+\t\tdma_buf_put(dmabuf);\n+\t} else {\n+\t\t/* No dmabuf, therefore just free the buffer here */\n+\t\tif (buffer->cookie)\n+\t\t\tdma_free_coherent(&sm_state->pdev->dev, buffer->size,\n+\t\t\t\t\t  buffer->cookie, buffer->dma_addr);\n+\t\tkfree(buffer);\n+\t}\n+\treturn ret;\n+}\n+\n+#ifndef CONFIG_ARM64\n+/* Converts VCSM_CACHE_OP_* to an operating function. */\n+static void (*cache_op_to_func(const unsigned int cache_op))\n+\t\t\t\t\t\t(const void*, const void*)\n+{\n+\tswitch (cache_op) {\n+\tcase VC_SM_CACHE_OP_NOP:\n+\t\treturn NULL;\n+\n+\tcase VC_SM_CACHE_OP_INV:\n+\tcase VC_SM_CACHE_OP_CLEAN:\n+\tcase VC_SM_CACHE_OP_FLUSH:\n+\t\treturn dmac_flush_range;\n+\n+\tdefault:\n+\t\tpr_err(\"[%s]: Invalid cache_op: 0x%08x\\n\", __func__, cache_op);\n+\t\treturn NULL;\n+\t}\n+}\n+\n+/*\n+ * Clean/invalid/flush cache of which buffer is already pinned (i.e. accessed).\n+ */\n+static int clean_invalid_contig_2d(const void __user *addr,\n+\t\t\t\t   const size_t block_count,\n+\t\t\t\t   const size_t block_size,\n+\t\t\t\t   const size_t stride,\n+\t\t\t\t   const unsigned int cache_op)\n+{\n+\tsize_t i;\n+\tvoid (*op_fn)(const void *start, const void *end);\n+\n+\tif (!block_size) {\n+\t\tpr_err(\"[%s]: size cannot be 0\\n\", __func__);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\top_fn = cache_op_to_func(cache_op);\n+\tif (!op_fn)\n+\t\treturn -EINVAL;\n+\n+\tfor (i = 0; i < block_count; i ++, addr += stride)\n+\t\top_fn(addr, addr + block_size);\n+\n+\treturn 0;\n+}\n+\n+static int vc_sm_cma_clean_invalid2(unsigned int cmdnr, unsigned long arg)\n+{\n+\tstruct vc_sm_cma_ioctl_clean_invalid2 ioparam;\n+\tstruct vc_sm_cma_ioctl_clean_invalid_block *block = NULL;\n+\tint i, ret = 0;\n+\n+\t/* Get parameter data. */\n+\tif (copy_from_user(&ioparam, (void *)arg, sizeof(ioparam))) {\n+\t\tpr_err(\"[%s]: failed to copy-from-user header for cmd %x\\n\",\n+\t\t       __func__, cmdnr);\n+\t\treturn -EFAULT;\n+\t}\n+\tblock = kmalloc(ioparam.op_count * sizeof(*block), GFP_KERNEL);\n+\tif (!block)\n+\t\treturn -EFAULT;\n+\n+\tif (copy_from_user(block, (void *)(arg + sizeof(ioparam)),\n+\t\t\t   ioparam.op_count * sizeof(*block)) != 0) {\n+\t\tpr_err(\"[%s]: failed to copy-from-user payload for cmd %x\\n\",\n+\t\t       __func__, cmdnr);\n+\t\tret = -EFAULT;\n+\t\tgoto out;\n+\t}\n+\n+\tfor (i = 0; i < ioparam.op_count; i++) {\n+\t\tconst struct vc_sm_cma_ioctl_clean_invalid_block * const op =\n+\t\t\t\t\t\t\t\tblock + i;\n+\n+\t\tif (op->invalidate_mode == VC_SM_CACHE_OP_NOP)\n+\t\t\tcontinue;\n+\n+\t\tret = clean_invalid_contig_2d((void __user *)op->start_address,\n+\t\t\t\t\t      op->block_count, op->block_size,\n+\t\t\t\t\t      op->inter_block_stride,\n+\t\t\t\t\t      op->invalidate_mode);\n+\t\tif (ret)\n+\t\t\tbreak;\n+\t}\n+out:\n+\tkfree(block);\n+\n+\treturn ret;\n+}\n+#endif\n+\n+static long vc_sm_cma_ioctl(struct file *file, unsigned int cmd,\n+\t\t\t    unsigned long arg)\n+{\n+\tint ret = 0;\n+\tunsigned int cmdnr = _IOC_NR(cmd);\n+\tstruct vc_sm_privdata_t *file_data =\n+\t    (struct vc_sm_privdata_t *)file->private_data;\n+\n+\t/* Validate we can work with this device. */\n+\tif (!sm_state || !file_data) {\n+\t\tpr_err(\"[%s]: invalid device\\n\", __func__);\n+\t\treturn -EPERM;\n+\t}\n+\n+\t/* Action is a re-post of a previously interrupted action? */\n+\tif (file_data->restart_sys == -EINTR) {\n+\t\tpr_debug(\"[%s]: clean up of action %u (trans_id: %u) following EINTR\\n\",\n+\t\t\t __func__, file_data->int_action,\n+\t\t\t file_data->int_trans_id);\n+\n+\t\tfile_data->restart_sys = 0;\n+\t}\n+\n+\t/* Now process the command. */\n+\tswitch (cmdnr) {\n+\t\t/* New memory allocation.\n+\t\t */\n+\tcase VC_SM_CMA_CMD_ALLOC:\n+\t{\n+\t\tstruct vc_sm_cma_ioctl_alloc ioparam;\n+\n+\t\t/* Get the parameter data. */\n+\t\tif (copy_from_user\n+\t\t    (&ioparam, (void *)arg, sizeof(ioparam)) != 0) {\n+\t\t\tpr_err(\"[%s]: failed to copy-from-user for cmd %x\\n\",\n+\t\t\t       __func__, cmdnr);\n+\t\t\tret = -EFAULT;\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\tret = vc_sm_cma_ioctl_alloc(file_data, &ioparam);\n+\t\tif (!ret &&\n+\t\t    (copy_to_user((void *)arg, &ioparam,\n+\t\t\t\t  sizeof(ioparam)) != 0)) {\n+\t\t\t/* FIXME: Release allocation */\n+\t\t\tpr_err(\"[%s]: failed to copy-to-user for cmd %x\\n\",\n+\t\t\t       __func__, cmdnr);\n+\t\t\tret = -EFAULT;\n+\t\t}\n+\t\tbreak;\n+\t}\n+\n+\tcase VC_SM_CMA_CMD_IMPORT_DMABUF:\n+\t{\n+\t\tstruct vc_sm_cma_ioctl_import_dmabuf ioparam;\n+\t\tstruct dma_buf *new_dmabuf;\n+\n+\t\t/* Get the parameter data. */\n+\t\tif (copy_from_user\n+\t\t    (&ioparam, (void *)arg, sizeof(ioparam)) != 0) {\n+\t\t\tpr_err(\"[%s]: failed to copy-from-user for cmd %x\\n\",\n+\t\t\t       __func__, cmdnr);\n+\t\t\tret = -EFAULT;\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\tret = vc_sm_cma_import_dmabuf_internal(file_data,\n+\t\t\t\t\t\t       NULL,\n+\t\t\t\t\t\t       ioparam.dmabuf_fd,\n+\t\t\t\t\t\t       &new_dmabuf);\n+\n+\t\tif (!ret) {\n+\t\t\tstruct vc_sm_buffer *buf = new_dmabuf->priv;\n+\n+\t\t\tioparam.size = buf->size;\n+\t\t\tioparam.handle = dma_buf_fd(new_dmabuf,\n+\t\t\t\t\t\t    O_CLOEXEC);\n+\t\t\tioparam.vc_handle = buf->vc_handle;\n+\t\t\tioparam.dma_addr = buf->dma_addr;\n+\n+\t\t\tif (ioparam.handle < 0 ||\n+\t\t\t    (copy_to_user((void *)arg, &ioparam,\n+\t\t\t\t\t  sizeof(ioparam)) != 0)) {\n+\t\t\t\tdma_buf_put(new_dmabuf);\n+\t\t\t\t/* FIXME: Release allocation */\n+\t\t\t\tret = -EFAULT;\n+\t\t\t}\n+\t\t}\n+\t\tbreak;\n+\t}\n+\n+#ifndef CONFIG_ARM64\n+\t/*\n+\t * Flush/Invalidate the cache for a given mapping.\n+\t * Blocks must be pinned (i.e. accessed) before this call.\n+\t */\n+\tcase VC_SM_CMA_CMD_CLEAN_INVALID2:\n+\t\tret = vc_sm_cma_clean_invalid2(cmdnr, arg);\n+\t\tbreak;\n+#endif\n+\n+\tdefault:\n+\t\tpr_debug(\"[%s]: cmd %x tgid %u, owner %u\\n\", __func__, cmdnr,\n+\t\t\t current->tgid, file_data->pid);\n+\n+\t\tret = -EINVAL;\n+\t\tbreak;\n+\t}\n+\n+\treturn ret;\n+}\n+\n+#ifdef CONFIG_COMPAT\n+struct vc_sm_cma_ioctl_clean_invalid2_32 {\n+\tu32 op_count;\n+\tstruct vc_sm_cma_ioctl_clean_invalid_block_32 {\n+\t\tu16 invalidate_mode;\n+\t\tu16 block_count;\n+\t\tcompat_uptr_t start_address;\n+\t\tu32 block_size;\n+\t\tu32 inter_block_stride;\n+\t} s[0];\n+};\n+\n+#define VC_SM_CMA_CMD_CLEAN_INVALID2_32\\\n+\t_IOR(VC_SM_CMA_MAGIC_TYPE, VC_SM_CMA_CMD_CLEAN_INVALID2,\\\n+\t struct vc_sm_cma_ioctl_clean_invalid2_32)\n+\n+static long vc_sm_cma_compat_ioctl(struct file *file, unsigned int cmd,\n+\t\t\t\t   unsigned long arg)\n+{\n+\tswitch (cmd) {\n+\tcase VC_SM_CMA_CMD_CLEAN_INVALID2_32:\n+\t\t/* FIXME */\n+\t\treturn -EINVAL;\n+\n+\tdefault:\n+\t\treturn vc_sm_cma_ioctl(file, cmd, arg);\n+\t}\n+}\n+#endif\n+\n+/* Device operations that we managed in this driver. */\n+static const struct file_operations vc_sm_ops = {\n+\t.owner = THIS_MODULE,\n+\t.unlocked_ioctl = vc_sm_cma_ioctl,\n+#ifdef CONFIG_COMPAT\n+\t.compat_ioctl = vc_sm_cma_compat_ioctl,\n+#endif\n+\t.open = vc_sm_cma_open,\n+\t.release = vc_sm_cma_release,\n+};\n+\n+/* Driver load/unload functions */\n+/* Videocore connected.  */\n+static void vc_sm_connected_init(void)\n+{\n+\tint ret;\n+\tstruct vchiq_instance *vchiq_instance;\n+\tstruct vc_sm_version version;\n+\tstruct vc_sm_result_t version_result;\n+\n+\tpr_info(\"[%s]: start\\n\", __func__);\n+\n+\t/*\n+\t * Initialize and create a VCHI connection for the shared memory service\n+\t * running on videocore.\n+\t */\n+\tret = vchiq_initialise(&vchiq_instance);\n+\tif (ret) {\n+\t\tpr_err(\"[%s]: failed to initialise VCHI instance (ret=%d)\\n\",\n+\t\t       __func__, ret);\n+\n+\t\treturn;\n+\t}\n+\n+\tret = vchiq_connect(vchiq_instance);\n+\tif (ret) {\n+\t\tpr_err(\"[%s]: failed to connect VCHI instance (ret=%d)\\n\",\n+\t\t       __func__, ret);\n+\n+\t\treturn;\n+\t}\n+\n+\t/* Initialize an instance of the shared memory service. */\n+\tsm_state->sm_handle = vc_sm_cma_vchi_init(vchiq_instance, 1,\n+\t\t\t\t\t\t  vc_sm_vpu_event);\n+\tif (!sm_state->sm_handle) {\n+\t\tpr_err(\"[%s]: failed to initialize shared memory service\\n\",\n+\t\t       __func__);\n+\n+\t\treturn;\n+\t}\n+\n+\t/* Create a debug fs directory entry (root). */\n+\tsm_state->dir_root = debugfs_create_dir(VC_SM_DIR_ROOT_NAME, NULL);\n+\n+\tsm_state->dir_state.show = &vc_sm_cma_global_state_show;\n+\tsm_state->dir_state.dir_entry =\n+\t\tdebugfs_create_file(VC_SM_STATE, 0444, sm_state->dir_root,\n+\t\t\t\t    &sm_state->dir_state,\n+\t\t\t\t    &vc_sm_cma_debug_fs_fops);\n+\n+\tINIT_LIST_HEAD(&sm_state->buffer_list);\n+\n+\t/* Create a shared memory device. */\n+\tsm_state->misc_dev.minor = MISC_DYNAMIC_MINOR;\n+\tsm_state->misc_dev.name = DEVICE_NAME;\n+\tsm_state->misc_dev.fops = &vc_sm_ops;\n+\tsm_state->misc_dev.parent = NULL;\n+\t/* Temporarily set as 666 until udev rules have been sorted */\n+\tsm_state->misc_dev.mode = 0666;\n+\tret = misc_register(&sm_state->misc_dev);\n+\tif (ret) {\n+\t\tpr_err(\"vcsm-cma: failed to register misc device.\\n\");\n+\t\tgoto err_remove_debugfs;\n+\t}\n+\n+\tsm_state->data_knl = vc_sm_cma_create_priv_data(0);\n+\tif (!sm_state->data_knl) {\n+\t\tpr_err(\"[%s]: failed to create kernel private data tracker\\n\",\n+\t\t       __func__);\n+\t\tgoto err_remove_misc_dev;\n+\t}\n+\n+\tversion.version = 2;\n+\tret = vc_sm_cma_vchi_client_version(sm_state->sm_handle, &version,\n+\t\t\t\t\t    &version_result,\n+\t\t\t\t\t    &sm_state->int_trans_id);\n+\tif (ret) {\n+\t\tpr_err(\"[%s]: Failed to send version request %d\\n\", __func__,\n+\t\t       ret);\n+\t}\n+\n+\t/* Done! */\n+\tsm_inited = 1;\n+\tpr_info(\"[%s]: installed successfully\\n\", __func__);\n+\treturn;\n+\n+err_remove_misc_dev:\n+\tmisc_deregister(&sm_state->misc_dev);\n+err_remove_debugfs:\n+\tdebugfs_remove_recursive(sm_state->dir_root);\n+\tvc_sm_cma_vchi_stop(&sm_state->sm_handle);\n+}\n+\n+/* Driver loading. */\n+static int bcm2835_vc_sm_cma_probe(struct platform_device *pdev)\n+{\n+\tpr_info(\"%s: Videocore shared memory driver\\n\", __func__);\n+\n+\tsm_state = devm_kzalloc(&pdev->dev, sizeof(*sm_state), GFP_KERNEL);\n+\tif (!sm_state)\n+\t\treturn -ENOMEM;\n+\tsm_state->pdev = pdev;\n+\tmutex_init(&sm_state->map_lock);\n+\n+\tspin_lock_init(&sm_state->kernelid_map_lock);\n+\tidr_init_base(&sm_state->kernelid_map, 1);\n+\n+\tpdev->dev.dma_parms = devm_kzalloc(&pdev->dev,\n+\t\t\t\t\t   sizeof(*pdev->dev.dma_parms),\n+\t\t\t\t\t   GFP_KERNEL);\n+\t/* dma_set_max_seg_size checks if dma_parms is NULL. */\n+\tdma_set_max_seg_size(&pdev->dev, 0x3FFFFFFF);\n+\n+\tvchiq_add_connected_callback(vc_sm_connected_init);\n+\treturn 0;\n+}\n+\n+/* Driver unloading. */\n+static int bcm2835_vc_sm_cma_remove(struct platform_device *pdev)\n+{\n+\tpr_debug(\"[%s]: start\\n\", __func__);\n+\tif (sm_inited) {\n+\t\tmisc_deregister(&sm_state->misc_dev);\n+\n+\t\t/* Remove all proc entries. */\n+\t\tdebugfs_remove_recursive(sm_state->dir_root);\n+\n+\t\t/* Stop the videocore shared memory service. */\n+\t\tvc_sm_cma_vchi_stop(&sm_state->sm_handle);\n+\t}\n+\n+\tif (sm_state) {\n+\t\tidr_destroy(&sm_state->kernelid_map);\n+\n+\t\t/* Free the memory for the state structure. */\n+\t\tmutex_destroy(&sm_state->map_lock);\n+\t}\n+\n+\tpr_debug(\"[%s]: end\\n\", __func__);\n+\treturn 0;\n+}\n+\n+/* Kernel API calls */\n+/* Get an internal resource handle mapped from the external one. */\n+int vc_sm_cma_int_handle(void *handle)\n+{\n+\tstruct dma_buf *dma_buf = (struct dma_buf *)handle;\n+\tstruct vc_sm_buffer *buf;\n+\n+\t/* Validate we can work with this device. */\n+\tif (!sm_state || !handle) {\n+\t\tpr_err(\"[%s]: invalid input\\n\", __func__);\n+\t\treturn 0;\n+\t}\n+\n+\tbuf = (struct vc_sm_buffer *)dma_buf->priv;\n+\treturn buf->vc_handle;\n+}\n+EXPORT_SYMBOL_GPL(vc_sm_cma_int_handle);\n+\n+/* Free a previously allocated shared memory handle and block. */\n+int vc_sm_cma_free(void *handle)\n+{\n+\tstruct dma_buf *dma_buf = (struct dma_buf *)handle;\n+\n+\t/* Validate we can work with this device. */\n+\tif (!sm_state || !handle) {\n+\t\tpr_err(\"[%s]: invalid input\\n\", __func__);\n+\t\treturn -EPERM;\n+\t}\n+\n+\tpr_debug(\"%s: handle %p/dmabuf %p\\n\", __func__, handle, dma_buf);\n+\n+\tdma_buf_put(dma_buf);\n+\n+\treturn 0;\n+}\n+EXPORT_SYMBOL_GPL(vc_sm_cma_free);\n+\n+/* Import a dmabuf to be shared with VC. */\n+int vc_sm_cma_import_dmabuf(struct dma_buf *src_dmabuf, void **handle)\n+{\n+\tstruct dma_buf *new_dma_buf;\n+\tint ret;\n+\n+\t/* Validate we can work with this device. */\n+\tif (!sm_state || !src_dmabuf || !handle) {\n+\t\tpr_err(\"[%s]: invalid input\\n\", __func__);\n+\t\treturn -EPERM;\n+\t}\n+\n+\tret = vc_sm_cma_import_dmabuf_internal(sm_state->data_knl, src_dmabuf,\n+\t\t\t\t\t       -1, &new_dma_buf);\n+\n+\tif (!ret) {\n+\t\tpr_debug(\"%s: imported to ptr %p\\n\", __func__, new_dma_buf);\n+\n+\t\t/* Assign valid handle at this time.*/\n+\t\t*handle = new_dma_buf;\n+\t} else {\n+\t\t/*\n+\t\t * succeeded in importing the dma_buf, but then\n+\t\t * failed to look it up again. How?\n+\t\t * Release the fd again.\n+\t\t */\n+\t\tpr_err(\"%s: imported vc_sm_cma_get_buffer failed %d\\n\",\n+\t\t       __func__, ret);\n+\t}\n+\n+\treturn ret;\n+}\n+EXPORT_SYMBOL_GPL(vc_sm_cma_import_dmabuf);\n+\n+static struct platform_driver bcm2835_vcsm_cma_driver = {\n+\t.probe = bcm2835_vc_sm_cma_probe,\n+\t.remove = bcm2835_vc_sm_cma_remove,\n+\t.driver = {\n+\t\t   .name = DEVICE_NAME,\n+\t\t   .owner = THIS_MODULE,\n+\t\t   },\n+};\n+\n+module_platform_driver(bcm2835_vcsm_cma_driver);\n+\n+MODULE_AUTHOR(\"Dave Stevenson\");\n+MODULE_DESCRIPTION(\"VideoCore CMA Shared Memory Driver\");\n+MODULE_LICENSE(\"GPL v2\");\n+MODULE_ALIAS(\"platform:vcsm-cma\");\n--- /dev/null\n+++ b/drivers/staging/vc04_services/vc-sm-cma/vc_sm.h\n@@ -0,0 +1,84 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+\n+/*\n+ * VideoCore Shared Memory driver using CMA.\n+ *\n+ * Copyright: 2018, Raspberry Pi (Trading) Ltd\n+ *\n+ */\n+\n+#ifndef VC_SM_H\n+#define VC_SM_H\n+\n+#include <linux/device.h>\n+#include <linux/dma-direction.h>\n+#include <linux/kref.h>\n+#include <linux/mm_types.h>\n+#include <linux/mutex.h>\n+#include <linux/rbtree.h>\n+#include <linux/sched.h>\n+#include <linux/shrinker.h>\n+#include <linux/types.h>\n+#include <linux/miscdevice.h>\n+\n+#define VC_SM_MAX_NAME_LEN 32\n+\n+enum vc_sm_vpu_mapping_state {\n+\tVPU_NOT_MAPPED,\n+\tVPU_MAPPED,\n+\tVPU_UNMAPPING\n+};\n+\n+struct vc_sm_alloc_data {\n+\tunsigned long num_pages;\n+\tvoid *priv_virt;\n+\tstruct sg_table *sg_table;\n+};\n+\n+struct vc_sm_imported {\n+\tstruct dma_buf *dma_buf;\n+\tstruct dma_buf_attachment *attach;\n+\tstruct sg_table *sgt;\n+};\n+\n+struct vc_sm_buffer {\n+\tstruct list_head global_buffer_list;\t/* Global list of buffers. */\n+\n+\t/* Index in the kernel_id idr so that we can find the\n+\t * mmal_msg_context again when servicing the VCHI reply.\n+\t */\n+\tint kernel_id;\n+\n+\tsize_t size;\n+\n+\t/* Lock over all the following state for this buffer */\n+\tstruct mutex lock;\n+\tstruct list_head attachments;\n+\n+\tchar name[VC_SM_MAX_NAME_LEN];\n+\n+\tint in_use:1;\t/* Kernel is still using this resource */\n+\tint imported:1;\t/* Imported dmabuf */\n+\n+\tenum vc_sm_vpu_mapping_state vpu_state;\n+\tu32 vc_handle;\t/* VideoCore handle for this buffer */\n+\tint vpu_allocated;\t/*\n+\t\t\t\t * The VPU made this allocation. Release the\n+\t\t\t\t * local dma_buf when the VPU releases the\n+\t\t\t\t * resource.\n+\t\t\t\t */\n+\n+\t/* DMABUF related fields */\n+\tstruct dma_buf *dma_buf;\n+\tdma_addr_t dma_addr;\n+\tvoid *cookie;\n+\n+\tstruct vc_sm_privdata_t *private;\n+\n+\tunion {\n+\t\tstruct vc_sm_alloc_data alloc;\n+\t\tstruct vc_sm_imported import;\n+\t};\n+};\n+\n+#endif\n--- /dev/null\n+++ b/drivers/staging/vc04_services/vc-sm-cma/vc_sm_cma_vchi.c\n@@ -0,0 +1,503 @@\n+// SPDX-License-Identifier: GPL-2.0\n+/*\n+ * VideoCore Shared Memory CMA allocator\n+ *\n+ * Copyright: 2018, Raspberry Pi (Trading) Ltd\n+ * Copyright 2011-2012 Broadcom Corporation.  All rights reserved.\n+ *\n+ * Based on vmcs_sm driver from Broadcom Corporation.\n+ *\n+ */\n+\n+/* ---- Include Files ----------------------------------------------------- */\n+#include <linux/completion.h>\n+#include <linux/kernel.h>\n+#include <linux/kthread.h>\n+#include <linux/list.h>\n+#include <linux/mutex.h>\n+#include <linux/semaphore.h>\n+#include <linux/slab.h>\n+#include <linux/types.h>\n+\n+#include \"vc_sm_cma_vchi.h\"\n+\n+#define VC_SM_VER  1\n+#define VC_SM_MIN_VER 0\n+\n+/* ---- Private Constants and Types -------------------------------------- */\n+\n+/* Command blocks come from a pool */\n+#define SM_MAX_NUM_CMD_RSP_BLKS 32\n+\n+/* The number of supported connections */\n+#define SM_MAX_NUM_CONNECTIONS 3\n+\n+struct sm_cmd_rsp_blk {\n+\tstruct list_head head;\t/* To create lists */\n+\t/* To be signaled when the response is there */\n+\tstruct completion cmplt;\n+\n+\tu32 id;\n+\tu16 length;\n+\n+\tu8 msg[VC_SM_MAX_MSG_LEN];\n+\n+\tuint32_t wait:1;\n+\tuint32_t sent:1;\n+\tuint32_t alloc:1;\n+\n+};\n+\n+struct sm_instance {\n+\tu32 num_connections;\n+\tunsigned int service_handle[SM_MAX_NUM_CONNECTIONS];\n+\tstruct task_struct *io_thread;\n+\tstruct completion io_cmplt;\n+\n+\tvpu_event_cb vpu_event;\n+\n+\t/* Mutex over the following lists */\n+\tstruct mutex lock;\n+\tu32 trans_id;\n+\tstruct list_head cmd_list;\n+\tstruct list_head rsp_list;\n+\tstruct list_head dead_list;\n+\n+\tstruct sm_cmd_rsp_blk free_blk[SM_MAX_NUM_CMD_RSP_BLKS];\n+\n+\t/* Mutex over the free_list */\n+\tstruct mutex free_lock;\n+\tstruct list_head free_list;\n+\n+\tstruct semaphore free_sema;\n+\n+};\n+\n+/* ---- Private Variables ------------------------------------------------ */\n+\n+/* ---- Private Function Prototypes -------------------------------------- */\n+\n+/* ---- Private Functions ------------------------------------------------ */\n+static int\n+bcm2835_vchi_msg_queue(unsigned int handle,\n+\t\t       void *data,\n+\t\t       unsigned int size)\n+{\n+\treturn vchiq_queue_kernel_message(handle, data, size);\n+}\n+\n+static struct\n+sm_cmd_rsp_blk *vc_vchi_cmd_create(struct sm_instance *instance,\n+\t\t\t\t   enum vc_sm_msg_type id, void *msg,\n+\t\t\t\t   u32 size, int wait)\n+{\n+\tstruct sm_cmd_rsp_blk *blk;\n+\tstruct vc_sm_msg_hdr_t *hdr;\n+\n+\tif (down_interruptible(&instance->free_sema)) {\n+\t\tblk = kmalloc(sizeof(*blk), GFP_KERNEL);\n+\t\tif (!blk)\n+\t\t\treturn NULL;\n+\n+\t\tblk->alloc = 1;\n+\t\tinit_completion(&blk->cmplt);\n+\t} else {\n+\t\tmutex_lock(&instance->free_lock);\n+\t\tblk =\n+\t\t    list_first_entry(&instance->free_list,\n+\t\t\t\t     struct sm_cmd_rsp_blk, head);\n+\t\tlist_del(&blk->head);\n+\t\tmutex_unlock(&instance->free_lock);\n+\t}\n+\n+\tblk->sent = 0;\n+\tblk->wait = wait;\n+\tblk->length = sizeof(*hdr) + size;\n+\n+\thdr = (struct vc_sm_msg_hdr_t *)blk->msg;\n+\thdr->type = id;\n+\tmutex_lock(&instance->lock);\n+\tinstance->trans_id++;\n+\t/*\n+\t * Retain the top bit for identifying asynchronous events, or VPU cmds.\n+\t */\n+\tinstance->trans_id &= ~0x80000000;\n+\thdr->trans_id = instance->trans_id;\n+\tblk->id = instance->trans_id;\n+\tmutex_unlock(&instance->lock);\n+\n+\tif (size)\n+\t\tmemcpy(hdr->body, msg, size);\n+\n+\treturn blk;\n+}\n+\n+static void\n+vc_vchi_cmd_delete(struct sm_instance *instance, struct sm_cmd_rsp_blk *blk)\n+{\n+\tif (blk->alloc) {\n+\t\tkfree(blk);\n+\t\treturn;\n+\t}\n+\n+\tmutex_lock(&instance->free_lock);\n+\tlist_add(&blk->head, &instance->free_list);\n+\tmutex_unlock(&instance->free_lock);\n+\tup(&instance->free_sema);\n+}\n+\n+static void vc_sm_cma_vchi_rx_ack(struct sm_instance *instance,\n+\t\t\t\t  struct sm_cmd_rsp_blk *cmd,\n+\t\t\t\t  struct vc_sm_result_t *reply,\n+\t\t\t\t  u32 reply_len)\n+{\n+\tmutex_lock(&instance->lock);\n+\tlist_for_each_entry(cmd,\n+\t\t\t    &instance->rsp_list,\n+\t\t\t    head) {\n+\t\tif (cmd->id == reply->trans_id)\n+\t\t\tbreak;\n+\t}\n+\tmutex_unlock(&instance->lock);\n+\n+\tif (&cmd->head == &instance->rsp_list) {\n+\t\t//pr_debug(\"%s: received response %u, throw away...\",\n+\t\tpr_err(\"%s: received response %u, throw away...\",\n+\t\t       __func__,\n+\t\t       reply->trans_id);\n+\t} else if (reply_len > sizeof(cmd->msg)) {\n+\t\tpr_err(\"%s: reply too big (%u) %u, throw away...\",\n+\t\t       __func__, reply_len,\n+\t\t     reply->trans_id);\n+\t} else {\n+\t\tmemcpy(cmd->msg, reply,\n+\t\t       reply_len);\n+\t\tcomplete(&cmd->cmplt);\n+\t}\n+}\n+\n+static int vc_sm_cma_vchi_videocore_io(void *arg)\n+{\n+\tstruct sm_instance *instance = arg;\n+\tstruct sm_cmd_rsp_blk *cmd = NULL, *cmd_tmp;\n+\tstruct vc_sm_result_t *reply;\n+\tstruct vchiq_header *header;\n+\ts32 status;\n+\tint svc_use = 1;\n+\n+\twhile (1) {\n+\t\tif (svc_use)\n+\t\t\tvchiq_release_service(instance->service_handle[0]);\n+\t\tsvc_use = 0;\n+\n+\t\tif (wait_for_completion_interruptible(&instance->io_cmplt))\n+\t\t\tcontinue;\n+\t\tvchiq_use_service(instance->service_handle[0]);\n+\t\tsvc_use = 1;\n+\n+\t\tdo {\n+\t\t\t/*\n+\t\t\t * Get new command and move it to response list\n+\t\t\t */\n+\t\t\tmutex_lock(&instance->lock);\n+\t\t\tif (list_empty(&instance->cmd_list)) {\n+\t\t\t\t/* no more commands to process */\n+\t\t\t\tmutex_unlock(&instance->lock);\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t\tcmd = list_first_entry(&instance->cmd_list,\n+\t\t\t\t\t       struct sm_cmd_rsp_blk, head);\n+\t\t\tlist_move(&cmd->head, &instance->rsp_list);\n+\t\t\tcmd->sent = 1;\n+\t\t\tmutex_unlock(&instance->lock);\n+\t\t\t/* Send the command */\n+\t\t\tstatus =\n+\t\t\t\tbcm2835_vchi_msg_queue(instance->service_handle[0],\n+\t\t\t\t\t\t       cmd->msg, cmd->length);\n+\t\t\tif (status) {\n+\t\t\t\tpr_err(\"%s: failed to queue message (%d)\",\n+\t\t\t\t       __func__, status);\n+\t\t\t}\n+\n+\t\t\t/* If no reply is needed then we're done */\n+\t\t\tif (!cmd->wait) {\n+\t\t\t\tmutex_lock(&instance->lock);\n+\t\t\t\tlist_del(&cmd->head);\n+\t\t\t\tmutex_unlock(&instance->lock);\n+\t\t\t\tvc_vchi_cmd_delete(instance, cmd);\n+\t\t\t\tcontinue;\n+\t\t\t}\n+\n+\t\t\tif (status) {\n+\t\t\t\tcomplete(&cmd->cmplt);\n+\t\t\t\tcontinue;\n+\t\t\t}\n+\n+\t\t} while (1);\n+\n+\t\twhile ((header = vchiq_msg_hold(instance->service_handle[0]))) {\n+\t\t\treply = (struct vc_sm_result_t *)header->data;\n+\t\t\tif (reply->trans_id & 0x80000000) {\n+\t\t\t\t/* Async event or cmd from the VPU */\n+\t\t\t\tif (instance->vpu_event)\n+\t\t\t\t\tinstance->vpu_event(instance, reply,\n+\t\t\t\t\t\t\t    header->size);\n+\t\t\t} else {\n+\t\t\t\tvc_sm_cma_vchi_rx_ack(instance, cmd, reply,\n+\t\t\t\t\t\t      header->size);\n+\t\t\t}\n+\n+\t\t\tvchiq_release_message(instance->service_handle[0],\n+\t\t\t\t\t      header);\n+\t\t}\n+\n+\t\t/* Go through the dead list and free them */\n+\t\tmutex_lock(&instance->lock);\n+\t\tlist_for_each_entry_safe(cmd, cmd_tmp, &instance->dead_list,\n+\t\t\t\t\t head) {\n+\t\t\tlist_del(&cmd->head);\n+\t\t\tvc_vchi_cmd_delete(instance, cmd);\n+\t\t}\n+\t\tmutex_unlock(&instance->lock);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static enum vchiq_status vc_sm_cma_vchi_callback(enum vchiq_reason reason,\n+\t\t\t\t\t\t struct vchiq_header *header,\n+\t\t\t\t\t\t unsigned int handle, void *userdata)\n+{\n+\tstruct sm_instance *instance = vchiq_get_service_userdata(handle);\n+\n+\tswitch (reason) {\n+\tcase VCHIQ_MESSAGE_AVAILABLE:\n+\t\tvchiq_msg_queue_push(handle, header);\n+\t\tcomplete(&instance->io_cmplt);\n+\t\tbreak;\n+\n+\tcase VCHIQ_SERVICE_CLOSED:\n+\t\tpr_info(\"%s: service CLOSED!!\", __func__);\n+\tdefault:\n+\t\tbreak;\n+\t}\n+\n+\treturn VCHIQ_SUCCESS;\n+}\n+\n+struct sm_instance *vc_sm_cma_vchi_init(struct vchiq_instance *vchiq_instance,\n+\t\t\t\t\tunsigned int num_connections,\n+\t\t\t\t\tvpu_event_cb vpu_event)\n+{\n+\tu32 i;\n+\tstruct sm_instance *instance;\n+\tint status;\n+\n+\tpr_debug(\"%s: start\", __func__);\n+\n+\tif (num_connections > SM_MAX_NUM_CONNECTIONS) {\n+\t\tpr_err(\"%s: unsupported number of connections %u (max=%u)\",\n+\t\t       __func__, num_connections, SM_MAX_NUM_CONNECTIONS);\n+\n+\t\tgoto err_null;\n+\t}\n+\t/* Allocate memory for this instance */\n+\tinstance = kzalloc(sizeof(*instance), GFP_KERNEL);\n+\n+\t/* Misc initialisations */\n+\tmutex_init(&instance->lock);\n+\tinit_completion(&instance->io_cmplt);\n+\tINIT_LIST_HEAD(&instance->cmd_list);\n+\tINIT_LIST_HEAD(&instance->rsp_list);\n+\tINIT_LIST_HEAD(&instance->dead_list);\n+\tINIT_LIST_HEAD(&instance->free_list);\n+\tsema_init(&instance->free_sema, SM_MAX_NUM_CMD_RSP_BLKS);\n+\tmutex_init(&instance->free_lock);\n+\tfor (i = 0; i < SM_MAX_NUM_CMD_RSP_BLKS; i++) {\n+\t\tinit_completion(&instance->free_blk[i].cmplt);\n+\t\tlist_add(&instance->free_blk[i].head, &instance->free_list);\n+\t}\n+\n+\t/* Open the VCHI service connections */\n+\tinstance->num_connections = num_connections;\n+\tfor (i = 0; i < num_connections; i++) {\n+\t\tstruct vchiq_service_params_kernel params = {\n+\t\t\t.version = VC_SM_VER,\n+\t\t\t.version_min = VC_SM_MIN_VER,\n+\t\t\t.fourcc = VCHIQ_MAKE_FOURCC('S', 'M', 'E', 'M'),\n+\t\t\t.callback = vc_sm_cma_vchi_callback,\n+\t\t\t.userdata = instance,\n+\t\t};\n+\n+\t\tstatus = vchiq_open_service(vchiq_instance, &params,\n+\t\t\t\t\t    &instance->service_handle[i]);\n+\t\tif (status) {\n+\t\t\tpr_err(\"%s: failed to open VCHI service (%d)\",\n+\t\t\t       __func__, status);\n+\n+\t\t\tgoto err_close_services;\n+\t\t}\n+\t}\n+\t/* Create the thread which takes care of all io to/from videoocore. */\n+\tinstance->io_thread = kthread_create(&vc_sm_cma_vchi_videocore_io,\n+\t\t\t\t\t     (void *)instance, \"SMIO\");\n+\tif (!instance->io_thread) {\n+\t\tpr_err(\"%s: failed to create SMIO thread\", __func__);\n+\n+\t\tgoto err_close_services;\n+\t}\n+\tinstance->vpu_event = vpu_event;\n+\tset_user_nice(instance->io_thread, -10);\n+\twake_up_process(instance->io_thread);\n+\n+\tpr_debug(\"%s: success - instance %p\", __func__, instance);\n+\treturn instance;\n+\n+err_close_services:\n+\tfor (i = 0; i < instance->num_connections; i++) {\n+\t\tif (instance->service_handle[i])\n+\t\t\tvchiq_close_service(instance->service_handle[i]);\n+\t}\n+\tkfree(instance);\n+err_null:\n+\tpr_debug(\"%s: FAILED\", __func__);\n+\treturn NULL;\n+}\n+\n+int vc_sm_cma_vchi_stop(struct sm_instance **handle)\n+{\n+\tstruct sm_instance *instance;\n+\tu32 i;\n+\n+\tif (!handle) {\n+\t\tpr_err(\"%s: invalid pointer to handle %p\", __func__, handle);\n+\t\tgoto lock;\n+\t}\n+\n+\tif (!*handle) {\n+\t\tpr_err(\"%s: invalid handle %p\", __func__, *handle);\n+\t\tgoto lock;\n+\t}\n+\n+\tinstance = *handle;\n+\n+\t/* Close all VCHI service connections */\n+\tfor (i = 0; i < instance->num_connections; i++) {\n+\t\tvchiq_use_service(instance->service_handle[i]);\n+\t\tvchiq_close_service(instance->service_handle[i]);\n+\t}\n+\n+\tkfree(instance);\n+\n+\t*handle = NULL;\n+\treturn 0;\n+\n+lock:\n+\treturn -EINVAL;\n+}\n+\n+static int vc_sm_cma_vchi_send_msg(struct sm_instance *handle,\n+\t\t\t\t   enum vc_sm_msg_type msg_id, void *msg,\n+\t\t\t\t   u32 msg_size, void *result, u32 result_size,\n+\t\t\t\t   u32 *cur_trans_id, u8 wait_reply)\n+{\n+\tint status = 0;\n+\tstruct sm_instance *instance = handle;\n+\tstruct sm_cmd_rsp_blk *cmd_blk;\n+\n+\tif (!handle) {\n+\t\tpr_err(\"%s: invalid handle\", __func__);\n+\t\treturn -EINVAL;\n+\t}\n+\tif (!msg) {\n+\t\tpr_err(\"%s: invalid msg pointer\", __func__);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tcmd_blk =\n+\t    vc_vchi_cmd_create(instance, msg_id, msg, msg_size, wait_reply);\n+\tif (!cmd_blk) {\n+\t\tpr_err(\"[%s]: failed to allocate global tracking resource\",\n+\t\t       __func__);\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\tif (cur_trans_id)\n+\t\t*cur_trans_id = cmd_blk->id;\n+\n+\tmutex_lock(&instance->lock);\n+\tlist_add_tail(&cmd_blk->head, &instance->cmd_list);\n+\tmutex_unlock(&instance->lock);\n+\tcomplete(&instance->io_cmplt);\n+\n+\tif (!wait_reply)\n+\t\t/* We're done */\n+\t\treturn 0;\n+\n+\t/* Wait for the response */\n+\tif (wait_for_completion_interruptible(&cmd_blk->cmplt)) {\n+\t\tmutex_lock(&instance->lock);\n+\t\tif (!cmd_blk->sent) {\n+\t\t\tlist_del(&cmd_blk->head);\n+\t\t\tmutex_unlock(&instance->lock);\n+\t\t\tvc_vchi_cmd_delete(instance, cmd_blk);\n+\t\t\treturn -ENXIO;\n+\t\t}\n+\n+\t\tlist_move(&cmd_blk->head, &instance->dead_list);\n+\t\tmutex_unlock(&instance->lock);\n+\t\tcomplete(&instance->io_cmplt);\n+\t\treturn -EINTR;\t/* We're done */\n+\t}\n+\n+\tif (result && result_size) {\n+\t\tmemcpy(result, cmd_blk->msg, result_size);\n+\t} else {\n+\t\tstruct vc_sm_result_t *res =\n+\t\t\t(struct vc_sm_result_t *)cmd_blk->msg;\n+\t\tstatus = (res->success == 0) ? 0 : -ENXIO;\n+\t}\n+\n+\tmutex_lock(&instance->lock);\n+\tlist_del(&cmd_blk->head);\n+\tmutex_unlock(&instance->lock);\n+\tvc_vchi_cmd_delete(instance, cmd_blk);\n+\treturn status;\n+}\n+\n+int vc_sm_cma_vchi_free(struct sm_instance *handle, struct vc_sm_free_t *msg,\n+\t\t\tu32 *cur_trans_id)\n+{\n+\treturn vc_sm_cma_vchi_send_msg(handle, VC_SM_MSG_TYPE_FREE,\n+\t\t\t\t   msg, sizeof(*msg), 0, 0, cur_trans_id, 0);\n+}\n+\n+int vc_sm_cma_vchi_import(struct sm_instance *handle, struct vc_sm_import *msg,\n+\t\t\t  struct vc_sm_import_result *result, u32 *cur_trans_id)\n+{\n+\treturn vc_sm_cma_vchi_send_msg(handle, VC_SM_MSG_TYPE_IMPORT,\n+\t\t\t\t   msg, sizeof(*msg), result, sizeof(*result),\n+\t\t\t\t   cur_trans_id, 1);\n+}\n+\n+int vc_sm_cma_vchi_client_version(struct sm_instance *handle,\n+\t\t\t\t  struct vc_sm_version *msg,\n+\t\t\t\t  struct vc_sm_result_t *result,\n+\t\t\t\t  u32 *cur_trans_id)\n+{\n+\treturn vc_sm_cma_vchi_send_msg(handle, VC_SM_MSG_TYPE_CLIENT_VERSION,\n+\t\t\t\t   //msg, sizeof(*msg), result, sizeof(*result),\n+\t\t\t\t   //cur_trans_id, 1);\n+\t\t\t\t   msg, sizeof(*msg), NULL, 0,\n+\t\t\t\t   cur_trans_id, 0);\n+}\n+\n+int vc_sm_vchi_client_vc_mem_req_reply(struct sm_instance *handle,\n+\t\t\t\t       struct vc_sm_vc_mem_request_result *msg,\n+\t\t\t\t       uint32_t *cur_trans_id)\n+{\n+\treturn vc_sm_cma_vchi_send_msg(handle,\n+\t\t\t\t       VC_SM_MSG_TYPE_VC_MEM_REQUEST_REPLY,\n+\t\t\t\t       msg, sizeof(*msg), 0, 0, cur_trans_id,\n+\t\t\t\t       0);\n+}\n--- /dev/null\n+++ b/drivers/staging/vc04_services/vc-sm-cma/vc_sm_cma_vchi.h\n@@ -0,0 +1,63 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+\n+/*\n+ * VideoCore Shared Memory CMA allocator\n+ *\n+ * Copyright: 2018, Raspberry Pi (Trading) Ltd\n+ * Copyright 2011-2012 Broadcom Corporation.  All rights reserved.\n+ *\n+ * Based on vmcs_sm driver from Broadcom Corporation.\n+ *\n+ */\n+\n+#ifndef __VC_SM_CMA_VCHI_H__INCLUDED__\n+#define __VC_SM_CMA_VCHI_H__INCLUDED__\n+\n+#include <linux/raspberrypi/vchiq.h>\n+\n+#include \"vc_sm_defs.h\"\n+\n+/*\n+ * Forward declare.\n+ */\n+struct sm_instance;\n+\n+typedef void (*vpu_event_cb)(struct sm_instance *instance,\n+\t\t\t     struct vc_sm_result_t *reply, int reply_len);\n+\n+/*\n+ * Initialize the shared memory service, opens up vchi connection to talk to it.\n+ */\n+struct sm_instance *vc_sm_cma_vchi_init(struct vchiq_instance *vchi_instance,\n+\t\t\t\t\tunsigned int num_connections,\n+\t\t\t\t\tvpu_event_cb vpu_event);\n+\n+/*\n+ * Terminates the shared memory service.\n+ */\n+int vc_sm_cma_vchi_stop(struct sm_instance **handle);\n+\n+/*\n+ * Ask the shared memory service to free up some memory that was previously\n+ * allocated by the vc_sm_cma_vchi_alloc function call.\n+ */\n+int vc_sm_cma_vchi_free(struct sm_instance *handle, struct vc_sm_free_t *msg,\n+\t\t\tu32 *cur_trans_id);\n+\n+/*\n+ * Import a contiguous block of memory and wrap it in a GPU MEM_HANDLE_T.\n+ */\n+int vc_sm_cma_vchi_import(struct sm_instance *handle, struct vc_sm_import *msg,\n+\t\t\t  struct vc_sm_import_result *result,\n+\t\t\t  u32 *cur_trans_id);\n+\n+int vc_sm_cma_vchi_client_version(struct sm_instance *handle,\n+\t\t\t\t  struct vc_sm_version *msg,\n+\t\t\t\t  struct vc_sm_result_t *result,\n+\t\t\t\t  u32 *cur_trans_id);\n+\n+int vc_sm_vchi_client_vc_mem_req_reply(struct sm_instance *handle,\n+\t\t\t\t       struct vc_sm_vc_mem_request_result *msg,\n+\t\t\t\t       uint32_t *cur_trans_id);\n+\n+#endif /* __VC_SM_CMA_VCHI_H__INCLUDED__ */\n--- /dev/null\n+++ b/drivers/staging/vc04_services/vc-sm-cma/vc_sm_defs.h\n@@ -0,0 +1,297 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+\n+/*\n+ * VideoCore Shared Memory CMA allocator\n+ *\n+ * Copyright: 2018, Raspberry Pi (Trading) Ltd\n+ *\n+ * Based on vc_sm_defs.h from the vmcs_sm driver Copyright Broadcom Corporation.\n+ * All IPC messages are copied across to this file, even if the vc-sm-cma\n+ * driver is not currently using them.\n+ *\n+ ****************************************************************************\n+ */\n+\n+#ifndef __VC_SM_DEFS_H__INCLUDED__\n+#define __VC_SM_DEFS_H__INCLUDED__\n+\n+/* Maximum message length */\n+#define VC_SM_MAX_MSG_LEN (sizeof(union vc_sm_msg_union_t) + \\\n+\tsizeof(struct vc_sm_msg_hdr_t))\n+#define VC_SM_MAX_RSP_LEN (sizeof(union vc_sm_msg_union_t))\n+\n+/* Resource name maximum size */\n+#define VC_SM_RESOURCE_NAME 32\n+\n+/*\n+ * Version to be reported to the VPU\n+ * VPU assumes 0 (aka 1) which does not require the released callback, nor\n+ * expect the client to handle VC_MEM_REQUESTS.\n+ * Version 2 requires the released callback, and must support VC_MEM_REQUESTS.\n+ */\n+#define VC_SM_PROTOCOL_VERSION\t2\n+\n+enum vc_sm_msg_type {\n+\t/* Message types supported for HOST->VC direction */\n+\n+\t/* Allocate shared memory block */\n+\tVC_SM_MSG_TYPE_ALLOC,\n+\t/* Lock allocated shared memory block */\n+\tVC_SM_MSG_TYPE_LOCK,\n+\t/* Unlock allocated shared memory block */\n+\tVC_SM_MSG_TYPE_UNLOCK,\n+\t/* Unlock allocated shared memory block, do not answer command */\n+\tVC_SM_MSG_TYPE_UNLOCK_NOANS,\n+\t/* Free shared memory block */\n+\tVC_SM_MSG_TYPE_FREE,\n+\t/* Resize a shared memory block */\n+\tVC_SM_MSG_TYPE_RESIZE,\n+\t/* Walk the allocated shared memory block(s) */\n+\tVC_SM_MSG_TYPE_WALK_ALLOC,\n+\n+\t/* A previously applied action will need to be reverted */\n+\tVC_SM_MSG_TYPE_ACTION_CLEAN,\n+\n+\t/*\n+\t * Import a physical address and wrap into a MEM_HANDLE_T.\n+\t * Release with VC_SM_MSG_TYPE_FREE.\n+\t */\n+\tVC_SM_MSG_TYPE_IMPORT,\n+\t/*\n+\t *Tells VC the protocol version supported by this client.\n+\t * 2 supports the async/cmd messages from the VPU for final release\n+\t * of memory, and for VC allocations.\n+\t */\n+\tVC_SM_MSG_TYPE_CLIENT_VERSION,\n+\t/* Response to VC request for memory */\n+\tVC_SM_MSG_TYPE_VC_MEM_REQUEST_REPLY,\n+\n+\t/*\n+\t * Asynchronous/cmd messages supported for VC->HOST direction.\n+\t * Signalled by setting the top bit in vc_sm_result_t trans_id.\n+\t */\n+\n+\t/*\n+\t * VC has finished with an imported memory allocation.\n+\t * Release any Linux reference counts on the underlying block.\n+\t */\n+\tVC_SM_MSG_TYPE_RELEASED,\n+\t/* VC request for memory */\n+\tVC_SM_MSG_TYPE_VC_MEM_REQUEST,\n+\n+\tVC_SM_MSG_TYPE_MAX\n+};\n+\n+/* Type of memory to be allocated */\n+enum vc_sm_alloc_type_t {\n+\tVC_SM_ALLOC_CACHED,\n+\tVC_SM_ALLOC_NON_CACHED,\n+};\n+\n+/* Message header for all messages in HOST->VC direction */\n+struct vc_sm_msg_hdr_t {\n+\tu32 type;\n+\tu32 trans_id;\n+\tu8 body[0];\n+\n+};\n+\n+/* Request to allocate memory (HOST->VC) */\n+struct vc_sm_alloc_t {\n+\t/* type of memory to allocate */\n+\tenum vc_sm_alloc_type_t type;\n+\t/* byte amount of data to allocate per unit */\n+\tu32 base_unit;\n+\t/* number of unit to allocate */\n+\tu32 num_unit;\n+\t/* alignment to be applied on allocation */\n+\tu32 alignment;\n+\t/* identity of who allocated this block */\n+\tu32 allocator;\n+\t/* resource name (for easier tracking on vc side) */\n+\tchar name[VC_SM_RESOURCE_NAME];\n+\n+};\n+\n+/* Result of a requested memory allocation (VC->HOST) */\n+struct vc_sm_alloc_result_t {\n+\t/* Transaction identifier */\n+\tu32 trans_id;\n+\n+\t/* Resource handle */\n+\tu32 res_handle;\n+\t/* Pointer to resource buffer */\n+\tu32 res_mem;\n+\t/* Resource base size (bytes) */\n+\tu32 res_base_size;\n+\t/* Resource number */\n+\tu32 res_num;\n+\n+};\n+\n+/* Request to free a previously allocated memory (HOST->VC) */\n+struct vc_sm_free_t {\n+\t/* Resource handle (returned from alloc) */\n+\tu32 res_handle;\n+\t/* Resource buffer (returned from alloc) */\n+\tu32 res_mem;\n+\n+};\n+\n+/* Request to lock a previously allocated memory (HOST->VC) */\n+struct vc_sm_lock_unlock_t {\n+\t/* Resource handle (returned from alloc) */\n+\tu32 res_handle;\n+\t/* Resource buffer (returned from alloc) */\n+\tu32 res_mem;\n+\n+};\n+\n+/* Request to resize a previously allocated memory (HOST->VC) */\n+struct vc_sm_resize_t {\n+\t/* Resource handle (returned from alloc) */\n+\tu32 res_handle;\n+\t/* Resource buffer (returned from alloc) */\n+\tu32 res_mem;\n+\t/* Resource *new* size requested (bytes) */\n+\tu32 res_new_size;\n+\n+};\n+\n+/* Result of a requested memory lock (VC->HOST) */\n+struct vc_sm_lock_result_t {\n+\t/* Transaction identifier */\n+\tu32 trans_id;\n+\n+\t/* Resource handle */\n+\tu32 res_handle;\n+\t/* Pointer to resource buffer */\n+\tu32 res_mem;\n+\t/*\n+\t * Pointer to former resource buffer if the memory\n+\t * was reallocated\n+\t */\n+\tu32 res_old_mem;\n+\n+};\n+\n+/* Generic result for a request (VC->HOST) */\n+struct vc_sm_result_t {\n+\t/* Transaction identifier */\n+\tu32 trans_id;\n+\n+\ts32 success;\n+\n+};\n+\n+/* Request to revert a previously applied action (HOST->VC) */\n+struct vc_sm_action_clean_t {\n+\t/* Action of interest */\n+\tenum vc_sm_msg_type res_action;\n+\t/* Transaction identifier for the action of interest */\n+\tu32 action_trans_id;\n+\n+};\n+\n+/* Request to remove all data associated with a given allocator (HOST->VC) */\n+struct vc_sm_free_all_t {\n+\t/* Allocator identifier */\n+\tu32 allocator;\n+};\n+\n+/* Request to import memory (HOST->VC) */\n+struct vc_sm_import {\n+\t/* type of memory to allocate */\n+\tenum vc_sm_alloc_type_t type;\n+\t/* pointer to the VC (ie physical) address of the allocated memory */\n+\tu32 addr;\n+\t/* size of buffer */\n+\tu32 size;\n+\t/* opaque handle returned in RELEASED messages */\n+\tu32 kernel_id;\n+\t/* Allocator identifier */\n+\tu32 allocator;\n+\t/* resource name (for easier tracking on vc side) */\n+\tchar     name[VC_SM_RESOURCE_NAME];\n+};\n+\n+/* Result of a requested memory import (VC->HOST) */\n+struct vc_sm_import_result {\n+\t/* Transaction identifier */\n+\tu32 trans_id;\n+\n+\t/* Resource handle */\n+\tu32 res_handle;\n+};\n+\n+/* Notification that VC has finished with an allocation (VC->HOST) */\n+struct vc_sm_released {\n+\t/* cmd type / trans_id */\n+\tu32 cmd;\n+\n+\t/* pointer to the VC (ie physical) address of the allocated memory */\n+\tu32 addr;\n+\t/* size of buffer */\n+\tu32 size;\n+\t/* opaque handle returned in RELEASED messages */\n+\tu32 kernel_id;\n+\tu32 vc_handle;\n+};\n+\n+/*\n+ * Client informing VC as to the protocol version it supports.\n+ * >=2 requires the released callback, and supports VC asking for memory.\n+ * Failure means that the firmware doesn't support this call, and therefore the\n+ * client should either fail, or NOT rely on getting the released callback.\n+ */\n+struct vc_sm_version {\n+\tu32 version;\n+};\n+\n+/* Request FROM VideoCore for some memory */\n+struct vc_sm_vc_mem_request {\n+\t/* cmd type */\n+\tu32 cmd;\n+\n+\t/* trans_id (from VPU) */\n+\tu32 trans_id;\n+\t/* size of buffer */\n+\tu32 size;\n+\t/* alignment of buffer */\n+\tu32 align;\n+\t/* resource name (for easier tracking) */\n+\tchar     name[VC_SM_RESOURCE_NAME];\n+\t/* VPU handle for the resource */\n+\tu32 vc_handle;\n+};\n+\n+/* Response from the kernel to provide the VPU with some memory */\n+struct vc_sm_vc_mem_request_result {\n+\t/* Transaction identifier for the VPU */\n+\tu32 trans_id;\n+\t/* pointer to the physical address of the allocated memory */\n+\tu32 addr;\n+\t/* opaque handle returned in RELEASED messages */\n+\tu32 kernel_id;\n+};\n+\n+/* Union of ALL messages */\n+union vc_sm_msg_union_t {\n+\tstruct vc_sm_alloc_t alloc;\n+\tstruct vc_sm_alloc_result_t alloc_result;\n+\tstruct vc_sm_free_t free;\n+\tstruct vc_sm_lock_unlock_t lock_unlock;\n+\tstruct vc_sm_action_clean_t action_clean;\n+\tstruct vc_sm_resize_t resize;\n+\tstruct vc_sm_lock_result_t lock_result;\n+\tstruct vc_sm_result_t result;\n+\tstruct vc_sm_free_all_t free_all;\n+\tstruct vc_sm_import import;\n+\tstruct vc_sm_import_result import_result;\n+\tstruct vc_sm_version version;\n+\tstruct vc_sm_released released;\n+\tstruct vc_sm_vc_mem_request vc_request;\n+\tstruct vc_sm_vc_mem_request_result vc_request_result;\n+};\n+\n+#endif /* __VC_SM_DEFS_H__INCLUDED__ */\n--- /dev/null\n+++ b/drivers/staging/vc04_services/vc-sm-cma/vc_sm_knl.h\n@@ -0,0 +1,28 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+\n+/*\n+ * VideoCore Shared Memory CMA allocator\n+ *\n+ * Copyright: 2018, Raspberry Pi (Trading) Ltd\n+ *\n+ * Based on vc_sm_defs.h from the vmcs_sm driver Copyright Broadcom Corporation.\n+ *\n+ */\n+\n+#ifndef __VC_SM_KNL_H__INCLUDED__\n+#define __VC_SM_KNL_H__INCLUDED__\n+\n+#if !defined(__KERNEL__)\n+#error \"This interface is for kernel use only...\"\n+#endif\n+\n+/* Free a previously allocated or imported shared memory handle and block. */\n+int vc_sm_cma_free(void *handle);\n+\n+/* Get an internal resource handle mapped from the external one. */\n+int vc_sm_cma_int_handle(void *handle);\n+\n+/* Import a block of memory into the GPU space. */\n+int vc_sm_cma_import_dmabuf(struct dma_buf *dmabuf, void **handle);\n+\n+#endif /* __VC_SM_KNL_H__INCLUDED__ */\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0339-staging-vchiq-mmal-Add-support-for-14bit-Bayer.patch",
    "content": "From 3791f318fc6368e22471515dfcbc40adeb764999 Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Wed, 6 May 2020 18:09:04 +0100\nSubject: [PATCH] staging: vchiq-mmal: Add support for 14bit Bayer\n\nAdd in the missing defines.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n drivers/staging/vc04_services/vchiq-mmal/mmal-encodings.h | 6 ++++++\n 1 file changed, 6 insertions(+)\n\n--- a/drivers/staging/vc04_services/vchiq-mmal/mmal-encodings.h\n+++ b/drivers/staging/vc04_services/vchiq-mmal/mmal-encodings.h\n@@ -90,6 +90,12 @@\n #define MMAL_ENCODING_BAYER_SGBRG12P   MMAL_FOURCC('p', 'G', '1', '2')\n #define MMAL_ENCODING_BAYER_SRGGB12P   MMAL_FOURCC('p', 'R', '1', '2')\n \n+//14 bit per pixel Bayer formats.\n+#define MMAL_ENCODING_BAYER_SBGGR14P   MMAL_FOURCC('p', 'B', 'E', 'E')\n+#define MMAL_ENCODING_BAYER_SGBRG14P   MMAL_FOURCC('p', 'G', 'E', 'E')\n+#define MMAL_ENCODING_BAYER_SGRBG14P   MMAL_FOURCC('p', 'g', 'E', 'E')\n+#define MMAL_ENCODING_BAYER_SRGGB14P   MMAL_FOURCC('p', 'R', 'E', 'E')\n+\n /* 16 bit per pixel Bayer formats. */\n #define MMAL_ENCODING_BAYER_SBGGR16    MMAL_FOURCC('B', 'G', '1', '6')\n #define MMAL_ENCODING_BAYER_SGBRG16    MMAL_FOURCC('G', 'B', '1', '6')\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0340-staging-mmal-vchiq-Add-monochrome-image-formats.patch",
    "content": "From 8af21994d7bd840cf8d06e099025e5657e533399 Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Wed, 6 May 2020 18:11:14 +0100\nSubject: [PATCH] staging: mmal-vchiq: Add monochrome image formats\n\nAdds support for monochrome image formats in the various\nMIPI packings.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n drivers/staging/vc04_services/vchiq-mmal/mmal-encodings.h | 7 +++++++\n 1 file changed, 7 insertions(+)\n\n--- a/drivers/staging/vc04_services/vchiq-mmal/mmal-encodings.h\n+++ b/drivers/staging/vc04_services/vchiq-mmal/mmal-encodings.h\n@@ -102,6 +102,13 @@\n #define MMAL_ENCODING_BAYER_SGRBG16    MMAL_FOURCC('G', 'R', '1', '6')\n #define MMAL_ENCODING_BAYER_SRGGB16    MMAL_FOURCC('R', 'G', '1', '6')\n \n+/* MIPI packed monochrome images */\n+#define MMAL_ENCODING_GREY    MMAL_FOURCC('G', 'R', 'E', 'Y')\n+#define MMAL_ENCODING_Y10P    MMAL_FOURCC('Y', '1', '0', 'P')\n+#define MMAL_ENCODING_Y12P    MMAL_FOURCC('Y', '1', '2', 'P')\n+#define MMAL_ENCODING_Y14P    MMAL_FOURCC('Y', '1', '4', 'P')\n+#define MMAL_ENCODING_Y16     MMAL_FOURCC('Y', '1', '6', ' ')\n+\n /** An EGL image handle\n  */\n #define MMAL_ENCODING_EGL_IMAGE        MMAL_FOURCC('E', 'G', 'L', 'I')\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0341-staging-mmal-vchiq-Use-vc-sm-cma-to-support-zero-cop.patch",
    "content": "From 821d92c939fbd94e0946fe93132f0125128c9781 Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.org>\nDate: Tue, 25 Sep 2018 16:07:55 +0100\nSubject: [PATCH] staging: mmal-vchiq: Use vc-sm-cma to support zero\n copy\n\nWith the vc-sm-cma driver we can support zero copy of buffers between\nthe kernel and VPU. Add this support to mmal-vchiq.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n .../staging/vc04_services/vchiq-mmal/Kconfig  |  1 +\n .../vc04_services/vchiq-mmal/mmal-common.h    |  4 ++\n .../vc04_services/vchiq-mmal/mmal-vchiq.c     | 65 ++++++++++++++++++-\n .../vc04_services/vchiq-mmal/mmal-vchiq.h     |  1 +\n 4 files changed, 69 insertions(+), 2 deletions(-)\n\n--- a/drivers/staging/vc04_services/vchiq-mmal/Kconfig\n+++ b/drivers/staging/vc04_services/vchiq-mmal/Kconfig\n@@ -1,6 +1,7 @@\n config BCM2835_VCHIQ_MMAL\n \ttristate \"BCM2835 MMAL VCHIQ service\"\n \tdepends on BCM2835_VCHIQ\n+\tselect BCM_VC_SM_CMA\n \thelp\n \t  Enables the MMAL API over VCHIQ interface as used for the\n \t  majority of the multimedia services on VideoCore.\n--- a/drivers/staging/vc04_services/vchiq-mmal/mmal-common.h\n+++ b/drivers/staging/vc04_services/vchiq-mmal/mmal-common.h\n@@ -50,6 +50,10 @@ struct mmal_buffer {\n \n \tstruct mmal_msg_context *msg_context;\n \n+\tstruct dma_buf *dma_buf;/* Exported dmabuf fd from videobuf2 */\n+\tvoid *vcsm_handle;\t/* VCSM handle having imported the dmabuf */\n+\tu32 vc_handle;\t\t/* VC handle to that dmabuf */\n+\n \tu32 cmd;\t\t/* MMAL command. 0=data. */\n \tunsigned long length;\n \tu32 mmal_flags;\n--- a/drivers/staging/vc04_services/vchiq-mmal/mmal-vchiq.c\n+++ b/drivers/staging/vc04_services/vchiq-mmal/mmal-vchiq.c\n@@ -27,9 +27,11 @@\n #include <media/videobuf2-vmalloc.h>\n \n #include \"mmal-common.h\"\n+#include \"mmal-parameters.h\"\n #include \"mmal-vchiq.h\"\n #include \"mmal-msg.h\"\n \n+#include \"vc-sm-cma/vc_sm_knl.h\"\n /*\n  * maximum number of components supported.\n  * This matches the maximum permitted by default on the VPU\n@@ -419,8 +421,13 @@ buffer_from_host(struct vchiq_mmal_insta\n \n \t/* buffer header */\n \tm.u.buffer_from_host.buffer_header.cmd = 0;\n-\tm.u.buffer_from_host.buffer_header.data =\n-\t\t(u32)(unsigned long)buf->buffer;\n+\tif (port->zero_copy) {\n+\t\tm.u.buffer_from_host.buffer_header.data = buf->vc_handle;\n+\t} else {\n+\t\tm.u.buffer_from_host.buffer_header.data =\n+\t\t\t(u32)(unsigned long)buf->buffer;\n+\t}\n+\n \tm.u.buffer_from_host.buffer_header.alloc_size = buf->buffer_size;\n \tif (port->type == MMAL_PORT_TYPE_OUTPUT) {\n \t\tm.u.buffer_from_host.buffer_header.length = 0;\n@@ -586,6 +593,22 @@ static void buffer_to_host_cb(struct vch\n \n \t\tmsg_context->u.bulk.status = msg->h.status;\n \n+\t} else if (msg->u.buffer_from_host.is_zero_copy) {\n+\t\t/*\n+\t\t * Zero copy buffer, so nothing to do.\n+\t\t * Copy buffer info and make callback.\n+\t\t */\n+\t\tmsg_context->u.bulk.buffer_used =\n+\t\t\t\tmsg->u.buffer_from_host.buffer_header.length;\n+\t\tmsg_context->u.bulk.mmal_flags =\n+\t\t\t\tmsg->u.buffer_from_host.buffer_header.flags;\n+\t\tmsg_context->u.bulk.dts =\n+\t\t\t\tmsg->u.buffer_from_host.buffer_header.dts;\n+\t\tmsg_context->u.bulk.pts =\n+\t\t\t\tmsg->u.buffer_from_host.buffer_header.pts;\n+\t\tmsg_context->u.bulk.cmd =\n+\t\t\t\tmsg->u.buffer_from_host.buffer_header.cmd;\n+\n \t} else if (msg->u.buffer_from_host.buffer_header.length == 0) {\n \t\t/* empty buffer */\n \t\tif (msg->u.buffer_from_host.buffer_header.flags &\n@@ -1530,6 +1553,9 @@ int vchiq_mmal_port_parameter_set(struct\n \n \tmutex_unlock(&instance->vchiq_mutex);\n \n+\tif (parameter == MMAL_PARAMETER_ZERO_COPY && !ret)\n+\t\tport->zero_copy = !!(*(bool *)value);\n+\n \treturn ret;\n }\n EXPORT_SYMBOL_GPL(vchiq_mmal_port_parameter_set);\n@@ -1698,6 +1724,31 @@ int vchiq_mmal_submit_buffer(struct vchi\n \tunsigned long flags = 0;\n \tint ret;\n \n+\t/*\n+\t * We really want to do this in mmal_vchi_buffer_init but can't as\n+\t * videobuf2 won't let us have the dmabuf there.\n+\t */\n+\tif (port->zero_copy && buffer->dma_buf && !buffer->vcsm_handle) {\n+\t\tpr_debug(\"%s: import dmabuf %p\\n\", __func__, buffer->dma_buf);\n+\t\tret = vc_sm_cma_import_dmabuf(buffer->dma_buf,\n+\t\t\t\t\t      &buffer->vcsm_handle);\n+\t\tif (ret) {\n+\t\t\tpr_err(\"%s: vc_sm_import_dmabuf_fd failed, ret %d\\n\",\n+\t\t\t       __func__, ret);\n+\t\t\treturn ret;\n+\t\t}\n+\n+\t\tbuffer->vc_handle = vc_sm_cma_int_handle(buffer->vcsm_handle);\n+\t\tif (!buffer->vc_handle) {\n+\t\t\tpr_err(\"%s: vc_sm_int_handle failed %d\\n\",\n+\t\t\t       __func__, ret);\n+\t\t\tvc_sm_cma_free(buffer->vcsm_handle);\n+\t\t\treturn ret;\n+\t\t}\n+\t\tpr_debug(\"%s: import dmabuf %p - got vc handle %08X\\n\",\n+\t\t\t __func__, buffer->dma_buf, buffer->vc_handle);\n+\t}\n+\n \tret = buffer_from_host(instance, port, buffer);\n \tif (ret == -EINVAL) {\n \t\t/* Port is disabled. Queue for when it is enabled. */\n@@ -1731,6 +1782,16 @@ int mmal_vchi_buffer_cleanup(struct mmal\n \t\trelease_msg_context(msg_context);\n \tbuf->msg_context = NULL;\n \n+\tif (buf->vcsm_handle) {\n+\t\tint ret;\n+\n+\t\tpr_debug(\"%s: vc_sm_cma_free on handle %p\\n\", __func__,\n+\t\t\t buf->vcsm_handle);\n+\t\tret = vc_sm_cma_free(buf->vcsm_handle);\n+\t\tif (ret)\n+\t\t\tpr_err(\"%s: vcsm_free failed, ret %d\\n\", __func__, ret);\n+\t\tbuf->vcsm_handle = 0;\n+\t}\n \treturn 0;\n }\n EXPORT_SYMBOL_GPL(mmal_vchi_buffer_cleanup);\n--- a/drivers/staging/vc04_services/vchiq-mmal/mmal-vchiq.h\n+++ b/drivers/staging/vc04_services/vchiq-mmal/mmal-vchiq.h\n@@ -49,6 +49,7 @@ typedef void (*vchiq_mmal_buffer_cb)(\n \n struct vchiq_mmal_port {\n \tu32 enabled:1;\n+\tu32 zero_copy:1;\n \tu32 handle;\n \tu32 type; /* port type, cached to use on port info set */\n \tu32 index; /* port index, cached to use on port info set */\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0342-staging-vc04_services-Add-a-V4L2-M2M-codec-driver.patch",
    "content": "From 0a0debba799056192927422c9dadf1db6a474580 Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Thu, 8 Oct 2020 20:24:12 +0100\nSubject: [PATCH] staging: vc04_services: Add a V4L2 M2M codec driver\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nThis adds a V4L2 memory to memory device that wraps the MMAL\nvideo decode and video_encode components for H264 and MJPEG encode\nand decode, MPEG4, H263, and VP8 decode (and MPEG2 decode\nif the appropriate licence has been purchased).\n\nThis patch squashes all the work done in developing the driver\non the Raspberry Pi rpi-5.4.y kernel branch.\nThanks to Kieran Bingham, Aman Gupta, Chen-Yu Tsai, and\nMarek Behún for their contributions. Please refer to the\nrpi-5.4.y branch for the full history.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n drivers/staging/vc04_services/Kconfig         |    1 +\n drivers/staging/vc04_services/Makefile        |    1 +\n .../vc04_services/bcm2835-codec/Kconfig       |   11 +\n .../vc04_services/bcm2835-codec/Makefile      |    8 +\n .../staging/vc04_services/bcm2835-codec/TODO  |    1 +\n .../bcm2835-codec/bcm2835-v4l2-codec.c        | 2984 +++++++++++++++++\n 6 files changed, 3006 insertions(+)\n create mode 100644 drivers/staging/vc04_services/bcm2835-codec/Kconfig\n create mode 100644 drivers/staging/vc04_services/bcm2835-codec/Makefile\n create mode 100644 drivers/staging/vc04_services/bcm2835-codec/TODO\n create mode 100644 drivers/staging/vc04_services/bcm2835-codec/bcm2835-v4l2-codec.c\n\n--- a/drivers/staging/vc04_services/Kconfig\n+++ b/drivers/staging/vc04_services/Kconfig\n@@ -24,6 +24,7 @@ source \"drivers/staging/vc04_services/bc\n source \"drivers/staging/vc04_services/bcm2835-camera/Kconfig\"\n \n source \"drivers/staging/vc04_services/vc-sm-cma/Kconfig\"\n+source \"drivers/staging/vc04_services/bcm2835-codec/Kconfig\"\n \n source \"drivers/staging/vc04_services/vchiq-mmal/Kconfig\"\n \n--- a/drivers/staging/vc04_services/Makefile\n+++ b/drivers/staging/vc04_services/Makefile\n@@ -12,6 +12,7 @@ obj-$(CONFIG_SND_BCM2835)\t\t+= bcm2835-au\n obj-$(CONFIG_VIDEO_BCM2835)\t\t+= bcm2835-camera/\n obj-$(CONFIG_BCM2835_VCHIQ_MMAL)\t+= vchiq-mmal/\n obj-$(CONFIG_BCM_VC_SM_CMA)\t\t+= vc-sm-cma/\n+obj-$(CONFIG_VIDEO_CODEC_BCM2835)\t+= bcm2835-codec/\n \n ccflags-y += -I $(srctree)/$(src)/include  -D__VCCOREVER__=0x04000000\n \n--- /dev/null\n+++ b/drivers/staging/vc04_services/bcm2835-codec/Kconfig\n@@ -0,0 +1,11 @@\n+config VIDEO_CODEC_BCM2835\n+\ttristate \"BCM2835 Video codec support\"\n+\tdepends on MEDIA_SUPPORT && MEDIA_CONTROLLER\n+\tdepends on VIDEO_V4L2 && (ARCH_BCM2835 || COMPILE_TEST)\n+\tselect BCM2835_VCHIQ_MMAL\n+\tselect VIDEOBUF2_DMA_CONTIG\n+\tselect V4L2_MEM2MEM_DEV\n+\thelp\n+\t  Say Y here to enable the V4L2 video codecs for\n+\t  Broadcom BCM2835 SoC. This operates over the VCHIQ interface\n+\t  to a service running on VideoCore.\n--- /dev/null\n+++ b/drivers/staging/vc04_services/bcm2835-codec/Makefile\n@@ -0,0 +1,8 @@\n+# SPDX-License-Identifier: GPL-2.0\n+bcm2835-codec-objs := bcm2835-v4l2-codec.o\n+\n+obj-$(CONFIG_VIDEO_CODEC_BCM2835) += bcm2835-codec.o\n+\n+ccflags-y += \\\n+\t-I$(srctree)/drivers/staging/vc04_services \\\n+\t-D__VCCOREVER__=0x04000000\n--- /dev/null\n+++ b/drivers/staging/vc04_services/bcm2835-codec/TODO\n@@ -0,0 +1 @@\n+No issues. Depends on VCHIQ which is in staging.\n\\ No newline at end of file\n--- /dev/null\n+++ b/drivers/staging/vc04_services/bcm2835-codec/bcm2835-v4l2-codec.c\n@@ -0,0 +1,2984 @@\n+// SPDX-License-Identifier: GPL-2.0\n+\n+/*\n+ * A v4l2-mem2mem device that wraps the video codec MMAL component.\n+ *\n+ * Copyright 2018 Raspberry Pi (Trading) Ltd.\n+ * Author: Dave Stevenson (dave.stevenson@raspberrypi.com)\n+ *\n+ * Loosely based on the vim2m virtual driver by Pawel Osciak\n+ * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.\n+ * Pawel Osciak, <pawel@osciak.com>\n+ * Marek Szyprowski, <m.szyprowski@samsung.com>\n+ *\n+ * Whilst this driver uses the v4l2_mem2mem framework, it does not need the\n+ * scheduling aspects, so will always take the buffers, pass them to the VPU,\n+ * and then signal the job as complete.\n+ *\n+ * This program is free software; you can redistribute it and/or modify\n+ * it under the terms of the GNU General Public License as published by the\n+ * Free Software Foundation; either version 2 of the\n+ * License, or (at your option) any later version\n+ */\n+#include <linux/module.h>\n+#include <linux/delay.h>\n+#include <linux/fs.h>\n+#include <linux/timer.h>\n+#include <linux/sched.h>\n+#include <linux/slab.h>\n+#include <linux/platform_device.h>\n+#include <linux/syscalls.h>\n+\n+#include <media/v4l2-mem2mem.h>\n+#include <media/v4l2-device.h>\n+#include <media/v4l2-ioctl.h>\n+#include <media/v4l2-ctrls.h>\n+#include <media/v4l2-event.h>\n+#include <media/videobuf2-dma-contig.h>\n+\n+#include \"vchiq-mmal/mmal-encodings.h\"\n+#include \"vchiq-mmal/mmal-msg.h\"\n+#include \"vchiq-mmal/mmal-parameters.h\"\n+#include \"vchiq-mmal/mmal-vchiq.h\"\n+\n+/*\n+ * Default /dev/videoN node numbers for decode and encode.\n+ * Deliberately avoid the very low numbers as these are often taken by webcams\n+ * etc, and simple apps tend to only go for /dev/video0.\n+ */\n+static int decode_video_nr = 10;\n+module_param(decode_video_nr, int, 0644);\n+MODULE_PARM_DESC(decode_video_nr, \"decoder video device number\");\n+\n+static int encode_video_nr = 11;\n+module_param(encode_video_nr, int, 0644);\n+MODULE_PARM_DESC(encode_video_nr, \"encoder video device number\");\n+\n+static int isp_video_nr = 12;\n+module_param(isp_video_nr, int, 0644);\n+MODULE_PARM_DESC(isp_video_nr, \"isp video device number\");\n+\n+/*\n+ * Workaround for GStreamer v4l2convert component not considering Bayer formats\n+ * as raw, and therefore not considering a V4L2 device that supports them as\n+ * a suitable candidate.\n+ */\n+static bool disable_bayer;\n+module_param(disable_bayer, bool, 0644);\n+MODULE_PARM_DESC(disable_bayer, \"Disable support for Bayer formats\");\n+\n+static unsigned int debug;\n+module_param(debug, uint, 0644);\n+MODULE_PARM_DESC(debug, \"activates debug info (0-3)\");\n+\n+enum bcm2835_codec_role {\n+\tDECODE,\n+\tENCODE,\n+\tISP,\n+};\n+\n+static const char * const roles[] = {\n+\t\"decode\",\n+\t\"encode\",\n+\t\"isp\"\n+};\n+\n+static const char * const components[] = {\n+\t\"ril.video_decode\",\n+\t\"ril.video_encode\",\n+\t\"ril.isp\",\n+};\n+\n+/* Timeout for stop_streaming to allow all buffers to return */\n+#define COMPLETE_TIMEOUT (2 * HZ)\n+\n+#define MIN_W\t\t32\n+#define MIN_H\t\t32\n+#define MAX_W\t\t1920\n+#define MAX_H\t\t1920\n+#define BPL_ALIGN\t32\n+#define DEFAULT_WIDTH\t640\n+#define DEFAULT_HEIGHT\t480\n+/*\n+ * The unanswered question - what is the maximum size of a compressed frame?\n+ * V4L2 mandates that the encoded frame must fit in a single buffer. Sizing\n+ * that buffer is a compromise between wasting memory and risking not fitting.\n+ * The 1080P version of Big Buck Bunny has some frames that exceed 512kB.\n+ * Adopt a moderately arbitrary split at 720P for switching between 512 and\n+ * 768kB buffers.\n+ */\n+#define DEF_COMP_BUF_SIZE_GREATER_720P\t(768 << 10)\n+#define DEF_COMP_BUF_SIZE_720P_OR_LESS\t(512 << 10)\n+\n+/* Flags that indicate a format can be used for capture/output */\n+#define MEM2MEM_CAPTURE\t\tBIT(0)\n+#define MEM2MEM_OUTPUT\t\tBIT(1)\n+\n+#define MEM2MEM_NAME\t\t\"bcm2835-codec\"\n+\n+struct bcm2835_codec_fmt {\n+\tu32\tfourcc;\n+\tint\tdepth;\n+\tint\tbytesperline_align;\n+\tu32\tflags;\n+\tu32\tmmal_fmt;\n+\tint\tsize_multiplier_x2;\n+\tbool\tis_bayer;\n+};\n+\n+static const struct bcm2835_codec_fmt supported_formats[] = {\n+\t{\n+\t\t/* YUV formats */\n+\t\t.fourcc\t\t\t= V4L2_PIX_FMT_YUV420,\n+\t\t.depth\t\t\t= 8,\n+\t\t.bytesperline_align\t= 32,\n+\t\t.flags\t\t\t= 0,\n+\t\t.mmal_fmt\t\t= MMAL_ENCODING_I420,\n+\t\t.size_multiplier_x2\t= 3,\n+\t}, {\n+\t\t.fourcc\t\t\t= V4L2_PIX_FMT_YVU420,\n+\t\t.depth\t\t\t= 8,\n+\t\t.bytesperline_align\t= 32,\n+\t\t.flags\t\t\t= 0,\n+\t\t.mmal_fmt\t\t= MMAL_ENCODING_YV12,\n+\t\t.size_multiplier_x2\t= 3,\n+\t}, {\n+\t\t.fourcc\t\t\t= V4L2_PIX_FMT_NV12,\n+\t\t.depth\t\t\t= 8,\n+\t\t.bytesperline_align\t= 32,\n+\t\t.flags\t\t\t= 0,\n+\t\t.mmal_fmt\t\t= MMAL_ENCODING_NV12,\n+\t\t.size_multiplier_x2\t= 3,\n+\t}, {\n+\t\t.fourcc\t\t\t= V4L2_PIX_FMT_NV21,\n+\t\t.depth\t\t\t= 8,\n+\t\t.bytesperline_align\t= 32,\n+\t\t.flags\t\t\t= 0,\n+\t\t.mmal_fmt\t\t= MMAL_ENCODING_NV21,\n+\t\t.size_multiplier_x2\t= 3,\n+\t}, {\n+\t\t.fourcc\t\t\t= V4L2_PIX_FMT_RGB565,\n+\t\t.depth\t\t\t= 16,\n+\t\t.bytesperline_align\t= 32,\n+\t\t.flags\t\t\t= 0,\n+\t\t.mmal_fmt\t\t= MMAL_ENCODING_RGB16,\n+\t\t.size_multiplier_x2\t= 2,\n+\t}, {\n+\t\t.fourcc\t\t\t= V4L2_PIX_FMT_YUYV,\n+\t\t.depth\t\t\t= 16,\n+\t\t.bytesperline_align\t= 32,\n+\t\t.flags\t\t\t= 0,\n+\t\t.mmal_fmt\t\t= MMAL_ENCODING_YUYV,\n+\t\t.size_multiplier_x2\t= 2,\n+\t}, {\n+\t\t.fourcc\t\t\t= V4L2_PIX_FMT_UYVY,\n+\t\t.depth\t\t\t= 16,\n+\t\t.bytesperline_align\t= 32,\n+\t\t.flags\t\t\t= 0,\n+\t\t.mmal_fmt\t\t= MMAL_ENCODING_UYVY,\n+\t\t.size_multiplier_x2\t= 2,\n+\t}, {\n+\t\t.fourcc\t\t\t= V4L2_PIX_FMT_YVYU,\n+\t\t.depth\t\t\t= 16,\n+\t\t.bytesperline_align\t= 32,\n+\t\t.flags\t\t\t= 0,\n+\t\t.mmal_fmt\t\t= MMAL_ENCODING_YVYU,\n+\t\t.size_multiplier_x2\t= 2,\n+\t}, {\n+\t\t.fourcc\t\t\t= V4L2_PIX_FMT_VYUY,\n+\t\t.depth\t\t\t= 16,\n+\t\t.bytesperline_align\t= 32,\n+\t\t.flags\t\t\t= 0,\n+\t\t.mmal_fmt\t\t= MMAL_ENCODING_VYUY,\n+\t\t.size_multiplier_x2\t= 2,\n+\t}, {\n+\t\t/* RGB formats */\n+\t\t.fourcc\t\t\t= V4L2_PIX_FMT_RGB24,\n+\t\t.depth\t\t\t= 24,\n+\t\t.bytesperline_align\t= 32,\n+\t\t.flags\t\t\t= 0,\n+\t\t.mmal_fmt\t\t= MMAL_ENCODING_RGB24,\n+\t\t.size_multiplier_x2\t= 2,\n+\t}, {\n+\t\t.fourcc\t\t\t= V4L2_PIX_FMT_BGR24,\n+\t\t.depth\t\t\t= 24,\n+\t\t.bytesperline_align\t= 32,\n+\t\t.flags\t\t\t= 0,\n+\t\t.mmal_fmt\t\t= MMAL_ENCODING_BGR24,\n+\t\t.size_multiplier_x2\t= 2,\n+\t}, {\n+\t\t.fourcc\t\t\t= V4L2_PIX_FMT_BGR32,\n+\t\t.depth\t\t\t= 32,\n+\t\t.bytesperline_align\t= 32,\n+\t\t.flags\t\t\t= 0,\n+\t\t.mmal_fmt\t\t= MMAL_ENCODING_BGRA,\n+\t\t.size_multiplier_x2\t= 2,\n+\t}, {\n+\t\t/* Bayer formats */\n+\t\t/* 8 bit */\n+\t\t.fourcc\t\t\t= V4L2_PIX_FMT_SRGGB8,\n+\t\t.depth\t\t\t= 8,\n+\t\t.bytesperline_align\t= 32,\n+\t\t.flags\t\t\t= 0,\n+\t\t.mmal_fmt\t\t= MMAL_ENCODING_BAYER_SRGGB8,\n+\t\t.size_multiplier_x2\t= 2,\n+\t\t.is_bayer\t\t= true,\n+\t}, {\n+\t\t.fourcc\t\t\t= V4L2_PIX_FMT_SBGGR8,\n+\t\t.depth\t\t\t= 8,\n+\t\t.bytesperline_align\t= 32,\n+\t\t.flags\t\t\t= 0,\n+\t\t.mmal_fmt\t\t= MMAL_ENCODING_BAYER_SBGGR8,\n+\t\t.size_multiplier_x2\t= 2,\n+\t\t.is_bayer\t\t= true,\n+\t}, {\n+\t\t.fourcc\t\t\t= V4L2_PIX_FMT_SGRBG8,\n+\t\t.depth\t\t\t= 8,\n+\t\t.bytesperline_align\t= 32,\n+\t\t.flags\t\t\t= 0,\n+\t\t.mmal_fmt\t\t= MMAL_ENCODING_BAYER_SGRBG8,\n+\t\t.size_multiplier_x2\t= 2,\n+\t\t.is_bayer\t\t= true,\n+\t}, {\n+\t\t.fourcc\t\t\t= V4L2_PIX_FMT_SGBRG8,\n+\t\t.depth\t\t\t= 8,\n+\t\t.bytesperline_align\t= 32,\n+\t\t.flags\t\t\t= 0,\n+\t\t.mmal_fmt\t\t= MMAL_ENCODING_BAYER_SGBRG8,\n+\t\t.size_multiplier_x2\t= 2,\n+\t\t.is_bayer\t\t= true,\n+\t}, {\n+\t\t/* 10 bit */\n+\t\t.fourcc\t\t\t= V4L2_PIX_FMT_SRGGB10P,\n+\t\t.depth\t\t\t= 10,\n+\t\t.bytesperline_align\t= 32,\n+\t\t.flags\t\t\t= 0,\n+\t\t.mmal_fmt\t\t= MMAL_ENCODING_BAYER_SRGGB10P,\n+\t\t.size_multiplier_x2\t= 2,\n+\t\t.is_bayer\t\t= true,\n+\t}, {\n+\t\t.fourcc\t\t\t= V4L2_PIX_FMT_SBGGR10P,\n+\t\t.depth\t\t\t= 10,\n+\t\t.bytesperline_align\t= 32,\n+\t\t.flags\t\t\t= 0,\n+\t\t.mmal_fmt\t\t= MMAL_ENCODING_BAYER_SBGGR10P,\n+\t\t.size_multiplier_x2\t= 2,\n+\t\t.is_bayer\t\t= true,\n+\t}, {\n+\t\t.fourcc\t\t\t= V4L2_PIX_FMT_SGRBG10P,\n+\t\t.depth\t\t\t= 10,\n+\t\t.bytesperline_align\t= 32,\n+\t\t.flags\t\t\t= 0,\n+\t\t.mmal_fmt\t\t= MMAL_ENCODING_BAYER_SGRBG10P,\n+\t\t.size_multiplier_x2\t= 2,\n+\t\t.is_bayer\t\t= true,\n+\t}, {\n+\t\t.fourcc\t\t\t= V4L2_PIX_FMT_SGBRG10P,\n+\t\t.depth\t\t\t= 10,\n+\t\t.bytesperline_align\t= 32,\n+\t\t.flags\t\t\t= 0,\n+\t\t.mmal_fmt\t\t= MMAL_ENCODING_BAYER_SGBRG10P,\n+\t\t.size_multiplier_x2\t= 2,\n+\t\t.is_bayer\t\t= true,\n+\t}, {\n+\t\t/* 12 bit */\n+\t\t.fourcc\t\t\t= V4L2_PIX_FMT_SRGGB12P,\n+\t\t.depth\t\t\t= 12,\n+\t\t.bytesperline_align\t= 32,\n+\t\t.flags\t\t\t= 0,\n+\t\t.mmal_fmt\t\t= MMAL_ENCODING_BAYER_SRGGB12P,\n+\t\t.size_multiplier_x2\t= 2,\n+\t\t.is_bayer\t\t= true,\n+\t}, {\n+\t\t.fourcc\t\t\t= V4L2_PIX_FMT_SBGGR12P,\n+\t\t.depth\t\t\t= 12,\n+\t\t.bytesperline_align\t= 32,\n+\t\t.flags\t\t\t= 0,\n+\t\t.mmal_fmt\t\t= MMAL_ENCODING_BAYER_SBGGR12P,\n+\t\t.size_multiplier_x2\t= 2,\n+\t\t.is_bayer\t\t= true,\n+\t}, {\n+\t\t.fourcc\t\t\t= V4L2_PIX_FMT_SGRBG12P,\n+\t\t.depth\t\t\t= 12,\n+\t\t.bytesperline_align\t= 32,\n+\t\t.flags\t\t\t= 0,\n+\t\t.mmal_fmt\t\t= MMAL_ENCODING_BAYER_SGRBG12P,\n+\t\t.size_multiplier_x2\t= 2,\n+\t\t.is_bayer\t\t= true,\n+\t}, {\n+\t\t.fourcc\t\t\t= V4L2_PIX_FMT_SGBRG12P,\n+\t\t.depth\t\t\t= 12,\n+\t\t.bytesperline_align\t= 32,\n+\t\t.flags\t\t\t= 0,\n+\t\t.mmal_fmt\t\t= MMAL_ENCODING_BAYER_SGBRG12P,\n+\t\t.size_multiplier_x2\t= 2,\n+\t\t.is_bayer\t\t= true,\n+\t}, {\n+\t\t/* 14 bit */\n+\t\t.fourcc\t\t\t= V4L2_PIX_FMT_SRGGB14P,\n+\t\t.depth\t\t\t= 14,\n+\t\t.bytesperline_align\t= 32,\n+\t\t.flags\t\t\t= 0,\n+\t\t.mmal_fmt\t\t= MMAL_ENCODING_BAYER_SRGGB14P,\n+\t\t.size_multiplier_x2\t= 2,\n+\t\t.is_bayer\t\t= true,\n+\t}, {\n+\t\t.fourcc\t\t\t= V4L2_PIX_FMT_SBGGR14P,\n+\t\t.depth\t\t\t= 14,\n+\t\t.bytesperline_align\t= 32,\n+\t\t.flags\t\t\t= 0,\n+\t\t.mmal_fmt\t\t= MMAL_ENCODING_BAYER_SBGGR14P,\n+\t\t.size_multiplier_x2\t= 2,\n+\t\t.is_bayer\t\t= true,\n+\n+\t}, {\n+\t\t.fourcc\t\t\t= V4L2_PIX_FMT_SGRBG14P,\n+\t\t.depth\t\t\t= 14,\n+\t\t.bytesperline_align\t= 32,\n+\t\t.flags\t\t\t= 0,\n+\t\t.mmal_fmt\t\t= MMAL_ENCODING_BAYER_SGRBG14P,\n+\t\t.size_multiplier_x2\t= 2,\n+\t\t.is_bayer\t\t= true,\n+\t}, {\n+\t\t.fourcc\t\t\t= V4L2_PIX_FMT_SGBRG14P,\n+\t\t.depth\t\t\t= 14,\n+\t\t.bytesperline_align\t= 32,\n+\t\t.flags\t\t\t= 0,\n+\t\t.mmal_fmt\t\t= MMAL_ENCODING_BAYER_SGBRG14P,\n+\t\t.size_multiplier_x2\t= 2,\n+\t\t.is_bayer\t\t= true,\n+\t}, {\n+\t\t/* 16 bit */\n+\t\t.fourcc\t\t\t= V4L2_PIX_FMT_SRGGB16,\n+\t\t.depth\t\t\t= 16,\n+\t\t.bytesperline_align\t= 32,\n+\t\t.flags\t\t\t= 0,\n+\t\t.mmal_fmt\t\t= MMAL_ENCODING_BAYER_SRGGB16,\n+\t\t.size_multiplier_x2\t= 2,\n+\t\t.is_bayer\t\t= true,\n+\t}, {\n+\t\t.fourcc\t\t\t= V4L2_PIX_FMT_SBGGR16,\n+\t\t.depth\t\t\t= 16,\n+\t\t.bytesperline_align\t= 32,\n+\t\t.flags\t\t\t= 0,\n+\t\t.mmal_fmt\t\t= MMAL_ENCODING_BAYER_SBGGR16,\n+\t\t.size_multiplier_x2\t= 2,\n+\t\t.is_bayer\t\t= true,\n+\t}, {\n+\t\t.fourcc\t\t\t= V4L2_PIX_FMT_SGRBG16,\n+\t\t.depth\t\t\t= 16,\n+\t\t.bytesperline_align\t= 32,\n+\t\t.flags\t\t\t= 0,\n+\t\t.mmal_fmt\t\t= MMAL_ENCODING_BAYER_SGRBG16,\n+\t\t.size_multiplier_x2\t= 2,\n+\t\t.is_bayer\t\t= true,\n+\t}, {\n+\t\t.fourcc\t\t\t= V4L2_PIX_FMT_SGBRG16,\n+\t\t.depth\t\t\t= 16,\n+\t\t.bytesperline_align\t= 32,\n+\t\t.flags\t\t\t= 0,\n+\t\t.mmal_fmt\t\t= MMAL_ENCODING_BAYER_SGBRG16,\n+\t\t.size_multiplier_x2\t= 2,\n+\t\t.is_bayer\t\t= true,\n+\t}, {\n+\t\t/* Monochrome MIPI formats */\n+\t\t/* 8 bit */\n+\t\t.fourcc\t\t\t= V4L2_PIX_FMT_GREY,\n+\t\t.depth\t\t\t= 8,\n+\t\t.bytesperline_align\t= 32,\n+\t\t.flags\t\t\t= 0,\n+\t\t.mmal_fmt\t\t= MMAL_ENCODING_GREY,\n+\t\t.size_multiplier_x2\t= 2,\n+\t}, {\n+\t\t/* 10 bit */\n+\t\t.fourcc\t\t\t= V4L2_PIX_FMT_Y10P,\n+\t\t.depth\t\t\t= 10,\n+\t\t.bytesperline_align\t= 32,\n+\t\t.flags\t\t\t= 0,\n+\t\t.mmal_fmt\t\t= MMAL_ENCODING_Y10P,\n+\t\t.size_multiplier_x2\t= 2,\n+\t}, {\n+\t\t/* 12 bit */\n+\t\t.fourcc\t\t\t= V4L2_PIX_FMT_Y12P,\n+\t\t.depth\t\t\t= 12,\n+\t\t.bytesperline_align\t= 32,\n+\t\t.flags\t\t\t= 0,\n+\t\t.mmal_fmt\t\t= MMAL_ENCODING_Y12P,\n+\t\t.size_multiplier_x2\t= 2,\n+\t}, {\n+\t\t/* 14 bit */\n+\t\t.fourcc\t\t\t= V4L2_PIX_FMT_Y14P,\n+\t\t.depth\t\t\t= 14,\n+\t\t.bytesperline_align\t= 32,\n+\t\t.flags\t\t\t= 0,\n+\t\t.mmal_fmt\t\t= MMAL_ENCODING_Y14P,\n+\t\t.size_multiplier_x2\t= 2,\n+\t}, {\n+\t\t/* 16 bit */\n+\t\t.fourcc\t\t\t= V4L2_PIX_FMT_Y16,\n+\t\t.depth\t\t\t= 16,\n+\t\t.bytesperline_align\t= 32,\n+\t\t.flags\t\t\t= 0,\n+\t\t.mmal_fmt\t\t= MMAL_ENCODING_Y16,\n+\t\t.size_multiplier_x2\t= 2,\n+\t}, {\n+\t\t/* Compressed formats */\n+\t\t.fourcc\t\t\t= V4L2_PIX_FMT_H264,\n+\t\t.depth\t\t\t= 0,\n+\t\t.flags\t\t\t= V4L2_FMT_FLAG_COMPRESSED,\n+\t\t.mmal_fmt\t\t= MMAL_ENCODING_H264,\n+\t}, {\n+\t\t.fourcc\t\t\t= V4L2_PIX_FMT_MJPEG,\n+\t\t.depth\t\t\t= 0,\n+\t\t.flags\t\t\t= V4L2_FMT_FLAG_COMPRESSED,\n+\t\t.mmal_fmt\t\t= MMAL_ENCODING_MJPEG,\n+\t}, {\n+\t\t.fourcc\t\t\t= V4L2_PIX_FMT_MPEG4,\n+\t\t.depth\t\t\t= 0,\n+\t\t.flags\t\t\t= V4L2_FMT_FLAG_COMPRESSED,\n+\t\t.mmal_fmt\t\t= MMAL_ENCODING_MP4V,\n+\t}, {\n+\t\t.fourcc\t\t\t= V4L2_PIX_FMT_H263,\n+\t\t.depth\t\t\t= 0,\n+\t\t.flags\t\t\t= V4L2_FMT_FLAG_COMPRESSED,\n+\t\t.mmal_fmt\t\t= MMAL_ENCODING_H263,\n+\t}, {\n+\t\t.fourcc\t\t\t= V4L2_PIX_FMT_MPEG2,\n+\t\t.depth\t\t\t= 0,\n+\t\t.flags\t\t\t= V4L2_FMT_FLAG_COMPRESSED,\n+\t\t.mmal_fmt\t\t= MMAL_ENCODING_MP2V,\n+\t}, {\n+\t\t.fourcc\t\t\t= V4L2_PIX_FMT_VP8,\n+\t\t.depth\t\t\t= 0,\n+\t\t.flags\t\t\t= V4L2_FMT_FLAG_COMPRESSED,\n+\t\t.mmal_fmt\t\t= MMAL_ENCODING_VP8,\n+\t},\n+};\n+\n+struct bcm2835_codec_fmt_list {\n+\tstruct bcm2835_codec_fmt *list;\n+\tunsigned int num_entries;\n+};\n+\n+struct m2m_mmal_buffer {\n+\tstruct v4l2_m2m_buffer\tm2m;\n+\tstruct mmal_buffer\tmmal;\n+};\n+\n+/* Per-queue, driver-specific private data */\n+struct bcm2835_codec_q_data {\n+\t/*\n+\t * These parameters should be treated as gospel, with everything else\n+\t * being determined from them.\n+\t */\n+\t/* Buffer width/height */\n+\tunsigned int\t\tbytesperline;\n+\tunsigned int\t\theight;\n+\t/* Crop size used for selection handling */\n+\tunsigned int\t\tcrop_width;\n+\tunsigned int\t\tcrop_height;\n+\tbool\t\t\tselection_set;\n+\n+\tunsigned int\t\tsizeimage;\n+\tunsigned int\t\tsequence;\n+\tstruct bcm2835_codec_fmt\t*fmt;\n+\n+\t/* One extra buffer header so we can send an EOS. */\n+\tstruct m2m_mmal_buffer\teos_buffer;\n+\tbool\t\t\teos_buffer_in_use;\t/* debug only */\n+};\n+\n+struct bcm2835_codec_dev {\n+\tstruct platform_device *pdev;\n+\n+\t/* v4l2 devices */\n+\tstruct v4l2_device\tv4l2_dev;\n+\tstruct video_device\tvfd;\n+\t/* mutex for the v4l2 device */\n+\tstruct mutex\t\tdev_mutex;\n+\tatomic_t\t\tnum_inst;\n+\n+\t/* allocated mmal instance and components */\n+\tenum bcm2835_codec_role\trole;\n+\t/* The list of formats supported on input and output queues. */\n+\tstruct bcm2835_codec_fmt_list\tsupported_fmts[2];\n+\n+\tstruct vchiq_mmal_instance\t*instance;\n+\n+\tstruct v4l2_m2m_dev\t*m2m_dev;\n+};\n+\n+struct bcm2835_codec_ctx {\n+\tstruct v4l2_fh\t\tfh;\n+\tstruct bcm2835_codec_dev\t*dev;\n+\n+\tstruct v4l2_ctrl_handler hdl;\n+\n+\tstruct vchiq_mmal_component  *component;\n+\tbool component_enabled;\n+\n+\tenum v4l2_colorspace\tcolorspace;\n+\tenum v4l2_ycbcr_encoding ycbcr_enc;\n+\tenum v4l2_xfer_func\txfer_func;\n+\tenum v4l2_quantization\tquant;\n+\n+\t/* Source and destination queue data */\n+\tstruct bcm2835_codec_q_data   q_data[2];\n+\ts32  bitrate;\n+\tunsigned int\tframerate_num;\n+\tunsigned int\tframerate_denom;\n+\n+\tbool aborting;\n+\tint num_ip_buffers;\n+\tint num_op_buffers;\n+\tstruct completion frame_cmplt;\n+};\n+\n+struct bcm2835_codec_driver {\n+\tstruct platform_device *pdev;\n+\tstruct media_device\tmdev;\n+\n+\tstruct bcm2835_codec_dev *encode;\n+\tstruct bcm2835_codec_dev *decode;\n+\tstruct bcm2835_codec_dev *isp;\n+};\n+\n+enum {\n+\tV4L2_M2M_SRC = 0,\n+\tV4L2_M2M_DST = 1,\n+};\n+\n+static const struct bcm2835_codec_fmt *get_fmt(u32 mmal_fmt)\n+{\n+\tunsigned int i;\n+\n+\tfor (i = 0; i < ARRAY_SIZE(supported_formats); i++) {\n+\t\tif (supported_formats[i].mmal_fmt == mmal_fmt &&\n+\t\t    (!disable_bayer || !supported_formats[i].is_bayer))\n+\t\t\treturn &supported_formats[i];\n+\t}\n+\treturn NULL;\n+}\n+\n+static inline\n+struct bcm2835_codec_fmt_list *get_format_list(struct bcm2835_codec_dev *dev,\n+\t\t\t\t\t       bool capture)\n+{\n+\treturn &dev->supported_fmts[capture ? 1 : 0];\n+}\n+\n+static\n+struct bcm2835_codec_fmt *get_default_format(struct bcm2835_codec_dev *dev,\n+\t\t\t\t\t     bool capture)\n+{\n+\treturn &dev->supported_fmts[capture ? 1 : 0].list[0];\n+}\n+\n+static\n+struct bcm2835_codec_fmt *find_format_pix_fmt(u32 pix_fmt,\n+\t\t\t\t\t      struct bcm2835_codec_dev *dev,\n+\t\t\t\t\t      bool capture)\n+{\n+\tstruct bcm2835_codec_fmt *fmt;\n+\tunsigned int k;\n+\tstruct bcm2835_codec_fmt_list *fmts =\n+\t\t\t\t\t&dev->supported_fmts[capture ? 1 : 0];\n+\n+\tfor (k = 0; k < fmts->num_entries; k++) {\n+\t\tfmt = &fmts->list[k];\n+\t\tif (fmt->fourcc == pix_fmt)\n+\t\t\tbreak;\n+\t}\n+\tif (k == fmts->num_entries)\n+\t\treturn NULL;\n+\n+\treturn &fmts->list[k];\n+}\n+\n+static inline\n+struct bcm2835_codec_fmt *find_format(struct v4l2_format *f,\n+\t\t\t\t      struct bcm2835_codec_dev *dev,\n+\t\t\t\t      bool capture)\n+{\n+\treturn find_format_pix_fmt(f->fmt.pix_mp.pixelformat, dev, capture);\n+}\n+\n+static inline struct bcm2835_codec_ctx *file2ctx(struct file *file)\n+{\n+\treturn container_of(file->private_data, struct bcm2835_codec_ctx, fh);\n+}\n+\n+static struct bcm2835_codec_q_data *get_q_data(struct bcm2835_codec_ctx *ctx,\n+\t\t\t\t\t       enum v4l2_buf_type type)\n+{\n+\tswitch (type) {\n+\tcase V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE:\n+\t\treturn &ctx->q_data[V4L2_M2M_SRC];\n+\tcase V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE:\n+\t\treturn &ctx->q_data[V4L2_M2M_DST];\n+\tdefault:\n+\t\tv4l2_err(&ctx->dev->v4l2_dev, \"%s: Invalid queue type %u\\n\",\n+\t\t\t __func__, type);\n+\t\tbreak;\n+\t}\n+\treturn NULL;\n+}\n+\n+static struct vchiq_mmal_port *get_port_data(struct bcm2835_codec_ctx *ctx,\n+\t\t\t\t\t     enum v4l2_buf_type type)\n+{\n+\tif (!ctx->component)\n+\t\treturn NULL;\n+\n+\tswitch (type) {\n+\tcase V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE:\n+\t\treturn &ctx->component->input[0];\n+\tcase V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE:\n+\t\treturn &ctx->component->output[0];\n+\tdefault:\n+\t\tv4l2_err(&ctx->dev->v4l2_dev, \"%s: Invalid queue type %u\\n\",\n+\t\t\t __func__, type);\n+\t\tbreak;\n+\t}\n+\treturn NULL;\n+}\n+\n+/*\n+ * mem2mem callbacks\n+ */\n+\n+/*\n+ * job_ready() - check whether an instance is ready to be scheduled to run\n+ */\n+static int job_ready(void *priv)\n+{\n+\tstruct bcm2835_codec_ctx *ctx = priv;\n+\n+\tif (!v4l2_m2m_num_src_bufs_ready(ctx->fh.m2m_ctx) &&\n+\t    !v4l2_m2m_num_dst_bufs_ready(ctx->fh.m2m_ctx))\n+\t\treturn 0;\n+\n+\treturn 1;\n+}\n+\n+static void job_abort(void *priv)\n+{\n+\tstruct bcm2835_codec_ctx *ctx = priv;\n+\n+\tv4l2_dbg(1, debug, &ctx->dev->v4l2_dev, \"%s\\n\", __func__);\n+\t/* Will cancel the transaction in the next interrupt handler */\n+\tctx->aborting = 1;\n+}\n+\n+static inline unsigned int get_sizeimage(int bpl, int width, int height,\n+\t\t\t\t\t struct bcm2835_codec_fmt *fmt)\n+{\n+\tif (fmt->flags & V4L2_FMT_FLAG_COMPRESSED) {\n+\t\tif (width * height > 1280 * 720)\n+\t\t\treturn DEF_COMP_BUF_SIZE_GREATER_720P;\n+\t\telse\n+\t\t\treturn DEF_COMP_BUF_SIZE_720P_OR_LESS;\n+\t} else {\n+\t\treturn (bpl * height * fmt->size_multiplier_x2) >> 1;\n+\t}\n+}\n+\n+static inline unsigned int get_bytesperline(int width,\n+\t\t\t\t\t    struct bcm2835_codec_fmt *fmt)\n+{\n+\treturn ALIGN((width * fmt->depth) >> 3, fmt->bytesperline_align);\n+}\n+\n+static void setup_mmal_port_format(struct bcm2835_codec_ctx *ctx,\n+\t\t\t\t   struct bcm2835_codec_q_data *q_data,\n+\t\t\t\t   struct vchiq_mmal_port *port)\n+{\n+\tport->format.encoding = q_data->fmt->mmal_fmt;\n+\n+\tif (!(q_data->fmt->flags & V4L2_FMT_FLAG_COMPRESSED)) {\n+\t\t/* Raw image format - set width/height */\n+\t\tport->es.video.width = (q_data->bytesperline << 3) /\n+\t\t\t\t\t\tq_data->fmt->depth;\n+\t\tport->es.video.height = q_data->height;\n+\t\tport->es.video.crop.width = q_data->crop_width;\n+\t\tport->es.video.crop.height = q_data->crop_height;\n+\t\tport->es.video.frame_rate.num = ctx->framerate_num;\n+\t\tport->es.video.frame_rate.den = ctx->framerate_denom;\n+\t} else {\n+\t\t/* Compressed format - leave resolution as 0 for decode */\n+\t\tif (ctx->dev->role == DECODE) {\n+\t\t\tport->es.video.width = 0;\n+\t\t\tport->es.video.height = 0;\n+\t\t\tport->es.video.crop.width = 0;\n+\t\t\tport->es.video.crop.height = 0;\n+\t\t} else {\n+\t\t\tport->es.video.width = q_data->crop_width;\n+\t\t\tport->es.video.height = q_data->height;\n+\t\t\tport->es.video.crop.width = q_data->crop_width;\n+\t\t\tport->es.video.crop.height = q_data->crop_height;\n+\t\t\tport->format.bitrate = ctx->bitrate;\n+\t\t\tport->es.video.frame_rate.num = ctx->framerate_num;\n+\t\t\tport->es.video.frame_rate.den = ctx->framerate_denom;\n+\t\t}\n+\t}\n+\tport->es.video.crop.x = 0;\n+\tport->es.video.crop.y = 0;\n+\n+\tport->current_buffer.size = q_data->sizeimage;\n+};\n+\n+static void ip_buffer_cb(struct vchiq_mmal_instance *instance,\n+\t\t\t struct vchiq_mmal_port *port, int status,\n+\t\t\t struct mmal_buffer *mmal_buf)\n+{\n+\tstruct bcm2835_codec_ctx *ctx = port->cb_ctx/*, *curr_ctx*/;\n+\tstruct m2m_mmal_buffer *buf =\n+\t\t\tcontainer_of(mmal_buf, struct m2m_mmal_buffer, mmal);\n+\n+\tv4l2_dbg(2, debug, &ctx->dev->v4l2_dev, \"%s: port %p buf %p length %lu, flags %x\\n\",\n+\t\t __func__, port, mmal_buf, mmal_buf->length,\n+\t\t mmal_buf->mmal_flags);\n+\n+\tif (buf == &ctx->q_data[V4L2_M2M_SRC].eos_buffer) {\n+\t\t/* Do we need to add lcoking to prevent multiple submission of\n+\t\t * the EOS, and therefore handle mutliple return here?\n+\t\t */\n+\t\tv4l2_dbg(1, debug, &ctx->dev->v4l2_dev, \"%s: eos buffer returned.\\n\",\n+\t\t\t __func__);\n+\t\tctx->q_data[V4L2_M2M_SRC].eos_buffer_in_use = false;\n+\t\treturn;\n+\t}\n+\n+\tif (status) {\n+\t\t/* error in transfer */\n+\t\tif (buf)\n+\t\t\t/* there was a buffer with the error so return it */\n+\t\t\tvb2_buffer_done(&buf->m2m.vb.vb2_buf,\n+\t\t\t\t\tVB2_BUF_STATE_ERROR);\n+\t\treturn;\n+\t}\n+\tif (mmal_buf->cmd) {\n+\t\tv4l2_err(&ctx->dev->v4l2_dev, \"%s: Not expecting cmd msgs on ip callback - %08x\\n\",\n+\t\t\t __func__, mmal_buf->cmd);\n+\t\t/*\n+\t\t * CHECKME: Should we return here. The buffer shouldn't have a\n+\t\t * message context or vb2 buf associated.\n+\t\t */\n+\t}\n+\n+\tv4l2_dbg(3, debug, &ctx->dev->v4l2_dev, \"%s: no error. Return buffer %p\\n\",\n+\t\t __func__, &buf->m2m.vb.vb2_buf);\n+\tvb2_buffer_done(&buf->m2m.vb.vb2_buf, VB2_BUF_STATE_DONE);\n+\n+\tctx->num_ip_buffers++;\n+\tv4l2_dbg(2, debug, &ctx->dev->v4l2_dev, \"%s: done %d input buffers\\n\",\n+\t\t __func__, ctx->num_ip_buffers);\n+\n+\tif (!port->enabled)\n+\t\tcomplete(&ctx->frame_cmplt);\n+}\n+\n+static void queue_res_chg_event(struct bcm2835_codec_ctx *ctx)\n+{\n+\tstatic const struct v4l2_event ev_src_ch = {\n+\t\t.type = V4L2_EVENT_SOURCE_CHANGE,\n+\t\t.u.src_change.changes =\n+\t\tV4L2_EVENT_SRC_CH_RESOLUTION,\n+\t};\n+\n+\tv4l2_event_queue_fh(&ctx->fh, &ev_src_ch);\n+}\n+\n+static void send_eos_event(struct bcm2835_codec_ctx *ctx)\n+{\n+\tstatic const struct v4l2_event ev = {\n+\t\t.type = V4L2_EVENT_EOS,\n+\t};\n+\n+\tv4l2_dbg(1, debug, &ctx->dev->v4l2_dev, \"Sending EOS event\\n\");\n+\n+\tv4l2_event_queue_fh(&ctx->fh, &ev);\n+}\n+\n+static void color_mmal2v4l(struct bcm2835_codec_ctx *ctx, u32 mmal_color_space)\n+{\n+\tswitch (mmal_color_space) {\n+\tcase MMAL_COLOR_SPACE_ITUR_BT601:\n+\t\tctx->colorspace = V4L2_COLORSPACE_REC709;\n+\t\tctx->xfer_func = V4L2_XFER_FUNC_709;\n+\t\tctx->ycbcr_enc = V4L2_YCBCR_ENC_601;\n+\t\tctx->quant = V4L2_QUANTIZATION_LIM_RANGE;\n+\t\tbreak;\n+\n+\tcase MMAL_COLOR_SPACE_ITUR_BT709:\n+\t\tctx->colorspace = V4L2_COLORSPACE_REC709;\n+\t\tctx->xfer_func = V4L2_XFER_FUNC_709;\n+\t\tctx->ycbcr_enc = V4L2_YCBCR_ENC_709;\n+\t\tctx->quant = V4L2_QUANTIZATION_LIM_RANGE;\n+\t\tbreak;\n+\t}\n+}\n+\n+static void handle_fmt_changed(struct bcm2835_codec_ctx *ctx,\n+\t\t\t       struct mmal_buffer *mmal_buf)\n+{\n+\tstruct bcm2835_codec_q_data *q_data;\n+\tstruct mmal_msg_event_format_changed *format =\n+\t\t(struct mmal_msg_event_format_changed *)mmal_buf->buffer;\n+\tv4l2_dbg(1, debug, &ctx->dev->v4l2_dev, \"%s: Format changed: buff size min %u, rec %u, buff num min %u, rec %u\\n\",\n+\t\t __func__,\n+\t\t format->buffer_size_min,\n+\t\t format->buffer_size_recommended,\n+\t\t format->buffer_num_min,\n+\t\t format->buffer_num_recommended\n+\t\t);\n+\tif (format->format.type != MMAL_ES_TYPE_VIDEO) {\n+\t\tv4l2_dbg(1, debug, &ctx->dev->v4l2_dev, \"%s: Format changed but not video %u\\n\",\n+\t\t\t __func__, format->format.type);\n+\t\treturn;\n+\t}\n+\tv4l2_dbg(1, debug, &ctx->dev->v4l2_dev, \"%s: Format changed to %ux%u, crop %ux%u, colourspace %08X\\n\",\n+\t\t __func__, format->es.video.width, format->es.video.height,\n+\t\t format->es.video.crop.width, format->es.video.crop.height,\n+\t\t format->es.video.color_space);\n+\n+\tq_data = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE);\n+\tv4l2_dbg(1, debug, &ctx->dev->v4l2_dev, \"%s: Format was %ux%u, crop %ux%u\\n\",\n+\t\t __func__, q_data->bytesperline, q_data->height,\n+\t\t q_data->crop_width, q_data->crop_height);\n+\n+\tq_data->crop_width = format->es.video.crop.width;\n+\tq_data->crop_height = format->es.video.crop.height;\n+\tq_data->bytesperline = get_bytesperline(format->es.video.width,\n+\t\t\t\t\t\tq_data->fmt);\n+\n+\tq_data->height = format->es.video.height;\n+\tq_data->sizeimage = format->buffer_size_min;\n+\tif (format->es.video.color_space)\n+\t\tcolor_mmal2v4l(ctx, format->es.video.color_space);\n+\n+\tqueue_res_chg_event(ctx);\n+}\n+\n+static void op_buffer_cb(struct vchiq_mmal_instance *instance,\n+\t\t\t struct vchiq_mmal_port *port, int status,\n+\t\t\t struct mmal_buffer *mmal_buf)\n+{\n+\tstruct bcm2835_codec_ctx *ctx = port->cb_ctx;\n+\tstruct m2m_mmal_buffer *buf;\n+\tstruct vb2_v4l2_buffer *vb2;\n+\n+\tv4l2_dbg(2, debug, &ctx->dev->v4l2_dev,\n+\t\t \"%s: status:%d, buf:%p, length:%lu, flags %u, pts %lld\\n\",\n+\t\t __func__, status, mmal_buf, mmal_buf->length,\n+\t\t mmal_buf->mmal_flags, mmal_buf->pts);\n+\n+\tbuf = container_of(mmal_buf, struct m2m_mmal_buffer, mmal);\n+\tvb2 = &buf->m2m.vb;\n+\n+\tif (status) {\n+\t\t/* error in transfer */\n+\t\tif (vb2) {\n+\t\t\t/* there was a buffer with the error so return it */\n+\t\t\tvb2_buffer_done(&vb2->vb2_buf, VB2_BUF_STATE_ERROR);\n+\t\t}\n+\t\treturn;\n+\t}\n+\n+\tif (mmal_buf->cmd) {\n+\t\tswitch (mmal_buf->cmd) {\n+\t\tcase MMAL_EVENT_FORMAT_CHANGED:\n+\t\t{\n+\t\t\thandle_fmt_changed(ctx, mmal_buf);\n+\t\t\tbreak;\n+\t\t}\n+\t\tdefault:\n+\t\t\tv4l2_err(&ctx->dev->v4l2_dev, \"%s: Unexpected event on output callback - %08x\\n\",\n+\t\t\t\t __func__, mmal_buf->cmd);\n+\t\t\tbreak;\n+\t\t}\n+\t\treturn;\n+\t}\n+\n+\tv4l2_dbg(3, debug, &ctx->dev->v4l2_dev, \"%s: length %lu, flags %x, idx %u\\n\",\n+\t\t __func__, mmal_buf->length, mmal_buf->mmal_flags,\n+\t\t vb2->vb2_buf.index);\n+\n+\tif (mmal_buf->length == 0) {\n+\t\t/* stream ended, or buffer being returned during disable. */\n+\t\tv4l2_dbg(2, debug, &ctx->dev->v4l2_dev, \"%s: Empty buffer - flags %04x\",\n+\t\t\t __func__, mmal_buf->mmal_flags);\n+\t\tif (!mmal_buf->mmal_flags & MMAL_BUFFER_HEADER_FLAG_EOS) {\n+\t\t\tvb2_buffer_done(&vb2->vb2_buf, VB2_BUF_STATE_ERROR);\n+\t\t\tif (!port->enabled)\n+\t\t\t\tcomplete(&ctx->frame_cmplt);\n+\t\t\treturn;\n+\t\t}\n+\t}\n+\tif (mmal_buf->mmal_flags & MMAL_BUFFER_HEADER_FLAG_EOS) {\n+\t\t/* EOS packet from the VPU */\n+\t\tsend_eos_event(ctx);\n+\t\tvb2->flags |= V4L2_BUF_FLAG_LAST;\n+\t}\n+\n+\t/* vb2 timestamps in nsecs, mmal in usecs */\n+\tvb2->vb2_buf.timestamp = mmal_buf->pts * 1000;\n+\n+\tvb2_set_plane_payload(&vb2->vb2_buf, 0, mmal_buf->length);\n+\tif (mmal_buf->mmal_flags & MMAL_BUFFER_HEADER_FLAG_KEYFRAME)\n+\t\tvb2->flags |= V4L2_BUF_FLAG_KEYFRAME;\n+\n+\tvb2_buffer_done(&vb2->vb2_buf, VB2_BUF_STATE_DONE);\n+\tctx->num_op_buffers++;\n+\n+\tv4l2_dbg(2, debug, &ctx->dev->v4l2_dev, \"%s: done %d output buffers\\n\",\n+\t\t __func__, ctx->num_op_buffers);\n+\n+\tif (!port->enabled)\n+\t\tcomplete(&ctx->frame_cmplt);\n+}\n+\n+/* vb2_to_mmal_buffer() - converts vb2 buffer header to MMAL\n+ *\n+ * Copies all the required fields from a VB2 buffer to the MMAL buffer header,\n+ * ready for sending to the VPU.\n+ */\n+static void vb2_to_mmal_buffer(struct m2m_mmal_buffer *buf,\n+\t\t\t       struct vb2_v4l2_buffer *vb2)\n+{\n+\tu64 pts;\n+\n+\tbuf->mmal.mmal_flags = 0;\n+\tif (vb2->flags & V4L2_BUF_FLAG_KEYFRAME)\n+\t\tbuf->mmal.mmal_flags |= MMAL_BUFFER_HEADER_FLAG_KEYFRAME;\n+\n+\t/*\n+\t * Adding this means that the data must be framed correctly as one frame\n+\t * per buffer. The underlying decoder has no such requirement, but it\n+\t * will reduce latency as the bistream parser will be kicked immediately\n+\t * to parse the frame, rather than relying on its own heuristics for\n+\t * when to wake up.\n+\t */\n+\tbuf->mmal.mmal_flags |= MMAL_BUFFER_HEADER_FLAG_FRAME_END;\n+\n+\tbuf->mmal.length = vb2->vb2_buf.planes[0].bytesused;\n+\t/*\n+\t * Minor ambiguity in the V4L2 spec as to whether passing in a 0 length\n+\t * buffer, or one with V4L2_BUF_FLAG_LAST set denotes end of stream.\n+\t * Handle either.\n+\t */\n+\tif (!buf->mmal.length || vb2->flags & V4L2_BUF_FLAG_LAST)\n+\t\tbuf->mmal.mmal_flags |= MMAL_BUFFER_HEADER_FLAG_EOS;\n+\n+\t/* vb2 timestamps in nsecs, mmal in usecs */\n+\tpts = vb2->vb2_buf.timestamp;\n+\tdo_div(pts, 1000);\n+\tbuf->mmal.pts = pts;\n+\tbuf->mmal.dts = MMAL_TIME_UNKNOWN;\n+}\n+\n+/* device_run() - prepares and starts the device\n+ *\n+ * This simulates all the immediate preparations required before starting\n+ * a device. This will be called by the framework when it decides to schedule\n+ * a particular instance.\n+ */\n+static void device_run(void *priv)\n+{\n+\tstruct bcm2835_codec_ctx *ctx = priv;\n+\tstruct bcm2835_codec_dev *dev = ctx->dev;\n+\tstruct vb2_v4l2_buffer *src_buf, *dst_buf;\n+\tstruct m2m_mmal_buffer *src_m2m_buf = NULL, *dst_m2m_buf = NULL;\n+\tstruct v4l2_m2m_buffer *m2m;\n+\tint ret;\n+\n+\tv4l2_dbg(3, debug, &ctx->dev->v4l2_dev, \"%s: off we go\\n\", __func__);\n+\n+\tsrc_buf = v4l2_m2m_buf_remove(&ctx->fh.m2m_ctx->out_q_ctx);\n+\tif (src_buf) {\n+\t\tm2m = container_of(src_buf, struct v4l2_m2m_buffer, vb);\n+\t\tsrc_m2m_buf = container_of(m2m, struct m2m_mmal_buffer, m2m);\n+\t\tvb2_to_mmal_buffer(src_m2m_buf, src_buf);\n+\n+\t\tret = vchiq_mmal_submit_buffer(dev->instance,\n+\t\t\t\t\t       &ctx->component->input[0],\n+\t\t\t\t\t       &src_m2m_buf->mmal);\n+\t\tv4l2_dbg(3, debug, &ctx->dev->v4l2_dev, \"%s: Submitted ip buffer len %lu, pts %llu, flags %04x\\n\",\n+\t\t\t __func__, src_m2m_buf->mmal.length,\n+\t\t\t src_m2m_buf->mmal.pts, src_m2m_buf->mmal.mmal_flags);\n+\t\tif (ret)\n+\t\t\tv4l2_err(&ctx->dev->v4l2_dev, \"%s: Failed submitting ip buffer\\n\",\n+\t\t\t\t __func__);\n+\t}\n+\n+\tdst_buf = v4l2_m2m_buf_remove(&ctx->fh.m2m_ctx->cap_q_ctx);\n+\tif (dst_buf) {\n+\t\tm2m = container_of(dst_buf, struct v4l2_m2m_buffer, vb);\n+\t\tdst_m2m_buf = container_of(m2m, struct m2m_mmal_buffer, m2m);\n+\t\tvb2_to_mmal_buffer(dst_m2m_buf, dst_buf);\n+\n+\t\tret = vchiq_mmal_submit_buffer(dev->instance,\n+\t\t\t\t\t       &ctx->component->output[0],\n+\t\t\t\t\t       &dst_m2m_buf->mmal);\n+\t\tif (ret)\n+\t\t\tv4l2_err(&ctx->dev->v4l2_dev, \"%s: Failed submitting op buffer\\n\",\n+\t\t\t\t __func__);\n+\t}\n+\n+\tv4l2_dbg(3, debug, &ctx->dev->v4l2_dev, \"%s: Submitted src %p, dst %p\\n\",\n+\t\t __func__, src_m2m_buf, dst_m2m_buf);\n+\n+\t/* Complete the job here. */\n+\tv4l2_m2m_job_finish(ctx->dev->m2m_dev, ctx->fh.m2m_ctx);\n+}\n+\n+/*\n+ * video ioctls\n+ */\n+static int vidioc_querycap(struct file *file, void *priv,\n+\t\t\t   struct v4l2_capability *cap)\n+{\n+\tstruct bcm2835_codec_dev *dev = video_drvdata(file);\n+\n+\tstrncpy(cap->driver, MEM2MEM_NAME, sizeof(cap->driver) - 1);\n+\tstrncpy(cap->card, dev->vfd.name, sizeof(cap->card) - 1);\n+\tsnprintf(cap->bus_info, sizeof(cap->bus_info), \"platform:%s\",\n+\t\t MEM2MEM_NAME);\n+\treturn 0;\n+}\n+\n+static int enum_fmt(struct v4l2_fmtdesc *f, struct bcm2835_codec_ctx *ctx,\n+\t\t    bool capture)\n+{\n+\tstruct bcm2835_codec_fmt *fmt;\n+\tstruct bcm2835_codec_fmt_list *fmts =\n+\t\t\t\t\tget_format_list(ctx->dev, capture);\n+\n+\tif (f->index < fmts->num_entries) {\n+\t\t/* Format found */\n+\t\tfmt = &fmts->list[f->index];\n+\t\tf->pixelformat = fmt->fourcc;\n+\t\tf->flags = fmt->flags;\n+\t\treturn 0;\n+\t}\n+\n+\t/* Format not found */\n+\treturn -EINVAL;\n+}\n+\n+static int vidioc_enum_fmt_vid_cap(struct file *file, void *priv,\n+\t\t\t\t   struct v4l2_fmtdesc *f)\n+{\n+\tstruct bcm2835_codec_ctx *ctx = file2ctx(file);\n+\n+\treturn enum_fmt(f, ctx, true);\n+}\n+\n+static int vidioc_enum_fmt_vid_out(struct file *file, void *priv,\n+\t\t\t\t   struct v4l2_fmtdesc *f)\n+{\n+\tstruct bcm2835_codec_ctx *ctx = file2ctx(file);\n+\n+\treturn enum_fmt(f, ctx, false);\n+}\n+\n+static int vidioc_g_fmt(struct bcm2835_codec_ctx *ctx, struct v4l2_format *f)\n+{\n+\tstruct vb2_queue *vq;\n+\tstruct bcm2835_codec_q_data *q_data;\n+\n+\tvq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type);\n+\tif (!vq)\n+\t\treturn -EINVAL;\n+\n+\tq_data = get_q_data(ctx, f->type);\n+\n+\tf->fmt.pix_mp.width\t\t\t= q_data->crop_width;\n+\tf->fmt.pix_mp.height\t\t\t= q_data->height;\n+\tf->fmt.pix_mp.pixelformat\t\t= q_data->fmt->fourcc;\n+\tf->fmt.pix_mp.field\t\t\t= V4L2_FIELD_NONE;\n+\tf->fmt.pix_mp.colorspace\t\t= ctx->colorspace;\n+\tf->fmt.pix_mp.plane_fmt[0].sizeimage\t= q_data->sizeimage;\n+\tf->fmt.pix_mp.plane_fmt[0].bytesperline\t= q_data->bytesperline;\n+\tf->fmt.pix_mp.num_planes\t\t= 1;\n+\tf->fmt.pix_mp.ycbcr_enc\t\t\t= ctx->ycbcr_enc;\n+\tf->fmt.pix_mp.quantization\t\t= ctx->quant;\n+\tf->fmt.pix_mp.xfer_func\t\t\t= ctx->xfer_func;\n+\n+\tmemset(f->fmt.pix_mp.plane_fmt[0].reserved, 0,\n+\t       sizeof(f->fmt.pix_mp.plane_fmt[0].reserved));\n+\n+\treturn 0;\n+}\n+\n+static int vidioc_g_fmt_vid_out(struct file *file, void *priv,\n+\t\t\t\tstruct v4l2_format *f)\n+{\n+\treturn vidioc_g_fmt(file2ctx(file), f);\n+}\n+\n+static int vidioc_g_fmt_vid_cap(struct file *file, void *priv,\n+\t\t\t\tstruct v4l2_format *f)\n+{\n+\treturn vidioc_g_fmt(file2ctx(file), f);\n+}\n+\n+static int vidioc_try_fmt(struct bcm2835_codec_ctx *ctx, struct v4l2_format *f,\n+\t\t\t  struct bcm2835_codec_fmt *fmt)\n+{\n+\t/*\n+\t * The V4L2 specification requires the driver to correct the format\n+\t * struct if any of the dimensions is unsupported\n+\t */\n+\tif (f->fmt.pix_mp.width > MAX_W)\n+\t\tf->fmt.pix_mp.width = MAX_W;\n+\tif (f->fmt.pix_mp.height > MAX_H)\n+\t\tf->fmt.pix_mp.height = MAX_H;\n+\n+\tif (!fmt->flags & V4L2_FMT_FLAG_COMPRESSED) {\n+\t\t/* Only clip min w/h on capture. Treat 0x0 as unknown. */\n+\t\tif (f->fmt.pix_mp.width < MIN_W)\n+\t\t\tf->fmt.pix_mp.width = MIN_W;\n+\t\tif (f->fmt.pix_mp.height < MIN_H)\n+\t\t\tf->fmt.pix_mp.height = MIN_H;\n+\n+\t\t/*\n+\t\t * For decoders the buffer must have a vertical alignment of 16\n+\t\t * lines.\n+\t\t * The selection will reflect any cropping rectangle when only\n+\t\t * some of the pixels are active.\n+\t\t */\n+\t\tif (ctx->dev->role == DECODE)\n+\t\t\tf->fmt.pix_mp.height = ALIGN(f->fmt.pix_mp.height, 16);\n+\t}\n+\tf->fmt.pix_mp.num_planes = 1;\n+\tf->fmt.pix_mp.plane_fmt[0].bytesperline =\n+\t\tget_bytesperline(f->fmt.pix_mp.width, fmt);\n+\tf->fmt.pix_mp.plane_fmt[0].sizeimage =\n+\t\tget_sizeimage(f->fmt.pix_mp.plane_fmt[0].bytesperline,\n+\t\t\t      f->fmt.pix_mp.width, f->fmt.pix_mp.height, fmt);\n+\tmemset(f->fmt.pix_mp.plane_fmt[0].reserved, 0,\n+\t       sizeof(f->fmt.pix_mp.plane_fmt[0].reserved));\n+\n+\tf->fmt.pix_mp.field = V4L2_FIELD_NONE;\n+\n+\treturn 0;\n+}\n+\n+static int vidioc_try_fmt_vid_cap(struct file *file, void *priv,\n+\t\t\t\t  struct v4l2_format *f)\n+{\n+\tstruct bcm2835_codec_fmt *fmt;\n+\tstruct bcm2835_codec_ctx *ctx = file2ctx(file);\n+\n+\tfmt = find_format(f, ctx->dev, true);\n+\tif (!fmt) {\n+\t\tf->fmt.pix_mp.pixelformat = get_default_format(ctx->dev,\n+\t\t\t\t\t\t\t       true)->fourcc;\n+\t\tfmt = find_format(f, ctx->dev, true);\n+\t}\n+\n+\treturn vidioc_try_fmt(ctx, f, fmt);\n+}\n+\n+static int vidioc_try_fmt_vid_out(struct file *file, void *priv,\n+\t\t\t\t  struct v4l2_format *f)\n+{\n+\tstruct bcm2835_codec_fmt *fmt;\n+\tstruct bcm2835_codec_ctx *ctx = file2ctx(file);\n+\n+\tfmt = find_format(f, ctx->dev, false);\n+\tif (!fmt) {\n+\t\tf->fmt.pix_mp.pixelformat = get_default_format(ctx->dev,\n+\t\t\t\t\t\t\t       false)->fourcc;\n+\t\tfmt = find_format(f, ctx->dev, false);\n+\t}\n+\n+\tif (!f->fmt.pix_mp.colorspace)\n+\t\tf->fmt.pix_mp.colorspace = ctx->colorspace;\n+\n+\treturn vidioc_try_fmt(ctx, f, fmt);\n+}\n+\n+static int vidioc_s_fmt(struct bcm2835_codec_ctx *ctx, struct v4l2_format *f,\n+\t\t\tunsigned int requested_height)\n+{\n+\tstruct bcm2835_codec_q_data *q_data;\n+\tstruct vb2_queue *vq;\n+\tstruct vchiq_mmal_port *port;\n+\tbool update_capture_port = false;\n+\tint ret;\n+\n+\tv4l2_dbg(1, debug, &ctx->dev->v4l2_dev,\t\"Setting format for type %d, wxh: %dx%d, fmt: %08x, size %u\\n\",\n+\t\t f->type, f->fmt.pix_mp.width, f->fmt.pix_mp.height,\n+\t\t f->fmt.pix_mp.pixelformat,\n+\t\t f->fmt.pix_mp.plane_fmt[0].sizeimage);\n+\n+\tvq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type);\n+\tif (!vq)\n+\t\treturn -EINVAL;\n+\n+\tq_data = get_q_data(ctx, f->type);\n+\tif (!q_data)\n+\t\treturn -EINVAL;\n+\n+\tif (vb2_is_busy(vq)) {\n+\t\tv4l2_err(&ctx->dev->v4l2_dev, \"%s queue busy\\n\", __func__);\n+\t\treturn -EBUSY;\n+\t}\n+\n+\tq_data->fmt = find_format(f, ctx->dev,\n+\t\t\t\t  f->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE);\n+\tq_data->crop_width = f->fmt.pix_mp.width;\n+\tq_data->height = f->fmt.pix_mp.height;\n+\tif (!q_data->selection_set)\n+\t\tq_data->crop_height = requested_height;\n+\n+\t/*\n+\t * Copying the behaviour of vicodec which retains a single set of\n+\t * colorspace parameters for both input and output.\n+\t */\n+\tctx->colorspace = f->fmt.pix_mp.colorspace;\n+\tctx->xfer_func = f->fmt.pix_mp.xfer_func;\n+\tctx->ycbcr_enc = f->fmt.pix_mp.ycbcr_enc;\n+\tctx->quant = f->fmt.pix_mp.quantization;\n+\n+\t/* All parameters should have been set correctly by try_fmt */\n+\tq_data->bytesperline = f->fmt.pix_mp.plane_fmt[0].bytesperline;\n+\tq_data->sizeimage = f->fmt.pix_mp.plane_fmt[0].sizeimage;\n+\n+\tv4l2_dbg(1, debug, &ctx->dev->v4l2_dev,\t\"Calulated bpl as %u, size %u\\n\",\n+\t\t q_data->bytesperline, q_data->sizeimage);\n+\n+\tif (ctx->dev->role == DECODE &&\n+\t    q_data->fmt->flags & V4L2_FMT_FLAG_COMPRESSED &&\n+\t    q_data->crop_width && q_data->height) {\n+\t\t/*\n+\t\t * On the decoder, if provided with a resolution on the input\n+\t\t * side, then replicate that to the output side.\n+\t\t * GStreamer appears not to support V4L2_EVENT_SOURCE_CHANGE,\n+\t\t * nor set up a resolution on the output side, therefore\n+\t\t * we can't decode anything at a resolution other than the\n+\t\t * default one.\n+\t\t */\n+\t\tstruct bcm2835_codec_q_data *q_data_dst =\n+\t\t\t\t\t\t&ctx->q_data[V4L2_M2M_DST];\n+\n+\t\tq_data_dst->crop_width = q_data->crop_width;\n+\t\tq_data_dst->crop_height = q_data->crop_height;\n+\t\tq_data_dst->height = ALIGN(q_data->crop_height, 16);\n+\n+\t\tq_data_dst->bytesperline =\n+\t\t\tget_bytesperline(f->fmt.pix_mp.width, q_data_dst->fmt);\n+\t\tq_data_dst->sizeimage = get_sizeimage(q_data_dst->bytesperline,\n+\t\t\t\t\t\t      q_data_dst->crop_width,\n+\t\t\t\t\t\t      q_data_dst->height,\n+\t\t\t\t\t\t      q_data_dst->fmt);\n+\t\tupdate_capture_port = true;\n+\t}\n+\n+\t/* If we have a component then setup the port as well */\n+\tport = get_port_data(ctx, vq->type);\n+\tif (!port)\n+\t\treturn 0;\n+\n+\tsetup_mmal_port_format(ctx, q_data, port);\n+\tret = vchiq_mmal_port_set_format(ctx->dev->instance, port);\n+\tif (ret) {\n+\t\tv4l2_err(&ctx->dev->v4l2_dev, \"%s: Failed vchiq_mmal_port_set_format on port, ret %d\\n\",\n+\t\t\t __func__, ret);\n+\t\tret = -EINVAL;\n+\t}\n+\n+\tif (q_data->sizeimage < port->minimum_buffer.size) {\n+\t\tv4l2_err(&ctx->dev->v4l2_dev, \"%s: Current buffer size of %u < min buf size %u - driver mismatch to MMAL\\n\",\n+\t\t\t __func__, q_data->sizeimage,\n+\t\t\t port->minimum_buffer.size);\n+\t}\n+\n+\tv4l2_dbg(1, debug, &ctx->dev->v4l2_dev,\t\"Set format for type %d, wxh: %dx%d, fmt: %08x, size %u\\n\",\n+\t\t f->type, q_data->crop_width, q_data->height,\n+\t\t q_data->fmt->fourcc, q_data->sizeimage);\n+\n+\tif (update_capture_port) {\n+\t\tstruct vchiq_mmal_port *port_dst = &ctx->component->output[0];\n+\t\tstruct bcm2835_codec_q_data *q_data_dst =\n+\t\t\t\t\t\t&ctx->q_data[V4L2_M2M_DST];\n+\n+\t\tsetup_mmal_port_format(ctx, q_data_dst, port_dst);\n+\t\tret = vchiq_mmal_port_set_format(ctx->dev->instance, port_dst);\n+\t\tif (ret) {\n+\t\t\tv4l2_err(&ctx->dev->v4l2_dev, \"%s: Failed vchiq_mmal_port_set_format on output port, ret %d\\n\",\n+\t\t\t\t __func__, ret);\n+\t\t\tret = -EINVAL;\n+\t\t}\n+\t}\n+\treturn ret;\n+}\n+\n+static int vidioc_s_fmt_vid_cap(struct file *file, void *priv,\n+\t\t\t\tstruct v4l2_format *f)\n+{\n+\tunsigned int height = f->fmt.pix_mp.height;\n+\tint ret;\n+\n+\tret = vidioc_try_fmt_vid_cap(file, priv, f);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\treturn vidioc_s_fmt(file2ctx(file), f, height);\n+}\n+\n+static int vidioc_s_fmt_vid_out(struct file *file, void *priv,\n+\t\t\t\tstruct v4l2_format *f)\n+{\n+\tunsigned int height = f->fmt.pix_mp.height;\n+\tint ret;\n+\n+\tret = vidioc_try_fmt_vid_out(file, priv, f);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = vidioc_s_fmt(file2ctx(file), f, height);\n+\treturn ret;\n+}\n+\n+static int vidioc_g_selection(struct file *file, void *priv,\n+\t\t\t      struct v4l2_selection *s)\n+{\n+\tstruct bcm2835_codec_ctx *ctx = file2ctx(file);\n+\tstruct bcm2835_codec_q_data *q_data;\n+\n+\t/*\n+\t * The selection API takes V4L2_BUF_TYPE_VIDEO_CAPTURE and\n+\t * V4L2_BUF_TYPE_VIDEO_OUTPUT, even if the device implements the MPLANE\n+\t * API. The V4L2 core will have converted the MPLANE variants to\n+\t * non-MPLANE.\n+\t * Open code this instead of using get_q_data in this case.\n+\t */\n+\tswitch (s->type) {\n+\tcase V4L2_BUF_TYPE_VIDEO_CAPTURE:\n+\t\t/* CAPTURE on encoder is not valid. */\n+\t\tif (ctx->dev->role == ENCODE)\n+\t\t\treturn -EINVAL;\n+\t\tq_data = &ctx->q_data[V4L2_M2M_DST];\n+\t\tbreak;\n+\tcase V4L2_BUF_TYPE_VIDEO_OUTPUT:\n+\t\t/* OUTPUT on deoder is not valid. */\n+\t\tif (ctx->dev->role == DECODE)\n+\t\t\treturn -EINVAL;\n+\t\tq_data = &ctx->q_data[V4L2_M2M_SRC];\n+\t\tbreak;\n+\tdefault:\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tswitch (ctx->dev->role) {\n+\tcase DECODE:\n+\t\tswitch (s->target) {\n+\t\tcase V4L2_SEL_TGT_COMPOSE_DEFAULT:\n+\t\tcase V4L2_SEL_TGT_COMPOSE:\n+\t\t\ts->r.left = 0;\n+\t\t\ts->r.top = 0;\n+\t\t\ts->r.width = q_data->crop_width;\n+\t\t\ts->r.height = q_data->crop_height;\n+\t\t\tbreak;\n+\t\tcase V4L2_SEL_TGT_COMPOSE_BOUNDS:\n+\t\t\ts->r.left = 0;\n+\t\t\ts->r.top = 0;\n+\t\t\ts->r.width = q_data->crop_width;\n+\t\t\ts->r.height = q_data->crop_height;\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t\tbreak;\n+\tcase ENCODE:\n+\t\tswitch (s->target) {\n+\t\tcase V4L2_SEL_TGT_CROP_DEFAULT:\n+\t\tcase V4L2_SEL_TGT_CROP_BOUNDS:\n+\t\t\ts->r.top = 0;\n+\t\t\ts->r.left = 0;\n+\t\t\ts->r.width = q_data->bytesperline;\n+\t\t\ts->r.height = q_data->height;\n+\t\t\tbreak;\n+\t\tcase V4L2_SEL_TGT_CROP:\n+\t\t\ts->r.top = 0;\n+\t\t\ts->r.left = 0;\n+\t\t\ts->r.width = q_data->crop_width;\n+\t\t\ts->r.height = q_data->crop_height;\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t\tbreak;\n+\tcase ISP:\n+\t\tbreak;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int vidioc_s_selection(struct file *file, void *priv,\n+\t\t\t      struct v4l2_selection *s)\n+{\n+\tstruct bcm2835_codec_ctx *ctx = file2ctx(file);\n+\tstruct bcm2835_codec_q_data *q_data = NULL;\n+\n+\t/*\n+\t * The selection API takes V4L2_BUF_TYPE_VIDEO_CAPTURE and\n+\t * V4L2_BUF_TYPE_VIDEO_OUTPUT, even if the device implements the MPLANE\n+\t * API. The V4L2 core will have converted the MPLANE variants to\n+\t * non-MPLANE.\n+\t *\n+\t * Open code this instead of using get_q_data in this case.\n+\t */\n+\tswitch (s->type) {\n+\tcase V4L2_BUF_TYPE_VIDEO_CAPTURE:\n+\t\t/* CAPTURE on encoder is not valid. */\n+\t\tif (ctx->dev->role == ENCODE)\n+\t\t\treturn -EINVAL;\n+\t\tq_data = &ctx->q_data[V4L2_M2M_DST];\n+\t\tbreak;\n+\tcase V4L2_BUF_TYPE_VIDEO_OUTPUT:\n+\t\t/* OUTPUT on deoder is not valid. */\n+\t\tif (ctx->dev->role == DECODE)\n+\t\t\treturn -EINVAL;\n+\t\tq_data = &ctx->q_data[V4L2_M2M_SRC];\n+\t\tbreak;\n+\tdefault:\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tv4l2_dbg(1, debug, &ctx->dev->v4l2_dev, \"%s: ctx %p, type %d, q_data %p, target %d, rect x/y %d/%d, w/h %ux%u\\n\",\n+\t\t __func__, ctx, s->type, q_data, s->target, s->r.left, s->r.top,\n+\t\t s->r.width, s->r.height);\n+\n+\tswitch (ctx->dev->role) {\n+\tcase DECODE:\n+\t\tswitch (s->target) {\n+\t\tcase V4L2_SEL_TGT_COMPOSE:\n+\t\t\t/* Accept cropped image */\n+\t\t\ts->r.left = 0;\n+\t\t\ts->r.top = 0;\n+\t\t\ts->r.width = min(s->r.width, q_data->crop_width);\n+\t\t\ts->r.height = min(s->r.height, q_data->height);\n+\t\t\tq_data->crop_width = s->r.width;\n+\t\t\tq_data->crop_height = s->r.height;\n+\t\t\tq_data->selection_set = true;\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t\tbreak;\n+\tcase ENCODE:\n+\t\tswitch (s->target) {\n+\t\tcase V4L2_SEL_TGT_CROP:\n+\t\t\t/* Only support crop from (0,0) */\n+\t\t\ts->r.top = 0;\n+\t\t\ts->r.left = 0;\n+\t\t\ts->r.width = min(s->r.width, q_data->crop_width);\n+\t\t\ts->r.height = min(s->r.height, q_data->crop_height);\n+\t\t\tq_data->crop_width = s->r.width;\n+\t\t\tq_data->crop_height = s->r.height;\n+\t\t\tq_data->selection_set = true;\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t\tbreak;\n+\tcase ISP:\n+\t\tbreak;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int vidioc_s_parm(struct file *file, void *priv,\n+\t\t\t struct v4l2_streamparm *parm)\n+{\n+\tstruct bcm2835_codec_ctx *ctx = file2ctx(file);\n+\n+\tif (parm->type != V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE)\n+\t\treturn -EINVAL;\n+\n+\tif (!parm->parm.output.timeperframe.denominator ||\n+\t    !parm->parm.output.timeperframe.numerator)\n+\t\treturn -EINVAL;\n+\n+\tctx->framerate_num =\n+\t\t\tparm->parm.output.timeperframe.denominator;\n+\tctx->framerate_denom =\n+\t\t\tparm->parm.output.timeperframe.numerator;\n+\n+\tparm->parm.output.capability = V4L2_CAP_TIMEPERFRAME;\n+\n+\treturn 0;\n+}\n+\n+static int vidioc_g_parm(struct file *file, void *priv,\n+\t\t\t struct v4l2_streamparm *parm)\n+{\n+\tstruct bcm2835_codec_ctx *ctx = file2ctx(file);\n+\n+\tif (parm->type != V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE)\n+\t\treturn -EINVAL;\n+\n+\tparm->parm.output.capability = V4L2_CAP_TIMEPERFRAME;\n+\tparm->parm.output.timeperframe.denominator =\n+\t\t\tctx->framerate_num;\n+\tparm->parm.output.timeperframe.numerator =\n+\t\t\tctx->framerate_denom;\n+\n+\treturn 0;\n+}\n+\n+static int vidioc_subscribe_evt(struct v4l2_fh *fh,\n+\t\t\t\tconst struct v4l2_event_subscription *sub)\n+{\n+\tswitch (sub->type) {\n+\tcase V4L2_EVENT_EOS:\n+\t\treturn v4l2_event_subscribe(fh, sub, 2, NULL);\n+\tcase V4L2_EVENT_SOURCE_CHANGE:\n+\t\treturn v4l2_src_change_event_subscribe(fh, sub);\n+\tdefault:\n+\t\treturn v4l2_ctrl_subscribe_event(fh, sub);\n+\t}\n+}\n+\n+static int bcm2835_codec_set_level_profile(struct bcm2835_codec_ctx *ctx,\n+\t\t\t\t\t   struct v4l2_ctrl *ctrl)\n+{\n+\tstruct mmal_parameter_video_profile param;\n+\tint param_size = sizeof(param);\n+\tint ret;\n+\n+\t/*\n+\t * Level and Profile are set via the same MMAL parameter.\n+\t * Retrieve the current settings and amend the one that has changed.\n+\t */\n+\tret = vchiq_mmal_port_parameter_get(ctx->dev->instance,\n+\t\t\t\t\t    &ctx->component->output[0],\n+\t\t\t\t\t    MMAL_PARAMETER_PROFILE,\n+\t\t\t\t\t    &param,\n+\t\t\t\t\t    &param_size);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tswitch (ctrl->id) {\n+\tcase V4L2_CID_MPEG_VIDEO_H264_PROFILE:\n+\t\tswitch (ctrl->val) {\n+\t\tcase V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE:\n+\t\t\tparam.profile = MMAL_VIDEO_PROFILE_H264_BASELINE;\n+\t\t\tbreak;\n+\t\tcase V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_BASELINE:\n+\t\t\tparam.profile =\n+\t\t\t\tMMAL_VIDEO_PROFILE_H264_CONSTRAINED_BASELINE;\n+\t\t\tbreak;\n+\t\tcase V4L2_MPEG_VIDEO_H264_PROFILE_MAIN:\n+\t\t\tparam.profile = MMAL_VIDEO_PROFILE_H264_MAIN;\n+\t\t\tbreak;\n+\t\tcase V4L2_MPEG_VIDEO_H264_PROFILE_HIGH:\n+\t\t\tparam.profile = MMAL_VIDEO_PROFILE_H264_HIGH;\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\t/* Should never get here */\n+\t\t\tbreak;\n+\t\t}\n+\t\tbreak;\n+\n+\tcase V4L2_CID_MPEG_VIDEO_H264_LEVEL:\n+\t\tswitch (ctrl->val) {\n+\t\tcase V4L2_MPEG_VIDEO_H264_LEVEL_1_0:\n+\t\t\tparam.level = MMAL_VIDEO_LEVEL_H264_1;\n+\t\t\tbreak;\n+\t\tcase V4L2_MPEG_VIDEO_H264_LEVEL_1B:\n+\t\t\tparam.level = MMAL_VIDEO_LEVEL_H264_1b;\n+\t\t\tbreak;\n+\t\tcase V4L2_MPEG_VIDEO_H264_LEVEL_1_1:\n+\t\t\tparam.level = MMAL_VIDEO_LEVEL_H264_11;\n+\t\t\tbreak;\n+\t\tcase V4L2_MPEG_VIDEO_H264_LEVEL_1_2:\n+\t\t\tparam.level = MMAL_VIDEO_LEVEL_H264_12;\n+\t\t\tbreak;\n+\t\tcase V4L2_MPEG_VIDEO_H264_LEVEL_1_3:\n+\t\t\tparam.level = MMAL_VIDEO_LEVEL_H264_13;\n+\t\t\tbreak;\n+\t\tcase V4L2_MPEG_VIDEO_H264_LEVEL_2_0:\n+\t\t\tparam.level = MMAL_VIDEO_LEVEL_H264_2;\n+\t\t\tbreak;\n+\t\tcase V4L2_MPEG_VIDEO_H264_LEVEL_2_1:\n+\t\t\tparam.level = MMAL_VIDEO_LEVEL_H264_21;\n+\t\t\tbreak;\n+\t\tcase V4L2_MPEG_VIDEO_H264_LEVEL_2_2:\n+\t\t\tparam.level = MMAL_VIDEO_LEVEL_H264_22;\n+\t\t\tbreak;\n+\t\tcase V4L2_MPEG_VIDEO_H264_LEVEL_3_0:\n+\t\t\tparam.level = MMAL_VIDEO_LEVEL_H264_3;\n+\t\t\tbreak;\n+\t\tcase V4L2_MPEG_VIDEO_H264_LEVEL_3_1:\n+\t\t\tparam.level = MMAL_VIDEO_LEVEL_H264_31;\n+\t\t\tbreak;\n+\t\tcase V4L2_MPEG_VIDEO_H264_LEVEL_3_2:\n+\t\t\tparam.level = MMAL_VIDEO_LEVEL_H264_32;\n+\t\t\tbreak;\n+\t\tcase V4L2_MPEG_VIDEO_H264_LEVEL_4_0:\n+\t\t\tparam.level = MMAL_VIDEO_LEVEL_H264_4;\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\t/* Should never get here */\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\tret = vchiq_mmal_port_parameter_set(ctx->dev->instance,\n+\t\t\t\t\t    &ctx->component->output[0],\n+\t\t\t\t\t    MMAL_PARAMETER_PROFILE,\n+\t\t\t\t\t    &param,\n+\t\t\t\t\t    param_size);\n+\n+\treturn ret;\n+}\n+\n+static int bcm2835_codec_s_ctrl(struct v4l2_ctrl *ctrl)\n+{\n+\tstruct bcm2835_codec_ctx *ctx =\n+\t\tcontainer_of(ctrl->handler, struct bcm2835_codec_ctx, hdl);\n+\tint ret = 0;\n+\n+\tswitch (ctrl->id) {\n+\tcase V4L2_CID_MPEG_VIDEO_BITRATE:\n+\t\tctx->bitrate = ctrl->val;\n+\t\tif (!ctx->component)\n+\t\t\tbreak;\n+\n+\t\tret = vchiq_mmal_port_parameter_set(ctx->dev->instance,\n+\t\t\t\t\t\t    &ctx->component->output[0],\n+\t\t\t\t\t\t    MMAL_PARAMETER_VIDEO_BIT_RATE,\n+\t\t\t\t\t\t    &ctrl->val,\n+\t\t\t\t\t\t    sizeof(ctrl->val));\n+\t\tbreak;\n+\n+\tcase V4L2_CID_MPEG_VIDEO_BITRATE_MODE: {\n+\t\tu32 bitrate_mode;\n+\n+\t\tif (!ctx->component)\n+\t\t\tbreak;\n+\n+\t\tswitch (ctrl->val) {\n+\t\tdefault:\n+\t\tcase V4L2_MPEG_VIDEO_BITRATE_MODE_VBR:\n+\t\t\tbitrate_mode = MMAL_VIDEO_RATECONTROL_VARIABLE;\n+\t\t\tbreak;\n+\t\tcase V4L2_MPEG_VIDEO_BITRATE_MODE_CBR:\n+\t\t\tbitrate_mode = MMAL_VIDEO_RATECONTROL_CONSTANT;\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\tret = vchiq_mmal_port_parameter_set(ctx->dev->instance,\n+\t\t\t\t\t\t    &ctx->component->output[0],\n+\t\t\t\t\t\t    MMAL_PARAMETER_RATECONTROL,\n+\t\t\t\t\t\t    &bitrate_mode,\n+\t\t\t\t\t\t    sizeof(bitrate_mode));\n+\t\tbreak;\n+\t}\n+\tcase V4L2_CID_MPEG_VIDEO_REPEAT_SEQ_HEADER:\n+\t\tif (!ctx->component)\n+\t\t\tbreak;\n+\n+\t\tret = vchiq_mmal_port_parameter_set(ctx->dev->instance,\n+\t\t\t\t\t\t    &ctx->component->output[0],\n+\t\t\t\t\t\t    MMAL_PARAMETER_VIDEO_ENCODE_INLINE_HEADER,\n+\t\t\t\t\t\t    &ctrl->val,\n+\t\t\t\t\t\t    sizeof(ctrl->val));\n+\t\tbreak;\n+\n+\tcase V4L2_CID_MPEG_VIDEO_H264_I_PERIOD:\n+\t\tif (!ctx->component)\n+\t\t\tbreak;\n+\n+\t\tret = vchiq_mmal_port_parameter_set(ctx->dev->instance,\n+\t\t\t\t\t\t    &ctx->component->output[0],\n+\t\t\t\t\t\t    MMAL_PARAMETER_INTRAPERIOD,\n+\t\t\t\t\t\t    &ctrl->val,\n+\t\t\t\t\t\t    sizeof(ctrl->val));\n+\t\tbreak;\n+\n+\tcase V4L2_CID_MPEG_VIDEO_H264_PROFILE:\n+\tcase V4L2_CID_MPEG_VIDEO_H264_LEVEL:\n+\t\tif (!ctx->component)\n+\t\t\tbreak;\n+\n+\t\tret = bcm2835_codec_set_level_profile(ctx, ctrl);\n+\t\tbreak;\n+\n+\tcase V4L2_CID_MPEG_VIDEO_FORCE_KEY_FRAME: {\n+\t\tu32 mmal_bool = 1;\n+\n+\t\tif (!ctx->component)\n+\t\t\tbreak;\n+\n+\t\tret = vchiq_mmal_port_parameter_set(ctx->dev->instance,\n+\t\t\t\t\t\t    &ctx->component->output[0],\n+\t\t\t\t\t\t    MMAL_PARAMETER_VIDEO_REQUEST_I_FRAME,\n+\t\t\t\t\t\t    &mmal_bool,\n+\t\t\t\t\t\t    sizeof(mmal_bool));\n+\t\tbreak;\n+\t}\n+\n+\tdefault:\n+\t\tv4l2_err(&ctx->dev->v4l2_dev, \"Invalid control\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (ret)\n+\t\tv4l2_err(&ctx->dev->v4l2_dev, \"Failed setting ctrl %08x, ret %d\\n\",\n+\t\t\t ctrl->id, ret);\n+\treturn ret ? -EINVAL : 0;\n+}\n+\n+static const struct v4l2_ctrl_ops bcm2835_codec_ctrl_ops = {\n+\t.s_ctrl = bcm2835_codec_s_ctrl,\n+};\n+\n+static int vidioc_try_decoder_cmd(struct file *file, void *priv,\n+\t\t\t\t  struct v4l2_decoder_cmd *cmd)\n+{\n+\tstruct bcm2835_codec_ctx *ctx = file2ctx(file);\n+\n+\tif (ctx->dev->role != DECODE)\n+\t\treturn -EINVAL;\n+\n+\tswitch (cmd->cmd) {\n+\tcase V4L2_DEC_CMD_STOP:\n+\t\tif (cmd->flags & V4L2_DEC_CMD_STOP_TO_BLACK) {\n+\t\t\tv4l2_err(&ctx->dev->v4l2_dev, \"%s: DEC cmd->flags=%u stop to black not supported\",\n+\t\t\t\t __func__, cmd->flags);\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t\tbreak;\n+\tcase V4L2_DEC_CMD_START:\n+\t\tbreak;\n+\tdefault:\n+\t\treturn -EINVAL;\n+\t}\n+\treturn 0;\n+}\n+\n+static int vidioc_decoder_cmd(struct file *file, void *priv,\n+\t\t\t      struct v4l2_decoder_cmd *cmd)\n+{\n+\tstruct bcm2835_codec_ctx *ctx = file2ctx(file);\n+\tstruct bcm2835_codec_q_data *q_data = &ctx->q_data[V4L2_M2M_SRC];\n+\tint ret;\n+\n+\tv4l2_dbg(2, debug, &ctx->dev->v4l2_dev, \"%s, cmd %u\", __func__,\n+\t\t cmd->cmd);\n+\tret = vidioc_try_decoder_cmd(file, priv, cmd);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tswitch (cmd->cmd) {\n+\tcase V4L2_DEC_CMD_STOP:\n+\t\tif (q_data->eos_buffer_in_use)\n+\t\t\tv4l2_err(&ctx->dev->v4l2_dev, \"EOS buffers already in use\\n\");\n+\t\tq_data->eos_buffer_in_use = true;\n+\n+\t\tq_data->eos_buffer.mmal.buffer_size = 0;\n+\t\tq_data->eos_buffer.mmal.length = 0;\n+\t\tq_data->eos_buffer.mmal.mmal_flags =\n+\t\t\t\t\t\tMMAL_BUFFER_HEADER_FLAG_EOS;\n+\t\tq_data->eos_buffer.mmal.pts = 0;\n+\t\tq_data->eos_buffer.mmal.dts = 0;\n+\n+\t\tif (!ctx->component)\n+\t\t\tbreak;\n+\n+\t\tret = vchiq_mmal_submit_buffer(ctx->dev->instance,\n+\t\t\t\t\t       &ctx->component->input[0],\n+\t\t\t\t\t       &q_data->eos_buffer.mmal);\n+\t\tif (ret)\n+\t\t\tv4l2_err(&ctx->dev->v4l2_dev,\n+\t\t\t\t \"%s: EOS buffer submit failed %d\\n\",\n+\t\t\t\t __func__, ret);\n+\n+\t\tbreak;\n+\n+\tcase V4L2_DEC_CMD_START:\n+\t\t/* Do we need to do anything here? */\n+\t\tbreak;\n+\n+\tdefault:\n+\t\treturn -EINVAL;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int vidioc_try_encoder_cmd(struct file *file, void *priv,\n+\t\t\t\t  struct v4l2_encoder_cmd *cmd)\n+{\n+\tstruct bcm2835_codec_ctx *ctx = file2ctx(file);\n+\n+\tif (ctx->dev->role != ENCODE)\n+\t\treturn -EINVAL;\n+\n+\tswitch (cmd->cmd) {\n+\tcase V4L2_ENC_CMD_STOP:\n+\t\tbreak;\n+\n+\tcase V4L2_ENC_CMD_START:\n+\t\t/* Do we need to do anything here? */\n+\t\tbreak;\n+\tdefault:\n+\t\treturn -EINVAL;\n+\t}\n+\treturn 0;\n+}\n+\n+static int vidioc_encoder_cmd(struct file *file, void *priv,\n+\t\t\t      struct v4l2_encoder_cmd *cmd)\n+{\n+\tstruct bcm2835_codec_ctx *ctx = file2ctx(file);\n+\tstruct bcm2835_codec_q_data *q_data = &ctx->q_data[V4L2_M2M_SRC];\n+\tint ret;\n+\n+\tv4l2_dbg(2, debug, &ctx->dev->v4l2_dev, \"%s, cmd %u\", __func__,\n+\t\t cmd->cmd);\n+\tret = vidioc_try_encoder_cmd(file, priv, cmd);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tswitch (cmd->cmd) {\n+\tcase V4L2_ENC_CMD_STOP:\n+\t\tif (q_data->eos_buffer_in_use)\n+\t\t\tv4l2_err(&ctx->dev->v4l2_dev, \"EOS buffers already in use\\n\");\n+\t\tq_data->eos_buffer_in_use = true;\n+\n+\t\tq_data->eos_buffer.mmal.buffer_size = 0;\n+\t\tq_data->eos_buffer.mmal.length = 0;\n+\t\tq_data->eos_buffer.mmal.mmal_flags =\n+\t\t\t\t\t\tMMAL_BUFFER_HEADER_FLAG_EOS;\n+\t\tq_data->eos_buffer.mmal.pts = 0;\n+\t\tq_data->eos_buffer.mmal.dts = 0;\n+\n+\t\tif (!ctx->component)\n+\t\t\tbreak;\n+\n+\t\tret = vchiq_mmal_submit_buffer(ctx->dev->instance,\n+\t\t\t\t\t       &ctx->component->input[0],\n+\t\t\t\t\t       &q_data->eos_buffer.mmal);\n+\t\tif (ret)\n+\t\t\tv4l2_err(&ctx->dev->v4l2_dev,\n+\t\t\t\t \"%s: EOS buffer submit failed %d\\n\",\n+\t\t\t\t __func__, ret);\n+\n+\t\tbreak;\n+\tcase V4L2_ENC_CMD_START:\n+\t\t/* Do we need to do anything here? */\n+\t\tbreak;\n+\n+\tdefault:\n+\t\treturn -EINVAL;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int vidioc_enum_framesizes(struct file *file, void *fh,\n+\t\t\t\t  struct v4l2_frmsizeenum *fsize)\n+{\n+\tstruct bcm2835_codec_fmt *fmt;\n+\n+\tfmt = find_format_pix_fmt(fsize->pixel_format, file2ctx(file)->dev,\n+\t\t\t\t  true);\n+\tif (!fmt)\n+\t\tfmt = find_format_pix_fmt(fsize->pixel_format,\n+\t\t\t\t\t  file2ctx(file)->dev,\n+\t\t\t\t\t  false);\n+\n+\tif (!fmt)\n+\t\treturn -EINVAL;\n+\n+\tif (fsize->index)\n+\t\treturn -EINVAL;\n+\n+\tfsize->type = V4L2_FRMSIZE_TYPE_STEPWISE;\n+\n+\tfsize->stepwise.min_width = MIN_W;\n+\tfsize->stepwise.max_width = MAX_W;\n+\tfsize->stepwise.step_width = 1;\n+\tfsize->stepwise.min_height = MIN_H;\n+\tfsize->stepwise.max_height = MAX_H;\n+\tfsize->stepwise.step_height = 1;\n+\n+\treturn 0;\n+}\n+\n+static const struct v4l2_ioctl_ops bcm2835_codec_ioctl_ops = {\n+\t.vidioc_querycap\t= vidioc_querycap,\n+\n+\t.vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap,\n+\t.vidioc_g_fmt_vid_cap_mplane\t= vidioc_g_fmt_vid_cap,\n+\t.vidioc_try_fmt_vid_cap_mplane\t= vidioc_try_fmt_vid_cap,\n+\t.vidioc_s_fmt_vid_cap_mplane\t= vidioc_s_fmt_vid_cap,\n+\n+\t.vidioc_enum_fmt_vid_out = vidioc_enum_fmt_vid_out,\n+\t.vidioc_g_fmt_vid_out_mplane\t= vidioc_g_fmt_vid_out,\n+\t.vidioc_try_fmt_vid_out_mplane\t= vidioc_try_fmt_vid_out,\n+\t.vidioc_s_fmt_vid_out_mplane\t= vidioc_s_fmt_vid_out,\n+\n+\t.vidioc_reqbufs\t\t= v4l2_m2m_ioctl_reqbufs,\n+\t.vidioc_querybuf\t= v4l2_m2m_ioctl_querybuf,\n+\t.vidioc_qbuf\t\t= v4l2_m2m_ioctl_qbuf,\n+\t.vidioc_dqbuf\t\t= v4l2_m2m_ioctl_dqbuf,\n+\t.vidioc_prepare_buf\t= v4l2_m2m_ioctl_prepare_buf,\n+\t.vidioc_create_bufs\t= v4l2_m2m_ioctl_create_bufs,\n+\t.vidioc_expbuf\t\t= v4l2_m2m_ioctl_expbuf,\n+\n+\t.vidioc_streamon\t= v4l2_m2m_ioctl_streamon,\n+\t.vidioc_streamoff\t= v4l2_m2m_ioctl_streamoff,\n+\n+\t.vidioc_g_selection\t= vidioc_g_selection,\n+\t.vidioc_s_selection\t= vidioc_s_selection,\n+\n+\t.vidioc_g_parm\t\t= vidioc_g_parm,\n+\t.vidioc_s_parm\t\t= vidioc_s_parm,\n+\n+\t.vidioc_subscribe_event = vidioc_subscribe_evt,\n+\t.vidioc_unsubscribe_event = v4l2_event_unsubscribe,\n+\n+\t.vidioc_decoder_cmd = vidioc_decoder_cmd,\n+\t.vidioc_try_decoder_cmd = vidioc_try_decoder_cmd,\n+\t.vidioc_encoder_cmd = vidioc_encoder_cmd,\n+\t.vidioc_try_encoder_cmd = vidioc_try_encoder_cmd,\n+\t.vidioc_enum_framesizes = vidioc_enum_framesizes,\n+};\n+\n+static int bcm2835_codec_set_ctrls(struct bcm2835_codec_ctx *ctx)\n+{\n+\t/*\n+\t * Query the control handler for the value of the various controls and\n+\t * set them.\n+\t */\n+\tconst u32 control_ids[] = {\n+\t\tV4L2_CID_MPEG_VIDEO_BITRATE_MODE,\n+\t\tV4L2_CID_MPEG_VIDEO_REPEAT_SEQ_HEADER,\n+\t\tV4L2_CID_MPEG_VIDEO_H264_I_PERIOD,\n+\t\tV4L2_CID_MPEG_VIDEO_H264_LEVEL,\n+\t\tV4L2_CID_MPEG_VIDEO_H264_PROFILE,\n+\t};\n+\tint i;\n+\n+\tfor (i = 0; i < ARRAY_SIZE(control_ids); i++) {\n+\t\tstruct v4l2_ctrl *ctrl;\n+\n+\t\tctrl = v4l2_ctrl_find(&ctx->hdl, control_ids[i]);\n+\t\tif (ctrl)\n+\t\t\tbcm2835_codec_s_ctrl(ctrl);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int bcm2835_codec_create_component(struct bcm2835_codec_ctx *ctx)\n+{\n+\tstruct bcm2835_codec_dev *dev = ctx->dev;\n+\tunsigned int enable = 1;\n+\tint ret;\n+\n+\tret = vchiq_mmal_component_init(dev->instance, components[dev->role],\n+\t\t\t\t\t&ctx->component);\n+\tif (ret < 0) {\n+\t\tv4l2_err(&dev->v4l2_dev, \"%s: failed to create component %s\\n\",\n+\t\t\t __func__, components[dev->role]);\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\tvchiq_mmal_port_parameter_set(dev->instance, &ctx->component->input[0],\n+\t\t\t\t      MMAL_PARAMETER_ZERO_COPY, &enable,\n+\t\t\t\t      sizeof(enable));\n+\tvchiq_mmal_port_parameter_set(dev->instance, &ctx->component->output[0],\n+\t\t\t\t      MMAL_PARAMETER_ZERO_COPY, &enable,\n+\t\t\t\t      sizeof(enable));\n+\n+\tsetup_mmal_port_format(ctx, &ctx->q_data[V4L2_M2M_SRC],\n+\t\t\t       &ctx->component->input[0]);\n+\n+\tsetup_mmal_port_format(ctx, &ctx->q_data[V4L2_M2M_DST],\n+\t\t\t       &ctx->component->output[0]);\n+\n+\tret = vchiq_mmal_port_set_format(dev->instance,\n+\t\t\t\t\t &ctx->component->input[0]);\n+\tif (ret < 0) {\n+\t\tv4l2_dbg(1, debug, &dev->v4l2_dev,\n+\t\t\t \"%s: vchiq_mmal_port_set_format ip port failed\\n\",\n+\t\t\t __func__);\n+\t\tgoto destroy_component;\n+\t}\n+\n+\tret = vchiq_mmal_port_set_format(dev->instance,\n+\t\t\t\t\t &ctx->component->output[0]);\n+\tif (ret < 0) {\n+\t\tv4l2_dbg(1, debug, &dev->v4l2_dev,\n+\t\t\t \"%s: vchiq_mmal_port_set_format op port failed\\n\",\n+\t\t\t __func__);\n+\t\tgoto destroy_component;\n+\t}\n+\n+\tif (dev->role == ENCODE) {\n+\t\tu32 param = 1;\n+\n+\t\tif (ctx->q_data[V4L2_M2M_SRC].sizeimage <\n+\t\t\tctx->component->output[0].minimum_buffer.size)\n+\t\t\tv4l2_err(&dev->v4l2_dev, \"buffer size mismatch sizeimage %u < min size %u\\n\",\n+\t\t\t\t ctx->q_data[V4L2_M2M_SRC].sizeimage,\n+\t\t\t\t ctx->component->output[0].minimum_buffer.size);\n+\n+\t\t/* Now we have a component we can set all the ctrls */\n+\t\tbcm2835_codec_set_ctrls(ctx);\n+\n+\t\t/* Enable SPS Timing header so framerate information is encoded\n+\t\t * in the H264 header.\n+\t\t */\n+\t\tvchiq_mmal_port_parameter_set(ctx->dev->instance,\n+\t\t\t\t\t      &ctx->component->output[0],\n+\t\t\t\t\t      MMAL_PARAMETER_VIDEO_ENCODE_SPS_TIMING,\n+\t\t\t\t\t      &param, sizeof(param));\n+\n+\t\t/* Enable inserting headers into the first frame */\n+\t\tvchiq_mmal_port_parameter_set(ctx->dev->instance,\n+\t\t\t\t\t      &ctx->component->control,\n+\t\t\t\t\t      MMAL_PARAMETER_VIDEO_ENCODE_HEADERS_WITH_FRAME,\n+\t\t\t\t\t      &param, sizeof(param));\n+\t\t/*\n+\t\t * Avoid fragmenting the buffers over multiple frames (unless\n+\t\t * the frame is bigger than the whole buffer)\n+\t\t */\n+\t\tvchiq_mmal_port_parameter_set(ctx->dev->instance,\n+\t\t\t\t\t      &ctx->component->control,\n+\t\t\t\t\t      MMAL_PARAMETER_MINIMISE_FRAGMENTATION,\n+\t\t\t\t\t      &param, sizeof(param));\n+\t} else {\n+\t\tif (ctx->q_data[V4L2_M2M_DST].sizeimage <\n+\t\t\tctx->component->output[0].minimum_buffer.size)\n+\t\t\tv4l2_err(&dev->v4l2_dev, \"buffer size mismatch sizeimage %u < min size %u\\n\",\n+\t\t\t\t ctx->q_data[V4L2_M2M_DST].sizeimage,\n+\t\t\t\t ctx->component->output[0].minimum_buffer.size);\n+\t}\n+\tv4l2_dbg(2, debug, &dev->v4l2_dev, \"%s: component created as %s\\n\",\n+\t\t __func__, components[dev->role]);\n+\n+\treturn 0;\n+\n+destroy_component:\n+\tvchiq_mmal_component_finalise(ctx->dev->instance, ctx->component);\n+\tctx->component = NULL;\n+\n+\treturn ret;\n+}\n+\n+/*\n+ * Queue operations\n+ */\n+\n+static int bcm2835_codec_queue_setup(struct vb2_queue *vq,\n+\t\t\t\t     unsigned int *nbuffers,\n+\t\t\t\t     unsigned int *nplanes,\n+\t\t\t\t     unsigned int sizes[],\n+\t\t\t\t     struct device *alloc_devs[])\n+{\n+\tstruct bcm2835_codec_ctx *ctx = vb2_get_drv_priv(vq);\n+\tstruct bcm2835_codec_q_data *q_data;\n+\tstruct vchiq_mmal_port *port;\n+\tunsigned int size;\n+\n+\tq_data = get_q_data(ctx, vq->type);\n+\tif (!q_data)\n+\t\treturn -EINVAL;\n+\n+\tif (!ctx->component)\n+\t\tif (bcm2835_codec_create_component(ctx))\n+\t\t\treturn -EINVAL;\n+\n+\tport = get_port_data(ctx, vq->type);\n+\n+\tsize = q_data->sizeimage;\n+\n+\tif (*nplanes)\n+\t\treturn sizes[0] < size ? -EINVAL : 0;\n+\n+\t*nplanes = 1;\n+\n+\tsizes[0] = size;\n+\tport->current_buffer.size = size;\n+\n+\tif (*nbuffers < port->minimum_buffer.num)\n+\t\t*nbuffers = port->minimum_buffer.num;\n+\t/* Add one buffer to take an EOS */\n+\tport->current_buffer.num = *nbuffers + 1;\n+\n+\treturn 0;\n+}\n+\n+static int bcm2835_codec_mmal_buf_cleanup(struct mmal_buffer *mmal_buf)\n+{\n+\tmmal_vchi_buffer_cleanup(mmal_buf);\n+\n+\tif (mmal_buf->dma_buf) {\n+\t\tdma_buf_put(mmal_buf->dma_buf);\n+\t\tmmal_buf->dma_buf = NULL;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int bcm2835_codec_buf_init(struct vb2_buffer *vb)\n+{\n+\tstruct bcm2835_codec_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);\n+\tstruct vb2_v4l2_buffer *vb2 = to_vb2_v4l2_buffer(vb);\n+\tstruct v4l2_m2m_buffer *m2m = container_of(vb2, struct v4l2_m2m_buffer,\n+\t\t\t\t\t\t   vb);\n+\tstruct m2m_mmal_buffer *buf = container_of(m2m, struct m2m_mmal_buffer,\n+\t\t\t\t\t\t   m2m);\n+\n+\tv4l2_dbg(2, debug, &ctx->dev->v4l2_dev, \"%s: ctx:%p, vb %p\\n\",\n+\t\t __func__, ctx, vb);\n+\tbuf->mmal.buffer = vb2_plane_vaddr(&buf->m2m.vb.vb2_buf, 0);\n+\tbuf->mmal.buffer_size = vb2_plane_size(&buf->m2m.vb.vb2_buf, 0);\n+\n+\tmmal_vchi_buffer_init(ctx->dev->instance, &buf->mmal);\n+\n+\treturn 0;\n+}\n+\n+static int bcm2835_codec_buf_prepare(struct vb2_buffer *vb)\n+{\n+\tstruct bcm2835_codec_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);\n+\tstruct bcm2835_codec_q_data *q_data;\n+\tstruct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);\n+\tstruct v4l2_m2m_buffer *m2m = container_of(vbuf, struct v4l2_m2m_buffer,\n+\t\t\t\t\t\t   vb);\n+\tstruct m2m_mmal_buffer *buf = container_of(m2m, struct m2m_mmal_buffer,\n+\t\t\t\t\t\t   m2m);\n+\tstruct dma_buf *dma_buf;\n+\tint ret;\n+\n+\tv4l2_dbg(4, debug, &ctx->dev->v4l2_dev, \"%s: type: %d ptr %p\\n\",\n+\t\t __func__, vb->vb2_queue->type, vb);\n+\n+\tq_data = get_q_data(ctx, vb->vb2_queue->type);\n+\tif (V4L2_TYPE_IS_OUTPUT(vb->vb2_queue->type)) {\n+\t\tif (vbuf->field == V4L2_FIELD_ANY)\n+\t\t\tvbuf->field = V4L2_FIELD_NONE;\n+\t\tif (vbuf->field != V4L2_FIELD_NONE) {\n+\t\t\tv4l2_err(&ctx->dev->v4l2_dev, \"%s field isn't supported\\n\",\n+\t\t\t\t __func__);\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t}\n+\n+\tif (vb2_plane_size(vb, 0) < q_data->sizeimage) {\n+\t\tv4l2_err(&ctx->dev->v4l2_dev, \"%s data will not fit into plane (%lu < %lu)\\n\",\n+\t\t\t __func__, vb2_plane_size(vb, 0),\n+\t\t\t (long)q_data->sizeimage);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (!V4L2_TYPE_IS_OUTPUT(vb->vb2_queue->type))\n+\t\tvb2_set_plane_payload(vb, 0, q_data->sizeimage);\n+\n+\tswitch (vb->memory) {\n+\tcase VB2_MEMORY_DMABUF:\n+\t\tdma_buf = dma_buf_get(vb->planes[0].m.fd);\n+\n+\t\tif (dma_buf != buf->mmal.dma_buf) {\n+\t\t\t/* dmabuf either hasn't already been mapped, or it has\n+\t\t\t * changed.\n+\t\t\t */\n+\t\t\tif (buf->mmal.dma_buf) {\n+\t\t\t\tv4l2_err(&ctx->dev->v4l2_dev,\n+\t\t\t\t\t \"%s Buffer changed - why did the core not call cleanup?\\n\",\n+\t\t\t\t\t __func__);\n+\t\t\t\tbcm2835_codec_mmal_buf_cleanup(&buf->mmal);\n+\t\t\t}\n+\n+\t\t\tbuf->mmal.dma_buf = dma_buf;\n+\t\t} else {\n+\t\t\t/* We already have a reference count on the dmabuf, so\n+\t\t\t * release the one we acquired above.\n+\t\t\t */\n+\t\t\tdma_buf_put(dma_buf);\n+\t\t}\n+\t\tret = 0;\n+\t\tbreak;\n+\tcase VB2_MEMORY_MMAP:\n+\t\t/*\n+\t\t * We want to do this at init, but vb2_core_expbuf checks that\n+\t\t * the index < q->num_buffers, and q->num_buffers only gets\n+\t\t * updated once all the buffers are allocated.\n+\t\t */\n+\t\tif (!buf->mmal.dma_buf) {\n+\t\t\tret = vb2_core_expbuf_dmabuf(vb->vb2_queue,\n+\t\t\t\t\t\t     vb->vb2_queue->type,\n+\t\t\t\t\t\t     vb->index, 0,\n+\t\t\t\t\t\t     O_CLOEXEC,\n+\t\t\t\t\t\t     &buf->mmal.dma_buf);\n+\t\t\tif (ret)\n+\t\t\t\tv4l2_err(&ctx->dev->v4l2_dev,\n+\t\t\t\t\t \"%s: Failed to expbuf idx %d, ret %d\\n\",\n+\t\t\t\t\t __func__, vb->index, ret);\n+\t\t} else {\n+\t\t\tret = 0;\n+\t\t}\n+\t\tbreak;\n+\tdefault:\n+\t\tret = -EINVAL;\n+\t\tbreak;\n+\t}\n+\n+\treturn ret;\n+}\n+\n+static void bcm2835_codec_buf_queue(struct vb2_buffer *vb)\n+{\n+\tstruct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);\n+\tstruct bcm2835_codec_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);\n+\n+\tv4l2_dbg(4, debug, &ctx->dev->v4l2_dev, \"%s: type: %d ptr %p vbuf->flags %u, seq %u, bytesused %u\\n\",\n+\t\t __func__, vb->vb2_queue->type, vb, vbuf->flags, vbuf->sequence,\n+\t\t vb->planes[0].bytesused);\n+\tv4l2_m2m_buf_queue(ctx->fh.m2m_ctx, vbuf);\n+}\n+\n+static void bcm2835_codec_buffer_cleanup(struct vb2_buffer *vb)\n+{\n+\tstruct bcm2835_codec_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);\n+\tstruct vb2_v4l2_buffer *vb2 = to_vb2_v4l2_buffer(vb);\n+\tstruct v4l2_m2m_buffer *m2m = container_of(vb2, struct v4l2_m2m_buffer,\n+\t\t\t\t\t\t   vb);\n+\tstruct m2m_mmal_buffer *buf = container_of(m2m, struct m2m_mmal_buffer,\n+\t\t\t\t\t\t   m2m);\n+\n+\tv4l2_dbg(2, debug, &ctx->dev->v4l2_dev, \"%s: ctx:%p, vb %p\\n\",\n+\t\t __func__, ctx, vb);\n+\n+\tbcm2835_codec_mmal_buf_cleanup(&buf->mmal);\n+}\n+\n+static int bcm2835_codec_start_streaming(struct vb2_queue *q,\n+\t\t\t\t\t unsigned int count)\n+{\n+\tstruct bcm2835_codec_ctx *ctx = vb2_get_drv_priv(q);\n+\tstruct bcm2835_codec_dev *dev = ctx->dev;\n+\tstruct bcm2835_codec_q_data *q_data = get_q_data(ctx, q->type);\n+\tstruct vchiq_mmal_port *port = get_port_data(ctx, q->type);\n+\tint ret;\n+\n+\tv4l2_dbg(1, debug, &ctx->dev->v4l2_dev, \"%s: type: %d count %d\\n\",\n+\t\t __func__, q->type, count);\n+\tq_data->sequence = 0;\n+\n+\tif (!ctx->component_enabled) {\n+\t\tret = vchiq_mmal_component_enable(dev->instance,\n+\t\t\t\t\t\t  ctx->component);\n+\t\tif (ret)\n+\t\t\tv4l2_err(&ctx->dev->v4l2_dev, \"%s: Failed enabling component, ret %d\\n\",\n+\t\t\t\t __func__, ret);\n+\t\tctx->component_enabled = true;\n+\t}\n+\n+\tif (count < port->minimum_buffer.num)\n+\t\tcount = port->minimum_buffer.num;\n+\n+\tif (port->current_buffer.num < count + 1) {\n+\t\tv4l2_dbg(2, debug, &ctx->dev->v4l2_dev, \"%s: ctx:%p, buffer count changed %u to %u\\n\",\n+\t\t\t __func__, ctx, port->current_buffer.num, count + 1);\n+\n+\t\tport->current_buffer.num = count + 1;\n+\t\tret = vchiq_mmal_port_set_format(dev->instance, port);\n+\t\tif (ret)\n+\t\t\tv4l2_err(&ctx->dev->v4l2_dev, \"%s: Error updating buffer count, ret %d\\n\",\n+\t\t\t\t __func__, ret);\n+\t}\n+\n+\tif (q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {\n+\t\t/*\n+\t\t * Create the EOS buffer.\n+\t\t * We only need the MMAL part, and want to NOT attach a memory\n+\t\t * buffer to it as it should only take flags.\n+\t\t */\n+\t\tmemset(&q_data->eos_buffer, 0, sizeof(q_data->eos_buffer));\n+\t\tmmal_vchi_buffer_init(dev->instance,\n+\t\t\t\t      &q_data->eos_buffer.mmal);\n+\t\tq_data->eos_buffer_in_use = false;\n+\n+\t\tport->cb_ctx = ctx;\n+\t\tret = vchiq_mmal_port_enable(dev->instance,\n+\t\t\t\t\t     port,\n+\t\t\t\t\t     ip_buffer_cb);\n+\t\tif (ret)\n+\t\t\tv4l2_err(&ctx->dev->v4l2_dev, \"%s: Failed enabling i/p port, ret %d\\n\",\n+\t\t\t\t __func__, ret);\n+\t} else {\n+\t\tport->cb_ctx = ctx;\n+\t\tret = vchiq_mmal_port_enable(dev->instance,\n+\t\t\t\t\t     port,\n+\t\t\t\t\t     op_buffer_cb);\n+\t\tif (ret)\n+\t\t\tv4l2_err(&ctx->dev->v4l2_dev, \"%s: Failed enabling o/p port, ret %d\\n\",\n+\t\t\t\t __func__, ret);\n+\t}\n+\treturn ret;\n+}\n+\n+static void bcm2835_codec_stop_streaming(struct vb2_queue *q)\n+{\n+\tstruct bcm2835_codec_ctx *ctx = vb2_get_drv_priv(q);\n+\tstruct bcm2835_codec_dev *dev = ctx->dev;\n+\tstruct bcm2835_codec_q_data *q_data = get_q_data(ctx, q->type);\n+\tstruct vchiq_mmal_port *port = get_port_data(ctx, q->type);\n+\tstruct vb2_v4l2_buffer *vbuf;\n+\tint ret;\n+\n+\tv4l2_dbg(1, debug, &ctx->dev->v4l2_dev, \"%s: type: %d - return buffers\\n\",\n+\t\t __func__, q->type);\n+\n+\tinit_completion(&ctx->frame_cmplt);\n+\n+\t/* Clear out all buffers held by m2m framework */\n+\tfor (;;) {\n+\t\tif (V4L2_TYPE_IS_OUTPUT(q->type))\n+\t\t\tvbuf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);\n+\t\telse\n+\t\t\tvbuf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);\n+\t\tif (!vbuf)\n+\t\t\tbreak;\n+\t\tv4l2_dbg(1, debug, &ctx->dev->v4l2_dev, \"%s: return buffer %p\\n\",\n+\t\t\t __func__, vbuf);\n+\n+\t\tv4l2_m2m_buf_done(vbuf, VB2_BUF_STATE_ERROR);\n+\t}\n+\n+\t/* Disable MMAL port - this will flush buffers back */\n+\tret = vchiq_mmal_port_disable(dev->instance, port);\n+\tif (ret)\n+\t\tv4l2_err(&ctx->dev->v4l2_dev, \"%s: Failed disabling %s port, ret %d\\n\",\n+\t\t\t __func__, V4L2_TYPE_IS_OUTPUT(q->type) ? \"i/p\" : \"o/p\",\n+\t\t\t ret);\n+\n+\twhile (atomic_read(&port->buffers_with_vpu)) {\n+\t\tv4l2_dbg(1, debug, &ctx->dev->v4l2_dev, \"%s: Waiting for buffers to be returned - %d outstanding\\n\",\n+\t\t\t __func__, atomic_read(&port->buffers_with_vpu));\n+\t\tret = wait_for_completion_timeout(&ctx->frame_cmplt,\n+\t\t\t\t\t\t  COMPLETE_TIMEOUT);\n+\t\tif (ret <= 0) {\n+\t\t\tv4l2_err(&ctx->dev->v4l2_dev, \"%s: Timeout waiting for buffers to be returned - %d outstanding\\n\",\n+\t\t\t\t __func__,\n+\t\t\t\t atomic_read(&port->buffers_with_vpu));\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\n+\t/* If both ports disabled, then disable the component */\n+\tif (ctx->component_enabled &&\n+\t    !ctx->component->input[0].enabled &&\n+\t    !ctx->component->output[0].enabled) {\n+\t\tret = vchiq_mmal_component_disable(dev->instance,\n+\t\t\t\t\t\t   ctx->component);\n+\t\tif (ret)\n+\t\t\tv4l2_err(&ctx->dev->v4l2_dev, \"%s: Failed enabling component, ret %d\\n\",\n+\t\t\t\t __func__, ret);\n+\t\tctx->component_enabled = false;\n+\t}\n+\n+\tif (V4L2_TYPE_IS_OUTPUT(q->type))\n+\t\tmmal_vchi_buffer_cleanup(&q_data->eos_buffer.mmal);\n+\n+\tv4l2_dbg(1, debug, &ctx->dev->v4l2_dev, \"%s: done\\n\", __func__);\n+}\n+\n+static const struct vb2_ops bcm2835_codec_qops = {\n+\t.queue_setup\t = bcm2835_codec_queue_setup,\n+\t.buf_init\t = bcm2835_codec_buf_init,\n+\t.buf_prepare\t = bcm2835_codec_buf_prepare,\n+\t.buf_queue\t = bcm2835_codec_buf_queue,\n+\t.buf_cleanup\t = bcm2835_codec_buffer_cleanup,\n+\t.start_streaming = bcm2835_codec_start_streaming,\n+\t.stop_streaming  = bcm2835_codec_stop_streaming,\n+\t.wait_prepare\t = vb2_ops_wait_prepare,\n+\t.wait_finish\t = vb2_ops_wait_finish,\n+};\n+\n+static int queue_init(void *priv, struct vb2_queue *src_vq,\n+\t\t      struct vb2_queue *dst_vq)\n+{\n+\tstruct bcm2835_codec_ctx *ctx = priv;\n+\tint ret;\n+\n+\tsrc_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;\n+\tsrc_vq->io_modes = VB2_MMAP | VB2_DMABUF;\n+\tsrc_vq->drv_priv = ctx;\n+\tsrc_vq->buf_struct_size = sizeof(struct m2m_mmal_buffer);\n+\tsrc_vq->ops = &bcm2835_codec_qops;\n+\tsrc_vq->mem_ops = &vb2_dma_contig_memops;\n+\tsrc_vq->dev = &ctx->dev->pdev->dev;\n+\tsrc_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;\n+\tsrc_vq->lock = &ctx->dev->dev_mutex;\n+\n+\tret = vb2_queue_init(src_vq);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tdst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;\n+\tdst_vq->io_modes = VB2_MMAP | VB2_DMABUF;\n+\tdst_vq->drv_priv = ctx;\n+\tdst_vq->buf_struct_size = sizeof(struct m2m_mmal_buffer);\n+\tdst_vq->ops = &bcm2835_codec_qops;\n+\tdst_vq->mem_ops = &vb2_dma_contig_memops;\n+\tdst_vq->dev = &ctx->dev->pdev->dev;\n+\tdst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;\n+\tdst_vq->lock = &ctx->dev->dev_mutex;\n+\n+\treturn vb2_queue_init(dst_vq);\n+}\n+\n+/*\n+ * File operations\n+ */\n+static int bcm2835_codec_open(struct file *file)\n+{\n+\tstruct bcm2835_codec_dev *dev = video_drvdata(file);\n+\tstruct bcm2835_codec_ctx *ctx = NULL;\n+\tstruct v4l2_ctrl_handler *hdl;\n+\tint rc = 0;\n+\n+\tif (mutex_lock_interruptible(&dev->dev_mutex)) {\n+\t\tv4l2_err(&dev->v4l2_dev, \"Mutex fail\\n\");\n+\t\treturn -ERESTARTSYS;\n+\t}\n+\tctx = kzalloc(sizeof(*ctx), GFP_KERNEL);\n+\tif (!ctx) {\n+\t\trc = -ENOMEM;\n+\t\tgoto open_unlock;\n+\t}\n+\n+\tctx->q_data[V4L2_M2M_SRC].fmt = get_default_format(dev, false);\n+\tctx->q_data[V4L2_M2M_DST].fmt = get_default_format(dev, true);\n+\n+\tctx->q_data[V4L2_M2M_SRC].crop_width = DEFAULT_WIDTH;\n+\tctx->q_data[V4L2_M2M_SRC].crop_height = DEFAULT_HEIGHT;\n+\tctx->q_data[V4L2_M2M_SRC].height = DEFAULT_HEIGHT;\n+\tctx->q_data[V4L2_M2M_SRC].bytesperline =\n+\t\t\tget_bytesperline(DEFAULT_WIDTH,\n+\t\t\t\t\t ctx->q_data[V4L2_M2M_SRC].fmt);\n+\tctx->q_data[V4L2_M2M_SRC].sizeimage =\n+\t\tget_sizeimage(ctx->q_data[V4L2_M2M_SRC].bytesperline,\n+\t\t\t      ctx->q_data[V4L2_M2M_SRC].crop_width,\n+\t\t\t      ctx->q_data[V4L2_M2M_SRC].height,\n+\t\t\t      ctx->q_data[V4L2_M2M_SRC].fmt);\n+\n+\tctx->q_data[V4L2_M2M_DST].crop_width = DEFAULT_WIDTH;\n+\tctx->q_data[V4L2_M2M_DST].crop_height = DEFAULT_HEIGHT;\n+\tctx->q_data[V4L2_M2M_DST].height = DEFAULT_HEIGHT;\n+\tctx->q_data[V4L2_M2M_DST].bytesperline =\n+\t\t\tget_bytesperline(DEFAULT_WIDTH,\n+\t\t\t\t\t ctx->q_data[V4L2_M2M_DST].fmt);\n+\tctx->q_data[V4L2_M2M_DST].sizeimage =\n+\t\tget_sizeimage(ctx->q_data[V4L2_M2M_DST].bytesperline,\n+\t\t\t      ctx->q_data[V4L2_M2M_DST].crop_width,\n+\t\t\t      ctx->q_data[V4L2_M2M_DST].height,\n+\t\t\t      ctx->q_data[V4L2_M2M_DST].fmt);\n+\n+\tctx->colorspace = V4L2_COLORSPACE_REC709;\n+\tctx->bitrate = 10 * 1000 * 1000;\n+\n+\tctx->framerate_num = 30;\n+\tctx->framerate_denom = 1;\n+\n+\t/* Initialise V4L2 contexts */\n+\tv4l2_fh_init(&ctx->fh, video_devdata(file));\n+\tfile->private_data = &ctx->fh;\n+\tctx->dev = dev;\n+\thdl = &ctx->hdl;\n+\tif (dev->role == ENCODE) {\n+\t\t/* Encode controls */\n+\t\tv4l2_ctrl_handler_init(hdl, 7);\n+\n+\t\tv4l2_ctrl_new_std_menu(hdl, &bcm2835_codec_ctrl_ops,\n+\t\t\t\t       V4L2_CID_MPEG_VIDEO_BITRATE_MODE,\n+\t\t\t\t       V4L2_MPEG_VIDEO_BITRATE_MODE_CBR, 0,\n+\t\t\t\t       V4L2_MPEG_VIDEO_BITRATE_MODE_VBR);\n+\t\tv4l2_ctrl_new_std(hdl, &bcm2835_codec_ctrl_ops,\n+\t\t\t\t  V4L2_CID_MPEG_VIDEO_BITRATE,\n+\t\t\t\t  25 * 1000, 25 * 1000 * 1000,\n+\t\t\t\t  25 * 1000, 10 * 1000 * 1000);\n+\t\tv4l2_ctrl_new_std(hdl, &bcm2835_codec_ctrl_ops,\n+\t\t\t\t  V4L2_CID_MPEG_VIDEO_REPEAT_SEQ_HEADER,\n+\t\t\t\t  0, 1,\n+\t\t\t\t  1, 0);\n+\t\tv4l2_ctrl_new_std(hdl, &bcm2835_codec_ctrl_ops,\n+\t\t\t\t  V4L2_CID_MPEG_VIDEO_H264_I_PERIOD,\n+\t\t\t\t  0, 0x7FFFFFFF,\n+\t\t\t\t  1, 60);\n+\t\tv4l2_ctrl_new_std_menu(hdl, &bcm2835_codec_ctrl_ops,\n+\t\t\t\t       V4L2_CID_MPEG_VIDEO_H264_LEVEL,\n+\t\t\t\t       V4L2_MPEG_VIDEO_H264_LEVEL_4_2,\n+\t\t\t\t       ~(BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_0) |\n+\t\t\t\t\t BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1B) |\n+\t\t\t\t\t BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_1) |\n+\t\t\t\t\t BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_2) |\n+\t\t\t\t\t BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_3) |\n+\t\t\t\t\t BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_0) |\n+\t\t\t\t\t BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_1) |\n+\t\t\t\t\t BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_2) |\n+\t\t\t\t\t BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_0) |\n+\t\t\t\t\t BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_1) |\n+\t\t\t\t\t BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_2) |\n+\t\t\t\t\t BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_0) |\n+\t\t\t\t\t BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_1) |\n+\t\t\t\t\t BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_2)),\n+\t\t\t\t       V4L2_MPEG_VIDEO_H264_LEVEL_4_0);\n+\t\tv4l2_ctrl_new_std_menu(hdl, &bcm2835_codec_ctrl_ops,\n+\t\t\t\t       V4L2_CID_MPEG_VIDEO_H264_PROFILE,\n+\t\t\t\t       V4L2_MPEG_VIDEO_H264_PROFILE_HIGH,\n+\t\t\t\t       ~(BIT(V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE) |\n+\t\t\t\t\t BIT(V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_BASELINE) |\n+\t\t\t\t\t BIT(V4L2_MPEG_VIDEO_H264_PROFILE_MAIN) |\n+\t\t\t\t\t BIT(V4L2_MPEG_VIDEO_H264_PROFILE_HIGH)),\n+\t\t\t\t\tV4L2_MPEG_VIDEO_H264_PROFILE_HIGH);\n+\t\tv4l2_ctrl_new_std(hdl, &bcm2835_codec_ctrl_ops,\n+\t\t\t\t  V4L2_CID_MPEG_VIDEO_FORCE_KEY_FRAME,\n+\t\t\t\t  0, 0, 0, 0);\n+\t\tif (hdl->error) {\n+\t\t\trc = hdl->error;\n+\t\t\tgoto free_ctrl_handler;\n+\t\t}\n+\t\tctx->fh.ctrl_handler = hdl;\n+\t\tv4l2_ctrl_handler_setup(hdl);\n+\t} else if (dev->role == DECODE) {\n+\t\tv4l2_ctrl_handler_init(hdl, 1);\n+\n+\t\tv4l2_ctrl_new_std(hdl, &bcm2835_codec_ctrl_ops,\n+\t\t\t\t  V4L2_CID_MIN_BUFFERS_FOR_CAPTURE,\n+\t\t\t\t  1, 1, 1, 1);\n+\t\tif (hdl->error) {\n+\t\t\trc = hdl->error;\n+\t\t\tgoto free_ctrl_handler;\n+\t\t}\n+\t\tctx->fh.ctrl_handler = hdl;\n+\t\tv4l2_ctrl_handler_setup(hdl);\n+\t}\n+\n+\tctx->fh.m2m_ctx = v4l2_m2m_ctx_init(dev->m2m_dev, ctx, &queue_init);\n+\n+\tif (IS_ERR(ctx->fh.m2m_ctx)) {\n+\t\trc = PTR_ERR(ctx->fh.m2m_ctx);\n+\n+\t\tgoto free_ctrl_handler;\n+\t}\n+\n+\t/* Set both queues as buffered as we have buffering in the VPU. That\n+\t * means that we will be scheduled whenever either an input or output\n+\t * buffer is available (otherwise one of each are required).\n+\t */\n+\tv4l2_m2m_set_src_buffered(ctx->fh.m2m_ctx, true);\n+\tv4l2_m2m_set_dst_buffered(ctx->fh.m2m_ctx, true);\n+\n+\tv4l2_fh_add(&ctx->fh);\n+\tatomic_inc(&dev->num_inst);\n+\n+\tmutex_unlock(&dev->dev_mutex);\n+\treturn 0;\n+\n+free_ctrl_handler:\n+\tv4l2_ctrl_handler_free(hdl);\n+\tkfree(ctx);\n+open_unlock:\n+\tmutex_unlock(&dev->dev_mutex);\n+\treturn rc;\n+}\n+\n+static int bcm2835_codec_release(struct file *file)\n+{\n+\tstruct bcm2835_codec_dev *dev = video_drvdata(file);\n+\tstruct bcm2835_codec_ctx *ctx = file2ctx(file);\n+\n+\tv4l2_dbg(1, debug, &dev->v4l2_dev, \"%s: Releasing instance %p\\n\",\n+\t\t __func__, ctx);\n+\n+\tv4l2_fh_del(&ctx->fh);\n+\tv4l2_fh_exit(&ctx->fh);\n+\tv4l2_ctrl_handler_free(&ctx->hdl);\n+\tmutex_lock(&dev->dev_mutex);\n+\tv4l2_m2m_ctx_release(ctx->fh.m2m_ctx);\n+\n+\tif (ctx->component)\n+\t\tvchiq_mmal_component_finalise(dev->instance, ctx->component);\n+\n+\tmutex_unlock(&dev->dev_mutex);\n+\tkfree(ctx);\n+\n+\tatomic_dec(&dev->num_inst);\n+\n+\treturn 0;\n+}\n+\n+static const struct v4l2_file_operations bcm2835_codec_fops = {\n+\t.owner\t\t= THIS_MODULE,\n+\t.open\t\t= bcm2835_codec_open,\n+\t.release\t= bcm2835_codec_release,\n+\t.poll\t\t= v4l2_m2m_fop_poll,\n+\t.unlocked_ioctl\t= video_ioctl2,\n+\t.mmap\t\t= v4l2_m2m_fop_mmap,\n+};\n+\n+static const struct video_device bcm2835_codec_videodev = {\n+\t.name\t\t= MEM2MEM_NAME,\n+\t.vfl_dir\t= VFL_DIR_M2M,\n+\t.fops\t\t= &bcm2835_codec_fops,\n+\t.ioctl_ops\t= &bcm2835_codec_ioctl_ops,\n+\t.minor\t\t= -1,\n+\t.release\t= video_device_release_empty,\n+};\n+\n+static const struct v4l2_m2m_ops m2m_ops = {\n+\t.device_run\t= device_run,\n+\t.job_ready\t= job_ready,\n+\t.job_abort\t= job_abort,\n+};\n+\n+/* Size of the array to provide to the VPU when asking for the list of supported\n+ * formats.\n+ * The ISP component currently advertises 44 input formats, so add a small\n+ * overhead on that.\n+ */\n+#define MAX_SUPPORTED_ENCODINGS 50\n+\n+/* Populate dev->supported_fmts with the formats supported by those ports. */\n+static int bcm2835_codec_get_supported_fmts(struct bcm2835_codec_dev *dev)\n+{\n+\tstruct bcm2835_codec_fmt *list;\n+\tstruct vchiq_mmal_component *component;\n+\tu32 fourccs[MAX_SUPPORTED_ENCODINGS];\n+\tu32 param_size = sizeof(fourccs);\n+\tunsigned int i, j, num_encodings;\n+\tint ret;\n+\n+\tret = vchiq_mmal_component_init(dev->instance, components[dev->role],\n+\t\t\t\t\t&component);\n+\tif (ret < 0) {\n+\t\tv4l2_err(&dev->v4l2_dev, \"%s: failed to create component %s\\n\",\n+\t\t\t __func__, components[dev->role]);\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\tret = vchiq_mmal_port_parameter_get(dev->instance,\n+\t\t\t\t\t    &component->input[0],\n+\t\t\t\t\t    MMAL_PARAMETER_SUPPORTED_ENCODINGS,\n+\t\t\t\t\t    &fourccs,\n+\t\t\t\t\t    &param_size);\n+\n+\tif (ret) {\n+\t\tif (ret == MMAL_MSG_STATUS_ENOSPC) {\n+\t\t\tv4l2_err(&dev->v4l2_dev, \"%s: port has more encoding than we provided space for. Some are dropped.\\n\",\n+\t\t\t\t __func__);\n+\t\t\tnum_encodings = MAX_SUPPORTED_ENCODINGS;\n+\t\t} else {\n+\t\t\tv4l2_err(&dev->v4l2_dev, \"%s: get_param ret %u.\\n\",\n+\t\t\t\t __func__, ret);\n+\t\t\tret = -EINVAL;\n+\t\t\tgoto destroy_component;\n+\t\t}\n+\t} else {\n+\t\tnum_encodings = param_size / sizeof(u32);\n+\t}\n+\n+\t/* Assume at this stage that all encodings will be supported in V4L2.\n+\t * Any that aren't supported will waste a very small amount of memory.\n+\t */\n+\tlist = devm_kzalloc(&dev->pdev->dev,\n+\t\t\t    sizeof(struct bcm2835_codec_fmt) * num_encodings,\n+\t\t\t    GFP_KERNEL);\n+\tif (!list) {\n+\t\tret = -ENOMEM;\n+\t\tgoto destroy_component;\n+\t}\n+\tdev->supported_fmts[0].list = list;\n+\n+\tfor (i = 0, j = 0; i < num_encodings; i++) {\n+\t\tconst struct bcm2835_codec_fmt *fmt = get_fmt(fourccs[i]);\n+\n+\t\tif (fmt) {\n+\t\t\tlist[j] = *fmt;\n+\t\t\tj++;\n+\t\t}\n+\t}\n+\tdev->supported_fmts[0].num_entries = j;\n+\n+\tparam_size = sizeof(fourccs);\n+\tret = vchiq_mmal_port_parameter_get(dev->instance,\n+\t\t\t\t\t    &component->output[0],\n+\t\t\t\t\t    MMAL_PARAMETER_SUPPORTED_ENCODINGS,\n+\t\t\t\t\t    &fourccs,\n+\t\t\t\t\t    &param_size);\n+\n+\tif (ret) {\n+\t\tif (ret == MMAL_MSG_STATUS_ENOSPC) {\n+\t\t\tv4l2_err(&dev->v4l2_dev, \"%s: port has more encoding than we provided space for. Some are dropped.\\n\",\n+\t\t\t\t __func__);\n+\t\t\tnum_encodings = MAX_SUPPORTED_ENCODINGS;\n+\t\t} else {\n+\t\t\tret = -EINVAL;\n+\t\t\tgoto destroy_component;\n+\t\t}\n+\t} else {\n+\t\tnum_encodings = param_size / sizeof(u32);\n+\t}\n+\t/* Assume at this stage that all encodings will be supported in V4L2. */\n+\tlist = devm_kzalloc(&dev->pdev->dev,\n+\t\t\t    sizeof(struct bcm2835_codec_fmt) * num_encodings,\n+\t\t\t    GFP_KERNEL);\n+\tif (!list) {\n+\t\tret = -ENOMEM;\n+\t\tgoto destroy_component;\n+\t}\n+\tdev->supported_fmts[1].list = list;\n+\n+\tfor (i = 0, j = 0; i < num_encodings; i++) {\n+\t\tconst struct bcm2835_codec_fmt *fmt = get_fmt(fourccs[i]);\n+\n+\t\tif (fmt) {\n+\t\t\tlist[j] = *fmt;\n+\t\t\tj++;\n+\t\t}\n+\t}\n+\tdev->supported_fmts[1].num_entries = j;\n+\n+\tret = 0;\n+\n+destroy_component:\n+\tvchiq_mmal_component_finalise(dev->instance, component);\n+\n+\treturn ret;\n+}\n+\n+static int bcm2835_codec_create(struct bcm2835_codec_driver *drv,\n+\t\t\t\tstruct bcm2835_codec_dev **new_dev,\n+\t\t\t\tenum bcm2835_codec_role role)\n+{\n+\tstruct platform_device *pdev = drv->pdev;\n+\tstruct bcm2835_codec_dev *dev;\n+\tstruct video_device *vfd;\n+\tint function;\n+\tint video_nr;\n+\tint ret;\n+\n+\tdev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);\n+\tif (!dev)\n+\t\treturn -ENOMEM;\n+\n+\tdev->pdev = pdev;\n+\n+\tdev->role = role;\n+\n+\tret = vchiq_mmal_init(&dev->instance);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = bcm2835_codec_get_supported_fmts(dev);\n+\tif (ret)\n+\t\tgoto vchiq_finalise;\n+\n+\tatomic_set(&dev->num_inst, 0);\n+\tmutex_init(&dev->dev_mutex);\n+\n+\t/* Initialise the video device */\n+\tdev->vfd = bcm2835_codec_videodev;\n+\n+\tvfd = &dev->vfd;\n+\tvfd->lock = &dev->dev_mutex;\n+\tvfd->v4l2_dev = &dev->v4l2_dev;\n+\tvfd->device_caps = V4L2_CAP_VIDEO_M2M_MPLANE | V4L2_CAP_STREAMING;\n+\tvfd->v4l2_dev->mdev = &drv->mdev;\n+\n+\tret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev);\n+\tif (ret)\n+\t\tgoto vchiq_finalise;\n+\n+\tswitch (role) {\n+\tcase DECODE:\n+\t\tv4l2_disable_ioctl(vfd, VIDIOC_ENCODER_CMD);\n+\t\tv4l2_disable_ioctl(vfd, VIDIOC_TRY_ENCODER_CMD);\n+\t\tv4l2_disable_ioctl(vfd, VIDIOC_S_PARM);\n+\t\tv4l2_disable_ioctl(vfd, VIDIOC_G_PARM);\n+\t\tfunction = MEDIA_ENT_F_PROC_VIDEO_DECODER;\n+\t\tvideo_nr = decode_video_nr;\n+\t\tbreak;\n+\tcase ENCODE:\n+\t\tv4l2_disable_ioctl(vfd, VIDIOC_DECODER_CMD);\n+\t\tv4l2_disable_ioctl(vfd, VIDIOC_TRY_DECODER_CMD);\n+\t\tfunction = MEDIA_ENT_F_PROC_VIDEO_ENCODER;\n+\t\tvideo_nr = encode_video_nr;\n+\t\tbreak;\n+\tcase ISP:\n+\t\tv4l2_disable_ioctl(vfd, VIDIOC_ENCODER_CMD);\n+\t\tv4l2_disable_ioctl(vfd, VIDIOC_TRY_ENCODER_CMD);\n+\t\tv4l2_disable_ioctl(vfd, VIDIOC_DECODER_CMD);\n+\t\tv4l2_disable_ioctl(vfd, VIDIOC_TRY_DECODER_CMD);\n+\t\tv4l2_disable_ioctl(vfd, VIDIOC_S_PARM);\n+\t\tv4l2_disable_ioctl(vfd, VIDIOC_G_PARM);\n+\t\tfunction = MEDIA_ENT_F_PROC_VIDEO_SCALER;\n+\t\tvideo_nr = isp_video_nr;\n+\t\tbreak;\n+\tdefault:\n+\t\tret = -EINVAL;\n+\t\tgoto unreg_dev;\n+\t}\n+\n+\tret = video_register_device(vfd, VFL_TYPE_VIDEO, video_nr);\n+\tif (ret) {\n+\t\tv4l2_err(&dev->v4l2_dev, \"Failed to register video device\\n\");\n+\t\tgoto unreg_dev;\n+\t}\n+\n+\tvideo_set_drvdata(vfd, dev);\n+\tsnprintf(vfd->name, sizeof(vfd->name), \"%s-%s\",\n+\t\t bcm2835_codec_videodev.name, roles[role]);\n+\tv4l2_info(&dev->v4l2_dev, \"Device registered as /dev/video%d\\n\",\n+\t\t  vfd->num);\n+\n+\t*new_dev = dev;\n+\n+\tdev->m2m_dev = v4l2_m2m_init(&m2m_ops);\n+\tif (IS_ERR(dev->m2m_dev)) {\n+\t\tv4l2_err(&dev->v4l2_dev, \"Failed to init mem2mem device\\n\");\n+\t\tret = PTR_ERR(dev->m2m_dev);\n+\t\tgoto err_m2m;\n+\t}\n+\n+\tret = v4l2_m2m_register_media_controller(dev->m2m_dev, vfd, function);\n+\tif (ret)\n+\t\tgoto err_m2m;\n+\n+\tv4l2_info(&dev->v4l2_dev, \"Loaded V4L2 %s\\n\",\n+\t\t  roles[role]);\n+\treturn 0;\n+\n+err_m2m:\n+\tv4l2_m2m_release(dev->m2m_dev);\n+\tvideo_unregister_device(&dev->vfd);\n+unreg_dev:\n+\tv4l2_device_unregister(&dev->v4l2_dev);\n+vchiq_finalise:\n+\tvchiq_mmal_finalise(dev->instance);\n+\treturn ret;\n+}\n+\n+static int bcm2835_codec_destroy(struct bcm2835_codec_dev *dev)\n+{\n+\tif (!dev)\n+\t\treturn -ENODEV;\n+\n+\tv4l2_info(&dev->v4l2_dev, \"Removing \" MEM2MEM_NAME \", %s\\n\",\n+\t\t  roles[dev->role]);\n+\tv4l2_m2m_unregister_media_controller(dev->m2m_dev);\n+\tv4l2_m2m_release(dev->m2m_dev);\n+\tvideo_unregister_device(&dev->vfd);\n+\tv4l2_device_unregister(&dev->v4l2_dev);\n+\tvchiq_mmal_finalise(dev->instance);\n+\n+\treturn 0;\n+}\n+\n+static int bcm2835_codec_probe(struct platform_device *pdev)\n+{\n+\tstruct bcm2835_codec_driver *drv;\n+\tstruct media_device *mdev;\n+\tint ret = 0;\n+\n+\tdrv = devm_kzalloc(&pdev->dev, sizeof(*drv), GFP_KERNEL);\n+\tif (!drv)\n+\t\treturn -ENOMEM;\n+\n+\tdrv->pdev = pdev;\n+\tmdev = &drv->mdev;\n+\tmdev->dev = &pdev->dev;\n+\n+\tstrscpy(mdev->model, bcm2835_codec_videodev.name, sizeof(mdev->model));\n+\tstrscpy(mdev->serial, \"0000\", sizeof(mdev->serial));\n+\tsnprintf(mdev->bus_info, sizeof(mdev->bus_info), \"platform:%s\",\n+\t\t pdev->name);\n+\n+\t/* This should return the vgencmd version information or such .. */\n+\tmdev->hw_revision = 1;\n+\tmedia_device_init(mdev);\n+\n+\tret = bcm2835_codec_create(drv, &drv->decode, DECODE);\n+\tif (ret)\n+\t\tgoto out;\n+\n+\tret = bcm2835_codec_create(drv, &drv->encode, ENCODE);\n+\tif (ret)\n+\t\tgoto out;\n+\n+\tret = bcm2835_codec_create(drv, &drv->isp, ISP);\n+\tif (ret)\n+\t\tgoto out;\n+\n+\t/* Register the media device node */\n+\tif (media_device_register(mdev) < 0)\n+\t\tgoto out;\n+\n+\tplatform_set_drvdata(pdev, drv);\n+\n+\treturn 0;\n+\n+out:\n+\tif (drv->isp) {\n+\t\tbcm2835_codec_destroy(drv->isp);\n+\t\tdrv->isp = NULL;\n+\t}\n+\tif (drv->encode) {\n+\t\tbcm2835_codec_destroy(drv->encode);\n+\t\tdrv->encode = NULL;\n+\t}\n+\tif (drv->decode) {\n+\t\tbcm2835_codec_destroy(drv->decode);\n+\t\tdrv->decode = NULL;\n+\t}\n+\treturn ret;\n+}\n+\n+static int bcm2835_codec_remove(struct platform_device *pdev)\n+{\n+\tstruct bcm2835_codec_driver *drv = platform_get_drvdata(pdev);\n+\n+\tmedia_device_unregister(&drv->mdev);\n+\n+\tbcm2835_codec_destroy(drv->isp);\n+\n+\tbcm2835_codec_destroy(drv->encode);\n+\n+\tbcm2835_codec_destroy(drv->decode);\n+\n+\tmedia_device_cleanup(&drv->mdev);\n+\n+\treturn 0;\n+}\n+\n+static struct platform_driver bcm2835_v4l2_codec_driver = {\n+\t.probe = bcm2835_codec_probe,\n+\t.remove = bcm2835_codec_remove,\n+\t.driver = {\n+\t\t   .name = \"bcm2835-codec\",\n+\t\t   .owner = THIS_MODULE,\n+\t\t   },\n+};\n+\n+module_platform_driver(bcm2835_v4l2_codec_driver);\n+\n+MODULE_DESCRIPTION(\"BCM2835 codec V4L2 driver\");\n+MODULE_AUTHOR(\"Dave Stevenson, <dave.stevenson@raspberrypi.com>\");\n+MODULE_LICENSE(\"GPL\");\n+MODULE_VERSION(\"0.0.1\");\n+MODULE_ALIAS(\"platform:bcm2835-codec\");\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0343-bcm2835-dma-only-reserve-channel-0-if-legacy-dma-dri.patch",
    "content": "From 137865877ea138ef9c593ce74cbd4ddc2560e057 Mon Sep 17 00:00:00 2001\nFrom: Matthias Reichl <hias@horus.com>\nDate: Sun, 11 Oct 2020 00:48:55 +0200\nSubject: [PATCH] bcm2835-dma: only reserve channel 0 if legacy dma\n driver is enabled\n\nIf CONFIG_DMA_BCM2708 isn't enabled there's no need to mask out\none of the already scarce DMA channels.\n\nSigned-off-by: Matthias Reichl <hias@horus.com>\n---\n drivers/dma/bcm2835-dma.c | 2 ++\n 1 file changed, 2 insertions(+)\n\n--- a/drivers/dma/bcm2835-dma.c\n+++ b/drivers/dma/bcm2835-dma.c\n@@ -1283,6 +1283,7 @@ static int bcm2835_dma_probe(struct plat\n \t\tgoto err_no_dma;\n \t}\n \n+#ifdef CONFIG_DMA_BCM2708\n \t/* One channel is reserved for the legacy API */\n \tif (chans_available & BCM2835_DMA_BULK_MASK) {\n \t\trc = bcm_dmaman_probe(pdev, base,\n@@ -1293,6 +1294,7 @@ static int bcm2835_dma_probe(struct plat\n \n \t\tchans_available &= ~BCM2835_DMA_BULK_MASK;\n \t}\n+#endif\n \n \t/* And possibly one for the 40-bit DMA memcpy API */\n \tif (chans_available & od->cfg_data->chan_40bit_mask &\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0344-uapi-bcm2835-isp-Add-bcm2835-isp-uapi-header-file.patch",
    "content": "From 29ac7eb75ee5ff8aeed1017f741b9f0bf2c94a89 Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Mon, 12 Oct 2020 17:03:14 +0100\nSubject: [PATCH] uapi: bcm2835-isp: Add bcm2835-isp uapi header file\n\nThis file defines the userland interface to the bcm2835-isp driver\nthat will follow in a separate commit.\n\nSigned-off-by: Naushir Patuck <naush@raspberrypi.com>\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n include/uapi/linux/bcm2835-isp.h | 320 +++++++++++++++++++++++++++++++\n 1 file changed, 320 insertions(+)\n create mode 100644 include/uapi/linux/bcm2835-isp.h\n\n--- /dev/null\n+++ b/include/uapi/linux/bcm2835-isp.h\n@@ -0,0 +1,320 @@\n+/* SPDX-License-Identifier: ((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) */\n+/*\n+ * bcm2835-isp.h\n+ *\n+ * BCM2835 ISP driver - user space header file.\n+ *\n+ * Copyright © 2019-2020 Raspberry Pi (Trading) Ltd.\n+ *\n+ * Author: Naushir Patuck (naush@raspberrypi.com)\n+ *\n+ */\n+\n+#ifndef __BCM2835_ISP_H_\n+#define __BCM2835_ISP_H_\n+\n+#include <linux/v4l2-controls.h>\n+\n+#define V4L2_CID_USER_BCM2835_ISP_CC_MATRIX\t\\\n+\t\t\t\t(V4L2_CID_USER_BCM2835_ISP_BASE + 0x0001)\n+#define V4L2_CID_USER_BCM2835_ISP_LENS_SHADING\t\\\n+\t\t\t\t(V4L2_CID_USER_BCM2835_ISP_BASE + 0x0002)\n+#define V4L2_CID_USER_BCM2835_ISP_BLACK_LEVEL\t\\\n+\t\t\t\t(V4L2_CID_USER_BCM2835_ISP_BASE + 0x0003)\n+#define V4L2_CID_USER_BCM2835_ISP_GEQ\t\t\\\n+\t\t\t\t(V4L2_CID_USER_BCM2835_ISP_BASE + 0x0004)\n+#define V4L2_CID_USER_BCM2835_ISP_GAMMA\t\t\\\n+\t\t\t\t(V4L2_CID_USER_BCM2835_ISP_BASE + 0x0005)\n+#define V4L2_CID_USER_BCM2835_ISP_DENOISE\t\\\n+\t\t\t\t(V4L2_CID_USER_BCM2835_ISP_BASE + 0x0006)\n+#define V4L2_CID_USER_BCM2835_ISP_SHARPEN\t\\\n+\t\t\t\t(V4L2_CID_USER_BCM2835_ISP_BASE + 0x0007)\n+#define V4L2_CID_USER_BCM2835_ISP_DPC\t\t\\\n+\t\t\t\t(V4L2_CID_USER_BCM2835_ISP_BASE + 0x0008)\n+\n+/*\n+ * All structs below are directly mapped onto the equivalent structs in\n+ * drivers/staging/vc04_services/vchiq-mmal/mmal-parameters.h\n+ * for convenience.\n+ */\n+\n+/**\n+ * struct bcm2835_isp_rational - Rational value type.\n+ *\n+ * @num:\tNumerator.\n+ * @den:\tDenominator.\n+ */\n+struct bcm2835_isp_rational {\n+\t__s32 num;\n+\t__u32 den;\n+};\n+\n+/**\n+ * struct bcm2835_isp_ccm - Colour correction matrix.\n+ *\n+ * @ccm:\t3x3 correction matrix coefficients.\n+ * @offsets:\t1x3 correction offsets.\n+ */\n+struct bcm2835_isp_ccm {\n+\tstruct bcm2835_isp_rational ccm[3][3];\n+\t__s32 offsets[3];\n+};\n+\n+/**\n+ * struct bcm2835_isp_custom_ccm - Custom CCM applied with the\n+ *\t\t\t\t   V4L2_CID_USER_BCM2835_ISP_CC_MATRIX ctrl.\n+ *\n+ * @enabled:\tEnable custom CCM.\n+ * @ccm:\tCustom CCM coefficients and offsets.\n+ */\n+struct bcm2835_isp_custom_ccm {\n+\t__u32 enabled;\n+\tstruct bcm2835_isp_ccm ccm;\n+};\n+\n+/**\n+ * enum bcm2835_isp_gain_format - format of the gains in the lens shading\n+ *\t\t\t\t  tables used with the\n+ *\t\t\t\t  V4L2_CID_USER_BCM2835_ISP_LENS_SHADING ctrl.\n+ *\n+ * @GAIN_FORMAT_U0P8_1:\t\tGains are u0.8 format, starting at 1.0\n+ * @GAIN_FORMAT_U1P7_0:\t\tGains are u1.7 format, starting at 0.0\n+ * @GAIN_FORMAT_U1P7_1:\t\tGains are u1.7 format, starting at 1.0\n+ * @GAIN_FORMAT_U2P6_0:\t\tGains are u2.6 format, starting at 0.0\n+ * @GAIN_FORMAT_U2P6_1:\t\tGains are u2.6 format, starting at 1.0\n+ * @GAIN_FORMAT_U3P5_0:\t\tGains are u3.5 format, starting at 0.0\n+ * @GAIN_FORMAT_U3P5_1:\t\tGains are u3.5 format, starting at 1.0\n+ * @GAIN_FORMAT_U4P10:\t\tGains are u4.10 format, starting at 0.0\n+ */\n+enum bcm2835_isp_gain_format {\n+\tGAIN_FORMAT_U0P8_1 = 0,\n+\tGAIN_FORMAT_U1P7_0 = 1,\n+\tGAIN_FORMAT_U1P7_1 = 2,\n+\tGAIN_FORMAT_U2P6_0 = 3,\n+\tGAIN_FORMAT_U2P6_1 = 4,\n+\tGAIN_FORMAT_U3P5_0 = 5,\n+\tGAIN_FORMAT_U3P5_1 = 6,\n+\tGAIN_FORMAT_U4P10  = 7,\n+};\n+\n+/**\n+ * struct bcm2835_isp_lens_shading - Lens shading tables supplied with the\n+ *\t\t\t\t     V4L2_CID_USER_BCM2835_ISP_LENS_SHADING\n+ *\t\t\t\t     ctrl.\n+ *\n+ * @enabled:\t\tEnable lens shading.\n+ * @grid_cell_size:\tSize of grid cells in samples (16, 32, 64, 128 or 256).\n+ * @grid_width:\t\tWidth of lens shading tables in grid cells.\n+ * @grid_stride:\tRow to row distance (in grid cells) between grid cells\n+ *\t\t\tin the same horizontal location.\n+ * @grid_height:\tHeight of lens shading tables in grid cells.\n+ * @dmabuf:\t\tdmabuf file handle containing the table.\n+ * @ref_transform:\tReference transform - unsupported, please pass zero.\n+ * @corner_sampled:\tWhether the gains are sampled at the corner points\n+ *\t\t\tof the grid cells or in the cell centres.\n+ * @gain_format:\tFormat of the gains (see enum &bcm2835_isp_gain_format).\n+ */\n+struct bcm2835_isp_lens_shading {\n+\t__u32 enabled;\n+\t__u32 grid_cell_size;\n+\t__u32 grid_width;\n+\t__u32 grid_stride;\n+\t__u32 grid_height;\n+\t__s32 dmabuf;\n+\t__u32 ref_transform;\n+\t__u32 corner_sampled;\n+\t__u32 gain_format;\n+};\n+\n+/**\n+ * struct bcm2835_isp_black_level - Sensor black level set with the\n+ *\t\t\t\t    V4L2_CID_USER_BCM2835_ISP_BLACK_LEVEL ctrl.\n+ *\n+ * @enabled:\t\tEnable black level.\n+ * @black_level_r:\tBlack level for red channel.\n+ * @black_level_g:\tBlack level for green channels.\n+ * @black_level_b:\tBlack level for blue channel.\n+ */\n+struct bcm2835_isp_black_level {\n+\t__u32 enabled;\n+\t__u16 black_level_r;\n+\t__u16 black_level_g;\n+\t__u16 black_level_b;\n+\t__u8 padding[2]; /* Unused */\n+};\n+\n+/**\n+ * struct bcm2835_isp_geq - Green equalisation parameters set with the\n+ *\t\t\t    V4L2_CID_USER_BCM2835_ISP_GEQ ctrl.\n+ *\n+ * @enabled:\tEnable green equalisation.\n+ * @offset:\tFixed offset of the green equalisation threshold.\n+ * @slope:\tSlope of the green equalisation threshold.\n+ */\n+struct bcm2835_isp_geq {\n+\t__u32 enabled;\n+\t__u32 offset;\n+\tstruct bcm2835_isp_rational slope;\n+};\n+\n+#define BCM2835_NUM_GAMMA_PTS 33\n+\n+/**\n+ * struct bcm2835_isp_gamma - Gamma parameters set with the\n+ *\t\t\t      V4L2_CID_USER_BCM2835_ISP_GAMMA ctrl.\n+ *\n+ * @enabled:\tEnable gamma adjustment.\n+ * @X:\t\tX values of the points defining the gamma curve.\n+ *\t\tValues should be scaled to 16 bits.\n+ * @Y:\t\tY values of the points defining the gamma curve.\n+ *\t\tValues should be scaled to 16 bits.\n+ */\n+struct bcm2835_isp_gamma {\n+\t__u32 enabled;\n+\t__u16 x[BCM2835_NUM_GAMMA_PTS];\n+\t__u16 y[BCM2835_NUM_GAMMA_PTS];\n+};\n+\n+/**\n+ * struct bcm2835_isp_denoise - Denoise parameters set with the\n+ *\t\t\t\tV4L2_CID_USER_BCM2835_ISP_DENOISE ctrl.\n+ *\n+ * @enabled:\tEnable denoise.\n+ * @constant:\tFixed offset of the noise threshold.\n+ * @slope:\tSlope of the noise threshold.\n+ * @strength:\tDenoise strength between 0.0 (off) and 1.0 (maximum).\n+ */\n+struct bcm2835_isp_denoise {\n+\t__u32 enabled;\n+\t__u32 constant;\n+\tstruct bcm2835_isp_rational slope;\n+\tstruct bcm2835_isp_rational strength;\n+};\n+\n+/**\n+ * struct bcm2835_isp_sharpen - Sharpen parameters set with the\n+ *\t\t\t\tV4L2_CID_USER_BCM2835_ISP_SHARPEN ctrl.\n+ *\n+ * @enabled:\tEnable sharpening.\n+ * @threshold:\tThreshold at which to start sharpening pixels.\n+ * @strength:\tStrength with which pixel sharpening increases.\n+ * @limit:\tLimit to the amount of sharpening applied.\n+ */\n+struct bcm2835_isp_sharpen {\n+\t__u32 enabled;\n+\tstruct bcm2835_isp_rational threshold;\n+\tstruct bcm2835_isp_rational strength;\n+\tstruct bcm2835_isp_rational limit;\n+};\n+\n+/**\n+ * enum bcm2835_isp_dpc_mode - defective pixel correction (DPC) strength.\n+ *\n+ * @DPC_MODE_OFF:\t\tNo DPC.\n+ * @DPC_MODE_NORMAL:\t\tNormal DPC.\n+ * @DPC_MODE_STRONG:\t\tStrong DPC.\n+ */\n+enum bcm2835_isp_dpc_mode {\n+\tDPC_MODE_OFF = 0,\n+\tDPC_MODE_NORMAL = 1,\n+\tDPC_MODE_STRONG = 2,\n+};\n+\n+/**\n+ * struct bcm2835_isp_dpc - Defective pixel correction (DPC) parameters set\n+ *\t\t\t    with the V4L2_CID_USER_BCM2835_ISP_DPC ctrl.\n+ *\n+ * @enabled:\tEnable DPC.\n+ * @strength:\tDPC strength (see enum &bcm2835_isp_dpc_mode).\n+ */\n+struct bcm2835_isp_dpc {\n+\t__u32 enabled;\n+\t__u32 strength;\n+};\n+\n+/*\n+ * ISP statistics structures.\n+ *\n+ * The bcm2835_isp_stats structure is generated at the output of the\n+ * statistics node.  Note that this does not directly map onto the statistics\n+ * output of the ISP HW.  Instead, the MMAL firmware code maps the HW statistics\n+ * to the bcm2835_isp_stats structure.\n+ */\n+#define DEFAULT_AWB_REGIONS_X 16\n+#define DEFAULT_AWB_REGIONS_Y 12\n+\n+#define NUM_HISTOGRAMS 2\n+#define NUM_HISTOGRAM_BINS 128\n+#define AWB_REGIONS (DEFAULT_AWB_REGIONS_X * DEFAULT_AWB_REGIONS_Y)\n+#define FLOATING_REGIONS 16\n+#define AGC_REGIONS 16\n+#define FOCUS_REGIONS 12\n+\n+/**\n+ * struct bcm2835_isp_stats_hist - Histogram statistics\n+ *\n+ * @r_hist:\tRed channel histogram.\n+ * @g_hist:\tCombined green channel histogram.\n+ * @b_hist:\tBlue channel histogram.\n+ */\n+struct bcm2835_isp_stats_hist {\n+\t__u32 r_hist[NUM_HISTOGRAM_BINS];\n+\t__u32 g_hist[NUM_HISTOGRAM_BINS];\n+\t__u32 b_hist[NUM_HISTOGRAM_BINS];\n+};\n+\n+/**\n+ * struct bcm2835_isp_stats_region - Region sums.\n+ *\n+ * @counted:\tThe number of 2x2 bayer tiles accumulated.\n+ * @notcounted:\tThe number of 2x2 bayer tiles not accumulated.\n+ * @r_sum:\tTotal sum of counted pixels in the red channel for a region.\n+ * @g_sum:\tTotal sum of counted pixels in the green channel for a region.\n+ * @b_sum:\tTotal sum of counted pixels in the blue channel for a region.\n+ */\n+struct bcm2835_isp_stats_region {\n+\t__u32 counted;\n+\t__u32 notcounted;\n+\t__u64 r_sum;\n+\t__u64 g_sum;\n+\t__u64 b_sum;\n+};\n+\n+/**\n+ * struct bcm2835_isp_stats_focus - Focus statistics.\n+ *\n+ * @contrast_val:\tFocus measure - accumulated output of the focus filter.\n+ *\t\t\tIn the first dimension, index [0] counts pixels below a\n+ *\t\t\tpreset threshold, and index [1] counts pixels above the\n+ *\t\t\tthreshold.  In the second dimension, index [0] uses the\n+ *\t\t\tfirst predefined filter, and index [1] uses the second\n+ *\t\t\tpredefined filter.\n+ * @contrast_val_num:\tThe number of counted pixels in the above accumulation.\n+ */\n+struct bcm2835_isp_stats_focus {\n+\t__u64 contrast_val[2][2];\n+\t__u32 contrast_val_num[2][2];\n+};\n+\n+/**\n+ * struct bcm2835_isp_stats - ISP statistics.\n+ *\n+ * @version:\t\tVersion of the bcm2835_isp_stats structure.\n+ * @size:\t\tSize of the bcm2835_isp_stats structure.\n+ * @hist:\t\tHistogram statistics for the entire image.\n+ * @awb_stats:\t\tStatistics for the regions defined for AWB calculations.\n+ * @floating_stats:\tStatistics for arbitrarily placed (floating) regions.\n+ * @agc_stats:\t\tStatistics for the regions defined for AGC calculations.\n+ * @focus_stats:\tFocus filter statistics for the focus regions.\n+ */\n+struct bcm2835_isp_stats {\n+\t__u32 version;\n+\t__u32 size;\n+\tstruct bcm2835_isp_stats_hist hist[NUM_HISTOGRAMS];\n+\tstruct bcm2835_isp_stats_region awb_stats[AWB_REGIONS];\n+\tstruct bcm2835_isp_stats_region floating_stats[FLOATING_REGIONS];\n+\tstruct bcm2835_isp_stats_region agc_stats[AGC_REGIONS];\n+\tstruct bcm2835_isp_stats_focus focus_stats[FOCUS_REGIONS];\n+};\n+\n+#endif /* __BCM2835_ISP_H_ */\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0345-staging-vc04_services-ISP-Add-a-more-complex-ISP-pro.patch",
    "content": "From 852ada216764e02c211a9029de885d11868e0bbc Mon Sep 17 00:00:00 2001\nFrom: Naushir Patuck <naush@raspberrypi.com>\nDate: Thu, 23 Apr 2020 10:17:37 +0100\nSubject: [PATCH] staging: vc04_services: ISP: Add a more complex ISP\n processing component\n\nDriver for the BCM2835 ISP hardware block.  This driver uses the MMAL\ncomponent to program the ISP hardware through the VC firmware.\n\nThe ISP component can produce two video stream outputs, and Bayer\nimage statistics. This can't be encompassed in a simple V4L2\nM2M device, so create a new device that registers 4 video nodes.\n\nThis patch squashes all the development patches from the earlier\nrpi-5.4.y branch into one\n\nSigned-off-by: Naushir Patuck <naush@raspberrypi.com>\n---\n MAINTAINERS                                   |    9 +\n drivers/staging/vc04_services/Kconfig         |    1 +\n drivers/staging/vc04_services/Makefile        |    1 +\n .../staging/vc04_services/bcm2835-isp/Kconfig |   14 +\n .../vc04_services/bcm2835-isp/Makefile        |    8 +\n .../bcm2835-isp/bcm2835-isp-ctrls.h           |   67 +\n .../bcm2835-isp/bcm2835-isp-fmts.h            |  353 ++++\n .../bcm2835-isp/bcm2835-v4l2-isp.c            | 1694 +++++++++++++++++\n .../vc04_services/vchiq-mmal/mmal-encodings.h |    4 +\n .../vchiq-mmal/mmal-parameters.h              |  153 +-\n 10 files changed, 2303 insertions(+), 1 deletion(-)\n create mode 100644 drivers/staging/vc04_services/bcm2835-isp/Kconfig\n create mode 100644 drivers/staging/vc04_services/bcm2835-isp/Makefile\n create mode 100644 drivers/staging/vc04_services/bcm2835-isp/bcm2835-isp-ctrls.h\n create mode 100644 drivers/staging/vc04_services/bcm2835-isp/bcm2835-isp-fmts.h\n create mode 100644 drivers/staging/vc04_services/bcm2835-isp/bcm2835-v4l2-isp.c\n\n--- a/MAINTAINERS\n+++ b/MAINTAINERS\n@@ -3432,6 +3432,15 @@ S:\tMaintained\n F:\tdrivers/media/platform/bcm2835/\n F:\tDocumentation/devicetree/bindings/media/brcm,bcm2835-unicam.yaml\n \n+BROADCOM BCM2835 ISP DRIVER\n+M:\tRaspberry Pi Kernel Maintenance <kernel-list@raspberrypi.com>\n+L:\tlinux-media@vger.kernel.org\n+S:\tMaintained\n+F:\tDocumentation/media/uapi/v4l/pixfmt-meta-bcm2835-isp-stats.rst\n+F:\tDocumentation/media/v4l-drivers/bcm2835-isp.rst\n+F:\tdrivers/staging/vc04_services/bcm2835-isp\n+F:\tinclude/uapi/linux/bcm2835-isp.h\n+\n BROADCOM BCM47XX MIPS ARCHITECTURE\n M:\tHauke Mehrtens <hauke@hauke-m.de>\n M:\tRafał Miłecki <zajec5@gmail.com>\n--- a/drivers/staging/vc04_services/Kconfig\n+++ b/drivers/staging/vc04_services/Kconfig\n@@ -25,6 +25,7 @@ source \"drivers/staging/vc04_services/bc\n \n source \"drivers/staging/vc04_services/vc-sm-cma/Kconfig\"\n source \"drivers/staging/vc04_services/bcm2835-codec/Kconfig\"\n+source \"drivers/staging/vc04_services/bcm2835-isp/Kconfig\"\n \n source \"drivers/staging/vc04_services/vchiq-mmal/Kconfig\"\n \n--- a/drivers/staging/vc04_services/Makefile\n+++ b/drivers/staging/vc04_services/Makefile\n@@ -13,6 +13,7 @@ obj-$(CONFIG_VIDEO_BCM2835)\t\t+= bcm2835-\n obj-$(CONFIG_BCM2835_VCHIQ_MMAL)\t+= vchiq-mmal/\n obj-$(CONFIG_BCM_VC_SM_CMA)\t\t+= vc-sm-cma/\n obj-$(CONFIG_VIDEO_CODEC_BCM2835)\t+= bcm2835-codec/\n+obj-$(CONFIG_VIDEO_ISP_BCM2835)\t\t+= bcm2835-isp/\n \n ccflags-y += -I $(srctree)/$(src)/include  -D__VCCOREVER__=0x04000000\n \n--- /dev/null\n+++ b/drivers/staging/vc04_services/bcm2835-isp/Kconfig\n@@ -0,0 +1,14 @@\n+config VIDEO_ISP_BCM2835\n+\ttristate \"BCM2835 ISP support\"\n+\tdepends on MEDIA_SUPPORT\n+\tdepends on VIDEO_V4L2 && (ARCH_BCM2835 || COMPILE_TEST)\n+\tdepends on MEDIA_CONTROLLER\n+\tselect BCM2835_VCHIQ_MMAL\n+\tselect VIDEOBUF2_DMA_CONTIG\n+\thelp\n+\t  This is the V4L2 driver for the Broadcom BCM2835 ISP hardware.\n+\t  This operates over the VCHIQ interface to a service running on\n+\t  VideoCore.\n+\n+\t  To compile this driver as a module, choose M here: the module\n+\t  will be called bcm2835-isp.\n--- /dev/null\n+++ b/drivers/staging/vc04_services/bcm2835-isp/Makefile\n@@ -0,0 +1,8 @@\n+# SPDX-License-Identifier: GPL-2.0\n+bcm2835-isp-objs := bcm2835-v4l2-isp.o\n+\n+obj-$(CONFIG_VIDEO_ISP_BCM2835) += bcm2835-isp.o\n+\n+ccflags-y += \\\n+\t-I$(srctree)/drivers/staging/vc04_services \\\n+\t-D__VCCOREVER__=0x04000000\n--- /dev/null\n+++ b/drivers/staging/vc04_services/bcm2835-isp/bcm2835-isp-ctrls.h\n@@ -0,0 +1,67 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+/*\n+ * Broadcom BCM2835 ISP driver\n+ *\n+ * Copyright © 2019-2020 Raspberry Pi (Trading) Ltd.\n+ *\n+ * Author: Naushir Patuck (naush@raspberrypi.com)\n+ *\n+ */\n+\n+#ifndef BCM2835_ISP_CTRLS\n+#define BCM2835_ISP_CTRLS\n+\n+#include <linux/bcm2835-isp.h>\n+\n+struct bcm2835_isp_custom_ctrl {\n+\tconst char *name;\n+\tu32 id;\n+\tu32 size;\n+\tu32 flags;\n+};\n+\n+static const struct bcm2835_isp_custom_ctrl custom_ctrls[] = {\n+\t{\n+\t\t.name\t= \"Colour Correction Matrix\",\n+\t\t.id\t= V4L2_CID_USER_BCM2835_ISP_CC_MATRIX,\n+\t\t.size\t= sizeof(struct bcm2835_isp_custom_ccm),\n+\t\t.flags  = 0\n+\t}, {\n+\t\t.name\t= \"Lens Shading\",\n+\t\t.id\t= V4L2_CID_USER_BCM2835_ISP_LENS_SHADING,\n+\t\t.size\t= sizeof(struct bcm2835_isp_lens_shading),\n+\t\t.flags  = V4L2_CTRL_FLAG_EXECUTE_ON_WRITE\n+\t}, {\n+\t\t.name\t= \"Black Level\",\n+\t\t.id\t= V4L2_CID_USER_BCM2835_ISP_BLACK_LEVEL,\n+\t\t.size\t= sizeof(struct bcm2835_isp_black_level),\n+\t\t.flags  = 0\n+\t}, {\n+\t\t.name\t= \"Green Equalisation\",\n+\t\t.id\t= V4L2_CID_USER_BCM2835_ISP_GEQ,\n+\t\t.size\t= sizeof(struct bcm2835_isp_geq),\n+\t\t.flags  = 0\n+\t}, {\n+\t\t.name\t= \"Gamma\",\n+\t\t.id\t= V4L2_CID_USER_BCM2835_ISP_GAMMA,\n+\t\t.size\t= sizeof(struct bcm2835_isp_gamma),\n+\t\t.flags  = 0\n+\t}, {\n+\t\t.name\t= \"Sharpen\",\n+\t\t.id\t= V4L2_CID_USER_BCM2835_ISP_SHARPEN,\n+\t\t.size\t= sizeof(struct bcm2835_isp_sharpen),\n+\t\t.flags  = 0\n+\t}, {\n+\t\t.name\t= \"Denoise\",\n+\t\t.id\t= V4L2_CID_USER_BCM2835_ISP_DENOISE,\n+\t\t.size\t= sizeof(struct bcm2835_isp_denoise),\n+\t\t.flags  = 0\n+\t}, {\n+\t\t.name\t= \"Defective Pixel Correction\",\n+\t\t.id\t= V4L2_CID_USER_BCM2835_ISP_DPC,\n+\t\t.size\t= sizeof(struct bcm2835_isp_dpc),\n+\t\t.flags  = 0\n+\t}\n+};\n+\n+#endif\n--- /dev/null\n+++ b/drivers/staging/vc04_services/bcm2835-isp/bcm2835-isp-fmts.h\n@@ -0,0 +1,353 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+/*\n+ * Broadcom BCM2835 ISP driver\n+ *\n+ * Copyright © 2019-2020 Raspberry Pi (Trading) Ltd.\n+ *\n+ * Author: Naushir Patuck (naush@raspberrypi.com)\n+ *\n+ */\n+\n+#ifndef BCM2835_ISP_FMTS\n+#define BCM2835_ISP_FMTS\n+\n+#include <linux/videodev2.h>\n+#include \"vchiq-mmal/mmal-encodings.h\"\n+\n+struct bcm2835_isp_fmt {\n+\tu32 fourcc;\n+\tint depth;\n+\tint bytesperline_align;\n+\tu32 mmal_fmt;\n+\tint size_multiplier_x2;\n+\tenum v4l2_colorspace colorspace;\n+\tunsigned int step_size;\n+};\n+\n+static const struct bcm2835_isp_fmt supported_formats[] = {\n+\t{\n+\t\t/* YUV formats */\n+\t\t.fourcc\t\t    = V4L2_PIX_FMT_YUV420,\n+\t\t.depth\t\t    = 8,\n+\t\t.bytesperline_align = 32,\n+\t\t.mmal_fmt\t    = MMAL_ENCODING_I420,\n+\t\t.size_multiplier_x2 = 3,\n+\t\t.colorspace\t    = V4L2_COLORSPACE_SMPTE170M,\n+\t\t.step_size\t    = 2,\n+\t}, {\n+\t\t.fourcc\t\t    = V4L2_PIX_FMT_YVU420,\n+\t\t.depth\t\t    = 8,\n+\t\t.bytesperline_align = 32,\n+\t\t.mmal_fmt\t    = MMAL_ENCODING_YV12,\n+\t\t.size_multiplier_x2 = 3,\n+\t\t.colorspace\t    = V4L2_COLORSPACE_SMPTE170M,\n+\t\t.step_size\t    = 2,\n+\t}, {\n+\t\t.fourcc\t\t    = V4L2_PIX_FMT_NV12,\n+\t\t.depth\t\t    = 8,\n+\t\t.bytesperline_align = 32,\n+\t\t.mmal_fmt\t    = MMAL_ENCODING_NV12,\n+\t\t.size_multiplier_x2 = 3,\n+\t\t.colorspace\t    = V4L2_COLORSPACE_SMPTE170M,\n+\t\t.step_size\t    = 2,\n+\t}, {\n+\t\t.fourcc\t\t    = V4L2_PIX_FMT_NV21,\n+\t\t.depth\t\t    = 8,\n+\t\t.bytesperline_align = 32,\n+\t\t.mmal_fmt\t    = MMAL_ENCODING_NV21,\n+\t\t.size_multiplier_x2 = 3,\n+\t\t.colorspace\t    = V4L2_COLORSPACE_SMPTE170M,\n+\t\t.step_size\t    = 2,\n+\t}, {\n+\t\t.fourcc\t\t    = V4L2_PIX_FMT_YUYV,\n+\t\t.depth\t\t    = 16,\n+\t\t.bytesperline_align = 64,\n+\t\t.mmal_fmt\t    = MMAL_ENCODING_YUYV,\n+\t\t.size_multiplier_x2 = 2,\n+\t\t.colorspace\t    = V4L2_COLORSPACE_SMPTE170M,\n+\t\t.step_size\t    = 2,\n+\t}, {\n+\t\t.fourcc\t\t    = V4L2_PIX_FMT_UYVY,\n+\t\t.depth\t\t    = 16,\n+\t\t.bytesperline_align = 64,\n+\t\t.mmal_fmt\t    = MMAL_ENCODING_UYVY,\n+\t\t.size_multiplier_x2 = 2,\n+\t\t.colorspace\t    = V4L2_COLORSPACE_SMPTE170M,\n+\t\t.step_size\t    = 2,\n+\t}, {\n+\t\t.fourcc\t\t    = V4L2_PIX_FMT_YVYU,\n+\t\t.depth\t\t    = 16,\n+\t\t.bytesperline_align = 64,\n+\t\t.mmal_fmt\t    = MMAL_ENCODING_YVYU,\n+\t\t.size_multiplier_x2 = 2,\n+\t\t.colorspace\t    = V4L2_COLORSPACE_SMPTE170M,\n+\t\t.step_size\t    = 2,\n+\t}, {\n+\t\t.fourcc\t\t    = V4L2_PIX_FMT_VYUY,\n+\t\t.depth\t\t    = 16,\n+\t\t.bytesperline_align = 64,\n+\t\t.mmal_fmt\t    = MMAL_ENCODING_VYUY,\n+\t\t.size_multiplier_x2 = 2,\n+\t\t.colorspace\t    = V4L2_COLORSPACE_SMPTE170M,\n+\t\t.step_size\t    = 2,\n+\t}, {\n+\t\t/* RGB formats */\n+\t\t.fourcc\t\t    = V4L2_PIX_FMT_RGB24,\n+\t\t.depth\t\t    = 24,\n+\t\t.bytesperline_align = 32,\n+\t\t.mmal_fmt\t    = MMAL_ENCODING_RGB24,\n+\t\t.size_multiplier_x2 = 2,\n+\t\t.colorspace\t    = V4L2_COLORSPACE_SRGB,\n+\t\t.step_size\t    = 1,\n+\t}, {\n+\t\t.fourcc\t\t    = V4L2_PIX_FMT_RGB565,\n+\t\t.depth\t\t    = 16,\n+\t\t.bytesperline_align = 32,\n+\t\t.mmal_fmt\t    = MMAL_ENCODING_RGB16,\n+\t\t.size_multiplier_x2 = 2,\n+\t\t.colorspace\t    = V4L2_COLORSPACE_SRGB,\n+\t\t.step_size\t    = 1,\n+\t}, {\n+\t\t.fourcc\t\t    = V4L2_PIX_FMT_BGR24,\n+\t\t.depth\t\t    = 24,\n+\t\t.bytesperline_align = 32,\n+\t\t.mmal_fmt\t    = MMAL_ENCODING_BGR24,\n+\t\t.size_multiplier_x2 = 2,\n+\t\t.colorspace\t    = V4L2_COLORSPACE_SRGB,\n+\t\t.step_size\t    = 1,\n+\t}, {\n+\t\t.fourcc\t\t    = V4L2_PIX_FMT_XBGR32,\n+\t\t.depth\t\t    = 32,\n+\t\t.bytesperline_align = 64,\n+\t\t.mmal_fmt\t    = MMAL_ENCODING_BGRA,\n+\t\t.size_multiplier_x2 = 2,\n+\t\t.colorspace\t    = V4L2_COLORSPACE_SRGB,\n+\t\t.step_size\t    = 1,\n+\t}, {\n+\t\t.fourcc\t\t    = V4L2_PIX_FMT_RGBX32,\n+\t\t.depth\t\t    = 32,\n+\t\t.bytesperline_align = 64,\n+\t\t.mmal_fmt\t    = MMAL_ENCODING_RGBA,\n+\t\t.size_multiplier_x2 = 2,\n+\t\t.colorspace\t    = V4L2_COLORSPACE_SRGB,\n+\t\t.step_size\t    = 1,\n+\t}, {\n+\t\t/* Bayer formats */\n+\t\t/* 8 bit */\n+\t\t.fourcc\t\t    = V4L2_PIX_FMT_SRGGB8,\n+\t\t.depth\t\t    = 8,\n+\t\t.bytesperline_align = 32,\n+\t\t.mmal_fmt\t    = MMAL_ENCODING_BAYER_SRGGB8,\n+\t\t.size_multiplier_x2 = 2,\n+\t\t.colorspace\t    = V4L2_COLORSPACE_RAW,\n+\t\t.step_size\t    = 2,\n+\t}, {\n+\t\t.fourcc\t\t    = V4L2_PIX_FMT_SBGGR8,\n+\t\t.depth\t\t    = 8,\n+\t\t.bytesperline_align = 32,\n+\t\t.mmal_fmt\t    = MMAL_ENCODING_BAYER_SBGGR8,\n+\t\t.size_multiplier_x2 = 2,\n+\t\t.colorspace\t    = V4L2_COLORSPACE_RAW,\n+\t\t.step_size\t    = 2,\n+\t}, {\n+\t\t.fourcc\t\t    = V4L2_PIX_FMT_SGRBG8,\n+\t\t.depth\t\t    = 8,\n+\t\t.bytesperline_align = 32,\n+\t\t.mmal_fmt\t    = MMAL_ENCODING_BAYER_SGRBG8,\n+\t\t.size_multiplier_x2 = 2,\n+\t\t.colorspace\t    = V4L2_COLORSPACE_RAW,\n+\t\t.step_size\t    = 2,\n+\t}, {\n+\t\t.fourcc\t\t    = V4L2_PIX_FMT_SGBRG8,\n+\t\t.depth\t\t    = 8,\n+\t\t.bytesperline_align = 32,\n+\t\t.mmal_fmt\t    = MMAL_ENCODING_BAYER_SGBRG8,\n+\t\t.size_multiplier_x2 = 2,\n+\t\t.colorspace\t    = V4L2_COLORSPACE_RAW,\n+\t\t.step_size\t    = 2,\n+\t}, {\n+\t\t/* 10 bit */\n+\t\t.fourcc\t\t    = V4L2_PIX_FMT_SRGGB10P,\n+\t\t.depth\t\t    = 10,\n+\t\t.bytesperline_align = 32,\n+\t\t.mmal_fmt\t    = MMAL_ENCODING_BAYER_SRGGB10P,\n+\t\t.size_multiplier_x2 = 2,\n+\t\t.colorspace\t    = V4L2_COLORSPACE_RAW,\n+\t\t.step_size\t    = 2,\n+\t}, {\n+\t\t.fourcc\t\t    = V4L2_PIX_FMT_SBGGR10P,\n+\t\t.depth\t\t    = 10,\n+\t\t.bytesperline_align = 32,\n+\t\t.mmal_fmt\t    = MMAL_ENCODING_BAYER_SBGGR10P,\n+\t\t.size_multiplier_x2 = 2,\n+\t\t.colorspace\t    = V4L2_COLORSPACE_RAW,\n+\t\t.step_size\t    = 2,\n+\t}, {\n+\t\t.fourcc\t\t    = V4L2_PIX_FMT_SGRBG10P,\n+\t\t.depth\t\t    = 10,\n+\t\t.bytesperline_align = 32,\n+\t\t.mmal_fmt\t    = MMAL_ENCODING_BAYER_SGRBG10P,\n+\t\t.size_multiplier_x2 = 2,\n+\t\t.colorspace\t    = V4L2_COLORSPACE_RAW,\n+\t\t.step_size\t    = 2,\n+\t}, {\n+\t\t.fourcc\t\t    = V4L2_PIX_FMT_SGBRG10P,\n+\t\t.depth\t\t    = 10,\n+\t\t.bytesperline_align = 32,\n+\t\t.mmal_fmt\t    = MMAL_ENCODING_BAYER_SGBRG10P,\n+\t\t.size_multiplier_x2 = 2,\n+\t\t.colorspace\t    = V4L2_COLORSPACE_RAW,\n+\t\t.step_size\t    = 2,\n+\t}, {\n+\t\t/* 12 bit */\n+\t\t.fourcc\t\t    = V4L2_PIX_FMT_SRGGB12P,\n+\t\t.depth\t\t    = 12,\n+\t\t.bytesperline_align = 32,\n+\t\t.mmal_fmt\t    = MMAL_ENCODING_BAYER_SRGGB12P,\n+\t\t.size_multiplier_x2 = 2,\n+\t\t.colorspace\t    = V4L2_COLORSPACE_RAW,\n+\t\t.step_size\t    = 2,\n+\t}, {\n+\t\t.fourcc\t\t    = V4L2_PIX_FMT_SBGGR12P,\n+\t\t.depth\t\t    = 12,\n+\t\t.bytesperline_align = 32,\n+\t\t.mmal_fmt\t    = MMAL_ENCODING_BAYER_SBGGR12P,\n+\t\t.size_multiplier_x2 = 2,\n+\t\t.colorspace\t    = V4L2_COLORSPACE_RAW,\n+\t\t.step_size\t    = 2,\n+\t}, {\n+\t\t.fourcc\t\t    = V4L2_PIX_FMT_SGRBG12P,\n+\t\t.depth\t\t    = 12,\n+\t\t.bytesperline_align = 32,\n+\t\t.mmal_fmt\t    = MMAL_ENCODING_BAYER_SGRBG12P,\n+\t\t.size_multiplier_x2 = 2,\n+\t\t.colorspace\t    = V4L2_COLORSPACE_RAW,\n+\t\t.step_size\t    = 2,\n+\t}, {\n+\t\t.fourcc\t\t    = V4L2_PIX_FMT_SGBRG12P,\n+\t\t.depth\t\t    = 12,\n+\t\t.bytesperline_align = 32,\n+\t\t.mmal_fmt\t    = MMAL_ENCODING_BAYER_SGBRG12P,\n+\t\t.size_multiplier_x2 = 2,\n+\t\t.colorspace\t    = V4L2_COLORSPACE_RAW,\n+\t\t.step_size\t    = 2,\n+\t}, {\n+\t\t/* 14 bit */\n+\t\t.fourcc\t\t    = V4L2_PIX_FMT_SRGGB14P,\n+\t\t.depth\t\t    = 14,\n+\t\t.bytesperline_align = 32,\n+\t\t.mmal_fmt\t    = MMAL_ENCODING_BAYER_SRGGB14P,\n+\t\t.size_multiplier_x2 = 2,\n+\t\t.colorspace\t    = V4L2_COLORSPACE_RAW,\n+\t\t.step_size\t    = 2,\n+\t}, {\n+\t\t.fourcc\t\t    = V4L2_PIX_FMT_SBGGR14P,\n+\t\t.depth\t\t    = 14,\n+\t\t.bytesperline_align = 32,\n+\t\t.mmal_fmt\t    = MMAL_ENCODING_BAYER_SBGGR14P,\n+\t\t.size_multiplier_x2 = 2,\n+\t\t.colorspace\t    = V4L2_COLORSPACE_RAW,\n+\t\t.step_size\t    = 2,\n+\t}, {\n+\t\t.fourcc\t\t    = V4L2_PIX_FMT_SGRBG14P,\n+\t\t.depth\t\t    = 14,\n+\t\t.bytesperline_align = 32,\n+\t\t.mmal_fmt\t    = MMAL_ENCODING_BAYER_SGRBG14P,\n+\t\t.size_multiplier_x2 = 2,\n+\t\t.colorspace\t    = V4L2_COLORSPACE_RAW,\n+\t\t.step_size\t    = 2,\n+\t}, {\n+\t\t.fourcc\t\t    = V4L2_PIX_FMT_SGBRG14P,\n+\t\t.depth\t\t    = 14,\n+\t\t.bytesperline_align = 32,\n+\t\t.mmal_fmt\t    = MMAL_ENCODING_BAYER_SGBRG14P,\n+\t\t.size_multiplier_x2 = 2,\n+\t\t.colorspace\t    = V4L2_COLORSPACE_RAW,\n+\t\t.step_size\t    = 2,\n+\t}, {\n+\t\t/* 16 bit */\n+\t\t.fourcc\t\t    = V4L2_PIX_FMT_SRGGB16,\n+\t\t.depth\t\t    = 16,\n+\t\t.bytesperline_align = 32,\n+\t\t.mmal_fmt\t    = MMAL_ENCODING_BAYER_SRGGB16,\n+\t\t.size_multiplier_x2 = 2,\n+\t\t.colorspace\t    = V4L2_COLORSPACE_RAW,\n+\t\t.step_size\t    = 2,\n+\t}, {\n+\t\t.fourcc\t\t    = V4L2_PIX_FMT_SBGGR16,\n+\t\t.depth\t\t    = 16,\n+\t\t.bytesperline_align = 32,\n+\t\t.mmal_fmt\t    = MMAL_ENCODING_BAYER_SBGGR16,\n+\t\t.size_multiplier_x2 = 2,\n+\t\t.colorspace\t    = V4L2_COLORSPACE_RAW,\n+\t\t.step_size\t    = 2,\n+\t}, {\n+\t\t.fourcc\t\t    = V4L2_PIX_FMT_SGRBG16,\n+\t\t.depth\t\t    = 16,\n+\t\t.bytesperline_align = 32,\n+\t\t.mmal_fmt\t    = MMAL_ENCODING_BAYER_SGRBG16,\n+\t\t.size_multiplier_x2 = 2,\n+\t\t.colorspace\t    = V4L2_COLORSPACE_RAW,\n+\t\t.step_size\t    = 2,\n+\t}, {\n+\t\t.fourcc\t\t    = V4L2_PIX_FMT_SGBRG16,\n+\t\t.depth\t\t    = 16,\n+\t\t.bytesperline_align = 32,\n+\t\t.mmal_fmt\t    = MMAL_ENCODING_BAYER_SGBRG16,\n+\t\t.size_multiplier_x2 = 2,\n+\t\t.colorspace\t    = V4L2_COLORSPACE_RAW,\n+\t\t.step_size\t    = 2,\n+\t}, {\n+\t\t/* Monochrome MIPI formats */\n+\t\t/* 8 bit */\n+\t\t.fourcc\t\t    = V4L2_PIX_FMT_GREY,\n+\t\t.depth\t\t    = 8,\n+\t\t.bytesperline_align = 32,\n+\t\t.mmal_fmt\t    = MMAL_ENCODING_GREY,\n+\t\t.size_multiplier_x2 = 2,\n+\t\t.colorspace\t    = V4L2_COLORSPACE_RAW,\n+\t\t.step_size\t    = 2,\n+\t}, {\n+\t\t/* 10 bit */\n+\t\t.fourcc\t\t    = V4L2_PIX_FMT_Y10P,\n+\t\t.depth\t\t    = 10,\n+\t\t.bytesperline_align = 32,\n+\t\t.mmal_fmt\t    = MMAL_ENCODING_Y10P,\n+\t\t.size_multiplier_x2 = 2,\n+\t\t.colorspace\t    = V4L2_COLORSPACE_RAW,\n+\t\t.step_size\t    = 2,\n+\t}, {\n+\t\t/* 12 bit */\n+\t\t.fourcc\t\t    = V4L2_PIX_FMT_Y12P,\n+\t\t.depth\t\t    = 12,\n+\t\t.bytesperline_align = 32,\n+\t\t.mmal_fmt\t    = MMAL_ENCODING_Y12P,\n+\t\t.size_multiplier_x2 = 2,\n+\t\t.colorspace\t    = V4L2_COLORSPACE_RAW,\n+\t\t.step_size\t    = 2,\n+\t}, {\n+\t\t/* 14 bit */\n+\t\t.fourcc\t\t    = V4L2_PIX_FMT_Y14P,\n+\t\t.depth\t\t    = 14,\n+\t\t.bytesperline_align = 32,\n+\t\t.mmal_fmt\t    = MMAL_ENCODING_Y14P,\n+\t\t.size_multiplier_x2 = 2,\n+\t\t.colorspace\t    = V4L2_COLORSPACE_RAW,\n+\t\t.step_size\t    = 2,\n+\t}, {\n+\t\t/* 16 bit */\n+\t\t.fourcc\t\t    = V4L2_PIX_FMT_Y16,\n+\t\t.depth\t\t    = 16,\n+\t\t.bytesperline_align = 32,\n+\t\t.mmal_fmt\t    = MMAL_ENCODING_Y16,\n+\t\t.size_multiplier_x2 = 2,\n+\t\t.colorspace\t    = V4L2_COLORSPACE_RAW,\n+\t\t.step_size\t    = 2,\n+\t}, {\n+\t\t.fourcc\t\t    = V4L2_META_FMT_BCM2835_ISP_STATS,\n+\t\t.mmal_fmt\t    = MMAL_ENCODING_BRCM_STATS,\n+\t\t/* The rest are not valid fields for stats. */\n+\t}\n+};\n+\n+#endif\n--- /dev/null\n+++ b/drivers/staging/vc04_services/bcm2835-isp/bcm2835-v4l2-isp.c\n@@ -0,0 +1,1694 @@\n+// SPDX-License-Identifier: GPL-2.0\n+/*\n+ * Broadcom BCM2835 ISP driver\n+ *\n+ * Copyright © 2019-2020 Raspberry Pi (Trading) Ltd.\n+ *\n+ * Author: Naushir Patuck (naush@raspberrypi.com)\n+ *\n+ */\n+\n+#include <linux/module.h>\n+#include <linux/platform_device.h>\n+\n+#include <media/v4l2-ctrls.h>\n+#include <media/v4l2-device.h>\n+#include <media/v4l2-event.h>\n+#include <media/v4l2-ioctl.h>\n+#include <media/videobuf2-dma-contig.h>\n+\n+#include \"vchiq-mmal/mmal-msg.h\"\n+#include \"vchiq-mmal/mmal-parameters.h\"\n+#include \"vchiq-mmal/mmal-vchiq.h\"\n+\n+#include \"vc-sm-cma/vc_sm_knl.h\"\n+\n+#include \"bcm2835-isp-ctrls.h\"\n+#include \"bcm2835-isp-fmts.h\"\n+\n+static unsigned int debug;\n+module_param(debug, uint, 0644);\n+MODULE_PARM_DESC(debug, \"activates debug info\");\n+\n+static unsigned int video_nr = 13;\n+module_param(video_nr, uint, 0644);\n+MODULE_PARM_DESC(video_nr, \"base video device number\");\n+\n+#define BCM2835_ISP_NAME \"bcm2835-isp\"\n+#define BCM2835_ISP_ENTITY_NAME_LEN 32\n+\n+#define BCM2835_ISP_NUM_OUTPUTS 1\n+#define BCM2835_ISP_NUM_CAPTURES 2\n+#define BCM2835_ISP_NUM_METADATA 1\n+\n+#define BCM2835_ISP_NUM_NODES\t\t\t\t\t\t\\\n+\t\t(BCM2835_ISP_NUM_OUTPUTS + BCM2835_ISP_NUM_CAPTURES +\t\\\n+\t\t BCM2835_ISP_NUM_METADATA)\n+\n+/* Default frame dimension of 1280 pixels. */\n+#define DEFAULT_DIM 1280U\n+/*\n+ * Maximum frame dimension of 16384 pixels.  Even though the ISP runs in tiles,\n+ * have a sensible limit so that we do not create an excessive number of tiles\n+ * to process.\n+ */\n+#define MAX_DIM 16384U\n+/*\n+ * Minimum frame dimension of 64 pixels.  Anything lower, and the tiling\n+ * algorithm may not be able to cope when applying filter context.\n+ */\n+#define MIN_DIM 64U\n+\n+/* Timeout for stop_streaming to allow all buffers to return */\n+#define COMPLETE_TIMEOUT (2 * HZ)\n+\n+/* Per-queue, driver-specific private data */\n+struct bcm2835_isp_q_data {\n+\t/*\n+\t * These parameters should be treated as gospel, with everything else\n+\t * being determined from them.\n+\t */\n+\tunsigned int bytesperline;\n+\tunsigned int width;\n+\tunsigned int height;\n+\tunsigned int sizeimage;\n+\tconst struct bcm2835_isp_fmt *fmt;\n+};\n+\n+/*\n+ * Structure to describe a single node /dev/video<N> which represents a single\n+ * input or output queue to the ISP device.\n+ */\n+struct bcm2835_isp_node {\n+\tint vfl_dir;\n+\tunsigned int id;\n+\tconst char *name;\n+\tstruct vchiq_mmal_port *port;\n+\tstruct video_device vfd;\n+\tstruct media_pad pad;\n+\tstruct media_intf_devnode *intf_devnode;\n+\tstruct media_link *intf_link;\n+\tstruct mutex lock; /* top level device node lock */\n+\tstruct mutex queue_lock;\n+\n+\tstruct vb2_queue queue;\n+\tunsigned int sequence;\n+\n+\t/* The list of formats supported on the node. */\n+\tstruct bcm2835_isp_fmt const **supported_fmts;\n+\tunsigned int num_supported_fmts;\n+\n+\tstruct bcm2835_isp_q_data q_data;\n+\n+\t/* Parent device structure */\n+\tstruct bcm2835_isp_dev *dev;\n+\n+\tbool registered;\n+\tbool media_node_registered;\n+};\n+\n+/*\n+ * Structure representing the entire ISP device, comprising several input and\n+ * output nodes /dev/video<N>.\n+ */\n+struct bcm2835_isp_dev {\n+\tstruct v4l2_device v4l2_dev;\n+\tstruct device *dev;\n+\tstruct v4l2_ctrl_handler ctrl_handler;\n+\tstruct media_device mdev;\n+\tstruct media_entity entity;\n+\tbool media_device_registered;\n+\tbool media_entity_registered;\n+\tstruct vchiq_mmal_instance *mmal_instance;\n+\tstruct vchiq_mmal_component *component;\n+\tstruct completion frame_cmplt;\n+\n+\tstruct bcm2835_isp_node node[BCM2835_ISP_NUM_NODES];\n+\tstruct media_pad pad[BCM2835_ISP_NUM_NODES];\n+\tatomic_t num_streaming;\n+\n+\t/* Image pipeline controls. */\n+\tint r_gain;\n+\tint b_gain;\n+};\n+\n+struct bcm2835_isp_buffer {\n+\tstruct vb2_v4l2_buffer vb;\n+\tstruct mmal_buffer mmal;\n+};\n+\n+static\n+inline struct bcm2835_isp_dev *node_get_dev(struct bcm2835_isp_node *node)\n+{\n+\treturn node->dev;\n+}\n+\n+static inline bool node_is_output(struct bcm2835_isp_node *node)\n+{\n+\treturn node->queue.type == V4L2_BUF_TYPE_VIDEO_OUTPUT;\n+}\n+\n+static inline bool node_is_capture(struct bcm2835_isp_node *node)\n+{\n+\treturn node->queue.type == V4L2_BUF_TYPE_VIDEO_CAPTURE;\n+}\n+\n+static inline bool node_is_stats(struct bcm2835_isp_node *node)\n+{\n+\treturn node->queue.type == V4L2_BUF_TYPE_META_CAPTURE;\n+}\n+\n+static inline enum v4l2_buf_type index_to_queue_type(int index)\n+{\n+\tif (index < BCM2835_ISP_NUM_OUTPUTS)\n+\t\treturn V4L2_BUF_TYPE_VIDEO_OUTPUT;\n+\telse if (index < BCM2835_ISP_NUM_OUTPUTS + BCM2835_ISP_NUM_CAPTURES)\n+\t\treturn V4L2_BUF_TYPE_VIDEO_CAPTURE;\n+\telse\n+\t\treturn V4L2_BUF_TYPE_META_CAPTURE;\n+}\n+\n+static int set_isp_param(struct bcm2835_isp_node *node, u32 parameter,\n+\t\t\t void *value, u32 value_size)\n+{\n+\tstruct bcm2835_isp_dev *dev = node_get_dev(node);\n+\n+\treturn vchiq_mmal_port_parameter_set(dev->mmal_instance, node->port,\n+\t\t\t\t\t     parameter, value, value_size);\n+}\n+\n+static int set_wb_gains(struct bcm2835_isp_node *node)\n+{\n+\tstruct bcm2835_isp_dev *dev = node_get_dev(node);\n+\tstruct mmal_parameter_awbgains gains = {\n+\t\t.r_gain = { dev->r_gain, 1000 },\n+\t\t.b_gain = { dev->b_gain, 1000 }\n+\t};\n+\n+\treturn set_isp_param(node, MMAL_PARAMETER_CUSTOM_AWB_GAINS,\n+\t\t\t     &gains, sizeof(gains));\n+}\n+\n+static int set_digital_gain(struct bcm2835_isp_node *node, uint32_t gain)\n+{\n+\tstruct mmal_parameter_rational digital_gain = {\n+\t\t.num = gain,\n+\t\t.den = 1000\n+\t};\n+\n+\treturn set_isp_param(node, MMAL_PARAMETER_DIGITAL_GAIN,\n+\t\t\t     &digital_gain, sizeof(digital_gain));\n+}\n+\n+static const struct bcm2835_isp_fmt *get_fmt(u32 mmal_fmt)\n+{\n+\tunsigned int i;\n+\n+\tfor (i = 0; i < ARRAY_SIZE(supported_formats); i++) {\n+\t\tif (supported_formats[i].mmal_fmt == mmal_fmt)\n+\t\t\treturn &supported_formats[i];\n+\t}\n+\treturn NULL;\n+}\n+\n+static const\n+struct bcm2835_isp_fmt *find_format_by_fourcc(unsigned int fourcc,\n+\t\t\t\t\t      struct bcm2835_isp_node *node)\n+{\n+\tconst struct bcm2835_isp_fmt *fmt;\n+\tunsigned int i;\n+\n+\tfor (i = 0; i < node->num_supported_fmts; i++) {\n+\t\tfmt = node->supported_fmts[i];\n+\t\tif (fmt->fourcc == fourcc)\n+\t\t\treturn fmt;\n+\t}\n+\n+\treturn NULL;\n+}\n+\n+static const\n+struct bcm2835_isp_fmt *find_format(struct v4l2_format *f,\n+\t\t\t\t    struct bcm2835_isp_node *node)\n+{\n+\treturn find_format_by_fourcc(node_is_stats(node) ?\n+\t\t\t\t     f->fmt.meta.dataformat :\n+\t\t\t\t     f->fmt.pix.pixelformat,\n+\t\t\t\t     node);\n+}\n+\n+/* vb2_to_mmal_buffer() - converts vb2 buffer header to MMAL\n+ *\n+ * Copies all the required fields from a VB2 buffer to the MMAL buffer header,\n+ * ready for sending to the VPU.\n+ */\n+static void vb2_to_mmal_buffer(struct mmal_buffer *buf,\n+\t\t\t       struct vb2_v4l2_buffer *vb2)\n+{\n+\tu64 pts;\n+\n+\tbuf->mmal_flags = 0;\n+\tif (vb2->flags & V4L2_BUF_FLAG_KEYFRAME)\n+\t\tbuf->mmal_flags |= MMAL_BUFFER_HEADER_FLAG_KEYFRAME;\n+\n+\t/* Data must be framed correctly as one frame per buffer. */\n+\tbuf->mmal_flags |= MMAL_BUFFER_HEADER_FLAG_FRAME_END;\n+\n+\tbuf->length = vb2->vb2_buf.planes[0].bytesused;\n+\t/*\n+\t * Minor ambiguity in the V4L2 spec as to whether passing in a 0 length\n+\t * buffer, or one with V4L2_BUF_FLAG_LAST set denotes end of stream.\n+\t * Handle either.\n+\t */\n+\tif (!buf->length || vb2->flags & V4L2_BUF_FLAG_LAST)\n+\t\tbuf->mmal_flags |= MMAL_BUFFER_HEADER_FLAG_EOS;\n+\n+\t/* vb2 timestamps in nsecs, mmal in usecs */\n+\tpts = vb2->vb2_buf.timestamp;\n+\tdo_div(pts, 1000);\n+\tbuf->pts = pts;\n+\tbuf->dts = MMAL_TIME_UNKNOWN;\n+}\n+\n+static void mmal_buffer_cb(struct vchiq_mmal_instance *instance,\n+\t\t\t   struct vchiq_mmal_port *port, int status,\n+\t\t\t   struct mmal_buffer *mmal_buf)\n+{\n+\tstruct bcm2835_isp_buffer *q_buf;\n+\tstruct bcm2835_isp_node *node = port->cb_ctx;\n+\tstruct bcm2835_isp_dev *dev = node_get_dev(node);\n+\tstruct vb2_v4l2_buffer *vb2;\n+\n+\tq_buf = container_of(mmal_buf, struct bcm2835_isp_buffer, mmal);\n+\tvb2 = &q_buf->vb;\n+\tv4l2_dbg(2, debug, &dev->v4l2_dev,\n+\t\t \"%s: port:%s[%d], status:%d, buf:%p, dmabuf:%p, length:%lu, flags %u, pts %lld\\n\",\n+\t\t __func__, node_is_output(node) ? \"input\" : \"output\", node->id,\n+\t\t status, mmal_buf, mmal_buf->dma_buf, mmal_buf->length,\n+\t\t mmal_buf->mmal_flags, mmal_buf->pts);\n+\n+\tif (mmal_buf->cmd)\n+\t\tv4l2_err(&dev->v4l2_dev,\n+\t\t\t \"%s: Unexpected event on output callback - %08x\\n\",\n+\t\t\t __func__, mmal_buf->cmd);\n+\n+\tif (status) {\n+\t\t/* error in transfer */\n+\t\tif (vb2) {\n+\t\t\t/* there was a buffer with the error so return it */\n+\t\t\tvb2_buffer_done(&vb2->vb2_buf, VB2_BUF_STATE_ERROR);\n+\t\t}\n+\t\treturn;\n+\t}\n+\n+\t/* vb2 timestamps in nsecs, mmal in usecs */\n+\tvb2->vb2_buf.timestamp = mmal_buf->pts * 1000;\n+\tvb2->sequence = node->sequence++;\n+\tvb2_set_plane_payload(&vb2->vb2_buf, 0, mmal_buf->length);\n+\tvb2_buffer_done(&vb2->vb2_buf, VB2_BUF_STATE_DONE);\n+\n+\tif (!port->enabled)\n+\t\tcomplete(&dev->frame_cmplt);\n+}\n+\n+static void setup_mmal_port_format(struct bcm2835_isp_node *node,\n+\t\t\t\t   struct vchiq_mmal_port *port)\n+{\n+\tstruct bcm2835_isp_q_data *q_data = &node->q_data;\n+\n+\tport->format.encoding = q_data->fmt->mmal_fmt;\n+\t/* Raw image format - set width/height */\n+\tport->es.video.width = (q_data->bytesperline << 3) / q_data->fmt->depth;\n+\tport->es.video.height = q_data->height;\n+\tport->es.video.crop.width = q_data->width;\n+\tport->es.video.crop.height = q_data->height;\n+\tport->es.video.crop.x = 0;\n+\tport->es.video.crop.y = 0;\n+};\n+\n+static int setup_mmal_port(struct bcm2835_isp_node *node)\n+{\n+\tstruct bcm2835_isp_dev *dev = node_get_dev(node);\n+\tunsigned int enable = 1;\n+\tint ret;\n+\n+\tv4l2_dbg(2, debug, &dev->v4l2_dev, \"%s: setup %s[%d]\\n\", __func__,\n+\t\t node->name, node->id);\n+\n+\tvchiq_mmal_port_parameter_set(dev->mmal_instance, node->port,\n+\t\t\t\t      MMAL_PARAMETER_ZERO_COPY, &enable,\n+\t\t\t\t      sizeof(enable));\n+\tsetup_mmal_port_format(node, node->port);\n+\tret = vchiq_mmal_port_set_format(dev->mmal_instance, node->port);\n+\tif (ret < 0) {\n+\t\tv4l2_dbg(1, debug, &dev->v4l2_dev,\n+\t\t\t \"%s: vchiq_mmal_port_set_format failed\\n\",\n+\t\t\t __func__);\n+\t\treturn ret;\n+\t}\n+\n+\tif (node->q_data.sizeimage < node->port->minimum_buffer.size) {\n+\t\tv4l2_err(&dev->v4l2_dev,\n+\t\t\t \"buffer size mismatch sizeimage %u < min size %u\\n\",\n+\t\t\t node->q_data.sizeimage,\n+\t\t\t node->port->minimum_buffer.size);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int bcm2835_isp_mmal_buf_cleanup(struct mmal_buffer *mmal_buf)\n+{\n+\tmmal_vchi_buffer_cleanup(mmal_buf);\n+\n+\tif (mmal_buf->dma_buf) {\n+\t\tdma_buf_put(mmal_buf->dma_buf);\n+\t\tmmal_buf->dma_buf = NULL;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int bcm2835_isp_node_queue_setup(struct vb2_queue *q,\n+\t\t\t\t\tunsigned int *nbuffers,\n+\t\t\t\t\tunsigned int *nplanes,\n+\t\t\t\t\tunsigned int sizes[],\n+\t\t\t\t\tstruct device *alloc_devs[])\n+{\n+\tstruct bcm2835_isp_node *node = vb2_get_drv_priv(q);\n+\tunsigned int size;\n+\n+\tif (setup_mmal_port(node))\n+\t\treturn -EINVAL;\n+\n+\tsize = node->q_data.sizeimage;\n+\tif (size == 0) {\n+\t\tv4l2_info(&node_get_dev(node)->v4l2_dev,\n+\t\t\t  \"%s: Image size unset in queue_setup for node %s[%d]\\n\",\n+\t\t\t  __func__, node->name, node->id);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (*nplanes)\n+\t\treturn sizes[0] < size ? -EINVAL : 0;\n+\n+\t*nplanes = 1;\n+\tsizes[0] = size;\n+\n+\tnode->port->current_buffer.size = size;\n+\n+\tif (*nbuffers < node->port->minimum_buffer.num)\n+\t\t*nbuffers = node->port->minimum_buffer.num;\n+\n+\tnode->port->current_buffer.num = *nbuffers;\n+\n+\tv4l2_dbg(2, debug, &node_get_dev(node)->v4l2_dev,\n+\t\t \"%s: Image size %u, nbuffers %u for node %s[%d]\\n\",\n+\t\t __func__, sizes[0], *nbuffers, node->name, node->id);\n+\treturn 0;\n+}\n+\n+static int bcm2835_isp_buf_init(struct vb2_buffer *vb)\n+{\n+\tstruct bcm2835_isp_node *node = vb2_get_drv_priv(vb->vb2_queue);\n+\tstruct bcm2835_isp_dev *dev = node_get_dev(node);\n+\tstruct vb2_v4l2_buffer *vb2 = to_vb2_v4l2_buffer(vb);\n+\tstruct bcm2835_isp_buffer *buf =\n+\t\tcontainer_of(vb2, struct bcm2835_isp_buffer, vb);\n+\n+\tv4l2_dbg(3, debug, &dev->v4l2_dev, \"%s: vb %p\\n\", __func__, vb);\n+\n+\tbuf->mmal.buffer = vb2_plane_vaddr(&buf->vb.vb2_buf, 0);\n+\tbuf->mmal.buffer_size = vb2_plane_size(&buf->vb.vb2_buf, 0);\n+\tmmal_vchi_buffer_init(dev->mmal_instance, &buf->mmal);\n+\treturn 0;\n+}\n+\n+static int bcm2835_isp_buf_prepare(struct vb2_buffer *vb)\n+{\n+\tstruct bcm2835_isp_node *node = vb2_get_drv_priv(vb->vb2_queue);\n+\tstruct bcm2835_isp_dev *dev = node_get_dev(node);\n+\tstruct vb2_v4l2_buffer *vb2 = to_vb2_v4l2_buffer(vb);\n+\tstruct bcm2835_isp_buffer *buf =\n+\t\tcontainer_of(vb2, struct bcm2835_isp_buffer, vb);\n+\tstruct dma_buf *dma_buf;\n+\tint ret;\n+\n+\tv4l2_dbg(3, debug, &dev->v4l2_dev, \"%s: type: %d ptr %p\\n\",\n+\t\t __func__, vb->vb2_queue->type, vb);\n+\n+\tif (V4L2_TYPE_IS_OUTPUT(vb->vb2_queue->type)) {\n+\t\tif (vb2->field == V4L2_FIELD_ANY)\n+\t\t\tvb2->field = V4L2_FIELD_NONE;\n+\t\tif (vb2->field != V4L2_FIELD_NONE) {\n+\t\t\tv4l2_err(&dev->v4l2_dev,\n+\t\t\t\t \"%s field isn't supported\\n\", __func__);\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t}\n+\n+\tif (vb2_plane_size(vb, 0) < node->q_data.sizeimage) {\n+\t\tv4l2_err(&dev->v4l2_dev,\n+\t\t\t \"%s data will not fit into plane (%lu < %lu)\\n\",\n+\t\t\t __func__, vb2_plane_size(vb, 0),\n+\t\t\t (long)node->q_data.sizeimage);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (!V4L2_TYPE_IS_OUTPUT(vb->vb2_queue->type))\n+\t\tvb2_set_plane_payload(vb, 0, node->q_data.sizeimage);\n+\n+\tswitch (vb->memory) {\n+\tcase VB2_MEMORY_DMABUF:\n+\t\tdma_buf = dma_buf_get(vb->planes[0].m.fd);\n+\n+\t\tif (dma_buf != buf->mmal.dma_buf) {\n+\t\t\t/*\n+\t\t\t * dmabuf either hasn't already been mapped, or it has\n+\t\t\t * changed.\n+\t\t\t */\n+\t\t\tif (buf->mmal.dma_buf) {\n+\t\t\t\tv4l2_err(&dev->v4l2_dev,\n+\t\t\t\t\t \"%s Buffer changed - why did the core not call cleanup?\\n\",\n+\t\t\t\t\t __func__);\n+\t\t\t\tbcm2835_isp_mmal_buf_cleanup(&buf->mmal);\n+\t\t\t}\n+\n+\t\t\tbuf->mmal.dma_buf = dma_buf;\n+\t\t} else {\n+\t\t\t/*\n+\t\t\t * Already have a reference to the buffer, so release it\n+\t\t\t * here.\n+\t\t\t */\n+\t\t\tdma_buf_put(dma_buf);\n+\t\t}\n+\t\tret = 0;\n+\t\tbreak;\n+\tcase VB2_MEMORY_MMAP:\n+\t\t/*\n+\t\t * We want to do this at init, but vb2_core_expbuf checks that\n+\t\t * the index < q->num_buffers, and q->num_buffers only gets\n+\t\t * updated once all the buffers are allocated.\n+\t\t */\n+\t\tif (!buf->mmal.dma_buf) {\n+\t\t\tret = vb2_core_expbuf_dmabuf(vb->vb2_queue,\n+\t\t\t\t\t\t     vb->vb2_queue->type,\n+\t\t\t\t\t\t     vb->index, 0, O_CLOEXEC,\n+\t\t\t\t\t\t     &buf->mmal.dma_buf);\n+\t\t\tv4l2_dbg(3, debug, &dev->v4l2_dev,\n+\t\t\t\t \"%s: exporting ptr %p to dmabuf %p\\n\",\n+\t\t\t\t __func__, vb, buf->mmal.dma_buf);\n+\t\t\tif (ret)\n+\t\t\t\tv4l2_err(&dev->v4l2_dev,\n+\t\t\t\t\t \"%s: Failed to expbuf idx %d, ret %d\\n\",\n+\t\t\t\t\t __func__, vb->index, ret);\n+\t\t} else {\n+\t\t\tret = 0;\n+\t\t}\n+\t\tbreak;\n+\tdefault:\n+\t\tret = -EINVAL;\n+\t\tbreak;\n+\t}\n+\n+\treturn ret;\n+}\n+\n+static void bcm2835_isp_node_buffer_queue(struct vb2_buffer *buf)\n+{\n+\tstruct bcm2835_isp_node *node = vb2_get_drv_priv(buf->vb2_queue);\n+\tstruct vb2_v4l2_buffer *vbuf =\n+\t\tcontainer_of(buf, struct vb2_v4l2_buffer, vb2_buf);\n+\tstruct bcm2835_isp_buffer *buffer =\n+\t\tcontainer_of(vbuf, struct bcm2835_isp_buffer, vb);\n+\tstruct bcm2835_isp_dev *dev = node_get_dev(node);\n+\n+\tv4l2_dbg(3, debug, &dev->v4l2_dev, \"%s: node %s[%d], buffer %p\\n\",\n+\t\t __func__, node->name, node->id, buffer);\n+\n+\tvb2_to_mmal_buffer(&buffer->mmal, &buffer->vb);\n+\tv4l2_dbg(3, debug, &dev->v4l2_dev,\n+\t\t \"%s: node %s[%d] - submitting  mmal dmabuf %p\\n\", __func__,\n+\t\t node->name, node->id, buffer->mmal.dma_buf);\n+\tvchiq_mmal_submit_buffer(dev->mmal_instance, node->port, &buffer->mmal);\n+}\n+\n+static void bcm2835_isp_buffer_cleanup(struct vb2_buffer *vb)\n+{\n+\tstruct vb2_v4l2_buffer *vb2 = to_vb2_v4l2_buffer(vb);\n+\tstruct bcm2835_isp_buffer *buffer =\n+\t\tcontainer_of(vb2, struct bcm2835_isp_buffer, vb);\n+\n+\tbcm2835_isp_mmal_buf_cleanup(&buffer->mmal);\n+}\n+\n+static int bcm2835_isp_node_start_streaming(struct vb2_queue *q,\n+\t\t\t\t\t    unsigned int count)\n+{\n+\tstruct bcm2835_isp_node *node = vb2_get_drv_priv(q);\n+\tstruct bcm2835_isp_dev *dev = node_get_dev(node);\n+\tint ret;\n+\n+\tv4l2_dbg(1, debug, &dev->v4l2_dev, \"%s: node %s[%d] (count %u)\\n\",\n+\t\t __func__, node->name, node->id, count);\n+\n+\tret = vchiq_mmal_component_enable(dev->mmal_instance, dev->component);\n+\tif (ret) {\n+\t\tv4l2_err(&dev->v4l2_dev, \"%s: Failed enabling component, ret %d\\n\",\n+\t\t\t __func__, ret);\n+\t\treturn -EIO;\n+\t}\n+\n+\tnode->sequence = 0;\n+\tnode->port->cb_ctx = node;\n+\tret = vchiq_mmal_port_enable(dev->mmal_instance, node->port,\n+\t\t\t\t     mmal_buffer_cb);\n+\tif (!ret)\n+\t\tatomic_inc(&dev->num_streaming);\n+\telse\n+\t\tv4l2_err(&dev->v4l2_dev,\n+\t\t\t \"%s: Failed enabling port, ret %d\\n\", __func__, ret);\n+\n+\treturn ret;\n+}\n+\n+static void bcm2835_isp_node_stop_streaming(struct vb2_queue *q)\n+{\n+\tstruct bcm2835_isp_node *node = vb2_get_drv_priv(q);\n+\tstruct bcm2835_isp_dev *dev = node_get_dev(node);\n+\tunsigned int i;\n+\tint ret;\n+\n+\tv4l2_dbg(1, debug, &dev->v4l2_dev, \"%s: node %s[%d], mmal port %p\\n\",\n+\t\t __func__, node->name, node->id, node->port);\n+\n+\tinit_completion(&dev->frame_cmplt);\n+\n+\t/* Disable MMAL port - this will flush buffers back */\n+\tret = vchiq_mmal_port_disable(dev->mmal_instance, node->port);\n+\tif (ret)\n+\t\tv4l2_err(&dev->v4l2_dev,\n+\t\t\t \"%s: Failed disabling %s port, ret %d\\n\", __func__,\n+\t\t\t node_is_output(node) ? \"i/p\" : \"o/p\",\n+\t\t\t ret);\n+\n+\twhile (atomic_read(&node->port->buffers_with_vpu)) {\n+\t\tv4l2_dbg(1, debug, &dev->v4l2_dev,\n+\t\t\t \"%s: Waiting for buffers to be returned - %d outstanding\\n\",\n+\t\t\t __func__, atomic_read(&node->port->buffers_with_vpu));\n+\t\tret = wait_for_completion_timeout(&dev->frame_cmplt,\n+\t\t\t\t\t\t  COMPLETE_TIMEOUT);\n+\t\tif (ret <= 0) {\n+\t\t\tv4l2_err(&dev->v4l2_dev,\n+\t\t\t\t \"%s: Timeout waiting for buffers to be returned - %d outstanding\\n\",\n+\t\t\t\t __func__,\n+\t\t\t\t atomic_read(&node->port->buffers_with_vpu));\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\n+\t/* Release the VCSM handle here to release the associated dmabuf */\n+\tfor (i = 0; i < q->num_buffers; i++) {\n+\t\tstruct vb2_v4l2_buffer *vb2 = to_vb2_v4l2_buffer(q->bufs[i]);\n+\t\tstruct bcm2835_isp_buffer *buf =\n+\t\t\tcontainer_of(vb2, struct bcm2835_isp_buffer, vb);\n+\t\tbcm2835_isp_mmal_buf_cleanup(&buf->mmal);\n+\t}\n+\n+\tatomic_dec(&dev->num_streaming);\n+\t/* If all ports disabled, then disable the component */\n+\tif (atomic_read(&dev->num_streaming) == 0) {\n+\t\tret = vchiq_mmal_component_disable(dev->mmal_instance,\n+\t\t\t\t\t\t   dev->component);\n+\t\tif (ret) {\n+\t\t\tv4l2_err(&dev->v4l2_dev,\n+\t\t\t\t \"%s: Failed disabling component, ret %d\\n\",\n+\t\t\t\t __func__, ret);\n+\t\t}\n+\t}\n+\n+\t/*\n+\t * Simply wait for any vb2 buffers to finish. We could take steps to\n+\t * make them complete more quickly if we care, or even return them\n+\t * ourselves.\n+\t */\n+\tvb2_wait_for_all_buffers(&node->queue);\n+}\n+\n+static const struct vb2_ops bcm2835_isp_node_queue_ops = {\n+\t.queue_setup\t\t= bcm2835_isp_node_queue_setup,\n+\t.buf_init\t\t= bcm2835_isp_buf_init,\n+\t.buf_prepare\t\t= bcm2835_isp_buf_prepare,\n+\t.buf_queue\t\t= bcm2835_isp_node_buffer_queue,\n+\t.buf_cleanup\t\t= bcm2835_isp_buffer_cleanup,\n+\t.start_streaming\t= bcm2835_isp_node_start_streaming,\n+\t.stop_streaming\t\t= bcm2835_isp_node_stop_streaming,\n+};\n+\n+static const\n+struct bcm2835_isp_fmt *get_default_format(struct bcm2835_isp_node *node)\n+{\n+\treturn node->supported_fmts[0];\n+}\n+\n+static inline unsigned int get_bytesperline(int width,\n+\t\t\t\t\t    const struct bcm2835_isp_fmt *fmt)\n+{\n+\t/* GPU aligns 24bpp images to a multiple of 32 pixels (not bytes). */\n+\tif (fmt->depth == 24)\n+\t\treturn ALIGN(width, 32) * 3;\n+\telse\n+\t\treturn ALIGN((width * fmt->depth) >> 3, fmt->bytesperline_align);\n+}\n+\n+static inline unsigned int get_sizeimage(int bpl, int width, int height,\n+\t\t\t\t\t const struct bcm2835_isp_fmt *fmt)\n+{\n+\treturn (bpl * height * fmt->size_multiplier_x2) >> 1;\n+}\n+\n+static int bcm2835_isp_s_ctrl(struct v4l2_ctrl *ctrl)\n+{\n+\tstruct bcm2835_isp_dev *dev =\n+\t      container_of(ctrl->handler, struct bcm2835_isp_dev, ctrl_handler);\n+\tstruct bcm2835_isp_node *node = &dev->node[0];\n+\tint ret = 0;\n+\n+\t/*\n+\t * The ISP firmware driver will ensure these settings are applied on\n+\t * a frame boundary, so we are safe to write them as they come in.\n+\t *\n+\t * Note that the bcm2835_isp_* param structures are identical to the\n+\t * mmal-parameters.h definitions.  This avoids the need for unnecessary\n+\t * field-by-field copying between structures.\n+\t */\n+\tswitch (ctrl->id) {\n+\tcase V4L2_CID_RED_BALANCE:\n+\t\tdev->r_gain = ctrl->val;\n+\t\tret = set_wb_gains(node);\n+\t\tbreak;\n+\tcase V4L2_CID_BLUE_BALANCE:\n+\t\tdev->b_gain = ctrl->val;\n+\t\tret = set_wb_gains(node);\n+\t\tbreak;\n+\tcase V4L2_CID_DIGITAL_GAIN:\n+\t\tret = set_digital_gain(node, ctrl->val);\n+\t\tbreak;\n+\tcase V4L2_CID_USER_BCM2835_ISP_CC_MATRIX:\n+\t\tret = set_isp_param(node, MMAL_PARAMETER_CUSTOM_CCM,\n+\t\t\t\t    ctrl->p_new.p_u8,\n+\t\t\t\t    sizeof(struct bcm2835_isp_custom_ccm));\n+\t\tbreak;\n+\tcase V4L2_CID_USER_BCM2835_ISP_LENS_SHADING:\n+\t{\n+\t\tstruct bcm2835_isp_lens_shading *v4l2_ls;\n+\t\tstruct mmal_parameter_lens_shading_v2 ls;\n+\t\tstruct dma_buf *dmabuf;\n+\t\tvoid *vcsm_handle;\n+\n+\t\tv4l2_ls = (struct bcm2835_isp_lens_shading *)ctrl->p_new.p_u8;\n+\t\t/*\n+\t\t * struct bcm2835_isp_lens_shading and struct\n+\t\t * mmal_parameter_lens_shading_v2 match so that we can do a\n+\t\t * simple memcpy here.\n+\t\t * Only the dmabuf to the actual table needs any manipulation.\n+\t\t */\n+\t\tmemcpy(&ls, v4l2_ls, sizeof(ls));\n+\n+\t\tdmabuf = dma_buf_get(v4l2_ls->dmabuf);\n+\t\tif (IS_ERR_OR_NULL(dmabuf))\n+\t\t\treturn -EINVAL;\n+\n+\t\tret = vc_sm_cma_import_dmabuf(dmabuf, &vcsm_handle);\n+\t\tif (ret) {\n+\t\t\tdma_buf_put(dmabuf);\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\n+\t\tls.mem_handle_table = vc_sm_cma_int_handle(vcsm_handle);\n+\t\tif (ls.mem_handle_table)\n+\t\t\t/* The VPU will take a reference on the vcsm handle,\n+\t\t\t * which in turn will retain a reference on the dmabuf.\n+\t\t\t * This code can therefore safely release all\n+\t\t\t * references to the buffer.\n+\t\t\t */\n+\t\t\tret = set_isp_param(node,\n+\t\t\t\t\t    MMAL_PARAMETER_LENS_SHADING_OVERRIDE,\n+\t\t\t\t\t    &ls,\n+\t\t\t\t\t    sizeof(ls));\n+\t\telse\n+\t\t\tret = -EINVAL;\n+\n+\t\tvc_sm_cma_free(vcsm_handle);\n+\t\tdma_buf_put(dmabuf);\n+\t\tbreak;\n+\t}\n+\tcase V4L2_CID_USER_BCM2835_ISP_BLACK_LEVEL:\n+\t\tret = set_isp_param(node, MMAL_PARAMETER_BLACK_LEVEL,\n+\t\t\t\t    ctrl->p_new.p_u8,\n+\t\t\t\t    sizeof(struct bcm2835_isp_black_level));\n+\t\tbreak;\n+\tcase V4L2_CID_USER_BCM2835_ISP_GEQ:\n+\t\tret = set_isp_param(node, MMAL_PARAMETER_GEQ,\n+\t\t\t\t    ctrl->p_new.p_u8,\n+\t\t\t\t    sizeof(struct bcm2835_isp_geq));\n+\t\tbreak;\n+\tcase V4L2_CID_USER_BCM2835_ISP_GAMMA:\n+\t\tret = set_isp_param(node, MMAL_PARAMETER_GAMMA,\n+\t\t\t\t    ctrl->p_new.p_u8,\n+\t\t\t\t    sizeof(struct bcm2835_isp_gamma));\n+\t\tbreak;\n+\tcase V4L2_CID_USER_BCM2835_ISP_DENOISE:\n+\t\tret = set_isp_param(node, MMAL_PARAMETER_DENOISE,\n+\t\t\t\t    ctrl->p_new.p_u8,\n+\t\t\t\t    sizeof(struct bcm2835_isp_denoise));\n+\t\tbreak;\n+\tcase V4L2_CID_USER_BCM2835_ISP_SHARPEN:\n+\t\tret = set_isp_param(node, MMAL_PARAMETER_SHARPEN,\n+\t\t\t\t    ctrl->p_new.p_u8,\n+\t\t\t\t    sizeof(struct bcm2835_isp_sharpen));\n+\t\tbreak;\n+\tcase V4L2_CID_USER_BCM2835_ISP_DPC:\n+\t\tret = set_isp_param(node, MMAL_PARAMETER_DPC,\n+\t\t\t\t    ctrl->p_new.p_u8,\n+\t\t\t\t    sizeof(struct bcm2835_isp_dpc));\n+\t\tbreak;\n+\tdefault:\n+\t\tv4l2_info(&dev->v4l2_dev, \"Unrecognised control\\n\");\n+\t\tret = -EINVAL;\n+\t}\n+\n+\tif (ret) {\n+\t\tv4l2_err(&dev->v4l2_dev, \"%s: Failed setting ctrl \\\"%s\\\" (%08x), err %d\\n\",\n+\t\t\t __func__, ctrl->name, ctrl->id, ret);\n+\t\tret = -EIO;\n+\t}\n+\n+\treturn ret;\n+}\n+\n+static const struct v4l2_ctrl_ops bcm2835_isp_ctrl_ops = {\n+\t.s_ctrl = bcm2835_isp_s_ctrl,\n+};\n+\n+static const struct v4l2_file_operations bcm2835_isp_fops = {\n+\t.owner\t\t= THIS_MODULE,\n+\t.open\t\t= v4l2_fh_open,\n+\t.release\t= vb2_fop_release,\n+\t.poll\t\t= vb2_fop_poll,\n+\t.unlocked_ioctl = video_ioctl2,\n+\t.mmap\t\t= vb2_fop_mmap\n+};\n+\n+static int populate_qdata_fmt(struct v4l2_format *f,\n+\t\t\t      struct bcm2835_isp_node *node)\n+{\n+\tstruct bcm2835_isp_dev *dev = node_get_dev(node);\n+\tstruct bcm2835_isp_q_data *q_data = &node->q_data;\n+\tint ret;\n+\n+\tif (!node_is_stats(node)) {\n+\t\tv4l2_dbg(1, debug, &dev->v4l2_dev,\n+\t\t\t \"%s: Setting pix format for type %d, wxh: %ux%u, fmt: %08x, size %u\\n\",\n+\t\t\t __func__, f->type, f->fmt.pix.width, f->fmt.pix.height,\n+\t\t\t f->fmt.pix.pixelformat, f->fmt.pix.sizeimage);\n+\n+\t\tq_data->fmt = find_format(f, node);\n+\t\tq_data->width = f->fmt.pix.width;\n+\t\tq_data->height = f->fmt.pix.height;\n+\t\tq_data->height = f->fmt.pix.height;\n+\n+\t\t/* All parameters should have been set correctly by try_fmt */\n+\t\tq_data->bytesperline = f->fmt.pix.bytesperline;\n+\t\tq_data->sizeimage = f->fmt.pix.sizeimage;\n+\t} else {\n+\t\tv4l2_dbg(1, debug, &dev->v4l2_dev,\n+\t\t\t \"%s: Setting meta format for fmt: %08x, size %u\\n\",\n+\t\t\t __func__, f->fmt.meta.dataformat,\n+\t\t\t f->fmt.meta.buffersize);\n+\n+\t\tq_data->fmt = find_format(f, node);\n+\t\tq_data->width = 0;\n+\t\tq_data->height = 0;\n+\t\tq_data->bytesperline = 0;\n+\t\tq_data->sizeimage = f->fmt.meta.buffersize;\n+\t}\n+\n+\tv4l2_dbg(1, debug, &dev->v4l2_dev,\n+\t\t \"%s: Calculated bpl as %u, size %u\\n\", __func__,\n+\t\t q_data->bytesperline, q_data->sizeimage);\n+\n+\tsetup_mmal_port_format(node, node->port);\n+\tret = vchiq_mmal_port_set_format(dev->mmal_instance, node->port);\n+\tif (ret) {\n+\t\tv4l2_err(&dev->v4l2_dev,\n+\t\t\t \"%s: Failed vchiq_mmal_port_set_format on port, ret %d\\n\",\n+\t\t\t __func__, ret);\n+\t\tret = -EINVAL;\n+\t}\n+\n+\tif (q_data->sizeimage < node->port->minimum_buffer.size) {\n+\t\tv4l2_err(&dev->v4l2_dev,\n+\t\t\t \"%s: Current buffer size of %u < min buf size %u - driver mismatch to MMAL\\n\",\n+\t\t\t __func__,\n+\t\t\t q_data->sizeimage,\n+\t\t\t node->port->minimum_buffer.size);\n+\t}\n+\n+\tv4l2_dbg(1, debug, &dev->v4l2_dev,\n+\t\t \"%s: Set format for type %d, wxh: %dx%d, fmt: %08x, size %u\\n\",\n+\t\t __func__, f->type, q_data->width, q_data->height,\n+\t\t q_data->fmt->fourcc, q_data->sizeimage);\n+\n+\treturn ret;\n+}\n+\n+static int bcm2835_isp_node_querycap(struct file *file, void *priv,\n+\t\t\t\t     struct v4l2_capability *cap)\n+{\n+\tstrscpy(cap->driver, BCM2835_ISP_NAME, sizeof(cap->driver));\n+\tstrscpy(cap->card, BCM2835_ISP_NAME, sizeof(cap->card));\n+\tsnprintf(cap->bus_info, sizeof(cap->bus_info), \"platform:%s\",\n+\t\t BCM2835_ISP_NAME);\n+\n+\treturn 0;\n+}\n+\n+static int bcm2835_isp_node_g_fmt(struct file *file, void *priv,\n+\t\t\t\t  struct v4l2_format *f)\n+{\n+\tstruct bcm2835_isp_node *node = video_drvdata(file);\n+\n+\tif (f->type != node->queue.type)\n+\t\treturn -EINVAL;\n+\n+\tif (node_is_stats(node)) {\n+\t\tf->fmt.meta.dataformat = V4L2_META_FMT_BCM2835_ISP_STATS;\n+\t\tf->fmt.meta.buffersize =\n+\t\t\tnode->port->minimum_buffer.size;\n+\t} else {\n+\t\tstruct bcm2835_isp_q_data *q_data = &node->q_data;\n+\n+\t\tf->fmt.pix.width = q_data->width;\n+\t\tf->fmt.pix.height = q_data->height;\n+\t\tf->fmt.pix.field = V4L2_FIELD_NONE;\n+\t\tf->fmt.pix.pixelformat = q_data->fmt->fourcc;\n+\t\tf->fmt.pix.bytesperline = q_data->bytesperline;\n+\t\tf->fmt.pix.sizeimage = q_data->sizeimage;\n+\t\tf->fmt.pix.colorspace = q_data->fmt->colorspace;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int bcm2835_isp_node_enum_fmt(struct file *file, void  *priv,\n+\t\t\t\t     struct v4l2_fmtdesc *f)\n+{\n+\tstruct bcm2835_isp_node *node = video_drvdata(file);\n+\n+\tif (f->type != node->queue.type)\n+\t\treturn -EINVAL;\n+\n+\tif (f->index < node->num_supported_fmts) {\n+\t\t/* Format found */\n+\t\tf->pixelformat = node->supported_fmts[f->index]->fourcc;\n+\t\tf->flags = 0;\n+\t\treturn 0;\n+\t}\n+\n+\treturn -EINVAL;\n+}\n+\n+static int bcm2835_isp_enum_framesizes(struct file *file, void *priv,\n+\t\t\t\t       struct v4l2_frmsizeenum *fsize)\n+{\n+\tstruct bcm2835_isp_node *node = video_drvdata(file);\n+\tstruct bcm2835_isp_dev *dev = node_get_dev(node);\n+\tconst struct bcm2835_isp_fmt *fmt;\n+\n+\tif (node_is_stats(node) || fsize->index)\n+\t\treturn -EINVAL;\n+\n+\tfmt = find_format_by_fourcc(fsize->pixel_format, node);\n+\tif (!fmt) {\n+\t\tv4l2_err(&dev->v4l2_dev, \"Invalid pixel code: %x\\n\",\n+\t\t\t fsize->pixel_format);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tfsize->type = V4L2_FRMSIZE_TYPE_STEPWISE;\n+\tfsize->stepwise.min_width = MIN_DIM;\n+\tfsize->stepwise.max_width = MAX_DIM;\n+\tfsize->stepwise.step_width = fmt->step_size;\n+\n+\tfsize->stepwise.min_height = MIN_DIM;\n+\tfsize->stepwise.max_height = MAX_DIM;\n+\tfsize->stepwise.step_height = fmt->step_size;\n+\n+\treturn 0;\n+}\n+\n+static int bcm2835_isp_node_try_fmt(struct file *file, void *priv,\n+\t\t\t\t    struct v4l2_format *f)\n+{\n+\tstruct bcm2835_isp_node *node = video_drvdata(file);\n+\tconst struct bcm2835_isp_fmt *fmt;\n+\n+\tif (f->type != node->queue.type)\n+\t\treturn -EINVAL;\n+\n+\tfmt = find_format(f, node);\n+\tif (!fmt)\n+\t\tfmt = get_default_format(node);\n+\n+\tif (!node_is_stats(node)) {\n+\t\tf->fmt.pix.width = max(min(f->fmt.pix.width, MAX_DIM),\n+\t\t\t\t       MIN_DIM);\n+\t\tf->fmt.pix.height = max(min(f->fmt.pix.height, MAX_DIM),\n+\t\t\t\t\tMIN_DIM);\n+\n+\t\tf->fmt.pix.pixelformat = fmt->fourcc;\n+\t\tf->fmt.pix.colorspace = fmt->colorspace;\n+\t\tf->fmt.pix.bytesperline = get_bytesperline(f->fmt.pix.width,\n+\t\t\t\t\t\t\t   fmt);\n+\t\tf->fmt.pix.field = V4L2_FIELD_NONE;\n+\t\tf->fmt.pix.sizeimage =\n+\t\t\tget_sizeimage(f->fmt.pix.bytesperline, f->fmt.pix.width,\n+\t\t\t\t      f->fmt.pix.height, fmt);\n+\t} else {\n+\t\tf->fmt.meta.dataformat = fmt->fourcc;\n+\t\tf->fmt.meta.buffersize = node->port->minimum_buffer.size;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int bcm2835_isp_node_s_fmt(struct file *file, void *priv,\n+\t\t\t\t  struct v4l2_format *f)\n+{\n+\tstruct bcm2835_isp_node *node = video_drvdata(file);\n+\tint ret;\n+\n+\tif (f->type != node->queue.type)\n+\t\treturn -EINVAL;\n+\n+\tret = bcm2835_isp_node_try_fmt(file, priv, f);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tv4l2_dbg(1, debug, &node_get_dev(node)->v4l2_dev,\n+\t\t \"%s: Set format for node %s[%d]\\n\",\n+\t\t __func__, node->name, node->id);\n+\n+\treturn populate_qdata_fmt(f, node);\n+}\n+\n+static int bcm2835_isp_node_s_selection(struct file *file, void *fh,\n+\t\t\t\t\tstruct v4l2_selection *s)\n+{\n+\tstruct mmal_parameter_crop crop;\n+\tstruct bcm2835_isp_node *node = video_drvdata(file);\n+\tstruct bcm2835_isp_dev *dev = node_get_dev(node);\n+\n+\t/* This return value is required fro V4L2 compliance. */\n+\tif (node_is_stats(node))\n+\t\treturn -ENOTTY;\n+\n+\tif (!s->r.width || !s->r.height)\n+\t\treturn -EINVAL;\n+\n+\t/* We can only set crop on the input. */\n+\tswitch (s->target) {\n+\tcase V4L2_SEL_TGT_CROP:\n+\t\t/*\n+\t\t * Adjust the crop window if it goes outside of the frame\n+\t\t * dimensions.\n+\t\t */\n+\t\ts->r.left = min((unsigned int)max(s->r.left, 0),\n+\t\t\t\tnode->q_data.width - MIN_DIM);\n+\t\ts->r.top = min((unsigned int)max(s->r.top, 0),\n+\t\t\t       node->q_data.height - MIN_DIM);\n+\t\ts->r.width = max(min(s->r.width,\n+\t\t\t\t     node->q_data.width - s->r.left), MIN_DIM);\n+\t\ts->r.height = max(min(s->r.height,\n+\t\t\t\t      node->q_data.height - s->r.top), MIN_DIM);\n+\t\tbreak;\n+\tcase V4L2_SEL_TGT_CROP_DEFAULT:\n+\t\t/* Default (i.e. no) crop window. */\n+\t\ts->r.left = 0;\n+\t\ts->r.top = 0;\n+\t\ts->r.width = node->q_data.width;\n+\t\ts->r.height = node->q_data.height;\n+\t\tbreak;\n+\tdefault:\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tcrop.rect.x = s->r.left;\n+\tcrop.rect.y = s->r.top;\n+\tcrop.rect.width = s->r.width;\n+\tcrop.rect.height = s->r.height;\n+\n+\treturn vchiq_mmal_port_parameter_set(dev->mmal_instance, node->port,\n+\t\t\t\t\t     MMAL_PARAMETER_CROP,\n+\t\t\t\t\t     &crop, sizeof(crop));\n+}\n+\n+static int bcm2835_isp_node_g_selection(struct file *file, void *fh,\n+\t\t\t\t\tstruct v4l2_selection *s)\n+{\n+\tstruct mmal_parameter_crop crop;\n+\tstruct bcm2835_isp_node *node = video_drvdata(file);\n+\tstruct bcm2835_isp_dev *dev = node_get_dev(node);\n+\tu32 crop_size = sizeof(crop);\n+\tint ret;\n+\n+\t/* We can only return out an input crop. */\n+\tswitch (s->target) {\n+\tcase V4L2_SEL_TGT_CROP:\n+\t\tret = vchiq_mmal_port_parameter_get(dev->mmal_instance,\n+\t\t\t\t\t\t    node->port,\n+\t\t\t\t\t\t    MMAL_PARAMETER_CROP,\n+\t\t\t\t\t\t    &crop, &crop_size);\n+\t\tif (!ret) {\n+\t\t\ts->r.left = crop.rect.x;\n+\t\t\ts->r.top = crop.rect.y;\n+\t\t\ts->r.width = crop.rect.width;\n+\t\t\ts->r.height = crop.rect.height;\n+\t\t}\n+\t\tbreak;\n+\tcase V4L2_SEL_TGT_CROP_DEFAULT:\n+\tcase V4L2_SEL_TGT_CROP_BOUNDS:\n+\t\t/* Default (i.e. no) crop window. */\n+\t\ts->r.left = 0;\n+\t\ts->r.top = 0;\n+\t\ts->r.width = node->q_data.width;\n+\t\ts->r.height = node->q_data.height;\n+\t\tret = 0;\n+\t\tbreak;\n+\tdefault:\n+\t\tret =  -EINVAL;\n+\t}\n+\n+\treturn ret;\n+}\n+\n+static int bcm3285_isp_subscribe_event(struct v4l2_fh *fh,\n+\t\t\t\t       const struct v4l2_event_subscription *s)\n+{\n+\tswitch (s->type) {\n+\t/* Cannot change source parameters dynamically at runtime. */\n+\tcase V4L2_EVENT_SOURCE_CHANGE:\n+\t\treturn -EINVAL;\n+\tcase V4L2_EVENT_CTRL:\n+\t\treturn v4l2_ctrl_subscribe_event(fh, s);\n+\tdefault:\n+\t\treturn v4l2_event_subscribe(fh, s, 4, NULL);\n+\t}\n+}\n+\n+static const struct v4l2_ioctl_ops bcm2835_isp_node_ioctl_ops = {\n+\t.vidioc_querycap\t\t= bcm2835_isp_node_querycap,\n+\t.vidioc_g_fmt_vid_cap\t\t= bcm2835_isp_node_g_fmt,\n+\t.vidioc_g_fmt_vid_out\t\t= bcm2835_isp_node_g_fmt,\n+\t.vidioc_g_fmt_meta_cap\t\t= bcm2835_isp_node_g_fmt,\n+\t.vidioc_s_fmt_vid_cap\t\t= bcm2835_isp_node_s_fmt,\n+\t.vidioc_s_fmt_vid_out\t\t= bcm2835_isp_node_s_fmt,\n+\t.vidioc_s_fmt_meta_cap\t\t= bcm2835_isp_node_s_fmt,\n+\t.vidioc_try_fmt_vid_cap\t\t= bcm2835_isp_node_try_fmt,\n+\t.vidioc_try_fmt_vid_out\t\t= bcm2835_isp_node_try_fmt,\n+\t.vidioc_try_fmt_meta_cap\t= bcm2835_isp_node_try_fmt,\n+\t.vidioc_s_selection\t\t= bcm2835_isp_node_s_selection,\n+\t.vidioc_g_selection\t\t= bcm2835_isp_node_g_selection,\n+\n+\t.vidioc_enum_fmt_vid_cap\t= bcm2835_isp_node_enum_fmt,\n+\t.vidioc_enum_fmt_vid_out\t= bcm2835_isp_node_enum_fmt,\n+\t.vidioc_enum_fmt_meta_cap\t= bcm2835_isp_node_enum_fmt,\n+\t.vidioc_enum_framesizes\t\t= bcm2835_isp_enum_framesizes,\n+\n+\t.vidioc_reqbufs\t\t\t= vb2_ioctl_reqbufs,\n+\t.vidioc_querybuf\t\t= vb2_ioctl_querybuf,\n+\t.vidioc_qbuf\t\t\t= vb2_ioctl_qbuf,\n+\t.vidioc_dqbuf\t\t\t= vb2_ioctl_dqbuf,\n+\t.vidioc_expbuf\t\t\t= vb2_ioctl_expbuf,\n+\t.vidioc_create_bufs\t\t= vb2_ioctl_create_bufs,\n+\t.vidioc_prepare_buf\t\t= vb2_ioctl_prepare_buf,\n+\n+\t.vidioc_streamon\t\t= vb2_ioctl_streamon,\n+\t.vidioc_streamoff\t\t= vb2_ioctl_streamoff,\n+\n+\t.vidioc_subscribe_event\t\t= bcm3285_isp_subscribe_event,\n+\t.vidioc_unsubscribe_event\t= v4l2_event_unsubscribe,\n+};\n+\n+/*\n+ * Size of the array to provide to the VPU when asking for the list of supported\n+ * formats.\n+ *\n+ * The ISP component currently advertises 44 input formats, so add a small\n+ * overhead on that. Should the component advertise more formats then the excess\n+ * will be dropped and a warning logged.\n+ */\n+#define MAX_SUPPORTED_ENCODINGS 50\n+\n+/* Populate node->supported_fmts with the formats supported by those ports. */\n+static int bcm2835_isp_get_supported_fmts(struct bcm2835_isp_node *node)\n+{\n+\tstruct bcm2835_isp_dev *dev = node_get_dev(node);\n+\tstruct bcm2835_isp_fmt const **list;\n+\tunsigned int i, j, num_encodings;\n+\tu32 fourccs[MAX_SUPPORTED_ENCODINGS];\n+\tu32 param_size = sizeof(fourccs);\n+\tint ret;\n+\n+\tret = vchiq_mmal_port_parameter_get(dev->mmal_instance, node->port,\n+\t\t\t\t\t    MMAL_PARAMETER_SUPPORTED_ENCODINGS,\n+\t\t\t\t\t    &fourccs, &param_size);\n+\n+\tif (ret) {\n+\t\tif (ret == MMAL_MSG_STATUS_ENOSPC) {\n+\t\t\tv4l2_err(&dev->v4l2_dev,\n+\t\t\t\t \"%s: port has more encoding than we provided space for. Some are dropped.\\n\",\n+\t\t\t\t __func__);\n+\t\t\tnum_encodings = MAX_SUPPORTED_ENCODINGS;\n+\t\t} else {\n+\t\t\tv4l2_err(&dev->v4l2_dev, \"%s: get_param ret %u.\\n\",\n+\t\t\t\t __func__, ret);\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t} else {\n+\t\tnum_encodings = param_size / sizeof(u32);\n+\t}\n+\n+\t/*\n+\t * Assume at this stage that all encodings will be supported in V4L2.\n+\t * Any that aren't supported will waste a very small amount of memory.\n+\t */\n+\tlist = devm_kzalloc(dev->dev,\n+\t\t\t    sizeof(struct bcm2835_isp_fmt *) * num_encodings,\n+\t\t\t    GFP_KERNEL);\n+\tif (!list)\n+\t\treturn -ENOMEM;\n+\tnode->supported_fmts = list;\n+\n+\tfor (i = 0, j = 0; i < num_encodings; i++) {\n+\t\tconst struct bcm2835_isp_fmt *fmt = get_fmt(fourccs[i]);\n+\n+\t\tif (fmt) {\n+\t\t\tlist[j] = fmt;\n+\t\t\tj++;\n+\t\t}\n+\t}\n+\tnode->num_supported_fmts = j;\n+\n+\treturn 0;\n+}\n+\n+/*\n+ * Register a device node /dev/video<N> to go along with one of the ISP's input\n+ * or output nodes.\n+ */\n+static int register_node(struct bcm2835_isp_dev *dev,\n+\t\t\t struct bcm2835_isp_node *node,\n+\t\t\t int index)\n+{\n+\tstruct video_device *vfd;\n+\tstruct vb2_queue *queue;\n+\tint ret;\n+\n+\tmutex_init(&node->lock);\n+\n+\tnode->dev = dev;\n+\tvfd = &node->vfd;\n+\tqueue = &node->queue;\n+\tqueue->type = index_to_queue_type(index);\n+\t/*\n+\t * Setup the node type-specific params.\n+\t *\n+\t * Only the OUTPUT node can set controls and crop windows. However,\n+\t * we must allow the s/g_selection ioctl on the stats node as v4l2\n+\t * compliance expects it to return a -ENOTTY, and the framework\n+\t * does not handle it if the ioctl is disabled.\n+\t */\n+\tswitch (queue->type) {\n+\tcase V4L2_BUF_TYPE_VIDEO_OUTPUT:\n+\t\tvfd->device_caps = V4L2_CAP_VIDEO_OUTPUT | V4L2_CAP_STREAMING;\n+\t\tnode->id = index;\n+\t\tnode->vfl_dir = VFL_DIR_TX;\n+\t\tnode->name = \"output\";\n+\t\tnode->port = &dev->component->input[node->id];\n+\t\tbreak;\n+\tcase V4L2_BUF_TYPE_VIDEO_CAPTURE:\n+\t\tvfd->device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING;\n+\t\t/* First Capture node starts at id 0, etc. */\n+\t\tnode->id = index - BCM2835_ISP_NUM_OUTPUTS;\n+\t\tnode->vfl_dir = VFL_DIR_RX;\n+\t\tnode->name = \"capture\";\n+\t\tnode->port = &dev->component->output[node->id];\n+\t\tv4l2_disable_ioctl(&node->vfd, VIDIOC_S_CTRL);\n+\t\tv4l2_disable_ioctl(&node->vfd, VIDIOC_S_SELECTION);\n+\t\tv4l2_disable_ioctl(&node->vfd, VIDIOC_G_SELECTION);\n+\t\tbreak;\n+\tcase V4L2_BUF_TYPE_META_CAPTURE:\n+\t\tvfd->device_caps = V4L2_CAP_META_CAPTURE | V4L2_CAP_STREAMING;\n+\t\tnode->id = index - BCM2835_ISP_NUM_OUTPUTS;\n+\t\tnode->vfl_dir = VFL_DIR_RX;\n+\t\tnode->name = \"stats\";\n+\t\tnode->port = &dev->component->output[node->id];\n+\t\tv4l2_disable_ioctl(&node->vfd, VIDIOC_S_CTRL);\n+\t\tv4l2_disable_ioctl(&node->vfd, VIDIOC_S_SELECTION);\n+\t\tv4l2_disable_ioctl(&node->vfd, VIDIOC_G_SELECTION);\n+\t\tbreak;\n+\t}\n+\n+\t/* We use the selection API instead of the old crop API. */\n+\tv4l2_disable_ioctl(vfd, VIDIOC_CROPCAP);\n+\tv4l2_disable_ioctl(vfd, VIDIOC_G_CROP);\n+\tv4l2_disable_ioctl(vfd, VIDIOC_S_CROP);\n+\n+\tret = bcm2835_isp_get_supported_fmts(node);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\t/* Initialise the video node. */\n+\tvfd->vfl_type\t= VFL_TYPE_VIDEO;\n+\tvfd->fops\t= &bcm2835_isp_fops,\n+\tvfd->ioctl_ops\t= &bcm2835_isp_node_ioctl_ops,\n+\tvfd->minor\t= -1,\n+\tvfd->release\t= video_device_release_empty,\n+\tvfd->queue\t= &node->queue;\n+\tvfd->lock\t= &node->lock;\n+\tvfd->v4l2_dev\t= &dev->v4l2_dev;\n+\tvfd->vfl_dir\t= node->vfl_dir;\n+\n+\tnode->q_data.fmt = get_default_format(node);\n+\tnode->q_data.width = DEFAULT_DIM;\n+\tnode->q_data.height = DEFAULT_DIM;\n+\tnode->q_data.bytesperline =\n+\t\tget_bytesperline(DEFAULT_DIM, node->q_data.fmt);\n+\tnode->q_data.sizeimage = node_is_stats(node) ?\n+\t\t\t\t node->port->recommended_buffer.size :\n+\t\t\t\t get_sizeimage(node->q_data.bytesperline,\n+\t\t\t\t\t       node->q_data.width,\n+\t\t\t\t\t       node->q_data.height,\n+\t\t\t\t\t       node->q_data.fmt);\n+\n+\tqueue->io_modes = VB2_MMAP | VB2_DMABUF;\n+\tqueue->drv_priv = node;\n+\tqueue->ops = &bcm2835_isp_node_queue_ops;\n+\tqueue->mem_ops = &vb2_dma_contig_memops;\n+\tqueue->buf_struct_size = sizeof(struct bcm2835_isp_buffer);\n+\tqueue->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;\n+\tqueue->dev = dev->dev;\n+\tqueue->lock = &node->queue_lock;\n+\n+\tret = vb2_queue_init(queue);\n+\tif (ret < 0) {\n+\t\tv4l2_info(&dev->v4l2_dev, \"vb2_queue_init failed\\n\");\n+\t\treturn ret;\n+\t}\n+\n+\t/* Set some controls and defaults, but only on the VIDEO_OUTPUT node. */\n+\tif (node_is_output(node)) {\n+\t\tunsigned int i;\n+\n+\t\t/* Use this ctrl template to assign custom ISP ctrls. */\n+\t\tstruct v4l2_ctrl_config ctrl_template = {\n+\t\t\t.ops\t\t= &bcm2835_isp_ctrl_ops,\n+\t\t\t.type\t\t= V4L2_CTRL_TYPE_U8,\n+\t\t\t.def\t\t= 0,\n+\t\t\t.min\t\t= 0x00,\n+\t\t\t.max\t\t= 0xff,\n+\t\t\t.step\t\t= 1,\n+\t\t};\n+\n+\t\t/* 3 standard controls, and an array of custom controls */\n+\t\tret = v4l2_ctrl_handler_init(&dev->ctrl_handler,\n+\t\t\t\t\t     3 + ARRAY_SIZE(custom_ctrls));\n+\t\tif (ret) {\n+\t\t\tv4l2_err(&dev->v4l2_dev, \"ctrl_handler init failed (%d)\\n\",\n+\t\t\t\t ret);\n+\t\t\tgoto queue_cleanup;\n+\t\t}\n+\n+\t\tdev->r_gain = 1000;\n+\t\tdev->b_gain = 1000;\n+\n+\t\tv4l2_ctrl_new_std(&dev->ctrl_handler,  &bcm2835_isp_ctrl_ops,\n+\t\t\t\t  V4L2_CID_RED_BALANCE, 1, 0xffff, 1,\n+\t\t\t\t  dev->r_gain);\n+\n+\t\tv4l2_ctrl_new_std(&dev->ctrl_handler, &bcm2835_isp_ctrl_ops,\n+\t\t\t\t  V4L2_CID_BLUE_BALANCE, 1, 0xffff, 1,\n+\t\t\t\t  dev->b_gain);\n+\n+\t\tv4l2_ctrl_new_std(&dev->ctrl_handler, &bcm2835_isp_ctrl_ops,\n+\t\t\t\t  V4L2_CID_DIGITAL_GAIN, 1, 0xffff, 1, 1000);\n+\n+\t\tfor (i = 0; i < ARRAY_SIZE(custom_ctrls); i++) {\n+\t\t\tctrl_template.name = custom_ctrls[i].name;\n+\t\t\tctrl_template.id = custom_ctrls[i].id;\n+\t\t\tctrl_template.dims[0] = custom_ctrls[i].size;\n+\t\t\tctrl_template.flags = custom_ctrls[i].flags;\n+\t\t\tv4l2_ctrl_new_custom(&dev->ctrl_handler,\n+\t\t\t\t\t     &ctrl_template, NULL);\n+\t\t}\n+\n+\t\tnode->vfd.ctrl_handler = &dev->ctrl_handler;\n+\t\tif (dev->ctrl_handler.error) {\n+\t\t\tret = dev->ctrl_handler.error;\n+\t\t\tv4l2_err(&dev->v4l2_dev, \"controls init failed (%d)\\n\",\n+\t\t\t\t ret);\n+\t\t\tv4l2_ctrl_handler_free(&dev->ctrl_handler);\n+\t\t\tgoto ctrl_cleanup;\n+\t\t}\n+\t}\n+\n+\t/* Define the device names */\n+\tsnprintf(vfd->name, sizeof(node->vfd.name), \"%s-%s%d\", BCM2835_ISP_NAME,\n+\t\t node->name, node->id);\n+\n+\tret = video_register_device(vfd, VFL_TYPE_VIDEO, video_nr + index);\n+\tif (ret) {\n+\t\tv4l2_err(&dev->v4l2_dev,\n+\t\t\t \"Failed to register video %s[%d] device node\\n\",\n+\t\t\t node->name, node->id);\n+\t\tgoto ctrl_cleanup;\n+\t}\n+\n+\tnode->registered = true;\n+\tvideo_set_drvdata(vfd, node);\n+\n+\tv4l2_info(&dev->v4l2_dev,\n+\t\t  \"Device node %s[%d] registered as /dev/video%d\\n\",\n+\t\t  node->name, node->id, vfd->num);\n+\n+\treturn 0;\n+\n+ctrl_cleanup:\n+\tif (node_is_output(node))\n+\t\tv4l2_ctrl_handler_free(&dev->ctrl_handler);\n+queue_cleanup:\n+\tvb2_queue_release(&node->queue);\n+\treturn ret;\n+}\n+\n+/* Unregister one of the /dev/video<N> nodes associated with the ISP. */\n+static void unregister_node(struct bcm2835_isp_node *node)\n+{\n+\tstruct bcm2835_isp_dev *dev = node_get_dev(node);\n+\n+\tv4l2_info(&dev->v4l2_dev,\n+\t\t  \"Unregistering node %s[%d] device node /dev/video%d\\n\",\n+\t\t  node->name, node->id, node->vfd.num);\n+\n+\tif (node->registered) {\n+\t\tvideo_unregister_device(&node->vfd);\n+\t\tif (node_is_output(node))\n+\t\t\tv4l2_ctrl_handler_free(&dev->ctrl_handler);\n+\t\tvb2_queue_release(&node->queue);\n+\t}\n+\n+\t/*\n+\t * node->supported_fmts.list is free'd automatically\n+\t * as a managed resource.\n+\t */\n+\tnode->supported_fmts = NULL;\n+\tnode->num_supported_fmts = 0;\n+\tnode->vfd.ctrl_handler = NULL;\n+\tnode->registered = false;\n+}\n+\n+static void media_controller_unregister(struct bcm2835_isp_dev *dev)\n+{\n+\tunsigned int i;\n+\n+\tv4l2_info(&dev->v4l2_dev, \"Unregister from media controller\\n\");\n+\n+\tif (dev->media_device_registered) {\n+\t\tmedia_device_unregister(&dev->mdev);\n+\t\tmedia_device_cleanup(&dev->mdev);\n+\t\tdev->media_device_registered = false;\n+\t}\n+\n+\tkfree(dev->entity.name);\n+\tdev->entity.name = NULL;\n+\n+\tif (dev->media_entity_registered) {\n+\t\tmedia_device_unregister_entity(&dev->entity);\n+\t\tdev->media_entity_registered = false;\n+\t}\n+\n+\tfor (i = 0; i < BCM2835_ISP_NUM_NODES; i++) {\n+\t\tstruct bcm2835_isp_node *node = &dev->node[i];\n+\n+\t\tif (node->media_node_registered) {\n+\t\t\tmedia_remove_intf_links(node->intf_link->intf);\n+\t\t\tmedia_entity_remove_links(&dev->node[i].vfd.entity);\n+\t\t\tmedia_devnode_remove(node->intf_devnode);\n+\t\t\tmedia_device_unregister_entity(&node->vfd.entity);\n+\t\t\tkfree(node->vfd.entity.name);\n+\t\t}\n+\t\tnode->media_node_registered = false;\n+\t}\n+\n+\tdev->v4l2_dev.mdev = NULL;\n+}\n+\n+static int media_controller_register_node(struct bcm2835_isp_dev *dev, int num)\n+{\n+\tstruct bcm2835_isp_node *node = &dev->node[num];\n+\tstruct media_entity *entity = &node->vfd.entity;\n+\tint output = node_is_output(node);\n+\tchar *name;\n+\tint ret;\n+\n+\tv4l2_info(&dev->v4l2_dev,\n+\t\t  \"Register %s node %d with media controller\\n\",\n+\t\t  output ? \"output\" : \"capture\", num);\n+\tentity->obj_type = MEDIA_ENTITY_TYPE_VIDEO_DEVICE;\n+\tentity->function = MEDIA_ENT_F_IO_V4L;\n+\tentity->info.dev.major = VIDEO_MAJOR;\n+\tentity->info.dev.minor = node->vfd.minor;\n+\tname = kmalloc(BCM2835_ISP_ENTITY_NAME_LEN, GFP_KERNEL);\n+\tif (!name) {\n+\t\tret = -ENOMEM;\n+\t\tgoto error_no_mem;\n+\t}\n+\tsnprintf(name, BCM2835_ISP_ENTITY_NAME_LEN, \"%s0-%s%d\",\n+\t\t BCM2835_ISP_NAME, output ? \"output\" : \"capture\", num);\n+\tentity->name = name;\n+\tnode->pad.flags = output ? MEDIA_PAD_FL_SOURCE : MEDIA_PAD_FL_SINK;\n+\tret = media_entity_pads_init(entity, 1, &node->pad);\n+\tif (ret)\n+\t\tgoto error_pads_init;\n+\tret = media_device_register_entity(&dev->mdev, entity);\n+\tif (ret)\n+\t\tgoto error_register_entity;\n+\n+\tnode->intf_devnode = media_devnode_create(&dev->mdev,\n+\t\t\t\t\t\t  MEDIA_INTF_T_V4L_VIDEO, 0,\n+\t\t\t\t\t\t  VIDEO_MAJOR, node->vfd.minor);\n+\tif (!node->intf_devnode) {\n+\t\tret = -ENOMEM;\n+\t\tgoto error_devnode_create;\n+\t}\n+\n+\tnode->intf_link = media_create_intf_link(entity,\n+\t\t\t\t\t\t &node->intf_devnode->intf,\n+\t\t\t\t\t\t MEDIA_LNK_FL_IMMUTABLE |\n+\t\t\t\t\t\t MEDIA_LNK_FL_ENABLED);\n+\tif (!node->intf_link) {\n+\t\tret = -ENOMEM;\n+\t\tgoto error_create_intf_link;\n+\t}\n+\n+\tif (output)\n+\t\tret = media_create_pad_link(entity, 0, &dev->entity, num,\n+\t\t\t\t\t    MEDIA_LNK_FL_IMMUTABLE |\n+\t\t\t\t\t\t    MEDIA_LNK_FL_ENABLED);\n+\telse\n+\t\tret = media_create_pad_link(&dev->entity, num, entity, 0,\n+\t\t\t\t\t    MEDIA_LNK_FL_IMMUTABLE |\n+\t\t\t\t\t    MEDIA_LNK_FL_ENABLED);\n+\tif (ret)\n+\t\tgoto error_create_pad_link;\n+\n+\tdev->node[num].media_node_registered = true;\n+\treturn 0;\n+\n+error_create_pad_link:\n+\tmedia_remove_intf_links(&node->intf_devnode->intf);\n+error_create_intf_link:\n+\tmedia_devnode_remove(node->intf_devnode);\n+error_devnode_create:\n+\tmedia_device_unregister_entity(&node->vfd.entity);\n+error_register_entity:\n+error_pads_init:\n+\tkfree(entity->name);\n+\tentity->name = NULL;\n+error_no_mem:\n+\tif (ret)\n+\t\tv4l2_info(&dev->v4l2_dev, \"Error registering node\\n\");\n+\n+\treturn ret;\n+}\n+\n+static int media_controller_register(struct bcm2835_isp_dev *dev)\n+{\n+\tchar *name;\n+\tunsigned int i;\n+\tint ret;\n+\n+\tv4l2_dbg(2, debug, &dev->v4l2_dev, \"Registering with media controller\\n\");\n+\tdev->mdev.dev = dev->dev;\n+\tstrscpy(dev->mdev.model, \"bcm2835-isp\",\n+\t\tsizeof(dev->mdev.model));\n+\tstrscpy(dev->mdev.bus_info, \"platform:bcm2835-isp\",\n+\t\tsizeof(dev->mdev.bus_info));\n+\tmedia_device_init(&dev->mdev);\n+\tdev->v4l2_dev.mdev = &dev->mdev;\n+\n+\tv4l2_dbg(2, debug, &dev->v4l2_dev, \"Register entity for nodes\\n\");\n+\n+\tname = kmalloc(BCM2835_ISP_ENTITY_NAME_LEN, GFP_KERNEL);\n+\tif (!name) {\n+\t\tret = -ENOMEM;\n+\t\tgoto done;\n+\t}\n+\tsnprintf(name, BCM2835_ISP_ENTITY_NAME_LEN, \"bcm2835_isp0\");\n+\tdev->entity.name = name;\n+\tdev->entity.obj_type = MEDIA_ENTITY_TYPE_BASE;\n+\tdev->entity.function = MEDIA_ENT_F_PROC_VIDEO_SCALER;\n+\n+\tfor (i = 0; i < BCM2835_ISP_NUM_NODES; i++) {\n+\t\tdev->pad[i].flags = node_is_output(&dev->node[i]) ?\n+\t\t\t\t\tMEDIA_PAD_FL_SINK : MEDIA_PAD_FL_SOURCE;\n+\t}\n+\n+\tret = media_entity_pads_init(&dev->entity, BCM2835_ISP_NUM_NODES,\n+\t\t\t\t     dev->pad);\n+\tif (ret)\n+\t\tgoto done;\n+\n+\tret = media_device_register_entity(&dev->mdev, &dev->entity);\n+\tif (ret)\n+\t\tgoto done;\n+\n+\tdev->media_entity_registered = true;\n+\tfor (i = 0; i < BCM2835_ISP_NUM_NODES; i++) {\n+\t\tret = media_controller_register_node(dev, i);\n+\t\tif (ret)\n+\t\t\tgoto done;\n+\t}\n+\n+\tret = media_device_register(&dev->mdev);\n+\tif (!ret)\n+\t\tdev->media_device_registered = true;\n+done:\n+\treturn ret;\n+}\n+\n+static int bcm2835_isp_remove(struct platform_device *pdev)\n+{\n+\tstruct bcm2835_isp_dev *dev = platform_get_drvdata(pdev);\n+\tunsigned int i;\n+\n+\tmedia_controller_unregister(dev);\n+\n+\tfor (i = 0; i < BCM2835_ISP_NUM_NODES; i++)\n+\t\tunregister_node(&dev->node[i]);\n+\n+\tv4l2_device_unregister(&dev->v4l2_dev);\n+\n+\tif (dev->component)\n+\t\tvchiq_mmal_component_finalise(dev->mmal_instance,\n+\t\t\t\t\t      dev->component);\n+\n+\tvchiq_mmal_finalise(dev->mmal_instance);\n+\n+\treturn 0;\n+}\n+\n+static int bcm2835_isp_probe(struct platform_device *pdev)\n+{\n+\tstruct bcm2835_isp_dev *dev;\n+\tunsigned int i;\n+\tint ret;\n+\n+\tdev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);\n+\tif (!dev)\n+\t\treturn -ENOMEM;\n+\n+\tdev->dev = &pdev->dev;\n+\n+\tret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = vchiq_mmal_init(&dev->mmal_instance);\n+\tif (ret) {\n+\t\tv4l2_device_unregister(&dev->v4l2_dev);\n+\t\treturn ret;\n+\t}\n+\n+\tret = vchiq_mmal_component_init(dev->mmal_instance, \"ril.isp\",\n+\t\t\t\t\t&dev->component);\n+\tif (ret) {\n+\t\tv4l2_err(&dev->v4l2_dev,\n+\t\t\t \"%s: failed to create ril.isp component\\n\", __func__);\n+\t\tgoto error;\n+\t}\n+\n+\tif (dev->component->inputs < BCM2835_ISP_NUM_OUTPUTS ||\n+\t    dev->component->outputs < BCM2835_ISP_NUM_CAPTURES +\n+\t\t\t\t\tBCM2835_ISP_NUM_METADATA) {\n+\t\tv4l2_err(&dev->v4l2_dev,\n+\t\t\t \"%s: ril.isp returned %d i/p (%d expected), %d o/p (%d expected) ports\\n\",\n+\t\t\t  __func__, dev->component->inputs,\n+\t\t\t  BCM2835_ISP_NUM_OUTPUTS,\n+\t\t\t  dev->component->outputs,\n+\t\t\t  BCM2835_ISP_NUM_CAPTURES + BCM2835_ISP_NUM_METADATA);\n+\t\tgoto error;\n+\t}\n+\n+\tatomic_set(&dev->num_streaming, 0);\n+\n+\tfor (i = 0; i < BCM2835_ISP_NUM_NODES; i++) {\n+\t\tstruct bcm2835_isp_node *node = &dev->node[i];\n+\n+\t\tret = register_node(dev, node, i);\n+\t\tif (ret)\n+\t\t\tgoto error;\n+\t}\n+\n+\tret = media_controller_register(dev);\n+\tif (ret)\n+\t\tgoto error;\n+\n+\tplatform_set_drvdata(pdev, dev);\n+\tv4l2_info(&dev->v4l2_dev, \"Loaded V4L2 %s\\n\", BCM2835_ISP_NAME);\n+\treturn 0;\n+\n+error:\n+\tbcm2835_isp_remove(pdev);\n+\n+\treturn ret;\n+}\n+\n+static struct platform_driver bcm2835_isp_pdrv = {\n+\t.probe = bcm2835_isp_probe,\n+\t.remove = bcm2835_isp_remove,\n+\t.driver = {\n+\t\t\t.name = BCM2835_ISP_NAME,\n+\t\t  },\n+};\n+\n+module_platform_driver(bcm2835_isp_pdrv);\n+\n+MODULE_DESCRIPTION(\"BCM2835 ISP driver\");\n+MODULE_AUTHOR(\"Naushir Patuck <naush@raspberrypi.com>\");\n+MODULE_LICENSE(\"GPL\");\n+MODULE_VERSION(\"1.0\");\n+MODULE_ALIAS(\"platform:bcm2835-isp\");\n--- a/drivers/staging/vc04_services/vchiq-mmal/mmal-encodings.h\n+++ b/drivers/staging/vc04_services/vchiq-mmal/mmal-encodings.h\n@@ -113,6 +113,10 @@\n  */\n #define MMAL_ENCODING_EGL_IMAGE        MMAL_FOURCC('E', 'G', 'L', 'I')\n \n+/** ISP image statistics format\n+ */\n+#define MMAL_ENCODING_BRCM_STATS       MMAL_FOURCC('S', 'T', 'A', 'T')\n+\n /* }@ */\n \n /** \\name Pre-defined audio encodings */\n--- a/drivers/staging/vc04_services/vchiq-mmal/mmal-parameters.h\n+++ b/drivers/staging/vc04_services/vchiq-mmal/mmal-parameters.h\n@@ -221,6 +221,62 @@ enum mmal_parameter_camera_type {\n \tMMAL_PARAMETER_SHUTTER_SPEED,\n \t\t/**< Takes a @ref MMAL_PARAMETER_AWB_GAINS_T */\n \tMMAL_PARAMETER_CUSTOM_AWB_GAINS,\n+\t\t/**< Takes a @ref MMAL_PARAMETER_CAMERA_SETTINGS_T */\n+\tMMAL_PARAMETER_CAMERA_SETTINGS,\n+\t\t/**< Takes a @ref MMAL_PARAMETER_PRIVACY_INDICATOR_T */\n+\tMMAL_PARAMETER_PRIVACY_INDICATOR,\n+\t\t/**< Takes a @ref MMAL_PARAMETER_BOOLEAN_T */\n+\tMMAL_PARAMETER_VIDEO_DENOISE,\n+\t\t/**< Takes a @ref MMAL_PARAMETER_BOOLEAN_T */\n+\tMMAL_PARAMETER_STILLS_DENOISE,\n+\t\t/**< Takes a @ref MMAL_PARAMETER_CAMERA_ANNOTATE_T */\n+\tMMAL_PARAMETER_ANNOTATE,\n+\t\t/**< Takes a @ref MMAL_PARAMETER_STEREOSCOPIC_MODE_T */\n+\tMMAL_PARAMETER_STEREOSCOPIC_MODE,\n+\t\t/**< Takes a @ref MMAL_PARAMETER_CAMERA_INTERFACE_T */\n+\tMMAL_PARAMETER_CAMERA_INTERFACE,\n+\t\t/**< Takes a @ref MMAL_PARAMETER_CAMERA_CLOCKING_MODE_T */\n+\tMMAL_PARAMETER_CAMERA_CLOCKING_MODE,\n+\t\t/**< Takes a @ref MMAL_PARAMETER_CAMERA_RX_CONFIG_T */\n+\tMMAL_PARAMETER_CAMERA_RX_CONFIG,\n+\t\t/**< Takes a @ref MMAL_PARAMETER_CAMERA_RX_TIMING_T */\n+\tMMAL_PARAMETER_CAMERA_RX_TIMING,\n+\t\t/**< Takes a @ref MMAL_PARAMETER_UINT32_T */\n+\tMMAL_PARAMETER_DPF_CONFIG,\n+\n+\t/* 0x50 */\n+\t\t/**< Takes a @ref MMAL_PARAMETER_UINT32_T */\n+\tMMAL_PARAMETER_JPEG_RESTART_INTERVAL,\n+\t\t/**< Takes a @ref MMAL_PARAMETER_UINT32_T */\n+\tMMAL_PARAMETER_CAMERA_ISP_BLOCK_OVERRIDE,\n+\t\t/**< Takes a @ref MMAL_PARAMETER_LENS_SHADING_T */\n+\tMMAL_PARAMETER_LENS_SHADING_OVERRIDE,\n+\t\t/**< Takes a @ref MMAL_PARAMETER_UINT32_T */\n+\tMMAL_PARAMETER_BLACK_LEVEL,\n+\t\t/**< Takes a @ref MMAL_PARAMETER_RESIZE_T */\n+\tMMAL_PARAMETER_RESIZE_PARAMS,\n+\t\t/**< Takes a @ref MMAL_PARAMETER_CROP_T */\n+\tMMAL_PARAMETER_CROP,\n+\t\t/**< Takes a @ref MMAL_PARAMETER_INT32_T */\n+\tMMAL_PARAMETER_OUTPUT_SHIFT,\n+\t\t/**< Takes a @ref MMAL_PARAMETER_INT32_T */\n+\tMMAL_PARAMETER_CCM_SHIFT,\n+\t\t/**< Takes a @ref MMAL_PARAMETER_CUSTOM_CCM_T */\n+\tMMAL_PARAMETER_CUSTOM_CCM,\n+\t\t/**< Takes a @ref MMAL_PARAMETER_RATIONAL_T */\n+\tMMAL_PARAMETER_ANALOG_GAIN,\n+\t\t/**< Takes a @ref MMAL_PARAMETER_RATIONAL_T */\n+\tMMAL_PARAMETER_DIGITAL_GAIN,\n+\t\t/**< Takes a @ref MMAL_PARAMETER_DENOISE_T */\n+\tMMAL_PARAMETER_DENOISE,\n+\t\t/**< Takes a @ref MMAL_PARAMETER_SHARPEN_T */\n+\tMMAL_PARAMETER_SHARPEN,\n+\t\t/**< Takes a @ref MMAL_PARAMETER_GEQ_T */\n+\tMMAL_PARAMETER_GEQ,\n+\t\t/**< Tales a @ref MMAP_PARAMETER_DPC_T */\n+\tMMAL_PARAMETER_DPC,\n+\t\t/**< Tales a @ref MMAP_PARAMETER_GAMMA_T */\n+\tMMAL_PARAMETER_GAMMA,\n };\n \n struct mmal_parameter_rational {\n@@ -786,7 +842,102 @@ struct mmal_parameter_camera_info {\n \tstruct mmal_parameter_camera_info_camera\n \t\tcameras[MMAL_PARAMETER_CAMERA_INFO_MAX_CAMERAS];\n \tstruct mmal_parameter_camera_info_flash\n-\t\t\t\tflashes[MMAL_PARAMETER_CAMERA_INFO_MAX_FLASHES];\n+\t\tflashes[MMAL_PARAMETER_CAMERA_INFO_MAX_FLASHES];\n+};\n+\n+struct mmal_parameter_ccm {\n+\tstruct mmal_parameter_rational ccm[3][3];\n+\ts32 offsets[3];\n+};\n+\n+struct mmal_parameter_custom_ccm {\n+\tu32 enabled; /**< Enable the custom CCM. */\n+\tstruct mmal_parameter_ccm ccm; /**< CCM to be used. */\n+};\n+\n+struct mmal_parameter_lens_shading {\n+\tu32 enabled;\n+\tu32 grid_cell_size;\n+\tu32 grid_width;\n+\tu32 grid_stride;\n+\tu32 grid_height;\n+\tu32 mem_handle_table;\n+\tu32 ref_transform;\n+};\n+\n+enum mmal_parameter_ls_gain_format_type {\n+\tMMAL_PARAMETER_LS_GAIN_FORMAT_TYPE_U0P8_1 = 0,\n+\tMMAL_PARAMETER_LS_GAIN_FORMAT_TYPE_U1P7_0 = 1,\n+\tMMAL_PARAMETER_LS_GAIN_FORMAT_TYPE_U1P7_1 = 2,\n+\tMMAL_PARAMETER_LS_GAIN_FORMAT_TYPE_U2P6_0 = 3,\n+\tMMAL_PARAMETER_LS_GAIN_FORMAT_TYPE_U2P6_1 = 4,\n+\tMMAL_PARAMETER_LS_GAIN_FORMAT_TYPE_U3P5_0 = 5,\n+\tMMAL_PARAMETER_LS_GAIN_FORMAT_TYPE_U3P5_1 = 6,\n+\tMMAL_PARAMETER_LS_GAIN_FORMAT_TYPE_U4P10  = 7,\n+\tMMAL_PARAMETER_LS_GAIN_FORMAT_TYPE_DUMMY  = 0x7FFFFFFF\n+};\n+\n+struct mmal_parameter_lens_shading_v2 {\n+\tu32 enabled;\n+\tu32 grid_cell_size;\n+\tu32 grid_width;\n+\tu32 grid_stride;\n+\tu32 grid_height;\n+\tu32 mem_handle_table;\n+\tu32 ref_transform;\n+\tu32 corner_sampled;\n+\tenum mmal_parameter_ls_gain_format_type gain_format;\n+};\n+\n+struct mmal_parameter_black_level {\n+\tu32 enabled;\n+\tu16 black_level_r;\n+\tu16 black_level_g;\n+\tu16 black_level_b;\n+\tu8 pad_[2]; /* Unused */\n+};\n+\n+struct mmal_parameter_geq {\n+\tu32 enabled;\n+\tu32 offset;\n+\tstruct mmal_parameter_rational slope;\n+};\n+\n+#define MMAL_NUM_GAMMA_PTS 33\n+struct mmal_parameter_gamma {\n+\tu32 enabled;\n+\tu16 x[MMAL_NUM_GAMMA_PTS];\n+\tu16 y[MMAL_NUM_GAMMA_PTS];\n+};\n+\n+struct mmal_parameter_denoise {\n+\tu32 enabled;\n+\tu32 constant;\n+\tstruct mmal_parameter_rational slope;\n+\tstruct mmal_parameter_rational strength;\n+};\n+\n+struct mmal_parameter_sharpen {\n+\tu32 enabled;\n+\tstruct mmal_parameter_rational threshold;\n+\tstruct mmal_parameter_rational strength;\n+\tstruct mmal_parameter_rational limit;\n+};\n+\n+enum mmal_dpc_mode {\n+\tMMAL_DPC_MODE_OFF = 0,\n+\tMMAL_DPC_MODE_NORMAL = 1,\n+\tMMAL_DPC_MODE_STRONG = 2,\n+\tMMAL_DPC_MODE_MAX = 0x7FFFFFFF,\n+};\n+\n+struct mmal_parameter_dpc {\n+\tu32 enabled;\n+\tu32 strength;\n+};\n+\n+struct mmal_parameter_crop {\n+\tstruct vchiq_mmal_rect rect;\n };\n \n #endif\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0346-drm-vc4-A-present-but-empty-dmas-disables-audio.patch",
    "content": "From 4de61df3c777ea6265d03be98b315c8644003ceb Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.org>\nDate: Wed, 31 Jul 2019 17:36:34 +0100\nSubject: [PATCH] drm/vc4: A present but empty dmas disables audio\n\nOverlays are unable to remove properties in the base DTB, but they\ncan overwrite them. Allow a present but empty 'dmas' property\nto also disable the HDMI audio interface.\n\nSee: https://github.com/raspberrypi/linux/issues/2489\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.org>\n---\n drivers/gpu/drm/vc4/vc4_hdmi.c | 6 ++++--\n 1 file changed, 4 insertions(+), 2 deletions(-)\n\n--- a/drivers/gpu/drm/vc4/vc4_hdmi.c\n+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c\n@@ -1333,10 +1333,12 @@ static int vc4_hdmi_audio_init(struct vc\n \tconst __be32 *addr;\n \tint index;\n \tint ret;\n+\tint len;\n \n-\tif (!of_find_property(dev->of_node, \"dmas\", NULL)) {\n+\tif (!of_find_property(dev->of_node, \"dmas\", &len) ||\n+\t    len == 0) {\n \t\tdev_warn(dev,\n-\t\t\t \"'dmas' DT property is missing, no HDMI audio\\n\");\n+\t\t\t \"'dmas' DT property is missing or empty, no HDMI audio\\n\");\n \t\treturn 0;\n \t}\n \n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0347-drm-vc4-Add-debugfs-node-that-dumps-the-current-disp.patch",
    "content": "From 09157702811f9e2144a769aef1f2269306fe86bb Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Tue, 6 Oct 2020 18:44:42 +0100\nSubject: [PATCH] drm/vc4: Add debugfs node that dumps the current\n display lists\n\nThis allows easy analysis of display lists when debugging.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n drivers/gpu/drm/vc4/vc4_hvs.c | 41 +++++++++++++++++++++++++++++++++++\n 1 file changed, 41 insertions(+)\n\n--- a/drivers/gpu/drm/vc4/vc4_hvs.c\n+++ b/drivers/gpu/drm/vc4/vc4_hvs.c\n@@ -95,6 +95,45 @@ static int vc4_hvs_debugfs_underrun(stru\n \treturn 0;\n }\n \n+static int vc4_hvs_debugfs_dlist(struct seq_file *m, void *data)\n+{\n+\tstruct drm_info_node *node = m->private;\n+\tstruct drm_device *dev = node->minor->dev;\n+\tstruct vc4_dev *vc4 = to_vc4_dev(dev);\n+\tstruct drm_printer p = drm_seq_file_printer(m);\n+\tunsigned int next_entry_start = 0;\n+\tunsigned int i, j;\n+\tu32 dlist_word, dispstat;\n+\n+\tfor (i = 0; i < SCALER_CHANNELS_COUNT; i++) {\n+\t\tdispstat = VC4_GET_FIELD(HVS_READ(SCALER_DISPSTATX(i)),\n+\t\t\t\t\t SCALER_DISPSTATX_MODE);\n+\t\tif (dispstat == SCALER_DISPSTATX_MODE_DISABLED ||\n+\t\t    dispstat == SCALER_DISPSTATX_MODE_EOF) {\n+\t\t\tdrm_printf(&p, \"HVS chan %u disabled\\n\", i);\n+\t\t\tcontinue;\n+\t\t}\n+\n+\t\tdrm_printf(&p, \"HVS chan %u:\\n\", i);\n+\n+\t\tfor (j = HVS_READ(SCALER_DISPLISTX(i)); j < 256; j++) {\n+\t\t\tdlist_word = readl((u32 __iomem *)vc4->hvs->dlist + j);\n+\t\t\tdrm_printf(&p, \"dlist: %02d: 0x%08x\\n\", j,\n+\t\t\t\t   dlist_word);\n+\t\t\tif (!next_entry_start ||\n+\t\t\t    next_entry_start == j) {\n+\t\t\t\tif (dlist_word & SCALER_CTL0_END)\n+\t\t\t\t\tbreak;\n+\t\t\t\tnext_entry_start = j +\n+\t\t\t\t\tVC4_GET_FIELD(dlist_word,\n+\t\t\t\t\t\t      SCALER_CTL0_SIZE);\n+\t\t\t}\n+\t\t}\n+\t}\n+\n+\treturn 0;\n+}\n+\n /* The filter kernel is composed of dwords each containing 3 9-bit\n  * signed integers packed next to each other.\n  */\n@@ -671,6 +710,8 @@ static int vc4_hvs_bind(struct device *d\n \tvc4_debugfs_add_regset32(drm, \"hvs_regs\", &hvs->regset);\n \tvc4_debugfs_add_file(drm, \"hvs_underrun\", vc4_hvs_debugfs_underrun,\n \t\t\t     NULL);\n+\tvc4_debugfs_add_file(drm, \"hvs_dlists\", vc4_hvs_debugfs_dlist,\n+\t\t\t     NULL);\n \n \treturn 0;\n }\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0348-gpio-Add-gpio-fsm-driver.patch",
    "content": "From 69f26eddc66378e33866cb30fc36309cd1d71b4a Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.com>\nDate: Wed, 30 Sep 2020 12:00:54 +0100\nSubject: [PATCH] gpio: Add gpio-fsm driver\n\nThe gpio-fsm driver implements simple state machines that allow GPIOs\nto be controlled in response to inputs from other GPIOs - real and\nsoft/virtual - and time delays. It can:\n+ create dummy GPIOs for drivers that demand them,\n+ drive multiple GPIOs from a single input, with optional delays,\n+ add a debounce circuit to an input,\n+ drive pattern sequences onto LEDs\netc.\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.com>\n---\n drivers/gpio/Kconfig                |    9 +\n drivers/gpio/Makefile               |    1 +\n drivers/gpio/gpio-fsm.c             | 1103 +++++++++++++++++++++++++++\n include/dt-bindings/gpio/gpio-fsm.h |   21 +\n 4 files changed, 1134 insertions(+)\n create mode 100644 drivers/gpio/gpio-fsm.c\n create mode 100644 include/dt-bindings/gpio/gpio-fsm.h\n\n--- a/drivers/gpio/Kconfig\n+++ b/drivers/gpio/Kconfig\n@@ -1164,6 +1164,15 @@ config HTC_EGPIO\n \t  several HTC phones.  It provides basic support for input\n \t  pins, output pins, and irqs.\n \n+config GPIO_FSM\n+\ttristate \"GPIO FSM support\"\n+\thelp\n+\t  The GPIO FSM driver allows the creation of state machines for\n+\t  manipulating GPIOs (both real and virtual), with state transitions\n+\t  triggered by GPIO edges or delays.\n+\n+\t  If unsure, say N.\n+\n config GPIO_JANZ_TTL\n \ttristate \"Janz VMOD-TTL Digital IO Module\"\n \tdepends on MFD_JANZ_CMODIO\n--- a/drivers/gpio/Makefile\n+++ b/drivers/gpio/Makefile\n@@ -61,6 +61,7 @@ obj-$(CONFIG_GPIO_EP93XX)\t\t+= gpio-ep93x\n obj-$(CONFIG_GPIO_EXAR)\t\t\t+= gpio-exar.o\n obj-$(CONFIG_GPIO_F7188X)\t\t+= gpio-f7188x.o\n obj-$(CONFIG_GPIO_FTGPIO010)\t\t+= gpio-ftgpio010.o\n+obj-$(CONFIG_GPIO_FSM)\t\t\t+= gpio-fsm.o\n obj-$(CONFIG_GPIO_GE_FPGA)\t\t+= gpio-ge.o\n obj-$(CONFIG_GPIO_GPIO_MM)\t\t+= gpio-gpio-mm.o\n obj-$(CONFIG_GPIO_GRGPIO)\t\t+= gpio-grgpio.o\n--- /dev/null\n+++ b/drivers/gpio/gpio-fsm.c\n@@ -0,0 +1,1103 @@\n+// SPDX-License-Identifier: GPL-2.0+\n+/*\n+ *  GPIO FSM driver\n+ *\n+ *  This driver implements simple state machines that allow real GPIOs to be\n+ *  controlled in response to inputs from other GPIOs - real and soft/virtual -\n+ *  and time delays. It can:\n+ *  + create dummy GPIOs for drivers that demand them\n+ *  + drive multiple GPIOs from a single input,  with optional delays\n+ *  + add a debounce circuit to an input\n+ *  + drive pattern sequences onto LEDs\n+ *  etc.\n+ *\n+ *  Copyright (C) 2020 Raspberry Pi (Trading) Ltd.\n+ */\n+\n+#include <linux/err.h>\n+#include <linux/gpio.h>\n+#include <linux/gpio/driver.h>\n+#include <linux/interrupt.h>\n+#include <linux/module.h>\n+#include <linux/platform_device.h>\n+\n+#include <dt-bindings/gpio/gpio-fsm.h>\n+\n+#define MODULE_NAME \"gpio-fsm\"\n+\n+#define GF_IO_TYPE(x) ((u32)(x) & 0xffff)\n+#define GF_IO_INDEX(x) ((u32)(x) >> 16)\n+\n+enum {\n+\tSIGNAL_GPIO,\n+\tSIGNAL_SOFT\n+};\n+\n+enum {\n+\tINPUT_GPIO,\n+\tINPUT_SOFT\n+};\n+\n+enum {\n+\tSYM_UNDEFINED,\n+\tSYM_NAME,\n+\tSYM_SET,\n+\tSYM_START,\n+\tSYM_SHUTDOWN,\n+\n+\tSYM_MAX\n+};\n+\n+struct soft_gpio {\n+\tint dir;\n+\tint value;\n+};\n+\n+struct input_gpio_state {\n+\tstruct gpio_fsm *gf;\n+\tstruct gpio_desc  *desc;\n+\tstruct fsm_state *target;\n+\tint index;\n+\tint value;\n+\tint irq;\n+\tbool enabled;\n+\tbool active_low;\n+};\n+\n+struct gpio_event {\n+\tint index;\n+\tint value;\n+\tstruct fsm_state *target;\n+};\n+\n+struct symtab_entry {\n+\tconst char *name;\n+\tvoid *value;\n+\tstruct symtab_entry *next;\n+};\n+\n+struct output_signal {\n+\tu8 type;\n+\tu8 value;\n+\tu16 index;\n+};\n+\n+struct fsm_state {\n+\tconst char *name;\n+\tstruct output_signal *signals;\n+\tstruct gpio_event *gpio_events;\n+\tstruct gpio_event *soft_events;\n+\tstruct fsm_state *delay_target;\n+\tstruct fsm_state *shutdown_target;\n+\tunsigned int num_signals;\n+\tunsigned int num_gpio_events;\n+\tunsigned int num_soft_events;\n+\tunsigned int delay_ms;\n+\tunsigned int shutdown_ms;\n+};\n+\n+struct gpio_fsm {\n+\tstruct gpio_chip gc;\n+\tstruct device *dev;\n+\tspinlock_t spinlock;\n+\tstruct work_struct work;\n+\tstruct timer_list timer;\n+\twait_queue_head_t shutdown_event;\n+\tstruct fsm_state *states;\n+\tstruct input_gpio_state *input_gpio_states;\n+\tstruct gpio_descs *input_gpios;\n+\tstruct gpio_descs *output_gpios;\n+\tstruct soft_gpio *soft_gpios;\n+\tstruct fsm_state *start_state;\n+\tstruct fsm_state *shutdown_state;\n+\tunsigned int num_states;\n+\tunsigned int num_output_gpios;\n+\tunsigned int num_input_gpios;\n+\tunsigned int num_soft_gpios;\n+\tunsigned int shutdown_timeout_ms;\n+\tunsigned int shutdown_jiffies;\n+\n+\tstruct fsm_state *current_state;\n+\tstruct fsm_state *next_state;\n+\tstruct fsm_state *delay_target_state;\n+\tint delay_ms;\n+\tunsigned int debug;\n+\tbool shutting_down;\n+\tstruct symtab_entry *symtab;\n+};\n+\n+static struct symtab_entry *do_add_symbol(struct symtab_entry **symtab,\n+\t\t\t\t\t  const char *name, void *value)\n+{\n+\tstruct symtab_entry **p = symtab;\n+\n+\twhile (*p && strcmp((*p)->name, name))\n+\t\tp = &(*p)->next;\n+\n+\tif (*p) {\n+\t\t/* This is an existing symbol */\n+\t\tif ((*p)->value) {\n+\t\t\t/* Already defined */\n+\t\t\tif (value) {\n+\t\t\t\tif ((uintptr_t)value < SYM_MAX)\n+\t\t\t\t\treturn ERR_PTR(-EINVAL);\n+\t\t\t\telse\n+\t\t\t\t\treturn ERR_PTR(-EEXIST);\n+\t\t\t}\n+\t\t} else {\n+\t\t\t/* Undefined */\n+\t\t\t(*p)->value = value;\n+\t\t}\n+\t} else {\n+\t\t/* This is a new symbol */\n+\t\t*p = kmalloc(sizeof(struct symtab_entry), GFP_KERNEL);\n+\t\tif (*p) {\n+\t\t\t(*p)->name = name;\n+\t\t\t(*p)->value = value;\n+\t\t\t(*p)->next = NULL;\n+\t\t}\n+\t}\n+\treturn *p;\n+}\n+\n+static int add_symbol(struct symtab_entry **symtab,\n+\t\t      const char *name, void *value)\n+{\n+\tstruct symtab_entry *sym = do_add_symbol(symtab, name, value);\n+\n+\treturn PTR_ERR_OR_ZERO(sym);\n+}\n+\n+static struct symtab_entry *get_symbol(struct symtab_entry **symtab,\n+\t\t\t\t       const char *name)\n+{\n+\tstruct symtab_entry *sym = do_add_symbol(symtab, name, NULL);\n+\n+\tif (IS_ERR(sym))\n+\t\treturn NULL;\n+\treturn sym;\n+}\n+\n+static void free_symbols(struct symtab_entry **symtab)\n+{\n+\tstruct symtab_entry *sym = *symtab;\n+\tvoid *p;\n+\n+\t*symtab = NULL;\n+\twhile (sym) {\n+\t\tp = sym;\n+\t\tsym = sym->next;\n+\t\tkfree(p);\n+\t}\n+}\n+\n+static int gpio_fsm_get_direction(struct gpio_chip *gc, unsigned int off)\n+{\n+\tstruct gpio_fsm *gf = gpiochip_get_data(gc);\n+\tstruct soft_gpio *sg;\n+\n+\tif (off >= gf->num_soft_gpios)\n+\t\treturn -EINVAL;\n+\tsg = &gf->soft_gpios[off];\n+\n+\treturn sg->dir;\n+}\n+\n+static int gpio_fsm_get(struct gpio_chip *gc, unsigned int off)\n+{\n+\tstruct gpio_fsm *gf = gpiochip_get_data(gc);\n+\tstruct soft_gpio *sg;\n+\n+\tif (off >= gf->num_soft_gpios)\n+\t\treturn -EINVAL;\n+\tsg = &gf->soft_gpios[off];\n+\n+\treturn sg->value;\n+}\n+\n+static void gpio_fsm_go_to_state(struct gpio_fsm *gf,\n+\t\t\t\t   struct fsm_state *new_state)\n+{\n+\tstruct input_gpio_state *inp_state;\n+\tstruct gpio_event *gp_ev;\n+\tstruct fsm_state *state;\n+\tint i;\n+\n+\tdev_dbg(gf->dev, \"go_to_state(%s)\\n\",\n+\t\t  new_state ? new_state->name : \"<unset>\");\n+\n+\tspin_lock(&gf->spinlock);\n+\n+\tif (gf->next_state) {\n+\t\t/* Something else has already requested a transition */\n+\t\tspin_unlock(&gf->spinlock);\n+\t\treturn;\n+\t}\n+\n+\tgf->next_state = new_state;\n+\tstate = gf->current_state;\n+\tgf->delay_target_state = NULL;\n+\n+\tif (state) {\n+\t\t/* Disarm any GPIO IRQs */\n+\t\tfor (i = 0; i < state->num_gpio_events; i++) {\n+\t\t\tgp_ev = &state->gpio_events[i];\n+\t\t\tinp_state = &gf->input_gpio_states[gp_ev->index];\n+\t\t\tinp_state->target = NULL;\n+\t\t}\n+\t}\n+\n+\tspin_unlock(&gf->spinlock);\n+\n+\tif (new_state)\n+\t\tschedule_work(&gf->work);\n+}\n+\n+static void gpio_fsm_set_soft(struct gpio_fsm *gf,\n+\t\t\t\tunsigned int off, int val)\n+{\n+\tstruct soft_gpio *sg = &gf->soft_gpios[off];\n+\tstruct gpio_event *gp_ev;\n+\tstruct fsm_state *state;\n+\tint i;\n+\n+\tdev_dbg(gf->dev, \"set(%d,%d)\\n\", off, val);\n+\tstate = gf->current_state;\n+\tsg->value = val;\n+\tfor (i = 0; i < state->num_soft_events; i++) {\n+\t\tgp_ev = &state->soft_events[i];\n+\t\tif (gp_ev->index == off && gp_ev->value == val) {\n+\t\t\tif (gf->debug)\n+\t\t\t\tdev_info(gf->dev,\n+\t\t\t\t\t \"GF_SOFT %d->%d -> %s\\n\", gp_ev->index,\n+\t\t\t\t\t gp_ev->value, gp_ev->target->name);\n+\t\t\tgpio_fsm_go_to_state(gf, gp_ev->target);\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+}\n+\n+static int gpio_fsm_direction_input(struct gpio_chip *gc, unsigned int off)\n+{\n+\tstruct gpio_fsm *gf = gpiochip_get_data(gc);\n+\tstruct soft_gpio *sg;\n+\n+\tif (off >= gf->num_soft_gpios)\n+\t\treturn -EINVAL;\n+\tsg = &gf->soft_gpios[off];\n+\tsg->dir = GPIOF_DIR_IN;\n+\n+\treturn 0;\n+}\n+\n+static int gpio_fsm_direction_output(struct gpio_chip *gc, unsigned int off,\n+\t\t\t\t       int value)\n+{\n+\tstruct gpio_fsm *gf = gpiochip_get_data(gc);\n+\tstruct soft_gpio *sg;\n+\n+\tif (off >= gf->num_soft_gpios)\n+\t\treturn -EINVAL;\n+\tsg = &gf->soft_gpios[off];\n+\tsg->dir = GPIOF_DIR_OUT;\n+\tgpio_fsm_set_soft(gf, off, value);\n+\n+\treturn 0;\n+}\n+\n+static void gpio_fsm_set(struct gpio_chip *gc, unsigned int off, int val)\n+{\n+\tstruct gpio_fsm *gf;\n+\n+\tgf = gpiochip_get_data(gc);\n+\tif (off < gf->num_soft_gpios)\n+\t\tgpio_fsm_set_soft(gf, off, val);\n+}\n+\n+static void gpio_fsm_enter_state(struct gpio_fsm *gf,\n+\t\t\t\t   struct fsm_state *state)\n+{\n+\tstruct input_gpio_state *inp_state;\n+\tstruct output_signal *signal;\n+\tstruct gpio_event *event;\n+\tstruct gpio_desc *gpiod;\n+\tstruct soft_gpio *soft;\n+\tint value;\n+\tint i;\n+\n+\tdev_dbg(gf->dev, \"enter_state(%s)\\n\", state->name);\n+\n+\tgf->current_state = state;\n+\n+\t// 1. Apply any listed signals\n+\tfor (i = 0; i < state->num_signals; i++) {\n+\t\tsignal = &state->signals[i];\n+\n+\t\tif (gf->debug)\n+\t\t\tdev_info(gf->dev, \"  set %s %d->%d\\n\",\n+\t\t\t\t (signal->type == SIGNAL_GPIO) ? \"GF_OUT\" :\n+\t\t\t\t \"GF_SOFT\",\n+\t\t\t\t signal->index, signal->value);\n+\t\tswitch (signal->type) {\n+\t\tcase SIGNAL_GPIO:\n+\t\t\tgpiod = gf->output_gpios->desc[signal->index];\n+\t\t\tgpiod_set_value_cansleep(gpiod, signal->value);\n+\t\t\tbreak;\n+\t\tcase SIGNAL_SOFT:\n+\t\t\tsoft = &gf->soft_gpios[signal->index];\n+\t\t\tgpio_fsm_set_soft(gf, signal->index, signal->value);\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\n+\t// 2. Exit if successfully reached shutdown state\n+\tif (gf->shutting_down && state == state->shutdown_target) {\n+\t\twake_up(&gf->shutdown_event);\n+\t\treturn;\n+\t}\n+\n+\t// 3. Schedule a timer callback if shutting down\n+\tif (state->shutdown_target) {\n+\t\t// Remember the absolute shutdown time in case remove is called\n+\t\t// at a later time.\n+\t\tgf->shutdown_jiffies =\n+\t\t\tjiffies + msecs_to_jiffies(state->shutdown_ms);\n+\n+\t\tif (gf->shutting_down) {\n+\t\t\tgf->delay_target_state = state->shutdown_target;\n+\t\t\tgf->delay_ms = state->shutdown_ms;\n+\t\t\tmod_timer(&gf->timer, gf->shutdown_jiffies);\n+\t\t}\n+\t}\n+\n+\t// During shutdown, skip everything else\n+\tif (gf->shutting_down)\n+\t\treturn;\n+\n+\t// Otherwise record what the shutdown time would be\n+\tgf->shutdown_jiffies = jiffies + msecs_to_jiffies(state->shutdown_ms);\n+\n+\t// 4. Check soft inputs for transitions to take\n+\tfor (i = 0; i < state->num_soft_events; i++) {\n+\t\tevent = &state->soft_events[i];\n+\t\tif (gf->soft_gpios[event->index].value == event->value) {\n+\t\t\tif (gf->debug)\n+\t\t\t\tdev_info(gf->dev,\n+\t\t\t\t\t \"GF_SOFT %d=%d -> %s\\n\", event->index,\n+\t\t\t\t\t event->value, event->target->name);\n+\t\t\tgpio_fsm_go_to_state(gf, event->target);\n+\t\t\treturn;\n+\t\t}\n+\t}\n+\n+\t// 5. Check GPIOs for transitions to take, enabling the IRQs\n+\tfor (i = 0; i < state->num_gpio_events; i++) {\n+\t\tevent = &state->gpio_events[i];\n+\t\tinp_state = &gf->input_gpio_states[event->index];\n+\t\tinp_state->target = event->target;\n+\t\tinp_state->value = event->value;\n+\t\tinp_state->enabled = true;\n+\n+\t\tvalue = gpiod_get_value(gf->input_gpios->desc[event->index]);\n+\n+\t\t// Clear stale event state\n+\t\tdisable_irq(inp_state->irq);\n+\n+\t\tirq_set_irq_type(inp_state->irq,\n+\t\t\t\t (inp_state->value ^ inp_state->active_low) ?\n+\t\t\t\t IRQF_TRIGGER_RISING : IRQF_TRIGGER_FALLING);\n+\t\tenable_irq(inp_state->irq);\n+\n+\t\tif (value == event->value && inp_state->target) {\n+\t\t\tif (gf->debug)\n+\t\t\t\tdev_info(gf->dev,\n+\t\t\t\t\t \"GF_IN %d=%d -> %s\\n\", event->index,\n+\t\t\t\t\t event->value, event->target->name);\n+\t\t\tgpio_fsm_go_to_state(gf, event->target);\n+\t\t\treturn;\n+\t\t}\n+\t}\n+\n+\t// 6. Schedule a timer callback if delay_target\n+\tif (state->delay_target) {\n+\t\tgf->delay_target_state = state->delay_target;\n+\t\tgf->delay_ms = state->delay_ms;\n+\t\tmod_timer(&gf->timer,\n+\t\t\t  jiffies + msecs_to_jiffies(state->delay_ms));\n+\t}\n+}\n+\n+static void gpio_fsm_work(struct work_struct *work)\n+{\n+\tstruct input_gpio_state *inp_state;\n+\tstruct fsm_state *new_state;\n+\tstruct fsm_state *state;\n+\tstruct gpio_event *gp_ev;\n+\tstruct gpio_fsm *gf;\n+\tint i;\n+\n+\tgf = container_of(work, struct gpio_fsm, work);\n+\tspin_lock(&gf->spinlock);\n+\tstate = gf->current_state;\n+\tnew_state = gf->next_state;\n+\tif (!new_state)\n+\t\tnew_state = gf->delay_target_state;\n+\tgf->next_state = NULL;\n+\tgf->delay_target_state = NULL;\n+\tspin_unlock(&gf->spinlock);\n+\n+\tif (state) {\n+\t\t/* Disable any enabled GPIO IRQs */\n+\t\tfor (i = 0; i < state->num_gpio_events; i++) {\n+\t\t\tgp_ev = &state->gpio_events[i];\n+\t\t\tinp_state = &gf->input_gpio_states[gp_ev->index];\n+\t\t\tif (inp_state->enabled) {\n+\t\t\t\tinp_state->enabled = false;\n+\t\t\t\tirq_set_irq_type(inp_state->irq,\n+\t\t\t\t\t\t IRQF_TRIGGER_NONE);\n+\t\t\t}\n+\t\t}\n+\t}\n+\n+\tif (new_state)\n+\t\tgpio_fsm_enter_state(gf, new_state);\n+}\n+\n+static irqreturn_t gpio_fsm_gpio_irq_handler(int irq, void *dev_id)\n+{\n+\tstruct input_gpio_state *inp_state = dev_id;\n+\tstruct gpio_fsm *gf = inp_state->gf;\n+\tstruct fsm_state *target;\n+\n+\ttarget = inp_state->target;\n+\tif (!target)\n+\t\treturn IRQ_NONE;\n+\n+\t/* If the IRQ has fired then the desired state _must_ have occurred */\n+\tinp_state->enabled = false;\n+\tirq_set_irq_type(inp_state->irq, IRQF_TRIGGER_NONE);\n+\tif (gf->debug)\n+\t\tdev_info(gf->dev, \"GF_IN %d->%d -> %s\\n\",\n+\t\t\t inp_state->index, inp_state->value, target->name);\n+\tgpio_fsm_go_to_state(gf, target);\n+\treturn IRQ_HANDLED;\n+}\n+\n+static void gpio_fsm_timer(struct timer_list *timer)\n+{\n+\tstruct gpio_fsm *gf = container_of(timer, struct gpio_fsm, timer);\n+\tstruct fsm_state *target;\n+\n+\ttarget = gf->delay_target_state;\n+\tif (!target)\n+\t\treturn;\n+\n+\tif (gf->debug)\n+\t\tdev_info(gf->dev, \"GF_DELAY %d -> %s\\n\", gf->delay_ms,\n+\t\t\t target->name);\n+\n+\tgpio_fsm_go_to_state(gf, target);\n+}\n+\n+int gpio_fsm_parse_signals(struct gpio_fsm *gf, struct fsm_state *state,\n+\t\t\t     struct property *prop)\n+{\n+\tconst __be32 *cells = prop->value;\n+\tstruct output_signal *signal;\n+\tu32 io;\n+\tu32 type;\n+\tu32 index;\n+\tu32 value;\n+\tint ret = 0;\n+\tint i;\n+\n+\tif (prop->length % 8) {\n+\t\tdev_err(gf->dev, \"malformed set in state %s\\n\",\n+\t\t\tstate->name);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tstate->num_signals = prop->length/8;\n+\tstate->signals = devm_kcalloc(gf->dev, state->num_signals,\n+\t\t\t\t      sizeof(struct output_signal),\n+\t\t\t\t      GFP_KERNEL);\n+\tfor (i = 0; i < state->num_signals; i++) {\n+\t\tsignal = &state->signals[i];\n+\t\tio = be32_to_cpu(cells[0]);\n+\t\ttype = GF_IO_TYPE(io);\n+\t\tindex = GF_IO_INDEX(io);\n+\t\tvalue = be32_to_cpu(cells[1]);\n+\n+\t\tif (type != GF_OUT && type != GF_SOFT) {\n+\t\t\tdev_err(gf->dev,\n+\t\t\t\t\"invalid set type %d in state %s\\n\",\n+\t\t\t\ttype, state->name);\n+\t\t\tret = -EINVAL;\n+\t\t\tbreak;\n+\t\t}\n+\t\tif (type == GF_OUT && index >= gf->num_output_gpios) {\n+\t\t\tdev_err(gf->dev,\n+\t\t\t\t\"invalid GF_OUT number %d in state %s\\n\",\n+\t\t\t\tindex, state->name);\n+\t\t\tret = -EINVAL;\n+\t\t\tbreak;\n+\t\t}\n+\t\tif (type == GF_SOFT && index >= gf->num_soft_gpios) {\n+\t\t\tdev_err(gf->dev,\n+\t\t\t\t\"invalid GF_SOFT number %d in state %s\\n\",\n+\t\t\t\tindex, state->name);\n+\t\t\tret = -EINVAL;\n+\t\t\tbreak;\n+\t\t}\n+\t\tif (value != 0 && value != 1) {\n+\t\t\tdev_err(gf->dev,\n+\t\t\t\t\"invalid set value %d in state %s\\n\",\n+\t\t\t\tvalue, state->name);\n+\t\t\tret = -EINVAL;\n+\t\t\tbreak;\n+\t\t}\n+\t\tsignal->type = (type == GF_OUT) ? SIGNAL_GPIO : SIGNAL_SOFT;\n+\t\tsignal->index = index;\n+\t\tsignal->value = value;\n+\t\tcells += 2;\n+\t}\n+\n+\treturn ret;\n+}\n+\n+struct gpio_event *new_event(struct gpio_event **events, int *num_events)\n+{\n+\tint num = ++(*num_events);\n+\t*events = krealloc(*events, num * sizeof(struct gpio_event),\n+\t\t\t   GFP_KERNEL);\n+\treturn *events ? *events + (num - 1) : NULL;\n+}\n+\n+int gpio_fsm_parse_events(struct gpio_fsm *gf, struct fsm_state *state,\n+\t\t\t    struct property *prop)\n+{\n+\tconst __be32 *cells = prop->value;\n+\tstruct symtab_entry *sym;\n+\tint num_cells;\n+\tint ret = 0;\n+\tint i;\n+\n+\tif (prop->length % 8) {\n+\t\tdev_err(gf->dev,\n+\t\t\t\"malformed transitions from state %s to state %s\\n\",\n+\t\t\tstate->name, prop->name);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tsym = get_symbol(&gf->symtab, prop->name);\n+\tnum_cells = prop->length / 4;\n+\ti = 0;\n+\twhile (i < num_cells) {\n+\t\tstruct gpio_event *gp_ev;\n+\t\tu32 event, param;\n+\t\tu32 index;\n+\n+\t\tevent = be32_to_cpu(cells[i++]);\n+\t\tparam = be32_to_cpu(cells[i++]);\n+\t\tindex = GF_IO_INDEX(event);\n+\n+\t\tswitch (GF_IO_TYPE(event)) {\n+\t\tcase GF_IN:\n+\t\t\tif (index >= gf->num_input_gpios) {\n+\t\t\t\tdev_err(gf->dev,\n+\t\t\t\t\t\"invalid GF_IN %d in transitions from state %s to state %s\\n\",\n+\t\t\t\t\tindex, state->name, prop->name);\n+\t\t\t\treturn -EINVAL;\n+\t\t\t}\n+\t\t\tif (param > 1) {\n+\t\t\t\tdev_err(gf->dev,\n+\t\t\t\t\t\"invalid GF_IN value %d in transitions from state %s to state %s\\n\",\n+\t\t\t\t\tparam, state->name, prop->name);\n+\t\t\t\treturn -EINVAL;\n+\t\t\t}\n+\t\t\tgp_ev = new_event(&state->gpio_events,\n+\t\t\t\t\t  &state->num_gpio_events);\n+\t\t\tif (!gp_ev)\n+\t\t\t\treturn -ENOMEM;\n+\t\t\tgp_ev->index = index;\n+\t\t\tgp_ev->value = param;\n+\t\t\tgp_ev->target = (struct fsm_state *)sym;\n+\t\t\tbreak;\n+\n+\t\tcase GF_SOFT:\n+\t\t\tif (index >= gf->num_soft_gpios) {\n+\t\t\t\tdev_err(gf->dev,\n+\t\t\t\t\t\"invalid GF_SOFT %d in transitions from state %s to state %s\\n\",\n+\t\t\t\t\tindex, state->name, prop->name);\n+\t\t\t\treturn -EINVAL;\n+\t\t\t}\n+\t\t\tif (param > 1) {\n+\t\t\t\tdev_err(gf->dev,\n+\t\t\t\t\t\"invalid GF_SOFT value %d in transitions from state %s to state %s\\n\",\n+\t\t\t\t\tparam, state->name, prop->name);\n+\t\t\t\treturn -EINVAL;\n+\t\t\t}\n+\t\t\tgp_ev = new_event(&state->soft_events,\n+\t\t\t\t\t  &state->num_soft_events);\n+\t\t\tif (!gp_ev)\n+\t\t\t\treturn -ENOMEM;\n+\t\t\tgp_ev->index = index;\n+\t\t\tgp_ev->value = param;\n+\t\t\tgp_ev->target = (struct fsm_state *)sym;\n+\t\t\tbreak;\n+\n+\t\tcase GF_DELAY:\n+\t\t\tif (state->delay_target) {\n+\t\t\t\tdev_err(gf->dev,\n+\t\t\t\t\t\"state %s has multiple GF_DELAYs\\n\",\n+\t\t\t\t\tstate->name);\n+\t\t\t\treturn -EINVAL;\n+\t\t\t}\n+\t\t\tstate->delay_target = (struct fsm_state *)sym;\n+\t\t\tstate->delay_ms = param;\n+\t\t\tbreak;\n+\n+\t\tcase GF_SHUTDOWN:\n+\t\t\tif (state->shutdown_target == state) {\n+\t\t\t\tdev_err(gf->dev,\n+\t\t\t\t\t\"shutdown state %s has GF_SHUTDOWN\\n\",\n+\t\t\t\t\tstate->name);\n+\t\t\t\treturn -EINVAL;\n+\t\t\t} else if (state->shutdown_target) {\n+\t\t\t\tdev_err(gf->dev,\n+\t\t\t\t\t\"state %s has multiple GF_SHUTDOWNs\\n\",\n+\t\t\t\t\tstate->name);\n+\t\t\t\treturn -EINVAL;\n+\t\t\t}\n+\t\t\tstate->shutdown_target =\n+\t\t\t\t(struct fsm_state *)sym;\n+\t\t\tstate->shutdown_ms = param;\n+\t\t\tbreak;\n+\n+\t\tdefault:\n+\t\t\tdev_err(gf->dev,\n+\t\t\t\t\"invalid event %08x in transitions from state %s to state %s\\n\",\n+\t\t\t\tevent, state->name, prop->name);\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t}\n+\tif (i != num_cells) {\n+\t\tdev_err(gf->dev,\n+\t\t\t\"malformed transitions from state %s to state %s\\n\",\n+\t\t\tstate->name, prop->name);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\treturn ret;\n+}\n+\n+int gpio_fsm_parse_state(struct gpio_fsm *gf,\n+\t\t\t   struct fsm_state *state,\n+\t\t\t   struct device_node *np)\n+{\n+\tstruct symtab_entry *sym;\n+\tstruct property *prop;\n+\tint ret;\n+\n+\tstate->name = np->name;\n+\tret = add_symbol(&gf->symtab, np->name, state);\n+\tif (ret) {\n+\t\tswitch (ret) {\n+\t\tcase -EINVAL:\n+\t\t\tdev_err(gf->dev, \"'%s' is not a valid state name\\n\",\n+\t\t\t\tnp->name);\n+\t\t\tbreak;\n+\t\tcase -EEXIST:\n+\t\t\tdev_err(gf->dev, \"state %s already defined\\n\",\n+\t\t\t\tnp->name);\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tdev_err(gf->dev, \"error %d adding state %s symbol\\n\",\n+\t\t\t\tret, np->name);\n+\t\t\tbreak;\n+\t\t}\n+\t\treturn ret;\n+\t}\n+\n+\tfor_each_property_of_node(np, prop) {\n+\t\tsym = get_symbol(&gf->symtab, prop->name);\n+\t\tif (!sym) {\n+\t\t\tret = -ENOMEM;\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\tswitch ((uintptr_t)sym->value) {\n+\t\tcase SYM_SET:\n+\t\t\tret = gpio_fsm_parse_signals(gf, state, prop);\n+\t\t\tbreak;\n+\t\tcase SYM_START:\n+\t\t\tif (gf->start_state) {\n+\t\t\t\tdev_err(gf->dev, \"multiple start states\\n\");\n+\t\t\t\tret = -EINVAL;\n+\t\t\t} else {\n+\t\t\t\tgf->start_state = state;\n+\t\t\t}\n+\t\t\tbreak;\n+\t\tcase SYM_SHUTDOWN:\n+\t\t\tstate->shutdown_target = state;\n+\t\t\tgf->shutdown_state = state;\n+\t\t\tbreak;\n+\t\tcase SYM_NAME:\n+\t\t\t/* Ignore */\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\t/* A set of transition events to this state */\n+\t\t\tret = gpio_fsm_parse_events(gf, state, prop);\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\n+\treturn ret;\n+}\n+\n+static void dump_all(struct gpio_fsm *gf)\n+{\n+\tint i, j;\n+\n+\tdev_info(gf->dev, \"Input GPIOs:\\n\");\n+\tfor (i = 0; i < gf->num_input_gpios; i++)\n+\t\tdev_info(gf->dev, \"  %d: %p\\n\", i,\n+\t\t\t gf->input_gpios->desc[i]);\n+\n+\tdev_info(gf->dev, \"Output GPIOs:\\n\");\n+\tfor (i = 0; i < gf->num_output_gpios; i++)\n+\t\tdev_info(gf->dev, \"  %d: %p\\n\", i,\n+\t\t\t gf->output_gpios->desc[i]);\n+\n+\tdev_info(gf->dev, \"Soft GPIOs:\\n\");\n+\tfor (i = 0; i < gf->num_soft_gpios; i++)\n+\t\tdev_info(gf->dev, \"  %d: %s %d\\n\", i,\n+\t\t\t (gf->soft_gpios[i].dir == GPIOF_DIR_IN) ? \"IN\" : \"OUT\",\n+\t\t\t gf->soft_gpios[i].value);\n+\n+\tdev_info(gf->dev, \"Start state: %s\\n\",\n+\t\t gf->start_state ? gf->start_state->name : \"-\");\n+\n+\tdev_info(gf->dev, \"Shutdown timeout: %d ms\\n\",\n+\t\t gf->shutdown_timeout_ms);\n+\n+\tfor (i = 0; i < gf->num_states; i++) {\n+\t\tstruct fsm_state *state = &gf->states[i];\n+\n+\t\tdev_info(gf->dev, \"State %s:\\n\", state->name);\n+\n+\t\tif (state->shutdown_target == state)\n+\t\t\tdev_info(gf->dev, \"  Shutdown state\\n\");\n+\n+\t\tdev_info(gf->dev, \"  Signals:\\n\");\n+\t\tfor (j = 0; j < state->num_signals; j++) {\n+\t\t\tstruct output_signal *signal = &state->signals[j];\n+\n+\t\t\tdev_info(gf->dev, \"    %d: %s %d=%d\\n\", j,\n+\t\t\t\t (signal->type == SIGNAL_GPIO) ? \"GPIO\" :\n+\t\t\t\t\t\t\t\t \"SOFT\",\n+\t\t\t\t signal->index, signal->value);\n+\t\t}\n+\n+\t\tdev_info(gf->dev, \"  GPIO events:\\n\");\n+\t\tfor (j = 0; j < state->num_gpio_events; j++) {\n+\t\t\tstruct gpio_event *event = &state->gpio_events[j];\n+\n+\t\t\tdev_info(gf->dev, \"    %d: %d=%d -> %s\\n\", j,\n+\t\t\t\t event->index, event->value,\n+\t\t\t\t event->target->name);\n+\t\t}\n+\n+\t\tdev_info(gf->dev, \"  Soft events:\\n\");\n+\t\tfor (j = 0; j < state->num_soft_events; j++) {\n+\t\t\tstruct gpio_event *event = &state->soft_events[j];\n+\n+\t\t\tdev_info(gf->dev, \"    %d: %d=%d -> %s\\n\", j,\n+\t\t\t\t event->index, event->value,\n+\t\t\t\t event->target->name);\n+\t\t}\n+\n+\t\tif (state->delay_target)\n+\t\t\tdev_info(gf->dev, \"  Delay: %d ms -> %s\\n\",\n+\t\t\t\t state->delay_ms, state->delay_target->name);\n+\n+\t\tif (state->shutdown_target && state->shutdown_target != state)\n+\t\t\tdev_info(gf->dev, \"  Shutdown: %d ms -> %s\\n\",\n+\t\t\t\t state->shutdown_ms,\n+\t\t\t\t state->shutdown_target->name);\n+\t}\n+\tdev_info(gf->dev, \"\\n\");\n+}\n+\n+static int resolve_sym_to_state(struct gpio_fsm *gf, struct fsm_state **pstate)\n+{\n+\tstruct symtab_entry *sym = (struct symtab_entry *)*pstate;\n+\n+\tif (!sym)\n+\t\treturn -ENOMEM;\n+\n+\t*pstate = sym->value;\n+\n+\tif (!*pstate) {\n+\t\tdev_err(gf->dev, \"state %s not defined\\n\",\n+\t\t\tsym->name);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int gpio_fsm_probe(struct platform_device *pdev)\n+{\n+\tstruct input_gpio_state *inp_state;\n+\tstruct device *dev = &pdev->dev;\n+\tstruct device_node *np = dev->of_node;\n+\tstruct device_node *cp;\n+\tstruct gpio_fsm *gf;\n+\tu32 debug = 0;\n+\tint num_states;\n+\tu32 num_soft_gpios;\n+\tint ret;\n+\tint i;\n+\tstatic const char *const reserved_symbols[] = {\n+\t\t[SYM_NAME] = \"name\",\n+\t\t[SYM_SET] = \"set\",\n+\t\t[SYM_START] = \"start_state\",\n+\t\t[SYM_SHUTDOWN] = \"shutdown_state\",\n+\t};\n+\n+\tif (of_property_read_u32(np, \"num-soft-gpios\", &num_soft_gpios)) {\n+\t\tdev_err(dev, \"missing 'num-soft-gpios' property\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tof_property_read_u32(np, \"debug\", &debug);\n+\n+\tgf = devm_kzalloc(dev, sizeof(*gf), GFP_KERNEL);\n+\tif (!gf)\n+\t\treturn -ENOMEM;\n+\n+\tgf->dev = dev;\n+\tgf->debug = debug;\n+\n+\tif (of_property_read_u32(np, \"shutdown-timeout-ms\",\n+\t\t\t\t &gf->shutdown_timeout_ms))\n+\t\tgf->shutdown_timeout_ms = 5000;\n+\n+\tgf->num_soft_gpios = num_soft_gpios;\n+\tgf->soft_gpios = devm_kcalloc(dev, num_soft_gpios,\n+\t\t\t\t      sizeof(struct soft_gpio), GFP_KERNEL);\n+\tif (!gf->soft_gpios)\n+\t\treturn -ENOMEM;\n+\tfor (i = 0; i < num_soft_gpios; i++) {\n+\t\tstruct soft_gpio *sg = &gf->soft_gpios[i];\n+\n+\t\tsg->dir = GPIOF_DIR_IN;\n+\t\tsg->value = 0;\n+\t}\n+\n+\tgf->input_gpios = devm_gpiod_get_array_optional(dev, \"input\", GPIOD_IN);\n+\tif (IS_ERR(gf->input_gpios)) {\n+\t\tret = PTR_ERR(gf->input_gpios);\n+\t\tdev_err(dev, \"failed to get input gpios from DT - %d\\n\", ret);\n+\t\treturn ret;\n+\t}\n+\tgf->num_input_gpios = (gf->input_gpios ? gf->input_gpios->ndescs : 0);\n+\n+\tgf->input_gpio_states = devm_kcalloc(dev, gf->num_input_gpios,\n+\t\t\t\t\t     sizeof(struct input_gpio_state),\n+\t\t\t\t\t     GFP_KERNEL);\n+\tif (!gf->input_gpio_states)\n+\t\treturn -ENOMEM;\n+\tfor (i = 0; i < gf->num_input_gpios; i++) {\n+\t\tinp_state = &gf->input_gpio_states[i];\n+\t\tinp_state->desc = gf->input_gpios->desc[i];\n+\t\tinp_state->gf = gf;\n+\t\tinp_state->index = i;\n+\t\tinp_state->irq = gpiod_to_irq(inp_state->desc);\n+\t\tinp_state->active_low = gpiod_is_active_low(inp_state->desc);\n+\t\tif (inp_state->irq >= 0)\n+\t\t\tret = devm_request_irq(gf->dev, inp_state->irq,\n+\t\t\t\t\t       gpio_fsm_gpio_irq_handler,\n+\t\t\t\t\t       IRQF_TRIGGER_NONE,\n+\t\t\t\t\t       dev_name(dev),\n+\t\t\t\t\t       inp_state);\n+\t\telse\n+\t\t\tret = inp_state->irq;\n+\n+\t\tif (ret) {\n+\t\t\tdev_err(dev,\n+\t\t\t\t\"failed to get IRQ for input gpio - %d\\n\",\n+\t\t\t\tret);\n+\t\t\treturn ret;\n+\t\t}\n+\t}\n+\n+\tgf->output_gpios = devm_gpiod_get_array_optional(dev, \"output\",\n+\t\t\t\t\t\t\t GPIOD_OUT_LOW);\n+\tif (IS_ERR(gf->output_gpios)) {\n+\t\tret = PTR_ERR(gf->output_gpios);\n+\t\tdev_err(dev, \"failed to get output gpios from DT - %d\\n\", ret);\n+\t\treturn ret;\n+\t}\n+\tgf->num_output_gpios = (gf->output_gpios ? gf->output_gpios->ndescs :\n+\t\t\t\t0);\n+\n+\tnum_states = of_get_child_count(np);\n+\tif (!num_states) {\n+\t\tdev_err(dev, \"no states declared\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\tgf->states = devm_kcalloc(dev, num_states,\n+\t\t\t\t  sizeof(struct fsm_state), GFP_KERNEL);\n+\tif (!gf->states)\n+\t\treturn -ENOMEM;\n+\n+\t// add reserved words to the symbol table\n+\tfor (i = 0; i < ARRAY_SIZE(reserved_symbols); i++) {\n+\t\tif (reserved_symbols[i])\n+\t\t\tadd_symbol(&gf->symtab, reserved_symbols[i], (void *)i);\n+\t}\n+\n+\t// parse the state\n+\tfor_each_child_of_node(np, cp) {\n+\t\tstruct fsm_state *state = &gf->states[gf->num_states];\n+\n+\t\tret = gpio_fsm_parse_state(gf, state, cp);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\t\tgf->num_states++;\n+\t}\n+\n+\tif (!gf->start_state) {\n+\t\tdev_err(gf->dev, \"no start state defined\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\t// resolve symbol pointers into state pointers\n+\tfor (i = 0; !ret && i < gf->num_states; i++) {\n+\t\tstruct fsm_state *state = &gf->states[i];\n+\t\tint j;\n+\n+\t\tfor (j = 0; !ret && j < state->num_gpio_events; j++) {\n+\t\t\tstruct gpio_event *ev = &state->gpio_events[j];\n+\n+\t\t\tret = resolve_sym_to_state(gf, &ev->target);\n+\t\t}\n+\n+\t\tfor (j = 0; !ret && j < state->num_soft_events; j++) {\n+\t\t\tstruct gpio_event *ev = &state->soft_events[j];\n+\n+\t\t\tret = resolve_sym_to_state(gf, &ev->target);\n+\t\t}\n+\n+\t\tif (!ret) {\n+\t\t\tresolve_sym_to_state(gf, &state->delay_target);\n+\t\t\tif (state->shutdown_target != state)\n+\t\t\t\tresolve_sym_to_state(gf,\n+\t\t\t\t\t\t     &state->shutdown_target);\n+\t\t}\n+\t}\n+\n+\tif (!ret && gf->debug > 1)\n+\t\tdump_all(gf);\n+\n+\tfree_symbols(&gf->symtab);\n+\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tgf->gc.parent = dev;\n+\tgf->gc.label = np->name;\n+\tgf->gc.owner = THIS_MODULE;\n+\tgf->gc.of_node = np;\n+\tgf->gc.base = -1;\n+\tgf->gc.ngpio = num_soft_gpios;\n+\n+\tgf->gc.get_direction = gpio_fsm_get_direction;\n+\tgf->gc.direction_input = gpio_fsm_direction_input;\n+\tgf->gc.direction_output = gpio_fsm_direction_output;\n+\tgf->gc.get = gpio_fsm_get;\n+\tgf->gc.set = gpio_fsm_set;\n+\tgf->gc.can_sleep = true;\n+\tspin_lock_init(&gf->spinlock);\n+\tINIT_WORK(&gf->work, gpio_fsm_work);\n+\ttimer_setup(&gf->timer, gpio_fsm_timer, 0);\n+\tinit_waitqueue_head(&gf->shutdown_event);\n+\n+\tplatform_set_drvdata(pdev, gf);\n+\n+\tif (gf->debug)\n+\t\tdev_info(gf->dev, \"Start -> %s\\n\", gf->start_state->name);\n+\n+\tgpio_fsm_go_to_state(gf, gf->start_state);\n+\n+\treturn devm_gpiochip_add_data(dev, &gf->gc, gf);\n+}\n+\n+static int gpio_fsm_remove(struct platform_device *pdev)\n+{\n+\tstruct gpio_fsm *gf = platform_get_drvdata(pdev);\n+\tint i;\n+\n+\tif (gf->shutdown_state) {\n+\t\tif (gf->debug)\n+\t\t\tdev_info(gf->dev, \"Shutting down...\\n\");\n+\n+\t\tspin_lock(&gf->spinlock);\n+\t\tgf->shutting_down = true;\n+\t\tif (gf->current_state->shutdown_target &&\n+\t\t    gf->current_state->shutdown_target != gf->current_state) {\n+\t\t\tgf->delay_target_state =\n+\t\t\t\tgf->current_state->shutdown_target;\n+\t\t\tmod_timer(&gf->timer, gf->shutdown_jiffies);\n+\t\t}\n+\t\tspin_unlock(&gf->spinlock);\n+\n+\t\twait_event_timeout(gf->shutdown_event,\n+\t\t\t\t   gf->current_state->shutdown_target ==\n+\t\t\t\t   gf->current_state,\n+\t\t\t\t   msecs_to_jiffies(gf->shutdown_timeout_ms));\n+\t\tif (gf->current_state->shutdown_target == gf->current_state)\n+\t\t\tgpio_fsm_enter_state(gf, gf->shutdown_state);\n+\t}\n+\tcancel_work_sync(&gf->work);\n+\tdel_timer_sync(&gf->timer);\n+\n+\t/* Events aren't allocated from managed storage */\n+\tfor (i = 0; i < gf->num_states; i++) {\n+\t\tkfree(gf->states[i].gpio_events);\n+\t\tkfree(gf->states[i].soft_events);\n+\t}\n+\tif (gf->debug)\n+\t\tdev_info(gf->dev, \"Exiting\\n\");\n+\n+\treturn 0;\n+}\n+\n+static void gpio_fsm_shutdown(struct platform_device *pdev)\n+{\n+\tgpio_fsm_remove(pdev);\n+}\n+\n+static const struct of_device_id gpio_fsm_ids[] = {\n+\t{ .compatible = \"rpi,gpio-fsm\" },\n+\t{ }\n+};\n+MODULE_DEVICE_TABLE(of, gpio_fsm_ids);\n+\n+static struct platform_driver gpio_fsm_driver = {\n+\t.driver\t= {\n+\t\t.name\t\t= MODULE_NAME,\n+\t\t.of_match_table\t= of_match_ptr(gpio_fsm_ids),\n+\t},\n+\t.probe = gpio_fsm_probe,\n+\t.remove = gpio_fsm_remove,\n+\t.shutdown = gpio_fsm_shutdown,\n+};\n+module_platform_driver(gpio_fsm_driver);\n+\n+MODULE_LICENSE(\"GPL\");\n+MODULE_AUTHOR(\"Phil Elwell <phil@raspberrypi.com>\");\n+MODULE_DESCRIPTION(\"GPIO FSM driver\");\n+MODULE_ALIAS(\"platform:gpio-fsm\");\n--- /dev/null\n+++ b/include/dt-bindings/gpio/gpio-fsm.h\n@@ -0,0 +1,21 @@\n+/* SPDX-License-Identifier: GPL-2.0+ */\n+/*\n+ * This header provides constants for binding rpi,gpio-fsm.\n+ */\n+\n+#ifndef _DT_BINDINGS_GPIO_FSM_H\n+#define _DT_BINDINGS_GPIO_FSM_H\n+\n+#define GF_IN       0\n+#define GF_OUT      1\n+#define GF_SOFT     2\n+#define GF_DELAY    3\n+#define GF_SHUTDOWN 4\n+\n+#define GF_IO(t, v) (((v) << 16) | ((t) & 0xffff))\n+\n+#define GF_IP(x)    GF_IO(GF_IN, (x))\n+#define GF_OP(x)    GF_IO(GF_OUT, (x))\n+#define GF_SW(x)    GF_IO(GF_SOFT, (x))\n+\n+#endif\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0349-drm-vc4-Add-all-the-HDMI-registers-into-the-debugfs-.patch",
    "content": "From ef65a6f064b3bd497d83b0f40908182ba2a2b863 Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Wed, 21 Oct 2020 18:34:56 +0100\nSubject: [PATCH] drm/vc4: Add all the HDMI registers into the debugfs\n dumps\n\nThe vc5 HDMI registers hadn't been added into the debugfs\nregister sets, therefore weren't dumped on request.\nAdd them in.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n drivers/gpu/drm/vc4/vc4_hdmi.c | 44 ++++++++++++++++++++++++++++++++++\n drivers/gpu/drm/vc4/vc4_hdmi.h |  9 +++++++\n 2 files changed, 53 insertions(+)\n\n--- a/drivers/gpu/drm/vc4/vc4_hdmi.c\n+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c\n@@ -92,6 +92,12 @@ static int vc4_hdmi_debugfs_regs(struct\n \n \tdrm_print_regset32(&p, &vc4_hdmi->hdmi_regset);\n \tdrm_print_regset32(&p, &vc4_hdmi->hd_regset);\n+\tdrm_print_regset32(&p, &vc4_hdmi->cec_regset);\n+\tdrm_print_regset32(&p, &vc4_hdmi->csc_regset);\n+\tdrm_print_regset32(&p, &vc4_hdmi->dvp_regset);\n+\tdrm_print_regset32(&p, &vc4_hdmi->phy_regset);\n+\tdrm_print_regset32(&p, &vc4_hdmi->ram_regset);\n+\tdrm_print_regset32(&p, &vc4_hdmi->rm_regset);\n \n \treturn 0;\n }\n@@ -1734,6 +1740,7 @@ static int vc5_hdmi_init_resources(struc\n \tstruct platform_device *pdev = vc4_hdmi->pdev;\n \tstruct device *dev = &pdev->dev;\n \tstruct resource *res;\n+\tint ret;\n \n \tres = platform_get_resource_byname(pdev, IORESOURCE_MEM, \"hdmi\");\n \tif (!res)\n@@ -1824,6 +1831,38 @@ static int vc5_hdmi_init_resources(struc\n \t\treturn PTR_ERR(vc4_hdmi->reset);\n \t}\n \n+\tret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->cec_regset, VC5_CEC);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->csc_regset, VC5_CSC);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->dvp_regset, VC5_DVP);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->phy_regset, VC5_PHY);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->ram_regset, VC5_RAM);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->rm_regset, VC5_RM);\n+\tif (ret)\n+\t\treturn ret;\n+\n \treturn 0;\n }\n \n--- a/drivers/gpu/drm/vc4/vc4_hdmi.h\n+++ b/drivers/gpu/drm/vc4/vc4_hdmi.h\n@@ -161,8 +161,16 @@ struct vc4_hdmi {\n \n \tstruct reset_control *reset;\n \n+\t/* Common debugfs regset */\n \tstruct debugfs_regset32 hdmi_regset;\n \tstruct debugfs_regset32 hd_regset;\n+\t/* VC5 debugfs regset */\n+\tstruct debugfs_regset32 cec_regset;\n+\tstruct debugfs_regset32 csc_regset;\n+\tstruct debugfs_regset32 dvp_regset;\n+\tstruct debugfs_regset32 phy_regset;\n+\tstruct debugfs_regset32 ram_regset;\n+\tstruct debugfs_regset32 rm_regset;\n };\n \n static inline struct vc4_hdmi *\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0350-ARM-dts-bcm271x-Use-a53-pmu-drop-RPI364.patch",
    "content": "From 97a2cff029c6c8f7f2550935e6110b81c69bc34a Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.com>\nDate: Thu, 19 Mar 2020 10:04:46 +0000\nSubject: [PATCH] ARM: dts: bcm271x: Use a53 pmu, drop RPI364\n\nThe upstream bcm2837.dtsi uses cortex-a53-pmu, so we can do the same\nbut with a fallback to the cortex-a7-pmu which is supported by the\n32-bit kernel.\n\nNow that we're using the natural fallback mechanism of compatible\nstrings, the RPI364 macro no longer serves any purpose - remove it.\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.com>\n---\n arch/arm/boot/dts/bcm2710.dtsi                        | 6 +-----\n arch/arm64/boot/dts/broadcom/bcm2710-rpi-2-b.dts      | 2 --\n arch/arm64/boot/dts/broadcom/bcm2710-rpi-3-b-plus.dts | 2 --\n arch/arm64/boot/dts/broadcom/bcm2710-rpi-3-b.dts      | 2 --\n arch/arm64/boot/dts/broadcom/bcm2710-rpi-cm3.dts      | 2 --\n arch/arm64/boot/dts/broadcom/bcm2711-rpi-4-b.dts      | 2 --\n 6 files changed, 1 insertion(+), 15 deletions(-)\n\n--- a/arch/arm/boot/dts/bcm2710.dtsi\n+++ b/arch/arm/boot/dts/bcm2710.dtsi\n@@ -5,11 +5,7 @@\n \tcompatible = \"brcm,bcm2837\", \"brcm,bcm2836\";\n \n \tarm-pmu {\n-#ifdef RPI364\n-\t\tcompatible = \"arm,armv8-pmuv3\", \"arm,cortex-a7-pmu\";\n-#else\n-\t\tcompatible = \"arm,cortex-a7-pmu\";\n-#endif\n+\t\tcompatible = \"arm,cortex-a53-pmu\", \"arm,cortex-a7-pmu\";\n \t};\n \n \tsoc {\n--- a/arch/arm64/boot/dts/broadcom/bcm2710-rpi-2-b.dts\n+++ b/arch/arm64/boot/dts/broadcom/bcm2710-rpi-2-b.dts\n@@ -1,3 +1 @@\n-#define RPI364\n-\n #include \"../../../../arm/boot/dts/bcm2710-rpi-2-b.dts\"\n--- a/arch/arm64/boot/dts/broadcom/bcm2710-rpi-3-b-plus.dts\n+++ b/arch/arm64/boot/dts/broadcom/bcm2710-rpi-3-b-plus.dts\n@@ -1,3 +1 @@\n-#define RPI364\n-\n #include \"../../../../arm/boot/dts/bcm2710-rpi-3-b-plus.dts\"\n--- a/arch/arm64/boot/dts/broadcom/bcm2710-rpi-3-b.dts\n+++ b/arch/arm64/boot/dts/broadcom/bcm2710-rpi-3-b.dts\n@@ -1,3 +1 @@\n-#define RPI364\n-\n #include \"../../../../arm/boot/dts/bcm2710-rpi-3-b.dts\"\n--- a/arch/arm64/boot/dts/broadcom/bcm2710-rpi-cm3.dts\n+++ b/arch/arm64/boot/dts/broadcom/bcm2710-rpi-cm3.dts\n@@ -1,3 +1 @@\n-#define RPI364\n-\n #include \"../../../../arm/boot/dts/bcm2710-rpi-cm3.dts\"\n--- a/arch/arm64/boot/dts/broadcom/bcm2711-rpi-4-b.dts\n+++ b/arch/arm64/boot/dts/broadcom/bcm2711-rpi-4-b.dts\n@@ -1,3 +1 @@\n-#define RPI364\n-\n #include \"../../../../arm/boot/dts/bcm2711-rpi-4-b.dts\"\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0351-overlays-Add-option-to-disable-composite-to-vc4-kms-.patch",
    "content": "From 8c4205446ace4f14ec8725d11f46b570e9bc1fd3 Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Fri, 23 Oct 2020 14:15:41 +0100\nSubject: [PATCH] overlays: Add option to disable composite to\n vc4-kms-v3d\n\nComposite gets enabled automatically if HDMI isn't detected,\nwhich can cause some grief in X should it be not connected\nand touchscreens are in use.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n arch/arm/boot/dts/overlays/README                  | 2 ++\n arch/arm/boot/dts/overlays/vc4-kms-v3d-overlay.dts | 1 +\n 2 files changed, 3 insertions(+)\n\n--- a/arch/arm/boot/dts/overlays/README\n+++ b/arch/arm/boot/dts/overlays/README\n@@ -2949,6 +2949,8 @@ Params: cma-512                 CMA is 5\n         cma-default             Use upstream's default value\n         audio                   Enable or disable audio over HDMI (default \"on\")\n         noaudio                 Disable all HDMI audio (default \"off\")\n+        nocomposite             Disable the composite video output (default\n+                                \"off\")\n \n \n Name:   vc4-kms-v3d-pi4\n--- a/arch/arm/boot/dts/overlays/vc4-kms-v3d-overlay.dts\n+++ b/arch/arm/boot/dts/overlays/vc4-kms-v3d-overlay.dts\n@@ -118,5 +118,6 @@\n \t__overrides__ {\n \t\taudio   = <0>,\"!13\", <0>,\"=14\";\n \t\tnoaudio = <0>,\"=13\", <0>,\"!14\";\n+\t\tnocomposite = <0>, \"!11\";\n \t};\n };\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0352-overlays-imx219-Correct-link-frequency-to-match-the-.patch",
    "content": "From 7ba47043d428bce18161417f134ca6492d097744 Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Wed, 11 Mar 2020 12:07:57 +0000\nSubject: [PATCH] overlays: imx219: Correct link frequency to match the\n upstream driver\n\nThe upstream driver is checking the link frequency parameter, and\nthe overlay had the wrong value.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n arch/arm/boot/dts/overlays/imx219-overlay.dts | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/arch/arm/boot/dts/overlays/imx219-overlay.dts\n+++ b/arch/arm/boot/dts/overlays/imx219-overlay.dts\n@@ -36,7 +36,7 @@\n \t\t\t\t\t\tdata-lanes = <1 2>;\n \t\t\t\t\t\tclock-noncontinuous;\n \t\t\t\t\t\tlink-frequencies =\n-\t\t\t\t\t\t\t/bits/ 64 <297000000>;\n+\t\t\t\t\t\t\t/bits/ 64 <456000000>;\n \t\t\t\t\t};\n \t\t\t\t};\n \t\t\t};\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0353-dts-Add-CM4-to-arm64-dt-files.patch",
    "content": "From aa9f4bd2a82bc227bc5d11939ad3cacb7a2663e6 Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Fri, 23 Oct 2020 15:45:11 +0100\nSubject: [PATCH] dts: Add CM4 to arm64 dt files\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n arch/arm64/boot/dts/broadcom/Makefile            | 3 ++-\n arch/arm64/boot/dts/broadcom/bcm2711-rpi-cm4.dts | 1 +\n 2 files changed, 3 insertions(+), 1 deletion(-)\n create mode 100644 arch/arm64/boot/dts/broadcom/bcm2711-rpi-cm4.dts\n\n--- a/arch/arm64/boot/dts/broadcom/Makefile\n+++ b/arch/arm64/boot/dts/broadcom/Makefile\n@@ -7,7 +7,8 @@ dtb-$(CONFIG_ARCH_BCM2709) += bcm2710-rp\n dtb-$(CONFIG_ARCH_BCM2709) += bcm2710-rpi-3-b.dtb\n dtb-$(CONFIG_ARCH_BCM2835) += bcm2710-rpi-2-b.dtb\n dtb-$(CONFIG_ARCH_BCM2835) += bcm2710-rpi-3-b.dtb\n-dtb-$(CONFIG_ARCH_BCM2835) += bcm2711-rpi-4-b.dtb\n+dtb-$(CONFIG_ARCH_BCM2835) += bcm2711-rpi-4-b.dtb \\\n+\t\t\t      bcm2711-rpi-cm4.dtb\n dtb-$(CONFIG_ARCH_BCM2835) += bcm2710-rpi-3-b-plus.dtb\n dtb-$(CONFIG_ARCH_BCM2709) += bcm2710-rpi-cm3.dtb\n dtb-$(CONFIG_ARCH_BCM2835) += bcm2710-rpi-cm3.dtb\n--- /dev/null\n+++ b/arch/arm64/boot/dts/broadcom/bcm2711-rpi-cm4.dts\n@@ -0,0 +1 @@\n+#include \"../../../../arm/boot/dts/bcm2711-rpi-cm4.dts\"\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0354-drm-vc4-Add-the-2711-HVS-as-a-suitable-DMA-node.patch",
    "content": "From 2b8894c7231f02a03e13c1785ed706471d511f8d Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Mon, 26 Oct 2020 12:38:27 +0000\nSubject: [PATCH] drm/vc4: Add the 2711 HVS as a suitable DMA node\n\nWith vc4-drv node not being under /soc on Pi4, we need to\nadopt the correct DMA parameters from a suitable sub-component.\nAdd \"brcm,bcm2711-hvs\" to that list of components.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n drivers/gpu/drm/vc4/vc4_drv.c | 1 +\n 1 file changed, 1 insertion(+)\n\n--- a/drivers/gpu/drm/vc4/vc4_drv.c\n+++ b/drivers/gpu/drm/vc4/vc4_drv.c\n@@ -248,6 +248,7 @@ static void vc4_match_add_drivers(struct\n \n const struct of_device_id vc4_dma_range_matches[] = {\n \t{ .compatible = \"brcm,bcm2835-hvs\" },\n+\t{ .compatible = \"brcm,bcm2711-hvs\" },\n \t{ .compatible = \"raspberrypi,rpi-firmware-kms\" },\n \t{ .compatible = \"brcm,bcm2835-v3d\" },\n \t{ .compatible = \"brcm,cygnus-v3d\" },\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0355-xhci-quirks-add-link-TRB-quirk-for-VL805.patch",
    "content": "From be6ae78e28ff92b6da6af988f3013420af957481 Mon Sep 17 00:00:00 2001\nFrom: Jonathan Bell <jonathan@raspberrypi.org>\nDate: Mon, 26 Oct 2020 14:03:35 +0000\nSubject: [PATCH] xhci: quirks: add link TRB quirk for VL805\n\nThe VL805 controller can't cope with the TR Dequeue Pointer for an endpoint\nbeing set to a Link TRB. The hardware-maintained endpoint context ends up\nstuck at the address of the Link TRB, leading to erroneous ring expansion\nevents whenever the enqueue pointer wraps to the dequeue position.\n\nIf the search for the end of the current TD and ring cycle state lands on\na Link TRB, move to the next segment.\n\nSee: https://github.com/raspberrypi/linux/issues/3919\n\nSigned-off-by: Jonathan Bell <jonathan@raspberrypi.com>\n---\n drivers/usb/host/xhci-pci.c  |  1 +\n drivers/usb/host/xhci-ring.c | 10 ++++++++++\n drivers/usb/host/xhci.h      |  1 +\n 3 files changed, 12 insertions(+)\n\n--- a/drivers/usb/host/xhci-pci.c\n+++ b/drivers/usb/host/xhci-pci.c\n@@ -291,6 +291,7 @@ static void xhci_pci_quirks(struct devic\n \tif (pdev->vendor == PCI_VENDOR_ID_VIA && pdev->device == 0x3483) {\n \t\txhci->quirks |= XHCI_LPM_SUPPORT;\n \t\txhci->quirks |= XHCI_EP_CTX_BROKEN_DCS;\n+\t\txhci->quirks |= XHCI_AVOID_DQ_ON_LINK;\n \t}\n \n \tif (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&\n--- a/drivers/usb/host/xhci-ring.c\n+++ b/drivers/usb/host/xhci-ring.c\n@@ -666,6 +666,16 @@ void xhci_find_new_dequeue_state(struct\n \n \t} while (!cycle_found || !td_last_trb_found);\n \n+\t/*\n+\t * Quirk: the xHC does not correctly parse link TRBs if the HW Dequeue\n+\t * pointer is set to one. Advance to the next TRB (and next segment).\n+\t */\n+\tif (xhci->quirks & XHCI_AVOID_DQ_ON_LINK && trb_is_link(new_deq)) {\n+\t\tif (link_trb_toggles_cycle(new_deq))\n+\t\t\tstate->new_cycle_state ^= 0x1;\n+\t\tnext_trb(xhci, ep_ring, &new_seg, &new_deq);\n+\t}\n+\n \tstate->new_deq_seg = new_seg;\n \tstate->new_deq_ptr = new_deq;\n \n--- a/drivers/usb/host/xhci.h\n+++ b/drivers/usb/host/xhci.h\n@@ -1888,6 +1888,7 @@ struct xhci_hcd {\n #define XHCI_SG_TRB_CACHE_SIZE_QUIRK\tBIT_ULL(39)\n #define XHCI_NO_SOFT_RETRY\tBIT_ULL(40)\n #define XHCI_EP_CTX_BROKEN_DCS\tBIT_ULL(42)\n+#define XHCI_AVOID_DQ_ON_LINK\tBIT_ULL(43)\n \n \tunsigned int\t\tnum_active_eps;\n \tunsigned int\t\tlimit_active_eps;\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0356-dts-Tidy-the-Raspberry-Pi-Makefile-entries.patch",
    "content": "From 8364d0445bde9900c7ef8e6f6d4ba2642dca0807 Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.com>\nDate: Mon, 26 Oct 2020 15:01:21 +0000\nSubject: [PATCH] dts: Tidy the Raspberry Pi Makefile entries\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.com>\n---\n arch/arm/boot/dts/Makefile            | 2 +-\n arch/arm64/boot/dts/broadcom/Makefile | 7 ++-----\n 2 files changed, 3 insertions(+), 6 deletions(-)\n\n--- a/arch/arm/boot/dts/Makefile\n+++ b/arch/arm/boot/dts/Makefile\n@@ -10,8 +10,8 @@ dtb-$(CONFIG_ARCH_BCM2835) += \\\n \tbcm2709-rpi-2-b.dtb \\\n \tbcm2710-rpi-2-b.dtb \\\n \tbcm2710-rpi-3-b.dtb \\\n-\tbcm2711-rpi-4-b.dtb \\\n \tbcm2710-rpi-3-b-plus.dtb \\\n+\tbcm2711-rpi-4-b.dtb \\\n \tbcm2710-rpi-cm3.dtb \\\n \tbcm2711-rpi-cm4.dtb\n \n--- a/arch/arm64/boot/dts/broadcom/Makefile\n+++ b/arch/arm64/boot/dts/broadcom/Makefile\n@@ -3,15 +3,12 @@ dtb-$(CONFIG_ARCH_BCM2835) += bcm2837-rp\n \t\t\t      bcm2837-rpi-3-b.dtb \\\n \t\t\t      bcm2837-rpi-3-b-plus.dtb \\\n \t\t\t      bcm2837-rpi-cm3-io3.dtb\n-dtb-$(CONFIG_ARCH_BCM2709) += bcm2710-rpi-2-b.dtb\n-dtb-$(CONFIG_ARCH_BCM2709) += bcm2710-rpi-3-b.dtb\n dtb-$(CONFIG_ARCH_BCM2835) += bcm2710-rpi-2-b.dtb\n dtb-$(CONFIG_ARCH_BCM2835) += bcm2710-rpi-3-b.dtb\n-dtb-$(CONFIG_ARCH_BCM2835) += bcm2711-rpi-4-b.dtb \\\n-\t\t\t      bcm2711-rpi-cm4.dtb\n dtb-$(CONFIG_ARCH_BCM2835) += bcm2710-rpi-3-b-plus.dtb\n-dtb-$(CONFIG_ARCH_BCM2709) += bcm2710-rpi-cm3.dtb\n+dtb-$(CONFIG_ARCH_BCM2835) += bcm2711-rpi-4-b.dtb\n dtb-$(CONFIG_ARCH_BCM2835) += bcm2710-rpi-cm3.dtb\n+dtb-$(CONFIG_ARCH_BCM2835) += bcm2711-rpi-cm4.dtb\n \n subdir-y\t+= northstar2\n subdir-y\t+= stingray\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0357-staging-bcm2835-audio-Add-disable-headphones-flag.patch",
    "content": "From 833b2341a6db499638d404de283a1b3c3a2a225f Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.com>\nDate: Mon, 26 Oct 2020 10:23:22 +0000\nSubject: [PATCH] staging: bcm2835-audio: Add disable-headphones flag\n\nAdd a property to allow the headphone output to be disabled. Use an\ninteger property rather than a boolean so that an overlay can clear it.\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.com>\n---\n drivers/staging/vc04_services/bcm2835-audio/bcm2835.c | 9 +++++++--\n 1 file changed, 7 insertions(+), 2 deletions(-)\n\n--- a/drivers/staging/vc04_services/bcm2835-audio/bcm2835.c\n+++ b/drivers/staging/vc04_services/bcm2835-audio/bcm2835.c\n@@ -381,11 +381,16 @@ static int snd_bcm2835_alsa_probe(struct\n \t}\n \n \tif (!enable_compat_alsa) {\n+\t\t// In this mode, enable analog output by default\n+\t\tu32 disable_headphones = 0;\n+\n \t\tif (!of_property_read_bool(dev->of_node, \"brcm,disable-hdmi\"))\n \t\t\tset_hdmi_enables(dev);\n \n-\t\t// In this mode, always enable analog output\n-\t\tenable_headphones = true;\n+\t\tof_property_read_u32(dev->of_node,\n+\t\t\t\t     \"brcm,disable-headphones\",\n+\t\t\t\t     &disable_headphones);\n+\t\tenable_headphones = !disable_headphones;\n \t} else {\n \t\tenable_hdmi0 = enable_hdmi;\n \t}\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0358-ARM-dts-Disable-headphone-audio-on-Zeroes-CM4.patch",
    "content": "From 895b2a5d3578ff5b91be41eb099280e2c63cb25c Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.com>\nDate: Mon, 26 Oct 2020 10:18:50 +0000\nSubject: [PATCH] ARM: dts: Disable headphone audio on Zeroes, CM4\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.com>\n---\n arch/arm/boot/dts/bcm2708-rpi-zero-w.dts | 1 +\n arch/arm/boot/dts/bcm2708-rpi-zero.dts   | 1 +\n arch/arm/boot/dts/bcm2711-rpi-cm4.dts    | 1 +\n 3 files changed, 3 insertions(+)\n\n--- a/arch/arm/boot/dts/bcm2708-rpi-zero-w.dts\n+++ b/arch/arm/boot/dts/bcm2708-rpi-zero-w.dts\n@@ -152,6 +152,7 @@\n &audio {\n \tpinctrl-names = \"default\";\n \tpinctrl-0 = <&audio_pins>;\n+\tbrcm,disable-headphones = <1>;\n };\n \n / {\n--- a/arch/arm/boot/dts/bcm2708-rpi-zero.dts\n+++ b/arch/arm/boot/dts/bcm2708-rpi-zero.dts\n@@ -106,6 +106,7 @@\n &audio {\n \tpinctrl-names = \"default\";\n \tpinctrl-0 = <&audio_pins>;\n+\tbrcm,disable-headphones = <1>;\n };\n \n / {\n--- a/arch/arm/boot/dts/bcm2711-rpi-cm4.dts\n+++ b/arch/arm/boot/dts/bcm2711-rpi-cm4.dts\n@@ -574,6 +574,7 @@\n &audio {\n \tpinctrl-names = \"default\";\n \tpinctrl-0 = <&audio_pins>;\n+\tbrcm,disable-headphones = <1>;\n };\n \n / {\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0359-overlays-Enable-headphone-audio-in-audremap.patch",
    "content": "From b16e7c1d42fafe29a34e8e0449c2d94debb38dc4 Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.com>\nDate: Mon, 26 Oct 2020 10:21:23 +0000\nSubject: [PATCH] overlays: Enable headphone audio in audremap\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.com>\n---\n arch/arm/boot/dts/overlays/audremap-overlay.dts | 7 +++++++\n 1 file changed, 7 insertions(+)\n\n--- a/arch/arm/boot/dts/overlays/audremap-overlay.dts\n+++ b/arch/arm/boot/dts/overlays/audremap-overlay.dts\n@@ -26,6 +26,13 @@\n \t\t};\n \t};\n \n+\tfragment@3 {\n+\t\ttarget = <&audio>;\n+\t\t__overlay__  {\n+\t\t\tbrcm,disable-headphones = <0>;\n+\t\t};\n+\t};\n+\n \t__overrides__ {\n \t\tswap_lr = <&frag0>, \"swap_lr?\";\n \t\tenable_jack = <&frag0>, \"enable_jack?\";\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0360-rpisense-fb-Set-pseudo_pallete-to-prevent-crash-on-f.patch",
    "content": "From 5a8f4fcd60686ac1f8e86e79ecbda81a4b9fef83 Mon Sep 17 00:00:00 2001\nFrom: Serge Schneider <serge@raspberrypi.com>\nDate: Mon, 26 Oct 2020 16:38:21 +0000\nSubject: [PATCH] rpisense-fb: Set pseudo_pallete to prevent crash on\n fbcon takeover\n\nSigned-off-by: Serge Schneider <serge@raspberrypi.com>\n---\n drivers/video/fbdev/rpisense-fb.c | 3 +++\n 1 file changed, 3 insertions(+)\n\n--- a/drivers/video/fbdev/rpisense-fb.c\n+++ b/drivers/video/fbdev/rpisense-fb.c\n@@ -52,6 +52,8 @@ static u8 gamma_low[32] = {0x00, 0x01, 0\n \n static u8 gamma_user[32];\n \n+static u32 pseudo_palette[16];\n+\n static struct rpisense_fb_param rpisense_fb_param = {\n \t.vmem = NULL,\n \t.vmemsize = 128,\n@@ -225,6 +227,7 @@ static int rpisense_fb_probe(struct plat\n \tinfo->flags = FBINFO_FLAG_DEFAULT | FBINFO_VIRTFB;\n \tinfo->screen_base = rpisense_fb_param.vmem;\n \tinfo->screen_size = rpisense_fb_param.vmemsize;\n+\tinfo->pseudo_palette = pseudo_palette;\n \n \tif (lowlight)\n \t\trpisense_fb_param.gamma = gamma_low;\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0361-ARM-dts-Expand-PCIe-space-on-BCM2711.patch",
    "content": "From f78a15dcaf63a5ad478670fd1d52d85261e88f37 Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.com>\nDate: Mon, 26 Oct 2020 10:35:43 +0000\nSubject: [PATCH] ARM: dts: Expand PCIe space on BCM2711\n\nAttempts to connect external GPUs to Compute Module 4's PCIe bus have\nhighlighted that the existing \"outbound window\" - the fraction of the\nPCI address base that is appears in the host's memory map - is\nrestrictively small. Expand the window to a full 1GB.\n\nSee: https://www.raspberrypi.org/forums/viewtopic.php?f=98&t=288902\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.com>\n---\n arch/arm/boot/dts/bcm2711.dtsi | 4 ++--\n 1 file changed, 2 insertions(+), 2 deletions(-)\n\n--- a/arch/arm/boot/dts/bcm2711.dtsi\n+++ b/arch/arm/boot/dts/bcm2711.dtsi\n@@ -560,8 +560,8 @@\n \t\t\tmsi-controller;\n \t\t\tmsi-parent = <&pcie0>;\n \n-\t\t\tranges = <0x02000000 0x0 0xf8000000 0x6 0x00000000\n-\t\t\t\t  0x0 0x04000000>;\n+\t\t\tranges = <0x02000000 0x0 0xc0000000 0x6 0x00000000\n+\t\t\t\t  0x0 0x40000000>;\n \t\t\t/*\n \t\t\t * The wrapper around the PCIe block has a bug\n \t\t\t * preventing it from accessing beyond the first 3GB of\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0362-dwc_otg-Minimise-header-and-fix-build-warnings.patch",
    "content": "From 649f8fd1bdd0eb3830ecc32a8e6905e6925952a1 Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.com>\nDate: Tue, 27 Oct 2020 09:59:49 +0000\nSubject: [PATCH] dwc_otg: Minimise header and fix build warnings\n\nDelete a large amount of unused declaration from \"usb.h\", some of which\nwere causing build warnings, and get the module building cleanly.\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.com>\n---\n drivers/usb/host/dwc_common_port/usb.h       | 664 -------------------\n drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c   |  10 +-\n drivers/usb/host/dwc_otg/dwc_otg_hcd.c       |  23 +-\n drivers/usb/host/dwc_otg/dwc_otg_hcd_ddma.c  |   3 +-\n drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c  |   8 +-\n drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c |   4 +-\n drivers/usb/host/dwc_otg/dwc_otg_pcd_intr.c  |   2 +-\n 7 files changed, 30 insertions(+), 684 deletions(-)\n\n--- a/drivers/usb/host/dwc_common_port/usb.h\n+++ b/drivers/usb/host/dwc_common_port/usb.h\n@@ -55,12 +55,6 @@ typedef u_int8_t uByte;\n typedef u_int8_t uWord[2];\n typedef u_int8_t uDWord[4];\n \n-#define USETW2(w,h,l) ((w)[0] = (u_int8_t)(l), (w)[1] = (u_int8_t)(h))\n-#define UCONSTW(x)\t{ (x) & 0xff, ((x) >> 8) & 0xff }\n-#define UCONSTDW(x)\t{ (x) & 0xff, ((x) >> 8) & 0xff, \\\n-\t\t\t  ((x) >> 16) & 0xff, ((x) >> 24) & 0xff }\n-\n-#if 1\n #define UGETW(w) ((w)[0] | ((w)[1] << 8))\n #define USETW(w,v) ((w)[0] = (u_int8_t)(v), (w)[1] = (u_int8_t)((v) >> 8))\n #define UGETDW(w) ((w)[0] | ((w)[1] << 8) | ((w)[2] << 16) | ((w)[3] << 24))\n@@ -68,31 +62,6 @@ typedef u_int8_t uDWord[4];\n \t\t     (w)[1] = (u_int8_t)((v) >> 8), \\\n \t\t     (w)[2] = (u_int8_t)((v) >> 16), \\\n \t\t     (w)[3] = (u_int8_t)((v) >> 24))\n-#else\n-/*\n- * On little-endian machines that can handle unanliged accesses\n- * (e.g. i386) these macros can be replaced by the following.\n- */\n-#define UGETW(w) (*(u_int16_t *)(w))\n-#define USETW(w,v) (*(u_int16_t *)(w) = (v))\n-#define UGETDW(w) (*(u_int32_t *)(w))\n-#define USETDW(w,v) (*(u_int32_t *)(w) = (v))\n-#endif\n-\n-/*\n- * Macros for accessing UAS IU fields, which are big-endian\n- */\n-#define IUSETW2(w,h,l) ((w)[0] = (u_int8_t)(h), (w)[1] = (u_int8_t)(l))\n-#define IUCONSTW(x)\t{ ((x) >> 8) & 0xff, (x) & 0xff }\n-#define IUCONSTDW(x)\t{ ((x) >> 24) & 0xff, ((x) >> 16) & 0xff, \\\n-\t\t\t((x) >> 8) & 0xff, (x) & 0xff }\n-#define IUGETW(w) (((w)[0] << 8) | (w)[1])\n-#define IUSETW(w,v) ((w)[0] = (u_int8_t)((v) >> 8), (w)[1] = (u_int8_t)(v))\n-#define IUGETDW(w) (((w)[0] << 24) | ((w)[1] << 16) | ((w)[2] << 8) | (w)[3])\n-#define IUSETDW(w,v) ((w)[0] = (u_int8_t)((v) >> 24), \\\n-\t\t      (w)[1] = (u_int8_t)((v) >> 16), \\\n-\t\t      (w)[2] = (u_int8_t)((v) >> 8), \\\n-\t\t      (w)[3] = (u_int8_t)(v))\n \n #define UPACKED __attribute__((__packed__))\n \n@@ -119,29 +88,6 @@ typedef struct {\n #define UT_ENDPOINT\t\t0x02\n #define UT_OTHER\t\t0x03\n \n-#define UT_READ_DEVICE\t\t(UT_READ  | UT_STANDARD | UT_DEVICE)\n-#define UT_READ_INTERFACE\t(UT_READ  | UT_STANDARD | UT_INTERFACE)\n-#define UT_READ_ENDPOINT\t(UT_READ  | UT_STANDARD | UT_ENDPOINT)\n-#define UT_WRITE_DEVICE\t\t(UT_WRITE | UT_STANDARD | UT_DEVICE)\n-#define UT_WRITE_INTERFACE\t(UT_WRITE | UT_STANDARD | UT_INTERFACE)\n-#define UT_WRITE_ENDPOINT\t(UT_WRITE | UT_STANDARD | UT_ENDPOINT)\n-#define UT_READ_CLASS_DEVICE\t(UT_READ  | UT_CLASS | UT_DEVICE)\n-#define UT_READ_CLASS_INTERFACE\t(UT_READ  | UT_CLASS | UT_INTERFACE)\n-#define UT_READ_CLASS_OTHER\t(UT_READ  | UT_CLASS | UT_OTHER)\n-#define UT_READ_CLASS_ENDPOINT\t(UT_READ  | UT_CLASS | UT_ENDPOINT)\n-#define UT_WRITE_CLASS_DEVICE\t(UT_WRITE | UT_CLASS | UT_DEVICE)\n-#define UT_WRITE_CLASS_INTERFACE (UT_WRITE | UT_CLASS | UT_INTERFACE)\n-#define UT_WRITE_CLASS_OTHER\t(UT_WRITE | UT_CLASS | UT_OTHER)\n-#define UT_WRITE_CLASS_ENDPOINT\t(UT_WRITE | UT_CLASS | UT_ENDPOINT)\n-#define UT_READ_VENDOR_DEVICE\t(UT_READ  | UT_VENDOR | UT_DEVICE)\n-#define UT_READ_VENDOR_INTERFACE (UT_READ  | UT_VENDOR | UT_INTERFACE)\n-#define UT_READ_VENDOR_OTHER\t(UT_READ  | UT_VENDOR | UT_OTHER)\n-#define UT_READ_VENDOR_ENDPOINT\t(UT_READ  | UT_VENDOR | UT_ENDPOINT)\n-#define UT_WRITE_VENDOR_DEVICE\t(UT_WRITE | UT_VENDOR | UT_DEVICE)\n-#define UT_WRITE_VENDOR_INTERFACE (UT_WRITE | UT_VENDOR | UT_INTERFACE)\n-#define UT_WRITE_VENDOR_OTHER\t(UT_WRITE | UT_VENDOR | UT_OTHER)\n-#define UT_WRITE_VENDOR_ENDPOINT (UT_WRITE | UT_VENDOR | UT_ENDPOINT)\n-\n /* Requests */\n #define UR_GET_STATUS\t\t0x00\n #define  USTAT_STANDARD_STATUS  0x00\n@@ -243,71 +189,6 @@ typedef struct {\n typedef struct {\n \tuByte\t\tbLength;\n \tuByte\t\tbDescriptorType;\n-\tuByte\t\tbDescriptorSubtype;\n-} UPACKED usb_descriptor_t;\n-\n-typedef struct {\n-\tuByte\t\tbLength;\n-\tuByte\t\tbDescriptorType;\n-} UPACKED usb_descriptor_header_t;\n-\n-typedef struct {\n-\tuByte\t\tbLength;\n-\tuByte\t\tbDescriptorType;\n-\tuWord\t\tbcdUSB;\n-#define UD_USB_2_0\t\t0x0200\n-#define UD_IS_USB2(d) (UGETW((d)->bcdUSB) >= UD_USB_2_0)\n-\tuByte\t\tbDeviceClass;\n-\tuByte\t\tbDeviceSubClass;\n-\tuByte\t\tbDeviceProtocol;\n-\tuByte\t\tbMaxPacketSize;\n-\t/* The fields below are not part of the initial descriptor. */\n-\tuWord\t\tidVendor;\n-\tuWord\t\tidProduct;\n-\tuWord\t\tbcdDevice;\n-\tuByte\t\tiManufacturer;\n-\tuByte\t\tiProduct;\n-\tuByte\t\tiSerialNumber;\n-\tuByte\t\tbNumConfigurations;\n-} UPACKED usb_device_descriptor_t;\n-#define USB_DEVICE_DESCRIPTOR_SIZE 18\n-\n-typedef struct {\n-\tuByte\t\tbLength;\n-\tuByte\t\tbDescriptorType;\n-\tuWord\t\twTotalLength;\n-\tuByte\t\tbNumInterface;\n-\tuByte\t\tbConfigurationValue;\n-\tuByte\t\tiConfiguration;\n-#define UC_ATT_ONE\t\t(1 << 7)\t/* must be set */\n-#define UC_ATT_SELFPOWER\t(1 << 6)\t/* self powered */\n-#define UC_ATT_WAKEUP\t\t(1 << 5)\t/* can wakeup */\n-#define UC_ATT_BATTERY\t\t(1 << 4)\t/* battery powered */\n-\tuByte\t\tbmAttributes;\n-#define UC_BUS_POWERED\t\t0x80\n-#define UC_SELF_POWERED\t\t0x40\n-#define UC_REMOTE_WAKEUP\t0x20\n-\tuByte\t\tbMaxPower; /* max current in 2 mA units */\n-#define UC_POWER_FACTOR 2\n-} UPACKED usb_config_descriptor_t;\n-#define USB_CONFIG_DESCRIPTOR_SIZE 9\n-\n-typedef struct {\n-\tuByte\t\tbLength;\n-\tuByte\t\tbDescriptorType;\n-\tuByte\t\tbInterfaceNumber;\n-\tuByte\t\tbAlternateSetting;\n-\tuByte\t\tbNumEndpoints;\n-\tuByte\t\tbInterfaceClass;\n-\tuByte\t\tbInterfaceSubClass;\n-\tuByte\t\tbInterfaceProtocol;\n-\tuByte\t\tiInterface;\n-} UPACKED usb_interface_descriptor_t;\n-#define USB_INTERFACE_DESCRIPTOR_SIZE 9\n-\n-typedef struct {\n-\tuByte\t\tbLength;\n-\tuByte\t\tbDescriptorType;\n \tuByte\t\tbEndpointAddress;\n #define UE_GET_DIR(a)\t((a) & 0x80)\n #define UE_SET_DIR(a,d)\t((a) | (((d)&1) << 7))\n@@ -332,27 +213,6 @@ typedef struct {\n } UPACKED usb_endpoint_descriptor_t;\n #define USB_ENDPOINT_DESCRIPTOR_SIZE 7\n \n-typedef struct ss_endpoint_companion_descriptor {\n-\tuByte bLength;\n-\tuByte bDescriptorType;\n-\tuByte bMaxBurst;\n-#define USSE_GET_MAX_STREAMS(a)\t\t((a) & 0x1f)\n-#define USSE_SET_MAX_STREAMS(a, b)\t((a) | ((b) & 0x1f))\n-#define USSE_GET_MAX_PACKET_NUM(a)\t((a) & 0x03)\n-#define USSE_SET_MAX_PACKET_NUM(a, b)\t((a) | ((b) & 0x03))\n-\tuByte bmAttributes;\n-\tuWord wBytesPerInterval;\n-} UPACKED ss_endpoint_companion_descriptor_t;\n-#define USB_SS_ENDPOINT_COMPANION_DESCRIPTOR_SIZE 6\n-\n-typedef struct {\n-\tuByte\t\tbLength;\n-\tuByte\t\tbDescriptorType;\n-\tuWord\t\tbString[127];\n-} UPACKED usb_string_descriptor_t;\n-#define USB_MAX_STRING_LEN 128\n-#define USB_LANGUAGE_TABLE 0\t/* # of the string language id table */\n-\n /* Hub specific request */\n #define UR_GET_BUS_STATE\t0x02\n #define UR_CLEAR_TT_BUFFER\t0x08\n@@ -411,530 +271,6 @@ typedef struct {\n } UPACKED usb_hub_descriptor_t;\n #define USB_HUB_DESCRIPTOR_SIZE 9 /* includes deprecated PortPowerCtrlMask */\n \n-typedef struct {\n-\tuByte\t\tbLength;\n-\tuByte\t\tbDescriptorType;\n-\tuWord\t\tbcdUSB;\n-\tuByte\t\tbDeviceClass;\n-\tuByte\t\tbDeviceSubClass;\n-\tuByte\t\tbDeviceProtocol;\n-\tuByte\t\tbMaxPacketSize0;\n-\tuByte\t\tbNumConfigurations;\n-\tuByte\t\tbReserved;\n-} UPACKED usb_device_qualifier_t;\n-#define USB_DEVICE_QUALIFIER_SIZE 10\n-\n-typedef struct {\n-\tuByte\t\tbLength;\n-\tuByte\t\tbDescriptorType;\n-\tuByte\t\tbmAttributes;\n-#define UOTG_SRP\t0x01\n-#define UOTG_HNP\t0x02\n-} UPACKED usb_otg_descriptor_t;\n-\n-/* OTG feature selectors */\n-#define UOTG_B_HNP_ENABLE\t3\n-#define UOTG_A_HNP_SUPPORT\t4\n-#define UOTG_A_ALT_HNP_SUPPORT\t5\n-\n-typedef struct {\n-\tuWord\t\twStatus;\n-/* Device status flags */\n-#define UDS_SELF_POWERED\t\t0x0001\n-#define UDS_REMOTE_WAKEUP\t\t0x0002\n-/* Endpoint status flags */\n-#define UES_HALT\t\t\t0x0001\n-} UPACKED usb_status_t;\n-\n-typedef struct {\n-\tuWord\t\twHubStatus;\n-#define UHS_LOCAL_POWER\t\t\t0x0001\n-#define UHS_OVER_CURRENT\t\t0x0002\n-\tuWord\t\twHubChange;\n-} UPACKED usb_hub_status_t;\n-\n-typedef struct {\n-\tuWord\t\twPortStatus;\n-#define UPS_CURRENT_CONNECT_STATUS\t0x0001\n-#define UPS_PORT_ENABLED\t\t0x0002\n-#define UPS_SUSPEND\t\t\t0x0004\n-#define UPS_OVERCURRENT_INDICATOR\t0x0008\n-#define UPS_RESET\t\t\t0x0010\n-#define UPS_PORT_POWER\t\t\t0x0100\n-#define UPS_LOW_SPEED\t\t\t0x0200\n-#define UPS_HIGH_SPEED\t\t\t0x0400\n-#define UPS_PORT_TEST\t\t\t0x0800\n-#define UPS_PORT_INDICATOR\t\t0x1000\n-\tuWord\t\twPortChange;\n-#define UPS_C_CONNECT_STATUS\t\t0x0001\n-#define UPS_C_PORT_ENABLED\t\t0x0002\n-#define UPS_C_SUSPEND\t\t\t0x0004\n-#define UPS_C_OVERCURRENT_INDICATOR\t0x0008\n-#define UPS_C_PORT_RESET\t\t0x0010\n-} UPACKED usb_port_status_t;\n-\n-#ifdef _MSC_VER\n-#include <poppack.h>\n-#endif\n-\n-/* Device class codes */\n-#define UDCLASS_IN_INTERFACE\t0x00\n-#define UDCLASS_COMM\t\t0x02\n-#define UDCLASS_HUB\t\t0x09\n-#define  UDSUBCLASS_HUB\t\t0x00\n-#define  UDPROTO_FSHUB\t\t0x00\n-#define  UDPROTO_HSHUBSTT\t0x01\n-#define  UDPROTO_HSHUBMTT\t0x02\n-#define UDCLASS_DIAGNOSTIC\t0xdc\n-#define UDCLASS_WIRELESS\t0xe0\n-#define  UDSUBCLASS_RF\t\t0x01\n-#define   UDPROTO_BLUETOOTH\t0x01\n-#define UDCLASS_VENDOR\t\t0xff\n-\n-/* Interface class codes */\n-#define UICLASS_UNSPEC\t\t0x00\n-\n-#define UICLASS_AUDIO\t\t0x01\n-#define  UISUBCLASS_AUDIOCONTROL\t1\n-#define  UISUBCLASS_AUDIOSTREAM\t\t2\n-#define  UISUBCLASS_MIDISTREAM\t\t3\n-\n-#define UICLASS_CDC\t\t0x02 /* communication */\n-#define  UISUBCLASS_DIRECT_LINE_CONTROL_MODEL\t1\n-#define  UISUBCLASS_ABSTRACT_CONTROL_MODEL\t2\n-#define  UISUBCLASS_TELEPHONE_CONTROL_MODEL\t3\n-#define  UISUBCLASS_MULTICHANNEL_CONTROL_MODEL\t4\n-#define  UISUBCLASS_CAPI_CONTROLMODEL\t\t5\n-#define  UISUBCLASS_ETHERNET_NETWORKING_CONTROL_MODEL 6\n-#define  UISUBCLASS_ATM_NETWORKING_CONTROL_MODEL 7\n-#define   UIPROTO_CDC_AT\t\t\t1\n-\n-#define UICLASS_HID\t\t0x03\n-#define  UISUBCLASS_BOOT\t1\n-#define  UIPROTO_BOOT_KEYBOARD\t1\n-\n-#define UICLASS_PHYSICAL\t0x05\n-\n-#define UICLASS_IMAGE\t\t0x06\n-\n-#define UICLASS_PRINTER\t\t0x07\n-#define  UISUBCLASS_PRINTER\t1\n-#define  UIPROTO_PRINTER_UNI\t1\n-#define  UIPROTO_PRINTER_BI\t2\n-#define  UIPROTO_PRINTER_1284\t3\n-\n-#define UICLASS_MASS\t\t0x08\n-#define  UISUBCLASS_RBC\t\t1\n-#define  UISUBCLASS_SFF8020I\t2\n-#define  UISUBCLASS_QIC157\t3\n-#define  UISUBCLASS_UFI\t\t4\n-#define  UISUBCLASS_SFF8070I\t5\n-#define  UISUBCLASS_SCSI\t6\n-#define  UIPROTO_MASS_CBI_I\t0\n-#define  UIPROTO_MASS_CBI\t1\n-#define  UIPROTO_MASS_BBB_OLD\t2\t/* Not in the spec anymore */\n-#define  UIPROTO_MASS_BBB\t80\t/* 'P' for the Iomega Zip drive */\n-\n-#define UICLASS_HUB\t\t0x09\n-#define  UISUBCLASS_HUB\t\t0\n-#define  UIPROTO_FSHUB\t\t0\n-#define  UIPROTO_HSHUBSTT\t0 /* Yes, same as previous */\n-#define  UIPROTO_HSHUBMTT\t1\n-\n-#define UICLASS_CDC_DATA\t0x0a\n-#define  UISUBCLASS_DATA\t\t0\n-#define   UIPROTO_DATA_ISDNBRI\t\t0x30    /* Physical iface */\n-#define   UIPROTO_DATA_HDLC\t\t0x31    /* HDLC */\n-#define   UIPROTO_DATA_TRANSPARENT\t0x32    /* Transparent */\n-#define   UIPROTO_DATA_Q921M\t\t0x50    /* Management for Q921 */\n-#define   UIPROTO_DATA_Q921\t\t0x51    /* Data for Q921 */\n-#define   UIPROTO_DATA_Q921TM\t\t0x52    /* TEI multiplexer for Q921 */\n-#define   UIPROTO_DATA_V42BIS\t\t0x90    /* Data compression */\n-#define   UIPROTO_DATA_Q931\t\t0x91    /* Euro-ISDN */\n-#define   UIPROTO_DATA_V120\t\t0x92    /* V.24 rate adaption */\n-#define   UIPROTO_DATA_CAPI\t\t0x93    /* CAPI 2.0 commands */\n-#define   UIPROTO_DATA_HOST_BASED\t0xfd    /* Host based driver */\n-#define   UIPROTO_DATA_PUF\t\t0xfe    /* see Prot. Unit Func. Desc.*/\n-#define   UIPROTO_DATA_VENDOR\t\t0xff    /* Vendor specific */\n-\n-#define UICLASS_SMARTCARD\t0x0b\n-\n-/*#define UICLASS_FIRM_UPD\t0x0c*/\n-\n-#define UICLASS_SECURITY\t0x0d\n-\n-#define UICLASS_DIAGNOSTIC\t0xdc\n-\n-#define UICLASS_WIRELESS\t0xe0\n-#define  UISUBCLASS_RF\t\t\t0x01\n-#define   UIPROTO_BLUETOOTH\t\t0x01\n-\n-#define UICLASS_APPL_SPEC\t0xfe\n-#define  UISUBCLASS_FIRMWARE_DOWNLOAD\t1\n-#define  UISUBCLASS_IRDA\t\t2\n-#define  UIPROTO_IRDA\t\t\t0\n-\n-#define UICLASS_VENDOR\t\t0xff\n-\n-#define USB_HUB_MAX_DEPTH 5\n-\n-/*\n- * Minimum time a device needs to be powered down to go through\n- * a power cycle.  XXX Are these time in the spec?\n- */\n-#define USB_POWER_DOWN_TIME\t200 /* ms */\n-#define USB_PORT_POWER_DOWN_TIME\t100 /* ms */\n-\n-#if 0\n-/* These are the values from the spec. */\n-#define USB_PORT_RESET_DELAY\t10  /* ms */\n-#define USB_PORT_ROOT_RESET_DELAY 50  /* ms */\n-#define USB_PORT_RESET_RECOVERY\t10  /* ms */\n-#define USB_PORT_POWERUP_DELAY\t100 /* ms */\n-#define USB_SET_ADDRESS_SETTLE\t2   /* ms */\n-#define USB_RESUME_DELAY\t(20*5)  /* ms */\n-#define USB_RESUME_WAIT\t\t10  /* ms */\n-#define USB_RESUME_RECOVERY\t10  /* ms */\n-#define USB_EXTRA_POWER_UP_TIME\t0   /* ms */\n-#else\n-/* Allow for marginal (i.e. non-conforming) devices. */\n-#define USB_PORT_RESET_DELAY\t50  /* ms */\n-#define USB_PORT_ROOT_RESET_DELAY 250  /* ms */\n-#define USB_PORT_RESET_RECOVERY\t250  /* ms */\n-#define USB_PORT_POWERUP_DELAY\t300 /* ms */\n-#define USB_SET_ADDRESS_SETTLE\t10  /* ms */\n-#define USB_RESUME_DELAY\t(50*5)  /* ms */\n-#define USB_RESUME_WAIT\t\t50  /* ms */\n-#define USB_RESUME_RECOVERY\t50  /* ms */\n-#define USB_EXTRA_POWER_UP_TIME\t20  /* ms */\n-#endif\n-\n-#define USB_MIN_POWER\t\t100 /* mA */\n-#define USB_MAX_POWER\t\t500 /* mA */\n-\n-#define USB_BUS_RESET_DELAY\t100 /* ms XXX?*/\n-\n-#define USB_UNCONFIG_NO 0\n-#define USB_UNCONFIG_INDEX (-1)\n-\n-/*** ioctl() related stuff ***/\n-\n-struct usb_ctl_request {\n-\tint\tucr_addr;\n-\tusb_device_request_t ucr_request;\n-\tvoid\t*ucr_data;\n-\tint\tucr_flags;\n-#define USBD_SHORT_XFER_OK\t0x04\t/* allow short reads */\n-\tint\tucr_actlen;\t\t/* actual length transferred */\n-};\n-\n-struct usb_alt_interface {\n-\tint\tuai_config_index;\n-\tint\tuai_interface_index;\n-\tint\tuai_alt_no;\n-};\n-\n-#define USB_CURRENT_CONFIG_INDEX (-1)\n-#define USB_CURRENT_ALT_INDEX (-1)\n-\n-struct usb_config_desc {\n-\tint\tucd_config_index;\n-\tusb_config_descriptor_t ucd_desc;\n-};\n-\n-struct usb_interface_desc {\n-\tint\tuid_config_index;\n-\tint\tuid_interface_index;\n-\tint\tuid_alt_index;\n-\tusb_interface_descriptor_t uid_desc;\n-};\n-\n-struct usb_endpoint_desc {\n-\tint\tued_config_index;\n-\tint\tued_interface_index;\n-\tint\tued_alt_index;\n-\tint\tued_endpoint_index;\n-\tusb_endpoint_descriptor_t ued_desc;\n-};\n-\n-struct usb_full_desc {\n-\tint\tufd_config_index;\n-\tu_int\tufd_size;\n-\tu_char\t*ufd_data;\n-};\n-\n-struct usb_string_desc {\n-\tint\tusd_string_index;\n-\tint\tusd_language_id;\n-\tusb_string_descriptor_t usd_desc;\n-};\n-\n-struct usb_ctl_report_desc {\n-\tint\tucrd_size;\n-\tu_char\tucrd_data[1024];\t/* filled data size will vary */\n-};\n-\n-typedef struct { u_int32_t cookie; } usb_event_cookie_t;\n-\n-#define USB_MAX_DEVNAMES 4\n-#define USB_MAX_DEVNAMELEN 16\n-struct usb_device_info {\n-\tu_int8_t\tudi_bus;\n-\tu_int8_t\tudi_addr;\t/* device address */\n-\tusb_event_cookie_t udi_cookie;\n-\tchar\t\tudi_product[USB_MAX_STRING_LEN];\n-\tchar\t\tudi_vendor[USB_MAX_STRING_LEN];\n-\tchar\t\tudi_release[8];\n-\tu_int16_t\tudi_productNo;\n-\tu_int16_t\tudi_vendorNo;\n-\tu_int16_t\tudi_releaseNo;\n-\tu_int8_t\tudi_class;\n-\tu_int8_t\tudi_subclass;\n-\tu_int8_t\tudi_protocol;\n-\tu_int8_t\tudi_config;\n-\tu_int8_t\tudi_speed;\n-#define USB_SPEED_UNKNOWN\t0\n-#define USB_SPEED_LOW\t\t1\n-#define USB_SPEED_FULL\t\t2\n-#define USB_SPEED_HIGH\t\t3\n-#define USB_SPEED_VARIABLE\t4\n-#define USB_SPEED_SUPER\t\t5\n-\tint\t\tudi_power;\t/* power consumption in mA, 0 if selfpowered */\n-\tint\t\tudi_nports;\n-\tchar\t\tudi_devnames[USB_MAX_DEVNAMES][USB_MAX_DEVNAMELEN];\n-\tu_int8_t\tudi_ports[16];/* hub only: addresses of devices on ports */\n-#define USB_PORT_ENABLED 0xff\n-#define USB_PORT_SUSPENDED 0xfe\n-#define USB_PORT_POWERED 0xfd\n-#define USB_PORT_DISABLED 0xfc\n-};\n-\n-struct usb_ctl_report {\n-\tint\tucr_report;\n-\tu_char\tucr_data[1024];\t/* filled data size will vary */\n-};\n-\n-struct usb_device_stats {\n-\tu_long\tuds_requests[4];\t/* indexed by transfer type UE_* */\n-};\n-\n-#define WUSB_MIN_IE\t\t\t0x80\n-#define WUSB_WCTA_IE\t\t\t0x80\n-#define WUSB_WCONNECTACK_IE\t\t0x81\n-#define WUSB_WHOSTINFO_IE\t\t0x82\n-#define  WUHI_GET_CA(_bmAttributes_) ((_bmAttributes_) & 0x3)\n-#define   WUHI_CA_RECONN\t\t0x00\n-#define   WUHI_CA_LIMITED\t\t0x01\n-#define   WUHI_CA_ALL\t\t\t0x03\n-#define  WUHI_GET_MLSI(_bmAttributes_) (((_bmAttributes_) & 0x38) >> 3)\n-#define WUSB_WCHCHANGEANNOUNCE_IE\t0x83\n-#define WUSB_WDEV_DISCONNECT_IE\t\t0x84\n-#define WUSB_WHOST_DISCONNECT_IE\t0x85\n-#define WUSB_WRELEASE_CHANNEL_IE\t0x86\n-#define WUSB_WWORK_IE\t\t\t0x87\n-#define WUSB_WCHANNEL_STOP_IE\t\t0x88\n-#define WUSB_WDEV_KEEPALIVE_IE\t\t0x89\n-#define WUSB_WISOCH_DISCARD_IE\t\t0x8A\n-#define WUSB_WRESETDEVICE_IE\t\t0x8B\n-#define WUSB_WXMIT_PACKET_ADJUST_IE\t0x8C\n-#define WUSB_MAX_IE\t\t\t0x8C\n-\n-/* Device Notification Types */\n-\n-#define WUSB_DN_MIN\t\t\t0x01\n-#define WUSB_DN_CONNECT\t\t\t0x01\n-# define WUSB_DA_OLDCONN\t0x00\n-# define WUSB_DA_NEWCONN\t0x01\n-# define WUSB_DA_SELF_BEACON\t0x02\n-# define WUSB_DA_DIR_BEACON\t0x04\n-# define WUSB_DA_NO_BEACON\t0x06\n-#define WUSB_DN_DISCONNECT\t\t0x02\n-#define WUSB_DN_EPRDY\t\t\t0x03\n-#define WUSB_DN_MASAVAILCHANGED\t\t0x04\n-#define WUSB_DN_REMOTEWAKEUP\t\t0x05\n-#define WUSB_DN_SLEEP\t\t\t0x06\n-#define WUSB_DN_ALIVE\t\t\t0x07\n-#define WUSB_DN_MAX\t\t\t0x07\n-\n-#ifdef _MSC_VER\n-#include <pshpack1.h>\n-#endif\n-\n-/* WUSB Handshake Data.  Used during the SET/GET HANDSHAKE requests */\n-typedef struct wusb_hndshk_data {\n-\tuByte bMessageNumber;\n-\tuByte bStatus;\n-\tuByte tTKID[3];\n-\tuByte bReserved;\n-\tuByte CDID[16];\n-\tuByte Nonce[16];\n-\tuByte MIC[8];\n-} UPACKED wusb_hndshk_data_t;\n-#define WUSB_HANDSHAKE_LEN_FOR_MIC\t38\n-\n-/* WUSB Connection Context */\n-typedef struct wusb_conn_context {\n-\tuByte CHID [16];\n-\tuByte CDID [16];\n-\tuByte CK [16];\n-} UPACKED wusb_conn_context_t;\n-\n-/* WUSB Security Descriptor */\n-typedef struct wusb_security_desc {\n-\tuByte bLength;\n-\tuByte bDescriptorType;\n-\tuWord wTotalLength;\n-\tuByte bNumEncryptionTypes;\n-} UPACKED wusb_security_desc_t;\n-\n-/* WUSB Encryption Type Descriptor */\n-typedef struct wusb_encrypt_type_desc {\n-\tuByte bLength;\n-\tuByte bDescriptorType;\n-\n-\tuByte bEncryptionType;\n-#define WUETD_UNSECURE\t\t0\n-#define WUETD_WIRED\t\t1\n-#define WUETD_CCM_1\t\t2\n-#define WUETD_RSA_1\t\t3\n-\n-\tuByte bEncryptionValue;\n-\tuByte bAuthKeyIndex;\n-} UPACKED wusb_encrypt_type_desc_t;\n-\n-/* WUSB Key Descriptor */\n-typedef struct wusb_key_desc {\n-\tuByte bLength;\n-\tuByte bDescriptorType;\n-\tuByte tTKID[3];\n-\tuByte bReserved;\n-\tuByte KeyData[1];\t/* variable length */\n-} UPACKED wusb_key_desc_t;\n-\n-/* WUSB BOS Descriptor (Binary device Object Store) */\n-typedef struct wusb_bos_desc {\n-\tuByte bLength;\n-\tuByte bDescriptorType;\n-\tuWord wTotalLength;\n-\tuByte bNumDeviceCaps;\n-} UPACKED wusb_bos_desc_t;\n-\n-#define USB_DEVICE_CAPABILITY_20_EXTENSION\t0x02\n-typedef struct usb_dev_cap_20_ext_desc {\n-\tuByte bLength;\n-\tuByte bDescriptorType;\n-\tuByte bDevCapabilityType;\n-#define USB_20_EXT_LPM\t\t\t\t0x02\n-\tuDWord bmAttributes;\n-} UPACKED usb_dev_cap_20_ext_desc_t;\n-\n-#define USB_DEVICE_CAPABILITY_SS_USB\t\t0x03\n-typedef struct usb_dev_cap_ss_usb {\n-\tuByte bLength;\n-\tuByte bDescriptorType;\n-\tuByte bDevCapabilityType;\n-#define USB_DC_SS_USB_LTM_CAPABLE\t\t0x02\n-\tuByte bmAttributes;\n-#define USB_DC_SS_USB_SPEED_SUPPORT_LOW\t\t0x01\n-#define USB_DC_SS_USB_SPEED_SUPPORT_FULL\t0x02\n-#define USB_DC_SS_USB_SPEED_SUPPORT_HIGH\t0x04\n-#define USB_DC_SS_USB_SPEED_SUPPORT_SS\t\t0x08\n-\tuWord wSpeedsSupported;\n-\tuByte bFunctionalitySupport;\n-\tuByte bU1DevExitLat;\n-\tuWord wU2DevExitLat;\n-} UPACKED usb_dev_cap_ss_usb_t;\n-\n-#define USB_DEVICE_CAPABILITY_CONTAINER_ID\t0x04\n-typedef struct usb_dev_cap_container_id {\n-\tuByte bLength;\n-\tuByte bDescriptorType;\n-\tuByte bDevCapabilityType;\n-\tuByte bReserved;\n-\tuByte containerID[16];\n-} UPACKED usb_dev_cap_container_id_t;\n-\n-/* Device Capability Type Codes */\n-#define WUSB_DEVICE_CAPABILITY_WIRELESS_USB 0x01\n-\n-/* Device Capability Descriptor */\n-typedef struct wusb_dev_cap_desc {\n-\tuByte bLength;\n-\tuByte bDescriptorType;\n-\tuByte bDevCapabilityType;\n-\tuByte caps[1];\t/* Variable length */\n-} UPACKED wusb_dev_cap_desc_t;\n-\n-/* Device Capability Descriptor */\n-typedef struct wusb_dev_cap_uwb_desc {\n-\tuByte bLength;\n-\tuByte bDescriptorType;\n-\tuByte bDevCapabilityType;\n-\tuByte bmAttributes;\n-\tuWord wPHYRates;\t/* Bitmap */\n-\tuByte bmTFITXPowerInfo;\n-\tuByte bmFFITXPowerInfo;\n-\tuWord bmBandGroup;\n-\tuByte bReserved;\n-} UPACKED wusb_dev_cap_uwb_desc_t;\n-\n-/* Wireless USB Endpoint Companion Descriptor */\n-typedef struct wusb_endpoint_companion_desc {\n-\tuByte bLength;\n-\tuByte bDescriptorType;\n-\tuByte bMaxBurst;\n-\tuByte bMaxSequence;\n-\tuWord wMaxStreamDelay;\n-\tuWord wOverTheAirPacketSize;\n-\tuByte bOverTheAirInterval;\n-\tuByte bmCompAttributes;\n-} UPACKED wusb_endpoint_companion_desc_t;\n-\n-/* Wireless USB Numeric Association M1 Data Structure */\n-typedef struct wusb_m1_data {\n-\tuByte version;\n-\tuWord langId;\n-\tuByte deviceFriendlyNameLength;\n-\tuByte sha_256_m3[32];\n-\tuByte deviceFriendlyName[256];\n-} UPACKED wusb_m1_data_t;\n-\n-typedef struct wusb_m2_data {\n-\tuByte version;\n-\tuWord langId;\n-\tuByte hostFriendlyNameLength;\n-\tuByte pkh[384];\n-\tuByte hostFriendlyName[256];\n-} UPACKED wusb_m2_data_t;\n-\n-typedef struct wusb_m3_data {\n-\tuByte pkd[384];\n-\tuByte nd;\n-} UPACKED wusb_m3_data_t;\n-\n-typedef struct wusb_m4_data {\n-\tuDWord _attributeTypeIdAndLength_1;\n-\tuWord  associationTypeId;\n-\n-\tuDWord _attributeTypeIdAndLength_2;\n-\tuWord  associationSubTypeId;\n-\n-\tuDWord _attributeTypeIdAndLength_3;\n-\tuDWord length;\n-\n-\tuDWord _attributeTypeIdAndLength_4;\n-\tuDWord associationStatus;\n-\n-\tuDWord _attributeTypeIdAndLength_5;\n-\tuByte  chid[16];\n-\n-\tuDWord _attributeTypeIdAndLength_6;\n-\tuByte  cdid[16];\n-\n-\tuDWord _attributeTypeIdAndLength_7;\n-\tuByte  bandGroups[2];\n-} UPACKED wusb_m4_data_t;\n-\n #ifdef _MSC_VER\n #include <poppack.h>\n #endif\n--- a/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c\n+++ b/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c\n@@ -240,7 +240,8 @@ static int notrace fiq_increment_dma_buf\n \thcdma_data_t hcdma;\n \tint i = st->channel[n].dma_info.index;\n \tint len;\n-\tstruct fiq_dma_blob *blob = (struct fiq_dma_blob *) st->dma_base;\n+\tstruct fiq_dma_blob *blob =\n+\t\t(struct fiq_dma_blob *)(uintptr_t)st->dma_base;\n \n \tlen = fiq_get_xfer_len(st, n);\n \tfiq_print(FIQDBG_INT, st, \"LEN: %03d\", len);\n@@ -249,7 +250,7 @@ static int notrace fiq_increment_dma_buf\n \tif (i > 6)\n \t\tBUG();\n \n-\thcdma.d32 = (dma_addr_t) &blob->channel[n].index[i].buf[0];\n+\thcdma.d32 = (u32)(uintptr_t)&blob->channel[n].index[i].buf[0];\n \tFIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HC_DMA, hcdma.d32);\n \tst->channel[n].dma_info.index = i;\n \treturn 0;\n@@ -289,7 +290,8 @@ static int notrace fiq_iso_out_advance(s\n \thcsplt_data_t hcsplt;\n \thctsiz_data_t hctsiz;\n \thcdma_data_t hcdma;\n-\tstruct fiq_dma_blob *blob = (struct fiq_dma_blob *) st->dma_base;\n+\tstruct fiq_dma_blob *blob =\n+\t\t(struct fiq_dma_blob *)(uintptr_t)st->dma_base;\n \tint last = 0;\n \tint i = st->channel[n].dma_info.index;\n \n@@ -301,7 +303,7 @@ static int notrace fiq_iso_out_advance(s\n \t\tlast = 1;\n \n \t/* New DMA address - address of bounce buffer referred to in index */\n-\thcdma.d32 = (dma_addr_t) blob->channel[n].index[i].buf;\n+\thcdma.d32 = (u32)(uintptr_t)blob->channel[n].index[i].buf;\n \t//hcdma.d32 = FIQ_READ(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HC_DMA);\n \t//hcdma.d32 += st->channel[n].dma_info.slot_len[i];\n \tfiq_print(FIQDBG_INT, st, \"LAST: %01d \", last);\n--- a/drivers/usb/host/dwc_otg/dwc_otg_hcd.c\n+++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd.c\n@@ -1270,7 +1270,8 @@ static void assign_and_init_hc(dwc_otg_h\n \thc->multi_count = 1;\n \n \tif (hcd->core_if->dma_enable) {\n-\t\thc->xfer_buff = (uint8_t *) urb->dma + urb->actual_length;\n+\t\thc->xfer_buff =\n+\t\t    (uint8_t *)(uintptr_t)urb->dma + urb->actual_length;\n \n \t\t/* For non-dword aligned case */\n \t\tif (((unsigned long)hc->xfer_buff & 0x3)\n@@ -1314,7 +1315,8 @@ static void assign_and_init_hc(dwc_otg_h\n \t\t\thc->ep_is_in = 0;\n \t\t\thc->data_pid_start = DWC_OTG_HC_PID_SETUP;\n \t\t\tif (hcd->core_if->dma_enable) {\n-\t\t\t\thc->xfer_buff = (uint8_t *) urb->setup_dma;\n+\t\t\t\thc->xfer_buff =\n+\t\t\t\t\t(uint8_t *)(uintptr_t)urb->setup_dma;\n \t\t\t} else {\n \t\t\t\thc->xfer_buff = (uint8_t *) urb->setup_packet;\n \t\t\t}\n@@ -1362,7 +1364,8 @@ static void assign_and_init_hc(dwc_otg_h\n \n \t\t\thc->xfer_len = 0;\n \t\t\tif (hcd->core_if->dma_enable) {\n-\t\t\t\thc->xfer_buff = (uint8_t *) hcd->status_buf_dma;\n+\t\t\t\thc->xfer_buff = (uint8_t *)\n+\t\t\t\t\t(uintptr_t)hcd->status_buf_dma;\n \t\t\t} else {\n \t\t\t\thc->xfer_buff = (uint8_t *) hcd->status_buf;\n \t\t\t}\n@@ -1390,7 +1393,7 @@ static void assign_and_init_hc(dwc_otg_h\n \t\t\tframe_desc->status = 0;\n \n \t\t\tif (hcd->core_if->dma_enable) {\n-\t\t\t\thc->xfer_buff = (uint8_t *) urb->dma;\n+\t\t\t\thc->xfer_buff = (uint8_t *)(uintptr_t)urb->dma;\n \t\t\t} else {\n \t\t\t\thc->xfer_buff = (uint8_t *) urb->buf;\n \t\t\t}\n@@ -1571,8 +1574,10 @@ int fiq_fsm_setup_periodic_dma(dwc_otg_h\n \t\t * Pointer arithmetic on hcd->fiq_state->dma_base (a dma_addr_t)\n \t\t * to point it to the correct offset in the allocated buffers.\n \t\t */\n-\t\tblob = (struct fiq_dma_blob *) hcd->fiq_state->dma_base;\n-\t\tst->hcdma_copy.d32 = (dma_addr_t) blob->channel[hc->hc_num].index[0].buf;\n+\t\tblob = (struct fiq_dma_blob *)\n+\t\t\t(uintptr_t)hcd->fiq_state->dma_base;\n+\t\tst->hcdma_copy.d32 =(u32)(uintptr_t)\n+\t\t\tblob->channel[hc->hc_num].index[0].buf;\n \n \t\t/* Calculate the max number of CSPLITS such that the FIQ can time out\n \t\t * a transaction if it fails.\n@@ -1627,8 +1632,10 @@ int fiq_fsm_setup_periodic_dma(dwc_otg_h\n \t\t\t * dma_addr_t) to point it to the correct offset in the\n \t\t\t * allocated buffers.\n \t\t\t */\n-\t\t\tblob = (struct fiq_dma_blob *) hcd->fiq_state->dma_base;\n-\t\t\tst->hcdma_copy.d32 = (dma_addr_t) blob->channel[hc->hc_num].index[0].buf;\n+\t\t\tblob = (struct fiq_dma_blob *)\n+\t\t\t\t(uintptr_t)hcd->fiq_state->dma_base;\n+\t\t\tst->hcdma_copy.d32 = (u32)(uintptr_t)\n+\t\t\t\tblob->channel[hc->hc_num].index[0].buf;\n \n \t\t\t/* fixup xfersize to the actual packet size */\n \t\t\tst->hctsiz_copy.b.pid = 0;\n--- a/drivers/usb/host/dwc_otg/dwc_otg_hcd_ddma.c\n+++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd_ddma.c\n@@ -620,7 +620,8 @@ static void init_non_isoc_dma_desc(dwc_o\n \n \t\tif (n_desc) {\n \t\t\t/* SG request - more than 1 QTDs */\n-\t\t\thc->xfer_buff = (uint8_t *)qtd->urb->dma + qtd->urb->actual_length;\n+\t\t\thc->xfer_buff = (uint8_t *)(uintptr_t)qtd->urb->dma +\n+\t\t\t\t\tqtd->urb->actual_length;\n \t\t\thc->xfer_len = qtd->urb->length - qtd->urb->actual_length;\n \t\t}\n \n--- a/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c\n+++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c\n@@ -1857,10 +1857,10 @@ static int32_t handle_hc_ahberr_intr(dwc\n \tDWC_ERROR(\"  Max packet size: %d\\n\",\n \t\t  dwc_otg_hcd_get_mps(&urb->pipe_info));\n \tDWC_ERROR(\"  Data buffer length: %d\\n\", urb->length);\n-\tDWC_ERROR(\"  Transfer buffer: %p, Transfer DMA: %p\\n\",\n-\t\t  urb->buf, (void *)urb->dma);\n-\tDWC_ERROR(\"  Setup buffer: %p, Setup DMA: %p\\n\",\n-\t\t  urb->setup_packet, (void *)urb->setup_dma);\n+\tDWC_ERROR(\"  Transfer buffer: %p, Transfer DMA: %pad\\n\",\n+\t\t  urb->buf, &urb->dma);\n+\tDWC_ERROR(\"  Setup buffer: %p, Setup DMA: %pad\\n\",\n+\t\t  urb->setup_packet, &urb->setup_dma);\n \tDWC_ERROR(\"  Interval: %d\\n\", urb->interval);\n \n \t/* Core haltes the channel for Descriptor DMA mode */\n--- a/drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c\n+++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c\n@@ -482,8 +482,8 @@ static void hcd_init_fiq(void *cookie)\n \t\t\totg_dev->os_dep.mphi_base + 0x1f0;\n \t\tdwc_otg_hcd->fiq_state->mphi_regs.swirq_clr =\n \t\t\totg_dev->os_dep.mphi_base + 0x1f4;\n-\t\tDWC_WARN(\"Fake MPHI regs_base at 0x%08x\",\n-\t\t\t (int)dwc_otg_hcd->fiq_state->mphi_regs.base);\n+\t\tDWC_WARN(\"Fake MPHI regs_base at %px\",\n+\t\t\t dwc_otg_hcd->fiq_state->mphi_regs.base);\n \t} else {\n \t\tdwc_otg_hcd->fiq_state->mphi_regs.ctrl =\n \t\t\totg_dev->os_dep.mphi_base + 0x4c;\n--- a/drivers/usb/host/dwc_otg/dwc_otg_pcd_intr.c\n+++ b/drivers/usb/host/dwc_otg/dwc_otg_pcd_intr.c\n@@ -3377,7 +3377,7 @@ void predict_nextep_seq( dwc_otg_core_if\n \tdtknq1_data_t dtknqr1;\n \tuint32_t in_tkn_epnums[4];\n \tuint8_t seqnum[MAX_EPS_CHANNELS];\n-\tuint8_t intkn_seq[TOKEN_Q_DEPTH];\n+\tuint8_t intkn_seq[1 << 5];\n \tgrstctl_t resetctl = {.d32 = 0 };\n \tuint8_t temp;\n \tint ndx = 0;\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0363-gpio-fsm-Fix-a-build-warning.patch",
    "content": "From f6df23eb130f2407565db92e60b66a56b9b6fdea Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.com>\nDate: Tue, 27 Oct 2020 12:10:04 +0000\nSubject: [PATCH] gpio-fsm: Fix a build warning\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.com>\n---\n drivers/gpio/gpio-fsm.c | 3 ++-\n 1 file changed, 2 insertions(+), 1 deletion(-)\n\n--- a/drivers/gpio/gpio-fsm.c\n+++ b/drivers/gpio/gpio-fsm.c\n@@ -956,7 +956,8 @@ static int gpio_fsm_probe(struct platfor\n \t// add reserved words to the symbol table\n \tfor (i = 0; i < ARRAY_SIZE(reserved_symbols); i++) {\n \t\tif (reserved_symbols[i])\n-\t\t\tadd_symbol(&gf->symtab, reserved_symbols[i], (void *)i);\n+\t\t\tadd_symbol(&gf->symtab, reserved_symbols[i],\n+\t\t\t\t   (void *)(uintptr_t)i);\n \t}\n \n \t// parse the state\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0364-rpivid_h625-Fix-build-warnings.patch",
    "content": "From 9543aebf83bfe2a2e81a607dc8240ee3a9a1ce66 Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.com>\nDate: Tue, 27 Oct 2020 12:10:40 +0000\nSubject: [PATCH] rpivid_h625: Fix build warnings\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.com>\n---\n drivers/staging/media/rpivid/rpivid_h265.c | 16 ++++++++--------\n 1 file changed, 8 insertions(+), 8 deletions(-)\n\n--- a/drivers/staging/media/rpivid/rpivid_h265.c\n+++ b/drivers/staging/media/rpivid/rpivid_h265.c\n@@ -1341,10 +1341,10 @@ static int frame_end(struct rpivid_dev *\n \n \t\tif (gptr_realloc_new(dev, de->cmd_copy_gptr, cmd_alloc)) {\n \t\t\tv4l2_err(&dev->v4l2_dev,\n-\t\t\t\t \"Alloc cmd buffer (%d): FAILED\\n\", cmd_alloc);\n+\t\t\t\t \"Alloc cmd buffer (%zu): FAILED\\n\", cmd_alloc);\n \t\t\treturn -ENOMEM;\n \t\t}\n-\t\tv4l2_info(&dev->v4l2_dev, \"Alloc cmd buffer (%d): OK\\n\",\n+\t\tv4l2_info(&dev->v4l2_dev, \"Alloc cmd buffer (%zu): OK\\n\",\n \t\t\t  cmd_alloc);\n \t}\n \n@@ -1696,12 +1696,12 @@ static void rpivid_h265_setup(struct rpi\n \t\t\t\t       bits_alloc,\n \t\t\t\t       DMA_ATTR_FORCE_CONTIGUOUS) != 0) {\n \t\t\t\tv4l2_err(&dev->v4l2_dev,\n-\t\t\t\t\t \"Unable to alloc buf (%d) for bit copy\\n\",\n+\t\t\t\t\t \"Unable to alloc buf (%zu) for bit copy\\n\",\n \t\t\t\t\t bits_alloc);\n \t\t\t\tgoto fail;\n \t\t\t}\n \t\t\tv4l2_info(&dev->v4l2_dev,\n-\t\t\t\t  \"Alloc buf (%d) for bit copy OK\\n\",\n+\t\t\t\t  \"Alloc buf (%zu) for bit copy OK\\n\",\n \t\t\t\t  bits_alloc);\n \t\t}\n \t}\n@@ -1995,11 +1995,11 @@ static void phase1_thread(struct rpivid_\n \tif (de->p1_status & STATUS_PU_EXHAUSTED) {\n \t\tif (gptr_realloc_new(dev, pu_gptr, next_size(pu_gptr->size))) {\n \t\t\tv4l2_err(&dev->v4l2_dev,\n-\t\t\t\t \"%s: PU realloc (%#x) failed\\n\",\n+\t\t\t\t \"%s: PU realloc (%zx) failed\\n\",\n \t\t\t\t __func__, pu_gptr->size);\n \t\t\tgoto fail;\n \t\t}\n-\t\tv4l2_info(&dev->v4l2_dev, \"%s: PU realloc (%#x) OK\\n\",\n+\t\tv4l2_info(&dev->v4l2_dev, \"%s: PU realloc (%zx) OK\\n\",\n \t\t\t  __func__, pu_gptr->size);\n \t}\n \n@@ -2007,11 +2007,11 @@ static void phase1_thread(struct rpivid_\n \t\tif (gptr_realloc_new(dev, coeff_gptr,\n \t\t\t\t     next_size(coeff_gptr->size))) {\n \t\t\tv4l2_err(&dev->v4l2_dev,\n-\t\t\t\t \"%s: Coeff realloc (%#x) failed\\n\",\n+\t\t\t\t \"%s: Coeff realloc (%zx) failed\\n\",\n \t\t\t\t __func__, coeff_gptr->size);\n \t\t\tgoto fail;\n \t\t}\n-\t\tv4l2_info(&dev->v4l2_dev, \"%s: Coeff realloc (%#x) OK\\n\",\n+\t\tv4l2_info(&dev->v4l2_dev, \"%s: Coeff realloc (%zx) OK\\n\",\n \t\t\t  __func__, coeff_gptr->size);\n \t}\n \n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0365-bcm2708_fb-Fix-a-build-warning.patch",
    "content": "From c672997eca56c52f5ba42cd644168dcb35e52e4a Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.com>\nDate: Tue, 27 Oct 2020 12:12:22 +0000\nSubject: [PATCH] bcm2708_fb: Fix a build warning\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.com>\n---\n drivers/video/fbdev/bcm2708_fb.c | 3 ++-\n 1 file changed, 2 insertions(+), 1 deletion(-)\n\n--- a/drivers/video/fbdev/bcm2708_fb.c\n+++ b/drivers/video/fbdev/bcm2708_fb.c\n@@ -693,7 +693,8 @@ static long vc_mem_copy(struct bcm2708_f\n \t\tu8 *q = (u8 *)ioparam->dst + offset;\n \n \t\tdma_memcpy(fb, bus_addr,\n-\t\t\t   INTALIAS_L1L2_NONALLOCATING((dma_addr_t)p), size);\n+\t\t\t   INTALIAS_L1L2_NONALLOCATING((u32)(uintptr_t)p),\n+\t\t\t\t\t\t       size);\n \t\tif (copy_to_user(q, buf, s) != 0) {\n \t\t\tpr_err(\"[%s]: failed to copy-to-user\\n\", __func__);\n \t\t\trc = -EFAULT;\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0366-PiFi-40-Devicetree-files.patch",
    "content": "From 5dd5b4625a4435f64ee6a1c9f47e3609e771f14b Mon Sep 17 00:00:00 2001\nFrom: David Knell <david.knell@gmail.com>\nDate: Wed, 28 Oct 2020 14:20:56 +0000\nSubject: [PATCH] PiFi-40 Devicetree files\n\nSigned-off-by: David Knell <david.knell@gmail.com>\n---\n arch/arm/boot/dts/overlays/Makefile           |  1 +\n arch/arm/boot/dts/overlays/README             |  6 +++\n .../arm/boot/dts/overlays/pifi-40-overlay.dts | 50 +++++++++++++++++++\n 3 files changed, 57 insertions(+)\n create mode 100644 arch/arm/boot/dts/overlays/pifi-40-overlay.dts\n\n--- a/arch/arm/boot/dts/overlays/Makefile\n+++ b/arch/arm/boot/dts/overlays/Makefile\n@@ -125,6 +125,7 @@ dtbo-$(CONFIG_ARCH_BCM2835) += \\\n \tpca953x.dtbo \\\n \tpibell.dtbo \\\n \tpifacedigital.dtbo \\\n+\tpifi-40.dtbo \\\n \tpiglow.dtbo \\\n \tpiscreen.dtbo \\\n \tpiscreen2r.dtbo \\\n--- a/arch/arm/boot/dts/overlays/README\n+++ b/arch/arm/boot/dts/overlays/README\n@@ -2000,6 +2000,12 @@ Params: spi-present-mask        8-bit in\n                                 0-3, which can be configured with JP1 and JP2.\n \n \n+Name:   pifi-40\n+Info:   Configures the PiFi 40W stereo amplifier\n+Load:   dtoverlay=pifi-40\n+Params: <None>\n+\n+\n Name:   piglow\n Info:   Configures the PiGlow by pimoroni.com\n Load:   dtoverlay=piglow\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/pifi-40-overlay.dts\n@@ -0,0 +1,50 @@\n+// Definitions for PiFi-40 Amp\n+/dts-v1/;\n+/plugin/;\n+#include <dt-bindings/gpio/gpio.h>\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&i2s>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&i2c1>;\n+\t\t__overlay__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\ttas5711l: audio-codec@1a {\n+\t\t\t\tcompatible = \"ti,tas5711\";\n+\t\t\t\treg = <0x1a>;\n+\t\t\t\t#sound-dai-cells = <0>;\n+\t\t\t\tsound-name-prefix = \"Left\";\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\n+\t\t\ttas5711r: audio-codec@1b {\n+\t\t\t\tcompatible = \"ti,tas5711\";\n+\t\t\t\treg = <0x1b>;\n+\t\t\t\t#sound-dai-cells = <0>;\n+\t\t\t\tsound-name-prefix = \"Right\";\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&sound>;\n+\t\tpifi_40: __overlay__ {\n+\t\t\tcompatible = \"pifi,pifi-40\";\n+\t\t\taudio-codec = <&tas5711l &tas5711r>;\n+\t\t\ti2s-controller = <&i2s>;\n+\t\t\tpdn-gpios = <&gpio 23 1>;\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+};\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0367-PiFi-40-driver-Makefile-and-Kconfig.patch",
    "content": "From 0fa0f5932fff8c960862176fd61a7bccd2f28b90 Mon Sep 17 00:00:00 2001\nFrom: David Knell <david.knell@gmail.com>\nDate: Wed, 28 Oct 2020 14:21:37 +0000\nSubject: [PATCH] PiFi-40 driver, Makefile and Kconfig\n\nSigned-off-by: David Knell <david.knell@gmail.com>\n---\n sound/soc/bcm/Kconfig   |   8 ++\n sound/soc/bcm/Makefile  |   3 +\n sound/soc/bcm/pifi-40.c | 283 ++++++++++++++++++++++++++++++++++++++++\n 3 files changed, 294 insertions(+)\n create mode 100644 sound/soc/bcm/pifi-40.c\n\n--- a/sound/soc/bcm/Kconfig\n+++ b/sound/soc/bcm/Kconfig\n@@ -100,6 +100,14 @@ config SND_BCM2708_SOC_HIFIBERRY_AMP\n         help\n          Say Y or M if you want to add support for the HifiBerry Amp amplifier board.\n \n+ config SND_BCM2708_SOC_PIFI_40\n+         tristate \"Support for the PiFi-40 amp\"\n+         depends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S\n+         select SND_SOC_TAS571X\n+         select SND_PIFI_40\n+         help\n+          Say Y or M if you want to add support for the PiFi40 amp board\n+\n config SND_BCM2708_SOC_RPI_CIRRUS\n         tristate \"Support for Cirrus Logic Audio Card\"\n         depends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S\n--- a/sound/soc/bcm/Makefile\n+++ b/sound/soc/bcm/Makefile\n@@ -45,6 +45,7 @@ snd-soc-pisound-objs := pisound.o\n snd-soc-fe-pi-audio-objs := fe-pi-audio.o\n snd-soc-rpi-simple-soundcard-objs := rpi-simple-soundcard.o\n snd-soc-rpi-wm8804-soundcard-objs := rpi-wm8804-soundcard.o\n+snd-soc-pifi-40-objs := pifi-40.o\n \n obj-$(CONFIG_SND_BCM2708_SOC_GOOGLEVOICEHAT_SOUNDCARD)  += snd-soc-googlevoicehat-codec.o\n obj-$(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS) += snd-soc-hifiberry-dacplus.o\n@@ -74,3 +75,5 @@ obj-$(CONFIG_SND_PISOUND) += snd-soc-pis\n obj-$(CONFIG_SND_BCM2708_SOC_FE_PI_AUDIO) += snd-soc-fe-pi-audio.o\n obj-$(CONFIG_SND_RPI_SIMPLE_SOUNDCARD) += snd-soc-rpi-simple-soundcard.o\n obj-$(CONFIG_SND_RPI_WM8804_SOUNDCARD) += snd-soc-rpi-wm8804-soundcard.o\n+obj-$(CONFIG_SND_BCM2708_SOC_PIFI_40) += snd-soc-pifi-40.o\n+\n--- /dev/null\n+++ b/sound/soc/bcm/pifi-40.c\n@@ -0,0 +1,283 @@\n+// SPDX-License-Identifier: GPL-2.0-only\n+/*\n+ * ALSA ASoC Machine Driver for PiFi-40\n+ *\n+ * Author:\tDavid Knell <david.knell@gmail.com)\n+ *\t\tbased on code by Daniel Matuschek <info@crazy-audio.com>\n+ *\t\tbased on code by Florian Meier <florian.meier@koalo.de>\n+ * Copyright (C) 2020\n+ *\n+ * This program is free software; you can redistribute it and/or\n+ * modify it under the terms of the GNU General Public License\n+ * version 2 as published by the Free Software Foundation.\n+ *\n+ * This program is distributed in the hope that it will be useful, but\n+ * WITHOUT ANY WARRANTY; without even the implied warranty of\n+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU\n+ * General Public License for more details.\n+ */\n+\n+#include <linux/module.h>\n+#include <linux/platform_device.h>\n+#include <linux/gpio/consumer.h>\n+#include <sound/core.h>\n+#include <sound/pcm.h>\n+#include <sound/pcm_params.h>\n+#include <sound/soc.h>\n+#include <linux/firmware.h>\n+#include <linux/delay.h>\n+#include <sound/tlv.h>\n+\n+static struct gpio_desc *pdn_gpio;\n+static int vol = 0x30;\n+\n+// Volume control\n+static int pifi_40_vol_get(struct snd_kcontrol *kcontrol,\n+\t\t\t   struct snd_ctl_elem_value *ucontrol)\n+{\n+\tucontrol->value.integer.value[0] = vol;\n+\tucontrol->value.integer.value[1] = vol;\n+\treturn 0;\n+}\n+\n+static int pifi_40_vol_set(struct snd_kcontrol *kcontrol,\n+\t\t\t   struct snd_ctl_elem_value *ucontrol)\n+{\n+\tstruct snd_soc_card *card = snd_kcontrol_chip(kcontrol);\n+\tstruct snd_soc_pcm_runtime *rtd;\n+\tunsigned int v = ucontrol->value.integer.value[0];\n+\tstruct snd_soc_component *dac[2];\n+\n+\trtd = snd_soc_get_pcm_runtime(card, &card->dai_link[0]);\n+\tdac[0] = asoc_rtd_to_codec(rtd, 0)->component;\n+\tdac[1] = asoc_rtd_to_codec(rtd, 1)->component;\n+\n+\tsnd_soc_component_write(dac[0], 0x07, 255 - v);\n+\tsnd_soc_component_write(dac[1], 0x07, 255 - v);\n+\n+\tvol = v;\n+\treturn 1;\n+}\n+\n+static const DECLARE_TLV_DB_SCALE(digital_tlv_master, -10350, 50, 1);\n+static const struct snd_kcontrol_new pifi_40_controls[] = {\n+\tSOC_DOUBLE_R_EXT_TLV(\"Master Volume\", 0x00, 0x01,\n+\t\t\t     0x00, // Min\n+\t\t\t     0xff, // Max\n+\t\t\t     0x01, // Invert\n+\t\t\t     pifi_40_vol_get, pifi_40_vol_set,\n+\t\t\t     digital_tlv_master)\n+};\n+\n+static const char * const codec_ctl_pfx[] = { \"Left\", \"Right\" };\n+\n+static const char * const codec_ctl_name[] = { \"Master Volume\",\n+\t\t\t\t\t\"Speaker Volume\",\n+\t\t\t\t\t\"Speaker Switch\" };\n+\n+static int snd_pifi_40_init(struct snd_soc_pcm_runtime *rtd)\n+{\n+\tstruct snd_soc_card *card = rtd->card;\n+\tstruct snd_soc_component *dac[2];\n+\tstruct snd_kcontrol *kctl;\n+\tint i, j;\n+\n+\tdac[0] = asoc_rtd_to_codec(rtd, 0)->component;\n+\tdac[1] = asoc_rtd_to_codec(rtd, 1)->component;\n+\n+\n+\t// Set up cards - pulse power down first\n+\tgpiod_set_value_cansleep(pdn_gpio, 1);\n+\tusleep_range(1000, 10000);\n+\tgpiod_set_value_cansleep(pdn_gpio, 0);\n+\tusleep_range(20000, 30000);\n+\n+\t// Oscillator trim\n+\tsnd_soc_component_write(dac[0], 0x1b, 0);\n+\tsnd_soc_component_write(dac[1], 0x1b, 0);\n+\tusleep_range(60000, 80000);\n+\n+\t// Common setup\n+\tfor (i = 0; i < 2; i++) {\n+\t\t// MCLK at 64fs, sample rate 44.1 or 48kHz\n+\t\tsnd_soc_component_write(dac[i], 0x00, 0x60);\n+\n+\t\t// Set up for PBTL\n+\t\tsnd_soc_component_write(dac[i], 0x19, 0x3A);\n+\t\tsnd_soc_component_write(dac[i], 0x25, 0x01103245);\n+\n+\t\t// Master vol to -10db\n+\t\tsnd_soc_component_write(dac[i], 0x07, 0x44);\n+\t}\n+\t// Inputs set to L and R respectively\n+\tsnd_soc_component_write(dac[0], 0x20, 0x00017772);\n+\tsnd_soc_component_write(dac[1], 0x20, 0x00107772);\n+\n+\t// Remove codec controls\n+\tfor (i = 0; i < 2; i++) {\n+\t\tfor (j = 0; j < 3; j++) {\n+\t\t\tchar cname[256];\n+\n+\t\t\tsprintf(cname, \"%s %s\", codec_ctl_pfx[i],\n+\t\t\t\tcodec_ctl_name[j]);\n+\t\t\tkctl = snd_soc_card_get_kcontrol(card, cname);\n+\t\t\tif (!kctl) {\n+\t\t\t\tpr_info(\"Control %s not found\\n\",\n+\t\t\t\t       cname);\n+\t\t\t} else {\n+\t\t\t\tkctl->vd[0].access =\n+\t\t\t\t\tSNDRV_CTL_ELEM_ACCESS_READWRITE;\n+\t\t\t\tsnd_ctl_remove(card->snd_card, kctl);\n+\t\t\t}\n+\t\t}\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int snd_pifi_40_hw_params(struct snd_pcm_substream *substream,\n+\t\t\t\t struct snd_pcm_hw_params *params)\n+{\n+\tstruct snd_soc_pcm_runtime *rtd = substream->private_data;\n+\tstruct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);\n+\tunsigned int sample_bits;\n+\n+\tsample_bits = snd_pcm_format_physical_width(params_format(params));\n+\treturn snd_soc_dai_set_bclk_ratio(cpu_dai, 64);\n+}\n+\n+static struct snd_soc_ops snd_pifi_40_ops = { .hw_params =\n+\t\t\t\t\t\t      snd_pifi_40_hw_params };\n+\n+static struct snd_soc_dai_link_component pifi_40_codecs[] = {\n+\t{\n+\t\t.dai_name = \"tas571x-hifi\",\n+\t},\n+\t{\n+\t\t.dai_name = \"tas571x-hifi\",\n+\t},\n+};\n+\n+SND_SOC_DAILINK_DEFS(\n+\tpifi_40_dai, DAILINK_COMP_ARRAY(COMP_EMPTY()),\n+\tDAILINK_COMP_ARRAY(COMP_CODEC(\"tas571x.1-001a\", \"tas571x-hifi\"),\n+\t\t\t   COMP_CODEC(\"tas571x.1-001b\", \"tas571x-hifi\")),\n+\tDAILINK_COMP_ARRAY(COMP_EMPTY()));\n+\n+static struct snd_soc_dai_link snd_pifi_40_dai[] = {\n+\t{\n+\t\t.name = \"PiFi40\",\n+\t\t.stream_name = \"PiFi40\",\n+\t\t.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |\n+\t\t\t   SND_SOC_DAIFMT_CBS_CFS,\n+\t\t.ops = &snd_pifi_40_ops,\n+\t\t.init = snd_pifi_40_init,\n+\t\tSND_SOC_DAILINK_REG(pifi_40_dai),\n+\t},\n+};\n+\n+// Machine driver\n+static struct snd_soc_card snd_pifi_40 = {\n+\t.name = \"PiFi40\",\n+\t.owner = THIS_MODULE,\n+\t.dai_link = snd_pifi_40_dai,\n+\t.num_links = ARRAY_SIZE(snd_pifi_40_dai),\n+\t.controls = pifi_40_controls,\n+\t.num_controls = ARRAY_SIZE(pifi_40_controls)\n+};\n+\n+static void snd_pifi_40_pdn(struct snd_soc_card *card, int on)\n+{\n+\tif (pdn_gpio)\n+\t\tgpiod_set_value_cansleep(pdn_gpio, on ? 0 : 1);\n+}\n+\n+static int snd_pifi_40_probe(struct platform_device *pdev)\n+{\n+\tstruct snd_soc_card *card = &snd_pifi_40;\n+\tint ret = 0, i = 0;\n+\n+\tcard->dev = &pdev->dev;\n+\tplatform_set_drvdata(pdev, &snd_pifi_40);\n+\n+\tif (pdev->dev.of_node) {\n+\t\tstruct device_node *i2s_node;\n+\t\tstruct snd_soc_dai_link *dai;\n+\n+\t\tdai = &snd_pifi_40_dai[0];\n+\t\ti2s_node = of_parse_phandle(pdev->dev.of_node, \"i2s-controller\",\n+\t\t\t\t\t    0);\n+\t\tif (i2s_node) {\n+\t\t\tfor (i = 0; i < card->num_links; i++) {\n+\t\t\t\tdai->cpus->dai_name = NULL;\n+\t\t\t\tdai->cpus->of_node = i2s_node;\n+\t\t\t\tdai->platforms->name = NULL;\n+\t\t\t\tdai->platforms->of_node = i2s_node;\n+\t\t\t}\n+\t\t}\n+\n+\t\tpifi_40_codecs[0].of_node =\n+\t\t\tof_parse_phandle(pdev->dev.of_node, \"audio-codec\", 0);\n+\t\tpifi_40_codecs[1].of_node =\n+\t\t\tof_parse_phandle(pdev->dev.of_node, \"audio-codec\", 1);\n+\t\tif (!pifi_40_codecs[0].of_node || !pifi_40_codecs[1].of_node) {\n+\t\t\tdev_err(&pdev->dev,\n+\t\t\t\t\"Property 'audio-codec' missing or invalid\\n\");\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\n+\t\tpdn_gpio = devm_gpiod_get_optional(&pdev->dev, \"pdn\",\n+\t\t\t\t\t\t   GPIOD_OUT_LOW);\n+\t\tif (IS_ERR(pdn_gpio)) {\n+\t\t\tret = PTR_ERR(pdn_gpio);\n+\t\t\tdev_err(&pdev->dev, \"failed to get pdn gpio: %d\\n\",\n+\t\t\t\tret);\n+\t\t\treturn ret;\n+\t\t}\n+\n+\t\tret = snd_soc_register_card(&snd_pifi_40);\n+\t\tif (ret < 0) {\n+\t\t\tdev_err(&pdev->dev,\n+\t\t\t\t\"snd_soc_register_card() failed: %d\\n\", ret);\n+\t\t\treturn ret;\n+\t\t}\n+\n+\t\treturn 0;\n+\t}\n+\n+\treturn -EINVAL;\n+}\n+\n+static int snd_pifi_40_remove(struct platform_device *pdev)\n+{\n+\tstruct snd_soc_card *card = platform_get_drvdata(pdev);\n+\n+\tkfree(&card->drvdata);\n+\tsnd_pifi_40_pdn(&snd_pifi_40, 0);\n+\treturn snd_soc_unregister_card(&snd_pifi_40);\n+}\n+\n+static const struct of_device_id snd_pifi_40_of_match[] = {\n+\t{\n+\t\t.compatible = \"pifi,pifi-40\",\n+\t},\n+\t{ /* sentinel */ },\n+};\n+\n+MODULE_DEVICE_TABLE(of, snd_pifi_40_of_match);\n+\n+static struct platform_driver snd_pifi_40_driver = {\n+\t.driver = {\n+\t\t.name = \"snd-pifi-40\",\n+\t\t.owner = THIS_MODULE,\n+\t\t.of_match_table = snd_pifi_40_of_match,\n+\t},\n+\t.probe = snd_pifi_40_probe,\n+\t.remove = snd_pifi_40_remove,\n+};\n+\n+module_platform_driver(snd_pifi_40_driver);\n+\n+MODULE_AUTHOR(\"David Knell <david.knell@gmail.com>\");\n+MODULE_DESCRIPTION(\"ALSA ASoC Machine Driver for PiFi-40\");\n+MODULE_LICENSE(\"GPL v2\");\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0368-bcm2835-pcm-Fix-up-multichannel-pcm-audio.patch",
    "content": "From 658f2c37e37817ed680b85a5aa97a4661d0306a6 Mon Sep 17 00:00:00 2001\nFrom: Dom Cobley <popcornmix@gmail.com>\nDate: Tue, 27 Oct 2020 12:24:14 +0000\nSubject: [PATCH] bcm2835-pcm: Fix up multichannel pcm audio\n\nFixes: a9c1660ff5f02d048c5f31abf1fd1108ccf9ef87\nSigned-off-by: Dom Cobley <popcornmix@gmail.com>\n---\n .../vc04_services/bcm2835-audio/bcm2835-pcm.c | 21 +++++++++----------\n 1 file changed, 10 insertions(+), 11 deletions(-)\n\n--- a/drivers/staging/vc04_services/bcm2835-audio/bcm2835-pcm.c\n+++ b/drivers/staging/vc04_services/bcm2835-audio/bcm2835-pcm.c\n@@ -14,14 +14,14 @@ static const struct snd_pcm_hardware snd\n \t\t SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_MMAP_VALID |\n \t\t SNDRV_PCM_INFO_SYNC_APPLPTR),\n \t.formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,\n-\t.rates = SNDRV_PCM_RATE_CONTINUOUS |  SNDRV_PCM_RATE_8000_192000,\n+\t.rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_192000,\n \t.rate_min = 8000,\n \t.rate_max = 192000,\n \t.channels_min = 1,\n-\t.channels_max = 2,\n-\t.buffer_bytes_max = 128 * 1024,\n+\t.channels_max = 8,\n+\t.buffer_bytes_max = 512 * 1024,\n \t.period_bytes_min = 1 * 1024,\n-\t.period_bytes_max = 128 * 1024,\n+\t.period_bytes_max = 512 * 1024,\n \t.periods_min = 1,\n \t.periods_max = 128,\n };\n@@ -31,16 +31,15 @@ static const struct snd_pcm_hardware snd\n \t\t SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_MMAP_VALID |\n \t\t SNDRV_PCM_INFO_SYNC_APPLPTR),\n \t.formats = SNDRV_PCM_FMTBIT_S16_LE,\n-\t.rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\n-\tSNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 |\n-\tSNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000,\n+\t.rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_44100 |\n+\tSNDRV_PCM_RATE_48000,\n \t.rate_min = 44100,\n-\t.rate_max = 192000,\n+\t.rate_max = 48000,\n \t.channels_min = 2,\n-\t.channels_max = 8,\n-\t.buffer_bytes_max = 512 * 1024,\n+\t.channels_max = 2,\n+\t.buffer_bytes_max = 128 * 1024,\n \t.period_bytes_min = 1 * 1024,\n-\t.period_bytes_max = 512 * 1024,\n+\t.period_bytes_max = 128 * 1024,\n \t.periods_min = 1,\n \t.periods_max = 128,\n };\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0369-watchdog-bcm2835-Ignore-params-after-the-partition-n.patch",
    "content": "From c518032ec09c3e21872a5b2f9114655d55d9ade1 Mon Sep 17 00:00:00 2001\nFrom: Tim Gover <tim.gover@raspberrypi.org>\nDate: Thu, 22 Oct 2020 15:30:55 +0100\nSubject: [PATCH] watchdog: bcm2835: Ignore params after the partition\n number\n\nUse sscanf to extract the partition number and ignore extra parameters\nwhich are only relevant to other reboot notifiers.\n---\n drivers/watchdog/bcm2835_wdt.c | 6 ++++--\n 1 file changed, 4 insertions(+), 2 deletions(-)\n\n--- a/drivers/watchdog/bcm2835_wdt.c\n+++ b/drivers/watchdog/bcm2835_wdt.c\n@@ -126,10 +126,12 @@ static int bcm2835_restart(struct watchd\n {\n \tstruct bcm2835_wdt *wdt = watchdog_get_drvdata(wdog);\n \n-\tunsigned long long val;\n+\tunsigned long val;\n \tu8 partition = 0;\n \n-\tif (data && !kstrtoull(data, 0, &val) && val <= 63)\n+\t// Allow extra arguments separated by spaces after\n+\t// the partition number.\n+\tif (data && sscanf(data, \"%lu\", &val) && val < 63)\n \t\tpartition = val;\n \n \t__bcm2835_restart(wdt, partition);\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0370-firmware-raspberrypi-Add-support-for-tryonce-reboot-.patch",
    "content": "From e32f7ddc830c3388a68dfe34881bce32afded0b9 Mon Sep 17 00:00:00 2001\nFrom: Tim Gover <tim.gover@raspberrypi.com>\nDate: Tue, 20 Oct 2020 11:55:37 +0100\nSubject: [PATCH] firmware: raspberrypi: Add support for tryonce reboot\n flag\n\nDefine a new mailbox (SET_REBOOT_FLAGS) which may be used to\npass optional flags to the Raspberry Pi firmware that changes\nthe behaviour of the bootloader and firmware during a reboot.\n\nCurrently this just defines the 'tryboot' flag which causes\nthe firmware to load tryboot.txt instead config.txt. This\nalternate configuration file can be used to specify the\npath of an alternate firmware and kernels allowing a fallback\nmechanism to be implemented for OS upgrades.\n---\n drivers/firmware/raspberrypi.c             | 25 ++++++++++++++++++++--\n include/soc/bcm2835/raspberrypi-firmware.h |  2 ++\n 2 files changed, 25 insertions(+), 2 deletions(-)\n\n--- a/drivers/firmware/raspberrypi.c\n+++ b/drivers/firmware/raspberrypi.c\n@@ -194,6 +194,7 @@ static int rpi_firmware_notify_reboot(st\n {\n \tstruct rpi_firmware *fw;\n \tstruct platform_device *pdev = g_pdev;\n+\tu32 reboot_flags = 0;\n \n \tif (!pdev)\n \t\treturn 0;\n@@ -202,8 +203,28 @@ static int rpi_firmware_notify_reboot(st\n \tif (!fw)\n \t\treturn 0;\n \n-\t(void)rpi_firmware_property(fw, RPI_FIRMWARE_NOTIFY_REBOOT,\n-\t\t\t\t    0, 0);\n+\t// The partition id is the first parameter followed by zero or\n+\t// more flags separated by spaces indicating the reason for the reboot.\n+\t//\n+\t// 'tryboot': Sets a one-shot flag which is cleared upon reboot and\n+\t//            causes the tryboot.txt to be loaded instead of config.txt\n+\t//            by the bootloader and the start.elf firmware.\n+\t//\n+\t//            This is intended to allow automatic fallback to a known\n+\t//            good image if an OS/FW upgrade fails.\n+\t//\n+\t// N.B. The firmware mechanism for storing reboot flags may vary\n+\t// on different Raspberry Pi models.\n+\tif (data && strstr(data, \" tryboot\"))\n+\t\treboot_flags |= 0x1;\n+\n+\t// The mailbox might have been called earlier, directly via vcmailbox\n+\t// so only overwrite if reboot flags are passed to the reboot command.\n+\tif (reboot_flags)\n+\t\t(void)rpi_firmware_property(fw, RPI_FIRMWARE_SET_REBOOT_FLAGS,\n+\t\t\t\t&reboot_flags, sizeof(reboot_flags));\n+\n+\t(void)rpi_firmware_property(fw, RPI_FIRMWARE_NOTIFY_REBOOT, NULL, 0);\n \n \treturn 0;\n }\n--- a/include/soc/bcm2835/raspberrypi-firmware.h\n+++ b/include/soc/bcm2835/raspberrypi-firmware.h\n@@ -96,6 +96,8 @@ enum rpi_firmware_property_tag {\n \tRPI_FIRMWARE_GET_POE_HAT_VAL =                        0x00030049,\n \tRPI_FIRMWARE_SET_POE_HAT_VAL =                        0x00030050,\n \tRPI_FIRMWARE_NOTIFY_XHCI_RESET =                      0x00030058,\n+\tRPI_FIRMWARE_GET_REBOOT_FLAGS =                       0x00030064,\n+\tRPI_FIRMWARE_SET_REBOOT_FLAGS =                       0x00038064,\n \n \t/* Dispmanx TAGS */\n \tRPI_FIRMWARE_FRAMEBUFFER_ALLOCATE =                   0x00040001,\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0371-phy-broadcom-split-out-the-BCM54213PE-from-the-BCM54.patch",
    "content": "From 7b0e9b30aaf78bddfcb589be0686846076f23f62 Mon Sep 17 00:00:00 2001\nFrom: Jonathan Bell <jonathan@raspberrypi.org>\nDate: Tue, 14 May 2019 17:00:41 +0100\nSubject: [PATCH] phy: broadcom: split out the BCM54213PE from the\n BCM54210E IDs\n\nThe last nibble is a revision ID, and the 54213pe is a later rev\nthan the 54210e. Running the 54210e setup code on a 54213pe results\nin a broken RGMII interface.\n\nSigned-off-by: Jonathan Bell <jonathan@raspberrypi.org>\n---\n drivers/net/phy/broadcom.c | 16 +++++++++++++---\n include/linux/brcmphy.h    |  1 +\n 2 files changed, 14 insertions(+), 3 deletions(-)\n\n--- a/drivers/net/phy/broadcom.c\n+++ b/drivers/net/phy/broadcom.c\n@@ -253,7 +253,8 @@ static void bcm54xx_adjust_rxrefclk(stru\n \t    BRCM_PHY_MODEL(phydev) != PHY_ID_BCM50610 &&\n \t    BRCM_PHY_MODEL(phydev) != PHY_ID_BCM50610M &&\n \t    BRCM_PHY_MODEL(phydev) != PHY_ID_BCM54810 &&\n-\t    BRCM_PHY_MODEL(phydev) != PHY_ID_BCM54811)\n+\t    BRCM_PHY_MODEL(phydev) != PHY_ID_BCM54811 &&\n+\t    BRCM_PHY_MODEL(phydev) != PHY_ID_BCM54213PE)\n \t\treturn;\n \n \tval = bcm_phy_read_shadow(phydev, BCM54XX_SHD_SCR3);\n@@ -784,13 +785,21 @@ static struct phy_driver broadcom_driver\n \t.config_intr\t= bcm_phy_config_intr,\n }, {\n \t.phy_id\t\t= PHY_ID_BCM54210E,\n-\t.phy_id_mask\t= 0xfffffff0,\n+\t.phy_id_mask\t= 0xffffffff,\n \t.name\t\t= \"Broadcom BCM54210E\",\n \t/* PHY_GBIT_FEATURES */\n \t.config_init\t= bcm54xx_config_init,\n \t.ack_interrupt\t= bcm_phy_ack_intr,\n \t.config_intr\t= bcm_phy_config_intr,\n }, {\n+\t.phy_id\t\t= PHY_ID_BCM54213PE,\n+\t.phy_id_mask\t= 0xffffffff,\n+\t.name\t\t= \"Broadcom BCM54213PE\",\n+\t/* PHY_GBIT_FEATURES */\n+\t.config_init\t= bcm54xx_config_init,\n+\t.ack_interrupt\t= bcm_phy_ack_intr,\n+\t.config_intr\t= bcm_phy_config_intr,\n+}, {\n \t.phy_id\t\t= PHY_ID_BCM5461,\n \t.phy_id_mask\t= 0xfffffff0,\n \t.name\t\t= \"Broadcom BCM5461\",\n@@ -946,7 +955,8 @@ module_phy_driver(broadcom_drivers);\n static struct mdio_device_id __maybe_unused broadcom_tbl[] = {\n \t{ PHY_ID_BCM5411, 0xfffffff0 },\n \t{ PHY_ID_BCM5421, 0xfffffff0 },\n-\t{ PHY_ID_BCM54210E, 0xfffffff0 },\n+\t{ PHY_ID_BCM54210E, 0xffffffff },\n+\t{ PHY_ID_BCM54213PE, 0xffffffff },\n \t{ PHY_ID_BCM5461, 0xfffffff0 },\n \t{ PHY_ID_BCM54612E, 0xfffffff0 },\n \t{ PHY_ID_BCM54616S, 0xfffffff0 },\n--- a/include/linux/brcmphy.h\n+++ b/include/linux/brcmphy.h\n@@ -22,6 +22,7 @@\n #define PHY_ID_BCM5411\t\t\t0x00206070\n #define PHY_ID_BCM5421\t\t\t0x002060e0\n #define PHY_ID_BCM54210E\t\t0x600d84a0\n+#define PHY_ID_BCM54213PE\t\t0x600d84a2\n #define PHY_ID_BCM5464\t\t\t0x002060b0\n #define PHY_ID_BCM5461\t\t\t0x002060c0\n #define PHY_ID_BCM54612E\t\t0x03625e60\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0372-phy-broadcom-Add-bcm54213pe-configuration.patch",
    "content": "From 066277e9437e41fea9c59455cc575b51a918af0c Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.com>\nDate: Thu, 29 Oct 2020 14:10:56 +0000\nSubject: [PATCH] phy: broadcom: Add bcm54213pe configuration\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.com>\n---\n drivers/net/phy/broadcom.c | 8 ++++++++\n 1 file changed, 8 insertions(+)\n\n--- a/drivers/net/phy/broadcom.c\n+++ b/drivers/net/phy/broadcom.c\n@@ -83,6 +83,11 @@ static int bcm54210e_config_init(struct\n \treturn 0;\n }\n \n+static int bcm54213pe_config_init(struct phy_device *phydev)\n+{\n+\treturn bcm54210e_config_init(phydev);\n+}\n+\n static int bcm54612e_config_init(struct phy_device *phydev)\n {\n \tint reg;\n@@ -358,6 +363,9 @@ static int bcm54xx_config_init(struct ph\n \tcase PHY_ID_BCM54616S:\n \t\terr = bcm54616s_config_init(phydev);\n \t\tbreak;\n+\tcase PHY_ID_BCM54213PE:\n+\t\terr = bcm54213pe_config_init(phydev);\n+\t\tbreak;\n \tcase PHY_ID_BCM54810:\n \t\t/* For BCM54810, we need to disable BroadR-Reach function */\n \t\tval = bcm_phy_read_exp(phydev,\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0373-overlays-Add-MAX31856-support-to-maxtherm-overlay.patch",
    "content": "From 9444edfa8b5b18f8727b82853dd50345a400a316 Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.com>\nDate: Thu, 22 Oct 2020 17:11:12 +0100\nSubject: [PATCH] overlays: Add MAX31856 support to maxtherm overlay\n\nExtend the maxtherm overlay with support for the MAX31856.\nThe driver reads the thermocouple type from a property, which is much\nmore civilised.\n\nSee: https://github.com/raspberrypi/linux/issues/3915\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.com>\n---\n arch/arm/boot/dts/overlays/README             | 18 ++++++++++++-----\n .../boot/dts/overlays/maxtherm-overlay.dts    | 20 +++++++++++++++++++\n 2 files changed, 33 insertions(+), 5 deletions(-)\n\n--- a/arch/arm/boot/dts/overlays/README\n+++ b/arch/arm/boot/dts/overlays/README\n@@ -1666,20 +1666,19 @@ Params: no-sdmode               Driver d\n \n \n Name:   maxtherm\n-Info:   Configure a MAX6675 or MAX31855 thermocouple as an IIO device.\n+Info:   Configure a MAX6675, MAX31855 or MAX31856 thermocouple as an IIO device.\n \n         For devices on spi1 or spi2, the interfaces should be enabled\n         with one of the spi1-1/2/3cs and/or spi2-1/2/3cs overlays.\n         The overlay expects to disable the relevant spidev node, so also using\n         e.g. cs0_spidev=off is unnecessary.\n \n-        Note:   with the 5.7 kernel (and later) there will also be\n-                overlays for MAX31855E, MAX31855J, MAX31855K,\n-                MAX31885N, MAX31855R, MAX31855S and MAX31855T.\n-\n         Example:\n         MAX31855 on /dev/spidev0.0\n             dtoverlay=maxtherm,spi0-0,max31855\n+        MAX31856 using a type J thermocouple on /dev/spidev2.1\n+            dtoverlay=spi2-2cs\n+            dtoverlay=maxtherm,spi2-1,max31856,type_j\n \n Load:   dtoverlay=maxtherm,<param>=<val>\n Params: spi<n>-<m>              Configure device at spi<n>, cs<m>\n@@ -1693,6 +1692,15 @@ Params: spi<n>-<m>              Configur\n         max31855r               Enable support for the MAX31855R\n         max31855s               Enable support for the MAX31855S\n         max31855t               Enable support for the MAX31855T\n+        max31856                Enable support for the MAX31856 (with type K)\n+        type_b                  Select a type B sensor for max31856\n+        type_e                  Select a type E sensor for max31856\n+        type_j                  Select a type J sensor for max31856\n+        type_k                  Select a type K sensor for max31856\n+        type_n                  Select a type N sensor for max31856\n+        type_r                  Select a type R sensor for max31856\n+        type_s                  Select a type S sensor for max31856\n+        type_t                  Select a type T sensor for max31856\n \n \n Name:   mbed-dac\n--- a/arch/arm/boot/dts/overlays/maxtherm-overlay.dts\n+++ b/arch/arm/boot/dts/overlays/maxtherm-overlay.dts\n@@ -5,6 +5,8 @@\n /dts-v1/;\n /plugin/;\n \n+#include <dt-bindings/iio/temperature/thermocouple.h>\n+\n / {\n \tcompatible = \"brcm,bcm2835\";\n \n@@ -128,6 +130,15 @@\n \t\t};\n \t};\n \n+\tfragment@16 {\n+\t\ttarget = <&max>;\n+\t\t__dormant__ {\n+\t\t\tcompatible = \"maxim,max31856\";\n+\t\t\tspi-cpha;\n+\t\t\tthermocouple-type = <THERMOCOUPLE_TYPE_K>;\n+\t\t};\n+\t};\n+\n \t__overrides__ {\n \t\tspi0-0 = <0>, \"+0\",\n \t\t\t <&maxfrag>,\"target:0=\",<&spi0>,\n@@ -162,5 +173,14 @@\n \t\tmax31855r = <0>,\"+13\";\n \t\tmax31855s = <0>,\"+14\";\n \t\tmax31855t = <0>,\"+15\";\n+\t\tmax31856  = <0>,\"+16\";\n+\t\ttype_b    = <&max>,\"thermocouple-type:0=\",<THERMOCOUPLE_TYPE_B>;\n+\t\ttype_e    = <&max>,\"thermocouple-type:0=\",<THERMOCOUPLE_TYPE_E>;\n+\t\ttype_j    = <&max>,\"thermocouple-type:0=\",<THERMOCOUPLE_TYPE_J>;\n+\t\ttype_k    = <&max>,\"thermocouple-type:0=\",<THERMOCOUPLE_TYPE_K>;\n+\t\ttype_n    = <&max>,\"thermocouple-type:0=\",<THERMOCOUPLE_TYPE_N>;\n+\t\ttype_r    = <&max>,\"thermocouple-type:0=\",<THERMOCOUPLE_TYPE_R>;\n+\t\ttype_s    = <&max>,\"thermocouple-type:0=\",<THERMOCOUPLE_TYPE_S>;\n+\t\ttype_t    = <&max>,\"thermocouple-type:0=\",<THERMOCOUPLE_TYPE_T>;\n \t};\n };\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0374-ARM-dts-Add-bcm2711-rpi-400.dts.patch",
    "content": "From 57e4984d7b342860d635155c13bf747d2c225e26 Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.com>\nDate: Tue, 14 Jul 2020 14:21:33 +0100\nSubject: [PATCH] ARM: dts: Add bcm2711-rpi-400.dts\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.com>\n---\n arch/arm/boot/dts/Makefile                    |   1 +\n arch/arm/boot/dts/bcm2711-rpi-400.dts         | 615 ++++++++++++++++++\n arch/arm64/boot/dts/broadcom/Makefile         |   1 +\n .../boot/dts/broadcom/bcm2711-rpi-400.dts     |   1 +\n 4 files changed, 618 insertions(+)\n create mode 100644 arch/arm/boot/dts/bcm2711-rpi-400.dts\n create mode 100644 arch/arm64/boot/dts/broadcom/bcm2711-rpi-400.dts\n\n--- a/arch/arm/boot/dts/Makefile\n+++ b/arch/arm/boot/dts/Makefile\n@@ -12,6 +12,7 @@ dtb-$(CONFIG_ARCH_BCM2835) += \\\n \tbcm2710-rpi-3-b.dtb \\\n \tbcm2710-rpi-3-b-plus.dtb \\\n \tbcm2711-rpi-4-b.dtb \\\n+\tbcm2711-rpi-400.dtb \\\n \tbcm2710-rpi-cm3.dtb \\\n \tbcm2711-rpi-cm4.dtb\n \n--- /dev/null\n+++ b/arch/arm/boot/dts/bcm2711-rpi-400.dts\n@@ -0,0 +1,615 @@\n+// SPDX-License-Identifier: GPL-2.0\n+/dts-v1/;\n+#include \"bcm2711.dtsi\"\n+#include \"bcm2835-rpi.dtsi\"\n+\n+#include <dt-bindings/reset/raspberrypi,firmware-reset.h>\n+\n+/ {\n+\tcompatible = \"raspberrypi,400\", \"brcm,bcm2711\";\n+\tmodel = \"Raspberry Pi 400\";\n+\n+\tchosen {\n+\t\t/* 8250 auxiliary UART instead of pl011 */\n+\t\tstdout-path = \"serial1:115200n8\";\n+\t};\n+\n+\t/* Will be filled by the bootloader */\n+\tmemory@0 {\n+\t\tdevice_type = \"memory\";\n+\t\treg = <0 0 0>;\n+\t};\n+\n+\taliases {\n+\t\temmc2bus = &emmc2bus;\n+\t\tethernet0 = &genet;\n+\t\tpcie0 = &pcie0;\n+\t};\n+\n+\tleds {\n+\t\tact {\n+\t\t\tgpios = <&gpio 42 GPIO_ACTIVE_HIGH>;\n+\t\t};\n+\n+\t\tpwr {\n+\t\t\tlabel = \"PWR\";\n+\t\t\tgpios = <&expgpio 2 GPIO_ACTIVE_LOW>;\n+\t\t\tdefault-state = \"keep\";\n+\t\t\tlinux,default-trigger = \"default-on\";\n+\t\t};\n+\t};\n+\n+\twifi_pwrseq: wifi-pwrseq {\n+\t\tcompatible = \"mmc-pwrseq-simple\";\n+\t\treset-gpios = <&expgpio 1 GPIO_ACTIVE_LOW>;\n+\t};\n+\n+\tsd_io_1v8_reg: sd_io_1v8_reg {\n+\t\tcompatible = \"regulator-gpio\";\n+\t\tregulator-name = \"vdd-sd-io\";\n+\t\tregulator-min-microvolt = <1800000>;\n+\t\tregulator-max-microvolt = <3300000>;\n+\t\tregulator-boot-on;\n+\t\tregulator-always-on;\n+\t\tregulator-settling-time-us = <5000>;\n+\t\tgpios = <&expgpio 4 GPIO_ACTIVE_HIGH>;\n+\t\tstates = <1800000 0x1\n+\t\t\t  3300000 0x0>;\n+\t\tstatus = \"okay\";\n+\t};\n+\n+\tsd_vcc_reg: sd_vcc_reg {\n+\t\tcompatible = \"regulator-fixed\";\n+\t\tregulator-name = \"vcc-sd\";\n+\t\tregulator-min-microvolt = <3300000>;\n+\t\tregulator-max-microvolt = <3300000>;\n+\t\tregulator-boot-on;\n+\t\tenable-active-high;\n+\t\tgpio = <&expgpio 6 GPIO_ACTIVE_HIGH>;\n+\t};\n+};\n+\n+&ddc0 {\n+\tstatus = \"okay\";\n+};\n+\n+&ddc1 {\n+\tstatus = \"okay\";\n+};\n+\n+&firmware {\n+\tfirmware_clocks: clocks {\n+\t\tcompatible = \"raspberrypi,firmware-clocks\";\n+\t\t#clock-cells = <1>;\n+\t};\n+\n+\texpgpio: gpio {\n+\t\tcompatible = \"raspberrypi,firmware-gpio\";\n+\t\tgpio-controller;\n+\t\t#gpio-cells = <2>;\n+\t\tgpio-line-names = \"BT_ON\",\n+\t\t\t\t  \"WL_ON\",\n+\t\t\t\t  \"PWR_LED_OFF\",\n+\t\t\t\t  \"GLOBAL_RESET\",\n+\t\t\t\t  \"VDD_SD_IO_SEL\",\n+\t\t\t\t  \"CAM_GPIO\",\n+\t\t\t\t  \"SD_PWR_ON\",\n+\t\t\t\t  \"SD_OC_N\";\n+\t\tstatus = \"okay\";\n+\t};\n+\n+\treset: reset {\n+\t\tcompatible = \"raspberrypi,firmware-reset\";\n+\t\t#reset-cells = <1>;\n+\t};\n+};\n+\n+&gpio {\n+\t/*\n+\t * Parts taken from rpi_SCH_4b_4p0_reduced.pdf and\n+\t * the official GPU firmware DT blob.\n+\t *\n+\t * Legend:\n+\t * \"FOO\" = GPIO line named \"FOO\" on the schematic\n+\t * \"FOO_N\" = GPIO line named \"FOO\" on schematic, active low\n+\t */\n+\tgpio-line-names = \"ID_SDA\",\n+\t\t\t  \"ID_SCL\",\n+\t\t\t  \"SDA1\",\n+\t\t\t  \"SCL1\",\n+\t\t\t  \"GPIO_GCLK\",\n+\t\t\t  \"GPIO5\",\n+\t\t\t  \"GPIO6\",\n+\t\t\t  \"SPI_CE1_N\",\n+\t\t\t  \"SPI_CE0_N\",\n+\t\t\t  \"SPI_MISO\",\n+\t\t\t  \"SPI_MOSI\",\n+\t\t\t  \"SPI_SCLK\",\n+\t\t\t  \"GPIO12\",\n+\t\t\t  \"GPIO13\",\n+\t\t\t  /* Serial port */\n+\t\t\t  \"TXD1\",\n+\t\t\t  \"RXD1\",\n+\t\t\t  \"GPIO16\",\n+\t\t\t  \"GPIO17\",\n+\t\t\t  \"GPIO18\",\n+\t\t\t  \"GPIO19\",\n+\t\t\t  \"GPIO20\",\n+\t\t\t  \"GPIO21\",\n+\t\t\t  \"GPIO22\",\n+\t\t\t  \"GPIO23\",\n+\t\t\t  \"GPIO24\",\n+\t\t\t  \"GPIO25\",\n+\t\t\t  \"GPIO26\",\n+\t\t\t  \"GPIO27\",\n+\t\t\t  \"RGMII_MDIO\",\n+\t\t\t  \"RGMIO_MDC\",\n+\t\t\t  /* Used by BT module */\n+\t\t\t  \"CTS0\",\n+\t\t\t  \"RTS0\",\n+\t\t\t  \"TXD0\",\n+\t\t\t  \"RXD0\",\n+\t\t\t  /* Used by Wifi */\n+\t\t\t  \"SD1_CLK\",\n+\t\t\t  \"SD1_CMD\",\n+\t\t\t  \"SD1_DATA0\",\n+\t\t\t  \"SD1_DATA1\",\n+\t\t\t  \"SD1_DATA2\",\n+\t\t\t  \"SD1_DATA3\",\n+\t\t\t  /* Shared with SPI flash */\n+\t\t\t  \"PWM0_MISO\",\n+\t\t\t  \"PWM1_MOSI\",\n+\t\t\t  \"STATUS_LED_G_CLK\",\n+\t\t\t  \"SPIFLASH_CE_N\",\n+\t\t\t  \"SDA0\",\n+\t\t\t  \"SCL0\",\n+\t\t\t  \"RGMII_RXCLK\",\n+\t\t\t  \"RGMII_RXCTL\",\n+\t\t\t  \"RGMII_RXD0\",\n+\t\t\t  \"RGMII_RXD1\",\n+\t\t\t  \"RGMII_RXD2\",\n+\t\t\t  \"RGMII_RXD3\",\n+\t\t\t  \"RGMII_TXCLK\",\n+\t\t\t  \"RGMII_TXCTL\",\n+\t\t\t  \"RGMII_TXD0\",\n+\t\t\t  \"RGMII_TXD1\",\n+\t\t\t  \"RGMII_TXD2\",\n+\t\t\t  \"RGMII_TXD3\";\n+};\n+\n+&hdmi0 {\n+\tclocks = <&firmware_clocks 13>, <&firmware_clocks 14>, <&dvp 0>, <&clk_27MHz>;\n+\tclock-names = \"hdmi\", \"bvb\", \"audio\", \"cec\";\n+\tstatus = \"okay\";\n+};\n+\n+&hdmi1 {\n+\tclocks = <&firmware_clocks 13>, <&firmware_clocks 14>, <&dvp 1>, <&clk_27MHz>;\n+\tclock-names = \"hdmi\", \"bvb\", \"audio\", \"cec\";\n+\tstatus = \"okay\";\n+};\n+\n+&hvs {\n+\tclocks = <&firmware_clocks 4>;\n+};\n+\n+&pixelvalve0 {\n+\tstatus = \"okay\";\n+};\n+\n+&pixelvalve1 {\n+\tstatus = \"okay\";\n+};\n+\n+&pixelvalve2 {\n+\tstatus = \"okay\";\n+};\n+\n+&pixelvalve4 {\n+\tstatus = \"okay\";\n+};\n+\n+&pwm1 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pwm1_0_gpio40 &pwm1_1_gpio41>;\n+\tstatus = \"okay\";\n+};\n+\n+/* SDHCI is used to control the SDIO for wireless */\n+&sdhci {\n+\t#address-cells = <1>;\n+\t#size-cells = <0>;\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&emmc_gpio34>;\n+\tbus-width = <4>;\n+\tnon-removable;\n+\tmmc-pwrseq = <&wifi_pwrseq>;\n+\tstatus = \"okay\";\n+\n+\tbrcmf: wifi@1 {\n+\t\treg = <1>;\n+\t\tcompatible = \"brcm,bcm4329-fmac\";\n+\t};\n+};\n+\n+/* EMMC2 is used to drive the SD card */\n+&emmc2 {\n+\tvqmmc-supply = <&sd_io_1v8_reg>;\n+\tvmmc-supply = <&sd_vcc_reg>;\n+\tbroken-cd;\n+\tstatus = \"okay\";\n+};\n+\n+&genet {\n+\tphy-handle = <&phy1>;\n+\tphy-mode = \"rgmii-rxid\";\n+\tstatus = \"okay\";\n+};\n+\n+&genet_mdio {\n+\tphy1: ethernet-phy@1 {\n+\t\t/* No PHY interrupt */\n+\t\treg = <0x1>;\n+\t};\n+};\n+\n+&pcie0 {\n+\tpci@1,0 {\n+\t\t#address-cells = <3>;\n+\t\t#size-cells = <2>;\n+\t\tranges;\n+\n+\t\treg = <0 0 0 0 0>;\n+\n+\t\tusb@1,0 {\n+\t\t\treg = <0x10000 0 0 0 0>;\n+\t\t\tresets = <&reset RASPBERRYPI_FIRMWARE_RESET_ID_USB>;\n+\t\t};\n+\t};\n+};\n+\n+/* uart0 communicates with the BT module */\n+&uart0 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&uart0_ctsrts_gpio30 &uart0_gpio32>;\n+\tuart-has-rtscts;\n+\tstatus = \"okay\";\n+\n+\tbluetooth {\n+\t\tcompatible = \"brcm,bcm43438-bt\";\n+\t\tmax-speed = <2000000>;\n+\t\tshutdown-gpios = <&expgpio 0 GPIO_ACTIVE_HIGH>;\n+\t};\n+};\n+\n+/* uart1 is mapped to the pin header */\n+&uart1 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&uart1_gpio14>;\n+\tstatus = \"okay\";\n+};\n+\n+&vchiq {\n+\tinterrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;\n+};\n+\n+&vc4 {\n+\tstatus = \"okay\";\n+};\n+\n+&vec {\n+\tstatus = \"disabled\";\n+};\n+\n+// =============================================\n+// Downstream rpi- changes\n+\n+#define BCM2711\n+\n+#include \"bcm270x.dtsi\"\n+#include \"bcm271x-rpi-bt.dtsi\"\n+\n+/ {\n+\tsoc {\n+\t\t/delete-node/ pixelvalve@7e807000;\n+\t\t/delete-node/ hdmi@7e902000;\n+\t};\n+};\n+\n+#include \"bcm2711-rpi.dtsi\"\n+#include \"bcm283x-rpi-csi1-2lane.dtsi\"\n+#include \"bcm283x-rpi-i2c0mux_0_44.dtsi\"\n+\n+/ {\n+\tchosen {\n+\t\tbootargs = \"coherent_pool=1M 8250.nr_uarts=1 snd_bcm2835.enable_compat_alsa=0 snd_bcm2835.enable_hdmi=1 snd_bcm2835.enable_headphones=1\";\n+\t};\n+\n+\taliases {\n+\t\tserial0 = &uart1;\n+\t\tserial1 = &uart0;\n+\t\tmmc0 = &emmc2;\n+\t\tmmc1 = &mmcnr;\n+\t\tmmc2 = &sdhost;\n+\t\t/delete-property/ i2c2;\n+\t\ti2c3 = &i2c3;\n+\t\ti2c4 = &i2c4;\n+\t\ti2c5 = &i2c5;\n+\t\ti2c6 = &i2c6;\n+\t\t/delete-property/ intc;\n+\t};\n+\n+\t/delete-node/ wifi-pwrseq;\n+};\n+\n+&mmcnr {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&sdio_pins>;\n+\tbus-width = <4>;\n+\tstatus = \"okay\";\n+};\n+\n+&uart0 {\n+\tpinctrl-0 = <&uart0_pins &bt_pins>;\n+\tstatus = \"okay\";\n+};\n+\n+&uart1 {\n+\tpinctrl-0 = <&uart1_pins>;\n+};\n+\n+&spi0 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&spi0_pins &spi0_cs_pins>;\n+\tcs-gpios = <&gpio 8 1>, <&gpio 7 1>;\n+\n+\tspidev0: spidev@0{\n+\t\tcompatible = \"spidev\";\n+\t\treg = <0>;\t/* CE0 */\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\tspi-max-frequency = <125000000>;\n+\t};\n+\n+\tspidev1: spidev@1{\n+\t\tcompatible = \"spidev\";\n+\t\treg = <1>;\t/* CE1 */\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\tspi-max-frequency = <125000000>;\n+\t};\n+};\n+\n+&gpio {\n+\tspi0_pins: spi0_pins {\n+\t\tbrcm,pins = <9 10 11>;\n+\t\tbrcm,function = <BCM2835_FSEL_ALT0>;\n+\t};\n+\n+\tspi0_cs_pins: spi0_cs_pins {\n+\t\tbrcm,pins = <8 7>;\n+\t\tbrcm,function = <BCM2835_FSEL_GPIO_OUT>;\n+\t};\n+\n+\tspi3_pins: spi3_pins {\n+\t\tbrcm,pins = <1 2 3>;\n+\t\tbrcm,function = <BCM2835_FSEL_ALT3>;\n+\t};\n+\n+\tspi3_cs_pins: spi3_cs_pins {\n+\t\tbrcm,pins = <0 24>;\n+\t\tbrcm,function = <BCM2835_FSEL_GPIO_OUT>;\n+\t};\n+\n+\tspi4_pins: spi4_pins {\n+\t\tbrcm,pins = <5 6 7>;\n+\t\tbrcm,function = <BCM2835_FSEL_ALT3>;\n+\t};\n+\n+\tspi4_cs_pins: spi4_cs_pins {\n+\t\tbrcm,pins = <4 25>;\n+\t\tbrcm,function = <BCM2835_FSEL_GPIO_OUT>;\n+\t};\n+\n+\tspi5_pins: spi5_pins {\n+\t\tbrcm,pins = <13 14 15>;\n+\t\tbrcm,function = <BCM2835_FSEL_ALT3>;\n+\t};\n+\n+\tspi5_cs_pins: spi5_cs_pins {\n+\t\tbrcm,pins = <12 26>;\n+\t\tbrcm,function = <BCM2835_FSEL_GPIO_OUT>;\n+\t};\n+\n+\tspi6_pins: spi6_pins {\n+\t\tbrcm,pins = <19 20 21>;\n+\t\tbrcm,function = <BCM2835_FSEL_ALT3>;\n+\t};\n+\n+\tspi6_cs_pins: spi6_cs_pins {\n+\t\tbrcm,pins = <18 27>;\n+\t\tbrcm,function = <BCM2835_FSEL_GPIO_OUT>;\n+\t};\n+\n+\ti2c0_pins: i2c0 {\n+\t\tbrcm,pins = <0 1>;\n+\t\tbrcm,function = <BCM2835_FSEL_ALT0>;\n+\t\tbrcm,pull = <BCM2835_PUD_UP>;\n+\t};\n+\n+\ti2c1_pins: i2c1 {\n+\t\tbrcm,pins = <2 3>;\n+\t\tbrcm,function = <BCM2835_FSEL_ALT0>;\n+\t\tbrcm,pull = <BCM2835_PUD_UP>;\n+\t};\n+\n+\ti2c3_pins: i2c3 {\n+\t\tbrcm,pins = <4 5>;\n+\t\tbrcm,function = <BCM2835_FSEL_ALT5>;\n+\t\tbrcm,pull = <BCM2835_PUD_UP>;\n+\t};\n+\n+\ti2c4_pins: i2c4 {\n+\t\tbrcm,pins = <8 9>;\n+\t\tbrcm,function = <BCM2835_FSEL_ALT5>;\n+\t\tbrcm,pull = <BCM2835_PUD_UP>;\n+\t};\n+\n+\ti2c5_pins: i2c5 {\n+\t\tbrcm,pins = <12 13>;\n+\t\tbrcm,function = <BCM2835_FSEL_ALT5>;\n+\t\tbrcm,pull = <BCM2835_PUD_UP>;\n+\t};\n+\n+\ti2c6_pins: i2c6 {\n+\t\tbrcm,pins = <22 23>;\n+\t\tbrcm,function = <BCM2835_FSEL_ALT5>;\n+\t\tbrcm,pull = <BCM2835_PUD_UP>;\n+\t};\n+\n+\ti2s_pins: i2s {\n+\t\tbrcm,pins = <18 19 20 21>;\n+\t\tbrcm,function = <BCM2835_FSEL_ALT0>;\n+\t};\n+\n+\tsdio_pins: sdio_pins {\n+\t\tbrcm,pins =     <34 35 36 37 38 39>;\n+\t\tbrcm,function = <BCM2835_FSEL_ALT3>; // alt3 = SD1\n+\t\tbrcm,pull =     <0 2 2 2 2 2>;\n+\t};\n+\n+\tbt_pins: bt_pins {\n+\t\tbrcm,pins = \"-\"; // non-empty to keep btuart happy, //4 = 0\n+\t\t\t\t // to fool pinctrl\n+\t\tbrcm,function = <0>;\n+\t\tbrcm,pull = <2>;\n+\t};\n+\n+\tuart0_pins: uart0_pins {\n+\t\tbrcm,pins = <32 33>;\n+\t\tbrcm,function = <BCM2835_FSEL_ALT3>;\n+\t\tbrcm,pull = <0 2>;\n+\t};\n+\n+\tuart1_pins: uart1_pins {\n+\t\tbrcm,pins;\n+\t\tbrcm,function;\n+\t\tbrcm,pull;\n+\t};\n+\n+\tuart2_pins: uart2_pins {\n+\t\tbrcm,pins = <0 1>;\n+\t\tbrcm,function = <BCM2835_FSEL_ALT4>;\n+\t\tbrcm,pull = <0 2>;\n+\t};\n+\n+\tuart3_pins: uart3_pins {\n+\t\tbrcm,pins = <4 5>;\n+\t\tbrcm,function = <BCM2835_FSEL_ALT4>;\n+\t\tbrcm,pull = <0 2>;\n+\t};\n+\n+\tuart4_pins: uart4_pins {\n+\t\tbrcm,pins = <8 9>;\n+\t\tbrcm,function = <BCM2835_FSEL_ALT4>;\n+\t\tbrcm,pull = <0 2>;\n+\t};\n+\n+\tuart5_pins: uart5_pins {\n+\t\tbrcm,pins = <12 13>;\n+\t\tbrcm,function = <BCM2835_FSEL_ALT4>;\n+\t\tbrcm,pull = <0 2>;\n+\t};\n+};\n+\n+&i2c0if {\n+\tclock-frequency = <100000>;\n+};\n+\n+&i2c1 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&i2c1_pins>;\n+\tclock-frequency = <100000>;\n+};\n+\n+&i2s {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&i2s_pins>;\n+};\n+\n+/ {\n+\t__overrides__ {\n+\t\t/delete-property/ i2c2_baudrate;\n+\t\t/delete-property/ i2c2_iknowwhatimdoing;\n+\t};\n+};\n+\n+// =============================================\n+// Board specific stuff here\n+\n+/ {\n+\tpower_ctrl: power_ctrl {\n+\t\tcompatible = \"gpio-poweroff\";\n+\t\tgpios = <&expgpio 5 0>;\n+\t\tforce;\n+\t};\n+};\n+\n+&sdhost {\n+\tstatus = \"disabled\";\n+};\n+\n+&phy1 {\n+\tled-modes = <0x00 0x08>; /* link/activity link */\n+};\n+\n+&gpio {\n+\taudio_pins: audio_pins {\n+\t\tbrcm,pins = <40 41>;\n+\t\tbrcm,function = <4>;\n+\t};\n+};\n+\n+&leds {\n+\tact_led: act {\n+\t\tlabel = \"led0\";\n+\t\tlinux,default-trigger = \"default-on\";\n+\t\tdefault-state = \"on\";\n+\t\tgpios = <&gpio 42 GPIO_ACTIVE_HIGH>;\n+\t};\n+\n+\tpwr_led: pwr {\n+\t\tlabel = \"led1\";\n+\t\tlinux,default-trigger = \"default-on\";\n+\t\tgpios = <&expgpio 2 GPIO_ACTIVE_LOW>;\n+\t};\n+};\n+\n+&pwm1 {\n+\tstatus = \"disabled\";\n+};\n+\n+&audio {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&audio_pins>;\n+\tbrcm,disable-headphones = <1>;\n+};\n+\n+/ {\n+\t__overrides__ {\n+\t\tact_led_gpio = <&act_led>,\"gpios:4\";\n+\t\tact_led_activelow = <&act_led>,\"gpios:8\";\n+\t\tact_led_trigger = <&act_led>,\"linux,default-trigger\";\n+\n+\t\tpwr_led_gpio = <&pwr_led>,\"gpios:4\";\n+\t\tpwr_led_activelow = <&pwr_led>,\"gpios:8\";\n+\t\tpwr_led_trigger = <&pwr_led>,\"linux,default-trigger\";\n+\n+\t\teth_led0 = <&phy1>,\"led-modes:0\";\n+\t\teth_led1 = <&phy1>,\"led-modes:4\";\n+\n+\t\tsd_poll_once = <&emmc2>, \"non-removable?\";\n+\t\tspi_dma4 = <&spi0>, \"dmas:0=\", <&dma40>,\n+\t\t\t   <&spi0>, \"dmas:8=\", <&dma40>;\n+\t};\n+};\n--- a/arch/arm64/boot/dts/broadcom/Makefile\n+++ b/arch/arm64/boot/dts/broadcom/Makefile\n@@ -7,6 +7,7 @@ dtb-$(CONFIG_ARCH_BCM2835) += bcm2710-rp\n dtb-$(CONFIG_ARCH_BCM2835) += bcm2710-rpi-3-b.dtb\n dtb-$(CONFIG_ARCH_BCM2835) += bcm2710-rpi-3-b-plus.dtb\n dtb-$(CONFIG_ARCH_BCM2835) += bcm2711-rpi-4-b.dtb\n+dtb-$(CONFIG_ARCH_BCM2835) += bcm2711-rpi-400.dtb\n dtb-$(CONFIG_ARCH_BCM2835) += bcm2710-rpi-cm3.dtb\n dtb-$(CONFIG_ARCH_BCM2835) += bcm2711-rpi-cm4.dtb\n \n--- /dev/null\n+++ b/arch/arm64/boot/dts/broadcom/bcm2711-rpi-400.dts\n@@ -0,0 +1 @@\n+#include \"../../../../arm/boot/dts/bcm2711-rpi-400.dts\"\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0375-overlays-Deprecate-and-delete-the-sdtweak-overlay.patch",
    "content": "From 068c8b508a0501de9bda9d6d9a8c4ddc06cf7ff8 Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.com>\nDate: Wed, 4 Nov 2020 11:25:02 +0000\nSubject: [PATCH] overlays: Deprecate and delete the sdtweak overlay\n\nThe sdtweak overlay has been superseded by the board-specific\nsd_* parameters such as sd_poll_once, sd_overclock etc.\n\nFor example, replace:\n\n    dtoverlay=sdtweak,poll_once\n\nwith:\n\n    dtparam=sd_poll_once\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.com>\n---\n arch/arm/boot/dts/overlays/Makefile           |  1 -\n arch/arm/boot/dts/overlays/README             | 27 +++----------------\n arch/arm/boot/dts/overlays/overlay_map.dts    |  4 +++\n .../arm/boot/dts/overlays/sdtweak-overlay.dts | 25 -----------------\n 4 files changed, 8 insertions(+), 49 deletions(-)\n delete mode 100644 arch/arm/boot/dts/overlays/sdtweak-overlay.dts\n\n--- a/arch/arm/boot/dts/overlays/Makefile\n+++ b/arch/arm/boot/dts/overlays/Makefile\n@@ -158,7 +158,6 @@ dtbo-$(CONFIG_ARCH_BCM2835) += \\\n \tsc16is752-spi1.dtbo \\\n \tsdhost.dtbo \\\n \tsdio.dtbo \\\n-\tsdtweak.dtbo \\\n \tsh1106-spi.dtbo \\\n \tsmi.dtbo \\\n \tsmi-dev.dtbo \\\n--- a/arch/arm/boot/dts/overlays/README\n+++ b/arch/arm/boot/dts/overlays/README\n@@ -2409,29 +2409,10 @@ Load:   <Deprecated>\n \n \n Name:   sdtweak\n-Info:   Tunes the bcm2835-sdhost SD/MMC driver\n-        N.B. This functionality is now available via the sd_* dtparams in the\n-        base DTB.\n-Load:   dtoverlay=sdtweak,<param>=<val>\n-Params: overclock_50            Clock (in MHz) to use when the MMC framework\n-                                requests 50MHz\n-\n-        force_pio               Disable DMA support (default off)\n-\n-        pio_limit               Number of blocks above which to use DMA\n-                                (default 1)\n-\n-        debug                   Enable debug output (default off)\n-\n-        poll_once               Looks for a card once after booting. Useful\n-                                for network booting scenarios to avoid the\n-                                overhead of continuous polling. N.B. Using\n-                                this option restricts the system to using a\n-                                single card per boot (or none at all).\n-                                (default off)\n-\n-        enable                  Set to off to completely disable the interface\n-                                (default on)\n+Info:   This overlay is now deprecated. Use the sd_* dtparams in the\n+        base DTB, e.g. \"dtoverlay=sdtweak,poll_once\" becomes\n+        \"dtparam=sd_poll_once\".\n+Load:   <Deprecated>\n \n \n Name:   sh1106-spi\n--- a/arch/arm/boot/dts/overlays/overlay_map.dts\n+++ b/arch/arm/boot/dts/overlays/overlay_map.dts\n@@ -61,6 +61,10 @@\n \t\tdeprecated = \"use sdio,bus_width=1,gpios_22_25\";\n \t};\n \n+\tsdtweak {\n+\t\tdeprecated = \"use 'dtparam=sd_poll_once' etc.\";\n+\t};\n+\n \tspi0-cs {\n \t\trenamed = \"spi0-2cs\";\n \t};\n--- a/arch/arm/boot/dts/overlays/sdtweak-overlay.dts\n+++ /dev/null\n@@ -1,25 +0,0 @@\n-/dts-v1/;\n-/plugin/;\n-\n-/* Provide backwards compatible aliases for the old sdhost dtparams. */\n-\n-/{\n-\tcompatible = \"brcm,bcm2835\";\n-\n-\tfragment@0 {\n-\t\ttarget = <&sdhost>;\n-\t\tfrag0: __overlay__ {\n-\t\t\tbrcm,overclock-50 = <0>;\n-\t\t\tbrcm,pio-limit = <1>;\n-\t\t};\n-\t};\n-\n-\t__overrides__ {\n-\t\toverclock_50     = <&frag0>,\"brcm,overclock-50:0\";\n-\t\tforce_pio        = <&frag0>,\"brcm,force-pio?\";\n-\t\tpio_limit        = <&frag0>,\"brcm,pio-limit:0\";\n-\t\tdebug            = <&frag0>,\"brcm,debug?\";\n-\t\tenable           = <&frag0>,\"status\";\n-\t\tpoll_once        = <&frag0>,\"non-removable?\";\n-\t};\n-};\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0376-ARM-dts-bcm27xx-Remove-enable_headphones-setting.patch",
    "content": "From 5ec30e3d930de9ca7bddbb8ef6b367c0bc89306f Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.com>\nDate: Thu, 5 Nov 2020 11:39:35 +0000\nSubject: [PATCH] ARM: dts: bcm27xx: Remove enable_headphones setting\n\nThe enable_headphones parameter of the snd_bcm2835 module is forced\nto 1 if enable_compat_alsa is 0, so setting them both on the kernel\ncommand line is pointless (and, in the case of Pi 400 and Pi Zeroes,\nconfusing).\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.com>\n---\n arch/arm/boot/dts/bcm2708-rpi-zero-w.dts   | 2 +-\n arch/arm/boot/dts/bcm2708-rpi-zero.dts     | 2 +-\n arch/arm/boot/dts/bcm270x.dtsi             | 2 +-\n arch/arm/boot/dts/bcm2710-rpi-3-b-plus.dts | 2 +-\n arch/arm/boot/dts/bcm2710-rpi-3-b.dts      | 2 +-\n arch/arm/boot/dts/bcm2711-rpi-4-b.dts      | 2 +-\n arch/arm/boot/dts/bcm2711-rpi-400.dts      | 2 +-\n arch/arm/boot/dts/bcm2711-rpi-cm4.dts      | 2 +-\n 8 files changed, 8 insertions(+), 8 deletions(-)\n\n--- a/arch/arm/boot/dts/bcm2708-rpi-zero-w.dts\n+++ b/arch/arm/boot/dts/bcm2708-rpi-zero-w.dts\n@@ -11,7 +11,7 @@\n \tmodel = \"Raspberry Pi Zero W\";\n \n \tchosen {\n-\t\tbootargs = \"coherent_pool=1M 8250.nr_uarts=1 snd_bcm2835.enable_compat_alsa=0 snd_bcm2835.enable_hdmi=1 snd_bcm2835.enable_headphones=1\";\n+\t\tbootargs = \"coherent_pool=1M 8250.nr_uarts=1 snd_bcm2835.enable_compat_alsa=0 snd_bcm2835.enable_hdmi=1\";\n \t};\n \n \taliases {\n--- a/arch/arm/boot/dts/bcm2708-rpi-zero.dts\n+++ b/arch/arm/boot/dts/bcm2708-rpi-zero.dts\n@@ -10,7 +10,7 @@\n \tmodel = \"Raspberry Pi Zero\";\n \n \tchosen {\n-\t\tbootargs = \"coherent_pool=1M snd_bcm2835.enable_compat_alsa=0 snd_bcm2835.enable_hdmi=1 snd_bcm2835.enable_headphones=1\";\n+\t\tbootargs = \"coherent_pool=1M snd_bcm2835.enable_compat_alsa=0 snd_bcm2835.enable_hdmi=1\";\n \t};\n };\n \n--- a/arch/arm/boot/dts/bcm270x.dtsi\n+++ b/arch/arm/boot/dts/bcm270x.dtsi\n@@ -3,7 +3,7 @@\n \n / {\n \tchosen {\n-\t\tbootargs = \"coherent_pool=1M snd_bcm2835.enable_compat_alsa=0 snd_bcm2835.enable_hdmi=1 snd_bcm2835.enable_headphones=1\";\n+\t\tbootargs = \"coherent_pool=1M snd_bcm2835.enable_compat_alsa=0 snd_bcm2835.enable_hdmi=1\";\n \t\t/delete-property/ stdout-path;\n \t};\n \n--- a/arch/arm/boot/dts/bcm2710-rpi-3-b-plus.dts\n+++ b/arch/arm/boot/dts/bcm2710-rpi-3-b-plus.dts\n@@ -12,7 +12,7 @@\n \tmodel = \"Raspberry Pi 3 Model B+\";\n \n \tchosen {\n-\t\tbootargs = \"coherent_pool=1M 8250.nr_uarts=1 snd_bcm2835.enable_compat_alsa=0 snd_bcm2835.enable_hdmi=1 snd_bcm2835.enable_headphones=1\";\n+\t\tbootargs = \"coherent_pool=1M 8250.nr_uarts=1 snd_bcm2835.enable_compat_alsa=0 snd_bcm2835.enable_hdmi=1\";\n \t};\n \n \taliases {\n--- a/arch/arm/boot/dts/bcm2710-rpi-3-b.dts\n+++ b/arch/arm/boot/dts/bcm2710-rpi-3-b.dts\n@@ -12,7 +12,7 @@\n \tmodel = \"Raspberry Pi 3 Model B\";\n \n \tchosen {\n-\t\tbootargs = \"coherent_pool=1M 8250.nr_uarts=1 snd_bcm2835.enable_compat_alsa=0 snd_bcm2835.enable_hdmi=1 snd_bcm2835.enable_headphones=1\";\n+\t\tbootargs = \"coherent_pool=1M 8250.nr_uarts=1 snd_bcm2835.enable_compat_alsa=0 snd_bcm2835.enable_hdmi=1\";\n \t};\n \n \taliases {\n--- a/arch/arm/boot/dts/bcm2711-rpi-4-b.dts\n+++ b/arch/arm/boot/dts/bcm2711-rpi-4-b.dts\n@@ -323,7 +323,7 @@\n \n / {\n \tchosen {\n-\t\tbootargs = \"coherent_pool=1M 8250.nr_uarts=1 snd_bcm2835.enable_compat_alsa=0 snd_bcm2835.enable_hdmi=1 snd_bcm2835.enable_headphones=1\";\n+\t\tbootargs = \"coherent_pool=1M 8250.nr_uarts=1 snd_bcm2835.enable_compat_alsa=0 snd_bcm2835.enable_hdmi=1\";\n \t};\n \n \taliases {\n--- a/arch/arm/boot/dts/bcm2711-rpi-400.dts\n+++ b/arch/arm/boot/dts/bcm2711-rpi-400.dts\n@@ -322,7 +322,7 @@\n \n / {\n \tchosen {\n-\t\tbootargs = \"coherent_pool=1M 8250.nr_uarts=1 snd_bcm2835.enable_compat_alsa=0 snd_bcm2835.enable_hdmi=1 snd_bcm2835.enable_headphones=1\";\n+\t\tbootargs = \"coherent_pool=1M 8250.nr_uarts=1 snd_bcm2835.enable_compat_alsa=0 snd_bcm2835.enable_hdmi=1\";\n \t};\n \n \taliases {\n--- a/arch/arm/boot/dts/bcm2711-rpi-cm4.dts\n+++ b/arch/arm/boot/dts/bcm2711-rpi-cm4.dts\n@@ -309,7 +309,7 @@\n \n / {\n \tchosen {\n-\t\tbootargs = \"coherent_pool=1M 8250.nr_uarts=1 snd_bcm2835.enable_compat_alsa=0 snd_bcm2835.enable_hdmi=1 snd_bcm2835.enable_headphones=1\";\n+\t\tbootargs = \"coherent_pool=1M 8250.nr_uarts=1 snd_bcm2835.enable_compat_alsa=0 snd_bcm2835.enable_hdmi=1\";\n \t};\n \n \taliases {\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0377-vc4_hdmi-Report-that-3d-stereo-is-allowed.patch",
    "content": "From cf945bde1fe7db593bfaab44505f9cd5246c49b6 Mon Sep 17 00:00:00 2001\nFrom: Dom Cobley <popcornmix@gmail.com>\nDate: Mon, 9 Nov 2020 19:49:32 +0000\nSubject: [PATCH] vc4_hdmi: Report that 3d/stereo is allowed\n\nSigned-off-by: Dom Cobley <popcornmix@gmail.com>\n---\n drivers/gpu/drm/vc4/vc4_hdmi.c | 1 +\n 1 file changed, 1 insertion(+)\n\n--- a/drivers/gpu/drm/vc4/vc4_hdmi.c\n+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c\n@@ -257,6 +257,7 @@ static int vc4_hdmi_connector_init(struc\n \n \tconnector->interlace_allowed = 1;\n \tconnector->doublescan_allowed = 0;\n+\tconnector->stereo_allowed = 1;\n \n \tdrm_connector_attach_encoder(connector, encoder);\n \n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0378-PCI-brcmstb-Restore-initial-fundamental-reset.patch",
    "content": "From 92f08923793d755a2eb1bf4724c6b6764cfba071 Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.com>\nDate: Wed, 11 Nov 2020 17:08:33 +0000\nSubject: [PATCH] PCI: brcmstb: Restore initial fundamental reset\n\n[1] replaced a single reset function with a pointer to one of two\nimplementations, but also removed the call asserting the reset\nat the start of brcm_pcie_setup. Doing so breaks Raspberry Pis with\nVL805 XHCI controllers lacking dedicated SPI EEPROMs, which have been\nused for USB booting but then need to be reset so that the kernel\ncan reconfigure them. The lack of a reset causes the firmware's loading\nof the EEPROM image to RAM to fail, breaking USB for the kernel.\n\nSee: https://www.raspberrypi.org/forums/viewtopic.php?p=1758157#p1758157\n\nFixes: 04356ac30771 (\"PCI: brcmstb: Add bcm7278 PERST# support\")\n\n[1] 04356ac30771 (\"PCI: brcmstb: Add bcm7278 PERST# support\")\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.com>\n---\n drivers/pci/controller/pcie-brcmstb.c | 2 ++\n 1 file changed, 2 insertions(+)\n\n--- a/drivers/pci/controller/pcie-brcmstb.c\n+++ b/drivers/pci/controller/pcie-brcmstb.c\n@@ -871,6 +871,8 @@ static int brcm_pcie_setup(struct brcm_p\n \n \t/* Reset the bridge */\n \tpcie->bridge_sw_init_set(pcie, 1);\n+\tpcie->perst_set(pcie, 1);\n+\n \tusleep_range(100, 200);\n \n \t/* Take the bridge out of reset */\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0379-vc4-Clear-unused-infoframe-packet-RAM-registers.patch",
    "content": "From cd097b7d08cef3c0e79f5d2ab2776c6c6b00a869 Mon Sep 17 00:00:00 2001\nFrom: Dom Cobley <popcornmix@gmail.com>\nDate: Tue, 10 Nov 2020 20:04:08 +0000\nSubject: [PATCH] vc4: Clear unused infoframe packet RAM registers\n\nUsing a hdmi analyser the bytes in packet ram\nregisters beyond the length were visible in the\ninfoframes and it flagged the checksum as invalid.\n\nZeroing unused words of packet RAM avoids this\n\nSigned-off-by: Dom Cobley <popcornmix@gmail.com>\n---\n drivers/gpu/drm/vc4/vc4_hdmi.c | 11 ++++++++++-\n 1 file changed, 10 insertions(+), 1 deletion(-)\n\n--- a/drivers/gpu/drm/vc4/vc4_hdmi.c\n+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c\n@@ -285,9 +285,11 @@ static void vc4_hdmi_write_infoframe(str\n \tconst struct vc4_hdmi_register *ram_packet_start =\n \t\t&vc4_hdmi->variant->registers[HDMI_RAM_PACKET_START];\n \tu32 packet_reg = ram_packet_start->offset + VC4_HDMI_PACKET_STRIDE * packet_id;\n+\tu32 packet_reg_next = ram_packet_start->offset +\n+\t\tVC4_HDMI_PACKET_STRIDE * (packet_id + 1);\n \tvoid __iomem *base = __vc4_hdmi_get_field_base(vc4_hdmi,\n \t\t\t\t\t\t       ram_packet_start->reg);\n-\tuint8_t buffer[VC4_HDMI_PACKET_STRIDE];\n+\tuint8_t buffer[VC4_HDMI_PACKET_STRIDE] = {};\n \tssize_t len, i;\n \tint ret;\n \n@@ -320,6 +322,13 @@ static void vc4_hdmi_write_infoframe(str\n \t\tpacket_reg += 4;\n \t}\n \n+\t/*\n+\t * clear remainder of packet ram as it's included in the\n+\t * infoframe and triggers a checksum error on hdmi analyser\n+\t */\n+\tfor (; packet_reg < packet_reg_next; packet_reg += 4)\n+\t\twritel(0, base + packet_reg);\n+\n \tHDMI_WRITE(HDMI_RAM_PACKET_CONFIG,\n \t\t   HDMI_READ(HDMI_RAM_PACKET_CONFIG) | BIT(packet_id));\n \tret = wait_for((HDMI_READ(HDMI_RAM_PACKET_STATUS) &\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0380-Input-edt-ft5x06-Poll-the-device-if-no-interrupt-is-.patch",
    "content": "From d7763e8128b7697f5521e08f097f455d20aab5be Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Fri, 6 Nov 2020 18:45:10 +0000\nSubject: [PATCH] Input: edt-ft5x06: Poll the device if no interrupt is\n configured.\n\nNot all systems have the interrupt line wired up, so switch to\npolling the touchscreen off a timer if no interrupt line is\nconfigured.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n drivers/input/touchscreen/edt-ft5x06.c | 51 +++++++++++++++++++++-----\n 1 file changed, 41 insertions(+), 10 deletions(-)\n\n--- a/drivers/input/touchscreen/edt-ft5x06.c\n+++ b/drivers/input/touchscreen/edt-ft5x06.c\n@@ -69,6 +69,8 @@\n #define EDT_RAW_DATA_RETRIES\t\t100\n #define EDT_RAW_DATA_DELAY\t\t1000 /* usec */\n \n+#define POLL_INTERVAL_MS\t\t17\t/* 17ms = 60fps */\n+\n enum edt_pmode {\n \tEDT_PMODE_NOT_SUPPORTED,\n \tEDT_PMODE_HIBERNATE,\n@@ -126,6 +128,9 @@ struct edt_ft5x06_ts_data {\n \n \tstruct edt_reg_addr reg_addr;\n \tenum edt_ver version;\n+\n+\tstruct timer_list timer;\n+\tstruct work_struct work_i2c_poll;\n };\n \n struct edt_i2c_chip_data {\n@@ -275,6 +280,22 @@ out:\n \treturn IRQ_HANDLED;\n }\n \n+static void edt_ft5x06_ts_irq_poll_timer(struct timer_list *t)\n+{\n+\tstruct edt_ft5x06_ts_data *tsdata = from_timer(tsdata, t, timer);\n+\n+\tschedule_work(&tsdata->work_i2c_poll);\n+\tmod_timer(&tsdata->timer, jiffies + msecs_to_jiffies(POLL_INTERVAL_MS));\n+}\n+\n+static void edt_ft5x06_ts_work_i2c_poll(struct work_struct *work)\n+{\n+\tstruct edt_ft5x06_ts_data *tsdata = container_of(work,\n+\t\t\tstruct edt_ft5x06_ts_data, work_i2c_poll);\n+\n+\tedt_ft5x06_ts_isr(0, tsdata);\n+}\n+\n static int edt_ft5x06_register_write(struct edt_ft5x06_ts_data *tsdata,\n \t\t\t\t     u8 addr, u8 value)\n {\n@@ -1221,17 +1242,27 @@ static int edt_ft5x06_ts_probe(struct i2\n \n \ti2c_set_clientdata(client, tsdata);\n \n-\tirq_flags = irq_get_trigger_type(client->irq);\n-\tif (irq_flags == IRQF_TRIGGER_NONE)\n-\t\tirq_flags = IRQF_TRIGGER_FALLING;\n-\tirq_flags |= IRQF_ONESHOT;\n-\n-\terror = devm_request_threaded_irq(&client->dev, client->irq,\n-\t\t\t\t\tNULL, edt_ft5x06_ts_isr, irq_flags,\n-\t\t\t\t\tclient->name, tsdata);\n-\tif (error) {\n-\t\tdev_err(&client->dev, \"Unable to request touchscreen IRQ.\\n\");\n-\t\treturn error;\n+\tif (client->irq) {\n+\t\tirq_flags = irq_get_trigger_type(client->irq);\n+\t\tif (irq_flags == IRQF_TRIGGER_NONE)\n+\t\t\tirq_flags = IRQF_TRIGGER_FALLING;\n+\t\tirq_flags |= IRQF_ONESHOT;\n+\n+\t\terror = devm_request_threaded_irq(&client->dev, client->irq,\n+\t\t\t\t\t\t  NULL, edt_ft5x06_ts_isr,\n+\t\t\t\t\t\t  irq_flags, client->name,\n+\t\t\t\t\t\t  tsdata);\n+\t\tif (error) {\n+\t\t\tdev_err(&client->dev, \"Unable to request touchscreen IRQ.\\n\");\n+\t\t\treturn error;\n+\t\t}\n+\t} else {\n+\t\tINIT_WORK(&tsdata->work_i2c_poll,\n+\t\t\t  edt_ft5x06_ts_work_i2c_poll);\n+\t\ttimer_setup(&tsdata->timer, edt_ft5x06_ts_irq_poll_timer, 0);\n+\t\ttsdata->timer.expires = jiffies +\n+\t\t\t\t\tmsecs_to_jiffies(POLL_INTERVAL_MS);\n+\t\tadd_timer(&tsdata->timer);\n \t}\n \n \terror = devm_device_add_group(&client->dev, &edt_ft5x06_attr_group);\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0381-dtoverlays-Add-an-overlay-for-the-EDT-FT5406-touchsc.patch",
    "content": "From e7972981794db2cfa349aa5d34171f83d4ffe830 Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Fri, 6 Nov 2020 18:52:25 +0000\nSubject: [PATCH] dtoverlays: Add an overlay for the EDT FT5406\n touchscreen\n\nThis touchscreen controller is used by the 7\" DSI panel, and\nthis overlay configures it for when it is NOT being polled by\nthe firmware.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n arch/arm/boot/dts/overlays/Makefile           |  1 +\n arch/arm/boot/dts/overlays/README             | 14 +++++++\n .../boot/dts/overlays/edt-ft5406-overlay.dts  | 42 +++++++++++++++++++\n 3 files changed, 57 insertions(+)\n create mode 100644 arch/arm/boot/dts/overlays/edt-ft5406-overlay.dts\n\n--- a/arch/arm/boot/dts/overlays/Makefile\n+++ b/arch/arm/boot/dts/overlays/Makefile\n@@ -40,6 +40,7 @@ dtbo-$(CONFIG_ARCH_BCM2835) += \\\n \tdraws.dtbo \\\n \tdwc-otg.dtbo \\\n \tdwc2.dtbo \\\n+\tedt-ft5406.dtbo \\\n \tenc28j60.dtbo \\\n \tenc28j60-spi2.dtbo \\\n \texc3000.dtbo \\\n--- a/arch/arm/boot/dts/overlays/README\n+++ b/arch/arm/boot/dts/overlays/README\n@@ -733,6 +733,20 @@ Params: dr_mode                 Dual rol\n [ The ds1307-rtc overlay has been deleted. See i2c-rtc. ]\n \n \n+Name:   edt-ft5406\n+Info:   Overlay for the EDT FT5406 touchscreen on the CSI/DSI I2C interface.\n+        This works with the Raspberry Pi 7\" touchscreen when not being polled\n+        by the firmware.\n+        You MUST use either \"disable_touchscreen=1\" or \"ignore_lcd=1\" in\n+        config.txt to stop the firmware polling the touchscreen.\n+Load:   dtoverlay=edt-ft5406,<param>=<val>\n+Params: sizex                   Touchscreen size x (default 800)\n+        sizey                   Touchscreen size y (default 480)\n+        invx                    Touchscreen inverted x axis\n+        invy                    Touchscreen inverted y axis\n+        swapxy                  Touchscreen swapped x y axis\n+\n+\n Name:   enc28j60\n Info:   Overlay for the Microchip ENC28J60 Ethernet Controller on SPI0\n Load:   dtoverlay=enc28j60,<param>=<val>\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/edt-ft5406-overlay.dts\n@@ -0,0 +1,42 @@\n+/*\n+ * Device Tree overlay for RaspberryPi 7\" Touchscreen panel\n+ *\n+ */\n+\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&i2c_csi_dsi>;\n+\t\t__overlay__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\t\t\tft5406: ts@38 {\n+\t\t\t\tcompatible = \"edt,edt-ft5406\";\n+\t\t\t\treg = <0x38>;\n+\n+\t\t\t\ttouchscreen-size-x = < 800 >;\n+\t\t\t\ttouchscreen-size-y = < 480 >;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&i2c0if>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\tsizex = <&ft5406>,\"touchscreen-size-x:0\";\n+\t\tsizey = <&ft5406>,\"touchscreen-size-y:0\";\n+\t\tinvx = <&ft5406>,\"touchscreen-inverted-x?\";\n+\t\tinvy = <&ft5406>,\"touchscreen-inverted-y?\";\n+\t\tswapxy = <&ft5406>,\"touchscreen-swapped-x-y?\";\n+\t};\n+};\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0382-drm-panel-raspberrypi-touchscreen-Use-independent-I2.patch",
    "content": "From 3ad3a680ece56c7134d9500a0413b4f9259c07d8 Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Thu, 23 Apr 2020 10:17:18 +0100\nSubject: [PATCH] drm/panel/raspberrypi-touchscreen: Use independent\n I2C actions with delay.\n\nWe now have the hardware I2C controller pinmuxed to the drive the\ndisplay I2C, but this controller does not support clock stretching.\nThe Atmel micro-controller in the panel requires clock stretching\nto allow it to prepare any data to be read.\n\nSplit the rpi_touchscreen_i2c_read into two independent transactions with\na delay between them for the Atmel to prepare the data.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n .../drm/panel/panel-raspberrypi-touchscreen.c | 30 ++++++++++++++++++-\n 1 file changed, 29 insertions(+), 1 deletion(-)\n\n--- a/drivers/gpu/drm/panel/panel-raspberrypi-touchscreen.c\n+++ b/drivers/gpu/drm/panel/panel-raspberrypi-touchscreen.c\n@@ -219,7 +219,35 @@ static struct rpi_touchscreen *panel_to_\n \n static int rpi_touchscreen_i2c_read(struct rpi_touchscreen *ts, u8 reg)\n {\n-\treturn i2c_smbus_read_byte_data(ts->i2c, reg);\n+\tstruct i2c_client *client = ts->i2c;\n+\tstruct i2c_msg msgs[1];\n+\tu8 addr_buf[1] = { reg };\n+\tu8 data_buf[1] = { 0, };\n+\tint ret;\n+\n+\t/* Write register address */\n+\tmsgs[0].addr = client->addr;\n+\tmsgs[0].flags = 0;\n+\tmsgs[0].len = ARRAY_SIZE(addr_buf);\n+\tmsgs[0].buf = addr_buf;\n+\n+\tret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));\n+\tif (ret != ARRAY_SIZE(msgs))\n+\t\treturn -EIO;\n+\n+\tusleep_range(100, 300);\n+\n+\t/* Read data from register */\n+\tmsgs[0].addr = client->addr;\n+\tmsgs[0].flags = I2C_M_RD;\n+\tmsgs[0].len = 1;\n+\tmsgs[0].buf = data_buf;\n+\n+\tret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));\n+\tif (ret != ARRAY_SIZE(msgs))\n+\t\treturn -EIO;\n+\n+\treturn data_buf[0];\n }\n \n static void rpi_touchscreen_i2c_write(struct rpi_touchscreen *ts,\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0383-drm-panel-raspberrypi-ts-Insert-delay-before-polling.patch",
    "content": "From 01cb60004018afba6e2b60149e4adbbf9e87d90b Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Tue, 10 Nov 2020 11:21:56 +0000\nSubject: [PATCH] drm/panel/raspberrypi-ts: Insert delay before polling\n for startup state\n\nIn switching to the hardware I2C controller there is an issue\nwhere we seem to not get back the correct state from the Pi\ntouchscreen.\nInsert a delay before polling to avoid this condition.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n drivers/gpu/drm/panel/panel-raspberrypi-touchscreen.c | 1 +\n 1 file changed, 1 insertion(+)\n\n--- a/drivers/gpu/drm/panel/panel-raspberrypi-touchscreen.c\n+++ b/drivers/gpu/drm/panel/panel-raspberrypi-touchscreen.c\n@@ -299,6 +299,7 @@ static int rpi_touchscreen_prepare(struc\n \tint i;\n \n \trpi_touchscreen_i2c_write(ts, REG_POWERON, 1);\n+\tusleep_range(20000, 25000);\n \t/* Wait for nPWRDWN to go low to indicate poweron is done. */\n \tfor (i = 0; i < 100; i++) {\n \t\tif (rpi_touchscreen_i2c_read(ts, REG_PORTB) & 1)\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0384-Add-devicetree-support-for-RaspberryPi-7-panel-over-.patch",
    "content": "From 818fff9eed1c36f404f0556a0b239b43799a094b Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Tue, 10 Nov 2020 17:49:35 +0000\nSubject: [PATCH] Add devicetree support for RaspberryPi 7\" panel over\n DSI I2C\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n arch/arm/boot/dts/overlays/Makefile           |  1 +\n arch/arm/boot/dts/overlays/README             |  8 +++\n .../overlays/vc4-kms-dsi-7inch-overlay.dts    | 56 +++++++++++++++++++\n 3 files changed, 65 insertions(+)\n create mode 100644 arch/arm/boot/dts/overlays/vc4-kms-dsi-7inch-overlay.dts\n\n--- a/arch/arm/boot/dts/overlays/Makefile\n+++ b/arch/arm/boot/dts/overlays/Makefile\n@@ -201,6 +201,7 @@ dtbo-$(CONFIG_ARCH_BCM2835) += \\\n \tupstream.dtbo \\\n \tupstream-pi4.dtbo \\\n \tvc4-fkms-v3d.dtbo \\\n+\tvc4-kms-dsi-7inch.dtbo \\\n \tvc4-kms-kippah-7inch.dtbo \\\n \tvc4-kms-v3d.dtbo \\\n \tvc4-kms-v3d-pi4.dtbo \\\n--- a/arch/arm/boot/dts/overlays/README\n+++ b/arch/arm/boot/dts/overlays/README\n@@ -2935,6 +2935,14 @@ Params: cma-512                 CMA is 5\n         cma-default             Use upstream's default value\n \n \n+Name:   vc4-kms-dsi-7inch\n+Info:   Enable the Raspberry Pi DSI 7\" screen.\n+        Use edt-ft5406 for the touchscreen element.\n+        Requires vc4-kms-v3d to be loaded.\n+Load:   dtoverlay=vc4-kms-dsi-7inch\n+Params: <None>\n+\n+\n Name:   vc4-kms-kippah-7inch\n Info:   Enable the Adafruit DPI Kippah with the 7\" Ontat panel attached.\n         Requires vc4-kms-v3d to be loaded.\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/vc4-kms-dsi-7inch-overlay.dts\n@@ -0,0 +1,56 @@\n+/*\n+ * Device Tree overlay for RaspberryPi 7\" Touchscreen panel\n+ *\n+ */\n+\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&dsi1>;\n+\t\t__overlay__ {\n+\t\t\t#address-cells = <1>; size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\t\t\tport {\n+\t\t\t\tdsi_out_port: endpoint {\n+\t\t\t\t\tremote-endpoint = <&panel_dsi_port>;\n+\t\t\t\t};\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&i2c_csi_dsi>;\n+\t\t__overlay__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\t\t\tlcd@45 {\n+\t\t\t\tcompatible = \"raspberrypi,7inch-touchscreen-panel\";\n+\t\t\t\treg = <0x45>;\n+\t\t\t\tport {\n+\t\t\t\t\tpanel_dsi_port: endpoint {\n+\t\t\t\t\t\tremote-endpoint = <&dsi_out_port>;\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&i2c0if>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@3 {\n+\t\ttarget = <&i2c0mux>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+};\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0385-mcp251xfd-add-overlay.patch",
    "content": "From 6a028ad5aed9e68280c9ccf6d4ca5370fcfdb4a2 Mon Sep 17 00:00:00 2001\nFrom: Marc Kleine-Budde <mkl@pengutronix.de>\nDate: Fri, 15 Nov 2019 00:54:07 +0100\nSubject: [PATCH] mcp251xfd: add overlay\n\nSigned-off-by: Marc Kleine-Budde <mkl@pengutronix.de>\n---\n arch/arm/boot/dts/overlays/Makefile           |   1 +\n arch/arm/boot/dts/overlays/README             |  22 ++\n .../boot/dts/overlays/mcp251xfd-overlay.dts   | 226 ++++++++++++++++++\n 3 files changed, 249 insertions(+)\n create mode 100644 arch/arm/boot/dts/overlays/mcp251xfd-overlay.dts\n\n--- a/arch/arm/boot/dts/overlays/Makefile\n+++ b/arch/arm/boot/dts/overlays/Makefile\n@@ -108,6 +108,7 @@ dtbo-$(CONFIG_ARCH_BCM2835) += \\\n \tmcp23s17.dtbo \\\n \tmcp2515-can0.dtbo \\\n \tmcp2515-can1.dtbo \\\n+\tmcp251xfd.dtbo \\\n \tmcp3008.dtbo \\\n \tmcp3202.dtbo \\\n \tmcp342x.dtbo \\\n--- a/arch/arm/boot/dts/overlays/README\n+++ b/arch/arm/boot/dts/overlays/README\n@@ -1779,6 +1779,28 @@ Params: oscillator              Clock fr\n         interrupt               GPIO for interrupt signal\n \n \n+Name:   mcp251xfd\n+Info:   Configures the MCP251XFD CAN controller family\n+        For devices on spi1 or spi2, the interfaces should be enabled\n+        with one of the spi1-1/2/3cs and/or spi2-1/2/3cs overlays.\n+Load:   dtoverlay=mcp251xfd,<param>=<val>\n+Params: spi<n>-<m>              Configure device at spi<n>, cs<m>\n+                                (boolean, required)\n+\n+        oscillator              Clock frequency for the CAN controller (Hz)\n+\n+        speed                   Maximum SPI frequence (Hz)\n+\n+        interrupt               GPIO for interrupt signal\n+\n+        rx_interrupt            GPIO for RX interrupt signal (nINT1) (optional)\n+\n+        xceiver_enable          GPIO for CAN transceiver enable (optional)\n+\n+        xceiver_active_high     specifiy if CAN transceiver enable pin is\n+                                active high (optional, default: active low)\n+\n+\n Name:   mcp3008\n Info:   Configures MCP3008 A/D converters\n         For devices on spi1 or spi2, the interfaces should be enabled\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/mcp251xfd-overlay.dts\n@@ -0,0 +1,226 @@\n+// SPDX-License-Identifier: (GPL-2.0 OR MIT)\n+\n+/dts-v1/;\n+/plugin/;\n+\n+#include <dt-bindings/gpio/gpio.h>\n+#include <dt-bindings/interrupt-controller/irq.h>\n+#include <dt-bindings/pinctrl/bcm2835.h>\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&spidev0>;\n+\t\t__dormant__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&spidev1>;\n+\t\t__dormant__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget-path = \"spi1/spidev@0\";\n+\t\t__dormant__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\tfragment@3 {\n+\t\ttarget-path = \"spi1/spidev@1\";\n+\t\t__dormant__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\tfragment@4 {\n+\t\ttarget-path = \"spi1/spidev@2\";\n+\t\t__dormant__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\tfragment@5 {\n+\t\ttarget-path = \"spi2/spidev@0\";\n+\t\t__dormant__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\tfragment@6 {\n+\t\ttarget-path = \"spi2/spidev@1\";\n+\t\t__dormant__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\tfragment@7 {\n+\t\ttarget-path = \"spi2/spidev@2\";\n+\t\t__dormant__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\tfragment@8 {\n+\t\ttarget = <&gpio>;\n+\t\t__overlay__ {\n+\t\t\tmcp251xfd_pins: mcp251xfd_pins {\n+\t\t\t\tbrcm,pins = <25>;\n+\t\t\t\tbrcm,function = <BCM2835_FSEL_GPIO_IN>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@9 {\n+\t\ttarget-path = \"/clocks\";\n+\t\t__overlay__ {\n+\t\t\tclk_mcp251xfd_osc: mcp251xfd-osc {\n+\t\t\t\t#clock-cells = <0>;\n+\t\t\t\tcompatible = \"fixed-clock\";\n+\t\t\t\tclock-frequency = <40000000>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tmcp251xfd_frag: fragment@10 {\n+\t\ttarget = <&spi0>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tmcp251xfd: mcp251xfd@0 {\n+\t\t\t\tcompatible = \"microchip,mcp251xfd\";\n+\t\t\t\treg = <0>;\n+\t\t\t\tpinctrl-names = \"default\";\n+\t\t\t\tpinctrl-0 = <&mcp251xfd_pins>;\n+\t\t\t\tspi-max-frequency = <20000000>;\n+\t\t\t\tinterrupt-parent = <&gpio>;\n+\t\t\t\tinterrupts = <25 IRQ_TYPE_LEVEL_LOW>;\n+\t\t\t\tclocks = <&clk_mcp251xfd_osc>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@11 {\n+\t\ttarget = <&mcp251xfd>;\n+\t\tmcp251xfd_rx_int_gpios: __dormant__ {\n+\t\t\tmicrochip,rx-int-gpios = <&gpio 255 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\t};\n+\n+\tfragment@12 {\n+\t\ttarget = <&gpio>;\n+\t\t__dormant__ {\n+\t\t\tmcp251xfd_xceiver_pins: mcp251xfd_xceiver_pins {\n+\t\t\t\tbrcm,pins = <255>;\n+\t\t\t\tbrcm,function = <BCM2835_FSEL_GPIO_OUT>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@13 {\n+\t\ttarget-path = \"/\";\n+\t\t__dormant__ {\n+\t\t\treg_mcp251xfd_xceiver: reg_mcp251xfd_xceiver {\n+\t\t\t\tcompatible = \"regulator-fixed\";\n+\t\t\t\tregulator-name = \"mcp251xfd_xceiver\";\n+\t\t\t\tregulator-min-microvolt = <3300000>;\n+\t\t\t\tregulator-max-microvolt = <3300000>;\n+\t\t\t\tgpio = <&gpio 4 GPIO_ACTIVE_HIGH>;\n+\t\t\t\tpinctrl-names = \"default\";\n+\t\t\t\tpinctrl-0 = <&mcp251xfd_xceiver_pins>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@14 {\n+\t\ttarget = <&mcp251xfd>;\n+\t\t__dormant__ {\n+\t\t\txceiver-supply = <&reg_mcp251xfd_xceiver>;\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\tspi0-0 = <0>, \"+0\",\n+\t\t\t<&mcp251xfd_frag>, \"target:0=\", <&spi0>,\n+\t\t\t<&mcp251xfd>, \"reg:0=0\",\n+\t\t\t<&mcp251xfd_pins>, \"name=mcp251xfd_spi0_0_pins\",\n+\t\t\t<&clk_mcp251xfd_osc>, \"name=mcp251xfd-spi0-0-osc\",\n+\t\t\t<&mcp251xfd_xceiver_pins>, \"name=mcp251xfd_spi0_0_xceiver_pins\",\n+\t\t\t<&reg_mcp251xfd_xceiver>, \"name=reg-mcp251xfd-spi0-0-xceiver\",\n+\t\t\t<&reg_mcp251xfd_xceiver>, \"regulator-name=mcp251xfd-spi0-0-xceiver\";\n+\t\tspi0-1 = <0>, \"+1\",\n+\t\t\t<&mcp251xfd_frag>, \"target:0=\", <&spi0>,\n+\t\t\t<&mcp251xfd>, \"reg:0=1\",\n+\t\t\t<&mcp251xfd_pins>, \"name=mcp251xfd_spi0_1_pins\",\n+\t\t\t<&clk_mcp251xfd_osc>, \"name=mcp251xfd-spi0-1-osc\",\n+\t\t\t<&mcp251xfd_xceiver_pins>, \"name=mcp251xfd_spi0_1_xceiver_pins\",\n+\t\t\t<&reg_mcp251xfd_xceiver>, \"name=reg-mcp251xfd-spi0-1-xceiver\",\n+\t\t\t<&reg_mcp251xfd_xceiver>, \"regulator-name=mcp251xfd-spi0-1-xceiver\";\n+\t\tspi1-0 = <0>, \"+2\",\n+\t\t\t<&mcp251xfd_frag>, \"target:0=\", <&spi1>,\n+\t\t\t<&mcp251xfd>, \"reg:0=0\",\n+\t\t\t<&mcp251xfd_pins>, \"name=mcp251xfd_spi1_0_pins\",\n+\t\t\t<&clk_mcp251xfd_osc>, \"name=mcp251xfd-spi1-0-osc\",\n+\t\t\t<&mcp251xfd_xceiver_pins>, \"name=mcp251xfd_spi1_0_xceiver_pins\",\n+\t\t\t<&reg_mcp251xfd_xceiver>, \"name=reg-mcp251xfd-spi1-0-xceiver\",\n+\t\t\t<&reg_mcp251xfd_xceiver>, \"regulator-name=mcp251xfd-spi1-0-xceiver\";\n+\t\tspi1-1 = <0>, \"+3\",\n+\t\t\t<&mcp251xfd_frag>, \"target:0=\", <&spi1>,\n+\t\t\t<&mcp251xfd>, \"reg:0=1\",\n+\t\t\t<&mcp251xfd_pins>, \"name=mcp251xfd_spi1_1_pins\",\n+\t\t\t<&clk_mcp251xfd_osc>, \"name=mcp251xfd-spi1-1-osc\",\n+\t\t\t<&mcp251xfd_xceiver_pins>, \"name=mcp251xfd_spi1_1_xceiver_pins\",\n+\t\t\t<&reg_mcp251xfd_xceiver>, \"name=reg-mcp251xfd-spi1-1-xceiver\",\n+\t\t\t<&reg_mcp251xfd_xceiver>, \"regulator-name=mcp251xfd-spi1-1-xceiver\";\n+\t\tspi1-2 = <0>, \"+4\",\n+\t\t\t<&mcp251xfd_frag>, \"target:0=\", <&spi1>,\n+\t\t\t<&mcp251xfd>, \"reg:0=2\",\n+\t\t\t<&mcp251xfd_pins>, \"name=mcp251xfd_spi1_2_pins\",\n+\t\t\t<&clk_mcp251xfd_osc>, \"name=mcp251xfd-spi1-2-osc\",\n+\t\t\t<&mcp251xfd_xceiver_pins>, \"name=mcp251xfd_spi1_2_xceiver_pins\",\n+\t\t\t<&reg_mcp251xfd_xceiver>, \"name=reg-mcp251xfd-spi1-2-xceiver\",\n+\t\t\t<&reg_mcp251xfd_xceiver>, \"regulator-name=mcp251xfd-spi1-2-xceiver\";\n+\t\tspi2-0 = <0>, \"+5\",\n+\t\t\t<&mcp251xfd_frag>, \"target:0=\", <&spi2>,\n+\t\t\t<&mcp251xfd>, \"reg:0=0\",\n+\t\t\t<&mcp251xfd_pins>, \"name=mcp251xfd_spi2_0_pins\",\n+\t\t\t<&clk_mcp251xfd_osc>, \"name=mcp251xfd-spi2-0-osc\",\n+\t\t\t<&mcp251xfd_xceiver_pins>, \"name=mcp251xfd_spi2_0_xceiver_pins\",\n+\t\t\t<&reg_mcp251xfd_xceiver>, \"name=reg-mcp251xfd-spi2-0-xceiver\",\n+\t\t\t<&reg_mcp251xfd_xceiver>, \"regulator-name=mcp251xfd-spi2-0-xceiver\";\n+\t\tspi2-1 = <0>, \"+6\",\n+\t\t\t<&mcp251xfd_frag>, \"target:0=\", <&spi2>,\n+\t\t\t<&mcp251xfd>, \"reg:0=1\",\n+\t\t\t<&mcp251xfd_pins>, \"name=mcp251xfd_spi2_1_pins\",\n+\t\t\t<&clk_mcp251xfd_osc>, \"name=mcp251xfd-spi2-1-osc\",\n+\t\t\t<&mcp251xfd_xceiver_pins>, \"name=mcp251xfd_spi2_1_xceiver_pins\",\n+\t\t\t<&reg_mcp251xfd_xceiver>, \"name=reg-mcp251xfd-spi2-1-xceiver\",\n+\t\t\t<&reg_mcp251xfd_xceiver>, \"regulator-name=mcp251xfd-spi2-1-xceiver\";\n+\t\tspi2-2 = <0>, \"+7\",\n+\t\t\t<&mcp251xfd_frag>, \"target:0=\", <&spi2>,\n+\t\t\t<&mcp251xfd>, \"reg:0=2\",\n+\t\t\t<&mcp251xfd_pins>, \"name=mcp251xfd_spi2_2_pins\",\n+\t\t\t<&clk_mcp251xfd_osc>, \"name=mcp251xfd-spi2-2-osc\",\n+\t\t\t<&mcp251xfd_xceiver_pins>, \"name=mcp251xfd_spi2_2_xceiver_pins\",\n+\t\t\t<&reg_mcp251xfd_xceiver>, \"name=reg-mcp251xfd-spi2-2-xceiver\",\n+\t\t\t<&reg_mcp251xfd_xceiver>, \"regulator-name=mcp251xfd-spi2-2-xceiver\";\n+\t\toscillator = <&clk_mcp251xfd_osc>, \"clock-frequency:0\";\n+\t\tspeed = <&mcp251xfd>, \"spi-max-frequency:0\";\n+\t\tinterrupt = <&mcp251xfd_pins>, \"brcm,pins:0\",\n+\t\t\t<&mcp251xfd>, \"interrupts:0\";\n+\t\trx_interrupt = <0>, \"+11\",\n+\t\t\t<&mcp251xfd_pins>, \"brcm,pins:4\",\n+\t\t\t<&mcp251xfd_rx_int_gpios>, \"microchip,rx-int-gpios:4\";\n+\t\txceiver_enable = <0>, \"+12+13+14\",\n+\t\t\t<&mcp251xfd_xceiver_pins>, \"brcm,pins:0\",\n+\t\t\t<&reg_mcp251xfd_xceiver>, \"gpio:4\";\n+\t\txceiver_active_high = <&reg_mcp251xfd_xceiver>, \"enable-active-high?\";\n+\t};\n+};\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0386-media-ov9281-Add-1280x720-and-640x480-modes.patch",
    "content": "From dd40e2ef1f8e6cded376b928451740a828e5e6ef Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Sun, 22 Nov 2020 11:01:08 +0000\nSubject: [PATCH] media: ov9281: Add 1280x720 and 640x480 modes\n\nBreaks out common register set and adds the different registers\nfor 1280x720 (cropped) and 640x480 (skipped) modes\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n drivers/media/i2c/ov9281.c | 146 ++++++++++++++++++++++++++++++++-----\n 1 file changed, 126 insertions(+), 20 deletions(-)\n\n--- a/drivers/media/i2c/ov9281.c\n+++ b/drivers/media/i2c/ov9281.c\n@@ -139,7 +139,7 @@ struct ov9281 {\n  * max_framerate 120fps for 10 bit, 144fps for 8 bit.\n  * mipi_datarate per lane 800Mbps\n  */\n-static const struct regval ov9281_1280x800_regs[] = {\n+static const struct regval ov9281_common_regs[] = {\n \t{0x0103, 0x01},\n \t{0x0302, 0x32},\n \t{0x030e, 0x02},\n@@ -177,13 +177,35 @@ static const struct regval ov9281_1280x8\n \t{0x372d, 0x22},\n \t{0x3731, 0x80},\n \t{0x3732, 0x30},\n-\t{0x3778, 0x00},\n \t{0x377d, 0x22},\n \t{0x3788, 0x02},\n \t{0x3789, 0xa4},\n \t{0x378a, 0x00},\n \t{0x378b, 0x4a},\n \t{0x3799, 0x20},\n+\t{0x3881, 0x42},\n+\t{0x38b1, 0x00},\n+\t{0x3920, 0xff},\n+\t{0x4010, 0x40},\n+\t{0x4043, 0x40},\n+\t{0x4307, 0x30},\n+\t{0x4317, 0x00},\n+\t{0x4501, 0x00},\n+\t{0x450a, 0x08},\n+\t{0x4601, 0x04},\n+\t{0x470f, 0x00},\n+\t{0x4f07, 0x00},\n+\t{0x4800, 0x00},\n+\t{0x5000, 0x9f},\n+\t{0x5001, 0x00},\n+\t{0x5e00, 0x00},\n+\t{0x5d00, 0x07},\n+\t{0x5d01, 0x00},\n+\t{REG_NULL, 0x00},\n+};\n+\n+static const struct regval ov9281_1280x800_regs[] = {\n+\t{0x3778, 0x10},\n \t{0x3800, 0x00},\n \t{0x3801, 0x00},\n \t{0x3802, 0x00},\n@@ -208,31 +230,83 @@ static const struct regval ov9281_1280x8\n \t{0x3815, 0x11},\n \t{0x3820, 0x40},\n \t{0x3821, 0x00},\n-\t{0x3881, 0x42},\n-\t{0x38b1, 0x00},\n-\t{0x3920, 0xff},\n \t{0x4003, 0x40},\n \t{0x4008, 0x04},\n \t{0x4009, 0x0b},\n \t{0x400c, 0x00},\n \t{0x400d, 0x07},\n-\t{0x4010, 0x40},\n-\t{0x4043, 0x40},\n-\t{0x4307, 0x30},\n-\t{0x4317, 0x00},\n-\t{0x4501, 0x00},\n \t{0x4507, 0x00},\n \t{0x4509, 0x00},\n-\t{0x450a, 0x08},\n-\t{0x4601, 0x04},\n-\t{0x470f, 0x00},\n-\t{0x4f07, 0x00},\n-\t{0x4800, 0x00},\n-\t{0x5000, 0x9f},\n-\t{0x5001, 0x00},\n-\t{0x5e00, 0x00},\n-\t{0x5d00, 0x07},\n-\t{0x5d01, 0x00},\n+\t{REG_NULL, 0x00},\n+};\n+\n+static const struct regval ov9281_1280x720_regs[] = {\n+\t{0x3778, 0x10},\n+\t{0x3800, 0x00},\n+\t{0x3801, 0x00},\n+\t{0x3802, 0x00},\n+\t{0x3803, 0x28},\n+\t{0x3804, 0x05},\n+\t{0x3805, 0x0f},\n+\t{0x3806, 0x03},\n+\t{0x3807, 0x07},\n+\t{0x3808, 0x05},\n+\t{0x3809, 0x00},\n+\t{0x380a, 0x02},\n+\t{0x380b, 0xd0},\n+\t{0x380c, 0x02},\n+\t{0x380d, 0xd8},\n+\t{0x380e, 0x03},\n+\t{0x380f, 0x8e},\n+\t{0x3810, 0x00},\n+\t{0x3811, 0x08},\n+\t{0x3812, 0x00},\n+\t{0x3813, 0x08},\n+\t{0x3814, 0x11},\n+\t{0x3815, 0x11},\n+\t{0x3820, 0x40},\n+\t{0x3821, 0x00},\n+\t{0x4003, 0x40},\n+\t{0x4008, 0x04},\n+\t{0x4009, 0x0b},\n+\t{0x400c, 0x00},\n+\t{0x400d, 0x07},\n+\t{0x4507, 0x00},\n+\t{0x4509, 0x00},\n+\t{REG_NULL, 0x00},\n+};\n+\n+static const struct regval ov9281_640x400_regs[] = {\n+\t{0x3800, 0x00},\n+\t{0x3801, 0x00},\n+\t{0x3802, 0x00},\n+\t{0x3803, 0x00},\n+\t{0x3804, 0x05},\n+\t{0x3805, 0x0f},\n+\t{0x3806, 0x03},\n+\t{0x3807, 0x2f},\n+\t{0x3808, 0x02},\n+\t{0x3809, 0x80},\n+\t{0x380a, 0x01},\n+\t{0x380b, 0x90},\n+\t{0x380c, 0x02},\n+\t{0x380d, 0xd8},\n+\t{0x380e, 0x02},\n+\t{0x380f, 0x08},\n+\t{0x3810, 0x00},\n+\t{0x3811, 0x04},\n+\t{0x3812, 0x00},\n+\t{0x3813, 0x04},\n+\t{0x3814, 0x31},\n+\t{0x3815, 0x22},\n+\t{0x3820, 0x60},\n+\t{0x3821, 0x01},\n+\t{0x4008, 0x02},\n+\t{0x4009, 0x05},\n+\t{0x400c, 0x00},\n+\t{0x400d, 0x03},\n+\t{0x4507, 0x03},\n+\t{0x4509, 0x80},\n \t{REG_NULL, 0x00},\n };\n \n@@ -263,6 +337,34 @@ static const struct ov9281_mode supporte\n \t\t},\n \t\t.reg_list = ov9281_1280x800_regs,\n \t},\n+\t{\n+\t\t.width = 1280,\n+\t\t.height = 720,\n+\t\t.exp_def = 0x0320,\n+\t\t.hts_def = 0x05b0,\n+\t\t.vts_def = 761,\n+\t\t.crop = {\n+\t\t\t.left = 0,\n+\t\t\t.top = 40,\n+\t\t\t.width = 1280,\n+\t\t\t.height = 720\n+\t\t},\n+\t\t.reg_list = ov9281_1280x720_regs,\n+\t},\n+\t{\n+\t\t.width = 640,\n+\t\t.height = 400,\n+\t\t.exp_def = 0x0320,\n+\t\t.hts_def = 0x05b0,\n+\t\t.vts_def = 421,\n+\t\t.crop = {\n+\t\t\t.left = 0,\n+\t\t\t.top = 0,\n+\t\t\t.width = 1280,\n+\t\t\t.height = 800\n+\t\t},\n+\t\t.reg_list = ov9281_640x400_regs,\n+\t},\n };\n \n static const s64 link_freq_menu_items[] = {\n@@ -567,6 +669,10 @@ static int __ov9281_start_stream(struct\n {\n \tint ret;\n \n+\tret = ov9281_write_array(ov9281->client, ov9281_common_regs);\n+\tif (ret)\n+\t\treturn ret;\n+\n \tret = ov9281_write_array(ov9281->client, ov9281->cur_mode->reg_list);\n \tif (ret)\n \t\treturn ret;\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0387-dt-bindings-Add-compatible-for-BCM2711-DSI1.patch",
    "content": "From 3acfacedd3d8f627d40bfaaf1a8312fe69823572 Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Thu, 12 Nov 2020 17:01:52 +0000\nSubject: [PATCH] dt-bindings: Add compatible for BCM2711 DSI1\n\nDSI1 on BCM2711 doesn't require the DMA workaround that is used\non BCM2835/6/7, therefore it needs a new compatible string.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n Documentation/devicetree/bindings/display/brcm,bcm2835-dsi0.yaml | 1 +\n 1 file changed, 1 insertion(+)\n\n--- a/Documentation/devicetree/bindings/display/brcm,bcm2835-dsi0.yaml\n+++ b/Documentation/devicetree/bindings/display/brcm,bcm2835-dsi0.yaml\n@@ -20,6 +20,7 @@ properties:\n     enum:\n       - brcm,bcm2835-dsi0\n       - brcm,bcm2835-dsi1\n+      - brcm,bcm2711-dsi1\n \n   reg:\n     maxItems: 1\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0388-dt-Use-compatible-string-for-BCM2711-DSI1.patch",
    "content": "From 3fa54d7688eaea066f1478ed6bc6051ee3b11f2b Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Thu, 12 Nov 2020 18:42:30 +0000\nSubject: [PATCH] dt: Use compatible string for BCM2711 DSI1\n\nUpdates the compatible string for DSI1 on BCM2711 to\ndifferentiate it from BCM2835.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n arch/arm/boot/dts/bcm2711.dtsi | 1 +\n 1 file changed, 1 insertion(+)\n\n--- a/arch/arm/boot/dts/bcm2711.dtsi\n+++ b/arch/arm/boot/dts/bcm2711.dtsi\n@@ -611,6 +611,7 @@\n \n &dsi1 {\n \tinterrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;\n+\tcompatible = \"brcm,bcm2711-dsi1\";\n };\n \n &gpio {\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0389-drm-vc4-Correct-DSI-register-definition.patch",
    "content": "From 264515dcb2a318072530a2171c084dc207006399 Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Mon, 30 Nov 2020 16:16:03 +0000\nSubject: [PATCH] drm/vc4: Correct DSI register definition\n\nThe DSI1_PHY_AFEC0_PD_DLANE1 and DSI1_PHY_AFEC0_PD_DLANE3 register\ndefinitions were swapped, so trying to use more than a single data\nlane failed as lane 1 would get powered down.\n(In theory a 4 lane device would work as all lanes would remain\npowered).\n\nCorrect the definitions.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n drivers/gpu/drm/vc4/vc4_dsi.c | 4 ++--\n 1 file changed, 2 insertions(+), 2 deletions(-)\n\n--- a/drivers/gpu/drm/vc4/vc4_dsi.c\n+++ b/drivers/gpu/drm/vc4/vc4_dsi.c\n@@ -306,11 +306,11 @@\n # define DSI0_PHY_AFEC0_RESET\t\t\tBIT(11)\n # define DSI1_PHY_AFEC0_PD_BG\t\t\tBIT(11)\n # define DSI0_PHY_AFEC0_PD\t\t\tBIT(10)\n-# define DSI1_PHY_AFEC0_PD_DLANE3\t\tBIT(10)\n+# define DSI1_PHY_AFEC0_PD_DLANE1\t\tBIT(10)\n # define DSI0_PHY_AFEC0_PD_BG\t\t\tBIT(9)\n # define DSI1_PHY_AFEC0_PD_DLANE2\t\tBIT(9)\n # define DSI0_PHY_AFEC0_PD_DLANE1\t\tBIT(8)\n-# define DSI1_PHY_AFEC0_PD_DLANE1\t\tBIT(8)\n+# define DSI1_PHY_AFEC0_PD_DLANE3\t\tBIT(8)\n # define DSI_PHY_AFEC0_PTATADJ_MASK\t\tVC4_MASK(7, 4)\n # define DSI_PHY_AFEC0_PTATADJ_SHIFT\t\t4\n # define DSI_PHY_AFEC0_CTATADJ_MASK\t\tVC4_MASK(3, 0)\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0390-Allo-boss2-driver.patch",
    "content": "From 5eba3bb8b48060a5ddf143c1aa69840a90dd9162 Mon Sep 17 00:00:00 2001\nFrom: Sudeep <sudeepkumar@cem-solutions.net>\nDate: Fri, 23 Oct 2020 15:47:17 +0530\nSubject: [PATCH] Allo boss2 driver\n\nSigned-off-by: Sudeep <sudeepkumar@cem-solutions.net>\n---\n sound/soc/bcm/Kconfig          |    9 +\n sound/soc/bcm/Makefile         |    2 +\n sound/soc/bcm/allo-boss2-dac.c | 1133 ++++++++++++++++++++++++++++++++\n 3 files changed, 1144 insertions(+)\n create mode 100644 sound/soc/bcm/allo-boss2-dac.c\n\n--- a/sound/soc/bcm/Kconfig\n+++ b/sound/soc/bcm/Kconfig\n@@ -267,6 +267,15 @@ config SND_BCM2708_SOC_ALLO_BOSS_DAC\n \thelp\n \t  Say Y or M if you want to add support for Allo Boss DAC.\n \n+config SND_BCM2708_SOC_ALLO_BOSS2_DAC\n+\ttristate \"Support for Allo Boss2 DAC\"\n+\tdepends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S\n+\tdepends on I2C\n+\tselect REGMAP_I2C\n+\tselect SND_AUDIO_GRAPH_CARD\n+\thelp\n+\t  Say Y or M if you want to add support for Allo Boss2 DAC.\n+\n config SND_BCM2708_SOC_ALLO_DIGIONE\n \ttristate \"Support for Allo DigiOne\"\n \tdepends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S\n--- a/sound/soc/bcm/Makefile\n+++ b/sound/soc/bcm/Makefile\n@@ -38,6 +38,7 @@ snd-soc-digidac1-soundcard-objs := digid\n snd-soc-dionaudio-loco-objs := dionaudio_loco.o\n snd-soc-dionaudio-loco-v2-objs := dionaudio_loco-v2.o\n snd-soc-allo-boss-dac-objs := allo-boss-dac.o\n+snd-soc-allo-boss2-dac-objs := allo-boss2-dac.o\n snd-soc-allo-piano-dac-objs := allo-piano-dac.o\n snd-soc-allo-piano-dac-plus-objs := allo-piano-dac-plus.o\n snd-soc-allo-katana-codec-objs := allo-katana-codec.o\n@@ -68,6 +69,7 @@ obj-$(CONFIG_SND_DIGIDAC1_SOUNDCARD) +=\n obj-$(CONFIG_SND_BCM2708_SOC_DIONAUDIO_LOCO) += snd-soc-dionaudio-loco.o\n obj-$(CONFIG_SND_BCM2708_SOC_DIONAUDIO_LOCO_V2) += snd-soc-dionaudio-loco-v2.o\n obj-$(CONFIG_SND_BCM2708_SOC_ALLO_BOSS_DAC) += snd-soc-allo-boss-dac.o\n+obj-$(CONFIG_SND_BCM2708_SOC_ALLO_BOSS2_DAC) += snd-soc-allo-boss2-dac.o\n obj-$(CONFIG_SND_BCM2708_SOC_ALLO_PIANO_DAC) += snd-soc-allo-piano-dac.o\n obj-$(CONFIG_SND_BCM2708_SOC_ALLO_PIANO_DAC_PLUS) += snd-soc-allo-piano-dac-plus.o\n obj-$(CONFIG_SND_BCM2708_SOC_ALLO_KATANA_DAC) += snd-soc-allo-katana-codec.o\n--- /dev/null\n+++ b/sound/soc/bcm/allo-boss2-dac.c\n@@ -0,0 +1,1133 @@\n+/*\n+ * Driver for the ALLO KATANA CODEC\n+ *\n+ * Author: Jaikumar <sudeepkumar@cem-solutions.net>\n+ *\t\tCopyright 2018\n+ *\n+ * This program is free software; you can redistribute it and/or\n+ * modify it under the terms of the GNU General Public License\n+ * version 2 as published by the Free Software Foundation.\n+ *\n+ * This program is distributed in the hope that it will be useful, but\n+ * WITHOUT ANY WARRANTY; without even the implied warranty of\n+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\n+ * General Public License for more details.\n+ */\n+\n+#include <linux/module.h>\n+#include <linux/moduleparam.h>\n+#include <linux/kernel.h>\n+#include <linux/init.h>\n+#include <linux/delay.h>\n+#include <linux/gpio.h>\n+#include <linux/gpio/consumer.h>\n+#include <linux/platform_device.h>\n+#include <linux/pm.h>\n+#include <linux/i2c.h>\n+#include <linux/of_device.h>\n+#include <linux/regmap.h>\n+#include <linux/slab.h>\n+#include <sound/core.h>\n+#include <sound/pcm.h>\n+#include <sound/pcm_params.h>\n+#include <sound/soc.h>\n+#include <sound/soc-dapm.h>\n+#include <sound/initval.h>\n+#include <sound/tlv.h>\n+#include <linux/of_gpio.h>\n+#include <linux/regulator/consumer.h>\n+#include <linux/pm_runtime.h>\n+#include <linux/of_irq.h>\n+#include <linux/completion.h>\n+#include <linux/mutex.h>\n+#include <linux/workqueue.h>\n+#include <sound/jack.h>\n+\n+#include \"../codecs/cs43130.h\"\n+\n+#include <linux/clk.h>\n+#include <linux/gcd.h>\n+#define DEBUG\n+\n+#define CS43130_DSD_EN_MASK             0x10\n+#define CS43130_PDN_DONE_INT_MASK        0x00\n+\n+static struct gpio_desc *snd_allo_clk44gpio;\n+static struct gpio_desc *snd_allo_clk48gpio;\n+\n+struct  cs43130_priv {\n+\tstruct snd_soc_component        *component;\n+\tstruct regmap                   *regmap;\n+\tstruct regulator_bulk_data      supplies[CS43130_NUM_SUPPLIES];\n+\tstruct gpio_desc                *reset_gpio;\n+\tunsigned int                    dev_id; /* codec device ID */\n+\tint                             xtal_ibias;\n+\t/* shared by both DAIs */\n+\tstruct mutex                    clk_mutex;\n+\tint                             clk_req;\n+\tbool                            pll_bypass;\n+\tstruct completion               xtal_rdy;\n+\tstruct completion               pll_rdy;\n+\tunsigned int                    mclk;\n+\tunsigned int                    mclk_int;\n+\tint                             mclk_int_src;\n+\n+\t/* DAI specific */\n+\tstruct cs43130_dai              dais[CS43130_DAI_ID_MAX];\n+\n+\t/* HP load specific */\n+\tbool                            dc_meas;\n+\tbool                            ac_meas;\n+\tbool                            hpload_done;\n+\tstruct completion               hpload_evt;\n+\tunsigned int                    hpload_stat;\n+\tu16                             hpload_dc[2];\n+\tu16                             dc_threshold[CS43130_DC_THRESHOLD];\n+\tu16                             ac_freq[CS43130_AC_FREQ];\n+\tu16                             hpload_ac[CS43130_AC_FREQ][2];\n+\tstruct workqueue_struct         *wq;\n+\tstruct work_struct              work;\n+\tstruct snd_soc_jack             jack;\n+};\n+\n+static const struct reg_default cs43130_reg_defaults[] = {\n+\t{CS43130_SYS_CLK_CTL_1, 0x06},\n+\t{CS43130_SP_SRATE, 0x01},\n+\t{CS43130_SP_BITSIZE, 0x05},\n+\t{CS43130_PAD_INT_CFG, 0x03},\n+\t{CS43130_PWDN_CTL, 0xFE},\n+\t{CS43130_CRYSTAL_SET, 0x04},\n+\t{CS43130_PLL_SET_1, 0x00},\n+\t{CS43130_PLL_SET_2, 0x00},\n+\t{CS43130_PLL_SET_3, 0x00},\n+\t{CS43130_PLL_SET_4, 0x00},\n+\t{CS43130_PLL_SET_5, 0x40},\n+\t{CS43130_PLL_SET_6, 0x10},\n+\t{CS43130_PLL_SET_7, 0x80},\n+\t{CS43130_PLL_SET_8, 0x03},\n+\t{CS43130_PLL_SET_9, 0x02},\n+\t{CS43130_PLL_SET_10, 0x02},\n+\t{CS43130_CLKOUT_CTL, 0x00},\n+\t{CS43130_ASP_NUM_1, 0x01},\n+\t{CS43130_ASP_NUM_2, 0x00},\n+\t{CS43130_ASP_DEN_1, 0x08},\n+\t{CS43130_ASP_DEN_2, 0x00},\n+\t{CS43130_ASP_LRCK_HI_TIME_1, 0x1F},\n+\t{CS43130_ASP_LRCK_HI_TIME_2, 0x00},\n+\t{CS43130_ASP_LRCK_PERIOD_1, 0x3F},\n+\t{CS43130_ASP_LRCK_PERIOD_2, 0x00},\n+\t{CS43130_ASP_CLOCK_CONF, 0x0C},\n+\t{CS43130_ASP_FRAME_CONF, 0x0A},\n+\t{CS43130_XSP_NUM_1, 0x01},\n+\t{CS43130_XSP_NUM_2, 0x00},\n+\t{CS43130_XSP_DEN_1, 0x02},\n+\t{CS43130_XSP_DEN_2, 0x00},\n+\t{CS43130_XSP_LRCK_HI_TIME_1, 0x1F},\n+\t{CS43130_XSP_LRCK_HI_TIME_2, 0x00},\n+\t{CS43130_XSP_LRCK_PERIOD_1, 0x3F},\n+\t{CS43130_XSP_LRCK_PERIOD_2, 0x00},\n+\t{CS43130_XSP_CLOCK_CONF, 0x0C},\n+\t{CS43130_XSP_FRAME_CONF, 0x0A},\n+\t{CS43130_ASP_CH_1_LOC, 0x00},\n+\t{CS43130_ASP_CH_2_LOC, 0x00},\n+\t{CS43130_ASP_CH_1_SZ_EN, 0x06},\n+\t{CS43130_ASP_CH_2_SZ_EN, 0x0E},\n+\t{CS43130_XSP_CH_1_LOC, 0x00},\n+\t{CS43130_XSP_CH_2_LOC, 0x00},\n+\t{CS43130_XSP_CH_1_SZ_EN, 0x06},\n+\t{CS43130_XSP_CH_2_SZ_EN, 0x0E},\n+\t{CS43130_DSD_VOL_B, 0x78},\n+\t{CS43130_DSD_VOL_A, 0x78},\n+\t{CS43130_DSD_PATH_CTL_1, 0xA8},\n+\t{CS43130_DSD_INT_CFG, 0x00},\n+\t{CS43130_DSD_PATH_CTL_2, 0x02},\n+\t{CS43130_DSD_PCM_MIX_CTL, 0x00},\n+\t{CS43130_DSD_PATH_CTL_3, 0x40},\n+\t{CS43130_HP_OUT_CTL_1, 0x30},\n+\t{CS43130_PCM_FILT_OPT, 0x02},\n+\t{CS43130_PCM_VOL_B, 0x78},\n+\t{CS43130_PCM_VOL_A, 0x78},\n+\t{CS43130_PCM_PATH_CTL_1, 0xA8},\n+\t{CS43130_PCM_PATH_CTL_2, 0x00},\n+\t{CS43130_CLASS_H_CTL, 0x1E},\n+\t{CS43130_HP_DETECT, 0x04},\n+\t{CS43130_HP_LOAD_1, 0x00},\n+\t{CS43130_HP_MEAS_LOAD_1, 0x00},\n+\t{CS43130_HP_MEAS_LOAD_2, 0x00},\n+\t{CS43130_INT_MASK_1, 0xFF},\n+\t{CS43130_INT_MASK_2, 0xFF},\n+\t{CS43130_INT_MASK_3, 0xFF},\n+\t{CS43130_INT_MASK_4, 0xFF},\n+\t{CS43130_INT_MASK_5, 0xFF},\n+};\n+static bool cs43130_volatile_register(struct device *dev, unsigned int reg)\n+{\n+\tswitch (reg) {\n+\tcase CS43130_INT_STATUS_1 ... CS43130_INT_STATUS_5:\n+\tcase CS43130_HP_DC_STAT_1 ... CS43130_HP_DC_STAT_2:\n+\tcase CS43130_HP_AC_STAT_1 ... CS43130_HP_AC_STAT_2:\n+\t\treturn true;\n+\tdefault:\n+\t\treturn false;\n+\t}\n+}\n+\n+static const char * const pcm_spd_texts[] = {\n+\t\"Fast\",\n+\t\"Slow\",\n+};\n+\n+static SOC_ENUM_SINGLE_DECL(pcm_spd_enum, CS43130_PCM_FILT_OPT, 7,\n+\t\t\tpcm_spd_texts);\n+\n+static const SNDRV_CTL_TLVD_DECLARE_DB_MINMAX(master_tlv, -12750, 0);\n+\n+static const struct snd_kcontrol_new cs43130_controls[] = {\n+\tSOC_DOUBLE_R_TLV(\"Master Playback Volume\", CS43130_PCM_VOL_B,\n+\t\t\tCS43130_PCM_VOL_A, 0, 255, 1, master_tlv),\n+\tSOC_DOUBLE(\"Master Playback Switch\", CS43130_PCM_PATH_CTL_1,\n+\t\t\t0, 1, 1, 1),\n+\tSOC_DOUBLE_R_TLV(\"Digital Playback Volume\", CS43130_DSD_VOL_B,\n+\t\t\tCS43130_DSD_VOL_A, 0, 255, 1, master_tlv),\n+\tSOC_DOUBLE(\"Digital Playback Switch\", CS43130_DSD_PATH_CTL_1,\n+\t\t\t0, 1, 1, 1),\n+\tSOC_SINGLE(\"HV_Enable\", CS43130_HP_OUT_CTL_1, 0, 1, 0),\n+\tSOC_ENUM(\"PCM Filter Speed\", pcm_spd_enum),\n+\tSOC_SINGLE(\"PCM Phase Compensation\", CS43130_PCM_FILT_OPT, 6, 1, 0),\n+\tSOC_SINGLE(\"PCM Nonoversample Emulate\", CS43130_PCM_FILT_OPT, 5, 1, 0),\n+\tSOC_SINGLE(\"PCM High-pass Filter\", CS43130_PCM_FILT_OPT, 1, 1, 0),\n+\tSOC_SINGLE(\"PCM De-emphasis Filter\", CS43130_PCM_FILT_OPT, 0, 1, 0),\n+};\n+\n+static bool cs43130_readable_register(struct device *dev, unsigned int reg)\n+{\n+\tswitch (reg) {\n+\tcase CS43130_DEVID_AB ... CS43130_SYS_CLK_CTL_1:\n+\tcase CS43130_SP_SRATE ... CS43130_PAD_INT_CFG:\n+\tcase CS43130_PWDN_CTL:\n+\tcase CS43130_CRYSTAL_SET:\n+\tcase CS43130_PLL_SET_1 ... CS43130_PLL_SET_5:\n+\tcase CS43130_PLL_SET_6:\n+\tcase CS43130_PLL_SET_7:\n+\tcase CS43130_PLL_SET_8:\n+\tcase CS43130_PLL_SET_9:\n+\tcase CS43130_PLL_SET_10:\n+\tcase CS43130_CLKOUT_CTL:\n+\tcase CS43130_ASP_NUM_1 ... CS43130_ASP_FRAME_CONF:\n+\tcase CS43130_XSP_NUM_1 ... CS43130_XSP_FRAME_CONF:\n+\tcase CS43130_ASP_CH_1_LOC:\n+\tcase CS43130_ASP_CH_2_LOC:\n+\tcase CS43130_ASP_CH_1_SZ_EN:\n+\tcase CS43130_ASP_CH_2_SZ_EN:\n+\tcase CS43130_XSP_CH_1_LOC:\n+\tcase CS43130_XSP_CH_2_LOC:\n+\tcase CS43130_XSP_CH_1_SZ_EN:\n+\tcase CS43130_XSP_CH_2_SZ_EN:\n+\tcase CS43130_DSD_VOL_B ... CS43130_DSD_PATH_CTL_3:\n+\tcase CS43130_HP_OUT_CTL_1:\n+\tcase CS43130_PCM_FILT_OPT ... CS43130_PCM_PATH_CTL_2:\n+\tcase CS43130_CLASS_H_CTL:\n+\tcase CS43130_HP_DETECT:\n+\tcase CS43130_HP_STATUS:\n+\tcase CS43130_HP_LOAD_1:\n+\tcase CS43130_HP_MEAS_LOAD_1:\n+\tcase CS43130_HP_MEAS_LOAD_2:\n+\tcase CS43130_HP_DC_STAT_1:\n+\tcase CS43130_HP_DC_STAT_2:\n+\tcase CS43130_HP_AC_STAT_1:\n+\tcase CS43130_HP_AC_STAT_2:\n+\tcase CS43130_HP_LOAD_STAT:\n+\tcase CS43130_INT_STATUS_1 ... CS43130_INT_STATUS_5:\n+\tcase CS43130_INT_MASK_1 ... CS43130_INT_MASK_5:\n+\t\treturn true;\n+\tdefault:\n+\t\treturn false;\n+\t}\n+}\n+static bool cs43130_precious_register(struct device *dev, unsigned int reg)\n+{\n+\tswitch (reg) {\n+\tcase CS43130_INT_STATUS_1 ... CS43130_INT_STATUS_5:\n+\t\treturn true;\n+\tdefault:\n+\t\treturn false;\n+\t}\n+}\n+static int cs43130_pcm_pdn(struct snd_soc_component *component)\n+{\n+\tstruct cs43130_priv *cs43130 =\n+\t\t\t\tsnd_soc_component_get_drvdata(component);\n+\tint ret;\n+\tunsigned int reg, pdn_int;\n+\n+\tregmap_write(cs43130->regmap, CS43130_DSD_PATH_CTL_2, 0x02);\n+\tregmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1,\n+\t\t\tCS43130_PDN_DONE_INT_MASK, 0);\n+\tregmap_update_bits(cs43130->regmap, CS43130_PWDN_CTL,\n+\t\t\tCS43130_PDN_HP_MASK, 1 << CS43130_PDN_HP_SHIFT);\n+\tusleep_range(10, 50);\n+\tret = regmap_read(cs43130->regmap, CS43130_INT_STATUS_1, &reg);\n+\tpdn_int = reg & 0xFE;\n+\tregmap_update_bits(cs43130->regmap, CS43130_PWDN_CTL,\n+\t\t\tCS43130_PDN_ASP_MASK, 1 << CS43130_PDN_ASP_SHIFT);\n+\treturn 0;\n+\n+}\n+static int cs43130_pwr_up_asp_dac(struct snd_soc_component *component)\n+{\n+\tstruct cs43130_priv *cs43130 =\n+\t\t\t\tsnd_soc_component_get_drvdata(component);\n+\n+\tregmap_update_bits(cs43130->regmap, CS43130_PAD_INT_CFG,\n+\t\t\tCS43130_ASP_3ST_MASK, 0);\n+\tregmap_write(cs43130->regmap, CS43130_DXD1, 0x99);\n+\tregmap_write(cs43130->regmap, CS43130_DXD13, 0x20);\n+\tregmap_update_bits(cs43130->regmap, CS43130_PWDN_CTL,\n+\t\t\tCS43130_PDN_ASP_MASK, 0);\n+\tregmap_update_bits(cs43130->regmap, CS43130_PWDN_CTL,\n+\t\t\tCS43130_PDN_HP_MASK, 0);\n+\tusleep_range(10000, 12000);\n+\tregmap_write(cs43130->regmap, CS43130_DXD1, 0x00);\n+\tregmap_write(cs43130->regmap, CS43130_DXD13, 0x00);\n+\treturn 0;\n+}\n+static int cs43130_change_clksrc(struct snd_soc_component *component,\n+\t\t\t\tenum cs43130_mclk_src_sel src)\n+{\n+\tint ret;\n+\tstruct cs43130_priv *cs43130 =\n+\t\t\t\tsnd_soc_component_get_drvdata(component);\n+\tint mclk_int_decoded;\n+\n+\tif (src == cs43130->mclk_int_src) {\n+\t\t/* clk source has not changed */\n+\t\treturn 0;\n+\t}\n+\tswitch (cs43130->mclk_int) {\n+\tcase CS43130_MCLK_22M:\n+\t\tmclk_int_decoded = CS43130_MCLK_22P5;\n+\t\tbreak;\n+\tcase CS43130_MCLK_24M:\n+\t\tmclk_int_decoded = CS43130_MCLK_24P5;\n+\t\tbreak;\n+\tdefault:\n+\t\tdev_err(component->dev, \"Invalid MCLK INT freq: %u\\n\",\n+\t\t\tcs43130->mclk_int);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tswitch (src) {\n+\tcase CS43130_MCLK_SRC_EXT:\n+\t\tcs43130->pll_bypass = true;\n+\t\tcs43130->mclk_int_src = CS43130_MCLK_SRC_EXT;\n+\t\tif (cs43130->xtal_ibias == CS43130_XTAL_UNUSED) {\n+\t\t\tregmap_update_bits(cs43130->regmap, CS43130_PWDN_CTL,\n+\t\t\t\t\tCS43130_PDN_XTAL_MASK,\n+\t\t\t\t\t1 << CS43130_PDN_XTAL_SHIFT);\n+\t\t} else {\n+\t\t\treinit_completion(&cs43130->xtal_rdy);\n+\t\t\tregmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1,\n+\t\t\t\t\tCS43130_XTAL_RDY_INT_MASK, 0);\n+\t\t\tregmap_update_bits(cs43130->regmap, CS43130_PWDN_CTL,\n+\t\t\t\t\tCS43130_PDN_XTAL_MASK, 0);\n+\t\t\tret = wait_for_completion_timeout(&cs43130->xtal_rdy,\n+\t\t\t\t\tmsecs_to_jiffies(100));\n+\t\t\tregmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1,\n+\t\t\t\t\tCS43130_XTAL_RDY_INT_MASK,\n+\t\t\t\t\t1 << CS43130_XTAL_RDY_INT_SHIFT);\n+\t\t\tif (ret == 0) {\n+\t\t\t\tdev_err(component->dev, \"Timeout waiting for XTAL_READY interrupt\\n\");\n+\t\t\t\treturn -ETIMEDOUT;\n+\t\t\t}\n+\t\t}\n+\tregmap_update_bits(cs43130->regmap, CS43130_SYS_CLK_CTL_1,\n+\t\t\t\tCS43130_MCLK_SRC_SEL_MASK,\n+\t\t\t\tsrc << CS43130_MCLK_SRC_SEL_SHIFT);\n+\tregmap_update_bits(cs43130->regmap, CS43130_SYS_CLK_CTL_1,\n+\t\t\t\tCS43130_MCLK_INT_MASK,\n+\t\t\t\tmclk_int_decoded << CS43130_MCLK_INT_SHIFT);\n+\tusleep_range(150, 200);\n+\tregmap_update_bits(cs43130->regmap, CS43130_PWDN_CTL,\n+\t\t\t\tCS43130_PDN_PLL_MASK,\n+\t\t\t\t1 << CS43130_PDN_PLL_SHIFT);\n+\tbreak;\n+\tcase CS43130_MCLK_SRC_RCO:\n+\t\tcs43130->mclk_int_src = CS43130_MCLK_SRC_RCO;\n+\n+\t\tregmap_update_bits(cs43130->regmap, CS43130_SYS_CLK_CTL_1,\n+\t\t\t\tCS43130_MCLK_SRC_SEL_MASK,\n+\t\t\t\tsrc << CS43130_MCLK_SRC_SEL_SHIFT);\n+\t\tregmap_update_bits(cs43130->regmap, CS43130_SYS_CLK_CTL_1,\n+\t\t\t\tCS43130_MCLK_INT_MASK,\n+\t\t\t\tCS43130_MCLK_22P5 << CS43130_MCLK_INT_SHIFT);\n+\t\tusleep_range(150, 200);\n+\t\tregmap_update_bits(cs43130->regmap, CS43130_PWDN_CTL,\n+\t\t\t\tCS43130_PDN_XTAL_MASK,\n+\t\t\t\t1 << CS43130_PDN_XTAL_SHIFT);\n+\t\tregmap_update_bits(cs43130->regmap, CS43130_PWDN_CTL,\n+\t\t\t\tCS43130_PDN_PLL_MASK,\n+\t\t\t\t1 << CS43130_PDN_PLL_SHIFT);\n+\tbreak;\n+\tdefault:\n+\t\tdev_err(component->dev, \"Invalid MCLK source value\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\treturn 0;\n+}\n+static const struct cs43130_bitwidth_map cs43130_bitwidth_table[] = {\n+\t{8,     CS43130_SP_BIT_SIZE_8,  CS43130_CH_BIT_SIZE_8},\n+\t{16,    CS43130_SP_BIT_SIZE_16, CS43130_CH_BIT_SIZE_16},\n+\t{24,    CS43130_SP_BIT_SIZE_24, CS43130_CH_BIT_SIZE_24},\n+\t{32,    CS43130_SP_BIT_SIZE_32, CS43130_CH_BIT_SIZE_32},\n+};\n+\n+static const struct cs43130_bitwidth_map *cs43130_get_bitwidth_table(\n+\t\t\t\t\tunsigned int bitwidth)\n+{\n+\tint i;\n+\n+\tfor (i = 0; i < ARRAY_SIZE(cs43130_bitwidth_table); i++) {\n+\t\tif (cs43130_bitwidth_table[i].bitwidth == bitwidth)\n+\t\t\treturn &cs43130_bitwidth_table[i];\n+\t}\n+\n+\treturn NULL;\n+}\n+static int cs43130_set_bitwidth(int dai_id, unsigned int bitwidth_dai,\n+\t\t\t\tstruct regmap *regmap)\n+{\n+\tconst struct cs43130_bitwidth_map *bw_map;\n+\n+\tbw_map = cs43130_get_bitwidth_table(bitwidth_dai);\n+\tif (!bw_map)\n+\t\treturn -EINVAL;\n+\n+\tswitch (dai_id) {\n+\tcase CS43130_ASP_PCM_DAI:\n+\tcase CS43130_ASP_DOP_DAI:\n+\t\tregmap_update_bits(regmap, CS43130_ASP_CH_1_SZ_EN,\n+\t\t\t\tCS43130_CH_BITSIZE_MASK, bw_map->ch_bit);\n+\t\tregmap_update_bits(regmap, CS43130_ASP_CH_2_SZ_EN,\n+\t\t\t\tCS43130_CH_BITSIZE_MASK, bw_map->ch_bit);\n+\t\tregmap_update_bits(regmap, CS43130_SP_BITSIZE,\n+\t\t\t\tCS43130_ASP_BITSIZE_MASK, bw_map->sp_bit);\n+\t\tbreak;\n+\tcase CS43130_XSP_DOP_DAI:\n+\t\tregmap_update_bits(regmap, CS43130_XSP_CH_1_SZ_EN,\n+\t\t\t\tCS43130_CH_BITSIZE_MASK, bw_map->ch_bit);\n+\t\tregmap_update_bits(regmap, CS43130_XSP_CH_2_SZ_EN,\n+\t\t\t\tCS43130_CH_BITSIZE_MASK, bw_map->ch_bit);\n+\t\tregmap_update_bits(regmap, CS43130_SP_BITSIZE,\n+\t\t\t\tCS43130_XSP_BITSIZE_MASK, bw_map->sp_bit <<\n+\t\t\t\tCS43130_XSP_BITSIZE_SHIFT);\n+\tbreak;\n+\tdefault:\n+\t\treturn -EINVAL;\n+\t}\n+\n+\treturn 0;\n+}\n+static const struct cs43130_rate_map cs43130_rate_table[] = {\n+\t{32000,         CS43130_ASP_SPRATE_32K},\n+\t{44100,         CS43130_ASP_SPRATE_44_1K},\n+\t{48000,         CS43130_ASP_SPRATE_48K},\n+\t{88200,         CS43130_ASP_SPRATE_88_2K},\n+\t{96000,         CS43130_ASP_SPRATE_96K},\n+\t{176400,        CS43130_ASP_SPRATE_176_4K},\n+\t{192000,        CS43130_ASP_SPRATE_192K},\n+\t{352800,        CS43130_ASP_SPRATE_352_8K},\n+\t{384000,        CS43130_ASP_SPRATE_384K},\n+};\n+\n+static const struct cs43130_rate_map *cs43130_get_rate_table(int fs)\n+{\n+\tint i;\n+\n+\tfor (i = 0; i < ARRAY_SIZE(cs43130_rate_table); i++) {\n+\t\tif (cs43130_rate_table[i].fs == fs)\n+\t\t\treturn &cs43130_rate_table[i];\n+\t}\n+\n+\treturn NULL;\n+}\n+\n+static const struct cs43130_clk_gen *cs43130_get_clk_gen(int mclk_int, int fs,\n+\tconst struct cs43130_clk_gen *clk_gen_table, int len_clk_gen_table)\n+{\n+\tint i;\n+\n+\tfor (i = 0; i < len_clk_gen_table; i++) {\n+\t\tif (clk_gen_table[i].mclk_int == mclk_int &&\n+\t\t\t\t\tclk_gen_table[i].fs == fs)\n+\t\t\treturn &clk_gen_table[i];\n+\t}\n+\treturn NULL;\n+}\n+\n+static int cs43130_set_sp_fmt(int dai_id, unsigned int bitwidth_sclk,\n+\t\t\t\tstruct snd_pcm_hw_params *params,\n+\t\t\t\tstruct cs43130_priv *cs43130)\n+{\n+\tu16 frm_size;\n+\tu16 hi_size;\n+\tu8 frm_delay;\n+\tu8 frm_phase;\n+\tu8 frm_data;\n+\tu8 sclk_edge;\n+\tu8 lrck_edge;\n+\tu8 clk_data;\n+\tu8 loc_ch1;\n+\tu8 loc_ch2;\n+\tu8 dai_mode_val;\n+\tconst struct cs43130_clk_gen *clk_gen;\n+\n+\tswitch (cs43130->dais[dai_id].dai_format) {\n+\tcase SND_SOC_DAIFMT_I2S:\n+\t\thi_size = bitwidth_sclk;\n+\t\tfrm_delay = 2;\n+\t\tfrm_phase = 0;\n+\t\tbreak;\n+\tcase SND_SOC_DAIFMT_LEFT_J:\n+\t\thi_size = bitwidth_sclk;\n+\t\tfrm_delay = 2;\n+\t\tfrm_phase = 1;\n+\t\tbreak;\n+\tcase SND_SOC_DAIFMT_DSP_A:\n+\t\thi_size = 1;\n+\t\tfrm_delay = 2;\n+\t\tfrm_phase = 1;\n+\t\tbreak;\n+\tcase SND_SOC_DAIFMT_DSP_B:\n+\t\thi_size = 1;\n+\t\tfrm_delay = 0;\n+\t\tfrm_phase = 1;\n+\t\tbreak;\n+\tdefault:\n+\t\treturn -EINVAL;\n+\t}\n+\tswitch (cs43130->dais[dai_id].dai_mode) {\n+\tcase SND_SOC_DAIFMT_CBS_CFS:\n+\t\tdai_mode_val = 0;\n+\t\tbreak;\n+\tcase SND_SOC_DAIFMT_CBM_CFM:\n+\t\tdai_mode_val = 1;\n+\t\tbreak;\n+\tdefault:\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tfrm_size = bitwidth_sclk * params_channels(params);\n+\tsclk_edge = 1;\n+\tlrck_edge = 0;\n+\tloc_ch1 = 0;\n+\tloc_ch2 = bitwidth_sclk * (params_channels(params) - 1);\n+\n+\tfrm_data = frm_delay & CS43130_SP_FSD_MASK;\n+\tfrm_data |= (frm_phase << CS43130_SP_STP_SHIFT) & CS43130_SP_STP_MASK;\n+\n+\tclk_data = lrck_edge & CS43130_SP_LCPOL_IN_MASK;\n+\tclk_data |= (lrck_edge << CS43130_SP_LCPOL_OUT_SHIFT) &\n+\t\t\tCS43130_SP_LCPOL_OUT_MASK;\n+\tclk_data |= (sclk_edge << CS43130_SP_SCPOL_IN_SHIFT) &\n+\t\t\tCS43130_SP_SCPOL_IN_MASK;\n+\tclk_data |= (sclk_edge << CS43130_SP_SCPOL_OUT_SHIFT) &\n+\t\t\tCS43130_SP_SCPOL_OUT_MASK;\n+\tclk_data |= (dai_mode_val << CS43130_SP_MODE_SHIFT) &\n+\t\t\tCS43130_SP_MODE_MASK;\n+\tswitch (dai_id) {\n+\tcase CS43130_ASP_PCM_DAI:\n+\tcase CS43130_ASP_DOP_DAI:\n+\t\tregmap_update_bits(cs43130->regmap, CS43130_ASP_LRCK_PERIOD_1,\n+\t\t\tCS43130_SP_LCPR_DATA_MASK, (frm_size - 1) >>\n+\t\t\tCS43130_SP_LCPR_LSB_DATA_SHIFT);\n+\t\tregmap_update_bits(cs43130->regmap, CS43130_ASP_LRCK_PERIOD_2,\n+\t\t\tCS43130_SP_LCPR_DATA_MASK, (frm_size - 1) >>\n+\t\t\tCS43130_SP_LCPR_MSB_DATA_SHIFT);\n+\t\tregmap_update_bits(cs43130->regmap, CS43130_ASP_LRCK_HI_TIME_1,\n+\t\t\tCS43130_SP_LCHI_DATA_MASK, (hi_size - 1) >>\n+\t\t\tCS43130_SP_LCHI_LSB_DATA_SHIFT);\n+\t\tregmap_update_bits(cs43130->regmap, CS43130_ASP_LRCK_HI_TIME_2,\n+\t\t\tCS43130_SP_LCHI_DATA_MASK, (hi_size - 1) >>\n+\t\t\tCS43130_SP_LCHI_MSB_DATA_SHIFT);\n+\t\tregmap_write(cs43130->regmap, CS43130_ASP_FRAME_CONF, frm_data);\n+\t\tregmap_write(cs43130->regmap, CS43130_ASP_CH_1_LOC, loc_ch1);\n+\t\tregmap_write(cs43130->regmap, CS43130_ASP_CH_2_LOC, loc_ch2);\n+\t\tregmap_update_bits(cs43130->regmap, CS43130_ASP_CH_1_SZ_EN,\n+\t\t\tCS43130_CH_EN_MASK, 1 << CS43130_CH_EN_SHIFT);\n+\t\tregmap_update_bits(cs43130->regmap, CS43130_ASP_CH_2_SZ_EN,\n+\t\t\tCS43130_CH_EN_MASK, 1 << CS43130_CH_EN_SHIFT);\n+\t\tregmap_write(cs43130->regmap, CS43130_ASP_CLOCK_CONF, clk_data);\n+\t\tbreak;\n+\tcase CS43130_XSP_DOP_DAI:\n+\t\tregmap_update_bits(cs43130->regmap, CS43130_XSP_LRCK_PERIOD_1,\n+\t\t\tCS43130_SP_LCPR_DATA_MASK, (frm_size - 1) >>\n+\t\t\tCS43130_SP_LCPR_LSB_DATA_SHIFT);\n+\t\tregmap_update_bits(cs43130->regmap, CS43130_XSP_LRCK_PERIOD_2,\n+\t\t\tCS43130_SP_LCPR_DATA_MASK, (frm_size - 1) >>\n+\t\t\tCS43130_SP_LCPR_MSB_DATA_SHIFT);\n+\t\tregmap_update_bits(cs43130->regmap, CS43130_XSP_LRCK_HI_TIME_1,\n+\t\t\tCS43130_SP_LCHI_DATA_MASK, (hi_size - 1) >>\n+\t\t\tCS43130_SP_LCHI_LSB_DATA_SHIFT);\n+\t\tregmap_update_bits(cs43130->regmap, CS43130_XSP_LRCK_HI_TIME_2,\n+\t\t\tCS43130_SP_LCHI_DATA_MASK, (hi_size - 1) >>\n+\t\t\tCS43130_SP_LCHI_MSB_DATA_SHIFT);\n+\t\tregmap_write(cs43130->regmap, CS43130_XSP_FRAME_CONF, frm_data);\n+\t\tregmap_write(cs43130->regmap, CS43130_XSP_CH_1_LOC, loc_ch1);\n+\t\tregmap_write(cs43130->regmap, CS43130_XSP_CH_2_LOC, loc_ch2);\n+\t\tregmap_update_bits(cs43130->regmap, CS43130_XSP_CH_1_SZ_EN,\n+\t\t\tCS43130_CH_EN_MASK, 1 << CS43130_CH_EN_SHIFT);\n+\t\tregmap_update_bits(cs43130->regmap, CS43130_XSP_CH_2_SZ_EN,\n+\t\t\tCS43130_CH_EN_MASK, 1 << CS43130_CH_EN_SHIFT);\n+\t\tregmap_write(cs43130->regmap, CS43130_XSP_CLOCK_CONF, clk_data);\n+\t\tbreak;\n+\tdefault:\n+\t\treturn -EINVAL;\n+\t}\n+\tswitch (frm_size) {\n+\tcase 16:\n+\t\tclk_gen = cs43130_get_clk_gen(cs43130->mclk_int,\n+\t\t\t\t\t\tparams_rate(params),\n+\t\t\t\t\t\tcs43130_16_clk_gen,\n+\t\t\t\t\t\tARRAY_SIZE(cs43130_16_clk_gen));\n+\t\tbreak;\n+\tcase 32:\n+\t\tclk_gen = cs43130_get_clk_gen(cs43130->mclk_int,\n+\t\t\t\t\t\tparams_rate(params),\n+\t\t\t\t\t\tcs43130_32_clk_gen,\n+\t\t\t\t\t\tARRAY_SIZE(cs43130_32_clk_gen));\n+\t\tbreak;\n+\tcase 48:\n+\t\tclk_gen = cs43130_get_clk_gen(cs43130->mclk_int,\n+\t\t\t\t\t\tparams_rate(params),\n+\t\t\t\t\t\tcs43130_48_clk_gen,\n+\t\t\t\t\t\tARRAY_SIZE(cs43130_48_clk_gen));\n+\t\tbreak;\n+\tcase 64:\n+\t\tclk_gen = cs43130_get_clk_gen(cs43130->mclk_int,\n+\t\t\t\t\t\tparams_rate(params),\n+\t\t\t\t\t\tcs43130_64_clk_gen,\n+\t\t\t\t\t\tARRAY_SIZE(cs43130_64_clk_gen));\n+\t\tbreak;\n+\tdefault:\n+\t\treturn -EINVAL;\n+\t}\n+\tif (!clk_gen)\n+\t\treturn -EINVAL;\n+\tswitch (dai_id) {\n+\tcase CS43130_ASP_PCM_DAI:\n+\tcase CS43130_ASP_DOP_DAI:\n+\t\tregmap_write(cs43130->regmap, CS43130_ASP_DEN_1,\n+\t\t\t\t(clk_gen->den & CS43130_SP_M_LSB_DATA_MASK) >>\n+\t\t\t\tCS43130_SP_M_LSB_DATA_SHIFT);\n+\t\tregmap_write(cs43130->regmap, CS43130_ASP_DEN_2,\n+\t\t\t\t(clk_gen->den & CS43130_SP_M_MSB_DATA_MASK) >>\n+\t\t\t\tCS43130_SP_M_MSB_DATA_SHIFT);\n+\t\tregmap_write(cs43130->regmap, CS43130_ASP_NUM_1,\n+\t\t\t\t(clk_gen->num & CS43130_SP_N_LSB_DATA_MASK) >>\n+\t\t\t\tCS43130_SP_N_LSB_DATA_SHIFT);\n+\t\tregmap_write(cs43130->regmap, CS43130_ASP_NUM_2,\n+\t\t\t\t(clk_gen->num & CS43130_SP_N_MSB_DATA_MASK) >>\n+\t\t\t\tCS43130_SP_N_MSB_DATA_SHIFT);\n+\t\tbreak;\n+\tcase CS43130_XSP_DOP_DAI:\n+\t\tregmap_write(cs43130->regmap, CS43130_XSP_DEN_1,\n+\t\t\t\t(clk_gen->den & CS43130_SP_M_LSB_DATA_MASK) >>\n+\t\t\t\tCS43130_SP_M_LSB_DATA_SHIFT);\n+\t\tregmap_write(cs43130->regmap, CS43130_XSP_DEN_2,\n+\t\t\t\t(clk_gen->den & CS43130_SP_M_MSB_DATA_MASK) >>\n+\t\t\t\tCS43130_SP_M_MSB_DATA_SHIFT);\n+\t\tregmap_write(cs43130->regmap, CS43130_XSP_NUM_1,\n+\t\t\t\t(clk_gen->num & CS43130_SP_N_LSB_DATA_MASK) >>\n+\t\t\t\tCS43130_SP_N_LSB_DATA_SHIFT);\n+\t\tregmap_write(cs43130->regmap, CS43130_XSP_NUM_2,\n+\t\t\t\t(clk_gen->num & CS43130_SP_N_MSB_DATA_MASK) >>\n+\t\t\t\tCS43130_SP_N_MSB_DATA_SHIFT);\n+\t\tbreak;\n+\tdefault:\n+\t\treturn -EINVAL;\n+\t}\n+\treturn 0;\n+}\n+\n+static int cs43130_hw_params(struct snd_pcm_substream *substream,\n+\t\t\t\tstruct snd_pcm_hw_params *params,\n+\t\t\t\tstruct snd_soc_dai *dai)\n+{\n+\tstruct snd_soc_component *component = dai->component;\n+\tstruct cs43130_priv *cs43130 =\n+\t\t\t\tsnd_soc_component_get_drvdata(component);\n+\tconst struct cs43130_rate_map *rate_map;\n+\tunsigned int sclk = cs43130->dais[dai->id].sclk;\n+\tunsigned int bitwidth_sclk;\n+\tunsigned int bitwidth_dai = (unsigned int)(params_width(params));\n+\tunsigned int dop_rate = (unsigned int)(params_rate(params));\n+\tunsigned int required_clk, ret;\n+\tu8 dsd_speed;\n+\n+\tcs43130->pll_bypass = true;\n+\tcs43130_pcm_pdn(component);\n+\tmutex_lock(&cs43130->clk_mutex);\n+\tif (!cs43130->clk_req) {\n+\t\t/* no DAI is currently using clk */\n+\t\tif (!(CS43130_MCLK_22M % params_rate(params))) {\n+\t\t\trequired_clk = CS43130_MCLK_22M;\n+\t\t\tcs43130->mclk_int =  CS43130_MCLK_22M;\n+\t\t\tgpiod_set_value_cansleep(snd_allo_clk44gpio, 1);\n+\t\t\tgpiod_set_value_cansleep(snd_allo_clk48gpio, 0);\n+\t\t\tusleep_range(13500, 14000);\n+\t\t} else {\n+\t\t\trequired_clk = CS43130_MCLK_24M;\n+\t\t\tcs43130->mclk_int =  CS43130_MCLK_24M;\n+\t\t\tgpiod_set_value_cansleep(snd_allo_clk48gpio, 1);\n+\t\t\tgpiod_set_value_cansleep(snd_allo_clk44gpio, 0);\n+\t\t\tusleep_range(13500, 14000);\n+\t\t}\n+\t\tif (cs43130->pll_bypass)\n+\t\t\tcs43130_change_clksrc(component, CS43130_MCLK_SRC_EXT);\n+\t\telse\n+\t\t\tcs43130_change_clksrc(component, CS43130_MCLK_SRC_PLL);\n+\t}\n+\n+\tcs43130->clk_req++;\n+\tmutex_unlock(&cs43130->clk_mutex);\n+\n+\tswitch (dai->id) {\n+\tcase CS43130_ASP_DOP_DAI:\n+\tcase CS43130_XSP_DOP_DAI:\n+\t\t/* DoP bitwidth is always 24-bit */\n+\t\tbitwidth_dai = 24;\n+\t\tsclk = params_rate(params) * bitwidth_dai *\n+\t\t\t\tparams_channels(params);\n+\n+\t\tswitch (params_rate(params)) {\n+\t\tcase 176400:\n+\t\t\tdsd_speed = 0;\n+\t\t\tbreak;\n+\t\tcase 352800:\n+\t\t\tdsd_speed = 1;\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tdev_err(component->dev, \"Rate(%u) not supported\\n\",\n+\t\t\t\tparams_rate(params));\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\n+\t\tregmap_update_bits(cs43130->regmap, CS43130_DSD_PATH_CTL_2,\n+\t\t\t\t\tCS43130_DSD_SPEED_MASK,\n+\t\t\t\t\tdsd_speed << CS43130_DSD_SPEED_SHIFT);\n+\t\tbreak;\n+\tcase CS43130_ASP_PCM_DAI:\n+\t\trate_map = cs43130_get_rate_table(params_rate(params));\n+\t\tif (!rate_map)\n+\t\t\treturn -EINVAL;\n+\n+\t\tregmap_write(cs43130->regmap, CS43130_SP_SRATE, rate_map->val);\n+\t\tif ((dop_rate == 176400) && (bitwidth_dai == 24)) {\n+\t\t\tdsd_speed = 0;\n+\t\t\tregmap_update_bits(cs43130->regmap,\n+\t\t\t\t\tCS43130_DSD_PATH_CTL_2,\n+\t\t\t\t\tCS43130_DSD_SPEED_MASK,\n+\t\t\t\t\tdsd_speed << CS43130_DSD_SPEED_SHIFT);\n+\t\t\tregmap_update_bits(cs43130->regmap,\n+\t\t\t\t\tCS43130_DSD_PATH_CTL_2,\n+\t\t\t\t\tCS43130_DSD_SRC_MASK,\n+\t\t\t\t\tCS43130_DSD_SRC_ASP <<\n+\t\t\t\t\tCS43130_DSD_SRC_SHIFT);\n+\t\t\tregmap_update_bits(cs43130->regmap,\n+\t\t\t\t\tCS43130_DSD_PATH_CTL_2,\n+\t\t\t\t\tCS43130_DSD_EN_MASK, 0x01 <<\n+\t\t\t\t\tCS43130_DSD_EN_SHIFT);\n+\t\t}\n+\t\tbreak;\n+\tdefault:\n+\t\tdev_err(component->dev, \"Invalid DAI (%d)\\n\", dai->id);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tswitch (dai->id) {\n+\tcase CS43130_ASP_DOP_DAI:\n+\t\tregmap_update_bits(cs43130->regmap, CS43130_DSD_PATH_CTL_2,\n+\t\t\t\tCS43130_DSD_SRC_MASK, CS43130_DSD_SRC_ASP <<\n+\t\t\t\tCS43130_DSD_SRC_SHIFT);\n+\t\tregmap_update_bits(cs43130->regmap, CS43130_DSD_PATH_CTL_2,\n+\t\t\t\tCS43130_DSD_EN_MASK, 0x01 <<\n+\t\t\t\tCS43130_DSD_EN_SHIFT);\n+\t\tbreak;\n+\tcase CS43130_XSP_DOP_DAI:\n+\t\tregmap_update_bits(cs43130->regmap, CS43130_DSD_PATH_CTL_2,\n+\t\t\t\tCS43130_DSD_SRC_MASK, CS43130_DSD_SRC_XSP <<\n+\t\t\t\tCS43130_DSD_SRC_SHIFT);\n+\t\tbreak;\n+\t}\n+\tif (!sclk && cs43130->dais[dai->id].dai_mode ==\n+\t\t\t\t\t\tSND_SOC_DAIFMT_CBM_CFM) {\n+\t\t/* Calculate SCLK in master mode if unassigned */\n+\t\tsclk = params_rate(params) * bitwidth_dai *\n+\t\t\t\tparams_channels(params);\n+\t}\n+\tif (!sclk) {\n+\t\t/* at this point, SCLK must be set */\n+\t\tdev_err(component->dev, \"SCLK freq is not set\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tbitwidth_sclk = (sclk / params_rate(params)) / params_channels(params);\n+\tif (bitwidth_sclk < bitwidth_dai) {\n+\t\tdev_err(component->dev, \"Format not supported: SCLK freq is too low\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tdev_dbg(component->dev,\n+\t\t\"sclk = %u, fs = %d, bitwidth_dai = %u\\n\",\n+\t\tsclk, params_rate(params), bitwidth_dai);\n+\n+\tdev_dbg(component->dev,\n+\t\t\"bitwidth_sclk = %u, num_ch = %u\\n\",\n+\t\tbitwidth_sclk, params_channels(params));\n+\n+\tcs43130_set_bitwidth(dai->id, bitwidth_dai, cs43130->regmap);\n+\tcs43130_set_sp_fmt(dai->id, bitwidth_sclk, params, cs43130);\n+\tret = cs43130_pwr_up_asp_dac(component);\n+\treturn 0;\n+}\n+\n+static int cs43130_hw_free(struct snd_pcm_substream *substream,\n+\t\t\t\t\tstruct snd_soc_dai *dai)\n+{\n+\tstruct snd_soc_component *component = dai->component;\n+\tstruct cs43130_priv *cs43130 =\n+\t\t\t\tsnd_soc_component_get_drvdata(component);\n+\n+\tmutex_lock(&cs43130->clk_mutex);\n+\tcs43130->clk_req--;\n+\tif (!cs43130->clk_req) {\n+\t\t/* no DAI is currently using clk */\n+\t\tcs43130_change_clksrc(component, CS43130_MCLK_SRC_RCO);\n+\t\tcs43130_pcm_pdn(component);\n+\t}\n+\tmutex_unlock(&cs43130->clk_mutex);\n+\n+\treturn 0;\n+}\n+\n+static const unsigned int cs43130_asp_src_rates[] = {\n+\t32000, 44100, 48000, 88200, 96000, 176400, 192000\n+};\n+\n+static const struct snd_pcm_hw_constraint_list cs43130_asp_constraints = {\n+\t.count  = ARRAY_SIZE(cs43130_asp_src_rates),\n+\t.list   = cs43130_asp_src_rates,\n+};\n+\n+static int cs43130_pcm_startup(struct snd_pcm_substream *substream,\n+\t\t\t\t\tstruct snd_soc_dai *dai)\n+{\n+\treturn snd_pcm_hw_constraint_list(substream->runtime, 0,\n+\t\t\t\t\tSNDRV_PCM_HW_PARAM_RATE,\n+\t\t\t\t\t&cs43130_asp_constraints);\n+}\n+\n+static int cs43130_pcm_set_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)\n+{\n+\tstruct snd_soc_component *component = codec_dai->component;\n+\tstruct cs43130_priv *cs43130 =\n+\t\t\t\tsnd_soc_component_get_drvdata(component);\n+\n+\tswitch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {\n+\tcase SND_SOC_DAIFMT_CBS_CFS:\n+\t\tcs43130->dais[codec_dai->id].dai_mode = SND_SOC_DAIFMT_CBS_CFS;\n+\t\tbreak;\n+\tcase SND_SOC_DAIFMT_CBM_CFM:\n+\t\tcs43130->dais[codec_dai->id].dai_mode = SND_SOC_DAIFMT_CBM_CFM;\n+\t\tbreak;\n+\tdefault:\n+\t\tdev_err(component->dev, \"unsupported mode\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tswitch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {\n+\tcase SND_SOC_DAIFMT_I2S:\n+\t\tcs43130->dais[codec_dai->id].dai_format = SND_SOC_DAIFMT_I2S;\n+\t\tbreak;\n+\tcase SND_SOC_DAIFMT_LEFT_J:\n+\t\tcs43130->dais[codec_dai->id].dai_format = SND_SOC_DAIFMT_LEFT_J;\n+\t\tbreak;\n+\tdefault:\n+\t\tdev_err(component->dev,\n+\t\t\t\"unsupported audio format\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tdev_dbg(component->dev, \"dai_id = %d,  dai_mode = %u, dai_format = %u\\n\",\n+\t\t\tcodec_dai->id,\n+\t\t\tcs43130->dais[codec_dai->id].dai_mode,\n+\t\t\tcs43130->dais[codec_dai->id].dai_format);\n+\n+\treturn 0;\n+}\n+\n+static int cs43130_set_sysclk(struct snd_soc_dai *codec_dai,\n+\t\t\t\t\tint clk_id, unsigned int freq, int dir)\n+{\n+\tstruct snd_soc_component *component = codec_dai->component;\n+\tstruct cs43130_priv *cs43130 =\n+\t\t\t\tsnd_soc_component_get_drvdata(component);\n+\n+\tcs43130->dais[codec_dai->id].sclk = freq;\n+\tdev_dbg(component->dev, \"dai_id = %d,  sclk = %u\\n\", codec_dai->id,\n+\t\t\t\tcs43130->dais[codec_dai->id].sclk);\n+\n+\treturn 0;\n+}\n+\n+static int cs43130_component_set_sysclk(struct snd_soc_component *component,\n+\t\t\t\t\tint clk_id, int source,\n+\t\t\t\t\tunsigned int freq, int dir)\n+{\n+\tstruct cs43130_priv *cs43130 =\n+\t\t\t\tsnd_soc_component_get_drvdata(component);\n+\n+\tdev_dbg(component->dev, \"clk_id = %d, source = %d, freq = %d, dir = %d\\n\",\n+\t\tclk_id, source, freq, dir);\n+\n+\tswitch (freq) {\n+\tcase CS43130_MCLK_22M:\n+\tcase CS43130_MCLK_24M:\n+\t\tcs43130->mclk = freq;\n+\t\tbreak;\n+\tdefault:\n+\t\tdev_err(component->dev, \"Invalid MCLK INT freq: %u\\n\", freq);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (source == CS43130_MCLK_SRC_EXT) {\n+\t\tcs43130->pll_bypass = true;\n+\t} else {\n+\t\tdev_err(component->dev, \"Invalid MCLK source\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\treturn 0;\n+}\n+static u16 const cs43130_ac_freq[CS43130_AC_FREQ] = {\n+\t24,\n+\t43,\n+\t93,\n+\t200,\n+\t431,\n+\t928,\n+\t2000,\n+\t4309,\n+\t9283,\n+\t20000,\n+};\n+static const struct snd_soc_dai_ops cs43130_dai_ops = {\n+\t.startup        = cs43130_pcm_startup,\n+\t.hw_params\t= cs43130_hw_params,\n+\t.hw_free        = cs43130_hw_free,\n+\t.set_sysclk     = cs43130_set_sysclk,\n+\t.set_fmt        = cs43130_pcm_set_fmt,\n+};\n+\n+static struct snd_soc_dai_driver cs43130_codec_dai = {\n+\t.name = \"allo-cs43130\",\n+\t.playback = {\n+\t\t.stream_name = \"Playback\",\n+\t\t.channels_min = 2,\n+\t\t.channels_max = 2,\n+\t\t.rates = SNDRV_PCM_RATE_CONTINUOUS,\n+\t\t.rate_min = 44100,\n+\t\t.rate_max = 192000,\n+\t\t.formats = SNDRV_PCM_FMTBIT_S16_LE |\n+\t\t\tSNDRV_PCM_FMTBIT_S24_LE |\n+\t\t\tSNDRV_PCM_FMTBIT_S32_LE\n+\n+\t},\n+\t.ops = &cs43130_dai_ops,\n+};\n+\n+static struct snd_soc_component_driver cs43130_component_driver = {\n+\t.idle_bias_on           = true,\n+\t.controls\t\t= cs43130_controls,\n+\t.num_controls\t\t= ARRAY_SIZE(cs43130_controls),\n+\t.set_sysclk             = cs43130_component_set_sysclk,\n+\t.idle_bias_on           = 1,\n+\t.use_pmdown_time        = 1,\n+\t.endianness             = 1,\n+\t.non_legacy_dai_naming  = 1,\n+};\n+\n+static const struct regmap_config cs43130_regmap = {\n+\t.reg_bits               = 24,\n+\t.pad_bits               = 8,\n+\t.val_bits               = 8,\n+\n+\t.max_register           = CS43130_LASTREG,\n+\t.reg_defaults           = cs43130_reg_defaults,\n+\t.num_reg_defaults       = ARRAY_SIZE(cs43130_reg_defaults),\n+\t.readable_reg           = cs43130_readable_register,\n+\t.precious_reg           = cs43130_precious_register,\n+\t.volatile_reg           = cs43130_volatile_register,\n+\t.cache_type             = REGCACHE_RBTREE,\n+\t/* needed for regcache_sync */\n+\t.use_single_read        = true,\n+\t.use_single_write       = true,\n+};\n+\n+static u16 const cs43130_dc_threshold[CS43130_DC_THRESHOLD] = {\n+\t50,\n+\t120,\n+};\n+\n+static int cs43130_handle_device_data(struct i2c_client *i2c_client,\n+\t\t\t\t\tstruct cs43130_priv *cs43130)\n+{\n+\tstruct device_node *np = i2c_client->dev.of_node;\n+\tunsigned int val;\n+\tint i;\n+\n+\tif (of_property_read_u32(np, \"cirrus,xtal-ibias\", &val) < 0) {\n+\t/* Crystal is unused. System clock is used for external MCLK */\n+\t\tcs43130->xtal_ibias = CS43130_XTAL_UNUSED;\n+\t\treturn 0;\n+\t}\n+\n+\tswitch (val) {\n+\tcase 1:\n+\t\tcs43130->xtal_ibias = CS43130_XTAL_IBIAS_7_5UA;\n+\t\tbreak;\n+\tcase 2:\n+\t\tcs43130->xtal_ibias = CS43130_XTAL_IBIAS_12_5UA;\n+\t\tbreak;\n+\tcase 3:\n+\t\tcs43130->xtal_ibias = CS43130_XTAL_IBIAS_15UA;\n+\t\tbreak;\n+\tdefault:\n+\t\tdev_err(&i2c_client->dev,\n+\t\t\t\"Invalid cirrus,xtal-ibias value: %d\\n\", val);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tcs43130->dc_meas = of_property_read_bool(np, \"cirrus,dc-measure\");\n+\tcs43130->ac_meas = of_property_read_bool(np, \"cirrus,ac-measure\");\n+\n+\tif (of_property_read_u16_array(np, \"cirrus,ac-freq\", cs43130->ac_freq,\n+\t\t\t\t\tCS43130_AC_FREQ) < 0) {\n+\t\tfor (i = 0; i < CS43130_AC_FREQ; i++)\n+\t\t\tcs43130->ac_freq[i] = cs43130_ac_freq[i];\n+\t}\n+\n+\tif (of_property_read_u16_array(np, \"cirrus,dc-threshold\",\n+\t\t\t\t\tcs43130->dc_threshold,\n+\t\t\t\t\tCS43130_DC_THRESHOLD) < 0) {\n+\t\tfor (i = 0; i < CS43130_DC_THRESHOLD; i++)\n+\t\t\tcs43130->dc_threshold[i] = cs43130_dc_threshold[i];\n+\t}\n+\n+\treturn 0;\n+}\n+\n+\n+static int allo_cs43130_component_probe(struct i2c_client *i2c,\n+\t\t\t     const struct i2c_device_id *id)\n+{\n+\tstruct regmap *regmap;\n+\tstruct regmap_config config = cs43130_regmap;\n+\tstruct device *dev = &i2c->dev;\n+\tstruct cs43130_priv *cs43130;\n+\tunsigned int devid = 0;\n+\tunsigned int reg;\n+\tint ret;\n+\n+\tregmap = devm_regmap_init_i2c(i2c, &config);\n+\tif (IS_ERR(regmap))\n+\t\treturn PTR_ERR(regmap);\n+\n+\tcs43130 = devm_kzalloc(dev, sizeof(struct cs43130_priv),\n+\t\t\t\t\tGFP_KERNEL);\n+\tif (!cs43130)\n+\t\treturn -ENOMEM;\n+\n+\tdev_set_drvdata(dev, cs43130);\n+\tcs43130->regmap = regmap;\n+\n+\tif (i2c->dev.of_node) {\n+\t\tret = cs43130_handle_device_data(i2c, cs43130);\n+\t\tif (ret != 0)\n+\t\t\treturn ret;\n+\t}\n+\tusleep_range(2000, 2050);\n+\n+\tret = regmap_read(cs43130->regmap, CS43130_DEVID_AB, &reg);\n+\tdevid = (reg & 0xFF) << 12;\n+\tret = regmap_read(cs43130->regmap, CS43130_DEVID_CD, &reg);\n+\tdevid |= (reg & 0xFF) << 4;\n+\tret = regmap_read(cs43130->regmap, CS43130_DEVID_E, &reg);\n+\tdevid |= (reg & 0xF0) >> 4;\n+\tif (devid != CS43198_CHIP_ID) {\n+\t\tdev_err(dev, \"Failed to read Chip or wrong Chip id: %d\\n\", ret);\n+\t\treturn ret;\n+\t}\n+\n+\tcs43130->mclk_int_src = CS43130_MCLK_SRC_RCO;\n+\tmsleep(20);\n+\n+\tret = snd_soc_register_component(dev, &cs43130_component_driver,\n+\t\t\t\t    &cs43130_codec_dai, 1);\n+\tif (ret != 0) {\n+\t\tdev_err(dev, \"failed to register codec: %d\\n\", ret);\n+\t\treturn ret;\n+\t}\n+\tregmap_update_bits(cs43130->regmap, CS43130_PAD_INT_CFG,\n+\t\t\tCS43130_ASP_3ST_MASK, 0);\n+\tregmap_update_bits(cs43130->regmap, CS43130_PAD_INT_CFG,\n+\t\t\tCS43130_XSP_3ST_MASK, 1);\n+\tregmap_update_bits(cs43130->regmap, CS43130_PWDN_CTL,\n+\t\t\tCS43130_PDN_HP_MASK, 1 << CS43130_PDN_HP_SHIFT);\n+\tmsleep(20);\n+\tregmap_write(cs43130->regmap, CS43130_CLASS_H_CTL, 0x06);\n+\tsnd_allo_clk44gpio = devm_gpiod_get(dev, \"clock44\", GPIOD_OUT_HIGH);\n+\tif (IS_ERR(snd_allo_clk44gpio))\n+\t\tdev_err(dev, \"devm_gpiod_get() failed\\n\");\n+\n+\tsnd_allo_clk48gpio = devm_gpiod_get(dev, \"clock48\", GPIOD_OUT_LOW);\n+\tif (IS_ERR(snd_allo_clk48gpio))\n+\t\tdev_err(dev, \"devm_gpiod_get() failed\\n\");\n+\n+\treturn 0;\n+}\n+\n+static int allo_cs43130_component_remove(struct i2c_client *i2c)\n+{\n+\tsnd_soc_unregister_component(&i2c->dev);\n+\treturn 0;\n+}\n+\n+static const struct i2c_device_id allo_cs43130_component_id[] = {\n+\t{ \"allo-cs43198\", },\n+\t{ }\n+};\n+MODULE_DEVICE_TABLE(i2c, allo_cs43130_component_id);\n+\n+static const struct of_device_id allo_cs43130_codec_of_match[] = {\n+\t{ .compatible = \"allo,allo-cs43198\", },\n+\t{ }\n+};\n+MODULE_DEVICE_TABLE(of, allo_cs43130_codec_of_match);\n+\n+static struct i2c_driver allo_cs43130_component_driver = {\n+\t.probe\t\t= allo_cs43130_component_probe,\n+\t.remove\t\t= allo_cs43130_component_remove,\n+\t.id_table\t= allo_cs43130_component_id,\n+\t.driver\t\t= {\n+\t.name\t\t= \"allo-cs43198\",\n+\t.of_match_table = allo_cs43130_codec_of_match,\n+\t},\n+};\n+\n+module_i2c_driver(allo_cs43130_component_driver);\n+\n+MODULE_DESCRIPTION(\"ASoC Allo Boss2 Codec Driver\");\n+MODULE_AUTHOR(\"Sudeepkumar <sudeepkumar@cem-solutions.net>\");\n+MODULE_LICENSE(\"GPL v2\");\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0391-Add-allo-boss2-overlay.patch",
    "content": "From d05c88f5281ef8d50c984bfca8faf8420c656057 Mon Sep 17 00:00:00 2001\nFrom: Sudeep <sudeepkumar@cem-solutions.net>\nDate: Fri, 23 Oct 2020 15:51:15 +0530\nSubject: [PATCH] Add allo boss2 overlay\n\nSigned-off-by: Sudeep <sudeepkumar@cem-solutions.net>\n---\n arch/arm/boot/dts/overlays/Makefile           |  1 +\n arch/arm/boot/dts/overlays/README             |  6 ++\n .../overlays/allo-boss2-dac-audio-overlay.dts | 57 +++++++++++++++++++\n 3 files changed, 64 insertions(+)\n create mode 100644 arch/arm/boot/dts/overlays/allo-boss2-dac-audio-overlay.dts\n\n--- a/arch/arm/boot/dts/overlays/Makefile\n+++ b/arch/arm/boot/dts/overlays/Makefile\n@@ -14,6 +14,7 @@ dtbo-$(CONFIG_ARCH_BCM2835) += \\\n \tadv728x-m.dtbo \\\n \takkordion-iqdacplus.dtbo \\\n \tallo-boss-dac-pcm512x-audio.dtbo \\\n+\tallo-boss2-dac-audio.dtbo \\\n \tallo-digione.dtbo \\\n \tallo-katana-dac-audio.dtbo \\\n \tallo-piano-dac-pcm512x-audio.dtbo \\\n--- a/arch/arm/boot/dts/overlays/README\n+++ b/arch/arm/boot/dts/overlays/README\n@@ -420,6 +420,12 @@ Params: 24db_digital_gain       Allow ga\n                                 slave\"\n \n \n+Name:   allo-boss2-dac-audio\n+Info:   Configures the Allo Boss2 DAC audio card\n+Load:   dtoverlay=allo-boss2-dac-audio\n+Params: <None>\n+\n+\n Name:   allo-digione\n Info:   Configures the Allo Digione audio card\n Load:   dtoverlay=allo-digione\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/allo-boss2-dac-audio-overlay.dts\n@@ -0,0 +1,57 @@\n+/* * Definitions for Allo Boss2 DAC boards\n+ */\n+\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&i2s>;\n+\t\t__overlay__ {\n+\t\t\t#sound-dai-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\t\t\tcpu_port: port {\n+\t\t\t\tcpu_endpoint: endpoint {\n+\t\t\t\t\tremote-endpoint = <&codec_endpoint>;\n+\t\t\t\t\tbitclock-master = <&codec_endpoint>;\n+\t\t\t\t\tframe-master = <&codec_endpoint>;\n+\t\t\t\t\tdai-format = \"i2s\";\n+\t\t\t\t};\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&i2c1>;\n+\t\t__overlay__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\t\t\tallo-cs43130@30 {\n+\t\t\t\t#sound-dai-cells = <0>;\n+\t\t\t\tcompatible = \"allo,allo-cs43198\";\n+\t\t\t\tclock44-gpio = <&gpio 5 0>;\n+\t\t\t\tclock48-gpio = <&gpio 6 0>;\n+\t\t\t\treg = <0x30>;\n+\t\t\t\tport {\n+\t\t\t\t\tcodec_endpoint: endpoint {\n+\t\t\t\t\tremote-endpoint = <&cpu_endpoint>;\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&sound>;\n+\t\tboss2_dac: __overlay__ {\n+\t\t\tcompatible = \"audio-graph-card\";\n+\t\t\tlabel = \"Allo Boss2\";\n+\t\t\tdais = <&cpu_port>;\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+};\n+\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0392-Overlay-Update-Allo-Piano-Plus-dac-driver-for-5.4.y-.patch",
    "content": "From b26fca3f72b9d79141a0355909602f5194dbd1b3 Mon Sep 17 00:00:00 2001\nFrom: paul-1 <6473457+paul-1@users.noreply.github.com>\nDate: Wed, 4 Nov 2020 19:17:48 -0500\nSubject: [PATCH] Overlay: Update Allo Piano Plus dac driver for 5.4.y\n kernels.\n\nCreate unique names for the two instances of the codec driver.\n\nSigned-off-by: Paul Hermann <paul@picoreplayer.org>\n---\n .../dts/overlays/allo-piano-dac-plus-pcm512x-audio-overlay.dts  | 2 ++\n 1 file changed, 2 insertions(+)\n\n--- a/arch/arm/boot/dts/overlays/allo-piano-dac-plus-pcm512x-audio-overlay.dts\n+++ b/arch/arm/boot/dts/overlays/allo-piano-dac-plus-pcm512x-audio-overlay.dts\n@@ -23,12 +23,14 @@\n \t\t\t\t#sound-dai-cells = <0>;\n \t\t\t\tcompatible = \"ti,pcm5122\";\n \t\t\t\treg = <0x4c>;\n+\t\t\t\tsound-name-prefix = \"Main\";\n \t\t\t\tstatus = \"okay\";\n \t\t\t};\n \t\t\tallo_pcm5122_4d: pcm5122@4d {\n \t\t\t\t#sound-dai-cells = <0>;\n \t\t\t\tcompatible = \"ti,pcm5122\";\n \t\t\t\treg = <0x4d>;\n+\t\t\t\tsound-name-prefix = \"Sub\";\n \t\t\t\tstatus = \"okay\";\n \t\t\t};\n \t\t};\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0393-media-bcm2835-unicam-Correctly-handle-error-propagat.patch",
    "content": "From a9077829ddaaea3366c4ff9be8b98e7c85403a1c Mon Sep 17 00:00:00 2001\nFrom: Naushir Patuck <naush@raspberrypi.com>\nDate: Wed, 2 Dec 2020 15:22:23 +0000\nSubject: [PATCH] media: bcm2835-unicam: Correctly handle error\n propagation for stream on\n\nOn a failure in start_streaming(), the error code would not propagate to\nthe calling function on all conditions. This would cause the userland\ncaller to not know of the failure.\n\nSigned-off-by: Naushir Patuck <naush@raspberrypi.com>\n---\n drivers/media/platform/bcm2835/bcm2835-unicam.c | 3 +--\n 1 file changed, 1 insertion(+), 2 deletions(-)\n\n--- a/drivers/media/platform/bcm2835/bcm2835-unicam.c\n+++ b/drivers/media/platform/bcm2835/bcm2835-unicam.c\n@@ -1730,8 +1730,7 @@ err_disable_unicam:\n \tunicam_disable(dev);\n \tclk_disable_unprepare(dev->clock);\n err_vpu_clock:\n-\tret = clk_set_min_rate(dev->vpu_clock, 0);\n-\tif (ret)\n+\tif (clk_set_min_rate(dev->vpu_clock, 0))\n \t\tunicam_err(dev, \"failed to reset the VPU clock\\n\");\n \tclk_disable_unprepare(dev->vpu_clock);\n err_pm_put:\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0394-media-bcm2835-unicam-Return-early-from-stop_streamin.patch",
    "content": "From a95a3e417cf425d03b3a62c1b34730cfcb21b197 Mon Sep 17 00:00:00 2001\nFrom: Naushir Patuck <naush@raspberrypi.com>\nDate: Wed, 2 Dec 2020 15:26:09 +0000\nSubject: [PATCH] media: bcm2835-unicam: Return early from\n stop_streaming() if stopped\n\nclk_disable_unprepare() is called unconditionally in stop_streaming().\nThis is incorrect in the cases where start_streaming() fails, and\nunprepares all clocks as part of the failure cleanup. To avoid this,\nensure that clk_disable_unprepare() is only called in stop_streaming()\nif the clocks are in a prepared state.\n\nSigned-off-by: Naushir Patuck <naush@raspberrypi.com>\n---\n drivers/media/platform/bcm2835/bcm2835-unicam.c | 16 +++++++++-------\n 1 file changed, 9 insertions(+), 7 deletions(-)\n\n--- a/drivers/media/platform/bcm2835/bcm2835-unicam.c\n+++ b/drivers/media/platform/bcm2835/bcm2835-unicam.c\n@@ -426,6 +426,8 @@ struct unicam_device {\n \tstruct clk *clock;\n \t/* vpu clock handle */\n \tstruct clk *vpu_clock;\n+\t/* clock status for error handling */\n+\tbool clocks_enabled;\n \t/* V4l2 device */\n \tstruct v4l2_device v4l2_dev;\n \tstruct media_device mdev;\n@@ -1724,6 +1726,7 @@ static int unicam_start_streaming(struct\n \t\tgoto err_disable_unicam;\n \t}\n \n+\tdev->clocks_enabled = true;\n \treturn 0;\n \n err_disable_unicam:\n@@ -1750,8 +1753,6 @@ static void unicam_stop_streaming(struct\n \tnode->streaming = false;\n \n \tif (node->pad_id == IMAGE_PAD) {\n-\t\tint ret;\n-\n \t\t/*\n \t\t * Stop streaming the sensor and disable the peripheral.\n \t\t * We cannot continue streaming embedded data with the\n@@ -1762,12 +1763,13 @@ static void unicam_stop_streaming(struct\n \n \t\tunicam_disable(dev);\n \n-\t\tret = clk_set_min_rate(dev->vpu_clock, 0);\n-\t\tif (ret)\n-\t\t\tunicam_err(dev, \"failed to reset the min VPU clock\\n\");\n+\t\tif (dev->clocks_enabled) {\n+\t\t\tif (clk_set_min_rate(dev->vpu_clock, 0))\n+\t\t\t\tunicam_err(dev, \"failed to reset the min VPU clock\\n\");\n \n-\t\tclk_disable_unprepare(dev->vpu_clock);\n-\t\tclk_disable_unprepare(dev->clock);\n+\t\t\tclk_disable_unprepare(dev->vpu_clock);\n+\t\t\tclk_disable_unprepare(dev->clock);\n+\t\t}\n \t\tunicam_runtime_put(dev);\n \n \t} else if (node->pad_id == METADATA_PAD) {\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0395-media-bcm2835-unicam-Clear-clock-state-when-stopping.patch",
    "content": "From 038ee7126dcfe172eefa1ee4c271af51fc9e633c Mon Sep 17 00:00:00 2001\nFrom: Naushir Patuck <naush@raspberrypi.com>\nDate: Wed, 2 Dec 2020 16:48:41 +0000\nSubject: [PATCH] media: bcm2835-unicam: Clear clock state when\n stopping streaming\n\nCommit 65e08c465020d4c5b51afb452efc2246d80fd66f failed to clear the\nclock state when the device stopped streaming. Fix this, as it might\nagain cause the same problems when doing an unprepare.\n\nSigned-off-by: Naushir Patuck <naush@raspberrypi.com>\n---\n drivers/media/platform/bcm2835/bcm2835-unicam.c | 1 +\n 1 file changed, 1 insertion(+)\n\n--- a/drivers/media/platform/bcm2835/bcm2835-unicam.c\n+++ b/drivers/media/platform/bcm2835/bcm2835-unicam.c\n@@ -1769,6 +1769,7 @@ static void unicam_stop_streaming(struct\n \n \t\t\tclk_disable_unprepare(dev->vpu_clock);\n \t\t\tclk_disable_unprepare(dev->clock);\n+\t\t\tdev->clocks_enabled = false;\n \t\t}\n \t\tunicam_runtime_put(dev);\n \n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0396-PCI-brcmstb-Advertise-MSI-X-support.patch",
    "content": "From 9cd85b8b4c18c913ac1d63eb2b6d13e3230516a3 Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.com>\nDate: Thu, 3 Dec 2020 13:44:42 +0000\nSubject: [PATCH] PCI: brcmstb: Advertise MSI-X support\n\nAlthough the BRCMSTB PCIe interface doesn't technically support the\nMSI-X spec, in practise it seems to work provided no more than 32\nMSI-Xs are required. Add the required flag to the driver to allow\nexperimentation with devices that demand MSI-X support.\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.com>\n---\n drivers/pci/controller/pcie-brcmstb.c | 3 ++-\n 1 file changed, 2 insertions(+), 1 deletion(-)\n\n--- a/drivers/pci/controller/pcie-brcmstb.c\n+++ b/drivers/pci/controller/pcie-brcmstb.c\n@@ -463,7 +463,8 @@ static struct irq_chip brcm_msi_irq_chip\n \n static struct msi_domain_info brcm_msi_domain_info = {\n \t/* Multi MSI is supported by the controller, but not by this driver */\n-\t.flags\t= (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS),\n+\t.flags\t= (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |\n+\t\t   MSI_FLAG_PCI_MSIX),\n \t.chip\t= &brcm_msi_irq_chip,\n };\n \n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0397-ARM-dts-CM4-audio-pins-are-not-connected.patch",
    "content": "From 3b2a09e95b28f9fd30bc569135d4e939d3d5eb7f Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.com>\nDate: Mon, 7 Dec 2020 09:35:57 +0000\nSubject: [PATCH] ARM: dts: CM4 audio pins are not connected\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.com>\n---\n arch/arm/boot/dts/bcm2711-rpi-cm4.dts | 2 --\n 1 file changed, 2 deletions(-)\n\n--- a/arch/arm/boot/dts/bcm2711-rpi-cm4.dts\n+++ b/arch/arm/boot/dts/bcm2711-rpi-cm4.dts\n@@ -548,8 +548,6 @@\n \n &gpio {\n \taudio_pins: audio_pins {\n-\t\tbrcm,pins = <40 41>;\n-\t\tbrcm,function = <4>;\n \t};\n };\n \n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0398-overlays-Add-PCF85063-and-PCF85063A-to-i2c-rtc.patch",
    "content": "From ba93a3eeaf4101166feec31b4a2799b6d4aee640 Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.com>\nDate: Mon, 7 Dec 2020 08:49:53 +0000\nSubject: [PATCH] overlays: Add PCF85063 and PCF85063A to i2c-rtc\n\nAdd support for the PCF85063 and PCF85063A RTC devices to the\ni2c-rtc overlay.\n\nAlso enable the device to be used on i2c0 (i2c_vc) on GPIOs 0&1 (use\nparameter \"i2c0\") and GPIOs 44 & 45 (use parameter \"i2c_csi_dsi\").\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.com>\n---\n arch/arm/boot/dts/overlays/README             |  8 ++\n .../arm/boot/dts/overlays/i2c-rtc-overlay.dts | 98 ++++++++++---------\n 2 files changed, 61 insertions(+), 45 deletions(-)\n\n--- a/arch/arm/boot/dts/overlays/README\n+++ b/arch/arm/boot/dts/overlays/README\n@@ -1257,6 +1257,10 @@ Params: abx80x                  Select o\n \n         pcf2129                 Select the PCF2129 device\n \n+        pcf85063                Select the PCF85363 device\n+\n+        pcf85063a               Select the PCF85363A device\n+\n         pcf8523                 Select the PCF8523 device\n \n         pcf85363                Select the PCF85363 device\n@@ -1269,6 +1273,10 @@ Params: abx80x                  Select o\n \n         sd3078                  Select the ZXW Shenzhen whwave SD3078 device\n \n+        i2c0                    Choose the I2C0 bus on GPIOs 0&1\n+\n+        i2c_csi_dsi             Choose the I2C0 bus on GPIOs 44&45\n+\n         addr                    Sets the address for the RTC. Note that the\n                                 device must be configured to use the specified\n                                 address.\n--- a/arch/arm/boot/dts/overlays/i2c-rtc-overlay.dts\n+++ b/arch/arm/boot/dts/overlays/i2c-rtc-overlay.dts\n@@ -6,235 +6,238 @@\n \tcompatible = \"brcm,bcm2835\";\n \n \tfragment@0 {\n-\t\ttarget = <&i2c_arm>;\n+\t\ttarget = <&i2cbus>;\n \t\t__dormant__ {\n \t\t\t#address-cells = <1>;\n \t\t\t#size-cells = <0>;\n-\t\t\tstatus = \"okay\";\n \n \t\t\tabx80x: abx80x@69 {\n \t\t\t\tcompatible = \"abracon,abx80x\";\n \t\t\t\treg = <0x69>;\n \t\t\t\tabracon,tc-diode = \"standard\";\n \t\t\t\tabracon,tc-resistor = <0>;\n-\t\t\t\tstatus = \"okay\";\n \t\t\t};\n \t\t};\n \t};\n \n \tfragment@1 {\n-\t\ttarget = <&i2c_arm>;\n+\t\ttarget = <&i2cbus>;\n \t\t__dormant__ {\n \t\t\t#address-cells = <1>;\n \t\t\t#size-cells = <0>;\n-\t\t\tstatus = \"okay\";\n \n \t\t\tds1307: ds1307@68 {\n \t\t\t\tcompatible = \"dallas,ds1307\";\n \t\t\t\treg = <0x68>;\n-\t\t\t\tstatus = \"okay\";\n \t\t\t};\n \t\t};\n \t};\n \n \tfragment@2 {\n-\t\ttarget = <&i2c_arm>;\n+\t\ttarget = <&i2cbus>;\n \t\t__dormant__ {\n \t\t\t#address-cells = <1>;\n \t\t\t#size-cells = <0>;\n-\t\t\tstatus = \"okay\";\n \n \t\t\tds1339: ds1339@68 {\n \t\t\t\tcompatible = \"dallas,ds1339\";\n \t\t\t\ttrickle-resistor-ohms = <0>;\n \t\t\t\treg = <0x68>;\n-\t\t\t\tstatus = \"okay\";\n \t\t\t};\n \t\t};\n \t};\n \n \tfragment@3 {\n-\t\ttarget = <&i2c_arm>;\n+\t\ttarget = <&i2cbus>;\n \t\t__dormant__ {\n \t\t\t#address-cells = <1>;\n \t\t\t#size-cells = <0>;\n-\t\t\tstatus = \"okay\";\n \n \t\t\tds3231: ds3231@68 {\n \t\t\t\tcompatible = \"maxim,ds3231\";\n \t\t\t\treg = <0x68>;\n-\t\t\t\tstatus = \"okay\";\n \t\t\t};\n \t\t};\n \t};\n \n \tfragment@4 {\n-\t\ttarget = <&i2c_arm>;\n+\t\ttarget = <&i2cbus>;\n \t\t__dormant__ {\n \t\t\t#address-cells = <1>;\n \t\t\t#size-cells = <0>;\n-\t\t\tstatus = \"okay\";\n \n \t\t\tmcp7940x: mcp7940x@6f {\n \t\t\t\tcompatible = \"microchip,mcp7940x\";\n \t\t\t\treg = <0x6f>;\n-\t\t\t\tstatus = \"okay\";\n \t\t\t};\n \t\t};\n \t};\n \n \tfragment@5 {\n-\t\ttarget = <&i2c_arm>;\n+\t\ttarget = <&i2cbus>;\n \t\t__dormant__ {\n \t\t\t#address-cells = <1>;\n \t\t\t#size-cells = <0>;\n-\t\t\tstatus = \"okay\";\n \n \t\t\tmcp7941x: mcp7941x@6f {\n \t\t\t\tcompatible = \"microchip,mcp7941x\";\n \t\t\t\treg = <0x6f>;\n-\t\t\t\tstatus = \"okay\";\n \t\t\t};\n \t\t};\n \t};\n \n \tfragment@6 {\n-\t\ttarget = <&i2c_arm>;\n+\t\ttarget = <&i2cbus>;\n \t\t__dormant__ {\n \t\t\t#address-cells = <1>;\n \t\t\t#size-cells = <0>;\n-\t\t\tstatus = \"okay\";\n \n \t\t\tpcf2127@51 {\n \t\t\t\tcompatible = \"nxp,pcf2127\";\n \t\t\t\treg = <0x51>;\n-\t\t\t\tstatus = \"okay\";\n \t\t\t};\n \t\t};\n \t};\n \n \tfragment@7 {\n-\t\ttarget = <&i2c_arm>;\n+\t\ttarget = <&i2cbus>;\n \t\t__dormant__ {\n \t\t\t#address-cells = <1>;\n \t\t\t#size-cells = <0>;\n-\t\t\tstatus = \"okay\";\n \n \t\t\tpcf8523: pcf8523@68 {\n \t\t\t\tcompatible = \"nxp,pcf8523\";\n \t\t\t\treg = <0x68>;\n-\t\t\t\tstatus = \"okay\";\n \t\t\t};\n \t\t};\n \t};\n \n \tfragment@8 {\n-\t\ttarget = <&i2c_arm>;\n+\t\ttarget = <&i2cbus>;\n \t\t__dormant__ {\n \t\t\t#address-cells = <1>;\n \t\t\t#size-cells = <0>;\n-\t\t\tstatus = \"okay\";\n \n \t\t\tpcf8563: pcf8563@51 {\n \t\t\t\tcompatible = \"nxp,pcf8563\";\n \t\t\t\treg = <0x51>;\n-\t\t\t\tstatus = \"okay\";\n \t\t\t};\n \t\t};\n \t};\n \n \tfragment@9 {\n-\t\ttarget = <&i2c_arm>;\n+\t\ttarget = <&i2cbus>;\n \t\t__dormant__ {\n \t\t\t#address-cells = <1>;\n \t\t\t#size-cells = <0>;\n-\t\t\tstatus = \"okay\";\n \n \t\t\tm41t62: m41t62@68 {\n \t\t\t\tcompatible = \"st,m41t62\";\n \t\t\t\treg = <0x68>;\n-\t\t\t\tstatus = \"okay\";\n \t\t\t};\n \t\t};\n \t};\n \n \tfragment@10 {\n-\t\ttarget = <&i2c_arm>;\n+\t\ttarget = <&i2cbus>;\n \t\t__dormant__ {\n \t\t\t#address-cells = <1>;\n \t\t\t#size-cells = <0>;\n-\t\t\tstatus = \"okay\";\n \n \t\t\trv3028: rv3028@52 {\n \t\t\t\tcompatible = \"microcrystal,rv3028\";\n \t\t\t\treg = <0x52>;\n-\t\t\t\tstatus = \"okay\";\n \t\t\t};\n \t\t};\n \t};\n \n \tfragment@11 {\n-\t\ttarget = <&i2c_arm>;\n+\t\ttarget = <&i2cbus>;\n \t\t__dormant__ {\n \t\t\t#address-cells = <1>;\n \t\t\t#size-cells = <0>;\n-\t\t\tstatus = \"okay\";\n \n \t\t\tpcf2129@51 {\n \t\t\t\tcompatible = \"nxp,pcf2129\";\n \t\t\t\treg = <0x51>;\n-\t\t\t\tstatus = \"okay\";\n \t\t\t};\n \t\t};\n \t};\n \n \tfragment@12 {\n-\t\ttarget = <&i2c_arm>;\n+\t\ttarget = <&i2cbus>;\n \t       __dormant__ {\n \t\t\t#address-cells = <1>;\n \t\t\t#size-cells = <0>;\n-\t\t\tstatus = \"okay\";\n \n \t\t\tpcf85363@51 {\n \t\t\t\tcompatible = \"nxp,pcf85363\";\n \t\t\t\treg = <0x51>;\n-\t\t\t\tstatus = \"okay\";\n \t\t\t};\n \t\t};\n \t};\n \n \tfragment@13 {\n-\t\ttarget = <&i2c_arm>;\n+\t\ttarget = <&i2cbus>;\n \t\t__dormant__ {\n \t\t\t#address-cells = <1>;\n \t\t\t#size-cells = <0>;\n-\t\t\tstatus = \"okay\";\n \n \t\t\trv1805: rv1805@69 {\n \t\t\t\tcompatible = \"microcrystal,rv1805\";\n \t\t\t\treg = <0x69>;\n \t\t\t\tabracon,tc-diode = \"standard\";\n \t\t\t\tabracon,tc-resistor = <0>;\n-\t\t\t\tstatus = \"okay\";\n \t\t\t};\n \t\t};\n \t};\n \n \tfragment@14 {\n-\t\ttarget = <&i2c_arm>;\n+\t\ttarget = <&i2cbus>;\n \t\t__dormant__ {\n \t\t\t#address-cells = <1>;\n \t\t\t#size-cells = <0>;\n-\t\t\tstatus = \"okay\";\n \n \t\t\tsd3078: sd3078@32 {\n \t\t\t\tcompatible = \"whwave,sd3078\";\n \t\t\t\treg = <0x32>;\n-\t\t\t\tstatus = \"okay\";\n \t\t\t};\n \t\t};\n \t};\n \n+\tfragment@15 {\n+\t\ttarget = <&i2cbus>;\n+\t       __dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tpcf85063@51 {\n+\t\t\t\tcompatible = \"nxp,pcf85063\";\n+\t\t\t\treg = <0x51>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@16 {\n+\t\ttarget = <&i2cbus>;\n+\t       __dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tpcf85063a@51 {\n+\t\t\t\tcompatible = \"nxp,pcf85063a\";\n+\t\t\t\treg = <0x51>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfrag100: fragment@100 {\n+\t\ttarget = <&i2c_arm>;\n+\t\ti2cbus: __overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n \t__overrides__ {\n \t\tabx80x = <0>,\"+0\";\n \t\tds1307 = <0>,\"+1\";\n@@ -251,6 +254,11 @@\n \t\tpcf85363 = <0>,\"+12\";\n \t\trv1805 = <0>,\"+13\";\n \t\tsd3078 = <0>,\"+14\";\n+\t\tpcf85063 = <0>,\"+15\";\n+\t\tpcf85063a = <0>,\"+16\";\n+\n+\t\ti2c0 = <&frag100>, \"target:0=\",<&i2c0>;\n+\t\ti2c_csi_dsi = <&frag100>, \"target:0=\",<&i2c_csi_dsi>;\n \n \t\taddr = <&abx80x>, \"reg:0\",\n \t\t       <&ds1307>, \"reg:0\",\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0399-overlays-Fix-cut-and-paste-error-in-README.patch",
    "content": "From 4e88fb586d6b2e062c1bb9613fa9aaf4ee52fe79 Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.com>\nDate: Mon, 7 Dec 2020 17:18:39 +0000\nSubject: [PATCH] overlays: Fix cut-and-paste error in README\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.com>\n---\n arch/arm/boot/dts/overlays/README | 4 ++--\n 1 file changed, 2 insertions(+), 2 deletions(-)\n\n--- a/arch/arm/boot/dts/overlays/README\n+++ b/arch/arm/boot/dts/overlays/README\n@@ -1257,9 +1257,9 @@ Params: abx80x                  Select o\n \n         pcf2129                 Select the PCF2129 device\n \n-        pcf85063                Select the PCF85363 device\n+        pcf85063                Select the PCF85063 device\n \n-        pcf85063a               Select the PCF85363A device\n+        pcf85063a               Select the PCF85063A device\n \n         pcf8523                 Select the PCF8523 device\n \n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0400-staging-bcm2835-codec-Ensure-OUTPUT-timestamps-are-a.patch",
    "content": "From 35e371f270fb14320de11b93cbc0f1e1024ff58c Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Wed, 4 Nov 2020 18:31:02 +0000\nSubject: [PATCH] staging/bcm2835-codec: Ensure OUTPUT timestamps are\n always forwarded\n\nThe firmware by default tries to ensure that decoded frame\ntimestamps always increment. This is counter to the V4L2 API\nwhich wants exactly the OUTPUT queue timestamps passed to the\nCAPTURE queue buffers.\n\nDisable the firmware option.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n .../bcm2835-codec/bcm2835-v4l2-codec.c              | 13 +++++++++++++\n .../vc04_services/vchiq-mmal/mmal-parameters.h      |  3 +++\n 2 files changed, 16 insertions(+)\n\n--- a/drivers/staging/vc04_services/bcm2835-codec/bcm2835-v4l2-codec.c\n+++ b/drivers/staging/vc04_services/bcm2835-codec/bcm2835-v4l2-codec.c\n@@ -2001,6 +2001,19 @@ static int bcm2835_codec_create_componen\n \t\t\t\t      MMAL_PARAMETER_ZERO_COPY, &enable,\n \t\t\t\t      sizeof(enable));\n \n+\tif (dev->role == DECODE) {\n+\t\t/*\n+\t\t * Disable firmware option that ensures decoded timestamps\n+\t\t * always increase.\n+\t\t */\n+\t\tenable = 0;\n+\t\tvchiq_mmal_port_parameter_set(dev->instance,\n+\t\t\t\t\t      &ctx->component->output[0],\n+\t\t\t\t\t      MMAL_PARAMETER_VIDEO_VALIDATE_TIMESTAMPS,\n+\t\t\t\t\t      &enable,\n+\t\t\t\t\t      sizeof(enable));\n+\t}\n+\n \tsetup_mmal_port_format(ctx, &ctx->q_data[V4L2_M2M_SRC],\n \t\t\t       &ctx->component->input[0]);\n \n--- a/drivers/staging/vc04_services/vchiq-mmal/mmal-parameters.h\n+++ b/drivers/staging/vc04_services/vchiq-mmal/mmal-parameters.h\n@@ -674,6 +674,9 @@ enum mmal_parameter_video_type {\n \n \t/**< Take a @ref MMAL_PARAMETER_BOOLEAN_T */\n \tMMAL_PARAMETER_VIDEO_ENCODE_HEADERS_WITH_FRAME,\n+\n+\t/**< Take a @ref MMAL_PARAMETER_BOOLEAN_T */\n+\tMMAL_PARAMETER_VIDEO_VALIDATE_TIMESTAMPS,\n };\n \n /** Valid mirror modes */\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0401-net-lan78xx-Ack-pending-PHY-ints-when-resetting.patch",
    "content": "From 4f060bf5900e8f17fb8cb8508dc08006b2a844b1 Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.com>\nDate: Tue, 15 Dec 2020 16:38:37 +0000\nSubject: [PATCH] net: lan78xx: Ack pending PHY ints when resetting\n\nlan78xx_link_reset explicitly clears the MAC's view of the PHY's IRQ\nstatus. In doing so it potentially leaves the PHY with a pending\ninterrupt that will never be acknowledged, at which point no further\ninterrupts will be generated.\n\nAvoid the problem by acknowledging any pending PHY interrupt after\nclearing the MAC's status bit.\n\nSee: https://github.com/raspberrypi/linux/issues/2937\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.com>\n---\n drivers/net/usb/lan78xx.c | 3 +++\n 1 file changed, 3 insertions(+)\n\n--- a/drivers/net/usb/lan78xx.c\n+++ b/drivers/net/usb/lan78xx.c\n@@ -1183,6 +1183,9 @@ static int lan78xx_link_reset(struct lan\n \tif (unlikely(ret < 0))\n \t\treturn -EIO;\n \n+\t/* Acknowledge any pending PHY interrupt, lest it be the last */\n+\tphy_read(phydev, LAN88XX_INT_STS);\n+\n \tmutex_lock(&phydev->lock);\n \tphy_read_status(phydev);\n \tlink = phydev->link;\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0402-overlays-mpu6050-Add-addr-parameter.patch",
    "content": "From 3e0ea72cab201faea51f8cdb490562151a3f01fd Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.com>\nDate: Tue, 15 Dec 2020 17:02:17 +0000\nSubject: [PATCH] overlays: mpu6050: Add 'addr' parameter\n\nThe mpu6050 starts up at address 0x68 by default, but can be set to\n0x69 if the ADO pin is pulled high. Give the overlay an addr parameter\nto allow devices at the alternate address to be used.\n\nSee: https://github.com/Hexxeh/rpi-firmware/issues/252\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.com>\n---\n arch/arm/boot/dts/overlays/README              | 1 +\n arch/arm/boot/dts/overlays/mpu6050-overlay.dts | 1 +\n 2 files changed, 2 insertions(+)\n\n--- a/arch/arm/boot/dts/overlays/README\n+++ b/arch/arm/boot/dts/overlays/README\n@@ -1920,6 +1920,7 @@ Name:   mpu6050\n Info:   Overlay for i2c connected mpu6050 imu\n Load:   dtoverlay=mpu6050,<param>=<val>\n Params: interrupt               GPIO pin for interrupt (default 4)\n+        addr                    I2C address of the device (default 0x68)\n \n \n Name:   mz61581\n--- a/arch/arm/boot/dts/overlays/mpu6050-overlay.dts\n+++ b/arch/arm/boot/dts/overlays/mpu6050-overlay.dts\n@@ -24,5 +24,6 @@\n \n         __overrides__ {\n                 interrupt = <&mpu6050>,\"interrupts:0\";\n+                addr = <&mpu6050>,\"reg:0\";\n         };\n };\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0403-drm-vc4-Make-normalize_zpos-conditional-on-using-fkm.patch",
    "content": "From a384e2c5d6e72e08e3d183b58ca8697f6665a793 Mon Sep 17 00:00:00 2001\nFrom: Dom Cobley <popcornmix@gmail.com>\nDate: Tue, 15 Dec 2020 16:26:51 +0000\nSubject: [PATCH] drm/vc4: Make normalize_zpos conditional on using\n fkms\n\nEric's view was that there was no point in having zpos\nsupport on vc4 as all the planes had the same functionality.\n\nCan be later squashed into (and fixes):\ndrm/vc4: Add firmware-kms mode\n\nSigned-off-by: Dom Cobley <popcornmix@gmail.com>\n---\n drivers/gpu/drm/vc4/vc4_kms.c | 3 ++-\n 1 file changed, 2 insertions(+), 1 deletion(-)\n\n--- a/drivers/gpu/drm/vc4/vc4_kms.c\n+++ b/drivers/gpu/drm/vc4/vc4_kms.c\n@@ -923,7 +923,8 @@ int vc4_kms_load(struct drm_device *dev)\n \tdev->mode_config.preferred_depth = 24;\n \tdev->mode_config.async_page_flip = true;\n \tdev->mode_config.allow_fb_modifiers = true;\n-\tdev->mode_config.normalize_zpos = true;\n+\tif (vc4->firmware_kms)\n+\t\tdev->mode_config.normalize_zpos = true;\n \n \tret = vc4_ctm_obj_init(vc4);\n \tif (ret)\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0404-overlays-Add-missing-addresses-to-ads1015-ads1115.patch",
    "content": "From f3f0143ace6866e7370e1cec6ff04f0e6ede11dd Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.com>\nDate: Wed, 16 Dec 2020 09:28:17 +0000\nSubject: [PATCH] overlays: Add missing addresses to ads1015/ads1115\n\nThe overlays for the ads1015 and ads1115 I2C ADCs omitted the addresses\nin the main device node names. As well as breaking the conventions for\nI2C devices, this prevents the firmware from renaming them when the\n\"reg\" property is modified, which in turn stops the overlays from being\ninstantiated multiple times.\n\nSee: https://www.raspberrypi.org/forums/viewtopic.php?f=107&t=294465\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.com>\n---\n arch/arm/boot/dts/overlays/ads1015-overlay.dts | 2 +-\n arch/arm/boot/dts/overlays/ads1115-overlay.dts | 2 +-\n 2 files changed, 2 insertions(+), 2 deletions(-)\n\n--- a/arch/arm/boot/dts/overlays/ads1015-overlay.dts\n+++ b/arch/arm/boot/dts/overlays/ads1015-overlay.dts\n@@ -13,7 +13,7 @@\n             #address-cells = <1>;\n             #size-cells = <0>;\n             status = \"okay\";\n-            ads1015: ads1015 {\n+            ads1015: ads1015@48 {\n                 compatible = \"ti,ads1015\";\n                 status = \"okay\";\n                 #address-cells = <1>;\n--- a/arch/arm/boot/dts/overlays/ads1115-overlay.dts\n+++ b/arch/arm/boot/dts/overlays/ads1115-overlay.dts\n@@ -15,7 +15,7 @@\n \t\t\t#size-cells = <0>;\n \t\t\tstatus = \"okay\";\n \n-\t\t\tads1115: ads1115 {\n+\t\t\tads1115: ads1115@48 {\n \t\t\t\tcompatible = \"ti,ads1115\";\n \t\t\t\tstatus = \"okay\";\n \t\t\t\t#address-cells = <1>;\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0405-media-i2c-imx477-Selection-compliance-fixes.patch",
    "content": "From cdbecdb538b1854fd61213c490da8b2ded81b5d8 Mon Sep 17 00:00:00 2001\nFrom: Naushir Patuck <naush@raspberrypi.com>\nDate: Wed, 9 Dec 2020 11:30:12 +0000\nSubject: [PATCH] media: i2c: imx477: Selection compliance fixes\n\nTo comply with the intended usage of the V4L2 selection target when\nused to retrieve a sensor image properties, adjust the rectangles\nreturned by the imx477 driver.\n\nThe top/left crop coordinates of the TGT_CROP rectangle were set to\n(0, 0) instead of (8, 16) which is the offset from the larger physical\npixel array rectangle. This was also a mismatch with the default values\ncrop rectangle value, so this is corrected. Found with v4l2-compliance.\n\nWhile at it, add V4L2_SEL_TGT_CROP_BOUNDS support: CROP_DEFAULT and\nCROP_BOUNDS have the same size as the non-active pixels are not readable\nusing the selection API. Found with v4l2-compliance.\n\nThis commit mirrors 543790f777ba1b3264c168c653db6d415e7c983f done for\nthe imx219 sensor.\n\nSigned-off-by: Naushir Patuck <naush@raspberrypi.com>\n---\n drivers/media/i2c/imx477.c | 17 +++++++++--------\n 1 file changed, 9 insertions(+), 8 deletions(-)\n\n--- a/drivers/media/i2c/imx477.c\n+++ b/drivers/media/i2c/imx477.c\n@@ -900,8 +900,8 @@ static const struct imx477_mode supporte\n \t\t.height = 3040,\n \t\t.line_length_pix = 0x5dc0,\n \t\t.crop = {\n-\t\t\t.left = 0,\n-\t\t\t.top = 0,\n+\t\t\t.left = IMX477_PIXEL_ARRAY_LEFT,\n+\t\t\t.top = IMX477_PIXEL_ARRAY_TOP,\n \t\t\t.width = 4056,\n \t\t\t.height = 3040,\n \t\t},\n@@ -924,8 +924,8 @@ static const struct imx477_mode supporte\n \t\t.height = 1520,\n \t\t.line_length_pix = 0x31c4,\n \t\t.crop = {\n-\t\t\t.left = 0,\n-\t\t\t.top = 0,\n+\t\t\t.left = IMX477_PIXEL_ARRAY_LEFT,\n+\t\t\t.top = IMX477_PIXEL_ARRAY_TOP,\n \t\t\t.width = 4056,\n \t\t\t.height = 3040,\n \t\t},\n@@ -948,8 +948,8 @@ static const struct imx477_mode supporte\n \t\t.height = 1080,\n \t\t.line_length_pix = 0x31c4,\n \t\t.crop = {\n-\t\t\t.left = 0,\n-\t\t\t.top = 440,\n+\t\t\t.left = IMX477_PIXEL_ARRAY_LEFT,\n+\t\t\t.top = IMX477_PIXEL_ARRAY_TOP + 440,\n \t\t\t.width = 4056,\n \t\t\t.height = 2600,\n \t\t},\n@@ -983,8 +983,8 @@ static const struct imx477_mode supporte\n \t\t\t * rectangle once the driver is expanded to represent\n \t\t\t * its processing blocks with multiple subdevs.\n \t\t\t */\n-\t\t\t.left = 4,\n-\t\t\t.top = 0,\n+\t\t\t.left = IMX477_PIXEL_ARRAY_LEFT + 4,\n+\t\t\t.top = IMX477_PIXEL_ARRAY_TOP,\n \t\t\t.width = 4052,\n \t\t\t.height = 3040,\n \t\t},\n@@ -1696,6 +1696,7 @@ static int imx477_get_selection(struct v\n \t\treturn 0;\n \n \tcase V4L2_SEL_TGT_CROP_DEFAULT:\n+\tcase V4L2_SEL_TGT_CROP_BOUNDS:\n \t\tsel->r.left = IMX477_PIXEL_ARRAY_LEFT;\n \t\tsel->r.top = IMX477_PIXEL_ARRAY_TOP;\n \t\tsel->r.width = IMX477_PIXEL_ARRAY_WIDTH;\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0406-staging-vc04_services-codec-Add-support-for-CID-MPEG.patch",
    "content": "From 8c2356e38c9a51356a9f0eacf08f4de6521ad0bd Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Sun, 13 Dec 2020 16:45:58 +0000\nSubject: [PATCH] staging/vc04_services/codec: Add support for CID\n MPEG_HEADER_MODE\n\nControl V4L2_CID_MPEG_VIDEO_HEADER_MODE controls whether the encoder\nis meant to emit the header bytes as a separate packet or with the\nfirst encoded frame.\nAdd support for it.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n .../bcm2835-codec/bcm2835-v4l2-codec.c         | 18 +++++++++++++++++-\n 1 file changed, 17 insertions(+), 1 deletion(-)\n\n--- a/drivers/staging/vc04_services/bcm2835-codec/bcm2835-v4l2-codec.c\n+++ b/drivers/staging/vc04_services/bcm2835-codec/bcm2835-v4l2-codec.c\n@@ -1692,6 +1692,17 @@ static int bcm2835_codec_s_ctrl(struct v\n \t\t\t\t\t\t    sizeof(ctrl->val));\n \t\tbreak;\n \n+\tcase V4L2_CID_MPEG_VIDEO_HEADER_MODE:\n+\t\tif (!ctx->component)\n+\t\t\tbreak;\n+\n+\t\tret = vchiq_mmal_port_parameter_set(ctx->dev->instance,\n+\t\t\t\t\t\t    &ctx->component->output[0],\n+\t\t\t\t\t\t    MMAL_PARAMETER_VIDEO_ENCODE_HEADERS_WITH_FRAME,\n+\t\t\t\t\t\t    &ctrl->val,\n+\t\t\t\t\t\t    sizeof(ctrl->val));\n+\t\tbreak;\n+\n \tcase V4L2_CID_MPEG_VIDEO_H264_I_PERIOD:\n \t\tif (!ctx->component)\n \t\t\tbreak;\n@@ -1963,6 +1974,7 @@ static int bcm2835_codec_set_ctrls(struc\n \tconst u32 control_ids[] = {\n \t\tV4L2_CID_MPEG_VIDEO_BITRATE_MODE,\n \t\tV4L2_CID_MPEG_VIDEO_REPEAT_SEQ_HEADER,\n+\t\tV4L2_CID_MPEG_VIDEO_HEADER_MODE,\n \t\tV4L2_CID_MPEG_VIDEO_H264_I_PERIOD,\n \t\tV4L2_CID_MPEG_VIDEO_H264_LEVEL,\n \t\tV4L2_CID_MPEG_VIDEO_H264_PROFILE,\n@@ -2515,7 +2527,7 @@ static int bcm2835_codec_open(struct fil\n \thdl = &ctx->hdl;\n \tif (dev->role == ENCODE) {\n \t\t/* Encode controls */\n-\t\tv4l2_ctrl_handler_init(hdl, 7);\n+\t\tv4l2_ctrl_handler_init(hdl, 9);\n \n \t\tv4l2_ctrl_new_std_menu(hdl, &bcm2835_codec_ctrl_ops,\n \t\t\t\t       V4L2_CID_MPEG_VIDEO_BITRATE_MODE,\n@@ -2525,6 +2537,10 @@ static int bcm2835_codec_open(struct fil\n \t\t\t\t  V4L2_CID_MPEG_VIDEO_BITRATE,\n \t\t\t\t  25 * 1000, 25 * 1000 * 1000,\n \t\t\t\t  25 * 1000, 10 * 1000 * 1000);\n+\t\tv4l2_ctrl_new_std_menu(hdl, &bcm2835_codec_ctrl_ops,\n+\t\t\t\t       V4L2_CID_MPEG_VIDEO_HEADER_MODE,\n+\t\t\t\t       V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME,\n+\t\t\t\t       0, V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME);\n \t\tv4l2_ctrl_new_std(hdl, &bcm2835_codec_ctrl_ops,\n \t\t\t\t  V4L2_CID_MPEG_VIDEO_REPEAT_SEQ_HEADER,\n \t\t\t\t  0, 1,\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0407-staging-vc04_services-codec-Clear-last-buf-dequeued-.patch",
    "content": "From b35ad716845db394d9850d123d3617653f26a921 Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Sun, 13 Dec 2020 16:54:43 +0000\nSubject: [PATCH] staging/vc04_services/codec: Clear last buf dequeued\n flag on START\n\nIt appears that the V4L2 M2M framework requires the driver to manually\ncall vb2_clear_last_buffer_dequeued on the CAPTURE queue during a\nV4L2_DEC_CMD_START.\nAdd such a call.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n .../staging/vc04_services/bcm2835-codec/bcm2835-v4l2-codec.c | 5 ++++-\n 1 file changed, 4 insertions(+), 1 deletion(-)\n\n--- a/drivers/staging/vc04_services/bcm2835-codec/bcm2835-v4l2-codec.c\n+++ b/drivers/staging/vc04_services/bcm2835-codec/bcm2835-v4l2-codec.c\n@@ -1780,6 +1780,7 @@ static int vidioc_decoder_cmd(struct fil\n {\n \tstruct bcm2835_codec_ctx *ctx = file2ctx(file);\n \tstruct bcm2835_codec_q_data *q_data = &ctx->q_data[V4L2_M2M_SRC];\n+\tstruct vb2_queue *dst_vq;\n \tint ret;\n \n \tv4l2_dbg(2, debug, &ctx->dev->v4l2_dev, \"%s, cmd %u\", __func__,\n@@ -1815,7 +1816,9 @@ static int vidioc_decoder_cmd(struct fil\n \t\tbreak;\n \n \tcase V4L2_DEC_CMD_START:\n-\t\t/* Do we need to do anything here? */\n+\t\tdst_vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx,\n+\t\t\t\t\t V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE);\n+\t\tvb2_clear_last_buffer_dequeued(dst_vq);\n \t\tbreak;\n \n \tdefault:\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0408-drm-atomic-Pass-the-full-state-to-CRTC-atomic-enable.patch",
    "content": "From 41661de0a014d606f6f55dd030a14bc341e677fc Mon Sep 17 00:00:00 2001\nFrom: Maxime Ripard <maxime@cerno.tech>\nDate: Thu, 8 Oct 2020 14:44:08 +0200\nSubject: [PATCH] drm/atomic: Pass the full state to CRTC atomic\n enable/disable\n\nCommit 351f950db4ab28c321a1bd4b92e4bb03e34c4703 upstream.\n\nIf the CRTC driver ever needs to access the full DRM state, it can't do so\nat atomic_enable / atomic_disable time since drm_atomic_helper_swap_state\nwill have cleared the pointer from the struct drm_crtc_state to the struct\ndrm_atomic_state before calling those hooks.\n\nIn order to allow that, let's pass the full DRM state to atomic_enable and\natomic_disable. The conversion was done using the coccinelle script below,\nbuilt tested on all the drivers and actually tested on vc4.\n\nvirtual report\n\n@@\nstruct drm_crtc_helper_funcs *FUNCS;\nidentifier dev, state;\nidentifier crtc, crtc_state;\n@@\n\n disable_outputs(struct drm_device *dev, struct drm_atomic_state *state)\n {\n \t<...\n-\tFUNCS->atomic_disable(crtc, crtc_state);\n+\tFUNCS->atomic_disable(crtc, state);\n \t...>\n }\n\n@@\nstruct drm_crtc_helper_funcs *FUNCS;\nidentifier dev, state;\nidentifier crtc, crtc_state;\n@@\n\n drm_atomic_helper_commit_modeset_enables(struct drm_device *dev, struct drm_atomic_state *state)\n {\n \t<...\n-\tFUNCS->atomic_enable(crtc, crtc_state);\n+\tFUNCS->atomic_enable(crtc, state);\n \t...>\n }\n\n@@\nidentifier crtc, old_state;\n@@\n\n struct drm_crtc_helper_funcs {\n\t...\n-\tvoid (*atomic_enable)(struct drm_crtc *crtc, struct drm_crtc_state *old_state);\n+\tvoid (*atomic_enable)(struct drm_crtc *crtc, struct drm_atomic_state *state);\n\t...\n-\tvoid (*atomic_disable)(struct drm_crtc *crtc, struct drm_crtc_state *old_state);\n+\tvoid (*atomic_disable)(struct drm_crtc *crtc, struct drm_atomic_state *state);\n\t...\n}\n\n@ crtc_atomic_func @\nidentifier helpers;\nidentifier func;\n@@\n\n(\nstatic struct drm_crtc_helper_funcs helpers = {\n\t...,\n\t.atomic_enable = func,\n\t...,\n};\n|\nstatic struct drm_crtc_helper_funcs helpers = {\n\t...,\n\t.atomic_disable = func,\n\t...,\n};\n)\n\n@ ignores_old_state @\nidentifier crtc_atomic_func.func;\nidentifier crtc, old_state;\n@@\n\nvoid func(struct drm_crtc *crtc,\n\t\tstruct drm_crtc_state *old_state)\n{\n\t... when != old_state\n}\n\n@ adds_old_state depends on crtc_atomic_func && !ignores_old_state @\nidentifier crtc_atomic_func.func;\nidentifier crtc, old_state;\n@@\n\nvoid func(struct drm_crtc *crtc, struct drm_crtc_state *old_state)\n{\n+\tstruct drm_crtc_state *old_state = drm_atomic_get_old_crtc_state(state, crtc);\n\t...\n}\n\n@ depends on crtc_atomic_func @\nidentifier crtc_atomic_func.func;\nexpression E;\ntype T;\n@@\n\nvoid func(...)\n{\n\t...\n-\tT state = E;\n+\tT crtc_state = E;\n\t<+...\n-\tstate\n+\tcrtc_state\n\t...+>\n\n}\n\n@ depends on crtc_atomic_func @\nidentifier crtc_atomic_func.func;\ntype T;\n@@\n\nvoid func(...)\n{\n\t...\n-\tT state;\n+\tT crtc_state;\n\t<+...\n-\tstate\n+\tcrtc_state\n\t...+>\n\n}\n\n@ depends on crtc_atomic_func @\nidentifier crtc_atomic_func.func;\nidentifier old_state;\nidentifier crtc;\n@@\n\nvoid func(struct drm_crtc *crtc,\n-\t       struct drm_crtc_state *old_state\n+\t       struct drm_atomic_state *state\n\t       )\n\t\t{ ... }\n\n@ include depends on adds_old_state @\n@@\n\n #include <drm/drm_atomic.h>\n\n@ no_include depends on !include && adds_old_state @\n@@\n\n+ #include <drm/drm_atomic.h>\n  #include <drm/...>\n\nSigned-off-by: Maxime Ripard <maxime@cerno.tech>\nAcked-by: Daniel Vetter <daniel.vetter@ffwll.ch>\nLink: https://patchwork.freedesktop.org/patch/msgid/845aa10ef171fc0ea060495efef142a0c13f7870.1602161031.git-series.maxime@cerno.tech\n---\n drivers/gpu/drm/arc/arcpgu_crtc.c                |  4 ++--\n drivers/gpu/drm/arm/display/komeda/komeda_crtc.c |  8 ++++++--\n drivers/gpu/drm/arm/hdlcd_crtc.c                 |  4 ++--\n drivers/gpu/drm/arm/malidp_crtc.c                |  6 ++++--\n drivers/gpu/drm/armada/armada_crtc.c             |  8 ++++++--\n drivers/gpu/drm/ast/ast_mode.c                   |  6 ++++--\n drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c   |  4 ++--\n drivers/gpu/drm/drm_atomic_helper.c              |  4 ++--\n drivers/gpu/drm/drm_simple_kms_helper.c          |  4 ++--\n drivers/gpu/drm/exynos/exynos_drm_crtc.c         |  4 ++--\n drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c       |  6 ++++--\n drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c   |  4 ++--\n drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c  |  4 ++--\n drivers/gpu/drm/imx/dcss/dcss-crtc.c             |  9 +++++++--\n drivers/gpu/drm/imx/ipuv3-crtc.c                 |  6 ++++--\n drivers/gpu/drm/ingenic/ingenic-drm-drv.c        |  4 ++--\n drivers/gpu/drm/mediatek/mtk_drm_crtc.c          |  4 ++--\n drivers/gpu/drm/meson/meson_crtc.c               |  8 ++++----\n drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c         |  7 +++++--\n drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c        |  4 ++--\n drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c        |  4 ++--\n drivers/gpu/drm/mxsfb/mxsfb_kms.c                |  4 ++--\n drivers/gpu/drm/omapdrm/omap_crtc.c              |  4 ++--\n drivers/gpu/drm/qxl/qxl_display.c                |  4 ++--\n drivers/gpu/drm/rcar-du/rcar_du_crtc.c           |  6 ++++--\n drivers/gpu/drm/rockchip/rockchip_drm_vop.c      |  6 ++++--\n drivers/gpu/drm/sti/sti_crtc.c                   |  4 ++--\n drivers/gpu/drm/stm/ltdc.c                       |  4 ++--\n drivers/gpu/drm/sun4i/sun4i_crtc.c               |  4 ++--\n drivers/gpu/drm/tegra/dc.c                       |  8 ++++----\n drivers/gpu/drm/tidss/tidss_crtc.c               |  6 ++++--\n drivers/gpu/drm/tilcdc/tilcdc_crtc.c             |  4 ++--\n drivers/gpu/drm/vboxvideo/vbox_mode.c            |  4 ++--\n drivers/gpu/drm/vc4/vc4_crtc.c                   |  8 ++++++--\n drivers/gpu/drm/vc4/vc4_txp.c                    |  9 +++++++--\n drivers/gpu/drm/virtio/virtgpu_display.c         |  4 ++--\n drivers/gpu/drm/vkms/vkms_crtc.c                 |  4 ++--\n drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c              |  4 ++--\n drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c             |  4 ++--\n drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c             |  4 ++--\n drivers/gpu/drm/xlnx/zynqmp_disp.c               |  6 ++++--\n drivers/gpu/drm/zte/zx_vou.c                     |  4 ++--\n include/drm/drm_modeset_helper_vtables.h         | 13 ++-----------\n 43 files changed, 131 insertions(+), 99 deletions(-)\n\n--- a/drivers/gpu/drm/arc/arcpgu_crtc.c\n+++ b/drivers/gpu/drm/arc/arcpgu_crtc.c\n@@ -116,7 +116,7 @@ static void arc_pgu_crtc_mode_set_nofb(s\n }\n \n static void arc_pgu_crtc_atomic_enable(struct drm_crtc *crtc,\n-\t\t\t\t       struct drm_crtc_state *old_state)\n+\t\t\t\t       struct drm_atomic_state *state)\n {\n \tstruct arcpgu_drm_private *arcpgu = crtc_to_arcpgu_priv(crtc);\n \n@@ -127,7 +127,7 @@ static void arc_pgu_crtc_atomic_enable(s\n }\n \n static void arc_pgu_crtc_atomic_disable(struct drm_crtc *crtc,\n-\t\t\t\t\tstruct drm_crtc_state *old_state)\n+\t\t\t\t\tstruct drm_atomic_state *state)\n {\n \tstruct arcpgu_drm_private *arcpgu = crtc_to_arcpgu_priv(crtc);\n \n--- a/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c\n+++ b/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c\n@@ -273,8 +273,10 @@ komeda_crtc_do_flush(struct drm_crtc *cr\n \n static void\n komeda_crtc_atomic_enable(struct drm_crtc *crtc,\n-\t\t\t  struct drm_crtc_state *old)\n+\t\t\t  struct drm_atomic_state *state)\n {\n+\tstruct drm_crtc_state *old = drm_atomic_get_old_crtc_state(state,\n+\t\t\t\t\t\t\t\t   crtc);\n \tpm_runtime_get_sync(crtc->dev->dev);\n \tkomeda_crtc_prepare(to_kcrtc(crtc));\n \tdrm_crtc_vblank_on(crtc);\n@@ -319,8 +321,10 @@ komeda_crtc_flush_and_wait_for_flip_done\n \n static void\n komeda_crtc_atomic_disable(struct drm_crtc *crtc,\n-\t\t\t   struct drm_crtc_state *old)\n+\t\t\t   struct drm_atomic_state *state)\n {\n+\tstruct drm_crtc_state *old = drm_atomic_get_old_crtc_state(state,\n+\t\t\t\t\t\t\t\t   crtc);\n \tstruct komeda_crtc *kcrtc = to_kcrtc(crtc);\n \tstruct komeda_crtc_state *old_st = to_kcrtc_st(old);\n \tstruct komeda_pipeline *master = kcrtc->master;\n--- a/drivers/gpu/drm/arm/hdlcd_crtc.c\n+++ b/drivers/gpu/drm/arm/hdlcd_crtc.c\n@@ -168,7 +168,7 @@ static void hdlcd_crtc_mode_set_nofb(str\n }\n \n static void hdlcd_crtc_atomic_enable(struct drm_crtc *crtc,\n-\t\t\t\t     struct drm_crtc_state *old_state)\n+\t\t\t\t     struct drm_atomic_state *state)\n {\n \tstruct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);\n \n@@ -179,7 +179,7 @@ static void hdlcd_crtc_atomic_enable(str\n }\n \n static void hdlcd_crtc_atomic_disable(struct drm_crtc *crtc,\n-\t\t\t\t      struct drm_crtc_state *old_state)\n+\t\t\t\t      struct drm_atomic_state *state)\n {\n \tstruct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);\n \n--- a/drivers/gpu/drm/arm/malidp_crtc.c\n+++ b/drivers/gpu/drm/arm/malidp_crtc.c\n@@ -46,7 +46,7 @@ static enum drm_mode_status malidp_crtc_\n }\n \n static void malidp_crtc_atomic_enable(struct drm_crtc *crtc,\n-\t\t\t\t      struct drm_crtc_state *old_state)\n+\t\t\t\t      struct drm_atomic_state *state)\n {\n \tstruct malidp_drm *malidp = crtc_to_malidp_device(crtc);\n \tstruct malidp_hw_device *hwdev = malidp->dev;\n@@ -70,8 +70,10 @@ static void malidp_crtc_atomic_enable(st\n }\n \n static void malidp_crtc_atomic_disable(struct drm_crtc *crtc,\n-\t\t\t\t       struct drm_crtc_state *old_state)\n+\t\t\t\t       struct drm_atomic_state *state)\n {\n+\tstruct drm_crtc_state *old_state = drm_atomic_get_old_crtc_state(state,\n+\t\t\t\t\t\t\t\t\t crtc);\n \tstruct malidp_drm *malidp = crtc_to_malidp_device(crtc);\n \tstruct malidp_hw_device *hwdev = malidp->dev;\n \tint err;\n--- a/drivers/gpu/drm/armada/armada_crtc.c\n+++ b/drivers/gpu/drm/armada/armada_crtc.c\n@@ -467,8 +467,10 @@ static void armada_drm_crtc_atomic_flush\n }\n \n static void armada_drm_crtc_atomic_disable(struct drm_crtc *crtc,\n-\t\t\t\t\t   struct drm_crtc_state *old_state)\n+\t\t\t\t\t   struct drm_atomic_state *state)\n {\n+\tstruct drm_crtc_state *old_state = drm_atomic_get_old_crtc_state(state,\n+\t\t\t\t\t\t\t\t\t crtc);\n \tstruct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);\n \tstruct drm_pending_vblank_event *event;\n \n@@ -503,8 +505,10 @@ static void armada_drm_crtc_atomic_disab\n }\n \n static void armada_drm_crtc_atomic_enable(struct drm_crtc *crtc,\n-\t\t\t\t\t  struct drm_crtc_state *old_state)\n+\t\t\t\t\t  struct drm_atomic_state *state)\n {\n+\tstruct drm_crtc_state *old_state = drm_atomic_get_old_crtc_state(state,\n+\t\t\t\t\t\t\t\t\t crtc);\n \tstruct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);\n \n \tDRM_DEBUG_KMS(\"[CRTC:%d:%s]\\n\", crtc->base.id, crtc->name);\n--- a/drivers/gpu/drm/ast/ast_mode.c\n+++ b/drivers/gpu/drm/ast/ast_mode.c\n@@ -793,7 +793,7 @@ ast_crtc_helper_atomic_flush(struct drm_\n \n static void\n ast_crtc_helper_atomic_enable(struct drm_crtc *crtc,\n-\t\t\t      struct drm_crtc_state *old_crtc_state)\n+\t\t\t      struct drm_atomic_state *state)\n {\n \tstruct drm_device *dev = crtc->dev;\n \tstruct ast_private *ast = to_ast_private(dev);\n@@ -816,8 +816,10 @@ ast_crtc_helper_atomic_enable(struct drm\n \n static void\n ast_crtc_helper_atomic_disable(struct drm_crtc *crtc,\n-\t\t\t       struct drm_crtc_state *old_crtc_state)\n+\t\t\t       struct drm_atomic_state *state)\n {\n+\tstruct drm_crtc_state *old_crtc_state = drm_atomic_get_old_crtc_state(state,\n+\t\t\t\t\t\t\t\t\t      crtc);\n \tstruct drm_device *dev = crtc->dev;\n \tstruct ast_private *ast = to_ast_private(dev);\n \n--- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c\n+++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c\n@@ -165,7 +165,7 @@ atmel_hlcdc_crtc_mode_valid(struct drm_c\n }\n \n static void atmel_hlcdc_crtc_atomic_disable(struct drm_crtc *c,\n-\t\t\t\t\t    struct drm_crtc_state *old_state)\n+\t\t\t\t\t    struct drm_atomic_state *state)\n {\n \tstruct drm_device *dev = c->dev;\n \tstruct atmel_hlcdc_crtc *crtc = drm_crtc_to_atmel_hlcdc_crtc(c);\n@@ -200,7 +200,7 @@ static void atmel_hlcdc_crtc_atomic_disa\n }\n \n static void atmel_hlcdc_crtc_atomic_enable(struct drm_crtc *c,\n-\t\t\t\t\t   struct drm_crtc_state *old_state)\n+\t\t\t\t\t   struct drm_atomic_state *state)\n {\n \tstruct drm_device *dev = c->dev;\n \tstruct atmel_hlcdc_crtc *crtc = drm_crtc_to_atmel_hlcdc_crtc(c);\n--- a/drivers/gpu/drm/drm_atomic_helper.c\n+++ b/drivers/gpu/drm/drm_atomic_helper.c\n@@ -1093,7 +1093,7 @@ disable_outputs(struct drm_device *dev,\n \t\tif (new_crtc_state->enable && funcs->prepare)\n \t\t\tfuncs->prepare(crtc);\n \t\telse if (funcs->atomic_disable)\n-\t\t\tfuncs->atomic_disable(crtc, old_crtc_state);\n+\t\t\tfuncs->atomic_disable(crtc, old_state);\n \t\telse if (funcs->disable)\n \t\t\tfuncs->disable(crtc);\n \t\telse if (funcs->dpms)\n@@ -1358,7 +1358,7 @@ void drm_atomic_helper_commit_modeset_en\n \t\t\tDRM_DEBUG_ATOMIC(\"enabling [CRTC:%d:%s]\\n\",\n \t\t\t\t\t crtc->base.id, crtc->name);\n \t\t\tif (funcs->atomic_enable)\n-\t\t\t\tfuncs->atomic_enable(crtc, old_crtc_state);\n+\t\t\t\tfuncs->atomic_enable(crtc, old_state);\n \t\t\telse if (funcs->commit)\n \t\t\t\tfuncs->commit(crtc);\n \t\t}\n--- a/drivers/gpu/drm/drm_simple_kms_helper.c\n+++ b/drivers/gpu/drm/drm_simple_kms_helper.c\n@@ -99,7 +99,7 @@ static int drm_simple_kms_crtc_check(str\n }\n \n static void drm_simple_kms_crtc_enable(struct drm_crtc *crtc,\n-\t\t\t\t       struct drm_crtc_state *old_state)\n+\t\t\t\t       struct drm_atomic_state *state)\n {\n \tstruct drm_plane *plane;\n \tstruct drm_simple_display_pipe *pipe;\n@@ -113,7 +113,7 @@ static void drm_simple_kms_crtc_enable(s\n }\n \n static void drm_simple_kms_crtc_disable(struct drm_crtc *crtc,\n-\t\t\t\t\tstruct drm_crtc_state *old_state)\n+\t\t\t\t\tstruct drm_atomic_state *state)\n {\n \tstruct drm_simple_display_pipe *pipe;\n \n--- a/drivers/gpu/drm/exynos/exynos_drm_crtc.c\n+++ b/drivers/gpu/drm/exynos/exynos_drm_crtc.c\n@@ -19,7 +19,7 @@\n #include \"exynos_drm_plane.h\"\n \n static void exynos_drm_crtc_atomic_enable(struct drm_crtc *crtc,\n-\t\t\t\t\t  struct drm_crtc_state *old_state)\n+\t\t\t\t\t  struct drm_atomic_state *state)\n {\n \tstruct exynos_drm_crtc *exynos_crtc = to_exynos_crtc(crtc);\n \n@@ -30,7 +30,7 @@ static void exynos_drm_crtc_atomic_enabl\n }\n \n static void exynos_drm_crtc_atomic_disable(struct drm_crtc *crtc,\n-\t\t\t\t\t   struct drm_crtc_state *old_state)\n+\t\t\t\t\t   struct drm_atomic_state *state)\n {\n \tstruct exynos_drm_crtc *exynos_crtc = to_exynos_crtc(crtc);\n \n--- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c\n+++ b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c\n@@ -43,8 +43,10 @@ static void fsl_dcu_drm_crtc_atomic_flus\n }\n \n static void fsl_dcu_drm_crtc_atomic_disable(struct drm_crtc *crtc,\n-\t\t\t\t\tstruct drm_crtc_state *old_crtc_state)\n+\t\t\t\t\tstruct drm_atomic_state *state)\n {\n+\tstruct drm_crtc_state *old_crtc_state = drm_atomic_get_old_crtc_state(state,\n+\t\t\t\t\t\t\t\t\t      crtc);\n \tstruct drm_device *dev = crtc->dev;\n \tstruct fsl_dcu_drm_device *fsl_dev = dev->dev_private;\n \n@@ -62,7 +64,7 @@ static void fsl_dcu_drm_crtc_atomic_disa\n }\n \n static void fsl_dcu_drm_crtc_atomic_enable(struct drm_crtc *crtc,\n-\t\t\t\t\t   struct drm_crtc_state *old_state)\n+\t\t\t\t\t   struct drm_atomic_state *state)\n {\n \tstruct drm_device *dev = crtc->dev;\n \tstruct fsl_dcu_drm_device *fsl_dev = dev->dev_private;\n--- a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c\n+++ b/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c\n@@ -172,7 +172,7 @@ static void hibmc_crtc_dpms(struct drm_c\n }\n \n static void hibmc_crtc_atomic_enable(struct drm_crtc *crtc,\n-\t\t\t\t     struct drm_crtc_state *old_state)\n+\t\t\t\t     struct drm_atomic_state *state)\n {\n \tunsigned int reg;\n \tstruct hibmc_drm_private *priv = crtc->dev->dev_private;\n@@ -191,7 +191,7 @@ static void hibmc_crtc_atomic_enable(str\n }\n \n static void hibmc_crtc_atomic_disable(struct drm_crtc *crtc,\n-\t\t\t\t      struct drm_crtc_state *old_state)\n+\t\t\t\t      struct drm_atomic_state *state)\n {\n \tunsigned int reg;\n \tstruct hibmc_drm_private *priv = crtc->dev->dev_private;\n--- a/drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c\n+++ b/drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c\n@@ -436,7 +436,7 @@ static void ade_dump_regs(void __iomem *\n #endif\n \n static void ade_crtc_atomic_enable(struct drm_crtc *crtc,\n-\t\t\t\t   struct drm_crtc_state *old_state)\n+\t\t\t\t   struct drm_atomic_state *state)\n {\n \tstruct kirin_crtc *kcrtc = to_kirin_crtc(crtc);\n \tstruct ade_hw_ctx *ctx = kcrtc->hw_ctx;\n@@ -459,7 +459,7 @@ static void ade_crtc_atomic_enable(struc\n }\n \n static void ade_crtc_atomic_disable(struct drm_crtc *crtc,\n-\t\t\t\t    struct drm_crtc_state *old_state)\n+\t\t\t\t    struct drm_atomic_state *state)\n {\n \tstruct kirin_crtc *kcrtc = to_kirin_crtc(crtc);\n \tstruct ade_hw_ctx *ctx = kcrtc->hw_ctx;\n--- a/drivers/gpu/drm/imx/dcss/dcss-crtc.c\n+++ b/drivers/gpu/drm/imx/dcss/dcss-crtc.c\n@@ -3,6 +3,7 @@\n  * Copyright 2019 NXP.\n  */\n \n+#include <drm/drm_atomic.h>\n #include <drm/drm_atomic_helper.h>\n #include <drm/drm_vblank.h>\n #include <linux/platform_device.h>\n@@ -77,8 +78,10 @@ static void dcss_crtc_atomic_flush(struc\n }\n \n static void dcss_crtc_atomic_enable(struct drm_crtc *crtc,\n-\t\t\t\t    struct drm_crtc_state *old_crtc_state)\n+\t\t\t\t    struct drm_atomic_state *state)\n {\n+\tstruct drm_crtc_state *old_crtc_state = drm_atomic_get_old_crtc_state(state,\n+\t\t\t\t\t\t\t\t\t      crtc);\n \tstruct dcss_crtc *dcss_crtc = container_of(crtc, struct dcss_crtc,\n \t\t\t\t\t\t   base);\n \tstruct dcss_dev *dcss = dcss_crtc->base.dev->dev_private;\n@@ -111,8 +114,10 @@ static void dcss_crtc_atomic_enable(stru\n }\n \n static void dcss_crtc_atomic_disable(struct drm_crtc *crtc,\n-\t\t\t\t     struct drm_crtc_state *old_crtc_state)\n+\t\t\t\t     struct drm_atomic_state *state)\n {\n+\tstruct drm_crtc_state *old_crtc_state = drm_atomic_get_old_crtc_state(state,\n+\t\t\t\t\t\t\t\t\t      crtc);\n \tstruct dcss_crtc *dcss_crtc = container_of(crtc, struct dcss_crtc,\n \t\t\t\t\t\t   base);\n \tstruct dcss_dev *dcss = dcss_crtc->base.dev->dev_private;\n--- a/drivers/gpu/drm/imx/ipuv3-crtc.c\n+++ b/drivers/gpu/drm/imx/ipuv3-crtc.c\n@@ -47,7 +47,7 @@ static inline struct ipu_crtc *to_ipu_cr\n }\n \n static void ipu_crtc_atomic_enable(struct drm_crtc *crtc,\n-\t\t\t\t   struct drm_crtc_state *old_state)\n+\t\t\t\t   struct drm_atomic_state *state)\n {\n \tstruct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);\n \tstruct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);\n@@ -79,8 +79,10 @@ static void ipu_crtc_disable_planes(stru\n }\n \n static void ipu_crtc_atomic_disable(struct drm_crtc *crtc,\n-\t\t\t\t    struct drm_crtc_state *old_crtc_state)\n+\t\t\t\t    struct drm_atomic_state *state)\n {\n+\tstruct drm_crtc_state *old_crtc_state = drm_atomic_get_old_crtc_state(state,\n+\t\t\t\t\t\t\t\t\t      crtc);\n \tstruct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);\n \tstruct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);\n \n--- a/drivers/gpu/drm/ingenic/ingenic-drm-drv.c\n+++ b/drivers/gpu/drm/ingenic/ingenic-drm-drv.c\n@@ -112,7 +112,7 @@ static inline struct ingenic_drm *drm_cr\n }\n \n static void ingenic_drm_crtc_atomic_enable(struct drm_crtc *crtc,\n-\t\t\t\t\t   struct drm_crtc_state *state)\n+\t\t\t\t\t   struct drm_atomic_state *state)\n {\n \tstruct ingenic_drm *priv = drm_crtc_get_priv(crtc);\n \n@@ -126,7 +126,7 @@ static void ingenic_drm_crtc_atomic_enab\n }\n \n static void ingenic_drm_crtc_atomic_disable(struct drm_crtc *crtc,\n-\t\t\t\t\t    struct drm_crtc_state *state)\n+\t\t\t\t\t    struct drm_atomic_state *state)\n {\n \tstruct ingenic_drm *priv = drm_crtc_get_priv(crtc);\n \tunsigned int var;\n--- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c\n+++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c\n@@ -517,7 +517,7 @@ void mtk_drm_crtc_async_update(struct dr\n }\n \n static void mtk_drm_crtc_atomic_enable(struct drm_crtc *crtc,\n-\t\t\t\t       struct drm_crtc_state *old_state)\n+\t\t\t\t       struct drm_atomic_state *state)\n {\n \tstruct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);\n \tstruct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];\n@@ -542,7 +542,7 @@ static void mtk_drm_crtc_atomic_enable(s\n }\n \n static void mtk_drm_crtc_atomic_disable(struct drm_crtc *crtc,\n-\t\t\t\t\tstruct drm_crtc_state *old_state)\n+\t\t\t\t\tstruct drm_atomic_state *state)\n {\n \tstruct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);\n \tstruct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];\n--- a/drivers/gpu/drm/meson/meson_crtc.c\n+++ b/drivers/gpu/drm/meson/meson_crtc.c\n@@ -82,7 +82,7 @@ static const struct drm_crtc_funcs meson\n };\n \n static void meson_g12a_crtc_atomic_enable(struct drm_crtc *crtc,\n-\t\t\t\t\t  struct drm_crtc_state *old_state)\n+\t\t\t\t\t  struct drm_atomic_state *state)\n {\n \tstruct meson_crtc *meson_crtc = to_meson_crtc(crtc);\n \tstruct drm_crtc_state *crtc_state = crtc->state;\n@@ -118,7 +118,7 @@ static void meson_g12a_crtc_atomic_enabl\n }\n \n static void meson_crtc_atomic_enable(struct drm_crtc *crtc,\n-\t\t\t\t     struct drm_crtc_state *old_state)\n+\t\t\t\t     struct drm_atomic_state *state)\n {\n \tstruct meson_crtc *meson_crtc = to_meson_crtc(crtc);\n \tstruct drm_crtc_state *crtc_state = crtc->state;\n@@ -146,7 +146,7 @@ static void meson_crtc_atomic_enable(str\n }\n \n static void meson_g12a_crtc_atomic_disable(struct drm_crtc *crtc,\n-\t\t\t\t\t   struct drm_crtc_state *old_state)\n+\t\t\t\t\t   struct drm_atomic_state *state)\n {\n \tstruct meson_crtc *meson_crtc = to_meson_crtc(crtc);\n \tstruct meson_drm *priv = meson_crtc->priv;\n@@ -171,7 +171,7 @@ static void meson_g12a_crtc_atomic_disab\n }\n \n static void meson_crtc_atomic_disable(struct drm_crtc *crtc,\n-\t\t\t\t      struct drm_crtc_state *old_state)\n+\t\t\t\t      struct drm_atomic_state *state)\n {\n \tstruct meson_crtc *meson_crtc = to_meson_crtc(crtc);\n \tstruct meson_drm *priv = meson_crtc->priv;\n--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c\n+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c\n@@ -11,6 +11,7 @@\n #include <linux/ktime.h>\n #include <linux/bits.h>\n \n+#include <drm/drm_atomic.h>\n #include <drm/drm_crtc.h>\n #include <drm/drm_flip_work.h>\n #include <drm/drm_mode.h>\n@@ -706,10 +707,12 @@ static struct drm_crtc_state *dpu_crtc_d\n }\n \n static void dpu_crtc_disable(struct drm_crtc *crtc,\n-\t\t\t     struct drm_crtc_state *old_crtc_state)\n+\t\t\t     struct drm_atomic_state *state)\n {\n \tstruct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);\n \tstruct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc->state);\n+\tstruct drm_crtc_state *old_crtc_state = drm_atomic_get_old_crtc_state(state,\n+\t\t\t\t\t\t\t\t\t      crtc);\n \tstruct drm_encoder *encoder;\n \tunsigned long flags;\n \tbool release_bandwidth = false;\n@@ -770,7 +773,7 @@ static void dpu_crtc_disable(struct drm_\n }\n \n static void dpu_crtc_enable(struct drm_crtc *crtc,\n-\t\tstruct drm_crtc_state *old_crtc_state)\n+\t\tstruct drm_atomic_state *state)\n {\n \tstruct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);\n \tstruct drm_encoder *encoder;\n--- a/drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c\n+++ b/drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c\n@@ -264,7 +264,7 @@ static void mdp4_crtc_mode_set_nofb(stru\n }\n \n static void mdp4_crtc_atomic_disable(struct drm_crtc *crtc,\n-\t\t\t\t     struct drm_crtc_state *old_state)\n+\t\t\t\t     struct drm_atomic_state *state)\n {\n \tstruct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);\n \tstruct mdp4_kms *mdp4_kms = get_kms(crtc);\n@@ -284,7 +284,7 @@ static void mdp4_crtc_atomic_disable(str\n }\n \n static void mdp4_crtc_atomic_enable(struct drm_crtc *crtc,\n-\t\t\t\t    struct drm_crtc_state *old_state)\n+\t\t\t\t    struct drm_atomic_state *state)\n {\n \tstruct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);\n \tstruct mdp4_kms *mdp4_kms = get_kms(crtc);\n--- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c\n+++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c\n@@ -483,7 +483,7 @@ static u32 mdp5_crtc_get_vblank_counter(\n }\n \n static void mdp5_crtc_atomic_disable(struct drm_crtc *crtc,\n-\t\t\t\t     struct drm_crtc_state *old_state)\n+\t\t\t\t     struct drm_atomic_state *state)\n {\n \tstruct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);\n \tstruct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);\n@@ -529,7 +529,7 @@ static void mdp5_crtc_vblank_on(struct d\n }\n \n static void mdp5_crtc_atomic_enable(struct drm_crtc *crtc,\n-\t\t\t\t    struct drm_crtc_state *old_state)\n+\t\t\t\t    struct drm_atomic_state *state)\n {\n \tstruct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);\n \tstruct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);\n--- a/drivers/gpu/drm/mxsfb/mxsfb_kms.c\n+++ b/drivers/gpu/drm/mxsfb/mxsfb_kms.c\n@@ -343,7 +343,7 @@ static void mxsfb_crtc_atomic_flush(stru\n }\n \n static void mxsfb_crtc_atomic_enable(struct drm_crtc *crtc,\n-\t\t\t\t     struct drm_crtc_state *old_state)\n+\t\t\t\t     struct drm_atomic_state *state)\n {\n \tstruct mxsfb_drm_private *mxsfb = to_mxsfb_drm_private(crtc->dev);\n \tstruct drm_device *drm = mxsfb->drm;\n@@ -367,7 +367,7 @@ static void mxsfb_crtc_atomic_enable(str\n }\n \n static void mxsfb_crtc_atomic_disable(struct drm_crtc *crtc,\n-\t\t\t\t      struct drm_crtc_state *old_state)\n+\t\t\t\t      struct drm_atomic_state *state)\n {\n \tstruct mxsfb_drm_private *mxsfb = to_mxsfb_drm_private(crtc->dev);\n \tstruct drm_device *drm = mxsfb->drm;\n--- a/drivers/gpu/drm/omapdrm/omap_crtc.c\n+++ b/drivers/gpu/drm/omapdrm/omap_crtc.c\n@@ -436,7 +436,7 @@ static void omap_crtc_arm_event(struct d\n }\n \n static void omap_crtc_atomic_enable(struct drm_crtc *crtc,\n-\t\t\t\t    struct drm_crtc_state *old_state)\n+\t\t\t\t    struct drm_atomic_state *state)\n {\n \tstruct omap_drm_private *priv = crtc->dev->dev_private;\n \tstruct omap_crtc *omap_crtc = to_omap_crtc(crtc);\n@@ -462,7 +462,7 @@ static void omap_crtc_atomic_enable(stru\n }\n \n static void omap_crtc_atomic_disable(struct drm_crtc *crtc,\n-\t\t\t\t     struct drm_crtc_state *old_state)\n+\t\t\t\t     struct drm_atomic_state *state)\n {\n \tstruct omap_drm_private *priv = crtc->dev->dev_private;\n \tstruct omap_crtc *omap_crtc = to_omap_crtc(crtc);\n--- a/drivers/gpu/drm/qxl/qxl_display.c\n+++ b/drivers/gpu/drm/qxl/qxl_display.c\n@@ -445,13 +445,13 @@ static const struct drm_framebuffer_func\n };\n \n static void qxl_crtc_atomic_enable(struct drm_crtc *crtc,\n-\t\t\t\t   struct drm_crtc_state *old_state)\n+\t\t\t\t   struct drm_atomic_state *state)\n {\n \tqxl_crtc_update_monitors_config(crtc, \"enable\");\n }\n \n static void qxl_crtc_atomic_disable(struct drm_crtc *crtc,\n-\t\t\t\t    struct drm_crtc_state *old_state)\n+\t\t\t\t    struct drm_atomic_state *state)\n {\n \tqxl_crtc_update_monitors_config(crtc, \"disable\");\n }\n--- a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c\n+++ b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c\n@@ -716,7 +716,7 @@ static int rcar_du_crtc_atomic_check(str\n }\n \n static void rcar_du_crtc_atomic_enable(struct drm_crtc *crtc,\n-\t\t\t\t       struct drm_crtc_state *old_state)\n+\t\t\t\t       struct drm_atomic_state *state)\n {\n \tstruct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);\n \tstruct rcar_du_crtc_state *rstate = to_rcar_crtc_state(crtc->state);\n@@ -751,8 +751,10 @@ static void rcar_du_crtc_atomic_enable(s\n }\n \n static void rcar_du_crtc_atomic_disable(struct drm_crtc *crtc,\n-\t\t\t\t\tstruct drm_crtc_state *old_state)\n+\t\t\t\t\tstruct drm_atomic_state *state)\n {\n+\tstruct drm_crtc_state *old_state = drm_atomic_get_old_crtc_state(state,\n+\t\t\t\t\t\t\t\t\t crtc);\n \tstruct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);\n \tstruct rcar_du_crtc_state *rstate = to_rcar_crtc_state(old_state);\n \tstruct rcar_du_device *rcdu = rcrtc->dev;\n--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c\n+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c\n@@ -693,7 +693,7 @@ static void rockchip_drm_set_win_enabled\n }\n \n static void vop_crtc_atomic_disable(struct drm_crtc *crtc,\n-\t\t\t\t    struct drm_crtc_state *old_state)\n+\t\t\t\t    struct drm_atomic_state *state)\n {\n \tstruct vop *vop = to_vop(crtc);\n \n@@ -1261,8 +1261,10 @@ static void vop_crtc_atomic_begin(struct\n }\n \n static void vop_crtc_atomic_enable(struct drm_crtc *crtc,\n-\t\t\t\t   struct drm_crtc_state *old_state)\n+\t\t\t\t   struct drm_atomic_state *state)\n {\n+\tstruct drm_crtc_state *old_state = drm_atomic_get_old_crtc_state(state,\n+\t\t\t\t\t\t\t\t\t crtc);\n \tstruct vop *vop = to_vop(crtc);\n \tconst struct vop_data *vop_data = vop->data;\n \tstruct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);\n--- a/drivers/gpu/drm/sti/sti_crtc.c\n+++ b/drivers/gpu/drm/sti/sti_crtc.c\n@@ -23,7 +23,7 @@\n #include \"sti_vtg.h\"\n \n static void sti_crtc_atomic_enable(struct drm_crtc *crtc,\n-\t\t\t\t   struct drm_crtc_state *old_state)\n+\t\t\t\t   struct drm_atomic_state *state)\n {\n \tstruct sti_mixer *mixer = to_sti_mixer(crtc);\n \n@@ -35,7 +35,7 @@ static void sti_crtc_atomic_enable(struc\n }\n \n static void sti_crtc_atomic_disable(struct drm_crtc *crtc,\n-\t\t\t\t    struct drm_crtc_state *old_state)\n+\t\t\t\t    struct drm_atomic_state *state)\n {\n \tstruct sti_mixer *mixer = to_sti_mixer(crtc);\n \n--- a/drivers/gpu/drm/stm/ltdc.c\n+++ b/drivers/gpu/drm/stm/ltdc.c\n@@ -420,7 +420,7 @@ static void ltdc_crtc_update_clut(struct\n }\n \n static void ltdc_crtc_atomic_enable(struct drm_crtc *crtc,\n-\t\t\t\t    struct drm_crtc_state *old_state)\n+\t\t\t\t    struct drm_atomic_state *state)\n {\n \tstruct ltdc_device *ldev = crtc_to_ltdc(crtc);\n \tstruct drm_device *ddev = crtc->dev;\n@@ -442,7 +442,7 @@ static void ltdc_crtc_atomic_enable(stru\n }\n \n static void ltdc_crtc_atomic_disable(struct drm_crtc *crtc,\n-\t\t\t\t     struct drm_crtc_state *old_state)\n+\t\t\t\t     struct drm_atomic_state *state)\n {\n \tstruct ltdc_device *ldev = crtc_to_ltdc(crtc);\n \tstruct drm_device *ddev = crtc->dev;\n--- a/drivers/gpu/drm/sun4i/sun4i_crtc.c\n+++ b/drivers/gpu/drm/sun4i/sun4i_crtc.c\n@@ -101,7 +101,7 @@ static void sun4i_crtc_atomic_flush(stru\n }\n \n static void sun4i_crtc_atomic_disable(struct drm_crtc *crtc,\n-\t\t\t\t      struct drm_crtc_state *old_state)\n+\t\t\t\t      struct drm_atomic_state *state)\n {\n \tstruct drm_encoder *encoder = sun4i_crtc_get_encoder(crtc);\n \tstruct sun4i_crtc *scrtc = drm_crtc_to_sun4i_crtc(crtc);\n@@ -122,7 +122,7 @@ static void sun4i_crtc_atomic_disable(st\n }\n \n static void sun4i_crtc_atomic_enable(struct drm_crtc *crtc,\n-\t\t\t\t     struct drm_crtc_state *old_state)\n+\t\t\t\t     struct drm_atomic_state *state)\n {\n \tstruct drm_encoder *encoder = sun4i_crtc_get_encoder(crtc);\n \tstruct sun4i_crtc *scrtc = drm_crtc_to_sun4i_crtc(crtc);\n--- a/drivers/gpu/drm/tegra/dc.c\n+++ b/drivers/gpu/drm/tegra/dc.c\n@@ -1748,7 +1748,7 @@ static int tegra_dc_wait_idle(struct teg\n }\n \n static void tegra_crtc_atomic_disable(struct drm_crtc *crtc,\n-\t\t\t\t      struct drm_crtc_state *old_state)\n+\t\t\t\t      struct drm_atomic_state *state)\n {\n \tstruct tegra_dc *dc = to_tegra_dc(crtc);\n \tu32 value;\n@@ -1805,10 +1805,10 @@ static void tegra_crtc_atomic_disable(st\n }\n \n static void tegra_crtc_atomic_enable(struct drm_crtc *crtc,\n-\t\t\t\t     struct drm_crtc_state *old_state)\n+\t\t\t\t     struct drm_atomic_state *state)\n {\n \tstruct drm_display_mode *mode = &crtc->state->adjusted_mode;\n-\tstruct tegra_dc_state *state = to_dc_state(crtc->state);\n+\tstruct tegra_dc_state *crtc_state = to_dc_state(crtc->state);\n \tstruct tegra_dc *dc = to_tegra_dc(crtc);\n \tu32 value;\n \tint err;\n@@ -1888,7 +1888,7 @@ static void tegra_crtc_atomic_enable(str\n \t\ttegra_dc_writel(dc, 0, DC_DISP_BORDER_COLOR);\n \n \t/* apply PLL and pixel clock changes */\n-\ttegra_dc_commit_state(dc, state);\n+\ttegra_dc_commit_state(dc, crtc_state);\n \n \t/* program display mode */\n \ttegra_dc_set_timings(dc, mode);\n--- a/drivers/gpu/drm/tidss/tidss_crtc.c\n+++ b/drivers/gpu/drm/tidss/tidss_crtc.c\n@@ -212,8 +212,10 @@ static void tidss_crtc_atomic_flush(stru\n }\n \n static void tidss_crtc_atomic_enable(struct drm_crtc *crtc,\n-\t\t\t\t     struct drm_crtc_state *old_state)\n+\t\t\t\t     struct drm_atomic_state *state)\n {\n+\tstruct drm_crtc_state *old_state = drm_atomic_get_old_crtc_state(state,\n+\t\t\t\t\t\t\t\t\t crtc);\n \tstruct tidss_crtc *tcrtc = to_tidss_crtc(crtc);\n \tstruct drm_device *ddev = crtc->dev;\n \tstruct tidss_device *tidss = to_tidss(ddev);\n@@ -255,7 +257,7 @@ static void tidss_crtc_atomic_enable(str\n }\n \n static void tidss_crtc_atomic_disable(struct drm_crtc *crtc,\n-\t\t\t\t      struct drm_crtc_state *old_state)\n+\t\t\t\t      struct drm_atomic_state *state)\n {\n \tstruct tidss_crtc *tcrtc = to_tidss_crtc(crtc);\n \tstruct drm_device *ddev = crtc->dev;\n--- a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c\n+++ b/drivers/gpu/drm/tilcdc/tilcdc_crtc.c\n@@ -484,7 +484,7 @@ static void tilcdc_crtc_enable(struct dr\n }\n \n static void tilcdc_crtc_atomic_enable(struct drm_crtc *crtc,\n-\t\t\t\t      struct drm_crtc_state *old_state)\n+\t\t\t\t      struct drm_atomic_state *state)\n {\n \ttilcdc_crtc_enable(crtc);\n }\n@@ -541,7 +541,7 @@ static void tilcdc_crtc_disable(struct d\n }\n \n static void tilcdc_crtc_atomic_disable(struct drm_crtc *crtc,\n-\t\t\t\t       struct drm_crtc_state *old_state)\n+\t\t\t\t       struct drm_atomic_state *state)\n {\n \ttilcdc_crtc_disable(crtc);\n }\n--- a/drivers/gpu/drm/vboxvideo/vbox_mode.c\n+++ b/drivers/gpu/drm/vboxvideo/vbox_mode.c\n@@ -213,12 +213,12 @@ static void vbox_crtc_set_base_and_mode(\n }\n \n static void vbox_crtc_atomic_enable(struct drm_crtc *crtc,\n-\t\t\t\t    struct drm_crtc_state *old_crtc_state)\n+\t\t\t\t    struct drm_atomic_state *state)\n {\n }\n \n static void vbox_crtc_atomic_disable(struct drm_crtc *crtc,\n-\t\t\t\t     struct drm_crtc_state *old_crtc_state)\n+\t\t\t\t     struct drm_atomic_state *state)\n {\n }\n \n--- a/drivers/gpu/drm/vc4/vc4_crtc.c\n+++ b/drivers/gpu/drm/vc4/vc4_crtc.c\n@@ -489,8 +489,10 @@ int vc4_crtc_disable_at_boot(struct drm_\n }\n \n static void vc4_crtc_atomic_disable(struct drm_crtc *crtc,\n-\t\t\t\t    struct drm_crtc_state *old_state)\n+\t\t\t\t    struct drm_atomic_state *state)\n {\n+\tstruct drm_crtc_state *old_state = drm_atomic_get_old_crtc_state(state,\n+\t\t\t\t\t\t\t\t\t crtc);\n \tstruct vc4_crtc_state *old_vc4_state = to_vc4_crtc_state(old_state);\n \tstruct drm_device *dev = crtc->dev;\n \n@@ -516,8 +518,10 @@ static void vc4_crtc_atomic_disable(stru\n }\n \n static void vc4_crtc_atomic_enable(struct drm_crtc *crtc,\n-\t\t\t\t   struct drm_crtc_state *old_state)\n+\t\t\t\t   struct drm_atomic_state *state)\n {\n+\tstruct drm_crtc_state *old_state = drm_atomic_get_old_crtc_state(state,\n+\t\t\t\t\t\t\t\t\t crtc);\n \tstruct drm_device *dev = crtc->dev;\n \tstruct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);\n \tstruct drm_encoder *encoder = vc4_get_crtc_encoder(crtc);\n--- a/drivers/gpu/drm/vc4/vc4_txp.c\n+++ b/drivers/gpu/drm/vc4/vc4_txp.c\n@@ -13,6 +13,7 @@\n #include <linux/of_platform.h>\n #include <linux/pm_runtime.h>\n \n+#include <drm/drm_atomic.h>\n #include <drm/drm_atomic_helper.h>\n #include <drm/drm_edid.h>\n #include <drm/drm_fb_cma_helper.h>\n@@ -401,15 +402,19 @@ static int vc4_txp_atomic_check(struct d\n }\n \n static void vc4_txp_atomic_enable(struct drm_crtc *crtc,\n-\t\t\t\t  struct drm_crtc_state *old_state)\n+\t\t\t\t  struct drm_atomic_state *state)\n {\n+\tstruct drm_crtc_state *old_state = drm_atomic_get_old_crtc_state(state,\n+\t\t\t\t\t\t\t\t\t crtc);\n \tdrm_crtc_vblank_on(crtc);\n \tvc4_hvs_atomic_enable(crtc, old_state);\n }\n \n static void vc4_txp_atomic_disable(struct drm_crtc *crtc,\n-\t\t\t\t   struct drm_crtc_state *old_state)\n+\t\t\t\t   struct drm_atomic_state *state)\n {\n+\tstruct drm_crtc_state *old_state = drm_atomic_get_old_crtc_state(state,\n+\t\t\t\t\t\t\t\t\t crtc);\n \tstruct drm_device *dev = crtc->dev;\n \n \t/* Disable vblank irq handling before crtc is disabled. */\n--- a/drivers/gpu/drm/virtio/virtgpu_display.c\n+++ b/drivers/gpu/drm/virtio/virtgpu_display.c\n@@ -95,12 +95,12 @@ static void virtio_gpu_crtc_mode_set_nof\n }\n \n static void virtio_gpu_crtc_atomic_enable(struct drm_crtc *crtc,\n-\t\t\t\t\t  struct drm_crtc_state *old_state)\n+\t\t\t\t\t  struct drm_atomic_state *state)\n {\n }\n \n static void virtio_gpu_crtc_atomic_disable(struct drm_crtc *crtc,\n-\t\t\t\t\t   struct drm_crtc_state *old_state)\n+\t\t\t\t\t   struct drm_atomic_state *state)\n {\n \tstruct drm_device *dev = crtc->dev;\n \tstruct virtio_gpu_device *vgdev = dev->dev_private;\n--- a/drivers/gpu/drm/vkms/vkms_crtc.c\n+++ b/drivers/gpu/drm/vkms/vkms_crtc.c\n@@ -215,13 +215,13 @@ static int vkms_crtc_atomic_check(struct\n }\n \n static void vkms_crtc_atomic_enable(struct drm_crtc *crtc,\n-\t\t\t\t    struct drm_crtc_state *old_state)\n+\t\t\t\t    struct drm_atomic_state *state)\n {\n \tdrm_crtc_vblank_on(crtc);\n }\n \n static void vkms_crtc_atomic_disable(struct drm_crtc *crtc,\n-\t\t\t\t     struct drm_crtc_state *old_state)\n+\t\t\t\t     struct drm_atomic_state *state)\n {\n \tdrm_crtc_vblank_off(crtc);\n }\n--- a/drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c\n+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c\n@@ -214,7 +214,7 @@ static void vmw_ldu_crtc_mode_set_nofb(s\n  * CRTC, it makes more sense to do those at plane update time.\n  */\n static void vmw_ldu_crtc_atomic_enable(struct drm_crtc *crtc,\n-\t\t\t\t       struct drm_crtc_state *old_state)\n+\t\t\t\t       struct drm_atomic_state *state)\n {\n }\n \n@@ -224,7 +224,7 @@ static void vmw_ldu_crtc_atomic_enable(s\n  * @crtc: CRTC to be turned off\n  */\n static void vmw_ldu_crtc_atomic_disable(struct drm_crtc *crtc,\n-\t\t\t\t\tstruct drm_crtc_state *old_state)\n+\t\t\t\t\tstruct drm_atomic_state *state)\n {\n }\n \n--- a/drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c\n+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c\n@@ -279,7 +279,7 @@ static void vmw_sou_crtc_helper_prepare(\n  * This is called after a mode set has been completed.\n  */\n static void vmw_sou_crtc_atomic_enable(struct drm_crtc *crtc,\n-\t\t\t\t       struct drm_crtc_state *old_state)\n+\t\t\t\t       struct drm_atomic_state *state)\n {\n }\n \n@@ -289,7 +289,7 @@ static void vmw_sou_crtc_atomic_enable(s\n  * @crtc: CRTC to be turned off\n  */\n static void vmw_sou_crtc_atomic_disable(struct drm_crtc *crtc,\n-\t\t\t\t\tstruct drm_crtc_state *old_state)\n+\t\t\t\t\tstruct drm_atomic_state *state)\n {\n \tstruct vmw_private *dev_priv;\n \tstruct vmw_screen_object_unit *sou;\n--- a/drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c\n+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c\n@@ -408,12 +408,12 @@ static void vmw_stdu_crtc_helper_prepare\n }\n \n static void vmw_stdu_crtc_atomic_enable(struct drm_crtc *crtc,\n-\t\t\t\t\tstruct drm_crtc_state *old_state)\n+\t\t\t\t\tstruct drm_atomic_state *state)\n {\n }\n \n static void vmw_stdu_crtc_atomic_disable(struct drm_crtc *crtc,\n-\t\t\t\t\t struct drm_crtc_state *old_state)\n+\t\t\t\t\t struct drm_atomic_state *state)\n {\n \tstruct vmw_private *dev_priv;\n \tstruct vmw_screen_target_display_unit *stdu;\n--- a/drivers/gpu/drm/xlnx/zynqmp_disp.c\n+++ b/drivers/gpu/drm/xlnx/zynqmp_disp.c\n@@ -1441,7 +1441,7 @@ static int zynqmp_disp_crtc_setup_clock(\n \n static void\n zynqmp_disp_crtc_atomic_enable(struct drm_crtc *crtc,\n-\t\t\t       struct drm_crtc_state *old_crtc_state)\n+\t\t\t       struct drm_atomic_state *state)\n {\n \tstruct zynqmp_disp *disp = crtc_to_disp(crtc);\n \tstruct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;\n@@ -1473,8 +1473,10 @@ zynqmp_disp_crtc_atomic_enable(struct dr\n \n static void\n zynqmp_disp_crtc_atomic_disable(struct drm_crtc *crtc,\n-\t\t\t\tstruct drm_crtc_state *old_crtc_state)\n+\t\t\t\tstruct drm_atomic_state *state)\n {\n+\tstruct drm_crtc_state *old_crtc_state = drm_atomic_get_old_crtc_state(state,\n+\t\t\t\t\t\t\t\t\t      crtc);\n \tstruct zynqmp_disp *disp = crtc_to_disp(crtc);\n \tstruct drm_plane_state *old_plane_state;\n \n--- a/drivers/gpu/drm/zte/zx_vou.c\n+++ b/drivers/gpu/drm/zte/zx_vou.c\n@@ -350,7 +350,7 @@ static inline void vou_chn_set_update(st\n }\n \n static void zx_crtc_atomic_enable(struct drm_crtc *crtc,\n-\t\t\t\t  struct drm_crtc_state *old_state)\n+\t\t\t\t  struct drm_atomic_state *state)\n {\n \tstruct drm_display_mode *mode = &crtc->state->adjusted_mode;\n \tbool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;\n@@ -455,7 +455,7 @@ static void zx_crtc_atomic_enable(struct\n }\n \n static void zx_crtc_atomic_disable(struct drm_crtc *crtc,\n-\t\t\t\t   struct drm_crtc_state *old_state)\n+\t\t\t\t   struct drm_atomic_state *state)\n {\n \tstruct zx_crtc *zcrtc = to_zx_crtc(crtc);\n \tconst struct zx_crtc_bits *bits = zcrtc->bits;\n--- a/include/drm/drm_modeset_helper_vtables.h\n+++ b/include/drm/drm_modeset_helper_vtables.h\n@@ -417,14 +417,10 @@ struct drm_crtc_helper_funcs {\n \t * @atomic_enable must be the inverse of @atomic_disable for atomic\n \t * drivers.\n \t *\n-\t * Drivers can use the @old_crtc_state input parameter if the operations\n-\t * needed to enable the CRTC don't depend solely on the new state but\n-\t * also on the transition between the old state and the new state.\n-\t *\n \t * This function is optional.\n \t */\n \tvoid (*atomic_enable)(struct drm_crtc *crtc,\n-\t\t\t      struct drm_crtc_state *old_crtc_state);\n+\t\t\t      struct drm_atomic_state *state);\n \n \t/**\n \t * @atomic_disable:\n@@ -441,15 +437,10 @@ struct drm_crtc_helper_funcs {\n \t * need to implement it if there's no need to disable anything at the\n \t * CRTC level.\n \t *\n-\t * Comparing to @disable, this one provides the additional input\n-\t * parameter @old_crtc_state which could be used to access the old\n-\t * state. Atomic drivers should consider to use this one instead\n-\t * of @disable.\n-\t *\n \t * This function is optional.\n \t */\n \tvoid (*atomic_disable)(struct drm_crtc *crtc,\n-\t\t\t       struct drm_crtc_state *old_crtc_state);\n+\t\t\t       struct drm_atomic_state *state);\n \n \t/**\n \t * @get_scanout_position:\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0409-drm-atomic-Pass-the-full-state-to-CRTC-atomic_check.patch",
    "content": "From 27a4cd3c9986626cc731282e2e4887121f72f5f7 Mon Sep 17 00:00:00 2001\nFrom: Maxime Ripard <maxime@cerno.tech>\nDate: Wed, 28 Oct 2020 13:32:21 +0100\nSubject: [PATCH] drm/atomic: Pass the full state to CRTC atomic_check\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nCommit 29b77ad7b9ca8c87152a1a9e8188970fb2a93df4 upstream.\n\nThe current atomic helpers have either their object state being passed as\nan argument or the full atomic state.\n\nThe former is the pattern that was done at first, before switching to the\nlatter for new hooks or when it was needed.\n\nLet's start convert all the remaining helpers to provide a consistent\ninterface, starting with the CRTC's atomic_check.\n\nThe conversion was done using the coccinelle script below,\nbuilt tested on all the drivers and actually tested on vc4.\n\nvirtual report\n\n@@\nstruct drm_crtc_helper_funcs *FUNCS;\nstruct drm_crtc *crtc;\nstruct drm_crtc_state *crtc_state;\nidentifier dev, state;\nidentifier ret, f;\n@@\n\n f(struct drm_device *dev, struct drm_atomic_state *state)\n {\n\t<...\n-\tret = FUNCS->atomic_check(crtc, crtc_state);\n+\tret = FUNCS->atomic_check(crtc, state);\n\t...>\n }\n\n@@\nidentifier crtc, new_state;\n@@\n\n struct drm_crtc_helper_funcs {\n \t...\n-\tint (*atomic_check)(struct drm_crtc *crtc, struct drm_crtc_state *new_state);\n+\tint (*atomic_check)(struct drm_crtc *crtc, struct drm_atomic_state *state);\n \t...\n}\n\n@ crtc_atomic_func @\nidentifier helpers;\nidentifier func;\n@@\n\nstatic struct drm_crtc_helper_funcs helpers = {\n\t...,\n\t.atomic_check = func,\n\t...,\n};\n\n@ ignores_new_state @\nidentifier crtc_atomic_func.func;\nidentifier crtc, new_state;\n@@\n\n int func(struct drm_crtc *crtc,\n\t\tstruct drm_crtc_state *new_state)\n {\n\t... when != new_state\n }\n\n@ adds_new_state depends on crtc_atomic_func && !ignores_new_state @\nidentifier crtc_atomic_func.func;\nidentifier crtc, new_state;\n@@\n\n int func(struct drm_crtc *crtc, struct drm_crtc_state *new_state)\n {\n+\tstruct drm_crtc_state *new_state = drm_atomic_get_new_crtc_state(state, crtc);\n \t...\n }\n\n@ depends on crtc_atomic_func @\nidentifier crtc_atomic_func.func;\nexpression E;\ntype T;\n@@\n\n int func(...)\n {\n\t...\n-\tT state = E;\n+\tT crtc_state = E;\n \t<+...\n-\tstate\n+\tcrtc_state\n \t...+>\n }\n\n@ depends on crtc_atomic_func @\nidentifier crtc_atomic_func.func;\ntype T;\n@@\n\n int func(...)\n {\n \t...\n-\tT state;\n+\tT crtc_state;\n \t<+...\n-\tstate\n+\tcrtc_state\n \t...+>\n }\n\n@ depends on crtc_atomic_func @\nidentifier crtc_atomic_func.func;\nidentifier new_state;\nidentifier crtc;\n@@\n\n int func(struct drm_crtc *crtc,\n-\t       struct drm_crtc_state *new_state\n+\t       struct drm_atomic_state *state\n\t       )\n { ... }\n\n@@\nidentifier new_state;\nidentifier crtc;\n@@\n\n int vmw_du_crtc_atomic_check(struct drm_crtc *crtc,\n-                             struct drm_crtc_state *new_state\n+                             struct drm_atomic_state *state\n               )\n {\n+       struct drm_crtc_state *new_state = drm_atomic_get_new_crtc_state(state, crtc);\n\t...\n }\n\n@@\nidentifier new_state;\nidentifier crtc;\n@@\n\n int vmw_du_crtc_atomic_check(struct drm_crtc *crtc,\n-                             struct drm_crtc_state *new_state\n+                             struct drm_atomic_state *state\n               );\n\n@ include depends on adds_new_state @\n@@\n\n #include <drm/drm_atomic.h>\n\n@ no_include depends on !include && adds_new_state @\n@@\n\n+ #include <drm/drm_atomic.h>\n  #include <drm/...>\n\nSigned-off-by: Maxime Ripard <maxime@cerno.tech>\nReviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>\nAcked-by: Thomas Zimmermann <tzimmermann@suse.de>\nLink: https://patchwork.freedesktop.org/patch/msgid/20201028123222.1732139-1-maxime@cerno.tech\n---\n .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 14 ++++++-----\n .../gpu/drm/arm/display/komeda/komeda_crtc.c  | 10 ++++----\n drivers/gpu/drm/arm/malidp_crtc.c             | 20 ++++++++--------\n drivers/gpu/drm/armada/armada_crtc.c          | 10 ++++----\n drivers/gpu/drm/ast/ast_mode.c                | 12 ++++++----\n .../gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c    |  3 ++-\n drivers/gpu/drm/drm_atomic_helper.c           |  2 +-\n drivers/gpu/drm/drm_simple_kms_helper.c       | 10 ++++----\n drivers/gpu/drm/exynos/exynos_drm_crtc.c      |  8 ++++---\n drivers/gpu/drm/imx/ipuv3-crtc.c              |  6 +++--\n drivers/gpu/drm/ingenic/ingenic-drm-drv.c     | 15 ++++++++----\n drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c      | 23 +++++++++++--------\n drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c     |  2 +-\n drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c     | 13 +++++++----\n drivers/gpu/drm/mxsfb/mxsfb_kms.c             | 10 ++++----\n drivers/gpu/drm/nouveau/dispnv50/head.c       |  7 ++++--\n drivers/gpu/drm/omapdrm/omap_crtc.c           | 13 +++++++----\n drivers/gpu/drm/rcar-du/rcar_du_crtc.c        | 11 +++++----\n drivers/gpu/drm/rockchip/rockchip_drm_vop.c   |  4 +++-\n drivers/gpu/drm/sun4i/sun4i_crtc.c            |  7 ++++--\n drivers/gpu/drm/tidss/tidss_crtc.c            | 10 ++++----\n drivers/gpu/drm/tilcdc/tilcdc_crtc.c          | 12 ++++++----\n drivers/gpu/drm/vc4/vc4_crtc.c                | 11 +++++----\n drivers/gpu/drm/vc4/vc4_txp.c                 | 10 ++++----\n drivers/gpu/drm/virtio/virtgpu_display.c      |  2 +-\n drivers/gpu/drm/vkms/vkms_crtc.c              | 16 +++++++------\n drivers/gpu/drm/vmwgfx/vmwgfx_kms.c           |  4 +++-\n drivers/gpu/drm/vmwgfx/vmwgfx_kms.h           |  2 +-\n drivers/gpu/drm/xlnx/zynqmp_disp.c            |  6 +++--\n include/drm/drm_modeset_helper_vtables.h      |  5 ++--\n 30 files changed, 168 insertions(+), 110 deletions(-)\n\n--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c\n+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c\n@@ -5606,17 +5606,19 @@ static void dm_update_crtc_active_planes\n }\n \n static int dm_crtc_helper_atomic_check(struct drm_crtc *crtc,\n-\t\t\t\t       struct drm_crtc_state *state)\n+\t\t\t\t       struct drm_atomic_state *state)\n {\n+\tstruct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,\n+\t\t\t\t\t\t\t\t\t  crtc);\n \tstruct amdgpu_device *adev = drm_to_adev(crtc->dev);\n \tstruct dc *dc = adev->dm.dc;\n-\tstruct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(state);\n+\tstruct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);\n \tint ret = -EINVAL;\n \n-\tdm_update_crtc_active_planes(crtc, state);\n+\tdm_update_crtc_active_planes(crtc, crtc_state);\n \n \tif (unlikely(!dm_crtc_state->stream &&\n-\t\t     modeset_required(state, NULL, dm_crtc_state->stream))) {\n+\t\t     modeset_required(crtc_state, NULL, dm_crtc_state->stream))) {\n \t\tWARN_ON(1);\n \t\treturn ret;\n \t}\n@@ -5627,8 +5629,8 @@ static int dm_crtc_helper_atomic_check(s\n \t * planes are disabled, which is not supported by the hardware. And there is legacy\n \t * userspace which stops using the HW cursor altogether in response to the resulting EINVAL.\n \t */\n-\tif (state->enable &&\n-\t    !(state->plane_mask & drm_plane_mask(crtc->primary)))\n+\tif (crtc_state->enable &&\n+\t    !(crtc_state->plane_mask & drm_plane_mask(crtc->primary)))\n \t\treturn -EINVAL;\n \n \t/* In some use cases, like reset, no stream is attached */\n--- a/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c\n+++ b/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c\n@@ -74,16 +74,18 @@ static void komeda_crtc_update_clock_rat\n  */\n static int\n komeda_crtc_atomic_check(struct drm_crtc *crtc,\n-\t\t\t struct drm_crtc_state *state)\n+\t\t\t struct drm_atomic_state *state)\n {\n+\tstruct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,\n+\t\t\t\t\t\t\t\t\t  crtc);\n \tstruct komeda_crtc *kcrtc = to_kcrtc(crtc);\n-\tstruct komeda_crtc_state *kcrtc_st = to_kcrtc_st(state);\n+\tstruct komeda_crtc_state *kcrtc_st = to_kcrtc_st(crtc_state);\n \tint err;\n \n-\tif (drm_atomic_crtc_needs_modeset(state))\n+\tif (drm_atomic_crtc_needs_modeset(crtc_state))\n \t\tkomeda_crtc_update_clock_ratio(kcrtc_st);\n \n-\tif (state->active) {\n+\tif (crtc_state->active) {\n \t\terr = komeda_build_display_data_flow(kcrtc, kcrtc_st);\n \t\tif (err)\n \t\t\treturn err;\n--- a/drivers/gpu/drm/arm/malidp_crtc.c\n+++ b/drivers/gpu/drm/arm/malidp_crtc.c\n@@ -337,8 +337,10 @@ mclk_calc:\n }\n \n static int malidp_crtc_atomic_check(struct drm_crtc *crtc,\n-\t\t\t\t    struct drm_crtc_state *state)\n+\t\t\t\t    struct drm_atomic_state *state)\n {\n+\tstruct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,\n+\t\t\t\t\t\t\t\t\t  crtc);\n \tstruct malidp_drm *malidp = crtc_to_malidp_device(crtc);\n \tstruct malidp_hw_device *hwdev = malidp->dev;\n \tstruct drm_plane *plane;\n@@ -373,7 +375,7 @@ static int malidp_crtc_atomic_check(stru\n \t */\n \n \t/* first count the number of rotated planes */\n-\tdrm_atomic_crtc_state_for_each_plane_state(plane, pstate, state) {\n+\tdrm_atomic_crtc_state_for_each_plane_state(plane, pstate, crtc_state) {\n \t\tstruct drm_framebuffer *fb = pstate->fb;\n \n \t\tif ((pstate->rotation & MALIDP_ROTATED_MASK) || fb->modifier)\n@@ -389,7 +391,7 @@ static int malidp_crtc_atomic_check(stru\n \t\trot_mem_free += hwdev->rotation_memory[1];\n \n \t/* now validate the rotation memory requirements */\n-\tdrm_atomic_crtc_state_for_each_plane_state(plane, pstate, state) {\n+\tdrm_atomic_crtc_state_for_each_plane_state(plane, pstate, crtc_state) {\n \t\tstruct malidp_plane *mp = to_malidp_plane(plane);\n \t\tstruct malidp_plane_state *ms = to_malidp_plane_state(pstate);\n \t\tstruct drm_framebuffer *fb = pstate->fb;\n@@ -417,18 +419,18 @@ static int malidp_crtc_atomic_check(stru\n \t}\n \n \t/* If only the writeback routing has changed, we don't need a modeset */\n-\tif (state->connectors_changed) {\n+\tif (crtc_state->connectors_changed) {\n \t\tu32 old_mask = crtc->state->connector_mask;\n-\t\tu32 new_mask = state->connector_mask;\n+\t\tu32 new_mask = crtc_state->connector_mask;\n \n \t\tif ((old_mask ^ new_mask) ==\n \t\t    (1 << drm_connector_index(&malidp->mw_connector.base)))\n-\t\t\tstate->connectors_changed = false;\n+\t\t\tcrtc_state->connectors_changed = false;\n \t}\n \n-\tret = malidp_crtc_atomic_check_gamma(crtc, state);\n-\tret = ret ? ret : malidp_crtc_atomic_check_ctm(crtc, state);\n-\tret = ret ? ret : malidp_crtc_atomic_check_scaling(crtc, state);\n+\tret = malidp_crtc_atomic_check_gamma(crtc, crtc_state);\n+\tret = ret ? ret : malidp_crtc_atomic_check_ctm(crtc, crtc_state);\n+\tret = ret ? ret : malidp_crtc_atomic_check_scaling(crtc, crtc_state);\n \n \treturn ret;\n }\n--- a/drivers/gpu/drm/armada/armada_crtc.c\n+++ b/drivers/gpu/drm/armada/armada_crtc.c\n@@ -413,15 +413,17 @@ static void armada_drm_crtc_mode_set_nof\n }\n \n static int armada_drm_crtc_atomic_check(struct drm_crtc *crtc,\n-\t\t\t\t\tstruct drm_crtc_state *state)\n+\t\t\t\t\tstruct drm_atomic_state *state)\n {\n+\tstruct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,\n+\t\t\t\t\t\t\t\t\t  crtc);\n \tDRM_DEBUG_KMS(\"[CRTC:%d:%s]\\n\", crtc->base.id, crtc->name);\n \n-\tif (state->gamma_lut && drm_color_lut_size(state->gamma_lut) != 256)\n+\tif (crtc_state->gamma_lut && drm_color_lut_size(crtc_state->gamma_lut) != 256)\n \t\treturn -EINVAL;\n \n-\tif (state->color_mgmt_changed)\n-\t\tstate->planes_changed = true;\n+\tif (crtc_state->color_mgmt_changed)\n+\t\tcrtc_state->planes_changed = true;\n \n \treturn 0;\n }\n--- a/drivers/gpu/drm/ast/ast_mode.c\n+++ b/drivers/gpu/drm/ast/ast_mode.c\n@@ -751,24 +751,26 @@ static void ast_crtc_dpms(struct drm_crt\n }\n \n static int ast_crtc_helper_atomic_check(struct drm_crtc *crtc,\n-\t\t\t\t\tstruct drm_crtc_state *state)\n+\t\t\t\t\tstruct drm_atomic_state *state)\n {\n+\tstruct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,\n+\t\t\t\t\t\t\t\t\t  crtc);\n \tstruct drm_device *dev = crtc->dev;\n \tstruct ast_crtc_state *ast_state;\n \tconst struct drm_format_info *format;\n \tbool succ;\n \n-\tif (!state->enable)\n+\tif (!crtc_state->enable)\n \t\treturn 0; /* no mode checks if CRTC is being disabled */\n \n-\tast_state = to_ast_crtc_state(state);\n+\tast_state = to_ast_crtc_state(crtc_state);\n \n \tformat = ast_state->format;\n \tif (drm_WARN_ON_ONCE(dev, !format))\n \t\treturn -EINVAL; /* BUG: We didn't set format in primary check(). */\n \n-\tsucc = ast_get_vbios_mode_info(format, &state->mode,\n-\t\t\t\t       &state->adjusted_mode,\n+\tsucc = ast_get_vbios_mode_info(format, &crtc_state->mode,\n+\t\t\t\t       &crtc_state->adjusted_mode,\n \t\t\t\t       &ast_state->vbios_mode_info);\n \tif (!succ)\n \t\treturn -EINVAL;\n--- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c\n+++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c\n@@ -325,8 +325,9 @@ static int atmel_hlcdc_crtc_select_outpu\n }\n \n static int atmel_hlcdc_crtc_atomic_check(struct drm_crtc *c,\n-\t\t\t\t\t struct drm_crtc_state *s)\n+\t\t\t\t\t struct drm_atomic_state *state)\n {\n+\tstruct drm_crtc_state *s = drm_atomic_get_new_crtc_state(state, c);\n \tint ret;\n \n \tret = atmel_hlcdc_crtc_select_output_mode(s);\n--- a/drivers/gpu/drm/drm_atomic_helper.c\n+++ b/drivers/gpu/drm/drm_atomic_helper.c\n@@ -918,7 +918,7 @@ drm_atomic_helper_check_planes(struct dr\n \t\tif (!funcs || !funcs->atomic_check)\n \t\t\tcontinue;\n \n-\t\tret = funcs->atomic_check(crtc, new_crtc_state);\n+\t\tret = funcs->atomic_check(crtc, state);\n \t\tif (ret) {\n \t\t\tDRM_DEBUG_ATOMIC(\"[CRTC:%d:%s] atomic driver check failed\\n\",\n \t\t\t\t\t crtc->base.id, crtc->name);\n--- a/drivers/gpu/drm/drm_simple_kms_helper.c\n+++ b/drivers/gpu/drm/drm_simple_kms_helper.c\n@@ -86,16 +86,18 @@ drm_simple_kms_crtc_mode_valid(struct dr\n }\n \n static int drm_simple_kms_crtc_check(struct drm_crtc *crtc,\n-\t\t\t\t     struct drm_crtc_state *state)\n+\t\t\t\t     struct drm_atomic_state *state)\n {\n-\tbool has_primary = state->plane_mask &\n+\tstruct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,\n+\t\t\t\t\t\t\t\t\t  crtc);\n+\tbool has_primary = crtc_state->plane_mask &\n \t\t\t   drm_plane_mask(crtc->primary);\n \n \t/* We always want to have an active plane with an active CRTC */\n-\tif (has_primary != state->enable)\n+\tif (has_primary != crtc_state->enable)\n \t\treturn -EINVAL;\n \n-\treturn drm_atomic_add_affected_planes(state->state, crtc);\n+\treturn drm_atomic_add_affected_planes(crtc_state->state, crtc);\n }\n \n static void drm_simple_kms_crtc_enable(struct drm_crtc *crtc,\n--- a/drivers/gpu/drm/exynos/exynos_drm_crtc.c\n+++ b/drivers/gpu/drm/exynos/exynos_drm_crtc.c\n@@ -49,15 +49,17 @@ static void exynos_drm_crtc_atomic_disab\n }\n \n static int exynos_crtc_atomic_check(struct drm_crtc *crtc,\n-\t\t\t\t     struct drm_crtc_state *state)\n+\t\t\t\t     struct drm_atomic_state *state)\n {\n+\tstruct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,\n+\t\t\t\t\t\t\t\t\t  crtc);\n \tstruct exynos_drm_crtc *exynos_crtc = to_exynos_crtc(crtc);\n \n-\tif (!state->enable)\n+\tif (!crtc_state->enable)\n \t\treturn 0;\n \n \tif (exynos_crtc->ops->atomic_check)\n-\t\treturn exynos_crtc->ops->atomic_check(exynos_crtc, state);\n+\t\treturn exynos_crtc->ops->atomic_check(exynos_crtc, crtc_state);\n \n \treturn 0;\n }\n--- a/drivers/gpu/drm/imx/ipuv3-crtc.c\n+++ b/drivers/gpu/drm/imx/ipuv3-crtc.c\n@@ -227,11 +227,13 @@ static bool ipu_crtc_mode_fixup(struct d\n }\n \n static int ipu_crtc_atomic_check(struct drm_crtc *crtc,\n-\t\t\t\t struct drm_crtc_state *state)\n+\t\t\t\t struct drm_atomic_state *state)\n {\n+\tstruct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,\n+\t\t\t\t\t\t\t\t\t  crtc);\n \tu32 primary_plane_mask = drm_plane_mask(crtc->primary);\n \n-\tif (state->active && (primary_plane_mask & state->plane_mask) == 0)\n+\tif (crtc_state->active && (primary_plane_mask & crtc_state->plane_mask) == 0)\n \t\treturn -EINVAL;\n \n \treturn 0;\n--- a/drivers/gpu/drm/ingenic/ingenic-drm-drv.c\n+++ b/drivers/gpu/drm/ingenic/ingenic-drm-drv.c\n@@ -195,22 +195,27 @@ static void ingenic_drm_crtc_update_timi\n }\n \n static int ingenic_drm_crtc_atomic_check(struct drm_crtc *crtc,\n-\t\t\t\t\t struct drm_crtc_state *state)\n+\t\t\t\t\t struct drm_atomic_state *state)\n {\n+\tstruct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,\n+\t\t\t\t\t\t\t\t\t  crtc);\n \tstruct ingenic_drm *priv = drm_crtc_get_priv(crtc);\n \tstruct drm_plane_state *f1_state, *f0_state, *ipu_state = NULL;\n \n-\tif (drm_atomic_crtc_needs_modeset(state) && priv->soc_info->has_osd) {\n-\t\tf1_state = drm_atomic_get_plane_state(state->state, &priv->f1);\n+\tif (drm_atomic_crtc_needs_modeset(crtc_state) && priv->soc_info->has_osd) {\n+\t\tf1_state = drm_atomic_get_plane_state(crtc_state->state,\n+\t\t\t\t\t\t      &priv->f1);\n \t\tif (IS_ERR(f1_state))\n \t\t\treturn PTR_ERR(f1_state);\n \n-\t\tf0_state = drm_atomic_get_plane_state(state->state, &priv->f0);\n+\t\tf0_state = drm_atomic_get_plane_state(crtc_state->state,\n+\t\t\t\t\t\t      &priv->f0);\n \t\tif (IS_ERR(f0_state))\n \t\t\treturn PTR_ERR(f0_state);\n \n \t\tif (IS_ENABLED(CONFIG_DRM_INGENIC_IPU) && priv->ipu_plane) {\n-\t\t\tipu_state = drm_atomic_get_plane_state(state->state, priv->ipu_plane);\n+\t\t\tipu_state = drm_atomic_get_plane_state(crtc_state->state,\n+\t\t\t\t\t\t\t       priv->ipu_plane);\n \t\t\tif (IS_ERR(ipu_state))\n \t\t\t\treturn PTR_ERR(ipu_state);\n \n--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c\n+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c\n@@ -815,10 +815,12 @@ struct plane_state {\n };\n \n static int dpu_crtc_atomic_check(struct drm_crtc *crtc,\n-\t\tstruct drm_crtc_state *state)\n+\t\tstruct drm_atomic_state *state)\n {\n+\tstruct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,\n+\t\t\t\t\t\t\t\t\t  crtc);\n \tstruct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);\n-\tstruct dpu_crtc_state *cstate = to_dpu_crtc_state(state);\n+\tstruct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc_state);\n \tstruct plane_state *pstates;\n \n \tconst struct drm_plane_state *pstate;\n@@ -835,32 +837,33 @@ static int dpu_crtc_atomic_check(struct\n \n \tpstates = kzalloc(sizeof(*pstates) * DPU_STAGE_MAX * 4, GFP_KERNEL);\n \n-\tif (!state->enable || !state->active) {\n+\tif (!crtc_state->enable || !crtc_state->active) {\n \t\tDPU_DEBUG(\"crtc%d -> enable %d, active %d, skip atomic_check\\n\",\n-\t\t\t\tcrtc->base.id, state->enable, state->active);\n+\t\t\t\tcrtc->base.id, crtc_state->enable,\n+\t\t\t\tcrtc_state->active);\n \t\tgoto end;\n \t}\n \n-\tmode = &state->adjusted_mode;\n+\tmode = &crtc_state->adjusted_mode;\n \tDPU_DEBUG(\"%s: check\", dpu_crtc->name);\n \n \t/* force a full mode set if active state changed */\n-\tif (state->active_changed)\n-\t\tstate->mode_changed = true;\n+\tif (crtc_state->active_changed)\n+\t\tcrtc_state->mode_changed = true;\n \n \tmemset(pipe_staged, 0, sizeof(pipe_staged));\n \n \tif (cstate->num_mixers) {\n \t\tmixer_width = mode->hdisplay / cstate->num_mixers;\n \n-\t\t_dpu_crtc_setup_lm_bounds(crtc, state);\n+\t\t_dpu_crtc_setup_lm_bounds(crtc, crtc_state);\n \t}\n \n \tcrtc_rect.x2 = mode->hdisplay;\n \tcrtc_rect.y2 = mode->vdisplay;\n \n \t /* get plane state for all drm planes associated with crtc state */\n-\tdrm_atomic_crtc_state_for_each_plane_state(plane, pstate, state) {\n+\tdrm_atomic_crtc_state_for_each_plane_state(plane, pstate, crtc_state) {\n \t\tstruct drm_rect dst, clip = crtc_rect;\n \n \t\tif (IS_ERR_OR_NULL(pstate)) {\n@@ -966,7 +969,7 @@ static int dpu_crtc_atomic_check(struct\n \n \tatomic_inc(&_dpu_crtc_get_kms(crtc)->bandwidth_ref);\n \n-\trc = dpu_core_perf_crtc_check(crtc, state);\n+\trc = dpu_core_perf_crtc_check(crtc, crtc_state);\n \tif (rc) {\n \t\tDPU_ERROR(\"crtc%d failed performance check %d\\n\",\n \t\t\t\tcrtc->base.id, rc);\n--- a/drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c\n+++ b/drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c\n@@ -307,7 +307,7 @@ static void mdp4_crtc_atomic_enable(stru\n }\n \n static int mdp4_crtc_atomic_check(struct drm_crtc *crtc,\n-\t\tstruct drm_crtc_state *state)\n+\t\tstruct drm_atomic_state *state)\n {\n \tstruct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);\n \tDBG(\"%s: check\", mdp4_crtc->name);\n--- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c\n+++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c\n@@ -7,6 +7,7 @@\n \n #include <linux/sort.h>\n \n+#include <drm/drm_atomic.h>\n #include <drm/drm_mode.h>\n #include <drm/drm_crtc.h>\n #include <drm/drm_flip_work.h>\n@@ -682,15 +683,17 @@ static enum mdp_mixer_stage_id get_start\n }\n \n static int mdp5_crtc_atomic_check(struct drm_crtc *crtc,\n-\t\tstruct drm_crtc_state *state)\n+\t\tstruct drm_atomic_state *state)\n {\n+\tstruct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,\n+\t\t\t\t\t\t\t\t\t  crtc);\n \tstruct mdp5_kms *mdp5_kms = get_kms(crtc);\n \tstruct drm_plane *plane;\n \tstruct drm_device *dev = crtc->dev;\n \tstruct plane_state pstates[STAGE_MAX + 1];\n \tconst struct mdp5_cfg_hw *hw_cfg;\n \tconst struct drm_plane_state *pstate;\n-\tconst struct drm_display_mode *mode = &state->adjusted_mode;\n+\tconst struct drm_display_mode *mode = &crtc_state->adjusted_mode;\n \tbool cursor_plane = false;\n \tbool need_right_mixer = false;\n \tint cnt = 0, i;\n@@ -699,7 +702,7 @@ static int mdp5_crtc_atomic_check(struct\n \n \tDBG(\"%s: check\", crtc->name);\n \n-\tdrm_atomic_crtc_state_for_each_plane_state(plane, pstate, state) {\n+\tdrm_atomic_crtc_state_for_each_plane_state(plane, pstate, crtc_state) {\n \t\tif (!pstate->visible)\n \t\t\tcontinue;\n \n@@ -731,7 +734,7 @@ static int mdp5_crtc_atomic_check(struct\n \tif (mode->hdisplay > hw_cfg->lm.max_width)\n \t\tneed_right_mixer = true;\n \n-\tret = mdp5_crtc_setup_pipeline(crtc, state, need_right_mixer);\n+\tret = mdp5_crtc_setup_pipeline(crtc, crtc_state, need_right_mixer);\n \tif (ret) {\n \t\tDRM_DEV_ERROR(dev->dev, \"couldn't assign mixers %d\\n\", ret);\n \t\treturn ret;\n@@ -744,7 +747,7 @@ static int mdp5_crtc_atomic_check(struct\n \tWARN_ON(cursor_plane &&\n \t\t(pstates[cnt - 1].plane->type != DRM_PLANE_TYPE_CURSOR));\n \n-\tstart = get_start_stage(crtc, state, &pstates[0].state->base);\n+\tstart = get_start_stage(crtc, crtc_state, &pstates[0].state->base);\n \n \t/* verify that there are not too many planes attached to crtc\n \t * and that we don't have conflicting mixer stages:\n--- a/drivers/gpu/drm/mxsfb/mxsfb_kms.c\n+++ b/drivers/gpu/drm/mxsfb/mxsfb_kms.c\n@@ -310,17 +310,19 @@ static void mxsfb_crtc_mode_set_nofb(str\n }\n \n static int mxsfb_crtc_atomic_check(struct drm_crtc *crtc,\n-\t\t\t\t   struct drm_crtc_state *state)\n+\t\t\t\t   struct drm_atomic_state *state)\n {\n-\tbool has_primary = state->plane_mask &\n+\tstruct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,\n+\t\t\t\t\t\t\t\t\t  crtc);\n+\tbool has_primary = crtc_state->plane_mask &\n \t\t\t   drm_plane_mask(crtc->primary);\n \n \t/* The primary plane has to be enabled when the CRTC is active. */\n-\tif (state->active && !has_primary)\n+\tif (crtc_state->active && !has_primary)\n \t\treturn -EINVAL;\n \n \t/* TODO: Is this needed ? */\n-\treturn drm_atomic_add_affected_planes(state->state, crtc);\n+\treturn drm_atomic_add_affected_planes(crtc_state->state, crtc);\n }\n \n static void mxsfb_crtc_atomic_flush(struct drm_crtc *crtc,\n--- a/drivers/gpu/drm/nouveau/dispnv50/head.c\n+++ b/drivers/gpu/drm/nouveau/dispnv50/head.c\n@@ -30,6 +30,7 @@\n #include <nvif/event.h>\n #include <nvif/cl0046.h>\n \n+#include <drm/drm_atomic.h>\n #include <drm/drm_atomic_helper.h>\n #include <drm/drm_crtc_helper.h>\n #include <drm/drm_vblank.h>\n@@ -315,12 +316,14 @@ nv50_head_atomic_check_mode(struct nv50_\n }\n \n static int\n-nv50_head_atomic_check(struct drm_crtc *crtc, struct drm_crtc_state *state)\n+nv50_head_atomic_check(struct drm_crtc *crtc, struct drm_atomic_state *state)\n {\n+\tstruct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,\n+\t\t\t\t\t\t\t\t\t  crtc);\n \tstruct nouveau_drm *drm = nouveau_drm(crtc->dev);\n \tstruct nv50_head *head = nv50_head(crtc);\n \tstruct nv50_head_atom *armh = nv50_head_atom(crtc->state);\n-\tstruct nv50_head_atom *asyh = nv50_head_atom(state);\n+\tstruct nv50_head_atom *asyh = nv50_head_atom(crtc_state);\n \tstruct nouveau_conn_atom *asyc = NULL;\n \tstruct drm_connector_state *conns;\n \tstruct drm_connector *conn;\n--- a/drivers/gpu/drm/omapdrm/omap_crtc.c\n+++ b/drivers/gpu/drm/omapdrm/omap_crtc.c\n@@ -569,22 +569,25 @@ static bool omap_crtc_is_manually_update\n }\n \n static int omap_crtc_atomic_check(struct drm_crtc *crtc,\n-\t\t\t\tstruct drm_crtc_state *state)\n+\t\t\t\tstruct drm_atomic_state *state)\n {\n+\tstruct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,\n+\t\t\t\t\t\t\t\t\t  crtc);\n \tstruct drm_plane_state *pri_state;\n \n-\tif (state->color_mgmt_changed && state->gamma_lut) {\n-\t\tunsigned int length = state->gamma_lut->length /\n+\tif (crtc_state->color_mgmt_changed && crtc_state->gamma_lut) {\n+\t\tunsigned int length = crtc_state->gamma_lut->length /\n \t\t\tsizeof(struct drm_color_lut);\n \n \t\tif (length < 2)\n \t\t\treturn -EINVAL;\n \t}\n \n-\tpri_state = drm_atomic_get_new_plane_state(state->state, crtc->primary);\n+\tpri_state = drm_atomic_get_new_plane_state(crtc_state->state,\n+\t\t\t\t\t\t   crtc->primary);\n \tif (pri_state) {\n \t\tstruct omap_crtc_state *omap_crtc_state =\n-\t\t\tto_omap_crtc_state(state);\n+\t\t\tto_omap_crtc_state(crtc_state);\n \n \t\t/* Mirror new values for zpos and rotation in omap_crtc_state */\n \t\tomap_crtc_state->zpos = pri_state->zpos;\n--- a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c\n+++ b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c\n@@ -688,20 +688,23 @@ static void rcar_du_crtc_stop(struct rca\n  */\n \n static int rcar_du_crtc_atomic_check(struct drm_crtc *crtc,\n-\t\t\t\t     struct drm_crtc_state *state)\n+\t\t\t\t     struct drm_atomic_state *state)\n {\n-\tstruct rcar_du_crtc_state *rstate = to_rcar_crtc_state(state);\n+\tstruct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,\n+\t\t\t\t\t\t\t\t\t  crtc);\n+\tstruct rcar_du_crtc_state *rstate = to_rcar_crtc_state(crtc_state);\n \tstruct drm_encoder *encoder;\n \tint ret;\n \n-\tret = rcar_du_cmm_check(crtc, state);\n+\tret = rcar_du_cmm_check(crtc, crtc_state);\n \tif (ret)\n \t\treturn ret;\n \n \t/* Store the routes from the CRTC output to the DU outputs. */\n \trstate->outputs = 0;\n \n-\tdrm_for_each_encoder_mask(encoder, crtc->dev, state->encoder_mask) {\n+\tdrm_for_each_encoder_mask(encoder, crtc->dev,\n+\t\t\t\t  crtc_state->encoder_mask) {\n \t\tstruct rcar_du_encoder *renc;\n \n \t\t/* Skip the writeback encoder. */\n--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c\n+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c\n@@ -1416,8 +1416,10 @@ static void vop_wait_for_irq_handler(str\n }\n \n static int vop_crtc_atomic_check(struct drm_crtc *crtc,\n-\t\t\t\t struct drm_crtc_state *crtc_state)\n+\t\t\t\t struct drm_atomic_state *state)\n {\n+\tstruct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,\n+\t\t\t\t\t\t\t\t\t  crtc);\n \tstruct vop *vop = to_vop(crtc);\n \tstruct drm_plane *plane;\n \tstruct drm_plane_state *plane_state;\n--- a/drivers/gpu/drm/sun4i/sun4i_crtc.c\n+++ b/drivers/gpu/drm/sun4i/sun4i_crtc.c\n@@ -15,6 +15,7 @@\n \n #include <video/videomode.h>\n \n+#include <drm/drm_atomic.h>\n #include <drm/drm_atomic_helper.h>\n #include <drm/drm_crtc.h>\n #include <drm/drm_modes.h>\n@@ -45,14 +46,16 @@ static struct drm_encoder *sun4i_crtc_ge\n }\n \n static int sun4i_crtc_atomic_check(struct drm_crtc *crtc,\n-\t\t\t\t    struct drm_crtc_state *state)\n+\t\t\t\t    struct drm_atomic_state *state)\n {\n+\tstruct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,\n+\t\t\t\t\t\t\t\t\t  crtc);\n \tstruct sun4i_crtc *scrtc = drm_crtc_to_sun4i_crtc(crtc);\n \tstruct sunxi_engine *engine = scrtc->engine;\n \tint ret = 0;\n \n \tif (engine && engine->ops && engine->ops->atomic_check)\n-\t\tret = engine->ops->atomic_check(engine, state);\n+\t\tret = engine->ops->atomic_check(engine, crtc_state);\n \n \treturn ret;\n }\n--- a/drivers/gpu/drm/tidss/tidss_crtc.c\n+++ b/drivers/gpu/drm/tidss/tidss_crtc.c\n@@ -85,8 +85,10 @@ void tidss_crtc_error_irq(struct drm_crt\n /* drm_crtc_helper_funcs */\n \n static int tidss_crtc_atomic_check(struct drm_crtc *crtc,\n-\t\t\t\t   struct drm_crtc_state *state)\n+\t\t\t\t   struct drm_atomic_state *state)\n {\n+\tstruct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,\n+\t\t\t\t\t\t\t\t\t  crtc);\n \tstruct drm_device *ddev = crtc->dev;\n \tstruct tidss_device *tidss = to_tidss(ddev);\n \tstruct dispc_device *dispc = tidss->dispc;\n@@ -97,10 +99,10 @@ static int tidss_crtc_atomic_check(struc\n \n \tdev_dbg(ddev->dev, \"%s\\n\", __func__);\n \n-\tif (!state->enable)\n+\tif (!crtc_state->enable)\n \t\treturn 0;\n \n-\tmode = &state->adjusted_mode;\n+\tmode = &crtc_state->adjusted_mode;\n \n \tok = dispc_vp_mode_valid(dispc, hw_videoport, mode);\n \tif (ok != MODE_OK) {\n@@ -109,7 +111,7 @@ static int tidss_crtc_atomic_check(struc\n \t\treturn -EINVAL;\n \t}\n \n-\treturn dispc_vp_bus_check(dispc, hw_videoport, state);\n+\treturn dispc_vp_bus_check(dispc, hw_videoport, crtc_state);\n }\n \n /*\n--- a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c\n+++ b/drivers/gpu/drm/tilcdc/tilcdc_crtc.c\n@@ -669,15 +669,17 @@ static bool tilcdc_crtc_mode_fixup(struc\n }\n \n static int tilcdc_crtc_atomic_check(struct drm_crtc *crtc,\n-\t\t\t\t    struct drm_crtc_state *state)\n+\t\t\t\t    struct drm_atomic_state *state)\n {\n+\tstruct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,\n+\t\t\t\t\t\t\t\t\t  crtc);\n \t/* If we are not active we don't care */\n-\tif (!state->active)\n+\tif (!crtc_state->active)\n \t\treturn 0;\n \n-\tif (state->state->planes[0].ptr != crtc->primary ||\n-\t    state->state->planes[0].state == NULL ||\n-\t    state->state->planes[0].state->crtc != crtc) {\n+\tif (crtc_state->state->planes[0].ptr != crtc->primary ||\n+\t    crtc_state->state->planes[0].state == NULL ||\n+\t    crtc_state->state->planes[0].state->crtc != crtc) {\n \t\tdev_dbg(crtc->dev->dev, \"CRTC primary plane must be present\");\n \t\treturn -EINVAL;\n \t}\n--- a/drivers/gpu/drm/vc4/vc4_crtc.c\n+++ b/drivers/gpu/drm/vc4/vc4_crtc.c\n@@ -601,18 +601,21 @@ void vc4_crtc_get_margins(struct drm_crt\n }\n \n static int vc4_crtc_atomic_check(struct drm_crtc *crtc,\n-\t\t\t\t struct drm_crtc_state *state)\n+\t\t\t\t struct drm_atomic_state *state)\n {\n-\tstruct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);\n+\tstruct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,\n+\t\t\t\t\t\t\t\t\t  crtc);\n+\tstruct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc_state);\n \tstruct drm_connector *conn;\n \tstruct drm_connector_state *conn_state;\n \tint ret, i;\n \n-\tret = vc4_hvs_atomic_check(crtc, state);\n+\tret = vc4_hvs_atomic_check(crtc, crtc_state);\n \tif (ret)\n \t\treturn ret;\n \n-\tfor_each_new_connector_in_state(state->state, conn, conn_state, i) {\n+\tfor_each_new_connector_in_state(crtc_state->state, conn, conn_state,\n+\t\t\t\t\ti) {\n \t\tif (conn_state->crtc != crtc)\n \t\t\tcontinue;\n \n--- a/drivers/gpu/drm/vc4/vc4_txp.c\n+++ b/drivers/gpu/drm/vc4/vc4_txp.c\n@@ -386,16 +386,18 @@ static const struct drm_crtc_funcs vc4_t\n };\n \n static int vc4_txp_atomic_check(struct drm_crtc *crtc,\n-\t\t\t\tstruct drm_crtc_state *state)\n+\t\t\t\tstruct drm_atomic_state *state)\n {\n-\tstruct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);\n+\tstruct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,\n+\t\t\t\t\t\t\t\t\t  crtc);\n+\tstruct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc_state);\n \tint ret;\n \n-\tret = vc4_hvs_atomic_check(crtc, state);\n+\tret = vc4_hvs_atomic_check(crtc, crtc_state);\n \tif (ret)\n \t\treturn ret;\n \n-\tstate->no_vblank = true;\n+\tcrtc_state->no_vblank = true;\n \tvc4_state->feed_txp = true;\n \n \treturn 0;\n--- a/drivers/gpu/drm/virtio/virtgpu_display.c\n+++ b/drivers/gpu/drm/virtio/virtgpu_display.c\n@@ -111,7 +111,7 @@ static void virtio_gpu_crtc_atomic_disab\n }\n \n static int virtio_gpu_crtc_atomic_check(struct drm_crtc *crtc,\n-\t\t\t\t\tstruct drm_crtc_state *state)\n+\t\t\t\t\tstruct drm_atomic_state *state)\n {\n \treturn 0;\n }\n--- a/drivers/gpu/drm/vkms/vkms_crtc.c\n+++ b/drivers/gpu/drm/vkms/vkms_crtc.c\n@@ -169,9 +169,11 @@ static const struct drm_crtc_funcs vkms_\n };\n \n static int vkms_crtc_atomic_check(struct drm_crtc *crtc,\n-\t\t\t\t  struct drm_crtc_state *state)\n+\t\t\t\t  struct drm_atomic_state *state)\n {\n-\tstruct vkms_crtc_state *vkms_state = to_vkms_crtc_state(state);\n+\tstruct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,\n+\t\t\t\t\t\t\t\t\t  crtc);\n+\tstruct vkms_crtc_state *vkms_state = to_vkms_crtc_state(crtc_state);\n \tstruct drm_plane *plane;\n \tstruct drm_plane_state *plane_state;\n \tint i = 0, ret;\n@@ -179,12 +181,12 @@ static int vkms_crtc_atomic_check(struct\n \tif (vkms_state->active_planes)\n \t\treturn 0;\n \n-\tret = drm_atomic_add_affected_planes(state->state, crtc);\n+\tret = drm_atomic_add_affected_planes(crtc_state->state, crtc);\n \tif (ret < 0)\n \t\treturn ret;\n \n-\tdrm_for_each_plane_mask(plane, crtc->dev, state->plane_mask) {\n-\t\tplane_state = drm_atomic_get_existing_plane_state(state->state,\n+\tdrm_for_each_plane_mask(plane, crtc->dev, crtc_state->plane_mask) {\n+\t\tplane_state = drm_atomic_get_existing_plane_state(crtc_state->state,\n \t\t\t\t\t\t\t\t  plane);\n \t\tWARN_ON(!plane_state);\n \n@@ -200,8 +202,8 @@ static int vkms_crtc_atomic_check(struct\n \tvkms_state->num_active_planes = i;\n \n \ti = 0;\n-\tdrm_for_each_plane_mask(plane, crtc->dev, state->plane_mask) {\n-\t\tplane_state = drm_atomic_get_existing_plane_state(state->state,\n+\tdrm_for_each_plane_mask(plane, crtc->dev, crtc_state->plane_mask) {\n+\t\tplane_state = drm_atomic_get_existing_plane_state(crtc_state->state,\n \t\t\t\t\t\t\t\t  plane);\n \n \t\tif (!plane_state->visible)\n--- a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c\n+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c\n@@ -522,8 +522,10 @@ int vmw_du_cursor_plane_atomic_check(str\n \n \n int vmw_du_crtc_atomic_check(struct drm_crtc *crtc,\n-\t\t\t     struct drm_crtc_state *new_state)\n+\t\t\t     struct drm_atomic_state *state)\n {\n+\tstruct drm_crtc_state *new_state = drm_atomic_get_new_crtc_state(state,\n+\t\t\t\t\t\t\t\t\t crtc);\n \tstruct vmw_display_unit *du = vmw_crtc_to_du(new_state->crtc);\n \tint connector_mask = drm_connector_mask(&du->connector);\n \tbool has_primary = new_state->plane_mask &\n--- a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.h\n+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.h\n@@ -473,7 +473,7 @@ void vmw_du_plane_unpin_surf(struct vmw_\n \t\t\t     bool unreference);\n \n int vmw_du_crtc_atomic_check(struct drm_crtc *crtc,\n-\t\t\t     struct drm_crtc_state *state);\n+\t\t\t     struct drm_atomic_state *state);\n void vmw_du_crtc_atomic_begin(struct drm_crtc *crtc,\n \t\t\t      struct drm_crtc_state *old_crtc_state);\n void vmw_du_crtc_atomic_flush(struct drm_crtc *crtc,\n--- a/drivers/gpu/drm/xlnx/zynqmp_disp.c\n+++ b/drivers/gpu/drm/xlnx/zynqmp_disp.c\n@@ -1506,9 +1506,11 @@ zynqmp_disp_crtc_atomic_disable(struct d\n }\n \n static int zynqmp_disp_crtc_atomic_check(struct drm_crtc *crtc,\n-\t\t\t\t\t struct drm_crtc_state *state)\n+\t\t\t\t\t struct drm_atomic_state *state)\n {\n-\treturn drm_atomic_add_affected_planes(state->state, crtc);\n+\tstruct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,\n+\t\t\t\t\t\t\t\t\t  crtc);\n+\treturn drm_atomic_add_affected_planes(crtc_state->state, crtc);\n }\n \n static void\n--- a/include/drm/drm_modeset_helper_vtables.h\n+++ b/include/drm/drm_modeset_helper_vtables.h\n@@ -336,8 +336,7 @@ struct drm_crtc_helper_funcs {\n \t *\n \t * This function is called in the check phase of an atomic update. The\n \t * driver is not allowed to change anything outside of the free-standing\n-\t * state objects passed-in or assembled in the overall &drm_atomic_state\n-\t * update tracking structure.\n+\t * state object passed-in.\n \t *\n \t * Also beware that userspace can request its own custom modes, neither\n \t * core nor helpers filter modes to the list of probe modes reported by\n@@ -353,7 +352,7 @@ struct drm_crtc_helper_funcs {\n \t * deadlock.\n \t */\n \tint (*atomic_check)(struct drm_crtc *crtc,\n-\t\t\t    struct drm_crtc_state *state);\n+\t\t\t    struct drm_atomic_state *state);\n \n \t/**\n \t * @atomic_begin:\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0410-drm-atomic-Pass-the-full-state-to-CRTC-atomic-begin-.patch",
    "content": "From 0dd369ae91c3c4d2db2aa292935d12db5a0d97e1 Mon Sep 17 00:00:00 2001\nFrom: Maxime Ripard <maxime@cerno.tech>\nDate: Wed, 28 Oct 2020 13:32:22 +0100\nSubject: [PATCH] drm/atomic: Pass the full state to CRTC atomic begin\n and flush\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nCommit f6ebe9f9c9233a6114eb922aba9a0c9ccc2d2e14 upstream.\n\nThe current atomic helpers have either their object state being passed as\nan argument or the full atomic state.\n\nThe former is the pattern that was done at first, before switching to the\nlatter for new hooks or when it was needed.\n\nLet's start convert all the remaining helpers to provide a consistent\ninterface, starting with the CRTC's atomic_begin and atomic_flush.\n\nThe conversion was done using the coccinelle script below, built tested on\nall the drivers and actually tested on vc4.\n\nvirtual report\n\n@@\nstruct drm_crtc_helper_funcs *FUNCS;\nidentifier old_crtc_state, old_state;\nidentifier crtc;\nidentifier f;\n@@\n\n f(struct drm_crtc_state *old_crtc_state)\n {\n\t...\n \tstruct drm_atomic_state *old_state = old_crtc_state->state;\n\t<...\n-\tFUNCS->atomic_begin(crtc, old_crtc_state);\n+\tFUNCS->atomic_begin(crtc, old_state);\n\t...>\n }\n\n@@\nstruct drm_crtc_helper_funcs *FUNCS;\nidentifier old_crtc_state, old_state;\nidentifier crtc;\nidentifier f;\n@@\n\n f(struct drm_crtc_state *old_crtc_state)\n {\n\t...\n \tstruct drm_atomic_state *old_state = old_crtc_state->state;\n\t<...\n-\tFUNCS->atomic_flush(crtc, old_crtc_state);\n+\tFUNCS->atomic_flush(crtc, old_state);\n\t...>\n }\n\n@@\nstruct drm_crtc_helper_funcs *FUNCS;\nstruct drm_crtc *crtc;\nstruct drm_crtc_state *crtc_state;\nidentifier dev, state;\nidentifier f;\n@@\n\n f(struct drm_device *dev, struct drm_atomic_state *state, ...)\n {\n\t<...\n-\tFUNCS->atomic_begin(crtc, crtc_state);\n+\tFUNCS->atomic_begin(crtc, state);\n\t...>\n }\n\n@@\nstruct drm_crtc_helper_funcs *FUNCS;\nstruct drm_crtc *crtc;\nstruct drm_crtc_state *crtc_state;\nidentifier dev, state;\nidentifier f;\n@@\n\n f(struct drm_device *dev, struct drm_atomic_state *state, ...)\n {\n\t<...\n-\tFUNCS->atomic_flush(crtc, crtc_state);\n+\tFUNCS->atomic_flush(crtc, state);\n\t...>\n }\n\n@@\nidentifier crtc, old_state;\n@@\n\n struct drm_crtc_helper_funcs {\n\t...\n-\tvoid (*atomic_begin)(struct drm_crtc *crtc, struct drm_crtc_state *old_state);\n+\tvoid (*atomic_begin)(struct drm_crtc *crtc, struct drm_atomic_state *state);\n\t...\n-\tvoid (*atomic_flush)(struct drm_crtc *crtc, struct drm_crtc_state *old_state);\n+\tvoid (*atomic_flush)(struct drm_crtc *crtc, struct drm_atomic_state *state);\n\t...\n}\n\n@ crtc_atomic_func @\nidentifier helpers;\nidentifier func;\n@@\n\n(\nstatic struct drm_crtc_helper_funcs helpers = {\n\t...,\n\t.atomic_begin = func,\n\t...,\n};\n|\nstatic struct drm_crtc_helper_funcs helpers = {\n\t...,\n\t.atomic_flush = func,\n\t...,\n};\n)\n\n@ ignores_old_state @\nidentifier crtc_atomic_func.func;\nidentifier crtc, old_state;\n@@\n\nvoid func(struct drm_crtc *crtc,\n\t\tstruct drm_crtc_state *old_state)\n{\n\t... when != old_state\n}\n\n@ adds_old_state depends on crtc_atomic_func && !ignores_old_state @\nidentifier crtc_atomic_func.func;\nidentifier crtc, old_state;\n@@\n\nvoid func(struct drm_crtc *crtc, struct drm_crtc_state *old_state)\n{\n+\tstruct drm_crtc_state *old_state = drm_atomic_get_old_crtc_state(state, crtc);\n\t...\n}\n\n@ depends on crtc_atomic_func @\nidentifier crtc_atomic_func.func;\nexpression E;\ntype T;\n@@\n\nvoid func(...)\n{\n\t...\n-\tT state = E;\n+\tT crtc_state = E;\n\t<+...\n-\tstate\n+\tcrtc_state\n\t...+>\n\n}\n\n@ depends on crtc_atomic_func @\nidentifier crtc_atomic_func.func;\ntype T;\n@@\n\nvoid func(...)\n{\n\t...\n-\tT state;\n+\tT crtc_state;\n\t<+...\n-\tstate\n+\tcrtc_state\n\t...+>\n\n}\n\n@@\nidentifier old_state;\nidentifier crtc;\n@@\n\n void vc4_hvs_atomic_flush(struct drm_crtc *crtc,\n-\t\t\t   struct drm_crtc_state *old_state\n+\t\t\t   struct drm_atomic_state *state\n\t\t\t   )\n{\n+\tstruct drm_crtc_state *old_state = drm_atomic_get_old_crtc_state(state, crtc);\n\t...\n}\n\n@@\nidentifier old_state;\nidentifier crtc;\n@@\n\n void vc4_hvs_atomic_flush(struct drm_crtc *crtc,\n-\t\t\t   struct drm_crtc_state *old_state\n+\t\t\t   struct drm_atomic_state *state\n\t\t\t   );\n\n@@\nidentifier old_state;\nidentifier crtc;\n@@\n\n void vmw_du_crtc_atomic_begin(struct drm_crtc *crtc,\n-\t\t\t   struct drm_crtc_state *old_state\n+\t\t\t   struct drm_atomic_state *state\n\t\t\t   )\n{\n\t...\n}\n\n@@\nidentifier old_state;\nidentifier crtc;\n@@\n\n void vmw_du_crtc_atomic_begin(struct drm_crtc *crtc,\n-\t\t\t   struct drm_crtc_state *old_state\n+\t\t\t   struct drm_atomic_state *state\n\t\t\t   );\n\n@@\nidentifier old_state;\nidentifier crtc;\n@@\n\n void vmw_du_crtc_atomic_flush(struct drm_crtc *crtc,\n-\t\t\t   struct drm_crtc_state *old_state\n+\t\t\t   struct drm_atomic_state *state\n\t\t\t   )\n{\n\t...\n}\n\n@@\nidentifier old_state;\nidentifier crtc;\n@@\n\n void vmw_du_crtc_atomic_flush(struct drm_crtc *crtc,\n-\t\t\t   struct drm_crtc_state *old_state\n+\t\t\t   struct drm_atomic_state *state\n\t\t\t   );\n\n@ depends on crtc_atomic_func @\nidentifier crtc_atomic_func.func;\nidentifier old_state;\nidentifier crtc;\n@@\n\nvoid func(struct drm_crtc *crtc,\n-\t       struct drm_crtc_state *old_state\n+\t       struct drm_atomic_state *state\n\t       )\n\t\t{ ... }\n\n@ include depends on adds_old_state @\n@@\n\n #include <drm/drm_atomic.h>\n\n@ no_include depends on !include && adds_old_state @\n@@\n\n+ #include <drm/drm_atomic.h>\n  #include <drm/...>\n\nSigned-off-by: Maxime Ripard <maxime@cerno.tech>\nReviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>\nAcked-by: Daniel Vetter <daniel.vetter@ffwll.ch>\nAcked-by: Thomas Zimmermann <tzimmermann@suse.de>\nLink: https://patchwork.freedesktop.org/patch/msgid/20201028123222.1732139-2-maxime@cerno.tech\n---\n drivers/gpu/drm/arm/display/komeda/komeda_crtc.c |  4 +++-\n drivers/gpu/drm/arm/hdlcd_crtc.c                 |  2 +-\n drivers/gpu/drm/armada/armada_crtc.c             |  4 ++--\n drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c   |  4 ++--\n drivers/gpu/drm/drm_atomic_helper.c              |  8 ++++----\n drivers/gpu/drm/exynos/exynos_drm_crtc.c         |  4 ++--\n drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c       |  2 +-\n drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c   |  4 ++--\n drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c  |  4 ++--\n drivers/gpu/drm/imx/dcss/dcss-crtc.c             |  4 ++--\n drivers/gpu/drm/imx/ipuv3-crtc.c                 |  4 ++--\n drivers/gpu/drm/ingenic/ingenic-drm-drv.c        | 14 +++++++-------\n drivers/gpu/drm/mediatek/mtk_drm_crtc.c          | 16 ++++++++--------\n drivers/gpu/drm/meson/meson_crtc.c               |  4 ++--\n drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c         |  4 ++--\n drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c        |  4 ++--\n drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c        |  4 ++--\n drivers/gpu/drm/mxsfb/mxsfb_kms.c                |  2 +-\n drivers/gpu/drm/omapdrm/omap_crtc.c              |  4 ++--\n drivers/gpu/drm/qxl/qxl_display.c                |  2 +-\n drivers/gpu/drm/rcar-du/rcar_du_crtc.c           |  4 ++--\n drivers/gpu/drm/rockchip/rockchip_drm_vop.c      |  8 ++++++--\n drivers/gpu/drm/sti/sti_crtc.c                   |  2 +-\n drivers/gpu/drm/stm/ltdc.c                       |  2 +-\n drivers/gpu/drm/sun4i/sun4i_crtc.c               |  6 ++++--\n drivers/gpu/drm/tegra/dc.c                       | 10 +++++-----\n drivers/gpu/drm/tidss/tidss_crtc.c               |  4 +++-\n drivers/gpu/drm/tilcdc/tilcdc_crtc.c             |  2 +-\n drivers/gpu/drm/vboxvideo/vbox_mode.c            |  2 +-\n drivers/gpu/drm/vc4/vc4_drv.h                    |  3 ++-\n drivers/gpu/drm/vc4/vc4_hvs.c                    |  4 +++-\n drivers/gpu/drm/virtio/virtgpu_display.c         |  2 +-\n drivers/gpu/drm/vkms/vkms_crtc.c                 |  4 ++--\n drivers/gpu/drm/vmwgfx/vmwgfx_kms.c              |  4 ++--\n drivers/gpu/drm/vmwgfx/vmwgfx_kms.h              |  4 ++--\n drivers/gpu/drm/xlnx/zynqmp_disp.c               |  4 ++--\n drivers/gpu/drm/zte/zx_vou.c                     |  2 +-\n include/drm/drm_modeset_helper_vtables.h         |  4 ++--\n 38 files changed, 91 insertions(+), 78 deletions(-)\n\n--- a/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c\n+++ b/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c\n@@ -385,8 +385,10 @@ komeda_crtc_atomic_disable(struct drm_cr\n \n static void\n komeda_crtc_atomic_flush(struct drm_crtc *crtc,\n-\t\t\t struct drm_crtc_state *old)\n+\t\t\t struct drm_atomic_state *state)\n {\n+\tstruct drm_crtc_state *old = drm_atomic_get_old_crtc_state(state,\n+\t\t\t\t\t\t\t\t   crtc);\n \t/* commit with modeset will be handled in enable/disable */\n \tif (drm_atomic_crtc_needs_modeset(crtc->state))\n \t\treturn;\n--- a/drivers/gpu/drm/arm/hdlcd_crtc.c\n+++ b/drivers/gpu/drm/arm/hdlcd_crtc.c\n@@ -205,7 +205,7 @@ static enum drm_mode_status hdlcd_crtc_m\n }\n \n static void hdlcd_crtc_atomic_begin(struct drm_crtc *crtc,\n-\t\t\t\t    struct drm_crtc_state *state)\n+\t\t\t\t    struct drm_atomic_state *state)\n {\n \tstruct drm_pending_vblank_event *event = crtc->state->event;\n \n--- a/drivers/gpu/drm/armada/armada_crtc.c\n+++ b/drivers/gpu/drm/armada/armada_crtc.c\n@@ -429,7 +429,7 @@ static int armada_drm_crtc_atomic_check(\n }\n \n static void armada_drm_crtc_atomic_begin(struct drm_crtc *crtc,\n-\t\t\t\t\t struct drm_crtc_state *old_crtc_state)\n+\t\t\t\t\t struct drm_atomic_state *state)\n {\n \tstruct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);\n \n@@ -443,7 +443,7 @@ static void armada_drm_crtc_atomic_begin\n }\n \n static void armada_drm_crtc_atomic_flush(struct drm_crtc *crtc,\n-\t\t\t\t\t struct drm_crtc_state *old_crtc_state)\n+\t\t\t\t\t struct drm_atomic_state *state)\n {\n \tstruct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);\n \n--- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c\n+++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c\n@@ -342,7 +342,7 @@ static int atmel_hlcdc_crtc_atomic_check\n }\n \n static void atmel_hlcdc_crtc_atomic_begin(struct drm_crtc *c,\n-\t\t\t\t\t  struct drm_crtc_state *old_s)\n+\t\t\t\t\t  struct drm_atomic_state *state)\n {\n \tstruct atmel_hlcdc_crtc *crtc = drm_crtc_to_atmel_hlcdc_crtc(c);\n \n@@ -357,7 +357,7 @@ static void atmel_hlcdc_crtc_atomic_begi\n }\n \n static void atmel_hlcdc_crtc_atomic_flush(struct drm_crtc *crtc,\n-\t\t\t\t\t  struct drm_crtc_state *old_s)\n+\t\t\t\t\t  struct drm_atomic_state *state)\n {\n \t/* TODO: write common plane control register if available */\n }\n--- a/drivers/gpu/drm/drm_atomic_helper.c\n+++ b/drivers/gpu/drm/drm_atomic_helper.c\n@@ -2507,7 +2507,7 @@ void drm_atomic_helper_commit_planes(str\n \t\tif (active_only && !new_crtc_state->active)\n \t\t\tcontinue;\n \n-\t\tfuncs->atomic_begin(crtc, old_crtc_state);\n+\t\tfuncs->atomic_begin(crtc, old_state);\n \t}\n \n \tfor_each_oldnew_plane_in_state(old_state, plane, old_plane_state, new_plane_state, i) {\n@@ -2565,7 +2565,7 @@ void drm_atomic_helper_commit_planes(str\n \t\tif (active_only && !new_crtc_state->active)\n \t\t\tcontinue;\n \n-\t\tfuncs->atomic_flush(crtc, old_crtc_state);\n+\t\tfuncs->atomic_flush(crtc, old_state);\n \t}\n }\n EXPORT_SYMBOL(drm_atomic_helper_commit_planes);\n@@ -2603,7 +2603,7 @@ drm_atomic_helper_commit_planes_on_crtc(\n \n \tcrtc_funcs = crtc->helper_private;\n \tif (crtc_funcs && crtc_funcs->atomic_begin)\n-\t\tcrtc_funcs->atomic_begin(crtc, old_crtc_state);\n+\t\tcrtc_funcs->atomic_begin(crtc, old_state);\n \n \tdrm_for_each_plane_mask(plane, crtc->dev, plane_mask) {\n \t\tstruct drm_plane_state *old_plane_state =\n@@ -2629,7 +2629,7 @@ drm_atomic_helper_commit_planes_on_crtc(\n \t}\n \n \tif (crtc_funcs && crtc_funcs->atomic_flush)\n-\t\tcrtc_funcs->atomic_flush(crtc, old_crtc_state);\n+\t\tcrtc_funcs->atomic_flush(crtc, old_state);\n }\n EXPORT_SYMBOL(drm_atomic_helper_commit_planes_on_crtc);\n \n--- a/drivers/gpu/drm/exynos/exynos_drm_crtc.c\n+++ b/drivers/gpu/drm/exynos/exynos_drm_crtc.c\n@@ -65,7 +65,7 @@ static int exynos_crtc_atomic_check(stru\n }\n \n static void exynos_crtc_atomic_begin(struct drm_crtc *crtc,\n-\t\t\t\t     struct drm_crtc_state *old_crtc_state)\n+\t\t\t\t     struct drm_atomic_state *state)\n {\n \tstruct exynos_drm_crtc *exynos_crtc = to_exynos_crtc(crtc);\n \n@@ -74,7 +74,7 @@ static void exynos_crtc_atomic_begin(str\n }\n \n static void exynos_crtc_atomic_flush(struct drm_crtc *crtc,\n-\t\t\t\t     struct drm_crtc_state *old_crtc_state)\n+\t\t\t\t     struct drm_atomic_state *state)\n {\n \tstruct exynos_drm_crtc *exynos_crtc = to_exynos_crtc(crtc);\n \n--- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c\n+++ b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c\n@@ -21,7 +21,7 @@\n #include \"fsl_dcu_drm_plane.h\"\n \n static void fsl_dcu_drm_crtc_atomic_flush(struct drm_crtc *crtc,\n-\t\t\t\t\t  struct drm_crtc_state *old_crtc_state)\n+\t\t\t\t\t  struct drm_atomic_state *state)\n {\n \tstruct drm_device *dev = crtc->dev;\n \tstruct fsl_dcu_drm_device *fsl_dev = dev->dev_private;\n--- a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c\n+++ b/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c\n@@ -393,7 +393,7 @@ static void hibmc_crtc_mode_set_nofb(str\n }\n \n static void hibmc_crtc_atomic_begin(struct drm_crtc *crtc,\n-\t\t\t\t    struct drm_crtc_state *old_state)\n+\t\t\t\t    struct drm_atomic_state *state)\n {\n \tunsigned int reg;\n \tstruct drm_device *dev = crtc->dev;\n@@ -413,7 +413,7 @@ static void hibmc_crtc_atomic_begin(stru\n }\n \n static void hibmc_crtc_atomic_flush(struct drm_crtc *crtc,\n-\t\t\t\t    struct drm_crtc_state *old_state)\n+\t\t\t\t    struct drm_atomic_state *state)\n \n {\n \tunsigned long flags;\n--- a/drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c\n+++ b/drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c\n@@ -485,7 +485,7 @@ static void ade_crtc_mode_set_nofb(struc\n }\n \n static void ade_crtc_atomic_begin(struct drm_crtc *crtc,\n-\t\t\t\t  struct drm_crtc_state *old_state)\n+\t\t\t\t  struct drm_atomic_state *state)\n {\n \tstruct kirin_crtc *kcrtc = to_kirin_crtc(crtc);\n \tstruct ade_hw_ctx *ctx = kcrtc->hw_ctx;\n@@ -498,7 +498,7 @@ static void ade_crtc_atomic_begin(struct\n }\n \n static void ade_crtc_atomic_flush(struct drm_crtc *crtc,\n-\t\t\t\t  struct drm_crtc_state *old_state)\n+\t\t\t\t  struct drm_atomic_state *state)\n \n {\n \tstruct kirin_crtc *kcrtc = to_kirin_crtc(crtc);\n--- a/drivers/gpu/drm/imx/dcss/dcss-crtc.c\n+++ b/drivers/gpu/drm/imx/dcss/dcss-crtc.c\n@@ -53,13 +53,13 @@ static const struct drm_crtc_funcs dcss_\n };\n \n static void dcss_crtc_atomic_begin(struct drm_crtc *crtc,\n-\t\t\t\t   struct drm_crtc_state *old_crtc_state)\n+\t\t\t\t   struct drm_atomic_state *state)\n {\n \tdrm_crtc_vblank_on(crtc);\n }\n \n static void dcss_crtc_atomic_flush(struct drm_crtc *crtc,\n-\t\t\t\t   struct drm_crtc_state *old_crtc_state)\n+\t\t\t\t   struct drm_atomic_state *state)\n {\n \tstruct dcss_crtc *dcss_crtc = container_of(crtc, struct dcss_crtc,\n \t\t\t\t\t\t   base);\n--- a/drivers/gpu/drm/imx/ipuv3-crtc.c\n+++ b/drivers/gpu/drm/imx/ipuv3-crtc.c\n@@ -240,13 +240,13 @@ static int ipu_crtc_atomic_check(struct\n }\n \n static void ipu_crtc_atomic_begin(struct drm_crtc *crtc,\n-\t\t\t\t  struct drm_crtc_state *old_crtc_state)\n+\t\t\t\t  struct drm_atomic_state *state)\n {\n \tdrm_crtc_vblank_on(crtc);\n }\n \n static void ipu_crtc_atomic_flush(struct drm_crtc *crtc,\n-\t\t\t\t  struct drm_crtc_state *old_crtc_state)\n+\t\t\t\t  struct drm_atomic_state *state)\n {\n \tspin_lock_irq(&crtc->dev->event_lock);\n \tif (crtc->state->event) {\n--- a/drivers/gpu/drm/ingenic/ingenic-drm-drv.c\n+++ b/drivers/gpu/drm/ingenic/ingenic-drm-drv.c\n@@ -253,7 +253,7 @@ ingenic_drm_crtc_mode_valid(struct drm_c\n }\n \n static void ingenic_drm_crtc_atomic_begin(struct drm_crtc *crtc,\n-\t\t\t\t\t  struct drm_crtc_state *oldstate)\n+\t\t\t\t\t  struct drm_atomic_state *state)\n {\n \tstruct ingenic_drm *priv = drm_crtc_get_priv(crtc);\n \tu32 ctrl = 0;\n@@ -273,20 +273,20 @@ static void ingenic_drm_crtc_atomic_begi\n }\n \n static void ingenic_drm_crtc_atomic_flush(struct drm_crtc *crtc,\n-\t\t\t\t\t  struct drm_crtc_state *oldstate)\n+\t\t\t\t\t  struct drm_atomic_state *state)\n {\n \tstruct ingenic_drm *priv = drm_crtc_get_priv(crtc);\n-\tstruct drm_crtc_state *state = crtc->state;\n-\tstruct drm_pending_vblank_event *event = state->event;\n+\tstruct drm_crtc_state *crtc_state = crtc->state;\n+\tstruct drm_pending_vblank_event *event = crtc_state->event;\n \n-\tif (drm_atomic_crtc_needs_modeset(state)) {\n-\t\tingenic_drm_crtc_update_timings(priv, &state->mode);\n+\tif (drm_atomic_crtc_needs_modeset(crtc_state)) {\n+\t\tingenic_drm_crtc_update_timings(priv, &crtc_state->mode);\n \n \t\tclk_set_rate(priv->pix_clk, state->adjusted_mode.clock * 1000);\n \t}\n \n \tif (event) {\n-\t\tstate->event = NULL;\n+\t\tcrtc_state->event = NULL;\n \n \t\tspin_lock_irq(&crtc->dev->event_lock);\n \t\tif (drm_crtc_vblank_get(crtc) == 0)\n--- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c\n+++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c\n@@ -575,24 +575,24 @@ static void mtk_drm_crtc_atomic_disable(\n }\n \n static void mtk_drm_crtc_atomic_begin(struct drm_crtc *crtc,\n-\t\t\t\t      struct drm_crtc_state *old_crtc_state)\n+\t\t\t\t      struct drm_atomic_state *state)\n {\n-\tstruct mtk_crtc_state *state = to_mtk_crtc_state(crtc->state);\n+\tstruct mtk_crtc_state *crtc_state = to_mtk_crtc_state(crtc->state);\n \tstruct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);\n \n-\tif (mtk_crtc->event && state->base.event)\n+\tif (mtk_crtc->event && crtc_state->base.event)\n \t\tDRM_ERROR(\"new event while there is still a pending event\\n\");\n \n-\tif (state->base.event) {\n-\t\tstate->base.event->pipe = drm_crtc_index(crtc);\n+\tif (crtc_state->base.event) {\n+\t\tcrtc_state->base.event->pipe = drm_crtc_index(crtc);\n \t\tWARN_ON(drm_crtc_vblank_get(crtc) != 0);\n-\t\tmtk_crtc->event = state->base.event;\n-\t\tstate->base.event = NULL;\n+\t\tmtk_crtc->event = crtc_state->base.event;\n+\t\tcrtc_state->base.event = NULL;\n \t}\n }\n \n static void mtk_drm_crtc_atomic_flush(struct drm_crtc *crtc,\n-\t\t\t\t      struct drm_crtc_state *old_crtc_state)\n+\t\t\t\t      struct drm_atomic_state *state)\n {\n \tstruct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);\n \tint i;\n--- a/drivers/gpu/drm/meson/meson_crtc.c\n+++ b/drivers/gpu/drm/meson/meson_crtc.c\n@@ -201,7 +201,7 @@ static void meson_crtc_atomic_disable(st\n }\n \n static void meson_crtc_atomic_begin(struct drm_crtc *crtc,\n-\t\t\t\t    struct drm_crtc_state *state)\n+\t\t\t\t    struct drm_atomic_state *state)\n {\n \tstruct meson_crtc *meson_crtc = to_meson_crtc(crtc);\n \tunsigned long flags;\n@@ -217,7 +217,7 @@ static void meson_crtc_atomic_begin(stru\n }\n \n static void meson_crtc_atomic_flush(struct drm_crtc *crtc,\n-\t\t\t\t    struct drm_crtc_state *old_crtc_state)\n+\t\t\t\t    struct drm_atomic_state *state)\n {\n \tstruct meson_crtc *meson_crtc = to_meson_crtc(crtc);\n \tstruct meson_drm *priv = meson_crtc->priv;\n--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c\n+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c\n@@ -486,7 +486,7 @@ static void _dpu_crtc_setup_cp_blocks(st\n }\n \n static void dpu_crtc_atomic_begin(struct drm_crtc *crtc,\n-\t\tstruct drm_crtc_state *old_state)\n+\t\tstruct drm_atomic_state *state)\n {\n \tstruct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc->state);\n \tstruct drm_encoder *encoder;\n@@ -527,7 +527,7 @@ static void dpu_crtc_atomic_begin(struct\n }\n \n static void dpu_crtc_atomic_flush(struct drm_crtc *crtc,\n-\t\tstruct drm_crtc_state *old_crtc_state)\n+\t\tstruct drm_atomic_state *state)\n {\n \tstruct dpu_crtc *dpu_crtc;\n \tstruct drm_device *dev;\n--- a/drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c\n+++ b/drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c\n@@ -316,14 +316,14 @@ static int mdp4_crtc_atomic_check(struct\n }\n \n static void mdp4_crtc_atomic_begin(struct drm_crtc *crtc,\n-\t\t\t\t   struct drm_crtc_state *old_crtc_state)\n+\t\t\t\t   struct drm_atomic_state *state)\n {\n \tstruct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);\n \tDBG(\"%s: begin\", mdp4_crtc->name);\n }\n \n static void mdp4_crtc_atomic_flush(struct drm_crtc *crtc,\n-\t\t\t\t   struct drm_crtc_state *old_crtc_state)\n+\t\t\t\t   struct drm_atomic_state *state)\n {\n \tstruct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);\n \tstruct drm_device *dev = crtc->dev;\n--- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c\n+++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c\n@@ -772,13 +772,13 @@ static int mdp5_crtc_atomic_check(struct\n }\n \n static void mdp5_crtc_atomic_begin(struct drm_crtc *crtc,\n-\t\t\t\t   struct drm_crtc_state *old_crtc_state)\n+\t\t\t\t   struct drm_atomic_state *state)\n {\n \tDBG(\"%s: begin\", crtc->name);\n }\n \n static void mdp5_crtc_atomic_flush(struct drm_crtc *crtc,\n-\t\t\t\t   struct drm_crtc_state *old_crtc_state)\n+\t\t\t\t   struct drm_atomic_state *state)\n {\n \tstruct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);\n \tstruct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state);\n--- a/drivers/gpu/drm/mxsfb/mxsfb_kms.c\n+++ b/drivers/gpu/drm/mxsfb/mxsfb_kms.c\n@@ -326,7 +326,7 @@ static int mxsfb_crtc_atomic_check(struc\n }\n \n static void mxsfb_crtc_atomic_flush(struct drm_crtc *crtc,\n-\t\t\t\t    struct drm_crtc_state *old_state)\n+\t\t\t\t    struct drm_atomic_state *state)\n {\n \tstruct drm_pending_vblank_event *event;\n \n--- a/drivers/gpu/drm/omapdrm/omap_crtc.c\n+++ b/drivers/gpu/drm/omapdrm/omap_crtc.c\n@@ -601,12 +601,12 @@ static int omap_crtc_atomic_check(struct\n }\n \n static void omap_crtc_atomic_begin(struct drm_crtc *crtc,\n-\t\t\t\t   struct drm_crtc_state *old_crtc_state)\n+\t\t\t\t   struct drm_atomic_state *state)\n {\n }\n \n static void omap_crtc_atomic_flush(struct drm_crtc *crtc,\n-\t\t\t\t   struct drm_crtc_state *old_crtc_state)\n+\t\t\t\t   struct drm_atomic_state *state)\n {\n \tstruct omap_drm_private *priv = crtc->dev->dev_private;\n \tstruct omap_crtc *omap_crtc = to_omap_crtc(crtc);\n--- a/drivers/gpu/drm/qxl/qxl_display.c\n+++ b/drivers/gpu/drm/qxl/qxl_display.c\n@@ -373,7 +373,7 @@ static void qxl_crtc_update_monitors_con\n }\n \n static void qxl_crtc_atomic_flush(struct drm_crtc *crtc,\n-\t\t\t\t  struct drm_crtc_state *old_crtc_state)\n+\t\t\t\t  struct drm_atomic_state *state)\n {\n \tqxl_crtc_update_monitors_config(crtc, \"flush\");\n }\n--- a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c\n+++ b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c\n@@ -785,7 +785,7 @@ static void rcar_du_crtc_atomic_disable(\n }\n \n static void rcar_du_crtc_atomic_begin(struct drm_crtc *crtc,\n-\t\t\t\t      struct drm_crtc_state *old_crtc_state)\n+\t\t\t\t      struct drm_atomic_state *state)\n {\n \tstruct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);\n \n@@ -814,7 +814,7 @@ static void rcar_du_crtc_atomic_begin(st\n }\n \n static void rcar_du_crtc_atomic_flush(struct drm_crtc *crtc,\n-\t\t\t\t      struct drm_crtc_state *old_crtc_state)\n+\t\t\t\t      struct drm_atomic_state *state)\n {\n \tstruct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);\n \tstruct drm_device *dev = rcrtc->crtc.dev;\n--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c\n+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c\n@@ -1247,8 +1247,10 @@ static void vop_crtc_gamma_set(struct vo\n }\n \n static void vop_crtc_atomic_begin(struct drm_crtc *crtc,\n-\t\t\t\t  struct drm_crtc_state *old_crtc_state)\n+\t\t\t\t  struct drm_atomic_state *state)\n {\n+\tstruct drm_crtc_state *old_crtc_state = drm_atomic_get_old_crtc_state(state,\n+\t\t\t\t\t\t\t\t\t      crtc);\n \tstruct vop *vop = to_vop(crtc);\n \n \t/*\n@@ -1463,8 +1465,10 @@ static int vop_crtc_atomic_check(struct\n }\n \n static void vop_crtc_atomic_flush(struct drm_crtc *crtc,\n-\t\t\t\t  struct drm_crtc_state *old_crtc_state)\n+\t\t\t\t  struct drm_atomic_state *state)\n {\n+\tstruct drm_crtc_state *old_crtc_state = drm_atomic_get_old_crtc_state(state,\n+\t\t\t\t\t\t\t\t\t      crtc);\n \tstruct drm_atomic_state *old_state = old_crtc_state->state;\n \tstruct drm_plane_state *old_plane_state, *new_plane_state;\n \tstruct vop *vop = to_vop(crtc);\n--- a/drivers/gpu/drm/sti/sti_crtc.c\n+++ b/drivers/gpu/drm/sti/sti_crtc.c\n@@ -133,7 +133,7 @@ sti_crtc_mode_set_nofb(struct drm_crtc *\n }\n \n static void sti_crtc_atomic_flush(struct drm_crtc *crtc,\n-\t\t\t\t  struct drm_crtc_state *old_crtc_state)\n+\t\t\t\t  struct drm_atomic_state *state)\n {\n \tstruct drm_device *drm_dev = crtc->dev;\n \tstruct sti_mixer *mixer = to_sti_mixer(crtc);\n--- a/drivers/gpu/drm/stm/ltdc.c\n+++ b/drivers/gpu/drm/stm/ltdc.c\n@@ -625,7 +625,7 @@ static void ltdc_crtc_mode_set_nofb(stru\n }\n \n static void ltdc_crtc_atomic_flush(struct drm_crtc *crtc,\n-\t\t\t\t   struct drm_crtc_state *old_crtc_state)\n+\t\t\t\t   struct drm_atomic_state *state)\n {\n \tstruct ltdc_device *ldev = crtc_to_ltdc(crtc);\n \tstruct drm_device *ddev = crtc->dev;\n--- a/drivers/gpu/drm/sun4i/sun4i_crtc.c\n+++ b/drivers/gpu/drm/sun4i/sun4i_crtc.c\n@@ -61,8 +61,10 @@ static int sun4i_crtc_atomic_check(struc\n }\n \n static void sun4i_crtc_atomic_begin(struct drm_crtc *crtc,\n-\t\t\t\t    struct drm_crtc_state *old_state)\n+\t\t\t\t    struct drm_atomic_state *state)\n {\n+\tstruct drm_crtc_state *old_state = drm_atomic_get_old_crtc_state(state,\n+\t\t\t\t\t\t\t\t\t crtc);\n \tstruct sun4i_crtc *scrtc = drm_crtc_to_sun4i_crtc(crtc);\n \tstruct drm_device *dev = crtc->dev;\n \tstruct sunxi_engine *engine = scrtc->engine;\n@@ -82,7 +84,7 @@ static void sun4i_crtc_atomic_begin(stru\n }\n \n static void sun4i_crtc_atomic_flush(struct drm_crtc *crtc,\n-\t\t\t\t    struct drm_crtc_state *old_state)\n+\t\t\t\t    struct drm_atomic_state *state)\n {\n \tstruct sun4i_crtc *scrtc = drm_crtc_to_sun4i_crtc(crtc);\n \tstruct drm_pending_vblank_event *event = crtc->state->event;\n--- a/drivers/gpu/drm/tegra/dc.c\n+++ b/drivers/gpu/drm/tegra/dc.c\n@@ -1924,7 +1924,7 @@ static void tegra_crtc_atomic_enable(str\n }\n \n static void tegra_crtc_atomic_begin(struct drm_crtc *crtc,\n-\t\t\t\t    struct drm_crtc_state *old_crtc_state)\n+\t\t\t\t    struct drm_atomic_state *state)\n {\n \tunsigned long flags;\n \n@@ -1943,17 +1943,17 @@ static void tegra_crtc_atomic_begin(stru\n }\n \n static void tegra_crtc_atomic_flush(struct drm_crtc *crtc,\n-\t\t\t\t    struct drm_crtc_state *old_crtc_state)\n+\t\t\t\t    struct drm_atomic_state *state)\n {\n-\tstruct tegra_dc_state *state = to_dc_state(crtc->state);\n+\tstruct tegra_dc_state *crtc_state = to_dc_state(crtc->state);\n \tstruct tegra_dc *dc = to_tegra_dc(crtc);\n \tu32 value;\n \n-\tvalue = state->planes << 8 | GENERAL_UPDATE;\n+\tvalue = crtc_state->planes << 8 | GENERAL_UPDATE;\n \ttegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);\n \tvalue = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);\n \n-\tvalue = state->planes | GENERAL_ACT_REQ;\n+\tvalue = crtc_state->planes | GENERAL_ACT_REQ;\n \ttegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);\n \tvalue = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);\n }\n--- a/drivers/gpu/drm/tidss/tidss_crtc.c\n+++ b/drivers/gpu/drm/tidss/tidss_crtc.c\n@@ -163,8 +163,10 @@ static void tidss_crtc_position_planes(s\n }\n \n static void tidss_crtc_atomic_flush(struct drm_crtc *crtc,\n-\t\t\t\t    struct drm_crtc_state *old_crtc_state)\n+\t\t\t\t    struct drm_atomic_state *state)\n {\n+\tstruct drm_crtc_state *old_crtc_state = drm_atomic_get_old_crtc_state(state,\n+\t\t\t\t\t\t\t\t\t      crtc);\n \tstruct tidss_crtc *tcrtc = to_tidss_crtc(crtc);\n \tstruct drm_device *ddev = crtc->dev;\n \tstruct tidss_device *tidss = to_tidss(ddev);\n--- a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c\n+++ b/drivers/gpu/drm/tilcdc/tilcdc_crtc.c\n@@ -547,7 +547,7 @@ static void tilcdc_crtc_atomic_disable(s\n }\n \n static void tilcdc_crtc_atomic_flush(struct drm_crtc *crtc,\n-\t\t\t\t     struct drm_crtc_state *old_state)\n+\t\t\t\t     struct drm_atomic_state *state)\n {\n \tif (!crtc->state->event)\n \t\treturn;\n--- a/drivers/gpu/drm/vboxvideo/vbox_mode.c\n+++ b/drivers/gpu/drm/vboxvideo/vbox_mode.c\n@@ -223,7 +223,7 @@ static void vbox_crtc_atomic_disable(str\n }\n \n static void vbox_crtc_atomic_flush(struct drm_crtc *crtc,\n-\t\t\t\t   struct drm_crtc_state *old_crtc_state)\n+\t\t\t\t   struct drm_atomic_state *state)\n {\n }\n \n--- a/drivers/gpu/drm/vc4/vc4_drv.h\n+++ b/drivers/gpu/drm/vc4/vc4_drv.h\n@@ -928,7 +928,8 @@ int vc4_hvs_get_fifo_from_output(struct\n int vc4_hvs_atomic_check(struct drm_crtc *crtc, struct drm_crtc_state *state);\n void vc4_hvs_atomic_enable(struct drm_crtc *crtc, struct drm_crtc_state *old_state);\n void vc4_hvs_atomic_disable(struct drm_crtc *crtc, struct drm_crtc_state *old_state);\n-void vc4_hvs_atomic_flush(struct drm_crtc *crtc, struct drm_crtc_state *state);\n+void vc4_hvs_atomic_flush(struct drm_crtc *crtc,\n+\t\t\t  struct drm_atomic_state *state);\n void vc4_hvs_dump_state(struct drm_device *dev);\n void vc4_hvs_unmask_underrun(struct drm_device *dev, int channel);\n void vc4_hvs_mask_underrun(struct drm_device *dev, int channel);\n--- a/drivers/gpu/drm/vc4/vc4_hvs.c\n+++ b/drivers/gpu/drm/vc4/vc4_hvs.c\n@@ -453,8 +453,10 @@ void vc4_hvs_atomic_disable(struct drm_c\n }\n \n void vc4_hvs_atomic_flush(struct drm_crtc *crtc,\n-\t\t\t  struct drm_crtc_state *old_state)\n+\t\t\t  struct drm_atomic_state *state)\n {\n+\tstruct drm_crtc_state *old_state = drm_atomic_get_old_crtc_state(state,\n+\t\t\t\t\t\t\t\t\t crtc);\n \tstruct drm_device *dev = crtc->dev;\n \tstruct vc4_dev *vc4 = to_vc4_dev(dev);\n \tstruct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);\n--- a/drivers/gpu/drm/virtio/virtgpu_display.c\n+++ b/drivers/gpu/drm/virtio/virtgpu_display.c\n@@ -117,7 +117,7 @@ static int virtio_gpu_crtc_atomic_check(\n }\n \n static void virtio_gpu_crtc_atomic_flush(struct drm_crtc *crtc,\n-\t\t\t\t\t struct drm_crtc_state *old_state)\n+\t\t\t\t\t struct drm_atomic_state *state)\n {\n \tstruct virtio_gpu_output *output = drm_crtc_to_virtio_gpu_output(crtc);\n \n--- a/drivers/gpu/drm/vkms/vkms_crtc.c\n+++ b/drivers/gpu/drm/vkms/vkms_crtc.c\n@@ -229,7 +229,7 @@ static void vkms_crtc_atomic_disable(str\n }\n \n static void vkms_crtc_atomic_begin(struct drm_crtc *crtc,\n-\t\t\t\t   struct drm_crtc_state *old_crtc_state)\n+\t\t\t\t   struct drm_atomic_state *state)\n {\n \tstruct vkms_output *vkms_output = drm_crtc_to_vkms_output(crtc);\n \n@@ -240,7 +240,7 @@ static void vkms_crtc_atomic_begin(struc\n }\n \n static void vkms_crtc_atomic_flush(struct drm_crtc *crtc,\n-\t\t\t\t   struct drm_crtc_state *old_crtc_state)\n+\t\t\t\t   struct drm_atomic_state *state)\n {\n \tstruct vkms_output *vkms_output = drm_crtc_to_vkms_output(crtc);\n \n--- a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c\n+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c\n@@ -554,13 +554,13 @@ int vmw_du_crtc_atomic_check(struct drm_\n \n \n void vmw_du_crtc_atomic_begin(struct drm_crtc *crtc,\n-\t\t\t      struct drm_crtc_state *old_crtc_state)\n+\t\t\t      struct drm_atomic_state *state)\n {\n }\n \n \n void vmw_du_crtc_atomic_flush(struct drm_crtc *crtc,\n-\t\t\t      struct drm_crtc_state *old_crtc_state)\n+\t\t\t      struct drm_atomic_state *state)\n {\n \tstruct drm_pending_vblank_event *event = crtc->state->event;\n \n--- a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.h\n+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.h\n@@ -475,9 +475,9 @@ void vmw_du_plane_unpin_surf(struct vmw_\n int vmw_du_crtc_atomic_check(struct drm_crtc *crtc,\n \t\t\t     struct drm_atomic_state *state);\n void vmw_du_crtc_atomic_begin(struct drm_crtc *crtc,\n-\t\t\t      struct drm_crtc_state *old_crtc_state);\n+\t\t\t      struct drm_atomic_state *state);\n void vmw_du_crtc_atomic_flush(struct drm_crtc *crtc,\n-\t\t\t      struct drm_crtc_state *old_crtc_state);\n+\t\t\t      struct drm_atomic_state *state);\n void vmw_du_crtc_reset(struct drm_crtc *crtc);\n struct drm_crtc_state *vmw_du_crtc_duplicate_state(struct drm_crtc *crtc);\n void vmw_du_crtc_destroy_state(struct drm_crtc *crtc,\n--- a/drivers/gpu/drm/xlnx/zynqmp_disp.c\n+++ b/drivers/gpu/drm/xlnx/zynqmp_disp.c\n@@ -1515,14 +1515,14 @@ static int zynqmp_disp_crtc_atomic_check\n \n static void\n zynqmp_disp_crtc_atomic_begin(struct drm_crtc *crtc,\n-\t\t\t      struct drm_crtc_state *old_crtc_state)\n+\t\t\t      struct drm_atomic_state *state)\n {\n \tdrm_crtc_vblank_on(crtc);\n }\n \n static void\n zynqmp_disp_crtc_atomic_flush(struct drm_crtc *crtc,\n-\t\t\t      struct drm_crtc_state *old_crtc_state)\n+\t\t\t      struct drm_atomic_state *state)\n {\n \tif (crtc->state->event) {\n \t\tstruct drm_pending_vblank_event *event;\n--- a/drivers/gpu/drm/zte/zx_vou.c\n+++ b/drivers/gpu/drm/zte/zx_vou.c\n@@ -473,7 +473,7 @@ static void zx_crtc_atomic_disable(struc\n }\n \n static void zx_crtc_atomic_flush(struct drm_crtc *crtc,\n-\t\t\t\t  struct drm_crtc_state *old_state)\n+\t\t\t\t  struct drm_atomic_state *state)\n {\n \tstruct drm_pending_vblank_event *event = crtc->state->event;\n \n--- a/include/drm/drm_modeset_helper_vtables.h\n+++ b/include/drm/drm_modeset_helper_vtables.h\n@@ -373,7 +373,7 @@ struct drm_crtc_helper_funcs {\n \t * transitional plane helpers, but it is optional.\n \t */\n \tvoid (*atomic_begin)(struct drm_crtc *crtc,\n-\t\t\t     struct drm_crtc_state *old_crtc_state);\n+\t\t\t     struct drm_atomic_state *state);\n \t/**\n \t * @atomic_flush:\n \t *\n@@ -397,7 +397,7 @@ struct drm_crtc_helper_funcs {\n \t * transitional plane helpers, but it is optional.\n \t */\n \tvoid (*atomic_flush)(struct drm_crtc *crtc,\n-\t\t\t     struct drm_crtc_state *old_crtc_state);\n+\t\t\t     struct drm_atomic_state *state);\n \n \t/**\n \t * @atomic_enable:\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0411-drm-vc4-hvs-Align-the-HVS-atomic-hooks-to-the-new-AP.patch",
    "content": "From d584fdf44b251f77cc29330d17b60be078acb440 Mon Sep 17 00:00:00 2001\nFrom: Maxime Ripard <maxime@cerno.tech>\nDate: Mon, 7 Dec 2020 16:57:11 +0100\nSubject: [PATCH] drm/vc4: hvs: Align the HVS atomic hooks to the new\n API\n\nSince the CRTC setup in vc4 is split between the PixelValves/TXP and the\nHVS, only the PV/TXP atomic hooks were updated in the previous commits, but\nit makes sense to update the HVS ones too.\n\nReviewed-by: Thomas Zimmermann <tzimmermann@suse.de>\nSigned-off-by: Maxime Ripard <maxime@cerno.tech>\n---\n drivers/gpu/drm/vc4/vc4_crtc.c | 4 +---\n drivers/gpu/drm/vc4/vc4_drv.h  | 4 ++--\n drivers/gpu/drm/vc4/vc4_hvs.c  | 8 +++++---\n drivers/gpu/drm/vc4/vc4_txp.c  | 8 ++------\n 4 files changed, 10 insertions(+), 14 deletions(-)\n\n--- a/drivers/gpu/drm/vc4/vc4_crtc.c\n+++ b/drivers/gpu/drm/vc4/vc4_crtc.c\n@@ -520,8 +520,6 @@ static void vc4_crtc_atomic_disable(stru\n static void vc4_crtc_atomic_enable(struct drm_crtc *crtc,\n \t\t\t\t   struct drm_atomic_state *state)\n {\n-\tstruct drm_crtc_state *old_state = drm_atomic_get_old_crtc_state(state,\n-\t\t\t\t\t\t\t\t\t crtc);\n \tstruct drm_device *dev = crtc->dev;\n \tstruct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);\n \tstruct drm_encoder *encoder = vc4_get_crtc_encoder(crtc);\n@@ -534,7 +532,7 @@ static void vc4_crtc_atomic_enable(struc\n \t */\n \tdrm_crtc_vblank_on(crtc);\n \n-\tvc4_hvs_atomic_enable(crtc, old_state);\n+\tvc4_hvs_atomic_enable(crtc, state);\n \n \tif (vc4_encoder->pre_crtc_configure)\n \t\tvc4_encoder->pre_crtc_configure(encoder);\n--- a/drivers/gpu/drm/vc4/vc4_drv.h\n+++ b/drivers/gpu/drm/vc4/vc4_drv.h\n@@ -926,8 +926,8 @@ extern struct platform_driver vc4_hvs_dr\n void vc4_hvs_stop_channel(struct drm_device *dev, unsigned int output);\n int vc4_hvs_get_fifo_from_output(struct drm_device *dev, unsigned int output);\n int vc4_hvs_atomic_check(struct drm_crtc *crtc, struct drm_crtc_state *state);\n-void vc4_hvs_atomic_enable(struct drm_crtc *crtc, struct drm_crtc_state *old_state);\n-void vc4_hvs_atomic_disable(struct drm_crtc *crtc, struct drm_crtc_state *old_state);\n+void vc4_hvs_atomic_enable(struct drm_crtc *crtc, struct drm_atomic_state *state);\n+void vc4_hvs_atomic_disable(struct drm_crtc *crtc, struct drm_atomic_state *state);\n void vc4_hvs_atomic_flush(struct drm_crtc *crtc,\n \t\t\t  struct drm_atomic_state *state);\n void vc4_hvs_dump_state(struct drm_device *dev);\n--- a/drivers/gpu/drm/vc4/vc4_hvs.c\n+++ b/drivers/gpu/drm/vc4/vc4_hvs.c\n@@ -430,11 +430,12 @@ static void vc4_hvs_update_dlist(struct\n }\n \n void vc4_hvs_atomic_enable(struct drm_crtc *crtc,\n-\t\t\t   struct drm_crtc_state *old_state)\n+\t\t\t   struct drm_atomic_state *state)\n {\n \tstruct drm_device *dev = crtc->dev;\n \tstruct vc4_dev *vc4 = to_vc4_dev(dev);\n-\tstruct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);\n+\tstruct drm_crtc_state *new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);\n+\tstruct vc4_crtc_state *vc4_state = to_vc4_crtc_state(new_crtc_state);\n \tstruct drm_display_mode *mode = &crtc->state->adjusted_mode;\n \tbool oneshot = vc4_state->feed_txp;\n \n@@ -443,9 +444,10 @@ void vc4_hvs_atomic_enable(struct drm_cr\n }\n \n void vc4_hvs_atomic_disable(struct drm_crtc *crtc,\n-\t\t\t    struct drm_crtc_state *old_state)\n+\t\t\t    struct drm_atomic_state *state)\n {\n \tstruct drm_device *dev = crtc->dev;\n+\tstruct drm_crtc_state *old_state = drm_atomic_get_old_crtc_state(state, crtc);\n \tstruct vc4_crtc_state *vc4_state = to_vc4_crtc_state(old_state);\n \tunsigned int chan = vc4_state->assigned_channel;\n \n--- a/drivers/gpu/drm/vc4/vc4_txp.c\n+++ b/drivers/gpu/drm/vc4/vc4_txp.c\n@@ -406,23 +406,19 @@ static int vc4_txp_atomic_check(struct d\n static void vc4_txp_atomic_enable(struct drm_crtc *crtc,\n \t\t\t\t  struct drm_atomic_state *state)\n {\n-\tstruct drm_crtc_state *old_state = drm_atomic_get_old_crtc_state(state,\n-\t\t\t\t\t\t\t\t\t crtc);\n \tdrm_crtc_vblank_on(crtc);\n-\tvc4_hvs_atomic_enable(crtc, old_state);\n+\tvc4_hvs_atomic_enable(crtc, state);\n }\n \n static void vc4_txp_atomic_disable(struct drm_crtc *crtc,\n \t\t\t\t   struct drm_atomic_state *state)\n {\n-\tstruct drm_crtc_state *old_state = drm_atomic_get_old_crtc_state(state,\n-\t\t\t\t\t\t\t\t\t crtc);\n \tstruct drm_device *dev = crtc->dev;\n \n \t/* Disable vblank irq handling before crtc is disabled. */\n \tdrm_crtc_vblank_off(crtc);\n \n-\tvc4_hvs_atomic_disable(crtc, old_state);\n+\tvc4_hvs_atomic_disable(crtc, state);\n \n \t/*\n \t * Make sure we issue a vblank event after disabling the CRTC if\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0412-drm-vc4-Pass-the-atomic-state-to-encoder-hooks.patch",
    "content": "From a7a8569adc035cf74a3b82d00ba266ac9b249a15 Mon Sep 17 00:00:00 2001\nFrom: Maxime Ripard <maxime@cerno.tech>\nDate: Tue, 15 Dec 2020 16:42:36 +0100\nSubject: [PATCH] drm/vc4: Pass the atomic state to encoder hooks\n\nWe'll need to access the connector state in our encoder setup, so let's\njust pass the whole DRM state to our private encoder hooks.\n\nAcked-by: Thomas Zimmermann <tzimmermann@suse.de>\nSigned-off-by: Maxime Ripard <maxime@cerno.tech>\n---\n drivers/gpu/drm/vc4/vc4_crtc.c | 18 ++++++++++--------\n drivers/gpu/drm/vc4/vc4_drv.h  | 10 +++++-----\n drivers/gpu/drm/vc4/vc4_hdmi.c | 15 ++++++++++-----\n 3 files changed, 25 insertions(+), 18 deletions(-)\n\n--- a/drivers/gpu/drm/vc4/vc4_crtc.c\n+++ b/drivers/gpu/drm/vc4/vc4_crtc.c\n@@ -420,7 +420,9 @@ static void require_hvs_enabled(struct d\n \t\t     SCALER_DISPCTRL_ENABLE);\n }\n \n-static int vc4_crtc_disable(struct drm_crtc *crtc, unsigned int channel)\n+static int vc4_crtc_disable(struct drm_crtc *crtc,\n+\t\t\t    struct drm_atomic_state *state,\n+\t\t\t    unsigned int channel)\n {\n \tstruct drm_encoder *encoder = vc4_get_crtc_encoder(crtc);\n \tstruct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder);\n@@ -452,13 +454,13 @@ static int vc4_crtc_disable(struct drm_c\n \tmdelay(20);\n \n \tif (vc4_encoder && vc4_encoder->post_crtc_disable)\n-\t\tvc4_encoder->post_crtc_disable(encoder);\n+\t\tvc4_encoder->post_crtc_disable(encoder, state);\n \n \tvc4_crtc_pixelvalve_reset(crtc);\n \tvc4_hvs_stop_channel(dev, channel);\n \n \tif (vc4_encoder && vc4_encoder->post_crtc_powerdown)\n-\t\tvc4_encoder->post_crtc_powerdown(encoder);\n+\t\tvc4_encoder->post_crtc_powerdown(encoder, state);\n \n \treturn 0;\n }\n@@ -485,7 +487,7 @@ int vc4_crtc_disable_at_boot(struct drm_\n \tif (channel < 0)\n \t\treturn 0;\n \n-\treturn vc4_crtc_disable(crtc, channel);\n+\treturn vc4_crtc_disable(crtc, NULL, channel);\n }\n \n static void vc4_crtc_atomic_disable(struct drm_crtc *crtc,\n@@ -501,7 +503,7 @@ static void vc4_crtc_atomic_disable(stru\n \t/* Disable vblank irq handling before crtc is disabled. */\n \tdrm_crtc_vblank_off(crtc);\n \n-\tvc4_crtc_disable(crtc, old_vc4_state->assigned_channel);\n+\tvc4_crtc_disable(crtc, state, old_vc4_state->assigned_channel);\n \n \t/*\n \t * Make sure we issue a vblank event after disabling the CRTC if\n@@ -535,14 +537,14 @@ static void vc4_crtc_atomic_enable(struc\n \tvc4_hvs_atomic_enable(crtc, state);\n \n \tif (vc4_encoder->pre_crtc_configure)\n-\t\tvc4_encoder->pre_crtc_configure(encoder);\n+\t\tvc4_encoder->pre_crtc_configure(encoder, state);\n \n \tvc4_crtc_config_pv(crtc);\n \n \tCRTC_WRITE(PV_CONTROL, CRTC_READ(PV_CONTROL) | PV_CONTROL_EN);\n \n \tif (vc4_encoder->pre_crtc_enable)\n-\t\tvc4_encoder->pre_crtc_enable(encoder);\n+\t\tvc4_encoder->pre_crtc_enable(encoder, state);\n \n \t/* When feeding the transposer block the pixelvalve is unneeded and\n \t * should not be enabled.\n@@ -551,7 +553,7 @@ static void vc4_crtc_atomic_enable(struc\n \t\t   CRTC_READ(PV_V_CONTROL) | PV_VCONTROL_VIDEN);\n \n \tif (vc4_encoder->post_crtc_enable)\n-\t\tvc4_encoder->post_crtc_enable(encoder);\n+\t\tvc4_encoder->post_crtc_enable(encoder, state);\n }\n \n static enum drm_mode_status vc4_crtc_mode_valid(struct drm_crtc *crtc,\n--- a/drivers/gpu/drm/vc4/vc4_drv.h\n+++ b/drivers/gpu/drm/vc4/vc4_drv.h\n@@ -449,12 +449,12 @@ struct vc4_encoder {\n \tenum vc4_encoder_type type;\n \tu32 clock_select;\n \n-\tvoid (*pre_crtc_configure)(struct drm_encoder *encoder);\n-\tvoid (*pre_crtc_enable)(struct drm_encoder *encoder);\n-\tvoid (*post_crtc_enable)(struct drm_encoder *encoder);\n+\tvoid (*pre_crtc_configure)(struct drm_encoder *encoder, struct drm_atomic_state *state);\n+\tvoid (*pre_crtc_enable)(struct drm_encoder *encoder, struct drm_atomic_state *state);\n+\tvoid (*post_crtc_enable)(struct drm_encoder *encoder, struct drm_atomic_state *state);\n \n-\tvoid (*post_crtc_disable)(struct drm_encoder *encoder);\n-\tvoid (*post_crtc_powerdown)(struct drm_encoder *encoder);\n+\tvoid (*post_crtc_disable)(struct drm_encoder *encoder, struct drm_atomic_state *state);\n+\tvoid (*post_crtc_powerdown)(struct drm_encoder *encoder, struct drm_atomic_state *state);\n };\n \n static inline struct vc4_encoder *\n--- a/drivers/gpu/drm/vc4/vc4_hdmi.c\n+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c\n@@ -412,7 +412,8 @@ static void vc4_hdmi_set_infoframes(stru\n \t\tvc4_hdmi_set_audio_infoframe(encoder);\n }\n \n-static void vc4_hdmi_encoder_post_crtc_disable(struct drm_encoder *encoder)\n+static void vc4_hdmi_encoder_post_crtc_disable(struct drm_encoder *encoder,\n+\t\t\t\t\t       struct drm_atomic_state *state)\n {\n \tstruct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);\n \n@@ -425,7 +426,8 @@ static void vc4_hdmi_encoder_post_crtc_d\n \t\t   HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_BLANKPIX);\n }\n \n-static void vc4_hdmi_encoder_post_crtc_powerdown(struct drm_encoder *encoder)\n+static void vc4_hdmi_encoder_post_crtc_powerdown(struct drm_encoder *encoder,\n+\t\t\t\t\t\t struct drm_atomic_state *state)\n {\n \tstruct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);\n \tint ret;\n@@ -638,7 +640,8 @@ static void vc4_hdmi_recenter_fifo(struc\n \t\t  \"VC4_HDMI_FIFO_CTL_RECENTER_DONE\");\n }\n \n-static void vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder *encoder)\n+static void vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder *encoder,\n+\t\t\t\t\t\tstruct drm_atomic_state *state)\n {\n \tstruct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;\n \tstruct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);\n@@ -720,7 +723,8 @@ static void vc4_hdmi_encoder_pre_crtc_co\n \t\tvc4_hdmi->variant->set_timings(vc4_hdmi, mode);\n }\n \n-static void vc4_hdmi_encoder_pre_crtc_enable(struct drm_encoder *encoder)\n+static void vc4_hdmi_encoder_pre_crtc_enable(struct drm_encoder *encoder,\n+\t\t\t\t\t     struct drm_atomic_state *state)\n {\n \tstruct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;\n \tstruct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);\n@@ -742,7 +746,8 @@ static void vc4_hdmi_encoder_pre_crtc_en\n \tHDMI_WRITE(HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N);\n }\n \n-static void vc4_hdmi_encoder_post_crtc_enable(struct drm_encoder *encoder)\n+static void vc4_hdmi_encoder_post_crtc_enable(struct drm_encoder *encoder,\n+\t\t\t\t\t      struct drm_atomic_state *state)\n {\n \tstruct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;\n \tstruct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0413-drm-vc4-hdmi-Don-t-access-the-connector-state-in-res.patch",
    "content": "From e1b4f5c3970e14abe197f328077b348b4969e68f Mon Sep 17 00:00:00 2001\nFrom: Maxime Ripard <maxime@cerno.tech>\nDate: Tue, 15 Dec 2020 16:42:38 +0100\nSubject: [PATCH] drm/vc4: hdmi: Don't access the connector state in\n reset if kmalloc fails\n\ndrm_atomic_helper_connector_reset uses kmalloc which, from an API\nstandpoint, can fail, and thus setting connector->state to NULL.\nHowever, our reset hook then calls drm_atomic_helper_connector_tv_reset\nthat will access connector->state without checking if it's a valid\npointer or not.\n\nMake sure we don't end up accessing a NULL pointer.\n\nAcked-by: Thomas Zimmermann <tzimmermann@suse.de>\nReviewed-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\nSuggested-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\nSigned-off-by: Maxime Ripard <maxime@cerno.tech>\n---\n drivers/gpu/drm/vc4/vc4_hdmi.c | 4 +++-\n 1 file changed, 3 insertions(+), 1 deletion(-)\n\n--- a/drivers/gpu/drm/vc4/vc4_hdmi.c\n+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c\n@@ -216,7 +216,9 @@ static int vc4_hdmi_connector_get_modes(\n static void vc4_hdmi_connector_reset(struct drm_connector *connector)\n {\n \tdrm_atomic_helper_connector_reset(connector);\n-\tdrm_atomic_helper_connector_tv_reset(connector);\n+\n+\tif (connector->state)\n+\t\tdrm_atomic_helper_connector_tv_reset(connector);\n }\n \n static const struct drm_connector_funcs vc4_hdmi_connector_funcs = {\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0414-drm-vc4-hdmi-Create-a-custom-connector-state.patch",
    "content": "From e072b2d845ff91716d630f4d2a105bf63698cfe1 Mon Sep 17 00:00:00 2001\nFrom: Maxime Ripard <maxime@cerno.tech>\nDate: Tue, 15 Dec 2020 16:42:39 +0100\nSubject: [PATCH] drm/vc4: hdmi: Create a custom connector state\n\nWhen run with a higher bpc than 8, the clock of the HDMI controller needs\nto be adjusted. Let's create a connector state that will be used at\natomic_check and atomic_enable to compute and store the clock rate\nassociated to the state.\n\nAcked-by: Thomas Zimmermann <tzimmermann@suse.de>\nSigned-off-by: Maxime Ripard <maxime@cerno.tech>\nReviewed-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n drivers/gpu/drm/vc4/vc4_hdmi.c | 33 ++++++++++++++++++++++++++++++---\n drivers/gpu/drm/vc4/vc4_hdmi.h | 10 ++++++++++\n 2 files changed, 40 insertions(+), 3 deletions(-)\n\n--- a/drivers/gpu/drm/vc4/vc4_hdmi.c\n+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c\n@@ -215,10 +215,37 @@ static int vc4_hdmi_connector_get_modes(\n \n static void vc4_hdmi_connector_reset(struct drm_connector *connector)\n {\n-\tdrm_atomic_helper_connector_reset(connector);\n+\tstruct vc4_hdmi_connector_state *old_state =\n+\t\tconn_state_to_vc4_hdmi_conn_state(connector->state);\n+\tstruct vc4_hdmi_connector_state *new_state =\n+\t\tkzalloc(sizeof(*new_state), GFP_KERNEL);\n \n \tif (connector->state)\n-\t\tdrm_atomic_helper_connector_tv_reset(connector);\n+\t\t__drm_atomic_helper_connector_destroy_state(connector->state);\n+\n+\tkfree(old_state);\n+\t__drm_atomic_helper_connector_reset(connector, &new_state->base);\n+\n+\tif (!new_state)\n+\t\treturn;\n+\n+\tdrm_atomic_helper_connector_tv_reset(connector);\n+}\n+\n+static struct drm_connector_state *\n+vc4_hdmi_connector_duplicate_state(struct drm_connector *connector)\n+{\n+\tstruct drm_connector_state *conn_state = connector->state;\n+\tstruct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state);\n+\tstruct vc4_hdmi_connector_state *new_state;\n+\n+\tnew_state = kzalloc(sizeof(*new_state), GFP_KERNEL);\n+\tif (!new_state)\n+\t\treturn NULL;\n+\n+\t__drm_atomic_helper_connector_duplicate_state(connector, &new_state->base);\n+\n+\treturn &new_state->base;\n }\n \n static const struct drm_connector_funcs vc4_hdmi_connector_funcs = {\n@@ -226,7 +253,7 @@ static const struct drm_connector_funcs\n \t.fill_modes = drm_helper_probe_single_connector_modes,\n \t.destroy = vc4_hdmi_connector_destroy,\n \t.reset = vc4_hdmi_connector_reset,\n-\t.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,\n+\t.atomic_duplicate_state = vc4_hdmi_connector_duplicate_state,\n \t.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,\n };\n \n--- a/drivers/gpu/drm/vc4/vc4_hdmi.h\n+++ b/drivers/gpu/drm/vc4/vc4_hdmi.h\n@@ -187,6 +187,16 @@ encoder_to_vc4_hdmi(struct drm_encoder *\n \treturn container_of(_encoder, struct vc4_hdmi, encoder);\n }\n \n+struct vc4_hdmi_connector_state {\n+\tstruct drm_connector_state\tbase;\n+};\n+\n+static inline struct vc4_hdmi_connector_state *\n+conn_state_to_vc4_hdmi_conn_state(struct drm_connector_state *conn_state)\n+{\n+\treturn container_of(conn_state, struct vc4_hdmi_connector_state, base);\n+}\n+\n void vc4_hdmi_phy_init(struct vc4_hdmi *vc4_hdmi,\n \t\t       struct drm_display_mode *mode);\n void vc4_hdmi_phy_disable(struct vc4_hdmi *vc4_hdmi);\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0415-drm-vc4-hdmi-Store-pixel-frequency-in-the-connector-.patch",
    "content": "From 1dd22d945a99fa35e387e01101c758ae7be3d9a4 Mon Sep 17 00:00:00 2001\nFrom: Maxime Ripard <maxime@cerno.tech>\nDate: Tue, 15 Dec 2020 16:42:40 +0100\nSubject: [PATCH] drm/vc4: hdmi: Store pixel frequency in the connector\n state\n\nThe pixel rate is for now quite simple to compute, but with more features\n(30 and 36 bits output, YUV output, etc.) will depend on a bunch of\nconnectors properties.\n\nLet's store the rate we have to run the pixel clock at in our custom\nconnector state, and compute it in atomic_check.\n\nAcked-by: Thomas Zimmermann <tzimmermann@suse.de>\nReviewed-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\nSigned-off-by: Maxime Ripard <maxime@cerno.tech>\n---\n drivers/gpu/drm/vc4/vc4_hdmi.c | 26 +++++++++++++++++++++++++-\n drivers/gpu/drm/vc4/vc4_hdmi.h |  1 +\n 2 files changed, 26 insertions(+), 1 deletion(-)\n\n--- a/drivers/gpu/drm/vc4/vc4_hdmi.c\n+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c\n@@ -243,6 +243,7 @@ vc4_hdmi_connector_duplicate_state(struc\n \tif (!new_state)\n \t\treturn NULL;\n \n+\tnew_state->pixel_rate = vc4_state->pixel_rate;\n \t__drm_atomic_helper_connector_duplicate_state(connector, &new_state->base);\n \n \treturn &new_state->base;\n@@ -669,9 +670,29 @@ static void vc4_hdmi_recenter_fifo(struc\n \t\t  \"VC4_HDMI_FIFO_CTL_RECENTER_DONE\");\n }\n \n+static struct drm_connector_state *\n+vc4_hdmi_encoder_get_connector_state(struct drm_encoder *encoder,\n+\t\t\t\t     struct drm_atomic_state *state)\n+{\n+\tstruct drm_connector_state *conn_state;\n+\tstruct drm_connector *connector;\n+\tunsigned int i;\n+\n+\tfor_each_new_connector_in_state(state, connector, conn_state, i) {\n+\t\tif (conn_state->best_encoder == encoder)\n+\t\t\treturn conn_state;\n+\t}\n+\n+\treturn NULL;\n+}\n+\n static void vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder *encoder,\n \t\t\t\t\t\tstruct drm_atomic_state *state)\n {\n+\tstruct drm_connector_state *conn_state =\n+\t\tvc4_hdmi_encoder_get_connector_state(encoder, state);\n+\tstruct vc4_hdmi_connector_state *vc4_conn_state =\n+\t\tconn_state_to_vc4_hdmi_conn_state(conn_state);\n \tstruct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;\n \tstruct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);\n \tunsigned long pixel_rate, hsm_rate;\n@@ -683,7 +704,7 @@ static void vc4_hdmi_encoder_pre_crtc_co\n \t\treturn;\n \t}\n \n-\tpixel_rate = mode->clock * 1000 * ((mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1);\n+\tpixel_rate = vc4_conn_state->pixel_rate;\n \tret = clk_set_rate(vc4_hdmi->pixel_clock, pixel_rate);\n \tif (ret) {\n \t\tDRM_ERROR(\"Failed to set pixel clock rate: %d\\n\", ret);\n@@ -845,6 +866,7 @@ static int vc4_hdmi_encoder_atomic_check\n \t\t\t\t\t struct drm_crtc_state *crtc_state,\n \t\t\t\t\t struct drm_connector_state *conn_state)\n {\n+\tstruct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state);\n \tstruct drm_display_mode *mode = &crtc_state->adjusted_mode;\n \tstruct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);\n \tunsigned long long pixel_rate = mode->clock * 1000;\n@@ -876,6 +898,8 @@ static int vc4_hdmi_encoder_atomic_check\n \tif (pixel_rate > vc4_hdmi->variant->max_pixel_clock)\n \t\treturn -EINVAL;\n \n+\tvc4_state->pixel_rate = pixel_rate;\n+\n \treturn 0;\n }\n \n--- a/drivers/gpu/drm/vc4/vc4_hdmi.h\n+++ b/drivers/gpu/drm/vc4/vc4_hdmi.h\n@@ -189,6 +189,7 @@ encoder_to_vc4_hdmi(struct drm_encoder *\n \n struct vc4_hdmi_connector_state {\n \tstruct drm_connector_state\tbase;\n+\tunsigned long long\t\tpixel_rate;\n };\n \n static inline struct vc4_hdmi_connector_state *\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0416-drm-vc4-hdmi-Use-the-connector-state-pixel-rate-for-.patch",
    "content": "From 6d15419acb9914041e90bc88044d87bbcdcfec00 Mon Sep 17 00:00:00 2001\nFrom: Maxime Ripard <maxime@cerno.tech>\nDate: Tue, 15 Dec 2020 16:42:41 +0100\nSubject: [PATCH] drm/vc4: hdmi: Use the connector state pixel rate for\n the PHY\n\nThe PHY initialisation parameters are not based on the pixel clock but\nthe TMDS clock rate which can be the pixel clock in the standard case,\nbut could be adjusted based on some parameters like the bits per color.\n\nSince the TMDS clock rate is stored in our custom connector state\nalready, let's reuse it from there instead of computing it again.\n\nAcked-by: Thomas Zimmermann <tzimmermann@suse.de>\nReviewed-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\nSigned-off-by: Maxime Ripard <maxime@cerno.tech>\n---\n drivers/gpu/drm/vc4/vc4_hdmi.c     |  2 +-\n drivers/gpu/drm/vc4/vc4_hdmi.h     | 11 +++++------\n drivers/gpu/drm/vc4/vc4_hdmi_phy.c |  8 +++++---\n 3 files changed, 11 insertions(+), 10 deletions(-)\n\n--- a/drivers/gpu/drm/vc4/vc4_hdmi.c\n+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c\n@@ -762,7 +762,7 @@ static void vc4_hdmi_encoder_pre_crtc_co\n \t}\n \n \tif (vc4_hdmi->variant->phy_init)\n-\t\tvc4_hdmi->variant->phy_init(vc4_hdmi, mode);\n+\t\tvc4_hdmi->variant->phy_init(vc4_hdmi, vc4_conn_state);\n \n \tHDMI_WRITE(HDMI_SCHEDULER_CONTROL,\n \t\t   HDMI_READ(HDMI_SCHEDULER_CONTROL) |\n--- a/drivers/gpu/drm/vc4/vc4_hdmi.h\n+++ b/drivers/gpu/drm/vc4/vc4_hdmi.h\n@@ -21,10 +21,9 @@ to_vc4_hdmi_encoder(struct drm_encoder *\n \treturn container_of(encoder, struct vc4_hdmi_encoder, base.base);\n }\n \n-struct drm_display_mode;\n-\n struct vc4_hdmi;\n struct vc4_hdmi_register;\n+struct vc4_hdmi_connector_state;\n \n enum vc4_hdmi_phy_channel {\n \tPHY_LANE_0 = 0,\n@@ -77,9 +76,9 @@ struct vc4_hdmi_variant {\n \tvoid (*set_timings)(struct vc4_hdmi *vc4_hdmi,\n \t\t\t    struct drm_display_mode *mode);\n \n-\t/* Callback to initialize the PHY according to the mode */\n+\t/* Callback to initialize the PHY according to the connector state */\n \tvoid (*phy_init)(struct vc4_hdmi *vc4_hdmi,\n-\t\t\t struct drm_display_mode *mode);\n+\t\t\t struct vc4_hdmi_connector_state *vc4_conn_state);\n \n \t/* Callback to disable the PHY */\n \tvoid (*phy_disable)(struct vc4_hdmi *vc4_hdmi);\n@@ -199,13 +198,13 @@ conn_state_to_vc4_hdmi_conn_state(struct\n }\n \n void vc4_hdmi_phy_init(struct vc4_hdmi *vc4_hdmi,\n-\t\t       struct drm_display_mode *mode);\n+\t\t       struct vc4_hdmi_connector_state *vc4_conn_state);\n void vc4_hdmi_phy_disable(struct vc4_hdmi *vc4_hdmi);\n void vc4_hdmi_phy_rng_enable(struct vc4_hdmi *vc4_hdmi);\n void vc4_hdmi_phy_rng_disable(struct vc4_hdmi *vc4_hdmi);\n \n void vc5_hdmi_phy_init(struct vc4_hdmi *vc4_hdmi,\n-\t\t       struct drm_display_mode *mode);\n+\t\t       struct vc4_hdmi_connector_state *vc4_conn_state);\n void vc5_hdmi_phy_disable(struct vc4_hdmi *vc4_hdmi);\n void vc5_hdmi_phy_rng_enable(struct vc4_hdmi *vc4_hdmi);\n void vc5_hdmi_phy_rng_disable(struct vc4_hdmi *vc4_hdmi);\n--- a/drivers/gpu/drm/vc4/vc4_hdmi_phy.c\n+++ b/drivers/gpu/drm/vc4/vc4_hdmi_phy.c\n@@ -127,7 +127,8 @@\n \n #define OSCILLATOR_FREQUENCY\t54000000\n \n-void vc4_hdmi_phy_init(struct vc4_hdmi *vc4_hdmi, struct drm_display_mode *mode)\n+void vc4_hdmi_phy_init(struct vc4_hdmi *vc4_hdmi,\n+\t\t       struct vc4_hdmi_connector_state *conn_state)\n {\n \t/* PHY should be in reset, like\n \t * vc4_hdmi_encoder_disable() does.\n@@ -339,11 +340,12 @@ static void vc5_hdmi_reset_phy(struct vc\n \tHDMI_WRITE(HDMI_TX_PHY_POWERDOWN_CTL, BIT(10));\n }\n \n-void vc5_hdmi_phy_init(struct vc4_hdmi *vc4_hdmi, struct drm_display_mode *mode)\n+void vc5_hdmi_phy_init(struct vc4_hdmi *vc4_hdmi,\n+\t\t       struct vc4_hdmi_connector_state *conn_state)\n {\n \tconst struct phy_lane_settings *chan0_settings, *chan1_settings, *chan2_settings, *clock_settings;\n \tconst struct vc4_hdmi_variant *variant = vc4_hdmi->variant;\n-\tunsigned long long pixel_freq = mode->clock * 1000;\n+\tunsigned long long pixel_freq = conn_state->pixel_rate;\n \tunsigned long long vco_freq;\n \tunsigned char word_sel;\n \tu8 vco_sel, vco_div;\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0417-drm-vc4-hdmi-Enable-10-12-bpc-output.patch",
    "content": "From 72a998c1462527c2d61c2f9a38525c99da442fb4 Mon Sep 17 00:00:00 2001\nFrom: Maxime Ripard <maxime@cerno.tech>\nDate: Tue, 15 Dec 2020 16:42:43 +0100\nSubject: [PATCH] drm/vc4: hdmi: Enable 10/12 bpc output\n\nThe BCM2711 supports higher bpc count than just 8, so let's support it in\nour driver.\n\nSigned-off-by: Maxime Ripard <maxime@cerno.tech>\nReviewed-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n drivers/gpu/drm/vc4/vc4_hdmi.c      | 70 ++++++++++++++++++++++++++++-\n drivers/gpu/drm/vc4/vc4_hdmi.h      |  1 +\n drivers/gpu/drm/vc4/vc4_hdmi_regs.h |  9 ++++\n 3 files changed, 79 insertions(+), 1 deletion(-)\n\n--- a/drivers/gpu/drm/vc4/vc4_hdmi.c\n+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c\n@@ -77,6 +77,17 @@\n #define VC5_HDMI_VERTB_VSPO_SHIFT\t\t16\n #define VC5_HDMI_VERTB_VSPO_MASK\t\tVC4_MASK(29, 16)\n \n+#define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_SHIFT\t8\n+#define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK\tVC4_MASK(10, 8)\n+\n+#define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_SHIFT\t\t0\n+#define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK\t\tVC4_MASK(3, 0)\n+\n+#define VC5_HDMI_GCP_CONFIG_GCP_ENABLE\t\tBIT(31)\n+\n+#define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_SHIFT\t8\n+#define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK\tVC4_MASK(15, 8)\n+\n # define VC4_HD_M_SW_RST\t\t\tBIT(2)\n # define VC4_HD_M_ENABLE\t\t\tBIT(0)\n \n@@ -229,6 +240,8 @@ static void vc4_hdmi_connector_reset(str\n \tif (!new_state)\n \t\treturn;\n \n+\tnew_state->base.max_bpc = 8;\n+\tnew_state->base.max_requested_bpc = 8;\n \tdrm_atomic_helper_connector_tv_reset(connector);\n }\n \n@@ -275,12 +288,20 @@ static int vc4_hdmi_connector_init(struc\n \t\t\t\t    vc4_hdmi->ddc);\n \tdrm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs);\n \n+\t/*\n+\t * Some of the properties below require access to state, like bpc.\n+\t * Allocate some default initial connector state with our reset helper.\n+\t */\n+\tif (connector->funcs->reset)\n+\t\tconnector->funcs->reset(connector);\n+\n \t/* Create and attach TV margin props to this connector. */\n \tret = drm_mode_create_tv_margin_properties(dev);\n \tif (ret)\n \t\treturn ret;\n \n \tdrm_connector_attach_tv_margin_properties(connector);\n+\tdrm_connector_attach_max_bpc_property(connector, 8, 12);\n \n \tconnector->polled = (DRM_CONNECTOR_POLL_CONNECT |\n \t\t\t     DRM_CONNECTOR_POLL_DISCONNECT);\n@@ -555,6 +576,7 @@ static void vc5_hdmi_csc_setup(struct vc\n }\n \n static void vc4_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,\n+\t\t\t\t struct drm_connector_state *state,\n \t\t\t\t struct drm_display_mode *mode)\n {\n \tbool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;\n@@ -598,7 +620,9 @@ static void vc4_hdmi_set_timings(struct\n \tHDMI_WRITE(HDMI_VERTB0, vertb_even);\n \tHDMI_WRITE(HDMI_VERTB1, vertb);\n }\n+\n static void vc5_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,\n+\t\t\t\t struct drm_connector_state *state,\n \t\t\t\t struct drm_display_mode *mode)\n {\n \tbool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;\n@@ -618,6 +642,9 @@ static void vc5_hdmi_set_timings(struct\n \t\t\t\t\tmode->crtc_vsync_end -\n \t\t\t\t\tinterlaced,\n \t\t\t\t\tVC4_HDMI_VERTB_VBP));\n+\tunsigned char gcp;\n+\tbool gcp_en;\n+\tu32 reg;\n \n \tHDMI_WRITE(HDMI_VEC_INTERFACE_XBAR, 0x354021);\n \tHDMI_WRITE(HDMI_HORZA,\n@@ -643,6 +670,39 @@ static void vc5_hdmi_set_timings(struct\n \tHDMI_WRITE(HDMI_VERTB0, vertb_even);\n \tHDMI_WRITE(HDMI_VERTB1, vertb);\n \n+\tswitch (state->max_bpc) {\n+\tcase 12:\n+\t\tgcp = 6;\n+\t\tgcp_en = true;\n+\t\tbreak;\n+\tcase 10:\n+\t\tgcp = 5;\n+\t\tgcp_en = true;\n+\t\tbreak;\n+\tcase 8:\n+\tdefault:\n+\t\tgcp = 4;\n+\t\tgcp_en = false;\n+\t\tbreak;\n+\t}\n+\n+\treg = HDMI_READ(HDMI_DEEP_COLOR_CONFIG_1);\n+\treg &= ~(VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK |\n+\t\t VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK);\n+\treg |= VC4_SET_FIELD(2, VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE) |\n+\t       VC4_SET_FIELD(gcp, VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH);\n+\tHDMI_WRITE(HDMI_DEEP_COLOR_CONFIG_1, reg);\n+\n+\treg = HDMI_READ(HDMI_GCP_WORD_1);\n+\treg &= ~VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK;\n+\treg |= VC4_SET_FIELD(gcp, VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1);\n+\tHDMI_WRITE(HDMI_GCP_WORD_1, reg);\n+\n+\treg = HDMI_READ(HDMI_GCP_CONFIG);\n+\treg &= ~VC5_HDMI_GCP_CONFIG_GCP_ENABLE;\n+\treg |= gcp_en ? VC5_HDMI_GCP_CONFIG_GCP_ENABLE : 0;\n+\tHDMI_WRITE(HDMI_GCP_CONFIG, reg);\n+\n \tHDMI_WRITE(HDMI_CLOCK_STOP, 0);\n }\n \n@@ -770,7 +830,7 @@ static void vc4_hdmi_encoder_pre_crtc_co\n \t\t   VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS);\n \n \tif (vc4_hdmi->variant->set_timings)\n-\t\tvc4_hdmi->variant->set_timings(vc4_hdmi, mode);\n+\t\tvc4_hdmi->variant->set_timings(vc4_hdmi, conn_state, mode);\n }\n \n static void vc4_hdmi_encoder_pre_crtc_enable(struct drm_encoder *encoder,\n@@ -892,6 +952,14 @@ static int vc4_hdmi_encoder_atomic_check\n \t\tpixel_rate = mode->clock * 1000;\n \t}\n \n+\tif (conn_state->max_bpc == 12) {\n+\t\tpixel_rate = pixel_rate * 150;\n+\t\tdo_div(pixel_rate, 100);\n+\t} else if (conn_state->max_bpc == 10) {\n+\t\tpixel_rate = pixel_rate * 125;\n+\t\tdo_div(pixel_rate, 100);\n+\t}\n+\n \tif (mode->flags & DRM_MODE_FLAG_DBLCLK)\n \t\tpixel_rate = pixel_rate * 2;\n \n--- a/drivers/gpu/drm/vc4/vc4_hdmi.h\n+++ b/drivers/gpu/drm/vc4/vc4_hdmi.h\n@@ -74,6 +74,7 @@ struct vc4_hdmi_variant {\n \n \t/* Callback to configure the video timings in the HDMI block */\n \tvoid (*set_timings)(struct vc4_hdmi *vc4_hdmi,\n+\t\t\t    struct drm_connector_state *state,\n \t\t\t    struct drm_display_mode *mode);\n \n \t/* Callback to initialize the PHY according to the connector state */\n--- a/drivers/gpu/drm/vc4/vc4_hdmi_regs.h\n+++ b/drivers/gpu/drm/vc4/vc4_hdmi_regs.h\n@@ -60,9 +60,12 @@ enum vc4_hdmi_field {\n \t */\n \tHDMI_CTS_0,\n \tHDMI_CTS_1,\n+\tHDMI_DEEP_COLOR_CONFIG_1,\n \tHDMI_DVP_CTL,\n \tHDMI_FIFO_CTL,\n \tHDMI_FRAME_COUNT,\n+\tHDMI_GCP_CONFIG,\n+\tHDMI_GCP_WORD_1,\n \tHDMI_HORZA,\n \tHDMI_HORZB,\n \tHDMI_HOTPLUG,\n@@ -231,6 +234,9 @@ static const struct vc4_hdmi_register vc\n \tVC4_HDMI_REG(HDMI_VERTB1, 0x0f8),\n \tVC4_HDMI_REG(HDMI_MAI_CHANNEL_MAP, 0x09c),\n \tVC4_HDMI_REG(HDMI_MAI_CONFIG, 0x0a0),\n+\tVC4_HDMI_REG(HDMI_DEEP_COLOR_CONFIG_1, 0x170),\n+\tVC4_HDMI_REG(HDMI_GCP_CONFIG, 0x178),\n+\tVC4_HDMI_REG(HDMI_GCP_WORD_1, 0x17c),\n \tVC4_HDMI_REG(HDMI_HOTPLUG, 0x1a8),\n \n \tVC5_DVP_REG(HDMI_CLOCK_STOP, 0x0bc),\n@@ -307,6 +313,9 @@ static const struct vc4_hdmi_register vc\n \tVC4_HDMI_REG(HDMI_VERTB1, 0x0f8),\n \tVC4_HDMI_REG(HDMI_MAI_CHANNEL_MAP, 0x09c),\n \tVC4_HDMI_REG(HDMI_MAI_CONFIG, 0x0a0),\n+\tVC4_HDMI_REG(HDMI_DEEP_COLOR_CONFIG_1, 0x170),\n+\tVC4_HDMI_REG(HDMI_GCP_CONFIG, 0x178),\n+\tVC4_HDMI_REG(HDMI_GCP_WORD_1, 0x17c),\n \tVC4_HDMI_REG(HDMI_HOTPLUG, 0x1a8),\n \n \tVC5_DVP_REG(HDMI_CLOCK_STOP, 0x0bc),\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0418-drm-vc4-Fixup-fkms-for-API-change.patch",
    "content": "From 3adbeebf1fb33937d8b5ef52103b7721621c57b1 Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Tue, 1 Dec 2020 14:57:41 +0000\nSubject: [PATCH] drm/vc4: Fixup fkms for API change\n\nAtomic flush and check changed API, so fix up the downstream-only\nFKMS driver.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n drivers/gpu/drm/vc4/vc4_firmware_kms.c | 13 +++++++++----\n 1 file changed, 9 insertions(+), 4 deletions(-)\n\n--- a/drivers/gpu/drm/vc4/vc4_firmware_kms.c\n+++ b/drivers/gpu/drm/vc4/vc4_firmware_kms.c\n@@ -1107,16 +1107,18 @@ vc4_crtc_mode_valid(struct drm_crtc *crt\n }\n \n static int vc4_crtc_atomic_check(struct drm_crtc *crtc,\n-\t\t\t\t struct drm_crtc_state *state)\n+\t\t\t\t struct drm_atomic_state *state)\n {\n-\tstruct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);\n+\tstruct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,\n+\t\t\t\t\t\t\t\t\t  crtc);\n+\tstruct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc_state);\n \tstruct drm_connector *conn;\n \tstruct drm_connector_state *conn_state;\n \tint i;\n \n \tDRM_DEBUG_KMS(\"[CRTC:%d] crtc_atomic_check.\\n\", crtc->base.id);\n \n-\tfor_each_new_connector_in_state(state->state, conn, conn_state, i) {\n+\tfor_each_new_connector_in_state(crtc_state->state, conn, conn_state, i) {\n \t\tif (conn_state->crtc != crtc)\n \t\t\tcontinue;\n \n@@ -1130,8 +1132,11 @@ static int vc4_crtc_atomic_check(struct\n }\n \n static void vc4_crtc_atomic_flush(struct drm_crtc *crtc,\n-\t\t\t\t  struct drm_crtc_state *old_state)\n+\t\t\t\t  struct drm_atomic_state *state)\n {\n+\tstruct drm_crtc_state *old_state = drm_atomic_get_old_crtc_state(state,\n+\t\t\t\t\t\t\t\t\t crtc);\n+\n \tDRM_DEBUG_KMS(\"[CRTC:%d] crtc_atomic_flush.\\n\",\n \t\t      crtc->base.id);\n \tif (crtc->state->active && old_state->active && crtc->state->event)\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0419-overlays-Rebuild-upstream-with-latest-ovmerge.patch",
    "content": "From 9deb443820a6cbcc39446928bab722a2a6c1f72a Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.com>\nDate: Wed, 30 Dec 2020 20:00:38 +0000\nSubject: [PATCH] overlays: Rebuild \"upstream\" with latest ovmerge\n\nThe latest ovmerge drops disabled fragments, causing the \"upstream\"\noverlay to change.\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.com>\n---\n .../boot/dts/overlays/upstream-overlay.dts    | 38 ++++-------\n .../dts/overlays/upstream-pi4-overlay.dts     | 66 +++++--------------\n 2 files changed, 31 insertions(+), 73 deletions(-)\n\n--- a/arch/arm/boot/dts/overlays/upstream-overlay.dts\n+++ b/arch/arm/boot/dts/overlays/upstream-overlay.dts\n@@ -8,96 +8,84 @@\n / {\n \tcompatible = \"brcm,bcm2835\";\n \tfragment@0 {\n-\t\ttarget = <&cma>;\n-\t\t__dormant__ {\n-\t\t\tsize = <0x10000000>;\n-\t\t};\n-\t};\n-\tfragment@1 {\n \t\ttarget = <&i2c2>;\n \t\t__overlay__ {\n \t\t\tstatus = \"okay\";\n \t\t};\n \t};\n-\tfragment@2 {\n+\tfragment@1 {\n \t\ttarget = <&fb>;\n \t\t__overlay__ {\n \t\t\tstatus = \"disabled\";\n \t\t};\n \t};\n-\tfragment@3 {\n+\tfragment@2 {\n \t\ttarget = <&pixelvalve0>;\n \t\t__overlay__ {\n \t\t\tstatus = \"okay\";\n \t\t};\n \t};\n-\tfragment@4 {\n+\tfragment@3 {\n \t\ttarget = <&pixelvalve1>;\n \t\t__overlay__ {\n \t\t\tstatus = \"okay\";\n \t\t};\n \t};\n-\tfragment@5 {\n+\tfragment@4 {\n \t\ttarget = <&pixelvalve2>;\n \t\t__overlay__ {\n \t\t\tstatus = \"okay\";\n \t\t};\n \t};\n-\tfragment@6 {\n+\tfragment@5 {\n \t\ttarget = <&hvs>;\n \t\t__overlay__ {\n \t\t\tstatus = \"okay\";\n \t\t};\n \t};\n-\tfragment@7 {\n+\tfragment@6 {\n \t\ttarget = <&hdmi>;\n \t\t__overlay__ {\n \t\t\tstatus = \"okay\";\n \t\t};\n \t};\n-\tfragment@8 {\n+\tfragment@7 {\n \t\ttarget = <&v3d>;\n \t\t__overlay__ {\n \t\t\tstatus = \"okay\";\n \t\t};\n \t};\n-\tfragment@9 {\n+\tfragment@8 {\n \t\ttarget = <&vc4>;\n \t\t__overlay__ {\n \t\t\tstatus = \"okay\";\n \t\t};\n \t};\n-\tfragment@10 {\n+\tfragment@9 {\n \t\ttarget = <&clocks>;\n \t\t__overlay__ {\n \t\t\tclaim-clocks = <BCM2835_PLLD_DSI0 BCM2835_PLLD_DSI1 BCM2835_PLLH_AUX BCM2835_PLLH_PIX>;\n \t\t};\n \t};\n-\tfragment@11 {\n+\tfragment@10 {\n \t\ttarget = <&vec>;\n \t\t__overlay__ {\n \t\t\tstatus = \"okay\";\n \t\t};\n \t};\n-\tfragment@12 {\n+\tfragment@11 {\n \t\ttarget = <&txp>;\n \t\t__overlay__ {\n \t\t\tstatus = \"okay\";\n \t\t};\n \t};\n-\tfragment@13 {\n-\t\ttarget = <&hdmi>;\n-\t\t__dormant__ {\n-\t\t\tdmas;\n-\t\t};\n-\t};\n-\tfragment@14 {\n+\tfragment@12 {\n \t\ttarget = <&audio>;\n \t\t__overlay__ {\n \t\t\tbrcm,disable-hdmi;\n \t\t};\n \t};\n-\tfragment@15 {\n+\tfragment@13 {\n \t\ttarget = <&usb>;\n \t\t#address-cells = <1>;\n \t\t#size-cells = <1>;\n--- a/arch/arm/boot/dts/overlays/upstream-pi4-overlay.dts\n+++ b/arch/arm/boot/dts/overlays/upstream-pi4-overlay.dts\n@@ -8,144 +8,114 @@\n / {\n \tcompatible = \"brcm,bcm2835\";\n \tfragment@0 {\n-\t\ttarget = <&cma>;\n-\t\t__dormant__ {\n-\t\t\tsize = <0x10000000>;\n-\t\t};\n-\t};\n-\tfragment@1 {\n \t\ttarget = <&ddc0>;\n \t\t__overlay__ {\n \t\t\tstatus = \"okay\";\n \t\t};\n \t};\n-\tfragment@2 {\n+\tfragment@1 {\n \t\ttarget = <&ddc1>;\n \t\t__overlay__ {\n \t\t\tstatus = \"okay\";\n \t\t};\n \t};\n-\tfragment@3 {\n+\tfragment@2 {\n \t\ttarget = <&hdmi0>;\n \t\t__overlay__ {\n \t\t\tstatus = \"okay\";\n \t\t};\n \t};\n-\tfragment@4 {\n+\tfragment@3 {\n \t\ttarget = <&hdmi1>;\n \t\t__overlay__ {\n \t\t\tstatus = \"okay\";\n \t\t};\n \t};\n-\tfragment@5 {\n+\tfragment@4 {\n \t\ttarget = <&hvs>;\n \t\t__overlay__ {\n \t\t\tstatus = \"okay\";\n \t\t};\n \t};\n-\tfragment@6 {\n+\tfragment@5 {\n \t\ttarget = <&pixelvalve0>;\n \t\t__overlay__ {\n \t\t\tstatus = \"okay\";\n \t\t};\n \t};\n-\tfragment@7 {\n+\tfragment@6 {\n \t\ttarget = <&pixelvalve1>;\n \t\t__overlay__ {\n \t\t\tstatus = \"okay\";\n \t\t};\n \t};\n-\tfragment@8 {\n+\tfragment@7 {\n \t\ttarget = <&pixelvalve2>;\n \t\t__overlay__ {\n \t\t\tstatus = \"okay\";\n \t\t};\n \t};\n-\tfragment@9 {\n+\tfragment@8 {\n \t\ttarget = <&pixelvalve3>;\n \t\t__overlay__ {\n \t\t\tstatus = \"okay\";\n \t\t};\n \t};\n-\tfragment@10 {\n+\tfragment@9 {\n \t\ttarget = <&pixelvalve4>;\n \t\t__overlay__ {\n \t\t\tstatus = \"okay\";\n \t\t};\n \t};\n-\tfragment@11 {\n+\tfragment@10 {\n \t\ttarget = <&v3d>;\n \t\t__overlay__ {\n \t\t\tstatus = \"okay\";\n \t\t};\n \t};\n-\tfragment@12 {\n+\tfragment@11 {\n \t\ttarget = <&vc4>;\n \t\t__overlay__ {\n \t\t\tstatus = \"okay\";\n \t\t};\n \t};\n-\tfragment@13 {\n+\tfragment@12 {\n \t\ttarget = <&txp>;\n \t\t__overlay__ {\n \t\t\tstatus = \"okay\";\n \t\t};\n \t};\n-\tfragment@14 {\n+\tfragment@13 {\n \t\ttarget = <&fb>;\n \t\t__overlay__ {\n \t\t\tstatus = \"disabled\";\n \t\t};\n \t};\n-\tfragment@15 {\n+\tfragment@14 {\n \t\ttarget = <&firmwarekms>;\n \t\t__overlay__ {\n \t\t\tstatus = \"disabled\";\n \t\t};\n \t};\n-\tfragment@16 {\n+\tfragment@15 {\n \t\ttarget = <&vec>;\n \t\t__overlay__ {\n \t\t\tstatus = \"disabled\";\n \t\t};\n \t};\n-\tfragment@17 {\n-\t\ttarget = <&hdmi0>;\n-\t\t__dormant__ {\n-\t\t\tdmas;\n-\t\t};\n-\t};\n-\tfragment@18 {\n-\t\ttarget = <&hdmi1>;\n-\t\t__dormant__ {\n-\t\t\tdmas;\n-\t\t};\n-\t};\n-\tfragment@19 {\n+\tfragment@16 {\n \t\ttarget = <&audio>;\n \t\t__overlay__ {\n \t\t\tbrcm,disable-hdmi;\n \t\t};\n \t};\n-\tfragment@20 {\n+\tfragment@17 {\n \t\ttarget = <&dvp>;\n \t\t__overlay__ {\n \t\t\tstatus = \"okay\";\n \t\t};\n \t};\n-\tfragment@21 {\n-\t\ttarget = <&pixelvalve3>;\n-\t\t__dormant__ {\n-\t\t\tstatus = \"okay\";\n-\t\t};\n-\t};\n-\tfragment@22 {\n-\t\ttarget = <&vec>;\n-\t\t__dormant__ {\n-\t\t\tstatus = \"okay\";\n-\t\t};\n-\t};\n-\tfragment@23 {\n+\tfragment@18 {\n \t\ttarget = <&usb>;\n \t\t#address-cells = <1>;\n \t\t#size-cells = <1>;\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0420-Add-overlay-for-Seeed-Studio-CAN-BUS-FD-HAT-4034.patch",
    "content": "From 0f49536b413a81aedb9635c7b2613ca5a8d554c4 Mon Sep 17 00:00:00 2001\nFrom: menschel <menschel.p@posteo.de>\nDate: Wed, 30 Dec 2020 21:55:34 +0100\nSubject: [PATCH] Add overlay for Seeed Studio CAN BUS FD HAT (#4034)\n\nThis patch adds the overlay for the Seeed Studio CAN BUS FD HAT\nwith two CAN FD Channels and an RTC.\nhttps://www.seeedstudio.com/CAN-BUS-FD-HAT-for-Raspberry-Pi-p-4742.html\n\nThe overlay was generated by\novmerge -c mcp251xfd-overlay.dts,spi0-0,interrupt=25 \\\n           mcp251xfd-overlay.dts,spi0-1,interrupt=24 \\\n           i2c-rtc-overlay.dts,pcf85063\n\n\nAlso, add description on how to generate overlays\n\nSigned-off-by: Patrick Menschel <menschel.p@posteo.de>\n---\n arch/arm/boot/dts/overlays/Makefile           |   1 +\n arch/arm/boot/dts/overlays/README             |  46 +++++++\n .../dts/overlays/seeed-can-fd-hat-overlay.dts | 117 ++++++++++++++++++\n 3 files changed, 164 insertions(+)\n create mode 100644 arch/arm/boot/dts/overlays/seeed-can-fd-hat-overlay.dts\n\n--- a/arch/arm/boot/dts/overlays/Makefile\n+++ b/arch/arm/boot/dts/overlays/Makefile\n@@ -161,6 +161,7 @@ dtbo-$(CONFIG_ARCH_BCM2835) += \\\n \tsc16is752-spi1.dtbo \\\n \tsdhost.dtbo \\\n \tsdio.dtbo \\\n+\tseeed-can-fd-hat.dtbo \\\n \tsh1106-spi.dtbo \\\n \tsmi.dtbo \\\n \tsmi-dev.dtbo \\\n--- a/arch/arm/boot/dts/overlays/README\n+++ b/arch/arm/boot/dts/overlays/README\n@@ -81,6 +81,44 @@ Parameters usually have default values,\n mandatory. See the list of overlays below for a description of the parameters\n and their defaults.\n \n+Making new Overlays based on existing Overlays\n+==============================================\n+\n+Recent overlays have been designed in a more general way, so that they can be\n+adapted to hardware by changing their parameters. When you have additional\n+hardware with more than one device of a kind, you end up using the same overlay\n+multiple times with other parameters, e.g.\n+\n+    # 2 CAN FD interfaces on spi but with different pins\n+    dtoverlay=mcp251xfd,spi0-0,interrupt=25\n+    dtoverlay=mcp251xfd,spi0-1,interrupt=24\n+\n+    # a realtime clock on i2c\n+    dtoverlay=i2c-rtc,pcf85063\n+\n+While this approach does work, it requires knowledge about the hardware design.\n+It is more feasible to simplify things for the end user by providing a single\n+overlay as it is done the traditional way.\n+\n+A new overlay can be generated by using ovmerge utility.\n+https://github.com/raspberrypi/utils/blob/master/ovmerge/ovmerge\n+\n+To generate an overlay for the above configuration we pass the configuration\n+to ovmerge and add the -c flag.\n+\n+    ovmerge -c mcp251xfd-overlay.dts,spi0-0,interrupt=25 \\\n+               mcp251xfd-overlay.dts,spi0-1,interrupt=24 \\\n+               i2c-rtc-overlay.dts,pcf85063 \\\n+    >> merged-overlay.dts\n+\n+The -c option writes the command above as a comment into the overlay as\n+a marker that this overlay is generated and how it was generated.\n+After compiling the overlay it can be loaded in a single line.\n+\n+    dtoverlay=merged\n+\n+It does the same as the original configuration but without parameters.\n+\n The Overlay and Parameter Reference\n ===================================\n \n@@ -2466,6 +2504,14 @@ Info:   This overlay is now deprecated.\n Load:   <Deprecated>\n \n \n+Name:   seeed-can-fd-hat\n+Info:   Overlay for Seeed Studio CAN BUS FD HAT with two CAN FD channels and an\n+        RTC.\n+        https://www.seeedstudio.com/CAN-BUS-FD-HAT-for-Raspberry-Pi-p-4742.html\n+Load:   dtoverlay=seeed-can-fd-hat\n+Params: <None>\n+\n+\n Name:   sh1106-spi\n Info:   Overlay for SH1106 OLED via SPI using fbtft staging driver.\n Load:   dtoverlay=sh1106-spi,<param>=<val>\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/seeed-can-fd-hat-overlay.dts\n@@ -0,0 +1,117 @@\n+// redo: ovmerge -c mcp251xfd-overlay.dts,spi0-0,interrupt=25 mcp251xfd-overlay.dts,spi0-1,interrupt=24 i2c-rtc-overlay.dts,pcf85063\n+\n+// Device tree overlay for https://www.seeedstudio.com/CAN-BUS-FD-HAT-for-Raspberry-Pi-p-4742.html \n+\n+/dts-v1/;\n+/plugin/;\n+\n+#include <dt-bindings/gpio/gpio.h>\n+#include <dt-bindings/interrupt-controller/irq.h>\n+#include <dt-bindings/pinctrl/bcm2835.h>\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\tfragment@0 {\n+\t\ttarget = <&spidev0>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\tfragment@1 {\n+\t\ttarget = <&gpio>;\n+\t\t__overlay__ {\n+\t\t\tmcp251xfd_pins: mcp251xfd_spi0_0_pins {\n+\t\t\t\tbrcm,pins = <25>;\n+\t\t\t\tbrcm,function = <BCM2835_FSEL_GPIO_IN>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\tfragment@2 {\n+\t\ttarget-path = \"/clocks\";\n+\t\t__overlay__ {\n+\t\t\tclk_mcp251xfd_osc: mcp251xfd-spi0-0-osc {\n+\t\t\t\t#clock-cells = <0>;\n+\t\t\t\tcompatible = \"fixed-clock\";\n+\t\t\t\tclock-frequency = <40000000>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\tfragment@3 {\n+\t\ttarget = <&spi0>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tmcp251xfd@0 {\n+\t\t\t\tcompatible = \"microchip,mcp251xfd\";\n+\t\t\t\treg = <0>;\n+\t\t\t\tpinctrl-names = \"default\";\n+\t\t\t\tpinctrl-0 = <&mcp251xfd_pins>;\n+\t\t\t\tspi-max-frequency = <20000000>;\n+\t\t\t\tinterrupt-parent = <&gpio>;\n+\t\t\t\tinterrupts = <25 IRQ_TYPE_LEVEL_LOW>;\n+\t\t\t\tclocks = <&clk_mcp251xfd_osc>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\tfragment@4 {\n+\t\ttarget = <&spidev1>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\tfragment@5 {\n+\t\ttarget = <&gpio>;\n+\t\t__overlay__ {\n+\t\t\tmcp251xfd_pins_1: mcp251xfd_spi0_1_pins {\n+\t\t\t\tbrcm,pins = <24>;\n+\t\t\t\tbrcm,function = <BCM2835_FSEL_GPIO_IN>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\tfragment@6 {\n+\t\ttarget-path = \"/clocks\";\n+\t\t__overlay__ {\n+\t\t\tclk_mcp251xfd_osc_1: mcp251xfd-spi0-1-osc {\n+\t\t\t\t#clock-cells = <0>;\n+\t\t\t\tcompatible = \"fixed-clock\";\n+\t\t\t\tclock-frequency = <40000000>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\tfragment@7 {\n+\t\ttarget = <&spi0>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tmcp251xfd@1 {\n+\t\t\t\tcompatible = \"microchip,mcp251xfd\";\n+\t\t\t\treg = <1>;\n+\t\t\t\tpinctrl-names = \"default\";\n+\t\t\t\tpinctrl-0 = <&mcp251xfd_pins_1>;\n+\t\t\t\tspi-max-frequency = <20000000>;\n+\t\t\t\tinterrupt-parent = <&gpio>;\n+\t\t\t\tinterrupts = <24 IRQ_TYPE_LEVEL_LOW>;\n+\t\t\t\tclocks = <&clk_mcp251xfd_osc_1>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\tfragment@8 {\n+\t\ttarget = <&i2cbus>;\n+\t\t__overlay__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tpcf85063@51 {\n+\t\t\t\tcompatible = \"nxp,pcf85063\";\n+\t\t\t\treg = <0x51>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\tfragment@9 {\n+\t\ttarget = <&i2c_arm>;\n+\t\ti2cbus: __overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+};\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0421-vc-sm-cma-fixed-kbuild-problem.patch",
    "content": "From 2e4145c9a9d22423d11ad33d56b01bc2973bcdbe Mon Sep 17 00:00:00 2001\nFrom: gesangtome <gesangtome@foxmail.com>\nDate: Fri, 1 Jan 2021 18:03:17 +0800\nSubject: [PATCH] vc-sm-cma: fixed kbuild problem\n\nerror logs:\n  drivers/staging/vc04_services/vc-sm-cma/Kconfig:1:error: recursive dependency detected!\n  drivers/staging/vc04_services/vc-sm-cma/Kconfig:1:      symbol BCM_VC_SM_CMA is selected by BCM2835_VCHIQ_MMAL\n  drivers/staging/vc04_services/vchiq-mmal/Kconfig:1:     symbol BCM2835_VCHIQ_MMAL depends on BCM2835_VCHIQ\n  drivers/staging/vc04_services/Kconfig:14:       symbol BCM2835_VCHIQ is selected by BCM_VC_SM_CMA\n  For a resolution refer to Documentation/kbuild/kconfig-language.rst\n  subsection \"Kconfig recursive dependency limitations\"\n\nTested-by: make ARCH=arm64 bcm2711_defconfig\nTest platform: fedora 33\nBranch: rpi-5.10.y\n---\n drivers/staging/vc04_services/vchiq-mmal/Kconfig | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/drivers/staging/vc04_services/vchiq-mmal/Kconfig\n+++ b/drivers/staging/vc04_services/vchiq-mmal/Kconfig\n@@ -1,6 +1,6 @@\n config BCM2835_VCHIQ_MMAL\n \ttristate \"BCM2835 MMAL VCHIQ service\"\n-\tdepends on BCM2835_VCHIQ\n+\tselect BCM2835_VCHIQ\n \tselect BCM_VC_SM_CMA\n \thelp\n \t  Enables the MMAL API over VCHIQ interface as used for the\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0422-staging-vc04-services-codec-Fix-logical-precedence-i.patch",
    "content": "From 984a05a26dacc21487d4b0fef4296dd695f3e0d8 Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Sat, 2 Jan 2021 10:51:58 +0000\nSubject: [PATCH] staging/vc04-services/codec: Fix logical precedence\n issue\n\nTwo issues identified with operator precedence in logical\nexpressions. Fix them.\n\nhttps://github.com/raspberrypi/linux/issues/4040\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n .../staging/vc04_services/bcm2835-codec/bcm2835-v4l2-codec.c  | 4 ++--\n 1 file changed, 2 insertions(+), 2 deletions(-)\n\n--- a/drivers/staging/vc04_services/bcm2835-codec/bcm2835-v4l2-codec.c\n+++ b/drivers/staging/vc04_services/bcm2835-codec/bcm2835-v4l2-codec.c\n@@ -908,7 +908,7 @@ static void op_buffer_cb(struct vchiq_mm\n \t\t/* stream ended, or buffer being returned during disable. */\n \t\tv4l2_dbg(2, debug, &ctx->dev->v4l2_dev, \"%s: Empty buffer - flags %04x\",\n \t\t\t __func__, mmal_buf->mmal_flags);\n-\t\tif (!mmal_buf->mmal_flags & MMAL_BUFFER_HEADER_FLAG_EOS) {\n+\t\tif (!(mmal_buf->mmal_flags & MMAL_BUFFER_HEADER_FLAG_EOS)) {\n \t\t\tvb2_buffer_done(&vb2->vb2_buf, VB2_BUF_STATE_ERROR);\n \t\t\tif (!port->enabled)\n \t\t\t\tcomplete(&ctx->frame_cmplt);\n@@ -1135,7 +1135,7 @@ static int vidioc_try_fmt(struct bcm2835\n \tif (f->fmt.pix_mp.height > MAX_H)\n \t\tf->fmt.pix_mp.height = MAX_H;\n \n-\tif (!fmt->flags & V4L2_FMT_FLAG_COMPRESSED) {\n+\tif (!(fmt->flags & V4L2_FMT_FLAG_COMPRESSED)) {\n \t\t/* Only clip min w/h on capture. Treat 0x0 as unknown. */\n \t\tif (f->fmt.pix_mp.width < MIN_W)\n \t\t\tf->fmt.pix_mp.width = MIN_W;\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0423-staging-vc04_services-Add-additional-unpacked-raw-fo.patch",
    "content": "From 44d7b4f2225a120a4ecaa3b0528c9fc9ce6bfafb Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Thu, 7 Jan 2021 10:43:20 +0000\nSubject: [PATCH] staging/vc04_services: Add additional unpacked raw\n formats\n\nSupport has been added for the unpacked (16bpp) versions of\nthe MIPI raw 10, 12, and 14 formats, so add the 4CCs for them.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n .../vc04_services/vchiq-mmal/mmal-encodings.h | 22 +++++++++++++++++++\n 1 file changed, 22 insertions(+)\n\n--- a/drivers/staging/vc04_services/vchiq-mmal/mmal-encodings.h\n+++ b/drivers/staging/vc04_services/vchiq-mmal/mmal-encodings.h\n@@ -102,12 +102,34 @@\n #define MMAL_ENCODING_BAYER_SGRBG16    MMAL_FOURCC('G', 'R', '1', '6')\n #define MMAL_ENCODING_BAYER_SRGGB16    MMAL_FOURCC('R', 'G', '1', '6')\n \n+/* 10 bit per pixel unpacked (16bit) Bayer formats. */\n+#define MMAL_ENCODING_BAYER_SBGGR10    MMAL_FOURCC('B', 'G', '1', '0')\n+#define MMAL_ENCODING_BAYER_SGRBG10    MMAL_FOURCC('B', 'A', '1', '0')\n+#define MMAL_ENCODING_BAYER_SGBRG10    MMAL_FOURCC('G', 'B', '1', '0')\n+#define MMAL_ENCODING_BAYER_SRGGB10    MMAL_FOURCC('R', 'G', '1', '0')\n+\n+/* 12 bit per pixel unpacked (16bit) Bayer formats */\n+#define MMAL_ENCODING_BAYER_SBGGR12    MMAL_FOURCC('B', 'G', '1', '2')\n+#define MMAL_ENCODING_BAYER_SGRBG12    MMAL_FOURCC('B', 'A', '1', '2')\n+#define MMAL_ENCODING_BAYER_SGBRG12    MMAL_FOURCC('G', 'B', '1', '2')\n+#define MMAL_ENCODING_BAYER_SRGGB12    MMAL_FOURCC('R', 'G', '1', '2')\n+\n+/* 14 bit per pixel unpacked (16bit) Bayer formats */\n+#define MMAL_ENCODING_BAYER_SBGGR14    MMAL_FOURCC('B', 'G', '1', '4')\n+#define MMAL_ENCODING_BAYER_SGBRG14    MMAL_FOURCC('G', 'B', '1', '4')\n+#define MMAL_ENCODING_BAYER_SGRBG14    MMAL_FOURCC('G', 'R', '1', '4')\n+#define MMAL_ENCODING_BAYER_SRGGB14    MMAL_FOURCC('R', 'G', '1', '4')\n+\n /* MIPI packed monochrome images */\n #define MMAL_ENCODING_GREY    MMAL_FOURCC('G', 'R', 'E', 'Y')\n #define MMAL_ENCODING_Y10P    MMAL_FOURCC('Y', '1', '0', 'P')\n #define MMAL_ENCODING_Y12P    MMAL_FOURCC('Y', '1', '2', 'P')\n #define MMAL_ENCODING_Y14P    MMAL_FOURCC('Y', '1', '4', 'P')\n #define MMAL_ENCODING_Y16     MMAL_FOURCC('Y', '1', '6', ' ')\n+/* Unpacked monochrome formats (16bit per sample, but only N LSBs used) */\n+#define MMAL_ENCODING_Y10     MMAL_FOURCC('Y', '1', '0', ' ')\n+#define MMAL_ENCODING_Y12     MMAL_FOURCC('Y', '1', '2', ' ')\n+#define MMAL_ENCODING_Y14     MMAL_FOURCC('Y', '1', '4', ' ')\n \n /** An EGL image handle\n  */\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0424-staging-bcm2835-codec-Add-the-unpacked-16bpp-raw-for.patch",
    "content": "From 49a0627f025c62465563090dc7785ba6c9764bcd Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Thu, 7 Jan 2021 10:45:16 +0000\nSubject: [PATCH] staging/bcm2835-codec: Add the unpacked (16bpp) raw\n formats\n\nNow that the firmware supports the unpacked (16bpp) variants\nof the MIPI raw formats, add the mappings.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n .../bcm2835-codec/bcm2835-v4l2-codec.c        | 128 +++++++++++++++++-\n 1 file changed, 126 insertions(+), 2 deletions(-)\n\n--- a/drivers/staging/vc04_services/bcm2835-codec/bcm2835-v4l2-codec.c\n+++ b/drivers/staging/vc04_services/bcm2835-codec/bcm2835-v4l2-codec.c\n@@ -381,6 +381,106 @@ static const struct bcm2835_codec_fmt su\n \t\t.size_multiplier_x2\t= 2,\n \t\t.is_bayer\t\t= true,\n \t}, {\n+\t\t/* Bayer formats unpacked to 16bpp */\n+\t\t/* 10 bit */\n+\t\t.fourcc\t\t\t= V4L2_PIX_FMT_SRGGB10,\n+\t\t.depth\t\t\t= 16,\n+\t\t.bytesperline_align\t= 32,\n+\t\t.flags\t\t\t= 0,\n+\t\t.mmal_fmt\t\t= MMAL_ENCODING_BAYER_SRGGB10,\n+\t\t.size_multiplier_x2\t= 2,\n+\t\t.is_bayer\t\t= true,\n+\t}, {\n+\t\t.fourcc\t\t\t= V4L2_PIX_FMT_SBGGR10,\n+\t\t.depth\t\t\t= 16,\n+\t\t.bytesperline_align\t= 32,\n+\t\t.flags\t\t\t= 0,\n+\t\t.mmal_fmt\t\t= MMAL_ENCODING_BAYER_SBGGR10,\n+\t\t.size_multiplier_x2\t= 2,\n+\t\t.is_bayer\t\t= true,\n+\t}, {\n+\t\t.fourcc\t\t\t= V4L2_PIX_FMT_SGRBG10,\n+\t\t.depth\t\t\t= 16,\n+\t\t.bytesperline_align\t= 32,\n+\t\t.flags\t\t\t= 0,\n+\t\t.mmal_fmt\t\t= MMAL_ENCODING_BAYER_SGRBG10,\n+\t\t.size_multiplier_x2\t= 2,\n+\t\t.is_bayer\t\t= true,\n+\t}, {\n+\t\t.fourcc\t\t\t= V4L2_PIX_FMT_SGBRG10,\n+\t\t.depth\t\t\t= 16,\n+\t\t.bytesperline_align\t= 32,\n+\t\t.flags\t\t\t= 0,\n+\t\t.mmal_fmt\t\t= MMAL_ENCODING_BAYER_SGBRG10,\n+\t\t.size_multiplier_x2\t= 2,\n+\t\t.is_bayer\t\t= true,\n+\t}, {\n+\t\t/* 12 bit */\n+\t\t.fourcc\t\t\t= V4L2_PIX_FMT_SRGGB12,\n+\t\t.depth\t\t\t= 16,\n+\t\t.bytesperline_align\t= 32,\n+\t\t.flags\t\t\t= 0,\n+\t\t.mmal_fmt\t\t= MMAL_ENCODING_BAYER_SRGGB12,\n+\t\t.size_multiplier_x2\t= 2,\n+\t\t.is_bayer\t\t= true,\n+\t}, {\n+\t\t.fourcc\t\t\t= V4L2_PIX_FMT_SBGGR12,\n+\t\t.depth\t\t\t= 16,\n+\t\t.bytesperline_align\t= 32,\n+\t\t.flags\t\t\t= 0,\n+\t\t.mmal_fmt\t\t= MMAL_ENCODING_BAYER_SBGGR12,\n+\t\t.size_multiplier_x2\t= 2,\n+\t\t.is_bayer\t\t= true,\n+\t}, {\n+\t\t.fourcc\t\t\t= V4L2_PIX_FMT_SGRBG12,\n+\t\t.depth\t\t\t= 16,\n+\t\t.bytesperline_align\t= 32,\n+\t\t.flags\t\t\t= 0,\n+\t\t.mmal_fmt\t\t= MMAL_ENCODING_BAYER_SGRBG12,\n+\t\t.size_multiplier_x2\t= 2,\n+\t\t.is_bayer\t\t= true,\n+\t}, {\n+\t\t.fourcc\t\t\t= V4L2_PIX_FMT_SGBRG12,\n+\t\t.depth\t\t\t= 16,\n+\t\t.bytesperline_align\t= 32,\n+\t\t.flags\t\t\t= 0,\n+\t\t.mmal_fmt\t\t= MMAL_ENCODING_BAYER_SGBRG12,\n+\t\t.size_multiplier_x2\t= 2,\n+\t\t.is_bayer\t\t= true,\n+\t}, {\n+\t\t/* 14 bit */\n+\t\t.fourcc\t\t\t= V4L2_PIX_FMT_SRGGB14,\n+\t\t.depth\t\t\t= 16,\n+\t\t.bytesperline_align\t= 32,\n+\t\t.flags\t\t\t= 0,\n+\t\t.mmal_fmt\t\t= MMAL_ENCODING_BAYER_SRGGB14,\n+\t\t.size_multiplier_x2\t= 2,\n+\t\t.is_bayer\t\t= true,\n+\t}, {\n+\t\t.fourcc\t\t\t= V4L2_PIX_FMT_SBGGR14,\n+\t\t.depth\t\t\t= 16,\n+\t\t.bytesperline_align\t= 32,\n+\t\t.flags\t\t\t= 0,\n+\t\t.mmal_fmt\t\t= MMAL_ENCODING_BAYER_SBGGR14,\n+\t\t.size_multiplier_x2\t= 2,\n+\t\t.is_bayer\t\t= true,\n+\t}, {\n+\t\t.fourcc\t\t\t= V4L2_PIX_FMT_SGRBG14,\n+\t\t.depth\t\t\t= 16,\n+\t\t.bytesperline_align\t= 32,\n+\t\t.flags\t\t\t= 0,\n+\t\t.mmal_fmt\t\t= MMAL_ENCODING_BAYER_SGRBG14,\n+\t\t.size_multiplier_x2\t= 2,\n+\t\t.is_bayer\t\t= true,\n+\t}, {\n+\t\t.fourcc\t\t\t= V4L2_PIX_FMT_SGBRG14,\n+\t\t.depth\t\t\t= 16,\n+\t\t.bytesperline_align\t= 32,\n+\t\t.flags\t\t\t= 0,\n+\t\t.mmal_fmt\t\t= MMAL_ENCODING_BAYER_SGBRG14,\n+\t\t.size_multiplier_x2\t= 2,\n+\t\t.is_bayer\t\t= true,\n+\t}, {\n \t\t/* Monochrome MIPI formats */\n \t\t/* 8 bit */\n \t\t.fourcc\t\t\t= V4L2_PIX_FMT_GREY,\n@@ -422,6 +522,30 @@ static const struct bcm2835_codec_fmt su\n \t\t.mmal_fmt\t\t= MMAL_ENCODING_Y16,\n \t\t.size_multiplier_x2\t= 2,\n \t}, {\n+\t\t/* 10 bit as 16bpp */\n+\t\t.fourcc\t\t\t= V4L2_PIX_FMT_Y10,\n+\t\t.depth\t\t\t= 16,\n+\t\t.bytesperline_align\t= 32,\n+\t\t.flags\t\t\t= 0,\n+\t\t.mmal_fmt\t\t= MMAL_ENCODING_Y10,\n+\t\t.size_multiplier_x2\t= 2,\n+\t}, {\n+\t\t/* 12 bit as 16bpp */\n+\t\t.fourcc\t\t\t= V4L2_PIX_FMT_Y12,\n+\t\t.depth\t\t\t= 16,\n+\t\t.bytesperline_align\t= 32,\n+\t\t.flags\t\t\t= 0,\n+\t\t.mmal_fmt\t\t= MMAL_ENCODING_Y12,\n+\t\t.size_multiplier_x2\t= 2,\n+\t}, {\n+\t\t/* 14 bit as 16bpp */\n+\t\t.fourcc\t\t\t= V4L2_PIX_FMT_Y14,\n+\t\t.depth\t\t\t= 16,\n+\t\t.bytesperline_align\t= 32,\n+\t\t.flags\t\t\t= 0,\n+\t\t.mmal_fmt\t\t= MMAL_ENCODING_Y14,\n+\t\t.size_multiplier_x2\t= 2,\n+\t}, {\n \t\t/* Compressed formats */\n \t\t.fourcc\t\t\t= V4L2_PIX_FMT_H264,\n \t\t.depth\t\t\t= 0,\n@@ -2681,10 +2805,10 @@ static const struct v4l2_m2m_ops m2m_ops\n \n /* Size of the array to provide to the VPU when asking for the list of supported\n  * formats.\n- * The ISP component currently advertises 44 input formats, so add a small\n+ * The ISP component currently advertises 62 input formats, so add a small\n  * overhead on that.\n  */\n-#define MAX_SUPPORTED_ENCODINGS 50\n+#define MAX_SUPPORTED_ENCODINGS 70\n \n /* Populate dev->supported_fmts with the formats supported by those ports. */\n static int bcm2835_codec_get_supported_fmts(struct bcm2835_codec_dev *dev)\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0425-staging-bcm2835-codec-Log-the-number-of-excess-suppo.patch",
    "content": "From fec4f38da35da73f0ee3b28ad7daaf4a97855ea7 Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Thu, 7 Jan 2021 11:41:26 +0000\nSubject: [PATCH] staging/bcm2835-codec: Log the number of excess\n supported formats\n\nWhen logging that the firmware has provided more supported formats\nthan we had allocated storage for, log the number allocated and\nreturned.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n .../vc04_services/bcm2835-codec/bcm2835-v4l2-codec.c | 12 ++++++++----\n 1 file changed, 8 insertions(+), 4 deletions(-)\n\n--- a/drivers/staging/vc04_services/bcm2835-codec/bcm2835-v4l2-codec.c\n+++ b/drivers/staging/vc04_services/bcm2835-codec/bcm2835-v4l2-codec.c\n@@ -2836,8 +2836,10 @@ static int bcm2835_codec_get_supported_f\n \n \tif (ret) {\n \t\tif (ret == MMAL_MSG_STATUS_ENOSPC) {\n-\t\t\tv4l2_err(&dev->v4l2_dev, \"%s: port has more encoding than we provided space for. Some are dropped.\\n\",\n-\t\t\t\t __func__);\n+\t\t\tv4l2_err(&dev->v4l2_dev,\n+\t\t\t\t \"%s: port has more encodings than we provided space for. Some are dropped (%u vs %u).\\n\",\n+\t\t\t\t __func__, param_size / sizeof(u32),\n+\t\t\t\t MAX_SUPPORTED_ENCODINGS);\n \t\t\tnum_encodings = MAX_SUPPORTED_ENCODINGS;\n \t\t} else {\n \t\t\tv4l2_err(&dev->v4l2_dev, \"%s: get_param ret %u.\\n\",\n@@ -2880,8 +2882,10 @@ static int bcm2835_codec_get_supported_f\n \n \tif (ret) {\n \t\tif (ret == MMAL_MSG_STATUS_ENOSPC) {\n-\t\t\tv4l2_err(&dev->v4l2_dev, \"%s: port has more encoding than we provided space for. Some are dropped.\\n\",\n-\t\t\t\t __func__);\n+\t\t\tv4l2_err(&dev->v4l2_dev,\n+\t\t\t\t \"%s: port has more encodings than we provided space for. Some are dropped (%u vs %u).\\n\",\n+\t\t\t\t __func__, param_size / sizeof(u32),\n+\t\t\t\t MAX_SUPPORTED_ENCODINGS);\n \t\t\tnum_encodings = MAX_SUPPORTED_ENCODINGS;\n \t\t} else {\n \t\t\tret = -EINVAL;\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0426-staging-bcm2835-isp-Add-the-unpacked-16bpp-raw-forma.patch",
    "content": "From 9a021facd450a55231938131702cbc8b4e9c92e7 Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Thu, 7 Jan 2021 11:37:10 +0000\nSubject: [PATCH] staging/bcm2835-isp: Add the unpacked (16bpp) raw\n formats\n\nNow that the firmware supports the unpacked (16bpp) variants\nof the MIPI raw formats, add the mappings.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n .../bcm2835-isp/bcm2835-isp-fmts.h            | 127 ++++++++++++++++++\n .../bcm2835-isp/bcm2835-v4l2-isp.c            |   4 +-\n 2 files changed, 129 insertions(+), 2 deletions(-)\n\n--- a/drivers/staging/vc04_services/bcm2835-isp/bcm2835-isp-fmts.h\n+++ b/drivers/staging/vc04_services/bcm2835-isp/bcm2835-isp-fmts.h\n@@ -298,6 +298,106 @@ static const struct bcm2835_isp_fmt supp\n \t\t.colorspace\t    = V4L2_COLORSPACE_RAW,\n \t\t.step_size\t    = 2,\n \t}, {\n+\t\t/* Bayer formats unpacked to 16bpp */\n+\t\t/* 10 bit */\n+\t\t.fourcc\t\t    = V4L2_PIX_FMT_SRGGB10,\n+\t\t.depth\t\t    = 16,\n+\t\t.bytesperline_align = 32,\n+\t\t.mmal_fmt\t    = MMAL_ENCODING_BAYER_SRGGB10,\n+\t\t.size_multiplier_x2 = 2,\n+\t\t.colorspace\t    = V4L2_COLORSPACE_RAW,\n+\t\t.step_size\t    = 2,\n+\t}, {\n+\t\t.fourcc\t\t    = V4L2_PIX_FMT_SBGGR10,\n+\t\t.depth\t\t    = 16,\n+\t\t.bytesperline_align = 32,\n+\t\t.mmal_fmt\t    = MMAL_ENCODING_BAYER_SBGGR10,\n+\t\t.size_multiplier_x2 = 2,\n+\t\t.colorspace\t    = V4L2_COLORSPACE_RAW,\n+\t\t.step_size\t    = 2,\n+\t}, {\n+\t\t.fourcc\t\t    = V4L2_PIX_FMT_SGRBG10,\n+\t\t.depth\t\t    = 16,\n+\t\t.bytesperline_align = 32,\n+\t\t.mmal_fmt\t    = MMAL_ENCODING_BAYER_SGRBG10,\n+\t\t.size_multiplier_x2 = 2,\n+\t\t.colorspace\t    = V4L2_COLORSPACE_RAW,\n+\t\t.step_size\t    = 2,\n+\t}, {\n+\t\t.fourcc\t\t    = V4L2_PIX_FMT_SGBRG10,\n+\t\t.depth\t\t    = 16,\n+\t\t.bytesperline_align = 32,\n+\t\t.mmal_fmt\t    = MMAL_ENCODING_BAYER_SGBRG10,\n+\t\t.size_multiplier_x2 = 2,\n+\t\t.colorspace\t    = V4L2_COLORSPACE_RAW,\n+\t\t.step_size\t    = 2,\n+\t}, {\n+\t\t/* 12 bit */\n+\t\t.fourcc\t\t    = V4L2_PIX_FMT_SRGGB12,\n+\t\t.depth\t\t    = 16,\n+\t\t.bytesperline_align = 32,\n+\t\t.mmal_fmt\t    = MMAL_ENCODING_BAYER_SRGGB12,\n+\t\t.size_multiplier_x2 = 2,\n+\t\t.colorspace\t    = V4L2_COLORSPACE_RAW,\n+\t\t.step_size\t    = 2,\n+\t}, {\n+\t\t.fourcc\t\t    = V4L2_PIX_FMT_SBGGR12,\n+\t\t.depth\t\t    = 16,\n+\t\t.bytesperline_align = 32,\n+\t\t.mmal_fmt\t    = MMAL_ENCODING_BAYER_SBGGR12,\n+\t\t.size_multiplier_x2 = 2,\n+\t\t.colorspace\t    = V4L2_COLORSPACE_RAW,\n+\t\t.step_size\t    = 2,\n+\t}, {\n+\t\t.fourcc\t\t    = V4L2_PIX_FMT_SGRBG12,\n+\t\t.depth\t\t    = 16,\n+\t\t.bytesperline_align = 32,\n+\t\t.mmal_fmt\t    = MMAL_ENCODING_BAYER_SGRBG12,\n+\t\t.size_multiplier_x2 = 2,\n+\t\t.colorspace\t    = V4L2_COLORSPACE_RAW,\n+\t\t.step_size\t    = 2,\n+\t}, {\n+\t\t.fourcc\t\t    = V4L2_PIX_FMT_SGBRG12,\n+\t\t.depth\t\t    = 16,\n+\t\t.bytesperline_align = 32,\n+\t\t.mmal_fmt\t    = MMAL_ENCODING_BAYER_SGBRG12,\n+\t\t.size_multiplier_x2 = 2,\n+\t\t.colorspace\t    = V4L2_COLORSPACE_RAW,\n+\t\t.step_size\t    = 2,\n+\t}, {\n+\t\t/* 14 bit */\n+\t\t.fourcc\t\t    = V4L2_PIX_FMT_SRGGB14,\n+\t\t.depth\t\t    = 16,\n+\t\t.bytesperline_align = 32,\n+\t\t.mmal_fmt\t    = MMAL_ENCODING_BAYER_SRGGB14,\n+\t\t.size_multiplier_x2 = 2,\n+\t\t.colorspace\t    = V4L2_COLORSPACE_RAW,\n+\t\t.step_size\t    = 2,\n+\t}, {\n+\t\t.fourcc\t\t    = V4L2_PIX_FMT_SBGGR14,\n+\t\t.depth\t\t    = 16,\n+\t\t.bytesperline_align = 32,\n+\t\t.mmal_fmt\t    = MMAL_ENCODING_BAYER_SBGGR14,\n+\t\t.size_multiplier_x2 = 2,\n+\t\t.colorspace\t    = V4L2_COLORSPACE_RAW,\n+\t\t.step_size\t    = 2,\n+\t}, {\n+\t\t.fourcc\t\t    = V4L2_PIX_FMT_SGRBG14,\n+\t\t.depth\t\t    = 16,\n+\t\t.bytesperline_align = 32,\n+\t\t.mmal_fmt\t    = MMAL_ENCODING_BAYER_SGRBG14,\n+\t\t.size_multiplier_x2 = 2,\n+\t\t.colorspace\t    = V4L2_COLORSPACE_RAW,\n+\t\t.step_size\t    = 2,\n+\t}, {\n+\t\t.fourcc\t\t    = V4L2_PIX_FMT_SGBRG14,\n+\t\t.depth\t\t    = 16,\n+\t\t.bytesperline_align = 32,\n+\t\t.mmal_fmt\t    = MMAL_ENCODING_BAYER_SGBRG14,\n+\t\t.size_multiplier_x2 = 2,\n+\t\t.colorspace\t    = V4L2_COLORSPACE_RAW,\n+\t\t.step_size\t    = 2,\n+\t}, {\n \t\t/* Monochrome MIPI formats */\n \t\t/* 8 bit */\n \t\t.fourcc\t\t    = V4L2_PIX_FMT_GREY,\n@@ -343,6 +443,33 @@ static const struct bcm2835_isp_fmt supp\n \t\t.size_multiplier_x2 = 2,\n \t\t.colorspace\t    = V4L2_COLORSPACE_RAW,\n \t\t.step_size\t    = 2,\n+\t}, {\n+\t\t/* 10 bit as 16bpp */\n+\t\t.fourcc\t\t    = V4L2_PIX_FMT_Y10,\n+\t\t.depth\t\t    = 16,\n+\t\t.bytesperline_align = 32,\n+\t\t.mmal_fmt\t    = MMAL_ENCODING_Y10,\n+\t\t.size_multiplier_x2 = 2,\n+\t\t.colorspace\t    = V4L2_COLORSPACE_RAW,\n+\t\t.step_size\t    = 2,\n+\t}, {\n+\t\t/* 12 bit as 16bpp */\n+\t\t.fourcc\t\t    = V4L2_PIX_FMT_Y12,\n+\t\t.depth\t\t    = 16,\n+\t\t.bytesperline_align = 32,\n+\t\t.mmal_fmt\t    = MMAL_ENCODING_Y12,\n+\t\t.size_multiplier_x2 = 2,\n+\t\t.colorspace\t    = V4L2_COLORSPACE_RAW,\n+\t\t.step_size\t    = 2,\n+\t}, {\n+\t\t/* 14 bit as 16bpp */\n+\t\t.fourcc\t\t    = V4L2_PIX_FMT_Y14,\n+\t\t.depth\t\t    = 16,\n+\t\t.bytesperline_align = 32,\n+\t\t.mmal_fmt\t    = MMAL_ENCODING_Y14,\n+\t\t.size_multiplier_x2 = 2,\n+\t\t.colorspace\t    = V4L2_COLORSPACE_RAW,\n+\t\t.step_size\t    = 2,\n \t}, {\n \t\t.fourcc\t\t    = V4L2_META_FMT_BCM2835_ISP_STATS,\n \t\t.mmal_fmt\t    = MMAL_ENCODING_BRCM_STATS,\n--- a/drivers/staging/vc04_services/bcm2835-isp/bcm2835-v4l2-isp.c\n+++ b/drivers/staging/vc04_services/bcm2835-isp/bcm2835-v4l2-isp.c\n@@ -1146,11 +1146,11 @@ static const struct v4l2_ioctl_ops bcm28\n  * Size of the array to provide to the VPU when asking for the list of supported\n  * formats.\n  *\n- * The ISP component currently advertises 44 input formats, so add a small\n+ * The ISP component currently advertises 62 input formats, so add a small\n  * overhead on that. Should the component advertise more formats then the excess\n  * will be dropped and a warning logged.\n  */\n-#define MAX_SUPPORTED_ENCODINGS 50\n+#define MAX_SUPPORTED_ENCODINGS 70\n \n /* Populate node->supported_fmts with the formats supported by those ports. */\n static int bcm2835_isp_get_supported_fmts(struct bcm2835_isp_node *node)\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0427-staging-bcm2835-isp-Log-the-number-of-excess-support.patch",
    "content": "From 6d82a5755bd242633d3640bf0fff5b05d52c4e01 Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Thu, 7 Jan 2021 11:43:22 +0000\nSubject: [PATCH] staging/bcm2835-isp: Log the number of excess\n supported formats\n\nWhen logging that the firmware has provided more supported formats\nthan we had allocated storage for, log the number allocated and\nreturned.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n drivers/staging/vc04_services/bcm2835-isp/bcm2835-v4l2-isp.c | 5 +++--\n 1 file changed, 3 insertions(+), 2 deletions(-)\n\n--- a/drivers/staging/vc04_services/bcm2835-isp/bcm2835-v4l2-isp.c\n+++ b/drivers/staging/vc04_services/bcm2835-isp/bcm2835-v4l2-isp.c\n@@ -1169,8 +1169,9 @@ static int bcm2835_isp_get_supported_fmt\n \tif (ret) {\n \t\tif (ret == MMAL_MSG_STATUS_ENOSPC) {\n \t\t\tv4l2_err(&dev->v4l2_dev,\n-\t\t\t\t \"%s: port has more encoding than we provided space for. Some are dropped.\\n\",\n-\t\t\t\t __func__);\n+\t\t\t\t \"%s: port has more encodings than we provided space for. Some are dropped (%u vs %u).\\n\",\n+\t\t\t\t __func__, param_size / sizeof(u32),\n+\t\t\t\t MAX_SUPPORTED_ENCODINGS);\n \t\t\tnum_encodings = MAX_SUPPORTED_ENCODINGS;\n \t\t} else {\n \t\t\tv4l2_err(&dev->v4l2_dev, \"%s: get_param ret %u.\\n\",\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0428-bcm2835-dma-Add-bcm2835-dma-Add-DMA_WIDE_SOURCE-and-.patch",
    "content": "From 7ab9c31d27699755870da3bae07b4a0f167b4284 Mon Sep 17 00:00:00 2001\nFrom: Dom Cobley <popcornmix@gmail.com>\nDate: Wed, 30 Dec 2020 14:51:29 +0000\nSubject: [PATCH] bcm2835-dma: Add bcm2835-dma: Add DMA_WIDE_SOURCE and\n DMA_WIDE_DEST flags\n\nUse (reserved) bits 24 and 25 of the dreq value\n(the second cell of the DT DMA descriptor) to request\nthat wide source reads or wide dest writes are required\n\nSigned-off-by: Dom Cobley <popcornmix@gmail.com>\n---\n drivers/dma/bcm2835-dma.c | 19 ++++++++++++++++---\n 1 file changed, 16 insertions(+), 3 deletions(-)\n\n--- a/drivers/dma/bcm2835-dma.c\n+++ b/drivers/dma/bcm2835-dma.c\n@@ -171,6 +171,17 @@ struct bcm2835_desc {\n #define WAIT_RESP(x) ((x & BCM2835_DMA_NO_WAIT_RESP) ? \\\n \t\t      0 : BCM2835_DMA_WAIT_RESP)\n \n+/* A fake bit to request that the driver requires wide reads */\n+#define BCM2835_DMA_WIDE_SOURCE BIT(24)\n+#define WIDE_SOURCE(x) ((x & BCM2835_DMA_WIDE_SOURCE) ? \\\n+\t\t      BCM2835_DMA_S_WIDTH : 0)\n+\n+/* A fake bit to request that the driver requires wide writes */\n+#define BCM2835_DMA_WIDE_DEST BIT(25)\n+#define WIDE_DEST(x) ((x & BCM2835_DMA_WIDE_DEST) ? \\\n+\t\t      BCM2835_DMA_D_WIDTH : 0)\n+\n+\n /* debug register bits */\n #define BCM2835_DMA_DEBUG_LAST_NOT_SET_ERR\tBIT(0)\n #define BCM2835_DMA_DEBUG_FIFO_ERR\t\tBIT(1)\n@@ -850,7 +861,8 @@ static struct dma_async_tx_descriptor *b\n {\n \tstruct bcm2835_chan *c = to_bcm2835_dma_chan(chan);\n \tstruct bcm2835_desc *d;\n-\tu32 info = BCM2835_DMA_D_INC | BCM2835_DMA_S_INC;\n+\tu32 info = BCM2835_DMA_D_INC | BCM2835_DMA_S_INC |\n+\t\t   WIDE_SOURCE(c->dreq) | WIDE_DEST(c->dreq);\n \tu32 extra = BCM2835_DMA_INT_EN | WAIT_RESP(c->dreq);\n \tsize_t max_len = bcm2835_dma_max_frame_length(c);\n \tsize_t frames;\n@@ -881,7 +893,8 @@ static struct dma_async_tx_descriptor *b\n \tstruct bcm2835_chan *c = to_bcm2835_dma_chan(chan);\n \tstruct bcm2835_desc *d;\n \tdma_addr_t src = 0, dst = 0;\n-\tu32 info = WAIT_RESP(c->dreq);\n+\tu32 info = WAIT_RESP(c->dreq) |\n+\t\t   WIDE_SOURCE(c->dreq) | WIDE_DEST(c->dreq);\n \tu32 extra = BCM2835_DMA_INT_EN;\n \tsize_t frames;\n \n@@ -943,7 +956,7 @@ static struct dma_async_tx_descriptor *b\n \tstruct bcm2835_chan *c = to_bcm2835_dma_chan(chan);\n \tstruct bcm2835_desc *d;\n \tdma_addr_t src, dst;\n-\tu32 info = WAIT_RESP(c->dreq);\n+\tu32 info = WAIT_RESP(c->dreq) | WIDE_SOURCE(c->dreq) | WIDE_DEST(c->dreq);\n \tu32 extra = 0;\n \tsize_t max_len = bcm2835_dma_max_frame_length(c);\n \tsize_t frames;\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0429-bcm2835-dma-Move-WAIT_RESP-from-extra-to-info.patch",
    "content": "From 319fb2652bdfc0176ec8c69ce612c0f0dcc4a0ed Mon Sep 17 00:00:00 2001\nFrom: popcornmix <popcornmix@gmail.com>\nDate: Mon, 11 Jan 2021 14:49:33 +0000\nSubject: [PATCH] bcm2835-dma: Move WAIT_RESP from extra to info\n\nQuestionable: Might want to drop\nSigned-off-by: popcornmix <popcornmix@gmail.com>\n---\n drivers/dma/bcm2835-dma.c | 4 ++--\n 1 file changed, 2 insertions(+), 2 deletions(-)\n\n--- a/drivers/dma/bcm2835-dma.c\n+++ b/drivers/dma/bcm2835-dma.c\n@@ -861,9 +861,9 @@ static struct dma_async_tx_descriptor *b\n {\n \tstruct bcm2835_chan *c = to_bcm2835_dma_chan(chan);\n \tstruct bcm2835_desc *d;\n-\tu32 info = BCM2835_DMA_D_INC | BCM2835_DMA_S_INC |\n+\tu32 info = BCM2835_DMA_D_INC | BCM2835_DMA_S_INC | WAIT_RESP(c->dreq) |\n \t\t   WIDE_SOURCE(c->dreq) | WIDE_DEST(c->dreq);\n-\tu32 extra = BCM2835_DMA_INT_EN | WAIT_RESP(c->dreq);\n+\tu32 extra = BCM2835_DMA_INT_EN;\n \tsize_t max_len = bcm2835_dma_max_frame_length(c);\n \tsize_t frames;\n \n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0430-bcm2835-dma-Avoid-losing-CS-flags-after-interrupt.patch",
    "content": "From 5226757c28364667ee1a6acad60dd76fc3394e34 Mon Sep 17 00:00:00 2001\nFrom: Dom Cobley <popcornmix@gmail.com>\nDate: Wed, 6 Jan 2021 18:16:10 +0000\nSubject: [PATCH] bcm2835-dma: Avoid losing CS flags after interrupt\n\nSigned-off-by: Dom Cobley <popcornmix@gmail.com>\n---\n drivers/dma/bcm2835-dma.c | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/drivers/dma/bcm2835-dma.c\n+++ b/drivers/dma/bcm2835-dma.c\n@@ -715,7 +715,7 @@ static irqreturn_t bcm2835_dma_callback(\n \t * if this IRQ handler is threaded.) If the channel is finished, it\n \t * will remain idle despite the ACTIVE flag being set.\n \t */\n-\twritel(BCM2835_DMA_INT | BCM2835_DMA_ACTIVE,\n+\twritel(BCM2835_DMA_INT | BCM2835_DMA_ACTIVE | BCM2835_DMA_CS_FLAGS(c->dreq),\n \t       c->chan_base + BCM2835_DMA_CS);\n \n \td = c->desc;\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0431-dt-Enable-DMA_WIDE_SOURCE-and-DMA_WIDE_DEST-for-hdmi.patch",
    "content": "From 4e79497bed02399934bdc8beaa980cb4b7bdf19f Mon Sep 17 00:00:00 2001\nFrom: popcornmix <popcornmix@gmail.com>\nDate: Mon, 11 Jan 2021 13:06:23 +0000\nSubject: [PATCH] dt: Enable DMA_WIDE_SOURCE and DMA_WIDE_DEST for hdmi\n audio\n\nSigned-off-by: popcornmix <popcornmix@gmail.com>\n---\n arch/arm/boot/dts/bcm2711-rpi.dtsi    | 4 ++--\n arch/arm/boot/dts/bcm2835-common.dtsi | 2 +-\n 2 files changed, 3 insertions(+), 3 deletions(-)\n\n--- a/arch/arm/boot/dts/bcm2711-rpi.dtsi\n+++ b/arch/arm/boot/dts/bcm2711-rpi.dtsi\n@@ -179,7 +179,7 @@\n };\n \n &hdmi0 {\n-\tdmas = <&dma (10|(1<<27))>;\n+\tdmas = <&dma (10|(1<<27)|(1<<24))>;\n \tstatus = \"disabled\";\n };\n \n@@ -188,7 +188,7 @@\n };\n \n &hdmi1 {\n-\tdmas = <&dma (17|(1<<27))>;\n+\tdmas = <&dma (17|(1<<27)|(1<<24))>;\n \tstatus = \"disabled\";\n };\n \n--- a/arch/arm/boot/dts/bcm2835-common.dtsi\n+++ b/arch/arm/boot/dts/bcm2835-common.dtsi\n@@ -123,7 +123,7 @@\n \t\t\tclocks = <&clocks BCM2835_PLLH_PIX>,\n \t\t\t\t <&clocks BCM2835_CLOCK_HSM>;\n \t\t\tclock-names = \"pixel\", \"hdmi\";\n-\t\t\tdmas = <&dma (17|(1<<27))>;\n+\t\t\tdmas = <&dma (17|(1<<27)|(1<<24))>;\n \t\t\tdma-names = \"audio-rx\";\n \t\t\tstatus = \"disabled\";\n \t\t};\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0432-bcm2711-rpi.dtsi-Bump-hdmi-audio-dma-panic-priority-.patch",
    "content": "From c6faef087c0a9a5f89dd29e1a557cb3dfc4b993b Mon Sep 17 00:00:00 2001\nFrom: Dom Cobley <popcornmix@gmail.com>\nDate: Wed, 6 Jan 2021 18:16:29 +0000\nSubject: [PATCH] bcm2711-rpi.dtsi: Bump hdmi audio dma panic priority\n to max\n\nSet panic priority to 15 and leave normal priority at 0\n\nSigned-off-by: Dom Cobley <popcornmix@gmail.com>\n---\n arch/arm/boot/dts/bcm2711-rpi.dtsi | 4 ++--\n 1 file changed, 2 insertions(+), 2 deletions(-)\n\n--- a/arch/arm/boot/dts/bcm2711-rpi.dtsi\n+++ b/arch/arm/boot/dts/bcm2711-rpi.dtsi\n@@ -179,7 +179,7 @@\n };\n \n &hdmi0 {\n-\tdmas = <&dma (10|(1<<27)|(1<<24))>;\n+\tdmas = <&dma (10|(1<<27)|(1<<24)|(0<<16)|(15<<20))>;\n \tstatus = \"disabled\";\n };\n \n@@ -188,7 +188,7 @@\n };\n \n &hdmi1 {\n-\tdmas = <&dma (17|(1<<27)|(1<<24))>;\n+\tdmas = <&dma (17|(1<<27)|(1<<24)|(0<<16)|(15<<20))>;\n \tstatus = \"disabled\";\n };\n \n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0433-media-i2c-ov5647-Selection-compliance-fixes.patch",
    "content": "From 86d0f09da59d89d549c1ce4c0996d5c84e9d7d7a Mon Sep 17 00:00:00 2001\nFrom: Paul Elder <paul.elder@ideasonboard.com>\nDate: Tue, 22 Dec 2020 14:27:46 +0900\nSubject: [PATCH] media: i2c: ov5647: Selection compliance fixes\n\nTo comply with the intended usage of the V4L2 selection target when\nused to retrieve a sensor image properties, adjust the rectangles\nreturned by the ov5647 driver.\n\nThe top/left crop coordinates of the TGT_CROP rectangle were set to\n(0, 0) instead of (16, 16) which is the offset from the larger physical\npixel array rectangle. This was also a mismatch with the default values\ncrop rectangle value, so this is corrected. Found with v4l2-compliance.\n\nWhile at it, add V4L2_SEL_TGT_CROP_BOUNDS support: CROP_DEFAULT and\nCROP_BOUNDS have the same size as the non-active pixels are not readable\nusing the selection API. Found with v4l2-compliance.\n\nSigned-off-by: Paul Elder <paul.elder@ideasonboard.com>\n---\n drivers/media/i2c/ov5647.c | 21 +++++++++++----------\n 1 file changed, 11 insertions(+), 10 deletions(-)\n\n--- a/drivers/media/i2c/ov5647.c\n+++ b/drivers/media/i2c/ov5647.c\n@@ -606,8 +606,8 @@ static struct ov5647_mode supported_mode\n \t\t\t.height = 480\n \t\t},\n \t\t.crop = {\n-\t\t\t.left = 0,\n-\t\t\t.top = 0,\n+\t\t\t.left = OV5647_PIXEL_ARRAY_LEFT,\n+\t\t\t.top = OV5647_PIXEL_ARRAY_TOP,\n \t\t\t.width = 1280,\n \t\t\t.height = 960,\n \t\t},\n@@ -632,8 +632,8 @@ static struct ov5647_mode supported_mode\n \t\t\t.height = 1944\n \t\t},\n \t\t.crop = {\n-\t\t\t.left = 0,\n-\t\t\t.top = 0,\n+\t\t\t.left = OV5647_PIXEL_ARRAY_LEFT,\n+\t\t\t.top = OV5647_PIXEL_ARRAY_TOP,\n \t\t\t.width = 2592,\n \t\t\t.height = 1944\n \t\t},\n@@ -656,8 +656,8 @@ static struct ov5647_mode supported_mode\n \t\t\t.height = 1080\n \t\t},\n \t\t.crop = {\n-\t\t\t.left = 348,\n-\t\t\t.top = 434,\n+\t\t\t.left = 364,\n+\t\t\t.top = 450,\n \t\t\t.width = 1928,\n \t\t\t.height = 1080,\n \t\t},\n@@ -679,8 +679,8 @@ static struct ov5647_mode supported_mode\n \t\t\t.height = 972\n \t\t},\n \t\t.crop = {\n-\t\t\t.left = 0,\n-\t\t\t.top = 0,\n+\t\t\t.left = OV5647_PIXEL_ARRAY_LEFT,\n+\t\t\t.top = OV5647_PIXEL_ARRAY_TOP,\n \t\t\t.width = 2592,\n \t\t\t.height = 1944,\n \t\t},\n@@ -703,8 +703,8 @@ static struct ov5647_mode supported_mode\n \t\t\t.height = 480\n \t\t},\n \t\t.crop = {\n-\t\t\t.left = 16,\n-\t\t\t.top = 0,\n+\t\t\t.left = OV5647_PIXEL_ARRAY_LEFT,\n+\t\t\t.top = OV5647_PIXEL_ARRAY_TOP,\n \t\t\t.width = 2560,\n \t\t\t.height = 1920,\n \t\t},\n@@ -1080,6 +1080,7 @@ static int ov5647_get_selection(struct v\n \t\treturn 0;\n \n \tcase V4L2_SEL_TGT_CROP_DEFAULT:\n+\tcase V4L2_SEL_TGT_CROP_BOUNDS:\n \t\tsel->r.top = OV5647_PIXEL_ARRAY_TOP;\n \t\tsel->r.left = OV5647_PIXEL_ARRAY_LEFT;\n \t\tsel->r.width = OV5647_PIXEL_ARRAY_WIDTH;\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0434-overlays-give-Seeed-Studio-CAN-BUS-FD-HAT-a-v2-postf.patch",
    "content": "From 69da0bd66630848403a1ccbb927d5325fc54381e Mon Sep 17 00:00:00 2001\nFrom: Marc Kleine-Budde <mkl@pengutronix.de>\nDate: Sat, 2 Jan 2021 21:08:59 +0100\nSubject: [PATCH] overlays: give Seeed Studio CAN BUS FD HAT a -v2\n postfix\n\nThere are several versions of the Seeed Studio CAN BUS FD HAT. This is the\nsecond version, based on the mcp2518fd, so give it a -v2 postfix.\n\nSigned-off-by: Marc Kleine-Budde <mkl@pengutronix.de>\n---\n arch/arm/boot/dts/overlays/Makefile                       | 2 +-\n arch/arm/boot/dts/overlays/README                         | 8 ++++----\n ...fd-hat-overlay.dts => seeed-can-fd-hat-v2-overlay.dts} | 0\n 3 files changed, 5 insertions(+), 5 deletions(-)\n rename arch/arm/boot/dts/overlays/{seeed-can-fd-hat-overlay.dts => seeed-can-fd-hat-v2-overlay.dts} (100%)\n\n--- a/arch/arm/boot/dts/overlays/Makefile\n+++ b/arch/arm/boot/dts/overlays/Makefile\n@@ -161,7 +161,7 @@ dtbo-$(CONFIG_ARCH_BCM2835) += \\\n \tsc16is752-spi1.dtbo \\\n \tsdhost.dtbo \\\n \tsdio.dtbo \\\n-\tseeed-can-fd-hat.dtbo \\\n+\tseeed-can-fd-hat-v2.dtbo \\\n \tsh1106-spi.dtbo \\\n \tsmi.dtbo \\\n \tsmi-dev.dtbo \\\n--- a/arch/arm/boot/dts/overlays/README\n+++ b/arch/arm/boot/dts/overlays/README\n@@ -2504,11 +2504,11 @@ Info:   This overlay is now deprecated.\n Load:   <Deprecated>\n \n \n-Name:   seeed-can-fd-hat\n-Info:   Overlay for Seeed Studio CAN BUS FD HAT with two CAN FD channels and an\n-        RTC.\n+Name:   seeed-can-fd-hat-v2\n+Info:   Overlay for Seeed Studio CAN BUS FD HAT with two CAN FD channels\n+        (based on the mcp2518fd) and an RTC.\n         https://www.seeedstudio.com/CAN-BUS-FD-HAT-for-Raspberry-Pi-p-4742.html\n-Load:   dtoverlay=seeed-can-fd-hat\n+Load:   dtoverlay=seeed-can-fd-hat-v2\n Params: <None>\n \n \n--- a/arch/arm/boot/dts/overlays/seeed-can-fd-hat-overlay.dts\n+++ /dev/null\n@@ -1,117 +0,0 @@\n-// redo: ovmerge -c mcp251xfd-overlay.dts,spi0-0,interrupt=25 mcp251xfd-overlay.dts,spi0-1,interrupt=24 i2c-rtc-overlay.dts,pcf85063\n-\n-// Device tree overlay for https://www.seeedstudio.com/CAN-BUS-FD-HAT-for-Raspberry-Pi-p-4742.html \n-\n-/dts-v1/;\n-/plugin/;\n-\n-#include <dt-bindings/gpio/gpio.h>\n-#include <dt-bindings/interrupt-controller/irq.h>\n-#include <dt-bindings/pinctrl/bcm2835.h>\n-\n-/ {\n-\tcompatible = \"brcm,bcm2835\";\n-\tfragment@0 {\n-\t\ttarget = <&spidev0>;\n-\t\t__overlay__ {\n-\t\t\tstatus = \"disabled\";\n-\t\t};\n-\t};\n-\tfragment@1 {\n-\t\ttarget = <&gpio>;\n-\t\t__overlay__ {\n-\t\t\tmcp251xfd_pins: mcp251xfd_spi0_0_pins {\n-\t\t\t\tbrcm,pins = <25>;\n-\t\t\t\tbrcm,function = <BCM2835_FSEL_GPIO_IN>;\n-\t\t\t};\n-\t\t};\n-\t};\n-\tfragment@2 {\n-\t\ttarget-path = \"/clocks\";\n-\t\t__overlay__ {\n-\t\t\tclk_mcp251xfd_osc: mcp251xfd-spi0-0-osc {\n-\t\t\t\t#clock-cells = <0>;\n-\t\t\t\tcompatible = \"fixed-clock\";\n-\t\t\t\tclock-frequency = <40000000>;\n-\t\t\t};\n-\t\t};\n-\t};\n-\tfragment@3 {\n-\t\ttarget = <&spi0>;\n-\t\t__overlay__ {\n-\t\t\tstatus = \"okay\";\n-\t\t\t#address-cells = <1>;\n-\t\t\t#size-cells = <0>;\n-\t\t\tmcp251xfd@0 {\n-\t\t\t\tcompatible = \"microchip,mcp251xfd\";\n-\t\t\t\treg = <0>;\n-\t\t\t\tpinctrl-names = \"default\";\n-\t\t\t\tpinctrl-0 = <&mcp251xfd_pins>;\n-\t\t\t\tspi-max-frequency = <20000000>;\n-\t\t\t\tinterrupt-parent = <&gpio>;\n-\t\t\t\tinterrupts = <25 IRQ_TYPE_LEVEL_LOW>;\n-\t\t\t\tclocks = <&clk_mcp251xfd_osc>;\n-\t\t\t};\n-\t\t};\n-\t};\n-\tfragment@4 {\n-\t\ttarget = <&spidev1>;\n-\t\t__overlay__ {\n-\t\t\tstatus = \"disabled\";\n-\t\t};\n-\t};\n-\tfragment@5 {\n-\t\ttarget = <&gpio>;\n-\t\t__overlay__ {\n-\t\t\tmcp251xfd_pins_1: mcp251xfd_spi0_1_pins {\n-\t\t\t\tbrcm,pins = <24>;\n-\t\t\t\tbrcm,function = <BCM2835_FSEL_GPIO_IN>;\n-\t\t\t};\n-\t\t};\n-\t};\n-\tfragment@6 {\n-\t\ttarget-path = \"/clocks\";\n-\t\t__overlay__ {\n-\t\t\tclk_mcp251xfd_osc_1: mcp251xfd-spi0-1-osc {\n-\t\t\t\t#clock-cells = <0>;\n-\t\t\t\tcompatible = \"fixed-clock\";\n-\t\t\t\tclock-frequency = <40000000>;\n-\t\t\t};\n-\t\t};\n-\t};\n-\tfragment@7 {\n-\t\ttarget = <&spi0>;\n-\t\t__overlay__ {\n-\t\t\tstatus = \"okay\";\n-\t\t\t#address-cells = <1>;\n-\t\t\t#size-cells = <0>;\n-\t\t\tmcp251xfd@1 {\n-\t\t\t\tcompatible = \"microchip,mcp251xfd\";\n-\t\t\t\treg = <1>;\n-\t\t\t\tpinctrl-names = \"default\";\n-\t\t\t\tpinctrl-0 = <&mcp251xfd_pins_1>;\n-\t\t\t\tspi-max-frequency = <20000000>;\n-\t\t\t\tinterrupt-parent = <&gpio>;\n-\t\t\t\tinterrupts = <24 IRQ_TYPE_LEVEL_LOW>;\n-\t\t\t\tclocks = <&clk_mcp251xfd_osc_1>;\n-\t\t\t};\n-\t\t};\n-\t};\n-\tfragment@8 {\n-\t\ttarget = <&i2cbus>;\n-\t\t__overlay__ {\n-\t\t\t#address-cells = <1>;\n-\t\t\t#size-cells = <0>;\n-\t\t\tpcf85063@51 {\n-\t\t\t\tcompatible = \"nxp,pcf85063\";\n-\t\t\t\treg = <0x51>;\n-\t\t\t};\n-\t\t};\n-\t};\n-\tfragment@9 {\n-\t\ttarget = <&i2c_arm>;\n-\t\ti2cbus: __overlay__ {\n-\t\t\tstatus = \"okay\";\n-\t\t};\n-\t};\n-};\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/seeed-can-fd-hat-v2-overlay.dts\n@@ -0,0 +1,117 @@\n+// redo: ovmerge -c mcp251xfd-overlay.dts,spi0-0,interrupt=25 mcp251xfd-overlay.dts,spi0-1,interrupt=24 i2c-rtc-overlay.dts,pcf85063\n+\n+// Device tree overlay for https://www.seeedstudio.com/CAN-BUS-FD-HAT-for-Raspberry-Pi-p-4742.html \n+\n+/dts-v1/;\n+/plugin/;\n+\n+#include <dt-bindings/gpio/gpio.h>\n+#include <dt-bindings/interrupt-controller/irq.h>\n+#include <dt-bindings/pinctrl/bcm2835.h>\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\tfragment@0 {\n+\t\ttarget = <&spidev0>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\tfragment@1 {\n+\t\ttarget = <&gpio>;\n+\t\t__overlay__ {\n+\t\t\tmcp251xfd_pins: mcp251xfd_spi0_0_pins {\n+\t\t\t\tbrcm,pins = <25>;\n+\t\t\t\tbrcm,function = <BCM2835_FSEL_GPIO_IN>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\tfragment@2 {\n+\t\ttarget-path = \"/clocks\";\n+\t\t__overlay__ {\n+\t\t\tclk_mcp251xfd_osc: mcp251xfd-spi0-0-osc {\n+\t\t\t\t#clock-cells = <0>;\n+\t\t\t\tcompatible = \"fixed-clock\";\n+\t\t\t\tclock-frequency = <40000000>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\tfragment@3 {\n+\t\ttarget = <&spi0>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tmcp251xfd@0 {\n+\t\t\t\tcompatible = \"microchip,mcp251xfd\";\n+\t\t\t\treg = <0>;\n+\t\t\t\tpinctrl-names = \"default\";\n+\t\t\t\tpinctrl-0 = <&mcp251xfd_pins>;\n+\t\t\t\tspi-max-frequency = <20000000>;\n+\t\t\t\tinterrupt-parent = <&gpio>;\n+\t\t\t\tinterrupts = <25 IRQ_TYPE_LEVEL_LOW>;\n+\t\t\t\tclocks = <&clk_mcp251xfd_osc>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\tfragment@4 {\n+\t\ttarget = <&spidev1>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\tfragment@5 {\n+\t\ttarget = <&gpio>;\n+\t\t__overlay__ {\n+\t\t\tmcp251xfd_pins_1: mcp251xfd_spi0_1_pins {\n+\t\t\t\tbrcm,pins = <24>;\n+\t\t\t\tbrcm,function = <BCM2835_FSEL_GPIO_IN>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\tfragment@6 {\n+\t\ttarget-path = \"/clocks\";\n+\t\t__overlay__ {\n+\t\t\tclk_mcp251xfd_osc_1: mcp251xfd-spi0-1-osc {\n+\t\t\t\t#clock-cells = <0>;\n+\t\t\t\tcompatible = \"fixed-clock\";\n+\t\t\t\tclock-frequency = <40000000>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\tfragment@7 {\n+\t\ttarget = <&spi0>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tmcp251xfd@1 {\n+\t\t\t\tcompatible = \"microchip,mcp251xfd\";\n+\t\t\t\treg = <1>;\n+\t\t\t\tpinctrl-names = \"default\";\n+\t\t\t\tpinctrl-0 = <&mcp251xfd_pins_1>;\n+\t\t\t\tspi-max-frequency = <20000000>;\n+\t\t\t\tinterrupt-parent = <&gpio>;\n+\t\t\t\tinterrupts = <24 IRQ_TYPE_LEVEL_LOW>;\n+\t\t\t\tclocks = <&clk_mcp251xfd_osc_1>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\tfragment@8 {\n+\t\ttarget = <&i2cbus>;\n+\t\t__overlay__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tpcf85063@51 {\n+\t\t\t\tcompatible = \"nxp,pcf85063\";\n+\t\t\t\treg = <0x51>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\tfragment@9 {\n+\t\ttarget = <&i2c_arm>;\n+\t\ti2cbus: __overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+};\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0435-overlays-Add-overlay-for-Seeed-Studio-CAN-BUS-FD-HAT.patch",
    "content": "From a58855e02a8a0a0de898efcfb0e4790076a0d640 Mon Sep 17 00:00:00 2001\nFrom: Marc Kleine-Budde <mkl@pengutronix.de>\nDate: Sat, 2 Jan 2021 21:38:58 +0100\nSubject: [PATCH] overlays: Add overlay for Seeed Studio CAN BUS FD HAT\n v1 (based on mcp2517fd)\n\nThis patch adds the overlay for the Seeed Studio CAN BUS FD HAT v1 with two CAN\nFD Channels (based on mcp2517fd).\n\nhttps://www.seeedstudio.com/2-Channel-CAN-BUS-FD-Shield-for-Raspberry-Pi-p-4072.html\n\nThe overlay was generated by:\novmerge -c spi1-1cs-overlay.dts,cs0_pin=18,cs0_spidev=false \\\n           mcp251xfd-overlay.dts,spi0-0,interrupt=25 \\\n           mcp251xfd-overlay.dts,spi1-0,interrupt=24\n\nSigned-off-by: Marc Kleine-Budde <mkl@pengutronix.de>\n---\n arch/arm/boot/dts/overlays/Makefile           |   1 +\n arch/arm/boot/dts/overlays/README             |   8 +\n .../overlays/seeed-can-fd-hat-v1-overlay.dts  | 138 ++++++++++++++++++\n 3 files changed, 147 insertions(+)\n create mode 100644 arch/arm/boot/dts/overlays/seeed-can-fd-hat-v1-overlay.dts\n\n--- a/arch/arm/boot/dts/overlays/Makefile\n+++ b/arch/arm/boot/dts/overlays/Makefile\n@@ -161,6 +161,7 @@ dtbo-$(CONFIG_ARCH_BCM2835) += \\\n \tsc16is752-spi1.dtbo \\\n \tsdhost.dtbo \\\n \tsdio.dtbo \\\n+\tseeed-can-fd-hat-v1.dtbo \\\n \tseeed-can-fd-hat-v2.dtbo \\\n \tsh1106-spi.dtbo \\\n \tsmi.dtbo \\\n--- a/arch/arm/boot/dts/overlays/README\n+++ b/arch/arm/boot/dts/overlays/README\n@@ -2504,6 +2504,14 @@ Info:   This overlay is now deprecated.\n Load:   <Deprecated>\n \n \n+Name:   seeed-can-fd-hat-v1\n+Info:   Overlay for Seeed Studio CAN BUS FD HAT with two CAN FD channels\n+        (based on the mcp2517fd).\n+        https://www.seeedstudio.com/2-Channel-CAN-BUS-FD-Shield-for-Raspberry-Pi-p-4072.html\n+Load:   dtoverlay=seeed-can-fd-hat-v1\n+Params: <None>\n+\n+\n Name:   seeed-can-fd-hat-v2\n Info:   Overlay for Seeed Studio CAN BUS FD HAT with two CAN FD channels\n         (based on the mcp2518fd) and an RTC.\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/seeed-can-fd-hat-v1-overlay.dts\n@@ -0,0 +1,138 @@\n+// redo: ovmerge -c spi1-1cs-overlay.dts,cs0_pin=18,cs0_spidev=false mcp251xfd-overlay.dts,spi0-0,interrupt=25 mcp251xfd-overlay.dts,spi1-0,interrupt=24\n+\n+// Device tree overlay for https://www.seeedstudio.com/2-Channel-CAN-BUS-FD-Shield-for-Raspberry-Pi-p-4072.html\n+\n+/dts-v1/;\n+/plugin/;\n+\n+#include <dt-bindings/gpio/gpio.h>\n+#include <dt-bindings/interrupt-controller/irq.h>\n+#include <dt-bindings/pinctrl/bcm2835.h>\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\tfragment@0 {\n+\t\ttarget = <&gpio>;\n+\t\t__overlay__ {\n+\t\t\tspi1_pins: spi1_pins {\n+\t\t\t\tbrcm,pins = <19 20 21>;\n+\t\t\t\tbrcm,function = <3>;\n+\t\t\t};\n+\t\t\tspi1_cs_pins: spi1_cs_pins {\n+\t\t\t\tbrcm,pins = <18>;\n+\t\t\t\tbrcm,function = <1>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\tfragment@1 {\n+\t\ttarget = <&spi1>;\n+\t\t__overlay__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&spi1_pins &spi1_cs_pins>;\n+\t\t\tcs-gpios = <&gpio 18 1>;\n+\t\t\tstatus = \"okay\";\n+\t\t\tspidev@0 {\n+\t\t\t\tcompatible = \"spidev\";\n+\t\t\t\treg = <0>;\n+\t\t\t\t#address-cells = <1>;\n+\t\t\t\t#size-cells = <0>;\n+\t\t\t\tspi-max-frequency = <125000000>;\n+\t\t\t\tstatus = \"disabled\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\tfragment@2 {\n+\t\ttarget = <&aux>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\tfragment@3 {\n+\t\ttarget = <&spidev0>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\tfragment@4 {\n+\t\ttarget = <&gpio>;\n+\t\t__overlay__ {\n+\t\t\tmcp251xfd_pins: mcp251xfd_spi0_0_pins {\n+\t\t\t\tbrcm,pins = <25>;\n+\t\t\t\tbrcm,function = <BCM2835_FSEL_GPIO_IN>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\tfragment@5 {\n+\t\ttarget-path = \"/clocks\";\n+\t\t__overlay__ {\n+\t\t\tclk_mcp251xfd_osc: mcp251xfd-spi0-0-osc {\n+\t\t\t\t#clock-cells = <0>;\n+\t\t\t\tcompatible = \"fixed-clock\";\n+\t\t\t\tclock-frequency = <40000000>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\tfragment@6 {\n+\t\ttarget = <&spi0>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tmcp251xfd@0 {\n+\t\t\t\tcompatible = \"microchip,mcp251xfd\";\n+\t\t\t\treg = <0>;\n+\t\t\t\tpinctrl-names = \"default\";\n+\t\t\t\tpinctrl-0 = <&mcp251xfd_pins>;\n+\t\t\t\tspi-max-frequency = <20000000>;\n+\t\t\t\tinterrupt-parent = <&gpio>;\n+\t\t\t\tinterrupts = <25 IRQ_TYPE_LEVEL_LOW>;\n+\t\t\t\tclocks = <&clk_mcp251xfd_osc>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\tfragment@7 {\n+\t\ttarget-path = \"spi1/spidev@0\";\n+\t\t__overlay__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\tfragment@8 {\n+\t\ttarget = <&gpio>;\n+\t\t__overlay__ {\n+\t\t\tmcp251xfd_pins_1: mcp251xfd_spi1_0_pins {\n+\t\t\t\tbrcm,pins = <24>;\n+\t\t\t\tbrcm,function = <BCM2835_FSEL_GPIO_IN>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\tfragment@9 {\n+\t\ttarget-path = \"/clocks\";\n+\t\t__overlay__ {\n+\t\t\tclk_mcp251xfd_osc_1: mcp251xfd-spi1-0-osc {\n+\t\t\t\t#clock-cells = <0>;\n+\t\t\t\tcompatible = \"fixed-clock\";\n+\t\t\t\tclock-frequency = <40000000>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\tfragment@10 {\n+\t\ttarget = <&spi1>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tmcp251xfd@0 {\n+\t\t\t\tcompatible = \"microchip,mcp251xfd\";\n+\t\t\t\treg = <0>;\n+\t\t\t\tpinctrl-names = \"default\";\n+\t\t\t\tpinctrl-0 = <&mcp251xfd_pins_1>;\n+\t\t\t\tspi-max-frequency = <20000000>;\n+\t\t\t\tinterrupt-parent = <&gpio>;\n+\t\t\t\tinterrupts = <24 IRQ_TYPE_LEVEL_LOW>;\n+\t\t\t\tclocks = <&clk_mcp251xfd_osc_1>;\n+\t\t\t};\n+\t\t};\n+\t};\n+};\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0436-overlays-add-wm8960-soundcard-overlay.patch",
    "content": "From fcfad9655db52b44c8e26727be97dea78531eea5 Mon Sep 17 00:00:00 2001\nFrom: Aaron Shaw <shawaj@gmail.com>\nDate: Sat, 2 Jan 2021 02:34:03 +0000\nSubject: [PATCH] overlays: add wm8960-soundcard overlay\n\nadd overlay for waveshare wm8960 simple-audio-card\n\nChange-type: patch\nSigned-off-by: Aaron Shaw <shawaj@gmail.com>\n---\n arch/arm/boot/dts/overlays/Makefile           |  3 +-\n arch/arm/boot/dts/overlays/README             |  7 ++\n .../dts/overlays/wm8960-soundcard-overlay.dts | 82 +++++++++++++++++++\n 3 files changed, 91 insertions(+), 1 deletion(-)\n create mode 100644 arch/arm/boot/dts/overlays/wm8960-soundcard-overlay.dts\n\n--- a/arch/arm/boot/dts/overlays/Makefile\n+++ b/arch/arm/boot/dts/overlays/Makefile\n@@ -213,7 +213,8 @@ dtbo-$(CONFIG_ARCH_BCM2835) += \\\n \tw1-gpio.dtbo \\\n \tw1-gpio-pullup.dtbo \\\n \tw5500.dtbo \\\n-\twittypi.dtbo\n+\twittypi.dtbo \\\n+\twm8960-soundcard.dtbo\n \n targets += dtbs dtbs_install\n targets += $(dtbo-y)\n--- a/arch/arm/boot/dts/overlays/README\n+++ b/arch/arm/boot/dts/overlays/README\n@@ -3127,6 +3127,13 @@ Params: led_gpio                GPIO for\n                                 \"default-on\")\n \n \n+Name:   wm8960-soundcard\n+Info:   Overlay for the Waveshare wm8960 soundcard\n+Load:   dtoverlay=wm8960-soundcard,<param>=<val>\n+Params: alsaname                Changes the card name in ALSA\n+        compatible              Changes the codec compatibility\n+\n+\n Troubleshooting\n ===============\n \n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/wm8960-soundcard-overlay.dts\n@@ -0,0 +1,82 @@\n+// Definitions for Waveshare WM8960 https://github.com/waveshare/WM8960-Audio-HAT\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&i2s>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget-path=\"/\";\n+\t\t__overlay__ {\n+\t\t\twm8960_mclk: wm8960_mclk {\n+\t\t\t\tcompatible = \"fixed-clock\";\n+\t\t\t\t#clock-cells = <0>;\n+\t\t\t\tclock-frequency = <12288000>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\tfragment@2 {\n+\t\ttarget = <&i2c1>;\n+\t\t__overlay__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\twm8960: wm8960 {\n+\t\t\t\tcompatible = \"wlf,wm8960\";\n+\t\t\t\treg = <0x1a>;\n+\t\t\t\t#sound-dai-cells = <0>;\n+\t\t\t\tAVDD-supply = <&vdd_5v0_reg>;\n+\t\t\t\tDVDD-supply = <&vdd_3v3_reg>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\n+\tfragment@3 {\n+\t\ttarget = <&sound>;\n+\t\tslave_overlay: __overlay__ {\n+\t\t\tcompatible = \"simple-audio-card\";\n+\t\t\tsimple-audio-card,format = \"i2s\";\n+\t\t\tsimple-audio-card,name = \"wm8960-soundcard\"; \n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tsimple-audio-card,widgets =\n+\t\t\t\t\"Microphone\", \"Mic Jack\",\n+\t\t\t\t\"Line\", \"Line In\",\n+\t\t\t\t\"Line\", \"Line Out\",\n+\t\t\t\t\"Speaker\", \"Speaker\",\n+\t\t\t\t\"Headphone\", \"Headphone Jack\";\n+\t\t\tsimple-audio-card,routing =\n+\t\t\t\t\"Headphone Jack\", \"HP_L\",\n+\t\t\t\t\"Headphone Jack\", \"HP_R\",\n+\t\t\t\t\"Speaker\", \"SPK_LP\",\n+\t\t\t\t\"Speaker\", \"SPK_LN\",\n+\t\t\t\t\"LINPUT1\", \"Mic Jack\",\n+\t\t\t\t\"LINPUT3\", \"Mic Jack\",\n+\t\t\t\t\"RINPUT1\", \"Mic Jack\",\n+\t\t\t\t\"RINPUT2\", \"Mic Jack\";\n+\n+\t\t\tsimple-audio-card,cpu {\n+\t\t\t\tsound-dai = <&i2s>;\n+\t\t\t};\n+\t\t\tdailink0_slave: simple-audio-card,codec {\n+\t\t\t\tsound-dai = <&wm8960>;\n+\t\t\t\tclocks = <&wm8960_mclk>;\n+\t\t\t\tclock-names = \"mclk\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\talsaname = <&slave_overlay>,\"simple-audio-card,name\";\n+\t\tcompatible = <&wm8960>,\"compatible\";\n+\t};\n+};\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0437-overlays-add-spi-override-to-merus-amp-overlay.patch",
    "content": "From e4ba525d61b49bd7355356ccc5eb76026f986c0a Mon Sep 17 00:00:00 2001\nFrom: Aaron Shaw <shawaj@gmail.com>\nDate: Sat, 26 Dec 2020 03:13:14 +0000\nSubject: [PATCH] overlays: add spi override to merus-amp overlay\n\nadds an override to the merus-amp overlay to turn the spi bus off\n\nChange-type: patch\nSigned-off-by: Aaron Shaw <shawaj@gmail.com>\n---\n arch/arm/boot/dts/overlays/README                |  4 ++--\n arch/arm/boot/dts/overlays/merus-amp-overlay.dts | 10 ++++++++++\n 2 files changed, 12 insertions(+), 2 deletions(-)\n\n--- a/arch/arm/boot/dts/overlays/README\n+++ b/arch/arm/boot/dts/overlays/README\n@@ -1914,8 +1914,8 @@ Params: speed                   Display\n \n Name:   merus-amp\n Info:   Configures the merus-amp audio card\n-Load:   dtoverlay=merus-amp\n-Params: <None>\n+Load:   dtoverlay=merus-amp,<param>=<val>\n+Params: spioff                  Turn SPI bus off\n \n \n Name:   midi-uart0\n--- a/arch/arm/boot/dts/overlays/merus-amp-overlay.dts\n+++ b/arch/arm/boot/dts/overlays/merus-amp-overlay.dts\n@@ -57,4 +57,14 @@\n \t\t\tstatus = \"okay\";\n \t\t};\n \t};\n+\n+\tfragment@4 {\n+\t\ttarget = <&spi0>;\n+\t\tfrag4: __overlay__ {\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\tspioff = <&frag4>, \"status=disabled\";\n+\t};\n };\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0438-dt-Add-a-camera-regulator-node-to-all-downstream-Pi-.patch",
    "content": "From 7782ca4dcb10a244ae476126220890a0843c439e Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Wed, 6 Jan 2021 17:28:57 +0000\nSubject: [PATCH] dt: Add a camera regulator node to all downstream Pi\n platforms\n\nThe current firmware fixup of camera sensor overlays is not\nparticularly nice, and it stops you being able to load them\ndynamically.\nIt's also incompatible with creating a simple DT that can be\nloaded for both CAM1 and CAM0 on a CM as they would both\ntry to claim the one GPIO.\n\nAlmost all sensors have a hook of some form for a regulator, so\nit's relatively straightforward to convert them all to use a\nfixed regulator with GPIO control.\n\nAdd a fixed regulator node for each platform with the GPIO\ncorrectly configured for the camera shutdown line. (The LED line\nis ignored).\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n arch/arm/boot/dts/bcm2708-rpi-b-plus.dts          |  5 +++++\n arch/arm/boot/dts/bcm2708-rpi-b-rev1.dts          |  5 +++++\n arch/arm/boot/dts/bcm2708-rpi-b.dts               |  5 +++++\n arch/arm/boot/dts/bcm2708-rpi-cm.dts              | 15 +++++++++++++++\n arch/arm/boot/dts/bcm2708-rpi-zero-w.dts          |  5 +++++\n arch/arm/boot/dts/bcm2708-rpi-zero.dts            |  5 +++++\n arch/arm/boot/dts/bcm2709-rpi-2-b.dts             |  5 +++++\n arch/arm/boot/dts/bcm2710-rpi-2-b.dts             |  5 +++++\n arch/arm/boot/dts/bcm2710-rpi-3-b-plus.dts        |  5 +++++\n arch/arm/boot/dts/bcm2710-rpi-3-b.dts             |  5 +++++\n arch/arm/boot/dts/bcm2710-rpi-cm3.dts             | 15 +++++++++++++++\n arch/arm/boot/dts/bcm2711-rpi-4-b.dts             |  5 +++++\n arch/arm/boot/dts/bcm2711-rpi-cm4.dts             |  8 ++++++++\n arch/arm/boot/dts/bcm283x-rpi-cam1-regulator.dtsi | 10 ++++++++++\n 14 files changed, 98 insertions(+)\n create mode 100644 arch/arm/boot/dts/bcm283x-rpi-cam1-regulator.dtsi\n\n--- a/arch/arm/boot/dts/bcm2708-rpi-b-plus.dts\n+++ b/arch/arm/boot/dts/bcm2708-rpi-b-plus.dts\n@@ -5,6 +5,7 @@\n #include \"bcm283x-rpi-smsc9514.dtsi\"\n #include \"bcm283x-rpi-csi1-2lane.dtsi\"\n #include \"bcm283x-rpi-i2c0mux_0_28.dtsi\"\n+#include \"bcm283x-rpi-cam1-regulator.dtsi\"\n \n / {\n \tcompatible = \"raspberrypi,model-b-plus\", \"brcm,bcm2835\";\n@@ -111,6 +112,10 @@\n \tpinctrl-0 = <&audio_pins>;\n };\n \n+&cam1_reg {\n+\tgpio = <&gpio 41 GPIO_ACTIVE_HIGH>;\n+};\n+\n / {\n \t__overrides__ {\n \t\tact_led_gpio = <&act_led>,\"gpios:4\";\n--- a/arch/arm/boot/dts/bcm2708-rpi-b-rev1.dts\n+++ b/arch/arm/boot/dts/bcm2708-rpi-b-rev1.dts\n@@ -4,6 +4,7 @@\n #include \"bcm2708-rpi.dtsi\"\n #include \"bcm283x-rpi-smsc9512.dtsi\"\n #include \"bcm283x-rpi-csi1-2lane.dtsi\"\n+#include \"bcm283x-rpi-cam1-regulator.dtsi\"\n \n / {\n \tcompatible = \"raspberrypi,model-b\", \"brcm,bcm2835\";\n@@ -118,6 +119,10 @@ i2c_csi_dsi: &i2c1 {\n \tpinctrl-0 = <&audio_pins>;\n };\n \n+&cam1_reg {\n+\tgpio = <&gpio 27 GPIO_ACTIVE_HIGH>;\n+};\n+\n / {\n \t__overrides__ {\n \t\tact_led_gpio = <&act_led>,\"gpios:4\";\n--- a/arch/arm/boot/dts/bcm2708-rpi-b.dts\n+++ b/arch/arm/boot/dts/bcm2708-rpi-b.dts\n@@ -5,6 +5,7 @@\n #include \"bcm283x-rpi-smsc9512.dtsi\"\n #include \"bcm283x-rpi-csi1-2lane.dtsi\"\n #include \"bcm283x-rpi-i2c0mux_0_28.dtsi\"\n+#include \"bcm283x-rpi-cam1-regulator.dtsi\"\n \n / {\n \tcompatible = \"raspberrypi,model-b\", \"brcm,bcm2835\";\n@@ -105,6 +106,10 @@\n \tpinctrl-0 = <&audio_pins>;\n };\n \n+&cam1_reg {\n+\tgpio = <&gpio 21 GPIO_ACTIVE_HIGH>;\n+};\n+\n / {\n \t__overrides__ {\n \t\tact_led_gpio = <&act_led>,\"gpios:4\";\n--- a/arch/arm/boot/dts/bcm2708-rpi-cm.dts\n+++ b/arch/arm/boot/dts/bcm2708-rpi-cm.dts\n@@ -8,6 +8,21 @@\n / {\n \tcompatible = \"raspberrypi,compute-module\", \"brcm,bcm2835\";\n \tmodel = \"Raspberry Pi Compute Module\";\n+\n+\tcam1_reg: cam1_reg {\n+\t\tcompatible = \"regulator-fixed\";\n+\t\tregulator-name = \"cam1-regulator\";\n+\t\tgpio = <&gpio 2 GPIO_ACTIVE_HIGH>;\n+\t\tenable-active-high;\n+\t\tstatus = \"disabled\";\n+\t};\n+\tcam0_reg: cam0_reg {\n+\t\tcompatible = \"regulator-fixed\";\n+\t\tregulator-name = \"cam0-regulator\";\n+\t\tgpio = <&gpio 30 GPIO_ACTIVE_HIGH>;\n+\t\tenable-active-high;\n+\t\tstatus = \"disabled\";\n+\t};\n };\n \n &uart0 {\n--- a/arch/arm/boot/dts/bcm2708-rpi-zero-w.dts\n+++ b/arch/arm/boot/dts/bcm2708-rpi-zero-w.dts\n@@ -5,6 +5,7 @@\n #include \"bcm283x-rpi-csi1-2lane.dtsi\"\n #include \"bcm283x-rpi-i2c0mux_0_28.dtsi\"\n #include \"bcm2708-rpi-bt.dtsi\"\n+#include \"bcm283x-rpi-cam1-regulator.dtsi\"\n \n / {\n \tcompatible = \"raspberrypi,model-zero-w\", \"brcm,bcm2835\";\n@@ -155,6 +156,10 @@\n \tbrcm,disable-headphones = <1>;\n };\n \n+&cam1_reg {\n+\tgpio = <&gpio 44 GPIO_ACTIVE_HIGH>;\n+};\n+\n / {\n \t__overrides__ {\n \t\tact_led_gpio = <&act_led>,\"gpios:4\";\n--- a/arch/arm/boot/dts/bcm2708-rpi-zero.dts\n+++ b/arch/arm/boot/dts/bcm2708-rpi-zero.dts\n@@ -4,6 +4,7 @@\n #include \"bcm2708-rpi.dtsi\"\n #include \"bcm283x-rpi-csi1-2lane.dtsi\"\n #include \"bcm283x-rpi-i2c0mux_0_28.dtsi\"\n+#include \"bcm283x-rpi-cam1-regulator.dtsi\"\n \n / {\n \tcompatible = \"raspberrypi,model-zero\", \"brcm,bcm2835\";\n@@ -109,6 +110,10 @@\n \tbrcm,disable-headphones = <1>;\n };\n \n+&cam1_reg {\n+\tgpio = <&gpio 41 GPIO_ACTIVE_HIGH>;\n+};\n+\n / {\n \t__overrides__ {\n \t\tact_led_gpio = <&act_led>,\"gpios:4\";\n--- a/arch/arm/boot/dts/bcm2709-rpi-2-b.dts\n+++ b/arch/arm/boot/dts/bcm2709-rpi-2-b.dts\n@@ -5,6 +5,7 @@\n #include \"bcm283x-rpi-smsc9514.dtsi\"\n #include \"bcm283x-rpi-csi1-2lane.dtsi\"\n #include \"bcm283x-rpi-i2c0mux_0_28.dtsi\"\n+#include \"bcm283x-rpi-cam1-regulator.dtsi\"\n \n / {\n \tcompatible = \"raspberrypi,2-model-b\", \"brcm,bcm2836\";\n@@ -111,6 +112,10 @@\n \tpinctrl-0 = <&audio_pins>;\n };\n \n+&cam1_reg {\n+\tgpio = <&gpio 41 GPIO_ACTIVE_HIGH>;\n+};\n+\n / {\n \t__overrides__ {\n \t\tact_led_gpio = <&act_led>,\"gpios:4\";\n--- a/arch/arm/boot/dts/bcm2710-rpi-2-b.dts\n+++ b/arch/arm/boot/dts/bcm2710-rpi-2-b.dts\n@@ -5,6 +5,7 @@\n #include \"bcm283x-rpi-smsc9514.dtsi\"\n #include \"bcm283x-rpi-csi1-2lane.dtsi\"\n #include \"bcm283x-rpi-i2c0mux_0_28.dtsi\"\n+#include \"bcm283x-rpi-cam1-regulator.dtsi\"\n \n / {\n \tcompatible = \"raspberrypi,2-model-b-rev2\", \"brcm,bcm2837\";\n@@ -111,6 +112,10 @@\n \tpinctrl-0 = <&audio_pins>;\n };\n \n+&cam1_reg {\n+\tgpio = <&gpio 41 GPIO_ACTIVE_HIGH>;\n+};\n+\n / {\n \t__overrides__ {\n \t\tact_led_gpio = <&act_led>,\"gpios:4\";\n--- a/arch/arm/boot/dts/bcm2710-rpi-3-b-plus.dts\n+++ b/arch/arm/boot/dts/bcm2710-rpi-3-b-plus.dts\n@@ -6,6 +6,7 @@\n #include \"bcm283x-rpi-csi1-2lane.dtsi\"\n #include \"bcm283x-rpi-i2c0mux_0_44.dtsi\"\n #include \"bcm271x-rpi-bt.dtsi\"\n+#include \"bcm283x-rpi-cam1-regulator.dtsi\"\n \n / {\n \tcompatible = \"raspberrypi,3-model-b-plus\", \"brcm,bcm2837\";\n@@ -176,6 +177,10 @@\n \tmicrochip,downshift-after = <2>;\n };\n \n+&cam1_reg {\n+\tgpio = <&expgpio 5 GPIO_ACTIVE_HIGH>;\n+};\n+\n / {\n \t__overrides__ {\n \t\tact_led_gpio = <&act_led>,\"gpios:4\";\n--- a/arch/arm/boot/dts/bcm2710-rpi-3-b.dts\n+++ b/arch/arm/boot/dts/bcm2710-rpi-3-b.dts\n@@ -6,6 +6,7 @@\n #include \"bcm283x-rpi-csi1-2lane.dtsi\"\n #include \"bcm283x-rpi-i2c0mux_0_44.dtsi\"\n #include \"bcm271x-rpi-bt.dtsi\"\n+#include \"bcm283x-rpi-cam1-regulator.dtsi\"\n \n / {\n \tcompatible = \"raspberrypi,3-model-b\", \"brcm,bcm2837\";\n@@ -185,6 +186,10 @@\n \tpinctrl-0 = <&audio_pins>;\n };\n \n+&cam1_reg {\n+\tgpio = <&expgpio 5 GPIO_ACTIVE_HIGH>;\n+};\n+\n / {\n \t__overrides__ {\n \t\tact_led_gpio = <&act_led>,\"gpios:4\";\n--- a/arch/arm/boot/dts/bcm2710-rpi-cm3.dts\n+++ b/arch/arm/boot/dts/bcm2710-rpi-cm3.dts\n@@ -8,6 +8,21 @@\n / {\n \tcompatible = \"raspberrypi,3-compute-module\", \"brcm,bcm2837\";\n \tmodel = \"Raspberry Pi Compute Module 3\";\n+\n+\tcam1_reg: cam1_reg {\n+\t\tcompatible = \"regulator-fixed\";\n+\t\tregulator-name = \"cam1-regulator\";\n+\t\tgpio = <&gpio 2 GPIO_ACTIVE_HIGH>;\n+\t\tenable-active-high;\n+\t\tstatus = \"disabled\";\n+\t};\n+\tcam0_reg: cam0_reg {\n+\t\tcompatible = \"regulator-fixed\";\n+\t\tregulator-name = \"cam0-regulator\";\n+\t\tgpio = <&gpio 30 GPIO_ACTIVE_HIGH>;\n+\t\tenable-active-high;\n+\t\tstatus = \"disabled\";\n+\t};\n };\n \n &uart0 {\n--- a/arch/arm/boot/dts/bcm2711-rpi-4-b.dts\n+++ b/arch/arm/boot/dts/bcm2711-rpi-4-b.dts\n@@ -320,6 +320,7 @@\n #include \"bcm2711-rpi.dtsi\"\n #include \"bcm283x-rpi-csi1-2lane.dtsi\"\n #include \"bcm283x-rpi-i2c0mux_0_44.dtsi\"\n+#include \"bcm283x-rpi-cam1-regulator.dtsi\"\n \n / {\n \tchosen {\n@@ -586,6 +587,10 @@\n \tpinctrl-0 = <&audio_pins>;\n };\n \n+&cam1_reg {\n+\tgpio = <&expgpio 5 GPIO_ACTIVE_HIGH>;\n+};\n+\n / {\n \t__overrides__ {\n \t\tact_led_gpio = <&act_led>,\"gpios:4\";\n--- a/arch/arm/boot/dts/bcm2711-rpi-cm4.dts\n+++ b/arch/arm/boot/dts/bcm2711-rpi-cm4.dts\n@@ -327,6 +327,14 @@\n \t};\n \n \t/delete-node/ wifi-pwrseq;\n+\n+\tcam0_reg: cam1_reg: cam1_reg {\n+\t\tcompatible = \"regulator-fixed\";\n+\t\tregulator-name = \"cam1-reg\";\n+\t\tgpio = <&expgpio 5 GPIO_ACTIVE_HIGH>;\n+\t\tenable-active-high;\n+\t\tstatus = \"disabled\";\n+\t};\n };\n \n &mmcnr {\n--- /dev/null\n+++ b/arch/arm/boot/dts/bcm283x-rpi-cam1-regulator.dtsi\n@@ -0,0 +1,10 @@\n+// SPDX-License-Identifier: GPL-2.0\n+\n+/ {\n+\tcam1_reg: cam1_reg {\n+\t\tcompatible = \"regulator-fixed\";\n+\t\tregulator-name = \"cam1-reg\";\n+\t\tenable-active-high;\n+\t\tstatus = \"disabled\";\n+\t};\n+};\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0439-dtoverlays-Update-sensor-overlays-to-use-cam1_reg-wh.patch",
    "content": "From ca1159109b527af8450b627936c6eb732f496c14 Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Wed, 6 Jan 2021 17:42:31 +0000\nSubject: [PATCH] dtoverlays: Update sensor overlays to use cam1_reg\n where possible\n\nUpdate those overlays that use the regulator framework to use the\nnew cam1_reg node to control the camera shutdown line, and remove\nthe firmware workaround nodes.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n arch/arm/boot/dts/overlays/imx219-overlay.dts | 18 +++++---------\n .../boot/dts/overlays/imx290_327-overlay.dtsi | 18 +++++---------\n arch/arm/boot/dts/overlays/imx477-overlay.dts | 24 +++++++------------\n arch/arm/boot/dts/overlays/ov7251-overlay.dts | 18 +++++---------\n arch/arm/boot/dts/overlays/ov9281-overlay.dts | 19 ++++++---------\n 5 files changed, 34 insertions(+), 63 deletions(-)\n\n--- a/arch/arm/boot/dts/overlays/imx219-overlay.dts\n+++ b/arch/arm/boot/dts/overlays/imx219-overlay.dts\n@@ -23,7 +23,7 @@\n \t\t\t\tclocks = <&imx219_clk>;\n \t\t\t\tclock-names = \"xclk\";\n \n-\t\t\t\tVANA-supply = <&imx219_vana>;\t/* 2.8v */\n+\t\t\t\tVANA-supply = <&cam1_reg>;\t/* 2.8v */\n \t\t\t\tVDIG-supply = <&imx219_vdig>;\t/* 1.8v */\n \t\t\t\tVDDL-supply = <&imx219_vddl>;\t/* 1.2v */\n \n@@ -69,14 +69,6 @@\n \tfragment@3 {\n \t\ttarget-path=\"/\";\n \t\t__overlay__ {\n-\t\t\timx219_vana: fixedregulator@0 {\n-\t\t\t\tcompatible = \"regulator-fixed\";\n-\t\t\t\tregulator-name = \"imx219_vana\";\n-\t\t\t\tregulator-min-microvolt = <2800000>;\n-\t\t\t\tregulator-max-microvolt = <2800000>;\n-\t\t\t\tgpio = <&gpio 41 GPIO_ACTIVE_HIGH>;\n-\t\t\t\tenable-active-high;\n-\t\t\t};\n \t\t\timx219_vdig: fixedregulator@1 {\n \t\t\t\tcompatible = \"regulator-fixed\";\n \t\t\t\tregulator-name = \"imx219_vdig\";\n@@ -106,10 +98,12 @@\n \t};\n \n \tfragment@5 {\n-\t\ttarget-path=\"/__overrides__\";\n+\t\ttarget = <&cam1_reg>;\n \t\t__overlay__ {\n-\t\t\tcam0-pwdn-ctrl = <&imx219_vana>,\"gpio:0\";\n-\t\t\tcam0-pwdn      = <&imx219_vana>,\"gpio:4\";\n+\t\t\tstatus = \"okay\";\n+\t\t\tregulator-name = \"imx219_vana\";\n+\t\t\tregulator-min-microvolt = <2800000>;\n+\t\t\tregulator-max-microvolt = <2800000>;\n \t\t};\n \t};\n \n--- a/arch/arm/boot/dts/overlays/imx290_327-overlay.dtsi\n+++ b/arch/arm/boot/dts/overlays/imx290_327-overlay.dtsi\n@@ -24,7 +24,7 @@\n \t\t\t\tclock-names = \"xclk\";\n \t\t\t\tclock-frequency = <37125000>;\n \n-\t\t\t\tvdda-supply = <&imx290_vdda>;\t/* 2.8v */\n+\t\t\t\tvdda-supply = <&cam1_reg>;\t/* 2.8v */\n \t\t\t\tvdddo-supply = <&imx290_vdddo>;\t/* 1.8v */\n \t\t\t\tvddd-supply = <&imx290_vddd>;\t/* 1.5v */\n \n@@ -61,14 +61,6 @@\n \tfragment@3 {\n \t\ttarget-path=\"/\";\n \t\t__overlay__ {\n-\t\t\timx290_vdda: fixedregulator@0 {\n-\t\t\t\tcompatible = \"regulator-fixed\";\n-\t\t\t\tregulator-name = \"imx290_vdda\";\n-\t\t\t\tregulator-min-microvolt = <2800000>;\n-\t\t\t\tregulator-max-microvolt = <2800000>;\n-\t\t\t\tgpio = <&gpio 41 GPIO_ACTIVE_HIGH>;\n-\t\t\t\tenable-active-high;\n-\t\t\t};\n \t\t\timx290_vdddo: fixedregulator@1 {\n \t\t\t\tcompatible = \"regulator-fixed\";\n \t\t\t\tregulator-name = \"imx290_vdddo\";\n@@ -98,10 +90,12 @@\n \t};\n \n \tfragment@5 {\n-\t\ttarget-path=\"/__overrides__\";\n+\t\ttarget = <&cam1_reg>;\n \t\t__overlay__ {\n-\t\t\tcam0-pwdn-ctrl = <&imx290_vdda>,\"gpio:0\";\n-\t\t\tcam0-pwdn      = <&imx290_vdda>,\"gpio:4\";\n+\t\t\tstatus = \"okay\";\n+\t\t\tregulator-name = \"imx290_vdda\";\n+\t\t\tregulator-min-microvolt = <2800000>;\n+\t\t\tregulator-max-microvolt = <2800000>;\n \t\t};\n \t};\n \n--- a/arch/arm/boot/dts/overlays/imx477-overlay.dts\n+++ b/arch/arm/boot/dts/overlays/imx477-overlay.dts\n@@ -23,7 +23,7 @@\n \t\t\t\tclocks = <&imx477_clk>;\n \t\t\t\tclock-names = \"xclk\";\n \n-\t\t\t\tVANA-supply = <&imx477_vana>;\t/* 2.8v */\n+\t\t\t\tVANA-supply = <&cam1_reg>;\t/* 2.8v */\n \t\t\t\tVDIG-supply = <&imx477_vdig>;\t/* 1.05v */\n \t\t\t\tVDDL-supply = <&imx477_vddl>;\t/* 1.8v */\n \n@@ -69,22 +69,13 @@\n \tfragment@3 {\n \t\ttarget-path=\"/\";\n \t\t__overlay__ {\n-\t\t\timx477_vana: fixedregulator@0 {\n-\t\t\t\tcompatible = \"regulator-fixed\";\n-\t\t\t\tregulator-name = \"imx477_vana\";\n-\t\t\t\tregulator-min-microvolt = <2800000>;\n-\t\t\t\tregulator-max-microvolt = <2800000>;\n-\t\t\t\tgpio = <&gpio 41 GPIO_ACTIVE_HIGH>;\n-\t\t\t\tenable-active-high;\n-\t\t\t\tstartup-delay-us = <300000>;\n-\t\t\t};\n-\t\t\timx477_vdig: fixedregulator@1 {\n+\t\t\timx477_vdig: fixedregulator@0 {\n \t\t\t\tcompatible = \"regulator-fixed\";\n \t\t\t\tregulator-name = \"imx477_vdig\";\n \t\t\t\tregulator-min-microvolt = <1050000>;\n \t\t\t\tregulator-max-microvolt = <1050000>;\n \t\t\t};\n-\t\t\timx477_vddl: fixedregulator@2 {\n+\t\t\timx477_vddl: fixedregulator@1 {\n \t\t\t\tcompatible = \"regulator-fixed\";\n \t\t\t\tregulator-name = \"imx477_vddl\";\n \t\t\t\tregulator-min-microvolt = <1800000>;\n@@ -106,10 +97,13 @@\n \t};\n \n \tfragment@5 {\n-\t\ttarget-path=\"/__overrides__\";\n+\t\ttarget = <&cam1_reg>;\n \t\t__overlay__ {\n-\t\t\tcam0-pwdn-ctrl = <&imx477_vana>,\"gpio:0\";\n-\t\t\tcam0-pwdn      = <&imx477_vana>,\"gpio:4\";\n+\t\t\tstatus = \"okay\";\n+\t\t\tregulator-name = \"imx477_vana\";\n+\t\t\tstartup-delay-us = <300000>;\n+\t\t\tregulator-min-microvolt = <2800000>;\n+\t\t\tregulator-max-microvolt = <2800000>;\n \t\t};\n \t};\n \n--- a/arch/arm/boot/dts/overlays/ov7251-overlay.dts\n+++ b/arch/arm/boot/dts/overlays/ov7251-overlay.dts\n@@ -25,11 +25,9 @@\n \t\t\t\tclock-frequency = <24000000>;\n \n \t\t\t\tvdddo-supply = <&ov7251_dovdd>;\n-\t\t\t\tvdda-supply = <&ov7251_avdd>;\n+\t\t\t\tvdda-supply = <&cam1_reg>;\n \t\t\t\tvddd-supply = <&ov7251_dvdd>;\n \n-\t\t\t\tenable-gpios = <&gpio 41 GPIO_ACTIVE_HIGH>;\n-\n \t\t\t\tport {\n \t\t\t\t\tov7251_0: endpoint {\n \t\t\t\t\t\tremote-endpoint = <&csi1_ep>;\n@@ -68,12 +66,6 @@\n \tfragment@3 {\n \t\ttarget-path=\"/\";\n \t\t__overlay__ {\n-\t\t\tov7251_avdd: fixedregulator@0 {\n-\t\t\t\tcompatible = \"regulator-fixed\";\n-\t\t\t\tregulator-name = \"ov7251_avdd\";\n-\t\t\t\tregulator-min-microvolt = <2800000>;\n-\t\t\t\tregulator-max-microvolt = <2800000>;\n-\t\t\t};\n \t\t\tov7251_dovdd: fixedregulator@1 {\n \t\t\t\tcompatible = \"regulator-fixed\";\n \t\t\t\tregulator-name = \"ov7251_dovdd\";\n@@ -102,10 +94,12 @@\n \t};\n \n \tfragment@5 {\n-\t\ttarget-path=\"/__overrides__\";\n+\t\ttarget = <&cam1_reg>;\n \t\t__overlay__ {\n-\t\t\tcam0-pwdn-ctrl = <&ov7251>,\"enable-gpios:0\";\n-\t\t\tcam0-pwdn      = <&ov7251>,\"enable-gpios:4\";\n+\t\t\tstatus = \"okay\";\n+\t\t\tregulator-name = \"ov7251_avdd\";\n+\t\t\tregulator-min-microvolt = <2800000>;\n+\t\t\tregulator-max-microvolt = <2800000>;\n \t\t};\n \t};\n };\n--- a/arch/arm/boot/dts/overlays/ov9281-overlay.dts\n+++ b/arch/arm/boot/dts/overlays/ov9281-overlay.dts\n@@ -23,7 +23,7 @@\n \t\t\t\tclocks = <&ov9281_clk>;\n \t\t\t\tclock-names = \"xvclk\";\n \n-\t\t\t\tavdd-supply = <&ov9281_avdd>;\n+\t\t\t\tavdd-supply = <&cam1_reg>;\n \t\t\t\tdovdd-supply = <&ov9281_dovdd>;\n \t\t\t\tdvdd-supply = <&ov9281_dvdd>;\n \n@@ -66,14 +66,6 @@\n \tfragment@3 {\n \t\ttarget-path=\"/\";\n \t\t__overlay__ {\n-\t\t\tov9281_avdd: fixedregulator@0 {\n-\t\t\t\tcompatible = \"regulator-fixed\";\n-\t\t\t\tregulator-name = \"ov9281_avdd\";\n-\t\t\t\tregulator-min-microvolt = <2800000>;\n-\t\t\t\tregulator-max-microvolt = <2800000>;\n-\t\t\t\tgpio = <&gpio 41 GPIO_ACTIVE_HIGH>;\n-\t\t\t\tenable-active-high;\n-\t\t\t};\n \t\t\tov9281_dovdd: fixedregulator@1 {\n \t\t\t\tcompatible = \"regulator-fixed\";\n \t\t\t\tregulator-name = \"ov9281_dovdd\";\n@@ -102,10 +94,13 @@\n \t};\n \n \tfragment@5 {\n-\t\ttarget-path=\"/__overrides__\";\n+\t\ttarget = <&cam1_reg>;\n \t\t__overlay__ {\n-\t\t\tcam0-pwdn-ctrl = <&ov9281_avdd>,\"gpio:0\";\n-\t\t\tcam0-pwdn      = <&ov9281_avdd>,\"gpio:4\";\n+\t\t\tstatus = \"okay\";\n+\t\t\tregulator-name = \"ov9281_avdd\";\n+\t\t\tregulator-min-microvolt = <2800000>;\n+\t\t\tregulator-max-microvolt = <2800000>;\n \t\t};\n \t};\n+\n };\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0440-overlays-seeed-can-fd-hat-clarify-how-to-identify-HA.patch",
    "content": "From d26e1eb0a7c538c457138245f5c5ad0c8312dc9f Mon Sep 17 00:00:00 2001\nFrom: Marc Kleine-Budde <mkl@pengutronix.de>\nDate: Sat, 9 Jan 2021 17:03:32 +0100\nSubject: [PATCH] overlays: seeed-can-fd-hat: clarify how to identify\n HAT version\n\nIt turns out the used CAN SPI chip is not a good way to identify the version of\nthe CAN HAT.\n\nThere are two different board layouts of the Seeed Studio CAN BUS FD HAT. The\nv1 board doesn't have a battery holder, while the v2 board has. Update the\noverlay README accordinly.\n\nLink: https://github.com/Seeed-Studio/seeed-linux-dtoverlays/issues/13\nCc: Patrick Menschel <menschel.p@posteo.de>\nSigned-off-by: Marc Kleine-Budde <mkl@pengutronix.de>\n---\n arch/arm/boot/dts/overlays/README | 10 ++++++----\n 1 file changed, 6 insertions(+), 4 deletions(-)\n\n--- a/arch/arm/boot/dts/overlays/README\n+++ b/arch/arm/boot/dts/overlays/README\n@@ -2505,16 +2505,18 @@ Load:   <Deprecated>\n \n \n Name:   seeed-can-fd-hat-v1\n-Info:   Overlay for Seeed Studio CAN BUS FD HAT with two CAN FD channels\n-        (based on the mcp2517fd).\n+Info:   Overlay for Seeed Studio CAN BUS FD HAT with two CAN FD\n+        channels without RTC. Use this overlay if your HAT has no\n+        battery holder.\n         https://www.seeedstudio.com/2-Channel-CAN-BUS-FD-Shield-for-Raspberry-Pi-p-4072.html\n Load:   dtoverlay=seeed-can-fd-hat-v1\n Params: <None>\n \n \n Name:   seeed-can-fd-hat-v2\n-Info:   Overlay for Seeed Studio CAN BUS FD HAT with two CAN FD channels\n-        (based on the mcp2518fd) and an RTC.\n+Info:   Overlay for Seeed Studio CAN BUS FD HAT with two CAN FD\n+        channels and an RTC. Use this overlay if your HAT has a\n+        battery holder.\n         https://www.seeedstudio.com/CAN-BUS-FD-HAT-for-Raspberry-Pi-p-4742.html\n Load:   dtoverlay=seeed-can-fd-hat-v2\n Params: <None>\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0441-SQUASH-Revert-overlays-Make-the-i2c-gpio-overlay-saf.patch",
    "content": "From d30018da40f9a6ce037a2acf2ea46d0ad3a08e6a Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.com>\nDate: Wed, 13 Jan 2021 21:25:38 +0000\nSubject: [PATCH] SQUASH: Revert: \"overlays: Make the i2c-gpio overlay\n safe again\"\n\nThis revert and its neighbour are opposites. When squashing, delete\nthe original commits as well.\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.com>\n---\n arch/arm/boot/dts/overlays/i2c-gpio-overlay.dts | 3 +++\n 1 file changed, 3 insertions(+)\n\n--- a/arch/arm/boot/dts/overlays/i2c-gpio-overlay.dts\n+++ b/arch/arm/boot/dts/overlays/i2c-gpio-overlay.dts\n@@ -11,6 +11,9 @@\n \t\ttarget-path = \"/\";\n \n \t\t__overlay__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n \t\t\ti2c_gpio: i2c@0 {\n \t\t\t\treg = <0xffffffff>;\n \t\t\t\tcompatible = \"i2c-gpio\";\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0442-SQUASH-Revert-overlays-Fix-dtc-warnings-in-i2c-gpio.patch",
    "content": "From 283e74412227e4d3baab7a2dc48d90d0dd044bbf Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.com>\nDate: Wed, 13 Jan 2021 21:27:56 +0000\nSubject: [PATCH] SQUASH: Revert \"overlays: Fix dtc warnings in\n i2c-gpio\"\n\nThis reverts commit 1c15edc0dca002c8536e9f1f5e1ec43017815018.\n\nThis revert and its neighbour are opposites. When squashing, delete\nthe original commits as well.\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.com>\n---\n arch/arm/boot/dts/overlays/i2c-gpio-overlay.dts | 3 ---\n 1 file changed, 3 deletions(-)\n\n--- a/arch/arm/boot/dts/overlays/i2c-gpio-overlay.dts\n+++ b/arch/arm/boot/dts/overlays/i2c-gpio-overlay.dts\n@@ -11,9 +11,6 @@\n \t\ttarget-path = \"/\";\n \n \t\t__overlay__ {\n-\t\t\t#address-cells = <1>;\n-\t\t\t#size-cells = <0>;\n-\n \t\t\ti2c_gpio: i2c@0 {\n \t\t\t\treg = <0xffffffff>;\n \t\t\t\tcompatible = \"i2c-gpio\";\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0443-uapi-bcm2835-isp-Add-colour-denoise-configuration.patch",
    "content": "From aed98a04e57de36ad35d4fd09c5ce0c9cdd580dc Mon Sep 17 00:00:00 2001\nFrom: Naushir Patuck <naush@raspberrypi.com>\nDate: Thu, 14 Jan 2021 09:18:42 +0000\nSubject: [PATCH] uapi: bcm2835-isp: Add colour denoise configuration\n\nAdd a configuration structure for colour denoise to the bcm2835_isp\ndriver.\n\nSigned-off-by: Naushir Patuck <naush@raspberrypi.com>\n---\n include/uapi/linux/bcm2835-isp.h | 27 +++++++++++++++++++++++++++\n 1 file changed, 27 insertions(+)\n\n--- a/include/uapi/linux/bcm2835-isp.h\n+++ b/include/uapi/linux/bcm2835-isp.h\n@@ -31,6 +31,8 @@\n \t\t\t\t(V4L2_CID_USER_BCM2835_ISP_BASE + 0x0007)\n #define V4L2_CID_USER_BCM2835_ISP_DPC\t\t\\\n \t\t\t\t(V4L2_CID_USER_BCM2835_ISP_BASE + 0x0008)\n+#define V4L2_CID_USER_BCM2835_ISP_CDN \\\n+\t\t\t\t(V4L2_CID_USER_BCM2835_ISP_BASE + 0x0009)\n \n /*\n  * All structs below are directly mapped onto the equivalent structs in\n@@ -176,6 +178,31 @@ struct bcm2835_isp_gamma {\n };\n \n /**\n+ * enum bcm2835_isp_cdn_mode - Mode of operation for colour denoise.\n+ *\n+ * @CDN_MODE_FAST:\t\tFast (but lower quality) colour denoise\n+ *\t\t\t\talgorithm, typically used for video recording.\n+ * @CDN_HIGH_QUALITY:\t\tHigh quality (but slower) colour denoise\n+ *\t\t\t\talgorithm, typically used for stills capture.\n+ */\n+enum bcm2835_isp_cdn_mode {\n+\tCDN_MODE_FAST = 0,\n+\tCDN_MODE_HIGH_QUALITY = 1,\n+};\n+\n+/**\n+ * struct bcm2835_isp_cdn - Colour denoise parameters set with the\n+ *\t\t\t    V4L2_CID_USER_BCM2835_ISP_CDN ctrl.\n+ *\n+ * @enabled:\tEnable colour denoise.\n+ * @mode:\tColour denoise operating mode (see enum &bcm2835_isp_cdn_mode)\n+ */\n+struct bcm2835_isp_cdn {\n+\t__u32 enabled;\n+\t__u32 mode;\n+};\n+\n+/**\n  * struct bcm2835_isp_denoise - Denoise parameters set with the\n  *\t\t\t\tV4L2_CID_USER_BCM2835_ISP_DENOISE ctrl.\n  *\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0444-staging-vc04_services-ISP-Add-colour-denoise-control.patch",
    "content": "From 42a7effa20225e5a3b70d5d10c13146b5bab6af2 Mon Sep 17 00:00:00 2001\nFrom: Naushir Patuck <naush@raspberrypi.com>\nDate: Thu, 14 Jan 2021 09:20:52 +0000\nSubject: [PATCH] staging: vc04_services: ISP: Add colour denoise\n control\n\nAdd colour denoise control to the bcm2835 driver through a new v4l2\ncontrol: V4L2_CID_USER_BCM2835_ISP_CDN.\n\nAdd the accompanying MMAL configuration structure definitions as well.\n\nSigned-off-by: Naushir Patuck <naush@raspberrypi.com>\n---\n .../vc04_services/bcm2835-isp/bcm2835-isp-ctrls.h   |  5 +++++\n .../vc04_services/bcm2835-isp/bcm2835-v4l2-isp.c    |  5 +++++\n .../vc04_services/vchiq-mmal/mmal-parameters.h      | 13 +++++++++++++\n 3 files changed, 23 insertions(+)\n\n--- a/drivers/staging/vc04_services/bcm2835-isp/bcm2835-isp-ctrls.h\n+++ b/drivers/staging/vc04_services/bcm2835-isp/bcm2835-isp-ctrls.h\n@@ -57,6 +57,11 @@ static const struct bcm2835_isp_custom_c\n \t\t.size\t= sizeof(struct bcm2835_isp_denoise),\n \t\t.flags  = 0\n \t}, {\n+\t\t.name\t= \"Colour Denoise\",\n+\t\t.id\t= V4L2_CID_USER_BCM2835_ISP_CDN,\n+\t\t.size\t= sizeof(struct bcm2835_isp_cdn),\n+\t\t.flags  = 0\n+\t}, {\n \t\t.name\t= \"Defective Pixel Correction\",\n \t\t.id\t= V4L2_CID_USER_BCM2835_ISP_DPC,\n \t\t.size\t= sizeof(struct bcm2835_isp_dpc),\n--- a/drivers/staging/vc04_services/bcm2835-isp/bcm2835-v4l2-isp.c\n+++ b/drivers/staging/vc04_services/bcm2835-isp/bcm2835-v4l2-isp.c\n@@ -764,6 +764,11 @@ static int bcm2835_isp_s_ctrl(struct v4l\n \t\t\t\t    ctrl->p_new.p_u8,\n \t\t\t\t    sizeof(struct bcm2835_isp_denoise));\n \t\tbreak;\n+\tcase V4L2_CID_USER_BCM2835_ISP_CDN:\n+\t\tret = set_isp_param(node, MMAL_PARAMETER_CDN,\n+\t\t\t\t    ctrl->p_new.p_u8,\n+\t\t\t\t    sizeof(struct bcm2835_isp_cdn));\n+\t\tbreak;\n \tcase V4L2_CID_USER_BCM2835_ISP_SHARPEN:\n \t\tret = set_isp_param(node, MMAL_PARAMETER_SHARPEN,\n \t\t\t\t    ctrl->p_new.p_u8,\n--- a/drivers/staging/vc04_services/vchiq-mmal/mmal-parameters.h\n+++ b/drivers/staging/vc04_services/vchiq-mmal/mmal-parameters.h\n@@ -277,6 +277,8 @@ enum mmal_parameter_camera_type {\n \tMMAL_PARAMETER_DPC,\n \t\t/**< Tales a @ref MMAP_PARAMETER_GAMMA_T */\n \tMMAL_PARAMETER_GAMMA,\n+\t\t/**< Takes a @ref MMAL_PARAMETER_CDN_T */\n+\tMMAL_PARAMETER_CDN,\n };\n \n struct mmal_parameter_rational {\n@@ -913,6 +915,17 @@ struct mmal_parameter_gamma {\n \tu16 y[MMAL_NUM_GAMMA_PTS];\n };\n \n+enum mmal_parameter_cdn_mode {\n+\tMMAL_PARAM_CDN_FAST = 0,\n+\tMMAL_PARAM_CDN_HIGH_QUALITY = 1,\n+\tMMAL_PARAM_CDN_DUMMY  = 0x7FFFFFFF\n+};\n+\n+struct mmal_parameter_colour_denoise {\n+\tu32 enabled;\n+\tenum mmal_parameter_cdn_mode mode;\n+};\n+\n struct mmal_parameter_denoise {\n \tu32 enabled;\n \tu32 constant;\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0445-dt-bindings-nvmem-Add-bindings-for-rmem-driver.patch",
    "content": "From 15cfca011ac1e08e073628b36f40d64f03fcf2b2 Mon Sep 17 00:00:00 2001\nFrom: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>\nDate: Thu, 10 Dec 2020 19:22:45 +0100\nSubject: [PATCH] dt-bindings: nvmem: Add bindings for rmem driver\n\nFirmware/co-processors might use reserved memory areas in order to pass\ndata stemming from an nvmem device otherwise non accessible to Linux.\nFor example an EEPROM memory only physically accessible to firmware, or\ndata only accessible early at boot time.\n\nIntroduce the dt-bindings to nvmem's rmem.\n\nSigned-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>\n\n---\n\nChanges since v1:\n - Update schema to new driver design\n---\n .../devicetree/bindings/nvmem/rmem.yaml       | 49 +++++++++++++++++++\n 1 file changed, 49 insertions(+)\n create mode 100644 Documentation/devicetree/bindings/nvmem/rmem.yaml\n\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/nvmem/rmem.yaml\n@@ -0,0 +1,49 @@\n+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)\n+%YAML 1.2\n+---\n+$id: http://devicetree.org/schemas/nvmem/rmem.yaml#\n+$schema: http://devicetree.org/meta-schemas/core.yaml#\n+\n+title: Reserved Memory Based nvmem Device\n+\n+maintainers:\n+  - Nicolas Saenz Julienne <nsaenzjulienne@suse.de>\n+\n+allOf:\n+  - $ref: \"nvmem.yaml#\"\n+\n+properties:\n+  compatible:\n+    items:\n+      - enum:\n+        - raspberrypi,bootloader-config\n+      - const: nvmem-rmem\n+\n+  no-map:\n+    $ref: /schemas/types.yaml#/definitions/flag\n+    description:\n+      Avoid creating a virtual mapping of the region as part of the OS'\n+      standard mapping of system memory.\n+\n+required:\n+  - compatible\n+  - no-map\n+\n+unevaluatedProperties: false\n+\n+examples:\n+  - |\n+        reserved-memory {\n+                #address-cells = <1>;\n+                #size-cells = <1>;\n+\n+                blconfig: nvram@10000000 {\n+                        compatible = \"raspberrypi,bootloader-config\", \"nvmem-rmem\";\n+                        #address-cells = <1>;\n+                        #size-cells = <1>;\n+                        reg = <0x10000000 0x1000>;\n+                        no-map;\n+                };\n+        };\n+\n+...\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0446-nvmem-Add-driver-to-expose-reserved-memory-as-nvmem.patch",
    "content": "From 639949895123bb937b374ccacae0675ff4ab6e55 Mon Sep 17 00:00:00 2001\nFrom: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>\nDate: Thu, 10 Dec 2020 12:13:49 +0100\nSubject: [PATCH] nvmem: Add driver to expose reserved memory as nvmem\n\nFirmware/co-processors might use reserved memory areas in order to pass\ndata stemming from an nvmem device otherwise non accessible to Linux.\nFor example an EEPROM memory only physically accessible to firmware, or\ndata only accessible early at boot time.\n\nIn order to expose this data to other drivers and user-space, the driver\nmodels the reserved memory area as an nvmem device.\n\nSigned-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>\n\n---\n\nChanges since v1:\n - Remove reserved memory phandle indirection by directly creating a\n   platform device from the reserved memory DT node\n - Only map memory upon reading it to avoid corruption\n - Small cosmetic cleanups\n---\n drivers/nvmem/Kconfig  |  8 ++++\n drivers/nvmem/Makefile |  2 +\n drivers/nvmem/rmem.c   | 97 ++++++++++++++++++++++++++++++++++++++++++\n drivers/of/platform.c  |  1 +\n 4 files changed, 108 insertions(+)\n create mode 100644 drivers/nvmem/rmem.c\n\n--- a/drivers/nvmem/Kconfig\n+++ b/drivers/nvmem/Kconfig\n@@ -270,4 +270,12 @@ config SPRD_EFUSE\n \t  This driver can also be built as a module. If so, the module\n \t  will be called nvmem-sprd-efuse.\n \n+config NVMEM_RMEM\n+\ttristate \"Reserved Memory Based Driver Support\"\n+\thelp\n+\t  This drivers maps reserved memory into an nvmem device. It might be\n+\t  useful to expose information left by firmware in memory.\n+\n+\t  This driver can also be built as a module. If so, the module\n+\t  will be called nvmem-rmem.\n endif\n--- a/drivers/nvmem/Makefile\n+++ b/drivers/nvmem/Makefile\n@@ -55,3 +55,5 @@ obj-$(CONFIG_NVMEM_ZYNQMP)\t+= nvmem_zynq\n nvmem_zynqmp_nvmem-y\t\t:= zynqmp_nvmem.o\n obj-$(CONFIG_SPRD_EFUSE)\t+= nvmem_sprd_efuse.o\n nvmem_sprd_efuse-y\t\t:= sprd-efuse.o\n+obj-$(CONFIG_NVMEM_RMEM) \t+= nvmem-rmem.o\n+nvmem-rmem-y\t\t\t:= rmem.o\n--- /dev/null\n+++ b/drivers/nvmem/rmem.c\n@@ -0,0 +1,97 @@\n+// SPDX-License-Identifier: GPL-2.0+\n+/*\n+ * Copyright (C) 2020 Nicolas Saenz Julienne <nsaenzjulienne@suse.de>\n+ */\n+\n+#include <linux/io.h>\n+#include <linux/module.h>\n+#include <linux/nvmem-provider.h>\n+#include <linux/of_reserved_mem.h>\n+#include <linux/platform_device.h>\n+\n+struct rmem {\n+\tstruct device *dev;\n+\tstruct nvmem_device *nvmem;\n+\tstruct reserved_mem *mem;\n+\n+\tphys_addr_t size;\n+};\n+\n+static int rmem_read(void *context, unsigned int offset,\n+\t\t     void *val, size_t bytes)\n+{\n+\tstruct rmem *priv = context;\n+\tsize_t available = priv->mem->size;\n+\tloff_t off = offset;\n+\tvoid *addr;\n+\tint count;\n+\n+\t/*\n+\t * Only map the reserved memory at this point to avoid potential rogue\n+\t * kernel threads inadvertently modifying it. Based on the current\n+\t * uses-cases for this driver, the performance hit isn't a concern.\n+\t * Nor is likely to be, given the nature of the subsystem. Most nvmem\n+\t * devices operate over slow buses to begin with.\n+\t *\n+\t * An alternative would be setting the memory as RO, set_memory_ro(),\n+\t * but as of Dec 2020 this isn't possible on arm64.\n+\t */\n+\taddr = memremap(priv->mem->base, available, MEMREMAP_WB);\n+\tif (IS_ERR(addr)) {\n+\t\tdev_err(priv->dev, \"Failed to remap memory region\\n\");\n+\t\treturn PTR_ERR(addr);\n+\t}\n+\n+\tcount = memory_read_from_buffer(val, bytes, &off, addr, available);\n+\n+\tmemunmap(addr);\n+\n+\treturn count;\n+}\n+\n+static int rmem_probe(struct platform_device *pdev)\n+{\n+\tstruct nvmem_config config = { };\n+\tstruct device *dev = &pdev->dev;\n+\tstruct reserved_mem *mem;\n+\tstruct rmem *priv;\n+\n+\tpriv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);\n+\tif (!priv)\n+\t\treturn -ENOMEM;\n+\tpriv->dev = dev;\n+\n+\tmem = of_reserved_mem_lookup(dev->of_node);\n+\tif (!mem) {\n+\t\tdev_err(dev, \"Failed to lookup reserved memory\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\tpriv->mem = mem;\n+\n+\tconfig.dev = dev;\n+\tconfig.priv = priv;\n+\tconfig.name = \"rmem\";\n+\tconfig.size = mem->size;\n+\tconfig.reg_read = rmem_read;\n+\n+\treturn PTR_ERR_OR_ZERO(devm_nvmem_register(dev, &config));\n+}\n+\n+static const struct of_device_id rmem_match[] = {\n+\t{ .compatible = \"nvmem-rmem\", },\n+\t{ /* sentinel */ },\n+};\n+MODULE_DEVICE_TABLE(of, rmem_match);\n+\n+static struct platform_driver rmem_driver = {\n+\t.probe = rmem_probe,\n+\t.driver = {\n+\t\t.name = \"rmem\",\n+\t\t.of_match_table = rmem_match,\n+\t},\n+};\n+module_platform_driver(rmem_driver);\n+\n+MODULE_AUTHOR(\"Nicolas Saenz Julienne <nsaenzjulienne@suse.de>\");\n+MODULE_DESCRIPTION(\"Reserved Memory Based nvmem Driver\");\n+MODULE_LICENSE(\"GPL\");\n--- a/drivers/of/platform.c\n+++ b/drivers/of/platform.c\n@@ -511,6 +511,7 @@ static const struct of_device_id reserve\n \t{ .compatible = \"qcom,rmtfs-mem\" },\n \t{ .compatible = \"qcom,cmd-db\" },\n \t{ .compatible = \"ramoops\" },\n+\t{ .compatible = \"nvmem-rmem\" },\n \t{}\n };\n \n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0447-ARM-dts-bcm2711-Add-reserved-memory-template-to-hold.patch",
    "content": "From b3a070cf6fe04129d2c174e45c14b98a759e0402 Mon Sep 17 00:00:00 2001\nFrom: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>\nDate: Fri, 11 Dec 2020 12:22:01 +0100\nSubject: [PATCH] ARM: dts: bcm2711: Add reserved memory template to\n hold firmware configuration\n\nRPi4's co-processor will copy the board's bootloader[1] configuration\ninto memory for the OS to consume. Specifically, for the bootloader\nconfiguration and upgrade user-space routines to query it through\nnvmem's sysfs interface.\n\nIntroduce a reserved-memory area template for the co-processor to edit\nbefore booting the system so as for Linux not to overwrite that memory\nand to expose it as an nvmem device.\n\nSigned-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>\n\n[1] https://www.raspberrypi.org/documentation/hardware/raspberrypi/bcm2711_bootloader_config.md\n---\n\nChanges since v1:\n - Introduce compatible string\n - Change alias name to something more explicit\n---\n arch/arm/boot/dts/bcm2711-rpi-4-b.dts | 17 +++++++++++++++++\n 1 file changed, 17 insertions(+)\n\n--- a/arch/arm/boot/dts/bcm2711-rpi-4-b.dts\n+++ b/arch/arm/boot/dts/bcm2711-rpi-4-b.dts\n@@ -24,6 +24,7 @@\n \t\temmc2bus = &emmc2bus;\n \t\tethernet0 = &genet;\n \t\tpcie0 = &pcie0;\n+\t\tblconfig = &blconfig;\n \t};\n \n \tleds {\n@@ -215,6 +216,22 @@\n \tstatus = \"okay\";\n };\n \n+&rmem {\n+\t/*\n+\t * RPi4's co-processor will copy the board's bootloader configuration\n+\t * into memory for the OS to consume. It'll also update this node with\n+\t * its placement information.\n+\t */\n+\tblconfig: nvram@0 {\n+\t\tcompatible = \"raspberrypi,bootloader-config\", \"nvmem-rmem\";\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <1>;\n+\t\treg = <0x0 0x0 0x0>;\n+\t\tno-map;\n+\t\tstatus = \"disabled\";\n+\t};\n+};\n+\n /* SDHCI is used to control the SDIO for wireless */\n &sdhci {\n \t#address-cells = <1>;\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0448-spi-bcm2835-Workaround-fix-for-zero-length-transfers.patch",
    "content": "From 54545710d40fd00e3c727603a446500b1b9b3d88 Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.com>\nDate: Thu, 28 Jan 2021 11:30:04 +0000\nSubject: [PATCH] spi: bcm2835: Workaround/fix for zero-length\n transfers\n\nA relatively recent commit ([1]) contained optimisation for the PIO\nSPI FIFO-filling functions. The commit message includes the phrase\n\"[t]he blind and counted loops are always called with nonzero count\".\nThis is technically true, but it is still possible for count to become\nzero before the loop is entered - if tfr->len is zero. Moving the loop\nexit condition to the end of the loop saves a few cycles, but results\nin a near-infinite loop should the revised count be zero on entry.\n\nStrangely, zero-lengthed transfers aren't filtered by the SPI framework\nand, even more strangely, the Python3 spidev library is triggering them\nfor no obvious reason.\n\nAvoid the problem completely by bailing out of the main transfer\nfunction early if trf->len is zero, although there may be a case for\nmoving the mitigation into the framework.\n\nSee: https://github.com/raspberrypi/linux/issues/4100\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.com>\n\n[1] 26751de25d25 (\"spi: bcm2835: Micro-optimise FIFO loops\")\n---\n drivers/spi/spi-bcm2835.c | 10 ++++++++++\n 1 file changed, 10 insertions(+)\n\n--- a/drivers/spi/spi-bcm2835.c\n+++ b/drivers/spi/spi-bcm2835.c\n@@ -1092,6 +1092,16 @@ static int bcm2835_spi_transfer_one(stru\n \tunsigned long hz_per_byte, byte_limit;\n \tu32 cs = bs->prepare_cs[spi->chip_select];\n \n+\tif (unlikely(!tfr->len)) {\n+\t\tstatic int warned;\n+\n+\t\tif (!warned)\n+\t\t\tdev_warn(&spi->dev,\n+\t\t\t\t \"zero-length SPI transfer ignored\\n\");\n+\t\twarned = 1;\n+\t\treturn 0;\n+\t}\n+\n \t/* set clock */\n \tspi_hz = tfr->speed_hz;\n \n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0449-kbuild-Silence-unavoidable-dtc-overlay-warnings.patch",
    "content": "From 452e2d1248f7782e769cdbdd01a0f479715d7bfb Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.com>\nDate: Fri, 29 Jan 2021 10:34:11 +0000\nSubject: [PATCH] kbuild: Silence unavoidable dtc overlay warnings\n\nMuch effort has been put into finding ways to avoid warnings from dtc\nabout overlays, usually to do with the presence of #address-cells and\nsize-cells, but not exclusively so. Since the issues being warned about\nare harmless, suppress the warnings to declutter the build output and\nto avoid alarming users.\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.com>\n---\n scripts/Makefile.lib | 6 ++++++\n 1 file changed, 6 insertions(+)\n\n--- a/scripts/Makefile.lib\n+++ b/scripts/Makefile.lib\n@@ -348,6 +348,12 @@ cmd_dtco = mkdir -p $(dir ${dtc-tmp}) ;\n \t$(DTC) -@ -H epapr -O dtb -o $@ -b 0 \\\n \t\t-i $(dir $<) $(DTC_FLAGS) \\\n \t\t-Wno-interrupts_property \\\n+\t\t-Wno-label_is_string \\\n+\t\t-Wno-reg_format \\\n+\t\t-Wno-pci_device_bus_num \\\n+\t\t-Wno-i2c_bus_reg \\\n+\t\t-Wno-spi_bus_reg \\\n+\t\t-Wno-avoid_default_addr_size \\\n \t\t-d $(depfile).dtc.tmp $(dtc-tmp) ; \\\n \tcat $(depfile).pre.tmp $(depfile).dtc.tmp > $(depfile)\n \n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0450-Adds-the-DT-overlays-to-support-Hifiberry-AMP100.patch",
    "content": "From bcaa1b9dcc731ff3d7a8d36769062e9571d0738c Mon Sep 17 00:00:00 2001\nFrom: Joerg Schambacher <joerg@i2audio.com>\nDate: Fri, 29 Jan 2021 08:26:44 +0100\nSubject: [PATCH] Adds the DT-overlays to support Hifiberry AMP100\n\nAdds new DT-overlay to control AMP100.\n\nSigned-off-by: Joerg Schambacher <joerg@hifiberry.com>\n---\n arch/arm/boot/dts/overlays/Makefile           |  1 +\n arch/arm/boot/dts/overlays/README             | 30 ++++++++-\n .../dts/overlays/hifiberry-amp100-overlay.dts | 64 +++++++++++++++++++\n 3 files changed, 94 insertions(+), 1 deletion(-)\n create mode 100644 arch/arm/boot/dts/overlays/hifiberry-amp100-overlay.dts\n\n--- a/arch/arm/boot/dts/overlays/Makefile\n+++ b/arch/arm/boot/dts/overlays/Makefile\n@@ -61,6 +61,7 @@ dtbo-$(CONFIG_ARCH_BCM2835) += \\\n \thd44780-lcd.dtbo \\\n \thdmi-backlight-hwhack-gpio.dtbo \\\n \thifiberry-amp.dtbo \\\n+\thifiberry-amp100.dtbo \\\n \thifiberry-dac.dtbo \\\n \thifiberry-dacplus.dtbo \\\n \thifiberry-dacplusadc.dtbo \\\n--- a/arch/arm/boot/dts/overlays/README\n+++ b/arch/arm/boot/dts/overlays/README\n@@ -1059,8 +1059,36 @@ Load:   dtoverlay=hifiberry-amp\n Params: <None>\n \n \n+Name:   hifiberry-amp100\n+Info:   Configures the HifiBerry AMP100 audio card\n+Load:   dtoverlay=hifiberry-amp100,<param>=<val>\n+Params: 24db_digital_gain       Allow gain to be applied via the PCM512x codec\n+                                Digital volume control. Enable with\n+                                \"dtoverlay=hifiberry-amp100,24db_digital_gain\"\n+                                (The default behaviour is that the Digital\n+                                volume control is limited to a maximum of\n+                                0dB. ie. it can attenuate but not provide\n+                                gain. For most users, this will be desired\n+                                as it will prevent clipping. By appending\n+                                the 24dB_digital_gain parameter, the Digital\n+                                volume control will allow up to 24dB of\n+                                gain. If this parameter is enabled, it is the\n+                                responsibility of the user to ensure that\n+                                the Digital volume control is set to a value\n+                                that does not result in clipping/distortion!)\n+        slave                   Force DAC+ Pro into slave mode, using Pi as\n+                                master for bit clock and frame clock.\n+        leds_off                If set to 'true' the onboard indicator LEDs\n+                                are switched off at all times.\n+        auto_mute               If set to 'true' the amplifier is automatically\n+                                muted when the DAC is not playing.\n+        mute_ext_ctl            The amplifier's HW mute control is enabled\n+                                in ALSA mixer and set to <val>.\n+                                Will be overwritten by ALSA user settings.\n+\n+\n Name:   hifiberry-dac\n-Info:   Configures the HifiBerry DAC audio card\n+Info:   Configures the HifiBerry DAC audio cards\n Load:   dtoverlay=hifiberry-dac\n Params: <None>\n \n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/hifiberry-amp100-overlay.dts\n@@ -0,0 +1,64 @@\n+// Definitions for HiFiBerry AMP100\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget-path = \"/\";\n+\t\t__overlay__ {\n+\t\t\tdacpro_osc: dacpro_osc {\n+\t\t\t\tcompatible = \"hifiberry,dacpro-clk\";\n+\t\t\t\t#clock-cells = <0>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&i2s>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&i2c1>;\n+\t\t__overlay__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tpcm5122@4d {\n+\t\t\t\t#sound-dai-cells = <0>;\n+\t\t\t\tcompatible = \"ti,pcm5122\";\n+\t\t\t\treg = <0x4d>;\n+\t\t\t\tclocks = <&dacpro_osc>;\n+\t\t\t\tAVDD-supply = <&vdd_3v3_reg>;\n+\t\t\t\tDVDD-supply = <&vdd_3v3_reg>;\n+\t\t\t\tCPVDD-supply = <&vdd_3v3_reg>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@3 {\n+\t\ttarget = <&sound>;\n+\t\thifiberry_dacplus: __overlay__ {\n+\t\t\tcompatible = \"hifiberry,hifiberry-dacplus\";\n+\t\t\ti2s-controller = <&i2s>;\n+\t\t\tstatus = \"okay\";\n+\t\t\tmute-gpio = <&gpio 4 0>;\n+\t\t\treset-gpio = <&gpio 17 0x11>;\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\t24db_digital_gain =\n+\t\t\t<&hifiberry_dacplus>,\"hifiberry,24db_digital_gain?\";\n+\t\tslave = <&hifiberry_dacplus>,\"hifiberry-dacplus,slave?\";\n+\t\tleds_off = <&hifiberry_dacplus>,\"hifiberry-dacplus,leds_off?\";\n+\t\tmute_ext_ctl = <&hifiberry_dacplus>,\"hifiberry-dacplus,mute_ext_ctl:0\";\n+\t\tauto_mute = <&hifiberry_dacplus>,\"hifiberry-dacplus,auto_mute?\";\n+\t};\n+};\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0451-Enhances-the-Hifiberry-DAC-driver-for-Hifiberry-AMP1.patch",
    "content": "From 1aebaa90d468875109f0bf37cd89c7cfd9ac69bf Mon Sep 17 00:00:00 2001\nFrom: Joerg Schambacher <joerg@i2audio.com>\nDate: Fri, 29 Jan 2021 16:16:39 +0100\nSubject: [PATCH] Enhances the Hifiberry DAC+ driver for Hifiberry\n AMP100 support\n\nAdds the necessary GPIO handling and ALSA mixer extensions.\nAlso fixes a problem with the PLL/CLK control when switching sample rates.\nThanks to Clive Messer for the support!\n\nSigned-off-by: Joerg Schambacher <joerg@hifiberry.com>\n---\n sound/soc/bcm/hifiberry_dacplus.c | 124 ++++++++++++++++++++++++++----\n 1 file changed, 111 insertions(+), 13 deletions(-)\n\n--- a/sound/soc/bcm/hifiberry_dacplus.c\n+++ b/sound/soc/bcm/hifiberry_dacplus.c\n@@ -1,10 +1,10 @@\n /*\n- * ASoC Driver for HiFiBerry DAC+ / DAC Pro\n+ * ASoC Driver for HiFiBerry DAC+ / DAC Pro / AMP100\n  *\n  * Author:\tDaniel Matuschek, Stuart MacLean <stuart@hifiberry.com>\n  *\t\tCopyright 2014-2015\n  *\t\tbased on code by Florian Meier <florian.meier@koalo.de>\n- *\t\tHeadphone added by Joerg Schambacher, joerg@i2audio.com\n+ *\t\tHeadphone/AMP100 Joerg Schambacher <joerg@hifiberry.com>\n  *\n  * This program is free software; you can redistribute it and/or\n  * modify it under the terms of the GNU General Public License\n@@ -17,6 +17,8 @@\n  */\n \n #include <linux/module.h>\n+#include <linux/gpio/consumer.h>\n+#include <../drivers/gpio/gpiolib.h>\n #include <linux/platform_device.h>\n #include <linux/kernel.h>\n #include <linux/clk.h>\n@@ -53,6 +55,47 @@ static bool slave;\n static bool snd_rpi_hifiberry_is_dacpro;\n static bool digital_gain_0db_limit = true;\n static bool leds_off;\n+static bool auto_mute;\n+static int mute_ext_ctl;\n+static int mute_ext;\n+static struct gpio_desc *snd_mute_gpio;\n+static struct gpio_desc *snd_reset_gpio;\n+static struct snd_soc_card snd_rpi_hifiberry_dacplus;\n+\n+static int snd_rpi_hifiberry_dacplus_mute_set(int mute)\n+{\n+\tgpiod_set_value_cansleep(snd_mute_gpio, mute);\n+\treturn 1;\n+}\n+\n+static int snd_rpi_hifiberry_dacplus_mute_get(struct snd_kcontrol *kcontrol,\n+\t\t\t\tstruct snd_ctl_elem_value *ucontrol)\n+{\n+\tucontrol->value.integer.value[0] = mute_ext;\n+\n+\treturn 0;\n+}\n+\n+static int snd_rpi_hifiberry_dacplus_mute_put(struct snd_kcontrol *kcontrol,\n+\t\t\t\tstruct snd_ctl_elem_value *ucontrol)\n+{\n+\tif (mute_ext == ucontrol->value.integer.value[0])\n+\t\treturn 0;\n+\n+\tmute_ext = ucontrol->value.integer.value[0];\n+\n+\treturn snd_rpi_hifiberry_dacplus_mute_set(mute_ext);\n+}\n+\n+static const char * const mute_text[] = {\"Play\", \"Mute\"};\n+static const struct soc_enum hb_dacplus_opt_mute_enum =\n+\tSOC_ENUM_SINGLE_EXT(2, mute_text);\n+\n+static const struct snd_kcontrol_new hb_dacplus_opt_mute_controls[] = {\n+\tSOC_ENUM_EXT(\"Mute(ext)\", hb_dacplus_opt_mute_enum,\n+\t\t\t      snd_rpi_hifiberry_dacplus_mute_get,\n+\t\t\t      snd_rpi_hifiberry_dacplus_mute_put),\n+};\n \n static void snd_rpi_hifiberry_dacplus_select_clk(struct snd_soc_component *component,\n \tint clk_id)\n@@ -68,6 +111,7 @@ static void snd_rpi_hifiberry_dacplus_se\n \t\tsnd_soc_component_update_bits(component, PCM512x_GPIO_CONTROL_1, 0x24, 0x04);\n \t\tbreak;\n \t}\n+\tusleep_range(2000, 2100);\n }\n \n static void snd_rpi_hifiberry_dacplus_clk_gpio(struct snd_soc_component *component)\n@@ -85,13 +129,6 @@ static bool snd_rpi_hifiberry_dacplus_is\n \treturn (!(sck & 0x40));\n }\n \n-static bool snd_rpi_hifiberry_dacplus_is_sclk_sleep(\n-\tstruct snd_soc_component *component)\n-{\n-\tmsleep(2);\n-\treturn snd_rpi_hifiberry_dacplus_is_sclk(component);\n-}\n-\n static bool snd_rpi_hifiberry_dacplus_is_pro_card(struct snd_soc_component *component)\n {\n \tbool isClk44EN, isClk48En, isNoClk;\n@@ -99,13 +136,13 @@ static bool snd_rpi_hifiberry_dacplus_is\n \tsnd_rpi_hifiberry_dacplus_clk_gpio(component);\n \n \tsnd_rpi_hifiberry_dacplus_select_clk(component, HIFIBERRY_DACPRO_CLK44EN);\n-\tisClk44EN = snd_rpi_hifiberry_dacplus_is_sclk_sleep(component);\n+\tisClk44EN = snd_rpi_hifiberry_dacplus_is_sclk(component);\n \n \tsnd_rpi_hifiberry_dacplus_select_clk(component, HIFIBERRY_DACPRO_NOCLOCK);\n-\tisNoClk = snd_rpi_hifiberry_dacplus_is_sclk_sleep(component);\n+\tisNoClk = snd_rpi_hifiberry_dacplus_is_sclk(component);\n \n \tsnd_rpi_hifiberry_dacplus_select_clk(component, HIFIBERRY_DACPRO_CLK48EN);\n-\tisClk48En = snd_rpi_hifiberry_dacplus_is_sclk_sleep(component);\n+\tisClk48En = snd_rpi_hifiberry_dacplus_is_sclk(component);\n \n \treturn (isClk44EN && isClk48En && !isNoClk);\n }\n@@ -149,6 +186,7 @@ static int snd_rpi_hifiberry_dacplus_ini\n {\n \tstruct snd_soc_component *component = asoc_rtd_to_codec(rtd, 0)->component;\n \tstruct pcm512x_priv *priv;\n+\tstruct snd_soc_card *card = &snd_rpi_hifiberry_dacplus;\n \n \tif (slave)\n \t\tsnd_rpi_hifiberry_is_dacpro = false;\n@@ -187,6 +225,20 @@ static int snd_rpi_hifiberry_dacplus_ini\n \t\tif (ret < 0)\n \t\t\tdev_warn(card->dev, \"Failed to set volume limit: %d\\n\", ret);\n \t}\n+\tif (snd_reset_gpio) {\n+\t\tgpiod_set_value_cansleep(snd_reset_gpio, 0);\n+\t\tmsleep(1);\n+\t\tgpiod_set_value_cansleep(snd_reset_gpio, 1);\n+\t\tmsleep(1);\n+\t\tgpiod_set_value_cansleep(snd_reset_gpio, 0);\n+\t}\n+\n+\tif (mute_ext_ctl)\n+\t\tsnd_soc_add_card_controls(card,\thb_dacplus_opt_mute_controls,\n+\t\t\t\tARRAY_SIZE(hb_dacplus_opt_mute_controls));\n+\n+\tif (snd_mute_gpio)\n+\t\tgpiod_set_value_cansleep(snd_mute_gpio,\tmute_ext);\n \n \treturn 0;\n }\n@@ -254,6 +306,8 @@ static int snd_rpi_hifiberry_dacplus_sta\n \tstruct snd_soc_pcm_runtime *rtd = substream->private_data;\n \tstruct snd_soc_component *component = asoc_rtd_to_codec(rtd, 0)->component;\n \n+\tif (auto_mute)\n+\t\tgpiod_set_value_cansleep(snd_mute_gpio, 0);\n \tif (leds_off)\n \t\treturn 0;\n \tsnd_soc_component_update_bits(component, PCM512x_GPIO_CONTROL_1, 0x08, 0x08);\n@@ -267,6 +321,8 @@ static void snd_rpi_hifiberry_dacplus_sh\n \tstruct snd_soc_component *component = asoc_rtd_to_codec(rtd, 0)->component;\n \n \tsnd_soc_component_update_bits(component, PCM512x_GPIO_CONTROL_1, 0x08, 0x00);\n+\tif (auto_mute)\n+\t\tgpiod_set_value_cansleep(snd_mute_gpio, 1);\n }\n \n /* machine stream operations */\n@@ -342,6 +398,8 @@ static int snd_rpi_hifiberry_dacplus_pro\n \tstruct device_node *tpa_node;\n \tstruct property *tpa_prop;\n \tstruct of_changeset ocs;\n+\tstruct property *pp;\n+\tint tmp;\n \n \t/* probe for head phone amp */\n \tret = hb_hp_detect();\n@@ -396,6 +454,39 @@ static int snd_rpi_hifiberry_dacplus_pro\n \t\t\t\t\t\t\"hifiberry-dacplus,slave\");\n \t\tleds_off = of_property_read_bool(pdev->dev.of_node,\n \t\t\t\t\t\t\"hifiberry-dacplus,leds_off\");\n+\t\tauto_mute = of_property_read_bool(pdev->dev.of_node,\n+\t\t\t\t\t\t\"hifiberry-dacplus,auto_mute\");\n+\n+\t\t/*\n+\t\t * check for HW MUTE as defined in DT-overlay\n+\t\t * active high, therefore default to HIGH to MUTE\n+\t\t */\n+\t\tsnd_mute_gpio =\tdevm_gpiod_get_optional(&pdev->dev,\n+\t\t\t\t\t\t \"mute\", GPIOD_OUT_HIGH);\n+\t\tif (IS_ERR(snd_mute_gpio)) {\n+\t\t\tdev_err(&pdev->dev, \"Can't allocate GPIO (HW-MUTE)\");\n+\t\t\treturn PTR_ERR(snd_mute_gpio);\n+\t\t}\n+\n+\t\t/* add ALSA control if requested in DT-overlay (AMP100) */\n+\t\tpp = of_find_property(pdev->dev.of_node,\n+\t\t\t\t\"hifiberry-dacplus,mute_ext_ctl\", &tmp);\n+\t\tif (pp) {\n+\t\t\tif (!of_property_read_u32(pdev->dev.of_node,\n+\t\t\t\t\"hifiberry-dacplus,mute_ext_ctl\", &mute_ext)) {\n+\t\t\t\t/* ALSA control will be used */\n+\t\t\t\tmute_ext_ctl = 1;\n+\t\t\t}\n+\t\t}\n+\n+\t\t/* check for HW RESET (AMP100) */\n+\t\tsnd_reset_gpio = devm_gpiod_get_optional(&pdev->dev,\n+\t\t\t\t\t\t\"reset\", GPIOD_OUT_HIGH);\n+\t\tif (IS_ERR(snd_reset_gpio)) {\n+\t\t\tdev_err(&pdev->dev, \"Can't allocate GPIO (HW-RESET)\");\n+\t\t\treturn PTR_ERR(snd_reset_gpio);\n+\t\t}\n+\n \t}\n \n \tret = devm_snd_soc_register_card(&pdev->dev,\n@@ -403,7 +494,14 @@ static int snd_rpi_hifiberry_dacplus_pro\n \tif (ret && ret != -EPROBE_DEFER)\n \t\tdev_err(&pdev->dev,\n \t\t\t\"snd_soc_register_card() failed: %d\\n\", ret);\n-\n+\tif (!ret) {\n+\t\tif (snd_mute_gpio)\n+\t\t\tdev_info(&pdev->dev, \"GPIO%i for HW-MUTE selected\",\n+\t\t\t\t\tgpio_chip_hwgpio(snd_mute_gpio));\n+\t\tif (snd_reset_gpio)\n+\t\t\tdev_info(&pdev->dev, \"GPIO%i for HW-RESET selected\",\n+\t\t\t\t\tgpio_chip_hwgpio(snd_reset_gpio));\n+\t}\n \treturn ret;\n }\n \n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0452-ARM-dts-Declare-Pi400-and-CM4-have-no-audio-pins.patch",
    "content": "From a3028b49ed28dfcd27fb12dd811ef5572fc80c30 Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.com>\nDate: Wed, 3 Feb 2021 16:23:43 +0000\nSubject: [PATCH] ARM: dts: Declare Pi400 and CM4 have no audio pins\n\nThe audio_pins node is left as a placeholder for the audremap overlay,\nand it must have (empty) brcm,function and brcm,pins properties\notherwise it will be rejected by the pinctrl driver.\n\nSee: https://www.raspberrypi.org/forums/viewtopic.php?f=98&t=301891\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.com>\n---\n arch/arm/boot/dts/bcm2711-rpi-400.dts | 4 ++--\n arch/arm/boot/dts/bcm2711-rpi-cm4.dts | 2 ++\n 2 files changed, 4 insertions(+), 2 deletions(-)\n\n--- a/arch/arm/boot/dts/bcm2711-rpi-400.dts\n+++ b/arch/arm/boot/dts/bcm2711-rpi-400.dts\n@@ -565,8 +565,8 @@\n \n &gpio {\n \taudio_pins: audio_pins {\n-\t\tbrcm,pins = <40 41>;\n-\t\tbrcm,function = <4>;\n+\t\tbrcm,pins = <>;\n+\t\tbrcm,function = <>;\n \t};\n };\n \n--- a/arch/arm/boot/dts/bcm2711-rpi-cm4.dts\n+++ b/arch/arm/boot/dts/bcm2711-rpi-cm4.dts\n@@ -556,6 +556,8 @@\n \n &gpio {\n \taudio_pins: audio_pins {\n+\t\tbrcm,pins = <>;\n+\t\tbrcm,function = <>;\n \t};\n };\n \n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0453-media-i2c-imx290-Replace-V4L2_CID_GAIN-with-V4L2_CID.patch",
    "content": "From 4a7aa2079f074dc7c2767bfa98eafb1a387f5129 Mon Sep 17 00:00:00 2001\nFrom: David Plowman <david.plowman@raspberrypi.com>\nDate: Thu, 4 Feb 2021 17:29:32 +0000\nSubject: [PATCH] media: i2c: imx290: Replace V4L2_CID_GAIN with\n V4L2_CID_ANALOGUE_GAIN\n\nMost software (including libcamera) requires V4L2_CID_ANALOGUE_GAIN,\nnot V4L2_CID_GAIN.\n\nThe range for the control is 0 to 100 for which the sensor uses only\nanalogue gain; higher values would involve digital gain which this\ncontrol should not apply.\n\nSigned-off-by: David Plowman <david.plowman@raspberrypi.com>\n---\n drivers/media/i2c/imx290.c | 4 ++--\n 1 file changed, 2 insertions(+), 2 deletions(-)\n\n--- a/drivers/media/i2c/imx290.c\n+++ b/drivers/media/i2c/imx290.c\n@@ -647,7 +647,7 @@ static int imx290_set_ctrl(struct v4l2_c\n \t\treturn 0;\n \n \tswitch (ctrl->id) {\n-\tcase V4L2_CID_GAIN:\n+\tcase V4L2_CID_ANALOGUE_GAIN:\n \t\tret = imx290_set_gain(imx290, ctrl->val);\n \t\tbreak;\n \tcase V4L2_CID_EXPOSURE:\n@@ -1331,7 +1331,7 @@ static int imx290_probe(struct i2c_clien\n \tv4l2_ctrl_handler_init(&imx290->ctrls, 4);\n \n \tv4l2_ctrl_new_std(&imx290->ctrls, &imx290_ctrl_ops,\n-\t\t\t  V4L2_CID_GAIN, 0, 238, 1, 0);\n+\t\t\t  V4L2_CID_ANALOGUE_GAIN, 0, 100, 1, 0);\n \n \tmode = imx290->current_mode;\n \timx290->hblank = v4l2_ctrl_new_std(&imx290->ctrls, &imx290_ctrl_ops,\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0454-media-i2c-imx290-Fix-number-of-controls-in-v4l2_ctrl.patch",
    "content": "From ff6a86ca7b8ca22cf270300ac192c7101a43bb44 Mon Sep 17 00:00:00 2001\nFrom: David Plowman <david.plowman@raspberrypi.com>\nDate: Thu, 4 Feb 2021 21:21:44 +0000\nSubject: [PATCH] media: i2c: imx290: Fix number of controls in\n v4l2_ctrl_handler_init\n\nThe number is only a hint, but may as well be correct.\n\nFixes: 471e0029e98aa (\"media: i2c: imx290: Convert HMAX setting into V4L2_CID_HBLANK\")\nFixes: be0b9b7ad1c27 (\"media: i2c: imx290: Add support for V4L2_CID_VBLANK\")\nFixes: 8483f0d7599aa (\"media: i2c: imx290: Add exposure control to the driver.\")\nFixes: 9764f3459c401 (\"media: i2c: imx290: Add H and V flip controls\")\nSigned-off-by: David Plowman <david.plowman@raspberrypi.com>\n---\n drivers/media/i2c/imx290.c | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/drivers/media/i2c/imx290.c\n+++ b/drivers/media/i2c/imx290.c\n@@ -1328,7 +1328,7 @@ static int imx290_probe(struct i2c_clien\n \t */\n \timx290_entity_init_cfg(&imx290->sd, NULL);\n \n-\tv4l2_ctrl_handler_init(&imx290->ctrls, 4);\n+\tv4l2_ctrl_handler_init(&imx290->ctrls, 9);\n \n \tv4l2_ctrl_new_std(&imx290->ctrls, &imx290_ctrl_ops,\n \t\t\t  V4L2_CID_ANALOGUE_GAIN, 0, 100, 1, 0);\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0455-ARM-bcm-Select-BRCMSTB_L2_IRQ-for-bcm2835.patch",
    "content": "From c6d5aeba7fd60727436c04bfa4cae8b29d48e0de Mon Sep 17 00:00:00 2001\nFrom: Maxime Ripard <maxime@cerno.tech>\nDate: Mon, 11 Jan 2021 15:22:55 +0100\nSubject: [PATCH] ARM: bcm: Select BRCMSTB_L2_IRQ for bcm2835\n\nThe BCM2711 has a number of instances of interrupt controllers handled\nby the driver behind the BRCMSTB_L2_IRQ Kconfig option (irq-brcmstb-l2).\n\nLet's select that driver as part of the ARCH_BCM2835 Kconfig option.\n\nSigned-off-by: Maxime Ripard <maxime@cerno.tech>\nAcked-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n arch/arm/mach-bcm/Kconfig    | 1 +\n arch/arm64/Kconfig.platforms | 1 +\n 2 files changed, 2 insertions(+)\n\n--- a/arch/arm/mach-bcm/Kconfig\n+++ b/arch/arm/mach-bcm/Kconfig\n@@ -161,6 +161,7 @@ config ARCH_BCM2835\n \tselect ARM_TIMER_SP804\n \tselect HAVE_ARM_ARCH_TIMER if ARCH_MULTI_V7\n \tselect BCM2835_TIMER\n+\tselect BRCMSTB_L2_IRQ\n \tselect FIQ\n \tselect PINCTRL\n \tselect PINCTRL_BCM2835\n--- a/arch/arm64/Kconfig.platforms\n+++ b/arch/arm64/Kconfig.platforms\n@@ -39,6 +39,7 @@ config ARCH_BCM2835\n \tselect ARM_AMBA\n \tselect ARM_GIC\n \tselect ARM_TIMER_SP804\n+\tselect BRCMSTB_L2_IRQ\n \thelp\n \t  This enables support for the Broadcom BCM2837 and BCM2711 SoC.\n \t  These SoCs are used in the Raspberry Pi 3 and 4 devices.\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0456-drm-vc4-hdmi-Update-the-CEC-clock-divider-on-HSM-rat.patch",
    "content": "From beadd8dfb16c626c2261fc6f8aab935cd7412603 Mon Sep 17 00:00:00 2001\nFrom: Maxime Ripard <maxime@cerno.tech>\nDate: Mon, 11 Jan 2021 15:23:01 +0100\nSubject: [PATCH] drm/vc4: hdmi: Update the CEC clock divider on HSM\n rate change\n\nAs part of the enable sequence we might change the HSM clock rate if the\npixel rate is different than the one we were already dealing with.\n\nOn the BCM2835 however, the CEC clock derives from the HSM clock so any\nrate change will need to be reflected in the CEC clock divider to output\n40kHz.\n\nFixes: cd4cb49dc5bb (\"drm/vc4: hdmi: Adjust HSM clock rate depending on pixel rate\")\nReviewed-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\nSigned-off-by: Maxime Ripard <maxime@cerno.tech>\n---\n drivers/gpu/drm/vc4/vc4_hdmi.c | 2 ++\n 1 file changed, 2 insertions(+)\n\n--- a/drivers/gpu/drm/vc4/vc4_hdmi.c\n+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c\n@@ -802,6 +802,8 @@ static void vc4_hdmi_encoder_pre_crtc_co\n \n \tvc4_hdmi_cec_update_clk_div(vc4_hdmi);\n \n+\tvc4_hdmi_cec_update_clk_div(vc4_hdmi);\n+\n \t/*\n \t * FIXME: When the pixel freq is 594MHz (4k60), this needs to be setup\n \t * at 300MHz.\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0457-drm-vc4-hdmi-Introduce-a-CEC-clock.patch",
    "content": "From b4627f9f36d8af7cb7bf24d8c1daee8b48f12299 Mon Sep 17 00:00:00 2001\nFrom: Maxime Ripard <maxime@cerno.tech>\nDate: Mon, 11 Jan 2021 15:23:02 +0100\nSubject: [PATCH] drm/vc4: hdmi: Introduce a CEC clock\n\nWhile the BCM2835 had the CEC clock derived from the HSM clock, the\nBCM2711 has a dedicated parent clock for it.\n\nLet's introduce a separate clock for it so that we can handle both\ncases.\n\nReviewed-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\nSigned-off-by: Maxime Ripard <maxime@cerno.tech>\n---\n drivers/gpu/drm/vc4/vc4_hdmi.c | 9 ++++++++-\n drivers/gpu/drm/vc4/vc4_hdmi.h | 1 +\n 2 files changed, 9 insertions(+), 1 deletion(-)\n\n--- a/drivers/gpu/drm/vc4/vc4_hdmi.c\n+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c\n@@ -151,7 +151,7 @@ static void vc4_hdmi_cec_update_clk_div(\n \t * Set the clock divider: the hsm_clock rate and this divider\n \t * setting will give a 40 kHz CEC clock.\n \t */\n-\tclk_cnt = clk_get_rate(vc4_hdmi->hsm_clock) / CEC_CLOCK_FREQ;\n+\tclk_cnt = clk_get_rate(vc4_hdmi->cec_clock) / CEC_CLOCK_FREQ;\n \tvalue |= clk_cnt << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT;\n \tHDMI_WRITE(HDMI_CEC_CNTRL_1, value);\n }\n@@ -1869,6 +1869,7 @@ static int vc4_hdmi_init_resources(struc\n \t\treturn PTR_ERR(vc4_hdmi->hsm_clock);\n \t}\n \tvc4_hdmi->audio_clock = vc4_hdmi->hsm_clock;\n+\tvc4_hdmi->cec_clock = vc4_hdmi->hsm_clock;\n \n \treturn 0;\n }\n@@ -1963,6 +1964,12 @@ static int vc5_hdmi_init_resources(struc\n \t\treturn PTR_ERR(vc4_hdmi->audio_clock);\n \t}\n \n+\tvc4_hdmi->cec_clock = devm_clk_get(dev, \"cec\");\n+\tif (IS_ERR(vc4_hdmi->cec_clock)) {\n+\t\tDRM_ERROR(\"Failed to get CEC clock\\n\");\n+\t\treturn PTR_ERR(vc4_hdmi->cec_clock);\n+\t}\n+\n \tvc4_hdmi->reset = devm_reset_control_get(dev, NULL);\n \tif (IS_ERR(vc4_hdmi->reset)) {\n \t\tDRM_ERROR(\"Failed to get HDMI reset line\\n\");\n--- a/drivers/gpu/drm/vc4/vc4_hdmi.h\n+++ b/drivers/gpu/drm/vc4/vc4_hdmi.h\n@@ -154,6 +154,7 @@ struct vc4_hdmi {\n \tbool cec_tx_ok;\n \tbool cec_irq_was_rx;\n \n+\tstruct clk *cec_clock;\n \tstruct clk *pixel_clock;\n \tstruct clk *hsm_clock;\n \tstruct clk *audio_clock;\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0458-drm-vc4-hdmi-Split-the-interrupt-handlers.patch",
    "content": "From 423173ed6e873ec9a6ae0e62d55bd4c746f0f982 Mon Sep 17 00:00:00 2001\nFrom: Maxime Ripard <maxime@cerno.tech>\nDate: Mon, 11 Jan 2021 15:23:03 +0100\nSubject: [PATCH] drm/vc4: hdmi: Split the interrupt handlers\n\nThe BCM2711 has two different interrupt sources to transmit and receive\nCEC messages, provided through an external interrupt chip shared between\nthe two HDMI interrupt controllers.\n\nThe rest of the CEC controller is identical though so we need to change\na bit the code organisation to share the code as much as possible, yet\nstill allowing to register independant handlers.\n\nSigned-off-by: Maxime Ripard <maxime@cerno.tech>\nReviewed-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n drivers/gpu/drm/vc4/vc4_hdmi.c | 86 +++++++++++++++++++++++++---------\n 1 file changed, 65 insertions(+), 21 deletions(-)\n\n--- a/drivers/gpu/drm/vc4/vc4_hdmi.c\n+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c\n@@ -1574,15 +1574,22 @@ static int vc4_hdmi_audio_init(struct vc\n }\n \n #ifdef CONFIG_DRM_VC4_HDMI_CEC\n-static irqreturn_t vc4_cec_irq_handler_thread(int irq, void *priv)\n+static irqreturn_t vc4_cec_irq_handler_rx_thread(int irq, void *priv)\n+{\n+\tstruct vc4_hdmi *vc4_hdmi = priv;\n+\n+\tif (vc4_hdmi->cec_rx_msg.len)\n+\t\tcec_received_msg(vc4_hdmi->cec_adap,\n+\t\t\t\t &vc4_hdmi->cec_rx_msg);\n+\n+\treturn IRQ_HANDLED;\n+}\n+\n+static irqreturn_t vc4_cec_irq_handler_tx_thread(int irq, void *priv)\n {\n \tstruct vc4_hdmi *vc4_hdmi = priv;\n \n-\tif (vc4_hdmi->cec_irq_was_rx) {\n-\t\tif (vc4_hdmi->cec_rx_msg.len)\n-\t\t\tcec_received_msg(vc4_hdmi->cec_adap,\n-\t\t\t\t\t &vc4_hdmi->cec_rx_msg);\n-\t} else if (vc4_hdmi->cec_tx_ok) {\n+\tif (vc4_hdmi->cec_tx_ok) {\n \t\tcec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_OK,\n \t\t\t\t  0, 0, 0, 0);\n \t} else {\n@@ -1596,6 +1603,19 @@ static irqreturn_t vc4_cec_irq_handler_t\n \treturn IRQ_HANDLED;\n }\n \n+static irqreturn_t vc4_cec_irq_handler_thread(int irq, void *priv)\n+{\n+\tstruct vc4_hdmi *vc4_hdmi = priv;\n+\tirqreturn_t ret;\n+\n+\tif (vc4_hdmi->cec_irq_was_rx)\n+\t\tret = vc4_cec_irq_handler_rx_thread(irq, priv);\n+\telse\n+\t\tret = vc4_cec_irq_handler_tx_thread(irq, priv);\n+\n+\treturn ret;\n+}\n+\n static void vc4_cec_read_msg(struct vc4_hdmi *vc4_hdmi, u32 cntrl1)\n {\n \tstruct drm_device *dev = vc4_hdmi->connector.dev;\n@@ -1620,31 +1640,55 @@ static void vc4_cec_read_msg(struct vc4_\n \t}\n }\n \n+static irqreturn_t vc4_cec_irq_handler_tx_bare(int irq, void *priv)\n+{\n+\tstruct vc4_hdmi *vc4_hdmi = priv;\n+\tu32 cntrl1;\n+\n+\tcntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1);\n+\tvc4_hdmi->cec_tx_ok = cntrl1 & VC4_HDMI_CEC_TX_STATUS_GOOD;\n+\tcntrl1 &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;\n+\tHDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);\n+\n+\treturn IRQ_WAKE_THREAD;\n+}\n+\n+static irqreturn_t vc4_cec_irq_handler_rx_bare(int irq, void *priv)\n+{\n+\tstruct vc4_hdmi *vc4_hdmi = priv;\n+\tu32 cntrl1;\n+\n+\tvc4_hdmi->cec_rx_msg.len = 0;\n+\tcntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1);\n+\tvc4_cec_read_msg(vc4_hdmi, cntrl1);\n+\tcntrl1 |= VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;\n+\tHDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);\n+\tcntrl1 &= ~VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;\n+\n+\tHDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);\n+\n+\treturn IRQ_WAKE_THREAD;\n+}\n+\n static irqreturn_t vc4_cec_irq_handler(int irq, void *priv)\n {\n \tstruct vc4_hdmi *vc4_hdmi = priv;\n \tu32 stat = HDMI_READ(HDMI_CEC_CPU_STATUS);\n-\tu32 cntrl1, cntrl5;\n+\tirqreturn_t ret;\n+\tu32 cntrl5;\n \n \tif (!(stat & VC4_HDMI_CPU_CEC))\n \t\treturn IRQ_NONE;\n-\tvc4_hdmi->cec_rx_msg.len = 0;\n-\tcntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1);\n+\n \tcntrl5 = HDMI_READ(HDMI_CEC_CNTRL_5);\n \tvc4_hdmi->cec_irq_was_rx = cntrl5 & VC4_HDMI_CEC_RX_CEC_INT;\n-\tif (vc4_hdmi->cec_irq_was_rx) {\n-\t\tvc4_cec_read_msg(vc4_hdmi, cntrl1);\n-\t\tcntrl1 |= VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;\n-\t\tHDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);\n-\t\tcntrl1 &= ~VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;\n-\t} else {\n-\t\tvc4_hdmi->cec_tx_ok = cntrl1 & VC4_HDMI_CEC_TX_STATUS_GOOD;\n-\t\tcntrl1 &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;\n-\t}\n-\tHDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);\n-\tHDMI_WRITE(HDMI_CEC_CPU_CLEAR, VC4_HDMI_CPU_CEC);\n+\tif (vc4_hdmi->cec_irq_was_rx)\n+\t\tret = vc4_cec_irq_handler_rx_bare(irq, priv);\n+\telse\n+\t\tret = vc4_cec_irq_handler_tx_bare(irq, priv);\n \n-\treturn IRQ_WAKE_THREAD;\n+\tHDMI_WRITE(HDMI_CEC_CPU_CLEAR, VC4_HDMI_CPU_CEC);\n+\treturn ret;\n }\n \n static int vc4_hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable)\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0459-drm-vc4-hdmi-Support-BCM2711-CEC-interrupt-setup.patch",
    "content": "From fe8bcda64e4d30cf91f2807973940873c1a577a2 Mon Sep 17 00:00:00 2001\nFrom: Maxime Ripard <maxime@cerno.tech>\nDate: Mon, 11 Jan 2021 15:23:04 +0100\nSubject: [PATCH] drm/vc4: hdmi: Support BCM2711 CEC interrupt setup\n\nThe HDMI controller found in the BCM2711 has an external interrupt\ncontroller for the CEC and hotplug interrupt shared between the two\ninstances.\n\nLet's add a variant flag to register a single interrupt handler and\ndeals with the interrupt handler setup, or two interrupt handlers\nrelying on an external irqchip.\n\nSigned-off-by: Maxime Ripard <maxime@cerno.tech>\nReviewed-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n drivers/gpu/drm/vc4/vc4_hdmi.c | 42 ++++++++++++++++++++++++++--------\n drivers/gpu/drm/vc4/vc4_hdmi.h |  7 ++++++\n 2 files changed, 39 insertions(+), 10 deletions(-)\n\n--- a/drivers/gpu/drm/vc4/vc4_hdmi.c\n+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c\n@@ -1725,9 +1725,11 @@ static int vc4_hdmi_cec_adap_enable(stru\n \t\t\t   ((3600 / usecs) << VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT) |\n \t\t\t   ((3500 / usecs) << VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT));\n \n-\t\tHDMI_WRITE(HDMI_CEC_CPU_MASK_CLEAR, VC4_HDMI_CPU_CEC);\n+\t\tif (!vc4_hdmi->variant->external_irq_controller)\n+\t\t\tHDMI_WRITE(HDMI_CEC_CPU_MASK_CLEAR, VC4_HDMI_CPU_CEC);\n \t} else {\n-\t\tHDMI_WRITE(HDMI_CEC_CPU_MASK_SET, VC4_HDMI_CPU_CEC);\n+\t\tif (!vc4_hdmi->variant->external_irq_controller)\n+\t\t\tHDMI_WRITE(HDMI_CEC_CPU_MASK_SET, VC4_HDMI_CPU_CEC);\n \t\tHDMI_WRITE(HDMI_CEC_CNTRL_5, val |\n \t\t\t   VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);\n \t}\n@@ -1799,8 +1801,6 @@ static int vc4_hdmi_cec_init(struct vc4_\n \tcec_fill_conn_info_from_drm(&conn_info, &vc4_hdmi->connector);\n \tcec_s_conn_info(vc4_hdmi->cec_adap, &conn_info);\n \n-\tHDMI_WRITE(HDMI_CEC_CPU_MASK_SET, 0xffffffff);\n-\n \tvalue = HDMI_READ(HDMI_CEC_CNTRL_1);\n \t/* Set the logical address to Unregistered */\n \tvalue |= VC4_HDMI_CEC_ADDR_MASK;\n@@ -1808,12 +1808,32 @@ static int vc4_hdmi_cec_init(struct vc4_\n \n \tvc4_hdmi_cec_update_clk_div(vc4_hdmi);\n \n-\tret = devm_request_threaded_irq(&pdev->dev, platform_get_irq(pdev, 0),\n-\t\t\t\t\tvc4_cec_irq_handler,\n-\t\t\t\t\tvc4_cec_irq_handler_thread, 0,\n-\t\t\t\t\t\"vc4 hdmi cec\", vc4_hdmi);\n-\tif (ret)\n-\t\tgoto err_delete_cec_adap;\n+\tif (vc4_hdmi->variant->external_irq_controller) {\n+\t\tret = devm_request_threaded_irq(&pdev->dev,\n+\t\t\t\t\t\tplatform_get_irq_byname(pdev, \"cec-rx\"),\n+\t\t\t\t\t\tvc4_cec_irq_handler_rx_bare,\n+\t\t\t\t\t\tvc4_cec_irq_handler_rx_thread, 0,\n+\t\t\t\t\t\t\"vc4 hdmi cec rx\", vc4_hdmi);\n+\t\tif (ret)\n+\t\t\tgoto err_delete_cec_adap;\n+\n+\t\tret = devm_request_threaded_irq(&pdev->dev,\n+\t\t\t\t\t\tplatform_get_irq_byname(pdev, \"cec-tx\"),\n+\t\t\t\t\t\tvc4_cec_irq_handler_tx_bare,\n+\t\t\t\t\t\tvc4_cec_irq_handler_tx_thread, 0,\n+\t\t\t\t\t\t\"vc4 hdmi cec tx\", vc4_hdmi);\n+\t\tif (ret)\n+\t\t\tgoto err_delete_cec_adap;\n+\t} else {\n+\t\tHDMI_WRITE(HDMI_CEC_CPU_MASK_SET, 0xffffffff);\n+\n+\t\tret = devm_request_threaded_irq(&pdev->dev, platform_get_irq(pdev, 0),\n+\t\t\t\t\t\tvc4_cec_irq_handler,\n+\t\t\t\t\t\tvc4_cec_irq_handler_thread, 0,\n+\t\t\t\t\t\t\"vc4 hdmi cec\", vc4_hdmi);\n+\t\tif (ret)\n+\t\t\tgoto err_delete_cec_adap;\n+\t}\n \n \tret = cec_register_adapter(vc4_hdmi->cec_adap, &pdev->dev);\n \tif (ret < 0)\n@@ -2288,6 +2308,7 @@ static const struct vc4_hdmi_variant bcm\n \t\tPHY_LANE_CK,\n \t},\n \t.unsupported_odd_h_timings\t= true,\n+\t.external_irq_controller\t= true,\n \n \t.init_resources\t\t= vc5_hdmi_init_resources,\n \t.csc_setup\t\t= vc5_hdmi_csc_setup,\n@@ -2314,6 +2335,7 @@ static const struct vc4_hdmi_variant bcm\n \t\tPHY_LANE_2,\n \t},\n \t.unsupported_odd_h_timings\t= true,\n+\t.external_irq_controller\t= true,\n \n \t.init_resources\t\t= vc5_hdmi_init_resources,\n \t.csc_setup\t\t= vc5_hdmi_csc_setup,\n--- a/drivers/gpu/drm/vc4/vc4_hdmi.h\n+++ b/drivers/gpu/drm/vc4/vc4_hdmi.h\n@@ -61,6 +61,13 @@ struct vc4_hdmi_variant {\n \t/* The BCM2711 cannot deal with odd horizontal pixel timings */\n \tbool unsupported_odd_h_timings;\n \n+\t/*\n+\t * The BCM2711 CEC/hotplug IRQ controller is shared between the\n+\t * two HDMI controllers, and we have a proper irqchip driver for\n+\t * it.\n+\t */\n+\tbool external_irq_controller;\n+\n \t/* Callback to get the resources (memory region, interrupts,\n \t * clocks, etc) for that variant.\n \t */\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0460-drm-vc4-hdmi-Don-t-register-the-CEC-adapter-if-there.patch",
    "content": "From 8fb908fe3f80d6bbc0a7f5e7fe14ababe7f87f83 Mon Sep 17 00:00:00 2001\nFrom: Maxime Ripard <maxime@cerno.tech>\nDate: Mon, 11 Jan 2021 15:23:06 +0100\nSubject: [PATCH] drm/vc4: hdmi: Don't register the CEC adapter if\n there's no interrupts\n\nWe introduced the BCM2711 support to the vc4 HDMI controller with 5.10,\nbut this was lacking any of the interrupts of the CEC controller so we\nhave to deal with the backward compatibility.\n\nDo so by simply ignoring the CEC setup if the DT doesn't have the\ninterrupts property.\n\nReviewed-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\nSigned-off-by: Maxime Ripard <maxime@cerno.tech>\n---\n drivers/gpu/drm/vc4/vc4_hdmi.c | 6 ++++++\n 1 file changed, 6 insertions(+)\n\n--- a/drivers/gpu/drm/vc4/vc4_hdmi.c\n+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c\n@@ -1787,9 +1787,15 @@ static int vc4_hdmi_cec_init(struct vc4_\n {\n \tstruct cec_connector_info conn_info;\n \tstruct platform_device *pdev = vc4_hdmi->pdev;\n+\tstruct device *dev = &pdev->dev;\n \tu32 value;\n \tint ret;\n \n+\tif (!of_find_property(dev->of_node, \"interrupts\", NULL)) {\n+\t\tdev_warn(dev, \"'interrupts' DT property is missing, no CEC\\n\");\n+\t\treturn 0;\n+\t}\n+\n \tvc4_hdmi->cec_adap = cec_allocate_adapter(&vc4_hdmi_cec_adap_ops,\n \t\t\t\t\t\t  vc4_hdmi, \"vc4\",\n \t\t\t\t\t\t  CEC_CAP_DEFAULTS |\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0461-dt-binding-display-bcm2711-hdmi-Add-CEC-and-hotplug-.patch",
    "content": "From d08cc5b251941721372910b4f7d0fdafced25d45 Mon Sep 17 00:00:00 2001\nFrom: Maxime Ripard <maxime@cerno.tech>\nDate: Mon, 11 Jan 2021 15:23:07 +0100\nSubject: [PATCH] dt-binding: display: bcm2711-hdmi: Add CEC and\n hotplug interrupts\n\nThe CEC and hotplug interrupts were missing when that binding was\nintroduced, let's add them in now that we've figured out how it works.\n\nSigned-off-by: Maxime Ripard <maxime@cerno.tech>\nAcked-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n .../bindings/display/brcm,bcm2711-hdmi.yaml   | 20 ++++++++++++++++++-\n 1 file changed, 19 insertions(+), 1 deletion(-)\n\n--- a/Documentation/devicetree/bindings/display/brcm,bcm2711-hdmi.yaml\n+++ b/Documentation/devicetree/bindings/display/brcm,bcm2711-hdmi.yaml\n@@ -53,6 +53,24 @@ properties:\n       - const: audio\n       - const: cec\n \n+  interrupts:\n+    items:\n+      - description: CEC TX interrupt\n+      - description: CEC RX interrupt\n+      - description: CEC stuck at low interrupt\n+      - description: Wake-up interrupt\n+      - description: Hotplug connected interrupt\n+      - description: Hotplug removed interrupt\n+\n+  interrupt-names:\n+    items:\n+      - const: cec-tx\n+      - const: cec-rx\n+      - const: cec-low\n+      - const: wakeup\n+      - const: hpd-connected\n+      - const: hpd-removed\n+\n   ddc:\n     allOf:\n       - $ref: /schemas/types.yaml#/definitions/phandle\n@@ -90,7 +108,7 @@ required:\n   - resets\n   - ddc\n \n-additionalProperties: false\n+unevaluatedProperties: false\n \n examples:\n   - |\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0462-ARM-dts-bcm2711-Add-the-CEC-interrupt-controller.patch",
    "content": "From 37e369738ad24d0e43a5db645dcf3a7c434d0db9 Mon Sep 17 00:00:00 2001\nFrom: Maxime Ripard <maxime@cerno.tech>\nDate: Mon, 11 Jan 2021 15:23:09 +0100\nSubject: [PATCH] ARM: dts: bcm2711: Add the CEC interrupt controller\n\nThe CEC and hotplug interrupts go through an interrupt controller shared\nbetween the two HDMI controllers.\n\nLet's add that interrupt controller and the interrupts for both HDMI\ncontrollers\n\nReviewed-by: Florian Fainelli <f.fainelli@gmail.com>\nSigned-off-by: Maxime Ripard <maxime@cerno.tech>\n---\n arch/arm/boot/dts/bcm2711.dtsi | 18 ++++++++++++++++++\n 1 file changed, 18 insertions(+)\n\n--- a/arch/arm/boot/dts/bcm2711.dtsi\n+++ b/arch/arm/boot/dts/bcm2711.dtsi\n@@ -309,6 +309,14 @@\n \t\t\t#reset-cells = <1>;\n \t\t};\n \n+\t\taon_intr: interrupt-controller@7ef00100 {\n+\t\t\tcompatible = \"brcm,bcm2711-l2-intc\", \"brcm,l2-intc\";\n+\t\t\treg = <0x7ef00100 0x30>;\n+\t\t\tinterrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tinterrupt-controller;\n+\t\t\t#interrupt-cells = <1>;\n+\t\t};\n+\n \t\thdmi0: hdmi@7ef00700 {\n \t\t\tcompatible = \"brcm,bcm2711-hdmi0\";\n \t\t\treg = <0x7ef00700 0x300>,\n@@ -337,6 +345,11 @@\n \t\t\t\t <&clk_27MHz>;\n \t\t\tclock-names = \"hdmi\", \"bvb\", \"audio\", \"cec\";\n \t\t\tresets = <&dvp 0>;\n+\t\t\tinterrupt-parent = <&aon_intr>;\n+\t\t\tinterrupts = <0>, <1>, <2>,\n+\t\t\t\t     <3>, <4>, <5>;\n+\t\t\tinterrupt-names = \"cec-tx\", \"cec-rx\", \"cec-low\",\n+\t\t\t\t\t  \"wakeup\", \"hpd-connected\", \"hpd-removed\";\n \t\t\tddc = <&ddc0>;\n \t\t\tdmas = <&dma 10>;\n \t\t\tdma-names = \"audio-rx\";\n@@ -381,6 +394,11 @@\n \t\t\t\t <&dvp 0>,\n \t\t\t\t <&clk_27MHz>;\n \t\t\tresets = <&dvp 1>;\n+\t\t\tinterrupt-parent = <&aon_intr>;\n+\t\t\tinterrupts = <8>, <7>, <6>,\n+\t\t\t\t     <9>, <10>, <11>;\n+\t\t\tinterrupt-names = \"cec-tx\", \"cec-rx\", \"cec-low\",\n+\t\t\t\t\t  \"wakeup\", \"hpd-connected\", \"hpd-removed\";\n \t\t\tdmas = <&dma 17>;\n \t\t\tdma-names = \"audio-rx\";\n \t\t\tinterrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0463-bcm2711-Disable-bsc_intr-and-aon_intr-by-default-and.patch",
    "content": "From 8c11d9b768c6753f045e8669a9d90bb008874b4b Mon Sep 17 00:00:00 2001\nFrom: Dom Cobley <popcornmix@gmail.com>\nDate: Wed, 9 Dec 2020 16:37:01 +0000\nSubject: [PATCH] bcm2711: Disable bsc_intr and aon_intr by default and\n enable in overlay\n\nSigned-off-by: Dom Cobley <popcornmix@gmail.com>\n---\n arch/arm/boot/dts/bcm2711.dtsi                     |  2 ++\n .../boot/dts/overlays/vc4-kms-v3d-pi4-overlay.dts  | 14 ++++++++++++++\n 2 files changed, 16 insertions(+)\n\n--- a/arch/arm/boot/dts/bcm2711.dtsi\n+++ b/arch/arm/boot/dts/bcm2711.dtsi\n@@ -315,6 +315,7 @@\n \t\t\tinterrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;\n \t\t\tinterrupt-controller;\n \t\t\t#interrupt-cells = <1>;\n+\t\t\tstatus = \"disabled\";\n \t\t};\n \n \t\thdmi0: hdmi@7ef00700 {\n--- a/arch/arm/boot/dts/overlays/vc4-kms-v3d-pi4-overlay.dts\n+++ b/arch/arm/boot/dts/overlays/vc4-kms-v3d-pi4-overlay.dts\n@@ -166,6 +166,13 @@\n \t\t};\n \t};\n \n+\tfragment@24 {\n+\t\ttarget = <&aon_intr>;\n+\t\t__overlay__  {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n \t__overrides__ {\n \t\taudio   = <0>,\"!17\";\n \t\taudio1   = <0>,\"!18\";\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0464-bcm2711-Remove-old-GIC-interrupt.patch",
    "content": "From b74589474b5db6154cca49278df7fdccf92b6ab9 Mon Sep 17 00:00:00 2001\nFrom: Dom Cobley <popcornmix@gmail.com>\nDate: Mon, 11 Jan 2021 17:08:20 +0000\nSubject: [PATCH] bcm2711: Remove old GIC interrupt\n\nNow handled through aon_intr\n\nSigned-off-by: Dom Cobley <popcornmix@gmail.com>\n---\n arch/arm/boot/dts/bcm2711.dtsi | 2 --\n 1 file changed, 2 deletions(-)\n\n--- a/arch/arm/boot/dts/bcm2711.dtsi\n+++ b/arch/arm/boot/dts/bcm2711.dtsi\n@@ -354,7 +354,6 @@\n \t\t\tddc = <&ddc0>;\n \t\t\tdmas = <&dma 10>;\n \t\t\tdma-names = \"audio-rx\";\n-\t\t\tinterrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;\n \t\t\tstatus = \"disabled\";\n \t\t};\n \n@@ -402,7 +401,6 @@\n \t\t\t\t\t  \"wakeup\", \"hpd-connected\", \"hpd-removed\";\n \t\t\tdmas = <&dma 17>;\n \t\t\tdma-names = \"audio-rx\";\n-\t\t\tinterrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;\n \t\t\tstatus = \"disabled\";\n \t\t};\n \n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0465-staging-bcm2835-camera-Fix-the-cherry-pick-of-AWB-Gr.patch",
    "content": "From da208ac4f51f643928847eabd81b7422fa6f6536 Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Mon, 8 Feb 2021 11:48:35 +0000\nSubject: [PATCH] staging:bcm2835-camera: Fix the cherry-pick of AWB\n Greyworld\n\nThe cherry-pick of the patch that added the greyworld AWB mode\nwas incomplete. Fix it up.\n\nFixes: b3ef481fe243 \"staging: bcm2835-camera: Add greyworld AWB mode\"\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n drivers/staging/vc04_services/bcm2835-camera/controls.c | 4 ++--\n 1 file changed, 2 insertions(+), 2 deletions(-)\n\n--- a/drivers/staging/vc04_services/bcm2835-camera/controls.c\n+++ b/drivers/staging/vc04_services/bcm2835-camera/controls.c\n@@ -1056,8 +1056,8 @@ static const struct bm2835_mmal_v4l2_ctr\n \t{\n \t\t.id = V4L2_CID_AUTO_N_PRESET_WHITE_BALANCE,\n \t\t.type = MMAL_CONTROL_TYPE_STD_MENU,\n-\t\t.min = ~0x3ff,\n-\t\t.max = V4L2_WHITE_BALANCE_SHADE,\n+\t\t.min = ~0x7ff,\n+\t\t.max = V4L2_WHITE_BALANCE_GREYWORLD,\n \t\t.def = V4L2_WHITE_BALANCE_AUTO,\n \t\t.step = 0,\n \t\t.imenu = NULL,\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0466-Overlays-for-PiFi-Mini-amp.patch",
    "content": "From 1040be57555a700e5949aa509299fea40649269e Mon Sep 17 00:00:00 2001\nFrom: David Knell <david.knell@gmail.com>\nDate: Mon, 8 Feb 2021 03:33:30 +0000\nSubject: [PATCH] Overlays for PiFi-Mini amp\n\nSigned-off-by: David Knell <david.knell@gmail.com>\n---\n arch/arm/boot/dts/overlays/Makefile           |  1 +\n arch/arm/boot/dts/overlays/README             |  6 +++\n .../dts/overlays/pifi-mini-210-overlay.dts    | 42 +++++++++++++++++++\n 3 files changed, 49 insertions(+)\n create mode 100644 arch/arm/boot/dts/overlays/pifi-mini-210-overlay.dts\n\n--- a/arch/arm/boot/dts/overlays/Makefile\n+++ b/arch/arm/boot/dts/overlays/Makefile\n@@ -130,6 +130,7 @@ dtbo-$(CONFIG_ARCH_BCM2835) += \\\n \tpibell.dtbo \\\n \tpifacedigital.dtbo \\\n \tpifi-40.dtbo \\\n+\tpifi-mini-210.dtbo \\\n \tpiglow.dtbo \\\n \tpiscreen.dtbo \\\n \tpiscreen2r.dtbo \\\n--- a/arch/arm/boot/dts/overlays/README\n+++ b/arch/arm/boot/dts/overlays/README\n@@ -2131,6 +2131,12 @@ Load:   dtoverlay=pifi-40\n Params: <None>\n \n \n+Name:   pifi-mini-210\n+Info:   Configures the PiFi Mini stereo amplifier\n+Load:   dtoverlay=pifi-mini-210\n+Params: <None>\n+\n+\n Name:   piglow\n Info:   Configures the PiGlow by pimoroni.com\n Load:   dtoverlay=piglow\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/pifi-mini-210-overlay.dts\n@@ -0,0 +1,42 @@\n+// Definitions for PiFi Mini 210\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&i2s>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&i2c1>;\n+\t\t__overlay__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\ttas5711@1a {\n+\t\t\t\t#sound-dai-cells = <0>;\n+\t\t\t\tcompatible = \"ti,tas5711\";\n+\t\t\t\treg = <0x1a>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t\tpdn-gpios = <&gpio 23 1>;\n+\t\t\t\treset-gpios = <&gpio 24 1>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&sound>;\n+\t\t__overlay__ {\n+\t\t\tcompatible = \"pifi,pifi-mini-210\";\n+\t\t\ti2s-controller = <&i2s>;\n+\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+};\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0467-Added-PiFi-Mini-to-rpi-simple-soundcard.c.patch",
    "content": "From 4951e0d22b58566678a16d53bf06851e1b63eeff Mon Sep 17 00:00:00 2001\nFrom: David Knell <david.knell@gmail.com>\nDate: Mon, 8 Feb 2021 03:35:15 +0000\nSubject: [PATCH] Added PiFi-Mini to rpi-simple-soundcard.c\n\nSigned-off-by: David Knell <david.knell@gmail.com>\n---\n sound/soc/bcm/rpi-simple-soundcard.c | 94 +++++++++++++++++++++++++---\n 1 file changed, 87 insertions(+), 7 deletions(-)\n\n--- a/sound/soc/bcm/rpi-simple-soundcard.c\n+++ b/sound/soc/bcm/rpi-simple-soundcard.c\n@@ -32,6 +32,7 @@\n \n #include <linux/module.h>\n #include <linux/platform_device.h>\n+#include <linux/gpio/consumer.h>\n \n #include <sound/core.h>\n #include <sound/pcm.h>\n@@ -45,6 +46,13 @@ struct snd_rpi_simple_drvdata {\n \tunsigned int fixed_bclk_ratio;\n };\n \n+static struct snd_soc_card snd_rpi_simple = {\n+\t.driver_name  = \"RPi-simple\",\n+\t.owner        = THIS_MODULE,\n+\t.dai_link     = NULL,\n+\t.num_links    = 1, /* Only a single DAI supported at the moment */\n+};\n+\n static int snd_rpi_simple_init(struct snd_soc_pcm_runtime *rtd)\n {\n \tstruct snd_rpi_simple_drvdata *drvdata =\n@@ -58,6 +66,60 @@ static int snd_rpi_simple_init(struct sn\n \treturn 0;\n }\n \n+static int pifi_mini_210_init(struct snd_soc_pcm_runtime *rtd)\n+{\n+\tstruct snd_soc_component *dac;\n+\tstruct gpio_desc *pdn_gpio, *rst_gpio;\n+\tstruct snd_soc_dai *codec_dai;\n+\tint ret;\n+\n+\tsnd_rpi_simple_init(rtd);\n+\tcodec_dai = asoc_rtd_to_codec(rtd, 0);\n+\n+\tdac = codec_dai[0].component;\n+\n+\tpdn_gpio = devm_gpiod_get_optional(snd_rpi_simple.dev, \"pdn\",\n+\t\t\t\t\t\tGPIOD_OUT_LOW);\n+\tif (IS_ERR(pdn_gpio)) {\n+\t\tret = PTR_ERR(pdn_gpio);\n+\t\tdev_err(snd_rpi_simple.dev, \"failed to get pdn gpio: %d\\n\", ret);\n+\t\treturn ret;\n+\t}\n+\n+\trst_gpio = devm_gpiod_get_optional(snd_rpi_simple.dev, \"rst\",\n+\t\t\t\t\t\tGPIOD_OUT_LOW);\n+\tif (IS_ERR(rst_gpio)) {\n+\t\tret = PTR_ERR(rst_gpio);\n+\t\tdev_err(snd_rpi_simple.dev, \"failed to get rst gpio: %d\\n\", ret);\n+\t\treturn ret;\n+\t}\n+\n+\t// Set up cards - pulse power down and reset first, then\n+\t// set up according to datasheet\n+\tgpiod_set_value_cansleep(pdn_gpio, 1);\n+\tgpiod_set_value_cansleep(rst_gpio, 1);\n+\tusleep_range(1000, 10000);\n+\tgpiod_set_value_cansleep(pdn_gpio, 0);\n+\tusleep_range(20000, 30000);\n+\tgpiod_set_value_cansleep(rst_gpio, 0);\n+\tusleep_range(20000, 30000);\n+\n+\t// Oscillator trim\n+\tsnd_soc_component_write(dac, 0x1b, 0);\n+\tusleep_range(60000, 80000);\n+\n+\t// MCLK at 64fs, sample rate 44.1 or 48kHz\n+\tsnd_soc_component_write(dac, 0x00, 0x60);\n+\n+\t// Set up for BTL - AD/BD mode - AD is 0x00107772, BD is 0x00987772\n+\tsnd_soc_component_write(dac, 0x20, 0x00107772);\n+\n+\t// End mute\n+\tsnd_soc_component_write(dac, 0x05, 0x00);\n+\n+\treturn 0;\n+}\n+\n static int snd_rpi_simple_hw_params(struct snd_pcm_substream *substream,\n \t\tstruct snd_pcm_hw_params *params)\n {\n@@ -255,6 +317,29 @@ static struct snd_rpi_simple_drvdata drv\n \t.fixed_bclk_ratio = 64,\n };\n \n+SND_SOC_DAILINK_DEFS(pifi_mini_210,\n+\tDAILINK_COMP_ARRAY(COMP_EMPTY()),\n+\tDAILINK_COMP_ARRAY(COMP_CODEC(\"tas571x.1-001a\", \"tas571x-hifi\")),\n+\tDAILINK_COMP_ARRAY(COMP_EMPTY()));\n+\n+static struct snd_soc_dai_link snd_pifi_mini_210_dai[] = {\n+\t{\n+\t\t.name           = \"PiFi Mini 210\",\n+\t\t.stream_name    = \"PiFi Mini 210 HiFi\",\n+\t\t.init\t\t\t= pifi_mini_210_init,\n+\t\t.dai_fmt        = SND_SOC_DAIFMT_I2S |\n+\t\t\t\t\tSND_SOC_DAIFMT_NB_NF |\n+\t\t\t\t\tSND_SOC_DAIFMT_CBS_CFS,\n+\t\tSND_SOC_DAILINK_REG(pifi_mini_210),\n+\t},\n+};\n+\n+static struct snd_rpi_simple_drvdata drvdata_pifi_mini_210 = {\n+\t.card_name        = \"snd_pifi_mini_210\",\n+\t.dai              = snd_pifi_mini_210_dai,\n+\t.fixed_bclk_ratio = 64,\n+};\n+\n static const struct of_device_id snd_rpi_simple_of_match[] = {\n \t{ .compatible = \"adi,adau1977-adc\",\n \t\t.data = (void *) &drvdata_adau1977 },\n@@ -269,16 +354,11 @@ static const struct of_device_id snd_rpi\n \t{ .compatible = \"rpi,rpi-dac\", &drvdata_rpi_dac},\n \t{ .compatible = \"merus,merus-amp\",\n \t\t.data = (void *) &drvdata_merus_amp },\n+\t{ .compatible = \"pifi,pifi-mini-210\",\n+\t\t.data = (void *) &drvdata_pifi_mini_210 },\n \t{},\n };\n \n-static struct snd_soc_card snd_rpi_simple = {\n-\t.driver_name  = \"RPi-simple\",\n-\t.owner        = THIS_MODULE,\n-\t.dai_link     = NULL,\n-\t.num_links    = 1, /* Only a single DAI supported at the moment */\n-};\n-\n static int snd_rpi_simple_probe(struct platform_device *pdev)\n {\n \tint ret = 0;\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0468-bcm2835-isp-Allow-formats-with-different-colour-spac.patch",
    "content": "From bfa002eac168328b599ea70ed81667c03b16cb7e Mon Sep 17 00:00:00 2001\nFrom: David Plowman <david.plowman@raspberrypi.com>\nDate: Tue, 12 Jan 2021 13:55:39 +0000\nSubject: [PATCH] bcm2835-isp: Allow formats with different colour\n spaces.\n\nEach supported format now includes a mask showing the allowed colour\nspaces, as well as a default colour space for when one was not\nspecified.\n\nAdditionally we translate the colour space to mmal format and pass it\nover to the VideoCore.\n\nSigned-off-by: David Plowman <david.plowman@raspberrypi.com>\n---\n .../bcm2835-isp/bcm2835-isp-fmts.h            | 180 ++++++++++++------\n .../bcm2835-isp/bcm2835-v4l2-isp.c            |  66 ++++++-\n 2 files changed, 190 insertions(+), 56 deletions(-)\n\n--- a/drivers/staging/vc04_services/bcm2835-isp/bcm2835-isp-fmts.h\n+++ b/drivers/staging/vc04_services/bcm2835-isp/bcm2835-isp-fmts.h\n@@ -20,10 +20,29 @@ struct bcm2835_isp_fmt {\n \tint bytesperline_align;\n \tu32 mmal_fmt;\n \tint size_multiplier_x2;\n-\tenum v4l2_colorspace colorspace;\n+\tu32 colorspace_mask;\n+\tenum v4l2_colorspace colorspace_default;\n \tunsigned int step_size;\n };\n \n+#define V4L2_COLORSPACE_MASK(colorspace) BIT(colorspace)\n+\n+#define V4L2_COLORSPACE_MASK_JPEG V4L2_COLORSPACE_MASK(V4L2_COLORSPACE_JPEG)\n+#define V4L2_COLORSPACE_MASK_SMPTE170M V4L2_COLORSPACE_MASK(V4L2_COLORSPACE_SMPTE170M)\n+#define V4L2_COLORSPACE_MASK_REC709 V4L2_COLORSPACE_MASK(V4L2_COLORSPACE_REC709)\n+#define V4L2_COLORSPACE_MASK_SRGB V4L2_COLORSPACE_MASK(V4L2_COLORSPACE_SRGB)\n+#define V4L2_COLORSPACE_MASK_RAW V4L2_COLORSPACE_MASK(V4L2_COLORSPACE_RAW)\n+\n+/*\n+ * The colour spaces we support for YUV outputs. SRGB features here because,\n+ * once you assign the default transfer func and so on, it and JPEG effectively\n+ * mean the same.\n+ */\n+#define V4L2_COLORSPACE_MASK_YUV (V4L2_COLORSPACE_MASK_JPEG | \\\n+\t\t\t\t  V4L2_COLORSPACE_MASK_SRGB | \\\n+\t\t\t\t  V4L2_COLORSPACE_MASK_SMPTE170M | \\\n+\t\t\t\t  V4L2_COLORSPACE_MASK_REC709)\n+\n static const struct bcm2835_isp_fmt supported_formats[] = {\n \t{\n \t\t/* YUV formats */\n@@ -32,7 +51,8 @@ static const struct bcm2835_isp_fmt supp\n \t\t.bytesperline_align = 32,\n \t\t.mmal_fmt\t    = MMAL_ENCODING_I420,\n \t\t.size_multiplier_x2 = 3,\n-\t\t.colorspace\t    = V4L2_COLORSPACE_SMPTE170M,\n+\t\t.colorspace_mask    = V4L2_COLORSPACE_MASK_YUV,\n+\t\t.colorspace_default = V4L2_COLORSPACE_JPEG,\n \t\t.step_size\t    = 2,\n \t}, {\n \t\t.fourcc\t\t    = V4L2_PIX_FMT_YVU420,\n@@ -40,7 +60,8 @@ static const struct bcm2835_isp_fmt supp\n \t\t.bytesperline_align = 32,\n \t\t.mmal_fmt\t    = MMAL_ENCODING_YV12,\n \t\t.size_multiplier_x2 = 3,\n-\t\t.colorspace\t    = V4L2_COLORSPACE_SMPTE170M,\n+\t\t.colorspace_mask    = V4L2_COLORSPACE_MASK_YUV,\n+\t\t.colorspace_default = V4L2_COLORSPACE_SMPTE170M,\n \t\t.step_size\t    = 2,\n \t}, {\n \t\t.fourcc\t\t    = V4L2_PIX_FMT_NV12,\n@@ -48,7 +69,8 @@ static const struct bcm2835_isp_fmt supp\n \t\t.bytesperline_align = 32,\n \t\t.mmal_fmt\t    = MMAL_ENCODING_NV12,\n \t\t.size_multiplier_x2 = 3,\n-\t\t.colorspace\t    = V4L2_COLORSPACE_SMPTE170M,\n+\t\t.colorspace_mask    = V4L2_COLORSPACE_MASK_YUV,\n+\t\t.colorspace_default = V4L2_COLORSPACE_SMPTE170M,\n \t\t.step_size\t    = 2,\n \t}, {\n \t\t.fourcc\t\t    = V4L2_PIX_FMT_NV21,\n@@ -56,7 +78,8 @@ static const struct bcm2835_isp_fmt supp\n \t\t.bytesperline_align = 32,\n \t\t.mmal_fmt\t    = MMAL_ENCODING_NV21,\n \t\t.size_multiplier_x2 = 3,\n-\t\t.colorspace\t    = V4L2_COLORSPACE_SMPTE170M,\n+\t\t.colorspace_mask    = V4L2_COLORSPACE_MASK_YUV,\n+\t\t.colorspace_default = V4L2_COLORSPACE_SMPTE170M,\n \t\t.step_size\t    = 2,\n \t}, {\n \t\t.fourcc\t\t    = V4L2_PIX_FMT_YUYV,\n@@ -64,7 +87,8 @@ static const struct bcm2835_isp_fmt supp\n \t\t.bytesperline_align = 64,\n \t\t.mmal_fmt\t    = MMAL_ENCODING_YUYV,\n \t\t.size_multiplier_x2 = 2,\n-\t\t.colorspace\t    = V4L2_COLORSPACE_SMPTE170M,\n+\t\t.colorspace_mask    = V4L2_COLORSPACE_MASK_YUV,\n+\t\t.colorspace_default = V4L2_COLORSPACE_SMPTE170M,\n \t\t.step_size\t    = 2,\n \t}, {\n \t\t.fourcc\t\t    = V4L2_PIX_FMT_UYVY,\n@@ -72,7 +96,8 @@ static const struct bcm2835_isp_fmt supp\n \t\t.bytesperline_align = 64,\n \t\t.mmal_fmt\t    = MMAL_ENCODING_UYVY,\n \t\t.size_multiplier_x2 = 2,\n-\t\t.colorspace\t    = V4L2_COLORSPACE_SMPTE170M,\n+\t\t.colorspace_mask    = V4L2_COLORSPACE_MASK_YUV,\n+\t\t.colorspace_default = V4L2_COLORSPACE_SMPTE170M,\n \t\t.step_size\t    = 2,\n \t}, {\n \t\t.fourcc\t\t    = V4L2_PIX_FMT_YVYU,\n@@ -80,7 +105,8 @@ static const struct bcm2835_isp_fmt supp\n \t\t.bytesperline_align = 64,\n \t\t.mmal_fmt\t    = MMAL_ENCODING_YVYU,\n \t\t.size_multiplier_x2 = 2,\n-\t\t.colorspace\t    = V4L2_COLORSPACE_SMPTE170M,\n+\t\t.colorspace_mask    = V4L2_COLORSPACE_MASK_YUV,\n+\t\t.colorspace_default = V4L2_COLORSPACE_SMPTE170M,\n \t\t.step_size\t    = 2,\n \t}, {\n \t\t.fourcc\t\t    = V4L2_PIX_FMT_VYUY,\n@@ -88,7 +114,8 @@ static const struct bcm2835_isp_fmt supp\n \t\t.bytesperline_align = 64,\n \t\t.mmal_fmt\t    = MMAL_ENCODING_VYUY,\n \t\t.size_multiplier_x2 = 2,\n-\t\t.colorspace\t    = V4L2_COLORSPACE_SMPTE170M,\n+\t\t.colorspace_mask    = V4L2_COLORSPACE_MASK_YUV,\n+\t\t.colorspace_default = V4L2_COLORSPACE_SMPTE170M,\n \t\t.step_size\t    = 2,\n \t}, {\n \t\t/* RGB formats */\n@@ -97,7 +124,8 @@ static const struct bcm2835_isp_fmt supp\n \t\t.bytesperline_align = 32,\n \t\t.mmal_fmt\t    = MMAL_ENCODING_RGB24,\n \t\t.size_multiplier_x2 = 2,\n-\t\t.colorspace\t    = V4L2_COLORSPACE_SRGB,\n+\t\t.colorspace_mask    = V4L2_COLORSPACE_MASK_SRGB,\n+\t\t.colorspace_default = V4L2_COLORSPACE_SRGB,\n \t\t.step_size\t    = 1,\n \t}, {\n \t\t.fourcc\t\t    = V4L2_PIX_FMT_RGB565,\n@@ -105,7 +133,8 @@ static const struct bcm2835_isp_fmt supp\n \t\t.bytesperline_align = 32,\n \t\t.mmal_fmt\t    = MMAL_ENCODING_RGB16,\n \t\t.size_multiplier_x2 = 2,\n-\t\t.colorspace\t    = V4L2_COLORSPACE_SRGB,\n+\t\t.colorspace_mask    = V4L2_COLORSPACE_MASK_SRGB,\n+\t\t.colorspace_default = V4L2_COLORSPACE_SRGB,\n \t\t.step_size\t    = 1,\n \t}, {\n \t\t.fourcc\t\t    = V4L2_PIX_FMT_BGR24,\n@@ -113,7 +142,8 @@ static const struct bcm2835_isp_fmt supp\n \t\t.bytesperline_align = 32,\n \t\t.mmal_fmt\t    = MMAL_ENCODING_BGR24,\n \t\t.size_multiplier_x2 = 2,\n-\t\t.colorspace\t    = V4L2_COLORSPACE_SRGB,\n+\t\t.colorspace_mask    = V4L2_COLORSPACE_MASK_SRGB,\n+\t\t.colorspace_default = V4L2_COLORSPACE_SRGB,\n \t\t.step_size\t    = 1,\n \t}, {\n \t\t.fourcc\t\t    = V4L2_PIX_FMT_XBGR32,\n@@ -121,7 +151,8 @@ static const struct bcm2835_isp_fmt supp\n \t\t.bytesperline_align = 64,\n \t\t.mmal_fmt\t    = MMAL_ENCODING_BGRA,\n \t\t.size_multiplier_x2 = 2,\n-\t\t.colorspace\t    = V4L2_COLORSPACE_SRGB,\n+\t\t.colorspace_mask    = V4L2_COLORSPACE_MASK_SRGB,\n+\t\t.colorspace_default = V4L2_COLORSPACE_SRGB,\n \t\t.step_size\t    = 1,\n \t}, {\n \t\t.fourcc\t\t    = V4L2_PIX_FMT_RGBX32,\n@@ -129,7 +160,8 @@ static const struct bcm2835_isp_fmt supp\n \t\t.bytesperline_align = 64,\n \t\t.mmal_fmt\t    = MMAL_ENCODING_RGBA,\n \t\t.size_multiplier_x2 = 2,\n-\t\t.colorspace\t    = V4L2_COLORSPACE_SRGB,\n+\t\t.colorspace_mask    = V4L2_COLORSPACE_MASK_SRGB,\n+\t\t.colorspace_default = V4L2_COLORSPACE_SRGB,\n \t\t.step_size\t    = 1,\n \t}, {\n \t\t/* Bayer formats */\n@@ -139,7 +171,8 @@ static const struct bcm2835_isp_fmt supp\n \t\t.bytesperline_align = 32,\n \t\t.mmal_fmt\t    = MMAL_ENCODING_BAYER_SRGGB8,\n \t\t.size_multiplier_x2 = 2,\n-\t\t.colorspace\t    = V4L2_COLORSPACE_RAW,\n+\t\t.colorspace_mask    = V4L2_COLORSPACE_MASK_RAW,\n+\t\t.colorspace_default = V4L2_COLORSPACE_RAW,\n \t\t.step_size\t    = 2,\n \t}, {\n \t\t.fourcc\t\t    = V4L2_PIX_FMT_SBGGR8,\n@@ -147,7 +180,8 @@ static const struct bcm2835_isp_fmt supp\n \t\t.bytesperline_align = 32,\n \t\t.mmal_fmt\t    = MMAL_ENCODING_BAYER_SBGGR8,\n \t\t.size_multiplier_x2 = 2,\n-\t\t.colorspace\t    = V4L2_COLORSPACE_RAW,\n+\t\t.colorspace_mask    = V4L2_COLORSPACE_MASK_RAW,\n+\t\t.colorspace_default = V4L2_COLORSPACE_RAW,\n \t\t.step_size\t    = 2,\n \t}, {\n \t\t.fourcc\t\t    = V4L2_PIX_FMT_SGRBG8,\n@@ -155,7 +189,8 @@ static const struct bcm2835_isp_fmt supp\n \t\t.bytesperline_align = 32,\n \t\t.mmal_fmt\t    = MMAL_ENCODING_BAYER_SGRBG8,\n \t\t.size_multiplier_x2 = 2,\n-\t\t.colorspace\t    = V4L2_COLORSPACE_RAW,\n+\t\t.colorspace_mask    = V4L2_COLORSPACE_MASK_RAW,\n+\t\t.colorspace_default = V4L2_COLORSPACE_RAW,\n \t\t.step_size\t    = 2,\n \t}, {\n \t\t.fourcc\t\t    = V4L2_PIX_FMT_SGBRG8,\n@@ -163,7 +198,8 @@ static const struct bcm2835_isp_fmt supp\n \t\t.bytesperline_align = 32,\n \t\t.mmal_fmt\t    = MMAL_ENCODING_BAYER_SGBRG8,\n \t\t.size_multiplier_x2 = 2,\n-\t\t.colorspace\t    = V4L2_COLORSPACE_RAW,\n+\t\t.colorspace_mask    = V4L2_COLORSPACE_MASK_RAW,\n+\t\t.colorspace_default = V4L2_COLORSPACE_RAW,\n \t\t.step_size\t    = 2,\n \t}, {\n \t\t/* 10 bit */\n@@ -172,7 +208,8 @@ static const struct bcm2835_isp_fmt supp\n \t\t.bytesperline_align = 32,\n \t\t.mmal_fmt\t    = MMAL_ENCODING_BAYER_SRGGB10P,\n \t\t.size_multiplier_x2 = 2,\n-\t\t.colorspace\t    = V4L2_COLORSPACE_RAW,\n+\t\t.colorspace_mask    = V4L2_COLORSPACE_MASK_RAW,\n+\t\t.colorspace_default = V4L2_COLORSPACE_RAW,\n \t\t.step_size\t    = 2,\n \t}, {\n \t\t.fourcc\t\t    = V4L2_PIX_FMT_SBGGR10P,\n@@ -180,7 +217,8 @@ static const struct bcm2835_isp_fmt supp\n \t\t.bytesperline_align = 32,\n \t\t.mmal_fmt\t    = MMAL_ENCODING_BAYER_SBGGR10P,\n \t\t.size_multiplier_x2 = 2,\n-\t\t.colorspace\t    = V4L2_COLORSPACE_RAW,\n+\t\t.colorspace_mask    = V4L2_COLORSPACE_MASK_RAW,\n+\t\t.colorspace_default = V4L2_COLORSPACE_RAW,\n \t\t.step_size\t    = 2,\n \t}, {\n \t\t.fourcc\t\t    = V4L2_PIX_FMT_SGRBG10P,\n@@ -188,7 +226,8 @@ static const struct bcm2835_isp_fmt supp\n \t\t.bytesperline_align = 32,\n \t\t.mmal_fmt\t    = MMAL_ENCODING_BAYER_SGRBG10P,\n \t\t.size_multiplier_x2 = 2,\n-\t\t.colorspace\t    = V4L2_COLORSPACE_RAW,\n+\t\t.colorspace_mask    = V4L2_COLORSPACE_MASK_RAW,\n+\t\t.colorspace_default = V4L2_COLORSPACE_RAW,\n \t\t.step_size\t    = 2,\n \t}, {\n \t\t.fourcc\t\t    = V4L2_PIX_FMT_SGBRG10P,\n@@ -196,7 +235,8 @@ static const struct bcm2835_isp_fmt supp\n \t\t.bytesperline_align = 32,\n \t\t.mmal_fmt\t    = MMAL_ENCODING_BAYER_SGBRG10P,\n \t\t.size_multiplier_x2 = 2,\n-\t\t.colorspace\t    = V4L2_COLORSPACE_RAW,\n+\t\t.colorspace_mask    = V4L2_COLORSPACE_MASK_RAW,\n+\t\t.colorspace_default = V4L2_COLORSPACE_RAW,\n \t\t.step_size\t    = 2,\n \t}, {\n \t\t/* 12 bit */\n@@ -205,7 +245,8 @@ static const struct bcm2835_isp_fmt supp\n \t\t.bytesperline_align = 32,\n \t\t.mmal_fmt\t    = MMAL_ENCODING_BAYER_SRGGB12P,\n \t\t.size_multiplier_x2 = 2,\n-\t\t.colorspace\t    = V4L2_COLORSPACE_RAW,\n+\t\t.colorspace_mask    = V4L2_COLORSPACE_MASK_RAW,\n+\t\t.colorspace_default = V4L2_COLORSPACE_RAW,\n \t\t.step_size\t    = 2,\n \t}, {\n \t\t.fourcc\t\t    = V4L2_PIX_FMT_SBGGR12P,\n@@ -213,7 +254,8 @@ static const struct bcm2835_isp_fmt supp\n \t\t.bytesperline_align = 32,\n \t\t.mmal_fmt\t    = MMAL_ENCODING_BAYER_SBGGR12P,\n \t\t.size_multiplier_x2 = 2,\n-\t\t.colorspace\t    = V4L2_COLORSPACE_RAW,\n+\t\t.colorspace_mask    = V4L2_COLORSPACE_MASK_RAW,\n+\t\t.colorspace_default = V4L2_COLORSPACE_RAW,\n \t\t.step_size\t    = 2,\n \t}, {\n \t\t.fourcc\t\t    = V4L2_PIX_FMT_SGRBG12P,\n@@ -221,7 +263,8 @@ static const struct bcm2835_isp_fmt supp\n \t\t.bytesperline_align = 32,\n \t\t.mmal_fmt\t    = MMAL_ENCODING_BAYER_SGRBG12P,\n \t\t.size_multiplier_x2 = 2,\n-\t\t.colorspace\t    = V4L2_COLORSPACE_RAW,\n+\t\t.colorspace_mask    = V4L2_COLORSPACE_MASK_RAW,\n+\t\t.colorspace_default = V4L2_COLORSPACE_RAW,\n \t\t.step_size\t    = 2,\n \t}, {\n \t\t.fourcc\t\t    = V4L2_PIX_FMT_SGBRG12P,\n@@ -229,7 +272,8 @@ static const struct bcm2835_isp_fmt supp\n \t\t.bytesperline_align = 32,\n \t\t.mmal_fmt\t    = MMAL_ENCODING_BAYER_SGBRG12P,\n \t\t.size_multiplier_x2 = 2,\n-\t\t.colorspace\t    = V4L2_COLORSPACE_RAW,\n+\t\t.colorspace_mask    = V4L2_COLORSPACE_MASK_RAW,\n+\t\t.colorspace_default = V4L2_COLORSPACE_RAW,\n \t\t.step_size\t    = 2,\n \t}, {\n \t\t/* 14 bit */\n@@ -238,7 +282,8 @@ static const struct bcm2835_isp_fmt supp\n \t\t.bytesperline_align = 32,\n \t\t.mmal_fmt\t    = MMAL_ENCODING_BAYER_SRGGB14P,\n \t\t.size_multiplier_x2 = 2,\n-\t\t.colorspace\t    = V4L2_COLORSPACE_RAW,\n+\t\t.colorspace_mask    = V4L2_COLORSPACE_MASK_RAW,\n+\t\t.colorspace_default = V4L2_COLORSPACE_RAW,\n \t\t.step_size\t    = 2,\n \t}, {\n \t\t.fourcc\t\t    = V4L2_PIX_FMT_SBGGR14P,\n@@ -246,7 +291,8 @@ static const struct bcm2835_isp_fmt supp\n \t\t.bytesperline_align = 32,\n \t\t.mmal_fmt\t    = MMAL_ENCODING_BAYER_SBGGR14P,\n \t\t.size_multiplier_x2 = 2,\n-\t\t.colorspace\t    = V4L2_COLORSPACE_RAW,\n+\t\t.colorspace_mask    = V4L2_COLORSPACE_MASK_RAW,\n+\t\t.colorspace_default = V4L2_COLORSPACE_RAW,\n \t\t.step_size\t    = 2,\n \t}, {\n \t\t.fourcc\t\t    = V4L2_PIX_FMT_SGRBG14P,\n@@ -254,7 +300,8 @@ static const struct bcm2835_isp_fmt supp\n \t\t.bytesperline_align = 32,\n \t\t.mmal_fmt\t    = MMAL_ENCODING_BAYER_SGRBG14P,\n \t\t.size_multiplier_x2 = 2,\n-\t\t.colorspace\t    = V4L2_COLORSPACE_RAW,\n+\t\t.colorspace_mask    = V4L2_COLORSPACE_MASK_RAW,\n+\t\t.colorspace_default = V4L2_COLORSPACE_RAW,\n \t\t.step_size\t    = 2,\n \t}, {\n \t\t.fourcc\t\t    = V4L2_PIX_FMT_SGBRG14P,\n@@ -262,7 +309,8 @@ static const struct bcm2835_isp_fmt supp\n \t\t.bytesperline_align = 32,\n \t\t.mmal_fmt\t    = MMAL_ENCODING_BAYER_SGBRG14P,\n \t\t.size_multiplier_x2 = 2,\n-\t\t.colorspace\t    = V4L2_COLORSPACE_RAW,\n+\t\t.colorspace_mask    = V4L2_COLORSPACE_MASK_RAW,\n+\t\t.colorspace_default = V4L2_COLORSPACE_RAW,\n \t\t.step_size\t    = 2,\n \t}, {\n \t\t/* 16 bit */\n@@ -271,7 +319,8 @@ static const struct bcm2835_isp_fmt supp\n \t\t.bytesperline_align = 32,\n \t\t.mmal_fmt\t    = MMAL_ENCODING_BAYER_SRGGB16,\n \t\t.size_multiplier_x2 = 2,\n-\t\t.colorspace\t    = V4L2_COLORSPACE_RAW,\n+\t\t.colorspace_mask    = V4L2_COLORSPACE_MASK_RAW,\n+\t\t.colorspace_default = V4L2_COLORSPACE_RAW,\n \t\t.step_size\t    = 2,\n \t}, {\n \t\t.fourcc\t\t    = V4L2_PIX_FMT_SBGGR16,\n@@ -279,7 +328,8 @@ static const struct bcm2835_isp_fmt supp\n \t\t.bytesperline_align = 32,\n \t\t.mmal_fmt\t    = MMAL_ENCODING_BAYER_SBGGR16,\n \t\t.size_multiplier_x2 = 2,\n-\t\t.colorspace\t    = V4L2_COLORSPACE_RAW,\n+\t\t.colorspace_mask    = V4L2_COLORSPACE_MASK_RAW,\n+\t\t.colorspace_default = V4L2_COLORSPACE_RAW,\n \t\t.step_size\t    = 2,\n \t}, {\n \t\t.fourcc\t\t    = V4L2_PIX_FMT_SGRBG16,\n@@ -287,7 +337,8 @@ static const struct bcm2835_isp_fmt supp\n \t\t.bytesperline_align = 32,\n \t\t.mmal_fmt\t    = MMAL_ENCODING_BAYER_SGRBG16,\n \t\t.size_multiplier_x2 = 2,\n-\t\t.colorspace\t    = V4L2_COLORSPACE_RAW,\n+\t\t.colorspace_mask    = V4L2_COLORSPACE_MASK_RAW,\n+\t\t.colorspace_default = V4L2_COLORSPACE_RAW,\n \t\t.step_size\t    = 2,\n \t}, {\n \t\t.fourcc\t\t    = V4L2_PIX_FMT_SGBRG16,\n@@ -295,7 +346,8 @@ static const struct bcm2835_isp_fmt supp\n \t\t.bytesperline_align = 32,\n \t\t.mmal_fmt\t    = MMAL_ENCODING_BAYER_SGBRG16,\n \t\t.size_multiplier_x2 = 2,\n-\t\t.colorspace\t    = V4L2_COLORSPACE_RAW,\n+\t\t.colorspace_mask    = V4L2_COLORSPACE_MASK_RAW,\n+\t\t.colorspace_default = V4L2_COLORSPACE_RAW,\n \t\t.step_size\t    = 2,\n \t}, {\n \t\t/* Bayer formats unpacked to 16bpp */\n@@ -305,7 +357,8 @@ static const struct bcm2835_isp_fmt supp\n \t\t.bytesperline_align = 32,\n \t\t.mmal_fmt\t    = MMAL_ENCODING_BAYER_SRGGB10,\n \t\t.size_multiplier_x2 = 2,\n-\t\t.colorspace\t    = V4L2_COLORSPACE_RAW,\n+\t\t.colorspace_mask    = V4L2_COLORSPACE_MASK_RAW,\n+\t\t.colorspace_default = V4L2_COLORSPACE_RAW,\n \t\t.step_size\t    = 2,\n \t}, {\n \t\t.fourcc\t\t    = V4L2_PIX_FMT_SBGGR10,\n@@ -313,7 +366,8 @@ static const struct bcm2835_isp_fmt supp\n \t\t.bytesperline_align = 32,\n \t\t.mmal_fmt\t    = MMAL_ENCODING_BAYER_SBGGR10,\n \t\t.size_multiplier_x2 = 2,\n-\t\t.colorspace\t    = V4L2_COLORSPACE_RAW,\n+\t\t.colorspace_mask    = V4L2_COLORSPACE_MASK_RAW,\n+\t\t.colorspace_default = V4L2_COLORSPACE_RAW,\n \t\t.step_size\t    = 2,\n \t}, {\n \t\t.fourcc\t\t    = V4L2_PIX_FMT_SGRBG10,\n@@ -321,7 +375,8 @@ static const struct bcm2835_isp_fmt supp\n \t\t.bytesperline_align = 32,\n \t\t.mmal_fmt\t    = MMAL_ENCODING_BAYER_SGRBG10,\n \t\t.size_multiplier_x2 = 2,\n-\t\t.colorspace\t    = V4L2_COLORSPACE_RAW,\n+\t\t.colorspace_mask    = V4L2_COLORSPACE_MASK_RAW,\n+\t\t.colorspace_default = V4L2_COLORSPACE_RAW,\n \t\t.step_size\t    = 2,\n \t}, {\n \t\t.fourcc\t\t    = V4L2_PIX_FMT_SGBRG10,\n@@ -329,7 +384,8 @@ static const struct bcm2835_isp_fmt supp\n \t\t.bytesperline_align = 32,\n \t\t.mmal_fmt\t    = MMAL_ENCODING_BAYER_SGBRG10,\n \t\t.size_multiplier_x2 = 2,\n-\t\t.colorspace\t    = V4L2_COLORSPACE_RAW,\n+\t\t.colorspace_mask    = V4L2_COLORSPACE_MASK_RAW,\n+\t\t.colorspace_default = V4L2_COLORSPACE_RAW,\n \t\t.step_size\t    = 2,\n \t}, {\n \t\t/* 12 bit */\n@@ -338,7 +394,8 @@ static const struct bcm2835_isp_fmt supp\n \t\t.bytesperline_align = 32,\n \t\t.mmal_fmt\t    = MMAL_ENCODING_BAYER_SRGGB12,\n \t\t.size_multiplier_x2 = 2,\n-\t\t.colorspace\t    = V4L2_COLORSPACE_RAW,\n+\t\t.colorspace_mask    = V4L2_COLORSPACE_MASK_RAW,\n+\t\t.colorspace_default = V4L2_COLORSPACE_RAW,\n \t\t.step_size\t    = 2,\n \t}, {\n \t\t.fourcc\t\t    = V4L2_PIX_FMT_SBGGR12,\n@@ -346,7 +403,8 @@ static const struct bcm2835_isp_fmt supp\n \t\t.bytesperline_align = 32,\n \t\t.mmal_fmt\t    = MMAL_ENCODING_BAYER_SBGGR12,\n \t\t.size_multiplier_x2 = 2,\n-\t\t.colorspace\t    = V4L2_COLORSPACE_RAW,\n+\t\t.colorspace_mask    = V4L2_COLORSPACE_MASK_RAW,\n+\t\t.colorspace_default = V4L2_COLORSPACE_RAW,\n \t\t.step_size\t    = 2,\n \t}, {\n \t\t.fourcc\t\t    = V4L2_PIX_FMT_SGRBG12,\n@@ -354,7 +412,8 @@ static const struct bcm2835_isp_fmt supp\n \t\t.bytesperline_align = 32,\n \t\t.mmal_fmt\t    = MMAL_ENCODING_BAYER_SGRBG12,\n \t\t.size_multiplier_x2 = 2,\n-\t\t.colorspace\t    = V4L2_COLORSPACE_RAW,\n+\t\t.colorspace_mask    = V4L2_COLORSPACE_MASK_RAW,\n+\t\t.colorspace_default = V4L2_COLORSPACE_RAW,\n \t\t.step_size\t    = 2,\n \t}, {\n \t\t.fourcc\t\t    = V4L2_PIX_FMT_SGBRG12,\n@@ -362,7 +421,8 @@ static const struct bcm2835_isp_fmt supp\n \t\t.bytesperline_align = 32,\n \t\t.mmal_fmt\t    = MMAL_ENCODING_BAYER_SGBRG12,\n \t\t.size_multiplier_x2 = 2,\n-\t\t.colorspace\t    = V4L2_COLORSPACE_RAW,\n+\t\t.colorspace_mask    = V4L2_COLORSPACE_MASK_RAW,\n+\t\t.colorspace_default = V4L2_COLORSPACE_RAW,\n \t\t.step_size\t    = 2,\n \t}, {\n \t\t/* 14 bit */\n@@ -371,7 +431,8 @@ static const struct bcm2835_isp_fmt supp\n \t\t.bytesperline_align = 32,\n \t\t.mmal_fmt\t    = MMAL_ENCODING_BAYER_SRGGB14,\n \t\t.size_multiplier_x2 = 2,\n-\t\t.colorspace\t    = V4L2_COLORSPACE_RAW,\n+\t\t.colorspace_mask    = V4L2_COLORSPACE_MASK_RAW,\n+\t\t.colorspace_default = V4L2_COLORSPACE_RAW,\n \t\t.step_size\t    = 2,\n \t}, {\n \t\t.fourcc\t\t    = V4L2_PIX_FMT_SBGGR14,\n@@ -379,7 +440,8 @@ static const struct bcm2835_isp_fmt supp\n \t\t.bytesperline_align = 32,\n \t\t.mmal_fmt\t    = MMAL_ENCODING_BAYER_SBGGR14,\n \t\t.size_multiplier_x2 = 2,\n-\t\t.colorspace\t    = V4L2_COLORSPACE_RAW,\n+\t\t.colorspace_mask    = V4L2_COLORSPACE_MASK_RAW,\n+\t\t.colorspace_default = V4L2_COLORSPACE_RAW,\n \t\t.step_size\t    = 2,\n \t}, {\n \t\t.fourcc\t\t    = V4L2_PIX_FMT_SGRBG14,\n@@ -387,7 +449,8 @@ static const struct bcm2835_isp_fmt supp\n \t\t.bytesperline_align = 32,\n \t\t.mmal_fmt\t    = MMAL_ENCODING_BAYER_SGRBG14,\n \t\t.size_multiplier_x2 = 2,\n-\t\t.colorspace\t    = V4L2_COLORSPACE_RAW,\n+\t\t.colorspace_mask    = V4L2_COLORSPACE_MASK_RAW,\n+\t\t.colorspace_default = V4L2_COLORSPACE_RAW,\n \t\t.step_size\t    = 2,\n \t}, {\n \t\t.fourcc\t\t    = V4L2_PIX_FMT_SGBRG14,\n@@ -395,7 +458,8 @@ static const struct bcm2835_isp_fmt supp\n \t\t.bytesperline_align = 32,\n \t\t.mmal_fmt\t    = MMAL_ENCODING_BAYER_SGBRG14,\n \t\t.size_multiplier_x2 = 2,\n-\t\t.colorspace\t    = V4L2_COLORSPACE_RAW,\n+\t\t.colorspace_mask    = V4L2_COLORSPACE_MASK_RAW,\n+\t\t.colorspace_default = V4L2_COLORSPACE_RAW,\n \t\t.step_size\t    = 2,\n \t}, {\n \t\t/* Monochrome MIPI formats */\n@@ -405,7 +469,8 @@ static const struct bcm2835_isp_fmt supp\n \t\t.bytesperline_align = 32,\n \t\t.mmal_fmt\t    = MMAL_ENCODING_GREY,\n \t\t.size_multiplier_x2 = 2,\n-\t\t.colorspace\t    = V4L2_COLORSPACE_RAW,\n+\t\t.colorspace_mask    = V4L2_COLORSPACE_MASK_RAW,\n+\t\t.colorspace_default = V4L2_COLORSPACE_RAW,\n \t\t.step_size\t    = 2,\n \t}, {\n \t\t/* 10 bit */\n@@ -414,7 +479,8 @@ static const struct bcm2835_isp_fmt supp\n \t\t.bytesperline_align = 32,\n \t\t.mmal_fmt\t    = MMAL_ENCODING_Y10P,\n \t\t.size_multiplier_x2 = 2,\n-\t\t.colorspace\t    = V4L2_COLORSPACE_RAW,\n+\t\t.colorspace_mask    = V4L2_COLORSPACE_MASK_RAW,\n+\t\t.colorspace_default = V4L2_COLORSPACE_RAW,\n \t\t.step_size\t    = 2,\n \t}, {\n \t\t/* 12 bit */\n@@ -423,7 +489,8 @@ static const struct bcm2835_isp_fmt supp\n \t\t.bytesperline_align = 32,\n \t\t.mmal_fmt\t    = MMAL_ENCODING_Y12P,\n \t\t.size_multiplier_x2 = 2,\n-\t\t.colorspace\t    = V4L2_COLORSPACE_RAW,\n+\t\t.colorspace_mask    = V4L2_COLORSPACE_MASK_RAW,\n+\t\t.colorspace_default = V4L2_COLORSPACE_RAW,\n \t\t.step_size\t    = 2,\n \t}, {\n \t\t/* 14 bit */\n@@ -432,7 +499,8 @@ static const struct bcm2835_isp_fmt supp\n \t\t.bytesperline_align = 32,\n \t\t.mmal_fmt\t    = MMAL_ENCODING_Y14P,\n \t\t.size_multiplier_x2 = 2,\n-\t\t.colorspace\t    = V4L2_COLORSPACE_RAW,\n+\t\t.colorspace_mask    = V4L2_COLORSPACE_MASK_RAW,\n+\t\t.colorspace_default = V4L2_COLORSPACE_RAW,\n \t\t.step_size\t    = 2,\n \t}, {\n \t\t/* 16 bit */\n@@ -441,7 +509,8 @@ static const struct bcm2835_isp_fmt supp\n \t\t.bytesperline_align = 32,\n \t\t.mmal_fmt\t    = MMAL_ENCODING_Y16,\n \t\t.size_multiplier_x2 = 2,\n-\t\t.colorspace\t    = V4L2_COLORSPACE_RAW,\n+\t\t.colorspace_mask    = V4L2_COLORSPACE_MASK_RAW,\n+\t\t.colorspace_default = V4L2_COLORSPACE_RAW,\n \t\t.step_size\t    = 2,\n \t}, {\n \t\t/* 10 bit as 16bpp */\n@@ -450,7 +519,8 @@ static const struct bcm2835_isp_fmt supp\n \t\t.bytesperline_align = 32,\n \t\t.mmal_fmt\t    = MMAL_ENCODING_Y10,\n \t\t.size_multiplier_x2 = 2,\n-\t\t.colorspace\t    = V4L2_COLORSPACE_RAW,\n+\t\t.colorspace_mask    = V4L2_COLORSPACE_MASK_RAW,\n+\t\t.colorspace_default = V4L2_COLORSPACE_RAW,\n \t\t.step_size\t    = 2,\n \t}, {\n \t\t/* 12 bit as 16bpp */\n@@ -459,7 +529,8 @@ static const struct bcm2835_isp_fmt supp\n \t\t.bytesperline_align = 32,\n \t\t.mmal_fmt\t    = MMAL_ENCODING_Y12,\n \t\t.size_multiplier_x2 = 2,\n-\t\t.colorspace\t    = V4L2_COLORSPACE_RAW,\n+\t\t.colorspace_mask    = V4L2_COLORSPACE_MASK_RAW,\n+\t\t.colorspace_default = V4L2_COLORSPACE_RAW,\n \t\t.step_size\t    = 2,\n \t}, {\n \t\t/* 14 bit as 16bpp */\n@@ -468,7 +539,8 @@ static const struct bcm2835_isp_fmt supp\n \t\t.bytesperline_align = 32,\n \t\t.mmal_fmt\t    = MMAL_ENCODING_Y14,\n \t\t.size_multiplier_x2 = 2,\n-\t\t.colorspace\t    = V4L2_COLORSPACE_RAW,\n+\t\t.colorspace_mask    = V4L2_COLORSPACE_MASK_RAW,\n+\t\t.colorspace_default = V4L2_COLORSPACE_RAW,\n \t\t.step_size\t    = 2,\n \t}, {\n \t\t.fourcc\t\t    = V4L2_META_FMT_BCM2835_ISP_STATS,\n--- a/drivers/staging/vc04_services/bcm2835-isp/bcm2835-v4l2-isp.c\n+++ b/drivers/staging/vc04_services/bcm2835-isp/bcm2835-v4l2-isp.c\n@@ -72,6 +72,7 @@ struct bcm2835_isp_q_data {\n \tunsigned int width;\n \tunsigned int height;\n \tunsigned int sizeimage;\n+\tenum v4l2_colorspace colorspace;\n \tconst struct bcm2835_isp_fmt *fmt;\n };\n \n@@ -311,6 +312,43 @@ static void mmal_buffer_cb(struct vchiq_\n \t\tcomplete(&dev->frame_cmplt);\n }\n \n+struct colorspace_translation {\n+\tenum v4l2_colorspace v4l2_value;\n+\tu32 mmal_value;\n+};\n+\n+static u32 translate_color_space(enum v4l2_colorspace color_space)\n+{\n+\tstatic const struct colorspace_translation translations[] = {\n+\t\t{ V4L2_COLORSPACE_DEFAULT, MMAL_COLOR_SPACE_UNKNOWN },\n+\t\t{ V4L2_COLORSPACE_SMPTE170M, MMAL_COLOR_SPACE_ITUR_BT601 },\n+\t\t{ V4L2_COLORSPACE_SMPTE240M, MMAL_COLOR_SPACE_SMPTE240M },\n+\t\t{ V4L2_COLORSPACE_REC709, MMAL_COLOR_SPACE_ITUR_BT709 },\n+\t\t/* V4L2_COLORSPACE_BT878 unavailable */\n+\t\t{ V4L2_COLORSPACE_470_SYSTEM_M, MMAL_COLOR_SPACE_BT470_2_M },\n+\t\t{ V4L2_COLORSPACE_470_SYSTEM_BG, MMAL_COLOR_SPACE_BT470_2_BG },\n+\t\t{ V4L2_COLORSPACE_JPEG, MMAL_COLOR_SPACE_JPEG_JFIF },\n+\t\t/*\n+\t\t * We don't have an encoding for SRGB as such, but VideoCore\n+\t\t * will do the right thing if it gets \"unknown\".\n+\t\t */\n+\t\t{ V4L2_COLORSPACE_SRGB, MMAL_COLOR_SPACE_UNKNOWN },\n+\t\t/* V4L2_COLORSPACE_OPRGB unavailable */\n+\t\t/* V4L2_COLORSPACE_BT2020 unavailable */\n+\t\t/* V4L2_COLORSPACE_RAW unavailable */\n+\t\t/* V4L2_COLORSPACE_DCI_P3 unavailable */\n+\t};\n+\n+\tunsigned int i;\n+\n+\tfor (i = 0; i < ARRAY_SIZE(translations); i++) {\n+\t\tif (color_space == translations[i].v4l2_value)\n+\t\t\treturn translations[i].mmal_value;\n+\t}\n+\n+\treturn MMAL_COLOR_SPACE_UNKNOWN;\n+}\n+\n static void setup_mmal_port_format(struct bcm2835_isp_node *node,\n \t\t\t\t   struct vchiq_mmal_port *port)\n {\n@@ -324,6 +362,7 @@ static void setup_mmal_port_format(struc\n \tport->es.video.crop.height = q_data->height;\n \tport->es.video.crop.x = 0;\n \tport->es.video.crop.y = 0;\n+\tport->es.video.color_space = translate_color_space(q_data->colorspace);\n };\n \n static int setup_mmal_port(struct bcm2835_isp_node *node)\n@@ -827,6 +866,9 @@ static int populate_qdata_fmt(struct v4l\n \t\t/* All parameters should have been set correctly by try_fmt */\n \t\tq_data->bytesperline = f->fmt.pix.bytesperline;\n \t\tq_data->sizeimage = f->fmt.pix.sizeimage;\n+\n+\t\t/* We must indicate which of the allowed colour spaces we have. */\n+\t\tq_data->colorspace = f->fmt.pix.colorspace;\n \t} else {\n \t\tv4l2_dbg(1, debug, &dev->v4l2_dev,\n \t\t\t \"%s: Setting meta format for fmt: %08x, size %u\\n\",\n@@ -838,6 +880,9 @@ static int populate_qdata_fmt(struct v4l\n \t\tq_data->height = 0;\n \t\tq_data->bytesperline = 0;\n \t\tq_data->sizeimage = f->fmt.meta.buffersize;\n+\n+\t\t/* This won't mean anything for metadata, but may as well fill it in. */\n+\t\tq_data->colorspace = V4L2_COLORSPACE_DEFAULT;\n \t}\n \n \tv4l2_dbg(1, debug, &dev->v4l2_dev,\n@@ -901,7 +946,7 @@ static int bcm2835_isp_node_g_fmt(struct\n \t\tf->fmt.pix.pixelformat = q_data->fmt->fourcc;\n \t\tf->fmt.pix.bytesperline = q_data->bytesperline;\n \t\tf->fmt.pix.sizeimage = q_data->sizeimage;\n-\t\tf->fmt.pix.colorspace = q_data->fmt->colorspace;\n+\t\tf->fmt.pix.colorspace = q_data->colorspace;\n \t}\n \n \treturn 0;\n@@ -968,13 +1013,29 @@ static int bcm2835_isp_node_try_fmt(stru\n \t\tfmt = get_default_format(node);\n \n \tif (!node_is_stats(node)) {\n+\t\tint is_rgb;\n+\n \t\tf->fmt.pix.width = max(min(f->fmt.pix.width, MAX_DIM),\n \t\t\t\t       MIN_DIM);\n \t\tf->fmt.pix.height = max(min(f->fmt.pix.height, MAX_DIM),\n \t\t\t\t\tMIN_DIM);\n \n \t\tf->fmt.pix.pixelformat = fmt->fourcc;\n-\t\tf->fmt.pix.colorspace = fmt->colorspace;\n+\n+\t\t/*\n+\t\t * Fill in the actual colour space when the requested one was\n+\t\t * not supported. This also catches the case when the \"default\"\n+\t\t * colour space was requested (as that's never in the mask).\n+\t\t */\n+\t\tif (!(V4L2_COLORSPACE_MASK(f->fmt.pix.colorspace) & fmt->colorspace_mask))\n+\t\t\tf->fmt.pix.colorspace = fmt->colorspace_default;\n+\t\t/* In all cases, we only support the defaults for these: */\n+\t\tf->fmt.pix.ycbcr_enc = V4L2_MAP_YCBCR_ENC_DEFAULT(f->fmt.pix.colorspace);\n+\t\tf->fmt.pix.xfer_func = V4L2_MAP_XFER_FUNC_DEFAULT(f->fmt.pix.colorspace);\n+\t\tis_rgb = f->fmt.pix.colorspace == V4L2_COLORSPACE_SRGB;\n+\t\tf->fmt.pix.quantization = V4L2_MAP_QUANTIZATION_DEFAULT(is_rgb, f->fmt.pix.colorspace,\n+\t\t\t\t\t\t\t\t\tf->fmt.pix.ycbcr_enc);\n+\n \t\tf->fmt.pix.bytesperline = get_bytesperline(f->fmt.pix.width,\n \t\t\t\t\t\t\t   fmt);\n \t\tf->fmt.pix.field = V4L2_FIELD_NONE;\n@@ -1299,6 +1360,7 @@ static int register_node(struct bcm2835_\n \t\t\t\t\t       node->q_data.width,\n \t\t\t\t\t       node->q_data.height,\n \t\t\t\t\t       node->q_data.fmt);\n+\tnode->q_data.colorspace = node->q_data.fmt->colorspace_default;\n \n \tqueue->io_modes = VB2_MMAP | VB2_DMABUF;\n \tqueue->drv_priv = node;\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0469-Hifiberry-DAC-ADC-Pro-fix-for-the-PLL-when-changing-.patch",
    "content": "From efe6cdae919bf4beffbef1e5691f2766182e0803 Mon Sep 17 00:00:00 2001\nFrom: Joerg Schambacher <joerg@i2audio.com>\nDate: Mon, 1 Feb 2021 16:53:46 +0100\nSubject: [PATCH] Hifiberry DAC+ADC Pro fix for the PLL when changing\n sample rates\n\nAdds 2 msecs delay when switching between oscillators to allow\ncorrect PLL settling.\nThanks to Clive Messer for the support!\n\nSigned-off-by: Joerg Schambacher <joerg@hifiberry.com>\n---\n sound/soc/bcm/hifiberry_dacplusadcpro.c | 14 ++++----------\n 1 file changed, 4 insertions(+), 10 deletions(-)\n\n--- a/sound/soc/bcm/hifiberry_dacplusadcpro.c\n+++ b/sound/soc/bcm/hifiberry_dacplusadcpro.c\n@@ -190,6 +190,7 @@ static void snd_rpi_hifiberry_dacplusadc\n \t\t\t\tPCM512x_GPIO_CONTROL_1, 0x24, 0x04);\n \t\tbreak;\n \t}\n+\tusleep_range(2000, 2100);\n }\n \n static void snd_rpi_hifiberry_dacplusadcpro_clk_gpio(struct snd_soc_component *component)\n@@ -207,13 +208,6 @@ static bool snd_rpi_hifiberry_dacplusadc\n \treturn (!(sck & 0x40));\n }\n \n-static bool snd_rpi_hifiberry_dacplusadcpro_is_sclk_sleep(\n-\tstruct snd_soc_component *component)\n-{\n-\tmsleep(2);\n-\treturn snd_rpi_hifiberry_dacplusadcpro_is_sclk(component);\n-}\n-\n static bool snd_rpi_hifiberry_dacplusadcpro_is_pro_card(struct snd_soc_component *component)\n {\n \tbool isClk44EN, isClk48En, isNoClk;\n@@ -221,13 +215,13 @@ static bool snd_rpi_hifiberry_dacplusadc\n \tsnd_rpi_hifiberry_dacplusadcpro_clk_gpio(component);\n \n \tsnd_rpi_hifiberry_dacplusadcpro_select_clk(component, HIFIBERRY_DACPRO_CLK44EN);\n-\tisClk44EN = snd_rpi_hifiberry_dacplusadcpro_is_sclk_sleep(component);\n+\tisClk44EN = snd_rpi_hifiberry_dacplusadcpro_is_sclk(component);\n \n \tsnd_rpi_hifiberry_dacplusadcpro_select_clk(component, HIFIBERRY_DACPRO_NOCLOCK);\n-\tisNoClk = snd_rpi_hifiberry_dacplusadcpro_is_sclk_sleep(component);\n+\tisNoClk = snd_rpi_hifiberry_dacplusadcpro_is_sclk(component);\n \n \tsnd_rpi_hifiberry_dacplusadcpro_select_clk(component, HIFIBERRY_DACPRO_CLK48EN);\n-\tisClk48En = snd_rpi_hifiberry_dacplusadcpro_is_sclk_sleep(component);\n+\tisClk48En = snd_rpi_hifiberry_dacplusadcpro_is_sclk(component);\n \n \treturn (isClk44EN && isClk48En && !isNoClk);\n }\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0470-Fixed-picture-line-bug-in-all-ov9281-modes.patch",
    "content": "From 02fe3934ba9b18cf48ad905626df8591cdfab8cf Mon Sep 17 00:00:00 2001\nFrom: Mathias Anhalt <mathiasanhalt@web.de>\nDate: Sun, 24 Jan 2021 15:15:01 +0100\nSubject: [PATCH] Fixed picture line bug in all ov9281 modes\n\nSigned-off-by: Mathias Anhalt <mathiasanhalt@web.de>\n---\n drivers/media/i2c/ov9281.c | 5 +++--\n 1 file changed, 3 insertions(+), 2 deletions(-)\n\n--- a/drivers/media/i2c/ov9281.c\n+++ b/drivers/media/i2c/ov9281.c\n@@ -205,7 +205,7 @@ static const struct regval ov9281_common\n };\n \n static const struct regval ov9281_1280x800_regs[] = {\n-\t{0x3778, 0x10},\n+\t{0x3778, 0x00},\n \t{0x3800, 0x00},\n \t{0x3801, 0x00},\n \t{0x3802, 0x00},\n@@ -241,7 +241,7 @@ static const struct regval ov9281_1280x8\n };\n \n static const struct regval ov9281_1280x720_regs[] = {\n-\t{0x3778, 0x10},\n+\t{0x3778, 0x00},\n \t{0x3800, 0x00},\n \t{0x3801, 0x00},\n \t{0x3802, 0x00},\n@@ -277,6 +277,7 @@ static const struct regval ov9281_1280x7\n };\n \n static const struct regval ov9281_640x400_regs[] = {\n+\t{0x3778, 0x10},\n \t{0x3800, 0x00},\n \t{0x3801, 0x00},\n \t{0x3802, 0x00},\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0471-Added-hflip-and-vflip-controls-to-ov9281.patch",
    "content": "From 6c7ebe661716fc23c52cd800a173e4675b10202a Mon Sep 17 00:00:00 2001\nFrom: Mathias Anhalt <mathiasanhalt@web.de>\nDate: Wed, 3 Feb 2021 20:34:09 +0100\nSubject: [PATCH] Added hflip and vflip controls to ov9281\n\nSigned-off-by: Mathias Anhalt <mathiasanhalt@web.de>\n---\n drivers/media/i2c/ov9281.c | 58 +++++++++++++++++++++++++++++++++++++-\n 1 file changed, 57 insertions(+), 1 deletion(-)\n\n--- a/drivers/media/i2c/ov9281.c\n+++ b/drivers/media/i2c/ov9281.c\n@@ -40,6 +40,10 @@\n #define CHIP_ID\t\t\t\t0x9281\n #define OV9281_REG_CHIP_ID\t\t0x300a\n \n+#define OV9281_REG_TIMING_FORMAT_1\t\t0x3820\n+#define OV9281_REG_TIMING_FORMAT_2\t\t0x3821\n+#define OV9281_FLIP_BIT\t\t\t\tBIT(2)\n+\n #define OV9281_REG_CTRL_MODE\t\t0x0100\n #define OV9281_MODE_SW_STANDBY\t\t0x0\n #define OV9281_MODE_STREAMING\t\tBIT(0)\n@@ -123,6 +127,8 @@ struct ov9281 {\n \tstruct v4l2_ctrl\t*digi_gain;\n \tstruct v4l2_ctrl\t*hblank;\n \tstruct v4l2_ctrl\t*vblank;\n+\tstruct v4l2_ctrl\t*hflip;\n+\tstruct v4l2_ctrl\t*vflip;\n \tstruct v4l2_ctrl\t*pixel_rate;\n \tstruct v4l2_ctrl\t*test_pattern;\n \tstruct mutex\t\tmutex;\n@@ -615,6 +621,42 @@ static int ov9281_enable_test_pattern(st\n \t\t\t\tOV9281_REG_VALUE_08BIT, val);\n }\n \n+static int ov9281_set_ctrl_hflip(struct ov9281 *ov9281, int value)\n+{\n+\tu32 current_val;\n+\tint ret = ov9281_read_reg(ov9281->client, OV9281_REG_TIMING_FORMAT_2,\n+\t\t\t\t\tOV9281_REG_VALUE_08BIT, &current_val);\n+\tif (!ret) {\n+\t\tif (value)\n+\t\t\tcurrent_val |= OV9281_FLIP_BIT;\n+\t\telse\n+\t\t\tcurrent_val &= ~OV9281_FLIP_BIT;\n+\t\treturn ov9281_write_reg(ov9281->client,\n+\t\t\t\t\t\tOV9281_REG_TIMING_FORMAT_2,\n+\t\t\t\t\t\tOV9281_REG_VALUE_08BIT,\n+\t\t\t\t\t\tcurrent_val);\n+\t}\n+\treturn ret;\n+}\n+\n+static int ov9281_set_ctrl_vflip(struct ov9281 *ov9281, int value)\n+{\n+\tu32 current_val;\n+\tint ret = ov9281_read_reg(ov9281->client, OV9281_REG_TIMING_FORMAT_1,\n+\t\t\t\t\tOV9281_REG_VALUE_08BIT, &current_val);\n+\tif (!ret) {\n+\t\tif (value)\n+\t\t\tcurrent_val |= OV9281_FLIP_BIT;\n+\t\telse\n+\t\t\tcurrent_val &= ~OV9281_FLIP_BIT;\n+\t\treturn ov9281_write_reg(ov9281->client,\n+\t\t\t\t\t\tOV9281_REG_TIMING_FORMAT_1,\n+\t\t\t\t\t\tOV9281_REG_VALUE_08BIT,\n+\t\t\t\t\t\tcurrent_val);\n+\t}\n+\treturn ret;\n+}\n+\n static const struct v4l2_rect *\n __ov9281_get_pad_crop(struct ov9281 *ov9281, struct v4l2_subdev_pad_config *cfg,\n \t\t      unsigned int pad, enum v4l2_subdev_format_whence which)\n@@ -933,6 +975,12 @@ static int ov9281_set_ctrl(struct v4l2_c\n \t\treturn 0;\n \n \tswitch (ctrl->id) {\n+\tcase V4L2_CID_HFLIP:\n+\t\tret = ov9281_set_ctrl_hflip(ov9281, ctrl->val);\n+\t\tbreak;\n+\tcase V4L2_CID_VFLIP:\n+\t\tret = ov9281_set_ctrl_vflip(ov9281, ctrl->val);\n+\t\tbreak;\n \tcase V4L2_CID_EXPOSURE:\n \t\t/* 4 least significant bits of expsoure are fractional part */\n \t\tret = ov9281_write_reg(ov9281->client, OV9281_REG_EXPOSURE,\n@@ -981,7 +1029,7 @@ static int ov9281_initialize_controls(st\n \n \thandler = &ov9281->ctrl_handler;\n \tmode = ov9281->cur_mode;\n-\tret = v4l2_ctrl_handler_init(handler, 8);\n+\tret = v4l2_ctrl_handler_init(handler, 9);\n \tif (ret)\n \t\treturn ret;\n \thandler->lock = &ov9281->mutex;\n@@ -1022,6 +1070,14 @@ static int ov9281_initialize_controls(st\n \t\t\t\t\t      OV9281_GAIN_STEP,\n \t\t\t\t\t      OV9281_GAIN_DEFAULT);\n \n+\tov9281->vflip = v4l2_ctrl_new_std(handler, &ov9281_ctrl_ops,\n+\t\t\t\t\t  V4L2_CID_VFLIP,\n+\t\t\t\t\t\t0, 1, 1, 0);\n+\n+\tov9281->hflip = v4l2_ctrl_new_std(handler, &ov9281_ctrl_ops,\n+\t\t\t\t\t  V4L2_CID_HFLIP,\n+\t\t\t\t\t\t0, 1, 1, 0);\n+\n \tov9281->test_pattern =\n \t\tv4l2_ctrl_new_std_menu_items(handler, &ov9281_ctrl_ops,\n \t\t\t\t\t     V4L2_CID_TEST_PATTERN,\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0472-gpio-fsm-Rename-num-soft-gpios-to-avoid-warning.patch",
    "content": "From f55b35f2dbd1ab60fe8d59c56ae1cbad2f3e67ab Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.com>\nDate: Mon, 15 Feb 2021 10:25:35 +0000\nSubject: [PATCH] gpio-fsm: Rename 'num-soft-gpios' to avoid warning\n\nAs of 5.10, the Device Tree parser warns about properties that look\nlike references to \"suppliers\" of various services. \"num-soft-gpios\"\nresembles a declaration of a GPIO called \"num-soft\", causing the value\nto be interpreted as a phandle, the owner of which is checked for a\n\"#gpio-cells\" property.\n\nTo avoid this warning, rename the gpio-fsm property to \"num-swgpios\".\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.com>\n---\n drivers/gpio/gpio-fsm.c | 5 +++--\n 1 file changed, 3 insertions(+), 2 deletions(-)\n\n--- a/drivers/gpio/gpio-fsm.c\n+++ b/drivers/gpio/gpio-fsm.c\n@@ -866,8 +866,9 @@ static int gpio_fsm_probe(struct platfor\n \t\t[SYM_SHUTDOWN] = \"shutdown_state\",\n \t};\n \n-\tif (of_property_read_u32(np, \"num-soft-gpios\", &num_soft_gpios)) {\n-\t\tdev_err(dev, \"missing 'num-soft-gpios' property\\n\");\n+\tif (of_property_read_u32(np, \"num-swgpios\", &num_soft_gpios) &&\n+\t    of_property_read_u32(np, \"num-soft-gpios\", &num_soft_gpios)) {\n+\t\tdev_err(dev, \"missing 'num-swgpios' property\\n\");\n \t\treturn -EINVAL;\n \t}\n \n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0473-overlays-Rename-gpio-fsm-property-num-soft-gpios.patch",
    "content": "From 89a7202785673e8bcef072ebcbe1eb0599b8ba88 Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.com>\nDate: Mon, 15 Feb 2021 10:32:18 +0000\nSubject: [PATCH] overlays: Rename gpio-fsm property num-soft-gpios\n\nThe gpio-fsm property \"num-soft-gpios\" triggers a kernel DT checker\nthat warns about the lack of #gpio-cells on a random node with the\nphandle that just happens to match the number of soft GPIOs. Rename\nthe property to \"num-swgpios\" to avoid the warning.\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.com>\n---\n arch/arm/boot/dts/overlays/fsm-demo-overlay.dts  | 2 +-\n arch/arm/boot/dts/overlays/ghost-amp-overlay.dts | 2 +-\n 2 files changed, 2 insertions(+), 2 deletions(-)\n\n--- a/arch/arm/boot/dts/overlays/fsm-demo-overlay.dts\n+++ b/arch/arm/boot/dts/overlays/fsm-demo-overlay.dts\n@@ -22,7 +22,7 @@\n \t\t\t\tdebug = <0>;\n \t\t\t\tgpio-controller;\n \t\t\t\t#gpio-cells = <2>;\n-\t\t\t\tnum-soft-gpios = <1>;\n+\t\t\t\tnum-swgpios = <1>;\n \t\t\t\tgpio-line-names = \"button2\";\n \t\t\t\tinput-gpios  = <&gpio 6 1>;  // BUTTON1 (active-low)\n \t\t\t\toutput-gpios = <&gpio 7 0>,  // RED\n--- a/arch/arm/boot/dts/overlays/ghost-amp-overlay.dts\n+++ b/arch/arm/boot/dts/overlays/ghost-amp-overlay.dts\n@@ -58,7 +58,7 @@\n \t\t\t\tdebug = <0>;\n \t\t\t\tgpio-controller;\n \t\t\t\t#gpio-cells = <2>;\n-\t\t\t\tnum-soft-gpios = <1>;\n+\t\t\t\tnum-swgpios = <1>;\n \t\t\t\tgpio-line-names = \"enable\";\n \t\t\t\tinput-gpios  = <&gpio 5 1>;  // FAULT (active low)\n \t\t\t\toutput-gpios = <&gpio 22 0>, // RELAY1\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0474-drm-fix-HDR-static-metadata-type-field-numbering.patch",
    "content": "From 9b1a01165ec1821802d2ec2090f3667e9faf9e79 Mon Sep 17 00:00:00 2001\nFrom: Laurentiu Palcu <laurentiu.palcu@nxp.com>\nDate: Wed, 27 Nov 2019 14:42:35 +0000\nSubject: [PATCH] drm: fix HDR static metadata type field numbering\n\nAccording to CTA-861 specification, HDR static metadata data block allows a\nsink to indicate which HDR metadata types it supports by setting the SM_0 to\nSM_7 bits. Currently, only Static Metadata Type 1 is supported and this is\nindicated by setting the SM_0 bit to 1.\n\nHowever, the connector->hdr_sink_metadata.hdmi_type1.metadata_type is always\n0, because hdr_metadata_type() in drm_edid.c checks the wrong bit.\n\nThis patch corrects the HDMI_STATIC_METADATA_TYPE1 bit position.\n\nSigned-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>\n---\n include/linux/hdmi.h | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/include/linux/hdmi.h\n+++ b/include/linux/hdmi.h\n@@ -156,7 +156,7 @@ enum hdmi_content_type {\n };\n \n enum hdmi_metadata_type {\n-\tHDMI_STATIC_METADATA_TYPE1 = 1,\n+\tHDMI_STATIC_METADATA_TYPE1 = 0,\n };\n \n enum hdmi_eotf {\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0475-drm-vc4-Add-HDR-metadata-property-to-the-VC5-HDMI-co.patch",
    "content": "From 82a5aa1df1b04efef46c7be82a7d71ea5300ce92 Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Wed, 2 Dec 2020 18:36:24 +0000\nSubject: [PATCH] drm/vc4: Add HDR metadata property to the VC5 HDMI\n connectors\n\nNow that we can export deeper colour depths, add in the signalling\nfor HDR metadata.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n drivers/gpu/drm/vc4/vc4_hdmi.c | 28 ++++++++++++++++++++++++++++\n drivers/gpu/drm/vc4/vc4_hdmi.h |  3 +++\n 2 files changed, 31 insertions(+)\n\n--- a/drivers/gpu/drm/vc4/vc4_hdmi.c\n+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c\n@@ -310,6 +310,10 @@ static int vc4_hdmi_connector_init(struc\n \tconnector->doublescan_allowed = 0;\n \tconnector->stereo_allowed = 1;\n \n+\tif (vc4_hdmi->variant->supports_hdr)\n+\t\tdrm_object_attach_property(&connector->base,\n+\t\t\tconnector->dev->mode_config.hdr_output_metadata_property, 0);\n+\n \tdrm_connector_attach_encoder(connector, encoder);\n \n \treturn 0;\n@@ -449,6 +453,25 @@ static void vc4_hdmi_set_audio_infoframe\n \tvc4_hdmi_write_infoframe(encoder, &frame);\n }\n \n+static void vc4_hdmi_set_hdr_infoframe(struct drm_encoder *encoder)\n+{\n+\tstruct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);\n+\tstruct drm_connector *connector = &vc4_hdmi->connector;\n+\tstruct drm_connector_state *conn_state = connector->state;\n+\tunion hdmi_infoframe frame;\n+\n+\tif (!vc4_hdmi->variant->supports_hdr)\n+\t\treturn;\n+\n+\tif (!conn_state->hdr_output_metadata)\n+\t\treturn;\n+\n+\tif (drm_hdmi_infoframe_set_hdr_metadata(&frame.drm, conn_state))\n+\t\treturn;\n+\n+\tvc4_hdmi_write_infoframe(encoder, &frame);\n+}\n+\n static void vc4_hdmi_set_infoframes(struct drm_encoder *encoder)\n {\n \tstruct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);\n@@ -461,6 +484,8 @@ static void vc4_hdmi_set_infoframes(stru\n \t */\n \tif (vc4_hdmi->audio.streaming)\n \t\tvc4_hdmi_set_audio_infoframe(encoder);\n+\n+\tvc4_hdmi_set_hdr_infoframe(encoder);\n }\n \n static void vc4_hdmi_encoder_post_crtc_disable(struct drm_encoder *encoder,\n@@ -2298,6 +2323,7 @@ static const struct vc4_hdmi_variant bcm\n \t.phy_rng_enable\t\t= vc4_hdmi_phy_rng_enable,\n \t.phy_rng_disable\t= vc4_hdmi_phy_rng_disable,\n \t.channel_map\t\t= vc4_hdmi_channel_map,\n+\t.supports_hdr\t\t= false,\n };\n \n static const struct vc4_hdmi_variant bcm2711_hdmi0_variant = {\n@@ -2325,6 +2351,7 @@ static const struct vc4_hdmi_variant bcm\n \t.phy_rng_enable\t\t= vc5_hdmi_phy_rng_enable,\n \t.phy_rng_disable\t= vc5_hdmi_phy_rng_disable,\n \t.channel_map\t\t= vc5_hdmi_channel_map,\n+\t.supports_hdr\t\t= true,\n };\n \n static const struct vc4_hdmi_variant bcm2711_hdmi1_variant = {\n@@ -2352,6 +2379,7 @@ static const struct vc4_hdmi_variant bcm\n \t.phy_rng_enable\t\t= vc5_hdmi_phy_rng_enable,\n \t.phy_rng_disable\t= vc5_hdmi_phy_rng_disable,\n \t.channel_map\t\t= vc5_hdmi_channel_map,\n+\t.supports_hdr\t\t= true,\n };\n \n static const struct of_device_id vc4_hdmi_dt_match[] = {\n--- a/drivers/gpu/drm/vc4/vc4_hdmi.h\n+++ b/drivers/gpu/drm/vc4/vc4_hdmi.h\n@@ -99,6 +99,9 @@ struct vc4_hdmi_variant {\n \n \t/* Callback to get channel map */\n \tu32 (*channel_map)(struct vc4_hdmi *vc4_hdmi, u32 channel_mask);\n+\n+\t/* Enables HDR metadata */\n+\tbool supports_hdr;\n };\n \n /* HDMI audio information */\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0476-drm-vc4-Add-connector-check-to-trigger-mode_change-w.patch",
    "content": "From c8a76985213abda828a2098c3d6ce8a49b5f9766 Mon Sep 17 00:00:00 2001\nFrom: Dom Cobley <popcornmix@gmail.com>\nDate: Fri, 5 Feb 2021 14:07:12 +0000\nSubject: [PATCH] drm/vc4: Add connector check to trigger mode_change\n when hdr metadata changes\n\nSigned-off-by: Dom Cobley <popcornmix@gmail.com>\n---\n drivers/gpu/drm/vc4/vc4_hdmi.c | 40 ++++++++++++++++++++++++++++++++++\n 1 file changed, 40 insertions(+)\n\n--- a/drivers/gpu/drm/vc4/vc4_hdmi.c\n+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c\n@@ -224,6 +224,45 @@ static int vc4_hdmi_connector_get_modes(\n \treturn ret;\n }\n \n+static bool hdr_metadata_equal(const struct drm_connector_state *old_state,\n+\t\t\t       const struct drm_connector_state *new_state)\n+{\n+\tstruct drm_property_blob *old_blob = old_state->hdr_output_metadata;\n+\tstruct drm_property_blob *new_blob = new_state->hdr_output_metadata;\n+\n+\tif (!old_blob || !new_blob)\n+\t\treturn old_blob == new_blob;\n+\n+\tif (old_blob->length != new_blob->length)\n+\t\treturn false;\n+\n+\treturn !memcmp(old_blob->data, new_blob->data, old_blob->length);\n+}\n+\n+static int vc4_hdmi_connector_atomic_check(struct drm_connector *connector,\n+\t\t\t\t\t  struct drm_atomic_state *state)\n+{\n+\tstruct drm_connector_state *old_state =\n+\t\tdrm_atomic_get_old_connector_state(state, connector);\n+\tstruct drm_connector_state *new_state =\n+\t\tdrm_atomic_get_new_connector_state(state, connector);\n+\tstruct drm_crtc *crtc = new_state->crtc;\n+\tstruct drm_crtc_state *crtc_state;\n+\n+\tif (!crtc)\n+\t\treturn 0;\n+\n+\tif (!hdr_metadata_equal(old_state, new_state)) {\n+\t\tcrtc_state = drm_atomic_get_crtc_state(state, crtc);\n+\t\tif (IS_ERR(crtc_state))\n+\t\t\treturn PTR_ERR(crtc_state);\n+\n+\t\tcrtc_state->mode_changed = true;\n+\t}\n+\n+\treturn 0;\n+}\n+\n static void vc4_hdmi_connector_reset(struct drm_connector *connector)\n {\n \tstruct vc4_hdmi_connector_state *old_state =\n@@ -273,6 +312,7 @@ static const struct drm_connector_funcs\n \n static const struct drm_connector_helper_funcs vc4_hdmi_connector_helper_funcs = {\n \t.get_modes = vc4_hdmi_connector_get_modes,\n+\t.atomic_check = vc4_hdmi_connector_atomic_check,\n };\n \n static int vc4_hdmi_connector_init(struct drm_device *dev,\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0477-staging-rpivid-Fix-crash-when-CMA-alloc-fails.patch",
    "content": "From 8ae4692aefa338ae3fff89c513fddd0400ea7a2a Mon Sep 17 00:00:00 2001\nFrom: John Cox <jc@kynesim.co.uk>\nDate: Mon, 8 Feb 2021 16:01:37 +0000\nSubject: [PATCH] staging: rpivid: Fix crash when CMA alloc fails\n\nIf realloc to increase coeff size fails then attempt to re-allocate\nthe original size.  If that also fails then flag a fatal error to abort\nall further decode.\n\nSigned-off-by: John Cox <jc@kynesim.co.uk>\n---\n drivers/staging/media/rpivid/rpivid.h      |  3 ++\n drivers/staging/media/rpivid/rpivid_h265.c | 44 +++++++++++++++++++++-\n 2 files changed, 45 insertions(+), 2 deletions(-)\n\n--- a/drivers/staging/media/rpivid/rpivid.h\n+++ b/drivers/staging/media/rpivid/rpivid.h\n@@ -88,6 +88,9 @@ struct rpivid_ctx {\n \tstruct v4l2_pix_format\t\tsrc_fmt;\n \tstruct v4l2_pix_format\t\tdst_fmt;\n \tint dst_fmt_set;\n+\t// fatal_err is set if an error has occurred s.t. decode cannot\n+\t// continue (such as running out of CMA)\n+\tint fatal_err;\n \n \tstruct v4l2_ctrl_handler\thdl;\n \tstruct v4l2_ctrl\t\t**ctrls;\n--- a/drivers/staging/media/rpivid/rpivid_h265.c\n+++ b/drivers/staging/media/rpivid/rpivid_h265.c\n@@ -73,10 +73,18 @@ static void gptr_free(struct rpivid_dev\n \tgptr->attrs = 0;\n }\n \n-/* Realloc but do not copy */\n+/* Realloc but do not copy\n+ *\n+ * Frees then allocs.\n+ * If the alloc fails then it attempts to re-allocote the old size\n+ * On error then check gptr->ptr to determine if anything is currently\n+ * allocated.\n+ */\n static int gptr_realloc_new(struct rpivid_dev * const dev,\n \t\t\t    struct rpivid_gptr * const gptr, size_t size)\n {\n+\tconst size_t old_size = gptr->size;\n+\n \tif (size == gptr->size)\n \t\treturn 0;\n \n@@ -88,7 +96,21 @@ static int gptr_realloc_new(struct rpivi\n \tgptr->size = size;\n \tgptr->ptr = dma_alloc_attrs(dev->dev, gptr->size,\n \t\t\t\t    &gptr->addr, GFP_KERNEL, gptr->attrs);\n-\treturn gptr->ptr ? 0 : -ENOMEM;\n+\n+\tif (!gptr->ptr) {\n+\t\tgptr->addr = 0;\n+\t\tgptr->size = old_size;\n+\t\tgptr->ptr = dma_alloc_attrs(dev->dev, gptr->size,\n+\t\t\t\t\t    &gptr->addr, GFP_KERNEL, gptr->attrs);\n+\t\tif (!gptr->ptr) {\n+\t\t\tgptr->size = 0;\n+\t\t\tgptr->addr = 0;\n+\t\t\tgptr->attrs = 0;\n+\t\t}\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\treturn 0;\n }\n \n /* floor(log2(x)) */\n@@ -2020,6 +2042,12 @@ static void phase1_thread(struct rpivid_\n \treturn;\n \n fail:\n+\tif (!pu_gptr->addr || !coeff_gptr->addr) {\n+\t\tv4l2_err(&dev->v4l2_dev,\n+\t\t\t \"%s: Fatal: failed to reclaim old alloc\\n\",\n+\t\t\t __func__);\n+\t\tctx->fatal_err = 1;\n+\t}\n \tdec_env_delete(de);\n \txtrace_fin(dev, de);\n \tv4l2_m2m_buf_done_and_job_finish(dev->m2m_dev, ctx->fh.m2m_ctx,\n@@ -2093,6 +2121,9 @@ static void phase1_claimed(struct rpivid\n \n \txtrace_in(dev, de);\n \n+\tif (ctx->fatal_err)\n+\t\tgoto fail;\n+\n \tde->pu_base_vc = pu_gptr->addr;\n \tde->pu_stride =\n \t\tALIGN_DOWN(pu_gptr->size / de->pic_height_in_ctbs_y, 64);\n@@ -2116,6 +2147,14 @@ static void phase1_claimed(struct rpivid\n \tapb_write_vc_addr_final(dev, RPI_CFBASE, de->cmd_copy_gptr->addr);\n \n \txtrace_ok(dev, de);\n+\treturn;\n+\n+fail:\n+\tdec_env_delete(de);\n+\txtrace_fin(dev, de);\n+\tv4l2_m2m_buf_done_and_job_finish(dev->m2m_dev, ctx->fh.m2m_ctx,\n+\t\t\t\t\t VB2_BUF_STATE_ERROR);\n+\txtrace_fail(dev, de);\n }\n \n static void dec_state_delete(struct rpivid_ctx *const ctx)\n@@ -2186,6 +2225,7 @@ static int rpivid_h265_start(struct rpiv\n \tv4l2_info(&dev->v4l2_dev, \"%s: (%dx%d)\\n\", __func__,\n \t\t  ctx->dst_fmt.width, ctx->dst_fmt.height);\n \n+\tctx->fatal_err = 0;\n \tctx->dec0 = NULL;\n \tctx->state = kzalloc(sizeof(*ctx->state), GFP_KERNEL);\n \tif (!ctx->state) {\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0478-dt-Add-option-for-dpi-without-DE-and-PCLK-for-VGA666.patch",
    "content": "From dad204699d870a86849a635ebec84f3259923a0e Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Thu, 4 Feb 2021 14:23:58 +0000\nSubject: [PATCH] dt: Add option for dpi without DE and PCLK (for\n VGA666)\n\nVGA666 doesn't use the DE or PCLK signals, therefore there is\nno point in claiming their use. It's also then possible to\nuse GPIOs 0&1 for DDC to read the EDID from the display.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n arch/arm/boot/dts/bcm270x.dtsi | 6 ++++++\n 1 file changed, 6 insertions(+)\n\n--- a/arch/arm/boot/dts/bcm270x.dtsi\n+++ b/arch/arm/boot/dts/bcm270x.dtsi\n@@ -170,6 +170,12 @@\n \t\t\t     20 21>;\n \t\tbrcm,function = <BCM2835_FSEL_ALT2>;\n \t};\n+\tdpi_18bit_gpio2: dpi_18bit_gpio2 {\n+\t\tbrcm,pins = <2 3 4 5 6 7 8 9 10 11\n+\t\t\t     12 13 14 15 16 17 18 19\n+\t\t\t     20 21>;\n+\t\tbrcm,function = <BCM2835_FSEL_ALT2>;\n+\t};\n };\n \n &uart0 {\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0479-dtoverlays-Add-an-overlay-for-the-VGA666-when-used-w.patch",
    "content": "From 99f2ab0dad947049e0fa62e88c1e4c1feb7ab379 Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Thu, 4 Feb 2021 14:41:10 +0000\nSubject: [PATCH] dtoverlays: Add an overlay for the VGA666 when used\n with vc4-kms-v3d\n\nIncludes optional use of GPIOs 0&1 / BSC0 for DDC to read the EDID\nfrom the display.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n arch/arm/boot/dts/overlays/Makefile           |   1 +\n arch/arm/boot/dts/overlays/README             |  10 ++\n .../dts/overlays/vc4-kms-vga666-overlay.dts   | 100 ++++++++++++++++++\n 3 files changed, 111 insertions(+)\n create mode 100644 arch/arm/boot/dts/overlays/vc4-kms-vga666-overlay.dts\n\n--- a/arch/arm/boot/dts/overlays/Makefile\n+++ b/arch/arm/boot/dts/overlays/Makefile\n@@ -211,6 +211,7 @@ dtbo-$(CONFIG_ARCH_BCM2835) += \\\n \tvc4-kms-kippah-7inch.dtbo \\\n \tvc4-kms-v3d.dtbo \\\n \tvc4-kms-v3d-pi4.dtbo \\\n+\tvc4-kms-vga666.dtbo \\\n \tvga666.dtbo \\\n \tw1-gpio.dtbo \\\n \tw1-gpio-pullup.dtbo \\\n--- a/arch/arm/boot/dts/overlays/README\n+++ b/arch/arm/boot/dts/overlays/README\n@@ -3120,10 +3120,20 @@ Params: cma-512                 CMA is 5\n                                 outputs)\n \n \n+Name:   vc4-kms-vga666\n+Info:   Enable the VGA666 (resistor ladder ADC) for the vc4-kms-v3d driver.\n+        Requires vc4-kms-v3d to be loaded.\n+Load:   dtoverlay=vc4-kms-vga666,<param>\n+Params: ddc                     Enables GPIOs 0&1 as the I2C to read the EDID\n+                                from the display. NB These are NOT 5V tolerant\n+                                GPIOs, therefore level shifters are required.\n+\n+\n Name:   vga666\n Info:   Overlay for the Fen Logic VGA666 board\n         This uses GPIOs 2-21 (so no I2C), and activates the output 2-3 seconds\n         after the kernel has started.\n+        NOT for use with vc4-kms-v3d.\n Load:   dtoverlay=vga666\n Params: <None>\n \n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/vc4-kms-vga666-overlay.dts\n@@ -0,0 +1,100 @@\n+/*\n+ * vc4-kms-vga666-overlay.dts\n+ * Configures a FenLogic or similar VGA666 DPI adapter when using the\n+ * vc4-kms-v3d driver.\n+ * If a suitable I2C level shifter is connected to GPIOs 0&1 and the VGA\n+ * ID1/SDA (pin 12) and ID3/SCL (pin 15) lines, then there is the option to\n+ * enable reading the EDID from the display.\n+ */\n+\n+/dts-v1/;\n+/plugin/;\n+\n+#include <dt-bindings/pinctrl/bcm2835.h>\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget-path = \"/\";\n+\t\t__overlay__ {\n+\t\t\tvga_connector: vga_connector {\n+\t\t\t\tcompatible = \"vga-connector\";\n+\t\t\t\tlabel = \"vga\";\n+\n+\t\t\t\tport {\n+\t\t\t\t\tvga_con_in: endpoint {\n+\t\t\t\t\t\tremote-endpoint = <&vga666_out>;\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\t\t\t};\n+\n+\t\t\tvga_dac {\n+\t\t\t\tcompatible = \"dumb-vga-dac\";\n+\n+\t\t\t\tports {\n+\t\t\t\t\t#address-cells = <1>;\n+\t\t\t\t\t#size-cells = <0>;\n+\n+\t\t\t\t\tport@0 {\n+\t\t\t\t\t\treg = <0>;\n+\n+\t\t\t\t\t\tvga666_in: endpoint {\n+\t\t\t\t\t\t\tremote-endpoint = <&dpi_out>;\n+\t\t\t\t\t\t};\n+\t\t\t\t\t};\n+\n+\t\t\t\t\tport@1 {\n+\t\t\t\t\t\treg = <1>;\n+\n+\t\t\t\t\t\tvga666_out: endpoint {\n+\t\t\t\t\t\t\tremote-endpoint = <&vga_con_in>;\n+\t\t\t\t\t\t};\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\t\t\t};\n+\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&dpi>;\n+\t\t__overlay__  {\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&dpi_18bit_gpio2>;\n+\n+\t\t\tport {\n+\t\t\t\tdpi_out: endpoint@0 {\n+\t\t\t\t\tremote-endpoint = <&vga666_in>;\n+\t\t\t\t};\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&vga_connector>;\n+\t\t__dormant__  {\n+\t\t\tddc-i2c-bus = <&i2c_vc>;\n+\t\t};\n+\t};\n+\n+\tfragment@3 {\n+\t\ttarget = <&i2c0if>;\n+\t\t__dormant__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@4 {\n+\t\ttarget = <&i2c0mux>;\n+\t\t__dormant__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\tddc = <0>,\"=2\", <0>,\"=3\", <0>,\"=4\";\n+\t};\n+};\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0480-drm-vc4-Change-the-default-DPI-format-to-being-18bpp.patch",
    "content": "From 9a5326f4c3a3a066802886f1e09216a1894c943d Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Fri, 12 Feb 2021 17:31:37 +0000\nSubject: [PATCH] drm/vc4: Change the default DPI format to being\n 18bpp, not 24.\n\nDPI hasn't really been used up until now, so the default has\nbeen meaningless.\nIn theory we should be able to pass the desired format for the\nadjacent bridge chip through, but framework seems to be missing\nfor that.\n\nAs the main device to use DPI is the VGA666 or Adafruit Kippah,\nboth of which use RGB666, change the default to being RGB666 instead\nof RGB888.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n drivers/gpu/drm/vc4/vc4_dpi.c | 4 ++--\n 1 file changed, 2 insertions(+), 2 deletions(-)\n\n--- a/drivers/gpu/drm/vc4/vc4_dpi.c\n+++ b/drivers/gpu/drm/vc4/vc4_dpi.c\n@@ -178,8 +178,8 @@ static void vc4_dpi_encoder_enable(struc\n \t\t\tbreak;\n \t\t}\n \t} else {\n-\t\t/* Default to 24bit if no connector found. */\n-\t\tdpi_c |= VC4_SET_FIELD(DPI_FORMAT_24BIT_888_RGB, DPI_FORMAT);\n+\t\t/* Default to 18bit if no connector found. */\n+\t\tdpi_c |= VC4_SET_FIELD(DPI_FORMAT_18BIT_666_RGB_1, DPI_FORMAT);\n \t}\n \n \tif (mode->flags & DRM_MODE_FLAG_NHSYNC)\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0481-gpio-fsm-Show-state-info-in-sys-class-gpio-fsm.patch",
    "content": "From 1e50027d42006cbc42957b5053caf96ee52c7f8c Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.com>\nDate: Sat, 17 Oct 2020 15:42:54 +0100\nSubject: [PATCH] gpio-fsm: Show state info in /sys/class/gpio-fsm\n\nAdd gpio-fsm sysfs entries under /sys/class/gpio-fsm. For each state\nmachine show the current state, which state (if any) will be entered\nafter a delay, and the current value of that delay.\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.com>\n---\n drivers/gpio/gpio-fsm.c | 112 ++++++++++++++++++++++++++++++++++++++--\n 1 file changed, 108 insertions(+), 4 deletions(-)\n\n--- a/drivers/gpio/gpio-fsm.c\n+++ b/drivers/gpio/gpio-fsm.c\n@@ -20,6 +20,7 @@\n #include <linux/interrupt.h>\n #include <linux/module.h>\n #include <linux/platform_device.h>\n+#include <linux/sysfs.h>\n \n #include <dt-bindings/gpio/gpio-fsm.h>\n \n@@ -120,6 +121,7 @@ struct gpio_fsm {\n \tstruct fsm_state *current_state;\n \tstruct fsm_state *next_state;\n \tstruct fsm_state *delay_target_state;\n+\tunsigned int delay_jiffies;\n \tint delay_ms;\n \tunsigned int debug;\n \tbool shutting_down;\n@@ -364,9 +366,10 @@ static void gpio_fsm_enter_state(struct\n \t\t\tjiffies + msecs_to_jiffies(state->shutdown_ms);\n \n \t\tif (gf->shutting_down) {\n+\t\t\tgf->delay_jiffies = gf->shutdown_jiffies;\n \t\t\tgf->delay_target_state = state->shutdown_target;\n \t\t\tgf->delay_ms = state->shutdown_ms;\n-\t\t\tmod_timer(&gf->timer, gf->shutdown_jiffies);\n+\t\t\tmod_timer(&gf->timer, gf->delay_jiffies);\n \t\t}\n \t}\n \n@@ -421,9 +424,10 @@ static void gpio_fsm_enter_state(struct\n \t// 6. Schedule a timer callback if delay_target\n \tif (state->delay_target) {\n \t\tgf->delay_target_state = state->delay_target;\n+\t\tgf->delay_jiffies = jiffies +\n+\t\t\tmsecs_to_jiffies(state->delay_ms);\n \t\tgf->delay_ms = state->delay_ms;\n-\t\tmod_timer(&gf->timer,\n-\t\t\t  jiffies + msecs_to_jiffies(state->delay_ms));\n+\t\tmod_timer(&gf->timer, gf->delay_jiffies);\n \t}\n }\n \n@@ -847,10 +851,81 @@ static int resolve_sym_to_state(struct g\n \treturn 0;\n }\n \n+\n+/*\n+ * /sys/class/gpio-fsm/<fsm-name>/\n+ *   /state ... the current state\n+ */\n+\n+static ssize_t state_show(struct device *dev,\n+\t\t\t  struct device_attribute *attr, char *buf)\n+{\n+\tconst struct gpio_fsm *gf = dev_get_drvdata(dev);\n+\n+\treturn sprintf(buf, \"%s\\n\", gf->current_state->name);\n+}\n+static DEVICE_ATTR_RO(state);\n+\n+static ssize_t delay_state_show(struct device *dev,\n+\t\t\t  struct device_attribute *attr, char *buf)\n+{\n+\tconst struct gpio_fsm *gf = dev_get_drvdata(dev);\n+\n+\treturn sprintf(buf, \"%s\\n\",\n+\t\t       gf->delay_target_state ? gf->delay_target_state->name :\n+\t\t       \"-\");\n+}\n+\n+static DEVICE_ATTR_RO(delay_state);\n+\n+static ssize_t delay_ms_show(struct device *dev,\n+\t\t\t     struct device_attribute *attr, char *buf)\n+{\n+\tconst struct gpio_fsm *gf = dev_get_drvdata(dev);\n+\tint jiffies_left;\n+\n+\tjiffies_left = gf->delay_jiffies - jiffies;\n+\treturn sprintf(buf,\n+\t\t       gf->delay_target_state ? \"%u\\n\" : \"-\\n\",\n+\t\t       jiffies_to_msecs(jiffies_left));\n+}\n+static DEVICE_ATTR_RO(delay_ms);\n+\n+static struct attribute *gpio_fsm_attrs[] = {\n+\t&dev_attr_state.attr,\n+\t&dev_attr_delay_state.attr,\n+\t&dev_attr_delay_ms.attr,\n+\tNULL,\n+};\n+\n+static const struct attribute_group gpio_fsm_group = {\n+\t.attrs = gpio_fsm_attrs,\n+\t//.is_visible = gpio_is_visible,\n+};\n+\n+static const struct attribute_group *gpio_fsm_groups[] = {\n+\t&gpio_fsm_group,\n+\tNULL\n+};\n+\n+static struct attribute *gpio_fsm_class_attrs[] = {\n+\t// There are no top-level attributes\n+\tNULL,\n+};\n+ATTRIBUTE_GROUPS(gpio_fsm_class);\n+\n+static struct class gpio_fsm_class = {\n+\t.name =\t\tMODULE_NAME,\n+\t.owner =\tTHIS_MODULE,\n+\n+\t.class_groups = gpio_fsm_class_groups,\n+};\n+\n static int gpio_fsm_probe(struct platform_device *pdev)\n {\n \tstruct input_gpio_state *inp_state;\n \tstruct device *dev = &pdev->dev;\n+\tstruct device *sysfs_dev;\n \tstruct device_node *np = dev->of_node;\n \tstruct device_node *cp;\n \tstruct gpio_fsm *gf;\n@@ -1029,6 +1104,13 @@ static int gpio_fsm_probe(struct platfor\n \n \tplatform_set_drvdata(pdev, gf);\n \n+\tsysfs_dev = device_create_with_groups(&gpio_fsm_class, dev,\n+\t\t\t\t\t      MKDEV(0, 0), gf,\n+\t\t\t\t\t      gpio_fsm_groups,\n+\t\t\t\t\t      \"%s\", np->name);\n+\tif (IS_ERR(sysfs_dev))\n+\t\tdev_err(gf->dev, \"Error creating sysfs entry\\n\");\n+\n \tif (gf->debug)\n \t\tdev_info(gf->dev, \"Start -> %s\\n\", gf->start_state->name);\n \n@@ -1097,7 +1179,29 @@ static struct platform_driver gpio_fsm_d\n \t.remove = gpio_fsm_remove,\n \t.shutdown = gpio_fsm_shutdown,\n };\n-module_platform_driver(gpio_fsm_driver);\n+\n+static int gpio_fsm_init(void)\n+{\n+\tint ret;\n+\n+\tret = class_register(&gpio_fsm_class);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = platform_driver_register(&gpio_fsm_driver);\n+\tif (ret)\n+\t\tclass_unregister(&gpio_fsm_class);\n+\n+\treturn ret;\n+}\n+module_init(gpio_fsm_init);\n+\n+static void gpio_fsm_exit(void)\n+{\n+\tplatform_driver_unregister(&gpio_fsm_driver);\n+\tclass_unregister(&gpio_fsm_class);\n+}\n+module_exit(gpio_fsm_exit);\n \n MODULE_LICENSE(\"GPL\");\n MODULE_AUTHOR(\"Phil Elwell <phil@raspberrypi.com>\");\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0482-gpio-fsm-Fix-shutdown-timeout-handling.patch",
    "content": "From a8862588c1ebbcb49b0650707020910270a81f07 Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.com>\nDate: Wed, 17 Feb 2021 09:21:30 +0000\nSubject: [PATCH] gpio-fsm: Fix shutdown timeout handling\n\nThe driver is intended to jump directly to a shutdown state in the\nevent of a timeout during shutdown, but the sense of the test was\ninverted.\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.com>\n---\n drivers/gpio/gpio-fsm.c | 3 ++-\n 1 file changed, 2 insertions(+), 1 deletion(-)\n\n--- a/drivers/gpio/gpio-fsm.c\n+++ b/drivers/gpio/gpio-fsm.c\n@@ -1142,7 +1142,8 @@ static int gpio_fsm_remove(struct platfo\n \t\t\t\t   gf->current_state->shutdown_target ==\n \t\t\t\t   gf->current_state,\n \t\t\t\t   msecs_to_jiffies(gf->shutdown_timeout_ms));\n-\t\tif (gf->current_state->shutdown_target == gf->current_state)\n+\t\t/* On failure to reach a shutdown state, jump to one */\n+\t\tif (gf->current_state->shutdown_target != gf->current_state)\n \t\t\tgpio_fsm_enter_state(gf, gf->shutdown_state);\n \t}\n \tcancel_work_sync(&gf->work);\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0483-overlays-fsm-demo-Ensure-all-LEDs-are-turned-off.patch",
    "content": "From 9884944068a577ef556d544ff7f57e4433aa995b Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.com>\nDate: Wed, 17 Feb 2021 09:29:26 +0000\nSubject: [PATCH] overlays: fsm-demo: Ensure all LEDs are turned off\n\nIf the shutdown process is delayed enough to trigger the shutdown\ntimeout then one or more states in the shutdown sequence might be\nskipped. Ensure that all LEDs are turned off regardless by explicitly\ndoing so in the shutdown state, as an example of good practices.\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.com>\n---\n arch/arm/boot/dts/overlays/fsm-demo-overlay.dts | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/arch/arm/boot/dts/overlays/fsm-demo-overlay.dts\n+++ b/arch/arm/boot/dts/overlays/fsm-demo-overlay.dts\n@@ -92,7 +92,7 @@\n \n \t\t\t\tshutdown4 {\n \t\t\t\t\tshutdown_state;\n-\t\t\t\t\tset = <RED 0>;\n+\t\t\t\t\tset = <RED 0>, <AMBER 0>, <GREEN 0>;\n \t\t\t\t};\n \t\t\t};\n \t       };\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0484-media-i2c-imx477-Remove-auto-frame-length-adjusting.patch",
    "content": "From d5517d71c77ba67cb9dc1985a649ff11017eca0e Mon Sep 17 00:00:00 2001\nFrom: Naushir Patuck <naush@raspberrypi.com>\nDate: Wed, 10 Feb 2021 10:18:53 +0000\nSubject: [PATCH] media: i2c: imx477: Remove auto frame length\n adjusting\n\nThe V4L2_CID_EXPOSURE_AUTO_PRIORITY was used to let the sensor control\nframe length (effectively framerate) based on the requested exposure\ntime requested. Remove this feature as it is never used, and goes\nagainst how V4L2 likes to handle exposure and vblank controls.\n\nSigned-off-by: Naushir Patuck <naush@raspberrypi.com>\n---\n drivers/media/i2c/imx477.c | 83 +++-----------------------------------\n 1 file changed, 6 insertions(+), 77 deletions(-)\n\n--- a/drivers/media/i2c/imx477.c\n+++ b/drivers/media/i2c/imx477.c\n@@ -1082,8 +1082,6 @@ struct imx477 {\n \tstruct v4l2_ctrl *hflip;\n \tstruct v4l2_ctrl *vblank;\n \tstruct v4l2_ctrl *hblank;\n-\t/* This ctrl allows automatic variable framerate */\n-\tstruct v4l2_ctrl *exposure_auto;\n \n \t/* Current mode */\n \tconst struct imx477_mode *mode;\n@@ -1280,66 +1278,14 @@ static int imx477_open(struct v4l2_subde\n \treturn 0;\n }\n \n-static int imx477_set_exposure(struct imx477 *imx477, unsigned int val)\n-{\n-\tint ret;\n-\n-\tret = imx477_write_reg(imx477, IMX477_REG_EXPOSURE,\n-\t\t\t       IMX477_REG_VALUE_16BIT, val);\n-\n-\t/* Setup the frame length in the case of auto framerate mode. */\n-\tif (imx477->exposure_auto->val) {\n-\t\tunsigned int frame_length, frame_length_max, frame_length_min;\n-\n-\t\tframe_length_min = imx477->vblank->minimum +\n-\t\t\t\t   imx477->mode->height;\n-\t\tframe_length_max = imx477->vblank->maximum +\n-\t\t\t\t   imx477->mode->height;\n-\t\tframe_length = max(frame_length_min,\n-\t\t\t\t   val + IMX477_EXPOSURE_OFFSET);\n-\t\tframe_length = min(frame_length_max, frame_length);\n-\t\tret += imx477_write_reg(imx477, IMX477_REG_FRAME_LENGTH,\n-\t\t\t\t\tIMX477_REG_VALUE_16BIT, frame_length);\n-\t}\n-\n-\treturn ret;\n-}\n-\n static void imx477_adjust_exposure_range(struct imx477 *imx477,\n \t\t\t\t\t struct v4l2_ctrl *ctrl)\n {\n \tint exposure_max, exposure_def;\n \n-\tif (ctrl->id == V4L2_CID_VBLANK || !ctrl->val) {\n-\t\t/*\n-\t\t * Either VBLANK has been changed or auto framerate\n-\t\t * adjusting has been disabled. Honour the VBLANK limits\n-\t\t * when setting exposure.\n-\t\t */\n-\t\texposure_max = imx477->mode->height + imx477->vblank->val -\n-\t\t\t\t\t\t      IMX477_EXPOSURE_OFFSET;\n-\n-\t\tif (ctrl->id == V4L2_CID_EXPOSURE_AUTO_PRIORITY) {\n-\t\t\t/*\n-\t\t\t * Allow VBLANK adjustments since the driver is not\n-\t\t\t * handling frame length control automatically.\n-\t\t\t */\n-\t\t\t__v4l2_ctrl_grab(imx477->vblank, false);\n-\t\t}\n-\t} else {\n-\t\t/*\n-\t\t * Auto framerate adjusting has been enabled. VBLANK\n-\t\t * ctrl has been disabled and exposure can ramp up\n-\t\t * to the maximum allowable value.\n-\t\t */\n-\t\texposure_max = IMX477_EXPOSURE_MAX;\n-\t\t/*\n-\t\t * Do not allow VBLANK adjustments if the driver is\n-\t\t * handling it frame length control automatically.\n-\t\t */\n-\t\t__v4l2_ctrl_grab(imx477->vblank, true);\n-\t}\n-\n+\t/* Honour the VBLANK limits when setting exposure. */\n+\texposure_max = imx477->mode->height + imx477->vblank->val -\n+\t\t\t\t\t\tIMX477_EXPOSURE_OFFSET;\n \texposure_def = min(exposure_max, imx477->exposure->val);\n \t__v4l2_ctrl_modify_range(imx477->exposure, imx477->exposure->minimum,\n \t\t\t\t exposure_max, imx477->exposure->step,\n@@ -1353,14 +1299,8 @@ static int imx477_set_ctrl(struct v4l2_c\n \tstruct i2c_client *client = v4l2_get_subdevdata(&imx477->sd);\n \tint ret = 0;\n \n-\tif (ctrl->id == V4L2_CID_VBLANK ||\n-\t    ctrl->id == V4L2_CID_EXPOSURE_AUTO_PRIORITY) {\n-\t\t/*\n-\t\t * These controls may change the limits of usable exposure,\n-\t\t * so check and adjust if necessary.\n-\t\t */\n+\tif (ctrl->id == V4L2_CID_VBLANK)\n \t\timx477_adjust_exposure_range(imx477, ctrl);\n-\t}\n \n \t/*\n \t * Applying V4L2 control value only happens\n@@ -1375,14 +1315,8 @@ static int imx477_set_ctrl(struct v4l2_c\n \t\t\t\t       IMX477_REG_VALUE_16BIT, ctrl->val);\n \t\tbreak;\n \tcase V4L2_CID_EXPOSURE:\n-\t\tret = imx477_set_exposure(imx477, ctrl->val);\n-\t\tbreak;\n-\tcase V4L2_CID_EXPOSURE_AUTO_PRIORITY:\n-\t\t/*\n-\t\t * imx477_set_exposure() will recalculate the frame length\n-\t\t * to adjust the framerate to match the exposure.\n-\t\t */\n-\t\tret = imx477_set_exposure(imx477, imx477->exposure->val);\n+\t\tret = imx477_write_reg(imx477, IMX477_REG_EXPOSURE,\n+\t\t\t\t       IMX477_REG_VALUE_16BIT, ctrl->val);\n \t\tbreak;\n \tcase V4L2_CID_DIGITAL_GAIN:\n \t\tret = imx477_write_reg(imx477, IMX477_REG_DIGITAL_GAIN,\n@@ -2005,11 +1939,6 @@ static int imx477_init_controls(struct i\n \t\t\t  IMX477_DGTL_GAIN_MIN, IMX477_DGTL_GAIN_MAX,\n \t\t\t  IMX477_DGTL_GAIN_STEP, IMX477_DGTL_GAIN_DEFAULT);\n \n-\timx477->exposure_auto =\n-\t\t\tv4l2_ctrl_new_std(ctrl_hdlr, &imx477_ctrl_ops,\n-\t\t\t\t\t  V4L2_CID_EXPOSURE_AUTO_PRIORITY,\n-\t\t\t\t\t  0, 1, 1, 0);\n-\n \timx477->hflip = v4l2_ctrl_new_std(ctrl_hdlr, &imx477_ctrl_ops,\n \t\t\t\t\t  V4L2_CID_HFLIP, 0, 1, 1, 0);\n \tif (imx477->hflip)\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0485-media-i2c-imx477-Add-very-long-exposure-control-to-t.patch",
    "content": "From 973d774838b036ceef91e09a7994558c793b4d8a Mon Sep 17 00:00:00 2001\nFrom: Naushir Patuck <naush@raspberrypi.com>\nDate: Wed, 10 Feb 2021 10:50:32 +0000\nSubject: [PATCH] media: i2c: imx477: Add very long exposure control to\n the driver\n\nAdd support for very long exposures by using the exposure multiplier\nregister. Userland does not need to pass any additional controls to\nenable long exposures, it simply requests a larger vblank to extend the\nexposure control range appropriately.\n\nCurrently, since hblank is fixed, a maximum of approximately 124 seconds\nof exposure time can be used. In a future change, hblank could also be\ncontrolled in userland to give over 200 seconds of exposure time.\n\nSigned-off-by: Naushir Patuck <naush@raspberrypi.com>\n---\n drivers/media/i2c/imx477.c | 47 +++++++++++++++++++++++++++++++++-----\n 1 file changed, 41 insertions(+), 6 deletions(-)\n\n--- a/drivers/media/i2c/imx477.c\n+++ b/drivers/media/i2c/imx477.c\n@@ -44,6 +44,10 @@\n #define IMX477_REG_FRAME_LENGTH\t\t0x0340\n #define IMX477_FRAME_LENGTH_MAX\t\t0xffdc\n \n+/* Long exposure multiplier */\n+#define IMX477_LONG_EXP_SHIFT_MAX\t7\n+#define IMX477_LONG_EXP_SHIFT_REG\t0x3100\n+\n /* Exposure control */\n #define IMX477_REG_EXPOSURE\t\t0x0202\n #define IMX477_EXPOSURE_OFFSET\t\t22\n@@ -1097,6 +1101,9 @@ struct imx477 {\n \n \t/* Rewrite common registers on stream on? */\n \tbool common_regs_written;\n+\n+\t/* Current long exposure factor in use. Set through V4L2_CID_VBLANK */\n+\tunsigned int long_exp_shift;\n };\n \n static inline struct imx477 *to_imx477(struct v4l2_subdev *_sd)\n@@ -1285,13 +1292,33 @@ static void imx477_adjust_exposure_range\n \n \t/* Honour the VBLANK limits when setting exposure. */\n \texposure_max = imx477->mode->height + imx477->vblank->val -\n-\t\t\t\t\t\tIMX477_EXPOSURE_OFFSET;\n+\t\t       (IMX477_EXPOSURE_OFFSET << imx477->long_exp_shift);\n \texposure_def = min(exposure_max, imx477->exposure->val);\n \t__v4l2_ctrl_modify_range(imx477->exposure, imx477->exposure->minimum,\n \t\t\t\t exposure_max, imx477->exposure->step,\n \t\t\t\t exposure_def);\n }\n \n+static int imx477_set_frame_length(struct imx477 *imx477, unsigned int val)\n+{\n+\tint ret = 0;\n+\n+\timx477->long_exp_shift = 0;\n+\n+\twhile (val > IMX477_FRAME_LENGTH_MAX) {\n+\t\timx477->long_exp_shift++;\n+\t\tval >>= 1;\n+\t}\n+\n+\tret = imx477_write_reg(imx477, IMX477_REG_FRAME_LENGTH,\n+\t\t\t       IMX477_REG_VALUE_16BIT, val);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\treturn imx477_write_reg(imx477, IMX477_LONG_EXP_SHIFT_REG,\n+\t\t\t\tIMX477_REG_VALUE_08BIT, imx477->long_exp_shift);\n+}\n+\n static int imx477_set_ctrl(struct v4l2_ctrl *ctrl)\n {\n \tstruct imx477 *imx477 =\n@@ -1299,6 +1326,10 @@ static int imx477_set_ctrl(struct v4l2_c\n \tstruct i2c_client *client = v4l2_get_subdevdata(&imx477->sd);\n \tint ret = 0;\n \n+\t/*\n+\t * The VBLANK control may change the limits of usable exposure, so check\n+\t * and adjust if necessary.\n+\t */\n \tif (ctrl->id == V4L2_CID_VBLANK)\n \t\timx477_adjust_exposure_range(imx477, ctrl);\n \n@@ -1316,7 +1347,8 @@ static int imx477_set_ctrl(struct v4l2_c\n \t\tbreak;\n \tcase V4L2_CID_EXPOSURE:\n \t\tret = imx477_write_reg(imx477, IMX477_REG_EXPOSURE,\n-\t\t\t\t       IMX477_REG_VALUE_16BIT, ctrl->val);\n+\t\t\t\t       IMX477_REG_VALUE_16BIT, ctrl->val >>\n+\t\t\t\t\t\t\timx477->long_exp_shift);\n \t\tbreak;\n \tcase V4L2_CID_DIGITAL_GAIN:\n \t\tret = imx477_write_reg(imx477, IMX477_REG_DIGITAL_GAIN,\n@@ -1350,9 +1382,8 @@ static int imx477_set_ctrl(struct v4l2_c\n \t\t\t\t       imx477->vflip->val << 1);\n \t\tbreak;\n \tcase V4L2_CID_VBLANK:\n-\t\tret = imx477_write_reg(imx477, IMX477_REG_FRAME_LENGTH,\n-\t\t\t\t       IMX477_REG_VALUE_16BIT,\n-\t\t\t\t       imx477->mode->height + ctrl->val);\n+\t\tret = imx477_set_frame_length(imx477,\n+\t\t\t\t\t      imx477->mode->height + ctrl->val);\n \t\tbreak;\n \tdefault:\n \t\tdev_info(&client->dev,\n@@ -1521,9 +1552,13 @@ static void imx477_set_framing_limits(st\n \tfrm_length_default =\n \t\t     imx477_get_frame_length(mode, &mode->timeperframe_default);\n \n+\t/* Default to no long exposure multiplier. */\n+\timx477->long_exp_shift = 0;\n+\n \t/* Update limits and set FPS to default */\n \t__v4l2_ctrl_modify_range(imx477->vblank, frm_length_min - mode->height,\n-\t\t\t\t IMX477_FRAME_LENGTH_MAX - mode->height,\n+\t\t\t\t ((1 << IMX477_LONG_EXP_SHIFT_MAX) *\n+\t\t\t\t\tIMX477_FRAME_LENGTH_MAX) - mode->height,\n \t\t\t\t 1, frm_length_default - mode->height);\n \n \t/* Setting this will adjust the exposure limits as well. */\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0486-media-i2c-imx290-Fix-up-exposure-calcuations-and-ran.patch",
    "content": "From 2b7aa91757952e3214ddfd335ae527b89240ecb8 Mon Sep 17 00:00:00 2001\nFrom: David Plowman <david.plowman@raspberrypi.com>\nDate: Wed, 17 Feb 2021 18:08:12 +0000\nSubject: [PATCH] media: i2c: imx290: Fix up exposure calcuations and\n ranges\n\nShould now correspond exactly to the datasheet.\n\nSigned-off-by: David Plowman <david.plowman@raspberrypi.com>\n---\n drivers/media/i2c/imx290.c | 14 +++++++-------\n 1 file changed, 7 insertions(+), 7 deletions(-)\n\n--- a/drivers/media/i2c/imx290.c\n+++ b/drivers/media/i2c/imx290.c\n@@ -50,7 +50,7 @@ enum imx290_clk_index {\n #define IMX290_HMAX_MIN_4LANE 2200 /* Min of 2200 pixels = 60fps */\n #define IMX290_HMAX_MAX 0xffff\n \n-#define IMX290_EXPOSURE_MIN 2\n+#define IMX290_EXPOSURE_MIN 1\n #define IMX290_EXPOSURE_STEP 1\n #define IMX290_EXPOSURE_LOW 0x3020\n #define IMX290_PGCTRL 0x308c\n@@ -584,7 +584,7 @@ static int imx290_set_gain(struct imx290\n static int imx290_set_exposure(struct imx290 *imx290, u32 value)\n {\n \tu32 exposure = (imx290->current_mode->height + imx290->vblank->val) -\n-\t\t\t\t\t\tvalue;\n+\t\t\t\t\t\tvalue - 1;\n \tint ret;\n \n \tret = imx290_write_buffered_reg(imx290, IMX290_EXPOSURE_LOW, 3,\n@@ -855,10 +855,10 @@ static int imx290_set_fmt(struct v4l2_su\n \t\t}\n \t\tif (imx290->exposure)\n \t\t\t__v4l2_ctrl_modify_range(imx290->exposure,\n-\t\t\t\t\t\t mode->vmax - mode->height,\n-\t\t\t\t\t\t mode->vmax - 4,\n+\t\t\t\t\t\t IMX290_EXPOSURE_MIN,\n+\t\t\t\t\t\t mode->vmax - 2,\n \t\t\t\t\t\t IMX290_EXPOSURE_STEP,\n-\t\t\t\t\t\t mode->vmax - 4);\n+\t\t\t\t\t\t mode->vmax - 2);\n \t}\n \n \t*format = fmt->format;\n@@ -1349,9 +1349,9 @@ static int imx290_probe(struct i2c_clien\n \timx290->exposure = v4l2_ctrl_new_std(&imx290->ctrls, &imx290_ctrl_ops,\n \t\t\t\t\t     V4L2_CID_EXPOSURE,\n \t\t\t\t\t     IMX290_EXPOSURE_MIN,\n-\t\t\t\t\t     mode->vmax - 4,\n+\t\t\t\t\t     mode->vmax - 2,\n \t\t\t\t\t     IMX290_EXPOSURE_STEP,\n-\t\t\t\t\t     mode->vmax - 4);\n+\t\t\t\t\t     mode->vmax - 2);\n \n \timx290->hflip = v4l2_ctrl_new_std(&imx290->ctrls, &imx290_ctrl_ops,\n \t\t\t\t\t  V4L2_CID_HFLIP, 0, 1, 1, 0);\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0487-media-i2c-imx290-Handle-exposure-correctly-when-vbla.patch",
    "content": "From 8e9c9047f05e165d158b3718528fc8bcdaf856e8 Mon Sep 17 00:00:00 2001\nFrom: David Plowman <david.plowman@raspberrypi.com>\nDate: Thu, 18 Feb 2021 11:58:29 +0000\nSubject: [PATCH] media: i2c: imx290: Handle exposure correctly when\n vblank changes\n\nWhen vblank changes we must modify the exposure range. Also, with this\nsensor, the effective exposure time implicitly changes when vblank\ndoes, so we have to reset it after every vblank update.\n\nSigned-off-by: David Plowman <david.plowman@raspberrypi.com>\n---\n drivers/media/i2c/imx290.c | 18 ++++++++++++++++++\n 1 file changed, 18 insertions(+)\n\n--- a/drivers/media/i2c/imx290.c\n+++ b/drivers/media/i2c/imx290.c\n@@ -618,6 +618,24 @@ static int imx290_set_vmax(struct imx290\n \tif (ret)\n \t\tdev_err(imx290->dev, \"Unable to write vmax\\n\");\n \n+\t/*\n+\t * Changing vblank changes the allowed range for exposure.\n+\t * We don't supply the current exposure as default here as it\n+\t * may lie outside the new range. We will reset it just below.\n+\t */\n+\t__v4l2_ctrl_modify_range(imx290->exposure,\n+\t\t\t\t IMX290_EXPOSURE_MIN,\n+\t\t\t\t vmax - 2,\n+\t\t\t\t IMX290_EXPOSURE_STEP,\n+\t\t\t\t vmax - 2);\n+\n+\t/*\n+\t * Becuse of the way exposure works for this sensor, updating\n+\t * vblank causes the effective exposure to change, so we must\n+\t * set it back to the \"new\" correct value.\n+\t */\n+\timx290_set_exposure(imx290, imx290->exposure->val);\n+\n \treturn ret;\n }\n \n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0488-DAC-overlays-4154.patch",
    "content": "From 58e6a45fb77833acc3fdaf0460ed3407f22dee63 Mon Sep 17 00:00:00 2001\nFrom: pifi-bz <73530753+pifi-bz@users.noreply.github.com>\nDate: Fri, 19 Feb 2021 13:14:32 +0200\nSubject: [PATCH] DAC overlays  (#4154)\n\nAdding overlays for PiFi DAC Zero and PiFi DAC HD.\n\nSigned-off-by: David Knell <david.knell@gmail.com>\n---\n arch/arm/boot/dts/overlays/Makefile           |  2 +\n arch/arm/boot/dts/overlays/README             | 12 +++++\n .../boot/dts/overlays/pifi-dac-hd-overlay.dts | 49 +++++++++++++++++++\n .../dts/overlays/pifi-dac-zero-overlay.dts    | 49 +++++++++++++++++++\n 4 files changed, 112 insertions(+)\n create mode 100644 arch/arm/boot/dts/overlays/pifi-dac-hd-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/pifi-dac-zero-overlay.dts\n\n--- a/arch/arm/boot/dts/overlays/Makefile\n+++ b/arch/arm/boot/dts/overlays/Makefile\n@@ -130,6 +130,8 @@ dtbo-$(CONFIG_ARCH_BCM2835) += \\\n \tpibell.dtbo \\\n \tpifacedigital.dtbo \\\n \tpifi-40.dtbo \\\n+\tpifi-dac-hd.dtbo \\\n+\tpifi-dac-zero.dtbo \\\n \tpifi-mini-210.dtbo \\\n \tpiglow.dtbo \\\n \tpiscreen.dtbo \\\n--- a/arch/arm/boot/dts/overlays/README\n+++ b/arch/arm/boot/dts/overlays/README\n@@ -2131,6 +2131,18 @@ Load:   dtoverlay=pifi-40\n Params: <None>\n \n \n+Name:   pifi-dac-hd\n+Info:   Configures the PiFi DAC HD\n+Load:   dtoverlay=pifi-dac-hd\n+Params: <None>\n+\n+\n+Name:   pifi-dac-zero\n+Info:   Configures the PiFi DAC Zero\n+Load:   dtoverlay=pifi-dac-zero\n+Params: <None>\n+\n+\n Name:   pifi-mini-210\n Info:   Configures the PiFi Mini stereo amplifier\n Load:   dtoverlay=pifi-mini-210\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/pifi-dac-hd-overlay.dts\n@@ -0,0 +1,49 @@\n+// Overlay for PiFi-DAC-HD\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&i2s>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&i2c1>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells =<0>;\n+\n+\t\t\tpcm5142: pcm5142@4c {\n+\t\t\t\t#sound-dai-cells = <0>;\n+\t\t\t\tcompatible = \"ti,pcm5142\";\n+\t\t\t\treg = <0x4c>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&sound>;\n+\t\t__overlay__ {\n+\t\t\tcompatible = \"simple-audio-card\";\n+\t\t\tsimple-audio-card,name = \"PiFi-DAC-HD\";\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tsimple-audio-card,dai-link@1 {\n+\t\t\t\tformat = \"i2s\";\n+\t\t\t\tcpu {\n+\t\t\t\t\tsound-dai = <&i2s>;\n+\t\t\t\t};\n+\t\t\t\tcodec {\n+\t\t\t\t\tsound-dai = <&pcm5142>;\n+\t\t\t\t};\n+\t\t\t};\n+\t\t};\n+\t};\n+};\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/pifi-dac-zero-overlay.dts\n@@ -0,0 +1,49 @@\n+// Overlay for PiFi-DAC-Zero\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&sound>;\n+\t\t__overlay__ {\n+\t\t\tcompatible = \"simple-audio-card\";\n+\t\t\tsimple-audio-card,name = \"PiFi-DAC-Zero\";\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tsimple-audio-card,dai-link@1 {\n+\t\t\t\tformat = \"i2s\";\n+\n+\t\t\t\tcpu {\n+\t\t\t\t\tsound-dai = <&i2s>;\n+\t\t\t\t\tdai-tdm-slot-num = <2>;\n+\t\t\t\t\tdai-tdm-slot-width = <32>;\n+\t\t\t\t};\n+\n+\t\t\t\tcodec {\n+\t\t\t\t\tsound-dai = <&codec_out>;\n+\t\t\t\t};\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget-path = \"/\";\n+\t\t__overlay__ {\n+\t\t\tcodec_out: pcm5102a-codec {\n+\t\t\t\t#sound-dai-cells = <0>;\n+\t\t\t\tcompatible = \"ti,pcm5102a\";\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&i2s>;\n+\t\t__overlay__ {\n+\t\t\t#sound-dai-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+};\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0489-media-i2c-imx477-Fix-crop-height-for-2028x1080-mode.patch",
    "content": "From 0444c9cf99e6dc1353b8bcfcd3580e3a4d91fb22 Mon Sep 17 00:00:00 2001\nFrom: Naushir Patuck <naush@raspberrypi.com>\nDate: Thu, 18 Feb 2021 15:05:57 +0000\nSubject: [PATCH] media: i2c: imx477: Fix crop height for 2028x1080\n mode\n\nThe crop height for this mode was set at 2600 lines, it should be 2160\nlines instead.\n\nSigned-off-by: Naushir Patuck <naush@raspberrypi.com>\n---\n drivers/media/i2c/imx477.c | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/drivers/media/i2c/imx477.c\n+++ b/drivers/media/i2c/imx477.c\n@@ -955,7 +955,7 @@ static const struct imx477_mode supporte\n \t\t\t.left = IMX477_PIXEL_ARRAY_LEFT,\n \t\t\t.top = IMX477_PIXEL_ARRAY_TOP + 440,\n \t\t\t.width = 4056,\n-\t\t\t.height = 2600,\n+\t\t\t.height = 2160,\n \t\t},\n \t\t.timeperframe_min = {\n \t\t\t.numerator = 100,\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0490-media-i2c-imx477-Replace-existing-1012x760-mode.patch",
    "content": "From f90f60490c5f5f944077a42b2394c0b51c393ce1 Mon Sep 17 00:00:00 2001\nFrom: Naushir Patuck <naush@raspberrypi.com>\nDate: Thu, 18 Feb 2021 15:23:11 +0000\nSubject: [PATCH] media: i2c: imx477: Replace existing 1012x760 mode\n\nThe existing 1012x760 120 fps mode has significant IQ problem using\nthe internal sensor scaler. Replace this mode with a 1332x990 120 fps\nmode instead. This new mode has a smaller field of view, but does not\nsuffer from the bad IQ of the original mode.\n\nSigned-off-by: Naushir Patuck <naush@raspberrypi.com>\n---\n drivers/media/i2c/imx477.c | 97 ++++++++++++++++++++------------------\n 1 file changed, 50 insertions(+), 47 deletions(-)\n\n--- a/drivers/media/i2c/imx477.c\n+++ b/drivers/media/i2c/imx477.c\n@@ -770,7 +770,7 @@ static const struct imx477_reg mode_2028\n };\n \n /* 4x4 binned. 120fps */\n-static const struct imx477_reg mode_1012x760_regs[] = {\n+static const struct imx477_reg mode_1332x990_regs[] = {\n \t{0x420b, 0x01},\n \t{0x990c, 0x00},\n \t{0x990d, 0x08},\n@@ -786,28 +786,31 @@ static const struct imx477_reg mode_1012\n \t{0x0112, 0x0a},\n \t{0x0113, 0x0a},\n \t{0x0114, 0x01},\n-\t{0x0342, 0x14},\n-\t{0x0343, 0x60},\n+\t{0x0342, 0x1a},\n+\t{0x0343, 0x08},\n+\t{0x0340, 0x04},\n+\t{0x0341, 0x1a},\n \t{0x0344, 0x00},\n \t{0x0345, 0x00},\n-\t{0x0346, 0x00},\n-\t{0x0347, 0x00},\n+\t{0x0346, 0x02},\n+\t{0x0347, 0x10},\n \t{0x0348, 0x0f},\n-\t{0x0349, 0xd3},\n-\t{0x034a, 0x0b},\n-\t{0x034b, 0xdf},\n+\t{0x0349, 0xd7},\n+\t{0x034a, 0x09},\n+\t{0x034b, 0xcf},\n \t{0x00e3, 0x00},\n \t{0x00e4, 0x00},\n \t{0x00fc, 0x0a},\n \t{0x00fd, 0x0a},\n \t{0x00fe, 0x0a},\n \t{0x00ff, 0x0a},\n+\t{0xe013, 0x00},\n \t{0x0220, 0x00},\n \t{0x0221, 0x11},\n \t{0x0381, 0x01},\n \t{0x0383, 0x01},\n \t{0x0385, 0x01},\n-\t{0x0387, 0x03},\n+\t{0x0387, 0x01},\n \t{0x0900, 0x01},\n \t{0x0901, 0x22},\n \t{0x0902, 0x02},\n@@ -831,29 +834,29 @@ static const struct imx477_reg mode_1012\n \t{0x936d, 0x5f},\n \t{0x9304, 0x03},\n \t{0x9305, 0x80},\n-\t{0x9e9a, 0x3f},\n-\t{0x9e9b, 0x3f},\n-\t{0x9e9c, 0x3f},\n-\t{0x9e9d, 0x27},\n-\t{0x9e9e, 0x27},\n-\t{0x9e9f, 0x27},\n+\t{0x9e9a, 0x2f},\n+\t{0x9e9b, 0x2f},\n+\t{0x9e9c, 0x2f},\n+\t{0x9e9d, 0x00},\n+\t{0x9e9e, 0x00},\n+\t{0x9e9f, 0x00},\n \t{0xa2a9, 0x27},\n \t{0xa2b7, 0x03},\n-\t{0x0401, 0x01},\n+\t{0x0401, 0x00},\n \t{0x0404, 0x00},\n-\t{0x0405, 0x20},\n-\t{0x0408, 0x00},\n-\t{0x0409, 0x00},\n+\t{0x0405, 0x10},\n+\t{0x0408, 0x01},\n+\t{0x0409, 0x5c},\n \t{0x040a, 0x00},\n \t{0x040b, 0x00},\n-\t{0x040c, 0x07},\n-\t{0x040d, 0xea},\n-\t{0x040e, 0x02},\n-\t{0x040f, 0xf8},\n-\t{0x034c, 0x03},\n-\t{0x034d, 0xf4},\n-\t{0x034e, 0x02},\n-\t{0x034f, 0xf8},\n+\t{0x040c, 0x05},\n+\t{0x040d, 0x34},\n+\t{0x040e, 0x03},\n+\t{0x040f, 0xde},\n+\t{0x034c, 0x05},\n+\t{0x034d, 0x34},\n+\t{0x034e, 0x03},\n+\t{0x034f, 0xde},\n \t{0x0301, 0x05},\n \t{0x0303, 0x02},\n \t{0x0305, 0x02},\n@@ -870,21 +873,21 @@ static const struct imx477_reg mode_1012\n \t{0x0822, 0x00},\n \t{0x0823, 0x00},\n \t{0x080a, 0x00},\n-\t{0x080b, 0x6f},\n+\t{0x080b, 0x7f},\n \t{0x080c, 0x00},\n-\t{0x080d, 0x3f},\n+\t{0x080d, 0x4f},\n \t{0x080e, 0x00},\n-\t{0x080f, 0xff},\n+\t{0x080f, 0x77},\n \t{0x0810, 0x00},\n-\t{0x0811, 0x4f},\n+\t{0x0811, 0x5f},\n \t{0x0812, 0x00},\n-\t{0x0813, 0x47},\n+\t{0x0813, 0x57},\n \t{0x0814, 0x00},\n-\t{0x0815, 0x37},\n-\t{0x0816, 0x00},\n-\t{0x0817, 0xe7},\n+\t{0x0815, 0x4f},\n+\t{0x0816, 0x01},\n+\t{0x0817, 0x27},\n \t{0x0818, 0x00},\n-\t{0x0819, 0x2f},\n+\t{0x0819, 0x3f},\n \t{0xe04c, 0x00},\n \t{0xe04d, 0x5f},\n \t{0xe04e, 0x00},\n@@ -893,7 +896,7 @@ static const struct imx477_reg mode_1012\n \t{0x3e37, 0x00},\n \t{0x3f50, 0x00},\n \t{0x3f56, 0x00},\n-\t{0x3f57, 0x96},\n+\t{0x3f57, 0xbf},\n };\n \n /* Mode configs */\n@@ -974,9 +977,9 @@ static const struct imx477_mode supporte\n \n static const struct imx477_mode supported_modes_10bit[] = {\n \t{\n-\t\t/* 720P 120fps. 4x4 binned */\n-\t\t.width = 1012,\n-\t\t.height = 760,\n+\t\t/* 120fps. 2x2 binned and cropped */\n+\t\t.width = 1332,\n+\t\t.height = 990,\n \t\t.line_length_pix = 0x1460,\n \t\t.crop = {\n \t\t\t/*\n@@ -987,10 +990,10 @@ static const struct imx477_mode supporte\n \t\t\t * rectangle once the driver is expanded to represent\n \t\t\t * its processing blocks with multiple subdevs.\n \t\t\t */\n-\t\t\t.left = IMX477_PIXEL_ARRAY_LEFT + 4,\n-\t\t\t.top = IMX477_PIXEL_ARRAY_TOP,\n-\t\t\t.width = 4052,\n-\t\t\t.height = 3040,\n+\t\t\t.left = IMX477_PIXEL_ARRAY_LEFT + 696,\n+\t\t\t.top = IMX477_PIXEL_ARRAY_TOP + 528,\n+\t\t\t.width = 2664,\n+\t\t\t.height = 1980,\n \t\t},\n \t\t.timeperframe_min = {\n \t\t\t.numerator = 100,\n@@ -998,11 +1001,11 @@ static const struct imx477_mode supporte\n \t\t},\n \t\t.timeperframe_default = {\n \t\t\t.numerator = 100,\n-\t\t\t.denominator = 60000\n+\t\t\t.denominator = 12000\n \t\t},\n \t\t.reg_list = {\n-\t\t\t.num_of_regs = ARRAY_SIZE(mode_1012x760_regs),\n-\t\t\t.regs = mode_1012x760_regs,\n+\t\t\t.num_of_regs = ARRAY_SIZE(mode_1332x990_regs),\n+\t\t\t.regs = mode_1332x990_regs,\n \t\t}\n \t}\n };\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0491-media-i2c-imx477-Remove-internal-v4l2_mbus_framefmt-.patch",
    "content": "From 013bd52fb83d145e90b8678c004ae1b32854d7f7 Mon Sep 17 00:00:00 2001\nFrom: Naushir Patuck <naush@raspberrypi.com>\nDate: Fri, 19 Feb 2021 10:30:49 +0000\nSubject: [PATCH] media: i2c: imx477: Remove internal\n v4l2_mbus_framefmt from the state\n\nThe only field in this struct that is used is the format code, so\nreplace the struct with this single field.\n\nSave the format code in imx477_set_pad_format() when setting up a new\nmode so that imx477_get_pad_format() performs the right lookup.\nOtherwise, this caused a bug where the mode lookup occurred on the\n12-bit table rather than the 10-bit table.\n\nSigned-off-by: Naushir Patuck <naush@raspberrypi.com>\n---\n drivers/media/i2c/imx477.c | 19 ++++---------------\n 1 file changed, 4 insertions(+), 15 deletions(-)\n\n--- a/drivers/media/i2c/imx477.c\n+++ b/drivers/media/i2c/imx477.c\n@@ -1073,7 +1073,7 @@ struct imx477 {\n \tstruct v4l2_subdev sd;\n \tstruct media_pad pad[NUM_PADS];\n \n-\tstruct v4l2_mbus_framefmt fmt;\n+\tunsigned int fmt_code;\n \n \tstruct clk *xclk;\n \tu32 xclk_freq;\n@@ -1235,21 +1235,9 @@ static u32 imx477_get_format_code(struct\n \n static void imx477_set_default_format(struct imx477 *imx477)\n {\n-\tstruct v4l2_mbus_framefmt *fmt = &imx477->fmt;\n-\n \t/* Set default mode to max resolution */\n \timx477->mode = &supported_modes_12bit[0];\n-\n-\tfmt->code = MEDIA_BUS_FMT_SRGGB12_1X12;\n-\tfmt->colorspace = V4L2_COLORSPACE_SRGB;\n-\tfmt->ycbcr_enc = V4L2_MAP_YCBCR_ENC_DEFAULT(fmt->colorspace);\n-\tfmt->quantization = V4L2_MAP_QUANTIZATION_DEFAULT(true,\n-\t\t\t\t\t\t\t  fmt->colorspace,\n-\t\t\t\t\t\t\t  fmt->ycbcr_enc);\n-\tfmt->xfer_func = V4L2_MAP_XFER_FUNC_DEFAULT(fmt->colorspace);\n-\tfmt->width = imx477->mode->width;\n-\tfmt->height = imx477->mode->height;\n-\tfmt->field = V4L2_FIELD_NONE;\n+\timx477->fmt_code = MEDIA_BUS_FMT_SRGGB12_1X12;\n }\n \n static int imx477_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)\n@@ -1520,7 +1508,7 @@ static int imx477_get_pad_format(struct\n \t\t\timx477_update_image_pad_format(imx477, imx477->mode,\n \t\t\t\t\t\t       fmt);\n \t\t\tfmt->format.code =\n-\t\t\t       imx477_get_format_code(imx477, imx477->fmt.code);\n+\t\t\t       imx477_get_format_code(imx477, imx477->fmt_code);\n \t\t} else {\n \t\t\timx477_update_metadata_pad_format(fmt);\n \t\t}\n@@ -1611,6 +1599,7 @@ static int imx477_set_pad_format(struct\n \t\t\t*framefmt = fmt->format;\n \t\t} else {\n \t\t\timx477->mode = mode;\n+\t\t\timx477->fmt_code = fmt->format.code;\n \t\t\timx477_set_framing_limits(imx477);\n \t\t}\n \t} else {\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0492-media-i2c-imx477-Remove-unused-function-parameter.patch",
    "content": "From 208c3db346fe64ed5e270350920aad5bc5425a14 Mon Sep 17 00:00:00 2001\nFrom: Naushir Patuck <naush@raspberrypi.com>\nDate: Fri, 19 Feb 2021 11:06:40 +0000\nSubject: [PATCH] media: i2c: imx477: Remove unused function parameter\n\nThe struct imx477 *ctrl parameter is not used in the function\nimx477_adjust_exposure_range(), so remove it.\n\nSigned-off-by: Naushir Patuck <naush@raspberrypi.com>\n---\n drivers/media/i2c/imx477.c | 5 ++---\n 1 file changed, 2 insertions(+), 3 deletions(-)\n\n--- a/drivers/media/i2c/imx477.c\n+++ b/drivers/media/i2c/imx477.c\n@@ -1276,8 +1276,7 @@ static int imx477_open(struct v4l2_subde\n \treturn 0;\n }\n \n-static void imx477_adjust_exposure_range(struct imx477 *imx477,\n-\t\t\t\t\t struct v4l2_ctrl *ctrl)\n+static void imx477_adjust_exposure_range(struct imx477 *imx477)\n {\n \tint exposure_max, exposure_def;\n \n@@ -1322,7 +1321,7 @@ static int imx477_set_ctrl(struct v4l2_c\n \t * and adjust if necessary.\n \t */\n \tif (ctrl->id == V4L2_CID_VBLANK)\n-\t\timx477_adjust_exposure_range(imx477, ctrl);\n+\t\timx477_adjust_exposure_range(imx477);\n \n \t/*\n \t * Applying V4L2 control value only happens\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0493-overlays-i2c-rtc-Add-the-Dallas-DS1340.patch",
    "content": "From fd478b369992e56665de3aabf0e19e24b5fa5e43 Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.com>\nDate: Fri, 26 Feb 2021 14:19:00 +0000\nSubject: [PATCH] overlays: i2c-rtc: Add the Dallas DS1340\n\nSee: https://github.com/raspberrypi/linux/issues/4180\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.com>\n---\n arch/arm/boot/dts/overlays/README              |  2 ++\n arch/arm/boot/dts/overlays/i2c-rtc-overlay.dts | 16 ++++++++++++++++\n 2 files changed, 18 insertions(+)\n\n--- a/arch/arm/boot/dts/overlays/README\n+++ b/arch/arm/boot/dts/overlays/README\n@@ -1311,6 +1311,8 @@ Params: abx80x                  Select o\n \n         ds1339                  Select the DS1339 device\n \n+        ds1340                  Select the DS1340 device\n+\n         ds3231                  Select the DS3231 device\n \n         m41t62                  Select the M41T62 device\n--- a/arch/arm/boot/dts/overlays/i2c-rtc-overlay.dts\n+++ b/arch/arm/boot/dts/overlays/i2c-rtc-overlay.dts\n@@ -231,6 +231,20 @@\n \t\t};\n \t};\n \n+\tfragment@17 {\n+\t\ttarget = <&i2cbus>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tds1340: ds1340@68 {\n+\t\t\t\tcompatible = \"dallas,ds1340\";\n+\t\t\t\ttrickle-resistor-ohms = <0>;\n+\t\t\t\treg = <0x68>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n \tfrag100: fragment@100 {\n \t\ttarget = <&i2c_arm>;\n \t\ti2cbus: __overlay__ {\n@@ -242,6 +256,7 @@\n \t\tabx80x = <0>,\"+0\";\n \t\tds1307 = <0>,\"+1\";\n \t\tds1339 = <0>,\"+2\";\n+\t\tds1340 = <0>,\"+17\";\n \t\tds3231 = <0>,\"+3\";\n \t\tmcp7940x = <0>,\"+4\";\n \t\tmcp7941x = <0>,\"+5\";\n@@ -273,6 +288,7 @@\n \t\ttrickle-diode-type = <&abx80x>,\"abracon,tc-diode\",\n \t\t\t\t     <&rv1805>,\"abracon,tc-diode\";\n \t\ttrickle-resistor-ohms = <&ds1339>,\"trickle-resistor-ohms:0\",\n+\t\t\t\t\t<&ds1340>,\"trickle-resistor-ohms:0\",\n \t\t\t\t\t<&abx80x>,\"abracon,tc-resistor:0\",\n \t\t\t\t\t<&rv3028>,\"trickle-resistor-ohms:0\",\n \t\t\t\t\t<&rv1805>,\"abracon,tc-resistor:0\";\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0494-overlays-Update-the-upstream-overlay.patch",
    "content": "From 6108bbb3c19fcba6b4b108efaefbc88cc8e1ba3e Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.com>\nDate: Fri, 26 Feb 2021 14:20:05 +0000\nSubject: [PATCH] overlays: Update the upstream overlay\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.com>\n---\n arch/arm/boot/dts/overlays/upstream-pi4-overlay.dts | 6 ++++++\n 1 file changed, 6 insertions(+)\n\n--- a/arch/arm/boot/dts/overlays/upstream-pi4-overlay.dts\n+++ b/arch/arm/boot/dts/overlays/upstream-pi4-overlay.dts\n@@ -116,6 +116,12 @@\n \t\t};\n \t};\n \tfragment@18 {\n+\t\ttarget = <&aon_intr>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\tfragment@19 {\n \t\ttarget = <&usb>;\n \t\t#address-cells = <1>;\n \t\t#size-cells = <1>;\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0495-Revert-Bluetooth-Always-request-for-user-confirmatio.patch",
    "content": "From 637d132b72c9208e086b71fbf39954cff3fb851c Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.com>\nDate: Mon, 1 Mar 2021 09:12:44 +0000\nSubject: [PATCH] Revert \"Bluetooth: Always request for user\n confirmation for Just Works (LE SC)\"\n\nThis reverts commit ffee202a78c2980688bc5d2f7d56480e69a5e0c9.\n\nThe commit \"Bluetooth: Always request for user confirmation for Just\nWorks\" prevents BLE devices pairing in (at least) the Raspberry Pi OS\nGUI. After reverting it, pairing works again. Although this companion\ncommit (\"... (LE SC)\") has not been demonstrated to be problematic,\nit follows the same logic and therefore could affect some use cases.\n\nIf another solution to the problem is found then this reversion will\nbe removed.\n\nSee: https://github.com/raspberrypi/linux/issues/4139\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.com>\n---\n net/bluetooth/smp.c | 5 +----\n 1 file changed, 1 insertion(+), 4 deletions(-)\n\n--- a/net/bluetooth/smp.c\n+++ b/net/bluetooth/smp.c\n@@ -2201,7 +2201,7 @@ mackey_and_ltk:\n \tif (err)\n \t\treturn SMP_UNSPECIFIED;\n \n-\tif (smp->method == REQ_OOB) {\n+\tif (smp->method == JUST_WORKS || smp->method == REQ_OOB) {\n \t\tif (hcon->out) {\n \t\t\tsc_dhkey_check(smp);\n \t\t\tSMP_ALLOW_CMD(smp, SMP_CMD_DHKEY_CHECK);\n@@ -2216,9 +2216,6 @@ mackey_and_ltk:\n \tconfirm_hint = 0;\n \n confirm:\n-\tif (smp->method == JUST_WORKS)\n-\t\tconfirm_hint = 1;\n-\n \terr = mgmt_user_confirm_request(hcon->hdev, &hcon->dst, hcon->type,\n \t\t\t\t\thcon->dst_type, passkey, confirm_hint);\n \tif (err)\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0496-Revert-Bluetooth-Always-request-for-user-confirmatio.patch",
    "content": "From e067981f7f882c787df637561fde847f197e9e00 Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.com>\nDate: Mon, 1 Mar 2021 09:14:35 +0000\nSubject: [PATCH] Revert \"Bluetooth: Always request for user\n confirmation for Just Works\"\n\nThis reverts commit 92516cd97fd4d8ad5b1421a0d51771044f453a5f.\n\nThi commit \"Bluetooth: Always request for user confirmation for Just\nWorks\" prevents BLE devices pairing in (at least) the Raspberry Pi OS\nGUI. After reverting it, pairing works again.\n\nIf another solution to the problem is found then this reversion will\nbe removed.\n\nSee: https://github.com/raspberrypi/linux/issues/4139\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.com>\n---\n net/bluetooth/smp.c | 11 ++---------\n 1 file changed, 2 insertions(+), 9 deletions(-)\n\n--- a/net/bluetooth/smp.c\n+++ b/net/bluetooth/smp.c\n@@ -883,16 +883,9 @@ static int tk_request(struct l2cap_conn\n \t    hcon->io_capability == HCI_IO_NO_INPUT_OUTPUT)\n \t\tsmp->method = JUST_WORKS;\n \n-\t/* If Just Works, Continue with Zero TK and ask user-space for\n-\t * confirmation */\n+\t/* If Just Works, Continue with Zero TK */\n \tif (smp->method == JUST_WORKS) {\n-\t\tret = mgmt_user_confirm_request(hcon->hdev, &hcon->dst,\n-\t\t\t\t\t\thcon->type,\n-\t\t\t\t\t\thcon->dst_type,\n-\t\t\t\t\t\tpasskey, 1);\n-\t\tif (ret)\n-\t\t\treturn ret;\n-\t\tset_bit(SMP_FLAG_WAIT_USER, &smp->flags);\n+\t\tset_bit(SMP_FLAG_TK_VALID, &smp->flags);\n \t\treturn 0;\n \t}\n \n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0497-media-bcm2835-unicam-Fix-bug-in-buffer-swapping-logi.patch",
    "content": "From 8740c5d8ab750b3e12f7f081082e2ae8c22ab6db Mon Sep 17 00:00:00 2001\nFrom: Naushir Patuck <naush@raspberrypi.com>\nDate: Fri, 5 Mar 2021 15:40:45 +0000\nSubject: [PATCH] media: bcm2835-unicam: Fix bug in buffer swapping\n logic\n\nIf multiple sets of interrupts occur simultaneously, it may be unsafe\nto swap buffers, as the hardware may already be re-using the current\nbuffers. In such cases, avoid swapping buffers, and wait for the next\nopportunity at the Frame End interrupt to signal completion.\n\nAdditionally, check the packet compare status when watching for frame\nend for buffers swaps, as this could also signify a frame end event.\n\nSigned-off-by: Naushir Patuck <naush@raspberrypi.com>\n---\n .../media/platform/bcm2835/bcm2835-unicam.c   | 21 ++++++++++++++++---\n 1 file changed, 18 insertions(+), 3 deletions(-)\n\n--- a/drivers/media/platform/bcm2835/bcm2835-unicam.c\n+++ b/drivers/media/platform/bcm2835/bcm2835-unicam.c\n@@ -798,6 +798,7 @@ static irqreturn_t unicam_isr(int irq, v\n \tunsigned int sequence = unicam->sequence;\n \tunsigned int i;\n \tu32 ista, sta;\n+\tbool fe;\n \tu64 ts;\n \n \tsta = reg_read(unicam, UNICAM_STA);\n@@ -815,12 +816,18 @@ static irqreturn_t unicam_isr(int irq, v\n \t\treturn IRQ_HANDLED;\n \n \t/*\n+\t * Look for either the Frame End interrupt or the Packet Capture status\n+\t * to signal a frame end.\n+\t */\n+\tfe = (ista & UNICAM_FEI || sta & UNICAM_PI0);\n+\n+\t/*\n \t * We must run the frame end handler first. If we have a valid next_frm\n \t * and we get a simultaneout FE + FS interrupt, running the FS handler\n \t * first would null out the next_frm ptr and we would have lost the\n \t * buffer forever.\n \t */\n-\tif (ista & UNICAM_FEI || sta & UNICAM_PI0) {\n+\tif (fe) {\n \t\t/*\n \t\t * Ensure we have swapped buffers already as we can't\n \t\t * stop the peripheral. If no buffer is available, use a\n@@ -831,7 +838,15 @@ static irqreturn_t unicam_isr(int irq, v\n \t\t\tif (!unicam->node[i].streaming)\n \t\t\t\tcontinue;\n \n-\t\t\tif (unicam->node[i].cur_frm)\n+\t\t\t/*\n+\t\t\t * If cur_frm == next_frm, it means we have not had\n+\t\t\t * a chance to swap buffers, likely due to having\n+\t\t\t * multiple interrupts occurring simultaneously (like FE\n+\t\t\t * + FS + LS). In this case, we cannot signal the buffer\n+\t\t\t * as complete, as the HW will reuse that buffer.\n+\t\t\t */\n+\t\t\tif (unicam->node[i].cur_frm &&\n+\t\t\t    unicam->node[i].cur_frm != unicam->node[i].next_frm)\n \t\t\t\tunicam_process_buffer_complete(&unicam->node[i],\n \t\t\t\t\t\t\t       sequence);\n \t\t\tunicam->node[i].cur_frm = unicam->node[i].next_frm;\n@@ -868,7 +883,7 @@ static irqreturn_t unicam_isr(int irq, v\n \t * where the HW does not actually swap it if the new frame has\n \t * already started.\n \t */\n-\tif (ista & (UNICAM_FSI | UNICAM_LCI) && !(ista & UNICAM_FEI)) {\n+\tif (ista & (UNICAM_FSI | UNICAM_LCI) && !fe) {\n \t\tfor (i = 0; i < ARRAY_SIZE(unicam->node); i++) {\n \t\t\tif (!unicam->node[i].streaming)\n \t\t\t\tcontinue;\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0498-Assign-crypto-aliases-to-different-AES-implementatio.patch",
    "content": "From 6d99147c19566e0f82eccef876f5aae2bc8d1fcb Mon Sep 17 00:00:00 2001\nFrom: Ben Avison <bavison@riscosopen.org>\nDate: Mon, 8 Mar 2021 15:32:25 +0000\nSubject: [PATCH] Assign crypto aliases to different AES implementation\n modules\n\nThe kernel modules aes-neon-blk and aes-neon-bs perform poorly, at least on\nCortex-A72 without crypto extensions. In fact, aes-arm64 outperforms them\non benchmarks, despite it being a simpler implementation (only accelerating\nthe single-block AES cipher).\n\nFor modes of operation where multiple cipher blocks can be processed in\nparallel, aes-neon-bs outperforms aes-neon-blk by around 60-70% and aes-arm64\nis another 10-20% faster still. But the difference is even more marked with\nmodes of operation with dependencies between neighbouring blocks, such as\nCBC encryption, which defeat parallelism: in these cases, aes-arm64 is\ntypically around 250% faster than either aes-neon-blk or aes-neon-bs.\n\nThe key trade-off with aes-arm64 is that the look-up tables are situated in\nRAM. This leaves them potentially open to cache timing attacks. The two other\nmodules, by contrast, load the look-up tables into NEON registers and so are\nable to perform in constant time.\n\nThis patch aims to load aes-arm64 more often.\n\nIf none of the currently-loaded crypto modules implement a given algorithm,\na new one is typically selected for loading using a platform-neutral alias\ndescribing the required algorithm. To enable users to still\nload aes-neon-blk or aes-neon-bs if they really want them, while still\nensuring that aes-arm64 is usually selected, remove the aliases from\naes-neonbs-glue.c and aes-glue.c and apply them to aes-cipher-glue.c, but\nstill build the two NEON modules.\n\nSince aes-glue.c can also be used to build aes-ce-blk, leave them enabled\nif USE_V8_CRYPTO_EXTENSIONS is defined, to ensure they are selected if we\nin future use a CPU which has the crypto extensions enabled.\n\nNote that the algorithm priority specifiers are unchanged, so if\naes-neon-bs is loaded at the same time as aes-arm64, the former will be\nused in preference. However, aes-neon-blk and aes-arm64 have tied priority,\nso whichever module was loaded first will be used (assuming aes-neon-bs is\nnot loaded).\n\nSigned-off-by: Ben Avison <bavison@riscosopen.org>\n---\n arch/arm64/crypto/aes-cipher-glue.c | 10 ++++++++++\n arch/arm64/crypto/aes-glue.c        |  4 ++--\n arch/arm64/crypto/aes-neonbs-glue.c |  5 -----\n 3 files changed, 12 insertions(+), 7 deletions(-)\n\n--- a/arch/arm64/crypto/aes-cipher-glue.c\n+++ b/arch/arm64/crypto/aes-cipher-glue.c\n@@ -9,6 +9,16 @@\n #include <linux/crypto.h>\n #include <linux/module.h>\n \n+MODULE_ALIAS_CRYPTO(\"ecb(aes)\");\n+MODULE_ALIAS_CRYPTO(\"cbc(aes)\");\n+MODULE_ALIAS_CRYPTO(\"ctr(aes)\");\n+MODULE_ALIAS_CRYPTO(\"xts(aes)\");\n+MODULE_ALIAS_CRYPTO(\"cts(cbc(aes))\");\n+MODULE_ALIAS_CRYPTO(\"essiv(cbc(aes),sha256)\");\n+MODULE_ALIAS_CRYPTO(\"cmac(aes)\");\n+MODULE_ALIAS_CRYPTO(\"xcbc(aes)\");\n+MODULE_ALIAS_CRYPTO(\"cbcmac(aes)\");\n+\n asmlinkage void __aes_arm64_encrypt(u32 *rk, u8 *out, const u8 *in, int rounds);\n asmlinkage void __aes_arm64_decrypt(u32 *rk, u8 *out, const u8 *in, int rounds);\n \n--- a/arch/arm64/crypto/aes-glue.c\n+++ b/arch/arm64/crypto/aes-glue.c\n@@ -55,17 +55,17 @@ MODULE_DESCRIPTION(\"AES-ECB/CBC/CTR/XTS\n #define aes_mac_update\t\tneon_aes_mac_update\n MODULE_DESCRIPTION(\"AES-ECB/CBC/CTR/XTS using ARMv8 NEON\");\n #endif\n-#if defined(USE_V8_CRYPTO_EXTENSIONS) || !IS_ENABLED(CONFIG_CRYPTO_AES_ARM64_BS)\n+#if defined(USE_V8_CRYPTO_EXTENSIONS)\n MODULE_ALIAS_CRYPTO(\"ecb(aes)\");\n MODULE_ALIAS_CRYPTO(\"cbc(aes)\");\n MODULE_ALIAS_CRYPTO(\"ctr(aes)\");\n MODULE_ALIAS_CRYPTO(\"xts(aes)\");\n-#endif\n MODULE_ALIAS_CRYPTO(\"cts(cbc(aes))\");\n MODULE_ALIAS_CRYPTO(\"essiv(cbc(aes),sha256)\");\n MODULE_ALIAS_CRYPTO(\"cmac(aes)\");\n MODULE_ALIAS_CRYPTO(\"xcbc(aes)\");\n MODULE_ALIAS_CRYPTO(\"cbcmac(aes)\");\n+#endif\n \n MODULE_AUTHOR(\"Ard Biesheuvel <ard.biesheuvel@linaro.org>\");\n MODULE_LICENSE(\"GPL v2\");\n--- a/arch/arm64/crypto/aes-neonbs-glue.c\n+++ b/arch/arm64/crypto/aes-neonbs-glue.c\n@@ -18,11 +18,6 @@\n MODULE_AUTHOR(\"Ard Biesheuvel <ard.biesheuvel@linaro.org>\");\n MODULE_LICENSE(\"GPL v2\");\n \n-MODULE_ALIAS_CRYPTO(\"ecb(aes)\");\n-MODULE_ALIAS_CRYPTO(\"cbc(aes)\");\n-MODULE_ALIAS_CRYPTO(\"ctr(aes)\");\n-MODULE_ALIAS_CRYPTO(\"xts(aes)\");\n-\n asmlinkage void aesbs_convert_key(u8 out[], u32 const rk[], int rounds);\n \n asmlinkage void aesbs_ecb_encrypt(u8 out[], u8 const in[], u8 const rk[],\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0499-overlays-Improve-the-i2c-rtc-i2c_csi_dsi-option.patch",
    "content": "From 7792f64f6d4fbd67ed99e63ad7e828430adb6bac Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.com>\nDate: Thu, 11 Mar 2021 16:11:46 +0000\nSubject: [PATCH] overlays: Improve the i2c-rtc,i2c_csi_dsi option\n\nThe i2c_csi_dsi parameter of the i2c-rtc overlay (added for the CM4IO\nboard) causes the RTC devices to be probed on the I2C0 bus appearing\non GPIOs 44 and 45. However, it didn't enable the other nodes necessary\nfor it to work - \"dtparam=i2c_vc=on\" was also required.\n\nFix that.\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.com>\n---\n arch/arm/boot/dts/overlays/i2c-rtc-overlay.dts | 17 ++++++++++++++++-\n 1 file changed, 16 insertions(+), 1 deletion(-)\n\n--- a/arch/arm/boot/dts/overlays/i2c-rtc-overlay.dts\n+++ b/arch/arm/boot/dts/overlays/i2c-rtc-overlay.dts\n@@ -252,6 +252,20 @@\n \t\t};\n \t};\n \n+\tfragment@101 {\n+\t\ttarget = <&i2c0if>;\n+\t\t__dormant__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@102 {\n+\t\ttarget = <&i2c0mux>;\n+\t\t__dormant__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n \t__overrides__ {\n \t\tabx80x = <0>,\"+0\";\n \t\tds1307 = <0>,\"+1\";\n@@ -273,7 +287,8 @@\n \t\tpcf85063a = <0>,\"+16\";\n \n \t\ti2c0 = <&frag100>, \"target:0=\",<&i2c0>;\n-\t\ti2c_csi_dsi = <&frag100>, \"target:0=\",<&i2c_csi_dsi>;\n+\t\ti2c_csi_dsi = <&frag100>, \"target:0=\",<&i2c_csi_dsi>,\n+\t\t\t      <0>,\"+101+102\";\n \n \t\taddr = <&abx80x>, \"reg:0\",\n \t\t       <&ds1307>, \"reg:0\",\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0500-media-v4l2_m2m-In-buffered-mode-run-jobs-if-either-p.patch",
    "content": "From f9ab3e8acbbd27e81a232aa671838ace4263d46a Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Mon, 1 Feb 2021 18:48:47 +0000\nSubject: [PATCH] media/v4l2_m2m: In buffered mode run jobs if either\n port is streaming\n\nIn order to get the intended behaviour of the stateful video\ndecoder API where only the OUTPUT queue needs to be enabled and fed\nbuffers in order to get the SOURCE_CHANGED event that configures the\nCAPTURE queue, we want the device to run should either queue be\nstreaming.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n drivers/media/v4l2-core/v4l2-mem2mem.c | 7 ++++---\n 1 file changed, 4 insertions(+), 3 deletions(-)\n\n--- a/drivers/media/v4l2-core/v4l2-mem2mem.c\n+++ b/drivers/media/v4l2-core/v4l2-mem2mem.c\n@@ -301,9 +301,10 @@ static void __v4l2_m2m_try_queue(struct\n \n \tdprintk(\"Trying to schedule a job for m2m_ctx: %p\\n\", m2m_ctx);\n \n-\tif (!m2m_ctx->out_q_ctx.q.streaming\n-\t    || !m2m_ctx->cap_q_ctx.q.streaming) {\n-\t\tdprintk(\"Streaming needs to be on for both queues\\n\");\n+\tif (!(m2m_ctx->out_q_ctx.q.streaming &&\n+\t      m2m_ctx->cap_q_ctx.q.streaming) &&\n+\t    !(m2m_ctx->out_q_ctx.buffered && m2m_ctx->out_q_ctx.q.streaming)) {\n+\t\tdprintk(\"Streaming needs to be on for both queues, or buffered and OUTPUT streaming\\n\");\n \t\treturn;\n \t}\n \n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0501-staging-bcm2835-codec-Correct-logging-of-size_t-to-z.patch",
    "content": "From c3da01fd97044bb1a48bd9146d15b374d4c1ce55 Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Mon, 1 Feb 2021 18:55:37 +0000\nSubject: [PATCH] staging/bcm2835-codec: Correct logging of size_t to\n %zu\n\nFixes: \"staging/bcm2835-codec: Log the number of excess supported formats\"\nWhich used %u for printing a size_t, and 64bit builds then log a warning.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n .../staging/vc04_services/bcm2835-codec/bcm2835-v4l2-codec.c  | 4 ++--\n 1 file changed, 2 insertions(+), 2 deletions(-)\n\n--- a/drivers/staging/vc04_services/bcm2835-codec/bcm2835-v4l2-codec.c\n+++ b/drivers/staging/vc04_services/bcm2835-codec/bcm2835-v4l2-codec.c\n@@ -2837,7 +2837,7 @@ static int bcm2835_codec_get_supported_f\n \tif (ret) {\n \t\tif (ret == MMAL_MSG_STATUS_ENOSPC) {\n \t\t\tv4l2_err(&dev->v4l2_dev,\n-\t\t\t\t \"%s: port has more encodings than we provided space for. Some are dropped (%u vs %u).\\n\",\n+\t\t\t\t \"%s: port has more encodings than we provided space for. Some are dropped (%zu vs %u).\\n\",\n \t\t\t\t __func__, param_size / sizeof(u32),\n \t\t\t\t MAX_SUPPORTED_ENCODINGS);\n \t\t\tnum_encodings = MAX_SUPPORTED_ENCODINGS;\n@@ -2883,7 +2883,7 @@ static int bcm2835_codec_get_supported_f\n \tif (ret) {\n \t\tif (ret == MMAL_MSG_STATUS_ENOSPC) {\n \t\t\tv4l2_err(&dev->v4l2_dev,\n-\t\t\t\t \"%s: port has more encodings than we provided space for. Some are dropped (%u vs %u).\\n\",\n+\t\t\t\t \"%s: port has more encodings than we provided space for. Some are dropped (%zu vs %u).\\n\",\n \t\t\t\t __func__, param_size / sizeof(u32),\n \t\t\t\t MAX_SUPPORTED_ENCODINGS);\n \t\t\tnum_encodings = MAX_SUPPORTED_ENCODINGS;\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0502-staging-bcm2835-codec-Add-support-for-pixel-aspect-r.patch",
    "content": "From 5a1f76940af2691627837bb4f181a672abfaffa2 Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Tue, 2 Feb 2021 15:50:18 +0000\nSubject: [PATCH] staging/bcm2835-codec: Add support for pixel aspect\n ratio\n\nIf the format is detected by the driver and a V4L2_EVENT_SOURCE_CHANGE\nevent is generated, then pass on the pixel aspect ratio as well.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n .../bcm2835-codec/bcm2835-v4l2-codec.c        | 31 +++++++++++++++++++\n 1 file changed, 31 insertions(+)\n\n--- a/drivers/staging/vc04_services/bcm2835-codec/bcm2835-v4l2-codec.c\n+++ b/drivers/staging/vc04_services/bcm2835-codec/bcm2835-v4l2-codec.c\n@@ -602,6 +602,7 @@ struct bcm2835_codec_q_data {\n \tunsigned int\t\tcrop_width;\n \tunsigned int\t\tcrop_height;\n \tbool\t\t\tselection_set;\n+\tstruct v4l2_fract\taspect_ratio;\n \n \tunsigned int\t\tsizeimage;\n \tunsigned int\t\tsequence;\n@@ -981,6 +982,9 @@ static void handle_fmt_changed(struct bc\n \tif (format->es.video.color_space)\n \t\tcolor_mmal2v4l(ctx, format->es.video.color_space);\n \n+\tq_data->aspect_ratio.numerator = format->es.video.par.num;\n+\tq_data->aspect_ratio.denominator = format->es.video.par.den;\n+\n \tqueue_res_chg_event(ctx);\n }\n \n@@ -1657,6 +1661,29 @@ static int vidioc_g_parm(struct file *fi\n \treturn 0;\n }\n \n+static int vidioc_g_pixelaspect(struct file *file, void *fh, int type,\n+\t\t\t\tstruct v4l2_fract *f)\n+{\n+\tstruct bcm2835_codec_ctx *ctx = file2ctx(file);\n+\n+\t/*\n+\t * The selection API takes V4L2_BUF_TYPE_VIDEO_CAPTURE and\n+\t * V4L2_BUF_TYPE_VIDEO_OUTPUT, even if the device implements the MPLANE\n+\t * API. The V4L2 core will have converted the MPLANE variants to\n+\t * non-MPLANE.\n+\t * Open code this instead of using get_q_data in this case.\n+\t */\n+\tif (ctx->dev->role != DECODE)\n+\t\treturn -ENOIOCTLCMD;\n+\n+\tif (type != V4L2_BUF_TYPE_VIDEO_CAPTURE)\n+\t\treturn -EINVAL;\n+\n+\t*f = ctx->q_data[V4L2_M2M_DST].aspect_ratio;\n+\n+\treturn 0;\n+}\n+\n static int vidioc_subscribe_evt(struct v4l2_fh *fh,\n \t\t\t\tconst struct v4l2_event_subscription *sub)\n {\n@@ -2082,6 +2109,8 @@ static const struct v4l2_ioctl_ops bcm28\n \t.vidioc_g_parm\t\t= vidioc_g_parm,\n \t.vidioc_s_parm\t\t= vidioc_s_parm,\n \n+\t.vidioc_g_pixelaspect\t= vidioc_g_pixelaspect,\n+\n \t.vidioc_subscribe_event = vidioc_subscribe_evt,\n \t.vidioc_unsubscribe_event = v4l2_event_unsubscribe,\n \n@@ -2640,6 +2669,8 @@ static int bcm2835_codec_open(struct fil\n \t\t\t      ctx->q_data[V4L2_M2M_DST].crop_width,\n \t\t\t      ctx->q_data[V4L2_M2M_DST].height,\n \t\t\t      ctx->q_data[V4L2_M2M_DST].fmt);\n+\tctx->q_data[V4L2_M2M_DST].aspect_ratio.numerator = 1;\n+\tctx->q_data[V4L2_M2M_DST].aspect_ratio.denominator = 1;\n \n \tctx->colorspace = V4L2_COLORSPACE_REC709;\n \tctx->bitrate = 10 * 1000 * 1000;\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0503-staging-bcm2835-codec-Implement-additional-g_selecti.patch",
    "content": "From ba936c1969753c11ed4f903d007f7e6a9e2d8abb Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Tue, 2 Feb 2021 16:46:39 +0000\nSubject: [PATCH] staging/bcm2835-codec: Implement additional\n g_selection calls for decode\n\nv4l_cropcap calls our vidioc_g_pixelaspect function to get the pixel\naspect ratio, but also calls g_selection for V4L2_SEL_TGT_CROP_BOUNDS\nand V4L2_SEL_TGT_CROP_DEFAULT. Whilst it allows for vidioc_g_pixelaspect\nnot to be implemented, it doesn't allow for either of the other two.\n\nAdd in support for the additional selection targets.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n .../vc04_services/bcm2835-codec/bcm2835-v4l2-codec.c      | 8 ++++++++\n 1 file changed, 8 insertions(+)\n\n--- a/drivers/staging/vc04_services/bcm2835-codec/bcm2835-v4l2-codec.c\n+++ b/drivers/staging/vc04_services/bcm2835-codec/bcm2835-v4l2-codec.c\n@@ -1517,6 +1517,14 @@ static int vidioc_g_selection(struct fil\n \t\t\ts->r.width = q_data->crop_width;\n \t\t\ts->r.height = q_data->crop_height;\n \t\t\tbreak;\n+\t\tcase V4L2_SEL_TGT_CROP_BOUNDS:\n+\t\tcase V4L2_SEL_TGT_CROP_DEFAULT:\n+\t\t\ts->r.left = 0;\n+\t\t\ts->r.top = 0;\n+\t\t\ts->r.width = (q_data->bytesperline << 3) /\n+\t\t\t\t\t\tq_data->fmt->depth;\n+\t\t\ts->r.height = q_data->height;\n+\t\t\tbreak;\n \t\tdefault:\n \t\t\treturn -EINVAL;\n \t\t}\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0504-staging-bcm2835-codec-Add-VC-1-support.patch",
    "content": "From 11bf5a8b401bbc34ace1acd8be9ed4099d95d0b1 Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Wed, 10 Mar 2021 19:07:48 +0000\nSubject: [PATCH] staging/bcm2835-codec: Add VC-1 support.\n\nProviding the relevant licence has been purchased, then Pi0-3\ncan decode VC-1.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n .../vc04_services/bcm2835-codec/bcm2835-v4l2-codec.c       | 7 ++++++-\n 1 file changed, 6 insertions(+), 1 deletion(-)\n\n--- a/drivers/staging/vc04_services/bcm2835-codec/bcm2835-v4l2-codec.c\n+++ b/drivers/staging/vc04_services/bcm2835-codec/bcm2835-v4l2-codec.c\n@@ -576,7 +576,12 @@ static const struct bcm2835_codec_fmt su\n \t\t.depth\t\t\t= 0,\n \t\t.flags\t\t\t= V4L2_FMT_FLAG_COMPRESSED,\n \t\t.mmal_fmt\t\t= MMAL_ENCODING_VP8,\n-\t},\n+\t}, {\n+\t\t.fourcc\t\t\t= V4L2_PIX_FMT_VC1_ANNEX_G,\n+\t\t.depth\t\t\t= 0,\n+\t\t.flags\t\t\t= V4L2_FMT_FLAG_COMPRESSED,\n+\t\t.mmal_fmt\t\t= MMAL_ENCODING_WVC1,\n+\t}\n };\n \n struct bcm2835_codec_fmt_list {\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0505-vc4-drm-Avoid-full-hdmi-audio-fifo-writes.patch",
    "content": "From d0df79e13ab947367b86d7861e34f85aa6aad020 Mon Sep 17 00:00:00 2001\nFrom: Dom Cobley <popcornmix@gmail.com>\nDate: Sun, 24 Jan 2021 15:44:10 +0000\nSubject: [PATCH] vc4/drm: Avoid full hdmi audio fifo writes\n\nWe are getting occasional VC4_HD_MAI_CTL_ERRORF in\nHDMI_MAI_CTL which seem to correspond with audio dropouts.\n\nReduce the threshold where we deassert DREQ to avoid the fifo overfilling\n\nSigned-off-by: Dom Cobley <popcornmix@gmail.com>\n---\n drivers/gpu/drm/vc4/vc4_hdmi.c | 8 ++++----\n 1 file changed, 4 insertions(+), 4 deletions(-)\n\n--- a/drivers/gpu/drm/vc4/vc4_hdmi.c\n+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c\n@@ -1297,10 +1297,10 @@ static int vc4_hdmi_audio_prepare(struct\n \n \t/* Set the MAI threshold */\n \tHDMI_WRITE(HDMI_MAI_THR,\n-\t\t   VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICHIGH) |\n-\t\t   VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICLOW) |\n-\t\t   VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQHIGH) |\n-\t\t   VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQLOW));\n+\t\t   VC4_SET_FIELD(0x08, VC4_HD_MAI_THR_PANICHIGH) |\n+\t\t   VC4_SET_FIELD(0x08, VC4_HD_MAI_THR_PANICLOW) |\n+\t\t   VC4_SET_FIELD(0x06, VC4_HD_MAI_THR_DREQHIGH) |\n+\t\t   VC4_SET_FIELD(0x08, VC4_HD_MAI_THR_DREQLOW));\n \n \tHDMI_WRITE(HDMI_MAI_CONFIG,\n \t\t   VC4_HDMI_MAI_CONFIG_BIT_REVERSE |\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0506-vc4-drm-Increase-hdmi-audio-axi-priority-to-avoid-lo.patch",
    "content": "From 40799ca446bed8dcb0bfc667fafb1c3a20f88b87 Mon Sep 17 00:00:00 2001\nFrom: Dom Cobley <popcornmix@gmail.com>\nDate: Fri, 12 Mar 2021 11:26:29 +0000\nSubject: [PATCH] vc4/drm: Increase hdmi audio axi priority to avoid\n lost samples\n\nWith HBR audio (8 channel 192kHz) we get occasional VC4_HD_MAI_CTL_DLATE error flags in\nHDMI_MAI_CTL which seem to correspond with audio dropouts.\n\nIncreasing the normal AXI priority for dma is needed to avoid these\n\nSigned-off-by: Dom Cobley <popcornmix@gmail.com>\n---\n arch/arm/boot/dts/bcm2711-rpi.dtsi | 4 ++--\n 1 file changed, 2 insertions(+), 2 deletions(-)\n\n--- a/arch/arm/boot/dts/bcm2711-rpi.dtsi\n+++ b/arch/arm/boot/dts/bcm2711-rpi.dtsi\n@@ -179,7 +179,7 @@\n };\n \n &hdmi0 {\n-\tdmas = <&dma (10|(1<<27)|(1<<24)|(0<<16)|(15<<20))>;\n+\tdmas = <&dma (10|(1<<27)|(1<<24)|(10<<16)|(15<<20))>;\n \tstatus = \"disabled\";\n };\n \n@@ -188,7 +188,7 @@\n };\n \n &hdmi1 {\n-\tdmas = <&dma (17|(1<<27)|(1<<24)|(0<<16)|(15<<20))>;\n+\tdmas = <&dma (17|(1<<27)|(1<<24)|(10<<16)|(15<<20))>;\n \tstatus = \"disabled\";\n };\n \n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0507-overlays-gpio-led-new-overlay.patch",
    "content": "From 095bad7f310809a951735d03be9d06938524a6bc Mon Sep 17 00:00:00 2001\nFrom: Assaf Gordon <assafgordon@gmail.com>\nDate: Fri, 12 Mar 2021 00:13:07 -0700\nSubject: [PATCH] overlays: gpio-led: new overlay\n\nAdd generic connection between the kernel's LED framework and\nRPI's GPIO pins.\n\nSigned-off-by: Assaf Gordon <assafgordon@gmail.com>\n---\n arch/arm/boot/dts/overlays/Makefile           |  1 +\n arch/arm/boot/dts/overlays/README             | 56 +++++++++++\n .../boot/dts/overlays/gpio-led-overlay.dts    | 97 +++++++++++++++++++\n 3 files changed, 154 insertions(+)\n create mode 100755 arch/arm/boot/dts/overlays/gpio-led-overlay.dts\n\n--- a/arch/arm/boot/dts/overlays/Makefile\n+++ b/arch/arm/boot/dts/overlays/Makefile\n@@ -54,6 +54,7 @@ dtbo-$(CONFIG_ARCH_BCM2835) += \\\n \tgpio-ir.dtbo \\\n \tgpio-ir-tx.dtbo \\\n \tgpio-key.dtbo \\\n+\tgpio-led.dtbo \\\n \tgpio-no-bank0-irq.dtbo \\\n \tgpio-no-irq.dtbo \\\n \tgpio-poweroff.dtbo \\\n--- a/arch/arm/boot/dts/overlays/README\n+++ b/arch/arm/boot/dts/overlays/README\n@@ -914,6 +914,62 @@ Params: gpio                    GPIO pin\n         keycode                 Set the key code for the button\n \n \n+\n+Name:   gpio-led\n+Info:   This is a generic overlay for activating LEDs (or any other component)\n+        by a GPIO pin. Multiple LEDs can be set up using multiple calls to the\n+        overlay. While there are many existing methods to activate LEDs on the\n+        RPi, this method offers some advantages:\n+        1) Does not require any userspace programs.\n+        2) LEDs can be connected to the kernel's led-trigger framework,\n+           and drive the LED based on triggers such as cpu load, heartbeat,\n+           kernel panic, key input, timers and others.\n+        3) LED can be tied to the input state of another GPIO pin.\n+        4) The LED is setup early during the kernel boot process (useful\n+           for cpu/heartbeat/panic triggers).\n+\n+        Typical electrical connection is:\n+           RPI-GPIO.19  ->  LED  -> 300ohm resister  -> RPI-GND\n+        The GPIO pin number can be changed with the 'gpio=' parameter.\n+\n+        To control an LED from userspace, write a 0 or 1 value:\n+           echo 1 > /sys/class/leds/myled1/brightness\n+        The 'myled1' name can be changed with the 'label=' parameter.\n+\n+        To connect the LED to a kernel trigger from userspace:\n+           echo cpu > /sys/class/leds/myled1/trigger\n+           echo heartbeat > /sys/class/leds/myled1/trigger\n+           echo none > /sys/class/leds/myled1/trigger\n+        To connect the LED to GPIO.26 pin (physical pin 37):\n+           echo gpio > /sys/class/leds/myled1/trigger\n+           echo 26 > /sys/class/leds/myled1/gpio\n+        Available triggers:\n+           cat /sys/class/leds/myled1/trigger\n+\n+        More information about the Linux kernel LED/Trigger system:\n+           https://www.kernel.org/doc/Documentation/leds/leds-class.rst\n+           https://www.kernel.org/doc/Documentation/leds/ledtrig-oneshot.rst\n+Load:   dtoverlay=gpio-led,<param>=<val>\n+Params: gpio                    GPIO pin connected to the LED (default 19)\n+        label                   The label for this LED. It will appear under\n+                                /sys/class/leds/<label> . Default 'myled1'.\n+        trigger                 Set the led-trigger to connect to this LED.\n+                                default 'none' (LED is user-controlled).\n+                                Some possible triggers:\n+                                 cpu - CPU load (all CPUs)\n+                                 cpu0 - CPU load of first CPU.\n+                                 mmc - disk activity (all disks)\n+                                 panic - turn on on kernel panic\n+                                 heartbeat - indicate system health\n+                                 gpio - connect to a GPIO input pin (note:\n+                                        currently the GPIO PIN can not be set\n+                                        using overlay parameters, must be\n+                                        done in userspace, see examples above.\n+        active_low              Set to 1 to turn invert the LED control\n+                                (writing 0 to /sys/class/leds/XXX/brightness\n+                                will turn on the GPIO/LED). Default '0'.\n+\n+\n Name:   gpio-no-bank0-irq\n Info:   Use this overlay to disable GPIO interrupts for GPIOs in bank 0 (0-27),\n         which can be useful for UIO drivers.\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/gpio-led-overlay.dts\n@@ -0,0 +1,97 @@\n+// SPDX-License-Identifier: GPL-2.0-or-later\n+/*\n+ * gpio-led - generic connection of kernel's LED framework to the RPI's GPIO.\n+ * Copyright (C) 2021 House Gordon Software Company Ltd. <assafgordon@gmail.com>\n+ *\n+ * Based on information from:\n+ *   https://mjoldfield.com/atelier/2017/03/rpi-devicetree.html\n+ *   https://www.raspberrypi.org/documentation/configuration/device-tree.md\n+ *   https://www.kernel.org/doc/html/latest/leds/index.html\n+ *\n+ * compile with:\n+ *   dtc -@ -Hepapr -I dts -O dtb -o gpio-led.dtbo gpio-led-overlay.dts\n+ *\n+ * There will be some warnings (can be ignored):\n+ *  Warning (label_is_string): /__overrides__:label: property is not a string\n+ *  Warning (unit_address_vs_reg): /fragment@0/__overlay__/led_pins@0:\n+ *                                 node has a unit name, but no reg property\n+ *  Warning (unit_address_vs_reg): /fragment@1/__overlay__/leds@0:\n+ *                                 node has a unit name, but no reg property\n+ *  Warning (gpios_property): /__overrides__: Missing property\n+ *                 '#gpio-cells' in node /fragment@1/__overlay__/leds@0/led\n+ *                  or bad phandle (referred from gpio[0])\n+ *\n+ * Typical electrical connection is:\n+ *    RPI-GPIO.19  ->  LED  -> 300ohm resister  -> RPI-GND\n+ *    The GPIO pin number can be changed with the 'gpio=' parameter.\n+ *\n+ * Test from user-space with:\n+ *   # if nothing is shown, the overlay file isn't found in /boot/overlays\n+ *   dtoverlay -a | grep gpio-led\n+ *\n+ *   # Load the overlay\n+ *   dtoverlay gpio-led label=moo gpio=19\n+ *\n+ *   # if nothing is shown, the overlay wasn't loaded successfully\n+ *   dtoverlay -l | grep gpio-led\n+ *\n+ *   echo 1 > /sys/class/leds/moo/brightness\n+ *   echo 0 > /sys/class/leds/moo/brightness\n+ *   echo cpu > /sys/class/leds/moo/trigger\n+ *   echo heartbeat > /sys/class/leds/moo/trigger\n+ *\n+ *   # unload the overlay\n+ *   dtoverlay -r gpio-led\n+ *\n+ * To load in /boot/config.txt add lines such as:\n+ *   dtoverlay=gpio-led,gpio=19,label=heart,trigger=heartbeat\n+ *   dtoverlay=gpio-led,gpio=26,label=brain,trigger=cpu\n+ */\n+\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\t// Configure the gpio pin controller\n+\t\ttarget = <&gpio>;\n+\t\t__overlay__ {\n+\t\t\tled_pin: led_pins@19 {\n+\t\t\t\tbrcm,pins = <19>; // gpio number\n+\t\t\t\tbrcm,function = <1>; // 0 = input, 1 = output\n+\t\t\t\tbrcm,pull = <0>; // 0 = none, 1 = pull down, 2 = pull up\n+\t\t\t};\n+\t\t};\n+\t};\n+\tfragment@1 {\n+\t\ttarget-path = \"/\";\n+\t\t__overlay__ {\n+\t\t\tleds: leds@0 {\n+\t\t\t\tcompatible = \"gpio-leds\";\n+\t\t\t\tpinctrl-names = \"default\";\n+\t\t\t\tpinctrl-0 = <&led_pin>;\n+\t\t\t\tstatus = \"okay\";\n+\n+\t\t\t\tled: led {\n+\t\t\t                label = \"myled1\";\n+\t\t\t\t\tgpios = <&gpio 19 0>;\n+\t\t\t                linux,default-trigger = \"none\";\n+\t\t\t\t};\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\tgpio =       <&led>,\"gpios:4\",\n+\t\t             <&leds>,\"reg:0\",\n+\t\t             <&led_pin>,\"brcm,pins:0\",\n+\t\t             <&led_pin>,\"reg:0\";\n+\t\tlabel =      <&led>,\"label\";\n+\t\tactive_low = <&led>,\"gpios:8\";\n+\t\ttrigger =    <&led>,\"linux,default-trigger\";\n+\t};\n+\n+};\n+\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0508-overlays-Add-pcie-32bit-dma-overlay.patch",
    "content": "From ce2860020c57a59c543139ad7b260624cd930dff Mon Sep 17 00:00:00 2001\nFrom: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>\nDate: Mon, 15 Mar 2021 17:25:02 +0100\nSubject: [PATCH] overlays: Add pcie-32bit-dma overlay\n\nIn order to accommodate full PCI DMA access to memory on newer BCM2711\nrevisions, we're forced to map PCIe's view of physical memory with an\noffset. This offset makes DMA addressing dependent on having 64bit\nsupport on the PCI device's side. Which isn't always the case.\n\nIn order to mitigate this, introduce the pcie-32bit-dma overlay which\nwill forbid firmware from updating the default inbound memory window.\nThe default setting, albeit limited to accessing the lower 3GB of\nmemory, will allow for 32bit DMA addresses at the expense of having to\nbounce buffers.\n\nLink: https://github.com/raspberrypi/linux/issues/4197\nSigned-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>\n---\n arch/arm/boot/dts/overlays/Makefile            |  1 +\n arch/arm/boot/dts/overlays/README              |  7 +++++++\n arch/arm/boot/dts/overlays/overlay_map.dts     |  4 ++++\n .../dts/overlays/pcie-32bit-dma-overlay.dts    | 18 ++++++++++++++++++\n 4 files changed, 30 insertions(+)\n create mode 100644 arch/arm/boot/dts/overlays/pcie-32bit-dma-overlay.dts\n\n--- a/arch/arm/boot/dts/overlays/Makefile\n+++ b/arch/arm/boot/dts/overlays/Makefile\n@@ -128,6 +128,7 @@ dtbo-$(CONFIG_ARCH_BCM2835) += \\\n \tov9281.dtbo \\\n \tpapirus.dtbo \\\n \tpca953x.dtbo \\\n+\tpcie-32bit-dma.dtbo \\\n \tpibell.dtbo \\\n \tpifacedigital.dtbo \\\n \tpifi-40.dtbo \\\n--- a/arch/arm/boot/dts/overlays/README\n+++ b/arch/arm/boot/dts/overlays/README\n@@ -2135,6 +2135,13 @@ Params: addr                    I2C addr\n         xra1202                 Select the Exar XRA1202 (8 bit)\n \n \n+Name:   pcie-32bit-dma\n+Info:   Force PCIe config to support 32bit DMA addresses at the expense of\n+        having to bounce buffers.\n+Load:   dtoverlay=pcie-32bit-dma\n+Params: <None>\n+\n+\n [ The pcf2127-rtc overlay has been deleted. See i2c-rtc. ]\n \n \n--- a/arch/arm/boot/dts/overlays/overlay_map.dts\n+++ b/arch/arm/boot/dts/overlays/overlay_map.dts\n@@ -37,6 +37,10 @@\n \t\tdeprecated = \"use gpio-ir\";\n \t};\n \n+\tpcie-32bit-dma {\n+\t\tbcm2711;\n+\t};\n+\n \tpi3-act-led {\n \t\trenamed = \"act-led\";\n \t};\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/pcie-32bit-dma-overlay.dts\n@@ -0,0 +1,18 @@\n+/*\n+ * pcie-32bit-dma-overlay.dts\n+ */\n+\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2711\";\n+\n+\tfragment@0 {\n+\t\ttarget-path = \"/aliases\";\n+\t\t__overlay__ {\n+\t\t\tpcie0 = \"\";\n+\t\t};\n+\t};\n+\n+};\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0509-ARM-dts-bcm2711-Add-aliases-for-additional-SPIs.patch",
    "content": "From fe7d0fa216c1ebea42e3391b18e9192eca5fa20f Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.com>\nDate: Mon, 22 Mar 2021 09:27:16 +0000\nSubject: [PATCH] ARM: dts: bcm2711: Add aliases for additional SPIs\n\nWithout aliases for the new SPI interfaces in BCM2711, spidev instances\nwill be allocated sequential numbers that may not match the number of\nthe physical interface.\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.com>\n---\n arch/arm/boot/dts/bcm2711-rpi-4-b.dts | 4 ++++\n arch/arm/boot/dts/bcm2711-rpi-400.dts | 4 ++++\n arch/arm/boot/dts/bcm2711-rpi-cm4.dts | 4 ++++\n 3 files changed, 12 insertions(+)\n\n--- a/arch/arm/boot/dts/bcm2711-rpi-4-b.dts\n+++ b/arch/arm/boot/dts/bcm2711-rpi-4-b.dts\n@@ -355,6 +355,10 @@\n \t\ti2c4 = &i2c4;\n \t\ti2c5 = &i2c5;\n \t\ti2c6 = &i2c6;\n+\t\tspi3 = &spi3;\n+\t\tspi4 = &spi4;\n+\t\tspi5 = &spi5;\n+\t\tspi6 = &spi6;\n \t\t/delete-property/ intc;\n \t};\n \n--- a/arch/arm/boot/dts/bcm2711-rpi-400.dts\n+++ b/arch/arm/boot/dts/bcm2711-rpi-400.dts\n@@ -336,6 +336,10 @@\n \t\ti2c4 = &i2c4;\n \t\ti2c5 = &i2c5;\n \t\ti2c6 = &i2c6;\n+\t\tspi3 = &spi3;\n+\t\tspi4 = &spi4;\n+\t\tspi5 = &spi5;\n+\t\tspi6 = &spi6;\n \t\t/delete-property/ intc;\n \t};\n \n--- a/arch/arm/boot/dts/bcm2711-rpi-cm4.dts\n+++ b/arch/arm/boot/dts/bcm2711-rpi-cm4.dts\n@@ -323,6 +323,10 @@\n \t\ti2c4 = &i2c4;\n \t\ti2c5 = &i2c5;\n \t\ti2c6 = &i2c6;\n+\t\tspi3 = &spi3;\n+\t\tspi4 = &spi4;\n+\t\tspi5 = &spi5;\n+\t\tspi6 = &spi6;\n \t\t/delete-property/ intc;\n \t};\n \n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0510-Make-rpi-poe-fan-less-noisy-in-cool-environments.patch",
    "content": "From 6e4cd276213a20bc55146588b0ec2fc6b622a9d7 Mon Sep 17 00:00:00 2001\nFrom: ProBackup-nl <515451+ProBackup-nl@users.noreply.github.com>\nDate: Thu, 18 Mar 2021 18:21:43 +0100\nSubject: [PATCH] Make rpi poe fan less noisy in cool environments\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nRun the PoE hat fan with reduced noise when possible. The PoE hat fan will spin even at PWM=1 and spins almost silent. Tested at 17ºC, the fan PWM alternates between 1 and 10, which is a lot less noisy then alternating between PWM levels 0 and 31.\n---\n arch/arm/boot/dts/overlays/rpi-poe-overlay.dts | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/arch/arm/boot/dts/overlays/rpi-poe-overlay.dts\n+++ b/arch/arm/boot/dts/overlays/rpi-poe-overlay.dts\n@@ -16,7 +16,7 @@\n \t\t\t\tcooling-min-state = <0>;\n \t\t\t\tcooling-max-state = <4>;\n \t\t\t\t#cooling-cells = <2>;\n-\t\t\t\tcooling-levels = <0 31 63 150 255>;\n+\t\t\t\tcooling-levels = <0 1 10 100 255>;\n \t\t\t\tstatus = \"okay\";\n \t\t\t};\n \t\t};\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0511-vc4-drm-Fix-source-offsets-with-DRM_FORMAT_P030.patch",
    "content": "From c470db2240fa76293025852533ae8bf1c5679bfb Mon Sep 17 00:00:00 2001\nFrom: Dom Cobley <popcornmix@gmail.com>\nDate: Mon, 22 Mar 2021 19:43:48 +0000\nSubject: [PATCH] vc4/drm: Fix source offsets with DRM_FORMAT_P030\n\nSpec says: bits [31:4] of the given address should point to\nthe 128-bit word containing the desired starting pixel,\nand bits[3:0] should be between 0 and 11, indicating which\nof the 12-pixels in that 128-bit word is the first pixel to be used\n\nSigned-off-by: Dom Cobley <popcornmix@gmail.com>\n---\n drivers/gpu/drm/vc4/vc4_plane.c | 24 ++++++++++++++++--------\n 1 file changed, 16 insertions(+), 8 deletions(-)\n\n--- a/drivers/gpu/drm/vc4/vc4_plane.c\n+++ b/drivers/gpu/drm/vc4/vc4_plane.c\n@@ -824,9 +824,20 @@ static int vc4_plane_mode_set(struct drm\n \t\tu32 tile_w, tile, x_off, pix_per_tile;\n \n \t\tif (fb->format->format == DRM_FORMAT_P030) {\n+\t\t\t/*\n+\t\t\t * Spec says: bits [31:4] of the given address should point to\n+\t\t\t * the 128-bit word containing the desired starting pixel,\n+\t\t\t * and bits[3:0] should be between 0 and 11, indicating which\n+\t\t\t * of the 12-pixels in that 128-bit word is the first pixel to be used\n+\t\t\t */\n+\t\t\tu32 aligned = vc4_state->src_x / 12;\n+\t\t\tu32 last_bits = vc4_state->src_x % 12;\n+\n+\t\t\tx_off = aligned * 16 + last_bits;\n \t\t\thvs_format = HVS_PIXEL_FORMAT_YCBCR_10BIT;\n \t\t\ttiling = SCALER_CTL0_TILING_128B;\n-\t\t\ttile_w = 96;\n+\t\t\ttile_w = 128;\n+\t\t\tpix_per_tile = 96;\n \t\t} else {\n \t\t\thvs_format = HVS_PIXEL_FORMAT_H264;\n \n@@ -846,17 +857,16 @@ static int vc4_plane_mode_set(struct drm\n \t\t\tdefault:\n \t\t\t\tbreak;\n \t\t\t}\n+\t\t\tpix_per_tile = tile_w / fb->format->cpp[0];\n+\t\t\tx_off = (vc4_state->src_x % pix_per_tile) /\n+\t\t\t\t(i ? h_subsample : 1) * fb->format->cpp[i];\n \t\t}\n \t\tif (param > SCALER_TILE_HEIGHT_MASK) {\n \t\t\tDRM_DEBUG_KMS(\"SAND height too large (%d)\\n\",\n \t\t\t\t      param);\n \t\t\treturn -EINVAL;\n \t\t}\n-\n-\t\tpix_per_tile = tile_w / fb->format->cpp[0];\n \t\ttile = vc4_state->src_x / pix_per_tile;\n-\t\tx_off = vc4_state->src_x % pix_per_tile;\n-\n \t\t/* Adjust the base pointer to the first pixel to be scanned\n \t\t * out.\n \t\t *\n@@ -872,9 +882,7 @@ static int vc4_plane_mode_set(struct drm\n \t\t\tvc4_state->offsets[i] += src_y /\n \t\t\t\t\t\t (i ? v_subsample : 1) *\n \t\t\t\t\t\t tile_w;\n-\t\t\tvc4_state->offsets[i] += x_off /\n-\t\t\t\t\t\t (i ? h_subsample : 1) *\n-\t\t\t\t\t\t fb->format->cpp[i];\n+\t\t\tvc4_state->offsets[i] += x_off & ~(i ? 1 : 0);\n \t\t}\n \n \t\tpitch0 = VC4_SET_FIELD(param, SCALER_TILE_HEIGHT);\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0512-vc4-drm-vc4_plane-Remove-subpixel-positioning-check.patch",
    "content": "From aa5ba5fd06cffacf4831fe6e9aef65081287924e Mon Sep 17 00:00:00 2001\nFrom: Dom Cobley <popcornmix@gmail.com>\nDate: Mon, 15 Mar 2021 13:28:06 +0000\nSubject: [PATCH] vc4/drm: vc4_plane: Remove subpixel positioning check\n\nThere is little harm in ignoring fractional coordinates\n(they just get truncated).\n\nWithout this:\nmodetest -M vc4 -F tiles,gradient -s 32:1920x1080-60 -P89@74:1920x1080*.1.1@XR24\n\nis rejected. We have the same issue in Kodi when trying to\nuse zoom options on video.\n\nNote: even if all coordinates are fully integer. e.g.\nsrc:[0,0,1920,1080] dest:[-10,-10,1940,1100]\n\nit will still get rejected as drm_atomic_helper_check_plane_state\nuses drm_rect_clip_scaled which transforms this to fractional src coords\n\nSigned-off-by: Dom Cobley <popcornmix@gmail.com>\n---\n drivers/gpu/drm/vc4/vc4_plane.c | 21 ++++++++-------------\n 1 file changed, 8 insertions(+), 13 deletions(-)\n\n--- a/drivers/gpu/drm/vc4/vc4_plane.c\n+++ b/drivers/gpu/drm/vc4/vc4_plane.c\n@@ -339,7 +339,6 @@ static int vc4_plane_setup_clipping_and_\n \tstruct vc4_plane_state *vc4_state = to_vc4_plane_state(state);\n \tstruct drm_framebuffer *fb = state->fb;\n \tstruct drm_gem_cma_object *bo = drm_fb_cma_get_gem_obj(fb, 0);\n-\tu32 subpixel_src_mask = (1 << 16) - 1;\n \tint num_planes = fb->format->num_planes;\n \tstruct drm_crtc_state *crtc_state;\n \tu32 h_subsample = fb->format->hsub;\n@@ -361,18 +360,14 @@ static int vc4_plane_setup_clipping_and_\n \tfor (i = 0; i < num_planes; i++)\n \t\tvc4_state->offsets[i] = bo->paddr + fb->offsets[i];\n \n-\t/* We don't support subpixel source positioning for scaling. */\n-\tif ((state->src.x1 & subpixel_src_mask) ||\n-\t    (state->src.x2 & subpixel_src_mask) ||\n-\t    (state->src.y1 & subpixel_src_mask) ||\n-\t    (state->src.y2 & subpixel_src_mask)) {\n-\t\treturn -EINVAL;\n-\t}\n-\n-\tvc4_state->src_x = state->src.x1 >> 16;\n-\tvc4_state->src_y = state->src.y1 >> 16;\n-\tvc4_state->src_w[0] = (state->src.x2 - state->src.x1) >> 16;\n-\tvc4_state->src_h[0] = (state->src.y2 - state->src.y1) >> 16;\n+\t/* We don't support subpixel source positioning for scaling,\n+\t * but fractional coordinates can be generated by clipping\n+\t * so just round for now\n+\t */\n+\tvc4_state->src_x = DIV_ROUND_CLOSEST(state->src.x1, 1<<16);\n+\tvc4_state->src_y = DIV_ROUND_CLOSEST(state->src.y1, 1<<16);\n+\tvc4_state->src_w[0] = DIV_ROUND_CLOSEST(state->src.x2, 1<<16) - vc4_state->src_x;\n+\tvc4_state->src_h[0] = DIV_ROUND_CLOSEST(state->src.y2, 1<<16) - vc4_state->src_y;\n \n \tvc4_state->crtc_x = state->dst.x1;\n \tvc4_state->crtc_y = state->dst.y1;\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0513-clk-raspberrypi-Also-support-HEVC-clock.patch",
    "content": "From 0bf118ac01f74d16e6220261b0ca66928587fb43 Mon Sep 17 00:00:00 2001\nFrom: Dom Cobley <popcornmix@gmail.com>\nDate: Mon, 22 Feb 2021 18:47:19 +0000\nSubject: [PATCH] clk-raspberrypi: Also support HEVC clock\n\nSigned-off-by: Dom Cobley <popcornmix@gmail.com>\n---\n drivers/clk/bcm/clk-raspberrypi.c | 1 +\n 1 file changed, 1 insertion(+)\n\n--- a/drivers/clk/bcm/clk-raspberrypi.c\n+++ b/drivers/clk/bcm/clk-raspberrypi.c\n@@ -271,6 +271,7 @@ static int raspberrypi_discover_clocks(s\n \t\tcase RPI_FIRMWARE_CORE_CLK_ID:\n \t\tcase RPI_FIRMWARE_M2MC_CLK_ID:\n \t\tcase RPI_FIRMWARE_V3D_CLK_ID:\n+\t\tcase RPI_FIRMWARE_HEVC_CLK_ID:\n \t\tcase RPI_FIRMWARE_PIXEL_BVB_CLK_ID:\n \t\t\thw = raspberrypi_clk_register(rpi, clks->parent,\n \t\t\t\t\t\t      clks->id);\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0514-dt-Switch-hevc-clock-from-fixed-to-firmware-driver.patch",
    "content": "From f62df99cbc8077b602006ccc47e4d2ce6acdeed2 Mon Sep 17 00:00:00 2001\nFrom: Dom Cobley <popcornmix@gmail.com>\nDate: Mon, 22 Feb 2021 18:47:43 +0000\nSubject: [PATCH] dt: Switch hevc clock from fixed to firmware driver\n\nSigned-off-by: Dom Cobley <popcornmix@gmail.com>\n---\n arch/arm/boot/dts/overlays/rpivid-v4l2-overlay.dts | 13 +------------\n 1 file changed, 1 insertion(+), 12 deletions(-)\n\n--- a/arch/arm/boot/dts/overlays/rpivid-v4l2-overlay.dts\n+++ b/arch/arm/boot/dts/overlays/rpivid-v4l2-overlay.dts\n@@ -24,7 +24,7 @@\n \n \t\t\t\tinterrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;\n \n-\t\t\t\tclocks = <&hevc_clk>;\n+\t\t\t\tclocks = <&firmware_clocks 11>;\n \t\t\t\tclock-names = \"hevc\";\n \t\t\t};\n \t\t};\n@@ -47,15 +47,4 @@\n \t\t\t};\n \t\t};\n \t};\n-\n-\tfragment@2 {\n-\t\ttarget-path = \"/\";\n-\t\t__overlay__ {\n-\t\t\thevc_clk: hevc_clk {\n-\t\t\t\tcompatible = \"fixed-clock\";\n-\t\t\t\t#clock-cells = <0>;\n-\t\t\t\tclock-frequency = <500000000>;\n-\t\t\t};\n-\t\t};\n-\t};\n };\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0515-rpivid-Request-maximum-hevc-clock.patch",
    "content": "From a292e26529c7f46a549625f94bdbba004d8caa5f Mon Sep 17 00:00:00 2001\nFrom: Dom Cobley <popcornmix@gmail.com>\nDate: Mon, 22 Feb 2021 18:50:50 +0000\nSubject: [PATCH] rpivid: Request maximum hevc clock\n\nQuery maximum and minimum clock from driver\nand use those\n\nSigned-off-by: Dom Cobley <popcornmix@gmail.com>\n---\n drivers/staging/media/rpivid/rpivid_video.c | 9 ++++++++-\n 1 file changed, 8 insertions(+), 1 deletion(-)\n\n--- a/drivers/staging/media/rpivid/rpivid_video.c\n+++ b/drivers/staging/media/rpivid/rpivid_video.c\n@@ -490,6 +490,7 @@ static int rpivid_start_streaming(struct\n {\n \tstruct rpivid_ctx *ctx = vb2_get_drv_priv(vq);\n \tstruct rpivid_dev *dev = ctx->dev;\n+\tlong max_hevc_clock = clk_round_rate(dev->clock, ULONG_MAX);\n \tint ret = 0;\n \n \tif (ctx->src_fmt.pixelformat != V4L2_PIX_FMT_HEVC_SLICE)\n@@ -498,7 +499,7 @@ static int rpivid_start_streaming(struct\n \tif (V4L2_TYPE_IS_OUTPUT(vq->type) && dev->dec_ops->start)\n \t\tret = dev->dec_ops->start(ctx);\n \n-\tret = clk_set_rate(dev->clock, 500 * 1000 * 1000);\n+\tret = clk_set_rate(dev->clock, max_hevc_clock);\n \tif (ret) {\n \t\tdev_err(dev->dev, \"Failed to set clock rate\\n\");\n \t\tgoto out;\n@@ -519,12 +520,18 @@ static void rpivid_stop_streaming(struct\n {\n \tstruct rpivid_ctx *ctx = vb2_get_drv_priv(vq);\n \tstruct rpivid_dev *dev = ctx->dev;\n+\tlong min_hevc_clock = clk_round_rate(dev->clock, 0);\n+\tint ret;\n \n \tif (V4L2_TYPE_IS_OUTPUT(vq->type) && dev->dec_ops->stop)\n \t\tdev->dec_ops->stop(ctx);\n \n \trpivid_queue_cleanup(vq, VB2_BUF_STATE_ERROR);\n \n+\tret = clk_set_rate(dev->clock, min_hevc_clock);\n+\tif (ret)\n+\t\tdev_err(dev->dev, \"Failed to set minimum clock rate\\n\");\n+\n \tclk_disable_unprepare(dev->clock);\n }\n \n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0516-staging-bcm2835-camera-Add-support-for-DMABUFs.patch",
    "content": "From 12dc4e884b44a95ebd4da612a5f57a24e9a1930f Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Wed, 17 Mar 2021 12:34:57 +0000\nSubject: [PATCH] staging/bcm2835-camera: Add support for DMABUFs\n\nDMABUFs are all handled by videobuf2, so there is no reason not\nto enable support for them.\n\nNote that this driver is still using the vmalloc allocator, so\nthe buffers it allocates will not be compatible with the codec\nor ISP driver that require contiguous buffers. However this\ndriver should be able to import the buffers allocated by them.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n drivers/staging/vc04_services/bcm2835-camera/bcm2835-camera.c | 3 ++-\n 1 file changed, 2 insertions(+), 1 deletion(-)\n\n--- a/drivers/staging/vc04_services/bcm2835-camera/bcm2835-camera.c\n+++ b/drivers/staging/vc04_services/bcm2835-camera/bcm2835-camera.c\n@@ -1453,6 +1453,7 @@ static const struct v4l2_ioctl_ops camer\n \t.vidioc_querybuf = vb2_ioctl_querybuf,\n \t.vidioc_qbuf = vb2_ioctl_qbuf,\n \t.vidioc_dqbuf = vb2_ioctl_dqbuf,\n+\t.vidioc_expbuf = vb2_ioctl_expbuf,\n \t.vidioc_enum_framesizes = vidioc_enum_framesizes,\n \t.vidioc_enum_frameintervals = vidioc_enum_frameintervals,\n \t.vidioc_g_parm        = vidioc_g_parm,\n@@ -1934,7 +1935,7 @@ static int bcm2835_mmal_probe(struct pla\n \t\tq = &dev->capture.vb_vidq;\n \t\tmemset(q, 0, sizeof(*q));\n \t\tq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;\n-\t\tq->io_modes = VB2_MMAP | VB2_USERPTR | VB2_READ;\n+\t\tq->io_modes = VB2_MMAP | VB2_USERPTR | VB2_READ | VB2_DMABUF;\n \t\tq->drv_priv = dev;\n \t\tq->buf_struct_size = sizeof(struct vb2_mmal_buffer);\n \t\tq->ops = &bm2835_mmal_video_qops;\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0517-staging-fbtft-Add-minipitft13-variant.patch",
    "content": "From b279b2516d9fc40cc491b142fbf453f9533f6e4f Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.com>\nDate: Fri, 19 Feb 2021 10:25:01 +0000\nSubject: [PATCH] staging: fbtft: Add minipitft13 variant\n\nThe Adafruit Mini-PiTFT13 display needs offsets applying when rotated,\nso use the \"variant\" mechanism to select a custom set_addr_win method\nusing a dedicated compatible string of \"fbtft,minipitft13\".\n\nSee: https://github.com/raspberrypi/firmware/issues/1524\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.com>\n---\n drivers/staging/fbtft/fb_st7789v.c | 45 +++++++++++++++++++++++++++++-\n 1 file changed, 44 insertions(+), 1 deletion(-)\n\n--- a/drivers/staging/fbtft/fb_st7789v.c\n+++ b/drivers/staging/fbtft/fb_st7789v.c\n@@ -66,6 +66,12 @@ enum st7789v_command {\n #define MADCTL_MX BIT(6) /* bitmask for column address order */\n #define MADCTL_MY BIT(7) /* bitmask for page address order */\n \n+static u32 col_offset = 0;\n+static u32 row_offset = 0;\n+static u8 col_hack_fix_offset = 0;\n+static short x_offset = 0;\n+static short y_offset = 0;\n+\n /**\n  * init_display() - initialize the display controller\n  *\n@@ -147,6 +153,22 @@ static int init_display(struct fbtft_par\n \treturn 0;\n }\n \n+static void minipitft13_set_addr_win(struct fbtft_par *par, int xs, int ys,\n+\t\t\t\t     int xe, int ye)\n+{\n+\txs += x_offset;\n+\txe += x_offset;\n+\tys += y_offset;\n+\tye += y_offset;\n+\twrite_reg(par, MIPI_DCS_SET_COLUMN_ADDRESS,\n+\t\t  xs >> 8, xs & 0xFF, xe >> 8, xe & 0xFF);\n+\n+\twrite_reg(par, MIPI_DCS_SET_PAGE_ADDRESS,\n+\t\t  ys >> 8, ys & 0xFF, ye >> 8, ye & 0xFF);\n+\n+\twrite_reg(par, MIPI_DCS_WRITE_MEMORY_START);\n+}\n+\n /**\n  * set_var() - apply LCD properties like rotation and BGR mode\n  *\n@@ -157,20 +179,32 @@ static int init_display(struct fbtft_par\n static int set_var(struct fbtft_par *par)\n {\n \tu8 madctl_par = 0;\n+\tstruct fbtft_display *display = &par->pdata->display;\n+\tu32 width = display->width;\n+\tu32 height = display->height;\n \n \tif (par->bgr)\n \t\tmadctl_par |= MADCTL_BGR;\n \tswitch (par->info->var.rotate) {\n \tcase 0:\n+\t\tx_offset = 0;\n+\t\ty_offset = 0;\n \t\tbreak;\n \tcase 90:\n \t\tmadctl_par |= (MADCTL_MV | MADCTL_MY);\n+\t\tx_offset = (320 - height) - row_offset;\n+\t\ty_offset = (240 - width) - col_offset;\n \t\tbreak;\n \tcase 180:\n \t\tmadctl_par |= (MADCTL_MX | MADCTL_MY);\n+\t\tx_offset = (240 - width) - col_offset + col_hack_fix_offset;\n+\t\t// hack tweak to account for extra pixel width to make even\n+\t\ty_offset = (320 - height) - row_offset;\n \t\tbreak;\n \tcase 270:\n \t\tmadctl_par |= (MADCTL_MV | MADCTL_MX);\n+\t\tx_offset = row_offset;\n+\t\ty_offset = col_offset;\n \t\tbreak;\n \tdefault:\n \t\treturn -EINVAL;\n@@ -267,7 +301,16 @@ static struct fbtft_display display = {\n \t},\n };\n \n-FBTFT_REGISTER_DRIVER(DRVNAME, \"sitronix,st7789v\", &display);\n+int variant_minipitft13(struct fbtft_display *display)\n+{\n+\tdisplay->fbtftops.set_addr_win = minipitft13_set_addr_win;\n+\treturn 0;\n+}\n+\n+FBTFT_REGISTER_DRIVER_START(&display)\n+FBTFT_COMPATIBLE(\"sitronix,st7789v\")\n+FBTFT_VARIANT_COMPATIBLE(\"fbtft,minipitft13\", variant_minipitft13)\n+FBTFT_REGISTER_DRIVER_END(DRVNAME, &display);\n \n MODULE_ALIAS(\"spi:\" DRVNAME);\n MODULE_ALIAS(\"platform:\" DRVNAME);\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0518-overlays-Add-minipitft13-overlay.patch",
    "content": "From 6c6596610381249719e87e324a9689cabc2a7cd8 Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.com>\nDate: Thu, 18 Feb 2021 21:05:44 +0000\nSubject: [PATCH] overlays: Add minipitft13 overlay\n\nminipitft13 is an overlay for the Adafruit 1.3\" 240x240 display\n(code 4484).\n\nSee: https://github.com/raspberrypi/firmware/issues/1524\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.com>\n---\n arch/arm/boot/dts/overlays/Makefile           |  1 +\n .../boot/dts/overlays/minipitft13-overlay.dts | 70 +++++++++++++++++++\n 2 files changed, 71 insertions(+)\n create mode 100644 arch/arm/boot/dts/overlays/minipitft13-overlay.dts\n\n--- a/arch/arm/boot/dts/overlays/Makefile\n+++ b/arch/arm/boot/dts/overlays/Makefile\n@@ -119,6 +119,7 @@ dtbo-$(CONFIG_ARCH_BCM2835) += \\\n \tmerus-amp.dtbo \\\n \tmidi-uart0.dtbo \\\n \tmidi-uart1.dtbo \\\n+\tminipitft13.dtbo \\\n \tminiuart-bt.dtbo \\\n \tmmc.dtbo \\\n \tmpu6050.dtbo \\\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/minipitft13-overlay.dts\n@@ -0,0 +1,70 @@\n+/*\n+ * Device Tree overlay for Adafruit Mini PiTFT 1.3\" and 1.5\" 240x240 Display\n+ *\n+ */\n+\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+        compatible = \"brcm,bcm2835\";\n+\n+        fragment@0 {\n+                target = <&spi0>;\n+                __overlay__ {\n+                        status = \"okay\";\n+\n+                        spidev@0{\n+                                status = \"disabled\";\n+                        };\n+\n+                        spidev@1{\n+                                status = \"disabled\";\n+                        };\n+                };\n+        };\n+\n+        fragment@1 {\n+                target = <&gpio>;\n+                __overlay__ {\n+                        pitft_pins: pitft_pins {\n+                                brcm,pins = <25>;\n+                                brcm,function = <1>; /* out */\n+                                brcm,pull = <0>; /* none */\n+                        };\n+                };\n+        };\n+\n+        fragment@2 {\n+                target = <&spi0>;\n+                __overlay__ {\n+                        /* needed to avoid dtc warning */\n+                        #address-cells = <1>;\n+                        #size-cells = <0>;\n+\n+                        pitft: pitft@0 {\n+                                compatible = \"fbtft,minipitft13\";\n+                                reg = <0>;\n+                                pinctrl-names = \"default\";\n+                                pinctrl-0 = <&pitft_pins>;\n+                                spi-max-frequency = <32000000>;\n+                                rotate = <0>;\n+                                width = <240>;\n+                                height = <240>;\n+                                buswidth = <8>;\n+                                dc-gpios = <&gpio 25 0>;\n+                                led-gpios = <&gpio 26 0>;\n+                                debug = <0>;\n+                        };\n+                };\n+        };\n+\n+        __overrides__ {\n+                speed =   <&pitft>,\"spi-max-frequency:0\";\n+                rotate =  <&pitft>,\"rotate:0\";\n+                width =   <&pitft>,\"width:0\";\n+                height =  <&pitft>,\"height:0\";\n+                fps =     <&pitft>,\"fps:0\";\n+                debug =   <&pitft>,\"debug:0\";\n+        };\n+};\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0519-overlays-ghost-amp-Minor-tweaks.patch",
    "content": "From e88444a73ef7bc16869e60ad1e392129a07a9f2c Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.com>\nDate: Wed, 3 Mar 2021 10:31:13 +0000\nSubject: [PATCH] overlays: ghost-amp: Minor tweaks\n\n1. Reduce the delay between RELAY1 and RELAY2 to 1000ms.\n2. Rename the states to simplify LED control by an external script.\n3. Claim all the required GPIOs, enabling pull-ups on the input.\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.com>\n---\n .../boot/dts/overlays/ghost-amp-overlay.dts   | 20 ++++++++++++++++---\n 1 file changed, 17 insertions(+), 3 deletions(-)\n\n--- a/arch/arm/boot/dts/overlays/ghost-amp-overlay.dts\n+++ b/arch/arm/boot/dts/overlays/ghost-amp-overlay.dts\n@@ -54,6 +54,8 @@\n \t\t__overlay__ {\n \t\t\tamp: ghost-amp {\n \t\t\t\tcompatible = \"rpi,gpio-fsm\";\n+\t\t\t\tpinctrl-names = \"default\";\n+\t\t\t\tpinctrl-0 = <&ghost_amp_pins>;\n \n \t\t\t\tdebug = <0>;\n \t\t\t\tgpio-controller;\n@@ -77,18 +79,18 @@\n \n \t\t\t\tamp_on_1 {\n \t\t\t\t\tset = <RELAY1 1>;\n-\t\t\t\t\tamp_on = <GF_DELAY 1500>;\n+\t\t\t\t\tamp_on = <GF_DELAY 1000>;\n \t\t\t\t\tamp_off = <ENABLE 0>;\n \t\t\t\t\tfault = <FAULT 1>;\n \t\t\t\t};\n \n \t\t\t\tamp_on {\n \t\t\t\t\tset = <RELAY2 1>;\n-\t\t\t\t\tamp_off_wait = <ENABLE 0>;\n+\t\t\t\t\tamp_on_wait = <ENABLE 0>;\n \t\t\t\t\tfault = <FAULT 1>;\n \t\t\t\t};\n \n-\t\t\t\tamp_off_wait {\n+\t\t\t\tamp_on_wait {\n \t\t\t\t\tamp_off_1 = <GF_DELAY (30*60*1000)>,\n \t\t\t\t\t\t    <GF_SHUTDOWN 0>;\n \t\t\t\t\tamp_on = <ENABLE 1>;\n@@ -107,11 +109,23 @@\n \t\t\t\tfault {\n \t\t\t\t\tset = <RELAY2 0>,\n \t\t\t\t\t      <RELAY1 0>;\n+\t\t\t\t\tamp_off = <FAULT 0>;\n \t\t\t\t\tshutdown_state;\n \t\t\t\t};\n \t\t\t};\n \t\t};\n \t};\n+\n+\tfragment@4 {\n+\t\ttarget = <&gpio>;\n+\t\t__overlay__ {\n+\t\t\tghost_amp_pins: ghost_amp_pins {\n+\t\t\t\tbrcm,pins = <5 22 23>;\n+\t\t\t\tbrcm,function = <0 1 1>; /* in out out */\n+\t\t\t\tbrcm,pull = <2 0 0>; /* up none none */\n+\t\t\t};\n+\t\t};\n+\t};\n \n \t__overrides__ {\n \t\tfsm_debug = <&amp>,\"debug:0\";\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0520-overlays-Add-README-entry-for-minipitft13.patch",
    "content": "From 7f2f7250d1f5ad8369fa4424e9091c6fffde408d Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.com>\nDate: Mon, 29 Mar 2021 12:05:06 +0100\nSubject: [PATCH] overlays: Add README entry for minipitft13\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.com>\n---\n arch/arm/boot/dts/overlays/README | 11 +++++++++++\n 1 file changed, 11 insertions(+)\n\n--- a/arch/arm/boot/dts/overlays/README\n+++ b/arch/arm/boot/dts/overlays/README\n@@ -2018,6 +2018,17 @@ Load:   dtoverlay=midi-uart1\n Params: <None>\n \n \n+Name:   minipitft13\n+Info:   Overlay for AdaFruit Mini Pi 1.3\" TFT via SPI using fbtft driver.\n+Load:   dtoverlay=minipitft13,<param>=<val>\n+Params: speed                   SPI bus speed (default 32000000)\n+        rotate                  Display rotation (0, 90, 180 or 270; default 0)\n+        width                   Display width (default 240)\n+        height                  Display height (default 240)\n+        fps                     Delay between frame updates (default 25)\n+        debug                   Debug output level (0-7; default 0)\n+\n+\n Name:   miniuart-bt\n Info:   Switch the onboard Bluetooth function on Pi 3B, 3B+, 3A+, 4B and Zero W\n         to use the mini-UART (ttyS0) and restore UART0/ttyAMA0 over GPIOs 14 &\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0521-ARM-dts-update-bcm2711-rpi-cm4.dts-and-400.patch",
    "content": "From a38d7464ca20e1c0aaa3ed77e03e1ea6af4bc557 Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.com>\nDate: Wed, 31 Mar 2021 10:22:30 +0100\nSubject: [PATCH] ARM: dts: update bcm2711-rpi-cm4.dts and -400\n\nNeither CM4 nor Pi 400 have appeared upstream yet, and as a result\nthey have missed out on improvements to the Pi 4B platform.\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.com>\n\nARM: dts: Bring bcm2711-rpi-400.dts up-to-date\n\nPi 400 support has not appeared upstream yet, and as a result it has\nmissed out on improvements to the other Pi 4 platforms.\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.com>\n---\n arch/arm/boot/dts/bcm2711-rpi-400.dts | 17 +++++++\n arch/arm/boot/dts/bcm2711-rpi-cm4.dts | 73 +++++++++++++++++++++------\n 2 files changed, 74 insertions(+), 16 deletions(-)\n\n--- a/arch/arm/boot/dts/bcm2711-rpi-400.dts\n+++ b/arch/arm/boot/dts/bcm2711-rpi-400.dts\n@@ -24,6 +24,7 @@\n \t\temmc2bus = &emmc2bus;\n \t\tethernet0 = &genet;\n \t\tpcie0 = &pcie0;\n+\t\tblconfig = &blconfig;\n \t};\n \n \tleds {\n@@ -215,6 +216,22 @@\n \tstatus = \"okay\";\n };\n \n+&rmem {\n+\t/*\n+\t * RPi4's co-processor will copy the board's bootloader configuration\n+\t * into memory for the OS to consume. It'll also update this node with\n+\t * its placement information.\n+\t */\n+\tblconfig: nvram@0 {\n+\t\tcompatible = \"raspberrypi,bootloader-config\", \"nvmem-rmem\";\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <1>;\n+\t\treg = <0x0 0x0 0x0>;\n+\t\tno-map;\n+\t\tstatus = \"disabled\";\n+\t};\n+};\n+\n /* SDHCI is used to control the SDIO for wireless */\n &sdhci {\n \t#address-cells = <1>;\n--- a/arch/arm/boot/dts/bcm2711-rpi-cm4.dts\n+++ b/arch/arm/boot/dts/bcm2711-rpi-cm4.dts\n@@ -3,6 +3,8 @@\n #include \"bcm2711.dtsi\"\n #include \"bcm2835-rpi.dtsi\"\n \n+#include <dt-bindings/reset/raspberrypi,firmware-reset.h>\n+\n / {\n \tcompatible = \"raspberrypi,4-compute-module\", \"brcm,bcm2711\";\n \tmodel = \"Raspberry Pi Compute Module 4\";\n@@ -22,6 +24,7 @@\n \t\temmc2bus = &emmc2bus;\n \t\tethernet0 = &genet;\n \t\tpcie0 = &pcie0;\n+\t\tblconfig = &blconfig;\n \t};\n \n \tleds {\n@@ -76,6 +79,11 @@\n };\n \n &firmware {\n+\tfirmware_clocks: clocks {\n+\t\tcompatible = \"raspberrypi,firmware-clocks\";\n+\t\t#clock-cells = <1>;\n+\t};\n+\n \texpgpio: gpio {\n \t\tcompatible = \"raspberrypi,firmware-gpio\";\n \t\tgpio-controller;\n@@ -102,6 +110,11 @@\n \t\t\toutput-low;\n \t\t};\n \t};\n+\n+\treset: reset {\n+\t\tcompatible = \"raspberrypi,firmware-reset\";\n+\t\t#reset-cells = <1>;\n+\t};\n };\n \n &gpio {\n@@ -209,20 +222,28 @@\n \tstatus = \"okay\";\n };\n \n-&vc4 {\n-\tstatus = \"okay\";\n-};\n-\n-&vec {\n-\tstatus = \"disabled\";\n-};\n-\n &pwm1 {\n \tpinctrl-names = \"default\";\n \tpinctrl-0 = <&pwm1_0_gpio40 &pwm1_1_gpio41>;\n \tstatus = \"okay\";\n };\n \n+&rmem {\n+\t/*\n+\t * RPi4's co-processor will copy the board's bootloader configuration\n+\t * into memory for the OS to consume. It'll also update this node with\n+\t * its placement information.\n+\t */\n+\tblconfig: nvram@0 {\n+\t\tcompatible = \"raspberrypi,bootloader-config\", \"nvmem-rmem\";\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <1>;\n+\t\treg = <0x0 0x0 0x0>;\n+\t\tno-map;\n+\t\tstatus = \"disabled\";\n+\t};\n+};\n+\n /* SDHCI is used to control the SDIO for wireless */\n &sdhci {\n \t#address-cells = <1>;\n@@ -262,6 +283,21 @@\n \t};\n };\n \n+&pcie0 {\n+\tpci@1,0 {\n+\t\t#address-cells = <3>;\n+\t\t#size-cells = <2>;\n+\t\tranges;\n+\n+\t\treg = <0 0 0 0 0>;\n+\n+\t\tusb@1,0 {\n+\t\t\treg = <0x10000 0 0 0 0>;\n+\t\t\tresets = <&reset RASPBERRYPI_FIRMWARE_RESET_ID_USB>;\n+\t\t};\n+\t};\n+};\n+\n /* uart0 communicates with the BT module */\n &uart0 {\n \tpinctrl-names = \"default\";\n@@ -287,6 +323,14 @@\n \tinterrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;\n };\n \n+&vc4 {\n+\tstatus = \"okay\";\n+};\n+\n+&vec {\n+\tstatus = \"disabled\";\n+};\n+\n // =============================================\n // Downstream rpi- changes\n \n@@ -306,6 +350,7 @@\n #include \"bcm283x-rpi-csi0-2lane.dtsi\"\n #include \"bcm283x-rpi-csi1-4lane.dtsi\"\n #include \"bcm283x-rpi-i2c0mux_0_44.dtsi\"\n+#include \"bcm283x-rpi-cam1-regulator.dtsi\"\n \n / {\n \tchosen {\n@@ -331,14 +376,6 @@\n \t};\n \n \t/delete-node/ wifi-pwrseq;\n-\n-\tcam0_reg: cam1_reg: cam1_reg {\n-\t\tcompatible = \"regulator-fixed\";\n-\t\tregulator-name = \"cam1-reg\";\n-\t\tgpio = <&expgpio 5 GPIO_ACTIVE_HIGH>;\n-\t\tenable-active-high;\n-\t\tstatus = \"disabled\";\n-\t};\n };\n \n &mmcnr {\n@@ -589,6 +626,10 @@\n \tbrcm,disable-headphones = <1>;\n };\n \n+cam0_reg: &cam1_reg {\n+\tgpio = <&expgpio 5 GPIO_ACTIVE_HIGH>;\n+};\n+\n / {\n \t__overrides__ {\n \t\tact_led_gpio = <&act_led>,\"gpios:4\";\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0522-vc4-drm-SQUASH-Fix-source-offsets-with-DRM_FORMAT_P0.patch",
    "content": "From 38643fd0a26ba42938a361db296e28f3b4975d8c Mon Sep 17 00:00:00 2001\nFrom: Dom Cobley <popcornmix@gmail.com>\nDate: Wed, 31 Mar 2021 18:12:55 +0100\nSubject: [PATCH] vc4/drm: SQUASH: Fix source offsets with\n DRM_FORMAT_P030\n\nx_off should only be within current stripe\nThe stripe number is accounted for elsewhere\n\nFixes: 9b1b1beb1c7e58b (\"vc4/drm: Fix source offsets with DRM_FORMAT_P030\")\n\nSigned-off-by: Dom Cobley <popcornmix@gmail.com>\n---\n drivers/gpu/drm/vc4/vc4_plane.c | 5 +++--\n 1 file changed, 3 insertions(+), 2 deletions(-)\n\n--- a/drivers/gpu/drm/vc4/vc4_plane.c\n+++ b/drivers/gpu/drm/vc4/vc4_plane.c\n@@ -825,8 +825,9 @@ static int vc4_plane_mode_set(struct drm\n \t\t\t * and bits[3:0] should be between 0 and 11, indicating which\n \t\t\t * of the 12-pixels in that 128-bit word is the first pixel to be used\n \t\t\t */\n-\t\t\tu32 aligned = vc4_state->src_x / 12;\n-\t\t\tu32 last_bits = vc4_state->src_x % 12;\n+\t                u32 remaining_pixels = vc4_state->src_x % 96;\n+\t\t\tu32 aligned = remaining_pixels / 12;\n+\t\t\tu32 last_bits = remaining_pixels % 12;\n \n \t\t\tx_off = aligned * 16 + last_bits;\n \t\t\thvs_format = HVS_PIXEL_FORMAT_YCBCR_10BIT;\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0523-dwc-otg-fix-clang-Wignored-attributes-warning.patch",
    "content": "From a928bb06853aa2fb2a17f5e6d22273e9731f8b3b Mon Sep 17 00:00:00 2001\nFrom: Jo Henke <37883863+jo-he@users.noreply.github.com>\nDate: Tue, 6 Apr 2021 11:21:35 +0000\nSubject: [PATCH] dwc-otg: fix clang -Wignored-attributes warning\n\nwarning: attribute declaration must precede definition\n---\n drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.h | 12 ++++++------\n 1 file changed, 6 insertions(+), 6 deletions(-)\n\n--- a/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.h\n+++ b/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.h\n@@ -255,17 +255,17 @@ struct fiq_dma_info {\n \tu8 slot_len[6];\n };\n \n-struct __attribute__((packed)) fiq_split_dma_slot {\n+struct fiq_split_dma_slot {\n \tu8 buf[188];\n-};\n+} __attribute__((packed));\n \n struct fiq_dma_channel {\n-\tstruct __attribute__((packed)) fiq_split_dma_slot index[6];\n-};\n+\tstruct fiq_split_dma_slot index[6];\n+} __attribute__((packed));\n \n struct fiq_dma_blob {\n-\tstruct __attribute__((packed)) fiq_dma_channel channel[0];\n-};\n+\tstruct fiq_dma_channel channel[0];\n+} __attribute__((packed));\n \n /**\n  * struct fiq_hs_isoc_info - USB2.0 isochronous data\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0524-dwc-otg-fix-clang-Wsometimes-uninitialized-warning.patch",
    "content": "From bb876407b553af0fd55b2b07f0261d1f02eae6c1 Mon Sep 17 00:00:00 2001\nFrom: Jo Henke <37883863+jo-he@users.noreply.github.com>\nDate: Tue, 6 Apr 2021 11:38:28 +0000\nSubject: [PATCH] dwc-otg: fix clang -Wsometimes-uninitialized warning\n\nwarning: variable 'retval' is used uninitialized whenever 'if' condition is false\n---\n drivers/usb/host/dwc_otg/dwc_otg_cil_intr.c | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/drivers/usb/host/dwc_otg/dwc_otg_cil_intr.c\n+++ b/drivers/usb/host/dwc_otg/dwc_otg_cil_intr.c\n@@ -805,7 +805,7 @@ static int32_t dwc_otg_handle_pwrdn_sess\n  */\n static uint32_t dwc_otg_handle_pwrdn_stschng_intr(dwc_otg_device_t *otg_dev)\n {\n-\tint retval;\n+\tuint32_t retval = 0;\n \tgpwrdn_data_t gpwrdn = {.d32 = 0 };\n \tgpwrdn_data_t gpwrdn_temp = {.d32 = 0 };\n \tdwc_otg_core_if_t *core_if = otg_dev->core_if;\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0525-dwc-otg-fix-clang-Wpointer-bool-conversion-warning.patch",
    "content": "From 58429d46cf9700a9087662633ab71027eeb80bd6 Mon Sep 17 00:00:00 2001\nFrom: Jo Henke <37883863+jo-he@users.noreply.github.com>\nDate: Tue, 6 Apr 2021 11:45:14 +0000\nSubject: [PATCH] dwc-otg: fix clang -Wpointer-bool-conversion warning\n\nwarning: address of array 'desc->wMaxPacketSize' will always evaluate to 'true'\n\nThe wMaxPacketSize field is actually a two element array which content should\nbe accessed via the UGETW macro.\n---\n drivers/usb/host/dwc_otg/dwc_otg_pcd.c | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/drivers/usb/host/dwc_otg/dwc_otg_pcd.c\n+++ b/drivers/usb/host/dwc_otg/dwc_otg_pcd.c\n@@ -1487,7 +1487,7 @@ int dwc_otg_pcd_ep_enable(dwc_otg_pcd_t\n \tnum = UE_GET_ADDR(desc->bEndpointAddress);\n \tdir = UE_GET_DIR(desc->bEndpointAddress);\n \n-\tif (!desc->wMaxPacketSize) {\n+\tif (!UGETW(desc->wMaxPacketSize)) {\n \t\tDWC_WARN(\"bad maxpacketsize\\n\");\n \t\tretval = -DWC_E_INVALID;\n \t\tgoto out;\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0526-Update-Allo-Piano-Dac-Driver.patch",
    "content": "From df85dac9b4a0855ba40c14fdf7ba93b33fd1db35 Mon Sep 17 00:00:00 2001\nFrom: paul-1 <6473457+paul-1@users.noreply.github.com>\nDate: Fri, 2 Apr 2021 10:56:19 -0400\nSubject: [PATCH] Update Allo Piano Dac Driver\n\nAdd unique names to the individual dac coded drivers\nRemove some of the codec controls that are not used.\n\nSigned-off-by: Paul Hermann <paul@picoreplayer.org>\n\n# Conflicts:\n#\tsound/soc/bcm/allo-piano-dac-plus.c\n---\n sound/soc/bcm/allo-piano-dac-plus.c | 152 +++++++++++++++++++++-------\n 1 file changed, 114 insertions(+), 38 deletions(-)\n\n--- a/sound/soc/bcm/allo-piano-dac-plus.c\n+++ b/sound/soc/bcm/allo-piano-dac-plus.c\n@@ -2,7 +2,8 @@\n  * ALSA ASoC Machine Driver for Allo Piano DAC Plus Subwoofer\n  *\n  * Author:\tBaswaraj K <jaikumar@cem-solutions.net>\n- *\t\tCopyright 2016\n+ *\t\tCopyright 2020\n+ *\t\tbased on code by David Knell <david.knell@gmail.com)\n  *\t\tbased on code by Daniel Matuschek <info@crazy-audio.com>\n  *\t\tbased on code by Florian Meier <florian.meier@koalo.de>\n  *\n@@ -276,8 +277,15 @@ static int snd_allo_piano_dual_mode_put(\n \t\t\t\tPCM512x_DIGITAL_VOLUME_2, 0xff);\n \n \t\tlist_for_each_entry(kctl, &snd_card_ptr->controls, list) {\n-\t\t\tif (!strncmp(kctl->id.name, \"Digital Playback Volume\",\n-\t\t\t\t\tsizeof(kctl->id.name))) {\n+\t\t\tif (!strncmp(kctl->id.name, \"Main Digital Playback Volume\",\n+\t\t\t\tsizeof(kctl->id.name))) {\n+\t\t\t\tmc = (struct soc_mixer_control *)\n+\t\t\t\t\tkctl->private_value;\n+\t\t\t\tmc->rreg = mc->reg;\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t\tif (!strncmp(kctl->id.name, \"Sub Digital Playback Volume\",\n+\t\t\t\tsizeof(kctl->id.name))) {\n \t\t\t\tmc = (struct soc_mixer_control *)\n \t\t\t\t\tkctl->private_value;\n \t\t\t\tmc->rreg = mc->reg;\n@@ -291,13 +299,20 @@ static int snd_allo_piano_dual_mode_put(\n \t\t\t\t\t\tPCM512x_DIGITAL_VOLUME_3);\n \n \t\tlist_for_each_entry(kctl, &snd_card_ptr->controls, list) {\n-\t\t\tif (!strncmp(kctl->id.name, \"Digital Playback Volume\",\n-\t\t\t\t\tsizeof(kctl->id.name))) {\n+\t\t\tif (!strncmp(kctl->id.name, \"Main Digital Playback Volume\",\n+\t\t\t\tsizeof(kctl->id.name))) {\n \t\t\t\tmc = (struct soc_mixer_control *)\n \t\t\t\t\tkctl->private_value;\n \t\t\t\tmc->rreg = PCM512x_DIGITAL_VOLUME_3;\n \t\t\t\tbreak;\n \t\t\t}\n+\t\t\tif (!strncmp(kctl->id.name, \"Sub Digital Playback Volume\",\n+\t\t\t\tsizeof(kctl->id.name))) {\n+\t\t\t\tmc = (struct soc_mixer_control *)\n+\t\t\t\t\tkctl->private_value;\n+\t\t\t\tmc->rreg = PCM512x_DIGITAL_VOLUME_2;\n+\t\t\t\tbreak;\n+\t\t\t}\n \t\t}\n \n \t\tsnd_soc_component_write(asoc_rtd_to_codec(rtd, 0)->component,\n@@ -344,13 +359,20 @@ static int snd_allo_piano_mode_put(struc\n \t\t\t\t\t\tPCM512x_DIGITAL_VOLUME_2);\n \n \t\tlist_for_each_entry(kctl, &snd_card_ptr->controls, list) {\n-\t\t\tif (!strncmp(kctl->id.name, \"Digital Playback Volume\",\n-\t\t\t\t\tsizeof(kctl->id.name))) {\n+\t\t\tif (!strncmp(kctl->id.name, \"Main Digital Playback Volume\",\n+\t\t\t\tsizeof(kctl->id.name))) {\n \t\t\t\tmc = (struct soc_mixer_control *)\n \t\t\t\t\tkctl->private_value;\n \t\t\t\tmc->rreg = PCM512x_DIGITAL_VOLUME_3;\n \t\t\t\tbreak;\n \t\t\t}\n+\t\t\tif (!strncmp(kctl->id.name, \"Sub Digital Playback Volume\",\n+\t\t\t\tsizeof(kctl->id.name))) {\n+\t\t\t\tmc = (struct soc_mixer_control *)\n+\t\t\t\t\tkctl->private_value;\n+\t\t\t\tmc->rreg = PCM512x_DIGITAL_VOLUME_2;\n+\t\t\t\tbreak;\n+\t\t\t}\n \t\t}\n \t\tsnd_soc_component_write(asoc_rtd_to_codec(rtd, 0)->component,\n \t\t\t\tPCM512x_DIGITAL_VOLUME_3, left_val);\n@@ -397,6 +419,7 @@ static int pcm512x_get_reg_sub(struct sn\n \tunsigned int left_val = 0;\n \tunsigned int right_val = 0;\n \trtd = snd_soc_get_pcm_runtime(card, &card->dai_link[0]);\n+\n \tright_val = snd_soc_component_read(asoc_rtd_to_codec(rtd, 1)->component,\n \t\t\tPCM512x_DIGITAL_VOLUME_3);\n \tif (glb_ptr->dual_mode != 1) {\n@@ -428,12 +451,6 @@ static int pcm512x_set_reg_sub(struct sn\n \tint ret = 0;\n \n \trtd = snd_soc_get_pcm_runtime(card, &card->dai_link[0]);\n-\tif (glb_ptr->dual_mode != 1) {\n-\t\tret = snd_soc_component_write(asoc_rtd_to_codec(rtd, 1)->component,\n-\t\t\t\tPCM512x_DIGITAL_VOLUME_2, (~left_val));\n-\t\tif (ret < 0)\n-\t\t\treturn ret;\n-\t}\n \n \tif (digital_gain_0db_limit) {\n \t\tret = snd_soc_limit_volume(card, \"Subwoofer Playback Volume\",\n@@ -443,10 +460,20 @@ static int pcm512x_set_reg_sub(struct sn\n \t\t\t\tret);\n \t}\n \n-\tret = snd_soc_component_write(asoc_rtd_to_codec(rtd, 1)->component,\n-\t\t\tPCM512x_DIGITAL_VOLUME_3, (~right_val));\n-\tif (ret < 0)\n-\t\treturn ret;\n+\t// When in Dual Mono, Sub vol control should not set anything.\n+\tif (glb_ptr->dual_mode != 1) { //Not in Dual Mono mode\n+\n+\t\tret = snd_soc_component_write(asoc_rtd_to_codec(rtd, 1)->component,\n+\t\t\t\tPCM512x_DIGITAL_VOLUME_2, (~left_val));\n+\t\tif (ret < 0)\n+\t\t\treturn ret;\n+\n+\t\tret = snd_soc_component_write(asoc_rtd_to_codec(rtd, 1)->component,\n+\t\t\t\tPCM512x_DIGITAL_VOLUME_3, (~right_val));\n+\t\tif (ret < 0)\n+\t\t\treturn ret;\n+\n+\t}\n \n \treturn 1;\n }\n@@ -505,7 +532,7 @@ static int pcm512x_get_reg_master(struct\n \tleft_val = snd_soc_component_read(asoc_rtd_to_codec(rtd, 0)->component,\n \t\t\tPCM512x_DIGITAL_VOLUME_2);\n \n-\tif (glb_ptr->dual_mode == 1) {\n+\tif (glb_ptr->dual_mode == 1) {  // in Dual Mono mode\n \t\tright_val = snd_soc_component_read(asoc_rtd_to_codec(rtd, 1)->component,\n \t\t\t\tPCM512x_DIGITAL_VOLUME_3);\n \t} else {\n@@ -543,8 +570,21 @@ static int pcm512x_set_reg_master(struct\n \t\t\t\tret);\n \t}\n \n-\tif (glb_ptr->dual_mode != 1) {\n+\tif (glb_ptr->dual_mode == 1) { //in Dual Mono Mode\n+\n+\t\tret = snd_soc_component_write(asoc_rtd_to_codec(rtd, 0)->component,\n+\t\t\t\tPCM512x_DIGITAL_VOLUME_2, (~left_val));\n+\t\tif (ret < 0)\n+\t\t\treturn ret;\n+\n \t\tret = snd_soc_component_write(asoc_rtd_to_codec(rtd, 1)->component,\n+\t\t\t\tPCM512x_DIGITAL_VOLUME_3, (~right_val));\n+\t\tif (ret < 0)\n+\t\t\treturn ret;\n+\n+\t} else {\n+\n+\t\tret = snd_soc_component_write(asoc_rtd_to_codec(rtd, 0)->component,\n \t\t\t\tPCM512x_DIGITAL_VOLUME_2, (~left_val));\n \t\tif (ret < 0)\n \t\t\treturn ret;\n@@ -555,16 +595,6 @@ static int pcm512x_set_reg_master(struct\n \t\t\treturn ret;\n \n \t}\n-\n-\tret = snd_soc_component_write(asoc_rtd_to_codec(rtd, 1)->component,\n-\t\t\tPCM512x_DIGITAL_VOLUME_3, (~right_val));\n-\tif (ret < 0)\n-\t\treturn ret;\n-\n-\tret = snd_soc_component_write(asoc_rtd_to_codec(rtd, 0)->component,\n-\t\t\tPCM512x_DIGITAL_VOLUME_2, (~left_val));\n-\tif (ret < 0)\n-\t\treturn ret;\n \treturn 1;\n }\n \n@@ -680,10 +710,32 @@ static const struct snd_kcontrol_new all\n \t\t\tpcm512x_set_reg_master_switch),\n };\n \n+static const char * const codec_ctl_pfx[] = { \"Main\", \"Sub\" };\n+static const char * const codec_ctl_name[] = {\n+\t\"Digital Playback Volume\",\n+\t\"Digital Playback Switch\",\n+\t\"Auto Mute Mono Switch\",\n+\t\"Auto Mute Switch\",\n+\t\"Auto Mute Time Left\",\n+\t\"Auto Mute Time Right\",\n+\t\"Clock Missing Period\",\n+\t\"Max Overclock DAC\",\n+\t\"Max Overclock DSP\",\n+\t\"Max Overclock PLL\",\n+\t\"Volume Ramp Down Emergency Rate\",\n+\t\"Volume Ramp Down Emergency Step\",\n+\t\"Volume Ramp Up Rate\",\n+\t\"Volume Ramp Down Rate\",\n+\t\"Volume Ramp Up Step\",\n+\t\"Volume Ramp Down Step\"\n+};\n+\n static int snd_allo_piano_dac_init(struct snd_soc_pcm_runtime *rtd)\n {\n \tstruct snd_soc_card *card = rtd->card;\n \tstruct glb_pool *glb_ptr;\n+\tstruct snd_kcontrol *kctl;\n+\tint i, j;\n \n \tglb_ptr = kzalloc(sizeof(struct glb_pool), GFP_KERNEL);\n \tif (!glb_ptr)\n@@ -698,12 +750,36 @@ static int snd_allo_piano_dac_init(struc\n \tif (digital_gain_0db_limit) {\n \t\tint ret;\n \n-\t\tret = snd_soc_limit_volume(card, \"Digital Playback Volume\",\n-\t\t\t\t\t207);\n-\t\tif (ret < 0)\n-\t\t\tdev_warn(card->dev, \"Failed to set volume limit: %d\\n\",\n-\t\t\t\tret);\n+\t\t//Set volume limit on both dacs\n+\t\tfor (i = 0; i < ARRAY_SIZE(codec_ctl_pfx); i++) {\n+\t\t\tchar cname[256];\n+\n+\t\t\tsprintf(cname, \"%s %s\", codec_ctl_pfx[i], codec_ctl_name[0]);\n+\t\t\tret = snd_soc_limit_volume(card, cname, 207);\n+\t\t\tif (ret < 0)\n+\t\t\t\tdev_warn(card->dev, \"Failed to set volume limit: %d\\n\",\n+\t\t\t\t\tret);\n+\t\t}\n+\t}\n+\n+\t// Remove codec controls\n+\tfor (i = 0; i < ARRAY_SIZE(codec_ctl_pfx); i++) {\n+\t\tfor (j = 0; j < ARRAY_SIZE(codec_ctl_name); j++) {\n+\t\t\tchar cname[256];\n+\n+\t\t\tsprintf(cname, \"%s %s\", codec_ctl_pfx[i], codec_ctl_name[j]);\n+\t\t\tkctl = snd_soc_card_get_kcontrol(card, cname);\n+\t\t\tif (!kctl) {\n+\t\t\t\tdev_err(rtd->card->dev, \"Control %s not found\\n\",\n+\t\t\t\t       cname);\n+\t\t\t} else {\n+\t\t\t\tkctl->vd[0].access =\n+\t\t\t\t\tSNDRV_CTL_ELEM_ACCESS_READWRITE;\n+\t\t\t\tsnd_ctl_remove(card->snd_card, kctl);\n+\t\t\t}\n+\t\t}\n \t}\n+\n \treturn 0;\n }\n \n@@ -842,10 +918,10 @@ static struct snd_soc_dai_link_component\n };\n \n SND_SOC_DAILINK_DEFS(allo_piano_dai_plus,\n-\tDAILINK_COMP_ARRAY(COMP_CPU(\"bcm2708-i2s.0\")),\n-\tDAILINK_COMP_ARRAY(COMP_CODEC(NULL, \"pcm512x-hifi\"),\n-\t\t\t   COMP_CODEC(NULL, \"pcm512x-hifi\")),\n-\tDAILINK_COMP_ARRAY(COMP_PLATFORM(\"bcm2708-i2s.0\")));\n+\tDAILINK_COMP_ARRAY(COMP_EMPTY()),\n+\tDAILINK_COMP_ARRAY(COMP_CODEC(\"pcm512x.1-004c\", \"pcm512x-hifi\"),\n+\t\t\t   COMP_CODEC(\"pcm512x.1-004d\", \"pcm512x-hifi\")),\n+\tDAILINK_COMP_ARRAY(COMP_EMPTY()));\n \n static struct snd_soc_dai_link snd_allo_piano_dac_dai[] = {\n \t{\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0527-drm-connector-Create-a-helper-to-attach-the-hdr_outp.patch",
    "content": "From c65eada45c578cfb558ee9a92ce5048a367692d7 Mon Sep 17 00:00:00 2001\nFrom: Maxime Ripard <maxime@cerno.tech>\nDate: Fri, 19 Mar 2021 11:21:41 +0100\nSubject: [PATCH] drm/connector: Create a helper to attach the\n hdr_output_metadata property\n\nAll the drivers that implement HDR output call pretty much the same\nfunction to initialise the hdr_output_metadata property, and while the\ncreation of that property is in a helper, every driver uses the same\ncode to attach it.\n\nProvide a helper for it as well\n\nSigned-off-by: Maxime Ripard <maxime@cerno.tech>\n---\n .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |  4 +---\n drivers/gpu/drm/bridge/synopsys/dw-hdmi.c     |  3 +--\n drivers/gpu/drm/drm_connector.c               | 21 +++++++++++++++++++\n drivers/gpu/drm/i915/display/intel_hdmi.c     |  3 +--\n include/drm/drm_connector.h                   |  1 +\n 5 files changed, 25 insertions(+), 7 deletions(-)\n\n--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c\n+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c\n@@ -6532,9 +6532,7 @@ void amdgpu_dm_connector_init_helper(str\n \tif (connector_type == DRM_MODE_CONNECTOR_HDMIA ||\n \t    connector_type == DRM_MODE_CONNECTOR_DisplayPort ||\n \t    connector_type == DRM_MODE_CONNECTOR_eDP) {\n-\t\tdrm_object_attach_property(\n-\t\t\t&aconnector->base.base,\n-\t\t\tdm->ddev->mode_config.hdr_output_metadata_property, 0);\n+\t\tdrm_connector_attach_hdr_output_metadata_property(&aconnector->base);\n \n \t\tif (!aconnector->mst_port)\n \t\t\tdrm_connector_attach_vrr_capable_property(&aconnector->base);\n--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c\n+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c\n@@ -2500,8 +2500,7 @@ static int dw_hdmi_connector_create(stru\n \tdrm_connector_attach_max_bpc_property(connector, 8, 16);\n \n \tif (hdmi->version >= 0x200a && hdmi->plat_data->use_drm_infoframe)\n-\t\tdrm_object_attach_property(&connector->base,\n-\t\t\tconnector->dev->mode_config.hdr_output_metadata_property, 0);\n+\t\tdrm_connector_attach_hdr_output_metadata_property(connector);\n \n \tdrm_connector_attach_encoder(connector, hdmi->bridge.encoder);\n \n--- a/drivers/gpu/drm/drm_connector.c\n+++ b/drivers/gpu/drm/drm_connector.c\n@@ -2144,6 +2144,27 @@ int drm_connector_attach_max_bpc_propert\n EXPORT_SYMBOL(drm_connector_attach_max_bpc_property);\n \n /**\n+ * drm_connector_attach_hdr_output_metadata_property - attach \"HDR_OUTPUT_METADA\" property\n+ * @connector: connector to attach the property on.\n+ *\n+ * This is used to allow the userspace to send HDR Metadata to the\n+ * driver.\n+ *\n+ * Returns:\n+ * Zero on success, negative errno on failure.\n+ */\n+int drm_connector_attach_hdr_output_metadata_property(struct drm_connector *connector)\n+{\n+\tstruct drm_device *dev = connector->dev;\n+\tstruct drm_property *prop = dev->mode_config.hdr_output_metadata_property;\n+\n+\tdrm_object_attach_property(&connector->base, prop, 0);\n+\n+\treturn 0;\n+}\n+EXPORT_SYMBOL(drm_connector_attach_hdr_output_metadata_property);\n+\n+/**\n  * drm_connector_set_vrr_capable_property - sets the variable refresh rate\n  * capable property for a connector\n  * @connector: drm connector\n--- a/drivers/gpu/drm/i915/display/intel_hdmi.c\n+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c\n@@ -2971,8 +2971,7 @@ intel_hdmi_add_properties(struct intel_h\n \tdrm_connector_attach_content_type_property(connector);\n \n \tif (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))\n-\t\tdrm_object_attach_property(&connector->base,\n-\t\t\tconnector->dev->mode_config.hdr_output_metadata_property, 0);\n+\t\tdrm_connector_attach_hdr_output_metadata_property(connector);\n \n \tif (!HAS_GMCH(dev_priv))\n \t\tdrm_connector_attach_max_bpc_property(connector, 8, 12);\n--- a/include/drm/drm_connector.h\n+++ b/include/drm/drm_connector.h\n@@ -1622,6 +1622,7 @@ int drm_connector_attach_scaling_mode_pr\n \t\t\t\t\t       u32 scaling_mode_mask);\n int drm_connector_attach_vrr_capable_property(\n \t\tstruct drm_connector *connector);\n+int drm_connector_attach_hdr_output_metadata_property(struct drm_connector *connector);\n int drm_mode_create_aspect_ratio_property(struct drm_device *dev);\n int drm_mode_create_hdmi_colorspace_property(struct drm_connector *connector);\n int drm_mode_create_dp_colorspace_property(struct drm_connector *connector);\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0528-drm-connector-Add-helper-to-compare-HDR-metadata.patch",
    "content": "From 5278eeece5b7b66019cf9c1a833c815cff9819ec Mon Sep 17 00:00:00 2001\nFrom: Maxime Ripard <maxime@cerno.tech>\nDate: Fri, 19 Mar 2021 13:05:53 +0100\nSubject: [PATCH] drm/connector: Add helper to compare HDR metadata\n\nAll the drivers that support the HDR metadata property have a similar\nfunction to compare the metadata from one connector state to the next,\nand force a mode change if they differ.\n\nAll these functions run pretty much the same code, so let's turn it into\nan helper that can be shared across those drivers.\n\nSigned-off-by: Maxime Ripard <maxime@cerno.tech>\n---\n .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 21 +-------------\n drivers/gpu/drm/bridge/synopsys/dw-hdmi.c     | 17 +----------\n drivers/gpu/drm/drm_connector.c               | 28 +++++++++++++++++++\n drivers/gpu/drm/i915/display/intel_atomic.c   | 13 +--------\n include/drm/drm_connector.h                   |  2 ++\n 5 files changed, 33 insertions(+), 48 deletions(-)\n\n--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c\n+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c\n@@ -5477,25 +5477,6 @@ static int fill_hdr_info_packet(const st\n \treturn 0;\n }\n \n-static bool\n-is_hdr_metadata_different(const struct drm_connector_state *old_state,\n-\t\t\t  const struct drm_connector_state *new_state)\n-{\n-\tstruct drm_property_blob *old_blob = old_state->hdr_output_metadata;\n-\tstruct drm_property_blob *new_blob = new_state->hdr_output_metadata;\n-\n-\tif (old_blob != new_blob) {\n-\t\tif (old_blob && new_blob &&\n-\t\t    old_blob->length == new_blob->length)\n-\t\t\treturn memcmp(old_blob->data, new_blob->data,\n-\t\t\t\t      old_blob->length);\n-\n-\t\treturn true;\n-\t}\n-\n-\treturn false;\n-}\n-\n static int\n amdgpu_dm_connector_atomic_check(struct drm_connector *conn,\n \t\t\t\t struct drm_atomic_state *state)\n@@ -5511,7 +5492,7 @@ amdgpu_dm_connector_atomic_check(struct\n \tif (!crtc)\n \t\treturn 0;\n \n-\tif (is_hdr_metadata_different(old_con_state, new_con_state)) {\n+\tif (!drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state)) {\n \t\tstruct dc_info_packet hdr_infopacket;\n \n \t\tret = fill_hdr_info_packet(new_con_state, &hdr_infopacket);\n--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c\n+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c\n@@ -2403,21 +2403,6 @@ static int dw_hdmi_connector_get_modes(s\n \treturn ret;\n }\n \n-static bool hdr_metadata_equal(const struct drm_connector_state *old_state,\n-\t\t\t       const struct drm_connector_state *new_state)\n-{\n-\tstruct drm_property_blob *old_blob = old_state->hdr_output_metadata;\n-\tstruct drm_property_blob *new_blob = new_state->hdr_output_metadata;\n-\n-\tif (!old_blob || !new_blob)\n-\t\treturn old_blob == new_blob;\n-\n-\tif (old_blob->length != new_blob->length)\n-\t\treturn false;\n-\n-\treturn !memcmp(old_blob->data, new_blob->data, old_blob->length);\n-}\n-\n static int dw_hdmi_connector_atomic_check(struct drm_connector *connector,\n \t\t\t\t\t  struct drm_atomic_state *state)\n {\n@@ -2431,7 +2416,7 @@ static int dw_hdmi_connector_atomic_chec\n \tif (!crtc)\n \t\treturn 0;\n \n-\tif (!hdr_metadata_equal(old_state, new_state)) {\n+\tif (!drm_connector_atomic_hdr_metadata_equal(old_state, new_state)) {\n \t\tcrtc_state = drm_atomic_get_crtc_state(state, crtc);\n \t\tif (IS_ERR(crtc_state))\n \t\t\treturn PTR_ERR(crtc_state);\n--- a/drivers/gpu/drm/drm_connector.c\n+++ b/drivers/gpu/drm/drm_connector.c\n@@ -2165,6 +2165,34 @@ int drm_connector_attach_hdr_output_meta\n EXPORT_SYMBOL(drm_connector_attach_hdr_output_metadata_property);\n \n /**\n+ * drm_connector_atomic_hdr_metadata_equal - checks if the hdr metadata changed\n+ * @old_state: old connector state to compare\n+ * @new_state: new connector state to compare\n+ *\n+ * This is used by HDR-enabled drivers to test whether the HDR metadata\n+ * have changed between two different connector state (and thus probably\n+ * requires a full blown mode change).\n+ *\n+ * Returns:\n+ * True if the metadata are equal, False otherwise\n+ */\n+bool drm_connector_atomic_hdr_metadata_equal(struct drm_connector_state *old_state,\n+\t\t\t\t\t     struct drm_connector_state *new_state)\n+{\n+\tstruct drm_property_blob *old_blob = old_state->hdr_output_metadata;\n+\tstruct drm_property_blob *new_blob = new_state->hdr_output_metadata;\n+\n+\tif (!old_blob || !new_blob)\n+\t\treturn old_blob == new_blob;\n+\n+\tif (old_blob->length != new_blob->length)\n+\t\treturn false;\n+\n+\treturn !memcmp(old_blob->data, new_blob->data, old_blob->length);\n+}\n+EXPORT_SYMBOL(drm_connector_atomic_hdr_metadata_equal);\n+\n+/**\n  * drm_connector_set_vrr_capable_property - sets the variable refresh rate\n  * capable property for a connector\n  * @connector: drm connector\n--- a/drivers/gpu/drm/i915/display/intel_atomic.c\n+++ b/drivers/gpu/drm/i915/display/intel_atomic.c\n@@ -109,16 +109,6 @@ int intel_digital_connector_atomic_set_p\n \treturn -EINVAL;\n }\n \n-static bool blob_equal(const struct drm_property_blob *a,\n-\t\t       const struct drm_property_blob *b)\n-{\n-\tif (a && b)\n-\t\treturn a->length == b->length &&\n-\t\t\t!memcmp(a->data, b->data, a->length);\n-\n-\treturn !a == !b;\n-}\n-\n int intel_digital_connector_atomic_check(struct drm_connector *conn,\n \t\t\t\t\t struct drm_atomic_state *state)\n {\n@@ -150,8 +140,7 @@ int intel_digital_connector_atomic_check\n \t    new_conn_state->base.picture_aspect_ratio != old_conn_state->base.picture_aspect_ratio ||\n \t    new_conn_state->base.content_type != old_conn_state->base.content_type ||\n \t    new_conn_state->base.scaling_mode != old_conn_state->base.scaling_mode ||\n-\t    !blob_equal(new_conn_state->base.hdr_output_metadata,\n-\t\t\told_conn_state->base.hdr_output_metadata))\n+\t    !drm_connector_atomic_hdr_metadata_equal(old_state, new_state))\n \t\tcrtc_state->mode_changed = true;\n \n \treturn 0;\n--- a/include/drm/drm_connector.h\n+++ b/include/drm/drm_connector.h\n@@ -1623,6 +1623,8 @@ int drm_connector_attach_scaling_mode_pr\n int drm_connector_attach_vrr_capable_property(\n \t\tstruct drm_connector *connector);\n int drm_connector_attach_hdr_output_metadata_property(struct drm_connector *connector);\n+bool drm_connector_atomic_hdr_metadata_equal(struct drm_connector_state *old_state,\n+\t\t\t\t\t     struct drm_connector_state *new_state);\n int drm_mode_create_aspect_ratio_property(struct drm_device *dev);\n int drm_mode_create_hdmi_colorspace_property(struct drm_connector *connector);\n int drm_mode_create_dp_colorspace_property(struct drm_connector *connector);\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0529-drm-vc4-Use-the-new-helpers.patch",
    "content": "From b29e72769f843afeb4585c5310f8bf23c0277daf Mon Sep 17 00:00:00 2001\nFrom: Maxime Ripard <maxime@cerno.tech>\nDate: Fri, 9 Apr 2021 17:31:55 +0200\nSubject: [PATCH] drm/vc4: Use the new helpers\n\nWe just introduced new helpers, so let's use them.\n\nSigned-off-by: Maxime Ripard <maxime@cerno.tech>\n---\n drivers/gpu/drm/vc4/vc4_hdmi.c | 23 ++++-------------------\n 1 file changed, 4 insertions(+), 19 deletions(-)\n\n--- a/drivers/gpu/drm/vc4/vc4_hdmi.c\n+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c\n@@ -224,21 +224,6 @@ static int vc4_hdmi_connector_get_modes(\n \treturn ret;\n }\n \n-static bool hdr_metadata_equal(const struct drm_connector_state *old_state,\n-\t\t\t       const struct drm_connector_state *new_state)\n-{\n-\tstruct drm_property_blob *old_blob = old_state->hdr_output_metadata;\n-\tstruct drm_property_blob *new_blob = new_state->hdr_output_metadata;\n-\n-\tif (!old_blob || !new_blob)\n-\t\treturn old_blob == new_blob;\n-\n-\tif (old_blob->length != new_blob->length)\n-\t\treturn false;\n-\n-\treturn !memcmp(old_blob->data, new_blob->data, old_blob->length);\n-}\n-\n static int vc4_hdmi_connector_atomic_check(struct drm_connector *connector,\n \t\t\t\t\t  struct drm_atomic_state *state)\n {\n@@ -247,12 +232,13 @@ static int vc4_hdmi_connector_atomic_che\n \tstruct drm_connector_state *new_state =\n \t\tdrm_atomic_get_new_connector_state(state, connector);\n \tstruct drm_crtc *crtc = new_state->crtc;\n-\tstruct drm_crtc_state *crtc_state;\n \n \tif (!crtc)\n \t\treturn 0;\n \n-\tif (!hdr_metadata_equal(old_state, new_state)) {\n+\tif (!drm_connector_atomic_hdr_metadata_equal(old_state, new_state)) {\n+\t\tstruct drm_crtc_state *crtc_state;\n+\n \t\tcrtc_state = drm_atomic_get_crtc_state(state, crtc);\n \t\tif (IS_ERR(crtc_state))\n \t\t\treturn PTR_ERR(crtc_state);\n@@ -351,8 +337,7 @@ static int vc4_hdmi_connector_init(struc\n \tconnector->stereo_allowed = 1;\n \n \tif (vc4_hdmi->variant->supports_hdr)\n-\t\tdrm_object_attach_property(&connector->base,\n-\t\t\tconnector->dev->mode_config.hdr_output_metadata_property, 0);\n+\t\tdrm_connector_attach_hdr_output_metadata_property(connector);\n \n \tdrm_connector_attach_encoder(connector, encoder);\n \n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0530-drm-connector-Add-a-helper-to-attach-the-colorspace-.patch",
    "content": "From a7f87202ec94410eabff8df2f4fced0141794a9a Mon Sep 17 00:00:00 2001\nFrom: Maxime Ripard <maxime@cerno.tech>\nDate: Fri, 9 Apr 2021 17:07:32 +0200\nSubject: [PATCH] drm/connector: Add a helper to attach the colorspace\n property\n\nThe intel driver uses the same logic to attach the Colorspace property\nin multiple places and we'll need it in vc4 too. Let's move that common\ncode in a helper.\n\nSigned-off-by: Maxime Ripard <maxime@cerno.tech>\n---\n drivers/gpu/drm/drm_connector.c               | 20 +++++++++++++++++++\n .../gpu/drm/i915/display/intel_connector.c    |  3 +--\n include/drm/drm_connector.h                   |  1 +\n 3 files changed, 22 insertions(+), 2 deletions(-)\n\n--- a/drivers/gpu/drm/drm_connector.c\n+++ b/drivers/gpu/drm/drm_connector.c\n@@ -2165,6 +2165,26 @@ int drm_connector_attach_hdr_output_meta\n EXPORT_SYMBOL(drm_connector_attach_hdr_output_metadata_property);\n \n /**\n+ * drm_connector_attach_colorspace_property - attach \"Colorspace\" property\n+ * @connector: connector to attach the property on.\n+ *\n+ * This is used to allow the userspace to signal the output colorspace\n+ * to the driver.\n+ *\n+ * Returns:\n+ * Zero on success, negative errno on failure.\n+ */\n+int drm_connector_attach_colorspace_property(struct drm_connector *connector)\n+{\n+\tstruct drm_property *prop = connector->colorspace_property;\n+\n+\tdrm_object_attach_property(&connector->base, prop, DRM_MODE_COLORIMETRY_DEFAULT);\n+\n+\treturn 0;\n+}\n+EXPORT_SYMBOL(drm_connector_attach_colorspace_property);\n+\n+/**\n  * drm_connector_atomic_hdr_metadata_equal - checks if the hdr metadata changed\n  * @old_state: old connector state to compare\n  * @new_state: new connector state to compare\n--- a/drivers/gpu/drm/i915/display/intel_connector.c\n+++ b/drivers/gpu/drm/i915/display/intel_connector.c\n@@ -297,6 +297,5 @@ intel_attach_colorspace_property(struct\n \t\treturn;\n \t}\n \n-\tdrm_object_attach_property(&connector->base,\n-\t\t\t\t   connector->colorspace_property, 0);\n+\tdrm_connector_attach_colorspace_property(connector);\n }\n--- a/include/drm/drm_connector.h\n+++ b/include/drm/drm_connector.h\n@@ -1622,6 +1622,7 @@ int drm_connector_attach_scaling_mode_pr\n \t\t\t\t\t       u32 scaling_mode_mask);\n int drm_connector_attach_vrr_capable_property(\n \t\tstruct drm_connector *connector);\n+int drm_connector_attach_colorspace_property(struct drm_connector *connector);\n int drm_connector_attach_hdr_output_metadata_property(struct drm_connector *connector);\n bool drm_connector_atomic_hdr_metadata_equal(struct drm_connector_state *old_state,\n \t\t\t\t\t     struct drm_connector_state *new_state);\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0531-drm-vc4-hdmi-Signal-the-proper-colorimetry-info-in-t.patch",
    "content": "From c1e98dfad80bdb512cd04c9ed5d989a5f0f6b13d Mon Sep 17 00:00:00 2001\nFrom: Maxime Ripard <maxime@cerno.tech>\nDate: Fri, 9 Apr 2021 17:16:42 +0200\nSubject: [PATCH] drm/vc4: hdmi: Signal the proper colorimetry info in\n the infoframe\n\nOur driver while supporting HDR didn't send the proper colorimetry info\nin the AVI infoframe.\n\nLet's add the property needed so that the userspace can let us know what\nthe colorspace is supposed to be.\n\nSigned-off-by: Maxime Ripard <maxime@cerno.tech>\n---\n drivers/gpu/drm/vc4/vc4_hdmi.c | 10 ++++++++--\n 1 file changed, 8 insertions(+), 2 deletions(-)\n\n--- a/drivers/gpu/drm/vc4/vc4_hdmi.c\n+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c\n@@ -236,7 +236,8 @@ static int vc4_hdmi_connector_atomic_che\n \tif (!crtc)\n \t\treturn 0;\n \n-\tif (!drm_connector_atomic_hdr_metadata_equal(old_state, new_state)) {\n+\tif (old_state->colorspace != new_state->colorspace ||\n+\t    !drm_connector_atomic_hdr_metadata_equal(old_state, new_state)) {\n \t\tstruct drm_crtc_state *crtc_state;\n \n \t\tcrtc_state = drm_atomic_get_crtc_state(state, crtc);\n@@ -326,6 +327,11 @@ static int vc4_hdmi_connector_init(struc\n \tif (ret)\n \t\treturn ret;\n \n+\tret = drm_mode_create_hdmi_colorspace_property(connector);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tdrm_connector_attach_colorspace_property(connector);\n \tdrm_connector_attach_tv_margin_properties(connector);\n \tdrm_connector_attach_max_bpc_property(connector, 8, 12);\n \n@@ -440,7 +446,7 @@ static void vc4_hdmi_set_avi_infoframe(s\n \t\t\t\t\t   vc4_encoder->limited_rgb_range ?\n \t\t\t\t\t   HDMI_QUANTIZATION_RANGE_LIMITED :\n \t\t\t\t\t   HDMI_QUANTIZATION_RANGE_FULL);\n-\n+\tdrm_hdmi_avi_infoframe_colorspace(&frame.avi, cstate);\n \tdrm_hdmi_avi_infoframe_bars(&frame.avi, cstate);\n \n \tvc4_hdmi_write_infoframe(encoder, &frame);\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0532-staging-vcsm-cma-Fix-memory-leak-from-not-detaching-.patch",
    "content": "From db7b984f1957e5a26775a62a78e60df3f2da671f Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Wed, 4 Nov 2020 18:54:20 +0000\nSubject: [PATCH] staging: vcsm-cma: Fix memory leak from not detaching\n dmabuf\n\nWhen importing there was a missing call to detach the buffer,\nso each import leaked the sg table entry.\n\nActually the release process for both locally allocated and\nimported buffers is identical, so fix them to both use the same\nfunction.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n .../staging/vc04_services/vc-sm-cma/vc_sm.c   | 22 ++-----------------\n 1 file changed, 2 insertions(+), 20 deletions(-)\n\n--- a/drivers/staging/vc04_services/vc-sm-cma/vc_sm.c\n+++ b/drivers/staging/vc04_services/vc-sm-cma/vc_sm.c\n@@ -237,6 +237,7 @@ static void vc_sm_add_resource(struct vc\n \n /*\n  * Cleans up imported dmabuf.\n+ * Should be called with mutex held.\n  */\n static void vc_sm_clean_up_dmabuf(struct vc_sm_buffer *buffer)\n {\n@@ -244,7 +245,6 @@ static void vc_sm_clean_up_dmabuf(struct\n \t\treturn;\n \n \t/* Handle cleaning up imported dmabufs */\n-\tmutex_lock(&buffer->lock);\n \tif (buffer->import.sgt) {\n \t\tdma_buf_unmap_attachment(buffer->import.attach,\n \t\t\t\t\t buffer->import.sgt,\n@@ -255,7 +255,6 @@ static void vc_sm_clean_up_dmabuf(struct\n \t\tdma_buf_detach(buffer->dma_buf, buffer->import.attach);\n \t\tbuffer->import.attach = NULL;\n \t}\n-\tmutex_unlock(&buffer->lock);\n }\n \n /*\n@@ -673,23 +672,6 @@ int vc_sm_import_dmabuf_mmap(struct dma_\n }\n \n static\n-void vc_sm_import_dma_buf_release(struct dma_buf *dmabuf)\n-{\n-\tstruct vc_sm_buffer *buf = dmabuf->priv;\n-\n-\tpr_debug(\"%s: Relasing dma_buf %p\\n\", __func__, dmabuf);\n-\tmutex_lock(&buf->lock);\n-\tif (!buf->imported)\n-\t\treturn;\n-\n-\tbuf->in_use = 0;\n-\n-\tvc_sm_vpu_free(buf);\n-\n-\tvc_sm_release_resource(buf);\n-}\n-\n-static\n int vc_sm_import_dma_buf_begin_cpu_access(struct dma_buf *dmabuf,\n \t\t\t\t\t  enum dma_data_direction direction)\n {\n@@ -717,7 +699,7 @@ static const struct dma_buf_ops dma_buf_\n \t.map_dma_buf = vc_sm_import_map_dma_buf,\n \t.unmap_dma_buf = vc_sm_import_unmap_dma_buf,\n \t.mmap = vc_sm_import_dmabuf_mmap,\n-\t.release = vc_sm_import_dma_buf_release,\n+\t.release = vc_sm_dma_buf_release,\n \t.attach = vc_sm_import_dma_buf_attach,\n \t.detach = vc_sm_import_dma_buf_detatch,\n \t.begin_cpu_access = vc_sm_import_dma_buf_begin_cpu_access,\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0533-vc4-kms-vc4_plane-Support-2020-colourspace-for-yuv-p.patch",
    "content": "From f5c7dd20b383a4ab8212736b37940a4339d80e33 Mon Sep 17 00:00:00 2001\nFrom: Dom Cobley <popcornmix@gmail.com>\nDate: Mon, 12 Apr 2021 17:27:43 +0100\nSubject: [PATCH] vc4/kms: vc4_plane: Support 2020 colourspace for yuv\n planes\n\nhttps://gist.github.com/popcornmix/6b3e23103c60170b02b148e0ba5d6ed7\n\nis the script used to generate the 601, 709 and 2020 colourspaces.\nI've regenetated the existing ones using script so it is reprocable\nbut there are lsb dfferences compared to values here (copied from spec)\nwhose origin is now lost.\n\nSigned-off-by: Dom Cobley <popcornmix@gmail.com>\n---\n drivers/gpu/drm/vc4/vc4_plane.c | 19 ++++++++++---------\n drivers/gpu/drm/vc4/vc4_regs.h  | 18 ++++++++++++------\n 2 files changed, 22 insertions(+), 15 deletions(-)\n\n--- a/drivers/gpu/drm/vc4/vc4_plane.c\n+++ b/drivers/gpu/drm/vc4/vc4_plane.c\n@@ -644,10 +644,10 @@ static const u32 colorspace_coeffs[2][DR\n \t\t\tSCALER_CSC1_ITR_R_709_3,\n \t\t\tSCALER_CSC2_ITR_R_709_3,\n \t\t}, {\n-\t\t\t/* BT2020. Not supported yet - copy 601 */\n-\t\t\tSCALER_CSC0_ITR_R_601_5,\n-\t\t\tSCALER_CSC1_ITR_R_601_5,\n-\t\t\tSCALER_CSC2_ITR_R_601_5,\n+\t\t\t/* BT2020 */\n+\t\t\tSCALER_CSC0_ITR_R_2020,\n+\t\t\tSCALER_CSC1_ITR_R_2020,\n+\t\t\tSCALER_CSC2_ITR_R_2020,\n \t\t}\n \t}, {\n \t\t/* Full range */\n@@ -662,10 +662,10 @@ static const u32 colorspace_coeffs[2][DR\n \t\t\tSCALER_CSC1_ITR_R_709_3_FR,\n \t\t\tSCALER_CSC2_ITR_R_709_3_FR,\n \t\t}, {\n-\t\t\t/* BT2020. Not supported yet - copy JFIF */\n-\t\t\tSCALER_CSC0_JPEG_JFIF,\n-\t\t\tSCALER_CSC1_JPEG_JFIF,\n-\t\t\tSCALER_CSC2_JPEG_JFIF,\n+\t\t\t/* BT2020 */\n+\t\t\tSCALER_CSC0_ITR_R_2020_FR,\n+\t\t\tSCALER_CSC1_ITR_R_2020_FR,\n+\t\t\tSCALER_CSC2_ITR_R_2020_FR,\n \t\t}\n \t}\n };\n@@ -1487,7 +1487,8 @@ struct drm_plane *vc4_plane_init(struct\n \n \tdrm_plane_create_color_properties(plane,\n \t\t\t\t\t  BIT(DRM_COLOR_YCBCR_BT601) |\n-\t\t\t\t\t  BIT(DRM_COLOR_YCBCR_BT709),\n+\t\t\t\t\t  BIT(DRM_COLOR_YCBCR_BT709) |\n+\t\t\t\t\t  BIT(DRM_COLOR_YCBCR_BT2020),\n \t\t\t\t\t  BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) |\n \t\t\t\t\t  BIT(DRM_COLOR_YCBCR_FULL_RANGE),\n \t\t\t\t\t  DRM_COLOR_YCBCR_BT709,\n--- a/drivers/gpu/drm/vc4/vc4_regs.h\n+++ b/drivers/gpu/drm/vc4/vc4_regs.h\n@@ -975,8 +975,10 @@ enum hvs_pixel_format {\n #define SCALER_CSC0_COEF_CR_OFS_SHIFT\t\t0\n #define SCALER_CSC0_ITR_R_601_5\t\t\t0x00f00000\n #define SCALER_CSC0_ITR_R_709_3\t\t\t0x00f00000\n+#define SCALER_CSC0_ITR_R_2020\t\t\t0x00f00000\n #define SCALER_CSC0_JPEG_JFIF\t\t\t0x00000000\n #define SCALER_CSC0_ITR_R_709_3_FR\t\t0x00000000\n+#define SCALER_CSC0_ITR_R_2020_FR\t\t0x00000000\n \n /* S2.8 contribution of Cb to Green */\n #define SCALER_CSC1_COEF_CB_GRN_MASK\t\tVC4_MASK(31, 22)\n@@ -991,9 +993,11 @@ enum hvs_pixel_format {\n #define SCALER_CSC1_COEF_CR_BLU_MASK\t\tVC4_MASK(1, 0)\n #define SCALER_CSC1_COEF_CR_BLU_SHIFT\t\t0\n #define SCALER_CSC1_ITR_R_601_5\t\t\t0xe73304a8\n-#define SCALER_CSC1_ITR_R_709_3\t\t\t0xf2b784a8\n-#define SCALER_CSC1_JPEG_JFIF\t\t\t0xea34a400\n-#define SCALER_CSC1_ITR_R_709_3_FR\t\t0xe23d0400\n+#define SCALER_CSC1_ITR_R_709_3\t\t\t0xf27784a8\n+#define SCALER_CSC1_ITR_R_2020\t\t\t0xf43594a8\n+#define SCALER_CSC1_JPEG_JFIF\t\t\t0xea349400\n+#define SCALER_CSC1_ITR_R_709_3_FR\t\t0xf4388400\n+#define SCALER_CSC1_ITR_R_2020_FR\t\t0xf5b6d400\n \n /* S2.8 contribution of Cb to Red */\n #define SCALER_CSC2_COEF_CB_RED_MASK\t\tVC4_MASK(29, 20)\n@@ -1004,10 +1008,12 @@ enum hvs_pixel_format {\n /* S2.8 contribution of Cb to Blue */\n #define SCALER_CSC2_COEF_CB_BLU_MASK\t\tVC4_MASK(19, 10)\n #define SCALER_CSC2_COEF_CB_BLU_SHIFT\t\t10\n-#define SCALER_CSC2_ITR_R_601_5\t\t\t0x00066204\n-#define SCALER_CSC2_ITR_R_709_3\t\t\t0x00072a1c\n-#define SCALER_CSC2_JPEG_JFIF\t\t\t0x000599c5\n+#define SCALER_CSC2_ITR_R_601_5\t\t\t0x00066604\n+#define SCALER_CSC2_ITR_R_709_3\t\t\t0x00072e1d\n+#define SCALER_CSC2_ITR_R_2020\t\t\t0x0006b624\n+#define SCALER_CSC2_JPEG_JFIF\t\t\t0x00059dc6\n #define SCALER_CSC2_ITR_R_709_3_FR\t\t0x00064ddb\n+#define SCALER_CSC2_ITR_R_2020_FR\t\t0x0005e5e2\n \n #define SCALER_TPZ0_VERT_RECALC\t\t\tBIT(31)\n #define SCALER_TPZ0_SCALE_MASK\t\t\tVC4_MASK(28, 8)\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0534-sound-usb-add-device-quirks-for-A4Tech-FHD-1080p-web.patch",
    "content": "From 42fbd61f4775d9ec9e7a1d1833565a45581efb27 Mon Sep 17 00:00:00 2001\nFrom: Jonathan Bell <jonathan@raspberrypi.com>\nDate: Thu, 15 Apr 2021 13:15:14 +0100\nSubject: [PATCH] sound/usb: add device quirks for A4Tech FHD 1080p\n webcams\n\nThese devices use a type of Sonix chipset that produces broken microphone\ndata if suspended/resumed.\n\nThey also don't support readback of the sample rate.\n\nSigned-off-by: Jonathan Bell <jonathan@raspberrypi.com>\n---\n sound/usb/quirks-table.h | 9 +++++++++\n sound/usb/quirks.c       | 1 +\n 2 files changed, 10 insertions(+)\n\n--- a/sound/usb/quirks-table.h\n+++ b/sound/usb/quirks-table.h\n@@ -47,6 +47,15 @@\n },\n \n {\n+\t/* A4Tech FHD 1080p webcam */\n+\tUSB_DEVICE(0x09da, 0x2695),\n+\t.driver_info = (unsigned long) &(const struct snd_usb_audio_quirk) {\n+\t\t.ifnum = QUIRK_ANY_INTERFACE,\n+\t\t.type = QUIRK_SETUP_DISABLE_AUTOSUSPEND\n+\t}\n+},\n+\n+{\n \t/* Creative BT-D1 */\n \tUSB_DEVICE(0x041e, 0x0005),\n \t.driver_info = (unsigned long) &(const struct snd_usb_audio_quirk) {\n--- a/sound/usb/quirks.c\n+++ b/sound/usb/quirks.c\n@@ -1530,6 +1530,7 @@ bool snd_usb_get_sample_rate_quirk(struc\n \tcase USB_ID(0x2912, 0x30c8): /* Audioengine D1 */\n \tcase USB_ID(0x413c, 0xa506): /* Dell AE515 sound bar */\n \tcase USB_ID(0x046d, 0x084c): /* Logitech ConferenceCam Connect */\n+\tcase USB_ID(0x09da, 0x2695): /* A4Tech FHD 1080p webcam */\n \t\treturn true;\n \t}\n \n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0535-sound-usb-call-usb_autopm_get_interface-for-devices-.patch",
    "content": "From ec43e93b7e36e2baa6685da504b9db3ac7048ceb Mon Sep 17 00:00:00 2001\nFrom: Jonathan Bell <jonathan@raspberrypi.com>\nDate: Fri, 16 Apr 2021 11:40:23 +0100\nSubject: [PATCH] sound/usb: call usb_autopm_get_interface() for\n devices that should not be suspended\n\nWebcams with microphones are composite devices, and autosuspend is set\nat the device level. If uvcvideo is probed after snd-usb-audio, the effect\nof the quirk applied by snd-usb-audio is undone by uvcvideo's global\napplication of autosuspend.\n\nIncrementing the interface's PM refcount in such cases prevents runtime PM\nfrom happening, thus the device is left active.\n\nSigned-off-by: Jonathan Bell <jonathan@raspberrypi.com>\n---\n sound/usb/quirks.c | 5 +++++\n 1 file changed, 5 insertions(+)\n\n--- a/sound/usb/quirks.c\n+++ b/sound/usb/quirks.c\n@@ -531,6 +531,11 @@ static int setup_disable_autosuspend(str\n \t\t\t\t       struct usb_driver *driver,\n \t\t\t\t       const struct snd_usb_audio_quirk *quirk)\n {\n+\t/*\n+\t * Grab the interface, because on a webcam uvcvideo may race\n+\t * with snd-usb-audio during probe and re-enable autosuspend.\n+\t */\n+\tusb_autopm_get_interface(iface);\n \tusb_disable_autosuspend(interface_to_usbdev(iface));\n \treturn 1;\t/* Continue with creating streams and mixer */\n }\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0536-overlays-ghost-amp-Add-DAC-mute-control.patch",
    "content": "From e56470876bda3751a1926aa5876495e3678e363f Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.com>\nDate: Fri, 16 Apr 2021 09:31:17 +0100\nSubject: [PATCH] overlays: ghost-amp: Add DAC mute control\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.com>\n---\n .../boot/dts/overlays/ghost-amp-overlay.dts   | 28 +++++++++++--------\n 1 file changed, 17 insertions(+), 11 deletions(-)\n\n--- a/arch/arm/boot/dts/overlays/ghost-amp-overlay.dts\n+++ b/arch/arm/boot/dts/overlays/ghost-amp-overlay.dts\n@@ -4,10 +4,11 @@\n \n #include <dt-bindings/gpio/gpio-fsm.h>\n \n-#define ENABLE GF_SW(0)\n-#define FAULT  GF_IP(0) // GPIO5\n-#define RELAY1 GF_OP(0) // GPIO22\n-#define RELAY2 GF_OP(1) // GPIO23\n+#define ENABLE   GF_SW(0)\n+#define FAULT    GF_IP(0) // GPIO5\n+#define RELAY1   GF_OP(0) // GPIO22\n+#define RELAY2   GF_OP(1) // GPIO23\n+#define RELAYSSR GF_OP(2) // GPIO24\n \n / {\n \tcompatible = \"brcm,bcm2835\";\n@@ -64,14 +65,16 @@\n \t\t\t\tgpio-line-names = \"enable\";\n \t\t\t\tinput-gpios  = <&gpio 5 1>;  // FAULT (active low)\n \t\t\t\toutput-gpios = <&gpio 22 0>, // RELAY1\n-\t\t\t\t\t       <&gpio 23 0>; // RELAY2\n+\t\t\t\t\t       <&gpio 23 0>, // RELAY2\n+\t\t\t\t\t       <&gpio 24 0>; // RELAYSSR\n \t\t\t\tshutdown-timeout-ms = <1000>;\n \n \t\t\t\tamp_off {\n \t\t\t\t\tstart_state;\n \t\t\t\t\tshutdown_state;\n \n-\t\t\t\t\tset = <RELAY2 0>,\n+\t\t\t\t\tset = <RELAYSSR 0>,\n+\t\t\t\t\t      <RELAY2 0>,\n \t\t\t\t\t      <RELAY1 0>;\n \t\t\t\t\tamp_on_1 = <ENABLE 1>;\n \t\t\t\t\tfault = <FAULT 1>;\n@@ -85,12 +88,14 @@\n \t\t\t\t};\n \n \t\t\t\tamp_on {\n-\t\t\t\t\tset = <RELAY2 1>;\n+\t\t\t\t\tset = <RELAY2 1>,\n+\t\t\t\t\t      <RELAYSSR 1>;\n \t\t\t\t\tamp_on_wait = <ENABLE 0>;\n \t\t\t\t\tfault = <FAULT 1>;\n \t\t\t\t};\n \n \t\t\t\tamp_on_wait {\n+\t\t\t\t\tset = <RELAYSSR 0>;\n \t\t\t\t\tamp_off_1 = <GF_DELAY (30*60*1000)>,\n \t\t\t\t\t\t    <GF_SHUTDOWN 0>;\n \t\t\t\t\tamp_on = <ENABLE 1>;\n@@ -107,7 +112,8 @@\n \t\t\t\t// Keep this a distinct state to prevent\n \t\t\t\t// changes and for the diagnostic output\n \t\t\t\tfault {\n-\t\t\t\t\tset = <RELAY2 0>,\n+\t\t\t\t\tset = <RELAYSSR 0>,\n+\t\t\t\t\t      <RELAY2 0>,\n \t\t\t\t\t      <RELAY1 0>;\n \t\t\t\t\tamp_off = <FAULT 0>;\n \t\t\t\t\tshutdown_state;\n@@ -120,9 +126,9 @@\n \t\ttarget = <&gpio>;\n \t\t__overlay__ {\n \t\t\tghost_amp_pins: ghost_amp_pins {\n-\t\t\t\tbrcm,pins = <5 22 23>;\n-\t\t\t\tbrcm,function = <0 1 1>; /* in out out */\n-\t\t\t\tbrcm,pull = <2 0 0>; /* up none none */\n+\t\t\t\tbrcm,pins = <5 22 23 24>;\n+\t\t\t\tbrcm,function = <0 1 1 1>; /* in out out out */\n+\t\t\t\tbrcm,pull = <2 0 0 0>; /* up none none none */\n \t\t\t};\n \t\t};\n \t};\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0537-clk-Introduce-a-clock-request-API.patch",
    "content": "From d937a5c25139dd919d857a8e4a6491917b568176 Mon Sep 17 00:00:00 2001\nFrom: Maxime Ripard <maxime@cerno.tech>\nDate: Tue, 13 Apr 2021 11:00:01 +0200\nSubject: [PATCH] clk: Introduce a clock request API\n\nIt's not unusual to find clocks being shared across multiple devices\nthat need to change the rate depending on what the device is doing at a\ngiven time.\n\nThe SoC found on the RaspberryPi4 (BCM2711) is in such a situation\nbetween its two HDMI controllers that share a clock that needs to be\nraised depending on the output resolution of each controller.\n\nThe current clk_set_rate API doesn't really allow to support that case\nsince there's really no synchronisation between multiple users, it's\nessentially a fire-and-forget solution.\n\nclk_set_min_rate does allow for such a synchronisation, but has another\ndrawback: it doesn't allow to reduce the clock rate once the work is\nover.\n\nIn our previous example, this means that if we were to raise the\nresolution of one HDMI controller to the largest resolution and then\nchanging for a smaller one, we would still have the clock running at the\nlargest resolution rate resulting in a poor power-efficiency.\n\nIn order to address both issues, let's create an API that allows user to\ncreate temporary requests to increase the rate to a minimum, before\ngoing back to the initial rate once the request is done.\n\nThis introduces mainly two side-effects:\n\n  * There's an interaction between clk_set_rate and requests. This has\n    been addressed by having clk_set_rate increasing the rate if it's\n    greater than what the requests asked for, and in any case changing\n    the rate the clock will return to once all the requests are done.\n\n  * Similarly, clk_round_rate has been adjusted to take the requests\n    into account and return a rate that will be greater or equal to the\n    requested rates.\n\nSigned-off-by: Maxime Ripard <maxime@cerno.tech>\n---\n drivers/clk/clk.c   | 121 ++++++++++++++++++++++++++++++++++++++++++++\n include/linux/clk.h |   4 ++\n 2 files changed, 125 insertions(+)\n\n--- a/drivers/clk/clk.c\n+++ b/drivers/clk/clk.c\n@@ -77,12 +77,14 @@ struct clk_core {\n \tunsigned int\t\tprotect_count;\n \tunsigned long\t\tmin_rate;\n \tunsigned long\t\tmax_rate;\n+\tunsigned long\t\tdefault_request_rate;\n \tunsigned long\t\taccuracy;\n \tint\t\t\tphase;\n \tstruct clk_duty\t\tduty;\n \tstruct hlist_head\tchildren;\n \tstruct hlist_node\tchild_node;\n \tstruct hlist_head\tclks;\n+\tstruct list_head\tpending_requests;\n \tunsigned int\t\tnotifier_count;\n #ifdef CONFIG_DEBUG_FS\n \tstruct dentry\t\t*dentry;\n@@ -105,6 +107,12 @@ struct clk {\n \tstruct hlist_node clks_node;\n };\n \n+struct clk_request {\n+\tstruct list_head list;\n+\tstruct clk *clk;\n+\tunsigned long rate;\n+};\n+\n /***           runtime pm          ***/\n static int clk_pm_runtime_get(struct clk_core *core)\n {\n@@ -1431,10 +1439,14 @@ unsigned long clk_hw_round_rate(struct c\n {\n \tint ret;\n \tstruct clk_rate_request req;\n+\tstruct clk_request *clk_req;\n \n \tclk_core_get_boundaries(hw->core, &req.min_rate, &req.max_rate);\n \treq.rate = rate;\n \n+\tlist_for_each_entry(clk_req, &hw->core->pending_requests, list)\n+\t\treq.min_rate = max(clk_req->rate, req.min_rate);\n+\n \tret = clk_core_round_rate_nolock(hw->core, &req);\n \tif (ret)\n \t\treturn 0;\n@@ -1455,6 +1467,7 @@ EXPORT_SYMBOL_GPL(clk_hw_round_rate);\n long clk_round_rate(struct clk *clk, unsigned long rate)\n {\n \tstruct clk_rate_request req;\n+\tstruct clk_request *clk_req;\n \tint ret;\n \n \tif (!clk)\n@@ -1468,6 +1481,9 @@ long clk_round_rate(struct clk *clk, uns\n \tclk_core_get_boundaries(clk->core, &req.min_rate, &req.max_rate);\n \treq.rate = rate;\n \n+\tlist_for_each_entry(clk_req, &clk->core->pending_requests, list)\n+\t\treq.min_rate = max(clk_req->rate, req.min_rate);\n+\n \tret = clk_core_round_rate_nolock(clk->core, &req);\n \n \tif (clk->exclusive_count)\n@@ -1935,6 +1951,7 @@ static struct clk_core *clk_calc_new_rat\n \tunsigned long new_rate;\n \tunsigned long min_rate;\n \tunsigned long max_rate;\n+\tstruct clk_request *req;\n \tint p_index = 0;\n \tlong ret;\n \n@@ -1949,6 +1966,9 @@ static struct clk_core *clk_calc_new_rat\n \n \tclk_core_get_boundaries(core, &min_rate, &max_rate);\n \n+\tlist_for_each_entry(req, &core->pending_requests, list)\n+\t\tmin_rate = max(req->rate, min_rate);\n+\n \t/* find the closest rate and parent clk/rate */\n \tif (clk_core_can_round(core)) {\n \t\tstruct clk_rate_request req;\n@@ -2153,6 +2173,7 @@ static unsigned long clk_core_req_round_\n {\n \tint ret, cnt;\n \tstruct clk_rate_request req;\n+\tstruct clk_request *clk_req;\n \n \tlockdep_assert_held(&prepare_lock);\n \n@@ -2167,6 +2188,9 @@ static unsigned long clk_core_req_round_\n \tclk_core_get_boundaries(core, &req.min_rate, &req.max_rate);\n \treq.rate = req_rate;\n \n+\tlist_for_each_entry(clk_req, &core->pending_requests, list)\n+\t\treq.min_rate = max(clk_req->rate, req.min_rate);\n+\n \tret = clk_core_round_rate_nolock(core, &req);\n \n \t/* restore the protection */\n@@ -2260,6 +2284,9 @@ int clk_set_rate(struct clk *clk, unsign\n \n \tret = clk_core_set_rate_nolock(clk->core, rate);\n \n+\tif (!list_empty(&clk->core->pending_requests))\n+\t\tclk->core->default_request_rate = rate;\n+\n \tif (clk->exclusive_count)\n \t\tclk_core_rate_protect(clk->core);\n \n@@ -2426,6 +2453,99 @@ int clk_set_max_rate(struct clk *clk, un\n EXPORT_SYMBOL_GPL(clk_set_max_rate);\n \n /**\n+ * clk_request_start - Request a rate to be enforced temporarily\n+ * @clk: the clk to act on\n+ * @rate: the new rate asked for\n+ *\n+ * This function will create a request to temporarily increase the rate\n+ * of the clock to a given rate to a certain minimum.\n+ *\n+ * This is meant as a best effort mechanism and while the rate of the\n+ * clock will be guaranteed to be equal or higher than the requested\n+ * rate, there's none on what the actual rate will be due to other\n+ * factors (other requests previously set, clock boundaries, etc.).\n+ *\n+ * Once the request is marked as done through clk_request_done(), the\n+ * rate will be reverted back to what the rate was before the request.\n+ *\n+ * The reported boundaries of the clock will also be adjusted so that\n+ * clk_round_rate() take those requests into account. A call to\n+ * clk_set_rate() during a request will affect the rate the clock will\n+ * return to after the requests on that clock are done.\n+ *\n+ * Returns 0 on success, an ERR_PTR otherwise.\n+ */\n+struct clk_request *clk_request_start(struct clk *clk, unsigned long rate)\n+{\n+\tstruct clk_request *req;\n+\tint ret;\n+\n+\tif (!clk)\n+\t\treturn ERR_PTR(-EINVAL);\n+\n+\treq = kzalloc(sizeof(*req), GFP_KERNEL);\n+\tif (!req)\n+\t\treturn ERR_PTR(-ENOMEM);\n+\n+\tclk_prepare_lock();\n+\n+\treq->clk = clk;\n+\treq->rate = rate;\n+\n+\tif (list_empty(&clk->core->pending_requests))\n+\t\tclk->core->default_request_rate = clk_core_get_rate_recalc(clk->core);\n+\n+\tret = clk_core_set_rate_nolock(clk->core, rate);\n+\tif (ret) {\n+\t\tclk_prepare_unlock();\n+\t\tkfree(req);\n+\t\treturn ERR_PTR(ret);\n+\t}\n+\n+\tlist_add_tail(&req->list, &clk->core->pending_requests);\n+\tclk_prepare_unlock();\n+\n+\treturn req;\n+}\n+EXPORT_SYMBOL_GPL(clk_request_start);\n+\n+/**\n+ * clk_request_done - Mark a clk_request as done\n+ * @req: the request to mark done\n+ *\n+ * This function will remove the rate request from the clock and adjust\n+ * the clock rate back to either to what it was before the request\n+ * started, or if there's any other request on that clock to a proper\n+ * rate for them.\n+ */\n+void clk_request_done(struct clk_request *req)\n+{\n+\tstruct clk_core *core = req->clk->core;\n+\n+\tclk_prepare_lock();\n+\n+\tlist_del(&req->list);\n+\n+\tif (list_empty(&core->pending_requests)) {\n+\t\tclk_core_set_rate_nolock(core, core->default_request_rate);\n+\t\tcore->default_request_rate = 0;\n+\t} else {\n+\t\tstruct clk_request *cur_req;\n+\t\tunsigned long new_rate = 0;\n+\n+\t\tlist_for_each_entry(cur_req, &core->pending_requests, list)\n+\t\t\tnew_rate = max(new_rate, cur_req->rate);\n+\n+\t\tclk_core_set_rate_nolock(core, new_rate);\n+\t}\n+\n+\tclk_prepare_unlock();\n+\n+\tkfree(req);\n+}\n+EXPORT_SYMBOL_GPL(clk_request_done);\n+\n+/**\n  * clk_get_parent - return the parent of a clk\n  * @clk: the clk whose parent gets returned\n  *\n@@ -3875,6 +3995,7 @@ __clk_register(struct device *dev, struc\n \t\tgoto fail_parents;\n \n \tINIT_HLIST_HEAD(&core->clks);\n+\tINIT_LIST_HEAD(&core->pending_requests);\n \n \t/*\n \t * Don't call clk_hw_create_clk() here because that would pin the\n--- a/include/linux/clk.h\n+++ b/include/linux/clk.h\n@@ -15,6 +15,7 @@\n \n struct device;\n struct clk;\n+struct clk_request;\n struct device_node;\n struct of_phandle_args;\n \n@@ -743,6 +744,9 @@ int clk_save_context(void);\n  */\n void clk_restore_context(void);\n \n+struct clk_request *clk_request_start(struct clk *clk, unsigned long rate);\n+void clk_request_done(struct clk_request *req);\n+\n #else /* !CONFIG_HAVE_CLK */\n \n static inline struct clk *clk_get(struct device *dev, const char *id)\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0538-drm-vc4-hdmi-Convert-to-the-new-clock-request-API.patch",
    "content": "From fe77a92b9018f9a2dbab0e2a600e368d55c667b0 Mon Sep 17 00:00:00 2001\nFrom: Maxime Ripard <maxime@cerno.tech>\nDate: Tue, 13 Apr 2021 11:55:55 +0200\nSubject: [PATCH] drm/vc4: hdmi: Convert to the new clock request API\n\nThe new clock request API allows us to increase the rate of the HSM\nclock to match our pixel rate requirements while decreasing it when\nwe're done, resulting in a better power-efficiency.\n\nSigned-off-by: Maxime Ripard <maxime@cerno.tech>\n---\n drivers/gpu/drm/vc4/vc4_hdmi.c | 22 +++++++++++++++-------\n drivers/gpu/drm/vc4/vc4_hdmi.h |  3 +++\n 2 files changed, 18 insertions(+), 7 deletions(-)\n\n--- a/drivers/gpu/drm/vc4/vc4_hdmi.c\n+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c\n@@ -546,6 +546,9 @@ static void vc4_hdmi_encoder_post_crtc_p\n \t\t   HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE);\n \n \tclk_disable_unprepare(vc4_hdmi->pixel_bvb_clock);\n+\tclk_request_done(vc4_hdmi->bvb_req);\n+\tclk_disable_unprepare(vc4_hdmi->hsm_clock);\n+\tclk_request_done(vc4_hdmi->hsm_req);\n \tclk_disable_unprepare(vc4_hdmi->pixel_clock);\n \n \tret = pm_runtime_put(&vc4_hdmi->pdev->dev);\n@@ -850,9 +853,9 @@ static void vc4_hdmi_encoder_pre_crtc_co\n \t * pixel clock, but HSM ends up being the limiting factor.\n \t */\n \thsm_rate = max_t(unsigned long, 120000000, (pixel_rate / 100) * 101);\n-\tret = clk_set_min_rate(vc4_hdmi->hsm_clock, hsm_rate);\n-\tif (ret) {\n-\t\tDRM_ERROR(\"Failed to set HSM clock rate: %d\\n\", ret);\n+\tvc4_hdmi->hsm_req = clk_request_start(vc4_hdmi->hsm_clock, hsm_rate);\n+\tif (IS_ERR(vc4_hdmi->hsm_req)) {\n+\t\tDRM_ERROR(\"Failed to set HSM clock rate: %ld\\n\", PTR_ERR(vc4_hdmi->hsm_req));\n \t\treturn;\n \t}\n \n@@ -864,10 +867,12 @@ static void vc4_hdmi_encoder_pre_crtc_co\n \t * FIXME: When the pixel freq is 594MHz (4k60), this needs to be setup\n \t * at 300MHz.\n \t */\n-\tret = clk_set_min_rate(vc4_hdmi->pixel_bvb_clock,\n-\t\t\t       (hsm_rate > VC4_HSM_MID_CLOCK ? 150000000 : 75000000));\n-\tif (ret) {\n-\t\tDRM_ERROR(\"Failed to set pixel bvb clock rate: %d\\n\", ret);\n+\tvc4_hdmi->bvb_req = clk_request_start(vc4_hdmi->pixel_bvb_clock,\n+\t\t\t\t\t      (hsm_rate > VC4_HSM_MID_CLOCK ? 150000000 : 75000000));\n+\tif (IS_ERR(vc4_hdmi->bvb_req)) {\n+\t\tDRM_ERROR(\"Failed to set pixel bvb clock rate: %ld\\n\", PTR_ERR(vc4_hdmi->bvb_req));\n+\t\tclk_request_done(vc4_hdmi->hsm_req);\n+\t\tclk_disable_unprepare(vc4_hdmi->hsm_clock);\n \t\tclk_disable_unprepare(vc4_hdmi->pixel_clock);\n \t\treturn;\n \t}\n@@ -875,6 +880,9 @@ static void vc4_hdmi_encoder_pre_crtc_co\n \tret = clk_prepare_enable(vc4_hdmi->pixel_bvb_clock);\n \tif (ret) {\n \t\tDRM_ERROR(\"Failed to turn on pixel bvb clock: %d\\n\", ret);\n+\t\tclk_request_done(vc4_hdmi->bvb_req);\n+\t\tclk_request_done(vc4_hdmi->hsm_req);\n+\t\tclk_disable_unprepare(vc4_hdmi->hsm_clock);\n \t\tclk_disable_unprepare(vc4_hdmi->pixel_clock);\n \t\treturn;\n \t}\n--- a/drivers/gpu/drm/vc4/vc4_hdmi.h\n+++ b/drivers/gpu/drm/vc4/vc4_hdmi.h\n@@ -172,6 +172,9 @@ struct vc4_hdmi {\n \n \tstruct reset_control *reset;\n \n+\tstruct clk_request *bvb_req;\n+\tstruct clk_request *hsm_req;\n+\n \t/* Common debugfs regset */\n \tstruct debugfs_regset32 hdmi_regset;\n \tstruct debugfs_regset32 hd_regset;\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0539-drm-vc4-hdmi-Convert-to-the-new-clock-request-API.patch",
    "content": "From ccc2fa16de3fef192885831595a168a36bfdd842 Mon Sep 17 00:00:00 2001\nFrom: Dom Cobley <popcornmix@gmail.com>\nDate: Tue, 13 Apr 2021 14:10:03 +0100\nSubject: [PATCH] drm/vc4: hdmi: Convert to the new clock request API\n\nThe new clock request API allows us to increase the rate of the\ncore clock as required during mode set while decreasing it when\nwe're done, resulting in a better power-efficiency.\n\nSigned-off-by: Dom Cobley <popcornmix@gmail.com>\n---\n drivers/gpu/drm/vc4/vc4_kms.c | 5 +++--\n 1 file changed, 3 insertions(+), 2 deletions(-)\n\n--- a/drivers/gpu/drm/vc4/vc4_kms.c\n+++ b/drivers/gpu/drm/vc4/vc4_kms.c\n@@ -313,6 +313,7 @@ vc4_atomic_complete_commit(struct drm_at\n \tstruct vc4_hvs *hvs = vc4->hvs;\n \tstruct drm_crtc_state *new_crtc_state;\n \tstruct drm_crtc *crtc;\n+\tstruct clk_request *core_req;\n \tint i;\n \n \tfor_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {\n@@ -326,7 +327,7 @@ vc4_atomic_complete_commit(struct drm_at\n \t}\n \n \tif (vc4->hvs && vc4->hvs->hvs5)\n-\t\tclk_set_min_rate(hvs->core_clk, 500000000);\n+\t\tcore_req = clk_request_start(hvs->core_clk, 500000000);\n \n \tdrm_atomic_helper_wait_for_fences(dev, state, false);\n \n@@ -358,7 +359,7 @@ vc4_atomic_complete_commit(struct drm_at\n \tdrm_atomic_helper_commit_cleanup_done(state);\n \n \tif (vc4->hvs && vc4->hvs->hvs5)\n-\t\tclk_set_min_rate(hvs->core_clk, 0);\n+\t\tclk_request_done(core_req);\n \n \tdrm_atomic_state_put(state);\n \n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0540-bcm2835-unicam-Switch-to-new-clock-api.patch",
    "content": "From 20d6f2f3e034889bcadb960e6ee4d6822d9dbcd7 Mon Sep 17 00:00:00 2001\nFrom: Dom Cobley <popcornmix@gmail.com>\nDate: Tue, 13 Apr 2021 16:48:35 +0100\nSubject: [PATCH] bcm2835-unicam: Switch to new clock api\n\nSigned-off-by: Dom Cobley <popcornmix@gmail.com>\n---\n drivers/media/platform/bcm2835/bcm2835-unicam.c | 13 ++++++-------\n 1 file changed, 6 insertions(+), 7 deletions(-)\n\n--- a/drivers/media/platform/bcm2835/bcm2835-unicam.c\n+++ b/drivers/media/platform/bcm2835/bcm2835-unicam.c\n@@ -426,6 +426,8 @@ struct unicam_device {\n \tstruct clk *clock;\n \t/* vpu clock handle */\n \tstruct clk *vpu_clock;\n+\t/* vpu clock request */\n+\tstruct clk_request *vpu_req;\n \t/* clock status for error handling */\n \tbool clocks_enabled;\n \t/* V4l2 device */\n@@ -1691,8 +1693,8 @@ static int unicam_start_streaming(struct\n \tunicam_dbg(1, dev, \"Running with %u data lanes\\n\",\n \t\t   dev->active_data_lanes);\n \n-\tret = clk_set_min_rate(dev->vpu_clock, MIN_VPU_CLOCK_RATE);\n-\tif (ret) {\n+\tdev->vpu_req = clk_request_start(dev->vpu_clock, MIN_VPU_CLOCK_RATE);\n+\tif (!dev->vpu_req) {\n \t\tunicam_err(dev, \"failed to set up VPU clock\\n\");\n \t\tgoto err_pm_put;\n \t}\n@@ -1748,8 +1750,7 @@ err_disable_unicam:\n \tunicam_disable(dev);\n \tclk_disable_unprepare(dev->clock);\n err_vpu_clock:\n-\tif (clk_set_min_rate(dev->vpu_clock, 0))\n-\t\tunicam_err(dev, \"failed to reset the VPU clock\\n\");\n+\tclk_request_done(dev->vpu_req);\n \tclk_disable_unprepare(dev->vpu_clock);\n err_pm_put:\n \tunicam_runtime_put(dev);\n@@ -1779,9 +1780,7 @@ static void unicam_stop_streaming(struct\n \t\tunicam_disable(dev);\n \n \t\tif (dev->clocks_enabled) {\n-\t\t\tif (clk_set_min_rate(dev->vpu_clock, 0))\n-\t\t\t\tunicam_err(dev, \"failed to reset the min VPU clock\\n\");\n-\n+\t\t\tclk_request_done(dev->vpu_req);\n \t\t\tclk_disable_unprepare(dev->vpu_clock);\n \t\t\tclk_disable_unprepare(dev->clock);\n \t\t\tdev->clocks_enabled = false;\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0541-rpivid-Switch-to-new-clock-api.patch",
    "content": "From 4ffdf70996826a87fceb78f2399c98e8a4c6aa89 Mon Sep 17 00:00:00 2001\nFrom: Dom Cobley <popcornmix@gmail.com>\nDate: Mon, 19 Apr 2021 19:30:26 +0100\nSubject: [PATCH] rpivid: Switch to new clock api\n\nSigned-off-by: Dom Cobley <popcornmix@gmail.com>\n---\n drivers/staging/media/rpivid/rpivid.h       |  1 +\n drivers/staging/media/rpivid/rpivid_video.c | 11 +++--------\n 2 files changed, 4 insertions(+), 8 deletions(-)\n\n--- a/drivers/staging/media/rpivid/rpivid.h\n+++ b/drivers/staging/media/rpivid/rpivid.h\n@@ -172,6 +172,7 @@ struct rpivid_dev {\n \tvoid __iomem\t\t*base_h265;\n \n \tstruct clk\t\t*clock;\n+\tstruct clk_request      *hevc_req;\n \n \tstruct rpivid_hw_irq_ctrl ic_active1;\n \tstruct rpivid_hw_irq_ctrl ic_active2;\n--- a/drivers/staging/media/rpivid/rpivid_video.c\n+++ b/drivers/staging/media/rpivid/rpivid_video.c\n@@ -499,8 +499,8 @@ static int rpivid_start_streaming(struct\n \tif (V4L2_TYPE_IS_OUTPUT(vq->type) && dev->dec_ops->start)\n \t\tret = dev->dec_ops->start(ctx);\n \n-\tret = clk_set_rate(dev->clock, max_hevc_clock);\n-\tif (ret) {\n+\tdev->hevc_req = clk_request_start(dev->clock, max_hevc_clock);\n+\tif (!dev->hevc_req) {\n \t\tdev_err(dev->dev, \"Failed to set clock rate\\n\");\n \t\tgoto out;\n \t}\n@@ -520,18 +520,13 @@ static void rpivid_stop_streaming(struct\n {\n \tstruct rpivid_ctx *ctx = vb2_get_drv_priv(vq);\n \tstruct rpivid_dev *dev = ctx->dev;\n-\tlong min_hevc_clock = clk_round_rate(dev->clock, 0);\n-\tint ret;\n \n \tif (V4L2_TYPE_IS_OUTPUT(vq->type) && dev->dec_ops->stop)\n \t\tdev->dec_ops->stop(ctx);\n \n \trpivid_queue_cleanup(vq, VB2_BUF_STATE_ERROR);\n \n-\tret = clk_set_rate(dev->clock, min_hevc_clock);\n-\tif (ret)\n-\t\tdev_err(dev->dev, \"Failed to set minimum clock rate\\n\");\n-\n+\tclk_request_done(dev->hevc_req);\n \tclk_disable_unprepare(dev->clock);\n }\n \n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0558-rpivid-Only-clk_request_done-once.patch",
    "content": "From 14bbd93c7d40b947bef6f6b0a203db1c5b263591 Mon Sep 17 00:00:00 2001\nFrom: Dom Cobley <popcornmix@gmail.com>\nDate: Tue, 20 Apr 2021 13:34:18 +0100\nSubject: [PATCH] rpivid: Only clk_request_done once\n\nFixes: 25486f49bfe2e3ae13b90478d1eebd91413136ad\nSigned-off-by: Dom Cobley <popcornmix@gmail.com>\n---\n drivers/staging/media/rpivid/rpivid_video.c | 6 +++++-\n 1 file changed, 5 insertions(+), 1 deletion(-)\n\n--- a/drivers/staging/media/rpivid/rpivid_video.c\n+++ b/drivers/staging/media/rpivid/rpivid_video.c\n@@ -526,7 +526,11 @@ static void rpivid_stop_streaming(struct\n \n \trpivid_queue_cleanup(vq, VB2_BUF_STATE_ERROR);\n \n-\tclk_request_done(dev->hevc_req);\n+\tif (dev->hevc_req)\n+\t{\n+\t\tclk_request_done(dev->hevc_req);\n+\t\tdev->hevc_req = NULL;\n+\t}\n \tclk_disable_unprepare(dev->clock);\n }\n \n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0559-dwc_otg-fix-an-undeclared-variable.patch",
    "content": "From e6845a88a3367be3c95aab00329eeedcd3eebec0 Mon Sep 17 00:00:00 2001\nFrom: wangzx <593074943@qq.com>\nDate: Tue, 20 Apr 2021 22:33:26 +0800\nSubject: [PATCH] dwc_otg: fix an undeclared variable Replace an\n undeclared variable used by DWC_DEBUGPL with the real endpoint address.\n DWC_DEBUGPL does nothing with DEBUG undefined so it did not go wrong before.\n Signed-off-by: Zixuan Wang <wangzixuan@sjtu.edu.cn>\n\n---\n drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c | 3 ++-\n 1 file changed, 2 insertions(+), 1 deletion(-)\n\n--- a/drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c\n+++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c\n@@ -1026,7 +1026,8 @@ static void endpoint_reset(struct usb_hc\n \tdwc_irqflags_t flags;\n \tdwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);\n \n-\tDWC_DEBUGPL(DBG_HCD, \"DWC OTG HCD EP RESET: Endpoint Num=0x%02d\\n\", epnum);\n+\tDWC_DEBUGPL(DBG_HCD, \"DWC OTG HCD EP RESET: Endpoint Num=0x%02d\\n\",\n+\t\t    ep->desc.bEndpointAddress);\n \n \tDWC_SPINLOCK_IRQSAVE(dwc_otg_hcd->lock, &flags);\n \tif (ep->hcpriv) {\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0560-drm-vc4-drv-Remove-the-DSI-pointer-in-vc4_drv.patch",
    "content": "From f9211d36925dac42f910d7d2e4c370e414fd24d2 Mon Sep 17 00:00:00 2001\nFrom: Maxime Ripard <maxime@cerno.tech>\nDate: Thu, 3 Dec 2020 14:25:36 +0100\nSubject: [PATCH] drm/vc4: drv: Remove the DSI pointer in vc4_drv\n\nCommit 51f4fcd9c4ea867c3b4fe58111f342ad0e80642a upstream.\n\nThat pointer isn't used anywhere, so there's no point in keeping it.\n\nReviewed-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\nSigned-off-by: Maxime Ripard <maxime@cerno.tech>\nLink: https://patchwork.freedesktop.org/patch/msgid/20201203132543.861591-2-maxime@cerno.tech\n---\n drivers/gpu/drm/vc4/vc4_drv.h | 1 -\n drivers/gpu/drm/vc4/vc4_dsi.c | 9 ---------\n 2 files changed, 10 deletions(-)\n\n--- a/drivers/gpu/drm/vc4/vc4_drv.h\n+++ b/drivers/gpu/drm/vc4/vc4_drv.h\n@@ -81,7 +81,6 @@ struct vc4_dev {\n \tstruct vc4_hvs *hvs;\n \tstruct vc4_v3d *v3d;\n \tstruct vc4_dpi *dpi;\n-\tstruct vc4_dsi *dsi1;\n \tstruct vc4_vec *vec;\n \tstruct vc4_txp *txp;\n \tstruct vc4_fkms *fkms;\n--- a/drivers/gpu/drm/vc4/vc4_dsi.c\n+++ b/drivers/gpu/drm/vc4/vc4_dsi.c\n@@ -1451,7 +1451,6 @@ static int vc4_dsi_bind(struct device *d\n {\n \tstruct platform_device *pdev = to_platform_device(dev);\n \tstruct drm_device *drm = dev_get_drvdata(master);\n-\tstruct vc4_dev *vc4 = to_vc4_dev(drm);\n \tstruct vc4_dsi *dsi = dev_get_drvdata(dev);\n \tstruct vc4_dsi_encoder *vc4_dsi_encoder;\n \tstruct drm_panel *panel;\n@@ -1604,9 +1603,6 @@ static int vc4_dsi_bind(struct device *d\n \tif (ret)\n \t\treturn ret;\n \n-\tif (dsi->port == 1)\n-\t\tvc4->dsi1 = dsi;\n-\n \tdrm_simple_encoder_init(drm, dsi->encoder, DRM_MODE_ENCODER_DSI);\n \tdrm_encoder_helper_add(dsi->encoder, &vc4_dsi_encoder_helper_funcs);\n \n@@ -1635,8 +1631,6 @@ static int vc4_dsi_bind(struct device *d\n static void vc4_dsi_unbind(struct device *dev, struct device *master,\n \t\t\t   void *data)\n {\n-\tstruct drm_device *drm = dev_get_drvdata(master);\n-\tstruct vc4_dev *vc4 = to_vc4_dev(drm);\n \tstruct vc4_dsi *dsi = dev_get_drvdata(dev);\n \n \tif (dsi->bridge)\n@@ -1648,9 +1642,6 @@ static void vc4_dsi_unbind(struct device\n \t */\n \tlist_splice_init(&dsi->bridge_chain, &dsi->encoder->bridge_chain);\n \tdrm_encoder_cleanup(dsi->encoder);\n-\n-\tif (dsi->port == 1)\n-\t\tvc4->dsi1 = NULL;\n }\n \n static const struct component_ops vc4_dsi_ops = {\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0561-drm-vc4-dsi-Use-snprintf-for-the-PHY-clocks-instead-.patch",
    "content": "From 7fe646b726b66c16f731e36e95d7eda9f182ba4d Mon Sep 17 00:00:00 2001\nFrom: Maxime Ripard <maxime@cerno.tech>\nDate: Thu, 3 Dec 2020 14:25:38 +0100\nSubject: [PATCH] drm/vc4: dsi: Use snprintf for the PHY clocks instead\n of an array\n\nCommit dc0bf36401e891c853e0a25baeb4e0b4e6f3626d upstream.\n\nThe DSI clocks setup function has been using an array to store the clock\nname of either the DSI0 or DSI1 blocks, using the port ID to choose the\nproper one.\n\nLet's switch to an snprintf call to do the same thing and simplify the\narray a bit.\n\nReviewed-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\nSigned-off-by: Maxime Ripard <maxime@cerno.tech>\nLink: https://patchwork.freedesktop.org/patch/msgid/20201203132543.861591-4-maxime@cerno.tech\n---\n drivers/gpu/drm/vc4/vc4_dsi.c | 17 +++++++++--------\n 1 file changed, 9 insertions(+), 8 deletions(-)\n\n--- a/drivers/gpu/drm/vc4/vc4_dsi.c\n+++ b/drivers/gpu/drm/vc4/vc4_dsi.c\n@@ -1390,12 +1390,12 @@ vc4_dsi_init_phy_clocks(struct vc4_dsi *\n \tstruct device *dev = &dsi->pdev->dev;\n \tconst char *parent_name = __clk_get_name(dsi->pll_phy_clock);\n \tstatic const struct {\n-\t\tconst char *dsi0_name, *dsi1_name;\n+\t\tconst char *name;\n \t\tint div;\n \t} phy_clocks[] = {\n-\t\t{ \"dsi0_byte\", \"dsi1_byte\", 8 },\n-\t\t{ \"dsi0_ddr2\", \"dsi1_ddr2\", 4 },\n-\t\t{ \"dsi0_ddr\", \"dsi1_ddr\", 2 },\n+\t\t{ \"byte\", 8 },\n+\t\t{ \"ddr2\", 4 },\n+\t\t{ \"ddr\", 2 },\n \t};\n \tint i;\n \n@@ -1411,8 +1411,12 @@ vc4_dsi_init_phy_clocks(struct vc4_dsi *\n \tfor (i = 0; i < ARRAY_SIZE(phy_clocks); i++) {\n \t\tstruct clk_fixed_factor *fix = &dsi->phy_clocks[i];\n \t\tstruct clk_init_data init;\n+\t\tchar clk_name[16];\n \t\tint ret;\n \n+\t\tsnprintf(clk_name, sizeof(clk_name),\n+\t\t\t \"dsi%u_%s\", dsi->port, phy_clocks[i].name);\n+\n \t\t/* We just use core fixed factor clock ops for the PHY\n \t\t * clocks.  The clocks are actually gated by the\n \t\t * PHY_AFEC0_DDRCLK_EN bits, which we should be\n@@ -1429,10 +1433,7 @@ vc4_dsi_init_phy_clocks(struct vc4_dsi *\n \t\tmemset(&init, 0, sizeof(init));\n \t\tinit.parent_names = &parent_name;\n \t\tinit.num_parents = 1;\n-\t\tif (dsi->port == 1)\n-\t\t\tinit.name = phy_clocks[i].dsi1_name;\n-\t\telse\n-\t\t\tinit.name = phy_clocks[i].dsi0_name;\n+\t\tinit.name = clk_name;\n \t\tinit.ops = &clk_fixed_factor_ops;\n \n \t\tret = devm_clk_hw_register(dev, &fix->hw);\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0562-drm-vc4-dsi-Introduce-a-variant-structure.patch",
    "content": "From 4dd1101f3e16e6202132ae34a8da2a7d78043d56 Mon Sep 17 00:00:00 2001\nFrom: Maxime Ripard <maxime@cerno.tech>\nDate: Thu, 3 Dec 2020 14:25:39 +0100\nSubject: [PATCH] drm/vc4: dsi: Introduce a variant structure\n\nCommit d1d195ce26a14ec0a87816c09ae514e1c40e97f7 upstream.\n\nMost of the differences between DSI0 and DSI1 are handled through the\nID. However, the BCM2711 DSI is going to introduce one more variable to\nthe mix and will break some expectations of the earlier, simpler, test.\n\nLet's add a variant structure that will address most of the differences\nbetween those three controllers.\n\nReviewed-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\nSigned-off-by: Maxime Ripard <maxime@cerno.tech>\nLink: https://patchwork.freedesktop.org/patch/msgid/20201203132543.861591-5-maxime@cerno.tech\n---\n drivers/gpu/drm/vc4/vc4_dsi.c | 63 ++++++++++++++++++++---------------\n 1 file changed, 37 insertions(+), 26 deletions(-)\n\n--- a/drivers/gpu/drm/vc4/vc4_dsi.c\n+++ b/drivers/gpu/drm/vc4/vc4_dsi.c\n@@ -493,6 +493,18 @@\n  */\n #define DSI1_ID\t\t\t0x8c\n \n+struct vc4_dsi_variant {\n+\t/* Whether we're on bcm2835's DSI0 or DSI1. */\n+\tunsigned int port;\n+\n+\tbool broken_axi_workaround;\n+\n+\tconst char *debugfs_name;\n+\tconst struct debugfs_reg32 *regs;\n+\tsize_t nregs;\n+\n+};\n+\n /* General DSI hardware state. */\n struct vc4_dsi {\n \tstruct platform_device *pdev;\n@@ -509,8 +521,7 @@ struct vc4_dsi {\n \tu32 *reg_dma_mem;\n \tdma_addr_t reg_paddr;\n \n-\t/* Whether we're on bcm2835's DSI0 or DSI1. */\n-\tint port;\n+\tconst struct vc4_dsi_variant *variant;\n \n \t/* DSI channel for the panel we're connected to. */\n \tu32 channel;\n@@ -586,10 +597,10 @@ dsi_dma_workaround_write(struct vc4_dsi\n #define DSI_READ(offset) readl(dsi->regs + (offset))\n #define DSI_WRITE(offset, val) dsi_dma_workaround_write(dsi, offset, val)\n #define DSI_PORT_READ(offset) \\\n-\tDSI_READ(dsi->port ? DSI1_##offset : DSI0_##offset)\n+\tDSI_READ(dsi->variant->port ? DSI1_##offset : DSI0_##offset)\n #define DSI_PORT_WRITE(offset, val) \\\n-\tDSI_WRITE(dsi->port ? DSI1_##offset : DSI0_##offset, val)\n-#define DSI_PORT_BIT(bit) (dsi->port ? DSI1_##bit : DSI0_##bit)\n+\tDSI_WRITE(dsi->variant->port ? DSI1_##offset : DSI0_##offset, val)\n+#define DSI_PORT_BIT(bit) (dsi->variant->port ? DSI1_##bit : DSI0_##bit)\n \n /* VC4 DSI encoder KMS struct */\n struct vc4_dsi_encoder {\n@@ -837,7 +848,7 @@ static void vc4_dsi_encoder_enable(struc\n \n \tret = pm_runtime_resume_and_get(dev);\n \tif (ret) {\n-\t\tDRM_ERROR(\"Failed to runtime PM enable on DSI%d\\n\", dsi->port);\n+\t\tDRM_ERROR(\"Failed to runtime PM enable on DSI%d\\n\", dsi->variant->port);\n \t\treturn;\n \t}\n \n@@ -871,7 +882,7 @@ static void vc4_dsi_encoder_enable(struc\n \tDSI_PORT_WRITE(STAT, DSI_PORT_READ(STAT));\n \n \t/* Set AFE CTR00/CTR1 to release powerdown of analog. */\n-\tif (dsi->port == 0) {\n+\tif (dsi->variant->port == 0) {\n \t\tu32 afec0 = (VC4_SET_FIELD(7, DSI_PHY_AFEC0_PTATADJ) |\n \t\t\t     VC4_SET_FIELD(7, DSI_PHY_AFEC0_CTATADJ));\n \n@@ -1017,7 +1028,7 @@ static void vc4_dsi_encoder_enable(struc\n \t\t       DSI_PORT_BIT(PHYC_CLANE_ENABLE) |\n \t\t       ((dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) ?\n \t\t\t0 : DSI_PORT_BIT(PHYC_HS_CLK_CONTINUOUS)) |\n-\t\t       (dsi->port == 0 ?\n+\t\t       (dsi->variant->port == 0 ?\n \t\t\tVC4_SET_FIELD(lpx - 1, DSI0_PHYC_ESC_CLK_LPDT) :\n \t\t\tVC4_SET_FIELD(lpx - 1, DSI1_PHYC_ESC_CLK_LPDT)));\n \n@@ -1043,13 +1054,13 @@ static void vc4_dsi_encoder_enable(struc\n \t\t       DSI_DISP1_ENABLE);\n \n \t/* Ungate the block. */\n-\tif (dsi->port == 0)\n+\tif (dsi->variant->port == 0)\n \t\tDSI_PORT_WRITE(CTRL, DSI_PORT_READ(CTRL) | DSI0_CTRL_CTRL0);\n \telse\n \t\tDSI_PORT_WRITE(CTRL, DSI_PORT_READ(CTRL) | DSI1_CTRL_EN);\n \n \t/* Bring AFE out of reset. */\n-\tif (dsi->port == 0) {\n+\tif (dsi->variant->port == 0) {\n \t} else {\n \t\tDSI_PORT_WRITE(PHY_AFEC0,\n \t\t\t       DSI_PORT_READ(PHY_AFEC0) &\n@@ -1305,8 +1316,16 @@ static const struct drm_encoder_helper_f\n \t.mode_fixup = vc4_dsi_encoder_mode_fixup,\n };\n \n+static const struct vc4_dsi_variant bcm2835_dsi1_variant = {\n+\t.port\t\t\t= 1,\n+\t.broken_axi_workaround\t= true,\n+\t.debugfs_name\t\t= \"dsi1_regs\",\n+\t.regs\t\t\t= dsi1_regs,\n+\t.nregs\t\t\t= ARRAY_SIZE(dsi1_regs),\n+};\n+\n static const struct of_device_id vc4_dsi_dt_match[] = {\n-\t{ .compatible = \"brcm,bcm2835-dsi1\", (void *)(uintptr_t)1 },\n+\t{ .compatible = \"brcm,bcm2835-dsi1\", &bcm2835_dsi1_variant },\n \t{}\n };\n \n@@ -1317,7 +1336,7 @@ static void dsi_handle_error(struct vc4_\n \tif (!(stat & bit))\n \t\treturn;\n \n-\tDRM_ERROR(\"DSI%d: %s error\\n\", dsi->port, type);\n+\tDRM_ERROR(\"DSI%d: %s error\\n\", dsi->variant->port, type);\n \t*ret = IRQ_HANDLED;\n }\n \n@@ -1415,7 +1434,7 @@ vc4_dsi_init_phy_clocks(struct vc4_dsi *\n \t\tint ret;\n \n \t\tsnprintf(clk_name, sizeof(clk_name),\n-\t\t\t \"dsi%u_%s\", dsi->port, phy_clocks[i].name);\n+\t\t\t \"dsi%u_%s\", dsi->variant->port, phy_clocks[i].name);\n \n \t\t/* We just use core fixed factor clock ops for the PHY\n \t\t * clocks.  The clocks are actually gated by the\n@@ -1463,7 +1482,7 @@ static int vc4_dsi_bind(struct device *d\n \tif (!match)\n \t\treturn -ENODEV;\n \n-\tdsi->port = (uintptr_t)match->data;\n+\tdsi->variant = match->data;\n \n \tvc4_dsi_encoder = devm_kzalloc(dev, sizeof(*vc4_dsi_encoder),\n \t\t\t\t       GFP_KERNEL);\n@@ -1480,13 +1499,8 @@ static int vc4_dsi_bind(struct device *d\n \t\treturn PTR_ERR(dsi->regs);\n \n \tdsi->regset.base = dsi->regs;\n-\tif (dsi->port == 0) {\n-\t\tdsi->regset.regs = dsi0_regs;\n-\t\tdsi->regset.nregs = ARRAY_SIZE(dsi0_regs);\n-\t} else {\n-\t\tdsi->regset.regs = dsi1_regs;\n-\t\tdsi->regset.nregs = ARRAY_SIZE(dsi1_regs);\n-\t}\n+\tdsi->regset.regs = dsi->variant->regs;\n+\tdsi->regset.nregs = dsi->variant->nregs;\n \n \tif (DSI_PORT_READ(ID) != DSI_ID_VALUE) {\n \t\tdev_err(dev, \"Port returned 0x%08x for ID instead of 0x%08x\\n\",\n@@ -1498,7 +1512,7 @@ static int vc4_dsi_bind(struct device *d\n \t * from the ARM.  It does handle writes from the DMA engine,\n \t * so set up a channel for talking to it.\n \t */\n-\tif (dsi->port == 1) {\n+\tif (dsi->variant->broken_axi_workaround) {\n \t\tdsi->reg_dma_mem = dma_alloc_coherent(dev, 4,\n \t\t\t\t\t\t      &dsi->reg_dma_paddr,\n \t\t\t\t\t\t      GFP_KERNEL);\n@@ -1619,10 +1633,7 @@ static int vc4_dsi_bind(struct device *d\n \t */\n \tlist_splice_init(&dsi->encoder->bridge_chain, &dsi->bridge_chain);\n \n-\tif (dsi->port == 0)\n-\t\tvc4_debugfs_add_regset32(drm, \"dsi0_regs\", &dsi->regset);\n-\telse\n-\t\tvc4_debugfs_add_regset32(drm, \"dsi1_regs\", &dsi->regset);\n+\tvc4_debugfs_add_regset32(drm, dsi->variant->debugfs_name, &dsi->regset);\n \n \tpm_runtime_enable(dev);\n \n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0563-drm-vc4-dsi-Add-support-for-DSI0.patch",
    "content": "From 7302f0d6f939247c1c658b79aba0866c92560ff7 Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Thu, 3 Dec 2020 14:25:40 +0100\nSubject: [PATCH] drm/vc4: dsi: Add support for DSI0\n\nCommit 4b265fe11fad4234b12d92dd8091f9aa0c878eea upstream.\n\nDSI0 was partially supported, but didn't register with the main\ndriver, and the code was inconsistent as to whether it checked\nport == 0 or port == 1.\n\nAdd compatible string and other support to make it consistent.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\nSigned-off-by: Maxime Ripard <maxime@cerno.tech>\nLink: https://patchwork.freedesktop.org/patch/msgid/20201203132543.861591-6-maxime@cerno.tech\n---\n drivers/gpu/drm/vc4/vc4_dsi.c | 8 ++++++++\n 1 file changed, 8 insertions(+)\n\n--- a/drivers/gpu/drm/vc4/vc4_dsi.c\n+++ b/drivers/gpu/drm/vc4/vc4_dsi.c\n@@ -1316,6 +1316,13 @@ static const struct drm_encoder_helper_f\n \t.mode_fixup = vc4_dsi_encoder_mode_fixup,\n };\n \n+static const struct vc4_dsi_variant bcm2835_dsi0_variant = {\n+\t.port\t\t\t= 0,\n+\t.debugfs_name\t\t= \"dsi0_regs\",\n+\t.regs\t\t\t= dsi0_regs,\n+\t.nregs\t\t\t= ARRAY_SIZE(dsi0_regs),\n+};\n+\n static const struct vc4_dsi_variant bcm2835_dsi1_variant = {\n \t.port\t\t\t= 1,\n \t.broken_axi_workaround\t= true,\n@@ -1325,6 +1332,7 @@ static const struct vc4_dsi_variant bcm2\n };\n \n static const struct of_device_id vc4_dsi_dt_match[] = {\n+\t{ .compatible = \"brcm,bcm2835-dsi0\", &bcm2835_dsi0_variant },\n \t{ .compatible = \"brcm,bcm2835-dsi1\", &bcm2835_dsi1_variant },\n \t{}\n };\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0564-drm-vc4-dsi-Add-configuration-for-BCM2711-DSI1.patch",
    "content": "From 24b8230e039c6bef2dcc0ea4ca7cb5d2441570f1 Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Thu, 3 Dec 2020 14:25:42 +0100\nSubject: [PATCH] drm/vc4: dsi: Add configuration for BCM2711 DSI1\n\nCommit d0666be8ef9e8e65d4b7fabc1606ec51f61384c0 upstream.\n\nBCM2711 DSI1 doesn't have the issue with the ARM not being\nable to write to the registers, therefore remove the DMA\nworkaround for that compatible string.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\nSigned-off-by: Maxime Ripard <maxime@cerno.tech>\nLink: https://patchwork.freedesktop.org/patch/msgid/20201203132543.861591-8-maxime@cerno.tech\n---\n drivers/gpu/drm/vc4/vc4_dsi.c | 12 ++++++++++--\n 1 file changed, 10 insertions(+), 2 deletions(-)\n\n--- a/drivers/gpu/drm/vc4/vc4_dsi.c\n+++ b/drivers/gpu/drm/vc4/vc4_dsi.c\n@@ -1316,6 +1316,13 @@ static const struct drm_encoder_helper_f\n \t.mode_fixup = vc4_dsi_encoder_mode_fixup,\n };\n \n+static const struct vc4_dsi_variant bcm2711_dsi1_variant = {\n+\t.port\t\t\t= 1,\n+\t.debugfs_name\t\t= \"dsi1_regs\",\n+\t.regs\t\t\t= dsi1_regs,\n+\t.nregs\t\t\t= ARRAY_SIZE(dsi1_regs),\n+};\n+\n static const struct vc4_dsi_variant bcm2835_dsi0_variant = {\n \t.port\t\t\t= 0,\n \t.debugfs_name\t\t= \"dsi0_regs\",\n@@ -1332,6 +1339,7 @@ static const struct vc4_dsi_variant bcm2\n };\n \n static const struct of_device_id vc4_dsi_dt_match[] = {\n+\t{ .compatible = \"brcm,bcm2711-dsi1\", &bcm2711_dsi1_variant },\n \t{ .compatible = \"brcm,bcm2835-dsi0\", &bcm2835_dsi0_variant },\n \t{ .compatible = \"brcm,bcm2835-dsi1\", &bcm2835_dsi1_variant },\n \t{}\n@@ -1516,8 +1524,8 @@ static int vc4_dsi_bind(struct device *d\n \t\treturn -ENODEV;\n \t}\n \n-\t/* DSI1 has a broken AXI slave that doesn't respond to writes\n-\t * from the ARM.  It does handle writes from the DMA engine,\n+\t/* DSI1 on BCM2835/6/7 has a broken AXI slave that doesn't respond to\n+\t * writes from the ARM.  It does handle writes from the DMA engine,\n \t * so set up a channel for talking to it.\n \t */\n \tif (dsi->variant->broken_axi_workaround) {\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0565-drm-vc4-Correct-pixel-order-for-DSI0.patch",
    "content": "From 59938610a705283fef63447c7e777781358610e2 Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Thu, 11 Feb 2021 18:37:04 +0000\nSubject: [PATCH] drm/vc4: Correct pixel order for DSI0\n\nFor slightly unknown reasons, dsi0 takes a different pixel format\nto dsi1, and that has to be set in the pixel valve.\n\nAmend the setup accordingly.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n drivers/gpu/drm/vc4/vc4_crtc.c | 3 ++-\n 1 file changed, 2 insertions(+), 1 deletion(-)\n\n--- a/drivers/gpu/drm/vc4/vc4_crtc.c\n+++ b/drivers/gpu/drm/vc4/vc4_crtc.c\n@@ -319,7 +319,8 @@ static void vc4_crtc_config_pv(struct dr\n \tu32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;\n \tbool is_dsi = (vc4_encoder->type == VC4_ENCODER_TYPE_DSI0 ||\n \t\t       vc4_encoder->type == VC4_ENCODER_TYPE_DSI1);\n-\tu32 format = is_dsi ? PV_CONTROL_FORMAT_DSIV_24 : PV_CONTROL_FORMAT_24;\n+\tbool is_dsi1 = vc4_encoder->type == VC4_ENCODER_TYPE_DSI1;\n+\tu32 format = is_dsi1 ? PV_CONTROL_FORMAT_DSIV_24 : PV_CONTROL_FORMAT_24;\n \tu8 ppc = pv_data->pixels_per_clock;\n \tbool debug_dump_regs = false;\n \n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0566-drm-vc4-Register-dsi0-as-the-correct-vc4-encoder-typ.patch",
    "content": "From b627cebfc64dd944b9571203e30456efbc0101c3 Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Mon, 8 Feb 2021 11:22:01 +0000\nSubject: [PATCH] drm/vc4: Register dsi0 as the correct vc4 encoder\n type\n\nvc4_dsi was registering both dsi0 and dsi1 as VC4_ENCODER_TYPE_DSI1\nwhich seemed to work OK for a single DSI display, but fails\nif there are two DSI displays connected.\n\nUpdate to register the correct type.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n drivers/gpu/drm/vc4/vc4_dsi.c | 3 ++-\n 1 file changed, 2 insertions(+), 1 deletion(-)\n\n--- a/drivers/gpu/drm/vc4/vc4_dsi.c\n+++ b/drivers/gpu/drm/vc4/vc4_dsi.c\n@@ -1506,7 +1506,8 @@ static int vc4_dsi_bind(struct device *d\n \t\treturn -ENOMEM;\n \n \tINIT_LIST_HEAD(&dsi->bridge_chain);\n-\tvc4_dsi_encoder->base.type = VC4_ENCODER_TYPE_DSI1;\n+\tvc4_dsi_encoder->base.type = dsi->variant->port ?\n+\t\t\tVC4_ENCODER_TYPE_DSI1 : VC4_ENCODER_TYPE_DSI0;\n \tvc4_dsi_encoder->dsi = dsi;\n \tdsi->encoder = &vc4_dsi_encoder->base.base;\n \n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0567-drm-vc4-Fix-dsi0-interrupt-support.patch",
    "content": "From 1ad48331b7697e4fbc9f4bd376fc2db342045cb6 Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Wed, 10 Feb 2021 18:46:22 +0000\nSubject: [PATCH] drm/vc4: Fix dsi0 interrupt support.\n\nDSI0 seemingly had very little or no testing as a load of\nthe register mappings were incorrect/missing, so host\ntransfers always timed out due to enabling/checking incorrect\nbits in the interrupt enable and status registers.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n drivers/gpu/drm/vc4/vc4_dsi.c | 111 ++++++++++++++++++++++++++--------\n 1 file changed, 85 insertions(+), 26 deletions(-)\n\n--- a/drivers/gpu/drm/vc4/vc4_dsi.c\n+++ b/drivers/gpu/drm/vc4/vc4_dsi.c\n@@ -181,8 +181,50 @@\n \n #define DSI0_TXPKT_PIX_FIFO\t\t0x20 /* AKA PIX_FIFO */\n \n-#define DSI0_INT_STAT\t\t0x24\n-#define DSI0_INT_EN\t\t0x28\n+#define DSI0_INT_STAT\t\t\t0x24\n+#define DSI0_INT_EN\t\t\t0x28\n+# define DSI0_INT_FIFO_ERR\t\tBIT(25)\n+# define DSI0_INT_CMDC_DONE_MASK\tVC4_MASK(24, 23)\n+# define DSI0_INT_CMDC_DONE_SHIFT\t23\n+#  define DSI0_INT_CMDC_DONE_NO_REPEAT\t\t1\n+#  define DSI0_INT_CMDC_DONE_REPEAT\t\t3\n+# define DSI0_INT_PHY_DIR_RTF\t\tBIT(22)\n+# define DSI0_INT_PHY_D1_ULPS\t\tBIT(21)\n+# define DSI0_INT_PHY_D1_STOP\t\tBIT(20)\n+# define DSI0_INT_PHY_RXLPDT\t\tBIT(19)\n+# define DSI0_INT_PHY_RXTRIG\t\tBIT(18)\n+# define DSI0_INT_PHY_D0_ULPS\t\tBIT(17)\n+# define DSI0_INT_PHY_D0_LPDT\t\tBIT(16)\n+# define DSI0_INT_PHY_D0_FTR\t\tBIT(15)\n+# define DSI0_INT_PHY_D0_STOP\t\tBIT(14)\n+/* Signaled when the clock lane enters the given state. */\n+# define DSI0_INT_PHY_CLK_ULPS\t\tBIT(13)\n+# define DSI0_INT_PHY_CLK_HS\t\tBIT(12)\n+# define DSI0_INT_PHY_CLK_FTR\t\tBIT(11)\n+/* Signaled on timeouts */\n+# define DSI0_INT_PR_TO\t\t\tBIT(10)\n+# define DSI0_INT_TA_TO\t\t\tBIT(9)\n+# define DSI0_INT_LPRX_TO\t\tBIT(8)\n+# define DSI0_INT_HSTX_TO\t\tBIT(7)\n+/* Contention on a line when trying to drive the line low */\n+# define DSI0_INT_ERR_CONT_LP1\t\tBIT(6)\n+# define DSI0_INT_ERR_CONT_LP0\t\tBIT(5)\n+/* Control error: incorrect line state sequence on data lane 0. */\n+# define DSI0_INT_ERR_CONTROL\t\tBIT(4)\n+# define DSI0_INT_ERR_SYNC_ESC\t\tBIT(3)\n+# define DSI0_INT_RX2_PKT\t\tBIT(2)\n+# define DSI0_INT_RX1_PKT\t\tBIT(1)\n+# define DSI0_INT_CMD_PKT\t\tBIT(0)\n+\n+#define DSI0_INTERRUPTS_ALWAYS_ENABLED\t(DSI0_INT_ERR_SYNC_ESC | \\\n+\t\t\t\t\t DSI0_INT_ERR_CONTROL |\t \\\n+\t\t\t\t\t DSI0_INT_ERR_CONT_LP0 | \\\n+\t\t\t\t\t DSI0_INT_ERR_CONT_LP1 | \\\n+\t\t\t\t\t DSI0_INT_HSTX_TO |\t \\\n+\t\t\t\t\t DSI0_INT_LPRX_TO |\t \\\n+\t\t\t\t\t DSI0_INT_TA_TO |\t \\\n+\t\t\t\t\t DSI0_INT_PR_TO)\n+\n # define DSI1_INT_PHY_D3_ULPS\t\tBIT(30)\n # define DSI1_INT_PHY_D3_STOP\t\tBIT(29)\n # define DSI1_INT_PHY_D2_ULPS\t\tBIT(28)\n@@ -894,6 +936,9 @@ static void vc4_dsi_encoder_enable(struc\n \n \t\tDSI_PORT_WRITE(PHY_AFEC0, afec0);\n \n+\t\t/* AFEC reset hold time */\n+\t\tmdelay(1);\n+\n \t\tDSI_PORT_WRITE(PHY_AFEC1,\n \t\t\t       VC4_SET_FIELD(6,  DSI0_PHY_AFEC1_IDR_DLANE1) |\n \t\t\t       VC4_SET_FIELD(6,  DSI0_PHY_AFEC1_IDR_DLANE0) |\n@@ -1060,12 +1105,9 @@ static void vc4_dsi_encoder_enable(struc\n \t\tDSI_PORT_WRITE(CTRL, DSI_PORT_READ(CTRL) | DSI1_CTRL_EN);\n \n \t/* Bring AFE out of reset. */\n-\tif (dsi->variant->port == 0) {\n-\t} else {\n-\t\tDSI_PORT_WRITE(PHY_AFEC0,\n-\t\t\t       DSI_PORT_READ(PHY_AFEC0) &\n-\t\t\t       ~DSI1_PHY_AFEC0_RESET);\n-\t}\n+\tDSI_PORT_WRITE(PHY_AFEC0,\n+\t\t       DSI_PORT_READ(PHY_AFEC0) &\n+\t\t       ~DSI_PORT_BIT(PHY_AFEC0_RESET));\n \n \tvc4_dsi_ulps(dsi, false);\n \n@@ -1184,13 +1226,28 @@ static ssize_t vc4_dsi_host_transfer(str\n \t/* Enable the appropriate interrupt for the transfer completion. */\n \tdsi->xfer_result = 0;\n \treinit_completion(&dsi->xfer_completion);\n-\tDSI_PORT_WRITE(INT_STAT, DSI1_INT_TXPKT1_DONE | DSI1_INT_PHY_DIR_RTF);\n-\tif (msg->rx_len) {\n-\t\tDSI_PORT_WRITE(INT_EN, (DSI1_INTERRUPTS_ALWAYS_ENABLED |\n-\t\t\t\t\tDSI1_INT_PHY_DIR_RTF));\n+\tif (dsi->variant->port == 0) {\n+\t\tDSI_PORT_WRITE(INT_STAT,\n+\t\t\t       DSI0_INT_CMDC_DONE_MASK | DSI1_INT_PHY_DIR_RTF);\n+\t\tif (msg->rx_len) {\n+\t\t\tDSI_PORT_WRITE(INT_EN, (DSI0_INTERRUPTS_ALWAYS_ENABLED |\n+\t\t\t\t\t\tDSI0_INT_PHY_DIR_RTF));\n+\t\t} else {\n+\t\t\tDSI_PORT_WRITE(INT_EN,\n+\t\t\t\t       (DSI0_INTERRUPTS_ALWAYS_ENABLED |\n+\t\t\t\t\tVC4_SET_FIELD(DSI0_INT_CMDC_DONE_NO_REPEAT,\n+\t\t\t\t\t\t      DSI0_INT_CMDC_DONE)));\n+\t\t}\n \t} else {\n-\t\tDSI_PORT_WRITE(INT_EN, (DSI1_INTERRUPTS_ALWAYS_ENABLED |\n-\t\t\t\t\tDSI1_INT_TXPKT1_DONE));\n+\t\tDSI_PORT_WRITE(INT_STAT,\n+\t\t\t       DSI1_INT_TXPKT1_DONE | DSI1_INT_PHY_DIR_RTF);\n+\t\tif (msg->rx_len) {\n+\t\t\tDSI_PORT_WRITE(INT_EN, (DSI1_INTERRUPTS_ALWAYS_ENABLED |\n+\t\t\t\t\t\tDSI1_INT_PHY_DIR_RTF));\n+\t\t} else {\n+\t\t\tDSI_PORT_WRITE(INT_EN, (DSI1_INTERRUPTS_ALWAYS_ENABLED |\n+\t\t\t\t\t\tDSI1_INT_TXPKT1_DONE));\n+\t\t}\n \t}\n \n \t/* Send the packet. */\n@@ -1207,7 +1264,7 @@ static ssize_t vc4_dsi_host_transfer(str\n \t\tret = dsi->xfer_result;\n \t}\n \n-\tDSI_PORT_WRITE(INT_EN, DSI1_INTERRUPTS_ALWAYS_ENABLED);\n+\tDSI_PORT_WRITE(INT_EN, DSI_PORT_BIT(INTERRUPTS_ALWAYS_ENABLED));\n \n \tif (ret)\n \t\tgoto reset_fifo_and_return;\n@@ -1253,7 +1310,7 @@ reset_fifo_and_return:\n \t\t       DSI_PORT_BIT(CTRL_RESET_FIFOS));\n \n \tDSI_PORT_WRITE(TXPKT1C, 0);\n-\tDSI_PORT_WRITE(INT_EN, DSI1_INTERRUPTS_ALWAYS_ENABLED);\n+\tDSI_PORT_WRITE(INT_EN, DSI_PORT_BIT(INTERRUPTS_ALWAYS_ENABLED));\n \treturn ret;\n }\n \n@@ -1386,26 +1443,28 @@ static irqreturn_t vc4_dsi_irq_handler(i\n \tDSI_PORT_WRITE(INT_STAT, stat);\n \n \tdsi_handle_error(dsi, &ret, stat,\n-\t\t\t DSI1_INT_ERR_SYNC_ESC, \"LPDT sync\");\n+\t\t\t DSI_PORT_BIT(INT_ERR_SYNC_ESC), \"LPDT sync\");\n \tdsi_handle_error(dsi, &ret, stat,\n-\t\t\t DSI1_INT_ERR_CONTROL, \"data lane 0 sequence\");\n+\t\t\t DSI_PORT_BIT(INT_ERR_CONTROL), \"data lane 0 sequence\");\n \tdsi_handle_error(dsi, &ret, stat,\n-\t\t\t DSI1_INT_ERR_CONT_LP0, \"LP0 contention\");\n+\t\t\t DSI_PORT_BIT(INT_ERR_CONT_LP0), \"LP0 contention\");\n \tdsi_handle_error(dsi, &ret, stat,\n-\t\t\t DSI1_INT_ERR_CONT_LP1, \"LP1 contention\");\n+\t\t\t DSI_PORT_BIT(INT_ERR_CONT_LP1), \"LP1 contention\");\n \tdsi_handle_error(dsi, &ret, stat,\n-\t\t\t DSI1_INT_HSTX_TO, \"HSTX timeout\");\n+\t\t\t DSI_PORT_BIT(INT_HSTX_TO), \"HSTX timeout\");\n \tdsi_handle_error(dsi, &ret, stat,\n-\t\t\t DSI1_INT_LPRX_TO, \"LPRX timeout\");\n+\t\t\t DSI_PORT_BIT(INT_LPRX_TO), \"LPRX timeout\");\n \tdsi_handle_error(dsi, &ret, stat,\n-\t\t\t DSI1_INT_TA_TO, \"turnaround timeout\");\n+\t\t\t DSI_PORT_BIT(INT_TA_TO), \"turnaround timeout\");\n \tdsi_handle_error(dsi, &ret, stat,\n-\t\t\t DSI1_INT_PR_TO, \"peripheral reset timeout\");\n+\t\t\t DSI_PORT_BIT(INT_PR_TO), \"peripheral reset timeout\");\n \n-\tif (stat & (DSI1_INT_TXPKT1_DONE | DSI1_INT_PHY_DIR_RTF)) {\n+\tif (stat & ((dsi->variant->port ? DSI1_INT_TXPKT1_DONE :\n+\t\t\t\t\t  DSI0_INT_CMDC_DONE_MASK) |\n+\t\t    DSI_PORT_BIT(INT_PHY_DIR_RTF))) {\n \t\tcomplete(&dsi->xfer_completion);\n \t\tret = IRQ_HANDLED;\n-\t} else if (stat & DSI1_INT_HSTX_TO) {\n+\t} else if (stat & DSI_PORT_BIT(INT_HSTX_TO)) {\n \t\tcomplete(&dsi->xfer_completion);\n \t\tdsi->xfer_result = -ETIMEDOUT;\n \t\tret = IRQ_HANDLED;\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0568-drm-vc4-Add-correct-stop-condition-to-vc4_dsi_encode.patch",
    "content": "From 709279f0925b7e17f64684a8cab44e1cb72ae56e Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Thu, 15 Apr 2021 16:18:16 +0100\nSubject: [PATCH] drm/vc4: Add correct stop condition to\n vc4_dsi_encoder_disable iteration\n\nvc4_dsi_encoder_disable is partially an open coded version of\ndrm_bridge_chain_disable, but it missed a termination condition\nin the loop for ->disable which meant that no post_disable\ncalls were made.\n\nAdd in the termination clause.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n drivers/gpu/drm/vc4/vc4_dsi.c | 3 +++\n 1 file changed, 3 insertions(+)\n\n--- a/drivers/gpu/drm/vc4/vc4_dsi.c\n+++ b/drivers/gpu/drm/vc4/vc4_dsi.c\n@@ -803,6 +803,9 @@ static void vc4_dsi_encoder_disable(stru\n \tlist_for_each_entry_reverse(iter, &dsi->bridge_chain, chain_node) {\n \t\tif (iter->funcs->disable)\n \t\t\titer->funcs->disable(iter);\n+\n+\t\tif (iter == dsi->bridge)\n+\t\t\tbreak;\n \t}\n \n \tvc4_dsi_ulps(dsi, true);\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0569-drm-atomic-Don-t-fixup-modes-that-haven-t-been-reset.patch",
    "content": "From 4b060ef559d6d6cd229484a60b56e15993f3053c Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Thu, 7 Jan 2021 16:30:55 +0000\nSubject: [PATCH] drm/atomic: Don't fixup modes that haven't been reset\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n drivers/gpu/drm/drm_atomic_helper.c | 5 +++++\n 1 file changed, 5 insertions(+)\n\n--- a/drivers/gpu/drm/drm_atomic_helper.c\n+++ b/drivers/gpu/drm/drm_atomic_helper.c\n@@ -430,6 +430,11 @@ mode_fixup(struct drm_atomic_state *stat\n \t\tnew_crtc_state =\n \t\t\tdrm_atomic_get_new_crtc_state(state, new_conn_state->crtc);\n \n+\t\tif (!new_crtc_state->mode_changed &&\n+\t\t    !new_crtc_state->connectors_changed) {\n+\t\t\tcontinue;\n+\t\t}\n+\n \t\t/*\n \t\t * Each encoder has at most one connector (since we always steal\n \t\t * it away), so we won't call ->mode_fixup twice.\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0570-drm-panel-jdi-lt070me05000-Use-gpiod_set_value_cansl.patch",
    "content": "From ec29b05b2da1d82d03730e0ac317efd3a7e97759 Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Thu, 15 Apr 2021 17:30:35 +0100\nSubject: [PATCH] drm/panel: jdi-lt070me05000: Use\n gpiod_set_value_cansleep\n\nThere is no reason why the control GPIOs for the panel can not\nbe connected to I2C or similar GPIO interfaces that may need to\nsleep, therefore switch from gpiod_set_value to\ngpiod_set_value_cansleep calls to configure them.\nWithout that you get complaints from gpiolib every time the state\nis changed.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n drivers/gpu/drm/panel/panel-jdi-lt070me05000.c | 18 +++++++++---------\n 1 file changed, 9 insertions(+), 9 deletions(-)\n\n--- a/drivers/gpu/drm/panel/panel-jdi-lt070me05000.c\n+++ b/drivers/gpu/drm/panel/panel-jdi-lt070me05000.c\n@@ -205,11 +205,11 @@ static int jdi_panel_unprepare(struct dr\n \tif (ret < 0)\n \t\tdev_err(dev, \"regulator disable failed, %d\\n\", ret);\n \n-\tgpiod_set_value(jdi->enable_gpio, 0);\n+\tgpiod_set_value_cansleep(jdi->enable_gpio, 0);\n \n-\tgpiod_set_value(jdi->reset_gpio, 1);\n+\tgpiod_set_value_cansleep(jdi->reset_gpio, 1);\n \n-\tgpiod_set_value(jdi->dcdc_en_gpio, 0);\n+\tgpiod_set_value_cansleep(jdi->dcdc_en_gpio, 0);\n \n \tjdi->prepared = false;\n \n@@ -233,13 +233,13 @@ static int jdi_panel_prepare(struct drm_\n \n \tmsleep(20);\n \n-\tgpiod_set_value(jdi->dcdc_en_gpio, 1);\n+\tgpiod_set_value_cansleep(jdi->dcdc_en_gpio, 1);\n \tusleep_range(10, 20);\n \n-\tgpiod_set_value(jdi->reset_gpio, 0);\n+\tgpiod_set_value_cansleep(jdi->reset_gpio, 0);\n \tusleep_range(10, 20);\n \n-\tgpiod_set_value(jdi->enable_gpio, 1);\n+\tgpiod_set_value_cansleep(jdi->enable_gpio, 1);\n \tusleep_range(10, 20);\n \n \tret = jdi_panel_init(jdi);\n@@ -263,11 +263,11 @@ poweroff:\n \tif (ret < 0)\n \t\tdev_err(dev, \"regulator disable failed, %d\\n\", ret);\n \n-\tgpiod_set_value(jdi->enable_gpio, 0);\n+\tgpiod_set_value_cansleep(jdi->enable_gpio, 0);\n \n-\tgpiod_set_value(jdi->reset_gpio, 1);\n+\tgpiod_set_value_cansleep(jdi->reset_gpio, 1);\n \n-\tgpiod_set_value(jdi->dcdc_en_gpio, 0);\n+\tgpiod_set_value_cansleep(jdi->dcdc_en_gpio, 0);\n \n \treturn ret;\n }\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0571-dtoverlays-Add-overlays-for-JDI-LT070ME05000-1200x19.patch",
    "content": "From 5752746d0694ee607c2971735f2befc8a86fbab9 Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Thu, 15 Apr 2021 16:46:34 +0100\nSubject: [PATCH] dtoverlays: Add overlays for JDI LT070ME05000\n 1200x1920 DSI panel\n\nCredit to forum member gizmomouse on\nhttps://www.raspberrypi.org/forums/viewtopic.php?f=98&t=253912 and\nAndrey Vostrukhin of Harlab for these overlays.\n\nSee https://github.com/harlab/CM4_LCD_LT070ME05000 for\nschematics and docs for the adapter board to connect this panel which\nis found in the Asus/Google 2013 Nexus 7\" tablet and therefore\nrelatively easily available.\n\nNote that this uses 4 DSI data lanes, and therefore MUST be used\nwith DISP1 on a Compute Module. It can not be used on a standard\nPi.\n\nThere are two versions of the adapter board. V1 connects the\ndisplay controls to Pi GPIOs, whilst v2 uses an I2C GPIO expander\nso needs no additional connections beyond the FFC and power.\n\nThe touchscreen overlay for these panels varies, so that part\nis not configured.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n arch/arm/boot/dts/overlays/Makefile           |  2 +\n arch/arm/boot/dts/overlays/README             | 21 ++++++\n .../vc4-kms-dsi-lt070me05000-overlay.dts      | 69 +++++++++++++++++++\n .../vc4-kms-dsi-lt070me05000-v2-overlay.dts   | 64 +++++++++++++++++\n 4 files changed, 156 insertions(+)\n create mode 100644 arch/arm/boot/dts/overlays/vc4-kms-dsi-lt070me05000-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/vc4-kms-dsi-lt070me05000-v2-overlay.dts\n\n--- a/arch/arm/boot/dts/overlays/Makefile\n+++ b/arch/arm/boot/dts/overlays/Makefile\n@@ -213,6 +213,8 @@ dtbo-$(CONFIG_ARCH_BCM2835) += \\\n \tupstream-pi4.dtbo \\\n \tvc4-fkms-v3d.dtbo \\\n \tvc4-kms-dsi-7inch.dtbo \\\n+\tvc4-kms-dsi-lt070me05000.dtbo \\\n+\tvc4-kms-dsi-lt070me05000-v2.dtbo \\\n \tvc4-kms-kippah-7inch.dtbo \\\n \tvc4-kms-v3d.dtbo \\\n \tvc4-kms-v3d-pi4.dtbo \\\n--- a/arch/arm/boot/dts/overlays/README\n+++ b/arch/arm/boot/dts/overlays/README\n@@ -3158,6 +3158,27 @@ Load:   dtoverlay=vc4-kms-dsi-7inch\n Params: <None>\n \n \n+Name:   vc4-kms-dsi-lt070me05000\n+Info:   Enable a JDI LT070ME05000 DSI display on DSI1.\n+        Note that this is a 4 lane DSI device, so it will only work on a Compute\n+        Module.\n+        Requires vc4-kms-v3d to be loaded.\n+Load:   dtoverlay=vc4-kms-dsi-lt070me05000,<param>\n+Params: reset                   GPIO for the reset signal (default 17)\n+        enable                  GPIO for the enable signal (default 4)\n+        dcdc-en                 GPIO for the DC-DC converter enable (default 5)\n+\n+\n+Name:   vc4-kms-dsi-lt070me05000-v2\n+Info:   Enable a JDI LT070ME05000 DSI display on DSI1 using Harlab's V2\n+        interface board.\n+        Note that this is a 4 lane DSI device, so it will only work on a Compute\n+        Module.\n+        Requires vc4-kms-v3d to be loaded.\n+Load:   dtoverlay=vc4-kms-dsi-lt070me05000-v2\n+Params: <None>\n+\n+\n Name:   vc4-kms-kippah-7inch\n Info:   Enable the Adafruit DPI Kippah with the 7\" Ontat panel attached.\n         Requires vc4-kms-v3d to be loaded.\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/vc4-kms-dsi-lt070me05000-overlay.dts\n@@ -0,0 +1,69 @@\n+/*\n+ * Device Tree overlay to connect a JDI LT070ME05000 DSI panel to DSI1.\n+ * This uses 4 DSI data lanes, so can only be used with a Compute Module.\n+ *\n+ * Credit to forum user gizmomouse on\n+ * https://www.raspberrypi.org/forums/viewtopic.php?f=98&t=253912 and\n+ * Andrey Vostrukhin of Harlab for the overlay.\n+ *\n+ * Refer to https://github.com/harlab/CM4_LCD_LT070ME05000 for schematics and\n+ * other documentation.\n+ */\n+\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&dsi1>;\n+\t\t__overlay__{\n+\t\t\tstatus = \"okay\";\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tport {\n+\t\t\t\tdsi_out_port:endpoint {\n+\t\t\t\t\tremote-endpoint = <&panel_dsi_port>;\n+\t\t\t\t};\n+\t\t\t};\n+\n+\t\t\tlt070me05000:lt070me05000@0 {\n+\t\t\t\tcompatible    = \"jdi,lt070me05000\";\n+\t\t\t\tstatus        = \"okay\";\n+\t\t\t\treg           = <0>;\n+\t\t\t\treset-gpios   = <&gpio 17 1>;   // LCD RST\n+\t\t\t\tenable-gpios  = <&gpio 4 0>;    // LCD Enable\n+\t\t\t\tdcdc-en-gpios = <&gpio 5 0>;    // LCD DC-DC Enable\n+\t\t\t\tport {\n+\t\t\t\t\tpanel_dsi_port: endpoint {\n+\t\t\t\t\t\tremote-endpoint = <&dsi_out_port>;\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&gpio>;\n+\t\t__overlay__ {\n+\t\t\tlt070me05000_pins: lt070me05000_pins {\n+\t\t\t\tbrcm,pins = <4 5 17>;\n+\t\t\t\tbrcm,function = <1 1 1>; // out\n+\t\t\t\tbrcm,pull = <0 0 0>; // off\n+\t\t\t};\n+\t\t};\n+\n+\t};\n+\n+\t__overrides__ {\n+\t\treset = <&lt070me05000_pins>,\"brcm,pins:8\",\n+\t\t\t<&lt070me05000>,\"reset-gpios:4\";\n+\n+\t\tenable = <&lt070me05000_pins>,\"brcm,pins:0\",\n+\t\t\t<&lt070me05000>,\"enable-gpios:4\";\n+\n+\t\tdcdc-en = <&lt070me05000_pins>,\"brcm,pins:4\",\n+\t\t\t<&lt070me05000>,\"dcdc-en-gpios:4\";\n+\t};\n+};\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/vc4-kms-dsi-lt070me05000-v2-overlay.dts\n@@ -0,0 +1,64 @@\n+/*\n+ * Device Tree overlay to connect a JDI LT070ME05000 DSI panel to DSI1.\n+ * This uses 4 DSI data lanes, so can only be used with a Compute Module.\n+ *\n+ * The overlay is for V2 of Harlab's interface board that uses a PCA9536 to\n+ * handle the panel's control GPIOs instead of wiring it back to Pi GPIOs.\n+ *\n+ * Credit to Andrey Vostrukhin of Harlab for the overlay.\n+ *\n+ * Refer to https://github.com/harlab/CM4_LCD_LT070ME05000 for schematics and\n+ * other documentation.\n+ */\n+\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&i2c_csi_dsi>;\n+\t\t__overlay__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tpca: pca@41 {\n+\t\t\t\tcompatible = \"nxp,pca9536\";\n+\t\t\t\treg = <0x41>;\n+\t\t\t\tgpio-controller;\n+\t\t\t\t#gpio-cells = <2>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&dsi1>;\n+\t\t__overlay__{\n+\t\t\tstatus = \"okay\";\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tport {\n+\t\t\t\tdsi_out_port:endpoint {\n+\t\t\t\t\tremote-endpoint = <&panel_dsi_port>;\n+\t\t\t\t};\n+\t\t\t};\n+\n+\t\t\tlt070me05000:lt070me05000@0 {\n+\t\t\t\tcompatible    = \"jdi,lt070me05000\";\n+\t\t\t\tstatus        = \"okay\";\n+\t\t\t\treg           = <0>;\n+\t\t\t\treset-gpios   = <&pca 0 1>;\n+\t\t\t\tenable-gpios  = <&pca 2 0>;\n+\t\t\t\tdcdc-en-gpios = <&pca 1 0>;\n+\t\t\t\tport {\n+\t\t\t\t\tpanel_dsi_port: endpoint {\n+\t\t\t\t\t\tremote-endpoint = <&dsi_out_port>;\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\t\t\t};\n+\t\t};\n+\t};\n+};\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0572-clk-requests-Ignore-if-the-pointer-is-null.patch",
    "content": "From 2a5ffbf8ad9d4881f90402b1b4d7f5c2ab7b89e6 Mon Sep 17 00:00:00 2001\nFrom: Maxime Ripard <maxime@cerno.tech>\nDate: Wed, 21 Apr 2021 12:14:44 +0200\nSubject: [PATCH] clk: requests: Ignore if the pointer is null\n\nSigned-off-by: Maxime Ripard <maxime@cerno.tech>\n---\n drivers/clk/clk.c | 3 +++\n 1 file changed, 3 insertions(+)\n\n--- a/drivers/clk/clk.c\n+++ b/drivers/clk/clk.c\n@@ -2522,6 +2522,9 @@ void clk_request_done(struct clk_request\n {\n \tstruct clk_core *core = req->clk->core;\n \n+\tif (!req)\n+\t\treturn;\n+\n \tclk_prepare_lock();\n \n \tlist_del(&req->list);\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0573-drm-vc4-hvs-Make-the-HVS-bind-first.patch",
    "content": "From 7109030996578e85610f30dc60c04c952e87fb2a Mon Sep 17 00:00:00 2001\nFrom: Maxime Ripard <maxime@cerno.tech>\nDate: Thu, 25 Feb 2021 14:42:03 +0100\nSubject: [PATCH] drm/vc4: hvs: Make the HVS bind first\n\nWe'll need to have the HVS binding before the HDMI controllers so that\nwe can check whether the firmware allows to run in 4kp60. Reorder a bit\nthe component list, and document the current constraints we're aware of.\n\nAcked-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\nAcked-by: Thomas Zimmermann <tzimmermann@suse.de>\nSigned-off-by: Maxime Ripard <maxime@cerno.tech>\n---\n drivers/gpu/drm/vc4/vc4_drv.c | 11 ++++++++++-\n 1 file changed, 10 insertions(+), 1 deletion(-)\n\n--- a/drivers/gpu/drm/vc4/vc4_drv.c\n+++ b/drivers/gpu/drm/vc4/vc4_drv.c\n@@ -354,12 +354,21 @@ static const struct component_master_ops\n \t.unbind = vc4_drm_unbind,\n };\n \n+/*\n+ * This list determines the binding order of our components, and we have\n+ * a few constraints:\n+ *   - The TXP driver needs to be bound before the PixelValves (CRTC)\n+ *     but after the HVS to set the possible_crtc field properly\n+ *   - The HDMI driver needs to be bound after the HVS so that we can\n+ *     lookup the HVS maximum core clock rate and figure out if we\n+ *     support 4kp60 or not.\n+ */\n static struct platform_driver *const component_drivers[] = {\n+\t&vc4_hvs_driver,\n \t&vc4_hdmi_driver,\n \t&vc4_vec_driver,\n \t&vc4_dpi_driver,\n \t&vc4_dsi_driver,\n-\t&vc4_hvs_driver,\n \t&vc4_txp_driver,\n \t&vc4_crtc_driver,\n \t&vc4_firmware_kms_driver,\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0574-drm-vc4-hdmi-Properly-compute-the-BVB-clock-rate.patch",
    "content": "From acc8ac41d15594d4f735531c89bbeb03d85c344d Mon Sep 17 00:00:00 2001\nFrom: Maxime Ripard <maxime@cerno.tech>\nDate: Thu, 8 Oct 2020 16:06:08 +0200\nSubject: [PATCH] drm/vc4: hdmi: Properly compute the BVB clock rate\n\nThe BVB clock rate computation doesn't take into account a mode clock of\n594MHz that we're going to need to support 4k60.\n\nAcked-by: Thomas Zimmermann <tzimmermann@suse.de>\nReviewed-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\nSigned-off-by: Maxime Ripard <maxime@cerno.tech>\n---\n drivers/gpu/drm/vc4/vc4_hdmi.c | 17 +++++++++--------\n 1 file changed, 9 insertions(+), 8 deletions(-)\n\n--- a/drivers/gpu/drm/vc4/vc4_hdmi.c\n+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c\n@@ -93,7 +93,6 @@\n \n #define HSM_MIN_CLOCK_FREQ\t120000000\n #define CEC_CLOCK_FREQ 40000\n-#define VC4_HSM_MID_CLOCK 149985000\n \n static int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused)\n {\n@@ -814,7 +813,7 @@ static void vc4_hdmi_encoder_pre_crtc_co\n \t\tconn_state_to_vc4_hdmi_conn_state(conn_state);\n \tstruct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;\n \tstruct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);\n-\tunsigned long pixel_rate, hsm_rate;\n+\tunsigned long bvb_rate, pixel_rate, hsm_rate;\n \tint ret;\n \n \tret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev);\n@@ -863,12 +862,14 @@ static void vc4_hdmi_encoder_pre_crtc_co\n \n \tvc4_hdmi_cec_update_clk_div(vc4_hdmi);\n \n-\t/*\n-\t * FIXME: When the pixel freq is 594MHz (4k60), this needs to be setup\n-\t * at 300MHz.\n-\t */\n-\tvc4_hdmi->bvb_req = clk_request_start(vc4_hdmi->pixel_bvb_clock,\n-\t\t\t\t\t      (hsm_rate > VC4_HSM_MID_CLOCK ? 150000000 : 75000000));\n+\tif (pixel_rate > 297000000)\n+\t\tbvb_rate = 300000000;\n+\telse if (pixel_rate > 148500000)\n+\t\tbvb_rate = 150000000;\n+\telse\n+\t\tbvb_rate = 75000000;\n+\n+\tvc4_hdmi->bvb_req = clk_request_start(vc4_hdmi->pixel_bvb_clock, bvb_rate);\n \tif (IS_ERR(vc4_hdmi->bvb_req)) {\n \t\tDRM_ERROR(\"Failed to set pixel bvb clock rate: %ld\\n\", PTR_ERR(vc4_hdmi->bvb_req));\n \t\tclk_request_done(vc4_hdmi->hsm_req);\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0575-drm-vc4-hdmi-Enable-the-scrambler.patch",
    "content": "From b1388530046be8a912979594f9c43b47d6f242fe Mon Sep 17 00:00:00 2001\nFrom: Maxime Ripard <maxime@cerno.tech>\nDate: Thu, 8 Oct 2020 16:06:58 +0200\nSubject: [PATCH] drm/vc4: hdmi: Enable the scrambler\n\nThe HDMI controller on the BCM2711 includes a scrambler in order to\nreach the HDMI 2.0 modes that require it. Let's add the support for it.\n\nAcked-by: Thomas Zimmermann <tzimmermann@suse.de>\nSigned-off-by: Maxime Ripard <maxime@cerno.tech>\n---\n drivers/gpu/drm/vc4/vc4_hdmi.c      | 64 +++++++++++++++++++++++++++++\n drivers/gpu/drm/vc4/vc4_hdmi_regs.h |  3 ++\n 2 files changed, 67 insertions(+)\n\n--- a/drivers/gpu/drm/vc4/vc4_hdmi.c\n+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c\n@@ -35,6 +35,7 @@\n #include <drm/drm_edid.h>\n #include <drm/drm_probe_helper.h>\n #include <drm/drm_simple_kms_helper.h>\n+#include <drm/drm_scdc_helper.h>\n #include <linux/clk.h>\n #include <linux/component.h>\n #include <linux/i2c.h>\n@@ -77,6 +78,8 @@\n #define VC5_HDMI_VERTB_VSPO_SHIFT\t\t16\n #define VC5_HDMI_VERTB_VSPO_MASK\t\tVC4_MASK(29, 16)\n \n+#define VC5_HDMI_SCRAMBLER_CTL_ENABLE\t\tBIT(0)\n+\n #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_SHIFT\t8\n #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK\tVC4_MASK(10, 8)\n \n@@ -518,6 +521,64 @@ static void vc4_hdmi_set_infoframes(stru\n \tvc4_hdmi_set_hdr_infoframe(encoder);\n }\n \n+static bool vc4_hdmi_supports_scrambling(struct drm_encoder *encoder,\n+\t\t\t\t\t struct drm_display_mode *mode)\n+{\n+\tstruct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);\n+\tstruct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);\n+\tstruct drm_display_info *display = &vc4_hdmi->connector.display_info;\n+\n+\tif (!vc4_encoder->hdmi_monitor)\n+\t\treturn false;\n+\n+\tif (!display->hdmi.scdc.supported ||\n+\t    !display->hdmi.scdc.scrambling.supported)\n+\t\treturn false;\n+\n+\treturn true;\n+}\n+\n+static void vc4_hdmi_enable_scrambling(struct drm_encoder *encoder)\n+{\n+\tstruct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;\n+\tstruct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);\n+\n+\tif (!vc4_hdmi_supports_scrambling(encoder, mode))\n+\t\treturn;\n+\n+\tif (!vc4_hdmi_mode_needs_scrambling(mode))\n+\t\treturn;\n+\n+\tdrm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, true);\n+\tdrm_scdc_set_scrambling(vc4_hdmi->ddc, true);\n+\n+\tHDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) |\n+\t\t   VC5_HDMI_SCRAMBLER_CTL_ENABLE);\n+}\n+\n+static void vc4_hdmi_disable_scrambling(struct drm_encoder *encoder)\n+{\n+\tstruct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);\n+\tstruct drm_crtc *crtc = encoder->crtc;\n+\n+\t/*\n+\t * At boot, encoder->crtc will be NULL. Since we don't know the\n+\t * state of the scrambler and in order to avoid any\n+\t * inconsistency, let's disable it all the time.\n+\t */\n+\tif (crtc && !vc4_hdmi_supports_scrambling(encoder, &crtc->mode))\n+\t\treturn;\n+\n+\tif (crtc && !vc4_hdmi_mode_needs_scrambling(&crtc->mode))\n+\t\treturn;\n+\n+\tHDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) &\n+\t\t   ~VC5_HDMI_SCRAMBLER_CTL_ENABLE);\n+\n+\tdrm_scdc_set_scrambling(vc4_hdmi->ddc, false);\n+\tdrm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, false);\n+}\n+\n static void vc4_hdmi_encoder_post_crtc_disable(struct drm_encoder *encoder,\n \t\t\t\t\t       struct drm_atomic_state *state)\n {\n@@ -530,6 +591,8 @@ static void vc4_hdmi_encoder_post_crtc_d\n \n \tHDMI_WRITE(HDMI_VID_CTL,\n \t\t   HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_BLANKPIX);\n+\n+\tvc4_hdmi_disable_scrambling(encoder);\n }\n \n static void vc4_hdmi_encoder_post_crtc_powerdown(struct drm_encoder *encoder,\n@@ -980,6 +1043,7 @@ static void vc4_hdmi_encoder_post_crtc_e\n \t}\n \n \tvc4_hdmi_recenter_fifo(vc4_hdmi);\n+\tvc4_hdmi_enable_scrambling(encoder);\n }\n \n static void vc4_hdmi_encoder_enable(struct drm_encoder *encoder)\n--- a/drivers/gpu/drm/vc4/vc4_hdmi_regs.h\n+++ b/drivers/gpu/drm/vc4/vc4_hdmi_regs.h\n@@ -100,6 +100,7 @@ enum vc4_hdmi_field {\n \tHDMI_RM_FORMAT,\n \tHDMI_RM_OFFSET,\n \tHDMI_SCHEDULER_CONTROL,\n+\tHDMI_SCRAMBLER_CTL,\n \tHDMI_SW_RESET_CONTROL,\n \tHDMI_TX_PHY_CHANNEL_SWAP,\n \tHDMI_TX_PHY_CLK_DIV,\n@@ -238,6 +239,7 @@ static const struct vc4_hdmi_register vc\n \tVC4_HDMI_REG(HDMI_GCP_CONFIG, 0x178),\n \tVC4_HDMI_REG(HDMI_GCP_WORD_1, 0x17c),\n \tVC4_HDMI_REG(HDMI_HOTPLUG, 0x1a8),\n+\tVC4_HDMI_REG(HDMI_SCRAMBLER_CTL, 0x1c4),\n \n \tVC5_DVP_REG(HDMI_CLOCK_STOP, 0x0bc),\n \tVC5_DVP_REG(HDMI_VEC_INTERFACE_XBAR, 0x0f0),\n@@ -317,6 +319,7 @@ static const struct vc4_hdmi_register vc\n \tVC4_HDMI_REG(HDMI_GCP_CONFIG, 0x178),\n \tVC4_HDMI_REG(HDMI_GCP_WORD_1, 0x17c),\n \tVC4_HDMI_REG(HDMI_HOTPLUG, 0x1a8),\n+\tVC4_HDMI_REG(HDMI_SCRAMBLER_CTL, 0x1c4),\n \n \tVC5_DVP_REG(HDMI_CLOCK_STOP, 0x0bc),\n \tVC5_DVP_REG(HDMI_VEC_INTERFACE_XBAR, 0x0f0),\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0576-drm-vc4-hdmi-Raise-the-maximum-clock-rate.patch",
    "content": "From 4950d441d18161b2432965ba3fc99382beafdf02 Mon Sep 17 00:00:00 2001\nFrom: Maxime Ripard <maxime@cerno.tech>\nDate: Thu, 8 Oct 2020 16:08:06 +0200\nSubject: [PATCH] drm/vc4: hdmi: Raise the maximum clock rate\n\nNow that we have the infrastructure in place, we can raise the maximum\npixel rate we can reach for HDMI0 on the BCM2711.\n\nHDMI1 is left untouched since its pixelvalve has a smaller FIFO and\nwould need a clock faster than what we can provide to support the same\nmodes.\n\nAcked-by: Thomas Zimmermann <tzimmermann@suse.de>\nReviewed-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\nSigned-off-by: Maxime Ripard <maxime@cerno.tech>\n---\n drivers/gpu/drm/vc4/vc4_hdmi.c | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/drivers/gpu/drm/vc4/vc4_hdmi.c\n+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c\n@@ -2434,7 +2434,7 @@ static const struct vc4_hdmi_variant bcm\n \t.encoder_type\t\t= VC4_ENCODER_TYPE_HDMI0,\n \t.debugfs_name\t\t= \"hdmi0_regs\",\n \t.card_name\t\t= \"vc4-hdmi-0\",\n-\t.max_pixel_clock\t= 297000000,\n+\t.max_pixel_clock\t= 600000000,\n \t.registers\t\t= vc5_hdmi_hdmi0_fields,\n \t.num_registers\t\t= ARRAY_SIZE(vc5_hdmi_hdmi0_fields),\n \t.phy_lane_mapping\t= {\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0577-vc4-drm-hdmi-Handle-case-when-bvb-clock-is-null.patch",
    "content": "From 33e8e066af31c3af1d18d615f5e8ab5e528e0000 Mon Sep 17 00:00:00 2001\nFrom: Dom Cobley <popcornmix@gmail.com>\nDate: Wed, 21 Apr 2021 15:15:42 +0100\nSubject: [PATCH] vc4/drm: hdmi: Handle case when bvb clock is null\n\nPi2/3 have no bvb clock but want the other clocks to remain enabled here\n\nSee: https://github.com/raspberrypi/linux/issues/4299\nSigned-off-by: Dom Cobley <popcornmix@gmail.com>\n---\n drivers/gpu/drm/vc4/vc4_hdmi.c | 9 ++++++---\n 1 file changed, 6 insertions(+), 3 deletions(-)\n\n--- a/drivers/gpu/drm/vc4/vc4_hdmi.c\n+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c\n@@ -608,7 +608,8 @@ static void vc4_hdmi_encoder_post_crtc_p\n \t\t   HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE);\n \n \tclk_disable_unprepare(vc4_hdmi->pixel_bvb_clock);\n-\tclk_request_done(vc4_hdmi->bvb_req);\n+\tif (vc4_hdmi->bvb_req)\n+\t\tclk_request_done(vc4_hdmi->bvb_req);\n \tclk_disable_unprepare(vc4_hdmi->hsm_clock);\n \tclk_request_done(vc4_hdmi->hsm_req);\n \tclk_disable_unprepare(vc4_hdmi->pixel_clock);\n@@ -932,7 +933,8 @@ static void vc4_hdmi_encoder_pre_crtc_co\n \telse\n \t\tbvb_rate = 75000000;\n \n-\tvc4_hdmi->bvb_req = clk_request_start(vc4_hdmi->pixel_bvb_clock, bvb_rate);\n+\tif (vc4_hdmi->pixel_bvb_clock)\n+\t\tvc4_hdmi->bvb_req = clk_request_start(vc4_hdmi->pixel_bvb_clock, bvb_rate);\n \tif (IS_ERR(vc4_hdmi->bvb_req)) {\n \t\tDRM_ERROR(\"Failed to set pixel bvb clock rate: %ld\\n\", PTR_ERR(vc4_hdmi->bvb_req));\n \t\tclk_request_done(vc4_hdmi->hsm_req);\n@@ -944,7 +946,8 @@ static void vc4_hdmi_encoder_pre_crtc_co\n \tret = clk_prepare_enable(vc4_hdmi->pixel_bvb_clock);\n \tif (ret) {\n \t\tDRM_ERROR(\"Failed to turn on pixel bvb clock: %d\\n\", ret);\n-\t\tclk_request_done(vc4_hdmi->bvb_req);\n+\t\tif (vc4_hdmi->bvb_req)\n+\t\t\tclk_request_done(vc4_hdmi->bvb_req);\n \t\tclk_request_done(vc4_hdmi->hsm_req);\n \t\tclk_disable_unprepare(vc4_hdmi->hsm_clock);\n \t\tclk_disable_unprepare(vc4_hdmi->pixel_clock);\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0578-overlays-spi-rtc-Add-ds3232-and-ds3234.patch",
    "content": "From 8273b9e71c1f5c1f6f74faac21de64bf42686817 Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.com>\nDate: Mon, 19 Apr 2021 10:33:24 +0100\nSubject: [PATCH] overlays: spi-rtc: Add ds3232 and ds3234\n\nExtend the spi-rtc overlay to support the ds3232 and ds3234 RTCs, as\nwell as adding parameters to select difference SPI controllers and\nchip selects.\n\nN.B. The default CS is now active-low - use the \"cs_high\" parameter to\noverride this.\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.com>\n---\n arch/arm/boot/dts/overlays/README             | 12 +++-\n .../arm/boot/dts/overlays/spi-rtc-overlay.dts | 58 ++++++++++++++++---\n 2 files changed, 61 insertions(+), 9 deletions(-)\n\n--- a/arch/arm/boot/dts/overlays/README\n+++ b/arch/arm/boot/dts/overlays/README\n@@ -2689,7 +2689,17 @@ Params: <None>\n Name:   spi-rtc\n Info:   Adds support for a number of SPI Real Time Clock devices\n Load:   dtoverlay=spi-rtc,<param>=<val>\n-Params: pcf2123                 Select the PCF2123 device\n+Params: ds3232                  Select the DS3232 device\n+        ds3234                  Select the DS3234 device\n+        pcf2123                 Select the PCF2123 device\n+\n+        spi0_0                  Use spi0.0 (default)\n+        spi0_1                  Use spi0.1\n+        spi1_0                  Use spi1.0\n+        spi1_1                  Use spi1.1\n+        spi2_0                  Use spi2.0\n+        spi2_1                  Use spi2.1\n+        cs_high                 This device requires an active-high CS\n \n \n Name:   spi0-1cs\n--- a/arch/arm/boot/dts/overlays/spi-rtc-overlay.dts\n+++ b/arch/arm/boot/dts/overlays/spi-rtc-overlay.dts\n@@ -1,3 +1,4 @@\n+// Definitions for several SPI-based Real Time Clocks\n /dts-v1/;\n /plugin/;\n \n@@ -5,29 +6,70 @@\n \tcompatible = \"brcm,bcm2835\";\n \n \tfragment@0 {\n-\t\ttarget = <&spidev0>;\n+\t\ttarget = <&rtc>;\n \t\t__dormant__ {\n-\t\t\tstatus = \"disabled\";\n+\t\t\tcompatible = \"maxim,ds3232\";\n \t\t};\n \t};\n \n \tfragment@1 {\n-\t\ttarget = <&spi0>;\n+\t\ttarget = <&rtc>;\n+\t\t__dormant__ {\n+\t\t\tcompatible = \"maxim,ds3234\";\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&rtc>;\n \t\t__dormant__ {\n+\t\t\tcompatible = \"nxp,rtc-pcf2123\";\n+\t\t};\n+\t};\n+\n+\tspidev: fragment@100 {\n+\t\ttarget = <&spidev0>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\tfrag101: fragment@101 {\n+\t\ttarget = <&spi0>;\n+\t\t__overlay__ {\n \t\t\t#address-cells = <1>;\n \t\t\t#size-cells = <0>;\n \t\t\tstatus = \"okay\";\n \n-\t\t\trtc-pcf2123@0 {\n-\t\t\t\tcompatible = \"nxp,rtc-pcf2123\";\n-\t\t\t\tspi-max-frequency = <5000000>;\n-\t\t\t\tspi-cs-high = <1>;\n+\t\t\trtc: rtc@0 {\n \t\t\t\treg = <0>;\n+\t\t\t\tspi-max-frequency = <5000000>;\n \t\t\t};\n \t\t};\n \t};\n \n \t__overrides__ {\n-\t\tpcf2123 = <0>, \"=0=1\";\n+\t\tspi0_0 = <&spidev>, \"target:0=\",<&spidev0>,\n+\t\t         <&frag101>, \"target:0=\",<&spi0>,\n+\t\t         <&rtc>, \"reg:0=0\";\n+\t\tspi0_1 = <&spidev>, \"target:0=\",<&spidev1>,\n+\t\t         <&frag101>, \"target:0=\",<&spi0>,\n+\t\t         <&rtc>, \"reg:0=1\";\n+\t\tspi1_0 = <0>,\"-100\",\n+\t\t         <&frag101>, \"target:0=\",<&spi1>,\n+\t\t         <&rtc>, \"reg:0=0\";\n+\t\tspi1_1 = <0>,\"-100\",\n+\t\t         <&frag101>, \"target:0=\",<&spi1>,\n+\t\t         <&rtc>, \"reg:0=1\";\n+\t\tspi2_0 = <0>,\"-100\",\n+\t\t         <&frag101>, \"target:0=\",<&spi2>,\n+\t\t         <&rtc>, \"reg:0=0\";\n+\t\tspi2_1 = <0>,\"-100\",\n+\t\t         <&frag101>, \"target:0=\",<&spi2>,\n+\t\t         <&rtc>, \"reg:0=1\";\n+\t\tcs_high = <&rtc>, \"spi-cs-high?\";\n+\n+\t\tds3232 = <0>,\"+0\";\n+\t\tds3234 = <0>,\"+1\";\n+\t\tpcf2123 = <0>,\"+2\";\n \t};\n };\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0579-drm-vc4-Fix-VEC-address-for-BCM2711-in-the-devicetre.patch",
    "content": "From 2d7a55e6a467b54ea40366f689e7702b88383e38 Mon Sep 17 00:00:00 2001\nFrom: kFYatek <4499762+kFYatek@users.noreply.github.com>\nDate: Sat, 27 Mar 2021 21:43:33 +0100\nSubject: [PATCH] drm/vc4: Fix VEC address for BCM2711 in the\n devicetrees\n\nThe VEC has a different address (0x7ec13000) on the BCM2711 (used in\ne.g. Raspberry Pi 4) compared to BCM238x (e.g. Pi 3 and earlier). This\nwas erroneously not taken account for.\n\nDefinition of the VEC in the devicetrees had to be moved from\nbcm283x.dtsi to bcm2711.dtsi and bcm2835-common.dtsi to allow for this\ndifferentiation.\n\nSigned-off-by: Mateusz Kwiatkowski <kfyatek+publicgit@gmail.com>\n---\n arch/arm/boot/dts/bcm2711.dtsi        | 8 ++++++++\n arch/arm/boot/dts/bcm2835-common.dtsi | 8 ++++++++\n arch/arm/boot/dts/bcm283x.dtsi        | 8 --------\n 3 files changed, 16 insertions(+), 8 deletions(-)\n\n--- a/arch/arm/boot/dts/bcm2711.dtsi\n+++ b/arch/arm/boot/dts/bcm2711.dtsi\n@@ -301,6 +301,14 @@\n \t\t\tstatus = \"disabled\";\n \t\t};\n \n+\t\tvec: vec@7ec13000 {\n+\t\t\tcompatible = \"brcm,bcm2835-vec\";\n+\t\t\treg = <0x7ec13000 0x1000>;\n+\t\t\tclocks = <&clocks BCM2835_CLOCK_VEC>;\n+\t\t\tinterrupts = <2 27>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n \t\tdvp: clock@7ef00000 {\n \t\t\tcompatible = \"brcm,brcm2711-dvp\";\n \t\t\treg = <0x7ef00000 0x10>;\n--- a/arch/arm/boot/dts/bcm2835-common.dtsi\n+++ b/arch/arm/boot/dts/bcm2835-common.dtsi\n@@ -106,6 +106,14 @@\n \t\t\tstatus = \"okay\";\n \t\t};\n \n+\t\tvec: vec@7e806000 {\n+\t\t\tcompatible = \"brcm,bcm2835-vec\";\n+\t\t\treg = <0x7e806000 0x1000>;\n+\t\t\tclocks = <&clocks BCM2835_CLOCK_VEC>;\n+\t\t\tinterrupts = <2 27>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n \t\tpixelvalve@7e807000 {\n \t\t\tcompatible = \"brcm,bcm2835-pixelvalve2\";\n \t\t\treg = <0x7e807000 0x100>;\n--- a/arch/arm/boot/dts/bcm283x.dtsi\n+++ b/arch/arm/boot/dts/bcm283x.dtsi\n@@ -490,14 +490,6 @@\n \t\t\tstatus = \"disabled\";\n \t\t};\n \n-\t\tvec: vec@7e806000 {\n-\t\t\tcompatible = \"brcm,bcm2835-vec\";\n-\t\t\treg = <0x7e806000 0x1000>;\n-\t\t\tclocks = <&clocks BCM2835_CLOCK_VEC>;\n-\t\t\tinterrupts = <2 27>;\n-\t\t\tstatus = \"disabled\";\n-\t\t};\n-\n \t\tusb: usb@7e980000 {\n \t\t\tcompatible = \"brcm,bcm2835-usb\";\n \t\t\treg = <0x7e980000 0x10000>;\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0580-drm-vc4-Separate-VEC-compatible-variants.patch",
    "content": "From 8d75ba91d48ee9fd39284bf44ca5e729e134e18c Mon Sep 17 00:00:00 2001\nFrom: kFYatek <4499762+kFYatek@users.noreply.github.com>\nDate: Sat, 27 Mar 2021 21:43:40 +0100\nSubject: [PATCH] drm/vc4: Separate VEC compatible variants\n\nThe VEC's DAC on BCM2711 is slightly different compared to the one on\nBCM283x and needs different configuration. In particular, bit 3\n(mask 0x8) switches the BCM2711 DAC input to \"self-test input data\",\nwhich makes the output unusable. Separating two compatible variants in\ndevicetrees and the DRM driver was therefore necessary.\n\nThe configurations used for both variants have been borrowed from\nRaspberry Pi (model 3B for BCM283x, 4B for BCM2711) firmware defaults.\n\nSigned-off-by: Mateusz Kwiatkowski <kfyatek+publicgit@gmail.com>\n---\n .../bindings/display/brcm,bcm2835-vec.yaml    |  4 ++-\n arch/arm/boot/dts/bcm2711.dtsi                |  2 +-\n drivers/gpu/drm/vc4/vc4_vec.c                 | 27 +++++++++++++++----\n 3 files changed, 26 insertions(+), 7 deletions(-)\n\n--- a/Documentation/devicetree/bindings/display/brcm,bcm2835-vec.yaml\n+++ b/Documentation/devicetree/bindings/display/brcm,bcm2835-vec.yaml\n@@ -11,7 +11,9 @@ maintainers:\n \n properties:\n   compatible:\n-    const: brcm,bcm2835-vec\n+    enum:\n+      - brcm,bcm2835-vec\n+      - brcm,bcm2711-vec\n \n   reg:\n     maxItems: 1\n--- a/arch/arm/boot/dts/bcm2711.dtsi\n+++ b/arch/arm/boot/dts/bcm2711.dtsi\n@@ -302,7 +302,7 @@\n \t\t};\n \n \t\tvec: vec@7ec13000 {\n-\t\t\tcompatible = \"brcm,bcm2835-vec\";\n+\t\t\tcompatible = \"brcm,bcm2711-vec\";\n \t\t\treg = <0x7ec13000 0x1000>;\n \t\t\tclocks = <&clocks BCM2835_CLOCK_VEC>;\n \t\t\tinterrupts = <2 27>;\n--- a/drivers/gpu/drm/vc4/vc4_vec.c\n+++ b/drivers/gpu/drm/vc4/vc4_vec.c\n@@ -154,9 +154,14 @@\n #define VEC_DAC_MISC_DAC_RST_N\t\tBIT(0)\n \n \n+struct vc4_vec_variant {\n+\tu32 dac_config;\n+};\n+\n /* General VEC hardware state. */\n struct vc4_vec {\n \tstruct platform_device *pdev;\n+\tconst struct vc4_vec_variant *variant;\n \n \tstruct drm_encoder *encoder;\n \tstruct drm_connector *connector;\n@@ -451,10 +456,7 @@ static void vc4_vec_encoder_enable(struc\n \tVEC_WRITE(VEC_CONFIG2,\n \t\t  VEC_CONFIG2_UV_DIG_DIS | VEC_CONFIG2_RGB_DIG_DIS);\n \tVEC_WRITE(VEC_CONFIG3, VEC_CONFIG3_HORIZ_LEN_STD);\n-\tVEC_WRITE(VEC_DAC_CONFIG,\n-\t\t  VEC_DAC_CONFIG_DAC_CTRL(0xc) |\n-\t\t  VEC_DAC_CONFIG_DRIVER_CTRL(0xc) |\n-\t\t  VEC_DAC_CONFIG_LDO_BIAS_CTRL(0x46));\n+\tVEC_WRITE(VEC_DAC_CONFIG, vec->variant->dac_config);\n \n \t/* Mask all interrupts. */\n \tVEC_WRITE(VEC_MASK0, 0);\n@@ -507,8 +509,21 @@ static const struct drm_encoder_helper_f\n \t.atomic_mode_set = vc4_vec_encoder_atomic_mode_set,\n };\n \n+static const struct vc4_vec_variant bcm2835_vec_variant = {\n+\t.dac_config = VEC_DAC_CONFIG_DAC_CTRL(0xc) |\n+\t\t      VEC_DAC_CONFIG_DRIVER_CTRL(0xc) |\n+\t\t      VEC_DAC_CONFIG_LDO_BIAS_CTRL(0x46)\n+};\n+\n+static const struct vc4_vec_variant bcm2711_vec_variant = {\n+\t.dac_config = VEC_DAC_CONFIG_DAC_CTRL(0x0) |\n+\t\t      VEC_DAC_CONFIG_DRIVER_CTRL(0x80) |\n+\t\t      VEC_DAC_CONFIG_LDO_BIAS_CTRL(0x61)\n+};\n+\n static const struct of_device_id vc4_vec_dt_match[] = {\n-\t{ .compatible = \"brcm,bcm2835-vec\", .data = NULL },\n+\t{ .compatible = \"brcm,bcm2835-vec\", .data = &bcm2835_vec_variant },\n+\t{ .compatible = \"brcm,bcm2711-vec\", .data = &bcm2711_vec_variant },\n \t{ /* sentinel */ },\n };\n \n@@ -546,6 +561,8 @@ static int vc4_vec_bind(struct device *d\n \tvec->encoder = &vc4_vec_encoder->base.base;\n \n \tvec->pdev = pdev;\n+\tvec->variant = (const struct vc4_vec_variant *)\n+\t\tof_device_get_match_data(dev);\n \tvec->regs = vc4_ioremap_regs(pdev, 0);\n \tif (IS_ERR(vec->regs))\n \t\treturn PTR_ERR(vec->regs);\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0581-clk-requests-Dereference-the-request-pointer-after-t.patch",
    "content": "From 491c6fbbe8fadead32fbe316fd5d0f21e9aa01f2 Mon Sep 17 00:00:00 2001\nFrom: Maxime Ripard <maxime@cerno.tech>\nDate: Thu, 22 Apr 2021 10:45:37 +0200\nSubject: [PATCH] clk: requests: Dereference the request pointer after\n the check\n\nThe current code will first dereference the req pointer and then test if\nit's NULL, resulting in a NULL pointer dereference if req is indeed\nNULL. Reorder the test and derefence to avoid the issue\n\nSigned-off-by: Maxime Ripard <maxime@cerno.tech>\n---\n drivers/clk/clk.c | 3 ++-\n 1 file changed, 2 insertions(+), 1 deletion(-)\n\n--- a/drivers/clk/clk.c\n+++ b/drivers/clk/clk.c\n@@ -2520,10 +2520,11 @@ EXPORT_SYMBOL_GPL(clk_request_start);\n  */\n void clk_request_done(struct clk_request *req)\n {\n-\tstruct clk_core *core = req->clk->core;\n+\tstruct clk_core *core;\n \n \tif (!req)\n \t\treturn;\n+\tcore = req->clk->core;\n \n \tclk_prepare_lock();\n \n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0582-staging-bcm2835-codec-Fix-support-for-levels-4.1-and.patch",
    "content": "From b935f992a71593042f118d004df7afb9c7f8b2f2 Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Thu, 25 Mar 2021 18:28:40 +0000\nSubject: [PATCH] staging/bcm2835-codec: Fix support for levels 4.1 and\n 4.2\n\nThe driver said it supported H264 levels 4.1 and 4.2, but\nwas missing the V4L2 to MMAL mappings.\n\nAdd in those mappings.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n .../vc04_services/bcm2835-codec/bcm2835-v4l2-codec.c  | 11 +++++++++++\n 1 file changed, 11 insertions(+)\n\n--- a/drivers/staging/vc04_services/bcm2835-codec/bcm2835-v4l2-codec.c\n+++ b/drivers/staging/vc04_services/bcm2835-codec/bcm2835-v4l2-codec.c\n@@ -1789,6 +1789,17 @@ static int bcm2835_codec_set_level_profi\n \t\tcase V4L2_MPEG_VIDEO_H264_LEVEL_4_0:\n \t\t\tparam.level = MMAL_VIDEO_LEVEL_H264_4;\n \t\t\tbreak;\n+\t\t/*\n+\t\t * Note that the hardware spec is level 4.0. Levels above that\n+\t\t * are there for correctly encoding the headers and may not\n+\t\t * be able to keep up with real-time.\n+\t\t */\n+\t\tcase V4L2_MPEG_VIDEO_H264_LEVEL_4_1:\n+\t\t\tparam.level = MMAL_VIDEO_LEVEL_H264_41;\n+\t\t\tbreak;\n+\t\tcase V4L2_MPEG_VIDEO_H264_LEVEL_4_2:\n+\t\t\tparam.level = MMAL_VIDEO_LEVEL_H264_42;\n+\t\t\tbreak;\n \t\tdefault:\n \t\t\t/* Should never get here */\n \t\t\tbreak;\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0583-staging-bcm2835-codec-Set-the-colourspace-appropriat.patch",
    "content": "From 8c0f9780d9a1b7812e01605bcac497503b175f53 Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Thu, 4 Feb 2021 19:08:23 +0000\nSubject: [PATCH] staging/bcm2835-codec: Set the colourspace\n appropriately for RGB formats\n\nVideo decode supports YUV and RGB formats. YUV needs to report SMPTE170M\nor REC709 appropriately, whilst RGB should report SRGB.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n .../bcm2835-codec/bcm2835-v4l2-codec.c        | 51 +++++++++++++------\n 1 file changed, 36 insertions(+), 15 deletions(-)\n\n--- a/drivers/staging/vc04_services/bcm2835-codec/bcm2835-v4l2-codec.c\n+++ b/drivers/staging/vc04_services/bcm2835-codec/bcm2835-v4l2-codec.c\n@@ -930,23 +930,43 @@ static void send_eos_event(struct bcm283\n \tv4l2_event_queue_fh(&ctx->fh, &ev);\n }\n \n-static void color_mmal2v4l(struct bcm2835_codec_ctx *ctx, u32 mmal_color_space)\n+static void color_mmal2v4l(struct bcm2835_codec_ctx *ctx, u32 encoding,\n+\t\t\t   u32 color_space)\n {\n-\tswitch (mmal_color_space) {\n-\tcase MMAL_COLOR_SPACE_ITUR_BT601:\n-\t\tctx->colorspace = V4L2_COLORSPACE_REC709;\n-\t\tctx->xfer_func = V4L2_XFER_FUNC_709;\n-\t\tctx->ycbcr_enc = V4L2_YCBCR_ENC_601;\n-\t\tctx->quant = V4L2_QUANTIZATION_LIM_RANGE;\n-\t\tbreak;\n+\tint is_rgb;\n \n-\tcase MMAL_COLOR_SPACE_ITUR_BT709:\n-\t\tctx->colorspace = V4L2_COLORSPACE_REC709;\n-\t\tctx->xfer_func = V4L2_XFER_FUNC_709;\n-\t\tctx->ycbcr_enc = V4L2_YCBCR_ENC_709;\n-\t\tctx->quant = V4L2_QUANTIZATION_LIM_RANGE;\n+\tswitch (encoding) {\n+\tcase MMAL_ENCODING_I420:\n+\tcase MMAL_ENCODING_YV12:\n+\tcase MMAL_ENCODING_NV12:\n+\tcase MMAL_ENCODING_NV21:\n+\tcase V4L2_PIX_FMT_YUYV:\n+\tcase V4L2_PIX_FMT_YVYU:\n+\tcase V4L2_PIX_FMT_UYVY:\n+\tcase V4L2_PIX_FMT_VYUY:\n+\t\t/* YUV based colourspaces */\n+\t\tswitch (color_space) {\n+\t\tcase MMAL_COLOR_SPACE_ITUR_BT601:\n+\t\t\tctx->colorspace = V4L2_COLORSPACE_SMPTE170M;\n+\t\t\tbreak;\n+\n+\t\tcase MMAL_COLOR_SPACE_ITUR_BT709:\n+\t\t\tctx->colorspace = V4L2_COLORSPACE_REC709;\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tbreak;\n+\t\t}\n+\t\tbreak;\n+\tdefault:\n+\t\t/* RGB based colourspaces */\n+\t\tctx->colorspace = V4L2_COLORSPACE_SRGB;\n \t\tbreak;\n \t}\n+\tctx->xfer_func = V4L2_MAP_XFER_FUNC_DEFAULT(ctx->colorspace);\n+\tctx->ycbcr_enc = V4L2_MAP_YCBCR_ENC_DEFAULT(ctx->colorspace);\n+\tis_rgb = ctx->colorspace == V4L2_COLORSPACE_SRGB;\n+\tctx->quant = V4L2_MAP_QUANTIZATION_DEFAULT(is_rgb, ctx->colorspace,\n+\t\t\t\t\t\t   ctx->ycbcr_enc);\n }\n \n static void handle_fmt_changed(struct bcm2835_codec_ctx *ctx,\n@@ -985,7 +1005,8 @@ static void handle_fmt_changed(struct bc\n \tq_data->height = format->es.video.height;\n \tq_data->sizeimage = format->buffer_size_min;\n \tif (format->es.video.color_space)\n-\t\tcolor_mmal2v4l(ctx, format->es.video.color_space);\n+\t\tcolor_mmal2v4l(ctx, format->format.encoding,\n+\t\t\t       format->es.video.color_space);\n \n \tq_data->aspect_ratio.numerator = format->es.video.par.num;\n \tq_data->aspect_ratio.denominator = format->es.video.par.den;\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0584-staging-bcm2835-codec-Pass-corrupt-frame-flag.patch",
    "content": "From 4dfae141d031d0d85c5d338a09fa9253343861e3 Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Wed, 9 Dec 2020 18:53:56 +0000\nSubject: [PATCH] staging/bcm2835-codec: Pass corrupt frame flag.\n\nMMAL has the flag MMAL_BUFFER_HEADER_FLAG_CORRUPTED but that\nwasn't being passed through, so add it.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n .../vc04_services/bcm2835-codec/bcm2835-v4l2-codec.c        | 6 +++++-\n 1 file changed, 5 insertions(+), 1 deletion(-)\n\n--- a/drivers/staging/vc04_services/bcm2835-codec/bcm2835-v4l2-codec.c\n+++ b/drivers/staging/vc04_services/bcm2835-codec/bcm2835-v4l2-codec.c\n@@ -1019,6 +1019,7 @@ static void op_buffer_cb(struct vchiq_mm\n \t\t\t struct mmal_buffer *mmal_buf)\n {\n \tstruct bcm2835_codec_ctx *ctx = port->cb_ctx;\n+\tenum vb2_buffer_state buf_state = VB2_BUF_STATE_DONE;\n \tstruct m2m_mmal_buffer *buf;\n \tstruct vb2_v4l2_buffer *vb2;\n \n@@ -1075,6 +1076,9 @@ static void op_buffer_cb(struct vchiq_mm\n \t\tvb2->flags |= V4L2_BUF_FLAG_LAST;\n \t}\n \n+\tif (mmal_buf->mmal_flags & MMAL_BUFFER_HEADER_FLAG_CORRUPTED)\n+\t\tbuf_state = VB2_BUF_STATE_ERROR;\n+\n \t/* vb2 timestamps in nsecs, mmal in usecs */\n \tvb2->vb2_buf.timestamp = mmal_buf->pts * 1000;\n \n@@ -1082,7 +1086,7 @@ static void op_buffer_cb(struct vchiq_mm\n \tif (mmal_buf->mmal_flags & MMAL_BUFFER_HEADER_FLAG_KEYFRAME)\n \t\tvb2->flags |= V4L2_BUF_FLAG_KEYFRAME;\n \n-\tvb2_buffer_done(&vb2->vb2_buf, VB2_BUF_STATE_DONE);\n+\tvb2_buffer_done(&vb2->vb2_buf, buf_state);\n \tctx->num_op_buffers++;\n \n \tv4l2_dbg(2, debug, &ctx->dev->v4l2_dev, \"%s: done %d output buffers\\n\",\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0585-staging-bcm2835-camera-Add-support-for-H264-levels-4.patch",
    "content": "From 8c85b83a8dc6c62fa20b87f2fe51b80a3bafc169 Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Thu, 25 Mar 2021 18:34:50 +0000\nSubject: [PATCH] staging/bcm2835-camera: Add support for H264 levels\n 4.1 and 4.2\n\nWhilst the hardware can't achieve the limits of level 4.2 under\nall situations, it can exceed level 4.0.\n\nAllow selection of levels 4.1 and 4.2.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n .../vc04_services/bcm2835-camera/controls.c   | 19 +++++++++++++++++--\n 1 file changed, 17 insertions(+), 2 deletions(-)\n\n--- a/drivers/staging/vc04_services/bcm2835-camera/controls.c\n+++ b/drivers/staging/vc04_services/bcm2835-camera/controls.c\n@@ -709,6 +709,8 @@ static int ctrl_set_video_encode_profile\n \t\tcase V4L2_MPEG_VIDEO_H264_LEVEL_3_1:\n \t\tcase V4L2_MPEG_VIDEO_H264_LEVEL_3_2:\n \t\tcase V4L2_MPEG_VIDEO_H264_LEVEL_4_0:\n+\t\tcase V4L2_MPEG_VIDEO_H264_LEVEL_4_1:\n+\t\tcase V4L2_MPEG_VIDEO_H264_LEVEL_4_2:\n \t\t\tdev->capture.enc_level = ctrl->val;\n \t\t\tbreak;\n \t\tdefault:\n@@ -774,6 +776,17 @@ static int ctrl_set_video_encode_profile\n \t\tcase V4L2_MPEG_VIDEO_H264_LEVEL_4_0:\n \t\t\tparam.level = MMAL_VIDEO_LEVEL_H264_4;\n \t\t\tbreak;\n+\t\t/*\n+\t\t * Note that the hardware spec is level 4.0. Achieving levels\n+\t\t * above that depend on exactly the resolution and frame rate\n+\t\t * being requested.\n+\t\t */\n+\t\tcase V4L2_MPEG_VIDEO_H264_LEVEL_4_1:\n+\t\t\tparam.level = MMAL_VIDEO_LEVEL_H264_41;\n+\t\t\tbreak;\n+\t\tcase V4L2_MPEG_VIDEO_H264_LEVEL_4_2:\n+\t\t\tparam.level = MMAL_VIDEO_LEVEL_H264_42;\n+\t\t\tbreak;\n \t\tdefault:\n \t\t\t/* Should never get here */\n \t\t\tbreak;\n@@ -1224,8 +1237,10 @@ static const struct bm2835_mmal_v4l2_ctr\n \t\t\t BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_0) |\n \t\t\t BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_1) |\n \t\t\t BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_2) |\n-\t\t\t BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_0)),\n-\t\t.max = V4L2_MPEG_VIDEO_H264_LEVEL_4_0,\n+\t\t\t BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_0) |\n+\t\t\t BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_1) |\n+\t\t\t BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_2)),\n+\t\t.max = V4L2_MPEG_VIDEO_H264_LEVEL_4_2,\n \t\t.def = V4L2_MPEG_VIDEO_H264_LEVEL_4_0,\n \t\t.step = 1,\n \t\t.imenu = NULL,\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0586-staging-bcm2835-codec-Do-not-update-crop-from-S_FMT-.patch",
    "content": "From 0409260a821dd9b8d3d8e5f4fbdee1b6f892bd4d Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Thu, 15 Apr 2021 11:07:55 +0100\nSubject: [PATCH] staging/bcm2835-codec: Do not update crop from S_FMT\n after res change\n\nDuring decode, setting the CAPTURE queue format was setting the crop\nrectangle to the requested height before aligning up the format to\ncater for simple clients that weren't expecting to deal with cropping\nand the SELECTION API.\nThis caused problems on some resolution change events if the client\ndidn't also then use the selection API.\n\nDisable the crop update after a resolution change.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n .../vc04_services/bcm2835-codec/bcm2835-v4l2-codec.c       | 7 +++++++\n 1 file changed, 7 insertions(+)\n\n--- a/drivers/staging/vc04_services/bcm2835-codec/bcm2835-v4l2-codec.c\n+++ b/drivers/staging/vc04_services/bcm2835-codec/bcm2835-v4l2-codec.c\n@@ -999,6 +999,13 @@ static void handle_fmt_changed(struct bc\n \n \tq_data->crop_width = format->es.video.crop.width;\n \tq_data->crop_height = format->es.video.crop.height;\n+\t/*\n+\t * Stop S_FMT updating crop_height should it be unaligned.\n+\t * Client can still update the crop region via S_SELECTION should it\n+\t * really want to, but the decoder is likely to complain that the\n+\t * format then doesn't match.\n+\t */\n+\tq_data->selection_set = true;\n \tq_data->bytesperline = get_bytesperline(format->es.video.width,\n \t\t\t\t\t\tq_data->fmt);\n \n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0587-staging-bcm2835-isp-Fix-compiler-warning.patch",
    "content": "From 2b301480c8ea5a2ca0c79d5a51981335976afe88 Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.com>\nDate: Fri, 23 Apr 2021 16:16:49 +0100\nSubject: [PATCH] staging/bcm2835-isp: Fix compiler warning\n\nThe result of dividing a u32 by a size_t is an unsigned int on arm32\nand a long unsigned int on arm64. Use \"%zu\" (the size_t format) to\nremove the build warning for 64-bit builds.\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.com>\n---\n drivers/staging/vc04_services/bcm2835-isp/bcm2835-v4l2-isp.c | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/drivers/staging/vc04_services/bcm2835-isp/bcm2835-v4l2-isp.c\n+++ b/drivers/staging/vc04_services/bcm2835-isp/bcm2835-v4l2-isp.c\n@@ -1235,7 +1235,7 @@ static int bcm2835_isp_get_supported_fmt\n \tif (ret) {\n \t\tif (ret == MMAL_MSG_STATUS_ENOSPC) {\n \t\t\tv4l2_err(&dev->v4l2_dev,\n-\t\t\t\t \"%s: port has more encodings than we provided space for. Some are dropped (%u vs %u).\\n\",\n+\t\t\t\t \"%s: port has more encodings than we provided space for. Some are dropped (%zu vs %u).\\n\",\n \t\t\t\t __func__, param_size / sizeof(u32),\n \t\t\t\t MAX_SUPPORTED_ENCODINGS);\n \t\t\tnum_encodings = MAX_SUPPORTED_ENCODINGS;\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0588-overlays-Allow-multiple-gpio-shutdown-instances.patch",
    "content": "From 76eb23d534419db5e794699ae77f1e644f975e8c Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.com>\nDate: Sun, 25 Apr 2021 21:07:03 +0100\nSubject: [PATCH] overlays: Allow multiple gpio-shutdown instances\n\nThere is no reason not to support multiple gpio-shutdown signals,\nso add the necessary __override__ magic.\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.com>\n---\n arch/arm/boot/dts/overlays/gpio-shutdown-overlay.dts | 6 ++++--\n 1 file changed, 4 insertions(+), 2 deletions(-)\n\n--- a/arch/arm/boot/dts/overlays/gpio-shutdown-overlay.dts\n+++ b/arch/arm/boot/dts/overlays/gpio-shutdown-overlay.dts\n@@ -24,7 +24,7 @@\n \t\t\t// by a \"pinctrl client\", as is done below. See:\n \t\t\t//   https://www.kernel.org/doc/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt\n \t\t\t//   https://www.kernel.org/doc/Documentation/devicetree/bindings/pinctrl/brcm,bcm2835-gpio.txt\n-\t\t\tpin_state: shutdown_button_pins {\n+\t\t\tpin_state: shutdown_button_pins@3 {\n \t\t\t\tbrcm,pins = <3>; // gpio number\n \t\t\t\tbrcm,function = <0>; // 0 = input, 1 = output\n \t\t\t\tbrcm,pull = <2>; // 0 = none, 1 = pull down, 2 = pull up\n@@ -35,7 +35,7 @@\n \t\t// Add a new device to the /soc devicetree node\n \t\ttarget-path = \"/soc\";\n \t\t__overlay__ {\n-\t\t\tshutdown_button {\n+\t\t\tshutdown_button: shutdown_button@3 {\n \t\t\t\t// Let the gpio-keys driver handle this device. See:\n \t\t\t\t// https://www.kernel.org/doc/Documentation/devicetree/bindings/input/gpio-keys.txt\n \t\t\t\tcompatible = \"gpio-keys\";\n@@ -69,6 +69,8 @@\n \t__overrides__ {\n \t\t// Allow overriding the GPIO number.\n \t\tgpio_pin = <&button>,\"gpios:4\",\n+\t\t\t   <&shutdown_button>,\"reg:0\",\n+\t\t\t   <&pin_state>,\"reg:0\",\n \t\t           <&pin_state>,\"brcm,pins:0\";\n \n \t\t// Allow changing the internal pullup/down state. 0 = none, 1 = pulldown, 2 = pullup\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0589-overlays-README-improve-the-gpio-poweroff-guide.patch",
    "content": "From 81fe79da00f4130ef329d22d6b9433f1ff7f2b6f Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.com>\nDate: Mon, 26 Apr 2021 09:58:14 +0100\nSubject: [PATCH] overlays: README - improve the gpio-poweroff guide\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.com>\n---\n arch/arm/boot/dts/overlays/README | 11 +++++++++--\n 1 file changed, 9 insertions(+), 2 deletions(-)\n\n--- a/arch/arm/boot/dts/overlays/README\n+++ b/arch/arm/boot/dts/overlays/README\n@@ -987,8 +987,15 @@ Params: <None>\n \n \n Name:   gpio-poweroff\n-Info:   Drives a GPIO high or low on poweroff (including halt). Enabling this\n-        overlay will prevent the ability to boot by driving GPIO3 low.\n+Info:   Drives a GPIO high or low on poweroff (including halt). Using this\n+        overlay interferes with the normal power-down sequence, preventing the\n+        kernel from resetting the SoC (a necessary step in a normal power-off\n+        or reboot). This also disables the ability to triger a boot by driving\n+        GPIO3 low.\n+\n+        Users of this overlay are required to provide an external mechanism to\n+        switch off the power supply when signalled - failure to do so results\n+        in a kernel BUG, increased power consumption and undefined behaviour.\n Load:   dtoverlay=gpio-poweroff,<param>=<val>\n Params: gpiopin                 GPIO for signalling (default 26)\n \n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0590-SQUASH-overlays-Fix-typo-in-README.patch",
    "content": "From 2b24b2486cd95e2b644efe190ab1577d15ab3dd3 Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.com>\nDate: Mon, 26 Apr 2021 10:08:21 +0100\nSubject: [PATCH] SQUASH: overlays: Fix typo in README\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.com>\n---\n arch/arm/boot/dts/overlays/README | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/arch/arm/boot/dts/overlays/README\n+++ b/arch/arm/boot/dts/overlays/README\n@@ -990,7 +990,7 @@ Name:   gpio-poweroff\n Info:   Drives a GPIO high or low on poweroff (including halt). Using this\n         overlay interferes with the normal power-down sequence, preventing the\n         kernel from resetting the SoC (a necessary step in a normal power-off\n-        or reboot). This also disables the ability to triger a boot by driving\n+        or reboot). This also disables the ability to trigger a boot by driving\n         GPIO3 low.\n \n         Users of this overlay are required to provide an external mechanism to\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0591-gpio-poweroff-Remember-the-old-poweroff-handler.patch",
    "content": "From 6fe800dee9b24ef1d75a0acd5b067a1e84f2a5da Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.com>\nDate: Tue, 27 Apr 2021 08:59:01 +0100\nSubject: [PATCH] gpio-poweroff: Remember the old poweroff handler\n\nKeeping a copy of the old poweroff handler allows it to be restored\nshould this module be unloaded, but also provides a fallback if the\npower hasn't been removed when the timeout elapses.\n\nSee: https://github.com/raspberrypi/rpi-eeprom/issues/330\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.com>\n---\n drivers/power/reset/gpio-poweroff.c | 7 ++++++-\n 1 file changed, 6 insertions(+), 1 deletion(-)\n\n--- a/drivers/power/reset/gpio-poweroff.c\n+++ b/drivers/power/reset/gpio-poweroff.c\n@@ -24,6 +24,7 @@ static struct gpio_desc *reset_gpio;\n static u32 timeout = DEFAULT_TIMEOUT_MS;\n static u32 active_delay = 100;\n static u32 inactive_delay = 100;\n+static void (*old_power_off)(void);\n \n static void gpio_poweroff_do_poweroff(void)\n {\n@@ -43,6 +44,9 @@ static void gpio_poweroff_do_poweroff(vo\n \t/* give it some time */\n \tmdelay(timeout);\n \n+\tif (old_power_off)\n+\t\told_power_off();\n+\n \tWARN_ON(1);\n }\n \n@@ -83,6 +87,7 @@ static int gpio_poweroff_probe(struct pl\n \t\tgpiod_export_link(&pdev->dev, \"poweroff-gpio\", reset_gpio);\n \t}\n \n+\told_power_off = pm_power_off;\n \tpm_power_off = &gpio_poweroff_do_poweroff;\n \treturn 0;\n }\n@@ -90,7 +95,7 @@ static int gpio_poweroff_probe(struct pl\n static int gpio_poweroff_remove(struct platform_device *pdev)\n {\n \tif (pm_power_off == &gpio_poweroff_do_poweroff)\n-\t\tpm_power_off = NULL;\n+\t\tpm_power_off = old_power_off;\n \n \tgpiod_unexport(reset_gpio);\n \n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0593-overlays-Add-ugreen-dabboard-overlay.patch",
    "content": "From d7a810374597774f0e01eedfc30074772f4e9f85 Mon Sep 17 00:00:00 2001\nFrom: Christoph <c.orth@ugreen.eu>\nDate: Wed, 28 Apr 2021 20:30:44 +0200\nSubject: [PATCH] overlays: Add ugreen-dabboard overlay\n\nThis is a simple overlay based on the simple-audio-card and the dmic\ncodec. It has the speciality that it is configured to use the codec\nas a master I2S device. It works for example with the Si468x DAB\nreceiver on the uGreen DABBoard.\n\nSee: https://github.com/raspberrypi/linux/issues/4304\n\nSigned-off-by: Christoph Orth <c.orth@ugreen.eu>\n---\n arch/arm/boot/dts/overlays/Makefile           |  1 +\n arch/arm/boot/dts/overlays/README             | 10 ++++\n .../dts/overlays/ugreen-dabboard-overlay.dts  | 49 +++++++++++++++++++\n 3 files changed, 60 insertions(+)\n create mode 100644 arch/arm/boot/dts/overlays/ugreen-dabboard-overlay.dts\n\n--- a/arch/arm/boot/dts/overlays/Makefile\n+++ b/arch/arm/boot/dts/overlays/Makefile\n@@ -209,6 +209,7 @@ dtbo-$(CONFIG_ARCH_BCM2835) += \\\n \tuart4.dtbo \\\n \tuart5.dtbo \\\n \tudrc.dtbo \\\n+\tugreen-dabboard.dtbo \\\n \tupstream.dtbo \\\n \tupstream-pi4.dtbo \\\n \tvc4-fkms-v3d.dtbo \\\n--- a/arch/arm/boot/dts/overlays/README\n+++ b/arch/arm/boot/dts/overlays/README\n@@ -3130,6 +3130,16 @@ Load:   dtoverlay=udrc,<param>=<val>\n Params: alsaname                Name of the ALSA audio device (default \"udrc\")\n \n \n+Name:   ugreen-dabboard\n+Info:   Configures the ugreen-dabboard I2S overlay\n+        This is a simple overlay based on the simple-audio-card and the dmic\n+        codec. It has the speciality that it is configured to use the codec\n+        as a master I2S device. It works for example with the Si468x DAB\n+        receiver on the uGreen DABBoard.\n+Load:   dtoverlay=ugreen-dabboard,<param>=<val>\n+Params: card-name               Override the default, \"dabboard\", card name.\n+\n+\n Name:   upstream\n Info:   Allow usage of downstream .dtb with upstream kernel. Comprises the\n         vc4-kms-v3d and dwc2 overlays.\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/ugreen-dabboard-overlay.dts\n@@ -0,0 +1,49 @@\n+// Definitions for the ugreen dabboard I2S\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&i2s>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget-path = \"/\";\n+\t\t__overlay__ {\n+\t\t\tdmic_codec: dmic-codec {\n+\t\t\t\t#sound-dai-cells = <0>;\n+\t\t\t\tcompatible = \"dmic-codec\";\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&sound>;\n+\t\tsound_overlay: __overlay__ {\n+\t\t\tcompatible = \"simple-audio-card\";\n+\t\t\tsimple-audio-card,format = \"i2s\";\n+\t\t\tsimple-audio-card,name = \"dabboard\";\n+\t\t\tsimple-audio-card,bitclock-master = <&dailink0_slave>;\n+\t\t\tsimple-audio-card,frame-master = <&dailink0_slave>;\n+\t\t\tsimple-audio-card,widgets = \"Microphone\", \"Microphone Jack\";\n+\t\t\tstatus = \"okay\";\n+\t\t\tsimple-audio-card,cpu {\n+\t\t\t\tsound-dai = <&i2s>;\n+\t\t\t};\n+\t\t\tdailink0_slave: simple-audio-card,codec {\n+\t\t\t\t#sound-dai-cells = <0>;\n+\t\t\t\tsound-dai = <&dmic_codec>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\tcard-name = <&sound_overlay>,\"simple-audio-card,name\";\n+\t};\n+};\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0594-ARM-dts-bcm2711-rpi-400-Limit-MDIO-clock-speed.patch",
    "content": "From a0b9fe9f3cd79bee2f7f1755310435792942435f Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.com>\nDate: Fri, 23 Apr 2021 15:02:58 +0100\nSubject: [PATCH] ARM: dts: bcm2711-rpi-400: Limit MDIO clock speed\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.com>\n---\n arch/arm/boot/dts/bcm2711-rpi-400.dts | 4 ++++\n 1 file changed, 4 insertions(+)\n\n--- a/arch/arm/boot/dts/bcm2711-rpi-400.dts\n+++ b/arch/arm/boot/dts/bcm2711-rpi-400.dts\n@@ -616,6 +616,10 @@\n \tbrcm,disable-headphones = <1>;\n };\n \n+&genet_mdio {\n+\tclock-frequency = <1950000>;\n+};\n+\n / {\n \t__overrides__ {\n \t\tact_led_gpio = <&act_led>,\"gpios:4\";\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0595-spi-bcm2835-Increase-the-CS-limit-to-24.patch",
    "content": "From c3fbb1e6771dabb14571552c036a049ffa470eb1 Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.com>\nDate: Fri, 30 Apr 2021 08:34:36 +0100\nSubject: [PATCH] spi: bcm2835: Increase the CS limit to 24\n\nIncrease the maximum number of CS lines to 24, and ensure this limit is\nnot exceeded.\n\nSee: https://github.com/raspberrypi/linux/pull/4281\n\nSuggested-by: Joe Burmeister <joe.burmeister@devtank.co.uk>\nSigned-off-by: Phil Elwell <phil@raspberrypi.com>\n---\n drivers/spi/spi-bcm2835.c | 6 ++++++\n 1 file changed, 6 insertions(+)\n\n--- a/drivers/spi/spi-bcm2835.c\n+++ b/drivers/spi/spi-bcm2835.c\n@@ -28,6 +28,7 @@\n #include <linux/gpio/consumer.h>\n #include <linux/gpio/machine.h> /* FIXME: using chip internals */\n #include <linux/gpio/driver.h> /* FIXME: using chip internals */\n+#include <linux/of_gpio.h>\n #include <linux/of_irq.h>\n #include <linux/spi/spi.h>\n \n@@ -1299,6 +1300,11 @@ static int bcm2835_spi_probe(struct plat\n \tstruct bcm2835_spi *bs;\n \tint err;\n \n+\tif (of_gpio_named_count(pdev->dev.of_node, \"cs-gpios\") >\n+\t    BCM2835_SPI_NUM_CS)\n+\t\treturn dev_err_probe(&pdev->dev, -EINVAL,\n+\t\t\t\t     \"too many chip selects\\n\");\n+\n \tctlr = devm_spi_alloc_master(&pdev->dev, ALIGN(sizeof(*bs),\n \t\t\t\t\t\t  dma_get_cache_alignment()));\n \tif (!ctlr)\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0596-clk-Always-clamp-the-rounded-rate.patch",
    "content": "From 8f26362634435209e4f849ce2efcb2b4f48c8f5b Mon Sep 17 00:00:00 2001\nFrom: Maxime Ripard <maxime@cerno.tech>\nDate: Wed, 5 May 2021 15:35:34 +0200\nSubject: [PATCH] clk: Always clamp the rounded rate\n\nThe current core while setting the min and max rate properly in the\nclk_request structure will not make sure that the requested rate is\nwithin these boundaries, leaving it to each and every driver to make\nsure it is.\n\nAdd a clamp call to make sure it's always done.\n\nSigned-off-by: Maxime Ripard <maxime@cerno.tech>\n---\n drivers/clk/clk.c | 2 ++\n 1 file changed, 2 insertions(+)\n\n--- a/drivers/clk/clk.c\n+++ b/drivers/clk/clk.c\n@@ -1334,6 +1334,8 @@ static int clk_core_determine_round_nolo\n \tif (!core)\n \t\treturn 0;\n \n+\treq->rate = clamp(req->rate, req->min_rate, req->max_rate);\n+\n \t/*\n \t * At this point, core protection will be disabled if\n \t * - if the provider is not protected at all\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0597-drm-vc4-crtc-Pass-the-drm_atomic_state-to-config_pv.patch",
    "content": "From 2163477b39ed25362d5679d0cf9b843fe2c4bfbb Mon Sep 17 00:00:00 2001\nFrom: Maxime Ripard <maxime@cerno.tech>\nDate: Thu, 6 May 2021 17:01:46 +0200\nSubject: [PATCH] drm/vc4: crtc: Pass the drm_atomic_state to config_pv\n\nThe vc4_crtc_config_pv will need to access the drm_atomic_state\nstructure and its only parent function, vc4_crtc_atomic_enable already\nhas access to it. Let's pass it as a parameter.\n\nFixes: 792c3132bc1b (\"drm/vc4: encoder: Add finer-grained encoder callbacks\")\nSigned-off-by: Maxime Ripard <maxime@cerno.tech>\n---\n drivers/gpu/drm/vc4/vc4_crtc.c | 8 ++++----\n 1 file changed, 4 insertions(+), 4 deletions(-)\n\n--- a/drivers/gpu/drm/vc4/vc4_crtc.c\n+++ b/drivers/gpu/drm/vc4/vc4_crtc.c\n@@ -305,7 +305,7 @@ static void vc4_crtc_pixelvalve_reset(st\n \tCRTC_WRITE(PV_CONTROL, CRTC_READ(PV_CONTROL) | PV_CONTROL_FIFO_CLR);\n }\n \n-static void vc4_crtc_config_pv(struct drm_crtc *crtc)\n+static void vc4_crtc_config_pv(struct drm_crtc *crtc, struct drm_atomic_state *state)\n {\n \tstruct drm_device *dev = crtc->dev;\n \tstruct vc4_dev *vc4 = to_vc4_dev(dev);\n@@ -313,8 +313,8 @@ static void vc4_crtc_config_pv(struct dr\n \tstruct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder);\n \tstruct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);\n \tconst struct vc4_pv_data *pv_data = vc4_crtc_to_vc4_pv_data(vc4_crtc);\n-\tstruct drm_crtc_state *state = crtc->state;\n-\tstruct drm_display_mode *mode = &state->adjusted_mode;\n+\tstruct drm_crtc_state *crtc_state = crtc->state;\n+\tstruct drm_display_mode *mode = &crtc_state->adjusted_mode;\n \tbool interlace = mode->flags & DRM_MODE_FLAG_INTERLACE;\n \tu32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;\n \tbool is_dsi = (vc4_encoder->type == VC4_ENCODER_TYPE_DSI0 ||\n@@ -540,7 +540,7 @@ static void vc4_crtc_atomic_enable(struc\n \tif (vc4_encoder->pre_crtc_configure)\n \t\tvc4_encoder->pre_crtc_configure(encoder, state);\n \n-\tvc4_crtc_config_pv(crtc);\n+\tvc4_crtc_config_pv(crtc, state);\n \n \tCRTC_WRITE(PV_CONTROL, CRTC_READ(PV_CONTROL) | PV_CONTROL_EN);\n \n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0598-drm-vc4-crtc-Fix-vc4_get_crtc_encoder-logic.patch",
    "content": "From bc75a1ca95c195508c7d9238a9dc31218ead3ad1 Mon Sep 17 00:00:00 2001\nFrom: Maxime Ripard <maxime@cerno.tech>\nDate: Thu, 6 May 2021 17:07:07 +0200\nSubject: [PATCH] drm/vc4: crtc: Fix vc4_get_crtc_encoder logic\n\nThe vc4_get_crtc_encoder function currently only works when the\nconnector->state->crtc pointer is set, which is only true when the\nconnector is currently enabled.\n\nHowever, we use it as part of the disable path as well, and our lookup\nwill fail in that case, resulting in it returning a null pointer we\ncan't act on.\n\nWe can access the connector that used to be connected to that crtc\nthough using the old connector state in the disable path.\n\nSince we want to support both the enable and disable path, we can\nsupport it by passing the state accessor variant as a function pointer,\ntogether with the atomic state.\n\nFixes: 792c3132bc1b (\"drm/vc4: encoder: Add finer-grained encoder callbacks\")\nSigned-off-by: Maxime Ripard <maxime@cerno.tech>\n---\n drivers/gpu/drm/vc4/vc4_crtc.c | 21 ++++++++++++++++-----\n 1 file changed, 16 insertions(+), 5 deletions(-)\n\n--- a/drivers/gpu/drm/vc4/vc4_crtc.c\n+++ b/drivers/gpu/drm/vc4/vc4_crtc.c\n@@ -279,14 +279,22 @@ static u32 vc4_crtc_get_fifo_full_level_\n  * allows drivers to push pixels to more than one encoder from the\n  * same CRTC.\n  */\n-static struct drm_encoder *vc4_get_crtc_encoder(struct drm_crtc *crtc)\n+static struct drm_encoder *vc4_get_crtc_encoder(struct drm_crtc *crtc,\n+\t\t\t\t\t\tstruct drm_atomic_state *state,\n+\t\t\t\t\t\tstruct drm_connector_state *(*get_state)(struct drm_atomic_state *state,\n+\t\t\t\t\t\t\t\t\t\t\t struct drm_connector *connector))\n {\n \tstruct drm_connector *connector;\n \tstruct drm_connector_list_iter conn_iter;\n \n \tdrm_connector_list_iter_begin(crtc->dev, &conn_iter);\n \tdrm_for_each_connector_iter(connector, &conn_iter) {\n-\t\tif (connector->state->crtc == crtc) {\n+\t\tstruct drm_connector_state *conn_state = get_state(state, connector);\n+\n+\t\tif (!conn_state)\n+\t\t\tcontinue;\n+\n+\t\tif (conn_state->crtc == crtc) {\n \t\t\tdrm_connector_list_iter_end(&conn_iter);\n \t\t\treturn connector->encoder;\n \t\t}\n@@ -309,7 +317,8 @@ static void vc4_crtc_config_pv(struct dr\n {\n \tstruct drm_device *dev = crtc->dev;\n \tstruct vc4_dev *vc4 = to_vc4_dev(dev);\n-\tstruct drm_encoder *encoder = vc4_get_crtc_encoder(crtc);\n+\tstruct drm_encoder *encoder = vc4_get_crtc_encoder(crtc, state,\n+\t\t\t\t\t\t\t   drm_atomic_get_new_connector_state);\n \tstruct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder);\n \tstruct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);\n \tconst struct vc4_pv_data *pv_data = vc4_crtc_to_vc4_pv_data(vc4_crtc);\n@@ -425,7 +434,8 @@ static int vc4_crtc_disable(struct drm_c\n \t\t\t    struct drm_atomic_state *state,\n \t\t\t    unsigned int channel)\n {\n-\tstruct drm_encoder *encoder = vc4_get_crtc_encoder(crtc);\n+\tstruct drm_encoder *encoder = vc4_get_crtc_encoder(crtc, state,\n+\t\t\t\t\t\t\t   drm_atomic_get_old_connector_state);\n \tstruct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder);\n \tstruct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);\n \tstruct drm_device *dev = crtc->dev;\n@@ -525,7 +535,8 @@ static void vc4_crtc_atomic_enable(struc\n {\n \tstruct drm_device *dev = crtc->dev;\n \tstruct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);\n-\tstruct drm_encoder *encoder = vc4_get_crtc_encoder(crtc);\n+\tstruct drm_encoder *encoder = vc4_get_crtc_encoder(crtc, state,\n+\t\t\t\t\t\t\t   drm_atomic_get_new_connector_state);\n \tstruct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder);\n \n \trequire_hvs_enabled(dev);\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0599-drm-vc4-crtc-Lookup-the-encoder-from-the-register-at.patch",
    "content": "From bb968f8f963e28d00fff213c62a2449c45ff19f4 Mon Sep 17 00:00:00 2001\nFrom: Maxime Ripard <maxime@cerno.tech>\nDate: Thu, 6 May 2021 17:15:57 +0200\nSubject: [PATCH] drm/vc4: crtc: Lookup the encoder from the register\n at boot\n\nAt boot, we can't rely on the vc4_get_crtc_encoder since we don't have a\nstate yet and thus will not be able to figure out which connector is\nattached to our CRTC.\n\nHowever, we have a muxing bit in the CRTC register we can use to get the\nencoder currently connected to the pixelvalve. We can thus read that\nregister, lookup the associated register through the vc4_pv_data\nstructure, and then pass it to vc4_crtc_disable so that we can perform\nthe proper operations.\n\nFixes: 875a4d536842 (\"drm/vc4: drv: Disable the CRTC at boot time\")\nSigned-off-by: Maxime Ripard <maxime@cerno.tech>\n---\n drivers/gpu/drm/vc4/vc4_crtc.c | 38 ++++++++++++++++++++++++++++++----\n 1 file changed, 34 insertions(+), 4 deletions(-)\n\n--- a/drivers/gpu/drm/vc4/vc4_crtc.c\n+++ b/drivers/gpu/drm/vc4/vc4_crtc.c\n@@ -431,11 +431,10 @@ static void require_hvs_enabled(struct d\n }\n \n static int vc4_crtc_disable(struct drm_crtc *crtc,\n+\t\t\t    struct drm_encoder *encoder,\n \t\t\t    struct drm_atomic_state *state,\n \t\t\t    unsigned int channel)\n {\n-\tstruct drm_encoder *encoder = vc4_get_crtc_encoder(crtc, state,\n-\t\t\t\t\t\t\t   drm_atomic_get_old_connector_state);\n \tstruct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder);\n \tstruct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);\n \tstruct drm_device *dev = crtc->dev;\n@@ -476,10 +475,29 @@ static int vc4_crtc_disable(struct drm_c\n \treturn 0;\n }\n \n+static struct drm_encoder *vc4_crtc_get_encoder_by_type(struct drm_crtc *crtc,\n+\t\t\t\t\t\t\tenum vc4_encoder_type type)\n+{\n+\tstruct drm_encoder *encoder;\n+\n+\tdrm_for_each_encoder(encoder, crtc->dev) {\n+\t\tstruct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder);\n+\n+\t\tif (vc4_encoder->type == type)\n+\t\t\treturn encoder;\n+\t}\n+\n+\treturn NULL;\n+}\n+\n int vc4_crtc_disable_at_boot(struct drm_crtc *crtc)\n {\n \tstruct drm_device *drm = crtc->dev;\n \tstruct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);\n+\tenum vc4_encoder_type encoder_type;\n+\tconst struct vc4_pv_data *pv_data;\n+\tstruct drm_encoder *encoder;\n+\tunsigned encoder_sel;\n \tint channel;\n \n \tif (!(of_device_is_compatible(vc4_crtc->pdev->dev.of_node,\n@@ -498,7 +516,17 @@ int vc4_crtc_disable_at_boot(struct drm_\n \tif (channel < 0)\n \t\treturn 0;\n \n-\treturn vc4_crtc_disable(crtc, NULL, channel);\n+\tencoder_sel = VC4_GET_FIELD(CRTC_READ(PV_CONTROL), PV_CONTROL_CLK_SELECT);\n+\tif (WARN_ON(encoder_sel != 0))\n+\t\treturn 0;\n+\n+\tpv_data = vc4_crtc_to_vc4_pv_data(vc4_crtc);\n+\tencoder_type = pv_data->encoder_types[encoder_sel];\n+\tencoder = vc4_crtc_get_encoder_by_type(crtc, encoder_type);\n+\tif (WARN_ON(!encoder))\n+\t\treturn 0;\n+\n+\treturn vc4_crtc_disable(crtc, encoder, NULL, channel);\n }\n \n static void vc4_crtc_atomic_disable(struct drm_crtc *crtc,\n@@ -507,6 +535,8 @@ static void vc4_crtc_atomic_disable(stru\n \tstruct drm_crtc_state *old_state = drm_atomic_get_old_crtc_state(state,\n \t\t\t\t\t\t\t\t\t crtc);\n \tstruct vc4_crtc_state *old_vc4_state = to_vc4_crtc_state(old_state);\n+\tstruct drm_encoder *encoder = vc4_get_crtc_encoder(crtc, state,\n+\t\t\t\t\t\t\t   drm_atomic_get_old_connector_state);\n \tstruct drm_device *dev = crtc->dev;\n \n \trequire_hvs_enabled(dev);\n@@ -514,7 +544,7 @@ static void vc4_crtc_atomic_disable(stru\n \t/* Disable vblank irq handling before crtc is disabled. */\n \tdrm_crtc_vblank_off(crtc);\n \n-\tvc4_crtc_disable(crtc, state, old_vc4_state->assigned_channel);\n+\tvc4_crtc_disable(crtc, encoder, state, old_vc4_state->assigned_channel);\n \n \t/*\n \t * Make sure we issue a vblank event after disabling the CRTC if\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0600-drm-vc4-hdmi-Simplify-the-connector-state-retrieval.patch",
    "content": "From a9c640d91233d2e1b38e32644a5f53bc2de1fce0 Mon Sep 17 00:00:00 2001\nFrom: Maxime Ripard <maxime@cerno.tech>\nDate: Thu, 29 Apr 2021 21:58:27 +0200\nSubject: [PATCH] drm/vc4: hdmi: Simplify the connector state retrieval\n\nWhen we have the entire DRM state, retrieving the connector state only\nrequires the drm_connector pointer. Fortunately for us, we have\nallocated it as a part of the vc4_hdmi structure, so we can retrieve get\na pointer by simply accessing our field in that structure.\n\nSigned-off-by: Maxime Ripard <maxime@cerno.tech>\n---\n drivers/gpu/drm/vc4/vc4_hdmi.c | 21 +++------------------\n 1 file changed, 3 insertions(+), 18 deletions(-)\n\n--- a/drivers/gpu/drm/vc4/vc4_hdmi.c\n+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c\n@@ -852,31 +852,16 @@ static void vc4_hdmi_recenter_fifo(struc\n \t\t  \"VC4_HDMI_FIFO_CTL_RECENTER_DONE\");\n }\n \n-static struct drm_connector_state *\n-vc4_hdmi_encoder_get_connector_state(struct drm_encoder *encoder,\n-\t\t\t\t     struct drm_atomic_state *state)\n-{\n-\tstruct drm_connector_state *conn_state;\n-\tstruct drm_connector *connector;\n-\tunsigned int i;\n-\n-\tfor_each_new_connector_in_state(state, connector, conn_state, i) {\n-\t\tif (conn_state->best_encoder == encoder)\n-\t\t\treturn conn_state;\n-\t}\n-\n-\treturn NULL;\n-}\n-\n static void vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder *encoder,\n \t\t\t\t\t\tstruct drm_atomic_state *state)\n {\n+\tstruct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);\n+\tstruct drm_connector *connector = &vc4_hdmi->connector;\n \tstruct drm_connector_state *conn_state =\n-\t\tvc4_hdmi_encoder_get_connector_state(encoder, state);\n+\t\tdrm_atomic_get_new_connector_state(state, connector);\n \tstruct vc4_hdmi_connector_state *vc4_conn_state =\n \t\tconn_state_to_vc4_hdmi_conn_state(conn_state);\n \tstruct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;\n-\tstruct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);\n \tunsigned long bvb_rate, pixel_rate, hsm_rate;\n \tint ret;\n \n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0601-drm-vc4-hdmi-Rely-on-interrupts-to-handle-hotplug.patch",
    "content": "From 263d69b2c6ff1d1de6c3788d1b01760d4a1ebd9d Mon Sep 17 00:00:00 2001\nFrom: Maxime Ripard <maxime@cerno.tech>\nDate: Thu, 29 Apr 2021 11:08:52 +0200\nSubject: [PATCH] drm/vc4: hdmi: Rely on interrupts to handle hotplug\n\nDRM currently polls for the HDMI connector status every 10s, which can\nbe an issue when we connect/disconnect a display quickly or the device\non the other end only issues a hotplug pulse (for example on EDID\nchange).\n\nSwitch the driver to rely on the internal controller logic for the\nBCM2711/RPi4.\n\nSigned-off-by: Maxime Ripard <maxime@cerno.tech>\n---\n drivers/gpu/drm/vc4/vc4_hdmi.c | 44 ++++++++++++++++++++++++++++++++++\n 1 file changed, 44 insertions(+)\n\n--- a/drivers/gpu/drm/vc4/vc4_hdmi.c\n+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c\n@@ -1690,6 +1690,46 @@ static int vc4_hdmi_audio_init(struct vc\n \n }\n \n+static irqreturn_t vc4_hdmi_hpd_irq_thread(int irq, void *priv)\n+{\n+\tstruct vc4_hdmi *vc4_hdmi = priv;\n+\tstruct drm_device *dev = vc4_hdmi->connector.dev;\n+\n+\tif (dev)\n+\t\tdrm_kms_helper_hotplug_event(dev);\n+\n+\treturn IRQ_HANDLED;\n+}\n+\n+static int vc4_hdmi_hotplug_init(struct vc4_hdmi *vc4_hdmi)\n+{\n+\tstruct platform_device *pdev = vc4_hdmi->pdev;\n+\tstruct device *dev = &pdev->dev;\n+\tint ret;\n+\n+\tif (vc4_hdmi->variant->external_irq_controller) {\n+\t\tret = devm_request_threaded_irq(dev,\n+\t\t\t\t\t\tplatform_get_irq_byname(pdev, \"hpd-connected\"),\n+\t\t\t\t\t\tNULL,\n+\t\t\t\t\t\tvc4_hdmi_hpd_irq_thread, IRQF_ONESHOT,\n+\t\t\t\t\t\t\"vc4 hdmi hpd connected\", vc4_hdmi);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\n+\t\tret = devm_request_threaded_irq(dev,\n+\t\t\t\t\t\tplatform_get_irq_byname(pdev, \"hpd-removed\"),\n+\t\t\t\t\t\tNULL,\n+\t\t\t\t\t\tvc4_hdmi_hpd_irq_thread, IRQF_ONESHOT,\n+\t\t\t\t\t\t\"vc4 hdmi hpd disconnected\", vc4_hdmi);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\n+\t\tconnector->polled = DRM_CONNECTOR_POLL_HPD;\n+\t}\n+\n+\treturn 0;\n+}\n+\n #ifdef CONFIG_DRM_VC4_HDMI_CEC\n static irqreturn_t vc4_cec_irq_handler_rx_thread(int irq, void *priv)\n {\n@@ -2317,6 +2357,10 @@ static int vc4_hdmi_bind(struct device *\n \tif (ret)\n \t\tgoto err_destroy_encoder;\n \n+\tret = vc4_hdmi_hotplug_init(vc4_hdmi);\n+\tif (ret)\n+\t\tgoto err_destroy_conn;\n+\n \tret = vc4_hdmi_cec_init(vc4_hdmi);\n \tif (ret)\n \t\tgoto err_destroy_conn;\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0602-drm-vc4-hdmi-Add-a-workqueue-to-set-scrambling.patch",
    "content": "From c20cb28d802aa148cfa90c0682323e9d52dc0466 Mon Sep 17 00:00:00 2001\nFrom: Maxime Ripard <maxime@cerno.tech>\nDate: Fri, 7 May 2021 15:28:21 +0200\nSubject: [PATCH] drm/vc4: hdmi: Add a workqueue to set scrambling\n\nIt looks like some displays (like the LG 27UL850-W) don't enable the\nscrambling when the HDMI driver enables it. However, if we set later the\nscrambler enable bit, the display will work as expected.\n\nLet's create delayed work queue to periodically look at the display\nscrambling status, and if it's not set yet try to enable it again.\n\nSigned-off-by: Maxime Ripard <maxime@cerno.tech>\n---\n drivers/gpu/drm/vc4/vc4_hdmi.c | 25 +++++++++++++++++++++++++\n drivers/gpu/drm/vc4/vc4_hdmi.h |  2 ++\n 2 files changed, 27 insertions(+)\n\n--- a/drivers/gpu/drm/vc4/vc4_hdmi.c\n+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c\n@@ -538,6 +538,8 @@ static bool vc4_hdmi_supports_scrambling\n \treturn true;\n }\n \n+#define SCRAMBLING_POLLING_DELAY_MS\t1000\n+\n static void vc4_hdmi_enable_scrambling(struct drm_encoder *encoder)\n {\n \tstruct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;\n@@ -554,6 +556,9 @@ static void vc4_hdmi_enable_scrambling(s\n \n \tHDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) |\n \t\t   VC5_HDMI_SCRAMBLER_CTL_ENABLE);\n+\n+\tqueue_delayed_work(system_wq, &vc4_hdmi->scrambling_work,\n+\t\t\t   msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS));\n }\n \n static void vc4_hdmi_disable_scrambling(struct drm_encoder *encoder)\n@@ -572,6 +577,9 @@ static void vc4_hdmi_disable_scrambling(\n \tif (crtc && !vc4_hdmi_mode_needs_scrambling(&crtc->mode))\n \t\treturn;\n \n+\tif (delayed_work_pending(&vc4_hdmi->scrambling_work))\n+\t\tcancel_delayed_work_sync(&vc4_hdmi->scrambling_work);\n+\n \tHDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) &\n \t\t   ~VC5_HDMI_SCRAMBLER_CTL_ENABLE);\n \n@@ -579,6 +587,22 @@ static void vc4_hdmi_disable_scrambling(\n \tdrm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, false);\n }\n \n+static void vc4_hdmi_scrambling_wq(struct work_struct *work)\n+{\n+\tstruct vc4_hdmi *vc4_hdmi = container_of(to_delayed_work(work),\n+\t\t\t\t\t\t struct vc4_hdmi,\n+\t\t\t\t\t\t scrambling_work);\n+\n+\tif (drm_scdc_get_scrambling_status(vc4_hdmi->ddc))\n+\t\treturn;\n+\n+\tdrm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, true);\n+\tdrm_scdc_set_scrambling(vc4_hdmi->ddc, true);\n+\n+\tqueue_delayed_work(system_wq, &vc4_hdmi->scrambling_work,\n+\t\t\t   msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS));\n+}\n+\n static void vc4_hdmi_encoder_post_crtc_disable(struct drm_encoder *encoder,\n \t\t\t\t\t       struct drm_atomic_state *state)\n {\n@@ -2275,6 +2299,7 @@ static int vc4_hdmi_bind(struct device *\n \tvc4_hdmi = devm_kzalloc(dev, sizeof(*vc4_hdmi), GFP_KERNEL);\n \tif (!vc4_hdmi)\n \t\treturn -ENOMEM;\n+\tINIT_DELAYED_WORK(&vc4_hdmi->scrambling_work, vc4_hdmi_scrambling_wq);\n \n \tdev_set_drvdata(dev, vc4_hdmi);\n \tencoder = &vc4_hdmi->encoder.base.base;\n--- a/drivers/gpu/drm/vc4/vc4_hdmi.h\n+++ b/drivers/gpu/drm/vc4/vc4_hdmi.h\n@@ -131,6 +131,8 @@ struct vc4_hdmi {\n \tstruct vc4_hdmi_encoder encoder;\n \tstruct drm_connector connector;\n \n+\tstruct delayed_work scrambling_work;\n+\n \tstruct i2c_adapter *ddc;\n \tvoid __iomem *hdmicore_regs;\n \tvoid __iomem *hd_regs;\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0603-vc4-drm-hdmi-Fix-missing-declaration.patch",
    "content": "From 68b5e1eb66bf0bdbc4ecb1987f5b0e42b017a844 Mon Sep 17 00:00:00 2001\nFrom: Dom Cobley <popcornmix@gmail.com>\nDate: Fri, 7 May 2021 17:22:53 +0100\nSubject: [PATCH] vc4/drm: hdmi: Fix missing declaration\n\nFixes: 671a8068ee5feae1d92e6d48027fa8de062e2af2\nSigned-off-by: Dom Cobley <popcornmix@gmail.com>\n---\n drivers/gpu/drm/vc4/vc4_hdmi.c | 1 +\n 1 file changed, 1 insertion(+)\n\n--- a/drivers/gpu/drm/vc4/vc4_hdmi.c\n+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c\n@@ -1729,6 +1729,7 @@ static int vc4_hdmi_hotplug_init(struct\n {\n \tstruct platform_device *pdev = vc4_hdmi->pdev;\n \tstruct device *dev = &pdev->dev;\n+\tstruct drm_connector *connector = &vc4_hdmi->connector;\n \tint ret;\n \n \tif (vc4_hdmi->variant->external_irq_controller) {\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0604-overlays-merus-amp-remove-spi-override.patch",
    "content": "From a502574b7e3283c8bf8b475b892ed6a6ddb01358 Mon Sep 17 00:00:00 2001\nFrom: AMuszkat <ariel.muszkat@gmail.com>\nDate: Sun, 28 Mar 2021 21:46:09 +0200\nSubject: [PATCH] overlays: merus-amp: remove spi override\n\nSigned-off-by: AMuszkat <ariel.muszkat@gmail.com>\n---\n arch/arm/boot/dts/overlays/merus-amp-overlay.dts | 10 ----------\n 1 file changed, 10 deletions(-)\n\n--- a/arch/arm/boot/dts/overlays/merus-amp-overlay.dts\n+++ b/arch/arm/boot/dts/overlays/merus-amp-overlay.dts\n@@ -57,14 +57,4 @@\n \t\t\tstatus = \"okay\";\n \t\t};\n \t};\n-\n-\tfragment@4 {\n-\t\ttarget = <&spi0>;\n-\t\tfrag4: __overlay__ {\n-\t\t};\n-\t};\n-\n-\t__overrides__ {\n-\t\tspioff = <&frag4>, \"status=disabled\";\n-\t};\n };\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0605-media-i2c-ov5647-Correct-pixel-array-offset.patch",
    "content": "From c4237f47536b91e894e26439353546e17c1221dc Mon Sep 17 00:00:00 2001\nFrom: David Plowman <david.plowman@raspberrypi.com>\nDate: Tue, 11 May 2021 12:52:26 +0100\nSubject: [PATCH] media: i2c: ov5647: Correct pixel array offset\n\nThe top offset in the pixel array is actually 6 (see page 3-1 of the\nOV5647 data sheet).\n\nFixes: f2f7ad5ce5e52 (\"media: i2c: ov5647: Selection compliance fixes\")\nSigned-off-by: David Plowman <david.plowman@raspberrypi.com>\n---\n drivers/media/i2c/ov5647.c | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/drivers/media/i2c/ov5647.c\n+++ b/drivers/media/i2c/ov5647.c\n@@ -77,7 +77,7 @@\n #define OV5647_NATIVE_HEIGHT\t\t1956U\n \n #define OV5647_PIXEL_ARRAY_LEFT\t\t16U\n-#define OV5647_PIXEL_ARRAY_TOP\t\t16U\n+#define OV5647_PIXEL_ARRAY_TOP\t\t6U\n #define OV5647_PIXEL_ARRAY_WIDTH\t2592U\n #define OV5647_PIXEL_ARRAY_HEIGHT\t1944U\n \n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0606-media-i2c-ov5647-Correct-minimum-VBLANK-value.patch",
    "content": "From 6131e50bfae6adb5ee52ad0d08cf12bfcbf8c606 Mon Sep 17 00:00:00 2001\nFrom: David Plowman <david.plowman@raspberrypi.com>\nDate: Tue, 11 May 2021 12:57:22 +0100\nSubject: [PATCH] media: i2c: ov5647: Correct minimum VBLANK value\n\nTrial and error reveals that the minimum vblank value appears to be 24\n(the OV5647 data sheet does not give any clues). This fixes streaming\nlock-ups in full resolution mode.\n\nFixes: 9b5a5ebedc303 (\"media: i2c: ov5647: Add support for V4L2_CID_VBLANK\")\nSigned-off-by: David Plowman <david.plowman@raspberrypi.com>\n---\n drivers/media/i2c/ov5647.c | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/drivers/media/i2c/ov5647.c\n+++ b/drivers/media/i2c/ov5647.c\n@@ -81,7 +81,7 @@\n #define OV5647_PIXEL_ARRAY_WIDTH\t2592U\n #define OV5647_PIXEL_ARRAY_HEIGHT\t1944U\n \n-#define OV5647_VBLANK_MIN\t\t4\n+#define OV5647_VBLANK_MIN\t\t24\n #define OV5647_VTS_MAX\t\t\t32767\n \n #define OV5647_EXPOSURE_MIN\t\t4\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0607-media-i2c-ov5647-Fix-v4l2-compliance-failure-subscri.patch",
    "content": "From c4a7091e7abe17e0d5a9d28fc5ad695f5ba599ae Mon Sep 17 00:00:00 2001\nFrom: David Plowman <david.plowman@raspberrypi.com>\nDate: Wed, 12 May 2021 07:39:21 +0100\nSubject: [PATCH] media: i2c: ov5647: Fix v4l2-compliance failure\n subscribing to events\n\nFixes the following v4l2-compliance failure:\n\nfail: v4l2-test-controls.cpp(871): subscribe event for control 'User Controls' failed test\n\nSigned-off-by: David Plowman <david.plowman@raspberrypi.com>\n---\n drivers/media/i2c/ov5647.c | 3 +++\n 1 file changed, 3 insertions(+)\n\n--- a/drivers/media/i2c/ov5647.c\n+++ b/drivers/media/i2c/ov5647.c\n@@ -31,6 +31,7 @@\n #include <linux/videodev2.h>\n #include <media/v4l2-ctrls.h>\n #include <media/v4l2-device.h>\n+#include <media/v4l2-event.h>\n #include <media/v4l2-fwnode.h>\n #include <media/v4l2-image-sizes.h>\n #include <media/v4l2-mediabus.h>\n@@ -1039,6 +1040,8 @@ static const struct v4l2_subdev_core_ops\n \t.g_register\t\t= ov5647_sensor_get_register,\n \t.s_register\t\t= ov5647_sensor_set_register,\n #endif\n+\t.subscribe_event = v4l2_ctrl_subdev_subscribe_event,\n+\t.unsubscribe_event = v4l2_event_subdev_unsubscribe,\n };\n \n static const struct v4l2_rect *\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0608-dtoverlays-Add-pinctrl-names-to-i2c0-overlay.patch",
    "content": "From 26715b72c201ab22e44698505969078520bddce0 Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Wed, 12 May 2021 16:44:11 +0100\nSubject: [PATCH] dtoverlays: Add pinctrl-names to i2c0 overlay.\n\nUsing dtoverlay=i2c0 failed to set up the pinctrl nodes as\npinctrl-name = \"default\"; was missing from the i2c0if node.\n\nhttps://www.raspberrypi.org/forums/viewtopic.php?f=107&t=311686&p=1864112\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n arch/arm/boot/dts/overlays/i2c0-overlay.dts | 1 +\n 1 file changed, 1 insertion(+)\n\n--- a/arch/arm/boot/dts/overlays/i2c0-overlay.dts\n+++ b/arch/arm/boot/dts/overlays/i2c0-overlay.dts\n@@ -8,6 +8,7 @@\n \t\ttarget = <&i2c0if>;\n \t\t__overlay__ {\n \t\t\tstatus = \"okay\";\n+\t\t\tpinctrl-names = \"default\";\n \t\t\tpinctrl-0 = <&i2c0_pins>;\n \t\t};\n \t};\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0609-dtoverlays-Update-__symbols__-i2c0-from-i2c0-overlay.patch",
    "content": "From a21652bfb50b240936124de0dbc288418106e5de Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Wed, 12 May 2021 16:47:05 +0100\nSubject: [PATCH] dtoverlays: Update /__symbols__/i2c0 from i2c0\n overlay\n\nUpdate the symbol as well as the alias so that other overlays will\nthen be applied against the right node.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n arch/arm/boot/dts/overlays/i2c0-overlay.dts | 8 ++++++++\n 1 file changed, 8 insertions(+)\n\n--- a/arch/arm/boot/dts/overlays/i2c0-overlay.dts\n+++ b/arch/arm/boot/dts/overlays/i2c0-overlay.dts\n@@ -65,6 +65,14 @@\n \t\t\ti2c0 = \"/soc/i2c@7e205000\";\n \t\t};\n \t};\n+\n+\tfragment@8 {\n+\t\ttarget-path = \"/__symbols__\";\n+\t\t__overlay__ {\n+\t\t\ti2c0 = \"/soc/i2c@7e205000\";\n+\t\t};\n+\t};\n+\n \t__overrides__ {\n \t\tpins_0_1   = <0>,\"+1-2-3-4\";\n \t\tpins_28_29 = <0>,\"-1+2-3-4\";\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0610-media-rpivid-Remove-the-need-to-have-num_entry_point.patch",
    "content": "From 0962d9e4a57c3faa29000c63c1cb28ad39a6c80c Mon Sep 17 00:00:00 2001\nFrom: John Cox <jc@kynesim.co.uk>\nDate: Thu, 21 May 2020 11:49:37 +0100\nSubject: [PATCH] media: rpivid: Remove the need to have\n num_entry_points set\n\nVAAPI H265 has num entry points but never sets it. Allow a VAAPI\nshim to work without requiring rewriting the VAAPI driver.\nnum_entry_points can be calculated from the slice_segment_addr\nof the next slice so delay processing until we have that.\n\nAlso includes some minor cosmetics.\n\nSigned-off-by: John Cox <jc@kynesim.co.uk>\n---\n drivers/staging/media/rpivid/rpivid_h265.c | 699 +++++++++++----------\n 1 file changed, 365 insertions(+), 334 deletions(-)\n\n--- a/drivers/staging/media/rpivid/rpivid_h265.c\n+++ b/drivers/staging/media/rpivid/rpivid_h265.c\n@@ -202,8 +202,17 @@ struct rpivid_dec_env {\n \tunsigned int dpbno_col;\n \tu32 reg_slicestart;\n \tint collocated_from_l0_flag;\n-\tunsigned int wpp_entry_x;\n-\tunsigned int wpp_entry_y;\n+\t/*\n+\t * Last CTB/Tile X,Y processed by (wpp_)entry_point\n+\t * Could be in _state as P0 only but needs updating where _state\n+\t * is const\n+\t */\n+\tunsigned int entry_ctb_x;\n+\tunsigned int entry_ctb_y;\n+\tunsigned int entry_tile_x;\n+\tunsigned int entry_tile_y;\n+\tunsigned int entry_qp;\n+\tu32 entry_slice;\n \n \tu32 rpi_config2;\n \tu32 rpi_framesize;\n@@ -239,22 +248,17 @@ struct rpivid_dec_state {\n \tstruct v4l2_ctrl_hevc_pps pps;\n \n \t// Helper vars & tables derived from sps/pps\n-\tunsigned int log2_ctb_size; /* log2 width of a CTB */\n-\tunsigned int ctb_width; /* Width in CTBs */\n-\tunsigned int ctb_height; /* Height in CTBs */\n-\tunsigned int ctb_size; /* Pic area in CTBs */\n-\tunsigned int num_tile_columns;\n-\tunsigned int num_tile_rows;\n-\tu8 column_width[member_size(struct v4l2_ctrl_hevc_pps,\n-\t\t\t\t    column_width_minus1)];\n-\tu8 row_height[member_size(struct v4l2_ctrl_hevc_pps,\n-\t\t\t\t  row_height_minus1)];\n+\tunsigned int log2_ctb_size;     /* log2 width of a CTB */\n+\tunsigned int ctb_width;         /* Width in CTBs */\n+\tunsigned int ctb_height;        /* Height in CTBs */\n+\tunsigned int ctb_size;          /* Pic area in CTBs */\n+\tunsigned int tile_width;        /* Width in tiles */\n+\tunsigned int tile_height;       /* Height in tiles */\n \n \tint *col_bd;\n \tint *row_bd;\n \tint *ctb_addr_rs_to_ts;\n \tint *ctb_addr_ts_to_rs;\n-\tint *tile_id;\n \n \t// Aux starage for DPB\n \t// Hold refs\n@@ -274,6 +278,12 @@ struct rpivid_dec_state {\n \tunsigned int slice_qp;\n \tunsigned int max_num_merge_cand; // 0 if I-slice\n \tbool dependent_slice_segment_flag;\n+\n+\tunsigned int start_ts;          /* slice_segment_addr -> ts */\n+\tunsigned int start_ctb_x;       /* CTB X,Y of start_ts */\n+\tunsigned int start_ctb_y;\n+\tunsigned int prev_ctb_x;        /* CTB X,Y of start_ts - 1 */\n+\tunsigned int prev_ctb_y;\n };\n \n static inline int clip_int(const int x, const int lo, const int hi)\n@@ -319,15 +329,16 @@ static int ctb_to_tile(unsigned int ctb,\n \treturn i - 1;\n }\n \n-static int ctb_to_slice_w_h(unsigned int ctb, int ctb_size, int width,\n-\t\t\t    unsigned int *bd, int num)\n+static unsigned int ctb_to_tile_x(const struct rpivid_dec_state *const s,\n+\t\t\t\t  const unsigned int ctb_x)\n {\n-\tif (ctb < bd[num - 1])\n-\t\treturn ctb_size;\n-\telse if (width % ctb_size)\n-\t\treturn width % ctb_size;\n-\telse\n-\t\treturn ctb_size;\n+\treturn ctb_to_tile(ctb_x, s->col_bd, s->tile_width);\n+}\n+\n+static unsigned int ctb_to_tile_y(const struct rpivid_dec_state *const s,\n+\t\t\t\t  const unsigned int ctb_y)\n+{\n+\treturn ctb_to_tile(ctb_y, s->row_bd, s->tile_height);\n }\n \n static void aux_q_free(struct rpivid_ctx *const ctx,\n@@ -532,6 +543,15 @@ static void write_prob(struct rpivid_dec\n \t\tp1_apb_write(de, 0x1000 + i,\n \t\t\t     dst[i] + (dst[i + 1] << 8) + (dst[i + 2] << 16) +\n \t\t\t\t     (dst[i + 3] << 24));\n+\n+\t/*\n+\t * Having written the prob array back it up\n+\t * This is not always needed but is a small overhead that simplifies\n+\t * (and speeds up) some multi-tile & WPP scenarios\n+\t * There are no scenarios where having written a prob we ever want\n+\t * a previous (non-initial) state back\n+\t */\n+\tp1_apb_write(de, RPI_TRANSFER, PROB_BACKUP);\n }\n \n static void write_scaling_factors(struct rpivid_dec_env *const de)\n@@ -552,8 +572,8 @@ static inline __u32 dma_to_axi_addr(dma_\n static void write_bitstream(struct rpivid_dec_env *const de,\n \t\t\t    const struct rpivid_dec_state *const s)\n {\n-\t// Note that FFmpeg removes emulation prevention bytes, so this is\n-\t// matched in the configuration here.\n+\t// Note that FFmpeg V4L2 does not remove emulation prevention bytes,\n+\t// so this is matched in the configuration here.\n \t// Whether that is the correct behaviour or not is not clear in the\n \t// spec.\n \tconst int rpi_use_emu = 1;\n@@ -579,78 +599,26 @@ static void write_bitstream(struct rpivi\n \n //////////////////////////////////////////////////////////////////////////////\n \n-static void write_slice(struct rpivid_dec_env *const de,\n-\t\t\tconst struct rpivid_dec_state *const s,\n-\t\t\tconst unsigned int slice_w,\n-\t\t\tconst unsigned int slice_h)\n-{\n-\tu32 u32 = (s->sh->slice_type << 12) +\n-\t\t  (((s->sh->flags &\n-\t\t     V4L2_HEVC_SLICE_PARAMS_FLAG_SLICE_SAO_LUMA) != 0)\n-\t\t   << 14) +\n-\t\t  (((s->sh->flags &\n-\t\t     V4L2_HEVC_SLICE_PARAMS_FLAG_SLICE_SAO_CHROMA) != 0)\n-\t\t   << 15) +\n-\t\t  (slice_w << 17) + (slice_h << 24);\n-\n-\tu32 |= (s->max_num_merge_cand << 0) + (s->nb_refs[L0] << 4) +\n-\t       (s->nb_refs[L1] << 8);\n-\n-\tif (s->sh->slice_type == HEVC_SLICE_B)\n-\t\tu32 |= ((s->sh->flags &\n-\t\t\t V4L2_HEVC_SLICE_PARAMS_FLAG_MVD_L1_ZERO) != 0)\n-\t\t       << 16;\n-\tp1_apb_write(de, RPI_SLICE, u32);\n-}\n-\n-//////////////////////////////////////////////////////////////////////////////\n-// Tiles mode\n-\n-static void new_entry_point(struct rpivid_dec_env *const de,\n-\t\t\t    const struct rpivid_dec_state *const s,\n-\t\t\t    const int do_bte,\n-\t\t\t    const int reset_qp_y, const int ctb_addr_ts)\n+/*\n+ * The slice constant part of the slice register - width and height need to\n+ * be ORed in later as they are per-tile / WPP-row\n+ */\n+static u32 slice_reg_const(const struct rpivid_dec_state *const s)\n {\n-\tint ctb_col = s->ctb_addr_ts_to_rs[ctb_addr_ts] %\n-\t\t\t\t\t\t\tde->pic_width_in_ctbs_y;\n-\tint ctb_row = s->ctb_addr_ts_to_rs[ctb_addr_ts] /\n-\t\t\t\t\t\t\tde->pic_width_in_ctbs_y;\n-\n-\tint tile_x = ctb_to_tile(ctb_col, s->col_bd, s->num_tile_columns);\n-\tint tile_y = ctb_to_tile(ctb_row, s->row_bd, s->num_tile_rows);\n-\n-\tint endx = s->col_bd[tile_x + 1] - 1;\n-\tint endy = s->row_bd[tile_y + 1] - 1;\n-\n-\tu8 slice_w = ctb_to_slice_w_h(ctb_col, 1 << s->log2_ctb_size,\n-\t\t\t\t      s->sps.pic_width_in_luma_samples,\n-\t\t\t\t      s->col_bd, s->num_tile_columns);\n-\tu8 slice_h = ctb_to_slice_w_h(ctb_row, 1 << s->log2_ctb_size,\n-\t\t\t\t      s->sps.pic_height_in_luma_samples,\n-\t\t\t\t      s->row_bd, s->num_tile_rows);\n-\n-\tp1_apb_write(de, RPI_TILESTART,\n-\t\t     s->col_bd[tile_x] + (s->row_bd[tile_y] << 16));\n-\tp1_apb_write(de, RPI_TILEEND, endx + (endy << 16));\n-\n-\tif (do_bte)\n-\t\tp1_apb_write(de, RPI_BEGINTILEEND, endx + (endy << 16));\n+\tu32 x = (s->max_num_merge_cand << 0) |\n+\t\t(s->nb_refs[L0] << 4) |\n+\t\t(s->nb_refs[L1] << 8) |\n+\t\t(s->sh->slice_type << 12);\n+\n+\tif (s->sh->flags & V4L2_HEVC_SLICE_PARAMS_FLAG_SLICE_SAO_LUMA)\n+\t\tx |= BIT(14);\n+\tif (s->sh->flags & V4L2_HEVC_SLICE_PARAMS_FLAG_SLICE_SAO_CHROMA)\n+\t\tx |= BIT(15);\n+\tif (s->sh->slice_type == HEVC_SLICE_B &&\n+\t    (s->sh->flags & V4L2_HEVC_SLICE_PARAMS_FLAG_MVD_L1_ZERO))\n+\t\tx |= BIT(16);\n \n-\twrite_slice(de, s, slice_w, slice_h);\n-\n-\tif (reset_qp_y) {\n-\t\tunsigned int sps_qp_bd_offset =\n-\t\t\t6 * s->sps.bit_depth_luma_minus8;\n-\n-\t\tp1_apb_write(de, RPI_QP, sps_qp_bd_offset + s->slice_qp);\n-\t}\n-\n-\tp1_apb_write(de, RPI_MODE,\n-\t\t     (0xFFFF << 0) + (0x0 << 16) +\n-\t\t\t     ((tile_x == s->num_tile_columns - 1) << 17) +\n-\t\t\t     ((tile_y == s->num_tile_rows - 1) << 18));\n-\n-\tp1_apb_write(de, RPI_CONTROL, (ctb_col << 0) + (ctb_row << 16));\n+\treturn x;\n }\n \n //////////////////////////////////////////////////////////////////////////////\n@@ -934,197 +902,256 @@ static void pre_slice_decode(struct rpiv\n \t\t       (sh->slice_cb_qp_offset & 31)); // CMD_QPOFF\n }\n \n-//////////////////////////////////////////////////////////////////////////////\n-// Write STATUS register with expected end CTU address of previous slice\n-\n-static void end_previous_slice(struct rpivid_dec_env *const de,\n-\t\t\t       const struct rpivid_dec_state *const s,\n-\t\t\t       const int ctb_addr_ts)\n-{\n-\tint last_x =\n-\t\ts->ctb_addr_ts_to_rs[ctb_addr_ts - 1] % de->pic_width_in_ctbs_y;\n-\tint last_y =\n-\t\ts->ctb_addr_ts_to_rs[ctb_addr_ts - 1] / de->pic_width_in_ctbs_y;\n-\n-\tp1_apb_write(de, RPI_STATUS, 1 + (last_x << 5) + (last_y << 18));\n-}\n-\n-static void wpp_pause(struct rpivid_dec_env *const de, int ctb_row)\n-{\n-\tp1_apb_write(de, RPI_STATUS, (ctb_row << 18) + 0x25);\n-\tp1_apb_write(de, RPI_TRANSFER, PROB_BACKUP);\n-\tp1_apb_write(de, RPI_MODE,\n-\t\t     ctb_row == de->pic_height_in_ctbs_y - 1 ?\n-\t\t\t\t\t\t\t0x70000 : 0x30000);\n-\tp1_apb_write(de, RPI_CONTROL, (ctb_row << 16) + 2);\n-}\n-\n-static void wpp_end_previous_slice(struct rpivid_dec_env *const de,\n-\t\t\t\t   const struct rpivid_dec_state *const s,\n-\t\t\t\t   int ctb_addr_ts)\n-{\n-\tint new_x = s->sh->slice_segment_addr % de->pic_width_in_ctbs_y;\n-\tint new_y = s->sh->slice_segment_addr / de->pic_width_in_ctbs_y;\n-\tint last_x =\n-\t\ts->ctb_addr_ts_to_rs[ctb_addr_ts - 1] % de->pic_width_in_ctbs_y;\n-\tint last_y =\n-\t\ts->ctb_addr_ts_to_rs[ctb_addr_ts - 1] / de->pic_width_in_ctbs_y;\n-\n-\tif (de->wpp_entry_x < 2 && (de->wpp_entry_y < new_y || new_x > 2) &&\n-\t    de->pic_width_in_ctbs_y > 2)\n-\t\twpp_pause(de, last_y);\n-\tp1_apb_write(de, RPI_STATUS, 1 + (last_x << 5) + (last_y << 18));\n-\tif (new_x == 2 || (de->pic_width_in_ctbs_y == 2 &&\n-\t\t\t   de->wpp_entry_y < new_y))\n-\t\tp1_apb_write(de, RPI_TRANSFER, PROB_BACKUP);\n+static void write_slice(struct rpivid_dec_env *const de,\n+\t\t\tconst struct rpivid_dec_state *const s,\n+\t\t\tconst u32 slice_const,\n+\t\t\tconst unsigned int ctb_col,\n+\t\t\tconst unsigned int ctb_row)\n+{\n+\tconst unsigned int cs = (1 << s->log2_ctb_size);\n+\tconst unsigned int w_last = s->sps.pic_width_in_luma_samples & (cs - 1);\n+\tconst unsigned int h_last = s->sps.pic_height_in_luma_samples & (cs - 1);\n+\n+\tp1_apb_write(de, RPI_SLICE,\n+\t\t     slice_const |\n+\t\t     ((ctb_col + 1 < s->ctb_width || !w_last ?\n+\t\t\t\tcs : w_last) << 17) |\n+\t\t     ((ctb_row + 1 < s->ctb_height || !h_last ?\n+\t\t\t\tcs : h_last) << 24));\n }\n \n-//////////////////////////////////////////////////////////////////////////////\n-// Wavefront mode\n+#define PAUSE_MODE_WPP  1\n+#define PAUSE_MODE_TILE 0xffff\n \n-static void wpp_entry_point(struct rpivid_dec_env *const de,\n+/*\n+ * N.B. This can be called to fill in data from the previous slice so must not\n+ * use any state data that may change from slice to slice (e.g. qp)\n+ */\n+static void new_entry_point(struct rpivid_dec_env *const de,\n \t\t\t    const struct rpivid_dec_state *const s,\n-\t\t\t    const int do_bte,\n-\t\t\t    const int reset_qp_y, const int ctb_addr_ts)\n-{\n-\tint ctb_size = 1 << s->log2_ctb_size;\n-\tint ctb_addr_rs = s->ctb_addr_ts_to_rs[ctb_addr_ts];\n-\n-\tint ctb_col = de->wpp_entry_x = ctb_addr_rs % de->pic_width_in_ctbs_y;\n-\tint ctb_row = de->wpp_entry_y = ctb_addr_rs / de->pic_width_in_ctbs_y;\n+\t\t\t    const bool do_bte,\n+\t\t\t    const bool reset_qp_y,\n+\t\t\t    const u32 pause_mode,\n+\t\t\t    const unsigned int tile_x,\n+\t\t\t    const unsigned int tile_y,\n+\t\t\t    const unsigned int ctb_col,\n+\t\t\t    const unsigned int ctb_row,\n+\t\t\t    const unsigned int slice_qp,\n+\t\t\t    const u32 slice_const)\n+{\n+\tconst unsigned int endx = s->col_bd[tile_x + 1] - 1;\n+\tconst unsigned int endy = (pause_mode == PAUSE_MODE_WPP) ?\n+\t\tctb_row : s->row_bd[tile_y + 1] - 1;\n \n-\tint endx = de->pic_width_in_ctbs_y - 1;\n-\tint endy = ctb_row;\n-\n-\tu8 slice_w = ctb_to_slice_w_h(ctb_col, ctb_size,\n-\t\t\t\t      s->sps.pic_width_in_luma_samples,\n-\t\t\t\t      s->col_bd, s->num_tile_columns);\n-\tu8 slice_h = ctb_to_slice_w_h(ctb_row, ctb_size,\n-\t\t\t\t      s->sps.pic_height_in_luma_samples,\n-\t\t\t\t      s->row_bd, s->num_tile_rows);\n-\n-\tp1_apb_write(de, RPI_TILESTART, 0);\n-\tp1_apb_write(de, RPI_TILEEND, endx + (endy << 16));\n+\tp1_apb_write(de, RPI_TILESTART,\n+\t\t     s->col_bd[tile_x] | (s->row_bd[tile_y] << 16));\n+\tp1_apb_write(de, RPI_TILEEND, endx | (endy << 16));\n \n \tif (do_bte)\n-\t\tp1_apb_write(de, RPI_BEGINTILEEND, endx + (endy << 16));\n+\t\tp1_apb_write(de, RPI_BEGINTILEEND, endx | (endy << 16));\n \n-\twrite_slice(de, s, slice_w,\n-\t\t    ctb_row == de->pic_height_in_ctbs_y - 1 ?\n-\t\t\t\t\t\t\tslice_h : ctb_size);\n+\twrite_slice(de, s, slice_const, endx, endy);\n \n \tif (reset_qp_y) {\n \t\tunsigned int sps_qp_bd_offset =\n \t\t\t6 * s->sps.bit_depth_luma_minus8;\n \n-\t\tp1_apb_write(de, RPI_QP, sps_qp_bd_offset + s->slice_qp);\n+\t\tp1_apb_write(de, RPI_QP, sps_qp_bd_offset + slice_qp);\n \t}\n \n \tp1_apb_write(de, RPI_MODE,\n-\t\t     ctb_row == de->pic_height_in_ctbs_y - 1 ?\n-\t\t\t\t\t\t\t0x60001 : 0x20001);\n-\tp1_apb_write(de, RPI_CONTROL, (ctb_col << 0) + (ctb_row << 16));\n+\t\t     pause_mode |\n+\t\t\t((endx == s->ctb_width - 1) << 17) |\n+\t\t\t((endy == s->ctb_height - 1) << 18));\n+\n+\tp1_apb_write(de, RPI_CONTROL, (ctb_col << 0) | (ctb_row << 16));\n+\n+\tde->entry_tile_x = tile_x;\n+\tde->entry_tile_y = tile_y;\n+\tde->entry_ctb_x = ctb_col;\n+\tde->entry_ctb_y = ctb_row;\n+\tde->entry_qp = slice_qp;\n+\tde->entry_slice = slice_const;\n }\n \n //////////////////////////////////////////////////////////////////////////////\n // Wavefront mode\n \n+static void wpp_pause(struct rpivid_dec_env *const de, int ctb_row)\n+{\n+\tp1_apb_write(de, RPI_STATUS, (ctb_row << 18) | 0x25);\n+\tp1_apb_write(de, RPI_TRANSFER, PROB_BACKUP);\n+\tp1_apb_write(de, RPI_MODE,\n+\t\t     ctb_row == de->pic_height_in_ctbs_y - 1 ?\n+\t\t\t\t\t\t\t0x70000 : 0x30000);\n+\tp1_apb_write(de, RPI_CONTROL, (ctb_row << 16) + 2);\n+}\n+\n+static void wpp_entry_fill(struct rpivid_dec_env *const de,\n+\t\t\t   const struct rpivid_dec_state *const s,\n+\t\t\t   const unsigned int last_y)\n+{\n+\tconst unsigned int last_x = s->ctb_width - 1;\n+\n+\twhile (de->entry_ctb_y < last_y) {\n+\t\t/* wpp_entry_x/y set by wpp_entry_point */\n+\t\tif (s->ctb_width > 2)\n+\t\t\twpp_pause(de, de->entry_ctb_y);\n+\t\tp1_apb_write(de, RPI_STATUS,\n+\t\t\t     (de->entry_ctb_y << 18) | (last_x << 5) | 2);\n+\n+\t\t/* if width == 1 then the saved state is the init one */\n+\t\tif (s->ctb_width == 2)\n+\t\t\tp1_apb_write(de, RPI_TRANSFER, PROB_BACKUP);\n+\t\telse\n+\t\t\tp1_apb_write(de, RPI_TRANSFER, PROB_RELOAD);\n+\n+\t\tnew_entry_point(de, s, false, true, PAUSE_MODE_WPP,\n+\t\t\t\t0, 0, 0, de->entry_ctb_y + 1,\n+\t\t\t\tde->entry_qp, de->entry_slice);\n+\t}\n+}\n+\n+static void wpp_end_previous_slice(struct rpivid_dec_env *const de,\n+\t\t\t\t   const struct rpivid_dec_state *const s)\n+{\n+\twpp_entry_fill(de, s, s->prev_ctb_y);\n+\n+\tif (de->entry_ctb_x < 2 &&\n+\t    (de->entry_ctb_y < s->start_ctb_y || s->start_ctb_x > 2) &&\n+\t    s->ctb_width > 2)\n+\t\twpp_pause(de, s->prev_ctb_y);\n+\tp1_apb_write(de, RPI_STATUS,\n+\t\t     1 | (s->prev_ctb_x << 5) | (s->prev_ctb_y << 18));\n+\tif (s->start_ctb_x == 2 ||\n+\t    (s->ctb_width == 2 && de->entry_ctb_y < s->start_ctb_y))\n+\t\tp1_apb_write(de, RPI_TRANSFER, PROB_BACKUP);\n+}\n+\n+/* Only main profile supported so WPP => !Tiles which makes some of the\n+ * next chunk code simpler\n+ */\n static void wpp_decode_slice(struct rpivid_dec_env *const de,\n-\t\t\t     const struct rpivid_dec_state *const s,\n-\t\t\t     const struct v4l2_ctrl_hevc_slice_params *sh,\n-\t\t\t     int ctb_addr_ts)\n-{\n-\tint i, reset_qp_y = 1;\n-\tint indep = !s->dependent_slice_segment_flag;\n-\tint ctb_col = s->sh->slice_segment_addr % de->pic_width_in_ctbs_y;\n+\t\t\t     const struct rpivid_dec_state *const s)\n+{\n+\tbool reset_qp_y = true;\n+\tconst bool indep = !s->dependent_slice_segment_flag;\n \n-\tif (ctb_addr_ts)\n-\t\twpp_end_previous_slice(de, s, ctb_addr_ts);\n+\tif (s->start_ts)\n+\t\twpp_end_previous_slice(de, s);\n \tpre_slice_decode(de, s);\n \twrite_bitstream(de, s);\n-\tif (ctb_addr_ts == 0 || indep || de->pic_width_in_ctbs_y == 1)\n+\n+\tif (!s->start_ts || indep || s->ctb_width == 1)\n \t\twrite_prob(de, s);\n-\telse if (ctb_col == 0)\n+\telse if (!s->start_ctb_x)\n \t\tp1_apb_write(de, RPI_TRANSFER, PROB_RELOAD);\n \telse\n-\t\treset_qp_y = 0;\n+\t\treset_qp_y = false;\n+\n \tprogram_slicecmds(de, s->slice_idx);\n \tnew_slice_segment(de, s);\n-\twpp_entry_point(de, s, indep, reset_qp_y, ctb_addr_ts);\n+\tnew_entry_point(de, s, indep, reset_qp_y, PAUSE_MODE_WPP,\n+\t\t\t0, 0, s->start_ctb_x, s->start_ctb_y,\n+\t\t\ts->slice_qp, slice_reg_const(s));\n \n-\tfor (i = 0; i < s->sh->num_entry_point_offsets; i++) {\n-\t\tint ctb_addr_rs = s->ctb_addr_ts_to_rs[ctb_addr_ts];\n-\t\tint ctb_row = ctb_addr_rs / de->pic_width_in_ctbs_y;\n-\t\tint last_x = de->pic_width_in_ctbs_y - 1;\n+\tif (s->frame_end) {\n+\t\twpp_entry_fill(de, s, s->ctb_height - 1);\n+\n+\t\tif (de->entry_ctb_x < 2 && s->ctb_width > 2)\n+\t\t\twpp_pause(de, s->ctb_height - 1);\n \n-\t\tif (de->pic_width_in_ctbs_y > 2)\n-\t\t\twpp_pause(de, ctb_row);\n \t\tp1_apb_write(de, RPI_STATUS,\n-\t\t\t     (ctb_row << 18) + (last_x << 5) + 2);\n-\t\tif (de->pic_width_in_ctbs_y == 2)\n-\t\t\tp1_apb_write(de, RPI_TRANSFER, PROB_BACKUP);\n-\t\tif (de->pic_width_in_ctbs_y == 1)\n-\t\t\twrite_prob(de, s);\n-\t\telse\n-\t\t\tp1_apb_write(de, RPI_TRANSFER, PROB_RELOAD);\n-\t\tctb_addr_ts += s->column_width[0];\n-\t\twpp_entry_point(de, s, 0, 1, ctb_addr_ts);\n+\t\t\t     1 | ((s->ctb_width - 1) << 5) |\n+\t\t\t\t((s->ctb_height - 1) << 18));\n \t}\n+\n }\n \n //////////////////////////////////////////////////////////////////////////////\n // Tiles mode\n \n+static void tile_entry_fill(struct rpivid_dec_env *const de,\n+\t\t\t    const struct rpivid_dec_state *const s,\n+\t\t\t    const unsigned int last_tile_x,\n+\t\t\t    const unsigned int last_tile_y)\n+{\n+\twhile (de->entry_tile_y < last_tile_y ||\n+\t       (de->entry_tile_y == last_tile_y &&\n+\t\tde->entry_tile_x < last_tile_x)) {\n+\t\tunsigned int t_x = de->entry_tile_x;\n+\t\tunsigned int t_y = de->entry_tile_y;\n+\t\tconst unsigned int last_x = s->col_bd[t_x + 1] - 1;\n+\t\tconst unsigned int last_y = s->row_bd[t_y + 1] - 1;\n+\n+\t\tp1_apb_write(de, RPI_STATUS,\n+\t\t\t     2 | (last_x << 5) | (last_y << 18));\n+\t\tp1_apb_write(de, RPI_TRANSFER, PROB_RELOAD);\n+\n+\t\t// Inc tile\n+\t\tif (++t_x >= s->tile_width) {\n+\t\t\tt_x = 0;\n+\t\t\t++t_y;\n+\t\t}\n+\n+\t\tnew_entry_point(de, s, false, true, PAUSE_MODE_TILE,\n+\t\t\t\tt_x, t_y, s->col_bd[t_x], s->row_bd[t_y],\n+\t\t\t\tde->entry_qp, de->entry_slice);\n+\t}\n+}\n+\n+/*\n+ * Write STATUS register with expected end CTU address of previous slice\n+ */\n+static void end_previous_slice(struct rpivid_dec_env *const de,\n+\t\t\t       const struct rpivid_dec_state *const s)\n+{\n+\ttile_entry_fill(de, s,\n+\t\t\tctb_to_tile_x(s, s->prev_ctb_x),\n+\t\t\tctb_to_tile_y(s, s->prev_ctb_y));\n+\tp1_apb_write(de, RPI_STATUS,\n+\t\t     1 | (s->prev_ctb_x << 5) | (s->prev_ctb_y << 18));\n+}\n+\n static void decode_slice(struct rpivid_dec_env *const de,\n-\t\t\t const struct rpivid_dec_state *const s,\n-\t\t\t const struct v4l2_ctrl_hevc_slice_params *const sh,\n-\t\t\t int ctb_addr_ts)\n+\t\t\t const struct rpivid_dec_state *const s)\n {\n-\tint i, reset_qp_y;\n+\tbool reset_qp_y;\n+\tunsigned int tile_x = ctb_to_tile_x(s, s->start_ctb_x);\n+\tunsigned int tile_y = ctb_to_tile_y(s, s->start_ctb_y);\n \n-\tif (ctb_addr_ts)\n-\t\tend_previous_slice(de, s, ctb_addr_ts);\n+\tif (s->start_ts)\n+\t\tend_previous_slice(de, s);\n \n \tpre_slice_decode(de, s);\n \twrite_bitstream(de, s);\n \n-#if DEBUG_TRACE_P1_CMD\n-\tif (p1_z < 256) {\n-\t\tv4l2_info(&de->ctx->dev->v4l2_dev,\n-\t\t\t  \"TS=%d, tile=%d/%d, dss=%d, flags=%#llx\\n\",\n-\t\t\t  ctb_addr_ts, s->tile_id[ctb_addr_ts],\n-\t\t\t  s->tile_id[ctb_addr_ts - 1],\n-\t\t\t  s->dependent_slice_segment_flag, sh->flags);\n-\t}\n-#endif\n-\n-\treset_qp_y = ctb_addr_ts == 0 ||\n-\t\t   s->tile_id[ctb_addr_ts] != s->tile_id[ctb_addr_ts - 1] ||\n-\t\t   !s->dependent_slice_segment_flag;\n+\treset_qp_y = !s->start_ts ||\n+\t\t!s->dependent_slice_segment_flag ||\n+\t\ttile_x != ctb_to_tile_x(s, s->prev_ctb_x) ||\n+\t\ttile_y != ctb_to_tile_y(s, s->prev_ctb_y);\n \tif (reset_qp_y)\n \t\twrite_prob(de, s);\n \n \tprogram_slicecmds(de, s->slice_idx);\n \tnew_slice_segment(de, s);\n \tnew_entry_point(de, s, !s->dependent_slice_segment_flag, reset_qp_y,\n-\t\t\tctb_addr_ts);\n-\n-\tfor (i = 0; i < s->sh->num_entry_point_offsets; i++) {\n-\t\tint ctb_addr_rs = s->ctb_addr_ts_to_rs[ctb_addr_ts];\n-\t\tint ctb_col = ctb_addr_rs % de->pic_width_in_ctbs_y;\n-\t\tint ctb_row = ctb_addr_rs / de->pic_width_in_ctbs_y;\n-\t\tint tile_x = ctb_to_tile(ctb_col, s->col_bd,\n-\t\t\t\t\t s->num_tile_columns - 1);\n-\t\tint tile_y =\n-\t\t\tctb_to_tile(ctb_row, s->row_bd, s->num_tile_rows - 1);\n-\t\tint last_x = s->col_bd[tile_x + 1] - 1;\n-\t\tint last_y = s->row_bd[tile_y + 1] - 1;\n+\t\t\tPAUSE_MODE_TILE,\n+\t\t\ttile_x, tile_y, s->start_ctb_x, s->start_ctb_y,\n+\t\t\ts->slice_qp, slice_reg_const(s));\n \n+\t/*\n+\t * If this is the last slice then fill in the other tile entries\n+\t * now, otherwise this will be done at the start of the next slice\n+\t * when it will be known where this slice finishes\n+\t */\n+\tif (s->frame_end) {\n+\t\ttile_entry_fill(de, s,\n+\t\t\t\ts->tile_width - 1,\n+\t\t\t\ts->tile_height - 1);\n \t\tp1_apb_write(de, RPI_STATUS,\n-\t\t\t     2 + (last_x << 5) + (last_y << 18));\n-\t\twrite_prob(de, s);\n-\t\tctb_addr_ts += s->column_width[tile_x] * s->row_height[tile_y];\n-\t\tnew_entry_point(de, s, 0, 1, ctb_addr_ts);\n+\t\t\t     1 | ((s->ctb_width - 1) << 5) |\n+\t\t\t\t((s->ctb_height - 1) << 18));\n \t}\n }\n \n@@ -1132,13 +1159,12 @@ static void decode_slice(struct rpivid_d\n // Scaling factors\n \n static void expand_scaling_list(const unsigned int size_id,\n-\t\t\t\tconst unsigned int matrix_id, u8 *const dst0,\n+\t\t\t\tu8 *const dst0,\n \t\t\t\tconst u8 *const src0, uint8_t dc)\n {\n \tu8 *d;\n \tunsigned int x, y;\n \n-\t// FIXME: matrix_id is unused ?\n \tswitch (size_id) {\n \tcase 0:\n \t\tmemcpy(dst0, src0, 16);\n@@ -1199,24 +1225,20 @@ static void populate_scaling_factors(con\n \tunsigned int mid;\n \n \tfor (mid = 0; mid < 6; mid++)\n-\t\texpand_scaling_list(0, mid,\n-\t\t\t\t    de->scaling_factors +\n+\t\texpand_scaling_list(0, de->scaling_factors +\n \t\t\t\t\t    scaling_factor_offsets[0][mid],\n \t\t\t\t    sl->scaling_list_4x4[mid], 0);\n \tfor (mid = 0; mid < 6; mid++)\n-\t\texpand_scaling_list(1, mid,\n-\t\t\t\t    de->scaling_factors +\n+\t\texpand_scaling_list(1, de->scaling_factors +\n \t\t\t\t\t    scaling_factor_offsets[1][mid],\n \t\t\t\t    sl->scaling_list_8x8[mid], 0);\n \tfor (mid = 0; mid < 6; mid++)\n-\t\texpand_scaling_list(2, mid,\n-\t\t\t\t    de->scaling_factors +\n+\t\texpand_scaling_list(2, de->scaling_factors +\n \t\t\t\t\t    scaling_factor_offsets[2][mid],\n \t\t\t\t    sl->scaling_list_16x16[mid],\n \t\t\t\t    sl->scaling_list_dc_coef_16x16[mid]);\n-\tfor (mid = 0; mid < 2; mid += 1)\n-\t\texpand_scaling_list(3, mid,\n-\t\t\t\t    de->scaling_factors +\n+\tfor (mid = 0; mid < 2; mid++)\n+\t\texpand_scaling_list(3, de->scaling_factors +\n \t\t\t\t\t    scaling_factor_offsets[3][mid],\n \t\t\t\t    sl->scaling_list_32x32[mid],\n \t\t\t\t    sl->scaling_list_dc_coef_32x32[mid]);\n@@ -1228,8 +1250,6 @@ static void free_ps_info(struct rpivid_d\n \ts->ctb_addr_rs_to_ts = NULL;\n \tkfree(s->ctb_addr_ts_to_rs);\n \ts->ctb_addr_ts_to_rs = NULL;\n-\tkfree(s->tile_id);\n-\ts->tile_id = NULL;\n \n \tkfree(s->col_bd);\n \ts->col_bd = NULL;\n@@ -1237,10 +1257,52 @@ static void free_ps_info(struct rpivid_d\n \ts->row_bd = NULL;\n }\n \n+static unsigned int tile_width(const struct rpivid_dec_state *const s,\n+\t\t\t       const unsigned int t_x)\n+{\n+\treturn s->col_bd[t_x + 1] - s->col_bd[t_x];\n+}\n+\n+static unsigned int tile_height(const struct rpivid_dec_state *const s,\n+\t\t\t\tconst unsigned int t_y)\n+{\n+\treturn s->row_bd[t_y + 1] - s->row_bd[t_y];\n+}\n+\n+static void fill_rs_to_ts(struct rpivid_dec_state *const s)\n+{\n+\tunsigned int ts = 0;\n+\tunsigned int t_y;\n+\tunsigned int tr_rs = 0;\n+\n+\tfor (t_y = 0; t_y != s->tile_height; ++t_y) {\n+\t\tconst unsigned int t_h = tile_height(s, t_y);\n+\t\tunsigned int t_x;\n+\t\tunsigned int tc_rs = tr_rs;\n+\n+\t\tfor (t_x = 0; t_x != s->tile_width; ++t_x) {\n+\t\t\tconst unsigned int t_w = tile_width(s, t_x);\n+\t\t\tunsigned int y;\n+\t\t\tunsigned int rs = tc_rs;\n+\n+\t\t\tfor (y = 0; y != t_h; ++y) {\n+\t\t\t\tunsigned int x;\n+\n+\t\t\t\tfor (x = 0; x != t_w; ++x) {\n+\t\t\t\t\ts->ctb_addr_rs_to_ts[rs + x] = ts;\n+\t\t\t\t\ts->ctb_addr_ts_to_rs[ts] = rs + x;\n+\t\t\t\t\t++ts;\n+\t\t\t\t}\n+\t\t\t\trs += s->ctb_width;\n+\t\t\t}\n+\t\t\ttc_rs += t_w;\n+\t\t}\n+\t\ttr_rs += t_h * s->ctb_width;\n+\t}\n+}\n+\n static int updated_ps(struct rpivid_dec_state *const s)\n {\n-\tunsigned int ctb_addr_rs;\n-\tint j, x, y, tile_id;\n \tunsigned int i;\n \n \tfree_ps_info(s);\n@@ -1259,104 +1321,49 @@ static int updated_ps(struct rpivid_dec_\n \n \t// Inferred parameters\n \n+\ts->ctb_addr_rs_to_ts = kmalloc_array(s->ctb_size,\n+\t\t\t\t\t     sizeof(*s->ctb_addr_rs_to_ts),\n+\t\t\t\t\t     GFP_KERNEL);\n+\ts->ctb_addr_ts_to_rs = kmalloc_array(s->ctb_size,\n+\t\t\t\t\t     sizeof(*s->ctb_addr_ts_to_rs),\n+\t\t\t\t\t     GFP_KERNEL);\n+\n \tif (!(s->pps.flags & V4L2_HEVC_PPS_FLAG_TILES_ENABLED)) {\n-\t\ts->num_tile_columns = 1;\n-\t\ts->num_tile_rows = 1;\n-\t\ts->column_width[0] = s->ctb_width;\n-\t\ts->row_height[0] = s->ctb_height;\n+\t\ts->tile_width = 1;\n+\t\ts->tile_height = 1;\n \t} else {\n-\t\ts->num_tile_columns = s->pps.num_tile_columns_minus1 + 1;\n-\t\ts->num_tile_rows = s->pps.num_tile_rows_minus1 + 1;\n-\t\tfor (i = 0; i < s->num_tile_columns; ++i)\n-\t\t\ts->column_width[i] = s->pps.column_width_minus1[i] + 1;\n-\t\tfor (i = 0; i < s->num_tile_rows; ++i)\n-\t\t\ts->row_height[i] = s->pps.row_height_minus1[i] + 1;\n+\t\ts->tile_width = s->pps.num_tile_columns_minus1 + 1;\n+\t\ts->tile_height = s->pps.num_tile_rows_minus1 + 1;\n \t}\n \n-\ts->col_bd = kmalloc((s->num_tile_columns + 1) * sizeof(*s->col_bd),\n+\ts->col_bd = kmalloc((s->tile_width + 1) * sizeof(*s->col_bd),\n \t\t\t    GFP_KERNEL);\n-\ts->row_bd = kmalloc((s->num_tile_rows + 1) * sizeof(*s->row_bd),\n+\ts->row_bd = kmalloc((s->tile_height + 1) * sizeof(*s->row_bd),\n \t\t\t    GFP_KERNEL);\n \n \ts->col_bd[0] = 0;\n-\tfor (i = 0; i < s->num_tile_columns; i++)\n-\t\ts->col_bd[i + 1] = s->col_bd[i] + s->column_width[i];\n+\tfor (i = 1; i < s->tile_width; i++)\n+\t\ts->col_bd[i] = s->col_bd[i - 1] +\n+\t\t\ts->pps.column_width_minus1[i - 1] + 1;\n+\ts->col_bd[s->tile_width] = s->ctb_width;\n \n \ts->row_bd[0] = 0;\n-\tfor (i = 0; i < s->num_tile_rows; i++)\n-\t\ts->row_bd[i + 1] = s->row_bd[i] + s->row_height[i];\n+\tfor (i = 1; i < s->tile_height; i++)\n+\t\ts->row_bd[i] = s->row_bd[i - 1] +\n+\t\t\ts->pps.row_height_minus1[i - 1] + 1;\n+\ts->row_bd[s->tile_height] = s->ctb_height;\n \n-\ts->ctb_addr_rs_to_ts = kmalloc_array(s->ctb_size,\n-\t\t\t\t\t     sizeof(*s->ctb_addr_rs_to_ts),\n-\t\t\t\t\t     GFP_KERNEL);\n-\ts->ctb_addr_ts_to_rs = kmalloc_array(s->ctb_size,\n-\t\t\t\t\t     sizeof(*s->ctb_addr_ts_to_rs),\n-\t\t\t\t\t     GFP_KERNEL);\n-\ts->tile_id = kmalloc_array(s->ctb_size, sizeof(*s->tile_id),\n-\t\t\t\t   GFP_KERNEL);\n-\n-\tfor (ctb_addr_rs = 0; ctb_addr_rs < s->ctb_size; ctb_addr_rs++) {\n-\t\tint tb_x = ctb_addr_rs % s->ctb_width;\n-\t\tint tb_y = ctb_addr_rs / s->ctb_width;\n-\t\tint tile_x = 0;\n-\t\tint tile_y = 0;\n-\t\tint val = 0;\n-\n-\t\tfor (i = 0; i < s->num_tile_columns; i++) {\n-\t\t\tif (tb_x < s->col_bd[i + 1]) {\n-\t\t\t\ttile_x = i;\n-\t\t\t\tbreak;\n-\t\t\t}\n-\t\t}\n-\n-\t\tfor (i = 0; i < s->num_tile_rows; i++) {\n-\t\t\tif (tb_y < s->row_bd[i + 1]) {\n-\t\t\t\ttile_y = i;\n-\t\t\t\tbreak;\n-\t\t\t}\n-\t\t}\n-\n-\t\tfor (i = 0; i < tile_x; i++)\n-\t\t\tval += s->row_height[tile_y] * s->column_width[i];\n-\t\tfor (i = 0; i < tile_y; i++)\n-\t\t\tval += s->ctb_width * s->row_height[i];\n-\n-\t\tval += (tb_y - s->row_bd[tile_y]) * s->column_width[tile_x] +\n-\t\t       tb_x - s->col_bd[tile_x];\n-\n-\t\ts->ctb_addr_rs_to_ts[ctb_addr_rs] = val;\n-\t\ts->ctb_addr_ts_to_rs[val] = ctb_addr_rs;\n-\t}\n-\n-\tfor (j = 0, tile_id = 0; j < s->num_tile_rows; j++)\n-\t\tfor (i = 0; i < s->num_tile_columns; i++, tile_id++)\n-\t\t\tfor (y = s->row_bd[j]; y < s->row_bd[j + 1]; y++)\n-\t\t\t\tfor (x = s->col_bd[i];\n-\t\t\t\t     x < s->col_bd[i + 1];\n-\t\t\t\t     x++)\n-\t\t\t\t\ts->tile_id[s->ctb_addr_rs_to_ts\n-\t\t\t\t\t\t\t   [y * s->ctb_width +\n-\t\t\t\t\t\t\t    x]] = tile_id;\n+\tfill_rs_to_ts(s);\n \n \treturn 0;\n }\n \n-static int frame_end(struct rpivid_dev *const dev,\n-\t\t     struct rpivid_dec_env *const de,\n-\t\t     const struct rpivid_dec_state *const s)\n-{\n-\tconst unsigned int last_x = s->col_bd[s->num_tile_columns] - 1;\n-\tconst unsigned int last_y = s->row_bd[s->num_tile_rows] - 1;\n-\tsize_t cmd_size;\n-\n-\tif (s->pps.flags & V4L2_HEVC_PPS_FLAG_ENTROPY_CODING_SYNC_ENABLED) {\n-\t\tif (de->wpp_entry_x < 2 && de->pic_width_in_ctbs_y > 2)\n-\t\t\twpp_pause(de, last_y);\n-\t}\n-\tp1_apb_write(de, RPI_STATUS, 1 + (last_x << 5) + (last_y << 18));\n-\n+static int write_cmd_buffer(struct rpivid_dev *const dev,\n+\t\t\t    struct rpivid_dec_env *const de,\n+\t\t\t    const struct rpivid_dec_state *const s)\n+{\n \t// Copy commands out to dma buf\n-\tcmd_size = de->cmd_len * sizeof(de->cmd_fifo[0]);\n+\tconst size_t cmd_size = de->cmd_len * sizeof(de->cmd_fifo[0]);\n \n \tif (!de->cmd_copy_gptr->ptr || cmd_size > de->cmd_copy_gptr->size) {\n \t\tsize_t cmd_alloc = round_up_size(cmd_size);\n@@ -1521,18 +1528,19 @@ static void rpivid_h265_setup(struct rpi\n \tstruct rpivid_q_aux *dpb_q_aux[V4L2_HEVC_DPB_ENTRIES_NUM_MAX];\n \tstruct rpivid_dec_state *const s = ctx->state;\n \tstruct vb2_queue *vq;\n-\tstruct rpivid_dec_env *de;\n-\tint ctb_addr_ts;\n+\tstruct rpivid_dec_env *de = ctx->dec0;\n+\tunsigned int prev_rs;\n \tunsigned int i;\n \tint use_aux;\n \tbool slice_temporal_mvp;\n \n+\txtrace_in(dev, de);\n+\n \tpred_weight_table = &sh->pred_weight_table;\n \n \ts->frame_end =\n \t\t((run->src->flags & V4L2_BUF_FLAG_M2M_HOLD_CAPTURE_BUF) == 0);\n \n-\tde = ctx->dec0;\n \tslice_temporal_mvp = (sh->flags &\n \t\t   V4L2_HEVC_SLICE_PARAMS_FLAG_SLICE_TEMPORAL_MVP_ENABLED);\n \n@@ -1662,6 +1670,13 @@ static void rpivid_h265_setup(struct rpi\n \t\t\t\t  s->sps.pic_height_in_luma_samples);\n \t\t\tgoto fail;\n \t\t}\n+\t\tif ((s->tile_width != 1 || s->tile_height != 1) &&\n+\t\t    (s->pps.flags &\n+\t\t     V4L2_HEVC_PPS_FLAG_ENTROPY_CODING_SYNC_ENABLED)) {\n+\t\t\tv4l2_warn(&dev->v4l2_dev,\n+\t\t\t\t  \"Tiles + WPP not supported\\n\");\n+\t\t\tgoto fail;\n+\t\t}\n \n \t\t// Fill in ref planes with our address s.t. if we mess\n \t\t// up refs somehow then we still have a valid address\n@@ -1760,15 +1775,24 @@ static void rpivid_h265_setup(struct rpi\n \tif (s->sps.flags & V4L2_HEVC_SPS_FLAG_SCALING_LIST_ENABLED)\n \t\tpopulate_scaling_factors(run, de, s);\n \n-\tctb_addr_ts = s->ctb_addr_rs_to_ts[sh->slice_segment_addr];\n+\t// Calc all the random coord info to avoid repeated conversion in/out\n+\ts->start_ts = s->ctb_addr_rs_to_ts[sh->slice_segment_addr];\n+\ts->start_ctb_x = sh->slice_segment_addr % de->pic_width_in_ctbs_y;\n+\ts->start_ctb_y = sh->slice_segment_addr / de->pic_width_in_ctbs_y;\n+\t// Last CTB of previous slice\n+\tprev_rs = !s->start_ts ? 0 : s->ctb_addr_ts_to_rs[s->start_ts - 1];\n+\ts->prev_ctb_x = prev_rs % de->pic_width_in_ctbs_y;\n+\ts->prev_ctb_y = prev_rs / de->pic_width_in_ctbs_y;\n \n \tif ((s->pps.flags & V4L2_HEVC_PPS_FLAG_ENTROPY_CODING_SYNC_ENABLED))\n-\t\twpp_decode_slice(de, s, sh, ctb_addr_ts);\n+\t\twpp_decode_slice(de, s);\n \telse\n-\t\tdecode_slice(de, s, sh, ctb_addr_ts);\n+\t\tdecode_slice(de, s);\n \n-\tif (!s->frame_end)\n+\tif (!s->frame_end) {\n+\t\txtrace_ok(dev, de);\n \t\treturn;\n+\t}\n \n \t// Frame end\n \tmemset(dpb_q_aux, 0,\n@@ -1776,8 +1800,9 @@ static void rpivid_h265_setup(struct rpi\n \t/*\n \t * Need Aux ents for all (ref) DPB ents if temporal MV could\n \t * be enabled for any pic\n-\t * ** At the moment we have aux ents for all pics whether or not\n-\t *    they are ref\n+\t * ** At the moment we create aux ents for all pics whether or not\n+\t *    they are ref - they should then be discarded by the DPB-aux\n+\t *    garbage collection code\n \t */\n \tuse_aux = ((s->sps.flags &\n \t\t  V4L2_HEVC_SPS_FLAG_SPS_TEMPORAL_MVP_ENABLED) != 0);\n@@ -1795,7 +1820,7 @@ static void rpivid_h265_setup(struct rpi\n \t}\n \n \t//        v4l2_info(&dev->v4l2_dev, \"rpivid_h265_end of frame\\n\");\n-\tif (frame_end(dev, de, s))\n+\tif (write_cmd_buffer(dev, de, s))\n \t\tgoto fail;\n \n \tfor (i = 0; i < sh->num_active_dpb_entries; ++i) {\n@@ -1876,6 +1901,7 @@ static void rpivid_h265_setup(struct rpi\n \t}\n \n \tde->state = RPIVID_DECODE_PHASE1;\n+\txtrace_ok(dev, de);\n \treturn;\n \n fail:\n@@ -1883,6 +1909,7 @@ fail:\n \t\t// Actual error reporting happens in Trigger\n \t\tde->state = s->frame_end ? RPIVID_DECODE_ERROR_DONE :\n \t\t\t\t\t   RPIVID_DECODE_ERROR_CONTINUE;\n+\txtrace_fail(dev, de);\n }\n \n //////////////////////////////////////////////////////////////////////////////\n@@ -2210,6 +2237,10 @@ static int rpivid_h265_start(struct rpiv\n \tsize_t pu_alloc;\n \tsize_t coeff_alloc;\n \n+#if DEBUG_TRACE_P1_CMD\n+\tp1_z = 0;\n+#endif\n+\n \t// Generate a sanitised WxH for memory alloc\n \t// Assume HD if unset\n \tif (w == 0)\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0611-media-rpivid-Convert-to-MPLANE.patch",
    "content": "From 84e8138ee002f3d0e643db45b8e27cb792c0c864 Mon Sep 17 00:00:00 2001\nFrom: John Cox <jc@kynesim.co.uk>\nDate: Thu, 11 Mar 2021 12:51:00 +0000\nSubject: [PATCH] media: rpivid: Convert to MPLANE\n\nUse multi-planar interface rather than single plane interface. This\nallows dmabufs holding compressed data to be resized.\n\nSigned-off-by: John Cox <jc@kynesim.co.uk>\n---\n drivers/staging/media/rpivid/rpivid.c       |  2 +-\n drivers/staging/media/rpivid/rpivid.h       |  4 +-\n drivers/staging/media/rpivid/rpivid_h265.c  |  9 ++-\n drivers/staging/media/rpivid/rpivid_video.c | 88 ++++++++++-----------\n drivers/staging/media/rpivid/rpivid_video.h |  4 +-\n 5 files changed, 52 insertions(+), 55 deletions(-)\n\n--- a/drivers/staging/media/rpivid/rpivid.c\n+++ b/drivers/staging/media/rpivid/rpivid.c\n@@ -283,7 +283,7 @@ static const struct video_device rpivid_\n \t.ioctl_ops\t= &rpivid_ioctl_ops,\n \t.minor\t\t= -1,\n \t.release\t= video_device_release_empty,\n-\t.device_caps\t= V4L2_CAP_VIDEO_M2M | V4L2_CAP_STREAMING,\n+\t.device_caps\t= V4L2_CAP_VIDEO_M2M_MPLANE | V4L2_CAP_STREAMING,\n };\n \n static const struct v4l2_m2m_ops rpivid_m2m_ops = {\n--- a/drivers/staging/media/rpivid/rpivid.h\n+++ b/drivers/staging/media/rpivid/rpivid.h\n@@ -85,8 +85,8 @@ struct rpivid_ctx {\n \tstruct v4l2_fh\t\t\tfh;\n \tstruct rpivid_dev\t\t*dev;\n \n-\tstruct v4l2_pix_format\t\tsrc_fmt;\n-\tstruct v4l2_pix_format\t\tdst_fmt;\n+\tstruct v4l2_pix_format_mplane\tsrc_fmt;\n+\tstruct v4l2_pix_format_mplane\tdst_fmt;\n \tint dst_fmt_set;\n \t// fatal_err is set if an error has occurred s.t. decode cannot\n \t// continue (such as running out of CMA)\n--- a/drivers/staging/media/rpivid/rpivid_h265.c\n+++ b/drivers/staging/media/rpivid/rpivid_h265.c\n@@ -1613,7 +1613,7 @@ static void rpivid_h265_setup(struct rpi\n \t\tde->cmd_copy_gptr = ctx->cmdbufs + 0;\n \n \t\tde->frame_c_offset = ctx->dst_fmt.height * 128;\n-\t\tde->frame_stride = ctx->dst_fmt.bytesperline * 128;\n+\t\tde->frame_stride = ctx->dst_fmt.plane_fmt[0].bytesperline * 128;\n \t\tde->frame_addr =\n \t\t\tvb2_dma_contig_plane_dma_addr(&run->dst->vb2_buf, 0);\n \t\tde->frame_aux = NULL;\n@@ -1654,11 +1654,11 @@ static void rpivid_h265_setup(struct rpi\n \t\t\tgoto fail;\n \t\t}\n \t\tif (run->dst->planes[0].length <\n-\t\t    ctx->dst_fmt.sizeimage) {\n+\t\t    ctx->dst_fmt.plane_fmt[0].sizeimage) {\n \t\t\tv4l2_warn(&dev->v4l2_dev,\n \t\t\t\t  \"Capture plane[0] length (%d) < sizeimage (%d)\\n\",\n \t\t\t\t  run->dst->planes[0].length,\n-\t\t\t\t  ctx->dst_fmt.sizeimage);\n+\t\t\t\t  ctx->dst_fmt.plane_fmt[0].sizeimage);\n \t\t\tgoto fail;\n \t\t}\n \n@@ -1812,7 +1812,8 @@ static void rpivid_h265_setup(struct rpi\n \t// slices. If this changes we will need idx mapping code.\n \t// Uses sh so here rather than trigger\n \n-\tvq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);\n+\tvq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx,\n+\t\t\t     V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE);\n \n \tif (!vq) {\n \t\tv4l2_err(&dev->v4l2_dev, \"VQ gone!\\n\");\n--- a/drivers/staging/media/rpivid/rpivid_video.c\n+++ b/drivers/staging/media/rpivid/rpivid_video.c\n@@ -42,25 +42,27 @@ static inline unsigned int constrain2x(u\n \t\t\t(x > y * 2) ? y : x;\n }\n \n-int rpivid_prepare_src_format(struct v4l2_pix_format *pix_fmt)\n+int rpivid_prepare_src_format(struct v4l2_pix_format_mplane *pix_fmt)\n {\n \tif (pix_fmt->pixelformat != V4L2_PIX_FMT_HEVC_SLICE)\n \t\treturn -EINVAL;\n \n \t/* Zero bytes per line for encoded source. */\n-\tpix_fmt->bytesperline = 0;\n+\tpix_fmt->plane_fmt[0].bytesperline = 0;\n \t/* Choose some minimum size since this can't be 0 */\n-\tpix_fmt->sizeimage = max_t(u32, SZ_1K, pix_fmt->sizeimage);\n+\tpix_fmt->plane_fmt[0].sizeimage = max_t(u32, SZ_1K,\n+\t\t\t\t\t\tpix_fmt->plane_fmt[0].sizeimage);\n+\tpix_fmt->num_planes = 1;\n \tpix_fmt->field = V4L2_FIELD_NONE;\n \treturn 0;\n }\n \n-int rpivid_prepare_dst_format(struct v4l2_pix_format *pix_fmt)\n+int rpivid_prepare_dst_format(struct v4l2_pix_format_mplane *pix_fmt)\n {\n \tunsigned int width = pix_fmt->width;\n \tunsigned int height = pix_fmt->height;\n-\tunsigned int sizeimage = pix_fmt->sizeimage;\n-\tunsigned int bytesperline = pix_fmt->bytesperline;\n+\tunsigned int sizeimage = pix_fmt->plane_fmt[0].sizeimage;\n+\tunsigned int bytesperline = pix_fmt->plane_fmt[0].bytesperline;\n \n \tswitch (pix_fmt->pixelformat) {\n \t/* For column formats set bytesperline to column height (stride2) */\n@@ -112,8 +114,9 @@ int rpivid_prepare_dst_format(struct v4l\n \tpix_fmt->height = height;\n \n \tpix_fmt->field = V4L2_FIELD_NONE;\n-\tpix_fmt->bytesperline = bytesperline;\n-\tpix_fmt->sizeimage = sizeimage;\n+\tpix_fmt->plane_fmt[0].bytesperline = bytesperline;\n+\tpix_fmt->plane_fmt[0].sizeimage = sizeimage;\n+\tpix_fmt->num_planes = 1;\n \treturn 0;\n }\n \n@@ -222,12 +225,12 @@ static u32 pixelformat_from_sps(const st\n \treturn pf;\n }\n \n-static struct v4l2_pix_format\n+static struct v4l2_pix_format_mplane\n rpivid_hevc_default_dst_fmt(struct rpivid_ctx * const ctx)\n {\n \tconst struct v4l2_ctrl_hevc_sps * const sps =\n \t\trpivid_find_control_data(ctx, V4L2_CID_MPEG_VIDEO_HEVC_SPS);\n-\tstruct v4l2_pix_format pix_fmt = {\n+\tstruct v4l2_pix_format_mplane pix_fmt = {\n \t\t.width = sps->pic_width_in_luma_samples,\n \t\t.height = sps->pic_height_in_luma_samples,\n \t\t.pixelformat = pixelformat_from_sps(sps, 0)\n@@ -267,7 +270,7 @@ static int rpivid_g_fmt_vid_cap(struct f\n \n \tif (!ctx->dst_fmt_set)\n \t\tctx->dst_fmt = rpivid_hevc_default_dst_fmt(ctx);\n-\tf->fmt.pix = ctx->dst_fmt;\n+\tf->fmt.pix_mp = ctx->dst_fmt;\n \treturn 0;\n }\n \n@@ -276,12 +279,12 @@ static int rpivid_g_fmt_vid_out(struct f\n {\n \tstruct rpivid_ctx *ctx = rpivid_file2ctx(file);\n \n-\tf->fmt.pix = ctx->src_fmt;\n+\tf->fmt.pix_mp = ctx->src_fmt;\n \treturn 0;\n }\n \n-static inline void copy_color(struct v4l2_pix_format *d,\n-\t\t\t      const struct v4l2_pix_format *s)\n+static inline void copy_color(struct v4l2_pix_format_mplane *d,\n+\t\t\t      const struct v4l2_pix_format_mplane *s)\n {\n \td->colorspace   = s->colorspace;\n \td->xfer_func    = s->xfer_func;\n@@ -298,12 +301,8 @@ static int rpivid_try_fmt_vid_cap(struct\n \tu32 pixelformat;\n \tint i;\n \n-\t/* Reject format types we don't support */\n-\tif (f->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)\n-\t\treturn -EINVAL;\n-\n \tfor (i = 0; (pixelformat = pixelformat_from_sps(sps, i)) != 0; i++) {\n-\t\tif (f->fmt.pix.pixelformat == pixelformat)\n+\t\tif (f->fmt.pix_mp.pixelformat == pixelformat)\n \t\t\tbreak;\n \t}\n \n@@ -317,23 +316,20 @@ static int rpivid_try_fmt_vid_cap(struct\n \n \t// We don't have any way of finding out colourspace so believe\n \t// anything we are told - take anything set in src as a default\n-\tif (f->fmt.pix.colorspace == V4L2_COLORSPACE_DEFAULT)\n-\t\tcopy_color(&f->fmt.pix, &ctx->src_fmt);\n+\tif (f->fmt.pix_mp.colorspace == V4L2_COLORSPACE_DEFAULT)\n+\t\tcopy_color(&f->fmt.pix_mp, &ctx->src_fmt);\n \n-\tf->fmt.pix.pixelformat = pixelformat;\n-\treturn rpivid_prepare_dst_format(&f->fmt.pix);\n+\tf->fmt.pix_mp.pixelformat = pixelformat;\n+\treturn rpivid_prepare_dst_format(&f->fmt.pix_mp);\n }\n \n static int rpivid_try_fmt_vid_out(struct file *file, void *priv,\n \t\t\t\t  struct v4l2_format *f)\n {\n-\tif (f->type != V4L2_BUF_TYPE_VIDEO_OUTPUT)\n-\t\treturn -EINVAL;\n-\n-\tif (rpivid_prepare_src_format(&f->fmt.pix)) {\n+\tif (rpivid_prepare_src_format(&f->fmt.pix_mp)) {\n \t\t// Set default src format\n-\t\tf->fmt.pix.pixelformat = RPIVID_SRC_PIXELFORMAT_DEFAULT;\n-\t\trpivid_prepare_src_format(&f->fmt.pix);\n+\t\tf->fmt.pix_mp.pixelformat = RPIVID_SRC_PIXELFORMAT_DEFAULT;\n+\t\trpivid_prepare_src_format(&f->fmt.pix_mp);\n \t}\n \treturn 0;\n }\n@@ -353,7 +349,7 @@ static int rpivid_s_fmt_vid_cap(struct f\n \tif (ret)\n \t\treturn ret;\n \n-\tctx->dst_fmt = f->fmt.pix;\n+\tctx->dst_fmt = f->fmt.pix_mp;\n \tctx->dst_fmt_set = 1;\n \n \treturn 0;\n@@ -374,14 +370,14 @@ static int rpivid_s_fmt_vid_out(struct f\n \tif (ret)\n \t\treturn ret;\n \n-\tctx->src_fmt = f->fmt.pix;\n+\tctx->src_fmt = f->fmt.pix_mp;\n \tctx->dst_fmt_set = 0;  // Setting src invalidates dst\n \n \tvq->subsystem_flags |=\n \t\tVB2_V4L2_FL_SUPPORTS_M2M_HOLD_CAPTURE_BUF;\n \n \t/* Propagate colorspace information to capture. */\n-\tcopy_color(&ctx->dst_fmt, &f->fmt.pix);\n+\tcopy_color(&ctx->dst_fmt, &f->fmt.pix_mp);\n \treturn 0;\n }\n \n@@ -389,14 +385,14 @@ const struct v4l2_ioctl_ops rpivid_ioctl\n \t.vidioc_querycap\t\t= rpivid_querycap,\n \n \t.vidioc_enum_fmt_vid_cap\t= rpivid_enum_fmt_vid_cap,\n-\t.vidioc_g_fmt_vid_cap\t\t= rpivid_g_fmt_vid_cap,\n-\t.vidioc_try_fmt_vid_cap\t\t= rpivid_try_fmt_vid_cap,\n-\t.vidioc_s_fmt_vid_cap\t\t= rpivid_s_fmt_vid_cap,\n+\t.vidioc_g_fmt_vid_cap_mplane\t= rpivid_g_fmt_vid_cap,\n+\t.vidioc_try_fmt_vid_cap_mplane\t= rpivid_try_fmt_vid_cap,\n+\t.vidioc_s_fmt_vid_cap_mplane\t= rpivid_s_fmt_vid_cap,\n \n \t.vidioc_enum_fmt_vid_out\t= rpivid_enum_fmt_vid_out,\n-\t.vidioc_g_fmt_vid_out\t\t= rpivid_g_fmt_vid_out,\n-\t.vidioc_try_fmt_vid_out\t\t= rpivid_try_fmt_vid_out,\n-\t.vidioc_s_fmt_vid_out\t\t= rpivid_s_fmt_vid_out,\n+\t.vidioc_g_fmt_vid_out_mplane\t= rpivid_g_fmt_vid_out,\n+\t.vidioc_try_fmt_vid_out_mplane\t= rpivid_try_fmt_vid_out,\n+\t.vidioc_s_fmt_vid_out_mplane\t= rpivid_s_fmt_vid_out,\n \n \t.vidioc_reqbufs\t\t\t= v4l2_m2m_ioctl_reqbufs,\n \t.vidioc_querybuf\t\t= v4l2_m2m_ioctl_querybuf,\n@@ -421,7 +417,7 @@ static int rpivid_queue_setup(struct vb2\n \t\t\t      struct device *alloc_devs[])\n {\n \tstruct rpivid_ctx *ctx = vb2_get_drv_priv(vq);\n-\tstruct v4l2_pix_format *pix_fmt;\n+\tstruct v4l2_pix_format_mplane *pix_fmt;\n \n \tif (V4L2_TYPE_IS_OUTPUT(vq->type))\n \t\tpix_fmt = &ctx->src_fmt;\n@@ -429,10 +425,10 @@ static int rpivid_queue_setup(struct vb2\n \t\tpix_fmt = &ctx->dst_fmt;\n \n \tif (*nplanes) {\n-\t\tif (sizes[0] < pix_fmt->sizeimage)\n+\t\tif (sizes[0] < pix_fmt->plane_fmt[0].sizeimage)\n \t\t\treturn -EINVAL;\n \t} else {\n-\t\tsizes[0] = pix_fmt->sizeimage;\n+\t\tsizes[0] = pix_fmt->plane_fmt[0].sizeimage;\n \t\t*nplanes = 1;\n \t}\n \n@@ -471,17 +467,17 @@ static int rpivid_buf_prepare(struct vb2\n {\n \tstruct vb2_queue *vq = vb->vb2_queue;\n \tstruct rpivid_ctx *ctx = vb2_get_drv_priv(vq);\n-\tstruct v4l2_pix_format *pix_fmt;\n+\tstruct v4l2_pix_format_mplane *pix_fmt;\n \n \tif (V4L2_TYPE_IS_OUTPUT(vq->type))\n \t\tpix_fmt = &ctx->src_fmt;\n \telse\n \t\tpix_fmt = &ctx->dst_fmt;\n \n-\tif (vb2_plane_size(vb, 0) < pix_fmt->sizeimage)\n+\tif (vb2_plane_size(vb, 0) < pix_fmt->plane_fmt[0].sizeimage)\n \t\treturn -EINVAL;\n \n-\tvb2_set_plane_payload(vb, 0, pix_fmt->sizeimage);\n+\tvb2_set_plane_payload(vb, 0, pix_fmt->plane_fmt[0].sizeimage);\n \n \treturn 0;\n }\n@@ -567,7 +563,7 @@ int rpivid_queue_init(void *priv, struct\n \tstruct rpivid_ctx *ctx = priv;\n \tint ret;\n \n-\tsrc_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT;\n+\tsrc_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;\n \tsrc_vq->io_modes = VB2_MMAP | VB2_DMABUF;\n \tsrc_vq->drv_priv = ctx;\n \tsrc_vq->buf_struct_size = sizeof(struct rpivid_buffer);\n@@ -584,7 +580,7 @@ int rpivid_queue_init(void *priv, struct\n \tif (ret)\n \t\treturn ret;\n \n-\tdst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;\n+\tdst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;\n \tdst_vq->io_modes = VB2_MMAP | VB2_DMABUF;\n \tdst_vq->drv_priv = ctx;\n \tdst_vq->buf_struct_size = sizeof(struct rpivid_buffer);\n--- a/drivers/staging/media/rpivid/rpivid_video.h\n+++ b/drivers/staging/media/rpivid/rpivid_video.h\n@@ -24,7 +24,7 @@ extern const struct v4l2_ioctl_ops rpivi\n \n int rpivid_queue_init(void *priv, struct vb2_queue *src_vq,\n \t\t      struct vb2_queue *dst_vq);\n-int rpivid_prepare_src_format(struct v4l2_pix_format *pix_fmt);\n-int rpivid_prepare_dst_format(struct v4l2_pix_format *pix_fmt);\n+int rpivid_prepare_src_format(struct v4l2_pix_format_mplane *pix_fmt);\n+int rpivid_prepare_dst_format(struct v4l2_pix_format_mplane *pix_fmt);\n \n #endif\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0612-media-rpivid-Add-an-enable-count-to-irq-claim-Qs.patch",
    "content": "From 8b6aa431b277cc3c49c0c8be2b49b395d29325cf Mon Sep 17 00:00:00 2001\nFrom: John Cox <jc@kynesim.co.uk>\nDate: Thu, 11 Mar 2021 18:43:15 +0000\nSubject: [PATCH] media: rpivid: Add an enable count to irq claim Qs\n\nAdd an enable count to the irq Q structures to allow the irq logic to\nblock further callbacks if resources associated with the irq are not\nyet available.\n\nSigned-off-by: John Cox <jc@kynesim.co.uk>\n---\n drivers/staging/media/rpivid/rpivid.h    |   2 +\n drivers/staging/media/rpivid/rpivid_hw.c | 118 +++++++++++++++--------\n drivers/staging/media/rpivid/rpivid_hw.h |   3 +\n 3 files changed, 85 insertions(+), 38 deletions(-)\n\n--- a/drivers/staging/media/rpivid/rpivid.h\n+++ b/drivers/staging/media/rpivid/rpivid.h\n@@ -151,6 +151,8 @@ struct rpivid_hw_irq_ctrl {\n \tstruct rpivid_hw_irq_ent *irq;\n \t/* Non-zero => do not start a new job - outer layer sched pending */\n \tint no_sched;\n+\t/* Enable count. -1 always OK, 0 do not sched, +ve shed & count down */\n+\tint enable;\n \t/* Thread CB requested */\n \tbool thread_reqed;\n };\n--- a/drivers/staging/media/rpivid/rpivid_hw.c\n+++ b/drivers/staging/media/rpivid/rpivid_hw.c\n@@ -42,35 +42,62 @@ static void pre_irq(struct rpivid_dev *d\n \tient->cb = cb;\n \tient->v = v;\n \n-\t// Not sure this lock is actually required\n \tspin_lock_irqsave(&ictl->lock, flags);\n \tictl->irq = ient;\n+\tictl->no_sched++;\n \tspin_unlock_irqrestore(&ictl->lock, flags);\n }\n \n-static void sched_claim(struct rpivid_dev * const dev,\n-\t\t\tstruct rpivid_hw_irq_ctrl * const ictl)\n+/* Should be called from inside ictl->lock */\n+static inline bool sched_enabled(const struct rpivid_hw_irq_ctrl * const ictl)\n {\n-\tfor (;;) {\n-\t\tstruct rpivid_hw_irq_ent *ient = NULL;\n-\t\tunsigned long flags;\n+\treturn ictl->no_sched <= 0 && ictl->enable;\n+}\n \n-\t\tspin_lock_irqsave(&ictl->lock, flags);\n+/* Should be called from inside ictl->lock & after checking sched_enabled() */\n+static inline void set_claimed(struct rpivid_hw_irq_ctrl * const ictl)\n+{\n+\tif (ictl->enable > 0)\n+\t\t--ictl->enable;\n+\tictl->no_sched = 1;\n+}\n \n-\t\tif (--ictl->no_sched <= 0) {\n-\t\t\tient = ictl->claim;\n-\t\t\tif (!ictl->irq && ient) {\n-\t\t\t\tictl->claim = ient->next;\n-\t\t\t\tictl->no_sched = 1;\n-\t\t\t}\n-\t\t}\n+/* Should be called from inside ictl->lock */\n+static struct rpivid_hw_irq_ent *get_sched(struct rpivid_hw_irq_ctrl * const ictl)\n+{\n+\tstruct rpivid_hw_irq_ent *ient;\n \n-\t\tspin_unlock_irqrestore(&ictl->lock, flags);\n+\tif (!sched_enabled(ictl))\n+\t\treturn NULL;\n+\n+\tient = ictl->claim;\n+\tif (!ient)\n+\t\treturn NULL;\n+\tictl->claim = ient->next;\n+\n+\tset_claimed(ictl);\n+\treturn ient;\n+}\n \n-\t\tif (!ient)\n-\t\t\tbreak;\n+/* Run a callback & check to see if there is anything else to run */\n+static void sched_cb(struct rpivid_dev * const dev,\n+\t\t     struct rpivid_hw_irq_ctrl * const ictl,\n+\t\t     struct rpivid_hw_irq_ent *ient)\n+{\n+\twhile (ient) {\n+\t\tunsigned long flags;\n \n \t\tient->cb(dev, ient->v);\n+\n+\t\tspin_lock_irqsave(&ictl->lock, flags);\n+\n+\t\t/* Always dec no_sched after cb exec - must have been set\n+\t\t * on entry to cb\n+\t\t */\n+\t\t--ictl->no_sched;\n+\t\tient = get_sched(ictl);\n+\n+\t\tspin_unlock_irqrestore(&ictl->lock, flags);\n \t}\n }\n \n@@ -84,7 +111,7 @@ static void pre_thread(struct rpivid_dev\n \tient->v = v;\n \tictl->irq = ient;\n \tictl->thread_reqed = true;\n-\tictl->no_sched++;\n+\tictl->no_sched++;\t/* This is unwound in do_thread */\n }\n \n // Called in irq context\n@@ -96,17 +123,10 @@ static void do_irq(struct rpivid_dev * c\n \n \tspin_lock_irqsave(&ictl->lock, flags);\n \tient = ictl->irq;\n-\tif (ient) {\n-\t\tictl->no_sched++;\n-\t\tictl->irq = NULL;\n-\t}\n+\tictl->irq = NULL;\n \tspin_unlock_irqrestore(&ictl->lock, flags);\n \n-\tif (ient) {\n-\t\tient->cb(dev, ient->v);\n-\n-\t\tsched_claim(dev, ictl);\n-\t}\n+\tsched_cb(dev, ictl, ient);\n }\n \n static void do_claim(struct rpivid_dev * const dev,\n@@ -127,7 +147,7 @@ static void do_claim(struct rpivid_dev *\n \t\tictl->tail->next = ient;\n \t\tictl->tail = ient;\n \t\tient = NULL;\n-\t} else if (ictl->no_sched || ictl->irq) {\n+\t} else if (!sched_enabled(ictl)) {\n \t\t// Empty Q but other activity in progress so Q\n \t\tictl->claim = ient;\n \t\tictl->tail = ient;\n@@ -135,16 +155,34 @@ static void do_claim(struct rpivid_dev *\n \t} else {\n \t\t// Nothing else going on - schedule immediately and\n \t\t// prevent anything else scheduling claims\n-\t\tictl->no_sched = 1;\n+\t\tset_claimed(ictl);\n \t}\n \n \tspin_unlock_irqrestore(&ictl->lock, flags);\n \n-\tif (ient) {\n-\t\tient->cb(dev, ient->v);\n+\tsched_cb(dev, ictl, ient);\n+}\n \n-\t\tsched_claim(dev, ictl);\n-\t}\n+/* Enable n claims.\n+ * n < 0   set to unlimited (default on init)\n+ * n = 0   if previously unlimited then disable otherwise nop\n+ * n > 0   if previously unlimited then set to n enables\n+ *         otherwise add n enables\n+ * The enable count is automatically decremented every time a claim is run\n+ */\n+static void do_enable_claim(struct rpivid_dev * const dev,\n+\t\t\t    int n,\n+\t\t\t    struct rpivid_hw_irq_ctrl * const ictl)\n+{\n+\tunsigned long flags;\n+\tstruct rpivid_hw_irq_ent *ient;\n+\n+\tspin_lock_irqsave(&ictl->lock, flags);\n+\tictl->enable = n < 0 ? -1 : ictl->enable <= 0 ? n : ictl->enable + n;\n+\tient = get_sched(ictl);\n+\tspin_unlock_irqrestore(&ictl->lock, flags);\n+\n+\tsched_cb(dev, ictl, ient);\n }\n \n static void ictl_init(struct rpivid_hw_irq_ctrl * const ictl)\n@@ -154,6 +192,8 @@ static void ictl_init(struct rpivid_hw_i\n \tictl->tail = NULL;\n \tictl->irq = NULL;\n \tictl->no_sched = 0;\n+\tictl->enable = -1;\n+\tictl->thread_reqed = false;\n }\n \n static void ictl_uninit(struct rpivid_hw_irq_ctrl * const ictl)\n@@ -203,11 +243,7 @@ static void do_thread(struct rpivid_dev\n \n \tspin_unlock_irqrestore(&ictl->lock, flags);\n \n-\tif (ient) {\n-\t\tient->cb(dev, ient->v);\n-\n-\t\tsched_claim(dev, ictl);\n-\t}\n+\tsched_cb(dev, ictl, ient);\n }\n \n static irqreturn_t rpivid_irq_thread(int irq, void *data)\n@@ -231,6 +267,12 @@ void rpivid_hw_irq_active1_thread(struct\n \tpre_thread(dev, ient, thread_cb, ctx, &dev->ic_active1);\n }\n \n+void rpivid_hw_irq_active1_enable_claim(struct rpivid_dev *dev,\n+\t\t\t\t\tint n)\n+{\n+\tdo_enable_claim(dev, n, &dev->ic_active1);\n+}\n+\n void rpivid_hw_irq_active1_claim(struct rpivid_dev *dev,\n \t\t\t\t struct rpivid_hw_irq_ent *ient,\n \t\t\t\t rpivid_irq_callback ready_cb, void *ctx)\n--- a/drivers/staging/media/rpivid/rpivid_hw.h\n+++ b/drivers/staging/media/rpivid/rpivid_hw.h\n@@ -272,6 +272,9 @@ static inline void apb_write_vc_len(cons\n \t\tARG_IC_ICTRL_ACTIVE1_INT_SET    |\\\n \t\tARG_IC_ICTRL_ACTIVE2_INT_SET)\n \n+/* Regulate claim Q */\n+void rpivid_hw_irq_active1_enable_claim(struct rpivid_dev *dev,\n+\t\t\t\t\tint n);\n /* Auto release once all CBs called */\n void rpivid_hw_irq_active1_claim(struct rpivid_dev *dev,\n \t\t\t\t struct rpivid_hw_irq_ent *ient,\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0613-RFC-media-Add-media_request_-pin-unpin-API.patch",
    "content": "From 739b9c6a80058d1aaeb66fdfe2910662f7f411ad Mon Sep 17 00:00:00 2001\nFrom: Ezequiel Garcia <ezequiel@collabora.com>\nDate: Sun, 21 Mar 2021 16:38:54 -0300\nSubject: [PATCH] RFC: media: Add media_request_{pin,unpin} API\n\nThis is probably not the API we will want to add, but it\nshould show what semantics are needed by drivers.\n\nThe goal is to allow the OUTPUT (aka source) buffer and the\ncontrols associated to a request to be released from the request,\nand in particular return the OUTPUT buffer back to userspace,\nwithout signalling the media request fd.\n\nThis is useful for devices that are able to pre-process\nthe OUTPUT buffer, therefore able to release it before\nthe decoding is finished. These drivers should signal\nthe media request fd only after the CAPTURE buffer is done.\n\nTested-by: John Cox <jc@kynesim.co.uk>\nSigned-off-by: Ezequiel Garcia <ezequiel@collabora.com>\n---\n drivers/media/mc/mc-request.c | 35 +++++++++++++++++++++++++++++++++++\n include/media/media-request.h | 12 ++++++++++++\n 2 files changed, 47 insertions(+)\n\n--- a/drivers/media/mc/mc-request.c\n+++ b/drivers/media/mc/mc-request.c\n@@ -504,3 +504,38 @@ unlock:\n \t\tmedia_request_put(req);\n }\n EXPORT_SYMBOL_GPL(media_request_object_complete);\n+\n+void media_request_pin(struct media_request *req)\n+{\n+\tunsigned long flags;\n+\n+\tspin_lock_irqsave(&req->lock, flags);\n+\tif (WARN_ON(req->state != MEDIA_REQUEST_STATE_QUEUED))\n+\t\tgoto unlock;\n+\treq->num_incomplete_objects++;\n+unlock:\n+\tspin_unlock_irqrestore(&req->lock, flags);\n+}\n+EXPORT_SYMBOL_GPL(media_request_pin);\n+\n+void media_request_unpin(struct media_request *req)\n+{\n+\tunsigned long flags;\n+\tbool completed = false;\n+\n+\tspin_lock_irqsave(&req->lock, flags);\n+\tif (WARN_ON(!req->num_incomplete_objects) ||\n+\t    WARN_ON(req->state != MEDIA_REQUEST_STATE_QUEUED))\n+\t\tgoto unlock;\n+\n+\tif (!--req->num_incomplete_objects) {\n+\t\treq->state = MEDIA_REQUEST_STATE_COMPLETE;\n+\t\twake_up_interruptible_all(&req->poll_wait);\n+\t\tcompleted = true;\n+\t}\n+unlock:\n+\tspin_unlock_irqrestore(&req->lock, flags);\n+\tif (completed)\n+\t\tmedia_request_put(req);\n+}\n+EXPORT_SYMBOL_GPL(media_request_unpin);\n--- a/include/media/media-request.h\n+++ b/include/media/media-request.h\n@@ -189,6 +189,10 @@ static inline void media_request_get(str\n  */\n void media_request_put(struct media_request *req);\n \n+void media_request_pin(struct media_request *req);\n+\n+void media_request_unpin(struct media_request *req);\n+\n /**\n  * media_request_get_by_fd - Get a media request by fd\n  *\n@@ -228,6 +232,14 @@ static inline void media_request_put(str\n {\n }\n \n+static inline void media_request_pin(struct media_request *req)\n+{\n+}\n+\n+static inline void media_request_unpin(struct media_request *req)\n+{\n+}\n+\n static inline struct media_request *\n media_request_get_by_fd(struct media_device *mdev, int request_fd)\n {\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0614-media-rpivid-Add-a-Pass0-to-accumulate-slices-and-re.patch",
    "content": "From a1902958d144d55309a1074f74fc9b3494d3042f Mon Sep 17 00:00:00 2001\nFrom: John Cox <jc@kynesim.co.uk>\nDate: Thu, 11 Mar 2021 19:08:00 +0000\nSubject: [PATCH] media: rpivid: Add a Pass0 to accumulate slices and\n rework job finish\n\nDue to overheads in assembling controls and requests it is worth having\nthe slice assembly phase separate from the h/w pass1 processing. Create\na queue to service pass1 rather than have the pass1 finished callback\ntrigger the next slice job.\n\nThis requires a rework of the logic that splits up the buffer and\nrequest done events. This code contains two ways of doing that, we use\nEzequiel Garcias <ezequiel@collabora.com> solution, but expect that\nin the future this will be handled by the framework in a cleaner manner.\n\nFix up the handling of some of the memory exhaustion crashes uncovered\nin the process of writing this code.\n\nSigned-off-by: John Cox <jc@kynesim.co.uk>\n---\n drivers/media/v4l2-core/v4l2-mem2mem.c     |   2 -\n drivers/staging/media/rpivid/rpivid.c      |  11 +-\n drivers/staging/media/rpivid/rpivid.h      |  20 +-\n drivers/staging/media/rpivid/rpivid_dec.c  |  32 +-\n drivers/staging/media/rpivid/rpivid_h265.c | 432 ++++++++++++++++-----\n drivers/staging/media/rpivid/rpivid_hw.c   |   8 +-\n 6 files changed, 374 insertions(+), 131 deletions(-)\n\n--- a/drivers/media/v4l2-core/v4l2-mem2mem.c\n+++ b/drivers/media/v4l2-core/v4l2-mem2mem.c\n@@ -492,8 +492,6 @@ void v4l2_m2m_job_finish(struct v4l2_m2m\n \t * holding capture buffers. Those should use\n \t * v4l2_m2m_buf_done_and_job_finish() instead.\n \t */\n-\tWARN_ON(m2m_ctx->out_q_ctx.q.subsystem_flags &\n-\t\tVB2_V4L2_FL_SUPPORTS_M2M_HOLD_CAPTURE_BUF);\n \tspin_lock_irqsave(&m2m_dev->job_spinlock, flags);\n \tschedule_next = _v4l2_m2m_job_finish(m2m_dev, m2m_ctx);\n \tspin_unlock_irqrestore(&m2m_dev->job_spinlock, flags);\n--- a/drivers/staging/media/rpivid/rpivid.c\n+++ b/drivers/staging/media/rpivid/rpivid.c\n@@ -79,17 +79,24 @@ static const struct rpivid_control rpivi\n \n #define rpivid_ctrls_COUNT\tARRAY_SIZE(rpivid_ctrls)\n \n-void *rpivid_find_control_data(struct rpivid_ctx *ctx, u32 id)\n+struct v4l2_ctrl *rpivid_find_ctrl(struct rpivid_ctx *ctx, u32 id)\n {\n \tunsigned int i;\n \n \tfor (i = 0; ctx->ctrls[i]; i++)\n \t\tif (ctx->ctrls[i]->id == id)\n-\t\t\treturn ctx->ctrls[i]->p_cur.p;\n+\t\t\treturn ctx->ctrls[i];\n \n \treturn NULL;\n }\n \n+void *rpivid_find_control_data(struct rpivid_ctx *ctx, u32 id)\n+{\n+\tstruct v4l2_ctrl *const ctrl = rpivid_find_ctrl(ctx, id);\n+\n+\treturn !ctrl ? NULL : ctrl->p_cur.p;\n+}\n+\n static int rpivid_init_ctrls(struct rpivid_dev *dev, struct rpivid_ctx *ctx)\n {\n \tstruct v4l2_ctrl_handler *hdl = &ctx->hdl;\n--- a/drivers/staging/media/rpivid/rpivid.h\n+++ b/drivers/staging/media/rpivid/rpivid.h\n@@ -24,6 +24,10 @@\n \n #define OPT_DEBUG_POLL_IRQ  0\n \n+#define RPIVID_DEC_ENV_COUNT 6\n+#define RPIVID_P1BUF_COUNT 3\n+#define RPIVID_P2BUF_COUNT 3\n+\n #define RPIVID_NAME\t\t\t\"rpivid\"\n \n #define RPIVID_CAPABILITY_UNTILED\tBIT(0)\n@@ -45,6 +49,7 @@ struct rpivid_control {\n };\n \n struct rpivid_h265_run {\n+\tu32 slice_ents;\n \tconst struct v4l2_ctrl_hevc_sps\t\t\t*sps;\n \tconst struct v4l2_ctrl_hevc_pps\t\t\t*pps;\n \tconst struct v4l2_ctrl_hevc_slice_params\t*slice_params;\n@@ -64,7 +69,6 @@ struct rpivid_buffer {\n \n struct rpivid_dec_state;\n struct rpivid_dec_env;\n-#define RPIVID_DEC_ENV_COUNT 3\n \n struct rpivid_gptr {\n \tsize_t size;\n@@ -79,7 +83,6 @@ typedef void (*rpivid_irq_callback)(stru\n struct rpivid_q_aux;\n #define RPIVID_AUX_ENT_COUNT VB2_MAX_FRAME\n \n-#define RPIVID_P2BUF_COUNT 2\n \n struct rpivid_ctx {\n \tstruct v4l2_fh\t\t\tfh;\n@@ -108,11 +111,13 @@ struct rpivid_ctx {\n \n \tstruct rpivid_dec_env *dec_pool;\n \n-\t/* Some of these should be in dev */\n-\tstruct rpivid_gptr bitbufs[1];  /* Will be 2 */\n-\tstruct rpivid_gptr cmdbufs[1];  /* Will be 2 */\n+\tunsigned int p1idx;\n+\tatomic_t p1out;\n+\tstruct rpivid_gptr bitbufs[RPIVID_P1BUF_COUNT];\n+\tstruct rpivid_gptr cmdbufs[RPIVID_P1BUF_COUNT];\n+\n+\t/* *** Should be in dev *** */\n \tunsigned int p2idx;\n-\tatomic_t p2out;\n \tstruct rpivid_gptr pu_bufs[RPIVID_P2BUF_COUNT];\n \tstruct rpivid_gptr coeff_bufs[RPIVID_P2BUF_COUNT];\n \n@@ -141,6 +146,8 @@ struct rpivid_variant {\n \n struct rpivid_hw_irq_ent;\n \n+#define RPIVID_ICTL_ENABLE_UNLIMITED (-1)\n+\n struct rpivid_hw_irq_ctrl {\n \t/* Spinlock protecting claim and tail */\n \tspinlock_t lock;\n@@ -182,6 +189,7 @@ struct rpivid_dev {\n \n extern struct rpivid_dec_ops rpivid_dec_ops_h265;\n \n+struct v4l2_ctrl *rpivid_find_ctrl(struct rpivid_ctx *ctx, u32 id);\n void *rpivid_find_control_data(struct rpivid_ctx *ctx, u32 id);\n \n #endif\n--- a/drivers/staging/media/rpivid/rpivid_dec.c\n+++ b/drivers/staging/media/rpivid/rpivid_dec.c\n@@ -21,8 +21,8 @@\n \n void rpivid_device_run(void *priv)\n {\n-\tstruct rpivid_ctx *ctx = priv;\n-\tstruct rpivid_dev *dev = ctx->dev;\n+\tstruct rpivid_ctx *const ctx = priv;\n+\tstruct rpivid_dev *const dev = ctx->dev;\n \tstruct rpivid_run run = {};\n \tstruct media_request *src_req;\n \n@@ -32,19 +32,17 @@ void rpivid_device_run(void *priv)\n \tif (!run.src || !run.dst) {\n \t\tv4l2_err(&dev->v4l2_dev, \"%s: Missing buffer: src=%p, dst=%p\\n\",\n \t\t\t __func__, run.src, run.dst);\n-\t\t/* We are stuffed - this probably won't dig us out of our\n-\t\t * current situation but it is better than nothing\n-\t\t */\n-\t\tv4l2_m2m_buf_done_and_job_finish(dev->m2m_dev, ctx->fh.m2m_ctx,\n-\t\t\t\t\t\t VB2_BUF_STATE_ERROR);\n-\t\treturn;\n+\t\tgoto fail;\n \t}\n \n-\t/* Apply request(s) controls if needed. */\n+\t/* Apply request(s) controls */\n \tsrc_req = run.src->vb2_buf.req_obj.req;\n+\tif (!src_req) {\n+\t\tv4l2_err(&dev->v4l2_dev, \"%s: Missing request\\n\", __func__);\n+\t\tgoto fail;\n+\t}\n \n-\tif (src_req)\n-\t\tv4l2_ctrl_request_setup(src_req, &ctx->hdl);\n+\tv4l2_ctrl_request_setup(src_req, &ctx->hdl);\n \n \tswitch (ctx->src_fmt.pixelformat) {\n \tcase V4L2_PIX_FMT_HEVC_SLICE:\n@@ -70,10 +68,14 @@ void rpivid_device_run(void *priv)\n \n \tdev->dec_ops->setup(ctx, &run);\n \n-\t/* Complete request(s) controls if needed. */\n-\n-\tif (src_req)\n-\t\tv4l2_ctrl_request_complete(src_req, &ctx->hdl);\n+\t/* Complete request(s) controls */\n+\tv4l2_ctrl_request_complete(src_req, &ctx->hdl);\n \n \tdev->dec_ops->trigger(ctx);\n+\treturn;\n+\n+fail:\n+\t/* We really shouldn't get here but tidy up what we can */\n+\tv4l2_m2m_buf_done_and_job_finish(dev->m2m_dev, ctx->fh.m2m_ctx,\n+\t\t\t\t\t VB2_BUF_STATE_ERROR);\n }\n--- a/drivers/staging/media/rpivid/rpivid_h265.c\n+++ b/drivers/staging/media/rpivid/rpivid_h265.c\n@@ -22,6 +22,8 @@\n #define DEBUG_TRACE_P1_CMD 0\n #define DEBUG_TRACE_EXECUTION 0\n \n+#define USE_REQUEST_PIN 1\n+\n #if DEBUG_TRACE_EXECUTION\n #define xtrace_in(dev_, de_)\\\n \tv4l2_info(&(dev_)->v4l2_dev, \"%s[%d]: in\\n\",   __func__,\\\n@@ -192,8 +194,6 @@ struct rpivid_dec_env {\n \tunsigned int decode_order;\n \tint p1_status;\t\t/* P1 status - what to realloc */\n \n-\tstruct rpivid_dec_env *phase_wait_q_next;\n-\n \tstruct rpi_cmd *cmd_fifo;\n \tunsigned int cmd_len, cmd_max;\n \tunsigned int num_slice_msgs;\n@@ -219,6 +219,7 @@ struct rpivid_dec_env {\n \tu32 rpi_currpoc;\n \n \tstruct vb2_v4l2_buffer *frame_buf; // Detached dest buffer\n+\tstruct vb2_v4l2_buffer *src_buf;   // Detached src buffer\n \tunsigned int frame_c_offset;\n \tunsigned int frame_stride;\n \tdma_addr_t frame_addr;\n@@ -235,9 +236,15 @@ struct rpivid_dec_env {\n \tsize_t bit_copy_len;\n \tstruct rpivid_gptr *cmd_copy_gptr;\n \n-\tu16 slice_msgs[2 * HEVC_MAX_REFS * 8 + 3];\n+#define SLICE_MSGS_MAX (2 * HEVC_MAX_REFS * 8 + 3)\n+\tu16 slice_msgs[SLICE_MSGS_MAX];\n \tu8 scaling_factors[NUM_SCALING_FACTORS];\n \n+#if USE_REQUEST_PIN\n+\tstruct media_request *req_pin;\n+#else\n+\tstruct media_request_object *req_obj;\n+#endif\n \tstruct rpivid_hw_irq_ent irq_ent;\n };\n \n@@ -286,6 +293,17 @@ struct rpivid_dec_state {\n \tunsigned int prev_ctb_y;\n };\n \n+#if !USE_REQUEST_PIN\n+static void dst_req_obj_release(struct media_request_object *object)\n+{\n+\tkfree(object);\n+}\n+\n+static const struct media_request_object_ops dst_req_obj_ops = {\n+\t.release = dst_req_obj_release,\n+};\n+#endif\n+\n static inline int clip_int(const int x, const int lo, const int hi)\n {\n \treturn x < lo ? lo : x > hi ? hi : x;\n@@ -298,15 +316,48 @@ static inline int clip_int(const int x,\n static int p1_z;\n #endif\n \n+static int cmds_check_space(struct rpivid_dec_env *const de, unsigned int n)\n+{\n+\tstruct rpi_cmd *a;\n+\tunsigned int newmax;\n+\n+\tif (n > 0x100000) {\n+\t\tv4l2_err(&de->ctx->dev->v4l2_dev,\n+\t\t\t \"%s: n %u implausible\\n\", __func__, n);\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\tif (de->cmd_len + n <= de->cmd_max)\n+\t\treturn 0;\n+\n+\tnewmax = 2 << log2_size(de->cmd_len + n);\n+\n+\ta = krealloc(de->cmd_fifo, newmax * sizeof(struct rpi_cmd),\n+\t\t     GFP_KERNEL);\n+\tif (!a) {\n+\t\tv4l2_err(&de->ctx->dev->v4l2_dev,\n+\t\t\t \"Failed cmd buffer realloc from %u to %u\\n\",\n+\t\t\t de->cmd_max, newmax);\n+\t\treturn -ENOMEM;\n+\t}\n+\tv4l2_info(&de->ctx->dev->v4l2_dev,\n+\t\t  \"cmd buffer realloc from %u to %u\\n\", de->cmd_max, newmax);\n+\n+\tde->cmd_fifo = a;\n+\tde->cmd_max = newmax;\n+\treturn 0;\n+}\n+\n // ???? u16 addr - put in u32\n-static int p1_apb_write(struct rpivid_dec_env *const de, const u16 addr,\n-\t\t\tconst u32 data)\n+static void p1_apb_write(struct rpivid_dec_env *const de, const u16 addr,\n+\t\t\t const u32 data)\n {\n-\tif (de->cmd_len == de->cmd_max)\n-\t\tde->cmd_fifo =\n-\t\t\tkrealloc(de->cmd_fifo,\n-\t\t\t\t (de->cmd_max *= 2) * sizeof(struct rpi_cmd),\n-\t\t\t\t GFP_KERNEL);\n+\tif (de->cmd_len >= de->cmd_max) {\n+\t\tv4l2_err(&de->ctx->dev->v4l2_dev,\n+\t\t\t \"%s: Overflow @ %d\\n\", __func__, de->cmd_len);\n+\t\treturn;\n+\t}\n+\n \tde->cmd_fifo[de->cmd_len].addr = addr;\n \tde->cmd_fifo[de->cmd_len].data = data;\n \n@@ -316,8 +367,7 @@ static int p1_apb_write(struct rpivid_de\n \t\t\t  de->cmd_len, addr, data);\n \t}\n #endif\n-\n-\treturn de->cmd_len++;\n+\tde->cmd_len++;\n }\n \n static int ctb_to_tile(unsigned int ctb, unsigned int *bd, int num)\n@@ -511,6 +561,7 @@ static const u8 prob_init[3][156] = {\n \t},\n };\n \n+#define CMDS_WRITE_PROB ((RPI_PROB_ARRAY_SIZE / 4) + 1)\n static void write_prob(struct rpivid_dec_env *const de,\n \t\t       const struct rpivid_dec_state *const s)\n {\n@@ -554,6 +605,7 @@ static void write_prob(struct rpivid_dec\n \tp1_apb_write(de, RPI_TRANSFER, PROB_BACKUP);\n }\n \n+#define CMDS_WRITE_SCALING_FACTORS NUM_SCALING_FACTORS\n static void write_scaling_factors(struct rpivid_dec_env *const de)\n {\n \tint i;\n@@ -569,8 +621,9 @@ static inline __u32 dma_to_axi_addr(dma_\n \treturn (__u32)(a >> 6);\n }\n \n-static void write_bitstream(struct rpivid_dec_env *const de,\n-\t\t\t    const struct rpivid_dec_state *const s)\n+#define CMDS_WRITE_BITSTREAM 4\n+static int write_bitstream(struct rpivid_dec_env *const de,\n+\t\t\t   const struct rpivid_dec_state *const s)\n {\n \t// Note that FFmpeg V4L2 does not remove emulation prevention bytes,\n \t// so this is matched in the configuration here.\n@@ -584,6 +637,13 @@ static void write_bitstream(struct rpivi\n \tif (s->src_addr != 0) {\n \t\taddr = s->src_addr + offset;\n \t} else {\n+\t\tif (len + de->bit_copy_len > de->bit_copy_gptr->size) {\n+\t\t\tv4l2_warn(&de->ctx->dev->v4l2_dev,\n+\t\t\t\t  \"Bit copy buffer overflow: size=%zu, offset=%zu, len=%u\\n\",\n+\t\t\t\t  de->bit_copy_gptr->size,\n+\t\t\t\t  de->bit_copy_len, len);\n+\t\t\treturn -ENOMEM;\n+\t\t}\n \t\tmemcpy(de->bit_copy_gptr->ptr + de->bit_copy_len,\n \t\t       s->src_buf + offset, len);\n \t\taddr = de->bit_copy_gptr->addr + de->bit_copy_len;\n@@ -595,6 +655,7 @@ static void write_bitstream(struct rpivi\n \tp1_apb_write(de, RPI_BFNUM, len);\n \tp1_apb_write(de, RPI_BFCONTROL, offset + (1 << 7)); // Stop\n \tp1_apb_write(de, RPI_BFCONTROL, offset + (rpi_use_emu << 6));\n+\treturn 0;\n }\n \n //////////////////////////////////////////////////////////////////////////////\n@@ -623,6 +684,7 @@ static u32 slice_reg_const(const struct\n \n //////////////////////////////////////////////////////////////////////////////\n \n+#define CMDS_NEW_SLICE_SEGMENT (4 + CMDS_WRITE_SCALING_FACTORS)\n static void new_slice_segment(struct rpivid_dec_env *const de,\n \t\t\t      const struct rpivid_dec_state *const s)\n {\n@@ -706,6 +768,7 @@ static void msg_slice(struct rpivid_dec_\n \tde->slice_msgs[de->num_slice_msgs++] = msg;\n }\n \n+#define CMDS_PROGRAM_SLICECMDS (1 + SLICE_MSGS_MAX)\n static void program_slicecmds(struct rpivid_dec_env *const de,\n \t\t\t      const int sliceid)\n {\n@@ -902,6 +965,7 @@ static void pre_slice_decode(struct rpiv\n \t\t       (sh->slice_cb_qp_offset & 31)); // CMD_QPOFF\n }\n \n+#define CMDS_WRITE_SLICE 1\n static void write_slice(struct rpivid_dec_env *const de,\n \t\t\tconst struct rpivid_dec_state *const s,\n \t\t\tconst u32 slice_const,\n@@ -927,6 +991,7 @@ static void write_slice(struct rpivid_de\n  * N.B. This can be called to fill in data from the previous slice so must not\n  * use any state data that may change from slice to slice (e.g. qp)\n  */\n+#define CMDS_NEW_ENTRY_POINT (6 + CMDS_WRITE_SLICE)\n static void new_entry_point(struct rpivid_dec_env *const de,\n \t\t\t    const struct rpivid_dec_state *const s,\n \t\t\t    const bool do_bte,\n@@ -977,6 +1042,7 @@ static void new_entry_point(struct rpivi\n //////////////////////////////////////////////////////////////////////////////\n // Wavefront mode\n \n+#define CMDS_WPP_PAUSE 4\n static void wpp_pause(struct rpivid_dec_env *const de, int ctb_row)\n {\n \tp1_apb_write(de, RPI_STATUS, (ctb_row << 18) | 0x25);\n@@ -987,12 +1053,19 @@ static void wpp_pause(struct rpivid_dec_\n \tp1_apb_write(de, RPI_CONTROL, (ctb_row << 16) + 2);\n }\n \n-static void wpp_entry_fill(struct rpivid_dec_env *const de,\n-\t\t\t   const struct rpivid_dec_state *const s,\n-\t\t\t   const unsigned int last_y)\n+#define CMDS_WPP_ENTRY_FILL_1 (CMDS_WPP_PAUSE + 2 + CMDS_NEW_ENTRY_POINT)\n+static int wpp_entry_fill(struct rpivid_dec_env *const de,\n+\t\t\t  const struct rpivid_dec_state *const s,\n+\t\t\t  const unsigned int last_y)\n {\n+\tint rv;\n \tconst unsigned int last_x = s->ctb_width - 1;\n \n+\trv = cmds_check_space(de, CMDS_WPP_ENTRY_FILL_1 *\n+\t\t\t\t  (last_y - de->entry_ctb_y));\n+\tif (rv)\n+\t\treturn rv;\n+\n \twhile (de->entry_ctb_y < last_y) {\n \t\t/* wpp_entry_x/y set by wpp_entry_point */\n \t\tif (s->ctb_width > 2)\n@@ -1010,12 +1083,21 @@ static void wpp_entry_fill(struct rpivid\n \t\t\t\t0, 0, 0, de->entry_ctb_y + 1,\n \t\t\t\tde->entry_qp, de->entry_slice);\n \t}\n+\treturn 0;\n }\n \n-static void wpp_end_previous_slice(struct rpivid_dec_env *const de,\n-\t\t\t\t   const struct rpivid_dec_state *const s)\n+static int wpp_end_previous_slice(struct rpivid_dec_env *const de,\n+\t\t\t\t  const struct rpivid_dec_state *const s)\n {\n-\twpp_entry_fill(de, s, s->prev_ctb_y);\n+\tint rv;\n+\n+\trv = wpp_entry_fill(de, s, s->prev_ctb_y);\n+\tif (rv)\n+\t\treturn rv;\n+\n+\trv = cmds_check_space(de, CMDS_WPP_PAUSE + 2);\n+\tif (rv)\n+\t\treturn rv;\n \n \tif (de->entry_ctb_x < 2 &&\n \t    (de->entry_ctb_y < s->start_ctb_y || s->start_ctb_x > 2) &&\n@@ -1026,21 +1108,38 @@ static void wpp_end_previous_slice(struc\n \tif (s->start_ctb_x == 2 ||\n \t    (s->ctb_width == 2 && de->entry_ctb_y < s->start_ctb_y))\n \t\tp1_apb_write(de, RPI_TRANSFER, PROB_BACKUP);\n+\treturn 0;\n }\n \n /* Only main profile supported so WPP => !Tiles which makes some of the\n  * next chunk code simpler\n  */\n-static void wpp_decode_slice(struct rpivid_dec_env *const de,\n-\t\t\t     const struct rpivid_dec_state *const s)\n+static int wpp_decode_slice(struct rpivid_dec_env *const de,\n+\t\t\t    const struct rpivid_dec_state *const s)\n {\n \tbool reset_qp_y = true;\n \tconst bool indep = !s->dependent_slice_segment_flag;\n+\tint rv;\n \n-\tif (s->start_ts)\n-\t\twpp_end_previous_slice(de, s);\n+\tif (s->start_ts) {\n+\t\trv = wpp_end_previous_slice(de, s);\n+\t\tif (rv)\n+\t\t\treturn rv;\n+\t}\n \tpre_slice_decode(de, s);\n-\twrite_bitstream(de, s);\n+\n+\trv = cmds_check_space(de,\n+\t\t\t      CMDS_WRITE_BITSTREAM +\n+\t\t\t\tCMDS_WRITE_PROB +\n+\t\t\t\tCMDS_PROGRAM_SLICECMDS +\n+\t\t\t\tCMDS_NEW_SLICE_SEGMENT +\n+\t\t\t\tCMDS_NEW_ENTRY_POINT);\n+\tif (rv)\n+\t\treturn rv;\n+\n+\trv = write_bitstream(de, s);\n+\tif (rv)\n+\t\treturn rv;\n \n \tif (!s->start_ts || indep || s->ctb_width == 1)\n \t\twrite_prob(de, s);\n@@ -1056,7 +1155,13 @@ static void wpp_decode_slice(struct rpiv\n \t\t\ts->slice_qp, slice_reg_const(s));\n \n \tif (s->frame_end) {\n-\t\twpp_entry_fill(de, s, s->ctb_height - 1);\n+\t\trv = wpp_entry_fill(de, s, s->ctb_height - 1);\n+\t\tif (rv)\n+\t\t\treturn rv;\n+\n+\t\trv = cmds_check_space(de, CMDS_WPP_PAUSE + 1);\n+\t\tif (rv)\n+\t\t\treturn rv;\n \n \t\tif (de->entry_ctb_x < 2 && s->ctb_width > 2)\n \t\t\twpp_pause(de, s->ctb_height - 1);\n@@ -1065,25 +1170,32 @@ static void wpp_decode_slice(struct rpiv\n \t\t\t     1 | ((s->ctb_width - 1) << 5) |\n \t\t\t\t((s->ctb_height - 1) << 18));\n \t}\n-\n+\treturn 0;\n }\n \n //////////////////////////////////////////////////////////////////////////////\n // Tiles mode\n \n-static void tile_entry_fill(struct rpivid_dec_env *const de,\n-\t\t\t    const struct rpivid_dec_state *const s,\n-\t\t\t    const unsigned int last_tile_x,\n-\t\t\t    const unsigned int last_tile_y)\n+// Guarantees 1 cmd entry free on exit\n+static int tile_entry_fill(struct rpivid_dec_env *const de,\n+\t\t\t   const struct rpivid_dec_state *const s,\n+\t\t\t   const unsigned int last_tile_x,\n+\t\t\t   const unsigned int last_tile_y)\n {\n \twhile (de->entry_tile_y < last_tile_y ||\n \t       (de->entry_tile_y == last_tile_y &&\n \t\tde->entry_tile_x < last_tile_x)) {\n+\t\tint rv;\n \t\tunsigned int t_x = de->entry_tile_x;\n \t\tunsigned int t_y = de->entry_tile_y;\n \t\tconst unsigned int last_x = s->col_bd[t_x + 1] - 1;\n \t\tconst unsigned int last_y = s->row_bd[t_y + 1] - 1;\n \n+\t\t// One more than needed here\n+\t\trv = cmds_check_space(de, CMDS_NEW_ENTRY_POINT + 3);\n+\t\tif (rv)\n+\t\t\treturn rv;\n+\n \t\tp1_apb_write(de, RPI_STATUS,\n \t\t\t     2 | (last_x << 5) | (last_y << 18));\n \t\tp1_apb_write(de, RPI_TRANSFER, PROB_RELOAD);\n@@ -1098,33 +1210,55 @@ static void tile_entry_fill(struct rpivi\n \t\t\t\tt_x, t_y, s->col_bd[t_x], s->row_bd[t_y],\n \t\t\t\tde->entry_qp, de->entry_slice);\n \t}\n+\treturn 0;\n }\n \n /*\n  * Write STATUS register with expected end CTU address of previous slice\n  */\n-static void end_previous_slice(struct rpivid_dec_env *const de,\n-\t\t\t       const struct rpivid_dec_state *const s)\n+static int end_previous_slice(struct rpivid_dec_env *const de,\n+\t\t\t      const struct rpivid_dec_state *const s)\n {\n-\ttile_entry_fill(de, s,\n-\t\t\tctb_to_tile_x(s, s->prev_ctb_x),\n-\t\t\tctb_to_tile_y(s, s->prev_ctb_y));\n+\tint rv;\n+\n+\trv = tile_entry_fill(de, s,\n+\t\t\t     ctb_to_tile_x(s, s->prev_ctb_x),\n+\t\t\t     ctb_to_tile_y(s, s->prev_ctb_y));\n+\tif (rv)\n+\t\treturn rv;\n+\n \tp1_apb_write(de, RPI_STATUS,\n \t\t     1 | (s->prev_ctb_x << 5) | (s->prev_ctb_y << 18));\n+\treturn 0;\n }\n \n-static void decode_slice(struct rpivid_dec_env *const de,\n-\t\t\t const struct rpivid_dec_state *const s)\n+static int decode_slice(struct rpivid_dec_env *const de,\n+\t\t\tconst struct rpivid_dec_state *const s)\n {\n \tbool reset_qp_y;\n \tunsigned int tile_x = ctb_to_tile_x(s, s->start_ctb_x);\n \tunsigned int tile_y = ctb_to_tile_y(s, s->start_ctb_y);\n+\tint rv;\n \n-\tif (s->start_ts)\n-\t\tend_previous_slice(de, s);\n+\tif (s->start_ts) {\n+\t\trv = end_previous_slice(de, s);\n+\t\tif (rv)\n+\t\t\treturn rv;\n+\t}\n+\n+\trv = cmds_check_space(de,\n+\t\t\t      CMDS_WRITE_BITSTREAM +\n+\t\t\t\tCMDS_WRITE_PROB +\n+\t\t\t\tCMDS_PROGRAM_SLICECMDS +\n+\t\t\t\tCMDS_NEW_SLICE_SEGMENT +\n+\t\t\t\tCMDS_NEW_ENTRY_POINT);\n+\tif (rv)\n+\t\treturn rv;\n \n \tpre_slice_decode(de, s);\n-\twrite_bitstream(de, s);\n+\trv = write_bitstream(de, s);\n+\tif (rv)\n+\t\treturn rv;\n \n \treset_qp_y = !s->start_ts ||\n \t\t!s->dependent_slice_segment_flag ||\n@@ -1146,13 +1280,16 @@ static void decode_slice(struct rpivid_d\n \t * when it will be known where this slice finishes\n \t */\n \tif (s->frame_end) {\n-\t\ttile_entry_fill(de, s,\n-\t\t\t\ts->tile_width - 1,\n-\t\t\t\ts->tile_height - 1);\n+\t\trv = tile_entry_fill(de, s,\n+\t\t\t\t     s->tile_width - 1,\n+\t\t\t\t     s->tile_height - 1);\n+\t\tif (rv)\n+\t\t\treturn rv;\n \t\tp1_apb_write(de, RPI_STATUS,\n \t\t\t     1 | ((s->ctb_width - 1) << 5) |\n \t\t\t\t((s->ctb_height - 1) << 18));\n \t}\n+\treturn 0;\n }\n \n //////////////////////////////////////////////////////////////////////////////\n@@ -1524,7 +1661,7 @@ static void rpivid_h265_setup(struct rpi\n \tstruct rpivid_dev *const dev = ctx->dev;\n \tconst struct v4l2_ctrl_hevc_slice_params *const sh =\n \t\t\t\t\t\trun->h265.slice_params;\n-\tconst struct v4l2_hevc_pred_weight_table *pred_weight_table;\n+//\tconst struct v4l2_hevc_pred_weight_table *pred_weight_table;\n \tstruct rpivid_q_aux *dpb_q_aux[V4L2_HEVC_DPB_ENTRIES_NUM_MAX];\n \tstruct rpivid_dec_state *const s = ctx->state;\n \tstruct vb2_queue *vq;\n@@ -1532,11 +1669,12 @@ static void rpivid_h265_setup(struct rpi\n \tunsigned int prev_rs;\n \tunsigned int i;\n \tint use_aux;\n+\tint rv;\n \tbool slice_temporal_mvp;\n \n \txtrace_in(dev, de);\n \n-\tpred_weight_table = &sh->pred_weight_table;\n+//\tpred_weight_table = &sh->pred_weight_table;\n \n \ts->frame_end =\n \t\t((run->src->flags & V4L2_BUF_FLAG_M2M_HOLD_CAPTURE_BUF) == 0);\n@@ -1608,9 +1746,9 @@ static void rpivid_h265_setup(struct rpi\n \t\tde->cmd_len = 0;\n \t\tde->dpbno_col = ~0U;\n \n-\t\tde->bit_copy_gptr = ctx->bitbufs + 0;\n+\t\tde->bit_copy_gptr = ctx->bitbufs + ctx->p1idx;\n \t\tde->bit_copy_len = 0;\n-\t\tde->cmd_copy_gptr = ctx->cmdbufs + 0;\n+\t\tde->cmd_copy_gptr = ctx->cmdbufs + ctx->p1idx;\n \n \t\tde->frame_c_offset = ctx->dst_fmt.height * 128;\n \t\tde->frame_stride = ctx->dst_fmt.plane_fmt[0].bytesperline * 128;\n@@ -1727,6 +1865,9 @@ static void rpivid_h265_setup(struct rpi\n \t\t\tbits_alloc = wxh < 983040 ? wxh * 3 / 4 :\n \t\t\t\twxh < 983040 * 2 ? 983040 * 3 / 4 :\n \t\t\t\twxh * 3 / 8;\n+\t\t\t/* Allow for bit depth */\n+\t\t\tbits_alloc += (bits_alloc *\n+\t\t\t\t       s->sps.bit_depth_luma_minus8) / 8;\n \t\t\tbits_alloc = round_up_size(bits_alloc);\n \n \t\t\tif (gptr_alloc(dev, de->bit_copy_gptr,\n@@ -1743,18 +1884,35 @@ static void rpivid_h265_setup(struct rpi\n \t\t}\n \t}\n \n-\t// Pre calc a few things\n-\ts->src_addr =\n-\t\t!s->frame_end ?\n-\t\t\t0 :\n-\t\t\tvb2_dma_contig_plane_dma_addr(&run->src->vb2_buf, 0);\n-\ts->src_buf = s->src_addr != 0 ? NULL :\n-\t\t\t\t\tvb2_plane_vaddr(&run->src->vb2_buf, 0);\n+\t// Either map src buffer or use directly\n+\ts->src_addr = 0;\n+\ts->src_buf = NULL;\n+\n+\tif (run->src->planes[0].bytesused < (sh->bit_size + 7) / 8) {\n+\t\tv4l2_warn(&dev->v4l2_dev,\n+\t\t\t  \"Bit size %d > bytesused %d\\n\",\n+\t\t\t  sh->bit_size, run->src->planes[0].bytesused);\n+\t\tgoto fail;\n+\t}\n+\tif (sh->data_bit_offset >= sh->bit_size ||\n+\t    sh->bit_size - sh->data_bit_offset < 8) {\n+\t\tv4l2_warn(&dev->v4l2_dev,\n+\t\t\t  \"Bit size %d < Bit offset %d + 8\\n\",\n+\t\t\t  sh->bit_size, sh->data_bit_offset);\n+\t\tgoto fail;\n+\t}\n+\n+\tif (s->frame_end)\n+\t\ts->src_addr = vb2_dma_contig_plane_dma_addr(&run->src->vb2_buf,\n+\t\t\t\t\t\t\t    0);\n+\tif (!s->src_addr)\n+\t\ts->src_buf = vb2_plane_vaddr(&run->src->vb2_buf, 0);\n \tif (!s->src_addr && !s->src_buf) {\n \t\tv4l2_err(&dev->v4l2_dev, \"Failed to map src buffer\\n\");\n \t\tgoto fail;\n \t}\n \n+\t// Pre calc a few things\n \ts->sh = sh;\n \ts->slice_qp = 26 + s->pps.init_qp_minus26 + s->sh->slice_qp_delta;\n \ts->max_num_merge_cand = sh->slice_type == HEVC_SLICE_I ?\n@@ -1785,9 +1943,11 @@ static void rpivid_h265_setup(struct rpi\n \ts->prev_ctb_y = prev_rs / de->pic_width_in_ctbs_y;\n \n \tif ((s->pps.flags & V4L2_HEVC_PPS_FLAG_ENTROPY_CODING_SYNC_ENABLED))\n-\t\twpp_decode_slice(de, s);\n+\t\trv = wpp_decode_slice(de, s);\n \telse\n-\t\tdecode_slice(de, s);\n+\t\trv = decode_slice(de, s);\n+\tif (rv)\n+\t\tgoto fail;\n \n \tif (!s->frame_end) {\n \t\txtrace_ok(dev, de);\n@@ -1945,29 +2105,28 @@ static int check_status(const struct rpi\n \treturn -1;\n }\n \n-static void cb_phase2(struct rpivid_dev *const dev, void *v)\n+static void phase2_cb(struct rpivid_dev *const dev, void *v)\n {\n \tstruct rpivid_dec_env *const de = v;\n-\tstruct rpivid_ctx *const ctx = de->ctx;\n \n \txtrace_in(dev, de);\n \n-\tv4l2_m2m_cap_buf_return(dev->m2m_dev, ctx->fh.m2m_ctx, de->frame_buf,\n-\t\t\t\tVB2_BUF_STATE_DONE);\n-\tde->frame_buf = NULL;\n+\t/* Done with buffers - allow new P1 */\n+\trpivid_hw_irq_active1_enable_claim(dev, 1);\n \n-\t/* Delete de before finish as finish might immediately trigger a reuse\n-\t * of de\n-\t */\n-\tdec_env_delete(de);\n+\tv4l2_m2m_buf_done(de->frame_buf, VB2_BUF_STATE_DONE);\n+\tde->frame_buf = NULL;\n \n-\tif (atomic_add_return(-1, &ctx->p2out) >= RPIVID_P2BUF_COUNT - 1) {\n-\t\txtrace_fin(dev, de);\n-\t\tv4l2_m2m_buf_done_and_job_finish(dev->m2m_dev, ctx->fh.m2m_ctx,\n-\t\t\t\t\t\t VB2_BUF_STATE_DONE);\n-\t}\n+#if USE_REQUEST_PIN\n+\tmedia_request_unpin(de->req_pin);\n+\tde->req_pin = NULL;\n+#else\n+\tmedia_request_object_complete(de->req_obj);\n+\tde->req_obj = NULL;\n+#endif\n \n \txtrace_ok(dev, de);\n+\tdec_env_delete(de);\n }\n \n static void phase2_claimed(struct rpivid_dev *const dev, void *v)\n@@ -2023,7 +2182,7 @@ static void phase2_claimed(struct rpivid\n \t//\t   de->ctx->colmvbuf.addr, de->ctx->colmvbuf.addr +\n \t//\t   de->ctx->colmvbuf.size);\n \n-\trpivid_hw_irq_active2_irq(dev, &de->irq_ent, cb_phase2, de);\n+\trpivid_hw_irq_active2_irq(dev, &de->irq_ent, phase2_cb, de);\n \n \tapb_write_final(dev, RPI_NUMROWS, de->pic_height_in_ctbs_y);\n \n@@ -2032,6 +2191,39 @@ static void phase2_claimed(struct rpivid\n \n static void phase1_claimed(struct rpivid_dev *const dev, void *v);\n \n+// release any and all objects associated with de\n+// and reenable phase 1 if required\n+static void phase1_err_fin(struct rpivid_dev *const dev,\n+\t\t\t   struct rpivid_ctx *const ctx,\n+\t\t\t   struct rpivid_dec_env *const de)\n+{\n+\t/* Return all detached buffers */\n+\tif (de->src_buf)\n+\t\tv4l2_m2m_buf_done(de->src_buf, VB2_BUF_STATE_ERROR);\n+\tde->src_buf = NULL;\n+\tif (de->frame_buf)\n+\t\tv4l2_m2m_buf_done(de->frame_buf, VB2_BUF_STATE_ERROR);\n+\tde->frame_buf = NULL;\n+#if USE_REQUEST_PIN\n+\tif (de->req_pin)\n+\t\tmedia_request_unpin(de->req_pin);\n+\tde->req_pin = NULL;\n+#else\n+\tif (de->req_obj)\n+\t\tmedia_request_object_complete(de->req_obj);\n+\tde->req_obj = NULL;\n+#endif\n+\n+\tdec_env_delete(de);\n+\n+\t/* Reenable phase 0 if we were blocking */\n+\tif (atomic_add_return(-1, &ctx->p1out) >= RPIVID_P1BUF_COUNT - 1)\n+\t\tv4l2_m2m_job_finish(dev->m2m_dev, ctx->fh.m2m_ctx);\n+\n+\t/* Done with P1-P2 buffers - allow new P1 */\n+\trpivid_hw_irq_active1_enable_claim(dev, 1);\n+}\n+\n static void phase1_thread(struct rpivid_dev *const dev, void *v)\n {\n \tstruct rpivid_dec_env *const de = v;\n@@ -2076,15 +2268,12 @@ fail:\n \t\t\t __func__);\n \t\tctx->fatal_err = 1;\n \t}\n-\tdec_env_delete(de);\n-\txtrace_fin(dev, de);\n-\tv4l2_m2m_buf_done_and_job_finish(dev->m2m_dev, ctx->fh.m2m_ctx,\n-\t\t\t\t\t VB2_BUF_STATE_ERROR);\n \txtrace_fail(dev, de);\n+\tphase1_err_fin(dev, ctx, de);\n }\n \n /* Always called in irq context (this is good) */\n-static void cb_phase1(struct rpivid_dev *const dev, void *v)\n+static void phase1_cb(struct rpivid_dev *const dev, void *v)\n {\n \tstruct rpivid_dec_env *const de = v;\n \tstruct rpivid_ctx *const ctx = de->ctx;\n@@ -2092,6 +2281,7 @@ static void cb_phase1(struct rpivid_dev\n \txtrace_in(dev, de);\n \n \tde->p1_status = check_status(dev);\n+\n \tif (de->p1_status != 0) {\n \t\tv4l2_info(&dev->v4l2_dev, \"%s: Post wait: %#x\\n\",\n \t\t\t  __func__, de->p1_status);\n@@ -2105,24 +2295,17 @@ static void cb_phase1(struct rpivid_dev\n \t\treturn;\n \t}\n \n-\t/* After the frame-buf is detached it must be returned but from\n-\t * this point onward (phase2_claimed, cb_phase2) there are no error\n-\t * paths so the return at the end of cb_phase2 is all that is needed\n-\t */\n-\tde->frame_buf = v4l2_m2m_cap_buf_detach(dev->m2m_dev, ctx->fh.m2m_ctx);\n-\tif (!de->frame_buf) {\n-\t\tv4l2_err(&dev->v4l2_dev, \"%s: No detached buffer\\n\", __func__);\n-\t\tgoto fail;\n-\t}\n+\tv4l2_m2m_buf_done(de->src_buf, VB2_BUF_STATE_DONE);\n+\tde->src_buf = NULL;\n \n+\t/* All phase1 error paths done - it is safe to inc p2idx */\n \tctx->p2idx =\n \t\t(ctx->p2idx + 1 >= RPIVID_P2BUF_COUNT) ? 0 : ctx->p2idx + 1;\n \n-\t// Enable the next setup if our Q isn't too big\n-\tif (atomic_add_return(1, &ctx->p2out) < RPIVID_P2BUF_COUNT) {\n+\t/* Renable the next setup if we were blocking */\n+\tif (atomic_add_return(-1, &ctx->p1out) >= RPIVID_P1BUF_COUNT - 1) {\n \t\txtrace_fin(dev, de);\n-\t\tv4l2_m2m_buf_done_and_job_finish(dev->m2m_dev, ctx->fh.m2m_ctx,\n-\t\t\t\t\t\t VB2_BUF_STATE_DONE);\n+\t\tv4l2_m2m_job_finish(dev->m2m_dev, ctx->fh.m2m_ctx);\n \t}\n \n \trpivid_hw_irq_active2_claim(dev, &de->irq_ent, phase2_claimed, de);\n@@ -2131,11 +2314,8 @@ static void cb_phase1(struct rpivid_dev\n \treturn;\n \n fail:\n-\tdec_env_delete(de);\n-\txtrace_fin(dev, de);\n-\tv4l2_m2m_buf_done_and_job_finish(dev->m2m_dev, ctx->fh.m2m_ctx,\n-\t\t\t\t\t VB2_BUF_STATE_ERROR);\n \txtrace_fail(dev, de);\n+\tphase1_err_fin(dev, ctx, de);\n }\n \n static void phase1_claimed(struct rpivid_dev *const dev, void *v)\n@@ -2160,6 +2340,10 @@ static void phase1_claimed(struct rpivid\n \tde->coeff_stride =\n \t\tALIGN_DOWN(coeff_gptr->size / de->pic_height_in_ctbs_y, 64);\n \n+\t/* phase1_claimed blocked until cb_phase1 completed so p2idx inc\n+\t * in cb_phase1 after error detection\n+\t */\n+\n \tapb_write_vc_addr(dev, RPI_PUWBASE, de->pu_base_vc);\n \tapb_write_vc_len(dev, RPI_PUWSTRIDE, de->pu_stride);\n \tapb_write_vc_addr(dev, RPI_COEFFWBASE, de->coeff_base_vc);\n@@ -2169,7 +2353,7 @@ static void phase1_claimed(struct rpivid\n \tapb_write(dev, RPI_CFNUM, de->cmd_len);\n \n \t// Claim irq\n-\trpivid_hw_irq_active1_irq(dev, &de->irq_ent, cb_phase1, de);\n+\trpivid_hw_irq_active1_irq(dev, &de->irq_ent, phase1_cb, de);\n \n \t// And start the h/w\n \tapb_write_vc_addr_final(dev, RPI_CFBASE, de->cmd_copy_gptr->addr);\n@@ -2178,11 +2362,8 @@ static void phase1_claimed(struct rpivid\n \treturn;\n \n fail:\n-\tdec_env_delete(de);\n-\txtrace_fin(dev, de);\n-\tv4l2_m2m_buf_done_and_job_finish(dev->m2m_dev, ctx->fh.m2m_ctx,\n-\t\t\t\t\t VB2_BUF_STATE_ERROR);\n \txtrace_fail(dev, de);\n+\tphase1_err_fin(dev, ctx, de);\n }\n \n static void dec_state_delete(struct rpivid_ctx *const ctx)\n@@ -2315,7 +2496,9 @@ static void rpivid_h265_trigger(struct r\n \tcase RPIVID_DECODE_SLICE_CONTINUE:\n \t\tv4l2_m2m_buf_done_and_job_finish(dev->m2m_dev, ctx->fh.m2m_ctx,\n \t\t\t\t\t\t VB2_BUF_STATE_DONE);\n+\t\txtrace_ok(dev, de);\n \t\tbreak;\n+\n \tdefault:\n \t\tv4l2_err(&dev->v4l2_dev, \"%s: Unexpected state: %d\\n\", __func__,\n \t\t\t de->state);\n@@ -2329,14 +2512,59 @@ static void rpivid_h265_trigger(struct r\n \t\tv4l2_m2m_buf_done_and_job_finish(dev->m2m_dev, ctx->fh.m2m_ctx,\n \t\t\t\t\t\t VB2_BUF_STATE_ERROR);\n \t\tbreak;\n+\n \tcase RPIVID_DECODE_PHASE1:\n \t\tctx->dec0 = NULL;\n+\n+#if !USE_REQUEST_PIN\n+\t\t/* Alloc a new request object - needs to be alloced dynamically\n+\t\t * as the media request will release it some random time after\n+\t\t * it is completed\n+\t\t */\n+\t\tde->req_obj = kmalloc(sizeof(*de->req_obj), GFP_KERNEL);\n+\t\tif (!de->req_obj) {\n+\t\t\txtrace_fail(dev, de);\n+\t\t\tdec_env_delete(de);\n+\t\t\tv4l2_m2m_buf_done_and_job_finish(dev->m2m_dev,\n+\t\t\t\t\t\t\t ctx->fh.m2m_ctx,\n+\t\t\t\t\t\t\t VB2_BUF_STATE_ERROR);\n+\t\t\tbreak;\n+\t\t}\n+\t\tmedia_request_object_init(de->req_obj);\n+#warning probably needs to _get the req obj too\n+#endif\n+\t\tctx->p1idx = (ctx->p1idx + 1 >= RPIVID_P1BUF_COUNT) ?\n+\t\t\t\t\t\t\t0 : ctx->p1idx + 1;\n+\n+\t\t/* We know we have src & dst so no need to test */\n+\t\tde->src_buf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);\n+\t\tde->frame_buf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);\n+\n+#if USE_REQUEST_PIN\n+\t\tde->req_pin = de->src_buf->vb2_buf.req_obj.req;\n+\t\tmedia_request_pin(de->req_pin);\n+#else\n+\t\tmedia_request_object_bind(de->src_buf->vb2_buf.req_obj.req,\n+\t\t\t\t\t  &dst_req_obj_ops, de, false,\n+\t\t\t\t\t  de->req_obj);\n+#endif\n+\n+\t\t/* We could get rid of the src buffer here if we've already\n+\t\t * copied it, but we don't copy the last buffer unless it\n+\t\t * didn't return a contig dma addr and that shouldn't happen\n+\t\t */\n+\n+\t\t/* Enable the next setup if our Q isn't too big */\n+\t\tif (atomic_add_return(1, &ctx->p1out) < RPIVID_P1BUF_COUNT) {\n+\t\t\txtrace_fin(dev, de);\n+\t\t\tv4l2_m2m_job_finish(dev->m2m_dev, ctx->fh.m2m_ctx);\n+\t\t}\n+\n \t\trpivid_hw_irq_active1_claim(dev, &de->irq_ent, phase1_claimed,\n \t\t\t\t\t    de);\n+\t\txtrace_ok(dev, de);\n \t\tbreak;\n \t}\n-\n-\txtrace_ok(dev, de);\n }\n \n struct rpivid_dec_ops rpivid_dec_ops_h265 = {\n--- a/drivers/staging/media/rpivid/rpivid_hw.c\n+++ b/drivers/staging/media/rpivid/rpivid_hw.c\n@@ -185,14 +185,14 @@ static void do_enable_claim(struct rpivi\n \tsched_cb(dev, ictl, ient);\n }\n \n-static void ictl_init(struct rpivid_hw_irq_ctrl * const ictl)\n+static void ictl_init(struct rpivid_hw_irq_ctrl * const ictl, int enables)\n {\n \tspin_lock_init(&ictl->lock);\n \tictl->claim = NULL;\n \tictl->tail = NULL;\n \tictl->irq = NULL;\n \tictl->no_sched = 0;\n-\tictl->enable = -1;\n+\tictl->enable = enables;\n \tictl->thread_reqed = false;\n }\n \n@@ -308,8 +308,8 @@ int rpivid_hw_probe(struct rpivid_dev *d\n \tint irq_dec;\n \tint ret = 0;\n \n-\tictl_init(&dev->ic_active1);\n-\tictl_init(&dev->ic_active2);\n+\tictl_init(&dev->ic_active1, RPIVID_P2BUF_COUNT);\n+\tictl_init(&dev->ic_active2, RPIVID_ICTL_ENABLE_UNLIMITED);\n \n \tres = platform_get_resource_byname(dev->pdev, IORESOURCE_MEM, \"intc\");\n \tif (!res)\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0615-media-rpivid-Map-cmd-buffer-directly.patch",
    "content": "From d4f8e47d60c180cf57eba4093a343230a824ecbf Mon Sep 17 00:00:00 2001\nFrom: John Cox <jc@kynesim.co.uk>\nDate: Mon, 29 Mar 2021 17:42:16 +0100\nSubject: [PATCH] media: rpivid: Map cmd buffer directly\n\nIt is unnecessary to have a separate dmabuf to hold the cmd buffer.\nMap it directly from the kmalloc.\n\nSigned-off-by: John Cox <jc@kynesim.co.uk>\n---\n drivers/staging/media/rpivid/rpivid.h      |  3 +-\n drivers/staging/media/rpivid/rpivid_h265.c | 48 ++++++++++------------\n drivers/staging/media/rpivid/rpivid_hw.c   |  2 +\n 3 files changed, 25 insertions(+), 28 deletions(-)\n\n--- a/drivers/staging/media/rpivid/rpivid.h\n+++ b/drivers/staging/media/rpivid/rpivid.h\n@@ -114,7 +114,6 @@ struct rpivid_ctx {\n \tunsigned int p1idx;\n \tatomic_t p1out;\n \tstruct rpivid_gptr bitbufs[RPIVID_P1BUF_COUNT];\n-\tstruct rpivid_gptr cmdbufs[RPIVID_P1BUF_COUNT];\n \n \t/* *** Should be in dev *** */\n \tunsigned int p2idx;\n@@ -183,6 +182,8 @@ struct rpivid_dev {\n \tstruct clk\t\t*clock;\n \tstruct clk_request      *hevc_req;\n \n+\tint\t\t\tcache_align;\n+\n \tstruct rpivid_hw_irq_ctrl ic_active1;\n \tstruct rpivid_hw_irq_ctrl ic_active2;\n };\n--- a/drivers/staging/media/rpivid/rpivid_h265.c\n+++ b/drivers/staging/media/rpivid/rpivid_h265.c\n@@ -227,6 +227,9 @@ struct rpivid_dec_env {\n \tstruct rpivid_q_aux *frame_aux;\n \tstruct rpivid_q_aux *col_aux;\n \n+\tdma_addr_t cmd_addr;\n+\tsize_t cmd_size;\n+\n \tdma_addr_t pu_base_vc;\n \tdma_addr_t coeff_base_vc;\n \tu32 pu_stride;\n@@ -234,7 +237,6 @@ struct rpivid_dec_env {\n \n \tstruct rpivid_gptr *bit_copy_gptr;\n \tsize_t bit_copy_len;\n-\tstruct rpivid_gptr *cmd_copy_gptr;\n \n #define SLICE_MSGS_MAX (2 * HEVC_MAX_REFS * 8 + 3)\n \tu16 slice_msgs[SLICE_MSGS_MAX];\n@@ -1499,22 +1501,17 @@ static int write_cmd_buffer(struct rpivi\n \t\t\t    struct rpivid_dec_env *const de,\n \t\t\t    const struct rpivid_dec_state *const s)\n {\n-\t// Copy commands out to dma buf\n-\tconst size_t cmd_size = de->cmd_len * sizeof(de->cmd_fifo[0]);\n-\n-\tif (!de->cmd_copy_gptr->ptr || cmd_size > de->cmd_copy_gptr->size) {\n-\t\tsize_t cmd_alloc = round_up_size(cmd_size);\n+\tconst size_t cmd_size = ALIGN(de->cmd_len * sizeof(de->cmd_fifo[0]),\n+\t\t\t\t      dev->cache_align);\n \n-\t\tif (gptr_realloc_new(dev, de->cmd_copy_gptr, cmd_alloc)) {\n-\t\t\tv4l2_err(&dev->v4l2_dev,\n-\t\t\t\t \"Alloc cmd buffer (%zu): FAILED\\n\", cmd_alloc);\n-\t\t\treturn -ENOMEM;\n-\t\t}\n-\t\tv4l2_info(&dev->v4l2_dev, \"Alloc cmd buffer (%zu): OK\\n\",\n-\t\t\t  cmd_alloc);\n+\tde->cmd_addr = dma_map_single(dev->dev, de->cmd_fifo,\n+\t\t\t\t      cmd_size, DMA_TO_DEVICE);\n+\tif (dma_mapping_error(dev->dev, de->cmd_addr)) {\n+\t\tv4l2_err(&dev->v4l2_dev,\n+\t\t\t \"Map cmd buffer (%zu): FAILED\\n\", cmd_size);\n+\t\treturn -ENOMEM;\n \t}\n-\n-\tmemcpy(de->cmd_copy_gptr->ptr, de->cmd_fifo, cmd_size);\n+\tde->cmd_size = cmd_size;\n \treturn 0;\n }\n \n@@ -1551,6 +1548,12 @@ static void dec_env_delete(struct rpivid\n \tstruct rpivid_ctx * const ctx = de->ctx;\n \tunsigned long lock_flags;\n \n+\tif (de->cmd_size) {\n+\t\tdma_unmap_single(ctx->dev->dev, de->cmd_addr, de->cmd_size,\n+\t\t\t\t DMA_TO_DEVICE);\n+\t\tde->cmd_size = 0;\n+\t}\n+\n \taux_q_release(ctx, &de->frame_aux);\n \taux_q_release(ctx, &de->col_aux);\n \n@@ -1603,7 +1606,8 @@ static int dec_env_init(struct rpivid_ct\n \n \t\tde->ctx = ctx;\n \t\tde->decode_order = i;\n-\t\tde->cmd_max = 1024;\n+//\t\tde->cmd_max = 1024;\n+\t\tde->cmd_max = 8096;\n \t\tde->cmd_fifo = kmalloc_array(de->cmd_max,\n \t\t\t\t\t     sizeof(struct rpi_cmd),\n \t\t\t\t\t     GFP_KERNEL);\n@@ -1748,7 +1752,6 @@ static void rpivid_h265_setup(struct rpi\n \n \t\tde->bit_copy_gptr = ctx->bitbufs + ctx->p1idx;\n \t\tde->bit_copy_len = 0;\n-\t\tde->cmd_copy_gptr = ctx->cmdbufs + ctx->p1idx;\n \n \t\tde->frame_c_offset = ctx->dst_fmt.height * 128;\n \t\tde->frame_stride = ctx->dst_fmt.plane_fmt[0].bytesperline * 128;\n@@ -2356,7 +2359,7 @@ static void phase1_claimed(struct rpivid\n \trpivid_hw_irq_active1_irq(dev, &de->irq_ent, phase1_cb, de);\n \n \t// And start the h/w\n-\tapb_write_vc_addr_final(dev, RPI_CFBASE, de->cmd_copy_gptr->addr);\n+\tapb_write_vc_addr_final(dev, RPI_CFBASE, de->cmd_addr);\n \n \txtrace_ok(dev, de);\n \treturn;\n@@ -2400,8 +2403,6 @@ static void rpivid_h265_stop(struct rpiv\n \n \tfor (i = 0; i != ARRAY_SIZE(ctx->bitbufs); ++i)\n \t\tgptr_free(dev, ctx->bitbufs + i);\n-\tfor (i = 0; i != ARRAY_SIZE(ctx->cmdbufs); ++i)\n-\t\tgptr_free(dev, ctx->cmdbufs + i);\n \tfor (i = 0; i != ARRAY_SIZE(ctx->pu_bufs); ++i)\n \t\tgptr_free(dev, ctx->pu_bufs + i);\n \tfor (i = 0; i != ARRAY_SIZE(ctx->coeff_bufs); ++i)\n@@ -2451,13 +2452,6 @@ static int rpivid_h265_start(struct rpiv\n \t\tgoto fail;\n \t}\n \n-\t// 16k is plenty for most purposes but we will realloc if needed\n-\tfor (i = 0; i != ARRAY_SIZE(ctx->cmdbufs); ++i) {\n-\t\tif (gptr_alloc(dev, ctx->cmdbufs + i, 0x4000,\n-\t\t\t       DMA_ATTR_FORCE_CONTIGUOUS))\n-\t\t\tgoto fail;\n-\t}\n-\n \t// Finger in the air PU & Coeff alloc\n \t// Will be realloced if too small\n \tcoeff_alloc = round_up_size(wxh);\n--- a/drivers/staging/media/rpivid/rpivid_hw.c\n+++ b/drivers/staging/media/rpivid/rpivid_hw.c\n@@ -331,6 +331,8 @@ int rpivid_hw_probe(struct rpivid_dev *d\n \tif (IS_ERR(dev->clock))\n \t\treturn PTR_ERR(dev->clock);\n \n+\tdev->cache_align = dma_get_cache_alignment();\n+\n \t// Disable IRQs & reset anything pending\n \tirq_write(dev, 0,\n \t\t  ARG_IC_ICTRL_ACTIVE1_EN_SET | ARG_IC_ICTRL_ACTIVE2_EN_SET);\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0616-media-rpivid-Improve-values-returned-when-setting-ou.patch",
    "content": "From 60374506d427194b8ebb8963f5358bffd347c2e3 Mon Sep 17 00:00:00 2001\nFrom: John Cox <jc@kynesim.co.uk>\nDate: Thu, 1 Apr 2021 16:20:58 +0100\nSubject: [PATCH] media: rpivid: Improve values returned when setting\n output format\n\nGuess a better value for the compressed bitstream buffer size\n\nSigned-off-by: John Cox <jc@kynesim.co.uk>\n---\n drivers/staging/media/rpivid/rpivid_h265.c  | 66 ++++-----------------\n drivers/staging/media/rpivid/rpivid_video.c | 61 +++++++++++++++++--\n drivers/staging/media/rpivid/rpivid_video.h |  4 ++\n 3 files changed, 70 insertions(+), 61 deletions(-)\n\n--- a/drivers/staging/media/rpivid/rpivid_h265.c\n+++ b/drivers/staging/media/rpivid/rpivid_h265.c\n@@ -18,6 +18,7 @@\n \n #include \"rpivid.h\"\n #include \"rpivid_hw.h\"\n+#include \"rpivid_video.h\"\n \n #define DEBUG_TRACE_P1_CMD 0\n #define DEBUG_TRACE_EXECUTION 0\n@@ -115,41 +116,9 @@ static int gptr_realloc_new(struct rpivi\n \treturn 0;\n }\n \n-/* floor(log2(x)) */\n-static unsigned int log2_size(size_t x)\n-{\n-\tunsigned int n = 0;\n-\n-\tif (x & ~0xffff) {\n-\t\tn += 16;\n-\t\tx >>= 16;\n-\t}\n-\tif (x & ~0xff) {\n-\t\tn += 8;\n-\t\tx >>= 8;\n-\t}\n-\tif (x & ~0xf) {\n-\t\tn += 4;\n-\t\tx >>= 4;\n-\t}\n-\tif (x & ~3) {\n-\t\tn += 2;\n-\t\tx >>= 2;\n-\t}\n-\treturn (x & ~1) ? n + 1 : n;\n-}\n-\n-static size_t round_up_size(const size_t x)\n-{\n-\t/* Admit no size < 256 */\n-\tconst unsigned int n = x < 256 ? 8 : log2_size(x) - 1;\n-\n-\treturn x >= (3 << n) ? 4 << n : (3 << n);\n-}\n-\n static size_t next_size(const size_t x)\n {\n-\treturn round_up_size(x + 1);\n+\treturn rpivid_round_up_size(x + 1);\n }\n \n #define NUM_SCALING_FACTORS 4064 /* Not a typo = 0xbe0 + 0x400 */\n@@ -332,7 +301,7 @@ static int cmds_check_space(struct rpivi\n \tif (de->cmd_len + n <= de->cmd_max)\n \t\treturn 0;\n \n-\tnewmax = 2 << log2_size(de->cmd_len + n);\n+\tnewmax = roundup_pow_of_two(de->cmd_len + n);\n \n \ta = krealloc(de->cmd_fifo, newmax * sizeof(struct rpi_cmd),\n \t\t     GFP_KERNEL);\n@@ -1855,23 +1824,10 @@ static void rpivid_h265_setup(struct rpi\n \t\t * slice as we can use the src buf directly\n \t\t */\n \t\tif (!s->frame_end && !de->bit_copy_gptr->ptr) {\n-\t\t\tconst size_t wxh = s->sps.pic_width_in_luma_samples *\n-\t\t\t\ts->sps.pic_height_in_luma_samples;\n \t\t\tsize_t bits_alloc;\n-\n-\t\t\t/* Annex A gives a min compression of 2 @ lvl 3.1\n-\t\t\t * (wxh <= 983040) and min 4 thereafter but avoid\n-\t\t\t * the odity of 983041 having a lower limit than\n-\t\t\t * 983040.\n-\t\t\t * Multiply by 3/2 for 4:2:0\n-\t\t\t */\n-\t\t\tbits_alloc = wxh < 983040 ? wxh * 3 / 4 :\n-\t\t\t\twxh < 983040 * 2 ? 983040 * 3 / 4 :\n-\t\t\t\twxh * 3 / 8;\n-\t\t\t/* Allow for bit depth */\n-\t\t\tbits_alloc += (bits_alloc *\n-\t\t\t\t       s->sps.bit_depth_luma_minus8) / 8;\n-\t\t\tbits_alloc = round_up_size(bits_alloc);\n+\t\t\tbits_alloc = rpivid_bit_buf_size(s->sps.pic_width_in_luma_samples,\n+\t\t\t\t\t\t\t s->sps.pic_height_in_luma_samples,\n+\t\t\t\t\t\t\t s->sps.bit_depth_luma_minus8);\n \n \t\t\tif (gptr_alloc(dev, de->bit_copy_gptr,\n \t\t\t\t       bits_alloc,\n@@ -2454,17 +2410,15 @@ static int rpivid_h265_start(struct rpiv\n \n \t// Finger in the air PU & Coeff alloc\n \t// Will be realloced if too small\n-\tcoeff_alloc = round_up_size(wxh);\n-\tpu_alloc = round_up_size(wxh / 4);\n+\tcoeff_alloc = rpivid_round_up_size(wxh);\n+\tpu_alloc = rpivid_round_up_size(wxh / 4);\n \tfor (i = 0; i != ARRAY_SIZE(ctx->pu_bufs); ++i) {\n \t\t// Don't actually need a kernel mapping here\n \t\tif (gptr_alloc(dev, ctx->pu_bufs + i, pu_alloc,\n-\t\t\t       DMA_ATTR_FORCE_CONTIGUOUS |\n-\t\t\t\t\tDMA_ATTR_NO_KERNEL_MAPPING))\n+\t\t\t       DMA_ATTR_NO_KERNEL_MAPPING))\n \t\t\tgoto fail;\n \t\tif (gptr_alloc(dev, ctx->coeff_bufs + i, coeff_alloc,\n-\t\t\t       DMA_ATTR_FORCE_CONTIGUOUS |\n-\t\t\t\t\tDMA_ATTR_NO_KERNEL_MAPPING))\n+\t\t\t       DMA_ATTR_NO_KERNEL_MAPPING))\n \t\t\tgoto fail;\n \t}\n \taux_q_init(ctx);\n--- a/drivers/staging/media/rpivid/rpivid_video.c\n+++ b/drivers/staging/media/rpivid/rpivid_video.c\n@@ -42,18 +42,69 @@ static inline unsigned int constrain2x(u\n \t\t\t(x > y * 2) ? y : x;\n }\n \n+size_t rpivid_round_up_size(const size_t x)\n+{\n+\t/* Admit no size < 256 */\n+\tconst unsigned int n = x < 256 ? 8 : ilog2(x);\n+\n+\treturn x >= (3 << n) ? 4 << n : (3 << n);\n+}\n+\n+size_t rpivid_bit_buf_size(unsigned int w, unsigned int h, unsigned int bits_minus8)\n+{\n+\tconst size_t wxh = w * h;\n+\tsize_t bits_alloc;\n+\n+\t/* Annex A gives a min compression of 2 @ lvl 3.1\n+\t * (wxh <= 983040) and min 4 thereafter but avoid\n+\t * the odity of 983041 having a lower limit than\n+\t * 983040.\n+\t * Multiply by 3/2 for 4:2:0\n+\t */\n+\tbits_alloc = wxh < 983040 ? wxh * 3 / 4 :\n+\t\twxh < 983040 * 2 ? 983040 * 3 / 4 :\n+\t\twxh * 3 / 8;\n+\t/* Allow for bit depth */\n+\tbits_alloc += (bits_alloc * bits_minus8) / 8;\n+\treturn rpivid_round_up_size(bits_alloc);\n+}\n+\n int rpivid_prepare_src_format(struct v4l2_pix_format_mplane *pix_fmt)\n {\n+\tsize_t size;\n+\tu32 w;\n+\tu32 h;\n+\n \tif (pix_fmt->pixelformat != V4L2_PIX_FMT_HEVC_SLICE)\n \t\treturn -EINVAL;\n \n-\t/* Zero bytes per line for encoded source. */\n-\tpix_fmt->plane_fmt[0].bytesperline = 0;\n-\t/* Choose some minimum size since this can't be 0 */\n-\tpix_fmt->plane_fmt[0].sizeimage = max_t(u32, SZ_1K,\n-\t\t\t\t\t\tpix_fmt->plane_fmt[0].sizeimage);\n+\tw = pix_fmt->width;\n+\th = pix_fmt->height;\n+\tif (!w || !h) {\n+\t\tw = 1920;\n+\t\th = 1080;\n+\t}\n+\tif (w > 4096)\n+\t\tw = 4096;\n+\tif (h > 4096)\n+\t\th = 4096;\n+\n+\tif (!pix_fmt->plane_fmt[0].sizeimage ||\n+\t    pix_fmt->plane_fmt[0].sizeimage > SZ_32M) {\n+\t\t/* Unspecified or way too big - pick max for size */\n+\t\tsize = rpivid_bit_buf_size(w, h, 2);\n+\t}\n+\t/* Set a minimum */\n+\tsize = max_t(u32, SZ_4K, pix_fmt->plane_fmt[0].sizeimage);\n+\n+\tpix_fmt->width = w;\n+\tpix_fmt->height = h;\n \tpix_fmt->num_planes = 1;\n \tpix_fmt->field = V4L2_FIELD_NONE;\n+\t/* Zero bytes per line for encoded source. */\n+\tpix_fmt->plane_fmt[0].bytesperline = 0;\n+\tpix_fmt->plane_fmt[0].sizeimage = size;\n+\n \treturn 0;\n }\n \n--- a/drivers/staging/media/rpivid/rpivid_video.h\n+++ b/drivers/staging/media/rpivid/rpivid_video.h\n@@ -24,6 +24,10 @@ extern const struct v4l2_ioctl_ops rpivi\n \n int rpivid_queue_init(void *priv, struct vb2_queue *src_vq,\n \t\t      struct vb2_queue *dst_vq);\n+\n+size_t rpivid_bit_buf_size(unsigned int w, unsigned int h, unsigned int bits_minus8);\n+size_t rpivid_round_up_size(const size_t x);\n+\n int rpivid_prepare_src_format(struct v4l2_pix_format_mplane *pix_fmt);\n int rpivid_prepare_dst_format(struct v4l2_pix_format_mplane *pix_fmt);\n \n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0617-media-rpivid-Improve-stream_on-off-conformance-clock.patch",
    "content": "From 6a269149abd400ff09bb61b254d7d7891b2b01b1 Mon Sep 17 00:00:00 2001\nFrom: John Cox <jc@kynesim.co.uk>\nDate: Sat, 3 Apr 2021 16:27:03 +0100\nSubject: [PATCH] media: rpivid: Improve stream_on/off conformance &\n clock setup\n\nFix stream on & off such that failures leave the driver in the correct\nstate.  Ensure that the clock is on when we are streaming and off when\nall contexts attached to this device have stopped streaming.\n\nSigned-off-by: John Cox <jc@kynesim.co.uk>\n---\n drivers/staging/media/rpivid/rpivid.c       |   8 +-\n drivers/staging/media/rpivid/rpivid.h       |  15 ++-\n drivers/staging/media/rpivid/rpivid_hw.c    |   1 +\n drivers/staging/media/rpivid/rpivid_video.c | 103 +++++++++++++++-----\n 4 files changed, 101 insertions(+), 26 deletions(-)\n\n--- a/drivers/staging/media/rpivid/rpivid.c\n+++ b/drivers/staging/media/rpivid/rpivid.c\n@@ -212,9 +212,12 @@ static int rpivid_open(struct file *file\n \tctx = kzalloc(sizeof(*ctx), GFP_KERNEL);\n \tif (!ctx) {\n \t\tmutex_unlock(&dev->dev_mutex);\n-\t\treturn -ENOMEM;\n+\t\tret = -ENOMEM;\n+\t\tgoto err_unlock;\n \t}\n \n+\tmutex_init(&ctx->ctx_mutex);\n+\n \tv4l2_fh_init(&ctx->fh, video_devdata(file));\n \tfile->private_data = &ctx->fh;\n \tctx->dev = dev;\n@@ -245,7 +248,9 @@ static int rpivid_open(struct file *file\n err_ctrls:\n \tv4l2_ctrl_handler_free(&ctx->hdl);\n err_free:\n+\tmutex_destroy(&ctx->ctx_mutex);\n \tkfree(ctx);\n+err_unlock:\n \tmutex_unlock(&dev->dev_mutex);\n \n \treturn ret;\n@@ -266,6 +271,7 @@ static int rpivid_release(struct file *f\n \tkfree(ctx->ctrls);\n \n \tv4l2_fh_exit(&ctx->fh);\n+\tmutex_destroy(&ctx->ctx_mutex);\n \n \tkfree(ctx);\n \n--- a/drivers/staging/media/rpivid/rpivid.h\n+++ b/drivers/staging/media/rpivid/rpivid.h\n@@ -84,6 +84,11 @@ struct rpivid_q_aux;\n #define RPIVID_AUX_ENT_COUNT VB2_MAX_FRAME\n \n \n+#define RPIVID_CTX_STATE_STOPPED\t0\t/* stream_off */\n+#define RPIVID_CTX_STATE_STREAM_ON\t1\t/* decoding */\n+#define RPIVID_CTX_STATE_STREAM_STOP\t2\t/* in stream_off */\n+#define RPIVID_CTX_STATE_STREAM_ERR\t3\t/* stream_on but broken */\n+\n struct rpivid_ctx {\n \tstruct v4l2_fh\t\t\tfh;\n \tstruct rpivid_dev\t\t*dev;\n@@ -91,10 +96,19 @@ struct rpivid_ctx {\n \tstruct v4l2_pix_format_mplane\tsrc_fmt;\n \tstruct v4l2_pix_format_mplane\tdst_fmt;\n \tint dst_fmt_set;\n+\n+\tatomic_t \t\t\tstream_state;\n+\tstruct clk_request\t\t*clk_req;\n+\tint \t\t\t\tsrc_stream_on;\n+\tint \t\t\t\tdst_stream_on;\n+\n \t// fatal_err is set if an error has occurred s.t. decode cannot\n \t// continue (such as running out of CMA)\n \tint fatal_err;\n \n+\t/* Lock for queue operations */\n+\tstruct mutex\t\t\tctx_mutex;\n+\n \tstruct v4l2_ctrl_handler\thdl;\n \tstruct v4l2_ctrl\t\t**ctrls;\n \n@@ -180,7 +194,6 @@ struct rpivid_dev {\n \tvoid __iomem\t\t*base_h265;\n \n \tstruct clk\t\t*clock;\n-\tstruct clk_request      *hevc_req;\n \n \tint\t\t\tcache_align;\n \n--- a/drivers/staging/media/rpivid/rpivid_hw.c\n+++ b/drivers/staging/media/rpivid/rpivid_hw.c\n@@ -359,6 +359,7 @@ int rpivid_hw_probe(struct rpivid_dev *d\n void rpivid_hw_remove(struct rpivid_dev *dev)\n {\n \t// IRQ auto freed on unload so no need to do it here\n+\t// ioremap auto freed on unload\n \tictl_uninit(&dev->ic_active1);\n \tictl_uninit(&dev->ic_active2);\n }\n--- a/drivers/staging/media/rpivid/rpivid_video.c\n+++ b/drivers/staging/media/rpivid/rpivid_video.c\n@@ -18,6 +18,7 @@\n #include <media/v4l2-mem2mem.h>\n \n #include \"rpivid.h\"\n+#include \"rpivid_hw.h\"\n #include \"rpivid_video.h\"\n #include \"rpivid_dec.h\"\n \n@@ -533,33 +534,85 @@ static int rpivid_buf_prepare(struct vb2\n \treturn 0;\n }\n \n+/* Only stops the clock if streaom off on both output & capture */\n+static void stop_clock(struct rpivid_dev *dev, struct rpivid_ctx *ctx)\n+{\n+\tif (ctx->src_stream_on ||\n+\t    ctx->dst_stream_on ||\n+\t    !ctx->clk_req)\n+\t\treturn;\n+\n+\tclk_request_done(ctx->clk_req);\n+\tctx->clk_req = NULL;\n+\n+\tclk_disable_unprepare(dev->clock);\n+}\n+\n+/* Always starts the clock if it isn't already on this ctx */\n+static int start_clock(struct rpivid_dev *dev, struct rpivid_ctx *ctx)\n+{\n+\tlong max_hevc_clock;\n+\tint rv;\n+\n+\tif (ctx->clk_req)\n+\t\treturn 0;\n+\n+\tmax_hevc_clock = clk_round_rate(dev->clock, ULONG_MAX);\n+\n+\tctx->clk_req = clk_request_start(dev->clock, max_hevc_clock);\n+\tif (!ctx->clk_req) {\n+\t\tdev_err(dev->dev, \"Failed to set clock rate\\n\");\n+\t\treturn -EIO;\n+\t}\n+\n+\trv = clk_prepare_enable(dev->clock);\n+\tif (rv) {\n+\t\tdev_err(dev->dev, \"Failed to enable clock\\n\");\n+\t\tclk_request_done(ctx->clk_req);\n+\t\tctx->clk_req = NULL;\n+\t\treturn rv;\n+\t}\n+\n+\treturn 0;\n+}\n+\n static int rpivid_start_streaming(struct vb2_queue *vq, unsigned int count)\n {\n \tstruct rpivid_ctx *ctx = vb2_get_drv_priv(vq);\n \tstruct rpivid_dev *dev = ctx->dev;\n-\tlong max_hevc_clock = clk_round_rate(dev->clock, ULONG_MAX);\n \tint ret = 0;\n \n-\tif (ctx->src_fmt.pixelformat != V4L2_PIX_FMT_HEVC_SLICE)\n-\t\treturn -EINVAL;\n-\n-\tif (V4L2_TYPE_IS_OUTPUT(vq->type) && dev->dec_ops->start)\n-\t\tret = dev->dec_ops->start(ctx);\n+\tif (!V4L2_TYPE_IS_OUTPUT(vq->type)) {\n+\t\tctx->dst_stream_on = 1;\n+\t\tgoto ok;\n+\t}\n \n-\tdev->hevc_req = clk_request_start(dev->clock, max_hevc_clock);\n-\tif (!dev->hevc_req) {\n-\t\tdev_err(dev->dev, \"Failed to set clock rate\\n\");\n-\t\tgoto out;\n+\tif (ctx->src_fmt.pixelformat != V4L2_PIX_FMT_HEVC_SLICE) {\n+\t\tret = -EINVAL;\n+\t\tgoto fail_cleanup;\n \t}\n \n-\tret = clk_prepare_enable(dev->clock);\n+\tif (ctx->src_stream_on)\n+\t\tgoto ok;\n+\n+\tret = start_clock(dev, ctx);\n \tif (ret)\n-\t\tdev_err(dev->dev, \"Failed to enable clock\\n\");\n+\t\tgoto fail_cleanup;\n \n-out:\n+\tif (dev->dec_ops->start)\n+\t\tret = dev->dec_ops->start(ctx);\n \tif (ret)\n-\t\trpivid_queue_cleanup(vq, VB2_BUF_STATE_QUEUED);\n+\t\tgoto fail_stop_clock;\n+\n+\tctx->src_stream_on = 1;\n+ok:\n+\treturn 0;\n \n+fail_stop_clock:\n+\tstop_clock(dev, ctx);\n+fail_cleanup:\n+\tv4l2_err(&dev->v4l2_dev, \"%s: qtype=%d: FAIL\\n\", __func__, vq->type);\n+\trpivid_queue_cleanup(vq, VB2_BUF_STATE_QUEUED);\n \treturn ret;\n }\n \n@@ -568,17 +621,19 @@ static void rpivid_stop_streaming(struct\n \tstruct rpivid_ctx *ctx = vb2_get_drv_priv(vq);\n \tstruct rpivid_dev *dev = ctx->dev;\n \n-\tif (V4L2_TYPE_IS_OUTPUT(vq->type) && dev->dec_ops->stop)\n-\t\tdev->dec_ops->stop(ctx);\n+\tif (V4L2_TYPE_IS_OUTPUT(vq->type)) {\n+\t\tctx->src_stream_on = 0;\n+\t\tif (dev->dec_ops->stop)\n+\t\t\tdev->dec_ops->stop(ctx);\n+\t} else {\n+\t\tctx->dst_stream_on = 0;\n+\t}\n \n \trpivid_queue_cleanup(vq, VB2_BUF_STATE_ERROR);\n \n-\tif (dev->hevc_req)\n-\t{\n-\t\tclk_request_done(dev->hevc_req);\n-\t\tdev->hevc_req = NULL;\n-\t}\n-\tclk_disable_unprepare(dev->clock);\n+\tvb2_wait_for_all_buffers(vq);\n+\n+\tstop_clock(dev, ctx);\n }\n \n static void rpivid_buf_queue(struct vb2_buffer *vb)\n@@ -622,7 +677,7 @@ int rpivid_queue_init(void *priv, struct\n \tsrc_vq->ops = &rpivid_qops;\n \tsrc_vq->mem_ops = &vb2_dma_contig_memops;\n \tsrc_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;\n-\tsrc_vq->lock = &ctx->dev->dev_mutex;\n+\tsrc_vq->lock = &ctx->ctx_mutex;\n \tsrc_vq->dev = ctx->dev->dev;\n \tsrc_vq->supports_requests = true;\n \tsrc_vq->requires_requests = true;\n@@ -639,7 +694,7 @@ int rpivid_queue_init(void *priv, struct\n \tdst_vq->ops = &rpivid_qops;\n \tdst_vq->mem_ops = &vb2_dma_contig_memops;\n \tdst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;\n-\tdst_vq->lock = &ctx->dev->dev_mutex;\n+\tdst_vq->lock = &ctx->ctx_mutex;\n \tdst_vq->dev = ctx->dev->dev;\n \n \treturn vb2_queue_init(dst_vq);\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0618-media-rpivid-Improve-SPS-PPS-error-handling-validati.patch",
    "content": "From f30e24aa4a64cb6c341140270b74357505a20d4f Mon Sep 17 00:00:00 2001\nFrom: John Cox <jc@kynesim.co.uk>\nDate: Thu, 8 Apr 2021 18:34:09 +0100\nSubject: [PATCH] media: rpivid: Improve SPS/PPS error\n handling/validation\n\nMove size and width checking from bitstream processing to control\nvalidation\n\nSigned-off-by: John Cox <jc@kynesim.co.uk>\n---\n drivers/staging/media/rpivid/rpivid.c      |   5 +-\n drivers/staging/media/rpivid/rpivid.h      |   6 +-\n drivers/staging/media/rpivid/rpivid_h265.c | 132 ++++++++++++++++++---\n 3 files changed, 121 insertions(+), 22 deletions(-)\n\n--- a/drivers/staging/media/rpivid/rpivid.c\n+++ b/drivers/staging/media/rpivid/rpivid.c\n@@ -38,12 +38,14 @@ static const struct rpivid_control rpivi\n \t{\n \t\t.cfg = {\n \t\t\t.id\t= V4L2_CID_MPEG_VIDEO_HEVC_SPS,\n+\t\t\t.ops\t= &rpivid_hevc_sps_ctrl_ops,\n \t\t},\n \t\t.required\t= true,\n \t},\n \t{\n \t\t.cfg = {\n \t\t\t.id\t= V4L2_CID_MPEG_VIDEO_HEVC_PPS,\n+\t\t\t.ops\t= &rpivid_hevc_pps_ctrl_ops,\n \t\t},\n \t\t.required\t= true,\n \t},\n@@ -119,7 +121,7 @@ static int rpivid_init_ctrls(struct rpiv\n \n \tfor (i = 0; i < rpivid_ctrls_COUNT; i++) {\n \t\tctrl = v4l2_ctrl_new_custom(hdl, &rpivid_ctrls[i].cfg,\n-\t\t\t\t\t    NULL);\n+\t\t\t\t\t    ctx);\n \t\tif (hdl->error) {\n \t\t\tv4l2_err(&dev->v4l2_dev,\n \t\t\t\t \"Failed to create new custom control id=%#x\\n\",\n@@ -191,6 +193,7 @@ static int rpivid_request_validate(struc\n \t\tif (!ctrl_test) {\n \t\t\tv4l2_info(&ctx->dev->v4l2_dev,\n \t\t\t\t  \"Missing required codec control\\n\");\n+\t\t\tv4l2_ctrl_request_hdl_put(hdl);\n \t\t\treturn -ENOENT;\n \t\t}\n \t}\n--- a/drivers/staging/media/rpivid/rpivid.h\n+++ b/drivers/staging/media/rpivid/rpivid.h\n@@ -185,7 +185,7 @@ struct rpivid_dev {\n \tstruct platform_device\t*pdev;\n \tstruct device\t\t*dev;\n \tstruct v4l2_m2m_dev\t*m2m_dev;\n-\tstruct rpivid_dec_ops\t*dec_ops;\n+\tconst struct rpivid_dec_ops *dec_ops;\n \n \t/* Device file mutex */\n \tstruct mutex\t\tdev_mutex;\n@@ -201,7 +201,9 @@ struct rpivid_dev {\n \tstruct rpivid_hw_irq_ctrl ic_active2;\n };\n \n-extern struct rpivid_dec_ops rpivid_dec_ops_h265;\n+extern const struct rpivid_dec_ops rpivid_dec_ops_h265;\n+extern const struct v4l2_ctrl_ops rpivid_hevc_sps_ctrl_ops;\n+extern const struct v4l2_ctrl_ops rpivid_hevc_pps_ctrl_ops;\n \n struct v4l2_ctrl *rpivid_find_ctrl(struct rpivid_ctx *ctx, u32 id);\n void *rpivid_find_control_data(struct rpivid_ctx *ctx, u32 id);\n--- a/drivers/staging/media/rpivid/rpivid_h265.c\n+++ b/drivers/staging/media/rpivid/rpivid_h265.c\n@@ -1432,9 +1432,13 @@ static int updated_ps(struct rpivid_dec_\n \ts->ctb_addr_rs_to_ts = kmalloc_array(s->ctb_size,\n \t\t\t\t\t     sizeof(*s->ctb_addr_rs_to_ts),\n \t\t\t\t\t     GFP_KERNEL);\n+\tif (!s->ctb_addr_rs_to_ts)\n+\t\tgoto fail;\n \ts->ctb_addr_ts_to_rs = kmalloc_array(s->ctb_size,\n \t\t\t\t\t     sizeof(*s->ctb_addr_ts_to_rs),\n \t\t\t\t\t     GFP_KERNEL);\n+\tif (!s->ctb_addr_ts_to_rs)\n+\t\tgoto fail;\n \n \tif (!(s->pps.flags & V4L2_HEVC_PPS_FLAG_TILES_ENABLED)) {\n \t\ts->tile_width = 1;\n@@ -1446,8 +1450,12 @@ static int updated_ps(struct rpivid_dec_\n \n \ts->col_bd = kmalloc((s->tile_width + 1) * sizeof(*s->col_bd),\n \t\t\t    GFP_KERNEL);\n+\tif (!s->col_bd)\n+\t\tgoto fail;\n \ts->row_bd = kmalloc((s->tile_height + 1) * sizeof(*s->row_bd),\n \t\t\t    GFP_KERNEL);\n+\tif (!s->row_bd)\n+\t\tgoto fail;\n \n \ts->col_bd[0] = 0;\n \tfor (i = 1; i < s->tile_width; i++)\n@@ -1462,8 +1470,13 @@ static int updated_ps(struct rpivid_dec_\n \ts->row_bd[s->tile_height] = s->ctb_height;\n \n \tfill_rs_to_ts(s);\n-\n \treturn 0;\n+\n+fail:\n+\tfree_ps_info(s);\n+\t/* Set invalid to force reload */\n+\ts->sps.pic_width_in_luma_samples = 0;\n+\treturn -ENOMEM;\n }\n \n static int write_cmd_buffer(struct rpivid_dev *const dev,\n@@ -1694,7 +1707,9 @@ static void rpivid_h265_setup(struct rpi\n \t\t\tmemcpy(&s->pps, run->h265.pps, sizeof(s->pps));\n \n \t\t\t/* Recalc stuff as required */\n-\t\t\tupdated_ps(s);\n+\t\t\trv = updated_ps(s);\n+\t\t\tif (rv)\n+\t\t\t\tgoto fail;\n \t\t}\n \n \t\tde = dec_env_new(ctx);\n@@ -1772,22 +1787,6 @@ static void rpivid_h265_setup(struct rpi\n \t\t\tgoto fail;\n \t\t}\n \n-\t\tif (s->sps.pic_width_in_luma_samples > 4096 ||\n-\t\t    s->sps.pic_height_in_luma_samples > 4096) {\n-\t\t\tv4l2_warn(&dev->v4l2_dev,\n-\t\t\t\t  \"Pic dimension (%dx%d) exeeds 4096\\n\",\n-\t\t\t\t  s->sps.pic_width_in_luma_samples,\n-\t\t\t\t  s->sps.pic_height_in_luma_samples);\n-\t\t\tgoto fail;\n-\t\t}\n-\t\tif ((s->tile_width != 1 || s->tile_height != 1) &&\n-\t\t    (s->pps.flags &\n-\t\t     V4L2_HEVC_PPS_FLAG_ENTROPY_CODING_SYNC_ENABLED)) {\n-\t\t\tv4l2_warn(&dev->v4l2_dev,\n-\t\t\t\t  \"Tiles + WPP not supported\\n\");\n-\t\t\tgoto fail;\n-\t\t}\n-\n \t\t// Fill in ref planes with our address s.t. if we mess\n \t\t// up refs somehow then we still have a valid address\n \t\t// entry\n@@ -2515,9 +2514,104 @@ static void rpivid_h265_trigger(struct r\n \t}\n }\n \n-struct rpivid_dec_ops rpivid_dec_ops_h265 = {\n+const struct rpivid_dec_ops rpivid_dec_ops_h265 = {\n \t.setup = rpivid_h265_setup,\n \t.start = rpivid_h265_start,\n \t.stop = rpivid_h265_stop,\n \t.trigger = rpivid_h265_trigger,\n };\n+\n+static int try_ctrl_sps(struct v4l2_ctrl *ctrl)\n+{\n+\tconst struct v4l2_ctrl_hevc_sps *const sps = ctrl->p_new.p_hevc_sps;\n+\tstruct rpivid_ctx *const ctx = ctrl->priv;\n+\tstruct rpivid_dev *const dev = ctx->dev;\n+\n+\tif (sps->chroma_format_idc != 1) {\n+\t\tv4l2_warn(&dev->v4l2_dev,\n+\t\t\t  \"Chroma format (%d) unsupported\\n\",\n+\t\t\t  sps->chroma_format_idc);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (sps->bit_depth_luma_minus8 != 0 &&\n+\t    sps->bit_depth_luma_minus8 != 2) {\n+\t\tv4l2_warn(&dev->v4l2_dev,\n+\t\t\t  \"Luma depth (%d) unsupported\\n\",\n+\t\t\t  sps->bit_depth_luma_minus8 + 8);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (sps->bit_depth_luma_minus8 != sps->bit_depth_chroma_minus8) {\n+\t\tv4l2_warn(&dev->v4l2_dev,\n+\t\t\t  \"Chroma depth (%d) != Luma depth (%d)\\n\",\n+\t\t\t  sps->bit_depth_chroma_minus8 + 8,\n+\t\t\t  sps->bit_depth_luma_minus8 + 8);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (!sps->pic_width_in_luma_samples ||\n+\t    !sps->pic_height_in_luma_samples ||\n+\t    sps->pic_width_in_luma_samples > 4096 ||\n+\t    sps->pic_height_in_luma_samples > 4096) {\n+\t\tv4l2_warn(&dev->v4l2_dev,\n+\t\t\t  \"Bad sps width (%u) x height (%u)\\n\",\n+\t\t\t  sps->pic_width_in_luma_samples,\n+\t\t\t  sps->pic_height_in_luma_samples);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (!ctx->dst_fmt_set)\n+\t\treturn 0;\n+\n+\tif ((sps->bit_depth_luma_minus8 == 0 &&\n+\t     ctx->dst_fmt.pixelformat != V4L2_PIX_FMT_NV12_COL128) ||\n+\t    (sps->bit_depth_luma_minus8 == 2 &&\n+\t     ctx->dst_fmt.pixelformat != V4L2_PIX_FMT_NV12_10_COL128)) {\n+\t\tv4l2_warn(&dev->v4l2_dev,\n+\t\t\t  \"SPS luma depth %d does not match capture format\\n\",\n+\t\t\t  sps->bit_depth_luma_minus8 + 8);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (sps->pic_width_in_luma_samples > ctx->dst_fmt.width ||\n+\t    sps->pic_height_in_luma_samples > ctx->dst_fmt.height) {\n+\t\tv4l2_warn(&dev->v4l2_dev,\n+\t\t\t  \"SPS size (%dx%d) > capture size (%d,%d)\\n\",\n+\t\t\t  sps->pic_width_in_luma_samples,\n+\t\t\t  sps->pic_height_in_luma_samples,\n+\t\t\t  ctx->dst_fmt.width,\n+\t\t\t  ctx->dst_fmt.height);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+const struct v4l2_ctrl_ops rpivid_hevc_sps_ctrl_ops = {\n+\t.try_ctrl = try_ctrl_sps,\n+};\n+\n+static int try_ctrl_pps(struct v4l2_ctrl *ctrl)\n+{\n+\tconst struct v4l2_ctrl_hevc_pps *const pps = ctrl->p_new.p_hevc_pps;\n+\tstruct rpivid_ctx *const ctx = ctrl->priv;\n+\tstruct rpivid_dev *const dev = ctx->dev;\n+\n+\tif ((pps->flags &\n+\t     V4L2_HEVC_PPS_FLAG_ENTROPY_CODING_SYNC_ENABLED) &&\n+\t    (pps->flags &\n+\t     V4L2_HEVC_PPS_FLAG_TILES_ENABLED) &&\n+\t    (pps->num_tile_columns_minus1 || pps->num_tile_rows_minus1)) {\n+\t\tv4l2_warn(&dev->v4l2_dev,\n+\t\t\t  \"WPP + Tiles not supported\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+const struct v4l2_ctrl_ops rpivid_hevc_pps_ctrl_ops = {\n+\t.try_ctrl = try_ctrl_pps,\n+};\n+\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0619-overlays-add-sensirion-sgp30-to-i2c-sensor-overlay.patch",
    "content": "From 0fa1f65da585dae9cf4fce77f412eb129ac13da6 Mon Sep 17 00:00:00 2001\nFrom: Mehmet Ahsen <2084476+mehmetahsen@users.noreply.github.com>\nDate: Fri, 21 May 2021 00:14:29 +0200\nSubject: [PATCH] overlays: add sensirion sgp30 to i2c-sensor overlay\n\n---\n arch/arm/boot/dts/overlays/README                |  3 +++\n .../arm/boot/dts/overlays/i2c-sensor-overlay.dts | 16 ++++++++++++++++\n 2 files changed, 19 insertions(+)\n mode change 100644 => 100755 arch/arm/boot/dts/overlays/i2c-sensor-overlay.dts\n\n--- a/arch/arm/boot/dts/overlays/README\n+++ b/arch/arm/boot/dts/overlays/README\n@@ -1527,6 +1527,9 @@ Params: addr                    Set the\n         sps30                   Select the Sensirion SPS30 particulate matter\n                                 sensor. Fixed address 0x69.\n \n+        sgp30                   Select the Sensirion SGP30 VOC sensor.\n+                                Fixed address 0x58.\n+\n         tmp102                  Select the Texas Instruments TMP102 temp sensor\n                                 Valid addresses 0x48-0x4b, default 0x48\n \n--- a/arch/arm/boot/dts/overlays/i2c-sensor-overlay.dts\n+++ b/arch/arm/boot/dts/overlays/i2c-sensor-overlay.dts\n@@ -246,6 +246,21 @@\n \t\t};\n \t};\n \n+\tfragment@16 {\n+\t\ttarget = <&i2c_arm>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tsgp30: sgp30@58 {\n+\t\t\t\tcompatible = \"sensirion,sgp30\";\n+\t\t\t\treg = <0x58>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n \t__overrides__ {\n \t\taddr =  <&bme280>,\"reg:0\", <&bmp280>,\"reg:0\", <&tmp102>,\"reg:0\",\n \t\t\t<&lm75>,\"reg:0\", <&hdc100x>,\"reg:0\", <&sht3x>,\"reg:0\",\n@@ -267,5 +282,6 @@\n \t\tmax17040 = <0>,\"+13\";\n \t\tbme680 = <0>,\"+14\";\n \t\tsps30 = <0>,\"+15\";\n+\t\tsgp30 = <0>,\"+16\";\n \t};\n };\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0620-overlays-Remove-deleted-merus-amp-parameter.patch",
    "content": "From 10db150791a90ab672767c2a44cb68455c2b8776 Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.com>\nDate: Fri, 21 May 2021 11:29:52 +0100\nSubject: [PATCH] overlays: Remove deleted merus-amp parameter\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.com>\n---\n arch/arm/boot/dts/overlays/README | 4 ++--\n 1 file changed, 2 insertions(+), 2 deletions(-)\n\n--- a/arch/arm/boot/dts/overlays/README\n+++ b/arch/arm/boot/dts/overlays/README\n@@ -2010,8 +2010,8 @@ Params: speed                   Display\n \n Name:   merus-amp\n Info:   Configures the merus-amp audio card\n-Load:   dtoverlay=merus-amp,<param>=<val>\n-Params: spioff                  Turn SPI bus off\n+Load:   dtoverlay=merus-amp\n+Params: <None>\n \n \n Name:   midi-uart0\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0621-overlays-add-bh1750-and-ccs811-to-i2c-sensor-4334.patch",
    "content": "From fa6a21d6e2e8d5416ec9d2ca7841777aa0822796 Mon Sep 17 00:00:00 2001\nFrom: Mart Lubbers <mart@martlubbers.net>\nDate: Tue, 11 May 2021 11:51:35 +0200\nSubject: [PATCH] overlays: add bh1750 and ccs811 to i2c-sensor (#4334)\n\nSee: https://github.com/raspberrypi/linux/pull/4334\n---\n arch/arm/boot/dts/overlays/README             | 15 +++++---\n .../boot/dts/overlays/i2c-sensor-overlay.dts  | 35 ++++++++++++++++++-\n 2 files changed, 45 insertions(+), 5 deletions(-)\n\n--- a/arch/arm/boot/dts/overlays/README\n+++ b/arch/arm/boot/dts/overlays/README\n@@ -1482,11 +1482,15 @@ Params: abx80x                  Select o\n \n \n Name:   i2c-sensor\n-Info:   Adds support for a number of I2C barometric pressure and temperature\n-        sensors on i2c_arm\n+Info:   Adds support for a number of I2C barometric pressure, temperature,\n+        light level and chemical sensors on i2c_arm\n Load:   dtoverlay=i2c-sensor,<param>=<val>\n-Params: addr                    Set the address for the BME280, BME680, BMP280,\n-                                DS1621, HDC100X, LM75, SHT3x or TMP102\n+Params: addr                    Set the address for the BH1750, BME280, BME680,\n+                                BMP280, CCS811, DS1621, HDC100X, LM75, SHT3x or\n+                                TMP102\n+\n+        bh1750                  Select the Rohm BH1750 ambient light sensor\n+                                Valid addresses 0x23 or 0x5c, default 0x23\n \n         bme280                  Select the Bosch Sensortronic BME280\n                                 Valid addresses 0x76-0x77, default 0x76\n@@ -1501,6 +1505,9 @@ Params: addr                    Set the\n         bmp280                  Select the Bosch Sensortronic BMP280\n                                 Valid addresses 0x76-0x77, default 0x76\n \n+        ccs811                  Select the AMS CCS811 digital gas sensor\n+                                Valid addresses 0x5a-0x5b, default 0x5b\n+\n         ds1621                  Select the Dallas Semiconductors DS1621 temp\n                                 sensor. Valid addresses 0x48-0x4f, default 0x48\n \n--- a/arch/arm/boot/dts/overlays/i2c-sensor-overlay.dts\n+++ b/arch/arm/boot/dts/overlays/i2c-sensor-overlay.dts\n@@ -261,10 +261,41 @@\n \t\t};\n \t};\n \n+\tfragment@17 {\n+\t\ttarget = <&i2c_arm>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tccs811: ccs811@5b {\n+\t\t\t\tcompatible = \"ccs811\";\n+\t\t\t\treg = <0x5b>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@18 {\n+\t\ttarget = <&i2c_arm>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tbh1750: bh1750@23 {\n+\t\t\t\tcompatible = \"bh1750\";\n+\t\t\t\treg = <0x23>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n \t__overrides__ {\n \t\taddr =  <&bme280>,\"reg:0\", <&bmp280>,\"reg:0\", <&tmp102>,\"reg:0\",\n \t\t\t<&lm75>,\"reg:0\", <&hdc100x>,\"reg:0\", <&sht3x>,\"reg:0\",\n-\t\t\t<&ds1621>,\"reg:0\", <&bme680>,\"reg:0\";\n+\t\t\t<&ds1621>,\"reg:0\", <&bme680>,\"reg:0\", <&ccs811>,\"reg:0\",\n+\t\t\t<&bh1750>,\"reg:0\";\n \t\tbme280 = <0>,\"+0\";\n \t\tbmp085 = <0>,\"+1\";\n \t\tbmp180 = <0>,\"+2\";\n@@ -283,5 +314,7 @@\n \t\tbme680 = <0>,\"+14\";\n \t\tsps30 = <0>,\"+15\";\n \t\tsgp30 = <0>,\"+16\";\n+\t\tccs811 = <0>, \"+17\";\n+\t\tbh1750 = <0>, \"+18\";\n \t};\n };\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0622-Add-Raspberry-Pi-PoE-HAT-support.patch",
    "content": "From 2150bf813a64c18cdc56ae6b84036377c242cebd Mon Sep 17 00:00:00 2001\nFrom: Serge Schneider <serge@raspberrypi.com>\nDate: Mon, 2 Dec 2019 14:48:05 +0000\nSubject: [PATCH] Add Raspberry Pi PoE+ HAT support\n\nSigned-off-by: Serge Schneider <serge@raspberrypi.com>\n---\n drivers/hwmon/rpi-poe-fan.c                |  35 +++-\n drivers/power/supply/Kconfig               |   6 +\n drivers/power/supply/Makefile              |   1 +\n drivers/power/supply/rpi_poe_power.c       | 227 +++++++++++++++++++++\n include/soc/bcm2835/raspberrypi-firmware.h |   3 +-\n 5 files changed, 261 insertions(+), 11 deletions(-)\n create mode 100644 drivers/power/supply/rpi_poe_power.c\n\n--- a/drivers/hwmon/rpi-poe-fan.c\n+++ b/drivers/hwmon/rpi-poe-fan.c\n@@ -28,6 +28,7 @@\n struct rpi_poe_fan_ctx {\n \tstruct mutex lock;\n \tstruct rpi_firmware *fw;\n+\tu32 set_tag;\n \tunsigned int pwm_value;\n \tunsigned int def_pwm_value;\n \tunsigned int rpi_poe_fan_state;\n@@ -43,13 +44,15 @@ struct fw_tag_data_s{\n \tu32 ret;\n };\n \n-static int write_reg(struct rpi_firmware *fw, u32 reg, u32 *val){\n+static int write_reg(struct rpi_firmware *fw, u32 reg, u32 *val, u32 set_tag)\n+{\n \tstruct fw_tag_data_s fw_tag_data = {\n \t\t.reg = reg,\n \t\t.val = *val\n \t};\n \tint ret;\n-\tret = rpi_firmware_property(fw, RPI_FIRMWARE_SET_POE_HAT_VAL,\n+\n+\tret = rpi_firmware_property(fw, set_tag,\n \t\t\t\t    &fw_tag_data, sizeof(fw_tag_data));\n \tif (ret) {\n \t\treturn ret;\n@@ -82,7 +85,7 @@ static int rpi_poe_reboot(struct notifie\n \t\t\t\t\t\t   nb);\n \n \tif (ctx->pwm_value != ctx->def_pwm_value)\n-\t\twrite_reg(ctx->fw, POE_CUR_PWM, &ctx->def_pwm_value);\n+\t\twrite_reg(ctx->fw, POE_CUR_PWM, &ctx->def_pwm_value, ctx->set_tag);\n \n \treturn NOTIFY_DONE;\n }\n@@ -95,7 +98,7 @@ static int  __set_pwm(struct rpi_poe_fan\n \tif (ctx->pwm_value == pwm)\n \t\tgoto exit_set_pwm_err;\n \n-\tret = write_reg(ctx->fw, POE_CUR_PWM, &pwm);\n+\tret = write_reg(ctx->fw, POE_CUR_PWM, &pwm, ctx->set_tag);\n \tif (!ret)\n \t\tctx->pwm_value = pwm;\n exit_set_pwm_err:\n@@ -110,7 +113,7 @@ static int  __set_def_pwm(struct rpi_poe\n \tif (ctx->def_pwm_value == def_pwm)\n \t\tgoto exit_set_def_pwm_err;\n \n-\tret = write_reg(ctx->fw, POE_DEF_PWM, &def_pwm);\n+\tret = write_reg(ctx->fw, POE_DEF_PWM, &def_pwm, ctx->set_tag);\n \tif (!ret)\n \t\tctx->def_pwm_value = def_pwm;\n exit_set_def_pwm_err:\n@@ -297,6 +300,7 @@ static int rpi_poe_fan_probe(struct plat\n \tstruct device *hwmon;\n \tstruct device_node *np = pdev->dev.of_node;\n \tstruct device_node *fw_node;\n+\tu32 revision;\n \tint ret;\n \n \tfw_node = of_parse_phandle(np, \"firmware\", 0);\n@@ -314,6 +318,17 @@ static int rpi_poe_fan_probe(struct plat\n \tctx->fw = rpi_firmware_get(fw_node);\n \tif (!ctx->fw)\n \t\treturn -EPROBE_DEFER;\n+\tret = rpi_firmware_property(ctx->fw,\n+\t\tRPI_FIRMWARE_GET_FIRMWARE_REVISION,\n+\t\t&revision, sizeof(revision));\n+\tif (ret) {\n+\t\tdev_err(&pdev->dev, \"Failed to get firmware revision: %i\\n\", ret);\n+\t\treturn ret;\n+\t}\n+\tif (revision < 0x60af72e8)\n+\t\tctx->set_tag = RPI_FIRMWARE_SET_POE_HAT_VAL_OLD;\n+\telse\n+\t\tctx->set_tag = RPI_FIRMWARE_SET_POE_HAT_VAL;\n \n \tplatform_set_drvdata(pdev, ctx);\n \n@@ -378,9 +393,9 @@ static int rpi_poe_fan_remove(struct pla\n \n \tunregister_reboot_notifier(&ctx->nb);\n \tthermal_cooling_device_unregister(ctx->cdev);\n-\tif (ctx->pwm_value != value) {\n-\t\twrite_reg(ctx->fw, POE_CUR_PWM, &value);\n-\t}\n+\tif (ctx->pwm_value != value)\n+\t\twrite_reg(ctx->fw, POE_CUR_PWM, &value, ctx->set_tag);\n+\n \treturn 0;\n }\n \n@@ -392,7 +407,7 @@ static int rpi_poe_fan_suspend(struct de\n \tint ret = 0;\n \n \tif (ctx->pwm_value != value)\n-\t\tret = write_reg(ctx->fw, POE_CUR_PWM, &value);\n+\t\tret = write_reg(ctx->fw, POE_CUR_PWM, &value, ctx->set_tag);\n \treturn ret;\n }\n \n@@ -403,7 +418,7 @@ static int rpi_poe_fan_resume(struct dev\n \tint ret = 0;\n \n \tif (value != 0)\n-\t\tret = write_reg(ctx->fw, POE_CUR_PWM, &value);\n+\t\tret = write_reg(ctx->fw, POE_CUR_PWM, &value, ctx->set_tag);\n \n \treturn ret;\n }\n--- a/drivers/power/supply/Kconfig\n+++ b/drivers/power/supply/Kconfig\n@@ -28,6 +28,12 @@ config POWER_SUPPLY_HWMON\n \t  Say 'Y' here if you want power supplies to\n \t  have hwmon sysfs interface too.\n \n+config RPI_POE_POWER\n+\ttristate \"Raspberry Pi PoE+ HAT power supply driver\"\n+\tdepends on RASPBERRYPI_FIRMWARE\n+\thelp\n+\t  Say Y here to enable support for Raspberry Pi PoE+ (Power over Ethernet\n+\t  Plus) HAT current measurement.\n \n config PDA_POWER\n \ttristate \"Generic PDA/phone power driver\"\n--- a/drivers/power/supply/Makefile\n+++ b/drivers/power/supply/Makefile\n@@ -9,6 +9,7 @@ obj-$(CONFIG_POWER_SUPPLY)\t+= power_supp\n obj-$(CONFIG_POWER_SUPPLY_HWMON) += power_supply_hwmon.o\n obj-$(CONFIG_GENERIC_ADC_BATTERY)\t+= generic-adc-battery.o\n \n+obj-$(CONFIG_RPI_POE_POWER)\t+= rpi_poe_power.o\n obj-$(CONFIG_PDA_POWER)\t\t+= pda_power.o\n obj-$(CONFIG_APM_POWER)\t\t+= apm_power.o\n obj-$(CONFIG_AXP20X_POWER)\t+= axp20x_usb_power.o\n--- /dev/null\n+++ b/drivers/power/supply/rpi_poe_power.c\n@@ -0,0 +1,227 @@\n+// SPDX-License-Identifier: GPL-2.0\n+/*\n+ * rpi-poe-power.c - Raspberry Pi PoE+ HAT power supply driver.\n+ *\n+ * Copyright (C) 2019 Raspberry Pi (Trading) Ltd.\n+ * Based on axp20x_ac_power.c by Quentin Schulz <quentin.schulz@free-electrons.com>\n+ *\n+ * Author: Serge Schneider <serge@raspberrypi.org>\n+ */\n+\n+#include <linux/module.h>\n+#include <linux/of.h>\n+#include <linux/platform_device.h>\n+#include <linux/power_supply.h>\n+#include <soc/bcm2835/raspberrypi-firmware.h>\n+\n+#define RPI_POE_ADC_REG\t\t\t0x2\n+#define RPI_POE_FLAG_REG\t\t0x4\n+\n+#define RPI_POE_FLAG_AT\t\t\tBIT(0)\n+#define RPI_POE_FLAG_OC\t\t\tBIT(1)\n+\n+#define RPI_POE_CURRENT_AF_MAX\t(2500 * 1000)\n+#define RPI_POE_CURRENT_AT_MAX\t(5000 * 1000)\n+\n+#define DRVNAME \"rpi-poe-power-supply\"\n+\n+struct rpi_poe_power_supply_ctx {\n+\tstruct power_supply *supply;\n+\tstruct rpi_firmware *fw;\n+};\n+\n+struct fw_tag_data_s {\n+\tu32 reg;\n+\tu32 val;\n+\tu32 ret;\n+};\n+\n+static int write_reg(struct rpi_firmware *fw, u32 reg, u32 *val)\n+{\n+\tstruct fw_tag_data_s fw_tag_data = {\n+\t\t.reg = reg,\n+\t\t.val = *val\n+\t};\n+\tint ret;\n+\n+\tret = rpi_firmware_property(fw, RPI_FIRMWARE_SET_POE_HAT_VAL,\n+\t\t\t\t    &fw_tag_data, sizeof(fw_tag_data));\n+\tif (ret)\n+\t\treturn ret;\n+\telse if (fw_tag_data.ret)\n+\t\treturn -EIO;\n+\treturn 0;\n+}\n+\n+static int read_reg(struct rpi_firmware *fw, u32 reg, u32 *val)\n+{\n+\tstruct fw_tag_data_s fw_tag_data = {\n+\t\t.reg = reg,\n+\t\t.val = *val\n+\t};\n+\tint ret;\n+\n+\tret = rpi_firmware_property(fw, RPI_FIRMWARE_GET_POE_HAT_VAL,\n+\t\t\t\t    &fw_tag_data, sizeof(fw_tag_data));\n+\tif (ret)\n+\t\treturn ret;\n+\telse if (fw_tag_data.ret)\n+\t\treturn -EIO;\n+\n+\t*val = fw_tag_data.val;\n+\treturn 0;\n+}\n+\n+static int rpi_poe_power_supply_get_property(struct power_supply *psy,\n+\t\t\t\t\tenum power_supply_property psp,\n+\t\t\t\t\tunion power_supply_propval *r_val)\n+{\n+\tstruct rpi_poe_power_supply_ctx *ctx = power_supply_get_drvdata(psy);\n+\tint ret;\n+\tunsigned int val = 0;\n+\n+\tswitch (psp) {\n+\tcase POWER_SUPPLY_PROP_HEALTH:\n+\t\tret = read_reg(ctx->fw, RPI_POE_FLAG_REG, &val);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\n+\t\tif (val & RPI_POE_FLAG_OC) {\n+\t\t\tr_val->intval = POWER_SUPPLY_HEALTH_UNSPEC_FAILURE;\n+\t\t\tval = RPI_POE_FLAG_OC;\n+\t\t\tret = write_reg(ctx->fw, RPI_POE_FLAG_REG, &val);\n+\t\t\tif (ret)\n+\t\t\t\treturn ret;\n+\t\t\treturn 0;\n+\t\t}\n+\n+\t\tr_val->intval = POWER_SUPPLY_HEALTH_GOOD;\n+\t\treturn 0;\n+\n+\tcase POWER_SUPPLY_PROP_ONLINE:\n+\t\tret = read_reg(ctx->fw, RPI_POE_ADC_REG, &val);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\n+\t\tr_val->intval = (val > 5);\n+\t\treturn 0;\n+\n+\tcase POWER_SUPPLY_PROP_CURRENT_AVG:\n+\t\tval = 50;\n+\t\tret = read_reg(ctx->fw, RPI_POE_ADC_REG, &val);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\t\tval = (val * 3300)/9821;\n+\t\tr_val->intval = val * 1000;\n+\t\treturn 0;\n+\n+\tcase POWER_SUPPLY_PROP_CURRENT_NOW:\n+\t\tret = read_reg(ctx->fw, RPI_POE_ADC_REG, &val);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\t\tval = (val * 3300)/9821;\n+\t\tr_val->intval = val * 1000;\n+\t\treturn 0;\n+\n+\tcase POWER_SUPPLY_PROP_CURRENT_MAX:\n+\t\tret = read_reg(ctx->fw, RPI_POE_FLAG_REG, &val);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\n+\t\tif (val & RPI_POE_FLAG_AT) {\n+\t\t\tr_val->intval = RPI_POE_CURRENT_AT_MAX;\n+\t\t\treturn 0;\n+\t\t}\n+\t\tr_val->intval = RPI_POE_CURRENT_AF_MAX;\n+\t\treturn 0;\n+\n+\tdefault:\n+\t\treturn -EINVAL;\n+\t}\n+\n+\treturn -EINVAL;\n+}\n+\n+static enum power_supply_property rpi_poe_power_supply_properties[] = {\n+\tPOWER_SUPPLY_PROP_HEALTH,\n+\tPOWER_SUPPLY_PROP_ONLINE,\n+\tPOWER_SUPPLY_PROP_CURRENT_AVG,\n+\tPOWER_SUPPLY_PROP_CURRENT_NOW,\n+\tPOWER_SUPPLY_PROP_CURRENT_MAX,\n+};\n+\n+static const struct power_supply_desc rpi_poe_power_supply_desc = {\n+\t.name = \"rpi-poe\",\n+\t.type = POWER_SUPPLY_TYPE_MAINS,\n+\t.properties = rpi_poe_power_supply_properties,\n+\t.num_properties = ARRAY_SIZE(rpi_poe_power_supply_properties),\n+\t.get_property = rpi_poe_power_supply_get_property,\n+};\n+\n+static int rpi_poe_power_supply_probe(struct platform_device *pdev)\n+{\n+\tstruct power_supply_config psy_cfg = {};\n+\tstruct rpi_poe_power_supply_ctx *ctx;\n+\tstruct device_node *fw_node;\n+\tu32 revision;\n+\n+\tif (!of_device_is_available(pdev->dev.of_node))\n+\t\treturn -ENODEV;\n+\n+\tfw_node = of_parse_phandle(pdev->dev.of_node, \"firmware\", 0);\n+\tif (!fw_node) {\n+\t\tdev_err(&pdev->dev, \"Missing firmware node\\n\");\n+\t\treturn -ENOENT;\n+\t}\n+\n+\tctx = devm_kzalloc(&pdev->dev, sizeof(*ctx), GFP_KERNEL);\n+\tif (!ctx)\n+\t\treturn -ENOMEM;\n+\n+\tctx->fw = rpi_firmware_get(fw_node);\n+\tif (!ctx->fw)\n+\t\treturn -EPROBE_DEFER;\n+\tif (rpi_firmware_property(ctx->fw,\n+\t\t\tRPI_FIRMWARE_GET_FIRMWARE_REVISION,\n+\t\t\t&revision, sizeof(revision))) {\n+\t\tdev_err(&pdev->dev, \"Failed to get firmware revision\\n\");\n+\t\treturn -ENOENT;\n+\t}\n+\tif (revision < 0x60af72e8) {\n+\t\tdev_err(&pdev->dev, \"Unsupported firmware\\n\");\n+\t\treturn -ENOENT;\n+\t}\n+\tplatform_set_drvdata(pdev, ctx);\n+\n+\tpsy_cfg.of_node = pdev->dev.of_node;\n+\tpsy_cfg.drv_data = ctx;\n+\n+\tctx->supply = devm_power_supply_register(&pdev->dev,\n+\t\t\t\t\t\t   &rpi_poe_power_supply_desc,\n+\t\t\t\t\t\t   &psy_cfg);\n+\tif (IS_ERR(ctx->supply))\n+\t\treturn PTR_ERR(ctx->supply);\n+\n+\treturn 0;\n+}\n+\n+static const struct of_device_id of_rpi_poe_power_supply_match[] = {\n+\t{ .compatible = \"raspberrypi,rpi-poe-power-supply\", },\n+\t{ /* sentinel */ }\n+};\n+MODULE_DEVICE_TABLE(of, of_rpi_poe_power_supply_match);\n+\n+static struct platform_driver rpi_poe_power_supply_driver = {\n+\t.probe = rpi_poe_power_supply_probe,\n+\t.driver = {\n+\t\t.name = DRVNAME,\n+\t\t.of_match_table = of_rpi_poe_power_supply_match\n+\t},\n+};\n+\n+module_platform_driver(rpi_poe_power_supply_driver);\n+\n+MODULE_AUTHOR(\"Serge Schneider <serge@raspberrypi.org>\");\n+MODULE_ALIAS(\"platform:\" DRVNAME);\n+MODULE_DESCRIPTION(\"Raspberry Pi PoE+ HAT power supply driver\");\n+MODULE_LICENSE(\"GPL\");\n--- a/include/soc/bcm2835/raspberrypi-firmware.h\n+++ b/include/soc/bcm2835/raspberrypi-firmware.h\n@@ -94,7 +94,8 @@ enum rpi_firmware_property_tag {\n \tRPI_FIRMWARE_GET_PERIPH_REG =                         0x00030045,\n \tRPI_FIRMWARE_SET_PERIPH_REG =                         0x00038045,\n \tRPI_FIRMWARE_GET_POE_HAT_VAL =                        0x00030049,\n-\tRPI_FIRMWARE_SET_POE_HAT_VAL =                        0x00030050,\n+\tRPI_FIRMWARE_SET_POE_HAT_VAL =                        0x00038049,\n+\tRPI_FIRMWARE_SET_POE_HAT_VAL_OLD =                    0x00030050,\n \tRPI_FIRMWARE_NOTIFY_XHCI_RESET =                      0x00030058,\n \tRPI_FIRMWARE_GET_REBOOT_FLAGS =                       0x00030064,\n \tRPI_FIRMWARE_SET_REBOOT_FLAGS =                       0x00038064,\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0623-overlays-Add-rpi-poe-plus-overlay.patch",
    "content": "From 022c80564d30bba83b82a0ccdff74648e47862dd Mon Sep 17 00:00:00 2001\nFrom: Serge Schneider <serge@raspberrypi.com>\nDate: Mon, 2 Dec 2019 14:48:05 +0000\nSubject: [PATCH] overlays: Add rpi-poe-plus overlay\n\nSigned-off-by: Serge Schneider <serge@raspberrypi.com>\n---\n arch/arm/boot/dts/overlays/Makefile           |  1 +\n arch/arm/boot/dts/overlays/README             | 21 +++++++++++++++++++\n .../dts/overlays/rpi-poe-plus-overlay.dts     | 19 +++++++++++++++++\n 3 files changed, 41 insertions(+)\n create mode 100644 arch/arm/boot/dts/overlays/rpi-poe-plus-overlay.dts\n\n--- a/arch/arm/boot/dts/overlays/Makefile\n+++ b/arch/arm/boot/dts/overlays/Makefile\n@@ -156,6 +156,7 @@ dtbo-$(CONFIG_ARCH_BCM2835) += \\\n \trpi-display.dtbo \\\n \trpi-ft5406.dtbo \\\n \trpi-poe.dtbo \\\n+\trpi-poe-plus.dtbo \\\n \trpi-proto.dtbo \\\n \trpi-sense.dtbo \\\n \trpi-tv.dtbo \\\n--- a/arch/arm/boot/dts/overlays/README\n+++ b/arch/arm/boot/dts/overlays/README\n@@ -2505,6 +2505,27 @@ Params: poe_fan_temp0           Temperat\n                                 the fan slows down (default 5000)\n \n \n+Name:   rpi-poe-plus\n+Info:   Raspberry Pi PoE+ HAT fan\n+Load:   dtoverlay=rpi-poe-plus,<param>[=<val>]\n+Params: poe_fan_temp0           Temperature (in millicelcius) at which the fan\n+                                turns on (default 40000)\n+        poe_fan_temp0_hyst      Temperature delta (in millicelcius) at which\n+                                the fan turns off (default 2000)\n+        poe_fan_temp1           Temperature (in millicelcius) at which the fan\n+                                speeds up (default 45000)\n+        poe_fan_temp1_hyst      Temperature delta (in millicelcius) at which\n+                                the fan slows down (default 2000)\n+        poe_fan_temp2           Temperature (in millicelcius) at which the fan\n+                                speeds up (default 50000)\n+        poe_fan_temp2_hyst      Temperature delta (in millicelcius) at which\n+                                the fan slows down (default 2000)\n+        poe_fan_temp3           Temperature (in millicelcius) at which the fan\n+                                speeds up (default 55000)\n+        poe_fan_temp3_hyst      Temperature delta (in millicelcius) at which\n+                                the fan slows down (default 5000)\n+\n+\n Name:   rpi-proto\n Info:   Configures the RPi Proto audio card\n Load:   dtoverlay=rpi-proto\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/rpi-poe-plus-overlay.dts\n@@ -0,0 +1,19 @@\n+// SPDX-License-Identifier: (GPL-2.0 OR MIT)\n+// Overlay for the Raspberry Pi PoE+ HAT.\n+\n+#include \"rpi-poe-overlay.dts\"\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@3 {\n+\t\ttarget-path = \"/\";\n+\t\t__overlay__ {\n+\t\t\trpi_poe_power_supply: rpi-poe-power-supply@0 {\n+\t\t\t\tcompatible = \"raspberrypi,rpi-poe-power-supply\";\n+\t\t\t\tfirmware = <&firmware>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+};\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0624-drm-vc4-FKMS-Change-of-Broadcast-RGB-mode-needs-a-mo.patch",
    "content": "From caa5d5dac396f5bfaef8bd65c1c39f4ff03a504a Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Fri, 21 May 2021 11:15:04 +0100\nSubject: [PATCH] drm/vc4: FKMS: Change of Broadcast RGB mode needs a\n mode change\n\nThe Broadcast RGB (aka HDMI limited/full range) property is only\nnotified to the firmware on mode change, so this needs to be\nsignalled when set.\n\nhttps://github.com/raspberrypi/firmware/issues/1580\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n drivers/gpu/drm/vc4/vc4_firmware_kms.c | 29 ++++++++++++++++++++++++++\n 1 file changed, 29 insertions(+)\n\n--- a/drivers/gpu/drm/vc4/vc4_firmware_kms.c\n+++ b/drivers/gpu/drm/vc4/vc4_firmware_kms.c\n@@ -1549,6 +1549,34 @@ int vc4_connector_atomic_set_property(st\n \treturn -EINVAL;\n }\n \n+int vc4_connector_atomic_check(struct drm_connector *connector,\n+\t\t\t       struct drm_atomic_state *state)\n+{\n+\tstruct drm_connector_state *old_state =\n+\t\tdrm_atomic_get_old_connector_state(state, connector);\n+\tstruct vc4_fkms_connector_state *vc4_old_state =\n+\t\t\t\t\tto_vc4_fkms_connector_state(old_state);\n+\tstruct drm_connector_state *new_state =\n+\t\tdrm_atomic_get_new_connector_state(state, connector);\n+\tstruct vc4_fkms_connector_state *vc4_new_state =\n+\t\t\t\t\tto_vc4_fkms_connector_state(new_state);\n+\tstruct drm_crtc *crtc = new_state->crtc;\n+\n+\tif (!crtc)\n+\t\treturn 0;\n+\n+\tif (vc4_old_state->broadcast_rgb != vc4_new_state->broadcast_rgb) {\n+\t\tstruct drm_crtc_state *crtc_state;\n+\n+\t\tcrtc_state = drm_atomic_get_crtc_state(state, crtc);\n+\t\tif (IS_ERR(crtc_state))\n+\t\t\treturn PTR_ERR(crtc_state);\n+\n+\t\tcrtc_state->mode_changed = true;\n+\t}\n+\treturn 0;\n+}\n+\n static void vc4_hdmi_connector_reset(struct drm_connector *connector)\n {\n \tdrm_atomic_helper_connector_reset(connector);\n@@ -1569,6 +1597,7 @@ static const struct drm_connector_funcs\n static const struct drm_connector_helper_funcs vc4_fkms_connector_helper_funcs = {\n \t.get_modes = vc4_fkms_connector_get_modes,\n \t.best_encoder = vc4_fkms_connector_best_encoder,\n+\t.atomic_check = vc4_connector_atomic_check,\n };\n \n static const struct drm_connector_helper_funcs vc4_fkms_lcd_conn_helper_funcs = {\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0625-overlays-Add-ssd1331-spi-support-for-OLED-screen.patch",
    "content": "From 32a85be60c722eff17ccade5d3e12971aad15f61 Mon Sep 17 00:00:00 2001\nFrom: Alex Kurichenko <oleksandr.kurichenko@deluxe.com>\nDate: Tue, 1 Jun 2021 01:53:47 +0300\nSubject: [PATCH] overlays: Add ssd1331-spi support for OLED screen\n\nSigned-off-by: Alex Kurichenko <oleksandr.kurichenko@deluxe.com>\n---\n arch/arm/boot/dts/overlays/Makefile           |  1 +\n arch/arm/boot/dts/overlays/README             | 11 +++\n .../boot/dts/overlays/ssd1331-spi-overlay.dts | 83 +++++++++++++++++++\n 3 files changed, 95 insertions(+)\n create mode 100644 arch/arm/boot/dts/overlays/ssd1331-spi-overlay.dts\n\n--- a/arch/arm/boot/dts/overlays/Makefile\n+++ b/arch/arm/boot/dts/overlays/Makefile\n@@ -196,6 +196,7 @@ dtbo-$(CONFIG_ARCH_BCM2835) += \\\n \tspi6-2cs.dtbo \\\n \tssd1306.dtbo \\\n \tssd1306-spi.dtbo \\\n+\tssd1331-spi.dtbo \\\n \tssd1351-spi.dtbo \\\n \tsuperaudioboard.dtbo \\\n \tsx150x.dtbo \\\n--- a/arch/arm/boot/dts/overlays/README\n+++ b/arch/arm/boot/dts/overlays/README\n@@ -3015,6 +3015,17 @@ Params: speed                   SPI bus\n         height                  Display height (32 or 64; default 64)\n \n \n+Name:   ssd1331-spi\n+Info:   Overlay for SSD1331 OLED via SPI using fbtft staging driver.\n+Load:   dtoverlay=ssd1331-spi,<param>=<val>\n+Params: speed                   SPI bus speed (default 4500000)\n+        rotate                  Display rotation (0, 90, 180 or 270; default 0)\n+        fps                     Delay between frame updates (default 25)\n+        debug                   Debug output level (0-7; default 0)\n+        dc_pin                  GPIO pin for D/C (default 24)\n+        reset_pin               GPIO pin for RESET (default 25)\n+\n+\n Name:   ssd1351-spi\n Info:   Overlay for SSD1351 OLED via SPI using fbtft staging driver.\n Load:   dtoverlay=ssd1351-spi,<param>=<val>\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/ssd1331-spi-overlay.dts\n@@ -0,0 +1,83 @@\n+/*\n+ * Device Tree overlay for SSD1331 based SPI OLED display\n+ *\n+ */\n+\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+        compatible = \"brcm,bcm2835\";\n+\n+        fragment@0 {\n+                target = <&spi0>;\n+                __overlay__ {\n+                        status = \"okay\";\n+                };\n+        };\n+\n+        fragment@1 {\n+                target = <&spidev0>;\n+                __overlay__ {\n+                        status = \"disabled\";\n+                };\n+        };\n+\n+        fragment@2 {\n+                target = <&spidev1>;\n+                __overlay__ {\n+                        status = \"disabled\";\n+                };\n+        };\n+\n+        fragment@3 {\n+                target = <&gpio>;\n+                __overlay__ {\n+                        ssd1331_pins: ssd1331_pins {\n+                                brcm,pins = <25 24>;\n+                                brcm,function = <1 1>; /* out out */\n+                        };\n+                };\n+        };\n+\n+        fragment@4 {\n+                target = <&spi0>;\n+                __overlay__ {\n+                        /* needed to avoid dtc warning */\n+                        #address-cells = <1>;\n+                        #size-cells = <0>;\n+\n+                        ssd1331: ssd1331@0{\n+                                compatible = \"solomon,ssd1331\";\n+                                reg = <0>;\n+                                pinctrl-names = \"default\";\n+                                pinctrl-0 = <&ssd1331_pins>;\n+\n+                                spi-max-frequency = <4500000>;\n+                                bgr = <0>;\n+                                bpp = <16>;\n+                                rotate = <0>;\n+                                fps = <25>;\n+                                buswidth = <8>;\n+                                reset-gpios = <&gpio 25 1>;\n+                                dc-gpios = <&gpio 24 0>;\n+                                debug = <0>;\n+\n+                                solomon,height = <64>;\n+                                solomon,width = <96>;\n+                                solomon,page-offset = <0>;\n+                        };\n+                };\n+        };\n+\n+        __overrides__ {\n+                speed     = <&ssd1331>,\"spi-max-frequency:0\";\n+                rotate    = <&ssd1331>,\"rotate:0\";\n+                fps       = <&ssd1331>,\"fps:0\";\n+                debug     = <&ssd1331>,\"debug:0\";\n+                dc_pin    = <&ssd1331>,\"dc-gpios:4\",\n+                            <&ssd1331_pins>,\"brcm,pins:4\";\n+                reset_pin = <&ssd1331>,\"reset-gpios:4\",\n+                            <&ssd1331_pins>,\"brcm,pins:0\";\n+        };\n+};\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0626-Fixes-an-onboard-clock-detection-problem-of-the-PRO-.patch",
    "content": "From d2a6770500f0f284850834ec08fbee5fd6aaee3e Mon Sep 17 00:00:00 2001\nFrom: Joerg Schambacher <joerg@i2audio.com>\nDate: Thu, 10 Jun 2021 13:14:05 +0200\nSubject: [PATCH] Fixes an onboard clock detection problem of the PRO\n versions\n\nIncreasing the sleep time after clock selection to 3-4ms\nallows the correct detection of all combinations of DAC+ Pro\nand DAC+ADC Pro sound cards and the various PI revisions.\n\nSigned-off-by: Joerg Schambacher <joerg@hifiberry.com>\n---\n sound/soc/bcm/hifiberry_dacplus.c       | 2 +-\n sound/soc/bcm/hifiberry_dacplusadcpro.c | 2 +-\n 2 files changed, 2 insertions(+), 2 deletions(-)\n\n--- a/sound/soc/bcm/hifiberry_dacplus.c\n+++ b/sound/soc/bcm/hifiberry_dacplus.c\n@@ -111,7 +111,7 @@ static void snd_rpi_hifiberry_dacplus_se\n \t\tsnd_soc_component_update_bits(component, PCM512x_GPIO_CONTROL_1, 0x24, 0x04);\n \t\tbreak;\n \t}\n-\tusleep_range(2000, 2100);\n+\tusleep_range(3000, 4000);\n }\n \n static void snd_rpi_hifiberry_dacplus_clk_gpio(struct snd_soc_component *component)\n--- a/sound/soc/bcm/hifiberry_dacplusadcpro.c\n+++ b/sound/soc/bcm/hifiberry_dacplusadcpro.c\n@@ -190,7 +190,7 @@ static void snd_rpi_hifiberry_dacplusadc\n \t\t\t\tPCM512x_GPIO_CONTROL_1, 0x24, 0x04);\n \t\tbreak;\n \t}\n-\tusleep_range(2000, 2100);\n+\tusleep_range(3000, 4000);\n }\n \n static void snd_rpi_hifiberry_dacplusadcpro_clk_gpio(struct snd_soc_component *component)\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0627-bcm2835-Allow-compressed-frames-to-set-sizeimage-438.patch",
    "content": "From 9eaafa9f93c9a97498b73583a70b9e238cbe4536 Mon Sep 17 00:00:00 2001\nFrom: jc-kynesim <jc@kynesim.co.uk>\nDate: Fri, 11 Jun 2021 15:14:31 +0100\nSubject: [PATCH] bcm2835: Allow compressed frames to set sizeimage\n (#4386)\n\nAllow the user to set sizeimage in TRY_FMT and S_FMT if the format\nflags have V4L2_FMT_FLAG_COMPRESSED set\n\nSigned-off-by: John Cox <jc@kynesim.co.uk>\n---\n .../bcm2835-codec/bcm2835-v4l2-codec.c          | 17 ++++++++++++++---\n 1 file changed, 14 insertions(+), 3 deletions(-)\n\n--- a/drivers/staging/vc04_services/bcm2835-codec/bcm2835-v4l2-codec.c\n+++ b/drivers/staging/vc04_services/bcm2835-codec/bcm2835-v4l2-codec.c\n@@ -1291,6 +1291,8 @@ static int vidioc_g_fmt_vid_cap(struct f\n static int vidioc_try_fmt(struct bcm2835_codec_ctx *ctx, struct v4l2_format *f,\n \t\t\t  struct bcm2835_codec_fmt *fmt)\n {\n+\tunsigned int sizeimage;\n+\n \t/*\n \t * The V4L2 specification requires the driver to correct the format\n \t * struct if any of the dimensions is unsupported\n@@ -1319,9 +1321,18 @@ static int vidioc_try_fmt(struct bcm2835\n \tf->fmt.pix_mp.num_planes = 1;\n \tf->fmt.pix_mp.plane_fmt[0].bytesperline =\n \t\tget_bytesperline(f->fmt.pix_mp.width, fmt);\n-\tf->fmt.pix_mp.plane_fmt[0].sizeimage =\n-\t\tget_sizeimage(f->fmt.pix_mp.plane_fmt[0].bytesperline,\n-\t\t\t      f->fmt.pix_mp.width, f->fmt.pix_mp.height, fmt);\n+\tsizeimage = get_sizeimage(f->fmt.pix_mp.plane_fmt[0].bytesperline,\n+\t\t\t\t  f->fmt.pix_mp.width, f->fmt.pix_mp.height,\n+\t\t\t\t  fmt);\n+\t/*\n+\t * Drivers must set sizeimage for uncompressed formats\n+\t * Compressed formats allow the client to request an alternate\n+\t * size for the buffer.\n+\t */\n+\tif (!(fmt->flags & V4L2_FMT_FLAG_COMPRESSED) ||\n+\t    f->fmt.pix_mp.plane_fmt[0].sizeimage < sizeimage)\n+\t\tf->fmt.pix_mp.plane_fmt[0].sizeimage = sizeimage;\n+\n \tmemset(f->fmt.pix_mp.plane_fmt[0].reserved, 0,\n \t       sizeof(f->fmt.pix_mp.plane_fmt[0].reserved));\n \n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0628-media-i2c-imx477-Fix-for-long-exposure-limit-calcula.patch",
    "content": "From cd306429474a0265660759ab12024d8ff978d586 Mon Sep 17 00:00:00 2001\nFrom: Naushir Patuck <naush@raspberrypi.com>\nDate: Fri, 11 Jun 2021 12:47:07 +0100\nSubject: [PATCH] media: i2c: imx477: Fix for long exposure limit\n calculations\n\nDo not scale IMX477_EXPOSURE_OFFSET with the long exposure factor during\nthe limit calculations. This allows larger exposure times, and does seem to be\nwhat the sensor is doing internally.\n\nSigned-off-by: Naushir Patuck <naush@raspberrypi.com>\n---\n drivers/media/i2c/imx477.c | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/drivers/media/i2c/imx477.c\n+++ b/drivers/media/i2c/imx477.c\n@@ -1282,7 +1282,7 @@ static void imx477_adjust_exposure_range\n \n \t/* Honour the VBLANK limits when setting exposure. */\n \texposure_max = imx477->mode->height + imx477->vblank->val -\n-\t\t       (IMX477_EXPOSURE_OFFSET << imx477->long_exp_shift);\n+\t\t       IMX477_EXPOSURE_OFFSET;\n \texposure_def = min(exposure_max, imx477->exposure->val);\n \t__v4l2_ctrl_modify_range(imx477->exposure, imx477->exposure->minimum,\n \t\t\t\t exposure_max, imx477->exposure->step,\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0629-overlays-ghost-amp-Change-early-disable-sequence.patch",
    "content": "From c6ae428b0fa43bee35aa6de4fb2f5d5cc81460a4 Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.com>\nDate: Mon, 14 Jun 2021 15:07:38 +0100\nSubject: [PATCH] overlays: ghost-amp: Change early-disable sequence\n\nIn the event that the ENABLE signal from the codec goes low before\nRELAY2 has been enabled, wait until the full 1000ms has elapsed then\nenable RELAY2 and jump to amp_on_wait, i.e. as if output had been\nfully enabled then disabled, rather than returning to the amp_off\nidle state.\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.com>\n---\n arch/arm/boot/dts/overlays/ghost-amp-overlay.dts | 14 ++++++++++----\n 1 file changed, 10 insertions(+), 4 deletions(-)\n\n--- a/arch/arm/boot/dts/overlays/ghost-amp-overlay.dts\n+++ b/arch/arm/boot/dts/overlays/ghost-amp-overlay.dts\n@@ -82,14 +82,20 @@\n \n \t\t\t\tamp_on_1 {\n \t\t\t\t\tset = <RELAY1 1>;\n-\t\t\t\t\tamp_on = <GF_DELAY 1000>;\n-\t\t\t\t\tamp_off = <ENABLE 0>;\n+\t\t\t\t\tamp_on_2 = <GF_DELAY 1000>;\n+\t\t\t\t\tamp_off = <GF_SHUTDOWN 0>;\n+\t\t\t\t\tfault = <FAULT 1>;\n+\t\t\t\t};\n+\n+\t\t\t\tamp_on_2 {\n+\t\t\t\t\tset = <RELAY2 1>;\n+\t\t\t\t\tamp_on_wait = <ENABLE 0>;\n+\t\t\t\t\tamp_on = <GF_DELAY 1>;\n \t\t\t\t\tfault = <FAULT 1>;\n \t\t\t\t};\n \n \t\t\t\tamp_on {\n-\t\t\t\t\tset = <RELAY2 1>,\n-\t\t\t\t\t      <RELAYSSR 1>;\n+\t\t\t\t\tset = <RELAYSSR 1>;\n \t\t\t\t\tamp_on_wait = <ENABLE 0>;\n \t\t\t\t\tfault = <FAULT 1>;\n \t\t\t\t};\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0630-drm-vc4-Make-vc4_crtc_get_encoder-public.patch",
    "content": "From 68f513af115c2ff6e5869f7f78d986d6121a122b Mon Sep 17 00:00:00 2001\nFrom: Maxime Ripard <maxime@cerno.tech>\nDate: Wed, 26 May 2021 16:07:01 +0200\nSubject: [PATCH] drm/vc4: Make vc4_crtc_get_encoder public\n\nWe'll need that function in vc4_kms to compute the core clock rate\nrequirements.\n\nSigned-off-by: Maxime Ripard <maxime@cerno.tech>\n---\n drivers/gpu/drm/vc4/vc4_crtc.c | 8 ++++----\n drivers/gpu/drm/vc4/vc4_drv.h  | 5 +++++\n 2 files changed, 9 insertions(+), 4 deletions(-)\n\n--- a/drivers/gpu/drm/vc4/vc4_crtc.c\n+++ b/drivers/gpu/drm/vc4/vc4_crtc.c\n@@ -279,10 +279,10 @@ static u32 vc4_crtc_get_fifo_full_level_\n  * allows drivers to push pixels to more than one encoder from the\n  * same CRTC.\n  */\n-static struct drm_encoder *vc4_get_crtc_encoder(struct drm_crtc *crtc,\n-\t\t\t\t\t\tstruct drm_atomic_state *state,\n-\t\t\t\t\t\tstruct drm_connector_state *(*get_state)(struct drm_atomic_state *state,\n-\t\t\t\t\t\t\t\t\t\t\t struct drm_connector *connector))\n+struct drm_encoder *vc4_get_crtc_encoder(struct drm_crtc *crtc,\n+\t\t\t\t\t struct drm_atomic_state *state,\n+\t\t\t\t\t struct drm_connector_state *(*get_state)(struct drm_atomic_state *state,\n+\t\t\t\t\t\t\t\t\t\t  struct drm_connector *connector))\n {\n \tstruct drm_connector *connector;\n \tstruct drm_connector_list_iter conn_iter;\n--- a/drivers/gpu/drm/vc4/vc4_drv.h\n+++ b/drivers/gpu/drm/vc4/vc4_drv.h\n@@ -522,6 +522,11 @@ vc4_crtc_to_vc4_pv_data(const struct vc4\n \treturn container_of(data, struct vc4_pv_data, base);\n }\n \n+struct drm_encoder *vc4_get_crtc_encoder(struct drm_crtc *crtc,\n+\t\t\t\t\t struct drm_atomic_state *state,\n+\t\t\t\t\t struct drm_connector_state *(*get_state)(struct drm_atomic_state *state,\n+\t\t\t\t\t\t\t\t\t\t  struct drm_connector *connector));\n+\n struct vc4_crtc_state {\n \tstruct drm_crtc_state base;\n \t/* Dlist area for this CRTC configuration. */\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0631-ASoC-codec-hdmi-codec-Support-IEC958-encoded-PCM-for.patch",
    "content": "From ab79274c7bab8e16822077ae0850e6cf9b2ec1b4 Mon Sep 17 00:00:00 2001\nFrom: Sia Jee Heng <jee.heng.sia@intel.com>\nDate: Thu, 4 Feb 2021 09:42:55 +0800\nSubject: [PATCH] ASoC: codec: hdmi-codec: Support IEC958 encoded PCM\n format\n\nExisting hdmi-codec driver only support standard pcm format.\nSupport of IEC958 encoded format pass from ALSA IEC958 plugin is needed\nso that the IEC958 encoded data can be streamed to the HDMI chip.\n\nSigned-off-by: Sia Jee Heng <jee.heng.sia@intel.com>\nLink: https://lore.kernel.org/r/20210204014258.10197-2-jee.heng.sia@intel.com\nSigned-off-by: Mark Brown <broonie@kernel.org>\nSigned-off-by: Maxime Ripard <maxime@cerno.tech>\n---\n include/sound/hdmi-codec.h    | 5 +++++\n sound/soc/codecs/hdmi-codec.c | 4 +++-\n 2 files changed, 8 insertions(+), 1 deletion(-)\n\n--- a/include/sound/hdmi-codec.h\n+++ b/include/sound/hdmi-codec.h\n@@ -34,6 +34,11 @@ struct hdmi_codec_daifmt {\n \tunsigned int frame_clk_inv:1;\n \tunsigned int bit_clk_master:1;\n \tunsigned int frame_clk_master:1;\n+\t/* bit_fmt could be standard PCM format or\n+\t * IEC958 encoded format. ALSA IEC958 plugin will pass\n+\t * IEC958_SUBFRAME format to the underneath driver.\n+\t */\n+\tsnd_pcm_format_t bit_fmt;\n };\n \n /*\n--- a/sound/soc/codecs/hdmi-codec.c\n+++ b/sound/soc/codecs/hdmi-codec.c\n@@ -487,6 +487,7 @@ static int hdmi_codec_hw_params(struct s\n \thp.sample_rate = params_rate(params);\n \thp.channels = params_channels(params);\n \n+\tcf->bit_fmt = params_format(params);\n \treturn hcp->hcd.ops->hw_params(dai->dev->parent, hcp->hcd.data,\n \t\t\t\t       cf, &hp);\n }\n@@ -615,7 +616,8 @@ static const struct snd_soc_dai_ops hdmi\n \t\t\t SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S20_3BE |\\\n \t\t\t SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_3BE |\\\n \t\t\t SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S24_BE |\\\n-\t\t\t SNDRV_PCM_FMTBIT_S32_LE | SNDRV_PCM_FMTBIT_S32_BE)\n+\t\t\t SNDRV_PCM_FMTBIT_S32_LE | SNDRV_PCM_FMTBIT_S32_BE |\\\n+\t\t\t SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE)\n \n static int hdmi_codec_pcm_new(struct snd_soc_pcm_runtime *rtd,\n \t\t\t      struct snd_soc_dai *dai)\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0632-ASoC-hdmi-codec-Rework-to-support-more-controls.patch",
    "content": "From 0ddc79efb48c97f0e678807fbe2471f122fd41f6 Mon Sep 17 00:00:00 2001\nFrom: Maxime Ripard <maxime@cerno.tech>\nDate: Wed, 28 Apr 2021 11:56:26 +0200\nSubject: [PATCH] ASoC: hdmi-codec: Rework to support more controls\n\nWe're going to add more controls to support the IEC958 output, so let's\nrework the control registration a bit to support more of them.\n\nSigned-off-by: Maxime Ripard <maxime@cerno.tech>\n---\n sound/soc/codecs/hdmi-codec.c | 41 ++++++++++++++++++++++-------------\n 1 file changed, 26 insertions(+), 15 deletions(-)\n\n--- a/sound/soc/codecs/hdmi-codec.c\n+++ b/sound/soc/codecs/hdmi-codec.c\n@@ -619,21 +619,23 @@ static const struct snd_soc_dai_ops hdmi\n \t\t\t SNDRV_PCM_FMTBIT_S32_LE | SNDRV_PCM_FMTBIT_S32_BE |\\\n \t\t\t SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE)\n \n+struct snd_kcontrol_new hdmi_codec_controls[] = {\n+\t{\n+\t\t.access\t= (SNDRV_CTL_ELEM_ACCESS_READ |\n+\t\t\t   SNDRV_CTL_ELEM_ACCESS_VOLATILE),\n+\t\t.iface\t= SNDRV_CTL_ELEM_IFACE_PCM,\n+\t\t.name\t= \"ELD\",\n+\t\t.info\t= hdmi_eld_ctl_info,\n+\t\t.get\t= hdmi_eld_ctl_get,\n+\t},\n+};\n+\n static int hdmi_codec_pcm_new(struct snd_soc_pcm_runtime *rtd,\n \t\t\t      struct snd_soc_dai *dai)\n {\n \tstruct snd_soc_dai_driver *drv = dai->driver;\n \tstruct hdmi_codec_priv *hcp = snd_soc_dai_get_drvdata(dai);\n-\tstruct snd_kcontrol *kctl;\n-\tstruct snd_kcontrol_new hdmi_eld_ctl = {\n-\t\t.access\t= SNDRV_CTL_ELEM_ACCESS_READ |\n-\t\t\t  SNDRV_CTL_ELEM_ACCESS_VOLATILE,\n-\t\t.iface\t= SNDRV_CTL_ELEM_IFACE_PCM,\n-\t\t.name\t= \"ELD\",\n-\t\t.info\t= hdmi_eld_ctl_info,\n-\t\t.get\t= hdmi_eld_ctl_get,\n-\t\t.device\t= rtd->pcm->device,\n-\t};\n+\tunsigned int i;\n \tint ret;\n \n \tret =  snd_pcm_add_chmap_ctls(rtd->pcm, SNDRV_PCM_STREAM_PLAYBACK,\n@@ -650,12 +652,21 @@ static int hdmi_codec_pcm_new(struct snd\n \thcp->chmap_info->chmap = hdmi_codec_stereo_chmaps;\n \thcp->chmap_idx = HDMI_CODEC_CHMAP_IDX_UNKNOWN;\n \n-\t/* add ELD ctl with the device number corresponding to the PCM stream */\n-\tkctl = snd_ctl_new1(&hdmi_eld_ctl, dai->component);\n-\tif (!kctl)\n-\t\treturn -ENOMEM;\n+\tfor (i = 0; i < ARRAY_SIZE(hdmi_codec_controls); i++) {\n+\t\tstruct snd_kcontrol *kctl;\n+\n+\t\t/* add ELD ctl with the device number corresponding to the PCM stream */\n+\t\tkctl = snd_ctl_new1(&hdmi_codec_controls[i], dai->component);\n+\t\tif (!kctl)\n+\t\t\treturn -ENOMEM;\n+\n+\t\tkctl->id.device = rtd->pcm->device;\n+\t\tret = snd_ctl_add(rtd->card->snd_card, kctl);\n+\t\tif (ret < 0)\n+\t\t\treturn ret;\n+\t}\n \n-\treturn snd_ctl_add(rtd->card->snd_card, kctl);\n+\treturn 0;\n }\n \n static int hdmi_dai_probe(struct snd_soc_dai *dai)\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0633-snd-iec958-split-status-creation-and-fill.patch",
    "content": "From 5dea9e48e2a2bd39524e21c1a743f08edd8e4ef6 Mon Sep 17 00:00:00 2001\nFrom: Maxime Ripard <maxime@cerno.tech>\nDate: Wed, 28 Apr 2021 15:29:13 +0200\nSubject: [PATCH] snd: iec958: split status creation and fill\n\nIn some situations, like a codec probe, we need to provide an IEC status\ndefault but don't have access to the sampling rate and width yet since\nno stream has been configured yet.\n\nEach and every driver has its own default, whereas the core iec958 code\nalso has some buried in the snd_pcm_create_iec958_consumer functions.\n\nLet's split these functions in two to provide a default that doesn't\nrely on the sampling rate and width, and another function to fill them\nwhen available.\n\nSigned-off-by: Maxime Ripard <maxime@cerno.tech>\n---\n include/sound/pcm_iec958.h |   8 +++\n sound/core/pcm_iec958.c    | 129 +++++++++++++++++++++++++------------\n 2 files changed, 95 insertions(+), 42 deletions(-)\n\n--- a/include/sound/pcm_iec958.h\n+++ b/include/sound/pcm_iec958.h\n@@ -4,6 +4,14 @@\n \n #include <linux/types.h>\n \n+int snd_pcm_create_iec958_consumer_default(u8 *cs, size_t len);\n+\n+int snd_pcm_fill_iec958_consumer(struct snd_pcm_runtime *runtime, u8 *cs,\n+\t\t\t\t size_t len);\n+\n+int snd_pcm_fill_iec958_consumer_hw_params(struct snd_pcm_hw_params *params,\n+\t\t\t\t\t   u8 *cs, size_t len);\n+\n int snd_pcm_create_iec958_consumer(struct snd_pcm_runtime *runtime, u8 *cs,\n \tsize_t len);\n \n--- a/sound/core/pcm_iec958.c\n+++ b/sound/core/pcm_iec958.c\n@@ -9,41 +9,68 @@\n #include <sound/pcm_params.h>\n #include <sound/pcm_iec958.h>\n \n-static int create_iec958_consumer(uint rate, uint sample_width,\n-\t\t\t\t  u8 *cs, size_t len)\n+int snd_pcm_create_iec958_consumer_default(u8 *cs, size_t len)\n {\n-\tunsigned int fs, ws;\n-\n \tif (len < 4)\n \t\treturn -EINVAL;\n \n-\tswitch (rate) {\n-\tcase 32000:\n-\t\tfs = IEC958_AES3_CON_FS_32000;\n-\t\tbreak;\n-\tcase 44100:\n-\t\tfs = IEC958_AES3_CON_FS_44100;\n-\t\tbreak;\n-\tcase 48000:\n-\t\tfs = IEC958_AES3_CON_FS_48000;\n-\t\tbreak;\n-\tcase 88200:\n-\t\tfs = IEC958_AES3_CON_FS_88200;\n-\t\tbreak;\n-\tcase 96000:\n-\t\tfs = IEC958_AES3_CON_FS_96000;\n-\t\tbreak;\n-\tcase 176400:\n-\t\tfs = IEC958_AES3_CON_FS_176400;\n-\t\tbreak;\n-\tcase 192000:\n-\t\tfs = IEC958_AES3_CON_FS_192000;\n-\t\tbreak;\n-\tdefault:\n+\tmemset(cs, 0, len);\n+\n+\tcs[0] = IEC958_AES0_CON_NOT_COPYRIGHT | IEC958_AES0_CON_EMPHASIS_NONE;\n+\tcs[1] = IEC958_AES1_CON_GENERAL;\n+\tcs[2] = IEC958_AES2_CON_SOURCE_UNSPEC | IEC958_AES2_CON_CHANNEL_UNSPEC;\n+\tcs[3] = IEC958_AES3_CON_CLOCK_1000PPM | IEC958_AES3_CON_FS_NOTID;\n+\n+\tif (len > 4)\n+\t\tcs[4] = IEC958_AES4_CON_WORDLEN_NOTID;\n+\n+\treturn len;\n+}\n+EXPORT_SYMBOL(snd_pcm_create_iec958_consumer_default);\n+\n+static int fill_iec958_consumer(uint rate, uint sample_width,\n+\t\t\t\tu8 *cs, size_t len)\n+{\n+\tif (len < 4)\n \t\treturn -EINVAL;\n+\n+\tif ((cs[3] & IEC958_AES3_CON_FS) == IEC958_AES3_CON_FS_NOTID) {\n+\t\tunsigned int fs;\n+\n+\t\tswitch (rate) {\n+\t\t\tcase 32000:\n+\t\t\t\tfs = IEC958_AES3_CON_FS_32000;\n+\t\t\t\tbreak;\n+\t\t\tcase 44100:\n+\t\t\t\tfs = IEC958_AES3_CON_FS_44100;\n+\t\t\t\tbreak;\n+\t\t\tcase 48000:\n+\t\t\t\tfs = IEC958_AES3_CON_FS_48000;\n+\t\t\t\tbreak;\n+\t\t\tcase 88200:\n+\t\t\t\tfs = IEC958_AES3_CON_FS_88200;\n+\t\t\t\tbreak;\n+\t\t\tcase 96000:\n+\t\t\t\tfs = IEC958_AES3_CON_FS_96000;\n+\t\t\t\tbreak;\n+\t\t\tcase 176400:\n+\t\t\t\tfs = IEC958_AES3_CON_FS_176400;\n+\t\t\t\tbreak;\n+\t\t\tcase 192000:\n+\t\t\t\tfs = IEC958_AES3_CON_FS_192000;\n+\t\t\t\tbreak;\n+\t\t\tdefault:\n+\t\t\t\treturn -EINVAL;\n+\t\t}\n+\n+\t\tcs[3] &= ~IEC958_AES3_CON_FS;\n+\t\tcs[3] |= fs;\n \t}\n \n-\tif (len > 4) {\n+\tif (len > 4 &&\n+\t    (cs[4] & IEC958_AES4_CON_WORDLEN) == IEC958_AES4_CON_WORDLEN_NOTID) {\n+\t\tunsigned int ws;\n+\n \t\tswitch (sample_width) {\n \t\tcase 16:\n \t\t\tws = IEC958_AES4_CON_WORDLEN_20_16;\n@@ -64,20 +91,29 @@ static int create_iec958_consumer(uint r\n \t\tdefault:\n \t\t\treturn -EINVAL;\n \t\t}\n-\t}\n \n-\tmemset(cs, 0, len);\n+\t\tcs[4] &= ~IEC958_AES4_CON_WORDLEN;\n+\t\tcs[4] |= ws;\n+\t}\n \n-\tcs[0] = IEC958_AES0_CON_NOT_COPYRIGHT | IEC958_AES0_CON_EMPHASIS_NONE;\n-\tcs[1] = IEC958_AES1_CON_GENERAL;\n-\tcs[2] = IEC958_AES2_CON_SOURCE_UNSPEC | IEC958_AES2_CON_CHANNEL_UNSPEC;\n-\tcs[3] = IEC958_AES3_CON_CLOCK_1000PPM | fs;\n+\treturn len;\n+}\n \n-\tif (len > 4)\n-\t\tcs[4] = ws;\n+int snd_pcm_fill_iec958_consumer_hw_params(struct snd_pcm_hw_params *params,\n+\t\t\t\t\t   u8 *cs, size_t len)\n+{\n+\treturn fill_iec958_consumer(params_rate(params), params_width(params), cs, len);\n+}\n+EXPORT_SYMBOL(snd_pcm_fill_iec958_consumer_hw_params);\n \n-\treturn len;\n+int snd_pcm_fill_iec958_consumer(struct snd_pcm_runtime *runtime,\n+\t\t\t\t u8 *cs, size_t len)\n+{\n+\treturn fill_iec958_consumer(runtime->rate,\n+\t\t\t\t    snd_pcm_format_width(runtime->format),\n+\t\t\t\t    cs, len);\n }\n+EXPORT_SYMBOL(snd_pcm_fill_iec958_consumer);\n \n /**\n  * snd_pcm_create_iec958_consumer - create consumer format IEC958 channel status\n@@ -95,9 +131,13 @@ static int create_iec958_consumer(uint r\n int snd_pcm_create_iec958_consumer(struct snd_pcm_runtime *runtime, u8 *cs,\n \tsize_t len)\n {\n-\treturn create_iec958_consumer(runtime->rate,\n-\t\t\t\t      snd_pcm_format_width(runtime->format),\n-\t\t\t\t      cs, len);\n+\tint ret;\n+\n+\tret = snd_pcm_create_iec958_consumer_default(cs, len);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\treturn snd_pcm_fill_iec958_consumer(runtime, cs, len);\n }\n EXPORT_SYMBOL(snd_pcm_create_iec958_consumer);\n \n@@ -117,7 +157,12 @@ EXPORT_SYMBOL(snd_pcm_create_iec958_cons\n int snd_pcm_create_iec958_consumer_hw_params(struct snd_pcm_hw_params *params,\n \t\t\t\t\t     u8 *cs, size_t len)\n {\n-\treturn create_iec958_consumer(params_rate(params), params_width(params),\n-\t\t\t\t      cs, len);\n+\tint ret;\n+\n+\tret = snd_pcm_create_iec958_consumer_default(cs, len);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\treturn fill_iec958_consumer(params_rate(params), params_width(params), cs, len);\n }\n EXPORT_SYMBOL(snd_pcm_create_iec958_consumer_hw_params);\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0634-ASoC-hdmi-codec-Add-iec958-controls.patch",
    "content": "From 011a6244136c86e03c77866d6ef9b8eac65fc575 Mon Sep 17 00:00:00 2001\nFrom: Maxime Ripard <maxime@cerno.tech>\nDate: Wed, 28 Apr 2021 15:29:51 +0200\nSubject: [PATCH] ASoC: hdmi-codec: Add iec958 controls\n\nSigned-off-by: Maxime Ripard <maxime@cerno.tech>\n---\n sound/soc/codecs/hdmi-codec.c | 66 +++++++++++++++++++++++++++++++++--\n 1 file changed, 64 insertions(+), 2 deletions(-)\n\n--- a/sound/soc/codecs/hdmi-codec.c\n+++ b/sound/soc/codecs/hdmi-codec.c\n@@ -278,6 +278,7 @@ struct hdmi_codec_priv {\n \tbool busy;\n \tstruct snd_soc_jack *jack;\n \tunsigned int jack_status;\n+\tu8 iec_status[5];\n };\n \n static const struct snd_soc_dapm_widget hdmi_widgets[] = {\n@@ -385,6 +386,47 @@ static int hdmi_codec_chmap_ctl_get(stru\n \treturn 0;\n }\n \n+static int hdmi_codec_iec958_info(struct snd_kcontrol *kcontrol,\n+\t\t\t\t  struct snd_ctl_elem_info *uinfo)\n+{\n+\tuinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;\n+\tuinfo->count = 1;\n+\treturn 0;\n+}\n+\n+static int hdmi_codec_iec958_default_get(struct snd_kcontrol *kcontrol,\n+\t\t\t\t\t struct snd_ctl_elem_value *ucontrol)\n+{\n+\tstruct snd_soc_component *component = snd_kcontrol_chip(kcontrol);\n+\tstruct hdmi_codec_priv *hcp = snd_soc_component_get_drvdata(component);\n+\n+\tmemcpy(ucontrol->value.iec958.status, hcp->iec_status,\n+\t       sizeof(hcp->iec_status));\n+\n+\treturn 0;\n+}\n+\n+static int hdmi_codec_iec958_default_put(struct snd_kcontrol *kcontrol,\n+\t\t\t\t\t struct snd_ctl_elem_value *ucontrol)\n+{\n+\tstruct snd_soc_component *component = snd_kcontrol_chip(kcontrol);\n+\tstruct hdmi_codec_priv *hcp = snd_soc_component_get_drvdata(component);\n+\n+\tmemcpy(hcp->iec_status, ucontrol->value.iec958.status,\n+\t       sizeof(hcp->iec_status));\n+\n+\treturn 0;\n+}\n+\n+static int hdmi_codec_iec958_mask_get(struct snd_kcontrol *kcontrol,\n+\t\t\t\t      struct snd_ctl_elem_value *ucontrol)\n+{\n+\tmemset(ucontrol->value.iec958.status, 0xff,\n+\t       sizeof_field(struct hdmi_codec_priv, iec_status));\n+\n+\treturn 0;\n+}\n+\n static int hdmi_codec_startup(struct snd_pcm_substream *substream,\n \t\t\t      struct snd_soc_dai *dai)\n {\n@@ -458,8 +500,9 @@ static int hdmi_codec_hw_params(struct s\n \t\tparams_width(params), params_rate(params),\n \t\tparams_channels(params));\n \n-\tret = snd_pcm_create_iec958_consumer_hw_params(params, hp.iec.status,\n-\t\t\t\t\t\t       sizeof(hp.iec.status));\n+\tmemcpy(hp.iec.status, hcp->iec_status, sizeof(hp->iec_status));\n+\tret = snd_pcm_fill_iec958_consumer_hw_params(params, hp.iec.status,\n+\t\t\t\t\t\t     sizeof(hp.iec.status));\n \tif (ret < 0) {\n \t\tdev_err(dai->dev, \"Creating IEC958 channel status failed %d\\n\",\n \t\t\tret);\n@@ -621,6 +664,20 @@ static const struct snd_soc_dai_ops hdmi\n \n struct snd_kcontrol_new hdmi_codec_controls[] = {\n \t{\n+\t\t.access = SNDRV_CTL_ELEM_ACCESS_READ,\n+\t\t.iface = SNDRV_CTL_ELEM_IFACE_PCM,\n+\t\t.name = SNDRV_CTL_NAME_IEC958(\"\", PLAYBACK, MASK),\n+\t\t.info = hdmi_codec_iec958_info,\n+\t\t.get = hdmi_codec_iec958_mask_get,\n+\t},\n+\t{\n+\t\t.iface = SNDRV_CTL_ELEM_IFACE_PCM,\n+\t\t.name = SNDRV_CTL_NAME_IEC958(\"\", PLAYBACK, DEFAULT),\n+\t\t.info = hdmi_codec_iec958_info,\n+\t\t.get = hdmi_codec_iec958_default_get,\n+\t\t.put = hdmi_codec_iec958_default_put,\n+\t},\n+\t{\n \t\t.access\t= (SNDRV_CTL_ELEM_ACCESS_READ |\n \t\t\t   SNDRV_CTL_ELEM_ACCESS_VOLATILE),\n \t\t.iface\t= SNDRV_CTL_ELEM_IFACE_PCM,\n@@ -845,6 +902,11 @@ static int hdmi_codec_probe(struct platf\n \thcp->hcd = *hcd;\n \tmutex_init(&hcp->lock);\n \n+\tret = snd_pcm_create_iec958_consumer_default(hcp->iec_status,\n+\t\t\t\t\t\t     sizeof(hcp->iec_status));\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n \tdaidrv = devm_kcalloc(dev, dai_count, sizeof(*daidrv), GFP_KERNEL);\n \tif (!daidrv)\n \t\treturn -ENOMEM;\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0635-ASoC-hdmi-codec-Add-a-prepare-hook.patch",
    "content": "From 067cda9dd7d018b033877df4996383b3529fdbad Mon Sep 17 00:00:00 2001\nFrom: Maxime Ripard <maxime@cerno.tech>\nDate: Fri, 30 Apr 2021 14:22:06 +0200\nSubject: [PATCH] ASoC: hdmi-codec: Add a prepare hook\n\nThe IEC958 status bit is usually set by the userspace after hw_params\nhas been called, so in order to use whatever is set by the userspace, we\nneed to implement the prepare hook. Let's add it to the hdmi_codec_ops,\nand mandate that either prepare or hw_params is implemented.\n\nSigned-off-by: Maxime Ripard <maxime@cerno.tech>\n---\n include/sound/hdmi-codec.h    |  12 +++-\n sound/soc/codecs/hdmi-codec.c | 112 ++++++++++++++++++++++++++--------\n 2 files changed, 99 insertions(+), 25 deletions(-)\n\n--- a/include/sound/hdmi-codec.h\n+++ b/include/sound/hdmi-codec.h\n@@ -65,13 +65,23 @@ struct hdmi_codec_ops {\n \n \t/*\n \t * Configures HDMI-encoder for audio stream.\n-\t * Mandatory\n+\t * Having either prepare or hw_params is mandatory.\n \t */\n \tint (*hw_params)(struct device *dev, void *data,\n \t\t\t struct hdmi_codec_daifmt *fmt,\n \t\t\t struct hdmi_codec_params *hparms);\n \n \t/*\n+\t * Configures HDMI-encoder for audio stream. Can be called\n+\t * multiple times for each setup.\n+\t *\n+\t * Having either prepare or hw_params is mandatory.\n+\t */\n+\tint (*prepare)(struct device *dev, void *data,\n+\t\t       struct hdmi_codec_daifmt *fmt,\n+\t\t       struct hdmi_codec_params *hparms);\n+\n+\t/*\n \t * Shuts down the audio stream.\n \t * Mandatory\n \t */\n--- a/sound/soc/codecs/hdmi-codec.c\n+++ b/sound/soc/codecs/hdmi-codec.c\n@@ -480,6 +480,42 @@ static void hdmi_codec_shutdown(struct s\n \tmutex_unlock(&hcp->lock);\n }\n \n+static int hdmi_codec_fill_codec_params(struct snd_soc_dai *dai,\n+\t\t\t\t\tunsigned int sample_width,\n+\t\t\t\t\tunsigned int sample_rate,\n+\t\t\t\t\tunsigned int channels,\n+\t\t\t\t\tstruct hdmi_codec_params *hp)\n+{\n+\tstruct hdmi_codec_priv *hcp = snd_soc_dai_get_drvdata(dai);\n+\tint idx;\n+\n+\t/* Select a channel allocation that matches with ELD and pcm channels */\n+\tidx = hdmi_codec_get_ch_alloc_table_idx(hcp, channels);\n+\tif (idx < 0) {\n+\t\tdev_err(dai->dev, \"Not able to map channels to speakers (%d)\\n\",\n+\t\t\tidx);\n+\t\thcp->chmap_idx = HDMI_CODEC_CHMAP_IDX_UNKNOWN;\n+\t\treturn idx;\n+\t}\n+\n+\tmemset(hp, 0, sizeof(*hp));\n+\n+\thdmi_audio_infoframe_init(&hp->cea);\n+\thp->cea.channels = channels;\n+\thp->cea.coding_type = HDMI_AUDIO_CODING_TYPE_STREAM;\n+\thp->cea.sample_size = HDMI_AUDIO_SAMPLE_SIZE_STREAM;\n+\thp->cea.sample_frequency = HDMI_AUDIO_SAMPLE_FREQUENCY_STREAM;\n+\thp->cea.channel_allocation = hdmi_codec_channel_alloc[idx].ca_id;\n+\n+\thp->sample_width = sample_width;\n+\thp->sample_rate = sample_rate;\n+\thp->channels = channels;\n+\n+\thcp->chmap_idx = hdmi_codec_channel_alloc[idx].ca_id;\n+\n+\treturn 0;\n+}\n+\n static int hdmi_codec_hw_params(struct snd_pcm_substream *substream,\n \t\t\t\tstruct snd_pcm_hw_params *params,\n \t\t\t\tstruct snd_soc_dai *dai)\n@@ -494,13 +530,24 @@ static int hdmi_codec_hw_params(struct s\n \t\t\t.dig_subframe = { 0 },\n \t\t}\n \t};\n-\tint ret, idx;\n+\tint ret;\n+\n+\tif (!hcp->hcd.ops->hw_params)\n+\t\treturn 0;\n \n \tdev_dbg(dai->dev, \"%s() width %d rate %d channels %d\\n\", __func__,\n \t\tparams_width(params), params_rate(params),\n \t\tparams_channels(params));\n \n-\tmemcpy(hp.iec.status, hcp->iec_status, sizeof(hp->iec_status));\n+\tret = hdmi_codec_fill_codec_params(dai,\n+\t\t\t\t\t   params_width(params),\n+\t\t\t\t\t   params_rate(params),\n+\t\t\t\t\t   params_channels(params),\n+\t\t\t\t\t   &hp);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\tmemcpy(hp.iec.status, hcp->iec_status, sizeof(hp.iec.status));\n \tret = snd_pcm_fill_iec958_consumer_hw_params(params, hp.iec.status,\n \t\t\t\t\t\t     sizeof(hp.iec.status));\n \tif (ret < 0) {\n@@ -509,32 +556,47 @@ static int hdmi_codec_hw_params(struct s\n \t\treturn ret;\n \t}\n \n-\thdmi_audio_infoframe_init(&hp.cea);\n-\thp.cea.channels = params_channels(params);\n-\thp.cea.coding_type = HDMI_AUDIO_CODING_TYPE_STREAM;\n-\thp.cea.sample_size = HDMI_AUDIO_SAMPLE_SIZE_STREAM;\n-\thp.cea.sample_frequency = HDMI_AUDIO_SAMPLE_FREQUENCY_STREAM;\n-\n-\t/* Select a channel allocation that matches with ELD and pcm channels */\n-\tidx = hdmi_codec_get_ch_alloc_table_idx(hcp, hp.cea.channels);\n-\tif (idx < 0) {\n-\t\tdev_err(dai->dev, \"Not able to map channels to speakers (%d)\\n\",\n-\t\t\tidx);\n-\t\thcp->chmap_idx = HDMI_CODEC_CHMAP_IDX_UNKNOWN;\n-\t\treturn idx;\n-\t}\n-\thp.cea.channel_allocation = hdmi_codec_channel_alloc[idx].ca_id;\n-\thcp->chmap_idx = hdmi_codec_channel_alloc[idx].ca_id;\n-\n-\thp.sample_width = params_width(params);\n-\thp.sample_rate = params_rate(params);\n-\thp.channels = params_channels(params);\n-\n \tcf->bit_fmt = params_format(params);\n \treturn hcp->hcd.ops->hw_params(dai->dev->parent, hcp->hcd.data,\n \t\t\t\t       cf, &hp);\n }\n \n+static int hdmi_codec_prepare(struct snd_pcm_substream *substream,\n+\t\t\t      struct snd_soc_dai *dai)\n+{\n+\tstruct hdmi_codec_priv *hcp = snd_soc_dai_get_drvdata(dai);\n+\tstruct hdmi_codec_daifmt *cf = dai->playback_dma_data;\n+\tstruct snd_pcm_runtime *runtime = substream->runtime;\n+\tunsigned int channels = runtime->channels;\n+\tunsigned int width = snd_pcm_format_width(runtime->format);\n+\tunsigned int rate = runtime->rate;\n+\tstruct hdmi_codec_params hp;\n+\tint ret;\n+\n+\tif (!hcp->hcd.ops->prepare)\n+\t\treturn 0;\n+\n+\tdev_dbg(dai->dev, \"%s() width %d rate %d channels %d\\n\", __func__,\n+\t\twidth, rate, channels);\n+\n+\tret = hdmi_codec_fill_codec_params(dai, width, rate, channels, &hp);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\tmemcpy(hp.iec.status, hcp->iec_status, sizeof(hp.iec.status));\n+\tret = snd_pcm_fill_iec958_consumer(runtime, hp.iec.status,\n+\t\t\t\t\t   sizeof(hp.iec.status));\n+\tif (ret < 0) {\n+\t\tdev_err(dai->dev, \"Creating IEC958 channel status failed %d\\n\",\n+\t\t\tret);\n+\t\treturn ret;\n+\t}\n+\n+\tcf->bit_fmt = runtime->format;\n+\treturn hcp->hcd.ops->prepare(dai->dev->parent, hcp->hcd.data,\n+\t\t\t\t     cf, &hp);\n+}\n+\n static int hdmi_codec_i2s_set_fmt(struct snd_soc_dai *dai,\n \t\t\t\t  unsigned int fmt)\n {\n@@ -626,6 +688,7 @@ static const struct snd_soc_dai_ops hdmi\n \t.startup\t= hdmi_codec_startup,\n \t.shutdown\t= hdmi_codec_shutdown,\n \t.hw_params\t= hdmi_codec_hw_params,\n+\t.prepare\t= hdmi_codec_prepare,\n \t.set_fmt\t= hdmi_codec_i2s_set_fmt,\n \t.mute_stream\t= hdmi_codec_mute,\n };\n@@ -889,7 +952,8 @@ static int hdmi_codec_probe(struct platf\n \t}\n \n \tdai_count = hcd->i2s + hcd->spdif;\n-\tif (dai_count < 1 || !hcd->ops || !hcd->ops->hw_params ||\n+\tif (dai_count < 1 || !hcd->ops ||\n+\t    (!hcd->ops->hw_params && !hcd->ops->prepare) ||\n \t    !hcd->ops->audio_shutdown) {\n \t\tdev_err(dev, \"%s: Invalid parameters\\n\", __func__);\n \t\treturn -EINVAL;\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0636-drm-vc4-Register-HDMI-codec.patch",
    "content": "From 1e6a19ca5f275155a4dd1961d351306b589b11a0 Mon Sep 17 00:00:00 2001\nFrom: Maxime Ripard <maxime@cerno.tech>\nDate: Mon, 26 Apr 2021 14:42:26 +0200\nSubject: [PATCH] drm/vc4: Register HDMI codec\n\nThe hdmi-codec brings a lot of advanced features, including the HDMI\nchannel mapping. Let's use it in our driver instead of our own codec.\n\nSigned-off-by: Maxime Ripard <maxime@cerno.tech>\n---\n drivers/gpu/drm/vc4/Kconfig    |   1 +\n drivers/gpu/drm/vc4/vc4_hdmi.c | 311 +++++++++------------------------\n drivers/gpu/drm/vc4/vc4_hdmi.h |   3 +-\n 3 files changed, 84 insertions(+), 231 deletions(-)\n\n--- a/drivers/gpu/drm/vc4/Kconfig\n+++ b/drivers/gpu/drm/vc4/Kconfig\n@@ -12,6 +12,7 @@ config DRM_VC4\n \tselect SND_PCM\n \tselect SND_PCM_ELD\n \tselect SND_SOC_GENERIC_DMAENGINE_PCM\n+\tselect SND_SOC_HDMI_CODEC\n \tselect DRM_MIPI_DSI\n \thelp\n \t  Choose this option if you have a system that has a Broadcom\n--- a/drivers/gpu/drm/vc4/vc4_hdmi.c\n+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c\n@@ -47,6 +47,7 @@\n #include <linux/reset.h>\n #include <sound/asoundef.h>\n #include <sound/dmaengine_pcm.h>\n+#include <sound/hdmi-codec.h>\n #include <sound/pcm_drm_eld.h>\n #include <sound/pcm_params.h>\n #include <sound/soc.h>\n@@ -96,6 +97,12 @@\n \n #define HSM_MIN_CLOCK_FREQ\t120000000\n #define CEC_CLOCK_FREQ 40000\n+#define HDMI_14_MAX_TMDS_CLK   (340 * 1000 * 1000)\n+\n+static bool vc4_hdmi_mode_needs_scrambling(const struct drm_display_mode *mode)\n+{\n+\treturn (mode->clock * 1000) > HDMI_14_MAX_TMDS_CLK;\n+}\n \n static int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused)\n {\n@@ -473,16 +480,10 @@ static void vc4_hdmi_set_spd_infoframe(s\n static void vc4_hdmi_set_audio_infoframe(struct drm_encoder *encoder)\n {\n \tstruct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);\n+\tstruct hdmi_audio_infoframe *audio = &vc4_hdmi->audio.infoframe;\n \tunion hdmi_infoframe frame;\n-\tint ret;\n-\n-\tret = hdmi_audio_infoframe_init(&frame.audio);\n-\n-\tframe.audio.coding_type = HDMI_AUDIO_CODING_TYPE_STREAM;\n-\tframe.audio.sample_frequency = HDMI_AUDIO_SAMPLE_FREQUENCY_STREAM;\n-\tframe.audio.sample_size = HDMI_AUDIO_SAMPLE_SIZE_STREAM;\n-\tframe.audio.channels = vc4_hdmi->audio.channels;\n \n+\tmemcpy(&frame.audio, audio, sizeof(*audio));\n \tvc4_hdmi_write_infoframe(encoder, &frame);\n }\n \n@@ -1215,18 +1216,10 @@ static inline struct vc4_hdmi *dai_to_hd\n \treturn snd_soc_card_get_drvdata(card);\n }\n \n-static int vc4_hdmi_audio_startup(struct snd_pcm_substream *substream,\n-\t\t\t\t  struct snd_soc_dai *dai)\n+static int vc4_hdmi_audio_startup(struct device *dev, void *data)\n {\n-\tstruct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai);\n+\tstruct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);\n \tstruct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;\n-\tstruct drm_connector *connector = &vc4_hdmi->connector;\n-\tint ret;\n-\n-\tif (vc4_hdmi->audio.substream && vc4_hdmi->audio.substream != substream)\n-\t\treturn -EINVAL;\n-\n-\tvc4_hdmi->audio.substream = substream;\n \n \t/*\n \t * If the HDMI encoder hasn't probed, or the encoder is\n@@ -1236,15 +1229,18 @@ static int vc4_hdmi_audio_startup(struct\n \t\t\t\tVC4_HDMI_RAM_PACKET_ENABLE))\n \t\treturn -ENODEV;\n \n-\tret = snd_pcm_hw_constraint_eld(substream->runtime, connector->eld);\n-\tif (ret)\n-\t\treturn ret;\n+\tvc4_hdmi->audio.streaming = true;\n \n-\treturn 0;\n-}\n+\tHDMI_WRITE(HDMI_MAI_CTL,\n+\t\t   VC4_HD_MAI_CTL_RESET |\n+\t\t   VC4_HD_MAI_CTL_FLUSH |\n+\t\t   VC4_HD_MAI_CTL_DLATE |\n+\t\t   VC4_HD_MAI_CTL_ERRORE |\n+\t\t   VC4_HD_MAI_CTL_ERRORF);\n+\n+\tif (vc4_hdmi->variant->phy_rng_enable)\n+\t\tvc4_hdmi->variant->phy_rng_enable(vc4_hdmi);\n \n-static int vc4_hdmi_audio_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)\n-{\n \treturn 0;\n }\n \n@@ -1264,17 +1260,20 @@ static void vc4_hdmi_audio_reset(struct\n \tHDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_FLUSH);\n }\n \n-static void vc4_hdmi_audio_shutdown(struct snd_pcm_substream *substream,\n-\t\t\t\t    struct snd_soc_dai *dai)\n+static void vc4_hdmi_audio_shutdown(struct device *dev, void *data)\n {\n-\tstruct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai);\n+\tstruct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);\n \n-\tif (substream != vc4_hdmi->audio.substream)\n-\t\treturn;\n+\tHDMI_WRITE(HDMI_MAI_CTL,\n+\t\t   VC4_HD_MAI_CTL_DLATE |\n+\t\t   VC4_HD_MAI_CTL_ERRORE |\n+\t\t   VC4_HD_MAI_CTL_ERRORF);\n \n-\tvc4_hdmi_audio_reset(vc4_hdmi);\n+\tif (vc4_hdmi->variant->phy_rng_disable)\n+\t\tvc4_hdmi->variant->phy_rng_disable(vc4_hdmi);\n \n-\tvc4_hdmi->audio.substream = NULL;\n+\tvc4_hdmi->audio.streaming = false;\n+\tvc4_hdmi_audio_reset(vc4_hdmi);\n }\n \n static int sample_rate_to_mai_fmt(int samplerate)\n@@ -1316,42 +1315,35 @@ static int sample_rate_to_mai_fmt(int sa\n }\n \n /* HDMI audio codec callbacks */\n-static int vc4_hdmi_audio_prepare(struct snd_pcm_substream *substream,\n-\t\t\t\t  struct snd_soc_dai *dai)\n+static int vc4_hdmi_audio_prepare(struct device *dev, void *data,\n+\t\t\t\t  struct hdmi_codec_daifmt *daifmt,\n+\t\t\t\t  struct hdmi_codec_params *params)\n {\n-\tstruct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai);\n+\tstruct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);\n \tstruct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;\n-\tstruct device *dev = &vc4_hdmi->pdev->dev;\n \tu32 audio_packet_config, channel_mask;\n \tu32 channel_map;\n \tu32 mai_audio_format;\n \tu32 mai_sample_rate;\n \n-\tif (substream != vc4_hdmi->audio.substream)\n-\t\treturn -EINVAL;\n+\tdev_dbg(dev, \"%s: %u Hz, %d bit, %d channels\\n\", __func__,\n+\t\tparams->sample_rate, params->sample_width,\n+\t\tparams->channels);\n \n-\tdev_dbg(dev, \"%s: %u Hz, %d bit, %d channels AES0=%02x\\n\",\n-\t\t__func__,\n-\t\tsubstream->runtime->rate,\n-\t\tsnd_pcm_format_width(substream->runtime->format),\n-\t\tsubstream->runtime->channels,\n-\t\tvc4_hdmi->audio.iec_status[0]);\n-\n-\tvc4_hdmi->audio.channels = substream->runtime->channels;\n-\tvc4_hdmi->audio.samplerate = substream->runtime->rate;\n+\tvc4_hdmi->audio.channels = params->channels;\n+\tvc4_hdmi->audio.samplerate = params->sample_rate;\n \n \tHDMI_WRITE(HDMI_MAI_CTL,\n-\t\t   VC4_HD_MAI_CTL_RESET |\n-\t\t   VC4_HD_MAI_CTL_FLUSH |\n-\t\t   VC4_HD_MAI_CTL_DLATE |\n-\t\t   VC4_HD_MAI_CTL_ERRORE |\n-\t\t   VC4_HD_MAI_CTL_ERRORF);\n+\t\t   VC4_SET_FIELD(params->channels, VC4_HD_MAI_CTL_CHNUM) |\n+\t\t   VC4_HD_MAI_CTL_WHOLSMP |\n+\t\t   VC4_HD_MAI_CTL_CHALIGN |\n+\t\t   VC4_HD_MAI_CTL_ENABLE);\n \n \tvc4_hdmi_audio_set_mai_clock(vc4_hdmi);\n \n \tmai_sample_rate = sample_rate_to_mai_fmt(vc4_hdmi->audio.samplerate);\n-\tif (vc4_hdmi->audio.iec_status[0] & IEC958_AES0_NONAUDIO &&\n-\t    vc4_hdmi->audio.channels == 8)\n+\tif (params->iec.status[0] & IEC958_AES0_NONAUDIO &&\n+\t    params->channels == 8)\n \t\tmai_audio_format = VC4_HDMI_MAI_FORMAT_HBR;\n \telse\n \t\tmai_audio_format = VC4_HDMI_MAI_FORMAT_PCM;\n@@ -1388,148 +1380,12 @@ static int vc4_hdmi_audio_prepare(struct\n \tHDMI_WRITE(HDMI_AUDIO_PACKET_CONFIG, audio_packet_config);\n \tvc4_hdmi_set_n_cts(vc4_hdmi);\n \n+\tmemcpy(&vc4_hdmi->audio.infoframe, &params->cea, sizeof(params->cea));\n \tvc4_hdmi_set_audio_infoframe(encoder);\n \n \treturn 0;\n }\n \n-static int vc4_hdmi_audio_trigger(struct snd_pcm_substream *substream, int cmd,\n-\t\t\t\t  struct snd_soc_dai *dai)\n-{\n-\tstruct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai);\n-\n-\tswitch (cmd) {\n-\tcase SNDRV_PCM_TRIGGER_START:\n-\t\tvc4_hdmi->audio.streaming = true;\n-\n-\t\tif (vc4_hdmi->variant->phy_rng_enable)\n-\t\t\tvc4_hdmi->variant->phy_rng_enable(vc4_hdmi);\n-\n-\t\tHDMI_WRITE(HDMI_MAI_CTL,\n-\t\t\t   VC4_SET_FIELD(vc4_hdmi->audio.channels,\n-\t\t\t\t\t VC4_HD_MAI_CTL_CHNUM) |\n-\t\t\t\t\t VC4_HD_MAI_CTL_WHOLSMP |\n-\t\t\t\t\t VC4_HD_MAI_CTL_CHALIGN |\n-\t\t\t\t\t VC4_HD_MAI_CTL_ENABLE);\n-\t\tbreak;\n-\tcase SNDRV_PCM_TRIGGER_STOP:\n-\t\tHDMI_WRITE(HDMI_MAI_CTL,\n-\t\t\t   VC4_HD_MAI_CTL_DLATE |\n-\t\t\t   VC4_HD_MAI_CTL_ERRORE |\n-\t\t\t   VC4_HD_MAI_CTL_ERRORF);\n-\n-\t\tif (vc4_hdmi->variant->phy_rng_disable)\n-\t\t\tvc4_hdmi->variant->phy_rng_disable(vc4_hdmi);\n-\n-\t\tvc4_hdmi->audio.streaming = false;\n-\n-\t\tbreak;\n-\tdefault:\n-\t\tbreak;\n-\t}\n-\n-\treturn 0;\n-}\n-\n-static inline struct vc4_hdmi *\n-snd_component_to_hdmi(struct snd_soc_component *component)\n-{\n-\tstruct snd_soc_card *card = snd_soc_component_get_drvdata(component);\n-\n-\treturn snd_soc_card_get_drvdata(card);\n-}\n-\n-static int vc4_hdmi_audio_eld_ctl_info(struct snd_kcontrol *kcontrol,\n-\t\t\t\t       struct snd_ctl_elem_info *uinfo)\n-{\n-\tstruct snd_soc_component *component = snd_kcontrol_chip(kcontrol);\n-\tstruct vc4_hdmi *vc4_hdmi = snd_component_to_hdmi(component);\n-\tstruct drm_connector *connector = &vc4_hdmi->connector;\n-\n-\tuinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;\n-\tuinfo->count = sizeof(connector->eld);\n-\n-\treturn 0;\n-}\n-\n-static int vc4_hdmi_audio_eld_ctl_get(struct snd_kcontrol *kcontrol,\n-\t\t\t\t      struct snd_ctl_elem_value *ucontrol)\n-{\n-\tstruct snd_soc_component *component = snd_kcontrol_chip(kcontrol);\n-\tstruct vc4_hdmi *vc4_hdmi = snd_component_to_hdmi(component);\n-\tstruct drm_connector *connector = &vc4_hdmi->connector;\n-\n-\tmemcpy(ucontrol->value.bytes.data, connector->eld,\n-\t       sizeof(connector->eld));\n-\n-\treturn 0;\n-}\n-\n-static int vc4_spdif_info(struct snd_kcontrol *kcontrol,\n-\t\t\t  struct snd_ctl_elem_info *uinfo)\n-{\n-\tuinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;\n-\tuinfo->count = 1;\n-\treturn 0;\n-}\n-\n-static int vc4_spdif_playback_get(struct snd_kcontrol *kcontrol,\n-\t\t\t\t  struct snd_ctl_elem_value *ucontrol)\n-{\n-\tstruct snd_soc_component *component = snd_kcontrol_chip(kcontrol);\n-\tstruct vc4_hdmi *vc4_hdmi = snd_component_to_hdmi(component);\n-\n-\tmemcpy(ucontrol->value.iec958.status, vc4_hdmi->audio.iec_status,\n-\t       sizeof(vc4_hdmi->audio.iec_status));\n-\n-\treturn 0;\n-}\n-\n-static int vc4_spdif_playback_put(struct snd_kcontrol *kcontrol,\n-\t\t\t\t  struct snd_ctl_elem_value *ucontrol)\n-{\n-\tstruct snd_soc_component *component = snd_kcontrol_chip(kcontrol);\n-\tstruct vc4_hdmi *vc4_hdmi = snd_component_to_hdmi(component);\n-\n-\tmemcpy(vc4_hdmi->audio.iec_status, ucontrol->value.iec958.status,\n-\t       sizeof(vc4_hdmi->audio.iec_status));\n-\n-\treturn 0;\n-}\n-\n-static int vc4_spdif_mask_get(struct snd_kcontrol *kcontrol,\n-\t\t\t      struct snd_ctl_elem_value *ucontrol)\n-{\n-\tmemset(ucontrol->value.iec958.status, 0xff,\n-\t       sizeof_field(struct vc4_hdmi_audio, iec_status));\n-\n-\treturn 0;\n-}\n-\n-static const struct snd_kcontrol_new vc4_hdmi_audio_controls[] = {\n-\t{\n-\t\t.access = SNDRV_CTL_ELEM_ACCESS_READ |\n-\t\t\t  SNDRV_CTL_ELEM_ACCESS_VOLATILE,\n-\t\t.iface = SNDRV_CTL_ELEM_IFACE_PCM,\n-\t\t.name = \"ELD\",\n-\t\t.info = vc4_hdmi_audio_eld_ctl_info,\n-\t\t.get = vc4_hdmi_audio_eld_ctl_get,\n-\t},\n-\t{\n-\t\t.iface =   SNDRV_CTL_ELEM_IFACE_MIXER,\n-\t\t.name =    SNDRV_CTL_NAME_IEC958(\"\", PLAYBACK, DEFAULT),\n-\t\t.info =    vc4_spdif_info,\n-\t\t.get =     vc4_spdif_playback_get,\n-\t\t.put =     vc4_spdif_playback_put,\n-\t},\n-\t{\n-\t\t.iface =   SNDRV_CTL_ELEM_IFACE_MIXER,\n-\t\t.name =    SNDRV_CTL_NAME_IEC958(\"\", PLAYBACK, MASK),\n-\t\t.info =    vc4_spdif_info,\n-\t\t.get =     vc4_spdif_mask_get,\n-\t},\n-};\n-\n static const struct snd_soc_dapm_widget vc4_hdmi_audio_widgets[] = {\n \tSND_SOC_DAPM_OUTPUT(\"TX\"),\n };\n@@ -1540,8 +1396,6 @@ static const struct snd_soc_dapm_route v\n \n static const struct snd_soc_component_driver vc4_hdmi_audio_component_drv = {\n \t.name\t\t\t= \"vc4-hdmi-codec-dai-component\",\n-\t.controls\t\t= vc4_hdmi_audio_controls,\n-\t.num_controls\t\t= ARRAY_SIZE(vc4_hdmi_audio_controls),\n \t.dapm_widgets\t\t= vc4_hdmi_audio_widgets,\n \t.num_dapm_widgets\t= ARRAY_SIZE(vc4_hdmi_audio_widgets),\n \t.dapm_routes\t\t= vc4_hdmi_audio_routes,\n@@ -1552,28 +1406,6 @@ static const struct snd_soc_component_dr\n \t.non_legacy_dai_naming\t= 1,\n };\n \n-static const struct snd_soc_dai_ops vc4_hdmi_audio_dai_ops = {\n-\t.startup = vc4_hdmi_audio_startup,\n-\t.shutdown = vc4_hdmi_audio_shutdown,\n-\t.prepare = vc4_hdmi_audio_prepare,\n-\t.set_fmt = vc4_hdmi_audio_set_fmt,\n-\t.trigger = vc4_hdmi_audio_trigger,\n-};\n-\n-static struct snd_soc_dai_driver vc4_hdmi_audio_codec_dai_drv = {\n-\t.name = \"vc4-hdmi-hifi\",\n-\t.playback = {\n-\t\t.stream_name = \"Playback\",\n-\t\t.channels_min = 2,\n-\t\t.channels_max = 8,\n-\t\t.rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |\n-\t\t\t SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |\n-\t\t\t SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\n-\t\t\t SNDRV_PCM_RATE_192000,\n-\t\t.formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,\n-\t},\n-};\n-\n static const struct snd_soc_component_driver vc4_hdmi_audio_cpu_dai_comp = {\n \t.name = \"vc4-hdmi-cpu-dai-component\",\n };\n@@ -1600,7 +1432,6 @@ static struct snd_soc_dai_driver vc4_hdm\n \t\t\t SNDRV_PCM_RATE_192000,\n \t\t.formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,\n \t},\n-\t.ops = &vc4_hdmi_audio_dai_ops,\n };\n \n static const struct snd_dmaengine_pcm_config pcm_conf = {\n@@ -1608,6 +1439,31 @@ static const struct snd_dmaengine_pcm_co\n \t.prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,\n };\n \n+\n+static int vc4_hdmi_audio_get_eld(struct device *dev, void *data,\n+\t\t\t\t  uint8_t *buf, size_t len)\n+{\n+\tstruct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);\n+\tstruct drm_connector *connector = &vc4_hdmi->connector;\n+\n+\tmemcpy(buf, connector->eld, min(sizeof(connector->eld), len));\n+\n+\treturn 0;\n+}\n+\n+static const struct hdmi_codec_ops vc4_hdmi_codec_ops = {\n+\t.get_eld = vc4_hdmi_audio_get_eld,\n+\t.prepare = vc4_hdmi_audio_prepare,\n+\t.audio_shutdown = vc4_hdmi_audio_shutdown,\n+\t.audio_startup = vc4_hdmi_audio_startup,\n+};\n+\n+struct hdmi_codec_pdata vc4_hdmi_codec_pdata = {\n+\t.ops = &vc4_hdmi_codec_ops,\n+\t.max_i2s_channels = 8,\n+\t.i2s = 1,\n+};\n+\n static int vc4_hdmi_audio_init(struct vc4_hdmi *vc4_hdmi)\n {\n \tconst struct vc4_hdmi_register *mai_data =\n@@ -1615,6 +1471,7 @@ static int vc4_hdmi_audio_init(struct vc\n \tstruct snd_soc_dai_link *dai_link = &vc4_hdmi->audio.link;\n \tstruct snd_soc_card *card = &vc4_hdmi->audio.card;\n \tstruct device *dev = &vc4_hdmi->pdev->dev;\n+\tstruct platform_device *codec_pdev;\n \tconst __be32 *addr;\n \tint index;\n \tint ret;\n@@ -1650,11 +1507,6 @@ static int vc4_hdmi_audio_init(struct vc\n \tvc4_hdmi->audio.dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;\n \tvc4_hdmi->audio.dma_data.maxburst = 2;\n \n-\tvc4_hdmi->audio.iec_status[0] = IEC958_AES0_CON_NOT_COPYRIGHT;\n-\tvc4_hdmi->audio.iec_status[1] =\n-\t\tIEC958_AES1_CON_ORIGINAL | IEC958_AES1_CON_PCM_CODER;\n-\tvc4_hdmi->audio.iec_status[3] = IEC958_AES3_CON_FS_48000;\n-\n \tret = devm_snd_dmaengine_pcm_register(dev, &pcm_conf, 0);\n \tif (ret) {\n \t\tdev_err(dev, \"Could not register PCM component: %d\\n\", ret);\n@@ -1668,12 +1520,13 @@ static int vc4_hdmi_audio_init(struct vc\n \t\treturn ret;\n \t}\n \n-\t/* register component and codec dai */\n-\tret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_component_drv,\n-\t\t\t\t     &vc4_hdmi_audio_codec_dai_drv, 1);\n-\tif (ret) {\n-\t\tdev_err(dev, \"Could not register component: %d\\n\", ret);\n-\t\treturn ret;\n+\tcodec_pdev = platform_device_register_data(dev, HDMI_CODEC_DRV_NAME,\n+\t\t\t\t\t\t   PLATFORM_DEVID_AUTO,\n+\t\t\t\t\t\t   &vc4_hdmi_codec_pdata,\n+\t\t\t\t\t\t   sizeof(vc4_hdmi_codec_pdata));\n+\tif (IS_ERR(codec_pdev)) {\n+\t\tdev_err(dev, \"Couldn't register the HDMI codec: %ld\\n\", PTR_ERR(codec_pdev));\n+\t\treturn PTR_ERR(codec_pdev);\n \t}\n \n \tdai_link->cpus\t\t= &vc4_hdmi->audio.cpu;\n@@ -1686,9 +1539,9 @@ static int vc4_hdmi_audio_init(struct vc\n \n \tdai_link->name = \"MAI\";\n \tdai_link->stream_name = \"MAI PCM\";\n-\tdai_link->codecs->dai_name = vc4_hdmi_audio_codec_dai_drv.name;\n+\tdai_link->codecs->dai_name = \"i2s-hifi\";\n \tdai_link->cpus->dai_name = dev_name(dev);\n-\tdai_link->codecs->name = dev_name(dev);\n+\tdai_link->codecs->name = dev_name(&codec_pdev->dev);\n \tdai_link->platforms->name = dev_name(dev);\n \n \tcard->dai_link = dai_link;\n--- a/drivers/gpu/drm/vc4/vc4_hdmi.h\n+++ b/drivers/gpu/drm/vc4/vc4_hdmi.h\n@@ -114,8 +114,7 @@ struct vc4_hdmi_audio {\n \tint samplerate;\n \tint channels;\n \tstruct snd_dmaengine_dai_dma_data dma_data;\n-\tstruct snd_pcm_substream *substream;\n-\n+\tstruct hdmi_audio_infoframe infoframe;\n \tbool streaming;\n \n \tunsigned char iec_status[4];\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0637-drm-vc4-hdmi-Remove-redundant-variables.patch",
    "content": "From 644a25e926abb918dfff7b3122896848ca35d2a1 Mon Sep 17 00:00:00 2001\nFrom: Maxime Ripard <maxime@cerno.tech>\nDate: Tue, 27 Apr 2021 16:26:39 +0200\nSubject: [PATCH] drm/vc4: hdmi: Remove redundant variables\n\nSigned-off-by: Maxime Ripard <maxime@cerno.tech>\n---\n drivers/gpu/drm/vc4/vc4_hdmi.c | 26 ++++++++++++--------------\n drivers/gpu/drm/vc4/vc4_hdmi.h |  4 ----\n 2 files changed, 12 insertions(+), 18 deletions(-)\n\n--- a/drivers/gpu/drm/vc4/vc4_hdmi.c\n+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c\n@@ -1165,12 +1165,13 @@ static u32 vc5_hdmi_channel_map(struct v\n }\n \n /* HDMI audio codec callbacks */\n-static void vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi *vc4_hdmi)\n+static void vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi *vc4_hdmi,\n+\t\t\t\t\t unsigned int samplerate)\n {\n \tu32 hsm_clock = clk_get_rate(vc4_hdmi->audio_clock);\n \tunsigned long n, m;\n \n-\trational_best_approximation(hsm_clock, vc4_hdmi->audio.samplerate,\n+\trational_best_approximation(hsm_clock, samplerate,\n \t\t\t\t    VC4_HD_MAI_SMP_N_MASK >>\n \t\t\t\t    VC4_HD_MAI_SMP_N_SHIFT,\n \t\t\t\t    (VC4_HD_MAI_SMP_M_MASK >>\n@@ -1182,12 +1183,11 @@ static void vc4_hdmi_audio_set_mai_clock\n \t\t   VC4_SET_FIELD(m - 1, VC4_HD_MAI_SMP_M));\n }\n \n-static void vc4_hdmi_set_n_cts(struct vc4_hdmi *vc4_hdmi)\n+static void vc4_hdmi_set_n_cts(struct vc4_hdmi *vc4_hdmi, unsigned int samplerate)\n {\n \tstruct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;\n \tstruct drm_crtc *crtc = encoder->crtc;\n \tconst struct drm_display_mode *mode = &crtc->state->adjusted_mode;\n-\tu32 samplerate = vc4_hdmi->audio.samplerate;\n \tu32 n, cts;\n \tu64 tmp;\n \n@@ -1321,27 +1321,25 @@ static int vc4_hdmi_audio_prepare(struct\n {\n \tstruct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);\n \tstruct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;\n+\tunsigned int sample_rate = params->sample_rate;\n+\tunsigned int channels = params->channels;\n \tu32 audio_packet_config, channel_mask;\n \tu32 channel_map;\n \tu32 mai_audio_format;\n \tu32 mai_sample_rate;\n \n \tdev_dbg(dev, \"%s: %u Hz, %d bit, %d channels\\n\", __func__,\n-\t\tparams->sample_rate, params->sample_width,\n-\t\tparams->channels);\n-\n-\tvc4_hdmi->audio.channels = params->channels;\n-\tvc4_hdmi->audio.samplerate = params->sample_rate;\n+\t\tsample_rate, params->sample_width, channels);\n \n \tHDMI_WRITE(HDMI_MAI_CTL,\n-\t\t   VC4_SET_FIELD(params->channels, VC4_HD_MAI_CTL_CHNUM) |\n+\t\t   VC4_SET_FIELD(channels, VC4_HD_MAI_CTL_CHNUM) |\n \t\t   VC4_HD_MAI_CTL_WHOLSMP |\n \t\t   VC4_HD_MAI_CTL_CHALIGN |\n \t\t   VC4_HD_MAI_CTL_ENABLE);\n \n-\tvc4_hdmi_audio_set_mai_clock(vc4_hdmi);\n+\tvc4_hdmi_audio_set_mai_clock(vc4_hdmi, sample_rate);\n \n-\tmai_sample_rate = sample_rate_to_mai_fmt(vc4_hdmi->audio.samplerate);\n+\tmai_sample_rate = sample_rate_to_mai_fmt(sample_rate);\n \tif (params->iec.status[0] & IEC958_AES0_NONAUDIO &&\n \t    params->channels == 8)\n \t\tmai_audio_format = VC4_HDMI_MAI_FORMAT_HBR;\n@@ -1359,7 +1357,7 @@ static int vc4_hdmi_audio_prepare(struct\n \t\tVC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS |\n \t\tVC4_SET_FIELD(0x8, VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER);\n \n-\tchannel_mask = GENMASK(vc4_hdmi->audio.channels - 1, 0);\n+\tchannel_mask = GENMASK(channels - 1, 0);\n \taudio_packet_config |= VC4_SET_FIELD(channel_mask,\n \t\t\t\t\t     VC4_HDMI_AUDIO_PACKET_CEA_MASK);\n \n@@ -1378,7 +1376,7 @@ static int vc4_hdmi_audio_prepare(struct\n \tchannel_map = vc4_hdmi->variant->channel_map(vc4_hdmi, channel_mask);\n \tHDMI_WRITE(HDMI_MAI_CHANNEL_MAP, channel_map);\n \tHDMI_WRITE(HDMI_AUDIO_PACKET_CONFIG, audio_packet_config);\n-\tvc4_hdmi_set_n_cts(vc4_hdmi);\n+\tvc4_hdmi_set_n_cts(vc4_hdmi, sample_rate);\n \n \tmemcpy(&vc4_hdmi->audio.infoframe, &params->cea, sizeof(params->cea));\n \tvc4_hdmi_set_audio_infoframe(encoder);\n--- a/drivers/gpu/drm/vc4/vc4_hdmi.h\n+++ b/drivers/gpu/drm/vc4/vc4_hdmi.h\n@@ -111,13 +111,9 @@ struct vc4_hdmi_audio {\n \tstruct snd_soc_dai_link_component cpu;\n \tstruct snd_soc_dai_link_component codec;\n \tstruct snd_soc_dai_link_component platform;\n-\tint samplerate;\n-\tint channels;\n \tstruct snd_dmaengine_dai_dma_data dma_data;\n \tstruct hdmi_audio_infoframe infoframe;\n \tbool streaming;\n-\n-\tunsigned char iec_status[4];\n };\n \n /* General HDMI hardware state. */\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0638-ARM-dts-bcm2711-Tune-DMA-parameters-for-HDMI-audio.patch",
    "content": "From 54643c62b6a848bfcfd86ac4eebbea28c0f1902e Mon Sep 17 00:00:00 2001\nFrom: Dom Cobley <popcornmix@gmail.com>\nDate: Wed, 28 Apr 2021 16:10:02 +0200\nSubject: [PATCH] ARM: dts: bcm2711: Tune DMA parameters for HDMI audio\n\nEnable NO_WAIT_RESP, DMA_WIDE_SOURCE, DMA_WIDE_DEST, and bump the DMA\npanic and AXI priorities to avoid any DMA transfer error with HBR audio\n(8 channel, 192Hz).\n\nSigned-off-by: Dom Cobley <popcornmix@gmail.com>\nSigned-off-by: Maxime Ripard <maxime@cerno.tech>\n---\n arch/arm/boot/dts/bcm2711.dtsi | 4 ++--\n 1 file changed, 2 insertions(+), 2 deletions(-)\n\n--- a/arch/arm/boot/dts/bcm2711.dtsi\n+++ b/arch/arm/boot/dts/bcm2711.dtsi\n@@ -360,7 +360,7 @@\n \t\t\tinterrupt-names = \"cec-tx\", \"cec-rx\", \"cec-low\",\n \t\t\t\t\t  \"wakeup\", \"hpd-connected\", \"hpd-removed\";\n \t\t\tddc = <&ddc0>;\n-\t\t\tdmas = <&dma 10>;\n+\t\t\tdmas = <&dma (10 | (1 << 27) | (1 << 24)| (15 << 20) | (10 << 16))>;\n \t\t\tdma-names = \"audio-rx\";\n \t\t\tstatus = \"disabled\";\n \t\t};\n@@ -407,7 +407,7 @@\n \t\t\t\t     <9>, <10>, <11>;\n \t\t\tinterrupt-names = \"cec-tx\", \"cec-rx\", \"cec-low\",\n \t\t\t\t\t  \"wakeup\", \"hpd-connected\", \"hpd-removed\";\n-\t\t\tdmas = <&dma 17>;\n+\t\t\tdmas = <&dma (17 | (1 << 27) | (1 << 24)| (15 << 20) | (10 << 16))>;\n \t\t\tdma-names = \"audio-rx\";\n \t\t\tstatus = \"disabled\";\n \t\t};\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0639-cgroup-Disable-cgroup-memory-by-default.patch",
    "content": "From 2b13c54592135b6fab269517ed687fa9f80bf8e5 Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.org>\nDate: Mon, 27 Nov 2017 17:14:54 +0000\nSubject: [PATCH] cgroup: Disable cgroup \"memory\" by default\n\nSome Raspberry Pis have limited RAM and most users won't use the\ncgroup memory support so it is disabled by default. Enable with:\n\n    cgroup_enable=memory\n\nSee: https://github.com/raspberrypi/linux/issues/1950\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.org>\n---\n kernel/cgroup/cgroup.c | 38 ++++++++++++++++++++++++++++++++++++++\n 1 file changed, 38 insertions(+)\n\n--- a/kernel/cgroup/cgroup.c\n+++ b/kernel/cgroup/cgroup.c\n@@ -5735,6 +5735,9 @@ int __init cgroup_init_early(void)\n \treturn 0;\n }\n \n+static u16 cgroup_enable_mask __initdata;\n+static int __init cgroup_disable(char *str);\n+\n /**\n  * cgroup_init - cgroup initialization\n  *\n@@ -5773,6 +5776,12 @@ int __init cgroup_init(void)\n \n \tmutex_unlock(&cgroup_mutex);\n \n+\t/*\n+\t * Apply an implicit disable, knowing that an explicit enable will\n+\t * prevent if from doing anything.\n+\t */\n+\tcgroup_disable(\"memory\");\n+\n \tfor_each_subsys(ss, ssid) {\n \t\tif (ss->early_init) {\n \t\t\tstruct cgroup_subsys_state *css =\n@@ -6311,6 +6320,10 @@ static int __init cgroup_disable(char *s\n \t\t\t    strcmp(token, ss->legacy_name))\n \t\t\t\tcontinue;\n \n+\t\t\t/* An explicit cgroup_enable overrides a disable */\n+\t\t\tif (cgroup_enable_mask & (1 << i))\n+\t\t\t\tcontinue;\n+\n \t\t\tstatic_branch_disable(cgroup_subsys_enabled_key[i]);\n \t\t\tpr_info(\"Disabling %s control group subsystem\\n\",\n \t\t\t\tss->name);\n@@ -6320,6 +6333,31 @@ static int __init cgroup_disable(char *s\n }\n __setup(\"cgroup_disable=\", cgroup_disable);\n \n+static int __init cgroup_enable(char *str)\n+{\n+\tstruct cgroup_subsys *ss;\n+\tchar *token;\n+\tint i;\n+\n+\twhile ((token = strsep(&str, \",\")) != NULL) {\n+\t\tif (!*token)\n+\t\t\tcontinue;\n+\n+\t\tfor_each_subsys(ss, i) {\n+\t\t\tif (strcmp(token, ss->name) &&\n+\t\t\t    strcmp(token, ss->legacy_name))\n+\t\t\t\tcontinue;\n+\n+\t\t\tcgroup_enable_mask |= 1 << i;\n+\t\t\tstatic_branch_enable(cgroup_subsys_enabled_key[i]);\n+\t\t\tpr_info(\"Enabling %s control group subsystem\\n\",\n+\t\t\t\tss->name);\n+\t\t}\n+\t}\n+\treturn 1;\n+}\n+__setup(\"cgroup_enable=\", cgroup_enable);\n+\n void __init __weak enable_debug_cgroup(void) { }\n \n static int __init enable_cgroup_debug(char *str)\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0640-media-i2c-imx290-Support-60fps-in-2-lane-operation.patch",
    "content": "From 5886d3655e1d876325ca348cf29fad3e92a45492 Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Thu, 17 Jun 2021 12:05:25 +0100\nSubject: [PATCH] media: i2c: imx290: Support 60fps in 2 lane operation\n\nCommit \"97589ad61c73 media: i2c: imx290: Add support for 2 data lanes\"\nadded support for running in two lane mode (instead of 4), but\nwithout changing the link frequency that resulted in a max of 30fps.\n\nCommit \"98e0500eadb7 media: i2c: imx290: Add configurable link frequency\nand pixel rate\" then doubled the link frequency when in 2 lane mode,\nbut didn't undo the correction for running at only 30fps, just extending\nhorizontal blanking instead.\nIt also didn't update the CSI timing registers in accordance with the\ndatasheet.\n\nRemove the 30fps limit on 2 lane by correcting the register config\nin accordance with the datasheet for 60fps operation over 2 lanes.\nFrame rate control (via V4L2_CID_VBLANK or HBLANK) can still reduce\nthe frame rate on 2 lanes back to 30fps.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n drivers/media/i2c/imx290.c | 163 ++++++++++++++++++++++---------------\n 1 file changed, 97 insertions(+), 66 deletions(-)\n\n--- a/drivers/media/i2c/imx290.c\n+++ b/drivers/media/i2c/imx290.c\n@@ -46,8 +46,7 @@ enum imx290_clk_index {\n #define IMX290_VMAX_MAX 0x3fff\n #define IMX290_HMAX_LOW 0x301c\n #define IMX290_HMAX_HIGH 0x301d\n-#define IMX290_HMAX_MIN_2LANE 4400 /* Min of 4400 pixels = 30fps */\n-#define IMX290_HMAX_MIN_4LANE 2200 /* Min of 2200 pixels = 60fps */\n+#define IMX290_HMAX_MIN 2200 /* Min of 2200 pixels = 60fps */\n #define IMX290_HMAX_MAX 0xffff\n \n #define IMX290_EXPOSURE_MIN 1\n@@ -89,8 +88,11 @@ struct imx290_mode {\n \tu8 link_freq_index;\n \tstruct v4l2_rect crop;\n \n-\tconst struct imx290_regval *data;\n-\tu32 data_size;\n+\tconst struct imx290_regval *mode_data;\n+\tu32 mode_data_size;\n+\tconst struct imx290_regval *lane_data;\n+\tu32 lane_data_size;\n+\n \n \t/* Clock setup can vary. Index as enum imx290_clk_index */\n \tconst struct imx290_regval *clk_data[2];\n@@ -242,8 +244,9 @@ static const struct imx290_regval imx290\n \t{ 0x3480, 0x92 },\n };\n \n-static const struct imx290_regval imx290_1080p_settings[] = {\n+static const struct imx290_regval imx290_1080p_common_settings[] = {\n \t/* mode settings */\n+\t{ IMX290_FR_FDG_SEL, 0x01 },\n \t{ 0x3007, 0x00 },\n \t{ 0x303a, 0x0c },\n \t{ 0x3414, 0x0a },\n@@ -253,8 +256,36 @@ static const struct imx290_regval imx290\n \t{ 0x3419, 0x04 },\n \t{ 0x3012, 0x64 },\n \t{ 0x3013, 0x00 },\n+};\n+\n+static const struct imx290_regval imx290_1080p_2lane_settings[] = {\n+\t{ 0x3405, 0x00 },\n \t/* data rate settings */\n+\t{ IMX290_PHY_LANE_NUM, 0x01 },\n+\t{ IMX290_CSI_LANE_MODE, 0x01 },\n+\t{ 0x3446, 0x77 },\n+\t{ 0x3447, 0x00 },\n+\t{ 0x3448, 0x67 },\n+\t{ 0x3449, 0x00 },\n+\t{ 0x344a, 0x47 },\n+\t{ 0x344b, 0x00 },\n+\t{ 0x344c, 0x37 },\n+\t{ 0x344d, 0x00 },\n+\t{ 0x344e, 0x3f },\n+\t{ 0x344f, 0x00 },\n+\t{ 0x3450, 0xff },\n+\t{ 0x3451, 0x00 },\n+\t{ 0x3452, 0x3f },\n+\t{ 0x3453, 0x00 },\n+\t{ 0x3454, 0x37 },\n+\t{ 0x3455, 0x00 },\n+};\n+\n+static const struct imx290_regval imx290_1080p_4lane_settings[] = {\n \t{ 0x3405, 0x10 },\n+\t/* data rate settings */\n+\t{ IMX290_PHY_LANE_NUM, 0x03 },\n+\t{ IMX290_CSI_LANE_MODE, 0x03 },\n \t{ 0x3446, 0x57 },\n \t{ 0x3447, 0x00 },\n \t{ 0x3448, 0x37 },\n@@ -297,8 +328,9 @@ static const struct imx290_regval imx290\n \t{ 0x3480, 0x92 },\n };\n \n-static const struct imx290_regval imx290_720p_settings[] = {\n+static const struct imx290_regval imx290_720p_common_settings[] = {\n \t/* mode settings */\n+\t{ IMX290_FR_FDG_SEL, 0x01 },\n \t{ 0x3007, 0x10 },\n \t{ 0x303a, 0x06 },\n \t{ 0x3414, 0x04 },\n@@ -308,8 +340,36 @@ static const struct imx290_regval imx290\n \t{ 0x3419, 0x02 },\n \t{ 0x3012, 0x64 },\n \t{ 0x3013, 0x00 },\n+};\n+\n+static const struct imx290_regval imx290_720p_2lane_settings[] = {\n+\t{ 0x3405, 0x00 },\n+\t{ IMX290_PHY_LANE_NUM, 0x01 },\n+\t{ IMX290_CSI_LANE_MODE, 0x01 },\n \t/* data rate settings */\n+\t{ 0x3446, 0x67 },\n+\t{ 0x3447, 0x00 },\n+\t{ 0x3448, 0x57 },\n+\t{ 0x3449, 0x00 },\n+\t{ 0x344a, 0x2f },\n+\t{ 0x344b, 0x00 },\n+\t{ 0x344c, 0x27 },\n+\t{ 0x344d, 0x00 },\n+\t{ 0x344e, 0x2f },\n+\t{ 0x344f, 0x00 },\n+\t{ 0x3450, 0xbf },\n+\t{ 0x3451, 0x00 },\n+\t{ 0x3452, 0x2f },\n+\t{ 0x3453, 0x00 },\n+\t{ 0x3454, 0x27 },\n+\t{ 0x3455, 0x00 },\n+};\n+\n+static const struct imx290_regval imx290_720p_4lane_settings[] = {\n \t{ 0x3405, 0x10 },\n+\t{ IMX290_PHY_LANE_NUM, 0x03 },\n+\t{ IMX290_CSI_LANE_MODE, 0x03 },\n+\t/* data rate settings */\n \t{ 0x3446, 0x4f },\n \t{ 0x3447, 0x00 },\n \t{ 0x3448, 0x2f },\n@@ -389,7 +449,7 @@ static const struct imx290_mode imx290_m\n \t{\n \t\t.width = 1920,\n \t\t.height = 1080,\n-\t\t.hmax = 0x1130,\n+\t\t.hmax = 0x0898,\n \t\t.vmax = 0x0465,\n \t\t.link_freq_index = FREQ_INDEX_1080P,\n \t\t.crop = {\n@@ -398,8 +458,10 @@ static const struct imx290_mode imx290_m\n \t\t\t.width = 1920,\n \t\t\t.height = 1080,\n \t\t},\n-\t\t.data = imx290_1080p_settings,\n-\t\t.data_size = ARRAY_SIZE(imx290_1080p_settings),\n+\t\t.mode_data = imx290_1080p_common_settings,\n+\t\t.mode_data_size = ARRAY_SIZE(imx290_1080p_common_settings),\n+\t\t.lane_data = imx290_1080p_2lane_settings,\n+\t\t.lane_data_size = ARRAY_SIZE(imx290_1080p_2lane_settings),\n \t\t.clk_data = {\n \t\t\t[CLK_37_125] = imx290_37_125mhz_clock_1080p,\n \t\t\t[CLK_74_25] = imx290_74_250mhz_clock_1080p,\n@@ -409,7 +471,7 @@ static const struct imx290_mode imx290_m\n \t{\n \t\t.width = 1280,\n \t\t.height = 720,\n-\t\t.hmax = 0x19c8,\n+\t\t.hmax = 0x0ce4,\n \t\t.vmax = 0x02ee,\n \t\t.link_freq_index = FREQ_INDEX_720P,\n \t\t.crop = {\n@@ -418,8 +480,10 @@ static const struct imx290_mode imx290_m\n \t\t\t.width = 1280,\n \t\t\t.height = 720,\n \t\t},\n-\t\t.data = imx290_720p_settings,\n-\t\t.data_size = ARRAY_SIZE(imx290_720p_settings),\n+\t\t.mode_data = imx290_720p_common_settings,\n+\t\t.mode_data_size = ARRAY_SIZE(imx290_720p_common_settings),\n+\t\t.lane_data = imx290_720p_2lane_settings,\n+\t\t.lane_data_size = ARRAY_SIZE(imx290_720p_2lane_settings),\n \t\t.clk_data = {\n \t\t\t[CLK_37_125] = imx290_37_125mhz_clock_1080p,\n \t\t\t[CLK_74_25] = imx290_74_250mhz_clock_1080p,\n@@ -441,8 +505,10 @@ static const struct imx290_mode imx290_m\n \t\t\t.width = 1920,\n \t\t\t.height = 1080,\n \t\t},\n-\t\t.data = imx290_1080p_settings,\n-\t\t.data_size = ARRAY_SIZE(imx290_1080p_settings),\n+\t\t.mode_data = imx290_1080p_common_settings,\n+\t\t.mode_data_size = ARRAY_SIZE(imx290_1080p_common_settings),\n+\t\t.lane_data = imx290_1080p_4lane_settings,\n+\t\t.lane_data_size = ARRAY_SIZE(imx290_1080p_4lane_settings),\n \t\t.clk_data = {\n \t\t\t[CLK_37_125] = imx290_37_125mhz_clock_720p,\n \t\t\t[CLK_74_25] = imx290_74_250mhz_clock_720p,\n@@ -461,8 +527,10 @@ static const struct imx290_mode imx290_m\n \t\t\t.width = 1280,\n \t\t\t.height = 720,\n \t\t},\n-\t\t.data = imx290_720p_settings,\n-\t\t.data_size = ARRAY_SIZE(imx290_720p_settings),\n+\t\t.mode_data = imx290_720p_common_settings,\n+\t\t.mode_data_size = ARRAY_SIZE(imx290_720p_common_settings),\n+\t\t.lane_data = imx290_720p_4lane_settings,\n+\t\t.lane_data_size = ARRAY_SIZE(imx290_720p_4lane_settings),\n \t\t.clk_data = {\n \t\t\t[CLK_37_125] = imx290_37_125mhz_clock_720p,\n \t\t\t[CLK_74_25] = imx290_74_250mhz_clock_720p,\n@@ -1016,8 +1084,18 @@ static int imx290_start_streaming(struct\n \t}\n \n \t/* Apply default values of current mode */\n-\tret = imx290_set_register_array(imx290, imx290->current_mode->data,\n-\t\t\t\t\timx290->current_mode->data_size);\n+\tret = imx290_set_register_array(imx290,\n+\t\t\t\t\timx290->current_mode->mode_data,\n+\t\t\t\t\timx290->current_mode->mode_data_size);\n+\tif (ret < 0) {\n+\t\tdev_err(imx290->dev, \"Could not set current mode\\n\");\n+\t\treturn ret;\n+\t}\n+\n+\t/* Apply lane config registers of current mode */\n+\tret = imx290_set_register_array(imx290,\n+\t\t\t\t\timx290->current_mode->lane_data,\n+\t\t\t\t\timx290->current_mode->lane_data_size);\n \tif (ret < 0) {\n \t\tdev_err(imx290->dev, \"Could not set current mode\\n\");\n \t\treturn ret;\n@@ -1082,49 +1160,6 @@ static int imx290_get_regulators(struct\n \t\t\t\t       imx290->supplies);\n }\n \n-static int imx290_set_data_lanes(struct imx290 *imx290)\n-{\n-\tint ret = 0, laneval, frsel;\n-\n-\tswitch (imx290->nlanes) {\n-\tcase 2:\n-\t\tlaneval = 0x01;\n-\t\tfrsel = 0x02;\n-\t\tbreak;\n-\tcase 4:\n-\t\tlaneval = 0x03;\n-\t\tfrsel = 0x01;\n-\t\tbreak;\n-\tdefault:\n-\t\t/*\n-\t\t * We should never hit this since the data lane count is\n-\t\t * validated in probe itself\n-\t\t */\n-\t\tdev_err(imx290->dev, \"Lane configuration not supported\\n\");\n-\t\tret = -EINVAL;\n-\t\tgoto exit;\n-\t}\n-\n-\tret = imx290_write_reg(imx290, IMX290_PHY_LANE_NUM, laneval);\n-\tif (ret) {\n-\t\tdev_err(imx290->dev, \"Error setting Physical Lane number register\\n\");\n-\t\tgoto exit;\n-\t}\n-\n-\tret = imx290_write_reg(imx290, IMX290_CSI_LANE_MODE, laneval);\n-\tif (ret) {\n-\t\tdev_err(imx290->dev, \"Error setting CSI Lane mode register\\n\");\n-\t\tgoto exit;\n-\t}\n-\n-\tret = imx290_write_reg(imx290, IMX290_FR_FDG_SEL, frsel);\n-\tif (ret)\n-\t\tdev_err(imx290->dev, \"Error setting FR/FDG SEL register\\n\");\n-\n-exit:\n-\treturn ret;\n-}\n-\n static int imx290_power_on(struct device *dev)\n {\n \tstruct i2c_client *client = to_i2c_client(dev);\n@@ -1149,9 +1184,6 @@ static int imx290_power_on(struct device\n \tgpiod_set_value_cansleep(imx290->rst_gpio, 0);\n \tusleep_range(30000, 31000);\n \n-\t/* Set data lane count */\n-\timx290_set_data_lanes(imx290);\n-\n \treturn 0;\n }\n \n@@ -1275,8 +1307,7 @@ static int imx290_probe(struct i2c_clien\n \t\tret = -EINVAL;\n \t\tgoto free_err;\n \t}\n-\timx290->hmax_min = (imx290->nlanes == 2) ? IMX290_HMAX_MIN_2LANE :\n-\t\t\t\t\t\t IMX290_HMAX_MIN_4LANE;\n+\timx290->hmax_min = IMX290_HMAX_MIN;\n \n \tdev_dbg(dev, \"Using %u data lanes\\n\", imx290->nlanes);\n \n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0641-media-i2c-imx290-Fix-the-pixel-rate-at-148.5Mpix-s.patch",
    "content": "From 3393c38cc1462337f40e24be91f47974bcfc3e4c Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Thu, 17 Jun 2021 13:00:39 +0100\nSubject: [PATCH] media: i2c: imx290: Fix the pixel rate at 148.5Mpix/s\n\nWhilst the datasheet lists the link frequency changing between\n1080p and 720p modes, reality is that with the default blanking\nwe have\n(1920 + 280) * (1080 + 45) * 60fps = 148.5MPix/s\nand\n(1280 + 2020) * (720 + 30) * 60fps = 148.5MPix/s\nand this reflects reality whether in 10 or 12 bit readout modes.\n\nHow this relates to link frequency is unclear as it differs\nfrom the datasheet, but all exposure and frame rate calcs need\nthe pixel rate to be correct, so make it so.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n drivers/media/i2c/imx290.c | 16 +---------------\n 1 file changed, 1 insertion(+), 15 deletions(-)\n\n--- a/drivers/media/i2c/imx290.c\n+++ b/drivers/media/i2c/imx290.c\n@@ -853,23 +853,9 @@ static inline u8 imx290_get_link_freq_in\n \treturn imx290->current_mode->link_freq_index;\n }\n \n-static s64 imx290_get_link_freq(struct imx290 *imx290)\n-{\n-\tu8 index = imx290_get_link_freq_index(imx290);\n-\n-\treturn *(imx290_link_freqs_ptr(imx290) + index);\n-}\n-\n static u64 imx290_calc_pixel_rate(struct imx290 *imx290)\n {\n-\ts64 link_freq = imx290_get_link_freq(imx290);\n-\tu8 nlanes = imx290->nlanes;\n-\tu64 pixel_rate;\n-\n-\t/* pixel rate = link_freq * 2 * nr_of_lanes / bits_per_sample */\n-\tpixel_rate = link_freq * 2 * nlanes;\n-\tdo_div(pixel_rate, imx290->bpp);\n-\treturn pixel_rate;\n+\treturn 148500000;\n }\n \n static int imx290_set_fmt(struct v4l2_subdev *sd,\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0642-media-i2c-imx290-Fix-clock-setup-register-assignment.patch",
    "content": "From d9e5544f2fe6d7a6da8dd618c09b7564acc5be31 Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Thu, 17 Jun 2021 17:27:46 +0100\nSubject: [PATCH] media: i2c: imx290: Fix clock setup register\n assignments\n\nWhen the clock setups were added for the alternate external clocks,\nthe settings for 2 lane 720p and 4 lane 1080p were transposed.\n2 lane 720p still worked, but 4 lane 1080p didn't.\n\nCorrect the assignments.\n\nFixes: 6b0c094a5b58 (media: i2c: imx290: Add support for 74.25MHz clock\")\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n drivers/media/i2c/imx290.c | 12 ++++++------\n 1 file changed, 6 insertions(+), 6 deletions(-)\n\n--- a/drivers/media/i2c/imx290.c\n+++ b/drivers/media/i2c/imx290.c\n@@ -485,10 +485,10 @@ static const struct imx290_mode imx290_m\n \t\t.lane_data = imx290_720p_2lane_settings,\n \t\t.lane_data_size = ARRAY_SIZE(imx290_720p_2lane_settings),\n \t\t.clk_data = {\n-\t\t\t[CLK_37_125] = imx290_37_125mhz_clock_1080p,\n-\t\t\t[CLK_74_25] = imx290_74_250mhz_clock_1080p,\n+\t\t\t[CLK_37_125] = imx290_37_125mhz_clock_720p,\n+\t\t\t[CLK_74_25] = imx290_74_250mhz_clock_720p,\n \t\t},\n-\t\t.clk_size = ARRAY_SIZE(imx290_37_125mhz_clock_1080p),\n+\t\t.clk_size = ARRAY_SIZE(imx290_37_125mhz_clock_720p),\n \t},\n };\n \n@@ -510,10 +510,10 @@ static const struct imx290_mode imx290_m\n \t\t.lane_data = imx290_1080p_4lane_settings,\n \t\t.lane_data_size = ARRAY_SIZE(imx290_1080p_4lane_settings),\n \t\t.clk_data = {\n-\t\t\t[CLK_37_125] = imx290_37_125mhz_clock_720p,\n-\t\t\t[CLK_74_25] = imx290_74_250mhz_clock_720p,\n+\t\t\t[CLK_37_125] = imx290_37_125mhz_clock_1080p,\n+\t\t\t[CLK_74_25] = imx290_74_250mhz_clock_1080p,\n \t\t},\n-\t\t.clk_size = ARRAY_SIZE(imx290_37_125mhz_clock_720p),\n+\t\t.clk_size = ARRAY_SIZE(imx290_37_125mhz_clock_1080p),\n \t},\n \t{\n \t\t.width = 1280,\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0643-drm-vc4-crtc-Add-encoder-to-vc4_crtc_config_pv-proto.patch",
    "content": "From 23771cfafeedba325b6e9d7dedde11eb25381d67 Mon Sep 17 00:00:00 2001\nFrom: Maxime Ripard <maxime@cerno.tech>\nDate: Mon, 14 Jun 2021 15:27:24 +0200\nSubject: [PATCH] drm/vc4: crtc: Add encoder to vc4_crtc_config_pv\n prototype\n\nvc4_crtc_config_pv() retrieves the encoder again, even though its only\ncaller, vc4_crtc_atomic_enable(), already did.\n\nPass the encoder pointer as an argument instead of going through all the\nconnectors to retrieve it again.\n\nSigned-off-by: Maxime Ripard <maxime@cerno.tech>\n---\n drivers/gpu/drm/vc4/vc4_crtc.c | 7 +++----\n 1 file changed, 3 insertions(+), 4 deletions(-)\n\n--- a/drivers/gpu/drm/vc4/vc4_crtc.c\n+++ b/drivers/gpu/drm/vc4/vc4_crtc.c\n@@ -313,12 +313,11 @@ static void vc4_crtc_pixelvalve_reset(st\n \tCRTC_WRITE(PV_CONTROL, CRTC_READ(PV_CONTROL) | PV_CONTROL_FIFO_CLR);\n }\n \n-static void vc4_crtc_config_pv(struct drm_crtc *crtc, struct drm_atomic_state *state)\n+static void vc4_crtc_config_pv(struct drm_crtc *crtc, struct drm_encoder *encoder,\n+\t\t\t       struct drm_atomic_state *state)\n {\n \tstruct drm_device *dev = crtc->dev;\n \tstruct vc4_dev *vc4 = to_vc4_dev(dev);\n-\tstruct drm_encoder *encoder = vc4_get_crtc_encoder(crtc, state,\n-\t\t\t\t\t\t\t   drm_atomic_get_new_connector_state);\n \tstruct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder);\n \tstruct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);\n \tconst struct vc4_pv_data *pv_data = vc4_crtc_to_vc4_pv_data(vc4_crtc);\n@@ -581,7 +580,7 @@ static void vc4_crtc_atomic_enable(struc\n \tif (vc4_encoder->pre_crtc_configure)\n \t\tvc4_encoder->pre_crtc_configure(encoder, state);\n \n-\tvc4_crtc_config_pv(crtc, state);\n+\tvc4_crtc_config_pv(crtc, encoder, state);\n \n \tCRTC_WRITE(PV_CONTROL, CRTC_READ(PV_CONTROL) | PV_CONTROL_EN);\n \n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0644-drm-vc4-crtc-Rework-the-encoder-retrieval-code-again.patch",
    "content": "From f1712f12335eb07211fe2869e8daee521f558ae1 Mon Sep 17 00:00:00 2001\nFrom: Maxime Ripard <maxime@cerno.tech>\nDate: Mon, 21 Jun 2021 16:07:22 +0200\nSubject: [PATCH] drm/vc4: crtc: Rework the encoder retrieval code\n (again)\n\nIt turns out the encoder retrieval code, in addition to being\nunnecessarily complicated, has a bug when only the planes and crtcs are\naffected by a given atomic commit.\n\nIndeed, in such a case, either drm_atomic_get_old_connector_state or\ndrm_atomic_get_new_connector_state will return NULL and thus our encoder\nretrieval code will not match on anything.\n\nWe can however simplify the code by using drm_for_each_encoder_mask, the\ndrm_crtc_state storing the encoders a given CRTC is connected to\ndirectly and without relying on any other state.\n\nSigned-off-by: Maxime Ripard <maxime@cerno.tech>\n---\n drivers/gpu/drm/vc4/vc4_crtc.c | 30 +++++++++---------------------\n drivers/gpu/drm/vc4/vc4_drv.h  |  4 +---\n 2 files changed, 10 insertions(+), 24 deletions(-)\n\n--- a/drivers/gpu/drm/vc4/vc4_crtc.c\n+++ b/drivers/gpu/drm/vc4/vc4_crtc.c\n@@ -280,26 +280,14 @@ static u32 vc4_crtc_get_fifo_full_level_\n  * same CRTC.\n  */\n struct drm_encoder *vc4_get_crtc_encoder(struct drm_crtc *crtc,\n-\t\t\t\t\t struct drm_atomic_state *state,\n-\t\t\t\t\t struct drm_connector_state *(*get_state)(struct drm_atomic_state *state,\n-\t\t\t\t\t\t\t\t\t\t  struct drm_connector *connector))\n+\t\t\t\t\t struct drm_crtc_state *state)\n {\n-\tstruct drm_connector *connector;\n-\tstruct drm_connector_list_iter conn_iter;\n+\tstruct drm_encoder *encoder;\n \n-\tdrm_connector_list_iter_begin(crtc->dev, &conn_iter);\n-\tdrm_for_each_connector_iter(connector, &conn_iter) {\n-\t\tstruct drm_connector_state *conn_state = get_state(state, connector);\n-\n-\t\tif (!conn_state)\n-\t\t\tcontinue;\n-\n-\t\tif (conn_state->crtc == crtc) {\n-\t\t\tdrm_connector_list_iter_end(&conn_iter);\n-\t\t\treturn connector->encoder;\n-\t\t}\n-\t}\n-\tdrm_connector_list_iter_end(&conn_iter);\n+\tWARN_ON(hweight32(state->encoder_mask) > 1);\n+\n+\tdrm_for_each_encoder_mask(encoder, crtc->dev, state->encoder_mask)\n+\t\treturn encoder;\n \n \treturn NULL;\n }\n@@ -534,8 +522,7 @@ static void vc4_crtc_atomic_disable(stru\n \tstruct drm_crtc_state *old_state = drm_atomic_get_old_crtc_state(state,\n \t\t\t\t\t\t\t\t\t crtc);\n \tstruct vc4_crtc_state *old_vc4_state = to_vc4_crtc_state(old_state);\n-\tstruct drm_encoder *encoder = vc4_get_crtc_encoder(crtc, state,\n-\t\t\t\t\t\t\t   drm_atomic_get_old_connector_state);\n+\tstruct drm_encoder *encoder = vc4_get_crtc_encoder(crtc, old_state);\n \tstruct drm_device *dev = crtc->dev;\n \n \trequire_hvs_enabled(dev);\n@@ -562,10 +549,11 @@ static void vc4_crtc_atomic_disable(stru\n static void vc4_crtc_atomic_enable(struct drm_crtc *crtc,\n \t\t\t\t   struct drm_atomic_state *state)\n {\n+\tstruct drm_crtc_state *new_state = drm_atomic_get_new_crtc_state(state,\n+\t\t\t\t\t\t\t\t\t crtc);\n \tstruct drm_device *dev = crtc->dev;\n \tstruct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);\n-\tstruct drm_encoder *encoder = vc4_get_crtc_encoder(crtc, state,\n-\t\t\t\t\t\t\t   drm_atomic_get_new_connector_state);\n+\tstruct drm_encoder *encoder = vc4_get_crtc_encoder(crtc, new_state);\n \tstruct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder);\n \n \trequire_hvs_enabled(dev);\n--- a/drivers/gpu/drm/vc4/vc4_drv.h\n+++ b/drivers/gpu/drm/vc4/vc4_drv.h\n@@ -523,9 +523,7 @@ vc4_crtc_to_vc4_pv_data(const struct vc4\n }\n \n struct drm_encoder *vc4_get_crtc_encoder(struct drm_crtc *crtc,\n-\t\t\t\t\t struct drm_atomic_state *state,\n-\t\t\t\t\t struct drm_connector_state *(*get_state)(struct drm_atomic_state *state,\n-\t\t\t\t\t\t\t\t\t\t  struct drm_connector *connector));\n+\t\t\t\t\t struct drm_crtc_state *state);\n \n struct vc4_crtc_state {\n \tstruct drm_crtc_state base;\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0645-drm-vc4-crtc-Add-some-logging.patch",
    "content": "From bcdc0a4520ea59c3e888ebb91c8f41e55841297d Mon Sep 17 00:00:00 2001\nFrom: Maxime Ripard <maxime@cerno.tech>\nDate: Mon, 21 Jun 2021 16:13:02 +0200\nSubject: [PATCH] drm/vc4: crtc: Add some logging\n\nThe encoder retrieval code has been a source of bugs and glitches in the\npast and the crtc <-> encoder association been wrong in a number of\ndifferent ways.\n\nAdd some logging to quickly spot issues if they occur.\n\nSigned-off-by: Maxime Ripard <maxime@cerno.tech>\n---\n drivers/gpu/drm/vc4/vc4_crtc.c | 6 ++++++\n 1 file changed, 6 insertions(+)\n\n--- a/drivers/gpu/drm/vc4/vc4_crtc.c\n+++ b/drivers/gpu/drm/vc4/vc4_crtc.c\n@@ -525,6 +525,9 @@ static void vc4_crtc_atomic_disable(stru\n \tstruct drm_encoder *encoder = vc4_get_crtc_encoder(crtc, old_state);\n \tstruct drm_device *dev = crtc->dev;\n \n+\tdrm_dbg(dev, \"Disabling CRTC %s (%u) connected to Encoder %s (%u)\",\n+\t\tcrtc->name, crtc->base.id, encoder->name, encoder->base.id);\n+\n \trequire_hvs_enabled(dev);\n \n \t/* Disable vblank irq handling before crtc is disabled. */\n@@ -556,6 +559,9 @@ static void vc4_crtc_atomic_enable(struc\n \tstruct drm_encoder *encoder = vc4_get_crtc_encoder(crtc, new_state);\n \tstruct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder);\n \n+\tdrm_dbg(dev, \"Enabling CRTC %s (%u) connected to Encoder %s (%u)\",\n+\t\tcrtc->name, crtc->base.id, encoder->name, encoder->base.id);\n+\n \trequire_hvs_enabled(dev);\n \n \t/* Enable vblank irq handling before crtc is started otherwise\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0646-drm-vc4-Leverage-the-load-tracker-on-the-BCM2711.patch",
    "content": "From e404d30f2b14a83f223aab6c92da2a52d1c91f61 Mon Sep 17 00:00:00 2001\nFrom: Maxime Ripard <maxime@cerno.tech>\nDate: Mon, 21 Jun 2021 17:19:22 +0200\nSubject: [PATCH] drm/vc4: Leverage the load tracker on the BCM2711\n\nThe load tracker was initially designed to report and warn about a load\ntoo high for the HVS. To do so, it computes for each plane the impact\nit's going to have on the HVS, and will warn (if it's enabled) if we go\nover what the hardware can process.\n\nWhile the limits being used are a bit irrelevant to the BCM2711, the\nalgorithm to compute the HVS load will be one component used in order to\ncompute the core clock rate on the BCM2711.\n\nLet's remove the hooks to prevent the load tracker to do its\ncomputation, but since we don't have the same limits, don't check them\nagainst them, and prevent the debugfs file to enable it from being\ncreated.\n\nSigned-off-by: Maxime Ripard <maxime@cerno.tech>\n---\n drivers/gpu/drm/vc4/vc4_debugfs.c |  7 +++++--\n drivers/gpu/drm/vc4/vc4_drv.h     |  3 ---\n drivers/gpu/drm/vc4/vc4_kms.c     | 16 +++++-----------\n drivers/gpu/drm/vc4/vc4_plane.c   |  3 ---\n 4 files changed, 10 insertions(+), 19 deletions(-)\n\n--- a/drivers/gpu/drm/vc4/vc4_debugfs.c\n+++ b/drivers/gpu/drm/vc4/vc4_debugfs.c\n@@ -7,6 +7,7 @@\n #include <linux/circ_buf.h>\n #include <linux/ctype.h>\n #include <linux/debugfs.h>\n+#include <linux/platform_device.h>\n \n #include \"vc4_drv.h\"\n #include \"vc4_regs.h\"\n@@ -26,8 +27,10 @@ vc4_debugfs_init(struct drm_minor *minor\n \tstruct vc4_dev *vc4 = to_vc4_dev(minor->dev);\n \tstruct vc4_debugfs_info_entry *entry;\n \n-\tdebugfs_create_bool(\"hvs_load_tracker\", S_IRUGO | S_IWUSR,\n-\t\t\t    minor->debugfs_root, &vc4->load_tracker_enabled);\n+\tif (!of_device_is_compatible(vc4->hvs->pdev->dev.of_node,\n+\t\t\t\t     \"brcm,bcm2711-vc5\"))\n+\t\tdebugfs_create_bool(\"hvs_load_tracker\", S_IRUGO | S_IWUSR,\n+\t\t\t\t    minor->debugfs_root, &vc4->load_tracker_enabled);\n \n \tlist_for_each_entry(entry, &vc4->debugfs_list, link) {\n \t\tdrm_debugfs_create_files(&entry->info, 1,\n--- a/drivers/gpu/drm/vc4/vc4_drv.h\n+++ b/drivers/gpu/drm/vc4/vc4_drv.h\n@@ -205,9 +205,6 @@ struct vc4_dev {\n \n \tint power_refcount;\n \n-\t/* Set to true when the load tracker is supported. */\n-\tbool load_tracker_available;\n-\n \t/* Set to true when the load tracker is active. */\n \tbool load_tracker_enabled;\n \n--- a/drivers/gpu/drm/vc4/vc4_kms.c\n+++ b/drivers/gpu/drm/vc4/vc4_kms.c\n@@ -598,9 +598,6 @@ static int vc4_load_tracker_atomic_check\n \tstruct drm_plane *plane;\n \tint i;\n \n-\tif (!vc4->load_tracker_available)\n-\t\treturn 0;\n-\n \tpriv_state = drm_atomic_get_private_obj_state(state,\n \t\t\t\t\t\t      &vc4->load_tracker);\n \tif (IS_ERR(priv_state))\n@@ -675,9 +672,6 @@ static void vc4_load_tracker_obj_fini(st\n {\n \tstruct vc4_dev *vc4 = to_vc4_dev(dev);\n \n-\tif (!vc4->load_tracker_available)\n-\t\treturn;\n-\n \tdrm_atomic_private_obj_fini(&vc4->load_tracker);\n }\n \n@@ -685,9 +679,6 @@ static int vc4_load_tracker_obj_init(str\n {\n \tstruct vc4_load_tracker_state *load_state;\n \n-\tif (!vc4->load_tracker_available)\n-\t\treturn 0;\n-\n \tload_state = kzalloc(sizeof(*load_state), GFP_KERNEL);\n \tif (!load_state)\n \t\treturn -ENOMEM;\n@@ -891,9 +882,12 @@ int vc4_kms_load(struct drm_device *dev)\n \t\t\t\t\t      \"brcm,bcm2711-vc5\");\n \tint ret;\n \n+\t/*\n+\t * The limits enforced by the load tracker aren't relevant for\n+\t * the BCM2711, but the load tracker computations are used for\n+\t * the core clock rate calculation.\n+\t */\n \tif (!is_vc5) {\n-\t\tvc4->load_tracker_available = true;\n-\n \t\t/* Start with the load tracker enabled. Can be\n \t\t * disabled through the debugfs load_tracker file.\n \t\t */\n--- a/drivers/gpu/drm/vc4/vc4_plane.c\n+++ b/drivers/gpu/drm/vc4/vc4_plane.c\n@@ -534,9 +534,6 @@ static void vc4_plane_calc_load(struct d\n \tstruct vc4_dev *vc4;\n \n \tvc4 = to_vc4_dev(state->plane->dev);\n-\tif (!vc4->load_tracker_available)\n-\t\treturn;\n-\n \tvc4_state = to_vc4_plane_state(state);\n \tcrtc_state = drm_atomic_get_existing_crtc_state(state->state,\n \t\t\t\t\t\t\tstate->crtc);\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0647-drm-vc4-Fix-timings-for-interlaced-modes.patch",
    "content": "From 5afb722d255335954c6b67470e0d261ea5d5ab7a Mon Sep 17 00:00:00 2001\nFrom: kFYatek <4499762+kFYatek@users.noreply.github.com>\nDate: Wed, 23 Jun 2021 01:11:26 +0200\nSubject: [PATCH] drm/vc4: Fix timings for interlaced modes\n\nIncrease the number of post-sync blanking lines on odd fields instead of\ndecreasing it on even fields. This makes the total number of lines\nproperly match the modelines.\n\nAdditionally fix the value of PV_VCONTROL_ODD_DELAY, which did not take\npixels_per_clock into account, causing some displays to invert the\nfields when driven by bcm2711.\n\nSigned-off-by: Mateusz Kwiatkowski <kfyatek+publicgit@gmail.com>\n---\n drivers/gpu/drm/vc4/vc4_crtc.c |  7 ++++---\n drivers/gpu/drm/vc4/vc4_hdmi.c | 12 ++++++------\n 2 files changed, 10 insertions(+), 9 deletions(-)\n\n--- a/drivers/gpu/drm/vc4/vc4_crtc.c\n+++ b/drivers/gpu/drm/vc4/vc4_crtc.c\n@@ -342,7 +342,8 @@ static void vc4_crtc_config_pv(struct dr\n \t\t\t\t PV_HORZB_HACTIVE));\n \n \tCRTC_WRITE(PV_VERTA,\n-\t\t   VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,\n+\t\t   VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end +\n+\t\t\t\t interlace,\n \t\t\t\t PV_VERTA_VBP) |\n \t\t   VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,\n \t\t\t\t PV_VERTA_VSYNC));\n@@ -354,7 +355,7 @@ static void vc4_crtc_config_pv(struct dr\n \tif (interlace) {\n \t\tCRTC_WRITE(PV_VERTA_EVEN,\n \t\t\t   VC4_SET_FIELD(mode->crtc_vtotal -\n-\t\t\t\t\t mode->crtc_vsync_end - 1,\n+\t\t\t\t\t mode->crtc_vsync_end,\n \t\t\t\t\t PV_VERTA_VBP) |\n \t\t\t   VC4_SET_FIELD(mode->crtc_vsync_end -\n \t\t\t\t\t mode->crtc_vsync_start,\n@@ -374,7 +375,7 @@ static void vc4_crtc_config_pv(struct dr\n \t\t\t   PV_VCONTROL_CONTINUOUS |\n \t\t\t   (is_dsi ? PV_VCONTROL_DSI : 0) |\n \t\t\t   PV_VCONTROL_INTERLACE |\n-\t\t\t   VC4_SET_FIELD(mode->htotal * pixel_rep / 2,\n+\t\t\t   VC4_SET_FIELD(mode->htotal * pixel_rep / (2 * ppc),\n \t\t\t\t\t PV_VCONTROL_ODD_DELAY));\n \t\tCRTC_WRITE(PV_VSYNCD_EVEN, 0);\n \t} else {\n--- a/drivers/gpu/drm/vc4/vc4_hdmi.c\n+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c\n@@ -736,12 +736,12 @@ static void vc4_hdmi_set_timings(struct\n \t\t\t\t   VC4_HDMI_VERTA_VFP) |\n \t\t     VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL));\n \tu32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |\n-\t\t     VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,\n+\t\t     VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end +\n+\t\t\t\t   interlaced,\n \t\t\t\t   VC4_HDMI_VERTB_VBP));\n \tu32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |\n \t\t\t  VC4_SET_FIELD(mode->crtc_vtotal -\n-\t\t\t\t\tmode->crtc_vsync_end -\n-\t\t\t\t\tinterlaced,\n+\t\t\t\t\tmode->crtc_vsync_end,\n \t\t\t\t\tVC4_HDMI_VERTB_VBP));\n \n \tHDMI_WRITE(HDMI_HORZA,\n@@ -782,12 +782,12 @@ static void vc5_hdmi_set_timings(struct\n \t\t\t\t   VC5_HDMI_VERTA_VFP) |\n \t\t     VC4_SET_FIELD(mode->crtc_vdisplay, VC5_HDMI_VERTA_VAL));\n \tu32 vertb = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) |\n-\t\t     VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,\n+\t\t     VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end +\n+\t\t\t\t   interlaced,\n \t\t\t\t   VC4_HDMI_VERTB_VBP));\n \tu32 vertb_even = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) |\n \t\t\t  VC4_SET_FIELD(mode->crtc_vtotal -\n-\t\t\t\t\tmode->crtc_vsync_end -\n-\t\t\t\t\tinterlaced,\n+\t\t\t\t\tmode->crtc_vsync_end,\n \t\t\t\t\tVC4_HDMI_VERTB_VBP));\n \tunsigned char gcp;\n \tbool gcp_en;\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0648-drm-vc4-Don-t-create-hvs_load_tracker-on-fkms.patch",
    "content": "From d695c7afe2e688663041f8861ebd31c1e8275f27 Mon Sep 17 00:00:00 2001\nFrom: Dom Cobley <popcornmix@gmail.com>\nDate: Thu, 24 Jun 2021 12:00:49 +0100\nSubject: [PATCH] drm/vc4: Don't create hvs_load_tracker on fkms\n\nfkms doesn't use vc4->hvs so protect against that\n\nSigned-off-by: Dom Cobley <popcornmix@gmail.com>\n---\n drivers/gpu/drm/vc4/vc4_debugfs.c | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/drivers/gpu/drm/vc4/vc4_debugfs.c\n+++ b/drivers/gpu/drm/vc4/vc4_debugfs.c\n@@ -27,7 +27,7 @@ vc4_debugfs_init(struct drm_minor *minor\n \tstruct vc4_dev *vc4 = to_vc4_dev(minor->dev);\n \tstruct vc4_debugfs_info_entry *entry;\n \n-\tif (!of_device_is_compatible(vc4->hvs->pdev->dev.of_node,\n+\tif (vc4->hvs && !of_device_is_compatible(vc4->hvs->pdev->dev.of_node,\n \t\t\t\t     \"brcm,bcm2711-vc5\"))\n \t\tdebugfs_create_bool(\"hvs_load_tracker\", S_IRUGO | S_IWUSR,\n \t\t\t\t    minor->debugfs_root, &vc4->load_tracker_enabled);\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0649-media-rpivid-Fix-H265-aux-ent-reuse-of-the-same-slot.patch",
    "content": "From e3e645fde7d3141767c52a1ae0ffd2f94d0046a4 Mon Sep 17 00:00:00 2001\nFrom: John Cox <jc@kynesim.co.uk>\nDate: Thu, 24 Jun 2021 14:43:49 +0100\nSubject: [PATCH] media: rpivid: Fix H265 aux ent reuse of the same\n slot\n\nIt is legitimate, though unusual, for an aux ent associated with a slot\nto be selected in phase 0 before a previous selection has been used and\nreleased in phase 2. Fix such that if the slot is found to be in use\nthat the aux ent associated with it is reused rather than an new aux\nent being created. This fixes a problem where when the first aux ent\nwas released the second was lost track of.\n\nThis bug spotted in Nick's testing. It may explain some other occasional,\nunreliable decode error reports where dmesg included \"Missing DPB AUX\nent\" logging.\n\nSigned-off-by: John Cox <jc@kynesim.co.uk>\n---\n drivers/staging/media/rpivid/rpivid_h265.c | 75 ++++++++++++++--------\n 1 file changed, 49 insertions(+), 26 deletions(-)\n\n--- a/drivers/staging/media/rpivid/rpivid_h265.c\n+++ b/drivers/staging/media/rpivid/rpivid_h265.c\n@@ -371,7 +371,8 @@ static void aux_q_free(struct rpivid_ctx\n \tkfree(aq);\n }\n \n-static struct rpivid_q_aux *aux_q_alloc(struct rpivid_ctx *const ctx)\n+static struct rpivid_q_aux *aux_q_alloc(struct rpivid_ctx *const ctx,\n+\t\t\t\t\tconst unsigned int q_index)\n {\n \tstruct rpivid_dev *const dev = ctx->dev;\n \tstruct rpivid_q_aux *const aq = kzalloc(sizeof(*aq), GFP_KERNEL);\n@@ -379,11 +380,17 @@ static struct rpivid_q_aux *aux_q_alloc(\n \tif (!aq)\n \t\treturn NULL;\n \n-\taq->refcount = 1;\n \tif (gptr_alloc(dev, &aq->col, ctx->colmv_picsize,\n \t\t       DMA_ATTR_FORCE_CONTIGUOUS | DMA_ATTR_NO_KERNEL_MAPPING))\n \t\tgoto fail;\n \n+\t/*\n+\t * Spinlock not required as called in P0 only and\n+\t * aux checks done by _new\n+\t */\n+\taq->refcount = 1;\n+\taq->q_index = q_index;\n+\tctx->aux_ents[q_index] = aq;\n \treturn aq;\n \n fail:\n@@ -398,22 +405,38 @@ static struct rpivid_q_aux *aux_q_new(st\n \tunsigned long lockflags;\n \n \tspin_lock_irqsave(&ctx->aux_lock, lockflags);\n-\taq = ctx->aux_free;\n-\tif (aq) {\n+\t/*\n+\t * If we already have this allocated to a slot then use that\n+\t * and assume that it will all work itself out in the pipeline\n+\t */\n+\tif ((aq = ctx->aux_ents[q_index]) != NULL) {\n+\t\t++aq->refcount;\n+\t} else if ((aq = ctx->aux_free) != NULL) {\n \t\tctx->aux_free = aq->next;\n \t\taq->next = NULL;\n \t\taq->refcount = 1;\n+\t\taq->q_index = q_index;\n+\t\tctx->aux_ents[q_index] = aq;\n \t}\n \tspin_unlock_irqrestore(&ctx->aux_lock, lockflags);\n \n-\tif (!aq) {\n-\t\taq = aux_q_alloc(ctx);\n-\t\tif (!aq)\n-\t\t\treturn NULL;\n-\t}\n+\tif (!aq)\n+\t\taq = aux_q_alloc(ctx, q_index);\n+\n+\treturn aq;\n+}\n+\n+static struct rpivid_q_aux *aux_q_ref_idx(struct rpivid_ctx *const ctx,\n+\t\t\t\t\t  const int q_index)\n+{\n+\tunsigned long lockflags;\n+\tstruct rpivid_q_aux *aq;\n+\n+\tspin_lock_irqsave(&ctx->aux_lock, lockflags);\n+\tif ((aq = ctx->aux_ents[q_index]) != NULL)\n+\t\t++aq->refcount;\n+\tspin_unlock_irqrestore(&ctx->aux_lock, lockflags);\n \n-\taq->q_index = q_index;\n-\tctx->aux_ents[q_index] = aq;\n \treturn aq;\n }\n \n@@ -436,21 +459,21 @@ static void aux_q_release(struct rpivid_\n \t\t\t  struct rpivid_q_aux **const paq)\n {\n \tstruct rpivid_q_aux *const aq = *paq;\n-\t*paq = NULL;\n-\n-\tif (aq) {\n-\t\tunsigned long lockflags;\n+\tunsigned long lockflags;\n \n-\t\tspin_lock_irqsave(&ctx->aux_lock, lockflags);\n+\tif (!aq)\n+\t\treturn;\n \n-\t\tif (--aq->refcount == 0) {\n-\t\t\taq->next = ctx->aux_free;\n-\t\t\tctx->aux_free = aq;\n-\t\t\tctx->aux_ents[aq->q_index] = NULL;\n-\t\t}\n+\t*paq = NULL;\n \n-\t\tspin_unlock_irqrestore(&ctx->aux_lock, lockflags);\n+\tspin_lock_irqsave(&ctx->aux_lock, lockflags);\n+\tif (--aq->refcount == 0) {\n+\t\taq->next = ctx->aux_free;\n+\t\tctx->aux_free = aq;\n+\t\tctx->aux_ents[aq->q_index] = NULL;\n+\t\taq->q_index = ~0U;\n \t}\n+\tspin_unlock_irqrestore(&ctx->aux_lock, lockflags);\n }\n \n static void aux_q_init(struct rpivid_ctx *const ctx)\n@@ -1958,12 +1981,12 @@ static void rpivid_h265_setup(struct rpi\n \t\t}\n \n \t\tif (use_aux) {\n-\t\t\tdpb_q_aux[i] = aux_q_ref(ctx,\n-\t\t\t\t\t\t ctx->aux_ents[buffer_index]);\n+\t\t\tdpb_q_aux[i] = aux_q_ref_idx(ctx, buffer_index);\n \t\t\tif (!dpb_q_aux[i])\n \t\t\t\tv4l2_warn(&dev->v4l2_dev,\n-\t\t\t\t\t  \"Missing DPB AUX ent %d index=%d\\n\",\n-\t\t\t\t\t  i, buffer_index);\n+\t\t\t\t\t  \"Missing DPB AUX ent %d, timestamp=%lld, index=%d\\n\",\n+\t\t\t\t\t  i, (long long)sh->dpb[i].timestamp,\n+\t\t\t\t\t  buffer_index);\n \t\t}\n \n \t\tde->ref_addrs[i] =\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0650-Support-RPi-DPI-interface-in-mode6-for-18-bit-color.patch",
    "content": "From 16edbdfde51fc3180cecb00ad0aa311bd4567650 Mon Sep 17 00:00:00 2001\nFrom: Joerg Quinten <aBUGSworstnightmare@gmail.com>\nDate: Fri, 18 Jun 2021 13:02:29 +0200\nSubject: [PATCH] Support RPi DPI interface in mode6 for 18-bit color\n\nA matching media bus format was added and an overlay for using it,\nboth with FB and VC4 was added as well.\n\nSigned-off-by: Joerg Quinten <aBUGSworstnightmare@gmail.com>\n---\n .../bindings/display/panel/panel-simple.yaml  |  2 +\n .../media/v4l/subdev-formats.rst              | 74 +++++++++++++++++++\n drivers/gpu/drm/panel/panel-simple.c          | 35 +++++++++\n drivers/gpu/drm/vc4/vc4_dpi.c                 | 10 +++\n include/uapi/linux/media-bus-format.h         |  4 +-\n 5 files changed, 124 insertions(+), 1 deletion(-)\n\n--- a/Documentation/devicetree/bindings/display/panel/panel-simple.yaml\n+++ b/Documentation/devicetree/bindings/display/panel/panel-simple.yaml\n@@ -147,6 +147,8 @@ properties:\n       - ivo,m133nwf4-r0\n         # Innolux AT043TN24 4.3\" WQVGA TFT LCD panel\n       - innolux,at043tn24\n+        # Innolux AT056tN53V1 5.6\" VGA (640x480) TFT LCD panel\n+      - innolux,at056tn53v1\n         # Innolux AT070TN92 7.0\" WQVGA TFT LCD panel\n       - innolux,at070tn92\n         # Innolux G070Y2-L01 7\" WVGA (800x480) TFT LCD panel\n--- a/Documentation/userspace-api/media/v4l/subdev-formats.rst\n+++ b/Documentation/userspace-api/media/v4l/subdev-formats.rst\n@@ -908,6 +908,43 @@ The following tables list existing packe\n       - g\\ :sub:`5`\n       - g\\ :sub:`4`\n       - g\\ :sub:`3`\n+    * .. _MEDIA-BUS-FMT-BGR666-1X18:\n+\n+      - MEDIA_BUS_FMT_RGB666_1X18\n+      - 0x101f\n+      -\n+      -\n+      -\n+      -\n+      -\n+      -\n+      -\n+      -\n+      -\n+      -\n+      -\n+      -\n+      -\n+      -\n+      -\n+      - b\\ :sub:`5`\n+      - b\\ :sub:`4`\n+      - b\\ :sub:`3`\n+      - b\\ :sub:`2`\n+      - b\\ :sub:`1`\n+      - b\\ :sub:`0`\n+      - g\\ :sub:`5`\n+      - g\\ :sub:`4`\n+      - g\\ :sub:`3`\n+      - g\\ :sub:`2`\n+      - g\\ :sub:`1`\n+      - g\\ :sub:`0`\n+      - r\\ :sub:`5`\n+      - r\\ :sub:`4`\n+      - r\\ :sub:`3`\n+      - r\\ :sub:`2`\n+      - r\\ :sub:`1`\n+      - r\\ :sub:`0`\n     * .. _MEDIA-BUS-FMT-RGB666-1X18:\n \n       - MEDIA_BUS_FMT_RGB666_1X18\n@@ -982,6 +1019,43 @@ The following tables list existing packe\n       - g\\ :sub:`2`\n       - g\\ :sub:`1`\n       - g\\ :sub:`0`\n+    * .. _MEDIA-BUS-FMT-BGR666-1X24_CPADHI:\n+\n+      - MEDIA_BUS_FMT_BGR666_1X24_CPADHI\n+      - 0x101e\n+      -\n+      -\n+      -\n+      -\n+      -\n+      -\n+      -\n+      -\n+      -\n+      - 0\n+      - 0\n+      - b\\ :sub:`5`\n+      - b\\ :sub:`4`\n+      - b\\ :sub:`3`\n+      - b\\ :sub:`2`\n+      - b\\ :sub:`1`\n+      - b\\ :sub:`0`\n+      - 0\n+      - 0\n+      - g\\ :sub:`5`\n+      - g\\ :sub:`4`\n+      - g\\ :sub:`3`\n+      - g\\ :sub:`2`\n+      - g\\ :sub:`1`\n+      - g\\ :sub:`0`\n+      - 0\n+      - 0\n+      - r\\ :sub:`5`\n+      - r\\ :sub:`4`\n+      - r\\ :sub:`3`\n+      - r\\ :sub:`2`\n+      - r\\ :sub:`1`\n+      - r\\ :sub:`0`\n     * .. _MEDIA-BUS-FMT-RGB666-1X24_CPADHI:\n \n       - MEDIA_BUS_FMT_RGB666_1X24_CPADHI\n--- a/drivers/gpu/drm/panel/panel-simple.c\n+++ b/drivers/gpu/drm/panel/panel-simple.c\n@@ -2094,6 +2094,38 @@ static const struct panel_desc innolux_a\n \t.bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,\n };\n \n+static const struct display_timing innolux_at056tn53v1_timing = {\n+\t.pixelclock = { 39700000, 39700000, 39700000},\n+\t.hactive = { 640, 640, 640 },\n+\t.hfront_porch = { 16, 16, 16 },\n+\t.hback_porch = { 134, 134, 134 },\n+\t.hsync_len = { 10, 10, 10},\n+\t.vactive = { 480, 480, 480 },\n+\t.vfront_porch = { 32, 32, 32},\n+\t.vback_porch = { 11, 11, 11 },\n+\t.vsync_len = { 2, 2, 2 },\n+\t.flags = DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_PHSYNC,\n+};\n+\n+static const struct panel_desc innolux_at056tn53v1 = {\n+\t.timings = &innolux_at056tn53v1_timing,\n+\t.num_timings = 1,\n+\t.bpc = 6,\n+\t.size = {\n+\t\t.width = 112,\n+\t\t.height = 84,\n+\t},\n+\t.delay = {\n+\t\t.prepare = 50,\n+\t\t.enable = 200,\n+\t\t.disable = 110,\n+\t\t.unprepare = 200,\n+\t},\n+\t.bus_format = MEDIA_BUS_FMT_BGR666_1X24_CPADHI,\n+\t.bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,\n+\t.connector_type = DRM_MODE_CONNECTOR_DPI,\n+};\n+\n static const struct drm_display_mode innolux_at070tn92_mode = {\n \t.clock = 33333,\n \t.hdisplay = 800,\n@@ -4077,6 +4109,9 @@ static const struct of_device_id platfor\n \t\t.compatible = \"innolux,at043tn24\",\n \t\t.data = &innolux_at043tn24,\n \t}, {\n+\t\t.compatible = \"innolux,at056tn53v1\",\n+\t\t.data = &innolux_at056tn53v1,\n+\t}, {\n \t\t.compatible = \"innolux,at070tn92\",\n \t\t.data = &innolux_at070tn92,\n \t}, {\n--- a/drivers/gpu/drm/vc4/vc4_dpi.c\n+++ b/drivers/gpu/drm/vc4/vc4_dpi.c\n@@ -165,10 +165,20 @@ static void vc4_dpi_encoder_enable(struc\n \t\t\tdpi_c |= VC4_SET_FIELD(DPI_FORMAT_18BIT_666_RGB_2,\n \t\t\t\t\t       DPI_FORMAT);\n \t\t\tbreak;\n+\t\tcase MEDIA_BUS_FMT_BGR666_1X24_CPADHI:\n+\t\t\tdpi_c |= VC4_SET_FIELD(DPI_FORMAT_18BIT_666_RGB_2,\n+\t\t\t\t\t       DPI_FORMAT);\n+\t\t\tdpi_c |= VC4_SET_FIELD(DPI_ORDER_BGR, DPI_ORDER);\n+\t\t\tbreak;\n \t\tcase MEDIA_BUS_FMT_RGB666_1X18:\n \t\t\tdpi_c |= VC4_SET_FIELD(DPI_FORMAT_18BIT_666_RGB_1,\n \t\t\t\t\t       DPI_FORMAT);\n \t\t\tbreak;\n+\t\tcase MEDIA_BUS_FMT_BGR666_1X18:\n+\t\t\tdpi_c |= VC4_SET_FIELD(DPI_FORMAT_18BIT_666_RGB_1,\n+\t\t\t\t\t       DPI_FORMAT);\n+\t\t\tdpi_c |= VC4_SET_FIELD(DPI_ORDER_BGR, DPI_ORDER);\n+\t\t\tbreak;\n \t\tcase MEDIA_BUS_FMT_RGB565_1X16:\n \t\t\tdpi_c |= VC4_SET_FIELD(DPI_FORMAT_16BIT_565_RGB_3,\n \t\t\t\t\t       DPI_FORMAT);\n--- a/include/uapi/linux/media-bus-format.h\n+++ b/include/uapi/linux/media-bus-format.h\n@@ -34,7 +34,7 @@\n \n #define MEDIA_BUS_FMT_FIXED\t\t\t0x0001\n \n-/* RGB - next is\t0x101d */\n+/* RGB - next is\t0x1020 */\n #define MEDIA_BUS_FMT_RGB444_1X12\t\t0x1016\n #define MEDIA_BUS_FMT_RGB444_2X8_PADHI_BE\t0x1001\n #define MEDIA_BUS_FMT_RGB444_2X8_PADHI_LE\t0x1002\n@@ -45,8 +45,10 @@\n #define MEDIA_BUS_FMT_BGR565_2X8_LE\t\t0x1006\n #define MEDIA_BUS_FMT_RGB565_2X8_BE\t\t0x1007\n #define MEDIA_BUS_FMT_RGB565_2X8_LE\t\t0x1008\n+#define MEDIA_BUS_FMT_BGR666_1X18\t\t0x101f\n #define MEDIA_BUS_FMT_RGB666_1X18\t\t0x1009\n #define MEDIA_BUS_FMT_RBG888_1X24\t\t0x100e\n+#define MEDIA_BUS_FMT_BGR666_1X24_CPADHI\t0x101e\n #define MEDIA_BUS_FMT_RGB666_1X24_CPADHI\t0x1015\n #define MEDIA_BUS_FMT_RGB666_1X7X3_SPWG\t\t0x1010\n #define MEDIA_BUS_FMT_BGR888_1X24\t\t0x1013\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0651-overlays-Add-dpi18cpadhi-vc4-kms-dpi-at056tn53v1.patch",
    "content": "From 5f7c6159c8bfa019b3d8d0fd7af930187f29dbad Mon Sep 17 00:00:00 2001\nFrom: Joerg Quinten <aBUGSworstnightmare@gmail.com>\nDate: Mon, 21 Jun 2021 16:10:32 +0200\nSubject: [PATCH] overlays: Add dpi18cpadhi, vc4-kms-dpi-at056tn53v1\n\nSigned-off-by: Joerg Quinten <aBUGSworstnightmare@gmail.com>\n---\n arch/arm/boot/dts/bcm270x.dtsi                | 13 ++++++\n arch/arm/boot/dts/overlays/Makefile           |  2 +\n arch/arm/boot/dts/overlays/README             | 15 +++++++\n .../boot/dts/overlays/dpi18cpadhi-overlay.dts | 26 +++++++++++\n .../vc4-kms-dpi-at056tn53v1-overlay.dts       | 44 +++++++++++++++++++\n 5 files changed, 100 insertions(+)\n create mode 100644 arch/arm/boot/dts/overlays/dpi18cpadhi-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/vc4-kms-dpi-at056tn53v1-overlay.dts\n\n--- a/arch/arm/boot/dts/bcm270x.dtsi\n+++ b/arch/arm/boot/dts/bcm270x.dtsi\n@@ -164,6 +164,19 @@\n &gpio {\n \tinterrupts = <2 17>, <2 18>;\n \n+\tdpi_18bit_cpadhi_gpio0: dpi_18bit_cpadhi_gpio0 {\n+\t\tbrcm,pins = <0 1 2 3 4 5 6 7 8 9\n+\t\t\t     12 13 14 15 16 17\n+\t\t\t     20 21 22 23 24 25>;\n+\t\tbrcm,function = <BCM2835_FSEL_ALT2>;\n+\t\tbrcm,pull = <0>; /* no pull */\n+\t};\n+\tdpi_18bit_cpadhi_gpio2: dpi_18bit_cpadhi_gpio2 {\n+\t\tbrcm,pins = <2 3 4 5 6 7 8 9\n+\t\t\t     12 13 14 15 16 17\n+\t\t\t     20 21 22 23 24 25>;\n+\t\tbrcm,function = <BCM2835_FSEL_ALT2>;\n+\t};\n \tdpi_18bit_gpio0: dpi_18bit_gpio0 {\n \t\tbrcm,pins = <0 1 2 3 4 5 6 7 8 9 10 11\n \t\t\t     12 13 14 15 16 17 18 19\n--- a/arch/arm/boot/dts/overlays/Makefile\n+++ b/arch/arm/boot/dts/overlays/Makefile\n@@ -37,6 +37,7 @@ dtbo-$(CONFIG_ARCH_BCM2835) += \\\n \tdisable-bt.dtbo \\\n \tdisable-wifi.dtbo \\\n \tdpi18.dtbo \\\n+\tdpi18cpadhi.dtbo \\\n \tdpi24.dtbo \\\n \tdraws.dtbo \\\n \tdwc-otg.dtbo \\\n@@ -215,6 +216,7 @@ dtbo-$(CONFIG_ARCH_BCM2835) += \\\n \tupstream.dtbo \\\n \tupstream-pi4.dtbo \\\n \tvc4-fkms-v3d.dtbo \\\n+\tvc4-kms-dpi-at056tn53v1.dtbo \\\n \tvc4-kms-dsi-7inch.dtbo \\\n \tvc4-kms-dsi-lt070me05000.dtbo \\\n \tvc4-kms-dsi-lt070me05000-v2.dtbo \\\n--- a/arch/arm/boot/dts/overlays/README\n+++ b/arch/arm/boot/dts/overlays/README\n@@ -695,6 +695,14 @@ Load:   dtoverlay=dpi18\n Params: <None>\n \n \n+Name:   dpi18cpadhi\n+Info:   Overlay for a generic 18-bit DPI display (in 'mode 6' connection scheme)\n+        This uses GPIOs 0-9,12-17,20-25 (so no I2C, uart etc.), and activates\n+        the output 3-3 seconds after the kernel has started.\n+Load:   dtoverlay=dpi18cpadhi\n+Params: <None>\n+\n+\n Name:   dpi24\n Info:   Overlay for a generic 24-bit DPI display\n         This uses GPIOs 0-27 (so no I2C, uart etc.), and activates the output\n@@ -3219,6 +3227,13 @@ Params: cma-512                 CMA is 5\n         cma-default             Use upstream's default value\n \n \n+Name:   vc4-kms-dpi-at056tn53v1\n+Info:   Enable an Innolux 5.6in VGA TFT connected to DPI interface under KMS.\n+        Requires vc4-kms-v3d to be loaded.\n+Load:   dtoverlay=vc4-kms-dpi-at056tn53v1\n+Params: <None>\n+\n+\n Name:   vc4-kms-dsi-7inch\n Info:   Enable the Raspberry Pi DSI 7\" screen.\n         Use edt-ft5406 for the touchscreen element.\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/dpi18cpadhi-overlay.dts\n@@ -0,0 +1,26 @@\n+/*\n+ * dpi18cpadhi-overlay.dts\n+ */\n+\n+/dts-v1/;\n+/plugin/;\n+\n+/{\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&fb>;\n+\t\t__overlay__ {\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&dpi_18bit_cpadhi_gpio0>;\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&vc4>;\n+\t\t__overlay__ {\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&dpi_18bit_cpadhi_gpio0>;\n+\t\t};\n+\t};\n+};\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/vc4-kms-dpi-at056tn53v1-overlay.dts\n@@ -0,0 +1,44 @@\n+/*\n+ * vc4-kms-dpi-at056tn53v1-overlay.dts\n+ */\n+\n+/dts-v1/;\n+/plugin/;\n+\n+#include <dt-bindings/gpio/gpio.h>\n+#include <dt-bindings/pinctrl/bcm2835.h>\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget-path = \"/\";\n+\t\t__overlay__ {\n+\t\t\tpanel: panel {\n+\t\t\t\tcompatible = \"innolux,at056tn53v1\", \"simple-panel\";\n+\n+\t\t\t\tport {\n+\t\t\t\t\tpanel_in: endpoint {\n+\t\t\t\t\t\tremote-endpoint = <&dpi_out>;\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&dpi>;\n+\t\t__overlay__  {\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&dpi_18bit_cpadhi_gpio0>;\n+\n+\t\t\tport {\n+\t\t\t\tdpi_out: endpoint {\n+\t\t\t\t\tremote-endpoint = <&panel_in>;\n+\t\t\t\t};\n+\t\t\t};\n+\t\t};\n+\t};\n+};\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0652-drm-vc4-Fix-pixel-wrap-issue-with-DVP-teardown.patch",
    "content": "From 4ec54ed688271966193b572ba5b150c6a4d270fc Mon Sep 17 00:00:00 2001\nFrom: Tim Gover <tim.gover@raspberrypi.com>\nDate: Thu, 24 Jun 2021 17:58:05 +0100\nSubject: [PATCH] drm: vc4: Fix pixel-wrap issue with DVP teardown\n\nAdjust the DVP enable/disable sequence to avoid a pixel getting stuck\nin an internal, non resettable FIFO within PixelValve when changing\nHDMI resolution.\n\nThe blank pixels features of the DVP can prevent signals back to\npixelvalve causing it to not clear the FIFO. Adjust the ordering\nand timing of operations to ensure the clear signal makes it through to\npixelvalve.\n\nSigned-off-by: Tim Gover <tim.gover@raspberrypi.com>\n---\n drivers/gpu/drm/vc4/vc4_hdmi.c | 15 ++++++++-------\n 1 file changed, 8 insertions(+), 7 deletions(-)\n\n--- a/drivers/gpu/drm/vc4/vc4_hdmi.c\n+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c\n@@ -611,12 +611,12 @@ static void vc4_hdmi_encoder_post_crtc_d\n \n \tHDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 0);\n \n-\tHDMI_WRITE(HDMI_VID_CTL, HDMI_READ(HDMI_VID_CTL) |\n-\t\t   VC4_HD_VID_CTL_CLRRGB | VC4_HD_VID_CTL_CLRSYNC);\n+\tHDMI_WRITE(HDMI_VID_CTL, HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_CLRRGB);\n \n-\tHDMI_WRITE(HDMI_VID_CTL,\n-\t\t   HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_BLANKPIX);\n+\tmdelay(1);\n \n+\tHDMI_WRITE(HDMI_VID_CTL,\n+\t\t   HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE);\n \tvc4_hdmi_disable_scrambling(encoder);\n }\n \n@@ -626,12 +626,12 @@ static void vc4_hdmi_encoder_post_crtc_p\n \tstruct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);\n \tint ret;\n \n+\tHDMI_WRITE(HDMI_VID_CTL,\n+\t\t   HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_BLANKPIX);\n+\n \tif (vc4_hdmi->variant->phy_disable)\n \t\tvc4_hdmi->variant->phy_disable(vc4_hdmi);\n \n-\tHDMI_WRITE(HDMI_VID_CTL,\n-\t\t   HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE);\n-\n \tclk_disable_unprepare(vc4_hdmi->pixel_bvb_clock);\n \tif (vc4_hdmi->bvb_req)\n \t\tclk_request_done(vc4_hdmi->bvb_req);\n@@ -1011,6 +1011,7 @@ static void vc4_hdmi_encoder_post_crtc_e\n \n \tHDMI_WRITE(HDMI_VID_CTL,\n \t\t   VC4_HD_VID_CTL_ENABLE |\n+\t\t   VC4_HD_VID_CTL_CLRRGB |\n \t\t   VC4_HD_VID_CTL_UNDERFLOW_ENABLE |\n \t\t   VC4_HD_VID_CTL_FRAME_COUNTER_RESET |\n \t\t   (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) |\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0653-media-i2c-ov9281-Remove-override-of-subdev-name.patch",
    "content": "From c6e499074a7862e5323b324520b5aec7d89ff420 Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Mon, 28 Jun 2021 10:49:04 +0100\nSubject: [PATCH] media: i2c: ov9281: Remove override of subdev name\n\nFrom the original Rockchip driver, the subdev was renamed\nfrom the default to being \"mov9281 <dev_name>\" whereas the\ndefault would have been \"ov9281 <dev_name>\".\n\nRemove the override to drop back to the default rather than\na vendor custom string.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n drivers/media/i2c/ov9281.c | 2 --\n 1 file changed, 2 deletions(-)\n\n--- a/drivers/media/i2c/ov9281.c\n+++ b/drivers/media/i2c/ov9281.c\n@@ -1197,8 +1197,6 @@ static int ov9281_probe(struct i2c_clien\n \tif (ret < 0)\n \t\tgoto err_power_off;\n \n-\tsnprintf(sd->name, sizeof(sd->name), \"m%s %s\",\n-\t\t OV9281_NAME, dev_name(sd->dev));\n \tret = v4l2_async_register_subdev_sensor_common(sd);\n \tif (ret) {\n \t\tdev_err(dev, \"v4l2 async register subdev failed\\n\");\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0654-drm-vc4-hdmi-Use-a-fixed-rate-for-the-HSM-clock-on-B.patch",
    "content": "From 0e0118339ce920d988c550d9013333c5d948ab08 Mon Sep 17 00:00:00 2001\nFrom: Dom Cobley <popcornmix@gmail.com>\nDate: Mon, 28 Jun 2021 16:07:16 +0200\nSubject: [PATCH] drm/vc4: hdmi: Use a fixed rate for the HSM clock on\n BCM2835\n\nBefore the introduction of the BCM2711 support, the HSM clock rate was\nfixed, and was the CEC and audio clock source on the SoCs previously\nsupported.\n\nThe HSM clock is also the source of the internal state machine of the\ncontroller and needs to run faster than the pixel clock. All these\nrequirements were met by running at 101% of the maximum pixel rate,\nmeeting the fixed clock requirement for audio and CEC, while remaining\nfaster than any pixel clock we might need.\n\nHowever, the BCM2711 brought support for 4k and therefore increased\nsignificantly the rate needed for the HSM, and new, independant, clocks\nto feed the audio and CEC clocks. Since the HSM clock can also run much\nhigher, we also need to lower its rate if possible to reduce its power\nconsumption.\n\nThe CEC support code changes its clock divider when the HSM clock rate\nis changed, but the audio support never had a similar feature and will\nglitch out if audio is played back during a mode set.\n\nSince the HSM rate was meant to be fixed on the SoCs prior to the\nBCM2711 anyway, let's introduce back a fixed HSM rate and fix audio.\n\nFixes: cd4cb49dc5bb (\"drm/vc4: hdmi: Adjust HSM clock rate depending on pixel rate\")\nSigned-off-by: Dom Cobley <popcornmix@gmail.com>\nSigned-off-by: Maxime Ripard <maxime@cerno.tech>\n---\n drivers/gpu/drm/vc4/vc4_hdmi.c | 54 +++++++++++++++++++++++-----------\n drivers/gpu/drm/vc4/vc4_hdmi.h |  3 ++\n 2 files changed, 40 insertions(+), 17 deletions(-)\n\n--- a/drivers/gpu/drm/vc4/vc4_hdmi.c\n+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c\n@@ -909,23 +909,7 @@ static void vc4_hdmi_encoder_pre_crtc_co\n \t\treturn;\n \t}\n \n-\t/*\n-\t * As stated in RPi's vc4 firmware \"HDMI state machine (HSM) clock must\n-\t * be faster than pixel clock, infinitesimally faster, tested in\n-\t * simulation. Otherwise, exact value is unimportant for HDMI\n-\t * operation.\" This conflicts with bcm2835's vc4 documentation, which\n-\t * states HSM's clock has to be at least 108% of the pixel clock.\n-\t *\n-\t * Real life tests reveal that vc4's firmware statement holds up, and\n-\t * users are able to use pixel clocks closer to HSM's, namely for\n-\t * 1920x1200@60Hz. So it was decided to have leave a 1% margin between\n-\t * both clocks. Which, for RPi0-3 implies a maximum pixel clock of\n-\t * 162MHz.\n-\t *\n-\t * Additionally, the AXI clock needs to be at least 25% of\n-\t * pixel clock, but HSM ends up being the limiting factor.\n-\t */\n-\thsm_rate = max_t(unsigned long, 120000000, (pixel_rate / 100) * 101);\n+\thsm_rate = vc4_hdmi->variant->calc_hsm_clock(vc4_hdmi, pixel_rate);\n \tvc4_hdmi->hsm_req = clk_request_start(vc4_hdmi->hsm_clock, hsm_rate);\n \tif (IS_ERR(vc4_hdmi->hsm_req)) {\n \t\tDRM_ERROR(\"Failed to set HSM clock rate: %ld\\n\", PTR_ERR(vc4_hdmi->hsm_req));\n@@ -1141,6 +1125,39 @@ static const struct drm_encoder_helper_f\n \t.enable = vc4_hdmi_encoder_enable,\n };\n \n+static u32 vc4_hdmi_calc_hsm_clock(struct vc4_hdmi *vc4_hdmi, unsigned long pixel_rate)\n+{\n+\t/*\n+\t * Whilst this can vary, all the CEC timings are derived from this\n+\t * clock, so make it constant to avoid having to reconfigure CEC on\n+\t * every mode change.\n+\t */\n+\n+\treturn 163682864;\n+}\n+\n+static u32 vc5_hdmi_calc_hsm_clock(struct vc4_hdmi *vc4_hdmi, unsigned long pixel_rate)\n+{\n+\t/*\n+\t * As stated in RPi's vc4 firmware \"HDMI state machine (HSM) clock must\n+\t * be faster than pixel clock, infinitesimally faster, tested in\n+\t * simulation. Otherwise, exact value is unimportant for HDMI\n+\t * operation.\" This conflicts with bcm2835's vc4 documentation, which\n+\t * states HSM's clock has to be at least 108% of the pixel clock.\n+\t *\n+\t * Real life tests reveal that vc4's firmware statement holds up, and\n+\t * users are able to use pixel clocks closer to HSM's, namely for\n+\t * 1920x1200@60Hz. So it was decided to have leave a 1% margin between\n+\t * both clocks. Which, for RPi0-3 implies a maximum pixel clock of\n+\t * 162MHz.\n+\t *\n+\t * Additionally, the AXI clock needs to be at least 25% of\n+\t * pixel clock, but HSM ends up being the limiting factor.\n+\t */\n+\n+\treturn max_t(unsigned long, 120000000, (pixel_rate / 100) * 101);\n+}\n+\n static u32 vc4_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask)\n {\n \tint i;\n@@ -2336,6 +2353,7 @@ static const struct vc4_hdmi_variant bcm\n \t.phy_disable\t\t= vc4_hdmi_phy_disable,\n \t.phy_rng_enable\t\t= vc4_hdmi_phy_rng_enable,\n \t.phy_rng_disable\t= vc4_hdmi_phy_rng_disable,\n+\t.calc_hsm_clock\t\t= vc4_hdmi_calc_hsm_clock,\n \t.channel_map\t\t= vc4_hdmi_channel_map,\n \t.supports_hdr\t\t= false,\n };\n@@ -2364,6 +2382,7 @@ static const struct vc4_hdmi_variant bcm\n \t.phy_disable\t\t= vc5_hdmi_phy_disable,\n \t.phy_rng_enable\t\t= vc5_hdmi_phy_rng_enable,\n \t.phy_rng_disable\t= vc5_hdmi_phy_rng_disable,\n+\t.calc_hsm_clock\t\t= vc5_hdmi_calc_hsm_clock,\n \t.channel_map\t\t= vc5_hdmi_channel_map,\n \t.supports_hdr\t\t= true,\n };\n@@ -2392,6 +2411,7 @@ static const struct vc4_hdmi_variant bcm\n \t.phy_disable\t\t= vc5_hdmi_phy_disable,\n \t.phy_rng_enable\t\t= vc5_hdmi_phy_rng_enable,\n \t.phy_rng_disable\t= vc5_hdmi_phy_rng_disable,\n+\t.calc_hsm_clock\t\t= vc5_hdmi_calc_hsm_clock,\n \t.channel_map\t\t= vc5_hdmi_channel_map,\n \t.supports_hdr\t\t= true,\n };\n--- a/drivers/gpu/drm/vc4/vc4_hdmi.h\n+++ b/drivers/gpu/drm/vc4/vc4_hdmi.h\n@@ -97,6 +97,9 @@ struct vc4_hdmi_variant {\n \t/* Callback to disable the RNG in the PHY */\n \tvoid (*phy_rng_disable)(struct vc4_hdmi *vc4_hdmi);\n \n+\t/* Callback to calculate hsm clock */\n+\tu32 (*calc_hsm_clock)(struct vc4_hdmi *vc4_hdmi, unsigned long pixel_rate);\n+\n \t/* Callback to get channel map */\n \tu32 (*channel_map)(struct vc4_hdmi *vc4_hdmi, u32 channel_mask);\n \n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0655-drm-vc4-hdmi-Enable-the-scrambler-on-reconnection.patch",
    "content": "From 6dda05f181e44d54b97fff75162f63d0fb84b944 Mon Sep 17 00:00:00 2001\nFrom: Maxime Ripard <maxime@cerno.tech>\nDate: Fri, 25 Jun 2021 16:22:39 +0200\nSubject: [PATCH] drm/vc4: hdmi: Enable the scrambler on reconnection\n\nIf we have a state already and disconnect/reconnect the display, the\nSCDC messages won't be sent again since we didn't go through a disable /\nenable cycle.\n\nIn order to fix this, let's call the vc4_hdmi_enable_scrambling function\nin the detect callback if there is a mode and it needs the scrambler to\nbe enabled.\n\nFixes: 74465b84fa27 (\"drm/vc4: hdmi: Enable the scrambler\")\nSigned-off-by: Maxime Ripard <maxime@cerno.tech>\n---\n drivers/gpu/drm/vc4/vc4_hdmi.c | 10 +++++++++-\n 1 file changed, 9 insertions(+), 1 deletion(-)\n\n--- a/drivers/gpu/drm/vc4/vc4_hdmi.c\n+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c\n@@ -168,6 +168,8 @@ static void vc4_hdmi_cec_update_clk_div(\n static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi) {}\n #endif\n \n+static void vc4_hdmi_enable_scrambling(struct drm_encoder *encoder);\n+\n static enum drm_connector_status\n vc4_hdmi_connector_detect(struct drm_connector *connector, bool force)\n {\n@@ -197,6 +199,8 @@ vc4_hdmi_connector_detect(struct drm_con\n \t\t\t}\n \t\t}\n \n+\t\tvc4_hdmi_enable_scrambling(&vc4_hdmi->encoder.base.base);\n+\n \t\tpm_runtime_put(&vc4_hdmi->pdev->dev);\n \t\treturn connector_status_connected;\n \t}\n@@ -543,9 +547,13 @@ static bool vc4_hdmi_supports_scrambling\n \n static void vc4_hdmi_enable_scrambling(struct drm_encoder *encoder)\n {\n-\tstruct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;\n+\tstruct drm_display_mode *mode;\n \tstruct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);\n \n+\tif (!encoder->crtc || !encoder->crtc->state)\n+\t\treturn;\n+\n+\tmode = &encoder->crtc->state->adjusted_mode;\n \tif (!vc4_hdmi_supports_scrambling(encoder, mode))\n \t\treturn;\n \n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0656-staging-vc04_services-isp-Set-the-YUV420-YVU420-form.patch",
    "content": "From 992fc6d6d31391d2eeff80b8f7f1992fe5e40fe0 Mon Sep 17 00:00:00 2001\nFrom: Naushir Patuck <naush@raspberrypi.com>\nDate: Tue, 29 Jun 2021 12:50:58 +0100\nSubject: [PATCH] staging: vc04_services: isp: Set the YUV420/YVU420\n format stride to 64 bytes\n\nThe bcm2835 ISP requires the base address of all input/output planes to have 32\nbyte alignment. Using a Y stride of 32 bytes would not guarantee that the V\nplane would fulfil this, e.g. a height of 650 lines would mean the V plane\nbuffer is not 32 byte aligned for YUV420 formats.\n\nHaving a Y stride of 64 bytes would ensure both U and V planes have a 32 byte\nalignment, as the luma height will always be an even number of lines.\n\nSigned-off-by: Naushir Patuck <naush@raspberrypi.com>\n---\n drivers/staging/vc04_services/bcm2835-isp/bcm2835-isp-fmts.h | 4 ++--\n 1 file changed, 2 insertions(+), 2 deletions(-)\n\n--- a/drivers/staging/vc04_services/bcm2835-isp/bcm2835-isp-fmts.h\n+++ b/drivers/staging/vc04_services/bcm2835-isp/bcm2835-isp-fmts.h\n@@ -48,7 +48,7 @@ static const struct bcm2835_isp_fmt supp\n \t\t/* YUV formats */\n \t\t.fourcc\t\t    = V4L2_PIX_FMT_YUV420,\n \t\t.depth\t\t    = 8,\n-\t\t.bytesperline_align = 32,\n+\t\t.bytesperline_align = 64,\n \t\t.mmal_fmt\t    = MMAL_ENCODING_I420,\n \t\t.size_multiplier_x2 = 3,\n \t\t.colorspace_mask    = V4L2_COLORSPACE_MASK_YUV,\n@@ -57,7 +57,7 @@ static const struct bcm2835_isp_fmt supp\n \t}, {\n \t\t.fourcc\t\t    = V4L2_PIX_FMT_YVU420,\n \t\t.depth\t\t    = 8,\n-\t\t.bytesperline_align = 32,\n+\t\t.bytesperline_align = 64,\n \t\t.mmal_fmt\t    = MMAL_ENCODING_YV12,\n \t\t.size_multiplier_x2 = 3,\n \t\t.colorspace_mask    = V4L2_COLORSPACE_MASK_YUV,\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0657-Documentation-devicetree-Add-documentation-for-imx37.patch",
    "content": "From 8b4767bd7bc7e8ae5d115b3a8dabc4fd7e855f4b Mon Sep 17 00:00:00 2001\nFrom: David Plowman <david.plowman@raspberrypi.com>\nDate: Tue, 29 Jun 2021 14:38:23 +0100\nSubject: [PATCH] Documentation: devicetree: Add documentation for\n imx378 sensor\n\nThe imx378 sensor is compatible with the imx477 and shares common\ndevice tree settings.\n\nSigned-off-by: David Plowman <david.plowman@raspberrypi.com>\n---\n .../devicetree/bindings/media/i2c/imx378.yaml | 113 ++++++++++++++++++\n MAINTAINERS                                   |   1 +\n 2 files changed, 114 insertions(+)\n create mode 100644 Documentation/devicetree/bindings/media/i2c/imx378.yaml\n\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/media/i2c/imx378.yaml\n@@ -0,0 +1,113 @@\n+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)\n+%YAML 1.2\n+---\n+$id: http://devicetree.org/schemas/media/i2c/imx378.yaml#\n+$schema: http://devicetree.org/meta-schemas/core.yaml#\n+\n+title: Sony 1/2.3-Inch 12Mpixel CMOS Digital Image Sensor\n+\n+maintainers:\n+  - Naushir Patuck <naush@raspberypi.com>\n+\n+description: |-\n+  The Sony IMX378 is a 1/2.3-inch CMOS active pixel digital image sensor\n+  with an active array size of 4056H x 3040V. It is programmable through\n+  I2C interface. The I2C address is fixed to 0x1A as per sensor data sheet.\n+  Image data is sent through MIPI CSI-2, which is configured as either 2 or\n+  4 data lanes.\n+\n+properties:\n+  compatible:\n+    const: sony,imx378\n+\n+  reg:\n+    description: I2C device address\n+    maxItems: 1\n+\n+  clocks:\n+    maxItems: 1\n+\n+  VDIG-supply:\n+    description:\n+      Digital I/O voltage supply, 1.05 volts\n+\n+  VANA-supply:\n+    description:\n+      Analog voltage supply, 2.8 volts\n+\n+  VDDL-supply:\n+    description:\n+      Digital core voltage supply, 1.8 volts\n+\n+  reset-gpios:\n+    description: |-\n+      Reference to the GPIO connected to the xclr pin, if any.\n+      Must be released (set high) after all supplies and INCK are applied.\n+\n+  # See ../video-interfaces.txt for more details\n+  port:\n+    type: object\n+    properties:\n+      endpoint:\n+        type: object\n+        properties:\n+          data-lanes:\n+            description: |-\n+              The sensor supports either two-lane, or four-lane operation.\n+              For two-lane operation the property must be set to <1 2>.\n+            items:\n+              - const: 1\n+              - const: 2\n+\n+          clock-noncontinuous:\n+            type: boolean\n+            description: |-\n+              MIPI CSI-2 clock is non-continuous if this property is present,\n+              otherwise it's continuous.\n+\n+          link-frequencies:\n+            allOf:\n+              - $ref: /schemas/types.yaml#/definitions/uint64-array\n+            description:\n+              Allowed data bus frequencies.\n+\n+        required:\n+          - link-frequencies\n+\n+required:\n+  - compatible\n+  - reg\n+  - clocks\n+  - VANA-supply\n+  - VDIG-supply\n+  - VDDL-supply\n+  - port\n+\n+additionalProperties: false\n+\n+examples:\n+  - |\n+    i2c0 {\n+        #address-cells = <1>;\n+        #size-cells = <0>;\n+\n+        imx378: sensor@10 {\n+            compatible = \"sony,imx378\";\n+            reg = <0x1a>;\n+            clocks = <&imx378_clk>;\n+            VANA-supply = <&imx378_vana>;   /* 2.8v */\n+            VDIG-supply = <&imx378_vdig>;   /* 1.05v */\n+            VDDL-supply = <&imx378_vddl>;   /* 1.8v */\n+\n+            port {\n+                imx378_0: endpoint {\n+                    remote-endpoint = <&csi1_ep>;\n+                    data-lanes = <1 2>;\n+                    clock-noncontinuous;\n+                    link-frequencies = /bits/ 64 <450000000>;\n+                };\n+            };\n+        };\n+    };\n+\n+...\n--- a/MAINTAINERS\n+++ b/MAINTAINERS\n@@ -16360,6 +16360,7 @@ M:\tRaspberry Pi Kernel Maintenance <kern\n L:\tlinux-media@vger.kernel.org\n S:\tMaintained\n T:\tgit git://linuxtv.org/media_tree.git\n+F:\tDocumentation/devicetree/bindings/media/i2c/imx378.yaml\n F:\tDocumentation/devicetree/bindings/media/i2c/imx477.yaml\n F:\tdrivers/media/i2c/imx477.c\n \n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0658-overlays-Add-overlay-for-imx378-sensor.patch",
    "content": "From 07dad18a058170c0bfd38fd1f0eb21407efcbafb Mon Sep 17 00:00:00 2001\nFrom: David Plowman <david.plowman@raspberrypi.com>\nDate: Tue, 29 Jun 2021 14:41:15 +0100\nSubject: [PATCH] overlays: Add overlay for imx378 sensor\n\nThis is based off a common overlay which is now also used by the\nimx477 sensor.\n\nSigned-off-by: David Plowman <david.plowman@raspberrypi.com>\n---\n arch/arm/boot/dts/overlays/Makefile           |   1 +\n arch/arm/boot/dts/overlays/README             |   9 ++\n arch/arm/boot/dts/overlays/imx378-overlay.dts |  10 ++\n arch/arm/boot/dts/overlays/imx477-overlay.dts | 109 +-----------------\n .../boot/dts/overlays/imx477_378-overlay.dtsi | 108 +++++++++++++++++\n 5 files changed, 131 insertions(+), 106 deletions(-)\n create mode 100644 arch/arm/boot/dts/overlays/imx378-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/imx477_378-overlay.dtsi\n\n--- a/arch/arm/boot/dts/overlays/Makefile\n+++ b/arch/arm/boot/dts/overlays/Makefile\n@@ -94,6 +94,7 @@ dtbo-$(CONFIG_ARCH_BCM2835) += \\\n \tilitek251x.dtbo \\\n \timx219.dtbo \\\n \timx290.dtbo \\\n+\timx378.dtbo \\\n \timx477.dtbo \\\n \tiqaudio-codec.dtbo \\\n \tiqaudio-dac.dtbo \\\n--- a/arch/arm/boot/dts/overlays/README\n+++ b/arch/arm/boot/dts/overlays/README\n@@ -1674,6 +1674,15 @@ Params: 4lane                   Enable 4\n         mono                    Denote that the module is a mono sensor.\n \n \n+Name:   imx378\n+Info:   Sony IMX378 camera module.\n+        Uses Unicam 1, which is the standard camera connector on most Pi\n+        variants.\n+Load:   dtoverlay=imx378,<param>=<val>\n+Params: rotation                Mounting rotation of the camera sensor (0 or\n+                                180, default 180)\n+\n+\n Name:   imx477\n Info:   Sony IMX477 camera module.\n         Uses Unicam 1, which is the standard camera connector on most Pi\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/imx378-overlay.dts\n@@ -0,0 +1,10 @@\n+// SPDX-License-Identifier: GPL-2.0-only\n+// Definitions for IMX378 camera module on VC I2C bus\n+/dts-v1/;\n+/plugin/;\n+\n+#include \"imx477_378-overlay.dtsi\"\n+\n+&imx477 {\n+\tcompatible = \"sony,imx378\";\n+};\n--- a/arch/arm/boot/dts/overlays/imx477-overlay.dts\n+++ b/arch/arm/boot/dts/overlays/imx477-overlay.dts\n@@ -3,111 +3,8 @@\n /dts-v1/;\n /plugin/;\n \n-#include <dt-bindings/gpio/gpio.h>\n+#include \"imx477_378-overlay.dtsi\"\n \n-/{\n-\tcompatible = \"brcm,bcm2835\";\n-\n-\tfragment@0 {\n-\t\ttarget = <&i2c_csi_dsi>;\n-\t\t__overlay__ {\n-\t\t\t#address-cells = <1>;\n-\t\t\t#size-cells = <0>;\n-\t\t\tstatus = \"okay\";\n-\n-\t\t\timx477: imx477@1a {\n-\t\t\t\tcompatible = \"sony,imx477\";\n-\t\t\t\treg = <0x1a>;\n-\t\t\t\tstatus = \"okay\";\n-\n-\t\t\t\tclocks = <&imx477_clk>;\n-\t\t\t\tclock-names = \"xclk\";\n-\n-\t\t\t\tVANA-supply = <&cam1_reg>;\t/* 2.8v */\n-\t\t\t\tVDIG-supply = <&imx477_vdig>;\t/* 1.05v */\n-\t\t\t\tVDDL-supply = <&imx477_vddl>;\t/* 1.8v */\n-\n-\t\t\t\trotation = <180>;\n-\n-\t\t\t\tport {\n-\t\t\t\t\timx477_0: endpoint {\n-\t\t\t\t\t\tremote-endpoint = <&csi1_ep>;\n-\t\t\t\t\t\tclock-lanes = <0>;\n-\t\t\t\t\t\tdata-lanes = <1 2>;\n-\t\t\t\t\t\tclock-noncontinuous;\n-\t\t\t\t\t\tlink-frequencies =\n-\t\t\t\t\t\t\t/bits/ 64 <450000000>;\n-\t\t\t\t\t};\n-\t\t\t\t};\n-\t\t\t};\n-\t\t};\n-\t};\n-\n-\tfragment@1 {\n-\t\ttarget = <&csi1>;\n-\t\t__overlay__ {\n-\t\t\tstatus = \"okay\";\n-\n-\t\t\tport {\n-\t\t\t\tcsi1_ep: endpoint {\n-\t\t\t\t\tremote-endpoint = <&imx477_0>;\n-\t\t\t\t\tclock-lanes = <0>;\n-\t\t\t\t\tdata-lanes = <1 2>;\n-\t\t\t\t\tclock-noncontinuous;\n-\t\t\t\t};\n-\t\t\t};\n-\t\t};\n-\t};\n-\n-\tfragment@2 {\n-\t\ttarget = <&i2c0if>;\n-\t\t__overlay__ {\n-\t\t\tstatus = \"okay\";\n-\t\t};\n-\t};\n-\n-\tfragment@3 {\n-\t\ttarget-path=\"/\";\n-\t\t__overlay__ {\n-\t\t\timx477_vdig: fixedregulator@0 {\n-\t\t\t\tcompatible = \"regulator-fixed\";\n-\t\t\t\tregulator-name = \"imx477_vdig\";\n-\t\t\t\tregulator-min-microvolt = <1050000>;\n-\t\t\t\tregulator-max-microvolt = <1050000>;\n-\t\t\t};\n-\t\t\timx477_vddl: fixedregulator@1 {\n-\t\t\t\tcompatible = \"regulator-fixed\";\n-\t\t\t\tregulator-name = \"imx477_vddl\";\n-\t\t\t\tregulator-min-microvolt = <1800000>;\n-\t\t\t\tregulator-max-microvolt = <1800000>;\n-\t\t\t};\n-\t\t\timx477_clk: camera-clk {\n-\t\t\t\tcompatible = \"fixed-clock\";\n-\t\t\t\t#clock-cells = <0>;\n-\t\t\t\tclock-frequency = <24000000>;\n-\t\t\t};\n-\t\t};\n-\t};\n-\n-\tfragment@4 {\n-\t\ttarget = <&i2c0mux>;\n-\t\t__overlay__ {\n-\t\t\tstatus = \"okay\";\n-\t\t};\n-\t};\n-\n-\tfragment@5 {\n-\t\ttarget = <&cam1_reg>;\n-\t\t__overlay__ {\n-\t\t\tstatus = \"okay\";\n-\t\t\tregulator-name = \"imx477_vana\";\n-\t\t\tstartup-delay-us = <300000>;\n-\t\t\tregulator-min-microvolt = <2800000>;\n-\t\t\tregulator-max-microvolt = <2800000>;\n-\t\t};\n-\t};\n-\n-\t__overrides__ {\n-\t\trotation = <&imx477>,\"rotation:0\";\n-\t};\n+&imx477 {\n+\tcompatible = \"sony,imx477\";\n };\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/imx477_378-overlay.dtsi\n@@ -0,0 +1,108 @@\n+// SPDX-License-Identifier: GPL-2.0-only\n+// Definitions for IMX477 camera module on VC I2C bus\n+\n+/{\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&i2c_csi_dsi>;\n+\t\t__overlay__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\timx477: imx477@1a {\n+\t\t\t\treg = <0x1a>;\n+\t\t\t\tstatus = \"okay\";\n+\n+\t\t\t\tclocks = <&imx477_clk>;\n+\t\t\t\tclock-names = \"xclk\";\n+\n+\t\t\t\tVANA-supply = <&cam1_reg>;\t/* 2.8v */\n+\t\t\t\tVDIG-supply = <&imx477_vdig>;\t/* 1.05v */\n+\t\t\t\tVDDL-supply = <&imx477_vddl>;\t/* 1.8v */\n+\n+\t\t\t\trotation = <180>;\n+\n+\t\t\t\tport {\n+\t\t\t\t\timx477_0: endpoint {\n+\t\t\t\t\t\tremote-endpoint = <&csi1_ep>;\n+\t\t\t\t\t\tclock-lanes = <0>;\n+\t\t\t\t\t\tdata-lanes = <1 2>;\n+\t\t\t\t\t\tclock-noncontinuous;\n+\t\t\t\t\t\tlink-frequencies =\n+\t\t\t\t\t\t\t/bits/ 64 <450000000>;\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&csi1>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tport {\n+\t\t\t\tcsi1_ep: endpoint {\n+\t\t\t\t\tremote-endpoint = <&imx477_0>;\n+\t\t\t\t\tclock-lanes = <0>;\n+\t\t\t\t\tdata-lanes = <1 2>;\n+\t\t\t\t\tclock-noncontinuous;\n+\t\t\t\t};\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&i2c0if>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@3 {\n+\t\ttarget-path=\"/\";\n+\t\t__overlay__ {\n+\t\t\timx477_vdig: fixedregulator@0 {\n+\t\t\t\tcompatible = \"regulator-fixed\";\n+\t\t\t\tregulator-name = \"imx477_vdig\";\n+\t\t\t\tregulator-min-microvolt = <1050000>;\n+\t\t\t\tregulator-max-microvolt = <1050000>;\n+\t\t\t};\n+\t\t\timx477_vddl: fixedregulator@1 {\n+\t\t\t\tcompatible = \"regulator-fixed\";\n+\t\t\t\tregulator-name = \"imx477_vddl\";\n+\t\t\t\tregulator-min-microvolt = <1800000>;\n+\t\t\t\tregulator-max-microvolt = <1800000>;\n+\t\t\t};\n+\t\t\timx477_clk: camera-clk {\n+\t\t\t\tcompatible = \"fixed-clock\";\n+\t\t\t\t#clock-cells = <0>;\n+\t\t\t\tclock-frequency = <24000000>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@4 {\n+\t\ttarget = <&i2c0mux>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@5 {\n+\t\ttarget = <&cam1_reg>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t\tregulator-name = \"imx477_vana\";\n+\t\t\tstartup-delay-us = <300000>;\n+\t\t\tregulator-min-microvolt = <2800000>;\n+\t\t\tregulator-max-microvolt = <2800000>;\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\trotation = <&imx477>,\"rotation:0\";\n+\t};\n+};\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0659-media-i2c-imx477-Extend-driver-to-support-imx378-sen.patch",
    "content": "From c298f9514f99b9dfde64bb5f07fe09ee8dfdcd48 Mon Sep 17 00:00:00 2001\nFrom: David Plowman <david.plowman@raspberrypi.com>\nDate: Tue, 29 Jun 2021 14:43:01 +0100\nSubject: [PATCH] media: i2c: imx477: Extend driver to support imx378\n sensor\n\nThe imx378 sensor is almost identical to the imx477 and can be\nsupported as a \"compatible\" sensor with just a few extra register\nwrites.\n\nSigned-off-by: David Plowman <david.plowman@raspberrypi.com>\n---\n drivers/media/i2c/Kconfig  |  2 +-\n drivers/media/i2c/imx477.c | 68 +++++++++++++++++++++++++++++++++-----\n 2 files changed, 60 insertions(+), 10 deletions(-)\n\n--- a/drivers/media/i2c/Kconfig\n+++ b/drivers/media/i2c/Kconfig\n@@ -807,7 +807,7 @@ config VIDEO_IMX477\n \tdepends on MEDIA_CAMERA_SUPPORT\n \thelp\n \t  This is a Video4Linux2 sensor driver for the Sony\n-\t  IMX477 camera.\n+\t  IMX477 camera. Also supports the Sony IMX378.\n \n \t  To compile this driver as a module, choose M here: the\n \t  module will be called imx477.\n--- a/drivers/media/i2c/imx477.c\n+++ b/drivers/media/i2c/imx477.c\n@@ -12,6 +12,7 @@\n #include <linux/gpio/consumer.h>\n #include <linux/i2c.h>\n #include <linux/module.h>\n+#include <linux/of_device.h>\n #include <linux/pm_runtime.h>\n #include <linux/regulator/consumer.h>\n #include <media/v4l2-ctrls.h>\n@@ -26,6 +27,7 @@\n /* Chip ID */\n #define IMX477_REG_CHIP_ID\t\t0x0016\n #define IMX477_CHIP_ID\t\t\t0x0477\n+#define IMX378_CHIP_ID\t\t\t0x0378\n \n #define IMX477_REG_MODE_SELECT\t\t0x0100\n #define IMX477_MODE_STANDBY\t\t0x00\n@@ -1069,6 +1071,11 @@ static const char * const imx477_supply_\n #define IMX477_XCLR_MIN_DELAY_US\t8000\n #define IMX477_XCLR_DELAY_RANGE_US\t1000\n \n+struct imx477_compatible_data {\n+\tunsigned int chip_id;\n+\tstruct imx477_reg_list extra_regs;\n+};\n+\n struct imx477 {\n \tstruct v4l2_subdev sd;\n \tstruct media_pad pad[NUM_PADS];\n@@ -1107,6 +1114,9 @@ struct imx477 {\n \n \t/* Current long exposure factor in use. Set through V4L2_CID_VBLANK */\n \tunsigned int long_exp_shift;\n+\n+\t/* Any extra information related to different compatible sensors */\n+\tconst struct imx477_compatible_data *compatible_data;\n };\n \n static inline struct imx477 *to_imx477(struct v4l2_subdev *_sd)\n@@ -1673,11 +1683,18 @@ static int imx477_start_streaming(struct\n {\n \tstruct i2c_client *client = v4l2_get_subdevdata(&imx477->sd);\n \tconst struct imx477_reg_list *reg_list;\n+\tconst struct imx477_reg_list *extra_regs;\n \tint ret;\n \n \tif (!imx477->common_regs_written) {\n \t\tret = imx477_write_regs(imx477, mode_common_regs,\n \t\t\t\t\tARRAY_SIZE(mode_common_regs));\n+\t\tif (!ret) {\n+\t\t\textra_regs = &imx477->compatible_data->extra_regs;\n+\t\t\tret = imx477_write_regs(imx477,\textra_regs->regs,\n+\t\t\t\t\t\textra_regs->num_of_regs);\n+\t\t}\n+\n \t\tif (ret) {\n \t\t\tdev_err(&client->dev, \"%s failed to set common settings\\n\",\n \t\t\t\t__func__);\n@@ -1863,7 +1880,7 @@ static int imx477_get_regulators(struct\n }\n \n /* Verify chip ID */\n-static int imx477_identify_module(struct imx477 *imx477)\n+static int imx477_identify_module(struct imx477 *imx477, u32 expected_id)\n {\n \tstruct i2c_client *client = v4l2_get_subdevdata(&imx477->sd);\n \tint ret;\n@@ -1873,16 +1890,18 @@ static int imx477_identify_module(struct\n \t\t\t      IMX477_REG_VALUE_16BIT, &val);\n \tif (ret) {\n \t\tdev_err(&client->dev, \"failed to read chip id %x, with error %d\\n\",\n-\t\t\tIMX477_CHIP_ID, ret);\n+\t\t\texpected_id, ret);\n \t\treturn ret;\n \t}\n \n-\tif (val != IMX477_CHIP_ID) {\n+\tif (val != expected_id) {\n \t\tdev_err(&client->dev, \"chip id mismatch: %x!=%x\\n\",\n-\t\t\tIMX477_CHIP_ID, val);\n+\t\t\texpected_id, val);\n \t\treturn -EIO;\n \t}\n \n+\tdev_info(&client->dev, \"Device found is imx%x\\n\", val);\n+\n \treturn 0;\n }\n \n@@ -2078,10 +2097,39 @@ error_out:\n \treturn ret;\n }\n \n+static const struct imx477_compatible_data imx477_compatible = {\n+\t.chip_id = IMX477_CHIP_ID,\n+\t.extra_regs = {\n+\t\t.num_of_regs = 0,\n+\t\t.regs = NULL\n+\t}\n+};\n+\n+static const struct imx477_reg imx378_regs[] = {\n+\t{0x3e35, 0x01},\n+\t{0x4421, 0x08},\n+\t{0x3ff9, 0x00},\n+};\n+\n+static const struct imx477_compatible_data imx378_compatible = {\n+\t.chip_id = IMX378_CHIP_ID,\n+\t.extra_regs = {\n+\t\t.num_of_regs = ARRAY_SIZE(imx378_regs),\n+\t\t.regs = imx378_regs\n+\t}\n+};\n+\n+static const struct of_device_id imx477_dt_ids[] = {\n+\t{ .compatible = \"sony,imx477\", .data = &imx477_compatible },\n+\t{ .compatible = \"sony,imx378\", .data = &imx378_compatible },\n+\t{ /* sentinel */ }\n+};\n+\n static int imx477_probe(struct i2c_client *client)\n {\n \tstruct device *dev = &client->dev;\n \tstruct imx477 *imx477;\n+\tconst struct of_device_id *match;\n \tint ret;\n \n \timx477 = devm_kzalloc(&client->dev, sizeof(*imx477), GFP_KERNEL);\n@@ -2090,6 +2138,12 @@ static int imx477_probe(struct i2c_clien\n \n \tv4l2_i2c_subdev_init(&imx477->sd, client, &imx477_subdev_ops);\n \n+\tmatch = of_match_device(imx477_dt_ids, dev);\n+\tif (!match)\n+\t\treturn -ENODEV;\n+\timx477->compatible_data =\n+\t\t(const struct imx477_compatible_data *)match->data;\n+\n \t/* Check the hardware configuration in device tree */\n \tif (imx477_check_hwcfg(dev))\n \t\treturn -EINVAL;\n@@ -2126,7 +2180,7 @@ static int imx477_probe(struct i2c_clien\n \tif (ret)\n \t\treturn ret;\n \n-\tret = imx477_identify_module(imx477);\n+\tret = imx477_identify_module(imx477, imx477->compatible_data->chip_id);\n \tif (ret)\n \t\tgoto error_power_off;\n \n@@ -2198,10 +2252,6 @@ static int imx477_remove(struct i2c_clie\n \treturn 0;\n }\n \n-static const struct of_device_id imx477_dt_ids[] = {\n-\t{ .compatible = \"sony,imx477\" },\n-\t{ /* sentinel */ }\n-};\n MODULE_DEVICE_TABLE(of, imx477_dt_ids);\n \n static const struct dev_pm_ops imx477_pm_ops = {\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0660-overlays-Make-i2c-rtc-and-i2c-rtc-gpio-share-RTCs.patch",
    "content": "From 299e9ffda004d3f5f722ebbd04be0250a618203a Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.com>\nDate: Wed, 30 Jun 2021 17:03:00 +0100\nSubject: [PATCH] overlays: Make i2c-rtc and i2c-rtc-gpio share RTCs\n\nLift the set of RTCs out of i2c-rtc and i2c-rtc-gpio to update\ni2c-rtc-gpio and to reduce duplication.\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.com>\n---\n arch/arm/boot/dts/overlays/README             |  10 +\n .../arm/boot/dts/overlays/i2c-rtc-common.dtsi | 290 ++++++++++++++++++\n .../dts/overlays/i2c-rtc-gpio-overlay.dts     | 249 +--------------\n .../arm/boot/dts/overlays/i2c-rtc-overlay.dts | 287 +----------------\n 4 files changed, 309 insertions(+), 527 deletions(-)\n create mode 100644 arch/arm/boot/dts/overlays/i2c-rtc-common.dtsi\n\n--- a/arch/arm/boot/dts/overlays/README\n+++ b/arch/arm/boot/dts/overlays/README\n@@ -1445,6 +1445,8 @@ Params: abx80x                  Select o\n \n         ds1339                  Select the DS1339 device\n \n+        ds1340                  Select the DS1340 device\n+\n         ds3231                  Select the DS3231 device\n \n         m41t62                  Select the M41T62 device\n@@ -1457,14 +1459,22 @@ Params: abx80x                  Select o\n \n         pcf2129                 Select the PCF2129 device\n \n+        pcf85063                Select the PCF85063 device\n+\n+        pcf85063a               Select the PCF85063A device\n+\n         pcf8523                 Select the PCF8523 device\n \n+        pcf85363                Select the PCF85363 device\n+\n         pcf8563                 Select the PCF8563 device\n \n         rv1805                  Select the Micro Crystal RV1805 device\n \n         rv3028                  Select the Micro Crystal RV3028 device\n \n+        sd3078                  Select the ZXW Shenzhen whwave SD3078 device\n+\n         addr                    Sets the address for the RTC. Note that the\n                                 device must be configured to use the specified\n                                 address.\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/i2c-rtc-common.dtsi\n@@ -0,0 +1,290 @@\n+// Definitions for several I2C based Real Time Clocks\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&i2cbus>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tabx80x: abx80x@69 {\n+\t\t\t\tcompatible = \"abracon,abx80x\";\n+\t\t\t\treg = <0x69>;\n+\t\t\t\tabracon,tc-diode = \"standard\";\n+\t\t\t\tabracon,tc-resistor = <0>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&i2cbus>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tds1307: ds1307@68 {\n+\t\t\t\tcompatible = \"dallas,ds1307\";\n+\t\t\t\treg = <0x68>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&i2cbus>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tds1339: ds1339@68 {\n+\t\t\t\tcompatible = \"dallas,ds1339\";\n+\t\t\t\ttrickle-resistor-ohms = <0>;\n+\t\t\t\treg = <0x68>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@3 {\n+\t\ttarget = <&i2cbus>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tds3231: ds3231@68 {\n+\t\t\t\tcompatible = \"maxim,ds3231\";\n+\t\t\t\treg = <0x68>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@4 {\n+\t\ttarget = <&i2cbus>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tmcp7940x: mcp7940x@6f {\n+\t\t\t\tcompatible = \"microchip,mcp7940x\";\n+\t\t\t\treg = <0x6f>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@5 {\n+\t\ttarget = <&i2cbus>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tmcp7941x: mcp7941x@6f {\n+\t\t\t\tcompatible = \"microchip,mcp7941x\";\n+\t\t\t\treg = <0x6f>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@6 {\n+\t\ttarget = <&i2cbus>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tpcf2127@51 {\n+\t\t\t\tcompatible = \"nxp,pcf2127\";\n+\t\t\t\treg = <0x51>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@7 {\n+\t\ttarget = <&i2cbus>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tpcf8523: pcf8523@68 {\n+\t\t\t\tcompatible = \"nxp,pcf8523\";\n+\t\t\t\treg = <0x68>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@8 {\n+\t\ttarget = <&i2cbus>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tpcf8563: pcf8563@51 {\n+\t\t\t\tcompatible = \"nxp,pcf8563\";\n+\t\t\t\treg = <0x51>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@9 {\n+\t\ttarget = <&i2cbus>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tm41t62: m41t62@68 {\n+\t\t\t\tcompatible = \"st,m41t62\";\n+\t\t\t\treg = <0x68>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@10 {\n+\t\ttarget = <&i2cbus>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\trv3028: rv3028@52 {\n+\t\t\t\tcompatible = \"microcrystal,rv3028\";\n+\t\t\t\treg = <0x52>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@11 {\n+\t\ttarget = <&i2cbus>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tpcf2129@51 {\n+\t\t\t\tcompatible = \"nxp,pcf2129\";\n+\t\t\t\treg = <0x51>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@12 {\n+\t\ttarget = <&i2cbus>;\n+\t       __dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tpcf85363@51 {\n+\t\t\t\tcompatible = \"nxp,pcf85363\";\n+\t\t\t\treg = <0x51>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@13 {\n+\t\ttarget = <&i2cbus>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\trv1805: rv1805@69 {\n+\t\t\t\tcompatible = \"microcrystal,rv1805\";\n+\t\t\t\treg = <0x69>;\n+\t\t\t\tabracon,tc-diode = \"standard\";\n+\t\t\t\tabracon,tc-resistor = <0>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@14 {\n+\t\ttarget = <&i2cbus>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tsd3078: sd3078@32 {\n+\t\t\t\tcompatible = \"whwave,sd3078\";\n+\t\t\t\treg = <0x32>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@15 {\n+\t\ttarget = <&i2cbus>;\n+\t       __dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tpcf85063@51 {\n+\t\t\t\tcompatible = \"nxp,pcf85063\";\n+\t\t\t\treg = <0x51>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@16 {\n+\t\ttarget = <&i2cbus>;\n+\t       __dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tpcf85063a@51 {\n+\t\t\t\tcompatible = \"nxp,pcf85063a\";\n+\t\t\t\treg = <0x51>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@17 {\n+\t\ttarget = <&i2cbus>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tds1340: ds1340@68 {\n+\t\t\t\tcompatible = \"dallas,ds1340\";\n+\t\t\t\ttrickle-resistor-ohms = <0>;\n+\t\t\t\treg = <0x68>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\t__overrides__ {\n+\t\tabx80x = <0>,\"+0\";\n+\t\tds1307 = <0>,\"+1\";\n+\t\tds1339 = <0>,\"+2\";\n+\t\tds1340 = <0>,\"+17\";\n+\t\tds3231 = <0>,\"+3\";\n+\t\tmcp7940x = <0>,\"+4\";\n+\t\tmcp7941x = <0>,\"+5\";\n+\t\tpcf2127 = <0>,\"+6\";\n+\t\tpcf8523 = <0>,\"+7\";\n+\t\tpcf8563 = <0>,\"+8\";\n+\t\tm41t62 = <0>,\"+9\";\n+\t\trv3028 = <0>,\"+10\";\n+\t\tpcf2129 = <0>,\"+11\";\n+\t\tpcf85363 = <0>,\"+12\";\n+\t\trv1805 = <0>,\"+13\";\n+\t\tsd3078 = <0>,\"+14\";\n+\t\tpcf85063 = <0>,\"+15\";\n+\t\tpcf85063a = <0>,\"+16\";\n+\n+\t\taddr = <&abx80x>, \"reg:0\",\n+\t\t       <&ds1307>, \"reg:0\",\n+\t\t       <&ds1339>, \"reg:0\",\n+\t\t       <&ds3231>, \"reg:0\",\n+\t\t       <&mcp7940x>, \"reg:0\",\n+\t\t       <&mcp7941x>, \"reg:0\",\n+\t\t       <&pcf8523>, \"reg:0\",\n+\t\t       <&pcf8563>, \"reg:0\",\n+\t\t       <&m41t62>, \"reg:0\",\n+\t\t       <&rv1805>, \"reg:0\";\n+\t\ttrickle-diode-type = <&abx80x>,\"abracon,tc-diode\",\n+\t\t\t\t     <&rv1805>,\"abracon,tc-diode\";\n+\t\ttrickle-resistor-ohms = <&ds1339>,\"trickle-resistor-ohms:0\",\n+\t\t\t\t\t<&ds1340>,\"trickle-resistor-ohms:0\",\n+\t\t\t\t\t<&abx80x>,\"abracon,tc-resistor:0\",\n+\t\t\t\t\t<&rv3028>,\"trickle-resistor-ohms:0\",\n+\t\t\t\t\t<&rv1805>,\"abracon,tc-resistor:0\";\n+\t\tbackup-switchover-mode = <&rv3028>,\"backup-switchover-mode:0\";\n+\t\twakeup-source = <&ds1339>,\"wakeup-source?\",\n+\t\t\t\t<&ds3231>,\"wakeup-source?\",\n+\t\t\t\t<&mcp7940x>,\"wakeup-source?\",\n+\t\t\t\t<&mcp7941x>,\"wakeup-source?\",\n+\t\t\t\t<&m41t62>,\"wakeup-source?\";\n+\t};\n+};\n--- a/arch/arm/boot/dts/overlays/i2c-rtc-gpio-overlay.dts\n+++ b/arch/arm/boot/dts/overlays/i2c-rtc-gpio-overlay.dts\n@@ -5,13 +5,13 @@\n \n #include <dt-bindings/gpio/gpio.h>\n \n-/ {\n-\tcompatible = \"brcm,bcm2835\";\n+#include \"i2c-rtc-common.dtsi\"\n \n-\tfragment@0 {\n+/ {\n+\tfragment@100 {\n \t\ttarget-path = \"/\";\n \t\t__overlay__ {\n-\t\t\ti2c_gpio: i2c-gpio-rtc@0 {\n+\t\t\ti2cbus: i2c-gpio-rtc@0 {\n \t\t\t\tcompatible = \"i2c-gpio\";\n \t\t\t\tgpios = <&gpio 23 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN) /* sda */\n \t\t\t\t\t &gpio 24 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN) /* scl */\n@@ -23,244 +23,9 @@\n \t\t};\n \t};\n \n-\tfragment@1 {\n-\t\ttarget = <&i2c_gpio>;\n-\t\t__dormant__ {\n-\t\t\t#address-cells = <1>;\n-\t\t\t#size-cells = <0>;\n-\t\t\tstatus = \"okay\";\n-\n-\t\t\tabx80x: abx80x@69 {\n-\t\t\t\tcompatible = \"abracon,abx80x\";\n-\t\t\t\treg = <0x69>;\n-\t\t\t\tabracon,tc-diode = \"standard\";\n-\t\t\t\tabracon,tc-resistor = <0>;\n-\t\t\t\tstatus = \"okay\";\n-\t\t\t};\n-\t\t};\n-\t};\n-\n-\tfragment@2 {\n-\t\ttarget = <&i2c_gpio>;\n-\t\t__dormant__ {\n-\t\t\t#address-cells = <1>;\n-\t\t\t#size-cells = <0>;\n-\t\t\tstatus = \"okay\";\n-\n-\t\t\tds1307: ds1307@68 {\n-\t\t\t\tcompatible = \"dallas,ds1307\";\n-\t\t\t\treg = <0x68>;\n-\t\t\t\tstatus = \"okay\";\n-\t\t\t};\n-\t\t};\n-\t};\n-\n-\tfragment@3 {\n-\t\ttarget = <&i2c_gpio>;\n-\t\t__dormant__ {\n-\t\t\t#address-cells = <1>;\n-\t\t\t#size-cells = <0>;\n-\t\t\tstatus = \"okay\";\n-\n-\t\t\tds1339: ds1339@68 {\n-\t\t\t\tcompatible = \"dallas,ds1339\";\n-\t\t\t\ttrickle-resistor-ohms = <0>;\n-\t\t\t\treg = <0x68>;\n-\t\t\t\tstatus = \"okay\";\n-\t\t\t};\n-\t\t};\n-\t};\n-\n-\tfragment@4 {\n-\t\ttarget = <&i2c_gpio>;\n-\t\t__dormant__ {\n-\t\t\t#address-cells = <1>;\n-\t\t\t#size-cells = <0>;\n-\t\t\tstatus = \"okay\";\n-\n-\t\t\tds3231: ds3231@68 {\n-\t\t\t\tcompatible = \"maxim,ds3231\";\n-\t\t\t\treg = <0x68>;\n-\t\t\t\tstatus = \"okay\";\n-\t\t\t};\n-\t\t};\n-\t};\n-\n-\tfragment@5 {\n-\t\ttarget = <&i2c_gpio>;\n-\t\t__dormant__ {\n-\t\t\t#address-cells = <1>;\n-\t\t\t#size-cells = <0>;\n-\t\t\tstatus = \"okay\";\n-\n-\t\t\tmcp7940x: mcp7940x@6f {\n-\t\t\t\tcompatible = \"microchip,mcp7940x\";\n-\t\t\t\treg = <0x6f>;\n-\t\t\t\tstatus = \"okay\";\n-\t\t\t};\n-\t\t};\n-\t};\n-\n-\tfragment@6 {\n-\t\ttarget = <&i2c_gpio>;\n-\t\t__dormant__ {\n-\t\t\t#address-cells = <1>;\n-\t\t\t#size-cells = <0>;\n-\t\t\tstatus = \"okay\";\n-\n-\t\t\tmcp7941x: mcp7941x@6f {\n-\t\t\t\tcompatible = \"microchip,mcp7941x\";\n-\t\t\t\treg = <0x6f>;\n-\t\t\t\tstatus = \"okay\";\n-\t\t\t};\n-\t\t};\n-\t};\n-\n-\tfragment@7 {\n-\t\ttarget = <&i2c_gpio>;\n-\t\t__dormant__ {\n-\t\t\t#address-cells = <1>;\n-\t\t\t#size-cells = <0>;\n-\t\t\tstatus = \"okay\";\n-\n-\t\t\tpcf2127@51 {\n-\t\t\t\tcompatible = \"nxp,pcf2127\";\n-\t\t\t\treg = <0x51>;\n-\t\t\t\tstatus = \"okay\";\n-\t\t\t};\n-\t\t};\n-\t};\n-\n-\tfragment@8 {\n-\t\ttarget = <&i2c_gpio>;\n-\t\t__dormant__ {\n-\t\t\t#address-cells = <1>;\n-\t\t\t#size-cells = <0>;\n-\t\t\tstatus = \"okay\";\n-\n-\t\t\tpcf8523: pcf8523@68 {\n-\t\t\t\tcompatible = \"nxp,pcf8523\";\n-\t\t\t\treg = <0x68>;\n-\t\t\t\tstatus = \"okay\";\n-\t\t\t};\n-\t\t};\n-\t};\n-\n-\tfragment@9 {\n-\t\ttarget = <&i2c_gpio>;\n-\t\t__dormant__ {\n-\t\t\t#address-cells = <1>;\n-\t\t\t#size-cells = <0>;\n-\t\t\tstatus = \"okay\";\n-\n-\t\t\tpcf8563: pcf8563@51 {\n-\t\t\t\tcompatible = \"nxp,pcf8563\";\n-\t\t\t\treg = <0x51>;\n-\t\t\t\tstatus = \"okay\";\n-\t\t\t};\n-\t\t};\n-\t};\n-\n-\tfragment@10 {\n-\t\ttarget = <&i2c_arm>;\n-\t\t__dormant__ {\n-\t\t\t#address-cells = <1>;\n-\t\t\t#size-cells = <0>;\n-\t\t\tstatus = \"okay\";\n-\n-\t\t\tm41t62: m41t62@68 {\n-\t\t\t\tcompatible = \"st,m41t62\";\n-\t\t\t\treg = <0x68>;\n-\t\t\t\tstatus = \"okay\";\n-\t\t\t};\n-\t\t};\n-\t};\n-\n-\tfragment@11 {\n-\t\ttarget = <&i2c_gpio>;\n-\t\t__dormant__ {\n-\t\t\t#address-cells = <1>;\n-\t\t\t#size-cells = <0>;\n-\t\t\tstatus = \"okay\";\n-\n-\t\t\trv3028: rv3028@52 {\n-\t\t\t\tcompatible = \"microcrystal,rv3028\";\n-\t\t\t\treg = <0x52>;\n-\t\t\t\tstatus = \"okay\";\n-\t\t\t};\n-\t\t};\n-\t};\n-\n-\tfragment@12 {\n-\t\ttarget = <&i2c_gpio>;\n-\t\t__dormant__ {\n-\t\t\t#address-cells = <1>;\n-\t\t\t#size-cells = <0>;\n-\t\t\tstatus = \"okay\";\n-\n-\t\t\tpcf2129@51 {\n-\t\t\t\tcompatible = \"nxp,pcf2129\";\n-\t\t\t\treg = <0x51>;\n-\t\t\t\tstatus = \"okay\";\n-\t\t\t};\n-\t\t};\n-\t};\n-\n-\tfragment@13 {\n-\t\ttarget = <&i2c_gpio>;\n-\t\t__dormant__ {\n-\t\t\t#address-cells = <1>;\n-\t\t\t#size-cells = <0>;\n-\t\t\tstatus = \"okay\";\n-\n-\t\t\trv1805: rv1805@69 {\n-\t\t\t\tcompatible = \"microcrystal,rv1805\";\n-\t\t\t\treg = <0x69>;\n-\t\t\t\tabracon,tc-diode = \"standard\";\n-\t\t\t\tabracon,tc-resistor = <0>;\n-\t\t\t\tstatus = \"okay\";\n-\t\t\t};\n-\t\t};\n-\t};\n-\n \t__overrides__ {\n-\t\tabx80x = <0>,\"+1\";\n-\t\tds1307 = <0>,\"+2\";\n-\t\tds1339 = <0>,\"+3\";\n-\t\tds3231 = <0>,\"+4\";\n-\t\tmcp7940x = <0>,\"+5\";\n-\t\tmcp7941x = <0>,\"+6\";\n-\t\tpcf2127 = <0>,\"+7\";\n-\t\tpcf8523 = <0>,\"+8\";\n-\t\tpcf8563 = <0>,\"+9\";\n-\t\tm41t62 = <0>,\"+10\";\n-\t\trv3028 = <0>,\"+11\";\n-\t\tpcf2129 = <0>,\"+12\";\n-\t\trv1805 = <0>,\"+13\";\n-\n-\t\taddr = <&abx80x>, \"reg:0\",\n-\t\t       <&ds1307>, \"reg:0\",\n-\t\t       <&ds1339>, \"reg:0\",\n-\t\t       <&ds3231>, \"reg:0\",\n-\t\t       <&mcp7940x>, \"reg:0\",\n-\t\t       <&mcp7941x>, \"reg:0\",\n-\t\t       <&pcf8523>, \"reg:0\",\n-\t\t       <&pcf8563>, \"reg:0\",\n-\t\t       <&m41t62>, \"reg:0\",\n-\t\t       <&rv1805>, \"reg:0\";\n-\t\ttrickle-diode-type = <&abx80x>,\"abracon,tc-diode\",\n-\t\t\t\t     <&rv1805>,\"abracon,tc-diode\";\n-\t\ttrickle-resistor-ohms = <&ds1339>,\"trickle-resistor-ohms:0\",\n-\t\t\t\t\t<&abx80x>,\"abracon,tc-resistor:0\",\n-\t\t\t\t\t<&rv3028>,\"trickle-resistor-ohms:0\",\n-\t\t\t\t\t<&rv1805>,\"abracon,tc-resistor:0\";\n-\t\tbackup-switchover-mode = <&rv3028>,\"backup-switchover-mode:0\";\n-\t\twakeup-source = <&ds1339>,\"wakeup-source?\",\n-\t\t\t\t<&ds3231>,\"wakeup-source?\",\n-\t\t\t\t<&mcp7940x>,\"wakeup-source?\",\n-\t\t\t\t<&mcp7941x>,\"wakeup-source?\";\n-\t\ti2c_gpio_sda = <&i2c_gpio>,\"gpios:4\";\n-\t\ti2c_gpio_scl = <&i2c_gpio>,\"gpios:16\";\n-\t\ti2c_gpio_delay_us = <&i2c_gpio>,\"i2c-gpio,delay-us:0\";\n+\t\ti2c_gpio_sda = <&i2cbus>,\"gpios:4\";\n+\t\ti2c_gpio_scl = <&i2cbus>,\"gpios:16\";\n+\t\ti2c_gpio_delay_us = <&i2cbus>,\"i2c-gpio,delay-us:0\";\n \t};\n };\n--- a/arch/arm/boot/dts/overlays/i2c-rtc-overlay.dts\n+++ b/arch/arm/boot/dts/overlays/i2c-rtc-overlay.dts\n@@ -2,249 +2,9 @@\n /dts-v1/;\n /plugin/;\n \n-/ {\n-\tcompatible = \"brcm,bcm2835\";\n-\n-\tfragment@0 {\n-\t\ttarget = <&i2cbus>;\n-\t\t__dormant__ {\n-\t\t\t#address-cells = <1>;\n-\t\t\t#size-cells = <0>;\n-\n-\t\t\tabx80x: abx80x@69 {\n-\t\t\t\tcompatible = \"abracon,abx80x\";\n-\t\t\t\treg = <0x69>;\n-\t\t\t\tabracon,tc-diode = \"standard\";\n-\t\t\t\tabracon,tc-resistor = <0>;\n-\t\t\t};\n-\t\t};\n-\t};\n-\n-\tfragment@1 {\n-\t\ttarget = <&i2cbus>;\n-\t\t__dormant__ {\n-\t\t\t#address-cells = <1>;\n-\t\t\t#size-cells = <0>;\n-\n-\t\t\tds1307: ds1307@68 {\n-\t\t\t\tcompatible = \"dallas,ds1307\";\n-\t\t\t\treg = <0x68>;\n-\t\t\t};\n-\t\t};\n-\t};\n-\n-\tfragment@2 {\n-\t\ttarget = <&i2cbus>;\n-\t\t__dormant__ {\n-\t\t\t#address-cells = <1>;\n-\t\t\t#size-cells = <0>;\n-\n-\t\t\tds1339: ds1339@68 {\n-\t\t\t\tcompatible = \"dallas,ds1339\";\n-\t\t\t\ttrickle-resistor-ohms = <0>;\n-\t\t\t\treg = <0x68>;\n-\t\t\t};\n-\t\t};\n-\t};\n-\n-\tfragment@3 {\n-\t\ttarget = <&i2cbus>;\n-\t\t__dormant__ {\n-\t\t\t#address-cells = <1>;\n-\t\t\t#size-cells = <0>;\n-\n-\t\t\tds3231: ds3231@68 {\n-\t\t\t\tcompatible = \"maxim,ds3231\";\n-\t\t\t\treg = <0x68>;\n-\t\t\t};\n-\t\t};\n-\t};\n-\n-\tfragment@4 {\n-\t\ttarget = <&i2cbus>;\n-\t\t__dormant__ {\n-\t\t\t#address-cells = <1>;\n-\t\t\t#size-cells = <0>;\n-\n-\t\t\tmcp7940x: mcp7940x@6f {\n-\t\t\t\tcompatible = \"microchip,mcp7940x\";\n-\t\t\t\treg = <0x6f>;\n-\t\t\t};\n-\t\t};\n-\t};\n-\n-\tfragment@5 {\n-\t\ttarget = <&i2cbus>;\n-\t\t__dormant__ {\n-\t\t\t#address-cells = <1>;\n-\t\t\t#size-cells = <0>;\n-\n-\t\t\tmcp7941x: mcp7941x@6f {\n-\t\t\t\tcompatible = \"microchip,mcp7941x\";\n-\t\t\t\treg = <0x6f>;\n-\t\t\t};\n-\t\t};\n-\t};\n-\n-\tfragment@6 {\n-\t\ttarget = <&i2cbus>;\n-\t\t__dormant__ {\n-\t\t\t#address-cells = <1>;\n-\t\t\t#size-cells = <0>;\n-\n-\t\t\tpcf2127@51 {\n-\t\t\t\tcompatible = \"nxp,pcf2127\";\n-\t\t\t\treg = <0x51>;\n-\t\t\t};\n-\t\t};\n-\t};\n-\n-\tfragment@7 {\n-\t\ttarget = <&i2cbus>;\n-\t\t__dormant__ {\n-\t\t\t#address-cells = <1>;\n-\t\t\t#size-cells = <0>;\n-\n-\t\t\tpcf8523: pcf8523@68 {\n-\t\t\t\tcompatible = \"nxp,pcf8523\";\n-\t\t\t\treg = <0x68>;\n-\t\t\t};\n-\t\t};\n-\t};\n-\n-\tfragment@8 {\n-\t\ttarget = <&i2cbus>;\n-\t\t__dormant__ {\n-\t\t\t#address-cells = <1>;\n-\t\t\t#size-cells = <0>;\n-\n-\t\t\tpcf8563: pcf8563@51 {\n-\t\t\t\tcompatible = \"nxp,pcf8563\";\n-\t\t\t\treg = <0x51>;\n-\t\t\t};\n-\t\t};\n-\t};\n-\n-\tfragment@9 {\n-\t\ttarget = <&i2cbus>;\n-\t\t__dormant__ {\n-\t\t\t#address-cells = <1>;\n-\t\t\t#size-cells = <0>;\n-\n-\t\t\tm41t62: m41t62@68 {\n-\t\t\t\tcompatible = \"st,m41t62\";\n-\t\t\t\treg = <0x68>;\n-\t\t\t};\n-\t\t};\n-\t};\n-\n-\tfragment@10 {\n-\t\ttarget = <&i2cbus>;\n-\t\t__dormant__ {\n-\t\t\t#address-cells = <1>;\n-\t\t\t#size-cells = <0>;\n-\n-\t\t\trv3028: rv3028@52 {\n-\t\t\t\tcompatible = \"microcrystal,rv3028\";\n-\t\t\t\treg = <0x52>;\n-\t\t\t};\n-\t\t};\n-\t};\n-\n-\tfragment@11 {\n-\t\ttarget = <&i2cbus>;\n-\t\t__dormant__ {\n-\t\t\t#address-cells = <1>;\n-\t\t\t#size-cells = <0>;\n-\n-\t\t\tpcf2129@51 {\n-\t\t\t\tcompatible = \"nxp,pcf2129\";\n-\t\t\t\treg = <0x51>;\n-\t\t\t};\n-\t\t};\n-\t};\n-\n-\tfragment@12 {\n-\t\ttarget = <&i2cbus>;\n-\t       __dormant__ {\n-\t\t\t#address-cells = <1>;\n-\t\t\t#size-cells = <0>;\n-\n-\t\t\tpcf85363@51 {\n-\t\t\t\tcompatible = \"nxp,pcf85363\";\n-\t\t\t\treg = <0x51>;\n-\t\t\t};\n-\t\t};\n-\t};\n-\n-\tfragment@13 {\n-\t\ttarget = <&i2cbus>;\n-\t\t__dormant__ {\n-\t\t\t#address-cells = <1>;\n-\t\t\t#size-cells = <0>;\n-\n-\t\t\trv1805: rv1805@69 {\n-\t\t\t\tcompatible = \"microcrystal,rv1805\";\n-\t\t\t\treg = <0x69>;\n-\t\t\t\tabracon,tc-diode = \"standard\";\n-\t\t\t\tabracon,tc-resistor = <0>;\n-\t\t\t};\n-\t\t};\n-\t};\n-\n-\tfragment@14 {\n-\t\ttarget = <&i2cbus>;\n-\t\t__dormant__ {\n-\t\t\t#address-cells = <1>;\n-\t\t\t#size-cells = <0>;\n-\n-\t\t\tsd3078: sd3078@32 {\n-\t\t\t\tcompatible = \"whwave,sd3078\";\n-\t\t\t\treg = <0x32>;\n-\t\t\t};\n-\t\t};\n-\t};\n-\n-\tfragment@15 {\n-\t\ttarget = <&i2cbus>;\n-\t       __dormant__ {\n-\t\t\t#address-cells = <1>;\n-\t\t\t#size-cells = <0>;\n-\n-\t\t\tpcf85063@51 {\n-\t\t\t\tcompatible = \"nxp,pcf85063\";\n-\t\t\t\treg = <0x51>;\n-\t\t\t};\n-\t\t};\n-\t};\n-\n-\tfragment@16 {\n-\t\ttarget = <&i2cbus>;\n-\t       __dormant__ {\n-\t\t\t#address-cells = <1>;\n-\t\t\t#size-cells = <0>;\n-\n-\t\t\tpcf85063a@51 {\n-\t\t\t\tcompatible = \"nxp,pcf85063a\";\n-\t\t\t\treg = <0x51>;\n-\t\t\t};\n-\t\t};\n-\t};\n-\n-\tfragment@17 {\n-\t\ttarget = <&i2cbus>;\n-\t\t__dormant__ {\n-\t\t\t#address-cells = <1>;\n-\t\t\t#size-cells = <0>;\n-\n-\t\t\tds1340: ds1340@68 {\n-\t\t\t\tcompatible = \"dallas,ds1340\";\n-\t\t\t\ttrickle-resistor-ohms = <0>;\n-\t\t\t\treg = <0x68>;\n-\t\t\t};\n-\t\t};\n-\t};\n+#include \"i2c-rtc-common.dtsi\"\n \n+/ {\n \tfrag100: fragment@100 {\n \t\ttarget = <&i2c_arm>;\n \t\ti2cbus: __overlay__ {\n@@ -267,51 +27,8 @@\n \t};\n \n \t__overrides__ {\n-\t\tabx80x = <0>,\"+0\";\n-\t\tds1307 = <0>,\"+1\";\n-\t\tds1339 = <0>,\"+2\";\n-\t\tds1340 = <0>,\"+17\";\n-\t\tds3231 = <0>,\"+3\";\n-\t\tmcp7940x = <0>,\"+4\";\n-\t\tmcp7941x = <0>,\"+5\";\n-\t\tpcf2127 = <0>,\"+6\";\n-\t\tpcf8523 = <0>,\"+7\";\n-\t\tpcf8563 = <0>,\"+8\";\n-\t\tm41t62 = <0>,\"+9\";\n-\t\trv3028 = <0>,\"+10\";\n-\t\tpcf2129 = <0>,\"+11\";\n-\t\tpcf85363 = <0>,\"+12\";\n-\t\trv1805 = <0>,\"+13\";\n-\t\tsd3078 = <0>,\"+14\";\n-\t\tpcf85063 = <0>,\"+15\";\n-\t\tpcf85063a = <0>,\"+16\";\n-\n \t\ti2c0 = <&frag100>, \"target:0=\",<&i2c0>;\n \t\ti2c_csi_dsi = <&frag100>, \"target:0=\",<&i2c_csi_dsi>,\n \t\t\t      <0>,\"+101+102\";\n-\n-\t\taddr = <&abx80x>, \"reg:0\",\n-\t\t       <&ds1307>, \"reg:0\",\n-\t\t       <&ds1339>, \"reg:0\",\n-\t\t       <&ds3231>, \"reg:0\",\n-\t\t       <&mcp7940x>, \"reg:0\",\n-\t\t       <&mcp7941x>, \"reg:0\",\n-\t\t       <&pcf8523>, \"reg:0\",\n-\t\t       <&pcf8563>, \"reg:0\",\n-\t\t       <&m41t62>, \"reg:0\",\n-\t\t       <&rv1805>, \"reg:0\";\n-\t\ttrickle-diode-type = <&abx80x>,\"abracon,tc-diode\",\n-\t\t\t\t     <&rv1805>,\"abracon,tc-diode\";\n-\t\ttrickle-resistor-ohms = <&ds1339>,\"trickle-resistor-ohms:0\",\n-\t\t\t\t\t<&ds1340>,\"trickle-resistor-ohms:0\",\n-\t\t\t\t\t<&abx80x>,\"abracon,tc-resistor:0\",\n-\t\t\t\t\t<&rv3028>,\"trickle-resistor-ohms:0\",\n-\t\t\t\t\t<&rv1805>,\"abracon,tc-resistor:0\";\n-\t\tbackup-switchover-mode = <&rv3028>,\"backup-switchover-mode:0\";\n-\t\twakeup-source = <&ds1339>,\"wakeup-source?\",\n-\t\t\t\t<&ds3231>,\"wakeup-source?\",\n-\t\t\t\t<&mcp7940x>,\"wakeup-source?\",\n-\t\t\t\t<&mcp7941x>,\"wakeup-source?\",\n-\t\t\t\t<&m41t62>,\"wakeup-source?\";\n \t};\n };\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0661-dt-bindings-clk-raspberrypi-Remove-unused-property.patch",
    "content": "From 821ca0c791f1e7dbee2b6121acb04f71e6d81168 Mon Sep 17 00:00:00 2001\nFrom: Maxime Ripard <maxime@cerno.tech>\nDate: Wed, 23 Jun 2021 11:47:38 +0200\nSubject: [PATCH] dt-bindings: clk: raspberrypi: Remove unused property\n\nThe raspberrypi,firmware property has been documented as required in the\nbinding but was never actually used in the final version of the binding.\nRemove it.\n\nSigned-off-by: Maxime Ripard <maxime@cerno.tech>\n---\n .../bindings/clock/raspberrypi,firmware-clocks.yaml        | 7 -------\n 1 file changed, 7 deletions(-)\n\n--- a/Documentation/devicetree/bindings/clock/raspberrypi,firmware-clocks.yaml\n+++ b/Documentation/devicetree/bindings/clock/raspberrypi,firmware-clocks.yaml\n@@ -16,15 +16,9 @@ properties:\n   compatible:\n     const: raspberrypi,firmware-clocks\n \n-  raspberrypi,firmware:\n-    $ref: /schemas/types.yaml#/definitions/phandle\n-    description: >\n-      Phandle to the mailbox node to communicate with the firmware.\n-\n required:\n   - \"#clock-cells\"\n   - compatible\n-  - raspberrypi,firmware\n \n additionalProperties: false\n \n@@ -32,7 +26,6 @@ examples:\n   - |\n     firmware_clocks: firmware-clocks {\n         compatible = \"raspberrypi,firmware-clocks\";\n-        raspberrypi,firmware = <&firmware>;\n         #clock-cells = <1>;\n     };\n \n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0662-dt-bindings-display-vc4-Add-phandle-to-the-firmware.patch",
    "content": "From 23db49ffa4fb3e0205433f22f56ce73cebe2cb03 Mon Sep 17 00:00:00 2001\nFrom: Maxime Ripard <maxime@cerno.tech>\nDate: Wed, 23 Jun 2021 11:48:35 +0200\nSubject: [PATCH] dt-bindings: display: vc4: Add phandle to the\n firmware\n\nThe vc4 driver will need to tell the firmware that it takes over the\ndisplay for the firmware to free its resources (lower the clock, free\nsome memory, etc.)\n\nLet's add an optional phandle to our firmware node.\n\nSigned-off-by: Maxime Ripard <maxime@cerno.tech>\n---\n .../devicetree/bindings/display/brcm,bcm2835-vc4.yaml        | 5 +++++\n 1 file changed, 5 insertions(+)\n\n--- a/Documentation/devicetree/bindings/display/brcm,bcm2835-vc4.yaml\n+++ b/Documentation/devicetree/bindings/display/brcm,bcm2835-vc4.yaml\n@@ -21,6 +21,11 @@ properties:\n       - brcm,bcm2835-vc4\n       - brcm,cygnus-vc4\n \n+  raspberrypi,firmware:\n+    $ref: /schemas/types.yaml#/definitions/phandle\n+    description: >\n+      Phandle to the mailbox node to communicate with the firmware.\n+\n required:\n   - compatible\n \n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0663-firmware-raspberrypi-Add-RPI_FIRMWARE_NOTIFY_DISPLAY.patch",
    "content": "From 63c7602ca03b9e10dbeb202ebc1f6aa702c1d17c Mon Sep 17 00:00:00 2001\nFrom: Maxime Ripard <maxime@cerno.tech>\nDate: Wed, 23 Jun 2021 11:53:46 +0200\nSubject: [PATCH] firmware: raspberrypi: Add\n RPI_FIRMWARE_NOTIFY_DISPLAY_DONE\n\nThe RPI_FIRMWARE_NOTIFY_DISPLAY_DONE firmware call allows to tell the\nfirmware the kernel is in charge of the display now and the firmware can\nfree whatever resources it was using.\n\nSigned-off-by: Maxime Ripard <maxime@cerno.tech>\n---\n include/soc/bcm2835/raspberrypi-firmware.h | 1 +\n 1 file changed, 1 insertion(+)\n\n--- a/include/soc/bcm2835/raspberrypi-firmware.h\n+++ b/include/soc/bcm2835/raspberrypi-firmware.h\n@@ -99,6 +99,7 @@ enum rpi_firmware_property_tag {\n \tRPI_FIRMWARE_NOTIFY_XHCI_RESET =                      0x00030058,\n \tRPI_FIRMWARE_GET_REBOOT_FLAGS =                       0x00030064,\n \tRPI_FIRMWARE_SET_REBOOT_FLAGS =                       0x00038064,\n+\tRPI_FIRMWARE_NOTIFY_DISPLAY_DONE =                    0x00030066,\n \n \t/* Dispmanx TAGS */\n \tRPI_FIRMWARE_FRAMEBUFFER_ALLOCATE =                   0x00040001,\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0664-drm-vc4-Remove-conflicting-framebuffers-before-calli.patch",
    "content": "From 89c8ca8b57abe798418bd6544b0fac9aa87cb691 Mon Sep 17 00:00:00 2001\nFrom: Maxime Ripard <maxime@cerno.tech>\nDate: Fri, 25 Jun 2021 17:01:33 +0200\nSubject: [PATCH] drm/vc4: Remove conflicting framebuffers before\n callind bind_all\n\nThe bind hooks will modify their controller registers, so simplefb is\ngoing to be unusable anyway. Let's avoid any transient state where it\ncould still be in the system but no longer functionnal.\n\nSigned-off-by: Maxime Ripard <maxime@cerno.tech>\n---\n drivers/gpu/drm/vc4/vc4_drv.c | 4 ++--\n 1 file changed, 2 insertions(+), 2 deletions(-)\n\n--- a/drivers/gpu/drm/vc4/vc4_drv.c\n+++ b/drivers/gpu/drm/vc4/vc4_drv.c\n@@ -305,6 +305,8 @@ static int vc4_drm_bind(struct device *d\n \tif (ret)\n \t\treturn ret;\n \n+\tdrm_fb_helper_remove_conflicting_framebuffers(NULL, \"vc4drmfb\", false);\n+\n \tret = component_bind_all(dev, drm);\n \tif (ret)\n \t\treturn ret;\n@@ -315,8 +317,6 @@ static int vc4_drm_bind(struct device *d\n \t\t\tgoto unbind_all;\n \t}\n \n-\tdrm_fb_helper_remove_conflicting_framebuffers(NULL, \"vc4drmfb\", false);\n-\n \tret = vc4_kms_load(drm);\n \tif (ret < 0)\n \t\tgoto unbind_all;\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0665-drm-vc4-Notify-the-firmware-when-DRM-is-in-charge.patch",
    "content": "From 154a12e5c0d417cae205b8e16431f29c627311e6 Mon Sep 17 00:00:00 2001\nFrom: Maxime Ripard <maxime@cerno.tech>\nDate: Wed, 23 Jun 2021 11:54:58 +0200\nSubject: [PATCH] drm/vc4: Notify the firmware when DRM is in charge\n\nOnce the call to drm_fb_helper_remove_conflicting_framebuffers() has\nbeen made, simplefb has been unregistered and the KMS driver is entirely\nin charge of the display.\n\nThus, we can notify the firmware it can free whatever resource it was\nusing to maintain simplefb functional.\n\nSigned-off-by: Maxime Ripard <maxime@cerno.tech>\n---\n drivers/gpu/drm/vc4/vc4_drv.c | 19 +++++++++++++++++++\n 1 file changed, 19 insertions(+)\n\n--- a/drivers/gpu/drm/vc4/vc4_drv.c\n+++ b/drivers/gpu/drm/vc4/vc4_drv.c\n@@ -36,6 +36,8 @@\n #include <drm/drm_fb_helper.h>\n #include <drm/drm_vblank.h>\n \n+#include <soc/bcm2835/raspberrypi-firmware.h>\n+\n #include \"uapi/drm/vc4_drm.h\"\n \n #include \"vc4_drv.h\"\n@@ -305,8 +307,25 @@ static int vc4_drm_bind(struct device *d\n \tif (ret)\n \t\treturn ret;\n \n+\tnode = of_parse_phandle(dev->of_node, \"raspberrypi,firmware\", 0);\n+\tif (node) {\n+\t\tvc4->firmware = rpi_firmware_get(dev->of_node);\n+\t\tof_node_put(node);\n+\n+\t\tif (!vc4->firmware)\n+\t\t\treturn -EPROBE_DEFER;\n+\t}\n+\n \tdrm_fb_helper_remove_conflicting_framebuffers(NULL, \"vc4drmfb\", false);\n \n+\tif (vc4->firmware) {\n+\t\tret = rpi_firmware_property(vc4->firmware,\n+\t\t\t\t\t    RPI_FIRMWARE_NOTIFY_DISPLAY_DONE,\n+\t\t\t\t\t    NULL, 0);\n+\t\tif (ret)\n+\t\t\tdrm_warn(drm, \"Couldn't stop firmware display driver: %d\\n\", ret);\n+\t}\n+\n \tret = component_bind_all(dev, drm);\n \tif (ret)\n \t\treturn ret;\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0666-ARM-dts-rpi-Add-the-firmware-node-to-vc4.patch",
    "content": "From e7a09a6262abe6181514a0b64f79acec8bc3c405 Mon Sep 17 00:00:00 2001\nFrom: Maxime Ripard <maxime@cerno.tech>\nDate: Wed, 23 Jun 2021 11:56:56 +0200\nSubject: [PATCH] ARM: dts: rpi: Add the firmware node to vc4\n\nAdd the firmware phandle to the vc4 node so that we can send it the\nmessage that we're done with the firmware display.\n\nSigned-off-by: Maxime Ripard <maxime@cerno.tech>\n---\n arch/arm/boot/dts/bcm2711-rpi.dtsi | 4 ++++\n arch/arm/boot/dts/bcm2835-rpi.dtsi | 4 ++++\n 2 files changed, 8 insertions(+)\n\n--- a/arch/arm/boot/dts/bcm2711-rpi.dtsi\n+++ b/arch/arm/boot/dts/bcm2711-rpi.dtsi\n@@ -35,6 +35,10 @@\n \t};\n };\n \n+&vc4 {\n+\traspberrypi,firmware = <&firmware>;\n+};\n+\n &cma {\n \t/* Limit cma to the lower 768MB to allow room for HIGHMEM on 32-bit */\n \talloc-ranges = <0x0 0x00000000 0x30000000>;\n--- a/arch/arm/boot/dts/bcm2835-rpi.dtsi\n+++ b/arch/arm/boot/dts/bcm2835-rpi.dtsi\n@@ -76,6 +76,10 @@\n \tpower-domains = <&power RPI_POWER_DOMAIN_USB>;\n };\n \n+&vc4 {\n+\traspberrypi,firmware = <&firmware>;\n+};\n+\n &vec {\n \tpower-domains = <&power RPI_POWER_DOMAIN_VEC>;\n \tstatus = \"okay\";\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0667-drm-vc4-hdmi-Put-the-device-on-error-in-pre_crtc_con.patch",
    "content": "From 60ed238e2225599540e47a95ecf50313cca9459e Mon Sep 17 00:00:00 2001\nFrom: Maxime Ripard <maxime@cerno.tech>\nDate: Tue, 29 Jun 2021 11:36:38 +0200\nSubject: [PATCH] drm/vc4: hdmi: Put the device on error in\n pre_crtc_configure\n\nIn the vc4_hdmi_encoder_pre_crtc_configure() function error path we\nnever actually call pm_runtime_put() even though\npm_runtime_resume_and_get() is our very first call.\n\nFixes: 4f6e3d66ac52 (\"drm/vc4: Add runtime PM support to the HDMI encoder driver\")\nSigned-off-by: Maxime Ripard <maxime@cerno.tech>\n---\n drivers/gpu/drm/vc4/vc4_hdmi.c | 6 ++++++\n 1 file changed, 6 insertions(+)\n\n--- a/drivers/gpu/drm/vc4/vc4_hdmi.c\n+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c\n@@ -901,6 +901,7 @@ static void vc4_hdmi_encoder_pre_crtc_co\n \tret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev);\n \tif (ret < 0) {\n \t\tDRM_ERROR(\"Failed to retain power domain: %d\\n\", ret);\n+\t\tpm_runtime_put(&vc4_hdmi->pdev->dev);\n \t\treturn;\n \t}\n \n@@ -908,12 +909,14 @@ static void vc4_hdmi_encoder_pre_crtc_co\n \tret = clk_set_rate(vc4_hdmi->pixel_clock, pixel_rate);\n \tif (ret) {\n \t\tDRM_ERROR(\"Failed to set pixel clock rate: %d\\n\", ret);\n+\t\tpm_runtime_put(&vc4_hdmi->pdev->dev);\n \t\treturn;\n \t}\n \n \tret = clk_prepare_enable(vc4_hdmi->pixel_clock);\n \tif (ret) {\n \t\tDRM_ERROR(\"Failed to turn on pixel clock: %d\\n\", ret);\n+\t\tpm_runtime_put(&vc4_hdmi->pdev->dev);\n \t\treturn;\n \t}\n \n@@ -921,6 +924,7 @@ static void vc4_hdmi_encoder_pre_crtc_co\n \tvc4_hdmi->hsm_req = clk_request_start(vc4_hdmi->hsm_clock, hsm_rate);\n \tif (IS_ERR(vc4_hdmi->hsm_req)) {\n \t\tDRM_ERROR(\"Failed to set HSM clock rate: %ld\\n\", PTR_ERR(vc4_hdmi->hsm_req));\n+\t\tpm_runtime_put(&vc4_hdmi->pdev->dev);\n \t\treturn;\n \t}\n \n@@ -942,6 +946,7 @@ static void vc4_hdmi_encoder_pre_crtc_co\n \t\tclk_request_done(vc4_hdmi->hsm_req);\n \t\tclk_disable_unprepare(vc4_hdmi->hsm_clock);\n \t\tclk_disable_unprepare(vc4_hdmi->pixel_clock);\n+\t\tpm_runtime_put(&vc4_hdmi->pdev->dev);\n \t\treturn;\n \t}\n \n@@ -953,6 +958,7 @@ static void vc4_hdmi_encoder_pre_crtc_co\n \t\tclk_request_done(vc4_hdmi->hsm_req);\n \t\tclk_disable_unprepare(vc4_hdmi->hsm_clock);\n \t\tclk_disable_unprepare(vc4_hdmi->pixel_clock);\n+\t\tpm_runtime_put(&vc4_hdmi->pdev->dev);\n \t\treturn;\n \t}\n \n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0668-drm-vc4-hdmi-Split-the-CEC-disable-enable-functions-.patch",
    "content": "From 7090c69d64c3871867e86adc5bf568d89608c965 Mon Sep 17 00:00:00 2001\nFrom: Maxime Ripard <maxime@cerno.tech>\nDate: Tue, 29 Jun 2021 09:53:52 +0200\nSubject: [PATCH] drm/vc4: hdmi: Split the CEC disable / enable\n functions in two\n\nIn order to ease further additions to the CEC enable and disable, let's\nsplit the function into two functions, one to enable and the other to\ndisable.\n\nSigned-off-by: Maxime Ripard <maxime@cerno.tech>\n---\n drivers/gpu/drm/vc4/vc4_hdmi.c | 75 ++++++++++++++++++++--------------\n 1 file changed, 45 insertions(+), 30 deletions(-)\n\n--- a/drivers/gpu/drm/vc4/vc4_hdmi.c\n+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c\n@@ -1756,7 +1756,7 @@ static irqreturn_t vc4_cec_irq_handler(i\n \treturn ret;\n }\n \n-static int vc4_hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable)\n+static int vc4_hdmi_cec_enable(struct cec_adapter *adap)\n {\n \tstruct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);\n \t/* clock period in microseconds */\n@@ -1769,38 +1769,53 @@ static int vc4_hdmi_cec_adap_enable(stru\n \tval |= ((4700 / usecs) << VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT) |\n \t       ((4500 / usecs) << VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT);\n \n-\tif (enable) {\n-\t\tHDMI_WRITE(HDMI_CEC_CNTRL_5, val |\n-\t\t\t   VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);\n-\t\tHDMI_WRITE(HDMI_CEC_CNTRL_5, val);\n-\t\tHDMI_WRITE(HDMI_CEC_CNTRL_2,\n-\t\t\t   ((1500 / usecs) << VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT) |\n-\t\t\t   ((1300 / usecs) << VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT) |\n-\t\t\t   ((800 / usecs) << VC4_HDMI_CEC_CNT_TO_800_US_SHIFT) |\n-\t\t\t   ((600 / usecs) << VC4_HDMI_CEC_CNT_TO_600_US_SHIFT) |\n-\t\t\t   ((400 / usecs) << VC4_HDMI_CEC_CNT_TO_400_US_SHIFT));\n-\t\tHDMI_WRITE(HDMI_CEC_CNTRL_3,\n-\t\t\t   ((2750 / usecs) << VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT) |\n-\t\t\t   ((2400 / usecs) << VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT) |\n-\t\t\t   ((2050 / usecs) << VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT) |\n-\t\t\t   ((1700 / usecs) << VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT));\n-\t\tHDMI_WRITE(HDMI_CEC_CNTRL_4,\n-\t\t\t   ((4300 / usecs) << VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT) |\n-\t\t\t   ((3900 / usecs) << VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT) |\n-\t\t\t   ((3600 / usecs) << VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT) |\n-\t\t\t   ((3500 / usecs) << VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT));\n-\n-\t\tif (!vc4_hdmi->variant->external_irq_controller)\n-\t\t\tHDMI_WRITE(HDMI_CEC_CPU_MASK_CLEAR, VC4_HDMI_CPU_CEC);\n-\t} else {\n-\t\tif (!vc4_hdmi->variant->external_irq_controller)\n-\t\t\tHDMI_WRITE(HDMI_CEC_CPU_MASK_SET, VC4_HDMI_CPU_CEC);\n-\t\tHDMI_WRITE(HDMI_CEC_CNTRL_5, val |\n-\t\t\t   VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);\n-\t}\n+\tHDMI_WRITE(HDMI_CEC_CNTRL_5, val |\n+\t\t   VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);\n+\tHDMI_WRITE(HDMI_CEC_CNTRL_5, val);\n+\tHDMI_WRITE(HDMI_CEC_CNTRL_2,\n+\t\t   ((1500 / usecs) << VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT) |\n+\t\t   ((1300 / usecs) << VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT) |\n+\t\t   ((800 / usecs) << VC4_HDMI_CEC_CNT_TO_800_US_SHIFT) |\n+\t\t   ((600 / usecs) << VC4_HDMI_CEC_CNT_TO_600_US_SHIFT) |\n+\t\t   ((400 / usecs) << VC4_HDMI_CEC_CNT_TO_400_US_SHIFT));\n+\tHDMI_WRITE(HDMI_CEC_CNTRL_3,\n+\t\t   ((2750 / usecs) << VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT) |\n+\t\t   ((2400 / usecs) << VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT) |\n+\t\t   ((2050 / usecs) << VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT) |\n+\t\t   ((1700 / usecs) << VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT));\n+\tHDMI_WRITE(HDMI_CEC_CNTRL_4,\n+\t\t   ((4300 / usecs) << VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT) |\n+\t\t   ((3900 / usecs) << VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT) |\n+\t\t   ((3600 / usecs) << VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT) |\n+\t\t   ((3500 / usecs) << VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT));\n+\n+\tif (!vc4_hdmi->variant->external_irq_controller)\n+\t\tHDMI_WRITE(HDMI_CEC_CPU_MASK_CLEAR, VC4_HDMI_CPU_CEC);\n+\n \treturn 0;\n }\n \n+static int vc4_hdmi_cec_disable(struct cec_adapter *adap)\n+{\n+\tstruct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);\n+\n+\tif (!vc4_hdmi->variant->external_irq_controller)\n+\t\tHDMI_WRITE(HDMI_CEC_CPU_MASK_SET, VC4_HDMI_CPU_CEC);\n+\n+\tHDMI_WRITE(HDMI_CEC_CNTRL_5, HDMI_READ(HDMI_CEC_CNTRL_5) |\n+\t\t   VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);\n+\n+\treturn 0;\n+}\n+\n+static int vc4_hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable)\n+{\n+\tif (enable)\n+\t\treturn vc4_hdmi_cec_enable(adap);\n+\telse\n+\t\treturn vc4_hdmi_cec_disable(adap);\n+}\n+\n static int vc4_hdmi_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr)\n {\n \tstruct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0670-drm-vc4-hdmi-Add-missing-clk_disable_unprepare-on-er.patch",
    "content": "From 8865bc13c5e22daa653ce4c1c419a6efaa701dac Mon Sep 17 00:00:00 2001\nFrom: Maxime Ripard <maxime@cerno.tech>\nDate: Fri, 2 Jul 2021 17:44:56 +0200\nSubject: [PATCH] drm/vc4: hdmi: Add missing clk_disable_unprepare on\n error path\n\nIn vc4_hdmi_encoder_pre_crtc_configure, if clk_request_start for the HSM\nclock fails, we don't call clk_disable_unprepare on the pixel clock even\nthough it's enabled by now.\n\nMake sure it's there to avoid leaking that reference.\n\nFixes: cd4cb49dc5bb (\"drm/vc4: hdmi: Adjust HSM clock rate depending on pixel rate\")\nSigned-off-by: Maxime Ripard <maxime@cerno.tech>\n---\n drivers/gpu/drm/vc4/vc4_hdmi.c | 1 +\n 1 file changed, 1 insertion(+)\n\n--- a/drivers/gpu/drm/vc4/vc4_hdmi.c\n+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c\n@@ -924,6 +924,7 @@ static void vc4_hdmi_encoder_pre_crtc_co\n \tvc4_hdmi->hsm_req = clk_request_start(vc4_hdmi->hsm_clock, hsm_rate);\n \tif (IS_ERR(vc4_hdmi->hsm_req)) {\n \t\tDRM_ERROR(\"Failed to set HSM clock rate: %ld\\n\", PTR_ERR(vc4_hdmi->hsm_req));\n+\t\tclk_disable_unprepare(vc4_hdmi->pixel_clock);\n \t\tpm_runtime_put(&vc4_hdmi->pdev->dev);\n \t\treturn;\n \t}\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0671-drm-vc4-hdmi-Warn-if-we-access-the-controller-while-.patch",
    "content": "From f67dbf74cc7bce6d85b7c4b5b917c30f2dfc2626 Mon Sep 17 00:00:00 2001\nFrom: Maxime Ripard <maxime@cerno.tech>\nDate: Mon, 5 Jul 2021 10:32:30 +0200\nSubject: [PATCH] drm/vc4: hdmi: Warn if we access the controller while\n disabled\n\nWe've had many silent hangs where the kernel would look like it just\nstalled due to the access to one of the HDMI registers while the\ncontroller was disabled.\n\nAdd a warning if we're about to do that so that it's at least not silent\nanymore.\n\nSigned-off-by: Maxime Ripard <maxime@cerno.tech>\n---\n drivers/gpu/drm/vc4/vc4_hdmi_regs.h | 6 ++++++\n 1 file changed, 6 insertions(+)\n\n--- a/drivers/gpu/drm/vc4/vc4_hdmi_regs.h\n+++ b/drivers/gpu/drm/vc4/vc4_hdmi_regs.h\n@@ -1,6 +1,8 @@\n #ifndef _VC4_HDMI_REGS_H_\n #define _VC4_HDMI_REGS_H_\n \n+#include <linux/pm_runtime.h>\n+\n #include \"vc4_hdmi.h\"\n \n #define VC4_HDMI_PACKET_STRIDE\t\t\t0x24\n@@ -412,6 +414,8 @@ static inline u32 vc4_hdmi_read(struct v\n \tconst struct vc4_hdmi_variant *variant = hdmi->variant;\n \tvoid __iomem *base;\n \n+\tWARN_ON(!pm_runtime_active(&hdmi->pdev->dev));\n+\n \tif (reg >= variant->num_registers) {\n \t\tdev_warn(&hdmi->pdev->dev,\n \t\t\t \"Invalid register ID %u\\n\", reg);\n@@ -438,6 +442,8 @@ static inline void vc4_hdmi_write(struct\n \tconst struct vc4_hdmi_variant *variant = hdmi->variant;\n \tvoid __iomem *base;\n \n+\tWARN_ON(!pm_runtime_active(&hdmi->pdev->dev));\n+\n \tif (reg >= variant->num_registers) {\n \t\tdev_warn(&hdmi->pdev->dev,\n \t\t\t \"Invalid register ID %u\\n\", reg);\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0673-vc4-drv-Only-notify-firmware-of-display-done-with-km.patch",
    "content": "From b14001459c04ec0d4a99c1a422077fbce5a0aebc Mon Sep 17 00:00:00 2001\nFrom: Dom Cobley <popcornmix@gmail.com>\nDate: Mon, 5 Jul 2021 11:43:12 +0100\nSubject: [PATCH] vc4/drv: Only notify firmware of display done with\n kms\n\nfkms driver still wants firmware display to be active\n\nSigned-off-by: Dom Cobley <popcornmix@gmail.com>\n---\n drivers/gpu/drm/vc4/vc4_drv.c | 14 +++++++++++++-\n 1 file changed, 13 insertions(+), 1 deletion(-)\n\n--- a/drivers/gpu/drm/vc4/vc4_drv.c\n+++ b/drivers/gpu/drm/vc4/vc4_drv.c\n@@ -258,6 +258,18 @@ const struct of_device_id vc4_dma_range_\n \t{}\n };\n \n+/*\n+ * we need this helper function for determining presence of fkms\n+ * before it's been bound\n+ */\n+static bool firmware_kms(void)\n+{\n+\treturn of_device_is_available(of_find_compatible_node(NULL, NULL,\n+\t       \"raspberrypi,rpi-firmware-kms\")) ||\n+\t       of_device_is_available(of_find_compatible_node(NULL, NULL,\n+\t       \"raspberrypi,rpi-firmware-kms-2711\"));\n+}\n+\n static int vc4_drm_bind(struct device *dev)\n {\n \tstruct platform_device *pdev = to_platform_device(dev);\n@@ -318,7 +330,7 @@ static int vc4_drm_bind(struct device *d\n \n \tdrm_fb_helper_remove_conflicting_framebuffers(NULL, \"vc4drmfb\", false);\n \n-\tif (vc4->firmware) {\n+\tif (vc4->firmware && !firmware_kms()) {\n \t\tret = rpi_firmware_property(vc4->firmware,\n \t\t\t\t\t    RPI_FIRMWARE_NOTIFY_DISPLAY_DONE,\n \t\t\t\t\t    NULL, 0);\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0674-dwc_otg-Update-NetBSD-usb.h-header-licence.patch",
    "content": "From 8bc1dcb94a58098b6d6f516c4c0141bded0ca2a1 Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.com>\nDate: Mon, 5 Jul 2021 19:38:21 +0100\nSubject: [PATCH] dwc_otg: Update NetBSD usb.h header licence\n\nNetBSD have changed their licensing requirements such that the 2-clause\nlicence is preferred. Update usb.h in the downstream dwc_otg code\naccordingly.\n\nSee https://www.netbsd.org/about/redistribution.html for more\ninformation.\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.com>\n---\n drivers/usb/host/dwc_common_port/usb.h | 7 -------\n 1 file changed, 7 deletions(-)\n\n--- a/drivers/usb/host/dwc_common_port/usb.h\n+++ b/drivers/usb/host/dwc_common_port/usb.h\n@@ -14,13 +14,6 @@\n  * 2. Redistributions in binary form must reproduce the above copyright\n  *    notice, this list of conditions and the following disclaimer in the\n  *    documentation and/or other materials provided with the distribution.\n- * 3. All advertising materials mentioning features or use of this software\n- *    must display the following acknowledgement:\n- *        This product includes software developed by the NetBSD\n- *        Foundation, Inc. and its contributors.\n- * 4. Neither the name of The NetBSD Foundation nor the names of its\n- *    contributors may be used to endorse or promote products derived\n- *    from this software without specific prior written permission.\n  *\n  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS\n  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0675-drm-vc4-hdmi-Drop-devm-interrupt-handler-for-CEC-int.patch",
    "content": "From 687a0fc86f37e0bc74c8382c0d89b0929fade1de Mon Sep 17 00:00:00 2001\nFrom: Maxime Ripard <maxime@cerno.tech>\nDate: Mon, 5 Jul 2021 15:47:43 +0200\nSubject: [PATCH] drm/vc4: hdmi: Drop devm interrupt handler for CEC\n interrupts\n\nThe CEC interrupt handlers are registered through the\ndevm_request_threaded_irq function. However, while free_irq is indeed\ncalled properly when the device is unbound or bind fails, it's called\nafter unbind or bind is done.\n\nIn our particular case, it means that on failure it creates a window\nwhere our interrupt handler can be called, but we're freeing every\nresource (CEC adapter, DRM objects, etc.) it might need.\n\nIn order to address this, let's switch to the non-devm variant to\ncontrol better when the handler will be unregistered and allow us to\nmake it safe.\n\nFixes: 15b4511a4af6 (\"drm/vc4: add HDMI CEC support\")\nSigned-off-by: Maxime Ripard <maxime@cerno.tech>\n---\n drivers/gpu/drm/vc4/vc4_hdmi.c | 49 +++++++++++++++++++++++-----------\n 1 file changed, 33 insertions(+), 16 deletions(-)\n\n--- a/drivers/gpu/drm/vc4/vc4_hdmi.c\n+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c\n@@ -1896,25 +1896,23 @@ static int vc4_hdmi_cec_init(struct vc4_\n \tvc4_hdmi_cec_update_clk_div(vc4_hdmi);\n \n \tif (vc4_hdmi->variant->external_irq_controller) {\n-\t\tret = devm_request_threaded_irq(&pdev->dev,\n-\t\t\t\t\t\tplatform_get_irq_byname(pdev, \"cec-rx\"),\n+\t\tret = request_threaded_irq(platform_get_irq_byname(pdev, \"cec-rx\"),\n \t\t\t\t\t\tvc4_cec_irq_handler_rx_bare,\n \t\t\t\t\t\tvc4_cec_irq_handler_rx_thread, 0,\n \t\t\t\t\t\t\"vc4 hdmi cec rx\", vc4_hdmi);\n \t\tif (ret)\n \t\t\tgoto err_delete_cec_adap;\n \n-\t\tret = devm_request_threaded_irq(&pdev->dev,\n-\t\t\t\t\t\tplatform_get_irq_byname(pdev, \"cec-tx\"),\n+\t\tret = request_threaded_irq(platform_get_irq_byname(pdev, \"cec-tx\"),\n \t\t\t\t\t\tvc4_cec_irq_handler_tx_bare,\n \t\t\t\t\t\tvc4_cec_irq_handler_tx_thread, 0,\n \t\t\t\t\t\t\"vc4 hdmi cec tx\", vc4_hdmi);\n \t\tif (ret)\n-\t\t\tgoto err_delete_cec_adap;\n+\t\t\tgoto err_remove_cec_rx_handler;\n \t} else {\n \t\tHDMI_WRITE(HDMI_CEC_CPU_MASK_SET, 0xffffffff);\n \n-\t\tret = devm_request_threaded_irq(&pdev->dev, platform_get_irq(pdev, 0),\n+\t\tret = request_threaded_irq(platform_get_irq(pdev, 0),\n \t\t\t\t\t\tvc4_cec_irq_handler,\n \t\t\t\t\t\tvc4_cec_irq_handler_thread, 0,\n \t\t\t\t\t\t\"vc4 hdmi cec\", vc4_hdmi);\n@@ -1924,10 +1922,20 @@ static int vc4_hdmi_cec_init(struct vc4_\n \n \tret = cec_register_adapter(vc4_hdmi->cec_adap, &pdev->dev);\n \tif (ret < 0)\n-\t\tgoto err_delete_cec_adap;\n+\t\tgoto err_remove_handlers;\n \n \treturn 0;\n \n+err_remove_handlers:\n+\tif (vc4_hdmi->variant->external_irq_controller)\n+\t\tfree_irq(platform_get_irq_byname(pdev, \"cec-tx\"), vc4_hdmi);\n+\telse\n+\t\tfree_irq(platform_get_irq(pdev, 0), vc4_hdmi);\n+\n+err_remove_cec_rx_handler:\n+\tif (vc4_hdmi->variant->external_irq_controller)\n+\t\tfree_irq(platform_get_irq_byname(pdev, \"cec-rx\"), vc4_hdmi);\n+\n err_delete_cec_adap:\n \tcec_delete_adapter(vc4_hdmi->cec_adap);\n \n@@ -1936,6 +1944,15 @@ err_delete_cec_adap:\n \n static void vc4_hdmi_cec_exit(struct vc4_hdmi *vc4_hdmi)\n {\n+\tstruct platform_device *pdev = vc4_hdmi->pdev;\n+\n+\tif (vc4_hdmi->variant->external_irq_controller) {\n+\t\tfree_irq(platform_get_irq_byname(pdev, \"cec-rx\"), vc4_hdmi);\n+\t\tfree_irq(platform_get_irq_byname(pdev, \"cec-tx\"), vc4_hdmi);\n+\t} else {\n+\t\tfree_irq(platform_get_irq(pdev, 0), vc4_hdmi);\n+\t}\n+\n \tcec_unregister_adapter(vc4_hdmi->cec_adap);\n }\n #else\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0676-drm-vc4-hdmi-Drop-devm-interrupt-handler-for-hotplug.patch",
    "content": "From fda46a52e84a5160d7277e55e1c1be376b0ba579 Mon Sep 17 00:00:00 2001\nFrom: Maxime Ripard <maxime@cerno.tech>\nDate: Mon, 5 Jul 2021 17:31:48 +0200\nSubject: [PATCH] drm/vc4: hdmi: Drop devm interrupt handler for\n hotplug interrupts\n\nThe hotplugs interrupt handlers are registered through the\ndevm_request_threaded_irq function. However, while free_irq is indeed\ncalled properly when the device is unbound or bind fails, it's called\nafter unbind or bind is done.\n\nIn our particular case, it means that on failure it creates a window\nwhere our interrupt handler can be called, but we're freeing every\nresource (CEC adapter, DRM objects, etc.) it might need.\n\nIn order to address this, let's switch to the non-devm variant to\ncontrol better when the handler will be unregistered and allow us to\nmake it safe.\n\nFixes: f4790083c7c2 (\"drm/vc4: hdmi: Rely on interrupts to handle hotplug\")\nSigned-off-by: Maxime Ripard <maxime@cerno.tech>\n---\n drivers/gpu/drm/vc4/vc4_hdmi.c | 41 +++++++++++++++++++++++-----------\n 1 file changed, 28 insertions(+), 13 deletions(-)\n\n--- a/drivers/gpu/drm/vc4/vc4_hdmi.c\n+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c\n@@ -1612,26 +1612,28 @@ static irqreturn_t vc4_hdmi_hpd_irq_thre\n static int vc4_hdmi_hotplug_init(struct vc4_hdmi *vc4_hdmi)\n {\n \tstruct platform_device *pdev = vc4_hdmi->pdev;\n-\tstruct device *dev = &pdev->dev;\n \tstruct drm_connector *connector = &vc4_hdmi->connector;\n \tint ret;\n \n \tif (vc4_hdmi->variant->external_irq_controller) {\n-\t\tret = devm_request_threaded_irq(dev,\n-\t\t\t\t\t\tplatform_get_irq_byname(pdev, \"hpd-connected\"),\n-\t\t\t\t\t\tNULL,\n-\t\t\t\t\t\tvc4_hdmi_hpd_irq_thread, IRQF_ONESHOT,\n-\t\t\t\t\t\t\"vc4 hdmi hpd connected\", vc4_hdmi);\n+\t\tunsigned int hpd_con = platform_get_irq_byname(pdev, \"hpd-connected\");\n+\t\tunsigned int hpd_rm = platform_get_irq_byname(pdev, \"hpd-removed\");\n+\n+\t\tret = request_threaded_irq(hpd_con,\n+\t\t\t\t\t   NULL,\n+\t\t\t\t\t   vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT,\n+\t\t\t\t\t   \"vc4 hdmi hpd connected\", vc4_hdmi);\n \t\tif (ret)\n \t\t\treturn ret;\n \n-\t\tret = devm_request_threaded_irq(dev,\n-\t\t\t\t\t\tplatform_get_irq_byname(pdev, \"hpd-removed\"),\n-\t\t\t\t\t\tNULL,\n-\t\t\t\t\t\tvc4_hdmi_hpd_irq_thread, IRQF_ONESHOT,\n-\t\t\t\t\t\t\"vc4 hdmi hpd disconnected\", vc4_hdmi);\n-\t\tif (ret)\n+\t\tret = request_threaded_irq(hpd_rm,\n+\t\t\t\t\t   NULL,\n+\t\t\t\t\t   vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT,\n+\t\t\t\t\t   \"vc4 hdmi hpd disconnected\", vc4_hdmi);\n+\t\tif (ret) {\n+\t\t\tfree_irq(hpd_con, vc4_hdmi);\n \t\t\treturn ret;\n+\t\t}\n \n \t\tconnector->polled = DRM_CONNECTOR_POLL_HPD;\n \t}\n@@ -1639,6 +1641,16 @@ static int vc4_hdmi_hotplug_init(struct\n \treturn 0;\n }\n \n+static void vc4_hdmi_hotplug_exit(struct vc4_hdmi *vc4_hdmi)\n+{\n+\tstruct platform_device *pdev = vc4_hdmi->pdev;\n+\n+\tif (vc4_hdmi->variant->external_irq_controller) {\n+\t\tfree_irq(platform_get_irq_byname(pdev, \"hpd-connected\"), vc4_hdmi);\n+\t\tfree_irq(platform_get_irq_byname(pdev, \"hpd-removed\"), vc4_hdmi);\n+\t}\n+}\n+\n #ifdef CONFIG_DRM_VC4_HDMI_CEC\n static irqreturn_t vc4_cec_irq_handler_rx_thread(int irq, void *priv)\n {\n@@ -2305,7 +2317,7 @@ static int vc4_hdmi_bind(struct device *\n \n \tret = vc4_hdmi_cec_init(vc4_hdmi);\n \tif (ret)\n-\t\tgoto err_destroy_conn;\n+\t\tgoto err_free_hotplug;\n \n \tret = vc4_hdmi_audio_init(vc4_hdmi);\n \tif (ret)\n@@ -2319,6 +2331,8 @@ static int vc4_hdmi_bind(struct device *\n \n err_free_cec:\n \tvc4_hdmi_cec_exit(vc4_hdmi);\n+err_free_hotplug:\n+\tvc4_hdmi_hotplug_exit(vc4_hdmi);\n err_destroy_conn:\n \tvc4_hdmi_connector_destroy(&vc4_hdmi->connector);\n err_destroy_encoder:\n@@ -2360,6 +2374,7 @@ static void vc4_hdmi_unbind(struct devic\n \tkfree(vc4_hdmi->hd_regset.regs);\n \n \tvc4_hdmi_cec_exit(vc4_hdmi);\n+\tvc4_hdmi_hotplug_exit(vc4_hdmi);\n \tvc4_hdmi_connector_destroy(&vc4_hdmi->connector);\n \tdrm_encoder_cleanup(&vc4_hdmi->encoder.base.base);\n \n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0677-drm-vc4-hdmi-Only-call-into-DRM-framework-if-registe.patch",
    "content": "From a4ea60641c2e5ac11d3472e723b33b36f16e6bcb Mon Sep 17 00:00:00 2001\nFrom: Maxime Ripard <maxime@cerno.tech>\nDate: Mon, 5 Jul 2021 16:15:56 +0200\nSubject: [PATCH] drm/vc4: hdmi: Only call into DRM framework if\n registered\n\nOur hotplug handler will currently call the drm_kms_helper_hotplug_event\nevery time a hotplug interrupt is called.\n\nHowever, since the device is registered after all the drivers have\nfinished their bind callback, we have a window between when we install\nour interrupt handler and when drm_dev_register() is eventually called\nwhere our handler can run and call drm_kms_helper_hotplug_event but the\ndevice hasn't been registered yet, causing a null pointer dereference.\n\nFix this by making sure we only call drm_kms_helper_hotplug_event if our\ndevice has been properly registered.\n\nFixes: f4790083c7c2 (\"drm/vc4: hdmi: Rely on interrupts to handle hotplug\")\nSigned-off-by: Maxime Ripard <maxime@cerno.tech>\n---\n drivers/gpu/drm/vc4/vc4_hdmi.c | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/drivers/gpu/drm/vc4/vc4_hdmi.c\n+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c\n@@ -1603,7 +1603,7 @@ static irqreturn_t vc4_hdmi_hpd_irq_thre\n \tstruct vc4_hdmi *vc4_hdmi = priv;\n \tstruct drm_device *dev = vc4_hdmi->connector.dev;\n \n-\tif (dev)\n+\tif (dev && dev->registered)\n \t\tdrm_kms_helper_hotplug_event(dev);\n \n \treturn IRQ_HANDLED;\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0678-bcm2711_thermal-Don-t-clamp-temperature-at-zero.patch",
    "content": "From 8f367667b69df3af3d5fa2695f14f97910beadfa Mon Sep 17 00:00:00 2001\nFrom: Dom Cobley <popcornmix@gmail.com>\nDate: Thu, 8 Jul 2021 13:48:11 +0100\nSubject: [PATCH] bcm2711_thermal: Don't clamp temperature at zero\n\nThe temperature sensor is valid below zero and the linux framework is happy with it.\n\nSee: https://www.raspberrypi.org/forums/viewtopic.php?f=98&t=315382\nSigned-off-by: Dom Cobley <popcornmix@gmail.com>\n---\n drivers/thermal/broadcom/bcm2711_thermal.c | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/drivers/thermal/broadcom/bcm2711_thermal.c\n+++ b/drivers/thermal/broadcom/bcm2711_thermal.c\n@@ -52,7 +52,7 @@ static int bcm2711_get_temp(void *data,\n \t/* Convert a HW code to a temperature reading (millidegree celsius) */\n \tt = slope * val + offset;\n \n-\t*temp = t < 0 ? 0 : t;\n+\t*temp = t;\n \n \treturn 0;\n }\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0679-media-bcm2835-unicam-Forward-input-status-from-subde.patch",
    "content": "From bfe4361859005edec5e7ae73274c363910f56d7f Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Jakub=20Van=C4=9Bk?= <linuxtardis@gmail.com>\nDate: Wed, 7 Jul 2021 22:48:20 +0200\nSubject: [PATCH] media: bcm2835-unicam: Forward input status from\n subdevice\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nThe vidioc_enum_input() v4l2 ioctl is capable of returning\nsensor/input status as well. This is used in current\nGStreamer HEAD for signal detection [1].\n\nbcm2835-unicam does handle this syscall, but it didn't ask\nthe subdevice driver about the input status. The input then\nappeared as always present.\n\nThis commit adds the necessary query. There is a precedent for\nthis - the R-Car VIN V4L2 driver does a similar call [2].\n\n[1]: https://gitlab.freedesktop.org/gstreamer/gst-plugins-good/-/blob/ce0be27caf69aa9d96b73bc2b50737451b6f6936/sys/v4l2/gstv4l2src.c#L553\n[2]: https://github.com/raspberrypi/linux/blob/7fb9d006d3ff3baf2e205e0c85c4e4fd0a64fcd0/drivers/media/platform/rcar-vin/rcar-v4l2.c#L548\n\nSigned-off-by: Jakub Vaněk <linuxtardis@gmail.com>\n---\n drivers/media/platform/bcm2835/bcm2835-unicam.c | 9 +++++++++\n 1 file changed, 9 insertions(+)\n\n--- a/drivers/media/platform/bcm2835/bcm2835-unicam.c\n+++ b/drivers/media/platform/bcm2835/bcm2835-unicam.c\n@@ -1806,6 +1806,7 @@ static int unicam_enum_input(struct file\n {\n \tstruct unicam_node *node = video_drvdata(file);\n \tstruct unicam_device *dev = node->dev;\n+\tint ret;\n \n \tif (inp->index != 0)\n \t\treturn -EINVAL;\n@@ -1822,6 +1823,14 @@ static int unicam_enum_input(struct file\n \t\tinp->capabilities = 0;\n \t\tinp->std = 0;\n \t}\n+\n+\tif (v4l2_subdev_has_op(dev->sensor, video, g_input_status)) {\n+\t\tret = v4l2_subdev_call(dev->sensor, video, g_input_status,\n+\t\t\t\t       &inp->status);\n+\t\tif (ret < 0)\n+\t\t\treturn ret;\n+\t}\n+\n \tsnprintf(inp->name, sizeof(inp->name), \"Camera 0\");\n \treturn 0;\n }\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0680-overlays-Add-overlay-for-Chipdip-I2S-master-DAC.patch",
    "content": "From 63f4efd396406bcfea7f72c4ba883a9acf0e039c Mon Sep 17 00:00:00 2001\nFrom: \"chipdip.lab\" <43340836+chipdipru@users.noreply.github.com>\nDate: Fri, 9 Jul 2021 16:00:22 +0300\nSubject: [PATCH] overlays: Add overlay for Chipdip I2S master DAC\n\nSigned-off-by: Evgenij Sapunov <evgenij.sapunov@chipdip.ru>\n---\n arch/arm/boot/dts/overlays/Makefile           |  1 +\n arch/arm/boot/dts/overlays/README             |  6 +++\n .../chipdip-i2s-master-dac-overlay.dts        | 53 +++++++++++++++++++\n 3 files changed, 60 insertions(+)\n create mode 100644 arch/arm/boot/dts/overlays/chipdip-i2s-master-dac-overlay.dts\n\n--- a/arch/arm/boot/dts/overlays/Makefile\n+++ b/arch/arm/boot/dts/overlays/Makefile\n@@ -30,6 +30,7 @@ dtbo-$(CONFIG_ARCH_BCM2835) += \\\n \taudiosense-pi.dtbo \\\n \taudremap.dtbo \\\n \tbalena-fin.dtbo \\\n+\tchipdip-i2s-master-dac.dtbo \\\n \tcma.dtbo \\\n \tdht11.dtbo \\\n \tdionaudio-loco.dtbo \\\n--- a/arch/arm/boot/dts/overlays/README\n+++ b/arch/arm/boot/dts/overlays/README\n@@ -622,6 +622,12 @@ Info:   This overlay is now deprecated -\n Load:   <Deprecated>\n \n \n+Name:   chipdip-i2s-master-dac\n+Info:   Configures Raspberry PI to work as I2S slave with BCLK=64Fs.\n+Load:   dtoverlay=chipdip-i2s-master-dac\n+Params: <None>\n+\n+\n Name:   cma\n Info:   Set custom CMA sizes, only use if you know what you are doing, might\n         clash with other overlays like vc4-fkms-v3d and vc4-kms-v3d.\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/chipdip-i2s-master-dac-overlay.dts\n@@ -0,0 +1,53 @@\n+/*\n+ * Device Tree overlay for ChipDip I2S master DAC\n+ */\n+\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+    compatible = \"brcm,bcm2835\";\n+    fragment@0 {\n+        target = <&sound>;\n+        __overlay__ {\n+            compatible = \"simple-audio-card\";\n+            simple-audio-card,name = \"ChipDip I2S master DAC\";\n+            status=\"okay\";\n+            playback_link: simple-audio-card,dai-link@0 {\n+                format = \"i2s\";\n+\t\tbitclock-master = <&p_codec_dai>;\n+                frame-master = <&p_codec_dai>;\n+                p_cpu_dai: cpu {\n+                        sound-dai = <&i2s>;\n+\t\t\tdai-tdm-slot-num = <2>;\n+\t\t\tdai-tdm-slot-width = <32>;\n+\t\t\t\t};\n+\n+                p_codec_dai: codec {\n+                        sound-dai = <&codec_out>;\n+                };\n+            };\n+        };\n+    }; \n+\n+    fragment@1 {\n+        target-path = \"/\";\n+        __overlay__ {\n+            codec_out: spdif-transmitter {\n+                #address-cells = <0>;\n+                #size-cells = <0>;\n+                #sound-dai-cells = <0>;\n+                compatible = \"linux,spdif-dit\";\n+                status = \"okay\";\n+            };\n+        };\n+    };\n+ \n+    fragment@2 {\n+        target = <&i2s>;\n+        __overlay__ {\n+            #sound-dai-cells = <0>;\n+            status = \"okay\";\n+        };\n+    };\n+}; \n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0681-drm-Introduce-an-atomic_commit_setup-function.patch",
    "content": "From 86fc6b59ae170399aaf8fd9880f1a3f79948f5a3 Mon Sep 17 00:00:00 2001\nFrom: Maxime Ripard <maxime@cerno.tech>\nDate: Fri, 4 Dec 2020 16:11:32 +0100\nSubject: [PATCH] drm: Introduce an atomic_commit_setup function\n\nPrivate objects storing a state shared across all CRTCs need to be\ncarefully handled to avoid a use-after-free issue.\n\nThe proper way to do this to track all the commits using that shared\nstate and wait for the previous commits to be done before going on with\nthe current one to avoid the reordering of commits that could occur.\n\nHowever, this commit setup needs to be done after\ndrm_atomic_helper_setup_commit(), because before the CRTC commit\nstructure hasn't been allocated before, and before the workqueue is\nscheduled, because we would be potentially reordered already otherwise.\n\nThat means that drivers currently have to roll their own\ndrm_atomic_helper_commit() function, even though it would be identical\nif not for the commit setup.\n\nLet's introduce a hook to do so that would be called as part of\ndrm_atomic_helper_commit, allowing us to reuse the atomic helpers.\n\nSuggested-by: Daniel Vetter <daniel.vetter@ffwll.ch>\nSigned-off-by: Maxime Ripard <maxime@cerno.tech>\n---\n drivers/gpu/drm/drm_atomic_helper.c      |  9 +++++++++\n include/drm/drm_modeset_helper_vtables.h | 21 +++++++++++++++++++++\n 2 files changed, 30 insertions(+)\n\n--- a/drivers/gpu/drm/drm_atomic_helper.c\n+++ b/drivers/gpu/drm/drm_atomic_helper.c\n@@ -2039,6 +2039,9 @@ crtc_or_fake_commit(struct drm_atomic_st\n  * should always call this function from their\n  * &drm_mode_config_funcs.atomic_commit hook.\n  *\n+ * Drivers that need to extend the commit setup to private objects can use the\n+ * &drm_mode_config_helper_funcs.atomic_commit_setup hook.\n+ *\n  * To be able to use this support drivers need to use a few more helper\n  * functions. drm_atomic_helper_wait_for_dependencies() must be called before\n  * actually committing the hardware state, and for nonblocking commits this call\n@@ -2082,8 +2085,11 @@ int drm_atomic_helper_setup_commit(struc\n \tstruct drm_plane *plane;\n \tstruct drm_plane_state *old_plane_state, *new_plane_state;\n \tstruct drm_crtc_commit *commit;\n+\tconst struct drm_mode_config_helper_funcs *funcs;\n \tint i, ret;\n \n+\tfuncs = state->dev->mode_config.helper_private;\n+\n \tfor_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {\n \t\tcommit = kzalloc(sizeof(*commit), GFP_KERNEL);\n \t\tif (!commit)\n@@ -2160,6 +2166,9 @@ int drm_atomic_helper_setup_commit(struc\n \t\tnew_plane_state->commit = drm_crtc_commit_get(commit);\n \t}\n \n+\tif (funcs && funcs->atomic_commit_setup)\n+\t\treturn funcs->atomic_commit_setup(state);\n+\n \treturn 0;\n }\n EXPORT_SYMBOL(drm_atomic_helper_setup_commit);\n--- a/include/drm/drm_modeset_helper_vtables.h\n+++ b/include/drm/drm_modeset_helper_vtables.h\n@@ -1396,6 +1396,27 @@ struct drm_mode_config_helper_funcs {\n \t * drm_atomic_helper_commit_tail().\n \t */\n \tvoid (*atomic_commit_tail)(struct drm_atomic_state *state);\n+\n+\t/**\n+\t * @atomic_commit_setup:\n+\t *\n+\t * This hook is used by the default atomic_commit() hook implemented in\n+\t * drm_atomic_helper_commit() together with the nonblocking helpers (see\n+\t * drm_atomic_helper_setup_commit()) to extend the DRM commit setup. It\n+\t * is not used by the atomic helpers.\n+\t *\n+\t * This function is called at the end of\n+\t * drm_atomic_helper_setup_commit(), so once the commit has been\n+\t * properly setup across the generic DRM object states. It allows\n+\t * drivers to do some additional commit tracking that isn't related to a\n+\t * CRTC, plane or connector, tracked in a &drm_private_obj structure.\n+\t *\n+\t * Note that the documentation of &drm_private_obj has more details on\n+\t * how one should implement this.\n+\t *\n+\t * This hook is optional.\n+\t */\n+\tint (*atomic_commit_setup)(struct drm_atomic_state *state);\n };\n \n #endif\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0682-drm-Document-use-after-free-gotcha-with-private-obje.patch",
    "content": "From c417eda92ac1a1a89c160826eb2068fbdf1895ab Mon Sep 17 00:00:00 2001\nFrom: Maxime Ripard <maxime@cerno.tech>\nDate: Fri, 4 Dec 2020 16:11:33 +0100\nSubject: [PATCH] drm: Document use-after-free gotcha with private\n objects\n\nThe private objects have a gotcha that could result in a use-after-free,\nmake sure it's properly documented.\n\nReviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>\nSigned-off-by: Maxime Ripard <maxime@cerno.tech>\n---\n include/drm/drm_atomic.h | 20 ++++++++++++++++++++\n 1 file changed, 20 insertions(+)\n\n--- a/include/drm/drm_atomic.h\n+++ b/include/drm/drm_atomic.h\n@@ -248,6 +248,26 @@ struct drm_private_state_funcs {\n  *    drm_dev_register()\n  * 2/ all calls to drm_atomic_private_obj_fini() must be done after calling\n  *    drm_dev_unregister()\n+ *\n+ * If that private object is used to store a state shared by multiple\n+ * CRTCs, proper care must be taken to ensure that non-blocking commits are\n+ * properly ordered to avoid a use-after-free issue.\n+ *\n+ * Indeed, assuming a sequence of two non-blocking &drm_atomic_commit on two\n+ * different &drm_crtc using different &drm_plane and &drm_connector, so with no\n+ * resources shared, there's no guarantee on which commit is going to happen\n+ * first. However, the second &drm_atomic_commit will consider the first\n+ * &drm_private_obj its old state, and will be in charge of freeing it whenever\n+ * the second &drm_atomic_commit is done.\n+ *\n+ * If the first &drm_atomic_commit happens after it, it will consider its\n+ * &drm_private_obj the new state and will be likely to access it, resulting in\n+ * an access to a freed memory region. Drivers should store (and get a reference\n+ * to) the &drm_crtc_commit structure in our private state in\n+ * &drm_mode_config_helper_funcs.atomic_commit_setup, and then wait for that\n+ * commit to complete as the first step of\n+ * &drm_mode_config_helper_funcs.atomic_commit_tail, similar to\n+ * drm_atomic_helper_wait_for_dependencies().\n  */\n struct drm_private_obj {\n \t/**\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0683-drm-vc4-Simplify-a-bit-the-global-atomic_check.patch",
    "content": "From d88f88dfdce0c6911802cb9a0da0c43ade854183 Mon Sep 17 00:00:00 2001\nFrom: Maxime Ripard <maxime@cerno.tech>\nDate: Fri, 4 Dec 2020 16:11:34 +0100\nSubject: [PATCH] drm/vc4: Simplify a bit the global atomic_check\n\nWhen we can't allocate a new channel, we can simply return instead of\nhaving to handle both cases, and that simplifies a bit the code.\n\nReviewed-by: Thomas Zimmermann <tzimmermann@suse.de>\nSigned-off-by: Maxime Ripard <maxime@cerno.tech>\n---\n drivers/gpu/drm/vc4/vc4_kms.c | 13 ++++++-------\n 1 file changed, 6 insertions(+), 7 deletions(-)\n\n--- a/drivers/gpu/drm/vc4/vc4_kms.c\n+++ b/drivers/gpu/drm/vc4/vc4_kms.c\n@@ -793,6 +793,7 @@ static int vc4_pv_muxing_atomic_check(st\n \t\t\tto_vc4_crtc_state(new_crtc_state);\n \t\tstruct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);\n \t\tunsigned int matching_channels;\n+\t\tunsigned int channel;\n \n \t\tif (vc4->firmware_kms)\n \t\t\tcontinue;\n@@ -836,14 +837,12 @@ static int vc4_pv_muxing_atomic_check(st\n \t\t * but it works so far.\n \t\t */\n \t\tmatching_channels = hvs_new_state->unassigned_channels & vc4_crtc->data->hvs_available_channels;\n-\t\tif (matching_channels) {\n-\t\t\tunsigned int channel = ffs(matching_channels) - 1;\n-\n-\t\t\tnew_vc4_crtc_state->assigned_channel = channel;\n-\t\t\thvs_new_state->unassigned_channels &= ~BIT(channel);\n-\t\t} else {\n+\t\tif (!matching_channels)\n \t\t\treturn -EINVAL;\n-\t\t}\n+\n+\t\tchannel = ffs(matching_channels) - 1;\n+\t\tnew_vc4_crtc_state->assigned_channel = channel;\n+\t\thvs_new_state->unassigned_channels &= ~BIT(channel);\n \t}\n \n \treturn 0;\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0684-drm-vc4-hdmi-Don-t-poll-for-the-infoframes-status-on.patch",
    "content": "From 643f9b3a9e48fb2378d3dde8cfef452f7628e295 Mon Sep 17 00:00:00 2001\nFrom: Maxime Ripard <maxime@cerno.tech>\nDate: Thu, 3 Dec 2020 08:46:24 +0100\nSubject: [PATCH] drm/vc4: hdmi: Don't poll for the infoframes status\n on setup\n\nThe infoframes are sent at a regular interval as a data island packet,\nso we don't need to wait for them to be sent when we're setting them up.\n\nHowever, we do need to poll when we're enabling since the we can't\nupdate the packet RAM until it has been sent.\n\nLet's add a boolean flag to tell whether we want to poll or not to\nsupport both cases.\n\nSuggested-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\nSigned-off-by: Maxime Ripard <maxime@cerno.tech>\nReviewed-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\nLink: https://patchwork.freedesktop.org/patch/msgid/20201203074624.721559-1-maxime@cerno.tech\n---\n drivers/gpu/drm/vc4/vc4_hdmi.c | 10 +++++++---\n 1 file changed, 7 insertions(+), 3 deletions(-)\n\n--- a/drivers/gpu/drm/vc4/vc4_hdmi.c\n+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c\n@@ -364,7 +364,8 @@ static int vc4_hdmi_connector_init(struc\n }\n \n static int vc4_hdmi_stop_packet(struct drm_encoder *encoder,\n-\t\t\t\tenum hdmi_infoframe_type type)\n+\t\t\t\tenum hdmi_infoframe_type type,\n+\t\t\t\tbool poll)\n {\n \tstruct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);\n \tu32 packet_id = type - 0x80;\n@@ -372,6 +373,9 @@ static int vc4_hdmi_stop_packet(struct d\n \tHDMI_WRITE(HDMI_RAM_PACKET_CONFIG,\n \t\t   HDMI_READ(HDMI_RAM_PACKET_CONFIG) & ~BIT(packet_id));\n \n+\tif (!poll)\n+\t\treturn 0;\n+\n \treturn wait_for(!(HDMI_READ(HDMI_RAM_PACKET_STATUS) &\n \t\t\t  BIT(packet_id)), 100);\n }\n@@ -400,7 +404,7 @@ static void vc4_hdmi_write_infoframe(str\n \tif (len < 0)\n \t\treturn;\n \n-\tret = vc4_hdmi_stop_packet(encoder, frame->any.type);\n+\tret = vc4_hdmi_stop_packet(encoder, frame->any.type, true);\n \tif (ret) {\n \t\tDRM_ERROR(\"Failed to wait for infoframe to go idle: %d\\n\", ret);\n \t\treturn;\n@@ -1284,7 +1288,7 @@ static void vc4_hdmi_audio_reset(struct\n \tint ret;\n \n \tvc4_hdmi->audio.streaming = false;\n-\tret = vc4_hdmi_stop_packet(encoder, HDMI_INFOFRAME_TYPE_AUDIO);\n+\tret = vc4_hdmi_stop_packet(encoder, HDMI_INFOFRAME_TYPE_AUDIO, false);\n \tif (ret)\n \t\tdev_err(dev, \"Failed to stop audio infoframe: %d\\n\", ret);\n \n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0685-drm-vc4-hvs-Align-the-HVS-atomic-hooks-to-the-new-AP.patch",
    "content": "From c53200aa7d0670aa21639512880669b94699aaee Mon Sep 17 00:00:00 2001\nFrom: Maxime Ripard <maxime@cerno.tech>\nDate: Tue, 15 Dec 2020 16:42:35 +0100\nSubject: [PATCH] drm/vc4: hvs: Align the HVS atomic hooks to the new\n API\n\nSince the CRTC setup in vc4 is split between the PixelValves/TXP and the\nHVS, only the PV/TXP atomic hooks were updated in the previous commits, but\nit makes sense to update the HVS ones too.\n\nReviewed-by: Thomas Zimmermann <tzimmermann@suse.de>\nSigned-off-by: Maxime Ripard <maxime@cerno.tech>\nLink: https://patchwork.freedesktop.org/patch/msgid/20201215154243.540115-2-maxime@cerno.tech\n---\n drivers/gpu/drm/vc4/vc4_crtc.c |  2 +-\n drivers/gpu/drm/vc4/vc4_drv.h  |  5 ++---\n drivers/gpu/drm/vc4/vc4_hvs.c  | 10 +++++-----\n drivers/gpu/drm/vc4/vc4_txp.c  |  2 +-\n 4 files changed, 9 insertions(+), 10 deletions(-)\n\n--- a/drivers/gpu/drm/vc4/vc4_crtc.c\n+++ b/drivers/gpu/drm/vc4/vc4_crtc.c\n@@ -646,7 +646,7 @@ static int vc4_crtc_atomic_check(struct\n \tstruct drm_connector_state *conn_state;\n \tint ret, i;\n \n-\tret = vc4_hvs_atomic_check(crtc, crtc_state);\n+\tret = vc4_hvs_atomic_check(crtc, state);\n \tif (ret)\n \t\treturn ret;\n \n--- a/drivers/gpu/drm/vc4/vc4_drv.h\n+++ b/drivers/gpu/drm/vc4/vc4_drv.h\n@@ -924,11 +924,10 @@ void vc4_irq_reset(struct drm_device *de\n extern struct platform_driver vc4_hvs_driver;\n void vc4_hvs_stop_channel(struct drm_device *dev, unsigned int output);\n int vc4_hvs_get_fifo_from_output(struct drm_device *dev, unsigned int output);\n-int vc4_hvs_atomic_check(struct drm_crtc *crtc, struct drm_crtc_state *state);\n+int vc4_hvs_atomic_check(struct drm_crtc *crtc, struct drm_atomic_state *state);\n void vc4_hvs_atomic_enable(struct drm_crtc *crtc, struct drm_atomic_state *state);\n void vc4_hvs_atomic_disable(struct drm_crtc *crtc, struct drm_atomic_state *state);\n-void vc4_hvs_atomic_flush(struct drm_crtc *crtc,\n-\t\t\t  struct drm_atomic_state *state);\n+void vc4_hvs_atomic_flush(struct drm_crtc *crtc, struct drm_atomic_state *state);\n void vc4_hvs_dump_state(struct drm_device *dev);\n void vc4_hvs_unmask_underrun(struct drm_device *dev, int channel);\n void vc4_hvs_mask_underrun(struct drm_device *dev, int channel);\n--- a/drivers/gpu/drm/vc4/vc4_hvs.c\n+++ b/drivers/gpu/drm/vc4/vc4_hvs.c\n@@ -365,10 +365,10 @@ void vc4_hvs_stop_channel(struct drm_dev\n \t\t     SCALER_DISPSTATX_EMPTY);\n }\n \n-int vc4_hvs_atomic_check(struct drm_crtc *crtc,\n-\t\t\t struct drm_crtc_state *state)\n+int vc4_hvs_atomic_check(struct drm_crtc *crtc, struct drm_atomic_state *state)\n {\n-\tstruct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);\n+\tstruct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc);\n+\tstruct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc_state);\n \tstruct drm_device *dev = crtc->dev;\n \tstruct vc4_dev *vc4 = to_vc4_dev(dev);\n \tstruct drm_plane *plane;\n@@ -380,10 +380,10 @@ int vc4_hvs_atomic_check(struct drm_crtc\n \t/* The pixelvalve can only feed one encoder (and encoders are\n \t * 1:1 with connectors.)\n \t */\n-\tif (hweight32(state->connector_mask) > 1)\n+\tif (hweight32(crtc_state->connector_mask) > 1)\n \t\treturn -EINVAL;\n \n-\tdrm_atomic_crtc_state_for_each_plane_state(plane, plane_state, state)\n+\tdrm_atomic_crtc_state_for_each_plane_state(plane, plane_state, crtc_state)\n \t\tdlist_count += vc4_plane_dlist_size(plane_state);\n \n \tdlist_count++; /* Account for SCALER_CTL0_END. */\n--- a/drivers/gpu/drm/vc4/vc4_txp.c\n+++ b/drivers/gpu/drm/vc4/vc4_txp.c\n@@ -393,7 +393,7 @@ static int vc4_txp_atomic_check(struct d\n \tstruct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc_state);\n \tint ret;\n \n-\tret = vc4_hvs_atomic_check(crtc, crtc_state);\n+\tret = vc4_hvs_atomic_check(crtc, state);\n \tif (ret)\n \t\treturn ret;\n \n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0686-drm-Use-the-state-pointer-directly-in-atomic_check.patch",
    "content": "From 1a941929a4163a147764711f6bfe2ad9f3614abb Mon Sep 17 00:00:00 2001\nFrom: Maxime Ripard <maxime@cerno.tech>\nDate: Mon, 2 Nov 2020 14:38:34 +0100\nSubject: [PATCH] drm: Use the state pointer directly in atomic_check\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nNow that atomic_check takes the global atomic state as a parameter, we\ndon't need to go through the pointer in the CRTC state.\n\nThis was done using the following coccinelle script:\n\n@ crtc_atomic_func @\nidentifier helpers;\nidentifier func;\n@@\n\nstatic struct drm_crtc_helper_funcs helpers = {\n\t...,\n\t.atomic_check = func,\n\t...,\n};\n\n@@\nidentifier crtc_atomic_func.func;\nidentifier crtc, state;\n@@\n\n  func(struct drm_crtc *crtc, struct drm_atomic_state *state) {\n  ...\n- struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc);\n  ... when != crtc_state\n- crtc_state->state\n+ state\n  ...\n }\n\n@@\nstruct drm_crtc_state *crtc_state;\nidentifier crtc_atomic_func.func;\nidentifier crtc, state;\n@@\n\n  func(struct drm_crtc *crtc, struct drm_atomic_state *state) {\n  ...\n- crtc_state->state\n+ state\n  ...\n }\n\nSuggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>\nSigned-off-by: Maxime Ripard <maxime@cerno.tech>\nReviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>\nLink: https://patchwork.freedesktop.org/patch/msgid/20201102133834.1176740-3-maxime@cerno.tech\n---\n drivers/gpu/drm/drm_simple_kms_helper.c | 2 +-\n drivers/gpu/drm/mxsfb/mxsfb_kms.c       | 2 +-\n drivers/gpu/drm/omapdrm/omap_crtc.c     | 2 +-\n drivers/gpu/drm/tilcdc/tilcdc_crtc.c    | 6 +++---\n drivers/gpu/drm/vc4/vc4_crtc.c          | 2 +-\n drivers/gpu/drm/xlnx/zynqmp_disp.c      | 4 +---\n 6 files changed, 8 insertions(+), 10 deletions(-)\n\n--- a/drivers/gpu/drm/drm_simple_kms_helper.c\n+++ b/drivers/gpu/drm/drm_simple_kms_helper.c\n@@ -97,7 +97,7 @@ static int drm_simple_kms_crtc_check(str\n \tif (has_primary != crtc_state->enable)\n \t\treturn -EINVAL;\n \n-\treturn drm_atomic_add_affected_planes(crtc_state->state, crtc);\n+\treturn drm_atomic_add_affected_planes(state, crtc);\n }\n \n static void drm_simple_kms_crtc_enable(struct drm_crtc *crtc,\n--- a/drivers/gpu/drm/mxsfb/mxsfb_kms.c\n+++ b/drivers/gpu/drm/mxsfb/mxsfb_kms.c\n@@ -322,7 +322,7 @@ static int mxsfb_crtc_atomic_check(struc\n \t\treturn -EINVAL;\n \n \t/* TODO: Is this needed ? */\n-\treturn drm_atomic_add_affected_planes(crtc_state->state, crtc);\n+\treturn drm_atomic_add_affected_planes(state, crtc);\n }\n \n static void mxsfb_crtc_atomic_flush(struct drm_crtc *crtc,\n--- a/drivers/gpu/drm/omapdrm/omap_crtc.c\n+++ b/drivers/gpu/drm/omapdrm/omap_crtc.c\n@@ -583,7 +583,7 @@ static int omap_crtc_atomic_check(struct\n \t\t\treturn -EINVAL;\n \t}\n \n-\tpri_state = drm_atomic_get_new_plane_state(crtc_state->state,\n+\tpri_state = drm_atomic_get_new_plane_state(state,\n \t\t\t\t\t\t   crtc->primary);\n \tif (pri_state) {\n \t\tstruct omap_crtc_state *omap_crtc_state =\n--- a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c\n+++ b/drivers/gpu/drm/tilcdc/tilcdc_crtc.c\n@@ -677,9 +677,9 @@ static int tilcdc_crtc_atomic_check(stru\n \tif (!crtc_state->active)\n \t\treturn 0;\n \n-\tif (crtc_state->state->planes[0].ptr != crtc->primary ||\n-\t    crtc_state->state->planes[0].state == NULL ||\n-\t    crtc_state->state->planes[0].state->crtc != crtc) {\n+\tif (state->planes[0].ptr != crtc->primary ||\n+\t    state->planes[0].state == NULL ||\n+\t    state->planes[0].state->crtc != crtc) {\n \t\tdev_dbg(crtc->dev->dev, \"CRTC primary plane must be present\");\n \t\treturn -EINVAL;\n \t}\n--- a/drivers/gpu/drm/vc4/vc4_crtc.c\n+++ b/drivers/gpu/drm/vc4/vc4_crtc.c\n@@ -650,7 +650,7 @@ static int vc4_crtc_atomic_check(struct\n \tif (ret)\n \t\treturn ret;\n \n-\tfor_each_new_connector_in_state(crtc_state->state, conn, conn_state,\n+\tfor_each_new_connector_in_state(state, conn, conn_state,\n \t\t\t\t\ti) {\n \t\tif (conn_state->crtc != crtc)\n \t\t\tcontinue;\n--- a/drivers/gpu/drm/xlnx/zynqmp_disp.c\n+++ b/drivers/gpu/drm/xlnx/zynqmp_disp.c\n@@ -1508,9 +1508,7 @@ zynqmp_disp_crtc_atomic_disable(struct d\n static int zynqmp_disp_crtc_atomic_check(struct drm_crtc *crtc,\n \t\t\t\t\t struct drm_atomic_state *state)\n {\n-\tstruct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,\n-\t\t\t\t\t\t\t\t\t  crtc);\n-\treturn drm_atomic_add_affected_planes(crtc_state->state, crtc);\n+\treturn drm_atomic_add_affected_planes(state, crtc);\n }\n \n static void\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0687-drm-vc4-Remove-unnecessary-drm_plane_cleanup-wrapper.patch",
    "content": "From c7b252e6121b8c72d0e0540478658485eaeebe86 Mon Sep 17 00:00:00 2001\nFrom: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>\nDate: Wed, 17 Jan 2018 23:15:18 +0200\nSubject: [PATCH] drm: vc4: Remove unnecessary drm_plane_cleanup()\n wrapper\n\nUse the drm_plane_cleanup() function directly as the drm_plane_funcs\n.destroy() handler without creating an unnecessary wrapper around it.\n\nSigned-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>\nAcked-by: Maxime Ripard <mripard@kernel.org>\nAcked-by: Daniel Vetter <daniel.vetter@ffwll.ch>\n---\n drivers/gpu/drm/vc4/vc4_plane.c | 7 +------\n 1 file changed, 1 insertion(+), 6 deletions(-)\n\n--- a/drivers/gpu/drm/vc4/vc4_plane.c\n+++ b/drivers/gpu/drm/vc4/vc4_plane.c\n@@ -1363,11 +1363,6 @@ static const struct drm_plane_helper_fun\n \t.atomic_async_update = vc4_plane_atomic_async_update,\n };\n \n-static void vc4_plane_destroy(struct drm_plane *plane)\n-{\n-\tdrm_plane_cleanup(plane);\n-}\n-\n static bool vc4_format_mod_supported(struct drm_plane *plane,\n \t\t\t\t     uint32_t format,\n \t\t\t\t     uint64_t modifier)\n@@ -1425,7 +1420,7 @@ static bool vc4_format_mod_supported(str\n static const struct drm_plane_funcs vc4_plane_funcs = {\n \t.update_plane = drm_atomic_helper_update_plane,\n \t.disable_plane = drm_atomic_helper_disable_plane,\n-\t.destroy = vc4_plane_destroy,\n+\t.destroy = drm_plane_cleanup,\n \t.set_property = NULL,\n \t.reset = vc4_plane_reset,\n \t.atomic_duplicate_state = vc4_plane_duplicate_state,\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0688-drm-vc4-plane-Remove-redundant-assignment.patch",
    "content": "From 9d766c97656ba1a8729e434ca6cd9b1e1172ee1f Mon Sep 17 00:00:00 2001\nFrom: Maxime Ripard <maxime@cerno.tech>\nDate: Thu, 18 Mar 2021 17:13:27 +0100\nSubject: [PATCH] drm/vc4: plane: Remove redundant assignment\n\nThe vc4_plane_atomic_async_update function assigns twice in a row the\nsrc_h field in the drm_plane_state structure to the same value. Remove\nthe second one.\n\nReviewed-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\nSigned-off-by: Maxime Ripard <maxime@cerno.tech>\nLink: https://patchwork.freedesktop.org/patch/msgid/20210318161328.1471556-2-maxime@cerno.tech\n---\n drivers/gpu/drm/vc4/vc4_plane.c | 1 -\n 1 file changed, 1 deletion(-)\n\n--- a/drivers/gpu/drm/vc4/vc4_plane.c\n+++ b/drivers/gpu/drm/vc4/vc4_plane.c\n@@ -1226,7 +1226,6 @@ static void vc4_plane_atomic_async_updat\n \tplane->state->src_y = state->src_y;\n \tplane->state->src_w = state->src_w;\n \tplane->state->src_h = state->src_h;\n-\tplane->state->src_h = state->src_h;\n \tplane->state->alpha = state->alpha;\n \tplane->state->pixel_blend_mode = state->pixel_blend_mode;\n \tplane->state->rotation = state->rotation;\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0689-drm-automatic-legacy-gamma-support.patch",
    "content": "From 88dea782ac45343b039ee1b6ee15b55e63a5f835 Mon Sep 17 00:00:00 2001\nFrom: Tomi Valkeinen <tomi.valkeinen@ti.com>\nDate: Fri, 11 Dec 2020 13:42:36 +0200\nSubject: [PATCH] drm: automatic legacy gamma support\n\nTo support legacy gamma ioctls the drivers need to set\ndrm_crtc_funcs.gamma_set either to a custom implementation or to\ndrm_atomic_helper_legacy_gamma_set. Most of the atomic drivers do the\nlatter.\n\nWe can simplify this by making the core handle it automatically.\n\nMove the drm_atomic_helper_legacy_gamma_set() functionality into\ndrm_color_mgmt.c to make drm_mode_gamma_set_ioctl() use\ndrm_crtc_funcs.gamma_set if set or GAMMA_LUT property if not.\n\nSigned-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>\nReviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>\nReviewed-by: Philippe Cornu <philippe.cornu@st.com>\nLink: https://patchwork.freedesktop.org/patch/msgid/20201211114237.213288-2-tomi.valkeinen@ti.com\n---\n .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |   1 -\n .../gpu/drm/arm/display/komeda/komeda_crtc.c  |   1 -\n drivers/gpu/drm/arm/malidp_crtc.c             |   1 -\n drivers/gpu/drm/armada/armada_crtc.c          |   1 -\n drivers/gpu/drm/ast/ast_mode.c                |   1 -\n .../gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c    |   1 -\n drivers/gpu/drm/drm_atomic_helper.c           |  70 -----------\n drivers/gpu/drm/drm_color_mgmt.c              | 111 ++++++++++++++++--\n drivers/gpu/drm/i915/display/intel_display.c  |   1 -\n drivers/gpu/drm/ingenic/ingenic-drm-drv.c     |   2 -\n drivers/gpu/drm/mediatek/mtk_drm_crtc.c       |   1 -\n drivers/gpu/drm/nouveau/dispnv50/head.c       |   2 -\n drivers/gpu/drm/omapdrm/omap_crtc.c           |   1 -\n drivers/gpu/drm/rcar-du/rcar_du_crtc.c        |   1 -\n drivers/gpu/drm/rockchip/rockchip_drm_vop.c   |   1 -\n drivers/gpu/drm/stm/ltdc.c                    |   1 -\n drivers/gpu/drm/vc4/vc4_crtc.c                |   1 -\n drivers/gpu/drm/vc4/vc4_txp.c                 |   1 -\n include/drm/drm_atomic_helper.h               |   4 -\n 19 files changed, 102 insertions(+), 101 deletions(-)\n\n--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c\n+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c\n@@ -4993,7 +4993,6 @@ static void dm_disable_vblank(struct drm\n static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = {\n \t.reset = dm_crtc_reset_state,\n \t.destroy = amdgpu_dm_crtc_destroy,\n-\t.gamma_set = drm_atomic_helper_legacy_gamma_set,\n \t.set_config = drm_atomic_helper_set_config,\n \t.page_flip = drm_atomic_helper_page_flip,\n \t.atomic_duplicate_state = dm_crtc_duplicate_state,\n--- a/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c\n+++ b/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c\n@@ -548,7 +548,6 @@ static void komeda_crtc_vblank_disable(s\n }\n \n static const struct drm_crtc_funcs komeda_crtc_funcs = {\n-\t.gamma_set\t\t= drm_atomic_helper_legacy_gamma_set,\n \t.destroy\t\t= drm_crtc_cleanup,\n \t.set_config\t\t= drm_atomic_helper_set_config,\n \t.page_flip\t\t= drm_atomic_helper_page_flip,\n--- a/drivers/gpu/drm/arm/malidp_crtc.c\n+++ b/drivers/gpu/drm/arm/malidp_crtc.c\n@@ -510,7 +510,6 @@ static void malidp_crtc_disable_vblank(s\n }\n \n static const struct drm_crtc_funcs malidp_crtc_funcs = {\n-\t.gamma_set = drm_atomic_helper_legacy_gamma_set,\n \t.destroy = drm_crtc_cleanup,\n \t.set_config = drm_atomic_helper_set_config,\n \t.page_flip = drm_atomic_helper_page_flip,\n--- a/drivers/gpu/drm/armada/armada_crtc.c\n+++ b/drivers/gpu/drm/armada/armada_crtc.c\n@@ -816,7 +816,6 @@ static const struct drm_crtc_funcs armad\n \t.cursor_set\t= armada_drm_crtc_cursor_set,\n \t.cursor_move\t= armada_drm_crtc_cursor_move,\n \t.destroy\t= armada_drm_crtc_destroy,\n-\t.gamma_set\t= drm_atomic_helper_legacy_gamma_set,\n \t.set_config\t= drm_atomic_helper_set_config,\n \t.page_flip\t= drm_atomic_helper_page_flip,\n \t.atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,\n--- a/drivers/gpu/drm/ast/ast_mode.c\n+++ b/drivers/gpu/drm/ast/ast_mode.c\n@@ -901,7 +901,6 @@ static void ast_crtc_atomic_destroy_stat\n \n static const struct drm_crtc_funcs ast_crtc_funcs = {\n \t.reset = ast_crtc_reset,\n-\t.gamma_set = drm_atomic_helper_legacy_gamma_set,\n \t.destroy = drm_crtc_cleanup,\n \t.set_config = drm_atomic_helper_set_config,\n \t.page_flip = drm_atomic_helper_page_flip,\n--- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c\n+++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c\n@@ -473,7 +473,6 @@ static const struct drm_crtc_funcs atmel\n \t.atomic_destroy_state = atmel_hlcdc_crtc_destroy_state,\n \t.enable_vblank = atmel_hlcdc_crtc_enable_vblank,\n \t.disable_vblank = atmel_hlcdc_crtc_disable_vblank,\n-\t.gamma_set = drm_atomic_helper_legacy_gamma_set,\n };\n \n int atmel_hlcdc_crtc_create(struct drm_device *dev)\n--- a/drivers/gpu/drm/drm_atomic_helper.c\n+++ b/drivers/gpu/drm/drm_atomic_helper.c\n@@ -3500,76 +3500,6 @@ fail:\n EXPORT_SYMBOL(drm_atomic_helper_page_flip_target);\n \n /**\n- * drm_atomic_helper_legacy_gamma_set - set the legacy gamma correction table\n- * @crtc: CRTC object\n- * @red: red correction table\n- * @green: green correction table\n- * @blue: green correction table\n- * @size: size of the tables\n- * @ctx: lock acquire context\n- *\n- * Implements support for legacy gamma correction table for drivers\n- * that support color management through the DEGAMMA_LUT/GAMMA_LUT\n- * properties. See drm_crtc_enable_color_mgmt() and the containing chapter for\n- * how the atomic color management and gamma tables work.\n- */\n-int drm_atomic_helper_legacy_gamma_set(struct drm_crtc *crtc,\n-\t\t\t\t       u16 *red, u16 *green, u16 *blue,\n-\t\t\t\t       uint32_t size,\n-\t\t\t\t       struct drm_modeset_acquire_ctx *ctx)\n-{\n-\tstruct drm_device *dev = crtc->dev;\n-\tstruct drm_atomic_state *state;\n-\tstruct drm_crtc_state *crtc_state;\n-\tstruct drm_property_blob *blob = NULL;\n-\tstruct drm_color_lut *blob_data;\n-\tint i, ret = 0;\n-\tbool replaced;\n-\n-\tstate = drm_atomic_state_alloc(crtc->dev);\n-\tif (!state)\n-\t\treturn -ENOMEM;\n-\n-\tblob = drm_property_create_blob(dev,\n-\t\t\t\t\tsizeof(struct drm_color_lut) * size,\n-\t\t\t\t\tNULL);\n-\tif (IS_ERR(blob)) {\n-\t\tret = PTR_ERR(blob);\n-\t\tblob = NULL;\n-\t\tgoto fail;\n-\t}\n-\n-\t/* Prepare GAMMA_LUT with the legacy values. */\n-\tblob_data = blob->data;\n-\tfor (i = 0; i < size; i++) {\n-\t\tblob_data[i].red = red[i];\n-\t\tblob_data[i].green = green[i];\n-\t\tblob_data[i].blue = blue[i];\n-\t}\n-\n-\tstate->acquire_ctx = ctx;\n-\tcrtc_state = drm_atomic_get_crtc_state(state, crtc);\n-\tif (IS_ERR(crtc_state)) {\n-\t\tret = PTR_ERR(crtc_state);\n-\t\tgoto fail;\n-\t}\n-\n-\t/* Reset DEGAMMA_LUT and CTM properties. */\n-\treplaced  = drm_property_replace_blob(&crtc_state->degamma_lut, NULL);\n-\treplaced |= drm_property_replace_blob(&crtc_state->ctm, NULL);\n-\treplaced |= drm_property_replace_blob(&crtc_state->gamma_lut, blob);\n-\tcrtc_state->color_mgmt_changed |= replaced;\n-\n-\tret = drm_atomic_commit(state);\n-\n-fail:\n-\tdrm_atomic_state_put(state);\n-\tdrm_property_blob_put(blob);\n-\treturn ret;\n-}\n-EXPORT_SYMBOL(drm_atomic_helper_legacy_gamma_set);\n-\n-/**\n  * drm_atomic_helper_bridge_propagate_bus_fmt() - Propagate output format to\n  *\t\t\t\t\t\t  the input end of a bridge\n  * @bridge: bridge control structure\n--- a/drivers/gpu/drm/drm_color_mgmt.c\n+++ b/drivers/gpu/drm/drm_color_mgmt.c\n@@ -22,6 +22,7 @@\n \n #include <linux/uaccess.h>\n \n+#include <drm/drm_atomic.h>\n #include <drm/drm_color_mgmt.h>\n #include <drm/drm_crtc.h>\n #include <drm/drm_device.h>\n@@ -89,9 +90,8 @@\n  *\tmodes) appropriately.\n  *\n  * There is also support for a legacy gamma table, which is set up by calling\n- * drm_mode_crtc_set_gamma_size(). Drivers which support both should use\n- * drm_atomic_helper_legacy_gamma_set() to alias the legacy gamma ramp with the\n- * \"GAMMA_LUT\" property above.\n+ * drm_mode_crtc_set_gamma_size(). The DRM core will then alias the legacy gamma\n+ * ramp with \"GAMMA_LUT\".\n  *\n  * Support for different non RGB color encodings is controlled through\n  * &drm_plane specific COLOR_ENCODING and COLOR_RANGE properties. They\n@@ -156,9 +156,6 @@ EXPORT_SYMBOL(drm_color_ctm_s31_32_to_qm\n  * optional. The gamma and degamma properties are only attached if\n  * their size is not 0 and ctm_property is only attached if has_ctm is\n  * true.\n- *\n- * Drivers should use drm_atomic_helper_legacy_gamma_set() to implement the\n- * legacy &drm_crtc_funcs.gamma_set callback.\n  */\n void drm_crtc_enable_color_mgmt(struct drm_crtc *crtc,\n \t\t\t\tuint degamma_lut_size,\n@@ -232,6 +229,102 @@ int drm_mode_crtc_set_gamma_size(struct\n EXPORT_SYMBOL(drm_mode_crtc_set_gamma_size);\n \n /**\n+ * drm_crtc_supports_legacy_gamma - does the crtc support legacy gamma correction table\n+ * @crtc: CRTC object\n+ *\n+ * Returns true/false if the given crtc supports setting the legacy gamma\n+ * correction table.\n+ */\n+static bool drm_crtc_supports_legacy_gamma(struct drm_crtc *crtc)\n+{\n+\tu32 gamma_id = crtc->dev->mode_config.gamma_lut_property->base.id;\n+\n+\tif (!crtc->gamma_size)\n+\t\treturn false;\n+\n+\tif (crtc->funcs->gamma_set)\n+\t\treturn true;\n+\n+\treturn !!drm_mode_obj_find_prop_id(&crtc->base, gamma_id);\n+}\n+\n+/**\n+ * drm_crtc_legacy_gamma_set - set the legacy gamma correction table\n+ * @crtc: CRTC object\n+ * @red: red correction table\n+ * @green: green correction table\n+ * @blue: green correction table\n+ * @size: size of the tables\n+ * @ctx: lock acquire context\n+ *\n+ * Implements support for legacy gamma correction table for drivers\n+ * that have set drm_crtc_funcs.gamma_set or that support color management\n+ * through the DEGAMMA_LUT/GAMMA_LUT properties. See\n+ * drm_crtc_enable_color_mgmt() and the containing chapter for\n+ * how the atomic color management and gamma tables work.\n+ *\n+ * This function sets the gamma using drm_crtc_funcs.gamma_set if set, or\n+ * alternatively using crtc color management properties.\n+ */\n+static int drm_crtc_legacy_gamma_set(struct drm_crtc *crtc,\n+\t\t\t\t     u16 *red, u16 *green, u16 *blue,\n+\t\t\t\t     u32 size,\n+\t\t\t\t     struct drm_modeset_acquire_ctx *ctx)\n+{\n+\tstruct drm_device *dev = crtc->dev;\n+\tstruct drm_atomic_state *state;\n+\tstruct drm_crtc_state *crtc_state;\n+\tstruct drm_property_blob *blob;\n+\tstruct drm_color_lut *blob_data;\n+\tint i, ret = 0;\n+\tbool replaced;\n+\n+\tif (crtc->funcs->gamma_set)\n+\t\treturn crtc->funcs->gamma_set(crtc, red, green, blue, size, ctx);\n+\n+\tstate = drm_atomic_state_alloc(crtc->dev);\n+\tif (!state)\n+\t\treturn -ENOMEM;\n+\n+\tblob = drm_property_create_blob(dev,\n+\t\t\t\t\tsizeof(struct drm_color_lut) * size,\n+\t\t\t\t\tNULL);\n+\tif (IS_ERR(blob)) {\n+\t\tret = PTR_ERR(blob);\n+\t\tblob = NULL;\n+\t\tgoto fail;\n+\t}\n+\n+\t/* Prepare GAMMA_LUT with the legacy values. */\n+\tblob_data = blob->data;\n+\tfor (i = 0; i < size; i++) {\n+\t\tblob_data[i].red = red[i];\n+\t\tblob_data[i].green = green[i];\n+\t\tblob_data[i].blue = blue[i];\n+\t}\n+\n+\tstate->acquire_ctx = ctx;\n+\tcrtc_state = drm_atomic_get_crtc_state(state, crtc);\n+\tif (IS_ERR(crtc_state)) {\n+\t\tret = PTR_ERR(crtc_state);\n+\t\tgoto fail;\n+\t}\n+\n+\t/* Set GAMMA_LUT and reset DEGAMMA_LUT and CTM */\n+\treplaced = drm_property_replace_blob(&crtc_state->degamma_lut, NULL);\n+\treplaced |= drm_property_replace_blob(&crtc_state->ctm, NULL);\n+\treplaced |= drm_property_replace_blob(&crtc_state->gamma_lut, blob);\n+\tcrtc_state->color_mgmt_changed |= replaced;\n+\n+\tret = drm_atomic_commit(state);\n+\n+fail:\n+\tdrm_atomic_state_put(state);\n+\tdrm_property_blob_put(blob);\n+\treturn ret;\n+}\n+\n+/**\n  * drm_mode_gamma_set_ioctl - set the gamma table\n  * @dev: DRM device\n  * @data: ioctl data\n@@ -262,7 +355,7 @@ int drm_mode_gamma_set_ioctl(struct drm_\n \tif (!crtc)\n \t\treturn -ENOENT;\n \n-\tif (crtc->funcs->gamma_set == NULL)\n+\tif (!drm_crtc_supports_legacy_gamma(crtc))\n \t\treturn -ENOSYS;\n \n \t/* memcpy into gamma store */\n@@ -290,8 +383,8 @@ int drm_mode_gamma_set_ioctl(struct drm_\n \t\tgoto out;\n \t}\n \n-\tret = crtc->funcs->gamma_set(crtc, r_base, g_base, b_base,\n-\t\t\t\t     crtc->gamma_size, &ctx);\n+\tret = drm_crtc_legacy_gamma_set(crtc, r_base, g_base, b_base,\n+\t\t\t\t\tcrtc->gamma_size, &ctx);\n \n out:\n \tDRM_MODESET_LOCK_ALL_END(dev, ctx, ret);\n--- a/drivers/gpu/drm/i915/display/intel_display.c\n+++ b/drivers/gpu/drm/i915/display/intel_display.c\n@@ -16562,7 +16562,6 @@ fail:\n }\n \n #define INTEL_CRTC_FUNCS \\\n-\t.gamma_set = drm_atomic_helper_legacy_gamma_set, \\\n \t.set_config = drm_atomic_helper_set_config, \\\n \t.destroy = intel_crtc_destroy, \\\n \t.page_flip = drm_atomic_helper_page_flip, \\\n--- a/drivers/gpu/drm/ingenic/ingenic-drm-drv.c\n+++ b/drivers/gpu/drm/ingenic/ingenic-drm-drv.c\n@@ -647,8 +647,6 @@ static const struct drm_crtc_funcs ingen\n \n \t.enable_vblank\t\t= ingenic_drm_enable_vblank,\n \t.disable_vblank\t\t= ingenic_drm_disable_vblank,\n-\n-\t.gamma_set\t\t= drm_atomic_helper_legacy_gamma_set,\n };\n \n static const struct drm_plane_helper_funcs ingenic_drm_plane_helper_funcs = {\n--- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c\n+++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c\n@@ -614,7 +614,6 @@ static const struct drm_crtc_funcs mtk_c\n \t.reset\t\t\t= mtk_drm_crtc_reset,\n \t.atomic_duplicate_state\t= mtk_drm_crtc_duplicate_state,\n \t.atomic_destroy_state\t= mtk_drm_crtc_destroy_state,\n-\t.gamma_set\t\t= drm_atomic_helper_legacy_gamma_set,\n \t.enable_vblank\t\t= mtk_drm_crtc_enable_vblank,\n \t.disable_vblank\t\t= mtk_drm_crtc_disable_vblank,\n };\n--- a/drivers/gpu/drm/nouveau/dispnv50/head.c\n+++ b/drivers/gpu/drm/nouveau/dispnv50/head.c\n@@ -506,7 +506,6 @@ nv50_head_destroy(struct drm_crtc *crtc)\n static const struct drm_crtc_funcs\n nv50_head_func = {\n \t.reset = nv50_head_reset,\n-\t.gamma_set = drm_atomic_helper_legacy_gamma_set,\n \t.destroy = nv50_head_destroy,\n \t.set_config = drm_atomic_helper_set_config,\n \t.page_flip = drm_atomic_helper_page_flip,\n@@ -521,7 +520,6 @@ nv50_head_func = {\n static const struct drm_crtc_funcs\n nvd9_head_func = {\n \t.reset = nv50_head_reset,\n-\t.gamma_set = drm_atomic_helper_legacy_gamma_set,\n \t.destroy = nv50_head_destroy,\n \t.set_config = drm_atomic_helper_set_config,\n \t.page_flip = drm_atomic_helper_page_flip,\n--- a/drivers/gpu/drm/omapdrm/omap_crtc.c\n+++ b/drivers/gpu/drm/omapdrm/omap_crtc.c\n@@ -741,7 +741,6 @@ static const struct drm_crtc_funcs omap_\n \t.set_config = drm_atomic_helper_set_config,\n \t.destroy = omap_crtc_destroy,\n \t.page_flip = drm_atomic_helper_page_flip,\n-\t.gamma_set = drm_atomic_helper_legacy_gamma_set,\n \t.atomic_duplicate_state = omap_crtc_duplicate_state,\n \t.atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,\n \t.atomic_set_property = omap_crtc_atomic_set_property,\n--- a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c\n+++ b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c\n@@ -1150,7 +1150,6 @@ static const struct drm_crtc_funcs crtc_\n \t.set_crc_source = rcar_du_crtc_set_crc_source,\n \t.verify_crc_source = rcar_du_crtc_verify_crc_source,\n \t.get_crc_sources = rcar_du_crtc_get_crc_sources,\n-\t.gamma_set = drm_atomic_helper_legacy_gamma_set,\n };\n \n /* -----------------------------------------------------------------------------\n--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c\n+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c\n@@ -1642,7 +1642,6 @@ static const struct drm_crtc_funcs vop_c\n \t.disable_vblank = vop_crtc_disable_vblank,\n \t.set_crc_source = vop_crtc_set_crc_source,\n \t.verify_crc_source = vop_crtc_verify_crc_source,\n-\t.gamma_set = drm_atomic_helper_legacy_gamma_set,\n };\n \n static void vop_fb_unref_worker(struct drm_flip_work *work, void *val)\n--- a/drivers/gpu/drm/stm/ltdc.c\n+++ b/drivers/gpu/drm/stm/ltdc.c\n@@ -742,7 +742,6 @@ static const struct drm_crtc_funcs ltdc_\n \t.enable_vblank = ltdc_crtc_enable_vblank,\n \t.disable_vblank = ltdc_crtc_disable_vblank,\n \t.get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,\n-\t.gamma_set = drm_atomic_helper_legacy_gamma_set,\n };\n \n /*\n--- a/drivers/gpu/drm/vc4/vc4_crtc.c\n+++ b/drivers/gpu/drm/vc4/vc4_crtc.c\n@@ -937,7 +937,6 @@ static const struct drm_crtc_funcs vc4_c\n \t.reset = vc4_crtc_reset,\n \t.atomic_duplicate_state = vc4_crtc_duplicate_state,\n \t.atomic_destroy_state = vc4_crtc_destroy_state,\n-\t.gamma_set = drm_atomic_helper_legacy_gamma_set,\n \t.enable_vblank = vc4_enable_vblank,\n \t.disable_vblank = vc4_disable_vblank,\n \t.get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,\n--- a/drivers/gpu/drm/vc4/vc4_txp.c\n+++ b/drivers/gpu/drm/vc4/vc4_txp.c\n@@ -380,7 +380,6 @@ static const struct drm_crtc_funcs vc4_t\n \t.reset\t\t\t= vc4_crtc_reset,\n \t.atomic_duplicate_state\t= vc4_crtc_duplicate_state,\n \t.atomic_destroy_state\t= vc4_crtc_destroy_state,\n-\t.gamma_set\t\t= drm_atomic_helper_legacy_gamma_set,\n \t.enable_vblank\t\t= vc4_txp_enable_vblank,\n \t.disable_vblank\t\t= vc4_txp_disable_vblank,\n };\n--- a/include/drm/drm_atomic_helper.h\n+++ b/include/drm/drm_atomic_helper.h\n@@ -147,10 +147,6 @@ int drm_atomic_helper_page_flip_target(\n \t\t\t\tuint32_t flags,\n \t\t\t\tuint32_t target,\n \t\t\t\tstruct drm_modeset_acquire_ctx *ctx);\n-int drm_atomic_helper_legacy_gamma_set(struct drm_crtc *crtc,\n-\t\t\t\t       u16 *red, u16 *green, u16 *blue,\n-\t\t\t\t       uint32_t size,\n-\t\t\t\t       struct drm_modeset_acquire_ctx *ctx);\n \n /**\n  * drm_atomic_crtc_for_each_plane - iterate over planes currently attached to CRTC\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0690-drm-Pass-the-full-state-to-connectors-atomic-functio.patch",
    "content": "From 05d10aebe62239b014098c8e517dd96848f9a495 Mon Sep 17 00:00:00 2001\nFrom: Maxime Ripard <maxime@cerno.tech>\nDate: Wed, 18 Nov 2020 10:47:58 +0100\nSubject: [PATCH] drm: Pass the full state to connectors atomic\n functions\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nThe current atomic helpers have either their object state being passed as\nan argument or the full atomic state.\n\nThe former is the pattern that was done at first, before switching to the\nlatter for new hooks or when it was needed.\n\nNow that the CRTCs have been converted, let's move forward with the\nconnectors to provide a consistent interface.\n\nThe conversion was done using the coccinelle script below, and built tested\non all the drivers.\n\n@@\nidentifier connector, connector_state;\n@@\n\n struct drm_connector_helper_funcs {\n\t...\n\tstruct drm_encoder* (*atomic_best_encoder)(struct drm_connector *connector,\n-\t\t\t\t\t\t   struct drm_connector_state *connector_state);\n+\t\t\t\t\t\t   struct drm_atomic_state *state);\n\t...\n}\n\n@@\nidentifier connector, connector_state;\n@@\n\n struct drm_connector_helper_funcs {\n\t...\n\tvoid (*atomic_commit)(struct drm_connector *connector,\n-\t\t\t      struct drm_connector_state *connector_state);\n+\t\t\t      struct drm_atomic_state *state);\n\t...\n}\n\n@@\nstruct drm_connector_helper_funcs *FUNCS;\nidentifier state;\nidentifier connector, connector_state;\nidentifier f;\n@@\n\n f(..., struct drm_atomic_state *state, ...)\n {\n\t<+...\n-\tFUNCS->atomic_commit(connector, connector_state);\n+\tFUNCS->atomic_commit(connector, state);\n\t...+>\n }\n\n@@\nstruct drm_connector_helper_funcs *FUNCS;\nidentifier state;\nidentifier connector, connector_state;\nidentifier var, f;\n@@\n\n f(struct drm_atomic_state *state, ...)\n {\n\t<+...\n-\tvar = FUNCS->atomic_best_encoder(connector, connector_state);\n+\tvar = FUNCS->atomic_best_encoder(connector, state);\n\t...+>\n }\n\n@ connector_atomic_func @\nidentifier helpers;\nidentifier func;\n@@\n\n(\nstatic struct drm_connector_helper_funcs helpers = {\n\t...,\n\t.atomic_best_encoder = func,\n\t...,\n};\n|\nstatic struct drm_connector_helper_funcs helpers = {\n\t...,\n\t.atomic_commit = func,\n\t...,\n};\n)\n\n@@\nidentifier connector_atomic_func.func;\nidentifier connector;\nsymbol state;\n@@\n\n func(struct drm_connector *connector,\n-      struct drm_connector_state *state\n+      struct drm_connector_state *connector_state\n      )\n {\n\t...\n-\tstate\n+\tconnector_state\n \t...\n }\n\n@ ignores_state @\nidentifier connector_atomic_func.func;\nidentifier connector, connector_state;\n@@\n\n func(struct drm_connector *connector,\n      struct drm_connector_state *connector_state)\n{\n\t... when != connector_state\n}\n\n@ adds_state depends on connector_atomic_func && !ignores_state @\nidentifier connector_atomic_func.func;\nidentifier connector, connector_state;\n@@\n\n func(struct drm_connector *connector, struct drm_connector_state *connector_state)\n {\n+\tstruct drm_connector_state *connector_state = drm_atomic_get_new_connector_state(state, connector);\n\t...\n }\n\n@ depends on connector_atomic_func @\nidentifier connector_atomic_func.func;\nidentifier connector_state;\nidentifier connector;\n@@\n\n func(struct drm_connector *connector,\n-     struct drm_connector_state *connector_state\n+     struct drm_atomic_state *state\n\t   )\n { ... }\n\n@ include depends on adds_state @\n@@\n\n #include <drm/drm_atomic.h>\n\n@ no_include depends on !include && adds_state @\n@@\n\n+ #include <drm/drm_atomic.h>\n  #include <drm/...>\n\nSigned-off-by: Maxime Ripard <maxime@cerno.tech>\nReviewed-by: Rodrigo Siqueira <rodrigosiqueiramelo@gmail.com>\nReviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>\nAcked-by: Thomas Zimmermann <tzimmermann@suse.de>\nAcked-by: Harry Wentland <harry.wentland@amd.com>\nCc: Leo Li <sunpeng.li@amd.com>\nCc: Alex Deucher <alexander.deucher@amd.com>\nCc: \"Christian König\" <christian.koenig@amd.com>\nCc: Jani Nikula <jani.nikula@linux.intel.com>\nCc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>\nCc: Rodrigo Vivi <rodrigo.vivi@intel.com>\nCc: Ben Skeggs <bskeggs@redhat.com>\nCc: Rodrigo Siqueira <rodrigosiqueiramelo@gmail.com>\nCc: Melissa Wen <melissa.srw@gmail.com>\nCc: Haneen Mohammed <hamohammed.sa@gmail.com>\nLink: https://patchwork.freedesktop.org/patch/msgid/20201118094758.506730-1-maxime@cerno.tech\n---\n .../drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c |  5 ++++-\n drivers/gpu/drm/drm_atomic_helper.c                 |  8 ++++----\n drivers/gpu/drm/i915/display/intel_dp_mst.c         |  7 +++++--\n drivers/gpu/drm/nouveau/dispnv50/disp.c             |  5 ++++-\n drivers/gpu/drm/vc4/vc4_txp.c                       |  4 +++-\n drivers/gpu/drm/vkms/vkms_writeback.c               |  8 ++++++--\n include/drm/drm_modeset_helper_vtables.h            | 13 ++++++-------\n 7 files changed, 32 insertions(+), 18 deletions(-)\n\n--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c\n+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c\n@@ -24,6 +24,7 @@\n  */\n \n #include <linux/version.h>\n+#include <drm/drm_atomic.h>\n #include <drm/drm_atomic_helper.h>\n #include <drm/drm_dp_mst_helper.h>\n #include <drm/drm_dp_helper.h>\n@@ -264,8 +265,10 @@ static int dm_dp_mst_get_modes(struct dr\n \n static struct drm_encoder *\n dm_mst_atomic_best_encoder(struct drm_connector *connector,\n-\t\t\t   struct drm_connector_state *connector_state)\n+\t\t\t   struct drm_atomic_state *state)\n {\n+\tstruct drm_connector_state *connector_state = drm_atomic_get_new_connector_state(state,\n+\t\t\t\t\t\t\t\t\t\t\t connector);\n \tstruct drm_device *dev = connector->dev;\n \tstruct amdgpu_device *adev = drm_to_adev(dev);\n \tstruct amdgpu_crtc *acrtc = to_amdgpu_crtc(connector_state->crtc);\n--- a/drivers/gpu/drm/drm_atomic_helper.c\n+++ b/drivers/gpu/drm/drm_atomic_helper.c\n@@ -122,7 +122,8 @@ static int handle_conflicting_encoders(s\n \t\t\tcontinue;\n \n \t\tif (funcs->atomic_best_encoder)\n-\t\t\tnew_encoder = funcs->atomic_best_encoder(connector, new_conn_state);\n+\t\t\tnew_encoder = funcs->atomic_best_encoder(connector,\n+\t\t\t\t\t\t\t\t state);\n \t\telse if (funcs->best_encoder)\n \t\t\tnew_encoder = funcs->best_encoder(connector);\n \t\telse\n@@ -345,8 +346,7 @@ update_connector_routing(struct drm_atom\n \tfuncs = connector->helper_private;\n \n \tif (funcs->atomic_best_encoder)\n-\t\tnew_encoder = funcs->atomic_best_encoder(connector,\n-\t\t\t\t\t\t\t new_connector_state);\n+\t\tnew_encoder = funcs->atomic_best_encoder(connector, state);\n \telse if (funcs->best_encoder)\n \t\tnew_encoder = funcs->best_encoder(connector);\n \telse\n@@ -1318,7 +1318,7 @@ static void drm_atomic_helper_commit_wri\n \n \t\tif (new_conn_state->writeback_job && new_conn_state->writeback_job->fb) {\n \t\t\tWARN_ON(connector->connector_type != DRM_MODE_CONNECTOR_WRITEBACK);\n-\t\t\tfuncs->atomic_commit(connector, new_conn_state);\n+\t\t\tfuncs->atomic_commit(connector, old_state);\n \t\t}\n \t}\n }\n--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c\n+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c\n@@ -23,6 +23,7 @@\n  *\n  */\n \n+#include <drm/drm_atomic.h>\n #include <drm/drm_atomic_helper.h>\n #include <drm/drm_edid.h>\n #include <drm/drm_probe_helper.h>\n@@ -708,11 +709,13 @@ intel_dp_mst_mode_valid_ctx(struct drm_c\n }\n \n static struct drm_encoder *intel_mst_atomic_best_encoder(struct drm_connector *connector,\n-\t\t\t\t\t\t\t struct drm_connector_state *state)\n+\t\t\t\t\t\t\t struct drm_atomic_state *state)\n {\n+\tstruct drm_connector_state *connector_state = drm_atomic_get_new_connector_state(state,\n+\t\t\t\t\t\t\t\t\t\t\t connector);\n \tstruct intel_connector *intel_connector = to_intel_connector(connector);\n \tstruct intel_dp *intel_dp = intel_connector->mst_port;\n-\tstruct intel_crtc *crtc = to_intel_crtc(state->crtc);\n+\tstruct intel_crtc *crtc = to_intel_crtc(connector_state->crtc);\n \n \treturn &intel_dp->mst_encoders[crtc->pipe]->base.base;\n }\n--- a/drivers/gpu/drm/nouveau/dispnv50/disp.c\n+++ b/drivers/gpu/drm/nouveau/dispnv50/disp.c\n@@ -32,6 +32,7 @@\n #include <linux/hdmi.h>\n #include <linux/component.h>\n \n+#include <drm/drm_atomic.h>\n #include <drm/drm_atomic_helper.h>\n #include <drm/drm_dp_helper.h>\n #include <drm/drm_edid.h>\n@@ -1161,8 +1162,10 @@ nv50_msto_new(struct drm_device *dev, st\n \n static struct drm_encoder *\n nv50_mstc_atomic_best_encoder(struct drm_connector *connector,\n-\t\t\t      struct drm_connector_state *connector_state)\n+\t\t\t      struct drm_atomic_state *state)\n {\n+\tstruct drm_connector_state *connector_state = drm_atomic_get_new_connector_state(state,\n+\t\t\t\t\t\t\t\t\t\t\t connector);\n \tstruct nv50_mstc *mstc = nv50_mstc(connector);\n \tstruct drm_crtc *crtc = connector_state->crtc;\n \n--- a/drivers/gpu/drm/vc4/vc4_txp.c\n+++ b/drivers/gpu/drm/vc4/vc4_txp.c\n@@ -273,8 +273,10 @@ static int vc4_txp_connector_atomic_chec\n }\n \n static void vc4_txp_connector_atomic_commit(struct drm_connector *conn,\n-\t\t\t\t\tstruct drm_connector_state *conn_state)\n+\t\t\t\t\tstruct drm_atomic_state *state)\n {\n+\tstruct drm_connector_state *conn_state = drm_atomic_get_new_connector_state(state,\n+\t\t\t\t\t\t\t\t\t\t    conn);\n \tstruct vc4_txp *txp = connector_to_vc4_txp(conn);\n \tstruct drm_gem_cma_object *gem;\n \tstruct drm_display_mode *mode;\n--- a/drivers/gpu/drm/vkms/vkms_writeback.c\n+++ b/drivers/gpu/drm/vkms/vkms_writeback.c\n@@ -1,6 +1,8 @@\n // SPDX-License-Identifier: GPL-2.0+\n \n #include \"vkms_drv.h\"\n+\n+#include <drm/drm_atomic.h>\n #include <drm/drm_fourcc.h>\n #include <drm/drm_writeback.h>\n #include <drm/drm_probe_helper.h>\n@@ -100,8 +102,10 @@ static void vkms_wb_cleanup_job(struct d\n }\n \n static void vkms_wb_atomic_commit(struct drm_connector *conn,\n-\t\t\t\t  struct drm_connector_state *state)\n+\t\t\t\t  struct drm_atomic_state *state)\n {\n+\tstruct drm_connector_state *connector_state = drm_atomic_get_new_connector_state(state,\n+\t\t\t\t\t\t\t\t\t\t\t conn);\n \tstruct vkms_device *vkmsdev = drm_device_to_vkms_device(conn->dev);\n \tstruct vkms_output *output = &vkmsdev->output;\n \tstruct drm_writeback_connector *wb_conn = &output->wb_connector;\n@@ -117,7 +121,7 @@ static void vkms_wb_atomic_commit(struct\n \tcrtc_state->active_writeback = conn_state->writeback_job->priv;\n \tcrtc_state->wb_pending = true;\n \tspin_unlock_irq(&output->composer_lock);\n-\tdrm_writeback_queue_job(wb_conn, state);\n+\tdrm_writeback_queue_job(wb_conn, connector_state);\n }\n \n static const struct drm_connector_helper_funcs vkms_wb_conn_helper_funcs = {\n--- a/include/drm/drm_modeset_helper_vtables.h\n+++ b/include/drm/drm_modeset_helper_vtables.h\n@@ -1044,9 +1044,8 @@ struct drm_connector_helper_funcs {\n \t * NOTE:\n \t *\n \t * This function is called in the check phase of an atomic update. The\n-\t * driver is not allowed to change anything outside of the free-standing\n-\t * state objects passed-in or assembled in the overall &drm_atomic_state\n-\t * update tracking structure.\n+\t * driver is not allowed to change anything outside of the\n+\t * &drm_atomic_state update tracking structure passed in.\n \t *\n \t * RETURNS:\n \t *\n@@ -1056,7 +1055,7 @@ struct drm_connector_helper_funcs {\n \t * for this.\n \t */\n \tstruct drm_encoder *(*atomic_best_encoder)(struct drm_connector *connector,\n-\t\t\t\t\t\t   struct drm_connector_state *connector_state);\n+\t\t\t\t\t\t   struct drm_atomic_state *state);\n \n \t/**\n \t * @atomic_check:\n@@ -1097,15 +1096,15 @@ struct drm_connector_helper_funcs {\n \t *\n \t * This hook is to be used by drivers implementing writeback connectors\n \t * that need a point when to commit the writeback job to the hardware.\n-\t * The writeback_job to commit is available in\n-\t * &drm_connector_state.writeback_job.\n+\t * The writeback_job to commit is available in the new connector state,\n+\t * in &drm_connector_state.writeback_job.\n \t *\n \t * This hook is optional.\n \t *\n \t * This callback is used by the atomic modeset helpers.\n \t */\n \tvoid (*atomic_commit)(struct drm_connector *connector,\n-\t\t\t      struct drm_connector_state *state);\n+\t\t\t      struct drm_atomic_state *state);\n \n \t/**\n \t * @prepare_writeback_job:\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0691-drm-vc4-replace-idr_init-by-idr_init_base.patch",
    "content": "From b19ef92e9e95765bab9b952aa781363fe2917254 Mon Sep 17 00:00:00 2001\nFrom: Deepak R Varma <mh12gx2825@gmail.com>\nDate: Fri, 6 Nov 2020 01:51:35 +0530\nSubject: [PATCH] drm/vc4: replace idr_init() by idr_init_base()\n\nidr_init() uses base 0 which is an invalid identifier for this driver.\nThe idr_alloc for this driver uses VC4_PERFMONID_MIN as start value for\nID range and it is #defined to 1. The new function idr_init_base allows\nIDR to set the ID lookup from base 1. This avoids all lookups that\notherwise starts from 0 since 0 is always unused / available.\n\nReferences: commit 6ce711f27500 (\"idr: Make 1-based IDRs more efficient\")\n\nSigned-off-by: Deepak R Varma <mh12gx2825@gmail.com>\nReviewed-by: Eric Anholt <eric@anholt.net>\nSigned-off-by: Maxime Ripard <maxime@cerno.tech>\nLink: https://patchwork.freedesktop.org/patch/msgid/20201105202135.GA145111@localhost\n---\n drivers/gpu/drm/vc4/vc4_perfmon.c | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/drivers/gpu/drm/vc4/vc4_perfmon.c\n+++ b/drivers/gpu/drm/vc4/vc4_perfmon.c\n@@ -77,7 +77,7 @@ struct vc4_perfmon *vc4_perfmon_find(str\n void vc4_perfmon_open_file(struct vc4_file *vc4file)\n {\n \tmutex_init(&vc4file->perfmon.lock);\n-\tidr_init(&vc4file->perfmon.idr);\n+\tidr_init_base(&vc4file->perfmon.idr, VC4_PERFMONID_MIN);\n }\n \n static int vc4_perfmon_idr_del(int id, void *elem, void *data)\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0692-drm-vc4-vc4_hdmi_regs-Mark-some-data-sets-as-__maybe.patch",
    "content": "From f0f694e4624f63ea58b2bf3d1774cc86917f39c7 Mon Sep 17 00:00:00 2001\nFrom: Lee Jones <lee.jones@linaro.org>\nDate: Mon, 16 Nov 2020 17:41:07 +0000\nSubject: [PATCH] drm/vc4/vc4_hdmi_regs: Mark some data sets as\n __maybe_unused\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nThe alternative is to move them into the source file that uses then,\nbut they are large and intrusive, so that strategy is being avoided.\n\nFixes the following W=1 kernel build warning(s):\n\n drivers/gpu/drm/vc4/vc4_hdmi_regs.h:282:39: warning: ‘vc5_hdmi_hdmi1_fields’ defined but not used [-Wunused-const-variable=]\n drivers/gpu/drm/vc4/vc4_hdmi_regs.h:206:39: warning: ‘vc5_hdmi_hdmi0_fields’ defined but not used [-Wunused-const-variable=]\n drivers/gpu/drm/vc4/vc4_hdmi_regs.h:145:39: warning: ‘vc4_hdmi_fields’ defined but not used [-Wunused-const-variable=]\n\nCc: Eric Anholt <eric@anholt.net>\nCc: Maxime Ripard <mripard@kernel.org>\nCc: David Airlie <airlied@linux.ie>\nCc: Daniel Vetter <daniel@ffwll.ch>\nCc: dri-devel@lists.freedesktop.org\nSigned-off-by: Lee Jones <lee.jones@linaro.org>\nSigned-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>\nLink: https://patchwork.freedesktop.org/patch/msgid/20201116174112.1833368-38-lee.jones@linaro.org\n---\n drivers/gpu/drm/vc4/vc4_hdmi_regs.h | 6 +++---\n 1 file changed, 3 insertions(+), 3 deletions(-)\n\n--- a/drivers/gpu/drm/vc4/vc4_hdmi_regs.h\n+++ b/drivers/gpu/drm/vc4/vc4_hdmi_regs.h\n@@ -149,7 +149,7 @@ struct vc4_hdmi_register {\n #define VC5_RAM_REG(reg, offset)\t_VC4_REG(VC5_RAM, reg, offset)\n #define VC5_RM_REG(reg, offset)\t\t_VC4_REG(VC5_RM, reg, offset)\n \n-static const struct vc4_hdmi_register vc4_hdmi_fields[] = {\n+static const struct vc4_hdmi_register __maybe_unused vc4_hdmi_fields[] = {\n \tVC4_HD_REG(HDMI_M_CTL, 0x000c),\n \tVC4_HD_REG(HDMI_MAI_CTL, 0x0014),\n \tVC4_HD_REG(HDMI_MAI_THR, 0x0018),\n@@ -211,7 +211,7 @@ static const struct vc4_hdmi_register vc\n \tVC4_HDMI_REG(HDMI_RAM_PACKET_START, 0x0400),\n };\n \n-static const struct vc4_hdmi_register vc5_hdmi_hdmi0_fields[] = {\n+static const struct vc4_hdmi_register __maybe_unused vc5_hdmi_hdmi0_fields[] = {\n \tVC4_HD_REG(HDMI_DVP_CTL, 0x0000),\n \tVC4_HD_REG(HDMI_MAI_CTL, 0x0010),\n \tVC4_HD_REG(HDMI_MAI_THR, 0x0014),\n@@ -291,7 +291,7 @@ static const struct vc4_hdmi_register vc\n \tVC5_CSC_REG(HDMI_CSC_34_33, 0x018),\n };\n \n-static const struct vc4_hdmi_register vc5_hdmi_hdmi1_fields[] = {\n+static const struct vc4_hdmi_register __maybe_unused vc5_hdmi_hdmi1_fields[] = {\n \tVC4_HD_REG(HDMI_DVP_CTL, 0x0000),\n \tVC4_HD_REG(HDMI_MAI_CTL, 0x0030),\n \tVC4_HD_REG(HDMI_MAI_THR, 0x0034),\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0693-drm-vc4-remove-unneeded-variable-ret.patch",
    "content": "From c0cfa3ce26baee0eb323481244e5a7f7a88db207 Mon Sep 17 00:00:00 2001\nFrom: Bernard Zhao <bernard@vivo.com>\nDate: Tue, 2 Feb 2021 04:23:38 -0800\nSubject: [PATCH] drm/vc4: remove unneeded variable: \"ret\"\n\nremove unneeded variable: \"ret\".\n\nSigned-off-by: Bernard Zhao <bernard@vivo.com>\nSigned-off-by: Maxime Ripard <maxime@cerno.tech>\nLink: https://patchwork.freedesktop.org/patch/msgid/20210202122338.15351-1-bernard@vivo.com\n(cherry picked from commit f0c5a89e534b43bfef8e7bf7baa5624cd84e1e18)\nSigned-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>\n---\n drivers/gpu/drm/vc4/vc4_gem.c | 3 +--\n 1 file changed, 1 insertion(+), 2 deletions(-)\n\n--- a/drivers/gpu/drm/vc4/vc4_gem.c\n+++ b/drivers/gpu/drm/vc4/vc4_gem.c\n@@ -1026,7 +1026,6 @@ int vc4_queue_seqno_cb(struct drm_device\n \t\t       void (*func)(struct vc4_seqno_cb *cb))\n {\n \tstruct vc4_dev *vc4 = to_vc4_dev(dev);\n-\tint ret = 0;\n \tunsigned long irqflags;\n \n \tcb->func = func;\n@@ -1041,7 +1040,7 @@ int vc4_queue_seqno_cb(struct drm_device\n \t}\n \tspin_unlock_irqrestore(&vc4->job_lock, irqflags);\n \n-\treturn ret;\n+\treturn 0;\n }\n \n /* Scheduled when any job has been completed, this walks the list of\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0694-overlays-Add-overlay-for-cap1106-capacitive-touch-se.patch",
    "content": "From 62ae8907efb221f232126726bf4df5c9da23a8b4 Mon Sep 17 00:00:00 2001\nFrom: Jesse Taube <Mr.Bossman075@gmail.com>\nDate: Thu, 8 Jul 2021 16:32:16 -0400\nSubject: [PATCH] overlays: Add overlay for cap1106 capacitive touch\n sensor\n\nSigned-off-by: Jesse Taube  <mr.bossman075@gmail.com>\n---\n arch/arm/boot/dts/overlays/Makefile           |  1 +\n arch/arm/boot/dts/overlays/README             |  6 +++\n .../arm/boot/dts/overlays/cap1106-overlay.dts | 52 +++++++++++++++++++\n 3 files changed, 59 insertions(+)\n create mode 100644 arch/arm/boot/dts/overlays/cap1106-overlay.dts\n\n--- a/arch/arm/boot/dts/overlays/Makefile\n+++ b/arch/arm/boot/dts/overlays/Makefile\n@@ -30,6 +30,7 @@ dtbo-$(CONFIG_ARCH_BCM2835) += \\\n \taudiosense-pi.dtbo \\\n \taudremap.dtbo \\\n \tbalena-fin.dtbo \\\n+\tcap1106.dtbo \\\n \tchipdip-i2s-master-dac.dtbo \\\n \tcma.dtbo \\\n \tdht11.dtbo \\\n--- a/arch/arm/boot/dts/overlays/README\n+++ b/arch/arm/boot/dts/overlays/README\n@@ -622,6 +622,12 @@ Info:   This overlay is now deprecated -\n Load:   <Deprecated>\n \n \n+Name:   cap1106\n+Info:   Enables the ability to use the cap1106 touch sensor as a keyboard\n+Load:   dtoverlay=cap1106,<param>=<val>\n+Params: int_pin                 GPIO pin for interrupt signal (default 23)\n+\n+\n Name:   chipdip-i2s-master-dac\n Info:   Configures Raspberry PI to work as I2S slave with BCLK=64Fs.\n Load:   dtoverlay=chipdip-i2s-master-dac\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/cap1106-overlay.dts\n@@ -0,0 +1,52 @@\n+// Overlay for cap1106 from  Microchip Semiconductor\n+// add CONFIG_KEYBOARD_CAP11XX=y\n+\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+        compatible = \"brcm,bcm2835\";\n+        fragment@0 {\n+                target = <&i2c1>;\n+                __overlay__{\n+                        status = \"okay\";\n+                        cap1106: cap1106@28 {\n+                                compatible = \"microchip,cap1106\";\n+                                pinctrl-0 = <&cap1106_pins>;\n+                                pinctrl-names = \"default\";\n+                                interrupt-parent = <&gpio>;\n+                                interrupts = <4 2>;\n+                                reg = <0x28>;\n+                                autorepeat;\n+                                microchip,sensor-gain = <2>;\n+\n+                                linux,keycodes = <2>,           /* KEY_1 */\n+                                                <3>,            /* KEY_2 */\n+                                                <4>,            /* KEY_3 */\n+                                                <5>,            /* KEY_4 */\n+                                                <6>,            /* KEY_5 */\n+                                                <7>;            /* KEY_6 */\n+\n+                                #address-cells = <1>;\n+                                #size-cells = <0>;\n+                                status = \"okay\";\n+\n+                        };\n+                };\n+        };\n+        fragment@1 {\n+                target = <&gpio>;\n+                __overlay__ {\n+                        cap1106_pins: cap1106_pins {\n+                                brcm,pins = <4>;\n+                                brcm,function = <0>; /* in */\n+                                brcm,pull = <0>; /* none */\n+                        };\n+                };\n+        };\n+\n+        __overrides__ {\n+                int_pin = <&cap1106>, \"interrupts:0\",\n+                          <&cap1106_pins>, \"brcm,pins:0\";\n+        };\n+};\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0695-drm-vc4-Fix-margin-calculations-for-the-right-bottom.patch",
    "content": "From 0427e8464446a03d287e7ec8b7bb74dd983b6988 Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Mon, 12 Jul 2021 12:27:59 +0100\nSubject: [PATCH] drm/vc4: Fix margin calculations for the right/bottom\n edges\n\nThe calculations clipped the right/bottom edge of the clipped\nrange based on the left/top margins.\n\nFixes: 666e73587f90 (\"drm/vc4: Take margin setup into account when updating planes\")\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n drivers/gpu/drm/vc4/vc4_plane.c | 8 ++++----\n 1 file changed, 4 insertions(+), 4 deletions(-)\n\n--- a/drivers/gpu/drm/vc4/vc4_plane.c\n+++ b/drivers/gpu/drm/vc4/vc4_plane.c\n@@ -310,16 +310,16 @@ static int vc4_plane_margins_adj(struct\n \t\t\t\t\t       adjhdisplay,\n \t\t\t\t\t       crtc_state->mode.hdisplay);\n \tvc4_pstate->crtc_x += left;\n-\tif (vc4_pstate->crtc_x > crtc_state->mode.hdisplay - left)\n-\t\tvc4_pstate->crtc_x = crtc_state->mode.hdisplay - left;\n+\tif (vc4_pstate->crtc_x > crtc_state->mode.hdisplay - right)\n+\t\tvc4_pstate->crtc_x = crtc_state->mode.hdisplay - right;\n \n \tadjvdisplay = crtc_state->mode.vdisplay - (top + bottom);\n \tvc4_pstate->crtc_y = DIV_ROUND_CLOSEST(vc4_pstate->crtc_y *\n \t\t\t\t\t       adjvdisplay,\n \t\t\t\t\t       crtc_state->mode.vdisplay);\n \tvc4_pstate->crtc_y += top;\n-\tif (vc4_pstate->crtc_y > crtc_state->mode.vdisplay - top)\n-\t\tvc4_pstate->crtc_y = crtc_state->mode.vdisplay - top;\n+\tif (vc4_pstate->crtc_y > crtc_state->mode.vdisplay - bottom)\n+\t\tvc4_pstate->crtc_y = crtc_state->mode.vdisplay - bottom;\n \n \tvc4_pstate->crtc_w = DIV_ROUND_CLOSEST(vc4_pstate->crtc_w *\n \t\t\t\t\t       adjhdisplay,\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0696-ydrm-vc4-fkms-Fix-margin-calculations-for-the-right-.patch",
    "content": "From e0aaa1acd1f33cc60e2b5c43cf6aac63bf3bbbc9 Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Mon, 12 Jul 2021 13:06:07 +0100\nSubject: [PATCH] ydrm/vc4: fkms: Fix margin calculations for the\n right/bottom edges\n\nThe calculations clipped the right/bottom edge of the clipped\nrange based on the left/top margins.\n\nhttps://github.com/raspberrypi/linux/issues/4447\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n drivers/gpu/drm/vc4/vc4_firmware_kms.c | 8 ++++----\n 1 file changed, 4 insertions(+), 4 deletions(-)\n\n--- a/drivers/gpu/drm/vc4/vc4_firmware_kms.c\n+++ b/drivers/gpu/drm/vc4/vc4_firmware_kms.c\n@@ -458,15 +458,15 @@ static int vc4_fkms_margins_adj(struct d\n \tplane->dst_x = DIV_ROUND_CLOSEST(plane->dst_x * adjhdisplay,\n \t\t\t\t\t (int)crtc_state->mode.hdisplay);\n \tplane->dst_x += left;\n-\tif (plane->dst_x > (int)(crtc_state->mode.hdisplay - left))\n-\t\tplane->dst_x = crtc_state->mode.hdisplay - left;\n+\tif (plane->dst_x > (int)(crtc_state->mode.hdisplay - right))\n+\t\tplane->dst_x = crtc_state->mode.hdisplay - right;\n \n \tadjvdisplay = crtc_state->mode.vdisplay - (top + bottom);\n \tplane->dst_y = DIV_ROUND_CLOSEST(plane->dst_y * adjvdisplay,\n \t\t\t\t\t (int)crtc_state->mode.vdisplay);\n \tplane->dst_y += top;\n-\tif (plane->dst_y > (int)(crtc_state->mode.vdisplay - top))\n-\t\tplane->dst_y = crtc_state->mode.vdisplay - top;\n+\tif (plane->dst_y > (int)(crtc_state->mode.vdisplay - bottom))\n+\t\tplane->dst_y = crtc_state->mode.vdisplay - bottom;\n \n \tplane->dst_w = DIV_ROUND_CLOSEST(plane->dst_w * adjhdisplay,\n \t\t\t\t\t crtc_state->mode.hdisplay);\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0697-ARM-dts-bcm2711-fold-in-the-correct-interrupt.patch",
    "content": "From b18f7a3c76cc764e58e9aabc3150a994e1d3f40b Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.com>\nDate: Mon, 12 Jul 2021 15:15:44 +0100\nSubject: [PATCH] ARM: dts: bcm2711: fold in the correct interrupt\n\nThe new vec node in bcm2711.dtsi should have the correct interrupt\nnumber to start with, rather than include the bcm283x version and\npatch it later.\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.com>\n---\n arch/arm/boot/dts/bcm2711.dtsi | 6 +-----\n 1 file changed, 1 insertion(+), 5 deletions(-)\n\n--- a/arch/arm/boot/dts/bcm2711.dtsi\n+++ b/arch/arm/boot/dts/bcm2711.dtsi\n@@ -305,7 +305,7 @@\n \t\t\tcompatible = \"brcm,bcm2711-vec\";\n \t\t\treg = <0x7ec13000 0x1000>;\n \t\t\tclocks = <&clocks BCM2835_CLOCK_VEC>;\n-\t\t\tinterrupts = <2 27>;\n+\t\t\tinterrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;\n \t\t\tstatus = \"disabled\";\n \t\t};\n \n@@ -1165,7 +1165,3 @@\n &usb {\n \tinterrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;\n };\n-\n-&vec {\n-\tinterrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;\n-};\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0698-overlays-Add-overlay-for-Si446x-Transceiver-SPI.patch",
    "content": "From 7f747c53fc4afa9a25eeb3ca290b4fed4690ca3f Mon Sep 17 00:00:00 2001\nFrom: \"Sunip K. Mukherjee\" <sunipkmukherjee@gmail.com>\nDate: Sun, 4 Jul 2021 16:03:07 -0400\nSubject: [PATCH] overlays: Add overlay for Si446x Transceiver SPI\n\nSee: https://github.com/raspberrypi/linux/pull/4430\n\nSigned-off-by: Sunip K. Mukherjee <sunipkmukherjee@gmail.com>\n---\n arch/arm/boot/dts/overlays/Makefile           |  1 +\n arch/arm/boot/dts/overlays/README             | 10 ++++\n .../boot/dts/overlays/si446x-spi0-overlay.dts | 53 +++++++++++++++++++\n 3 files changed, 64 insertions(+)\n create mode 100644 arch/arm/boot/dts/overlays/si446x-spi0-overlay.dts\n\n--- a/arch/arm/boot/dts/overlays/Makefile\n+++ b/arch/arm/boot/dts/overlays/Makefile\n@@ -176,6 +176,7 @@ dtbo-$(CONFIG_ARCH_BCM2835) += \\\n \tseeed-can-fd-hat-v1.dtbo \\\n \tseeed-can-fd-hat-v2.dtbo \\\n \tsh1106-spi.dtbo \\\n+\tsi446x-spi0.dtbo \\\n \tsmi.dtbo \\\n \tsmi-dev.dtbo \\\n \tsmi-nand.dtbo \\\n--- a/arch/arm/boot/dts/overlays/README\n+++ b/arch/arm/boot/dts/overlays/README\n@@ -2733,6 +2733,16 @@ Params: speed                   SPI bus\n         height                  Display height (32 or 64; default 64)\n \n \n+Name:   si446x-spi0\n+Info:   Overlay for Si446x UHF Transceiver via SPI using si446x driver.\n+        The driver is currently out-of-tree at\n+        https://github.com/sunipkmukherjee/silabs.git\n+Load:   dtoverlay=si446x-spi0,<param>=<val>\n+Params: speed                   SPI bus speed (default 4000000)\n+        int_pin                 GPIO pin for interrupts (default 17)\n+        reset_pin               GPIO pin for RESET (default 27)\n+\n+\n Name:   smi\n Info:   Enables the Secondary Memory Interface peripheral. Uses GPIOs 2-25!\n Load:   dtoverlay=smi\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/si446x-spi0-overlay.dts\n@@ -0,0 +1,53 @@\n+// Overlay for the SiLabs Si446X Controller - SPI0\n+// Default Interrupt Pin: 17\n+// Default SDN Pin: 27\n+/dts-v1/;\n+/plugin/;\n+\n+   / {\n+    compatible = \"brcm,bcm2835\";\n+\n+    fragment@0 {\n+        target = <&spi0>;\n+        __overlay__ {\n+            // needed to avoid dtc warning\n+            #address-cells = <1>;\n+            #size-cells = <0>;\n+\n+            status = \"okay\";\n+\n+            uhf0: si446x@0{\n+                compatible = \"silabs,si446x\";\n+                reg = <0>; // CE0\n+                pinctrl-names = \"default\";\n+                pinctrl-0 = <&uhf0_pins>;\n+                interrupt-parent = <&gpio>;\n+                interrupts = <17 0x2>; // falling edge\n+                spi-max-frequency = <4000000>;\n+                sdn_pin = <27>;\n+                irq_pin = <17>;\n+                status = \"okay\";\n+            };\n+        };\n+    };\n+\n+    fragment@1 {\n+        target = <&gpio>;\n+        __overlay__ {\n+            uhf0_pins: uhf0_pins {\n+                brcm,pins = <17 27>;\n+                brcm,function = <0 1>; // in, out\n+                brcm,pull = <2 0>; // high, none\n+            };\n+        };\n+    };\n+\n+    __overrides__ {\n+        int_pin = <&uhf0>, \"interrupts:0\",\n+                  <&uhf0>, \"irq_pin:0\",\n+                  <&uhf0_pins>, \"brcm,pins:0\";\n+        reset_pin = <&uhf0>, \"sdn_pin:0\",\n+                    <&uhf0_pins>, \"brcm,pins:4\";\n+        speed   = <&uhf0>, \"spi-max-frequency:0\";\n+    };\n+};\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0699-drm-vc4-Fix-timings-for-VEC-modes.patch",
    "content": "From 023e20cf561dc49897997f55e88b7d336eb5cee9 Mon Sep 17 00:00:00 2001\nFrom: Mateusz Kwiatkowski <kfyatek+publicgit@gmail.com>\nDate: Thu, 15 Jul 2021 01:07:30 +0200\nSubject: [PATCH] drm/vc4: Fix timings for VEC modes\n\nThis commit fixes vertical timings of the VEC (composite output) modes\nto accurately represent the 525-line (\"NTSC\") and 625-line (\"PAL\") ITU-R\nstandards.\n\nPrevious timings were actually defined as 502 and 601 lines, resulting\nin non-standard 62.69 Hz and 52 Hz signals being generated,\nrespectively.\n\nChanges to vc4_crtc.c have also been made, to make the PixelValve\nvertical timings accurately correspond to the DRM modeline in interlaced\nmodes. The resulting VERTA/VERTB register values have been verified\nagainst the reference values set by the Raspberry Pi firmware.\n\nSigned-off-by: Mateusz Kwiatkowski <kfyatek+publicgit@gmail.com>\n---\n drivers/gpu/drm/vc4/vc4_crtc.c | 70 +++++++++++++++++++++-------------\n drivers/gpu/drm/vc4/vc4_vec.c  |  4 +-\n 2 files changed, 45 insertions(+), 29 deletions(-)\n\n--- a/drivers/gpu/drm/vc4/vc4_crtc.c\n+++ b/drivers/gpu/drm/vc4/vc4_crtc.c\n@@ -316,8 +316,14 @@ static void vc4_crtc_config_pv(struct dr\n \tbool is_dsi = (vc4_encoder->type == VC4_ENCODER_TYPE_DSI0 ||\n \t\t       vc4_encoder->type == VC4_ENCODER_TYPE_DSI1);\n \tbool is_dsi1 = vc4_encoder->type == VC4_ENCODER_TYPE_DSI1;\n+\tbool is_vec = vc4_encoder->type == VC4_ENCODER_TYPE_VEC;\n \tu32 format = is_dsi1 ? PV_CONTROL_FORMAT_DSIV_24 : PV_CONTROL_FORMAT_24;\n \tu8 ppc = pv_data->pixels_per_clock;\n+\n+\tu16 vert_bp = mode->crtc_vtotal - mode->crtc_vsync_end;\n+\tu16 vert_sync = mode->crtc_vsync_end - mode->crtc_vsync_start;\n+\tu16 vert_fp = mode->crtc_vsync_start - mode->crtc_vdisplay;\n+\n \tbool debug_dump_regs = false;\n \n \tif (debug_dump_regs) {\n@@ -341,49 +347,59 @@ static void vc4_crtc_config_pv(struct dr\n \t\t   VC4_SET_FIELD(mode->hdisplay * pixel_rep / ppc,\n \t\t\t\t PV_HORZB_HACTIVE));\n \n-\tCRTC_WRITE(PV_VERTA,\n-\t\t   VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end +\n-\t\t\t\t interlace,\n-\t\t\t\t PV_VERTA_VBP) |\n-\t\t   VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,\n-\t\t\t\t PV_VERTA_VSYNC));\n-\tCRTC_WRITE(PV_VERTB,\n-\t\t   VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,\n-\t\t\t\t PV_VERTB_VFP) |\n-\t\t   VC4_SET_FIELD(mode->crtc_vdisplay, PV_VERTB_VACTIVE));\n-\n \tif (interlace) {\n+\t\tbool odd_field_first = false;\n+\t\tu32 field_delay = mode->htotal * pixel_rep / (2 * ppc);\n+\t\tu16 vert_bp_even = vert_bp;\n+\t\tu16 vert_fp_even = vert_fp;\n+\n+\t\tif (is_vec) {\n+\t\t\t/* VEC (composite output) */\n+\t\t\t++field_delay;\n+\t\t\tif (mode->htotal == 858) {\n+\t\t\t\t/* 525-line mode (NTSC or PAL-M) */\n+\t\t\t\todd_field_first = true;\n+\t\t\t}\n+\t\t}\n+\n+\t\tif (odd_field_first)\n+\t\t\t++vert_fp_even;\n+\t\telse\n+\t\t\t++vert_bp;\n+\n \t\tCRTC_WRITE(PV_VERTA_EVEN,\n-\t\t\t   VC4_SET_FIELD(mode->crtc_vtotal -\n-\t\t\t\t\t mode->crtc_vsync_end,\n-\t\t\t\t\t PV_VERTA_VBP) |\n-\t\t\t   VC4_SET_FIELD(mode->crtc_vsync_end -\n-\t\t\t\t\t mode->crtc_vsync_start,\n-\t\t\t\t\t PV_VERTA_VSYNC));\n+\t\t\t   VC4_SET_FIELD(vert_bp_even, PV_VERTA_VBP) |\n+\t\t\t   VC4_SET_FIELD(vert_sync, PV_VERTA_VSYNC));\n \t\tCRTC_WRITE(PV_VERTB_EVEN,\n-\t\t\t   VC4_SET_FIELD(mode->crtc_vsync_start -\n-\t\t\t\t\t mode->crtc_vdisplay,\n-\t\t\t\t\t PV_VERTB_VFP) |\n+\t\t\t   VC4_SET_FIELD(vert_fp_even, PV_VERTB_VFP) |\n \t\t\t   VC4_SET_FIELD(mode->crtc_vdisplay, PV_VERTB_VACTIVE));\n \n-\t\t/* We set up first field even mode for HDMI.  VEC's\n-\t\t * NTSC mode would want first field odd instead, once\n-\t\t * we support it (to do so, set ODD_FIRST and put the\n-\t\t * delay in VSYNCD_EVEN instead).\n+\t\t/* We set up first field even mode for HDMI and VEC's PAL.\n+\t\t * For NTSC, we need first field odd.\n \t\t */\n \t\tCRTC_WRITE(PV_V_CONTROL,\n \t\t\t   PV_VCONTROL_CONTINUOUS |\n \t\t\t   (is_dsi ? PV_VCONTROL_DSI : 0) |\n \t\t\t   PV_VCONTROL_INTERLACE |\n-\t\t\t   VC4_SET_FIELD(mode->htotal * pixel_rep / (2 * ppc),\n-\t\t\t\t\t PV_VCONTROL_ODD_DELAY));\n-\t\tCRTC_WRITE(PV_VSYNCD_EVEN, 0);\n+\t\t\t   (odd_field_first\n+\t\t\t\t   ? PV_VCONTROL_ODD_FIRST\n+\t\t\t\t   : VC4_SET_FIELD(field_delay,\n+\t\t\t\t\t\t   PV_VCONTROL_ODD_DELAY)));\n+\t\tCRTC_WRITE(PV_VSYNCD_EVEN,\n+\t\t\t   (odd_field_first ? field_delay : 0));\n \t} else {\n \t\tCRTC_WRITE(PV_V_CONTROL,\n \t\t\t   PV_VCONTROL_CONTINUOUS |\n \t\t\t   (is_dsi ? PV_VCONTROL_DSI : 0));\n \t}\n \n+\tCRTC_WRITE(PV_VERTA,\n+\t\t   VC4_SET_FIELD(vert_bp, PV_VERTA_VBP) |\n+\t\t   VC4_SET_FIELD(vert_sync, PV_VERTA_VSYNC));\n+\tCRTC_WRITE(PV_VERTB,\n+\t\t   VC4_SET_FIELD(vert_fp, PV_VERTB_VFP) |\n+\t\t   VC4_SET_FIELD(mode->crtc_vdisplay, PV_VERTB_VACTIVE));\n+\n \tif (is_dsi)\n \t\tCRTC_WRITE(PV_HACT_ACT, mode->hdisplay * pixel_rep);\n \n--- a/drivers/gpu/drm/vc4/vc4_vec.c\n+++ b/drivers/gpu/drm/vc4/vc4_vec.c\n@@ -262,7 +262,7 @@ static void vc4_vec_ntsc_j_mode_set(stru\n static const struct drm_display_mode ntsc_mode = {\n \tDRM_MODE(\"720x480\", DRM_MODE_TYPE_DRIVER, 13500,\n \t\t 720, 720 + 14, 720 + 14 + 64, 720 + 14 + 64 + 60, 0,\n-\t\t 480, 480 + 3, 480 + 3 + 3, 480 + 3 + 3 + 16, 0,\n+\t\t 480, 480 + 7, 480 + 7 + 6, 525, 0,\n \t\t DRM_MODE_FLAG_INTERLACE)\n };\n \n@@ -284,7 +284,7 @@ static void vc4_vec_pal_m_mode_set(struc\n static const struct drm_display_mode pal_mode = {\n \tDRM_MODE(\"720x576\", DRM_MODE_TYPE_DRIVER, 13500,\n \t\t 720, 720 + 20, 720 + 20 + 64, 720 + 20 + 64 + 60, 0,\n-\t\t 576, 576 + 2, 576 + 2 + 3, 576 + 2 + 3 + 20, 0,\n+\t\t 576, 576 + 4, 576 + 4 + 6, 625, 0,\n \t\t DRM_MODE_FLAG_INTERLACE)\n };\n \n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0700-drm-vc4-Refactor-VEC-TV-mode-setting.patch",
    "content": "From db797f19f66c49273ad00803756c429ed776dc01 Mon Sep 17 00:00:00 2001\nFrom: Mateusz Kwiatkowski <kfyatek+publicgit@gmail.com>\nDate: Thu, 15 Jul 2021 01:07:49 +0200\nSubject: [PATCH] drm/vc4: Refactor VEC TV mode setting\n\nChange the mode_set function pointer logic to declarative config0,\nconfig1 and custom_freq fields, to make TV mode setting logic more\nconcise and uniform.\n\nAdditionally, remove the superfluous tv_mode field, which was redundant\nwith the mode field in struct drm_tv_connector_state.\n\nSigned-off-by: Mateusz Kwiatkowski <kfyatek+publicgit@gmail.com>\n---\n drivers/gpu/drm/vc4/vc4_vec.c | 69 +++++++++++------------------------\n 1 file changed, 22 insertions(+), 47 deletions(-)\n\n--- a/drivers/gpu/drm/vc4/vc4_vec.c\n+++ b/drivers/gpu/drm/vc4/vc4_vec.c\n@@ -170,8 +170,6 @@ struct vc4_vec {\n \n \tstruct clk *clock;\n \n-\tconst struct vc4_vec_tv_mode *tv_mode;\n-\n \tstruct debugfs_regset32 regset;\n };\n \n@@ -217,7 +215,9 @@ enum vc4_vec_tv_mode_id {\n \n struct vc4_vec_tv_mode {\n \tconst struct drm_display_mode *mode;\n-\tvoid (*mode_set)(struct vc4_vec *vec);\n+\tu32 config0;\n+\tu32 config1;\n+\tu32 custom_freq;\n };\n \n static const struct debugfs_reg32 vec_regs[] = {\n@@ -247,18 +247,6 @@ static const struct debugfs_reg32 vec_re\n \tVC4_REG32(VEC_DAC_MISC),\n };\n \n-static void vc4_vec_ntsc_mode_set(struct vc4_vec *vec)\n-{\n-\tVEC_WRITE(VEC_CONFIG0, VEC_CONFIG0_NTSC_STD | VEC_CONFIG0_PDEN);\n-\tVEC_WRITE(VEC_CONFIG1, VEC_CONFIG1_C_CVBS_CVBS);\n-}\n-\n-static void vc4_vec_ntsc_j_mode_set(struct vc4_vec *vec)\n-{\n-\tVEC_WRITE(VEC_CONFIG0, VEC_CONFIG0_NTSC_STD);\n-\tVEC_WRITE(VEC_CONFIG1, VEC_CONFIG1_C_CVBS_CVBS);\n-}\n-\n static const struct drm_display_mode ntsc_mode = {\n \tDRM_MODE(\"720x480\", DRM_MODE_TYPE_DRIVER, 13500,\n \t\t 720, 720 + 14, 720 + 14 + 64, 720 + 14 + 64 + 60, 0,\n@@ -266,21 +254,6 @@ static const struct drm_display_mode nts\n \t\t DRM_MODE_FLAG_INTERLACE)\n };\n \n-static void vc4_vec_pal_mode_set(struct vc4_vec *vec)\n-{\n-\tVEC_WRITE(VEC_CONFIG0, VEC_CONFIG0_PAL_BDGHI_STD);\n-\tVEC_WRITE(VEC_CONFIG1, VEC_CONFIG1_C_CVBS_CVBS);\n-}\n-\n-static void vc4_vec_pal_m_mode_set(struct vc4_vec *vec)\n-{\n-\tVEC_WRITE(VEC_CONFIG0, VEC_CONFIG0_PAL_BDGHI_STD);\n-\tVEC_WRITE(VEC_CONFIG1,\n-\t\t  VEC_CONFIG1_C_CVBS_CVBS | VEC_CONFIG1_CUSTOM_FREQ);\n-\tVEC_WRITE(VEC_FREQ3_2, 0x223b);\n-\tVEC_WRITE(VEC_FREQ1_0, 0x61d1);\n-}\n-\n static const struct drm_display_mode pal_mode = {\n \tDRM_MODE(\"720x576\", DRM_MODE_TYPE_DRIVER, 13500,\n \t\t 720, 720 + 20, 720 + 20 + 64, 720 + 20 + 64 + 60, 0,\n@@ -291,19 +264,24 @@ static const struct drm_display_mode pal\n static const struct vc4_vec_tv_mode vc4_vec_tv_modes[] = {\n \t[VC4_VEC_TV_MODE_NTSC] = {\n \t\t.mode = &ntsc_mode,\n-\t\t.mode_set = vc4_vec_ntsc_mode_set,\n+\t\t.config0 = VEC_CONFIG0_NTSC_STD | VEC_CONFIG0_PDEN,\n+\t\t.config1 = VEC_CONFIG1_C_CVBS_CVBS,\n \t},\n \t[VC4_VEC_TV_MODE_NTSC_J] = {\n \t\t.mode = &ntsc_mode,\n-\t\t.mode_set = vc4_vec_ntsc_j_mode_set,\n+\t\t.config0 = VEC_CONFIG0_NTSC_STD,\n+\t\t.config1 = VEC_CONFIG1_C_CVBS_CVBS,\n \t},\n \t[VC4_VEC_TV_MODE_PAL] = {\n \t\t.mode = &pal_mode,\n-\t\t.mode_set = vc4_vec_pal_mode_set,\n+\t\t.config0 = VEC_CONFIG0_PAL_BDGHI_STD,\n+\t\t.config1 = VEC_CONFIG1_C_CVBS_CVBS,\n \t},\n \t[VC4_VEC_TV_MODE_PAL_M] = {\n \t\t.mode = &pal_mode,\n-\t\t.mode_set = vc4_vec_pal_m_mode_set,\n+\t\t.config0 = VEC_CONFIG0_PAL_BDGHI_STD,\n+\t\t.config1 = VEC_CONFIG1_C_CVBS_CVBS | VEC_CONFIG1_CUSTOM_FREQ,\n+\t\t.custom_freq = 0x223b61d1,\n \t},\n };\n \n@@ -373,7 +351,6 @@ static struct drm_connector *vc4_vec_con\n \tdrm_object_attach_property(&connector->base,\n \t\t\t\t   dev->mode_config.tv_mode_property,\n \t\t\t\t   VC4_VEC_TV_MODE_NTSC);\n-\tvec->tv_mode = &vc4_vec_tv_modes[VC4_VEC_TV_MODE_NTSC];\n \n \tdrm_connector_attach_encoder(connector, vec->encoder);\n \n@@ -406,6 +383,7 @@ static void vc4_vec_encoder_enable(struc\n {\n \tstruct vc4_vec_encoder *vc4_vec_encoder = to_vc4_vec_encoder(encoder);\n \tstruct vc4_vec *vec = vc4_vec_encoder->vec;\n+\tunsigned int tv_mode = vec->connector->state->tv.mode;\n \tint ret;\n \n \tret = pm_runtime_get_sync(&vec->pdev->dev);\n@@ -461,7 +439,15 @@ static void vc4_vec_encoder_enable(struc\n \t/* Mask all interrupts. */\n \tVEC_WRITE(VEC_MASK0, 0);\n \n-\tvec->tv_mode->mode_set(vec);\n+\tVEC_WRITE(VEC_CONFIG0, vc4_vec_tv_modes[tv_mode].config0);\n+\tVEC_WRITE(VEC_CONFIG1, vc4_vec_tv_modes[tv_mode].config1);\n+\tif (vc4_vec_tv_modes[tv_mode].custom_freq != 0) {\n+\t\tVEC_WRITE(VEC_FREQ3_2,\n+\t\t\t  (vc4_vec_tv_modes[tv_mode].custom_freq >> 16) &\n+\t\t\t  0xffff);\n+\t\tVEC_WRITE(VEC_FREQ1_0,\n+\t\t\t  vc4_vec_tv_modes[tv_mode].custom_freq & 0xffff);\n+\t}\n \n \tVEC_WRITE(VEC_DAC_MISC,\n \t\t  VEC_DAC_MISC_VID_ACT | VEC_DAC_MISC_DAC_RST_N);\n@@ -476,16 +462,6 @@ static bool vc4_vec_encoder_mode_fixup(s\n \treturn true;\n }\n \n-static void vc4_vec_encoder_atomic_mode_set(struct drm_encoder *encoder,\n-\t\t\t\t\tstruct drm_crtc_state *crtc_state,\n-\t\t\t\t\tstruct drm_connector_state *conn_state)\n-{\n-\tstruct vc4_vec_encoder *vc4_vec_encoder = to_vc4_vec_encoder(encoder);\n-\tstruct vc4_vec *vec = vc4_vec_encoder->vec;\n-\n-\tvec->tv_mode = &vc4_vec_tv_modes[conn_state->tv.mode];\n-}\n-\n static int vc4_vec_encoder_atomic_check(struct drm_encoder *encoder,\n \t\t\t\t\tstruct drm_crtc_state *crtc_state,\n \t\t\t\t\tstruct drm_connector_state *conn_state)\n@@ -506,7 +482,6 @@ static const struct drm_encoder_helper_f\n \t.enable = vc4_vec_encoder_enable,\n \t.mode_fixup = vc4_vec_encoder_mode_fixup,\n \t.atomic_check = vc4_vec_encoder_atomic_check,\n-\t.atomic_mode_set = vc4_vec_encoder_atomic_mode_set,\n };\n \n static const struct vc4_vec_variant bcm2835_vec_variant = {\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0701-drm-vc4-Fix-definition-of-PAL-M-mode.patch",
    "content": "From fd0b5aec6d320f10b869cae06b6f2c8ca650e8e2 Mon Sep 17 00:00:00 2001\nFrom: Mateusz Kwiatkowski <kfyatek+publicgit@gmail.com>\nDate: Thu, 15 Jul 2021 01:07:53 +0200\nSubject: [PATCH] drm/vc4: Fix definition of PAL-M mode\n\nPAL-M is a Brazilian analog TV standard that uses a PAL-style chroma\nsubcarrier at 3.575611[888111] MHz on top of 525-line (480i60) timings.\nThis commit makes the driver actually use the proper VEC preset for this\nmode instead of just changing PAL subcarrier frequency.\n\nDRM mode constant names have also been changed, as they no longer\ncorrespond to the \"NTSC\" or \"PAL\" terms.\n\nSigned-off-by: Mateusz Kwiatkowski <kfyatek+publicgit@gmail.com>\n---\n drivers/gpu/drm/vc4/vc4_vec.c | 18 +++++++++---------\n 1 file changed, 9 insertions(+), 9 deletions(-)\n\n--- a/drivers/gpu/drm/vc4/vc4_vec.c\n+++ b/drivers/gpu/drm/vc4/vc4_vec.c\n@@ -68,6 +68,7 @@\n #define VEC_CONFIG0_STD_MASK\t\tGENMASK(1, 0)\n #define VEC_CONFIG0_NTSC_STD\t\t0\n #define VEC_CONFIG0_PAL_BDGHI_STD\t1\n+#define VEC_CONFIG0_PAL_M_STD\t\t2\n #define VEC_CONFIG0_PAL_N_STD\t\t3\n \n #define VEC_SCHPH\t\t\t0x108\n@@ -247,14 +248,14 @@ static const struct debugfs_reg32 vec_re\n \tVC4_REG32(VEC_DAC_MISC),\n };\n \n-static const struct drm_display_mode ntsc_mode = {\n+static const struct drm_display_mode drm_mode_480i = {\n \tDRM_MODE(\"720x480\", DRM_MODE_TYPE_DRIVER, 13500,\n \t\t 720, 720 + 14, 720 + 14 + 64, 720 + 14 + 64 + 60, 0,\n \t\t 480, 480 + 7, 480 + 7 + 6, 525, 0,\n \t\t DRM_MODE_FLAG_INTERLACE)\n };\n \n-static const struct drm_display_mode pal_mode = {\n+static const struct drm_display_mode drm_mode_576i = {\n \tDRM_MODE(\"720x576\", DRM_MODE_TYPE_DRIVER, 13500,\n \t\t 720, 720 + 20, 720 + 20 + 64, 720 + 20 + 64 + 60, 0,\n \t\t 576, 576 + 4, 576 + 4 + 6, 625, 0,\n@@ -263,25 +264,24 @@ static const struct drm_display_mode pal\n \n static const struct vc4_vec_tv_mode vc4_vec_tv_modes[] = {\n \t[VC4_VEC_TV_MODE_NTSC] = {\n-\t\t.mode = &ntsc_mode,\n+\t\t.mode = &drm_mode_480i,\n \t\t.config0 = VEC_CONFIG0_NTSC_STD | VEC_CONFIG0_PDEN,\n \t\t.config1 = VEC_CONFIG1_C_CVBS_CVBS,\n \t},\n \t[VC4_VEC_TV_MODE_NTSC_J] = {\n-\t\t.mode = &ntsc_mode,\n+\t\t.mode = &drm_mode_480i,\n \t\t.config0 = VEC_CONFIG0_NTSC_STD,\n \t\t.config1 = VEC_CONFIG1_C_CVBS_CVBS,\n \t},\n \t[VC4_VEC_TV_MODE_PAL] = {\n-\t\t.mode = &pal_mode,\n+\t\t.mode = &drm_mode_576i,\n \t\t.config0 = VEC_CONFIG0_PAL_BDGHI_STD,\n \t\t.config1 = VEC_CONFIG1_C_CVBS_CVBS,\n \t},\n \t[VC4_VEC_TV_MODE_PAL_M] = {\n-\t\t.mode = &pal_mode,\n-\t\t.config0 = VEC_CONFIG0_PAL_BDGHI_STD,\n-\t\t.config1 = VEC_CONFIG1_C_CVBS_CVBS | VEC_CONFIG1_CUSTOM_FREQ,\n-\t\t.custom_freq = 0x223b61d1,\n+\t\t.mode = &drm_mode_480i,\n+\t\t.config0 = VEC_CONFIG0_PAL_M_STD,\n+\t\t.config1 = VEC_CONFIG1_C_CVBS_CVBS,\n \t},\n };\n \n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0702-drm-vc4-Add-support-for-more-analog-TV-standards.patch",
    "content": "From 6eca6c329b247adab647f1d4b380cd630f923806 Mon Sep 17 00:00:00 2001\nFrom: Mateusz Kwiatkowski <kfyatek+publicgit@gmail.com>\nDate: Thu, 15 Jul 2021 01:07:58 +0200\nSubject: [PATCH] drm/vc4: Add support for more analog TV standards\n\nAdd support for the following composite output modes (all of them are\nsomewhat more obscure than the previously defined ones):\n\n- NTSC_443 - NTSC-style signal with the chroma subcarrier shifted to\n  4.43361875 MHz (the PAL subcarrier frequency). Never used for\n  broadcasting, but sometimes used as a hack to play NTSC content in PAL\n  regions (e.g. on VCRs).\n- PAL_N - PAL with alternative chroma subcarrier frequency,\n  3.58205625 MHz. Used as a broadcast standard in Argentina, Paraguay\n  and Uruguay to fit 576i50 with colour in 6 MHz channel raster.\n- PAL60 - 480i60 signal with PAL-style color at normal European PAL\n  frequency. Another non-standard, non-broadcast mode, used in similar\n  contexts as NTSC_443. Some displays support one but not the other.\n- SECAM - French frequency-modulated analog color standard; also have\n  been broadcast in Eastern Europe and various parts of Africa and Asia.\n  Uses the same 576i50 timings as PAL.\n\nAlso added some comments explaining color subcarrier frequency\nregisters.\n\nSigned-off-by: Mateusz Kwiatkowski <kfyatek+publicgit@gmail.com>\n---\n drivers/gpu/drm/vc4/vc4_vec.c | 63 +++++++++++++++++++++++++++++++++++\n 1 file changed, 63 insertions(+)\n\n--- a/drivers/gpu/drm/vc4/vc4_vec.c\n+++ b/drivers/gpu/drm/vc4/vc4_vec.c\n@@ -45,6 +45,7 @@\n #define VEC_CONFIG0_YDEL(x)\t\t((x) << 26)\n #define VEC_CONFIG0_CDEL_MASK\t\tGENMASK(25, 24)\n #define VEC_CONFIG0_CDEL(x)\t\t((x) << 24)\n+#define VEC_CONFIG0_SECAM_STD\t\tBIT(21)\n #define VEC_CONFIG0_PBPR_FIL\t\tBIT(18)\n #define VEC_CONFIG0_CHROMA_GAIN_MASK\tGENMASK(17, 16)\n #define VEC_CONFIG0_CHROMA_GAIN_UNITY\t(0 << 16)\n@@ -75,6 +76,27 @@\n #define VEC_SOFT_RESET\t\t\t0x10c\n #define VEC_CLMP0_START\t\t\t0x144\n #define VEC_CLMP0_END\t\t\t0x148\n+\n+/*\n+ * These set the color subcarrier frequency\n+ * if VEC_CONFIG1_CUSTOM_FREQ is enabled.\n+ *\n+ * VEC_FREQ1_0 contains the most significant 16-bit half-word,\n+ * VEC_FREQ3_2 contains the least significant 16-bit half-word.\n+ * 0x80000000 seems to be equivalent to the pixel clock\n+ * (which itself is the VEC clock divided by 8).\n+ *\n+ * Reference values (with the default pixel clock of 13.5 MHz):\n+ *\n+ * NTSC  (3579545.[45] Hz)     - 0x21F07C1F\n+ * PAL   (4433618.75 Hz)       - 0x2A098ACB\n+ * PAL-M (3575611.[888111] Hz) - 0x21E6EFE3\n+ * PAL-N (3582056.25 Hz)       - 0x21F69446\n+ *\n+ * NOTE: For SECAM, it is used as the Dr center frequency,\n+ * regardless of whether VEC_CONFIG1_CUSTOM_FREQ is enabled or not;\n+ * that is specified as 4406250 Hz, which corresponds to 0x29C71C72.\n+ */\n #define VEC_FREQ3_2\t\t\t0x180\n #define VEC_FREQ1_0\t\t\t0x184\n \n@@ -117,6 +139,14 @@\n \n #define VEC_INTERRUPT_CONTROL\t\t0x190\n #define VEC_INTERRUPT_STATUS\t\t0x194\n+\n+/*\n+ * Db center frequency for SECAM; the clock for this is the same as for\n+ * VEC_FREQ3_2/VEC_FREQ1_0, which is used for Dr center frequency.\n+ *\n+ * This is specified as 4250000 Hz, which corresponds to 0x284BDA13.\n+ * That is also the default value, so no need to set it explicitly.\n+ */\n #define VEC_FCW_SECAM_B\t\t\t0x198\n #define VEC_SECAM_GAIN_VAL\t\t0x19c\n \n@@ -210,8 +240,12 @@ to_vc4_vec_connector(struct drm_connecto\n enum vc4_vec_tv_mode_id {\n \tVC4_VEC_TV_MODE_NTSC,\n \tVC4_VEC_TV_MODE_NTSC_J,\n+\tVC4_VEC_TV_MODE_NTSC_443,\n \tVC4_VEC_TV_MODE_PAL,\n \tVC4_VEC_TV_MODE_PAL_M,\n+\tVC4_VEC_TV_MODE_PAL_N,\n+\tVC4_VEC_TV_MODE_PAL60,\n+\tVC4_VEC_TV_MODE_SECAM,\n };\n \n struct vc4_vec_tv_mode {\n@@ -273,6 +307,13 @@ static const struct vc4_vec_tv_mode vc4_\n \t\t.config0 = VEC_CONFIG0_NTSC_STD,\n \t\t.config1 = VEC_CONFIG1_C_CVBS_CVBS,\n \t},\n+\t[VC4_VEC_TV_MODE_NTSC_443] = {\n+\t\t/* NTSC with PAL chroma frequency */\n+\t\t.mode = &drm_mode_480i,\n+\t\t.config0 = VEC_CONFIG0_NTSC_STD,\n+\t\t.config1 = VEC_CONFIG1_C_CVBS_CVBS | VEC_CONFIG1_CUSTOM_FREQ,\n+\t\t.custom_freq = 0x2a098acb,\n+\t},\n \t[VC4_VEC_TV_MODE_PAL] = {\n \t\t.mode = &drm_mode_576i,\n \t\t.config0 = VEC_CONFIG0_PAL_BDGHI_STD,\n@@ -283,6 +324,24 @@ static const struct vc4_vec_tv_mode vc4_\n \t\t.config0 = VEC_CONFIG0_PAL_M_STD,\n \t\t.config1 = VEC_CONFIG1_C_CVBS_CVBS,\n \t},\n+\t[VC4_VEC_TV_MODE_PAL_N] = {\n+\t\t.mode = &drm_mode_576i,\n+\t\t.config0 = VEC_CONFIG0_PAL_N_STD,\n+\t\t.config1 = VEC_CONFIG1_C_CVBS_CVBS,\n+\t},\n+\t[VC4_VEC_TV_MODE_PAL60] = {\n+\t\t/* PAL-M with chroma frequency of regular PAL */\n+\t\t.mode = &drm_mode_480i,\n+\t\t.config0 = VEC_CONFIG0_PAL_M_STD,\n+\t\t.config1 = VEC_CONFIG1_C_CVBS_CVBS | VEC_CONFIG1_CUSTOM_FREQ,\n+\t\t.custom_freq = 0x2a098acb,\n+\t},\n+\t[VC4_VEC_TV_MODE_SECAM] = {\n+\t\t.mode = &drm_mode_576i,\n+\t\t.config0 = VEC_CONFIG0_SECAM_STD,\n+\t\t.config1 = VEC_CONFIG1_C_CVBS_CVBS,\n+\t\t.custom_freq = 0x29c71c72,\n+\t},\n };\n \n static enum drm_connector_status\n@@ -505,8 +564,12 @@ static const struct of_device_id vc4_vec\n static const char * const tv_mode_names[] = {\n \t[VC4_VEC_TV_MODE_NTSC] = \"NTSC\",\n \t[VC4_VEC_TV_MODE_NTSC_J] = \"NTSC-J\",\n+\t[VC4_VEC_TV_MODE_NTSC_443] = \"NTSC-443\",\n \t[VC4_VEC_TV_MODE_PAL] = \"PAL\",\n \t[VC4_VEC_TV_MODE_PAL_M] = \"PAL-M\",\n+\t[VC4_VEC_TV_MODE_PAL_N] = \"PAL-N\",\n+\t[VC4_VEC_TV_MODE_PAL60] = \"PAL60\",\n+\t[VC4_VEC_TV_MODE_SECAM] = \"SECAM\",\n };\n \n static int vc4_vec_bind(struct device *dev, struct device *master, void *data)\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0703-drm-vc4-Allow-setting-the-TV-norm-via-module-paramet.patch",
    "content": "From 2a153d97f5ea9086f309a0abef57dfe0b7a46e96 Mon Sep 17 00:00:00 2001\nFrom: Mateusz Kwiatkowski <kfyatek+publicgit@gmail.com>\nDate: Thu, 15 Jul 2021 01:08:01 +0200\nSubject: [PATCH] drm/vc4: Allow setting the TV norm via module\n parameter\n\nSimilar to the ch7006 and nouveau drivers, introduce a \"tv_mode\" module\nparameter that allow setting the TV norm by specifying vc4.tv_norm= on\nthe kernel command line.\n\nIf that is not specified, try inferring one of the most popular norms\n(PAL or NTSC) from the video mode specified on the command line. On\nRaspberry Pis, this causes the most common cases of the sdtv_mode\nsetting in config.txt to be respected.\n\nSigned-off-by: Mateusz Kwiatkowski <kfyatek+publicgit@gmail.com>\n---\n drivers/gpu/drm/vc4/vc4_vec.c | 72 ++++++++++++++++++++++++++++-------\n 1 file changed, 58 insertions(+), 14 deletions(-)\n\n--- a/drivers/gpu/drm/vc4/vc4_vec.c\n+++ b/drivers/gpu/drm/vc4/vc4_vec.c\n@@ -66,7 +66,7 @@\n #define VEC_CONFIG0_YCDELAY\t\tBIT(4)\n #define VEC_CONFIG0_RAMPEN\t\tBIT(2)\n #define VEC_CONFIG0_YCDIS\t\tBIT(2)\n-#define VEC_CONFIG0_STD_MASK\t\tGENMASK(1, 0)\n+#define VEC_CONFIG0_STD_MASK\t\t(VEC_CONFIG0_SECAM_STD | GENMASK(1, 0))\n #define VEC_CONFIG0_NTSC_STD\t\t0\n #define VEC_CONFIG0_PAL_BDGHI_STD\t1\n #define VEC_CONFIG0_PAL_M_STD\t\t2\n@@ -185,6 +185,8 @@\n #define VEC_DAC_MISC_DAC_RST_N\t\tBIT(0)\n \n \n+static char *vc4_vec_tv_norm;\n+\n struct vc4_vec_variant {\n \tu32 dac_config;\n };\n@@ -344,6 +346,44 @@ static const struct vc4_vec_tv_mode vc4_\n \t},\n };\n \n+static const char * const tv_mode_names[] = {\n+\t[VC4_VEC_TV_MODE_NTSC] = \"NTSC\",\n+\t[VC4_VEC_TV_MODE_NTSC_J] = \"NTSC-J\",\n+\t[VC4_VEC_TV_MODE_NTSC_443] = \"NTSC-443\",\n+\t[VC4_VEC_TV_MODE_PAL] = \"PAL\",\n+\t[VC4_VEC_TV_MODE_PAL_M] = \"PAL-M\",\n+\t[VC4_VEC_TV_MODE_PAL_N] = \"PAL-N\",\n+\t[VC4_VEC_TV_MODE_PAL60] = \"PAL60\",\n+\t[VC4_VEC_TV_MODE_SECAM] = \"SECAM\",\n+};\n+\n+enum vc4_vec_tv_mode_id\n+vc4_vec_get_default_mode(struct drm_connector *connector)\n+{\n+\tint i;\n+\n+\tif (vc4_vec_tv_norm) {\n+\t\tfor (i = 0; i < ARRAY_SIZE(tv_mode_names); i++)\n+\t\t\tif (strcmp(vc4_vec_tv_norm, tv_mode_names[i]) == 0)\n+\t\t\t\treturn (enum vc4_vec_tv_mode_id) i;\n+\t} else if (connector->cmdline_mode.specified &&\n+\t\t   ((connector->cmdline_mode.refresh_specified &&\n+\t\t     (connector->cmdline_mode.refresh == 25 ||\n+\t\t      connector->cmdline_mode.refresh == 50)) ||\n+\t\t    (!connector->cmdline_mode.refresh_specified &&\n+\t\t     (connector->cmdline_mode.yres == 288 ||\n+\t\t      connector->cmdline_mode.yres == 576)))) {\n+\t\t/*\n+\t\t * no explicitly specified TV norm; use PAL if a mode that\n+\t\t * looks like PAL has been specified on the command line\n+\t\t */\n+\t\treturn VC4_VEC_TV_MODE_PAL;\n+\t}\n+\n+\t/* in all other cases, default to NTSC */\n+\treturn VC4_VEC_TV_MODE_NTSC;\n+}\n+\n static enum drm_connector_status\n vc4_vec_connector_detect(struct drm_connector *connector, bool force)\n {\n@@ -373,11 +413,19 @@ static int vc4_vec_connector_get_modes(s\n \treturn 1;\n }\n \n+static void vc4_vec_connector_reset(struct drm_connector *connector)\n+{\n+\tdrm_atomic_helper_connector_reset(connector);\n+\t/* preserve TV standard */\n+\tif (connector->state)\n+\t\tconnector->state->tv.mode = vc4_vec_get_default_mode(connector);\n+}\n+\n static const struct drm_connector_funcs vc4_vec_connector_funcs = {\n \t.detect = vc4_vec_connector_detect,\n \t.fill_modes = drm_helper_probe_single_connector_modes,\n \t.destroy = vc4_vec_connector_destroy,\n-\t.reset = drm_atomic_helper_connector_reset,\n+\t.reset = vc4_vec_connector_reset,\n \t.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,\n \t.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,\n };\n@@ -409,7 +457,7 @@ static struct drm_connector *vc4_vec_con\n \n \tdrm_object_attach_property(&connector->base,\n \t\t\t\t   dev->mode_config.tv_mode_property,\n-\t\t\t\t   VC4_VEC_TV_MODE_NTSC);\n+\t\t\t\t   vc4_vec_get_default_mode(connector));\n \n \tdrm_connector_attach_encoder(connector, vec->encoder);\n \n@@ -561,17 +609,6 @@ static const struct of_device_id vc4_vec\n \t{ /* sentinel */ },\n };\n \n-static const char * const tv_mode_names[] = {\n-\t[VC4_VEC_TV_MODE_NTSC] = \"NTSC\",\n-\t[VC4_VEC_TV_MODE_NTSC_J] = \"NTSC-J\",\n-\t[VC4_VEC_TV_MODE_NTSC_443] = \"NTSC-443\",\n-\t[VC4_VEC_TV_MODE_PAL] = \"PAL\",\n-\t[VC4_VEC_TV_MODE_PAL_M] = \"PAL-M\",\n-\t[VC4_VEC_TV_MODE_PAL_N] = \"PAL-N\",\n-\t[VC4_VEC_TV_MODE_PAL60] = \"PAL60\",\n-\t[VC4_VEC_TV_MODE_SECAM] = \"SECAM\",\n-};\n-\n static int vc4_vec_bind(struct device *dev, struct device *master, void *data)\n {\n \tstruct platform_device *pdev = to_platform_device(dev);\n@@ -680,3 +717,10 @@ struct platform_driver vc4_vec_driver =\n \t\t.of_match_table = vc4_vec_dt_match,\n \t},\n };\n+\n+module_param_named(tv_norm, vc4_vec_tv_norm, charp, 0600);\n+MODULE_PARM_DESC(tv_norm, \"Default TV norm.\\n\"\n+\t\t \"\\t\\tSupported: NTSC, NTSC-J, NTSC-443, PAL, PAL-M, PAL-N,\\n\"\n+\t\t \"\\t\\t\\tPAL60, SECAM.\\n\"\n+\t\t \"\\t\\tDefault: PAL if a 50 Hz mode has been set via video=,\\n\"\n+\t\t \"\\t\\t\\tNTSC otherwise\");\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0704-drm-vc4-Refactor-mode-checking-logic.patch",
    "content": "From 63470fe3eedc28c8fd8c050cb5427a3f31bd99bd Mon Sep 17 00:00:00 2001\nFrom: Mateusz Kwiatkowski <kfyatek+publicgit@gmail.com>\nDate: Thu, 15 Jul 2021 01:08:05 +0200\nSubject: [PATCH] drm/vc4: Refactor mode checking logic\n\nReplace drm_encoder_helper_funcs::atomic_check with\ndrm_connector_helper_funcs::atomic_check - the former is not called\nduring drm_mode_obj_set_property_ioctl(). Set crtc_state->mode_changed\nif TV norm changes even without explicit mode change. This makes things\nlike \"xrandr --output Composite-1 --set mode PAL-M\" work properly.\n\nSigned-off-by: Mateusz Kwiatkowski <kfyatek+publicgit@gmail.com>\n---\n drivers/gpu/drm/vc4/vc4_vec.c | 42 ++++++++++++++++++++++-------------\n 1 file changed, 26 insertions(+), 16 deletions(-)\n\n--- a/drivers/gpu/drm/vc4/vc4_vec.c\n+++ b/drivers/gpu/drm/vc4/vc4_vec.c\n@@ -421,6 +421,31 @@ static void vc4_vec_connector_reset(stru\n \t\tconnector->state->tv.mode = vc4_vec_get_default_mode(connector);\n }\n \n+static int vc4_vec_connector_atomic_check(struct drm_connector *conn,\n+\t\t\t\t\t  struct drm_atomic_state *state)\n+{\n+\tstruct drm_connector_state *old_state =\n+\t\tdrm_atomic_get_old_connector_state(state, conn);\n+\tstruct drm_connector_state *new_state =\n+\t\tdrm_atomic_get_new_connector_state(state, conn);\n+\n+\tconst struct vc4_vec_tv_mode *vec_mode =\n+\t\t&vc4_vec_tv_modes[new_state->tv.mode];\n+\n+\tif (new_state->crtc) {\n+\t\tstruct drm_crtc_state *crtc_state =\n+\t\t\tdrm_atomic_get_new_crtc_state(state, new_state->crtc);\n+\n+\t\tif (!drm_mode_equal(vec_mode->mode, &crtc_state->mode))\n+\t\t\treturn -EINVAL;\n+\n+\t\tif (old_state->tv.mode != new_state->tv.mode)\n+\t\t\tcrtc_state->mode_changed = true;\n+\t}\n+\n+\treturn 0;\n+}\n+\n static const struct drm_connector_funcs vc4_vec_connector_funcs = {\n \t.detect = vc4_vec_connector_detect,\n \t.fill_modes = drm_helper_probe_single_connector_modes,\n@@ -432,6 +457,7 @@ static const struct drm_connector_funcs\n \n static const struct drm_connector_helper_funcs vc4_vec_connector_helper_funcs = {\n \t.get_modes = vc4_vec_connector_get_modes,\n+\t.atomic_check = vc4_vec_connector_atomic_check,\n };\n \n static struct drm_connector *vc4_vec_connector_init(struct drm_device *dev,\n@@ -569,26 +595,10 @@ static bool vc4_vec_encoder_mode_fixup(s\n \treturn true;\n }\n \n-static int vc4_vec_encoder_atomic_check(struct drm_encoder *encoder,\n-\t\t\t\t\tstruct drm_crtc_state *crtc_state,\n-\t\t\t\t\tstruct drm_connector_state *conn_state)\n-{\n-\tconst struct vc4_vec_tv_mode *vec_mode;\n-\n-\tvec_mode = &vc4_vec_tv_modes[conn_state->tv.mode];\n-\n-\tif (conn_state->crtc &&\n-\t    !drm_mode_equal(vec_mode->mode, &crtc_state->adjusted_mode))\n-\t\treturn -EINVAL;\n-\n-\treturn 0;\n-}\n-\n static const struct drm_encoder_helper_funcs vc4_vec_encoder_helper_funcs = {\n \t.disable = vc4_vec_encoder_disable,\n \t.enable = vc4_vec_encoder_enable,\n \t.mode_fixup = vc4_vec_encoder_mode_fixup,\n-\t.atomic_check = vc4_vec_encoder_atomic_check,\n };\n \n static const struct vc4_vec_variant bcm2835_vec_variant = {\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0705-drm-vc4-Fix-typo-when-getting-firmware-node.patch",
    "content": "From d53e26567315cab039c8ae67c4f5b807c9a498b1 Mon Sep 17 00:00:00 2001\nFrom: Dom Cobley <popcornmix@gmail.com>\nDate: Thu, 15 Jul 2021 20:08:13 +0100\nSubject: [PATCH] drm/vc4: Fix typo when getting firmware node\n\nSigned-off-by: Dom Cobley <popcornmix@gmail.com>\n---\n drivers/gpu/drm/vc4/vc4_drv.c | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/drivers/gpu/drm/vc4/vc4_drv.c\n+++ b/drivers/gpu/drm/vc4/vc4_drv.c\n@@ -321,7 +321,7 @@ static int vc4_drm_bind(struct device *d\n \n \tnode = of_parse_phandle(dev->of_node, \"raspberrypi,firmware\", 0);\n \tif (node) {\n-\t\tvc4->firmware = rpi_firmware_get(dev->of_node);\n+\t\tvc4->firmware = rpi_firmware_get(node);\n \t\tof_node_put(node);\n \n \t\tif (!vc4->firmware)\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0706-ARM-dts-bcm2711-Tidy-the-HDMI-I2C-aliases.patch",
    "content": "From fdde18c3416afd1e971ddee7a65f08bed9fd44a7 Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.com>\nDate: Mon, 19 Jul 2021 10:47:02 +0100\nSubject: [PATCH] ARM: dts: bcm2711: Tidy the HDMI I2C aliases\n\nThe bcm2711 vc3-kms-v3d overlay enables the I2C instances used for\nEDID data. Give these distinct I2C interface numbers (20 & 21) to\nclearly separate them from other regular I2C blocks (1, 3-6) and the\nmux on I2C0 (10+).\n\nThe 2711 DTS tree no longer includes i2c2, so the explicit deletion can\nbe removed.\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.com>\n---\n arch/arm/boot/dts/bcm2711-rpi-4-b.dts | 10 ++--------\n arch/arm/boot/dts/bcm2711-rpi-400.dts | 10 ++--------\n arch/arm/boot/dts/bcm2711-rpi-cm4.dts | 10 ++--------\n 3 files changed, 6 insertions(+), 24 deletions(-)\n\n--- a/arch/arm/boot/dts/bcm2711-rpi-4-b.dts\n+++ b/arch/arm/boot/dts/bcm2711-rpi-4-b.dts\n@@ -350,11 +350,12 @@\n \t\tmmc0 = &emmc2;\n \t\tmmc1 = &mmcnr;\n \t\tmmc2 = &sdhost;\n-\t\t/delete-property/ i2c2;\n \t\ti2c3 = &i2c3;\n \t\ti2c4 = &i2c4;\n \t\ti2c5 = &i2c5;\n \t\ti2c6 = &i2c6;\n+\t\ti2c20 = &ddc0;\n+\t\ti2c21 = &ddc1;\n \t\tspi3 = &spi3;\n \t\tspi4 = &spi4;\n \t\tspi5 = &spi5;\n@@ -560,13 +561,6 @@\n \tpinctrl-0 = <&i2s_pins>;\n };\n \n-/ {\n-\t__overrides__ {\n-\t\t/delete-property/ i2c2_baudrate;\n-\t\t/delete-property/ i2c2_iknowwhatimdoing;\n-\t};\n-};\n-\n // =============================================\n // Board specific stuff here\n \n--- a/arch/arm/boot/dts/bcm2711-rpi-400.dts\n+++ b/arch/arm/boot/dts/bcm2711-rpi-400.dts\n@@ -348,11 +348,12 @@\n \t\tmmc0 = &emmc2;\n \t\tmmc1 = &mmcnr;\n \t\tmmc2 = &sdhost;\n-\t\t/delete-property/ i2c2;\n \t\ti2c3 = &i2c3;\n \t\ti2c4 = &i2c4;\n \t\ti2c5 = &i2c5;\n \t\ti2c6 = &i2c6;\n+\t\ti2c20 = &ddc0;\n+\t\ti2c21 = &ddc1;\n \t\tspi3 = &spi3;\n \t\tspi4 = &spi4;\n \t\tspi5 = &spi5;\n@@ -558,13 +559,6 @@\n \tpinctrl-0 = <&i2s_pins>;\n };\n \n-/ {\n-\t__overrides__ {\n-\t\t/delete-property/ i2c2_baudrate;\n-\t\t/delete-property/ i2c2_iknowwhatimdoing;\n-\t};\n-};\n-\n // =============================================\n // Board specific stuff here\n \n--- a/arch/arm/boot/dts/bcm2711-rpi-cm4.dts\n+++ b/arch/arm/boot/dts/bcm2711-rpi-cm4.dts\n@@ -363,11 +363,12 @@\n \t\tmmc0 = &emmc2;\n \t\tmmc1 = &mmcnr;\n \t\tmmc2 = &sdhost;\n-\t\t/delete-property/ i2c2;\n \t\ti2c3 = &i2c3;\n \t\ti2c4 = &i2c4;\n \t\ti2c5 = &i2c5;\n \t\ti2c6 = &i2c6;\n+\t\ti2c20 = &ddc0;\n+\t\ti2c21 = &ddc1;\n \t\tspi3 = &spi3;\n \t\tspi4 = &spi4;\n \t\tspi5 = &spi5;\n@@ -573,13 +574,6 @@\n \tpinctrl-0 = <&i2s_pins>;\n };\n \n-/ {\n-\t__overrides__ {\n-\t\t/delete-property/ i2c2_baudrate;\n-\t\t/delete-property/ i2c2_iknowwhatimdoing;\n-\t};\n-};\n-\n // =============================================\n // Board specific stuff here\n \n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0707-media-i2c-imx477-Fix-framerates-for-1332x990-mode.patch",
    "content": "From 184e61559e917f70f5d10c96a43055c0891504b0 Mon Sep 17 00:00:00 2001\nFrom: David Plowman <david.plowman@raspberrypi.com>\nDate: Tue, 20 Jul 2021 15:10:03 +0100\nSubject: [PATCH] media: i2c: imx477: Fix framerates for 1332x990 mode\n\nThe imx477 driver's line length for this mode had not been updated to\nthe value supplied to us by the sensor manufacturer. With this\ncorrection the sensor delivers the framerates that are expected.\n\nSigned-off-by: David Plowman <david.plowman@raspberrypi.com>\n---\n drivers/media/i2c/imx477.c | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/drivers/media/i2c/imx477.c\n+++ b/drivers/media/i2c/imx477.c\n@@ -982,7 +982,7 @@ static const struct imx477_mode supporte\n \t\t/* 120fps. 2x2 binned and cropped */\n \t\t.width = 1332,\n \t\t.height = 990,\n-\t\t.line_length_pix = 0x1460,\n+\t\t.line_length_pix = 6664,\n \t\t.crop = {\n \t\t\t/*\n \t\t\t * FIXME: the analog crop rectangle is actually\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0708-drm-uapi-Add-USB-connector-type.patch",
    "content": "From 6e2988c88939fdd70e6a456bdd7ad65fcdcf97c7 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Noralf=20Tr=C3=B8nnes?= <noralf@tronnes.org>\nDate: Sat, 13 Mar 2021 12:25:43 +0100\nSubject: [PATCH] drm/uapi: Add USB connector type\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\n[ Upstream commit 757e26712337be6be70f7405c38cc0639957eedc ]\n\nAdd a connector type for USB connected display panels.\n\nSome examples of what current userspace will name the connector:\n- Weston: \"UNNAMED-%d\"\n- Mutter: \"Unknown20-%d\"\n- X: \"Unknown20-%d\"\n\nv2:\n- Update drm_connector_enum_list\n- Add examples to commit message\n\nAcked-by: Daniel Vetter <daniel.vetter@ffwll.ch>\nSigned-off-by: Noralf Trønnes <noralf@tronnes.org>\nLink: https://patchwork.freedesktop.org/patch/msgid/20210313112545.37527-2-noralf@tronnes.org\n---\n drivers/gpu/drm/drm_connector.c | 1 +\n include/uapi/drm/drm_mode.h     | 1 +\n 2 files changed, 2 insertions(+)\n\n--- a/drivers/gpu/drm/drm_connector.c\n+++ b/drivers/gpu/drm/drm_connector.c\n@@ -94,6 +94,7 @@ static struct drm_conn_prop_enum_list dr\n \t{ DRM_MODE_CONNECTOR_DPI, \"DPI\" },\n \t{ DRM_MODE_CONNECTOR_WRITEBACK, \"Writeback\" },\n \t{ DRM_MODE_CONNECTOR_SPI, \"SPI\" },\n+\t{ DRM_MODE_CONNECTOR_USB, \"USB\" },\n };\n \n void drm_connector_ida_init(void)\n--- a/include/uapi/drm/drm_mode.h\n+++ b/include/uapi/drm/drm_mode.h\n@@ -367,6 +367,7 @@ enum drm_mode_subconnector {\n #define DRM_MODE_CONNECTOR_DPI\t\t17\n #define DRM_MODE_CONNECTOR_WRITEBACK\t18\n #define DRM_MODE_CONNECTOR_SPI\t\t19\n+#define DRM_MODE_CONNECTOR_USB\t\t20\n \n struct drm_mode_get_connector {\n \n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0709-drm-Add-GUD-USB-Display-driver.patch",
    "content": "From 140a4e12d8ec470fe0807931893d3d48ffda46b3 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Noralf=20Tr=C3=B8nnes?= <noralf@tronnes.org>\nDate: Sat, 13 Mar 2021 12:25:45 +0100\nSubject: [PATCH] drm: Add GUD USB Display driver\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\n[ Upstream commit 40e1a70b4aedf2859a1829991b48ef0ebe650bf2 ]\n\nThis adds a USB display driver with the intention that it can be\nused with future USB interfaced low end displays/adapters. The Linux\ngadget device driver will serve as the canonical device implementation.\n\nThe following DRM properties are supported:\n- Plane rotation\n- Connector TV properties\n\nThere is also support for backlight brightness exposed as a backlight\ndevice.\n\nDisplay modes can be made available to the host driver either as DRM\ndisplay modes or through EDID. If both are present, EDID is just passed\non to userspace.\n\nPerformance is preferred over color depth, so if the device supports\nRGB565, DRM_CAP_DUMB_PREFERRED_DEPTH will return 16.\n\nIf the device transfer buffer can't fit an uncompressed framebuffer\nupdate, the update is split up into parts that do fit.\n\nOptimal user experience is achieved by providing damage reports either by\nsetting FB_DAMAGE_CLIPS on pageflips or calling DRM_IOCTL_MODE_DIRTYFB.\n\nLZ4 compression is used if the device supports it.\n\nThe driver supports a one bit monochrome transfer format: R1. This is not\nimplemented in the gadget driver. It is added in preparation for future\nmonochrome e-ink displays.\n\nThe driver is MIT licensed to smooth the path for any BSD port of the\ndriver.\n\nv2:\n- Use devm_drm_dev_alloc() and drmm_mode_config_init()\n- drm_fbdev_generic_setup: Use preferred_bpp=0, 16 was a copy paste error\n- The drm_backlight_helper is dropped, copy in the code\n- Support protocol version backwards compatibility for device\n\nv3:\n- Use donated Openmoko USB pid\n- Use direct compression from framebuffer when pitch matches, not only on\n  full frames, so split updates can benefit\n- Use __le16 in struct gud_drm_req_get_connector_status\n- Set edid property when the device only provides edid\n- Clear compression fields in struct gud_drm_req_set_buffer\n- Fix protocol version negotiation\n- Remove mode->vrefresh, it's calculated\n\nv4:\n- Drop the status req polling which was a workaround for something that\n  turned out to be a dwc2 udc driver problem\n- Add a flag for the Linux gadget to require a status request on\n  SET operations. Other devices will only get status req on STALL errors\n- Use protocol specific error codes (Peter)\n- Add a flag for devices that want to receive the entire framebuffer on\n  each flush (Lubomir)\n- Retry a failed framebuffer flush\n- If mode has changed wait for worker and clear pending damage before\n  queuing up new damage, fb width/height might have changed\n- Increase error counter on bulk transfer failures\n- Use DRM_MODE_CONNECTOR_USB\n- Handle R1 kmalloc error (Peter)\n- Don't try and replicate the USB get descriptor request standard for the\n  display descriptor (Peter)\n- Make max_buffer_size optional (Peter), drop the pow2 requirement since\n  it's not necessary anymore.\n- Don't pre-alloc a control request buffer, it was only 4k\n- Let gud.h describe the whole protocol explicitly and don't let DRM\n  leak into it (Peter)\n- Drop display mode .hskew and .vscan from the protocol\n- Shorten names: s/GUD_DRM_/GUD_/ s/gud_drm_/gud_/ (Peter)\n- Fix gud_pipe_check() connector picking when switching connector\n- Drop gud_drm_driver_gem_create_object() cached is default now\n- Retrieve USB device from struct drm_device.dev instead of keeping a\n  pointer\n- Honour fb->offsets[0]\n- Fix mode fetching when connector status is forced\n- Check EDID length reported by the device\n- Use drm_do_get_edid() so userspace can overrride EDID\n- Set epoch counter to signal connector status change\n- gud_drm_driver can be const now\n\nv5:\n- GUD_DRM_FORMAT_R1: Use non-human ascii values (Daniel)\n- Change name to: GUD USB Display (Thomas, Simon)\n- Change one __u32 -> __le32 in protocol header\n- Always log fb flush errors, unless the previous one failed\n- Run backlight update in a worker to avoid upsetting lockdep (Daniel)\n- Drop backlight_ops.get_brightness, there's no readback from the device\n  so it doesn't really add anything.\n- Set dma mask, needed by dma-buf importers\n\nv6:\n- Use obj-y in Makefile (Peter)\n- Fix missing le32_to_cpu() when using GUD_DISPLAY_MAGIC (Peter)\n- Set initial brightness on backlight device\n\nv7:\n- LZ4_compress_default() can return zero, check for that\n- Fix memory leak in gud_pipe_check() error path (Peter)\n- Improve debug and error messages (Peter)\n- Don't pass length in protocol structs (Peter)\n- Pass USB interface to gud_usb_control_msg() et al. (Peter)\n- Improve gud_connector_fill_properties() (Peter)\n- Add GUD_PIXEL_FORMAT_RGB111 (Peter)\n- Remove GUD_REQ_SET_VERSION (Peter)\n- Fix DRM_IOCTL_MODE_OBJ_SETPROPERTY and the rotation property\n- Fix dma-buf import (Thomas)\n\nv8:\n- Forgot to filter RGB111 from reaching userspace\n- Handle a device that only returns unknown device properties (Peter)\n- s/GUD_PIXEL_FORMAT_RGB111/GUD_PIXEL_FORMAT_XRGB1111/ (Peter)\n- Fix R1 and XRGB1111 format conversion\n- Add FIXME about Big Endian being broken (Peter, Ilia)\n\nCc: Lubomir Rintel <lkundrak@v3.sk>\nAcked-by: Daniel Vetter <daniel.vetter@ffwll.ch>\nReviewed-by: Peter Stuge <peter@stuge.se>\nTested-by: Peter Stuge <peter@stuge.se>\nSigned-off-by: Noralf Trønnes <noralf@tronnes.org>\nLink: https://patchwork.freedesktop.org/patch/msgid/20210313112545.37527-4-noralf@tronnes.org\n[ backport changes:\n  - Remove include drm_gem_atomic_helper.h\n  - s/drm_gem_simple_display_pipe_prepare_fb/drm_gem_fb_simple_display_pipe_prepare_fb/\n  - Remove const from gud_drm_driver\n  - Change drm_gem_shmem_{vmap,vunmap} signatures\n  - Add gud_gem_create_object() to get cached memory mapping.\n]\nSigned-off-by: Noralf Trønnes <noralf@tronnes.org>\n---\n MAINTAINERS                         |   8 +\n drivers/gpu/drm/Kconfig             |   2 +\n drivers/gpu/drm/Makefile            |   1 +\n drivers/gpu/drm/gud/Kconfig         |  14 +\n drivers/gpu/drm/gud/Makefile        |   4 +\n drivers/gpu/drm/gud/gud_connector.c | 729 ++++++++++++++++++++++++++++\n drivers/gpu/drm/gud/gud_drv.c       | 674 +++++++++++++++++++++++++\n drivers/gpu/drm/gud/gud_internal.h  | 154 ++++++\n drivers/gpu/drm/gud/gud_pipe.c      | 551 +++++++++++++++++++++\n include/drm/gud.h                   | 333 +++++++++++++\n 10 files changed, 2470 insertions(+)\n create mode 100644 drivers/gpu/drm/gud/Kconfig\n create mode 100644 drivers/gpu/drm/gud/Makefile\n create mode 100644 drivers/gpu/drm/gud/gud_connector.c\n create mode 100644 drivers/gpu/drm/gud/gud_drv.c\n create mode 100644 drivers/gpu/drm/gud/gud_internal.h\n create mode 100644 drivers/gpu/drm/gud/gud_pipe.c\n create mode 100644 include/drm/gud.h\n\n--- a/MAINTAINERS\n+++ b/MAINTAINERS\n@@ -5526,6 +5526,14 @@ S:\tMaintained\n F:\tDocumentation/devicetree/bindings/display/panel/feiyang,fy07024di26a30d.yaml\n F:\tdrivers/gpu/drm/panel/panel-feiyang-fy07024di26a30d.c\n \n+DRM DRIVER FOR GENERIC USB DISPLAY\n+M:\tNoralf Trønnes <noralf@tronnes.org>\n+S:\tMaintained\n+W:\thttps://github.com/notro/gud/wiki\n+T:\tgit git://anongit.freedesktop.org/drm/drm-misc\n+F:\tdrivers/gpu/drm/gud/\n+F:\tinclude/drm/gud.h\n+\n DRM DRIVER FOR GRAIN MEDIA GM12U320 PROJECTORS\n M:\tHans de Goede <hdegoede@redhat.com>\n S:\tMaintained\n--- a/drivers/gpu/drm/Kconfig\n+++ b/drivers/gpu/drm/Kconfig\n@@ -392,6 +392,8 @@ source \"drivers/gpu/drm/tidss/Kconfig\"\n \n source \"drivers/gpu/drm/xlnx/Kconfig\"\n \n+source \"drivers/gpu/drm/gud/Kconfig\"\n+\n # Keep legacy drivers last\n \n menuconfig DRM_LEGACY\n--- a/drivers/gpu/drm/Makefile\n+++ b/drivers/gpu/drm/Makefile\n@@ -124,3 +124,4 @@ obj-$(CONFIG_DRM_ASPEED_GFX) += aspeed/\n obj-$(CONFIG_DRM_MCDE) += mcde/\n obj-$(CONFIG_DRM_TIDSS) += tidss/\n obj-y\t\t\t+= xlnx/\n+obj-y\t\t\t+= gud/\n--- /dev/null\n+++ b/drivers/gpu/drm/gud/Kconfig\n@@ -0,0 +1,14 @@\n+# SPDX-License-Identifier: GPL-2.0\n+\n+config DRM_GUD\n+\ttristate \"GUD USB Display\"\n+\tdepends on DRM && USB\n+\tselect LZ4_COMPRESS\n+\tselect DRM_KMS_HELPER\n+\tselect DRM_GEM_SHMEM_HELPER\n+\tselect BACKLIGHT_CLASS_DEVICE\n+\thelp\n+\t  This is a DRM display driver for GUD USB Displays or display\n+\t  adapters.\n+\n+\t  If M is selected the module will be called gud.\n--- /dev/null\n+++ b/drivers/gpu/drm/gud/Makefile\n@@ -0,0 +1,4 @@\n+# SPDX-License-Identifier: GPL-2.0\n+\n+gud-y\t\t\t\t:= gud_drv.o gud_pipe.o gud_connector.o\n+obj-$(CONFIG_DRM_GUD)\t\t+= gud.o\n--- /dev/null\n+++ b/drivers/gpu/drm/gud/gud_connector.c\n@@ -0,0 +1,729 @@\n+// SPDX-License-Identifier: MIT\n+/*\n+ * Copyright 2020 Noralf Trønnes\n+ */\n+\n+#include <linux/backlight.h>\n+#include <linux/workqueue.h>\n+\n+#include <drm/drm_atomic.h>\n+#include <drm/drm_atomic_state_helper.h>\n+#include <drm/drm_connector.h>\n+#include <drm/drm_drv.h>\n+#include <drm/drm_encoder.h>\n+#include <drm/drm_file.h>\n+#include <drm/drm_modeset_helper_vtables.h>\n+#include <drm/drm_print.h>\n+#include <drm/drm_probe_helper.h>\n+#include <drm/drm_simple_kms_helper.h>\n+#include <drm/gud.h>\n+\n+#include \"gud_internal.h\"\n+\n+struct gud_connector {\n+\tstruct drm_connector connector;\n+\tstruct drm_encoder encoder;\n+\tstruct backlight_device *backlight;\n+\tstruct work_struct backlight_work;\n+\n+\t/* Supported properties */\n+\tu16 *properties;\n+\tunsigned int num_properties;\n+\n+\t/* Initial gadget tv state if applicable, applied on state reset */\n+\tstruct drm_tv_connector_state initial_tv_state;\n+\n+\t/*\n+\t * Initial gadget backlight brightness if applicable, applied on state reset.\n+\t * The value -ENODEV is used to signal no backlight.\n+\t */\n+\tint initial_brightness;\n+};\n+\n+static inline struct gud_connector *to_gud_connector(struct drm_connector *connector)\n+{\n+\treturn container_of(connector, struct gud_connector, connector);\n+}\n+\n+static void gud_conn_err(struct drm_connector *connector, const char *msg, int ret)\n+{\n+\tdev_err(connector->dev->dev, \"%s: %s (ret=%d)\\n\", connector->name, msg, ret);\n+}\n+\n+/*\n+ * Use a worker to avoid taking kms locks inside the backlight lock.\n+ * Other display drivers use backlight within their kms locks.\n+ * This avoids inconsistent locking rules, which would upset lockdep.\n+ */\n+static void gud_connector_backlight_update_status_work(struct work_struct *work)\n+{\n+\tstruct gud_connector *gconn = container_of(work, struct gud_connector, backlight_work);\n+\tstruct drm_connector *connector = &gconn->connector;\n+\tstruct drm_connector_state *connector_state;\n+\tstruct drm_device *drm = connector->dev;\n+\tstruct drm_modeset_acquire_ctx ctx;\n+\tstruct drm_atomic_state *state;\n+\tint idx, ret;\n+\n+\tif (!drm_dev_enter(drm, &idx))\n+\t\treturn;\n+\n+\tstate = drm_atomic_state_alloc(drm);\n+\tif (!state) {\n+\t\tret = -ENOMEM;\n+\t\tgoto exit;\n+\t}\n+\n+\tdrm_modeset_acquire_init(&ctx, 0);\n+\tstate->acquire_ctx = &ctx;\n+retry:\n+\tconnector_state = drm_atomic_get_connector_state(state, connector);\n+\tif (IS_ERR(connector_state)) {\n+\t\tret = PTR_ERR(connector_state);\n+\t\tgoto out;\n+\t}\n+\n+\t/* Reuse tv.brightness to avoid having to subclass */\n+\tconnector_state->tv.brightness = gconn->backlight->props.brightness;\n+\n+\tret = drm_atomic_commit(state);\n+out:\n+\tif (ret == -EDEADLK) {\n+\t\tdrm_atomic_state_clear(state);\n+\t\tdrm_modeset_backoff(&ctx);\n+\t\tgoto retry;\n+\t}\n+\n+\tdrm_atomic_state_put(state);\n+\n+\tdrm_modeset_drop_locks(&ctx);\n+\tdrm_modeset_acquire_fini(&ctx);\n+exit:\n+\tdrm_dev_exit(idx);\n+\n+\tif (ret)\n+\t\tdev_err(drm->dev, \"Failed to update backlight, err=%d\\n\", ret);\n+}\n+\n+static int gud_connector_backlight_update_status(struct backlight_device *bd)\n+{\n+\tstruct drm_connector *connector = bl_get_data(bd);\n+\tstruct gud_connector *gconn = to_gud_connector(connector);\n+\n+\t/* The USB timeout is 5 seconds so use system_long_wq for worst case scenario */\n+\tqueue_work(system_long_wq, &gconn->backlight_work);\n+\n+\treturn 0;\n+}\n+\n+static const struct backlight_ops gud_connector_backlight_ops = {\n+\t.update_status\t= gud_connector_backlight_update_status,\n+};\n+\n+static int gud_connector_backlight_register(struct gud_connector *gconn)\n+{\n+\tstruct drm_connector *connector = &gconn->connector;\n+\tstruct backlight_device *bd;\n+\tconst char *name;\n+\tconst struct backlight_properties props = {\n+\t\t.type = BACKLIGHT_RAW,\n+\t\t.scale = BACKLIGHT_SCALE_NON_LINEAR,\n+\t\t.max_brightness = 100,\n+\t\t.brightness = gconn->initial_brightness,\n+\t};\n+\n+\tname = kasprintf(GFP_KERNEL, \"card%d-%s-backlight\",\n+\t\t\t connector->dev->primary->index, connector->name);\n+\tif (!name)\n+\t\treturn -ENOMEM;\n+\n+\tbd = backlight_device_register(name, connector->kdev, connector,\n+\t\t\t\t       &gud_connector_backlight_ops, &props);\n+\tkfree(name);\n+\tif (IS_ERR(bd))\n+\t\treturn PTR_ERR(bd);\n+\n+\tgconn->backlight = bd;\n+\n+\treturn 0;\n+}\n+\n+static int gud_connector_detect(struct drm_connector *connector,\n+\t\t\t\tstruct drm_modeset_acquire_ctx *ctx, bool force)\n+{\n+\tstruct gud_device *gdrm = to_gud_device(connector->dev);\n+\tint idx, ret;\n+\tu8 status;\n+\n+\tif (!drm_dev_enter(connector->dev, &idx))\n+\t\treturn connector_status_disconnected;\n+\n+\tif (force) {\n+\t\tret = gud_usb_set(gdrm, GUD_REQ_SET_CONNECTOR_FORCE_DETECT,\n+\t\t\t\t  connector->index, NULL, 0);\n+\t\tif (ret) {\n+\t\t\tret = connector_status_unknown;\n+\t\t\tgoto exit;\n+\t\t}\n+\t}\n+\n+\tret = gud_usb_get_u8(gdrm, GUD_REQ_GET_CONNECTOR_STATUS, connector->index, &status);\n+\tif (ret) {\n+\t\tret = connector_status_unknown;\n+\t\tgoto exit;\n+\t}\n+\n+\tswitch (status & GUD_CONNECTOR_STATUS_CONNECTED_MASK) {\n+\tcase GUD_CONNECTOR_STATUS_DISCONNECTED:\n+\t\tret = connector_status_disconnected;\n+\t\tbreak;\n+\tcase GUD_CONNECTOR_STATUS_CONNECTED:\n+\t\tret = connector_status_connected;\n+\t\tbreak;\n+\tdefault:\n+\t\tret = connector_status_unknown;\n+\t\tbreak;\n+\t};\n+\n+\tif (status & GUD_CONNECTOR_STATUS_CHANGED)\n+\t\tconnector->epoch_counter += 1;\n+exit:\n+\tdrm_dev_exit(idx);\n+\n+\treturn ret;\n+}\n+\n+struct gud_connector_get_edid_ctx {\n+\tvoid *buf;\n+\tsize_t len;\n+\tbool edid_override;\n+};\n+\n+static int gud_connector_get_edid_block(void *data, u8 *buf, unsigned int block, size_t len)\n+{\n+\tstruct gud_connector_get_edid_ctx *ctx = data;\n+\tsize_t start = block * EDID_LENGTH;\n+\n+\tctx->edid_override = false;\n+\n+\tif (start + len > ctx->len)\n+\t\treturn -1;\n+\n+\tmemcpy(buf, ctx->buf + start, len);\n+\n+\treturn 0;\n+}\n+\n+static int gud_connector_get_modes(struct drm_connector *connector)\n+{\n+\tstruct gud_device *gdrm = to_gud_device(connector->dev);\n+\tstruct gud_display_mode_req *reqmodes = NULL;\n+\tstruct gud_connector_get_edid_ctx edid_ctx;\n+\tunsigned int i, num_modes = 0;\n+\tstruct edid *edid = NULL;\n+\tint idx, ret;\n+\n+\tif (!drm_dev_enter(connector->dev, &idx))\n+\t\treturn 0;\n+\n+\tedid_ctx.edid_override = true;\n+\tedid_ctx.buf = kmalloc(GUD_CONNECTOR_MAX_EDID_LEN, GFP_KERNEL);\n+\tif (!edid_ctx.buf)\n+\t\tgoto out;\n+\n+\tret = gud_usb_get(gdrm, GUD_REQ_GET_CONNECTOR_EDID, connector->index,\n+\t\t\t  edid_ctx.buf, GUD_CONNECTOR_MAX_EDID_LEN);\n+\tif (ret > 0 && ret % EDID_LENGTH) {\n+\t\tgud_conn_err(connector, \"Invalid EDID size\", ret);\n+\t} else if (ret > 0) {\n+\t\tedid_ctx.len = ret;\n+\t\tedid = drm_do_get_edid(connector, gud_connector_get_edid_block, &edid_ctx);\n+\t}\n+\n+\tkfree(edid_ctx.buf);\n+\tdrm_connector_update_edid_property(connector, edid);\n+\n+\tif (edid && edid_ctx.edid_override)\n+\t\tgoto out;\n+\n+\treqmodes = kmalloc_array(GUD_CONNECTOR_MAX_NUM_MODES, sizeof(*reqmodes), GFP_KERNEL);\n+\tif (!reqmodes)\n+\t\tgoto out;\n+\n+\tret = gud_usb_get(gdrm, GUD_REQ_GET_CONNECTOR_MODES, connector->index,\n+\t\t\t  reqmodes, GUD_CONNECTOR_MAX_NUM_MODES * sizeof(*reqmodes));\n+\tif (ret <= 0)\n+\t\tgoto out;\n+\tif (ret % sizeof(*reqmodes)) {\n+\t\tgud_conn_err(connector, \"Invalid display mode array size\", ret);\n+\t\tgoto out;\n+\t}\n+\n+\tnum_modes = ret / sizeof(*reqmodes);\n+\n+\tfor (i = 0; i < num_modes; i++) {\n+\t\tstruct drm_display_mode *mode;\n+\n+\t\tmode = drm_mode_create(connector->dev);\n+\t\tif (!mode) {\n+\t\t\tnum_modes = i;\n+\t\t\tgoto out;\n+\t\t}\n+\n+\t\tgud_to_display_mode(mode, &reqmodes[i]);\n+\t\tdrm_mode_probed_add(connector, mode);\n+\t}\n+out:\n+\tif (!num_modes)\n+\t\tnum_modes = drm_add_edid_modes(connector, edid);\n+\n+\tkfree(reqmodes);\n+\tkfree(edid);\n+\tdrm_dev_exit(idx);\n+\n+\treturn num_modes;\n+}\n+\n+static int gud_connector_atomic_check(struct drm_connector *connector,\n+\t\t\t\t      struct drm_atomic_state *state)\n+{\n+\tstruct drm_connector_state *new_state;\n+\tstruct drm_crtc_state *new_crtc_state;\n+\tstruct drm_connector_state *old_state;\n+\n+\tnew_state = drm_atomic_get_new_connector_state(state, connector);\n+\tif (!new_state->crtc)\n+\t\treturn 0;\n+\n+\told_state = drm_atomic_get_old_connector_state(state, connector);\n+\tnew_crtc_state = drm_atomic_get_new_crtc_state(state, new_state->crtc);\n+\n+\tif (old_state->tv.margins.left != new_state->tv.margins.left ||\n+\t    old_state->tv.margins.right != new_state->tv.margins.right ||\n+\t    old_state->tv.margins.top != new_state->tv.margins.top ||\n+\t    old_state->tv.margins.bottom != new_state->tv.margins.bottom ||\n+\t    old_state->tv.mode != new_state->tv.mode ||\n+\t    old_state->tv.brightness != new_state->tv.brightness ||\n+\t    old_state->tv.contrast != new_state->tv.contrast ||\n+\t    old_state->tv.flicker_reduction != new_state->tv.flicker_reduction ||\n+\t    old_state->tv.overscan != new_state->tv.overscan ||\n+\t    old_state->tv.saturation != new_state->tv.saturation ||\n+\t    old_state->tv.hue != new_state->tv.hue)\n+\t\tnew_crtc_state->connectors_changed = true;\n+\n+\treturn 0;\n+}\n+\n+static const struct drm_connector_helper_funcs gud_connector_helper_funcs = {\n+\t.detect_ctx = gud_connector_detect,\n+\t.get_modes = gud_connector_get_modes,\n+\t.atomic_check = gud_connector_atomic_check,\n+};\n+\n+static int gud_connector_late_register(struct drm_connector *connector)\n+{\n+\tstruct gud_connector *gconn = to_gud_connector(connector);\n+\n+\tif (gconn->initial_brightness < 0)\n+\t\treturn 0;\n+\n+\treturn gud_connector_backlight_register(gconn);\n+}\n+\n+static void gud_connector_early_unregister(struct drm_connector *connector)\n+{\n+\tstruct gud_connector *gconn = to_gud_connector(connector);\n+\n+\tbacklight_device_unregister(gconn->backlight);\n+\tcancel_work_sync(&gconn->backlight_work);\n+}\n+\n+static void gud_connector_destroy(struct drm_connector *connector)\n+{\n+\tstruct gud_connector *gconn = to_gud_connector(connector);\n+\n+\tdrm_connector_cleanup(connector);\n+\tkfree(gconn->properties);\n+\tkfree(gconn);\n+}\n+\n+static void gud_connector_reset(struct drm_connector *connector)\n+{\n+\tstruct gud_connector *gconn = to_gud_connector(connector);\n+\n+\tdrm_atomic_helper_connector_reset(connector);\n+\tconnector->state->tv = gconn->initial_tv_state;\n+\t/* Set margins from command line */\n+\tdrm_atomic_helper_connector_tv_reset(connector);\n+\tif (gconn->initial_brightness >= 0)\n+\t\tconnector->state->tv.brightness = gconn->initial_brightness;\n+}\n+\n+static const struct drm_connector_funcs gud_connector_funcs = {\n+\t.fill_modes = drm_helper_probe_single_connector_modes,\n+\t.late_register = gud_connector_late_register,\n+\t.early_unregister = gud_connector_early_unregister,\n+\t.destroy = gud_connector_destroy,\n+\t.reset = gud_connector_reset,\n+\t.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,\n+\t.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,\n+};\n+\n+/*\n+ * The tv.mode property is shared among the connectors and its enum names are\n+ * driver specific. This means that if more than one connector uses tv.mode,\n+ * the enum names has to be the same.\n+ */\n+static int gud_connector_add_tv_mode(struct gud_device *gdrm, struct drm_connector *connector)\n+{\n+\tsize_t buf_len = GUD_CONNECTOR_TV_MODE_MAX_NUM * GUD_CONNECTOR_TV_MODE_NAME_LEN;\n+\tconst char *modes[GUD_CONNECTOR_TV_MODE_MAX_NUM];\n+\tunsigned int i, num_modes;\n+\tchar *buf;\n+\tint ret;\n+\n+\tbuf = kmalloc(buf_len, GFP_KERNEL);\n+\tif (!buf)\n+\t\treturn -ENOMEM;\n+\n+\tret = gud_usb_get(gdrm, GUD_REQ_GET_CONNECTOR_TV_MODE_VALUES,\n+\t\t\t  connector->index, buf, buf_len);\n+\tif (ret < 0)\n+\t\tgoto free;\n+\tif (!ret || ret % GUD_CONNECTOR_TV_MODE_NAME_LEN) {\n+\t\tret = -EIO;\n+\t\tgoto free;\n+\t}\n+\n+\tnum_modes = ret / GUD_CONNECTOR_TV_MODE_NAME_LEN;\n+\tfor (i = 0; i < num_modes; i++)\n+\t\tmodes[i] = &buf[i * GUD_CONNECTOR_TV_MODE_NAME_LEN];\n+\n+\tret = drm_mode_create_tv_properties(connector->dev, num_modes, modes);\n+free:\n+\tkfree(buf);\n+\tif (ret < 0)\n+\t\tgud_conn_err(connector, \"Failed to add TV modes\", ret);\n+\n+\treturn ret;\n+}\n+\n+static struct drm_property *\n+gud_connector_property_lookup(struct drm_connector *connector, u16 prop)\n+{\n+\tstruct drm_mode_config *config = &connector->dev->mode_config;\n+\n+\tswitch (prop) {\n+\tcase GUD_PROPERTY_TV_LEFT_MARGIN:\n+\t\treturn config->tv_left_margin_property;\n+\tcase GUD_PROPERTY_TV_RIGHT_MARGIN:\n+\t\treturn config->tv_right_margin_property;\n+\tcase GUD_PROPERTY_TV_TOP_MARGIN:\n+\t\treturn config->tv_top_margin_property;\n+\tcase GUD_PROPERTY_TV_BOTTOM_MARGIN:\n+\t\treturn config->tv_bottom_margin_property;\n+\tcase GUD_PROPERTY_TV_MODE:\n+\t\treturn config->tv_mode_property;\n+\tcase GUD_PROPERTY_TV_BRIGHTNESS:\n+\t\treturn config->tv_brightness_property;\n+\tcase GUD_PROPERTY_TV_CONTRAST:\n+\t\treturn config->tv_contrast_property;\n+\tcase GUD_PROPERTY_TV_FLICKER_REDUCTION:\n+\t\treturn config->tv_flicker_reduction_property;\n+\tcase GUD_PROPERTY_TV_OVERSCAN:\n+\t\treturn config->tv_overscan_property;\n+\tcase GUD_PROPERTY_TV_SATURATION:\n+\t\treturn config->tv_saturation_property;\n+\tcase GUD_PROPERTY_TV_HUE:\n+\t\treturn config->tv_hue_property;\n+\tdefault:\n+\t\treturn ERR_PTR(-EINVAL);\n+\t}\n+}\n+\n+static unsigned int *gud_connector_tv_state_val(u16 prop, struct drm_tv_connector_state *state)\n+{\n+\tswitch (prop) {\n+\tcase GUD_PROPERTY_TV_LEFT_MARGIN:\n+\t\treturn &state->margins.left;\n+\tcase GUD_PROPERTY_TV_RIGHT_MARGIN:\n+\t\treturn &state->margins.right;\n+\tcase GUD_PROPERTY_TV_TOP_MARGIN:\n+\t\treturn &state->margins.top;\n+\tcase GUD_PROPERTY_TV_BOTTOM_MARGIN:\n+\t\treturn &state->margins.bottom;\n+\tcase GUD_PROPERTY_TV_MODE:\n+\t\treturn &state->mode;\n+\tcase GUD_PROPERTY_TV_BRIGHTNESS:\n+\t\treturn &state->brightness;\n+\tcase GUD_PROPERTY_TV_CONTRAST:\n+\t\treturn &state->contrast;\n+\tcase GUD_PROPERTY_TV_FLICKER_REDUCTION:\n+\t\treturn &state->flicker_reduction;\n+\tcase GUD_PROPERTY_TV_OVERSCAN:\n+\t\treturn &state->overscan;\n+\tcase GUD_PROPERTY_TV_SATURATION:\n+\t\treturn &state->saturation;\n+\tcase GUD_PROPERTY_TV_HUE:\n+\t\treturn &state->hue;\n+\tdefault:\n+\t\treturn ERR_PTR(-EINVAL);\n+\t}\n+}\n+\n+static int gud_connector_add_properties(struct gud_device *gdrm, struct gud_connector *gconn)\n+{\n+\tstruct drm_connector *connector = &gconn->connector;\n+\tstruct drm_device *drm = &gdrm->drm;\n+\tstruct gud_property_req *properties;\n+\tunsigned int i, num_properties;\n+\tint ret;\n+\n+\tproperties = kcalloc(GUD_CONNECTOR_PROPERTIES_MAX_NUM, sizeof(*properties), GFP_KERNEL);\n+\tif (!properties)\n+\t\treturn -ENOMEM;\n+\n+\tret = gud_usb_get(gdrm, GUD_REQ_GET_CONNECTOR_PROPERTIES, connector->index,\n+\t\t\t  properties, GUD_CONNECTOR_PROPERTIES_MAX_NUM * sizeof(*properties));\n+\tif (ret <= 0)\n+\t\tgoto out;\n+\tif (ret % sizeof(*properties)) {\n+\t\tret = -EIO;\n+\t\tgoto out;\n+\t}\n+\n+\tnum_properties = ret / sizeof(*properties);\n+\tret = 0;\n+\n+\tgconn->properties = kcalloc(num_properties, sizeof(*gconn->properties), GFP_KERNEL);\n+\tif (!gconn->properties) {\n+\t\tret = -ENOMEM;\n+\t\tgoto out;\n+\t}\n+\n+\tfor (i = 0; i < num_properties; i++) {\n+\t\tu16 prop = le16_to_cpu(properties[i].prop);\n+\t\tu64 val = le64_to_cpu(properties[i].val);\n+\t\tstruct drm_property *property;\n+\t\tunsigned int *state_val;\n+\n+\t\tdrm_dbg(drm, \"property: %u = %llu(0x%llx)\\n\", prop, val, val);\n+\n+\t\tswitch (prop) {\n+\t\tcase GUD_PROPERTY_TV_LEFT_MARGIN:\n+\t\t\tfallthrough;\n+\t\tcase GUD_PROPERTY_TV_RIGHT_MARGIN:\n+\t\t\tfallthrough;\n+\t\tcase GUD_PROPERTY_TV_TOP_MARGIN:\n+\t\t\tfallthrough;\n+\t\tcase GUD_PROPERTY_TV_BOTTOM_MARGIN:\n+\t\t\tret = drm_mode_create_tv_margin_properties(drm);\n+\t\t\tif (ret)\n+\t\t\t\tgoto out;\n+\t\t\tbreak;\n+\t\tcase GUD_PROPERTY_TV_MODE:\n+\t\t\tret = gud_connector_add_tv_mode(gdrm, connector);\n+\t\t\tif (ret)\n+\t\t\t\tgoto out;\n+\t\t\tbreak;\n+\t\tcase GUD_PROPERTY_TV_BRIGHTNESS:\n+\t\t\tfallthrough;\n+\t\tcase GUD_PROPERTY_TV_CONTRAST:\n+\t\t\tfallthrough;\n+\t\tcase GUD_PROPERTY_TV_FLICKER_REDUCTION:\n+\t\t\tfallthrough;\n+\t\tcase GUD_PROPERTY_TV_OVERSCAN:\n+\t\t\tfallthrough;\n+\t\tcase GUD_PROPERTY_TV_SATURATION:\n+\t\t\tfallthrough;\n+\t\tcase GUD_PROPERTY_TV_HUE:\n+\t\t\t/* This is a no-op if already added. */\n+\t\t\tret = drm_mode_create_tv_properties(drm, 0, NULL);\n+\t\t\tif (ret)\n+\t\t\t\tgoto out;\n+\t\t\tbreak;\n+\t\tcase GUD_PROPERTY_BACKLIGHT_BRIGHTNESS:\n+\t\t\tif (val > 100) {\n+\t\t\t\tret = -EINVAL;\n+\t\t\t\tgoto out;\n+\t\t\t}\n+\t\t\tgconn->initial_brightness = val;\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\t/* New ones might show up in future devices, skip those we don't know. */\n+\t\t\tdrm_dbg(drm, \"Ignoring unknown property: %u\\n\", prop);\n+\t\t\tcontinue;\n+\t\t}\n+\n+\t\tgconn->properties[gconn->num_properties++] = prop;\n+\n+\t\tif (prop == GUD_PROPERTY_BACKLIGHT_BRIGHTNESS)\n+\t\t\tcontinue; /* not a DRM property */\n+\n+\t\tproperty = gud_connector_property_lookup(connector, prop);\n+\t\tif (WARN_ON(IS_ERR(property)))\n+\t\t\tcontinue;\n+\n+\t\tstate_val = gud_connector_tv_state_val(prop, &gconn->initial_tv_state);\n+\t\tif (WARN_ON(IS_ERR(state_val)))\n+\t\t\tcontinue;\n+\n+\t\t*state_val = val;\n+\t\tdrm_object_attach_property(&connector->base, property, 0);\n+\t}\n+out:\n+\tkfree(properties);\n+\n+\treturn ret;\n+}\n+\n+int gud_connector_fill_properties(struct drm_connector_state *connector_state,\n+\t\t\t\t  struct gud_property_req *properties)\n+{\n+\tstruct gud_connector *gconn = to_gud_connector(connector_state->connector);\n+\tunsigned int i;\n+\n+\tfor (i = 0; i < gconn->num_properties; i++) {\n+\t\tu16 prop = gconn->properties[i];\n+\t\tu64 val;\n+\n+\t\tif (prop == GUD_PROPERTY_BACKLIGHT_BRIGHTNESS) {\n+\t\t\tval = connector_state->tv.brightness;\n+\t\t} else {\n+\t\t\tunsigned int *state_val;\n+\n+\t\t\tstate_val = gud_connector_tv_state_val(prop, &connector_state->tv);\n+\t\t\tif (WARN_ON_ONCE(IS_ERR(state_val)))\n+\t\t\t\treturn PTR_ERR(state_val);\n+\n+\t\t\tval = *state_val;\n+\t\t}\n+\n+\t\tproperties[i].prop = cpu_to_le16(prop);\n+\t\tproperties[i].val = cpu_to_le64(val);\n+\t}\n+\n+\treturn gconn->num_properties;\n+}\n+\n+static int gud_connector_create(struct gud_device *gdrm, unsigned int index,\n+\t\t\t\tstruct gud_connector_descriptor_req *desc)\n+{\n+\tstruct drm_device *drm = &gdrm->drm;\n+\tstruct gud_connector *gconn;\n+\tstruct drm_connector *connector;\n+\tstruct drm_encoder *encoder;\n+\tint ret, connector_type;\n+\tu32 flags;\n+\n+\tgconn = kzalloc(sizeof(*gconn), GFP_KERNEL);\n+\tif (!gconn)\n+\t\treturn -ENOMEM;\n+\n+\tINIT_WORK(&gconn->backlight_work, gud_connector_backlight_update_status_work);\n+\tgconn->initial_brightness = -ENODEV;\n+\tflags = le32_to_cpu(desc->flags);\n+\tconnector = &gconn->connector;\n+\n+\tdrm_dbg(drm, \"Connector: index=%u type=%u flags=0x%x\\n\", index, desc->connector_type, flags);\n+\n+\tswitch (desc->connector_type) {\n+\tcase GUD_CONNECTOR_TYPE_PANEL:\n+\t\tconnector_type = DRM_MODE_CONNECTOR_USB;\n+\t\tbreak;\n+\tcase GUD_CONNECTOR_TYPE_VGA:\n+\t\tconnector_type = DRM_MODE_CONNECTOR_VGA;\n+\t\tbreak;\n+\tcase GUD_CONNECTOR_TYPE_DVI:\n+\t\tconnector_type = DRM_MODE_CONNECTOR_DVID;\n+\t\tbreak;\n+\tcase GUD_CONNECTOR_TYPE_COMPOSITE:\n+\t\tconnector_type = DRM_MODE_CONNECTOR_Composite;\n+\t\tbreak;\n+\tcase GUD_CONNECTOR_TYPE_SVIDEO:\n+\t\tconnector_type = DRM_MODE_CONNECTOR_SVIDEO;\n+\t\tbreak;\n+\tcase GUD_CONNECTOR_TYPE_COMPONENT:\n+\t\tconnector_type = DRM_MODE_CONNECTOR_Component;\n+\t\tbreak;\n+\tcase GUD_CONNECTOR_TYPE_DISPLAYPORT:\n+\t\tconnector_type = DRM_MODE_CONNECTOR_DisplayPort;\n+\t\tbreak;\n+\tcase GUD_CONNECTOR_TYPE_HDMI:\n+\t\tconnector_type = DRM_MODE_CONNECTOR_HDMIA;\n+\t\tbreak;\n+\tdefault: /* future types */\n+\t\tconnector_type = DRM_MODE_CONNECTOR_USB;\n+\t\tbreak;\n+\t};\n+\n+\tdrm_connector_helper_add(connector, &gud_connector_helper_funcs);\n+\tret = drm_connector_init(drm, connector, &gud_connector_funcs, connector_type);\n+\tif (ret) {\n+\t\tkfree(connector);\n+\t\treturn ret;\n+\t}\n+\n+\tif (WARN_ON(connector->index != index))\n+\t\treturn -EINVAL;\n+\n+\tif (flags & GUD_CONNECTOR_FLAGS_POLL_STATUS)\n+\t\tconnector->polled = (DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT);\n+\tif (flags & GUD_CONNECTOR_FLAGS_INTERLACE)\n+\t\tconnector->interlace_allowed = true;\n+\tif (flags & GUD_CONNECTOR_FLAGS_DOUBLESCAN)\n+\t\tconnector->doublescan_allowed = true;\n+\n+\tret = gud_connector_add_properties(gdrm, gconn);\n+\tif (ret) {\n+\t\tgud_conn_err(connector, \"Failed to add properties\", ret);\n+\t\treturn ret;\n+\t}\n+\n+\t/* The first connector is attached to the existing simple pipe encoder */\n+\tif (!connector->index) {\n+\t\tencoder = &gdrm->pipe.encoder;\n+\t} else {\n+\t\tencoder = &gconn->encoder;\n+\n+\t\tret = drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_NONE);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\n+\t\tencoder->possible_crtcs = 1;\n+\t}\n+\n+\treturn drm_connector_attach_encoder(connector, encoder);\n+}\n+\n+int gud_get_connectors(struct gud_device *gdrm)\n+{\n+\tstruct gud_connector_descriptor_req *descs;\n+\tunsigned int i, num_connectors;\n+\tint ret;\n+\n+\tdescs = kmalloc_array(GUD_CONNECTORS_MAX_NUM, sizeof(*descs), GFP_KERNEL);\n+\tif (!descs)\n+\t\treturn -ENOMEM;\n+\n+\tret = gud_usb_get(gdrm, GUD_REQ_GET_CONNECTORS, 0,\n+\t\t\t  descs, GUD_CONNECTORS_MAX_NUM * sizeof(descs));\n+\tif (ret < 0)\n+\t\tgoto free;\n+\tif (!ret || ret % sizeof(*descs)) {\n+\t\tret = -EIO;\n+\t\tgoto free;\n+\t}\n+\n+\tnum_connectors = ret / sizeof(*descs);\n+\n+\tfor (i = 0; i < num_connectors; i++) {\n+\t\tret = gud_connector_create(gdrm, i, &descs[i]);\n+\t\tif (ret)\n+\t\t\tgoto free;\n+\t}\n+free:\n+\tkfree(descs);\n+\n+\treturn ret;\n+}\n--- /dev/null\n+++ b/drivers/gpu/drm/gud/gud_drv.c\n@@ -0,0 +1,674 @@\n+// SPDX-License-Identifier: MIT\n+/*\n+ * Copyright 2020 Noralf Trønnes\n+ */\n+\n+#include <linux/dma-buf.h>\n+#include <linux/dma-mapping.h>\n+#include <linux/lz4.h>\n+#include <linux/module.h>\n+#include <linux/platform_device.h>\n+#include <linux/string_helpers.h>\n+#include <linux/usb.h>\n+#include <linux/vmalloc.h>\n+#include <linux/workqueue.h>\n+\n+#include <drm/drm_atomic_helper.h>\n+#include <drm/drm_damage_helper.h>\n+#include <drm/drm_debugfs.h>\n+#include <drm/drm_drv.h>\n+#include <drm/drm_fb_helper.h>\n+#include <drm/drm_fourcc.h>\n+#include <drm/drm_gem_framebuffer_helper.h>\n+#include <drm/drm_gem_shmem_helper.h>\n+#include <drm/drm_managed.h>\n+#include <drm/drm_print.h>\n+#include <drm/drm_probe_helper.h>\n+#include <drm/drm_simple_kms_helper.h>\n+#include <drm/gud.h>\n+\n+#include \"gud_internal.h\"\n+\n+/* Only used internally */\n+static const struct drm_format_info gud_drm_format_r1 = {\n+\t.format = GUD_DRM_FORMAT_R1,\n+\t.num_planes = 1,\n+\t.char_per_block = { 1, 0, 0 },\n+\t.block_w = { 8, 0, 0 },\n+\t.block_h = { 1, 0, 0 },\n+\t.hsub = 1,\n+\t.vsub = 1,\n+};\n+\n+static const struct drm_format_info gud_drm_format_xrgb1111 = {\n+\t.format = GUD_DRM_FORMAT_XRGB1111,\n+\t.num_planes = 1,\n+\t.char_per_block = { 1, 0, 0 },\n+\t.block_w = { 2, 0, 0 },\n+\t.block_h = { 1, 0, 0 },\n+\t.hsub = 1,\n+\t.vsub = 1,\n+};\n+\n+static int gud_usb_control_msg(struct usb_interface *intf, bool in,\n+\t\t\t       u8 request, u16 value, void *buf, size_t len)\n+{\n+\tu8 requesttype = USB_TYPE_VENDOR | USB_RECIP_INTERFACE;\n+\tu8 ifnum = intf->cur_altsetting->desc.bInterfaceNumber;\n+\tstruct usb_device *usb = interface_to_usbdev(intf);\n+\tunsigned int pipe;\n+\n+\tif (len && !buf)\n+\t\treturn -EINVAL;\n+\n+\tif (in) {\n+\t\tpipe = usb_rcvctrlpipe(usb, 0);\n+\t\trequesttype |= USB_DIR_IN;\n+\t} else {\n+\t\tpipe = usb_sndctrlpipe(usb, 0);\n+\t\trequesttype |= USB_DIR_OUT;\n+\t}\n+\n+\treturn usb_control_msg(usb, pipe, request, requesttype, value,\n+\t\t\t       ifnum, buf, len, USB_CTRL_GET_TIMEOUT);\n+}\n+\n+static int gud_get_display_descriptor(struct usb_interface *intf,\n+\t\t\t\t      struct gud_display_descriptor_req *desc)\n+{\n+\tvoid *buf;\n+\tint ret;\n+\n+\tbuf = kmalloc(sizeof(*desc), GFP_KERNEL);\n+\tif (!buf)\n+\t\treturn -ENOMEM;\n+\n+\tret = gud_usb_control_msg(intf, true, GUD_REQ_GET_DESCRIPTOR, 0, buf, sizeof(*desc));\n+\tmemcpy(desc, buf, sizeof(*desc));\n+\tkfree(buf);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\tif (ret != sizeof(*desc))\n+\t\treturn -EIO;\n+\n+\tif (desc->magic != le32_to_cpu(GUD_DISPLAY_MAGIC))\n+\t\treturn -ENODATA;\n+\n+\tDRM_DEV_DEBUG_DRIVER(&intf->dev,\n+\t\t\t     \"version=%u flags=0x%x compression=0x%x max_buffer_size=%u\\n\",\n+\t\t\t     desc->version, le32_to_cpu(desc->flags), desc->compression,\n+\t\t\t     le32_to_cpu(desc->max_buffer_size));\n+\n+\tif (!desc->version || !desc->max_width || !desc->max_height ||\n+\t    le32_to_cpu(desc->min_width) > le32_to_cpu(desc->max_width) ||\n+\t    le32_to_cpu(desc->min_height) > le32_to_cpu(desc->max_height))\n+\t\treturn -EINVAL;\n+\n+\treturn 0;\n+}\n+\n+static int gud_status_to_errno(u8 status)\n+{\n+\tswitch (status) {\n+\tcase GUD_STATUS_OK:\n+\t\treturn 0;\n+\tcase GUD_STATUS_BUSY:\n+\t\treturn -EBUSY;\n+\tcase GUD_STATUS_REQUEST_NOT_SUPPORTED:\n+\t\treturn -EOPNOTSUPP;\n+\tcase GUD_STATUS_PROTOCOL_ERROR:\n+\t\treturn -EPROTO;\n+\tcase GUD_STATUS_INVALID_PARAMETER:\n+\t\treturn -EINVAL;\n+\tcase GUD_STATUS_ERROR:\n+\t\treturn -EREMOTEIO;\n+\tdefault:\n+\t\treturn -EREMOTEIO;\n+\t}\n+}\n+\n+static int gud_usb_get_status(struct usb_interface *intf)\n+{\n+\tint ret, status = -EIO;\n+\tu8 *buf;\n+\n+\tbuf = kmalloc(sizeof(*buf), GFP_KERNEL);\n+\tif (!buf)\n+\t\treturn -ENOMEM;\n+\n+\tret = gud_usb_control_msg(intf, true, GUD_REQ_GET_STATUS, 0, buf, sizeof(*buf));\n+\tif (ret == sizeof(*buf))\n+\t\tstatus = gud_status_to_errno(*buf);\n+\tkfree(buf);\n+\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\treturn status;\n+}\n+\n+static int gud_usb_transfer(struct gud_device *gdrm, bool in, u8 request, u16 index,\n+\t\t\t    void *buf, size_t len)\n+{\n+\tstruct usb_interface *intf = to_usb_interface(gdrm->drm.dev);\n+\tint idx, ret;\n+\n+\tdrm_dbg(&gdrm->drm, \"%s: request=0x%x index=%u len=%zu\\n\",\n+\t\tin ? \"get\" : \"set\", request, index, len);\n+\n+\tif (!drm_dev_enter(&gdrm->drm, &idx))\n+\t\treturn -ENODEV;\n+\n+\tmutex_lock(&gdrm->ctrl_lock);\n+\n+\tret = gud_usb_control_msg(intf, in, request, index, buf, len);\n+\tif (ret == -EPIPE || ((gdrm->flags & GUD_DISPLAY_FLAG_STATUS_ON_SET) && !in && ret >= 0)) {\n+\t\tint status;\n+\n+\t\tstatus = gud_usb_get_status(intf);\n+\t\tif (status < 0) {\n+\t\t\tret = status;\n+\t\t} else if (ret < 0) {\n+\t\t\tdev_err_once(gdrm->drm.dev,\n+\t\t\t\t     \"Unexpected status OK for failed transfer\\n\");\n+\t\t\tret = -EPIPE;\n+\t\t}\n+\t}\n+\n+\tif (ret < 0) {\n+\t\tdrm_dbg(&gdrm->drm, \"ret=%d\\n\", ret);\n+\t\tgdrm->stats_num_errors++;\n+\t}\n+\n+\tmutex_unlock(&gdrm->ctrl_lock);\n+\tdrm_dev_exit(idx);\n+\n+\treturn ret;\n+}\n+\n+/*\n+ * @buf cannot be allocated on the stack.\n+ * Returns number of bytes received or negative error code on failure.\n+ */\n+int gud_usb_get(struct gud_device *gdrm, u8 request, u16 index, void *buf, size_t max_len)\n+{\n+\treturn gud_usb_transfer(gdrm, true, request, index, buf, max_len);\n+}\n+\n+/*\n+ * @buf can be allocated on the stack or NULL.\n+ * Returns zero on success or negative error code on failure.\n+ */\n+int gud_usb_set(struct gud_device *gdrm, u8 request, u16 index, void *buf, size_t len)\n+{\n+\tvoid *trbuf = NULL;\n+\tint ret;\n+\n+\tif (buf && len) {\n+\t\ttrbuf = kmemdup(buf, len, GFP_KERNEL);\n+\t\tif (!trbuf)\n+\t\t\treturn -ENOMEM;\n+\t}\n+\n+\tret = gud_usb_transfer(gdrm, false, request, index, trbuf, len);\n+\tkfree(trbuf);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\treturn ret != len ? -EIO : 0;\n+}\n+\n+/*\n+ * @val can be allocated on the stack.\n+ * Returns zero on success or negative error code on failure.\n+ */\n+int gud_usb_get_u8(struct gud_device *gdrm, u8 request, u16 index, u8 *val)\n+{\n+\tu8 *buf;\n+\tint ret;\n+\n+\tbuf = kmalloc(sizeof(*val), GFP_KERNEL);\n+\tif (!buf)\n+\t\treturn -ENOMEM;\n+\n+\tret = gud_usb_get(gdrm, request, index, buf, sizeof(*val));\n+\t*val = *buf;\n+\tkfree(buf);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\treturn ret != sizeof(*val) ? -EIO : 0;\n+}\n+\n+/* Returns zero on success or negative error code on failure. */\n+int gud_usb_set_u8(struct gud_device *gdrm, u8 request, u8 val)\n+{\n+\treturn gud_usb_set(gdrm, request, 0, &val, sizeof(val));\n+}\n+\n+static int gud_get_properties(struct gud_device *gdrm)\n+{\n+\tstruct gud_property_req *properties;\n+\tunsigned int i, num_properties;\n+\tint ret;\n+\n+\tproperties = kcalloc(GUD_PROPERTIES_MAX_NUM, sizeof(*properties), GFP_KERNEL);\n+\tif (!properties)\n+\t\treturn -ENOMEM;\n+\n+\tret = gud_usb_get(gdrm, GUD_REQ_GET_PROPERTIES, 0,\n+\t\t\t  properties, GUD_PROPERTIES_MAX_NUM * sizeof(*properties));\n+\tif (ret <= 0)\n+\t\tgoto out;\n+\tif (ret % sizeof(*properties)) {\n+\t\tret = -EIO;\n+\t\tgoto out;\n+\t}\n+\n+\tnum_properties = ret / sizeof(*properties);\n+\tret = 0;\n+\n+\tgdrm->properties = drmm_kcalloc(&gdrm->drm, num_properties, sizeof(*gdrm->properties),\n+\t\t\t\t\tGFP_KERNEL);\n+\tif (!gdrm->properties) {\n+\t\tret = -ENOMEM;\n+\t\tgoto out;\n+\t}\n+\n+\tfor (i = 0; i < num_properties; i++) {\n+\t\tu16 prop = le16_to_cpu(properties[i].prop);\n+\t\tu64 val = le64_to_cpu(properties[i].val);\n+\n+\t\tswitch (prop) {\n+\t\tcase GUD_PROPERTY_ROTATION:\n+\t\t\t/*\n+\t\t\t * DRM UAPI matches the protocol so use the value directly,\n+\t\t\t * but mask out any additions on future devices.\n+\t\t\t */\n+\t\t\tval &= GUD_ROTATION_MASK;\n+\t\t\tret = drm_plane_create_rotation_property(&gdrm->pipe.plane,\n+\t\t\t\t\t\t\t\t DRM_MODE_ROTATE_0, val);\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\t/* New ones might show up in future devices, skip those we don't know. */\n+\t\t\tdrm_dbg(&gdrm->drm, \"Ignoring unknown property: %u\\n\", prop);\n+\t\t\tcontinue;\n+\t\t}\n+\n+\t\tif (ret)\n+\t\t\tgoto out;\n+\n+\t\tgdrm->properties[gdrm->num_properties++] = prop;\n+\t}\n+out:\n+\tkfree(properties);\n+\n+\treturn ret;\n+}\n+\n+static struct drm_gem_object *gud_gem_create_object(struct drm_device *dev, size_t size)\n+{\n+\tstruct drm_gem_shmem_object *shmem;\n+\n+\tshmem = kzalloc(sizeof(*shmem), GFP_KERNEL);\n+\tif (!shmem)\n+\t\treturn NULL;\n+\n+\tshmem->map_cached = true;\n+\n+\treturn &shmem->base;\n+}\n+\n+/*\n+ * FIXME: Dma-buf sharing requires DMA support by the importing device.\n+ *        This function is a workaround to make USB devices work as well.\n+ *        See todo.rst for how to fix the issue in the dma-buf framework.\n+ */\n+static struct drm_gem_object *gud_gem_prime_import(struct drm_device *drm, struct dma_buf *dma_buf)\n+{\n+\tstruct gud_device *gdrm = to_gud_device(drm);\n+\n+\tif (!gdrm->dmadev)\n+\t\treturn ERR_PTR(-ENODEV);\n+\n+\treturn drm_gem_prime_import_dev(drm, dma_buf, gdrm->dmadev);\n+}\n+\n+static int gud_stats_debugfs(struct seq_file *m, void *data)\n+{\n+\tstruct drm_info_node *node = m->private;\n+\tstruct gud_device *gdrm = to_gud_device(node->minor->dev);\n+\tchar buf[10];\n+\n+\tstring_get_size(gdrm->bulk_len, 1, STRING_UNITS_2, buf, sizeof(buf));\n+\tseq_printf(m, \"Max buffer size: %s\\n\", buf);\n+\tseq_printf(m, \"Number of errors:  %u\\n\", gdrm->stats_num_errors);\n+\n+\tseq_puts(m, \"Compression:      \");\n+\tif (gdrm->compression & GUD_COMPRESSION_LZ4)\n+\t\tseq_puts(m, \" lz4\");\n+\tif (!gdrm->compression)\n+\t\tseq_puts(m, \" none\");\n+\tseq_puts(m, \"\\n\");\n+\n+\tif (gdrm->compression) {\n+\t\tu64 remainder;\n+\t\tu64 ratio = div64_u64_rem(gdrm->stats_length, gdrm->stats_actual_length,\n+\t\t\t\t\t  &remainder);\n+\t\tu64 ratio_frac = div64_u64(remainder * 10, gdrm->stats_actual_length);\n+\n+\t\tseq_printf(m, \"Compression ratio: %llu.%llu\\n\", ratio, ratio_frac);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static const struct drm_info_list gud_debugfs_list[] = {\n+\t{ \"stats\", gud_stats_debugfs, 0, NULL },\n+};\n+\n+static void gud_debugfs_init(struct drm_minor *minor)\n+{\n+\tdrm_debugfs_create_files(gud_debugfs_list, ARRAY_SIZE(gud_debugfs_list),\n+\t\t\t\t minor->debugfs_root, minor);\n+}\n+\n+static const struct drm_simple_display_pipe_funcs gud_pipe_funcs = {\n+\t.check      = gud_pipe_check,\n+\t.update\t    = gud_pipe_update,\n+\t.prepare_fb = drm_gem_fb_simple_display_pipe_prepare_fb,\n+};\n+\n+static const struct drm_mode_config_funcs gud_mode_config_funcs = {\n+\t.fb_create = drm_gem_fb_create_with_dirty,\n+\t.atomic_check = drm_atomic_helper_check,\n+\t.atomic_commit = drm_atomic_helper_commit,\n+};\n+\n+static const u64 gud_pipe_modifiers[] = {\n+\tDRM_FORMAT_MOD_LINEAR,\n+\tDRM_FORMAT_MOD_INVALID\n+};\n+\n+DEFINE_DRM_GEM_FOPS(gud_fops);\n+\n+static struct drm_driver gud_drm_driver = {\n+\t.driver_features\t= DRIVER_MODESET | DRIVER_GEM | DRIVER_ATOMIC,\n+\t.fops\t\t\t= &gud_fops,\n+\tDRM_GEM_SHMEM_DRIVER_OPS,\n+\t.gem_create_object\t= gud_gem_create_object,\n+\t.gem_prime_import\t= gud_gem_prime_import,\n+\t.debugfs_init\t\t= gud_debugfs_init,\n+\n+\t.name\t\t\t= \"gud\",\n+\t.desc\t\t\t= \"Generic USB Display\",\n+\t.date\t\t\t= \"20200422\",\n+\t.major\t\t\t= 1,\n+\t.minor\t\t\t= 0,\n+};\n+\n+static void gud_free_buffers_and_mutex(struct drm_device *drm, void *unused)\n+{\n+\tstruct gud_device *gdrm = to_gud_device(drm);\n+\n+\tvfree(gdrm->compress_buf);\n+\tkfree(gdrm->bulk_buf);\n+\tmutex_destroy(&gdrm->ctrl_lock);\n+\tmutex_destroy(&gdrm->damage_lock);\n+}\n+\n+static int gud_probe(struct usb_interface *intf, const struct usb_device_id *id)\n+{\n+\tconst struct drm_format_info *xrgb8888_emulation_format = NULL;\n+\tbool rgb565_supported = false, xrgb8888_supported = false;\n+\tunsigned int num_formats_dev, num_formats = 0;\n+\tstruct usb_endpoint_descriptor *bulk_out;\n+\tstruct gud_display_descriptor_req desc;\n+\tstruct device *dev = &intf->dev;\n+\tsize_t max_buffer_size = 0;\n+\tstruct gud_device *gdrm;\n+\tstruct drm_device *drm;\n+\tu8 *formats_dev;\n+\tu32 *formats;\n+\tint ret, i;\n+\n+\tret = usb_find_bulk_out_endpoint(intf->cur_altsetting, &bulk_out);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = gud_get_display_descriptor(intf, &desc);\n+\tif (ret) {\n+\t\tDRM_DEV_DEBUG_DRIVER(dev, \"Not a display interface: ret=%d\\n\", ret);\n+\t\treturn -ENODEV;\n+\t}\n+\n+\tif (desc.version > 1) {\n+\t\tdev_err(dev, \"Protocol version %u is not supported\\n\", desc.version);\n+\t\treturn -ENODEV;\n+\t}\n+\n+\tgdrm = devm_drm_dev_alloc(dev, &gud_drm_driver, struct gud_device, drm);\n+\tif (IS_ERR(gdrm))\n+\t\treturn PTR_ERR(gdrm);\n+\n+\tdrm = &gdrm->drm;\n+\tdrm->mode_config.funcs = &gud_mode_config_funcs;\n+\tret = drmm_mode_config_init(drm);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tgdrm->flags = le32_to_cpu(desc.flags);\n+\tgdrm->compression = desc.compression & GUD_COMPRESSION_LZ4;\n+\n+\tif (gdrm->flags & GUD_DISPLAY_FLAG_FULL_UPDATE && gdrm->compression)\n+\t\treturn -EINVAL;\n+\n+\tmutex_init(&gdrm->ctrl_lock);\n+\tmutex_init(&gdrm->damage_lock);\n+\tINIT_WORK(&gdrm->work, gud_flush_work);\n+\tgud_clear_damage(gdrm);\n+\n+\tret = drmm_add_action_or_reset(drm, gud_free_buffers_and_mutex, NULL);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tdrm->mode_config.min_width = le32_to_cpu(desc.min_width);\n+\tdrm->mode_config.max_width = le32_to_cpu(desc.max_width);\n+\tdrm->mode_config.min_height = le32_to_cpu(desc.min_height);\n+\tdrm->mode_config.max_height = le32_to_cpu(desc.max_height);\n+\n+\tformats_dev = devm_kmalloc(dev, GUD_FORMATS_MAX_NUM, GFP_KERNEL);\n+\t/* Add room for emulated XRGB8888 */\n+\tformats = devm_kmalloc_array(dev, GUD_FORMATS_MAX_NUM + 1, sizeof(*formats), GFP_KERNEL);\n+\tif (!formats_dev || !formats)\n+\t\treturn -ENOMEM;\n+\n+\tret = gud_usb_get(gdrm, GUD_REQ_GET_FORMATS, 0, formats_dev, GUD_FORMATS_MAX_NUM);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\tnum_formats_dev = ret;\n+\tfor (i = 0; i < num_formats_dev; i++) {\n+\t\tconst struct drm_format_info *info;\n+\t\tsize_t fmt_buf_size;\n+\t\tu32 format;\n+\n+\t\tformat = gud_to_fourcc(formats_dev[i]);\n+\t\tif (!format) {\n+\t\t\tdrm_dbg(drm, \"Unsupported format: 0x%02x\\n\", formats_dev[i]);\n+\t\t\tcontinue;\n+\t\t}\n+\n+\t\tif (format == GUD_DRM_FORMAT_R1)\n+\t\t\tinfo = &gud_drm_format_r1;\n+\t\telse if (format == GUD_DRM_FORMAT_XRGB1111)\n+\t\t\tinfo = &gud_drm_format_xrgb1111;\n+\t\telse\n+\t\t\tinfo = drm_format_info(format);\n+\n+\t\tswitch (format) {\n+\t\tcase GUD_DRM_FORMAT_R1:\n+\t\t\tfallthrough;\n+\t\tcase GUD_DRM_FORMAT_XRGB1111:\n+\t\t\tif (!xrgb8888_emulation_format)\n+\t\t\t\txrgb8888_emulation_format = info;\n+\t\t\tbreak;\n+\t\tcase DRM_FORMAT_RGB565:\n+\t\t\trgb565_supported = true;\n+\t\t\tif (!xrgb8888_emulation_format)\n+\t\t\t\txrgb8888_emulation_format = info;\n+\t\t\tbreak;\n+\t\tcase DRM_FORMAT_XRGB8888:\n+\t\t\txrgb8888_supported = true;\n+\t\t\tbreak;\n+\t\t};\n+\n+\t\tfmt_buf_size = drm_format_info_min_pitch(info, 0, drm->mode_config.max_width) *\n+\t\t\t       drm->mode_config.max_height;\n+\t\tmax_buffer_size = max(max_buffer_size, fmt_buf_size);\n+\n+\t\tif (format == GUD_DRM_FORMAT_R1 || format == GUD_DRM_FORMAT_XRGB1111)\n+\t\t\tcontinue; /* Internal not for userspace */\n+\n+\t\tformats[num_formats++] = format;\n+\t}\n+\n+\tif (!num_formats && !xrgb8888_emulation_format) {\n+\t\tdev_err(dev, \"No supported pixel formats found\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\t/* Prefer speed over color depth */\n+\tif (rgb565_supported)\n+\t\tdrm->mode_config.preferred_depth = 16;\n+\n+\tif (!xrgb8888_supported && xrgb8888_emulation_format) {\n+\t\tgdrm->xrgb8888_emulation_format = xrgb8888_emulation_format;\n+\t\tformats[num_formats++] = DRM_FORMAT_XRGB8888;\n+\t}\n+\n+\tif (desc.max_buffer_size)\n+\t\tmax_buffer_size = le32_to_cpu(desc.max_buffer_size);\n+retry:\n+\t/*\n+\t * Use plain kmalloc here since devm_kmalloc() places struct devres at the beginning\n+\t * of the buffer it allocates. This wastes a lot of memory when allocating big buffers.\n+\t * Asking for 2M would actually allocate 4M. This would also prevent getting the biggest\n+\t * possible buffer potentially leading to split transfers.\n+\t */\n+\tgdrm->bulk_buf = kmalloc(max_buffer_size, GFP_KERNEL | __GFP_NOWARN);\n+\tif (!gdrm->bulk_buf) {\n+\t\tmax_buffer_size = roundup_pow_of_two(max_buffer_size) / 2;\n+\t\tif (max_buffer_size < SZ_512K)\n+\t\t\treturn -ENOMEM;\n+\t\tgoto retry;\n+\t}\n+\n+\tgdrm->bulk_pipe = usb_sndbulkpipe(interface_to_usbdev(intf), usb_endpoint_num(bulk_out));\n+\tgdrm->bulk_len = max_buffer_size;\n+\n+\tif (gdrm->compression & GUD_COMPRESSION_LZ4) {\n+\t\tgdrm->lz4_comp_mem = devm_kmalloc(dev, LZ4_MEM_COMPRESS, GFP_KERNEL);\n+\t\tif (!gdrm->lz4_comp_mem)\n+\t\t\treturn -ENOMEM;\n+\n+\t\tgdrm->compress_buf = vmalloc(gdrm->bulk_len);\n+\t\tif (!gdrm->compress_buf)\n+\t\t\treturn -ENOMEM;\n+\t}\n+\n+\tret = drm_simple_display_pipe_init(drm, &gdrm->pipe, &gud_pipe_funcs,\n+\t\t\t\t\t   formats, num_formats,\n+\t\t\t\t\t   gud_pipe_modifiers, NULL);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tdevm_kfree(dev, formats);\n+\tdevm_kfree(dev, formats_dev);\n+\n+\tret = gud_get_properties(gdrm);\n+\tif (ret) {\n+\t\tdev_err(dev, \"Failed to get properties (error=%d)\\n\", ret);\n+\t\treturn ret;\n+\t}\n+\n+\tdrm_plane_enable_fb_damage_clips(&gdrm->pipe.plane);\n+\n+\tret = gud_get_connectors(gdrm);\n+\tif (ret) {\n+\t\tdev_err(dev, \"Failed to get connectors (error=%d)\\n\", ret);\n+\t\treturn ret;\n+\t}\n+\n+\tdrm_mode_config_reset(drm);\n+\n+\tusb_set_intfdata(intf, gdrm);\n+\n+\tgdrm->dmadev = usb_intf_get_dma_device(intf);\n+\tif (!gdrm->dmadev)\n+\t\tdev_warn(dev, \"buffer sharing not supported\");\n+\n+\tret = drm_dev_register(drm, 0);\n+\tif (ret) {\n+\t\tput_device(gdrm->dmadev);\n+\t\treturn ret;\n+\t}\n+\n+\tdrm_kms_helper_poll_init(drm);\n+\n+\tdrm_fbdev_generic_setup(drm, 0);\n+\n+\treturn 0;\n+}\n+\n+static void gud_disconnect(struct usb_interface *interface)\n+{\n+\tstruct gud_device *gdrm = usb_get_intfdata(interface);\n+\tstruct drm_device *drm = &gdrm->drm;\n+\n+\tdrm_dbg(drm, \"%s:\\n\", __func__);\n+\n+\tdrm_kms_helper_poll_fini(drm);\n+\tdrm_dev_unplug(drm);\n+\tdrm_atomic_helper_shutdown(drm);\n+\tput_device(gdrm->dmadev);\n+\tgdrm->dmadev = NULL;\n+}\n+\n+static int gud_suspend(struct usb_interface *intf, pm_message_t message)\n+{\n+\tstruct gud_device *gdrm = usb_get_intfdata(intf);\n+\n+\treturn drm_mode_config_helper_suspend(&gdrm->drm);\n+}\n+\n+static int gud_resume(struct usb_interface *intf)\n+{\n+\tstruct gud_device *gdrm = usb_get_intfdata(intf);\n+\n+\tdrm_mode_config_helper_resume(&gdrm->drm);\n+\n+\treturn 0;\n+}\n+\n+static const struct usb_device_id gud_id_table[] = {\n+\t{ USB_DEVICE_INTERFACE_CLASS(0x1d50, 0x614d, USB_CLASS_VENDOR_SPEC) },\n+\t{ }\n+};\n+\n+MODULE_DEVICE_TABLE(usb, gud_id_table);\n+\n+static struct usb_driver gud_usb_driver = {\n+\t.name\t\t= \"gud\",\n+\t.probe\t\t= gud_probe,\n+\t.disconnect\t= gud_disconnect,\n+\t.id_table\t= gud_id_table,\n+\t.suspend\t= gud_suspend,\n+\t.resume\t\t= gud_resume,\n+\t.reset_resume\t= gud_resume,\n+};\n+\n+module_usb_driver(gud_usb_driver);\n+\n+MODULE_AUTHOR(\"Noralf Trønnes\");\n+MODULE_LICENSE(\"Dual MIT/GPL\");\n--- /dev/null\n+++ b/drivers/gpu/drm/gud/gud_internal.h\n@@ -0,0 +1,154 @@\n+/* SPDX-License-Identifier: MIT */\n+\n+#ifndef __LINUX_GUD_INTERNAL_H\n+#define __LINUX_GUD_INTERNAL_H\n+\n+#include <linux/list.h>\n+#include <linux/mutex.h>\n+#include <linux/usb.h>\n+#include <linux/workqueue.h>\n+#include <uapi/drm/drm_fourcc.h>\n+\n+#include <drm/drm_modes.h>\n+#include <drm/drm_simple_kms_helper.h>\n+\n+struct gud_device {\n+\tstruct drm_device drm;\n+\tstruct drm_simple_display_pipe pipe;\n+\tstruct device *dmadev;\n+\tstruct work_struct work;\n+\tu32 flags;\n+\tconst struct drm_format_info *xrgb8888_emulation_format;\n+\n+\tu16 *properties;\n+\tunsigned int num_properties;\n+\n+\tunsigned int bulk_pipe;\n+\tvoid *bulk_buf;\n+\tsize_t bulk_len;\n+\n+\tu8 compression;\n+\tvoid *lz4_comp_mem;\n+\tvoid *compress_buf;\n+\n+\tu64 stats_length;\n+\tu64 stats_actual_length;\n+\tunsigned int stats_num_errors;\n+\n+\tstruct mutex ctrl_lock; /* Serialize get/set and status transfers */\n+\n+\tstruct mutex damage_lock; /* Protects the following members: */\n+\tstruct drm_framebuffer *fb;\n+\tstruct drm_rect damage;\n+\tbool prev_flush_failed;\n+};\n+\n+static inline struct gud_device *to_gud_device(struct drm_device *drm)\n+{\n+\treturn container_of(drm, struct gud_device, drm);\n+}\n+\n+static inline struct usb_device *gud_to_usb_device(struct gud_device *gdrm)\n+{\n+\treturn interface_to_usbdev(to_usb_interface(gdrm->drm.dev));\n+}\n+\n+int gud_usb_get(struct gud_device *gdrm, u8 request, u16 index, void *buf, size_t len);\n+int gud_usb_set(struct gud_device *gdrm, u8 request, u16 index, void *buf, size_t len);\n+int gud_usb_get_u8(struct gud_device *gdrm, u8 request, u16 index, u8 *val);\n+int gud_usb_set_u8(struct gud_device *gdrm, u8 request, u8 val);\n+\n+void gud_clear_damage(struct gud_device *gdrm);\n+void gud_flush_work(struct work_struct *work);\n+int gud_pipe_check(struct drm_simple_display_pipe *pipe,\n+\t\t   struct drm_plane_state *new_plane_state,\n+\t\t   struct drm_crtc_state *new_crtc_state);\n+void gud_pipe_update(struct drm_simple_display_pipe *pipe,\n+\t\t     struct drm_plane_state *old_state);\n+int gud_connector_fill_properties(struct drm_connector_state *connector_state,\n+\t\t\t\t  struct gud_property_req *properties);\n+int gud_get_connectors(struct gud_device *gdrm);\n+\n+/* Driver internal fourcc transfer formats */\n+#define GUD_DRM_FORMAT_R1\t\t0x00000122\n+#define GUD_DRM_FORMAT_XRGB1111\t\t0x03121722\n+\n+static inline u8 gud_from_fourcc(u32 fourcc)\n+{\n+\tswitch (fourcc) {\n+\tcase GUD_DRM_FORMAT_R1:\n+\t\treturn GUD_PIXEL_FORMAT_R1;\n+\tcase GUD_DRM_FORMAT_XRGB1111:\n+\t\treturn GUD_PIXEL_FORMAT_XRGB1111;\n+\tcase DRM_FORMAT_RGB565:\n+\t\treturn GUD_PIXEL_FORMAT_RGB565;\n+\tcase DRM_FORMAT_XRGB8888:\n+\t\treturn GUD_PIXEL_FORMAT_XRGB8888;\n+\tcase DRM_FORMAT_ARGB8888:\n+\t\treturn GUD_PIXEL_FORMAT_ARGB8888;\n+\t};\n+\n+\treturn 0;\n+}\n+\n+static inline u32 gud_to_fourcc(u8 format)\n+{\n+\tswitch (format) {\n+\tcase GUD_PIXEL_FORMAT_R1:\n+\t\treturn GUD_DRM_FORMAT_R1;\n+\tcase GUD_PIXEL_FORMAT_XRGB1111:\n+\t\treturn GUD_DRM_FORMAT_XRGB1111;\n+\tcase GUD_PIXEL_FORMAT_RGB565:\n+\t\treturn DRM_FORMAT_RGB565;\n+\tcase GUD_PIXEL_FORMAT_XRGB8888:\n+\t\treturn DRM_FORMAT_XRGB8888;\n+\tcase GUD_PIXEL_FORMAT_ARGB8888:\n+\t\treturn DRM_FORMAT_ARGB8888;\n+\t};\n+\n+\treturn 0;\n+}\n+\n+static inline void gud_from_display_mode(struct gud_display_mode_req *dst,\n+\t\t\t\t\t const struct drm_display_mode *src)\n+{\n+\tu32 flags = src->flags & GUD_DISPLAY_MODE_FLAG_USER_MASK;\n+\n+\tif (src->type & DRM_MODE_TYPE_PREFERRED)\n+\t\tflags |= GUD_DISPLAY_MODE_FLAG_PREFERRED;\n+\n+\tdst->clock = cpu_to_le32(src->clock);\n+\tdst->hdisplay = cpu_to_le16(src->hdisplay);\n+\tdst->hsync_start = cpu_to_le16(src->hsync_start);\n+\tdst->hsync_end = cpu_to_le16(src->hsync_end);\n+\tdst->htotal = cpu_to_le16(src->htotal);\n+\tdst->vdisplay = cpu_to_le16(src->vdisplay);\n+\tdst->vsync_start = cpu_to_le16(src->vsync_start);\n+\tdst->vsync_end = cpu_to_le16(src->vsync_end);\n+\tdst->vtotal = cpu_to_le16(src->vtotal);\n+\tdst->flags = cpu_to_le32(flags);\n+}\n+\n+static inline void gud_to_display_mode(struct drm_display_mode *dst,\n+\t\t\t\t       const struct gud_display_mode_req *src)\n+{\n+\tu32 flags = le32_to_cpu(src->flags);\n+\n+\tmemset(dst, 0, sizeof(*dst));\n+\tdst->clock = le32_to_cpu(src->clock);\n+\tdst->hdisplay = le16_to_cpu(src->hdisplay);\n+\tdst->hsync_start = le16_to_cpu(src->hsync_start);\n+\tdst->hsync_end = le16_to_cpu(src->hsync_end);\n+\tdst->htotal = le16_to_cpu(src->htotal);\n+\tdst->vdisplay = le16_to_cpu(src->vdisplay);\n+\tdst->vsync_start = le16_to_cpu(src->vsync_start);\n+\tdst->vsync_end = le16_to_cpu(src->vsync_end);\n+\tdst->vtotal = le16_to_cpu(src->vtotal);\n+\tdst->flags = flags & GUD_DISPLAY_MODE_FLAG_USER_MASK;\n+\tdst->type = DRM_MODE_TYPE_DRIVER;\n+\tif (flags & GUD_DISPLAY_MODE_FLAG_PREFERRED)\n+\t\tdst->type |= DRM_MODE_TYPE_PREFERRED;\n+\tdrm_mode_set_name(dst);\n+}\n+\n+#endif\n--- /dev/null\n+++ b/drivers/gpu/drm/gud/gud_pipe.c\n@@ -0,0 +1,551 @@\n+// SPDX-License-Identifier: MIT\n+/*\n+ * Copyright 2020 Noralf Trønnes\n+ */\n+\n+#include <linux/dma-buf.h>\n+#include <linux/lz4.h>\n+#include <linux/usb.h>\n+#include <linux/workqueue.h>\n+\n+#include <drm/drm_atomic.h>\n+#include <drm/drm_connector.h>\n+#include <drm/drm_damage_helper.h>\n+#include <drm/drm_drv.h>\n+#include <drm/drm_format_helper.h>\n+#include <drm/drm_fourcc.h>\n+#include <drm/drm_framebuffer.h>\n+#include <drm/drm_gem_shmem_helper.h>\n+#include <drm/drm_print.h>\n+#include <drm/drm_rect.h>\n+#include <drm/drm_simple_kms_helper.h>\n+#include <drm/gud.h>\n+\n+#include \"gud_internal.h\"\n+\n+/*\n+ * FIXME: The driver is probably broken on Big Endian machines.\n+ * See discussion:\n+ * https://lore.kernel.org/dri-devel/CAKb7UvihLX0hgBOP3VBG7O+atwZcUVCPVuBdfmDMpg0NjXe-cQ@mail.gmail.com/\n+ */\n+\n+static bool gud_is_big_endian(void)\n+{\n+#if defined(__BIG_ENDIAN)\n+\treturn true;\n+#else\n+\treturn false;\n+#endif\n+}\n+\n+static size_t gud_xrgb8888_to_r124(u8 *dst, const struct drm_format_info *format,\n+\t\t\t\t   void *src, struct drm_framebuffer *fb,\n+\t\t\t\t   struct drm_rect *rect)\n+{\n+\tunsigned int block_width = drm_format_info_block_width(format, 0);\n+\tunsigned int bits_per_pixel = 8 / block_width;\n+\tunsigned int x, y, width, height;\n+\tu8 pix, *pix8, *block = dst; /* Assign to silence compiler warning */\n+\tsize_t len;\n+\tvoid *buf;\n+\n+\tWARN_ON_ONCE(format->char_per_block[0] != 1);\n+\n+\t/* Start on a byte boundary */\n+\trect->x1 = ALIGN_DOWN(rect->x1, block_width);\n+\twidth = drm_rect_width(rect);\n+\theight = drm_rect_height(rect);\n+\tlen = drm_format_info_min_pitch(format, 0, width) * height;\n+\n+\tbuf = kmalloc(width * height, GFP_KERNEL);\n+\tif (!buf)\n+\t\treturn 0;\n+\n+\tdrm_fb_xrgb8888_to_gray8(buf, src, fb, rect);\n+\tpix8 = buf;\n+\n+\tfor (y = 0; y < height; y++) {\n+\t\tfor (x = 0; x < width; x++) {\n+\t\t\tunsigned int pixpos = x % block_width; /* within byte from the left */\n+\t\t\tunsigned int pixshift = (block_width - pixpos - 1) * bits_per_pixel;\n+\n+\t\t\tif (!pixpos) {\n+\t\t\t\tblock = dst++;\n+\t\t\t\t*block = 0;\n+\t\t\t}\n+\n+\t\t\tpix = (*pix8++) >> (8 - bits_per_pixel);\n+\t\t\t*block |= pix << pixshift;\n+\t\t}\n+\t}\n+\n+\tkfree(buf);\n+\n+\treturn len;\n+}\n+\n+static size_t gud_xrgb8888_to_color(u8 *dst, const struct drm_format_info *format,\n+\t\t\t\t    void *src, struct drm_framebuffer *fb,\n+\t\t\t\t    struct drm_rect *rect)\n+{\n+\tunsigned int block_width = drm_format_info_block_width(format, 0);\n+\tunsigned int bits_per_pixel = 8 / block_width;\n+\tu8 r, g, b, pix, *block = dst; /* Assign to silence compiler warning */\n+\tunsigned int x, y, width;\n+\tu32 *pix32;\n+\tsize_t len;\n+\n+\t/* Start on a byte boundary */\n+\trect->x1 = ALIGN_DOWN(rect->x1, block_width);\n+\twidth = drm_rect_width(rect);\n+\tlen = drm_format_info_min_pitch(format, 0, width) * drm_rect_height(rect);\n+\n+\tfor (y = rect->y1; y < rect->y2; y++) {\n+\t\tpix32 = src + (y * fb->pitches[0]);\n+\t\tpix32 += rect->x1;\n+\n+\t\tfor (x = 0; x < width; x++) {\n+\t\t\tunsigned int pixpos = x % block_width; /* within byte from the left */\n+\t\t\tunsigned int pixshift = (block_width - pixpos - 1) * bits_per_pixel;\n+\n+\t\t\tif (!pixpos) {\n+\t\t\t\tblock = dst++;\n+\t\t\t\t*block = 0;\n+\t\t\t}\n+\n+\t\t\tr = *pix32 >> 16;\n+\t\t\tg = *pix32 >> 8;\n+\t\t\tb = *pix32++;\n+\n+\t\t\tswitch (format->format) {\n+\t\t\tcase GUD_DRM_FORMAT_XRGB1111:\n+\t\t\t\tpix = ((r >> 7) << 2) | ((g >> 7) << 1) | (b >> 7);\n+\t\t\t\tbreak;\n+\t\t\tdefault:\n+\t\t\t\tWARN_ON_ONCE(1);\n+\t\t\t\treturn len;\n+\t\t\t};\n+\n+\t\t\t*block |= pix << pixshift;\n+\t\t}\n+\t}\n+\n+\treturn len;\n+}\n+\n+static int gud_prep_flush(struct gud_device *gdrm, struct drm_framebuffer *fb,\n+\t\t\t  const struct drm_format_info *format, struct drm_rect *rect,\n+\t\t\t  struct gud_set_buffer_req *req)\n+{\n+\tstruct dma_buf_attachment *import_attach = fb->obj[0]->import_attach;\n+\tu8 compression = gdrm->compression;\n+\tvoid *vmap, *vaddr, *buf;\n+\tsize_t pitch, len;\n+\tint ret = 0;\n+\n+\tpitch = drm_format_info_min_pitch(format, 0, drm_rect_width(rect));\n+\tlen = pitch * drm_rect_height(rect);\n+\tif (len > gdrm->bulk_len)\n+\t\treturn -E2BIG;\n+\n+\tvmap = drm_gem_shmem_vmap(fb->obj[0]);\n+\tif (!vmap)\n+\t\treturn -ENOMEM;\n+\n+\tvaddr = vmap + fb->offsets[0];\n+\n+\tif (import_attach) {\n+\t\tret = dma_buf_begin_cpu_access(import_attach->dmabuf, DMA_FROM_DEVICE);\n+\t\tif (ret)\n+\t\t\tgoto vunmap;\n+\t}\n+retry:\n+\tif (compression)\n+\t\tbuf = gdrm->compress_buf;\n+\telse\n+\t\tbuf = gdrm->bulk_buf;\n+\n+\t/*\n+\t * Imported buffers are assumed to be write-combined and thus uncached\n+\t * with slow reads (at least on ARM).\n+\t */\n+\tif (format != fb->format) {\n+\t\tif (format->format == GUD_DRM_FORMAT_R1) {\n+\t\t\tlen = gud_xrgb8888_to_r124(buf, format, vaddr, fb, rect);\n+\t\t\tif (!len) {\n+\t\t\t\tret = -ENOMEM;\n+\t\t\t\tgoto end_cpu_access;\n+\t\t\t}\n+\t\t} else if (format->format == DRM_FORMAT_RGB565) {\n+\t\t\tdrm_fb_xrgb8888_to_rgb565(buf, vaddr, fb, rect, gud_is_big_endian());\n+\t\t} else {\n+\t\t\tlen = gud_xrgb8888_to_color(buf, format, vaddr, fb, rect);\n+\t\t}\n+\t} else if (gud_is_big_endian() && format->cpp[0] > 1) {\n+\t\tdrm_fb_swab(buf, vaddr, fb, rect, !import_attach);\n+\t} else if (compression && !import_attach && pitch == fb->pitches[0]) {\n+\t\t/* can compress directly from the framebuffer */\n+\t\tbuf = vaddr + rect->y1 * pitch;\n+\t} else {\n+\t\tdrm_fb_memcpy(buf, vaddr, fb, rect);\n+\t}\n+\n+\tmemset(req, 0, sizeof(*req));\n+\treq->x = cpu_to_le32(rect->x1);\n+\treq->y = cpu_to_le32(rect->y1);\n+\treq->width = cpu_to_le32(drm_rect_width(rect));\n+\treq->height = cpu_to_le32(drm_rect_height(rect));\n+\treq->length = cpu_to_le32(len);\n+\n+\tif (compression & GUD_COMPRESSION_LZ4) {\n+\t\tint complen;\n+\n+\t\tcomplen = LZ4_compress_default(buf, gdrm->bulk_buf, len, len, gdrm->lz4_comp_mem);\n+\t\tif (complen <= 0) {\n+\t\t\tcompression = 0;\n+\t\t\tgoto retry;\n+\t\t}\n+\n+\t\treq->compression = GUD_COMPRESSION_LZ4;\n+\t\treq->compressed_length = cpu_to_le32(complen);\n+\t}\n+\n+end_cpu_access:\n+\tif (import_attach)\n+\t\tdma_buf_end_cpu_access(import_attach->dmabuf, DMA_FROM_DEVICE);\n+vunmap:\n+\tdrm_gem_shmem_vunmap(fb->obj[0], vmap);\n+\n+\treturn ret;\n+}\n+\n+static int gud_flush_rect(struct gud_device *gdrm, struct drm_framebuffer *fb,\n+\t\t\t  const struct drm_format_info *format, struct drm_rect *rect)\n+{\n+\tstruct usb_device *usb = gud_to_usb_device(gdrm);\n+\tstruct gud_set_buffer_req req;\n+\tint ret, actual_length;\n+\tsize_t len, trlen;\n+\n+\tdrm_dbg(&gdrm->drm, \"Flushing [FB:%d] \" DRM_RECT_FMT \"\\n\", fb->base.id, DRM_RECT_ARG(rect));\n+\n+\tret = gud_prep_flush(gdrm, fb, format, rect, &req);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tlen = le32_to_cpu(req.length);\n+\n+\tif (req.compression)\n+\t\ttrlen = le32_to_cpu(req.compressed_length);\n+\telse\n+\t\ttrlen = len;\n+\n+\tgdrm->stats_length += len;\n+\t/* Did it wrap around? */\n+\tif (gdrm->stats_length <= len && gdrm->stats_actual_length) {\n+\t\tgdrm->stats_length = len;\n+\t\tgdrm->stats_actual_length = 0;\n+\t}\n+\tgdrm->stats_actual_length += trlen;\n+\n+\tif (!(gdrm->flags & GUD_DISPLAY_FLAG_FULL_UPDATE) || gdrm->prev_flush_failed) {\n+\t\tret = gud_usb_set(gdrm, GUD_REQ_SET_BUFFER, 0, &req, sizeof(req));\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\t}\n+\n+\tret = usb_bulk_msg(usb, gdrm->bulk_pipe, gdrm->bulk_buf, trlen,\n+\t\t\t   &actual_length, msecs_to_jiffies(3000));\n+\tif (!ret && trlen != actual_length)\n+\t\tret = -EIO;\n+\tif (ret)\n+\t\tgdrm->stats_num_errors++;\n+\n+\treturn ret;\n+}\n+\n+void gud_clear_damage(struct gud_device *gdrm)\n+{\n+\tgdrm->damage.x1 = INT_MAX;\n+\tgdrm->damage.y1 = INT_MAX;\n+\tgdrm->damage.x2 = 0;\n+\tgdrm->damage.y2 = 0;\n+}\n+\n+static void gud_add_damage(struct gud_device *gdrm, struct drm_rect *damage)\n+{\n+\tgdrm->damage.x1 = min(gdrm->damage.x1, damage->x1);\n+\tgdrm->damage.y1 = min(gdrm->damage.y1, damage->y1);\n+\tgdrm->damage.x2 = max(gdrm->damage.x2, damage->x2);\n+\tgdrm->damage.y2 = max(gdrm->damage.y2, damage->y2);\n+}\n+\n+static void gud_retry_failed_flush(struct gud_device *gdrm, struct drm_framebuffer *fb,\n+\t\t\t\t   struct drm_rect *damage)\n+{\n+\t/*\n+\t * pipe_update waits for the worker when the display mode is going to change.\n+\t * This ensures that the width and height is still the same making it safe to\n+\t * add back the damage.\n+\t */\n+\n+\tmutex_lock(&gdrm->damage_lock);\n+\tif (!gdrm->fb) {\n+\t\tdrm_framebuffer_get(fb);\n+\t\tgdrm->fb = fb;\n+\t}\n+\tgud_add_damage(gdrm, damage);\n+\tmutex_unlock(&gdrm->damage_lock);\n+\n+\t/* Retry only once to avoid a possible storm in case of continues errors. */\n+\tif (!gdrm->prev_flush_failed)\n+\t\tqueue_work(system_long_wq, &gdrm->work);\n+\tgdrm->prev_flush_failed = true;\n+}\n+\n+void gud_flush_work(struct work_struct *work)\n+{\n+\tstruct gud_device *gdrm = container_of(work, struct gud_device, work);\n+\tconst struct drm_format_info *format;\n+\tstruct drm_framebuffer *fb;\n+\tstruct drm_rect damage;\n+\tunsigned int i, lines;\n+\tint idx, ret = 0;\n+\tsize_t pitch;\n+\n+\tif (!drm_dev_enter(&gdrm->drm, &idx))\n+\t\treturn;\n+\n+\tmutex_lock(&gdrm->damage_lock);\n+\tfb = gdrm->fb;\n+\tgdrm->fb = NULL;\n+\tdamage = gdrm->damage;\n+\tgud_clear_damage(gdrm);\n+\tmutex_unlock(&gdrm->damage_lock);\n+\n+\tif (!fb)\n+\t\tgoto out;\n+\n+\tformat = fb->format;\n+\tif (format->format == DRM_FORMAT_XRGB8888 && gdrm->xrgb8888_emulation_format)\n+\t\tformat = gdrm->xrgb8888_emulation_format;\n+\n+\t/* Split update if it's too big */\n+\tpitch = drm_format_info_min_pitch(format, 0, drm_rect_width(&damage));\n+\tlines = drm_rect_height(&damage);\n+\n+\tif (gdrm->bulk_len < lines * pitch)\n+\t\tlines = gdrm->bulk_len / pitch;\n+\n+\tfor (i = 0; i < DIV_ROUND_UP(drm_rect_height(&damage), lines); i++) {\n+\t\tstruct drm_rect rect = damage;\n+\n+\t\trect.y1 += i * lines;\n+\t\trect.y2 = min_t(u32, rect.y1 + lines, damage.y2);\n+\n+\t\tret = gud_flush_rect(gdrm, fb, format, &rect);\n+\t\tif (ret) {\n+\t\t\tif (ret != -ENODEV && ret != -ECONNRESET &&\n+\t\t\t    ret != -ESHUTDOWN && ret != -EPROTO) {\n+\t\t\t\tbool prev_flush_failed = gdrm->prev_flush_failed;\n+\n+\t\t\t\tgud_retry_failed_flush(gdrm, fb, &damage);\n+\t\t\t\tif (!prev_flush_failed)\n+\t\t\t\t\tdev_err_ratelimited(fb->dev->dev,\n+\t\t\t\t\t\t\t    \"Failed to flush framebuffer: error=%d\\n\", ret);\n+\t\t\t}\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\tgdrm->prev_flush_failed = false;\n+\t}\n+\n+\tdrm_framebuffer_put(fb);\n+out:\n+\tdrm_dev_exit(idx);\n+}\n+\n+static void gud_fb_queue_damage(struct gud_device *gdrm, struct drm_framebuffer *fb,\n+\t\t\t\tstruct drm_rect *damage)\n+{\n+\tstruct drm_framebuffer *old_fb = NULL;\n+\n+\tmutex_lock(&gdrm->damage_lock);\n+\n+\tif (fb != gdrm->fb) {\n+\t\told_fb = gdrm->fb;\n+\t\tdrm_framebuffer_get(fb);\n+\t\tgdrm->fb = fb;\n+\t}\n+\n+\tgud_add_damage(gdrm, damage);\n+\n+\tmutex_unlock(&gdrm->damage_lock);\n+\n+\tqueue_work(system_long_wq, &gdrm->work);\n+\n+\tif (old_fb)\n+\t\tdrm_framebuffer_put(old_fb);\n+}\n+\n+int gud_pipe_check(struct drm_simple_display_pipe *pipe,\n+\t\t   struct drm_plane_state *new_plane_state,\n+\t\t   struct drm_crtc_state *new_crtc_state)\n+{\n+\tstruct gud_device *gdrm = to_gud_device(pipe->crtc.dev);\n+\tstruct drm_plane_state *old_plane_state = pipe->plane.state;\n+\tconst struct drm_display_mode *mode = &new_crtc_state->mode;\n+\tstruct drm_atomic_state *state = new_plane_state->state;\n+\tstruct drm_framebuffer *old_fb = old_plane_state->fb;\n+\tstruct drm_connector_state *connector_state = NULL;\n+\tstruct drm_framebuffer *fb = new_plane_state->fb;\n+\tconst struct drm_format_info *format = fb->format;\n+\tstruct drm_connector *connector;\n+\tunsigned int i, num_properties;\n+\tstruct gud_state_req *req;\n+\tint idx, ret;\n+\tsize_t len;\n+\n+\tif (WARN_ON_ONCE(!fb))\n+\t\treturn -EINVAL;\n+\n+\tif (old_plane_state->rotation != new_plane_state->rotation)\n+\t\tnew_crtc_state->mode_changed = true;\n+\n+\tif (old_fb && old_fb->format != format)\n+\t\tnew_crtc_state->mode_changed = true;\n+\n+\tif (!new_crtc_state->mode_changed && !new_crtc_state->connectors_changed)\n+\t\treturn 0;\n+\n+\t/* Only one connector is supported */\n+\tif (hweight32(new_crtc_state->connector_mask) != 1)\n+\t\treturn -EINVAL;\n+\n+\tif (format->format == DRM_FORMAT_XRGB8888 && gdrm->xrgb8888_emulation_format)\n+\t\tformat = gdrm->xrgb8888_emulation_format;\n+\n+\tfor_each_new_connector_in_state(state, connector, connector_state, i) {\n+\t\tif (connector_state->crtc)\n+\t\t\tbreak;\n+\t}\n+\n+\t/*\n+\t * DRM_IOCTL_MODE_OBJ_SETPROPERTY on the rotation property will not have\n+\t * the connector included in the state.\n+\t */\n+\tif (!connector_state) {\n+\t\tstruct drm_connector_list_iter conn_iter;\n+\n+\t\tdrm_connector_list_iter_begin(pipe->crtc.dev, &conn_iter);\n+\t\tdrm_for_each_connector_iter(connector, &conn_iter) {\n+\t\t\tif (connector->state->crtc) {\n+\t\t\t\tconnector_state = connector->state;\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t}\n+\t\tdrm_connector_list_iter_end(&conn_iter);\n+\t}\n+\n+\tif (WARN_ON_ONCE(!connector_state))\n+\t\treturn -ENOENT;\n+\n+\tlen = struct_size(req, properties,\n+\t\t\t  GUD_PROPERTIES_MAX_NUM + GUD_CONNECTOR_PROPERTIES_MAX_NUM);\n+\treq = kzalloc(len, GFP_KERNEL);\n+\tif (!req)\n+\t\treturn -ENOMEM;\n+\n+\tgud_from_display_mode(&req->mode, mode);\n+\n+\treq->format = gud_from_fourcc(format->format);\n+\tif (WARN_ON_ONCE(!req->format)) {\n+\t\tret = -EINVAL;\n+\t\tgoto out;\n+\t}\n+\n+\treq->connector = drm_connector_index(connector_state->connector);\n+\n+\tret = gud_connector_fill_properties(connector_state, req->properties);\n+\tif (ret < 0)\n+\t\tgoto out;\n+\n+\tnum_properties = ret;\n+\tfor (i = 0; i < gdrm->num_properties; i++) {\n+\t\tu16 prop = gdrm->properties[i];\n+\t\tu64 val;\n+\n+\t\tswitch (prop) {\n+\t\tcase GUD_PROPERTY_ROTATION:\n+\t\t\t/* DRM UAPI matches the protocol so use value directly */\n+\t\t\tval = new_plane_state->rotation;\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tWARN_ON_ONCE(1);\n+\t\t\tret = -EINVAL;\n+\t\t\tgoto out;\n+\t\t}\n+\n+\t\treq->properties[num_properties + i].prop = cpu_to_le16(prop);\n+\t\treq->properties[num_properties + i].val = cpu_to_le64(val);\n+\t\tnum_properties++;\n+\t}\n+\n+\tif (drm_dev_enter(fb->dev, &idx)) {\n+\t\tlen = struct_size(req, properties, num_properties);\n+\t\tret = gud_usb_set(gdrm, GUD_REQ_SET_STATE_CHECK, 0, req, len);\n+\t\tdrm_dev_exit(idx);\n+\t}  else {\n+\t\tret = -ENODEV;\n+\t}\n+out:\n+\tkfree(req);\n+\n+\treturn ret;\n+}\n+\n+void gud_pipe_update(struct drm_simple_display_pipe *pipe,\n+\t\t     struct drm_plane_state *old_state)\n+{\n+\tstruct drm_device *drm = pipe->crtc.dev;\n+\tstruct gud_device *gdrm = to_gud_device(drm);\n+\tstruct drm_plane_state *state = pipe->plane.state;\n+\tstruct drm_framebuffer *fb = state->fb;\n+\tstruct drm_crtc *crtc = &pipe->crtc;\n+\tstruct drm_rect damage;\n+\tint idx;\n+\n+\tif (crtc->state->mode_changed || !crtc->state->enable) {\n+\t\tcancel_work_sync(&gdrm->work);\n+\t\tmutex_lock(&gdrm->damage_lock);\n+\t\tif (gdrm->fb) {\n+\t\t\tdrm_framebuffer_put(gdrm->fb);\n+\t\t\tgdrm->fb = NULL;\n+\t\t}\n+\t\tgud_clear_damage(gdrm);\n+\t\tmutex_unlock(&gdrm->damage_lock);\n+\t}\n+\n+\tif (!drm_dev_enter(drm, &idx))\n+\t\treturn;\n+\n+\tif (!old_state->fb)\n+\t\tgud_usb_set_u8(gdrm, GUD_REQ_SET_CONTROLLER_ENABLE, 1);\n+\n+\tif (fb && (crtc->state->mode_changed || crtc->state->connectors_changed))\n+\t\tgud_usb_set(gdrm, GUD_REQ_SET_STATE_COMMIT, 0, NULL, 0);\n+\n+\tif (crtc->state->active_changed)\n+\t\tgud_usb_set_u8(gdrm, GUD_REQ_SET_DISPLAY_ENABLE, crtc->state->active);\n+\n+\tif (drm_atomic_helper_damage_merged(old_state, state, &damage)) {\n+\t\tif (gdrm->flags & GUD_DISPLAY_FLAG_FULL_UPDATE)\n+\t\t\tdrm_rect_init(&damage, 0, 0, fb->width, fb->height);\n+\t\tgud_fb_queue_damage(gdrm, fb, &damage);\n+\t}\n+\n+\tif (!crtc->state->enable)\n+\t\tgud_usb_set_u8(gdrm, GUD_REQ_SET_CONTROLLER_ENABLE, 0);\n+\n+\tdrm_dev_exit(idx);\n+}\n--- /dev/null\n+++ b/include/drm/gud.h\n@@ -0,0 +1,333 @@\n+/* SPDX-License-Identifier: MIT */\n+/*\n+ * Copyright 2020 Noralf Trønnes\n+ */\n+\n+#ifndef __LINUX_GUD_H\n+#define __LINUX_GUD_H\n+\n+#include <linux/types.h>\n+\n+/*\n+ * struct gud_display_descriptor_req - Display descriptor\n+ * @magic: Magic value GUD_DISPLAY_MAGIC\n+ * @version: Protocol version\n+ * @flags: Flags\n+ *         - STATUS_ON_SET: Always do a status request after a SET request.\n+ *                          This is used by the Linux gadget driver since it has\n+ *                          no way to control the status stage of a control OUT\n+ *                          request that has a payload.\n+ *         - FULL_UPDATE:   Always send the entire framebuffer when flushing changes.\n+ *                          The GUD_REQ_SET_BUFFER request will not be sent\n+ *                          before each bulk transfer, it will only be sent if the\n+ *                          previous bulk transfer had failed. This gives the device\n+ *                          a chance to reset its state machine if needed.\n+ *                          This flag can not be used in combination with compression.\n+ * @compression: Supported compression types\n+ *               - GUD_COMPRESSION_LZ4: LZ4 lossless compression.\n+ * @max_buffer_size: Maximum buffer size the device can handle (optional).\n+ *                   This is useful for devices that don't have a big enough\n+ *                   buffer to decompress the entire framebuffer in one go.\n+ * @min_width: Minimum pixel width the controller can handle\n+ * @max_width: Maximum width\n+ * @min_height: Minimum height\n+ * @max_height: Maximum height\n+ *\n+ * Devices that have only one display mode will have min_width == max_width\n+ * and min_height == max_height.\n+ */\n+struct gud_display_descriptor_req {\n+\t__le32 magic;\n+#define GUD_DISPLAY_MAGIC\t\t\t0x1d50614d\n+\t__u8 version;\n+\t__le32 flags;\n+#define GUD_DISPLAY_FLAG_STATUS_ON_SET\t\tBIT(0)\n+#define GUD_DISPLAY_FLAG_FULL_UPDATE\t\tBIT(1)\n+\t__u8 compression;\n+#define GUD_COMPRESSION_LZ4\t\t\tBIT(0)\n+\t__le32 max_buffer_size;\n+\t__le32 min_width;\n+\t__le32 max_width;\n+\t__le32 min_height;\n+\t__le32 max_height;\n+} __packed;\n+\n+/*\n+ * struct gud_property_req - Property\n+ * @prop: Property\n+ * @val: Value\n+ */\n+struct gud_property_req {\n+\t__le16 prop;\n+\t__le64 val;\n+} __packed;\n+\n+/*\n+ * struct gud_display_mode_req - Display mode\n+ * @clock: Pixel clock in kHz\n+ * @hdisplay: Horizontal display size\n+ * @hsync_start: Horizontal sync start\n+ * @hsync_end: Horizontal sync end\n+ * @htotal: Horizontal total size\n+ * @vdisplay: Vertical display size\n+ * @vsync_start: Vertical sync start\n+ * @vsync_end: Vertical sync end\n+ * @vtotal: Vertical total size\n+ * @flags: Bits 0-13 are the same as in the RandR protocol and also what DRM uses.\n+ *         The deprecated bits are reused for internal protocol flags leaving us\n+ *         free to follow DRM for the other bits in the future.\n+ *         - FLAG_PREFERRED: Set on the preferred display mode.\n+ */\n+struct gud_display_mode_req {\n+\t__le32 clock;\n+\t__le16 hdisplay;\n+\t__le16 hsync_start;\n+\t__le16 hsync_end;\n+\t__le16 htotal;\n+\t__le16 vdisplay;\n+\t__le16 vsync_start;\n+\t__le16 vsync_end;\n+\t__le16 vtotal;\n+\t__le32 flags;\n+#define GUD_DISPLAY_MODE_FLAG_PHSYNC\t\tBIT(0)\n+#define GUD_DISPLAY_MODE_FLAG_NHSYNC\t\tBIT(1)\n+#define GUD_DISPLAY_MODE_FLAG_PVSYNC\t\tBIT(2)\n+#define GUD_DISPLAY_MODE_FLAG_NVSYNC\t\tBIT(3)\n+#define GUD_DISPLAY_MODE_FLAG_INTERLACE\t\tBIT(4)\n+#define GUD_DISPLAY_MODE_FLAG_DBLSCAN\t\tBIT(5)\n+#define GUD_DISPLAY_MODE_FLAG_CSYNC\t\tBIT(6)\n+#define GUD_DISPLAY_MODE_FLAG_PCSYNC\t\tBIT(7)\n+#define GUD_DISPLAY_MODE_FLAG_NCSYNC\t\tBIT(8)\n+#define GUD_DISPLAY_MODE_FLAG_HSKEW\t\tBIT(9)\n+/* BCast and PixelMultiplex are deprecated */\n+#define GUD_DISPLAY_MODE_FLAG_DBLCLK\t\tBIT(12)\n+#define GUD_DISPLAY_MODE_FLAG_CLKDIV2\t\tBIT(13)\n+#define GUD_DISPLAY_MODE_FLAG_USER_MASK\t\t\\\n+\t\t(GUD_DISPLAY_MODE_FLAG_PHSYNC | GUD_DISPLAY_MODE_FLAG_NHSYNC | \\\n+\t\tGUD_DISPLAY_MODE_FLAG_PVSYNC | GUD_DISPLAY_MODE_FLAG_NVSYNC | \\\n+\t\tGUD_DISPLAY_MODE_FLAG_INTERLACE | GUD_DISPLAY_MODE_FLAG_DBLSCAN | \\\n+\t\tGUD_DISPLAY_MODE_FLAG_CSYNC | GUD_DISPLAY_MODE_FLAG_PCSYNC | \\\n+\t\tGUD_DISPLAY_MODE_FLAG_NCSYNC | GUD_DISPLAY_MODE_FLAG_HSKEW | \\\n+\t\tGUD_DISPLAY_MODE_FLAG_DBLCLK | GUD_DISPLAY_MODE_FLAG_CLKDIV2)\n+/* Internal protocol flags */\n+#define GUD_DISPLAY_MODE_FLAG_PREFERRED\t\tBIT(10)\n+} __packed;\n+\n+/*\n+ * struct gud_connector_descriptor_req - Connector descriptor\n+ * @connector_type: Connector type (GUD_CONNECTOR_TYPE_*).\n+ *                  If the host doesn't support the type it should fall back to PANEL.\n+ * @flags: Flags\n+ *         - POLL_STATUS: Connector status can change (polled every 10 seconds)\n+ *         - INTERLACE: Interlaced modes are supported\n+ *         - DOUBLESCAN: Doublescan modes are supported\n+ */\n+struct gud_connector_descriptor_req {\n+\t__u8 connector_type;\n+#define GUD_CONNECTOR_TYPE_PANEL\t\t0\n+#define GUD_CONNECTOR_TYPE_VGA\t\t\t1\n+#define GUD_CONNECTOR_TYPE_COMPOSITE\t\t2\n+#define GUD_CONNECTOR_TYPE_SVIDEO\t\t3\n+#define GUD_CONNECTOR_TYPE_COMPONENT\t\t4\n+#define GUD_CONNECTOR_TYPE_DVI\t\t\t5\n+#define GUD_CONNECTOR_TYPE_DISPLAYPORT\t\t6\n+#define GUD_CONNECTOR_TYPE_HDMI\t\t\t7\n+\t__le32 flags;\n+#define GUD_CONNECTOR_FLAGS_POLL_STATUS\t\tBIT(0)\n+#define GUD_CONNECTOR_FLAGS_INTERLACE\t\tBIT(1)\n+#define GUD_CONNECTOR_FLAGS_DOUBLESCAN\t\tBIT(2)\n+} __packed;\n+\n+/*\n+ * struct gud_set_buffer_req - Set buffer transfer info\n+ * @x: X position of rectangle\n+ * @y: Y position\n+ * @width: Pixel width of rectangle\n+ * @height: Pixel height\n+ * @length: Buffer length in bytes\n+ * @compression: Transfer compression\n+ * @compressed_length: Compressed buffer length\n+ *\n+ * This request is issued right before the bulk transfer.\n+ * @x, @y, @width and @height specifies the rectangle where the buffer should be\n+ * placed inside the framebuffer.\n+ */\n+struct gud_set_buffer_req {\n+\t__le32 x;\n+\t__le32 y;\n+\t__le32 width;\n+\t__le32 height;\n+\t__le32 length;\n+\t__u8 compression;\n+\t__le32 compressed_length;\n+} __packed;\n+\n+/*\n+ * struct gud_state_req - Display state\n+ * @mode: Display mode\n+ * @format: Pixel format GUD_PIXEL_FORMAT_*\n+ * @connector: Connector index\n+ * @properties: Array of properties\n+ *\n+ * The entire state is transferred each time there's a change.\n+ */\n+struct gud_state_req {\n+\tstruct gud_display_mode_req mode;\n+\t__u8 format;\n+\t__u8 connector;\n+\tstruct gud_property_req properties[];\n+} __packed;\n+\n+/* List of supported connector properties: */\n+\n+/* Margins in pixels to deal with overscan, range 0-100 */\n+#define GUD_PROPERTY_TV_LEFT_MARGIN\t\t\t1\n+#define GUD_PROPERTY_TV_RIGHT_MARGIN\t\t\t2\n+#define GUD_PROPERTY_TV_TOP_MARGIN\t\t\t3\n+#define GUD_PROPERTY_TV_BOTTOM_MARGIN\t\t\t4\n+#define GUD_PROPERTY_TV_MODE\t\t\t\t5\n+/* Brightness in percent, range 0-100 */\n+#define GUD_PROPERTY_TV_BRIGHTNESS\t\t\t6\n+/* Contrast in percent, range 0-100 */\n+#define GUD_PROPERTY_TV_CONTRAST\t\t\t7\n+/* Flicker reduction in percent, range 0-100 */\n+#define GUD_PROPERTY_TV_FLICKER_REDUCTION\t\t8\n+/* Overscan in percent, range 0-100 */\n+#define GUD_PROPERTY_TV_OVERSCAN\t\t\t9\n+/* Saturation in percent, range 0-100 */\n+#define GUD_PROPERTY_TV_SATURATION\t\t\t10\n+/* Hue in percent, range 0-100 */\n+#define GUD_PROPERTY_TV_HUE\t\t\t\t11\n+\n+/*\n+ * Backlight brightness is in the range 0-100 inclusive. The value represents the human perceptual\n+ * brightness and not a linear PWM value. 0 is minimum brightness which should not turn the\n+ * backlight completely off. The DPMS connector property should be used to control power which will\n+ * trigger a GUD_REQ_SET_DISPLAY_ENABLE request.\n+ *\n+ * This does not map to a DRM property, it is used with the backlight device.\n+ */\n+#define GUD_PROPERTY_BACKLIGHT_BRIGHTNESS\t\t12\n+\n+/* List of supported properties that are not connector propeties: */\n+\n+/*\n+ * Plane rotation. Should return the supported bitmask on\n+ * GUD_REQ_GET_PROPERTIES. GUD_ROTATION_0 is mandatory.\n+ *\n+ * Note: This is not display rotation so 90/270 will need scaling to make it fit (unless squared).\n+ */\n+#define GUD_PROPERTY_ROTATION\t\t\t\t50\n+  #define GUD_ROTATION_0\t\t\tBIT(0)\n+  #define GUD_ROTATION_90\t\t\tBIT(1)\n+  #define GUD_ROTATION_180\t\t\tBIT(2)\n+  #define GUD_ROTATION_270\t\t\tBIT(3)\n+  #define GUD_ROTATION_REFLECT_X\t\tBIT(4)\n+  #define GUD_ROTATION_REFLECT_Y\t\tBIT(5)\n+  #define GUD_ROTATION_MASK\t\t\t(GUD_ROTATION_0 | GUD_ROTATION_90 | \\\n+\t\t\t\t\t\tGUD_ROTATION_180 | GUD_ROTATION_270 | \\\n+\t\t\t\t\t\tGUD_ROTATION_REFLECT_X | GUD_ROTATION_REFLECT_Y)\n+\n+/* USB Control requests: */\n+\n+/* Get status from the last GET/SET control request. Value is u8. */\n+#define GUD_REQ_GET_STATUS\t\t\t\t0x00\n+  /* Status values: */\n+  #define GUD_STATUS_OK\t\t\t\t0x00\n+  #define GUD_STATUS_BUSY\t\t\t0x01\n+  #define GUD_STATUS_REQUEST_NOT_SUPPORTED\t0x02\n+  #define GUD_STATUS_PROTOCOL_ERROR\t\t0x03\n+  #define GUD_STATUS_INVALID_PARAMETER\t\t0x04\n+  #define GUD_STATUS_ERROR\t\t\t0x05\n+\n+/* Get display descriptor as a &gud_display_descriptor_req */\n+#define GUD_REQ_GET_DESCRIPTOR\t\t\t\t0x01\n+\n+/* Get supported pixel formats as a byte array of GUD_PIXEL_FORMAT_* */\n+#define GUD_REQ_GET_FORMATS\t\t\t\t0x40\n+  #define GUD_FORMATS_MAX_NUM\t\t\t32\n+  /* R1 is a 1-bit monochrome transfer format presented to userspace as XRGB8888 */\n+  #define GUD_PIXEL_FORMAT_R1\t\t\t0x01\n+  #define GUD_PIXEL_FORMAT_XRGB1111\t\t0x20\n+  #define GUD_PIXEL_FORMAT_RGB565\t\t0x40\n+  #define GUD_PIXEL_FORMAT_XRGB8888\t\t0x80\n+  #define GUD_PIXEL_FORMAT_ARGB8888\t\t0x81\n+\n+/*\n+ * Get supported properties that are not connector propeties as a &gud_property_req array.\n+ * gud_property_req.val often contains the initial value for the property.\n+ */\n+#define GUD_REQ_GET_PROPERTIES\t\t\t\t0x41\n+  #define GUD_PROPERTIES_MAX_NUM\t\t32\n+\n+/* Connector requests have the connector index passed in the wValue field */\n+\n+/* Get connector descriptors as an array of &gud_connector_descriptor_req */\n+#define GUD_REQ_GET_CONNECTORS\t\t\t\t0x50\n+  #define GUD_CONNECTORS_MAX_NUM\t\t32\n+\n+/*\n+ * Get properties supported by the connector as a &gud_property_req array.\n+ * gud_property_req.val often contains the initial value for the property.\n+ */\n+#define GUD_REQ_GET_CONNECTOR_PROPERTIES\t\t0x51\n+  #define GUD_CONNECTOR_PROPERTIES_MAX_NUM\t32\n+\n+/*\n+ * Issued when there's a TV_MODE property present.\n+ * Gets an array of the supported TV_MODE names each entry of length\n+ * GUD_CONNECTOR_TV_MODE_NAME_LEN. Names must be NUL-terminated.\n+ */\n+#define GUD_REQ_GET_CONNECTOR_TV_MODE_VALUES\t\t0x52\n+  #define GUD_CONNECTOR_TV_MODE_NAME_LEN\t16\n+  #define GUD_CONNECTOR_TV_MODE_MAX_NUM\t\t16\n+\n+/* When userspace checks connector status, this is issued first, not used for poll requests. */\n+#define GUD_REQ_SET_CONNECTOR_FORCE_DETECT\t\t0x53\n+\n+/*\n+ * Get connector status. Value is u8.\n+ *\n+ * Userspace will get a HOTPLUG uevent if one of the following is true:\n+ * - Connection status has changed since last\n+ * - CHANGED is set\n+ */\n+#define GUD_REQ_GET_CONNECTOR_STATUS\t\t\t0x54\n+  #define GUD_CONNECTOR_STATUS_DISCONNECTED\t0x00\n+  #define GUD_CONNECTOR_STATUS_CONNECTED\t0x01\n+  #define GUD_CONNECTOR_STATUS_UNKNOWN\t\t0x02\n+  #define GUD_CONNECTOR_STATUS_CONNECTED_MASK\t0x03\n+  #define GUD_CONNECTOR_STATUS_CHANGED\t\tBIT(7)\n+\n+/*\n+ * Display modes can be fetched as either EDID data or an array of &gud_display_mode_req.\n+ *\n+ * If GUD_REQ_GET_CONNECTOR_MODES returns zero, EDID is used to create display modes.\n+ * If both display modes and EDID are returned, EDID is just passed on to userspace\n+ * in the EDID connector property.\n+ */\n+\n+/* Get &gud_display_mode_req array of supported display modes */\n+#define GUD_REQ_GET_CONNECTOR_MODES\t\t\t0x55\n+  #define GUD_CONNECTOR_MAX_NUM_MODES\t\t128\n+\n+/* Get Extended Display Identification Data */\n+#define GUD_REQ_GET_CONNECTOR_EDID\t\t\t0x56\n+  #define GUD_CONNECTOR_MAX_EDID_LEN\t\t2048\n+\n+/* Set buffer properties before bulk transfer as &gud_set_buffer_req */\n+#define GUD_REQ_SET_BUFFER\t\t\t\t0x60\n+\n+/* Check display configuration as &gud_state_req */\n+#define GUD_REQ_SET_STATE_CHECK\t\t\t\t0x61\n+\n+/* Apply the previous STATE_CHECK configuration */\n+#define GUD_REQ_SET_STATE_COMMIT\t\t\t0x62\n+\n+/* Enable/disable the display controller, value is u8: 0/1 */\n+#define GUD_REQ_SET_CONTROLLER_ENABLE\t\t\t0x63\n+\n+/* Enable/disable display/output (DPMS), value is u8: 0/1 */\n+#define GUD_REQ_SET_DISPLAY_ENABLE\t\t\t0x64\n+\n+#endif\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0710-drm-gud-fix-sizeof-use.patch",
    "content": "From 7496cbd572b0f5266fd752f6182b3f138a4ff0e6 Mon Sep 17 00:00:00 2001\nFrom: kernel test robot <lkp@intel.com>\nDate: Mon, 22 Mar 2021 18:44:33 +0100\nSubject: [PATCH] drm/gud: fix sizeof use\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\n[ Upstream commit b91fbdc1df15befb3e51b9795b15d71fa4298602 ]\n\ndrivers/gpu/drm/gud/gud_connector.c:710:37-43: ERROR: application of sizeof to pointer\n\n sizeof when applied to a pointer typed expression gives the size of\n the pointer\n\nGenerated by: scripts/coccinelle/misc/noderef.cocci\n\nFixes: 40e1a70b4aed (\"drm: Add GUD USB Display driver\")\nReported-by: kernel test robot <lkp@intel.com>\nSigned-off-by: kernel test robot <lkp@intel.com>\n[fix subject]\nSigned-off-by: Noralf Trønnes <noralf@tronnes.org>\nLink: https://patchwork.freedesktop.org/patch/msgid/20210322174434.58849-1-noralf@tronnes.org\n---\n drivers/gpu/drm/gud/gud_connector.c | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/drivers/gpu/drm/gud/gud_connector.c\n+++ b/drivers/gpu/drm/gud/gud_connector.c\n@@ -707,7 +707,7 @@ int gud_get_connectors(struct gud_device\n \t\treturn -ENOMEM;\n \n \tret = gud_usb_get(gdrm, GUD_REQ_GET_CONNECTORS, 0,\n-\t\t\t  descs, GUD_CONNECTORS_MAX_NUM * sizeof(descs));\n+\t\t\t  descs, GUD_CONNECTORS_MAX_NUM * sizeof(*descs));\n \tif (ret < 0)\n \t\tgoto free;\n \tif (!ret || ret % sizeof(*descs)) {\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0711-drm-gud-Remove-unneeded-semicolon.patch",
    "content": "From f163b3a83a57e4a6946555fa6e363c7d89bfc380 Mon Sep 17 00:00:00 2001\nFrom: kernel test robot <lkp@intel.com>\nDate: Mon, 22 Mar 2021 18:44:34 +0100\nSubject: [PATCH] drm/gud: Remove unneeded semicolon\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\n[ Upstream commit 166633c85c21fbe0baec40c898ca5a4f6eee0a08 ]\n\ndrivers/gpu/drm/gud/gud_connector.c:658:2-3: Unneeded semicolon\ndrivers/gpu/drm/gud/gud_connector.c:186:2-3: Unneeded semicolon\ndrivers/gpu/drm/gud/gud_drv.c:511:3-4: Unneeded semicolon\ndrivers/gpu/drm/gud/gud_pipe.c:127:4-5: Unneeded semicolon\n\n Remove unneeded semicolon.\n\nGenerated by: scripts/coccinelle/misc/semicolon.cocci\n\nFixes: 40e1a70b4aed (\"drm: Add GUD USB Display driver\")\nReported-by: kernel test robot <lkp@intel.com>\nSigned-off-by: kernel test robot <lkp@intel.com>\n[fix subject and squash 3 per file patches]\nSigned-off-by: Noralf Trønnes <noralf@tronnes.org>\nLink: https://patchwork.freedesktop.org/patch/msgid/20210322174434.58849-2-noralf@tronnes.org\n---\n drivers/gpu/drm/gud/gud_connector.c | 4 ++--\n drivers/gpu/drm/gud/gud_drv.c       | 2 +-\n drivers/gpu/drm/gud/gud_pipe.c      | 2 +-\n 3 files changed, 4 insertions(+), 4 deletions(-)\n\n--- a/drivers/gpu/drm/gud/gud_connector.c\n+++ b/drivers/gpu/drm/gud/gud_connector.c\n@@ -183,7 +183,7 @@ static int gud_connector_detect(struct d\n \tdefault:\n \t\tret = connector_status_unknown;\n \t\tbreak;\n-\t};\n+\t}\n \n \tif (status & GUD_CONNECTOR_STATUS_CHANGED)\n \t\tconnector->epoch_counter += 1;\n@@ -655,7 +655,7 @@ static int gud_connector_create(struct g\n \tdefault: /* future types */\n \t\tconnector_type = DRM_MODE_CONNECTOR_USB;\n \t\tbreak;\n-\t};\n+\t}\n \n \tdrm_connector_helper_add(connector, &gud_connector_helper_funcs);\n \tret = drm_connector_init(drm, connector, &gud_connector_funcs, connector_type);\n--- a/drivers/gpu/drm/gud/gud_drv.c\n+++ b/drivers/gpu/drm/gud/gud_drv.c\n@@ -521,7 +521,7 @@ static int gud_probe(struct usb_interfac\n \t\tcase DRM_FORMAT_XRGB8888:\n \t\t\txrgb8888_supported = true;\n \t\t\tbreak;\n-\t\t};\n+\t\t}\n \n \t\tfmt_buf_size = drm_format_info_min_pitch(info, 0, drm->mode_config.max_width) *\n \t\t\t       drm->mode_config.max_height;\n--- a/drivers/gpu/drm/gud/gud_pipe.c\n+++ b/drivers/gpu/drm/gud/gud_pipe.c\n@@ -124,7 +124,7 @@ static size_t gud_xrgb8888_to_color(u8 *\n \t\t\tdefault:\n \t\t\t\tWARN_ON_ONCE(1);\n \t\t\t\treturn len;\n-\t\t\t};\n+\t\t\t}\n \n \t\t\t*block |= pix << pixshift;\n \t\t}\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0712-drm-gud-cleanup-coding-style-a-bit.patch",
    "content": "From a70cf7096e7171131db2689a0111c08b5f7bd764 Mon Sep 17 00:00:00 2001\nFrom: Bernard Zhao <bernard@vivo.com>\nDate: Fri, 2 Apr 2021 01:55:21 -0700\nSubject: [PATCH] drm/gud: cleanup coding style a bit\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\n[ Upstream commit 6dd7efc437611db16d432e0030f72d0c7e890127 ]\n\nFix coccicheck warning:\ndrivers/gpu/drm/gud/gud_internal.h:89:2-3: Unneeded semicolon\ndrivers/gpu/drm/gud/gud_internal.h:107:2-3: Unneeded semicolon\n\nSigned-off-by: Bernard Zhao <bernard@vivo.com>\nSigned-off-by: Noralf Trønnes <noralf@tronnes.org>\nLink: https://patchwork.freedesktop.org/patch/msgid/20210402085523.76928-1-bernard@vivo.com\n---\n drivers/gpu/drm/gud/gud_internal.h | 4 ++--\n 1 file changed, 2 insertions(+), 2 deletions(-)\n\n--- a/drivers/gpu/drm/gud/gud_internal.h\n+++ b/drivers/gpu/drm/gud/gud_internal.h\n@@ -86,7 +86,7 @@ static inline u8 gud_from_fourcc(u32 fou\n \t\treturn GUD_PIXEL_FORMAT_XRGB8888;\n \tcase DRM_FORMAT_ARGB8888:\n \t\treturn GUD_PIXEL_FORMAT_ARGB8888;\n-\t};\n+\t}\n \n \treturn 0;\n }\n@@ -104,7 +104,7 @@ static inline u32 gud_to_fourcc(u8 forma\n \t\treturn DRM_FORMAT_XRGB8888;\n \tcase GUD_PIXEL_FORMAT_ARGB8888:\n \t\treturn DRM_FORMAT_ARGB8888;\n-\t};\n+\t}\n \n \treturn 0;\n }\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0713-drm-gud-Free-buffers-on-device-removal.patch",
    "content": "From 888d867aa6f8fe384b37c0915eed07bb3a970fc4 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Noralf=20Tr=C3=B8nnes?= <noralf@tronnes.org>\nDate: Thu, 1 Jul 2021 19:07:47 +0200\nSubject: [PATCH] drm/gud: Free buffers on device removal\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\n[ drm-misc commit f8ac863b6a93863334cefb94285daaa6617381b5 ]\n\nFree transfer and compression buffers on device removal instead of at\nDRM device removal time. This ensures that the usual 2x8MB buffers are\nreleased when the device is unplugged and not kept around should\nuserspace keep the DRM device fd open.\n\nAt least Ubuntu 20.04 doesn't release the DRM device on unplug.\n\nThe damage_lock mutex is not destroyed because it is used outside the\ndrm_dev_enter/exit block in gud_pipe_update(). AFAICT it's possible for\nan open fbdev descriptor to trigger a commit after the USB device is gone.\n\nv2: Don't destroy damage_lock\n\nReviewed-by: Linus Walleij <linus.walleij@linaro.org>\nSigned-off-by: Noralf Trønnes <noralf@tronnes.org>\nLink: https://patchwork.freedesktop.org/patch/msgid/20210701170748.58009-1-noralf@tronnes.org\n---\n drivers/gpu/drm/gud/gud_drv.c | 9 +++++----\n 1 file changed, 5 insertions(+), 4 deletions(-)\n\n--- a/drivers/gpu/drm/gud/gud_drv.c\n+++ b/drivers/gpu/drm/gud/gud_drv.c\n@@ -407,14 +407,15 @@ static struct drm_driver gud_drm_driver\n \t.minor\t\t\t= 0,\n };\n \n-static void gud_free_buffers_and_mutex(struct drm_device *drm, void *unused)\n+static void gud_free_buffers_and_mutex(void *data)\n {\n-\tstruct gud_device *gdrm = to_gud_device(drm);\n+\tstruct gud_device *gdrm = data;\n \n \tvfree(gdrm->compress_buf);\n+\tgdrm->compress_buf = NULL;\n \tkfree(gdrm->bulk_buf);\n+\tgdrm->bulk_buf = NULL;\n \tmutex_destroy(&gdrm->ctrl_lock);\n-\tmutex_destroy(&gdrm->damage_lock);\n }\n \n static int gud_probe(struct usb_interface *intf, const struct usb_device_id *id)\n@@ -468,7 +469,7 @@ static int gud_probe(struct usb_interfac\n \tINIT_WORK(&gdrm->work, gud_flush_work);\n \tgud_clear_damage(gdrm);\n \n-\tret = drmm_add_action_or_reset(drm, gud_free_buffers_and_mutex, NULL);\n+\tret = devm_add_action(dev, gud_free_buffers_and_mutex, gdrm);\n \tif (ret)\n \t\treturn ret;\n \n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0714-drm-gud-Use-scatter-gather-USB-bulk-transfer.patch",
    "content": "From 1cff637824f8e5626a754cbbb97bc8f3730a88f0 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Noralf=20Tr=C3=B8nnes?= <noralf@tronnes.org>\nDate: Thu, 1 Jul 2021 19:07:48 +0200\nSubject: [PATCH] drm/gud: Use scatter-gather USB bulk transfer\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\n[ drm-misc commit 2eecd93b743b5611cd3654698794b4d0cefdc9ee ]\n\nThere'a limit to how big a kmalloc buffer can be, and as memory gets\nfragmented it becomes more difficult to get big buffers. The downside of\nsmaller buffers is that the driver has to split the transfer up which\nhampers performance. Compression might also take a hit because of the\nsplitting.\n\nSolve this by allocating the transfer buffer using vmalloc and create a\nSG table to be passed on to the USB subsystem. vmalloc_32() is used to\navoid DMA bounce buffers on USB controllers that can only access 32-bit\naddresses.\n\nThis also solves the problem that split transfers can give host side\ntearing since flushing is decoupled from rendering.\n\nusb_sg_wait() doesn't have timeout handling builtin, so it is wrapped in\na timer like 4 out of 6 users in the kernel have done.\n\nv2:\n- Use DIV_ROUND_UP (Linus)\n- Add timeout note to the commit log (Linus)\n- Expand note about upper buffer limit (Linus)\n- Change var name s/timer/ctx/ in gud_usb_bulk_timeout()\n\nReviewed-by: Linus Walleij <linus.walleij@linaro.org>\nSigned-off-by: Noralf Trønnes <noralf@tronnes.org>\nLink: https://patchwork.freedesktop.org/patch/msgid/20210701170748.58009-2-noralf@tronnes.org\n---\n drivers/gpu/drm/gud/gud_drv.c      | 50 +++++++++++++++++++++---------\n drivers/gpu/drm/gud/gud_internal.h |  2 ++\n drivers/gpu/drm/gud/gud_pipe.c     | 47 ++++++++++++++++++++++++----\n 3 files changed, 78 insertions(+), 21 deletions(-)\n\n--- a/drivers/gpu/drm/gud/gud_drv.c\n+++ b/drivers/gpu/drm/gud/gud_drv.c\n@@ -407,13 +407,40 @@ static struct drm_driver gud_drm_driver\n \t.minor\t\t\t= 0,\n };\n \n+static int gud_alloc_bulk_buffer(struct gud_device *gdrm)\n+{\n+\tunsigned int i, num_pages;\n+\tstruct page **pages;\n+\tvoid *ptr;\n+\tint ret;\n+\n+\tgdrm->bulk_buf = vmalloc_32(gdrm->bulk_len);\n+\tif (!gdrm->bulk_buf)\n+\t\treturn -ENOMEM;\n+\n+\tnum_pages = DIV_ROUND_UP(gdrm->bulk_len, PAGE_SIZE);\n+\tpages = kmalloc_array(num_pages, sizeof(struct page *), GFP_KERNEL);\n+\tif (!pages)\n+\t\treturn -ENOMEM;\n+\n+\tfor (i = 0, ptr = gdrm->bulk_buf; i < num_pages; i++, ptr += PAGE_SIZE)\n+\t\tpages[i] = vmalloc_to_page(ptr);\n+\n+\tret = sg_alloc_table_from_pages(&gdrm->bulk_sgt, pages, num_pages,\n+\t\t\t\t\t0, gdrm->bulk_len, GFP_KERNEL);\n+\tkfree(pages);\n+\n+\treturn ret;\n+}\n+\n static void gud_free_buffers_and_mutex(void *data)\n {\n \tstruct gud_device *gdrm = data;\n \n \tvfree(gdrm->compress_buf);\n \tgdrm->compress_buf = NULL;\n-\tkfree(gdrm->bulk_buf);\n+\tsg_free_table(&gdrm->bulk_sgt);\n+\tvfree(gdrm->bulk_buf);\n \tgdrm->bulk_buf = NULL;\n \tmutex_destroy(&gdrm->ctrl_lock);\n }\n@@ -550,24 +577,17 @@ static int gud_probe(struct usb_interfac\n \n \tif (desc.max_buffer_size)\n \t\tmax_buffer_size = le32_to_cpu(desc.max_buffer_size);\n-retry:\n-\t/*\n-\t * Use plain kmalloc here since devm_kmalloc() places struct devres at the beginning\n-\t * of the buffer it allocates. This wastes a lot of memory when allocating big buffers.\n-\t * Asking for 2M would actually allocate 4M. This would also prevent getting the biggest\n-\t * possible buffer potentially leading to split transfers.\n-\t */\n-\tgdrm->bulk_buf = kmalloc(max_buffer_size, GFP_KERNEL | __GFP_NOWARN);\n-\tif (!gdrm->bulk_buf) {\n-\t\tmax_buffer_size = roundup_pow_of_two(max_buffer_size) / 2;\n-\t\tif (max_buffer_size < SZ_512K)\n-\t\t\treturn -ENOMEM;\n-\t\tgoto retry;\n-\t}\n+\t/* Prevent a misbehaving device from allocating loads of RAM. 4096x4096@XRGB8888 = 64 MB */\n+\tif (max_buffer_size > SZ_64M)\n+\t\tmax_buffer_size = SZ_64M;\n \n \tgdrm->bulk_pipe = usb_sndbulkpipe(interface_to_usbdev(intf), usb_endpoint_num(bulk_out));\n \tgdrm->bulk_len = max_buffer_size;\n \n+\tret = gud_alloc_bulk_buffer(gdrm);\n+\tif (ret)\n+\t\treturn ret;\n+\n \tif (gdrm->compression & GUD_COMPRESSION_LZ4) {\n \t\tgdrm->lz4_comp_mem = devm_kmalloc(dev, LZ4_MEM_COMPRESS, GFP_KERNEL);\n \t\tif (!gdrm->lz4_comp_mem)\n--- a/drivers/gpu/drm/gud/gud_internal.h\n+++ b/drivers/gpu/drm/gud/gud_internal.h\n@@ -5,6 +5,7 @@\n \n #include <linux/list.h>\n #include <linux/mutex.h>\n+#include <linux/scatterlist.h>\n #include <linux/usb.h>\n #include <linux/workqueue.h>\n #include <uapi/drm/drm_fourcc.h>\n@@ -26,6 +27,7 @@ struct gud_device {\n \tunsigned int bulk_pipe;\n \tvoid *bulk_buf;\n \tsize_t bulk_len;\n+\tstruct sg_table bulk_sgt;\n \n \tu8 compression;\n \tvoid *lz4_comp_mem;\n--- a/drivers/gpu/drm/gud/gud_pipe.c\n+++ b/drivers/gpu/drm/gud/gud_pipe.c\n@@ -219,13 +219,51 @@ vunmap:\n \treturn ret;\n }\n \n+struct gud_usb_bulk_context {\n+\tstruct timer_list timer;\n+\tstruct usb_sg_request sgr;\n+};\n+\n+static void gud_usb_bulk_timeout(struct timer_list *t)\n+{\n+\tstruct gud_usb_bulk_context *ctx = from_timer(ctx, t, timer);\n+\n+\tusb_sg_cancel(&ctx->sgr);\n+}\n+\n+static int gud_usb_bulk(struct gud_device *gdrm, size_t len)\n+{\n+\tstruct gud_usb_bulk_context ctx;\n+\tint ret;\n+\n+\tret = usb_sg_init(&ctx.sgr, gud_to_usb_device(gdrm), gdrm->bulk_pipe, 0,\n+\t\t\t  gdrm->bulk_sgt.sgl, gdrm->bulk_sgt.nents, len, GFP_KERNEL);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\ttimer_setup_on_stack(&ctx.timer, gud_usb_bulk_timeout, 0);\n+\tmod_timer(&ctx.timer, jiffies + msecs_to_jiffies(3000));\n+\n+\tusb_sg_wait(&ctx.sgr);\n+\n+\tif (!del_timer_sync(&ctx.timer))\n+\t\tret = -ETIMEDOUT;\n+\telse if (ctx.sgr.status < 0)\n+\t\tret = ctx.sgr.status;\n+\telse if (ctx.sgr.bytes != len)\n+\t\tret = -EIO;\n+\n+\tdestroy_timer_on_stack(&ctx.timer);\n+\n+\treturn ret;\n+}\n+\n static int gud_flush_rect(struct gud_device *gdrm, struct drm_framebuffer *fb,\n \t\t\t  const struct drm_format_info *format, struct drm_rect *rect)\n {\n-\tstruct usb_device *usb = gud_to_usb_device(gdrm);\n \tstruct gud_set_buffer_req req;\n-\tint ret, actual_length;\n \tsize_t len, trlen;\n+\tint ret;\n \n \tdrm_dbg(&gdrm->drm, \"Flushing [FB:%d] \" DRM_RECT_FMT \"\\n\", fb->base.id, DRM_RECT_ARG(rect));\n \n@@ -254,10 +292,7 @@ static int gud_flush_rect(struct gud_dev\n \t\t\treturn ret;\n \t}\n \n-\tret = usb_bulk_msg(usb, gdrm->bulk_pipe, gdrm->bulk_buf, trlen,\n-\t\t\t   &actual_length, msecs_to_jiffies(3000));\n-\tif (!ret && trlen != actual_length)\n-\t\tret = -EIO;\n+\tret = gud_usb_bulk(gdrm, trlen);\n \tif (ret)\n \t\tgdrm->stats_num_errors++;\n \n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0715-drm-gud-Add-Raspberry-Pi-Pico-ID.patch",
    "content": "From 57f251cd4c0172cd080ca83994e794b1b6515148 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Noralf=20Tr=C3=B8nnes?= <noralf@tronnes.org>\nDate: Sat, 3 Jul 2021 16:13:20 +0200\nSubject: [PATCH] drm/gud: Add Raspberry Pi Pico ID\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\n[ drm-misc commit b3f4ef669357d5b9a2c5e8c33e3967a2070db7f9 ]\n\nAdd VID/PID for the Raspberry Pi Pico implementation.\nSource: https://github.com/notro/gud-pico\n\nCc: Linus Walleij <linus.walleij@linaro.org>\nSigned-off-by: Noralf Trønnes <noralf@tronnes.org>\nReviewed-by: Peter Stuge <peter@stuge.se>\nLink: https://patchwork.freedesktop.org/patch/msgid/20210703141321.35494-1-noralf@tronnes.org\n---\n drivers/gpu/drm/gud/gud_drv.c | 1 +\n 1 file changed, 1 insertion(+)\n\n--- a/drivers/gpu/drm/gud/gud_drv.c\n+++ b/drivers/gpu/drm/gud/gud_drv.c\n@@ -674,6 +674,7 @@ static int gud_resume(struct usb_interfa\n \n static const struct usb_device_id gud_id_table[] = {\n \t{ USB_DEVICE_INTERFACE_CLASS(0x1d50, 0x614d, USB_CLASS_VENDOR_SPEC) },\n+\t{ USB_DEVICE_INTERFACE_CLASS(0x16d0, 0x10a9, USB_CLASS_VENDOR_SPEC) },\n \t{ }\n };\n \n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0716-drm-gud-Add-async_flush-module-parameter.patch",
    "content": "From e0eb7ca2dd07ca8878b67cc20e75f9d7e46d80f4 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Noralf=20Tr=C3=B8nnes?= <noralf@tronnes.org>\nDate: Sat, 3 Jul 2021 16:13:21 +0200\nSubject: [PATCH] drm/gud: Add async_flush module parameter\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\n[ drm-misc commit a0356899ebe8ecde0da9c5685cc47154db973a5e ]\n\nProvide a way for userspace to choose synchronous flushing/pageflips.\nThis helps save CPU and power.\n\nIt is also useful for test scripts since userspace can know when a flush\nhas happended and wait before doing the next visual test.\n\nCc: Linus Walleij <linus.walleij@linaro.org>\nSigned-off-by: Noralf Trønnes <noralf@tronnes.org>\nReviewed-by: Peter Stuge <peter@stuge.se>\nLink: https://patchwork.freedesktop.org/patch/msgid/20210703141321.35494-2-noralf@tronnes.org\n---\n drivers/gpu/drm/gud/gud_pipe.c | 15 +++++++++++++++\n 1 file changed, 15 insertions(+)\n\n--- a/drivers/gpu/drm/gud/gud_pipe.c\n+++ b/drivers/gpu/drm/gud/gud_pipe.c\n@@ -24,6 +24,19 @@\n #include \"gud_internal.h\"\n \n /*\n+ * Some userspace rendering loops runs all displays in the same loop.\n+ * This means that a fast display will have to wait for a slow one.\n+ * For this reason gud does flushing asynchronous by default.\n+ * The down side is that in e.g. a single display setup userspace thinks\n+ * the display is insanely fast since the driver reports back immediately\n+ * that the flush/pageflip is done. This wastes CPU and power.\n+ * Such users might want to set this module parameter to false.\n+ */\n+static bool gud_async_flush = true;\n+module_param_named(async_flush, gud_async_flush, bool, 0644);\n+MODULE_PARM_DESC(async_flush, \"Enable asynchronous flushing [default=true]\");\n+\n+/*\n  * FIXME: The driver is probably broken on Big Endian machines.\n  * See discussion:\n  * https://lore.kernel.org/dri-devel/CAKb7UvihLX0hgBOP3VBG7O+atwZcUVCPVuBdfmDMpg0NjXe-cQ@mail.gmail.com/\n@@ -577,6 +590,8 @@ void gud_pipe_update(struct drm_simple_d\n \t\tif (gdrm->flags & GUD_DISPLAY_FLAG_FULL_UPDATE)\n \t\t\tdrm_rect_init(&damage, 0, 0, fb->width, fb->height);\n \t\tgud_fb_queue_damage(gdrm, fb, &damage);\n+\t\tif (!gud_async_flush)\n+\t\t\tflush_work(&gdrm->work);\n \t}\n \n \tif (!crtc->state->enable)\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0717-drm-vc4-hdmi-Make-sure-the-controller-is-powered-up-.patch",
    "content": "From 94bc403a9a7af3bd042ecdc160e6ab0b08331df8 Mon Sep 17 00:00:00 2001\nFrom: Maxime Ripard <maxime@cerno.tech>\nDate: Fri, 2 Jul 2021 12:03:28 +0200\nSubject: [PATCH] drm/vc4: hdmi: Make sure the controller is powered up during\n bind\n\nIn the bind hook, we actually need the device to have the HSM clock\nrunning during the final part of the display initialisation where we\nreset the controller and initialise the CEC component.\n\nFailing to do so will result in a complete, silent, hang of the CPU.\n\nFixes: 411efa18e4b0 (\"drm/vc4: hdmi: Move the HSM clock enable to runtime_pm\")\nSigned-off-by: Maxime Ripard <maxime@cerno.tech>\n---\n drivers/gpu/drm/vc4/vc4_hdmi.c | 17 +++++++++++++++--\n 1 file changed, 15 insertions(+), 2 deletions(-)\n\n--- a/drivers/gpu/drm/vc4/vc4_hdmi.c\n+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c\n@@ -2295,6 +2295,18 @@ static int vc4_hdmi_bind(struct device *\n \tif (ret)\n \t\tgoto err_put_ddc;\n \n+\t/*\n+\t * We need to have the device powered up at this point to call\n+\t * our reset hook and for the CEC init.\n+\t */\n+\tret = vc4_hdmi_runtime_resume(dev);\n+\tif (ret)\n+\t\tgoto err_put_ddc;\n+\n+\tpm_runtime_get_noresume(dev);\n+\tpm_runtime_set_active(dev);\n+\tpm_runtime_enable(dev);\n+\n \tif (vc4_hdmi->variant->reset)\n \t\tvc4_hdmi->variant->reset(vc4_hdmi);\n \n@@ -2306,8 +2318,6 @@ static int vc4_hdmi_bind(struct device *\n \t\tclk_prepare_enable(vc4_hdmi->pixel_bvb_clock);\n \t}\n \n-\tpm_runtime_enable(dev);\n-\n \tdrm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS);\n \tdrm_encoder_helper_add(encoder, &vc4_hdmi_encoder_helper_funcs);\n \n@@ -2331,6 +2341,8 @@ static int vc4_hdmi_bind(struct device *\n \t\t\t     vc4_hdmi_debugfs_regs,\n \t\t\t     vc4_hdmi);\n \n+\tpm_runtime_put_sync(dev);\n+\n \treturn 0;\n \n err_free_cec:\n@@ -2341,6 +2353,7 @@ err_destroy_conn:\n \tvc4_hdmi_connector_destroy(&vc4_hdmi->connector);\n err_destroy_encoder:\n \tdrm_encoder_cleanup(encoder);\n+\tpm_runtime_put_sync(dev);\n \tpm_runtime_disable(dev);\n err_put_ddc:\n \tput_device(&vc4_hdmi->ddc->dev);\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0718-overlays-Set-CMA-to-512MB-on-Pi-4-for-vc4.patch",
    "content": "From aa4e10d677dfe14c7e3132595558bcbf2fc25aca Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.com>\nDate: Mon, 26 Jul 2021 11:05:18 +0100\nSubject: [PATCH] overlays: Set CMA to 512MB on Pi 4 for vc4\n\nPi 4s have at least 1GB, and there are advantages to having more CMA\navailable (HEVC works out of the box, support for more complex video\nsetups, etc.) without significant disadvantages.\n\nCan be overridden by appending a parameter to the dtoverlay line, e.g.\ndtoverlay=vc4-fkms-v3d,cma-256\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.com>\n---\n arch/arm/boot/dts/overlays/Makefile           |  1 +\n arch/arm/boot/dts/overlays/README             | 17 +++++++\n arch/arm/boot/dts/overlays/overlay_map.dts    |  9 ++++\n .../dts/overlays/upstream-pi4-overlay.dts     |  2 +-\n .../dts/overlays/vc4-fkms-v3d-pi4-overlay.dts | 44 +++++++++++++++++++\n .../dts/overlays/vc4-kms-v3d-pi4-overlay.dts  |  6 ++-\n 6 files changed, 77 insertions(+), 2 deletions(-)\n create mode 100644 arch/arm/boot/dts/overlays/vc4-fkms-v3d-pi4-overlay.dts\n\n--- a/arch/arm/boot/dts/overlays/Makefile\n+++ b/arch/arm/boot/dts/overlays/Makefile\n@@ -220,6 +220,7 @@ dtbo-$(CONFIG_ARCH_BCM2835) += \\\n \tupstream.dtbo \\\n \tupstream-pi4.dtbo \\\n \tvc4-fkms-v3d.dtbo \\\n+\tvc4-fkms-v3d-pi4.dtbo \\\n \tvc4-kms-dpi-at056tn53v1.dtbo \\\n \tvc4-kms-dsi-7inch.dtbo \\\n \tvc4-kms-dsi-lt070me05000.dtbo \\\n--- a/arch/arm/boot/dts/overlays/README\n+++ b/arch/arm/boot/dts/overlays/README\n@@ -3268,6 +3268,23 @@ Params: cma-512                 CMA is 5\n         cma-default             Use upstream's default value\n \n \n+Name:   vc4-fkms-v3d-pi4\n+Info:   Enable Eric Anholt's DRM VC4 V3D driver on top of the dispmanx\n+        display stack.\n+Load:   dtoverlay=vc4-fkms-v3d-pi4,<param>\n+Params: cma-512                 CMA is 512MB (needs 1GB)\n+        cma-448                 CMA is 448MB (needs 1GB)\n+        cma-384                 CMA is 384MB (needs 1GB)\n+        cma-320                 CMA is 320MB (needs 1GB)\n+        cma-256                 CMA is 256MB (needs 1GB)\n+        cma-192                 CMA is 192MB (needs 1GB)\n+        cma-128                 CMA is 128MB\n+        cma-96                  CMA is 96MB\n+        cma-64                  CMA is 64MB\n+        cma-size                CMA size in bytes, 4MB aligned\n+        cma-default             Use upstream's default value\n+\n+\n Name:   vc4-kms-dpi-at056tn53v1\n Info:   Enable an Innolux 5.6in VGA TFT connected to DPI interface under KMS.\n         Requires vc4-kms-v3d to be loaded.\n--- a/arch/arm/boot/dts/overlays/overlay_map.dts\n+++ b/arch/arm/boot/dts/overlays/overlay_map.dts\n@@ -138,6 +138,15 @@\n \t\tbcm2711;\n \t};\n \n+\tvc4-fkms-v3d {\n+\t\tbcm2835;\n+\t\tbcm2711 = \"vc4-fkms-v3d-pi4\";\n+\t};\n+\n+\tvc4-fkms-v3d-pi4 {\n+\t\tbcm2711;\n+\t};\n+\n \tvc4-kms-v3d {\n \t\tbcm2835;\n \t\tbcm2711 = \"vc4-kms-v3d-pi4\";\n--- a/arch/arm/boot/dts/overlays/upstream-pi4-overlay.dts\n+++ b/arch/arm/boot/dts/overlays/upstream-pi4-overlay.dts\n@@ -6,7 +6,7 @@\n #include <dt-bindings/clock/bcm2835.h>\n \n / {\n-\tcompatible = \"brcm,bcm2835\";\n+\tcompatible = \"brcm,bcm2711\";\n \tfragment@0 {\n \t\ttarget = <&ddc0>;\n \t\t__overlay__ {\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/vc4-fkms-v3d-pi4-overlay.dts\n@@ -0,0 +1,44 @@\n+/*\n+ * vc4-fkms-v3d-overlay.dts\n+ */\n+\n+/dts-v1/;\n+/plugin/;\n+\n+#include \"cma-overlay.dts\"\n+\n+&frag0 {\n+       size = <(512*1024*1024)>;\n+};\n+\n+/ {\n+\tcompatible = \"brcm,bcm2711\";\n+\n+\tfragment@1 {\n+\t\ttarget = <&fb>;\n+\t\t__overlay__  {\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&firmwarekms>;\n+\t\t__overlay__  {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@3 {\n+\t\ttarget = <&v3d>;\n+\t\t__overlay__  {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@4 {\n+\t\ttarget = <&vc4>;\n+\t\t__overlay__  {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+};\n--- a/arch/arm/boot/dts/overlays/vc4-kms-v3d-pi4-overlay.dts\n+++ b/arch/arm/boot/dts/overlays/vc4-kms-v3d-pi4-overlay.dts\n@@ -9,8 +9,12 @@\n \n #include \"cma-overlay.dts\"\n \n+&frag0 {\n+       size = <(512*1024*1024)>;\n+};\n+\n / {\n-\tcompatible = \"brcm,bcm2835\";\n+\tcompatible = \"brcm,bcm2711\";\n \n \tfragment@1 {\n \t\ttarget = <&ddc0>;\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0719-ARM-dts-Correct-CM4-PHY-MDIO-address.patch",
    "content": "From d0edf1b5178fc3a3ef093755c209cad43e6d8426 Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.com>\nDate: Mon, 26 Jul 2021 13:24:09 +0100\nSubject: [PATCH] ARM: dts: Correct CM4 PHY MDIO address\n\nThe firmware patches the PHY MDIO address in the DTB to cope with\nvariations between board revisions, but the default for the CM4 PHY\nis currently 1 when it should be 0.\n\nReported-by: Stefan Wahren <stefan.wahren@i2se.com>\nSigned-off-by: Phil Elwell <phil@raspberrypi.com>\n---\n arch/arm/boot/dts/bcm2711-rpi-cm4.dts | 4 ++--\n 1 file changed, 2 insertions(+), 2 deletions(-)\n\n--- a/arch/arm/boot/dts/bcm2711-rpi-cm4.dts\n+++ b/arch/arm/boot/dts/bcm2711-rpi-cm4.dts\n@@ -277,9 +277,9 @@\n };\n \n &genet_mdio {\n-\tphy1: ethernet-phy@1 {\n+\tphy1: ethernet-phy@0 {\n \t\t/* No PHY interrupt */\n-\t\treg = <0x1>;\n+\t\treg = <0x0>;\n \t};\n };\n \n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0720-drm-vc4-Increase-the-core-clock-based-on-HVS-load.patch",
    "content": "From cf8b55ab71c780cefff2c152949303e82559701c Mon Sep 17 00:00:00 2001\nFrom: Dom Cobley <popcornmix@gmail.com>\nDate: Mon, 26 Jul 2021 18:03:53 +0100\nSubject: [PATCH] drm/vc4: Increase the core clock based on HVS load\n\nDepending on a given HVS output (HVS to PixelValves) and input (planes\nattached to a channel) load, the HVS needs for the core clock to be\nraised above its boot time default.\n\nFailing to do so will result in a vblank timeout and a stalled display\npipeline.\n\nSigned-off-by: Maxime Ripard <maxime@cerno.tech>\n---\n drivers/gpu/drm/vc4/vc4_crtc.c |  15 +++++\n drivers/gpu/drm/vc4/vc4_drv.h  |   3 +\n drivers/gpu/drm/vc4/vc4_kms.c  | 116 ++++++++++++++++++++++++++++++++-\n 3 files changed, 131 insertions(+), 3 deletions(-)\n\n--- a/drivers/gpu/drm/vc4/vc4_crtc.c\n+++ b/drivers/gpu/drm/vc4/vc4_crtc.c\n@@ -660,12 +660,27 @@ static int vc4_crtc_atomic_check(struct\n \tstruct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc_state);\n \tstruct drm_connector *conn;\n \tstruct drm_connector_state *conn_state;\n+\tstruct drm_encoder *encoder;\n \tint ret, i;\n \n \tret = vc4_hvs_atomic_check(crtc, state);\n \tif (ret)\n \t\treturn ret;\n \n+\tencoder = vc4_get_crtc_encoder(crtc, crtc_state);\n+\tif (encoder) {\n+\t\tconst struct drm_display_mode *mode = &crtc_state->adjusted_mode;\n+\t\tstruct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder);\n+\n+\t\tmode = &crtc_state->adjusted_mode;\n+\t\tif (vc4_encoder->type == VC4_ENCODER_TYPE_HDMI0) {\n+\t\t\tvc4_state->hvs_load = max(mode->clock * mode->hdisplay / mode->htotal + 1000,\n+\t\t\t\t\t\t  mode->clock * 9 / 10) * 1000;\n+\t\t} else {\n+\t\t\tvc4_state->hvs_load = mode->clock * 1000;\n+\t\t}\n+\t}\n+\n \tfor_each_new_connector_in_state(state, conn, conn_state,\n \t\t\t\t\ti) {\n \t\tif (conn_state->crtc != crtc)\n--- a/drivers/gpu/drm/vc4/vc4_drv.h\n+++ b/drivers/gpu/drm/vc4/vc4_drv.h\n@@ -326,6 +326,7 @@ struct vc4_hvs {\n \tu32 __iomem *dlist;\n \n \tstruct clk *core_clk;\n+\tstruct clk_request *core_req;\n \n \t/* Memory manager for CRTCs to allocate space in the display\n \t * list.  Units are dwords.\n@@ -537,6 +538,8 @@ struct vc4_crtc_state {\n \t\tunsigned int bottom;\n \t} margins;\n \n+\tunsigned long hvs_load;\n+\n \t/* Transitional state below, only valid during atomic commits */\n \tbool update_muxing;\n };\n--- a/drivers/gpu/drm/vc4/vc4_kms.c\n+++ b/drivers/gpu/drm/vc4/vc4_kms.c\n@@ -40,6 +40,9 @@ static struct vc4_ctm_state *to_vc4_ctm_\n struct vc4_hvs_state {\n \tstruct drm_private_state base;\n \tunsigned int unassigned_channels;\n+\tunsigned int num_outputs;\n+\tunsigned long fifo_load;\n+\tunsigned long core_clock_rate;\n };\n \n static struct vc4_hvs_state *\n@@ -186,6 +189,19 @@ vc4_ctm_commit(struct vc4_dev *vc4, stru\n }\n \n static struct vc4_hvs_state *\n+vc4_hvs_get_new_global_state(struct drm_atomic_state *state)\n+{\n+\tstruct vc4_dev *vc4 = to_vc4_dev(state->dev);\n+\tstruct drm_private_state *priv_state;\n+\n+\tpriv_state = drm_atomic_get_new_private_obj_state(state, &vc4->hvs_channels);\n+\tif (IS_ERR(priv_state))\n+\t\treturn ERR_CAST(priv_state);\n+\n+\treturn to_vc4_hvs_state(priv_state);\n+}\n+\n+static struct vc4_hvs_state *\n vc4_hvs_get_global_state(struct drm_atomic_state *state)\n {\n \tstruct vc4_dev *vc4 = to_vc4_dev(state->dev);\n@@ -312,10 +328,15 @@ vc4_atomic_complete_commit(struct drm_at\n \tstruct vc4_dev *vc4 = to_vc4_dev(dev);\n \tstruct vc4_hvs *hvs = vc4->hvs;\n \tstruct drm_crtc_state *new_crtc_state;\n+\tstruct vc4_hvs_state *hvs_state;\n \tstruct drm_crtc *crtc;\n \tstruct clk_request *core_req;\n \tint i;\n \n+\thvs_state = vc4_hvs_get_new_global_state(state);\n+\tif (WARN_ON(!hvs_state))\n+\t\treturn;\n+\n \tfor_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {\n \t\tstruct vc4_crtc_state *vc4_crtc_state;\n \n@@ -326,9 +347,20 @@ vc4_atomic_complete_commit(struct drm_at\n \t\tvc4_hvs_mask_underrun(dev, vc4_crtc_state->assigned_channel);\n \t}\n \n-\tif (vc4->hvs && vc4->hvs->hvs5)\n+\tif (vc4->hvs && vc4->hvs->hvs5) {\n+\t\t/*\n+\t\t * Do a temporary request on the core clock during the\n+\t\t * modeset.\n+\t\t */\n \t\tcore_req = clk_request_start(hvs->core_clk, 500000000);\n \n+\t\t/*\n+\t\t * And remove the previous one based on the HVS\n+\t\t * requirements if any.\n+\t\t */\n+\t\tclk_request_done(hvs->core_req);\n+\t}\n+\n \tdrm_atomic_helper_wait_for_fences(dev, state, false);\n \n \tdrm_atomic_helper_wait_for_dependencies(state);\n@@ -358,8 +390,20 @@ vc4_atomic_complete_commit(struct drm_at\n \n \tdrm_atomic_helper_commit_cleanup_done(state);\n \n-\tif (vc4->hvs && vc4->hvs->hvs5)\n+\tif (vc4->hvs && vc4->hvs->hvs5) {\n+\t\tdrm_dbg(dev, \"Running the core clock at %lu Hz\\n\",\n+\t\t\thvs_state->core_clock_rate);\n+\n+\t\t/*\n+\t\t * Request a clock rate based on the current HVS\n+\t\t * requirements.\n+\t\t */\n+\t\thvs->core_req = clk_request_start(hvs->core_clk,\n+\t\t\t\t\t\t  hvs_state->core_clock_rate);\n+\n+\t\t/* And drop the temporary request */\n \t\tclk_request_done(core_req);\n+\t}\n \n \tdrm_atomic_state_put(state);\n \n@@ -703,6 +747,9 @@ vc4_hvs_channels_duplicate_state(struct\n \t__drm_atomic_helper_private_obj_duplicate_state(obj, &state->base);\n \n \tstate->unassigned_channels = old_state->unassigned_channels;\n+\tstate->fifo_load = old_state->fifo_load;\n+\tstate->num_outputs = old_state->num_outputs;\n+\tstate->core_clock_rate = old_state->core_clock_rate;\n \n \treturn &state->base;\n }\n@@ -849,6 +896,65 @@ static int vc4_pv_muxing_atomic_check(st\n }\n \n static int\n+vc4_core_clock_atomic_check(struct drm_atomic_state *state)\n+{\n+\tstruct vc4_dev *vc4 = to_vc4_dev(state->dev);\n+\tstruct drm_private_state *priv_state;\n+\tstruct vc4_hvs_state *hvs_new_state;\n+\tstruct vc4_load_tracker_state *load_state;\n+\tstruct drm_crtc_state *old_crtc_state, *new_crtc_state;\n+\tstruct drm_crtc *crtc;\n+\tunsigned long pixel_rate;\n+\tunsigned long cob_rate;\n+\tunsigned int i;\n+\n+\tpriv_state = drm_atomic_get_private_obj_state(state,\n+\t\t\t\t\t\t      &vc4->load_tracker);\n+\tif (IS_ERR(priv_state))\n+\t\treturn PTR_ERR(priv_state);\n+\n+\tload_state = to_vc4_load_tracker_state(priv_state);\n+\n+\thvs_new_state = vc4_hvs_get_global_state(state);\n+\tif (!hvs_new_state)\n+\t\treturn -EINVAL;\n+\n+\tfor_each_oldnew_crtc_in_state(state, crtc,\n+\t\t\t\t      old_crtc_state,\n+\t\t\t\t      new_crtc_state,\n+\t\t\t\t      i) {\n+\t\tif (old_crtc_state->active) {\n+\t\t\tstruct vc4_crtc_state *old_vc4_state =\n+\t\t\t\tto_vc4_crtc_state(old_crtc_state);\n+\n+\t\t\thvs_new_state->num_outputs -= 1;\n+\t\t\thvs_new_state->fifo_load -= old_vc4_state->hvs_load;\n+\t\t}\n+\n+\t\tif (new_crtc_state->active) {\n+\t\t\tstruct vc4_crtc_state *new_vc4_state =\n+\t\t\t\tto_vc4_crtc_state(new_crtc_state);\n+\n+\t\t\thvs_new_state->num_outputs += 1;\n+\t\t\thvs_new_state->fifo_load += new_vc4_state->hvs_load;\n+\t\t}\n+\t}\n+\n+\tcob_rate = hvs_new_state->fifo_load;\n+\tpixel_rate = load_state->hvs_load;\n+\tif (hvs_new_state->num_outputs > 1) {\n+\t\tpixel_rate = (pixel_rate * 40) / 100;\n+\t} else {\n+\t\tpixel_rate = (pixel_rate * 60) / 100;\n+\t}\n+\n+\thvs_new_state->core_clock_rate = max(cob_rate, pixel_rate);\n+\n+\treturn 0;\n+}\n+\n+\n+static int\n vc4_atomic_check(struct drm_device *dev, struct drm_atomic_state *state)\n {\n \tint ret;\n@@ -865,7 +971,11 @@ vc4_atomic_check(struct drm_device *dev,\n \tif (ret)\n \t\treturn ret;\n \n-\treturn vc4_load_tracker_atomic_check(state);\n+\tret = vc4_load_tracker_atomic_check(state);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\treturn vc4_core_clock_atomic_check(state);\n }\n \n static const struct drm_mode_config_funcs vc4_mode_funcs = {\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0721-drm-vc4-Increase-the-core-clock-to-a-minimum-of-500M.patch",
    "content": "From f79e871c8d9fbe90b351f61b052878d98b999b1b Mon Sep 17 00:00:00 2001\nFrom: Dom Cobley <popcornmix@gmail.com>\nDate: Mon, 26 Jul 2021 18:07:25 +0100\nSubject: [PATCH] drm/vc4: Increase the core clock to a minimum of 500MHz\n\nThe core clock needs to be raised temporarily during a modeset to\n500MHz. However, the HVS core clock requirement might be higher than\n500MHz. This rate will be enforced at the end of the mode setting,\nmeaning that might might end up with a core clock rate lower than\nplanned on the first mode set.\n\nUse the maximum value of 500MHz and the HVS core clock rate for our\ntemporary boost to fix this issue.\n\nSigned-off-by: Maxime Ripard <maxime@cerno.tech>\n---\n drivers/gpu/drm/vc4/vc4_kms.c | 8 +++++++-\n 1 file changed, 7 insertions(+), 1 deletion(-)\n\n--- a/drivers/gpu/drm/vc4/vc4_kms.c\n+++ b/drivers/gpu/drm/vc4/vc4_kms.c\n@@ -348,11 +348,17 @@ vc4_atomic_complete_commit(struct drm_at\n \t}\n \n \tif (vc4->hvs && vc4->hvs->hvs5) {\n+\t\tunsigned long core_rate = max_t(unsigned long,\n+\t\t\t\t\t\t500000000,\n+\t\t\t\t\t\thvs_state->core_clock_rate);\n+\n+\t\tdrm_dbg(dev, \"Raising the core clock at %lu Hz\\n\", core_rate);\n+\n \t\t/*\n \t\t * Do a temporary request on the core clock during the\n \t\t * modeset.\n \t\t */\n-\t\tcore_req = clk_request_start(hvs->core_clk, 500000000);\n+\t\tcore_req = clk_request_start(hvs->core_clk, core_rate);\n \n \t\t/*\n \t\t * And remove the previous one based on the HVS\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0722-overlays-Update-and-rename-chipdip-i2s-master-dac.patch",
    "content": "From e83ebb02f24f527df4916309cdb0b8a3f7d07a79 Mon Sep 17 00:00:00 2001\nFrom: \"chipdip.lab\" <43340836+chipdipru@users.noreply.github.com>\nDate: Mon, 26 Jul 2021 14:43:11 +0300\nSubject: [PATCH] overlays: Update and rename chipdip-i2s-master-dac\n\nSimple card fragment removed, GPIO fragment added.\n\nSigned-off-by: Evgenij Sapunov <evgenij.sapunov@chipdip.ru>\n---\n arch/arm/boot/dts/overlays/Makefile           |  2 +-\n arch/arm/boot/dts/overlays/README             |  6 +--\n .../boot/dts/overlays/chipdip-dac-overlay.dts | 46 ++++++++++++++++\n .../chipdip-i2s-master-dac-overlay.dts        | 53 -------------------\n 4 files changed, 50 insertions(+), 57 deletions(-)\n create mode 100644 arch/arm/boot/dts/overlays/chipdip-dac-overlay.dts\n delete mode 100644 arch/arm/boot/dts/overlays/chipdip-i2s-master-dac-overlay.dts\n\n--- a/arch/arm/boot/dts/overlays/Makefile\n+++ b/arch/arm/boot/dts/overlays/Makefile\n@@ -31,7 +31,7 @@ dtbo-$(CONFIG_ARCH_BCM2835) += \\\n \taudremap.dtbo \\\n \tbalena-fin.dtbo \\\n \tcap1106.dtbo \\\n-\tchipdip-i2s-master-dac.dtbo \\\n+\tchipdip-dac.dtbo \\\n \tcma.dtbo \\\n \tdht11.dtbo \\\n \tdionaudio-loco.dtbo \\\n--- a/arch/arm/boot/dts/overlays/README\n+++ b/arch/arm/boot/dts/overlays/README\n@@ -628,9 +628,9 @@ Load:   dtoverlay=cap1106,<param>=<val>\n Params: int_pin                 GPIO pin for interrupt signal (default 23)\n \n \n-Name:   chipdip-i2s-master-dac\n-Info:   Configures Raspberry PI to work as I2S slave with BCLK=64Fs.\n-Load:   dtoverlay=chipdip-i2s-master-dac\n+Name:   chipdip-dac\n+Info:   Configures Chip Dip audio cards.\n+Load:   dtoverlay=chipdip-dac\n Params: <None>\n \n \n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/chipdip-dac-overlay.dts\n@@ -0,0 +1,46 @@\n+/*\n+ * Device Tree overlay for ChipDip DAC\n+ */\n+\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"brcm,bcm2835\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&i2s>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget-path = \"/\";\n+\t\t__overlay__ {\n+\t\t\tspdif-transmitter {\n+\t\t\t\t#address-cells = <0>;\n+\t\t\t\t#size-cells = <0>;\n+\t\t\t\t#sound-dai-cells = <0>;\n+\t\t\t\tcompatible = \"linux,spdif-dit\";\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&sound>;\n+\t\t__overlay__ {\n+\t\t\tcompatible = \"chipdip,chipdip-dac\";\n+\t\t\ti2s-controller = <&i2s>;\n+\t\t\tsr0-gpios = <&gpio 5 0>;\n+\t\t\tsr1-gpios = <&gpio 6 0>;\n+\t\t\tsr2-gpios = <&gpio 12 0>;\n+\t\t\tres0-gpios = <&gpio 24 0>;\n+\t\t\tres1-gpios = <&gpio 27 0>;\n+\t\t\tmute-gpios = <&gpio 4 0>;\n+\t\t\tsdwn-gpios = <&gpio 13 0>;\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+};\n--- a/arch/arm/boot/dts/overlays/chipdip-i2s-master-dac-overlay.dts\n+++ /dev/null\n@@ -1,53 +0,0 @@\n-/*\n- * Device Tree overlay for ChipDip I2S master DAC\n- */\n-\n-/dts-v1/;\n-/plugin/;\n-\n-/ {\n-    compatible = \"brcm,bcm2835\";\n-    fragment@0 {\n-        target = <&sound>;\n-        __overlay__ {\n-            compatible = \"simple-audio-card\";\n-            simple-audio-card,name = \"ChipDip I2S master DAC\";\n-            status=\"okay\";\n-            playback_link: simple-audio-card,dai-link@0 {\n-                format = \"i2s\";\n-\t\tbitclock-master = <&p_codec_dai>;\n-                frame-master = <&p_codec_dai>;\n-                p_cpu_dai: cpu {\n-                        sound-dai = <&i2s>;\n-\t\t\tdai-tdm-slot-num = <2>;\n-\t\t\tdai-tdm-slot-width = <32>;\n-\t\t\t\t};\n-\n-                p_codec_dai: codec {\n-                        sound-dai = <&codec_out>;\n-                };\n-            };\n-        };\n-    }; \n-\n-    fragment@1 {\n-        target-path = \"/\";\n-        __overlay__ {\n-            codec_out: spdif-transmitter {\n-                #address-cells = <0>;\n-                #size-cells = <0>;\n-                #sound-dai-cells = <0>;\n-                compatible = \"linux,spdif-dit\";\n-                status = \"okay\";\n-            };\n-        };\n-    };\n- \n-    fragment@2 {\n-        target = <&i2s>;\n-        __overlay__ {\n-            #sound-dai-cells = <0>;\n-            status = \"okay\";\n-        };\n-    };\n-}; \n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0723-ASoC-bcm-Add-chipdip-dac-driver.patch",
    "content": "From e17c3e2ccb04657ca00984477854a6a700fef01d Mon Sep 17 00:00:00 2001\nFrom: \"chipdip.lab\" <43340836+chipdipru@users.noreply.github.com>\nDate: Mon, 26 Jul 2021 14:45:59 +0300\nSubject: [PATCH] ASoC: bcm: Add chipdip-dac driver\n\nDriver chipdip-dac.c added into sound/soc/bcm/, files\nsound/soc/bcm/Kconfig and sound/soc/bcm/Makefile updated.\n\nSigned-off-by: Evgenij Sapunov <evgenij.sapunov@chipdip.ru>\n---\n sound/soc/bcm/Kconfig       |   6 +\n sound/soc/bcm/Makefile      |   3 +-\n sound/soc/bcm/chipdip-dac.c | 275 ++++++++++++++++++++++++++++++++++++\n 3 files changed, 283 insertions(+), 1 deletion(-)\n create mode 100644 sound/soc/bcm/chipdip-dac.c\n\n--- a/sound/soc/bcm/Kconfig\n+++ b/sound/soc/bcm/Kconfig\n@@ -27,6 +27,12 @@ config SND_BCM63XX_I2S_WHISTLER\n \n \t  If you don't know what to do here, say N\n \n+config SND_BCM2708_SOC_CHIPDIP_DAC\n+         tristate \"Support for the ChipDip DAC\"\n+         depends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S\n+         help\n+          Say Y or M if you want to add support for the ChipDip DAC soundcard\n+\n config SND_BCM2708_SOC_GOOGLEVOICEHAT_SOUNDCARD\n \ttristate \"Support for Google voiceHAT soundcard\"\n \tdepends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S\n--- a/sound/soc/bcm/Makefile\n+++ b/sound/soc/bcm/Makefile\n@@ -47,6 +47,7 @@ snd-soc-fe-pi-audio-objs := fe-pi-audio.\n snd-soc-rpi-simple-soundcard-objs := rpi-simple-soundcard.o\n snd-soc-rpi-wm8804-soundcard-objs := rpi-wm8804-soundcard.o\n snd-soc-pifi-40-objs := pifi-40.o\n+snd-soc-chipdip-dac-objs := chipdip-dac.o\n \n obj-$(CONFIG_SND_BCM2708_SOC_GOOGLEVOICEHAT_SOUNDCARD)  += snd-soc-googlevoicehat-codec.o\n obj-$(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS) += snd-soc-hifiberry-dacplus.o\n@@ -78,4 +79,4 @@ obj-$(CONFIG_SND_BCM2708_SOC_FE_PI_AUDIO\n obj-$(CONFIG_SND_RPI_SIMPLE_SOUNDCARD) += snd-soc-rpi-simple-soundcard.o\n obj-$(CONFIG_SND_RPI_WM8804_SOUNDCARD) += snd-soc-rpi-wm8804-soundcard.o\n obj-$(CONFIG_SND_BCM2708_SOC_PIFI_40) += snd-soc-pifi-40.o\n-\n+obj-$(CONFIG_SND_BCM2708_SOC_CHIPDIP_DAC) += snd-soc-chipdip-dac.o\n--- /dev/null\n+++ b/sound/soc/bcm/chipdip-dac.c\n@@ -0,0 +1,275 @@\n+/*\n+ * ASoC Driver for ChipDip DAC\n+ *\n+ * Author:\tEvgenij Sapunov\n+ *\t\tCopyright 2021\n+ *\t\tbased on code by Milan Neskovic <info@justboom.co>\n+ *\t\tbased on code by Jaikumar <jaikumar@cem-solutions.net>\n+ *\n+ * Thanks to Phil Elwell (pelwell) for help.\n+ *\n+ * This program is free software; you can redistribute it and/or\n+ * modify it under the terms of the GNU General Public License\n+ * version 2 as published by the Free Software Foundation.\n+ *\n+ * This program is distributed in the hope that it will be useful, but\n+ * WITHOUT ANY WARRANTY; without even the implied warranty of\n+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\n+ * General Public License for more details.\n+ */\n+\n+#include <linux/module.h>\n+#include <linux/gpio/consumer.h>\n+#include <linux/platform_device.h>\n+#include <linux/delay.h>\n+\n+#include <sound/core.h>\n+#include <sound/pcm.h>\n+#include <sound/pcm_params.h>\n+#include <sound/soc.h>\n+#include <sound/jack.h>\n+\n+#define SR_BIT_0                  0 //sample rate bits\n+#define SR_BIT_1                  1\n+#define SR_BIT_2                  2\n+#define BD_BIT_0                  3 //bit depth bits\n+#define BD_BIT_1                  4\n+\n+#define SAMPLE_RATE_MASK_44_1     0\n+#define SAMPLE_RATE_MASK_48       (1 << SR_BIT_0)\n+#define SAMPLE_RATE_MASK_88_2     ((1 << SR_BIT_2) | (1 << SR_BIT_1))\n+#define SAMPLE_RATE_MASK_96       (1 << SR_BIT_1)\n+#define SAMPLE_RATE_MASK_176_4    ((1 << SR_BIT_2) | (1 << SR_BIT_1) | (1 << SR_BIT_0))\n+#define SAMPLE_RATE_MASK_192      ((1 << SR_BIT_1) | (1 << SR_BIT_0))\n+#define SAMPLE_RATE_MASK          ((1 << SR_BIT_2) | (1 << SR_BIT_1) | (1 << SR_BIT_0))\n+\n+#define BIT_DEPTH_MASK_16         0\n+#define BIT_DEPTH_MASK_24         (1 << BD_BIT_0)\n+#define BIT_DEPTH_MASK_32         (1 << BD_BIT_1)\n+#define BIT_DEPTH_MASK            ((1 << BD_BIT_1) | (1 << BD_BIT_0))\n+\n+#define MUTE_ACTIVE               0\n+#define MUTE_NOT_ACTIVE           1\n+\n+#define HW_PARAMS_GPIO_COUNT      5\n+\n+static struct gpio_desc *mute_gpio;\n+static struct gpio_desc *sdwn_gpio;\n+static struct gpio_desc *hw_params_gpios[HW_PARAMS_GPIO_COUNT];\n+static int current_width;\n+static int current_rate;\n+\n+static void snd_rpi_chipdip_dac_gpio_array_set(int value);\n+static void snd_rpi_chipdip_dac_gpio_set(struct gpio_desc *gpio_item, int value);\n+\n+static void snd_rpi_chipdip_dac_gpio_array_set(int value)\n+{\n+\tint i = 0;\n+\n+\tfor (i = 0; i < HW_PARAMS_GPIO_COUNT; i++)\n+\t\tsnd_rpi_chipdip_dac_gpio_set(hw_params_gpios[i], ((value >> i) & 1));\n+}\n+\n+static void snd_rpi_chipdip_dac_gpio_set(struct gpio_desc *gpio_item, int value)\n+{\n+\tif (gpio_item)\n+\t\tgpiod_set_value_cansleep(gpio_item, value);\n+}\n+\n+static int snd_rpi_chipdip_dac_init(struct snd_soc_pcm_runtime *rtd)\n+{\n+\treturn 0;\n+}\n+\n+static int snd_rpi_chipdip_dac_hw_params(struct snd_pcm_substream *substream,\n+\t\t\t\t\t struct snd_pcm_hw_params *params)\n+{\n+\tint ret = 0;\n+\tint gpio_change_pending = 0;\n+\tint sample_rate_state = 0;\n+\tint bit_depth_state = 0;\n+\tint param_value = params_width(params);\n+\tstruct snd_soc_pcm_runtime *rtd = substream->private_data;\n+\n+\tret = snd_soc_dai_set_bclk_ratio(asoc_rtd_to_cpu(rtd, 0), 2 * 32);\n+\n+\tif (current_width != param_value) {\n+\t\tcurrent_width = param_value;\n+\t\tgpio_change_pending = 1;\n+\n+\t\tswitch (param_value) {\n+\t\tcase 16:\n+\t\t\tbit_depth_state = BIT_DEPTH_MASK_16;\n+\t\t\tbreak;\n+\t\tcase 24:\n+\t\t\tbit_depth_state = BIT_DEPTH_MASK_24;\n+\t\t\tbreak;\n+\t\tcase 32:\n+\t\t\tbit_depth_state = BIT_DEPTH_MASK_32;\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t}\n+\n+\tparam_value = params_rate(params);\n+\tif (current_rate != param_value) {\n+\t\tcurrent_rate = param_value;\n+\t\tgpio_change_pending = 1;\n+\n+\t\tswitch (param_value) {\n+\t\tcase 44100:\n+\t\t\tsample_rate_state = SAMPLE_RATE_MASK_44_1;\n+\t\t\tbreak;\n+\t\tcase 48000:\n+\t\t\tsample_rate_state = SAMPLE_RATE_MASK_48;\n+\t\t\tbreak;\n+\t\tcase 88200:\n+\t\t\tsample_rate_state = SAMPLE_RATE_MASK_88_2;\n+\t\t\tbreak;\n+\t\tcase 96000:\n+\t\t\tsample_rate_state = SAMPLE_RATE_MASK_96;\n+\t\t\tbreak;\n+\t\tcase 176400:\n+\t\t\tsample_rate_state = SAMPLE_RATE_MASK_176_4;\n+\t\t\tbreak;\n+\t\tcase 192000:\n+\t\t\tsample_rate_state = SAMPLE_RATE_MASK_192;\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t}\n+\n+\tif (gpio_change_pending) {\n+\t\tsnd_rpi_chipdip_dac_gpio_set(mute_gpio, MUTE_ACTIVE);\n+\t\tsnd_rpi_chipdip_dac_gpio_array_set(bit_depth_state | sample_rate_state);\n+\t\tmsleep(300);\n+\t\tsnd_rpi_chipdip_dac_gpio_set(mute_gpio, MUTE_NOT_ACTIVE);\n+\t}\n+\n+\treturn ret;\n+}\n+\n+static int snd_rpi_chipdip_dac_startup(struct snd_pcm_substream *substream)\n+{\n+\treturn 0;\n+}\n+\n+static void snd_rpi_chipdip_dac_shutdown(struct snd_pcm_substream *substream)\n+{\n+\n+}\n+\n+/* machine stream operations */\n+static struct snd_soc_ops snd_rpi_chipdip_dac_ops = {\n+\t.hw_params = snd_rpi_chipdip_dac_hw_params,\n+\t.startup = snd_rpi_chipdip_dac_startup,\n+\t.shutdown = snd_rpi_chipdip_dac_shutdown,\n+};\n+\n+SND_SOC_DAILINK_DEFS(hifi,\n+\tDAILINK_COMP_ARRAY(COMP_CPU(\"bcm2708-i2s.0\")),\n+\tDAILINK_COMP_ARRAY(COMP_CODEC(\"spdif-transmitter\", \"dit-hifi\")),\n+\tDAILINK_COMP_ARRAY(COMP_PLATFORM(\"bcm2708-i2s.0\")));\n+\n+static struct snd_soc_dai_link snd_rpi_chipdip_dac_dai[] = {\n+{\n+\t.name\t\t= \"ChipDip DAC\",\n+\t.stream_name\t= \"ChipDip DAC HiFi\",\n+\t.dai_fmt\t= SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |\n+\t\t\t\tSND_SOC_DAIFMT_CBM_CFM,\n+\t.ops\t\t= &snd_rpi_chipdip_dac_ops,\n+\t.init\t\t= snd_rpi_chipdip_dac_init,\n+\tSND_SOC_DAILINK_REG(hifi),\n+},\n+};\n+\n+/* audio machine driver */\n+static struct snd_soc_card snd_rpi_chipdip_dac = {\n+\t.name         = \"ChipDipDAC\",\n+\t.driver_name  = \"ChipdipDac\",\n+\t.owner        = THIS_MODULE,\n+\t.dai_link     = snd_rpi_chipdip_dac_dai,\n+\t.num_links    = ARRAY_SIZE(snd_rpi_chipdip_dac_dai),\n+};\n+\n+static int snd_rpi_chipdip_dac_probe(struct platform_device *pdev)\n+{\n+\tint ret = 0;\n+\tint i = 0;\n+\n+\tsnd_rpi_chipdip_dac.dev = &pdev->dev;\n+\n+\tif (pdev->dev.of_node) {\n+\t\tstruct device_node *i2s_node;\n+\t\tstruct snd_soc_dai_link *dai = &snd_rpi_chipdip_dac_dai[0];\n+\t\ti2s_node = of_parse_phandle(pdev->dev.of_node,\n+\t\t\t\t\t\"i2s-controller\", 0);\n+\n+\t\tif (i2s_node) {\n+\t\t\tdai->cpus->dai_name = NULL;\n+\t\t\tdai->cpus->of_node = i2s_node;\n+\t\t\tdai->platforms->name = NULL;\n+\t\t\tdai->platforms->of_node = i2s_node;\n+\t\t}\n+\t}\n+\n+\thw_params_gpios[SR_BIT_0] = devm_gpiod_get_optional(&pdev->dev, \"sr0\", GPIOD_OUT_LOW);\n+\thw_params_gpios[SR_BIT_1] = devm_gpiod_get_optional(&pdev->dev, \"sr1\", GPIOD_OUT_LOW);\n+\thw_params_gpios[SR_BIT_2] = devm_gpiod_get_optional(&pdev->dev, \"sr2\", GPIOD_OUT_LOW);\n+\thw_params_gpios[BD_BIT_0] = devm_gpiod_get_optional(&pdev->dev, \"res0\", GPIOD_OUT_LOW);\n+\thw_params_gpios[BD_BIT_1] = devm_gpiod_get_optional(&pdev->dev, \"res1\", GPIOD_OUT_LOW);\n+\tmute_gpio = devm_gpiod_get_optional(&pdev->dev, \"mute\", GPIOD_OUT_LOW);\n+\tsdwn_gpio = devm_gpiod_get_optional(&pdev->dev, \"sdwn\", GPIOD_OUT_HIGH);\n+\n+\tfor (i = 0; i < HW_PARAMS_GPIO_COUNT; i++) {\n+\t\tif (IS_ERR(hw_params_gpios[i])) {\n+\t\t\tret = PTR_ERR(hw_params_gpios[i]);\n+\t\t\tdev_err(&pdev->dev, \"failed to get hw_params gpio: %d\\n\", ret);\n+\t\t\treturn ret;\n+\t\t}\n+\t}\n+\n+\tif (IS_ERR(mute_gpio)) {\n+\t\tret = PTR_ERR(mute_gpio);\n+\t\tdev_err(&pdev->dev, \"failed to get mute gpio: %d\\n\", ret);\n+\t\treturn ret;\n+\t}\n+\n+\tif (IS_ERR(sdwn_gpio)) {\n+\t\tret = PTR_ERR(sdwn_gpio);\n+\t\tdev_err(&pdev->dev, \"failed to get sdwn gpio: %d\\n\", ret);\n+\t\treturn ret;\n+\t}\n+\n+\tsnd_rpi_chipdip_dac_gpio_set(sdwn_gpio, 1);\n+\n+\tret = devm_snd_soc_register_card(&pdev->dev, &snd_rpi_chipdip_dac);\n+\tif (ret && ret != -EPROBE_DEFER)\n+\t\tdev_err(&pdev->dev,\n+\t\t\t\"snd_soc_register_card() failed: %d\\n\", ret);\n+\n+\treturn ret;\n+}\n+\n+static const struct of_device_id snd_rpi_chipdip_dac_of_match[] = {\n+\t{ .compatible = \"chipdip,chipdip-dac\", },\n+\t{},\n+};\n+MODULE_DEVICE_TABLE(of, snd_rpi_chipdip_dac_of_match);\n+\n+static struct platform_driver snd_rpi_chipdip_dac_driver = {\n+\t.driver = {\n+\t\t.name   = \"snd-rpi-chipdip-dac\",\n+\t\t.owner  = THIS_MODULE,\n+\t\t.of_match_table = snd_rpi_chipdip_dac_of_match,\n+\t},\n+\t.probe          = snd_rpi_chipdip_dac_probe,\n+};\n+\n+module_platform_driver(snd_rpi_chipdip_dac_driver);\n+\n+MODULE_AUTHOR(\"Evgenij Sapunov <evgenij.sapunov@chipdip.ru>\");\n+MODULE_DESCRIPTION(\"ASoC Driver for ChipDip DAC\");\n+MODULE_LICENSE(\"GPL v2\");\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0724-char-vc_mem-Delete-dead-code.patch",
    "content": "From 2fd0a43bfe9e3e53fe566759d6c2cb63ba557ad3 Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.com>\nDate: Wed, 28 Jul 2021 09:49:21 +0100\nSubject: [PATCH] char: vc_mem: Delete dead code\n\nThere are no error exists once device_create has succeeded, and\ntherefore no need to call device_destroy from vc_mem_init.\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.com>\n---\n drivers/char/broadcom/vc_mem.c | 2 --\n 1 file changed, 2 deletions(-)\n\n--- a/drivers/char/broadcom/vc_mem.c\n+++ b/drivers/char/broadcom/vc_mem.c\n@@ -333,8 +333,6 @@ vc_mem_init(void)\n \tvc_mem_inited = 1;\n \treturn 0;\n \n-\tdevice_destroy(vc_mem_class, vc_mem_devnum);\n-\n out_class_destroy:\n \tclass_destroy(vc_mem_class);\n \tvc_mem_class = NULL;\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0725-overlays-Add-Ablic-S35390A-to-i2c-rtc-and-gpio.patch",
    "content": "From 886c341229589e7d46cbdb8194c23faee0e2a6f9 Mon Sep 17 00:00:00 2001\nFrom: WoodenNautilus <86767647+WoodenNautilus@users.noreply.github.com>\nDate: Tue, 3 Aug 2021 11:13:06 +0200\nSubject: [PATCH] overlays: Add Ablic S35390A to i2c-rtc and -gpio\n\nSee: https://github.com/raspberrypi/linux/pull/4492\n\nSigned-off-by: Maxime Torrelli <maxime.torrelli@gmail.com>\n---\n arch/arm/boot/dts/overlays/README              |  4 ++++\n arch/arm/boot/dts/overlays/i2c-rtc-common.dtsi | 17 ++++++++++++++++-\n 2 files changed, 20 insertions(+), 1 deletion(-)\n\n--- a/arch/arm/boot/dts/overlays/README\n+++ b/arch/arm/boot/dts/overlays/README\n@@ -1424,6 +1424,8 @@ Params: abx80x                  Select o\n \n         sd3078                  Select the ZXW Shenzhen whwave SD3078 device\n \n+        s35390a                 Select the ABLIC S35390A device\n+\n         i2c0                    Choose the I2C0 bus on GPIOs 0&1\n \n         i2c_csi_dsi             Choose the I2C0 bus on GPIOs 44&45\n@@ -1487,6 +1489,8 @@ Params: abx80x                  Select o\n \n         sd3078                  Select the ZXW Shenzhen whwave SD3078 device\n \n+        s35390a                 Select the ABLIC S35390A device\n+\n         addr                    Sets the address for the RTC. Note that the\n                                 device must be configured to use the specified\n                                 address.\n--- a/arch/arm/boot/dts/overlays/i2c-rtc-common.dtsi\n+++ b/arch/arm/boot/dts/overlays/i2c-rtc-common.dtsi\n@@ -243,6 +243,19 @@\n \t\t};\n \t};\n \n+\tfragment@18 {\n+\t\ttarget = <&i2cbus>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\ts35390a: s35390a@30 {\n+\t\t\t\tcompatible = \"ablic,s35390a\";\n+\t\t\t\treg = <0x30>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n \t__overrides__ {\n \t\tabx80x = <0>,\"+0\";\n \t\tds1307 = <0>,\"+1\";\n@@ -262,6 +275,7 @@\n \t\tsd3078 = <0>,\"+14\";\n \t\tpcf85063 = <0>,\"+15\";\n \t\tpcf85063a = <0>,\"+16\";\n+\t\ts35390a = <0>,\"+18\";\n \n \t\taddr = <&abx80x>, \"reg:0\",\n \t\t       <&ds1307>, \"reg:0\",\n@@ -272,7 +286,8 @@\n \t\t       <&pcf8523>, \"reg:0\",\n \t\t       <&pcf8563>, \"reg:0\",\n \t\t       <&m41t62>, \"reg:0\",\n-\t\t       <&rv1805>, \"reg:0\";\n+\t\t       <&rv1805>, \"reg:0\",\n+\t\t       <&s35390a>, \"reg:0\";\n \t\ttrickle-diode-type = <&abx80x>,\"abracon,tc-diode\",\n \t\t\t\t     <&rv1805>,\"abracon,tc-diode\";\n \t\ttrickle-resistor-ohms = <&ds1339>,\"trickle-resistor-ohms:0\",\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0726-dtoverlays-Add-orientation-and-rotation-parameter-to.patch",
    "content": "From 9637391eb4ad9410f4a366b4d78c7cfd909572da Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Mon, 2 Aug 2021 14:30:15 +0100\nSubject: [PATCH] dtoverlays: Add orientation (and rotation) parameter\n to sensor overlays\n\nAdd the orientation parameter to all the camera sensor overlays to\navoid libcamera complaining, and add the rotation parameter where\nit hadn't been added before.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n arch/arm/boot/dts/overlays/README             | 26 ++++++++++++++++---\n arch/arm/boot/dts/overlays/imx219-overlay.dts |  2 ++\n .../boot/dts/overlays/imx290_327-overlay.dtsi |  5 ++++\n .../boot/dts/overlays/imx477_378-overlay.dtsi |  2 ++\n arch/arm/boot/dts/overlays/ov5647-overlay.dts |  2 ++\n arch/arm/boot/dts/overlays/ov7251-overlay.dts |  8 ++++++\n arch/arm/boot/dts/overlays/ov9281-overlay.dts |  7 +++++\n 7 files changed, 48 insertions(+), 4 deletions(-)\n\n--- a/arch/arm/boot/dts/overlays/README\n+++ b/arch/arm/boot/dts/overlays/README\n@@ -1682,6 +1682,8 @@ Info:   Sony IMX219 camera module.\n Load:   dtoverlay=imx219,<param>=<val>\n Params: rotation                Mounting rotation of the camera sensor (0 or\n                                 180, default 180)\n+        orientation             Sensor orientation (0 = front, 1 = rear,\n+                                2 = external, default external)\n \n \n Name:   imx290\n@@ -1698,6 +1700,10 @@ Params: 4lane                   Enable 4\n                                 (the default), whilst those from Innomaker use\n                                 74.25MHz.\n         mono                    Denote that the module is a mono sensor.\n+        orientation             Sensor orientation (0 = front, 1 = rear,\n+                                2 = external, default external)\n+        rotation                Mounting rotation of the camera sensor (0 or\n+                                180, default 0)\n \n \n Name:   imx378\n@@ -1707,6 +1713,8 @@ Info:   Sony IMX378 camera module.\n Load:   dtoverlay=imx378,<param>=<val>\n Params: rotation                Mounting rotation of the camera sensor (0 or\n                                 180, default 180)\n+        orientation             Sensor orientation (0 = front, 1 = rear,\n+                                2 = external, default external)\n \n \n Name:   imx477\n@@ -1716,6 +1724,8 @@ Info:   Sony IMX477 camera module.\n Load:   dtoverlay=imx477,<param>=<val>\n Params: rotation                Mounting rotation of the camera sensor (0 or\n                                 180, default 180)\n+        orientation             Sensor orientation (0 = front, 1 = rear,\n+                                2 = external, default external)\n \n \n Name:   iqaudio-codec\n@@ -2141,22 +2151,30 @@ Info:   Omnivision OV5647 camera module.\n Load:   dtoverlay=ov5647,<param>=<val>\n Params: rotation                Mounting rotation of the camera sensor (0 or\n                                 180, default 0)\n+        orientation             Sensor orientation (0 = front, 1 = rear,\n+                                2 = external, default external)\n \n \n Name:   ov7251\n Info:   Omnivision OV7251 camera module.\n         Uses Unicam 1, which is the standard camera connector on most Pi\n         variants.\n-Load:   dtoverlay=ov7251\n-Params: <None>\n+Load:   dtoverlay=ov7251,<param>=<val>\n+Params: rotation                Mounting rotation of the camera sensor (0 or\n+                                180, default 0)\n+        orientation             Sensor orientation (0 = front, 1 = rear,\n+                                2 = external, default external)\n \n \n Name:   ov9281\n Info:   Omnivision OV9281 camera module.\n         Uses Unicam 1, which is the standard camera connector on most Pi\n         variants.\n-Load:   dtoverlay=ov9281\n-Params: <None>\n+Load:   dtoverlay=ov9281,<param>=<val>\n+Params: rotation                Mounting rotation of the camera sensor (0 or\n+                                180, default 0)\n+        orientation             Sensor orientation (0 = front, 1 = rear,\n+                                2 = external, default external)\n \n \n Name:   papirus\n--- a/arch/arm/boot/dts/overlays/imx219-overlay.dts\n+++ b/arch/arm/boot/dts/overlays/imx219-overlay.dts\n@@ -28,6 +28,7 @@\n \t\t\t\tVDDL-supply = <&imx219_vddl>;\t/* 1.2v */\n \n \t\t\t\trotation = <180>;\n+\t\t\t\torientation = <2>;\n \n \t\t\t\tport {\n \t\t\t\t\timx219_0: endpoint {\n@@ -109,5 +110,6 @@\n \n \t__overrides__ {\n \t\trotation = <&imx219>,\"rotation:0\";\n+\t\torientation = <&imx219>,\"orientation:0\";\n \t};\n };\n--- a/arch/arm/boot/dts/overlays/imx290_327-overlay.dtsi\n+++ b/arch/arm/boot/dts/overlays/imx290_327-overlay.dtsi\n@@ -24,6 +24,9 @@\n \t\t\t\tclock-names = \"xclk\";\n \t\t\t\tclock-frequency = <37125000>;\n \n+\t\t\t\trotation = <0>;\n+\t\t\t\torientation = <2>;\n+\n \t\t\t\tvdda-supply = <&cam1_reg>;\t/* 2.8v */\n \t\t\t\tvdddo-supply = <&imx290_vdddo>;\t/* 1.8v */\n \t\t\t\tvddd-supply = <&imx290_vddd>;\t/* 1.5v */\n@@ -135,5 +138,7 @@\n \t\t4lane = <0>, \"-6+7-8+9\";\n \t\tclock-frequency = <&imx290_clk>,\"clock-frequency:0\",\n \t\t\t\t  <&imx290>,\"clock-frequency:0\";\n+\t\trotation = <&imx290>,\"rotation:0\";\n+\t\torientation = <&imx290>,\"orientation:0\";\n \t};\n };\n--- a/arch/arm/boot/dts/overlays/imx477_378-overlay.dtsi\n+++ b/arch/arm/boot/dts/overlays/imx477_378-overlay.dtsi\n@@ -23,6 +23,7 @@\n \t\t\t\tVDDL-supply = <&imx477_vddl>;\t/* 1.8v */\n \n \t\t\t\trotation = <180>;\n+\t\t\t\torientation = <2>;\n \n \t\t\t\tport {\n \t\t\t\t\timx477_0: endpoint {\n@@ -104,5 +105,6 @@\n \n \t__overrides__ {\n \t\trotation = <&imx477>,\"rotation:0\";\n+\t\torientation = <&imx477>,\"orientation:0\";\n \t};\n };\n--- a/arch/arm/boot/dts/overlays/ov5647-overlay.dts\n+++ b/arch/arm/boot/dts/overlays/ov5647-overlay.dts\n@@ -22,6 +22,7 @@\n \t\t\t\tclocks = <&ov5647_clk>;\n \n \t\t\t\trotation = <0>;\n+\t\t\t\torientation = <2>;\n \n \t\t\t\tport {\n \t\t\t\t\tov5647_0: endpoint {\n@@ -88,5 +89,6 @@\n \n \t__overrides__ {\n \t\trotation = <&ov5647>,\"rotation:0\";\n+\t\torientation = <&ov5647>,\"orientation:0\";\n \t};\n };\n--- a/arch/arm/boot/dts/overlays/ov7251-overlay.dts\n+++ b/arch/arm/boot/dts/overlays/ov7251-overlay.dts\n@@ -28,6 +28,9 @@\n \t\t\t\tvdda-supply = <&cam1_reg>;\n \t\t\t\tvddd-supply = <&ov7251_dvdd>;\n \n+\t\t\t\trotation = <0>;\n+\t\t\t\torientation = <2>;\n+\n \t\t\t\tport {\n \t\t\t\t\tov7251_0: endpoint {\n \t\t\t\t\t\tremote-endpoint = <&csi1_ep>;\n@@ -102,4 +105,9 @@\n \t\t\tregulator-max-microvolt = <2800000>;\n \t\t};\n \t};\n+\n+\t__overrides__ {\n+\t\trotation = <&ov7251>,\"rotation:0\";\n+\t\torientation = <&ov7251>,\"orientation:0\";\n+\t};\n };\n--- a/arch/arm/boot/dts/overlays/ov9281-overlay.dts\n+++ b/arch/arm/boot/dts/overlays/ov9281-overlay.dts\n@@ -27,6 +27,9 @@\n \t\t\t\tdovdd-supply = <&ov9281_dovdd>;\n \t\t\t\tdvdd-supply = <&ov9281_dvdd>;\n \n+\t\t\t\trotation = <0>;\n+\t\t\t\torientation = <2>;\n+\n \t\t\t\tport {\n \t\t\t\t\tov9281_0: endpoint {\n \t\t\t\t\t\tremote-endpoint = <&csi1_ep>;\n@@ -103,4 +106,8 @@\n \t\t};\n \t};\n \n+\t__overrides__ {\n+\t\trotation = <&ov9281>,\"rotation:0\";\n+\t\torientation = <&ov9281>,\"orientation:0\";\n+\t};\n };\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0727-media-i2c-imx290-Add-fwnode-properties-controls.patch",
    "content": "From 5aeffc428adfd3a97014056e36fd5496119da743 Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Tue, 3 Aug 2021 11:25:59 +0100\nSubject: [PATCH] media: i2c: imx290: Add fwnode properties controls\n\nAdd call to v4l2_ctrl_new_fwnode_properties to read and\ncreate the fwnode based controls.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n drivers/media/i2c/imx290.c | 12 +++++++++++-\n 1 file changed, 11 insertions(+), 1 deletion(-)\n\n--- a/drivers/media/i2c/imx290.c\n+++ b/drivers/media/i2c/imx290.c\n@@ -1242,6 +1242,7 @@ static const struct of_device_id imx290_\n \n static int imx290_probe(struct i2c_client *client)\n {\n+\tstruct v4l2_fwnode_device_properties props;\n \tstruct device *dev = &client->dev;\n \tstruct fwnode_handle *endpoint;\n \t/* Only CSI2 is supported for now: */\n@@ -1363,7 +1364,7 @@ static int imx290_probe(struct i2c_clien\n \t */\n \timx290_entity_init_cfg(&imx290->sd, NULL);\n \n-\tv4l2_ctrl_handler_init(&imx290->ctrls, 9);\n+\tv4l2_ctrl_handler_init(&imx290->ctrls, 11);\n \n \tv4l2_ctrl_new_std(&imx290->ctrls, &imx290_ctrl_ops,\n \t\t\t  V4L2_CID_ANALOGUE_GAIN, 0, 100, 1, 0);\n@@ -1411,6 +1412,15 @@ static int imx290_probe(struct i2c_clien\n \t\t\t\t     ARRAY_SIZE(imx290_test_pattern_menu) - 1,\n \t\t\t\t     0, 0, imx290_test_pattern_menu);\n \n+\tret = v4l2_fwnode_device_parse(&client->dev, &props);\n+\tif (ret)\n+\t\tgoto free_ctrl;\n+\n+\tret = v4l2_ctrl_new_fwnode_properties(&imx290->ctrls, &imx290_ctrl_ops,\n+\t\t\t\t\t      &props);\n+\tif (ret)\n+\t\tgoto free_ctrl;\n+\n \timx290->sd.ctrl_handler = &imx290->ctrls;\n \n \tif (imx290->ctrls.error) {\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0728-media-i2c-ov9281-Add-fwnode-properties-controls.patch",
    "content": "From d7afaa8a210db98544d53fc319187191ae9807b4 Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Tue, 3 Aug 2021 11:30:58 +0100\nSubject: [PATCH] media: i2c: ov9281: Add fwnode properties controls\n\nAdd call to v4l2_ctrl_new_fwnode_properties to read and\ncreate the fwnode based controls.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n drivers/media/i2c/ov9281.c | 13 ++++++++++++-\n 1 file changed, 12 insertions(+), 1 deletion(-)\n\n--- a/drivers/media/i2c/ov9281.c\n+++ b/drivers/media/i2c/ov9281.c\n@@ -25,6 +25,7 @@\n #include <media/media-entity.h>\n #include <media/v4l2-async.h>\n #include <media/v4l2-ctrls.h>\n+#include <media/v4l2-fwnode.h>\n #include <media/v4l2-subdev.h>\n \n #define OV9281_LINK_FREQ_400MHZ\t\t400000000\n@@ -1020,6 +1021,7 @@ static const struct v4l2_ctrl_ops ov9281\n \n static int ov9281_initialize_controls(struct ov9281 *ov9281)\n {\n+\tstruct v4l2_fwnode_device_properties props;\n \tconst struct ov9281_mode *mode;\n \tstruct v4l2_ctrl_handler *handler;\n \tstruct v4l2_ctrl *ctrl;\n@@ -1029,7 +1031,7 @@ static int ov9281_initialize_controls(st\n \n \thandler = &ov9281->ctrl_handler;\n \tmode = ov9281->cur_mode;\n-\tret = v4l2_ctrl_handler_init(handler, 9);\n+\tret = v4l2_ctrl_handler_init(handler, 11);\n \tif (ret)\n \t\treturn ret;\n \thandler->lock = &ov9281->mutex;\n@@ -1091,6 +1093,15 @@ static int ov9281_initialize_controls(st\n \t\tgoto err_free_handler;\n \t}\n \n+\tret = v4l2_fwnode_device_parse(&ov9281->client->dev, &props);\n+\tif (ret)\n+\t\tgoto err_free_handler;\n+\n+\tret = v4l2_ctrl_new_fwnode_properties(handler, &ov9281_ctrl_ops,\n+\t\t\t\t\t      &props);\n+\tif (ret)\n+\t\tgoto err_free_handler;\n+\n \tov9281->subdev.ctrl_handler = handler;\n \n \treturn 0;\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0729-media-i2c-ov7251-Add-fwnode-properties-controls.patch",
    "content": "From f58356e67346323ffd3061aea7ca16c0f0f6a72e Mon Sep 17 00:00:00 2001\nFrom: Dave Stevenson <dave.stevenson@raspberrypi.com>\nDate: Tue, 3 Aug 2021 11:33:33 +0100\nSubject: [PATCH] media: i2c: ov7251: Add fwnode properties controls\n\nAdd call to v4l2_ctrl_new_fwnode_properties to read and\ncreate the fwnode based controls.\n\nSigned-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>\n---\n drivers/media/i2c/ov7251.c | 12 +++++++++++-\n 1 file changed, 11 insertions(+), 1 deletion(-)\n\n--- a/drivers/media/i2c/ov7251.c\n+++ b/drivers/media/i2c/ov7251.c\n@@ -1253,6 +1253,7 @@ static const struct v4l2_subdev_ops ov72\n \n static int ov7251_probe(struct i2c_client *client)\n {\n+\tstruct v4l2_fwnode_device_properties props;\n \tstruct device *dev = &client->dev;\n \tstruct fwnode_handle *endpoint;\n \tstruct ov7251 *ov7251;\n@@ -1338,7 +1339,7 @@ static int ov7251_probe(struct i2c_clien\n \n \tmutex_init(&ov7251->lock);\n \n-\tv4l2_ctrl_handler_init(&ov7251->ctrls, 7);\n+\tv4l2_ctrl_handler_init(&ov7251->ctrls, 9);\n \tov7251->ctrls.lock = &ov7251->lock;\n \n \tv4l2_ctrl_new_std(&ov7251->ctrls, &ov7251_ctrl_ops,\n@@ -1374,6 +1375,15 @@ static int ov7251_probe(struct i2c_clien\n \t\tgoto free_ctrl;\n \t}\n \n+\tret = v4l2_fwnode_device_parse(&client->dev, &props);\n+\tif (ret)\n+\t\tgoto free_ctrl;\n+\n+\tret = v4l2_ctrl_new_fwnode_properties(&ov7251->ctrls, &ov7251_ctrl_ops,\n+\t\t\t\t\t      &props);\n+\tif (ret)\n+\t\tgoto free_ctrl;\n+\n \tv4l2_i2c_subdev_init(&ov7251->sd, client, &ov7251_subdev_ops);\n \tov7251->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;\n \tov7251->pad.flags = MEDIA_PAD_FL_SOURCE;\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0730-overlays-Reduce-Pi-4-vc4-CMA-size-to-320MB.patch",
    "content": "From 0d5d8f373125e5bdf331d8fc579b2cf18171c1c0 Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.com>\nDate: Tue, 3 Aug 2021 11:32:30 +0100\nSubject: [PATCH] overlays: Reduce Pi 4 vc4 CMA size to 320MB\n\nReduce the default CMA allocation requested by the vc4-kms-v3d-pi4 and\nvc4-fkms-v3d-pi4 overlays to 320MB.\n\nUse magic values of the form (<n>*64 - 4)MB to encode default values\nof <n>*64MB, allowing these defaults to be distinguished from values\nset explicitly by the user with the usual overlay parameters (e.g.\n\"cma-384\"). Only default values will be capped if the Pi RAM is too\nsmall or the gpu_mem setting too large for it to be viable.\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.com>\n---\n arch/arm/boot/dts/overlays/vc4-fkms-v3d-pi4-overlay.dts | 2 +-\n arch/arm/boot/dts/overlays/vc4-kms-v3d-pi4-overlay.dts  | 2 +-\n 2 files changed, 2 insertions(+), 2 deletions(-)\n\n--- a/arch/arm/boot/dts/overlays/vc4-fkms-v3d-pi4-overlay.dts\n+++ b/arch/arm/boot/dts/overlays/vc4-fkms-v3d-pi4-overlay.dts\n@@ -8,7 +8,7 @@\n #include \"cma-overlay.dts\"\n \n &frag0 {\n-       size = <(512*1024*1024)>;\n+\tsize = <((320-4)*1024*1024)>;\n };\n \n / {\n--- a/arch/arm/boot/dts/overlays/vc4-kms-v3d-pi4-overlay.dts\n+++ b/arch/arm/boot/dts/overlays/vc4-kms-v3d-pi4-overlay.dts\n@@ -10,7 +10,7 @@\n #include \"cma-overlay.dts\"\n \n &frag0 {\n-       size = <(512*1024*1024)>;\n+\tsize = <((320-4)*1024*1024)>;\n };\n \n / {\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0731-Revert-overlays-Update-display-GPIO-declarations-for.patch",
    "content": "From c90422ce5c24b9f1f4c03e935918e85bef6cb336 Mon Sep 17 00:00:00 2001\nFrom: Ahmet Inan <inan@aicodix.de>\nDate: Wed, 4 Aug 2021 10:10:11 +0200\nSubject: [PATCH] Revert \"overlays: Update display GPIO declarations\"\n for Goodix\n\nThis reverts commit b7d685c0b1bd1b98af0e9c1f5d43769982bdbfb2 for Goodix\n\nSigned-off-by: Ahmet Inan <inan@aicodix.de>\n---\n arch/arm/boot/dts/overlays/goodix-overlay.dts | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/arch/arm/boot/dts/overlays/goodix-overlay.dts\n+++ b/arch/arm/boot/dts/overlays/goodix-overlay.dts\n@@ -31,7 +31,7 @@\n \t\t\t\tinterrupt-parent = <&gpio>;\n \t\t\t\tinterrupts = <4 2>; // high-to-low edge triggered\n \t\t\t\tirq-gpios = <&gpio 4 0>; // Pin7 on GPIO header\n-\t\t\t\treset-gpios = <&gpio 17 1>; // Pin11 on GPIO header\n+\t\t\t\treset-gpios = <&gpio 17 0>; // Pin11 on GPIO header\n \t\t\t};\n \t\t};\n \t};\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0732-overlays-Add-midi-uart-2345-overlay.dts.patch",
    "content": "From 37f172b47784a4debc62cb71974eac303031e69c Mon Sep 17 00:00:00 2001\nFrom: pjx3 <pjx3@users.noreply.github.com>\nDate: Sun, 8 Aug 2021 20:09:46 +0100\nSubject: [PATCH] overlays: Add midi-uart{2345}-overlay.dts\n\nAdded overlays for enabling MIDI baudrates on additional UARTs\n\nSigned-off-by: Pete Marshall <petemarshall303@gmail.com>\n---\n arch/arm/boot/dts/overlays/Makefile           |  4 ++\n arch/arm/boot/dts/overlays/README             | 28 ++++++++++++++\n .../boot/dts/overlays/midi-uart2-overlay.dts  | 37 ++++++++++++++++++\n .../boot/dts/overlays/midi-uart3-overlay.dts  | 38 +++++++++++++++++++\n .../boot/dts/overlays/midi-uart4-overlay.dts  | 38 +++++++++++++++++++\n .../boot/dts/overlays/midi-uart5-overlay.dts  | 38 +++++++++++++++++++\n 6 files changed, 183 insertions(+)\n create mode 100644 arch/arm/boot/dts/overlays/midi-uart2-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/midi-uart3-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/midi-uart4-overlay.dts\n create mode 100644 arch/arm/boot/dts/overlays/midi-uart5-overlay.dts\n\n--- a/arch/arm/boot/dts/overlays/Makefile\n+++ b/arch/arm/boot/dts/overlays/Makefile\n@@ -123,6 +123,10 @@ dtbo-$(CONFIG_ARCH_BCM2835) += \\\n \tmerus-amp.dtbo \\\n \tmidi-uart0.dtbo \\\n \tmidi-uart1.dtbo \\\n+\tmidi-uart2.dtbo \\\n+\tmidi-uart3.dtbo \\\n+\tmidi-uart4.dtbo \\\n+\tmidi-uart5.dtbo \\\n \tminipitft13.dtbo \\\n \tminiuart-bt.dtbo \\\n \tmmc.dtbo \\\n--- a/arch/arm/boot/dts/overlays/README\n+++ b/arch/arm/boot/dts/overlays/README\n@@ -2088,6 +2088,34 @@ Load:   dtoverlay=midi-uart1\n Params: <None>\n \n \n+Name:   midi-uart2\n+Info:   Configures UART2 (ttyAMA1) so that a requested 38.4kbaud actually gets\n+        31.25kbaud, the frequency required for MIDI\n+Load:   dtoverlay=midi-uart2\n+Params: <None>\n+\n+\n+Name:   midi-uart3\n+Info:   Configures UART3 (ttyAMA2) so that a requested 38.4kbaud actually gets\n+        31.25kbaud, the frequency required for MIDI\n+Load:   dtoverlay=midi-uart3\n+Params: <None>\n+\n+\n+Name:   midi-uart4\n+Info:   Configures UART4 (ttyAMA3) so that a requested 38.4kbaud actually gets\n+        31.25kbaud, the frequency required for MIDI\n+Load:   dtoverlay=midi-uart4\n+Params: <None>\n+\n+\n+Name:   midi-uart5\n+Info:   Configures UART5 (ttyAMA4) so that a requested 38.4kbaud actually gets\n+        31.25kbaud, the frequency required for MIDI\n+Load:   dtoverlay=midi-uart5\n+Params: <None>\n+\n+\n Name:   minipitft13\n Info:   Overlay for AdaFruit Mini Pi 1.3\" TFT via SPI using fbtft driver.\n Load:   dtoverlay=minipitft13,<param>=<val>\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/midi-uart2-overlay.dts\n@@ -0,0 +1,37 @@\n+/dts-v1/;\n+/plugin/;\n+\n+#include <dt-bindings/clock/bcm2835.h>\n+\n+/*\n+ * Fake a higher clock rate to get a larger divisor, and thereby a lower\n+ * baudrate. The real clock is 48MHz, which we scale so that requesting\n+ * 38.4kHz results in an actual 31.25kHz.\n+ *\n+ *   48000000*38400/31250 = 58982400\n+ */\n+\n+/{\n+        compatible = \"brcm,bcm2835\";\n+\n+        fragment@0 {\n+                target-path = \"/\";\n+                __overlay__ {\n+                        midi_clk: midi_clk2 {\n+                                compatible = \"fixed-clock\";\n+                                #clock-cells = <0>;\n+                                clock-output-names = \"uart2_pclk\";\n+                                clock-frequency = <58982400>;\n+                        };\n+                };\n+        };\n+\n+        fragment@1 {\n+                target = <&uart2>;\n+                __overlay__ {\n+                        clocks = <&midi_clk>,\n+                                 <&clocks BCM2835_CLOCK_VPU>;\n+                };\n+        };\n+};\n+\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/midi-uart3-overlay.dts\n@@ -0,0 +1,38 @@\n+/dts-v1/;\n+/plugin/;\n+\n+#include <dt-bindings/clock/bcm2835.h>\n+\n+/*\n+ * Fake a higher clock rate to get a larger divisor, and thereby a lower\n+ * baudrate. The real clock is 48MHz, which we scale so that requesting\n+ * 38.4kHz results in an actual 31.25kHz.\n+ *\n+ *   48000000*38400/31250 = 58982400\n+ */\n+\n+/{\n+        compatible = \"brcm,bcm2835\";\n+\n+        fragment@0 {\n+                target-path = \"/\";\n+                __overlay__ {\n+                        midi_clk: midi_clk3 {\n+                                compatible = \"fixed-clock\";\n+                                #clock-cells = <0>;\n+                                clock-output-names = \"uart3_pclk\";\n+                                clock-frequency = <58982400>;\n+                        };\n+                };\n+        };\n+\n+        fragment@1 {\n+                target = <&uart3>;\n+                __overlay__ {\n+                        clocks = <&midi_clk>,\n+                                 <&clocks BCM2835_CLOCK_VPU>;\n+                };\n+        };\n+};\n+\n+\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/midi-uart4-overlay.dts\n@@ -0,0 +1,38 @@\n+/dts-v1/;\n+/plugin/;\n+\n+#include <dt-bindings/clock/bcm2835.h>\n+\n+/*\n+ * Fake a higher clock rate to get a larger divisor, and thereby a lower\n+ * baudrate. The real clock is 48MHz, which we scale so that requesting\n+ * 38.4kHz results in an actual 31.25kHz.\n+ *\n+ *   48000000*38400/31250 = 58982400\n+ */\n+\n+/{\n+        compatible = \"brcm,bcm2835\";\n+\n+        fragment@0 {\n+                target-path = \"/\";\n+                __overlay__ {\n+                        midi_clk: midi_clk4 {\n+                                compatible = \"fixed-clock\";\n+                                #clock-cells = <0>;\n+                                clock-output-names = \"uart4_pclk\";\n+                                clock-frequency = <58982400>;\n+                        };\n+                };\n+        };\n+\n+        fragment@1 {\n+                target = <&uart4>;\n+                __overlay__ {\n+                        clocks = <&midi_clk>,\n+                                 <&clocks BCM2835_CLOCK_VPU>;\n+                };\n+        };\n+};\n+\n+\n--- /dev/null\n+++ b/arch/arm/boot/dts/overlays/midi-uart5-overlay.dts\n@@ -0,0 +1,38 @@\n+/dts-v1/;\n+/plugin/;\n+\n+#include <dt-bindings/clock/bcm2835.h>\n+\n+/*\n+ * Fake a higher clock rate to get a larger divisor, and thereby a lower\n+ * baudrate. The real clock is 48MHz, which we scale so that requesting\n+ * 38.4kHz results in an actual 31.25kHz.\n+ *\n+ *   48000000*38400/31250 = 58982400\n+ */\n+\n+/{\n+        compatible = \"brcm,bcm2835\";\n+\n+        fragment@0 {\n+                target-path = \"/\";\n+                __overlay__ {\n+                        midi_clk: midi_clk5 {\n+                                compatible = \"fixed-clock\";\n+                                #clock-cells = <0>;\n+                                clock-output-names = \"uart5_pclk\";\n+                                clock-frequency = <58982400>;\n+                        };\n+                };\n+        };\n+\n+        fragment@1 {\n+                target = <&uart5>;\n+                __overlay__ {\n+                        clocks = <&midi_clk>,\n+                                 <&clocks BCM2835_CLOCK_VPU>;\n+                };\n+        };\n+};\n+\n+\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0733-usb-xhci-workaround-for-bogus-SET_DEQ_PENDING-endpoi.patch",
    "content": "From dedd960b894217ae0960a7ac493def9edfa96905 Mon Sep 17 00:00:00 2001\nFrom: Jonathan Bell <jonathan@raspberrypi.com>\nDate: Wed, 11 Aug 2021 15:33:57 +0100\nSubject: [PATCH] usb: xhci: workaround for bogus SET_DEQ_PENDING\n endpoint state\n\nSee https://github.com/raspberrypi/linux/issues/3981\n\nAn unknown unsafe memory access can result in the ep_state variable\nin xhci_virt_ep being trampled with a stuck SET_DEQ_PENDING state\ndespite successful completion of a Set TR Deq Pointer command.\n\nAll URB enqueue/dequeue calls for the endpoint will fail in this state\nso no transfers are possible until the device is reconnected.\n\nAs a workaround, clear the flag if we see it set and issue a new Set\nTR Deq command anyway - this should be harmless, as a prior Set TR Deq\ncommand will only have been issued in the Stopped state, and if the\nendpoint is Running then the controller is required to ignore it and\nrespond with a Context State Error event TRB.\n\nSigned-off-by: Jonathan Bell <jonathan@raspberrypi.com>\n---\n drivers/usb/host/xhci-ring.c | 6 +++---\n 1 file changed, 3 insertions(+), 3 deletions(-)\n\n--- a/drivers/usb/host/xhci-ring.c\n+++ b/drivers/usb/host/xhci-ring.c\n@@ -4268,9 +4268,9 @@ void xhci_queue_new_dequeue_state(struct\n \t}\n \tep = &xhci->devs[slot_id]->eps[ep_index];\n \tif ((ep->ep_state & SET_DEQ_PENDING)) {\n-\t\txhci_warn(xhci, \"WARN Cannot submit Set TR Deq Ptr\\n\");\n-\t\txhci_warn(xhci, \"A Set TR Deq Ptr command is pending.\\n\");\n-\t\treturn;\n+\t\txhci_warn(xhci, \"WARN A Set TR Deq Ptr command is pending for slot %u ep %u\\n\",\n+\t\t\t  slot_id, ep_index);\n+\t\tep->ep_state &= ~SET_DEQ_PENDING;\n \t}\n \n \t/* This function gets called from contexts where it cannot sleep */\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0734-overlays-Add-TI-BQ32000-RTC-support.patch",
    "content": "From 1afb520ffaf9667f18336aa4e983a2dd95462f20 Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.com>\nDate: Mon, 16 Aug 2021 11:11:35 +0100\nSubject: [PATCH] overlays: Add TI BQ32000 RTC support\n\nSee: https://github.com/raspberrypi/linux/issues/4531\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.com>\n---\n arch/arm/boot/dts/overlays/README             | 10 ++++++++++\n .../arm/boot/dts/overlays/i2c-rtc-common.dtsi | 20 ++++++++++++++++++-\n 2 files changed, 29 insertions(+), 1 deletion(-)\n\n--- a/arch/arm/boot/dts/overlays/README\n+++ b/arch/arm/boot/dts/overlays/README\n@@ -1390,6 +1390,8 @@ Params: abx80x                  Select o\n                                   AB0801, AB0803, AB0804, AB0805,\n                                   AB1801, AB1803, AB1804, AB1805\n \n+        bq32000                 Select the TI BQ32000 device\n+\n         ds1307                  Select the DS1307 device\n \n         ds1339                  Select the DS1339 device\n@@ -1434,6 +1436,9 @@ Params: abx80x                  Select o\n                                 device must be configured to use the specified\n                                 address.\n \n+        trickle-diode-disable   Do not use the internal trickle charger diode\n+                                (BQ32000 only)\n+\n         trickle-diode-type      Diode type for trickle charge - \"standard\" or\n                                 \"schottky\" (ABx80x and RV1805 only)\n \n@@ -1455,6 +1460,8 @@ Params: abx80x                  Select o\n                                   AB0801, AB0803, AB0804, AB0805,\n                                   AB1801, AB1803, AB1804, AB1805\n \n+        bq32000                 Select the TI BQ32000 device\n+\n         ds1307                  Select the DS1307 device\n \n         ds1339                  Select the DS1339 device\n@@ -1495,6 +1502,9 @@ Params: abx80x                  Select o\n                                 device must be configured to use the specified\n                                 address.\n \n+        trickle-diode-disable   Do not use the internal trickle charger diode\n+                                (BQ32000 only)\n+\n         trickle-diode-type      Diode type for trickle charge - \"standard\" or\n                                 \"schottky\" (ABx80x and RV1805 only)\n \n--- a/arch/arm/boot/dts/overlays/i2c-rtc-common.dtsi\n+++ b/arch/arm/boot/dts/overlays/i2c-rtc-common.dtsi\n@@ -256,6 +256,21 @@\n \t\t};\n \t};\n \n+\tfragment@19 {\n+\t\ttarget = <&i2cbus>;\n+\t\t__dormant__ {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tbq32000: bq32000@68 {\n+\t\t\t\tcompatible = \"ti,bq32000\";\n+\t\t\t\ttrickle-resistor-ohms = <0>;\n+\t\t\t\treg = <0x68>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\n \t__overrides__ {\n \t\tabx80x = <0>,\"+0\";\n \t\tds1307 = <0>,\"+1\";\n@@ -276,6 +291,7 @@\n \t\tpcf85063 = <0>,\"+15\";\n \t\tpcf85063a = <0>,\"+16\";\n \t\ts35390a = <0>,\"+18\";\n+\t\tbq32000 = <0>,\"+19\";\n \n \t\taddr = <&abx80x>, \"reg:0\",\n \t\t       <&ds1307>, \"reg:0\",\n@@ -288,13 +304,15 @@\n \t\t       <&m41t62>, \"reg:0\",\n \t\t       <&rv1805>, \"reg:0\",\n \t\t       <&s35390a>, \"reg:0\";\n+\t\ttrickle-diode-disable = <&bq32000>,\"trickle-diode-disable?\";\n \t\ttrickle-diode-type = <&abx80x>,\"abracon,tc-diode\",\n \t\t\t\t     <&rv1805>,\"abracon,tc-diode\";\n \t\ttrickle-resistor-ohms = <&ds1339>,\"trickle-resistor-ohms:0\",\n \t\t\t\t\t<&ds1340>,\"trickle-resistor-ohms:0\",\n \t\t\t\t\t<&abx80x>,\"abracon,tc-resistor:0\",\n \t\t\t\t\t<&rv3028>,\"trickle-resistor-ohms:0\",\n-\t\t\t\t\t<&rv1805>,\"abracon,tc-resistor:0\";\n+\t\t\t\t\t<&rv1805>,\"abracon,tc-resistor:0\",\n+\t\t\t\t\t<&bq32000>,\"abracon,tc-resistor:0\";\n \t\tbackup-switchover-mode = <&rv3028>,\"backup-switchover-mode:0\";\n \t\twakeup-source = <&ds1339>,\"wakeup-source?\",\n \t\t\t\t<&ds3231>,\"wakeup-source?\",\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0736-ARM-dts-Adapt-to-upstream-changes.patch",
    "content": "From e6942acef85ed8ce64d64147aa2328fbc67065c9 Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.com>\nDate: Tue, 27 Jul 2021 22:22:52 +0100\nSubject: [PATCH] ARM: dts: Adapt to upstream changes\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.com>\n---\n arch/arm/boot/dts/bcm2708-rpi-b-plus.dts   |  4 ++--\n arch/arm/boot/dts/bcm2708-rpi-b-rev1.dts   |  2 +-\n arch/arm/boot/dts/bcm2708-rpi-b.dts        |  2 +-\n arch/arm/boot/dts/bcm2708-rpi-cm.dtsi      |  2 +-\n arch/arm/boot/dts/bcm2708-rpi-zero-w.dts   |  2 +-\n arch/arm/boot/dts/bcm2708-rpi-zero.dts     |  2 +-\n arch/arm/boot/dts/bcm2709-rpi-2-b.dts      |  4 ++--\n arch/arm/boot/dts/bcm270x.dtsi             |  2 +-\n arch/arm/boot/dts/bcm2710-rpi-2-b.dts      |  4 ++--\n arch/arm/boot/dts/bcm2710-rpi-3-b-plus.dts |  4 ++--\n arch/arm/boot/dts/bcm2710-rpi-3-b.dts      |  4 ++--\n arch/arm/boot/dts/bcm2710-rpi-cm3.dts      |  2 +-\n arch/arm/boot/dts/bcm2711-rpi-4-b.dts      |  4 ++--\n arch/arm/boot/dts/bcm2711-rpi-400.dts      | 10 ++++++----\n arch/arm/boot/dts/bcm2711-rpi-cm4.dts      | 10 ++++++----\n 15 files changed, 31 insertions(+), 27 deletions(-)\n\n--- a/arch/arm/boot/dts/bcm2708-rpi-b-plus.dts\n+++ b/arch/arm/boot/dts/bcm2708-rpi-b-plus.dts\n@@ -90,13 +90,13 @@\n };\n \n &leds {\n-\tact_led: act {\n+\tact_led: led-act {\n \t\tlabel = \"led0\";\n \t\tlinux,default-trigger = \"mmc0\";\n \t\tgpios = <&gpio 47 0>;\n \t};\n \n-\tpwr_led: pwr {\n+\tpwr_led: led-pwr {\n \t\tlabel = \"led1\";\n \t\tlinux,default-trigger = \"input\";\n \t\tgpios = <&gpio 35 0>;\n--- a/arch/arm/boot/dts/bcm2708-rpi-b-rev1.dts\n+++ b/arch/arm/boot/dts/bcm2708-rpi-b-rev1.dts\n@@ -103,7 +103,7 @@ i2c_csi_dsi: &i2c1 {\n };\n \n &leds {\n-\tact_led: act {\n+\tact_led: led-act {\n \t\tlabel = \"led0\";\n \t\tlinux,default-trigger = \"mmc0\";\n \t\tgpios = <&gpio 16 1>;\n--- a/arch/arm/boot/dts/bcm2708-rpi-b.dts\n+++ b/arch/arm/boot/dts/bcm2708-rpi-b.dts\n@@ -90,7 +90,7 @@\n };\n \n &leds {\n-\tact_led: act {\n+\tact_led: led-act {\n \t\tlabel = \"led0\";\n \t\tlinux,default-trigger = \"mmc0\";\n \t\tgpios = <&gpio 16 1>;\n--- a/arch/arm/boot/dts/bcm2708-rpi-cm.dtsi\n+++ b/arch/arm/boot/dts/bcm2708-rpi-cm.dtsi\n@@ -2,7 +2,7 @@\n #include \"bcm2708-rpi.dtsi\"\n \n &leds {\n-\tact_led: act {\n+\tact_led: led-act {\n \t\tlabel = \"led0\";\n \t\tlinux,default-trigger = \"mmc0\";\n \t\tgpios = <&gpio 47 0>;\n--- a/arch/arm/boot/dts/bcm2708-rpi-zero-w.dts\n+++ b/arch/arm/boot/dts/bcm2708-rpi-zero-w.dts\n@@ -139,7 +139,7 @@\n };\n \n &leds {\n-\tact_led: act {\n+\tact_led: led-act {\n \t\tlabel = \"led0\";\n \t\tlinux,default-trigger = \"actpwr\";\n \t\tgpios = <&gpio 47 GPIO_ACTIVE_LOW>;\n--- a/arch/arm/boot/dts/bcm2708-rpi-zero.dts\n+++ b/arch/arm/boot/dts/bcm2708-rpi-zero.dts\n@@ -93,7 +93,7 @@\n };\n \n &leds {\n-\tact_led: act {\n+\tact_led: led-act {\n \t\tlabel = \"led0\";\n \t\tlinux,default-trigger = \"actpwr\";\n \t\tgpios = <&gpio 47 GPIO_ACTIVE_LOW>;\n--- a/arch/arm/boot/dts/bcm2709-rpi-2-b.dts\n+++ b/arch/arm/boot/dts/bcm2709-rpi-2-b.dts\n@@ -90,13 +90,13 @@\n };\n \n &leds {\n-\tact_led: act {\n+\tact_led: led-act {\n \t\tlabel = \"led0\";\n \t\tlinux,default-trigger = \"mmc0\";\n \t\tgpios = <&gpio 47 0>;\n \t};\n \n-\tpwr_led: pwr {\n+\tpwr_led: led-pwr {\n \t\tlabel = \"led1\";\n \t\tlinux,default-trigger = \"input\";\n \t\tgpios = <&gpio 35 0>;\n--- a/arch/arm/boot/dts/bcm270x.dtsi\n+++ b/arch/arm/boot/dts/bcm270x.dtsi\n@@ -33,7 +33,7 @@\n \t\t};\n #endif\n \n-\t\t/delete-node/ sdhci@7e300000;\n+\t\t/delete-node/ mmc@7e300000;\n \n \t\tsdhci: mmc: mmc@7e300000 {\n \t\t\tcompatible = \"brcm,bcm2835-mmc\", \"brcm,bcm2835-sdhci\";\n--- a/arch/arm/boot/dts/bcm2710-rpi-2-b.dts\n+++ b/arch/arm/boot/dts/bcm2710-rpi-2-b.dts\n@@ -90,13 +90,13 @@\n };\n \n &leds {\n-\tact_led: act {\n+\tact_led: led-act {\n \t\tlabel = \"led0\";\n \t\tlinux,default-trigger = \"mmc0\";\n \t\tgpios = <&gpio 47 0>;\n \t};\n \n-\tpwr_led: pwr {\n+\tpwr_led: led-pwr {\n \t\tlabel = \"led1\";\n \t\tlinux,default-trigger = \"input\";\n \t\tgpios = <&gpio 35 0>;\n--- a/arch/arm/boot/dts/bcm2710-rpi-3-b-plus.dts\n+++ b/arch/arm/boot/dts/bcm2710-rpi-3-b-plus.dts\n@@ -149,13 +149,13 @@\n };\n \n &leds {\n-\tact_led: act {\n+\tact_led: led-act {\n \t\tlabel = \"led0\";\n \t\tlinux,default-trigger = \"mmc0\";\n \t\tgpios = <&gpio 29 0>;\n \t};\n \n-\tpwr_led: pwr {\n+\tpwr_led: led-pwr {\n \t\tlabel = \"led1\";\n \t\tlinux,default-trigger = \"default-on\";\n \t\tgpios = <&expgpio 2 GPIO_ACTIVE_LOW>;\n--- a/arch/arm/boot/dts/bcm2710-rpi-3-b.dts\n+++ b/arch/arm/boot/dts/bcm2710-rpi-3-b.dts\n@@ -164,13 +164,13 @@\n };\n \n &leds {\n-\tact_led: act {\n+\tact_led: led-act {\n \t\tlabel = \"led0\";\n \t\tlinux,default-trigger = \"mmc0\";\n \t\tgpios = <&virtgpio 0 0>;\n \t};\n \n-\tpwr_led: pwr {\n+\tpwr_led: led-pwr {\n \t\tlabel = \"led1\";\n \t\tlinux,default-trigger = \"input\";\n \t\tgpios = <&expgpio 7 0>;\n--- a/arch/arm/boot/dts/bcm2710-rpi-cm3.dts\n+++ b/arch/arm/boot/dts/bcm2710-rpi-cm3.dts\n@@ -123,7 +123,7 @@\n };\n \n &leds {\n-\tact_led: act {\n+\tact_led: led-act {\n \t\tlabel = \"led0\";\n \t\tlinux,default-trigger = \"mmc0\";\n \t\tgpios = <&virtgpio 0 0>;\n--- a/arch/arm/boot/dts/bcm2711-rpi-4-b.dts\n+++ b/arch/arm/boot/dts/bcm2711-rpi-4-b.dts\n@@ -580,13 +580,13 @@\n };\n \n &leds {\n-\tact_led: act {\n+\tact_led: led-act {\n \t\tlabel = \"led0\";\n \t\tlinux,default-trigger = \"mmc0\";\n \t\tgpios = <&gpio 42 GPIO_ACTIVE_HIGH>;\n \t};\n \n-\tpwr_led: pwr {\n+\tpwr_led: led-pwr {\n \t\tlabel = \"led1\";\n \t\tlinux,default-trigger = \"default-on\";\n \t\tgpios = <&expgpio 2 GPIO_ACTIVE_LOW>;\n--- a/arch/arm/boot/dts/bcm2711-rpi-400.dts\n+++ b/arch/arm/boot/dts/bcm2711-rpi-400.dts\n@@ -28,11 +28,11 @@\n \t};\n \n \tleds {\n-\t\tact {\n+\t\tled-act {\n \t\t\tgpios = <&gpio 42 GPIO_ACTIVE_HIGH>;\n \t\t};\n \n-\t\tpwr {\n+\t\tled-pwr {\n \t\t\tlabel = \"PWR\";\n \t\t\tgpios = <&expgpio 2 GPIO_ACTIVE_LOW>;\n \t\t\tdefault-state = \"keep\";\n@@ -181,12 +181,14 @@\n &hdmi0 {\n \tclocks = <&firmware_clocks 13>, <&firmware_clocks 14>, <&dvp 0>, <&clk_27MHz>;\n \tclock-names = \"hdmi\", \"bvb\", \"audio\", \"cec\";\n+\twifi-2.4ghz-coexistence;\n \tstatus = \"okay\";\n };\n \n &hdmi1 {\n \tclocks = <&firmware_clocks 13>, <&firmware_clocks 14>, <&dvp 1>, <&clk_27MHz>;\n \tclock-names = \"hdmi\", \"bvb\", \"audio\", \"cec\";\n+\twifi-2.4ghz-coexistence;\n \tstatus = \"okay\";\n };\n \n@@ -586,14 +588,14 @@\n };\n \n &leds {\n-\tact_led: act {\n+\tact_led: led-act {\n \t\tlabel = \"led0\";\n \t\tlinux,default-trigger = \"default-on\";\n \t\tdefault-state = \"on\";\n \t\tgpios = <&gpio 42 GPIO_ACTIVE_HIGH>;\n \t};\n \n-\tpwr_led: pwr {\n+\tpwr_led: led-pwr {\n \t\tlabel = \"led1\";\n \t\tlinux,default-trigger = \"default-on\";\n \t\tgpios = <&expgpio 2 GPIO_ACTIVE_LOW>;\n--- a/arch/arm/boot/dts/bcm2711-rpi-cm4.dts\n+++ b/arch/arm/boot/dts/bcm2711-rpi-cm4.dts\n@@ -28,11 +28,11 @@\n \t};\n \n \tleds {\n-\t\tact {\n+\t\tled-act {\n \t\t\tgpios = <&gpio 42 GPIO_ACTIVE_HIGH>;\n \t\t};\n \n-\t\tpwr {\n+\t\tled-pwr {\n \t\t\tlabel = \"PWR\";\n \t\t\tgpios = <&expgpio 2 GPIO_ACTIVE_LOW>;\n \t\t\tdefault-state = \"keep\";\n@@ -193,12 +193,14 @@\n &hdmi0 {\n \tclocks = <&firmware_clocks 13>, <&firmware_clocks 14>, <&dvp 0>, <&clk_27MHz>;\n \tclock-names = \"hdmi\", \"bvb\", \"audio\", \"cec\";\n+\twifi-2.4ghz-coexistence;\n \tstatus = \"okay\";\n };\n \n &hdmi1 {\n \tclocks = <&firmware_clocks 13>, <&firmware_clocks 14>, <&dvp 1>, <&clk_27MHz>;\n \tclock-names = \"hdmi\", \"bvb\", \"audio\", \"cec\";\n+\twifi-2.4ghz-coexistence;\n \tstatus = \"okay\";\n };\n \n@@ -597,13 +599,13 @@\n };\n \n &leds {\n-\tact_led: act {\n+\tact_led: led-act {\n \t\tlabel = \"led0\";\n \t\tlinux,default-trigger = \"mmc0\";\n \t\tgpios = <&gpio 42 GPIO_ACTIVE_HIGH>;\n \t};\n \n-\tpwr_led: pwr {\n+\tpwr_led: led-pwr {\n \t\tlabel = \"led1\";\n \t\tlinux,default-trigger = \"default-on\";\n \t\tgpios = <&expgpio 2 GPIO_ACTIVE_LOW>;\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0737-overlays-rpi-poe-plus-Improve-the-cooling-levels.patch",
    "content": "From 2a30b8254d34a2656d798931f46af157afd152c0 Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.com>\nDate: Wed, 18 Aug 2021 17:26:49 +0100\nSubject: [PATCH] overlays: rpi-poe-plus: Improve the cooling levels\n\nThe PoE HAT cooling levels are not well suited for the PoE+ HAT - the\nfan fails to come on until the temperature reaches the third trip point\n(50C).\n\nGive the rpi-poe-plus overlay a different set of cooling levels -\n0 32 64 128 255, as suggested by @chris-kai-in.\n\nSee: https://github.com/raspberrypi/firmware/issues/1607\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.com>\n---\n arch/arm/boot/dts/overlays/rpi-poe-plus-overlay.dts | 4 ++++\n 1 file changed, 4 insertions(+)\n\n--- a/arch/arm/boot/dts/overlays/rpi-poe-plus-overlay.dts\n+++ b/arch/arm/boot/dts/overlays/rpi-poe-plus-overlay.dts\n@@ -17,3 +17,7 @@\n \t\t};\n \t};\n };\n+\n+&fan0 {\n+\tcooling-levels = <0 32 64 128 255>;\n+};\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/950-0738-Makefiles-dt-Always-set-on-ARCH_BCM2835.patch",
    "content": "From 72d78ec8b6898976ea46b1c0cb9780707985cd80 Mon Sep 17 00:00:00 2001\nFrom: Phil Elwell <phil@raspberrypi.com>\nDate: Thu, 19 Aug 2021 14:28:56 +0100\nSubject: [PATCH] Makefiles: dt: Always set '-@' on ARCH_BCM2835\n\nOn the BCM2835 architecture, always add the '-@' option to enable the\ngeneration of symbols, rather than relying on DTC_FLAGS being empty\nor correct.\n\nSee: https://github.com/raspberrypi/linux/issues/3846\n\nSigned-off-by: Phil Elwell <phil@raspberrypi.com>\n---\n arch/arm/boot/dts/Makefile            | 2 +-\n arch/arm64/boot/dts/broadcom/Makefile | 2 +-\n 2 files changed, 2 insertions(+), 2 deletions(-)\n\n--- a/arch/arm/boot/dts/Makefile\n+++ b/arch/arm/boot/dts/Makefile\n@@ -1433,5 +1433,5 @@ subdir-y\t:= overlays\n \n # Enable fixups to support overlays on BCM2835 platforms\n ifeq ($(CONFIG_ARCH_BCM2835),y)\n-\tDTC_FLAGS ?= -@\n+\tDTC_FLAGS += -@\n endif\n--- a/arch/arm64/boot/dts/broadcom/Makefile\n+++ b/arch/arm64/boot/dts/broadcom/Makefile\n@@ -16,5 +16,5 @@ subdir-y\t+= stingray\n \n # Enable fixups to support overlays on BCM2835 platforms\n ifeq ($(CONFIG_ARCH_BCM2835),y)\n-\tDTC_FLAGS ?= -@\n+\tDTC_FLAGS += -@\n endif\n"
  },
  {
    "path": "target/linux/bcm27xx/patches-5.10/960-hwrng-iproc-set-quality-to-1000.patch",
    "content": "From d3e5e7f3a4e6f61e8c380b9a610212267ee72dbd Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com>\nDate: Sat, 20 Feb 2021 19:24:50 +0100\nSubject: [PATCH] hwrng: iproc: set quality to 1000\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nThis allows khwrngd to make use of iproc-rng200.\n\nSigned-off-by: Álvaro Fernández Rojas <noltari@gmail.com>\n---\n drivers/char/hw_random/iproc-rng200.c | 1 +\n 1 file changed, 1 insertion(+)\n\n--- a/drivers/char/hw_random/iproc-rng200.c\n+++ b/drivers/char/hw_random/iproc-rng200.c\n@@ -263,6 +263,7 @@ static int iproc_rng200_probe(struct pla\n \n \tpriv->rng.name = pdev->name;\n \tpriv->rng.cleanup = iproc_rng200_cleanup;\n+\tpriv->rng.quality = 1000;\n \n \tif (of_device_is_compatible(dev->of_node, \"brcm,bcm2711-rng200\")) {\n \t\tpriv->rng.init = bcm2711_rng200_init;\n"
  },
  {
    "path": "target/linux/bcm47xx/Makefile",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2006-2008 OpenWrt.org\n\ninclude $(TOPDIR)/rules.mk\n\nARCH:=mipsel\nBOARD:=bcm47xx\nBOARDNAME:=Broadcom BCM47xx/53xx (MIPS)\nFEATURES:=squashfs usb\nSUBTARGETS:=generic mips74k legacy\n\nKERNEL_PATCHVER:=5.10\n\ndefine Target/Description\n\tBuild firmware images for Broadcom based BCM47xx/53xx routers with MIPS CPU, *not* ARM.\nendef\n\ninclude $(INCLUDE_DIR)/target.mk\n\nDEFAULT_PACKAGES += swconfig nvram otrx \\\n\tkmod-leds-gpio kmod-gpio-button-hotplug\n\n$(eval $(call BuildTarget))\n"
  },
  {
    "path": "target/linux/bcm47xx/base-files/etc/board.d/01_network",
    "content": "# Copyright (C) 2006-2015 OpenWrt.org\n\n. /lib/functions/system.sh\n. /lib/functions/uci-defaults.sh\n\nconfigure_by_vlanports() {\n\tlocal vlan0ports=\"$(nvram get vlan0ports)\"\n\tlocal vlan1ports=\"$(nvram get vlan1ports)\"\n\tlocal vlan2ports=\"$(nvram get vlan2ports)\"\n\tlocal cpuport=\"$(swconfig dev switch0 help 2>/dev/null | sed -ne \"s|.*cpu @ \\([0-9]*\\).*|\\1|p\")\"\n\n\tif [ \"${vlan0ports:0:9}\" = \"0 1 2 3 8\" -a \"${vlan1ports:0:3}\" = \"4 8\" -a ${cpuport:-0} -eq 8 ] || \\\n\t   [ \"${vlan1ports:0:9}\" = \"0 1 2 3 8\" -a \"${vlan2ports:0:3}\" = \"4 8\" -a ${cpuport:-0} -eq 8 ] || \\\n\t   [ \"${vlan2ports:0:9}\" = \"0 1 2 3 8\" -a \"${vlan1ports:0:3}\" = \"4 8\" -a ${cpuport:-0} -eq 8 ];\n\tthen\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0:lan\" \"1:lan\" \"2:lan\" \"3:lan\" \"4:wan\" \"8@eth0\"\n\n\telif [ \"${vlan0ports:0:9}\" = \"1 2 3 4 8\" -a \"${vlan1ports:0:3}\" = \"0 8\" -a ${cpuport:-0} -eq 8 ] || \\\n\t     [ \"${vlan1ports:0:9}\" = \"1 2 3 4 8\" -a \"${vlan2ports:0:3}\" = \"0 8\" -a ${cpuport:-0} -eq 8 ] || \\\n\t     [ \"${vlan2ports:0:9}\" = \"1 2 3 4 8\" -a \"${vlan1ports:0:3}\" = \"0 8\" -a ${cpuport:-0} -eq 8 ];\n\tthen\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"1:lan\" \"2:lan\" \"3:lan\" \"4:lan\" \"0:wan\" \"8@eth0\"\n\n\telif [ \"${vlan0ports:0:9}\" = \"0 1 2 3 5\" -a \"${vlan1ports:0:3}\" = \"4 5\" -a ${cpuport:-0} -eq 5 ] || \\\n\t\t [ \"${vlan1ports:0:9}\" = \"0 1 2 3 5\" -a \"${vlan2ports:0:3}\" = \"4 5\" -a ${cpuport:-0} -eq 5 ] || \\\n\t\t [ \"${vlan2ports:0:9}\" = \"0 1 2 3 5\" -a \"${vlan1ports:0:3}\" = \"4 5\" -a ${cpuport:-0} -eq 5 ];\n\tthen\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0:lan\" \"1:lan\" \"2:lan\" \"3:lan\" \"4:wan\" \"5@eth0\"\n\n\telif [ \"${vlan0ports:0:9}\" = \"1 2 3 4 5\" -a \"${vlan1ports:0:3}\" = \"0 5\" -a ${cpuport:-0} -eq 5 ] || \\\n\t     [ \"${vlan1ports:0:9}\" = \"1 2 3 4 5\" -a \"${vlan2ports:0:3}\" = \"0 5\" -a ${cpuport:-0} -eq 5 ] || \\\n\t     [ \"${vlan2ports:0:9}\" = \"1 2 3 4 5\" -a \"${vlan1ports:0:3}\" = \"0 5\" -a ${cpuport:-0} -eq 5 ];\n\tthen\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"1:lan\" \"2:lan\" \"3:lan\" \"4:lan\" \"0:wan\" \"5@eth0\"\n\n\telse\n\t\tlogger -t \"01_network\" \"Unable to determine network configuration\"\n\t\tucidef_set_interface_lan \"eth0\"\n\tfi\n}\n\nconfigure_by_boardnum() {\n\tlocal boardnum=\"$1\"\n\n\tcase \"$boardnum\" in\n\t# WAP54G, Sitecom WL-105b\n\t\"2\" | \\\n\t\"1024\")\n\t\tucidef_set_interface_lan \"eth0\"\n\t\t;;\n\n\t# Generic detection fallback\n\t*)\n\t\tconfigure_by_vlanports\n\t\t;;\n\tesac\n}\n\nconfigure_by_boardtype() {\n\tlocal boardtype=\"$1\"\n\tlocal boardnum=\"$2\"\n\n\tcase \"$boardtype\" in\n\t\"bcm94710r4\")\n\t\tucidef_set_interfaces_lan_wan \"eth0\" \"eth1\"\n\t\t;;\n\n\t\"0x0467\")\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0:lan\" \"1:lan\" \"2:lan\" \"3:lan\" \"4:wan\" \"5@eth0\"\n\t\t;;\n\n\t\"0x042f\" | \\\n\t\"0x0472\")\n\t\t# WL-500gP\n\t\tif [ \"$boardnum\" = \"45\" ]; then\n\t\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\t\"0:wan\" \"1:lan\" \"2:lan\" \"3:lan\" \"4:lan\" \"5@eth0\"\n\n\t\t# Generic BCM94704\n\t\telse\n\t\t\tucidef_set_interface_wan \"eth1\"\n\t\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\t\"0:lan\" \"1:lan\" \"2:lan\" \"3:lan\" \"4:lan\" \"5@eth0\"\n\n\t\t\t# MAC addresses on 4704 tend to be screwed up. Add a workaround here\n\t\t\tlocal mac=\"$(nvram get et0macaddr)\"\n\t\t\tlocal pat=\"[0-9a-fA-F][0-9a-fA-F]:[0-9a-fA-F][0-9a-fA-F]\"\n\t\t\t\t  pat=\"$pat:[0-9a-fA-F][0-9a-fA-F]:[0-9a-fA-F][0-9a-fA-F]\"\n\t\t\t\t  pat=\"$pat:[0-9a-fA-F][0-9a-fA-F]:[0-9a-fA-F][0-9a-fA-F]\"\n\n\t\t\tcase \"$mac\" in\n\t\t\t$pat)\n\t\t\t\tucidef_set_interface_macaddr \"lan\" \"$mac\"\n\t\t\t\tucidef_set_interface_macaddr \"wan\" \"$(macaddr_add \"$mac\" 1)\"\n\t\t\t\t;;\n\t\t\tesac\n\t\tfi\n\t\t;;\n\n\t# Buffalo WBR-B11 and Buffalo WBR-G54\n\t\"bcm94710ap\")\n\t\tucidef_set_interface_wan \"eth1\"\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0:lan\" \"1:lan\" \"2:lan\" \"3:lan\" \"4:lan\" \"5@eth0\"\n\t\t;;\n\n\t*)\n\t\tconfigure_by_boardnum \"$boardnum\"\n\t\t;;\n\tesac\n}\n\nconfigure_by_model() {\n\tlocal model=\"$1\"\n\tlocal boardtype=\"$2\"\n\tlocal boardnum=\"$3\"\n\n\t# Netgear WGT634U exception\n\tif grep -sqE 'mtd0: 000(6|a)0000' /proc/mtd; then\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0:lan\" \"1:lan\" \"2:lan\" \"3:lan\" \"4:wan\" \"5@eth0\"\n\t\treturn\n\tfi\n\n\tcase \"$model\" in\n\t\"Asus WLHDD\" | \\\n\t\"Asus WL300G\")\n\t\tucidef_set_interface_lan \"eth1\"\n\t\t;;\n\n\t\"Asus WL330GE\")\n\t\tucidef_add_switch \"switch0\" \"4:lan\" \"5t@eth0\"\n\t\t;;\n\n\t\"Asus WL500G\" | \\\n\t\"Microsoft MN-700\")\n\t\tucidef_set_interfaces_lan_wan \"eth0\" \"eth1\"\n\t\t;;\n\n\t\"Asus WL500GP V2\")\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0:lan:4\" \"1:lan:3\" \"2:lan:2\" \"3:lan:1\" \"4:wan\" \"5@eth0\"\n\t\t;;\n\n\t\"Asus RT-N12\"* | \\\n\t\"Buffalo WHR-G125\" | \\\n\t\"D-Link DIR-330\" | \\\n\t\"Motorola WR850G\" | \\\n\t\"Siemens SE505 V2\")\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0:lan\" \"1:lan\" \"2:lan\" \"3:lan\" \"4:wan\" \"5@eth0\"\n\t\t;;\n\n\t\"Asus WL700\")\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0:wan\" \"1:lan\" \"2:lan\" \"3:lan\" \"4:lan\" \"5@eth0\"\n\t\t;;\n\n\t\"Asus WL500W\" | \\\n\t\"Dell TrueMobile 2300\")\n\t\tucidef_set_interface_wan \"eth1\"\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0:lan\" \"1:lan\" \"2:lan\" \"3:lan\" \"5@eth0\"\n\t\t;;\n\n\t\"Asus RT-N16\"* | \\\n\t\"Linksys E3000 V1\" | \\\n\t\"Linksys WRT610N V2\" | \\\n\t\"Netgear WNR3500 V2\" | \\\n\t\"Netgear WNR3500L\")\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0:wan\" \"1:lan:4\" \"2:lan:3\" \"3:lan:2\" \"4:lan:1\" \"8@eth0\"\n\t\t;;\n\n\t\"Netgear R6200 V1\")\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0:lan:4\" \"1:lan:3\" \"2:lan:2\" \"3:lan:1\" \"4:wan\" \"8@eth0\"\n\t\t;;\n\n\t\"Netgear WN2500RP V1\")\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0:lan:4\" \"1:lan:3\" \"2:lan:2\" \"3:lan:1\" \"5@eth0\"\n\t\t;;\n\n\t*)\n\t\tconfigure_by_boardtype \"$boardtype\" \"$boardnum\"\n\t\t;;\n\tesac\n}\n\n\nmodel=\"$(cat /tmp/sysinfo/model)\"\nboardtype=\"$(board_name)\"\n\ncase \"$boardtype\" in\n\t*:*)\n\t\tboardnum=\"${boardtype##*:}\"\n\t\tboardtype=\"${boardtype%:*}\"\n\t;;\nesac\n\nboard_config_update\n\nconfigure_by_model \"$model\" \"$boardtype\" \"$boardnum\"\n\nboard_config_flush\n"
  },
  {
    "path": "target/linux/bcm47xx/base-files/etc/diag.sh",
    "content": "#!/bin/sh\n# Copyright (C) 2006 OpenWrt.org\n\n. /lib/functions/leds.sh\n\nget_status_led() {\n\tfor led in dmz power diag wps; do\n\t\tstatus_led_file=$(find /sys/class/leds/ -name \"*${led}*\" | head -n1)\n\t\tif [ ! -f $status_led_file ]; then\n\t\t\tstatus_led=$(basename $status_led_file)\n\t\t\treturn\n\t\tfi;\n\tdone\n}\n\nset_state() {\n\tget_status_led\n\n\tcase \"$1\" in\n\tpreinit)\n\t\tstatus_led_blink_preinit\n\t\t;;\n\tfailsafe)\n\t\tstatus_led_blink_failsafe\n\t\t;;\n\tpreinit_regular)\n\t\tstatus_led_blink_preinit_regular\n\t\t;;\n\tdone)\n\t\tstatus_led_on\n\t\t;;\n\tesac\n}\n"
  },
  {
    "path": "target/linux/bcm47xx/base-files/etc/init.d/wmacfixup",
    "content": "#!/bin/sh /etc/rc.common\n# Copyright (C) 2010 OpenWrt.org\n\nSTART=41\n\nboot() {\n\t[ -d /sys/class/ieee80211 ] || exit\n\n\tcommit=0\n\n\tfixup_wmac() {\n\t\tlocal cfg=\"$1\"\n\t\tlocal cfmac\n\n\t\tconfig_get cfmac \"$cfg\" macaddr\n\n\t\t[ \"$cfmac\" != \"00:90:4c:5f:00:2a\" ] || {\n\t\t\tlocal nvmac=\"$(nvram get il0macaddr 2>/dev/null)\"\n\t\t\t[ -n \"$nvmac\" ] && [ \"$nvmac != \"$cfmac ] && {\n\t\t\t\tuci set wireless.$cfg.macaddr=\"$nvmac\"\n\t\t\t\tcommit=1\n\t\t\t}\n\t\t}\n\t}\n\n\tconfig_load wireless\n\tconfig_foreach fixup_wmac wifi-device\n\n\t[ \"$commit\" = 1 ] && uci commit wireless\n}\n\nstart() { :; }\nstop()  { :; }\n"
  },
  {
    "path": "target/linux/bcm47xx/base-files/etc/uci-defaults/03_network_migration",
    "content": "#\n# Copyright (C) 2014-2015 OpenWrt.org\n#\n\nuci show network | grep \"\\.vlan=0\"\n[ $? -ne 0 ] && exit 0\n\nlogger -t network \"network config is invalid, creating new one\"\n\nlan_proto=\"$(uci -q get network.lan.proto)\"\nlan_ipaddr=\"$(uci -q get network.lan.ipaddr)\"\nlan_netmask=\"$(uci -q get network.lan.netmask)\"\nwan_proto=\"$(uci -q get network.wan.proto)\"\nwan_ipaddr=\"$(uci -q get network.wan.ipaddr)\"\nwan_netmask=\"$(uci -q get network.wan.netmask)\"\n\necho \"\" > /etc/config/network\nconfig_generate\n\nuci set network.lan.proto=$lan_proto\nuci set network.lan.ipaddr=$lan_ipaddr\nuci set network.lan.netmask=$lan_netmask\nuci set network.wan.proto=$wan_proto\nuci set network.wan.ipaddr=$wan_ipaddr\nuci set network.wan.netmask=$wan_netmask\nuci commit network\n\nexit 0\n"
  },
  {
    "path": "target/linux/bcm47xx/base-files/etc/uci-defaults/09_fix_crc",
    "content": "#\n# Copyright (C) 2007 OpenWrt.org\n#\n\nmtd fixtrx firmware\n"
  },
  {
    "path": "target/linux/bcm47xx/base-files/lib/preinit/01_sysinfo",
    "content": "do_sysinfo_bcm47xx() {\n\tlocal boardtype=\"$(nvram get boardtype)\"\n\tlocal boardnum=\"$(nvram get boardnum)\"\n\tlocal model=\"$(sed -ne 's/^machine[ \\t]*: //p' /proc/cpuinfo)\"\n\n\t[ -z \"$model\" ] && model=\"unknown\"\n\t[ -z \"$boardtype\" ] && boardtype=\"unknown\"\n\n\t[ -e \"/tmp/sysinfo/\" ] || mkdir -p \"/tmp/sysinfo/\"\n\techo \"$boardtype${boardnum:+:$boardnum}\" > /tmp/sysinfo/board_name\n\techo \"$model\" > /tmp/sysinfo/model\n}\n\nboot_hook_add preinit_main do_sysinfo_bcm47xx\n"
  },
  {
    "path": "target/linux/bcm47xx/base-files/lib/upgrade/platform.sh",
    "content": "PART_NAME=firmware\n\nLXL_FLAGS_VENDOR_LUXUL=0x00000001\n\n# $(1): file to read magic from\n# $(2): offset in bytes\nget_magic_long_at() {\n\tdd if=\"$1\" skip=$2 bs=1 count=4 2>/dev/null | hexdump -v -n 4 -e '1/1 \"%02x\"'\n}\n\n# $(1): file to read LE long number from\n# $(2): offset in bytes\nget_le_long_at() {\n\techo $((0x$(dd if=\"$1\" skip=$2 bs=1 count=4 2>/dev/null | hexdump -v -e '1/4 \"%02x\"')))\n}\n\nplatform_expected_image() {\n\tlocal model=\"$(cat /tmp/sysinfo/model)\"\n\n\tcase \"$model\" in\n\t\t\"Netgear R6200 V1\")\techo \"chk U12H192T00_NETGEAR\"; return;;\n\t\t\"Netgear WGR614 V8\")\techo \"chk U12H072T00_NETGEAR\"; return;;\n\t\t\"Netgear WGR614 V9\")\techo \"chk U12H094T00_NETGEAR\"; return;;\n\t\t\"Netgear WGR614 V10\")\techo \"chk U12H139T01_NETGEAR\"; return;;\n\t\t\"Netgear WN2500RP V1\")\techo \"chk U12H197T00_NETGEAR\"; return;;\n\t\t\"Netgear WN2500RP V2\")\techo \"chk U12H294T00_NETGEAR\"; return;;\n\t\t\"Netgear WNDR3300\")\techo \"chk U12H093T00_NETGEAR\"; return;;\n\t\t\"Netgear WNDR3400 V1\")\techo \"chk U12H155T00_NETGEAR\"; return;;\n\t\t\"Netgear WNDR3400 V2\")\techo \"chk U12H187T00_NETGEAR\"; return;;\n\t\t\"Netgear WNDR3400 V3\")\techo \"chk U12H208T00_NETGEAR\"; return;;\n\t\t\"Netgear WNDR3400 Vcna\")\techo \"chk U12H155T01_NETGEAR\"; return;;\n\t\t\"Netgear WNDR3700 V3\")\techo \"chk U12H194T00_NETGEAR\"; return;;\n\t\t\"Netgear WNDR4000\")\techo \"chk U12H181T00_NETGEAR\"; return;;\n\t\t\"Netgear WNDR4500 V1\")\techo \"chk U12H189T00_NETGEAR\"; return;;\n\t\t\"Netgear WNDR4500 V2\")\techo \"chk U12H224T00_NETGEAR\"; return;;\n\t\t\"Netgear WNR2000 V2\")\techo \"chk U12H114T00_NETGEAR\"; return;;\n\t\t\"Netgear WNR3500L\")\techo \"chk U12H136T99_NETGEAR\"; return;;\n\t\t\"Netgear WNR3500U\")\techo \"chk U12H136T00_NETGEAR\"; return;;\n\t\t\"Netgear WNR3500 V2\")\techo \"chk U12H127T00_NETGEAR\"; return;;\n\t\t\"Netgear WNR3500 V2vc\")\techo \"chk U12H127T70_NETGEAR\"; return;;\n\t\t\"Netgear WNR834B V2\")\techo \"chk U12H081T00_NETGEAR\"; return;;\n\t\t\"Linksys E900 V1\")\techo \"cybertan E900\"; return;;\n\t\t\"Linksys E1000 V1\")\techo \"cybertan E100\"; return;;\n\t\t\"Linksys E1000 V2\")\techo \"cybertan E100\"; return;;\n\t\t\"Linksys E1000 V2.1\")\techo \"cybertan E100\"; return;;\n\t\t\"Linksys E1200 V2\")\techo \"cybertan E122\"; return;;\n\t\t\"Linksys E2000 V1\")\techo \"cybertan 32XN\"; return;;\n\t\t\"Linksys E3000 V1\")\techo \"cybertan 61XN\"; return;;\n\t\t\"Linksys E3200 V1\")\techo \"cybertan 3200\"; return;;\n\t\t\"Linksys E4200 V1\")\techo \"cybertan 4200\"; return;;\n\t\t\"Linksys WRT150N V1.1\")\techo \"cybertan N150\"; return;;\n\t\t\"Linksys WRT150N V1\")\techo \"cybertan N150\"; return;;\n\t\t\"Linksys WRT160N V1\")\techo \"cybertan N150\"; return;;\n\t\t\"Linksys WRT160N V3\")\techo \"cybertan N150\"; return;;\n\t\t\"Linksys WRT300N V1\")\techo \"cybertan EWCB\"; return;;\n\t\t\"Linksys WRT300N V1.1\")\techo \"cybertan EWC2\"; return;;\n\t\t\"Linksys WRT310N V1\")\techo \"cybertan 310N\"; return;;\n\t\t\"Linksys WRT310N V2\")\techo \"cybertan 310N\"; return;;\n\t\t\"Linksys WRT610N V1\")\techo \"cybertan 610N\"; return;;\n\t\t\"Linksys WRT610N V2\")\techo \"cybertan 610N\"; return;;\n\t\t\"Luxul XAP-310 V1\")\techo \"lxl XAP-310\"; return;;\n\t\t\"Luxul XAP-1210 V1\")\techo \"lxl XAP-1210\"; return;;\n\t\t\"Luxul XAP-1230 V1\")\techo \"lxl XAP-1230\"; return;;\n\t\t\"Luxul XAP-1240 V1\")\techo \"lxl XAP-1240\"; return;;\n\t\t\"Luxul XAP-1500 V1\")\techo \"lxl XAP-1500\"; return;;\n\t\t\"Luxul ABR-4400 V1\")\techo \"lxl ABR-4400\"; return;;\n\t\t\"Luxul XBR-4400 V1\")\techo \"lxl XBR-4400\"; return;;\n\t\t\"Luxul XVW-P30 V1\")\techo \"lxl XVW-P30\"; return;;\n\t\t\"Luxul XWR-600 V1\")\techo \"lxl XWR-600\"; return;;\n\t\t\"Luxul XWR-1750 V1\")\techo \"lxl XWR-1750\"; return;;\n\tesac\n}\n\nbcm47xx_identify() {\n\tlocal magic\n\n\tmagic=$(get_magic_long \"$1\")\n\tcase \"$magic\" in\n\t\t\"48445230\")\n\t\t\techo \"trx\"\n\t\t\treturn\n\t\t\t;;\n\t\t\"2a23245e\")\n\t\t\techo \"chk\"\n\t\t\treturn\n\t\t\t;;\n\t\t\"4c584c23\")\n\t\t\techo \"lxl\"\n\t\t\treturn\n\t\t\t;;\n\tesac\n\n\tmagic=$(get_magic_long_at \"$1\" 14)\n\t[ \"$magic\" = \"55324e44\" ] && {\n\t\techo \"cybertan\"\n\t\treturn\n\t}\n\n\tmagic=$(get_magic_long_at \"$1\" 60)\n\t[ \"$magic\" = \"4c584c23\" ] && {\n\t\techo \"lxlold\"\n\t\treturn\n\t}\n\n\techo \"unknown\"\n}\n\nplatform_check_image() {\n\t[ \"$#\" -gt 1 ] && return 1\n\n\tlocal file_type=$(bcm47xx_identify \"$1\")\n\tlocal magic\n\tlocal error=0\n\n\tcase \"$file_type\" in\n\t\t\"chk\")\n\t\t\tlocal header_len=$((0x$(get_magic_long_at \"$1\" 4)))\n\t\t\tlocal board_id_len=$(($header_len - 40))\n\t\t\tlocal board_id=$(dd if=\"$1\" skip=40 bs=1 count=$board_id_len 2>/dev/null | hexdump -v -e '1/1 \"%c\"')\n\t\t\tlocal dev_board_id=$(platform_expected_image)\n\t\t\techo \"Found CHK image with device board_id $board_id\"\n\n\t\t\t[ -n \"$dev_board_id\" -a \"chk $board_id\" != \"$dev_board_id\" ] && {\n\t\t\t\techo \"Firmware board_id doesn't match device board_id ($dev_board_id)\"\n\t\t\t\terror=1\n\t\t\t}\n\n\t\t\tif ! otrx check \"$1\" -o \"$header_len\"; then\n\t\t\t\techo \"No valid TRX firmware in the CHK image\"\n\t\t\t\tnotify_firmware_test_result \"trx_valid\" 0\n\t\t\t\terror=1\n\t\t\telse\n\t\t\t\tnotify_firmware_test_result \"trx_valid\" 1\n\t\t\tfi\n\t\t;;\n\t\t\"cybertan\")\n\t\t\tlocal pattern=$(dd if=\"$1\" bs=1 count=4 2>/dev/null | hexdump -v -e '1/1 \"%c\"')\n\t\t\tlocal dev_pattern=$(platform_expected_image)\n\t\t\techo \"Found CyberTAN image with device pattern: $pattern\"\n\n\t\t\t[ -n \"$dev_pattern\" -a \"cybertan $pattern\" != \"$dev_pattern\" ] && {\n\t\t\t\techo \"Firmware pattern doesn't match device pattern ($dev_pattern)\"\n\t\t\t\terror=1\n\t\t\t}\n\n\t\t\tif ! otrx check \"$1\" -o 32; then\n\t\t\t\techo \"No valid TRX firmware in the CyberTAN image\"\n\t\t\t\tnotify_firmware_test_result \"trx_valid\" 0\n\t\t\t\terror=1\n\t\t\telse\n\t\t\t\tnotify_firmware_test_result \"trx_valid\" 1\n\t\t\tfi\n\t\t;;\n\t\t\"lxl\")\n\t\t\tlocal hdr_len=$(get_le_long_at \"$1\" 8)\n\t\t\tlocal flags=$(get_le_long_at \"$1\" 12)\n\t\t\tlocal board=$(dd if=\"$1\" skip=16 bs=1 count=16 2>/dev/null | hexdump -v -e '1/1 \"%c\"')\n\t\t\tlocal dev_board=$(platform_expected_image)\n\t\t\techo \"Found Luxul image for board $board\"\n\n\t\t\t[ -n \"$dev_board\" -a \"lxl $board\" != \"$dev_board\" ] && {\n\t\t\t\techo \"Firmware ($board) doesn't match device ($dev_board)\"\n\t\t\t\terror=1\n\t\t\t}\n\n\t\t\t[ $((flags & LXL_FLAGS_VENDOR_LUXUL)) -gt 0 ] && notify_firmware_no_backup\n\n\t\t\tif ! otrx check \"$1\" -o \"$hdr_len\"; then\n\t\t\t\techo \"No valid TRX firmware in the Luxul image\"\n\t\t\t\tnotify_firmware_test_result \"trx_valid\" 0\n\t\t\t\terror=1\n\t\t\telse\n\t\t\t\tnotify_firmware_test_result \"trx_valid\" 1\n\t\t\tfi\n\t\t;;\n\t\t\"lxlold\")\n\t\t\tlocal board_id=$(dd if=\"$1\" skip=48 bs=1 count=12 2>/dev/null | hexdump -v -e '1/1 \"%c\"')\n\t\t\tlocal dev_board_id=$(platform_expected_image)\n\t\t\techo \"Found Luxul image with device board_id $board_id\"\n\n\t\t\t[ -n \"$dev_board_id\" -a \"lxl $board_id\" != \"$dev_board_id\" ] && {\n\t\t\t\techo \"Firmware board_id doesn't match device board_id ($dev_board_id)\"\n\t\t\t\terror=1\n\t\t\t}\n\n\t\t\tnotify_firmware_no_backup\n\n\t\t\tif ! otrx check \"$1\" -o 64; then\n\t\t\t\techo \"No valid TRX firmware in the Luxul image\"\n\t\t\t\tnotify_firmware_test_result \"trx_valid\" 0\n\t\t\t\terror=1\n\t\t\telse\n\t\t\t\tnotify_firmware_test_result \"trx_valid\" 1\n\t\t\tfi\n\t\t;;\n\t\t\"trx\")\n\t\t\tif ! otrx check \"$1\"; then\n\t\t\t\techo \"Invalid (corrupted?) TRX firmware\"\n\t\t\t\tnotify_firmware_test_result \"trx_valid\" 0\n\t\t\t\terror=1\n\t\t\telse\n\t\t\t\tnotify_firmware_test_result \"trx_valid\" 1\n\t\t\tfi\n\t\t;;\n\t\t*)\n\t\t\techo \"Invalid image type. Please use firmware specific for this device.\"\n\t\t\tnotify_firmware_broken\n\t\t\terror=1\n\t\t;;\n\tesac\n\n\treturn $error\n}\n\nplatform_trx_from_chk_cmd() {\n\tlocal header_len=$((0x$(get_magic_long_at \"$1\" 4)))\n\n\techo -n dd bs=$header_len skip=1\n}\n\nplatform_trx_from_cybertan_cmd() {\n\techo -n dd bs=32 skip=1\n}\n\nplatform_trx_from_lxl_cmd() {\n\tlocal hdr_len=$(get_le_long_at \"$1\" 8)\n\n\techo -n dd skip=$hdr_len iflag=skip_bytes\n}\n\nplatform_trx_from_lxlold_cmd() {\n\techo -n dd bs=64 skip=1\n}\n\nplatform_do_upgrade() {\n\tlocal file_type=$(bcm47xx_identify \"$1\")\n\tlocal trx=\"$1\"\n\tlocal cmd=\"\"\n\n\tcase \"$file_type\" in\n\t\t\"chk\")\t\tcmd=$(platform_trx_from_chk_cmd \"$trx\");;\n\t\t\"cybertan\")\tcmd=$(platform_trx_from_cybertan_cmd \"$trx\");;\n\t\t\"lxl\")\t\tcmd=$(platform_trx_from_lxl_cmd \"$trx\");;\n\t\t\"lxlold\")\tcmd=$(platform_trx_from_lxlold_cmd \"$trx\");;\n\tesac\n\n\tdefault_do_upgrade \"$trx\" \"$cmd\"\n}\n"
  },
  {
    "path": "target/linux/bcm47xx/config-5.10",
    "content": "CONFIG_ADM6996_PHY=y\nCONFIG_ARCH_BINFMT_ELF_STATE=y\nCONFIG_ARCH_CLOCKSOURCE_DATA=y\nCONFIG_ARCH_DISCARD_MEMBLOCK=y\nCONFIG_ARCH_HAS_ELF_RANDOMIZE=y\nCONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y\nCONFIG_ARCH_HIBERNATION_POSSIBLE=y\nCONFIG_ARCH_MMAP_RND_BITS_MAX=15\nCONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15\nCONFIG_ARCH_SUPPORTS_UPROBES=y\nCONFIG_ARCH_SUSPEND_POSSIBLE=y\nCONFIG_ARCH_USE_BUILTIN_BSWAP=y\nCONFIG_ARCH_USE_QUEUED_RWLOCKS=y\nCONFIG_ARCH_USE_QUEUED_SPINLOCKS=y\nCONFIG_ARCH_WANT_IPC_PARSE_VERSION=y\nCONFIG_BCM47XX=y\nCONFIG_BCM47XX_BCMA=y\nCONFIG_BCM47XX_NVRAM=y\nCONFIG_BCM47XX_SPROM=y\nCONFIG_BCM47XX_SSB=y\nCONFIG_BCM47XX_WDT=y\nCONFIG_BCMA=y\nCONFIG_BCMA_BLOCKIO=y\nCONFIG_BCMA_DEBUG=y\nCONFIG_BCMA_DRIVER_GMAC_CMN=y\nCONFIG_BCMA_DRIVER_GPIO=y\nCONFIG_BCMA_DRIVER_MIPS=y\nCONFIG_BCMA_DRIVER_PCI=y\nCONFIG_BCMA_DRIVER_PCI_HOSTMODE=y\nCONFIG_BCMA_HOST_PCI=y\nCONFIG_BCMA_HOST_PCI_POSSIBLE=y\nCONFIG_BCMA_HOST_SOC=y\nCONFIG_BCMA_NFLASH=y\nCONFIG_BCMA_PFLASH=y\nCONFIG_BCMA_SFLASH=y\n# CONFIG_BGMAC_BCMA is not set\nCONFIG_BLK_MQ_PCI=y\nCONFIG_CEVT_R4K=y\nCONFIG_CLONE_BACKWARDS=y\nCONFIG_CMDLINE=\"noinitrd console=ttyS0,115200\"\nCONFIG_CMDLINE_BOOL=y\n# CONFIG_CMDLINE_OVERRIDE is not set\n# CONFIG_COMMON_CLK is not set\nCONFIG_COMPAT_32BIT_TIME=y\n# CONFIG_CPU_BMIPS is not set\nCONFIG_CPU_GENERIC_DUMP_TLB=y\nCONFIG_CPU_HAS_PREFETCH=y\nCONFIG_CPU_HAS_SYNC=y\nCONFIG_CPU_LITTLE_ENDIAN=y\nCONFIG_CPU_MIPS32=y\nCONFIG_CPU_MIPS32_R1=y\n# CONFIG_CPU_MIPS32_R2 is not set\nCONFIG_CPU_MIPSR1=y\nCONFIG_CPU_MIPSR2_IRQ_VI=y\nCONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y\nCONFIG_CPU_R4K_CACHE_TLB=y\nCONFIG_CPU_R4K_FPU=y\nCONFIG_CPU_SUPPORTS_32BIT_KERNEL=y\nCONFIG_CPU_SUPPORTS_HIGHMEM=y\nCONFIG_CRYPTO_RNG2=y\nCONFIG_CRYPTO_WORKQUEUE=y\nCONFIG_CSRC_R4K=y\nCONFIG_DMA_DIRECT_OPS=y\nCONFIG_DMA_NONCOHERENT=y\nCONFIG_DMA_NONCOHERENT_CACHE_SYNC=y\nCONFIG_DMA_NONCOHERENT_MMAP=y\nCONFIG_DMA_NONCOHERENT_OPS=y\n# CONFIG_EARLY_PRINTK is not set\nCONFIG_FIXED_PHY=y\nCONFIG_GENERIC_ATOMIC64=y\nCONFIG_GENERIC_CLOCKEVENTS=y\nCONFIG_GENERIC_CMOS_UPDATE=y\nCONFIG_GENERIC_CPU_AUTOPROBE=y\nCONFIG_GENERIC_IRQ_CHIP=y\nCONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y\nCONFIG_GENERIC_IRQ_SHOW=y\nCONFIG_GENERIC_LIB_ASHLDI3=y\nCONFIG_GENERIC_LIB_ASHRDI3=y\nCONFIG_GENERIC_LIB_CMPDI2=y\nCONFIG_GENERIC_LIB_LSHRDI3=y\nCONFIG_GENERIC_LIB_UCMPDI2=y\nCONFIG_GENERIC_PCI_IOMAP=y\nCONFIG_GENERIC_SCHED_CLOCK=y\nCONFIG_GENERIC_SMP_IDLE_THREAD=y\nCONFIG_GENERIC_TIME_VSYSCALL=y\nCONFIG_GPIOLIB=y\nCONFIG_GPIOLIB_IRQCHIP=y\nCONFIG_GPIO_WDT=y\nCONFIG_HANDLE_DOMAIN_IRQ=y\nCONFIG_HARDWARE_WATCHPOINTS=y\nCONFIG_HAS_DMA=y\nCONFIG_HAS_IOMEM=y\nCONFIG_HAS_IOPORT_MAP=y\nCONFIG_HAVE_ARCH_COMPILER_H=y\nCONFIG_HAVE_ARCH_JUMP_LABEL=y\nCONFIG_HAVE_ARCH_KGDB=y\nCONFIG_HAVE_ARCH_SECCOMP_FILTER=y\nCONFIG_HAVE_ARCH_TRACEHOOK=y\nCONFIG_HAVE_CBPF_JIT=y\nCONFIG_HAVE_CONTEXT_TRACKING=y\nCONFIG_HAVE_COPY_THREAD_TLS=y\nCONFIG_HAVE_C_RECORDMCOUNT=y\nCONFIG_HAVE_DEBUG_KMEMLEAK=y\nCONFIG_HAVE_DEBUG_STACKOVERFLOW=y\nCONFIG_HAVE_DMA_CONTIGUOUS=y\nCONFIG_HAVE_DYNAMIC_FTRACE=y\nCONFIG_HAVE_FTRACE_MCOUNT_RECORD=y\nCONFIG_HAVE_FUNCTION_GRAPH_TRACER=y\nCONFIG_HAVE_FUNCTION_TRACER=y\nCONFIG_HAVE_GENERIC_DMA_COHERENT=y\nCONFIG_HAVE_IDE=y\nCONFIG_HAVE_IRQ_EXIT_ON_IRQ_STACK=y\nCONFIG_HAVE_IRQ_TIME_ACCOUNTING=y\nCONFIG_HAVE_LATENCYTOP_SUPPORT=y\nCONFIG_HAVE_LD_DEAD_CODE_DATA_ELIMINATION=y\nCONFIG_HAVE_MEMBLOCK=y\nCONFIG_HAVE_MEMBLOCK_NODE_MAP=y\nCONFIG_HAVE_MOD_ARCH_SPECIFIC=y\nCONFIG_HAVE_NET_DSA=y\nCONFIG_HAVE_OPROFILE=y\nCONFIG_HAVE_PERF_EVENTS=y\nCONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y\nCONFIG_HAVE_RSEQ=y\nCONFIG_HAVE_SYSCALL_TRACEPOINTS=y\nCONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y\nCONFIG_HW_HAS_PCI=y\nCONFIG_HW_RANDOM=y\nCONFIG_HZ_PERIODIC=y\nCONFIG_INITRAMFS_SOURCE=\"\"\nCONFIG_IRQ_DOMAIN=y\nCONFIG_IRQ_FORCED_THREADING=y\nCONFIG_IRQ_MIPS_CPU=y\nCONFIG_IRQ_WORK=y\nCONFIG_LEDS_GPIO_REGISTER=y\nCONFIG_LOCK_DEBUGGING_SUPPORT=y\nCONFIG_MDIO_BUS=y\nCONFIG_MDIO_DEVICE=y\nCONFIG_MEMFD_CREATE=y\nCONFIG_MIGRATION=y\nCONFIG_MIPS=y\nCONFIG_MIPS_ASID_BITS=8\nCONFIG_MIPS_ASID_SHIFT=0\nCONFIG_MIPS_CLOCK_VSYSCALL=y\n# CONFIG_MIPS_CMDLINE_BUILTIN_EXTEND is not set\nCONFIG_MIPS_CMDLINE_FROM_BOOTLOADER=y\nCONFIG_MIPS_L1_CACHE_SHIFT=5\nCONFIG_MODULES_USE_ELF_REL=y\nCONFIG_MTD_BCM47XXSFLASH=y\nCONFIG_MTD_BCM47XX_PARTS=y\nCONFIG_MTD_NAND=y\nCONFIG_MTD_NAND_BCM47XXNFLASH=y\nCONFIG_MTD_NAND_ECC=y\nCONFIG_MTD_PARSER_TRX=y\nCONFIG_MTD_PHYSMAP=y\nCONFIG_NEED_DMA_MAP_STATE=y\nCONFIG_NEED_PER_CPU_KM=y\nCONFIG_NO_EXCEPT_FILL=y\nCONFIG_NO_GENERIC_PCI_IOPORT_MAP=y\n# CONFIG_OF is not set\nCONFIG_PCI=y\nCONFIG_PCI_DISABLE_COMMON_QUIRKS=y\nCONFIG_PCI_DOMAINS=y\nCONFIG_PCI_DRIVERS_LEGACY=y\nCONFIG_PERF_USE_VMALLOC=y\nCONFIG_PGTABLE_LEVELS=2\nCONFIG_PHYLIB=y\nCONFIG_SERIAL_8250_EXTENDED=y\nCONFIG_SERIAL_8250_SHARE_IRQ=y\nCONFIG_SRCU=y\nCONFIG_SSB=y\nCONFIG_SSB_B43_PCI_BRIDGE=y\nCONFIG_SSB_BLOCKIO=y\nCONFIG_SSB_DRIVER_EXTIF=y\nCONFIG_SSB_DRIVER_GIGE=y\nCONFIG_SSB_DRIVER_GPIO=y\nCONFIG_SSB_DRIVER_MIPS=y\nCONFIG_SSB_DRIVER_PCICORE=y\nCONFIG_SSB_DRIVER_PCICORE_POSSIBLE=y\nCONFIG_SSB_EMBEDDED=y\nCONFIG_SSB_HOST_SOC=y\nCONFIG_SSB_PCICORE_HOSTMODE=y\nCONFIG_SSB_PCIHOST=y\nCONFIG_SSB_PCIHOST_POSSIBLE=y\nCONFIG_SSB_SERIAL=y\nCONFIG_SSB_SFLASH=y\nCONFIG_SSB_SPROM=y\nCONFIG_SWCONFIG=y\nCONFIG_SWCONFIG_B53=y\n# CONFIG_SWCONFIG_B53_MMAP_DRIVER is not set\nCONFIG_SWCONFIG_B53_PHY_DRIVER=y\nCONFIG_SWCONFIG_B53_PHY_FIXUP=y\n# CONFIG_SWCONFIG_B53_SRAB_DRIVER is not set\nCONFIG_SWPHY=y\nCONFIG_SYSCTL_EXCEPTION_TRACE=y\nCONFIG_SYS_HAS_CPU_BMIPS=y\nCONFIG_SYS_HAS_CPU_BMIPS32_3300=y\nCONFIG_SYS_HAS_CPU_MIPS32_R1=y\nCONFIG_SYS_HAS_CPU_MIPS32_R2=y\nCONFIG_SYS_HAS_EARLY_PRINTK=y\nCONFIG_SYS_SUPPORTS_32BIT_KERNEL=y\nCONFIG_SYS_SUPPORTS_ARBIT_HZ=y\nCONFIG_SYS_SUPPORTS_HIGHMEM=y\nCONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y\nCONFIG_SYS_SUPPORTS_MIPS16=y\nCONFIG_SYS_SUPPORTS_ZBOOT=y\nCONFIG_TICK_CPU_ACCOUNTING=y\nCONFIG_TINY_SRCU=y\nCONFIG_USB_SUPPORT=y\nCONFIG_USE_GENERIC_EARLY_PRINTK_8250=y\nCONFIG_WATCHDOG_CORE=y\n"
  },
  {
    "path": "target/linux/bcm47xx/generic/profiles/100-Broadcom-b43.mk",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2007-2013 OpenWrt.org\n\ndefine Profile/Broadcom-b43\n  NAME:=Broadcom SoC, all Ethernet, BCM43xx WiFi (b43, default)\n  PACKAGES:=kmod-b44 kmod-tg3 kmod-bgmac kmod-b43 kmod-b43legacy\nendef\n\ndefine Profile/Broadcom-b43/Description\n\tPackage set compatible with hardware any Broadcom BCM47xx or BCM535x\n\tSoC with Broadcom BCM43xx Wifi cards using the mac80211, b43 and\n\tb43legacy drivers and b44, tg3 or bgmac Ethernet driver.\nendef\n\n$(eval $(call Profile,Broadcom-b43))\n\n"
  },
  {
    "path": "target/linux/bcm47xx/generic/profiles/101-Broadcom-wl.mk",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2010-2013 OpenWrt.org\n\ndefine Profile/Broadcom-wl\n  NAME:=Broadcom SoC, all Ethernet, BCM43xx WiFi (wl, proprietary)\n  PACKAGES:=-wpad-basic-wolfssl kmod-b44 kmod-tg3 kmod-bgmac kmod-brcm-wl wlc nas\nendef\n\ndefine Profile/Broadcom-wl/Description\n\tPackage set compatible with hardware any Broadcom BCM47xx or BCM535x\n\tSoC with Broadcom BCM43xx Wifi cards using the proprietary Broadcom\n\twireless \"wl\" driver and b44, tg3 or bgmac Ethernet driver.\nendef\n\n$(eval $(call Profile,Broadcom-wl))\n\n"
  },
  {
    "path": "target/linux/bcm47xx/generic/profiles/104-Broadcom-ath5k.mk",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2006-2013 OpenWrt.org\n\ndefine Profile/Broadcom-ath5k\n  NAME:=Broadcom SoC, all Ethernet, Atheros WiFi (ath5k)\n  PACKAGES:=kmod-b44 kmod-tg3 kmod-bgmac kmod-ath5k\nendef\n\ndefine Profile/Broadcom-ath5k/Description\n\tPackage set compatible with hardware any Broadcom BCM47xx or BCM535x\n\tSoC with Atheros Wifi cards using the mac80211 and ath5k drivers and\n\tb44, tg3 or bgmac Ethernet driver.\nendef\n$(eval $(call Profile,Broadcom-ath5k))\n\n"
  },
  {
    "path": "target/linux/bcm47xx/generic/profiles/105-Broadcom-none.mk",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2006-2013 OpenWrt.org\n\ndefine Profile/Broadcom-none\n  NAME:=Broadcom SoC, all Ethernet, No WiFi\n  PACKAGES:=-wpad-basic-wolfssl kmod-b44 kmod-tg3 kmod-bgmac\nendef\n\ndefine Profile/Broadcom-none/Description\n\tPackage set compatible with hardware any Broadcom BCM47xx or BCM535x\n\tSoC without any Wifi cards and b44, tg3 or bgmac Ethernet driver.\nendef\n$(eval $(call Profile,Broadcom-none))\n\n"
  },
  {
    "path": "target/linux/bcm47xx/generic/profiles/200-Broadcom-b44-b43.mk",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2007-2013 OpenWrt.org\n\ndefine Profile/Broadcom-b44-b43\n  NAME:=Broadcom SoC, b44 Ethernet, BCM43xx WiFi (b43, default)\n  PACKAGES:=kmod-b44 kmod-b43 kmod-b43legacy\nendef\n\ndefine Profile/Broadcom-b44-b43/Description\n\tPackage set compatible with hardware older Broadcom BCM47xx or BCM535x\n\tSoC with Broadcom BCM43xx Wifi cards using the mac80211, b43 and\n\tb43legacy drivers and b44 Ethernet driver.\nendef\n\n$(eval $(call Profile,Broadcom-b44-b43))\n\n"
  },
  {
    "path": "target/linux/bcm47xx/generic/profiles/201-Broadcom-b44-wl.mk",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2010-2013 OpenWrt.org\n\ndefine Profile/Broadcom-b44-wl\n  NAME:=Broadcom SoC, b44 Ethernet, BCM43xx WiFi (wl, proprietary)\n  PACKAGES:=-wpad-basic-wolfssl kmod-b44 kmod-brcm-wl wlc nas\nendef\n\ndefine Profile/Broadcom-b44-wl/Description\n\tPackage set compatible with hardware older Broadcom BCM47xx or BCM535x\n\tSoC with Broadcom BCM43xx Wifi cards using the proprietary Broadcom\n\twireless \"wl\" driver and b44 Ethernet driver.\nendef\n\n$(eval $(call Profile,Broadcom-b44-wl))\n\n"
  },
  {
    "path": "target/linux/bcm47xx/generic/profiles/204-Broadcom-b44-ath5k.mk",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2006-2013 OpenWrt.org\n\ndefine Profile/Broadcom-b44-ath5k\n  NAME:=Broadcom SoC, b44 Ethernet, Atheros WiFi (ath5k)\n  PACKAGES:=kmod-b44 kmod-ath5k\nendef\n\ndefine Profile/Broadcom-b44-ath5k/Description\n\tPackage set compatible with hardware older Broadcom BCM47xx or BCM535x\n\tSoC with Atheros Wifi cards using the mac80211 and ath5k drivers and\n\tb44 Ethernet driver.\nendef\n$(eval $(call Profile,Broadcom-b44-ath5k))\n\n"
  },
  {
    "path": "target/linux/bcm47xx/generic/profiles/205-Broadcom-b44-none.mk",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2006-2013 OpenWrt.org\n\ndefine Profile/Broadcom-b44-none\n  NAME:=Broadcom SoC, b44 Ethernet, No WiFi\n  PACKAGES:=-wpad-basic-wolfssl kmod-b44\nendef\n\ndefine Profile/Broadcom-b44-none/Description\n\tPackage set compatible with hardware older Broadcom BCM47xx or BCM535x\n\tSoC without any Wifi cards and b44 Ethernet driver.\nendef\n$(eval $(call Profile,Broadcom-b44-none))\n\n"
  },
  {
    "path": "target/linux/bcm47xx/generic/profiles/210-Broadcom-tg3-b43.mk",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2007-2013 OpenWrt.org\n\ndefine Profile/Broadcom-tg3-b43\n  NAME:=Broadcom SoC, tg3 Ethernet, BCM43xx WiFi (b43)\n  PACKAGES:=kmod-b43 kmod-tg3\nendef\n\ndefine Profile/Broadcom-tg3-b43/Description\n\tPackage set compatible with hardware Broadcom BCM4705/BCM4785\n\tSoCs with Broadcom BCM43xx Wifi cards using the mac80211 and b43\n\tdriver and tg3 Ethernet driver.\nendef\n\n$(eval $(call Profile,Broadcom-tg3-b43))\n\n"
  },
  {
    "path": "target/linux/bcm47xx/generic/profiles/211-Broadcom-tg3-wl.mk",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2010-2013 OpenWrt.org\n\ndefine Profile/Broadcom-tg3-wl\n  NAME:=Broadcom SoC, tg3 Ethernet, BCM43xx WiFi (wl, proprietary)\n  PACKAGES:=-wpad-basic-wolfssl kmod-brcm-wl wlc nas kmod-tg3\nendef\n\ndefine Profile/Broadcom-tg3-wl/Description\n\tPackage set compatible with hardware Broadcom BCM4705/BCM4785\n\tSoC with Broadcom BCM43xx Wifi cards using the proprietary Broadcom\n\twireless \"wl\" driver and tg3 Ethernet driver.\nendef\n\n$(eval $(call Profile,Broadcom-tg3-wl))\n\n"
  },
  {
    "path": "target/linux/bcm47xx/generic/profiles/215-Broadcom-tg3-none.mk",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2006-2013 OpenWrt.org\n\ndefine Profile/Broadcom-tg3-none\n  NAME:=Broadcom SoC, tg3 Ethernet, no WiFi\n  PACKAGES:=-wpad-basic-wolfssl kmod-tg3\nendef\n\ndefine Profile/Broadcom-tg3-none/Description\n\tPackage set compatible with hardware Broadcom BCM4705/BCM4785\n\tSoC without any Wifi cards and tg3 Ethernet driver.\nendef\n$(eval $(call Profile,Broadcom-tg3-none))\n\n"
  },
  {
    "path": "target/linux/bcm47xx/generic/profiles/220-Broadcom-bgmac-b43.mk",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2007-2013 OpenWrt.org\n\ndefine Profile/Broadcom-bgmac-b43\n  NAME:=Broadcom SoC, bgmac Ethernet, BCM43xx WiFi (b43)\n  PACKAGES:=kmod-bgmac kmod-b43\nendef\n\ndefine Profile/Broadcom-bgmac-b43/Description\n\tPackage set compatible with hardware newer Broadcom BCM47xx or BCM535x\n\tSoC with Broadcom BCM43xx Wifi cards using the mac80211 and b43\n\tdrivers and bgmac Ethernet driver.\nendef\n\n$(eval $(call Profile,Broadcom-bgmac-b43))\n\n"
  },
  {
    "path": "target/linux/bcm47xx/generic/profiles/221-Broadcom-bgmac-wl.mk",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2010-2013 OpenWrt.org\n\ndefine Profile/Broadcom-bgmac-wl\n  NAME:=Broadcom SoC, bgmac Ethernet, BCM43xx WiFi (wl, proprietary)\n  PACKAGES:=-wpad-basic-wolfssl kmod-bgmac kmod-brcm-wl wlc nas\nendef\n\ndefine Profile/Broadcom-bgmac-wl/Description\n\tPackage set compatible with hardware newer Broadcom BCM47xx or BCM535x\n\tSoC with Broadcom BCM43xx Wifi cards using the proprietary Broadcom\n\twireless \"wl\" driver and bgmac Ethernet driver.\nendef\n\n$(eval $(call Profile,Broadcom-bgmac-wl))\n\n"
  },
  {
    "path": "target/linux/bcm47xx/generic/profiles/225-Broadcom-bgmac-none.mk",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2006-2013 OpenWrt.org\n\ndefine Profile/Broadcom-bgmac-none\n  NAME:=Broadcom SoC, bgmac Ethernet, No WiFi\n  PACKAGES:=-wpad-basic-wolfssl kmod-bgmac\nendef\n\ndefine Profile/Broadcom-bgmac-none/Description\n\tPackage set compatible with hardware newer Broadcom BCM47xx or BCM535x\n\tSoC without any Wifi cards and bgmac Ethernet driver.\nendef\n$(eval $(call Profile,Broadcom-bgmac-none))\n\n"
  },
  {
    "path": "target/linux/bcm47xx/generic/profiles/226-Broadcom-bgmac-brcsmac.mk",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2007-2013 OpenWrt.org\n\ndefine Profile/Broadcom-bgmac-brcmsmac\n  NAME:=Broadcom SoC, bgmac Ethernet, BCM43xx WiFi (brcmsmac)\n  PACKAGES:=kmod-bgmac kmod-brcmsmac\nendef\n\ndefine Profile/Broadcom-bgmac-brcmsmac/Description\n\tPackage set compatable with newer gigabit + N based bcm47xx SoCs with\n\tBroadcom BCM43xx Wifi cards using the mac80211 brcmsmac driver and\n\tbgmac Ethernet driver.\nendef\n\n$(eval $(call Profile,Broadcom-bgmac-brcmsmac))\n\n"
  },
  {
    "path": "target/linux/bcm47xx/generic/profiles/PS-1208MFG.mk",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2007-2010 OpenWrt.org\n\ndefine Profile/Ps1208mfg\n  NAME:=Edimax PS-1208MFG\n  PACKAGES:=-firewall -dropbear -dnsmasq -mtd -ppp -wpad-basic-wolfssl kmod-b44 block-mount kmod-usb-storage kmod-usb2 kmod-usb-ohci -iptables -swconfig kmod-fs-ext4\nendef\n\ndefine Profile/Ps1208mfg/Description\n\tPackage set optimize for edimax PS-1208MFG printserver\nendef\n\n$(eval $(call Profile,Ps1208mfg))\n\n"
  },
  {
    "path": "target/linux/bcm47xx/generic/target.mk",
    "content": "BOARDNAME:=Generic\nFEATURES+=pcmcia\n\nDEFAULT_PACKAGES += wpad-basic-wolfssl\n\ndefine Target/Description\n\tBuild generic firmware for all Broadcom BCM47xx and BCM53xx MIPS\n\tdevices. It runs on both architectures BMIPS3300 and MIPS 74K.\nendef\n"
  },
  {
    "path": "target/linux/bcm47xx/image/Makefile",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2006-2016 OpenWrt.org\n\ninclude $(TOPDIR)/rules.mk\ninclude $(INCLUDE_DIR)/image.mk\n\nUSB1_PACKAGES := kmod-usb-ohci\nUSB2_PACKAGES := $(USB1_PACKAGES) kmod-usb2\n\ndefine Build/Clean\n\t$(MAKE) -C lzma-loader clean\nendef\n\ndefine Image/Prepare\n\t# Optimized LZMA compression (with dictionary), handled by lzma-loader.\n\tcat $(KDIR)/vmlinux | $(STAGING_DIR_HOST)/bin/lzma e -si -so -eos -lc1 -lp2 -pb2 > $(KDIR)/vmlinux.lzma\n\n\t# Less optimal LZMA compression (no dictionary), handled by CFE.\n\t$(STAGING_DIR_HOST)/bin/lzma e -so -d16 $(KDIR)/vmlinux > $(KDIR)/vmlinux-nodictionary.lzma\n\n\tgzip -nc9 $(KDIR)/vmlinux > $(KDIR)/vmlinux.gz\nifneq ($(CONFIG_TARGET_ROOTFS_INITRAMFS),)\n\tcat $(KDIR)/vmlinux-initramfs | $(STAGING_DIR_HOST)/bin/lzma e -si -so -eos -lc1 -lp2 -pb2 > $(KDIR)/vmlinux-initramfs.lzma\n\t$(STAGING_DIR_HOST)/bin/lzma e -so -d16 $(KDIR)/vmlinux-initramfs > $(KDIR)/vmlinux-initramfs-nodictionary.lzma\nendif\n\trm -f $(KDIR)/loader.gz\n\t$(MAKE) -C lzma-loader \\\n\t\tBUILD_DIR=\"$(KDIR)\" \\\n\t\tTARGET=\"$(KDIR)\" \\\n\t\tclean install\n\techo -ne \"\\\\x00\" >> $(KDIR)/loader.gz\n\trm -f $(KDIR)/fs_mark\n\techo -ne '\\xde\\xad\\xc0\\xde' > $(KDIR)/fs_mark\n\t$(call prepare_generic_squashfs,$(KDIR)/fs_mark)\nendef\n\ndefine trxalign/jffs2-128k\n-a 0x20000 -f $(KDIR)/root.$(1)\nendef\ndefine trxalign/jffs2-64k\n-a 0x10000 -f $(KDIR)/root.$(1)\nendef\ndefine trxalign/squashfs\n-a 1024 -f $(1) $(if $(2),-f $(2)) -a 0x10000 -A $(KDIR)/fs_mark\nendef\n\n#################################################\n# Images\n#################################################\n\ndefine Build/trx-with-loader\n\t$(STAGING_DIR_HOST)/bin/trx \\\n\t\t-m 33554432 \\\n\t\t-o $@.new \\\n\t\t-f $(KDIR)/loader.gz \\\n\t\t-f $(IMAGE_KERNEL) \\\n\t\t$(call trxalign/$(FILESYSTEM),$@)\n\tmv $@.new $@\nendef\n\ndefine Build/trx-v2-with-loader\n\t$(STAGING_DIR_HOST)/bin/trx \\\n\t\t-2 \\\n\t\t-m 33554432 \\\n\t\t-o $@.new \\\n\t\t-f $(KDIR)/loader.gz \\\n\t\t-f $(KDIR)/vmlinux.lzma \\\n\t\t$(call trxalign/$(FILESYSTEM),$@,$@.pattern)\n\tmv $@.new $@\nendef\n\ndefine Build/trx-without-loader\n\t$(STAGING_DIR_HOST)/bin/trx \\\n\t\t-m 33554432 \\\n\t\t-o $@.new \\\n\t\t-f $(IMAGE_KERNEL) \\\n\t\t$(call trxalign/$(FILESYSTEM),$@)\n\tmv $@.new $@\nendef\n\ndefine Build/asus-trx\n\t$(STAGING_DIR_HOST)/bin/asustrx -p $(PRODUCTID) -i $@ -o $@.new\n\tmv $@.new $@\nendef\n\ndefine Build/edimax-bin\n\t$(STAGING_DIR_HOST)/bin/trx2edips $@ $@.new\n\tmv $@.new $@\nendef\n\ndefine Build/huawei-bin\n\tdd if=/dev/zero of=$@.new bs=92 count=1\n\techo -ne 'HDR0\\x08\\x00\\x00\\x00' >> $@.new\n\tcat $@ >> $@.new\n\tmv $@.new $@\nendef\n\ndefine Build/linksys-bin\n\t$(STAGING_DIR_HOST)/bin/addpattern -4 -p $(DEVICE_ID) -v v$(VERSION) $(if $(SERIAL),-s $(SERIAL)) -i $@ -o $@.new\n\tmv $@.new $@\nendef\n\ndefine Build/linksys-pattern-partition\n\t$(STAGING_DIR_HOST)/bin/addpattern -5 -p $(DEVICE_ID) -v v$(VERSION) $(if $(SERIAL),-s $(SERIAL)) -i /dev/null -o $@.pattern\nendef\n\ndefine Build/motorola-bin\n\t$(STAGING_DIR_HOST)/bin/motorola-bin -$(MOTOROLA_DEVICE) $@ $@.new\n\tmv $@.new $@\nendef\n\ndefine Build/prepend-with-elf\n\tmv $@ $@.old\n\tdd if=$(KDIR)/loader.elf of=$@ bs=131072 conv=sync\n\tcat $@.old >> $@\nendef\n\ndefine Build/tailed-bin\n\techo $(BIN_TAIL) >> $@\nendef\n\ndefine Build/usrobotics-bin\n\t$(STAGING_DIR_HOST)/bin/trx2usr $@ $@.new\n\tmv $@.new $@\nendef\n\n#################################################\n# Devices\n#################################################\n\nDEVICE_VARS += PRODUCTID\nDEVICE_VARS += DEVICE_ID VERSION SERIAL\nDEVICE_VARS += NETGEAR_BOARD_ID NETGEAR_REGION\nDEVICE_VARS += MOTOROLA_DEVICE\nDEVICE_VARS += BIN_TAIL\n\ndefine Device/Default\n\tKERNEL := kernel-bin\n\tDEVICE_IMG_NAME = $$(DEVICE_IMG_PREFIX)-$$(1).$$(2)\n\tKERNEL_NAME = vmlinux.lzma\n\tKERNEL_INITRAMFS_NAME = vmlinux-initramfs.lzma\n\tFILESYSTEMS := $(FS_64K)\n\tIMAGES := trx\n\tIMAGE/trx := append-rootfs | trx-with-loader\nendef\n\ndefine Device/standard\n  DEVICE_VENDOR := Generic\n  DEVICE_MODEL := Image with LZMA loader and LZMA compressed kernel\nendef\n\ndefine Device/standard-noloader-gz\n  DEVICE_VENDOR := Generic\n  DEVICE_MODEL := Image with gzipped kernel\n  KERNEL_NAME = vmlinux.gz\n  IMAGE/trx := append-rootfs | trx-without-loader\nendef\n\ndefine Device/standard-noloader-nodictionarylzma\n  DEVICE_VENDOR := Generic\n  DEVICE_MODEL := Image with LZMA compressed kernel matching CFE decompressor\n  KERNEL_NAME = vmlinux-nodictionary.lzma\n  IMAGE/trx := append-rootfs | trx-without-loader\nendef\n\ndefine Device/asus\n\tDEVICE_VENDOR := ASUS\n\tIMAGES := trx\n\tIMAGE/trx := append-rootfs | trx-with-loader | asus-trx\nendef\n\ndefine Device/linksys\n\tDEVICE_VENDOR := Linksys\n\tIMAGES := bin\n\tIMAGE/bin := append-rootfs | trx-with-loader | linksys-bin\nendef\n\ndefine Device/motorola\n\tDEVICE_VENDOR := Motorola\n\tIMAGES := bin\n\tIMAGE/bin := append-rootfs | trx-with-loader | motorola-bin\nendef\n\ndefine Device/netgear\n\tDEVICE_VENDOR := NETGEAR\n\tIMAGES := chk\n\tIMAGE/chk := append-rootfs | trx-with-loader | netgear-chk\nendef\n\n#################################################\n# Subtarget devices\n#################################################\n\ninclude $(SUBTARGET).mk\n\n#################################################\n# Shared BuildImage defines\n#################################################\n\ndefine Image/Build/Initramfs\n\t$(STAGING_DIR_HOST)/bin/trx \\\n\t\t-m 33554432 \\\n\t\t-o $(BIN_DIR)/$(IMG_PREFIX)-initramfs.trx \\\n\t\t-f $(KDIR)/loader.gz \\\n\t\t-f $(KDIR)/vmlinux-initramfs.lzma\n\t$(STAGING_DIR_HOST)/bin/trx \\\n\t\t-m 33554432 \\\n\t\t-o $(BIN_DIR)/$(IMG_PREFIX)-initramfs-noloader-nodictionary.trx \\\n\t\t-f $(KDIR)/vmlinux-initramfs-nodictionary.lzma\nendef\n\n# $(1): filesystem type.\ndefine Image/Build\n\t# TODO: Move it to Device/*\nifneq ($(CONFIG_TARGET_ROOTFS_INITRAMFS),)\n\t$(call Image/Build/Initramfs)\nendif\nendef\n\n$(eval $(call BuildImage))\n"
  },
  {
    "path": "target/linux/bcm47xx/image/generic.mk",
    "content": "#################################################\n# Subtarget generic\n#################################################\n\n  # BCM4705 with tg3\ndefine Device/linksys_wrt300n-v1.1\n  DEVICE_MODEL := WRT300N\n  DEVICE_VARIANT := v1.1\n  DEVICE_PACKAGES := kmod-tg3 kmod-b43\n  $(Device/linksys)\n  DEVICE_ID := EWC2\n  VERSION := 1.51.2\nendef\nTARGET_DEVICES += linksys_wrt300n-v1.1\n\ndefine Device/linksys_wrt310n-v1\n  DEVICE_MODEL := WRT310N\n  DEVICE_VARIANT := v1\n  DEVICE_PACKAGES := kmod-tg3 kmod-b43\n  $(Device/linksys)\n  DEVICE_ID := 310N\n  VERSION := 1.0.10\nendef\nTARGET_DEVICES += linksys_wrt310n-v1\n\ndefine Device/linksys_wrt350n-v1\n  DEVICE_MODEL := WRT350N\n  DEVICE_VARIANT := v1\n  DEVICE_PACKAGES := kmod-tg3 kmod-b43 $(USB2_PACKAGES)\n  $(Device/linksys)\n  DEVICE_ID := EWCG\n  VERSION := 1.04.1\nendef\nTARGET_DEVICES += linksys_wrt350n-v1\n\ndefine Device/linksys_wrt610n-v1\n  DEVICE_MODEL := WRT610N\n  DEVICE_VARIANT := v1\n  DEVICE_PACKAGES := kmod-tg3 kmod-b43 $(USB2_PACKAGES)\n  $(Device/linksys)\n  DEVICE_ID := 610N\n  VERSION := 1.0.1\nendef\nTARGET_DEVICES += linksys_wrt610n-v1\n\n  # BCMA SoC with SSB WiFi\ndefine Device/linksys_wrt610n-v2\n  DEVICE_MODEL := WRT610N\n  DEVICE_VARIANT := v2\n  DEVICE_PACKAGES := kmod-bgmac kmod-b43 $(USB2_PACKAGES)\n  $(Device/linksys)\n  DEVICE_ID := 610N\n  VERSION := 2.0.0\nendef\nTARGET_DEVICES += linksys_wrt610n-v2\n\ndefine Device/linksys_e3000-v1\n  DEVICE_MODEL := E3000\n  DEVICE_VARIANT := v1\n  DEVICE_PACKAGES := kmod-bgmac kmod-b43 $(USB2_PACKAGES)\n  $(Device/linksys)\n  DEVICE_ID := 61XN\n  VERSION := 1.0.3\nendef\nTARGET_DEVICES += linksys_e3000-v1\n\n# generic has Ethernet drivers as modules so overwrite standard image\ndefine Device/standard\n  DEVICE_VENDOR := Generic\n  DEVICE_MODEL := Image with LZMA loader and LZMA compressed kernel\n  DEVICE_PACKAGES := kmod-b44 kmod-bgmac kmod-tg3\nendef\nTARGET_DEVICES += standard\n"
  },
  {
    "path": "target/linux/bcm47xx/image/legacy.mk",
    "content": "#################################################\n# Subtarget legacy\n#################################################\n\ndefine Device/asus_wl-300g\n  DEVICE_MODEL := WL-300g\n  DEVICE_PACKAGES := kmod-b43 kmod-b43legacy\n  $(Device/asus)\n  PRODUCTID := \"WL300g      \"\nendef\nTARGET_DEVICES += asus_wl-300g\n\ndefine Device/asus_wl-320gp\n  DEVICE_MODEL := WL-320gP\n  DEVICE_PACKAGES := kmod-b43\n  $(Device/asus)\n  PRODUCTID := \"WL320gP     \"\nendef\nTARGET_DEVICES += asus_wl-320gp\n\ndefine Device/asus_wl-330ge\n  DEVICE_MODEL := WL-330gE\n  DEVICE_PACKAGES := kmod-b43\n  $(Device/asus)\n  PRODUCTID := \"WL-330gE    \"\nendef\nTARGET_DEVICES += asus_wl-330ge\n\ndefine Device/asus_wl-500gd\n  DEVICE_MODEL := WL-500g Deluxe\n  DEVICE_PACKAGES := kmod-b43 $(USB2_PACKAGES)\n  $(Device/asus)\n  PRODUCTID := \"WL500gx     \"\nendef\nTARGET_DEVICES += asus_wl-500gd\n\ndefine Device/asus_wl-500gp-v1\n  DEVICE_MODEL := WL-500gP\n  DEVICE_VARIANT := v1\n  DEVICE_PACKAGES := kmod-b43 $(USB2_PACKAGES)\n  $(Device/asus)\n  PRODUCTID := \"WL500gp     \"\nendef\nTARGET_DEVICES += asus_wl-500gp-v1\n\ndefine Device/asus_wl-500gp-v2\n  DEVICE_MODEL := WL-500gP\n  DEVICE_VARIANT := v2\n  DEVICE_PACKAGES := kmod-b43 $(USB2_PACKAGES)\n  $(Device/asus)\n  PRODUCTID := \"WL500gpv2   \"\nendef\nTARGET_DEVICES += asus_wl-500gp-v2\n\ndefine Device/asus_wl-500w\n  DEVICE_MODEL := WL-500W\n  DEVICE_PACKAGES := kmod-b43 kmod-usb-uhci kmod-usb2-pci\n  $(Device/asus)\n  PRODUCTID := \"WL500W      \"\nendef\nTARGET_DEVICES += asus_wl-500w\n\ndefine Device/asus_wl-520gu\n  DEVICE_MODEL := WL-520gU\n  DEVICE_PACKAGES := kmod-b43 $(USB2_PACKAGES)\n  $(Device/asus)\n  PRODUCTID := \"WL520gu     \"\nendef\nTARGET_DEVICES += asus_wl-520gu\n\ndefine Device/asus_wl-550ge\n  DEVICE_MODEL := WL-550gE\n  DEVICE_PACKAGES := kmod-b43\n  $(Device/asus)\n  PRODUCTID := \"WL550gE     \"\nendef\nTARGET_DEVICES += asus_wl-550ge\n\ndefine Device/asus_wl-hdd25\n  DEVICE_MODEL := WL-HDD25\n  DEVICE_PACKAGES := kmod-b43 kmod-b43legacy $(USB1_PACKAGES)\n  $(Device/asus)\n  PRODUCTID := \"WLHDD       \"\nendef\nTARGET_DEVICES += asus_wl-hdd25\n\ndefine Device/dlink_dwl-3150\n  DEVICE_VENDOR := D-Link\n  DEVICE_MODEL := DWL-3150\n  IMAGES := bin\n  IMAGE/bin := append-rootfs | trx-with-loader | tailed-bin\n  BIN_TAIL := BCM-5352-2050-0000000-01\nendef\nTARGET_DEVICES += dlink_dwl-3150\n\ndefine Device/edimax_ps1208-mfg\n  DEVICE_VENDOR := Edimax\n  DEVICE_MODEL := PS-1208MFg\n  DEVICE_PACKAGES := kmod-b43 $(USB2_PACKAGES)\n  IMAGES := bin\n  IMAGE/bin := append-rootfs | trx-with-loader | edimax-bin\nendef\nTARGET_DEVICES += edimax_ps1208-mfg\n\ndefine Device/huawei_e970\n  DEVICE_VENDOR := Huawei\n  DEVICE_MODEL := E970\n  DEVICE_PACKAGES := kmod-b43\n  KERNEL_NAME = vmlinux.gz\n  IMAGES := bin\n  IMAGE/bin := append-rootfs | trx-without-loader | huawei-bin\nendef\nTARGET_DEVICES += huawei_e970\n\ndefine Device/linksys_wrt54g3g\n  DEVICE_MODEL := WRT54G3G\n  DEVICE_PACKAGES := kmod-b43\n  $(Device/linksys)\n  DEVICE_ID := W54F\n  VERSION := 2.20.1\nendef\nTARGET_DEVICES += linksys_wrt54g3g\n\ndefine Device/linksys_wrt54g3g-em\n  DEVICE_MODEL := WRT54G3G-EM\n  $(Device/linksys)\n  DEVICE_ID := W3GN\n  VERSION := 2.20.1\nendef\nTARGET_DEVICES += linksys_wrt54g3g-em\n\ndefine Device/linksys_wrt54g3gv2-vf\n  DEVICE_VENDOR := Linksys\n  DEVICE_MODEL := WRT54G3GV2-VF\n  DEVICE_PACKAGES := kmod-b43 $(USB2_PACKAGES)\n  FILESYSTEMS := $(FS_128K)\n  IMAGES := noheader.bin bin\n  IMAGE/noheader.bin := linksys-pattern-partition | append-rootfs | trx-v2-with-loader\n  IMAGE/bin := linksys-pattern-partition | append-rootfs | trx-v2-with-loader | linksys-bin\n  DEVICE_ID := 3G2V\n  VERSION := 3.00.24\n  SERIAL := 6\nendef\nTARGET_DEVICES += linksys_wrt54g3gv2-vf\n\ndefine Device/linksys_wrt54g\n  DEVICE_MODEL := WRT54G\n  DEVICE_PACKAGES := kmod-b43 kmod-b43legacy\n  $(Device/linksys)\n  DEVICE_ID := W54G\n  VERSION := 4.71.1\nendef\nTARGET_DEVICES += linksys_wrt54g\n\ndefine Device/linksys_wrt54gs\n  DEVICE_MODEL := WRT54GS\n  DEVICE_VARIANT := v1/v2/v3\n  DEVICE_ALT0_VENDOR := Linksys\n  DEVICE_ALT0_MODEL := WRT54G-TM\n  DEVICE_ALT0_VARIANT := v1\n  DEVICE_PACKAGES := kmod-b43\n  $(Device/linksys)\n  FILESYSTEMS := $(FS_128K)\n  DEVICE_ID := W54S\n  VERSION := 4.80.1\nendef\nTARGET_DEVICES += linksys_wrt54gs\n\ndefine Device/linksys_wrt54gs-v4\n  DEVICE_MODEL := WRT54GS\n  DEVICE_VARIANT := v4\n  DEVICE_PACKAGES := kmod-b43\n  $(Device/linksys)\n  DEVICE_ID := W54s\n  VERSION := 1.09.1\nendef\nTARGET_DEVICES += linksys_wrt54gs-v4\n\ndefine Device/linksys_wrtsl54gs\n  DEVICE_MODEL := WRTSL54GS\n  DEVICE_PACKAGES := kmod-b43 $(USB2_PACKAGES)\n  $(Device/linksys)\n  FILESYSTEMS := $(FS_128K)\n  DEVICE_ID := W54U\n  VERSION := 2.08.1\nendef\nTARGET_DEVICES += linksys_wrtsl54gs\n\ndefine Device/linksys_wrt150n\n  DEVICE_MODEL := WRT150N\n  DEVICE_PACKAGES := kmod-b43\n  $(Device/linksys)\n  DEVICE_ID := N150\n  VERSION := 1.51.3\nendef\nTARGET_DEVICES += linksys_wrt150n\n\ndefine Device/linksys_wrt160n-v1\n  DEVICE_MODEL := WRT160N\n  DEVICE_VARIANT := v1\n  DEVICE_PACKAGES := kmod-b43\n  $(Device/linksys)\n  DEVICE_ID := N150\n  VERSION := 1.50.1\nendef\nTARGET_DEVICES += linksys_wrt160n-v1\n\ndefine Device/linksys_wrt300n-v1\n  DEVICE_MODEL := WRT300N\n  DEVICE_VARIANT := v1\n  DEVICE_PACKAGES := kmod-b43\n  $(Device/linksys)\n  IMAGES := bin trx\n  DEVICE_ID := EWCB\n  VERSION := 1.03.6\nendef\nTARGET_DEVICES += linksys_wrt300n-v1\n\ndefine Device/motorola_wa840g\n  DEVICE_MODEL := WA840G\n  DEVICE_PACKAGES := kmod-b43 kmod-b43legacy\n  $(Device/motorola)\n  MOTOROLA_DEVICE := 2\nendef\nTARGET_DEVICES += motorola_wa840g\n\ndefine Device/motorola_we800g\n  DEVICE_MODEL := WE800G\n  DEVICE_PACKAGES := kmod-b43 kmod-b43legacy\n  $(Device/motorola)\n  MOTOROLA_DEVICE := 3\nendef\nTARGET_DEVICES += motorola_we800g\n\ndefine Device/motorola_wr850g\n  DEVICE_MODEL := WR850G\n  DEVICE_PACKAGES := kmod-b43 kmod-b43legacy\n  $(Device/motorola)\n  MOTOROLA_DEVICE := 1\nendef\nTARGET_DEVICES += motorola_wr850g\n\ndefine Device/netgear_wgr614-v8\n  DEVICE_MODEL := WGR614\n  DEVICE_VARIANT := v8\n  DEVICE_PACKAGES := kmod-b43\n  $(Device/netgear)\n  NETGEAR_BOARD_ID := U12H072T00_NETGEAR\n  NETGEAR_REGION := 2\nendef\nTARGET_DEVICES += netgear_wgr614-v8\n\ndefine Device/netgear_wgt634u\n  DEVICE_VENDOR := NETGEAR\n  DEVICE_MODEL := WGT634U\n  DEVICE_PACKAGES := kmod-ath5k $(USB2_PACKAGES)\n  FILESYSTEMS := $(FS_128K)\n  IMAGES := bin\n  IMAGE/bin := append-rootfs | trx-with-loader | prepend-with-elf\nendef\nTARGET_DEVICES += netgear_wgt634u\n\ndefine Device/netgear_wndr3300-v1\n  DEVICE_MODEL := WNDR3300\n  DEVICE_VARIANT := v1\n  DEVICE_PACKAGES := kmod-b43\n  $(Device/netgear)\n  NETGEAR_BOARD_ID := U12H093T00_NETGEAR\n  NETGEAR_REGION := 2\nendef\nTARGET_DEVICES += netgear_wndr3300-v1\n\ndefine Device/netgear_wnr834b-v2\n  DEVICE_MODEL := WNR834B\n  DEVICE_VARIANT := v2\n  DEVICE_PACKAGES := kmod-b43\n  $(Device/netgear)\n  NETGEAR_BOARD_ID := U12H081T00_NETGEAR\n  NETGEAR_REGION := 2\nendef\nTARGET_DEVICES += netgear_wnr834b-v2\n\ndefine Device/usrobotics_usr5461\n  DEVICE_VENDOR := US Robotics\n  DEVICE_MODEL := USR5461\n  DEVICE_PACKAGES := kmod-b43 $(USB1_PACKAGES)\n  IMAGES := bin\n  IMAGE/bin := append-rootfs | trx-with-loader | usrobotics-bin\nendef\nTARGET_DEVICES += usrobotics_usr5461\n\nTARGET_DEVICES += standard standard-noloader-gz\n"
  },
  {
    "path": "target/linux/bcm47xx/image/lzma-loader/Makefile",
    "content": "# \n# Copyright (C) 2006 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME := lzma-loader\nPKG_BUILD_DIR := $(BUILD_DIR)/$(PKG_NAME)\n\n$(PKG_BUILD_DIR)/.prepared:\n\tmkdir $(PKG_BUILD_DIR)\n\t$(CP) ./src/* $(PKG_BUILD_DIR)/\n\ttouch $@\n\n$(PKG_BUILD_DIR)/loader.gz: $(PKG_BUILD_DIR)/.prepared\n\t$(MAKE) -C $(PKG_BUILD_DIR) CC=\"$(TARGET_CC)\" \\\n\t\tLD=\"$(TARGET_CROSS)ld\" CROSS_COMPILE=\"$(TARGET_CROSS)\"\n\ndownload: \nprepare: $(PKG_BUILD_DIR)/.prepared\ncompile: $(PKG_BUILD_DIR)/loader.gz\ninstall:\n\nifneq ($(TARGET),)\ninstall: compile\n\t$(CP) $(PKG_BUILD_DIR)/loader.gz $(PKG_BUILD_DIR)/loader.elf $(TARGET)/\nendif\n\nclean:\n\trm -rf $(PKG_BUILD_DIR)\n"
  },
  {
    "path": "target/linux/bcm47xx/image/lzma-loader/src/LzmaDecode.c",
    "content": "/*\n  LzmaDecode.c\n  LZMA Decoder\n  \n  LZMA SDK 4.05 Copyright (c) 1999-2004 Igor Pavlov (2004-08-25)\n  http://www.7-zip.org/\n\n  LZMA SDK is licensed under two licenses:\n  1) GNU Lesser General Public License (GNU LGPL)\n  2) Common Public License (CPL)\n  It means that you can select one of these two licenses and \n  follow rules of that license.\n\n  SPECIAL EXCEPTION:\n  Igor Pavlov, as the author of this code, expressly permits you to \n  statically or dynamically link your code (or bind by name) to the \n  interfaces of this file without subjecting your linked code to the \n  terms of the CPL or GNU LGPL. Any modifications or additions \n  to this file, however, are subject to the LGPL or CPL terms.\n*/\n\n#include \"LzmaDecode.h\"\n\n#ifndef Byte\n#define Byte unsigned char\n#endif\n\n#define kNumTopBits 24\n#define kTopValue ((UInt32)1 << kNumTopBits)\n\n#define kNumBitModelTotalBits 11\n#define kBitModelTotal (1 << kNumBitModelTotalBits)\n#define kNumMoveBits 5\n\ntypedef struct _CRangeDecoder\n{\n  Byte *Buffer;\n  Byte *BufferLim;\n  UInt32 Range;\n  UInt32 Code;\n  #ifdef _LZMA_IN_CB\n  ILzmaInCallback *InCallback;\n  int Result;\n  #endif\n  int ExtraBytes;\n} CRangeDecoder;\n\nByte RangeDecoderReadByte(CRangeDecoder *rd)\n{\n  if (rd->Buffer == rd->BufferLim)\n  {\n    #ifdef _LZMA_IN_CB\n    UInt32 size;\n    rd->Result = rd->InCallback->Read(rd->InCallback, &rd->Buffer, &size);\n    rd->BufferLim = rd->Buffer + size;\n    if (size == 0)\n    #endif\n    {\n      rd->ExtraBytes = 1;\n      return 0xFF;\n    }\n  }\n  return (*rd->Buffer++);\n}\n\n/* #define ReadByte (*rd->Buffer++) */\n#define ReadByte (RangeDecoderReadByte(rd))\n\nvoid RangeDecoderInit(CRangeDecoder *rd,\n  #ifdef _LZMA_IN_CB\n    ILzmaInCallback *inCallback\n  #else\n    Byte *stream, UInt32 bufferSize\n  #endif\n    )\n{\n  int i;\n  #ifdef _LZMA_IN_CB\n  rd->InCallback = inCallback;\n  rd->Buffer = rd->BufferLim = 0;\n  #else\n  rd->Buffer = stream;\n  rd->BufferLim = stream + bufferSize;\n  #endif\n  rd->ExtraBytes = 0;\n  rd->Code = 0;\n  rd->Range = (0xFFFFFFFF);\n  for(i = 0; i < 5; i++)\n    rd->Code = (rd->Code << 8) | ReadByte;\n}\n\n#define RC_INIT_VAR UInt32 range = rd->Range; UInt32 code = rd->Code;        \n#define RC_FLUSH_VAR rd->Range = range; rd->Code = code;\n#define RC_NORMALIZE if (range < kTopValue) { range <<= 8; code = (code << 8) | ReadByte; }\n\nUInt32 RangeDecoderDecodeDirectBits(CRangeDecoder *rd, int numTotalBits)\n{\n  RC_INIT_VAR\n  UInt32 result = 0;\n  int i;\n  for (i = numTotalBits; i > 0; i--)\n  {\n    /* UInt32 t; */\n    range >>= 1;\n\n    result <<= 1;\n    if (code >= range)\n    {\n      code -= range;\n      result |= 1;\n    }\n    /*\n    t = (code - range) >> 31;\n    t &= 1;\n    code -= range & (t - 1);\n    result = (result + result) | (1 - t);\n    */\n    RC_NORMALIZE\n  }\n  RC_FLUSH_VAR\n  return result;\n}\n\nint RangeDecoderBitDecode(CProb *prob, CRangeDecoder *rd)\n{\n  UInt32 bound = (rd->Range >> kNumBitModelTotalBits) * *prob;\n  if (rd->Code < bound)\n  {\n    rd->Range = bound;\n    *prob += (kBitModelTotal - *prob) >> kNumMoveBits;\n    if (rd->Range < kTopValue)\n    {\n      rd->Code = (rd->Code << 8) | ReadByte;\n      rd->Range <<= 8;\n    }\n    return 0;\n  }\n  else\n  {\n    rd->Range -= bound;\n    rd->Code -= bound;\n    *prob -= (*prob) >> kNumMoveBits;\n    if (rd->Range < kTopValue)\n    {\n      rd->Code = (rd->Code << 8) | ReadByte;\n      rd->Range <<= 8;\n    }\n    return 1;\n  }\n}\n\n#define RC_GET_BIT2(prob, mi, A0, A1) \\\n  UInt32 bound = (range >> kNumBitModelTotalBits) * *prob; \\\n  if (code < bound) \\\n    { A0; range = bound; *prob += (kBitModelTotal - *prob) >> kNumMoveBits; mi <<= 1; } \\\n  else \\\n    { A1; range -= bound; code -= bound; *prob -= (*prob) >> kNumMoveBits; mi = (mi + mi) + 1; } \\\n  RC_NORMALIZE\n\n#define RC_GET_BIT(prob, mi) RC_GET_BIT2(prob, mi, ; , ;)               \n\nint RangeDecoderBitTreeDecode(CProb *probs, int numLevels, CRangeDecoder *rd)\n{\n  int mi = 1;\n  int i;\n  #ifdef _LZMA_LOC_OPT\n  RC_INIT_VAR\n  #endif\n  for(i = numLevels; i > 0; i--)\n  {\n    #ifdef _LZMA_LOC_OPT\n    CProb *prob = probs + mi;\n    RC_GET_BIT(prob, mi)\n    #else\n    mi = (mi + mi) + RangeDecoderBitDecode(probs + mi, rd);\n    #endif\n  }\n  #ifdef _LZMA_LOC_OPT\n  RC_FLUSH_VAR\n  #endif\n  return mi - (1 << numLevels);\n}\n\nint RangeDecoderReverseBitTreeDecode(CProb *probs, int numLevels, CRangeDecoder *rd)\n{\n  int mi = 1;\n  int i;\n  int symbol = 0;\n  #ifdef _LZMA_LOC_OPT\n  RC_INIT_VAR\n  #endif\n  for(i = 0; i < numLevels; i++)\n  {\n    #ifdef _LZMA_LOC_OPT\n    CProb *prob = probs + mi;\n    RC_GET_BIT2(prob, mi, ; , symbol |= (1 << i))\n    #else\n    int bit = RangeDecoderBitDecode(probs + mi, rd);\n    mi = mi + mi + bit;\n    symbol |= (bit << i);\n    #endif\n  }\n  #ifdef _LZMA_LOC_OPT\n  RC_FLUSH_VAR\n  #endif\n  return symbol;\n}\n\nByte LzmaLiteralDecode(CProb *probs, CRangeDecoder *rd)\n{ \n  int symbol = 1;\n  #ifdef _LZMA_LOC_OPT\n  RC_INIT_VAR\n  #endif\n  do\n  {\n    #ifdef _LZMA_LOC_OPT\n    CProb *prob = probs + symbol;\n    RC_GET_BIT(prob, symbol)\n    #else\n    symbol = (symbol + symbol) | RangeDecoderBitDecode(probs + symbol, rd);\n    #endif\n  }\n  while (symbol < 0x100);\n  #ifdef _LZMA_LOC_OPT\n  RC_FLUSH_VAR\n  #endif\n  return symbol;\n}\n\nByte LzmaLiteralDecodeMatch(CProb *probs, CRangeDecoder *rd, Byte matchByte)\n{ \n  int symbol = 1;\n  #ifdef _LZMA_LOC_OPT\n  RC_INIT_VAR\n  #endif\n  do\n  {\n    int bit;\n    int matchBit = (matchByte >> 7) & 1;\n    matchByte <<= 1;\n    #ifdef _LZMA_LOC_OPT\n    {\n      CProb *prob = probs + ((1 + matchBit) << 8) + symbol;\n      RC_GET_BIT2(prob, symbol, bit = 0, bit = 1)\n    }\n    #else\n    bit = RangeDecoderBitDecode(probs + ((1 + matchBit) << 8) + symbol, rd);\n    symbol = (symbol << 1) | bit;\n    #endif\n    if (matchBit != bit)\n    {\n      while (symbol < 0x100)\n      {\n        #ifdef _LZMA_LOC_OPT\n        CProb *prob = probs + symbol;\n        RC_GET_BIT(prob, symbol)\n        #else\n        symbol = (symbol + symbol) | RangeDecoderBitDecode(probs + symbol, rd);\n        #endif\n      }\n      break;\n    }\n  }\n  while (symbol < 0x100);\n  #ifdef _LZMA_LOC_OPT\n  RC_FLUSH_VAR\n  #endif\n  return symbol;\n}\n\n#define kNumPosBitsMax 4\n#define kNumPosStatesMax (1 << kNumPosBitsMax)\n\n#define kLenNumLowBits 3\n#define kLenNumLowSymbols (1 << kLenNumLowBits)\n#define kLenNumMidBits 3\n#define kLenNumMidSymbols (1 << kLenNumMidBits)\n#define kLenNumHighBits 8\n#define kLenNumHighSymbols (1 << kLenNumHighBits)\n\n#define LenChoice 0\n#define LenChoice2 (LenChoice + 1)\n#define LenLow (LenChoice2 + 1)\n#define LenMid (LenLow + (kNumPosStatesMax << kLenNumLowBits))\n#define LenHigh (LenMid + (kNumPosStatesMax << kLenNumMidBits))\n#define kNumLenProbs (LenHigh + kLenNumHighSymbols) \n\nint LzmaLenDecode(CProb *p, CRangeDecoder *rd, int posState)\n{\n  if(RangeDecoderBitDecode(p + LenChoice, rd) == 0)\n    return RangeDecoderBitTreeDecode(p + LenLow +\n        (posState << kLenNumLowBits), kLenNumLowBits, rd);\n  if(RangeDecoderBitDecode(p + LenChoice2, rd) == 0)\n    return kLenNumLowSymbols + RangeDecoderBitTreeDecode(p + LenMid +\n        (posState << kLenNumMidBits), kLenNumMidBits, rd);\n  return kLenNumLowSymbols + kLenNumMidSymbols + \n      RangeDecoderBitTreeDecode(p + LenHigh, kLenNumHighBits, rd);\n}\n\n#define kNumStates 12\n\n#define kStartPosModelIndex 4\n#define kEndPosModelIndex 14\n#define kNumFullDistances (1 << (kEndPosModelIndex >> 1))\n\n#define kNumPosSlotBits 6\n#define kNumLenToPosStates 4\n\n#define kNumAlignBits 4\n#define kAlignTableSize (1 << kNumAlignBits)\n\n#define kMatchMinLen 2\n\n#define IsMatch 0\n#define IsRep (IsMatch + (kNumStates << kNumPosBitsMax))\n#define IsRepG0 (IsRep + kNumStates)\n#define IsRepG1 (IsRepG0 + kNumStates)\n#define IsRepG2 (IsRepG1 + kNumStates)\n#define IsRep0Long (IsRepG2 + kNumStates)\n#define PosSlot (IsRep0Long + (kNumStates << kNumPosBitsMax))\n#define SpecPos (PosSlot + (kNumLenToPosStates << kNumPosSlotBits))\n#define Align (SpecPos + kNumFullDistances - kEndPosModelIndex)\n#define LenCoder (Align + kAlignTableSize)\n#define RepLenCoder (LenCoder + kNumLenProbs)\n#define Literal (RepLenCoder + kNumLenProbs)\n\n#if Literal != LZMA_BASE_SIZE\nStopCompilingDueBUG\n#endif\n\n#ifdef _LZMA_OUT_READ\n\ntypedef struct _LzmaVarState\n{\n  CRangeDecoder RangeDecoder;\n  Byte *Dictionary;\n  UInt32 DictionarySize;\n  UInt32 DictionaryPos;\n  UInt32 GlobalPos;\n  UInt32 Reps[4];\n  int lc;\n  int lp;\n  int pb;\n  int State;\n  int PreviousIsMatch;\n  int RemainLen;\n} LzmaVarState;\n\nint LzmaDecoderInit(\n    unsigned char *buffer, UInt32 bufferSize,\n    int lc, int lp, int pb,\n    unsigned char *dictionary, UInt32 dictionarySize,\n    #ifdef _LZMA_IN_CB\n    ILzmaInCallback *inCallback\n    #else\n    unsigned char *inStream, UInt32 inSize\n    #endif\n    )\n{\n  LzmaVarState *vs = (LzmaVarState *)buffer;\n  CProb *p = (CProb *)(buffer + sizeof(LzmaVarState));\n  UInt32 numProbs = Literal + ((UInt32)LZMA_LIT_SIZE << (lc + lp));\n  UInt32 i;\n  if (bufferSize < numProbs * sizeof(CProb) + sizeof(LzmaVarState))\n    return LZMA_RESULT_NOT_ENOUGH_MEM;\n  vs->Dictionary = dictionary;\n  vs->DictionarySize = dictionarySize;\n  vs->DictionaryPos = 0;\n  vs->GlobalPos = 0;\n  vs->Reps[0] = vs->Reps[1] = vs->Reps[2] = vs->Reps[3] = 1;\n  vs->lc = lc;\n  vs->lp = lp;\n  vs->pb = pb;\n  vs->State = 0;\n  vs->PreviousIsMatch = 0;\n  vs->RemainLen = 0;\n  dictionary[dictionarySize - 1] = 0;\n  for (i = 0; i < numProbs; i++)\n    p[i] = kBitModelTotal >> 1; \n  RangeDecoderInit(&vs->RangeDecoder, \n      #ifdef _LZMA_IN_CB\n      inCallback\n      #else\n      inStream, inSize\n      #endif\n  );\n  return LZMA_RESULT_OK;\n}\n\nint LzmaDecode(unsigned char *buffer, \n    unsigned char *outStream, UInt32 outSize,\n    UInt32 *outSizeProcessed)\n{\n  LzmaVarState *vs = (LzmaVarState *)buffer;\n  CProb *p = (CProb *)(buffer + sizeof(LzmaVarState));\n  CRangeDecoder rd = vs->RangeDecoder;\n  int state = vs->State;\n  int previousIsMatch = vs->PreviousIsMatch;\n  Byte previousByte;\n  UInt32 rep0 = vs->Reps[0], rep1 = vs->Reps[1], rep2 = vs->Reps[2], rep3 = vs->Reps[3];\n  UInt32 nowPos = 0;\n  UInt32 posStateMask = (1 << (vs->pb)) - 1;\n  UInt32 literalPosMask = (1 << (vs->lp)) - 1;\n  int lc = vs->lc;\n  int len = vs->RemainLen;\n  UInt32 globalPos = vs->GlobalPos;\n\n  Byte *dictionary = vs->Dictionary;\n  UInt32 dictionarySize = vs->DictionarySize;\n  UInt32 dictionaryPos = vs->DictionaryPos;\n\n  if (len == -1)\n  {\n    *outSizeProcessed = 0;\n    return LZMA_RESULT_OK;\n  }\n\n  while(len > 0 && nowPos < outSize)\n  {\n    UInt32 pos = dictionaryPos - rep0;\n    if (pos >= dictionarySize)\n      pos += dictionarySize;\n    outStream[nowPos++] = dictionary[dictionaryPos] = dictionary[pos];\n    if (++dictionaryPos == dictionarySize)\n      dictionaryPos = 0;\n    len--;\n  }\n  if (dictionaryPos == 0)\n    previousByte = dictionary[dictionarySize - 1];\n  else\n    previousByte = dictionary[dictionaryPos - 1];\n#else\n\nint LzmaDecode(\n    Byte *buffer, UInt32 bufferSize,\n    int lc, int lp, int pb,\n    #ifdef _LZMA_IN_CB\n    ILzmaInCallback *inCallback,\n    #else\n    unsigned char *inStream, UInt32 inSize,\n    #endif\n    unsigned char *outStream, UInt32 outSize,\n    UInt32 *outSizeProcessed)\n{\n  UInt32 numProbs = Literal + ((UInt32)LZMA_LIT_SIZE << (lc + lp));\n  CProb *p = (CProb *)buffer;\n  CRangeDecoder rd;\n  UInt32 i;\n  int state = 0;\n  int previousIsMatch = 0;\n  Byte previousByte = 0;\n  UInt32 rep0 = 1, rep1 = 1, rep2 = 1, rep3 = 1;\n  UInt32 nowPos = 0;\n  UInt32 posStateMask = (1 << pb) - 1;\n  UInt32 literalPosMask = (1 << lp) - 1;\n  int len = 0;\n  if (bufferSize < numProbs * sizeof(CProb))\n    return LZMA_RESULT_NOT_ENOUGH_MEM;\n  for (i = 0; i < numProbs; i++)\n    p[i] = kBitModelTotal >> 1; \n  RangeDecoderInit(&rd, \n      #ifdef _LZMA_IN_CB\n      inCallback\n      #else\n      inStream, inSize\n      #endif\n      );\n#endif\n\n  *outSizeProcessed = 0;\n  while(nowPos < outSize)\n  {\n    int posState = (int)(\n        (nowPos \n        #ifdef _LZMA_OUT_READ\n        + globalPos\n        #endif\n        )\n        & posStateMask);\n    #ifdef _LZMA_IN_CB\n    if (rd.Result != LZMA_RESULT_OK)\n      return rd.Result;\n    #endif\n    if (rd.ExtraBytes != 0)\n      return LZMA_RESULT_DATA_ERROR;\n    if (RangeDecoderBitDecode(p + IsMatch + (state << kNumPosBitsMax) + posState, &rd) == 0)\n    {\n      CProb *probs = p + Literal + (LZMA_LIT_SIZE * \n        (((\n        (nowPos \n        #ifdef _LZMA_OUT_READ\n        + globalPos\n        #endif\n        )\n        & literalPosMask) << lc) + (previousByte >> (8 - lc))));\n\n      if (state < 4) state = 0;\n      else if (state < 10) state -= 3;\n      else state -= 6;\n      if (previousIsMatch)\n      {\n        Byte matchByte;\n        #ifdef _LZMA_OUT_READ\n        UInt32 pos = dictionaryPos - rep0;\n        if (pos >= dictionarySize)\n          pos += dictionarySize;\n        matchByte = dictionary[pos];\n        #else\n        matchByte = outStream[nowPos - rep0];\n        #endif\n        previousByte = LzmaLiteralDecodeMatch(probs, &rd, matchByte);\n        previousIsMatch = 0;\n      }\n      else\n        previousByte = LzmaLiteralDecode(probs, &rd);\n      outStream[nowPos++] = previousByte;\n      #ifdef _LZMA_OUT_READ\n      dictionary[dictionaryPos] = previousByte;\n      if (++dictionaryPos == dictionarySize)\n        dictionaryPos = 0;\n      #endif\n    }\n    else             \n    {\n      previousIsMatch = 1;\n      if (RangeDecoderBitDecode(p + IsRep + state, &rd) == 1)\n      {\n        if (RangeDecoderBitDecode(p + IsRepG0 + state, &rd) == 0)\n        {\n          if (RangeDecoderBitDecode(p + IsRep0Long + (state << kNumPosBitsMax) + posState, &rd) == 0)\n          {\n            #ifdef _LZMA_OUT_READ\n            UInt32 pos;\n            #endif\n            if (\n               (nowPos \n                #ifdef _LZMA_OUT_READ\n                + globalPos\n                #endif\n               )\n               == 0)\n              return LZMA_RESULT_DATA_ERROR;\n            state = state < 7 ? 9 : 11;\n            #ifdef _LZMA_OUT_READ\n            pos = dictionaryPos - rep0;\n            if (pos >= dictionarySize)\n              pos += dictionarySize;\n            previousByte = dictionary[pos];\n            dictionary[dictionaryPos] = previousByte;\n            if (++dictionaryPos == dictionarySize)\n              dictionaryPos = 0;\n            #else\n            previousByte = outStream[nowPos - rep0];\n            #endif\n            outStream[nowPos++] = previousByte;\n            continue;\n          }\n        }\n        else\n        {\n          UInt32 distance;\n          if(RangeDecoderBitDecode(p + IsRepG1 + state, &rd) == 0)\n            distance = rep1;\n          else \n          {\n            if(RangeDecoderBitDecode(p + IsRepG2 + state, &rd) == 0)\n              distance = rep2;\n            else\n            {\n              distance = rep3;\n              rep3 = rep2;\n            }\n            rep2 = rep1;\n          }\n          rep1 = rep0;\n          rep0 = distance;\n        }\n        len = LzmaLenDecode(p + RepLenCoder, &rd, posState);\n        state = state < 7 ? 8 : 11;\n      }\n      else\n      {\n        int posSlot;\n        rep3 = rep2;\n        rep2 = rep1;\n        rep1 = rep0;\n        state = state < 7 ? 7 : 10;\n        len = LzmaLenDecode(p + LenCoder, &rd, posState);\n        posSlot = RangeDecoderBitTreeDecode(p + PosSlot +\n            ((len < kNumLenToPosStates ? len : kNumLenToPosStates - 1) << \n            kNumPosSlotBits), kNumPosSlotBits, &rd);\n        if (posSlot >= kStartPosModelIndex)\n        {\n          int numDirectBits = ((posSlot >> 1) - 1);\n          rep0 = ((2 | ((UInt32)posSlot & 1)) << numDirectBits);\n          if (posSlot < kEndPosModelIndex)\n          {\n            rep0 += RangeDecoderReverseBitTreeDecode(\n                p + SpecPos + rep0 - posSlot - 1, numDirectBits, &rd);\n          }\n          else\n          {\n            rep0 += RangeDecoderDecodeDirectBits(&rd, \n                numDirectBits - kNumAlignBits) << kNumAlignBits;\n            rep0 += RangeDecoderReverseBitTreeDecode(p + Align, kNumAlignBits, &rd);\n          }\n        }\n        else\n          rep0 = posSlot;\n        rep0++;\n      }\n      if (rep0 == (UInt32)(0))\n      {\n        /* it's for stream version */\n        len = -1;\n        break;\n      }\n      if (rep0 > nowPos \n        #ifdef _LZMA_OUT_READ\n        + globalPos\n        #endif\n        )\n      {\n        return LZMA_RESULT_DATA_ERROR;\n      }\n      len += kMatchMinLen;\n      do\n      {\n        #ifdef _LZMA_OUT_READ\n        UInt32 pos = dictionaryPos - rep0;\n        if (pos >= dictionarySize)\n          pos += dictionarySize;\n        previousByte = dictionary[pos];\n        dictionary[dictionaryPos] = previousByte;\n        if (++dictionaryPos == dictionarySize)\n          dictionaryPos = 0;\n        #else\n        previousByte = outStream[nowPos - rep0];\n        #endif\n        outStream[nowPos++] = previousByte;\n        len--;\n      }\n      while(len > 0 && nowPos < outSize);\n    }\n  }\n\n  #ifdef _LZMA_OUT_READ\n  vs->RangeDecoder = rd;\n  vs->DictionaryPos = dictionaryPos;\n  vs->GlobalPos = globalPos + nowPos;\n  vs->Reps[0] = rep0;\n  vs->Reps[1] = rep1;\n  vs->Reps[2] = rep2;\n  vs->Reps[3] = rep3;\n  vs->State = state;\n  vs->PreviousIsMatch = previousIsMatch;\n  vs->RemainLen = len;\n  #endif\n\n  *outSizeProcessed = nowPos;\n  return LZMA_RESULT_OK;\n}\n"
  },
  {
    "path": "target/linux/bcm47xx/image/lzma-loader/src/LzmaDecode.h",
    "content": "/* \n  LzmaDecode.h\n  LZMA Decoder interface\n\n  LZMA SDK 4.05 Copyright (c) 1999-2004 Igor Pavlov (2004-08-25)\n  http://www.7-zip.org/\n\n  LZMA SDK is licensed under two licenses:\n  1) GNU Lesser General Public License (GNU LGPL)\n  2) Common Public License (CPL)\n  It means that you can select one of these two licenses and \n  follow rules of that license.\n\n  SPECIAL EXCEPTION:\n  Igor Pavlov, as the author of this code, expressly permits you to \n  statically or dynamically link your code (or bind by name) to the \n  interfaces of this file without subjecting your linked code to the \n  terms of the CPL or GNU LGPL. Any modifications or additions \n  to this file, however, are subject to the LGPL or CPL terms.\n*/\n\n#ifndef __LZMADECODE_H\n#define __LZMADECODE_H\n\n/* #define _LZMA_IN_CB */\n/* Use callback for input data */\n\n/* #define _LZMA_OUT_READ */\n/* Use read function for output data */\n\n/* #define _LZMA_PROB32 */\n/* It can increase speed on some 32-bit CPUs, \n   but memory usage will be doubled in that case */\n\n/* #define _LZMA_LOC_OPT */\n/* Enable local speed optimizations inside code */\n\n#ifndef UInt32\n#ifdef _LZMA_UINT32_IS_ULONG\n#define UInt32 unsigned long\n#else\n#define UInt32 unsigned int\n#endif\n#endif\n\n#ifdef _LZMA_PROB32\n#define CProb UInt32\n#else\n#define CProb unsigned short\n#endif\n\n#define LZMA_RESULT_OK 0\n#define LZMA_RESULT_DATA_ERROR 1\n#define LZMA_RESULT_NOT_ENOUGH_MEM 2\n\n#ifdef _LZMA_IN_CB\ntypedef struct _ILzmaInCallback\n{\n  int (*Read)(void *object, unsigned char **buffer, UInt32 *bufferSize);\n} ILzmaInCallback;\n#endif\n\n#define LZMA_BASE_SIZE 1846\n#define LZMA_LIT_SIZE 768\n\n/* \nbufferSize = (LZMA_BASE_SIZE + (LZMA_LIT_SIZE << (lc + lp)))* sizeof(CProb)\nbufferSize += 100 in case of _LZMA_OUT_READ\nby default CProb is unsigned short, \nbut if specify _LZMA_PROB_32, CProb will be UInt32(unsigned int)\n*/\n\n#ifdef _LZMA_OUT_READ\nint LzmaDecoderInit(\n    unsigned char *buffer, UInt32 bufferSize,\n    int lc, int lp, int pb,\n    unsigned char *dictionary, UInt32 dictionarySize,\n  #ifdef _LZMA_IN_CB\n    ILzmaInCallback *inCallback\n  #else\n    unsigned char *inStream, UInt32 inSize\n  #endif\n);\n#endif\n\nint LzmaDecode(\n    unsigned char *buffer, \n  #ifndef _LZMA_OUT_READ\n    UInt32 bufferSize,\n    int lc, int lp, int pb,\n  #ifdef _LZMA_IN_CB\n    ILzmaInCallback *inCallback,\n  #else\n    unsigned char *inStream, UInt32 inSize,\n  #endif\n  #endif\n    unsigned char *outStream, UInt32 outSize,\n    UInt32 *outSizeProcessed);\n\n#endif\n"
  },
  {
    "path": "target/linux/bcm47xx/image/lzma-loader/src/Makefile",
    "content": "#\n# Makefile for Broadcom BCM947XX boards\n#\n# Copyright 2001-2003, Broadcom Corporation\n# All Rights Reserved.\n# \n# THIS SOFTWARE IS OFFERED \"AS IS\", AND BROADCOM GRANTS NO WARRANTIES OF ANY\n# KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM\n# SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS\n# FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.\n#\n# Copyright 2004  Manuel Novoa III <mjn3@codepoet.org>\n#   Modified to support bzip'd kernels.\n#   Of course, it would be better to integrate bunzip capability into CFE.\n#\n# Copyright 2005  Oleg I. Vdovikin <oleg@cs.msu.su>\n#   Cleaned up, modified for lzma support, removed from kernel\n#\n\nTEXT_START\t:= 0x80001000\nBZ_TEXT_START\t:= 0x80700000\nBZ_STACK_START\t:= 0x80800000\n\nOBJCOPY\t\t:= $(CROSS_COMPILE)objcopy -O binary -R .reginfo -R .note -R .comment -R .mdebug -S\n\nCFLAGS\t\t= -D__KERNEL__ -Wall -Wstrict-prototypes -Wno-trigraphs -Os \\\n\t\t  -fno-strict-aliasing -fno-common -fomit-frame-pointer -G 0 -mno-abicalls -fno-pic \\\n\t\t  -ffunction-sections -pipe -mlong-calls -fno-common \\\n\t\t  -mabi=32 -march=mips32 -Wa,-32 -Wa,-march=mips32 -Wa,-mips32 -Wa,--trap\nCFLAGS\t\t+= -DLOADADDR=$(TEXT_START) -D_LZMA_IN_CB\n\nASFLAGS\t\t= $(CFLAGS) -D__ASSEMBLY__ -DBZ_TEXT_START=$(BZ_TEXT_START) -DBZ_STACK_START=$(BZ_STACK_START)\n\nSEDFLAGS\t:= s/BZ_TEXT_START/$(BZ_TEXT_START)/;s/BZ_STACK_START/$(BZ_STACK_START)/;s/TEXT_START/$(TEXT_START)/\n\nOBJECTS\t\t:= head.o data.o\n\nall: loader.gz loader.elf\n\n# Don't build dependencies, this may die if $(CC) isn't gcc\ndep:\n\ninstall:\n\nloader.gz: loader\n\tgzip -nc9 $< > $@\n\nloader.elf: loader.o\n\tcp $< $@\n\nloader: loader.o\n\t$(OBJCOPY) $< $@\n\nloader.o: loader.lds $(OBJECTS)\n\t$(LD) -static --gc-sections -no-warn-mismatch -T loader.lds -o $@ $(OBJECTS)\n\nloader.lds: loader.lds.in Makefile\n\t@sed \"$(SEDFLAGS)\" < $< > $@\n\ndata.o: data.lds decompress.image\n\t$(LD) -no-warn-mismatch -T data.lds -r -o $@ -b binary decompress.image -b elf32-tradlittlemips\n\ndata.lds:\n\t@echo \"SECTIONS { .data : { code_start = .; *(.data) code_stop = .; }}\" > $@\n\ndecompress.image: decompress\n\t$(OBJCOPY) $< $@\n\ndecompress: decompress.lds decompress.o LzmaDecode.o\n\t$(LD) -static --gc-sections -no-warn-mismatch -T decompress.lds -o $@ decompress.o LzmaDecode.o\n\ndecompress.lds: decompress.lds.in Makefile\n\t@sed \"$(SEDFLAGS)\" < $< > $@\n\nmrproper: clean\n\nclean:\n\trm -f loader.gz loader decompress *.lds *.o *.image\n"
  },
  {
    "path": "target/linux/bcm47xx/image/lzma-loader/src/README",
    "content": "/*\n * LZMA compressed kernel decompressor for bcm947xx boards\n *\n * Copyright (C) 2005 by Oleg I. Vdovikin <oleg@cs.msu.su>\n *\n * This program is free software; you can redistribute it and/or modify\n * it under the terms of the GNU General Public License as published by\n * the Free Software Foundation; either version 2 of the License, or\n * (at your option) any later version.\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU\n * General Public License for more details.\n *\n * You should have received a copy of the GNU General Public License\n * along with this program; if not, write to the Free Software\n * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\n *\n */\n\nThe code is intended to decompress kernel, being compressed using lzma utility\nbuild using 7zip LZMA SDK. This utility is located in the LZMA_Alone directory\n\ndecompressor code expects that your .trx file consist of three partitions: \n\n1) decompressor itself (this is gziped code which pmon/cfe will extract and run\non boot-up instead of real kernel)\n2) LZMA compressed kernel (both streamed and regular modes are supported now)\n3) Root filesystem\n\nPlease be sure to apply the following patch for use this new trx layout (it will\nallow using both new and old trx files for root filesystem lookup code)\n\n--- linuz/arch/mips/brcm-boards/bcm947xx/setup.c        2005-01-23 19:24:27.503322896 +0300\n+++ linux/arch/mips/brcm-boards/bcm947xx/setup.c        2005-01-23 19:29:05.237100944 +0300\n@@ -221,7 +221,9 @@\n                /* Try looking at TRX header for rootfs offset */\n                if (le32_to_cpu(trx->magic) == TRX_MAGIC) {\n                        bcm947xx_parts[1].offset = off;\n-                       if (le32_to_cpu(trx->offsets[1]) > off)\n+                       if (le32_to_cpu(trx->offsets[2]) > off)\n+                               off = le32_to_cpu(trx->offsets[2]);\n+                       else if (le32_to_cpu(trx->offsets[1]) > off)\n                                off = le32_to_cpu(trx->offsets[1]);\n                        continue;\n                }\n\n\nRevision history:\n\t0.02\tInitial release\n\t0.03\tAdded Mineharu Takahara <mtakahar@yahoo.com> patch to pass actual\n\t\toutput size to decoder (stream mode compressed input is not \n\t\ta requirement anymore)\n\t0.04\tReordered functions using lds script\n"
  },
  {
    "path": "target/linux/bcm47xx/image/lzma-loader/src/decompress.c",
    "content": "/*\n * LZMA compressed kernel decompressor for bcm947xx boards\n *\n * Copyright (C) 2005 by Oleg I. Vdovikin <oleg@cs.msu.su>\n *\n * This program is free software; you can redistribute it and/or modify\n * it under the terms of the GNU General Public License as published by\n * the Free Software Foundation; either version 2 of the License, or\n * (at your option) any later version.\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU\n * General Public License for more details.\n *\n * You should have received a copy of the GNU General Public License\n * along with this program; if not, write to the Free Software\n * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\n *\n *\n * Please note, this was code based on the bunzip2 decompressor code\n * by Manuel Novoa III  (mjn3@codepoet.org), although the only thing left\n * is an idea and part of original vendor code\n *\n *\n * 12-Mar-2005  Mineharu Takahara <mtakahar@yahoo.com>\n *   pass actual output size to decoder (stream mode\n *   compressed input is not a requirement anymore)\n *\n * 24-Apr-2005 Oleg I. Vdovikin\n *   reordered functions using lds script, removed forward decl\n *\n */\n\n#include \"LzmaDecode.h\"\n\n#define BCM4710_FLASH\t\t0x1fc00000\t/* Flash */\n\n#define KSEG0\t\t\t0x80000000\n#define KSEG1\t\t\t0xa0000000\n\n#define KSEG1ADDR(a)\t\t((((unsigned)(a)) & 0x1fffffffU) | KSEG1)\n\n#define Index_Invalidate_I\t0x00\n#define Index_Writeback_Inv_D   0x01\n\n#define cache_unroll(base,op)\t\\\n\t__asm__ __volatile__(\t\t\\\n\t\t\".set noreorder;\\n\"\t\t\\\n\t\t\".set mips3;\\n\"\t\t\t\\\n\t\t\"cache %1, (%0);\\n\"\t\t\\\n\t\t\".set mips0;\\n\"\t\t\t\\\n\t\t\".set reorder\\n\"\t\t\\\n\t\t:\t\t\t\t\t\t\\\n\t\t: \"r\" (base),\t\t\t\\\n\t\t  \"i\" (op));\n\nstatic __inline__ void blast_icache(unsigned long size, unsigned long lsize)\n{\n\tunsigned long start = KSEG0;\n\tunsigned long end = (start + size);\n\n\twhile(start < end) {\n\t\tcache_unroll(start,Index_Invalidate_I);\n\t\tstart += lsize;\n\t}\n}\n\nstatic __inline__ void blast_dcache(unsigned long size, unsigned long lsize)\n{\n\tunsigned long start = KSEG0;\n\tunsigned long end = (start + size);\n\n\twhile(start < end) {\n\t\tcache_unroll(start,Index_Writeback_Inv_D);\n\t\tstart += lsize;\n\t}\n}\n\n#define TRX_MAGIC       0x30524448      /* \"HDR0\" */\n\nstruct trx_header {\n\tunsigned int magic;\t\t/* \"HDR0\" */\n\tunsigned int len;\t\t/* Length of file including header */\n\tunsigned int crc32;\t\t/* 32-bit CRC from flag_version to end of file */\n\tunsigned int flag_version;\t/* 0:15 flags, 16:31 version */\n\tunsigned int offsets[3];\t/* Offsets of partitions from start of header */\n};\n\n#define EDIMAX_PS_HEADER_MAGIC\t0x36315350 /*  \"PS16\"  */\n#define EDIMAX_PS_HEADER_LEN\t0xc /* 12 bytes long for edimax header */\n\n/* beyound the image end, size not known in advance */\nextern unsigned char workspace[];\n\nunsigned int offset;\nunsigned char *data;\n\n/* flash access should be aligned, so wrapper is used */\n/* read byte from the flash, all accesses are 32-bit aligned */\nstatic int read_byte(void *object, unsigned char **buffer, UInt32 *bufferSize)\n{\n\tstatic unsigned int val;\n\n\tif (((unsigned int)offset % 4) == 0) {\n\t\tval = *(unsigned int *)data;\n\t\tdata += 4;\n\t}\n\t\n\t*bufferSize = 1;\n\t*buffer = ((unsigned char *)&val) + (offset++ & 3);\n\t\n\treturn LZMA_RESULT_OK;\n}\n\nstatic __inline__ unsigned char get_byte(void)\n{\n\tunsigned char *buffer;\n\tUInt32 fake;\n\t\n\treturn read_byte(0, &buffer, &fake), *buffer;\n}\n\n/* should be the first function */\nvoid entry(unsigned long icache_size, unsigned long icache_lsize, \n\tunsigned long dcache_size, unsigned long dcache_lsize,\n\tunsigned long fw_arg0, unsigned long fw_arg1,\n\tunsigned long fw_arg2, unsigned long fw_arg3)\n{\n\tunsigned int i;  /* temp value */\n\tunsigned int lc; /* literal context bits */\n\tunsigned int lp; /* literal pos state bits */\n\tunsigned int pb; /* pos state bits */\n\tunsigned int osize; /* uncompressed size */\n\n\tILzmaInCallback callback;\n\tcallback.Read = read_byte;\n\n\t/* look for trx header, 32-bit data access */\n\tfor (data = ((unsigned char *) KSEG1ADDR(BCM4710_FLASH));\n\t\t((struct trx_header *)data)->magic != TRX_MAGIC &&\n\t\t((struct trx_header *)data)->magic != EDIMAX_PS_HEADER_MAGIC;\n\t\t data += 65536);\n\n\tif (((struct trx_header *)data)->magic == EDIMAX_PS_HEADER_MAGIC)\n\t\tdata += EDIMAX_PS_HEADER_LEN;\n\t/* compressed kernel is in the partition 0 or 1 */\n\tif (((struct trx_header *)data)->offsets[1] > 65536) \n\t\tdata += ((struct trx_header *)data)->offsets[0];\n\telse\n\t\tdata += ((struct trx_header *)data)->offsets[1];\n\n\toffset = 0;\n\n\t/* lzma args */\n\ti = get_byte();\n\tlc = i % 9, i = i / 9;\n\tlp = i % 5, pb = i / 5;\n\n\t/* skip rest of the LZMA coder property */\n\tfor (i = 0; i < 4; i++)\n\t\tget_byte();\n\n\t/* read the lower half of uncompressed size in the header */\n\tosize = ((unsigned int)get_byte()) +\n\t\t((unsigned int)get_byte() << 8) +\n\t\t((unsigned int)get_byte() << 16) +\n\t\t((unsigned int)get_byte() << 24);\n\n\t/* skip rest of the header (upper half of uncompressed size) */\n\tfor (i = 0; i < 4; i++) \n\t\tget_byte();\n\n\t/* decompress kernel */\n\tif (LzmaDecode(workspace, ~0, lc, lp, pb, &callback,\n\t\t(unsigned char*)LOADADDR, osize, &i) == LZMA_RESULT_OK)\n\t{\n\t\tblast_dcache(dcache_size, dcache_lsize);\n\t\tblast_icache(icache_size, icache_lsize);\n\n\t\t/* Jump to load address */\n\t\t((void (*)(unsigned long, unsigned long, unsigned long,\n\t\t\tunsigned long)) LOADADDR)(fw_arg0, fw_arg1, fw_arg2,\n\t\t\t\tfw_arg3);\n\t}\n}\n"
  },
  {
    "path": "target/linux/bcm47xx/image/lzma-loader/src/decompress.lds.in",
    "content": "OUTPUT_ARCH(mips)\nENTRY(entry)\nSECTIONS {\n\t. = BZ_TEXT_START;\n\t.text : {\n\t\t*(.text.entry)\n\t\t*(.text)\n\t\t*(.rodata)\n\t}\n\n\t.data : {\n\t\t*(.data)\n\t}\n\n\t.bss : {\n\t\t*(.bss)\n\t}\n\n\tworkspace = .;\n}\n"
  },
  {
    "path": "target/linux/bcm47xx/image/lzma-loader/src/head.S",
    "content": "/* Copyright 2005 Oleg I. Vdovikin (oleg@cs.msu.su)\t*/\n/* cache manipulation adapted from Broadcom code \t*/\n/* idea taken from original bunzip2 decompressor code\t*/\n/* Copyright 2004 Manuel Novoa III (mjn3@codepoet.org)\t*/\n/* Licensed under the linux kernel's version of the GPL.*/\n\n#include <asm/asm.h>\n#include <asm/regdef.h>\n\n#define KSEG0\t\t0x80000000\n\n#define C0_CONFIG\t$16\n#define C0_TAGLO\t$28\n#define C0_TAGHI\t$29\n\n#define\tCONF1_DA_SHIFT\t7\t\t\t/* D$ associativity */\n#define CONF1_DA_MASK\t0x00000380\n#define CONF1_DA_BASE\t1\n#define CONF1_DL_SHIFT\t10\t\t\t/* D$ line size */\n#define CONF1_DL_MASK\t0x00001c00\n#define CONF1_DL_BASE\t2\n#define CONF1_DS_SHIFT\t13\t\t\t/* D$ sets/way */\n#define CONF1_DS_MASK\t0x0000e000\n#define CONF1_DS_BASE\t64\n#define CONF1_IA_SHIFT\t16\t\t\t/* I$ associativity */\n#define CONF1_IA_MASK\t0x00070000\n#define CONF1_IA_BASE\t1\n#define CONF1_IL_SHIFT\t19\t\t\t/* I$ line size */\n#define CONF1_IL_MASK\t0x00380000\n#define CONF1_IL_BASE\t2\n#define CONF1_IS_SHIFT\t22\t\t\t/* Instruction cache sets/way */\n#define CONF1_IS_MASK\t0x01c00000\n#define CONF1_IS_BASE\t64\n\n#define Index_Invalidate_I\t0x00\n#define Index_Writeback_Inv_D   0x01\n\n\t.text\n\tLEAF(startup)\n\t.set noreorder\n\tli\tsp, BZ_STACK_START\n\taddi    sp, -48\n\tsw      a0, 16(sp)\n\tsw      a1, 20(sp)\n\tsw      a2, 24(sp)\n\tsw      a3, 28(sp)\n\n\t/* Copy decompressor code to the right place */\n\tli\tt2, BZ_TEXT_START\n\tadd\ta0, t2, 0\n\tla      a1, code_start\n\tla\ta2, code_stop\n$L1:\n\tlw\tt0, 0(a1)\n\tsw\tt0, 0(a0)\n\tadd\ta1, 4\n\tadd\ta0, 4\n\tblt\ta1, a2, $L1\n\tnop\n\n\t/* At this point we need to invalidate dcache and */\n\t/* icache before jumping to new code */\n\n1:\t/* Get cache sizes */\n\t.set\tmips32\n\tmfc0\ts0,C0_CONFIG,1\n\t.set\tmips0\n\n\tli\ts1,CONF1_DL_MASK\n\tand\ts1,s0\n\tbeq\ts1,zero,nodc\n\tnop\n\n\tsrl\ts1,CONF1_DL_SHIFT\n\tli\tt0,CONF1_DL_BASE\n\tsll\ts1,t0,s1\t\t/* s1 has D$ cache line size */\n\n\tli\ts2,CONF1_DA_MASK\n\tand\ts2,s0\n\tsrl\ts2,CONF1_DA_SHIFT\n\taddiu\ts2,CONF1_DA_BASE\t/* s2 now has D$ associativity */\n\n\tli\tt0,CONF1_DS_MASK\n\tand\tt0,s0\n\tsrl\tt0,CONF1_DS_SHIFT\n\tli\ts3,CONF1_DS_BASE\n\tsll\ts3,s3,t0\t\t/* s3 has D$ sets per way */\n\n\tmultu\ts2,s3\t\t\t/* sets/way * associativity */\n\tmflo\tt0\t\t\t/* total cache lines */\n\n\tmultu\ts1,t0\t\t\t/* D$ linesize * lines */\n\tmflo\ts2\t\t\t/* s2 is now D$ size in bytes */\n\n\t/* Initilize the D$: */\n\tmtc0\tzero,C0_TAGLO\n\tmtc0\tzero,C0_TAGHI\n\n\tli\tt0,KSEG0\t\t/* Just an address for the first $ line */\n\taddu\tt1,t0,s2\t\t/*  + size of cache == end */\n\n\t.set\tmips3\n1:\tcache\tIndex_Writeback_Inv_D,0(t0)\n\t.set\tmips0\n\tbne\tt0,t1,1b\n\taddu\tt0,s1\n\nnodc:\n\t/* Now we get to do it all again for the I$ */\n\n\tmove\ts3,zero\t\t\t/* just in case there is no icache */\n\tmove\ts4,zero\n\n\tli\tt0,CONF1_IL_MASK\n\tand\tt0,s0\n\tbeq\tt0,zero,noic\n\tnop\n\n\tsrl\tt0,CONF1_IL_SHIFT\n\tli\ts3,CONF1_IL_BASE\n\tsll\ts3,t0\t\t\t/* s3 has I$ cache line size */\n\n\tli\tt0,CONF1_IA_MASK\n\tand\tt0,s0\n\tsrl\tt0,CONF1_IA_SHIFT\n\taddiu\ts4,t0,CONF1_IA_BASE\t/* s4 now has I$ associativity */\n\n\tli\tt0,CONF1_IS_MASK\n\tand\tt0,s0\n\tsrl\tt0,CONF1_IS_SHIFT\n\tli\ts5,CONF1_IS_BASE\n\tsll\ts5,t0\t\t\t/* s5 has I$ sets per way */\n\n\tmultu\ts4,s5\t\t\t/* sets/way * associativity */\n\tmflo\tt0\t\t\t/* s4 is now total cache lines */\n\n\tmultu\ts3,t0\t\t\t/* I$ linesize * lines */\n\tmflo\ts4\t\t\t/* s4 is cache size in bytes */\n\n\t/* Initilize the I$: */\n\tmtc0\tzero,C0_TAGLO\n\tmtc0\tzero,C0_TAGHI\n\n\tli\tt0,KSEG0\t\t/* Just an address for the first $ line */\n\taddu\tt1,t0,s4\t\t/*  + size of cache == end */\n\n\t.set\tmips3\n1:\tcache\tIndex_Invalidate_I,0(t0)\n\t.set\tmips0\n\tbne\tt0,t1,1b\n\taddu\tt0,s3\n\nnoic:\n\tmove\ta0,s4\t\t\t/* icache size */\n\tmove\ta1,s3\t\t\t/* icache line size */\n\tmove\ta2,s2\t\t\t/* dcache size */\n\tjal\tt2\n\tmove\ta3,s1\t\t\t/* dcache line size */\n\n\t.set reorder\n\tEND(startup)\n"
  },
  {
    "path": "target/linux/bcm47xx/image/lzma-loader/src/loader.lds.in",
    "content": "OUTPUT_ARCH(mips)\nENTRY(startup)\nSECTIONS {\n\t. = TEXT_START;\n\t.text : {\n\t\t*(.text)\n\t\t*(.rodata)\n\t}\n\n\t.data : {\n\t\t*(.data)\n\t}\n\n\t.bss : {\n\t\t*(.bss)\n\t}\n}\n"
  },
  {
    "path": "target/linux/bcm47xx/image/mips74k.mk",
    "content": "#################################################\n# Subtarget mips74k\n#################################################\n\ndefine Device/asus_rt-ac53u\n  DEVICE_MODEL := RT-AC53U\n  DEVICE_PACKAGES := $(USB2_PACKAGES)\n  $(Device/asus)\n  PRODUCTID := RT-AC53U\nendef\nTARGET_DEVICES += asus_rt-ac53u\n\ndefine Device/asus_rt-ac66u\n  DEVICE_MODEL := RT-AC66U\n  DEVICE_PACKAGES := kmod-b43 $(USB2_PACKAGES)\n  $(Device/asus)\n  PRODUCTID := RT-AC66U\n  DEFAULT := n\nendef\nTARGET_DEVICES += asus_rt-ac66u\n\ndefine Device/asus_rt-n10\n  DEVICE_MODEL := RT-N10\n  DEVICE_PACKAGES := kmod-b43\n  $(Device/asus)\n  PRODUCTID := \"RT-N10      \"\nendef\nTARGET_DEVICES += asus_rt-n10\n\ndefine Device/asus_rt-n10p\n  DEVICE_MODEL := RT-N10P\n  DEVICE_VARIANT := v1\n  DEVICE_PACKAGES := kmod-b43\n  $(Device/asus)\n  PRODUCTID := RT-N10P\nendef\nTARGET_DEVICES += asus_rt-n10p\n\ndefine Device/asus_rt-n10p-v2\n  DEVICE_MODEL := RT-N10P\n  DEVICE_VARIANT := v2\n  $(Device/asus)\n  PRODUCTID := RT-N10PV2\nendef\nTARGET_DEVICES += asus_rt-n10p-v2\n\ndefine Device/asus_rt-n10u\n  DEVICE_MODEL := RT-N10U\n  DEVICE_VARIANT := A\n  DEVICE_PACKAGES := kmod-b43 $(USB2_PACKAGES)\n  $(Device/asus)\n  PRODUCTID := RT-N10U\nendef\nTARGET_DEVICES += asus_rt-n10u\n\ndefine Device/asus_rt-n10u-b\n  DEVICE_MODEL := RT-N10U\n  DEVICE_VARIANT := B\n  DEVICE_PACKAGES := kmod-b43 $(USB2_PACKAGES)\n  $(Device/asus)\n  PRODUCTID := RT-N10U\nendef\nTARGET_DEVICES += asus_rt-n10u-b\n\ndefine Device/asus_rt-n12\n  DEVICE_MODEL := RT-N12\n  DEVICE_VARIANT := A1\n  DEVICE_PACKAGES := kmod-b43\n  $(Device/asus)\n  PRODUCTID := \"RT-N12      \"\nendef\nTARGET_DEVICES += asus_rt-n12\n\ndefine Device/asus_rt-n12-b1\n  DEVICE_MODEL := RT-N12\n  DEVICE_VARIANT := B1\n  $(Device/asus)\n  PRODUCTID := RT-N12B1\nendef\nTARGET_DEVICES += asus_rt-n12-b1\n\ndefine Device/asus_rt-n12-c1\n  DEVICE_MODEL := RT-N12\n  DEVICE_VARIANT := C1\n  $(Device/asus)\n  PRODUCTID := RT-N12C1\nendef\nTARGET_DEVICES += asus_rt-n12-c1\n\ndefine Device/asus_rt-n12-d1\n  DEVICE_MODEL := RT-N12\n  DEVICE_VARIANT := D1\n  $(Device/asus)\n  PRODUCTID := RT-N12D1\nendef\nTARGET_DEVICES += asus_rt-n12-d1\n\ndefine Device/asus_rt-n12hp\n  DEVICE_MODEL := RT-N12HP\n  $(Device/asus)\n  PRODUCTID := RT-N12HP\nendef\nTARGET_DEVICES += asus_rt-n12hp\n\ndefine Device/asus_rt-n14uhp\n  DEVICE_MODEL := RT-N14UHP\n  DEVICE_PACKAGES := kmod-b43 $(USB2_PACKAGES)\n  $(Device/asus)\n  PRODUCTID := RT-N14UHP\nendef\nTARGET_DEVICES += asus_rt-n14uhp\n\ndefine Device/asus_rt-n15u\n  DEVICE_MODEL := RT-N15U\n  DEVICE_PACKAGES := kmod-b43 $(USB2_PACKAGES)\n  $(Device/asus)\n  PRODUCTID := RT-N15U\nendef\nTARGET_DEVICES += asus_rt-n15u\n\ndefine Device/asus_rt-n16\n  DEVICE_MODEL := RT-N16\n  DEVICE_PACKAGES := kmod-b43 $(USB2_PACKAGES)\n  $(Device/asus)\n  PRODUCTID := RT-N16\nendef\nTARGET_DEVICES += asus_rt-n16\n\ndefine Device/asus_rt-n53\n  DEVICE_MODEL := RT-N53\n  DEVICE_PACKAGES := kmod-b43\n  $(Device/asus)\n  PRODUCTID := RT-N53\nendef\nTARGET_DEVICES += asus_rt-n53\n\ndefine Device/asus_rt-n66u\n  DEVICE_MODEL := RT-N66U\n  DEVICE_PACKAGES := kmod-b43 $(USB2_PACKAGES)\n  $(Device/asus)\n  PRODUCTID := RT-N66U\nendef\nTARGET_DEVICES += asus_rt-n66u\n\ndefine Device/asus_rt-n66w\n  DEVICE_MODEL := RT-N66W\n  DEVICE_PACKAGES := kmod-b43 $(USB2_PACKAGES)\n  $(Device/asus)\n  PRODUCTID := RT-N66U\nendef\nTARGET_DEVICES += asus_rt-n66w\n\ndefine Device/linksys_wrt160n-v3\n  DEVICE_MODEL := WRT160N\n  DEVICE_VARIANT := v3\n  DEVICE_PACKAGES := kmod-b43\n  $(Device/linksys)\n  DEVICE_ID := N150\n  VERSION := 3.0.3\n  DEFAULT := n\nendef\nTARGET_DEVICES += linksys_wrt160n-v3\n\ndefine Device/linksys_wrt310n-v2\n  DEVICE_MODEL := WRT310N\n  DEVICE_VARIANT := v2\n  DEVICE_PACKAGES := kmod-b43\n  $(Device/linksys)\n  DEVICE_ID := 310N\n  VERSION := 2.0.1\nendef\nTARGET_DEVICES += linksys_wrt310n-v2\n\ndefine Device/linksys_wrt320n-v1\n  DEVICE_MODEL := WRT320N\n  DEVICE_VARIANT := v1\n  DEVICE_PACKAGES := kmod-b43\n  $(Device/linksys)\n  DEVICE_ID := 320N\n  VERSION := 1.0.5\nendef\nTARGET_DEVICES += linksys_wrt320n-v1\n\ndefine Device/linksys_e900-v1\n  DEVICE_MODEL := E900\n  DEVICE_VARIANT := v1\n  $(Device/linksys)\n  DEVICE_ID := E900\n  VERSION := 1.0.4\nendef\nTARGET_DEVICES += linksys_e900-v1\n\ndefine Device/linksys_e1000\n  DEVICE_MODEL := E1000\n  DEVICE_VARIANT := v1/v2/v2.1\n  DEVICE_PACKAGES := kmod-b43\n  $(Device/linksys)\n  DEVICE_ID := E100\n  VERSION := 1.1.3\nendef\nTARGET_DEVICES += linksys_e1000\n\ndefine Device/linksys_e1200-v1\n  DEVICE_MODEL := E1200\n  DEVICE_VARIANT := v1\n  $(Device/linksys)\n  DEVICE_ID := E120\n  VERSION := 1.0.3\nendef\nTARGET_DEVICES += linksys_e1200-v1\n\ndefine Device/linksys_e1200-v2\n  DEVICE_MODEL := E1200\n  DEVICE_VARIANT := v2\n  $(Device/linksys)\n  DEVICE_ID := E122\n  VERSION := 1.0.4\nendef\nTARGET_DEVICES += linksys_e1200-v2\n\ndefine Device/linksys_e1500-v1\n  DEVICE_MODEL := E1500\n  DEVICE_VARIANT := v1\n  $(Device/linksys)\n  DEVICE_ID := E150\n  VERSION := 1.0.5\nendef\nTARGET_DEVICES += linksys_e1500-v1\n\ndefine Device/linksys_e1550-v1\n  DEVICE_MODEL := E1550\n  DEVICE_VARIANT := v1\n  DEVICE_PACKAGES := kmod-b43 $(USB2_PACKAGES)\n  $(Device/linksys)\n  DEVICE_ID := 1550\n  VERSION := 1.0.3\nendef\nTARGET_DEVICES += linksys_e1550-v1\n\ndefine Device/linksys_e2000-v1\n  DEVICE_MODEL := E2000\n  DEVICE_VARIANT := v1\n  DEVICE_PACKAGES := kmod-b43\n  $(Device/linksys)\n  DEVICE_ID := 32XN\n  VERSION := 1.0.4\nendef\nTARGET_DEVICES += linksys_e2000-v1\n\ndefine Device/linksys_e2500-v1\n  DEVICE_MODEL := E2500\n  DEVICE_VARIANT := v1\n  DEVICE_PACKAGES := kmod-b43\n  $(Device/linksys)\n  DEVICE_ID := E25X\n  VERSION := 1.0.7\nendef\nTARGET_DEVICES += linksys_e2500-v1\n\ndefine Device/linksys_e2500-v2\n  DEVICE_MODEL := E2500\n  DEVICE_VARIANT := v2\n  DEVICE_PACKAGES := kmod-b43\n  $(Device/linksys)\n  DEVICE_ID := E25X\n  VERSION := 2.0.0\nendef\nTARGET_DEVICES += linksys_e2500-v2\n\ndefine Device/linksys_e2500-v2.1\n  DEVICE_MODEL := E2500\n  DEVICE_VARIANT := v2.1\n  DEVICE_PACKAGES := kmod-b43\n  $(Device/linksys)\n  DEVICE_ID := 25RU\n  VERSION := 2.1.0\nendef\nTARGET_DEVICES += linksys_e2500-v2.1\n\ndefine Device/linksys_e2500-v3\n  DEVICE_MODEL := E2500\n  DEVICE_VARIANT := v3\n  DEVICE_PACKAGES := kmod-b43\n  $(Device/linksys)\n  DEVICE_ID := 25V3\n  VERSION := 3.0.0\nendef\nTARGET_DEVICES += linksys_e2500-v3\n\ndefine Device/linksys_e3200-v1\n  DEVICE_MODEL := E3200\n  DEVICE_VARIANT := v1\n  DEVICE_PACKAGES := kmod-b43\n  $(Device/linksys)\n  DEVICE_ID := 3200\n  VERSION := 1.0.1\nendef\nTARGET_DEVICES += linksys_e3200-v1\n\ndefine Device/linksys_e4200-v1\n  DEVICE_MODEL := E4200\n  DEVICE_VARIANT := v1\n  DEVICE_PACKAGES := kmod-b43 $(USB2_PACKAGES)\n  $(Device/linksys)\n  DEVICE_ID := 4200\n  VERSION := 1.0.5\nendef\nTARGET_DEVICES += linksys_e4200-v1\n\ndefine Device/netgear_r6200-v1\n  DEVICE_MODEL := R6200\n  DEVICE_VARIANT := v1\n  DEVICE_PACKAGES := kmod-b43 $(USB2_PACKAGES)\n  $(Device/netgear)\n  NETGEAR_BOARD_ID := U12H192T00_NETGEAR\n  NETGEAR_REGION := 1\nendef\nTARGET_DEVICES += netgear_r6200-v1\n\ndefine Device/netgear_wgr614-v10-na\n  DEVICE_MODEL := WGR614\n  DEVICE_VARIANT := v10 (NA)\n  $(Device/netgear)\n  NETGEAR_BOARD_ID := U12H139T01_NETGEAR\n  NETGEAR_REGION := 2\nendef\nTARGET_DEVICES += netgear_wgr614-v10-na\n\ndefine Device/netgear_wgr614-v10\n  DEVICE_MODEL := WGR614\n  DEVICE_VARIANT := v10\n  $(Device/netgear)\n  NETGEAR_BOARD_ID := U12H139T01_NETGEAR\n  NETGEAR_REGION := 1\nendef\nTARGET_DEVICES += netgear_wgr614-v10\n\ndefine Device/netgear_wn2500rp-v1\n  DEVICE_MODEL := WN2500RP\n  DEVICE_VARIANT := v1\n  DEVICE_PACKAGES := kmod-b43\n  $(Device/netgear)\n  NETGEAR_BOARD_ID := U12H197T00_NETGEAR\n  NETGEAR_REGION := 1\nendef\nTARGET_DEVICES += netgear_wn2500rp-v1\n\ndefine Device/netgear_wn3000rp\n  DEVICE_MODEL := WN3000RP\n  $(Device/netgear)\n  NETGEAR_BOARD_ID := U12H163T01_NETGEAR\n  NETGEAR_REGION := 1\nendef\nTARGET_DEVICES += netgear_wn3000rp\n\ndefine Device/netgear_wndr3400-v1\n  DEVICE_MODEL := WNDR3400\n  DEVICE_VARIANT := v1\n  DEVICE_PACKAGES := kmod-b43 $(USB2_PACKAGES)\n  $(Device/netgear)\n  NETGEAR_BOARD_ID := U12H155T00_NETGEAR\n  NETGEAR_REGION := 2\nendef\nTARGET_DEVICES += netgear_wndr3400-v1\n\ndefine Device/netgear_wndr3400-v2\n  DEVICE_MODEL := WNDR3400\n  DEVICE_VARIANT := v2\n  DEVICE_PACKAGES := kmod-b43 $(USB2_PACKAGES)\n  $(Device/netgear)\n  NETGEAR_BOARD_ID := U12H187T00_NETGEAR\n  NETGEAR_REGION := 2\nendef\nTARGET_DEVICES += netgear_wndr3400-v2\n\ndefine Device/netgear_wndr3400-v3\n  DEVICE_MODEL := WNDR3400\n  DEVICE_VARIANT := v3\n  DEVICE_PACKAGES := kmod-b43 $(USB2_PACKAGES)\n  $(Device/netgear)\n  NETGEAR_BOARD_ID := U12H208T00_NETGEAR\n  NETGEAR_REGION := 1\nendef\nTARGET_DEVICES += netgear_wndr3400-v3\n\ndefine Device/netgear_wndr3700-v3\n  DEVICE_MODEL := WNDR3700\n  DEVICE_VARIANT := v3\n  DEVICE_PACKAGES := kmod-b43 $(USB2_PACKAGES)\n  $(Device/netgear)\n  NETGEAR_BOARD_ID := U12H194T00_NETGEAR\n  NETGEAR_REGION := 2\nendef\nTARGET_DEVICES += netgear_wndr3700-v3\n\ndefine Device/netgear_wndr3400-vcna\n  DEVICE_MODEL := WNDR3400\n  DEVICE_VARIANT := vcna\n  DEVICE_PACKAGES := kmod-b43 $(USB2_PACKAGES)\n  $(Device/netgear)\n  NETGEAR_BOARD_ID := U12H155T01_NETGEAR\n  NETGEAR_REGION := 2\n  DEFAULT := n\nendef\nTARGET_DEVICES += netgear_wndr3400-vcna\n\ndefine Device/netgear_wndr4000\n  DEVICE_MODEL := WNDR4000\n  DEVICE_VARIANT := v1\n  DEVICE_PACKAGES := kmod-b43 $(USB2_PACKAGES)\n  $(Device/netgear)\n  NETGEAR_BOARD_ID := U12H181T00_NETGEAR\n  NETGEAR_REGION := 2\nendef\nTARGET_DEVICES += netgear_wndr4000\n\ndefine Device/netgear_wnr1000-v3\n  DEVICE_MODEL := WNR1000\n  DEVICE_VARIANT := v3\n  $(Device/netgear)\n  NETGEAR_BOARD_ID := U12H139T00_NETGEAR\n  NETGEAR_REGION := 2\nendef\nTARGET_DEVICES += netgear_wnr1000-v3\n\ndefine Device/netgear_wnr2000v2\n  DEVICE_MODEL := WNR2000\n  DEVICE_VARIANT := v2\n  DEVICE_PACKAGES := kmod-b43\n  $(Device/netgear)\n  NETGEAR_BOARD_ID := U12H114T00_NETGEAR\n  NETGEAR_REGION := 2\nendef\nTARGET_DEVICES += netgear_wnr2000v2\n\ndefine Device/netgear_wnr3500l-v1-na\n  DEVICE_MODEL := WNR3500L\n  DEVICE_VARIANT := v1 (NA)\n  DEVICE_PACKAGES := kmod-b43 $(USB2_PACKAGES)\n  $(Device/netgear)\n  NETGEAR_BOARD_ID := U12H136T99_NETGEAR\n  NETGEAR_REGION := 2\nendef\nTARGET_DEVICES += netgear_wnr3500l-v1-na\n\ndefine Device/netgear_wnr3500l-v1\n  DEVICE_MODEL := WNR3500L\n  DEVICE_VARIANT := v1 (ROW)\n  DEVICE_PACKAGES := kmod-b43 $(USB2_PACKAGES)\n  $(Device/netgear)\n  NETGEAR_BOARD_ID := U12H136T99_NETGEAR\n  NETGEAR_REGION := 1\nendef\nTARGET_DEVICES += netgear_wnr3500l-v1\n\ndefine Device/netgear_wnr3500l-v2\n  DEVICE_MODEL := WNR3500L\n  DEVICE_VARIANT := v2\n  DEVICE_PACKAGES := $(USB2_PACKAGES)\n  $(Device/netgear)\n  NETGEAR_BOARD_ID := U12H172T00_NETGEAR\n  NETGEAR_REGION := 1\nendef\nTARGET_DEVICES += netgear_wnr3500l-v2\n\ndefine Device/netgear_wnr3500u\n  DEVICE_MODEL := WNR3500U\n  DEVICE_PACKAGES := $(USB2_PACKAGES)\n  $(Device/netgear)\n  NETGEAR_BOARD_ID := U12H136T00_NETGEAR\n  NETGEAR_REGION := 2\n  DEFAULT := n\nendef\nTARGET_DEVICES += netgear_wnr3500u\n\ndefine Device/netgear_wnr3500-v2\n  DEVICE_MODEL := WNR3500\n  DEVICE_VARIANT := v2\n  DEVICE_PACKAGES := kmod-b43\n  $(Device/netgear)\n  NETGEAR_BOARD_ID := U12H127T00_NETGEAR\n  NETGEAR_REGION := 2\nendef\nTARGET_DEVICES += netgear_wnr3500-v2\n\ndefine Device/netgear_wnr3500-v2-vc\n  DEVICE_MODEL := WNR3500\n  DEVICE_VARIANT := v2 (VC)\n  DEVICE_PACKAGES := kmod-b43\n  $(Device/netgear)\n  NETGEAR_BOARD_ID := U12H127T70_NETGEAR\n  NETGEAR_REGION := 2\n  DEFAULT := n\nendef\nTARGET_DEVICES += netgear_wnr3500-v2-vc\n\nTARGET_DEVICES += standard standard-noloader-nodictionarylzma\n"
  },
  {
    "path": "target/linux/bcm47xx/legacy/config-default",
    "content": "CONFIG_B44=y\nCONFIG_B44_PCI=y\nCONFIG_B44_PCICORE_AUTOSELECT=y\nCONFIG_B44_PCI_AUTOSELECT=y\n# CONFIG_BCM47XX_BCMA is not set\n# CONFIG_BCMA is not set\n# CONFIG_MTD_NAND is not set\n# CONFIG_SSB_DRIVER_GIGE is not set\n"
  },
  {
    "path": "target/linux/bcm47xx/legacy/profiles/100-Broadcom-b43.mk",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2007-2013 OpenWrt.org\n\ndefine Profile/Broadcom-b43\n  NAME:=Broadcom SoC, all Ethernet, BCM43xx WiFi (b43, default)\n  PACKAGES:=kmod-b43 kmod-b43legacy\nendef\n\ndefine Profile/Broadcom-b43/Description\n\tPackage set compatible with hardware any Broadcom BCM47xx or BCM535x\n\tSoC with Broadcom BCM43xx Wifi cards using the mac80211, b43 and\n\tb43legacy drivers and b44, tg3 or bgmac Ethernet driver.\nendef\n\n$(eval $(call Profile,Broadcom-b43))\n\n"
  },
  {
    "path": "target/linux/bcm47xx/legacy/profiles/101-Broadcom-wl.mk",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2010-2013 OpenWrt.org\n\ndefine Profile/Broadcom-wl\n  NAME:=Broadcom SoC, all Ethernet, BCM43xx WiFi (wl, proprietary)\n  PACKAGES:=-wpad-basic-wolfssl kmod-brcm-wl-mini wlc nas\nendef\n\ndefine Profile/Broadcom-wl/Description\n\tPackage set compatible with hardware any Broadcom BCM47xx or BCM535x\n\tSoC with Broadcom BCM43xx Wifi cards using the proprietary Broadcom\n\twireless \"wl\" driver and b44, tg3 or bgmac Ethernet driver.\nendef\n\n$(eval $(call Profile,Broadcom-wl))\n\n"
  },
  {
    "path": "target/linux/bcm47xx/legacy/target.mk",
    "content": "FEATURES += low_mem pcmcia small_flash\nBOARDNAME:=Legacy (BMIPS3300)\n\nDEFAULT_PACKAGES += wpad-basic-wolfssl\n\ndefine Target/Description\n\tBuild firmware for Broadcom BCM47xx and BCM53xx devices with\n\tBMIPS3300 CPU except for BCM4705 SoC.\n\tSupported SoCs: BCM5352E, BCM5354, BCM5365?, BCM4712, BCM4704.\nendef\n"
  },
  {
    "path": "target/linux/bcm47xx/mips74k/config-default",
    "content": "# CONFIG_ADM6996_PHY is not set\n# CONFIG_BCM47XX_SSB is not set\nCONFIG_BGMAC=y\nCONFIG_BGMAC_BCMA=y\nCONFIG_BOUNCE=y\n# CONFIG_CPU_MIPS32_R1 is not set\n# CONFIG_CPU_MIPSR1 is not set\nCONFIG_CPU_MIPS32_R2=y\nCONFIG_CPU_MIPSR2=y\n# CONFIG_FIXED_PHY is not set\n# CONFIG_GPIO_WDT is not set\nCONFIG_HIGHMEM=y\n# CONFIG_SSB is not set\n# CONFIG_SSB_DRIVER_EXTIF is not set\n# CONFIG_SSB_DRIVER_GIGE is not set\n# CONFIG_SSB_DRIVER_MIPS is not set\n# CONFIG_SSB_EMBEDDED is not set\n# CONFIG_SSB_PCICORE_HOSTMODE is not set\n# CONFIG_SSB_SERIAL is not set\n# CONFIG_SSB_SFLASH is not set\n"
  },
  {
    "path": "target/linux/bcm47xx/mips74k/profiles/100-Broadcom-b43.mk",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2014 OpenWrt.org\n\ndefine Profile/Broadcom-mips74k-b43\n  NAME:=Broadcom SoC, BCM43xx WiFi (b43)\n  PACKAGES:=kmod-b43\nendef\n\ndefine Profile/Broadcom-mips74k-b43/Description\n\tPackage set for devices with BCM43xx WiFi including mac80211 and b43\n\tdriver.\nendef\n\n$(eval $(call Profile,Broadcom-mips74k-b43))\n\n"
  },
  {
    "path": "target/linux/bcm47xx/mips74k/profiles/101-Broadcom-brcsmac.mk",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2014 OpenWrt.org\n\ndefine Profile/Broadcom-mips74k-brcmsmac\n  NAME:=Broadcom SoC, BCM43xx WiFi (brcmsmac)\n  PACKAGES:=kmod-brcmsmac\nendef\n\ndefine Profile/Broadcom-mips74k-brcmsmac/Description\n\tPackage set for devices with BCM43xx WiFi including mac80211 and\n\tbrcmsmac driver.\nendef\n\n$(eval $(call Profile,Broadcom-mips74k-brcmsmac))\n\n"
  },
  {
    "path": "target/linux/bcm47xx/mips74k/profiles/102-Broadcom-wl.mk",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2014 OpenWrt.org\n\ndefine Profile/Broadcom-mips74k-wl\n  NAME:=Broadcom SoC, BCM43xx WiFi (proprietary wl)\n  PACKAGES:=-wpad-basic-wolfssl kmod-brcm-wl wlc nas\nendef\n\ndefine Profile/Broadcom-mips74k-wl/Description\n\tPackage set for devices with BCM43xx WiFi including proprietary (and\n\tclosed source) driver \"wl\".\nendef\n\n$(eval $(call Profile,Broadcom-mips74k-wl))\n\n"
  },
  {
    "path": "target/linux/bcm47xx/mips74k/profiles/103-Broadcom-none.mk",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2014 OpenWrt.org\n\ndefine Profile/Broadcom-mips74k-none\n  NAME:=Broadcom SoC, No WiFi\n  PACKAGES:=-wpad-basic-wolfssl\nendef\n\ndefine Profile/Broadcom-mips74k-none/Description\n\tPackage set for devices without a WiFi.\nendef\n\n$(eval $(call Profile,Broadcom-mips74k-none))\n\n"
  },
  {
    "path": "target/linux/bcm47xx/mips74k/target.mk",
    "content": "BOARDNAME:=MIPS 74K\nCPU_TYPE:=74kc\n\nDEFAULT_PACKAGES += wpad-basic-wolfssl\n\ndefine Target/Description\n\tBuild firmware for Broadcom BCM47xx and BCM53xx devices with\n\tMIPS 74K CPU.\nendef\n"
  },
  {
    "path": "target/linux/bcm47xx/modules.mk",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2006-2012 OpenWrt.org\n\ndefine KernelPackage/bgmac\n  TITLE:=Broadcom bgmac driver\n  KCONFIG:=CONFIG_BGMAC CONFIG_BGMAC_BCMA\n  DEPENDS:=@TARGET_bcm47xx @!TARGET_bcm47xx_legacy\n  SUBMENU:=$(NETWORK_DEVICES_MENU)\n  FILES:= \\\n\t$(LINUX_DIR)/drivers/net/ethernet/broadcom/bgmac-bcma.ko \\\n\t$(LINUX_DIR)/drivers/net/ethernet/broadcom/bgmac-bcma-mdio.ko \\\n\t$(LINUX_DIR)/drivers/net/ethernet/broadcom/bgmac.ko\n  AUTOLOAD:=$(call AutoProbe,bgmac-bcma)\nendef\n\ndefine KernelPackage/bgmac/description\n Kernel modules for Broadcom bgmac Ethernet adapters.\nendef\n\n$(eval $(call KernelPackage,bgmac))\n"
  },
  {
    "path": "target/linux/bcm47xx/patches-5.10/159-cpu_fixes.patch",
    "content": "--- a/arch/mips/include/asm/r4kcache.h\n+++ b/arch/mips/include/asm/r4kcache.h\n@@ -28,6 +28,38 @@\n extern void (*r4k_blast_dcache)(void);\n extern void (*r4k_blast_icache)(void);\n \n+#if defined(CONFIG_BCM47XX) && !defined(CONFIG_CPU_MIPS32_R2)\n+#include <asm/paccess.h>\n+#include <linux/ssb/ssb.h>\n+#define BCM4710_DUMMY_RREG() bcm4710_dummy_rreg()\n+\n+static inline unsigned long bcm4710_dummy_rreg(void)\n+{\n+      return *(volatile unsigned long *)(KSEG1ADDR(SSB_ENUM_BASE));\n+}\n+\n+#define BCM4710_FILL_TLB(addr) bcm4710_fill_tlb((void *)(addr))\n+\n+static inline unsigned long bcm4710_fill_tlb(void *addr)\n+{\n+      return *(unsigned long *)addr;\n+}\n+\n+#define BCM4710_PROTECTED_FILL_TLB(addr) bcm4710_protected_fill_tlb((void *)(addr))\n+\n+static inline void bcm4710_protected_fill_tlb(void *addr)\n+{\n+      unsigned long x;\n+      get_dbe(x, (unsigned long *)addr);;\n+}\n+\n+#else\n+#define BCM4710_DUMMY_RREG()\n+\n+#define BCM4710_FILL_TLB(addr)\n+#define BCM4710_PROTECTED_FILL_TLB(addr)\n+#endif\n+\n /*\n  * This macro return a properly sign-extended address suitable as base address\n  * for indexed cache operations.  Two issues here:\n@@ -61,6 +93,7 @@ static inline void flush_icache_line_ind\n \n static inline void flush_dcache_line_indexed(unsigned long addr)\n {\n+\tBCM4710_DUMMY_RREG();\n \tcache_op(Index_Writeback_Inv_D, addr);\n }\n \n@@ -84,11 +117,13 @@ static inline void flush_icache_line(uns\n \n static inline void flush_dcache_line(unsigned long addr)\n {\n+\tBCM4710_DUMMY_RREG();\n \tcache_op(Hit_Writeback_Inv_D, addr);\n }\n \n static inline void invalidate_dcache_line(unsigned long addr)\n {\n+\tBCM4710_DUMMY_RREG();\n \tcache_op(Hit_Invalidate_D, addr);\n }\n \n@@ -161,6 +196,7 @@ static inline int protected_flush_icache\n #ifdef CONFIG_EVA\n \t\treturn protected_cachee_op(Hit_Invalidate_I, addr);\n #else\n+\t\tBCM4710_DUMMY_RREG();\n \t\treturn protected_cache_op(Hit_Invalidate_I, addr);\n #endif\n \t}\n@@ -174,6 +210,7 @@ static inline int protected_flush_icache\n  */\n static inline int protected_writeback_dcache_line(unsigned long addr)\n {\n+\tBCM4710_DUMMY_RREG();\n #ifdef CONFIG_EVA\n \treturn protected_cachee_op(Hit_Writeback_Inv_D, addr);\n #else\n@@ -203,8 +240,51 @@ static inline void invalidate_tcache_pag\n \tunroll(times, _cache_op, insn, op, (addr) + (i++ * (lsize)));\t\\\n } while (0)\n \n+static inline void blast_dcache(void)\n+{\n+\tunsigned long start = KSEG0;\n+\tunsigned long dcache_size = current_cpu_data.dcache.waysize * current_cpu_data.dcache.ways;\n+\tunsigned long end = (start + dcache_size);\n+\n+\tdo {\n+\t\tBCM4710_DUMMY_RREG();\n+\t\tcache_op(Index_Writeback_Inv_D, start);\n+\t\tstart += current_cpu_data.dcache.linesz;\n+\t} while(start < end);\n+}\n+\n+static inline void blast_dcache_page(unsigned long page)\n+{\n+\tunsigned long start = page;\n+\tunsigned long end = start + PAGE_SIZE;\n+\n+\tBCM4710_FILL_TLB(start);\n+\tdo {\n+\t\tBCM4710_DUMMY_RREG();\n+\t\tcache_op(Hit_Writeback_Inv_D, start);\n+\t\tstart += current_cpu_data.dcache.linesz;\n+\t} while(start < end);\n+}\n+\n+static inline void blast_dcache_page_indexed(unsigned long page)\n+{\n+\tunsigned long start = page;\n+\tunsigned long end = start + PAGE_SIZE;\n+\tunsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit;\n+\tunsigned long ws_end = current_cpu_data.dcache.ways <<\n+\t                       current_cpu_data.dcache.waybit;\n+\tunsigned long ws, addr;\n+\tfor (ws = 0; ws < ws_end; ws += ws_inc) {\n+\t\tstart = page + ws;\n+\t\tfor (addr = start; addr < end; addr += current_cpu_data.dcache.linesz) {\n+\t\t\tBCM4710_DUMMY_RREG();\n+\t\t\tcache_op(Index_Writeback_Inv_D, addr);\n+\t\t}\n+\t}\n+}\n+\n /* build blast_xxx, blast_xxx_page, blast_xxx_page_indexed */\n-#define __BUILD_BLAST_CACHE(pfx, desc, indexop, hitop, lsize, extra)\t\\\n+#define __BUILD_BLAST_CACHE(pfx, desc, indexop, hitop, lsize, extra, war) \\\n static inline void extra##blast_##pfx##cache##lsize(void)\t\t\\\n {\t\t\t\t\t\t\t\t\t\\\n \tunsigned long start = INDEX_BASE;\t\t\t\t\\\n@@ -214,6 +294,7 @@ static inline void extra##blast_##pfx##c\n \t\t\t       current_cpu_data.desc.waybit;\t\t\\\n \tunsigned long ws, addr;\t\t\t\t\t\t\\\n \t\t\t\t\t\t\t\t\t\\\n+\twar\t\t\t\t\t\t\t\t\\\n \tfor (ws = 0; ws < ws_end; ws += ws_inc)\t\t\t\t\\\n \t\tfor (addr = start; addr < end; addr += lsize * 32)\t\\\n \t\t\tcache_unroll(32, kernel_cache, indexop,\t\t\\\n@@ -225,6 +306,7 @@ static inline void extra##blast_##pfx##c\n \tunsigned long start = page;\t\t\t\t\t\\\n \tunsigned long end = page + PAGE_SIZE;\t\t\t\t\\\n \t\t\t\t\t\t\t\t\t\\\n+\twar\t\t\t\t\t\t\t\t\\\n \tdo {\t\t\t\t\t\t\t\t\\\n \t\tcache_unroll(32, kernel_cache, hitop, start, lsize);\t\\\n \t\tstart += lsize * 32;\t\t\t\t\t\\\n@@ -241,32 +323,33 @@ static inline void extra##blast_##pfx##c\n \t\t\t       current_cpu_data.desc.waybit;\t\t\\\n \tunsigned long ws, addr;\t\t\t\t\t\t\\\n \t\t\t\t\t\t\t\t\t\\\n+\twar\t\t\t\t\t\t\t\t\\\n \tfor (ws = 0; ws < ws_end; ws += ws_inc)\t\t\t\t\\\n \t\tfor (addr = start; addr < end; addr += lsize * 32)\t\\\n \t\t\tcache_unroll(32, kernel_cache, indexop,\t\t\\\n \t\t\t\t     addr | ws, lsize);\t\t\t\\\n }\n \n-__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16, )\n-__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16, )\n-__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16, )\n-__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32, )\n-__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32, )\n-__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I_Loongson2, 32, loongson2_)\n-__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32, )\n-__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 64, )\n-__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64, )\n-__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64, )\n-__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 128, )\n-__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 128, )\n-__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128, )\n-\n-__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 16, )\n-__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 32, )\n-__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 16, )\n-__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 32, )\n-__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 64, )\n-__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 128, )\n+__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16, , )\n+__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16, , BCM4710_FILL_TLB(start);)\n+__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16, , )\n+__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32, , )\n+__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32, , BCM4710_FILL_TLB(start);)\n+__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I_Loongson2, 32, loongson2_, BCM4710_FILL_TLB(start);)\n+__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32, , )\n+__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 64, , )\n+__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64, , BCM4710_FILL_TLB(start);)\n+__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64, , )\n+__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 128, , )\n+__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 128, , )\n+__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128, , )\n+\n+__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 16, , )\n+__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 32, , )\n+__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 16, , )\n+__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 32, , )\n+__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 64, , )\n+__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 128, , )\n \n #define __BUILD_BLAST_USER_CACHE(pfx, desc, indexop, hitop, lsize) \\\n static inline void blast_##pfx##cache##lsize##_user_page(unsigned long page) \\\n@@ -291,58 +374,29 @@ __BUILD_BLAST_USER_CACHE(d, dcache, Inde\n __BUILD_BLAST_USER_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64)\n \n /* build blast_xxx_range, protected_blast_xxx_range */\n-#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot, extra)\t\\\n+#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot, extra, war, war2)\t\\\n static inline void prot##extra##blast_##pfx##cache##_range(unsigned long start, \\\n \t\t\t\t\t\t    unsigned long end)\t\\\n {\t\t\t\t\t\t\t\t\t\\\n \tunsigned long lsize = cpu_##desc##_line_size();\t\t\t\\\n-\tunsigned long lsize_2 = lsize * 2;\t\t\t\t\\\n-\tunsigned long lsize_3 = lsize * 3;\t\t\t\t\\\n-\tunsigned long lsize_4 = lsize * 4;\t\t\t\t\\\n-\tunsigned long lsize_5 = lsize * 5;\t\t\t\t\\\n-\tunsigned long lsize_6 = lsize * 6;\t\t\t\t\\\n-\tunsigned long lsize_7 = lsize * 7;\t\t\t\t\\\n-\tunsigned long lsize_8 = lsize * 8;\t\t\t\t\\\n \tunsigned long addr = start & ~(lsize - 1);\t\t\t\\\n-\tunsigned long aend = (end + lsize - 1) & ~(lsize - 1);\t\t\\\n-\tint lines = (aend - addr) / lsize;\t\t\t\t\\\n-\t\t\t\t\t\t\t\t\t\\\n-\twhile (lines >= 8) {\t\t\t\t\t\t\\\n-\t\tprot##cache_op(hitop, addr);\t\t\t\t\\\n-\t\tprot##cache_op(hitop, addr + lsize);\t\t\t\\\n-\t\tprot##cache_op(hitop, addr + lsize_2);\t\t\t\\\n-\t\tprot##cache_op(hitop, addr + lsize_3);\t\t\t\\\n-\t\tprot##cache_op(hitop, addr + lsize_4);\t\t\t\\\n-\t\tprot##cache_op(hitop, addr + lsize_5);\t\t\t\\\n-\t\tprot##cache_op(hitop, addr + lsize_6);\t\t\t\\\n-\t\tprot##cache_op(hitop, addr + lsize_7);\t\t\t\\\n-\t\taddr += lsize_8;\t\t\t\t\t\\\n-\t\tlines -= 8;\t\t\t\t\t\t\\\n-\t}\t\t\t\t\t\t\t\t\\\n-\t\t\t\t\t\t\t\t\t\\\n-\tif (lines & 0x4) {\t\t\t\t\t\t\\\n-\t\tprot##cache_op(hitop, addr);\t\t\t\t\\\n-\t\tprot##cache_op(hitop, addr + lsize);\t\t\t\\\n-\t\tprot##cache_op(hitop, addr + lsize_2);\t\t\t\\\n-\t\tprot##cache_op(hitop, addr + lsize_3);\t\t\t\\\n-\t\taddr += lsize_4;\t\t\t\t\t\\\n-\t}\t\t\t\t\t\t\t\t\\\n+\tunsigned long aend = (end - 1) & ~(lsize - 1);\t\t\t\\\n \t\t\t\t\t\t\t\t\t\\\n-\tif (lines & 0x2) {\t\t\t\t\t\t\\\n-\t\tprot##cache_op(hitop, addr);\t\t\t\t\\\n-\t\tprot##cache_op(hitop, addr + lsize);\t\t\t\\\n-\t\taddr += lsize_2;\t\t\t\t\t\\\n-\t}\t\t\t\t\t\t\t\t\\\n+\twar\t\t\t\t\t\t\t\t\\\n \t\t\t\t\t\t\t\t\t\\\n-\tif (lines & 0x1) {\t\t\t\t\t\t\\\n+\twhile (1) {\t\t\t\t\t\t\t\\\n+\t\twar2\t\t\t\t\t\t\t\\\n \t\tprot##cache_op(hitop, addr);\t\t\t\t\\\n+\t\tif (addr == aend)\t\t\t\t\t\\\n+\t\t\tbreak;\t\t\t\t\t\t\\\n+\t\taddr += lsize;\t\t\t\t\t\t\\\n \t}\t\t\t\t\t\t\t\t\\\n }\n \n #ifndef CONFIG_EVA\n \n-__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_, )\n-__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_, )\n+__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_, , BCM4710_PROTECTED_FILL_TLB(addr); BCM4710_PROTECTED_FILL_TLB(aend);, BCM4710_DUMMY_RREG();)\n+__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_, , , )\n \n #else\n \n@@ -376,15 +430,15 @@ __BUILD_PROT_BLAST_CACHE_RANGE(d, dcache\n __BUILD_PROT_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I)\n \n #endif\n-__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_, )\n+__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_, , , )\n __BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I_Loongson2, \\\n-\tprotected_, loongson2_)\n-__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, , )\n-__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, , )\n-__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, , )\n+\tprotected_, loongson2_, , )\n+__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, , , BCM4710_FILL_TLB(addr); BCM4710_FILL_TLB(aend);, BCM4710_DUMMY_RREG();)\n+__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, , , , )\n+__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, , , , )\n /* blast_inv_dcache_range */\n-__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, , )\n-__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD, , )\n+__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, , , , BCM4710_DUMMY_RREG();)\n+__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD, , , , )\n \n /* Currently, this is very specific to Loongson-3 */\n #define __BUILD_BLAST_CACHE_NODE(pfx, desc, indexop, hitop, lsize)\t\\\n--- a/arch/mips/include/asm/stackframe.h\n+++ b/arch/mips/include/asm/stackframe.h\n@@ -429,6 +429,10 @@\n #else\n \t\t.set\tpush\n \t\t.set\tarch=r4000\n+#ifdef CONFIG_BCM47XX\n+\t\tnop\n+\t\tnop\n+#endif\n \t\teret\n \t\t.set\tpop\n #endif\n--- a/arch/mips/kernel/genex.S\n+++ b/arch/mips/kernel/genex.S\n@@ -22,6 +22,19 @@\n #include <asm/war.h>\n #include <asm/thread_info.h>\n \n+#ifdef CONFIG_BCM47XX\n+# ifdef eret\n+#  undef eret\n+# endif\n+# define eret \t\t\t\t\t\\\n+\t.set push;\t\t\t\t\\\n+\t.set noreorder;\t\t\t\t\\\n+\t nop; \t\t\t\t\t\\\n+\t nop;\t\t\t\t\t\\\n+\t eret;\t\t\t\t\t\\\n+\t.set pop;\n+#endif\n+\n \t__INIT\n \n /*\n@@ -33,6 +46,9 @@\n NESTED(except_vec3_generic, 0, sp)\n \t.set\tpush\n \t.set\tnoat\n+#ifdef CONFIG_BCM47XX\n+\tnop\n+#endif\n \tmfc0\tk1, CP0_CAUSE\n \tandi\tk1, k1, 0x7c\n #ifdef CONFIG_64BIT\n@@ -53,6 +69,9 @@ NESTED(except_vec3_r4000, 0, sp)\n \t.set\tpush\n \t.set\tarch=r4000\n \t.set\tnoat\n+#ifdef CONFIG_BCM47XX\n+\tnop\n+#endif\n \tmfc0\tk1, CP0_CAUSE\n \tli\tk0, 31<<2\n \tandi\tk1, k1, 0x7c\n--- a/arch/mips/mm/c-r4k.c\n+++ b/arch/mips/mm/c-r4k.c\n@@ -38,6 +38,9 @@\n #include <asm/dma-coherence.h>\n #include <asm/mips-cps.h>\n \n+/* For enabling BCM4710 cache workarounds */\n+static int bcm4710 = 0;\n+\n /*\n  * Bits describing what cache ops an SMP callback function may perform.\n  *\n@@ -190,6 +193,9 @@ static void r4k_blast_dcache_user_page_s\n {\n \tunsigned long  dc_lsize = cpu_dcache_line_size();\n \n+\tif (bcm4710)\n+\t\tr4k_blast_dcache_page = blast_dcache_page;\n+\telse\n \tif (dc_lsize == 0)\n \t\tr4k_blast_dcache_user_page = (void *)cache_noop;\n \telse if (dc_lsize == 16)\n@@ -208,6 +214,9 @@ static void r4k_blast_dcache_page_indexe\n {\n \tunsigned long dc_lsize = cpu_dcache_line_size();\n \n+\tif (bcm4710)\n+\t\tr4k_blast_dcache_page_indexed = blast_dcache_page_indexed;\n+\telse\n \tif (dc_lsize == 0)\n \t\tr4k_blast_dcache_page_indexed = (void *)cache_noop;\n \telse if (dc_lsize == 16)\n@@ -227,6 +236,9 @@ static void r4k_blast_dcache_setup(void)\n {\n \tunsigned long dc_lsize = cpu_dcache_line_size();\n \n+\tif (bcm4710)\n+\t\tr4k_blast_dcache = blast_dcache;\n+\telse\n \tif (dc_lsize == 0)\n \t\tr4k_blast_dcache = (void *)cache_noop;\n \telse if (dc_lsize == 16)\n@@ -1818,6 +1830,17 @@ static void coherency_setup(void)\n \t * silly idea of putting something else there ...\n \t */\n \tswitch (current_cpu_type()) {\n+\tcase CPU_BMIPS3300:\n+\t\t{\n+\t\t\tu32 cm;\n+\t\t\tcm = read_c0_diag();\n+\t\t\t/* Enable icache */\n+\t\t\tcm |= (1 << 31);\n+\t\t\t/* Enable dcache */\n+\t\t\tcm |= (1 << 30);\n+\t\t\twrite_c0_diag(cm);\n+\t\t}\n+\t\tbreak;\n \tcase CPU_R4000PC:\n \tcase CPU_R4000SC:\n \tcase CPU_R4000MC:\n@@ -1864,6 +1887,15 @@ void r4k_cache_init(void)\n \textern void build_copy_page(void);\n \tstruct cpuinfo_mips *c = &current_cpu_data;\n \n+\t/* Check if special workarounds are required */\n+#if defined(CONFIG_BCM47XX) && !defined(CONFIG_CPU_MIPS32_R2)\n+\tif (current_cpu_data.cputype == CPU_BMIPS32 && (current_cpu_data.processor_id & 0xff) == 0) {\n+\t\tprintk(\"Enabling BCM4710A0 cache workarounds.\\n\");\n+\t\tbcm4710 = 1;\n+\t} else\n+#endif\n+\t\tbcm4710 = 0;\n+\n \tprobe_pcache();\n \tprobe_vcache();\n \tsetup_scache();\n@@ -1940,7 +1972,15 @@ void r4k_cache_init(void)\n \t */\n \tlocal_r4k___flush_cache_all(NULL);\n \n+#ifdef CONFIG_BCM47XX\n+\t{\n+\t\tstatic void (*_coherency_setup)(void);\n+\t\t_coherency_setup = (void (*)(void)) KSEG1ADDR(coherency_setup);\n+\t\t_coherency_setup();\n+\t}\n+#else\n \tcoherency_setup();\n+#endif\n \tboard_cache_error_setup = r4k_cache_error_setup;\n \n \t/*\n--- a/arch/mips/mm/tlbex.c\n+++ b/arch/mips/mm/tlbex.c\n@@ -984,6 +984,9 @@ void build_get_pgde32(u32 **p, unsigned\n \t\tuasm_i_srl(p, ptr, ptr, SMP_CPUID_PTRSHIFT);\n \t\tuasm_i_addu(p, ptr, tmp, ptr);\n #else\n+#ifdef CONFIG_BCM47XX\n+\t\tuasm_i_nop(p);\n+#endif\n \t\tUASM_i_LA_mostly(p, ptr, pgdc);\n #endif\n \t\tuasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */\n@@ -1345,6 +1348,9 @@ static void build_r4000_tlb_refill_handl\n #ifdef CONFIG_64BIT\n \t\tbuild_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */\n #else\n+# ifdef CONFIG_BCM47XX\n+\t\tuasm_i_nop(&p);\n+# endif\n \t\tbuild_get_pgde32(&p, K0, K1); /* get pgd in K1 */\n #endif\n \n@@ -1356,6 +1362,9 @@ static void build_r4000_tlb_refill_handl\n \t\tbuild_update_entries(&p, K0, K1);\n \t\tbuild_tlb_write_entry(&p, &l, &r, tlb_random);\n \t\tuasm_l_leave(&l, p);\n+#ifdef CONFIG_BCM47XX\n+\t\tuasm_i_nop(&p);\n+#endif\n \t\tuasm_i_eret(&p); /* return from trap */\n \t}\n #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT\n@@ -2056,6 +2065,9 @@ build_r4000_tlbchange_handler_head(u32 *\n #ifdef CONFIG_64BIT\n \tbuild_get_pmde64(p, l, r, wr.r1, wr.r2); /* get pmd in ptr */\n #else\n+# ifdef CONFIG_BCM47XX\n+\tuasm_i_nop(p);\n+# endif\n \tbuild_get_pgde32(p, wr.r1, wr.r2); /* get pgd in ptr */\n #endif\n \n@@ -2102,6 +2114,9 @@ build_r4000_tlbchange_handler_tail(u32 *\n \tbuild_tlb_write_entry(p, l, r, tlb_indexed);\n \tuasm_l_leave(l, *p);\n \tbuild_restore_work_registers(p);\n+#ifdef CONFIG_BCM47XX\n+\tuasm_i_nop(p);\n+#endif\n \tuasm_i_eret(p); /* return from trap */\n \n #ifdef CONFIG_64BIT\n"
  },
  {
    "path": "target/linux/bcm47xx/patches-5.10/160-kmap_coherent.patch",
    "content": "From: Jeff Hansen <jhansen@cardaccess-inc.com>\nSubject: [PATCH] kmap_coherent\n\nOn ASUS WL-500gP there are some \"Data bus error\"s when executing simple\ncommands liks \"ps\" or \"cat /proc/1/cmdline\".\n\nThis fixes OpenWrt ticket #1485: https://dev.openwrt.org/ticket/1485\n---\n--- a/arch/mips/include/asm/cpu-features.h\n+++ b/arch/mips/include/asm/cpu-features.h\n@@ -242,6 +242,9 @@\n #ifndef cpu_has_pindexed_dcache\n #define cpu_has_pindexed_dcache\t(cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX)\n #endif\n+#ifndef cpu_use_kmap_coherent\n+#define cpu_use_kmap_coherent 1\n+#endif\n \n /*\n  * I-Cache snoops remote store.\t This only matters on SMP.  Some multiprocessors\n--- a/arch/mips/include/asm/mach-bcm47xx/cpu-feature-overrides.h\n+++ b/arch/mips/include/asm/mach-bcm47xx/cpu-feature-overrides.h\n@@ -80,4 +80,6 @@\n #define cpu_scache_line_size()\t\t0\n #define cpu_has_vz\t\t\t0\n \n+#define cpu_use_kmap_coherent\t\t0\n+\n #endif /* __ASM_MACH_BCM47XX_CPU_FEATURE_OVERRIDES_H */\n--- a/arch/mips/mm/c-r4k.c\n+++ b/arch/mips/mm/c-r4k.c\n@@ -699,7 +699,7 @@ static inline void local_r4k_flush_cache\n \t\tmap_coherent = (cpu_has_dc_aliases &&\n \t\t\t\tpage_mapcount(page) &&\n \t\t\t\t!Page_dcache_dirty(page));\n-\t\tif (map_coherent)\n+\t\tif (map_coherent && cpu_use_kmap_coherent)\n \t\t\tvaddr = kmap_coherent(page, addr);\n \t\telse\n \t\t\tvaddr = kmap_atomic(page);\n@@ -721,7 +721,7 @@ static inline void local_r4k_flush_cache\n \t}\n \n \tif (vaddr) {\n-\t\tif (map_coherent)\n+\t\tif (map_coherent && cpu_use_kmap_coherent)\n \t\t\tkunmap_coherent();\n \t\telse\n \t\t\tkunmap_atomic(vaddr);\n--- a/arch/mips/mm/init.c\n+++ b/arch/mips/mm/init.c\n@@ -173,7 +173,7 @@ void copy_user_highpage(struct page *to,\n \tvoid *vfrom, *vto;\n \n \tvto = kmap_atomic(to);\n-\tif (cpu_has_dc_aliases &&\n+\tif (cpu_has_dc_aliases && cpu_use_kmap_coherent &&\n \t    page_mapcount(from) && !Page_dcache_dirty(from)) {\n \t\tvfrom = kmap_coherent(from, vaddr);\n \t\tcopy_page(vto, vfrom);\n@@ -195,7 +195,7 @@ void copy_to_user_page(struct vm_area_st\n \tstruct page *page, unsigned long vaddr, void *dst, const void *src,\n \tunsigned long len)\n {\n-\tif (cpu_has_dc_aliases &&\n+\tif (cpu_has_dc_aliases && cpu_use_kmap_coherent &&\n \t    page_mapcount(page) && !Page_dcache_dirty(page)) {\n \t\tvoid *vto = kmap_coherent(page, vaddr) + (vaddr & ~PAGE_MASK);\n \t\tmemcpy(vto, src, len);\n@@ -213,7 +213,7 @@ void copy_from_user_page(struct vm_area_\n \tstruct page *page, unsigned long vaddr, void *dst, const void *src,\n \tunsigned long len)\n {\n-\tif (cpu_has_dc_aliases &&\n+\tif (cpu_has_dc_aliases && cpu_use_kmap_coherent &&\n \t    page_mapcount(page) && !Page_dcache_dirty(page)) {\n \t\tvoid *vfrom = kmap_coherent(page, vaddr) + (vaddr & ~PAGE_MASK);\n \t\tmemcpy(dst, vfrom, len);\n"
  },
  {
    "path": "target/linux/bcm47xx/patches-5.10/209-b44-register-adm-switch.patch",
    "content": "From b36f694256f41bc71571f467646d015dda128d14 Mon Sep 17 00:00:00 2001\nFrom: Hauke Mehrtens <hauke@hauke-m.de>\nDate: Sat, 9 Nov 2013 17:03:59 +0100\nSubject: [PATCH 210/210] b44: register adm switch\n\n---\n drivers/net/ethernet/broadcom/b44.c |   57 +++++++++++++++++++++++++++++++++++\n drivers/net/ethernet/broadcom/b44.h |    3 ++\n 2 files changed, 60 insertions(+)\n\n--- a/drivers/net/ethernet/broadcom/b44.c\n+++ b/drivers/net/ethernet/broadcom/b44.c\n@@ -31,6 +31,8 @@\n #include <linux/ssb/ssb.h>\n #include <linux/slab.h>\n #include <linux/phy.h>\n+#include <linux/platform_device.h>\n+#include <linux/platform_data/adm6996-gpio.h>\n \n #include <linux/uaccess.h>\n #include <asm/io.h>\n@@ -2243,6 +2245,69 @@ static void b44_adjust_link(struct net_d\n \t}\n }\n \n+#ifdef CONFIG_BCM47XX\n+static int b44_register_adm_switch(struct b44 *bp)\n+{\n+\tint gpio;\n+\tstruct platform_device *pdev;\n+\tstruct adm6996_gpio_platform_data adm_data = {0};\n+\tstruct platform_device_info info = {0};\n+\n+\tadm_data.model = ADM6996L;\n+\tgpio = bcm47xx_nvram_gpio_pin(\"adm_eecs\");\n+\tif (gpio >= 0)\n+\t\tadm_data.eecs = gpio;\n+\telse\n+\t\tadm_data.eecs = 2;\n+\n+\tgpio = bcm47xx_nvram_gpio_pin(\"adm_eesk\");\n+\tif (gpio >= 0)\n+\t\tadm_data.eesk = gpio;\n+\telse\n+\t\tadm_data.eesk = 3;\n+\n+\tgpio = bcm47xx_nvram_gpio_pin(\"adm_eedi\");\n+\tif (gpio >= 0)\n+\t\tadm_data.eedi = gpio;\n+\telse\n+\t\tadm_data.eedi = 4;\n+\n+\t/*\n+\t * We ignore the \"adm_rc\" GPIO here. The driver does not use it,\n+\t * and it conflicts with the Reset button GPIO on the Linksys WRT54GSv1.\n+\t */\n+\n+\tinfo.parent = bp->sdev->dev;\n+\tinfo.name = \"adm6996_gpio\";\n+\tinfo.id = -1;\n+\tinfo.data = &adm_data;\n+\tinfo.size_data = sizeof(adm_data);\n+\n+\tif (!bp->adm_switch) {\n+\t\tpdev = platform_device_register_full(&info);\n+\t\tif (IS_ERR(pdev))\n+\t\t\treturn PTR_ERR(pdev);\n+\n+\t\tbp->adm_switch = pdev;\n+\t}\n+\treturn 0;\n+}\n+static void b44_unregister_adm_switch(struct b44 *bp)\n+{\n+\tif (bp->adm_switch)\n+\t\tplatform_device_unregister(bp->adm_switch);\n+}\n+#else\n+static int b44_register_adm_switch(struct b44 *bp)\n+{\n+\treturn 0;\n+}\n+static void b44_unregister_adm_switch(struct b44 *bp)\n+{\n+\n+}\n+#endif /* CONFIG_BCM47XX */\n+\n static int b44_register_phy_one(struct b44 *bp)\n {\n \t__ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };\n@@ -2279,6 +2344,9 @@ static int b44_register_phy_one(struct b\n \tif (!mdiobus_is_registered_device(bp->mii_bus, bp->phy_addr) &&\n \t    (sprom->boardflags_lo & (B44_BOARDFLAG_ROBO | B44_BOARDFLAG_ADM))) {\n \n+\t\tif (sprom->boardflags_lo & B44_BOARDFLAG_ADM)\n+\t\t\tb44_register_adm_switch(bp);\n+\n \t\tdev_info(sdev->dev,\n \t\t\t \"could not find PHY at %i, use fixed one\\n\",\n \t\t\t bp->phy_addr);\n@@ -2473,6 +2541,7 @@ static void b44_remove_one(struct ssb_de\n \tunregister_netdev(dev);\n \tif (bp->flags & B44_FLAG_EXTERNAL_PHY)\n \t\tb44_unregister_phy_one(bp);\n+\tb44_unregister_adm_switch(bp);\n \tssb_device_disable(sdev, 0);\n \tssb_bus_may_powerdown(sdev->bus);\n \tnetif_napi_del(&bp->napi);\n--- a/drivers/net/ethernet/broadcom/b44.h\n+++ b/drivers/net/ethernet/broadcom/b44.h\n@@ -408,6 +408,9 @@ struct b44 {\n \tstruct mii_bus\t\t*mii_bus;\n \tint\t\t\told_link;\n \tstruct mii_if_info\tmii_if;\n+\n+\t/* platform device for associated switch */\n+\tstruct platform_device *adm_switch;\n };\n \n #endif /* _B44_H */\n"
  },
  {
    "path": "target/linux/bcm47xx/patches-5.10/210-b44_phy_fix.patch",
    "content": "--- a/drivers/net/ethernet/broadcom/b44.c\n+++ b/drivers/net/ethernet/broadcom/b44.c\n@@ -429,10 +429,34 @@ static void b44_wap54g10_workaround(stru\n error:\n \tpr_warn(\"PHY: cannot reset MII transceiver isolate bit\\n\");\n }\n+\n+static void b44_bcm47xx_workarounds(struct b44 *bp)\n+{\n+\tchar buf[20];\n+\tstruct ssb_device *sdev = bp->sdev;\n+\n+\t/* Toshiba WRC-1000, Siemens SE505 v1, Askey RT-210W, RT-220W */\n+\tif (sdev->bus->sprom.board_num == 100) {\n+\t\tbp->phy_addr = B44_PHY_ADDR_NO_LOCAL_PHY;\n+\t} else {\n+\t\t/* WL-HDD */\n+\t\tif (bcm47xx_nvram_getenv(\"hardware_version\", buf, sizeof(buf)) >= 0 &&\n+\t\t    !strncmp(buf, \"WL300-\", strlen(\"WL300-\"))) {\n+\t\t\tif (sdev->bus->sprom.et0phyaddr == 0 &&\n+\t\t\t    sdev->bus->sprom.et1phyaddr == 1)\n+\t\t\t\tbp->phy_addr = B44_PHY_ADDR_NO_LOCAL_PHY;\n+\t\t}\n+\t}\n+\treturn;\n+}\n #else\n static inline void b44_wap54g10_workaround(struct b44 *bp)\n {\n }\n+\n+static inline void b44_bcm47xx_workarounds(struct b44 *bp)\n+{\n+}\n #endif\n \n static int b44_setup_phy(struct b44 *bp)\n@@ -441,6 +465,7 @@ static int b44_setup_phy(struct b44 *bp)\n \tint err;\n \n \tb44_wap54g10_workaround(bp);\n+\tb44_bcm47xx_workarounds(bp);\n \n \tif (bp->flags & B44_FLAG_EXTERNAL_PHY)\n \t\treturn 0;\n@@ -2173,6 +2198,8 @@ static int b44_get_invariants(struct b44\n \t * valid PHY address. */\n \tbp->phy_addr &= 0x1F;\n \n+\tb44_bcm47xx_workarounds(bp);\n+\n \tmemcpy(bp->dev->dev_addr, addr, ETH_ALEN);\n \n \tif (!is_valid_ether_addr(&bp->dev->dev_addr[0])){\n"
  },
  {
    "path": "target/linux/bcm47xx/patches-5.10/280-activate_ssb_support_in_usb.patch",
    "content": "This prevents the options from being delete with make kernel_oldconfig.\n---\n drivers/ssb/Kconfig |    2 ++\n 1 file changed, 2 insertions(+)\n\n--- a/drivers/bcma/Kconfig\n+++ b/drivers/bcma/Kconfig\n@@ -32,6 +32,7 @@ config BCMA_HOST_PCI\n config BCMA_HOST_SOC\n \tbool \"Support for BCMA in a SoC\"\n \tdepends on HAS_IOMEM\n+\tselect USB_HCD_BCMA if USB_EHCI_HCD || USB_OHCI_HCD\n \thelp\n \t  Host interface for a Broadcom AIX bus directly mapped into\n \t  the memory. This only works with the Broadcom SoCs from the\n--- a/drivers/ssb/Kconfig\n+++ b/drivers/ssb/Kconfig\n@@ -136,6 +136,7 @@ config SSB_SFLASH\n config SSB_EMBEDDED\n \tbool\n \tdepends on SSB_DRIVER_MIPS && SSB_PCICORE_HOSTMODE\n+\tselect USB_HCD_SSB if USB_EHCI_HCD || USB_OHCI_HCD\n \tdefault y\n \n config SSB_DRIVER_EXTIF\n"
  },
  {
    "path": "target/linux/bcm47xx/patches-5.10/300-fork_cacheflush.patch",
    "content": "From: Wolfram Joost <dbox2@frokaschwei.de>\nSubject: [PATCH] fork_cacheflush\n\nOn ASUS WL-500gP there are many unexpected \"Segmentation fault\"s that\nseem to be caused by a kernel. They can be avoided by:\n1) Disabling highpage\n2) Using flush_cache_mm in flush_cache_dup_mm\n\nFor details see OpenWrt ticket #2035 https://dev.openwrt.org/ticket/2035\n---\n--- a/arch/mips/include/asm/cacheflush.h\n+++ b/arch/mips/include/asm/cacheflush.h\n@@ -46,7 +46,7 @@\n extern void (*flush_cache_all)(void);\n extern void (*__flush_cache_all)(void);\n extern void (*flush_cache_mm)(struct mm_struct *mm);\n-#define flush_cache_dup_mm(mm)\tdo { (void) (mm); } while (0)\n+#define flush_cache_dup_mm(mm) flush_cache_mm(mm)\n extern void (*flush_cache_range)(struct vm_area_struct *vma,\n \tunsigned long start, unsigned long end);\n extern void (*flush_cache_page)(struct vm_area_struct *vma, unsigned long page, unsigned long pfn);\n"
  },
  {
    "path": "target/linux/bcm47xx/patches-5.10/310-no_highpage.patch",
    "content": "From: Jeff Hansen <jhansen@cardaccess-inc.com>\nSubject: [PATCH] no highpage\n\nOn ASUS WL-500gP there are many unexpected \"Segmentation fault\"s that\nseem to be caused by a kernel. They can be avoided by:\n1) Disabling highpage\n2) Using flush_cache_mm in flush_cache_dup_mm\n\nFor details see OpenWrt ticket #2035 https://dev.openwrt.org/ticket/2035\n---\n--- a/arch/mips/include/asm/page.h\n+++ b/arch/mips/include/asm/page.h\n@@ -71,6 +71,7 @@ static inline unsigned int page_size_ftl\n #endif /* CONFIG_MIPS_HUGE_TLB_SUPPORT */\n \n #include <linux/pfn.h>\n+#include <asm/cpu-features.h>\n \n extern void build_clear_page(void);\n extern void build_copy_page(void);\n@@ -110,11 +111,16 @@ static inline void clear_user_page(void\n \t\tflush_data_cache_page((unsigned long)addr);\n }\n \n-struct vm_area_struct;\n-extern void copy_user_highpage(struct page *to, struct page *from,\n-\tunsigned long vaddr, struct vm_area_struct *vma);\n+static inline void copy_user_page(void *vto, void *vfrom, unsigned long vaddr,\n+\tstruct page *to)\n+{\n+\textern void (*flush_data_cache_page)(unsigned long addr);\n \n-#define __HAVE_ARCH_COPY_USER_HIGHPAGE\n+\tcopy_page(vto, vfrom);\n+\tif (!cpu_has_ic_fills_f_dc ||\n+\t    pages_do_alias((unsigned long)vto, vaddr & PAGE_MASK))\n+\t\tflush_data_cache_page((unsigned long)vto);\n+}\n \n /*\n  * These are used to make use of C type-checking..\n--- a/arch/mips/mm/init.c\n+++ b/arch/mips/mm/init.c\n@@ -167,30 +167,6 @@ void kunmap_coherent(void)\n \tpreempt_enable();\n }\n \n-void copy_user_highpage(struct page *to, struct page *from,\n-\tunsigned long vaddr, struct vm_area_struct *vma)\n-{\n-\tvoid *vfrom, *vto;\n-\n-\tvto = kmap_atomic(to);\n-\tif (cpu_has_dc_aliases && cpu_use_kmap_coherent &&\n-\t    page_mapcount(from) && !Page_dcache_dirty(from)) {\n-\t\tvfrom = kmap_coherent(from, vaddr);\n-\t\tcopy_page(vto, vfrom);\n-\t\tkunmap_coherent();\n-\t} else {\n-\t\tvfrom = kmap_atomic(from);\n-\t\tcopy_page(vto, vfrom);\n-\t\tkunmap_atomic(vfrom);\n-\t}\n-\tif ((!cpu_has_ic_fills_f_dc) ||\n-\t    pages_do_alias((unsigned long)vto, vaddr & PAGE_MASK))\n-\t\tflush_data_cache_page((unsigned long)vto);\n-\tkunmap_atomic(vto);\n-\t/* Make sure this page is cleared on other CPU's too before using it */\n-\tsmp_wmb();\n-}\n-\n void copy_to_user_page(struct vm_area_struct *vma,\n \tstruct page *page, unsigned long vaddr, void *dst, const void *src,\n \tunsigned long len)\n"
  },
  {
    "path": "target/linux/bcm47xx/patches-5.10/320-MIPS-BCM47XX-Devices-database-update-for-4.x.patch",
    "content": "--- a/arch/mips/bcm47xx/board.c\n+++ b/arch/mips/bcm47xx/board.c\n@@ -141,6 +141,7 @@ struct bcm47xx_board_type_list2 bcm47xx_\n \t{{BCM47XX_BOARD_LINKSYS_WRT300NV11, \"Linksys WRT300N V1.1\"}, \"WRT300N\", \"1.1\"},\n \t{{BCM47XX_BOARD_LINKSYS_WRT310NV1, \"Linksys WRT310N V1\"}, \"WRT310N\", \"1.0\"},\n \t{{BCM47XX_BOARD_LINKSYS_WRT310NV2, \"Linksys WRT310N V2\"}, \"WRT310N\", \"2.0\"},\n+\t{{BCM47XX_BOARD_LINKSYS_WRT320N_V1, \"Linksys WRT320N V1\"}, \"WRT320N\", \"1.0\"},\n \t{{BCM47XX_BOARD_LINKSYS_WRT54G3GV2, \"Linksys WRT54G3GV2-VF\"}, \"WRT54G3GV2-VF\", \"1.0\"},\n \t{{BCM47XX_BOARD_LINKSYS_WRT610NV1, \"Linksys WRT610N V1\"}, \"WRT610N\", \"1.0\"},\n \t{{BCM47XX_BOARD_LINKSYS_WRT610NV2, \"Linksys WRT610N V2\"}, \"WRT610N\", \"2.0\"},\n@@ -161,9 +162,12 @@ struct bcm47xx_board_type_list1 bcm47xx_\n \t{{BCM47XX_BOARD_LUXUL_XWR_600_V1, \"Luxul XWR-600 V1\"}, \"luxul_xwr600_v1\"},\n \t{{BCM47XX_BOARD_LUXUL_XWR_1750_V1, \"Luxul XWR-1750 V1\"}, \"luxul_xwr1750_v1\"},\n \t{{BCM47XX_BOARD_NETGEAR_R6200_V1, \"Netgear R6200 V1\"}, \"U12H192T00_NETGEAR\"},\n+\t{{BCM47XX_BOARD_NETGEAR_R6300_V1, \"Netgear R6300 V1\"}, \"U12H218T00_NETGEAR\"},\n \t{{BCM47XX_BOARD_NETGEAR_WGR614V8, \"Netgear WGR614 V8\"}, \"U12H072T00_NETGEAR\"},\n \t{{BCM47XX_BOARD_NETGEAR_WGR614V9, \"Netgear WGR614 V9\"}, \"U12H094T00_NETGEAR\"},\n \t{{BCM47XX_BOARD_NETGEAR_WGR614_V10, \"Netgear WGR614 V10\"}, \"U12H139T01_NETGEAR\"},\n+\t{{BCM47XX_BOARD_NETGEAR_WN2500RP_V1, \"Netgear WN2500RP V1\"}, \"U12H197T00_NETGEAR\"},\n+\t{{BCM47XX_BOARD_NETGEAR_WN2500RP_V2, \"Netgear WN2500RP V2\"}, \"U12H294T00_NETGEAR\"},\n \t{{BCM47XX_BOARD_NETGEAR_WNDR3300, \"Netgear WNDR3300\"}, \"U12H093T00_NETGEAR\"},\n \t{{BCM47XX_BOARD_NETGEAR_WNDR3400V1, \"Netgear WNDR3400 V1\"}, \"U12H155T00_NETGEAR\"},\n \t{{BCM47XX_BOARD_NETGEAR_WNDR3400V2, \"Netgear WNDR3400 V2\"}, \"U12H187T00_NETGEAR\"},\n--- a/arch/mips/bcm47xx/buttons.c\n+++ b/arch/mips/bcm47xx/buttons.c\n@@ -27,6 +27,12 @@\n /* Asus */\n \n static const struct gpio_keys_button\n+bcm47xx_buttons_asus_rtn10u[] __initconst = {\n+\tBCM47XX_GPIO_KEY(20, KEY_WPS_BUTTON),\n+\tBCM47XX_GPIO_KEY(21, KEY_RESTART),\n+};\n+\n+static const struct gpio_keys_button\n bcm47xx_buttons_asus_rtn12[] __initconst = {\n \tBCM47XX_GPIO_KEY(0, KEY_WPS_BUTTON),\n \tBCM47XX_GPIO_KEY(1, KEY_RESTART),\n@@ -277,6 +283,18 @@ bcm47xx_buttons_linksys_wrt310nv1[] __in\n };\n \n static const struct gpio_keys_button\n+bcm47xx_buttons_linksys_wrt310n_v2[] __initconst = {\n+\tBCM47XX_GPIO_KEY(5, KEY_WPS_BUTTON),\n+\tBCM47XX_GPIO_KEY(6, KEY_RESTART),\n+};\n+\n+static const struct gpio_keys_button\n+bcm47xx_buttons_linksys_wrt320n_v1[] __initconst = {\n+\tBCM47XX_GPIO_KEY(5, KEY_WPS_BUTTON),\n+\tBCM47XX_GPIO_KEY(8, KEY_RESTART),\n+};\n+\n+static const struct gpio_keys_button\n bcm47xx_buttons_linksys_wrt54g3gv2[] __initconst = {\n \tBCM47XX_GPIO_KEY(5, KEY_WIMAX),\n \tBCM47XX_GPIO_KEY(6, KEY_RESTART),\n@@ -392,6 +410,17 @@ bcm47xx_buttons_netgear_r6200_v1[] __ini\n };\n \n static const struct gpio_keys_button\n+bcm47xx_buttons_netgear_r6300_v1[] __initconst = {\n+\tBCM47XX_GPIO_KEY(6, KEY_RESTART),\n+};\n+\n+static const struct gpio_keys_button\n+bcm47xx_buttons_netgear_wn2500rp_v1[] __initconst = {\n+\tBCM47XX_GPIO_KEY(12, KEY_RESTART),\n+\tBCM47XX_GPIO_KEY(31, KEY_WPS_BUTTON),\n+};\n+\n+static const struct gpio_keys_button\n bcm47xx_buttons_netgear_wndr3400v1[] __initconst = {\n \tBCM47XX_GPIO_KEY(4, KEY_RESTART),\n \tBCM47XX_GPIO_KEY(6, KEY_WPS_BUTTON),\n@@ -478,6 +507,9 @@ int __init bcm47xx_buttons_register(void\n \tint err;\n \n \tswitch (board) {\n+\tcase BCM47XX_BOARD_ASUS_RTN10U:\n+\t\terr = bcm47xx_copy_bdata(bcm47xx_buttons_asus_rtn10u);\n+\t\tbreak;\n \tcase BCM47XX_BOARD_ASUS_RTN12:\n \t\terr = bcm47xx_copy_bdata(bcm47xx_buttons_asus_rtn12);\n \t\tbreak;\n@@ -608,6 +640,12 @@ int __init bcm47xx_buttons_register(void\n \tcase BCM47XX_BOARD_LINKSYS_WRT310NV1:\n \t\terr = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_wrt310nv1);\n \t\tbreak;\n+\tcase BCM47XX_BOARD_LINKSYS_WRT310NV2:\n+\t\terr = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_wrt310n_v2);\n+\t\tbreak;\n+\tcase BCM47XX_BOARD_LINKSYS_WRT320N_V1:\n+\t\terr = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_wrt320n_v1);\n+\t\tbreak;\n \tcase BCM47XX_BOARD_LINKSYS_WRT54G3GV2:\n \t\terr = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_wrt54g3gv2);\n \t\tbreak;\n@@ -674,6 +712,12 @@ int __init bcm47xx_buttons_register(void\n \tcase BCM47XX_BOARD_NETGEAR_R6200_V1:\n \t\terr = bcm47xx_copy_bdata(bcm47xx_buttons_netgear_r6200_v1);\n \t\tbreak;\n+\tcase BCM47XX_BOARD_NETGEAR_R6300_V1:\n+\t\terr = bcm47xx_copy_bdata(bcm47xx_buttons_netgear_r6300_v1);\n+\t\tbreak;\n+\tcase BCM47XX_BOARD_NETGEAR_WN2500RP_V1:\n+\t\terr = bcm47xx_copy_bdata(bcm47xx_buttons_netgear_wn2500rp_v1);\n+\t\tbreak;\n \tcase BCM47XX_BOARD_NETGEAR_WNDR3400V1:\n \t\terr = bcm47xx_copy_bdata(bcm47xx_buttons_netgear_wndr3400v1);\n \t\tbreak;\n--- a/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h\n+++ b/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h\n@@ -72,6 +72,7 @@ enum bcm47xx_board {\n \tBCM47XX_BOARD_LINKSYS_WRT300NV11,\n \tBCM47XX_BOARD_LINKSYS_WRT310NV1,\n \tBCM47XX_BOARD_LINKSYS_WRT310NV2,\n+\tBCM47XX_BOARD_LINKSYS_WRT320N_V1,\n \tBCM47XX_BOARD_LINKSYS_WRT54G3GV2,\n \tBCM47XX_BOARD_LINKSYS_WRT54G_TYPE_0101,\n \tBCM47XX_BOARD_LINKSYS_WRT54G_TYPE_0467,\n@@ -99,9 +100,12 @@ enum bcm47xx_board {\n \tBCM47XX_BOARD_MOTOROLA_WR850GV2V3,\n \n \tBCM47XX_BOARD_NETGEAR_R6200_V1,\n+\tBCM47XX_BOARD_NETGEAR_R6300_V1,\n \tBCM47XX_BOARD_NETGEAR_WGR614V8,\n \tBCM47XX_BOARD_NETGEAR_WGR614V9,\n \tBCM47XX_BOARD_NETGEAR_WGR614_V10,\n+\tBCM47XX_BOARD_NETGEAR_WN2500RP_V1,\n+\tBCM47XX_BOARD_NETGEAR_WN2500RP_V2,\n \tBCM47XX_BOARD_NETGEAR_WNDR3300,\n \tBCM47XX_BOARD_NETGEAR_WNDR3400V1,\n \tBCM47XX_BOARD_NETGEAR_WNDR3400V2,\n--- a/arch/mips/bcm47xx/leds.c\n+++ b/arch/mips/bcm47xx/leds.c\n@@ -30,6 +30,14 @@\n /* Asus */\n \n static const struct gpio_led\n+bcm47xx_leds_asus_rtn10u[] __initconst = {\n+\tBCM47XX_GPIO_LED(5, \"green\", \"wlan\", 0, LEDS_GPIO_DEFSTATE_OFF),\n+\tBCM47XX_GPIO_LED(6, \"green\", \"power\", 1, LEDS_GPIO_DEFSTATE_ON),\n+\tBCM47XX_GPIO_LED(7, \"green\", \"wps\", 0, LEDS_GPIO_DEFSTATE_OFF),\n+\tBCM47XX_GPIO_LED(8, \"green\", \"usb\", 0, LEDS_GPIO_DEFSTATE_OFF),\n+};\n+\n+static const struct gpio_led\n bcm47xx_leds_asus_rtn12[] __initconst = {\n \tBCM47XX_GPIO_LED(2, \"unk\", \"power\", 1, LEDS_GPIO_DEFSTATE_ON),\n \tBCM47XX_GPIO_LED(7, \"unk\", \"wlan\", 0, LEDS_GPIO_DEFSTATE_OFF),\n@@ -314,6 +322,13 @@ bcm47xx_leds_linksys_wrt310nv1[] __initc\n };\n \n static const struct gpio_led\n+bcm47xx_leds_linksys_wrt320n_v1[] __initconst = {\n+\tBCM47XX_GPIO_LED(1, \"blue\", \"wlan\", 1, LEDS_GPIO_DEFSTATE_OFF),\n+\tBCM47XX_GPIO_LED(2, \"blue\", \"power\", 0, LEDS_GPIO_DEFSTATE_ON),\n+\tBCM47XX_GPIO_LED(4, \"amber\", \"wps\", 1, LEDS_GPIO_DEFSTATE_OFF),\n+};\n+\n+static const struct gpio_led\n bcm47xx_leds_linksys_wrt54g_generic[] __initconst = {\n \tBCM47XX_GPIO_LED(0, \"unk\", \"dmz\", 1, LEDS_GPIO_DEFSTATE_OFF),\n \tBCM47XX_GPIO_LED(1, \"unk\", \"power\", 0, LEDS_GPIO_DEFSTATE_ON),\n@@ -556,6 +571,9 @@ void __init bcm47xx_leds_register(void)\n \tenum bcm47xx_board board = bcm47xx_board_get();\n \n \tswitch (board) {\n+\tcase BCM47XX_BOARD_ASUS_RTN10U:\n+\t\tbcm47xx_set_pdata(bcm47xx_leds_asus_rtn10u);\n+\t\tbreak;\n \tcase BCM47XX_BOARD_ASUS_RTN12:\n \t\tbcm47xx_set_pdata(bcm47xx_leds_asus_rtn12);\n \t\tbreak;\n@@ -689,6 +707,9 @@ void __init bcm47xx_leds_register(void)\n \tcase BCM47XX_BOARD_LINKSYS_WRT310NV1:\n \t\tbcm47xx_set_pdata(bcm47xx_leds_linksys_wrt310nv1);\n \t\tbreak;\n+\tcase BCM47XX_BOARD_LINKSYS_WRT320N_V1:\n+\t\tbcm47xx_set_pdata(bcm47xx_leds_linksys_wrt320n_v1);\n+\t\tbreak;\n \tcase BCM47XX_BOARD_LINKSYS_WRT54G3GV2:\n \t\tbcm47xx_set_pdata(bcm47xx_leds_linksys_wrt54g3gv2);\n \t\tbreak;\n"
  },
  {
    "path": "target/linux/bcm47xx/patches-5.10/400-mtd-bcm47xxpart-get-nvram.patch",
    "content": "--- a/drivers/mtd/parsers/bcm47xxpart.c\n+++ b/drivers/mtd/parsers/bcm47xxpart.c\n@@ -98,6 +98,7 @@ static int bcm47xxpart_parse(struct mtd_\n \tint trx_num = 0; /* Number of found TRX partitions */\n \tint possible_nvram_sizes[] = { 0x8000, 0xF000, 0x10000, };\n \tint err;\n+\tbool found_nvram = false;\n \n \t/*\n \t * Some really old flashes (like AT45DB*) had smaller erasesize-s, but\n@@ -279,12 +280,23 @@ static int bcm47xxpart_parse(struct mtd_\n \t\tif (buf[0] == NVRAM_HEADER) {\n \t\t\tbcm47xxpart_add_part(&parts[curr_part++], \"nvram\",\n \t\t\t\t\t     master->size - blocksize, 0);\n+\t\t\tfound_nvram = true;\n \t\t\tbreak;\n \t\t}\n \t}\n \n \tkfree(buf);\n \n+\tif (!found_nvram) {\n+\t\tpr_err(\"can not find a nvram partition reserve last block\\n\");\n+\t\tbcm47xxpart_add_part(&parts[curr_part++], \"nvram_guess\",\n+\t\t\t\t     master->size - blocksize * 2, MTD_WRITEABLE);\n+\t\tfor (i = 0; i < curr_part; i++) {\n+\t\t\tif (parts[i].size + parts[i].offset == master->size)\n+\t\t\t\tparts[i].offset -= blocksize * 2;\n+\t\t}\n+\t}\n+\n \t/*\n \t * Assume that partitions end at the beginning of the one they are\n \t * followed by.\n"
  },
  {
    "path": "target/linux/bcm47xx/patches-5.10/610-pci_ide_fix.patch",
    "content": "From: b.sander\nSubject: [PATCH] pci: IDE fix\n\nThese are standard probing messages when using pdc202xx_old:\npdc202xx_old 0000:00:01.0: IDE controller (0x105a:0x0d30 rev 0x02)\nPCI: Enabling device 0000:00:01.0 (0004 -> 0007)\nPCI: Fixing up device 0000:00:01.0\n0000:00:01.0: (U)DMA Burst Bit DISABLED Primary PCI Mode Secondary PCI Mode.\n0000:00:01.0: FORCING BURST BIT 0x00->0x01 ACTIVE\npdc202xx_old 0000:00:01.0: 100% native mode on irq 6\n\nWith the default MAX_HWIFS value after above we get:\n    ide2: BM-DMA at 0x0400-0x0407\n    ide3: BM-DMA at 0x0408-0x040f\nProbing IDE interface ide2...\nhde: CF500, CFA DISK drive\n\nAs you can see it's ide2 + ide3 and hde.\n\nWith this patch applied we get:\n    ide0: BM-DMA at 0x0400-0x0407\n    ide1: BM-DMA at 0x0408-0x040f\nProbing IDE interface ide0...\nhda: CF500, CFA DISK drive\n\nThis fixes OpenWrt ticket #7061: https://dev.openwrt.org/ticket/7061\n---\n--- a/include/linux/ide.h\n+++ b/include/linux/ide.h\n@@ -236,7 +236,11 @@ static inline void ide_std_init_ports(st\n \thw->io_ports.ctl_addr = ctl_addr;\n }\n \n+#if defined CONFIG_BCM47XX\n+# define MAX_HWIFS\t2\n+#else\n #define MAX_HWIFS\t10\n+#endif\n \n /*\n  * Now for the data we need to maintain per-drive:  ide_drive_t\n"
  },
  {
    "path": "target/linux/bcm47xx/patches-5.10/700-net-bgmac-connect-to-PHY-even-if-it-is-BGMAC_PHY_NOR.patch",
    "content": "From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Sun, 7 Nov 2021 14:20:40 +0100\nSubject: [PATCH] net: bgmac: connect to PHY even if it is BGMAC_PHY_NOREGS\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nRecent bgmac change was meant to just fix a race between \"Generic PHY\"\nand \"bcm53xx\" drivers after -EPROBE_DEFER. It modified bgmac to use\nphy_connect() only if there is a real PHY device connected.\n\nThat change broke bgmac on bcm47xx. bcma_phy_connect() now registers a\nfixed PHY with the bgmac_phy_connect_direct(). That fails as another\nfixed PHY (also using address 0) is already registered - by bcm47xx arch\ncode bcm47xx_register_bus_complete().\n\nThis change brings origial behaviour. It connects Ethernet interface\nwith pseudo-PHY (switch device) and adjusts Ethernet interface link to\nmatch connected switch.\n\nThis fixes:\n[    2.548098] bgmac_bcma bcma0:1: Failed to register fixed PHY device\n[    2.554584] bgmac_bcma bcma0:1: Cannot connect to phy\n\nFixes: b5375509184d (\"net: bgmac: improve handling PHY\")\nLink: https://lore.kernel.org/netdev/3639116e-9292-03ca-b9d9-d741118a4541@gmail.com/T/#u\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\n---\n drivers/net/ethernet/broadcom/bgmac-bcma.c | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/drivers/net/ethernet/broadcom/bgmac-bcma.c\n+++ b/drivers/net/ethernet/broadcom/bgmac-bcma.c\n@@ -94,7 +94,7 @@ static int bcma_phy_connect(struct bgmac\n \t\treturn 0;\n \n \t/* Connect to the PHY */\n-\tif (bgmac->mii_bus && bgmac->phyaddr != BGMAC_PHY_NOREGS) {\n+\tif (bgmac->mii_bus) {\n \t\tsnprintf(bus_id, sizeof(bus_id), PHY_ID_FMT, bgmac->mii_bus->id,\n \t\t\t bgmac->phyaddr);\n \t\tphy_dev = phy_connect(bgmac->net_dev, bus_id, bgmac_adjust_link,\n"
  },
  {
    "path": "target/linux/bcm47xx/patches-5.10/791-tg3-no-pci-sleep.patch",
    "content": "When the Ethernet controller is powered down and someone wants to \naccess the mdio bus like the witch driver (b53) the system crashed if \nPCI_D3hot was set before. This patch deactivates this power sawing mode \nwhen a switch driver is in use.\n\n--- a/drivers/net/ethernet/broadcom/tg3.c\n+++ b/drivers/net/ethernet/broadcom/tg3.c\n@@ -4273,7 +4273,8 @@ static int tg3_power_down_prepare(struct\n static void tg3_power_down(struct tg3 *tp)\n {\n \tpci_wake_from_d3(tp->pdev, tg3_flag(tp, WOL_ENABLE));\n-\tpci_set_power_state(tp->pdev, PCI_D3hot);\n+\tif (!tg3_flag(tp, ROBOSWITCH))\n+\t\tpci_set_power_state(tp->pdev, PCI_D3hot);\n }\n \n static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u32 *speed, u8 *duplex)\n"
  },
  {
    "path": "target/linux/bcm47xx/patches-5.10/800-bcma-add-table-of-serial-flashes-with-smaller-blocks.patch",
    "content": "From 597715c61ae75a05ab3310a34ff3857a006f0f63 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <zajec5@gmail.com>\nDate: Thu, 20 Nov 2014 21:32:42 +0100\nSubject: [PATCH] bcma: add table of serial flashes with smaller blocks\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nSigned-off-by: Rafał Miłecki <zajec5@gmail.com>\n---\n drivers/bcma/driver_chipcommon_sflash.c | 29 +++++++++++++++++++++++++++++\n 1 file changed, 29 insertions(+)\n\n--- a/drivers/bcma/driver_chipcommon_sflash.c\n+++ b/drivers/bcma/driver_chipcommon_sflash.c\n@@ -9,6 +9,7 @@\n \n #include <linux/platform_device.h>\n #include <linux/bcma/bcma.h>\n+#include <bcm47xx_board.h>\n \n static struct resource bcma_sflash_resource = {\n \t.name\t= \"bcma_sflash\",\n@@ -42,6 +43,13 @@ static const struct bcma_sflash_tbl_e bc\n \t{ NULL },\n };\n \n+/* Some devices use smaller blocks (and have more of them) */\n+static const struct bcma_sflash_tbl_e bcma_sflash_st_shrink_tbl[] = {\n+\t{ \"M25P16\", 0x14, 0x1000, 512, },\n+\t{ \"M25P32\", 0x15, 0x1000, 1024, },\n+\t{ NULL },\n+};\n+\n static const struct bcma_sflash_tbl_e bcma_sflash_sst_tbl[] = {\n \t{ \"SST25WF512\", 1, 0x1000, 16, },\n \t{ \"SST25VF512\", 0x48, 0x1000, 16, },\n@@ -85,6 +93,24 @@ static void bcma_sflash_cmd(struct bcma_\n \tbcma_err(cc->core->bus, \"SFLASH control command failed (timeout)!\\n\");\n }\n \n+const struct bcma_sflash_tbl_e *bcma_sflash_shrink_flash(u32 id)\n+{\n+\tenum bcm47xx_board board = bcm47xx_board_get();\n+\tconst struct bcma_sflash_tbl_e *e;\n+\n+\tswitch (board) {\n+\tcase BCM47XX_BOARD_NETGEAR_WGR614_V10:\n+\tcase BCM47XX_BOARD_NETGEAR_WNR1000_V3:\n+\t\tfor (e = bcma_sflash_st_shrink_tbl; e->name; e++) {\n+\t\t\tif (e->id == id)\n+\t\t\t\treturn e;\n+\t\t}\n+\t\treturn NULL;\n+\tdefault:\n+\t\treturn NULL;\n+\t}\n+}\n+\n /* Initialize serial flash access */\n int bcma_sflash_init(struct bcma_drv_cc *cc)\n {\n@@ -115,6 +141,10 @@ int bcma_sflash_init(struct bcma_drv_cc\n \t\tcase 0x13:\n \t\t\treturn -ENOTSUPP;\n \t\tdefault:\n+\t\t\te = bcma_sflash_shrink_flash(id);\n+\t\t\tif (e)\n+\t\t\t\tbreak;\n+\n \t\t\tfor (e = bcma_sflash_st_tbl; e->name; e++) {\n \t\t\t\tif (e->id == id)\n \t\t\t\t\tbreak;\n"
  },
  {
    "path": "target/linux/bcm47xx/patches-5.10/820-wgt634u-nvram-fix.patch",
    "content": "The Netgear wgt634u uses a different format for storing the \nconfiguration. This patch is needed to read out the correct \nconfiguration. The cfe_env.c file uses a different method way to read \nout the configuration than the in kernel cfe config reader.\n\n--- a/drivers/firmware/broadcom/Makefile\n+++ b/drivers/firmware/broadcom/Makefile\n@@ -1,4 +1,4 @@\n # SPDX-License-Identifier: GPL-2.0-only\n-obj-$(CONFIG_BCM47XX_NVRAM)\t\t+= bcm47xx_nvram.o\n+obj-$(CONFIG_BCM47XX_NVRAM)\t\t+= bcm47xx_nvram.o cfe_env.o\n obj-$(CONFIG_BCM47XX_SPROM)\t\t+= bcm47xx_sprom.o\n obj-$(CONFIG_TEE_BNXT_FW)\t\t+= tee_bnxt_fw.o\n--- /dev/null\n+++ b/drivers/firmware/broadcom/cfe_env.c\n@@ -0,0 +1,228 @@\n+/*\n+ * CFE environment variable access\n+ *\n+ * Copyright 2001-2003, Broadcom Corporation\n+ * Copyright 2006, Felix Fietkau <nbd@nbd.name>\n+ * \n+ * This program is free software; you can redistribute  it and/or modify it\n+ * under  the terms of  the GNU General  Public License as published by the\n+ * Free Software Foundation;  either version 2 of the  License, or (at your\n+ * option) any later version.\n+ */\n+\n+#include <linux/init.h>\n+#include <linux/module.h>\n+#include <linux/kernel.h>\n+#include <linux/string.h>\n+#include <asm/io.h>\n+#include <linux/uaccess.h>\n+\n+#define NVRAM_SIZE       (0x1ff0)\n+static char _nvdata[NVRAM_SIZE];\n+static char _valuestr[256];\n+\n+/*\n+ * TLV types.  These codes are used in the \"type-length-value\"\n+ * encoding of the items stored in the NVRAM device (flash or EEPROM)\n+ *\n+ * The layout of the flash/nvram is as follows:\n+ *\n+ * <type> <length> <data ...> <type> <length> <data ...> <type_end>\n+ *\n+ * The type code of \"ENV_TLV_TYPE_END\" marks the end of the list.\n+ * The \"length\" field marks the length of the data section, not\n+ * including the type and length fields.\n+ *\n+ * Environment variables are stored as follows:\n+ *\n+ * <type_env> <length> <flags> <name> = <value>\n+ *\n+ * If bit 0 (low bit) is set, the length is an 8-bit value.\n+ * If bit 0 (low bit) is clear, the length is a 16-bit value\n+ * \n+ * Bit 7 set indicates \"user\" TLVs.  In this case, bit 0 still\n+ * indicates the size of the length field.  \n+ *\n+ * Flags are from the constants below:\n+ *\n+ */\n+#define ENV_LENGTH_16BITS\t0x00\t/* for low bit */\n+#define ENV_LENGTH_8BITS\t0x01\n+\n+#define ENV_TYPE_USER\t\t0x80\n+\n+#define ENV_CODE_SYS(n,l) (((n)<<1)|(l))\n+#define ENV_CODE_USER(n,l) ((((n)<<1)|(l)) | ENV_TYPE_USER)\n+\n+/*\n+ * The actual TLV types we support\n+ */\n+\n+#define ENV_TLV_TYPE_END\t0x00\t\n+#define ENV_TLV_TYPE_ENV\tENV_CODE_SYS(0,ENV_LENGTH_8BITS)\n+\n+/*\n+ * Environment variable flags \n+ */\n+\n+#define ENV_FLG_NORMAL\t\t0x00\t/* normal read/write */\n+#define ENV_FLG_BUILTIN\t\t0x01\t/* builtin - not stored in flash */\n+#define ENV_FLG_READONLY\t0x02\t/* read-only - cannot be changed */\n+\n+#define ENV_FLG_MASK\t\t0xFF\t/* mask of attributes we keep */\n+#define ENV_FLG_ADMIN\t\t0x100\t/* lets us internally override permissions */\n+\n+\n+/*  *********************************************************************\n+    *  _nvram_read(buffer,offset,length)\n+    *  \n+    *  Read data from the NVRAM device\n+    *  \n+    *  Input parameters: \n+    *  \t   buffer - destination buffer\n+    *  \t   offset - offset of data to read\n+    *  \t   length - number of bytes to read\n+    *  \t   \n+    *  Return value:\n+    *  \t   number of bytes read, or <0 if error occured\n+    ********************************************************************* */\n+static int\n+_nvram_read(unsigned char *nv_buf, unsigned char *buffer, int offset, int length)\n+{\n+    int i;\n+    if (offset > NVRAM_SIZE)\n+\treturn -1; \n+\n+    for ( i = 0; i < length; i++) {\n+\tbuffer[i] = ((volatile unsigned char*)nv_buf)[offset + i];\n+    }\n+    return length;\n+}\n+\n+\n+static char*\n+_strnchr(const char *dest,int c,size_t cnt)\n+{\n+\twhile (*dest && (cnt > 0)) {\n+\tif (*dest == c) return (char *) dest;\n+\tdest++;\n+\tcnt--;\n+\t}\n+\treturn NULL;\n+}\n+\n+\n+\n+/*\n+ * Core support API: Externally visible.\n+ */\n+\n+/*\n+ * Get the value of an NVRAM variable\n+ * @param\tname\tname of variable to get\n+ * @return\tvalue of variable or NULL if undefined\n+ */\n+\n+char *cfe_env_get(unsigned char *nv_buf, const char *name)\n+{\n+    int size;\n+    unsigned char *buffer;\n+    unsigned char *ptr;\n+    unsigned char *envval;\n+    unsigned int reclen;\n+    unsigned int rectype;\n+    int offset;\n+    int flg;\n+    \n+\tif (!strcmp(name, \"nvram_type\"))\n+\t\treturn \"cfe\";\n+\t\n+    size = NVRAM_SIZE;\n+    buffer = &_nvdata[0];\n+\n+    ptr = buffer;\n+    offset = 0;\n+\n+    /* Read the record type and length */\n+    if (_nvram_read(nv_buf, ptr,offset,1) != 1) {\n+\tgoto error;\n+    }\n+    \n+    while ((*ptr != ENV_TLV_TYPE_END)  && (size > 1)) {\n+\n+\t/* Adjust pointer for TLV type */\n+\trectype = *(ptr);\n+\toffset++;\n+\tsize--;\n+\n+\t/* \n+\t * Read the length.  It can be either 1 or 2 bytes\n+\t * depending on the code \n+\t */\n+\tif (rectype & ENV_LENGTH_8BITS) {\n+\t    /* Read the record type and length - 8 bits */\n+\t    if (_nvram_read(nv_buf, ptr,offset,1) != 1) {\n+\t\tgoto error;\n+\t    }\n+\t    reclen = *(ptr);\n+\t    size--;\n+\t    offset++;\n+\t}\n+\telse {\n+\t    /* Read the record type and length - 16 bits, MSB first */\n+\t    if (_nvram_read(nv_buf, ptr,offset,2) != 2) {\n+\t\tgoto error;\n+\t    }\n+\t    reclen = (((unsigned int) *(ptr)) << 8) + (unsigned int) *(ptr+1);\n+\t    size -= 2;\n+\t    offset += 2;\n+\t}\n+\n+\tif (reclen > size)\n+\t    break;\t/* should not happen, bad NVRAM */\n+\n+\tswitch (rectype) {\n+\t    case ENV_TLV_TYPE_ENV:\n+\t\t/* Read the TLV data */\n+\t\tif (_nvram_read(nv_buf, ptr,offset,reclen) != reclen)\n+\t\t    goto error;\n+\t\tflg = *ptr++;\n+\t\tenvval = (unsigned char *) _strnchr(ptr,'=',(reclen-1));\n+\t\tif (envval) {\n+\t\t    *envval++ = '\\0';\n+\t\t    memcpy(_valuestr,envval,(reclen-1)-(envval-ptr));\n+\t\t    _valuestr[(reclen-1)-(envval-ptr)] = '\\0';\n+#if 0\t\t\t\n+\t\t    printk(KERN_INFO \"NVRAM:%s=%s\\n\", ptr, _valuestr);\n+#endif\n+\t\t    if(!strcmp(ptr, name)){\n+\t\t\treturn _valuestr;\n+\t\t    }\n+\t\t    if((strlen(ptr) > 1) && !strcmp(&ptr[1], name))\n+\t\t\treturn _valuestr;\n+\t\t}\n+\t\tbreak;\n+\t\t\n+\t    default: \n+\t\t/* Unknown TLV type, skip it. */\n+\t\tbreak;\n+\t    }\n+\n+\t/*\n+\t * Advance to next TLV \n+\t */\n+\t\t\n+\tsize -= (int)reclen;\n+\toffset += reclen;\n+\n+\t/* Read the next record type */\n+\tptr = buffer;\n+\tif (_nvram_read(nv_buf, ptr,offset,1) != 1)\n+\t    goto error;\n+\t}\n+\n+error:\n+    return NULL;\n+\n+}\n+\n--- a/drivers/firmware/broadcom/bcm47xx_nvram.c\n+++ b/drivers/firmware/broadcom/bcm47xx_nvram.c\n@@ -33,6 +33,8 @@ struct nvram_header {\n static char nvram_buf[NVRAM_SPACE];\n static size_t nvram_len;\n static const u32 nvram_sizes[] = {0x6000, 0x8000, 0xF000, 0x10000};\n+static int cfe_env;\n+extern char *cfe_env_get(char *nv_buf, const char *name);\n \n /**\n  * bcm47xx_nvram_is_valid - check for a valid NVRAM at specified memory\n@@ -80,6 +82,26 @@ static int bcm47xx_nvram_find_and_copy(v\n \t\treturn -EEXIST;\n \t}\n \n+\tcfe_env = 0;\n+\n+\t/* XXX: hack for supporting the CFE environment stuff on WGT634U */\n+\tif (res_size >= 8 * 1024 * 1024) {\n+\t\tu32 *src = (u32 *)(flash_start + 8 * 1024 * 1024 - 0x2000);\n+\t\tu32 *dst = (u32 *)nvram_buf;\n+\n+\t\tif ((*src & 0xff00ff) == 0x000001) {\n+\t\t\tprintk(\"early_nvram_init: WGT634U NVRAM found.\\n\");\n+\n+\t\t\tfor (i = 0; i < 0x1ff0; i++) {\n+\t\t\t\tif (*src == 0xFFFFFFFF)\n+\t\t\t\t\tbreak;\n+\t\t\t\t*dst++ = *src++;\n+\t\t\t}\n+\t\t\tcfe_env = 1;\n+\t\t\treturn 0;\n+\t\t}\n+\t}\n+\n \t/* TODO: when nvram is on nand flash check for bad blocks first. */\n \n \t/* Try every possible flash size and check for NVRAM at its end */\n@@ -172,6 +194,13 @@ int bcm47xx_nvram_getenv(const char *nam\n \tif (!name)\n \t\treturn -EINVAL;\n \n+\tif (cfe_env) {\n+\t\tvalue = cfe_env_get(nvram_buf, name);\n+\t\tif (!value)\n+\t\t\treturn -ENOENT;\n+\t\treturn snprintf(val, val_len, \"%s\", value);\n+\t}\n+\n \tif (!nvram_len) {\n \t\terr = nvram_init();\n \t\tif (err)\n"
  },
  {
    "path": "target/linux/bcm47xx/patches-5.10/830-huawei_e970_support.patch",
    "content": "--- a/arch/mips/bcm47xx/setup.c\n+++ b/arch/mips/bcm47xx/setup.c\n@@ -37,6 +37,7 @@\n #include <linux/ssb/ssb.h>\n #include <linux/ssb/ssb_embedded.h>\n #include <linux/bcma/bcma_soc.h>\n+#include <linux/old_gpio_wdt.h>\n #include <asm/bootinfo.h>\n #include <asm/idle.h>\n #include <asm/prom.h>\n@@ -254,6 +255,33 @@ static struct fixed_phy_status bcm47xx_f\n \t.duplex\t= DUPLEX_FULL,\n };\n \n+static struct gpio_wdt_platform_data gpio_wdt_data;\n+\n+static struct platform_device gpio_wdt_device = {\n+\t.name\t\t\t= \"gpio-wdt\",\n+\t.id\t\t\t= 0,\n+\t.dev\t\t\t= {\n+\t\t.platform_data\t= &gpio_wdt_data,\n+\t},\n+};\n+\n+static int __init bcm47xx_register_gpio_watchdog(void)\n+{\n+\tenum bcm47xx_board board = bcm47xx_board_get();\n+\n+\tswitch (board) {\n+\tcase BCM47XX_BOARD_HUAWEI_E970:\n+\t\tpr_info(\"bcm47xx: detected Huawei E970 or similar, starting early gpio_wdt timer\\n\");\n+\t\tgpio_wdt_data.gpio = 7;\n+\t\tgpio_wdt_data.interval = HZ;\n+\t\tgpio_wdt_data.first_interval = HZ / 5;\n+\t\treturn platform_device_register(&gpio_wdt_device);\n+\tdefault:\n+\t\t/* Nothing to do */\n+\t\treturn 0;\n+\t}\n+}\n+\n static int __init bcm47xx_register_bus_complete(void)\n {\n \tswitch (bcm47xx_bus_type) {\n@@ -275,6 +303,7 @@ static int __init bcm47xx_register_bus_c\n \tbcm47xx_workarounds();\n \n \tfixed_phy_add(PHY_POLL, 0, &bcm47xx_fixed_phy_status);\n+\tbcm47xx_register_gpio_watchdog();\n \treturn 0;\n }\n device_initcall(bcm47xx_register_bus_complete);\n--- a/arch/mips/configs/bcm47xx_defconfig\n+++ b/arch/mips/configs/bcm47xx_defconfig\n@@ -63,6 +63,7 @@ CONFIG_HW_RANDOM=y\n CONFIG_GPIO_SYSFS=y\n CONFIG_WATCHDOG=y\n CONFIG_BCM47XX_WDT=y\n+CONFIG_GPIO_WDT=y\n CONFIG_SSB_DRIVER_GIGE=y\n CONFIG_BCMA_DRIVER_GMAC_CMN=y\n CONFIG_USB=y\n--- a/drivers/ssb/embedded.c\n+++ b/drivers/ssb/embedded.c\n@@ -34,11 +34,36 @@ int ssb_watchdog_timer_set(struct ssb_bu\n }\n EXPORT_SYMBOL(ssb_watchdog_timer_set);\n \n+#ifdef CONFIG_BCM47XX\n+#include <bcm47xx_board.h>\n+\n+static bool ssb_watchdog_supported(void)\n+{\n+\tenum bcm47xx_board board = bcm47xx_board_get();\n+\n+\t/* The Huawei E970 has a hardware watchdog using a GPIO */\n+\tswitch (board) {\n+\tcase BCM47XX_BOARD_HUAWEI_E970:\n+\t\treturn false;\n+\tdefault:\n+\t\treturn true;\n+\t}\n+}\n+#else\n+static bool ssb_watchdog_supported(void)\n+{\n+\treturn true;\n+}\n+#endif\n+\n int ssb_watchdog_register(struct ssb_bus *bus)\n {\n \tstruct bcm47xx_wdt wdt = {};\n \tstruct platform_device *pdev;\n \n+\tif (!ssb_watchdog_supported())\n+\t\treturn 0;\n+\n \tif (ssb_chipco_available(&bus->chipco)) {\n \t\twdt.driver_data = &bus->chipco;\n \t\twdt.timer_set = ssb_chipco_watchdog_timer_set_wdt;\n"
  },
  {
    "path": "target/linux/bcm47xx/patches-5.10/831-old_gpio_wdt.patch",
    "content": "This generic GPIO watchdog is used on Huawei E970 (bcm47xx)\n\nSigned-off-by: Mathias Adam <m.adam--openwrt@adamis.de>\n\n--- a/drivers/watchdog/Kconfig\n+++ b/drivers/watchdog/Kconfig\n@@ -1698,6 +1698,15 @@ config WDT_MTX1\n \t  Hardware driver for the MTX-1 boards. This is a watchdog timer that\n \t  will reboot the machine after a 100 seconds timer expired.\n \n+config GPIO_WDT\n+\ttristate \"GPIO Hardware Watchdog\"\n+ \thelp\n+\t  Hardware driver for GPIO-controlled watchdogs. GPIO pin and\n+\t  toggle interval settings are platform-specific. The driver\n+\t  will stop toggling the GPIO (i.e. machine reboots) after a\n+\t  100 second timer expired and no process has written to\n+\t  /dev/watchdog during that time.\n+\n config PNX833X_WDT\n \ttristate \"PNX833x Hardware Watchdog\"\n \tdepends on SOC_PNX8335\n--- a/drivers/watchdog/Makefile\n+++ b/drivers/watchdog/Makefile\n@@ -161,6 +161,7 @@ obj-$(CONFIG_RC32434_WDT) += rc32434_wdt\n obj-$(CONFIG_INDYDOG) += indydog.o\n obj-$(CONFIG_JZ4740_WDT) += jz4740_wdt.o\n obj-$(CONFIG_WDT_MTX1) += mtx-1_wdt.o\n+obj-$(CONFIG_GPIO_WDT) += old_gpio_wdt.o\n obj-$(CONFIG_PNX833X_WDT) += pnx833x_wdt.o\n obj-$(CONFIG_SIBYTE_WDOG) += sb_wdog.o\n obj-$(CONFIG_AR7_WDT) += ar7_wdt.o\n--- /dev/null\n+++ b/drivers/watchdog/old_gpio_wdt.c\n@@ -0,0 +1,301 @@\n+/*\n+ *      Driver for GPIO-controlled Hardware Watchdogs.\n+ *\n+ *      Copyright (C) 2013 Mathias Adam <m.adam--linux@adamis.de>\n+ *\n+ *      Replaces mtx1_wdt (driver for the MTX-1 Watchdog):\n+ *\n+ *      (C) Copyright 2005 4G Systems <info@4g-systems.biz>,\n+ *                              All Rights Reserved.\n+ *                              http://www.4g-systems.biz\n+ *\n+ *      (C) Copyright 2007 OpenWrt.org, Florian Fainelli <florian@openwrt.org>\n+ *\n+ *      This program is free software; you can redistribute it and/or\n+ *      modify it under the terms of the GNU General Public License\n+ *      as published by the Free Software Foundation; either version\n+ *      2 of the License, or (at your option) any later version.\n+ *\n+ *      Neither Michael Stickel nor 4G Systems admit liability nor provide\n+ *      warranty for any of this software. This material is provided\n+ *      \"AS-IS\" and at no charge.\n+ *\n+ *      (c) Copyright 2005    4G Systems <info@4g-systems.biz>\n+ *\n+ *      Release 0.01.\n+ *      Author: Michael Stickel  michael.stickel@4g-systems.biz\n+ *\n+ *      Release 0.02.\n+ *      Author: Florian Fainelli florian@openwrt.org\n+ *              use the Linux watchdog/timer APIs\n+ *\n+ *      Release 0.03.\n+ *      Author: Mathias Adam <m.adam--linux@adamis.de>\n+ *              make it a generic gpio watchdog driver\n+ *\n+ *      The Watchdog is configured to reset the MTX-1\n+ *      if it is not triggered for 100 seconds.\n+ *      It should not be triggered more often than 1.6 seconds.\n+ *\n+ *      A timer triggers the watchdog every 5 seconds, until\n+ *      it is opened for the first time. After the first open\n+ *      it MUST be triggered every 2..95 seconds.\n+ */\n+\n+#include <linux/module.h>\n+#include <linux/moduleparam.h>\n+#include <linux/types.h>\n+#include <linux/errno.h>\n+#include <linux/miscdevice.h>\n+#include <linux/fs.h>\n+#include <linux/init.h>\n+#include <linux/ioport.h>\n+#include <linux/timer.h>\n+#include <linux/completion.h>\n+#include <linux/jiffies.h>\n+#include <linux/watchdog.h>\n+#include <linux/platform_device.h>\n+#include <linux/io.h>\n+#include <linux/uaccess.h>\n+#include <linux/gpio.h>\n+#include <linux/old_gpio_wdt.h>\n+\n+static int ticks = 100 * HZ;\n+\n+static struct {\n+\tstruct completion stop;\n+\tspinlock_t lock;\n+\tint running;\n+\tstruct timer_list timer;\n+\tint queue;\n+\tint default_ticks;\n+\tunsigned long inuse;\n+\tunsigned gpio;\n+\tunsigned int gstate;\n+\tint interval;\n+\tint first_interval;\n+} gpio_wdt_device;\n+\n+static void gpio_wdt_trigger(struct timer_list *unused)\n+{\n+\tspin_lock(&gpio_wdt_device.lock);\n+\tif (gpio_wdt_device.running && ticks > 0)\n+\t\tticks -= gpio_wdt_device.interval;\n+\n+\t/* toggle wdt gpio */\n+\tgpio_wdt_device.gstate = !gpio_wdt_device.gstate;\n+\tgpio_set_value(gpio_wdt_device.gpio, gpio_wdt_device.gstate);\n+\n+\tif (gpio_wdt_device.queue && ticks > 0)\n+\t\tmod_timer(&gpio_wdt_device.timer, jiffies + gpio_wdt_device.interval);\n+\telse\n+\t\tcomplete(&gpio_wdt_device.stop);\n+\tspin_unlock(&gpio_wdt_device.lock);\n+}\n+\n+static void gpio_wdt_reset(void)\n+{\n+\tticks = gpio_wdt_device.default_ticks;\n+}\n+\n+\n+static void gpio_wdt_start(void)\n+{\n+\tunsigned long flags;\n+\n+\tspin_lock_irqsave(&gpio_wdt_device.lock, flags);\n+\tif (!gpio_wdt_device.queue) {\n+\t\tgpio_wdt_device.queue = 1;\n+\t\tgpio_wdt_device.gstate = 1;\n+\t\tgpio_set_value(gpio_wdt_device.gpio, 1);\n+\t\tmod_timer(&gpio_wdt_device.timer, jiffies + gpio_wdt_device.first_interval);\n+\t}\n+\tgpio_wdt_device.running++;\n+\tspin_unlock_irqrestore(&gpio_wdt_device.lock, flags);\n+}\n+\n+static int gpio_wdt_stop(void)\n+{\n+\tunsigned long flags;\n+\n+\tspin_lock_irqsave(&gpio_wdt_device.lock, flags);\n+\tif (gpio_wdt_device.queue) {\n+\t\tgpio_wdt_device.queue = 0;\n+\t\tgpio_wdt_device.gstate = 0;\n+\t\tgpio_set_value(gpio_wdt_device.gpio, 0);\n+\t}\n+\tticks = gpio_wdt_device.default_ticks;\n+\tspin_unlock_irqrestore(&gpio_wdt_device.lock, flags);\n+\treturn 0;\n+}\n+\n+/* Filesystem functions */\n+\n+static int gpio_wdt_open(struct inode *inode, struct file *file)\n+{\n+\tif (test_and_set_bit(0, &gpio_wdt_device.inuse))\n+\t\treturn -EBUSY;\n+\treturn nonseekable_open(inode, file);\n+}\n+\n+\n+static int gpio_wdt_release(struct inode *inode, struct file *file)\n+{\n+\tclear_bit(0, &gpio_wdt_device.inuse);\n+\treturn 0;\n+}\n+\n+static long gpio_wdt_ioctl(struct file *file, unsigned int cmd,\n+\t\t\t\t\t\t\tunsigned long arg)\n+{\n+\tvoid __user *argp = (void __user *)arg;\n+\tint __user *p = (int __user *)argp;\n+\tunsigned int value;\n+\tstatic const struct watchdog_info ident = {\n+\t\t.options = WDIOF_CARDRESET,\n+\t\t.identity = \"GPIO WDT\",\n+\t};\n+\n+\tswitch (cmd) {\n+\tcase WDIOC_GETSUPPORT:\n+\t\tif (copy_to_user(argp, &ident, sizeof(ident)))\n+\t\t\treturn -EFAULT;\n+\t\tbreak;\n+\tcase WDIOC_GETSTATUS:\n+\tcase WDIOC_GETBOOTSTATUS:\n+\t\tput_user(0, p);\n+\t\tbreak;\n+\tcase WDIOC_SETOPTIONS:\n+\t\tif (get_user(value, p))\n+\t\t\treturn -EFAULT;\n+\t\tif (value & WDIOS_ENABLECARD)\n+\t\t\tgpio_wdt_start();\n+\t\telse if (value & WDIOS_DISABLECARD)\n+\t\t\tgpio_wdt_stop();\n+\t\telse\n+\t\t\treturn -EINVAL;\n+\t\treturn 0;\n+\tcase WDIOC_KEEPALIVE:\n+\t\tgpio_wdt_reset();\n+\t\tbreak;\n+\tdefault:\n+\t\treturn -ENOTTY;\n+\t}\n+\treturn 0;\n+}\n+\n+\n+static ssize_t gpio_wdt_write(struct file *file, const char *buf,\n+\t\t\t\t\t\tsize_t count, loff_t *ppos)\n+{\n+\tif (!count)\n+\t\treturn -EIO;\n+\tgpio_wdt_reset();\n+\treturn count;\n+}\n+\n+static const struct file_operations gpio_wdt_fops = {\n+\t.owner\t\t= THIS_MODULE,\n+\t.llseek\t\t= no_llseek,\n+\t.unlocked_ioctl\t= gpio_wdt_ioctl,\n+\t.open\t\t= gpio_wdt_open,\n+\t.write\t\t= gpio_wdt_write,\n+\t.release\t= gpio_wdt_release,\n+};\n+\n+\n+static struct miscdevice gpio_wdt_misc = {\n+\t.minor\t= WATCHDOG_MINOR,\n+\t.name\t= \"watchdog\",\n+\t.fops\t= &gpio_wdt_fops,\n+};\n+\n+\n+static int gpio_wdt_probe(struct platform_device *pdev)\n+{\n+\tint ret;\n+\tstruct gpio_wdt_platform_data *gpio_wdt_data = pdev->dev.platform_data;\n+\n+\tgpio_wdt_device.gpio = gpio_wdt_data->gpio;\n+\tgpio_wdt_device.interval = gpio_wdt_data->interval;\n+\tgpio_wdt_device.first_interval = gpio_wdt_data->first_interval;\n+\tif (gpio_wdt_device.first_interval <= 0) {\n+\t\tgpio_wdt_device.first_interval = gpio_wdt_device.interval;\n+\t}\n+\n+\tret = gpio_request(gpio_wdt_device.gpio, \"gpio-wdt\");\n+\tif (ret < 0) {\n+\t\tdev_err(&pdev->dev, \"failed to request gpio\");\n+\t\treturn ret;\n+\t}\n+\n+\tspin_lock_init(&gpio_wdt_device.lock);\n+\tinit_completion(&gpio_wdt_device.stop);\n+\tgpio_wdt_device.queue = 0;\n+\tclear_bit(0, &gpio_wdt_device.inuse);\n+\ttimer_setup(&gpio_wdt_device.timer, gpio_wdt_trigger, 0L);\n+\tgpio_wdt_device.default_ticks = ticks;\n+\n+\tgpio_wdt_start();\n+\tdev_info(&pdev->dev, \"GPIO Hardware Watchdog driver (gpio=%i interval=%i/%i)\\n\",\n+\t\tgpio_wdt_data->gpio, gpio_wdt_data->first_interval, gpio_wdt_data->interval);\n+\treturn 0;\n+}\n+\n+static int gpio_wdt_remove(struct platform_device *pdev)\n+{\n+\t/* FIXME: do we need to lock this test ? */\n+\tif (gpio_wdt_device.queue) {\n+\t\tgpio_wdt_device.queue = 0;\n+\t\twait_for_completion(&gpio_wdt_device.stop);\n+\t}\n+\n+\tgpio_free(gpio_wdt_device.gpio);\n+\tmisc_deregister(&gpio_wdt_misc);\n+\treturn 0;\n+}\n+\n+static struct platform_driver gpio_wdt_driver = {\n+\t.probe = gpio_wdt_probe,\n+\t.remove = gpio_wdt_remove,\n+\t.driver.name = \"gpio-wdt\",\n+\t.driver.owner = THIS_MODULE,\n+};\n+\n+static int __init gpio_wdt_init(void)\n+{\n+\treturn platform_driver_register(&gpio_wdt_driver);\n+}\n+arch_initcall(gpio_wdt_init);\n+\n+/*\n+ * We do wdt initialization in two steps: arch_initcall probes the wdt\n+ * very early to start pinging the watchdog (misc devices are not yet\n+ * available), and later module_init() just registers the misc device.\n+ */\n+static int gpio_wdt_init_late(void)\n+{\n+\tint ret;\n+\n+\tret = misc_register(&gpio_wdt_misc);\n+\tif (ret < 0) {\n+\t\tpr_err(\"GPIO_WDT: failed to register misc device\\n\");\n+\t\treturn ret;\n+\t}\n+\treturn 0;\n+}\n+#ifndef MODULE\n+module_init(gpio_wdt_init_late);\n+#endif\n+\n+static void __exit gpio_wdt_exit(void)\n+{\n+\tplatform_driver_unregister(&gpio_wdt_driver);\n+}\n+module_exit(gpio_wdt_exit);\n+\n+MODULE_AUTHOR(\"Michael Stickel, Florian Fainelli, Mathias Adam\");\n+MODULE_DESCRIPTION(\"Driver for GPIO hardware watchdogs\");\n+MODULE_LICENSE(\"GPL\");\n+MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);\n+MODULE_ALIAS(\"platform:gpio-wdt\");\n--- /dev/null\n+++ b/include/linux/old_gpio_wdt.h\n@@ -0,0 +1,21 @@\n+/*\n+ *  Definitions for the GPIO watchdog driver\n+ *\n+ *  Copyright (C) 2013 Mathias Adam <m.adam--linux@adamis.de>\n+ *\n+ *  This program is free software; you can redistribute it and/or modify\n+ *  it under the terms of the GNU General Public License version 2 as\n+ *  published by the Free Software Foundation.\n+ *\n+ */\n+\n+#ifndef _GPIO_WDT_H_\n+#define _GPIO_WDT_H_\n+\n+struct gpio_wdt_platform_data {\n+\tint\tgpio;\t\t/* GPIO line number */\n+\tint\tinterval;\t/* watchdog reset interval in system ticks */\n+\tint\tfirst_interval;\t/* first wd reset interval in system ticks */\n+};\n+\n+#endif /* _GPIO_WDT_H_ */\n"
  },
  {
    "path": "target/linux/bcm47xx/patches-5.10/900-ssb-reject-PCI-writes-setting-CardBus-bridge-resourc.patch",
    "content": "From 5c81397a0147ea59c778d1de14ef54e2268221f6 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <zajec5@gmail.com>\nDate: Wed, 8 Apr 2015 06:58:11 +0200\nSubject: [PATCH] ssb: reject PCI writes setting CardBus bridge resources\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nIf SoC has a CardBus we can set resources of device at slot 1 only. It's\nimpossigle to set bridge resources as it simply overwrites device 1\nconfiguration and usually results in Data bus error-s.\n\nSigned-off-by: Rafał Miłecki <zajec5@gmail.com>\n---\n drivers/ssb/driver_pcicore.c | 4 ++++\n 1 file changed, 4 insertions(+)\n\n--- a/drivers/ssb/driver_pcicore.c\n+++ b/drivers/ssb/driver_pcicore.c\n@@ -164,6 +164,10 @@ static int ssb_extpci_write_config(struc\n \tWARN_ON(!pc->hostmode);\n \tif (unlikely(len != 1 && len != 2 && len != 4))\n \t\tgoto out;\n+\t/* CardBus SoCs allow configuring dev 1 resources only */\n+\tif (extpci_core->cardbusmode && dev != 1 &&\n+\t    off >= PCI_BASE_ADDRESS_0 && off <= PCI_BASE_ADDRESS_5)\n+\t\tgoto out;\n \taddr = get_cfgspace_addr(pc, bus, dev, func, off);\n \tif (unlikely(!addr))\n \t\tgoto out;\n"
  },
  {
    "path": "target/linux/bcm47xx/patches-5.10/940-bcm47xx-yenta.patch",
    "content": "--- a/drivers/pcmcia/yenta_socket.c\n+++ b/drivers/pcmcia/yenta_socket.c\n@@ -932,6 +932,8 @@ static unsigned int yenta_probe_irq(stru\n \t * Probe for usable interrupts using the force\n \t * register to generate bogus card status events.\n \t */\n+#ifndef CONFIG_BCM47XX\n+\t/* WRT54G3G does not like this */\n \tcb_writel(socket, CB_SOCKET_EVENT, -1);\n \tcb_writel(socket, CB_SOCKET_MASK, CB_CSTSMASK);\n \treg = exca_readb(socket, I365_CSCINT);\n@@ -947,6 +949,7 @@ static unsigned int yenta_probe_irq(stru\n \t}\n \tcb_writel(socket, CB_SOCKET_MASK, 0);\n \texca_writeb(socket, I365_CSCINT, reg);\n+#endif\n \n \tmask = probe_irq_mask(val) & 0xffff;\n \n@@ -1031,6 +1034,10 @@ static void yenta_get_socket_capabilitie\n \telse\n \t\tsocket->socket.irq_mask = 0;\n \n+\t/* irq mask probing is broken for the WRT54G3G */\n+\tif (socket->socket.irq_mask == 0)\n+\t\tsocket->socket.irq_mask = 0x6f8;\n+\n \tdev_info(&socket->dev->dev, \"ISA IRQ mask 0x%04x, PCI irq %d\\n\",\n \t\t socket->socket.irq_mask, socket->cb_irq);\n }\n@@ -1262,6 +1269,15 @@ static int yenta_probe(struct pci_dev *d\n \tdev_info(&dev->dev, \"Socket status: %08x\\n\",\n \t\t cb_readl(socket, CB_SOCKET_STATE));\n \n+\t/* Generate an interrupt on card insert/remove */\n+\tconfig_writew(socket, CB_SOCKET_MASK, CB_CSTSMASK | CB_CDMASK);\n+\n+\t/* Set up Multifunction Routing Status Register */\n+\tconfig_writew(socket, 0x8C, 0x1000 /* MFUNC3 to GPIO3 */ | 0x2 /* MFUNC0 to INTA */);\n+\n+\t/* Switch interrupts to parallelized */\n+\tconfig_writeb(socket, 0x92, 0x64);\n+\n \tyenta_fixup_parent_bridge(dev->subordinate);\n \n \t/* Register it with the pcmcia layer.. */\n"
  },
  {
    "path": "target/linux/bcm47xx/patches-5.10/976-ssb_increase_pci_delay.patch",
    "content": "--- a/drivers/ssb/driver_pcicore.c\n+++ b/drivers/ssb/driver_pcicore.c\n@@ -390,7 +390,7 @@ static void ssb_pcicore_init_hostmode(st\n \tset_io_port_base(ssb_pcicore_controller.io_map_base);\n \t/* Give some time to the PCI controller to configure itself with the new\n \t * values. Not waiting at this point causes crashes of the machine. */\n-\tmdelay(10);\n+\tmdelay(300);\n \tregister_pci_controller(&ssb_pcicore_controller);\n }\n \n"
  },
  {
    "path": "target/linux/bcm47xx/patches-5.10/999-wl_exports.patch",
    "content": "--- a/drivers/firmware/broadcom/bcm47xx_nvram.c\n+++ b/drivers/firmware/broadcom/bcm47xx_nvram.c\n@@ -30,7 +30,8 @@ struct nvram_header {\n \tu32 config_ncdl;\t/* ncdl values for memc */\n };\n \n-static char nvram_buf[NVRAM_SPACE];\n+char nvram_buf[NVRAM_SPACE];\n+EXPORT_SYMBOL(nvram_buf);\n static size_t nvram_len;\n static const u32 nvram_sizes[] = {0x6000, 0x8000, 0xF000, 0x10000};\n static int cfe_env;\n--- a/arch/mips/mm/cache.c\n+++ b/arch/mips/mm/cache.c\n@@ -61,6 +61,9 @@ void (*_dma_cache_wback_inv)(unsigned lo\n void (*_dma_cache_wback)(unsigned long start, unsigned long size);\n void (*_dma_cache_inv)(unsigned long start, unsigned long size);\n \n+EXPORT_SYMBOL(_dma_cache_wback_inv);\n+EXPORT_SYMBOL(_dma_cache_inv);\n+\n #endif /* CONFIG_DMA_NONCOHERENT */\n \n /*\n"
  },
  {
    "path": "target/linux/bcm4908/Makefile",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n\ninclude $(TOPDIR)/rules.mk\n\nARCH:=aarch64\nBOARD:=bcm4908\nBOARDNAME:=Broadcom BCM4908 (ARMv8A CPUs Brahma-B53)\nFEATURES:=squashfs nand usb gpio\nCPU_TYPE:=cortex-a53\nSUBTARGETS:=generic\n\nKERNEL_PATCHVER:=5.10\n\ndefine Target/Description\n\tBuild firmware images for Broadcom BCM4908 SoC family routers.\nendef\n\ninclude $(INCLUDE_DIR)/target.mk\n\nKERNELNAME:=Image dtbs\n\nDEFAULT_PACKAGES += \\\n\tbcm4908img fdt-utils uboot-envtools \\\n\tkmod-gpio-button-hotplug \\\n\tkmod-usb-ohci kmod-usb2 kmod-usb3\n\n$(eval $(call BuildTarget))\n"
  },
  {
    "path": "target/linux/bcm4908/base-files/etc/board.d/02_network",
    "content": "# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause\n\n. /lib/functions/system.sh\n. /lib/functions/uci-defaults.sh\n\nbcm4908_setup_interfaces()\n{\n\tlocal board=\"$1\"\n\n\tcase \"$board\" in\n\tasus,gt-ac5300)\n\t\tucidef_set_interface_lan \"lan1 lan2 lan5 lan6 sw\"\n\t\t;;\n\t*)\n\t\tucidef_set_interfaces_lan_wan \"lan1 lan2 lan3 lan4\" \"wan\"\n\t\t;;\n\tesac\n}\n\nboard_config_update\nboard=$(board_name)\nbcm4908_setup_interfaces \"$board\"\nboard_config_flush\n\nexit 0\n"
  },
  {
    "path": "target/linux/bcm4908/base-files/lib/functions/bcm4908.sh",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause\n\nFS_STATE_READY=2\n\n# $(1): file to read from\n# $(2): offset in bytes\nget_hex_u32_le() {\n\tdd if=\"$1\" skip=$2 bs=1 count=4 2>/dev/null | hexdump -v -e '1/4 \"%02x\"'\n}\n\n# Setup /tmp/env.config to provide \"metadata\" UBI volume access\n#\n# It can be used with \"fw_printenv -c /tmp/env.config\"\nbcm4908_pkgtb_setup_env_config() {\n\tlocal size=$((0x$(get_hex_u32_le /dev/ubi0_1 4)))\n\n\tdd if=/dev/ubi0_1 of=/tmp/env.head count=8 iflag=count_bytes\n\tdd if=/dev/ubi0_1 of=/tmp/env.body skip=8 iflag=skip_bytes\n\tprintf \"%s\\t0x%x\\t0x%x\\t0x%x\" \"/tmp/env.body\" 0x0 $size $size > /tmp/env.config\n}\n\nbcm4908_committed_image_seq() {\n\tbcm4908_pkgtb_setup_env_config\n\n\tcommited=\"$(fw_printenv -n -c /tmp/env.config COMMITTED)\"\n\t[ -n \"$commited\" ] && {\n\t\tseq=$(fw_printenv -n -c /tmp/env.config SEQ | cut -d ',' -f $commited)\n\t\t[ -n \"$seq\" ] && {\n\t\t\techo $seq\n\t\t\treturn\n\t\t}\n\t}\n\n\techo \"Failed to read COMMITED and SEQ from metadata1\" >&2\n}\n\n# Make sure \"rootfs_data\" UBI volume matches currently flashed image\n#\n# On mismatch \"rootfs_data\" will be wiped and assigned\n#\n# $1: UBI volume of \"rootfs_data\" (e.g. ubi0_123)\nbcm4908_verify_rootfs_data() {\n\tlocal ubivol=\"$1\"\n\tlocal dir=/tmp/rootfs_data\n\tlocal seq=\"$(bcm4908_committed_image_seq)\"\n\n\t[ -z \"$seq\" ] && return\n\n\tmkdir $dir\n\tif ! mount -t ubifs /dev/$ubivol $dir; then\n\t\techo \"Failed to mount $ubivol UBI volume\" >&2\n\t\trmdir $dir\n\t\treturn\n\tfi\n\n\t# Wipe rootfs_data if it doesn't belong to us\n\t[ \"$(readlink $dir/.openwrt-image-seq)\" != \"$seq\" ] && {\n\t\techo \"Removing \\\"rootfs_data\\\" content\"\n\t\trm -rf $dir/..?* $dir/.[!.]* $dir/*\n\t}\n\n\t# If rootfs_data is clean (or was just wiped) claim it\n\t[ -z \"$(ls -A $dir)\" ] && {\n\t\techo \"Assigning \\\"rootfs_data\\\" to the current firmware\"\n\t\t# Claim this \"rootfs_data\"\n\t\tln -s $seq $dir/.openwrt-image-seq\n\t\t# Mark it ready to avoid \"mount_root\" wiping it again\n\t\tln -s $FS_STATE_READY $dir/.fs_state\n\t}\n\n\tumount $dir\n\trmdir $dir\n}\n"
  },
  {
    "path": "target/linux/bcm4908/base-files/lib/preinit/75_rootfs_prepare",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause\n\n. /lib/functions/bcm4908.sh\n\nrootfs_create() {\n\tlocal blocks\n\n\tblocks=$(cat /sys/class/ubi/ubi0/avail_eraseblocks)\n\t[ -z \"$blocks\" ] && {\n\t\techo \"Failed to read amount of available erase blocks\" >&2\n\t\treturn\n\t}\n\n\t# Use 80% of remaining flash size for \"rootfs_data\"\n\tubimkvol /dev/ubi0 -n 20 -N rootfs_data --lebs $((blocks / 100 * 80))\n\tmknod -m 0600 /dev/ubi0_20 c 252 21\n\n\tbcm4908_verify_rootfs_data ubi0_20\n}\n\nrootfs_prepare() {\n\t# Do nothing on CFE devices\n\tubinfo /dev/ubi0 -N metadata1 > /dev/null 2>&1 || return\n\n\t# Find UBI volume device (e.g. ubi0_123)\n\tlocal ubivol=\"$(grep rootfs_data /sys/devices/virtual/ubi/ubi*/ubi*/name | sed -n 's/.*\\(ubi\\d*_\\d*\\).*/\\1/p')\"\n\tif [ -n \"$ubivol\" ]; then\n\t\tbcm4908_verify_rootfs_data $ubivol\n\telse\n\t\techo \"Creating \\\"rootfs_data\\\" UBI volume\"\n\t\trootfs_create\n\tfi\n}\n\nboot_hook_add preinit_main rootfs_prepare\n"
  },
  {
    "path": "target/linux/bcm4908/base-files/lib/upgrade/platform.sh",
    "content": "# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause\n\n. /lib/functions/bcm4908.sh\n\nRAMFS_COPY_BIN=\"bcm4908img expr grep ln fdtget fw_printenv fw_setenv readlink tr\"\n\nPART_NAME=firmware\n\nBCM4908_FW_FORMAT=\nBCM4908_FW_BOARD_ID=\nBCM4908_FW_INT_IMG_FORMAT=\n\n# $(1): file to read from\n# $(2): offset in bytes\n# $(3): length in bytes\nget_content() {\n\tdd if=\"$1\" skip=$2 bs=1 count=$3 2>/dev/null\n}\n\n# $(1): file to read from\n# $(2): offset in bytes\nget_hex_u32_le() {\n\tdd if=\"$1\" skip=$2 bs=1 count=4 2>/dev/null | hexdump -v -e '1/4 \"%02x\"'\n}\n\n# $(1): file to read from\n# $(2): offset in bytes\nget_hex_u32_be() {\n\tdd if=\"$1\" skip=$2 bs=1 count=4 2>/dev/null | hexdump -v -e '1/1 \"%02x\"'\n}\n\nplatform_expected_image() {\n\tlocal machine=$(board_name)\n\n\tcase \"$machine\" in\n\t\tasus,gt-ac5300)\t\t\techo \"asus GT-AC5300\";;\n\t\tnetgear,r8000p)\t\t\techo \"chk U12H359T00_NETGEAR\";;\n\t\ttplink,archer-c2300-v1)\t\techo \"\";;\n\tesac\n}\n\nplatform_identify() {\n\tlocal magic\n\tlocal size\n\n\tmagic=$(get_hex_u32_be \"$1\" 0)\n\tcase \"$magic\" in\n\t\td00dfeed)\n\t\t\tBCM4908_FW_FORMAT=\"pkgtb\"\n\t\t\treturn\n\t\t\t;;\n\t\t2a23245e)\n\t\t\tlocal header_len=$((0x$(get_hex_u32_be \"$1\" 4)))\n\t\t\tlocal board_id_len=$(($header_len - 40))\n\n\t\t\tBCM4908_FW_FORMAT=\"chk\"\n\t\t\tBCM4908_FW_BOARD_ID=$(dd if=\"$1\" skip=40 bs=1 count=$board_id_len 2>/dev/null | hexdump -v -e '1/1 \"%c\"')\n\t\t\tmagic=$(get_hex_u32_be \"$1\" \"$header_len\")\n\t\t\t[ \"$magic\" = \"d00dfeed\" ] && {\n\t\t\t\tBCM4908_FW_INT_IMG_FORMAT=\"pkgtb\"\n\t\t\t} || {\n\t\t\t\tBCM4908_FW_INT_IMG_FORMAT=\"bcm4908img\"\n\t\t\t}\n\t\t\tBCM4908_FW_INT_IMG_EXTRACT_CMD=\"dd skip=$header_len iflag=skip_bytes\"\n\t\t\treturn\n\t\t;;\n\tesac\n\n\tsize=$(wc -c \"$1\" | cut -d ' ' -f 1)\n\n\tmagic=$(get_content \"$1\" $((size - 20 - 64 + 8)) 12)\n\tcase \"$magic\" in\n\t\tGT-AC5300)\n\t\t\tlocal size=$(wc -c \"$1\" | cut -d ' ' -f 1)\n\n\t\t\tBCM4908_FW_FORMAT=\"asus\"\n\t\t\tBCM4908_FW_BOARD_ID=$(get_content \"$1\" $((size - 20 - 64 + 8)) 12)\n\t\t\tBCM4908_FW_INT_IMG_FORMAT=\"bcm4908img\"\n\t\t\treturn\n\t\t;;\n\tesac\n\n\t# Detecting native format is a bit complex (it may start with CFE or\n\t# JFFS2) so just use bcm4908img instead of bash hacks.\n\t# Make it the last attempt as bcm4908img detects also vendor formats.\n\tbcm4908img info -i \"$1\" > /dev/null && {\n\t\tBCM4908_FW_FORMAT=\"bcm4908img\"\n\t\treturn\n\t}\n}\n\n#\n# pkgtb helpers\n#\n\nplatform_pkgtb_get_image_name() {\n\tlocal configuration=$($2 < $1 | fdtget - /configurations default)\n\t[ -z \"$configuration\" ] && {\n\t\techo \"Failed to read default configuration from pkgtb\" >&2\n\t\treturn\n\t}\n\n\tlocal image_name=$($2 < $1 | fdtget - /configurations/$configuration $3)\n\t[ -z \"$image_name\" ] && {\n\t\techo \"Failed to read $3 from pkgtb configuration \\\"$configuration\\\"\" >&2\n\t\treturn\n\t}\n\n\techo \"$image_name\"\n}\n\nplatform_pkgtb_get_image() {\n\tlocal cmd=\"${2:-cat}\"\n\n\tlocal image_name=$(platform_pkgtb_get_image_name \"$1\" \"$cmd\" \"$3\")\n\n\t$cmd < $1 | fdtget -p - /images/$image_name | grep -Eq \"^data$\" && {\n\t\t$cmd < $1 | fdtget -t r - /images/$image_name data\n\t\treturn\n\t}\n\n\t$cmd < $1 | fdtget -p - /images/$image_name | grep -Eq \"^data-position$\" && {\n\t\tlocal data_position=$($cmd < $1 | fdtget - /images/$image_name data-position)\n\t\tlocal data_size=$($cmd < $1 | fdtget - /images/$image_name data-size)\n\t\t$cmd < $1 2>/dev/null | dd skip=$data_position count=$data_size iflag=skip_bytes,count_bytes\n\t\treturn\n\t}\n\n\t$cmd < $1 | fdtget -p - /images/$image_name | grep -Eq \"^data-offset\" && {\n\t\tlocal data_offset=$($cmd < $1 | fdtget - /images/$image_name data-offset)\n\t\tlocal totalsize=$(get_hex_u32_be \"$1\" 4)\n\t\tlocal data_position=$(((0x$totalsize + data_offset + 3) & ~3))\n\t\tlocal data_size=$($cmd < $1 | fdtget - /images/$image_name data-size)\n\t\t$cmd < $1 2>/dev/null | dd skip=$data_position count=$data_size iflag=skip_bytes,count_bytes\n\t\treturn\n\t}\n}\n\nplatform_pkgtb_get_upgrade_index() {\n\tcase \"$(fw_printenv -l /tmp -n -c /tmp/env.config COMMITTED)\" in\n\t\t1) echo 2;;\n\t\t2) echo 1;;\n\t\t*) echo 1;;\n\tesac\n}\n\nplatform_pkgtb_commit() {\n\tlocal size=$((0x$(get_hex_u32_le /dev/ubi0_1 4)))\n\tlocal valid1=0\n\tlocal valid2=0\n\tlocal seq1\n\tlocal seq2\n\tlocal tmp\n\n\t# Read current values\n\tfor valid in $(fw_printenv -l /tmp -n -c /tmp/env.config VALID | tr ',' ' '); do\n\t\tcase \"$valid\" in\n\t\t\t1) valid0=1;;\n\t\t\t2) valid1=2;;\n\t\tesac\n\tdone\n\tseq0=$(fw_printenv -l /tmp -n -c /tmp/env.config SEQ | cut -d ',' -f 1)\n\tseq1=$(fw_printenv -l /tmp -n -c /tmp/env.config SEQ | cut -d ',' -f 2)\n\n\t# Calculate values\n\tcase \"$1\" in\n\t\t1) valid0=1; seq0=$(((seq1 + 1) % 1000));;\n\t\t2) valid1=2; seq1=$(((seq0 + 1) % 1000));;\n\tesac\n\n\t# Update variables\n\tfw_setenv -l /tmp -c /tmp/env.config COMMITTED \"$1\"\n\tfw_setenv -l /tmp -c /tmp/env.config VALID \"$valid0,$valid1\"\n\tfw_setenv -l /tmp -c /tmp/env.config SEQ \"$seq0,$seq1\"\n\n\t# Write\n\ttmp=$(cat /tmp/env.head /tmp/env.body | wc -c)\n\tcat /tmp/env.head /tmp/env.body | ubiupdatevol /dev/ubi0_1 -s $tmp -\n}\n\n#\n# check\n#\n\nplatform_check_pkgtb() {\n\tlocal cmd=\"${2:-cat}\"\n\n\t[ -n \"$(platform_pkgtb_get_image_name \"$1\" \"$cmd\" \"bootfs\")\" -a -n \"$(platform_pkgtb_get_image_name \"$1\" \"$cmd\" \"rootfs\")\" ]\n}\n\nplatform_check_image() {\n\t[ \"$#\" -gt 1 ] && return 1\n\n\tlocal expected_image=$(platform_expected_image)\n\tlocal error=0\n\n\tplatform_identify \"$1\"\n\t[ -z \"$BCM4908_FW_FORMAT\" ] && {\n\t\techo \"Invalid image type. Please use firmware specific for this device.\"\n\t\tnotify_firmware_broken\n\t\treturn 1\n\t}\n\techo \"Found $BCM4908_FW_FORMAT firmware for device ${BCM4908_FW_BOARD_ID:----}\"\n\n\tlocal expected_image=\"$(platform_expected_image)\"\n\t[ -n \"$expected_image\" -a -n \"$BCM4908_FW_BOARD_ID\" -a \"$BCM4908_FW_FORMAT $BCM4908_FW_BOARD_ID\" != \"$expected_image\" ] && {\n\t\techo \"Firmware doesn't match device ($expected_image)\"\n\t\terror=1\n\t}\n\n\tcase \"$BCM4908_FW_FORMAT\" in\n\t\t\"bcm4908img\")\n\t\t\tbcm4908img info -i \"$1\" > /dev/null || {\n\t\t\t\techo \"Failed to validate BCM4908 image\" >&2\n\t\t\t\tnotify_firmware_broken\n\t\t\t\treturn 1\n\t\t\t}\n\n\t\t\tbcm4908img bootfs -i \"$1\" ls | grep -q \"1-openwrt\" || {\n\t\t\t\t# OpenWrt images have 1-openwrt dummy file in the bootfs.\n\t\t\t\t# Don't allow backup if it's missing\n\t\t\t\tnotify_firmware_no_backup\n\t\t\t}\n\t\t\t;;\n\t\t\"pkgtb\")\n\t\t\tplatform_check_pkgtb \"$1\" || {\n\t\t\t\techo \"Failed to validate pkgtb firmware\" >&2\n\t\t\t\tnotify_firmware_broken\n\t\t\t\treturn 1\n\t\t\t}\n\t\t\t;;\n\t\t*)\n\t\t\tcase \"$BCM4908_FW_INT_IMG_FORMAT\" in\n\t\t\t\t\"bcm4908img\")\n\t\t\t\t\tbcm4908img info -i \"$1\" > /dev/null || {\n\t\t\t\t\t\techo \"Failed to validate BCM4908 image\" >&2\n\t\t\t\t\t\tnotify_firmware_broken\n\t\t\t\t\t\treturn 1\n\t\t\t\t\t}\n\n\t\t\t\t\tbcm4908img bootfs -i \"$1\" ls | grep -q \"1-openwrt\" || {\n\t\t\t\t\t\t# OpenWrt images have 1-openwrt dummy file in the bootfs.\n\t\t\t\t\t\t# Don't allow backup if it's missing\n\t\t\t\t\t\tnotify_firmware_no_backup\n\t\t\t\t\t}\n\t\t\t\t\t;;\n\t\t\t\t\"pkgtb\")\n\t\t\t\t\tplatform_check_pkgtb \"$1\" \"$BCM4908_FW_INT_IMG_EXTRACT_CMD\" || {\n\t\t\t\t\t\techo \"Failed to validate pkgtb firmware\" >&2\n\t\t\t\t\t\tnotify_firmware_broken\n\t\t\t\t\t\treturn 1\n\t\t\t\t\t}\n\t\t\t\t\t;;\n\t\t\tesac\n\t\t\t;;\n\tesac\n\n\treturn $error\n}\n\n#\n# upgrade\n#\n\nplatform_pkgtb_clean_rootfs_data() {\n\tlocal ubidev=$(nand_find_ubi $CI_UBIPART)\n\tlocal ubivol=\"$(nand_find_volume $ubidev rootfs_data)\"\n\n\tbcm4908_verify_rootfs_data \"$ubivol\"\n}\n\nplatform_do_upgrade_pkgtb() {\n\tlocal cmd=\"${2:-cat}\"\n\tlocal size\n\tlocal idx bootfs_id rootfs_id\n\n\tbcm4908_pkgtb_setup_env_config\n\n\tidx=$(platform_pkgtb_get_upgrade_index)\n\tcase \"$idx\" in\n\t\t1) bootfs_id=3; rootfs_id=4;;\n\t\t2) bootfs_id=5; rootfs_id=6;;\n\tesac\n\n\tsize=$(platform_pkgtb_get_image \"$1\" \"$cmd\" \"bootfs\" | wc -c)\n\tubirmvol /dev/ubi0 -N bootfs$idx\n\tubimkvol /dev/ubi0 -n $bootfs_id -N bootfs$idx -t static -s $size\n\tplatform_pkgtb_get_image \"$1\" \"$cmd\" \"bootfs\" | ubiupdatevol /dev/ubi0_$bootfs_id -s $size -\n\n\tsize=$(platform_pkgtb_get_image \"$1\" \"$cmd\" \"rootfs\" | wc -c)\n\tubirmvol /dev/ubi0 -N rootfs$idx\n\tubimkvol /dev/ubi0 -n $rootfs_id -N rootfs$idx -t dynamic -s $size\n\tplatform_pkgtb_get_image \"$1\" \"$cmd\" \"rootfs\" | ubiupdatevol /dev/ubi0_$rootfs_id -s $size -\n\n\tplatform_pkgtb_commit $idx\n\n\tCI_UBIPART=\"image\"\n\tplatform_pkgtb_clean_rootfs_data\n\tnand_do_upgrade_success\n}\n\n# $1: cferam index increment value\nplatform_calc_new_cferam() {\n\tlocal inc=\"$1\"\n\tlocal dir=\"/tmp/sysupgrade-bcm4908\"\n\n\tlocal mtd=$(find_mtd_part bootfs)\n\t[ -z \"$mtd\" ] && {\n\t\techo \"Failed to find bootfs partition\" >&2\n\t\treturn\n\t}\n\n\trm -fR $dir\n\tmkdir -p $dir\n\tmount -t jffs2 -o ro $mtd $dir || {\n\t\techo \"Failed to mount bootfs partition $mtd\" >&2\n\t\trm -fr $dir\n\t\treturn\n\t}\n\n\tlocal idx=$(ls $dir/cferam.??? | sed -n 's/.*cferam\\.\\(\\d\\d\\d\\)/\\1/p')\n\t[ -z \"$idx\" ] && {\n\t\techo \"Failed to find cferam current index\" >&2\n\t\trm -fr $dir\n\t\treturn\n\t}\n\n\tumount $dir\n\trm -fr $dir\n\n\tidx=$(($(expr $idx + $inc) % 1000))\n\n\techo $(printf \"cferam.%03d\" $idx)\n}\n\nplatform_do_upgrade_ubi() {\n\tlocal dir=\"/tmp/sysupgrade-bcm4908\"\n\tlocal inc=1\n\n\t# Verify new bootfs size\n\tlocal mtd_bootfs_size=$(grep \"\\\"bootfs\\\"\" /proc/mtd | sed \"s/mtd[0-9]*:[ \\t]*\\([^ \\t]*\\).*/\\1/\")\n\t[ -z \"$mtd_bootfs_size\" ] && {\n\t\techo \"Unable to find \\\"bootfs\\\" partition size\"\n\t\treturn\n\t}\n\tmtd_bootfs_size=$((0x$mtd_bootfs_size))\n\tlocal img_bootfs_size=$(bcm4908img extract -i \"$1\" -t bootfs | wc -c)\n\t[ $img_bootfs_size -gt $mtd_bootfs_size ] && {\n\t\techo \"New bootfs doesn't fit MTD partition.\"\n\t\treturn\n\t}\n\n\t# Find cferam name for new firmware\n\t# For UBI we always flash \"firmware\" so don't increase cferam index if\n\t# there is \"fallback\". That could result in cferam.999 & cferam.001\n\t[ -n \"$(find_mtd_index backup)\" -o -n \"$(find_mtd_index fallback)\" ] && inc=0\n\tlocal cferam=$(platform_calc_new_cferam $inc)\n\t[ -z \"$cferam\" ] && exit 1\n\n\t# Prepare new firmware\n\tbcm4908img bootfs -i \"$1\" mv cferam.000 $cferam || {\n\t\techo \"Failed to rename cferam.000 to $cferam\" >&2\n\t\texit 1\n\t}\n\n\t# Extract rootfs for further flashing\n\trm -fr $dir\n\tmkdir -p $dir\n\tbcm4908img extract -i \"$1\" -t rootfs > $dir/root || {\n\t\techo \"Failed to extract rootfs\" >&2\n\t\trm -fr $dir\n\t\texit 1\n\t}\n\n\t# Flash bootfs MTD partition with new one\n\tmtd erase bootfs || {\n\t\techo \"Failed to erase bootfs\" >&2\n\t\trm -fr $dir\n\t\texit 1\n\t}\n\tbcm4908img extract -i \"$1\" -t bootfs | mtd write - bootfs || {\n\t\techo \"Failed to flash bootfs\" >&2\n\t\trm -fr $dir\n\t\texit 1\n\t}\n\n\tnand_do_upgrade $dir/root\n}\n\nplatform_do_upgrade() {\n\tplatform_identify \"$1\"\n\n\t# Try NAND aware UBI upgrade for OpenWrt images\n\tcase \"$BCM4908_FW_FORMAT\" in\n\t\t\"bcm4908img\")\n\t\t\tbcm4908img bootfs -i \"$1\" ls | grep -q \"1-openwrt\" && platform_do_upgrade_ubi \"$1\"\n\t\t\t;;\n\t\t\"pkgtb\")\n\t\t\tplatform_do_upgrade_pkgtb \"$1\"\n\t\t\t;;\n\t\t*)\n\t\t\tcase \"$BCM4908_FW_INT_IMG_FORMAT\" in\n\t\t\t\t\"bcm4908img\")\n\t\t\t\t\tbcm4908img bootfs -i \"$1\" ls | grep -q \"1-openwrt\" && platform_do_upgrade_ubi \"$1\"\n\t\t\t\t\t;;\n\t\t\t\t\"pkgtb\")\n\t\t\t\t\tplatform_do_upgrade_pkgtb \"$1\" \"$BCM4908_FW_INT_IMG_EXTRACT_CMD\"\n\t\t\t\t\t;;\n\t\t\t\t*)\n\t\t\t\t\techo \"NAND aware sysupgrade is unsupported for $BCM4908_FW_FORMAT format\"\n\t\t\t\t\t;;\n\t\t\tesac\n\t\t\t;;\n\tesac\n\n\t# Above calls exit on success.\n\t# If we got here it isn't OpenWrt image or something went wrong.\n\t[ \"$BCM4908_FW_FORMAT\" = \"pkgtb\" -o \"$BCM4908_FW_INT_IMG_FORMAT\" = \"pkgtb\" ] && {\n\t\techo \"Failed to upgrade pkgtb. Fallback to raw flashing is impossible for this format.\" >&2\n\t\texit 1\n\t}\n\techo \"Writing whole image to NAND flash. All erase counters will be lost.\"\n\n\t# Find cferam name for new firmware\n\tlocal cferam=$(platform_calc_new_cferam 1)\n\t[ -z \"$cferam\" ] && exit 1\n\n\t# Prepare new firmware\n\tbcm4908img bootfs -i \"$1\" mv cferam.000 $cferam || {\n\t\techo \"Failed to rename cferam.000 to $cferam\" >&2\n\t\texit 1\n\t}\n\n\t# Jush flash firmware partition as is\n\t[ -n \"$(find_mtd_index backup)\" ] && PART_NAME=backup\n\t[ -n \"$(find_mtd_index fallback)\" ] && PART_NAME=fallback\n\tmtd erase $PART_NAME\n\tdefault_do_upgrade \"$1\" \"bcm4908img extract -t firmware\"\n}\n"
  },
  {
    "path": "target/linux/bcm4908/config-5.10",
    "content": "CONFIG_64BIT=y\nCONFIG_ARCH_BCM4908=y\nCONFIG_ARCH_DMA_ADDR_T_64BIT=y\nCONFIG_ARCH_KEEP_MEMBLOCK=y\nCONFIG_ARCH_MMAP_RND_BITS=18\nCONFIG_ARCH_MMAP_RND_BITS_MAX=24\nCONFIG_ARCH_MMAP_RND_BITS_MIN=18\nCONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11\nCONFIG_ARCH_PROC_KCORE_TEXT=y\nCONFIG_ARCH_SELECT_MEMORY_MODEL=y\nCONFIG_ARCH_SPARSEMEM_DEFAULT=y\nCONFIG_ARCH_SPARSEMEM_ENABLE=y\nCONFIG_ARCH_STACKWALK=y\nCONFIG_ARCH_SUSPEND_POSSIBLE=y\nCONFIG_ARM64=y\nCONFIG_ARM64_4K_PAGES=y\nCONFIG_ARM64_PAGE_SHIFT=12\nCONFIG_ARM64_PA_BITS=48\nCONFIG_ARM64_PA_BITS_48=y\nCONFIG_ARM64_PTR_AUTH=y\nCONFIG_ARM64_SVE=y\nCONFIG_ARM64_TAGGED_ADDR_ABI=y\nCONFIG_ARM64_VA_BITS=39\nCONFIG_ARM64_VA_BITS_39=y\nCONFIG_ARM_AMBA=y\nCONFIG_ARM_ARCH_TIMER=y\nCONFIG_ARM_ARCH_TIMER_EVTSTREAM=y\nCONFIG_ARM_GIC=y\nCONFIG_ARM_GIC_V3=y\nCONFIG_ARM_GIC_V3_ITS=y\nCONFIG_ARM_PSCI_FW=y\nCONFIG_AUDIT_ARCH_COMPAT_GENERIC=y\nCONFIG_B53=y\nCONFIG_BCM4908_ENET=y\nCONFIG_BCM7038_WDT=y\nCONFIG_BCM7XXX_PHY=y\nCONFIG_BCM_NET_PHYLIB=y\nCONFIG_BCM_PMB=y\n# CONFIG_BLK_DEV_INITRD is not set\nCONFIG_BLK_PM=y\nCONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y\nCONFIG_CLKDEV_LOOKUP=y\nCONFIG_CLONE_BACKWARDS=y\nCONFIG_CMDLINE=\"earlycon=bcm63xx_uart,0xff800640 console=ttyS0,115200\"\nCONFIG_CMDLINE_FORCE=y\nCONFIG_COMMON_CLK=y\n# CONFIG_COMPAT_32BIT_TIME is not set\nCONFIG_CPU_RMAP=y\nCONFIG_CRC16=y\nCONFIG_CRYPTO_DEFLATE=y\nCONFIG_CRYPTO_HASH_INFO=y\nCONFIG_CRYPTO_LZO=y\nCONFIG_CRYPTO_RNG2=y\nCONFIG_CRYPTO_ZSTD=y\nCONFIG_DCACHE_WORD_ACCESS=y\nCONFIG_DMA_DIRECT_REMAP=y\nCONFIG_DMA_REMAP=y\nCONFIG_DTC=y\nCONFIG_EDAC_SUPPORT=y\nCONFIG_FIXED_PHY=y\nCONFIG_FIX_EARLYCON_MEM=y\nCONFIG_FRAME_POINTER=y\nCONFIG_FW_LOADER_PAGED_BUF=y\nCONFIG_GENERIC_ALLOCATOR=y\nCONFIG_GENERIC_ARCH_TOPOLOGY=y\nCONFIG_GENERIC_BUG=y\nCONFIG_GENERIC_BUG_RELATIVE_POINTERS=y\nCONFIG_GENERIC_CLOCKEVENTS=y\nCONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y\nCONFIG_GENERIC_CPU_AUTOPROBE=y\nCONFIG_GENERIC_CPU_VULNERABILITIES=y\nCONFIG_GENERIC_CSUM=y\nCONFIG_GENERIC_EARLY_IOREMAP=y\nCONFIG_GENERIC_GETTIMEOFDAY=y\nCONFIG_GENERIC_IDLE_POLL_SETUP=y\nCONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y\nCONFIG_GENERIC_IRQ_MULTI_HANDLER=y\nCONFIG_GENERIC_IRQ_SHOW=y\nCONFIG_GENERIC_IRQ_SHOW_LEVEL=y\nCONFIG_GENERIC_MSI_IRQ=y\nCONFIG_GENERIC_MSI_IRQ_DOMAIN=y\nCONFIG_GENERIC_PCI_IOMAP=y\nCONFIG_GENERIC_PHY=y\nCONFIG_GENERIC_PINCONF=y\nCONFIG_GENERIC_PINCTRL_GROUPS=y\nCONFIG_GENERIC_PINMUX_FUNCTIONS=y\nCONFIG_GENERIC_SCHED_CLOCK=y\nCONFIG_GENERIC_SMP_IDLE_THREAD=y\nCONFIG_GENERIC_STRNCPY_FROM_USER=y\nCONFIG_GENERIC_STRNLEN_USER=y\nCONFIG_GENERIC_TIME_VSYSCALL=y\nCONFIG_GPIOLIB=y\nCONFIG_GPIO_GENERIC=y\nCONFIG_GPIO_GENERIC_PLATFORM=y\nCONFIG_GRO_CELLS=y\nCONFIG_HANDLE_DOMAIN_IRQ=y\nCONFIG_HARDIRQS_SW_RESEND=y\nCONFIG_HAS_DMA=y\nCONFIG_HAS_IOMEM=y\nCONFIG_HOLES_IN_ZONE=y\nCONFIG_HZ_PERIODIC=y\nCONFIG_I2C=y\nCONFIG_I2C_BOARDINFO=y\nCONFIG_I2C_BRCMSTB=y\nCONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000\nCONFIG_IRQCHIP=y\nCONFIG_IRQ_DOMAIN=y\nCONFIG_IRQ_DOMAIN_HIERARCHY=y\nCONFIG_IRQ_FORCED_THREADING=y\nCONFIG_IRQ_WORK=y\nCONFIG_LEDS_GPIO=y\nCONFIG_LIBFDT=y\nCONFIG_LOCK_DEBUGGING_SUPPORT=y\nCONFIG_LOCK_SPIN_ON_OWNER=y\nCONFIG_LZO_COMPRESS=y\nCONFIG_LZO_DECOMPRESS=y\nCONFIG_MDIO_BCM_UNIMAC=y\nCONFIG_MDIO_BUS=y\nCONFIG_MDIO_DEVICE=y\nCONFIG_MDIO_DEVRES=y\nCONFIG_MEMFD_CREATE=y\nCONFIG_MFD_SYSCON=y\nCONFIG_MIGRATION=y\nCONFIG_MODULES_USE_ELF_RELA=y\nCONFIG_MTD_CMDLINE_PARTS=y\nCONFIG_MTD_NAND_BRCMNAND=y\nCONFIG_MTD_NAND_CORE=y\nCONFIG_MTD_NAND_ECC=y\nCONFIG_MTD_NAND_ECC_SW_HAMMING=y\nCONFIG_MTD_OF_PARTS_BCM4908=y\n# CONFIG_MTD_OF_PARTS_LINKSYS_NS is not set\nCONFIG_MTD_RAW_NAND=y\nCONFIG_MTD_SPLIT_CFE_BOOTFS=y\n# CONFIG_MTD_SPLIT_SQUASHFS_ROOT is not set\nCONFIG_MTD_UBI=y\nCONFIG_MTD_UBI_BEB_LIMIT=20\nCONFIG_MTD_UBI_BLOCK=y\nCONFIG_MTD_UBI_WL_THRESHOLD=4096\nCONFIG_MUTEX_SPIN_ON_OWNER=y\nCONFIG_NEED_DMA_MAP_STATE=y\nCONFIG_NEED_SG_DMA_LENGTH=y\nCONFIG_NET_DEVLINK=y\nCONFIG_NET_DSA=y\nCONFIG_NET_DSA_BCM_SF2=y\nCONFIG_NET_DSA_TAG_BRCM=y\nCONFIG_NET_DSA_TAG_BRCM_COMMON=y\nCONFIG_NET_DSA_TAG_BRCM_LEGACY=y\nCONFIG_NET_DSA_TAG_BRCM_PREPEND=y\nCONFIG_NET_FLOW_LIMIT=y\nCONFIG_NET_SWITCHDEV=y\nCONFIG_NO_IOPORT_MAP=y\nCONFIG_NR_CPUS=4\nCONFIG_OF=y\nCONFIG_OF_ADDRESS=y\nCONFIG_OF_EARLY_FLATTREE=y\nCONFIG_OF_FLATTREE=y\nCONFIG_OF_GPIO=y\nCONFIG_OF_IRQ=y\nCONFIG_OF_KOBJ=y\nCONFIG_OF_MDIO=y\nCONFIG_OF_NET=y\nCONFIG_PADATA=y\nCONFIG_PARTITION_PERCPU=y\nCONFIG_PGTABLE_LEVELS=3\nCONFIG_PHYLIB=y\nCONFIG_PHYLINK=y\nCONFIG_PHYS_ADDR_T_64BIT=y\nCONFIG_PHY_BRCM_USB=y\nCONFIG_PINCTRL=y\nCONFIG_PINCTRL_BCM4908=y\n# CONFIG_PINCTRL_SINGLE is not set\nCONFIG_PM=y\nCONFIG_PM_CLK=y\nCONFIG_PM_GENERIC_DOMAINS=y\nCONFIG_PM_GENERIC_DOMAINS_OF=y\nCONFIG_POWER_RESET=y\nCONFIG_POWER_RESET_SYSCON=y\nCONFIG_POWER_SUPPLY=y\nCONFIG_QUEUED_RWLOCKS=y\nCONFIG_QUEUED_SPINLOCKS=y\nCONFIG_RATIONAL=y\nCONFIG_REGMAP=y\nCONFIG_REGMAP_MMIO=y\nCONFIG_RELOCATABLE=y\nCONFIG_RFS_ACCEL=y\nCONFIG_RODATA_FULL_DEFAULT_ENABLED=y\nCONFIG_RPS=y\nCONFIG_RWSEM_SPIN_ON_OWNER=y\n# CONFIG_SERIAL_8250 is not set\nCONFIG_SERIAL_BCM63XX=y\nCONFIG_SERIAL_BCM63XX_CONSOLE=y\nCONFIG_SGL_ALLOC=y\nCONFIG_SMP=y\nCONFIG_SPARSEMEM_VMEMMAP_ENABLE=y\nCONFIG_SPARSE_IRQ=y\nCONFIG_SRCU=y\nCONFIG_SWIOTLB=y\nCONFIG_SWPHY=y\nCONFIG_SYSCTL_EXCEPTION_TRACE=y\nCONFIG_SYS_SUPPORTS_HUGETLBFS=y\nCONFIG_THREAD_INFO_IN_TASK=y\nCONFIG_TICK_CPU_ACCOUNTING=y\nCONFIG_TIMER_OF=y\nCONFIG_TIMER_PROBE=y\nCONFIG_TREE_RCU=y\nCONFIG_TREE_SRCU=y\nCONFIG_UBIFS_FS=y\nCONFIG_UNMAP_KERNEL_AT_EL0=y\nCONFIG_USB_SUPPORT=y\nCONFIG_VMAP_STACK=y\nCONFIG_WATCHDOG_CORE=y\nCONFIG_XPS=y\nCONFIG_XXHASH=y\nCONFIG_ZLIB_DEFLATE=y\nCONFIG_ZLIB_INFLATE=y\nCONFIG_ZONE_DMA32=y\nCONFIG_ZSTD_COMPRESS=y\nCONFIG_ZSTD_DECOMPRESS=y\n"
  },
  {
    "path": "target/linux/bcm4908/files-5.10/drivers/net/ethernet/broadcom/unimac.h",
    "content": "/* SPDX-License-Identifier: GPL-2.0-only */\n#ifndef __UNIMAC_H\n#define __UNIMAC_H\n\n#define UMAC_HD_BKP_CTRL\t\t0x004\n#define  HD_FC_EN\t\t\t(1 << 0)\n#define  HD_FC_BKOFF_OK\t\t\t(1 << 1)\n#define  IPG_CONFIG_RX_SHIFT\t\t2\n#define  IPG_CONFIG_RX_MASK\t\t0x1F\n#define UMAC_CMD\t\t\t0x008\n#define  CMD_TX_EN\t\t\t(1 << 0)\n#define  CMD_RX_EN\t\t\t(1 << 1)\n#define  CMD_SPEED_10\t\t\t0\n#define  CMD_SPEED_100\t\t\t1\n#define  CMD_SPEED_1000\t\t\t2\n#define  CMD_SPEED_2500\t\t\t3\n#define  CMD_SPEED_SHIFT\t\t2\n#define  CMD_SPEED_MASK\t\t\t3\n#define  CMD_PROMISC\t\t\t(1 << 4)\n#define  CMD_PAD_EN\t\t\t(1 << 5)\n#define  CMD_CRC_FWD\t\t\t(1 << 6)\n#define  CMD_PAUSE_FWD\t\t\t(1 << 7)\n#define  CMD_RX_PAUSE_IGNORE\t\t(1 << 8)\n#define  CMD_TX_ADDR_INS\t\t(1 << 9)\n#define  CMD_HD_EN\t\t\t(1 << 10)\n#define  CMD_SW_RESET_OLD\t\t(1 << 11)\n#define  CMD_SW_RESET\t\t\t(1 << 13)\n#define  CMD_LCL_LOOP_EN\t\t(1 << 15)\n#define  CMD_AUTO_CONFIG\t\t(1 << 22)\n#define  CMD_CNTL_FRM_EN\t\t(1 << 23)\n#define  CMD_NO_LEN_CHK\t\t\t(1 << 24)\n#define  CMD_RMT_LOOP_EN\t\t(1 << 25)\n#define  CMD_RX_ERR_DISC\t\t(1 << 26)\n#define  CMD_PRBL_EN\t\t\t(1 << 27)\n#define  CMD_TX_PAUSE_IGNORE\t\t(1 << 28)\n#define  CMD_TX_RX_EN\t\t\t(1 << 29)\n#define  CMD_RUNT_FILTER_DIS\t\t(1 << 30)\n#define UMAC_MAC0\t\t\t0x00c\n#define UMAC_MAC1\t\t\t0x010\n#define UMAC_MAX_FRAME_LEN\t\t0x014\n#define UMAC_PAUSE_QUANTA\t\t0x018\n#define UMAC_MODE\t\t\t0x044\n#define  MODE_LINK_STATUS\t\t(1 << 5)\n#define UMAC_FRM_TAG0\t\t\t0x048\t\t/* outer tag */\n#define UMAC_FRM_TAG1\t\t\t0x04c\t\t/* inner tag */\n#define UMAC_TX_IPG_LEN\t\t\t0x05c\n#define UMAC_EEE_CTRL\t\t\t0x064\n#define  EN_LPI_RX_PAUSE\t\t(1 << 0)\n#define  EN_LPI_TX_PFC\t\t\t(1 << 1)\n#define  EN_LPI_TX_PAUSE\t\t(1 << 2)\n#define  EEE_EN\t\t\t\t(1 << 3)\n#define  RX_FIFO_CHECK\t\t\t(1 << 4)\n#define  EEE_TX_CLK_DIS\t\t\t(1 << 5)\n#define  DIS_EEE_10M\t\t\t(1 << 6)\n#define  LP_IDLE_PREDICTION_MODE\t(1 << 7)\n#define UMAC_EEE_LPI_TIMER\t\t0x068\n#define UMAC_EEE_WAKE_TIMER\t\t0x06C\n#define UMAC_EEE_REF_COUNT\t\t0x070\n#define  EEE_REFERENCE_COUNT_MASK\t0xffff\n#define UMAC_RX_IPG_INV\t\t\t0x078\n#define UMAC_MACSEC_PROG_TX_CRC\t\t0x310\n#define UMAC_MACSEC_CTRL\t\t0x314\n#define UMAC_PAUSE_CTRL\t\t\t0x330\n#define UMAC_TX_FLUSH\t\t\t0x334\n#define UMAC_RX_FIFO_STATUS\t\t0x338\n#define UMAC_TX_FIFO_STATUS\t\t0x33c\n\n#endif\n"
  },
  {
    "path": "target/linux/bcm4908/generic/target.mk",
    "content": "BOARDNAME:=Generic\n"
  },
  {
    "path": "target/linux/bcm4908/image/Makefile",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n\ninclude $(TOPDIR)/rules.mk\ninclude $(INCLUDE_DIR)/image.mk\n\nDEVICE_VARS += ASUS_PRODUCTID ASUS_BUILD_NO ASUS_FW_REV ASUS_EXT_NO\nDEVICE_VARS += NETGEAR_BOARD_ID NETGEAR_REGION\nDEVICE_VARS += PKGTB_ITS\n\ndefine Image/Prepare\n\tcp bootfs-generic.its $(KDIR)/\n\tsed -i \"s=\\$$$${images_dir}=$(STAGING_DIR_IMAGE)=\" $(KDIR)/bootfs-generic.its\n\tsed -i \"s=\\$$$${dts_dir}=$(DTS_DIR)=\" $(KDIR)/bootfs-generic.its\nendef\n\ndefine Build/bootfs\n\tcat $@ | $(STAGING_DIR_HOST)/bin/lzma e -eos -si -so > $@.tmp\n\tmv $@.tmp $@\n\tsed -i \"s=\\$${kernel}=$@=\" $(KDIR)/bootfs-generic.its\n\tPATH=$(LINUX_DIR)/scripts/dtc:$(PATH) mkimage -f $(KDIR)/bootfs-generic.its $(KDIR)/bootfs-generic.itb\nendef\n\ndefine Build/bcm4908asus\n\t$(STAGING_DIR_HOST)/bin/bcm4908asus create -i $@ \\\n\t\t-p $(ASUS_PRODUCTID) -b $(ASUS_BUILD_NO) -f $(ASUS_FW_REV) \\\n\t\t-e $(ASUS_EXT_NO)\nendef\n\ndefine Build/bcm4908img\n\trm -fr $@-bootfs\n\tmkdir -p $@-bootfs\n\tcp -r $(DEVICE_NAME)/* $@-bootfs/\n\ttouch $@-bootfs/1-openwrt\n\tcp $(DTS_DIR)/$(firstword $(DEVICE_DTS)).dtb $@-bootfs/94908.dtb\n\tcp $(KDIR)/bcm63xx-cfe/$(subst _,$(comma),$(DEVICE_NAME))/cferam.000 $@-bootfs/\n\tcp $(IMAGE_KERNEL) $@-bootfs/vmlinux.lz\n\n\t$(STAGING_DIR_HOST)/bin/mkfs.jffs2 --pad=0x800000 --little-endian --squash-uids \\\n\t\t-v -e 128KiB -o $@-bootfs.jffs2 -d $@-bootfs -m none -n\n\t$(STAGING_DIR_HOST)/bin/bcm4908img create $@.new -f $@-bootfs.jffs2 \\\n\t\t-a 0x20000 -f $@\n\tmv $@.new $@\nendef\n\ndefine Build/bcm4908kernel\n\t$(STAGING_DIR_HOST)/bin/bcm4908kernel -i $@ -o $@.new\n\tmv $@.new $@\nendef\n\ndefine Build/bcm4908lzma\n\t$(STAGING_DIR_HOST)/bin/lzma e -lc1 -lp2 -pb2 -d22 $@ $@.new\n\tmv $@.new $@\nendef\n\ndefine Build/pkgtb\n\tmv $@ $@.rootfs\n\tcp $(PKGTB_ITS) $@.its\n\tsed -i \"s=\\$${bootfs}=$(KDIR)/bootfs-generic.itb=\" $@.its\n\tsed -i \"s=\\$${rootfs}=$@.rootfs=\" $@.its\n\tPATH=$(LINUX_DIR)/scripts/dtc:$(PATH) mkimage -f $@.its $@\nendef\n\ndefine Device/Default\n  KERNEL := kernel-bin | bcm4908lzma | bcm4908kernel\n  KERNEL_DEPENDS = $$(wildcard $(DTS_DIR)/$$(DEVICE_DTS).dts)\n  KERNEL_INITRAMFS_SUFFIX := .bin\n  KERNEL_INITRAMFS := kernel-bin | bcm4908lzma | bcm4908kernel\n  FILESYSTEMS := squashfs\n  KERNEL_NAME := Image\n  DEVICE_IMG_NAME = $$(DEVICE_IMG_PREFIX)-$$(1).$$(2)\n  BLOCKSIZE := 128k\n  PAGESIZE := 2048\n  IMAGE/bin := append-ubi | bcm4908img\nendef\n\ndefine Device/asus_gt-ac5300\n  DEVICE_VENDOR := Asus\n  DEVICE_MODEL := GT-AC5300\n  DEVICE_DTS := broadcom/bcm4908/bcm4908-asus-gt-ac5300\n  IMAGES := bin\n  IMAGE/bin := append-ubi | bcm4908img | bcm4908asus\n  ASUS_PRODUCTID := GT-AC5300\n  ASUS_BUILD_NO := 384\n  ASUS_FW_REV := 3.0.0.4\n  ASUS_EXT_NO := 21140\nendef\nTARGET_DEVICES += asus_gt-ac5300\n\ndefine Device/netgear_r8000p\n  DEVICE_VENDOR := Netgear\n  DEVICE_MODEL := R8000P\n  DEVICE_DTS := broadcom/bcm4908/bcm4906-netgear-r8000p\n  IMAGES := bin\n  IMAGE/chk := append-ubi | bcm4908img | netgear-chk\n  NETGEAR_BOARD_ID := U12H359T00_NETGEAR\n  NETGEAR_REGION := 1\nendef\nTARGET_DEVICES += netgear_r8000p\n\ndefine Device/tplink_archer-c2300-v1\n  DEVICE_VENDOR := TP-Link\n  DEVICE_MODEL := Archer C2300\n  DEVICE_VARIANT := v1\n  DEVICE_DTS := broadcom/bcm4908/bcm4906-tplink-archer-c2300-v1\n  IMAGES := bin\n  IMAGE/bin := append-ubi | bcm4908img\n  BROKEN := y\nendef\nTARGET_DEVICES += tplink_archer-c2300-v1\n\ndefine Device/netgear\n  DEVICE_VENDOR := NETGEAR\n  KERNEL := kernel-bin | bootfs\n  IMAGES := chk\n  IMAGE/chk := append-rootfs | pkgtb | netgear-chk\n  NETGEAR_REGION := 1\nendef\n\ndefine Device/netgear_raxe500\n  DEVICE_MODEL := RAXE500\n  $(Device/netgear)\n  PKGTB_ITS := pkgtb-bcm4908.its\n  NETGEAR_BOARD_ID := U12H449T00_NETGEAR\nendef\n# TARGET_DEVICES += netgear_raxe500\n\n$(eval $(call BuildImage))\n"
  },
  {
    "path": "target/linux/bcm4908/image/asus_gt-ac5300/rom/etc/image_ident",
    "content": "@(#) $imageversion: HND1731918 $\n@(#) $imageversion: HND1731918 $\n"
  },
  {
    "path": "target/linux/bcm4908/image/asus_gt-ac5300/rom/etc/image_version",
    "content": "HND1731918\n"
  },
  {
    "path": "target/linux/bcm4908/image/bootfs-generic.its",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n/dts-v1/;\n\n/ {\n\tdescription = \"OpenWrt bootfs image\";\n\t#address-cells = <1>;\n\n\timages {\n\t\tatf {\n\t\t\tdescription = \"ATF\";\n\t\t\tdata = /incbin/(\"${images_dir}/bl31.bin\");\n\t\t\ttype = \"firmware\";\n\t\t\tarch = \"arm64\";\n\t\t\tos = \"arm-trusted-firmware\";\n\t\t\tcompression = \"none\";\n\t\t\tload = <0x4000>;\n\t\t\tentry = <0x4000>;\n\n\t\t\thash-1 {\n\t\t\t\talgo = \"sha256\";\n\t\t\t};\n\t\t};\n\n\t\tuboot {\n\t\t\tdescription = \"U-Boot\";\n\t\t\tdata = /incbin/(\"${images_dir}/u-boot/u-boot-nodtb.bin\");\n\t\t\tos = \"U-Boot\";\n\t\t\tarch = \"arm64\";\n\t\t\tcompression = \"none\";\n\t\t\tload = <0x1000000>;\n\t\t\tentry = <0x1000000>;\n\n\t\t\thash-1 {\n\t\t\t\talgo = \"sha256\";\n\t\t\t};\n\t\t};\n\n\t\tkernel {\n\t\t\tdescription = \"Linux kernel\";\n\t\t\tdata = /incbin/(\"${kernel}\");\n\t\t\ttype = \"kernel\";\n\t\t\tos = \"linux\";\n\t\t\tarch = \"arm64\";\n\t\t\tcompression = \"lzma\";\n\t\t\tload = <0x80000>;\n\t\t\tentry = <0x80000>;\n\n\t\t\thash-1 {\n\t\t\t\talgo = \"sha256\";\n\t\t\t};\n\t\t};\n\n\t\tfdt_uboot {\n\t\t\tdescription = \"dtb\";\n\t\t\tdata = /incbin/(\"${images_dir}/u-boot/u-boot.dtb\");\n\t\t\ttype = \"flat_dt\";\n\t\t\tcompression = \"none\";\n\n\t\t\thash-1 {\n\t\t\t\talgo = \"sha256\";\n\t\t\t};\n\t\t};\n\n\t\tfdt_GTAX6000 {\n\t\t\tdescription = \"dtb\";\n\t\t\tdata = /incbin/(\"${images_dir}/u-boot/GTAX6000.dtb\");\n\t\t\ttype = \"flat_dt\";\n\t\t\tcompression = \"none\";\n\n\t\t\thash-1 {\n\t\t\t\talgo = \"sha256\";\n\t\t\t};\n\t\t};\n\n\t\tfdt_uboot_RAX220 {\n\t\t\tdescription = \"dtb\";\n\t\t\tdata = /incbin/(\"${images_dir}/u-boot/RAX220.dtb\");\n\t\t\ttype = \"flat_dt\";\n\t\t\tcompression = \"none\";\n\n\t\t\thash-1 {\n\t\t\t\talgo = \"sha256\";\n\t\t\t};\n\t\t};\n\n\t\tfdt_linux_RAX220 {\n\t\t\tdescription = \"dtb\";\n\t\t\tdata = /incbin/(\"${dts_dir}/broadcom/bcm4908/bcm4908-netgear-raxe500.dtb\");\n\t\t\tarch = \"arm64\";\n\t\t\ttype = \"flat_dt\";\n\t\t\tcompression = \"none\";\n\t\t};\n\t};\n\n\tconfigurations {\n\t\tdefault = \"conf_uboot\";\n\n\t\tconf_uboot {\n\t\t\tdescription = \"BRCM 63xxx with uboot\";\n\t\t\tfdt = \"fdt_uboot\";\n\t\t\tloadables = \"atf\", \"uboot\";\n\t\t};\n\n\t\tconf_ub_GTAX6000 {\n\t\t\tdescription = \"GTAX6000\";\n\t\t\tfdt = \"fdt_GTAX6000\";\n\t\t\tloadables = \"atf\", \"uboot\";\n\t\t};\n\n\t\tconf_ub_RAX220 {\n\t\t\tdescription = \"RAX220\";\n\t\t\tfdt = \"fdt_uboot_RAX220\";\n\t\t\tloadables = \"atf\", \"uboot\";\n\t\t};\n\n\t\tconf_lx_RAX220 {\n\t\t\tdescription = \"BRCM 63xxx linux\";\n\t\t\tkernel = \"kernel\";\n\t\t\tfdt = \"fdt_linux_RAX220\";\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/bcm4908/image/netgear_r8000p/etc/image_ident",
    "content": "@(#) $imageversion: 5024HNDrc11R8000P2602103 $\n@(#) $imageversion: 5024HNDrc11R8000P2602103 $\n@(#) $changelist: Changelist: REL_502HND04rc11_BISON04T_REL_7_14_170_34Revision:   765096 $\n@(#) $changelist: Changelist: REL_502HND04rc11_BISON04T_REL_7_14_170_34Revision:   765096 $\n"
  },
  {
    "path": "target/linux/bcm4908/image/netgear_r8000p/etc/image_version",
    "content": "5024HNDrc11R8000P2602103\n"
  },
  {
    "path": "target/linux/bcm4908/image/pkgtb-bcm4908.its",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n/dts-v1/;\n\n/ {\n\tdescription = \"Broadcom image upgrade package tree binary\";\n\t#address-cells = <1>;\n\n\timages {\n\t\tbootfs_4908_a0+ {\n\t\t\tdescription = \"bootfs\";\n\t\t\tdata = /incbin/(\"${bootfs}\");\n\t\t\ttype = \"multi\";\n\t\t\tcompression = \"none\";\n\n\t\t\thash-1 {\n\t\t\t\talgo = \"sha256\";\n\t\t\t};\n\t\t};\n\n\t\tnand_squashfs {\n\t\t\tdescription = \"rootfs\";\n\t\t\tdata = /incbin/(\"${rootfs}\");\n\t\t\ttype = \"filesystem\";\n\t\t\tcompression = \"none\";\n\n\t\t\thash-1 {\n\t\t\t\talgo = \"sha256\";\n\t\t\t};\n\t\t};\n\t};\n\n\tconfigurations {\n\t\tdefault = \"conf_4908_a0+_nand_squashfs\";\n\n\t\tconf_4908_a0+_nand_squashfs {\n\t\t\tdescription = \"Brcm Image Bundle\";\n\t\t\tbootfs = \"bootfs_4908_a0+\";\n\t\t\trootfs = \"nand_squashfs\";\n\t\t\tcompatible = \"flash=nand;chip=4908;rev=a0+;ip=ipv6,ipv4;ddr=ddr3;fstype=squashfs\";\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/bcm4908/image/pkgtb-bcm4912.its",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n/dts-v1/;\n\n/ {\n\tdescription = \"Broadcom image upgrade package tree binary\";\n\t#address-cells = <1>;\n\n\timages {\n\t\tbootfs_4912_a0+ {\n\t\t\tdescription = \"bootfs\";\n\t\t\tdata = /incbin/(\"${bootfs}\");\n\t\t\ttype = \"multi\";\n\t\t\tcompression = \"none\";\n\n\t\t\thash-1 {\n\t\t\t\talgo = \"sha256\";\n\t\t\t};\n\t\t};\n\n\t\tnand_squashfs {\n\t\t\tdescription = \"rootfs\";\n\t\t\tdata = /incbin/(\"${rootfs}\");\n\t\t\ttype = \"filesystem\";\n\t\t\tcompression = \"none\";\n\n\t\t\thash-1 {\n\t\t\t\talgo = \"sha256\";\n\t\t\t};\n\t\t};\n\t};\n\n\tconfigurations {\n\t\tdefault = \"conf_4912_a0+_nand_squashfs\";\n\n\t\tconf_4912_a0+_nand_squashfs {\n\t\t\tdescription = \"Brcm Image Bundle\";\n\t\t\tbootfs = \"bootfs_4912_a0+\";\n\t\t\trootfs = \"nand_squashfs\";\n\t\t\tcompatible = \"flash=nand;chip=4912;rev=a0+;ip=ipv6,ipv4;ddr=ddr3,ddr4;fstype=squashfs\";\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/bcm4908/image/tplink_archer-c2300-v1/etc/image_version",
    "content": "5022HNDrc7HND2221446\n"
  },
  {
    "path": "target/linux/bcm4908/patches-5.10/030-v5.11-0001-dt-bindings-arm-bcm-document-BCM4908-bindings.patch",
    "content": "From 2f8913a7b17efd3a116825160a2d3a6610444587 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Thu, 12 Nov 2020 16:08:31 +0100\nSubject: [PATCH] dt-bindings: arm: bcm: document BCM4908 bindings\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nBCM4908 is a new family that includes BCM4906, BCM4908 and BCM49408.\nIt's mostly used in home routers and often replaces Northstar in vendors\nportfolio.\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n .../bindings/arm/bcm/brcm,bcm4908.yaml        | 38 +++++++++++++++++++\n 1 file changed, 38 insertions(+)\n create mode 100644 Documentation/devicetree/bindings/arm/bcm/brcm,bcm4908.yaml\n\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4908.yaml\n@@ -0,0 +1,38 @@\n+# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause\n+%YAML 1.2\n+---\n+$id: http://devicetree.org/schemas/arm/bcm/brcm,bcm4908.yaml#\n+$schema: http://devicetree.org/meta-schemas/core.yaml#\n+\n+title: Broadcom BCM4908 device tree bindings\n+\n+description:\n+  Broadcom BCM4906 / BCM4908 / BCM49408 Wi-Fi/network SoCs with Brahma CPUs.\n+\n+maintainers:\n+  - Rafał Miłecki <rafal@milecki.pl>\n+\n+properties:\n+  $nodename:\n+    const: '/'\n+  compatible:\n+    oneOf:\n+      - description: BCM4906 based boards\n+        items:\n+          - const: brcm,bcm4906\n+          - const: brcm,bcm4908\n+\n+      - description: BCM4908 based boards\n+        items:\n+          - enum:\n+              - asus,gt-ac5300\n+          - const: brcm,bcm4908\n+\n+      - description: BCM49408 based boards\n+        items:\n+          - const: brcm,bcm49408\n+          - const: brcm,bcm4908\n+\n+additionalProperties: true\n+\n+...\n"
  },
  {
    "path": "target/linux/bcm4908/patches-5.10/030-v5.11-0002-arm64-dts-broadcom-add-BCM4908-and-Asus-GT-AC5300-ea.patch",
    "content": "From 2961f69f151c0a6771f55cef46398fe49ca20902 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Thu, 12 Nov 2020 16:08:32 +0100\nSubject: [PATCH] arm64: dts: broadcom: add BCM4908 and Asus GT-AC5300 early\n DTS files\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nThey don't descibe hardware fully yet but it's enough to boot a system.\n\nSome missing blocks:\n1. PMC (Power Management Controller?)\n2. Ethernet\n3. Crypto\n4. Thermal\n\nAsus DTS is missing defining full NAND partitions layout and buttons.\n\nFurther changes will fill those gaps as soon as required bindings will\nbe found / tested / added.\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n arch/arm64/boot/dts/broadcom/Makefile         |   1 +\n arch/arm64/boot/dts/broadcom/bcm4908/Makefile |   2 +\n .../bcm4908/bcm4908-asus-gt-ac5300.dts        |  66 +++++++\n .../boot/dts/broadcom/bcm4908/bcm4908.dtsi    | 187 ++++++++++++++++++\n 4 files changed, 256 insertions(+)\n create mode 100644 arch/arm64/boot/dts/broadcom/bcm4908/Makefile\n create mode 100644 arch/arm64/boot/dts/broadcom/bcm4908/bcm4908-asus-gt-ac5300.dts\n create mode 100644 arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi\n\n--- a/arch/arm64/boot/dts/broadcom/Makefile\n+++ b/arch/arm64/boot/dts/broadcom/Makefile\n@@ -5,5 +5,6 @@ dtb-$(CONFIG_ARCH_BCM2835) += bcm2711-rp\n \t\t\t      bcm2837-rpi-3-b-plus.dtb \\\n \t\t\t      bcm2837-rpi-cm3-io3.dtb\n \n+subdir-y\t+= bcm4908\n subdir-y\t+= northstar2\n subdir-y\t+= stingray\n--- /dev/null\n+++ b/arch/arm64/boot/dts/broadcom/bcm4908/Makefile\n@@ -0,0 +1,2 @@\n+# SPDX-License-Identifier: GPL-2.0\n+dtb-$(CONFIG_ARCH_BCM4908) += bcm4908-asus-gt-ac5300.dtb\n--- /dev/null\n+++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908-asus-gt-ac5300.dts\n@@ -0,0 +1,66 @@\n+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n+\n+#include <dt-bindings/gpio/gpio.h>\n+#include <dt-bindings/input/input.h>\n+\n+#include \"bcm4908.dtsi\"\n+\n+/ {\n+\tcompatible = \"asus,gt-ac5300\", \"brcm,bcm4908\";\n+\tmodel = \"Asus GT-AC5300\";\n+\n+\tmemory@0 {\n+\t\tdevice_type = \"memory\";\n+\t\treg = <0x00 0x00 0x00 0x40000000>;\n+\t};\n+\n+\tgpio-keys-polled {\n+\t\tcompatible = \"gpio-keys-polled\";\n+\t\tpoll-interval = <100>;\n+\n+\t\twifi {\n+\t\t\tlabel = \"WiFi\";\n+\t\t\tlinux,code = <KEY_RFKILL>;\n+\t\t\tgpios = <&gpio0 28 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\n+\t\twps {\n+\t\t\tlabel = \"WPS\";\n+\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n+\t\t\tgpios = <&gpio0 29 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\n+\t\trestart {\n+\t\t\tlabel = \"Reset\";\n+\t\t\tlinux,code = <KEY_RESTART>;\n+\t\t\tgpios = <&gpio0 30 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\n+\t\tbrightness {\n+\t\t\tlabel = \"LEDs\";\n+\t\t\tlinux,code = <KEY_BRIGHTNESS_ZERO>;\n+\t\t\tgpios = <&gpio0 31 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\t};\n+};\n+\n+&nandcs {\n+\tnand-ecc-strength = <4>;\n+\tnand-ecc-step-size = <512>;\n+\tnand-on-flash-bbt;\n+\tbrcm,nand-has-wp;\n+\n+\t#address-cells = <1>;\n+\t#size-cells = <0>;\n+\n+\tpartitions {\n+\t\tcompatible = \"fixed-partitions\";\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <1>;\n+\n+\t\tpartition@0 {\n+\t\t\tlabel = \"cferom\";\n+\t\t\treg = <0x0 0x100000>;\n+\t\t};\n+\t};\n+};\n--- /dev/null\n+++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi\n@@ -0,0 +1,187 @@\n+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n+\n+#include <dt-bindings/interrupt-controller/irq.h>\n+#include <dt-bindings/interrupt-controller/arm-gic.h>\n+\n+/dts-v1/;\n+\n+/ {\n+\tinterrupt-parent = <&gic>;\n+\n+\t#address-cells = <2>;\n+\t#size-cells = <2>;\n+\n+\taliases {\n+\t\tserial0 = &uart0;\n+\t};\n+\n+\tchosen {\n+\t\tstdout-path = \"serial0:115200n8\";\n+\t};\n+\n+\tcpus {\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\n+\t\tcpu0: cpu@0 {\n+\t\t\tdevice_type = \"cpu\";\n+\t\t\tcompatible = \"brcm,brahma-b53\";\n+\t\t\treg = <0x0>;\n+\t\t\tnext-level-cache = <&l2>;\n+\t\t};\n+\n+\t\tcpu1: cpu@1 {\n+\t\t\tdevice_type = \"cpu\";\n+\t\t\tcompatible = \"brcm,brahma-b53\";\n+\t\t\treg = <0x1>;\n+\t\t\tenable-method = \"spin-table\";\n+\t\t\tcpu-release-addr = <0x0 0xfff8>;\n+\t\t\tnext-level-cache = <&l2>;\n+\t\t};\n+\n+\t\tcpu2: cpu@2 {\n+\t\t\tdevice_type = \"cpu\";\n+\t\t\tcompatible = \"brcm,brahma-b53\";\n+\t\t\treg = <0x2>;\n+\t\t\tenable-method = \"spin-table\";\n+\t\t\tcpu-release-addr = <0x0 0xfff8>;\n+\t\t\tnext-level-cache = <&l2>;\n+\t\t};\n+\n+\t\tcpu3: cpu@3 {\n+\t\t\tdevice_type = \"cpu\";\n+\t\t\tcompatible = \"brcm,brahma-b53\";\n+\t\t\treg = <0x3>;\n+\t\t\tenable-method = \"spin-table\";\n+\t\t\tcpu-release-addr = <0x0 0xfff8>;\n+\t\t\tnext-level-cache = <&l2>;\n+\t\t};\n+\n+\t\tl2: l2-cache0 {\n+\t\t\tcompatible = \"cache\";\n+\t\t};\n+\t};\n+\n+\taxi@81000000 {\n+\t\tcompatible = \"simple-bus\";\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <1>;\n+\t\tranges = <0x00 0x00 0x81000000 0x4000>;\n+\n+\t\tgic: interrupt-controller@1000 {\n+\t\t\tcompatible = \"arm,gic-400\";\n+\t\t\t#interrupt-cells = <3>;\n+\t\t\t#address-cells = <0>;\n+\t\t\tinterrupt-controller;\n+\t\t\treg = <0x1000 0x1000>,\n+\t\t\t      <0x2000 0x2000>;\n+\t\t};\n+\t};\n+\n+\ttimer {\n+\t\tcompatible = \"arm,armv8-timer\";\n+\t\tinterrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,\n+\t\t\t     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,\n+\t\t\t     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,\n+\t\t\t     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;\n+\t};\n+\n+\tpmu {\n+\t\tcompatible = \"arm,cortex-a53-pmu\";\n+\t\tinterrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t     <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;\n+\t\tinterrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;\n+\t};\n+\n+\tclocks {\n+\t\tperiph_clk: periph_clk {\n+\t\t\tcompatible = \"fixed-clock\";\n+\t\t\t#clock-cells = <0>;\n+\t\t\tclock-frequency = <50000000>;\n+\t\t\tclock-output-names = \"periph\";\n+\t\t};\n+\t};\n+\n+\tsoc {\n+\t\tcompatible = \"simple-bus\";\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <1>;\n+\t\tranges = <0x00 0x00 0x80000000 0x10000>;\n+\n+\t\tusb@c300 {\n+\t\t\tcompatible = \"generic-ehci\";\n+\t\t\treg = <0xc300 0x100>;\n+\t\t\tinterrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tusb@c400 {\n+\t\t\tcompatible = \"generic-ohci\";\n+\t\t\treg = <0xc400 0x100>;\n+\t\t\tinterrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tusb@d000 {\n+\t\t\tcompatible = \"generic-xhci\";\n+\t\t\treg = <0xd000 0x8c8>;\n+\t\t\tinterrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\tbus@ff800000 {\n+\t\tcompatible = \"simple-bus\";\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <1>;\n+\t\tranges = <0x00 0x00 0xff800000 0x3000>;\n+\n+\t\ttimer: timer@400 {\n+\t\t\tcompatible = \"brcm,bcm6328-timer\", \"syscon\";\n+\t\t\treg = <0x400 0x3c>;\n+\t\t};\n+\n+\t\tgpio0: gpio-controller@500 {\n+\t\t\tcompatible = \"brcm,bcm6345-gpio\";\n+\t\t\treg-names = \"dirout\", \"dat\";\n+\t\t\treg = <0x500 0x28>, <0x528 0x28>;\n+\n+\t\t\t#gpio-cells = <2>;\n+\t\t\tgpio-controller;\n+\t\t};\n+\n+\t\tuart0: serial@640 {\n+\t\t\tcompatible = \"brcm,bcm6345-uart\";\n+\t\t\treg = <0x640 0x18>;\n+\t\t\tinterrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tclocks = <&periph_clk>;\n+\t\t\tclock-names = \"periph\";\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\n+\t\tnand@1800 {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tcompatible = \"brcm,brcmnand-v7.1\", \"brcm,brcmnand\";\n+\t\t\treg = <0x1800 0x600>, <0x2000 0x10>;\n+\t\t\treg-names = \"nand\", \"nand-int-base\";\n+\t\t\tinterrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tinterrupt-names = \"nand\";\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tnandcs: nandcs@0 {\n+\t\t\t\tcompatible = \"brcm,nandcs\";\n+\t\t\t\treg = <0>;\n+\t\t\t};\n+\t\t};\n+\n+\t\treboot {\n+\t\t\tcompatible = \"syscon-reboot\";\n+\t\t\tregmap = <&timer>;\n+\t\t\toffset = <0x34>;\n+\t\t\tmask = <1>;\n+\t\t};\n+\t};\n+};\n"
  },
  {
    "path": "target/linux/bcm4908/patches-5.10/030-v5.11-0003-v5.11-arm64-add-config-for-Broadcom-BCM4908-SoCs.patch",
    "content": "From dccb22d078ebd098115e4f66bde1ee2249c8640b Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Thu, 12 Nov 2020 16:08:30 +0100\nSubject: [PATCH] arm64: add config for Broadcom BCM4908 SoCs\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nAdd ARCH_BCM4908 config that can be used for compiling DTS files.\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n arch/arm64/Kconfig.platforms | 8 ++++++++\n arch/arm64/configs/defconfig | 1 +\n 2 files changed, 9 insertions(+)\n\n--- a/arch/arm64/Kconfig.platforms\n+++ b/arch/arm64/Kconfig.platforms\n@@ -43,6 +43,14 @@ config ARCH_BCM2835\n \t  This enables support for the Broadcom BCM2837 and BCM2711 SoC.\n \t  These SoCs are used in the Raspberry Pi 3 and 4 devices.\n \n+config ARCH_BCM4908\n+\tbool \"Broadcom BCM4908 family\"\n+\tselect GPIOLIB\n+\thelp\n+\t  This enables support for the Broadcom BCM4906, BCM4908 and\n+\t  BCM49408 SoCs. These SoCs use Brahma-B53 cores and can be\n+\t  found in home routers.\n+\n config ARCH_BCM_IPROC\n \tbool \"Broadcom iProc SoC Family\"\n \tselect COMMON_CLK_IPROC\n--- a/arch/arm64/configs/defconfig\n+++ b/arch/arm64/configs/defconfig\n@@ -32,6 +32,7 @@ CONFIG_ARCH_AGILEX=y\n CONFIG_ARCH_SUNXI=y\n CONFIG_ARCH_ALPINE=y\n CONFIG_ARCH_BCM2835=y\n+CONFIG_ARCH_BCM4908=y\n CONFIG_ARCH_BCM_IPROC=y\n CONFIG_ARCH_BERLIN=y\n CONFIG_ARCH_BRCMSTB=y\n"
  },
  {
    "path": "target/linux/bcm4908/patches-5.10/031-v5.12-0001-dt-bindings-arm-bcm-document-Netgear-R8000P-binding.patch",
    "content": "From 3a5da4f54801ac42837a0b3151fa8285e01e8b0e Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Tue, 8 Dec 2020 08:03:03 +0100\nSubject: [PATCH] dt-bindings: arm: bcm: document Netgear R8000P binding\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nIt's a BCM4906 based device.\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nAcked-by: Rob Herring <robh@kernel.org>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n Documentation/devicetree/bindings/arm/bcm/brcm,bcm4908.yaml | 2 ++\n 1 file changed, 2 insertions(+)\n\n--- a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4908.yaml\n+++ b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4908.yaml\n@@ -19,6 +19,8 @@ properties:\n     oneOf:\n       - description: BCM4906 based boards\n         items:\n+          - enum:\n+              - netgear,r8000p\n           - const: brcm,bcm4906\n           - const: brcm,bcm4908\n \n"
  },
  {
    "path": "target/linux/bcm4908/patches-5.10/031-v5.12-0002-arm64-dts-broadcom-bcm4908-add-BCM4906-Netgear-R8000.patch",
    "content": "From c8b404fb05dcfadff477e49b7ea6b500e015f101 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Tue, 8 Dec 2020 08:03:04 +0100\nSubject: [PATCH 2/4] arm64: dts: broadcom: bcm4908: add BCM4906 Netgear R8000P\n DTS files\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nNetgear R8000P is home router based on BCM4906 that is a cheaper variant\nof BCM4908 (e.g. 2 cores instead of 4).\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n arch/arm64/boot/dts/broadcom/bcm4908/Makefile |  1 +\n .../bcm4908/bcm4906-netgear-r8000p.dts        | 52 +++++++++++++++++++\n .../boot/dts/broadcom/bcm4908/bcm4906.dtsi    | 18 +++++++\n 3 files changed, 71 insertions(+)\n create mode 100644 arch/arm64/boot/dts/broadcom/bcm4908/bcm4906-netgear-r8000p.dts\n create mode 100644 arch/arm64/boot/dts/broadcom/bcm4908/bcm4906.dtsi\n\n--- a/arch/arm64/boot/dts/broadcom/bcm4908/Makefile\n+++ b/arch/arm64/boot/dts/broadcom/bcm4908/Makefile\n@@ -1,2 +1,3 @@\n # SPDX-License-Identifier: GPL-2.0\n+dtb-$(CONFIG_ARCH_BCM4908) += bcm4906-netgear-r8000p.dtb\n dtb-$(CONFIG_ARCH_BCM4908) += bcm4908-asus-gt-ac5300.dtb\n--- /dev/null\n+++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4906-netgear-r8000p.dts\n@@ -0,0 +1,52 @@\n+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n+\n+#include <dt-bindings/gpio/gpio.h>\n+#include <dt-bindings/input/input.h>\n+#include <dt-bindings/leds/common.h>\n+\n+#include \"bcm4906.dtsi\"\n+\n+/ {\n+\tcompatible = \"netgear,r8000p\", \"brcm,bcm4906\", \"brcm,bcm4908\";\n+\tmodel = \"Netgear R8000P\";\n+\n+\tmemory@0 {\n+\t\tdevice_type = \"memory\";\n+\t\treg = <0x00 0x00 0x00 0x20000000>;\n+\t};\n+\n+\tleds {\n+\t\tcompatible = \"gpio-leds\";\n+\n+\t\twps {\n+\t\t\tfunction = LED_FUNCTION_WPS;\n+\t\t\tcolor = <LED_COLOR_ID_WHITE>;\n+\t\t\tgpios = <&gpio0 10 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\t};\n+};\n+\n+&nandcs {\n+\tnand-ecc-strength = <4>;\n+\tnand-ecc-step-size = <512>;\n+\tnand-on-flash-bbt;\n+\n+\t#address-cells = <1>;\n+\t#size-cells = <0>;\n+\n+\tpartitions {\n+\t\tcompatible = \"fixed-partitions\";\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <1>;\n+\n+\t\tpartition@0 {\n+\t\t\tlabel = \"cferom\";\n+\t\t\treg = <0x0 0x100000>;\n+\t\t};\n+\n+\t\tpartition@100000 {\n+\t\t\tlabel = \"firmware\";\n+\t\t\treg = <0x100000 0x4400000>;\n+\t\t};\n+\t};\n+};\n--- /dev/null\n+++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4906.dtsi\n@@ -0,0 +1,18 @@\n+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n+\n+#include \"bcm4908.dtsi\"\n+\n+/ {\n+\tcpus {\n+\t\t/delete-node/ cpu@2;\n+\n+\t\t/delete-node/ cpu@3;\n+\t};\n+\n+\tpmu {\n+\t\tcompatible = \"arm,cortex-a53-pmu\";\n+\t\tinterrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;\n+\t\tinterrupt-affinity = <&cpu0>, <&cpu1>;\n+\t};\n+};\n"
  },
  {
    "path": "target/linux/bcm4908/patches-5.10/031-v5.12-0003-arm64-dts-broadcom-bcm4908-use-proper-NAND-binding.patch",
    "content": "From 56098be85d19cd56b59d7b3854ea035cc8cb9e95 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Tue, 8 Dec 2020 11:49:50 +0100\nSubject: [PATCH 3/4] arm64: dts: broadcom: bcm4908: use proper NAND binding\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nBCM4908 has controller that needs different IRQ handling just like the\nBCM63138. Describe it properly.\n\nOn Linux this change fixes:\nbrcmstb_nand ff801800.nand: timeout waiting for command 0x9\nbrcmstb_nand ff801800.nand: intfc status d0000000\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi\n+++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi\n@@ -164,7 +164,7 @@\n \t\tnand@1800 {\n \t\t\t#address-cells = <1>;\n \t\t\t#size-cells = <0>;\n-\t\t\tcompatible = \"brcm,brcmnand-v7.1\", \"brcm,brcmnand\";\n+\t\t\tcompatible = \"brcm,nand-bcm63138\", \"brcm,brcmnand-v7.1\", \"brcm,brcmnand\";\n \t\t\treg = <0x1800 0x600>, <0x2000 0x10>;\n \t\t\treg-names = \"nand\", \"nand-int-base\";\n \t\t\tinterrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;\n"
  },
  {
    "path": "target/linux/bcm4908/patches-5.10/031-v5.12-0004-arm64-dts-broadcom-bcm4908-describe-PCIe-reset-contr.patch",
    "content": "From 1b88c6ed26a1aa1d68d1661404e6e939709ff530 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Thu, 10 Dec 2020 08:21:54 +0100\nSubject: [PATCH 4/4] arm64: dts: broadcom: bcm4908: describe PCIe reset\n controller\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nThis reset controller is a single register in the Broadcom's MISC block.\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi | 15 +++++++++++++++\n 1 file changed, 15 insertions(+)\n\n--- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi\n+++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi\n@@ -177,6 +177,21 @@\n \t\t\t};\n \t\t};\n \n+\t\tmisc@2600 {\n+\t\t\tcompatible = \"brcm,misc\", \"simple-mfd\";\n+\t\t\treg = <0x2600 0xe4>;\n+\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <1>;\n+\t\t\tranges = <0x00 0x2600 0xe4>;\n+\n+\t\t\treset-controller@2644 {\n+\t\t\t\tcompatible = \"brcm,bcm4908-misc-pcie-reset\";\n+\t\t\t\treg = <0x44 0x04>;\n+\t\t\t\t#reset-cells = <1>;\n+\t\t\t};\n+\t\t};\n+\n \t\treboot {\n \t\t\tcompatible = \"syscon-reboot\";\n \t\t\tregmap = <&timer>;\n"
  },
  {
    "path": "target/linux/bcm4908/patches-5.10/031-v5.12-0005-arm64-dts-broadcom-bcm4908-describe-internal-switch.patch",
    "content": "From 527a3ac9bdf81da4b7160ce3cea57f28a0e5eb64 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Wed, 13 Jan 2021 12:14:06 +0100\nSubject: [PATCH] arm64: dts: broadcom: bcm4908: describe internal switch\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nBCM4908 has internal switch with 5 GPHYs. Ports 0 - 3 are always\nconnected to the internal PHYs. Remaining ports depend on device setup.\n\nAsus GT-AC5300 has an extra switch with its PHYs accessible using the\ninternal MDIO.\n\nCPU port and Ethernet interface remain to be documented.\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n .../bcm4908/bcm4908-asus-gt-ac5300.dts        | 51 +++++++++++\n .../boot/dts/broadcom/bcm4908/bcm4908.dtsi    | 85 ++++++++++++++++++-\n 2 files changed, 135 insertions(+), 1 deletion(-)\n\n--- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908-asus-gt-ac5300.dts\n+++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908-asus-gt-ac5300.dts\n@@ -44,6 +44,57 @@\n \t};\n };\n \n+&ports {\n+\tport@0 {\n+\t\tlabel = \"lan2\";\n+\t};\n+\n+\tport@1 {\n+\t\tlabel = \"lan1\";\n+\t};\n+\n+\tport@2 {\n+\t\tlabel = \"lan6\";\n+\t};\n+\n+\tport@3 {\n+\t\tlabel = \"lan5\";\n+\t};\n+\n+\t/* External BCM53134S switch */\n+\tport@7 {\n+\t\tlabel = \"sw\";\n+\t\treg = <7>;\n+\n+\t\tfixed-link {\n+\t\t\tspeed = <1000>;\n+\t\t\tfull-duplex;\n+\t\t};\n+\t};\n+};\n+\n+&mdio {\n+\t/* lan8 */\n+\tethernet-phy@0 {\n+\t\treg = <0>;\n+\t};\n+\n+\t/* lan7 */\n+\tethernet-phy@1 {\n+\t\treg = <1>;\n+\t};\n+\n+\t/* lan4 */\n+\tethernet-phy@2 {\n+\t\treg = <2>;\n+\t};\n+\n+\t/* lan3 */\n+\tethernet-phy@3 {\n+\t\treg = <3>;\n+\t};\n+};\n+\n &nandcs {\n \tnand-ecc-strength = <4>;\n \tnand-ecc-step-size = <512>;\n--- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi\n+++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi\n@@ -108,7 +108,7 @@\n \t\tcompatible = \"simple-bus\";\n \t\t#address-cells = <1>;\n \t\t#size-cells = <1>;\n-\t\tranges = <0x00 0x00 0x80000000 0x10000>;\n+\t\tranges = <0x00 0x00 0x80000000 0xd0000>;\n \n \t\tusb@c300 {\n \t\t\tcompatible = \"generic-ehci\";\n@@ -130,6 +130,89 @@\n \t\t\tinterrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;\n \t\t\tstatus = \"disabled\";\n \t\t};\n+\n+\t\tethernet-switch@80000 {\n+\t\t\tcompatible = \"simple-bus\";\n+\t\t\t#size-cells = <1>;\n+\t\t\t#address-cells = <1>;\n+\t\t\tranges = <0 0x80000 0x50000>;\n+\n+\t\t\tethernet-switch@0 {\n+\t\t\t\tcompatible = \"brcm,bcm4908-switch\";\n+\t\t\t\treg = <0x0 0x40000>,\n+\t\t\t\t      <0x40000 0x110>,\n+\t\t\t\t      <0x40340 0x30>,\n+\t\t\t\t      <0x40380 0x30>,\n+\t\t\t\t      <0x40600 0x34>,\n+\t\t\t\t      <0x40800 0x208>;\n+\t\t\t\treg-names = \"core\", \"reg\", \"intrl2_0\",\n+\t\t\t\t\t    \"intrl2_1\", \"fcb\", \"acb\";\n+\t\t\t\tinterrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t\t\t     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\t\tbrcm,num-gphy = <5>;\n+\t\t\t\tbrcm,num-rgmii-ports = <2>;\n+\n+\t\t\t\t#address-cells = <1>;\n+\t\t\t\t#size-cells = <0>;\n+\n+\t\t\t\tports: ports {\n+\t\t\t\t\t#address-cells = <1>;\n+\t\t\t\t\t#size-cells = <0>;\n+\n+\t\t\t\t\tport@0 {\n+\t\t\t\t\t\treg = <0>;\n+\t\t\t\t\t\tphy-mode = \"internal\";\n+\t\t\t\t\t\tphy-handle = <&phy8>;\n+\t\t\t\t\t};\n+\n+\t\t\t\t\tport@1 {\n+\t\t\t\t\t\treg = <1>;\n+\t\t\t\t\t\tphy-mode = \"internal\";\n+\t\t\t\t\t\tphy-handle = <&phy9>;\n+\t\t\t\t\t};\n+\n+\t\t\t\t\tport@2 {\n+\t\t\t\t\t\treg = <2>;\n+\t\t\t\t\t\tphy-mode = \"internal\";\n+\t\t\t\t\t\tphy-handle = <&phy10>;\n+\t\t\t\t\t};\n+\n+\t\t\t\t\tport@3 {\n+\t\t\t\t\t\treg = <3>;\n+\t\t\t\t\t\tphy-mode = \"internal\";\n+\t\t\t\t\t\tphy-handle = <&phy11>;\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\t\t\t};\n+\n+\t\t\tmdio: mdio@405c0 {\n+\t\t\t\tcompatible = \"brcm,unimac-mdio\";\n+\t\t\t\treg = <0x405c0 0x8>;\n+\t\t\t\treg-names = \"mdio\";\n+\t\t\t\t#size-cells = <0>;\n+\t\t\t\t#address-cells = <1>;\n+\n+\t\t\t\tphy8: ethernet-phy@8 {\n+\t\t\t\t\treg = <8>;\n+\t\t\t\t};\n+\n+\t\t\t\tphy9: ethernet-phy@9 {\n+\t\t\t\t\treg = <9>;\n+\t\t\t\t};\n+\n+\t\t\t\tphy10: ethernet-phy@a {\n+\t\t\t\t\treg = <10>;\n+\t\t\t\t};\n+\n+\t\t\t\tphy11: ethernet-phy@b {\n+\t\t\t\t\treg = <11>;\n+\t\t\t\t};\n+\n+\t\t\t\tphy12: ethernet-phy@c {\n+\t\t\t\t\treg = <12>;\n+\t\t\t\t};\n+\t\t\t};\n+\t\t};\n \t};\n \n \tbus@ff800000 {\n"
  },
  {
    "path": "target/linux/bcm4908/patches-5.10/031-v5.12-0006-arm64-dts-broadcom-bcm4908-describe-PMB-block.patch",
    "content": "From edcf90801c8e58bd6306d85a4e714a6f09f452df Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Wed, 13 Jan 2021 12:15:47 +0100\nSubject: [PATCH] arm64: dts: broadcom: bcm4908: describe PMB block\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nPMB (Power Management Bus) controls powering connected devices (e.g.\nPCIe, USB, SATA). In BCM4908 it's a part of the PROCMON block.\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n .../boot/dts/broadcom/bcm4908/bcm4908.dtsi      | 17 ++++++++++++++++-\n 1 file changed, 16 insertions(+), 1 deletion(-)\n\n--- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi\n+++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi\n@@ -108,7 +108,7 @@\n \t\tcompatible = \"simple-bus\";\n \t\t#address-cells = <1>;\n \t\t#size-cells = <1>;\n-\t\tranges = <0x00 0x00 0x80000000 0xd0000>;\n+\t\tranges = <0x00 0x00 0x80000000 0x281000>;\n \n \t\tusb@c300 {\n \t\t\tcompatible = \"generic-ehci\";\n@@ -213,6 +213,21 @@\n \t\t\t\t};\n \t\t\t};\n \t\t};\n+\n+\t\tprocmon: syscon@280000 {\n+\t\t\tcompatible = \"simple-bus\";\n+\t\t\treg = <0x280000 0x1000>;\n+\t\t\tranges;\n+\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <1>;\n+\n+\t\t\tpower-controller@2800c0 {\n+\t\t\t\tcompatible = \"brcm,bcm4908-pmb\";\n+\t\t\t\treg = <0x2800c0 0x40>;\n+\t\t\t\t#power-domain-cells = <1>;\n+\t\t\t};\n+\t\t};\n \t};\n \n \tbus@ff800000 {\n"
  },
  {
    "path": "target/linux/bcm4908/patches-5.10/032-v5.13-0001-arm64-dts-broadcom-bcm4908-describe-USB-PHY.patch",
    "content": "From 3c321ba794ca6383a4aa68ea803e18cc6ad44412 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Fri, 19 Feb 2021 06:50:26 +0100\nSubject: [PATCH] arm64: dts: broadcom: bcm4908: describe USB PHY\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nBCM4908 uses slightly modified STB family USB PHY. It handles OHCI/EHCI\nand XHCI. It requires powering up using the PMB.\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n .../bcm4908/bcm4906-netgear-r8000p.dts        | 17 +++++++++++++\n .../bcm4908/bcm4908-asus-gt-ac5300.dts        | 17 +++++++++++++\n .../boot/dts/broadcom/bcm4908/bcm4908.dtsi    | 25 ++++++++++++++++---\n 3 files changed, 55 insertions(+), 4 deletions(-)\n\n--- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4906-netgear-r8000p.dts\n+++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4906-netgear-r8000p.dts\n@@ -26,6 +26,23 @@\n \t};\n };\n \n+&usb_phy {\n+\tbrcm,ioc = <1>;\n+\tstatus = \"okay\";\n+};\n+\n+&ehci {\n+\tstatus = \"okay\";\n+};\n+\n+&ohci {\n+\tstatus = \"okay\";\n+};\n+\n+&xhci {\n+\tstatus = \"okay\";\n+};\n+\n &nandcs {\n \tnand-ecc-strength = <4>;\n \tnand-ecc-step-size = <512>;\n--- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908-asus-gt-ac5300.dts\n+++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908-asus-gt-ac5300.dts\n@@ -44,6 +44,23 @@\n \t};\n };\n \n+&usb_phy {\n+\tbrcm,ioc = <1>;\n+\tstatus = \"okay\";\n+};\n+\n+&ehci {\n+\tstatus = \"okay\";\n+};\n+\n+&ohci {\n+\tstatus = \"okay\";\n+};\n+\n+&xhci {\n+\tstatus = \"okay\";\n+};\n+\n &ports {\n \tport@0 {\n \t\tlabel = \"lan2\";\n--- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi\n+++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi\n@@ -2,6 +2,8 @@\n \n #include <dt-bindings/interrupt-controller/irq.h>\n #include <dt-bindings/interrupt-controller/arm-gic.h>\n+#include <dt-bindings/phy/phy.h>\n+#include <dt-bindings/soc/bcm-pmb.h>\n \n /dts-v1/;\n \n@@ -110,24 +112,39 @@\n \t\t#size-cells = <1>;\n \t\tranges = <0x00 0x00 0x80000000 0x281000>;\n \n-\t\tusb@c300 {\n+\t\tusb_phy: usb-phy@c200 {\n+\t\t\tcompatible = \"brcm,bcm4908-usb-phy\";\n+\t\t\treg = <0xc200 0x100>;\n+\t\t\treg-names = \"ctrl\";\n+\t\t\tpower-domains = <&pmb BCM_PMB_HOST_USB>;\n+\t\t\tdr_mode = \"host\";\n+\t\t\tbrcm,has-xhci;\n+\t\t\tbrcm,has-eohci;\n+\t\t\t#phy-cells = <1>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tehci: usb@c300 {\n \t\t\tcompatible = \"generic-ehci\";\n \t\t\treg = <0xc300 0x100>;\n \t\t\tinterrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tphys = <&usb_phy PHY_TYPE_USB2>;\n \t\t\tstatus = \"disabled\";\n \t\t};\n \n-\t\tusb@c400 {\n+\t\tohci: usb@c400 {\n \t\t\tcompatible = \"generic-ohci\";\n \t\t\treg = <0xc400 0x100>;\n \t\t\tinterrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tphys = <&usb_phy PHY_TYPE_USB2>;\n \t\t\tstatus = \"disabled\";\n \t\t};\n \n-\t\tusb@d000 {\n+\t\txhci: usb@d000 {\n \t\t\tcompatible = \"generic-xhci\";\n \t\t\treg = <0xd000 0x8c8>;\n \t\t\tinterrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tphys = <&usb_phy PHY_TYPE_USB3>;\n \t\t\tstatus = \"disabled\";\n \t\t};\n \n@@ -222,7 +239,7 @@\n \t\t\t#address-cells = <1>;\n \t\t\t#size-cells = <1>;\n \n-\t\t\tpower-controller@2800c0 {\n+\t\t\tpmb: power-controller@2800c0 {\n \t\t\t\tcompatible = \"brcm,bcm4908-pmb\";\n \t\t\t\treg = <0x2800c0 0x40>;\n \t\t\t\t#power-domain-cells = <1>;\n"
  },
  {
    "path": "target/linux/bcm4908/patches-5.10/032-v5.13-0002-arm64-dts-broadcom-bcm4908-describe-Ethernet-control.patch",
    "content": "From b1bbe48eec190b6a35f400c5a3ec6b0fc8fc3fe6 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Fri, 19 Feb 2021 06:50:27 +0100\nSubject: [PATCH] arm64: dts: broadcom: bcm4908: describe Ethernet controller\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nBCM4908 SoCs have an integrated Ethernet controller.\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n .../boot/dts/broadcom/bcm4908/bcm4908.dtsi    | 19 +++++++++++++++++++\n 1 file changed, 19 insertions(+)\n\n--- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi\n+++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi\n@@ -112,6 +112,14 @@\n \t\t#size-cells = <1>;\n \t\tranges = <0x00 0x00 0x80000000 0x281000>;\n \n+\t\tenet: ethernet@2000 {\n+\t\t\tcompatible = \"brcm,bcm4908-enet\";\n+\t\t\treg = <0x2000 0x1000>;\n+\n+\t\t\tinterrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tinterrupt-names = \"rx\";\n+\t\t};\n+\n \t\tusb_phy: usb-phy@c200 {\n \t\t\tcompatible = \"brcm,bcm4908-usb-phy\";\n \t\t\treg = <0xc200 0x100>;\n@@ -199,6 +207,17 @@\n \t\t\t\t\t\tphy-mode = \"internal\";\n \t\t\t\t\t\tphy-handle = <&phy11>;\n \t\t\t\t\t};\n+\n+\t\t\t\t\tport@8 {\n+\t\t\t\t\t\treg = <8>;\n+\t\t\t\t\t\tphy-mode = \"internal\";\n+\t\t\t\t\t\tethernet = <&enet>;\n+\n+\t\t\t\t\t\tfixed-link {\n+\t\t\t\t\t\t\tspeed = <1000>;\n+\t\t\t\t\t\t\tfull-duplex;\n+\t\t\t\t\t\t};\n+\t\t\t\t\t};\n \t\t\t\t};\n \t\t\t};\n \n"
  },
  {
    "path": "target/linux/bcm4908/patches-5.10/032-v5.13-0003-arm64-dts-broadcom-bcm4908-describe-Netgear-R8000P-s.patch",
    "content": "From 406e98afffe975982f63ea5d21bf9a47a81b56ee Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Fri, 19 Feb 2021 06:50:28 +0100\nSubject: [PATCH] arm64: dts: broadcom: bcm4908: describe Netgear R8000P switch\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nR8000P model has 4 LAN ports and 1 WAN port.\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n .../bcm4908/bcm4906-netgear-r8000p.dts        | 25 +++++++++++++++++++\n 1 file changed, 25 insertions(+)\n\n--- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4906-netgear-r8000p.dts\n+++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4906-netgear-r8000p.dts\n@@ -43,6 +43,31 @@\n \tstatus = \"okay\";\n };\n \n+&ports {\n+\tport@0 {\n+\t\tlabel = \"lan4\";\n+\t};\n+\n+\tport@1 {\n+\t\tlabel = \"lan3\";\n+\t};\n+\n+\tport@2 {\n+\t\tlabel = \"lan2\";\n+\t};\n+\n+\tport@3 {\n+\t\tlabel = \"lan1\";\n+\t};\n+\n+\tport@7 {\n+\t\treg = <7>;\n+\t\tphy-mode = \"internal\";\n+\t\tphy-handle = <&phy12>;\n+\t\tlabel = \"wan\";\n+\t};\n+};\n+\n &nandcs {\n \tnand-ecc-strength = <4>;\n \tnand-ecc-step-size = <512>;\n"
  },
  {
    "path": "target/linux/bcm4908/patches-5.10/032-v5.13-0004-arm64-dts-broadcom-bcm4908-add-remaining-Netgear-R80.patch",
    "content": "From 6224415c0389ba6661825746312163a64ece8f3a Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Fri, 19 Feb 2021 06:50:29 +0100\nSubject: [PATCH] arm64: dts: broadcom: bcm4908: add remaining Netgear R8000P\n LEDs\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nThere are a few more GPIO connected LEDs there didn't get described\ninitially.\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n .../bcm4908/bcm4906-netgear-r8000p.dts        | 50 ++++++++++++++++++-\n 1 file changed, 49 insertions(+), 1 deletion(-)\n\n--- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4906-netgear-r8000p.dts\n+++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4906-netgear-r8000p.dts\n@@ -18,11 +18,59 @@\n \tleds {\n \t\tcompatible = \"gpio-leds\";\n \n-\t\twps {\n+\t\tled-power-white {\n+\t\t\tfunction = LED_FUNCTION_POWER;\n+\t\t\tcolor = <LED_COLOR_ID_WHITE>;\n+\t\t\tgpios = <&gpio0 8 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\n+\t\tled-power-amber {\n+\t\t\tfunction = LED_FUNCTION_POWER;\n+\t\t\tcolor = <LED_COLOR_ID_AMBER>;\n+\t\t\tgpios = <&gpio0 9 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\n+\t\tled-wps {\n \t\t\tfunction = LED_FUNCTION_WPS;\n \t\t\tcolor = <LED_COLOR_ID_WHITE>;\n \t\t\tgpios = <&gpio0 10 GPIO_ACTIVE_LOW>;\n \t\t};\n+\n+\t\tled-2ghz {\n+\t\t\tfunction = \"2ghz\";\n+\t\t\tcolor = <LED_COLOR_ID_WHITE>;\n+\t\t\tgpios = <&gpio0 14 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\n+\t\tled-5ghz-1 {\n+\t\t\tfunction = \"5ghz-1\";\n+\t\t\tcolor = <LED_COLOR_ID_WHITE>;\n+\t\t\tgpios = <&gpio0 15 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\n+\t\tled-5ghz-2 {\n+\t\t\tfunction = \"5ghz-2\";\n+\t\t\tcolor = <LED_COLOR_ID_WHITE>;\n+\t\t\tgpios = <&gpio0 16 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\n+\t\tled-usb2 {\n+\t\t\tfunction = \"usb2\";\n+\t\t\tcolor = <LED_COLOR_ID_WHITE>;\n+\t\t\tgpios = <&gpio0 17 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\n+\t\tled-usb3 {\n+\t\t\tfunction = \"usb3\";\n+\t\t\tcolor = <LED_COLOR_ID_WHITE>;\n+\t\t\tgpios = <&gpio0 18 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\n+\t\tled-wifi {\n+\t\t\tfunction = \"wifi\";\n+\t\t\tcolor = <LED_COLOR_ID_WHITE>;\n+\t\t\tgpios = <&gpio0 56 GPIO_ACTIVE_LOW>;\n+\t\t};\n \t};\n };\n \n"
  },
  {
    "path": "target/linux/bcm4908/patches-5.10/032-v5.13-0005-arm64-dts-broadcom-bcm4908-describe-firmware-partiti.patch",
    "content": "From cbaca2c467dc25a163107e14a53b7925214eab17 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Fri, 19 Feb 2021 06:50:30 +0100\nSubject: [PATCH] arm64: dts: broadcom: bcm4908: describe firmware partitions\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nBCM4908 bootloader supports multiple firmware partitions and has its own\nbindings defined for them.\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n .../dts/broadcom/bcm4908/bcm4906-netgear-r8000p.dts  |  1 +\n .../dts/broadcom/bcm4908/bcm4908-asus-gt-ac5300.dts  | 12 +++++++++++-\n 2 files changed, 12 insertions(+), 1 deletion(-)\n\n--- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4906-netgear-r8000p.dts\n+++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4906-netgear-r8000p.dts\n@@ -135,6 +135,7 @@\n \t\t};\n \n \t\tpartition@100000 {\n+\t\t\tcompatible = \"brcm,bcm4908-firmware\";\n \t\t\tlabel = \"firmware\";\n \t\t\treg = <0x100000 0x4400000>;\n \t\t};\n--- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908-asus-gt-ac5300.dts\n+++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908-asus-gt-ac5300.dts\n@@ -122,7 +122,7 @@\n \t#size-cells = <0>;\n \n \tpartitions {\n-\t\tcompatible = \"fixed-partitions\";\n+\t\tcompatible = \"brcm,bcm4908-partitions\";\n \t\t#address-cells = <1>;\n \t\t#size-cells = <1>;\n \n@@ -130,5 +130,15 @@\n \t\t\tlabel = \"cferom\";\n \t\t\treg = <0x0 0x100000>;\n \t\t};\n+\n+\t\tpartition@100000 {\n+\t\t\tcompatible = \"brcm,bcm4908-firmware\";\n+\t\t\treg = <0x100000 0x5700000>;\n+\t\t};\n+\n+\t\tpartition@5800000 {\n+\t\t\tcompatible = \"brcm,bcm4908-firmware\";\n+\t\t\treg = <0x5800000 0x5700000>;\n+\t\t};\n \t};\n };\n"
  },
  {
    "path": "target/linux/bcm4908/patches-5.10/032-v5.13-0006-arm64-dts-broadcom-bcm4908-fix-switch-parent-node-na.patch",
    "content": "From a348ff97ffb840b9d74b0e64b3e0e6002187d224 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Tue, 9 Mar 2021 19:44:09 +0100\nSubject: [PATCH] arm64: dts: broadcom: bcm4908: fix switch parent node name\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nEthernet switch and MDIO are grouped using \"simple-bus\". It's not\nallowed to use \"ethernet-switch\" node name as it isn't a switch. Replace\nit with \"bus\".\n\nFixes: 527a3ac9bdf8 (\"arm64: dts: broadcom: bcm4908: describe internal switch\")\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi\n+++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi\n@@ -156,7 +156,7 @@\n \t\t\tstatus = \"disabled\";\n \t\t};\n \n-\t\tethernet-switch@80000 {\n+\t\tbus@80000 {\n \t\t\tcompatible = \"simple-bus\";\n \t\t\t#size-cells = <1>;\n \t\t\t#address-cells = <1>;\n"
  },
  {
    "path": "target/linux/bcm4908/patches-5.10/032-v5.13-0007-dt-bindings-arm-bcm-document-TP-Link-Archer-C2300-bi.patch",
    "content": "From b3de2a12d1a61d90a4d86c9840acc7d05066137f Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Wed, 10 Mar 2021 08:46:02 +0100\nSubject: [PATCH] dt-bindings: arm: bcm: document TP-Link Archer C2300 binding\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nOne more BCM4906 based device.\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nReviewed-by: Rob Herring <robh@kernel.org>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n Documentation/devicetree/bindings/arm/bcm/brcm,bcm4908.yaml | 1 +\n 1 file changed, 1 insertion(+)\n\n--- a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4908.yaml\n+++ b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4908.yaml\n@@ -21,6 +21,7 @@ properties:\n         items:\n           - enum:\n               - netgear,r8000p\n+              - tplink,archer-c2300-v1\n           - const: brcm,bcm4906\n           - const: brcm,bcm4908\n \n"
  },
  {
    "path": "target/linux/bcm4908/patches-5.10/032-v5.13-0008-arm64-dts-broadcom-bcm4908-add-TP-Link-Archer-C2300-.patch",
    "content": "From 6a30934a5470a0ce7ea32b0c6b600accfae94b1a Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Wed, 10 Mar 2021 08:46:03 +0100\nSubject: [PATCH] arm64: dts: broadcom: bcm4908: add TP-Link Archer C2300 V1\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nArcher C2300 V1 is a home router based on the BCM4906 (2 CPU cores). It\nhas 512 MiB of RAM, NAND flash, USB 2.0 and USB 3.0 ports, 4 LAN ports,\n1 WAN port.\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n arch/arm64/boot/dts/broadcom/bcm4908/Makefile |   1 +\n .../bcm4906-tplink-archer-c2300-v1.dts        | 182 ++++++++++++++++++\n 2 files changed, 183 insertions(+)\n create mode 100644 arch/arm64/boot/dts/broadcom/bcm4908/bcm4906-tplink-archer-c2300-v1.dts\n\n--- a/arch/arm64/boot/dts/broadcom/bcm4908/Makefile\n+++ b/arch/arm64/boot/dts/broadcom/bcm4908/Makefile\n@@ -1,3 +1,4 @@\n # SPDX-License-Identifier: GPL-2.0\n dtb-$(CONFIG_ARCH_BCM4908) += bcm4906-netgear-r8000p.dtb\n+dtb-$(CONFIG_ARCH_BCM4908) += bcm4906-tplink-archer-c2300-v1.dtb\n dtb-$(CONFIG_ARCH_BCM4908) += bcm4908-asus-gt-ac5300.dtb\n--- /dev/null\n+++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4906-tplink-archer-c2300-v1.dts\n@@ -0,0 +1,182 @@\n+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n+\n+#include <dt-bindings/gpio/gpio.h>\n+#include <dt-bindings/input/input.h>\n+#include <dt-bindings/leds/common.h>\n+\n+#include \"bcm4906.dtsi\"\n+\n+/ {\n+\tcompatible = \"tplink,archer-c2300-v1\", \"brcm,bcm4906\", \"brcm,bcm4908\";\n+\tmodel = \"TP-Link Archer C2300 V1\";\n+\n+\tmemory@0 {\n+\t\tdevice_type = \"memory\";\n+\t\treg = <0x00 0x00 0x00 0x20000000>;\n+\t};\n+\n+\tleds {\n+\t\tcompatible = \"gpio-leds\";\n+\n+\t\tled-power {\n+\t\t\tfunction = LED_FUNCTION_POWER;\n+\t\t\tcolor = <LED_COLOR_ID_BLUE>;\n+\t\t\tgpios = <&gpio0 0 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\n+\t\tled-2ghz {\n+\t\t\tfunction = \"2ghz\";\n+\t\t\tcolor = <LED_COLOR_ID_BLUE>;\n+\t\t\tgpios = <&gpio0 2 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\n+\t\tled-5ghz {\n+\t\t\tfunction = \"5ghz\";\n+\t\t\tcolor = <LED_COLOR_ID_BLUE>;\n+\t\t\tgpios = <&gpio0 3 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\n+\t\tled-wan-amber {\n+\t\t\tfunction = LED_FUNCTION_WAN;\n+\t\t\tcolor = <LED_COLOR_ID_AMBER>;\n+\t\t\tgpios = <&gpio0 4 GPIO_ACTIVE_HIGH>;\n+\t\t};\n+\n+\t\tled-wan-blue {\n+\t\t\tfunction = LED_FUNCTION_WAN;\n+\t\t\tcolor = <LED_COLOR_ID_BLUE>;\n+\t\t\tgpios = <&gpio0 10 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\n+\t\tled-lan {\n+\t\t\tfunction = LED_FUNCTION_LAN;\n+\t\t\tcolor = <LED_COLOR_ID_BLUE>;\n+\t\t\tgpios = <&gpio0 12 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\n+\t\tled-wps {\n+\t\t\tfunction = LED_FUNCTION_WPS;\n+\t\t\tcolor = <LED_COLOR_ID_BLUE>;\n+\t\t\tgpios = <&gpio0 14 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\n+\t\tled-usb2 {\n+\t\t\tfunction = \"usb2\";\n+\t\t\tcolor = <LED_COLOR_ID_BLUE>;\n+\t\t\tgpios = <&gpio0 15 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\n+\t\tled-usb3 {\n+\t\t\tfunction = \"usbd3\";\n+\t\t\tcolor = <LED_COLOR_ID_BLUE>;\n+\t\t\tgpios = <&gpio0 17 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\n+\t\tled-brightness {\n+\t\t\tfunction = LED_FUNCTION_BACKLIGHT;\n+\t\t\tcolor = <LED_COLOR_ID_WHITE>;\n+\t\t\tgpios = <&gpio0 19 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\t};\n+\n+\tgpio-keys-polled {\n+\t\tcompatible = \"gpio-keys-polled\";\n+\t\tpoll-interval = <100>;\n+\n+\t\tbrightness {\n+\t\t\tlabel = \"LEDs\";\n+\t\t\tlinux,code = <KEY_BRIGHTNESS_ZERO>;\n+\t\t\tgpios = <&gpio0 18 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\n+\t\twps {\n+\t\t\tlabel = \"WPS\";\n+\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n+\t\t\tgpios = <&gpio0 21 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\n+\t\twifi {\n+\t\t\tlabel = \"WiFi\";\n+\t\t\tlinux,code = <KEY_RFKILL>;\n+\t\t\tgpios = <&gpio0 22 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\n+\t\trestart {\n+\t\t\tlabel = \"Reset\";\n+\t\t\tlinux,code = <KEY_RESTART>;\n+\t\t\tgpios = <&gpio0 23 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\t};\n+};\n+\n+&usb_phy {\n+\tbrcm,ioc = <1>;\n+\tstatus = \"okay\";\n+};\n+\n+&ehci {\n+\tstatus = \"okay\";\n+};\n+\n+&ohci {\n+\tstatus = \"okay\";\n+};\n+\n+&xhci {\n+\tstatus = \"okay\";\n+};\n+\n+&ports {\n+\tport@0 {\n+\t\tlabel = \"lan4\";\n+\t};\n+\n+\tport@1 {\n+\t\tlabel = \"lan3\";\n+\t};\n+\n+\tport@2 {\n+\t\tlabel = \"lan2\";\n+\t};\n+\n+\tport@3 {\n+\t\tlabel = \"lan1\";\n+\t};\n+\n+\tport@7 {\n+\t\treg = <7>;\n+\t\tphy-mode = \"internal\";\n+\t\tphy-handle = <&phy12>;\n+\t\tlabel = \"wan\";\n+\t};\n+};\n+\n+&nandcs {\n+\tnand-ecc-strength = <4>;\n+\tnand-ecc-step-size = <512>;\n+\tnand-on-flash-bbt;\n+\n+\t#address-cells = <1>;\n+\t#size-cells = <0>;\n+\n+\tpartitions {\n+\t\tcompatible = \"brcm,bcm4908-partitions\";\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <1>;\n+\n+\t\tpartition@0 {\n+\t\t\tlabel = \"cferom\";\n+\t\t\treg = <0x0 0x100000>;\n+\t\t};\n+\n+\t\tpartition@100000 {\n+\t\t\tcompatible = \"brcm,bcm4908-firmware\";\n+\t\t\treg = <0x100000 0x3900000>;\n+\t\t};\n+\n+\t\tpartition@5800000 {\n+\t\t\tcompatible = \"brcm,bcm4908-firmware\";\n+\t\t\treg = <0x3a00000 0x3900000>;\n+\t\t};\n+\t};\n+};\n"
  },
  {
    "path": "target/linux/bcm4908/patches-5.10/032-v5.13-0009-arm64-dts-broadcom-bcm4908-set-Asus-GT-AC5300-port-7.patch",
    "content": "From 5ccb9f9cf05bbd729430c6d6d30d40c96a15c56a Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Fri, 12 Mar 2021 12:01:20 +0100\nSubject: [PATCH] arm64: dts: broadcom: bcm4908: set Asus GT-AC5300 port 7 PHY\n mode\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nPort 7 is connected to the external BCM53134S switch using RGMII.\n\nFixes: 527a3ac9bdf8 (\"arm64: dts: broadcom: bcm4908: describe internal switch\")\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n arch/arm64/boot/dts/broadcom/bcm4908/bcm4908-asus-gt-ac5300.dts | 1 +\n 1 file changed, 1 insertion(+)\n\n--- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908-asus-gt-ac5300.dts\n+++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908-asus-gt-ac5300.dts\n@@ -82,6 +82,7 @@\n \tport@7 {\n \t\tlabel = \"sw\";\n \t\treg = <7>;\n+\t\tphy-mode = \"rgmii\";\n \n \t\tfixed-link {\n \t\t\tspeed = <1000>;\n"
  },
  {
    "path": "target/linux/bcm4908/patches-5.10/032-v5.13-0010-arm64-dts-broadcom-bcm4908-add-Ethernet-TX-irq.patch",
    "content": "From 5337af7918bedde9713cd223ce5df74b3d6c7d7a Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Wed, 17 Mar 2021 09:16:31 +0100\nSubject: [PATCH] arm64: dts: broadcom: bcm4908: add Ethernet TX irq\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nThis hardware supports two interrupts, one per DMA channel (RX and TX).\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi | 5 +++--\n 1 file changed, 3 insertions(+), 2 deletions(-)\n\n--- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi\n+++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi\n@@ -116,8 +116,9 @@\n \t\t\tcompatible = \"brcm,bcm4908-enet\";\n \t\t\treg = <0x2000 0x1000>;\n \n-\t\t\tinterrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;\n-\t\t\tinterrupt-names = \"rx\";\n+\t\t\tinterrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t\t     <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tinterrupt-names = \"rx\", \"tx\";\n \t\t};\n \n \t\tusb_phy: usb-phy@c200 {\n"
  },
  {
    "path": "target/linux/bcm4908/patches-5.10/032-v5.13-0011-arm64-dts-broadcom-bcm4908-add-Ethernet-MAC-addr.patch",
    "content": "From 9f01f5cdb548352418b34ce77db02a560fe2913b Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Mon, 29 Mar 2021 17:45:14 +0200\nSubject: [PATCH] arm64: dts: broadcom: bcm4908: add Ethernet MAC addr\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nOn most BCM4908 devices MAC address can be read from the bootloader\nbinary section containing device settings. Use NVMEM to describe that.\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n .../broadcom/bcm4908/bcm4906-netgear-r8000p.dts    | 14 ++++++++++++++\n .../broadcom/bcm4908/bcm4908-asus-gt-ac5300.dts    | 14 ++++++++++++++\n 2 files changed, 28 insertions(+)\n\n--- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4906-netgear-r8000p.dts\n+++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4906-netgear-r8000p.dts\n@@ -74,6 +74,11 @@\n \t};\n };\n \n+&enet {\n+\tnvmem-cells = <&base_mac_addr>;\n+\tnvmem-cell-names = \"mac-address\";\n+};\n+\n &usb_phy {\n \tbrcm,ioc = <1>;\n \tstatus = \"okay\";\n@@ -130,8 +135,17 @@\n \t\t#size-cells = <1>;\n \n \t\tpartition@0 {\n+\t\t\tcompatible = \"nvmem-cells\";\n \t\t\tlabel = \"cferom\";\n \t\t\treg = <0x0 0x100000>;\n+\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <1>;\n+\t\t\tranges = <0 0x0 0x100000>;\n+\n+\t\t\tbase_mac_addr: mac@106a0 {\n+\t\t\t\treg = <0x106a0 0x6>;\n+\t\t\t};\n \t\t};\n \n \t\tpartition@100000 {\n--- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908-asus-gt-ac5300.dts\n+++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908-asus-gt-ac5300.dts\n@@ -44,6 +44,11 @@\n \t};\n };\n \n+&enet {\n+\tnvmem-cells = <&base_mac_addr>;\n+\tnvmem-cell-names = \"mac-address\";\n+};\n+\n &usb_phy {\n \tbrcm,ioc = <1>;\n \tstatus = \"okay\";\n@@ -128,8 +133,17 @@\n \t\t#size-cells = <1>;\n \n \t\tpartition@0 {\n+\t\t\tcompatible = \"nvmem-cells\";\n \t\t\tlabel = \"cferom\";\n \t\t\treg = <0x0 0x100000>;\n+\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <1>;\n+\t\t\tranges = <0 0x0 0x100000>;\n+\n+\t\t\tbase_mac_addr: mac@106a0 {\n+\t\t\t\treg = <0x106a0 0x6>;\n+\t\t\t};\n \t\t};\n \n \t\tpartition@100000 {\n"
  },
  {
    "path": "target/linux/bcm4908/patches-5.10/033-v5.14-0001-ARM-dts-BCM5301X-Fix-NAND-nodes-names.patch",
    "content": "From b660269cba748dfd07eb5551a88ff34d5ea0b86e Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Fri, 16 Apr 2021 15:37:48 +0200\nSubject: [PATCH] ARM: dts: BCM5301X: Fix NAND nodes names\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nThis matches nand-controller.yaml requirements.\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n\n--- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi\n+++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi\n@@ -306,7 +306,7 @@\n \t\t\tinterrupt-names = \"nand\";\n \t\t\tstatus = \"okay\";\n \n-\t\t\tnandcs: nandcs@0 {\n+\t\t\tnandcs: nand@0 {\n \t\t\t\tcompatible = \"brcm,nandcs\";\n \t\t\t\treg = <0>;\n \t\t\t};\n"
  },
  {
    "path": "target/linux/bcm4908/patches-5.10/034-v5.16-0001-arm64-dts-broadcom-bcm4908-Fix-NAND-node-name.patch",
    "content": "From d0ae9c944b9472c5691a482297df7a57d7fd1199 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Thu, 19 Aug 2021 14:11:08 +0200\nSubject: [PATCH] arm64: dts: broadcom: bcm4908: Fix NAND node name\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nThis matches nand-controller.yaml requirements.\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi\n+++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi\n@@ -296,7 +296,7 @@\n \t\t\tstatus = \"okay\";\n \t\t};\n \n-\t\tnand@1800 {\n+\t\tnand-controller@1800 {\n \t\t\t#address-cells = <1>;\n \t\t\t#size-cells = <0>;\n \t\t\tcompatible = \"brcm,nand-bcm63138\", \"brcm,brcmnand-v7.1\", \"brcm,brcmnand\";\n"
  },
  {
    "path": "target/linux/bcm4908/patches-5.10/034-v5.16-0002-arm64-dts-broadcom-bcm4908-Move-reboot-syscon-out-of.patch",
    "content": "From 6cf9f70255b90b540b9cbde062f18fea29024a75 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Thu, 19 Aug 2021 14:26:06 +0200\nSubject: [PATCH] arm64: dts: broadcom: bcm4908: Move reboot syscon out of bus\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nThis fixes following error for every bcm4908 DTS file:\nbus@ff800000: reboot: {'type': 'object'} is not allowed for {'compatible': ['syscon-reboot'], 'regmap': [[15]], 'offset': [[52]], 'mask': [[1]]}\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi | 12 ++++++------\n 1 file changed, 6 insertions(+), 6 deletions(-)\n\n--- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi\n+++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi\n@@ -326,12 +326,12 @@\n \t\t\t\t#reset-cells = <1>;\n \t\t\t};\n \t\t};\n+\t};\n \n-\t\treboot {\n-\t\t\tcompatible = \"syscon-reboot\";\n-\t\t\tregmap = <&timer>;\n-\t\t\toffset = <0x34>;\n-\t\t\tmask = <1>;\n-\t\t};\n+\treboot {\n+\t\tcompatible = \"syscon-reboot\";\n+\t\tregmap = <&timer>;\n+\t\toffset = <0x34>;\n+\t\tmask = <1>;\n \t};\n };\n"
  },
  {
    "path": "target/linux/bcm4908/patches-5.10/034-v5.16-0003-arm64-dts-broadcom-bcm4908-Fix-UART-clock-name.patch",
    "content": "From 6c38c39ab2141f53786d73e706675e8819a3f2cb Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Thu, 19 Aug 2021 17:37:02 +0200\nSubject: [PATCH] arm64: dts: broadcom: bcm4908: Fix UART clock name\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nAccording to the binding the correct clock name is \"refclk\".\n\nFixes: 2961f69f151c (\"arm64: dts: broadcom: add BCM4908 and Asus GT-AC5300 early DTS files\")\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi\n+++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi\n@@ -292,7 +292,7 @@\n \t\t\treg = <0x640 0x18>;\n \t\t\tinterrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;\n \t\t\tclocks = <&periph_clk>;\n-\t\t\tclock-names = \"periph\";\n+\t\t\tclock-names = \"refclk\";\n \t\t\tstatus = \"okay\";\n \t\t};\n \n"
  },
  {
    "path": "target/linux/bcm4908/patches-5.10/035-v5.17-0001-dt-bindings-arm-bcm-document-Netgear-RAXE500-binding.patch",
    "content": "From 7b0c9ca7f18e8d2e2cf3c342d91f037d436777bf Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Fri, 5 Nov 2021 11:14:12 +0100\nSubject: [PATCH] dt-bindings: arm: bcm: document Netgear RAXE500 binding\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nOne more BCM4908 based device.\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nAcked-by: Rob Herring <robh@kernel.org>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n Documentation/devicetree/bindings/arm/bcm/brcm,bcm4908.yaml | 1 +\n 1 file changed, 1 insertion(+)\n\n--- a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4908.yaml\n+++ b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4908.yaml\n@@ -29,6 +29,7 @@ properties:\n         items:\n           - enum:\n               - asus,gt-ac5300\n+              - netgear,raxe500\n           - const: brcm,bcm4908\n \n       - description: BCM49408 based boards\n"
  },
  {
    "path": "target/linux/bcm4908/patches-5.10/035-v5.17-0002-arm64-dts-broadcom-bcm4908-add-DT-for-Netgear-RAXE50.patch",
    "content": "From d0e68d354f345873e15876a7b35be1baaf5e3ec9 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Fri, 5 Nov 2021 11:14:13 +0100\nSubject: [PATCH] arm64: dts: broadcom: bcm4908: add DT for Netgear RAXE500\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nIt's a home router based on BCM4908 SoC. It has: 1 GiB of RAM, 512 MiB\nNAND flash, 6 Ethernet ports and 3 x BCM43684 (WiFi). One of Ethernet\nports is \"2.5 G Multi-Gig port\" that isn't described yet (it isn't known\nhow it's wired up).\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n arch/arm64/boot/dts/broadcom/bcm4908/Makefile |  1 +\n .../bcm4908/bcm4908-netgear-raxe500.dts       | 50 +++++++++++++++++++\n 2 files changed, 51 insertions(+)\n create mode 100644 arch/arm64/boot/dts/broadcom/bcm4908/bcm4908-netgear-raxe500.dts\n\n--- a/arch/arm64/boot/dts/broadcom/bcm4908/Makefile\n+++ b/arch/arm64/boot/dts/broadcom/bcm4908/Makefile\n@@ -2,3 +2,4 @@\n dtb-$(CONFIG_ARCH_BCM4908) += bcm4906-netgear-r8000p.dtb\n dtb-$(CONFIG_ARCH_BCM4908) += bcm4906-tplink-archer-c2300-v1.dtb\n dtb-$(CONFIG_ARCH_BCM4908) += bcm4908-asus-gt-ac5300.dtb\n+dtb-$(CONFIG_ARCH_BCM4908) += bcm4908-netgear-raxe500.dtb\n--- /dev/null\n+++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908-netgear-raxe500.dts\n@@ -0,0 +1,50 @@\n+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n+\n+#include \"bcm4908.dtsi\"\n+\n+/ {\n+\tcompatible = \"netgear,raxe500\", \"brcm,bcm4908\";\n+\tmodel = \"Netgear RAXE500\";\n+\n+\tmemory@0 {\n+\t\tdevice_type = \"memory\";\n+\t\treg = <0x00 0x00 0x00 0x40000000>;\n+\t};\n+};\n+\n+&ehci {\n+\tstatus = \"okay\";\n+};\n+\n+&ohci {\n+\tstatus = \"okay\";\n+};\n+\n+&xhci {\n+\tstatus = \"okay\";\n+};\n+\n+&ports {\n+\tport@0 {\n+\t\tlabel = \"lan4\";\n+\t};\n+\n+\tport@1 {\n+\t\tlabel = \"lan3\";\n+\t};\n+\n+\tport@2 {\n+\t\tlabel = \"lan2\";\n+\t};\n+\n+\tport@3 {\n+\t\tlabel = \"lan1\";\n+\t};\n+\n+\tport@7 {\n+\t\treg = <7>;\n+\t\tphy-mode = \"internal\";\n+\t\tphy-handle = <&phy12>;\n+\t\tlabel = \"wan\";\n+\t};\n+};\n"
  },
  {
    "path": "target/linux/bcm4908/patches-5.10/036-v5.18-0001-arm64-dts-broadcom-bcm4908-use-proper-TWD-binding.patch",
    "content": "From 33826e9c6ba76b265d4e26cb95493fa27ed78974 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Wed, 29 Dec 2021 11:23:14 +0100\nSubject: [PATCH] arm64: dts: broadcom: bcm4908: use proper TWD binding\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nBlock at <ff800400 0x4c> is a TWD that contains timers, watchdog and\nreset. Actual timers happen to be at block beginning but they only span\nacross the first 0x28 registers. It means the old block description was\nincorrect (size 0x3c).\n\nDrop timers binding for now and use documented TWD binding. Timers\nshould be properly documented and defined as TWD subnode.\n\nFixes: 2961f69f151c (\"arm64: dts: broadcom: add BCM4908 and Asus GT-AC5300 early DTS files\")\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi | 8 ++++----\n 1 file changed, 4 insertions(+), 4 deletions(-)\n\n--- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi\n+++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi\n@@ -273,9 +273,9 @@\n \t\t#size-cells = <1>;\n \t\tranges = <0x00 0x00 0xff800000 0x3000>;\n \n-\t\ttimer: timer@400 {\n-\t\t\tcompatible = \"brcm,bcm6328-timer\", \"syscon\";\n-\t\t\treg = <0x400 0x3c>;\n+\t\ttwd: timer-mfd@400 {\n+\t\t\tcompatible = \"brcm,bcm4908-twd\", \"simple-mfd\", \"syscon\";\n+\t\t\treg = <0x400 0x4c>;\n \t\t};\n \n \t\tgpio0: gpio-controller@500 {\n@@ -330,7 +330,7 @@\n \n \treboot {\n \t\tcompatible = \"syscon-reboot\";\n-\t\tregmap = <&timer>;\n+\t\tregmap = <&twd>;\n \t\toffset = <0x34>;\n \t\tmask = <1>;\n \t};\n"
  },
  {
    "path": "target/linux/bcm4908/patches-5.10/036-v5.18-0002-arm64-dts-broadcom-bcm4908-add-pinctrl-binding.patch",
    "content": "From 72b1c5da796ec5266f2012c36470e226cb4f09c9 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Thu, 30 Dec 2021 12:05:35 +0100\nSubject: [PATCH] arm64: dts: broadcom: bcm4908: add pinctrl binding\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nDescribe pinmux block with its maps.\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n .../boot/dts/broadcom/bcm4908/bcm4908.dtsi    | 135 ++++++++++++++++++\n 1 file changed, 135 insertions(+)\n\n--- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi\n+++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi\n@@ -287,6 +287,141 @@\n \t\t\tgpio-controller;\n \t\t};\n \n+\t\tpinctrl@560 {\n+\t\t\tcompatible = \"brcm,bcm4908-pinctrl\";\n+\t\t\treg = <0x560 0x10>;\n+\n+\t\t\tpins_led_0_a: led_0-a-pins {\n+\t\t\t\tfunction = \"led_0\";\n+\t\t\t\tgroups = \"led_0_grp_a\";\n+\t\t\t};\n+\n+\t\t\tpins_led_1_a: led_1-a-pins {\n+\t\t\t\tfunction = \"led_1\";\n+\t\t\t\tgroups = \"led_1_grp_a\";\n+\t\t\t};\n+\n+\t\t\tpins_led_2_a: led_2-a-pins {\n+\t\t\t\tfunction = \"led_2\";\n+\t\t\t\tgroups = \"led_2_grp_a\";\n+\t\t\t};\n+\n+\t\t\tpins_led_3_a: led_3-a-pins {\n+\t\t\t\tfunction = \"led_3\";\n+\t\t\t\tgroups = \"led_3_grp_a\";\n+\t\t\t};\n+\n+\t\t\tpins_led_4_a: led_4-a-pins {\n+\t\t\t\tfunction = \"led_4\";\n+\t\t\t\tgroups = \"led_4_grp_a\";\n+\t\t\t};\n+\n+\t\t\tpins_led_5_a: led_5-a-pins {\n+\t\t\t\tfunction = \"led_5\";\n+\t\t\t\tgroups = \"led_5_grp_a\";\n+\t\t\t};\n+\n+\t\t\tpins_led_6_a: led_6-a-pins {\n+\t\t\t\tfunction = \"led_6\";\n+\t\t\t\tgroups = \"led_6_grp_a\";\n+\t\t\t};\n+\n+\t\t\tpins_led_7_a: led_7-a-pins {\n+\t\t\t\tfunction = \"led_7\";\n+\t\t\t\tgroups = \"led_7_grp_a\";\n+\t\t\t};\n+\n+\t\t\tpins_led_8_a: led_8-a-pins {\n+\t\t\t\tfunction = \"led_8\";\n+\t\t\t\tgroups = \"led_8_grp_a\";\n+\t\t\t};\n+\n+\t\t\tpins_led_9_a: led_9-a-pins {\n+\t\t\t\tfunction = \"led_9\";\n+\t\t\t\tgroups = \"led_9_grp_a\";\n+\t\t\t};\n+\n+\t\t\tpins_led_21_a: led_21-a-pins {\n+\t\t\t\tfunction = \"led_21\";\n+\t\t\t\tgroups = \"led_21_grp_a\";\n+\t\t\t};\n+\n+\t\t\tpins_led_22_a: led_22-a-pins {\n+\t\t\t\tfunction = \"led_22\";\n+\t\t\t\tgroups = \"led_22_grp_a\";\n+\t\t\t};\n+\n+\t\t\tpins_led_26_a: led_26-a-pins {\n+\t\t\t\tfunction = \"led_26\";\n+\t\t\t\tgroups = \"led_26_grp_a\";\n+\t\t\t};\n+\n+\t\t\tpins_led_27_a: led_27-a-pins {\n+\t\t\t\tfunction = \"led_27\";\n+\t\t\t\tgroups = \"led_27_grp_a\";\n+\t\t\t};\n+\n+\t\t\tpins_led_28_a: led_28-a-pins {\n+\t\t\t\tfunction = \"led_28\";\n+\t\t\t\tgroups = \"led_28_grp_a\";\n+\t\t\t};\n+\n+\t\t\tpins_led_29_a: led_29-a-pins {\n+\t\t\t\tfunction = \"led_29\";\n+\t\t\t\tgroups = \"led_29_grp_a\";\n+\t\t\t};\n+\n+\t\t\tpins_led_30_a: led_30-a-pins {\n+\t\t\t\tfunction = \"led_30\";\n+\t\t\t\tgroups = \"led_30_grp_a\";\n+\t\t\t};\n+\n+\t\t\tpins_hs_uart: hs_uart-pins {\n+\t\t\t\tfunction = \"hs_uart\";\n+\t\t\t\tgroups = \"hs_uart_grp\";\n+\t\t\t};\n+\n+\t\t\tpins_i2c_a: i2c-a-pins {\n+\t\t\t\tfunction = \"i2c\";\n+\t\t\t\tgroups = \"i2c_grp_a\";\n+\t\t\t};\n+\n+\t\t\tpins_i2c_b: i2c-b-pins {\n+\t\t\t\tfunction = \"i2c\";\n+\t\t\t\tgroups = \"i2c_grp_b\";\n+\t\t\t};\n+\n+\t\t\tpins_i2s: i2s-pins {\n+\t\t\t\tfunction = \"i2s\";\n+\t\t\t\tgroups = \"i2s_grp\";\n+\t\t\t};\n+\n+\t\t\tpins_nand_ctrl: nand_ctrl-pins {\n+\t\t\t\tfunction = \"nand_ctrl\";\n+\t\t\t\tgroups = \"nand_ctrl_grp\";\n+\t\t\t};\n+\n+\t\t\tpins_nand_data: nand_data-pins {\n+\t\t\t\tfunction = \"nand_data\";\n+\t\t\t\tgroups = \"nand_data_grp\";\n+\t\t\t};\n+\n+\t\t\tpins_emmc_ctrl: emmc_ctrl-pins {\n+\t\t\t\tfunction = \"emmc_ctrl\";\n+\t\t\t\tgroups = \"emmc_ctrl_grp\";\n+\t\t\t};\n+\n+\t\t\tpins_usb0_pwr: usb0_pwr-pins {\n+\t\t\t\tfunction = \"usb0_pwr\";\n+\t\t\t\tgroups = \"usb0_pwr_grp\";\n+\t\t\t};\n+\n+\t\t\tpins_usb1_pwr: usb1_pwr-pins {\n+\t\t\t\tfunction = \"usb1_pwr\";\n+\t\t\t\tgroups = \"usb1_pwr_grp\";\n+\t\t\t};\n+\t\t};\n+\n \t\tuart0: serial@640 {\n \t\t\tcompatible = \"brcm,bcm6345-uart\";\n \t\t\treg = <0x640 0x18>;\n"
  },
  {
    "path": "target/linux/bcm4908/patches-5.10/036-v5.18-0003-arm64-dts-broadcom-bcm4908-add-watchdog-block.patch",
    "content": "From 47513f6dd93b5b7d91143219c2c1fb883664ed13 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Wed, 9 Feb 2022 21:14:17 +0100\nSubject: [PATCH] arm64: dts: broadcom: bcm4908: add watchdog block\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nBCM4908 has the same watchdog as BCM63xx devices. Use \"brcm,bcm6345-wdt\"\nbinding which matches the first SoC with that block.\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi | 9 +++++++++\n 1 file changed, 9 insertions(+)\n\n--- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi\n+++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi\n@@ -276,6 +276,15 @@\n \t\ttwd: timer-mfd@400 {\n \t\t\tcompatible = \"brcm,bcm4908-twd\", \"simple-mfd\", \"syscon\";\n \t\t\treg = <0x400 0x4c>;\n+\t\t\tranges = <0x0 0x400 0x4c>;\n+\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <1>;\n+\n+\t\t\twatchdog@28 {\n+\t\t\t\tcompatible = \"brcm,bcm6345-wdt\";\n+\t\t\t\treg = <0x28 0x8>;\n+\t\t\t};\n \t\t};\n \n \t\tgpio0: gpio-controller@500 {\n"
  },
  {
    "path": "target/linux/bcm4908/patches-5.10/036-v5.18-0004-arm64-dts-broadcom-bcm4908-add-I2C-block.patch",
    "content": "From ba5dfa2fd8d0aed4e4b6f650ba9e8ea7cdd6ead1 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Tue, 15 Feb 2022 07:36:39 +0100\nSubject: [PATCH] arm64: dts: broadcom: bcm4908: add I2C block\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nBCM4908 uses the same I2C hw as BCM63xx / BCM67xx / BCM68xx SoCs.\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi | 9 +++++++++\n 1 file changed, 9 insertions(+)\n\n--- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi\n+++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi\n@@ -456,6 +456,15 @@\n \t\t\t};\n \t\t};\n \n+\t\ti2c@2100 {\n+\t\t\tcompatible = \"brcm,brcmper-i2c\";\n+\t\t\treg = <0x2100 0x58>;\n+\t\t\tclock-frequency = <97500>;\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&pins_i2c_a>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n \t\tmisc@2600 {\n \t\t\tcompatible = \"brcm,misc\", \"simple-mfd\";\n \t\t\treg = <0x2600 0xe4>;\n"
  },
  {
    "path": "target/linux/bcm4908/patches-5.10/071-v5.12-0001-net-dsa-bcm_sf2-support-BCM4908-s-integrated-switch.patch",
    "content": "From 73b7a6047971aa6ce4a70fc4901964d14f077171 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Wed, 6 Jan 2021 22:32:02 +0100\nSubject: [PATCH] net: dsa: bcm_sf2: support BCM4908's integrated switch\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nBCM4908 family SoCs come with integrated Starfighter 2 switch. Its\nregisters layout it a mix of BCM7278 and BCM7445. It has 5 integrated\nPHYs and 8 ports. It also supports RGMII and SerDes.\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nAcked-by: Florian Fainelli <f.fainelli@gmail.com>\nLink: https://lore.kernel.org/r/20210106213202.17459-3-zajec5@gmail.com\nSigned-off-by: Jakub Kicinski <kuba@kernel.org>\n---\n drivers/net/dsa/b53/b53_common.c | 14 +++++++++++++\n drivers/net/dsa/b53/b53_priv.h   |  1 +\n drivers/net/dsa/bcm_sf2.c        | 36 +++++++++++++++++++++++++++++---\n drivers/net/dsa/bcm_sf2_regs.h   |  1 +\n 4 files changed, 49 insertions(+), 3 deletions(-)\n\n--- a/drivers/net/dsa/b53/b53_common.c\n+++ b/drivers/net/dsa/b53/b53_common.c\n@@ -2493,6 +2493,22 @@ static const struct b53_chip_data b53_sw\n \t\t.jumbo_pm_reg = B53_JUMBO_PORT_MASK,\n \t\t.jumbo_size_reg = B53_JUMBO_MAX_SIZE,\n \t},\n+\t/* Starfighter 2 */\n+\t{\n+\t\t.chip_id = BCM4908_DEVICE_ID,\n+\t\t.dev_name = \"BCM4908\",\n+\t\t.vlans = 4096,\n+\t\t.enabled_ports = 0x1bf,\n+#if 0\n+\t\t.arl_bins = 4,\n+\t\t.arl_buckets = 256,\n+#endif\n+\t\t.cpu_port = 8, /* TODO: ports 4, 5, 8 */\n+\t\t.vta_regs = B53_VTA_REGS,\n+\t\t.duplex_reg = B53_DUPLEX_STAT_GE,\n+\t\t.jumbo_pm_reg = B53_JUMBO_PORT_MASK,\n+\t\t.jumbo_size_reg = B53_JUMBO_MAX_SIZE,\n+\t},\n \t{\n \t\t.chip_id = BCM7445_DEVICE_ID,\n \t\t.dev_name = \"BCM7445\",\n--- a/drivers/net/dsa/b53/b53_priv.h\n+++ b/drivers/net/dsa/b53/b53_priv.h\n@@ -64,6 +64,7 @@ struct b53_io_ops {\n #define B53_INVALID_LANE\t0xff\n \n enum {\n+\tBCM4908_DEVICE_ID = 0x4908,\n \tBCM5325_DEVICE_ID = 0x25,\n \tBCM5365_DEVICE_ID = 0x65,\n \tBCM5389_DEVICE_ID = 0x89,\n--- a/drivers/net/dsa/bcm_sf2.c\n+++ b/drivers/net/dsa/bcm_sf2.c\n@@ -105,7 +105,8 @@ static void bcm_sf2_imp_setup(struct dsa\n \tb53_brcm_hdr_setup(ds, port);\n \n \tif (port == 8) {\n-\t\tif (priv->type == BCM7445_DEVICE_ID)\n+\t\tif (priv->type == BCM4908_DEVICE_ID ||\n+\t\t    priv->type == BCM7445_DEVICE_ID)\n \t\t\toffset = CORE_STS_OVERRIDE_IMP;\n \t\telse\n \t\t\toffset = CORE_STS_OVERRIDE_IMP2;\n@@ -711,7 +712,8 @@ static void bcm_sf2_sw_mac_link_down(str\n \tu32 reg, offset;\n \n \tif (port != core_readl(priv, CORE_IMP0_PRT_ID)) {\n-\t\tif (priv->type == BCM7445_DEVICE_ID)\n+\t\tif (priv->type == BCM4908_DEVICE_ID ||\n+\t\t    priv->type == BCM7445_DEVICE_ID)\n \t\t\toffset = CORE_STS_OVERRIDE_GMIIP_PORT(port);\n \t\telse\n \t\t\toffset = CORE_STS_OVERRIDE_GMIIP2_PORT(port);\n@@ -738,7 +740,8 @@ static void bcm_sf2_sw_mac_link_up(struc\n \tbcm_sf2_sw_mac_link_set(ds, port, interface, true);\n \n \tif (port != core_readl(priv, CORE_IMP0_PRT_ID)) {\n-\t\tif (priv->type == BCM7445_DEVICE_ID)\n+\t\tif (priv->type == BCM4908_DEVICE_ID ||\n+\t\t    priv->type == BCM7445_DEVICE_ID)\n \t\t\toffset = CORE_STS_OVERRIDE_GMIIP_PORT(port);\n \t\telse\n \t\t\toffset = CORE_STS_OVERRIDE_GMIIP2_PORT(port);\n@@ -1131,6 +1134,30 @@ struct bcm_sf2_of_data {\n \tunsigned int num_cfp_rules;\n };\n \n+static const u16 bcm_sf2_4908_reg_offsets[] = {\n+\t[REG_SWITCH_CNTRL]\t= 0x00,\n+\t[REG_SWITCH_STATUS]\t= 0x04,\n+\t[REG_DIR_DATA_WRITE]\t= 0x08,\n+\t[REG_DIR_DATA_READ]\t= 0x0c,\n+\t[REG_SWITCH_REVISION]\t= 0x10,\n+\t[REG_PHY_REVISION]\t= 0x14,\n+\t[REG_SPHY_CNTRL]\t= 0x24,\n+\t[REG_CROSSBAR]\t\t= 0xc8,\n+\t[REG_RGMII_0_CNTRL]\t= 0xe0,\n+\t[REG_RGMII_1_CNTRL]\t= 0xec,\n+\t[REG_RGMII_2_CNTRL]\t= 0xf8,\n+\t[REG_LED_0_CNTRL]\t= 0x40,\n+\t[REG_LED_1_CNTRL]\t= 0x4c,\n+\t[REG_LED_2_CNTRL]\t= 0x58,\n+};\n+\n+static const struct bcm_sf2_of_data bcm_sf2_4908_data = {\n+\t.type\t\t= BCM4908_DEVICE_ID,\n+\t.core_reg_align\t= 0,\n+\t.reg_offsets\t= bcm_sf2_4908_reg_offsets,\n+\t.num_cfp_rules\t= 0, /* FIXME */\n+};\n+\n /* Register offsets for the SWITCH_REG_* block */\n static const u16 bcm_sf2_7445_reg_offsets[] = {\n \t[REG_SWITCH_CNTRL]\t= 0x00,\n@@ -1179,6 +1206,9 @@ static const struct bcm_sf2_of_data bcm_\n };\n \n static const struct of_device_id bcm_sf2_of_match[] = {\n+\t{ .compatible = \"brcm,bcm4908-switch\",\n+\t  .data = &bcm_sf2_4908_data\n+\t},\n \t{ .compatible = \"brcm,bcm7445-switch-v4.0\",\n \t  .data = &bcm_sf2_7445_data\n \t},\n--- a/drivers/net/dsa/bcm_sf2_regs.h\n+++ b/drivers/net/dsa/bcm_sf2_regs.h\n@@ -17,6 +17,7 @@ enum bcm_sf2_reg_offs {\n \tREG_SWITCH_REVISION,\n \tREG_PHY_REVISION,\n \tREG_SPHY_CNTRL,\n+\tREG_CROSSBAR,\n \tREG_RGMII_0_CNTRL,\n \tREG_RGMII_1_CNTRL,\n \tREG_RGMII_2_CNTRL,\n"
  },
  {
    "path": "target/linux/bcm4908/patches-5.10/071-v5.12-0002-net-dsa-bcm_sf2-use-2-Gbps-IMP-port-link-on-BCM4908.patch",
    "content": "From 8373a0fe9c7160a55482effa8a3f725efd3f8434 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Wed, 10 Mar 2021 13:51:59 +0100\nSubject: [PATCH] net: dsa: bcm_sf2: use 2 Gbps IMP port link on BCM4908\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nBCM4908 uses 2 Gbps link between switch and the Ethernet interface.\nWithout this BCM4908 devices were able to achieve only 2 x ~895 Mb/s.\nThis allows handling e.g. NAT traffic with 940 Mb/s.\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nAcked-by: Florian Fainelli <f.fainelli@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/dsa/bcm_sf2.c | 5 ++++-\n 1 file changed, 4 insertions(+), 1 deletion(-)\n\n--- a/drivers/net/dsa/bcm_sf2.c\n+++ b/drivers/net/dsa/bcm_sf2.c\n@@ -114,7 +114,10 @@ static void bcm_sf2_imp_setup(struct dsa\n \t\t/* Force link status for IMP port */\n \t\treg = core_readl(priv, offset);\n \t\treg |= (MII_SW_OR | LINK_STS);\n-\t\treg &= ~GMII_SPEED_UP_2G;\n+\t\tif (priv->type == BCM4908_DEVICE_ID)\n+\t\t\treg |= GMII_SPEED_UP_2G;\n+\t\telse\n+\t\t\treg &= ~GMII_SPEED_UP_2G;\n \t\tcore_writel(priv, reg, offset);\n \n \t\t/* Enable Broadcast, Multicast, Unicast forwarding to IMP port */\n"
  },
  {
    "path": "target/linux/bcm4908/patches-5.10/072-v5.12-0001-dt-bindings-net-document-BCM4908-Ethernet-controller.patch",
    "content": "From 387d1c1819790aa8398c7cffab587f9a050a0d1a Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Sun, 7 Feb 2021 23:26:31 +0100\nSubject: [PATCH] dt-bindings: net: document BCM4908 Ethernet controller\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nBCM4908 is a family of SoCs with integrated Ethernet controller.\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n .../bindings/net/brcm,bcm4908enet.yaml        | 45 +++++++++++++++++++\n 1 file changed, 45 insertions(+)\n create mode 100644 Documentation/devicetree/bindings/net/brcm,bcm4908enet.yaml\n\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/net/brcm,bcm4908enet.yaml\n@@ -0,0 +1,45 @@\n+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause\n+%YAML 1.2\n+---\n+$id: http://devicetree.org/schemas/net/brcm,bcm4908enet.yaml#\n+$schema: http://devicetree.org/meta-schemas/core.yaml#\n+\n+title: Broadcom BCM4908 Ethernet controller\n+\n+description: Broadcom's Ethernet controller integrated into BCM4908 family SoCs\n+\n+maintainers:\n+  - Rafał Miłecki <rafal@milecki.pl>\n+\n+properties:\n+  compatible:\n+    const: brcm,bcm4908enet\n+\n+  reg:\n+    maxItems: 1\n+\n+  interrupts:\n+    description: RX interrupt\n+\n+  interrupt-names:\n+    const: rx\n+\n+required:\n+  - reg\n+  - interrupts\n+  - interrupt-names\n+\n+additionalProperties: false\n+\n+examples:\n+  - |\n+    #include <dt-bindings/interrupt-controller/irq.h>\n+    #include <dt-bindings/interrupt-controller/arm-gic.h>\n+\n+    ethernet@80002000 {\n+        compatible = \"brcm,bcm4908enet\";\n+        reg = <0x80002000 0x1000>;\n+\n+        interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;\n+        interrupt-names = \"rx\";\n+    };\n"
  },
  {
    "path": "target/linux/bcm4908/patches-5.10/072-v5.12-0002-net-broadcom-bcm4908enet-add-BCM4908-controller-driv.patch",
    "content": "From 4feffeadbcb2e5b11cbbf191a33c245b74a5837b Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Sun, 7 Feb 2021 23:26:32 +0100\nSubject: [PATCH] net: broadcom: bcm4908enet: add BCM4908 controller driver\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nBCM4908 SoCs family uses Ethernel controller that includes UniMAC but\nuses different DMA engine (than other controllers) and requires\ndifferent programming.\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n MAINTAINERS                                 |   9 +\n drivers/net/ethernet/broadcom/Kconfig       |   8 +\n drivers/net/ethernet/broadcom/Makefile      |   1 +\n drivers/net/ethernet/broadcom/bcm4908enet.c | 676 ++++++++++++++++++++\n drivers/net/ethernet/broadcom/bcm4908enet.h |  96 +++\n 5 files changed, 790 insertions(+)\n create mode 100644 drivers/net/ethernet/broadcom/bcm4908enet.c\n create mode 100644 drivers/net/ethernet/broadcom/bcm4908enet.h\n\n--- a/MAINTAINERS\n+++ b/MAINTAINERS\n@@ -3427,6 +3427,15 @@ F:\tDocumentation/devicetree/bindings/mip\n F:\tarch/mips/bcm47xx/*\n F:\tarch/mips/include/asm/mach-bcm47xx/*\n \n+BROADCOM BCM4908 ETHERNET DRIVER\n+M:\tRafał Miłecki <rafal@milecki.pl>\n+M:\tbcm-kernel-feedback-list@broadcom.com\n+L:\tnetdev@vger.kernel.org\n+S:\tMaintained\n+F:\tDocumentation/devicetree/bindings/net/brcm,bcm4908enet.yaml\n+F:\tdrivers/net/ethernet/broadcom/bcm4908enet.*\n+F:\tdrivers/net/ethernet/broadcom/unimac.h\n+\n BROADCOM BCM5301X ARM ARCHITECTURE\n M:\tHauke Mehrtens <hauke@hauke-m.de>\n M:\tRafał Miłecki <zajec5@gmail.com>\n--- a/drivers/net/ethernet/broadcom/Kconfig\n+++ b/drivers/net/ethernet/broadcom/Kconfig\n@@ -51,6 +51,14 @@ config B44_PCI\n \tdepends on B44_PCI_AUTOSELECT && B44_PCICORE_AUTOSELECT\n \tdefault y\n \n+config BCM4908ENET\n+\ttristate \"Broadcom BCM4908 internal mac support\"\n+\tdepends on ARCH_BCM4908 || COMPILE_TEST\n+\tdefault y\n+\thelp\n+\t  This driver supports Ethernet controller integrated into Broadcom\n+\t  BCM4908 family SoCs.\n+\n config BCM63XX_ENET\n \ttristate \"Broadcom 63xx internal mac support\"\n \tdepends on BCM63XX\n--- a/drivers/net/ethernet/broadcom/Makefile\n+++ b/drivers/net/ethernet/broadcom/Makefile\n@@ -4,6 +4,7 @@\n #\n \n obj-$(CONFIG_B44) += b44.o\n+obj-$(CONFIG_BCM4908ENET) += bcm4908enet.o\n obj-$(CONFIG_BCM63XX_ENET) += bcm63xx_enet.o\n obj-$(CONFIG_BCMGENET) += genet/\n obj-$(CONFIG_BNX2) += bnx2.o\n--- /dev/null\n+++ b/drivers/net/ethernet/broadcom/bcm4908enet.c\n@@ -0,0 +1,676 @@\n+// SPDX-License-Identifier: GPL-2.0-only\n+/*\n+ * Copyright (C) 2021 Rafał Miłecki <rafal@milecki.pl>\n+ */\n+\n+#include <linux/delay.h>\n+#include <linux/etherdevice.h>\n+#include <linux/interrupt.h>\n+#include <linux/module.h>\n+#include <linux/of.h>\n+#include <linux/platform_device.h>\n+#include <linux/slab.h>\n+#include <linux/string.h>\n+\n+#include \"bcm4908enet.h\"\n+#include \"unimac.h\"\n+\n+#define ENET_DMA_CH_RX_CFG\t\t\tENET_DMA_CH0_CFG\n+#define ENET_DMA_CH_TX_CFG\t\t\tENET_DMA_CH1_CFG\n+#define ENET_DMA_CH_RX_STATE_RAM\t\tENET_DMA_CH0_STATE_RAM\n+#define ENET_DMA_CH_TX_STATE_RAM\t\tENET_DMA_CH1_STATE_RAM\n+\n+#define ENET_TX_BDS_NUM\t\t\t\t200\n+#define ENET_RX_BDS_NUM\t\t\t\t200\n+#define ENET_RX_BDS_NUM_MAX\t\t\t8192\n+\n+#define ENET_DMA_INT_DEFAULTS\t\t\t(ENET_DMA_CH_CFG_INT_DONE | \\\n+\t\t\t\t\t\t ENET_DMA_CH_CFG_INT_NO_DESC | \\\n+\t\t\t\t\t\t ENET_DMA_CH_CFG_INT_BUFF_DONE)\n+#define ENET_DMA_MAX_BURST_LEN\t\t\t8 /* in 64 bit words */\n+\n+#define ENET_MTU_MIN\t\t\t\t60\n+#define ENET_MTU_MAX\t\t\t\t1500 /* Is it possible to support 2044? */\n+#define ENET_MTU_MAX_EXTRA_SIZE\t\t\t32 /* L2 */\n+\n+struct bcm4908enet_dma_ring_bd {\n+\t__le32 ctl;\n+\t__le32 addr;\n+} __packed;\n+\n+struct bcm4908enet_dma_ring_slot {\n+\tstruct sk_buff *skb;\n+\tunsigned int len;\n+\tdma_addr_t dma_addr;\n+};\n+\n+struct bcm4908enet_dma_ring {\n+\tint is_tx;\n+\tint read_idx;\n+\tint write_idx;\n+\tint length;\n+\tu16 cfg_block;\n+\tu16 st_ram_block;\n+\n+\tunion {\n+\t\tvoid *cpu_addr;\n+\t\tstruct bcm4908enet_dma_ring_bd *buf_desc;\n+\t};\n+\tdma_addr_t dma_addr;\n+\n+\tstruct bcm4908enet_dma_ring_slot *slots;\n+};\n+\n+struct bcm4908enet {\n+\tstruct device *dev;\n+\tstruct net_device *netdev;\n+\tstruct napi_struct napi;\n+\tvoid __iomem *base;\n+\n+\tstruct bcm4908enet_dma_ring tx_ring;\n+\tstruct bcm4908enet_dma_ring rx_ring;\n+};\n+\n+/***\n+ * R/W ops\n+ */\n+\n+static inline u32 enet_read(struct bcm4908enet *enet, u16 offset)\n+{\n+\treturn readl(enet->base + offset);\n+}\n+\n+static inline void enet_write(struct bcm4908enet *enet, u16 offset, u32 value)\n+{\n+\twritel(value, enet->base + offset);\n+}\n+\n+static inline void enet_maskset(struct bcm4908enet *enet, u16 offset, u32 mask, u32 set)\n+{\n+\tu32 val;\n+\n+\tWARN_ON(set & ~mask);\n+\n+\tval = enet_read(enet, offset);\n+\tval = (val & ~mask) | (set & mask);\n+\tenet_write(enet, offset, val);\n+}\n+\n+static inline void enet_set(struct bcm4908enet *enet, u16 offset, u32 set)\n+{\n+\tenet_maskset(enet, offset, set, set);\n+}\n+\n+static inline u32 enet_umac_read(struct bcm4908enet *enet, u16 offset)\n+{\n+\treturn enet_read(enet, ENET_UNIMAC + offset);\n+}\n+\n+static inline void enet_umac_write(struct bcm4908enet *enet, u16 offset, u32 value)\n+{\n+\tenet_write(enet, ENET_UNIMAC + offset, value);\n+}\n+\n+static inline void enet_umac_maskset(struct bcm4908enet *enet, u16 offset, u32 mask, u32 set)\n+{\n+\tenet_maskset(enet, ENET_UNIMAC + offset, mask, set);\n+}\n+\n+static inline void enet_umac_set(struct bcm4908enet *enet, u16 offset, u32 set)\n+{\n+\tenet_set(enet, ENET_UNIMAC + offset, set);\n+}\n+\n+/***\n+ * Helpers\n+ */\n+\n+static void bcm4908enet_intrs_on(struct bcm4908enet *enet)\n+{\n+\tenet_write(enet, ENET_DMA_CH_RX_CFG + ENET_DMA_CH_CFG_INT_MASK, ENET_DMA_INT_DEFAULTS);\n+}\n+\n+static void bcm4908enet_intrs_off(struct bcm4908enet *enet)\n+{\n+\tenet_write(enet, ENET_DMA_CH_RX_CFG + ENET_DMA_CH_CFG_INT_MASK, 0);\n+}\n+\n+static void bcm4908enet_intrs_ack(struct bcm4908enet *enet)\n+{\n+\tenet_write(enet, ENET_DMA_CH_RX_CFG + ENET_DMA_CH_CFG_INT_STAT, ENET_DMA_INT_DEFAULTS);\n+}\n+\n+/***\n+ * DMA\n+ */\n+\n+static int bcm4908_dma_alloc_buf_descs(struct bcm4908enet *enet, struct bcm4908enet_dma_ring *ring)\n+{\n+\tint size = ring->length * sizeof(struct bcm4908enet_dma_ring_bd);\n+\tstruct device *dev = enet->dev;\n+\n+\tring->cpu_addr = dma_alloc_coherent(dev, size, &ring->dma_addr, GFP_KERNEL);\n+\tif (!ring->cpu_addr)\n+\t\treturn -ENOMEM;\n+\n+\tif (((uintptr_t)ring->cpu_addr) & (0x40 - 1)) {\n+\t\tdev_err(dev, \"Invalid DMA ring alignment\\n\");\n+\t\tgoto err_free_buf_descs;\n+\t}\n+\n+\tring->slots = kzalloc(ring->length * sizeof(*ring->slots), GFP_KERNEL);\n+\tif (!ring->slots)\n+\t\tgoto err_free_buf_descs;\n+\n+\tmemset(ring->cpu_addr, 0, size);\n+\n+\tring->read_idx = 0;\n+\tring->write_idx = 0;\n+\n+\treturn 0;\n+\n+err_free_buf_descs:\n+\tdma_free_coherent(dev, size, ring->cpu_addr, ring->dma_addr);\n+\treturn -ENOMEM;\n+}\n+\n+static void bcm4908enet_dma_free(struct bcm4908enet *enet)\n+{\n+\tstruct bcm4908enet_dma_ring *tx_ring = &enet->tx_ring;\n+\tstruct bcm4908enet_dma_ring *rx_ring = &enet->rx_ring;\n+\tstruct device *dev = enet->dev;\n+\tint size;\n+\n+\tsize = rx_ring->length * sizeof(struct bcm4908enet_dma_ring_bd);\n+\tif (rx_ring->cpu_addr)\n+\t\tdma_free_coherent(dev, size, rx_ring->cpu_addr, rx_ring->dma_addr);\n+\tkfree(rx_ring->slots);\n+\n+\tsize = tx_ring->length * sizeof(struct bcm4908enet_dma_ring_bd);\n+\tif (tx_ring->cpu_addr)\n+\t\tdma_free_coherent(dev, size, tx_ring->cpu_addr, tx_ring->dma_addr);\n+\tkfree(tx_ring->slots);\n+}\n+\n+static int bcm4908enet_dma_alloc(struct bcm4908enet *enet)\n+{\n+\tstruct bcm4908enet_dma_ring *tx_ring = &enet->tx_ring;\n+\tstruct bcm4908enet_dma_ring *rx_ring = &enet->rx_ring;\n+\tstruct device *dev = enet->dev;\n+\tint err;\n+\n+\ttx_ring->length = ENET_TX_BDS_NUM;\n+\ttx_ring->is_tx = 1;\n+\ttx_ring->cfg_block = ENET_DMA_CH_TX_CFG;\n+\ttx_ring->st_ram_block = ENET_DMA_CH_TX_STATE_RAM;\n+\terr = bcm4908_dma_alloc_buf_descs(enet, tx_ring);\n+\tif (err) {\n+\t\tdev_err(dev, \"Failed to alloc TX buf descriptors: %d\\n\", err);\n+\t\treturn err;\n+\t}\n+\n+\trx_ring->length = ENET_RX_BDS_NUM;\n+\trx_ring->is_tx = 0;\n+\trx_ring->cfg_block = ENET_DMA_CH_RX_CFG;\n+\trx_ring->st_ram_block = ENET_DMA_CH_RX_STATE_RAM;\n+\terr = bcm4908_dma_alloc_buf_descs(enet, rx_ring);\n+\tif (err) {\n+\t\tdev_err(dev, \"Failed to alloc RX buf descriptors: %d\\n\", err);\n+\t\tbcm4908enet_dma_free(enet);\n+\t\treturn err;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static void bcm4908enet_dma_reset(struct bcm4908enet *enet)\n+{\n+\tstruct bcm4908enet_dma_ring *rings[] = { &enet->rx_ring, &enet->tx_ring };\n+\tint i;\n+\n+\t/* Disable the DMA controller and channel */\n+\tfor (i = 0; i < ARRAY_SIZE(rings); i++)\n+\t\tenet_write(enet, rings[i]->cfg_block + ENET_DMA_CH_CFG, 0);\n+\tenet_maskset(enet, ENET_DMA_CONTROLLER_CFG, ENET_DMA_CTRL_CFG_MASTER_EN, 0);\n+\n+\t/* Reset channels state */\n+\tfor (i = 0; i < ARRAY_SIZE(rings); i++) {\n+\t\tstruct bcm4908enet_dma_ring *ring = rings[i];\n+\n+\t\tenet_write(enet, ring->st_ram_block + ENET_DMA_CH_STATE_RAM_BASE_DESC_PTR, 0);\n+\t\tenet_write(enet, ring->st_ram_block + ENET_DMA_CH_STATE_RAM_STATE_DATA, 0);\n+\t\tenet_write(enet, ring->st_ram_block + ENET_DMA_CH_STATE_RAM_DESC_LEN_STATUS, 0);\n+\t\tenet_write(enet, ring->st_ram_block + ENET_DMA_CH_STATE_RAM_DESC_BASE_BUFPTR, 0);\n+\t}\n+}\n+\n+static int bcm4908enet_dma_alloc_rx_buf(struct bcm4908enet *enet, unsigned int idx)\n+{\n+\tstruct bcm4908enet_dma_ring_bd *buf_desc = &enet->rx_ring.buf_desc[idx];\n+\tstruct bcm4908enet_dma_ring_slot *slot = &enet->rx_ring.slots[idx];\n+\tstruct device *dev = enet->dev;\n+\tu32 tmp;\n+\tint err;\n+\n+\tslot->len = ENET_MTU_MAX + ENET_MTU_MAX_EXTRA_SIZE;\n+\n+\tslot->skb = netdev_alloc_skb(enet->netdev, slot->len);\n+\tif (!slot->skb)\n+\t\treturn -ENOMEM;\n+\n+\tslot->dma_addr = dma_map_single(dev, slot->skb->data, slot->len, DMA_FROM_DEVICE);\n+\terr = dma_mapping_error(dev, slot->dma_addr);\n+\tif (err) {\n+\t\tdev_err(dev, \"Failed to map DMA buffer: %d\\n\", err);\n+\t\tkfree_skb(slot->skb);\n+\t\tslot->skb = NULL;\n+\t\treturn err;\n+\t}\n+\n+\ttmp = slot->len << DMA_CTL_LEN_DESC_BUFLENGTH_SHIFT;\n+\ttmp |= DMA_CTL_STATUS_OWN;\n+\tif (idx == enet->rx_ring.length - 1)\n+\t\ttmp |= DMA_CTL_STATUS_WRAP;\n+\tbuf_desc->ctl = cpu_to_le32(tmp);\n+\tbuf_desc->addr = cpu_to_le32(slot->dma_addr);\n+\n+\treturn 0;\n+}\n+\n+static void bcm4908enet_dma_ring_init(struct bcm4908enet *enet,\n+\t\t\t\t      struct bcm4908enet_dma_ring *ring)\n+{\n+\tint reset_channel = 0; /* We support only 1 main channel (with TX and RX) */\n+\tint reset_subch = ring->is_tx ? 1 : 0;\n+\n+\t/* Reset the DMA channel */\n+\tenet_write(enet, ENET_DMA_CTRL_CHANNEL_RESET, BIT(reset_channel * 2 + reset_subch));\n+\tenet_write(enet, ENET_DMA_CTRL_CHANNEL_RESET, 0);\n+\n+\tenet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG, 0);\n+\tenet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG_MAX_BURST, ENET_DMA_MAX_BURST_LEN);\n+\tenet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG_INT_MASK, 0);\n+\n+\tenet_write(enet, ring->st_ram_block + ENET_DMA_CH_STATE_RAM_BASE_DESC_PTR,\n+\t\t   (uint32_t)ring->dma_addr);\n+}\n+\n+static void bcm4908enet_dma_uninit(struct bcm4908enet *enet)\n+{\n+\tstruct bcm4908enet_dma_ring *rx_ring = &enet->rx_ring;\n+\tstruct bcm4908enet_dma_ring_slot *slot;\n+\tstruct device *dev = enet->dev;\n+\tint i;\n+\n+\tfor (i = rx_ring->length - 1; i >= 0; i--) {\n+\t\tslot = &rx_ring->slots[i];\n+\t\tif (!slot->skb)\n+\t\t\tcontinue;\n+\t\tdma_unmap_single(dev, slot->dma_addr, slot->len, DMA_FROM_DEVICE);\n+\t\tkfree_skb(slot->skb);\n+\t\tslot->skb = NULL;\n+\t}\n+}\n+\n+static int bcm4908enet_dma_init(struct bcm4908enet *enet)\n+{\n+\tstruct bcm4908enet_dma_ring *rx_ring = &enet->rx_ring;\n+\tstruct device *dev = enet->dev;\n+\tint err;\n+\tint i;\n+\n+\tfor (i = 0; i < rx_ring->length; i++) {\n+\t\terr = bcm4908enet_dma_alloc_rx_buf(enet, i);\n+\t\tif (err) {\n+\t\t\tdev_err(dev, \"Failed to alloc RX buffer: %d\\n\", err);\n+\t\t\tbcm4908enet_dma_uninit(enet);\n+\t\t\treturn err;\n+\t\t}\n+\t}\n+\n+\tbcm4908enet_dma_ring_init(enet, &enet->tx_ring);\n+\tbcm4908enet_dma_ring_init(enet, &enet->rx_ring);\n+\n+\treturn 0;\n+}\n+\n+static void bcm4908enet_dma_tx_ring_ensable(struct bcm4908enet *enet,\n+\t\t\t\t\t    struct bcm4908enet_dma_ring *ring)\n+{\n+\tenet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG, ENET_DMA_CH_CFG_ENABLE);\n+}\n+\n+static void bcm4908enet_dma_tx_ring_disable(struct bcm4908enet *enet,\n+\t\t\t\t\t    struct bcm4908enet_dma_ring *ring)\n+{\n+\tenet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG, 0);\n+}\n+\n+static void bcm4908enet_dma_rx_ring_enable(struct bcm4908enet *enet,\n+\t\t\t\t\t   struct bcm4908enet_dma_ring *ring)\n+{\n+\tenet_set(enet, ring->cfg_block + ENET_DMA_CH_CFG, ENET_DMA_CH_CFG_ENABLE);\n+}\n+\n+static void bcm4908enet_dma_rx_ring_disable(struct bcm4908enet *enet,\n+\t\t\t\t\t    struct bcm4908enet_dma_ring *ring)\n+{\n+\tunsigned long deadline;\n+\tu32 tmp;\n+\n+\tenet_maskset(enet, ring->cfg_block + ENET_DMA_CH_CFG, ENET_DMA_CH_CFG_ENABLE, 0);\n+\n+\tdeadline = jiffies + usecs_to_jiffies(2000);\n+\tdo {\n+\t\ttmp = enet_read(enet, ring->cfg_block + ENET_DMA_CH_CFG);\n+\t\tif (!(tmp & ENET_DMA_CH_CFG_ENABLE))\n+\t\t\treturn;\n+\t\tenet_maskset(enet, ring->cfg_block + ENET_DMA_CH_CFG, ENET_DMA_CH_CFG_ENABLE, 0);\n+\t\tusleep_range(10, 30);\n+\t} while (!time_after_eq(jiffies, deadline));\n+\n+\tdev_warn(enet->dev, \"Timeout waiting for DMA TX stop\\n\");\n+}\n+\n+/***\n+ * Ethernet driver\n+ */\n+\n+static void bcm4908enet_gmac_init(struct bcm4908enet *enet)\n+{\n+\tu32 cmd;\n+\n+\tcmd = enet_umac_read(enet, UMAC_CMD);\n+\tenet_umac_write(enet, UMAC_CMD, cmd | CMD_SW_RESET);\n+\tenet_umac_write(enet, UMAC_CMD, cmd & ~CMD_SW_RESET);\n+\n+\tenet_set(enet, ENET_FLUSH, ENET_FLUSH_RXFIFO_FLUSH | ENET_FLUSH_TXFIFO_FLUSH);\n+\tenet_maskset(enet, ENET_FLUSH, ENET_FLUSH_RXFIFO_FLUSH | ENET_FLUSH_TXFIFO_FLUSH, 0);\n+\n+\tenet_set(enet, ENET_MIB_CTRL, ENET_MIB_CTRL_CLR_MIB);\n+\tenet_maskset(enet, ENET_MIB_CTRL, ENET_MIB_CTRL_CLR_MIB, 0);\n+\n+\tcmd = enet_umac_read(enet, UMAC_CMD);\n+\tcmd &= ~(CMD_SPEED_MASK << CMD_SPEED_SHIFT);\n+\tcmd &= ~CMD_TX_EN;\n+\tcmd &= ~CMD_RX_EN;\n+\tcmd |= CMD_SPEED_1000 << CMD_SPEED_SHIFT;\n+\tenet_umac_write(enet, UMAC_CMD, cmd);\n+\n+\tenet_maskset(enet, ENET_GMAC_STATUS,\n+\t\t     ENET_GMAC_STATUS_ETH_SPEED_MASK |\n+\t\t     ENET_GMAC_STATUS_HD |\n+\t\t     ENET_GMAC_STATUS_AUTO_CFG_EN |\n+\t\t     ENET_GMAC_STATUS_LINK_UP,\n+\t\t     ENET_GMAC_STATUS_ETH_SPEED_1000 |\n+\t\t     ENET_GMAC_STATUS_AUTO_CFG_EN |\n+\t\t     ENET_GMAC_STATUS_LINK_UP);\n+}\n+\n+static irqreturn_t bcm4908enet_irq_handler(int irq, void *dev_id)\n+{\n+\tstruct bcm4908enet *enet = dev_id;\n+\n+\tbcm4908enet_intrs_off(enet);\n+\tbcm4908enet_intrs_ack(enet);\n+\n+\tnapi_schedule(&enet->napi);\n+\n+\treturn IRQ_HANDLED;\n+}\n+\n+static int bcm4908enet_open(struct net_device *netdev)\n+{\n+\tstruct bcm4908enet *enet = netdev_priv(netdev);\n+\tstruct device *dev = enet->dev;\n+\tint err;\n+\n+\terr = request_irq(netdev->irq, bcm4908enet_irq_handler, 0, \"enet\", enet);\n+\tif (err) {\n+\t\tdev_err(dev, \"Failed to request IRQ %d: %d\\n\", netdev->irq, err);\n+\t\treturn err;\n+\t}\n+\n+\tbcm4908enet_gmac_init(enet);\n+\tbcm4908enet_dma_reset(enet);\n+\tbcm4908enet_dma_init(enet);\n+\n+\tenet_umac_set(enet, UMAC_CMD, CMD_TX_EN | CMD_RX_EN);\n+\n+\tenet_set(enet, ENET_DMA_CONTROLLER_CFG, ENET_DMA_CTRL_CFG_MASTER_EN);\n+\tenet_maskset(enet, ENET_DMA_CONTROLLER_CFG, ENET_DMA_CTRL_CFG_FLOWC_CH1_EN, 0);\n+\tbcm4908enet_dma_rx_ring_enable(enet, &enet->rx_ring);\n+\n+\tnapi_enable(&enet->napi);\n+\tnetif_carrier_on(netdev);\n+\tnetif_start_queue(netdev);\n+\n+\tbcm4908enet_intrs_ack(enet);\n+\tbcm4908enet_intrs_on(enet);\n+\n+\treturn 0;\n+}\n+\n+static int bcm4908enet_stop(struct net_device *netdev)\n+{\n+\tstruct bcm4908enet *enet = netdev_priv(netdev);\n+\n+\tnetif_stop_queue(netdev);\n+\tnetif_carrier_off(netdev);\n+\tnapi_disable(&enet->napi);\n+\n+\tbcm4908enet_dma_rx_ring_disable(enet, &enet->rx_ring);\n+\tbcm4908enet_dma_tx_ring_disable(enet, &enet->tx_ring);\n+\n+\tbcm4908enet_dma_uninit(enet);\n+\n+\tfree_irq(enet->netdev->irq, enet);\n+\n+\treturn 0;\n+}\n+\n+static int bcm4908enet_start_xmit(struct sk_buff *skb, struct net_device *netdev)\n+{\n+\tstruct bcm4908enet *enet = netdev_priv(netdev);\n+\tstruct bcm4908enet_dma_ring *ring = &enet->tx_ring;\n+\tstruct bcm4908enet_dma_ring_slot *slot;\n+\tstruct device *dev = enet->dev;\n+\tstruct bcm4908enet_dma_ring_bd *buf_desc;\n+\tint free_buf_descs;\n+\tu32 tmp;\n+\n+\t/* Free transmitted skbs */\n+\twhile (ring->read_idx != ring->write_idx) {\n+\t\tbuf_desc = &ring->buf_desc[ring->read_idx];\n+\t\tif (buf_desc->ctl & DMA_CTL_STATUS_OWN)\n+\t\t\tbreak;\n+\t\tslot = &ring->slots[ring->read_idx];\n+\n+\t\tdma_unmap_single(dev, slot->dma_addr, slot->len, DMA_TO_DEVICE);\n+\t\tdev_kfree_skb(slot->skb);\n+\t\tif (++ring->read_idx == ring->length)\n+\t\t\tring->read_idx = 0;\n+\t}\n+\n+\t/* Don't use the last empty buf descriptor */\n+\tif (ring->read_idx <= ring->write_idx)\n+\t\tfree_buf_descs = ring->read_idx - ring->write_idx + ring->length;\n+\telse\n+\t\tfree_buf_descs = ring->read_idx - ring->write_idx;\n+\tif (free_buf_descs < 2)\n+\t\treturn NETDEV_TX_BUSY;\n+\n+\t/* Hardware removes OWN bit after sending data */\n+\tbuf_desc = &ring->buf_desc[ring->write_idx];\n+\tif (unlikely(le32_to_cpu(buf_desc->ctl) & DMA_CTL_STATUS_OWN)) {\n+\t\tnetif_stop_queue(netdev);\n+\t\treturn NETDEV_TX_BUSY;\n+\t}\n+\n+\tslot = &ring->slots[ring->write_idx];\n+\tslot->skb = skb;\n+\tslot->len = skb->len;\n+\tslot->dma_addr = dma_map_single(dev, skb->data, skb->len, DMA_TO_DEVICE);\n+\tif (unlikely(dma_mapping_error(dev, slot->dma_addr)))\n+\t\treturn NETDEV_TX_BUSY;\n+\n+\ttmp = skb->len << DMA_CTL_LEN_DESC_BUFLENGTH_SHIFT;\n+\ttmp |= DMA_CTL_STATUS_OWN;\n+\ttmp |= DMA_CTL_STATUS_SOP;\n+\ttmp |= DMA_CTL_STATUS_EOP;\n+\ttmp |= DMA_CTL_STATUS_APPEND_CRC;\n+\tif (ring->write_idx + 1 == ring->length - 1)\n+\t\ttmp |= DMA_CTL_STATUS_WRAP;\n+\n+\tbuf_desc->addr = cpu_to_le32((uint32_t)slot->dma_addr);\n+\tbuf_desc->ctl = cpu_to_le32(tmp);\n+\n+\tbcm4908enet_dma_tx_ring_ensable(enet, &enet->tx_ring);\n+\n+\tif (++ring->write_idx == ring->length - 1)\n+\t\tring->write_idx = 0;\n+\tenet->netdev->stats.tx_bytes += skb->len;\n+\tenet->netdev->stats.tx_packets++;\n+\n+\treturn NETDEV_TX_OK;\n+}\n+\n+static int bcm4908enet_poll(struct napi_struct *napi, int weight)\n+{\n+\tstruct bcm4908enet *enet = container_of(napi, struct bcm4908enet, napi);\n+\tstruct device *dev = enet->dev;\n+\tint handled = 0;\n+\n+\twhile (handled < weight) {\n+\t\tstruct bcm4908enet_dma_ring_bd *buf_desc;\n+\t\tstruct bcm4908enet_dma_ring_slot slot;\n+\t\tu32 ctl;\n+\t\tint len;\n+\t\tint err;\n+\n+\t\tbuf_desc = &enet->rx_ring.buf_desc[enet->rx_ring.read_idx];\n+\t\tctl = le32_to_cpu(buf_desc->ctl);\n+\t\tif (ctl & DMA_CTL_STATUS_OWN)\n+\t\t\tbreak;\n+\n+\t\tslot = enet->rx_ring.slots[enet->rx_ring.read_idx];\n+\n+\t\t/* Provide new buffer before unpinning the old one */\n+\t\terr = bcm4908enet_dma_alloc_rx_buf(enet, enet->rx_ring.read_idx);\n+\t\tif (err)\n+\t\t\tbreak;\n+\n+\t\tif (++enet->rx_ring.read_idx == enet->rx_ring.length)\n+\t\t\tenet->rx_ring.read_idx = 0;\n+\n+\t\tlen = (ctl & DMA_CTL_LEN_DESC_BUFLENGTH) >> DMA_CTL_LEN_DESC_BUFLENGTH_SHIFT;\n+\n+\t\tif (len < ENET_MTU_MIN ||\n+\t\t    (ctl & (DMA_CTL_STATUS_SOP | DMA_CTL_STATUS_EOP)) != (DMA_CTL_STATUS_SOP | DMA_CTL_STATUS_EOP)) {\n+\t\t\tenet->netdev->stats.rx_dropped++;\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\tdma_unmap_single(dev, slot.dma_addr, slot.len, DMA_FROM_DEVICE);\n+\n+\t\tskb_put(slot.skb, len - 4 + 2);\n+\t\tslot.skb->protocol = eth_type_trans(slot.skb, enet->netdev);\n+\t\tnetif_receive_skb(slot.skb);\n+\n+\t\tenet->netdev->stats.rx_packets++;\n+\t\tenet->netdev->stats.rx_bytes += len;\n+\t}\n+\n+\tif (handled < weight) {\n+\t\tnapi_complete_done(napi, handled);\n+\t\tbcm4908enet_intrs_on(enet);\n+\t}\n+\n+\treturn handled;\n+}\n+\n+static const struct net_device_ops bcm96xx_netdev_ops = {\n+\t.ndo_open = bcm4908enet_open,\n+\t.ndo_stop = bcm4908enet_stop,\n+\t.ndo_start_xmit = bcm4908enet_start_xmit,\n+\t.ndo_set_mac_address = eth_mac_addr,\n+};\n+\n+static int bcm4908enet_probe(struct platform_device *pdev)\n+{\n+\tstruct device *dev = &pdev->dev;\n+\tstruct net_device *netdev;\n+\tstruct bcm4908enet *enet;\n+\tint err;\n+\n+\tnetdev = devm_alloc_etherdev(dev, sizeof(*enet));\n+\tif (!netdev)\n+\t\treturn -ENOMEM;\n+\n+\tenet = netdev_priv(netdev);\n+\tenet->dev = dev;\n+\tenet->netdev = netdev;\n+\n+\tenet->base = devm_platform_ioremap_resource(pdev, 0);\n+\tif (IS_ERR(enet->base)) {\n+\t\tdev_err(dev, \"Failed to map registers: %ld\\n\", PTR_ERR(enet->base));\n+\t\treturn PTR_ERR(enet->base);\n+\t}\n+\n+\tnetdev->irq = platform_get_irq_byname(pdev, \"rx\");\n+\tif (netdev->irq < 0)\n+\t\treturn netdev->irq;\n+\n+\tdma_set_coherent_mask(dev, DMA_BIT_MASK(32));\n+\n+\terr = bcm4908enet_dma_alloc(enet);\n+\tif (err)\n+\t\treturn err;\n+\n+\tSET_NETDEV_DEV(netdev, &pdev->dev);\n+\teth_hw_addr_random(netdev);\n+\tnetdev->netdev_ops = &bcm96xx_netdev_ops;\n+\tnetdev->min_mtu = ETH_ZLEN;\n+\tnetdev->mtu = ENET_MTU_MAX;\n+\tnetdev->max_mtu = ENET_MTU_MAX;\n+\tnetif_napi_add(netdev, &enet->napi, bcm4908enet_poll, 64);\n+\n+\terr = register_netdev(netdev);\n+\tif (err) {\n+\t\tbcm4908enet_dma_free(enet);\n+\t\treturn err;\n+\t}\n+\n+\tplatform_set_drvdata(pdev, enet);\n+\n+\treturn 0;\n+}\n+\n+static int bcm4908enet_remove(struct platform_device *pdev)\n+{\n+\tstruct bcm4908enet *enet = platform_get_drvdata(pdev);\n+\n+\tunregister_netdev(enet->netdev);\n+\tnetif_napi_del(&enet->napi);\n+\tbcm4908enet_dma_free(enet);\n+\n+\treturn 0;\n+}\n+\n+static const struct of_device_id bcm4908enet_of_match[] = {\n+\t{ .compatible = \"brcm,bcm4908enet\"},\n+\t{},\n+};\n+\n+static struct platform_driver bcm4908enet_driver = {\n+\t.driver = {\n+\t\t.name = \"bcm4908enet\",\n+\t\t.of_match_table = bcm4908enet_of_match,\n+\t},\n+\t.probe\t= bcm4908enet_probe,\n+\t.remove = bcm4908enet_remove,\n+};\n+module_platform_driver(bcm4908enet_driver);\n+\n+MODULE_LICENSE(\"GPL v2\");\n+MODULE_DEVICE_TABLE(of, bcm4908enet_of_match);\n--- /dev/null\n+++ b/drivers/net/ethernet/broadcom/bcm4908enet.h\n@@ -0,0 +1,96 @@\n+/* SPDX-License-Identifier: GPL-2.0-only */\n+#ifndef __BCM4908ENET_H\n+#define __BCM4908ENET_H\n+\n+#define ENET_CONTROL\t\t\t\t\t0x000\n+#define ENET_MIB_CTRL\t\t\t\t\t0x004\n+#define  ENET_MIB_CTRL_CLR_MIB\t\t\t\t0x00000001\n+#define ENET_RX_ERR_MASK\t\t\t\t0x008\n+#define ENET_MIB_MAX_PKT_SIZE\t\t\t\t0x00C\n+#define  ENET_MIB_MAX_PKT_SIZE_VAL\t\t\t0x00003fff\n+#define ENET_DIAG_OUT\t\t\t\t\t0x01c\n+#define ENET_ENABLE_DROP_PKT\t\t\t\t0x020\n+#define ENET_IRQ_ENABLE\t\t\t\t\t0x024\n+#define  ENET_IRQ_ENABLE_OVFL\t\t\t\t0x00000001\n+#define ENET_GMAC_STATUS\t\t\t\t0x028\n+#define  ENET_GMAC_STATUS_ETH_SPEED_MASK\t\t0x00000003\n+#define  ENET_GMAC_STATUS_ETH_SPEED_10\t\t\t0x00000000\n+#define  ENET_GMAC_STATUS_ETH_SPEED_100\t\t\t0x00000001\n+#define  ENET_GMAC_STATUS_ETH_SPEED_1000\t\t0x00000002\n+#define  ENET_GMAC_STATUS_HD\t\t\t\t0x00000004\n+#define  ENET_GMAC_STATUS_AUTO_CFG_EN\t\t\t0x00000008\n+#define  ENET_GMAC_STATUS_LINK_UP\t\t\t0x00000010\n+#define ENET_IRQ_STATUS\t\t\t\t\t0x02c\n+#define  ENET_IRQ_STATUS_OVFL\t\t\t\t0x00000001\n+#define ENET_OVERFLOW_COUNTER\t\t\t\t0x030\n+#define ENET_FLUSH\t\t\t\t\t0x034\n+#define  ENET_FLUSH_RXFIFO_FLUSH\t\t\t0x00000001\n+#define  ENET_FLUSH_TXFIFO_FLUSH\t\t\t0x00000002\n+#define ENET_RSV_SELECT\t\t\t\t\t0x038\n+#define ENET_BP_FORCE\t\t\t\t\t0x03c\n+#define  ENET_BP_FORCE_FORCE\t\t\t\t0x00000001\n+#define ENET_DMA_RX_OK_TO_SEND_COUNT\t\t\t0x040\n+#define  ENET_DMA_RX_OK_TO_SEND_COUNT_VAL\t\t0x0000000f\n+#define ENET_TX_CRC_CTRL\t\t\t\t0x044\n+#define ENET_MIB\t\t\t\t\t0x200\n+#define ENET_UNIMAC\t\t\t\t\t0x400\n+#define ENET_DMA\t\t\t\t\t0x800\n+#define ENET_DMA_CONTROLLER_CFG\t\t\t\t0x800\n+#define  ENET_DMA_CTRL_CFG_MASTER_EN\t\t\t0x00000001\n+#define  ENET_DMA_CTRL_CFG_FLOWC_CH1_EN\t\t\t0x00000002\n+#define  ENET_DMA_CTRL_CFG_FLOWC_CH3_EN\t\t\t0x00000004\n+#define ENET_DMA_FLOWCTL_CH1_THRESH_LO\t\t\t0x804\n+#define ENET_DMA_FLOWCTL_CH1_THRESH_HI\t\t\t0x808\n+#define ENET_DMA_FLOWCTL_CH1_ALLOC\t\t\t0x80c\n+#define  ENET_DMA_FLOWCTL_CH1_ALLOC_FORCE\t\t0x80000000\n+#define ENET_DMA_FLOWCTL_CH3_THRESH_LO\t\t\t0x810\n+#define ENET_DMA_FLOWCTL_CH3_THRESH_HI\t\t\t0x814\n+#define ENET_DMA_FLOWCTL_CH3_ALLOC\t\t\t0x818\n+#define ENET_DMA_FLOWCTL_CH5_THRESH_LO\t\t\t0x81C\n+#define ENET_DMA_FLOWCTL_CH5_THRESH_HI\t\t\t0x820\n+#define ENET_DMA_FLOWCTL_CH5_ALLOC\t\t\t0x824\n+#define ENET_DMA_FLOWCTL_CH7_THRESH_LO\t\t\t0x828\n+#define ENET_DMA_FLOWCTL_CH7_THRESH_HI\t\t\t0x82C\n+#define ENET_DMA_FLOWCTL_CH7_ALLOC\t\t\t0x830\n+#define ENET_DMA_CTRL_CHANNEL_RESET\t\t\t0x834\n+#define ENET_DMA_CTRL_CHANNEL_DEBUG\t\t\t0x838\n+#define ENET_DMA_CTRL_GLOBAL_INTERRUPT_STATUS\t\t0x840\n+#define ENET_DMA_CTRL_GLOBAL_INTERRUPT_MASK\t\t0x844\n+#define ENET_DMA_CH0_CFG\t\t\t\t0xa00\t\t/* RX */\n+#define ENET_DMA_CH1_CFG\t\t\t\t0xa10\t\t/* TX */\n+#define ENET_DMA_CH0_STATE_RAM\t\t\t\t0xc00\t\t/* RX */\n+#define ENET_DMA_CH1_STATE_RAM\t\t\t\t0xc10\t\t/* TX */\n+\n+#define ENET_DMA_CH_CFG\t\t\t\t\t0x00\t\t/* assorted configuration */\n+#define  ENET_DMA_CH_CFG_ENABLE\t\t\t\t0x00000001\t/* set to enable channel */\n+#define  ENET_DMA_CH_CFG_PKT_HALT\t\t\t0x00000002\t/* idle after an EOP flag is detected */\n+#define  ENET_DMA_CH_CFG_BURST_HALT\t\t\t0x00000004\t/* idle after finish current memory burst */\n+#define ENET_DMA_CH_CFG_INT_STAT\t\t\t0x04\t\t/* interrupts control and status */\n+#define ENET_DMA_CH_CFG_INT_MASK\t\t\t0x08\t\t/* interrupts mask */\n+#define  ENET_DMA_CH_CFG_INT_BUFF_DONE\t\t\t0x00000001\t/* buffer done */\n+#define  ENET_DMA_CH_CFG_INT_DONE\t\t\t0x00000002\t/* packet xfer complete */\n+#define  ENET_DMA_CH_CFG_INT_NO_DESC\t\t\t0x00000004\t/* no valid descriptors */\n+#define  ENET_DMA_CH_CFG_INT_RX_ERROR\t\t\t0x00000008\t/* rxdma detect client protocol error */\n+#define ENET_DMA_CH_CFG_MAX_BURST\t\t\t0x0c\t\t/* max burst length permitted */\n+#define  ENET_DMA_CH_CFG_MAX_BURST_DESCSIZE_SEL\t\t0x00040000\t/* DMA Descriptor Size Selection */\n+#define ENET_DMA_CH_CFG_SIZE\t\t\t\t0x10\n+\n+#define ENET_DMA_CH_STATE_RAM_BASE_DESC_PTR\t\t0x00\t\t/* descriptor ring start address */\n+#define ENET_DMA_CH_STATE_RAM_STATE_DATA\t\t0x04\t\t/* state/bytes done/ring offset */\n+#define ENET_DMA_CH_STATE_RAM_DESC_LEN_STATUS\t\t0x08\t\t/* buffer descriptor status and len */\n+#define ENET_DMA_CH_STATE_RAM_DESC_BASE_BUFPTR\t\t0x0c\t\t/* buffer descrpitor current processing */\n+#define ENET_DMA_CH_STATE_RAM_SIZE\t\t\t0x10\n+\n+#define DMA_CTL_STATUS_APPEND_CRC\t\t\t0x00000100\n+#define DMA_CTL_STATUS_APPEND_BRCM_TAG\t\t\t0x00000200\n+#define DMA_CTL_STATUS_PRIO\t\t\t\t0x00000C00  /* Prio for Tx */\n+#define DMA_CTL_STATUS_WRAP\t\t\t\t0x00001000  /* */\n+#define DMA_CTL_STATUS_SOP\t\t\t\t0x00002000  /* first buffer in packet */\n+#define DMA_CTL_STATUS_EOP\t\t\t\t0x00004000  /* last buffer in packet */\n+#define DMA_CTL_STATUS_OWN\t\t\t\t0x00008000  /* cleared by DMA, set by SW */\n+#define DMA_CTL_LEN_DESC_BUFLENGTH\t\t\t0x0fff0000\n+#define DMA_CTL_LEN_DESC_BUFLENGTH_SHIFT\t\t16\n+#define DMA_CTL_LEN_DESC_MULTICAST\t\t\t0x40000000\n+#define DMA_CTL_LEN_DESC_USEFPM\t\t\t\t0x80000000\n+\n+#endif\n"
  },
  {
    "path": "target/linux/bcm4908/patches-5.10/073-v5.12-0001-dt-bindings-net-rename-BCM4908-Ethernet-binding.patch",
    "content": "From 6710c5b0674f8811f7d8fbfc526684e7ed77f765 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Thu, 11 Feb 2021 13:12:32 +0100\nSubject: [PATCH] dt-bindings: net: rename BCM4908 Ethernet binding\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nRob pointed out that a normal convention is \"brcm,bcm4908-enet\" so\nupdate whole binding to match it.\n\nSuggested-by: Rob Herring <robh@kernel.org>\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nReviewed-by: Florian Fainelli <f.fainelli@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n .../net/{brcm,bcm4908enet.yaml => brcm,bcm4908-enet.yaml}   | 6 +++---\n MAINTAINERS                                                 | 2 +-\n 2 files changed, 4 insertions(+), 4 deletions(-)\n rename Documentation/devicetree/bindings/net/{brcm,bcm4908enet.yaml => brcm,bcm4908-enet.yaml} (85%)\n\n--- a/Documentation/devicetree/bindings/net/brcm,bcm4908enet.yaml\n+++ /dev/null\n@@ -1,45 +0,0 @@\n-# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause\n-%YAML 1.2\n----\n-$id: http://devicetree.org/schemas/net/brcm,bcm4908enet.yaml#\n-$schema: http://devicetree.org/meta-schemas/core.yaml#\n-\n-title: Broadcom BCM4908 Ethernet controller\n-\n-description: Broadcom's Ethernet controller integrated into BCM4908 family SoCs\n-\n-maintainers:\n-  - Rafał Miłecki <rafal@milecki.pl>\n-\n-properties:\n-  compatible:\n-    const: brcm,bcm4908enet\n-\n-  reg:\n-    maxItems: 1\n-\n-  interrupts:\n-    description: RX interrupt\n-\n-  interrupt-names:\n-    const: rx\n-\n-required:\n-  - reg\n-  - interrupts\n-  - interrupt-names\n-\n-additionalProperties: false\n-\n-examples:\n-  - |\n-    #include <dt-bindings/interrupt-controller/irq.h>\n-    #include <dt-bindings/interrupt-controller/arm-gic.h>\n-\n-    ethernet@80002000 {\n-        compatible = \"brcm,bcm4908enet\";\n-        reg = <0x80002000 0x1000>;\n-\n-        interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;\n-        interrupt-names = \"rx\";\n-    };\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/net/brcm,bcm4908-enet.yaml\n@@ -0,0 +1,45 @@\n+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause\n+%YAML 1.2\n+---\n+$id: http://devicetree.org/schemas/net/brcm,bcm4908-enet.yaml#\n+$schema: http://devicetree.org/meta-schemas/core.yaml#\n+\n+title: Broadcom BCM4908 Ethernet controller\n+\n+description: Broadcom's Ethernet controller integrated into BCM4908 family SoCs\n+\n+maintainers:\n+  - Rafał Miłecki <rafal@milecki.pl>\n+\n+properties:\n+  compatible:\n+    const: brcm,bcm4908-enet\n+\n+  reg:\n+    maxItems: 1\n+\n+  interrupts:\n+    description: RX interrupt\n+\n+  interrupt-names:\n+    const: rx\n+\n+required:\n+  - reg\n+  - interrupts\n+  - interrupt-names\n+\n+additionalProperties: false\n+\n+examples:\n+  - |\n+    #include <dt-bindings/interrupt-controller/irq.h>\n+    #include <dt-bindings/interrupt-controller/arm-gic.h>\n+\n+    ethernet@80002000 {\n+        compatible = \"brcm,bcm4908-enet\";\n+        reg = <0x80002000 0x1000>;\n+\n+        interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;\n+        interrupt-names = \"rx\";\n+    };\n--- a/MAINTAINERS\n+++ b/MAINTAINERS\n@@ -3432,7 +3432,7 @@ M:\tRafał Miłecki <rafal@milecki.pl>\n M:\tbcm-kernel-feedback-list@broadcom.com\n L:\tnetdev@vger.kernel.org\n S:\tMaintained\n-F:\tDocumentation/devicetree/bindings/net/brcm,bcm4908enet.yaml\n+F:\tDocumentation/devicetree/bindings/net/brcm,bcm4908-enet.yaml\n F:\tdrivers/net/ethernet/broadcom/bcm4908enet.*\n F:\tdrivers/net/ethernet/broadcom/unimac.h\n \n"
  },
  {
    "path": "target/linux/bcm4908/patches-5.10/073-v5.12-0002-dt-bindings-net-bcm4908-enet-include-ethernet-contro.patch",
    "content": "From f08b5cf1eb1f2aefc6fe4a89c8c757ba94721d0b Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Thu, 11 Feb 2021 13:12:33 +0100\nSubject: [PATCH] dt-bindings: net: bcm4908-enet: include\n ethernet-controller.yaml\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nIt should be /included/ by every Ethernet controller binding. It adds\nsupport for various generic properties.\n\nSuggested-by: Rob Herring <robh@kernel.org>\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nReviewed-by: Florian Fainelli <f.fainelli@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n Documentation/devicetree/bindings/net/brcm,bcm4908-enet.yaml | 3 +++\n 1 file changed, 3 insertions(+)\n\n--- a/Documentation/devicetree/bindings/net/brcm,bcm4908-enet.yaml\n+++ b/Documentation/devicetree/bindings/net/brcm,bcm4908-enet.yaml\n@@ -11,6 +11,9 @@ description: Broadcom's Ethernet control\n maintainers:\n   - Rafał Miłecki <rafal@milecki.pl>\n \n+allOf:\n+  - $ref: ethernet-controller.yaml#\n+\n properties:\n   compatible:\n     const: brcm,bcm4908-enet\n"
  },
  {
    "path": "target/linux/bcm4908/patches-5.10/073-v5.12-0003-net-broadcom-rename-BCM4908-driver-update-DT-binding.patch",
    "content": "From 9d61d138ab30bbfe4a8609853c81e881c4054a0b Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Thu, 11 Feb 2021 13:12:34 +0100\nSubject: [PATCH] net: broadcom: rename BCM4908 driver & update DT binding\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\ncompatible string was updated to match normal naming convention so\nupdate driver as well\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nReviewed-by: Florian Fainelli <f.fainelli@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n MAINTAINERS                                   |   2 +-\n drivers/net/ethernet/broadcom/Kconfig         |   2 +-\n drivers/net/ethernet/broadcom/Makefile        |   2 +-\n .../{bcm4908enet.c => bcm4908_enet.c}         | 215 +++++++++---------\n .../{bcm4908enet.h => bcm4908_enet.h}         |   4 +-\n 5 files changed, 113 insertions(+), 112 deletions(-)\n rename drivers/net/ethernet/broadcom/{bcm4908enet.c => bcm4908_enet.c} (68%)\n rename drivers/net/ethernet/broadcom/{bcm4908enet.h => bcm4908_enet.h} (98%)\n\n--- a/MAINTAINERS\n+++ b/MAINTAINERS\n@@ -3433,7 +3433,7 @@ M:\tbcm-kernel-feedback-list@broadcom.com\n L:\tnetdev@vger.kernel.org\n S:\tMaintained\n F:\tDocumentation/devicetree/bindings/net/brcm,bcm4908-enet.yaml\n-F:\tdrivers/net/ethernet/broadcom/bcm4908enet.*\n+F:\tdrivers/net/ethernet/broadcom/bcm4908_enet.*\n F:\tdrivers/net/ethernet/broadcom/unimac.h\n \n BROADCOM BCM5301X ARM ARCHITECTURE\n--- a/drivers/net/ethernet/broadcom/Kconfig\n+++ b/drivers/net/ethernet/broadcom/Kconfig\n@@ -51,7 +51,7 @@ config B44_PCI\n \tdepends on B44_PCI_AUTOSELECT && B44_PCICORE_AUTOSELECT\n \tdefault y\n \n-config BCM4908ENET\n+config BCM4908_ENET\n \ttristate \"Broadcom BCM4908 internal mac support\"\n \tdepends on ARCH_BCM4908 || COMPILE_TEST\n \tdefault y\n--- a/drivers/net/ethernet/broadcom/Makefile\n+++ b/drivers/net/ethernet/broadcom/Makefile\n@@ -4,7 +4,7 @@\n #\n \n obj-$(CONFIG_B44) += b44.o\n-obj-$(CONFIG_BCM4908ENET) += bcm4908enet.o\n+obj-$(CONFIG_BCM4908_ENET) += bcm4908_enet.o\n obj-$(CONFIG_BCM63XX_ENET) += bcm63xx_enet.o\n obj-$(CONFIG_BCMGENET) += genet/\n obj-$(CONFIG_BNX2) += bnx2.o\n--- a/drivers/net/ethernet/broadcom/bcm4908enet.c\n+++ /dev/null\n@@ -1,676 +0,0 @@\n-// SPDX-License-Identifier: GPL-2.0-only\n-/*\n- * Copyright (C) 2021 Rafał Miłecki <rafal@milecki.pl>\n- */\n-\n-#include <linux/delay.h>\n-#include <linux/etherdevice.h>\n-#include <linux/interrupt.h>\n-#include <linux/module.h>\n-#include <linux/of.h>\n-#include <linux/platform_device.h>\n-#include <linux/slab.h>\n-#include <linux/string.h>\n-\n-#include \"bcm4908enet.h\"\n-#include \"unimac.h\"\n-\n-#define ENET_DMA_CH_RX_CFG\t\t\tENET_DMA_CH0_CFG\n-#define ENET_DMA_CH_TX_CFG\t\t\tENET_DMA_CH1_CFG\n-#define ENET_DMA_CH_RX_STATE_RAM\t\tENET_DMA_CH0_STATE_RAM\n-#define ENET_DMA_CH_TX_STATE_RAM\t\tENET_DMA_CH1_STATE_RAM\n-\n-#define ENET_TX_BDS_NUM\t\t\t\t200\n-#define ENET_RX_BDS_NUM\t\t\t\t200\n-#define ENET_RX_BDS_NUM_MAX\t\t\t8192\n-\n-#define ENET_DMA_INT_DEFAULTS\t\t\t(ENET_DMA_CH_CFG_INT_DONE | \\\n-\t\t\t\t\t\t ENET_DMA_CH_CFG_INT_NO_DESC | \\\n-\t\t\t\t\t\t ENET_DMA_CH_CFG_INT_BUFF_DONE)\n-#define ENET_DMA_MAX_BURST_LEN\t\t\t8 /* in 64 bit words */\n-\n-#define ENET_MTU_MIN\t\t\t\t60\n-#define ENET_MTU_MAX\t\t\t\t1500 /* Is it possible to support 2044? */\n-#define ENET_MTU_MAX_EXTRA_SIZE\t\t\t32 /* L2 */\n-\n-struct bcm4908enet_dma_ring_bd {\n-\t__le32 ctl;\n-\t__le32 addr;\n-} __packed;\n-\n-struct bcm4908enet_dma_ring_slot {\n-\tstruct sk_buff *skb;\n-\tunsigned int len;\n-\tdma_addr_t dma_addr;\n-};\n-\n-struct bcm4908enet_dma_ring {\n-\tint is_tx;\n-\tint read_idx;\n-\tint write_idx;\n-\tint length;\n-\tu16 cfg_block;\n-\tu16 st_ram_block;\n-\n-\tunion {\n-\t\tvoid *cpu_addr;\n-\t\tstruct bcm4908enet_dma_ring_bd *buf_desc;\n-\t};\n-\tdma_addr_t dma_addr;\n-\n-\tstruct bcm4908enet_dma_ring_slot *slots;\n-};\n-\n-struct bcm4908enet {\n-\tstruct device *dev;\n-\tstruct net_device *netdev;\n-\tstruct napi_struct napi;\n-\tvoid __iomem *base;\n-\n-\tstruct bcm4908enet_dma_ring tx_ring;\n-\tstruct bcm4908enet_dma_ring rx_ring;\n-};\n-\n-/***\n- * R/W ops\n- */\n-\n-static inline u32 enet_read(struct bcm4908enet *enet, u16 offset)\n-{\n-\treturn readl(enet->base + offset);\n-}\n-\n-static inline void enet_write(struct bcm4908enet *enet, u16 offset, u32 value)\n-{\n-\twritel(value, enet->base + offset);\n-}\n-\n-static inline void enet_maskset(struct bcm4908enet *enet, u16 offset, u32 mask, u32 set)\n-{\n-\tu32 val;\n-\n-\tWARN_ON(set & ~mask);\n-\n-\tval = enet_read(enet, offset);\n-\tval = (val & ~mask) | (set & mask);\n-\tenet_write(enet, offset, val);\n-}\n-\n-static inline void enet_set(struct bcm4908enet *enet, u16 offset, u32 set)\n-{\n-\tenet_maskset(enet, offset, set, set);\n-}\n-\n-static inline u32 enet_umac_read(struct bcm4908enet *enet, u16 offset)\n-{\n-\treturn enet_read(enet, ENET_UNIMAC + offset);\n-}\n-\n-static inline void enet_umac_write(struct bcm4908enet *enet, u16 offset, u32 value)\n-{\n-\tenet_write(enet, ENET_UNIMAC + offset, value);\n-}\n-\n-static inline void enet_umac_maskset(struct bcm4908enet *enet, u16 offset, u32 mask, u32 set)\n-{\n-\tenet_maskset(enet, ENET_UNIMAC + offset, mask, set);\n-}\n-\n-static inline void enet_umac_set(struct bcm4908enet *enet, u16 offset, u32 set)\n-{\n-\tenet_set(enet, ENET_UNIMAC + offset, set);\n-}\n-\n-/***\n- * Helpers\n- */\n-\n-static void bcm4908enet_intrs_on(struct bcm4908enet *enet)\n-{\n-\tenet_write(enet, ENET_DMA_CH_RX_CFG + ENET_DMA_CH_CFG_INT_MASK, ENET_DMA_INT_DEFAULTS);\n-}\n-\n-static void bcm4908enet_intrs_off(struct bcm4908enet *enet)\n-{\n-\tenet_write(enet, ENET_DMA_CH_RX_CFG + ENET_DMA_CH_CFG_INT_MASK, 0);\n-}\n-\n-static void bcm4908enet_intrs_ack(struct bcm4908enet *enet)\n-{\n-\tenet_write(enet, ENET_DMA_CH_RX_CFG + ENET_DMA_CH_CFG_INT_STAT, ENET_DMA_INT_DEFAULTS);\n-}\n-\n-/***\n- * DMA\n- */\n-\n-static int bcm4908_dma_alloc_buf_descs(struct bcm4908enet *enet, struct bcm4908enet_dma_ring *ring)\n-{\n-\tint size = ring->length * sizeof(struct bcm4908enet_dma_ring_bd);\n-\tstruct device *dev = enet->dev;\n-\n-\tring->cpu_addr = dma_alloc_coherent(dev, size, &ring->dma_addr, GFP_KERNEL);\n-\tif (!ring->cpu_addr)\n-\t\treturn -ENOMEM;\n-\n-\tif (((uintptr_t)ring->cpu_addr) & (0x40 - 1)) {\n-\t\tdev_err(dev, \"Invalid DMA ring alignment\\n\");\n-\t\tgoto err_free_buf_descs;\n-\t}\n-\n-\tring->slots = kzalloc(ring->length * sizeof(*ring->slots), GFP_KERNEL);\n-\tif (!ring->slots)\n-\t\tgoto err_free_buf_descs;\n-\n-\tmemset(ring->cpu_addr, 0, size);\n-\n-\tring->read_idx = 0;\n-\tring->write_idx = 0;\n-\n-\treturn 0;\n-\n-err_free_buf_descs:\n-\tdma_free_coherent(dev, size, ring->cpu_addr, ring->dma_addr);\n-\treturn -ENOMEM;\n-}\n-\n-static void bcm4908enet_dma_free(struct bcm4908enet *enet)\n-{\n-\tstruct bcm4908enet_dma_ring *tx_ring = &enet->tx_ring;\n-\tstruct bcm4908enet_dma_ring *rx_ring = &enet->rx_ring;\n-\tstruct device *dev = enet->dev;\n-\tint size;\n-\n-\tsize = rx_ring->length * sizeof(struct bcm4908enet_dma_ring_bd);\n-\tif (rx_ring->cpu_addr)\n-\t\tdma_free_coherent(dev, size, rx_ring->cpu_addr, rx_ring->dma_addr);\n-\tkfree(rx_ring->slots);\n-\n-\tsize = tx_ring->length * sizeof(struct bcm4908enet_dma_ring_bd);\n-\tif (tx_ring->cpu_addr)\n-\t\tdma_free_coherent(dev, size, tx_ring->cpu_addr, tx_ring->dma_addr);\n-\tkfree(tx_ring->slots);\n-}\n-\n-static int bcm4908enet_dma_alloc(struct bcm4908enet *enet)\n-{\n-\tstruct bcm4908enet_dma_ring *tx_ring = &enet->tx_ring;\n-\tstruct bcm4908enet_dma_ring *rx_ring = &enet->rx_ring;\n-\tstruct device *dev = enet->dev;\n-\tint err;\n-\n-\ttx_ring->length = ENET_TX_BDS_NUM;\n-\ttx_ring->is_tx = 1;\n-\ttx_ring->cfg_block = ENET_DMA_CH_TX_CFG;\n-\ttx_ring->st_ram_block = ENET_DMA_CH_TX_STATE_RAM;\n-\terr = bcm4908_dma_alloc_buf_descs(enet, tx_ring);\n-\tif (err) {\n-\t\tdev_err(dev, \"Failed to alloc TX buf descriptors: %d\\n\", err);\n-\t\treturn err;\n-\t}\n-\n-\trx_ring->length = ENET_RX_BDS_NUM;\n-\trx_ring->is_tx = 0;\n-\trx_ring->cfg_block = ENET_DMA_CH_RX_CFG;\n-\trx_ring->st_ram_block = ENET_DMA_CH_RX_STATE_RAM;\n-\terr = bcm4908_dma_alloc_buf_descs(enet, rx_ring);\n-\tif (err) {\n-\t\tdev_err(dev, \"Failed to alloc RX buf descriptors: %d\\n\", err);\n-\t\tbcm4908enet_dma_free(enet);\n-\t\treturn err;\n-\t}\n-\n-\treturn 0;\n-}\n-\n-static void bcm4908enet_dma_reset(struct bcm4908enet *enet)\n-{\n-\tstruct bcm4908enet_dma_ring *rings[] = { &enet->rx_ring, &enet->tx_ring };\n-\tint i;\n-\n-\t/* Disable the DMA controller and channel */\n-\tfor (i = 0; i < ARRAY_SIZE(rings); i++)\n-\t\tenet_write(enet, rings[i]->cfg_block + ENET_DMA_CH_CFG, 0);\n-\tenet_maskset(enet, ENET_DMA_CONTROLLER_CFG, ENET_DMA_CTRL_CFG_MASTER_EN, 0);\n-\n-\t/* Reset channels state */\n-\tfor (i = 0; i < ARRAY_SIZE(rings); i++) {\n-\t\tstruct bcm4908enet_dma_ring *ring = rings[i];\n-\n-\t\tenet_write(enet, ring->st_ram_block + ENET_DMA_CH_STATE_RAM_BASE_DESC_PTR, 0);\n-\t\tenet_write(enet, ring->st_ram_block + ENET_DMA_CH_STATE_RAM_STATE_DATA, 0);\n-\t\tenet_write(enet, ring->st_ram_block + ENET_DMA_CH_STATE_RAM_DESC_LEN_STATUS, 0);\n-\t\tenet_write(enet, ring->st_ram_block + ENET_DMA_CH_STATE_RAM_DESC_BASE_BUFPTR, 0);\n-\t}\n-}\n-\n-static int bcm4908enet_dma_alloc_rx_buf(struct bcm4908enet *enet, unsigned int idx)\n-{\n-\tstruct bcm4908enet_dma_ring_bd *buf_desc = &enet->rx_ring.buf_desc[idx];\n-\tstruct bcm4908enet_dma_ring_slot *slot = &enet->rx_ring.slots[idx];\n-\tstruct device *dev = enet->dev;\n-\tu32 tmp;\n-\tint err;\n-\n-\tslot->len = ENET_MTU_MAX + ENET_MTU_MAX_EXTRA_SIZE;\n-\n-\tslot->skb = netdev_alloc_skb(enet->netdev, slot->len);\n-\tif (!slot->skb)\n-\t\treturn -ENOMEM;\n-\n-\tslot->dma_addr = dma_map_single(dev, slot->skb->data, slot->len, DMA_FROM_DEVICE);\n-\terr = dma_mapping_error(dev, slot->dma_addr);\n-\tif (err) {\n-\t\tdev_err(dev, \"Failed to map DMA buffer: %d\\n\", err);\n-\t\tkfree_skb(slot->skb);\n-\t\tslot->skb = NULL;\n-\t\treturn err;\n-\t}\n-\n-\ttmp = slot->len << DMA_CTL_LEN_DESC_BUFLENGTH_SHIFT;\n-\ttmp |= DMA_CTL_STATUS_OWN;\n-\tif (idx == enet->rx_ring.length - 1)\n-\t\ttmp |= DMA_CTL_STATUS_WRAP;\n-\tbuf_desc->ctl = cpu_to_le32(tmp);\n-\tbuf_desc->addr = cpu_to_le32(slot->dma_addr);\n-\n-\treturn 0;\n-}\n-\n-static void bcm4908enet_dma_ring_init(struct bcm4908enet *enet,\n-\t\t\t\t      struct bcm4908enet_dma_ring *ring)\n-{\n-\tint reset_channel = 0; /* We support only 1 main channel (with TX and RX) */\n-\tint reset_subch = ring->is_tx ? 1 : 0;\n-\n-\t/* Reset the DMA channel */\n-\tenet_write(enet, ENET_DMA_CTRL_CHANNEL_RESET, BIT(reset_channel * 2 + reset_subch));\n-\tenet_write(enet, ENET_DMA_CTRL_CHANNEL_RESET, 0);\n-\n-\tenet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG, 0);\n-\tenet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG_MAX_BURST, ENET_DMA_MAX_BURST_LEN);\n-\tenet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG_INT_MASK, 0);\n-\n-\tenet_write(enet, ring->st_ram_block + ENET_DMA_CH_STATE_RAM_BASE_DESC_PTR,\n-\t\t   (uint32_t)ring->dma_addr);\n-}\n-\n-static void bcm4908enet_dma_uninit(struct bcm4908enet *enet)\n-{\n-\tstruct bcm4908enet_dma_ring *rx_ring = &enet->rx_ring;\n-\tstruct bcm4908enet_dma_ring_slot *slot;\n-\tstruct device *dev = enet->dev;\n-\tint i;\n-\n-\tfor (i = rx_ring->length - 1; i >= 0; i--) {\n-\t\tslot = &rx_ring->slots[i];\n-\t\tif (!slot->skb)\n-\t\t\tcontinue;\n-\t\tdma_unmap_single(dev, slot->dma_addr, slot->len, DMA_FROM_DEVICE);\n-\t\tkfree_skb(slot->skb);\n-\t\tslot->skb = NULL;\n-\t}\n-}\n-\n-static int bcm4908enet_dma_init(struct bcm4908enet *enet)\n-{\n-\tstruct bcm4908enet_dma_ring *rx_ring = &enet->rx_ring;\n-\tstruct device *dev = enet->dev;\n-\tint err;\n-\tint i;\n-\n-\tfor (i = 0; i < rx_ring->length; i++) {\n-\t\terr = bcm4908enet_dma_alloc_rx_buf(enet, i);\n-\t\tif (err) {\n-\t\t\tdev_err(dev, \"Failed to alloc RX buffer: %d\\n\", err);\n-\t\t\tbcm4908enet_dma_uninit(enet);\n-\t\t\treturn err;\n-\t\t}\n-\t}\n-\n-\tbcm4908enet_dma_ring_init(enet, &enet->tx_ring);\n-\tbcm4908enet_dma_ring_init(enet, &enet->rx_ring);\n-\n-\treturn 0;\n-}\n-\n-static void bcm4908enet_dma_tx_ring_ensable(struct bcm4908enet *enet,\n-\t\t\t\t\t    struct bcm4908enet_dma_ring *ring)\n-{\n-\tenet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG, ENET_DMA_CH_CFG_ENABLE);\n-}\n-\n-static void bcm4908enet_dma_tx_ring_disable(struct bcm4908enet *enet,\n-\t\t\t\t\t    struct bcm4908enet_dma_ring *ring)\n-{\n-\tenet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG, 0);\n-}\n-\n-static void bcm4908enet_dma_rx_ring_enable(struct bcm4908enet *enet,\n-\t\t\t\t\t   struct bcm4908enet_dma_ring *ring)\n-{\n-\tenet_set(enet, ring->cfg_block + ENET_DMA_CH_CFG, ENET_DMA_CH_CFG_ENABLE);\n-}\n-\n-static void bcm4908enet_dma_rx_ring_disable(struct bcm4908enet *enet,\n-\t\t\t\t\t    struct bcm4908enet_dma_ring *ring)\n-{\n-\tunsigned long deadline;\n-\tu32 tmp;\n-\n-\tenet_maskset(enet, ring->cfg_block + ENET_DMA_CH_CFG, ENET_DMA_CH_CFG_ENABLE, 0);\n-\n-\tdeadline = jiffies + usecs_to_jiffies(2000);\n-\tdo {\n-\t\ttmp = enet_read(enet, ring->cfg_block + ENET_DMA_CH_CFG);\n-\t\tif (!(tmp & ENET_DMA_CH_CFG_ENABLE))\n-\t\t\treturn;\n-\t\tenet_maskset(enet, ring->cfg_block + ENET_DMA_CH_CFG, ENET_DMA_CH_CFG_ENABLE, 0);\n-\t\tusleep_range(10, 30);\n-\t} while (!time_after_eq(jiffies, deadline));\n-\n-\tdev_warn(enet->dev, \"Timeout waiting for DMA TX stop\\n\");\n-}\n-\n-/***\n- * Ethernet driver\n- */\n-\n-static void bcm4908enet_gmac_init(struct bcm4908enet *enet)\n-{\n-\tu32 cmd;\n-\n-\tcmd = enet_umac_read(enet, UMAC_CMD);\n-\tenet_umac_write(enet, UMAC_CMD, cmd | CMD_SW_RESET);\n-\tenet_umac_write(enet, UMAC_CMD, cmd & ~CMD_SW_RESET);\n-\n-\tenet_set(enet, ENET_FLUSH, ENET_FLUSH_RXFIFO_FLUSH | ENET_FLUSH_TXFIFO_FLUSH);\n-\tenet_maskset(enet, ENET_FLUSH, ENET_FLUSH_RXFIFO_FLUSH | ENET_FLUSH_TXFIFO_FLUSH, 0);\n-\n-\tenet_set(enet, ENET_MIB_CTRL, ENET_MIB_CTRL_CLR_MIB);\n-\tenet_maskset(enet, ENET_MIB_CTRL, ENET_MIB_CTRL_CLR_MIB, 0);\n-\n-\tcmd = enet_umac_read(enet, UMAC_CMD);\n-\tcmd &= ~(CMD_SPEED_MASK << CMD_SPEED_SHIFT);\n-\tcmd &= ~CMD_TX_EN;\n-\tcmd &= ~CMD_RX_EN;\n-\tcmd |= CMD_SPEED_1000 << CMD_SPEED_SHIFT;\n-\tenet_umac_write(enet, UMAC_CMD, cmd);\n-\n-\tenet_maskset(enet, ENET_GMAC_STATUS,\n-\t\t     ENET_GMAC_STATUS_ETH_SPEED_MASK |\n-\t\t     ENET_GMAC_STATUS_HD |\n-\t\t     ENET_GMAC_STATUS_AUTO_CFG_EN |\n-\t\t     ENET_GMAC_STATUS_LINK_UP,\n-\t\t     ENET_GMAC_STATUS_ETH_SPEED_1000 |\n-\t\t     ENET_GMAC_STATUS_AUTO_CFG_EN |\n-\t\t     ENET_GMAC_STATUS_LINK_UP);\n-}\n-\n-static irqreturn_t bcm4908enet_irq_handler(int irq, void *dev_id)\n-{\n-\tstruct bcm4908enet *enet = dev_id;\n-\n-\tbcm4908enet_intrs_off(enet);\n-\tbcm4908enet_intrs_ack(enet);\n-\n-\tnapi_schedule(&enet->napi);\n-\n-\treturn IRQ_HANDLED;\n-}\n-\n-static int bcm4908enet_open(struct net_device *netdev)\n-{\n-\tstruct bcm4908enet *enet = netdev_priv(netdev);\n-\tstruct device *dev = enet->dev;\n-\tint err;\n-\n-\terr = request_irq(netdev->irq, bcm4908enet_irq_handler, 0, \"enet\", enet);\n-\tif (err) {\n-\t\tdev_err(dev, \"Failed to request IRQ %d: %d\\n\", netdev->irq, err);\n-\t\treturn err;\n-\t}\n-\n-\tbcm4908enet_gmac_init(enet);\n-\tbcm4908enet_dma_reset(enet);\n-\tbcm4908enet_dma_init(enet);\n-\n-\tenet_umac_set(enet, UMAC_CMD, CMD_TX_EN | CMD_RX_EN);\n-\n-\tenet_set(enet, ENET_DMA_CONTROLLER_CFG, ENET_DMA_CTRL_CFG_MASTER_EN);\n-\tenet_maskset(enet, ENET_DMA_CONTROLLER_CFG, ENET_DMA_CTRL_CFG_FLOWC_CH1_EN, 0);\n-\tbcm4908enet_dma_rx_ring_enable(enet, &enet->rx_ring);\n-\n-\tnapi_enable(&enet->napi);\n-\tnetif_carrier_on(netdev);\n-\tnetif_start_queue(netdev);\n-\n-\tbcm4908enet_intrs_ack(enet);\n-\tbcm4908enet_intrs_on(enet);\n-\n-\treturn 0;\n-}\n-\n-static int bcm4908enet_stop(struct net_device *netdev)\n-{\n-\tstruct bcm4908enet *enet = netdev_priv(netdev);\n-\n-\tnetif_stop_queue(netdev);\n-\tnetif_carrier_off(netdev);\n-\tnapi_disable(&enet->napi);\n-\n-\tbcm4908enet_dma_rx_ring_disable(enet, &enet->rx_ring);\n-\tbcm4908enet_dma_tx_ring_disable(enet, &enet->tx_ring);\n-\n-\tbcm4908enet_dma_uninit(enet);\n-\n-\tfree_irq(enet->netdev->irq, enet);\n-\n-\treturn 0;\n-}\n-\n-static int bcm4908enet_start_xmit(struct sk_buff *skb, struct net_device *netdev)\n-{\n-\tstruct bcm4908enet *enet = netdev_priv(netdev);\n-\tstruct bcm4908enet_dma_ring *ring = &enet->tx_ring;\n-\tstruct bcm4908enet_dma_ring_slot *slot;\n-\tstruct device *dev = enet->dev;\n-\tstruct bcm4908enet_dma_ring_bd *buf_desc;\n-\tint free_buf_descs;\n-\tu32 tmp;\n-\n-\t/* Free transmitted skbs */\n-\twhile (ring->read_idx != ring->write_idx) {\n-\t\tbuf_desc = &ring->buf_desc[ring->read_idx];\n-\t\tif (buf_desc->ctl & DMA_CTL_STATUS_OWN)\n-\t\t\tbreak;\n-\t\tslot = &ring->slots[ring->read_idx];\n-\n-\t\tdma_unmap_single(dev, slot->dma_addr, slot->len, DMA_TO_DEVICE);\n-\t\tdev_kfree_skb(slot->skb);\n-\t\tif (++ring->read_idx == ring->length)\n-\t\t\tring->read_idx = 0;\n-\t}\n-\n-\t/* Don't use the last empty buf descriptor */\n-\tif (ring->read_idx <= ring->write_idx)\n-\t\tfree_buf_descs = ring->read_idx - ring->write_idx + ring->length;\n-\telse\n-\t\tfree_buf_descs = ring->read_idx - ring->write_idx;\n-\tif (free_buf_descs < 2)\n-\t\treturn NETDEV_TX_BUSY;\n-\n-\t/* Hardware removes OWN bit after sending data */\n-\tbuf_desc = &ring->buf_desc[ring->write_idx];\n-\tif (unlikely(le32_to_cpu(buf_desc->ctl) & DMA_CTL_STATUS_OWN)) {\n-\t\tnetif_stop_queue(netdev);\n-\t\treturn NETDEV_TX_BUSY;\n-\t}\n-\n-\tslot = &ring->slots[ring->write_idx];\n-\tslot->skb = skb;\n-\tslot->len = skb->len;\n-\tslot->dma_addr = dma_map_single(dev, skb->data, skb->len, DMA_TO_DEVICE);\n-\tif (unlikely(dma_mapping_error(dev, slot->dma_addr)))\n-\t\treturn NETDEV_TX_BUSY;\n-\n-\ttmp = skb->len << DMA_CTL_LEN_DESC_BUFLENGTH_SHIFT;\n-\ttmp |= DMA_CTL_STATUS_OWN;\n-\ttmp |= DMA_CTL_STATUS_SOP;\n-\ttmp |= DMA_CTL_STATUS_EOP;\n-\ttmp |= DMA_CTL_STATUS_APPEND_CRC;\n-\tif (ring->write_idx + 1 == ring->length - 1)\n-\t\ttmp |= DMA_CTL_STATUS_WRAP;\n-\n-\tbuf_desc->addr = cpu_to_le32((uint32_t)slot->dma_addr);\n-\tbuf_desc->ctl = cpu_to_le32(tmp);\n-\n-\tbcm4908enet_dma_tx_ring_ensable(enet, &enet->tx_ring);\n-\n-\tif (++ring->write_idx == ring->length - 1)\n-\t\tring->write_idx = 0;\n-\tenet->netdev->stats.tx_bytes += skb->len;\n-\tenet->netdev->stats.tx_packets++;\n-\n-\treturn NETDEV_TX_OK;\n-}\n-\n-static int bcm4908enet_poll(struct napi_struct *napi, int weight)\n-{\n-\tstruct bcm4908enet *enet = container_of(napi, struct bcm4908enet, napi);\n-\tstruct device *dev = enet->dev;\n-\tint handled = 0;\n-\n-\twhile (handled < weight) {\n-\t\tstruct bcm4908enet_dma_ring_bd *buf_desc;\n-\t\tstruct bcm4908enet_dma_ring_slot slot;\n-\t\tu32 ctl;\n-\t\tint len;\n-\t\tint err;\n-\n-\t\tbuf_desc = &enet->rx_ring.buf_desc[enet->rx_ring.read_idx];\n-\t\tctl = le32_to_cpu(buf_desc->ctl);\n-\t\tif (ctl & DMA_CTL_STATUS_OWN)\n-\t\t\tbreak;\n-\n-\t\tslot = enet->rx_ring.slots[enet->rx_ring.read_idx];\n-\n-\t\t/* Provide new buffer before unpinning the old one */\n-\t\terr = bcm4908enet_dma_alloc_rx_buf(enet, enet->rx_ring.read_idx);\n-\t\tif (err)\n-\t\t\tbreak;\n-\n-\t\tif (++enet->rx_ring.read_idx == enet->rx_ring.length)\n-\t\t\tenet->rx_ring.read_idx = 0;\n-\n-\t\tlen = (ctl & DMA_CTL_LEN_DESC_BUFLENGTH) >> DMA_CTL_LEN_DESC_BUFLENGTH_SHIFT;\n-\n-\t\tif (len < ENET_MTU_MIN ||\n-\t\t    (ctl & (DMA_CTL_STATUS_SOP | DMA_CTL_STATUS_EOP)) != (DMA_CTL_STATUS_SOP | DMA_CTL_STATUS_EOP)) {\n-\t\t\tenet->netdev->stats.rx_dropped++;\n-\t\t\tbreak;\n-\t\t}\n-\n-\t\tdma_unmap_single(dev, slot.dma_addr, slot.len, DMA_FROM_DEVICE);\n-\n-\t\tskb_put(slot.skb, len - 4 + 2);\n-\t\tslot.skb->protocol = eth_type_trans(slot.skb, enet->netdev);\n-\t\tnetif_receive_skb(slot.skb);\n-\n-\t\tenet->netdev->stats.rx_packets++;\n-\t\tenet->netdev->stats.rx_bytes += len;\n-\t}\n-\n-\tif (handled < weight) {\n-\t\tnapi_complete_done(napi, handled);\n-\t\tbcm4908enet_intrs_on(enet);\n-\t}\n-\n-\treturn handled;\n-}\n-\n-static const struct net_device_ops bcm96xx_netdev_ops = {\n-\t.ndo_open = bcm4908enet_open,\n-\t.ndo_stop = bcm4908enet_stop,\n-\t.ndo_start_xmit = bcm4908enet_start_xmit,\n-\t.ndo_set_mac_address = eth_mac_addr,\n-};\n-\n-static int bcm4908enet_probe(struct platform_device *pdev)\n-{\n-\tstruct device *dev = &pdev->dev;\n-\tstruct net_device *netdev;\n-\tstruct bcm4908enet *enet;\n-\tint err;\n-\n-\tnetdev = devm_alloc_etherdev(dev, sizeof(*enet));\n-\tif (!netdev)\n-\t\treturn -ENOMEM;\n-\n-\tenet = netdev_priv(netdev);\n-\tenet->dev = dev;\n-\tenet->netdev = netdev;\n-\n-\tenet->base = devm_platform_ioremap_resource(pdev, 0);\n-\tif (IS_ERR(enet->base)) {\n-\t\tdev_err(dev, \"Failed to map registers: %ld\\n\", PTR_ERR(enet->base));\n-\t\treturn PTR_ERR(enet->base);\n-\t}\n-\n-\tnetdev->irq = platform_get_irq_byname(pdev, \"rx\");\n-\tif (netdev->irq < 0)\n-\t\treturn netdev->irq;\n-\n-\tdma_set_coherent_mask(dev, DMA_BIT_MASK(32));\n-\n-\terr = bcm4908enet_dma_alloc(enet);\n-\tif (err)\n-\t\treturn err;\n-\n-\tSET_NETDEV_DEV(netdev, &pdev->dev);\n-\teth_hw_addr_random(netdev);\n-\tnetdev->netdev_ops = &bcm96xx_netdev_ops;\n-\tnetdev->min_mtu = ETH_ZLEN;\n-\tnetdev->mtu = ENET_MTU_MAX;\n-\tnetdev->max_mtu = ENET_MTU_MAX;\n-\tnetif_napi_add(netdev, &enet->napi, bcm4908enet_poll, 64);\n-\n-\terr = register_netdev(netdev);\n-\tif (err) {\n-\t\tbcm4908enet_dma_free(enet);\n-\t\treturn err;\n-\t}\n-\n-\tplatform_set_drvdata(pdev, enet);\n-\n-\treturn 0;\n-}\n-\n-static int bcm4908enet_remove(struct platform_device *pdev)\n-{\n-\tstruct bcm4908enet *enet = platform_get_drvdata(pdev);\n-\n-\tunregister_netdev(enet->netdev);\n-\tnetif_napi_del(&enet->napi);\n-\tbcm4908enet_dma_free(enet);\n-\n-\treturn 0;\n-}\n-\n-static const struct of_device_id bcm4908enet_of_match[] = {\n-\t{ .compatible = \"brcm,bcm4908enet\"},\n-\t{},\n-};\n-\n-static struct platform_driver bcm4908enet_driver = {\n-\t.driver = {\n-\t\t.name = \"bcm4908enet\",\n-\t\t.of_match_table = bcm4908enet_of_match,\n-\t},\n-\t.probe\t= bcm4908enet_probe,\n-\t.remove = bcm4908enet_remove,\n-};\n-module_platform_driver(bcm4908enet_driver);\n-\n-MODULE_LICENSE(\"GPL v2\");\n-MODULE_DEVICE_TABLE(of, bcm4908enet_of_match);\n--- /dev/null\n+++ b/drivers/net/ethernet/broadcom/bcm4908_enet.c\n@@ -0,0 +1,677 @@\n+// SPDX-License-Identifier: GPL-2.0-only\n+/*\n+ * Copyright (C) 2021 Rafał Miłecki <rafal@milecki.pl>\n+ */\n+\n+#include <linux/delay.h>\n+#include <linux/etherdevice.h>\n+#include <linux/interrupt.h>\n+#include <linux/module.h>\n+#include <linux/of.h>\n+#include <linux/platform_device.h>\n+#include <linux/slab.h>\n+#include <linux/string.h>\n+\n+#include \"bcm4908_enet.h\"\n+#include \"unimac.h\"\n+\n+#define ENET_DMA_CH_RX_CFG\t\t\tENET_DMA_CH0_CFG\n+#define ENET_DMA_CH_TX_CFG\t\t\tENET_DMA_CH1_CFG\n+#define ENET_DMA_CH_RX_STATE_RAM\t\tENET_DMA_CH0_STATE_RAM\n+#define ENET_DMA_CH_TX_STATE_RAM\t\tENET_DMA_CH1_STATE_RAM\n+\n+#define ENET_TX_BDS_NUM\t\t\t\t200\n+#define ENET_RX_BDS_NUM\t\t\t\t200\n+#define ENET_RX_BDS_NUM_MAX\t\t\t8192\n+\n+#define ENET_DMA_INT_DEFAULTS\t\t\t(ENET_DMA_CH_CFG_INT_DONE | \\\n+\t\t\t\t\t\t ENET_DMA_CH_CFG_INT_NO_DESC | \\\n+\t\t\t\t\t\t ENET_DMA_CH_CFG_INT_BUFF_DONE)\n+#define ENET_DMA_MAX_BURST_LEN\t\t\t8 /* in 64 bit words */\n+\n+#define ENET_MTU_MIN\t\t\t\t60\n+#define ENET_MTU_MAX\t\t\t\t1500 /* Is it possible to support 2044? */\n+#define ENET_MTU_MAX_EXTRA_SIZE\t\t\t32 /* L2 */\n+\n+struct bcm4908_enet_dma_ring_bd {\n+\t__le32 ctl;\n+\t__le32 addr;\n+} __packed;\n+\n+struct bcm4908_enet_dma_ring_slot {\n+\tstruct sk_buff *skb;\n+\tunsigned int len;\n+\tdma_addr_t dma_addr;\n+};\n+\n+struct bcm4908_enet_dma_ring {\n+\tint is_tx;\n+\tint read_idx;\n+\tint write_idx;\n+\tint length;\n+\tu16 cfg_block;\n+\tu16 st_ram_block;\n+\n+\tunion {\n+\t\tvoid *cpu_addr;\n+\t\tstruct bcm4908_enet_dma_ring_bd *buf_desc;\n+\t};\n+\tdma_addr_t dma_addr;\n+\n+\tstruct bcm4908_enet_dma_ring_slot *slots;\n+};\n+\n+struct bcm4908_enet {\n+\tstruct device *dev;\n+\tstruct net_device *netdev;\n+\tstruct napi_struct napi;\n+\tvoid __iomem *base;\n+\n+\tstruct bcm4908_enet_dma_ring tx_ring;\n+\tstruct bcm4908_enet_dma_ring rx_ring;\n+};\n+\n+/***\n+ * R/W ops\n+ */\n+\n+static inline u32 enet_read(struct bcm4908_enet *enet, u16 offset)\n+{\n+\treturn readl(enet->base + offset);\n+}\n+\n+static inline void enet_write(struct bcm4908_enet *enet, u16 offset, u32 value)\n+{\n+\twritel(value, enet->base + offset);\n+}\n+\n+static inline void enet_maskset(struct bcm4908_enet *enet, u16 offset, u32 mask, u32 set)\n+{\n+\tu32 val;\n+\n+\tWARN_ON(set & ~mask);\n+\n+\tval = enet_read(enet, offset);\n+\tval = (val & ~mask) | (set & mask);\n+\tenet_write(enet, offset, val);\n+}\n+\n+static inline void enet_set(struct bcm4908_enet *enet, u16 offset, u32 set)\n+{\n+\tenet_maskset(enet, offset, set, set);\n+}\n+\n+static inline u32 enet_umac_read(struct bcm4908_enet *enet, u16 offset)\n+{\n+\treturn enet_read(enet, ENET_UNIMAC + offset);\n+}\n+\n+static inline void enet_umac_write(struct bcm4908_enet *enet, u16 offset, u32 value)\n+{\n+\tenet_write(enet, ENET_UNIMAC + offset, value);\n+}\n+\n+static inline void enet_umac_maskset(struct bcm4908_enet *enet, u16 offset, u32 mask, u32 set)\n+{\n+\tenet_maskset(enet, ENET_UNIMAC + offset, mask, set);\n+}\n+\n+static inline void enet_umac_set(struct bcm4908_enet *enet, u16 offset, u32 set)\n+{\n+\tenet_set(enet, ENET_UNIMAC + offset, set);\n+}\n+\n+/***\n+ * Helpers\n+ */\n+\n+static void bcm4908_enet_intrs_on(struct bcm4908_enet *enet)\n+{\n+\tenet_write(enet, ENET_DMA_CH_RX_CFG + ENET_DMA_CH_CFG_INT_MASK, ENET_DMA_INT_DEFAULTS);\n+}\n+\n+static void bcm4908_enet_intrs_off(struct bcm4908_enet *enet)\n+{\n+\tenet_write(enet, ENET_DMA_CH_RX_CFG + ENET_DMA_CH_CFG_INT_MASK, 0);\n+}\n+\n+static void bcm4908_enet_intrs_ack(struct bcm4908_enet *enet)\n+{\n+\tenet_write(enet, ENET_DMA_CH_RX_CFG + ENET_DMA_CH_CFG_INT_STAT, ENET_DMA_INT_DEFAULTS);\n+}\n+\n+/***\n+ * DMA\n+ */\n+\n+static int bcm4908_dma_alloc_buf_descs(struct bcm4908_enet *enet,\n+\t\t\t\t       struct bcm4908_enet_dma_ring *ring)\n+{\n+\tint size = ring->length * sizeof(struct bcm4908_enet_dma_ring_bd);\n+\tstruct device *dev = enet->dev;\n+\n+\tring->cpu_addr = dma_alloc_coherent(dev, size, &ring->dma_addr, GFP_KERNEL);\n+\tif (!ring->cpu_addr)\n+\t\treturn -ENOMEM;\n+\n+\tif (((uintptr_t)ring->cpu_addr) & (0x40 - 1)) {\n+\t\tdev_err(dev, \"Invalid DMA ring alignment\\n\");\n+\t\tgoto err_free_buf_descs;\n+\t}\n+\n+\tring->slots = kzalloc(ring->length * sizeof(*ring->slots), GFP_KERNEL);\n+\tif (!ring->slots)\n+\t\tgoto err_free_buf_descs;\n+\n+\tmemset(ring->cpu_addr, 0, size);\n+\n+\tring->read_idx = 0;\n+\tring->write_idx = 0;\n+\n+\treturn 0;\n+\n+err_free_buf_descs:\n+\tdma_free_coherent(dev, size, ring->cpu_addr, ring->dma_addr);\n+\treturn -ENOMEM;\n+}\n+\n+static void bcm4908_enet_dma_free(struct bcm4908_enet *enet)\n+{\n+\tstruct bcm4908_enet_dma_ring *tx_ring = &enet->tx_ring;\n+\tstruct bcm4908_enet_dma_ring *rx_ring = &enet->rx_ring;\n+\tstruct device *dev = enet->dev;\n+\tint size;\n+\n+\tsize = rx_ring->length * sizeof(struct bcm4908_enet_dma_ring_bd);\n+\tif (rx_ring->cpu_addr)\n+\t\tdma_free_coherent(dev, size, rx_ring->cpu_addr, rx_ring->dma_addr);\n+\tkfree(rx_ring->slots);\n+\n+\tsize = tx_ring->length * sizeof(struct bcm4908_enet_dma_ring_bd);\n+\tif (tx_ring->cpu_addr)\n+\t\tdma_free_coherent(dev, size, tx_ring->cpu_addr, tx_ring->dma_addr);\n+\tkfree(tx_ring->slots);\n+}\n+\n+static int bcm4908_enet_dma_alloc(struct bcm4908_enet *enet)\n+{\n+\tstruct bcm4908_enet_dma_ring *tx_ring = &enet->tx_ring;\n+\tstruct bcm4908_enet_dma_ring *rx_ring = &enet->rx_ring;\n+\tstruct device *dev = enet->dev;\n+\tint err;\n+\n+\ttx_ring->length = ENET_TX_BDS_NUM;\n+\ttx_ring->is_tx = 1;\n+\ttx_ring->cfg_block = ENET_DMA_CH_TX_CFG;\n+\ttx_ring->st_ram_block = ENET_DMA_CH_TX_STATE_RAM;\n+\terr = bcm4908_dma_alloc_buf_descs(enet, tx_ring);\n+\tif (err) {\n+\t\tdev_err(dev, \"Failed to alloc TX buf descriptors: %d\\n\", err);\n+\t\treturn err;\n+\t}\n+\n+\trx_ring->length = ENET_RX_BDS_NUM;\n+\trx_ring->is_tx = 0;\n+\trx_ring->cfg_block = ENET_DMA_CH_RX_CFG;\n+\trx_ring->st_ram_block = ENET_DMA_CH_RX_STATE_RAM;\n+\terr = bcm4908_dma_alloc_buf_descs(enet, rx_ring);\n+\tif (err) {\n+\t\tdev_err(dev, \"Failed to alloc RX buf descriptors: %d\\n\", err);\n+\t\tbcm4908_enet_dma_free(enet);\n+\t\treturn err;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static void bcm4908_enet_dma_reset(struct bcm4908_enet *enet)\n+{\n+\tstruct bcm4908_enet_dma_ring *rings[] = { &enet->rx_ring, &enet->tx_ring };\n+\tint i;\n+\n+\t/* Disable the DMA controller and channel */\n+\tfor (i = 0; i < ARRAY_SIZE(rings); i++)\n+\t\tenet_write(enet, rings[i]->cfg_block + ENET_DMA_CH_CFG, 0);\n+\tenet_maskset(enet, ENET_DMA_CONTROLLER_CFG, ENET_DMA_CTRL_CFG_MASTER_EN, 0);\n+\n+\t/* Reset channels state */\n+\tfor (i = 0; i < ARRAY_SIZE(rings); i++) {\n+\t\tstruct bcm4908_enet_dma_ring *ring = rings[i];\n+\n+\t\tenet_write(enet, ring->st_ram_block + ENET_DMA_CH_STATE_RAM_BASE_DESC_PTR, 0);\n+\t\tenet_write(enet, ring->st_ram_block + ENET_DMA_CH_STATE_RAM_STATE_DATA, 0);\n+\t\tenet_write(enet, ring->st_ram_block + ENET_DMA_CH_STATE_RAM_DESC_LEN_STATUS, 0);\n+\t\tenet_write(enet, ring->st_ram_block + ENET_DMA_CH_STATE_RAM_DESC_BASE_BUFPTR, 0);\n+\t}\n+}\n+\n+static int bcm4908_enet_dma_alloc_rx_buf(struct bcm4908_enet *enet, unsigned int idx)\n+{\n+\tstruct bcm4908_enet_dma_ring_bd *buf_desc = &enet->rx_ring.buf_desc[idx];\n+\tstruct bcm4908_enet_dma_ring_slot *slot = &enet->rx_ring.slots[idx];\n+\tstruct device *dev = enet->dev;\n+\tu32 tmp;\n+\tint err;\n+\n+\tslot->len = ENET_MTU_MAX + ENET_MTU_MAX_EXTRA_SIZE;\n+\n+\tslot->skb = netdev_alloc_skb(enet->netdev, slot->len);\n+\tif (!slot->skb)\n+\t\treturn -ENOMEM;\n+\n+\tslot->dma_addr = dma_map_single(dev, slot->skb->data, slot->len, DMA_FROM_DEVICE);\n+\terr = dma_mapping_error(dev, slot->dma_addr);\n+\tif (err) {\n+\t\tdev_err(dev, \"Failed to map DMA buffer: %d\\n\", err);\n+\t\tkfree_skb(slot->skb);\n+\t\tslot->skb = NULL;\n+\t\treturn err;\n+\t}\n+\n+\ttmp = slot->len << DMA_CTL_LEN_DESC_BUFLENGTH_SHIFT;\n+\ttmp |= DMA_CTL_STATUS_OWN;\n+\tif (idx == enet->rx_ring.length - 1)\n+\t\ttmp |= DMA_CTL_STATUS_WRAP;\n+\tbuf_desc->ctl = cpu_to_le32(tmp);\n+\tbuf_desc->addr = cpu_to_le32(slot->dma_addr);\n+\n+\treturn 0;\n+}\n+\n+static void bcm4908_enet_dma_ring_init(struct bcm4908_enet *enet,\n+\t\t\t\t       struct bcm4908_enet_dma_ring *ring)\n+{\n+\tint reset_channel = 0; /* We support only 1 main channel (with TX and RX) */\n+\tint reset_subch = ring->is_tx ? 1 : 0;\n+\n+\t/* Reset the DMA channel */\n+\tenet_write(enet, ENET_DMA_CTRL_CHANNEL_RESET, BIT(reset_channel * 2 + reset_subch));\n+\tenet_write(enet, ENET_DMA_CTRL_CHANNEL_RESET, 0);\n+\n+\tenet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG, 0);\n+\tenet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG_MAX_BURST, ENET_DMA_MAX_BURST_LEN);\n+\tenet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG_INT_MASK, 0);\n+\n+\tenet_write(enet, ring->st_ram_block + ENET_DMA_CH_STATE_RAM_BASE_DESC_PTR,\n+\t\t   (uint32_t)ring->dma_addr);\n+}\n+\n+static void bcm4908_enet_dma_uninit(struct bcm4908_enet *enet)\n+{\n+\tstruct bcm4908_enet_dma_ring *rx_ring = &enet->rx_ring;\n+\tstruct bcm4908_enet_dma_ring_slot *slot;\n+\tstruct device *dev = enet->dev;\n+\tint i;\n+\n+\tfor (i = rx_ring->length - 1; i >= 0; i--) {\n+\t\tslot = &rx_ring->slots[i];\n+\t\tif (!slot->skb)\n+\t\t\tcontinue;\n+\t\tdma_unmap_single(dev, slot->dma_addr, slot->len, DMA_FROM_DEVICE);\n+\t\tkfree_skb(slot->skb);\n+\t\tslot->skb = NULL;\n+\t}\n+}\n+\n+static int bcm4908_enet_dma_init(struct bcm4908_enet *enet)\n+{\n+\tstruct bcm4908_enet_dma_ring *rx_ring = &enet->rx_ring;\n+\tstruct device *dev = enet->dev;\n+\tint err;\n+\tint i;\n+\n+\tfor (i = 0; i < rx_ring->length; i++) {\n+\t\terr = bcm4908_enet_dma_alloc_rx_buf(enet, i);\n+\t\tif (err) {\n+\t\t\tdev_err(dev, \"Failed to alloc RX buffer: %d\\n\", err);\n+\t\t\tbcm4908_enet_dma_uninit(enet);\n+\t\t\treturn err;\n+\t\t}\n+\t}\n+\n+\tbcm4908_enet_dma_ring_init(enet, &enet->tx_ring);\n+\tbcm4908_enet_dma_ring_init(enet, &enet->rx_ring);\n+\n+\treturn 0;\n+}\n+\n+static void bcm4908_enet_dma_tx_ring_ensable(struct bcm4908_enet *enet,\n+\t\t\t\t\t     struct bcm4908_enet_dma_ring *ring)\n+{\n+\tenet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG, ENET_DMA_CH_CFG_ENABLE);\n+}\n+\n+static void bcm4908_enet_dma_tx_ring_disable(struct bcm4908_enet *enet,\n+\t\t\t\t\t     struct bcm4908_enet_dma_ring *ring)\n+{\n+\tenet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG, 0);\n+}\n+\n+static void bcm4908_enet_dma_rx_ring_enable(struct bcm4908_enet *enet,\n+\t\t\t\t\t    struct bcm4908_enet_dma_ring *ring)\n+{\n+\tenet_set(enet, ring->cfg_block + ENET_DMA_CH_CFG, ENET_DMA_CH_CFG_ENABLE);\n+}\n+\n+static void bcm4908_enet_dma_rx_ring_disable(struct bcm4908_enet *enet,\n+\t\t\t\t\t     struct bcm4908_enet_dma_ring *ring)\n+{\n+\tunsigned long deadline;\n+\tu32 tmp;\n+\n+\tenet_maskset(enet, ring->cfg_block + ENET_DMA_CH_CFG, ENET_DMA_CH_CFG_ENABLE, 0);\n+\n+\tdeadline = jiffies + usecs_to_jiffies(2000);\n+\tdo {\n+\t\ttmp = enet_read(enet, ring->cfg_block + ENET_DMA_CH_CFG);\n+\t\tif (!(tmp & ENET_DMA_CH_CFG_ENABLE))\n+\t\t\treturn;\n+\t\tenet_maskset(enet, ring->cfg_block + ENET_DMA_CH_CFG, ENET_DMA_CH_CFG_ENABLE, 0);\n+\t\tusleep_range(10, 30);\n+\t} while (!time_after_eq(jiffies, deadline));\n+\n+\tdev_warn(enet->dev, \"Timeout waiting for DMA TX stop\\n\");\n+}\n+\n+/***\n+ * Ethernet driver\n+ */\n+\n+static void bcm4908_enet_gmac_init(struct bcm4908_enet *enet)\n+{\n+\tu32 cmd;\n+\n+\tcmd = enet_umac_read(enet, UMAC_CMD);\n+\tenet_umac_write(enet, UMAC_CMD, cmd | CMD_SW_RESET);\n+\tenet_umac_write(enet, UMAC_CMD, cmd & ~CMD_SW_RESET);\n+\n+\tenet_set(enet, ENET_FLUSH, ENET_FLUSH_RXFIFO_FLUSH | ENET_FLUSH_TXFIFO_FLUSH);\n+\tenet_maskset(enet, ENET_FLUSH, ENET_FLUSH_RXFIFO_FLUSH | ENET_FLUSH_TXFIFO_FLUSH, 0);\n+\n+\tenet_set(enet, ENET_MIB_CTRL, ENET_MIB_CTRL_CLR_MIB);\n+\tenet_maskset(enet, ENET_MIB_CTRL, ENET_MIB_CTRL_CLR_MIB, 0);\n+\n+\tcmd = enet_umac_read(enet, UMAC_CMD);\n+\tcmd &= ~(CMD_SPEED_MASK << CMD_SPEED_SHIFT);\n+\tcmd &= ~CMD_TX_EN;\n+\tcmd &= ~CMD_RX_EN;\n+\tcmd |= CMD_SPEED_1000 << CMD_SPEED_SHIFT;\n+\tenet_umac_write(enet, UMAC_CMD, cmd);\n+\n+\tenet_maskset(enet, ENET_GMAC_STATUS,\n+\t\t     ENET_GMAC_STATUS_ETH_SPEED_MASK |\n+\t\t     ENET_GMAC_STATUS_HD |\n+\t\t     ENET_GMAC_STATUS_AUTO_CFG_EN |\n+\t\t     ENET_GMAC_STATUS_LINK_UP,\n+\t\t     ENET_GMAC_STATUS_ETH_SPEED_1000 |\n+\t\t     ENET_GMAC_STATUS_AUTO_CFG_EN |\n+\t\t     ENET_GMAC_STATUS_LINK_UP);\n+}\n+\n+static irqreturn_t bcm4908_enet_irq_handler(int irq, void *dev_id)\n+{\n+\tstruct bcm4908_enet *enet = dev_id;\n+\n+\tbcm4908_enet_intrs_off(enet);\n+\tbcm4908_enet_intrs_ack(enet);\n+\n+\tnapi_schedule(&enet->napi);\n+\n+\treturn IRQ_HANDLED;\n+}\n+\n+static int bcm4908_enet_open(struct net_device *netdev)\n+{\n+\tstruct bcm4908_enet *enet = netdev_priv(netdev);\n+\tstruct device *dev = enet->dev;\n+\tint err;\n+\n+\terr = request_irq(netdev->irq, bcm4908_enet_irq_handler, 0, \"enet\", enet);\n+\tif (err) {\n+\t\tdev_err(dev, \"Failed to request IRQ %d: %d\\n\", netdev->irq, err);\n+\t\treturn err;\n+\t}\n+\n+\tbcm4908_enet_gmac_init(enet);\n+\tbcm4908_enet_dma_reset(enet);\n+\tbcm4908_enet_dma_init(enet);\n+\n+\tenet_umac_set(enet, UMAC_CMD, CMD_TX_EN | CMD_RX_EN);\n+\n+\tenet_set(enet, ENET_DMA_CONTROLLER_CFG, ENET_DMA_CTRL_CFG_MASTER_EN);\n+\tenet_maskset(enet, ENET_DMA_CONTROLLER_CFG, ENET_DMA_CTRL_CFG_FLOWC_CH1_EN, 0);\n+\tbcm4908_enet_dma_rx_ring_enable(enet, &enet->rx_ring);\n+\n+\tnapi_enable(&enet->napi);\n+\tnetif_carrier_on(netdev);\n+\tnetif_start_queue(netdev);\n+\n+\tbcm4908_enet_intrs_ack(enet);\n+\tbcm4908_enet_intrs_on(enet);\n+\n+\treturn 0;\n+}\n+\n+static int bcm4908_enet_stop(struct net_device *netdev)\n+{\n+\tstruct bcm4908_enet *enet = netdev_priv(netdev);\n+\n+\tnetif_stop_queue(netdev);\n+\tnetif_carrier_off(netdev);\n+\tnapi_disable(&enet->napi);\n+\n+\tbcm4908_enet_dma_rx_ring_disable(enet, &enet->rx_ring);\n+\tbcm4908_enet_dma_tx_ring_disable(enet, &enet->tx_ring);\n+\n+\tbcm4908_enet_dma_uninit(enet);\n+\n+\tfree_irq(enet->netdev->irq, enet);\n+\n+\treturn 0;\n+}\n+\n+static int bcm4908_enet_start_xmit(struct sk_buff *skb, struct net_device *netdev)\n+{\n+\tstruct bcm4908_enet *enet = netdev_priv(netdev);\n+\tstruct bcm4908_enet_dma_ring *ring = &enet->tx_ring;\n+\tstruct bcm4908_enet_dma_ring_slot *slot;\n+\tstruct device *dev = enet->dev;\n+\tstruct bcm4908_enet_dma_ring_bd *buf_desc;\n+\tint free_buf_descs;\n+\tu32 tmp;\n+\n+\t/* Free transmitted skbs */\n+\twhile (ring->read_idx != ring->write_idx) {\n+\t\tbuf_desc = &ring->buf_desc[ring->read_idx];\n+\t\tif (buf_desc->ctl & DMA_CTL_STATUS_OWN)\n+\t\t\tbreak;\n+\t\tslot = &ring->slots[ring->read_idx];\n+\n+\t\tdma_unmap_single(dev, slot->dma_addr, slot->len, DMA_TO_DEVICE);\n+\t\tdev_kfree_skb(slot->skb);\n+\t\tif (++ring->read_idx == ring->length)\n+\t\t\tring->read_idx = 0;\n+\t}\n+\n+\t/* Don't use the last empty buf descriptor */\n+\tif (ring->read_idx <= ring->write_idx)\n+\t\tfree_buf_descs = ring->read_idx - ring->write_idx + ring->length;\n+\telse\n+\t\tfree_buf_descs = ring->read_idx - ring->write_idx;\n+\tif (free_buf_descs < 2)\n+\t\treturn NETDEV_TX_BUSY;\n+\n+\t/* Hardware removes OWN bit after sending data */\n+\tbuf_desc = &ring->buf_desc[ring->write_idx];\n+\tif (unlikely(le32_to_cpu(buf_desc->ctl) & DMA_CTL_STATUS_OWN)) {\n+\t\tnetif_stop_queue(netdev);\n+\t\treturn NETDEV_TX_BUSY;\n+\t}\n+\n+\tslot = &ring->slots[ring->write_idx];\n+\tslot->skb = skb;\n+\tslot->len = skb->len;\n+\tslot->dma_addr = dma_map_single(dev, skb->data, skb->len, DMA_TO_DEVICE);\n+\tif (unlikely(dma_mapping_error(dev, slot->dma_addr)))\n+\t\treturn NETDEV_TX_BUSY;\n+\n+\ttmp = skb->len << DMA_CTL_LEN_DESC_BUFLENGTH_SHIFT;\n+\ttmp |= DMA_CTL_STATUS_OWN;\n+\ttmp |= DMA_CTL_STATUS_SOP;\n+\ttmp |= DMA_CTL_STATUS_EOP;\n+\ttmp |= DMA_CTL_STATUS_APPEND_CRC;\n+\tif (ring->write_idx + 1 == ring->length - 1)\n+\t\ttmp |= DMA_CTL_STATUS_WRAP;\n+\n+\tbuf_desc->addr = cpu_to_le32((uint32_t)slot->dma_addr);\n+\tbuf_desc->ctl = cpu_to_le32(tmp);\n+\n+\tbcm4908_enet_dma_tx_ring_ensable(enet, &enet->tx_ring);\n+\n+\tif (++ring->write_idx == ring->length - 1)\n+\t\tring->write_idx = 0;\n+\tenet->netdev->stats.tx_bytes += skb->len;\n+\tenet->netdev->stats.tx_packets++;\n+\n+\treturn NETDEV_TX_OK;\n+}\n+\n+static int bcm4908_enet_poll(struct napi_struct *napi, int weight)\n+{\n+\tstruct bcm4908_enet *enet = container_of(napi, struct bcm4908_enet, napi);\n+\tstruct device *dev = enet->dev;\n+\tint handled = 0;\n+\n+\twhile (handled < weight) {\n+\t\tstruct bcm4908_enet_dma_ring_bd *buf_desc;\n+\t\tstruct bcm4908_enet_dma_ring_slot slot;\n+\t\tu32 ctl;\n+\t\tint len;\n+\t\tint err;\n+\n+\t\tbuf_desc = &enet->rx_ring.buf_desc[enet->rx_ring.read_idx];\n+\t\tctl = le32_to_cpu(buf_desc->ctl);\n+\t\tif (ctl & DMA_CTL_STATUS_OWN)\n+\t\t\tbreak;\n+\n+\t\tslot = enet->rx_ring.slots[enet->rx_ring.read_idx];\n+\n+\t\t/* Provide new buffer before unpinning the old one */\n+\t\terr = bcm4908_enet_dma_alloc_rx_buf(enet, enet->rx_ring.read_idx);\n+\t\tif (err)\n+\t\t\tbreak;\n+\n+\t\tif (++enet->rx_ring.read_idx == enet->rx_ring.length)\n+\t\t\tenet->rx_ring.read_idx = 0;\n+\n+\t\tlen = (ctl & DMA_CTL_LEN_DESC_BUFLENGTH) >> DMA_CTL_LEN_DESC_BUFLENGTH_SHIFT;\n+\n+\t\tif (len < ENET_MTU_MIN ||\n+\t\t    (ctl & (DMA_CTL_STATUS_SOP | DMA_CTL_STATUS_EOP)) != (DMA_CTL_STATUS_SOP | DMA_CTL_STATUS_EOP)) {\n+\t\t\tenet->netdev->stats.rx_dropped++;\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\tdma_unmap_single(dev, slot.dma_addr, slot.len, DMA_FROM_DEVICE);\n+\n+\t\tskb_put(slot.skb, len - 4 + 2);\n+\t\tslot.skb->protocol = eth_type_trans(slot.skb, enet->netdev);\n+\t\tnetif_receive_skb(slot.skb);\n+\n+\t\tenet->netdev->stats.rx_packets++;\n+\t\tenet->netdev->stats.rx_bytes += len;\n+\t}\n+\n+\tif (handled < weight) {\n+\t\tnapi_complete_done(napi, handled);\n+\t\tbcm4908_enet_intrs_on(enet);\n+\t}\n+\n+\treturn handled;\n+}\n+\n+static const struct net_device_ops bcm96xx_netdev_ops = {\n+\t.ndo_open = bcm4908_enet_open,\n+\t.ndo_stop = bcm4908_enet_stop,\n+\t.ndo_start_xmit = bcm4908_enet_start_xmit,\n+\t.ndo_set_mac_address = eth_mac_addr,\n+};\n+\n+static int bcm4908_enet_probe(struct platform_device *pdev)\n+{\n+\tstruct device *dev = &pdev->dev;\n+\tstruct net_device *netdev;\n+\tstruct bcm4908_enet *enet;\n+\tint err;\n+\n+\tnetdev = devm_alloc_etherdev(dev, sizeof(*enet));\n+\tif (!netdev)\n+\t\treturn -ENOMEM;\n+\n+\tenet = netdev_priv(netdev);\n+\tenet->dev = dev;\n+\tenet->netdev = netdev;\n+\n+\tenet->base = devm_platform_ioremap_resource(pdev, 0);\n+\tif (IS_ERR(enet->base)) {\n+\t\tdev_err(dev, \"Failed to map registers: %ld\\n\", PTR_ERR(enet->base));\n+\t\treturn PTR_ERR(enet->base);\n+\t}\n+\n+\tnetdev->irq = platform_get_irq_byname(pdev, \"rx\");\n+\tif (netdev->irq < 0)\n+\t\treturn netdev->irq;\n+\n+\tdma_set_coherent_mask(dev, DMA_BIT_MASK(32));\n+\n+\terr = bcm4908_enet_dma_alloc(enet);\n+\tif (err)\n+\t\treturn err;\n+\n+\tSET_NETDEV_DEV(netdev, &pdev->dev);\n+\teth_hw_addr_random(netdev);\n+\tnetdev->netdev_ops = &bcm96xx_netdev_ops;\n+\tnetdev->min_mtu = ETH_ZLEN;\n+\tnetdev->mtu = ENET_MTU_MAX;\n+\tnetdev->max_mtu = ENET_MTU_MAX;\n+\tnetif_napi_add(netdev, &enet->napi, bcm4908_enet_poll, 64);\n+\n+\terr = register_netdev(netdev);\n+\tif (err) {\n+\t\tbcm4908_enet_dma_free(enet);\n+\t\treturn err;\n+\t}\n+\n+\tplatform_set_drvdata(pdev, enet);\n+\n+\treturn 0;\n+}\n+\n+static int bcm4908_enet_remove(struct platform_device *pdev)\n+{\n+\tstruct bcm4908_enet *enet = platform_get_drvdata(pdev);\n+\n+\tunregister_netdev(enet->netdev);\n+\tnetif_napi_del(&enet->napi);\n+\tbcm4908_enet_dma_free(enet);\n+\n+\treturn 0;\n+}\n+\n+static const struct of_device_id bcm4908_enet_of_match[] = {\n+\t{ .compatible = \"brcm,bcm4908-enet\"},\n+\t{},\n+};\n+\n+static struct platform_driver bcm4908_enet_driver = {\n+\t.driver = {\n+\t\t.name = \"bcm4908_enet\",\n+\t\t.of_match_table = bcm4908_enet_of_match,\n+\t},\n+\t.probe\t= bcm4908_enet_probe,\n+\t.remove = bcm4908_enet_remove,\n+};\n+module_platform_driver(bcm4908_enet_driver);\n+\n+MODULE_LICENSE(\"GPL v2\");\n+MODULE_DEVICE_TABLE(of, bcm4908_enet_of_match);\n--- a/drivers/net/ethernet/broadcom/bcm4908enet.h\n+++ /dev/null\n@@ -1,96 +0,0 @@\n-/* SPDX-License-Identifier: GPL-2.0-only */\n-#ifndef __BCM4908ENET_H\n-#define __BCM4908ENET_H\n-\n-#define ENET_CONTROL\t\t\t\t\t0x000\n-#define ENET_MIB_CTRL\t\t\t\t\t0x004\n-#define  ENET_MIB_CTRL_CLR_MIB\t\t\t\t0x00000001\n-#define ENET_RX_ERR_MASK\t\t\t\t0x008\n-#define ENET_MIB_MAX_PKT_SIZE\t\t\t\t0x00C\n-#define  ENET_MIB_MAX_PKT_SIZE_VAL\t\t\t0x00003fff\n-#define ENET_DIAG_OUT\t\t\t\t\t0x01c\n-#define ENET_ENABLE_DROP_PKT\t\t\t\t0x020\n-#define ENET_IRQ_ENABLE\t\t\t\t\t0x024\n-#define  ENET_IRQ_ENABLE_OVFL\t\t\t\t0x00000001\n-#define ENET_GMAC_STATUS\t\t\t\t0x028\n-#define  ENET_GMAC_STATUS_ETH_SPEED_MASK\t\t0x00000003\n-#define  ENET_GMAC_STATUS_ETH_SPEED_10\t\t\t0x00000000\n-#define  ENET_GMAC_STATUS_ETH_SPEED_100\t\t\t0x00000001\n-#define  ENET_GMAC_STATUS_ETH_SPEED_1000\t\t0x00000002\n-#define  ENET_GMAC_STATUS_HD\t\t\t\t0x00000004\n-#define  ENET_GMAC_STATUS_AUTO_CFG_EN\t\t\t0x00000008\n-#define  ENET_GMAC_STATUS_LINK_UP\t\t\t0x00000010\n-#define ENET_IRQ_STATUS\t\t\t\t\t0x02c\n-#define  ENET_IRQ_STATUS_OVFL\t\t\t\t0x00000001\n-#define ENET_OVERFLOW_COUNTER\t\t\t\t0x030\n-#define ENET_FLUSH\t\t\t\t\t0x034\n-#define  ENET_FLUSH_RXFIFO_FLUSH\t\t\t0x00000001\n-#define  ENET_FLUSH_TXFIFO_FLUSH\t\t\t0x00000002\n-#define ENET_RSV_SELECT\t\t\t\t\t0x038\n-#define ENET_BP_FORCE\t\t\t\t\t0x03c\n-#define  ENET_BP_FORCE_FORCE\t\t\t\t0x00000001\n-#define ENET_DMA_RX_OK_TO_SEND_COUNT\t\t\t0x040\n-#define  ENET_DMA_RX_OK_TO_SEND_COUNT_VAL\t\t0x0000000f\n-#define ENET_TX_CRC_CTRL\t\t\t\t0x044\n-#define ENET_MIB\t\t\t\t\t0x200\n-#define ENET_UNIMAC\t\t\t\t\t0x400\n-#define ENET_DMA\t\t\t\t\t0x800\n-#define ENET_DMA_CONTROLLER_CFG\t\t\t\t0x800\n-#define  ENET_DMA_CTRL_CFG_MASTER_EN\t\t\t0x00000001\n-#define  ENET_DMA_CTRL_CFG_FLOWC_CH1_EN\t\t\t0x00000002\n-#define  ENET_DMA_CTRL_CFG_FLOWC_CH3_EN\t\t\t0x00000004\n-#define ENET_DMA_FLOWCTL_CH1_THRESH_LO\t\t\t0x804\n-#define ENET_DMA_FLOWCTL_CH1_THRESH_HI\t\t\t0x808\n-#define ENET_DMA_FLOWCTL_CH1_ALLOC\t\t\t0x80c\n-#define  ENET_DMA_FLOWCTL_CH1_ALLOC_FORCE\t\t0x80000000\n-#define ENET_DMA_FLOWCTL_CH3_THRESH_LO\t\t\t0x810\n-#define ENET_DMA_FLOWCTL_CH3_THRESH_HI\t\t\t0x814\n-#define ENET_DMA_FLOWCTL_CH3_ALLOC\t\t\t0x818\n-#define ENET_DMA_FLOWCTL_CH5_THRESH_LO\t\t\t0x81C\n-#define ENET_DMA_FLOWCTL_CH5_THRESH_HI\t\t\t0x820\n-#define ENET_DMA_FLOWCTL_CH5_ALLOC\t\t\t0x824\n-#define ENET_DMA_FLOWCTL_CH7_THRESH_LO\t\t\t0x828\n-#define ENET_DMA_FLOWCTL_CH7_THRESH_HI\t\t\t0x82C\n-#define ENET_DMA_FLOWCTL_CH7_ALLOC\t\t\t0x830\n-#define ENET_DMA_CTRL_CHANNEL_RESET\t\t\t0x834\n-#define ENET_DMA_CTRL_CHANNEL_DEBUG\t\t\t0x838\n-#define ENET_DMA_CTRL_GLOBAL_INTERRUPT_STATUS\t\t0x840\n-#define ENET_DMA_CTRL_GLOBAL_INTERRUPT_MASK\t\t0x844\n-#define ENET_DMA_CH0_CFG\t\t\t\t0xa00\t\t/* RX */\n-#define ENET_DMA_CH1_CFG\t\t\t\t0xa10\t\t/* TX */\n-#define ENET_DMA_CH0_STATE_RAM\t\t\t\t0xc00\t\t/* RX */\n-#define ENET_DMA_CH1_STATE_RAM\t\t\t\t0xc10\t\t/* TX */\n-\n-#define ENET_DMA_CH_CFG\t\t\t\t\t0x00\t\t/* assorted configuration */\n-#define  ENET_DMA_CH_CFG_ENABLE\t\t\t\t0x00000001\t/* set to enable channel */\n-#define  ENET_DMA_CH_CFG_PKT_HALT\t\t\t0x00000002\t/* idle after an EOP flag is detected */\n-#define  ENET_DMA_CH_CFG_BURST_HALT\t\t\t0x00000004\t/* idle after finish current memory burst */\n-#define ENET_DMA_CH_CFG_INT_STAT\t\t\t0x04\t\t/* interrupts control and status */\n-#define ENET_DMA_CH_CFG_INT_MASK\t\t\t0x08\t\t/* interrupts mask */\n-#define  ENET_DMA_CH_CFG_INT_BUFF_DONE\t\t\t0x00000001\t/* buffer done */\n-#define  ENET_DMA_CH_CFG_INT_DONE\t\t\t0x00000002\t/* packet xfer complete */\n-#define  ENET_DMA_CH_CFG_INT_NO_DESC\t\t\t0x00000004\t/* no valid descriptors */\n-#define  ENET_DMA_CH_CFG_INT_RX_ERROR\t\t\t0x00000008\t/* rxdma detect client protocol error */\n-#define ENET_DMA_CH_CFG_MAX_BURST\t\t\t0x0c\t\t/* max burst length permitted */\n-#define  ENET_DMA_CH_CFG_MAX_BURST_DESCSIZE_SEL\t\t0x00040000\t/* DMA Descriptor Size Selection */\n-#define ENET_DMA_CH_CFG_SIZE\t\t\t\t0x10\n-\n-#define ENET_DMA_CH_STATE_RAM_BASE_DESC_PTR\t\t0x00\t\t/* descriptor ring start address */\n-#define ENET_DMA_CH_STATE_RAM_STATE_DATA\t\t0x04\t\t/* state/bytes done/ring offset */\n-#define ENET_DMA_CH_STATE_RAM_DESC_LEN_STATUS\t\t0x08\t\t/* buffer descriptor status and len */\n-#define ENET_DMA_CH_STATE_RAM_DESC_BASE_BUFPTR\t\t0x0c\t\t/* buffer descrpitor current processing */\n-#define ENET_DMA_CH_STATE_RAM_SIZE\t\t\t0x10\n-\n-#define DMA_CTL_STATUS_APPEND_CRC\t\t\t0x00000100\n-#define DMA_CTL_STATUS_APPEND_BRCM_TAG\t\t\t0x00000200\n-#define DMA_CTL_STATUS_PRIO\t\t\t\t0x00000C00  /* Prio for Tx */\n-#define DMA_CTL_STATUS_WRAP\t\t\t\t0x00001000  /* */\n-#define DMA_CTL_STATUS_SOP\t\t\t\t0x00002000  /* first buffer in packet */\n-#define DMA_CTL_STATUS_EOP\t\t\t\t0x00004000  /* last buffer in packet */\n-#define DMA_CTL_STATUS_OWN\t\t\t\t0x00008000  /* cleared by DMA, set by SW */\n-#define DMA_CTL_LEN_DESC_BUFLENGTH\t\t\t0x0fff0000\n-#define DMA_CTL_LEN_DESC_BUFLENGTH_SHIFT\t\t16\n-#define DMA_CTL_LEN_DESC_MULTICAST\t\t\t0x40000000\n-#define DMA_CTL_LEN_DESC_USEFPM\t\t\t\t0x80000000\n-\n-#endif\n--- /dev/null\n+++ b/drivers/net/ethernet/broadcom/bcm4908_enet.h\n@@ -0,0 +1,96 @@\n+/* SPDX-License-Identifier: GPL-2.0-only */\n+#ifndef __BCM4908_ENET_H\n+#define __BCM4908_ENET_H\n+\n+#define ENET_CONTROL\t\t\t\t\t0x000\n+#define ENET_MIB_CTRL\t\t\t\t\t0x004\n+#define  ENET_MIB_CTRL_CLR_MIB\t\t\t\t0x00000001\n+#define ENET_RX_ERR_MASK\t\t\t\t0x008\n+#define ENET_MIB_MAX_PKT_SIZE\t\t\t\t0x00C\n+#define  ENET_MIB_MAX_PKT_SIZE_VAL\t\t\t0x00003fff\n+#define ENET_DIAG_OUT\t\t\t\t\t0x01c\n+#define ENET_ENABLE_DROP_PKT\t\t\t\t0x020\n+#define ENET_IRQ_ENABLE\t\t\t\t\t0x024\n+#define  ENET_IRQ_ENABLE_OVFL\t\t\t\t0x00000001\n+#define ENET_GMAC_STATUS\t\t\t\t0x028\n+#define  ENET_GMAC_STATUS_ETH_SPEED_MASK\t\t0x00000003\n+#define  ENET_GMAC_STATUS_ETH_SPEED_10\t\t\t0x00000000\n+#define  ENET_GMAC_STATUS_ETH_SPEED_100\t\t\t0x00000001\n+#define  ENET_GMAC_STATUS_ETH_SPEED_1000\t\t0x00000002\n+#define  ENET_GMAC_STATUS_HD\t\t\t\t0x00000004\n+#define  ENET_GMAC_STATUS_AUTO_CFG_EN\t\t\t0x00000008\n+#define  ENET_GMAC_STATUS_LINK_UP\t\t\t0x00000010\n+#define ENET_IRQ_STATUS\t\t\t\t\t0x02c\n+#define  ENET_IRQ_STATUS_OVFL\t\t\t\t0x00000001\n+#define ENET_OVERFLOW_COUNTER\t\t\t\t0x030\n+#define ENET_FLUSH\t\t\t\t\t0x034\n+#define  ENET_FLUSH_RXFIFO_FLUSH\t\t\t0x00000001\n+#define  ENET_FLUSH_TXFIFO_FLUSH\t\t\t0x00000002\n+#define ENET_RSV_SELECT\t\t\t\t\t0x038\n+#define ENET_BP_FORCE\t\t\t\t\t0x03c\n+#define  ENET_BP_FORCE_FORCE\t\t\t\t0x00000001\n+#define ENET_DMA_RX_OK_TO_SEND_COUNT\t\t\t0x040\n+#define  ENET_DMA_RX_OK_TO_SEND_COUNT_VAL\t\t0x0000000f\n+#define ENET_TX_CRC_CTRL\t\t\t\t0x044\n+#define ENET_MIB\t\t\t\t\t0x200\n+#define ENET_UNIMAC\t\t\t\t\t0x400\n+#define ENET_DMA\t\t\t\t\t0x800\n+#define ENET_DMA_CONTROLLER_CFG\t\t\t\t0x800\n+#define  ENET_DMA_CTRL_CFG_MASTER_EN\t\t\t0x00000001\n+#define  ENET_DMA_CTRL_CFG_FLOWC_CH1_EN\t\t\t0x00000002\n+#define  ENET_DMA_CTRL_CFG_FLOWC_CH3_EN\t\t\t0x00000004\n+#define ENET_DMA_FLOWCTL_CH1_THRESH_LO\t\t\t0x804\n+#define ENET_DMA_FLOWCTL_CH1_THRESH_HI\t\t\t0x808\n+#define ENET_DMA_FLOWCTL_CH1_ALLOC\t\t\t0x80c\n+#define  ENET_DMA_FLOWCTL_CH1_ALLOC_FORCE\t\t0x80000000\n+#define ENET_DMA_FLOWCTL_CH3_THRESH_LO\t\t\t0x810\n+#define ENET_DMA_FLOWCTL_CH3_THRESH_HI\t\t\t0x814\n+#define ENET_DMA_FLOWCTL_CH3_ALLOC\t\t\t0x818\n+#define ENET_DMA_FLOWCTL_CH5_THRESH_LO\t\t\t0x81C\n+#define ENET_DMA_FLOWCTL_CH5_THRESH_HI\t\t\t0x820\n+#define ENET_DMA_FLOWCTL_CH5_ALLOC\t\t\t0x824\n+#define ENET_DMA_FLOWCTL_CH7_THRESH_LO\t\t\t0x828\n+#define ENET_DMA_FLOWCTL_CH7_THRESH_HI\t\t\t0x82C\n+#define ENET_DMA_FLOWCTL_CH7_ALLOC\t\t\t0x830\n+#define ENET_DMA_CTRL_CHANNEL_RESET\t\t\t0x834\n+#define ENET_DMA_CTRL_CHANNEL_DEBUG\t\t\t0x838\n+#define ENET_DMA_CTRL_GLOBAL_INTERRUPT_STATUS\t\t0x840\n+#define ENET_DMA_CTRL_GLOBAL_INTERRUPT_MASK\t\t0x844\n+#define ENET_DMA_CH0_CFG\t\t\t\t0xa00\t\t/* RX */\n+#define ENET_DMA_CH1_CFG\t\t\t\t0xa10\t\t/* TX */\n+#define ENET_DMA_CH0_STATE_RAM\t\t\t\t0xc00\t\t/* RX */\n+#define ENET_DMA_CH1_STATE_RAM\t\t\t\t0xc10\t\t/* TX */\n+\n+#define ENET_DMA_CH_CFG\t\t\t\t\t0x00\t\t/* assorted configuration */\n+#define  ENET_DMA_CH_CFG_ENABLE\t\t\t\t0x00000001\t/* set to enable channel */\n+#define  ENET_DMA_CH_CFG_PKT_HALT\t\t\t0x00000002\t/* idle after an EOP flag is detected */\n+#define  ENET_DMA_CH_CFG_BURST_HALT\t\t\t0x00000004\t/* idle after finish current memory burst */\n+#define ENET_DMA_CH_CFG_INT_STAT\t\t\t0x04\t\t/* interrupts control and status */\n+#define ENET_DMA_CH_CFG_INT_MASK\t\t\t0x08\t\t/* interrupts mask */\n+#define  ENET_DMA_CH_CFG_INT_BUFF_DONE\t\t\t0x00000001\t/* buffer done */\n+#define  ENET_DMA_CH_CFG_INT_DONE\t\t\t0x00000002\t/* packet xfer complete */\n+#define  ENET_DMA_CH_CFG_INT_NO_DESC\t\t\t0x00000004\t/* no valid descriptors */\n+#define  ENET_DMA_CH_CFG_INT_RX_ERROR\t\t\t0x00000008\t/* rxdma detect client protocol error */\n+#define ENET_DMA_CH_CFG_MAX_BURST\t\t\t0x0c\t\t/* max burst length permitted */\n+#define  ENET_DMA_CH_CFG_MAX_BURST_DESCSIZE_SEL\t\t0x00040000\t/* DMA Descriptor Size Selection */\n+#define ENET_DMA_CH_CFG_SIZE\t\t\t\t0x10\n+\n+#define ENET_DMA_CH_STATE_RAM_BASE_DESC_PTR\t\t0x00\t\t/* descriptor ring start address */\n+#define ENET_DMA_CH_STATE_RAM_STATE_DATA\t\t0x04\t\t/* state/bytes done/ring offset */\n+#define ENET_DMA_CH_STATE_RAM_DESC_LEN_STATUS\t\t0x08\t\t/* buffer descriptor status and len */\n+#define ENET_DMA_CH_STATE_RAM_DESC_BASE_BUFPTR\t\t0x0c\t\t/* buffer descrpitor current processing */\n+#define ENET_DMA_CH_STATE_RAM_SIZE\t\t\t0x10\n+\n+#define DMA_CTL_STATUS_APPEND_CRC\t\t\t0x00000100\n+#define DMA_CTL_STATUS_APPEND_BRCM_TAG\t\t\t0x00000200\n+#define DMA_CTL_STATUS_PRIO\t\t\t\t0x00000C00  /* Prio for Tx */\n+#define DMA_CTL_STATUS_WRAP\t\t\t\t0x00001000  /* */\n+#define DMA_CTL_STATUS_SOP\t\t\t\t0x00002000  /* first buffer in packet */\n+#define DMA_CTL_STATUS_EOP\t\t\t\t0x00004000  /* last buffer in packet */\n+#define DMA_CTL_STATUS_OWN\t\t\t\t0x00008000  /* cleared by DMA, set by SW */\n+#define DMA_CTL_LEN_DESC_BUFLENGTH\t\t\t0x0fff0000\n+#define DMA_CTL_LEN_DESC_BUFLENGTH_SHIFT\t\t16\n+#define DMA_CTL_LEN_DESC_MULTICAST\t\t\t0x40000000\n+#define DMA_CTL_LEN_DESC_USEFPM\t\t\t\t0x80000000\n+\n+#endif\n"
  },
  {
    "path": "target/linux/bcm4908/patches-5.10/073-v5.12-0004-net-broadcom-bcm4908_enet-drop-unneeded-memset.patch",
    "content": "From af263af64683f018be9ce3c309edfa9903f5109a Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Thu, 11 Feb 2021 13:12:35 +0100\nSubject: [PATCH] net: broadcom: bcm4908_enet: drop unneeded memset()\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\ndma_alloc_coherent takes care of zeroing allocated memory\n\nSuggested-by: Andrew Lunn <andrew@lunn.ch>\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nReviewed-by: Andrew Lunn <andrew@lunn.ch>\nReviewed-by: Florian Fainelli <f.fainelli@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/ethernet/broadcom/bcm4908_enet.c | 2 --\n 1 file changed, 2 deletions(-)\n\n--- a/drivers/net/ethernet/broadcom/bcm4908_enet.c\n+++ b/drivers/net/ethernet/broadcom/bcm4908_enet.c\n@@ -163,8 +163,6 @@ static int bcm4908_dma_alloc_buf_descs(s\n \tif (!ring->slots)\n \t\tgoto err_free_buf_descs;\n \n-\tmemset(ring->cpu_addr, 0, size);\n-\n \tring->read_idx = 0;\n \tring->write_idx = 0;\n \n"
  },
  {
    "path": "target/linux/bcm4908/patches-5.10/073-v5.12-0005-net-broadcom-bcm4908_enet-drop-inline-from-C-functio.patch",
    "content": "From 7b778ae4eb9cd6e1518e4e47902a104b13ae8929 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Thu, 11 Feb 2021 13:12:36 +0100\nSubject: [PATCH] net: broadcom: bcm4908_enet: drop \"inline\" from C functions\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nIt seems preferred to let compiler optimize code if applicable.\nWhile at it drop unused enet_umac_maskset().\n\nSuggested-by: Andrew Lunn <andrew@lunn.ch>\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nReviewed-by: Andrew Lunn <andrew@lunn.ch>\nReviewed-by: Florian Fainelli <f.fainelli@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/ethernet/broadcom/bcm4908_enet.c | 19 +++++++------------\n 1 file changed, 7 insertions(+), 12 deletions(-)\n\n--- a/drivers/net/ethernet/broadcom/bcm4908_enet.c\n+++ b/drivers/net/ethernet/broadcom/bcm4908_enet.c\n@@ -75,17 +75,17 @@ struct bcm4908_enet {\n  * R/W ops\n  */\n \n-static inline u32 enet_read(struct bcm4908_enet *enet, u16 offset)\n+static u32 enet_read(struct bcm4908_enet *enet, u16 offset)\n {\n \treturn readl(enet->base + offset);\n }\n \n-static inline void enet_write(struct bcm4908_enet *enet, u16 offset, u32 value)\n+static void enet_write(struct bcm4908_enet *enet, u16 offset, u32 value)\n {\n \twritel(value, enet->base + offset);\n }\n \n-static inline void enet_maskset(struct bcm4908_enet *enet, u16 offset, u32 mask, u32 set)\n+static void enet_maskset(struct bcm4908_enet *enet, u16 offset, u32 mask, u32 set)\n {\n \tu32 val;\n \n@@ -96,27 +96,22 @@ static inline void enet_maskset(struct b\n \tenet_write(enet, offset, val);\n }\n \n-static inline void enet_set(struct bcm4908_enet *enet, u16 offset, u32 set)\n+static void enet_set(struct bcm4908_enet *enet, u16 offset, u32 set)\n {\n \tenet_maskset(enet, offset, set, set);\n }\n \n-static inline u32 enet_umac_read(struct bcm4908_enet *enet, u16 offset)\n+static u32 enet_umac_read(struct bcm4908_enet *enet, u16 offset)\n {\n \treturn enet_read(enet, ENET_UNIMAC + offset);\n }\n \n-static inline void enet_umac_write(struct bcm4908_enet *enet, u16 offset, u32 value)\n+static void enet_umac_write(struct bcm4908_enet *enet, u16 offset, u32 value)\n {\n \tenet_write(enet, ENET_UNIMAC + offset, value);\n }\n \n-static inline void enet_umac_maskset(struct bcm4908_enet *enet, u16 offset, u32 mask, u32 set)\n-{\n-\tenet_maskset(enet, ENET_UNIMAC + offset, mask, set);\n-}\n-\n-static inline void enet_umac_set(struct bcm4908_enet *enet, u16 offset, u32 set)\n+static void enet_umac_set(struct bcm4908_enet *enet, u16 offset, u32 set)\n {\n \tenet_set(enet, ENET_UNIMAC + offset, set);\n }\n"
  },
  {
    "path": "target/linux/bcm4908/patches-5.10/073-v5.12-0006-net-broadcom-bcm4908_enet-fix-minor-typos.patch",
    "content": "From e3948811720341f99cd5cb4a8a650473400ec4f8 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Thu, 11 Feb 2021 13:12:37 +0100\nSubject: [PATCH] net: broadcom: bcm4908_enet: fix minor typos\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\n1. Fix \"ensable\" typo noticed by Andrew\n2. Fix chipset name in the struct net_device_ops variable\n\nSuggested-by: Andrew Lunn <andrew@lunn.ch>\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nReviewed-by: Andrew Lunn <andrew@lunn.ch>\nReviewed-by: Florian Fainelli <f.fainelli@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/ethernet/broadcom/bcm4908_enet.c | 10 +++++-----\n 1 file changed, 5 insertions(+), 5 deletions(-)\n\n--- a/drivers/net/ethernet/broadcom/bcm4908_enet.c\n+++ b/drivers/net/ethernet/broadcom/bcm4908_enet.c\n@@ -328,8 +328,8 @@ static int bcm4908_enet_dma_init(struct\n \treturn 0;\n }\n \n-static void bcm4908_enet_dma_tx_ring_ensable(struct bcm4908_enet *enet,\n-\t\t\t\t\t     struct bcm4908_enet_dma_ring *ring)\n+static void bcm4908_enet_dma_tx_ring_enable(struct bcm4908_enet *enet,\n+\t\t\t\t\t    struct bcm4908_enet_dma_ring *ring)\n {\n \tenet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG, ENET_DMA_CH_CFG_ENABLE);\n }\n@@ -519,7 +519,7 @@ static int bcm4908_enet_start_xmit(struc\n \tbuf_desc->addr = cpu_to_le32((uint32_t)slot->dma_addr);\n \tbuf_desc->ctl = cpu_to_le32(tmp);\n \n-\tbcm4908_enet_dma_tx_ring_ensable(enet, &enet->tx_ring);\n+\tbcm4908_enet_dma_tx_ring_enable(enet, &enet->tx_ring);\n \n \tif (++ring->write_idx == ring->length - 1)\n \t\tring->write_idx = 0;\n@@ -583,7 +583,7 @@ static int bcm4908_enet_poll(struct napi\n \treturn handled;\n }\n \n-static const struct net_device_ops bcm96xx_netdev_ops = {\n+static const struct net_device_ops bcm4908_enet_netdev_ops = {\n \t.ndo_open = bcm4908_enet_open,\n \t.ndo_stop = bcm4908_enet_stop,\n \t.ndo_start_xmit = bcm4908_enet_start_xmit,\n@@ -623,7 +623,7 @@ static int bcm4908_enet_probe(struct pla\n \n \tSET_NETDEV_DEV(netdev, &pdev->dev);\n \teth_hw_addr_random(netdev);\n-\tnetdev->netdev_ops = &bcm96xx_netdev_ops;\n+\tnetdev->netdev_ops = &bcm4908_enet_netdev_ops;\n \tnetdev->min_mtu = ETH_ZLEN;\n \tnetdev->mtu = ENET_MTU_MAX;\n \tnetdev->max_mtu = ENET_MTU_MAX;\n"
  },
  {
    "path": "target/linux/bcm4908/patches-5.10/073-v5.12-0007-net-broadcom-bcm4908_enet-fix-received-skb-length.patch",
    "content": "From 195e2d9febfbeef1d09701c387925e5c2f5cb038 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Thu, 11 Feb 2021 13:12:38 +0100\nSubject: [PATCH] net: broadcom: bcm4908_enet: fix received skb length\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nUse ETH_FCS_LEN instead of magic value and drop incorrect + 2\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nReviewed-by: Florian Fainelli <f.fainelli@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/ethernet/broadcom/bcm4908_enet.c | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/drivers/net/ethernet/broadcom/bcm4908_enet.c\n+++ b/drivers/net/ethernet/broadcom/bcm4908_enet.c\n@@ -567,7 +567,7 @@ static int bcm4908_enet_poll(struct napi\n \n \t\tdma_unmap_single(dev, slot.dma_addr, slot.len, DMA_FROM_DEVICE);\n \n-\t\tskb_put(slot.skb, len - 4 + 2);\n+\t\tskb_put(slot.skb, len - ETH_FCS_LEN);\n \t\tslot.skb->protocol = eth_type_trans(slot.skb, enet->netdev);\n \t\tnetif_receive_skb(slot.skb);\n \n"
  },
  {
    "path": "target/linux/bcm4908/patches-5.10/073-v5.12-0008-net-broadcom-bcm4908_enet-fix-endianness-in-xmit-cod.patch",
    "content": "From bdd70b997799099597fc0952fb0ec1bd80505bc4 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Thu, 11 Feb 2021 13:12:39 +0100\nSubject: [PATCH] net: broadcom: bcm4908_enet: fix endianness in xmit code\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nUse le32_to_cpu() for reading __le32 struct field filled by hw.\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nReviewed-by: Florian Fainelli <f.fainelli@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/ethernet/broadcom/bcm4908_enet.c | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/drivers/net/ethernet/broadcom/bcm4908_enet.c\n+++ b/drivers/net/ethernet/broadcom/bcm4908_enet.c\n@@ -476,7 +476,7 @@ static int bcm4908_enet_start_xmit(struc\n \t/* Free transmitted skbs */\n \twhile (ring->read_idx != ring->write_idx) {\n \t\tbuf_desc = &ring->buf_desc[ring->read_idx];\n-\t\tif (buf_desc->ctl & DMA_CTL_STATUS_OWN)\n+\t\tif (le32_to_cpu(buf_desc->ctl) & DMA_CTL_STATUS_OWN)\n \t\t\tbreak;\n \t\tslot = &ring->slots[ring->read_idx];\n \n"
  },
  {
    "path": "target/linux/bcm4908/patches-5.10/073-v5.12-0009-net-broadcom-bcm4908_enet-set-MTU-on-open-on-request.patch",
    "content": "From 14b3b46a67f78ade99eafcbf320105615e948569 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Fri, 12 Feb 2021 16:21:35 +0100\nSubject: [PATCH] net: broadcom: bcm4908_enet: set MTU on open & on request\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nHardware comes up with default max frame size set to 1518. When using it\nwith switch it results in actual Ethernet MTU 1492:\n1518 - 14 (Ethernet header) - 4 (Broadcom's tag) - 4 (802.1q) - 4 (FCS)\n\nAbove means hardware in its default state can't handle standard Ethernet\ntraffic (MTU 1500).\n\nDefine maximum possible Ethernet overhead and always set MAC max frame\nlength accordingly. This change fixes handling Ethernet frames of length\n1506 - 1514.\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/ethernet/broadcom/bcm4908_enet.c | 31 ++++++++++++++++----\n 1 file changed, 25 insertions(+), 6 deletions(-)\n\n--- a/drivers/net/ethernet/broadcom/bcm4908_enet.c\n+++ b/drivers/net/ethernet/broadcom/bcm4908_enet.c\n@@ -5,6 +5,7 @@\n \n #include <linux/delay.h>\n #include <linux/etherdevice.h>\n+#include <linux/if_vlan.h>\n #include <linux/interrupt.h>\n #include <linux/module.h>\n #include <linux/of.h>\n@@ -29,9 +30,10 @@\n \t\t\t\t\t\t ENET_DMA_CH_CFG_INT_BUFF_DONE)\n #define ENET_DMA_MAX_BURST_LEN\t\t\t8 /* in 64 bit words */\n \n-#define ENET_MTU_MIN\t\t\t\t60\n-#define ENET_MTU_MAX\t\t\t\t1500 /* Is it possible to support 2044? */\n-#define ENET_MTU_MAX_EXTRA_SIZE\t\t\t32 /* L2 */\n+#define ENET_MTU_MAX\t\t\t\tETH_DATA_LEN /* Is it possible to support 2044? */\n+#define BRCM_MAX_TAG_LEN\t\t\t6\n+#define ENET_MAX_ETH_OVERHEAD\t\t\t(ETH_HLEN + BRCM_MAX_TAG_LEN + VLAN_HLEN + \\\n+\t\t\t\t\t\t ETH_FCS_LEN + 4) /* 32 */\n \n struct bcm4908_enet_dma_ring_bd {\n \t__le32 ctl;\n@@ -135,6 +137,11 @@ static void bcm4908_enet_intrs_ack(struc\n \tenet_write(enet, ENET_DMA_CH_RX_CFG + ENET_DMA_CH_CFG_INT_STAT, ENET_DMA_INT_DEFAULTS);\n }\n \n+static void bcm4908_enet_set_mtu(struct bcm4908_enet *enet, int mtu)\n+{\n+\tenet_umac_write(enet, UMAC_MAX_FRAME_LEN, mtu + ENET_MAX_ETH_OVERHEAD);\n+}\n+\n /***\n  * DMA\n  */\n@@ -246,7 +253,7 @@ static int bcm4908_enet_dma_alloc_rx_buf\n \tu32 tmp;\n \tint err;\n \n-\tslot->len = ENET_MTU_MAX + ENET_MTU_MAX_EXTRA_SIZE;\n+\tslot->len = ENET_MTU_MAX + ENET_MAX_ETH_OVERHEAD;\n \n \tslot->skb = netdev_alloc_skb(enet->netdev, slot->len);\n \tif (!slot->skb)\n@@ -374,6 +381,8 @@ static void bcm4908_enet_gmac_init(struc\n {\n \tu32 cmd;\n \n+\tbcm4908_enet_set_mtu(enet, enet->netdev->mtu);\n+\n \tcmd = enet_umac_read(enet, UMAC_CMD);\n \tenet_umac_write(enet, UMAC_CMD, cmd | CMD_SW_RESET);\n \tenet_umac_write(enet, UMAC_CMD, cmd & ~CMD_SW_RESET);\n@@ -559,7 +568,7 @@ static int bcm4908_enet_poll(struct napi\n \n \t\tlen = (ctl & DMA_CTL_LEN_DESC_BUFLENGTH) >> DMA_CTL_LEN_DESC_BUFLENGTH_SHIFT;\n \n-\t\tif (len < ENET_MTU_MIN ||\n+\t\tif (len < ETH_ZLEN ||\n \t\t    (ctl & (DMA_CTL_STATUS_SOP | DMA_CTL_STATUS_EOP)) != (DMA_CTL_STATUS_SOP | DMA_CTL_STATUS_EOP)) {\n \t\t\tenet->netdev->stats.rx_dropped++;\n \t\t\tbreak;\n@@ -583,11 +592,21 @@ static int bcm4908_enet_poll(struct napi\n \treturn handled;\n }\n \n+static int bcm4908_enet_change_mtu(struct net_device *netdev, int new_mtu)\n+{\n+\tstruct bcm4908_enet *enet = netdev_priv(netdev);\n+\n+\tbcm4908_enet_set_mtu(enet, new_mtu);\n+\n+\treturn 0;\n+}\n+\n static const struct net_device_ops bcm4908_enet_netdev_ops = {\n \t.ndo_open = bcm4908_enet_open,\n \t.ndo_stop = bcm4908_enet_stop,\n \t.ndo_start_xmit = bcm4908_enet_start_xmit,\n \t.ndo_set_mac_address = eth_mac_addr,\n+\t.ndo_change_mtu = bcm4908_enet_change_mtu,\n };\n \n static int bcm4908_enet_probe(struct platform_device *pdev)\n@@ -625,7 +644,7 @@ static int bcm4908_enet_probe(struct pla\n \teth_hw_addr_random(netdev);\n \tnetdev->netdev_ops = &bcm4908_enet_netdev_ops;\n \tnetdev->min_mtu = ETH_ZLEN;\n-\tnetdev->mtu = ENET_MTU_MAX;\n+\tnetdev->mtu = ETH_DATA_LEN;\n \tnetdev->max_mtu = ENET_MTU_MAX;\n \tnetif_napi_add(netdev, &enet->napi, bcm4908_enet_poll, 64);\n \n"
  },
  {
    "path": "target/linux/bcm4908/patches-5.10/073-v5.12-0010-net-broadcom-bcm4908_enet-fix-RX-path-possible-mem-l.patch",
    "content": "From 4dc7f09b8becfa35a55430a49d95acf19f996e6b Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Wed, 24 Feb 2021 16:18:41 +0100\nSubject: [PATCH] net: broadcom: bcm4908_enet: fix RX path possible mem leak\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nAfter filling RX ring slot with new skb it's required to free old skb.\nImmediately on error or later in the net subsystem.\n\nFixes: 4feffeadbcb2 (\"net: broadcom: bcm4908enet: add BCM4908 controller driver\")\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nAcked-by: Florian Fainelli <f.fainelli@gmail.com>\nLink: https://lore.kernel.org/r/20210224151842.2419-1-zajec5@gmail.com\nSigned-off-by: Jakub Kicinski <kuba@kernel.org>\n---\n drivers/net/ethernet/broadcom/bcm4908_enet.c | 1 +\n 1 file changed, 1 insertion(+)\n\n--- a/drivers/net/ethernet/broadcom/bcm4908_enet.c\n+++ b/drivers/net/ethernet/broadcom/bcm4908_enet.c\n@@ -570,6 +570,7 @@ static int bcm4908_enet_poll(struct napi\n \n \t\tif (len < ETH_ZLEN ||\n \t\t    (ctl & (DMA_CTL_STATUS_SOP | DMA_CTL_STATUS_EOP)) != (DMA_CTL_STATUS_SOP | DMA_CTL_STATUS_EOP)) {\n+\t\t\tkfree_skb(slot.skb);\n \t\t\tenet->netdev->stats.rx_dropped++;\n \t\t\tbreak;\n \t\t}\n"
  },
  {
    "path": "target/linux/bcm4908/patches-5.10/073-v5.12-0011-net-broadcom-bcm4908_enet-fix-NAPI-poll-returned-val.patch",
    "content": "From 4d9274cee40b6a20dd6148c6c81c6733c2678cbc Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Wed, 24 Feb 2021 16:18:42 +0100\nSubject: [PATCH] net: broadcom: bcm4908_enet: fix NAPI poll returned value\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nMissing increment was resulting in poll function always returning 0\ninstead of amount of processed packets.\n\nFixes: 4feffeadbcb2 (\"net: broadcom: bcm4908enet: add BCM4908 controller driver\")\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nAcked-by: Florian Fainelli <f.fainelli@gmail.com>\nLink: https://lore.kernel.org/r/20210224151842.2419-2-zajec5@gmail.com\nSigned-off-by: Jakub Kicinski <kuba@kernel.org>\n---\n drivers/net/ethernet/broadcom/bcm4908_enet.c | 2 ++\n 1 file changed, 2 insertions(+)\n\n--- a/drivers/net/ethernet/broadcom/bcm4908_enet.c\n+++ b/drivers/net/ethernet/broadcom/bcm4908_enet.c\n@@ -583,6 +583,8 @@ static int bcm4908_enet_poll(struct napi\n \n \t\tenet->netdev->stats.rx_packets++;\n \t\tenet->netdev->stats.rx_bytes += len;\n+\n+\t\thandled++;\n \t}\n \n \tif (handled < weight) {\n"
  },
  {
    "path": "target/linux/bcm4908/patches-5.10/073-v5.12-0012-net-broadcom-bcm4908_enet-enable-RX-after-processing.patch",
    "content": "From d313d16bbaea0f11a2e98f04a6c678b43c208915 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Fri, 26 Feb 2021 14:20:38 +0100\nSubject: [PATCH] net: broadcom: bcm4908_enet: enable RX after processing\n packets\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nWhen receiving a lot of packets hardware may run out of free\ndescriptiors and stop RX ring. Enable it every time after handling\nreceived packets.\n\nFixes: 4feffeadbcb2 (\"net: broadcom: bcm4908enet: add BCM4908 controller driver\")\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nAcked-by: Florian Fainelli <f.fainelli@gmail.com>\nLink: https://lore.kernel.org/r/20210226132038.29849-1-zajec5@gmail.com\nSigned-off-by: Jakub Kicinski <kuba@kernel.org>\n---\n drivers/net/ethernet/broadcom/bcm4908_enet.c | 3 +++\n 1 file changed, 3 insertions(+)\n\n--- a/drivers/net/ethernet/broadcom/bcm4908_enet.c\n+++ b/drivers/net/ethernet/broadcom/bcm4908_enet.c\n@@ -592,6 +592,9 @@ static int bcm4908_enet_poll(struct napi\n \t\tbcm4908_enet_intrs_on(enet);\n \t}\n \n+\t/* Hardware could disable ring if it run out of descriptors */\n+\tbcm4908_enet_dma_rx_ring_enable(enet, &enet->rx_ring);\n+\n \treturn handled;\n }\n \n"
  },
  {
    "path": "target/linux/bcm4908/patches-5.10/073-v5.12-0013-net-broadcom-BCM4908_ENET-should-not-default-to-y-un.patch",
    "content": "From a3bc483216650a7232559bf0a1debfbabff3e12c Mon Sep 17 00:00:00 2001\nFrom: Geert Uytterhoeven <geert+renesas@glider.be>\nDate: Tue, 16 Mar 2021 15:03:41 +0100\nSubject: [PATCH] net: broadcom: BCM4908_ENET should not default to y,\n unconditionally\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nMerely enabling compile-testing should not enable additional code.\nTo fix this, restrict the automatic enabling of BCM4908_ENET to\nARCH_BCM4908.\n\nFixes: 4feffeadbcb2e5b1 (\"net: broadcom: bcm4908enet: add BCM4908 controller driver\")\nSigned-off-by: Geert Uytterhoeven <geert+renesas@glider.be>\nAcked-by: Florian Fainelli <f.fainelli@gmail.com>\nAcked-by: Rafał Miłecki <rafal@milecki.pl>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/ethernet/broadcom/Kconfig | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/drivers/net/ethernet/broadcom/Kconfig\n+++ b/drivers/net/ethernet/broadcom/Kconfig\n@@ -54,7 +54,7 @@ config B44_PCI\n config BCM4908_ENET\n \ttristate \"Broadcom BCM4908 internal mac support\"\n \tdepends on ARCH_BCM4908 || COMPILE_TEST\n-\tdefault y\n+\tdefault y if ARCH_BCM4908\n \thelp\n \t  This driver supports Ethernet controller integrated into Broadcom\n \t  BCM4908 family SoCs.\n"
  },
  {
    "path": "target/linux/bcm4908/patches-5.10/074-v5.13-0001-net-broadcom-bcm4908_enet-read-MAC-from-OF.patch",
    "content": "From 3559c1ea4336636c886002996d50805365d3055c Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Wed, 10 Mar 2021 09:48:13 +0100\nSubject: [PATCH] net: broadcom: bcm4908_enet: read MAC from OF\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nBCM4908 devices have MAC address accessible using NVMEM so it's needed\nto use OF helper for reading it.\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/ethernet/broadcom/bcm4908_enet.c | 8 +++++++-\n 1 file changed, 7 insertions(+), 1 deletion(-)\n\n--- a/drivers/net/ethernet/broadcom/bcm4908_enet.c\n+++ b/drivers/net/ethernet/broadcom/bcm4908_enet.c\n@@ -9,6 +9,7 @@\n #include <linux/interrupt.h>\n #include <linux/module.h>\n #include <linux/of.h>\n+#include <linux/of_net.h>\n #include <linux/platform_device.h>\n #include <linux/slab.h>\n #include <linux/string.h>\n@@ -647,7 +648,9 @@ static int bcm4908_enet_probe(struct pla\n \t\treturn err;\n \n \tSET_NETDEV_DEV(netdev, &pdev->dev);\n-\teth_hw_addr_random(netdev);\n+\tof_get_mac_address(dev->of_node, netdev->dev_addr);\n+\tif (!is_valid_ether_addr(netdev->dev_addr))\n+\t\teth_hw_addr_random(netdev);\n \tnetdev->netdev_ops = &bcm4908_enet_netdev_ops;\n \tnetdev->min_mtu = ETH_ZLEN;\n \tnetdev->mtu = ETH_DATA_LEN;\n"
  },
  {
    "path": "target/linux/bcm4908/patches-5.10/074-v5.13-0002-dt-bindings-net-bcm4908-enet-add-optional-TX-interru.patch",
    "content": "From ab4dda7a8cb7e55ea3d92fd5e249cf6f5396028c Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Thu, 11 Mar 2021 13:35:20 +0100\nSubject: [PATCH] dt-bindings: net: bcm4908-enet: add optional TX interrupt\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nI discovered that hardware actually supports two interrupts, one per DMA\nchannel (RX and TX).\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n .../bindings/net/brcm,bcm4908-enet.yaml         | 17 +++++++++++++----\n 1 file changed, 13 insertions(+), 4 deletions(-)\n\n--- a/Documentation/devicetree/bindings/net/brcm,bcm4908-enet.yaml\n+++ b/Documentation/devicetree/bindings/net/brcm,bcm4908-enet.yaml\n@@ -22,10 +22,18 @@ properties:\n     maxItems: 1\n \n   interrupts:\n-    description: RX interrupt\n+    minItems: 1\n+    maxItems: 2\n+    items:\n+      - description: RX interrupt\n+      - description: TX interrupt\n \n   interrupt-names:\n-    const: rx\n+    minItems: 1\n+    maxItems: 2\n+    items:\n+      - const: rx\n+      - const: tx\n \n required:\n   - reg\n@@ -43,6 +51,7 @@ examples:\n         compatible = \"brcm,bcm4908-enet\";\n         reg = <0x80002000 0x1000>;\n \n-        interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;\n-        interrupt-names = \"rx\";\n+        interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,\n+                     <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;\n+        interrupt-names = \"rx\", \"tx\";\n     };\n"
  },
  {
    "path": "target/linux/bcm4908/patches-5.10/074-v5.13-0003-net-broadcom-bcm4908_enet-support-TX-interrupt.patch",
    "content": "From 12bb508bfe5a564c36864b12253db23cac83bfa1 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Thu, 11 Mar 2021 13:35:21 +0100\nSubject: [PATCH] net: broadcom: bcm4908_enet: support TX interrupt\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nIt appears that each DMA channel has its own interrupt and both rings\ncan be configured (the same way) to handle interrupts.\n\n1. Make ring interrupts code generic (make it operate on given ring)\n2. Move napi to ring (so each has its own)\n3. Make IRQ handler generic (match ring against received IRQ number)\n4. Add (optional) support for TX interrupt\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/ethernet/broadcom/bcm4908_enet.c | 138 ++++++++++++++-----\n 1 file changed, 103 insertions(+), 35 deletions(-)\n\n--- a/drivers/net/ethernet/broadcom/bcm4908_enet.c\n+++ b/drivers/net/ethernet/broadcom/bcm4908_enet.c\n@@ -54,6 +54,7 @@ struct bcm4908_enet_dma_ring {\n \tint length;\n \tu16 cfg_block;\n \tu16 st_ram_block;\n+\tstruct napi_struct napi;\n \n \tunion {\n \t\tvoid *cpu_addr;\n@@ -67,8 +68,8 @@ struct bcm4908_enet_dma_ring {\n struct bcm4908_enet {\n \tstruct device *dev;\n \tstruct net_device *netdev;\n-\tstruct napi_struct napi;\n \tvoid __iomem *base;\n+\tint irq_tx;\n \n \tstruct bcm4908_enet_dma_ring tx_ring;\n \tstruct bcm4908_enet_dma_ring rx_ring;\n@@ -123,24 +124,31 @@ static void enet_umac_set(struct bcm4908\n  * Helpers\n  */\n \n-static void bcm4908_enet_intrs_on(struct bcm4908_enet *enet)\n+static void bcm4908_enet_set_mtu(struct bcm4908_enet *enet, int mtu)\n {\n-\tenet_write(enet, ENET_DMA_CH_RX_CFG + ENET_DMA_CH_CFG_INT_MASK, ENET_DMA_INT_DEFAULTS);\n+\tenet_umac_write(enet, UMAC_MAX_FRAME_LEN, mtu + ENET_MAX_ETH_OVERHEAD);\n }\n \n-static void bcm4908_enet_intrs_off(struct bcm4908_enet *enet)\n+/***\n+ * DMA ring ops\n+ */\n+\n+static void bcm4908_enet_dma_ring_intrs_on(struct bcm4908_enet *enet,\n+\t\t\t\t\t   struct bcm4908_enet_dma_ring *ring)\n {\n-\tenet_write(enet, ENET_DMA_CH_RX_CFG + ENET_DMA_CH_CFG_INT_MASK, 0);\n+\tenet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG_INT_MASK, ENET_DMA_INT_DEFAULTS);\n }\n \n-static void bcm4908_enet_intrs_ack(struct bcm4908_enet *enet)\n+static void bcm4908_enet_dma_ring_intrs_off(struct bcm4908_enet *enet,\n+\t\t\t\t\t    struct bcm4908_enet_dma_ring *ring)\n {\n-\tenet_write(enet, ENET_DMA_CH_RX_CFG + ENET_DMA_CH_CFG_INT_STAT, ENET_DMA_INT_DEFAULTS);\n+\tenet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG_INT_MASK, 0);\n }\n \n-static void bcm4908_enet_set_mtu(struct bcm4908_enet *enet, int mtu)\n+static void bcm4908_enet_dma_ring_intrs_ack(struct bcm4908_enet *enet,\n+\t\t\t\t\t    struct bcm4908_enet_dma_ring *ring)\n {\n-\tenet_umac_write(enet, UMAC_MAX_FRAME_LEN, mtu + ENET_MAX_ETH_OVERHEAD);\n+\tenet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG_INT_STAT, ENET_DMA_INT_DEFAULTS);\n }\n \n /***\n@@ -414,11 +422,14 @@ static void bcm4908_enet_gmac_init(struc\n static irqreturn_t bcm4908_enet_irq_handler(int irq, void *dev_id)\n {\n \tstruct bcm4908_enet *enet = dev_id;\n+\tstruct bcm4908_enet_dma_ring *ring;\n \n-\tbcm4908_enet_intrs_off(enet);\n-\tbcm4908_enet_intrs_ack(enet);\n+\tring = (irq == enet->irq_tx) ? &enet->tx_ring : &enet->rx_ring;\n \n-\tnapi_schedule(&enet->napi);\n+\tbcm4908_enet_dma_ring_intrs_off(enet, ring);\n+\tbcm4908_enet_dma_ring_intrs_ack(enet, ring);\n+\n+\tnapi_schedule(&ring->napi);\n \n \treturn IRQ_HANDLED;\n }\n@@ -426,6 +437,8 @@ static irqreturn_t bcm4908_enet_irq_hand\n static int bcm4908_enet_open(struct net_device *netdev)\n {\n \tstruct bcm4908_enet *enet = netdev_priv(netdev);\n+\tstruct bcm4908_enet_dma_ring *tx_ring = &enet->tx_ring;\n+\tstruct bcm4908_enet_dma_ring *rx_ring = &enet->rx_ring;\n \tstruct device *dev = enet->dev;\n \tint err;\n \n@@ -435,6 +448,17 @@ static int bcm4908_enet_open(struct net_\n \t\treturn err;\n \t}\n \n+\tif (enet->irq_tx > 0) {\n+\t\terr = request_irq(enet->irq_tx, bcm4908_enet_irq_handler, 0,\n+\t\t\t\t  \"tx\", enet);\n+\t\tif (err) {\n+\t\t\tdev_err(dev, \"Failed to request IRQ %d: %d\\n\",\n+\t\t\t\tenet->irq_tx, err);\n+\t\t\tfree_irq(netdev->irq, enet);\n+\t\t\treturn err;\n+\t\t}\n+\t}\n+\n \tbcm4908_enet_gmac_init(enet);\n \tbcm4908_enet_dma_reset(enet);\n \tbcm4908_enet_dma_init(enet);\n@@ -443,14 +467,19 @@ static int bcm4908_enet_open(struct net_\n \n \tenet_set(enet, ENET_DMA_CONTROLLER_CFG, ENET_DMA_CTRL_CFG_MASTER_EN);\n \tenet_maskset(enet, ENET_DMA_CONTROLLER_CFG, ENET_DMA_CTRL_CFG_FLOWC_CH1_EN, 0);\n-\tbcm4908_enet_dma_rx_ring_enable(enet, &enet->rx_ring);\n \n-\tnapi_enable(&enet->napi);\n+\tif (enet->irq_tx > 0) {\n+\t\tnapi_enable(&tx_ring->napi);\n+\t\tbcm4908_enet_dma_ring_intrs_ack(enet, tx_ring);\n+\t\tbcm4908_enet_dma_ring_intrs_on(enet, tx_ring);\n+\t}\n+\n+\tbcm4908_enet_dma_rx_ring_enable(enet, rx_ring);\n+\tnapi_enable(&rx_ring->napi);\n \tnetif_carrier_on(netdev);\n \tnetif_start_queue(netdev);\n-\n-\tbcm4908_enet_intrs_ack(enet);\n-\tbcm4908_enet_intrs_on(enet);\n+\tbcm4908_enet_dma_ring_intrs_ack(enet, rx_ring);\n+\tbcm4908_enet_dma_ring_intrs_on(enet, rx_ring);\n \n \treturn 0;\n }\n@@ -458,16 +487,20 @@ static int bcm4908_enet_open(struct net_\n static int bcm4908_enet_stop(struct net_device *netdev)\n {\n \tstruct bcm4908_enet *enet = netdev_priv(netdev);\n+\tstruct bcm4908_enet_dma_ring *tx_ring = &enet->tx_ring;\n+\tstruct bcm4908_enet_dma_ring *rx_ring = &enet->rx_ring;\n \n \tnetif_stop_queue(netdev);\n \tnetif_carrier_off(netdev);\n-\tnapi_disable(&enet->napi);\n+\tnapi_disable(&rx_ring->napi);\n+\tnapi_disable(&tx_ring->napi);\n \n \tbcm4908_enet_dma_rx_ring_disable(enet, &enet->rx_ring);\n \tbcm4908_enet_dma_tx_ring_disable(enet, &enet->tx_ring);\n \n \tbcm4908_enet_dma_uninit(enet);\n \n+\tfree_irq(enet->irq_tx, enet);\n \tfree_irq(enet->netdev->irq, enet);\n \n \treturn 0;\n@@ -484,25 +517,19 @@ static int bcm4908_enet_start_xmit(struc\n \tu32 tmp;\n \n \t/* Free transmitted skbs */\n-\twhile (ring->read_idx != ring->write_idx) {\n-\t\tbuf_desc = &ring->buf_desc[ring->read_idx];\n-\t\tif (le32_to_cpu(buf_desc->ctl) & DMA_CTL_STATUS_OWN)\n-\t\t\tbreak;\n-\t\tslot = &ring->slots[ring->read_idx];\n-\n-\t\tdma_unmap_single(dev, slot->dma_addr, slot->len, DMA_TO_DEVICE);\n-\t\tdev_kfree_skb(slot->skb);\n-\t\tif (++ring->read_idx == ring->length)\n-\t\t\tring->read_idx = 0;\n-\t}\n+\tif (enet->irq_tx < 0 &&\n+\t    !(le32_to_cpu(ring->buf_desc[ring->read_idx].ctl) & DMA_CTL_STATUS_OWN))\n+\t\tnapi_schedule(&enet->tx_ring.napi);\n \n \t/* Don't use the last empty buf descriptor */\n \tif (ring->read_idx <= ring->write_idx)\n \t\tfree_buf_descs = ring->read_idx - ring->write_idx + ring->length;\n \telse\n \t\tfree_buf_descs = ring->read_idx - ring->write_idx;\n-\tif (free_buf_descs < 2)\n+\tif (free_buf_descs < 2) {\n+\t\tnetif_stop_queue(netdev);\n \t\treturn NETDEV_TX_BUSY;\n+\t}\n \n \t/* Hardware removes OWN bit after sending data */\n \tbuf_desc = &ring->buf_desc[ring->write_idx];\n@@ -539,9 +566,10 @@ static int bcm4908_enet_start_xmit(struc\n \treturn NETDEV_TX_OK;\n }\n \n-static int bcm4908_enet_poll(struct napi_struct *napi, int weight)\n+static int bcm4908_enet_poll_rx(struct napi_struct *napi, int weight)\n {\n-\tstruct bcm4908_enet *enet = container_of(napi, struct bcm4908_enet, napi);\n+\tstruct bcm4908_enet_dma_ring *rx_ring = container_of(napi, struct bcm4908_enet_dma_ring, napi);\n+\tstruct bcm4908_enet *enet = container_of(rx_ring, struct bcm4908_enet, rx_ring);\n \tstruct device *dev = enet->dev;\n \tint handled = 0;\n \n@@ -590,7 +618,7 @@ static int bcm4908_enet_poll(struct napi\n \n \tif (handled < weight) {\n \t\tnapi_complete_done(napi, handled);\n-\t\tbcm4908_enet_intrs_on(enet);\n+\t\tbcm4908_enet_dma_ring_intrs_on(enet, rx_ring);\n \t}\n \n \t/* Hardware could disable ring if it run out of descriptors */\n@@ -599,6 +627,42 @@ static int bcm4908_enet_poll(struct napi\n \treturn handled;\n }\n \n+static int bcm4908_enet_poll_tx(struct napi_struct *napi, int weight)\n+{\n+\tstruct bcm4908_enet_dma_ring *tx_ring = container_of(napi, struct bcm4908_enet_dma_ring, napi);\n+\tstruct bcm4908_enet *enet = container_of(tx_ring, struct bcm4908_enet, tx_ring);\n+\tstruct bcm4908_enet_dma_ring_bd *buf_desc;\n+\tstruct bcm4908_enet_dma_ring_slot *slot;\n+\tstruct device *dev = enet->dev;\n+\tunsigned int bytes = 0;\n+\tint handled = 0;\n+\n+\twhile (handled < weight && tx_ring->read_idx != tx_ring->write_idx) {\n+\t\tbuf_desc = &tx_ring->buf_desc[tx_ring->read_idx];\n+\t\tif (le32_to_cpu(buf_desc->ctl) & DMA_CTL_STATUS_OWN)\n+\t\t\tbreak;\n+\t\tslot = &tx_ring->slots[tx_ring->read_idx];\n+\n+\t\tdma_unmap_single(dev, slot->dma_addr, slot->len, DMA_TO_DEVICE);\n+\t\tdev_kfree_skb(slot->skb);\n+\t\tbytes += slot->len;\n+\t\tif (++tx_ring->read_idx == tx_ring->length)\n+\t\t\ttx_ring->read_idx = 0;\n+\n+\t\thandled++;\n+\t}\n+\n+\tif (handled < weight) {\n+\t\tnapi_complete_done(napi, handled);\n+\t\tbcm4908_enet_dma_ring_intrs_on(enet, tx_ring);\n+\t}\n+\n+\tif (netif_queue_stopped(enet->netdev))\n+\t\tnetif_wake_queue(enet->netdev);\n+\n+\treturn handled;\n+}\n+\n static int bcm4908_enet_change_mtu(struct net_device *netdev, int new_mtu)\n {\n \tstruct bcm4908_enet *enet = netdev_priv(netdev);\n@@ -641,6 +705,8 @@ static int bcm4908_enet_probe(struct pla\n \tif (netdev->irq < 0)\n \t\treturn netdev->irq;\n \n+\tenet->irq_tx = platform_get_irq_byname(pdev, \"tx\");\n+\n \tdma_set_coherent_mask(dev, DMA_BIT_MASK(32));\n \n \terr = bcm4908_enet_dma_alloc(enet);\n@@ -655,7 +721,8 @@ static int bcm4908_enet_probe(struct pla\n \tnetdev->min_mtu = ETH_ZLEN;\n \tnetdev->mtu = ETH_DATA_LEN;\n \tnetdev->max_mtu = ENET_MTU_MAX;\n-\tnetif_napi_add(netdev, &enet->napi, bcm4908_enet_poll, 64);\n+\tnetif_tx_napi_add(netdev, &enet->tx_ring.napi, bcm4908_enet_poll_tx, NAPI_POLL_WEIGHT);\n+\tnetif_napi_add(netdev, &enet->rx_ring.napi, bcm4908_enet_poll_rx, NAPI_POLL_WEIGHT);\n \n \terr = register_netdev(netdev);\n \tif (err) {\n@@ -673,7 +740,8 @@ static int bcm4908_enet_remove(struct pl\n \tstruct bcm4908_enet *enet = platform_get_drvdata(pdev);\n \n \tunregister_netdev(enet->netdev);\n-\tnetif_napi_del(&enet->napi);\n+\tnetif_napi_del(&enet->rx_ring.napi);\n+\tnetif_napi_del(&enet->tx_ring.napi);\n \tbcm4908_enet_dma_free(enet);\n \n \treturn 0;\n"
  },
  {
    "path": "target/linux/bcm4908/patches-5.10/075-v5.13-0001-net-dsa-bcm_sf2-store-PHY-interface-mode-in-port-str.patch",
    "content": "From 01488a0ccd9abe15565bed50a45afcddbb0fe199 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Fri, 12 Mar 2021 11:41:07 +0100\nSubject: [PATCH] net: dsa: bcm_sf2: store PHY interface/mode in port structure\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nIt's needed later for proper switch / crossbar setup.\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nAcked-by: Florian Fainelli <f.fainelli@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/dsa/bcm_sf2.c | 16 ++++++++++++----\n drivers/net/dsa/bcm_sf2.h |  1 +\n 2 files changed, 13 insertions(+), 4 deletions(-)\n\n--- a/drivers/net/dsa/bcm_sf2.c\n+++ b/drivers/net/dsa/bcm_sf2.c\n@@ -446,10 +446,11 @@ static void bcm_sf2_intr_disable(struct\n static void bcm_sf2_identify_ports(struct bcm_sf2_priv *priv,\n \t\t\t\t   struct device_node *dn)\n {\n+\tstruct device *dev = priv->dev->ds->dev;\n+\tstruct bcm_sf2_port_status *port_st;\n \tstruct device_node *port;\n \tunsigned int port_num;\n \tstruct property *prop;\n-\tphy_interface_t mode;\n \tint err;\n \n \tpriv->moca_port = -1;\n@@ -458,19 +459,26 @@ static void bcm_sf2_identify_ports(struc\n \t\tif (of_property_read_u32(port, \"reg\", &port_num))\n \t\t\tcontinue;\n \n+\t\tif (port_num >= DSA_MAX_PORTS) {\n+\t\t\tdev_err(dev, \"Invalid port number %d\\n\", port_num);\n+\t\t\tcontinue;\n+\t\t}\n+\n+\t\tport_st = &priv->port_sts[port_num];\n+\n \t\t/* Internal PHYs get assigned a specific 'phy-mode' property\n \t\t * value: \"internal\" to help flag them before MDIO probing\n \t\t * has completed, since they might be turned off at that\n \t\t * time\n \t\t */\n-\t\terr = of_get_phy_mode(port, &mode);\n+\t\terr = of_get_phy_mode(port, &port_st->mode);\n \t\tif (err)\n \t\t\tcontinue;\n \n-\t\tif (mode == PHY_INTERFACE_MODE_INTERNAL)\n+\t\tif (port_st->mode == PHY_INTERFACE_MODE_INTERNAL)\n \t\t\tpriv->int_phy_mask |= 1 << port_num;\n \n-\t\tif (mode == PHY_INTERFACE_MODE_MOCA)\n+\t\tif (port_st->mode == PHY_INTERFACE_MODE_MOCA)\n \t\t\tpriv->moca_port = port_num;\n \n \t\tif (of_property_read_bool(port, \"brcm,use-bcm-hdr\"))\n--- a/drivers/net/dsa/bcm_sf2.h\n+++ b/drivers/net/dsa/bcm_sf2.h\n@@ -44,6 +44,7 @@ struct bcm_sf2_hw_params {\n #define BCM_SF2_REGS_NUM\t6\n \n struct bcm_sf2_port_status {\n+\tphy_interface_t mode;\n \tunsigned int link;\n \tbool enabled;\n };\n"
  },
  {
    "path": "target/linux/bcm4908/patches-5.10/075-v5.13-0002-net-dsa-bcm_sf2-setup-BCM4908-internal-crossbar.patch",
    "content": "From a9349f08ec6c1251d41ef167d27a15cc39bc5b97 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Fri, 12 Mar 2021 11:41:08 +0100\nSubject: [PATCH] net: dsa: bcm_sf2: setup BCM4908 internal crossbar\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nOn some SoCs (e.g. BCM4908, BCM631[345]8) SF2 has an integrated\ncrossbar. It allows connecting its selected external ports to internal\nports. It's used by vendors to handle custom Ethernet setups.\n\nBCM4908 has following 3x2 crossbar. On Asus GT-AC5300 rgmii is used for\nconnecting external BCM53134S switch. GPHY4 is usually used for WAN\nport. More fancy devices use SerDes for 2.5 Gbps Ethernet.\n\n              ┌──────────┐\nSerDes ─── 0 ─┤          │\n              │   3x2    ├─ 0 ─── switch port 7\n GPHY4 ─── 1 ─┤          │\n              │ crossbar ├─ 1 ─── runner (accelerator)\n rgmii ─── 2 ─┤          │\n              └──────────┘\n\nUse setup data based on DT info to configure BCM4908's switch port 7.\nRight now only GPHY and rgmii variants are supported. Handling SerDes\ncan be implemented later.\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nAcked-by: Florian Fainelli <f.fainelli@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/dsa/bcm_sf2.c      | 45 ++++++++++++++++++++++++++++++++++\n drivers/net/dsa/bcm_sf2.h      |  1 +\n drivers/net/dsa/bcm_sf2_regs.h |  7 ++++++\n 3 files changed, 53 insertions(+)\n\n--- a/drivers/net/dsa/bcm_sf2.c\n+++ b/drivers/net/dsa/bcm_sf2.c\n@@ -435,6 +435,44 @@ static int bcm_sf2_sw_rst(struct bcm_sf2\n \treturn 0;\n }\n \n+static void bcm_sf2_crossbar_setup(struct bcm_sf2_priv *priv)\n+{\n+\tstruct device *dev = priv->dev->ds->dev;\n+\tint shift;\n+\tu32 mask;\n+\tu32 reg;\n+\tint i;\n+\n+\tmask = BIT(priv->num_crossbar_int_ports) - 1;\n+\n+\treg = reg_readl(priv, REG_CROSSBAR);\n+\tswitch (priv->type) {\n+\tcase BCM4908_DEVICE_ID:\n+\t\tshift = CROSSBAR_BCM4908_INT_P7 * priv->num_crossbar_int_ports;\n+\t\treg &= ~(mask << shift);\n+\t\tif (0) /* FIXME */\n+\t\t\treg |= CROSSBAR_BCM4908_EXT_SERDES << shift;\n+\t\telse if (priv->int_phy_mask & BIT(7))\n+\t\t\treg |= CROSSBAR_BCM4908_EXT_GPHY4 << shift;\n+\t\telse if (phy_interface_mode_is_rgmii(priv->port_sts[7].mode))\n+\t\t\treg |= CROSSBAR_BCM4908_EXT_RGMII << shift;\n+\t\telse if (WARN(1, \"Invalid port mode\\n\"))\n+\t\t\treturn;\n+\t\tbreak;\n+\tdefault:\n+\t\treturn;\n+\t}\n+\treg_writel(priv, reg, REG_CROSSBAR);\n+\n+\treg = reg_readl(priv, REG_CROSSBAR);\n+\tfor (i = 0; i < priv->num_crossbar_int_ports; i++) {\n+\t\tshift = i * priv->num_crossbar_int_ports;\n+\n+\t\tdev_dbg(dev, \"crossbar int port #%d - ext port #%d\\n\", i,\n+\t\t\t(reg >> shift) & mask);\n+\t}\n+}\n+\n static void bcm_sf2_intr_disable(struct bcm_sf2_priv *priv)\n {\n \tintrl2_0_mask_set(priv, 0xffffffff);\n@@ -872,6 +910,8 @@ static int bcm_sf2_sw_resume(struct dsa_\n \t\treturn ret;\n \t}\n \n+\tbcm_sf2_crossbar_setup(priv);\n+\n \tret = bcm_sf2_cfp_resume(ds);\n \tif (ret)\n \t\treturn ret;\n@@ -1143,6 +1183,7 @@ struct bcm_sf2_of_data {\n \tconst u16 *reg_offsets;\n \tunsigned int core_reg_align;\n \tunsigned int num_cfp_rules;\n+\tunsigned int num_crossbar_int_ports;\n };\n \n static const u16 bcm_sf2_4908_reg_offsets[] = {\n@@ -1167,6 +1208,7 @@ static const struct bcm_sf2_of_data bcm_\n \t.core_reg_align\t= 0,\n \t.reg_offsets\t= bcm_sf2_4908_reg_offsets,\n \t.num_cfp_rules\t= 0, /* FIXME */\n+\t.num_crossbar_int_ports = 2,\n };\n \n /* Register offsets for the SWITCH_REG_* block */\n@@ -1277,6 +1319,7 @@ static int bcm_sf2_sw_probe(struct platf\n \tpriv->reg_offsets = data->reg_offsets;\n \tpriv->core_reg_align = data->core_reg_align;\n \tpriv->num_cfp_rules = data->num_cfp_rules;\n+\tpriv->num_crossbar_int_ports = data->num_crossbar_int_ports;\n \n \tpriv->rcdev = devm_reset_control_get_optional_exclusive(&pdev->dev,\n \t\t\t\t\t\t\t\t\"switch\");\n@@ -1350,6 +1393,8 @@ static int bcm_sf2_sw_probe(struct platf\n \t\tgoto out_clk_mdiv;\n \t}\n \n+\tbcm_sf2_crossbar_setup(priv);\n+\n \tbcm_sf2_gphy_enable_set(priv->dev->ds, true);\n \n \tret = bcm_sf2_mdio_register(ds);\n--- a/drivers/net/dsa/bcm_sf2.h\n+++ b/drivers/net/dsa/bcm_sf2.h\n@@ -74,6 +74,7 @@ struct bcm_sf2_priv {\n \tconst u16\t\t\t*reg_offsets;\n \tunsigned int\t\t\tcore_reg_align;\n \tunsigned int\t\t\tnum_cfp_rules;\n+\tunsigned int\t\t\tnum_crossbar_int_ports;\n \n \t/* spinlock protecting access to the indirect registers */\n \tspinlock_t\t\t\tindir_lock;\n--- a/drivers/net/dsa/bcm_sf2_regs.h\n+++ b/drivers/net/dsa/bcm_sf2_regs.h\n@@ -48,6 +48,13 @@ enum bcm_sf2_reg_offs {\n #define  PHY_PHYAD_SHIFT\t\t8\n #define  PHY_PHYAD_MASK\t\t\t0x1F\n \n+/* Relative to REG_CROSSBAR */\n+#define CROSSBAR_BCM4908_INT_P7\t\t0\n+#define CROSSBAR_BCM4908_INT_RUNNER\t1\n+#define CROSSBAR_BCM4908_EXT_SERDES\t0\n+#define CROSSBAR_BCM4908_EXT_GPHY4\t1\n+#define CROSSBAR_BCM4908_EXT_RGMII\t2\n+\n #define REG_RGMII_CNTRL_P(x)\t\t(REG_RGMII_0_CNTRL + (x))\n \n /* Relative to REG_RGMII_CNTRL */\n"
  },
  {
    "path": "target/linux/bcm4908/patches-5.10/075-v5.13-0003-net-dsa-bcm_sf2-Fill-in-BCM4908-CFP-entries.patch",
    "content": "From f4e6d7cdbfae502788bc468295b232dec76ee57e Mon Sep 17 00:00:00 2001\nFrom: Florian Fainelli <f.fainelli@gmail.com>\nDate: Fri, 12 Mar 2021 13:11:01 -0800\nSubject: [PATCH] net: dsa: bcm_sf2: Fill in BCM4908 CFP entries\n\nThe BCM4908 switch has 256 CFP entrie, update that setting so CFP can be\nused.\n\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/dsa/bcm_sf2.c | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/drivers/net/dsa/bcm_sf2.c\n+++ b/drivers/net/dsa/bcm_sf2.c\n@@ -1207,7 +1207,7 @@ static const struct bcm_sf2_of_data bcm_\n \t.type\t\t= BCM4908_DEVICE_ID,\n \t.core_reg_align\t= 0,\n \t.reg_offsets\t= bcm_sf2_4908_reg_offsets,\n-\t.num_cfp_rules\t= 0, /* FIXME */\n+\t.num_cfp_rules\t= 256,\n \t.num_crossbar_int_ports = 2,\n };\n \n"
  },
  {
    "path": "target/linux/bcm4908/patches-5.10/075-v5.13-0004-net-dsa-bcm_sf2-add-function-finding-RGMII-register.patch",
    "content": "From 55cfeb396965c3906a84d09a9c487d065e37773b Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Thu, 18 Mar 2021 09:01:42 +0100\nSubject: [PATCH 1/2] net: dsa: bcm_sf2: add function finding RGMII register\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nSimple macro like REG_RGMII_CNTRL_P() is insufficient as:\n1. It doesn't validate port argument\n2. It doesn't support chipsets with non-lineral RGMII regs layout\n\nMissing port validation could result in getting register offset from out\nof array. Random memory -> random offset -> random reads/writes. It\naffected e.g. BCM4908 for REG_RGMII_CNTRL_P(7).\n\nFixes: a78e86ed586d (\"net: dsa: bcm_sf2: Prepare for different register layouts\")\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nAcked-by: Florian Fainelli <f.fainelli@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/dsa/bcm_sf2.c      | 49 +++++++++++++++++++++++++++++-----\n drivers/net/dsa/bcm_sf2_regs.h |  2 --\n 2 files changed, 42 insertions(+), 9 deletions(-)\n\n--- a/drivers/net/dsa/bcm_sf2.c\n+++ b/drivers/net/dsa/bcm_sf2.c\n@@ -75,6 +75,31 @@ static void bcm_sf2_recalc_clock(struct\n \tclk_set_rate(priv->clk_mdiv, new_rate);\n }\n \n+static u16 bcm_sf2_reg_rgmii_cntrl(struct bcm_sf2_priv *priv, int port)\n+{\n+\tswitch (priv->type) {\n+\tcase BCM4908_DEVICE_ID:\n+\t\t/* TODO */\n+\t\tbreak;\n+\tdefault:\n+\t\tswitch (port) {\n+\t\tcase 0:\n+\t\t\treturn REG_RGMII_0_CNTRL;\n+\t\tcase 1:\n+\t\t\treturn REG_RGMII_1_CNTRL;\n+\t\tcase 2:\n+\t\t\treturn REG_RGMII_2_CNTRL;\n+\t\tdefault:\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\n+\tWARN_ONCE(1, \"Unsupported port %d\\n\", port);\n+\n+\t/* RO fallback reg */\n+\treturn REG_SWITCH_STATUS;\n+}\n+\n static void bcm_sf2_imp_setup(struct dsa_switch *ds, int port)\n {\n \tstruct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);\n@@ -696,6 +721,7 @@ static void bcm_sf2_sw_mac_config(struct\n {\n \tstruct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);\n \tu32 id_mode_dis = 0, port_mode;\n+\tu32 reg_rgmii_ctrl;\n \tu32 reg;\n \n \tif (port == core_readl(priv, CORE_IMP0_PRT_ID))\n@@ -719,10 +745,12 @@ static void bcm_sf2_sw_mac_config(struct\n \t\treturn;\n \t}\n \n+\treg_rgmii_ctrl = bcm_sf2_reg_rgmii_cntrl(priv, port);\n+\n \t/* Clear id_mode_dis bit, and the existing port mode, let\n \t * RGMII_MODE_EN bet set by mac_link_{up,down}\n \t */\n-\treg = reg_readl(priv, REG_RGMII_CNTRL_P(port));\n+\treg = reg_readl(priv, reg_rgmii_ctrl);\n \treg &= ~ID_MODE_DIS;\n \treg &= ~(PORT_MODE_MASK << PORT_MODE_SHIFT);\n \n@@ -730,13 +758,14 @@ static void bcm_sf2_sw_mac_config(struct\n \tif (id_mode_dis)\n \t\treg |= ID_MODE_DIS;\n \n-\treg_writel(priv, reg, REG_RGMII_CNTRL_P(port));\n+\treg_writel(priv, reg, reg_rgmii_ctrl);\n }\n \n static void bcm_sf2_sw_mac_link_set(struct dsa_switch *ds, int port,\n \t\t\t\t    phy_interface_t interface, bool link)\n {\n \tstruct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);\n+\tu32 reg_rgmii_ctrl;\n \tu32 reg;\n \n \tif (!phy_interface_mode_is_rgmii(interface) &&\n@@ -744,13 +773,15 @@ static void bcm_sf2_sw_mac_link_set(stru\n \t    interface != PHY_INTERFACE_MODE_REVMII)\n \t\treturn;\n \n+\treg_rgmii_ctrl = bcm_sf2_reg_rgmii_cntrl(priv, port);\n+\n \t/* If the link is down, just disable the interface to conserve power */\n-\treg = reg_readl(priv, REG_RGMII_CNTRL_P(port));\n+\treg = reg_readl(priv, reg_rgmii_ctrl);\n \tif (link)\n \t\treg |= RGMII_MODE_EN;\n \telse\n \t\treg &= ~RGMII_MODE_EN;\n-\treg_writel(priv, reg, REG_RGMII_CNTRL_P(port));\n+\treg_writel(priv, reg, reg_rgmii_ctrl);\n }\n \n static void bcm_sf2_sw_mac_link_down(struct dsa_switch *ds, int port,\n@@ -784,11 +815,15 @@ static void bcm_sf2_sw_mac_link_up(struc\n {\n \tstruct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);\n \tstruct ethtool_eee *p = &priv->dev->ports[port].eee;\n-\tu32 reg, offset;\n \n \tbcm_sf2_sw_mac_link_set(ds, port, interface, true);\n \n \tif (port != core_readl(priv, CORE_IMP0_PRT_ID)) {\n+\t\tu32 reg_rgmii_ctrl;\n+\t\tu32 reg, offset;\n+\n+\t\treg_rgmii_ctrl = bcm_sf2_reg_rgmii_cntrl(priv, port);\n+\n \t\tif (priv->type == BCM4908_DEVICE_ID ||\n \t\t    priv->type == BCM7445_DEVICE_ID)\n \t\t\toffset = CORE_STS_OVERRIDE_GMIIP_PORT(port);\n@@ -799,7 +834,7 @@ static void bcm_sf2_sw_mac_link_up(struc\n \t\t    interface == PHY_INTERFACE_MODE_RGMII_TXID ||\n \t\t    interface == PHY_INTERFACE_MODE_MII ||\n \t\t    interface == PHY_INTERFACE_MODE_REVMII) {\n-\t\t\treg = reg_readl(priv, REG_RGMII_CNTRL_P(port));\n+\t\t\treg = reg_readl(priv, reg_rgmii_ctrl);\n \t\t\treg &= ~(RX_PAUSE_EN | TX_PAUSE_EN);\n \n \t\t\tif (tx_pause)\n@@ -807,7 +842,7 @@ static void bcm_sf2_sw_mac_link_up(struc\n \t\t\tif (rx_pause)\n \t\t\t\treg |= RX_PAUSE_EN;\n \n-\t\t\treg_writel(priv, reg, REG_RGMII_CNTRL_P(port));\n+\t\t\treg_writel(priv, reg, reg_rgmii_ctrl);\n \t\t}\n \n \t\treg = SW_OVERRIDE | LINK_STS;\n--- a/drivers/net/dsa/bcm_sf2_regs.h\n+++ b/drivers/net/dsa/bcm_sf2_regs.h\n@@ -55,8 +55,6 @@ enum bcm_sf2_reg_offs {\n #define CROSSBAR_BCM4908_EXT_GPHY4\t1\n #define CROSSBAR_BCM4908_EXT_RGMII\t2\n \n-#define REG_RGMII_CNTRL_P(x)\t\t(REG_RGMII_0_CNTRL + (x))\n-\n /* Relative to REG_RGMII_CNTRL */\n #define  RGMII_MODE_EN\t\t\t(1 << 0)\n #define  ID_MODE_DIS\t\t\t(1 << 1)\n"
  },
  {
    "path": "target/linux/bcm4908/patches-5.10/075-v5.13-0005-net-dsa-bcm_sf2-fix-BCM4908-RGMII-reg-s.patch",
    "content": "From 6859d91549341c2ad769d482de58129f080c0f04 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Thu, 18 Mar 2021 09:01:43 +0100\nSubject: [PATCH 2/2] net: dsa: bcm_sf2: fix BCM4908 RGMII reg(s)\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nBCM4908 has only 1 RGMII reg for controlling port 7.\n\nFixes: 73b7a6047971 (\"net: dsa: bcm_sf2: support BCM4908's integrated switch\")\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nAcked-by: Florian Fainelli <f.fainelli@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/dsa/bcm_sf2.c      | 11 +++++++----\n drivers/net/dsa/bcm_sf2_regs.h |  1 +\n 2 files changed, 8 insertions(+), 4 deletions(-)\n\n--- a/drivers/net/dsa/bcm_sf2.c\n+++ b/drivers/net/dsa/bcm_sf2.c\n@@ -79,7 +79,12 @@ static u16 bcm_sf2_reg_rgmii_cntrl(struc\n {\n \tswitch (priv->type) {\n \tcase BCM4908_DEVICE_ID:\n-\t\t/* TODO */\n+\t\tswitch (port) {\n+\t\tcase 7:\n+\t\t\treturn REG_RGMII_11_CNTRL;\n+\t\tdefault:\n+\t\t\tbreak;\n+\t\t}\n \t\tbreak;\n \tdefault:\n \t\tswitch (port) {\n@@ -1230,9 +1235,7 @@ static const u16 bcm_sf2_4908_reg_offset\n \t[REG_PHY_REVISION]\t= 0x14,\n \t[REG_SPHY_CNTRL]\t= 0x24,\n \t[REG_CROSSBAR]\t\t= 0xc8,\n-\t[REG_RGMII_0_CNTRL]\t= 0xe0,\n-\t[REG_RGMII_1_CNTRL]\t= 0xec,\n-\t[REG_RGMII_2_CNTRL]\t= 0xf8,\n+\t[REG_RGMII_11_CNTRL]\t= 0x014c,\n \t[REG_LED_0_CNTRL]\t= 0x40,\n \t[REG_LED_1_CNTRL]\t= 0x4c,\n \t[REG_LED_2_CNTRL]\t= 0x58,\n--- a/drivers/net/dsa/bcm_sf2_regs.h\n+++ b/drivers/net/dsa/bcm_sf2_regs.h\n@@ -21,6 +21,7 @@ enum bcm_sf2_reg_offs {\n \tREG_RGMII_0_CNTRL,\n \tREG_RGMII_1_CNTRL,\n \tREG_RGMII_2_CNTRL,\n+\tREG_RGMII_11_CNTRL,\n \tREG_LED_0_CNTRL,\n \tREG_LED_1_CNTRL,\n \tREG_LED_2_CNTRL,\n"
  },
  {
    "path": "target/linux/bcm4908/patches-5.10/075-v5.13-0006-net-dsa-bcm_sf2-Fix-bcm_sf2_reg_rgmii_cntrl-call-for.patch",
    "content": "From fc516d3a6aa2c6ffe27d0da8818d13839e023e7e Mon Sep 17 00:00:00 2001\nFrom: Florian Fainelli <f.fainelli@gmail.com>\nDate: Fri, 21 May 2021 10:46:14 -0700\nSubject: [PATCH] net: dsa: bcm_sf2: Fix bcm_sf2_reg_rgmii_cntrl() call for\n non-RGMII port\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nWe cannot call bcm_sf2_reg_rgmii_cntrl() for a port that is not RGMII,\nyet we do that in bcm_sf2_sw_mac_link_up() irrespective of the port's\ninterface. Move that read until we have properly qualified the PHY\ninterface mode. This avoids triggering a warning on 7278 platforms that\nhave GMII ports.\n\nFixes: 55cfeb396965 (\"net: dsa: bcm_sf2: add function finding RGMII register\")\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\nAcked-by: Rafał Miłecki <rafal@milecki.pl>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/dsa/bcm_sf2.c | 5 ++---\n 1 file changed, 2 insertions(+), 3 deletions(-)\n\n--- a/drivers/net/dsa/bcm_sf2.c\n+++ b/drivers/net/dsa/bcm_sf2.c\n@@ -824,11 +824,9 @@ static void bcm_sf2_sw_mac_link_up(struc\n \tbcm_sf2_sw_mac_link_set(ds, port, interface, true);\n \n \tif (port != core_readl(priv, CORE_IMP0_PRT_ID)) {\n-\t\tu32 reg_rgmii_ctrl;\n+\t\tu32 reg_rgmii_ctrl = 0;\n \t\tu32 reg, offset;\n \n-\t\treg_rgmii_ctrl = bcm_sf2_reg_rgmii_cntrl(priv, port);\n-\n \t\tif (priv->type == BCM4908_DEVICE_ID ||\n \t\t    priv->type == BCM7445_DEVICE_ID)\n \t\t\toffset = CORE_STS_OVERRIDE_GMIIP_PORT(port);\n@@ -839,6 +837,7 @@ static void bcm_sf2_sw_mac_link_up(struc\n \t\t    interface == PHY_INTERFACE_MODE_RGMII_TXID ||\n \t\t    interface == PHY_INTERFACE_MODE_MII ||\n \t\t    interface == PHY_INTERFACE_MODE_REVMII) {\n+\t\t\treg_rgmii_ctrl = bcm_sf2_reg_rgmii_cntrl(priv, port);\n \t\t\treg = reg_readl(priv, reg_rgmii_ctrl);\n \t\t\treg &= ~(RX_PAUSE_EN | TX_PAUSE_EN);\n \n"
  },
  {
    "path": "target/linux/bcm4908/patches-5.10/076-v5.17-net-dsa-bcm_sf2-refactor-LED-regs-access.patch",
    "content": "From af30f8eaa8fe4ff1987280f716309711997bd979 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Wed, 29 Dec 2021 18:16:42 +0100\nSubject: [PATCH] net: dsa: bcm_sf2: refactor LED regs access\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\n1. Define more regs. Some switches (e.g. BCM4908) have up to 6 regs.\n2. Add helper for handling non-lineral port <-> reg mappings.\n3. Add support for 12 B LED reg blocks on BCM4908 (different layout)\n\nComplete support for LEDs setup will be implemented once Linux receives\na proper design & implementation for \"hardware\" LEDs.\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nAcked-by: Florian Fainelli <f.fainelli@gmail.com>\nLink: https://lore.kernel.org/r/20211229171642.22942-1-zajec5@gmail.com\nSigned-off-by: Jakub Kicinski <kuba@kernel.org>\n---\n drivers/net/dsa/bcm_sf2.c      | 54 ++++++++++++++++++++++++----\n drivers/net/dsa/bcm_sf2.h      | 10 ++++++\n drivers/net/dsa/bcm_sf2_regs.h | 65 +++++++++++++++++++++++++++++++---\n 3 files changed, 119 insertions(+), 10 deletions(-)\n\n--- a/drivers/net/dsa/bcm_sf2.c\n+++ b/drivers/net/dsa/bcm_sf2.c\n@@ -32,6 +32,38 @@\n #include \"b53/b53_priv.h\"\n #include \"b53/b53_regs.h\"\n \n+static u16 bcm_sf2_reg_led_base(struct bcm_sf2_priv *priv, int port)\n+{\n+\tswitch (port) {\n+\tcase 0:\n+\t\treturn REG_LED_0_CNTRL;\n+\tcase 1:\n+\t\treturn REG_LED_1_CNTRL;\n+\tcase 2:\n+\t\treturn REG_LED_2_CNTRL;\n+\t}\n+\n+\tswitch (priv->type) {\n+\tcase BCM4908_DEVICE_ID:\n+\t\tswitch (port) {\n+\t\tcase 3:\n+\t\t\treturn REG_LED_3_CNTRL;\n+\t\tcase 7:\n+\t\t\treturn REG_LED_4_CNTRL;\n+\t\tdefault:\n+\t\t\tbreak;\n+\t\t}\n+\t\tbreak;\n+\tdefault:\n+\t\tbreak;\n+\t}\n+\n+\tWARN_ONCE(1, \"Unsupported port %d\\n\", port);\n+\n+\t/* RO fallback reg */\n+\treturn REG_SWITCH_STATUS;\n+}\n+\n /* Return the number of active ports, not counting the IMP (CPU) port */\n static unsigned int bcm_sf2_num_active_ports(struct dsa_switch *ds)\n {\n@@ -187,9 +219,14 @@ static void bcm_sf2_gphy_enable_set(stru\n \n \t/* Use PHY-driven LED signaling */\n \tif (!enable) {\n-\t\treg = reg_readl(priv, REG_LED_CNTRL(0));\n-\t\treg |= SPDLNK_SRC_SEL;\n-\t\treg_writel(priv, reg, REG_LED_CNTRL(0));\n+\t\tu16 led_ctrl = bcm_sf2_reg_led_base(priv, 0);\n+\n+\t\tif (priv->type == BCM7278_DEVICE_ID ||\n+\t\t    priv->type == BCM7445_DEVICE_ID) {\n+\t\t\treg = reg_led_readl(priv, led_ctrl, 0);\n+\t\t\treg |= LED_CNTRL_SPDLNK_SRC_SEL;\n+\t\t\treg_led_writel(priv, reg, led_ctrl, 0);\n+\t\t}\n \t}\n }\n \n@@ -1235,9 +1272,14 @@ static const u16 bcm_sf2_4908_reg_offset\n \t[REG_SPHY_CNTRL]\t= 0x24,\n \t[REG_CROSSBAR]\t\t= 0xc8,\n \t[REG_RGMII_11_CNTRL]\t= 0x014c,\n-\t[REG_LED_0_CNTRL]\t= 0x40,\n-\t[REG_LED_1_CNTRL]\t= 0x4c,\n-\t[REG_LED_2_CNTRL]\t= 0x58,\n+\t[REG_LED_0_CNTRL]\t\t= 0x40,\n+\t[REG_LED_1_CNTRL]\t\t= 0x4c,\n+\t[REG_LED_2_CNTRL]\t\t= 0x58,\n+\t[REG_LED_3_CNTRL]\t\t= 0x64,\n+\t[REG_LED_4_CNTRL]\t\t= 0x88,\n+\t[REG_LED_5_CNTRL]\t\t= 0xa0,\n+\t[REG_LED_AGGREGATE_CTRL]\t= 0xb8,\n+\n };\n \n static const struct bcm_sf2_of_data bcm_sf2_4908_data = {\n--- a/drivers/net/dsa/bcm_sf2.h\n+++ b/drivers/net/dsa/bcm_sf2.h\n@@ -210,6 +210,16 @@ SF2_IO_MACRO(acb);\n SWITCH_INTR_L2(0);\n SWITCH_INTR_L2(1);\n \n+static inline u32 reg_led_readl(struct bcm_sf2_priv *priv, u16 off, u16 reg)\n+{\n+\treturn readl_relaxed(priv->reg + priv->reg_offsets[off] + reg);\n+}\n+\n+static inline void reg_led_writel(struct bcm_sf2_priv *priv, u32 val, u16 off, u16 reg)\n+{\n+\twritel_relaxed(val, priv->reg + priv->reg_offsets[off] + reg);\n+}\n+\n /* RXNFC */\n int bcm_sf2_get_rxnfc(struct dsa_switch *ds, int port,\n \t\t      struct ethtool_rxnfc *nfc, u32 *rule_locs);\n--- a/drivers/net/dsa/bcm_sf2_regs.h\n+++ b/drivers/net/dsa/bcm_sf2_regs.h\n@@ -25,6 +25,10 @@ enum bcm_sf2_reg_offs {\n \tREG_LED_0_CNTRL,\n \tREG_LED_1_CNTRL,\n \tREG_LED_2_CNTRL,\n+\tREG_LED_3_CNTRL,\n+\tREG_LED_4_CNTRL,\n+\tREG_LED_5_CNTRL,\n+\tREG_LED_AGGREGATE_CTRL,\n \tREG_SWITCH_REG_MAX,\n };\n \n@@ -56,6 +60,63 @@ enum bcm_sf2_reg_offs {\n #define CROSSBAR_BCM4908_EXT_GPHY4\t1\n #define CROSSBAR_BCM4908_EXT_RGMII\t2\n \n+/* Relative to REG_LED_*_CNTRL (BCM7278, BCM7445) */\n+#define  LED_CNTRL_NO_LINK_ENCODE_SHIFT\t\t0\n+#define  LED_CNTRL_M10_ENCODE_SHIFT\t\t2\n+#define  LED_CNTRL_M100_ENCODE_SHIFT\t\t4\n+#define  LED_CNTRL_M1000_ENCODE_SHIFT\t\t6\n+#define  LED_CNTRL_SEL_NO_LINK_ENCODE_SHIFT\t8\n+#define  LED_CNTRL_SEL_10M_ENCODE_SHIFT\t\t10\n+#define  LED_CNTRL_SEL_100M_ENCODE_SHIFT\t12\n+#define  LED_CNTRL_SEL_1000M_ENCODE_SHIFT\t14\n+#define  LED_CNTRL_RX_DV_EN\t\t\t(1 << 16)\n+#define  LED_CNTRL_TX_EN_EN\t\t\t(1 << 17)\n+#define  LED_CNTRL_SPDLNK_LED0_ACT_SEL_SHIFT\t18\n+#define  LED_CNTRL_SPDLNK_LED1_ACT_SEL_SHIFT\t20\n+#define  LED_CNTRL_ACT_LED_ACT_SEL_SHIFT\t22\n+#define  LED_CNTRL_SPDLNK_SRC_SEL\t\t(1 << 24)\n+#define  LED_CNTRL_SPDLNK_LED0_ACT_POL_SEL\t(1 << 25)\n+#define  LED_CNTRL_SPDLNK_LED1_ACT_POL_SEL\t(1 << 26)\n+#define  LED_CNTRL_ACT_LED_POL_SEL\t\t(1 << 27)\n+#define  LED_CNTRL_MASK\t\t\t\t0x3\n+\n+/* Register relative to REG_LED_*_CNTRL (BCM4908) */\n+#define REG_LED_CTRL\t\t\t\t0x0\n+#define  LED_CTRL_RX_ACT_EN\t\t\t0x00000001\n+#define  LED_CTRL_TX_ACT_EN\t\t\t0x00000002\n+#define  LED_CTRL_SPDLNK_LED0_ACT_SEL\t\t0x00000004\n+#define  LED_CTRL_SPDLNK_LED1_ACT_SEL\t\t0x00000008\n+#define  LED_CTRL_SPDLNK_LED2_ACT_SEL\t\t0x00000010\n+#define  LED_CTRL_ACT_LED_ACT_SEL\t\t0x00000020\n+#define  LED_CTRL_SPDLNK_LED0_ACT_POL_SEL\t0x00000040\n+#define  LED_CTRL_SPDLNK_LED1_ACT_POL_SEL\t0x00000080\n+#define  LED_CTRL_SPDLNK_LED2_ACT_POL_SEL\t0x00000100\n+#define  LED_CTRL_ACT_LED_POL_SEL\t\t0x00000200\n+#define  LED_CTRL_LED_SPD_OVRD\t\t\t0x00001c00\n+#define  LED_CTRL_LNK_STATUS_OVRD\t\t0x00002000\n+#define  LED_CTRL_SPD_OVRD_EN\t\t\t0x00004000\n+#define  LED_CTRL_LNK_OVRD_EN\t\t\t0x00008000\n+\n+/* Register relative to REG_LED_*_CNTRL (BCM4908) */\n+#define REG_LED_LINK_SPEED_ENC_SEL\t\t0x4\n+#define  LED_LINK_SPEED_ENC_SEL_NO_LINK_SHIFT\t0\n+#define  LED_LINK_SPEED_ENC_SEL_10M_SHIFT\t3\n+#define  LED_LINK_SPEED_ENC_SEL_100M_SHIFT\t6\n+#define  LED_LINK_SPEED_ENC_SEL_1000M_SHIFT\t9\n+#define  LED_LINK_SPEED_ENC_SEL_2500M_SHIFT\t12\n+#define  LED_LINK_SPEED_ENC_SEL_10G_SHIFT\t15\n+#define  LED_LINK_SPEED_ENC_SEL_MASK\t\t0x7\n+\n+/* Register relative to REG_LED_*_CNTRL (BCM4908) */\n+#define REG_LED_LINK_SPEED_ENC\t\t\t0x8\n+#define  LED_LINK_SPEED_ENC_NO_LINK_SHIFT\t0\n+#define  LED_LINK_SPEED_ENC_M10_SHIFT\t\t3\n+#define  LED_LINK_SPEED_ENC_M100_SHIFT\t\t6\n+#define  LED_LINK_SPEED_ENC_M1000_SHIFT\t\t9\n+#define  LED_LINK_SPEED_ENC_M2500_SHIFT\t\t12\n+#define  LED_LINK_SPEED_ENC_M10G_SHIFT\t\t15\n+#define  LED_LINK_SPEED_ENC_MASK\t\t0x7\n+\n /* Relative to REG_RGMII_CNTRL */\n #define  RGMII_MODE_EN\t\t\t(1 << 0)\n #define  ID_MODE_DIS\t\t\t(1 << 1)\n@@ -73,10 +134,6 @@ enum bcm_sf2_reg_offs {\n #define  LPI_COUNT_SHIFT\t\t9\n #define  LPI_COUNT_MASK\t\t\t0x3F\n \n-#define REG_LED_CNTRL(x)\t\t(REG_LED_0_CNTRL + (x))\n-\n-#define  SPDLNK_SRC_SEL\t\t\t(1 << 24)\n-\n /* Register set relative to 'INTRL2_0' and 'INTRL2_1' */\n #define INTRL2_CPU_STATUS\t\t0x00\n #define INTRL2_CPU_SET\t\t\t0x04\n"
  },
  {
    "path": "target/linux/bcm4908/patches-5.10/080-v5.11-tty-serial-bcm63xx-lower-driver-dependencies.patch",
    "content": "From f35a07f92616700733636c06dd6e5b6cdc807fe4 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Wed, 25 Nov 2020 10:06:08 +0100\nSubject: [PATCH] tty: serial: bcm63xx: lower driver dependencies\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nHardware supported by bcm63xx is also used by BCM4908 SoCs family that\nis ARM64. In future more architectures may need it as well. There is\nnothing arch specific breaking compilation so just stick to requiring\nCOMMON_CLK.\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nLink: https://lore.kernel.org/r/20201125090608.28442-1-zajec5@gmail.com\nSigned-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>\n---\n drivers/tty/serial/Kconfig | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/drivers/tty/serial/Kconfig\n+++ b/drivers/tty/serial/Kconfig\n@@ -1133,7 +1133,7 @@ config SERIAL_TIMBERDALE\n config SERIAL_BCM63XX\n \ttristate \"Broadcom BCM63xx/BCM33xx UART support\"\n \tselect SERIAL_CORE\n-\tdepends on MIPS || ARM || COMPILE_TEST\n+\tdepends on COMMON_CLK\n \thelp\n \t  This enables the driver for the onchip UART core found on\n \t  the following chipsets:\n"
  },
  {
    "path": "target/linux/bcm4908/patches-5.10/081-v5.12-reset-simple-add-BCM4908-MISC-PCIe-reset-controller-.patch",
    "content": "From def26913b66fd94e431afecf28e09c08e8c02a35 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Fri, 27 Nov 2020 12:14:42 +0100\nSubject: [PATCH] reset: simple: add BCM4908 MISC PCIe reset controller support\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nIt's a trivial reset controller. One register with bit per PCIe core.\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nAcked-by: Florian Fainelli <f.fainelli@gmail.com>\nSigned-off-by: Philipp Zabel <p.zabel@pengutronix.de>\n---\n drivers/reset/Kconfig        | 2 +-\n drivers/reset/reset-simple.c | 2 ++\n 2 files changed, 3 insertions(+), 1 deletion(-)\n\n--- a/drivers/reset/Kconfig\n+++ b/drivers/reset/Kconfig\n@@ -167,7 +167,7 @@ config RESET_SCMI\n \n config RESET_SIMPLE\n \tbool \"Simple Reset Controller Driver\" if COMPILE_TEST\n-\tdefault ARCH_AGILEX || ARCH_ASPEED || ARCH_BITMAIN || ARCH_REALTEK || ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX || ARC\n+\tdefault ARCH_AGILEX || ARCH_ASPEED || ARCH_BCM4908 || ARCH_BITMAIN || ARCH_REALTEK || ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX || ARC\n \thelp\n \t  This enables a simple reset controller driver for reset lines that\n \t  that can be asserted and deasserted by toggling bits in a contiguous,\n--- a/drivers/reset/reset-simple.c\n+++ b/drivers/reset/reset-simple.c\n@@ -146,6 +146,8 @@ static const struct of_device_id reset_s\n \t{ .compatible = \"aspeed,ast2500-lpc-reset\" },\n \t{ .compatible = \"bitmain,bm1880-reset\",\n \t\t.data = &reset_simple_active_low },\n+\t{ .compatible = \"brcm,bcm4908-misc-pcie-reset\",\n+\t\t.data = &reset_simple_active_low },\n \t{ .compatible = \"snps,dw-high-reset\" },\n \t{ .compatible = \"snps,dw-low-reset\",\n \t\t.data = &reset_simple_active_low },\n"
  },
  {
    "path": "target/linux/bcm4908/patches-5.10/082-v5.12-0001-dt-bindings-power-document-Broadcom-s-PMB-binding.patch",
    "content": "From 82853543057f78d8a331272b70bc3f1e8cb0cbf4 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Mon, 14 Dec 2020 19:07:42 +0100\nSubject: [PATCH] dt-bindings: power: document Broadcom's PMB binding\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nBroadcom's PMB is power controller used for disabling and enabling SoC\ndevices.\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nReviewed-by: Rob Herring <robh@kernel.org>\nAcked-by: Florian Fainelli <f.fainelli@gmail.com>\nAcked-by: Ulf Hansson <ulf.hansson@linaro.org>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n .../bindings/power/brcm,bcm-pmb.yaml          | 50 +++++++++++++++++++\n include/dt-bindings/soc/bcm-pmb.h             | 11 ++++\n 2 files changed, 61 insertions(+)\n create mode 100644 Documentation/devicetree/bindings/power/brcm,bcm-pmb.yaml\n create mode 100644 include/dt-bindings/soc/bcm-pmb.h\n\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/power/brcm,bcm-pmb.yaml\n@@ -0,0 +1,50 @@\n+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause\n+%YAML 1.2\n+---\n+$id: http://devicetree.org/schemas/power/brcm,bcm-pmb.yaml#\n+$schema: http://devicetree.org/meta-schemas/core.yaml#\n+\n+title: Broadcom PMB (Power Management Bus) controller\n+\n+description: This document describes Broadcom's PMB controller. It supports\n+  powering various types of connected devices (e.g. PCIe, USB, SATA).\n+\n+maintainers:\n+  - Rafał Miłecki <rafal@milecki.pl>\n+\n+properties:\n+  compatible:\n+    enum:\n+      - brcm,bcm4908-pmb\n+\n+  reg:\n+    description: register space of one or more buses\n+    maxItems: 1\n+\n+  big-endian:\n+    $ref: /schemas/types.yaml#/definitions/flag\n+    description: Flag to use for block working in big endian mode.\n+\n+  \"#power-domain-cells\":\n+    description: cell specifies device ID (see bcm-pmb.h)\n+    const: 1\n+\n+required:\n+  - reg\n+  - \"#power-domain-cells\"\n+\n+additionalProperties: false\n+\n+examples:\n+  - |\n+    #include <dt-bindings/soc/bcm-pmb.h>\n+\n+    pmb: power-controller@802800e0 {\n+        compatible = \"brcm,bcm4908-pmb\";\n+        reg = <0x802800e0 0x40>;\n+        #power-domain-cells = <1>;\n+    };\n+\n+    foo {\n+        power-domains = <&pmb BCM_PMB_PCIE0>;\n+    };\n--- /dev/null\n+++ b/include/dt-bindings/soc/bcm-pmb.h\n@@ -0,0 +1,11 @@\n+/* SPDX-License-Identifier: GPL-2.0-or-later OR MIT */\n+\n+#ifndef __DT_BINDINGS_SOC_BCM_PMB_H\n+#define __DT_BINDINGS_SOC_BCM_PMB_H\n+\n+#define BCM_PMB_PCIE0\t\t\t\t0x01\n+#define BCM_PMB_PCIE1\t\t\t\t0x02\n+#define BCM_PMB_PCIE2\t\t\t\t0x03\n+#define BCM_PMB_HOST_USB\t\t\t0x04\n+\n+#endif\n"
  },
  {
    "path": "target/linux/bcm4908/patches-5.10/082-v5.12-0002-soc-bcm-add-PM-driver-for-Broadcom-s-PMB.patch",
    "content": "From 8bcac4011ebe0dbdd46fd55b036ee855c95702d3 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Mon, 14 Dec 2020 19:07:43 +0100\nSubject: [PATCH] soc: bcm: add PM driver for Broadcom's PMB\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nPMB originally comes from BCM63138 but can be also found on many other\nchipsets (e.g. BCM4908). It's needed to power on and off SoC blocks like\nPCIe, SATA, USB.\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nAcked-by: Ulf Hansson <ulf.hansson@linaro.org>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n MAINTAINERS                       |  10 +\n drivers/soc/bcm/Makefile          |   2 +-\n drivers/soc/bcm/bcm63xx/Kconfig   |   9 +\n drivers/soc/bcm/bcm63xx/Makefile  |   1 +\n drivers/soc/bcm/bcm63xx/bcm-pmb.c | 333 ++++++++++++++++++++++++++++++\n 5 files changed, 354 insertions(+), 1 deletion(-)\n create mode 100644 drivers/soc/bcm/bcm63xx/bcm-pmb.c\n\n--- a/MAINTAINERS\n+++ b/MAINTAINERS\n@@ -3674,6 +3674,16 @@ L:\tlinux-mips@vger.kernel.org\n S:\tMaintained\n F:\tdrivers/firmware/broadcom/*\n \n+BROADCOM PMB (POWER MANAGEMENT BUS) DRIVER\n+M:\tRafał Miłecki <rafal@milecki.pl>\n+M:\tFlorian Fainelli <f.fainelli@gmail.com>\n+M:\tbcm-kernel-feedback-list@broadcom.com\n+L:\tlinux-pm@vger.kernel.org\n+S:\tMaintained\n+T:\tgit git://github.com/broadcom/stblinux.git\n+F:\tdrivers/soc/bcm/bcm-pmb.c\n+F:\tinclude/dt-bindings/soc/bcm-pmb.h\n+\n BROADCOM SPECIFIC AMBA DRIVER (BCMA)\n M:\tRafał Miłecki <zajec5@gmail.com>\n L:\tlinux-wireless@vger.kernel.org\n--- a/drivers/soc/bcm/Makefile\n+++ b/drivers/soc/bcm/Makefile\n@@ -1,5 +1,5 @@\n # SPDX-License-Identifier: GPL-2.0-only\n obj-$(CONFIG_BCM2835_POWER)\t+= bcm2835-power.o\n obj-$(CONFIG_RASPBERRYPI_POWER)\t+= raspberrypi-power.o\n-obj-$(CONFIG_SOC_BCM63XX)\t+= bcm63xx/\n+obj-y\t\t\t\t+= bcm63xx/\n obj-$(CONFIG_SOC_BRCMSTB)\t+= brcmstb/\n--- a/drivers/soc/bcm/bcm63xx/Kconfig\n+++ b/drivers/soc/bcm/bcm63xx/Kconfig\n@@ -10,3 +10,12 @@ config BCM63XX_POWER\n \t  BCM6318, BCM6328, BCM6362 and BCM63268 SoCs.\n \n endif # SOC_BCM63XX\n+\n+config BCM_PMB\n+\tbool \"Broadcom PMB (Power Management Bus) driver\"\n+\tdepends on ARCH_BCM4908 || (COMPILE_TEST && OF)\n+\tdefault ARCH_BCM4908\n+\tselect PM_GENERIC_DOMAINS if PM\n+\thelp\n+\t  This enables support for the Broadcom's PMB (Power Management Bus) that\n+\t  is used for disabling and enabling SoC devices.\n--- a/drivers/soc/bcm/bcm63xx/Makefile\n+++ b/drivers/soc/bcm/bcm63xx/Makefile\n@@ -1,2 +1,3 @@\n # SPDX-License-Identifier: GPL-2.0-only\n obj-$(CONFIG_BCM63XX_POWER) += bcm63xx-power.o\n+obj-$(CONFIG_BCM_PMB)\t\t+= bcm-pmb.o\n--- /dev/null\n+++ b/drivers/soc/bcm/bcm63xx/bcm-pmb.c\n@@ -0,0 +1,333 @@\n+// SPDX-License-Identifier: GPL-2.0-or-later\n+/*\n+ * Copyright (c) 2013 Broadcom\n+ * Copyright (C) 2020 Rafał Miłecki <rafal@milecki.pl>\n+ */\n+\n+#include <dt-bindings/soc/bcm-pmb.h>\n+#include <linux/io.h>\n+#include <linux/module.h>\n+#include <linux/of.h>\n+#include <linux/of_device.h>\n+#include <linux/platform_device.h>\n+#include <linux/pm_domain.h>\n+#include <linux/reset/bcm63xx_pmb.h>\n+\n+#define BPCM_ID_REG\t\t\t\t\t0x00\n+#define BPCM_CAPABILITIES\t\t\t\t0x04\n+#define  BPCM_CAP_NUM_ZONES\t\t\t\t0x000000ff\n+#define  BPCM_CAP_SR_REG_BITS\t\t\t\t0x0000ff00\n+#define  BPCM_CAP_PLLTYPE\t\t\t\t0x00030000\n+#define  BPCM_CAP_UBUS\t\t\t\t\t0x00080000\n+#define BPCM_CONTROL\t\t\t\t\t0x08\n+#define BPCM_STATUS\t\t\t\t\t0x0c\n+#define BPCM_ROSC_CONTROL\t\t\t\t0x10\n+#define BPCM_ROSC_THRESH_H\t\t\t\t0x14\n+#define BPCM_ROSC_THRESHOLD_BCM6838\t\t\t0x14\n+#define BPCM_ROSC_THRESH_S\t\t\t\t0x18\n+#define BPCM_ROSC_COUNT_BCM6838\t\t\t\t0x18\n+#define BPCM_ROSC_COUNT\t\t\t\t\t0x1c\n+#define BPCM_PWD_CONTROL_BCM6838\t\t\t0x1c\n+#define BPCM_PWD_CONTROL\t\t\t\t0x20\n+#define BPCM_SR_CONTROL_BCM6838\t\t\t\t0x20\n+#define BPCM_PWD_ACCUM_CONTROL\t\t\t\t0x24\n+#define BPCM_SR_CONTROL\t\t\t\t\t0x28\n+#define BPCM_GLOBAL_CONTROL\t\t\t\t0x2c\n+#define BPCM_MISC_CONTROL\t\t\t\t0x30\n+#define BPCM_MISC_CONTROL2\t\t\t\t0x34\n+#define BPCM_SGPHY_CNTL\t\t\t\t\t0x38\n+#define BPCM_SGPHY_STATUS\t\t\t\t0x3c\n+#define BPCM_ZONE0\t\t\t\t\t0x40\n+#define  BPCM_ZONE_CONTROL\t\t\t\t0x00\n+#define   BPCM_ZONE_CONTROL_MANUAL_CLK_EN\t\t0x00000001\n+#define   BPCM_ZONE_CONTROL_MANUAL_RESET_CTL\t\t0x00000002\n+#define   BPCM_ZONE_CONTROL_FREQ_SCALE_USED\t\t0x00000004\t/* R/O */\n+#define   BPCM_ZONE_CONTROL_DPG_CAPABLE\t\t\t0x00000008\t/* R/O */\n+#define   BPCM_ZONE_CONTROL_MANUAL_MEM_PWR\t\t0x00000030\n+#define   BPCM_ZONE_CONTROL_MANUAL_ISO_CTL\t\t0x00000040\n+#define   BPCM_ZONE_CONTROL_MANUAL_CTL\t\t\t0x00000080\n+#define   BPCM_ZONE_CONTROL_DPG_CTL_EN\t\t\t0x00000100\n+#define   BPCM_ZONE_CONTROL_PWR_DN_REQ\t\t\t0x00000200\n+#define   BPCM_ZONE_CONTROL_PWR_UP_REQ\t\t\t0x00000400\n+#define   BPCM_ZONE_CONTROL_MEM_PWR_CTL_EN\t\t0x00000800\n+#define   BPCM_ZONE_CONTROL_BLK_RESET_ASSERT\t\t0x00001000\n+#define   BPCM_ZONE_CONTROL_MEM_STBY\t\t\t0x00002000\n+#define   BPCM_ZONE_CONTROL_RESERVED\t\t\t0x0007c000\n+#define   BPCM_ZONE_CONTROL_PWR_CNTL_STATE\t\t0x00f80000\n+#define   BPCM_ZONE_CONTROL_FREQ_SCALAR_DYN_SEL\t\t0x01000000\t/* R/O */\n+#define   BPCM_ZONE_CONTROL_PWR_OFF_STATE\t\t0x02000000\t/* R/O */\n+#define   BPCM_ZONE_CONTROL_PWR_ON_STATE\t\t0x04000000\t/* R/O */\n+#define   BPCM_ZONE_CONTROL_PWR_GOOD\t\t\t0x08000000\t/* R/O */\n+#define   BPCM_ZONE_CONTROL_DPG_PWR_STATE\t\t0x10000000\t/* R/O */\n+#define   BPCM_ZONE_CONTROL_MEM_PWR_STATE\t\t0x20000000\t/* R/O */\n+#define   BPCM_ZONE_CONTROL_ISO_STATE\t\t\t0x40000000\t/* R/O */\n+#define   BPCM_ZONE_CONTROL_RESET_STATE\t\t\t0x80000000\t/* R/O */\n+#define  BPCM_ZONE_CONFIG1\t\t\t\t0x04\n+#define  BPCM_ZONE_CONFIG2\t\t\t\t0x08\n+#define  BPCM_ZONE_FREQ_SCALAR_CONTROL\t\t\t0x0c\n+#define  BPCM_ZONE_SIZE\t\t\t\t\t0x10\n+\n+struct bcm_pmb {\n+\tstruct device *dev;\n+\tvoid __iomem *base;\n+\tspinlock_t lock;\n+\tbool little_endian;\n+\tstruct genpd_onecell_data genpd_onecell_data;\n+};\n+\n+struct bcm_pmb_pd_data {\n+\tconst char * const name;\n+\tint id;\n+\tu8 bus;\n+\tu8 device;\n+};\n+\n+struct bcm_pmb_pm_domain {\n+\tstruct bcm_pmb *pmb;\n+\tconst struct bcm_pmb_pd_data *data;\n+\tstruct generic_pm_domain genpd;\n+};\n+\n+static int bcm_pmb_bpcm_read(struct bcm_pmb *pmb, int bus, u8 device,\n+\t\t\t     int offset, u32 *val)\n+{\n+\tvoid __iomem *base = pmb->base + bus * 0x20;\n+\tunsigned long flags;\n+\tint err;\n+\n+\tspin_lock_irqsave(&pmb->lock, flags);\n+\terr = bpcm_rd(base, device, offset, val);\n+\tspin_unlock_irqrestore(&pmb->lock, flags);\n+\n+\tif (!err)\n+\t\t*val = pmb->little_endian ? le32_to_cpu(*val) : be32_to_cpu(*val);\n+\n+\treturn err;\n+}\n+\n+static int bcm_pmb_bpcm_write(struct bcm_pmb *pmb, int bus, u8 device,\n+\t\t\t      int offset, u32 val)\n+{\n+\tvoid __iomem *base = pmb->base + bus * 0x20;\n+\tunsigned long flags;\n+\tint err;\n+\n+\tval = pmb->little_endian ? cpu_to_le32(val) : cpu_to_be32(val);\n+\n+\tspin_lock_irqsave(&pmb->lock, flags);\n+\terr = bpcm_wr(base, device, offset, val);\n+\tspin_unlock_irqrestore(&pmb->lock, flags);\n+\n+\treturn err;\n+}\n+\n+static int bcm_pmb_power_off_zone(struct bcm_pmb *pmb, int bus, u8 device,\n+\t\t\t\t  int zone)\n+{\n+\tint offset;\n+\tu32 val;\n+\tint err;\n+\n+\toffset = BPCM_ZONE0 + zone * BPCM_ZONE_SIZE + BPCM_ZONE_CONTROL;\n+\n+\terr = bcm_pmb_bpcm_read(pmb, bus, device, offset, &val);\n+\tif (err)\n+\t\treturn err;\n+\n+\tval |= BPCM_ZONE_CONTROL_PWR_DN_REQ;\n+\tval &= ~BPCM_ZONE_CONTROL_PWR_UP_REQ;\n+\n+\terr = bcm_pmb_bpcm_write(pmb, bus, device, offset, val);\n+\n+\treturn err;\n+}\n+\n+static int bcm_pmb_power_on_zone(struct bcm_pmb *pmb, int bus, u8 device,\n+\t\t\t\t int zone)\n+{\n+\tint offset;\n+\tu32 val;\n+\tint err;\n+\n+\toffset = BPCM_ZONE0 + zone * BPCM_ZONE_SIZE + BPCM_ZONE_CONTROL;\n+\n+\terr = bcm_pmb_bpcm_read(pmb, bus, device, offset, &val);\n+\tif (err)\n+\t\treturn err;\n+\n+\tif (!(val & BPCM_ZONE_CONTROL_PWR_ON_STATE)) {\n+\t\tval &= ~BPCM_ZONE_CONTROL_PWR_DN_REQ;\n+\t\tval |= BPCM_ZONE_CONTROL_DPG_CTL_EN;\n+\t\tval |= BPCM_ZONE_CONTROL_PWR_UP_REQ;\n+\t\tval |= BPCM_ZONE_CONTROL_MEM_PWR_CTL_EN;\n+\t\tval |= BPCM_ZONE_CONTROL_BLK_RESET_ASSERT;\n+\n+\t\terr = bcm_pmb_bpcm_write(pmb, bus, device, offset, val);\n+\t}\n+\n+\treturn err;\n+}\n+\n+static int bcm_pmb_power_off_device(struct bcm_pmb *pmb, int bus, u8 device)\n+{\n+\tint offset;\n+\tu32 val;\n+\tint err;\n+\n+\t/* Entire device can be powered off by powering off the 0th zone */\n+\toffset = BPCM_ZONE0 + BPCM_ZONE_CONTROL;\n+\n+\terr = bcm_pmb_bpcm_read(pmb, bus, device, offset, &val);\n+\tif (err)\n+\t\treturn err;\n+\n+\tif (!(val & BPCM_ZONE_CONTROL_PWR_OFF_STATE)) {\n+\t\tval = BPCM_ZONE_CONTROL_PWR_DN_REQ;\n+\n+\t\terr = bcm_pmb_bpcm_write(pmb, bus, device, offset, val);\n+\t}\n+\n+\treturn err;\n+}\n+\n+static int bcm_pmb_power_on_device(struct bcm_pmb *pmb, int bus, u8 device)\n+{\n+\tu32 val;\n+\tint err;\n+\tint i;\n+\n+\terr = bcm_pmb_bpcm_read(pmb, bus, device, BPCM_CAPABILITIES, &val);\n+\tif (err)\n+\t\treturn err;\n+\n+\tfor (i = 0; i < (val & BPCM_CAP_NUM_ZONES); i++) {\n+\t\terr = bcm_pmb_power_on_zone(pmb, bus, device, i);\n+\t\tif (err)\n+\t\t\treturn err;\n+\t}\n+\n+\treturn err;\n+}\n+\n+static int bcm_pmb_power_on(struct generic_pm_domain *genpd)\n+{\n+\tstruct bcm_pmb_pm_domain *pd = container_of(genpd, struct bcm_pmb_pm_domain, genpd);\n+\tconst struct bcm_pmb_pd_data *data = pd->data;\n+\tstruct bcm_pmb *pmb = pd->pmb;\n+\n+\tswitch (data->id) {\n+\tcase BCM_PMB_PCIE0:\n+\tcase BCM_PMB_PCIE1:\n+\tcase BCM_PMB_PCIE2:\n+\t\treturn bcm_pmb_power_on_zone(pmb, data->bus, data->device, 0);\n+\tcase BCM_PMB_HOST_USB:\n+\t\treturn bcm_pmb_power_on_device(pmb, data->bus, data->device);\n+\tdefault:\n+\t\tdev_err(pmb->dev, \"unsupported device id: %d\\n\", data->id);\n+\t\treturn -EINVAL;\n+\t}\n+}\n+\n+static int bcm_pmb_power_off(struct generic_pm_domain *genpd)\n+{\n+\tstruct bcm_pmb_pm_domain *pd = container_of(genpd, struct bcm_pmb_pm_domain, genpd);\n+\tconst struct bcm_pmb_pd_data *data = pd->data;\n+\tstruct bcm_pmb *pmb = pd->pmb;\n+\n+\tswitch (data->id) {\n+\tcase BCM_PMB_PCIE0:\n+\tcase BCM_PMB_PCIE1:\n+\tcase BCM_PMB_PCIE2:\n+\t\treturn bcm_pmb_power_off_zone(pmb, data->bus, data->device, 0);\n+\tcase BCM_PMB_HOST_USB:\n+\t\treturn bcm_pmb_power_off_device(pmb, data->bus, data->device);\n+\tdefault:\n+\t\tdev_err(pmb->dev, \"unsupported device id: %d\\n\", data->id);\n+\t\treturn -EINVAL;\n+\t}\n+}\n+\n+static int bcm_pmb_probe(struct platform_device *pdev)\n+{\n+\tstruct device *dev = &pdev->dev;\n+\tconst struct bcm_pmb_pd_data *table;\n+\tconst struct bcm_pmb_pd_data *e;\n+\tstruct resource *res;\n+\tstruct bcm_pmb *pmb;\n+\tint max_id;\n+\tint err;\n+\n+\tpmb = devm_kzalloc(dev, sizeof(*pmb), GFP_KERNEL);\n+\tif (!pmb)\n+\t\treturn -ENOMEM;\n+\n+\tpmb->dev = dev;\n+\n+\tres = platform_get_resource(pdev, IORESOURCE_MEM, 0);\n+\tpmb->base = devm_ioremap_resource(&pdev->dev, res);\n+\tif (IS_ERR(pmb->base))\n+\t\treturn PTR_ERR(pmb->base);\n+\n+\tspin_lock_init(&pmb->lock);\n+\n+\tpmb->little_endian = !of_device_is_big_endian(dev->of_node);\n+\n+\ttable = of_device_get_match_data(dev);\n+\tif (!table)\n+\t\treturn -EINVAL;\n+\n+\tmax_id = 0;\n+\tfor (e = table; e->name; e++)\n+\t\tmax_id = max(max_id, e->id);\n+\n+\tpmb->genpd_onecell_data.num_domains = max_id + 1;\n+\tpmb->genpd_onecell_data.domains =\n+\t\tdevm_kcalloc(dev, pmb->genpd_onecell_data.num_domains,\n+\t\t\t     sizeof(struct generic_pm_domain *), GFP_KERNEL);\n+\tif (!pmb->genpd_onecell_data.domains)\n+\t\treturn -ENOMEM;\n+\n+\tfor (e = table; e->name; e++) {\n+\t\tstruct bcm_pmb_pm_domain *pd = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL);\n+\n+\t\tpd->pmb = pmb;\n+\t\tpd->data = e;\n+\t\tpd->genpd.name = e->name;\n+\t\tpd->genpd.power_on = bcm_pmb_power_on;\n+\t\tpd->genpd.power_off = bcm_pmb_power_off;\n+\n+\t\tpm_genpd_init(&pd->genpd, NULL, true);\n+\t\tpmb->genpd_onecell_data.domains[e->id] = &pd->genpd;\n+\t}\n+\n+\terr = of_genpd_add_provider_onecell(dev->of_node, &pmb->genpd_onecell_data);\n+\tif (err) {\n+\t\tdev_err(dev, \"failed to add genpd provider: %d\\n\", err);\n+\t\treturn err;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static const struct bcm_pmb_pd_data bcm_pmb_bcm4908_data[] = {\n+\t{ .name = \"pcie2\", .id = BCM_PMB_PCIE2, .bus = 0, .device = 2, },\n+\t{ .name = \"pcie0\", .id = BCM_PMB_PCIE0, .bus = 1, .device = 14, },\n+\t{ .name = \"pcie1\", .id = BCM_PMB_PCIE1, .bus = 1, .device = 15, },\n+\t{ .name = \"usb\", .id = BCM_PMB_HOST_USB, .bus = 1, .device = 17, },\n+\t{ },\n+};\n+\n+static const struct of_device_id bcm_pmb_of_match[] = {\n+\t{ .compatible = \"brcm,bcm4908-pmb\", .data = &bcm_pmb_bcm4908_data, },\n+\t{ },\n+};\n+\n+static struct platform_driver bcm_pmb_driver = {\n+\t.driver = {\n+\t\t.name = \"bcm-pmb\",\n+\t\t.of_match_table = bcm_pmb_of_match,\n+\t},\n+\t.probe  = bcm_pmb_probe,\n+};\n+\n+builtin_platform_driver(bcm_pmb_driver);\n"
  },
  {
    "path": "target/linux/bcm4908/patches-5.10/082-v5.12-0003-soc-bcm-brcmstb-add-stubs-for-getting-platform-IDs.patch",
    "content": "From 149ae80b1d50e7db5ac7df1cdf0820017b70e716 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Thu, 14 Jan 2021 11:53:18 +0100\nSubject: [PATCH] soc: bcm: brcmstb: add stubs for getting platform IDs\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nSome brcmstb drivers may be shared with other SoC families. E.g. the\nsame USB PHY block is shared by brcmstb and BCM4908.\n\nTo avoid building brcmstb common code on non-brcmstb platforms we need\nstubs for:\n1. brcmstb_get_family_id()\n2. brcmstb_get_product_id()\n(to avoid \"undefined reference to\" errors).\n\nWith this change PHY_BRCM_USB will not have to unconditionally select\nSOC_BRCMSTB anymore.\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n include/linux/soc/brcmstb/brcmstb.h | 16 ++++++++++++++++\n 1 file changed, 16 insertions(+)\n\n--- a/include/linux/soc/brcmstb/brcmstb.h\n+++ b/include/linux/soc/brcmstb/brcmstb.h\n@@ -2,6 +2,8 @@\n #ifndef __BRCMSTB_SOC_H\n #define __BRCMSTB_SOC_H\n \n+#include <linux/kconfig.h>\n+\n static inline u32 BRCM_ID(u32 reg)\n {\n \treturn reg >> 28 ? reg >> 16 : reg >> 8;\n@@ -12,6 +14,8 @@ static inline u32 BRCM_REV(u32 reg)\n \treturn reg & 0xff;\n }\n \n+#if IS_ENABLED(CONFIG_SOC_BRCMSTB)\n+\n /*\n  * Helper functions for getting family or product id from the\n  * SoC driver.\n@@ -19,4 +23,16 @@ static inline u32 BRCM_REV(u32 reg)\n u32 brcmstb_get_family_id(void);\n u32 brcmstb_get_product_id(void);\n \n+#else\n+static inline u32 brcmstb_get_family_id(void)\n+{\n+\treturn 0;\n+}\n+\n+static inline u32 brcmstb_get_product_id(void)\n+{\n+\treturn 0;\n+}\n+#endif\n+\n #endif /* __BRCMSTB_SOC_H */\n"
  },
  {
    "path": "target/linux/bcm4908/patches-5.10/085-v5.18-0001-dt-bindings-pinctrl-Add-binding-for-BCM4908-pinctrl.patch",
    "content": "From 7b5730f0ff24b0d7d1cb660a482384a807618a46 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Mon, 24 Jan 2022 11:22:42 +0100\nSubject: [PATCH] dt-bindings: pinctrl: Add binding for BCM4908 pinctrl\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nIt's hardware block that is part of every SoC from BCM4908 family.\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nReviewed-by: Rob Herring <robh@kernel.org>\nLink: https://lore.kernel.org/r/20220124102243.14912-1-zajec5@gmail.com\nSigned-off-by: Linus Walleij <linus.walleij@linaro.org>\n---\n .../pinctrl/brcm,bcm4908-pinctrl.yaml         | 72 +++++++++++++++++++\n MAINTAINERS                                   |  7 ++\n 2 files changed, 79 insertions(+)\n create mode 100644 Documentation/devicetree/bindings/pinctrl/brcm,bcm4908-pinctrl.yaml\n\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/pinctrl/brcm,bcm4908-pinctrl.yaml\n@@ -0,0 +1,72 @@\n+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause\n+%YAML 1.2\n+---\n+$id: http://devicetree.org/schemas/pinctrl/brcm,bcm4908-pinctrl.yaml#\n+$schema: http://devicetree.org/meta-schemas/core.yaml#\n+\n+title: Broadcom BCM4908 pin controller\n+\n+maintainers:\n+  - Rafał Miłecki <rafal@milecki.pl>\n+\n+description:\n+  Binding for pin controller present on BCM4908 family SoCs.\n+\n+properties:\n+  compatible:\n+    const: brcm,bcm4908-pinctrl\n+\n+  reg:\n+    maxItems: 1\n+\n+patternProperties:\n+  '-pins$':\n+    type: object\n+    $ref: pinmux-node.yaml#\n+\n+    properties:\n+      function:\n+        enum: [ led_0, led_1, led_2, led_3, led_4, led_5, led_6, led_7, led_8,\n+                led_9, led_10, led_11, led_12, led_13, led_14, led_15, led_16,\n+                led_17, led_18, led_19, led_20, led_21, led_22, led_23, led_24,\n+                led_25, led_26, led_27, led_28, led_29, led_30, led_31,\n+                hs_uart, i2c, i2s, nand_ctrl, nand_data, emmc_ctrl, usb0_pwr,\n+                usb1_pwr ]\n+\n+      groups:\n+        minItems: 1\n+        maxItems: 2\n+        items:\n+          enum: [ led_0_grp_a, led_1_grp_a, led_2_grp_a, led_3_grp_a,\n+                  led_4_grp_a, led_5_grp_a, led_6_grp_a, led_7_grp_a,\n+                  led_8_grp_a, led_9_grp_a, led_10_grp_a, led_10_grp_b,\n+                  led_11_grp_a, led_11_grp_b, led_12_grp_a, led_12_grp_b,\n+                  led_13_grp_a, led_13_grp_b, led_14_grp_a, led_15_grp_a,\n+                  led_16_grp_a, led_17_grp_a, led_18_grp_a, led_19_grp_a,\n+                  led_20_grp_a, led_21_grp_a, led_22_grp_a, led_23_grp_a,\n+                  led_24_grp_a, led_25_grp_a, led_26_grp_a, led_27_grp_a,\n+                  led_28_grp_a, led_29_grp_a, led_30_grp_a, led_31_grp_a,\n+                  led_31_grp_b, hs_uart_grp, i2c_grp_a, i2c_grp_b, i2s_grp,\n+                  nand_ctrl_grp, nand_data_grp, emmc_ctrl_grp, usb0_pwr_grp,\n+                  usb1_pwr_grp ]\n+\n+allOf:\n+  - $ref: pinctrl.yaml#\n+\n+required:\n+  - compatible\n+  - reg\n+\n+unevaluatedProperties: false\n+\n+examples:\n+  - |\n+    pinctrl@ff800560 {\n+        compatible = \"brcm,bcm4908-pinctrl\";\n+        reg = <0xff800560 0x10>;\n+\n+        led_0-a-pins {\n+            function = \"led_0\";\n+            groups = \"led_0_grp_a\";\n+        };\n+    };\n--- a/MAINTAINERS\n+++ b/MAINTAINERS\n@@ -3436,6 +3436,13 @@ F:\tDocumentation/devicetree/bindings/net\n F:\tdrivers/net/ethernet/broadcom/bcm4908_enet.*\n F:\tdrivers/net/ethernet/broadcom/unimac.h\n \n+BROADCOM BCM4908 PINMUX DRIVER\n+M:\tRafał Miłecki <rafal@milecki.pl>\n+M:\tbcm-kernel-feedback-list@broadcom.com\n+L:\tlinux-gpio@vger.kernel.org\n+S:\tMaintained\n+F:\tDocumentation/devicetree/bindings/pinctrl/brcm,bcm4908-pinctrl.yaml\n+\n BROADCOM BCM5301X ARM ARCHITECTURE\n M:\tHauke Mehrtens <hauke@hauke-m.de>\n M:\tRafał Miłecki <zajec5@gmail.com>\n"
  },
  {
    "path": "target/linux/bcm4908/patches-5.10/085-v5.18-0002-pinctrl-bcm-add-driver-for-BCM4908-pinmux.patch",
    "content": "From f7e322d99f1180270fb4a3e1ae992b3116cfcf34 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Mon, 24 Jan 2022 11:22:43 +0100\nSubject: [PATCH] pinctrl: bcm: add driver for BCM4908 pinmux\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nBCM4908 has its own pins layout so it needs a custom binding and a Linux\ndriver.\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nReviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>\nLink: https://lore.kernel.org/r/20220124102243.14912-2-zajec5@gmail.com\nSigned-off-by: Linus Walleij <linus.walleij@linaro.org>\n---\n MAINTAINERS                           |   1 +\n drivers/pinctrl/bcm/Kconfig           |  14 +\n drivers/pinctrl/bcm/Makefile          |   1 +\n drivers/pinctrl/bcm/pinctrl-bcm4908.c | 563 ++++++++++++++++++++++++++\n 4 files changed, 579 insertions(+)\n create mode 100644 drivers/pinctrl/bcm/pinctrl-bcm4908.c\n\n--- a/MAINTAINERS\n+++ b/MAINTAINERS\n@@ -3442,6 +3442,7 @@ M:\tbcm-kernel-feedback-list@broadcom.com\n L:\tlinux-gpio@vger.kernel.org\n S:\tMaintained\n F:\tDocumentation/devicetree/bindings/pinctrl/brcm,bcm4908-pinctrl.yaml\n+F:\tdrivers/pinctrl/bcm/pinctrl-bcm4908.c\n \n BROADCOM BCM5301X ARM ARCHITECTURE\n M:\tHauke Mehrtens <hauke@hauke-m.de>\n--- a/drivers/pinctrl/bcm/Kconfig\n+++ b/drivers/pinctrl/bcm/Kconfig\n@@ -29,6 +29,20 @@ config PINCTRL_BCM2835\n \thelp\n \t   Say Y here to enable the Broadcom BCM2835 GPIO driver.\n \n+config PINCTRL_BCM4908\n+\ttristate \"Broadcom BCM4908 pinmux driver\"\n+\tdepends on OF && (ARCH_BCM4908 || COMPILE_TEST)\n+\tselect PINMUX\n+\tselect PINCONF\n+\tselect GENERIC_PINCONF\n+\tselect GENERIC_PINCTRL_GROUPS\n+\tselect GENERIC_PINMUX_FUNCTIONS\n+\tdefault ARCH_BCM4908\n+\thelp\n+\t  Driver for BCM4908 family SoCs with integrated pin controller.\n+\n+\t  If compiled as module it will be called pinctrl-bcm4908.\n+\n config PINCTRL_IPROC_GPIO\n \tbool \"Broadcom iProc GPIO (with PINCONF) driver\"\n \tdepends on OF_GPIO && (ARCH_BCM_IPROC || COMPILE_TEST)\n--- a/drivers/pinctrl/bcm/Makefile\n+++ b/drivers/pinctrl/bcm/Makefile\n@@ -3,6 +3,7 @@\n \n obj-$(CONFIG_PINCTRL_BCM281XX)\t\t+= pinctrl-bcm281xx.o\n obj-$(CONFIG_PINCTRL_BCM2835)\t\t+= pinctrl-bcm2835.o\n+obj-$(CONFIG_PINCTRL_BCM4908)\t\t+= pinctrl-bcm4908.o\n obj-$(CONFIG_PINCTRL_IPROC_GPIO)\t+= pinctrl-iproc-gpio.o\n obj-$(CONFIG_PINCTRL_CYGNUS_MUX)\t+= pinctrl-cygnus-mux.o\n obj-$(CONFIG_PINCTRL_NS)\t\t+= pinctrl-ns.o\n--- /dev/null\n+++ b/drivers/pinctrl/bcm/pinctrl-bcm4908.c\n@@ -0,0 +1,560 @@\n+// SPDX-License-Identifier: GPL-2.0\n+/* Copyright (C) 2021 Rafał Miłecki <rafal@milecki.pl> */\n+\n+#include <linux/err.h>\n+#include <linux/io.h>\n+#include <linux/mod_devicetable.h>\n+#include <linux/module.h>\n+#include <linux/pinctrl/pinconf-generic.h>\n+#include <linux/pinctrl/pinctrl.h>\n+#include <linux/pinctrl/pinmux.h>\n+#include <linux/platform_device.h>\n+#include <linux/slab.h>\n+#include <linux/string_helpers.h>\n+\n+#include \"../core.h\"\n+#include \"../pinmux.h\"\n+\n+#define BCM4908_NUM_PINS\t\t\t86\n+\n+#define BCM4908_TEST_PORT_BLOCK_EN_LSB\t\t\t0x00\n+#define BCM4908_TEST_PORT_BLOCK_DATA_MSB\t\t0x04\n+#define BCM4908_TEST_PORT_BLOCK_DATA_LSB\t\t0x08\n+#define  BCM4908_TEST_PORT_LSB_PINMUX_DATA_SHIFT\t12\n+#define BCM4908_TEST_PORT_COMMAND\t\t\t0x0c\n+#define  BCM4908_TEST_PORT_CMD_LOAD_MUX_REG\t\t0x00000021\n+\n+struct bcm4908_pinctrl {\n+\tstruct device *dev;\n+\tvoid __iomem *base;\n+\tstruct mutex mutex;\n+\tstruct pinctrl_dev *pctldev;\n+\tstruct pinctrl_desc pctldesc;\n+};\n+\n+/*\n+ * Groups\n+ */\n+\n+struct bcm4908_pinctrl_pin_setup {\n+\tunsigned int number;\n+\tunsigned int function;\n+};\n+\n+static const struct bcm4908_pinctrl_pin_setup led_0_pins_a[] = {\n+\t{ 0, 3 },\n+};\n+\n+static const struct bcm4908_pinctrl_pin_setup led_1_pins_a[] = {\n+\t{ 1, 3 },\n+};\n+\n+static const struct bcm4908_pinctrl_pin_setup led_2_pins_a[] = {\n+\t{ 2, 3 },\n+};\n+\n+static const struct bcm4908_pinctrl_pin_setup led_3_pins_a[] = {\n+\t{ 3, 3 },\n+};\n+\n+static const struct bcm4908_pinctrl_pin_setup led_4_pins_a[] = {\n+\t{ 4, 3 },\n+};\n+\n+static const struct bcm4908_pinctrl_pin_setup led_5_pins_a[] = {\n+\t{ 5, 3 },\n+};\n+\n+static const struct bcm4908_pinctrl_pin_setup led_6_pins_a[] = {\n+\t{ 6, 3 },\n+};\n+\n+static const struct bcm4908_pinctrl_pin_setup led_7_pins_a[] = {\n+\t{ 7, 3 },\n+};\n+\n+static const struct bcm4908_pinctrl_pin_setup led_8_pins_a[] = {\n+\t{ 8, 3 },\n+};\n+\n+static const struct bcm4908_pinctrl_pin_setup led_9_pins_a[] = {\n+\t{ 9, 3 },\n+};\n+\n+static const struct bcm4908_pinctrl_pin_setup led_10_pins_a[] = {\n+\t{ 10, 3 },\n+};\n+\n+static const struct bcm4908_pinctrl_pin_setup led_11_pins_a[] = {\n+\t{ 11, 3 },\n+};\n+\n+static const struct bcm4908_pinctrl_pin_setup led_12_pins_a[] = {\n+\t{ 12, 3 },\n+};\n+\n+static const struct bcm4908_pinctrl_pin_setup led_13_pins_a[] = {\n+\t{ 13, 3 },\n+};\n+\n+static const struct bcm4908_pinctrl_pin_setup led_14_pins_a[] = {\n+\t{ 14, 3 },\n+};\n+\n+static const struct bcm4908_pinctrl_pin_setup led_15_pins_a[] = {\n+\t{ 15, 3 },\n+};\n+\n+static const struct bcm4908_pinctrl_pin_setup led_16_pins_a[] = {\n+\t{ 16, 3 },\n+};\n+\n+static const struct bcm4908_pinctrl_pin_setup led_17_pins_a[] = {\n+\t{ 17, 3 },\n+};\n+\n+static const struct bcm4908_pinctrl_pin_setup led_18_pins_a[] = {\n+\t{ 18, 3 },\n+};\n+\n+static const struct bcm4908_pinctrl_pin_setup led_19_pins_a[] = {\n+\t{ 19, 3 },\n+};\n+\n+static const struct bcm4908_pinctrl_pin_setup led_20_pins_a[] = {\n+\t{ 20, 3 },\n+};\n+\n+static const struct bcm4908_pinctrl_pin_setup led_21_pins_a[] = {\n+\t{ 21, 3 },\n+};\n+\n+static const struct bcm4908_pinctrl_pin_setup led_22_pins_a[] = {\n+\t{ 22, 3 },\n+};\n+\n+static const struct bcm4908_pinctrl_pin_setup led_23_pins_a[] = {\n+\t{ 23, 3 },\n+};\n+\n+static const struct bcm4908_pinctrl_pin_setup led_24_pins_a[] = {\n+\t{ 24, 3 },\n+};\n+\n+static const struct bcm4908_pinctrl_pin_setup led_25_pins_a[] = {\n+\t{ 25, 3 },\n+};\n+\n+static const struct bcm4908_pinctrl_pin_setup led_26_pins_a[] = {\n+\t{ 26, 3 },\n+};\n+\n+static const struct bcm4908_pinctrl_pin_setup led_27_pins_a[] = {\n+\t{ 27, 3 },\n+};\n+\n+static const struct bcm4908_pinctrl_pin_setup led_28_pins_a[] = {\n+\t{ 28, 3 },\n+};\n+\n+static const struct bcm4908_pinctrl_pin_setup led_29_pins_a[] = {\n+\t{ 29, 3 },\n+};\n+\n+static const struct bcm4908_pinctrl_pin_setup led_30_pins_a[] = {\n+\t{ 30, 3 },\n+};\n+\n+static const struct bcm4908_pinctrl_pin_setup led_31_pins_a[] = {\n+\t{ 31, 3 },\n+};\n+\n+static const struct bcm4908_pinctrl_pin_setup led_10_pins_b[] = {\n+\t{ 8, 2 },\n+};\n+\n+static const struct bcm4908_pinctrl_pin_setup led_11_pins_b[] = {\n+\t{ 9, 2 },\n+};\n+\n+static const struct bcm4908_pinctrl_pin_setup led_12_pins_b[] = {\n+\t{ 0, 2 },\n+};\n+\n+static const struct bcm4908_pinctrl_pin_setup led_13_pins_b[] = {\n+\t{ 1, 2 },\n+};\n+\n+static const struct bcm4908_pinctrl_pin_setup led_31_pins_b[] = {\n+\t{ 30, 2 },\n+};\n+\n+static const struct bcm4908_pinctrl_pin_setup hs_uart_pins[] = {\n+\t{ 10, 0 },\t/* CTS */\n+\t{ 11, 0 },\t/* RTS */\n+\t{ 12, 0 },\t/* RXD */\n+\t{ 13, 0 },\t/* TXD */\n+};\n+\n+static const struct bcm4908_pinctrl_pin_setup i2c_pins_a[] = {\n+\t{ 18, 0 },\t/* SDA */\n+\t{ 19, 0 },\t/* SCL */\n+};\n+\n+static const struct bcm4908_pinctrl_pin_setup i2c_pins_b[] = {\n+\t{ 22, 0 },\t/* SDA */\n+\t{ 23, 0 },\t/* SCL */\n+};\n+\n+static const struct bcm4908_pinctrl_pin_setup i2s_pins[] = {\n+\t{ 27, 0 },\t/* MCLK */\n+\t{ 28, 0 },\t/* LRCK */\n+\t{ 29, 0 },\t/* SDATA */\n+\t{ 30, 0 },\t/* SCLK */\n+};\n+\n+static const struct bcm4908_pinctrl_pin_setup nand_ctrl_pins[] = {\n+\t{ 32, 0 },\n+\t{ 33, 0 },\n+\t{ 34, 0 },\n+\t{ 43, 0 },\n+\t{ 44, 0 },\n+\t{ 45, 0 },\n+\t{ 56, 1 },\n+};\n+\n+static const struct bcm4908_pinctrl_pin_setup nand_data_pins[] = {\n+\t{ 35, 0 },\n+\t{ 36, 0 },\n+\t{ 37, 0 },\n+\t{ 38, 0 },\n+\t{ 39, 0 },\n+\t{ 40, 0 },\n+\t{ 41, 0 },\n+\t{ 42, 0 },\n+};\n+\n+static const struct bcm4908_pinctrl_pin_setup emmc_ctrl_pins[] = {\n+\t{ 46, 0 },\n+\t{ 47, 0 },\n+};\n+\n+static const struct bcm4908_pinctrl_pin_setup usb0_pwr_pins[] = {\n+\t{ 63, 0 },\n+\t{ 64, 0 },\n+};\n+\n+static const struct bcm4908_pinctrl_pin_setup usb1_pwr_pins[] = {\n+\t{ 66, 0 },\n+\t{ 67, 0 },\n+};\n+\n+struct bcm4908_pinctrl_grp {\n+\tconst char *name;\n+\tconst struct bcm4908_pinctrl_pin_setup *pins;\n+\tconst unsigned int num_pins;\n+};\n+\n+static const struct bcm4908_pinctrl_grp bcm4908_pinctrl_grps[] = {\n+\t{ \"led_0_grp_a\", led_0_pins_a, ARRAY_SIZE(led_0_pins_a) },\n+\t{ \"led_1_grp_a\", led_1_pins_a, ARRAY_SIZE(led_1_pins_a) },\n+\t{ \"led_2_grp_a\", led_2_pins_a, ARRAY_SIZE(led_2_pins_a) },\n+\t{ \"led_3_grp_a\", led_3_pins_a, ARRAY_SIZE(led_3_pins_a) },\n+\t{ \"led_4_grp_a\", led_4_pins_a, ARRAY_SIZE(led_4_pins_a) },\n+\t{ \"led_5_grp_a\", led_5_pins_a, ARRAY_SIZE(led_5_pins_a) },\n+\t{ \"led_6_grp_a\", led_6_pins_a, ARRAY_SIZE(led_6_pins_a) },\n+\t{ \"led_7_grp_a\", led_7_pins_a, ARRAY_SIZE(led_7_pins_a) },\n+\t{ \"led_8_grp_a\", led_8_pins_a, ARRAY_SIZE(led_8_pins_a) },\n+\t{ \"led_9_grp_a\", led_9_pins_a, ARRAY_SIZE(led_9_pins_a) },\n+\t{ \"led_10_grp_a\", led_10_pins_a, ARRAY_SIZE(led_10_pins_a) },\n+\t{ \"led_11_grp_a\", led_11_pins_a, ARRAY_SIZE(led_11_pins_a) },\n+\t{ \"led_12_grp_a\", led_12_pins_a, ARRAY_SIZE(led_12_pins_a) },\n+\t{ \"led_13_grp_a\", led_13_pins_a, ARRAY_SIZE(led_13_pins_a) },\n+\t{ \"led_14_grp_a\", led_14_pins_a, ARRAY_SIZE(led_14_pins_a) },\n+\t{ \"led_15_grp_a\", led_15_pins_a, ARRAY_SIZE(led_15_pins_a) },\n+\t{ \"led_16_grp_a\", led_16_pins_a, ARRAY_SIZE(led_16_pins_a) },\n+\t{ \"led_17_grp_a\", led_17_pins_a, ARRAY_SIZE(led_17_pins_a) },\n+\t{ \"led_18_grp_a\", led_18_pins_a, ARRAY_SIZE(led_18_pins_a) },\n+\t{ \"led_19_grp_a\", led_19_pins_a, ARRAY_SIZE(led_19_pins_a) },\n+\t{ \"led_20_grp_a\", led_20_pins_a, ARRAY_SIZE(led_20_pins_a) },\n+\t{ \"led_21_grp_a\", led_21_pins_a, ARRAY_SIZE(led_21_pins_a) },\n+\t{ \"led_22_grp_a\", led_22_pins_a, ARRAY_SIZE(led_22_pins_a) },\n+\t{ \"led_23_grp_a\", led_23_pins_a, ARRAY_SIZE(led_23_pins_a) },\n+\t{ \"led_24_grp_a\", led_24_pins_a, ARRAY_SIZE(led_24_pins_a) },\n+\t{ \"led_25_grp_a\", led_25_pins_a, ARRAY_SIZE(led_25_pins_a) },\n+\t{ \"led_26_grp_a\", led_26_pins_a, ARRAY_SIZE(led_26_pins_a) },\n+\t{ \"led_27_grp_a\", led_27_pins_a, ARRAY_SIZE(led_27_pins_a) },\n+\t{ \"led_28_grp_a\", led_28_pins_a, ARRAY_SIZE(led_28_pins_a) },\n+\t{ \"led_29_grp_a\", led_29_pins_a, ARRAY_SIZE(led_29_pins_a) },\n+\t{ \"led_30_grp_a\", led_30_pins_a, ARRAY_SIZE(led_30_pins_a) },\n+\t{ \"led_31_grp_a\", led_31_pins_a, ARRAY_SIZE(led_31_pins_a) },\n+\t{ \"led_10_grp_b\", led_10_pins_b, ARRAY_SIZE(led_10_pins_b) },\n+\t{ \"led_11_grp_b\", led_11_pins_b, ARRAY_SIZE(led_11_pins_b) },\n+\t{ \"led_12_grp_b\", led_12_pins_b, ARRAY_SIZE(led_12_pins_b) },\n+\t{ \"led_13_grp_b\", led_13_pins_b, ARRAY_SIZE(led_13_pins_b) },\n+\t{ \"led_31_grp_b\", led_31_pins_b, ARRAY_SIZE(led_31_pins_b) },\n+\t{ \"hs_uart_grp\", hs_uart_pins, ARRAY_SIZE(hs_uart_pins) },\n+\t{ \"i2c_grp_a\", i2c_pins_a, ARRAY_SIZE(i2c_pins_a) },\n+\t{ \"i2c_grp_b\", i2c_pins_b, ARRAY_SIZE(i2c_pins_b) },\n+\t{ \"i2s_grp\", i2s_pins, ARRAY_SIZE(i2s_pins) },\n+\t{ \"nand_ctrl_grp\", nand_ctrl_pins, ARRAY_SIZE(nand_ctrl_pins) },\n+\t{ \"nand_data_grp\", nand_data_pins, ARRAY_SIZE(nand_data_pins) },\n+\t{ \"emmc_ctrl_grp\", emmc_ctrl_pins, ARRAY_SIZE(emmc_ctrl_pins) },\n+\t{ \"usb0_pwr_grp\", usb0_pwr_pins, ARRAY_SIZE(usb0_pwr_pins) },\n+\t{ \"usb1_pwr_grp\", usb1_pwr_pins, ARRAY_SIZE(usb1_pwr_pins) },\n+};\n+\n+/*\n+ * Functions\n+ */\n+\n+struct bcm4908_pinctrl_function {\n+\tconst char *name;\n+\tconst char * const *groups;\n+\tconst unsigned int num_groups;\n+};\n+\n+static const char * const led_0_groups[] = { \"led_0_grp_a\" };\n+static const char * const led_1_groups[] = { \"led_1_grp_a\" };\n+static const char * const led_2_groups[] = { \"led_2_grp_a\" };\n+static const char * const led_3_groups[] = { \"led_3_grp_a\" };\n+static const char * const led_4_groups[] = { \"led_4_grp_a\" };\n+static const char * const led_5_groups[] = { \"led_5_grp_a\" };\n+static const char * const led_6_groups[] = { \"led_6_grp_a\" };\n+static const char * const led_7_groups[] = { \"led_7_grp_a\" };\n+static const char * const led_8_groups[] = { \"led_8_grp_a\" };\n+static const char * const led_9_groups[] = { \"led_9_grp_a\" };\n+static const char * const led_10_groups[] = { \"led_10_grp_a\", \"led_10_grp_b\" };\n+static const char * const led_11_groups[] = { \"led_11_grp_a\", \"led_11_grp_b\" };\n+static const char * const led_12_groups[] = { \"led_12_grp_a\", \"led_12_grp_b\" };\n+static const char * const led_13_groups[] = { \"led_13_grp_a\", \"led_13_grp_b\" };\n+static const char * const led_14_groups[] = { \"led_14_grp_a\" };\n+static const char * const led_15_groups[] = { \"led_15_grp_a\" };\n+static const char * const led_16_groups[] = { \"led_16_grp_a\" };\n+static const char * const led_17_groups[] = { \"led_17_grp_a\" };\n+static const char * const led_18_groups[] = { \"led_18_grp_a\" };\n+static const char * const led_19_groups[] = { \"led_19_grp_a\" };\n+static const char * const led_20_groups[] = { \"led_20_grp_a\" };\n+static const char * const led_21_groups[] = { \"led_21_grp_a\" };\n+static const char * const led_22_groups[] = { \"led_22_grp_a\" };\n+static const char * const led_23_groups[] = { \"led_23_grp_a\" };\n+static const char * const led_24_groups[] = { \"led_24_grp_a\" };\n+static const char * const led_25_groups[] = { \"led_25_grp_a\" };\n+static const char * const led_26_groups[] = { \"led_26_grp_a\" };\n+static const char * const led_27_groups[] = { \"led_27_grp_a\" };\n+static const char * const led_28_groups[] = { \"led_28_grp_a\" };\n+static const char * const led_29_groups[] = { \"led_29_grp_a\" };\n+static const char * const led_30_groups[] = { \"led_30_grp_a\" };\n+static const char * const led_31_groups[] = { \"led_31_grp_a\", \"led_31_grp_b\" };\n+static const char * const hs_uart_groups[] = { \"hs_uart_grp\" };\n+static const char * const i2c_groups[] = { \"i2c_grp_a\", \"i2c_grp_b\" };\n+static const char * const i2s_groups[] = { \"i2s_grp\" };\n+static const char * const nand_ctrl_groups[] = { \"nand_ctrl_grp\" };\n+static const char * const nand_data_groups[] = { \"nand_data_grp\" };\n+static const char * const emmc_ctrl_groups[] = { \"emmc_ctrl_grp\" };\n+static const char * const usb0_pwr_groups[] = { \"usb0_pwr_grp\" };\n+static const char * const usb1_pwr_groups[] = { \"usb1_pwr_grp\" };\n+\n+static const struct bcm4908_pinctrl_function bcm4908_pinctrl_functions[] = {\n+\t{ \"led_0\", led_0_groups, ARRAY_SIZE(led_0_groups) },\n+\t{ \"led_1\", led_1_groups, ARRAY_SIZE(led_1_groups) },\n+\t{ \"led_2\", led_2_groups, ARRAY_SIZE(led_2_groups) },\n+\t{ \"led_3\", led_3_groups, ARRAY_SIZE(led_3_groups) },\n+\t{ \"led_4\", led_4_groups, ARRAY_SIZE(led_4_groups) },\n+\t{ \"led_5\", led_5_groups, ARRAY_SIZE(led_5_groups) },\n+\t{ \"led_6\", led_6_groups, ARRAY_SIZE(led_6_groups) },\n+\t{ \"led_7\", led_7_groups, ARRAY_SIZE(led_7_groups) },\n+\t{ \"led_8\", led_8_groups, ARRAY_SIZE(led_8_groups) },\n+\t{ \"led_9\", led_9_groups, ARRAY_SIZE(led_9_groups) },\n+\t{ \"led_10\", led_10_groups, ARRAY_SIZE(led_10_groups) },\n+\t{ \"led_11\", led_11_groups, ARRAY_SIZE(led_11_groups) },\n+\t{ \"led_12\", led_12_groups, ARRAY_SIZE(led_12_groups) },\n+\t{ \"led_13\", led_13_groups, ARRAY_SIZE(led_13_groups) },\n+\t{ \"led_14\", led_14_groups, ARRAY_SIZE(led_14_groups) },\n+\t{ \"led_15\", led_15_groups, ARRAY_SIZE(led_15_groups) },\n+\t{ \"led_16\", led_16_groups, ARRAY_SIZE(led_16_groups) },\n+\t{ \"led_17\", led_17_groups, ARRAY_SIZE(led_17_groups) },\n+\t{ \"led_18\", led_18_groups, ARRAY_SIZE(led_18_groups) },\n+\t{ \"led_19\", led_19_groups, ARRAY_SIZE(led_19_groups) },\n+\t{ \"led_20\", led_20_groups, ARRAY_SIZE(led_20_groups) },\n+\t{ \"led_21\", led_21_groups, ARRAY_SIZE(led_21_groups) },\n+\t{ \"led_22\", led_22_groups, ARRAY_SIZE(led_22_groups) },\n+\t{ \"led_23\", led_23_groups, ARRAY_SIZE(led_23_groups) },\n+\t{ \"led_24\", led_24_groups, ARRAY_SIZE(led_24_groups) },\n+\t{ \"led_25\", led_25_groups, ARRAY_SIZE(led_25_groups) },\n+\t{ \"led_26\", led_26_groups, ARRAY_SIZE(led_26_groups) },\n+\t{ \"led_27\", led_27_groups, ARRAY_SIZE(led_27_groups) },\n+\t{ \"led_28\", led_28_groups, ARRAY_SIZE(led_28_groups) },\n+\t{ \"led_29\", led_29_groups, ARRAY_SIZE(led_29_groups) },\n+\t{ \"led_30\", led_30_groups, ARRAY_SIZE(led_30_groups) },\n+\t{ \"led_31\", led_31_groups, ARRAY_SIZE(led_31_groups) },\n+\t{ \"hs_uart\", hs_uart_groups, ARRAY_SIZE(hs_uart_groups) },\n+\t{ \"i2c\", i2c_groups, ARRAY_SIZE(i2c_groups) },\n+\t{ \"i2s\", i2s_groups, ARRAY_SIZE(i2s_groups) },\n+\t{ \"nand_ctrl\", nand_ctrl_groups, ARRAY_SIZE(nand_ctrl_groups) },\n+\t{ \"nand_data\", nand_data_groups, ARRAY_SIZE(nand_data_groups) },\n+\t{ \"emmc_ctrl\", emmc_ctrl_groups, ARRAY_SIZE(emmc_ctrl_groups) },\n+\t{ \"usb0_pwr\", usb0_pwr_groups, ARRAY_SIZE(usb0_pwr_groups) },\n+\t{ \"usb1_pwr\", usb1_pwr_groups, ARRAY_SIZE(usb1_pwr_groups) },\n+};\n+\n+/*\n+ * Groups code\n+ */\n+\n+static const struct pinctrl_ops bcm4908_pinctrl_ops = {\n+\t.get_groups_count = pinctrl_generic_get_group_count,\n+\t.get_group_name = pinctrl_generic_get_group_name,\n+\t.get_group_pins = pinctrl_generic_get_group_pins,\n+\t.dt_node_to_map = pinconf_generic_dt_node_to_map_group,\n+\t.dt_free_map = pinconf_generic_dt_free_map,\n+};\n+\n+/*\n+ * Functions code\n+ */\n+\n+static int bcm4908_pinctrl_set_mux(struct pinctrl_dev *pctrl_dev,\n+\t\t\t      unsigned int func_selector,\n+\t\t\t      unsigned int group_selector)\n+{\n+\tstruct bcm4908_pinctrl *bcm4908_pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);\n+\tconst struct bcm4908_pinctrl_grp *group;\n+\tstruct group_desc *group_desc;\n+\tint i;\n+\n+\tgroup_desc = pinctrl_generic_get_group(pctrl_dev, group_selector);\n+\tif (!group_desc)\n+\t\treturn -EINVAL;\n+\tgroup = group_desc->data;\n+\n+\tmutex_lock(&bcm4908_pinctrl->mutex);\n+\tfor (i = 0; i < group->num_pins; i++) {\n+\t\tu32 lsb = 0;\n+\n+\t\tlsb |= group->pins[i].number;\n+\t\tlsb |= group->pins[i].function << BCM4908_TEST_PORT_LSB_PINMUX_DATA_SHIFT;\n+\n+\t\twritel(0x0, bcm4908_pinctrl->base + BCM4908_TEST_PORT_BLOCK_DATA_MSB);\n+\t\twritel(lsb, bcm4908_pinctrl->base + BCM4908_TEST_PORT_BLOCK_DATA_LSB);\n+\t\twritel(BCM4908_TEST_PORT_CMD_LOAD_MUX_REG,\n+\t\t       bcm4908_pinctrl->base + BCM4908_TEST_PORT_COMMAND);\n+\t}\n+\tmutex_unlock(&bcm4908_pinctrl->mutex);\n+\n+\treturn 0;\n+}\n+\n+static const struct pinmux_ops bcm4908_pinctrl_pmxops = {\n+\t.get_functions_count = pinmux_generic_get_function_count,\n+\t.get_function_name = pinmux_generic_get_function_name,\n+\t.get_function_groups = pinmux_generic_get_function_groups,\n+\t.set_mux = bcm4908_pinctrl_set_mux,\n+};\n+\n+/*\n+ * Controller code\n+ */\n+\n+static struct pinctrl_desc bcm4908_pinctrl_desc = {\n+\t.name = \"bcm4908-pinctrl\",\n+\t.pctlops = &bcm4908_pinctrl_ops,\n+\t.pmxops = &bcm4908_pinctrl_pmxops,\n+};\n+\n+static const struct of_device_id bcm4908_pinctrl_of_match_table[] = {\n+\t{ .compatible = \"brcm,bcm4908-pinctrl\", },\n+\t{ }\n+};\n+\n+static int bcm4908_pinctrl_probe(struct platform_device *pdev)\n+{\n+\tstruct device *dev = &pdev->dev;\n+\tstruct bcm4908_pinctrl *bcm4908_pinctrl;\n+\tstruct pinctrl_desc *pctldesc;\n+\tstruct pinctrl_pin_desc *pins;\n+\tint i;\n+\n+\tbcm4908_pinctrl = devm_kzalloc(dev, sizeof(*bcm4908_pinctrl), GFP_KERNEL);\n+\tif (!bcm4908_pinctrl)\n+\t\treturn -ENOMEM;\n+\tpctldesc = &bcm4908_pinctrl->pctldesc;\n+\tplatform_set_drvdata(pdev, bcm4908_pinctrl);\n+\n+\t/* Set basic properties */\n+\n+\tbcm4908_pinctrl->dev = dev;\n+\n+\tbcm4908_pinctrl->base = devm_platform_ioremap_resource(pdev, 0);\n+\tif (IS_ERR(bcm4908_pinctrl->base))\n+\t\treturn PTR_ERR(bcm4908_pinctrl->base);\n+\n+\tmutex_init(&bcm4908_pinctrl->mutex);\n+\n+\tmemcpy(pctldesc, &bcm4908_pinctrl_desc, sizeof(*pctldesc));\n+\n+\t/* Set pinctrl properties */\n+\n+\tpins = devm_kcalloc(dev, BCM4908_NUM_PINS, sizeof(*pins), GFP_KERNEL);\n+\tif (!pins)\n+\t\treturn -ENOMEM;\n+\tfor (i = 0; i < BCM4908_NUM_PINS; i++) {\n+\t\tpins[i].number = i;\n+\t\tpins[i].name = devm_kasprintf(dev, GFP_KERNEL, \"pin-%d\", i);\n+\t\tif (!pins[i].name)\n+\t\t\treturn -ENOMEM;\n+\t}\n+\tpctldesc->pins = pins;\n+\tpctldesc->npins = BCM4908_NUM_PINS;\n+\n+\t/* Register */\n+\n+\tbcm4908_pinctrl->pctldev = devm_pinctrl_register(dev, pctldesc, bcm4908_pinctrl);\n+\tif (IS_ERR(bcm4908_pinctrl->pctldev))\n+\t\treturn dev_err_probe(dev, PTR_ERR(bcm4908_pinctrl->pctldev),\n+\t\t\t\t     \"Failed to register pinctrl\\n\");\n+\n+\t/* Groups */\n+\n+\tfor (i = 0; i < ARRAY_SIZE(bcm4908_pinctrl_grps); i++) {\n+\t\tconst struct bcm4908_pinctrl_grp *group = &bcm4908_pinctrl_grps[i];\n+\t\tint *pins;\n+\t\tint j;\n+\n+\t\tpins = devm_kcalloc(dev, group->num_pins, sizeof(*pins), GFP_KERNEL);\n+\t\tif (!pins)\n+\t\t\treturn -ENOMEM;\n+\t\tfor (j = 0; j < group->num_pins; j++)\n+\t\t\tpins[j] = group->pins[j].number;\n+\n+\t\tpinctrl_generic_add_group(bcm4908_pinctrl->pctldev, group->name,\n+\t\t\t\t\t  pins, group->num_pins, (void *)group);\n+\t}\n+\n+\t/* Functions */\n+\n+\tfor (i = 0; i < ARRAY_SIZE(bcm4908_pinctrl_functions); i++) {\n+\t\tconst struct bcm4908_pinctrl_function *function = &bcm4908_pinctrl_functions[i];\n+\n+\t\tpinmux_generic_add_function(bcm4908_pinctrl->pctldev,\n+\t\t\t\t\t    function->name,\n+\t\t\t\t\t    function->groups,\n+\t\t\t\t\t    function->num_groups, NULL);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static struct platform_driver bcm4908_pinctrl_driver = {\n+\t.probe = bcm4908_pinctrl_probe,\n+\t.driver = {\n+\t\t.name = \"bcm4908-pinctrl\",\n+\t\t.of_match_table = bcm4908_pinctrl_of_match_table,\n+\t},\n+};\n+\n+module_platform_driver(bcm4908_pinctrl_driver);\n+\n+MODULE_AUTHOR(\"Rafał Miłecki\");\n+MODULE_LICENSE(\"GPL v2\");\n+MODULE_DEVICE_TABLE(of, bcm4908_pinctrl_of_match_table);\n"
  },
  {
    "path": "target/linux/bcm4908/patches-5.10/086-v5.12-0001-phy-phy-brcm-usb-improve-getting-OF-matching-data.patch",
    "content": "From d14f4cce9340a6586512a0eb6bc680dedeaaef14 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Wed, 16 Dec 2020 15:33:04 +0100\nSubject: [PATCH] phy: phy-brcm-usb: improve getting OF matching data\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\n1. Use of_device_get_match_data() helper to simplify the code\n2. Check for NULL as a good practice\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nAcked-by: Florian Fainelli <f.fainelli@gmail.com>\nLink: https://lore.kernel.org/r/20201216143305.12179-1-zajec5@gmail.com\nSigned-off-by: Vinod Koul <vkoul@kernel.org>\n---\n drivers/phy/broadcom/phy-brcm-usb.c | 7 ++++---\n 1 file changed, 4 insertions(+), 3 deletions(-)\n\n--- a/drivers/phy/broadcom/phy-brcm-usb.c\n+++ b/drivers/phy/broadcom/phy-brcm-usb.c\n@@ -11,6 +11,7 @@\n #include <linux/io.h>\n #include <linux/module.h>\n #include <linux/of.h>\n+#include <linux/of_device.h>\n #include <linux/phy/phy.h>\n #include <linux/platform_device.h>\n #include <linux/interrupt.h>\n@@ -457,7 +458,6 @@ static int brcm_usb_phy_probe(struct pla\n \tstruct device_node *dn = pdev->dev.of_node;\n \tint err;\n \tconst char *mode;\n-\tconst struct of_device_id *match;\n \tvoid (*dvr_init)(struct brcm_usb_init_params *params);\n \tconst struct match_chip_info *info;\n \tstruct regmap *rmap;\n@@ -471,8 +471,9 @@ static int brcm_usb_phy_probe(struct pla\n \tpriv->ini.family_id = brcmstb_get_family_id();\n \tpriv->ini.product_id = brcmstb_get_product_id();\n \n-\tmatch = of_match_node(brcm_usb_dt_ids, dev->of_node);\n-\tinfo = match->data;\n+\tinfo = of_device_get_match_data(&pdev->dev);\n+\tif (!info)\n+\t\treturn -ENOENT;\n \tdvr_init = info->init_func;\n \t(*dvr_init)(&priv->ini);\n \n"
  },
  {
    "path": "target/linux/bcm4908/patches-5.10/086-v5.12-0002-phy-phy-brcm-usb-specify-init-function-format-at-str.patch",
    "content": "From 915f1d230e5292bc2156a9997bcb19d9e632f10b Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Wed, 16 Dec 2020 15:33:05 +0100\nSubject: [PATCH] phy: phy-brcm-usb: specify init function format at struct\n level\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nThis is slightly cleaner solution that assures noone assings a wrong\nfunction to the pointer.\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nAcked-by: Florian Fainelli <f.fainelli@gmail.com>\nLink: https://lore.kernel.org/r/20201216143305.12179-2-zajec5@gmail.com\nSigned-off-by: Vinod Koul <vkoul@kernel.org>\n---\n drivers/phy/broadcom/phy-brcm-usb.c | 7 +++----\n 1 file changed, 3 insertions(+), 4 deletions(-)\n\n--- a/drivers/phy/broadcom/phy-brcm-usb.c\n+++ b/drivers/phy/broadcom/phy-brcm-usb.c\n@@ -36,7 +36,7 @@ struct value_to_name_map {\n };\n \n struct match_chip_info {\n-\tvoid *init_func;\n+\tvoid (*init_func)(struct brcm_usb_init_params *params);\n \tu8 required_regs[BRCM_REGS_MAX + 1];\n \tu8 optional_reg;\n };\n@@ -458,7 +458,6 @@ static int brcm_usb_phy_probe(struct pla\n \tstruct device_node *dn = pdev->dev.of_node;\n \tint err;\n \tconst char *mode;\n-\tvoid (*dvr_init)(struct brcm_usb_init_params *params);\n \tconst struct match_chip_info *info;\n \tstruct regmap *rmap;\n \tint x;\n@@ -474,8 +473,8 @@ static int brcm_usb_phy_probe(struct pla\n \tinfo = of_device_get_match_data(&pdev->dev);\n \tif (!info)\n \t\treturn -ENOENT;\n-\tdvr_init = info->init_func;\n-\t(*dvr_init)(&priv->ini);\n+\n+\tinfo->init_func(&priv->ini);\n \n \tdev_dbg(dev, \"Best mapping table is for %s\\n\",\n \t\tpriv->ini.family_name);\n"
  },
  {
    "path": "target/linux/bcm4908/patches-5.10/086-v5.12-0003-dt-bindings-phy-brcm-brcmstb-usb-phy-convert-to-the-.patch",
    "content": "From b39069a482ade0c5e18c407c3218ba1aeed371b6 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Wed, 6 Jan 2021 21:58:36 +0100\nSubject: [PATCH] dt-bindings: phy: brcm, brcmstb-usb-phy: convert to the\n json-schema\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nChanges that require mentioning:\n1. interrupt-names\n   Name \"wakeup\" was changed to the \"wake\". It matches example and what\n   Linux driver looks for in the first place\n2. brcm,ipp and brcm,ioc\n   Both were described as booleans with 0 / 1 values. In examples they\n   were integers and Linux checks for int as well. Both got uint32.\n3. Added minimal description\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nReviewed-by: Florian Fainelli <f.fainelli@gmail.com>\nReviewed-by: Rob Herring <robh@kernel.org>\nLink: https://lore.kernel.org/r/20210106205838.10964-1-zajec5@gmail.com\nSigned-off-by: Vinod Koul <vkoul@kernel.org>\n---\n .../bindings/phy/brcm,brcmstb-usb-phy.txt     |  86 --------\n .../bindings/phy/brcm,brcmstb-usb-phy.yaml    | 193 ++++++++++++++++++\n 2 files changed, 193 insertions(+), 86 deletions(-)\n delete mode 100644 Documentation/devicetree/bindings/phy/brcm,brcmstb-usb-phy.txt\n create mode 100644 Documentation/devicetree/bindings/phy/brcm,brcmstb-usb-phy.yaml\n\n--- a/Documentation/devicetree/bindings/phy/brcm,brcmstb-usb-phy.txt\n+++ /dev/null\n@@ -1,86 +0,0 @@\n-Broadcom STB USB PHY\n-\n-Required properties:\n-- compatible: should be one of\n-\t\"brcm,brcmstb-usb-phy\"\n-\t\"brcm,bcm7216-usb-phy\"\n-\t\"brcm,bcm7211-usb-phy\"\n-\n-- reg and reg-names properties requirements are specific to the\n-  compatible string.\n-  \"brcm,brcmstb-usb-phy\":\n-    - reg: 1 or 2 offset and length pairs. One for the base CTRL registers\n-           and an optional pair for systems with USB 3.x support\n-    - reg-names: not specified\n-  \"brcm,bcm7216-usb-phy\":\n-    - reg: 3 offset and length pairs for CTRL, XHCI_EC and XHCI_GBL\n-           registers\n-    - reg-names: \"ctrl\", \"xhci_ec\", \"xhci_gbl\"\n-  \"brcm,bcm7211-usb-phy\":\n-    - reg: 5 offset and length pairs for CTRL, XHCI_EC, XHCI_GBL,\n-           USB_PHY and USB_MDIO registers and an optional pair\n-\t   for the BDC registers\n-    - reg-names: \"ctrl\", \"xhci_ec\", \"xhci_gbl\", \"usb_phy\", \"usb_mdio\", \"bdc_ec\"\n-\n-- #phy-cells: Shall be 1 as it expects one argument for setting\n-\t      the type of the PHY. Possible values are:\n-\t      - PHY_TYPE_USB2 for USB1.1/2.0 PHY\n-\t      - PHY_TYPE_USB3 for USB3.x PHY\n-\n-Optional Properties:\n-- clocks : clock phandles.\n-- clock-names: String, clock name.\n-- interrupts: wakeup interrupt\n-- interrupt-names: \"wakeup\"\n-- brcm,ipp: Boolean, Invert Port Power.\n-  Possible values are: 0 (Don't invert), 1 (Invert)\n-- brcm,ioc: Boolean, Invert Over Current detection.\n-  Possible values are: 0 (Don't invert), 1 (Invert)\n-- dr_mode: String, PHY Device mode.\n-  Possible values are: \"host\", \"peripheral \", \"drd\" or \"typec-pd\"\n-  If this property is not defined, the phy will default to \"host\" mode.\n-- brcm,syscon-piarbctl: phandle to syscon for handling config registers\n-NOTE: one or both of the following two properties must be set\n-- brcm,has-xhci: Boolean indicating the phy has an XHCI phy.\n-- brcm,has-eohci: Boolean indicating the phy has an EHCI/OHCI phy.\n-\n-\n-Example:\n-\n-usbphy_0: usb-phy@f0470200 {\n-\treg = <0xf0470200 0xb8>,\n-\t\t<0xf0471940 0x6c0>;\n-\tcompatible = \"brcm,brcmstb-usb-phy\";\n-\t#phy-cells = <1>;\n-\tdr_mode = \"host\"\n-\tbrcm,ioc = <1>;\n-\tbrcm,ipp = <1>;\n-\tbrcm,has-xhci;\n-\tbrcm,has-eohci;\n-\tclocks = <&usb20>, <&usb30>;\n-\tclock-names = \"sw_usb\", \"sw_usb3\";\n-};\n-\n-usb-phy@29f0200 {\n-\treg = <0x29f0200 0x200>,\n-\t\t<0x29c0880 0x30>,\n-\t\t<0x29cc100 0x534>,\n-\t\t<0x2808000 0x24>,\n-\t\t<0x2980080 0x8>;\n-\treg-names = \"ctrl\",\n-\t\t\"xhci_ec\",\n-\t\t\"xhci_gbl\",\n-\t\t\"usb_phy\",\n-\t\t\"usb_mdio\";\n-\tbrcm,ioc = <0x0>;\n-\tbrcm,ipp = <0x0>;\n-\tcompatible = \"brcm,bcm7211-usb-phy\";\n-\tinterrupts = <0x30>;\n-\tinterrupt-parent = <&vpu_intr1_nosec_intc>;\n-\tinterrupt-names = \"wake\";\n-\t#phy-cells = <0x1>;\n-\tbrcm,has-xhci;\n-\tsyscon-piarbctl = <&syscon_piarbctl>;\n-\tclocks = <&scmi_clk 256>;\n-\tclock-names = \"sw_usb\";\n-};\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/phy/brcm,brcmstb-usb-phy.yaml\n@@ -0,0 +1,193 @@\n+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause\n+%YAML 1.2\n+---\n+$id: http://devicetree.org/schemas/phy/brcm,brcmstb-usb-phy.yaml#\n+$schema: http://devicetree.org/meta-schemas/core.yaml#\n+\n+title: Broadcom STB USB PHY\n+\n+description: Broadcom's PHY that handles EHCI/OHCI and/or XHCI\n+\n+maintainers:\n+  - Al Cooper <alcooperx@gmail.com>\n+  - Rafał Miłecki <rafal@milecki.pl>\n+\n+properties:\n+  compatible:\n+    enum:\n+      - brcm,bcm7211-usb-phy\n+      - brcm,bcm7216-usb-phy\n+      - brcm,brcmstb-usb-phy\n+\n+  reg:\n+    minItems: 1\n+    maxItems: 6\n+    items:\n+      - description: the base CTRL register\n+      - description: XHCI EC register\n+      - description: XHCI GBL register\n+      - description: USB PHY register\n+      - description: USB MDIO register\n+      - description: BDC register\n+\n+  reg-names:\n+    minItems: 1\n+    maxItems: 6\n+    items:\n+      - const: ctrl\n+      - const: xhci_ec\n+      - const: xhci_gbl\n+      - const: usb_phy\n+      - const: usb_mdio\n+      - const: bdc_ec\n+\n+  clocks:\n+    minItems: 1\n+    maxItems: 2\n+\n+  clock-names:\n+    minItems: 1\n+    maxItems: 2\n+    items:\n+      - const: sw_usb\n+      - const: sw_usb3\n+\n+  interrupts:\n+    description: wakeup interrupt\n+\n+  interrupt-names:\n+    const: wake\n+\n+  brcm,ipp:\n+    $ref: /schemas/types.yaml#/definitions/uint32\n+    description: Invert Port Power\n+    minimum: 0\n+    maximum: 1\n+\n+  brcm,ioc:\n+    $ref: /schemas/types.yaml#/definitions/uint32\n+    description: Invert Over Current detection\n+    minimum: 0\n+    maximum: 1\n+\n+  dr_mode:\n+    description: PHY Device mode. If this property is not defined, the PHY will\n+      default to \"host\" mode.\n+    enum:\n+      - host\n+      - peripheral\n+      - drd\n+      - typec-pd\n+\n+  brcm,syscon-piarbctl:\n+    description: phandle to syscon for handling config registers\n+    $ref: /schemas/types.yaml#/definitions/phandle\n+\n+  brcm,has-xhci:\n+    description: Indicates the PHY has an XHCI PHY.\n+    type: boolean\n+\n+  brcm,has-eohci:\n+    description: Indicates the PHY has an EHCI/OHCI PHY.\n+    type: boolean\n+\n+  \"#phy-cells\":\n+    description: |\n+      Cell allows setting the type of the PHY. Possible values are:\n+      - PHY_TYPE_USB2 for USB1.1/2.0 PHY\n+      - PHY_TYPE_USB3 for USB3.x PHY\n+    const: 1\n+\n+required:\n+  - reg\n+  - \"#phy-cells\"\n+\n+anyOf:\n+  - required:\n+      - brcm,has-xhci\n+  - required:\n+      - brcm,has-eohci\n+\n+allOf:\n+  - if:\n+      properties:\n+        compatible:\n+          contains:\n+            const: brcm,brcmstb-usb-phy\n+    then:\n+      properties:\n+        reg:\n+          minItems: 1\n+          maxItems: 2\n+  - if:\n+      properties:\n+        compatible:\n+          contains:\n+            const: brcm,bcm7211-usb-phy\n+    then:\n+      properties:\n+        reg:\n+          minItems: 5\n+          maxItems: 6\n+        reg-names:\n+          minItems: 5\n+          maxItems: 6\n+  - if:\n+      properties:\n+        compatible:\n+          contains:\n+            const: brcm,bcm7216-usb-phy\n+    then:\n+      properties:\n+        reg:\n+          minItems: 3\n+          maxItems: 3\n+        reg-names:\n+          minItems: 3\n+          maxItems: 3\n+\n+additionalProperties: false\n+\n+examples:\n+  - |\n+    #include <dt-bindings/phy/phy.h>\n+\n+    usb-phy@f0470200 {\n+        compatible = \"brcm,brcmstb-usb-phy\";\n+        reg = <0xf0470200 0xb8>,\n+              <0xf0471940 0x6c0>;\n+        #phy-cells = <1>;\n+        dr_mode = \"host\";\n+        brcm,ioc = <1>;\n+        brcm,ipp = <1>;\n+        brcm,has-xhci;\n+        brcm,has-eohci;\n+        clocks = <&usb20>, <&usb30>;\n+        clock-names = \"sw_usb\", \"sw_usb3\";\n+    };\n+  - |\n+    #include <dt-bindings/phy/phy.h>\n+\n+    usb-phy@29f0200 {\n+        compatible = \"brcm,bcm7211-usb-phy\";\n+        reg = <0x29f0200 0x200>,\n+              <0x29c0880 0x30>,\n+              <0x29cc100 0x534>,\n+              <0x2808000 0x24>,\n+              <0x2980080 0x8>;\n+        reg-names = \"ctrl\",\n+            \"xhci_ec\",\n+            \"xhci_gbl\",\n+            \"usb_phy\",\n+            \"usb_mdio\";\n+        brcm,ioc = <0x0>;\n+        brcm,ipp = <0x0>;\n+        interrupts = <0x30>;\n+        interrupt-parent = <&vpu_intr1_nosec_intc>;\n+        interrupt-names = \"wake\";\n+        #phy-cells = <0x1>;\n+        brcm,has-xhci;\n+        brcm,syscon-piarbctl = <&syscon_piarbctl>;\n+        clocks = <&scmi_clk 256>;\n+        clock-names = \"sw_usb\";\n+    };\n"
  },
  {
    "path": "target/linux/bcm4908/patches-5.10/086-v5.12-0004-dt-bindings-phy-brcm-brcmstb-usb-phy-add-BCM4908-bin.patch",
    "content": "From 46b616c1574def7a1629bdeded3d44e76382f950 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Wed, 6 Jan 2021 21:58:37 +0100\nSubject: [PATCH] dt-bindings: phy: brcm, brcmstb-usb-phy: add BCM4908 binding\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nBCM4908 uses the same PHY and may require just a slightly different\nprogramming.\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nAcked-by: Florian Fainelli <f.fainelli@gmail.com>\nAcked-by: Rob Herring <robh@kernel.org>\nLink: https://lore.kernel.org/r/20210106205838.10964-2-zajec5@gmail.com\nSigned-off-by: Vinod Koul <vkoul@kernel.org>\n---\n .../devicetree/bindings/phy/brcm,brcmstb-usb-phy.yaml        | 5 ++++-\n 1 file changed, 4 insertions(+), 1 deletion(-)\n\n--- a/Documentation/devicetree/bindings/phy/brcm,brcmstb-usb-phy.yaml\n+++ b/Documentation/devicetree/bindings/phy/brcm,brcmstb-usb-phy.yaml\n@@ -15,6 +15,7 @@ maintainers:\n properties:\n   compatible:\n     enum:\n+      - brcm,bcm4908-usb-phy\n       - brcm,bcm7211-usb-phy\n       - brcm,bcm7216-usb-phy\n       - brcm,brcmstb-usb-phy\n@@ -113,7 +114,9 @@ allOf:\n       properties:\n         compatible:\n           contains:\n-            const: brcm,brcmstb-usb-phy\n+            enum:\n+              - const: brcm,bcm4908-usb-phy\n+              - const: brcm,brcmstb-usb-phy\n     then:\n       properties:\n         reg:\n"
  },
  {
    "path": "target/linux/bcm4908/patches-5.10/086-v5.12-0005-phy-phy-brcm-usb-support-PHY-on-the-BCM4908.patch",
    "content": "From 4b402fa8e0b7817f3e3738d7828038f114e6899e Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Wed, 6 Jan 2021 21:58:38 +0100\nSubject: [PATCH] phy: phy-brcm-usb: support PHY on the BCM4908\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nBCM4908 seems to have slightly different registers but works when\nprogrammed just like the STB one.\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nAcked-by: Florian Fainelli <f.fainelli@gmail.com>\nLink: https://lore.kernel.org/r/20210106205838.10964-3-zajec5@gmail.com\nSigned-off-by: Vinod Koul <vkoul@kernel.org>\n---\n drivers/phy/broadcom/Kconfig        | 3 ++-\n drivers/phy/broadcom/phy-brcm-usb.c | 4 ++++\n 2 files changed, 6 insertions(+), 1 deletion(-)\n\n--- a/drivers/phy/broadcom/Kconfig\n+++ b/drivers/phy/broadcom/Kconfig\n@@ -91,10 +91,11 @@ config PHY_BRCM_SATA\n \n config PHY_BRCM_USB\n \ttristate \"Broadcom STB USB PHY driver\"\n-\tdepends on ARCH_BRCMSTB || COMPILE_TEST\n+\tdepends on ARCH_BCM4908 || ARCH_BRCMSTB || COMPILE_TEST\n \tdepends on OF\n \tselect GENERIC_PHY\n \tselect SOC_BRCMSTB\n+\tdefault ARCH_BCM4908\n \tdefault ARCH_BRCMSTB\n \thelp\n \t  Enable this to support the Broadcom STB USB PHY.\n--- a/drivers/phy/broadcom/phy-brcm-usb.c\n+++ b/drivers/phy/broadcom/phy-brcm-usb.c\n@@ -317,6 +317,10 @@ static const struct match_chip_info chip\n \n static const struct of_device_id brcm_usb_dt_ids[] = {\n \t{\n+\t\t.compatible = \"brcm,bcm4908-usb-phy\",\n+\t\t.data = &chip_info_7445,\n+\t},\n+\t{\n \t\t.compatible = \"brcm,bcm7216-usb-phy\",\n \t\t.data = &chip_info_7216,\n \t},\n"
  },
  {
    "path": "target/linux/bcm4908/patches-5.10/086-v5.13-0001-phy-phy-brcm-usb-select-SOC_BRCMSTB-on-brcmstb-only.patch",
    "content": "From 261ab1fd5c5d2d7ff7d5bab3f5db3c69c4bcea58 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Fri, 5 Mar 2021 16:24:06 +0100\nSubject: [PATCH] phy: phy-brcm-usb: select SOC_BRCMSTB on brcmstb only\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nphy-brcm-usb has some conditional init code required on selected brcmstb\ndevices. Execution of that code depends on family / product detected by\nbrcmstb soc code.\n\nFor ARCH_BCM4908 brcmstb soc code always return 0 values as ids. Don't\nbother selecting & compiling that redundant driver.\n\nDepends-on: 149ae80b1d50 (\"soc: bcm: brcmstb: add stubs for getting platform IDs\")\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nAcked-by: Florian Fainelli <f.fainelli@gmail.com>\nLink: https://lore.kernel.org/r/20210305152406.2588-1-zajec5@gmail.com\nSigned-off-by: Vinod Koul <vkoul@kernel.org>\n---\n drivers/phy/broadcom/Kconfig | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/drivers/phy/broadcom/Kconfig\n+++ b/drivers/phy/broadcom/Kconfig\n@@ -94,7 +94,7 @@ config PHY_BRCM_USB\n \tdepends on ARCH_BCM4908 || ARCH_BRCMSTB || COMPILE_TEST\n \tdepends on OF\n \tselect GENERIC_PHY\n-\tselect SOC_BRCMSTB\n+\tselect SOC_BRCMSTB if ARCH_BRCMSTB\n \tdefault ARCH_BCM4908\n \tdefault ARCH_BRCMSTB\n \thelp\n"
  },
  {
    "path": "target/linux/bcm4908/patches-5.10/086-v5.13-0002-dt-bindings-phy-brcm-brcmstb-usb-phy-add-power-domai.patch",
    "content": "From d9de0cbd5b1f6b51c92a40937945f26a35d848ff Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Tue, 9 Mar 2021 19:26:16 +0100\nSubject: [PATCH] dt-bindings: phy: brcm,brcmstb-usb-phy: add power-domains\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nOn BCM4908 USB PHY is managed using power controller so it needs\ndescribing properly using the power-domains.\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nAcked-by: Florian Fainelli <f.fainelli@gmail.com>\nLink: https://lore.kernel.org/r/20210309182616.25783-1-zajec5@gmail.com\nSigned-off-by: Vinod Koul <vkoul@kernel.org>\n---\n .../devicetree/bindings/phy/brcm,brcmstb-usb-phy.yaml          | 3 +++\n 1 file changed, 3 insertions(+)\n\n--- a/Documentation/devicetree/bindings/phy/brcm,brcmstb-usb-phy.yaml\n+++ b/Documentation/devicetree/bindings/phy/brcm,brcmstb-usb-phy.yaml\n@@ -42,6 +42,9 @@ properties:\n       - const: usb_mdio\n       - const: bdc_ec\n \n+  power-domains:\n+    maxItems: 1\n+\n   clocks:\n     minItems: 1\n     maxItems: 2\n"
  },
  {
    "path": "target/linux/bcm4908/patches-5.10/087-v5.18-0001-i2c-brcmstb-allow-compiling-on-BCM4908.patch",
    "content": "From d0aee048d648ec2d9aa7af43b127ebf847d497d5 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Fri, 11 Feb 2022 11:58:06 +0100\nSubject: [PATCH] i2c: brcmstb: allow compiling on BCM4908\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nBCM4908 SoCs use the same I2C hardware block as STB and BCM63xx devices.\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nAcked-by: Florian Fainelli <f.fainelli@gmail.com>\nSigned-off-by: Wolfram Sang <wsa@kernel.org>\n---\n drivers/i2c/busses/Kconfig | 4 ++--\n 1 file changed, 2 insertions(+), 2 deletions(-)\n\n--- a/drivers/i2c/busses/Kconfig\n+++ b/drivers/i2c/busses/Kconfig\n@@ -477,8 +477,8 @@ config I2C_BCM_KONA\n \n config I2C_BRCMSTB\n \ttristate \"BRCM Settop/DSL I2C controller\"\n-\tdepends on ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC || \\\n-\t\t   ARCH_BCM_63XX || COMPILE_TEST\n+\tdepends on ARCH_BCM2835 || ARCH_BCM4908 || ARCH_BCM_63XX || \\\n+\t\t   ARCH_BRCMSTB || BMIPS_GENERIC || COMPILE_TEST\n \tdefault y\n \thelp\n \t  If you say yes to this option, support will be included for the\n"
  },
  {
    "path": "target/linux/bcm4908/patches-5.10/088-v5.18-phy-phy-brcm-usb-fixup-BCM4908-support.patch",
    "content": "From 32942d33d63d27714ed16a4176e5a99547adb6e0 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Fri, 18 Feb 2022 18:24:59 +0100\nSubject: [PATCH] phy: phy-brcm-usb: fixup BCM4908 support\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nJust like every other family BCM4908 should get its own enum value. That\nis required to properly handle it in chipset conditional code.\n\nThe real change is excluding BCM4908 from the PLL reprogramming code\n(see brcmusb_usb3_pll_54mhz()). I'm not sure what's the BCM4908\nreference clock frequency but:\n1. BCM4908 custom driver from Broadcom's SDK doesn't reprogram PLL\n2. Doing that in Linux driver stopped PHY handling some USB 3.0 devices\n\nThis change makes USB 3.0 PHY recognize e.g.:\n1. 04e8:6860 - Samsung Electronics Co., Ltd Galaxy series, misc. (MTP mode)\n2. 1058:259f - Western Digital My Passport 259F\n\nBroadcom's STB SoCs come with a set of SUN_TOP_CTRL_* registers that\nallow reading chip family and product ids. Such a block & register is\nmissing on BCM4908 so this commit introduces \"compatible\" string\nspecific binding.\n\nFixes: 4b402fa8e0b7 (\"phy: phy-brcm-usb: support PHY on the BCM4908\")\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nReviewed-by: Florian Fainelli <f.fainelli@gmail.com>\nLink: https://lore.kernel.org/r/20220218172459.10431-1-zajec5@gmail.com\nSigned-off-by: Vinod Koul <vkoul@kernel.org>\n---\n drivers/phy/broadcom/phy-brcm-usb-init.c | 36 ++++++++++++++++++++++++\n drivers/phy/broadcom/phy-brcm-usb-init.h |  1 +\n drivers/phy/broadcom/phy-brcm-usb.c      | 11 +++++++-\n 3 files changed, 47 insertions(+), 1 deletion(-)\n\n--- a/drivers/phy/broadcom/phy-brcm-usb-init.c\n+++ b/drivers/phy/broadcom/phy-brcm-usb-init.c\n@@ -79,6 +79,7 @@\n \n enum brcm_family_type {\n \tBRCM_FAMILY_3390A0,\n+\tBRCM_FAMILY_4908,\n \tBRCM_FAMILY_7250B0,\n \tBRCM_FAMILY_7271A0,\n \tBRCM_FAMILY_7364A0,\n@@ -96,6 +97,7 @@ enum brcm_family_type {\n \n static const char *family_names[BRCM_FAMILY_COUNT] = {\n \tUSB_BRCM_FAMILY(3390A0),\n+\tUSB_BRCM_FAMILY(4908),\n \tUSB_BRCM_FAMILY(7250B0),\n \tUSB_BRCM_FAMILY(7271A0),\n \tUSB_BRCM_FAMILY(7364A0),\n@@ -203,6 +205,27 @@ usb_reg_bits_map_table[BRCM_FAMILY_COUNT\n \t\tUSB_CTRL_USB_PM_USB20_HC_RESETB_VAR_MASK,\n \t\tENDIAN_SETTINGS, /* USB_CTRL_SETUP ENDIAN bits */\n \t},\n+\t/* 4908 */\n+\t[BRCM_FAMILY_4908] = {\n+\t\t0, /* USB_CTRL_SETUP_SCB1_EN_MASK */\n+\t\t0, /* USB_CTRL_SETUP_SCB2_EN_MASK */\n+\t\t0, /* USB_CTRL_SETUP_SS_EHCI64BIT_EN_MASK */\n+\t\t0, /* USB_CTRL_SETUP_STRAP_IPP_SEL_MASK */\n+\t\t0, /* USB_CTRL_SETUP_OC3_DISABLE_MASK */\n+\t\t0, /* USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK */\n+\t\t0, /* USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK */\n+\t\tUSB_CTRL_USB_PM_XHC_SOFT_RESETB_MASK,\n+\t\tUSB_CTRL_USB_PM_USB_PWRDN_MASK,\n+\t\t0, /* USB_CTRL_USB30_CTL1_XHC_SOFT_RESETB_MASK */\n+\t\t0, /* USB_CTRL_USB30_CTL1_USB3_IOC_MASK */\n+\t\t0, /* USB_CTRL_USB30_CTL1_USB3_IPP_MASK */\n+\t\t0, /* USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_MASK */\n+\t\t0, /* USB_CTRL_USB_PM_SOFT_RESET_MASK */\n+\t\t0, /* USB_CTRL_SETUP_CC_DRD_MODE_ENABLE_MASK */\n+\t\t0, /* USB_CTRL_SETUP_STRAP_CC_DRD_MODE_ENABLE_SEL_MASK */\n+\t\t0, /* USB_CTRL_USB_PM_USB20_HC_RESETB_VAR_MASK */\n+\t\t0, /* USB_CTRL_SETUP ENDIAN bits */\n+\t},\n \t/* 7250b0 */\n \t[BRCM_FAMILY_7250B0] = {\n \t\tUSB_CTRL_SETUP_SCB1_EN_MASK,\n@@ -559,6 +582,7 @@ static void brcmusb_usb3_pll_54mhz(struc\n \t */\n \tswitch (params->selected_family) {\n \tcase BRCM_FAMILY_3390A0:\n+\tcase BRCM_FAMILY_4908:\n \tcase BRCM_FAMILY_7250B0:\n \tcase BRCM_FAMILY_7366C0:\n \tcase BRCM_FAMILY_74371A0:\n@@ -1004,6 +1028,18 @@ static const struct brcm_usb_init_ops bc\n \t.set_dual_select = usb_set_dual_select,\n };\n \n+void brcm_usb_dvr_init_4908(struct brcm_usb_init_params *params)\n+{\n+\tint fam;\n+\n+\tfam = BRCM_FAMILY_4908;\n+\tparams->selected_family = fam;\n+\tparams->usb_reg_bits_map =\n+\t\t&usb_reg_bits_map_table[fam][0];\n+\tparams->family_name = family_names[fam];\n+\tparams->ops = &bcm7445_ops;\n+}\n+\n void brcm_usb_dvr_init_7445(struct brcm_usb_init_params *params)\n {\n \tint fam;\n--- a/drivers/phy/broadcom/phy-brcm-usb-init.h\n+++ b/drivers/phy/broadcom/phy-brcm-usb-init.h\n@@ -64,6 +64,7 @@ struct  brcm_usb_init_params {\n \tbool suspend_with_clocks;\n };\n \n+void brcm_usb_dvr_init_4908(struct brcm_usb_init_params *params);\n void brcm_usb_dvr_init_7445(struct brcm_usb_init_params *params);\n void brcm_usb_dvr_init_7216(struct brcm_usb_init_params *params);\n void brcm_usb_dvr_init_7211b0(struct brcm_usb_init_params *params);\n--- a/drivers/phy/broadcom/phy-brcm-usb.c\n+++ b/drivers/phy/broadcom/phy-brcm-usb.c\n@@ -283,6 +283,15 @@ static const struct attribute_group brcm\n \t.attrs = brcm_usb_phy_attrs,\n };\n \n+static const struct match_chip_info chip_info_4908 = {\n+\t.init_func = &brcm_usb_dvr_init_4908,\n+\t.required_regs = {\n+\t\tBRCM_REGS_CTRL,\n+\t\tBRCM_REGS_XHCI_EC,\n+\t\t-1,\n+\t},\n+};\n+\n static const struct match_chip_info chip_info_7216 = {\n \t.init_func = &brcm_usb_dvr_init_7216,\n \t.required_regs = {\n@@ -318,7 +327,7 @@ static const struct match_chip_info chip\n static const struct of_device_id brcm_usb_dt_ids[] = {\n \t{\n \t\t.compatible = \"brcm,bcm4908-usb-phy\",\n-\t\t.data = &chip_info_7445,\n+\t\t.data = &chip_info_4908,\n \t},\n \t{\n \t\t.compatible = \"brcm,bcm7216-usb-phy\",\n"
  },
  {
    "path": "target/linux/bcm4908/patches-5.10/170-net-broadcom-bcm4908_enet-reset-DMA-rings-sw-indexes.patch",
    "content": "From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Tue, 22 Jun 2021 07:05:04 +0200\nSubject: [PATCH] net: broadcom: bcm4908_enet: reset DMA rings sw indexes\n properly\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nResetting software indexes in bcm4908_dma_alloc_buf_descs() is not\nenough as it's called during device probe only. Driver resets DMA on\nevery .ndo_open callback and it's required to reset indexes then.\n\nThis fixes inconsistent rings state and stalled traffic after interface\ndown & up sequence.\n\nFixes: 4feffeadbcb2 (\"net: broadcom: bcm4908enet: add BCM4908 controller driver\")\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\n---\n drivers/net/ethernet/broadcom/bcm4908_enet.c | 6 +++---\n 1 file changed, 3 insertions(+), 3 deletions(-)\n\n--- a/drivers/net/ethernet/broadcom/bcm4908_enet.c\n+++ b/drivers/net/ethernet/broadcom/bcm4908_enet.c\n@@ -174,9 +174,6 @@ static int bcm4908_dma_alloc_buf_descs(s\n \tif (!ring->slots)\n \t\tgoto err_free_buf_descs;\n \n-\tring->read_idx = 0;\n-\tring->write_idx = 0;\n-\n \treturn 0;\n \n err_free_buf_descs:\n@@ -303,6 +300,9 @@ static void bcm4908_enet_dma_ring_init(s\n \n \tenet_write(enet, ring->st_ram_block + ENET_DMA_CH_STATE_RAM_BASE_DESC_PTR,\n \t\t   (uint32_t)ring->dma_addr);\n+\n+\tring->read_idx = 0;\n+\tring->write_idx = 0;\n }\n \n static void bcm4908_enet_dma_uninit(struct bcm4908_enet *enet)\n"
  },
  {
    "path": "target/linux/bcm4908/patches-5.10/181-watchdog-allow-building-BCM7038_WDT-for-BCM4908.patch",
    "content": "From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Wed, 9 Feb 2022 21:32:02 +0100\nSubject: [PATCH] watchdog: allow building BCM7038_WDT for BCM4908\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nBCM4908 is a SoCs family that shares a lot of hardware with BCM63xx\nincluding the watchdog block. Allow building this driver for it.\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nAcked-by: Florian Fainelli <f.fainelli@gmail.com>\nReviewed-by: Guenter Roeck <linux@roeck-us.net>\n---\n drivers/watchdog/Kconfig | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/drivers/watchdog/Kconfig\n+++ b/drivers/watchdog/Kconfig\n@@ -1800,7 +1800,7 @@ config BCM7038_WDT\n \ttristate \"BCM7038 Watchdog\"\n \tselect WATCHDOG_CORE\n \tdepends on HAS_IOMEM\n-\tdepends on ARCH_BRCMSTB || BMIPS_GENERIC || COMPILE_TEST\n+\tdepends on ARCH_BCM4908 || ARCH_BRCMSTB || BMIPS_GENERIC || COMPILE_TEST\n \thelp\n \t Watchdog driver for the built-in hardware in Broadcom 7038 and\n \t later SoCs used in set-top boxes.  BCM7038 was made public\n"
  },
  {
    "path": "target/linux/bcm4908/patches-5.10/182-watchdog-bcm7038_wdt-Support-BCM6345-compatible-stri.patch",
    "content": "From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Wed, 16 Feb 2022 07:28:34 +0100\nSubject: [PATCH] watchdog: bcm7038_wdt: Support BCM6345 compatible string\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nA new \"compatible\" value has been added in the commit 17fffe91ba36\n(\"dt-bindings: watchdog: Add BCM6345 compatible to BCM7038 binding\").\nIt's meant to be used for BCM63xx SoCs family but hardware block can be\nprogrammed just like the 7038 one.\n\nCc: Florian Fainelli <f.fainelli@gmail.com>\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\n---\n drivers/watchdog/bcm7038_wdt.c | 1 +\n 1 file changed, 1 insertion(+)\n\n--- a/drivers/watchdog/bcm7038_wdt.c\n+++ b/drivers/watchdog/bcm7038_wdt.c\n@@ -193,6 +193,7 @@ static SIMPLE_DEV_PM_OPS(bcm7038_wdt_pm_\n \t\t\t bcm7038_wdt_resume);\n \n static const struct of_device_id bcm7038_wdt_match[] = {\n+\t{ .compatible = \"brcm,bcm6345-wdt\" },\n \t{ .compatible = \"brcm,bcm7038-wdt\" },\n \t{},\n };\n"
  },
  {
    "path": "target/linux/bcm4908/patches-5.10/300-arm64-dts-broadcom-bcm4908-limit-amount-of-GPIOs.patch",
    "content": "From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Mon, 15 Feb 2021 22:01:03 +0100\nSubject: [PATCH] arm64: dts: broadcom: bcm4908: limit amount of GPIOs\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nLinux driver can't handle more than 64 GPIOs\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\n---\n\n--- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi\n+++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi\n@@ -290,7 +290,7 @@\n \t\tgpio0: gpio-controller@500 {\n \t\t\tcompatible = \"brcm,bcm6345-gpio\";\n \t\t\treg-names = \"dirout\", \"dat\";\n-\t\t\treg = <0x500 0x28>, <0x528 0x28>;\n+\t\t\treg = <0x500 0x8>, <0x528 0x8>;\n \n \t\t\t#gpio-cells = <2>;\n \t\t\tgpio-controller;\n"
  },
  {
    "path": "target/linux/bcm4908/patches-5.10/400-mtd-rawnand-brcmnand-disable-WP-on-BCM4908.patch",
    "content": "From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Thu, 21 Jan 2021 10:44:53 +0100\nSubject: [PATCH] mtd: rawnand: brcmnand: disable WP on BCM4908\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nBCM4908 contains NAND controller version 0x0701 (v7.1). It means that\nNAND_WP should be available.\n\nFor some reason setting #WP on doesn't result in clearing NAND_STATUS_WP\nstatus bit:\n[    1.077857] bcm63138_nand ff801800.nand: timeout on status poll (expected c0000040 got c00000c0)\n[    1.086832] bcm63138_nand ff801800.nand: nand #WP expected on\n\nFor now try working without touching #WP.\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\n---\n\n--- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c\n+++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c\n@@ -37,7 +37,11 @@\n  * 1: NAND_WP is set by default, cleared for erase/write operations\n  * 2: NAND_WP is always cleared\n  */\n+#if IS_ENABLED(CONFIG_ARCH_BCM4908)\n+static int wp_on = 0;\n+#else\n static int wp_on = 1;\n+#endif\n module_param(wp_on, int, 0444);\n \n /***********************************************************************\n"
  },
  {
    "path": "target/linux/bcm4908/patches-5.10/700-net-dsa-bcm_sf2-enable-GPHY-for-switch-probing.patch",
    "content": "From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Mon, 15 Feb 2021 23:59:26 +0100\nSubject: [PATCH] net: dsa: bcm_sf2: enable GPHY for switch probing\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nGPHY needs to be enabled to succesfully probe & setup switch port\nconnected to it. Otherwise hardcoding PHY OUI would be required.\n\nBefore:\nbrcm-sf2 80080000.switch lan4 (uninitialized): PHY [800c05c0.mdio--1:08] driver [Generic PHY] (irq=POLL)\nbrcm-sf2 80080000.switch lan3 (uninitialized): PHY [800c05c0.mdio--1:09] driver [Generic PHY] (irq=POLL)\nbrcm-sf2 80080000.switch lan2 (uninitialized): PHY [800c05c0.mdio--1:0a] driver [Generic PHY] (irq=POLL)\nbrcm-sf2 80080000.switch lan1 (uninitialized): PHY [800c05c0.mdio--1:0b] driver [Generic PHY] (irq=POLL)\nbrcm-sf2 80080000.switch wan (uninitialized): error -5 setting up PHY for tree 0, switch 0, port 7\n\nAfter:\nbrcm-sf2 80080000.switch lan4 (uninitialized): PHY [800c05c0.mdio--1:08] driver [Generic PHY] (irq=POLL)\nbrcm-sf2 80080000.switch lan3 (uninitialized): PHY [800c05c0.mdio--1:09] driver [Generic PHY] (irq=POLL)\nbrcm-sf2 80080000.switch lan2 (uninitialized): PHY [800c05c0.mdio--1:0a] driver [Generic PHY] (irq=POLL)\nbrcm-sf2 80080000.switch lan1 (uninitialized): PHY [800c05c0.mdio--1:0b] driver [Generic PHY] (irq=POLL)\nbrcm-sf2 80080000.switch wan (uninitialized): PHY [800c05c0.mdio--1:0c] driver [Generic PHY] (irq=POLL)\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\n---\n drivers/net/dsa/bcm_sf2.c | 4 ++++\n 1 file changed, 4 insertions(+)\n\n--- a/drivers/net/dsa/bcm_sf2.c\n+++ b/drivers/net/dsa/bcm_sf2.c\n@@ -1532,10 +1532,14 @@ static int bcm_sf2_sw_probe(struct platf\n \trev = reg_readl(priv, REG_PHY_REVISION);\n \tpriv->hw_params.gphy_rev = rev & PHY_REVISION_MASK;\n \n+\tbcm_sf2_gphy_enable_set(priv->dev->ds, true);\n+\n \tret = b53_switch_register(dev);\n \tif (ret)\n \t\tgoto out_mdio;\n \n+\tbcm_sf2_gphy_enable_set(priv->dev->ds, false);\n+\n \tdev_info(&pdev->dev,\n \t\t \"Starfighter 2 top: %x.%02x, core: %x.%02x, IRQs: %d, %d\\n\",\n \t\t priv->hw_params.top_rev >> 8, priv->hw_params.top_rev & 0xff,\n"
  },
  {
    "path": "target/linux/bcm4908/patches-5.10/701-net-dsa-bcm_sf2-keep-GPHY-enabled-on-the-BCM4908.patch",
    "content": "From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Tue, 16 Feb 2021 00:06:35 +0100\nSubject: [PATCH] net: dsa: bcm_sf2: keep GPHY enabled on the BCM4908\n\nTrying to access disabled PHY results in MDIO_READ_FAIL and:\n[   11.962886] brcm-sf2 80080000.switch wan: configuring for phy/internal link mode\n[   11.972500] 8021q: adding VLAN 0 to HW filter on device wan\n[   11.980205] ------------[ cut here ]------------\n[   11.984885] WARNING: CPU: 0 PID: 7 at phy_error+0x10/0x58\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\n---\n drivers/net/dsa/bcm_sf2.c | 6 ++++++\n 1 file changed, 6 insertions(+)\n\n--- a/drivers/net/dsa/bcm_sf2.c\n+++ b/drivers/net/dsa/bcm_sf2.c\n@@ -1546,6 +1546,12 @@ static int bcm_sf2_sw_probe(struct platf\n \t\t priv->hw_params.core_rev >> 8, priv->hw_params.core_rev & 0xff,\n \t\t priv->irq0, priv->irq1);\n \n+\t/* BCM4908 has 5 GPHYs which means bcm_sf2_port_setup() will not enable\n+\t * GPHY when needed. Leave it enabled here.\n+\t */\n+\tif (priv->type == BCM4908_DEVICE_ID)\n+\t\tbcm_sf2_gphy_enable_set(priv->dev->ds, true);\n+\n \treturn 0;\n \n out_mdio:\n"
  },
  {
    "path": "target/linux/bcm53xx/Makefile",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2013 OpenWrt.org\n\ninclude $(TOPDIR)/rules.mk\n\nARCH:=arm\nBOARD:=bcm53xx\nBOARDNAME:=Broadcom BCM47xx/53xx (ARM)\nFEATURES:=squashfs nand usb pci pcie gpio pwm\nCPU_TYPE:=cortex-a9\nSUBTARGETS:=generic\n\nKERNEL_PATCHVER:=5.10\nKERNEL_TESTING_PATCHVER:=5.15\n\ndefine Target/Description\n\tBuild firmware images for Broadcom based BCM47xx/53xx routers with ARM CPU, *not* MIPS.\nendef\n\ninclude $(INCLUDE_DIR)/target.mk\n\nKERNELNAME:=zImage dtbs\n\nDEFAULT_PACKAGES += nvram \\\n\tosafeloader oseama otrx \\\n\tkmod-gpio-button-hotplug \\\n\tkmod-leds-gpio\n\n$(eval $(call BuildTarget))\n"
  },
  {
    "path": "target/linux/bcm53xx/base-files/etc/board.d/01_leds",
    "content": "\n. /lib/functions/uci-defaults.sh\n\nboard_config_update\n\ncase \"$(board_name)\" in\nnetgear,r8000)\n\tucidef_set_led_usbport \"usb2\" \"USB 2.0\" \"bcm53xx:white:usb2\" \"usb1-port2\" \"usb2-port2\"\n\tucidef_set_led_usbport \"usb3\" \"USB 3.0\" \"bcm53xx:white:usb3\" \"usb1-port1\" \"usb2-port1\" \"usb4-port1\"\n\t;;\nesac\n\nboard_config_flush\n\nexit 0\n"
  },
  {
    "path": "target/linux/bcm53xx/base-files/etc/board.d/02_network",
    "content": "#\n# Copyright (C) 2011 OpenWrt.org\n#\n\n. /lib/functions/system.sh\n. /lib/functions/uci-defaults.sh\n\nbcm53xx_setup_interfaces()\n{\n\tlocal board=\"$1\"\n\n\tcase \"$board\" in\n\tasus,rt-ac87u)\n\t\tucidef_set_interfaces_lan_wan \"lan1 lan2 lan3\" \"wan\"\n\t\t;;\n\tasus,rt-ac88u)\n\t\tucidef_set_interfaces_lan_wan \"lan1 lan2 lan3 lan4 extsw\" \"wan\"\n\t\t;;\n\tlinksys,panamera)\n\t\tucidef_set_interfaces_lan_wan \"lan1 lan2 lan3 lan4 lan5 lan6 lan7 lan8 extsw\" \"wan\"\n\t\t;;\n\tluxul,xap-1610-v1)\n\t\tucidef_set_interface_lan \"poe lan\" \"dhcp\"\n\t\t;;\n\tmeraki,mr32)\n\t\tucidef_set_interface_lan \"poe\" \"dhcp\"\n\t\t;;\n\tphicomm,k3)\n\t\tucidef_set_interfaces_lan_wan \"lan1 lan2 lan3\" \"wan\"\n\t\t;;\n\t*)\n\t\tucidef_set_interfaces_lan_wan \"lan1 lan2 lan3 lan4\" \"wan\"\n\t\t;;\n\tesac\n}\n\nbcm53xx_setup_macs()\n{\n\tlocal board=\"$1\"\n\n\twan_macaddr=\"$(nvram get wan_hwaddr)\"\n\n\tcase \"$board\" in\n\tasus,rt-ac87u)\n\t\tetXmacaddr=$(nvram get et1macaddr)\n\t\toffset=1\n\t\t;;\n\tdlink,dir-885l | \\\n\tlinksys,panamera | \\\n\tnetgear,r7900 | \\\n\tnetgear,r8000 | \\\n\tnetgear,r8500)\n\t\tetXmacaddr=$(nvram get et2macaddr)\n\t\toffset=1\n\t\t;;\n\tluxul,xwr-3100v1 | \\\n\tluxul,xwr-3150-v1)\n\t\tetXmacaddr=$(nvram get et0macaddr)\n\t\toffset=5\n\t\t;;\n\t*)\n\t\tetXmacaddr=$(nvram get et0macaddr)\n\t\toffset=1\n\t\t;;\n\tesac\n\n\t# If WAN MAC isn't explicitly set, calculate it using base MAC as reference.\n\t[ -z \"$wan_macaddr\" -a -n \"$etXmacaddr\" ] && wan_macaddr=$(macaddr_add \"$etXmacaddr\" $offset)\n\n\t[ -n \"$wan_macaddr\" ] && ucidef_set_interface_macaddr \"wan\" \"$wan_macaddr\"\n}\n\nboard_config_update\nboard=$(board_name)\nbcm53xx_setup_interfaces \"$board\"\nbcm53xx_setup_macs \"$board\"\nboard_config_flush\n\nexit 0\n"
  },
  {
    "path": "target/linux/bcm53xx/base-files/etc/diag.sh",
    "content": "#!/bin/sh\n\n. /lib/functions/leds.sh\n\nget_status_led() {\n\tlocal status_led_file\n\n\t# There may be more than one color of power LED, try to avoid amber/red\n\tstatus_led_file=$(find /sys/class/leds/ -name \"*:power\" -a ! -name \"*:amber:*\" -a ! -name \"*:red:*\" | head -n1)\n\tif [ -d \"$status_led_file\" ]; then\n\t\tstatus_led=$(basename $status_led_file)\n\t\treturn\n\tfi;\n\n\t# Now just pick any power LED\n\tstatus_led_file=$(find /sys/class/leds/ -name \"*:power\" | head -n1)\n\tif [ -d \"$status_led_file\" ]; then\n\t\tstatus_led=$(basename $status_led_file)\n\t\treturn\n\tfi;\n}\n\nset_state() {\n\tget_status_led\n\n\t[ -z \"$status_led\" ] && return\n\n\tcase \"$1\" in\n\tpreinit)\n\t\tstatus_led_blink_preinit\n\t\t;;\n\tfailsafe)\n\t\tstatus_led_blink_failsafe\n\t\t;;\n\tpreinit_regular)\n\t\tstatus_led_blink_preinit_regular\n\t\t;;\n\tdone)\n\t\tstatus_led_on\n\t\t;;\n\tesac\n}\n"
  },
  {
    "path": "target/linux/bcm53xx/base-files/etc/uci-defaults/03_dsa_migrate",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n\n# Exit if network doesn't contain any swconfig section\nuci -q get network.@switch[0] > /dev/null || exit 0\n\nlan_proto=\"$(uci -q get network.lan.proto)\"\nlan_ipaddr=\"$(uci -q get network.lan.ipaddr)\"\nlan_netmask=\"$(uci -q get network.lan.netmask)\"\nwan_proto=\"$(uci -q get network.wan.proto)\"\nwan_ipaddr=\"$(uci -q get network.wan.ipaddr)\"\nwan_netmask=\"$(uci -q get network.wan.netmask)\"\n\nrm /etc/config/network\nconfig_generate\n\nuci -q batch <<-EOF\n\tset network.lan.proto=\"$lan_proto\"\n\tset network.lan.ipaddr=\"$lan_ipaddr\"\n\tset network.lan.netmask=\"$lan_netmask\"\n\tset network.wan.proto=\"$wan_proto\"\n\tset network.wan.ipaddr=\"$wan_ipaddr\"\n\tset network.wan.netmask=\"$wan_netmask\"\nEOF\n"
  },
  {
    "path": "target/linux/bcm53xx/base-files/etc/uci-defaults/09_fix_crc",
    "content": "kernel_size=$(sed -n 's/mtd[0-9]*: \\([0-9a-f]*\\).*\"\\(kernel\\|linux\\)\".*/\\1/p' /proc/mtd)\n\nmtd ${kernel_size:+-c 0x$kernel_size} fixtrx firmware && exit 0\nmtd ${kernel_size:+-c 0x$kernel_size} fixseama firmware && exit 0\nexit 1\n"
  },
  {
    "path": "target/linux/bcm53xx/base-files/lib/preinit/07_set_preinit_iface_bcm53xx",
    "content": "set_preinit_iface() {\n\t. /lib/functions.sh\n\n\tcase $(board_name) in\n\tmeraki,mr32)\n\t\t# switch needs to be out of the vlan mode.\n\t\tswconfig dev switch0 set reset 1\n\t\tswconfig dev switch0 set enable_vlan 0\n\t\tswconfig dev switch0 set apply 1\n\t\t;;\n\tesac\n}\n\nboot_hook_add preinit_main set_preinit_iface\n"
  },
  {
    "path": "target/linux/bcm53xx/base-files/lib/upgrade/platform.sh",
    "content": "RAMFS_COPY_BIN='osafeloader oseama otrx truncate'\n\nPART_NAME=firmware\n\nBCM53XX_FW_FORMAT=\nBCM53XX_FW_BOARD_ID=\nBCM53XX_FW_INT_IMG_FORMAT=\nBCM53XX_FW_INT_IMG_TRX_OFFSET=\nBCM53XX_FW_INT_IMG_EXTRACT_CMD=\n\nLXL_FLAGS_VENDOR_LUXUL=0x00000001\n\n# $(1): file to read magic from\n# $(2): offset in bytes\nget_magic_long_at() {\n\tdd if=\"$1\" skip=$2 bs=1 count=4 2>/dev/null | hexdump -v -e '1/1 \"%02x\"'\n}\n\n# $(1): file to read LE long number from\n# $(2): offset in bytes\nget_le_long_at() {\n\techo $((0x$(dd if=\"$1\" skip=$2 bs=1 count=4 2>/dev/null | hexdump -v -e '1/4 \"%02x\"')))\n}\n\nplatform_flash_type() {\n\t# On NAND devices \"rootfs\" is UBI volume, so won't be find in /proc/mtd\n\tgrep -q \"\\\"rootfs\\\"\" /proc/mtd && {\n\t\techo \"serial\"\n\t\treturn\n\t}\n\n\techo \"nand\"\n}\n\nplatform_expected_image() {\n\tlocal machine=$(board_name)\n\n\tcase \"$machine\" in\n\t\t\"dlink,dir-885l\")\techo \"seamaseal wrgac42_dlink.2015_dir885l\"; return;;\n\t\t\"luxul,abr-4500-v1\")\techo \"lxl ABR-4500\"; return;;\n\t\t\"luxul,xap-810-v1\")\techo \"lxl XAP-810\"; return;;\n\t\t\"luxul,xap-1410v1\")\techo \"lxl XAP-1410\"; return;;\n\t\t\"luxul,xap-1440-v1\")\techo \"lxl XAP-1440\"; return;;\n\t\t\"luxul,xap-1510v1\")\techo \"lxl XAP-1510\"; return;;\n\t\t\"luxul,xap-1610-v1\")\techo \"lxl XAP-1610\"; return;;\n\t\t\"luxul,xbr-4500-v1\")\techo \"lxl XBR-4500\"; return;;\n\t\t\"luxul,xwc-1000\")\techo \"lxl XWC-1000\"; return;;\n\t\t\"luxul,xwc-2000-v1\")\techo \"lxl XWC-2000\"; return;;\n\t\t\"luxul,xwr-1200v1\")\techo \"lxl XWR-1200\"; return;;\n\t\t\"luxul,xwr-3100v1\")\techo \"lxl XWR-3100\"; return;;\n\t\t\"luxul,xwr-3150-v1\")\techo \"lxl XWR-3150\"; return;;\n\t\t\"netgear,r6250v1\")\techo \"chk U12H245T00_NETGEAR\"; return;;\n\t\t\"netgear,r6300v2\")\techo \"chk U12H240T00_NETGEAR\"; return;;\n\t\t\"netgear,r7000\")\techo \"chk U12H270T00_NETGEAR\"; return;;\n\t\t\"netgear,r7900\")\techo \"chk U12H315T30_NETGEAR\"; return;;\n\t\t\"netgear,r8000\")\techo \"chk U12H315T00_NETGEAR\"; return;;\n\t\t\"netgear,r8500\")\techo \"chk U12H334T00_NETGEAR\"; return;;\n\t\t\"tplink,archer-c9-v1\")\techo \"safeloader\"; return;;\n\tesac\n}\n\nplatform_identify() {\n\tlocal magic\n\n\tmagic=$(get_magic_long \"$1\")\n\tcase \"$magic\" in\n\t\t\"48445230\")\n\t\t\tBCM53XX_FW_FORMAT=\"trx\"\n\t\t\treturn\n\t\t\t;;\n\t\t\"2a23245e\")\n\t\t\tlocal header_len=$((0x$(get_magic_long_at \"$1\" 4)))\n\t\t\tlocal board_id_len=$(($header_len - 40))\n\n\t\t\tBCM53XX_FW_FORMAT=\"chk\"\n\t\t\tBCM53XX_FW_BOARD_ID=$(dd if=\"$1\" skip=40 bs=1 count=$board_id_len 2>/dev/null | hexdump -v -e '1/1 \"%c\"')\n\t\t\tBCM53XX_FW_INT_IMG_FORMAT=\"trx\"\n\t\t\tBCM53XX_FW_INT_IMG_TRX_OFFSET=\"$header_len\"\n\t\t\tBCM53XX_FW_INT_IMG_EXTRACT_CMD=\"dd skip=$header_len iflag=skip_bytes\"\n\t\t\treturn\n\t\t\t;;\n\t\t\"4c584c23\")\n\t\t\tlocal hdr_len=$(get_le_long_at \"$1\" 8)\n\t\t\tlocal flags=$(get_le_long_at \"$1\" 12)\n\n\t\t\t[ $((flags & LXL_FLAGS_VENDOR_LUXUL)) -gt 0 ] && notify_firmware_no_backup\n\n\t\t\tBCM53XX_FW_FORMAT=\"lxl\"\n\t\t\tBCM53XX_FW_BOARD_ID=$(dd if=\"$1\" skip=16 bs=1 count=16 2>/dev/null | hexdump -v -e '1/1 \"%c\"')\n\t\t\tBCM53XX_FW_INT_IMG_FORMAT=\"trx\"\n\t\t\tBCM53XX_FW_INT_IMG_TRX_OFFSET=\"$hdr_len\"\n\t\t\tBCM53XX_FW_INT_IMG_EXTRACT_CMD=\"dd skip=$hdr_len iflag=skip_bytes\"\n\n\t\t\treturn\n\t\t\t;;\n\t\t\"5ea3a417\")\n\t\t\tBCM53XX_FW_FORMAT=\"seamaseal\"\n\t\t\tBCM53XX_FW_BOARD_ID=$(oseama info \"$1\" | grep \"Meta entry:.*signature=\" | sed \"s/.*=//\")\n\t\t\tBCM53XX_FW_INT_IMG_EXTRACT_CMD=\"oseama extract - -e 0\"\n\t\t\treturn\n\t\t\t;;\n\tesac\n\n\tmagic=$(get_magic_long_at \"$1\" 14)\n\t[ \"$magic\" = \"55324e44\" ] && {\n\t\tBCM53XX_FW_FORMAT=\"cybertan\"\n\t\tBCM53XX_FW_BOARD_ID=$(dd if=\"$1\" bs=1 count=4 2>/dev/null | hexdump -v -e '1/1 \"%c\"')\n\t\tBCM53XX_FW_INT_IMG_FORMAT=\"trx\"\n\t\tBCM53XX_FW_INT_IMG_TRX_OFFSET=\"32\"\n\t\tBCM53XX_FW_INT_IMG_EXTRACT_CMD=\"dd skip=32 iflag=skip_bytes\"\n\t\treturn\n\t}\n\n\tmagic=$(get_magic_long_at \"$1\" 60)\n\t[ \"$magic\" = \"4c584c23\" ] && {\n\t\tnotify_firmware_no_backup\n\n\t\tBCM53XX_FW_FORMAT=\"lxlold\"\n\t\tBCM53XX_FW_BOARD_ID=$(dd if=\"$1\" skip=48 bs=1 count=12 2>/dev/null | hexdump -v -e '1/1 \"%c\"')\n\t\tBCM53XX_FW_INT_IMG_FORMAT=\"trx\"\n\t\tBCM53XX_FW_INT_IMG_TRX_OFFSET=\"64\"\n\t\tBCM53XX_FW_INT_IMG_EXTRACT_CMD=\"dd skip=64 iflag=skip_bytes\"\n\t\treturn\n\t}\n\n\tif osafeloader info \"$1\" > /dev/null 2>&1; then\n\t\tBCM53XX_FW_FORMAT=\"safeloader\"\n\t\treturn\n\tfi\n}\n\nplatform_other_check_image() {\n\t[ \"$#\" -gt 1 ] && return 1\n\n\tlocal error=0\n\n\tplatform_identify \"$1\"\n\t[ -z \"$BCM53XX_FW_FORMAT\" ] && {\n\t\techo \"Invalid image type. Please use firmware specific for this device.\"\n\t\tnotify_firmware_broken\n\t\treturn 1\n\t}\n\techo \"Found $BCM53XX_FW_FORMAT firmware for device $BCM53XX_FW_BOARD_ID\"\n\n\tlocal expected_image=\"$(platform_expected_image)\"\n\tlocal tmp_format=$BCM53XX_FW_FORMAT\n\t[ \"$tmp_format\" = \"lxlold\" ] && tmp_format=\"lxl\"\n\t[ -n \"$expected_image\" -a -n \"$BCM53XX_FW_BOARD_ID\" -a \"$expected_image\" != \"$tmp_format $BCM53XX_FW_BOARD_ID\" ] && {\n\t\techo \"Firmware doesn't match device ($expected_image)\"\n\t\terror=1\n\t}\n\n\tcase \"$BCM53XX_FW_FORMAT\" in\n\t\t\"seamaseal\")\n\t\t\t$(oseama info \"$1\" -e 0 | grep -q \"Meta entry:.*type=firmware\") || {\n\t\t\t\techo \"Seama seal doesn't contain firmware entity\"\n\t\t\t\terror=1\n\t\t\t}\n\t\t\t;;\n\t\t\"trx\")\n\t\t\tif ! otrx check \"$1\"; then\n\t\t\t\techo \"Failed to find a valid TRX in firmware\"\n\t\t\t\tnotify_firmware_test_result \"trx_valid\" 0\n\t\t\t\terror=1\n\t\t\telse\n\t\t\t\tnotify_firmware_test_result \"trx_valid\" 1\n\t\t\tfi\n\n\t\t\t[ \"$expected_image\" == \"safeloader\" ] && {\n\t\t\t\techo \"This device expects SafeLoader format and may not work with TRX\"\n\t\t\t\terror=1\n\t\t\t}\n\t\t\t;;\n\t\t*)\n\t\t\tcase \"$BCM53XX_FW_INT_IMG_FORMAT\" in\n\t\t\t\t\"trx\")\n\t\t\t\t\t# Make sure that both ways of extracting TRX work.\n\t\t\t\t\t# platform_do_upgrade() may use any of them.\n\t\t\t\t\tif ! otrx check \"$1\" -o \"$BCM53XX_FW_INT_IMG_TRX_OFFSET\" || \\\n\t\t\t\t\t   ! $BCM53XX_FW_INT_IMG_EXTRACT_CMD < $1 | otrx check -; then\n\t\t\t\t\t\techo \"Invalid (corrupted?) TRX firmware\"\n\t\t\t\t\t\tnotify_firmware_test_result \"trx_valid\" 0\n\t\t\t\t\t\terror=1\n\t\t\t\t\telse\n\t\t\t\t\t\tnotify_firmware_test_result \"trx_valid\" 1\n\t\t\t\t\tfi\n\t\t\t\t\t;;\n\t\t\tesac\n\t\t\t;;\n\tesac\n\n\treturn $error\n}\n\nplatform_check_image() {\n\tcase \"$(board_name)\" in\n\tmeraki,mr32)\n\t\t# Ideally, REQUIRE_IMAGE_METADATA=1 would suffice\n\t\t# but this would require converting all other\n\t\t# devices too.\n\t\tnand_do_platform_check meraki-mr32 \"$1\"\n\t\treturn $?\n\t\t;;\n\t*)\n\t\tplatform_other_check_image \"$1\"\n\t\treturn $?\n\t\t;;\n\tesac\n\n\treturn 1\n}\n\n\n# $(1): TRX image or firmware containing TRX\n# $(2): offset of TRX in firmware (optional)\nplatform_do_upgrade_nand_trx() {\n\tlocal dir=\"/tmp/sysupgrade-bcm53xx\"\n\tlocal trx=\"$1\"\n\tlocal offset=\"$2\"\n\n\t# Extract partitions from trx\n\trm -fR $dir\n\tmkdir -p $dir\n\totrx extract \"$trx\" \\\n\t\t${offset:+-o $offset} \\\n\t\t-1 $dir/kernel \\\n\t\t-2 $dir/root\n\t[ $? -ne 0 ] && {\n\t\techo \"Failed to extract TRX partitions.\"\n\t\treturn\n\t}\n\n\t# Firmwares without UBI image should be flashed \"normally\"\n\tlocal root_type=$(identify $dir/root)\n\t[ \"$root_type\" != \"ubi\" ] && {\n\t\techo \"Provided firmware doesn't use UBI for rootfs.\"\n\t\treturn\n\t}\n\n\t# Prepare TRX file with just a kernel that will replace current one\n\tlocal linux_length=$(grep \"\\\"linux\\\"\" /proc/mtd | sed \"s/mtd[0-9]*:[ \\t]*\\([^ \\t]*\\).*/\\1/\")\n\t[ -z \"$linux_length\" ] && {\n\t\techo \"Unable to find \\\"linux\\\" partition size\"\n\t\texit 1\n\t}\n\tlinux_length=$((0x$linux_length))\n\tlocal kernel_length=$(wc -c $dir/kernel | cut -d ' ' -f 1)\n\t[ $kernel_length -gt $linux_length ] && {\n\t\techo \"New kernel doesn't fit \\\"linux\\\" partition.\"\n\t\treturn\n\t}\n\trm -f /tmp/null.bin\n\trm -f /tmp/kernel.trx\n\ttouch /tmp/null.bin\n\totrx create /tmp/kernel.trx \\\n\t\t-f $dir/kernel -b $(($linux_length + 28)) \\\n\t\t-f /tmp/null.bin\n\t[ $? -ne 0 ] && {\n\t\techo \"Failed to create simple TRX with new kernel.\"\n\t\treturn\n\t}\n\n\t# Prepare UBI image (drop unwanted extra blocks)\n\tlocal ubi_length=0\n\twhile [ \"$(dd if=$dir/root skip=$ubi_length bs=1 count=4 2>/dev/null)\" = \"UBI#\" ]; do\n\t\tubi_length=$(($ubi_length + 131072))\n\tdone\n\ttruncate -s $ubi_length $dir/root\n\t[ $? -ne 0 ] && {\n\t\techo \"Failed to prepare new UBI image.\"\n\t\treturn\n\t}\n\n\t# Flash\n\tmtd write /tmp/kernel.trx firmware || exit 1\n\tnand_do_upgrade $dir/root\n}\n\nplatform_do_upgrade_nand_seamaseal() {\n\tlocal dir=\"/tmp/sysupgrade-bcm53xx\"\n\tlocal seamaseal=\"$1\"\n\tlocal tmp\n\n\t# Extract Seama entity from Seama seal\n\trm -fR $dir\n\tmkdir -p $dir\n\toseama extract \"$seamaseal\" \\\n\t\t-e 0 \\\n\t\t-o $dir/seama.entity\n\t[ $? -ne 0 ] && {\n\t\techo \"Failed to extract Seama entity.\"\n\t\treturn\n\t}\n\tlocal entity_size=$(wc -c $dir/seama.entity | cut -d ' ' -f 1)\n\n\tlocal ubi_offset=0\n\ttmp=0\n\twhile [ 1 ]; do\n\t\t[ $tmp -ge $entity_size ] && break\n\t\t[ \"$(dd if=$dir/seama.entity skip=$tmp bs=1 count=4 2>/dev/null)\" = \"UBI#\" ] && {\n\t\t\tubi_offset=$tmp\n\t\t\tbreak\n\t\t}\n\t\ttmp=$(($tmp + 131072))\n\tdone\n\t[ $ubi_offset -eq 0 ] && {\n\t\techo \"Failed to find UBI in Seama entity.\"\n\t\treturn\n\t}\n\n\tlocal ubi_length=0\n\twhile [ \"$(dd if=$dir/seama.entity skip=$(($ubi_offset + $ubi_length)) bs=1 count=4 2>/dev/null)\" = \"UBI#\" ]; do\n\t\tubi_length=$(($ubi_length + 131072))\n\tdone\n\n\tdd if=$dir/seama.entity of=$dir/kernel.seama bs=131072 count=$(($ubi_offset / 131072)) 2>/dev/null\n\tdd if=$dir/seama.entity of=$dir/root.ubi bs=131072 skip=$(($ubi_offset / 131072)) count=$(($ubi_length / 131072)) 2>/dev/null\n\n\t# Flash\n\tlocal kernel_size=$(sed -n 's/mtd[0-9]*: \\([0-9a-f]*\\).*\"\\(kernel\\|linux\\)\".*/\\1/p' /proc/mtd)\n\tmtd write $dir/kernel.seama firmware || exit 1\n\tmtd ${kernel_size:+-c 0x$kernel_size} fixseama firmware\n\tnand_do_upgrade $dir/root.ubi\n}\n\nplatform_img_from_safeloader() {\n\tlocal dir=\"/tmp/sysupgrade-bcm53xx\"\n\n\t# Extract partitions from SafeLoader\n\trm -fR $dir\n\tmkdir -p $dir\n\tosafeloader extract \"$1\" \\\n\t\t-p \"os-image\" \\\n\t\t-o $dir/os-image\n\tosafeloader extract \"$1\" \\\n\t\t-p \"file-system\" \\\n\t\t-o $dir/file-system\n\n\tmtd write $dir/file-system rootfs\n\n\techo -n $dir/os-image\n}\n\nplatform_other_do_upgrade() {\n\tplatform_identify \"$1\"\n\n\t[ \"$(platform_flash_type)\" == \"nand\" ] && {\n\t\t# Try NAND-aware upgrade\n\t\tcase \"$BCM53XX_FW_FORMAT\" in\n\t\t\t\"seamaseal\")\n\t\t\t\tplatform_do_upgrade_nand_seamaseal \"$1\"\n\t\t\t\t;;\n\t\t\t\"trx\")\n\t\t\t\tplatform_do_upgrade_nand_trx \"$1\"\n\t\t\t\t;;\n\t\t\t*)\n\t\t\t\tcase \"$BCM53XX_FW_INT_IMG_FORMAT\" in\n\t\t\t\t\t\"trx\")\n\t\t\t\t\t\tplatform_do_upgrade_nand_trx \"$1\" \"$BCM53XX_FW_INT_IMG_TRX_OFFSET\"\n\t\t\t\t\t\t;;\n\t\t\t\t\t*)\n\t\t\t\t\t\techo \"NAND aware sysupgrade is unsupported for $BCM53XX_FW_FORMAT format\"\n\t\t\t\t\t\t;;\n\t\t\t\tesac\n\t\t\t\t;;\n\t\tesac\n\n\t\t# Above calls exit on success.\n\t\t# If we got here something went wrong.\n\t\techo \"Writing whole image to NAND flash. All erase counters will be lost.\"\n\t}\n\n\tcase \"$BCM53XX_FW_FORMAT\" in\n\t\t\"safeloader\")\n\t\t\tPART_NAME=os-image\n\t\t\timg=$(platform_img_from_safeloader \"$1\")\n\t\t\tdefault_do_upgrade \"$img\"\n\t\t\t;;\n\t\t\"seamaseal\")\n\t\t\tdefault_do_upgrade \"$1\" \"$BCM53XX_FW_INT_IMG_EXTRACT_CMD\"\n\t\t\t;;\n\t\t\"trx\")\n\t\t\tdefault_do_upgrade \"$1\"\n\t\t\t;;\n\t\t*)\n\t\t\tcase \"$BCM53XX_FW_INT_IMG_FORMAT\" in\n\t\t\t\t\"trx\")\n\t\t\t\t\tdefault_do_upgrade \"$1\" \"$BCM53XX_FW_INT_IMG_EXTRACT_CMD\"\n\t\t\t\t\t;;\n\t\t\tesac\n\t\t\t;;\n\tesac\n}\n\nplatform_do_upgrade() {\n\tcase \"$(board_name)\" in\n\tmeraki,mr32)\n\t\tCI_KERNPART=\"part.safe\"\n\t\tnand_do_upgrade \"$1\"\n\t\t;;\n\t*)\n\t\tplatform_other_do_upgrade \"$1\"\n\t\t;;\n\tesac\n}\n"
  },
  {
    "path": "target/linux/bcm53xx/config-5.10",
    "content": "CONFIG_ALIGNMENT_TRAP=y\nCONFIG_ARCH_32BIT_OFF_T=y\nCONFIG_ARCH_BCM=y\nCONFIG_ARCH_BCM_5301X=y\nCONFIG_ARCH_BCM_53573=y\n# CONFIG_ARCH_BCM_HR2 is not set\nCONFIG_ARCH_BCM_IPROC=y\nCONFIG_ARCH_HIBERNATION_POSSIBLE=y\nCONFIG_ARCH_KEEP_MEMBLOCK=y\nCONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y\nCONFIG_ARCH_MULTIPLATFORM=y\nCONFIG_ARCH_MULTI_V6_V7=y\nCONFIG_ARCH_MULTI_V7=y\nCONFIG_ARCH_NR_GPIO=0\nCONFIG_ARCH_OPTIONAL_KERNEL_RWX=y\nCONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y\nCONFIG_ARCH_SELECT_MEMORY_MODEL=y\nCONFIG_ARCH_SPARSEMEM_ENABLE=y\nCONFIG_ARCH_SUSPEND_POSSIBLE=y\nCONFIG_ARM=y\nCONFIG_ARM_AMBA=y\nCONFIG_ARM_APPENDED_DTB=y\nCONFIG_ARM_ARCH_TIMER=y\nCONFIG_ARM_ARCH_TIMER_EVTSTREAM=y\n# CONFIG_ARM_ATAG_DTB_COMPAT is not set\nCONFIG_ARM_ERRATA_754322=y\nCONFIG_ARM_ERRATA_764369=y\nCONFIG_ARM_ERRATA_775420=y\nCONFIG_ARM_GIC=y\nCONFIG_ARM_GLOBAL_TIMER=y\nCONFIG_ARM_HAS_SG_CHAIN=y\nCONFIG_ARM_HEAVY_MB=y\nCONFIG_ARM_L1_CACHE_SHIFT=6\nCONFIG_ARM_L1_CACHE_SHIFT_6=y\nCONFIG_ARM_PATCH_IDIV=y\nCONFIG_ARM_PATCH_PHYS_VIRT=y\nCONFIG_ARM_THUMB=y\nCONFIG_ARM_UNWIND=y\nCONFIG_ARM_VIRT_EXT=y\nCONFIG_ATAGS=y\nCONFIG_AUTO_ZRELADDR=y\nCONFIG_B53=y\nCONFIG_B53_MDIO_DRIVER=y\nCONFIG_B53_SRAB_DRIVER=y\nCONFIG_BCM47XX_NVRAM=y\nCONFIG_BCM47XX_SPROM=y\nCONFIG_BCM47XX_WDT=y\nCONFIG_BCMA=y\nCONFIG_BCMA_BLOCKIO=y\nCONFIG_BCMA_DEBUG=y\nCONFIG_BCMA_DRIVER_GMAC_CMN=y\nCONFIG_BCMA_DRIVER_GPIO=y\nCONFIG_BCMA_DRIVER_PCI=y\nCONFIG_BCMA_HOST_PCI=y\nCONFIG_BCMA_HOST_PCI_POSSIBLE=y\nCONFIG_BCMA_HOST_SOC=y\nCONFIG_BCMA_SFLASH=y\n# CONFIG_BCM_CYGNUS_PHY is not set\nCONFIG_BCM_NET_PHYLIB=y\nCONFIG_BCM_NS_THERMAL=y\nCONFIG_BCM_SR_THERMAL=y\nCONFIG_BGMAC=y\nCONFIG_BGMAC_BCMA=y\n# CONFIG_BGMAC_PLATFORM is not set\nCONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y\nCONFIG_BLK_MQ_PCI=y\nCONFIG_BOUNCE=y\nCONFIG_BROADCOM_PHY=y\nCONFIG_CACHE_L2X0=y\nCONFIG_CLKDEV_LOOKUP=y\nCONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK=y\nCONFIG_CLKSRC_MMIO=y\n# CONFIG_CLK_BCM_NS2 is not set\nCONFIG_CLK_BCM_NSP=y\n# CONFIG_CLK_BCM_SR is not set\nCONFIG_CLONE_BACKWARDS=y\nCONFIG_COMMON_CLK=y\nCONFIG_COMMON_CLK_IPROC=y\nCONFIG_COMPAT_32BIT_TIME=y\nCONFIG_CPU_32v6K=y\nCONFIG_CPU_32v7=y\nCONFIG_CPU_ABRT_EV7=y\nCONFIG_CPU_CACHE_V7=y\nCONFIG_CPU_CACHE_VIPT=y\nCONFIG_CPU_COPY_V6=y\nCONFIG_CPU_CP15=y\nCONFIG_CPU_CP15_MMU=y\nCONFIG_CPU_HAS_ASID=y\nCONFIG_CPU_PABRT_V7=y\nCONFIG_CPU_RMAP=y\nCONFIG_CPU_SPECTRE=y\nCONFIG_CPU_THUMB_CAPABLE=y\nCONFIG_CPU_TLB_V7=y\nCONFIG_CPU_V7=y\nCONFIG_CRC16=y\nCONFIG_CRYPTO_DEFLATE=y\nCONFIG_CRYPTO_HASH_INFO=y\nCONFIG_CRYPTO_LZO=y\nCONFIG_CRYPTO_RNG2=y\nCONFIG_CRYPTO_ZSTD=y\nCONFIG_DCACHE_WORD_ACCESS=y\nCONFIG_DEBUG_BCM_5301X=y\nCONFIG_DEBUG_INFO=y\nCONFIG_DEBUG_LL=y\nCONFIG_DEBUG_LL_INCLUDE=\"debug/8250.S\"\nCONFIG_DEBUG_MISC=y\nCONFIG_DEBUG_UART_8250=y\nCONFIG_DEBUG_UART_8250_SHIFT=0\nCONFIG_DEBUG_UART_PHYS=0x18000300\nCONFIG_DEBUG_UART_VIRT=0xf1000300\nCONFIG_DEBUG_UNCOMPRESS=y\nCONFIG_DEBUG_USER=y\nCONFIG_DMA_OPS=y\nCONFIG_DMA_REMAP=y\nCONFIG_DTC=y\nCONFIG_EARLY_PRINTK=y\nCONFIG_EDAC_ATOMIC_SCRUB=y\nCONFIG_EDAC_SUPPORT=y\nCONFIG_EXTCON=y\nCONFIG_FIXED_PHY=y\nCONFIG_FIX_EARLYCON_MEM=y\nCONFIG_FW_LOADER_PAGED_BUF=y\n# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set\nCONFIG_GENERIC_ALLOCATOR=y\nCONFIG_GENERIC_ARCH_TOPOLOGY=y\nCONFIG_GENERIC_BUG=y\nCONFIG_GENERIC_CLOCKEVENTS=y\nCONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y\nCONFIG_GENERIC_CPU_AUTOPROBE=y\nCONFIG_GENERIC_EARLY_IOREMAP=y\nCONFIG_GENERIC_GETTIMEOFDAY=y\nCONFIG_GENERIC_IDLE_POLL_SETUP=y\nCONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y\nCONFIG_GENERIC_IRQ_MULTI_HANDLER=y\nCONFIG_GENERIC_IRQ_SHOW=y\nCONFIG_GENERIC_IRQ_SHOW_LEVEL=y\nCONFIG_GENERIC_PCI_IOMAP=y\nCONFIG_GENERIC_PHY=y\nCONFIG_GENERIC_PINCONF=y\nCONFIG_GENERIC_PINCTRL_GROUPS=y\nCONFIG_GENERIC_PINMUX_FUNCTIONS=y\nCONFIG_GENERIC_SCHED_CLOCK=y\nCONFIG_GENERIC_SMP_IDLE_THREAD=y\nCONFIG_GENERIC_STRNCPY_FROM_USER=y\nCONFIG_GENERIC_STRNLEN_USER=y\nCONFIG_GENERIC_TIME_VSYSCALL=y\nCONFIG_GENERIC_VDSO_32=y\nCONFIG_GPIOLIB=y\nCONFIG_GPIOLIB_IRQCHIP=y\nCONFIG_GPIO_74X164=y\nCONFIG_GPIO_BCM_XGS_IPROC=y\nCONFIG_GPIO_GENERIC=y\nCONFIG_GRO_CELLS=y\nCONFIG_HANDLE_DOMAIN_IRQ=y\nCONFIG_HARDEN_BRANCH_PREDICTOR=y\nCONFIG_HARDIRQS_SW_RESEND=y\nCONFIG_HAS_DMA=y\nCONFIG_HAS_IOMEM=y\nCONFIG_HAS_IOPORT_MAP=y\nCONFIG_HAVE_SMP=y\nCONFIG_HIGHMEM=y\nCONFIG_HIGHPTE=y\nCONFIG_HW_RANDOM=y\nCONFIG_HW_RANDOM_BCM2835=y\nCONFIG_HZ_FIXED=0\nCONFIG_HZ_PERIODIC=y\nCONFIG_INITRAMFS_SOURCE=\"\"\nCONFIG_IO_URING=y\nCONFIG_IRQCHIP=y\nCONFIG_IRQ_DOMAIN=y\nCONFIG_IRQ_DOMAIN_HIERARCHY=y\nCONFIG_IRQ_FORCED_THREADING=y\nCONFIG_IRQ_WORK=y\nCONFIG_LIBFDT=y\nCONFIG_LOCK_DEBUGGING_SUPPORT=y\nCONFIG_LOCK_SPIN_ON_OWNER=y\nCONFIG_LZO_COMPRESS=y\nCONFIG_LZO_DECOMPRESS=y\nCONFIG_MDIO_BCM_IPROC=y\nCONFIG_MDIO_BUS=y\nCONFIG_MDIO_BUS_MUX=y\n# CONFIG_MDIO_BUS_MUX_BCM_IPROC is not set\nCONFIG_MDIO_BUS_MUX_MMIOREG=y\nCONFIG_MDIO_DEVICE=y\nCONFIG_MDIO_DEVRES=y\nCONFIG_MEMFD_CREATE=y\nCONFIG_MFD_SYSCON=y\nCONFIG_MIGHT_HAVE_CACHE_L2X0=y\nCONFIG_MIGRATION=y\nCONFIG_MODULES_USE_ELF_REL=y\nCONFIG_MTD_BCM47XXSFLASH=y\nCONFIG_MTD_BCM47XX_PARTS=y\nCONFIG_MTD_NAND_BRCMNAND=y\nCONFIG_MTD_NAND_CORE=y\nCONFIG_MTD_NAND_ECC=y\nCONFIG_MTD_NAND_ECC_SW_HAMMING=y\nCONFIG_MTD_OF_PARTS_LINKSYS_NS=y\nCONFIG_MTD_PARSER_TRX=y\nCONFIG_MTD_RAW_NAND=y\nCONFIG_MTD_SPI_NOR=y\nCONFIG_MTD_SPLIT_SEAMA_FW=y\nCONFIG_MTD_UBI=y\nCONFIG_MTD_UBI_BEB_LIMIT=20\nCONFIG_MTD_UBI_BLOCK=y\nCONFIG_MTD_UBI_WL_THRESHOLD=4096\nCONFIG_MUTEX_SPIN_ON_OWNER=y\nCONFIG_NEED_DMA_MAP_STATE=y\nCONFIG_NET_DEVLINK=y\nCONFIG_NET_DSA=y\nCONFIG_NET_DSA_TAG_BRCM=y\nCONFIG_NET_DSA_TAG_BRCM_COMMON=y\nCONFIG_NET_DSA_TAG_BRCM_LEGACY=y\nCONFIG_NET_DSA_TAG_BRCM_PREPEND=y\nCONFIG_NET_FLOW_LIMIT=y\nCONFIG_NET_SWITCHDEV=y\nCONFIG_NR_CPUS=2\nCONFIG_NVMEM=y\nCONFIG_NVMEM_BRCM_NVRAM=y\nCONFIG_NVMEM_SYSFS=y\nCONFIG_OF=y\nCONFIG_OF_ADDRESS=y\nCONFIG_OF_EARLY_FLATTREE=y\nCONFIG_OF_FLATTREE=y\nCONFIG_OF_GPIO=y\nCONFIG_OF_IRQ=y\nCONFIG_OF_KOBJ=y\nCONFIG_OF_MDIO=y\nCONFIG_OF_NET=y\nCONFIG_OLD_SIGACTION=y\nCONFIG_OLD_SIGSUSPEND3=y\nCONFIG_OUTER_CACHE=y\nCONFIG_OUTER_CACHE_SYNC=y\nCONFIG_PADATA=y\nCONFIG_PAGE_OFFSET=0xC0000000\nCONFIG_PCI=y\nCONFIG_PCIE_IPROC=y\nCONFIG_PCIE_IPROC_BCMA=y\n# CONFIG_PCIE_IPROC_PLATFORM is not set\nCONFIG_PCI_DOMAINS=y\nCONFIG_PCI_DOMAINS_GENERIC=y\nCONFIG_PERF_USE_VMALLOC=y\nCONFIG_PGTABLE_LEVELS=2\nCONFIG_PHYLIB=y\nCONFIG_PHYLINK=y\n# CONFIG_PHY_BCM_NS_USB2 is not set\n# CONFIG_PHY_BCM_NS_USB3 is not set\n# CONFIG_PHY_BCM_SR_PCIE is not set\nCONFIG_PHY_BCM_SR_USB=y\n# CONFIG_PHY_BRCM_SATA is not set\n# CONFIG_PHY_NS2_USB_DRD is not set\nCONFIG_PINCTRL=y\n# CONFIG_PINCTRL_IPROC_GPIO is not set\nCONFIG_PINCTRL_NS=y\n# CONFIG_PINCTRL_NS2_MUX is not set\nCONFIG_PWM=y\nCONFIG_PWM_BCM_IPROC=y\nCONFIG_PWM_SYSFS=y\nCONFIG_RATIONAL=y\nCONFIG_REGMAP=y\nCONFIG_REGMAP_MMIO=y\nCONFIG_RFS_ACCEL=y\nCONFIG_RPS=y\nCONFIG_RWSEM_SPIN_ON_OWNER=y\nCONFIG_SERIAL_8250_FSL=y\nCONFIG_SERIAL_MCTRL_GPIO=y\nCONFIG_SERIAL_OF_PLATFORM=y\nCONFIG_SGL_ALLOC=y\nCONFIG_SMP=y\nCONFIG_SMP_ON_UP=y\nCONFIG_SPARSE_IRQ=y\nCONFIG_SPI=y\nCONFIG_SPI_BCM_QSPI=y\nCONFIG_SPI_BITBANG=y\nCONFIG_SPI_GPIO=y\nCONFIG_SPI_MASTER=y\nCONFIG_SPI_MEM=y\nCONFIG_SRCU=y\nCONFIG_SWPHY=y\nCONFIG_SWP_EMULATE=y\nCONFIG_SYS_SUPPORTS_APM_EMULATION=y\nCONFIG_THERMAL=y\nCONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y\nCONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0\nCONFIG_THERMAL_GOV_STEP_WISE=y\nCONFIG_THERMAL_OF=y\nCONFIG_TICK_CPU_ACCOUNTING=y\nCONFIG_TIMER_OF=y\nCONFIG_TIMER_PROBE=y\nCONFIG_TREE_RCU=y\nCONFIG_TREE_SRCU=y\nCONFIG_UBIFS_FS=y\nCONFIG_UNCOMPRESS_INCLUDE=\"debug/uncompress.h\"\nCONFIG_UNWINDER_ARM=y\nCONFIG_USB_SUPPORT=y\nCONFIG_USE_OF=y\n# CONFIG_VFP is not set\nCONFIG_WATCHDOG_CORE=y\nCONFIG_XPS=y\nCONFIG_XXHASH=y\nCONFIG_XZ_DEC_ARM=y\nCONFIG_XZ_DEC_BCJ=y\nCONFIG_ZBOOT_ROM_BSS=0x0\nCONFIG_ZBOOT_ROM_TEXT=0x0\nCONFIG_ZLIB_DEFLATE=y\nCONFIG_ZLIB_INFLATE=y\nCONFIG_ZSTD_COMPRESS=y\nCONFIG_ZSTD_DECOMPRESS=y\n"
  },
  {
    "path": "target/linux/bcm53xx/config-5.15",
    "content": "CONFIG_AF_UNIX_OOB=y\nCONFIG_ALIGNMENT_TRAP=y\nCONFIG_ARCH_32BIT_OFF_T=y\nCONFIG_ARCH_BCM=y\nCONFIG_ARCH_BCM_5301X=y\nCONFIG_ARCH_BCM_53573=y\n# CONFIG_ARCH_BCM_HR2 is not set\nCONFIG_ARCH_BCM_IPROC=y\nCONFIG_ARCH_HIBERNATION_POSSIBLE=y\nCONFIG_ARCH_KEEP_MEMBLOCK=y\nCONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y\nCONFIG_ARCH_MULTIPLATFORM=y\nCONFIG_ARCH_MULTI_V6_V7=y\nCONFIG_ARCH_MULTI_V7=y\nCONFIG_ARCH_NR_GPIO=0\nCONFIG_ARCH_OPTIONAL_KERNEL_RWX=y\nCONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y\nCONFIG_ARCH_SELECT_MEMORY_MODEL=y\nCONFIG_ARCH_SPARSEMEM_ENABLE=y\nCONFIG_ARCH_SUSPEND_POSSIBLE=y\nCONFIG_ARM=y\nCONFIG_ARM_AMBA=y\nCONFIG_ARM_APPENDED_DTB=y\nCONFIG_ARM_ARCH_TIMER=y\nCONFIG_ARM_ARCH_TIMER_EVTSTREAM=y\n# CONFIG_ARM_ATAG_DTB_COMPAT is not set\nCONFIG_ARM_ERRATA_754322=y\nCONFIG_ARM_ERRATA_764369=y\nCONFIG_ARM_ERRATA_775420=y\nCONFIG_ARM_GIC=y\nCONFIG_ARM_GLOBAL_TIMER=y\nCONFIG_ARM_GT_INITIAL_PRESCALER_VAL=1\nCONFIG_ARM_HAS_SG_CHAIN=y\nCONFIG_ARM_HEAVY_MB=y\nCONFIG_ARM_L1_CACHE_SHIFT=6\nCONFIG_ARM_L1_CACHE_SHIFT_6=y\nCONFIG_ARM_PATCH_IDIV=y\nCONFIG_ARM_PATCH_PHYS_VIRT=y\nCONFIG_ARM_THUMB=y\nCONFIG_ARM_UNWIND=y\nCONFIG_ARM_VIRT_EXT=y\nCONFIG_ATAGS=y\nCONFIG_AUTO_ZRELADDR=y\nCONFIG_B53=y\nCONFIG_B53_MDIO_DRIVER=y\nCONFIG_B53_SRAB_DRIVER=y\nCONFIG_BCM47XX_NVRAM=y\nCONFIG_BCM47XX_SPROM=y\nCONFIG_BCM47XX_WDT=y\nCONFIG_BCMA=y\nCONFIG_BCMA_BLOCKIO=y\nCONFIG_BCMA_DEBUG=y\nCONFIG_BCMA_DRIVER_GMAC_CMN=y\nCONFIG_BCMA_DRIVER_GPIO=y\nCONFIG_BCMA_DRIVER_PCI=y\nCONFIG_BCMA_HOST_PCI=y\nCONFIG_BCMA_HOST_PCI_POSSIBLE=y\nCONFIG_BCMA_HOST_SOC=y\nCONFIG_BCMA_SFLASH=y\n# CONFIG_BCM_CYGNUS_PHY is not set\nCONFIG_BCM_NET_PHYLIB=y\nCONFIG_BCM_NS_THERMAL=y\nCONFIG_BCM_SR_THERMAL=y\nCONFIG_BGMAC=y\nCONFIG_BGMAC_BCMA=y\n# CONFIG_BGMAC_PLATFORM is not set\nCONFIG_BINARY_PRINTF=y\nCONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y\nCONFIG_BLK_MQ_PCI=y\nCONFIG_BOUNCE=y\nCONFIG_BROADCOM_PHY=y\nCONFIG_CACHE_L2X0=y\nCONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK=y\nCONFIG_CLKSRC_MMIO=y\n# CONFIG_CLK_BCM_NS2 is not set\nCONFIG_CLK_BCM_NSP=y\n# CONFIG_CLK_BCM_SR is not set\nCONFIG_CLONE_BACKWARDS=y\nCONFIG_COMMON_CLK=y\nCONFIG_COMMON_CLK_IPROC=y\nCONFIG_COMPAT_32BIT_TIME=y\nCONFIG_CPU_32v6K=y\nCONFIG_CPU_32v7=y\nCONFIG_CPU_ABRT_EV7=y\nCONFIG_CPU_CACHE_V7=y\nCONFIG_CPU_CACHE_VIPT=y\nCONFIG_CPU_COPY_V6=y\nCONFIG_CPU_CP15=y\nCONFIG_CPU_CP15_MMU=y\nCONFIG_CPU_HAS_ASID=y\nCONFIG_CPU_PABRT_V7=y\nCONFIG_CPU_RMAP=y\nCONFIG_CPU_SPECTRE=y\nCONFIG_CPU_THUMB_CAPABLE=y\nCONFIG_CPU_TLB_V7=y\nCONFIG_CPU_V7=y\nCONFIG_CRC16=y\nCONFIG_CRYPTO_DEFLATE=y\nCONFIG_CRYPTO_HASH_INFO=y\nCONFIG_CRYPTO_LZO=y\nCONFIG_CRYPTO_RNG2=y\nCONFIG_CRYPTO_ZSTD=y\nCONFIG_DCACHE_WORD_ACCESS=y\nCONFIG_DEBUG_BCM_5301X=y\nCONFIG_DEBUG_INFO=y\nCONFIG_DEBUG_LL=y\nCONFIG_DEBUG_LL_INCLUDE=\"debug/8250.S\"\nCONFIG_DEBUG_MISC=y\nCONFIG_DEBUG_UART_8250=y\nCONFIG_DEBUG_UART_8250_SHIFT=0\nCONFIG_DEBUG_UART_PHYS=0x18000300\nCONFIG_DEBUG_UART_VIRT=0xf1000300\nCONFIG_DEBUG_UNCOMPRESS=y\nCONFIG_DEBUG_USER=y\nCONFIG_DMA_OPS=y\nCONFIG_DMA_REMAP=y\nCONFIG_DTC=y\nCONFIG_EARLY_PRINTK=y\nCONFIG_EDAC_ATOMIC_SCRUB=y\nCONFIG_EDAC_SUPPORT=y\nCONFIG_EXTCON=y\nCONFIG_FIXED_PHY=y\nCONFIG_FIX_EARLYCON_MEM=y\nCONFIG_FWNODE_MDIO=y\nCONFIG_FW_LOADER_PAGED_BUF=y\n# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set\nCONFIG_GENERIC_ALLOCATOR=y\nCONFIG_GENERIC_ARCH_TOPOLOGY=y\nCONFIG_GENERIC_BUG=y\nCONFIG_GENERIC_CLOCKEVENTS=y\nCONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y\nCONFIG_GENERIC_CPU_AUTOPROBE=y\nCONFIG_GENERIC_CPU_VULNERABILITIES=y\nCONFIG_GENERIC_EARLY_IOREMAP=y\nCONFIG_GENERIC_GETTIMEOFDAY=y\nCONFIG_GENERIC_IDLE_POLL_SETUP=y\nCONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y\nCONFIG_GENERIC_IRQ_MULTI_HANDLER=y\nCONFIG_GENERIC_IRQ_SHOW=y\nCONFIG_GENERIC_IRQ_SHOW_LEVEL=y\nCONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y\nCONFIG_GENERIC_PCI_IOMAP=y\nCONFIG_GENERIC_PHY=y\nCONFIG_GENERIC_PINCONF=y\nCONFIG_GENERIC_PINCTRL_GROUPS=y\nCONFIG_GENERIC_PINMUX_FUNCTIONS=y\nCONFIG_GENERIC_SCHED_CLOCK=y\nCONFIG_GENERIC_SMP_IDLE_THREAD=y\nCONFIG_GENERIC_STRNCPY_FROM_USER=y\nCONFIG_GENERIC_STRNLEN_USER=y\nCONFIG_GENERIC_TIME_VSYSCALL=y\nCONFIG_GENERIC_VDSO_32=y\nCONFIG_GPIOLIB=y\nCONFIG_GPIOLIB_IRQCHIP=y\nCONFIG_GPIO_74X164=y\nCONFIG_GPIO_BCM_XGS_IPROC=y\nCONFIG_GPIO_CDEV=y\nCONFIG_GPIO_GENERIC=y\nCONFIG_GRO_CELLS=y\nCONFIG_HANDLE_DOMAIN_IRQ=y\nCONFIG_HARDEN_BRANCH_PREDICTOR=y\nCONFIG_HARDIRQS_SW_RESEND=y\nCONFIG_HAS_DMA=y\nCONFIG_HAS_IOMEM=y\nCONFIG_HAS_IOPORT_MAP=y\nCONFIG_HAVE_SMP=y\nCONFIG_HIGHMEM=y\nCONFIG_HIGHPTE=y\nCONFIG_HW_RANDOM=y\nCONFIG_HW_RANDOM_BCM2835=y\nCONFIG_HZ_FIXED=0\nCONFIG_HZ_PERIODIC=y\nCONFIG_INITRAMFS_SOURCE=\"\"\nCONFIG_IO_URING=y\nCONFIG_IRQCHIP=y\nCONFIG_IRQ_DOMAIN=y\nCONFIG_IRQ_DOMAIN_HIERARCHY=y\nCONFIG_IRQ_FORCED_THREADING=y\nCONFIG_IRQ_WORK=y\nCONFIG_KMAP_LOCAL=y\nCONFIG_KMAP_LOCAL_NON_LINEAR_PTE_ARRAY=y\nCONFIG_LIBFDT=y\nCONFIG_LOCK_DEBUGGING_SUPPORT=y\nCONFIG_LOCK_SPIN_ON_OWNER=y\nCONFIG_LTO_NONE=y\nCONFIG_LZO_COMPRESS=y\nCONFIG_LZO_DECOMPRESS=y\nCONFIG_MDIO_BCM_IPROC=y\nCONFIG_MDIO_BUS=y\nCONFIG_MDIO_BUS_MUX=y\n# CONFIG_MDIO_BUS_MUX_BCM_IPROC is not set\nCONFIG_MDIO_BUS_MUX_MMIOREG=y\nCONFIG_MDIO_DEVICE=y\nCONFIG_MDIO_DEVRES=y\nCONFIG_MEMFD_CREATE=y\nCONFIG_MFD_SYSCON=y\nCONFIG_MIGHT_HAVE_CACHE_L2X0=y\nCONFIG_MIGRATION=y\nCONFIG_MODULES_USE_ELF_REL=y\nCONFIG_MTD_BCM47XXSFLASH=y\nCONFIG_MTD_BCM47XX_PARTS=y\nCONFIG_MTD_NAND_BRCMNAND=y\nCONFIG_MTD_NAND_CORE=y\nCONFIG_MTD_NAND_ECC=y\nCONFIG_MTD_NAND_ECC_SW_HAMMING=y\nCONFIG_MTD_OF_PARTS_LINKSYS_NS=y\nCONFIG_MTD_PARSER_TRX=y\nCONFIG_MTD_RAW_NAND=y\nCONFIG_MTD_SPI_NOR=y\nCONFIG_MTD_SPLIT_SEAMA_FW=y\nCONFIG_MTD_UBI=y\nCONFIG_MTD_UBI_BEB_LIMIT=20\nCONFIG_MTD_UBI_BLOCK=y\nCONFIG_MTD_UBI_WL_THRESHOLD=4096\nCONFIG_MUTEX_SPIN_ON_OWNER=y\nCONFIG_NEED_DMA_MAP_STATE=y\nCONFIG_NET_DEVLINK=y\nCONFIG_NET_DSA=y\nCONFIG_NET_DSA_TAG_BRCM=y\nCONFIG_NET_DSA_TAG_BRCM_COMMON=y\nCONFIG_NET_DSA_TAG_BRCM_LEGACY=y\nCONFIG_NET_DSA_TAG_BRCM_PREPEND=y\nCONFIG_NET_FLOW_LIMIT=y\nCONFIG_NET_SELFTESTS=y\nCONFIG_NET_SOCK_MSG=y\nCONFIG_NET_SWITCHDEV=y\nCONFIG_NR_CPUS=2\nCONFIG_NVMEM=y\nCONFIG_NVMEM_BRCM_NVRAM=y\nCONFIG_NVMEM_SYSFS=y\nCONFIG_OF=y\nCONFIG_OF_ADDRESS=y\nCONFIG_OF_EARLY_FLATTREE=y\nCONFIG_OF_FLATTREE=y\nCONFIG_OF_GPIO=y\nCONFIG_OF_IRQ=y\nCONFIG_OF_KOBJ=y\nCONFIG_OF_MDIO=y\nCONFIG_OLD_SIGACTION=y\nCONFIG_OLD_SIGSUSPEND3=y\nCONFIG_OUTER_CACHE=y\nCONFIG_OUTER_CACHE_SYNC=y\nCONFIG_PADATA=y\nCONFIG_PAGE_OFFSET=0xC0000000\nCONFIG_PCI=y\nCONFIG_PCIE_IPROC=y\nCONFIG_PCIE_IPROC_BCMA=y\n# CONFIG_PCIE_IPROC_PLATFORM is not set\nCONFIG_PCI_DOMAINS=y\nCONFIG_PCI_DOMAINS_GENERIC=y\nCONFIG_PERF_USE_VMALLOC=y\nCONFIG_PGTABLE_LEVELS=2\nCONFIG_PHYLIB=y\nCONFIG_PHYLINK=y\n# CONFIG_PHY_BCM_NS_USB2 is not set\n# CONFIG_PHY_BCM_NS_USB3 is not set\n# CONFIG_PHY_BCM_SR_PCIE is not set\nCONFIG_PHY_BCM_SR_USB=y\n# CONFIG_PHY_BRCM_SATA is not set\n# CONFIG_PHY_NS2_USB_DRD is not set\nCONFIG_PINCTRL=y\n# CONFIG_PINCTRL_IPROC_GPIO is not set\nCONFIG_PINCTRL_NS=y\n# CONFIG_PINCTRL_NS2_MUX is not set\nCONFIG_PTP_1588_CLOCK_OPTIONAL=y\nCONFIG_PWM=y\nCONFIG_PWM_BCM_IPROC=y\nCONFIG_PWM_SYSFS=y\nCONFIG_RATIONAL=y\nCONFIG_REGMAP=y\nCONFIG_REGMAP_MMIO=y\nCONFIG_RFS_ACCEL=y\nCONFIG_RPS=y\nCONFIG_RWSEM_SPIN_ON_OWNER=y\nCONFIG_SERIAL_8250_FSL=y\nCONFIG_SERIAL_MCTRL_GPIO=y\nCONFIG_SERIAL_OF_PLATFORM=y\nCONFIG_SGL_ALLOC=y\nCONFIG_SMP=y\nCONFIG_SMP_ON_UP=y\nCONFIG_SOCK_RX_QUEUE_MAPPING=y\nCONFIG_SPARSE_IRQ=y\nCONFIG_SPI=y\nCONFIG_SPI_BCM_QSPI=y\nCONFIG_SPI_BITBANG=y\nCONFIG_SPI_GPIO=y\nCONFIG_SPI_MASTER=y\nCONFIG_SPI_MEM=y\nCONFIG_SRCU=y\nCONFIG_SWPHY=y\nCONFIG_SWP_EMULATE=y\nCONFIG_SYS_SUPPORTS_APM_EMULATION=y\nCONFIG_THERMAL=y\nCONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y\nCONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0\nCONFIG_THERMAL_GOV_STEP_WISE=y\nCONFIG_THERMAL_OF=y\nCONFIG_TICK_CPU_ACCOUNTING=y\nCONFIG_TIMER_OF=y\nCONFIG_TIMER_PROBE=y\nCONFIG_TREE_RCU=y\nCONFIG_TREE_SRCU=y\nCONFIG_UBIFS_FS=y\nCONFIG_UNCOMPRESS_INCLUDE=\"debug/uncompress.h\"\nCONFIG_UNWINDER_ARM=y\nCONFIG_USB_SUPPORT=y\nCONFIG_USE_OF=y\n# CONFIG_VFP is not set\nCONFIG_WATCHDOG_CORE=y\nCONFIG_XPS=y\nCONFIG_XXHASH=y\nCONFIG_XZ_DEC_ARM=y\nCONFIG_XZ_DEC_BCJ=y\nCONFIG_ZBOOT_ROM_BSS=0x0\nCONFIG_ZBOOT_ROM_TEXT=0x0\nCONFIG_ZLIB_DEFLATE=y\nCONFIG_ZLIB_INFLATE=y\nCONFIG_ZSTD_COMPRESS=y\nCONFIG_ZSTD_DECOMPRESS=y\n"
  },
  {
    "path": "target/linux/bcm53xx/files/arch/arm/boot/compressed/cache-v7-min.S",
    "content": "/*\n * This is a part of mm/cache-v7.S with extracted entry flushing D-cache. We\n * need it for Broadcom devices with broken bootloader leaving cache enabled.\n *\n * Copyright (C) 2001 Deep Blue Solutions Ltd.\n * Copyright (C) 2005 ARM Ltd.\n *\n * This program is free software; you can redistribute it and/or modify\n * it under the terms of the GNU General Public License version 2 as\n * published by the Free Software Foundation.\n */\n\n#include <linux/linkage.h>\n#include <linux/init.h>\n\n\t__INIT\n\n/*\n *\tv7_flush_dcache_all()\n *\n *\tFlush the whole D-cache.\n *\n *\tCorrupted registers: r0-r7, r9-r11 (r6 only in Thumb mode)\n *\n *\t- mm    - mm_struct describing address space\n */\nENTRY(v7_flush_dcache_all)\n\tdmb\t\t\t\t\t@ ensure ordering with previous memory accesses\n\tmrc\tp15, 1, r0, c0, c0, 1\t\t@ read clidr\n\tmov\tr3, r0, lsr #23\t\t\t@ move LoC into position\n\tands\tr3, r3, #7 << 1\t\t\t@ extract LoC*2 from clidr\n\tbeq\tfinished\t\t\t@ if loc is 0, then no need to clean\nstart_flush_levels:\n\tmov\tr10, #0\t\t\t\t@ start clean at cache level 0\nflush_levels:\n\tadd\tr2, r10, r10, lsr #1\t\t@ work out 3x current cache level\n\tmov\tr1, r0, lsr r2\t\t\t@ extract cache type bits from clidr\n\tand\tr1, r1, #7\t\t\t@ mask of the bits for current cache only\n\tcmp\tr1, #2\t\t\t\t@ see what cache we have at this level\n\tblt\tskip\t\t\t\t@ skip if no cache, or just i-cache\n#ifdef CONFIG_PREEMPT\n\tsave_and_disable_irqs_notrace r9\t@ make cssr&csidr read atomic\n#endif\n\tmcr\tp15, 2, r10, c0, c0, 0\t\t@ select current cache level in cssr\n\tisb\t\t\t\t\t@ isb to sych the new cssr&csidr\n\tmrc\tp15, 1, r1, c0, c0, 0\t\t@ read the new csidr\n#ifdef CONFIG_PREEMPT\n\trestore_irqs_notrace r9\n#endif\n\tand\tr2, r1, #7\t\t\t@ extract the length of the cache lines\n\tadd\tr2, r2, #4\t\t\t@ add 4 (line length offset)\n\tmovw\tr4, #0x3ff\n\tands\tr4, r4, r1, lsr #3\t\t@ find maximum number on the way size\n\tclz\tr5, r4\t\t\t\t@ find bit position of way size increment\n\tmovw\tr7, #0x7fff\n\tands\tr7, r7, r1, lsr #13\t\t@ extract max number of the index size\nloop1:\n\tmov\tr9, r7\t\t\t\t@ create working copy of max index\nloop2:\n ARM(\torr\tr11, r10, r4, lsl r5\t)\t@ factor way and cache number into r11\n THUMB(\tlsl\tr6, r4, r5\t\t)\n THUMB(\torr\tr11, r10, r6\t\t)\t@ factor way and cache number into r11\n ARM(\torr\tr11, r11, r9, lsl r2\t)\t@ factor index number into r11\n THUMB(\tlsl\tr6, r9, r2\t\t)\n THUMB(\torr\tr11, r11, r6\t\t)\t@ factor index number into r11\n\tmcr\tp15, 0, r11, c7, c14, 2\t\t@ clean & invalidate by set/way\n\tsubs\tr9, r9, #1\t\t\t@ decrement the index\n\tbge\tloop2\n\tsubs\tr4, r4, #1\t\t\t@ decrement the way\n\tbge\tloop1\nskip:\n\tadd\tr10, r10, #2\t\t\t@ increment cache number\n\tcmp\tr3, r10\n\tbgt\tflush_levels\nfinished:\n\tmov\tr10, #0\t\t\t\t@ swith back to cache level 0\n\tmcr\tp15, 2, r10, c0, c0, 0\t\t@ select current cache level in cssr\n\tdsb\tst\n\tisb\n\tret\tlr\nENDPROC(v7_flush_dcache_all)\n"
  },
  {
    "path": "target/linux/bcm53xx/generic/target.mk",
    "content": "BOARDNAME:=Generic\n"
  },
  {
    "path": "target/linux/bcm53xx/image/Makefile",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2013 OpenWrt.org\n\ninclude $(TOPDIR)/rules.mk\ninclude $(INCLUDE_DIR)/image.mk\n\ndefine Image/Prepare\n\trm -f $(KDIR)/fs_mark\n\techo -ne '\\xde\\xad\\xc0\\xde' > $(KDIR)/fs_mark\n\t$(call prepare_generic_squashfs,$(KDIR)/fs_mark)\n\n\t# For UBI we want only one extra block\n\trm -f $(KDIR)/ubi_mark\n\techo -ne '\\xde\\xad\\xc0\\xde' > $(KDIR)/ubi_mark\nendef\n\ndefine Build/lzma-d16\n\t$(STAGING_DIR_HOST)/bin/lzma e $@ -d16 $(1) $@.new\n\tmv $@.new $@\nendef\n\n# Similar to Build/tplink-safeloader but uses TRX instead of clean kernel\ndefine Build/bcm53xx-tplink-safeloader\n\t$(STAGING_DIR_HOST)/bin/trx \\\n\t\t-o $@.trx \\\n\t\t-m 33554432 \\\n\t\t-f $(IMAGE_KERNEL) -a 1024\n\t$(STAGING_DIR_HOST)/bin/tplink-safeloader \\\n\t\t-B $(TPLINK_BOARD) \\\n\t\t-k $@.trx \\\n\t\t-r $@ \\\n\t\t-j \\\n\t\t-o $@.new\n\tmv $@.new $@\n\trm $@.trx\nendef\n\ndefine Build/buffalo-wzr-header\n\t$(eval product=$(word 1,$(1)))\n\t$(eval region=$(word 2,$(1)))\n\t( \\\n\t\techo $(product)_$(BUFFALO_TAG_VERSION)_$(BUFFALO_TAG_MINOR)_$(region)_$(BUFFALO_TAG_PLATFORM); \\\n\t\techo filelen=$$(stat -c%s $@); \\\n\t\tcat $@ \\\n\t) > $@.new\n\tmv $@.new $@\nendef\n\n# TRX with only one (kernel) partition\ndefine Build/trx\n\t$(STAGING_DIR_HOST)/bin/trx \\\n\t\t-o $@.new \\\n\t\t-m 33554432 \\\n\t\t-f $@\n\tmv $@.new $@\nendef\n\ndefine Build/trx-serial\n\t$(STAGING_DIR_HOST)/bin/otrx create $@.new \\\n\t\t-f $(IMAGE_KERNEL) -a 1024 \\\n\t\t-f $@ -a 0x10000 -A $(KDIR)/fs_mark\n\tmv $@.new $@\nendef\n\ndefine Build/trx-nand\n\t# kernel: always use 4 MiB (-28 B or TRX header) to allow upgrades even\n\t#\t  if it grows up between releases\n\t# root: UBI with one extra block containing UBI mark to trigger erasing\n\t#\trest of partition\n\t$(STAGING_DIR_HOST)/bin/otrx create $@.new \\\n\t\t-f $(IMAGE_KERNEL) -a 0x20000 -b 0x400000 \\\n\t\t-f $@ \\\n\t\t-A $(KDIR)/ubi_mark -a 0x20000\n\tmv $@.new $@\nendef\n\ndefine Build/asus-trx\n\t$(STAGING_DIR_HOST)/bin/asustrx \\\n\t\t-p $(ASUS_PRODUCTID) -i $@ -o $@.new\n\tmv $@.new $@\nendef\n\ndefine Build/luxul-lxl\n\t$(STAGING_DIR_HOST)/bin/lxlfw create $@.new \\\n\t\t-i $@ \\\n\t\t-b $(LUXUL_BOARD)\n\tmv $@.new $@\nendef\n\ndefine Build/seama-nand\n\t# Seama entity\n\t$(STAGING_DIR_HOST)/bin/oseama \\\n\t\tentity $@.entity \\\n\t\t-m \"dev=/dev/mtdblock/7\" \\\n\t\t-m \"type=firmware\" \\\n\t\t-f $(IMAGE_KERNEL) \\\n\t\t-b 0x400000 \\\n\t\t-f $@ \\\n\t\t-f $(KDIR)/ubi_mark\n\t# Seama container\n\t$(STAGING_DIR_HOST)/bin/seama \\\n\t\t-s $@ \\\n\t\t-m \"signature=$(SIGNATURE)\" \\\n\t\t-i $@.entity\nendef\n\nDEVICE_VARS += ASUS_PRODUCTID\nDEVICE_VARS += BUFFALO_TAG_PLATFORM BUFFALO_TAG_VERSION BUFFALO_TAG_MINOR\nDEVICE_VARS += SIGNATURE\nDEVICE_VARS += NETGEAR_BOARD_ID NETGEAR_REGION TPLINK_BOARD\nDEVICE_VARS += LUXUL_BOARD\n\nIEEE8021X := wpad-basic-wolfssl\nB43 := $(IEEE8021X) kmod-b43\nBRCMFMAC_43602A1 := $(IEEE8021X) kmod-brcmfmac brcmfmac-firmware-43602a1-pcie\nBRCMFMAC_4366B1 := $(IEEE8021X) kmod-brcmfmac brcmfmac-firmware-4366b1-pcie\nBRCMFMAC_4366C0 := $(IEEE8021X) kmod-brcmfmac brcmfmac-firmware-4366c0-pcie\nUSB2_PACKAGES := kmod-usb-ohci kmod-usb2 kmod-phy-bcm-ns-usb2\nUSB2_PACKAGES += kmod-usb-ledtrig-usbport\nUSB3_PACKAGES := $(USB2_PACKAGES) kmod-usb3 kmod-phy-bcm-ns-usb3\n\ndefine Device/Default\n  # .dtb files are prefixed by SoC type, e.g. bcm4708- which is not included in device/image names\n  # extract the full dtb name based on the device info\n  DEVICE_DTS := $(patsubst %.dtb,%,$(notdir $(wildcard $(if $(IB),$(KDIR),$(DTS_DIR))/*-$(subst _,-,$(1)).dtb)))\n  KERNEL := kernel-bin | append-dtb | lzma-d16\n  KERNEL_DEPENDS = $$(wildcard $(DTS_DIR)/$$(DEVICE_DTS).dts)\n  KERNEL_INITRAMFS_SUFFIX := .trx\n  KERNEL_INITRAMFS := kernel-bin | append-dtb | lzma-d16 | trx\n  FILESYSTEMS := squashfs\n  KERNEL_NAME := zImage\n  DEVICE_IMG_NAME = $$(DEVICE_IMG_PREFIX)-$$(1).$$(2)\n  IMAGES := trx\n  BLOCKSIZE := 128k\n  PAGESIZE := 2048\n  IMAGE/trx := append-ubi | trx-nand\nendef\n\ndefine Device/asus\n  DEVICE_VENDOR := ASUS\n  IMAGES := trx\n  IMAGE/trx := append-ubi | trx-nand | asus-trx\nendef\n\ndefine Device/asus_rt-ac56u\n  $(call Device/asus)\n  DEVICE_MODEL := RT-AC56U\n  DEVICE_PACKAGES := $(B43) $(USB3_PACKAGES)\n  ASUS_PRODUCTID := RT-AC56U\nendef\nTARGET_DEVICES += asus_rt-ac56u\n\ndefine Device/asus_rt-ac68u\n  $(call Device/asus)\n  DEVICE_MODEL := RT-AC68U\n  DEVICE_PACKAGES := $(USB3_PACKAGES)\n  ASUS_PRODUCTID := RT-AC68U\nendef\nTARGET_DEVICES += asus_rt-ac68u\n\ndefine Device/asus_rt-ac87u\n  $(call Device/asus)\n  DEVICE_MODEL := RT-AC87U\n  DEVICE_PACKAGES := $(USB3_PACKAGES)\n  ASUS_PRODUCTID := RT-AC87U\nendef\nTARGET_DEVICES += asus_rt-ac87u\n\ndefine Device/asus_rt-ac88u\n  $(call Device/asus)\n  DEVICE_MODEL := RT-AC88U\n  DEVICE_PACKAGES := $(BRCMFMAC_4366C0) $(USB3_PACKAGES)\n  ASUS_PRODUCTID := RT-AC88U\n  BROKEN := y\nendef\nTARGET_DEVICES += asus_rt-ac88u\n\ndefine Device/asus_rt-n18u\n  $(call Device/asus)\n  DEVICE_MODEL := RT-N18U\n  DEVICE_PACKAGES := $(USB3_PACKAGES)\n  ASUS_PRODUCTID := RT-N18U\nendef\nTARGET_DEVICES += asus_rt-n18u\n\n# Buffalo devices have TFTP recovery mode which can work nicely with initramfs\n# kernels.\n# We should have two initramfs images for Buffalo: plain initramfs kernel and\n# TRX with initramfs kernel. It's not possible right now so let's just build\n# plain initramfs kernel as it may be more useful.\ndefine Device/buffalo/Default\n  DEVICE_VENDOR := Buffalo\n  KERNEL_INITRAMFS_SUFFIX = $$(KERNEL_SUFFIX)\n  KERNEL_INITRAMFS = $$(KERNEL)\nendef\n\ndefine Device/buffalo_wxr-1900dhp\n  $(call Device/buffalo/Default)\n  DEVICE_MODEL := WXR-1900DHP\n  DEVICE_PACKAGES := $(USB3_PACKAGES)\nendef\nTARGET_DEVICES += buffalo_wxr-1900dhp\n\ndefine Device/buffalo_wzr-600dhp2\n  $(call Device/buffalo/Default)\n  DEVICE_MODEL := WZR-600DHP2\n  DEVICE_PACKAGES := $(B43) $(USB2_PACKAGES)\nendef\nTARGET_DEVICES += buffalo_wzr-600dhp2\n\ndefine Device/buffalo_wzr-900dhp\n  $(call Device/buffalo/Default)\n  DEVICE_MODEL := WZR-900DHP\n  DEVICE_PACKAGES := $(B43) $(USB3_PACKAGES)\n  BUFFALO_TAG_PLATFORM := bcm\n  BUFFALO_TAG_VERSION := 9.99\n  BUFFALO_TAG_MINOR := 9.99\n  IMAGES += factory-DHP-EU.bin factory-DHP2-JP.bin\n  IMAGE/factory-DHP-EU.bin := \\\n\tappend-ubi | trx-nand | buffalo-wzr-header WZR-900DHP EU | \\\n\tbuffalo-enc WZR-900DHP $$(BUFFALO_TAG_VERSION) | \\\n\tbuffalo-tag-dhp WZR-900DHP EU mlang20 | buffalo-enc-tag | \\\n\tbuffalo-dhp-image\n  IMAGE/factory-DHP2-JP.bin := \\\n\tappend-ubi | trx-nand | buffalo-wzr-header WZR-900DHP2 JP | \\\n\tbuffalo-enc WZR-900DHP2 $$(BUFFALO_TAG_VERSION) | \\\n\tbuffalo-tag-dhp WZR-900DHP2 JP jp | buffalo-enc-tag | \\\n\tbuffalo-dhp-image\nendef\nTARGET_DEVICES += buffalo_wzr-900dhp\n\ndefine Device/buffalo_wzr-1750dhp\n  $(call Device/buffalo/Default)\n  DEVICE_MODEL := WZR-1750DHP\n  DEVICE_PACKAGES := $(B43) $(USB3_PACKAGES)\nendef\nTARGET_DEVICES += buffalo_wzr-1750dhp\n\ndefine Device/dlink\n  DEVICE_VENDOR := D-Link\n  IMAGES := bin\n  IMAGE/bin := append-ubi | seama-nand\nendef\n\ndefine Device/dlink_dir-885l\n  DEVICE_MODEL := DIR-885L\n  DEVICE_PACKAGES := $(BRCMFMAC_4366B1) $(USB3_PACKAGES)\n  $(Device/dlink)\n  SIGNATURE := wrgac42_dlink.2015_dir885l\nendef\nTARGET_DEVICES += dlink_dir-885l\n\ndefine Device/linksys_ea6300-v1\n  DEVICE_VENDOR := Linksys\n  DEVICE_MODEL := EA6300\n  DEVICE_VARIANT := v1\n  DEVICE_PACKAGES := $(B43) $(USB3_PACKAGES)\nendef\nTARGET_DEVICES += linksys_ea6300-v1\n\ndefine Device/linksys_ea6500-v2\n  DEVICE_VENDOR := Linksys\n  DEVICE_MODEL := EA6500\n  DEVICE_VARIANT := v2\n  DEVICE_PACKAGES := $(B43) $(USB3_PACKAGES)\nendef\nTARGET_DEVICES += linksys_ea6500-v2\n\ndefine Device/linksys_ea9200\n  DEVICE_VENDOR := Linksys\n  DEVICE_MODEL := EA9200\n  DEVICE_VARIANT := v1\n  DEVICE_PACKAGES := $(BRCMFMAC_43602A1) $(USB3_PACKAGES)\nendef\nTARGET_DEVICES += linksys_ea9200\n\ndefine Device/linksys_ea9500\n  DEVICE_VENDOR := Linksys\n  DEVICE_MODEL := EA9500\n  DEVICE_PACKAGES := $(BRCMFMAC_4366C0) $(USB3_PACKAGES)\n  DEVICE_DTS := bcm47094-linksys-panamera\nendef\nTARGET_DEVICES += linksys_ea9500\n\ndefine Device/luxul\n  DEVICE_VENDOR := Luxul\n  IMAGES := lxl\n  IMAGE/lxl := append-ubi | trx-nand | luxul-lxl\nendef\n\ndefine Device/luxul_abr-4500\n  $(Device/luxul)\n  DEVICE_MODEL := ABR-4500\n  DEVICE_PACKAGES := $(USB3_PACKAGES)\n  LUXUL_BOARD := ABR-4500\nendef\nTARGET_DEVICES += luxul_abr-4500\n\ndefine Device/luxul_xap-1610\n  $(Device/luxul)\n  DEVICE_MODEL := XAP-1610\n  DEVICE_PACKAGES := $(BRCMFMAC_4366C0)\n  IMAGE/lxl := append-rootfs | trx-serial | luxul-lxl\n  LUXUL_BOARD := XAP-1610\nendef\nTARGET_DEVICES += luxul_xap-1610\n\ndefine Device/luxul_xbr-4500\n  $(Device/luxul)\n  DEVICE_MODEL := XBR-4500\n  DEVICE_PACKAGES := $(USB3_PACKAGES)\n  LUXUL_BOARD := XBR-4500\nendef\nTARGET_DEVICES += luxul_xbr-4500\n\ndefine Device/luxul_xwr-3150\n  $(Device/luxul)\n  DEVICE_MODEL := XWR-3150\n  DEVICE_PACKAGES := $(BRCMFMAC_4366C0) $(USB3_PACKAGES)\n  DEVICE_DTS := bcm47094-luxul-xwr-3150-v1\n  LUXUL_BOARD := XWR-3150\nendef\nTARGET_DEVICES += luxul_xwr-3150\n\ndefine Device/meraki_mr32\n  DEVICE_VENDOR := Meraki\n  DEVICE_MODEL := MR32\n  DEVICE_PACKAGES := $(B43) kmod-i2c-bcm-iproc kmod-eeprom-at24 \\\n\tkmod-leds-pwm kmod-hwmon-ina2xx kmod-bluetooth\n  DEVICE_DTS := bcm53016-meraki-mr32\n# Meraki FW r23 tries to resize the part.safe partition before it will\n# flash the image. This is a bit of a problem, since resizing will fail\n# if the partition is smaller than the old one.\n  KERNEL_LOADADDR := 0x00008000\n  KERNEL_INITRAMFS_SUFFIX := .bin\n  DEVICE_DTS_DELIMITER := @\n  DEVICE_DTS_CONFIG := config@1\n  KERNEL_INITRAMFS := kernel-bin | fit none $$(DTS_DIR)/$$(DEVICE_DTS).dtb | \\\n\tpad-to 10362880\n  KERNEL := kernel-bin | fit none $$(DTS_DIR)/$$(DEVICE_DTS).dtb\n  IMAGES += sysupgrade.bin\n# Currently the only device that uses the new image check\n  IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata\n\n# The loader is specifically looking for fdt@2:\n# [    3.190000] find_itb_subimage: error finding fdt@2: FDT_ERR_NOTFOUND\n# The image won't boot, if it isn't found. :(\n  DEVICE_FDT_NUM := 2\nendef\nTARGET_DEVICES += meraki_mr32\n\ndefine Device/netgear\n  DEVICE_VENDOR := NETGEAR\n  IMAGES := chk\n  IMAGE/chk := append-ubi | trx-nand | netgear-chk\n  NETGEAR_REGION := 1\nendef\n\ndefine Device/netgear_r6250\n  DEVICE_MODEL := R6250\n  DEVICE_PACKAGES := $(B43) $(USB3_PACKAGES)\n  $(Device/netgear)\n  NETGEAR_BOARD_ID := U12H245T00_NETGEAR\nendef\nTARGET_DEVICES += netgear_r6250\n\ndefine Device/netgear_r6300-v2\n  DEVICE_MODEL := R6300\n  DEVICE_VARIANT := v2\n  DEVICE_PACKAGES := $(B43) $(USB3_PACKAGES)\n  $(Device/netgear)\n  NETGEAR_BOARD_ID := U12H240T00_NETGEAR\nendef\nTARGET_DEVICES += netgear_r6300-v2\n\ndefine Device/netgear_r7000\n  DEVICE_MODEL := R7000\n  DEVICE_PACKAGES := $(USB3_PACKAGES)\n  $(Device/netgear)\n  NETGEAR_BOARD_ID := U12H270T00_NETGEAR\nendef\nTARGET_DEVICES += netgear_r7000\n\ndefine Device/netgear_r7900\n  DEVICE_MODEL := R7900\n  DEVICE_PACKAGES := $(BRCMFMAC_43602A1) $(USB3_PACKAGES)\n  $(Device/netgear)\n  NETGEAR_BOARD_ID := U12H315T30_NETGEAR\nendef\nTARGET_DEVICES += netgear_r7900\n\ndefine Device/netgear_r8000\n  DEVICE_MODEL := R8000\n  DEVICE_PACKAGES := $(BRCMFMAC_43602A1) $(USB3_PACKAGES)\n  $(Device/netgear)\n  NETGEAR_BOARD_ID := U12H315T00_NETGEAR\nendef\nTARGET_DEVICES += netgear_r8000\n\ndefine Device/netgear_r8500\n  DEVICE_MODEL := R8500\n  DEVICE_PACKAGES := $(BRCMFMAC_4366B1) $(USB3_PACKAGES)\n  $(Device/netgear)\n  NETGEAR_BOARD_ID := U12H334T00_NETGEAR\n  DEFAULT := n\nendef\nTARGET_DEVICES += netgear_r8500\n\ndefine Device/smartrg_sr400ac\n  DEVICE_VENDOR := SmartRG\n  DEVICE_MODEL := SR400ac\n  DEVICE_PACKAGES := $(BRCMFMAC_43602A1) $(USB3_PACKAGES)\n  IMAGES := trx\n  IMAGE/trx := append-rootfs | trx-serial\n  KERNEL_INITRAMFS_SUFFIX := .bin\n  KERNEL_INITRAMFS := kernel-bin | append-dtb | lzma-d16\nendef\nTARGET_DEVICES += smartrg_sr400ac\n\ndefine Device/phicomm_k3\n  DEVICE_VENDOR := PHICOMM\n  DEVICE_MODEL := K3\n  DEVICE_PACKAGES := $(BRCMFMAC_4366C0) $(USB3_PACKAGES)\n  IMAGES := trx\nendef\nTARGET_DEVICES += phicomm_k3\n\ndefine Device/tenda_ac9\n  DEVICE_VENDOR := Tenda\n  DEVICE_MODEL := AC9\n  DEVICE_PACKAGES := $(B43) $(USB2_PACKAGES)\n  IMAGES := trx\n  IMAGE/trx := append-rootfs | trx-serial\nendef\nTARGET_DEVICES += tenda_ac9\n\ndefine Device/tplink_archer-c5-v2\n  DEVICE_VENDOR := TP-Link\n  DEVICE_MODEL := Archer C5\n  DEVICE_VARIANT := v2\n  DEVICE_PACKAGES := $(B43) $(USB2_PACKAGES)\n  IMAGES := bin\n  IMAGE/bin := append-rootfs | bcm53xx-tplink-safeloader\n  TPLINK_BOARD := ARCHER-C5-V2\n  BROKEN := y\nendef\n#TARGET_DEVICES += tplink_archer-c5-v2\n\ndefine Device/tplink_archer-c9-v1\n  DEVICE_VENDOR := TP-Link\n  DEVICE_MODEL := Archer C9\n  DEVICE_VARIANT := v1\n  DEVICE_PACKAGES := $(USB3_PACKAGES)\n  IMAGES := bin\n  IMAGE/bin := append-rootfs | bcm53xx-tplink-safeloader\n  TPLINK_BOARD := ARCHERC9\n  BROKEN := y\nendef\n#TARGET_DEVICES += tplink_archer-c9-v1\n\n$(eval $(call BuildImage))\n"
  },
  {
    "path": "target/linux/bcm53xx/modules.mk",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2016 Rafał Miłecki <rafal@milecki.pl>\n\ndefine KernelPackage/phy-bcm-ns-usb2\n  TITLE:=Broadcom Northstar USB 2.0 PHY Driver\n  KCONFIG:=CONFIG_PHY_BCM_NS_USB2\n  DEPENDS:=@TARGET_bcm53xx\n  SUBMENU:=$(USB_MENU)\n  FILES:=$(LINUX_DIR)/drivers/phy/broadcom/phy-bcm-ns-usb2.ko\n  AUTOLOAD:=$(call AutoLoad,45,phy-bcm-ns-usb2,1)\nendef\n\ndefine KernelPackage/phy-bcm-ns-usb2/description\n  Support for Broadcom USB 2.0 PHY connected to the USB controller on Northstar\n  family.\nendef\n\n$(eval $(call KernelPackage,phy-bcm-ns-usb2))\n\ndefine KernelPackage/phy-bcm-ns-usb3\n  TITLE:=Broadcom Northstar USB 3.0 PHY Driver\n  KCONFIG:=CONFIG_PHY_BCM_NS_USB3\n  DEPENDS:=@TARGET_bcm53xx\n  SUBMENU:=$(USB_MENU)\n  FILES:=$(LINUX_DIR)/drivers/phy/broadcom/phy-bcm-ns-usb3.ko\n  AUTOLOAD:=$(call AutoLoad,45,phy-bcm-ns-usb3,1)\nendef\n\ndefine KernelPackage/phy-bcm-ns-usb3/description\n  Support for Broadcom USB 3.0 PHY connected to the USB controller on Northstar\n  family.\nendef\n\n$(eval $(call KernelPackage,phy-bcm-ns-usb3))\n\ndefine KernelPackage/i2c-bcm-iproc\n  TITLE:=Broadcom iProc I2C controller\n  KCONFIG:= \\\n\tCONFIG_I2C_BCM_IPROC \\\n\tCONFIG_I2C_SLAVE_TESTUNIT=n\n  DEPENDS:=@TARGET_bcm53xx +kmod-i2c-core\n  SUBMENU:=$(I2C_MENU)\n  FILES:=$(LINUX_DIR)/drivers/i2c/busses/i2c-bcm-iproc.ko\n  AUTOLOAD:=$(call AutoLoad,59,i2c-bcm-iproc,1)\nendef\n\ndefine KernelPackage/i2c-bcm-iproc/description\n Kernel module for the Broadcom iProc I2C controller.\nendef\n\n$(eval $(call KernelPackage,i2c-bcm-iproc))\n"
  },
  {
    "path": "target/linux/bcm53xx/patches-5.10/030-v5.11-0001-ARM-dts-BCM5301X-Linksys-EA9500-add-port-5-and-port-.patch",
    "content": "From 1ca5f2430c4f9d85b98b8d6e5d93f8d4802faf8e Mon Sep 17 00:00:00 2001\nFrom: Vivek Unune <npcomplete13@gmail.com>\nDate: Wed, 14 Oct 2020 15:27:27 -0400\nSubject: [PATCH] ARM: dts: BCM5301X: Linksys EA9500 add port 5 and port 7\n\nAdd ports 5 and 7 which are connected to gmac cores 1 & 2.\nThese will be disabled for now.\n\nSigned-off-by: Vivek Unune <npcomplete13@gmail.com>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n .../boot/dts/bcm47094-linksys-panamera.dts    | 24 +++++++++++++++++++\n 1 file changed, 24 insertions(+)\n\n--- a/arch/arm/boot/dts/bcm47094-linksys-panamera.dts\n+++ b/arch/arm/boot/dts/bcm47094-linksys-panamera.dts\n@@ -242,6 +242,30 @@\n \t\t\tlabel = \"wan\";\n \t\t};\n \n+\t\tport@5 {\n+\t\t\treg = <5>;\n+\t\t\tethernet = <&gmac0>;\n+\t\t\tlabel = \"cpu\";\n+\t\t\tstatus = \"disabled\";\n+\n+\t\t\tfixed-link {\n+\t\t\t\tspeed = <1000>;\n+\t\t\t\tfull-duplex;\n+\t\t\t};\n+\t\t};\n+\n+\t\tport@7 {\n+\t\t\treg = <7>;\n+\t\t\tethernet = <&gmac1>;\n+\t\t\tlabel = \"cpu\";\n+\t\t\tstatus = \"disabled\";\n+\n+\t\t\tfixed-link {\n+\t\t\t\tspeed = <1000>;\n+\t\t\t\tfull-duplex;\n+\t\t\t};\n+\t\t};\n+\n \t\tport@8 {\n \t\t\treg = <8>;\n \t\t\tethernet = <&gmac2>;\n"
  },
  {
    "path": "target/linux/bcm53xx/patches-5.10/030-v5.11-0002-ARM-dts-BCM5301X-Harmonize-EHCI-OHCI-DT-nodes-name.patch",
    "content": "From 74abbfe99f43eb7466d26d9e48fbeb46b8f3d804 Mon Sep 17 00:00:00 2001\nFrom: Serge Semin <Sergey.Semin@baikalelectronics.ru>\nDate: Tue, 20 Oct 2020 14:59:37 +0300\nSubject: [PATCH] ARM: dts: BCM5301X: Harmonize EHCI/OHCI DT nodes name\n\nIn accordance with the Generic EHCI/OHCI bindings the corresponding node\nname is suppose to comply with the Generic USB HCD DT schema, which\nrequires the USB nodes to have the name acceptable by the regexp:\n\"^usb(@.*)?\" . Make sure the \"generic-ehci\" and \"generic-ohci\"-compatible\nnodes are correctly named.\n\nSigned-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>\nAcked-by: Florian Fainelli <f.fainelli@gmail.com>\nAcked-by: Krzysztof Kozlowski <krzk@kernel.org>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n arch/arm/boot/dts/bcm5301x.dtsi | 4 ++--\n arch/arm/boot/dts/bcm53573.dtsi | 4 ++--\n 2 files changed, 4 insertions(+), 4 deletions(-)\n\n--- a/arch/arm/boot/dts/bcm5301x.dtsi\n+++ b/arch/arm/boot/dts/bcm5301x.dtsi\n@@ -267,7 +267,7 @@\n \n \t\t\tinterrupt-parent = <&gic>;\n \n-\t\t\tehci: ehci@21000 {\n+\t\t\tehci: usb@21000 {\n \t\t\t\t#usb-cells = <0>;\n \n \t\t\t\tcompatible = \"generic-ehci\";\n@@ -289,7 +289,7 @@\n \t\t\t\t};\n \t\t\t};\n \n-\t\t\tohci: ohci@22000 {\n+\t\t\tohci: usb@22000 {\n \t\t\t\t#usb-cells = <0>;\n \n \t\t\t\tcompatible = \"generic-ohci\";\n--- a/arch/arm/boot/dts/bcm53573.dtsi\n+++ b/arch/arm/boot/dts/bcm53573.dtsi\n@@ -135,7 +135,7 @@\n \t\t\t#address-cells = <1>;\n \t\t\t#size-cells = <1>;\n \n-\t\t\tehci: ehci@4000 {\n+\t\t\tehci: usb@4000 {\n \t\t\t\tcompatible = \"generic-ehci\";\n \t\t\t\treg = <0x4000 0x1000>;\n \t\t\t\tinterrupt-parent = <&gic>;\n@@ -155,7 +155,7 @@\n \t\t\t\t};\n \t\t\t};\n \n-\t\t\tohci: ohci@d000 {\n+\t\t\tohci: usb@d000 {\n \t\t\t\t#usb-cells = <0>;\n \n \t\t\t\tcompatible = \"generic-ohci\";\n"
  },
  {
    "path": "target/linux/bcm53xx/patches-5.10/030-v5.11-0003-ARM-dts-BCM5310X-Harmonize-xHCI-DT-nodes-name.patch",
    "content": "From 4b650a20bdb5f9558007dd3055a17a1644a91c3e Mon Sep 17 00:00:00 2001\nFrom: Serge Semin <Sergey.Semin@baikalelectronics.ru>\nDate: Tue, 20 Oct 2020 14:59:46 +0300\nSubject: [PATCH] ARM: dts: BCM5310X: Harmonize xHCI DT nodes name\n\nIn accordance with the Generic xHCI bindings the corresponding node\nname is suppose to comply with the Generic USB HCD DT schema, which\nrequires the USB nodes to have the name acceptable by the regexp:\n\"^usb(@.*)?\" . Make sure the \"generic-xhci\"-compatible nodes are\ncorrectly named.\n\nSigned-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>\nAcked-by: Krzysztof Kozlowski <krzk@kernel.org>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n arch/arm/boot/dts/bcm5301x.dtsi | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/arch/arm/boot/dts/bcm5301x.dtsi\n+++ b/arch/arm/boot/dts/bcm5301x.dtsi\n@@ -320,7 +320,7 @@\n \n \t\t\tinterrupt-parent = <&gic>;\n \n-\t\t\txhci: xhci@23000 {\n+\t\t\txhci: usb@23000 {\n \t\t\t\t#usb-cells = <0>;\n \n \t\t\t\tcompatible = \"generic-xhci\";\n"
  },
  {
    "path": "target/linux/bcm53xx/patches-5.10/030-v5.11-0004-ARM-dts-BCM5301X-Linksys-EA9500-add-fixed-partitions.patch",
    "content": "From bd9a01e28e5d1632528e531480b42d6e2c861d88 Mon Sep 17 00:00:00 2001\nFrom: Vivek Unune <npcomplete13@gmail.com>\nDate: Sun, 1 Nov 2020 15:08:03 -0500\nSubject: [PATCH] ARM: dts: BCM5301X: Linksys EA9500 add fixed partitions\n\nThis router has dual paritions to store trx firmware image and\ndual partitions for nvram. The second one in each of these cases acts\nas a backup store.\n\nWhen tested with OpenWrt, the default partition parser causes two issues:\n\n1. It labels both nvram partitions as nvram. In factory, second one is\nlabeled devinfo.\n2. It parses second trx image and tries to create second 'linux' partition\nand fails with - cannot create duplicate 'linux' partition\n\nThe following patch works around both of these issues.\n\nSigned-off-by: Vivek Unune <npcomplete13@gmail.com>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n .../boot/dts/bcm47094-linksys-panamera.dts    | 41 +++++++++++++++++++\n 1 file changed, 41 insertions(+)\n\n--- a/arch/arm/boot/dts/bcm47094-linksys-panamera.dts\n+++ b/arch/arm/boot/dts/bcm47094-linksys-panamera.dts\n@@ -292,3 +292,44 @@\n &usb3_phy {\n \tstatus = \"okay\";\n };\n+\n+&nandcs {\n+\tpartitions {\n+\t\tcompatible = \"fixed-partitions\";\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <1>;\n+\n+\t\tpartition@0 {\n+\t\t\tlabel = \"boot\";\n+\t\t\treg = <0x0000000 0x0080000>;\n+\t\t\tread-only;\n+\t\t};\n+\n+\t\tpartition@80000 {\n+\t\t\tlabel = \"nvram\";\n+\t\t\treg = <0x080000 0x0100000>;\n+\t\t};\n+\n+\t\tpartition@180000{\n+\t\t\tlabel = \"devinfo\";\n+\t\t\treg = <0x0180000 0x080000>;\n+\t\t};\n+\n+\t\tpartition@200000 {\n+\t\t\tlabel = \"firmware\";\n+\t\t\treg = <0x0200000 0x01D00000>;\n+\t\t\tcompatible = \"brcm,trx\";\n+\t\t};\n+\n+\t\tpartition@1F00000 {\n+\t\t\tlabel = \"failsafe\";\n+\t\t\treg = <0x01F00000 0x01D00000>;\n+\t\t\tread-only;\n+\t\t};\n+\n+\t\tpartition@5200000 {\n+\t\t\tlabel = \"system\";\n+\t\t\treg = <0x05200000 0x02E00000>;\n+\t\t};\n+\t};\n+};\n"
  },
  {
    "path": "target/linux/bcm53xx/patches-5.10/030-v5.11-0005-ARM-dts-BCM5301X-Use-corretc-pinctrl-compatible-for-.patch",
    "content": "From 2f34ae32f5e74096540cd7ce95bfd467cb74b21a Mon Sep 17 00:00:00 2001\nFrom: Vivek Unune <npcomplete13@gmail.com>\nDate: Wed, 4 Nov 2020 15:29:51 -0500\nSubject: [PATCH] ARM: dts: BCM5301X: Use corretc pinctrl compatible for 4709x\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nBCM47094 version of pinmux uses different compatible and supports MDIO\npinmux pins. Hence, use the correct compatible string and defines the\nMDIO pins group.\n\nSigned-off-by: Vivek Unune <npcomplete13@gmail.com>\nAcked-by: Rafał Miłecki <rafal@milecki.pl>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n arch/arm/boot/dts/bcm47094.dtsi | 9 +++++++++\n arch/arm/boot/dts/bcm5301x.dtsi | 2 +-\n 2 files changed, 10 insertions(+), 1 deletion(-)\n\n--- a/arch/arm/boot/dts/bcm47094.dtsi\n+++ b/arch/arm/boot/dts/bcm47094.dtsi\n@@ -8,6 +8,15 @@\n / {\n };\n \n+&pinctrl {\n+\tcompatible = \"brcm,bcm4709-pinmux\";\n+\n+\tpinmux_mdio: mdio {\n+\t\tgroups = \"mdio_grp\";\n+\t\tfunction = \"mdio\";\n+\t};\n+};\n+\n &usb3_phy {\n \tcompatible = \"brcm,ns-bx-usb3-phy\";\n };\n--- a/arch/arm/boot/dts/bcm5301x.dtsi\n+++ b/arch/arm/boot/dts/bcm5301x.dtsi\n@@ -430,7 +430,7 @@\n \t\t\t#address-cells = <1>;\n \t\t\t#size-cells = <1>;\n \n-\t\t\tpin-controller@1c0 {\n+\t\t\tpinctrl: pin-controller@1c0 {\n \t\t\t\tcompatible = \"brcm,bcm4708-pinmux\";\n \t\t\t\treg = <0x1c0 0x24>;\n \t\t\t\treg-names = \"cru_gpio_control\";\n"
  },
  {
    "path": "target/linux/bcm53xx/patches-5.10/030-v5.11-0006-ARM-dts-BCM5301X-Linksys-EA9500-make-use-of-pinctrl.patch",
    "content": "From c862059875cffc013ee27bf9759ac288224e7a14 Mon Sep 17 00:00:00 2001\nFrom: Vivek Unune <npcomplete13@gmail.com>\nDate: Wed, 4 Nov 2020 15:29:52 -0500\nSubject: [PATCH] ARM: dts: BCM5301X: Linksys EA9500 make use of pinctrl\n\nNow that we have a pin controller, use that instead of manuplating the\nmdio/mdc pins directly. i.e. we no longer require the mdio-mii-mux\n\nSigned-off-by: Vivek Unune <npcomplete13@gmail.com>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n .../boot/dts/bcm47094-linksys-panamera.dts    | 26 +++----------------\n 1 file changed, 4 insertions(+), 22 deletions(-)\n\n--- a/arch/arm/boot/dts/bcm47094-linksys-panamera.dts\n+++ b/arch/arm/boot/dts/bcm47094-linksys-panamera.dts\n@@ -123,33 +123,13 @@\n \t\t};\n \t};\n \n-\tmdio-bus-mux {\n-\t\t#address-cells = <1>;\n-\t\t#size-cells = <0>;\n+\tmdio-bus-mux@18003000 {\n \n \t\t/* BIT(9) = 1 => external mdio */\n-\t\tmdio_ext: mdio@200 {\n+\t\tmdio@200 {\n \t\t\treg = <0x200>;\n \t\t\t#address-cells = <1>;\n \t\t\t#size-cells = <0>;\n-\t\t};\n-\t};\n-\n-\tmdio-mii-mux {\n-\t\tcompatible = \"mdio-mux-mmioreg\";\n-\t\tmdio-parent-bus = <&mdio_ext>;\n-\t\t#address-cells = <1>;\n-\t\t#size-cells = <0>;\n-\t\treg = <0x1800c1c0 0x4>;\n-\n-\t\t/* BIT(6) = mdc, BIT(7) = mdio */\n-\t\tmux-mask = <0xc0>;\n-\n-\t\tmdio-mii@0 {\n-\t\t\t/* Enable MII function */\n-\t\t\treg = <0x0>;\n-\t\t\t#address-cells = <1>;\n-\t\t\t#size-cells = <0>;\n \n \t\t\tswitch@0  {\n \t\t\t\tcompatible = \"brcm,bcm53125\";\n@@ -159,6 +139,8 @@\n \t\t\t\treset-names = \"robo_reset\";\n \t\t\t\treg = <0>;\n \t\t\t\tdsa,member = <1 0>;\n+\t\t\t\tpinctrl-names = \"default\";\n+\t\t\t\tpinctrl-0 = <&pinmux_mdio>;\n \n \t\t\t\tports {\n \t\t\t\t\t#address-cells = <1>;\n"
  },
  {
    "path": "target/linux/bcm53xx/patches-5.10/030-v5.11-0007-ARM-dts-BCM5301X-Move-CRU-devices-to-the-CRU-node.patch",
    "content": "From 776461b1795b4dc4084894cf53399044aafa1d21 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Wed, 11 Nov 2020 15:55:38 +0100\nSubject: [PATCH] ARM: dts: BCM5301X: Move CRU devices to the CRU node\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nClocks and thermal blocks are part of the CRU (\"Clock and Reset Unit\" or\n\"Central Resource Unit\").\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n arch/arm/boot/dts/bcm5301x.dtsi | 51 +++++++++++++++++----------------\n 1 file changed, 26 insertions(+), 25 deletions(-)\n\n--- a/arch/arm/boot/dts/bcm5301x.dtsi\n+++ b/arch/arm/boot/dts/bcm5301x.dtsi\n@@ -430,6 +430,26 @@\n \t\t\t#address-cells = <1>;\n \t\t\t#size-cells = <1>;\n \n+\t\t\tlcpll0: lcpll0@100 {\n+\t\t\t\t#clock-cells = <1>;\n+\t\t\t\tcompatible = \"brcm,nsp-lcpll0\";\n+\t\t\t\treg = <0x100 0x14>;\n+\t\t\t\tclocks = <&osc>;\n+\t\t\t\tclock-output-names = \"lcpll0\", \"pcie_phy\",\n+\t\t\t\t\t\t     \"sdio\", \"ddr_phy\";\n+\t\t\t};\n+\n+\t\t\tgenpll: genpll@140 {\n+\t\t\t\t#clock-cells = <1>;\n+\t\t\t\tcompatible = \"brcm,nsp-genpll\";\n+\t\t\t\treg = <0x140 0x24>;\n+\t\t\t\tclocks = <&osc>;\n+\t\t\t\tclock-output-names = \"genpll\", \"phy\",\n+\t\t\t\t\t\t     \"ethernetclk\",\n+\t\t\t\t\t\t     \"usbclk\", \"iprocfast\",\n+\t\t\t\t\t\t     \"sata1\", \"sata2\";\n+\t\t\t};\n+\n \t\t\tpinctrl: pin-controller@1c0 {\n \t\t\t\tcompatible = \"brcm,bcm4708-pinmux\";\n \t\t\t\treg = <0x1c0 0x24>;\n@@ -456,32 +476,13 @@\n \t\t\t\t\tfunction = \"uart1\";\n \t\t\t\t};\n \t\t\t};\n-\t\t};\n-\t};\n \n-\tlcpll0: lcpll0@1800c100 {\n-\t\t#clock-cells = <1>;\n-\t\tcompatible = \"brcm,nsp-lcpll0\";\n-\t\treg = <0x1800c100 0x14>;\n-\t\tclocks = <&osc>;\n-\t\tclock-output-names = \"lcpll0\", \"pcie_phy\", \"sdio\",\n-\t\t\t\t     \"ddr_phy\";\n-\t};\n-\n-\tgenpll: genpll@1800c140 {\n-\t\t#clock-cells = <1>;\n-\t\tcompatible = \"brcm,nsp-genpll\";\n-\t\treg = <0x1800c140 0x24>;\n-\t\tclocks = <&osc>;\n-\t\tclock-output-names = \"genpll\", \"phy\", \"ethernetclk\",\n-\t\t\t\t     \"usbclk\", \"iprocfast\", \"sata1\",\n-\t\t\t\t     \"sata2\";\n-\t};\n-\n-\tthermal: thermal@1800c2c0 {\n-\t\tcompatible = \"brcm,ns-thermal\";\n-\t\treg = <0x1800c2c0 0x10>;\n-\t\t#thermal-sensor-cells = <0>;\n+\t\t\tthermal: thermal@2c0 {\n+\t\t\t\tcompatible = \"brcm,ns-thermal\";\n+\t\t\t\treg = <0x2c0 0x10>;\n+\t\t\t\t#thermal-sensor-cells = <0>;\n+\t\t\t};\n+\t\t};\n \t};\n \n \tsrab: srab@18007000 {\n"
  },
  {
    "path": "target/linux/bcm53xx/patches-5.10/030-v5.11-0008-ARM-dts-BCM5301X-Disable-USB-3-PHY-on-devices-withou.patch",
    "content": "From 632ddf978565378e7efb9ea77c0ba239ea66bfdc Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Fri, 13 Nov 2020 11:09:19 +0100\nSubject: [PATCH] ARM: dts: BCM5301X: Disable USB 3 PHY on devices without USB\n 3\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nIt seems pointless to have it enabled.\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts       | 4 ----\n arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts       | 4 ----\n arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts | 4 ----\n arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts      | 4 ----\n arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts      | 4 ----\n arch/arm/boot/dts/bcm47081-tplink-archer-c5-v2.dts | 4 ----\n 6 files changed, 24 deletions(-)\n\n--- a/arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts\n+++ b/arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts\n@@ -57,10 +57,6 @@\n \tstatus = \"okay\";\n };\n \n-&usb3_phy {\n-\tstatus = \"okay\";\n-};\n-\n &srab {\n \tstatus = \"okay\";\n \n--- a/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts\n+++ b/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts\n@@ -64,10 +64,6 @@\n \tstatus = \"okay\";\n };\n \n-&usb3_phy {\n-\tstatus = \"okay\";\n-};\n-\n &srab {\n \tstatus = \"okay\";\n \n--- a/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts\n+++ b/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts\n@@ -117,7 +117,3 @@\n \t\t};\n \t};\n };\n-\n-&usb3_phy {\n-\tstatus = \"okay\";\n-};\n--- a/arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts\n+++ b/arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts\n@@ -57,10 +57,6 @@\n \tstatus = \"okay\";\n };\n \n-&usb3_phy {\n-\tstatus = \"okay\";\n-};\n-\n &srab {\n \tstatus = \"okay\";\n \n--- a/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts\n+++ b/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts\n@@ -105,10 +105,6 @@\n \tstatus = \"okay\";\n };\n \n-&usb3_phy {\n-\tstatus = \"okay\";\n-};\n-\n &srab {\n \tstatus = \"okay\";\n \n--- a/arch/arm/boot/dts/bcm47081-tplink-archer-c5-v2.dts\n+++ b/arch/arm/boot/dts/bcm47081-tplink-archer-c5-v2.dts\n@@ -126,7 +126,3 @@\n &usb2 {\n \tvcc-gpio = <&chipcommon 9 GPIO_ACTIVE_HIGH>;\n };\n-\n-&usb3_phy {\n-\tstatus = \"okay\";\n-};\n"
  },
  {
    "path": "target/linux/bcm53xx/patches-5.10/030-v5.11-0009-ARM-dts-BCM5301X-Enable-USB-3-PHY-on-Luxul-XWR-3150.patch",
    "content": "From b2ab5e8697ef6591aeeda23be49e096705dbbda3 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Fri, 13 Nov 2020 10:50:12 +0100\nSubject: [PATCH] ARM: dts: BCM5301X: Enable USB 3 PHY on Luxul XWR-3150\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nThis device has a functional USB 3 port so PHY is required.\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nReported-by: kernel test robot <lkp@intel.com>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts | 4 ++++\n 1 file changed, 4 insertions(+)\n\n--- a/arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts\n+++ b/arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts\n@@ -71,6 +71,10 @@\n \tvcc-gpio = <&chipcommon 18 GPIO_ACTIVE_HIGH>;\n };\n \n+&usb3_phy {\n+\tstatus = \"okay\";\n+};\n+\n &spi_nor {\n \tstatus = \"okay\";\n };\n"
  },
  {
    "path": "target/linux/bcm53xx/patches-5.10/030-v5.11-0010-ARM-dts-BCM5301X-Update-Ethernet-switch-node-name.patch",
    "content": "From f527cb6f3345f7faa8e61dd9f3c437437327428c Mon Sep 17 00:00:00 2001\nFrom: Florian Fainelli <f.fainelli@gmail.com>\nDate: Mon, 9 Nov 2020 11:41:01 -0800\nSubject: [PATCH] ARM: dts: BCM5301X: Update Ethernet switch node name\n\nUpdate the switch unit name from srab to ethernet-switch, allowing us to\nfix warnings such as:\n\n  CHECK   arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dt.yaml\narch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dt.yaml:\nsrab@18007000: $nodename:0: 'srab@18007000' does not match\n'^(ethernet-)?switch(@.*)?$'\n        From schema:\nDocumentation/devicetree/bindings/net/dsa/b53.yaml\n\nReviewed-by: Vladimir Oltean <olteanv@gmail.com>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n arch/arm/boot/dts/bcm5301x.dtsi | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/arch/arm/boot/dts/bcm5301x.dtsi\n+++ b/arch/arm/boot/dts/bcm5301x.dtsi\n@@ -485,7 +485,7 @@\n \t\t};\n \t};\n \n-\tsrab: srab@18007000 {\n+\tsrab: ethernet-switch@18007000 {\n \t\tcompatible = \"brcm,bcm5301x-srab\";\n \t\treg = <0x18007000 0x1000>;\n \n"
  },
  {
    "path": "target/linux/bcm53xx/patches-5.10/030-v5.11-0011-ARM-dts-BCM5301X-Add-a-default-compatible-for-switch.patch",
    "content": "From 953efcb0c0234f8c488ebd4090378e949d6ba78b Mon Sep 17 00:00:00 2001\nFrom: Florian Fainelli <f.fainelli@gmail.com>\nDate: Mon, 9 Nov 2020 16:42:09 -0800\nSubject: [PATCH] ARM: dts: BCM5301X: Add a default compatible for switch node\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nProvide a default compatible string which is based on the 53011 SRAB\ncompatible by default. The 4709 and 47094 default to the 53012 SRAB\ncompatible.\n\nThis allows us to have sane defaults and silences the following\nwarnings:\n\narch/arm/boot/dts/bcm4708-asus-rt-ac56u.dt.yaml:\nethernet-switch@18007000: compatible: 'oneOf' conditional failed, one\nmust be fixed:\n        ['brcm,bcm5301x-srab'] is too short\n        'brcm,bcm5325' was expected\n        'brcm,bcm53115' was expected\n        'brcm,bcm53125' was expected\n        'brcm,bcm53128' was expected\n        'brcm,bcm5365' was expected\n        'brcm,bcm5395' was expected\n        'brcm,bcm5389' was expected\n        'brcm,bcm5397' was expected\n        'brcm,bcm5398' was expected\n        'brcm,bcm11360-srab' was expected\n        'brcm,bcm5301x-srab' is not one of ['brcm,bcm53010-srab',\n'brcm,bcm53011-srab', 'brcm,bcm53012-srab', 'brcm,bcm53018-srab',\n'brcm,bcm53019-srab']\n        'brcm,bcm5301x-srab' is not one of ['brcm,bcm11404-srab',\n'brcm,bcm11407-srab', 'brcm,bcm11409-srab', 'brcm,bcm58310-srab',\n'brcm,bcm58311-srab', 'brcm,bcm58313-srab']\n        'brcm,bcm5301x-srab' is not one of ['brcm,bcm58522-srab',\n'brcm,bcm58523-srab', 'brcm,bcm58525-srab', 'brcm,bcm58622-srab',\n'brcm,bcm58623-srab', 'brcm,bcm58625-srab', 'brcm,bcm88312-srab']\n        'brcm,bcm5301x-srab' is not one of ['brcm,bcm3384-switch',\n'brcm,bcm6328-switch', 'brcm,bcm6368-switch']\n        From schema:\nDocumentation/devicetree/bindings/net/dsa/b53.yaml\n\nAcked-by: Rafał Miłecki <rafal@milecki.pl>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n arch/arm/boot/dts/bcm4709.dtsi  | 4 ++++\n arch/arm/boot/dts/bcm47094.dtsi | 4 ++++\n arch/arm/boot/dts/bcm5301x.dtsi | 2 +-\n 3 files changed, 9 insertions(+), 1 deletion(-)\n\n--- a/arch/arm/boot/dts/bcm4709.dtsi\n+++ b/arch/arm/boot/dts/bcm4709.dtsi\n@@ -9,3 +9,7 @@\n \tclock-frequency = <125000000>;\n \tstatus = \"okay\";\n };\n+\n+&srab {\n+\tcompatible = \"brcm,bcm53012-srab\", \"brcm,bcm5301x-srab\";\n+};\n--- a/arch/arm/boot/dts/bcm47094.dtsi\n+++ b/arch/arm/boot/dts/bcm47094.dtsi\n@@ -25,3 +25,7 @@\n \tclock-frequency = <125000000>;\n \tstatus = \"okay\";\n };\n+\n+&srab {\n+\tcompatible = \"brcm,bcm53012-srab\", \"brcm,bcm5301x-srab\";\n+};\n--- a/arch/arm/boot/dts/bcm5301x.dtsi\n+++ b/arch/arm/boot/dts/bcm5301x.dtsi\n@@ -486,7 +486,7 @@\n \t};\n \n \tsrab: ethernet-switch@18007000 {\n-\t\tcompatible = \"brcm,bcm5301x-srab\";\n+\t\tcompatible = \"brcm,bcm53011-srab\", \"brcm,bcm5301x-srab\";\n \t\treg = <0x18007000 0x1000>;\n \n \t\tstatus = \"disabled\";\n"
  },
  {
    "path": "target/linux/bcm53xx/patches-5.10/030-v5.11-0012-ARM-dts-BCM5301X-Provide-defaults-ports-container-no.patch",
    "content": "From fd577b41421bc24e2d04cab96d387301b649eb14 Mon Sep 17 00:00:00 2001\nFrom: Florian Fainelli <f.fainelli@gmail.com>\nDate: Mon, 9 Nov 2020 17:20:17 -0800\nSubject: [PATCH] ARM: dts: BCM5301X: Provide defaults ports container node\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nProvide an empty 'ports' container node with the correct #address-cells\nand #size-cells properties. This silences the following warning:\n\narch/arm/boot/dts/bcm4708-asus-rt-ac56u.dt.yaml:\nethernet-switch@18007000: 'oneOf' conditional failed, one must be fixed:\n        'ports' is a required property\n        'ethernet-ports' is a required property\n        From schema:\nDocumentation/devicetree/bindings/net/dsa/b53.yaml\n\nAcked-by: Rafał Miłecki <rafal@milecki.pl>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts     | 3 ---\n arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts     | 3 ---\n arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts    | 3 ---\n arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts    | 3 ---\n arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts    | 3 ---\n arch/arm/boot/dts/bcm47094-linksys-panamera.dts  | 3 ---\n arch/arm/boot/dts/bcm47094-luxul-xap-1610.dts    | 3 ---\n arch/arm/boot/dts/bcm47094-luxul-xwc-2000.dts    | 3 ---\n arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts    | 3 ---\n arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts | 3 ---\n arch/arm/boot/dts/bcm5301x.dtsi                  | 4 ++++\n arch/arm/boot/dts/bcm953012er.dts                | 3 ---\n 12 files changed, 4 insertions(+), 33 deletions(-)\n\n--- a/arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts\n+++ b/arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts\n@@ -61,9 +61,6 @@\n \tstatus = \"okay\";\n \n \tports {\n-\t\t#address-cells = <1>;\n-\t\t#size-cells = <0>;\n-\n \t\tport@0 {\n \t\t\treg = <0>;\n \t\t\tlabel = \"poe\";\n--- a/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts\n+++ b/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts\n@@ -68,9 +68,6 @@\n \tstatus = \"okay\";\n \n \tports {\n-\t\t#address-cells = <1>;\n-\t\t#size-cells = <0>;\n-\n \t\tport@4 {\n \t\t\treg = <4>;\n \t\t\tlabel = \"lan\";\n--- a/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts\n+++ b/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts\n@@ -122,9 +122,6 @@\n \tstatus = \"okay\";\n \n \tports {\n-\t\t#address-cells = <1>;\n-\t\t#size-cells = <0>;\n-\n \t\tport@0 {\n \t\t\treg = <0>;\n \t\t\tlabel = \"lan4\";\n--- a/arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts\n+++ b/arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts\n@@ -61,9 +61,6 @@\n \tstatus = \"okay\";\n \n \tports {\n-\t\t#address-cells = <1>;\n-\t\t#size-cells = <0>;\n-\n \t\tport@4 {\n \t\t\treg = <4>;\n \t\t\tlabel = \"poe\";\n--- a/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts\n+++ b/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts\n@@ -109,9 +109,6 @@\n \tstatus = \"okay\";\n \n \tports {\n-\t\t#address-cells = <1>;\n-\t\t#size-cells = <0>;\n-\n \t\tport@0 {\n \t\t\treg = <0>;\n \t\t\tlabel = \"lan4\";\n--- a/arch/arm/boot/dts/bcm47094-linksys-panamera.dts\n+++ b/arch/arm/boot/dts/bcm47094-linksys-panamera.dts\n@@ -201,9 +201,6 @@\n \tdsa,member = <0 0>;\n \n \tports {\n-\t\t#address-cells = <1>;\n-\t\t#size-cells = <0>;\n-\n \t\tport@1 {\n \t\t\treg = <1>;\n \t\t\tlabel = \"lan7\";\n--- a/arch/arm/boot/dts/bcm47094-luxul-xap-1610.dts\n+++ b/arch/arm/boot/dts/bcm47094-luxul-xap-1610.dts\n@@ -59,9 +59,6 @@\n \tstatus = \"okay\";\n \n \tports {\n-\t\t#address-cells = <1>;\n-\t\t#size-cells = <0>;\n-\n \t\tport@0 {\n \t\t\treg = <0>;\n \t\t\tlabel = \"poe\";\n--- a/arch/arm/boot/dts/bcm47094-luxul-xwc-2000.dts\n+++ b/arch/arm/boot/dts/bcm47094-luxul-xwc-2000.dts\n@@ -57,9 +57,6 @@\n \tstatus = \"okay\";\n \n \tports {\n-\t\t#address-cells = <1>;\n-\t\t#size-cells = <0>;\n-\n \t\tport@0 {\n \t\t\treg = <0>;\n \t\t\tlabel = \"lan\";\n--- a/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts\n+++ b/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts\n@@ -108,9 +108,6 @@\n \tstatus = \"okay\";\n \n \tports {\n-\t\t#address-cells = <1>;\n-\t\t#size-cells = <0>;\n-\n \t\tport@0 {\n \t\t\treg = <0>;\n \t\t\tlabel = \"lan4\";\n--- a/arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts\n+++ b/arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts\n@@ -83,9 +83,6 @@\n \tstatus = \"okay\";\n \n \tports {\n-\t\t#address-cells = <1>;\n-\t\t#size-cells = <0>;\n-\n \t\tport@0 {\n \t\t\treg = <0>;\n \t\t\tlabel = \"lan4\";\n--- a/arch/arm/boot/dts/bcm5301x.dtsi\n+++ b/arch/arm/boot/dts/bcm5301x.dtsi\n@@ -492,6 +492,10 @@\n \t\tstatus = \"disabled\";\n \n \t\t/* ports are defined in board DTS */\n+\t\tports {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t};\n \t};\n \n \trng: rng@18004000 {\n--- a/arch/arm/boot/dts/bcm953012er.dts\n+++ b/arch/arm/boot/dts/bcm953012er.dts\n@@ -69,9 +69,6 @@\n \tstatus = \"okay\";\n \n \tports {\n-\t\t#address-cells = <1>;\n-\t\t#size-cells = <0>;\n-\n \t\tport@0 {\n \t\t\treg = <0>;\n \t\t\tlabel = \"port0\";\n"
  },
  {
    "path": "target/linux/bcm53xx/patches-5.10/030-v5.11-0013-ARM-dts-NSP-Update-ethernet-switch-node-name.patch",
    "content": "From fd66cd0d79cb836badecb91fdd19afd32afbb443 Mon Sep 17 00:00:00 2001\nFrom: Florian Fainelli <f.fainelli@gmail.com>\nDate: Mon, 9 Nov 2020 12:02:08 -0800\nSubject: [PATCH 13/16] ARM: dts: NSP: Update ethernet switch node name\n\nUpdate the switch unit name from srab to ethernet-switch, allowing us\nto fix warnings such as:\n\n     CHECK   arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dt.yaml\n    arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dt.yaml:\n    srab@18007000: $nodename:0: 'srab@18007000' does not match\n    '^(ethernet-)?switch(@.*)?$'\n            From schema:\n    Documentation/devicetree/bindings/net/dsa/b53.yaml\n\nReviewed-by: Vladimir Oltean <olteanv@gmail.com>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n arch/arm/boot/dts/bcm-nsp.dtsi | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/arch/arm/boot/dts/bcm-nsp.dtsi\n+++ b/arch/arm/boot/dts/bcm-nsp.dtsi\n@@ -385,7 +385,7 @@\n \t\t\tclock-names = \"apb_pclk\";\n \t\t};\n \n-\t\tsrab: srab@36000 {\n+\t\tsrab: ethernet-switch@36000 {\n \t\t\tcompatible = \"brcm,nsp-srab\";\n \t\t\treg = <0x36000 0x1000>,\n \t\t\t      <0x3f308 0x8>,\n"
  },
  {
    "path": "target/linux/bcm53xx/patches-5.10/030-v5.11-0014-ARM-dts-NSP-Fix-Ethernet-switch-SGMII-register-name.patch",
    "content": "From 8b0235d1deace8f1bd8cdd149d698fee3974fdf4 Mon Sep 17 00:00:00 2001\nFrom: Florian Fainelli <f.fainelli@gmail.com>\nDate: Mon, 9 Nov 2020 12:06:15 -0800\nSubject: [PATCH 14/16] ARM: dts: NSP: Fix Ethernet switch SGMII register name\n\nThe register name should be \"sgmii_config\", not \"sgmii\", this is not a\nfunctional change since no code is currently looking for that register\nby name (or at all).\n\nReviewed-by: Vladimir Oltean <olteanv@gmail.com>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n arch/arm/boot/dts/bcm-nsp.dtsi | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/arch/arm/boot/dts/bcm-nsp.dtsi\n+++ b/arch/arm/boot/dts/bcm-nsp.dtsi\n@@ -390,7 +390,7 @@\n \t\t\treg = <0x36000 0x1000>,\n \t\t\t      <0x3f308 0x8>,\n \t\t\t      <0x3f410 0xc>;\n-\t\t\treg-names = \"srab\", \"mux_config\", \"sgmii\";\n+\t\t\treg-names = \"srab\", \"mux_config\", \"sgmii_config\";\n \t\t\tinterrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,\n \t\t\t\t     <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,\n \t\t\t\t     <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,\n"
  },
  {
    "path": "target/linux/bcm53xx/patches-5.10/030-v5.11-0015-ARM-dts-NSP-Add-a-SRAB-compatible-string-for-each-bo.patch",
    "content": "From 42791b317db4cda36751f57bada27857849811d3 Mon Sep 17 00:00:00 2001\nFrom: Florian Fainelli <f.fainelli@gmail.com>\nDate: Mon, 9 Nov 2020 17:41:32 -0800\nSubject: [PATCH 15/16] ARM: dts: NSP: Add a SRAB compatible string for each\n board\n\nProvide a valid compatible string for the Ethernet switch node based on\nthe board including the switch. This allows us to have sane defaults and\nsilences the following warnings:\n\n arch/arm/boot/dts/bcm958522er.dt.yaml:\n    ethernet-switch@36000: compatible: 'oneOf' conditional failed,\none\n    must be fixed:\n            ['brcm,bcm5301x-srab'] is too short\n            'brcm,bcm5325' was expected\n            'brcm,bcm53115' was expected\n            'brcm,bcm53125' was expected\n            'brcm,bcm53128' was expected\n            'brcm,bcm5365' was expected\n            'brcm,bcm5395' was expected\n            'brcm,bcm5389' was expected\n            'brcm,bcm5397' was expected\n            'brcm,bcm5398' was expected\n            'brcm,bcm11360-srab' was expected\n            'brcm,bcm5301x-srab' is not one of ['brcm,bcm53010-srab',\n    'brcm,bcm53011-srab', 'brcm,bcm53012-srab', 'brcm,bcm53018-srab',\n    'brcm,bcm53019-srab']\n            'brcm,bcm5301x-srab' is not one of ['brcm,bcm11404-srab',\n    'brcm,bcm11407-srab', 'brcm,bcm11409-srab', 'brcm,bcm58310-srab',\n    'brcm,bcm58311-srab', 'brcm,bcm58313-srab']\n            'brcm,bcm5301x-srab' is not one of ['brcm,bcm58522-srab',\n    'brcm,bcm58523-srab', 'brcm,bcm58525-srab', 'brcm,bcm58622-srab',\n    'brcm,bcm58623-srab', 'brcm,bcm58625-srab', 'brcm,bcm88312-srab']\n            'brcm,bcm5301x-srab' is not one of ['brcm,bcm3384-switch',\n    'brcm,bcm6328-switch', 'brcm,bcm6368-switch']\n            From schema:\n    Documentation/devicetree/bindings/net/dsa/b53.yaml\n\nReviewed-by: Vladimir Oltean <olteanv@gmail.com>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n arch/arm/boot/dts/bcm958522er.dts  | 4 ++++\n arch/arm/boot/dts/bcm958525er.dts  | 4 ++++\n arch/arm/boot/dts/bcm958525xmc.dts | 4 ++++\n 3 files changed, 12 insertions(+)\n\n--- a/arch/arm/boot/dts/bcm958522er.dts\n+++ b/arch/arm/boot/dts/bcm958522er.dts\n@@ -178,3 +178,7 @@\n &xhci {\n \tstatus = \"okay\";\n };\n+\n+&srab {\n+\tcompatible = \"brcm,bcm58522-srab\", \"brcm,nsp-srab\";\n+};\n--- a/arch/arm/boot/dts/bcm958525er.dts\n+++ b/arch/arm/boot/dts/bcm958525er.dts\n@@ -190,3 +190,7 @@\n &xhci {\n \tstatus = \"okay\";\n };\n+\n+&srab {\n+\tcompatible = \"brcm,bcm58525-srab\", \"brcm,nsp-srab\";\n+};\n--- a/arch/arm/boot/dts/bcm958525xmc.dts\n+++ b/arch/arm/boot/dts/bcm958525xmc.dts\n@@ -210,3 +210,7 @@\n &xhci {\n \tstatus = \"okay\";\n };\n+\n+&srab {\n+\tcompatible = \"brcm,bcm58525-srab\", \"brcm,nsp-srab\";\n+};\n"
  },
  {
    "path": "target/linux/bcm53xx/patches-5.10/030-v5.11-0016-ARM-dts-NSP-Provide-defaults-ports-container-node.patch",
    "content": "From 51e40c25aa18d926a8eb1c07289d01611b21123a Mon Sep 17 00:00:00 2001\nFrom: Florian Fainelli <f.fainelli@gmail.com>\nDate: Mon, 9 Nov 2020 17:44:33 -0800\nSubject: [PATCH 16/16] ARM: dts: NSP: Provide defaults ports container node\n\nProvide an empty 'ports' container node with the correct #address-cells\nand #size-cells properties. This silences the following warning:\n\narch/arm/boot/dts/bcm958522er.dt.yaml:\nethernet-switch@36000: 'oneOf' conditional failed, one must be fixed:\n            'ports' is a required property\n            'ethernet-ports' is a required property\n            From schema:\nDocumentation/devicetree/bindings/net/dsa/b53.yaml\n\nReviewed-by: Vladimir Oltean <olteanv@gmail.com>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n arch/arm/boot/dts/bcm-nsp.dtsi    | 4 ++++\n arch/arm/boot/dts/bcm958622hr.dts | 3 ---\n arch/arm/boot/dts/bcm958623hr.dts | 3 ---\n arch/arm/boot/dts/bcm958625hr.dts | 3 ---\n arch/arm/boot/dts/bcm958625k.dts  | 3 ---\n arch/arm/boot/dts/bcm988312hr.dts | 3 ---\n 6 files changed, 4 insertions(+), 15 deletions(-)\n\n--- a/arch/arm/boot/dts/bcm-nsp.dtsi\n+++ b/arch/arm/boot/dts/bcm-nsp.dtsi\n@@ -420,6 +420,10 @@\n \t\t\tstatus = \"disabled\";\n \n \t\t\t/* ports are defined in board DTS */\n+\t\t\tports {\n+\t\t\t\t#address-cells = <1>;\n+\t\t\t\t#size-cells = <0>;\n+\t\t\t};\n \t\t};\n \n \t\ti2c0: i2c@38000 {\n--- a/arch/arm/boot/dts/bcm958622hr.dts\n+++ b/arch/arm/boot/dts/bcm958622hr.dts\n@@ -176,9 +176,6 @@\n \tstatus = \"okay\";\n \n \tports {\n-\t\t#address-cells = <1>;\n-\t\t#size-cells = <0>;\n-\n \t\tport@0 {\n \t\t\tlabel = \"port0\";\n \t\t\treg = <0>;\n--- a/arch/arm/boot/dts/bcm958623hr.dts\n+++ b/arch/arm/boot/dts/bcm958623hr.dts\n@@ -180,9 +180,6 @@\n \tstatus = \"okay\";\n \n \tports {\n-\t\t#address-cells = <1>;\n-\t\t#size-cells = <0>;\n-\n \t\tport@0 {\n \t\t\tlabel = \"port0\";\n \t\t\treg = <0>;\n--- a/arch/arm/boot/dts/bcm958625hr.dts\n+++ b/arch/arm/boot/dts/bcm958625hr.dts\n@@ -195,9 +195,6 @@\n \tstatus = \"okay\";\n \n \tports {\n-\t\t#address-cells = <1>;\n-\t\t#size-cells = <0>;\n-\n \t\tport@0 {\n \t\t\tlabel = \"port0\";\n \t\t\treg = <0>;\n--- a/arch/arm/boot/dts/bcm958625k.dts\n+++ b/arch/arm/boot/dts/bcm958625k.dts\n@@ -216,9 +216,6 @@\n \tstatus = \"okay\";\n \n \tports {\n-\t\t#address-cells = <1>;\n-\t\t#size-cells = <0>;\n-\n \t\tport@0 {\n \t\t\tlabel = \"port0\";\n \t\t\treg = <0>;\n--- a/arch/arm/boot/dts/bcm988312hr.dts\n+++ b/arch/arm/boot/dts/bcm988312hr.dts\n@@ -184,9 +184,6 @@\n \tstatus = \"okay\";\n \n \tports {\n-\t\t#address-cells = <1>;\n-\t\t#size-cells = <0>;\n-\n \t\tport@0 {\n \t\t\tlabel = \"port0\";\n \t\t\treg = <0>;\n"
  },
  {
    "path": "target/linux/bcm53xx/patches-5.10/031-v5.13-0002-ARM-dts-BCM5301X-Describe-NVMEM-NVRAM-on-Linksys-Lux.patch",
    "content": "From 428ac8df021dd1cbcc693eb76636873d42327e5d Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Wed, 10 Mar 2021 22:04:46 +0100\nSubject: [PATCH] ARM: dts: BCM5301X: Describe NVMEM NVRAM on Linksys & Luxul\n routers\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nProvide access to NVRAM which contains device environment variables.\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n arch/arm/boot/dts/bcm4708-linksys-ea6300-v1.dts  | 5 +++++\n arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts    | 5 +++++\n arch/arm/boot/dts/bcm4709-linksys-ea9200.dts     | 5 +++++\n arch/arm/boot/dts/bcm47094-linksys-panamera.dts  | 5 +++++\n arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts    | 5 +++++\n arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts    | 5 +++++\n arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts    | 5 +++++\n arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts | 5 +++++\n 8 files changed, 40 insertions(+)\n\n--- a/arch/arm/boot/dts/bcm4708-linksys-ea6300-v1.dts\n+++ b/arch/arm/boot/dts/bcm4708-linksys-ea6300-v1.dts\n@@ -21,6 +21,11 @@\n \t\treg = <0x00000000 0x08000000>;\n \t};\n \n+\tnvram@1c080000 {\n+\t\tcompatible = \"brcm,nvram\";\n+\t\treg = <0x1c080000 0x180000>;\n+\t};\n+\n \tgpio-keys {\n \t\tcompatible = \"gpio-keys\";\n \n--- a/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts\n+++ b/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts\n@@ -21,6 +21,11 @@\n \t\treg = <0x00000000 0x08000000>;\n \t};\n \n+\tnvram@1eff0000 {\n+\t\tcompatible = \"brcm,nvram\";\n+\t\treg = <0x1eff0000 0x10000>;\n+\t};\n+\n \tleds {\n \t\tcompatible = \"gpio-leds\";\n \n--- a/arch/arm/boot/dts/bcm4709-linksys-ea9200.dts\n+++ b/arch/arm/boot/dts/bcm4709-linksys-ea9200.dts\n@@ -22,6 +22,11 @@\n \t\t      <0x88000000 0x08000000>;\n \t};\n \n+\tnvram@1c080000 {\n+\t\tcompatible = \"brcm,nvram\";\n+\t\treg = <0x1c080000 0x180000>;\n+\t};\n+\n \tgpio-keys {\n \t\tcompatible = \"gpio-keys\";\n \t\t#address-cells = <1>;\n--- a/arch/arm/boot/dts/bcm47094-linksys-panamera.dts\n+++ b/arch/arm/boot/dts/bcm47094-linksys-panamera.dts\n@@ -22,6 +22,11 @@\n \t\t      <0x88000000 0x08000000>;\n \t};\n \n+\tnvram@1c080000 {\n+\t\tcompatible = \"brcm,nvram\";\n+\t\treg = <0x1c080000 0x100000>;\n+\t};\n+\n \tgpio-keys {\n \t\tcompatible = \"gpio-keys\";\n \n--- a/arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts\n+++ b/arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts\n@@ -22,6 +22,11 @@\n \t\t      <0x88000000 0x18000000>;\n \t};\n \n+\tnvram@1eff0000 {\n+\t\tcompatible = \"brcm,nvram\";\n+\t\treg = <0x1eff0000 0x10000>;\n+\t};\n+\n \tleds {\n \t\tcompatible = \"gpio-leds\";\n \n--- a/arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts\n+++ b/arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts\n@@ -22,6 +22,11 @@\n \t\t      <0x88000000 0x18000000>;\n \t};\n \n+\tnvram@1eff0000 {\n+\t\tcompatible = \"brcm,nvram\";\n+\t\treg = <0x1eff0000 0x10000>;\n+\t};\n+\n \tleds {\n \t\tcompatible = \"gpio-leds\";\n \n--- a/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts\n+++ b/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts\n@@ -22,6 +22,11 @@\n \t\t      <0x88000000 0x08000000>;\n \t};\n \n+\tnvram@1eff0000 {\n+\t\tcompatible = \"brcm,nvram\";\n+\t\treg = <0x1eff0000 0x10000>;\n+\t};\n+\n \tleds {\n \t\tcompatible = \"gpio-leds\";\n \n--- a/arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts\n+++ b/arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts\n@@ -22,6 +22,11 @@\n \t\t      <0x88000000 0x18000000>;\n \t};\n \n+\tnvram@1eff0000 {\n+\t\tcompatible = \"brcm,nvram\";\n+\t\treg = <0x1eff0000 0x10000>;\n+\t};\n+\n \tleds {\n \t\tcompatible = \"gpio-leds\";\n \n"
  },
  {
    "path": "target/linux/bcm53xx/patches-5.10/031-v5.13-0003-ARM-dts-BCM5301X-Fix-Linksys-EA9500-partitions.patch",
    "content": "From 1d3352aeed164ef73f05cf80ca001f11d2f3312d Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Mon, 29 Mar 2021 07:54:30 +0200\nSubject: [PATCH] ARM: dts: BCM5301X: Fix Linksys EA9500 partitions\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nPartitions are basically fixed indeed but firmware ones don't have\nhardcoded function (\"firmware\" vs \"failsafe\"). Actual function depends\non bootloader configuration. Use a proper binding for that.\n\nWhile at it fix numbers formatting to avoid:\narch/arm/boot/dts/bcm47094-linksys-panamera.dt.yaml: partitions: 'partition@1F00000' does not match any of the regexes: '^partition@[0-9a-f]+$', 'pinctrl-[0-9]+'\n        From schema: Documentation/devicetree/bindings/mtd/partitions/linksys,ns-partitions.yaml\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n arch/arm/boot/dts/bcm47094-linksys-panamera.dts | 16 +++++++---------\n 1 file changed, 7 insertions(+), 9 deletions(-)\n\n--- a/arch/arm/boot/dts/bcm47094-linksys-panamera.dts\n+++ b/arch/arm/boot/dts/bcm47094-linksys-panamera.dts\n@@ -279,7 +279,7 @@\n \n &nandcs {\n \tpartitions {\n-\t\tcompatible = \"fixed-partitions\";\n+\t\tcompatible = \"linksys,ns-partitions\";\n \t\t#address-cells = <1>;\n \t\t#size-cells = <1>;\n \n@@ -300,20 +300,18 @@\n \t\t};\n \n \t\tpartition@200000 {\n-\t\t\tlabel = \"firmware\";\n-\t\t\treg = <0x0200000 0x01D00000>;\n-\t\t\tcompatible = \"brcm,trx\";\n+\t\t\treg = <0x0200000 0x01d00000>;\n+\t\t\tcompatible = \"linksys,ns-firmware\", \"brcm,trx\";\n \t\t};\n \n-\t\tpartition@1F00000 {\n-\t\t\tlabel = \"failsafe\";\n-\t\t\treg = <0x01F00000 0x01D00000>;\n-\t\t\tread-only;\n+\t\tpartition@1f00000 {\n+\t\t\treg = <0x01f00000 0x01d00000>;\n+\t\t\tcompatible = \"linksys,ns-firmware\", \"brcm,trx\";\n \t\t};\n \n \t\tpartition@5200000 {\n \t\t\tlabel = \"system\";\n-\t\t\treg = <0x05200000 0x02E00000>;\n+\t\t\treg = <0x05200000 0x02e00000>;\n \t\t};\n \t};\n };\n"
  },
  {
    "path": "target/linux/bcm53xx/patches-5.10/031-v5.13-0004-ARM-dts-BCM5301X-Set-Linksys-EA9500-power-LED.patch",
    "content": "From dcb56d61d5a8acca0a357cc603397bc0272ce4cb Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Mon, 29 Mar 2021 10:04:09 +0200\nSubject: [PATCH] ARM: dts: BCM5301X: Set Linksys EA9500 power LED\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nSet Linux default trigger to default on, just like it's normally done\nfor power LEDs.\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n arch/arm/boot/dts/bcm47094-linksys-panamera.dts | 1 +\n 1 file changed, 1 insertion(+)\n\n--- a/arch/arm/boot/dts/bcm47094-linksys-panamera.dts\n+++ b/arch/arm/boot/dts/bcm47094-linksys-panamera.dts\n@@ -75,6 +75,7 @@\n \t\tpower {\n \t\t\tlabel = \"bcm53xx:white:power\";\n \t\t\tgpios = <&chipcommon 4 GPIO_ACTIVE_HIGH>;\n+\t\t\tlinux,default-trigger = \"default-on\";\n \t\t};\n \n \t\twifi-disabled {\n"
  },
  {
    "path": "target/linux/bcm53xx/patches-5.10/032-v5.14-0001-ARM-dts-BCM5301X-Fix-NAND-nodes-names.patch",
    "content": "From b660269cba748dfd07eb5551a88ff34d5ea0b86e Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Fri, 16 Apr 2021 15:37:48 +0200\nSubject: [PATCH] ARM: dts: BCM5301X: Fix NAND nodes names\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nThis matches nand-controller.yaml requirements.\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n\n--- a/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts\n+++ b/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts\n@@ -24,8 +24,8 @@\n \t\treg = <0x00000000 0x08000000>;\n \t};\n \n-\tnand: nand@18028000 {\n-\t\tnandcs@0 {\n+\tnand_controller: nand-controller@18028000 {\n+\t\tnand@0 {\n \t\t\tpartitions {\n \t\t\t\tcompatible = \"fixed-partitions\";\n \t\t\t\t#address-cells = <1>;\n--- a/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts\n+++ b/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts\n@@ -25,8 +25,8 @@\n \t\t      <0x88000000 0x08000000>;\n \t};\n \n-\tnand: nand@18028000 {\n-\t\tnandcs@0 {\n+\tnand_controller: nand-controller@18028000 {\n+\t\tnand@0 {\n \t\t\tpartitions {\n \t\t\t\tcompatible = \"fixed-partitions\";\n \t\t\t\t#address-cells = <1>;\n--- a/arch/arm/boot/dts/bcm5301x-nand-cs0.dtsi\n+++ b/arch/arm/boot/dts/bcm5301x-nand-cs0.dtsi\n@@ -6,8 +6,8 @@\n  */\n \n / {\n-\tnand@18028000 {\n-\t\tnandcs: nandcs@0 {\n+\tnand-controller@18028000 {\n+\t\tnandcs: nand@0 {\n \t\t\tcompatible = \"brcm,nandcs\";\n \t\t\treg = <0>;\n \t\t\t#address-cells = <1>;\n--- a/arch/arm/boot/dts/bcm5301x.dtsi\n+++ b/arch/arm/boot/dts/bcm5301x.dtsi\n@@ -503,7 +503,7 @@\n \t\treg = <0x18004000 0x14>;\n \t};\n \n-\tnand: nand@18028000 {\n+\tnand_controller: nand-controller@18028000 {\n \t\tcompatible = \"brcm,nand-iproc\", \"brcm,brcmnand-v6.1\", \"brcm,brcmnand\";\n \t\treg = <0x18028000 0x600>, <0x1811a408 0x600>, <0x18028f00 0x20>;\n \t\treg-names = \"nand\", \"iproc-idm\", \"iproc-ext\";\n--- a/arch/arm/boot/dts/bcm953012k.dts\n+++ b/arch/arm/boot/dts/bcm953012k.dts\n@@ -49,8 +49,8 @@\n \t};\n };\n \n-&nand {\n-\tnandcs@0 {\n+&nand_controller {\n+\tnand@0 {\n \t\tcompatible = \"brcm,nandcs\";\n \t\treg = <0>;\n \t\tnand-on-flash-bbt;\n"
  },
  {
    "path": "target/linux/bcm53xx/patches-5.10/032-v5.14-0002-ARM-dts-BCM5301X-Fix-pinmux-subnodes-names.patch",
    "content": "From bb95d7d440fefd104c593d9cb20da6d34a474e97 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Wed, 21 Apr 2021 11:00:06 +0200\nSubject: [PATCH] ARM: dts: BCM5301X: Fix pinmux subnodes names\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nThis matches pinmux-node.yaml requirements.\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n arch/arm/boot/dts/bcm47094.dtsi | 2 +-\n arch/arm/boot/dts/bcm5301x.dtsi | 6 +++---\n 2 files changed, 4 insertions(+), 4 deletions(-)\n\n--- a/arch/arm/boot/dts/bcm47094.dtsi\n+++ b/arch/arm/boot/dts/bcm47094.dtsi\n@@ -11,7 +11,7 @@\n &pinctrl {\n \tcompatible = \"brcm,bcm4709-pinmux\";\n \n-\tpinmux_mdio: mdio {\n+\tpinmux_mdio: mdio-pins {\n \t\tgroups = \"mdio_grp\";\n \t\tfunction = \"mdio\";\n \t};\n--- a/arch/arm/boot/dts/bcm5301x.dtsi\n+++ b/arch/arm/boot/dts/bcm5301x.dtsi\n@@ -460,18 +460,18 @@\n \t\t\t\t\tfunction = \"spi\";\n \t\t\t\t};\n \n-\t\t\t\tpinmux_i2c: i2c {\n+\t\t\t\tpinmux_i2c: i2c-pins {\n \t\t\t\t\tgroups = \"i2c_grp\";\n \t\t\t\t\tfunction = \"i2c\";\n \t\t\t\t};\n \n-\t\t\t\tpinmux_pwm: pwm {\n+\t\t\t\tpinmux_pwm: pwm-pins {\n \t\t\t\t\tgroups = \"pwm0_grp\", \"pwm1_grp\",\n \t\t\t\t\t\t \"pwm2_grp\", \"pwm3_grp\";\n \t\t\t\t\tfunction = \"pwm\";\n \t\t\t\t};\n \n-\t\t\t\tpinmux_uart1: uart1 {\n+\t\t\t\tpinmux_uart1: uart1-pins {\n \t\t\t\t\tgroups = \"uart1_grp\";\n \t\t\t\t\tfunction = \"uart1\";\n \t\t\t\t};\n"
  },
  {
    "path": "target/linux/bcm53xx/patches-5.10/033-v5.15-0001-ARM-dts-NSP-add-device-names-to-compatible.patch",
    "content": "From 465078bfdf5271601f098450ae2fc974865c59fd Mon Sep 17 00:00:00 2001\nFrom: Matthew Hagan <mnhagan88@gmail.com>\nDate: Thu, 10 Jun 2021 21:35:10 +0100\nSubject: [PATCH] ARM: dts: NSP: add device names to compatible\n\nCurrently only the SoC type and platform are specified for all NSP\ndevices. This patch adds the device names.\n\nSigned-off-by: Matthew Hagan <mnhagan88@gmail.com>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n arch/arm/boot/dts/bcm958522er.dts  | 2 +-\n arch/arm/boot/dts/bcm958525er.dts  | 2 +-\n arch/arm/boot/dts/bcm958525xmc.dts | 2 +-\n arch/arm/boot/dts/bcm958622hr.dts  | 2 +-\n arch/arm/boot/dts/bcm958625hr.dts  | 2 +-\n arch/arm/boot/dts/bcm958625k.dts   | 2 +-\n arch/arm/boot/dts/bcm988312hr.dts  | 2 +-\n 7 files changed, 7 insertions(+), 7 deletions(-)\n\n--- a/arch/arm/boot/dts/bcm958522er.dts\n+++ b/arch/arm/boot/dts/bcm958522er.dts\n@@ -37,7 +37,7 @@\n \n / {\n \tmodel = \"NorthStar Plus SVK (BCM958522ER)\";\n-\tcompatible = \"brcm,bcm58522\", \"brcm,nsp\";\n+\tcompatible = \"brcm,bcm958522er\", \"brcm,bcm58522\", \"brcm,nsp\";\n \n \tchosen {\n \t\tstdout-path = \"serial0:115200n8\";\n--- a/arch/arm/boot/dts/bcm958525er.dts\n+++ b/arch/arm/boot/dts/bcm958525er.dts\n@@ -37,7 +37,7 @@\n \n / {\n \tmodel = \"NorthStar Plus SVK (BCM958525ER)\";\n-\tcompatible = \"brcm,bcm58525\", \"brcm,nsp\";\n+\tcompatible = \"brcm,bcm958525er\", \"brcm,bcm58525\", \"brcm,nsp\";\n \n \tchosen {\n \t\tstdout-path = \"serial0:115200n8\";\n--- a/arch/arm/boot/dts/bcm958525xmc.dts\n+++ b/arch/arm/boot/dts/bcm958525xmc.dts\n@@ -37,7 +37,7 @@\n \n / {\n \tmodel = \"NorthStar Plus XMC (BCM958525xmc)\";\n-\tcompatible = \"brcm,bcm58525\", \"brcm,nsp\";\n+\tcompatible = \"brcm,bcm958525xmc\", \"brcm,bcm58525\", \"brcm,nsp\";\n \n \tchosen {\n \t\tstdout-path = \"serial0:115200n8\";\n--- a/arch/arm/boot/dts/bcm958622hr.dts\n+++ b/arch/arm/boot/dts/bcm958622hr.dts\n@@ -37,7 +37,7 @@\n \n / {\n \tmodel = \"NorthStar Plus SVK (BCM958622HR)\";\n-\tcompatible = \"brcm,bcm58622\", \"brcm,nsp\";\n+\tcompatible = \"brcm,bcm958622hr\", \"brcm,bcm58622\", \"brcm,nsp\";\n \n \tchosen {\n \t\tstdout-path = \"serial0:115200n8\";\n--- a/arch/arm/boot/dts/bcm958625hr.dts\n+++ b/arch/arm/boot/dts/bcm958625hr.dts\n@@ -37,7 +37,7 @@\n \n / {\n \tmodel = \"NorthStar Plus SVK (BCM958625HR)\";\n-\tcompatible = \"brcm,bcm58625\", \"brcm,nsp\";\n+\tcompatible = \"brcm,bcm958625hr\", \"brcm,bcm58625\", \"brcm,nsp\";\n \n \tchosen {\n \t\tstdout-path = \"serial0:115200n8\";\n--- a/arch/arm/boot/dts/bcm958625k.dts\n+++ b/arch/arm/boot/dts/bcm958625k.dts\n@@ -36,7 +36,7 @@\n \n / {\n \tmodel = \"NorthStar Plus SVK (BCM958625K)\";\n-\tcompatible = \"brcm,bcm58625\", \"brcm,nsp\";\n+\tcompatible = \"brcm,bcm958625k\", \"brcm,bcm58625\", \"brcm,nsp\";\n \n \tchosen {\n \t\tstdout-path = \"serial0:115200n8\";\n--- a/arch/arm/boot/dts/bcm988312hr.dts\n+++ b/arch/arm/boot/dts/bcm988312hr.dts\n@@ -37,7 +37,7 @@\n \n / {\n \tmodel = \"NorthStar Plus SVK (BCM988312HR)\";\n-\tcompatible = \"brcm,bcm88312\", \"brcm,nsp\";\n+\tcompatible = \"brcm,bcm988312hr\", \"brcm,bcm88312\", \"brcm,nsp\";\n \n \tchosen {\n \t\tstdout-path = \"serial0:115200n8\";\n"
  },
  {
    "path": "target/linux/bcm53xx/patches-5.10/033-v5.15-0002-ARM-dts-NSP-enable-DMA-on-bcm988312hr.patch",
    "content": "From 1b90dde4278a7b459979706b572785bc3a10bbb5 Mon Sep 17 00:00:00 2001\nFrom: Matthew Hagan <mnhagan88@gmail.com>\nDate: Thu, 10 Jun 2021 21:35:12 +0100\nSubject: [PATCH] ARM: dts: NSP: enable DMA on bcm988312hr\n\nThe previous patch \"ARM: dts: NSP: Disable PL330 by default, add\ndma-coherent property\" set the DMAC to disabled by default, requiring it\nto be manually enabled on each device. The bcm988312hr was mistakenly\nomitted. This patch adds it back.\n\nSigned-off-by: Matthew Hagan <mnhagan88@gmail.com>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n arch/arm/boot/dts/bcm988312hr.dts | 4 ++++\n 1 file changed, 4 insertions(+)\n\n--- a/arch/arm/boot/dts/bcm988312hr.dts\n+++ b/arch/arm/boot/dts/bcm988312hr.dts\n@@ -58,6 +58,10 @@\n \n /* USB 3 support needed to be complete */\n \n+&dma {\n+\tstatus = \"okay\";\n+};\n+\n &amac0 {\n \tstatus = \"okay\";\n };\n"
  },
  {
    "path": "target/linux/bcm53xx/patches-5.10/033-v5.15-0003-ARM-dts-NSP-disable-qspi-node-by-default.patch",
    "content": "From 091a12b1814142eac16a115dab206f735b5476a9 Mon Sep 17 00:00:00 2001\nFrom: Matthew Hagan <mnhagan88@gmail.com>\nDate: Sun, 13 Jun 2021 10:46:34 +0100\nSubject: [PATCH] ARM: dts: NSP: disable qspi node by default\n\nThe QSPI bus is enabled by default, however this may not used on all\ndevices. This patch disables by default, requiring it to be explicitly\nenabled where required.\n\nSigned-off-by: Matthew Hagan <mnhagan88@gmail.com>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n arch/arm/boot/dts/bcm-nsp.dtsi     | 1 +\n arch/arm/boot/dts/bcm958522er.dts  | 1 +\n arch/arm/boot/dts/bcm958525er.dts  | 1 +\n arch/arm/boot/dts/bcm958525xmc.dts | 1 +\n arch/arm/boot/dts/bcm958622hr.dts  | 1 +\n arch/arm/boot/dts/bcm958623hr.dts  | 1 +\n arch/arm/boot/dts/bcm958625hr.dts  | 1 +\n arch/arm/boot/dts/bcm958625k.dts   | 1 +\n arch/arm/boot/dts/bcm988312hr.dts  | 1 +\n 9 files changed, 9 insertions(+)\n\n--- a/arch/arm/boot/dts/bcm-nsp.dtsi\n+++ b/arch/arm/boot/dts/bcm-nsp.dtsi\n@@ -310,6 +310,7 @@\n \t\t\tnum-cs = <2>;\n \t\t\t#address-cells = <1>;\n \t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"disabled\";\n \t\t};\n \n \t\txhci: usb@29000 {\n--- a/arch/arm/boot/dts/bcm958522er.dts\n+++ b/arch/arm/boot/dts/bcm958522er.dts\n@@ -134,6 +134,7 @@\n };\n \n &qspi {\n+\tstatus = \"okay\";\n \tbspi-sel = <0>;\n \tflash: m25p80@0 {\n \t\t#address-cells = <1>;\n--- a/arch/arm/boot/dts/bcm958525er.dts\n+++ b/arch/arm/boot/dts/bcm958525er.dts\n@@ -134,6 +134,7 @@\n };\n \n &qspi {\n+\tstatus = \"okay\";\n \tbspi-sel = <0>;\n \tflash: m25p80@0 {\n \t\t#address-cells = <1>;\n--- a/arch/arm/boot/dts/bcm958525xmc.dts\n+++ b/arch/arm/boot/dts/bcm958525xmc.dts\n@@ -150,6 +150,7 @@\n };\n \n &qspi {\n+\tstatus = \"okay\";\n \tbspi-sel = <0>;\n \tflash: m25p80@0 {\n \t\t#address-cells = <1>;\n--- a/arch/arm/boot/dts/bcm958622hr.dts\n+++ b/arch/arm/boot/dts/bcm958622hr.dts\n@@ -138,6 +138,7 @@\n };\n \n &qspi {\n+\tstatus = \"okay\";\n \tbspi-sel = <0>;\n \tflash: m25p80@0 {\n \t\t#address-cells = <1>;\n--- a/arch/arm/boot/dts/bcm958623hr.dts\n+++ b/arch/arm/boot/dts/bcm958623hr.dts\n@@ -142,6 +142,7 @@\n };\n \n &qspi {\n+\tstatus = \"okay\";\n \tbspi-sel = <0>;\n \tflash: m25p80@0 {\n \t\t#address-cells = <1>;\n--- a/arch/arm/boot/dts/bcm958625hr.dts\n+++ b/arch/arm/boot/dts/bcm958625hr.dts\n@@ -149,6 +149,7 @@\n };\n \n &qspi {\n+\tstatus = \"okay\";\n \tbspi-sel = <0>;\n \tflash: m25p80@0 {\n \t\t#address-cells = <1>;\n--- a/arch/arm/boot/dts/bcm958625k.dts\n+++ b/arch/arm/boot/dts/bcm958625k.dts\n@@ -153,6 +153,7 @@\n };\n \n &qspi {\n+\tstatus = \"okay\";\n \tbspi-sel = <0>;\n \tflash: m25p80@0 {\n \t\t#address-cells = <1>;\n--- a/arch/arm/boot/dts/bcm988312hr.dts\n+++ b/arch/arm/boot/dts/bcm988312hr.dts\n@@ -138,6 +138,7 @@\n };\n \n &qspi {\n+\tstatus = \"okay\";\n \tbspi-sel = <0>;\n \tflash: m25p80@0 {\n \t\t#address-cells = <1>;\n"
  },
  {
    "path": "target/linux/bcm53xx/patches-5.10/033-v5.15-0004-ARM-dts-NSP-add-MDIO-bus-controller-node.patch",
    "content": "From 236b31b1d84eb0e4f10c5f113a2675529456f919 Mon Sep 17 00:00:00 2001\nFrom: Matthew Hagan <mnhagan88@gmail.com>\nDate: Sun, 13 Jun 2021 10:46:36 +0100\nSubject: [PATCH] ARM: dts: NSP: add MDIO bus controller node\n\nThis patch adds the node for the MDIO bus controller, present on the NSP\nSoC.\n\nSigned-off-by: Matthew Hagan <mnhagan88@gmail.com>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n arch/arm/boot/dts/bcm-nsp.dtsi | 7 +++++++\n 1 file changed, 7 insertions(+)\n\n--- a/arch/arm/boot/dts/bcm-nsp.dtsi\n+++ b/arch/arm/boot/dts/bcm-nsp.dtsi\n@@ -363,6 +363,13 @@\n \t\t\tstatus = \"disabled\";\n \t\t};\n \n+\t\tmdio: mdio@32000 {\n+\t\t\tcompatible = \"brcm,iproc-mdio\";\n+\t\t\treg = <0x32000 0x8>;\n+\t\t\t#size-cells = <0>;\n+\t\t\t#address-cells = <1>;\n+\t\t};\n+\n \t\trng: rng@33000 {\n \t\t\tcompatible = \"brcm,bcm-nsp-rng\";\n \t\t\treg = <0x33000 0x14>;\n"
  },
  {
    "path": "target/linux/bcm53xx/patches-5.10/033-v5.15-0005-ARM-dts-NSP-Move-USB3-PHY-to-internal-MDIO-bus.patch",
    "content": "From 1c615401bddb1be21e1d375aaa071680f40f1ae2 Mon Sep 17 00:00:00 2001\nFrom: Matthew Hagan <mnhagan88@gmail.com>\nDate: Sun, 13 Jun 2021 10:46:37 +0100\nSubject: [PATCH] ARM: dts: NSP: Move USB3 PHY to internal MDIO bus\n\nThis patch largely replicates Vivek Unune's patch \"ARM: dts:\nBCM5301X:Make usb3 phy use mdio phy driver\"[1] for the NSP platform,\nwhereby we need to create an mdio-mux to facilitate switches\nconfigured via external MDIO, in this case on the Meraki MX65.\n\nHowever in doing so, we are creating an overlap with usb3_phy's\nccb-mii range. To resolve this, usb3_phy should be moved to a child\nnode of the internal MDIO bus. The result is heavily based upon Vivek's\npatch. This has also been cross-referenced with Yendapally Reddy's\nearlier work which utilised the subsequently dropped brcm,nsp-usb3-phy\ndriver: \"[PATCH v2 4/4] arm: dts: nsp: Add USB nodes to device tree\"\n[2]. Finally, this change provides conformance to the bcm-ns-usb3-phy\ndocumentation, utilising the required usb3-dmp-syscon property. Note\nthat support for the deprecated ccb-mii bindings has been dropped as of\n\"phy: phy-bcm-ns-usb3: drop support for deprecated DT binding\"[3].\n\n[1] https://lore.kernel.org/patchwork/patch/933971/\n[2] https://www.spinics.net/lists/arm-kernel/msg555132.html\n[3] https://lore.kernel.org/linux-devicetree/20201113113423.9466-1-zajec5@gmail.com/\n\nSigned-off-by: Matthew Hagan <mnhagan88@gmail.com>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n arch/arm/boot/dts/bcm-nsp.dtsi | 38 +++++++++++++++++++++++++++-------\n 1 file changed, 31 insertions(+), 7 deletions(-)\n\n--- a/arch/arm/boot/dts/bcm-nsp.dtsi\n+++ b/arch/arm/boot/dts/bcm-nsp.dtsi\n@@ -370,6 +370,35 @@\n \t\t\t#address-cells = <1>;\n \t\t};\n \n+\t\tmdio-mux@32000 {\n+\t\t\tcompatible = \"mdio-mux-mmioreg\";\n+\t\t\treg = <0x32000 0x4>;\n+\t\t\tmux-mask = <0x200>;\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tmdio-parent-bus = <&mdio>;\n+\n+\t\t\tmdio_int: mdio@0 {\n+\t\t\t\treg = <0x0>;\n+\t\t\t\t#address-cells = <1>;\n+\t\t\t\t#size-cells = <0>;\n+\n+\t\t\t\tusb3_phy: usb3-phy@10 {\n+\t\t\t\t\tcompatible = \"brcm,ns-bx-usb3-phy\";\n+\t\t\t\t\treg = <0x10>;\n+\t\t\t\t\tusb3-dmp-syscon = <&usb3_dmp>;\n+\t\t\t\t\t#phy-cells = <0>;\n+\t\t\t\t\tstatus = \"disabled\";\n+\t\t\t\t};\n+\t\t\t};\n+\n+\t\t\tmdio_ext: mdio@200 {\n+\t\t\t\treg = <0x200>;\n+\t\t\t\t#address-cells = <1>;\n+\t\t\t\t#size-cells = <0>;\n+\t\t\t};\n+\t\t};\n+\n \t\trng: rng@33000 {\n \t\t\tcompatible = \"brcm,bcm-nsp-rng\";\n \t\t\treg = <0x33000 0x14>;\n@@ -528,13 +557,8 @@\n \t\t\t};\n \t\t};\n \n-\t\tusb3_phy: usb3-phy@104000 {\n-\t\t\tcompatible = \"brcm,ns-bx-usb3-phy\";\n-\t\t\treg = <0x104000 0x1000>,\n-\t\t\t      <0x032000 0x1000>;\n-\t\t\treg-names = \"dmp\", \"ccb-mii\";\n-\t\t\t#phy-cells = <0>;\n-\t\t\tstatus = \"disabled\";\n+\t\tusb3_dmp: syscon@104000 {\n+\t\t\treg = <0x104000 0x1000>;\n \t\t};\n \t};\n \n"
  },
  {
    "path": "target/linux/bcm53xx/patches-5.10/033-v5.15-0006-ARM-dts-NSP-Add-common-bindings-for-MX64-MX65.patch",
    "content": "From f111016a8293b968f05450fec83020c94d0f88c2 Mon Sep 17 00:00:00 2001\nFrom: Matthew Hagan <mnhagan88@gmail.com>\nDate: Fri, 6 Aug 2021 21:44:32 +0100\nSubject: [PATCH] ARM: dts: NSP: Add common bindings for MX64/MX65\n\nThese bindings are required for all Meraki MX64/MX65 devices. These\ncommon bindings include memory (2GB), PWM LEDs, AMAC, I2C (AT24), NAND\npartitions, EHCI, OHCI and pinctrl.\n\nSigned-off-by: Matthew Hagan <mnhagan88@gmail.com>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n .../dts/bcm958625-meraki-mx6x-common.dtsi     | 129 ++++++++++++++++++\n 1 file changed, 129 insertions(+)\n create mode 100644 arch/arm/boot/dts/bcm958625-meraki-mx6x-common.dtsi\n\n--- /dev/null\n+++ b/arch/arm/boot/dts/bcm958625-meraki-mx6x-common.dtsi\n@@ -0,0 +1,129 @@\n+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n+/*\n+ * Common Bindings for Cisco Meraki MX64 (Kingpin) and MX65 (Alamo) devices.\n+ *\n+ * Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com>\n+ */\n+\n+#include \"bcm-nsp.dtsi\"\n+#include <dt-bindings/gpio/gpio.h>\n+#include <dt-bindings/input/input.h>\n+#include <dt-bindings/leds/common.h>\n+\n+/ {\n+\tpwm-leds {\n+\t\tcompatible = \"pwm-leds\";\n+\n+\t\tled-1 {\n+\t\t\tfunction = LED_FUNCTION_INDICATOR;\n+\t\t\tcolor = <LED_COLOR_ID_RED>;\n+\t\t\tpwms = <&pwm 1 50000>;\n+\t\t\tmax-brightness = <255>;\n+\t\t};\n+\n+\t\tled-2 {\n+\t\t\tfunction = LED_FUNCTION_INDICATOR;\n+\t\t\tcolor = <LED_COLOR_ID_GREEN>;\n+\t\t\tpwms = <&pwm 2 50000>;\n+\t\t\tmax-brightness = <255>;\n+\t\t};\n+\n+\t\tled-3 {\n+\t\t\tfunction = LED_FUNCTION_INDICATOR;\n+\t\t\tcolor = <LED_COLOR_ID_BLUE>;\n+\t\t\tpwms = <&pwm 3 50000>;\n+\t\t\tmax-brightness = <255>;\n+\t\t};\n+\t};\n+};\n+\n+&amac2 {\n+\tstatus = \"okay\";\n+};\n+\n+&ehci0 {\n+\tstatus = \"okay\";\n+};\n+\n+&i2c0 {\n+\tstatus = \"okay\";\n+\n+\tat24@50 {\n+\t\tcompatible = \"atmel,24c64\";\n+\t\treg = <0x50>;\n+\t\tpagesize = <32>;\n+\t\tread-only;\n+\t};\n+};\n+\n+&nand_controller {\n+\tnand@0 {\n+\t\tcompatible = \"brcm,nandcs\";\n+\t\treg = <0>;\n+\t\tnand-on-flash-bbt;\n+\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <1>;\n+\n+\t\tnand-ecc-strength = <24>;\n+\t\tnand-ecc-step-size = <1024>;\n+\n+\t\tbrcm,nand-oob-sector-size = <27>;\n+\n+\t\tpartition@0 {\n+\t\t\tlabel = \"u-boot\";\n+\t\t\treg = <0x0 0x80000>;\n+\t\t\tread-only;\n+\t\t};\n+\n+\t\tpartition@80000 {\n+\t\t\tlabel = \"shmoo\";\n+\t\t\treg = <0x80000 0x80000>;\n+\t\t\tread-only;\n+\t\t};\n+\n+\t\tpartition@100000 {\n+\t\t\tlabel = \"bootkernel1\";\n+\t\t\treg = <0x100000 0x300000>;\n+\t\t};\n+\n+\t\tpartition@400000 {\n+\t\t\tlabel = \"nvram\";\n+\t\t\treg = <0x400000 0x100000>;\n+\t\t};\n+\n+\t\tpartition@500000 {\n+\t\t\tlabel = \"bootkernel2\";\n+\t\t\treg = <0x500000 0x300000>;\n+\t\t};\n+\n+\t\tpartition@800000 {\n+\t\t\tlabel = \"ubi\";\n+\t\t\treg = <0x800000 0x3f700000>;\n+\t\t};\n+\t};\n+};\n+\n+&ohci0 {\n+\tstatus = \"okay\";\n+};\n+\n+&pinctrl {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pwm_leds>;\n+\n+\tpwm_leds: pwm_leds {\n+\t\tfunction = \"pwm\";\n+\t\tgroups = \"pwm1_grp\", \"pwm2_grp\", \"pwm3_grp\";\n+\t};\n+};\n+\n+&pwm {\n+\tstatus = \"okay\";\n+\t#pwm-cells = <2>;\n+};\n+\n+&uart0 {\n+\tclock-frequency = <62500000>;\n+\tstatus = \"okay\";\n+};\n"
  },
  {
    "path": "target/linux/bcm53xx/patches-5.10/033-v5.15-0007-ARM-dts-NSP-Add-Ax-stepping-modifications.patch",
    "content": "From 2addf9266a1d0f4ba59c9868b3effcd50de441a4 Mon Sep 17 00:00:00 2001\nFrom: Matthew Hagan <mnhagan88@gmail.com>\nDate: Fri, 6 Aug 2021 21:44:33 +0100\nSubject: [PATCH] ARM: dts: NSP: Add Ax stepping modifications\n\nWhile uncommon, some Ax NSP SoCs exist in the wild. This stepping\nrequires a modified secondary CPU boot-reg and removal of DMA coherency\nproperties. Without these modifications, the secondary CPU will be\ninactive and many peripherals will exhibit undefined behaviour.\n\nSigned-off-by: Matthew Hagan <mnhagan88@gmail.com>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n arch/arm/boot/dts/bcm-nsp-ax.dtsi | 70 +++++++++++++++++++++++++++++++\n 1 file changed, 70 insertions(+)\n create mode 100644 arch/arm/boot/dts/bcm-nsp-ax.dtsi\n\n--- /dev/null\n+++ b/arch/arm/boot/dts/bcm-nsp-ax.dtsi\n@@ -0,0 +1,70 @@\n+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n+/*\n+ * Broadcom Northstar Plus Ax stepping-specific bindings.\n+ * Notable differences from B0+ are the secondary-boot-reg and\n+ * lack of DMA coherency.\n+ */\n+\n+&cpu1 {\n+\tsecondary-boot-reg = <0xffff042c>;\n+};\n+\n+&dma {\n+\t/delete-property/ dma-coherent;\n+};\n+\n+&sdio {\n+\t/delete-property/ dma-coherent;\n+};\n+\n+&amac0 {\n+\t/delete-property/ dma-coherent;\n+};\n+\n+&amac1 {\n+\t/delete-property/ dma-coherent;\n+};\n+\n+&amac2 {\n+\t/delete-property/ dma-coherent;\n+};\n+\n+&ehci0 {\n+\t/delete-property/ dma-coherent;\n+};\n+\n+&mailbox {\n+\t/delete-property/ dma-coherent;\n+};\n+\n+&xhci {\n+\t/delete-property/ dma-coherent;\n+};\n+\n+&ehci0 {\n+\t/delete-property/ dma-coherent;\n+};\n+\n+&ohci0 {\n+\t/delete-property/ dma-coherent;\n+};\n+\n+&i2c0 {\n+\t/delete-property/ dma-coherent;\n+};\n+\n+&sata {\n+\t/delete-property/ dma-coherent;\n+};\n+\n+&pcie0 {\n+\t/delete-property/ dma-coherent;\n+};\n+\n+&pcie1 {\n+\t/delete-property/ dma-coherent;\n+};\n+\n+&pcie2 {\n+\t/delete-property/ dma-coherent;\n+};\n"
  },
  {
    "path": "target/linux/bcm53xx/patches-5.10/033-v5.15-0008-ARM-dts-NSP-Add-DT-files-for-Meraki-MX64-series.patch",
    "content": "From 3f902645280baf0d7dab57c227cc14f43edb45ef Mon Sep 17 00:00:00 2001\nFrom: Matthew Hagan <mnhagan88@gmail.com>\nDate: Fri, 6 Aug 2021 21:44:34 +0100\nSubject: [PATCH] ARM: dts: NSP: Add DT files for Meraki MX64 series\n\nMX64 & MX64W Hardware info:\n  - CPU: Broadcom BCM58625 Cortex A9 @ 1200Mhz\n  - RAM: 2 GB (4 x 4Gb SK Hynix H5TC4G83CFR)\n  - Storage: 1 GB (Micron MT29F8G08ABACA)\n  - Networking: BCM58625 internal switch (5x 1GbE ports)\n  - USB: 1x USB2.0\n  - Serial: Internal header\n  - WLAN(MX64W only): 2x Broadcom BCM43520KMLG on the PCI bus\n\nThis patch adds the Meraki MX64 series-specific bindings. Since some\ndevices make use of the older A0 SoC, changes need to be made to\naccommodate this case, including removal of coherency options and\nmodification to the secondary-boot-reg.\n\nSigned-off-by: Matthew Hagan <mnhagan88@gmail.com>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n arch/arm/boot/dts/Makefile                    |   4 +\n .../boot/dts/bcm958625-meraki-kingpin.dtsi    | 163 ++++++++++++++++++\n .../arm/boot/dts/bcm958625-meraki-mx64-a0.dts |  25 +++\n arch/arm/boot/dts/bcm958625-meraki-mx64.dts   |  24 +++\n .../boot/dts/bcm958625-meraki-mx64w-a0.dts    |  33 ++++\n arch/arm/boot/dts/bcm958625-meraki-mx64w.dts  |  32 ++++\n 6 files changed, 281 insertions(+)\n create mode 100644 arch/arm/boot/dts/bcm958625-meraki-kingpin.dtsi\n create mode 100644 arch/arm/boot/dts/bcm958625-meraki-mx64-a0.dts\n create mode 100644 arch/arm/boot/dts/bcm958625-meraki-mx64.dts\n create mode 100644 arch/arm/boot/dts/bcm958625-meraki-mx64w-a0.dts\n create mode 100644 arch/arm/boot/dts/bcm958625-meraki-mx64w.dts\n\n--- a/arch/arm/boot/dts/Makefile\n+++ b/arch/arm/boot/dts/Makefile\n@@ -158,6 +158,10 @@ dtb-$(CONFIG_ARCH_BCM_NSP) += \\\n \tbcm958525xmc.dtb \\\n \tbcm958622hr.dtb \\\n \tbcm958623hr.dtb \\\n+\tbcm958625-meraki-mx64.dtb \\\n+\tbcm958625-meraki-mx64-a0.dtb \\\n+\tbcm958625-meraki-mx64w.dtb \\\n+\tbcm958625-meraki-mx64w-a0.dtb \\\n \tbcm958625hr.dtb \\\n \tbcm988312hr.dtb \\\n \tbcm958625k.dtb\n--- /dev/null\n+++ b/arch/arm/boot/dts/bcm958625-meraki-kingpin.dtsi\n@@ -0,0 +1,163 @@\n+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n+/*\n+ * Device Tree Bindings for Cisco Meraki MX64 series (Kingpin).\n+ *\n+ * Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com>\n+ */\n+\n+#include \"bcm958625-meraki-mx6x-common.dtsi\"\n+\n+/ {\n+\n+\tkeys {\n+\t\tcompatible = \"gpio-keys-polled\";\n+\t\tautorepeat;\n+\t\tpoll-interval = <20>;\n+\n+\t\treset {\n+\t\t\tlabel = \"reset\";\n+\t\t\tlinux,code = <KEY_RESTART>;\n+\t\t\tgpios = <&gpioa 6 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\t};\n+\n+\tleds {\n+\t\tcompatible = \"gpio-leds\";\n+\n+\t\tled-0 {\n+\t\t\t/* green:lan1-left */\n+\t\t\tfunction = LED_FUNCTION_ACTIVITY;\n+\t\t\tfunction-enumerator = <0>;\n+\t\t\tcolor = <LED_COLOR_ID_GREEN>;\n+\t\t\tgpios = <&gpioa 19 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\n+\t\tled-1 {\n+\t\t\t/* green:lan1-right */\n+\t\t\tfunction = LED_FUNCTION_ACTIVITY;\n+\t\t\tfunction-enumerator = <1>;\n+\t\t\tcolor = <LED_COLOR_ID_GREEN>;\n+\t\t\tgpios = <&gpioa 18 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\n+\t\tled-2 {\n+\t\t\t/* green:lan2-left */\n+\t\t\tfunction = LED_FUNCTION_ACTIVITY;\n+\t\t\tfunction-enumerator = <2>;\n+\t\t\tcolor = <LED_COLOR_ID_GREEN>;\n+\t\t\tgpios = <&gpioa 24 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\n+\t\tled-3 {\n+\t\t\t/* green:lan2-right */\n+\t\t\tfunction = LED_FUNCTION_ACTIVITY;\n+\t\t\tfunction-enumerator = <3>;\n+\t\t\tcolor = <LED_COLOR_ID_GREEN>;\n+\t\t\tgpios = <&gpioa 20 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\n+\t\tled-4 {\n+\t\t\t/* green:lan3-left */\n+\t\t\tfunction = LED_FUNCTION_ACTIVITY;\n+\t\t\tfunction-enumerator = <4>;\n+\t\t\tcolor = <LED_COLOR_ID_GREEN>;\n+\t\t\tgpios = <&gpioa 26 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\n+\t\tled-5 {\n+\t\t\t/* green:lan3-right */\n+\t\t\tfunction = LED_FUNCTION_ACTIVITY;\n+\t\t\tfunction-enumerator = <5>;\n+\t\t\tcolor = <LED_COLOR_ID_GREEN>;\n+\t\t\tgpios = <&gpioa 25 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\n+\t\tled-6 {\n+\t\t\t/* green:lan4-left */\n+\t\t\tfunction = LED_FUNCTION_ACTIVITY;\n+\t\t\tfunction-enumerator = <6>;\n+\t\t\tcolor = <LED_COLOR_ID_GREEN>;\n+\t\t\tgpios = <&gpioa 28 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\n+\t\tled-7 {\n+\t\t\t/* green:lan4-right */\n+\t\t\tfunction = LED_FUNCTION_ACTIVITY;\n+\t\t\tfunction-enumerator = <7>;\n+\t\t\tcolor = <LED_COLOR_ID_GREEN>;\n+\t\t\tgpios = <&gpioa 27 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\n+\t\tled-8 {\n+\t\t\t/* green:wan-left */\n+\t\t\tfunction = LED_FUNCTION_ACTIVITY;\n+\t\t\tfunction-enumerator = <8>;\n+\t\t\tcolor = <LED_COLOR_ID_GREEN>;\n+\t\t\tgpios = <&gpioa 30 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\n+\t\tled-9 {\n+\t\t\t/* green:wan-right */\n+\t\t\tfunction = LED_FUNCTION_ACTIVITY;\n+\t\t\tfunction-enumerator = <9>;\n+\t\t\tcolor = <LED_COLOR_ID_GREEN>;\n+\t\t\tgpios = <&gpioa 29 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\n+\t\tled-a {\n+\t\t\t/* amber:power */\n+\t\t\tfunction = LED_FUNCTION_POWER;\n+\t\t\tcolor = <LED_COLOR_ID_AMBER>;\n+\t\t\tgpios = <&gpioa 0 GPIO_ACTIVE_LOW>;\n+\t\t\tdefault-state = \"on\";\n+\t\t};\n+\n+\t\tled-b {\n+\t\t\t/* white:status */\n+\t\t\tfunction = LED_FUNCTION_STATUS;\n+\t\t\tcolor = <LED_COLOR_ID_WHITE>;\n+\t\t\tgpios = <&gpioa 31 GPIO_ACTIVE_HIGH>;\n+\t\t};\n+\t};\n+};\n+\n+&srab {\n+\tcompatible = \"brcm,bcm58625-srab\", \"brcm,nsp-srab\";\n+\tstatus = \"okay\";\n+\n+\tports {\n+\t\tport@0 {\n+\t\t\tlabel = \"lan1\";\n+\t\t\treg = <0>;\n+\t\t};\n+\n+\t\tport@1 {\n+\t\t\tlabel = \"lan2\";\n+\t\t\treg = <1>;\n+\t\t};\n+\n+\t\tport@2 {\n+\t\t\tlabel = \"lan3\";\n+\t\t\treg = <2>;\n+\t\t};\n+\n+\t\tport@3 {\n+\t\t\tlabel = \"lan4\";\n+\t\t\treg = <3>;\n+\t\t};\n+\n+\t\tport@4 {\n+\t\t\tlabel = \"wan\";\n+\t\t\treg = <4>;\n+\t\t};\n+\n+\t\tport@8 {\n+\t\t\tethernet = <&amac2>;\n+\t\t\treg = <8>;\n+\t\t\tfixed-link {\n+\t\t\t\tspeed = <1000>;\n+\t\t\t\tfull-duplex;\n+\t\t\t};\n+\t\t};\n+\t};\n+};\n--- /dev/null\n+++ b/arch/arm/boot/dts/bcm958625-meraki-mx64-a0.dts\n@@ -0,0 +1,25 @@\n+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n+/*\n+ * Device Tree Bindings for Cisco Meraki MX64 with A0 SoC.\n+ *\n+ * Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com>\n+ */\n+\n+/dts-v1/;\n+\n+#include \"bcm958625-meraki-kingpin.dtsi\"\n+#include \"bcm-nsp-ax.dtsi\"\n+\n+/ {\n+\tmodel = \"Cisco Meraki MX64(A0)\";\n+\tcompatible = \"meraki,mx64-a0\", \"brcm,bcm58625\", \"brcm,nsp\";\n+\n+\tchosen {\n+\t\tstdout-path = \"serial0:115200n8\";\n+\t};\n+\n+\tmemory@60000000 {\n+\t\tdevice_type = \"memory\";\n+\t\treg = <0x60000000 0x80000000>;\n+\t};\n+};\n--- /dev/null\n+++ b/arch/arm/boot/dts/bcm958625-meraki-mx64.dts\n@@ -0,0 +1,24 @@\n+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n+/*\n+ * Device Tree Bindings for Cisco Meraki MX64 with B0+ SoC.\n+ *\n+ * Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com>\n+ */\n+\n+/dts-v1/;\n+\n+#include \"bcm958625-meraki-kingpin.dtsi\"\n+\n+/ {\n+\tmodel = \"Cisco Meraki MX64\";\n+\tcompatible = \"meraki,mx64\", \"brcm,bcm58625\", \"brcm,nsp\";\n+\n+\tchosen {\n+\t\tstdout-path = \"serial0:115200n8\";\n+\t};\n+\n+\tmemory@60000000 {\n+\t\tdevice_type = \"memory\";\n+\t\treg = <0x60000000 0x80000000>;\n+\t};\n+};\n--- /dev/null\n+++ b/arch/arm/boot/dts/bcm958625-meraki-mx64w-a0.dts\n@@ -0,0 +1,33 @@\n+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n+/*\n+ * Device Tree Bindings for Cisco Meraki MX64W with A0 SoC.\n+ *\n+ * Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com>\n+ */\n+\n+/dts-v1/;\n+\n+#include \"bcm958625-meraki-kingpin.dtsi\"\n+#include \"bcm-nsp-ax.dtsi\"\n+\n+/ {\n+\tmodel = \"Cisco Meraki MX64W(A0)\";\n+\tcompatible = \"meraki,mx64w-a0\", \"brcm,bcm58625\", \"brcm,nsp\";\n+\n+\tchosen {\n+\t\tstdout-path = \"serial0:115200n8\";\n+\t};\n+\n+\tmemory@60000000 {\n+\t\tdevice_type = \"memory\";\n+\t\treg = <0x60000000 0x80000000>;\n+\t};\n+};\n+\n+&pcie0 {\n+\tstatus = \"okay\";\n+};\n+\n+&pcie1 {\n+\tstatus = \"okay\";\n+};\n--- /dev/null\n+++ b/arch/arm/boot/dts/bcm958625-meraki-mx64w.dts\n@@ -0,0 +1,32 @@\n+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n+/*\n+ * Device Tree Bindings for Cisco Meraki MX64W with B0+ SoC.\n+ *\n+ * Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com>\n+ */\n+\n+/dts-v1/;\n+\n+#include \"bcm958625-meraki-kingpin.dtsi\"\n+\n+/ {\n+\tmodel = \"Cisco Meraki MX64W\";\n+\tcompatible = \"meraki,mx64w\", \"brcm,bcm58625\", \"brcm,nsp\";\n+\n+\tchosen {\n+\t\tstdout-path = \"serial0:115200n8\";\n+\t};\n+\n+\tmemory@60000000 {\n+\t\tdevice_type = \"memory\";\n+\t\treg = <0x60000000 0x80000000>;\n+\t};\n+};\n+\n+&pcie0 {\n+\tstatus = \"okay\";\n+};\n+\n+&pcie1 {\n+\tstatus = \"okay\";\n+};\n"
  },
  {
    "path": "target/linux/bcm53xx/patches-5.10/033-v5.15-0009-ARM-dts-NSP-Add-DT-files-for-Meraki-MX65-series.patch",
    "content": "From 702a8f4744ed5b480f2b2411858184afdb10f9fd Mon Sep 17 00:00:00 2001\nFrom: Matthew Hagan <mnhagan88@gmail.com>\nDate: Fri, 6 Aug 2021 21:44:35 +0100\nSubject: [PATCH] ARM: dts: NSP: Add DT files for Meraki MX65 series\n\nMX65 & MX65W Hardware info:\n  - CPU: Broadcom BCM58625 Cortex A9 @ 1200Mhz\n  - RAM: 2 GB (4 x 4Gb SK Hynix H5TC4G83CFR)\n  - Storage: 1 GB (Micron MT29F8G08ABACA)\n  - Networking: BCM58625 switch (2x 1GbE ports)\n    2x Qualcomm QCA8337 switches (10x 1GbE ports total)\n  - PSE: Broadcom BCM59111KMLG connected to LAN ports 11 & 12\n  - USB: 1x USB2.0\n  - Serial: Internal header\n  - WLAN(MX65W Only): 2x Broadcom BCM43520KMLG on the PCI bus.\n\nNote that a driver and firmware image for the BCM59111 PSE has been\nreleased under GPL, but this is not present in the kernel.\n\nSigned-off-by: Matthew Hagan <mnhagan88@gmail.com>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n arch/arm/boot/dts/Makefile                    |   2 +\n arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi | 279 ++++++++++++++++++\n arch/arm/boot/dts/bcm958625-meraki-mx65.dts   |  24 ++\n arch/arm/boot/dts/bcm958625-meraki-mx65w.dts  |  32 ++\n 4 files changed, 337 insertions(+)\n create mode 100644 arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi\n create mode 100644 arch/arm/boot/dts/bcm958625-meraki-mx65.dts\n create mode 100644 arch/arm/boot/dts/bcm958625-meraki-mx65w.dts\n\n--- a/arch/arm/boot/dts/Makefile\n+++ b/arch/arm/boot/dts/Makefile\n@@ -162,6 +162,8 @@ dtb-$(CONFIG_ARCH_BCM_NSP) += \\\n \tbcm958625-meraki-mx64-a0.dtb \\\n \tbcm958625-meraki-mx64w.dtb \\\n \tbcm958625-meraki-mx64w-a0.dtb \\\n+\tbcm958625-meraki-mx65.dtb \\\n+\tbcm958625-meraki-mx65w.dtb \\\n \tbcm958625hr.dtb \\\n \tbcm988312hr.dtb \\\n \tbcm958625k.dtb\n--- /dev/null\n+++ b/arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi\n@@ -0,0 +1,279 @@\n+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n+/*\n+ * Device Tree Bindings for Cisco Meraki MX65 series (Alamo).\n+ *\n+ * Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com>\n+ */\n+\n+#include \"bcm958625-meraki-mx6x-common.dtsi\"\n+\n+/ {\n+\tkeys {\n+\t\tcompatible = \"gpio-keys-polled\";\n+\t\tautorepeat;\n+\t\tpoll-interval = <20>;\n+\n+\t\treset {\n+\t\t\tlabel = \"reset\";\n+\t\t\tlinux,code = <KEY_RESTART>;\n+\t\t\tgpios = <&gpioa 8 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\t};\n+\n+\tleds {\n+\t\tcompatible = \"gpio-leds\";\n+\n+\t\tled-0 {\n+\t\t\t/* green:wan1-left */\n+\t\t\tfunction = LED_FUNCTION_ACTIVITY;\n+\t\t\tfunction-enumerator = <0>;\n+\t\t\tcolor = <LED_COLOR_ID_GREEN>;\n+\t\t\tgpios = <&gpioa 25 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\n+\t\tled-1 {\n+\t\t\t/* green:wan1-right */\n+\t\t\tfunction = LED_FUNCTION_ACTIVITY;\n+\t\t\tfunction-enumerator = <1>;\n+\t\t\tcolor = <LED_COLOR_ID_GREEN>;\n+\t\t\tgpios = <&gpioa 24 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\n+\t\tled-2 {\n+\t\t\t/* green:wan2-left */\n+\t\t\tfunction = LED_FUNCTION_ACTIVITY;\n+\t\t\tfunction-enumerator = <2>;\n+\t\t\tcolor = <LED_COLOR_ID_GREEN>;\n+\t\t\tgpios = <&gpioa 27 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\n+\t\tled-3 {\n+\t\t\t/* green:wan2-right */\n+\t\t\tfunction = LED_FUNCTION_ACTIVITY;\n+\t\t\tfunction-enumerator = <3>;\n+\t\t\tcolor = <LED_COLOR_ID_GREEN>;\n+\t\t\tgpios = <&gpioa 26 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\n+\t\tled-4 {\n+\t\t\t/* amber:power */\n+\t\t\tfunction = LED_FUNCTION_POWER;\n+\t\t\tcolor = <LED_COLOR_ID_AMBER>;\n+\t\t\tgpios = <&gpioa 3 GPIO_ACTIVE_HIGH>;\n+\t\t\tdefault-state = \"on\";\n+\t\t};\n+\n+\t\tled-5 {\n+\t\t\t/* white:status */\n+\t\t\tfunction = LED_FUNCTION_STATUS;\n+\t\t\tcolor = <LED_COLOR_ID_WHITE>;\n+\t\t\tgpios = <&gpioa 31 GPIO_ACTIVE_HIGH>;\n+\t\t};\n+\t};\n+\n+\tmdio-mii-mux {\n+\t\tcompatible = \"mdio-mux-mmioreg\";\n+\t\treg = <0x1803f1c0 0x4>;\n+\t\tmux-mask = <0x2000>;\n+\t\tmdio-parent-bus = <&mdio_ext>;\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\n+\t\tmdio@0 {\n+\t\t\treg = <0x0>;\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tphy_port6: phy@0 {\n+\t\t\t\treg = <0>;\n+\t\t\t};\n+\n+\t\t\tphy_port7: phy@1 {\n+\t\t\t\treg = <1>;\n+\t\t\t};\n+\n+\t\t\tphy_port8: phy@2 {\n+\t\t\t\treg = <2>;\n+\t\t\t};\n+\n+\t\t\tphy_port9: phy@3 {\n+\t\t\t\treg = <3>;\n+\t\t\t};\n+\n+\t\t\tphy_port10: phy@4 {\n+\t\t\t\treg = <4>;\n+\t\t\t};\n+\n+\t\t\tswitch@10 {\n+\t\t\t\tcompatible = \"qca,qca8337\";\n+\t\t\t\treg = <0x10>;\n+\t\t\t\tdsa,member = <1 0>;\n+\n+\t\t\t\tports {\n+\t\t\t\t\t#address-cells = <1>;\n+\t\t\t\t\t#size-cells = <0>;\n+\t\t\t\t\tport@0 {\n+\t\t\t\t\t\treg = <0>;\n+\t\t\t\t\t\tethernet = <&sgmii1>;\n+\t\t\t\t\t\tphy-mode = \"sgmii\";\n+\t\t\t\t\t\tfixed-link {\n+\t\t\t\t\t\t\tspeed = <1000>;\n+\t\t\t\t\t\t\tfull-duplex;\n+\t\t\t\t\t\t};\n+\t\t\t\t\t};\n+\n+\t\t\t\t\tport@1 {\n+\t\t\t\t\t\treg = <1>;\n+\t\t\t\t\t\tlabel = \"lan8\";\n+\t\t\t\t\t\tphy-handle = <&phy_port6>;\n+\t\t\t\t\t};\n+\n+\t\t\t\t\tport@2 {\n+\t\t\t\t\t\treg = <2>;\n+\t\t\t\t\t\tlabel = \"lan9\";\n+\t\t\t\t\t\tphy-handle = <&phy_port7>;\n+\t\t\t\t\t};\n+\n+\t\t\t\t\tport@3 {\n+\t\t\t\t\t\treg = <3>;\n+\t\t\t\t\t\tlabel = \"lan10\";\n+\t\t\t\t\t\tphy-handle = <&phy_port8>;\n+\t\t\t\t\t};\n+\n+\t\t\t\t\tport@4 {\n+\t\t\t\t\t\treg = <4>;\n+\t\t\t\t\t\tlabel = \"lan11\";\n+\t\t\t\t\t\tphy-handle = <&phy_port9>;\n+\t\t\t\t\t};\n+\n+\t\t\t\t\tport@5 {\n+\t\t\t\t\t\treg = <5>;\n+\t\t\t\t\t\tlabel = \"lan12\";\n+\t\t\t\t\t\tphy-handle = <&phy_port10>;\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\t\t\t};\n+\t\t};\n+\n+\t\tmdio-mii@2000 {\n+\t\t\treg = <0x2000>;\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tphy_port1: phy@0 {\n+\t\t\t\treg = <0>;\n+\t\t\t};\n+\n+\t\t\tphy_port2: phy@1 {\n+\t\t\t\treg = <1>;\n+\t\t\t};\n+\n+\t\t\tphy_port3: phy@2 {\n+\t\t\t\treg = <2>;\n+\t\t\t};\n+\n+\t\t\tphy_port4: phy@3 {\n+\t\t\t\treg = <3>;\n+\t\t\t};\n+\n+\t\t\tphy_port5: phy@4 {\n+\t\t\t\treg = <4>;\n+\t\t\t};\n+\n+\t\t\tswitch@10 {\n+\t\t\t\tcompatible = \"qca,qca8337\";\n+\t\t\t\treg = <0x10>;\n+\t\t\t\tdsa,member = <2 0>;\n+\n+\t\t\t\tports {\n+\t\t\t\t\t#address-cells = <1>;\n+\t\t\t\t\t#size-cells = <0>;\n+\t\t\t\t\tport@0 {\n+\t\t\t\t\t\treg = <0>;\n+\t\t\t\t\t\tethernet = <&sgmii0>;\n+\t\t\t\t\t\tphy-mode = \"sgmii\";\n+\t\t\t\t\t\tfixed-link {\n+\t\t\t\t\t\t\tspeed = <1000>;\n+\t\t\t\t\t\t\tfull-duplex;\n+\t\t\t\t\t\t};\n+\t\t\t\t\t};\n+\n+\t\t\t\t\tport@1 {\n+\t\t\t\t\t\treg = <1>;\n+\t\t\t\t\t\tlabel = \"lan3\";\n+\t\t\t\t\t\tphy-handle = <&phy_port1>;\n+\t\t\t\t\t};\n+\n+\t\t\t\t\tport@2 {\n+\t\t\t\t\t\treg = <2>;\n+\t\t\t\t\t\tlabel = \"lan4\";\n+\t\t\t\t\t\tphy-handle = <&phy_port2>;\n+\t\t\t\t\t};\n+\n+\t\t\t\t\tport@3 {\n+\t\t\t\t\t\treg = <3>;\n+\t\t\t\t\t\tlabel = \"lan5\";\n+\t\t\t\t\t\tphy-handle = <&phy_port3>;\n+\t\t\t\t\t};\n+\n+\t\t\t\t\tport@4 {\n+\t\t\t\t\t\treg = <4>;\n+\t\t\t\t\t\tlabel = \"lan6\";\n+\t\t\t\t\t\tphy-handle = <&phy_port4>;\n+\t\t\t\t\t};\n+\n+\t\t\t\t\tport@5 {\n+\t\t\t\t\t\treg = <5>;\n+\t\t\t\t\t\tlabel = \"lan7\";\n+\t\t\t\t\t\tphy-handle = <&phy_port5>;\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\t\t\t};\n+\t\t};\n+\t};\n+};\n+\n+&srab {\n+\tcompatible = \"brcm,bcm58625-srab\", \"brcm,nsp-srab\";\n+\tstatus = \"okay\";\n+\tdsa,member = <0 0>;\n+\n+\tports {\n+\t\tport@0 {\n+\t\t\tlabel = \"wan1\";\n+\t\t\treg = <0>;\n+\t\t};\n+\n+\t\tport@1 {\n+\t\t\tlabel = \"wan2\";\n+\t\t\treg = <1>;\n+\t\t};\n+\n+\t\tsgmii0: port@4 {\n+\t\t\tlabel = \"sw0\";\n+\t\t\treg = <4>;\n+\t\t\tfixed-link {\n+\t\t\t\tspeed = <1000>;\n+\t\t\t\tfull-duplex;\n+\t\t\t};\n+\t\t};\n+\n+\t\tsgmii1: port@5 {\n+\t\t\tlabel = \"sw1\";\n+\t\t\treg = <5>;\n+\t\t\tfixed-link {\n+\t\t\t\tspeed = <1000>;\n+\t\t\t\tfull-duplex;\n+\t\t\t};\n+\t\t};\n+\n+\t\tport@8 {\n+\t\t\tethernet = <&amac2>;\n+\t\t\treg = <8>;\n+\t\t\tfixed-link {\n+\t\t\t\tspeed = <1000>;\n+\t\t\t\tfull-duplex;\n+\t\t\t};\n+\t\t};\n+\t};\n+};\n--- /dev/null\n+++ b/arch/arm/boot/dts/bcm958625-meraki-mx65.dts\n@@ -0,0 +1,24 @@\n+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n+/*\n+ * Device Tree Bindings for Cisco Meraki MX65.\n+ *\n+ * Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com>\n+ */\n+\n+/dts-v1/;\n+\n+#include \"bcm958625-meraki-alamo.dtsi\"\n+\n+/ {\n+\tmodel = \"Cisco Meraki MX65\";\n+\tcompatible = \"meraki,mx65\", \"brcm,bcm58625\", \"brcm,nsp\";\n+\n+\tchosen {\n+\t\tstdout-path = \"serial0:115200n8\";\n+\t};\n+\n+\tmemory@60000000 {\n+\t\tdevice_type = \"memory\";\n+\t\treg = <0x60000000 0x80000000>;\n+\t};\n+};\n--- /dev/null\n+++ b/arch/arm/boot/dts/bcm958625-meraki-mx65w.dts\n@@ -0,0 +1,32 @@\n+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n+/*\n+ * Device Tree Bindings for Cisco Meraki MX65W.\n+ *\n+ * Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com>\n+ */\n+\n+/dts-v1/;\n+\n+#include \"bcm958625-meraki-alamo.dtsi\"\n+\n+/ {\n+\tmodel = \"Cisco Meraki MX65W\";\n+\tcompatible = \"meraki,mx65w\", \"brcm,bcm58625\", \"brcm,nsp\";\n+\n+\tchosen {\n+\t\tstdout-path = \"serial0:115200n8\";\n+\t};\n+\n+\tmemory@60000000 {\n+\t\tdevice_type = \"memory\";\n+\t\treg = <0x60000000 0x80000000>;\n+\t};\n+};\n+\n+&pcie0 {\n+\tstatus = \"okay\";\n+};\n+\n+&pcie1 {\n+\tstatus = \"okay\";\n+};\n"
  },
  {
    "path": "target/linux/bcm53xx/patches-5.10/033-v5.15-0010-ARM-dts-BCM5301X-Fix-nodes-names.patch",
    "content": "From 0e89c0d8e8edece7f8e4607841ca6651885d23b1 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Thu, 19 Aug 2021 08:57:00 +0200\nSubject: [PATCH] ARM: dts: BCM5301X: Fix nodes names\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nThis fixes following errors for all BCM5301X dts files:\nchipcommonA@18000000: $nodename:0: 'chipcommonA@18000000' does not match '^([a-z][a-z0-9\\\\-]+-bus|bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$'\nmpcore@19000000: $nodename:0: 'mpcore@19000000' does not match '^([a-z][a-z0-9\\\\-]+-bus|bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$'\nmdio-bus-mux@18003000: $nodename:0: 'mdio-bus-mux@18003000' does not match '^mdio-mux[\\\\-@]?'\ndmu@1800c000: $nodename:0: 'dmu@1800c000' does not match '^([a-z][a-z0-9\\\\-]+-bus|bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$'\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n arch/arm/boot/dts/bcm47094-linksys-panamera.dts | 2 +-\n arch/arm/boot/dts/bcm5301x.dtsi                 | 8 ++++----\n 2 files changed, 5 insertions(+), 5 deletions(-)\n\n--- a/arch/arm/boot/dts/bcm47094-linksys-panamera.dts\n+++ b/arch/arm/boot/dts/bcm47094-linksys-panamera.dts\n@@ -129,7 +129,7 @@\n \t\t};\n \t};\n \n-\tmdio-bus-mux@18003000 {\n+\tmdio-mux@18003000 {\n \n \t\t/* BIT(9) = 1 => external mdio */\n \t\tmdio@200 {\n--- a/arch/arm/boot/dts/bcm5301x.dtsi\n+++ b/arch/arm/boot/dts/bcm5301x.dtsi\n@@ -19,7 +19,7 @@\n \t#size-cells = <1>;\n \tinterrupt-parent = <&gic>;\n \n-\tchipcommonA@18000000 {\n+\tchipcommon-a-bus@18000000 {\n \t\tcompatible = \"simple-bus\";\n \t\tranges = <0x00000000 0x18000000 0x00001000>;\n \t\t#address-cells = <1>;\n@@ -44,7 +44,7 @@\n \t\t};\n \t};\n \n-\tmpcore@19000000 {\n+\tmpcore-bus@19000000 {\n \t\tcompatible = \"simple-bus\";\n \t\tranges = <0x00000000 0x19000000 0x00023000>;\n \t\t#address-cells = <1>;\n@@ -371,7 +371,7 @@\n \t\t#address-cells = <1>;\n \t};\n \n-\tmdio-bus-mux@18003000 {\n+\tmdio-mux@18003000 {\n \t\tcompatible = \"mdio-mux-mmioreg\";\n \t\tmdio-parent-bus = <&mdio>;\n \t\t#address-cells = <1>;\n@@ -417,7 +417,7 @@\n \t\tstatus = \"disabled\";\n \t};\n \n-\tdmu@1800c000 {\n+\tdmu-bus@1800c000 {\n \t\tcompatible = \"simple-bus\";\n \t\tranges = <0 0x1800c000 0x1000>;\n \t\t#address-cells = <1>;\n"
  },
  {
    "path": "target/linux/bcm53xx/patches-5.10/033-v5.15-0011-ARM-dts-BCM5301X-Fix-MDIO-mux-binding.patch",
    "content": "From 75a5646c26895c4cfadc8d54aa53ac5455947895 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Thu, 19 Aug 2021 08:57:01 +0200\nSubject: [PATCH] ARM: dts: BCM5301X: Fix MDIO mux binding\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nThis fixes following error for all BCM5301X dts files:\nmdio-bus-mux@18003000: compatible: ['mdio-mux-mmioreg'] is too short\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n arch/arm/boot/dts/bcm5301x.dtsi | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/arch/arm/boot/dts/bcm5301x.dtsi\n+++ b/arch/arm/boot/dts/bcm5301x.dtsi\n@@ -372,7 +372,7 @@\n \t};\n \n \tmdio-mux@18003000 {\n-\t\tcompatible = \"mdio-mux-mmioreg\";\n+\t\tcompatible = \"mdio-mux-mmioreg\", \"mdio-mux\";\n \t\tmdio-parent-bus = <&mdio>;\n \t\t#address-cells = <1>;\n \t\t#size-cells = <0>;\n"
  },
  {
    "path": "target/linux/bcm53xx/patches-5.10/033-v5.16-0013-ARM-dts-NSP-Add-bcm958623hr-board-name-to-dts.patch",
    "content": "From 695717eb4c61173d05a277e37132b5e2c6531bf1 Mon Sep 17 00:00:00 2001\nFrom: Matthew Hagan <mnhagan88@gmail.com>\nDate: Sun, 29 Aug 2021 22:37:47 +0000\nSubject: [PATCH] ARM: dts: NSP: Add bcm958623hr board name to dts\n\nThis board was previously added to\nDocumentation/devicetree/bindings/arm/bcm/brcm,nsp.yaml\nhowever the dts file was not updated to reflect this change. This patch\ncorrects bcm958623hr.dts by adding the board name to the compatible.\n\nSigned-off-by: Matthew Hagan <mnhagan88@gmail.com>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n arch/arm/boot/dts/bcm958623hr.dts | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/arch/arm/boot/dts/bcm958623hr.dts\n+++ b/arch/arm/boot/dts/bcm958623hr.dts\n@@ -37,7 +37,7 @@\n \n / {\n \tmodel = \"NorthStar Plus SVK (BCM958623HR)\";\n-\tcompatible = \"brcm,bcm58623\", \"brcm,nsp\";\n+\tcompatible = \"brcm,bcm958623hr\", \"brcm,bcm58623\", \"brcm,nsp\";\n \n \tchosen {\n \t\tstdout-path = \"serial0:115200n8\";\n"
  },
  {
    "path": "target/linux/bcm53xx/patches-5.10/033-v5.16-0015-ARM-dts-NSP-Fix-MDIO-mux-node-names.patch",
    "content": "From 38f8111369f318a538e9d4d89d8e48030c22fb40 Mon Sep 17 00:00:00 2001\nFrom: Matthew Hagan <mnhagan88@gmail.com>\nDate: Sun, 29 Aug 2021 22:37:49 +0000\nSubject: [PATCH] ARM: dts: NSP: Fix MDIO mux node names\n\nWhile functional, the mdio-mux-mmioreg binding does not conform to\nDocumentation/devicetree/bindings/net/mdio-mux-mmioreg.yaml in that an\nmdio-mux compatible is also required. Without this the following output\nis observed when running dtbs_check:\n\nmdio-mux@32000: compatible: ['mdio-mux-mmioreg'] is too short\n\nThis change brings conformance to this requirement and corresponds\nlikewise to Rafal Milecki's change to the BCM5301x platform[1].\n\n[1] https://lore.kernel.org/linux-arm-kernel/20210822191256.3715003-1-f.fainelli@gmail.com/T/\n\nSigned-off-by: Matthew Hagan <mnhagan88@gmail.com>\nReviewed-by: Andrew Lunn <andrew@lunn.ch>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n arch/arm/boot/dts/bcm-nsp.dtsi                | 2 +-\n arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi | 2 +-\n 2 files changed, 2 insertions(+), 2 deletions(-)\n\n--- a/arch/arm/boot/dts/bcm-nsp.dtsi\n+++ b/arch/arm/boot/dts/bcm-nsp.dtsi\n@@ -371,7 +371,7 @@\n \t\t};\n \n \t\tmdio-mux@32000 {\n-\t\t\tcompatible = \"mdio-mux-mmioreg\";\n+\t\t\tcompatible = \"mdio-mux-mmioreg\", \"mdio-mux\";\n \t\t\treg = <0x32000 0x4>;\n \t\t\tmux-mask = <0x200>;\n \t\t\t#address-cells = <1>;\n--- a/arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi\n+++ b/arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi\n@@ -72,7 +72,7 @@\n \t};\n \n \tmdio-mii-mux {\n-\t\tcompatible = \"mdio-mux-mmioreg\";\n+\t\tcompatible = \"mdio-mux-mmioreg\", \"mdio-mux\";\n \t\treg = <0x1803f1c0 0x4>;\n \t\tmux-mask = <0x2000>;\n \t\tmdio-parent-bus = <&mdio_ext>;\n"
  },
  {
    "path": "target/linux/bcm53xx/patches-5.10/033-v5.16-0016-ARM-dts-NSP-Fix-MX64-MX65-eeprom-node-name.patch",
    "content": "From 56e4e548427240d85fd220460d0ab5987e1dec00 Mon Sep 17 00:00:00 2001\nFrom: Matthew Hagan <mnhagan88@gmail.com>\nDate: Sun, 29 Aug 2021 22:37:50 +0000\nSubject: [PATCH] ARM: dts: NSP: Fix MX64/MX65 eeprom node name\n\nRunning dtbs_check yields the following message when checking the\nMX64/MX65 devicetree:\nat24@50: $nodename:0: 'at24@50' does not match '^eeprom@[0-9a-f]{1,2}$'\n\nThis patch fixes the issue by renaming the at24 node appropriately.\n\nSigned-off-by: Matthew Hagan <mnhagan88@gmail.com>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n arch/arm/boot/dts/bcm958625-meraki-mx6x-common.dtsi | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/arch/arm/boot/dts/bcm958625-meraki-mx6x-common.dtsi\n+++ b/arch/arm/boot/dts/bcm958625-meraki-mx6x-common.dtsi\n@@ -48,7 +48,7 @@\n &i2c0 {\n \tstatus = \"okay\";\n \n-\tat24@50 {\n+\teeprom@50 {\n \t\tcompatible = \"atmel,24c64\";\n \t\treg = <0x50>;\n \t\tpagesize = <32>;\n"
  },
  {
    "path": "target/linux/bcm53xx/patches-5.10/033-v5.16-0017-ARM-dts-NSP-Fix-MX65-MDIO-mux-warnings.patch",
    "content": "From f5fc9044e5d45a4d97b5240c8723f4677f647c9f Mon Sep 17 00:00:00 2001\nFrom: Matthew Hagan <mnhagan88@gmail.com>\nDate: Sun, 29 Aug 2021 22:37:51 +0000\nSubject: [PATCH] ARM: dts: NSP: Fix MX65 MDIO mux warnings\n\nThe naming of this node is based upon that of the initial EA9500 dts[1].\nHowever this does not conform with the mdio-mux format, yielding the\nfollowing message when running dtbs_check:\nmdio-mii-mux: $nodename:0: 'mdio-mii-mux' does not match '^mdio-mux[\\\\-@]?'\n\nSecondly, this node should be moved to within the axi node and given the\nappropriate unit address. This also requires exposing the axi node via a\nlabel in bcm-nsp.dtsi. This fixes the following warning:\nWarning (unit_address_vs_reg): /mdio-mii-mux: node has a reg or ranges property, but no unit name\n\n[1]https://patchwork.ozlabs.org/project/linux-imx/patch/20180618174159.86150-1-npcomplete13@gmail.com/#1941353\n\nSigned-off-by: Matthew Hagan <mnhagan88@gmail.com>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n arch/arm/boot/dts/bcm-nsp.dtsi                | 2 +-\n arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi | 6 ++++--\n 2 files changed, 5 insertions(+), 3 deletions(-)\n\n--- a/arch/arm/boot/dts/bcm-nsp.dtsi\n+++ b/arch/arm/boot/dts/bcm-nsp.dtsi\n@@ -166,7 +166,7 @@\n \t\t};\n \t};\n \n-\taxi@18000000 {\n+\taxi: axi@18000000 {\n \t\tcompatible = \"simple-bus\";\n \t\tranges = <0x00000000 0x18000000 0x0011c40c>;\n \t\t#address-cells = <1>;\n--- a/arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi\n+++ b/arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi\n@@ -70,10 +70,12 @@\n \t\t\tgpios = <&gpioa 31 GPIO_ACTIVE_HIGH>;\n \t\t};\n \t};\n+};\n \n-\tmdio-mii-mux {\n+&axi {\n+\tmdio-mux@3f1c0 {\n \t\tcompatible = \"mdio-mux-mmioreg\", \"mdio-mux\";\n-\t\treg = <0x1803f1c0 0x4>;\n+\t\treg = <0x3f1c0 0x4>;\n \t\tmux-mask = <0x2000>;\n \t\tmdio-parent-bus = <&mdio_ext>;\n \t\t#address-cells = <1>;\n"
  },
  {
    "path": "target/linux/bcm53xx/patches-5.10/033-v5.16-0018-ARM-dts-BCM5301X-Specify-switch-ports-for-more-devic.patch",
    "content": "From 225ffaf3d0e00daa2d0c7b68e8fd731ebbde3c03 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Tue, 7 Sep 2021 08:00:48 +0200\nSubject: [PATCH] ARM: dts: BCM5301X: Specify switch ports for more devices\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nThose are remaining models I have that didn't have ports yet. All\ntested.\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n arch/arm/boot/dts/bcm4708-netgear-r6250.dts   | 37 ++++++++++++++++\n .../boot/dts/bcm47081-buffalo-wzr-600dhp2.dts | 37 ++++++++++++++++\n arch/arm/boot/dts/bcm4709-netgear-r8000.dts   | 42 +++++++++++++++++++\n arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts | 42 +++++++++++++++++++\n arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts | 37 ++++++++++++++++\n arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts | 37 ++++++++++++++++\n 6 files changed, 232 insertions(+)\n\n--- a/arch/arm/boot/dts/bcm4708-netgear-r6250.dts\n+++ b/arch/arm/boot/dts/bcm4708-netgear-r6250.dts\n@@ -94,3 +94,40 @@\n &usb3_phy {\n \tstatus = \"okay\";\n };\n+\n+&srab {\n+\tstatus = \"okay\";\n+\n+\tports {\n+\t\tport@0 {\n+\t\t\treg = <0>;\n+\t\t\tlabel = \"lan4\";\n+\t\t};\n+\n+\t\tport@1 {\n+\t\t\treg = <1>;\n+\t\t\tlabel = \"lan3\";\n+\t\t};\n+\n+\t\tport@2 {\n+\t\t\treg = <2>;\n+\t\t\tlabel = \"lan2\";\n+\t\t};\n+\n+\t\tport@3 {\n+\t\t\treg = <3>;\n+\t\t\tlabel = \"lan1\";\n+\t\t};\n+\n+\t\tport@4 {\n+\t\t\treg = <4>;\n+\t\t\tlabel = \"wan\";\n+\t\t};\n+\n+\t\tport@5 {\n+\t\t\treg = <5>;\n+\t\t\tlabel = \"cpu\";\n+\t\t\tethernet = <&gmac0>;\n+\t\t};\n+\t};\n+};\n--- a/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts\n+++ b/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts\n@@ -117,3 +117,40 @@\n \t\t};\n \t};\n };\n+\n+&srab {\n+\tstatus = \"okay\";\n+\n+\tports {\n+\t\tport@0 {\n+\t\t\treg = <0>;\n+\t\t\tlabel = \"lan1\";\n+\t\t};\n+\n+\t\tport@1 {\n+\t\t\treg = <1>;\n+\t\t\tlabel = \"lan2\";\n+\t\t};\n+\n+\t\tport@2 {\n+\t\t\treg = <2>;\n+\t\t\tlabel = \"lan3\";\n+\t\t};\n+\n+\t\tport@3 {\n+\t\t\treg = <3>;\n+\t\t\tlabel = \"lan4\";\n+\t\t};\n+\n+\t\tport@4 {\n+\t\t\treg = <4>;\n+\t\t\tlabel = \"wan\";\n+\t\t};\n+\n+\t\tport@5 {\n+\t\t\treg = <5>;\n+\t\t\tlabel = \"cpu\";\n+\t\t\tethernet = <&gmac0>;\n+\t\t};\n+\t};\n+};\n--- a/arch/arm/boot/dts/bcm4709-netgear-r8000.dts\n+++ b/arch/arm/boot/dts/bcm4709-netgear-r8000.dts\n@@ -187,3 +187,45 @@\n &usb3_phy {\n \tstatus = \"okay\";\n };\n+\n+&srab {\n+\tstatus = \"okay\";\n+\n+\tports {\n+\t\tport@0 {\n+\t\t\treg = <0>;\n+\t\t\tlabel = \"lan1\";\n+\t\t};\n+\n+\t\tport@1 {\n+\t\t\treg = <1>;\n+\t\t\tlabel = \"lan2\";\n+\t\t};\n+\n+\t\tport@2 {\n+\t\t\treg = <2>;\n+\t\t\tlabel = \"lan3\";\n+\t\t};\n+\n+\t\tport@3 {\n+\t\t\treg = <3>;\n+\t\t\tlabel = \"lan4\";\n+\t\t};\n+\n+\t\tport@4 {\n+\t\t\treg = <4>;\n+\t\t\tlabel = \"wan\";\n+\t\t};\n+\n+\t\tport@8 {\n+\t\t\treg = <8>;\n+\t\t\tlabel = \"cpu\";\n+\t\t\tethernet = <&gmac2>;\n+\n+\t\t\tfixed-link {\n+\t\t\t\tspeed = <1000>;\n+\t\t\t\tfull-duplex;\n+\t\t\t};\n+\t\t};\n+\t};\n+};\n--- a/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts\n+++ b/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts\n@@ -118,3 +118,45 @@\n &usb3_phy {\n \tstatus = \"okay\";\n };\n+\n+&srab {\n+\tstatus = \"okay\";\n+\n+\tports {\n+\t\tport@0 {\n+\t\t\treg = <0>;\n+\t\t\tlabel = \"lan4\";\n+\t\t};\n+\n+\t\tport@1 {\n+\t\t\treg = <1>;\n+\t\t\tlabel = \"lan3\";\n+\t\t};\n+\n+\t\tport@2 {\n+\t\t\treg = <2>;\n+\t\t\tlabel = \"lan2\";\n+\t\t};\n+\n+\t\tport@3 {\n+\t\t\treg = <3>;\n+\t\t\tlabel = \"lan1\";\n+\t\t};\n+\n+\t\tport@4 {\n+\t\t\treg = <4>;\n+\t\t\tlabel = \"wan\";\n+\t\t};\n+\n+\t\tport@8 {\n+\t\t\treg = <8>;\n+\t\t\tlabel = \"cpu\";\n+\t\t\tethernet = <&gmac2>;\n+\n+\t\t\tfixed-link {\n+\t\t\t\tspeed = <1000>;\n+\t\t\t\tfull-duplex;\n+\t\t\t};\n+\t\t};\n+\t};\n+};\n--- a/arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts\n+++ b/arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts\n@@ -68,3 +68,40 @@\n &usb3_phy {\n \tstatus = \"okay\";\n };\n+\n+&srab {\n+\tstatus = \"okay\";\n+\n+\tports {\n+\t\tport@0 {\n+\t\t\treg = <0>;\n+\t\t\tlabel = \"wan\";\n+\t\t};\n+\n+\t\tport@1 {\n+\t\t\treg = <1>;\n+\t\t\tlabel = \"lan4\";\n+\t\t};\n+\n+\t\tport@2 {\n+\t\t\treg = <2>;\n+\t\t\tlabel = \"lan3\";\n+\t\t};\n+\n+\t\tport@3 {\n+\t\t\treg = <3>;\n+\t\t\tlabel = \"lan2\";\n+\t\t};\n+\n+\t\tport@4 {\n+\t\t\treg = <4>;\n+\t\t\tlabel = \"lan1\";\n+\t\t};\n+\n+\t\tport@5 {\n+\t\t\treg = <5>;\n+\t\t\tlabel = \"cpu\";\n+\t\t\tethernet = <&gmac0>;\n+\t\t};\n+\t};\n+};\n--- a/arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts\n+++ b/arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts\n@@ -68,3 +68,40 @@\n &usb3_phy {\n \tstatus = \"okay\";\n };\n+\n+&srab {\n+\tstatus = \"okay\";\n+\n+\tports {\n+\t\tport@0 {\n+\t\t\treg = <0>;\n+\t\t\tlabel = \"wan\";\n+\t\t};\n+\n+\t\tport@1 {\n+\t\t\treg = <1>;\n+\t\t\tlabel = \"lan4\";\n+\t\t};\n+\n+\t\tport@2 {\n+\t\t\treg = <2>;\n+\t\t\tlabel = \"lan3\";\n+\t\t};\n+\n+\t\tport@3 {\n+\t\t\treg = <3>;\n+\t\t\tlabel = \"lan2\";\n+\t\t};\n+\n+\t\tport@4 {\n+\t\t\treg = <4>;\n+\t\t\tlabel = \"lan1\";\n+\t\t};\n+\n+\t\tport@5 {\n+\t\t\treg = <5>;\n+\t\t\tlabel = \"cpu\";\n+\t\t\tethernet = <&gmac0>;\n+\t\t};\n+\t};\n+};\n"
  },
  {
    "path": "target/linux/bcm53xx/patches-5.10/033-v5.16-0019-ARM-dts-BCM53573-Describe-on-SoC-BCM53125-rev-4-swit.patch",
    "content": "From 9fb90ae6cae7f8fe4fbf626945f32cd9da2c3892 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Mon, 20 Sep 2021 16:10:23 +0200\nSubject: [PATCH] ARM: dts: BCM53573: Describe on-SoC BCM53125 rev 4 switch\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nBCM53573 family SoC have Ethernet switch connected to the first Ethernet\ncontroller (accessible over MDIO).\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n arch/arm/boot/dts/bcm53573.dtsi | 18 ++++++++++++++++++\n 1 file changed, 18 insertions(+)\n\n--- a/arch/arm/boot/dts/bcm53573.dtsi\n+++ b/arch/arm/boot/dts/bcm53573.dtsi\n@@ -180,6 +180,24 @@\n \n \t\tgmac0: ethernet@5000 {\n \t\t\treg = <0x5000 0x1000>;\n+\n+\t\t\tmdio {\n+\t\t\t\t#address-cells = <1>;\n+\t\t\t\t#size-cells = <0>;\n+\n+\t\t\t\tswitch: switch@1e {\n+\t\t\t\t\tcompatible = \"brcm,bcm53125\";\n+\t\t\t\t\treg = <0x1e>;\n+\n+\t\t\t\t\tstatus = \"disabled\";\n+\n+\t\t\t\t\t/* ports are defined in board DTS */\n+\t\t\t\t\tports {\n+\t\t\t\t\t\t#address-cells = <1>;\n+\t\t\t\t\t\t#size-cells = <0>;\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\t\t\t};\n \t\t};\n \n \t\tgmac1: ethernet@b000 {\n"
  },
  {
    "path": "target/linux/bcm53xx/patches-5.10/033-v5.16-0020-ARM-dts-BCM53573-Add-Tenda-AC9-switch-ports.patch",
    "content": "From 64612828628cca6e3992e421f45c242dc6625647 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Mon, 20 Sep 2021 16:10:24 +0200\nSubject: [PATCH] ARM: dts: BCM53573: Add Tenda AC9 switch ports\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nThis router has 1 WAN and 4 LAN ports.\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n arch/arm/boot/dts/bcm47189-tenda-ac9.dts | 37 ++++++++++++++++++++++++\n 1 file changed, 37 insertions(+)\n\n--- a/arch/arm/boot/dts/bcm47189-tenda-ac9.dts\n+++ b/arch/arm/boot/dts/bcm47189-tenda-ac9.dts\n@@ -105,3 +105,40 @@\n \t\t};\n \t};\n };\n+\n+&switch {\n+\tstatus = \"okay\";\n+\n+\tports {\n+\t\tport@0 {\n+\t\t\treg = <0>;\n+\t\t\tlabel = \"wan\";\n+\t\t};\n+\n+\t\tport@1 {\n+\t\t\treg = <1>;\n+\t\t\tlabel = \"lan1\";\n+\t\t};\n+\n+\t\tport@2 {\n+\t\t\treg = <2>;\n+\t\t\tlabel = \"lan2\";\n+\t\t};\n+\n+\t\tport@3 {\n+\t\t\treg = <3>;\n+\t\t\tlabel = \"lan3\";\n+\t\t};\n+\n+\t\tport@4 {\n+\t\t\treg = <4>;\n+\t\t\tlabel = \"lan4\";\n+\t\t};\n+\n+\t\tport@5 {\n+\t\t\treg = <5>;\n+\t\t\tlabel = \"cpu\";\n+\t\t\tethernet = <&gmac0>;\n+\t\t};\n+\t};\n+};\n"
  },
  {
    "path": "target/linux/bcm53xx/patches-5.10/033-v5.16-0021-ARM-BCM53016-Specify-switch-ports-for-Meraki-MR32.patch",
    "content": "From 6abc4ca5a28070945e0d68cb4160b309bfbf4b8b Mon Sep 17 00:00:00 2001\nFrom: Christian Lamparter <chunkeey@gmail.com>\nDate: Sat, 18 Sep 2021 19:29:30 +0200\nSubject: [PATCH] ARM: BCM53016: Specify switch ports for Meraki MR32\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nthe switch identifies itself as a BCM53012 (rev 5)...\nThis patch has been tested & verified on OpenWrt's\nsnapshot with Linux 5.10 (didn't test any older kernels).\nThe MR32 is able to \"talk to the network\" as before with\nOpenWrt's SWITCHDEV b53 driver.\n\n| b53-srab-switch 18007000.ethernet-switch: found switch: BCM53012, rev 5\n| libphy: dsa slave smi: probed\n| b53-srab-switch 18007000.ethernet-switch poe (uninitialized):\n|\tPHY [dsa-0.0:00] driver [Generic PHY] (irq=POLL)\n| b53-srab-switch 18007000.ethernet-switch: Using legacy PHYLIB callbacks.\n|\tPlease migrate to PHYLINK!\n| DSA: tree 0 setup\n\nReported-by: Rafał Miłecki <zajec5@gmail.com>\nSigned-off-by: Christian Lamparter <chunkeey@gmail.com>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n arch/arm/boot/dts/bcm53016-meraki-mr32.dts | 22 ++++++++++++++++++++++\n 1 file changed, 22 insertions(+)\n\n--- a/arch/arm/boot/dts/bcm53016-meraki-mr32.dts\n+++ b/arch/arm/boot/dts/bcm53016-meraki-mr32.dts\n@@ -217,3 +217,25 @@\n \t\t};\n \t};\n };\n+\n+&srab {\n+\tstatus = \"okay\";\n+\n+\tports {\n+\t\tport@0 {\n+\t\t\treg = <0>;\n+\t\t\tlabel = \"poe\";\n+\t\t};\n+\n+\t\tport@5 {\n+\t\t\treg = <5>;\n+\t\t\tlabel = \"cpu\";\n+\t\t\tethernet = <&gmac0>;\n+\n+\t\t\tfixed-link {\n+\t\t\t\tspeed = <1000>;\n+\t\t\t\tduplex-full;\n+\t\t\t};\n+\t\t};\n+\t};\n+};\n"
  },
  {
    "path": "target/linux/bcm53xx/patches-5.10/033-v5.16-0022-ARM-BCM53016-MR32-get-mac-address-from-nvmem.patch",
    "content": "From 477ffdbdf389cc91294d66e251cc6f856da5820c Mon Sep 17 00:00:00 2001\nFrom: Christian Lamparter <chunkeey@gmail.com>\nDate: Sat, 18 Sep 2021 19:29:31 +0200\nSubject: [PATCH] ARM: BCM53016: MR32: get mac-address from nvmem\n\nThe MAC-Address of the MR32's sole ethernet port is\nlocated in offset 0x66 of the attached AT24C64 eeprom.\n\nSigned-off-by: Christian Lamparter <chunkeey@gmail.com>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n arch/arm/boot/dts/bcm53016-meraki-mr32.dts | 11 +++++++++++\n 1 file changed, 11 insertions(+)\n\n--- a/arch/arm/boot/dts/bcm53016-meraki-mr32.dts\n+++ b/arch/arm/boot/dts/bcm53016-meraki-mr32.dts\n@@ -110,6 +110,12 @@\n \t\t\treg = <0x50>;\n \t\t\tpagesize = <32>;\n \t\t\tread-only;\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <1>;\n+\n+\t\t\tmac_address: mac-address@66 {\n+\t\t\t\treg = <0x66 0x6>;\n+\t\t\t};\n \t\t};\n \t};\n };\n@@ -133,6 +139,11 @@\n \t */\n };\n \n+&gmac0 {\n+\tnvmem-cell-names = \"mac-address\";\n+\tnvmem-cells = <&mac_address>;\n+};\n+\n &gmac1 {\n \tstatus = \"disabled\";\n };\n"
  },
  {
    "path": "target/linux/bcm53xx/patches-5.10/033-v5.16-0023-ARM-dts-BCM5301X-Add-DT-for-Asus-RT-AC88U.patch",
    "content": "From beff77b93452cd2057c859694709dd34a181488f Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>\nDate: Tue, 21 Sep 2021 20:19:01 +0800\nSubject: [PATCH] ARM: dts: BCM5301X: Add DT for Asus RT-AC88U\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nHardware Info\n-------------\n\nProcessor\t- Broadcom BCM4709C0KFEBG dual-core @ 1.4 GHz\nSwitch\t\t- BCM53012 in BCM4709C0KFEBG & external RTL8365MB\nDDR3 RAM\t- 512 MB\nFlash\t\t- 128 MB (ESMT F59L1G81LA-25T)\n2.4GHz\t\t- BCM4366 4×4 2.4/5G single chip 802.11ac SoC\n5GHz\t\t- BCM4366 4×4 2.4/5G single chip 802.11ac SoC\nPorts\t\t- 8 Ports, 1 WAN Ports\n\nTested on OpenWrt on kernel 5.10 built with DSA driver.\n\nSigned-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n arch/arm/boot/dts/Makefile                   |   1 +\n arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts | 200 +++++++++++++++++++\n 2 files changed, 201 insertions(+)\n create mode 100644 arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts\n\n--- a/arch/arm/boot/dts/Makefile\n+++ b/arch/arm/boot/dts/Makefile\n@@ -118,6 +118,7 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \\\n \tbcm4709-netgear-r7000.dtb \\\n \tbcm4709-netgear-r8000.dtb \\\n \tbcm4709-tplink-archer-c9-v1.dtb \\\n+\tbcm47094-asus-rt-ac88u.dtb \\\n \tbcm47094-dlink-dir-885l.dtb \\\n \tbcm47094-linksys-panamera.dtb \\\n \tbcm47094-luxul-abr-4500.dtb \\\n--- /dev/null\n+++ b/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts\n@@ -0,0 +1,200 @@\n+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n+/*\n+ * Copyright (C) 2021 Arınç ÜNAL <arinc.unal@arinc9.com>\n+ */\n+\n+/dts-v1/;\n+\n+#include \"bcm47094.dtsi\"\n+#include \"bcm5301x-nand-cs0-bch8.dtsi\"\n+\n+/ {\n+\tcompatible = \"asus,rt-ac88u\", \"brcm,bcm47094\", \"brcm,bcm4708\";\n+\tmodel = \"Asus RT-AC88U\";\n+\n+\tchosen {\n+\t\tbootargs = \"earlycon\";\n+\t};\n+\n+\tmemory@0 {\n+\t\tdevice_type = \"memory\";\n+\t\treg = <0x00000000 0x08000000>,\n+\t\t      <0x88000000 0x18000000>;\n+\t};\n+\n+\tnvram@1c080000 {\n+\t\tcompatible = \"brcm,nvram\";\n+\t\treg = <0x1c080000 0x00180000>;\n+\t};\n+\n+\tleds {\n+\t\tcompatible = \"gpio-leds\";\n+\n+\t\tpower {\n+\t\t\tlabel = \"white:power\";\n+\t\t\tgpios = <&chipcommon 3 GPIO_ACTIVE_LOW>;\n+\t\t\tlinux,default-trigger = \"default-on\";\n+\t\t};\n+\n+\t\twan-red {\n+\t\t\tlabel = \"red:wan\";\n+\t\t\tgpios = <&chipcommon 5 GPIO_ACTIVE_HIGH>;\n+\t\t};\n+\n+\t\tlan {\n+\t\t\tlabel = \"white:lan\";\n+\t\t\tgpios = <&chipcommon 21 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\n+\t\tusb2 {\n+\t\t\tlabel = \"white:usb2\";\n+\t\t\tgpios = <&chipcommon 16 GPIO_ACTIVE_LOW>;\n+\t\t\ttrigger-sources = <&ehci_port2>;\n+\t\t\tlinux,default-trigger = \"usbport\";\n+\t\t};\n+\n+\t\tusb3 {\n+\t\t\tlabel = \"white:usb3\";\n+\t\t\tgpios = <&chipcommon 17 GPIO_ACTIVE_LOW>;\n+\t\t\ttrigger-sources = <&ehci_port1>, <&xhci_port1>;\n+\t\t\tlinux,default-trigger = \"usbport\";\n+\t\t};\n+\n+\t\twps {\n+\t\t\tlabel = \"white:wps\";\n+\t\t\tgpios = <&chipcommon 19 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\t};\n+\n+\tgpio-keys {\n+\t\tcompatible = \"gpio-keys\";\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\n+\t\twps {\n+\t\t\tlabel = \"WPS\";\n+\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n+\t\t\tgpios = <&chipcommon 20 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\n+\t\treset {\n+\t\t\tlabel = \"Reset\";\n+\t\t\tlinux,code = <KEY_RESTART>;\n+\t\t\tgpios = <&chipcommon 11 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\n+\t\twifi {\n+\t\t\tlabel = \"Wi-Fi\";\n+\t\t\tlinux,code = <KEY_RFKILL>;\n+\t\t\tgpios = <&chipcommon 18 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\n+\t\tled {\n+\t\t\tlabel = \"Backlight\";\n+\t\t\tlinux,code = <KEY_BRIGHTNESS_ZERO>;\n+\t\t\tgpios = <&chipcommon 4 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\t};\n+};\n+\n+&srab {\n+\tcompatible = \"brcm,bcm53012-srab\", \"brcm,bcm5301x-srab\";\n+\tstatus = \"okay\";\n+\tdsa,member = <0 0>;\n+\n+\tports {\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\n+\t\tport@0 {\n+\t\t\treg = <0>;\n+\t\t\tlabel = \"lan4\";\n+\t\t};\n+\n+\t\tport@1 {\n+\t\t\treg = <1>;\n+\t\t\tlabel = \"lan3\";\n+\t\t};\n+\n+\t\tport@2 {\n+\t\t\treg = <2>;\n+\t\t\tlabel = \"lan2\";\n+\t\t};\n+\n+\t\tport@3 {\n+\t\t\treg = <3>;\n+\t\t\tlabel = \"lan1\";\n+\t\t};\n+\n+\t\tport@4 {\n+\t\t\treg = <4>;\n+\t\t\tlabel = \"wan\";\n+\t\t};\n+\n+\t\tsw0_p5: port@5 {\n+\t\t\treg = <5>;\n+\t\t\tlabel = \"extsw\";\n+\n+\t\t\tfixed-link {\n+\t\t\t\tspeed = <1000>;\n+\t\t\t\tfull-duplex;\n+\t\t\t};\n+\t\t};\n+\n+\t\tport@7 {\n+\t\t\treg = <7>;\n+\t\t\tethernet = <&gmac1>;\n+\t\t\tlabel = \"cpu\";\n+\n+\t\t\tfixed-link {\n+\t\t\t\tspeed = <1000>;\n+\t\t\t\tfull-duplex;\n+\t\t\t};\n+\t\t};\n+\n+\t\tport@8 {\n+\t\t\treg = <8>;\n+\t\t\tethernet = <&gmac2>;\n+\t\t\tlabel = \"cpu\";\n+\t\t\tstatus = \"disabled\";\n+\n+\t\t\tfixed-link {\n+\t\t\t\tspeed = <1000>;\n+\t\t\t\tfull-duplex;\n+\t\t\t};\n+\t\t};\n+\t};\n+};\n+\n+&usb2 {\n+\tvcc-gpio = <&chipcommon 9 GPIO_ACTIVE_HIGH>;\n+};\n+\n+&usb3_phy {\n+\tstatus = \"okay\";\n+};\n+\n+&nandcs {\n+\tpartitions {\n+\t\tcompatible = \"fixed-partitions\";\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <1>;\n+\n+\t\tpartition@0 {\n+\t\t\tlabel = \"boot\";\n+\t\t\treg = <0x00000000 0x00080000>;\n+\t\t\tread-only;\n+\t\t};\n+\n+\t\tpartition@80000 {\n+\t\t\tlabel = \"nvram\";\n+\t\t\treg = <0x00080000 0x00180000>;\n+\t\t};\n+\n+\t\tpartition@200000 {\n+\t\t\tlabel = \"firmware\";\n+\t\t\treg = <0x00200000 0x07e00000>;\n+\t\t\tcompatible = \"brcm,trx\";\n+\t\t};\n+\t};\n+};\n"
  },
  {
    "path": "target/linux/bcm53xx/patches-5.10/034-v5.17-0001-ARM-dts-NSP-MX65-add-qca8k-falling-edge-PLL-properti.patch",
    "content": "From 58d3d07985c1adab31a3ed76360d016bb1c5b358 Mon Sep 17 00:00:00 2001\nFrom: Matthew Hagan <mnhagan88@gmail.com>\nDate: Fri, 15 Oct 2021 23:50:22 +0100\nSubject: [PATCH] ARM: dts: NSP: MX65: add qca8k falling-edge, PLL properties\n\nThis patch enables two properties for the QCA8337 switches on the MX65.\n\nSet the SGMII transmit clock to falling edge\n\"qca,sgmii-txclk-falling-edge\" to conform to the OEM configuration [1].\n\nThe new explicit PLL enable option \"qca,sgmii-enable-pll\" is required\n[2].\n\n[1] https://git.kernel.org/netdev/net-next/c/6c43809bf1be\n[2] https://git.kernel.org/netdev/net-next/c/bbc4799e8bb6\n\nSigned-off-by: Matthew Hagan <mnhagan88@gmail.com>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi | 4 ++++\n 1 file changed, 4 insertions(+)\n\n--- a/arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi\n+++ b/arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi\n@@ -118,6 +118,8 @@\n \t\t\t\t\t\treg = <0>;\n \t\t\t\t\t\tethernet = <&sgmii1>;\n \t\t\t\t\t\tphy-mode = \"sgmii\";\n+\t\t\t\t\t\tqca,sgmii-enable-pll;\n+\t\t\t\t\t\tqca,sgmii-txclk-falling-edge;\n \t\t\t\t\t\tfixed-link {\n \t\t\t\t\t\t\tspeed = <1000>;\n \t\t\t\t\t\t\tfull-duplex;\n@@ -194,6 +196,8 @@\n \t\t\t\t\t\treg = <0>;\n \t\t\t\t\t\tethernet = <&sgmii0>;\n \t\t\t\t\t\tphy-mode = \"sgmii\";\n+\t\t\t\t\t\tqca,sgmii-enable-pll;\n+\t\t\t\t\t\tqca,sgmii-txclk-falling-edge;\n \t\t\t\t\t\tfixed-link {\n \t\t\t\t\t\t\tspeed = <1000>;\n \t\t\t\t\t\t\tfull-duplex;\n"
  },
  {
    "path": "target/linux/bcm53xx/patches-5.10/034-v5.17-0002-ARM-dts-BCM5301X-remove-unnecessary-address-size-cel.patch",
    "content": "From 835992e7eca4b29a87c204cefff2f7863fd087f3 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>\nDate: Wed, 27 Oct 2021 00:57:03 +0800\nSubject: [PATCH] ARM: dts: BCM5301X: remove unnecessary address & size cells\n from Asus RT-AC88U\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nRemove the unnecessary #address-cells & #size-cells in the gpio-keys node\nfrom the device tree of Asus RT-AC88U.\n\nSigned-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts | 2 --\n 1 file changed, 2 deletions(-)\n\n--- a/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts\n+++ b/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts\n@@ -68,8 +68,6 @@\n \n \tgpio-keys {\n \t\tcompatible = \"gpio-keys\";\n-\t\t#address-cells = <1>;\n-\t\t#size-cells = <0>;\n \n \t\twps {\n \t\t\tlabel = \"WPS\";\n"
  },
  {
    "path": "target/linux/bcm53xx/patches-5.10/034-v5.17-0003-ARM-dts-BCM5301X-define-RTL8365MB-switch-on-Asus-RT-.patch",
    "content": "From b6c99228c8edc5e67d8229ba1c5f76cce210ddfc Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>\nDate: Wed, 27 Oct 2021 00:57:06 +0800\nSubject: [PATCH] ARM: dts: BCM5301X: define RTL8365MB switch on Asus RT-AC88U\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nDefine the Realtek RTL8365MB switch without interrupt support on the device\ntree of Asus RT-AC88U.\n\nSigned-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>\nAcked-by: Alvin Šipraga <alsi@bang-olufsen.dk>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts | 77 ++++++++++++++++++++\n 1 file changed, 77 insertions(+)\n\n--- a/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts\n+++ b/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts\n@@ -93,6 +93,83 @@\n \t\t\tgpios = <&chipcommon 4 GPIO_ACTIVE_LOW>;\n \t\t};\n \t};\n+\n+\tswitch {\n+\t\tcompatible = \"realtek,rtl8365mb\";\n+\t\t/* 7 = MDIO (has input reads), 6 = MDC (clock, output only) */\n+\t\tmdc-gpios = <&chipcommon 6 GPIO_ACTIVE_HIGH>;\n+\t\tmdio-gpios = <&chipcommon 7 GPIO_ACTIVE_HIGH>;\n+\t\treset-gpios = <&chipcommon 10 GPIO_ACTIVE_LOW>;\n+\t\trealtek,disable-leds;\n+\t\tdsa,member = <1 0>;\n+\n+\t\tports {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\treg = <0>;\n+\n+\t\t\tport@0 {\n+\t\t\t\treg = <0>;\n+\t\t\t\tlabel = \"lan5\";\n+\t\t\t\tphy-handle = <&ethphy0>;\n+\t\t\t};\n+\n+\t\t\tport@1 {\n+\t\t\t\treg = <1>;\n+\t\t\t\tlabel = \"lan6\";\n+\t\t\t\tphy-handle = <&ethphy1>;\n+\t\t\t};\n+\n+\t\t\tport@2 {\n+\t\t\t\treg = <2>;\n+\t\t\t\tlabel = \"lan7\";\n+\t\t\t\tphy-handle = <&ethphy2>;\n+\t\t\t};\n+\n+\t\t\tport@3 {\n+\t\t\t\treg = <3>;\n+\t\t\t\tlabel = \"lan8\";\n+\t\t\t\tphy-handle = <&ethphy3>;\n+\t\t\t};\n+\n+\t\t\tport@6 {\n+\t\t\t\treg = <6>;\n+\t\t\t\tlabel = \"cpu\";\n+\t\t\t\tethernet = <&sw0_p5>;\n+\t\t\t\tphy-mode = \"rgmii\";\n+\t\t\t\ttx-internal-delay-ps = <2000>;\n+\t\t\t\trx-internal-delay-ps = <2000>;\n+\n+\t\t\t\tfixed-link {\n+\t\t\t\t\tspeed = <1000>;\n+\t\t\t\t\tfull-duplex;\n+\t\t\t\t\tpause;\n+\t\t\t\t};\n+\t\t\t};\n+\t\t};\n+\n+\t\tmdio {\n+\t\t\tcompatible = \"realtek,smi-mdio\";\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tethphy0: ethernet-phy@0 {\n+\t\t\t\treg = <0>;\n+\t\t\t};\n+\n+\t\t\tethphy1: ethernet-phy@1 {\n+\t\t\t\treg = <1>;\n+\t\t\t};\n+\n+\t\t\tethphy2: ethernet-phy@2 {\n+\t\t\t\treg = <2>;\n+\t\t\t};\n+\n+\t\t\tethphy3: ethernet-phy@3 {\n+\t\t\t\treg = <3>;\n+\t\t\t};\n+\t\t};\n+\t};\n };\n \n &srab {\n"
  },
  {
    "path": "target/linux/bcm53xx/patches-5.10/034-v5.17-0004-ARM-BCM53016-MR32-convert-to-Broadcom-iProc-I2C-Driv.patch",
    "content": "From de7880016665afe7fa7d40e1fafa859260d53ba1 Mon Sep 17 00:00:00 2001\nFrom: Christian Lamparter <chunkeey@gmail.com>\nDate: Thu, 28 Oct 2021 09:03:44 +0200\nSubject: [PATCH] ARM: BCM53016: MR32: convert to Broadcom iProc I2C Driver\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nreplaces the bit-banged i2c-gpio provided i2c functionality\nwith the hardware in the SoC.\n\nDuring review of the MR32, Florian Fainelli pointed out that the\nSoC has a real I2C-controller. Furthermore, the connected pins\n(SDA and SCL) would line up perfectly for use. Back then I couldn't\nget it working though and I left it with i2c-gpio (which worked).\n\nNow we know the reason: the interrupt was incorrectly specified.\n(Hence, this patch depends on Florian Fainelli's\n\"ARM: dts: BCM5301X: Fix I2C controller interrupt\" patch).\n\nCc: Florian Fainelli <f.fainelli@gmail.com>\nCc: Rafał Miłecki <zajec5@gmail.com>\nCc: Matthew Hagan <mnhagan88@gmail.com>\nSigned-off-by: Christian Lamparter <chunkeey@gmail.com>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n arch/arm/boot/dts/bcm53016-meraki-mr32.dts | 62 ++++++++++------------\n 1 file changed, 28 insertions(+), 34 deletions(-)\n\n--- a/arch/arm/boot/dts/bcm53016-meraki-mr32.dts\n+++ b/arch/arm/boot/dts/bcm53016-meraki-mr32.dts\n@@ -84,40 +84,6 @@\n \t\t\tmax-brightness = <255>;\n \t\t};\n \t};\n-\n-\ti2c {\n-\t\t/*\n-\t\t * The platform provided I2C does not budge.\n-\t\t * This is a replacement until I can figure\n-\t\t * out what are the missing bits...\n-\t\t */\n-\n-\t\tcompatible = \"i2c-gpio\";\n-\t\tsda-gpios = <&chipcommon 5 GPIO_ACTIVE_HIGH>;\n-\t\tscl-gpios = <&chipcommon 4 GPIO_ACTIVE_HIGH>;\n-\t\ti2c-gpio,delay-us = <10>; /* close to 100 kHz */\n-\t\t#address-cells = <1>;\n-\t\t#size-cells = <0>;\n-\n-\t\tcurrent_sense: ina219@45 {\n-\t\t\tcompatible = \"ti,ina219\";\n-\t\t\treg = <0x45>;\n-\t\t\tshunt-resistor = <60000>; /* = 60 mOhms */\n-\t\t};\n-\n-\t\teeprom: eeprom@50 {\n-\t\t\tcompatible = \"atmel,24c64\";\n-\t\t\treg = <0x50>;\n-\t\t\tpagesize = <32>;\n-\t\t\tread-only;\n-\t\t\t#address-cells = <1>;\n-\t\t\t#size-cells = <1>;\n-\n-\t\t\tmac_address: mac-address@66 {\n-\t\t\t\treg = <0x66 0x6>;\n-\t\t\t};\n-\t\t};\n-\t};\n };\n \n &uart0 {\n@@ -250,3 +216,31 @@\n \t\t};\n \t};\n };\n+\n+&i2c0 {\n+\tstatus = \"okay\";\n+\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pinmux_i2c>;\n+\n+\tclock-frequency = <100000>;\n+\n+\tcurrent_sense: ina219@45 {\n+\t\tcompatible = \"ti,ina219\";\n+\t\treg = <0x45>;\n+\t\tshunt-resistor = <60000>; /* = 60 mOhms */\n+\t};\n+\n+\teeprom: eeprom@50 {\n+\t\tcompatible = \"atmel,24c64\";\n+\t\treg = <0x50>;\n+\t\tpagesize = <32>;\n+\t\tread-only;\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <1>;\n+\n+\t\tmac_address: mac-address@66 {\n+\t\t\treg = <0x66 0x6>;\n+\t\t};\n+\t};\n+};\n"
  },
  {
    "path": "target/linux/bcm53xx/patches-5.10/034-v5.17-0005-ARM-dts-BCM5301X-update-CRU-block-description.patch",
    "content": "From 31fd9b79dc580301c53a001482755ba7e88c2809 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Fri, 29 Oct 2021 18:05:23 +0200\nSubject: [PATCH] ARM: dts: BCM5301X: update CRU block description\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nThis describes CRU in a way matching documentation and fixes:\n\narch/arm/boot/dts/bcm4708-asus-rt-ac56u.dt.yaml: cru@100: $nodename:0: 'cru@100' does not match '^([a-z][a-z0-9\\\\-]+-bus|bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$'\n        From schema: /lib/python3.6/site-packages/dtschema/schemas/simple-bus.yaml\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n arch/arm/boot/dts/bcm5301x.dtsi | 13 +++++++++----\n 1 file changed, 9 insertions(+), 4 deletions(-)\n\n--- a/arch/arm/boot/dts/bcm5301x.dtsi\n+++ b/arch/arm/boot/dts/bcm5301x.dtsi\n@@ -423,14 +423,14 @@\n \t\t#address-cells = <1>;\n \t\t#size-cells = <1>;\n \n-\t\tcru@100 {\n-\t\t\tcompatible = \"simple-bus\";\n+\t\tcru-bus@100 {\n+\t\t\tcompatible = \"brcm,ns-cru\", \"simple-mfd\";\n \t\t\treg = <0x100 0x1a4>;\n \t\t\tranges;\n \t\t\t#address-cells = <1>;\n \t\t\t#size-cells = <1>;\n \n-\t\t\tlcpll0: lcpll0@100 {\n+\t\t\tlcpll0: clock-controller@100 {\n \t\t\t\t#clock-cells = <1>;\n \t\t\t\tcompatible = \"brcm,nsp-lcpll0\";\n \t\t\t\treg = <0x100 0x14>;\n@@ -439,7 +439,7 @@\n \t\t\t\t\t\t     \"sdio\", \"ddr_phy\";\n \t\t\t};\n \n-\t\t\tgenpll: genpll@140 {\n+\t\t\tgenpll: clock-controller@140 {\n \t\t\t\t#clock-cells = <1>;\n \t\t\t\tcompatible = \"brcm,nsp-genpll\";\n \t\t\t\treg = <0x140 0x24>;\n@@ -450,6 +450,11 @@\n \t\t\t\t\t\t     \"sata1\", \"sata2\";\n \t\t\t};\n \n+\t\t\tsyscon@180 {\n+\t\t\t\tcompatible = \"brcm,cru-clkset\", \"syscon\";\n+\t\t\t\treg = <0x180 0x4>;\n+\t\t\t};\n+\n \t\t\tpinctrl: pin-controller@1c0 {\n \t\t\t\tcompatible = \"brcm,bcm4708-pinmux\";\n \t\t\t\treg = <0x1c0 0x24>;\n"
  },
  {
    "path": "target/linux/bcm53xx/patches-5.10/034-v5.17-0006-ARM-dts-BCM5301X-use-non-deprecated-USB-2.0-PHY-bind.patch",
    "content": "From 1a46061a2a4130a08841941ce6dcaa32be2ce312 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Tue, 23 Nov 2021 10:03:33 +0100\nSubject: [PATCH] ARM: dts: BCM5301X: use non-deprecated USB 2.0 PHY binding\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nThe new binding covers a single reg and uses syscon to reference shared\nregister.\n\nReferences: 55b9b741712d (\"dt-bindings: phy: brcm,ns-usb2-phy: bind just a PHY block\")\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n arch/arm/boot/dts/bcm5301x.dtsi | 20 ++++++++++----------\n 1 file changed, 10 insertions(+), 10 deletions(-)\n\n--- a/arch/arm/boot/dts/bcm5301x.dtsi\n+++ b/arch/arm/boot/dts/bcm5301x.dtsi\n@@ -148,15 +148,6 @@\n \t\t};\n \t};\n \n-\tusb2_phy: usb2-phy@1800c000 {\n-\t\tcompatible = \"brcm,ns-usb2-phy\";\n-\t\treg = <0x1800c000 0x1000>;\n-\t\treg-names = \"dmu\";\n-\t\t#phy-cells = <0>;\n-\t\tclocks = <&genpll BCM_NSP_GENPLL_USB_PHY_REF_CLK>;\n-\t\tclock-names = \"phy-ref-clk\";\n-\t};\n-\n \taxi@18000000 {\n \t\tcompatible = \"brcm,bus-axi\";\n \t\treg = <0x18000000 0x1000>;\n@@ -450,7 +441,16 @@\n \t\t\t\t\t\t     \"sata1\", \"sata2\";\n \t\t\t};\n \n-\t\t\tsyscon@180 {\n+\t\t\tusb2_phy: phy@164 {\n+\t\t\t\tcompatible = \"brcm,ns-usb2-phy\";\n+\t\t\t\treg = <0x164 0x4>;\n+\t\t\t\tbrcm,syscon-clkset = <&cru_clkset>;\n+\t\t\t\tclocks = <&genpll BCM_NSP_GENPLL_USB_PHY_REF_CLK>;\n+\t\t\t\tclock-names = \"phy-ref-clk\";\n+\t\t\t\t#phy-cells = <0>;\n+\t\t\t};\n+\n+\t\t\tcru_clkset: syscon@180 {\n \t\t\t\tcompatible = \"brcm,cru-clkset\", \"syscon\";\n \t\t\t\treg = <0x180 0x4>;\n \t\t\t};\n"
  },
  {
    "path": "target/linux/bcm53xx/patches-5.10/034-v5.17-0007-ARM-dts-NSP-Fixed-iProc-PCIe-MSI-sub-node.patch",
    "content": "From 69c4e53bdd055ecc27761f6971a50c631ff9072e Mon Sep 17 00:00:00 2001\nFrom: Florian Fainelli <f.fainelli@gmail.com>\nDate: Thu, 2 Dec 2021 15:16:27 -0800\nSubject: [PATCH] ARM: dts: NSP: Fixed iProc PCIe MSI sub-node\n\nRename the msi controller unit name to 'msi' to avoid collisions with\nthe 'msi-controller' boolean property.\n\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n arch/arm/boot/dts/bcm-nsp.dtsi | 6 +++---\n 1 file changed, 3 insertions(+), 3 deletions(-)\n\n--- a/arch/arm/boot/dts/bcm-nsp.dtsi\n+++ b/arch/arm/boot/dts/bcm-nsp.dtsi\n@@ -587,7 +587,7 @@\n \t\tstatus = \"disabled\";\n \n \t\tmsi-parent = <&msi0>;\n-\t\tmsi0: msi-controller {\n+\t\tmsi0: msi {\n \t\t\tcompatible = \"brcm,iproc-msi\";\n \t\t\tmsi-controller;\n \t\t\tinterrupt-parent = <&gic>;\n@@ -624,7 +624,7 @@\n \t\tstatus = \"disabled\";\n \n \t\tmsi-parent = <&msi1>;\n-\t\tmsi1: msi-controller {\n+\t\tmsi1: msi {\n \t\t\tcompatible = \"brcm,iproc-msi\";\n \t\t\tmsi-controller;\n \t\t\tinterrupt-parent = <&gic>;\n@@ -661,7 +661,7 @@\n \t\tstatus = \"disabled\";\n \n \t\tmsi-parent = <&msi2>;\n-\t\tmsi2: msi-controller {\n+\t\tmsi2: msi {\n \t\t\tcompatible = \"brcm,iproc-msi\";\n \t\t\tmsi-controller;\n \t\t\tinterrupt-parent = <&gic>;\n"
  },
  {
    "path": "target/linux/bcm53xx/patches-5.10/034-v5.17-0008-ARM-dts-NSP-Rename-SATA-unit-name.patch",
    "content": "From 9a68c53f875e88edd3403c001ad85f4ac0ed3486 Mon Sep 17 00:00:00 2001\nFrom: Florian Fainelli <f.fainelli@gmail.com>\nDate: Tue, 7 Dec 2021 10:19:09 -0800\nSubject: [PATCH] ARM: dts: NSP: Rename SATA unit name\n\nRename the SATA controller unit name from ahci to sata in preparation\nfor adding the Broadcom SATA3 controller YAML binding which will bring\nvalidation.\n\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n arch/arm/boot/dts/bcm-nsp.dtsi | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/arch/arm/boot/dts/bcm-nsp.dtsi\n+++ b/arch/arm/boot/dts/bcm-nsp.dtsi\n@@ -534,7 +534,7 @@\n \t\t\t};\n \t\t};\n \n-\t\tsata: ahci@41000 {\n+\t\tsata: sata@41000 {\n \t\t\tcompatible = \"brcm,bcm-nsp-ahci\";\n \t\t\treg-names = \"ahci\", \"top-ctrl\";\n \t\t\treg = <0x41000 0x1000>, <0x40020 0x1c>;\n"
  },
  {
    "path": "target/linux/bcm53xx/patches-5.10/034-v5.17-0009-ARM-dts-BCM5301X-correct-RX-delay-and-enable-flow-co.patch",
    "content": "From 5e33f1c4a7cb914a003a304ab8eef705b17aabb7 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>\nDate: Fri, 17 Dec 2021 00:03:19 +0800\nSubject: [PATCH] ARM: dts: BCM5301X: correct RX delay and enable flow control\n on Asus RT-AC88U\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nThe current 'rx-internal-delay-ps' property value on the Realtek switch\nnode, 2000, will be divided by 300, resulting in 6.66, which will be\nrounded to the closest step value, 7. Change it to 2100 to be accurate.\nSee ef136837aaf6 (\"net: dsa: rtl8365mb: set RGMII RX delay in steps of\n0.3 ns\") for reference.\n\nFlow control needs to be enabled on both sides of the internal and\nexternal switch. It is already enabled on the CPU port of the Realtek\nswitch so we also enable it on the external switch port of the Broadcom\nswitch as well.\n\nSigned-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts | 3 ++-\n 1 file changed, 2 insertions(+), 1 deletion(-)\n\n--- a/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts\n+++ b/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts\n@@ -138,7 +138,7 @@\n \t\t\t\tethernet = <&sw0_p5>;\n \t\t\t\tphy-mode = \"rgmii\";\n \t\t\t\ttx-internal-delay-ps = <2000>;\n-\t\t\t\trx-internal-delay-ps = <2000>;\n+\t\t\t\trx-internal-delay-ps = <2100>;\n \n \t\t\t\tfixed-link {\n \t\t\t\t\tspeed = <1000>;\n@@ -213,6 +213,7 @@\n \t\t\tfixed-link {\n \t\t\t\tspeed = <1000>;\n \t\t\t\tfull-duplex;\n+\t\t\t\tpause;\n \t\t\t};\n \t\t};\n \n"
  },
  {
    "path": "target/linux/bcm53xx/patches-5.10/034-v5.17-0010-Revert-ARM-dts-BCM5301X-define-RTL8365MB-switch-on-A.patch",
    "content": "From 8b0c59c622dc4dab970ec63264fb5b152944ac80 Mon Sep 17 00:00:00 2001\nFrom: Arnd Bergmann <arnd@arndb.de>\nDate: Thu, 23 Dec 2021 00:17:17 +0100\nSubject: [PATCH] Revert \"ARM: dts: BCM5301X: define RTL8365MB switch on Asus\n RT-AC88U\"\n\nThis reverts commit 3d2d52a0d1835b56f6bd67d268f6c39df0e41692, it caused\na build regression:\n\narch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts:109.4-14: Warning (reg_format): /switch/ports:reg: property has invalid length (4 bytes) (#address-cells == 2, #size-cells == 1)\narch/arm/boot/dts/bcm47094-asus-rt-ac88u.dtb: Warning (pci_device_reg): Failed prerequisite 'reg_format'\narch/arm/boot/dts/bcm47094-asus-rt-ac88u.dtb: Warning (pci_device_bus_num): Failed prerequisite 'reg_format'\narch/arm/boot/dts/bcm47094-asus-rt-ac88u.dtb: Warning (i2c_bus_reg): Failed prerequisite 'reg_format'\narch/arm/boot/dts/bcm47094-asus-rt-ac88u.dtb: Warning (spi_bus_reg): Failed prerequisite 'reg_format'\narch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts:106.9-149.5: Warning (avoid_default_addr_size): /switch/ports: Relying on default #address-cells value\narch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts:106.9-149.5: Warning (avoid_default_addr_size): /switch/ports: Relying on default #size-cells value\n\nReported-by: Stephen Rothwell <sfr@canb.auug.org.au>\nSigned-off-by: Arnd Bergmann <arnd@arndb.de>\n---\n arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts | 77 --------------------\n 1 file changed, 77 deletions(-)\n\n--- a/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts\n+++ b/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts\n@@ -93,83 +93,6 @@\n \t\t\tgpios = <&chipcommon 4 GPIO_ACTIVE_LOW>;\n \t\t};\n \t};\n-\n-\tswitch {\n-\t\tcompatible = \"realtek,rtl8365mb\";\n-\t\t/* 7 = MDIO (has input reads), 6 = MDC (clock, output only) */\n-\t\tmdc-gpios = <&chipcommon 6 GPIO_ACTIVE_HIGH>;\n-\t\tmdio-gpios = <&chipcommon 7 GPIO_ACTIVE_HIGH>;\n-\t\treset-gpios = <&chipcommon 10 GPIO_ACTIVE_LOW>;\n-\t\trealtek,disable-leds;\n-\t\tdsa,member = <1 0>;\n-\n-\t\tports {\n-\t\t\t#address-cells = <1>;\n-\t\t\t#size-cells = <0>;\n-\t\t\treg = <0>;\n-\n-\t\t\tport@0 {\n-\t\t\t\treg = <0>;\n-\t\t\t\tlabel = \"lan5\";\n-\t\t\t\tphy-handle = <&ethphy0>;\n-\t\t\t};\n-\n-\t\t\tport@1 {\n-\t\t\t\treg = <1>;\n-\t\t\t\tlabel = \"lan6\";\n-\t\t\t\tphy-handle = <&ethphy1>;\n-\t\t\t};\n-\n-\t\t\tport@2 {\n-\t\t\t\treg = <2>;\n-\t\t\t\tlabel = \"lan7\";\n-\t\t\t\tphy-handle = <&ethphy2>;\n-\t\t\t};\n-\n-\t\t\tport@3 {\n-\t\t\t\treg = <3>;\n-\t\t\t\tlabel = \"lan8\";\n-\t\t\t\tphy-handle = <&ethphy3>;\n-\t\t\t};\n-\n-\t\t\tport@6 {\n-\t\t\t\treg = <6>;\n-\t\t\t\tlabel = \"cpu\";\n-\t\t\t\tethernet = <&sw0_p5>;\n-\t\t\t\tphy-mode = \"rgmii\";\n-\t\t\t\ttx-internal-delay-ps = <2000>;\n-\t\t\t\trx-internal-delay-ps = <2100>;\n-\n-\t\t\t\tfixed-link {\n-\t\t\t\t\tspeed = <1000>;\n-\t\t\t\t\tfull-duplex;\n-\t\t\t\t\tpause;\n-\t\t\t\t};\n-\t\t\t};\n-\t\t};\n-\n-\t\tmdio {\n-\t\t\tcompatible = \"realtek,smi-mdio\";\n-\t\t\t#address-cells = <1>;\n-\t\t\t#size-cells = <0>;\n-\n-\t\t\tethphy0: ethernet-phy@0 {\n-\t\t\t\treg = <0>;\n-\t\t\t};\n-\n-\t\t\tethphy1: ethernet-phy@1 {\n-\t\t\t\treg = <1>;\n-\t\t\t};\n-\n-\t\t\tethphy2: ethernet-phy@2 {\n-\t\t\t\treg = <2>;\n-\t\t\t};\n-\n-\t\t\tethphy3: ethernet-phy@3 {\n-\t\t\t\treg = <3>;\n-\t\t\t};\n-\t\t};\n-\t};\n };\n \n &srab {\n"
  },
  {
    "path": "target/linux/bcm53xx/patches-5.10/035-v5.18-0001-ARM-dts-BCM5301X-define-RTL8365MB-switch-on-Asus-RT-.patch",
    "content": "From 441d531ec9b766f49e01c107a3043235daa4493f Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>\nDate: Sun, 2 Jan 2022 23:33:04 +0300\nSubject: [PATCH] ARM: dts: BCM5301X: define RTL8365MB switch on Asus RT-AC88U\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nDefine the Realtek RTL8365MB switch without interrupt support on the device\ntree of Asus RT-AC88U.\n\nSigned-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>\nAcked-by: Alvin Šipraga <alsi@bang-olufsen.dk>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts | 76 ++++++++++++++++++++\n 1 file changed, 76 insertions(+)\n\n--- a/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts\n+++ b/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts\n@@ -93,6 +93,82 @@\n \t\t\tgpios = <&chipcommon 4 GPIO_ACTIVE_LOW>;\n \t\t};\n \t};\n+\n+\tswitch {\n+\t\tcompatible = \"realtek,rtl8365mb\";\n+\t\t/* 7 = MDIO (has input reads), 6 = MDC (clock, output only) */\n+\t\tmdc-gpios = <&chipcommon 6 GPIO_ACTIVE_HIGH>;\n+\t\tmdio-gpios = <&chipcommon 7 GPIO_ACTIVE_HIGH>;\n+\t\treset-gpios = <&chipcommon 10 GPIO_ACTIVE_LOW>;\n+\t\trealtek,disable-leds;\n+\t\tdsa,member = <1 0>;\n+\n+\t\tports {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tport@0 {\n+\t\t\t\treg = <0>;\n+\t\t\t\tlabel = \"lan5\";\n+\t\t\t\tphy-handle = <&ethphy0>;\n+\t\t\t};\n+\n+\t\t\tport@1 {\n+\t\t\t\treg = <1>;\n+\t\t\t\tlabel = \"lan6\";\n+\t\t\t\tphy-handle = <&ethphy1>;\n+\t\t\t};\n+\n+\t\t\tport@2 {\n+\t\t\t\treg = <2>;\n+\t\t\t\tlabel = \"lan7\";\n+\t\t\t\tphy-handle = <&ethphy2>;\n+\t\t\t};\n+\n+\t\t\tport@3 {\n+\t\t\t\treg = <3>;\n+\t\t\t\tlabel = \"lan8\";\n+\t\t\t\tphy-handle = <&ethphy3>;\n+\t\t\t};\n+\n+\t\t\tport@6 {\n+\t\t\t\treg = <6>;\n+\t\t\t\tlabel = \"cpu\";\n+\t\t\t\tethernet = <&sw0_p5>;\n+\t\t\t\tphy-mode = \"rgmii\";\n+\t\t\t\ttx-internal-delay-ps = <2000>;\n+\t\t\t\trx-internal-delay-ps = <2100>;\n+\n+\t\t\t\tfixed-link {\n+\t\t\t\t\tspeed = <1000>;\n+\t\t\t\t\tfull-duplex;\n+\t\t\t\t\tpause;\n+\t\t\t\t};\n+\t\t\t};\n+\t\t};\n+\n+\t\tmdio {\n+\t\t\tcompatible = \"realtek,smi-mdio\";\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tethphy0: ethernet-phy@0 {\n+\t\t\t\treg = <0>;\n+\t\t\t};\n+\n+\t\t\tethphy1: ethernet-phy@1 {\n+\t\t\t\treg = <1>;\n+\t\t\t};\n+\n+\t\t\tethphy2: ethernet-phy@2 {\n+\t\t\t\treg = <2>;\n+\t\t\t};\n+\n+\t\t\tethphy3: ethernet-phy@3 {\n+\t\t\t\treg = <3>;\n+\t\t\t};\n+\t\t};\n+\t};\n };\n \n &srab {\n"
  },
  {
    "path": "target/linux/bcm53xx/patches-5.10/035-v5.18-0002-ARM-dts-NSP-MX6X-get-mac-address-from-eeprom.patch",
    "content": "From 66848aff05f669e95795b5f3a163f4762781333e Mon Sep 17 00:00:00 2001\nFrom: Matthew Hagan <mnhagan88@gmail.com>\nDate: Wed, 23 Feb 2022 23:50:39 +0000\nSubject: [PATCH] ARM: dts: NSP: MX6X: get mac-address from eeprom\n\nThe MAC address on the MX64/MX65 series is located on the AT24 EEPROM.\nThis is the same as other Meraki devices such as the MR32 [1].\n\n[1] https://lore.kernel.org/linux-arm-kernel/fa8271d02ef74a687f365cebe5c55ec846963ab7.1631986106.git.chunkeey@gmail.com/\n\nSigned-off-by: Matthew Hagan <mnhagan88@gmail.com>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n arch/arm/boot/dts/bcm958625-meraki-mx6x-common.dtsi | 8 ++++++++\n 1 file changed, 8 insertions(+)\n\n--- a/arch/arm/boot/dts/bcm958625-meraki-mx6x-common.dtsi\n+++ b/arch/arm/boot/dts/bcm958625-meraki-mx6x-common.dtsi\n@@ -39,6 +39,8 @@\n \n &amac2 {\n \tstatus = \"okay\";\n+\tnvmem-cells = <&mac_address>;\n+\tnvmem-cell-names = \"mac-address\";\n };\n \n &ehci0 {\n@@ -53,6 +55,12 @@\n \t\treg = <0x50>;\n \t\tpagesize = <32>;\n \t\tread-only;\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <1>;\n+\n+\t\tmac_address: mac-address@66 {\n+\t\t\treg = <0x66 0x6>;\n+\t\t};\n \t};\n };\n \n"
  },
  {
    "path": "target/linux/bcm53xx/patches-5.10/035-v5.18-0003-ARM-dts-NSP-MX6X-correct-LED-function-types.patch",
    "content": "From 482c85c7fc95c572d368b2214b9e9d2c4a2e5789 Mon Sep 17 00:00:00 2001\nFrom: Matthew Hagan <mnhagan88@gmail.com>\nDate: Wed, 23 Feb 2022 23:50:40 +0000\nSubject: [PATCH] ARM: dts: NSP: MX6X: correct LED function types\n\nCurrently, the amber LED will remain always on. This is due to a\nmisinterpretation of the LED sub-node properties, where-by \"default-state\"\nwas used to indicate the initial state when powering on the device. When in\nuse, however, this resulted in the amber LED always being on. Instead change\nthis to only indicate a fault state.\n\nAssign LED_FUNCTION_POWER to the green PWM LED.\n\nThese changes bring the MX64/65 in line with the MR32's devicetree.\n\nSigned-off-by: Matthew Hagan <mnhagan88@gmail.com>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi       | 3 +--\n arch/arm/boot/dts/bcm958625-meraki-kingpin.dtsi     | 3 +--\n arch/arm/boot/dts/bcm958625-meraki-mx6x-common.dtsi | 2 +-\n 3 files changed, 3 insertions(+), 5 deletions(-)\n\n--- a/arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi\n+++ b/arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi\n@@ -57,10 +57,9 @@\n \n \t\tled-4 {\n \t\t\t/* amber:power */\n-\t\t\tfunction = LED_FUNCTION_POWER;\n+\t\t\tfunction = LED_FUNCTION_FAULT;\n \t\t\tcolor = <LED_COLOR_ID_AMBER>;\n \t\t\tgpios = <&gpioa 3 GPIO_ACTIVE_HIGH>;\n-\t\t\tdefault-state = \"on\";\n \t\t};\n \n \t\tled-5 {\n--- a/arch/arm/boot/dts/bcm958625-meraki-kingpin.dtsi\n+++ b/arch/arm/boot/dts/bcm958625-meraki-kingpin.dtsi\n@@ -106,10 +106,9 @@\n \n \t\tled-a {\n \t\t\t/* amber:power */\n-\t\t\tfunction = LED_FUNCTION_POWER;\n+\t\t\tfunction = LED_FUNCTION_FAULT;\n \t\t\tcolor = <LED_COLOR_ID_AMBER>;\n \t\t\tgpios = <&gpioa 0 GPIO_ACTIVE_LOW>;\n-\t\t\tdefault-state = \"on\";\n \t\t};\n \n \t\tled-b {\n--- a/arch/arm/boot/dts/bcm958625-meraki-mx6x-common.dtsi\n+++ b/arch/arm/boot/dts/bcm958625-meraki-mx6x-common.dtsi\n@@ -22,7 +22,7 @@\n \t\t};\n \n \t\tled-2 {\n-\t\t\tfunction = LED_FUNCTION_INDICATOR;\n+\t\t\tfunction = LED_FUNCTION_POWER;\n \t\t\tcolor = <LED_COLOR_ID_GREEN>;\n \t\t\tpwms = <&pwm 2 50000>;\n \t\t\tmax-brightness = <255>;\n"
  },
  {
    "path": "target/linux/bcm53xx/patches-5.10/035-v5.18-0004-ARM-dts-BCM5301X-Add-Ethernet-MAC-address-to-Luxul-X.patch",
    "content": "From c8442f0fb09ca3d842b9b23d1d0650f649fd10f8 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Mon, 28 Feb 2022 10:52:07 +0100\nSubject: [PATCH] ARM: dts: BCM5301X: Add Ethernet MAC address to Luxul\n XWR-3150\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nLuxul XWR-3150 stores MAC as NVRAM variable. Add NVMEM cell for it and\nreference it in the Ethernet interface node.\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts | 8 ++++++++\n 1 file changed, 8 insertions(+)\n\n--- a/arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts\n+++ b/arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts\n@@ -25,6 +25,9 @@\n \tnvram@1eff0000 {\n \t\tcompatible = \"brcm,nvram\";\n \t\treg = <0x1eff0000 0x10000>;\n+\n+\t\tet0macaddr: et0macaddr {\n+\t\t};\n \t};\n \n \tleds {\n@@ -72,6 +75,11 @@\n \t};\n };\n \n+&gmac0 {\n+\tnvmem-cells = <&et0macaddr>;\n+\tnvmem-cell-names = \"mac-address\";\n+};\n+\n &usb3 {\n \tvcc-gpio = <&chipcommon 18 GPIO_ACTIVE_HIGH>;\n };\n"
  },
  {
    "path": "target/linux/bcm53xx/patches-5.10/070-v5.17-phy-bcm-ns-usb2-support-updated-DT-binding-with-PHY-.patch",
    "content": "From d3bc6269e21fc474763708e79c7a118740befb94 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Tue, 26 Oct 2021 11:37:16 +0200\nSubject: [PATCH] phy: bcm-ns-usb2: support updated DT binding with PHY reg\n space\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nUpdated DT binding maps just a PHY's register space instead of the whole\nDMU block. Accessing a common CRU reg is handled using syscon &\nregmap.\n\nThe old binding has been deprecated and remains supported as a fallback\nmethod.\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nLink: https://lore.kernel.org/r/20211026093716.5567-1-zajec5@gmail.com\nSigned-off-by: Vinod Koul <vkoul@kernel.org>\n---\n drivers/phy/broadcom/phy-bcm-ns-usb2.c | 52 +++++++++++++++++++++-----\n 1 file changed, 43 insertions(+), 9 deletions(-)\n\n--- a/drivers/phy/broadcom/phy-bcm-ns-usb2.c\n+++ b/drivers/phy/broadcom/phy-bcm-ns-usb2.c\n@@ -9,17 +9,23 @@\n #include <linux/clk.h>\n #include <linux/delay.h>\n #include <linux/err.h>\n+#include <linux/mfd/syscon.h>\n #include <linux/module.h>\n #include <linux/of_address.h>\n #include <linux/of_platform.h>\n #include <linux/phy/phy.h>\n #include <linux/platform_device.h>\n+#include <linux/regmap.h>\n #include <linux/slab.h>\n \n struct bcm_ns_usb2 {\n \tstruct device *dev;\n \tstruct clk *ref_clk;\n \tstruct phy *phy;\n+\tstruct regmap *clkset;\n+\tvoid __iomem *base;\n+\n+\t/* Deprecated binding */\n \tvoid __iomem *dmu;\n };\n \n@@ -27,7 +33,6 @@ static int bcm_ns_usb2_phy_init(struct p\n {\n \tstruct bcm_ns_usb2 *usb2 = phy_get_drvdata(phy);\n \tstruct device *dev = usb2->dev;\n-\tvoid __iomem *dmu = usb2->dmu;\n \tu32 ref_clk_rate, usb2ctl, usb_pll_ndiv, usb_pll_pdiv;\n \tint err = 0;\n \n@@ -44,7 +49,10 @@ static int bcm_ns_usb2_phy_init(struct p\n \t\tgoto err_clk_off;\n \t}\n \n-\tusb2ctl = readl(dmu + BCMA_DMU_CRU_USB2_CONTROL);\n+\tif (usb2->base)\n+\t\tusb2ctl = readl(usb2->base);\n+\telse\n+\t\tusb2ctl = readl(usb2->dmu + BCMA_DMU_CRU_USB2_CONTROL);\n \n \tif (usb2ctl & BCMA_DMU_CRU_USB2_CONTROL_USB_PLL_PDIV_MASK) {\n \t\tusb_pll_pdiv = usb2ctl;\n@@ -58,15 +66,24 @@ static int bcm_ns_usb2_phy_init(struct p\n \tusb_pll_ndiv = (1920000000 * usb_pll_pdiv) / ref_clk_rate;\n \n \t/* Unlock DMU PLL settings with some magic value */\n-\twritel(0x0000ea68, dmu + BCMA_DMU_CRU_CLKSET_KEY);\n+\tif (usb2->clkset)\n+\t\tregmap_write(usb2->clkset, 0, 0x0000ea68);\n+\telse\n+\t\twritel(0x0000ea68, usb2->dmu + BCMA_DMU_CRU_CLKSET_KEY);\n \n \t/* Write USB 2.0 PLL control setting */\n \tusb2ctl &= ~BCMA_DMU_CRU_USB2_CONTROL_USB_PLL_NDIV_MASK;\n \tusb2ctl |= usb_pll_ndiv << BCMA_DMU_CRU_USB2_CONTROL_USB_PLL_NDIV_SHIFT;\n-\twritel(usb2ctl, dmu + BCMA_DMU_CRU_USB2_CONTROL);\n+\tif (usb2->base)\n+\t\twritel(usb2ctl, usb2->base);\n+\telse\n+\t\twritel(usb2ctl, usb2->dmu + BCMA_DMU_CRU_USB2_CONTROL);\n \n \t/* Lock DMU PLL settings */\n-\twritel(0x00000000, dmu + BCMA_DMU_CRU_CLKSET_KEY);\n+\tif (usb2->clkset)\n+\t\tregmap_write(usb2->clkset, 0, 0x00000000);\n+\telse\n+\t\twritel(0x00000000, usb2->dmu + BCMA_DMU_CRU_CLKSET_KEY);\n \n err_clk_off:\n \tclk_disable_unprepare(usb2->ref_clk);\n@@ -91,11 +108,28 @@ static int bcm_ns_usb2_probe(struct plat\n \t\treturn -ENOMEM;\n \tusb2->dev = dev;\n \n-\tres = platform_get_resource_byname(pdev, IORESOURCE_MEM, \"dmu\");\n-\tusb2->dmu = devm_ioremap_resource(dev, res);\n-\tif (IS_ERR(usb2->dmu)) {\n-\t\tdev_err(dev, \"Failed to map DMU regs\\n\");\n-\t\treturn PTR_ERR(usb2->dmu);\n+\tif (of_find_property(dev->of_node, \"brcm,syscon-clkset\", NULL)) {\n+\t\tusb2->base = devm_platform_ioremap_resource(pdev, 0);\n+\t\tif (IS_ERR(usb2->base)) {\n+\t\t\tdev_err(dev, \"Failed to map control reg\\n\");\n+\t\t\treturn PTR_ERR(usb2->base);\n+\t\t}\n+\n+\t\tusb2->clkset = syscon_regmap_lookup_by_phandle(dev->of_node,\n+\t\t\t\t\t\t\t       \"brcm,syscon-clkset\");\n+\t\tif (IS_ERR(usb2->clkset)) {\n+\t\t\tdev_err(dev, \"Failed to lookup clkset regmap\\n\");\n+\t\t\treturn PTR_ERR(usb2->clkset);\n+\t\t}\n+\t} else {\n+\t\tres = platform_get_resource_byname(pdev, IORESOURCE_MEM, \"dmu\");\n+\t\tusb2->dmu = devm_ioremap_resource(dev, res);\n+\t\tif (IS_ERR(usb2->dmu)) {\n+\t\t\tdev_err(dev, \"Failed to map DMU regs\\n\");\n+\t\t\treturn PTR_ERR(usb2->dmu);\n+\t\t}\n+\n+\t\tdev_warn(dev, \"using deprecated DT binding\\n\");\n \t}\n \n \tusb2->ref_clk = devm_clk_get(dev, \"phy-ref-clk\");\n"
  },
  {
    "path": "target/linux/bcm53xx/patches-5.10/080-v5.13-0001-dt-bindings-nvmem-add-Broadcom-s-NVRAM.patch",
    "content": "From c39edb9f9dcb6c8a0ba0ebf5df9e0ac93ab94b82 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Fri, 5 Mar 2021 19:32:35 +0100\nSubject: [PATCH] dt-bindings: nvmem: add Broadcom's NVRAM\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nBroadcom's NVRAM structure contains device data and can be accessed\nusing I/O mapping.\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nReviewed-by: Rob Herring <robh@kernel.org>\nSigned-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>\n---\n .../devicetree/bindings/nvmem/brcm,nvram.yaml | 34 +++++++++++++++++++\n 1 file changed, 34 insertions(+)\n create mode 100644 Documentation/devicetree/bindings/nvmem/brcm,nvram.yaml\n\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/nvmem/brcm,nvram.yaml\n@@ -0,0 +1,34 @@\n+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)\n+%YAML 1.2\n+---\n+$id: http://devicetree.org/schemas/nvmem/brcm,nvram.yaml#\n+$schema: http://devicetree.org/meta-schemas/core.yaml#\n+\n+title: Broadcom's NVRAM\n+\n+description: |\n+  Broadcom's NVRAM is a structure containing device specific environment\n+  variables. It is used for storing device configuration, booting parameters\n+  and calibration data.\n+\n+  NVRAM can be accessed on Broadcom BCM47xx MIPS and Northstar ARM Cortex-A9\n+  devices usiong I/O mapped memory.\n+\n+maintainers:\n+  - Rafał Miłecki <rafal@milecki.pl>\n+\n+allOf:\n+  - $ref: \"nvmem.yaml#\"\n+\n+properties:\n+  compatible:\n+    const: brcm,nvram\n+\n+unevaluatedProperties: false\n+\n+examples:\n+  - |\n+    nvram@1eff0000 {\n+            compatible = \"brcm,nvram\";\n+            reg = <0x1eff0000 0x10000>;\n+    };\n"
  },
  {
    "path": "target/linux/bcm53xx/patches-5.10/080-v5.13-0002-nvmem-brcm_nvram-new-driver-exposing-Broadcom-s-NVRA.patch",
    "content": "From b152bbeb0282bfcf6f91d0d5befd7582c1c3fc23 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Fri, 5 Mar 2021 19:32:36 +0100\nSubject: [PATCH] nvmem: brcm_nvram: new driver exposing Broadcom's NVRAM\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nThis driver provides access to Broadcom's NVRAM.\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nSigned-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>\n---\n drivers/nvmem/Kconfig      |  9 +++++\n drivers/nvmem/Makefile     |  2 +\n drivers/nvmem/brcm_nvram.c | 78 ++++++++++++++++++++++++++++++++++++++\n 3 files changed, 89 insertions(+)\n create mode 100644 drivers/nvmem/brcm_nvram.c\n\n--- a/drivers/nvmem/Kconfig\n+++ b/drivers/nvmem/Kconfig\n@@ -270,4 +270,13 @@ config SPRD_EFUSE\n \t  This driver can also be built as a module. If so, the module\n \t  will be called nvmem-sprd-efuse.\n \n+\n+config NVMEM_BRCM_NVRAM\n+\ttristate \"Broadcom's NVRAM support\"\n+\tdepends on ARCH_BCM_5301X || COMPILE_TEST\n+\tdepends on HAS_IOMEM\n+\thelp\n+\t  This driver provides support for Broadcom's NVRAM that can be accessed\n+\t  using I/O mapping.\n+\n endif\n--- a/drivers/nvmem/Makefile\n+++ b/drivers/nvmem/Makefile\n@@ -55,3 +55,5 @@ obj-$(CONFIG_NVMEM_ZYNQMP)\t+= nvmem_zynq\n nvmem_zynqmp_nvmem-y\t\t:= zynqmp_nvmem.o\n obj-$(CONFIG_SPRD_EFUSE)\t+= nvmem_sprd_efuse.o\n nvmem_sprd_efuse-y\t\t:= sprd-efuse.o\n+obj-$(CONFIG_NVMEM_BRCM_NVRAM)\t+= nvmem_brcm_nvram.o\n+nvmem_brcm_nvram-y\t\t:= brcm_nvram.o\n--- /dev/null\n+++ b/drivers/nvmem/brcm_nvram.c\n@@ -0,0 +1,78 @@\n+// SPDX-License-Identifier: GPL-2.0-only\n+/*\n+ * Copyright (C) 2021 Rafał Miłecki <rafal@milecki.pl>\n+ */\n+\n+#include <linux/io.h>\n+#include <linux/mod_devicetable.h>\n+#include <linux/module.h>\n+#include <linux/nvmem-provider.h>\n+#include <linux/platform_device.h>\n+\n+struct brcm_nvram {\n+\tstruct device *dev;\n+\tvoid __iomem *base;\n+};\n+\n+static int brcm_nvram_read(void *context, unsigned int offset, void *val,\n+\t\t\t   size_t bytes)\n+{\n+\tstruct brcm_nvram *priv = context;\n+\tu8 *dst = val;\n+\n+\twhile (bytes--)\n+\t\t*dst++ = readb(priv->base + offset++);\n+\n+\treturn 0;\n+}\n+\n+static int brcm_nvram_probe(struct platform_device *pdev)\n+{\n+\tstruct nvmem_config config = {\n+\t\t.name = \"brcm-nvram\",\n+\t\t.reg_read = brcm_nvram_read,\n+\t};\n+\tstruct device *dev = &pdev->dev;\n+\tstruct resource *res;\n+\tstruct brcm_nvram *priv;\n+\n+\tpriv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);\n+\tif (!priv)\n+\t\treturn -ENOMEM;\n+\tpriv->dev = dev;\n+\n+\tres = platform_get_resource(pdev, IORESOURCE_MEM, 0);\n+\tpriv->base = devm_ioremap_resource(dev, res);\n+\tif (IS_ERR(priv->base))\n+\t\treturn PTR_ERR(priv->base);\n+\n+\tconfig.dev = dev;\n+\tconfig.priv = priv;\n+\tconfig.size = resource_size(res);\n+\n+\treturn PTR_ERR_OR_ZERO(devm_nvmem_register(dev, &config));\n+}\n+\n+static const struct of_device_id brcm_nvram_of_match_table[] = {\n+\t{ .compatible = \"brcm,nvram\", },\n+\t{},\n+};\n+\n+static struct platform_driver brcm_nvram_driver = {\n+\t.probe = brcm_nvram_probe,\n+\t.driver = {\n+\t\t.name = \"brcm_nvram\",\n+\t\t.of_match_table = brcm_nvram_of_match_table,\n+\t},\n+};\n+\n+static int __init brcm_nvram_init(void)\n+{\n+\treturn platform_driver_register(&brcm_nvram_driver);\n+}\n+\n+subsys_initcall_sync(brcm_nvram_init);\n+\n+MODULE_AUTHOR(\"Rafał Miłecki\");\n+MODULE_LICENSE(\"GPL\");\n+MODULE_DEVICE_TABLE(of, brcm_nvram_of_match_table);\n"
  },
  {
    "path": "target/linux/bcm53xx/patches-5.10/140-mtd-parsers-trx-parse-firmware-MTD-partitions-only.patch",
    "content": "From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Tue, 13 Apr 2021 18:25:20 +0200\nSubject: [PATCH] mtd: parsers: trx: parse \"firmware\" MTD partitions only\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nParsing every partition with \"compatible\" set to \"brcm,trx\" results in\nparsing both: firmware partition and failsafe partition on devices that\nimplement failsafe booting. This affects e.g. Linksys EA9500 which has:\n\npartition@200000 {\n\treg = <0x0200000 0x01d00000>;\n\tcompatible = \"linksys,ns-firmware\", \"brcm,trx\";\n};\n\npartition@1f00000 {\n\treg = <0x01f00000 0x01d00000>;\n\tcompatible = \"linksys,ns-firmware\", \"brcm,trx\";\n};\n\nCheck for MTD partition name \"firmware\" before parsing. Recently added\nofpart_linksys_ns.c creates \"firmware\" and \"failsafe\" depending on\nbootloader setup.\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\n---\n drivers/mtd/parsers/parser_trx.c | 4 ++++\n 1 file changed, 4 insertions(+)\n\n--- a/drivers/mtd/parsers/parser_trx.c\n+++ b/drivers/mtd/parsers/parser_trx.c\n@@ -92,6 +92,10 @@ static int parser_trx_parse(struct mtd_i\n \tif (err != 0 && err != -EINVAL)\n \t\tpr_err(\"failed to parse \\\"brcm,trx-magic\\\" DT attribute, using default: %d\\n\", err);\n \n+\t/* Don't parse any failsafe / backup partitions */\n+\tif (strcmp(mtd->name, \"firmware\"))\n+\t\treturn -EINVAL;\n+\n \tparts = kcalloc(TRX_PARSER_MAX_PARTS, sizeof(struct mtd_partition),\n \t\t\tGFP_KERNEL);\n \tif (!parts)\n"
  },
  {
    "path": "target/linux/bcm53xx/patches-5.10/180-usb-xhci-add-support-for-performing-fake-doorbell.patch",
    "content": "From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Sat, 1 Oct 2016 22:54:48 +0200\nSubject: [PATCH] usb: xhci: add support for performing fake doorbell\n\nBroadcom's Northstar XHCI controllers seem to need a special start\nprocedure to work correctly. There isn't any official documentation of\nthis, the problem is that controller doesn't detect any connected\ndevices with default setup. Moreover connecting USB device to controller\nthat doesn't run properly can cause SoC's watchdog issues.\n\nA workaround that was successfully tested on multiple devices is to\nperform a fake doorbell. This patch adds code for doing this and enables\nit on BCM4708 family.\n---\n drivers/usb/host/xhci-plat.c |  6 +++++\n drivers/usb/host/xhci.c      | 63 +++++++++++++++++++++++++++++++++++++++++---\n drivers/usb/host/xhci.h      |  1 +\n 3 files changed, 67 insertions(+), 3 deletions(-)\n\n--- a/drivers/usb/host/xhci-plat.c\n+++ b/drivers/usb/host/xhci-plat.c\n@@ -77,6 +77,8 @@ static int xhci_priv_resume_quirk(struct\n static void xhci_plat_quirks(struct device *dev, struct xhci_hcd *xhci)\n {\n \tstruct xhci_plat_priv *priv = xhci_to_priv(xhci);\n+\tstruct platform_device*pdev = to_platform_device(dev);\n+\tstruct device_node *node = pdev->dev.of_node;\n \n \t/*\n \t * As of now platform drivers don't provide MSI support so we ensure\n@@ -84,6 +86,9 @@ static void xhci_plat_quirks(struct devi\n \t * dev struct in order to setup MSI\n \t */\n \txhci->quirks |= XHCI_PLAT | priv->quirks;\n+\n+\tif (node && of_machine_is_compatible(\"brcm,bcm4708\"))\n+\t\txhci->quirks |= XHCI_FAKE_DOORBELL;\n }\n \n /* called during probe() after chip reset completes */\n--- a/drivers/usb/host/xhci.c\n+++ b/drivers/usb/host/xhci.c\n@@ -156,6 +156,49 @@ int xhci_start(struct xhci_hcd *xhci)\n \treturn ret;\n }\n \n+/**\n+ * xhci_fake_doorbell - Perform a fake doorbell on a specified slot\n+ *\n+ * Some controllers require a fake doorbell to start correctly. Without that\n+ * they simply don't detect any devices.\n+ */\n+static int xhci_fake_doorbell(struct xhci_hcd *xhci, int slot_id)\n+{\n+\tu32 temp;\n+\n+\t/* Alloc a virt device for that slot */\n+\tif (!xhci_alloc_virt_device(xhci, slot_id, NULL, GFP_NOIO)) {\n+\t\txhci_warn(xhci, \"Could not allocate xHCI USB device data structures\\n\");\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\t/* Ring fake doorbell for slot_id ep 0 */\n+\txhci_ring_ep_doorbell(xhci, slot_id, 0, 0);\n+\tusleep_range(1000, 1500);\n+\n+\t/* Read the status to check if HSE is set or not */\n+\ttemp = readl(&xhci->op_regs->status);\n+\n+\t/* Clear HSE if set */\n+\tif (temp & STS_FATAL) {\n+\t\txhci_dbg(xhci, \"HSE problem detected, status: 0x%08x\\n\", temp);\n+\t\ttemp &= ~0x1fff;\n+\t\ttemp |= STS_FATAL;\n+\t\twritel(temp, &xhci->op_regs->status);\n+\t\tusleep_range(1000, 1500);\n+\t\treadl(&xhci->op_regs->status);\n+\t}\n+\n+\t/* Free virt device */\n+\txhci_free_virt_device(xhci, slot_id);\n+\n+\t/* We're done if controller is already running */\n+\tif (readl(&xhci->op_regs->command) & CMD_RUN)\n+\t\treturn 0;\n+\n+\treturn xhci_start(xhci);\n+}\n+\n /*\n  * Reset a halted HC.\n  *\n@@ -606,10 +649,20 @@ static int xhci_init(struct usb_hcd *hcd\n \n static int xhci_run_finished(struct xhci_hcd *xhci)\n {\n-\tif (xhci_start(xhci)) {\n-\t\txhci_halt(xhci);\n-\t\treturn -ENODEV;\n+\tint err;\n+\n+\terr = xhci_start(xhci);\n+\tif (err) {\n+\t\terr = -ENODEV;\n+\t\tgoto err_halt;\n \t}\n+\n+\tif (xhci->quirks & XHCI_FAKE_DOORBELL) {\n+\t\terr = xhci_fake_doorbell(xhci, 1);\n+\t\tif (err)\n+\t\t\tgoto err_halt;\n+\t}\n+\n \txhci->shared_hcd->state = HC_STATE_RUNNING;\n \txhci->cmd_ring_state = CMD_RING_STATE_RUNNING;\n \n@@ -619,6 +672,10 @@ static int xhci_run_finished(struct xhci\n \txhci_dbg_trace(xhci, trace_xhci_dbg_init,\n \t\t\t\"Finished xhci_run for USB3 roothub\");\n \treturn 0;\n+\n+err_halt:\n+\txhci_halt(xhci);\n+\treturn err;\n }\n \n /*\n--- a/drivers/usb/host/xhci.h\n+++ b/drivers/usb/host/xhci.h\n@@ -1888,6 +1888,7 @@ struct xhci_hcd {\n #define XHCI_SG_TRB_CACHE_SIZE_QUIRK\tBIT_ULL(39)\n #define XHCI_NO_SOFT_RETRY\tBIT_ULL(40)\n #define XHCI_EP_CTX_BROKEN_DCS\tBIT_ULL(42)\n+#define XHCI_FAKE_DOORBELL\tBIT_ULL(44)\n \n \tunsigned int\t\tnum_active_eps;\n \tunsigned int\t\tlimit_active_eps;\n"
  },
  {
    "path": "target/linux/bcm53xx/patches-5.10/300-ARM-BCM5301X-Disable-MMU-and-Dcache-during-decompres.patch",
    "content": "From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Wed, 24 Sep 2014 22:14:07 +0200\nSubject: [PATCH] ARM: BCM5301X: Disable MMU and Dcache during decompression\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nBroadcom devices have broken CFE (bootloader) that leaves hardware in an\ninvalid state. It causes problems with booting Linux. On Northstar\ndevices kernel was randomly hanging in ~25% of tries during early init.\nHangs used to happen at random places in the start_kernel. On BCM53573\nkernel doesn't even seem to start booting.\n\nTo workaround this problem we need to do following very early:\n1) Clear 2 following bits in the SCTLR register:\n#define CR_M    (1 << 0)        /* MMU enable */\n#define CR_C    (1 << 2)        /* Dcache enable */\n2) Flush the whole D-cache\n3) Disable L2 cache\n\nUnfortunately this patch is not upstreamable as it does above things\nunconditionally. We can't check if we are running on Broadcom platform\nin any safe way and doing such hacks with ARCH_MULTI_V7 is unacceptable\nas it could break other devices support.\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\n---\n\n--- a/arch/arm/boot/compressed/Makefile\n+++ b/arch/arm/boot/compressed/Makefile\n@@ -35,6 +35,11 @@ ifeq ($(CONFIG_ARCH_ACORN),y)\n OBJS\t\t+= ll_char_wr.o font.o\n endif\n \n+ifeq ($(CONFIG_ARCH_BCM_5301X),y)\n+OBJS\t\t+= head-bcm_5301x-mpcore.o\n+OBJS\t\t+= cache-v7-min.o\n+endif\n+\n ifeq ($(CONFIG_ARCH_SA1100),y)\n OBJS\t\t+= head-sa1100.o\n endif\n--- /dev/null\n+++ b/arch/arm/boot/compressed/head-bcm_5301x-mpcore.S\n@@ -0,0 +1,37 @@\n+/*\n+ *\n+ * Platform specific tweaks.  This is merged into head.S by the linker.\n+ *\n+ */\n+\n+#include <linux/linkage.h>\n+#include <asm/assembler.h>\n+#include <asm/cp15.h>\n+\n+\t\t.section        \".start\", \"ax\"\n+\n+/*\n+ * This code section is spliced into the head code by the linker\n+ */\n+\n+__plat_uncompress_start:\n+\n+\t@ Preserve r8/r7 i.e. kernel entry values\n+\tmov\tr12, r8\n+\n+\t@ Clear MMU enable and Dcache enable bits\n+\tmrc\tp15, 0, r0, c1, c0, 0\t\t@ Read SCTLR\n+\tbic\tr0, #CR_C|CR_M\n+\tmcr\tp15, 0, r0, c1, c0, 0\t\t@ Write SCTLR\n+\tnop\n+\n+\t@ Call the cache invalidation routine\n+\tbl\tv7_flush_dcache_all\n+\tnop\n+\tmov\tr0,#0\n+\tldr\tr3, =0x19022000\t\t\t@ L2 cache controller, control reg\n+\tstr\tr0, [r3, #0x100]\t\t@ Disable L2 cache\n+\tnop\n+\n+\t@ Restore\n+\tmov\tr8, r12\n--- a/arch/arm/boot/compressed/cache-v7-min.S\n+++ b/arch/arm/boot/compressed/cache-v7-min.S\n@@ -12,6 +12,7 @@\n \n #include <linux/linkage.h>\n #include <linux/init.h>\n+#include <asm/assembler.h>\n \n \t__INIT\n \n@@ -63,7 +64,7 @@ loop2:\n  ARM(\torr\tr11, r11, r9, lsl r2\t)\t@ factor index number into r11\n  THUMB(\tlsl\tr6, r9, r2\t\t)\n  THUMB(\torr\tr11, r11, r6\t\t)\t@ factor index number into r11\n-\tmcr\tp15, 0, r11, c7, c14, 2\t\t@ clean & invalidate by set/way\n+\tmcr     p15, 0, r11, c7, c6, 2\t\t@ clean & invalidate by set/way\n \tsubs\tr9, r9, #1\t\t\t@ decrement the index\n \tbge\tloop2\n \tsubs\tr4, r4, #1\t\t\t@ decrement the way\n"
  },
  {
    "path": "target/linux/bcm53xx/patches-5.10/304-ARM-dts-BCM5301X-Specify-switch-ports-for-remaining-.patch",
    "content": "From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nSubject: [PATCH] ARM: dts: BCM5301X: Specify switch ports for remaining\n devices\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\n---\n\n--- a/arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dts\n+++ b/arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dts\n@@ -93,3 +93,40 @@\n &usb3_phy {\n \tstatus = \"okay\";\n };\n+\n+&srab {\n+\tstatus = \"okay\";\n+\n+\tports {\n+\t\tport@0 {\n+\t\t\treg = <0>;\n+\t\t\tlabel = \"lan1\";\n+\t\t};\n+\n+\t\tport@1 {\n+\t\t\treg = <1>;\n+\t\t\tlabel = \"lan2\";\n+\t\t};\n+\n+\t\tport@2 {\n+\t\t\treg = <2>;\n+\t\t\tlabel = \"lan3\";\n+\t\t};\n+\n+\t\tport@3 {\n+\t\t\treg = <3>;\n+\t\t\tlabel = \"lan4\";\n+\t\t};\n+\n+\t\tport@4 {\n+\t\t\treg = <4>;\n+\t\t\tlabel = \"wan\";\n+\t\t};\n+\n+\t\tport@5 {\n+\t\t\treg = <5>;\n+\t\t\tlabel = \"cpu\";\n+\t\t\tethernet = <&gmac0>;\n+\t\t};\n+\t};\n+};\n--- a/arch/arm/boot/dts/bcm4708-asus-rt-ac68u.dts\n+++ b/arch/arm/boot/dts/bcm4708-asus-rt-ac68u.dts\n@@ -83,3 +83,40 @@\n &usb3_phy {\n \tstatus = \"okay\";\n };\n+\n+&srab {\n+\tstatus = \"okay\";\n+\n+\tports {\n+\t\tport@0 {\n+\t\t\treg = <0>;\n+\t\t\tlabel = \"wan\";\n+\t\t};\n+\n+\t\tport@1 {\n+\t\t\treg = <1>;\n+\t\t\tlabel = \"lan1\";\n+\t\t};\n+\n+\t\tport@2 {\n+\t\t\treg = <2>;\n+\t\t\tlabel = \"lan2\";\n+\t\t};\n+\n+\t\tport@3 {\n+\t\t\treg = <3>;\n+\t\t\tlabel = \"lan3\";\n+\t\t};\n+\n+\t\tport@4 {\n+\t\t\treg = <4>;\n+\t\t\tlabel = \"lan4\";\n+\t\t};\n+\n+\t\tport@5 {\n+\t\t\treg = <5>;\n+\t\t\tlabel = \"cpu\";\n+\t\t\tethernet = <&gmac0>;\n+\t\t};\n+\t};\n+};\n--- a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts\n+++ b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts\n@@ -149,3 +149,40 @@\n &usb3_phy {\n \tstatus = \"okay\";\n };\n+\n+&srab {\n+\tstatus = \"okay\";\n+\n+\tports {\n+\t\tport@0 {\n+\t\t\treg = <0>;\n+\t\t\tlabel = \"lan1\";\n+\t\t};\n+\n+\t\tport@1 {\n+\t\t\treg = <1>;\n+\t\t\tlabel = \"lan2\";\n+\t\t};\n+\n+\t\tport@2 {\n+\t\t\treg = <2>;\n+\t\t\tlabel = \"lan3\";\n+\t\t};\n+\n+\t\tport@3 {\n+\t\t\treg = <3>;\n+\t\t\tlabel = \"lan4\";\n+\t\t};\n+\n+\t\tport@4 {\n+\t\t\treg = <4>;\n+\t\t\tlabel = \"wan\";\n+\t\t};\n+\n+\t\tport@5 {\n+\t\t\treg = <5>;\n+\t\t\tlabel = \"cpu\";\n+\t\t\tethernet = <&gmac0>;\n+\t\t};\n+\t};\n+};\n--- a/arch/arm/boot/dts/bcm4708-linksys-ea6300-v1.dts\n+++ b/arch/arm/boot/dts/bcm4708-linksys-ea6300-v1.dts\n@@ -46,3 +46,40 @@\n &usb3_phy {\n \tstatus = \"okay\";\n };\n+\n+&srab {\n+\tstatus = \"okay\";\n+\n+\tports {\n+\t\tport@0 {\n+\t\t\treg = <0>;\n+\t\t\tlabel = \"lan1\";\n+\t\t};\n+\n+\t\tport@1 {\n+\t\t\treg = <1>;\n+\t\t\tlabel = \"lan2\";\n+\t\t};\n+\n+\t\tport@2 {\n+\t\t\treg = <2>;\n+\t\t\tlabel = \"lan3\";\n+\t\t};\n+\n+\t\tport@3 {\n+\t\t\treg = <3>;\n+\t\t\tlabel = \"lan4\";\n+\t\t};\n+\n+\t\tport@4 {\n+\t\t\treg = <4>;\n+\t\t\tlabel = \"wan\";\n+\t\t};\n+\n+\t\tport@5 {\n+\t\t\treg = <5>;\n+\t\t\tlabel = \"cpu\";\n+\t\t\tethernet = <&gmac0>;\n+\t\t};\n+\t};\n+};\n--- a/arch/arm/boot/dts/bcm4708-linksys-ea6500-v2.dts\n+++ b/arch/arm/boot/dts/bcm4708-linksys-ea6500-v2.dts\n@@ -42,3 +42,40 @@\n &usb3_phy {\n \tstatus = \"okay\";\n };\n+\n+&srab {\n+\tstatus = \"okay\";\n+\n+\tports {\n+\t\tport@0 {\n+\t\t\treg = <0>;\n+\t\t\tlabel = \"lan1\";\n+\t\t};\n+\n+\t\tport@1 {\n+\t\t\treg = <1>;\n+\t\t\tlabel = \"lan2\";\n+\t\t};\n+\n+\t\tport@2 {\n+\t\t\treg = <2>;\n+\t\t\tlabel = \"lan3\";\n+\t\t};\n+\n+\t\tport@3 {\n+\t\t\treg = <3>;\n+\t\t\tlabel = \"lan4\";\n+\t\t};\n+\n+\t\tport@4 {\n+\t\t\treg = <4>;\n+\t\t\tlabel = \"wan\";\n+\t\t};\n+\n+\t\tport@5 {\n+\t\t\treg = <5>;\n+\t\t\tlabel = \"cpu\";\n+\t\t\tethernet = <&gmac0>;\n+\t\t};\n+\t};\n+};\n--- a/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts\n+++ b/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts\n@@ -86,3 +86,40 @@\n &usb3_phy {\n \tstatus = \"okay\";\n };\n+\n+&srab {\n+\tstatus = \"okay\";\n+\n+\tports {\n+\t\tport@0 {\n+\t\t\treg = <0>;\n+\t\t\tlabel = \"lan1\";\n+\t\t};\n+\n+\t\tport@1 {\n+\t\t\treg = <1>;\n+\t\t\tlabel = \"lan2\";\n+\t\t};\n+\n+\t\tport@2 {\n+\t\t\treg = <2>;\n+\t\t\tlabel = \"lan3\";\n+\t\t};\n+\n+\t\tport@3 {\n+\t\t\treg = <3>;\n+\t\t\tlabel = \"lan4\";\n+\t\t};\n+\n+\t\tport@4 {\n+\t\t\treg = <4>;\n+\t\t\tlabel = \"wan\";\n+\t\t};\n+\n+\t\tport@5 {\n+\t\t\treg = <5>;\n+\t\t\tlabel = \"cpu\";\n+\t\t\tethernet = <&gmac0>;\n+\t\t};\n+\t};\n+};\n--- a/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts\n+++ b/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts\n@@ -77,3 +77,40 @@\n &usb3_phy {\n \tstatus = \"okay\";\n };\n+\n+&srab {\n+\tstatus = \"okay\";\n+\n+\tports {\n+\t\tport@0 {\n+\t\t\treg = <0>;\n+\t\t\tlabel = \"wan\";\n+\t\t};\n+\n+\t\tport@1 {\n+\t\t\treg = <1>;\n+\t\t\tlabel = \"lan1\";\n+\t\t};\n+\n+\t\tport@2 {\n+\t\t\treg = <2>;\n+\t\t\tlabel = \"lan2\";\n+\t\t};\n+\n+\t\tport@3 {\n+\t\t\treg = <3>;\n+\t\t\tlabel = \"lan3\";\n+\t\t};\n+\n+\t\tport@4 {\n+\t\t\treg = <4>;\n+\t\t\tlabel = \"lan4\";\n+\t\t};\n+\n+\t\tport@5 {\n+\t\t\treg = <5>;\n+\t\t\tlabel = \"cpu\";\n+\t\t\tethernet = <&gmac0>;\n+\t\t};\n+\t};\n+};\n--- a/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts\n+++ b/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts\n@@ -68,6 +68,38 @@\n \tstatus = \"okay\";\n };\n \n+&srab {\n+\tstatus = \"okay\";\n+\n+\tports {\n+\t\tport@0 {\n+\t\t\treg = <0>;\n+\t\t\tlabel = \"wan\";\n+\t\t};\n+\n+\t\tport@1 {\n+\t\t\treg = <1>;\n+\t\t\tlabel = \"lan1\";\n+\t\t};\n+\n+\t\tport@2 {\n+\t\t\treg = <2>;\n+\t\t\tlabel = \"lan2\";\n+\t\t};\n+\n+\t\tport@3 {\n+\t\t\treg = <3>;\n+\t\t\tlabel = \"lan3\";\n+\t\t};\n+\n+\t\tport@7 {\n+\t\t\treg = <7>;\n+\t\t\tlabel = \"cpu\";\n+\t\t\tethernet = <&gmac1>;\n+\t\t};\n+\t};\n+};\n+\n &nandcs {\n \tpartitions {\n \t\tcompatible = \"fixed-partitions\";\n--- a/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts\n+++ b/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts\n@@ -132,3 +132,40 @@\n &usb3_phy {\n \tstatus = \"okay\";\n };\n+\n+&srab {\n+\tstatus = \"okay\";\n+\n+\tports {\n+\t\tport@0 {\n+\t\t\treg = <0>;\n+\t\t\tlabel = \"lan1\";\n+\t\t};\n+\n+\t\tport@1 {\n+\t\t\treg = <1>;\n+\t\t\tlabel = \"lan2\";\n+\t\t};\n+\n+\t\tport@2 {\n+\t\t\treg = <2>;\n+\t\t\tlabel = \"lan3\";\n+\t\t};\n+\n+\t\tport@3 {\n+\t\t\treg = <3>;\n+\t\t\tlabel = \"lan4\";\n+\t\t};\n+\n+\t\tport@4 {\n+\t\t\treg = <4>;\n+\t\t\tlabel = \"wan\";\n+\t\t};\n+\n+\t\tport@5 {\n+\t\t\treg = <5>;\n+\t\t\tlabel = \"cpu\";\n+\t\t\tethernet = <&gmac0>;\n+\t\t};\n+\t};\n+};\n--- a/arch/arm/boot/dts/bcm4709-linksys-ea9200.dts\n+++ b/arch/arm/boot/dts/bcm4709-linksys-ea9200.dts\n@@ -49,3 +49,45 @@\n &usb3_phy {\n \tstatus = \"okay\";\n };\n+\n+&srab {\n+\tstatus = \"okay\";\n+\n+\tports {\n+\t\tport@0 {\n+\t\t\treg = <0>;\n+\t\t\tlabel = \"lan1\";\n+\t\t};\n+\n+\t\tport@1 {\n+\t\t\treg = <1>;\n+\t\t\tlabel = \"lan2\";\n+\t\t};\n+\n+\t\tport@2 {\n+\t\t\treg = <2>;\n+\t\t\tlabel = \"lan3\";\n+\t\t};\n+\n+\t\tport@3 {\n+\t\t\treg = <3>;\n+\t\t\tlabel = \"lan4\";\n+\t\t};\n+\n+\t\tport@4 {\n+\t\t\treg = <4>;\n+\t\t\tlabel = \"wan\";\n+\t\t};\n+\n+\t\tport@8 {\n+\t\t\treg = <8>;\n+\t\t\tlabel = \"cpu\";\n+\t\t\tethernet = <&gmac2>;\n+\n+\t\t\tfixed-link {\n+\t\t\t\tspeed = <1000>;\n+\t\t\t\tfull-duplex;\n+\t\t\t};\n+\t\t};\n+\t};\n+};\n--- a/arch/arm/boot/dts/bcm4709-netgear-r7000.dts\n+++ b/arch/arm/boot/dts/bcm4709-netgear-r7000.dts\n@@ -106,3 +106,40 @@\n &usb3_phy {\n \tstatus = \"okay\";\n };\n+\n+&srab {\n+\tstatus = \"okay\";\n+\n+\tports {\n+\t\tport@0 {\n+\t\t\treg = <0>;\n+\t\t\tlabel = \"wan\";\n+\t\t};\n+\n+\t\tport@1 {\n+\t\t\treg = <1>;\n+\t\t\tlabel = \"lan1\";\n+\t\t};\n+\n+\t\tport@2 {\n+\t\t\treg = <2>;\n+\t\t\tlabel = \"lan2\";\n+\t\t};\n+\n+\t\tport@3 {\n+\t\t\treg = <3>;\n+\t\t\tlabel = \"lan3\";\n+\t\t};\n+\n+\t\tport@4 {\n+\t\t\treg = <4>;\n+\t\t\tlabel = \"lan4\";\n+\t\t};\n+\n+\t\tport@5 {\n+\t\t\treg = <5>;\n+\t\t\tlabel = \"cpu\";\n+\t\t\tethernet = <&gmac0>;\n+\t\t};\n+\t};\n+};\n--- a/arch/arm/boot/dts/bcm47094-netgear-r8500.dts\n+++ b/arch/arm/boot/dts/bcm47094-netgear-r8500.dts\n@@ -94,3 +94,45 @@\n &usb3_phy {\n \tstatus = \"okay\";\n };\n+\n+&srab {\n+\tstatus = \"okay\";\n+\n+\tports {\n+\t\tport@0 {\n+\t\t\treg = <0>;\n+\t\t\tlabel = \"wan\";\n+\t\t};\n+\n+\t\tport@1 {\n+\t\t\treg = <1>;\n+\t\t\tlabel = \"lan1\";\n+\t\t};\n+\n+\t\tport@2 {\n+\t\t\treg = <2>;\n+\t\t\tlabel = \"lan2\";\n+\t\t};\n+\n+\t\tport@3 {\n+\t\t\treg = <3>;\n+\t\t\tlabel = \"lan3\";\n+\t\t};\n+\n+\t\tport@4 {\n+\t\t\treg = <4>;\n+\t\t\tlabel = \"lan4\";\n+\t\t};\n+\n+\t\tport@8 {\n+\t\t\treg = <8>;\n+\t\t\tlabel = \"cpu\";\n+\t\t\tethernet = <&gmac2>;\n+\n+\t\t\tfixed-link {\n+\t\t\t\tspeed = <1000>;\n+\t\t\t\tfull-duplex;\n+\t\t\t};\n+\t\t};\n+\t};\n+};\n--- a/arch/arm/boot/dts/bcm47094-phicomm-k3.dts\n+++ b/arch/arm/boot/dts/bcm47094-phicomm-k3.dts\n@@ -38,6 +38,38 @@\n \tstatus = \"okay\";\n };\n \n+&srab {\n+\tstatus = \"okay\";\n+\n+\tports {\n+\t\tport@0 {\n+\t\t\treg = <0>;\n+\t\t\tlabel = \"lan1\";\n+\t\t};\n+\n+\t\tport@1 {\n+\t\t\treg = <1>;\n+\t\t\tlabel = \"lan2\";\n+\t\t};\n+\n+\t\tport@2 {\n+\t\t\treg = <2>;\n+\t\t\tlabel = \"lan3\";\n+\t\t};\n+\n+\t\tport@3 {\n+\t\t\treg = <3>;\n+\t\t\tlabel = \"wan\";\n+\t\t};\n+\n+\t\tport@5 {\n+\t\t\treg = <5>;\n+\t\t\tlabel = \"cpu\";\n+\t\t\tethernet = <&gmac0>;\n+\t\t};\n+\t};\n+};\n+\n &nandcs {\n \tpartitions {\n \t\tcompatible = \"fixed-partitions\";\n--- a/arch/arm/boot/dts/bcm47081-tplink-archer-c5-v2.dts\n+++ b/arch/arm/boot/dts/bcm47081-tplink-archer-c5-v2.dts\n@@ -91,6 +91,43 @@\n \t};\n };\n \n+&srab {\n+\tstatus = \"okay\";\n+\n+\tports {\n+\t\tport@0 {\n+\t\t\treg = <0>;\n+\t\t\tlabel = \"wan\";\n+\t\t};\n+\n+\t\tport@1 {\n+\t\t\treg = <1>;\n+\t\t\tlabel = \"lan1\";\n+\t\t};\n+\n+\t\tport@2 {\n+\t\t\treg = <2>;\n+\t\t\tlabel = \"lan2\";\n+\t\t};\n+\n+\t\tport@3 {\n+\t\t\treg = <3>;\n+\t\t\tlabel = \"lan3\";\n+\t\t};\n+\n+\t\tport@4 {\n+\t\t\treg = <4>;\n+\t\t\tlabel = \"lan4\";\n+\t\t};\n+\n+\t\tport@5 {\n+\t\t\treg = <5>;\n+\t\t\tlabel = \"cpu\";\n+\t\t\tethernet = <&gmac0>;\n+\t\t};\n+\t};\n+};\n+\n &spi_nor {\n \tstatus = \"okay\";\n \n--- a/arch/arm/boot/dts/bcm4709-tplink-archer-c9-v1.dts\n+++ b/arch/arm/boot/dts/bcm4709-tplink-archer-c9-v1.dts\n@@ -102,6 +102,43 @@\n \tvcc-gpio = <&chipcommon 12 GPIO_ACTIVE_HIGH>;\n };\n \n+&srab {\n+\tstatus = \"okay\";\n+\n+\tports {\n+\t\tport@0 {\n+\t\t\treg = <0>;\n+\t\t\tlabel = \"wan\";\n+\t\t};\n+\n+\t\tport@1 {\n+\t\t\treg = <1>;\n+\t\t\tlabel = \"lan1\";\n+\t\t};\n+\n+\t\tport@2 {\n+\t\t\treg = <2>;\n+\t\t\tlabel = \"lan2\";\n+\t\t};\n+\n+\t\tport@3 {\n+\t\t\treg = <3>;\n+\t\t\tlabel = \"lan3\";\n+\t\t};\n+\n+\t\tport@4 {\n+\t\t\treg = <4>;\n+\t\t\tlabel = \"lan4\";\n+\t\t};\n+\n+\t\tport@5 {\n+\t\t\treg = <5>;\n+\t\t\tlabel = \"cpu\";\n+\t\t\tethernet = <&gmac0>;\n+\t\t};\n+\t};\n+};\n+\n &spi_nor {\n \tstatus = \"okay\";\n \n--- a/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts\n+++ b/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts\n@@ -107,3 +107,41 @@\n &usb3_phy {\n \tstatus = \"okay\";\n };\n+\n+&srab {\n+\tstatus = \"okay\";\n+\n+\tports {\n+\t\tport@0 {\n+\t\t\treg = <0>;\n+\t\t\tlabel = \"lan1\";\n+\t\t};\n+\n+\t\tport@1 {\n+\t\t\treg = <1>;\n+\t\t\tlabel = \"lan2\";\n+\t\t};\n+\n+\t\tport@2 {\n+\t\t\treg = <2>;\n+\t\t\tlabel = \"lan3\";\n+\t\t};\n+\n+\t\tport@3 {\n+\t\t\treg = <3>;\n+\t\t\tlabel = \"lan4\";\n+\t\t};\n+\n+\t\tport@4 {\n+\t\t\treg = <4>;\n+\t\t\tlabel = \"wan\";\n+\t\t};\n+\n+\t\tport@5 {\n+\t\t\treg = <5>;\n+\t\t\tlabel = \"cpu\";\n+\t\t\tethernet = <&gmac0>;\n+\t\t};\n+\t};\n+};\n+\n"
  },
  {
    "path": "target/linux/bcm53xx/patches-5.10/310-ARM-BCM5301X-Add-DT-for-Netgear-R7900.patch",
    "content": "From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <zajec5@gmail.com>\nSubject: [PATCH] ARM: BCM5301X: Add DT for Netgear R7900\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nSigned-off-by: Rafał Miłecki <zajec5@gmail.com>\n---\n\n--- a/arch/arm/boot/dts/Makefile\n+++ b/arch/arm/boot/dts/Makefile\n@@ -116,6 +116,7 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \\\n \tbcm4709-buffalo-wxr-1900dhp.dtb \\\n \tbcm4709-linksys-ea9200.dtb \\\n \tbcm4709-netgear-r7000.dtb \\\n+\tbcm4709-netgear-r7900.dtb \\\n \tbcm4709-netgear-r8000.dtb \\\n \tbcm4709-tplink-archer-c9-v1.dtb \\\n \tbcm47094-asus-rt-ac88u.dtb \\\n--- /dev/null\n+++ b/arch/arm/boot/dts/bcm4709-netgear-r7900.dts\n@@ -0,0 +1,42 @@\n+/*\n+ * Broadcom BCM470X / BCM5301X ARM platform code.\n+ * DTS for Netgear R7900\n+ *\n+ * Copyright (C) 2016 Rafał Miłecki <zajec5@gmail.com>\n+ *\n+ * Licensed under the GNU/GPL. See COPYING for details.\n+ */\n+\n+/dts-v1/;\n+\n+#include \"bcm4709.dtsi\"\n+#include \"bcm5301x-nand-cs0-bch8.dtsi\"\n+\n+/ {\n+\tcompatible = \"netgear,r7900\", \"brcm,bcm4709\", \"brcm,bcm4708\";\n+\tmodel = \"Netgear R7900\";\n+\n+\tchosen {\n+\t\tbootargs = \"console=ttyS0,115200\";\n+\t};\n+\n+\tmemory {\n+\t\treg = <0x00000000 0x08000000\n+\t\t       0x88000000 0x08000000>;\n+\t};\n+\n+\taxi@18000000 {\n+\t\tusb3@23000 {\n+\t\t\treg = <0x00023000 0x1000>;\n+\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <1>;\n+\n+\t\t\tvcc-gpio = <&chipcommon 0 GPIO_ACTIVE_HIGH>;\n+\t\t};\n+\t};\n+};\n+\n+&uart0 {\n+\tstatus = \"okay\";\n+};\n"
  },
  {
    "path": "target/linux/bcm53xx/patches-5.10/320-ARM-dts-BCM5301X-Switch-back-to-old-clock-nodes-name.patch",
    "content": "From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Tue, 23 Nov 2021 13:13:05 +0100\nSubject: [PATCH] ARM: dts: BCM5301X: Switch back to old clock nodes names\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nFirst of all using the same node name prefix resulted in trying to\nregister 2 clocks under the same \"clock-controller\" name:\n\n[    0.000000] __clk_core_init: clk clock-controller already initialized\n[    0.000000] ------------[ cut here ]------------\n[    0.000000] WARNING: CPU: 0 PID: 0 at drivers/clk/bcm/clk-iproc-pll.c:802 iproc_pll_clk_setup+0x4c8/0x4f4\n[    0.000000] Modules linked in:\n[    0.000000] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 5.10.80 #0\n[    0.000000] Hardware name: BCM5301X\n[    0.000000] [<c0108410>] (unwind_backtrace) from [<c0104bc4>] (show_stack+0x10/0x14)\n[    0.000000] [<c0104bc4>] (show_stack) from [<c03dca28>] (dump_stack+0x94/0xa8)\n[    0.000000] [<c03dca28>] (dump_stack) from [<c0118440>] (__warn+0xb8/0x114)\n[    0.000000] [<c0118440>] (__warn) from [<c0118504>] (warn_slowpath_fmt+0x68/0x78)\n[    0.000000] [<c0118504>] (warn_slowpath_fmt) from [<c043281c>] (iproc_pll_clk_setup+0x4c8/0x4f4)\n[    0.000000] [<c043281c>] (iproc_pll_clk_setup) from [<c0818c04>] (nsp_genpll_clk_init+0x30/0x38)\n[    0.000000] [<c0818c04>] (nsp_genpll_clk_init) from [<c0818634>] (of_clk_init+0x118/0x1f8)\n[    0.000000] [<c0818634>] (of_clk_init) from [<c08039b0>] (time_init+0x24/0x30)\n[    0.000000] [<c08039b0>] (time_init) from [<c0800d14>] (start_kernel+0x398/0x50c)\n[    0.000000] [<c0800d14>] (start_kernel) from [<00000000>] (0x0)\n[    0.000000] ---[ end trace fe236bfe9559ee50 ]---\n\nSecondly using any other names than \"lcpll0\" and \"genpll\" breaks output\nclocks:\n\n$ cat /sys/kernel/debug/clk/usbclk/clk_rate\n0\n\nFor some reason iproc_clk_recalc_rate() gets called with \"parent_rate\"\nargument 0 whenever clocks aren't named \"lcpll0\" and \"genpll\".\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\n---\n arch/arm/boot/dts/bcm5301x.dtsi | 4 ++--\n 1 file changed, 2 insertions(+), 2 deletions(-)\n\n--- a/arch/arm/boot/dts/bcm5301x.dtsi\n+++ b/arch/arm/boot/dts/bcm5301x.dtsi\n@@ -421,7 +421,7 @@\n \t\t\t#address-cells = <1>;\n \t\t\t#size-cells = <1>;\n \n-\t\t\tlcpll0: clock-controller@100 {\n+\t\t\tlcpll0: lcpll0@100 {\n \t\t\t\t#clock-cells = <1>;\n \t\t\t\tcompatible = \"brcm,nsp-lcpll0\";\n \t\t\t\treg = <0x100 0x14>;\n@@ -430,7 +430,7 @@\n \t\t\t\t\t\t     \"sdio\", \"ddr_phy\";\n \t\t\t};\n \n-\t\t\tgenpll: clock-controller@140 {\n+\t\t\tgenpll: genpll@140 {\n \t\t\t\t#clock-cells = <1>;\n \t\t\t\tcompatible = \"brcm,nsp-genpll\";\n \t\t\t\treg = <0x140 0x24>;\n"
  },
  {
    "path": "target/linux/bcm53xx/patches-5.10/321-ARM-dts-BCM5301X-Describe-partition-formats.patch",
    "content": "From 7166207bd1d8c46d09d640d46afc685df9bb9083 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Thu, 22 Nov 2018 09:21:49 +0100\nSubject: [PATCH] ARM: dts: BCM5301X: Describe partition formats\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nIt's needed by OpenWrt for custom partitioning.\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\n---\n arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts | 1 +\n 1 file changed, 1 insertion(+)\n\n--- a/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts\n+++ b/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts\n@@ -35,6 +35,7 @@\n \t\t\t\tpartition@0 {\n \t\t\t\t\tlabel = \"firmware\";\n \t\t\t\t\treg = <0x00000000 0x08000000>;\n+\t\t\t\t\tcompatible = \"seama\";\n \t\t\t\t};\n \t\t\t};\n \t\t};\n"
  },
  {
    "path": "target/linux/bcm53xx/patches-5.10/500-UBI-Detect-EOF-mark-and-erase-all-remaining-blocks.patch",
    "content": "From 2a2af518266a29323cf30c3f9ba9ef2ceb1dd84b Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <zajec5@gmail.com>\nDate: Thu, 16 Oct 2014 20:52:16 +0200\nSubject: [PATCH] UBI: Detect EOF mark and erase all remaining blocks\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nSigned-off-by: Rafał Miłecki <zajec5@gmail.com>\n---\n drivers/mtd/ubi/attach.c | 5 +++++\n drivers/mtd/ubi/io.c     | 4 ++++\n drivers/mtd/ubi/ubi.h    | 1 +\n 3 files changed, 10 insertions(+)\n\n--- a/drivers/mtd/ubi/attach.c\n+++ b/drivers/mtd/ubi/attach.c\n@@ -82,6 +82,9 @@ static int self_check_ai(struct ubi_devi\n #define AV_ADD\t\tBIT(1)\n #define AV_FIND_OR_ADD\t(AV_FIND | AV_ADD)\n \n+/* Set on finding block with 0xdeadc0de, indicates erasing all blocks behind */\n+bool erase_all_next;\n+\n /**\n  * find_or_add_av - internal function to find a volume, add a volume or do\n  *\t\t    both (find and add if missing).\n@@ -1580,6 +1583,8 @@ int ubi_attach(struct ubi_device *ubi, i\n \tif (!ai)\n \t\treturn -ENOMEM;\n \n+\terase_all_next = false;\n+\n #ifdef CONFIG_MTD_UBI_FASTMAP\n \t/* On small flash devices we disable fastmap in any case. */\n \tif ((int)mtd_div_by_eb(ubi->mtd->size, ubi->mtd) <= UBI_FM_MAX_START) {\n--- a/drivers/mtd/ubi/io.c\n+++ b/drivers/mtd/ubi/io.c\n@@ -710,6 +710,10 @@ int ubi_io_read_ec_hdr(struct ubi_device\n \t}\n \n \tmagic = be32_to_cpu(ec_hdr->magic);\n+\tif (magic == 0xdeadc0de)\n+\t\terase_all_next = true;\n+\tif (erase_all_next)\n+\t\treturn read_err ? UBI_IO_FF_BITFLIPS : UBI_IO_FF;\n \tif (magic != UBI_EC_HDR_MAGIC) {\n \t\tif (mtd_is_eccerr(read_err))\n \t\t\treturn UBI_IO_BAD_HDR_EBADMSG;\n--- a/drivers/mtd/ubi/ubi.h\n+++ b/drivers/mtd/ubi/ubi.h\n@@ -824,6 +824,7 @@ extern struct mutex ubi_devices_mutex;\n extern struct blocking_notifier_head ubi_notifiers;\n \n /* attach.c */\n+extern bool erase_all_next;\n struct ubi_ainf_peb *ubi_alloc_aeb(struct ubi_attach_info *ai, int pnum,\n \t\t\t\t   int ec);\n void ubi_free_aeb(struct ubi_attach_info *ai, struct ubi_ainf_peb *aeb);\n"
  },
  {
    "path": "target/linux/bcm53xx/patches-5.10/800-0001-firmware-bcm47xx_nvram-support-init-from-IO-memory.patch",
    "content": "From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Thu, 11 Mar 2021 08:24:44 +0100\nSubject: [PATCH] firmware: bcm47xx_nvram: support init from IO memory\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\n---\n drivers/firmware/broadcom/bcm47xx_nvram.c | 17 +++++++++++++++++\n include/linux/bcm47xx_nvram.h             |  6 ++++++\n 2 files changed, 23 insertions(+)\n\n--- a/drivers/firmware/broadcom/bcm47xx_nvram.c\n+++ b/drivers/firmware/broadcom/bcm47xx_nvram.c\n@@ -110,6 +110,23 @@ found:\n \treturn 0;\n }\n \n+int bcm47xx_nvram_init_from_iomem(void __iomem *nvram_start, size_t res_size)\n+{\n+\tif (nvram_len) {\n+\t\tpr_warn(\"nvram already initialized\\n\");\n+\t\treturn -EEXIST;\n+\t}\n+\n+\tif (!bcm47xx_nvram_is_valid(nvram_start)) {\n+\t\tpr_err(\"No valid NVRAM found\\n\");\n+\t\treturn -ENOENT;\n+\t}\n+\n+\tbcm47xx_nvram_copy(nvram_start, res_size);\n+\n+\treturn 0;\n+}\n+\n /*\n  * On bcm47xx we need access to the NVRAM very early, so we can't use mtd\n  * subsystem to access flash. We can't even use platform device / driver to\n--- a/include/linux/bcm47xx_nvram.h\n+++ b/include/linux/bcm47xx_nvram.h\n@@ -11,6 +11,7 @@\n #include <linux/vmalloc.h>\n \n #ifdef CONFIG_BCM47XX_NVRAM\n+int bcm47xx_nvram_init_from_iomem(void __iomem *nvram_start, size_t res_size);\n int bcm47xx_nvram_init_from_mem(u32 base, u32 lim);\n int bcm47xx_nvram_getenv(const char *name, char *val, size_t val_len);\n int bcm47xx_nvram_gpio_pin(const char *name);\n@@ -20,6 +21,11 @@ static inline void bcm47xx_nvram_release\n \tvfree(nvram);\n };\n #else\n+static inline int bcm47xx_nvram_init_from_iomem(void __iomem *nvram_start,\n+\t\t\t\t\t\tsize_t res_size)\n+{\n+\treturn -ENOTSUPP;\n+}\n static inline int bcm47xx_nvram_init_from_mem(u32 base, u32 lim)\n {\n \treturn -ENOTSUPP;\n"
  },
  {
    "path": "target/linux/bcm53xx/patches-5.10/800-0002-nvmem-brcm_nvram-provide-NVMEM-content-to-the-NVRAM-.patch",
    "content": "From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Thu, 11 Mar 2021 08:26:14 +0100\nSubject: [PATCH] nvmem: brcm_nvram: provide NVMEM content to the NVRAM driver\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\n---\n drivers/nvmem/brcm_nvram.c | 3 +++\n 1 file changed, 3 insertions(+)\n\n--- a/drivers/nvmem/brcm_nvram.c\n+++ b/drivers/nvmem/brcm_nvram.c\n@@ -3,6 +3,7 @@\n  * Copyright (C) 2021 Rafał Miłecki <rafal@milecki.pl>\n  */\n \n+#include <linux/bcm47xx_nvram.h>\n #include <linux/io.h>\n #include <linux/mod_devicetable.h>\n #include <linux/module.h>\n@@ -46,6 +47,8 @@ static int brcm_nvram_probe(struct platf\n \tif (IS_ERR(priv->base))\n \t\treturn PTR_ERR(priv->base);\n \n+\tbcm47xx_nvram_init_from_iomem(priv->base, resource_size(res));\n+\n \tconfig.dev = dev;\n \tconfig.priv = priv;\n \tconfig.size = resource_size(res);\n"
  },
  {
    "path": "target/linux/bcm53xx/patches-5.10/905-BCM53573-minor-hacks.patch",
    "content": "From 6f1c62440eb6846cb8045d7a5480ec7bbe47c96f Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Mon, 15 Aug 2016 10:30:41 +0200\nSubject: [PATCH] BCM53573 minor hacks\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\n---\n\n--- a/arch/arm/boot/dts/bcm53573.dtsi\n+++ b/arch/arm/boot/dts/bcm53573.dtsi\n@@ -54,6 +54,7 @@\n \t\t\t     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,\n \t\t\t     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,\n \t\t\t     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;\n+\t\tclocks = <&ilp>;\n \t};\n \n \tclocks {\n--- a/drivers/bcma/main.c\n+++ b/drivers/bcma/main.c\n@@ -328,14 +328,6 @@ static int bcma_register_devices(struct\n \t}\n #endif\n \n-#ifdef CONFIG_BCMA_SFLASH\n-\tif (bus->drv_cc.sflash.present) {\n-\t\terr = platform_device_register(&bcma_sflash_dev);\n-\t\tif (err)\n-\t\t\tbcma_err(bus, \"Error registering serial flash\\n\");\n-\t}\n-#endif\n-\n #ifdef CONFIG_BCMA_NFLASH\n \tif (bus->drv_cc.nflash.present) {\n \t\terr = platform_device_register(&bcma_nflash_dev);\n@@ -413,6 +405,14 @@ int bcma_bus_register(struct bcma_bus *b\n \t\t\tbcma_register_core(bus, core);\n \t}\n \n+#ifdef CONFIG_BCMA_SFLASH\n+\tif (bus->drv_cc.sflash.present) {\n+\t\terr = platform_device_register(&bcma_sflash_dev);\n+\t\tif (err)\n+\t\t\tbcma_err(bus, \"Error registering serial flash\\n\");\n+\t}\n+#endif\n+\n \t/* Try to get SPROM */\n \terr = bcma_sprom_get(bus);\n \tif (err == -ENOENT) {\n--- a/drivers/clocksource/arm_arch_timer.c\n+++ b/drivers/clocksource/arm_arch_timer.c\n@@ -14,6 +14,7 @@\n #include <linux/smp.h>\n #include <linux/cpu.h>\n #include <linux/cpu_pm.h>\n+#include <linux/clk.h>\n #include <linux/clockchips.h>\n #include <linux/clocksource.h>\n #include <linux/interrupt.h>\n@@ -934,6 +935,16 @@ static void arch_timer_of_configure_rate\n \tif (of_property_read_u32(np, \"clock-frequency\", &arch_timer_rate))\n \t\tarch_timer_rate = rate;\n \n+\t/* Get clk rate through clk driver if present */\n+\tif (!arch_timer_rate) {\n+\t\tstruct clk *clk = of_clk_get(np, 0);\n+\n+\t\tif (!IS_ERR(clk)) {\n+\t\t\tif (!clk_prepare_enable(clk))\n+\t\t\t\tarch_timer_rate = clk_get_rate(clk);\n+\t\t}\n+\t}\n+\n \t/* Check the timer frequency. */\n \tif (validate_timer_rate())\n \t\tpr_warn(\"frequency not available\\n\");\n"
  },
  {
    "path": "target/linux/bcm53xx/patches-5.15/030-v5.15-0001-ARM-dts-NSP-add-device-names-to-compatible.patch",
    "content": "From 465078bfdf5271601f098450ae2fc974865c59fd Mon Sep 17 00:00:00 2001\nFrom: Matthew Hagan <mnhagan88@gmail.com>\nDate: Thu, 10 Jun 2021 21:35:10 +0100\nSubject: [PATCH] ARM: dts: NSP: add device names to compatible\n\nCurrently only the SoC type and platform are specified for all NSP\ndevices. This patch adds the device names.\n\nSigned-off-by: Matthew Hagan <mnhagan88@gmail.com>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n arch/arm/boot/dts/bcm958522er.dts  | 2 +-\n arch/arm/boot/dts/bcm958525er.dts  | 2 +-\n arch/arm/boot/dts/bcm958525xmc.dts | 2 +-\n arch/arm/boot/dts/bcm958622hr.dts  | 2 +-\n arch/arm/boot/dts/bcm958625hr.dts  | 2 +-\n arch/arm/boot/dts/bcm958625k.dts   | 2 +-\n arch/arm/boot/dts/bcm988312hr.dts  | 2 +-\n 7 files changed, 7 insertions(+), 7 deletions(-)\n\n--- a/arch/arm/boot/dts/bcm958522er.dts\n+++ b/arch/arm/boot/dts/bcm958522er.dts\n@@ -37,7 +37,7 @@\n \n / {\n \tmodel = \"NorthStar Plus SVK (BCM958522ER)\";\n-\tcompatible = \"brcm,bcm58522\", \"brcm,nsp\";\n+\tcompatible = \"brcm,bcm958522er\", \"brcm,bcm58522\", \"brcm,nsp\";\n \n \tchosen {\n \t\tstdout-path = \"serial0:115200n8\";\n--- a/arch/arm/boot/dts/bcm958525er.dts\n+++ b/arch/arm/boot/dts/bcm958525er.dts\n@@ -37,7 +37,7 @@\n \n / {\n \tmodel = \"NorthStar Plus SVK (BCM958525ER)\";\n-\tcompatible = \"brcm,bcm58525\", \"brcm,nsp\";\n+\tcompatible = \"brcm,bcm958525er\", \"brcm,bcm58525\", \"brcm,nsp\";\n \n \tchosen {\n \t\tstdout-path = \"serial0:115200n8\";\n--- a/arch/arm/boot/dts/bcm958525xmc.dts\n+++ b/arch/arm/boot/dts/bcm958525xmc.dts\n@@ -37,7 +37,7 @@\n \n / {\n \tmodel = \"NorthStar Plus XMC (BCM958525xmc)\";\n-\tcompatible = \"brcm,bcm58525\", \"brcm,nsp\";\n+\tcompatible = \"brcm,bcm958525xmc\", \"brcm,bcm58525\", \"brcm,nsp\";\n \n \tchosen {\n \t\tstdout-path = \"serial0:115200n8\";\n--- a/arch/arm/boot/dts/bcm958622hr.dts\n+++ b/arch/arm/boot/dts/bcm958622hr.dts\n@@ -37,7 +37,7 @@\n \n / {\n \tmodel = \"NorthStar Plus SVK (BCM958622HR)\";\n-\tcompatible = \"brcm,bcm58622\", \"brcm,nsp\";\n+\tcompatible = \"brcm,bcm958622hr\", \"brcm,bcm58622\", \"brcm,nsp\";\n \n \tchosen {\n \t\tstdout-path = \"serial0:115200n8\";\n--- a/arch/arm/boot/dts/bcm958625hr.dts\n+++ b/arch/arm/boot/dts/bcm958625hr.dts\n@@ -37,7 +37,7 @@\n \n / {\n \tmodel = \"NorthStar Plus SVK (BCM958625HR)\";\n-\tcompatible = \"brcm,bcm58625\", \"brcm,nsp\";\n+\tcompatible = \"brcm,bcm958625hr\", \"brcm,bcm58625\", \"brcm,nsp\";\n \n \tchosen {\n \t\tstdout-path = \"serial0:115200n8\";\n--- a/arch/arm/boot/dts/bcm958625k.dts\n+++ b/arch/arm/boot/dts/bcm958625k.dts\n@@ -36,7 +36,7 @@\n \n / {\n \tmodel = \"NorthStar Plus SVK (BCM958625K)\";\n-\tcompatible = \"brcm,bcm58625\", \"brcm,nsp\";\n+\tcompatible = \"brcm,bcm958625k\", \"brcm,bcm58625\", \"brcm,nsp\";\n \n \tchosen {\n \t\tstdout-path = \"serial0:115200n8\";\n--- a/arch/arm/boot/dts/bcm988312hr.dts\n+++ b/arch/arm/boot/dts/bcm988312hr.dts\n@@ -37,7 +37,7 @@\n \n / {\n \tmodel = \"NorthStar Plus SVK (BCM988312HR)\";\n-\tcompatible = \"brcm,bcm88312\", \"brcm,nsp\";\n+\tcompatible = \"brcm,bcm988312hr\", \"brcm,bcm88312\", \"brcm,nsp\";\n \n \tchosen {\n \t\tstdout-path = \"serial0:115200n8\";\n"
  },
  {
    "path": "target/linux/bcm53xx/patches-5.15/030-v5.15-0002-ARM-dts-NSP-enable-DMA-on-bcm988312hr.patch",
    "content": "From 1b90dde4278a7b459979706b572785bc3a10bbb5 Mon Sep 17 00:00:00 2001\nFrom: Matthew Hagan <mnhagan88@gmail.com>\nDate: Thu, 10 Jun 2021 21:35:12 +0100\nSubject: [PATCH] ARM: dts: NSP: enable DMA on bcm988312hr\n\nThe previous patch \"ARM: dts: NSP: Disable PL330 by default, add\ndma-coherent property\" set the DMAC to disabled by default, requiring it\nto be manually enabled on each device. The bcm988312hr was mistakenly\nomitted. This patch adds it back.\n\nSigned-off-by: Matthew Hagan <mnhagan88@gmail.com>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n arch/arm/boot/dts/bcm988312hr.dts | 4 ++++\n 1 file changed, 4 insertions(+)\n\n--- a/arch/arm/boot/dts/bcm988312hr.dts\n+++ b/arch/arm/boot/dts/bcm988312hr.dts\n@@ -58,6 +58,10 @@\n \n /* USB 3 support needed to be complete */\n \n+&dma {\n+\tstatus = \"okay\";\n+};\n+\n &amac0 {\n \tstatus = \"okay\";\n };\n"
  },
  {
    "path": "target/linux/bcm53xx/patches-5.15/030-v5.15-0003-ARM-dts-NSP-disable-qspi-node-by-default.patch",
    "content": "From 091a12b1814142eac16a115dab206f735b5476a9 Mon Sep 17 00:00:00 2001\nFrom: Matthew Hagan <mnhagan88@gmail.com>\nDate: Sun, 13 Jun 2021 10:46:34 +0100\nSubject: [PATCH] ARM: dts: NSP: disable qspi node by default\n\nThe QSPI bus is enabled by default, however this may not used on all\ndevices. This patch disables by default, requiring it to be explicitly\nenabled where required.\n\nSigned-off-by: Matthew Hagan <mnhagan88@gmail.com>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n arch/arm/boot/dts/bcm-nsp.dtsi     | 1 +\n arch/arm/boot/dts/bcm958522er.dts  | 1 +\n arch/arm/boot/dts/bcm958525er.dts  | 1 +\n arch/arm/boot/dts/bcm958525xmc.dts | 1 +\n arch/arm/boot/dts/bcm958622hr.dts  | 1 +\n arch/arm/boot/dts/bcm958623hr.dts  | 1 +\n arch/arm/boot/dts/bcm958625hr.dts  | 1 +\n arch/arm/boot/dts/bcm958625k.dts   | 1 +\n arch/arm/boot/dts/bcm988312hr.dts  | 1 +\n 9 files changed, 9 insertions(+)\n\n--- a/arch/arm/boot/dts/bcm-nsp.dtsi\n+++ b/arch/arm/boot/dts/bcm-nsp.dtsi\n@@ -310,6 +310,7 @@\n \t\t\tnum-cs = <2>;\n \t\t\t#address-cells = <1>;\n \t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"disabled\";\n \t\t};\n \n \t\txhci: usb@29000 {\n--- a/arch/arm/boot/dts/bcm958522er.dts\n+++ b/arch/arm/boot/dts/bcm958522er.dts\n@@ -134,6 +134,7 @@\n };\n \n &qspi {\n+\tstatus = \"okay\";\n \tbspi-sel = <0>;\n \tflash: m25p80@0 {\n \t\t#address-cells = <1>;\n--- a/arch/arm/boot/dts/bcm958525er.dts\n+++ b/arch/arm/boot/dts/bcm958525er.dts\n@@ -134,6 +134,7 @@\n };\n \n &qspi {\n+\tstatus = \"okay\";\n \tbspi-sel = <0>;\n \tflash: m25p80@0 {\n \t\t#address-cells = <1>;\n--- a/arch/arm/boot/dts/bcm958525xmc.dts\n+++ b/arch/arm/boot/dts/bcm958525xmc.dts\n@@ -150,6 +150,7 @@\n };\n \n &qspi {\n+\tstatus = \"okay\";\n \tbspi-sel = <0>;\n \tflash: m25p80@0 {\n \t\t#address-cells = <1>;\n--- a/arch/arm/boot/dts/bcm958622hr.dts\n+++ b/arch/arm/boot/dts/bcm958622hr.dts\n@@ -138,6 +138,7 @@\n };\n \n &qspi {\n+\tstatus = \"okay\";\n \tbspi-sel = <0>;\n \tflash: m25p80@0 {\n \t\t#address-cells = <1>;\n--- a/arch/arm/boot/dts/bcm958623hr.dts\n+++ b/arch/arm/boot/dts/bcm958623hr.dts\n@@ -142,6 +142,7 @@\n };\n \n &qspi {\n+\tstatus = \"okay\";\n \tbspi-sel = <0>;\n \tflash: m25p80@0 {\n \t\t#address-cells = <1>;\n--- a/arch/arm/boot/dts/bcm958625hr.dts\n+++ b/arch/arm/boot/dts/bcm958625hr.dts\n@@ -149,6 +149,7 @@\n };\n \n &qspi {\n+\tstatus = \"okay\";\n \tbspi-sel = <0>;\n \tflash: m25p80@0 {\n \t\t#address-cells = <1>;\n--- a/arch/arm/boot/dts/bcm958625k.dts\n+++ b/arch/arm/boot/dts/bcm958625k.dts\n@@ -153,6 +153,7 @@\n };\n \n &qspi {\n+\tstatus = \"okay\";\n \tbspi-sel = <0>;\n \tflash: m25p80@0 {\n \t\t#address-cells = <1>;\n--- a/arch/arm/boot/dts/bcm988312hr.dts\n+++ b/arch/arm/boot/dts/bcm988312hr.dts\n@@ -138,6 +138,7 @@\n };\n \n &qspi {\n+\tstatus = \"okay\";\n \tbspi-sel = <0>;\n \tflash: m25p80@0 {\n \t\t#address-cells = <1>;\n"
  },
  {
    "path": "target/linux/bcm53xx/patches-5.15/030-v5.15-0004-ARM-dts-NSP-add-MDIO-bus-controller-node.patch",
    "content": "From 236b31b1d84eb0e4f10c5f113a2675529456f919 Mon Sep 17 00:00:00 2001\nFrom: Matthew Hagan <mnhagan88@gmail.com>\nDate: Sun, 13 Jun 2021 10:46:36 +0100\nSubject: [PATCH] ARM: dts: NSP: add MDIO bus controller node\n\nThis patch adds the node for the MDIO bus controller, present on the NSP\nSoC.\n\nSigned-off-by: Matthew Hagan <mnhagan88@gmail.com>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n arch/arm/boot/dts/bcm-nsp.dtsi | 7 +++++++\n 1 file changed, 7 insertions(+)\n\n--- a/arch/arm/boot/dts/bcm-nsp.dtsi\n+++ b/arch/arm/boot/dts/bcm-nsp.dtsi\n@@ -363,6 +363,13 @@\n \t\t\tstatus = \"disabled\";\n \t\t};\n \n+\t\tmdio: mdio@32000 {\n+\t\t\tcompatible = \"brcm,iproc-mdio\";\n+\t\t\treg = <0x32000 0x8>;\n+\t\t\t#size-cells = <0>;\n+\t\t\t#address-cells = <1>;\n+\t\t};\n+\n \t\trng: rng@33000 {\n \t\t\tcompatible = \"brcm,bcm-nsp-rng\";\n \t\t\treg = <0x33000 0x14>;\n"
  },
  {
    "path": "target/linux/bcm53xx/patches-5.15/030-v5.15-0005-ARM-dts-NSP-Move-USB3-PHY-to-internal-MDIO-bus.patch",
    "content": "From 1c615401bddb1be21e1d375aaa071680f40f1ae2 Mon Sep 17 00:00:00 2001\nFrom: Matthew Hagan <mnhagan88@gmail.com>\nDate: Sun, 13 Jun 2021 10:46:37 +0100\nSubject: [PATCH] ARM: dts: NSP: Move USB3 PHY to internal MDIO bus\n\nThis patch largely replicates Vivek Unune's patch \"ARM: dts:\nBCM5301X:Make usb3 phy use mdio phy driver\"[1] for the NSP platform,\nwhereby we need to create an mdio-mux to facilitate switches\nconfigured via external MDIO, in this case on the Meraki MX65.\n\nHowever in doing so, we are creating an overlap with usb3_phy's\nccb-mii range. To resolve this, usb3_phy should be moved to a child\nnode of the internal MDIO bus. The result is heavily based upon Vivek's\npatch. This has also been cross-referenced with Yendapally Reddy's\nearlier work which utilised the subsequently dropped brcm,nsp-usb3-phy\ndriver: \"[PATCH v2 4/4] arm: dts: nsp: Add USB nodes to device tree\"\n[2]. Finally, this change provides conformance to the bcm-ns-usb3-phy\ndocumentation, utilising the required usb3-dmp-syscon property. Note\nthat support for the deprecated ccb-mii bindings has been dropped as of\n\"phy: phy-bcm-ns-usb3: drop support for deprecated DT binding\"[3].\n\n[1] https://lore.kernel.org/patchwork/patch/933971/\n[2] https://www.spinics.net/lists/arm-kernel/msg555132.html\n[3] https://lore.kernel.org/linux-devicetree/20201113113423.9466-1-zajec5@gmail.com/\n\nSigned-off-by: Matthew Hagan <mnhagan88@gmail.com>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n arch/arm/boot/dts/bcm-nsp.dtsi | 38 +++++++++++++++++++++++++++-------\n 1 file changed, 31 insertions(+), 7 deletions(-)\n\n--- a/arch/arm/boot/dts/bcm-nsp.dtsi\n+++ b/arch/arm/boot/dts/bcm-nsp.dtsi\n@@ -370,6 +370,35 @@\n \t\t\t#address-cells = <1>;\n \t\t};\n \n+\t\tmdio-mux@32000 {\n+\t\t\tcompatible = \"mdio-mux-mmioreg\";\n+\t\t\treg = <0x32000 0x4>;\n+\t\t\tmux-mask = <0x200>;\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tmdio-parent-bus = <&mdio>;\n+\n+\t\t\tmdio_int: mdio@0 {\n+\t\t\t\treg = <0x0>;\n+\t\t\t\t#address-cells = <1>;\n+\t\t\t\t#size-cells = <0>;\n+\n+\t\t\t\tusb3_phy: usb3-phy@10 {\n+\t\t\t\t\tcompatible = \"brcm,ns-bx-usb3-phy\";\n+\t\t\t\t\treg = <0x10>;\n+\t\t\t\t\tusb3-dmp-syscon = <&usb3_dmp>;\n+\t\t\t\t\t#phy-cells = <0>;\n+\t\t\t\t\tstatus = \"disabled\";\n+\t\t\t\t};\n+\t\t\t};\n+\n+\t\t\tmdio_ext: mdio@200 {\n+\t\t\t\treg = <0x200>;\n+\t\t\t\t#address-cells = <1>;\n+\t\t\t\t#size-cells = <0>;\n+\t\t\t};\n+\t\t};\n+\n \t\trng: rng@33000 {\n \t\t\tcompatible = \"brcm,bcm-nsp-rng\";\n \t\t\treg = <0x33000 0x14>;\n@@ -528,13 +557,8 @@\n \t\t\t};\n \t\t};\n \n-\t\tusb3_phy: usb3-phy@104000 {\n-\t\t\tcompatible = \"brcm,ns-bx-usb3-phy\";\n-\t\t\treg = <0x104000 0x1000>,\n-\t\t\t      <0x032000 0x1000>;\n-\t\t\treg-names = \"dmp\", \"ccb-mii\";\n-\t\t\t#phy-cells = <0>;\n-\t\t\tstatus = \"disabled\";\n+\t\tusb3_dmp: syscon@104000 {\n+\t\t\treg = <0x104000 0x1000>;\n \t\t};\n \t};\n \n"
  },
  {
    "path": "target/linux/bcm53xx/patches-5.15/030-v5.15-0006-ARM-dts-NSP-Add-common-bindings-for-MX64-MX65.patch",
    "content": "From f111016a8293b968f05450fec83020c94d0f88c2 Mon Sep 17 00:00:00 2001\nFrom: Matthew Hagan <mnhagan88@gmail.com>\nDate: Fri, 6 Aug 2021 21:44:32 +0100\nSubject: [PATCH] ARM: dts: NSP: Add common bindings for MX64/MX65\n\nThese bindings are required for all Meraki MX64/MX65 devices. These\ncommon bindings include memory (2GB), PWM LEDs, AMAC, I2C (AT24), NAND\npartitions, EHCI, OHCI and pinctrl.\n\nSigned-off-by: Matthew Hagan <mnhagan88@gmail.com>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n .../dts/bcm958625-meraki-mx6x-common.dtsi     | 129 ++++++++++++++++++\n 1 file changed, 129 insertions(+)\n create mode 100644 arch/arm/boot/dts/bcm958625-meraki-mx6x-common.dtsi\n\n--- /dev/null\n+++ b/arch/arm/boot/dts/bcm958625-meraki-mx6x-common.dtsi\n@@ -0,0 +1,129 @@\n+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n+/*\n+ * Common Bindings for Cisco Meraki MX64 (Kingpin) and MX65 (Alamo) devices.\n+ *\n+ * Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com>\n+ */\n+\n+#include \"bcm-nsp.dtsi\"\n+#include <dt-bindings/gpio/gpio.h>\n+#include <dt-bindings/input/input.h>\n+#include <dt-bindings/leds/common.h>\n+\n+/ {\n+\tpwm-leds {\n+\t\tcompatible = \"pwm-leds\";\n+\n+\t\tled-1 {\n+\t\t\tfunction = LED_FUNCTION_INDICATOR;\n+\t\t\tcolor = <LED_COLOR_ID_RED>;\n+\t\t\tpwms = <&pwm 1 50000>;\n+\t\t\tmax-brightness = <255>;\n+\t\t};\n+\n+\t\tled-2 {\n+\t\t\tfunction = LED_FUNCTION_INDICATOR;\n+\t\t\tcolor = <LED_COLOR_ID_GREEN>;\n+\t\t\tpwms = <&pwm 2 50000>;\n+\t\t\tmax-brightness = <255>;\n+\t\t};\n+\n+\t\tled-3 {\n+\t\t\tfunction = LED_FUNCTION_INDICATOR;\n+\t\t\tcolor = <LED_COLOR_ID_BLUE>;\n+\t\t\tpwms = <&pwm 3 50000>;\n+\t\t\tmax-brightness = <255>;\n+\t\t};\n+\t};\n+};\n+\n+&amac2 {\n+\tstatus = \"okay\";\n+};\n+\n+&ehci0 {\n+\tstatus = \"okay\";\n+};\n+\n+&i2c0 {\n+\tstatus = \"okay\";\n+\n+\tat24@50 {\n+\t\tcompatible = \"atmel,24c64\";\n+\t\treg = <0x50>;\n+\t\tpagesize = <32>;\n+\t\tread-only;\n+\t};\n+};\n+\n+&nand_controller {\n+\tnand@0 {\n+\t\tcompatible = \"brcm,nandcs\";\n+\t\treg = <0>;\n+\t\tnand-on-flash-bbt;\n+\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <1>;\n+\n+\t\tnand-ecc-strength = <24>;\n+\t\tnand-ecc-step-size = <1024>;\n+\n+\t\tbrcm,nand-oob-sector-size = <27>;\n+\n+\t\tpartition@0 {\n+\t\t\tlabel = \"u-boot\";\n+\t\t\treg = <0x0 0x80000>;\n+\t\t\tread-only;\n+\t\t};\n+\n+\t\tpartition@80000 {\n+\t\t\tlabel = \"shmoo\";\n+\t\t\treg = <0x80000 0x80000>;\n+\t\t\tread-only;\n+\t\t};\n+\n+\t\tpartition@100000 {\n+\t\t\tlabel = \"bootkernel1\";\n+\t\t\treg = <0x100000 0x300000>;\n+\t\t};\n+\n+\t\tpartition@400000 {\n+\t\t\tlabel = \"nvram\";\n+\t\t\treg = <0x400000 0x100000>;\n+\t\t};\n+\n+\t\tpartition@500000 {\n+\t\t\tlabel = \"bootkernel2\";\n+\t\t\treg = <0x500000 0x300000>;\n+\t\t};\n+\n+\t\tpartition@800000 {\n+\t\t\tlabel = \"ubi\";\n+\t\t\treg = <0x800000 0x3f700000>;\n+\t\t};\n+\t};\n+};\n+\n+&ohci0 {\n+\tstatus = \"okay\";\n+};\n+\n+&pinctrl {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pwm_leds>;\n+\n+\tpwm_leds: pwm_leds {\n+\t\tfunction = \"pwm\";\n+\t\tgroups = \"pwm1_grp\", \"pwm2_grp\", \"pwm3_grp\";\n+\t};\n+};\n+\n+&pwm {\n+\tstatus = \"okay\";\n+\t#pwm-cells = <2>;\n+};\n+\n+&uart0 {\n+\tclock-frequency = <62500000>;\n+\tstatus = \"okay\";\n+};\n"
  },
  {
    "path": "target/linux/bcm53xx/patches-5.15/030-v5.15-0007-ARM-dts-NSP-Add-Ax-stepping-modifications.patch",
    "content": "From 2addf9266a1d0f4ba59c9868b3effcd50de441a4 Mon Sep 17 00:00:00 2001\nFrom: Matthew Hagan <mnhagan88@gmail.com>\nDate: Fri, 6 Aug 2021 21:44:33 +0100\nSubject: [PATCH] ARM: dts: NSP: Add Ax stepping modifications\n\nWhile uncommon, some Ax NSP SoCs exist in the wild. This stepping\nrequires a modified secondary CPU boot-reg and removal of DMA coherency\nproperties. Without these modifications, the secondary CPU will be\ninactive and many peripherals will exhibit undefined behaviour.\n\nSigned-off-by: Matthew Hagan <mnhagan88@gmail.com>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n arch/arm/boot/dts/bcm-nsp-ax.dtsi | 70 +++++++++++++++++++++++++++++++\n 1 file changed, 70 insertions(+)\n create mode 100644 arch/arm/boot/dts/bcm-nsp-ax.dtsi\n\n--- /dev/null\n+++ b/arch/arm/boot/dts/bcm-nsp-ax.dtsi\n@@ -0,0 +1,70 @@\n+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n+/*\n+ * Broadcom Northstar Plus Ax stepping-specific bindings.\n+ * Notable differences from B0+ are the secondary-boot-reg and\n+ * lack of DMA coherency.\n+ */\n+\n+&cpu1 {\n+\tsecondary-boot-reg = <0xffff042c>;\n+};\n+\n+&dma {\n+\t/delete-property/ dma-coherent;\n+};\n+\n+&sdio {\n+\t/delete-property/ dma-coherent;\n+};\n+\n+&amac0 {\n+\t/delete-property/ dma-coherent;\n+};\n+\n+&amac1 {\n+\t/delete-property/ dma-coherent;\n+};\n+\n+&amac2 {\n+\t/delete-property/ dma-coherent;\n+};\n+\n+&ehci0 {\n+\t/delete-property/ dma-coherent;\n+};\n+\n+&mailbox {\n+\t/delete-property/ dma-coherent;\n+};\n+\n+&xhci {\n+\t/delete-property/ dma-coherent;\n+};\n+\n+&ehci0 {\n+\t/delete-property/ dma-coherent;\n+};\n+\n+&ohci0 {\n+\t/delete-property/ dma-coherent;\n+};\n+\n+&i2c0 {\n+\t/delete-property/ dma-coherent;\n+};\n+\n+&sata {\n+\t/delete-property/ dma-coherent;\n+};\n+\n+&pcie0 {\n+\t/delete-property/ dma-coherent;\n+};\n+\n+&pcie1 {\n+\t/delete-property/ dma-coherent;\n+};\n+\n+&pcie2 {\n+\t/delete-property/ dma-coherent;\n+};\n"
  },
  {
    "path": "target/linux/bcm53xx/patches-5.15/030-v5.15-0008-ARM-dts-NSP-Add-DT-files-for-Meraki-MX64-series.patch",
    "content": "From 3f902645280baf0d7dab57c227cc14f43edb45ef Mon Sep 17 00:00:00 2001\nFrom: Matthew Hagan <mnhagan88@gmail.com>\nDate: Fri, 6 Aug 2021 21:44:34 +0100\nSubject: [PATCH] ARM: dts: NSP: Add DT files for Meraki MX64 series\n\nMX64 & MX64W Hardware info:\n  - CPU: Broadcom BCM58625 Cortex A9 @ 1200Mhz\n  - RAM: 2 GB (4 x 4Gb SK Hynix H5TC4G83CFR)\n  - Storage: 1 GB (Micron MT29F8G08ABACA)\n  - Networking: BCM58625 internal switch (5x 1GbE ports)\n  - USB: 1x USB2.0\n  - Serial: Internal header\n  - WLAN(MX64W only): 2x Broadcom BCM43520KMLG on the PCI bus\n\nThis patch adds the Meraki MX64 series-specific bindings. Since some\ndevices make use of the older A0 SoC, changes need to be made to\naccommodate this case, including removal of coherency options and\nmodification to the secondary-boot-reg.\n\nSigned-off-by: Matthew Hagan <mnhagan88@gmail.com>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n arch/arm/boot/dts/Makefile                    |   4 +\n .../boot/dts/bcm958625-meraki-kingpin.dtsi    | 163 ++++++++++++++++++\n .../arm/boot/dts/bcm958625-meraki-mx64-a0.dts |  25 +++\n arch/arm/boot/dts/bcm958625-meraki-mx64.dts   |  24 +++\n .../boot/dts/bcm958625-meraki-mx64w-a0.dts    |  33 ++++\n arch/arm/boot/dts/bcm958625-meraki-mx64w.dts  |  32 ++++\n 6 files changed, 281 insertions(+)\n create mode 100644 arch/arm/boot/dts/bcm958625-meraki-kingpin.dtsi\n create mode 100644 arch/arm/boot/dts/bcm958625-meraki-mx64-a0.dts\n create mode 100644 arch/arm/boot/dts/bcm958625-meraki-mx64.dts\n create mode 100644 arch/arm/boot/dts/bcm958625-meraki-mx64w-a0.dts\n create mode 100644 arch/arm/boot/dts/bcm958625-meraki-mx64w.dts\n\n--- a/arch/arm/boot/dts/Makefile\n+++ b/arch/arm/boot/dts/Makefile\n@@ -157,6 +157,10 @@ dtb-$(CONFIG_ARCH_BCM_NSP) += \\\n \tbcm958525xmc.dtb \\\n \tbcm958622hr.dtb \\\n \tbcm958623hr.dtb \\\n+\tbcm958625-meraki-mx64.dtb \\\n+\tbcm958625-meraki-mx64-a0.dtb \\\n+\tbcm958625-meraki-mx64w.dtb \\\n+\tbcm958625-meraki-mx64w-a0.dtb \\\n \tbcm958625hr.dtb \\\n \tbcm988312hr.dtb \\\n \tbcm958625k.dtb\n--- /dev/null\n+++ b/arch/arm/boot/dts/bcm958625-meraki-kingpin.dtsi\n@@ -0,0 +1,163 @@\n+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n+/*\n+ * Device Tree Bindings for Cisco Meraki MX64 series (Kingpin).\n+ *\n+ * Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com>\n+ */\n+\n+#include \"bcm958625-meraki-mx6x-common.dtsi\"\n+\n+/ {\n+\n+\tkeys {\n+\t\tcompatible = \"gpio-keys-polled\";\n+\t\tautorepeat;\n+\t\tpoll-interval = <20>;\n+\n+\t\treset {\n+\t\t\tlabel = \"reset\";\n+\t\t\tlinux,code = <KEY_RESTART>;\n+\t\t\tgpios = <&gpioa 6 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\t};\n+\n+\tleds {\n+\t\tcompatible = \"gpio-leds\";\n+\n+\t\tled-0 {\n+\t\t\t/* green:lan1-left */\n+\t\t\tfunction = LED_FUNCTION_ACTIVITY;\n+\t\t\tfunction-enumerator = <0>;\n+\t\t\tcolor = <LED_COLOR_ID_GREEN>;\n+\t\t\tgpios = <&gpioa 19 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\n+\t\tled-1 {\n+\t\t\t/* green:lan1-right */\n+\t\t\tfunction = LED_FUNCTION_ACTIVITY;\n+\t\t\tfunction-enumerator = <1>;\n+\t\t\tcolor = <LED_COLOR_ID_GREEN>;\n+\t\t\tgpios = <&gpioa 18 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\n+\t\tled-2 {\n+\t\t\t/* green:lan2-left */\n+\t\t\tfunction = LED_FUNCTION_ACTIVITY;\n+\t\t\tfunction-enumerator = <2>;\n+\t\t\tcolor = <LED_COLOR_ID_GREEN>;\n+\t\t\tgpios = <&gpioa 24 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\n+\t\tled-3 {\n+\t\t\t/* green:lan2-right */\n+\t\t\tfunction = LED_FUNCTION_ACTIVITY;\n+\t\t\tfunction-enumerator = <3>;\n+\t\t\tcolor = <LED_COLOR_ID_GREEN>;\n+\t\t\tgpios = <&gpioa 20 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\n+\t\tled-4 {\n+\t\t\t/* green:lan3-left */\n+\t\t\tfunction = LED_FUNCTION_ACTIVITY;\n+\t\t\tfunction-enumerator = <4>;\n+\t\t\tcolor = <LED_COLOR_ID_GREEN>;\n+\t\t\tgpios = <&gpioa 26 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\n+\t\tled-5 {\n+\t\t\t/* green:lan3-right */\n+\t\t\tfunction = LED_FUNCTION_ACTIVITY;\n+\t\t\tfunction-enumerator = <5>;\n+\t\t\tcolor = <LED_COLOR_ID_GREEN>;\n+\t\t\tgpios = <&gpioa 25 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\n+\t\tled-6 {\n+\t\t\t/* green:lan4-left */\n+\t\t\tfunction = LED_FUNCTION_ACTIVITY;\n+\t\t\tfunction-enumerator = <6>;\n+\t\t\tcolor = <LED_COLOR_ID_GREEN>;\n+\t\t\tgpios = <&gpioa 28 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\n+\t\tled-7 {\n+\t\t\t/* green:lan4-right */\n+\t\t\tfunction = LED_FUNCTION_ACTIVITY;\n+\t\t\tfunction-enumerator = <7>;\n+\t\t\tcolor = <LED_COLOR_ID_GREEN>;\n+\t\t\tgpios = <&gpioa 27 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\n+\t\tled-8 {\n+\t\t\t/* green:wan-left */\n+\t\t\tfunction = LED_FUNCTION_ACTIVITY;\n+\t\t\tfunction-enumerator = <8>;\n+\t\t\tcolor = <LED_COLOR_ID_GREEN>;\n+\t\t\tgpios = <&gpioa 30 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\n+\t\tled-9 {\n+\t\t\t/* green:wan-right */\n+\t\t\tfunction = LED_FUNCTION_ACTIVITY;\n+\t\t\tfunction-enumerator = <9>;\n+\t\t\tcolor = <LED_COLOR_ID_GREEN>;\n+\t\t\tgpios = <&gpioa 29 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\n+\t\tled-a {\n+\t\t\t/* amber:power */\n+\t\t\tfunction = LED_FUNCTION_POWER;\n+\t\t\tcolor = <LED_COLOR_ID_AMBER>;\n+\t\t\tgpios = <&gpioa 0 GPIO_ACTIVE_LOW>;\n+\t\t\tdefault-state = \"on\";\n+\t\t};\n+\n+\t\tled-b {\n+\t\t\t/* white:status */\n+\t\t\tfunction = LED_FUNCTION_STATUS;\n+\t\t\tcolor = <LED_COLOR_ID_WHITE>;\n+\t\t\tgpios = <&gpioa 31 GPIO_ACTIVE_HIGH>;\n+\t\t};\n+\t};\n+};\n+\n+&srab {\n+\tcompatible = \"brcm,bcm58625-srab\", \"brcm,nsp-srab\";\n+\tstatus = \"okay\";\n+\n+\tports {\n+\t\tport@0 {\n+\t\t\tlabel = \"lan1\";\n+\t\t\treg = <0>;\n+\t\t};\n+\n+\t\tport@1 {\n+\t\t\tlabel = \"lan2\";\n+\t\t\treg = <1>;\n+\t\t};\n+\n+\t\tport@2 {\n+\t\t\tlabel = \"lan3\";\n+\t\t\treg = <2>;\n+\t\t};\n+\n+\t\tport@3 {\n+\t\t\tlabel = \"lan4\";\n+\t\t\treg = <3>;\n+\t\t};\n+\n+\t\tport@4 {\n+\t\t\tlabel = \"wan\";\n+\t\t\treg = <4>;\n+\t\t};\n+\n+\t\tport@8 {\n+\t\t\tethernet = <&amac2>;\n+\t\t\treg = <8>;\n+\t\t\tfixed-link {\n+\t\t\t\tspeed = <1000>;\n+\t\t\t\tfull-duplex;\n+\t\t\t};\n+\t\t};\n+\t};\n+};\n--- /dev/null\n+++ b/arch/arm/boot/dts/bcm958625-meraki-mx64-a0.dts\n@@ -0,0 +1,25 @@\n+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n+/*\n+ * Device Tree Bindings for Cisco Meraki MX64 with A0 SoC.\n+ *\n+ * Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com>\n+ */\n+\n+/dts-v1/;\n+\n+#include \"bcm958625-meraki-kingpin.dtsi\"\n+#include \"bcm-nsp-ax.dtsi\"\n+\n+/ {\n+\tmodel = \"Cisco Meraki MX64(A0)\";\n+\tcompatible = \"meraki,mx64-a0\", \"brcm,bcm58625\", \"brcm,nsp\";\n+\n+\tchosen {\n+\t\tstdout-path = \"serial0:115200n8\";\n+\t};\n+\n+\tmemory@60000000 {\n+\t\tdevice_type = \"memory\";\n+\t\treg = <0x60000000 0x80000000>;\n+\t};\n+};\n--- /dev/null\n+++ b/arch/arm/boot/dts/bcm958625-meraki-mx64.dts\n@@ -0,0 +1,24 @@\n+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n+/*\n+ * Device Tree Bindings for Cisco Meraki MX64 with B0+ SoC.\n+ *\n+ * Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com>\n+ */\n+\n+/dts-v1/;\n+\n+#include \"bcm958625-meraki-kingpin.dtsi\"\n+\n+/ {\n+\tmodel = \"Cisco Meraki MX64\";\n+\tcompatible = \"meraki,mx64\", \"brcm,bcm58625\", \"brcm,nsp\";\n+\n+\tchosen {\n+\t\tstdout-path = \"serial0:115200n8\";\n+\t};\n+\n+\tmemory@60000000 {\n+\t\tdevice_type = \"memory\";\n+\t\treg = <0x60000000 0x80000000>;\n+\t};\n+};\n--- /dev/null\n+++ b/arch/arm/boot/dts/bcm958625-meraki-mx64w-a0.dts\n@@ -0,0 +1,33 @@\n+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n+/*\n+ * Device Tree Bindings for Cisco Meraki MX64W with A0 SoC.\n+ *\n+ * Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com>\n+ */\n+\n+/dts-v1/;\n+\n+#include \"bcm958625-meraki-kingpin.dtsi\"\n+#include \"bcm-nsp-ax.dtsi\"\n+\n+/ {\n+\tmodel = \"Cisco Meraki MX64W(A0)\";\n+\tcompatible = \"meraki,mx64w-a0\", \"brcm,bcm58625\", \"brcm,nsp\";\n+\n+\tchosen {\n+\t\tstdout-path = \"serial0:115200n8\";\n+\t};\n+\n+\tmemory@60000000 {\n+\t\tdevice_type = \"memory\";\n+\t\treg = <0x60000000 0x80000000>;\n+\t};\n+};\n+\n+&pcie0 {\n+\tstatus = \"okay\";\n+};\n+\n+&pcie1 {\n+\tstatus = \"okay\";\n+};\n--- /dev/null\n+++ b/arch/arm/boot/dts/bcm958625-meraki-mx64w.dts\n@@ -0,0 +1,32 @@\n+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n+/*\n+ * Device Tree Bindings for Cisco Meraki MX64W with B0+ SoC.\n+ *\n+ * Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com>\n+ */\n+\n+/dts-v1/;\n+\n+#include \"bcm958625-meraki-kingpin.dtsi\"\n+\n+/ {\n+\tmodel = \"Cisco Meraki MX64W\";\n+\tcompatible = \"meraki,mx64w\", \"brcm,bcm58625\", \"brcm,nsp\";\n+\n+\tchosen {\n+\t\tstdout-path = \"serial0:115200n8\";\n+\t};\n+\n+\tmemory@60000000 {\n+\t\tdevice_type = \"memory\";\n+\t\treg = <0x60000000 0x80000000>;\n+\t};\n+};\n+\n+&pcie0 {\n+\tstatus = \"okay\";\n+};\n+\n+&pcie1 {\n+\tstatus = \"okay\";\n+};\n"
  },
  {
    "path": "target/linux/bcm53xx/patches-5.15/030-v5.15-0009-ARM-dts-NSP-Add-DT-files-for-Meraki-MX65-series.patch",
    "content": "From 702a8f4744ed5b480f2b2411858184afdb10f9fd Mon Sep 17 00:00:00 2001\nFrom: Matthew Hagan <mnhagan88@gmail.com>\nDate: Fri, 6 Aug 2021 21:44:35 +0100\nSubject: [PATCH] ARM: dts: NSP: Add DT files for Meraki MX65 series\n\nMX65 & MX65W Hardware info:\n  - CPU: Broadcom BCM58625 Cortex A9 @ 1200Mhz\n  - RAM: 2 GB (4 x 4Gb SK Hynix H5TC4G83CFR)\n  - Storage: 1 GB (Micron MT29F8G08ABACA)\n  - Networking: BCM58625 switch (2x 1GbE ports)\n    2x Qualcomm QCA8337 switches (10x 1GbE ports total)\n  - PSE: Broadcom BCM59111KMLG connected to LAN ports 11 & 12\n  - USB: 1x USB2.0\n  - Serial: Internal header\n  - WLAN(MX65W Only): 2x Broadcom BCM43520KMLG on the PCI bus.\n\nNote that a driver and firmware image for the BCM59111 PSE has been\nreleased under GPL, but this is not present in the kernel.\n\nSigned-off-by: Matthew Hagan <mnhagan88@gmail.com>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n arch/arm/boot/dts/Makefile                    |   2 +\n arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi | 279 ++++++++++++++++++\n arch/arm/boot/dts/bcm958625-meraki-mx65.dts   |  24 ++\n arch/arm/boot/dts/bcm958625-meraki-mx65w.dts  |  32 ++\n 4 files changed, 337 insertions(+)\n create mode 100644 arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi\n create mode 100644 arch/arm/boot/dts/bcm958625-meraki-mx65.dts\n create mode 100644 arch/arm/boot/dts/bcm958625-meraki-mx65w.dts\n\n--- a/arch/arm/boot/dts/Makefile\n+++ b/arch/arm/boot/dts/Makefile\n@@ -161,6 +161,8 @@ dtb-$(CONFIG_ARCH_BCM_NSP) += \\\n \tbcm958625-meraki-mx64-a0.dtb \\\n \tbcm958625-meraki-mx64w.dtb \\\n \tbcm958625-meraki-mx64w-a0.dtb \\\n+\tbcm958625-meraki-mx65.dtb \\\n+\tbcm958625-meraki-mx65w.dtb \\\n \tbcm958625hr.dtb \\\n \tbcm988312hr.dtb \\\n \tbcm958625k.dtb\n--- /dev/null\n+++ b/arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi\n@@ -0,0 +1,279 @@\n+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n+/*\n+ * Device Tree Bindings for Cisco Meraki MX65 series (Alamo).\n+ *\n+ * Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com>\n+ */\n+\n+#include \"bcm958625-meraki-mx6x-common.dtsi\"\n+\n+/ {\n+\tkeys {\n+\t\tcompatible = \"gpio-keys-polled\";\n+\t\tautorepeat;\n+\t\tpoll-interval = <20>;\n+\n+\t\treset {\n+\t\t\tlabel = \"reset\";\n+\t\t\tlinux,code = <KEY_RESTART>;\n+\t\t\tgpios = <&gpioa 8 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\t};\n+\n+\tleds {\n+\t\tcompatible = \"gpio-leds\";\n+\n+\t\tled-0 {\n+\t\t\t/* green:wan1-left */\n+\t\t\tfunction = LED_FUNCTION_ACTIVITY;\n+\t\t\tfunction-enumerator = <0>;\n+\t\t\tcolor = <LED_COLOR_ID_GREEN>;\n+\t\t\tgpios = <&gpioa 25 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\n+\t\tled-1 {\n+\t\t\t/* green:wan1-right */\n+\t\t\tfunction = LED_FUNCTION_ACTIVITY;\n+\t\t\tfunction-enumerator = <1>;\n+\t\t\tcolor = <LED_COLOR_ID_GREEN>;\n+\t\t\tgpios = <&gpioa 24 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\n+\t\tled-2 {\n+\t\t\t/* green:wan2-left */\n+\t\t\tfunction = LED_FUNCTION_ACTIVITY;\n+\t\t\tfunction-enumerator = <2>;\n+\t\t\tcolor = <LED_COLOR_ID_GREEN>;\n+\t\t\tgpios = <&gpioa 27 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\n+\t\tled-3 {\n+\t\t\t/* green:wan2-right */\n+\t\t\tfunction = LED_FUNCTION_ACTIVITY;\n+\t\t\tfunction-enumerator = <3>;\n+\t\t\tcolor = <LED_COLOR_ID_GREEN>;\n+\t\t\tgpios = <&gpioa 26 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\n+\t\tled-4 {\n+\t\t\t/* amber:power */\n+\t\t\tfunction = LED_FUNCTION_POWER;\n+\t\t\tcolor = <LED_COLOR_ID_AMBER>;\n+\t\t\tgpios = <&gpioa 3 GPIO_ACTIVE_HIGH>;\n+\t\t\tdefault-state = \"on\";\n+\t\t};\n+\n+\t\tled-5 {\n+\t\t\t/* white:status */\n+\t\t\tfunction = LED_FUNCTION_STATUS;\n+\t\t\tcolor = <LED_COLOR_ID_WHITE>;\n+\t\t\tgpios = <&gpioa 31 GPIO_ACTIVE_HIGH>;\n+\t\t};\n+\t};\n+\n+\tmdio-mii-mux {\n+\t\tcompatible = \"mdio-mux-mmioreg\";\n+\t\treg = <0x1803f1c0 0x4>;\n+\t\tmux-mask = <0x2000>;\n+\t\tmdio-parent-bus = <&mdio_ext>;\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\n+\t\tmdio@0 {\n+\t\t\treg = <0x0>;\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tphy_port6: phy@0 {\n+\t\t\t\treg = <0>;\n+\t\t\t};\n+\n+\t\t\tphy_port7: phy@1 {\n+\t\t\t\treg = <1>;\n+\t\t\t};\n+\n+\t\t\tphy_port8: phy@2 {\n+\t\t\t\treg = <2>;\n+\t\t\t};\n+\n+\t\t\tphy_port9: phy@3 {\n+\t\t\t\treg = <3>;\n+\t\t\t};\n+\n+\t\t\tphy_port10: phy@4 {\n+\t\t\t\treg = <4>;\n+\t\t\t};\n+\n+\t\t\tswitch@10 {\n+\t\t\t\tcompatible = \"qca,qca8337\";\n+\t\t\t\treg = <0x10>;\n+\t\t\t\tdsa,member = <1 0>;\n+\n+\t\t\t\tports {\n+\t\t\t\t\t#address-cells = <1>;\n+\t\t\t\t\t#size-cells = <0>;\n+\t\t\t\t\tport@0 {\n+\t\t\t\t\t\treg = <0>;\n+\t\t\t\t\t\tethernet = <&sgmii1>;\n+\t\t\t\t\t\tphy-mode = \"sgmii\";\n+\t\t\t\t\t\tfixed-link {\n+\t\t\t\t\t\t\tspeed = <1000>;\n+\t\t\t\t\t\t\tfull-duplex;\n+\t\t\t\t\t\t};\n+\t\t\t\t\t};\n+\n+\t\t\t\t\tport@1 {\n+\t\t\t\t\t\treg = <1>;\n+\t\t\t\t\t\tlabel = \"lan8\";\n+\t\t\t\t\t\tphy-handle = <&phy_port6>;\n+\t\t\t\t\t};\n+\n+\t\t\t\t\tport@2 {\n+\t\t\t\t\t\treg = <2>;\n+\t\t\t\t\t\tlabel = \"lan9\";\n+\t\t\t\t\t\tphy-handle = <&phy_port7>;\n+\t\t\t\t\t};\n+\n+\t\t\t\t\tport@3 {\n+\t\t\t\t\t\treg = <3>;\n+\t\t\t\t\t\tlabel = \"lan10\";\n+\t\t\t\t\t\tphy-handle = <&phy_port8>;\n+\t\t\t\t\t};\n+\n+\t\t\t\t\tport@4 {\n+\t\t\t\t\t\treg = <4>;\n+\t\t\t\t\t\tlabel = \"lan11\";\n+\t\t\t\t\t\tphy-handle = <&phy_port9>;\n+\t\t\t\t\t};\n+\n+\t\t\t\t\tport@5 {\n+\t\t\t\t\t\treg = <5>;\n+\t\t\t\t\t\tlabel = \"lan12\";\n+\t\t\t\t\t\tphy-handle = <&phy_port10>;\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\t\t\t};\n+\t\t};\n+\n+\t\tmdio-mii@2000 {\n+\t\t\treg = <0x2000>;\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tphy_port1: phy@0 {\n+\t\t\t\treg = <0>;\n+\t\t\t};\n+\n+\t\t\tphy_port2: phy@1 {\n+\t\t\t\treg = <1>;\n+\t\t\t};\n+\n+\t\t\tphy_port3: phy@2 {\n+\t\t\t\treg = <2>;\n+\t\t\t};\n+\n+\t\t\tphy_port4: phy@3 {\n+\t\t\t\treg = <3>;\n+\t\t\t};\n+\n+\t\t\tphy_port5: phy@4 {\n+\t\t\t\treg = <4>;\n+\t\t\t};\n+\n+\t\t\tswitch@10 {\n+\t\t\t\tcompatible = \"qca,qca8337\";\n+\t\t\t\treg = <0x10>;\n+\t\t\t\tdsa,member = <2 0>;\n+\n+\t\t\t\tports {\n+\t\t\t\t\t#address-cells = <1>;\n+\t\t\t\t\t#size-cells = <0>;\n+\t\t\t\t\tport@0 {\n+\t\t\t\t\t\treg = <0>;\n+\t\t\t\t\t\tethernet = <&sgmii0>;\n+\t\t\t\t\t\tphy-mode = \"sgmii\";\n+\t\t\t\t\t\tfixed-link {\n+\t\t\t\t\t\t\tspeed = <1000>;\n+\t\t\t\t\t\t\tfull-duplex;\n+\t\t\t\t\t\t};\n+\t\t\t\t\t};\n+\n+\t\t\t\t\tport@1 {\n+\t\t\t\t\t\treg = <1>;\n+\t\t\t\t\t\tlabel = \"lan3\";\n+\t\t\t\t\t\tphy-handle = <&phy_port1>;\n+\t\t\t\t\t};\n+\n+\t\t\t\t\tport@2 {\n+\t\t\t\t\t\treg = <2>;\n+\t\t\t\t\t\tlabel = \"lan4\";\n+\t\t\t\t\t\tphy-handle = <&phy_port2>;\n+\t\t\t\t\t};\n+\n+\t\t\t\t\tport@3 {\n+\t\t\t\t\t\treg = <3>;\n+\t\t\t\t\t\tlabel = \"lan5\";\n+\t\t\t\t\t\tphy-handle = <&phy_port3>;\n+\t\t\t\t\t};\n+\n+\t\t\t\t\tport@4 {\n+\t\t\t\t\t\treg = <4>;\n+\t\t\t\t\t\tlabel = \"lan6\";\n+\t\t\t\t\t\tphy-handle = <&phy_port4>;\n+\t\t\t\t\t};\n+\n+\t\t\t\t\tport@5 {\n+\t\t\t\t\t\treg = <5>;\n+\t\t\t\t\t\tlabel = \"lan7\";\n+\t\t\t\t\t\tphy-handle = <&phy_port5>;\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\t\t\t};\n+\t\t};\n+\t};\n+};\n+\n+&srab {\n+\tcompatible = \"brcm,bcm58625-srab\", \"brcm,nsp-srab\";\n+\tstatus = \"okay\";\n+\tdsa,member = <0 0>;\n+\n+\tports {\n+\t\tport@0 {\n+\t\t\tlabel = \"wan1\";\n+\t\t\treg = <0>;\n+\t\t};\n+\n+\t\tport@1 {\n+\t\t\tlabel = \"wan2\";\n+\t\t\treg = <1>;\n+\t\t};\n+\n+\t\tsgmii0: port@4 {\n+\t\t\tlabel = \"sw0\";\n+\t\t\treg = <4>;\n+\t\t\tfixed-link {\n+\t\t\t\tspeed = <1000>;\n+\t\t\t\tfull-duplex;\n+\t\t\t};\n+\t\t};\n+\n+\t\tsgmii1: port@5 {\n+\t\t\tlabel = \"sw1\";\n+\t\t\treg = <5>;\n+\t\t\tfixed-link {\n+\t\t\t\tspeed = <1000>;\n+\t\t\t\tfull-duplex;\n+\t\t\t};\n+\t\t};\n+\n+\t\tport@8 {\n+\t\t\tethernet = <&amac2>;\n+\t\t\treg = <8>;\n+\t\t\tfixed-link {\n+\t\t\t\tspeed = <1000>;\n+\t\t\t\tfull-duplex;\n+\t\t\t};\n+\t\t};\n+\t};\n+};\n--- /dev/null\n+++ b/arch/arm/boot/dts/bcm958625-meraki-mx65.dts\n@@ -0,0 +1,24 @@\n+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n+/*\n+ * Device Tree Bindings for Cisco Meraki MX65.\n+ *\n+ * Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com>\n+ */\n+\n+/dts-v1/;\n+\n+#include \"bcm958625-meraki-alamo.dtsi\"\n+\n+/ {\n+\tmodel = \"Cisco Meraki MX65\";\n+\tcompatible = \"meraki,mx65\", \"brcm,bcm58625\", \"brcm,nsp\";\n+\n+\tchosen {\n+\t\tstdout-path = \"serial0:115200n8\";\n+\t};\n+\n+\tmemory@60000000 {\n+\t\tdevice_type = \"memory\";\n+\t\treg = <0x60000000 0x80000000>;\n+\t};\n+};\n--- /dev/null\n+++ b/arch/arm/boot/dts/bcm958625-meraki-mx65w.dts\n@@ -0,0 +1,32 @@\n+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n+/*\n+ * Device Tree Bindings for Cisco Meraki MX65W.\n+ *\n+ * Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com>\n+ */\n+\n+/dts-v1/;\n+\n+#include \"bcm958625-meraki-alamo.dtsi\"\n+\n+/ {\n+\tmodel = \"Cisco Meraki MX65W\";\n+\tcompatible = \"meraki,mx65w\", \"brcm,bcm58625\", \"brcm,nsp\";\n+\n+\tchosen {\n+\t\tstdout-path = \"serial0:115200n8\";\n+\t};\n+\n+\tmemory@60000000 {\n+\t\tdevice_type = \"memory\";\n+\t\treg = <0x60000000 0x80000000>;\n+\t};\n+};\n+\n+&pcie0 {\n+\tstatus = \"okay\";\n+};\n+\n+&pcie1 {\n+\tstatus = \"okay\";\n+};\n"
  },
  {
    "path": "target/linux/bcm53xx/patches-5.15/030-v5.16-0013-ARM-dts-NSP-Add-bcm958623hr-board-name-to-dts.patch",
    "content": "From 695717eb4c61173d05a277e37132b5e2c6531bf1 Mon Sep 17 00:00:00 2001\nFrom: Matthew Hagan <mnhagan88@gmail.com>\nDate: Sun, 29 Aug 2021 22:37:47 +0000\nSubject: [PATCH] ARM: dts: NSP: Add bcm958623hr board name to dts\n\nThis board was previously added to\nDocumentation/devicetree/bindings/arm/bcm/brcm,nsp.yaml\nhowever the dts file was not updated to reflect this change. This patch\ncorrects bcm958623hr.dts by adding the board name to the compatible.\n\nSigned-off-by: Matthew Hagan <mnhagan88@gmail.com>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n arch/arm/boot/dts/bcm958623hr.dts | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/arch/arm/boot/dts/bcm958623hr.dts\n+++ b/arch/arm/boot/dts/bcm958623hr.dts\n@@ -37,7 +37,7 @@\n \n / {\n \tmodel = \"NorthStar Plus SVK (BCM958623HR)\";\n-\tcompatible = \"brcm,bcm58623\", \"brcm,nsp\";\n+\tcompatible = \"brcm,bcm958623hr\", \"brcm,bcm58623\", \"brcm,nsp\";\n \n \tchosen {\n \t\tstdout-path = \"serial0:115200n8\";\n"
  },
  {
    "path": "target/linux/bcm53xx/patches-5.15/030-v5.16-0015-ARM-dts-NSP-Fix-MDIO-mux-node-names.patch",
    "content": "From 38f8111369f318a538e9d4d89d8e48030c22fb40 Mon Sep 17 00:00:00 2001\nFrom: Matthew Hagan <mnhagan88@gmail.com>\nDate: Sun, 29 Aug 2021 22:37:49 +0000\nSubject: [PATCH] ARM: dts: NSP: Fix MDIO mux node names\n\nWhile functional, the mdio-mux-mmioreg binding does not conform to\nDocumentation/devicetree/bindings/net/mdio-mux-mmioreg.yaml in that an\nmdio-mux compatible is also required. Without this the following output\nis observed when running dtbs_check:\n\nmdio-mux@32000: compatible: ['mdio-mux-mmioreg'] is too short\n\nThis change brings conformance to this requirement and corresponds\nlikewise to Rafal Milecki's change to the BCM5301x platform[1].\n\n[1] https://lore.kernel.org/linux-arm-kernel/20210822191256.3715003-1-f.fainelli@gmail.com/T/\n\nSigned-off-by: Matthew Hagan <mnhagan88@gmail.com>\nReviewed-by: Andrew Lunn <andrew@lunn.ch>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n arch/arm/boot/dts/bcm-nsp.dtsi                | 2 +-\n arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi | 2 +-\n 2 files changed, 2 insertions(+), 2 deletions(-)\n\n--- a/arch/arm/boot/dts/bcm-nsp.dtsi\n+++ b/arch/arm/boot/dts/bcm-nsp.dtsi\n@@ -371,7 +371,7 @@\n \t\t};\n \n \t\tmdio-mux@32000 {\n-\t\t\tcompatible = \"mdio-mux-mmioreg\";\n+\t\t\tcompatible = \"mdio-mux-mmioreg\", \"mdio-mux\";\n \t\t\treg = <0x32000 0x4>;\n \t\t\tmux-mask = <0x200>;\n \t\t\t#address-cells = <1>;\n--- a/arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi\n+++ b/arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi\n@@ -72,7 +72,7 @@\n \t};\n \n \tmdio-mii-mux {\n-\t\tcompatible = \"mdio-mux-mmioreg\";\n+\t\tcompatible = \"mdio-mux-mmioreg\", \"mdio-mux\";\n \t\treg = <0x1803f1c0 0x4>;\n \t\tmux-mask = <0x2000>;\n \t\tmdio-parent-bus = <&mdio_ext>;\n"
  },
  {
    "path": "target/linux/bcm53xx/patches-5.15/030-v5.16-0016-ARM-dts-NSP-Fix-MX64-MX65-eeprom-node-name.patch",
    "content": "From 56e4e548427240d85fd220460d0ab5987e1dec00 Mon Sep 17 00:00:00 2001\nFrom: Matthew Hagan <mnhagan88@gmail.com>\nDate: Sun, 29 Aug 2021 22:37:50 +0000\nSubject: [PATCH] ARM: dts: NSP: Fix MX64/MX65 eeprom node name\n\nRunning dtbs_check yields the following message when checking the\nMX64/MX65 devicetree:\nat24@50: $nodename:0: 'at24@50' does not match '^eeprom@[0-9a-f]{1,2}$'\n\nThis patch fixes the issue by renaming the at24 node appropriately.\n\nSigned-off-by: Matthew Hagan <mnhagan88@gmail.com>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n arch/arm/boot/dts/bcm958625-meraki-mx6x-common.dtsi | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/arch/arm/boot/dts/bcm958625-meraki-mx6x-common.dtsi\n+++ b/arch/arm/boot/dts/bcm958625-meraki-mx6x-common.dtsi\n@@ -48,7 +48,7 @@\n &i2c0 {\n \tstatus = \"okay\";\n \n-\tat24@50 {\n+\teeprom@50 {\n \t\tcompatible = \"atmel,24c64\";\n \t\treg = <0x50>;\n \t\tpagesize = <32>;\n"
  },
  {
    "path": "target/linux/bcm53xx/patches-5.15/030-v5.16-0017-ARM-dts-NSP-Fix-MX65-MDIO-mux-warnings.patch",
    "content": "From f5fc9044e5d45a4d97b5240c8723f4677f647c9f Mon Sep 17 00:00:00 2001\nFrom: Matthew Hagan <mnhagan88@gmail.com>\nDate: Sun, 29 Aug 2021 22:37:51 +0000\nSubject: [PATCH] ARM: dts: NSP: Fix MX65 MDIO mux warnings\n\nThe naming of this node is based upon that of the initial EA9500 dts[1].\nHowever this does not conform with the mdio-mux format, yielding the\nfollowing message when running dtbs_check:\nmdio-mii-mux: $nodename:0: 'mdio-mii-mux' does not match '^mdio-mux[\\\\-@]?'\n\nSecondly, this node should be moved to within the axi node and given the\nappropriate unit address. This also requires exposing the axi node via a\nlabel in bcm-nsp.dtsi. This fixes the following warning:\nWarning (unit_address_vs_reg): /mdio-mii-mux: node has a reg or ranges property, but no unit name\n\n[1]https://patchwork.ozlabs.org/project/linux-imx/patch/20180618174159.86150-1-npcomplete13@gmail.com/#1941353\n\nSigned-off-by: Matthew Hagan <mnhagan88@gmail.com>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n arch/arm/boot/dts/bcm-nsp.dtsi                | 2 +-\n arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi | 6 ++++--\n 2 files changed, 5 insertions(+), 3 deletions(-)\n\n--- a/arch/arm/boot/dts/bcm-nsp.dtsi\n+++ b/arch/arm/boot/dts/bcm-nsp.dtsi\n@@ -166,7 +166,7 @@\n \t\t};\n \t};\n \n-\taxi@18000000 {\n+\taxi: axi@18000000 {\n \t\tcompatible = \"simple-bus\";\n \t\tranges = <0x00000000 0x18000000 0x0011c40c>;\n \t\t#address-cells = <1>;\n--- a/arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi\n+++ b/arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi\n@@ -70,10 +70,12 @@\n \t\t\tgpios = <&gpioa 31 GPIO_ACTIVE_HIGH>;\n \t\t};\n \t};\n+};\n \n-\tmdio-mii-mux {\n+&axi {\n+\tmdio-mux@3f1c0 {\n \t\tcompatible = \"mdio-mux-mmioreg\", \"mdio-mux\";\n-\t\treg = <0x1803f1c0 0x4>;\n+\t\treg = <0x3f1c0 0x4>;\n \t\tmux-mask = <0x2000>;\n \t\tmdio-parent-bus = <&mdio_ext>;\n \t\t#address-cells = <1>;\n"
  },
  {
    "path": "target/linux/bcm53xx/patches-5.15/030-v5.16-0018-ARM-dts-BCM5301X-Specify-switch-ports-for-more-devic.patch",
    "content": "From 225ffaf3d0e00daa2d0c7b68e8fd731ebbde3c03 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Tue, 7 Sep 2021 08:00:48 +0200\nSubject: [PATCH] ARM: dts: BCM5301X: Specify switch ports for more devices\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nThose are remaining models I have that didn't have ports yet. All\ntested.\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n arch/arm/boot/dts/bcm4708-netgear-r6250.dts   | 37 ++++++++++++++++\n .../boot/dts/bcm47081-buffalo-wzr-600dhp2.dts | 37 ++++++++++++++++\n arch/arm/boot/dts/bcm4709-netgear-r8000.dts   | 42 +++++++++++++++++++\n arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts | 42 +++++++++++++++++++\n arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts | 37 ++++++++++++++++\n arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts | 37 ++++++++++++++++\n 6 files changed, 232 insertions(+)\n\n--- a/arch/arm/boot/dts/bcm4708-netgear-r6250.dts\n+++ b/arch/arm/boot/dts/bcm4708-netgear-r6250.dts\n@@ -94,3 +94,40 @@\n &usb3_phy {\n \tstatus = \"okay\";\n };\n+\n+&srab {\n+\tstatus = \"okay\";\n+\n+\tports {\n+\t\tport@0 {\n+\t\t\treg = <0>;\n+\t\t\tlabel = \"lan4\";\n+\t\t};\n+\n+\t\tport@1 {\n+\t\t\treg = <1>;\n+\t\t\tlabel = \"lan3\";\n+\t\t};\n+\n+\t\tport@2 {\n+\t\t\treg = <2>;\n+\t\t\tlabel = \"lan2\";\n+\t\t};\n+\n+\t\tport@3 {\n+\t\t\treg = <3>;\n+\t\t\tlabel = \"lan1\";\n+\t\t};\n+\n+\t\tport@4 {\n+\t\t\treg = <4>;\n+\t\t\tlabel = \"wan\";\n+\t\t};\n+\n+\t\tport@5 {\n+\t\t\treg = <5>;\n+\t\t\tlabel = \"cpu\";\n+\t\t\tethernet = <&gmac0>;\n+\t\t};\n+\t};\n+};\n--- a/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts\n+++ b/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts\n@@ -117,3 +117,40 @@\n \t\t};\n \t};\n };\n+\n+&srab {\n+\tstatus = \"okay\";\n+\n+\tports {\n+\t\tport@0 {\n+\t\t\treg = <0>;\n+\t\t\tlabel = \"lan1\";\n+\t\t};\n+\n+\t\tport@1 {\n+\t\t\treg = <1>;\n+\t\t\tlabel = \"lan2\";\n+\t\t};\n+\n+\t\tport@2 {\n+\t\t\treg = <2>;\n+\t\t\tlabel = \"lan3\";\n+\t\t};\n+\n+\t\tport@3 {\n+\t\t\treg = <3>;\n+\t\t\tlabel = \"lan4\";\n+\t\t};\n+\n+\t\tport@4 {\n+\t\t\treg = <4>;\n+\t\t\tlabel = \"wan\";\n+\t\t};\n+\n+\t\tport@5 {\n+\t\t\treg = <5>;\n+\t\t\tlabel = \"cpu\";\n+\t\t\tethernet = <&gmac0>;\n+\t\t};\n+\t};\n+};\n--- a/arch/arm/boot/dts/bcm4709-netgear-r8000.dts\n+++ b/arch/arm/boot/dts/bcm4709-netgear-r8000.dts\n@@ -187,3 +187,45 @@\n &usb3_phy {\n \tstatus = \"okay\";\n };\n+\n+&srab {\n+\tstatus = \"okay\";\n+\n+\tports {\n+\t\tport@0 {\n+\t\t\treg = <0>;\n+\t\t\tlabel = \"lan1\";\n+\t\t};\n+\n+\t\tport@1 {\n+\t\t\treg = <1>;\n+\t\t\tlabel = \"lan2\";\n+\t\t};\n+\n+\t\tport@2 {\n+\t\t\treg = <2>;\n+\t\t\tlabel = \"lan3\";\n+\t\t};\n+\n+\t\tport@3 {\n+\t\t\treg = <3>;\n+\t\t\tlabel = \"lan4\";\n+\t\t};\n+\n+\t\tport@4 {\n+\t\t\treg = <4>;\n+\t\t\tlabel = \"wan\";\n+\t\t};\n+\n+\t\tport@8 {\n+\t\t\treg = <8>;\n+\t\t\tlabel = \"cpu\";\n+\t\t\tethernet = <&gmac2>;\n+\n+\t\t\tfixed-link {\n+\t\t\t\tspeed = <1000>;\n+\t\t\t\tfull-duplex;\n+\t\t\t};\n+\t\t};\n+\t};\n+};\n--- a/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts\n+++ b/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts\n@@ -118,3 +118,45 @@\n &usb3_phy {\n \tstatus = \"okay\";\n };\n+\n+&srab {\n+\tstatus = \"okay\";\n+\n+\tports {\n+\t\tport@0 {\n+\t\t\treg = <0>;\n+\t\t\tlabel = \"lan4\";\n+\t\t};\n+\n+\t\tport@1 {\n+\t\t\treg = <1>;\n+\t\t\tlabel = \"lan3\";\n+\t\t};\n+\n+\t\tport@2 {\n+\t\t\treg = <2>;\n+\t\t\tlabel = \"lan2\";\n+\t\t};\n+\n+\t\tport@3 {\n+\t\t\treg = <3>;\n+\t\t\tlabel = \"lan1\";\n+\t\t};\n+\n+\t\tport@4 {\n+\t\t\treg = <4>;\n+\t\t\tlabel = \"wan\";\n+\t\t};\n+\n+\t\tport@8 {\n+\t\t\treg = <8>;\n+\t\t\tlabel = \"cpu\";\n+\t\t\tethernet = <&gmac2>;\n+\n+\t\t\tfixed-link {\n+\t\t\t\tspeed = <1000>;\n+\t\t\t\tfull-duplex;\n+\t\t\t};\n+\t\t};\n+\t};\n+};\n--- a/arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts\n+++ b/arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts\n@@ -68,3 +68,40 @@\n &usb3_phy {\n \tstatus = \"okay\";\n };\n+\n+&srab {\n+\tstatus = \"okay\";\n+\n+\tports {\n+\t\tport@0 {\n+\t\t\treg = <0>;\n+\t\t\tlabel = \"wan\";\n+\t\t};\n+\n+\t\tport@1 {\n+\t\t\treg = <1>;\n+\t\t\tlabel = \"lan4\";\n+\t\t};\n+\n+\t\tport@2 {\n+\t\t\treg = <2>;\n+\t\t\tlabel = \"lan3\";\n+\t\t};\n+\n+\t\tport@3 {\n+\t\t\treg = <3>;\n+\t\t\tlabel = \"lan2\";\n+\t\t};\n+\n+\t\tport@4 {\n+\t\t\treg = <4>;\n+\t\t\tlabel = \"lan1\";\n+\t\t};\n+\n+\t\tport@5 {\n+\t\t\treg = <5>;\n+\t\t\tlabel = \"cpu\";\n+\t\t\tethernet = <&gmac0>;\n+\t\t};\n+\t};\n+};\n--- a/arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts\n+++ b/arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts\n@@ -68,3 +68,40 @@\n &usb3_phy {\n \tstatus = \"okay\";\n };\n+\n+&srab {\n+\tstatus = \"okay\";\n+\n+\tports {\n+\t\tport@0 {\n+\t\t\treg = <0>;\n+\t\t\tlabel = \"wan\";\n+\t\t};\n+\n+\t\tport@1 {\n+\t\t\treg = <1>;\n+\t\t\tlabel = \"lan4\";\n+\t\t};\n+\n+\t\tport@2 {\n+\t\t\treg = <2>;\n+\t\t\tlabel = \"lan3\";\n+\t\t};\n+\n+\t\tport@3 {\n+\t\t\treg = <3>;\n+\t\t\tlabel = \"lan2\";\n+\t\t};\n+\n+\t\tport@4 {\n+\t\t\treg = <4>;\n+\t\t\tlabel = \"lan1\";\n+\t\t};\n+\n+\t\tport@5 {\n+\t\t\treg = <5>;\n+\t\t\tlabel = \"cpu\";\n+\t\t\tethernet = <&gmac0>;\n+\t\t};\n+\t};\n+};\n"
  },
  {
    "path": "target/linux/bcm53xx/patches-5.15/030-v5.16-0019-ARM-dts-BCM53573-Describe-on-SoC-BCM53125-rev-4-swit.patch",
    "content": "From 9fb90ae6cae7f8fe4fbf626945f32cd9da2c3892 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Mon, 20 Sep 2021 16:10:23 +0200\nSubject: [PATCH] ARM: dts: BCM53573: Describe on-SoC BCM53125 rev 4 switch\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nBCM53573 family SoC have Ethernet switch connected to the first Ethernet\ncontroller (accessible over MDIO).\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n arch/arm/boot/dts/bcm53573.dtsi | 18 ++++++++++++++++++\n 1 file changed, 18 insertions(+)\n\n--- a/arch/arm/boot/dts/bcm53573.dtsi\n+++ b/arch/arm/boot/dts/bcm53573.dtsi\n@@ -180,6 +180,24 @@\n \n \t\tgmac0: ethernet@5000 {\n \t\t\treg = <0x5000 0x1000>;\n+\n+\t\t\tmdio {\n+\t\t\t\t#address-cells = <1>;\n+\t\t\t\t#size-cells = <0>;\n+\n+\t\t\t\tswitch: switch@1e {\n+\t\t\t\t\tcompatible = \"brcm,bcm53125\";\n+\t\t\t\t\treg = <0x1e>;\n+\n+\t\t\t\t\tstatus = \"disabled\";\n+\n+\t\t\t\t\t/* ports are defined in board DTS */\n+\t\t\t\t\tports {\n+\t\t\t\t\t\t#address-cells = <1>;\n+\t\t\t\t\t\t#size-cells = <0>;\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\t\t\t};\n \t\t};\n \n \t\tgmac1: ethernet@b000 {\n"
  },
  {
    "path": "target/linux/bcm53xx/patches-5.15/030-v5.16-0020-ARM-dts-BCM53573-Add-Tenda-AC9-switch-ports.patch",
    "content": "From 64612828628cca6e3992e421f45c242dc6625647 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Mon, 20 Sep 2021 16:10:24 +0200\nSubject: [PATCH] ARM: dts: BCM53573: Add Tenda AC9 switch ports\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nThis router has 1 WAN and 4 LAN ports.\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n arch/arm/boot/dts/bcm47189-tenda-ac9.dts | 37 ++++++++++++++++++++++++\n 1 file changed, 37 insertions(+)\n\n--- a/arch/arm/boot/dts/bcm47189-tenda-ac9.dts\n+++ b/arch/arm/boot/dts/bcm47189-tenda-ac9.dts\n@@ -105,3 +105,40 @@\n \t\t};\n \t};\n };\n+\n+&switch {\n+\tstatus = \"okay\";\n+\n+\tports {\n+\t\tport@0 {\n+\t\t\treg = <0>;\n+\t\t\tlabel = \"wan\";\n+\t\t};\n+\n+\t\tport@1 {\n+\t\t\treg = <1>;\n+\t\t\tlabel = \"lan1\";\n+\t\t};\n+\n+\t\tport@2 {\n+\t\t\treg = <2>;\n+\t\t\tlabel = \"lan2\";\n+\t\t};\n+\n+\t\tport@3 {\n+\t\t\treg = <3>;\n+\t\t\tlabel = \"lan3\";\n+\t\t};\n+\n+\t\tport@4 {\n+\t\t\treg = <4>;\n+\t\t\tlabel = \"lan4\";\n+\t\t};\n+\n+\t\tport@5 {\n+\t\t\treg = <5>;\n+\t\t\tlabel = \"cpu\";\n+\t\t\tethernet = <&gmac0>;\n+\t\t};\n+\t};\n+};\n"
  },
  {
    "path": "target/linux/bcm53xx/patches-5.15/030-v5.16-0021-ARM-BCM53016-Specify-switch-ports-for-Meraki-MR32.patch",
    "content": "From 6abc4ca5a28070945e0d68cb4160b309bfbf4b8b Mon Sep 17 00:00:00 2001\nFrom: Christian Lamparter <chunkeey@gmail.com>\nDate: Sat, 18 Sep 2021 19:29:30 +0200\nSubject: [PATCH] ARM: BCM53016: Specify switch ports for Meraki MR32\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nthe switch identifies itself as a BCM53012 (rev 5)...\nThis patch has been tested & verified on OpenWrt's\nsnapshot with Linux 5.10 (didn't test any older kernels).\nThe MR32 is able to \"talk to the network\" as before with\nOpenWrt's SWITCHDEV b53 driver.\n\n| b53-srab-switch 18007000.ethernet-switch: found switch: BCM53012, rev 5\n| libphy: dsa slave smi: probed\n| b53-srab-switch 18007000.ethernet-switch poe (uninitialized):\n|\tPHY [dsa-0.0:00] driver [Generic PHY] (irq=POLL)\n| b53-srab-switch 18007000.ethernet-switch: Using legacy PHYLIB callbacks.\n|\tPlease migrate to PHYLINK!\n| DSA: tree 0 setup\n\nReported-by: Rafał Miłecki <zajec5@gmail.com>\nSigned-off-by: Christian Lamparter <chunkeey@gmail.com>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n arch/arm/boot/dts/bcm53016-meraki-mr32.dts | 22 ++++++++++++++++++++++\n 1 file changed, 22 insertions(+)\n\n--- a/arch/arm/boot/dts/bcm53016-meraki-mr32.dts\n+++ b/arch/arm/boot/dts/bcm53016-meraki-mr32.dts\n@@ -217,3 +217,25 @@\n \t\t};\n \t};\n };\n+\n+&srab {\n+\tstatus = \"okay\";\n+\n+\tports {\n+\t\tport@0 {\n+\t\t\treg = <0>;\n+\t\t\tlabel = \"poe\";\n+\t\t};\n+\n+\t\tport@5 {\n+\t\t\treg = <5>;\n+\t\t\tlabel = \"cpu\";\n+\t\t\tethernet = <&gmac0>;\n+\n+\t\t\tfixed-link {\n+\t\t\t\tspeed = <1000>;\n+\t\t\t\tduplex-full;\n+\t\t\t};\n+\t\t};\n+\t};\n+};\n"
  },
  {
    "path": "target/linux/bcm53xx/patches-5.15/030-v5.16-0022-ARM-BCM53016-MR32-get-mac-address-from-nvmem.patch",
    "content": "From 477ffdbdf389cc91294d66e251cc6f856da5820c Mon Sep 17 00:00:00 2001\nFrom: Christian Lamparter <chunkeey@gmail.com>\nDate: Sat, 18 Sep 2021 19:29:31 +0200\nSubject: [PATCH] ARM: BCM53016: MR32: get mac-address from nvmem\n\nThe MAC-Address of the MR32's sole ethernet port is\nlocated in offset 0x66 of the attached AT24C64 eeprom.\n\nSigned-off-by: Christian Lamparter <chunkeey@gmail.com>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n arch/arm/boot/dts/bcm53016-meraki-mr32.dts | 11 +++++++++++\n 1 file changed, 11 insertions(+)\n\n--- a/arch/arm/boot/dts/bcm53016-meraki-mr32.dts\n+++ b/arch/arm/boot/dts/bcm53016-meraki-mr32.dts\n@@ -110,6 +110,12 @@\n \t\t\treg = <0x50>;\n \t\t\tpagesize = <32>;\n \t\t\tread-only;\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <1>;\n+\n+\t\t\tmac_address: mac-address@66 {\n+\t\t\t\treg = <0x66 0x6>;\n+\t\t\t};\n \t\t};\n \t};\n };\n@@ -133,6 +139,11 @@\n \t */\n };\n \n+&gmac0 {\n+\tnvmem-cell-names = \"mac-address\";\n+\tnvmem-cells = <&mac_address>;\n+};\n+\n &gmac1 {\n \tstatus = \"disabled\";\n };\n"
  },
  {
    "path": "target/linux/bcm53xx/patches-5.15/030-v5.16-0023-ARM-dts-BCM5301X-Add-DT-for-Asus-RT-AC88U.patch",
    "content": "From beff77b93452cd2057c859694709dd34a181488f Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>\nDate: Tue, 21 Sep 2021 20:19:01 +0800\nSubject: [PATCH] ARM: dts: BCM5301X: Add DT for Asus RT-AC88U\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nHardware Info\n-------------\n\nProcessor\t- Broadcom BCM4709C0KFEBG dual-core @ 1.4 GHz\nSwitch\t\t- BCM53012 in BCM4709C0KFEBG & external RTL8365MB\nDDR3 RAM\t- 512 MB\nFlash\t\t- 128 MB (ESMT F59L1G81LA-25T)\n2.4GHz\t\t- BCM4366 4×4 2.4/5G single chip 802.11ac SoC\n5GHz\t\t- BCM4366 4×4 2.4/5G single chip 802.11ac SoC\nPorts\t\t- 8 Ports, 1 WAN Ports\n\nTested on OpenWrt on kernel 5.10 built with DSA driver.\n\nSigned-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n arch/arm/boot/dts/Makefile                   |   1 +\n arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts | 200 +++++++++++++++++++\n 2 files changed, 201 insertions(+)\n create mode 100644 arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts\n\n--- a/arch/arm/boot/dts/Makefile\n+++ b/arch/arm/boot/dts/Makefile\n@@ -117,6 +117,7 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \\\n \tbcm4709-netgear-r7000.dtb \\\n \tbcm4709-netgear-r8000.dtb \\\n \tbcm4709-tplink-archer-c9-v1.dtb \\\n+\tbcm47094-asus-rt-ac88u.dtb \\\n \tbcm47094-dlink-dir-885l.dtb \\\n \tbcm47094-linksys-panamera.dtb \\\n \tbcm47094-luxul-abr-4500.dtb \\\n--- /dev/null\n+++ b/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts\n@@ -0,0 +1,200 @@\n+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n+/*\n+ * Copyright (C) 2021 Arınç ÜNAL <arinc.unal@arinc9.com>\n+ */\n+\n+/dts-v1/;\n+\n+#include \"bcm47094.dtsi\"\n+#include \"bcm5301x-nand-cs0-bch8.dtsi\"\n+\n+/ {\n+\tcompatible = \"asus,rt-ac88u\", \"brcm,bcm47094\", \"brcm,bcm4708\";\n+\tmodel = \"Asus RT-AC88U\";\n+\n+\tchosen {\n+\t\tbootargs = \"earlycon\";\n+\t};\n+\n+\tmemory@0 {\n+\t\tdevice_type = \"memory\";\n+\t\treg = <0x00000000 0x08000000>,\n+\t\t      <0x88000000 0x18000000>;\n+\t};\n+\n+\tnvram@1c080000 {\n+\t\tcompatible = \"brcm,nvram\";\n+\t\treg = <0x1c080000 0x00180000>;\n+\t};\n+\n+\tleds {\n+\t\tcompatible = \"gpio-leds\";\n+\n+\t\tpower {\n+\t\t\tlabel = \"white:power\";\n+\t\t\tgpios = <&chipcommon 3 GPIO_ACTIVE_LOW>;\n+\t\t\tlinux,default-trigger = \"default-on\";\n+\t\t};\n+\n+\t\twan-red {\n+\t\t\tlabel = \"red:wan\";\n+\t\t\tgpios = <&chipcommon 5 GPIO_ACTIVE_HIGH>;\n+\t\t};\n+\n+\t\tlan {\n+\t\t\tlabel = \"white:lan\";\n+\t\t\tgpios = <&chipcommon 21 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\n+\t\tusb2 {\n+\t\t\tlabel = \"white:usb2\";\n+\t\t\tgpios = <&chipcommon 16 GPIO_ACTIVE_LOW>;\n+\t\t\ttrigger-sources = <&ehci_port2>;\n+\t\t\tlinux,default-trigger = \"usbport\";\n+\t\t};\n+\n+\t\tusb3 {\n+\t\t\tlabel = \"white:usb3\";\n+\t\t\tgpios = <&chipcommon 17 GPIO_ACTIVE_LOW>;\n+\t\t\ttrigger-sources = <&ehci_port1>, <&xhci_port1>;\n+\t\t\tlinux,default-trigger = \"usbport\";\n+\t\t};\n+\n+\t\twps {\n+\t\t\tlabel = \"white:wps\";\n+\t\t\tgpios = <&chipcommon 19 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\t};\n+\n+\tgpio-keys {\n+\t\tcompatible = \"gpio-keys\";\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\n+\t\twps {\n+\t\t\tlabel = \"WPS\";\n+\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n+\t\t\tgpios = <&chipcommon 20 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\n+\t\treset {\n+\t\t\tlabel = \"Reset\";\n+\t\t\tlinux,code = <KEY_RESTART>;\n+\t\t\tgpios = <&chipcommon 11 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\n+\t\twifi {\n+\t\t\tlabel = \"Wi-Fi\";\n+\t\t\tlinux,code = <KEY_RFKILL>;\n+\t\t\tgpios = <&chipcommon 18 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\n+\t\tled {\n+\t\t\tlabel = \"Backlight\";\n+\t\t\tlinux,code = <KEY_BRIGHTNESS_ZERO>;\n+\t\t\tgpios = <&chipcommon 4 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\t};\n+};\n+\n+&srab {\n+\tcompatible = \"brcm,bcm53012-srab\", \"brcm,bcm5301x-srab\";\n+\tstatus = \"okay\";\n+\tdsa,member = <0 0>;\n+\n+\tports {\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\n+\t\tport@0 {\n+\t\t\treg = <0>;\n+\t\t\tlabel = \"lan4\";\n+\t\t};\n+\n+\t\tport@1 {\n+\t\t\treg = <1>;\n+\t\t\tlabel = \"lan3\";\n+\t\t};\n+\n+\t\tport@2 {\n+\t\t\treg = <2>;\n+\t\t\tlabel = \"lan2\";\n+\t\t};\n+\n+\t\tport@3 {\n+\t\t\treg = <3>;\n+\t\t\tlabel = \"lan1\";\n+\t\t};\n+\n+\t\tport@4 {\n+\t\t\treg = <4>;\n+\t\t\tlabel = \"wan\";\n+\t\t};\n+\n+\t\tsw0_p5: port@5 {\n+\t\t\treg = <5>;\n+\t\t\tlabel = \"extsw\";\n+\n+\t\t\tfixed-link {\n+\t\t\t\tspeed = <1000>;\n+\t\t\t\tfull-duplex;\n+\t\t\t};\n+\t\t};\n+\n+\t\tport@7 {\n+\t\t\treg = <7>;\n+\t\t\tethernet = <&gmac1>;\n+\t\t\tlabel = \"cpu\";\n+\n+\t\t\tfixed-link {\n+\t\t\t\tspeed = <1000>;\n+\t\t\t\tfull-duplex;\n+\t\t\t};\n+\t\t};\n+\n+\t\tport@8 {\n+\t\t\treg = <8>;\n+\t\t\tethernet = <&gmac2>;\n+\t\t\tlabel = \"cpu\";\n+\t\t\tstatus = \"disabled\";\n+\n+\t\t\tfixed-link {\n+\t\t\t\tspeed = <1000>;\n+\t\t\t\tfull-duplex;\n+\t\t\t};\n+\t\t};\n+\t};\n+};\n+\n+&usb2 {\n+\tvcc-gpio = <&chipcommon 9 GPIO_ACTIVE_HIGH>;\n+};\n+\n+&usb3_phy {\n+\tstatus = \"okay\";\n+};\n+\n+&nandcs {\n+\tpartitions {\n+\t\tcompatible = \"fixed-partitions\";\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <1>;\n+\n+\t\tpartition@0 {\n+\t\t\tlabel = \"boot\";\n+\t\t\treg = <0x00000000 0x00080000>;\n+\t\t\tread-only;\n+\t\t};\n+\n+\t\tpartition@80000 {\n+\t\t\tlabel = \"nvram\";\n+\t\t\treg = <0x00080000 0x00180000>;\n+\t\t};\n+\n+\t\tpartition@200000 {\n+\t\t\tlabel = \"firmware\";\n+\t\t\treg = <0x00200000 0x07e00000>;\n+\t\t\tcompatible = \"brcm,trx\";\n+\t\t};\n+\t};\n+};\n"
  },
  {
    "path": "target/linux/bcm53xx/patches-5.15/031-v5.17-0001-ARM-dts-NSP-MX65-add-qca8k-falling-edge-PLL-properti.patch",
    "content": "From 58d3d07985c1adab31a3ed76360d016bb1c5b358 Mon Sep 17 00:00:00 2001\nFrom: Matthew Hagan <mnhagan88@gmail.com>\nDate: Fri, 15 Oct 2021 23:50:22 +0100\nSubject: [PATCH] ARM: dts: NSP: MX65: add qca8k falling-edge, PLL properties\n\nThis patch enables two properties for the QCA8337 switches on the MX65.\n\nSet the SGMII transmit clock to falling edge\n\"qca,sgmii-txclk-falling-edge\" to conform to the OEM configuration [1].\n\nThe new explicit PLL enable option \"qca,sgmii-enable-pll\" is required\n[2].\n\n[1] https://git.kernel.org/netdev/net-next/c/6c43809bf1be\n[2] https://git.kernel.org/netdev/net-next/c/bbc4799e8bb6\n\nSigned-off-by: Matthew Hagan <mnhagan88@gmail.com>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi | 4 ++++\n 1 file changed, 4 insertions(+)\n\n--- a/arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi\n+++ b/arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi\n@@ -118,6 +118,8 @@\n \t\t\t\t\t\treg = <0>;\n \t\t\t\t\t\tethernet = <&sgmii1>;\n \t\t\t\t\t\tphy-mode = \"sgmii\";\n+\t\t\t\t\t\tqca,sgmii-enable-pll;\n+\t\t\t\t\t\tqca,sgmii-txclk-falling-edge;\n \t\t\t\t\t\tfixed-link {\n \t\t\t\t\t\t\tspeed = <1000>;\n \t\t\t\t\t\t\tfull-duplex;\n@@ -194,6 +196,8 @@\n \t\t\t\t\t\treg = <0>;\n \t\t\t\t\t\tethernet = <&sgmii0>;\n \t\t\t\t\t\tphy-mode = \"sgmii\";\n+\t\t\t\t\t\tqca,sgmii-enable-pll;\n+\t\t\t\t\t\tqca,sgmii-txclk-falling-edge;\n \t\t\t\t\t\tfixed-link {\n \t\t\t\t\t\t\tspeed = <1000>;\n \t\t\t\t\t\t\tfull-duplex;\n"
  },
  {
    "path": "target/linux/bcm53xx/patches-5.15/031-v5.17-0002-ARM-dts-BCM5301X-remove-unnecessary-address-size-cel.patch",
    "content": "From 835992e7eca4b29a87c204cefff2f7863fd087f3 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>\nDate: Wed, 27 Oct 2021 00:57:03 +0800\nSubject: [PATCH] ARM: dts: BCM5301X: remove unnecessary address & size cells\n from Asus RT-AC88U\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nRemove the unnecessary #address-cells & #size-cells in the gpio-keys node\nfrom the device tree of Asus RT-AC88U.\n\nSigned-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts | 2 --\n 1 file changed, 2 deletions(-)\n\n--- a/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts\n+++ b/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts\n@@ -68,8 +68,6 @@\n \n \tgpio-keys {\n \t\tcompatible = \"gpio-keys\";\n-\t\t#address-cells = <1>;\n-\t\t#size-cells = <0>;\n \n \t\twps {\n \t\t\tlabel = \"WPS\";\n"
  },
  {
    "path": "target/linux/bcm53xx/patches-5.15/031-v5.17-0003-ARM-dts-BCM5301X-define-RTL8365MB-switch-on-Asus-RT-.patch",
    "content": "From b6c99228c8edc5e67d8229ba1c5f76cce210ddfc Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>\nDate: Wed, 27 Oct 2021 00:57:06 +0800\nSubject: [PATCH] ARM: dts: BCM5301X: define RTL8365MB switch on Asus RT-AC88U\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nDefine the Realtek RTL8365MB switch without interrupt support on the device\ntree of Asus RT-AC88U.\n\nSigned-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>\nAcked-by: Alvin Šipraga <alsi@bang-olufsen.dk>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts | 77 ++++++++++++++++++++\n 1 file changed, 77 insertions(+)\n\n--- a/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts\n+++ b/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts\n@@ -93,6 +93,83 @@\n \t\t\tgpios = <&chipcommon 4 GPIO_ACTIVE_LOW>;\n \t\t};\n \t};\n+\n+\tswitch {\n+\t\tcompatible = \"realtek,rtl8365mb\";\n+\t\t/* 7 = MDIO (has input reads), 6 = MDC (clock, output only) */\n+\t\tmdc-gpios = <&chipcommon 6 GPIO_ACTIVE_HIGH>;\n+\t\tmdio-gpios = <&chipcommon 7 GPIO_ACTIVE_HIGH>;\n+\t\treset-gpios = <&chipcommon 10 GPIO_ACTIVE_LOW>;\n+\t\trealtek,disable-leds;\n+\t\tdsa,member = <1 0>;\n+\n+\t\tports {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\treg = <0>;\n+\n+\t\t\tport@0 {\n+\t\t\t\treg = <0>;\n+\t\t\t\tlabel = \"lan5\";\n+\t\t\t\tphy-handle = <&ethphy0>;\n+\t\t\t};\n+\n+\t\t\tport@1 {\n+\t\t\t\treg = <1>;\n+\t\t\t\tlabel = \"lan6\";\n+\t\t\t\tphy-handle = <&ethphy1>;\n+\t\t\t};\n+\n+\t\t\tport@2 {\n+\t\t\t\treg = <2>;\n+\t\t\t\tlabel = \"lan7\";\n+\t\t\t\tphy-handle = <&ethphy2>;\n+\t\t\t};\n+\n+\t\t\tport@3 {\n+\t\t\t\treg = <3>;\n+\t\t\t\tlabel = \"lan8\";\n+\t\t\t\tphy-handle = <&ethphy3>;\n+\t\t\t};\n+\n+\t\t\tport@6 {\n+\t\t\t\treg = <6>;\n+\t\t\t\tlabel = \"cpu\";\n+\t\t\t\tethernet = <&sw0_p5>;\n+\t\t\t\tphy-mode = \"rgmii\";\n+\t\t\t\ttx-internal-delay-ps = <2000>;\n+\t\t\t\trx-internal-delay-ps = <2000>;\n+\n+\t\t\t\tfixed-link {\n+\t\t\t\t\tspeed = <1000>;\n+\t\t\t\t\tfull-duplex;\n+\t\t\t\t\tpause;\n+\t\t\t\t};\n+\t\t\t};\n+\t\t};\n+\n+\t\tmdio {\n+\t\t\tcompatible = \"realtek,smi-mdio\";\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tethphy0: ethernet-phy@0 {\n+\t\t\t\treg = <0>;\n+\t\t\t};\n+\n+\t\t\tethphy1: ethernet-phy@1 {\n+\t\t\t\treg = <1>;\n+\t\t\t};\n+\n+\t\t\tethphy2: ethernet-phy@2 {\n+\t\t\t\treg = <2>;\n+\t\t\t};\n+\n+\t\t\tethphy3: ethernet-phy@3 {\n+\t\t\t\treg = <3>;\n+\t\t\t};\n+\t\t};\n+\t};\n };\n \n &srab {\n"
  },
  {
    "path": "target/linux/bcm53xx/patches-5.15/031-v5.17-0004-ARM-BCM53016-MR32-convert-to-Broadcom-iProc-I2C-Driv.patch",
    "content": "From de7880016665afe7fa7d40e1fafa859260d53ba1 Mon Sep 17 00:00:00 2001\nFrom: Christian Lamparter <chunkeey@gmail.com>\nDate: Thu, 28 Oct 2021 09:03:44 +0200\nSubject: [PATCH] ARM: BCM53016: MR32: convert to Broadcom iProc I2C Driver\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nreplaces the bit-banged i2c-gpio provided i2c functionality\nwith the hardware in the SoC.\n\nDuring review of the MR32, Florian Fainelli pointed out that the\nSoC has a real I2C-controller. Furthermore, the connected pins\n(SDA and SCL) would line up perfectly for use. Back then I couldn't\nget it working though and I left it with i2c-gpio (which worked).\n\nNow we know the reason: the interrupt was incorrectly specified.\n(Hence, this patch depends on Florian Fainelli's\n\"ARM: dts: BCM5301X: Fix I2C controller interrupt\" patch).\n\nCc: Florian Fainelli <f.fainelli@gmail.com>\nCc: Rafał Miłecki <zajec5@gmail.com>\nCc: Matthew Hagan <mnhagan88@gmail.com>\nSigned-off-by: Christian Lamparter <chunkeey@gmail.com>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n arch/arm/boot/dts/bcm53016-meraki-mr32.dts | 62 ++++++++++------------\n 1 file changed, 28 insertions(+), 34 deletions(-)\n\n--- a/arch/arm/boot/dts/bcm53016-meraki-mr32.dts\n+++ b/arch/arm/boot/dts/bcm53016-meraki-mr32.dts\n@@ -84,40 +84,6 @@\n \t\t\tmax-brightness = <255>;\n \t\t};\n \t};\n-\n-\ti2c {\n-\t\t/*\n-\t\t * The platform provided I2C does not budge.\n-\t\t * This is a replacement until I can figure\n-\t\t * out what are the missing bits...\n-\t\t */\n-\n-\t\tcompatible = \"i2c-gpio\";\n-\t\tsda-gpios = <&chipcommon 5 GPIO_ACTIVE_HIGH>;\n-\t\tscl-gpios = <&chipcommon 4 GPIO_ACTIVE_HIGH>;\n-\t\ti2c-gpio,delay-us = <10>; /* close to 100 kHz */\n-\t\t#address-cells = <1>;\n-\t\t#size-cells = <0>;\n-\n-\t\tcurrent_sense: ina219@45 {\n-\t\t\tcompatible = \"ti,ina219\";\n-\t\t\treg = <0x45>;\n-\t\t\tshunt-resistor = <60000>; /* = 60 mOhms */\n-\t\t};\n-\n-\t\teeprom: eeprom@50 {\n-\t\t\tcompatible = \"atmel,24c64\";\n-\t\t\treg = <0x50>;\n-\t\t\tpagesize = <32>;\n-\t\t\tread-only;\n-\t\t\t#address-cells = <1>;\n-\t\t\t#size-cells = <1>;\n-\n-\t\t\tmac_address: mac-address@66 {\n-\t\t\t\treg = <0x66 0x6>;\n-\t\t\t};\n-\t\t};\n-\t};\n };\n \n &uart0 {\n@@ -250,3 +216,31 @@\n \t\t};\n \t};\n };\n+\n+&i2c0 {\n+\tstatus = \"okay\";\n+\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pinmux_i2c>;\n+\n+\tclock-frequency = <100000>;\n+\n+\tcurrent_sense: ina219@45 {\n+\t\tcompatible = \"ti,ina219\";\n+\t\treg = <0x45>;\n+\t\tshunt-resistor = <60000>; /* = 60 mOhms */\n+\t};\n+\n+\teeprom: eeprom@50 {\n+\t\tcompatible = \"atmel,24c64\";\n+\t\treg = <0x50>;\n+\t\tpagesize = <32>;\n+\t\tread-only;\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <1>;\n+\n+\t\tmac_address: mac-address@66 {\n+\t\t\treg = <0x66 0x6>;\n+\t\t};\n+\t};\n+};\n"
  },
  {
    "path": "target/linux/bcm53xx/patches-5.15/031-v5.17-0005-ARM-dts-BCM5301X-update-CRU-block-description.patch",
    "content": "From 31fd9b79dc580301c53a001482755ba7e88c2809 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Fri, 29 Oct 2021 18:05:23 +0200\nSubject: [PATCH] ARM: dts: BCM5301X: update CRU block description\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nThis describes CRU in a way matching documentation and fixes:\n\narch/arm/boot/dts/bcm4708-asus-rt-ac56u.dt.yaml: cru@100: $nodename:0: 'cru@100' does not match '^([a-z][a-z0-9\\\\-]+-bus|bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$'\n        From schema: /lib/python3.6/site-packages/dtschema/schemas/simple-bus.yaml\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n arch/arm/boot/dts/bcm5301x.dtsi | 13 +++++++++----\n 1 file changed, 9 insertions(+), 4 deletions(-)\n\n--- a/arch/arm/boot/dts/bcm5301x.dtsi\n+++ b/arch/arm/boot/dts/bcm5301x.dtsi\n@@ -423,14 +423,14 @@\n \t\t#address-cells = <1>;\n \t\t#size-cells = <1>;\n \n-\t\tcru@100 {\n-\t\t\tcompatible = \"simple-bus\";\n+\t\tcru-bus@100 {\n+\t\t\tcompatible = \"brcm,ns-cru\", \"simple-mfd\";\n \t\t\treg = <0x100 0x1a4>;\n \t\t\tranges;\n \t\t\t#address-cells = <1>;\n \t\t\t#size-cells = <1>;\n \n-\t\t\tlcpll0: lcpll0@100 {\n+\t\t\tlcpll0: clock-controller@100 {\n \t\t\t\t#clock-cells = <1>;\n \t\t\t\tcompatible = \"brcm,nsp-lcpll0\";\n \t\t\t\treg = <0x100 0x14>;\n@@ -439,7 +439,7 @@\n \t\t\t\t\t\t     \"sdio\", \"ddr_phy\";\n \t\t\t};\n \n-\t\t\tgenpll: genpll@140 {\n+\t\t\tgenpll: clock-controller@140 {\n \t\t\t\t#clock-cells = <1>;\n \t\t\t\tcompatible = \"brcm,nsp-genpll\";\n \t\t\t\treg = <0x140 0x24>;\n@@ -450,6 +450,11 @@\n \t\t\t\t\t\t     \"sata1\", \"sata2\";\n \t\t\t};\n \n+\t\t\tsyscon@180 {\n+\t\t\t\tcompatible = \"brcm,cru-clkset\", \"syscon\";\n+\t\t\t\treg = <0x180 0x4>;\n+\t\t\t};\n+\n \t\t\tpinctrl: pin-controller@1c0 {\n \t\t\t\tcompatible = \"brcm,bcm4708-pinmux\";\n \t\t\t\treg = <0x1c0 0x24>;\n"
  },
  {
    "path": "target/linux/bcm53xx/patches-5.15/031-v5.17-0006-ARM-dts-BCM5301X-use-non-deprecated-USB-2.0-PHY-bind.patch",
    "content": "From 1a46061a2a4130a08841941ce6dcaa32be2ce312 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Tue, 23 Nov 2021 10:03:33 +0100\nSubject: [PATCH] ARM: dts: BCM5301X: use non-deprecated USB 2.0 PHY binding\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nThe new binding covers a single reg and uses syscon to reference shared\nregister.\n\nReferences: 55b9b741712d (\"dt-bindings: phy: brcm,ns-usb2-phy: bind just a PHY block\")\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n arch/arm/boot/dts/bcm5301x.dtsi | 20 ++++++++++----------\n 1 file changed, 10 insertions(+), 10 deletions(-)\n\n--- a/arch/arm/boot/dts/bcm5301x.dtsi\n+++ b/arch/arm/boot/dts/bcm5301x.dtsi\n@@ -148,15 +148,6 @@\n \t\t};\n \t};\n \n-\tusb2_phy: usb2-phy@1800c000 {\n-\t\tcompatible = \"brcm,ns-usb2-phy\";\n-\t\treg = <0x1800c000 0x1000>;\n-\t\treg-names = \"dmu\";\n-\t\t#phy-cells = <0>;\n-\t\tclocks = <&genpll BCM_NSP_GENPLL_USB_PHY_REF_CLK>;\n-\t\tclock-names = \"phy-ref-clk\";\n-\t};\n-\n \taxi@18000000 {\n \t\tcompatible = \"brcm,bus-axi\";\n \t\treg = <0x18000000 0x1000>;\n@@ -450,7 +441,16 @@\n \t\t\t\t\t\t     \"sata1\", \"sata2\";\n \t\t\t};\n \n-\t\t\tsyscon@180 {\n+\t\t\tusb2_phy: phy@164 {\n+\t\t\t\tcompatible = \"brcm,ns-usb2-phy\";\n+\t\t\t\treg = <0x164 0x4>;\n+\t\t\t\tbrcm,syscon-clkset = <&cru_clkset>;\n+\t\t\t\tclocks = <&genpll BCM_NSP_GENPLL_USB_PHY_REF_CLK>;\n+\t\t\t\tclock-names = \"phy-ref-clk\";\n+\t\t\t\t#phy-cells = <0>;\n+\t\t\t};\n+\n+\t\t\tcru_clkset: syscon@180 {\n \t\t\t\tcompatible = \"brcm,cru-clkset\", \"syscon\";\n \t\t\t\treg = <0x180 0x4>;\n \t\t\t};\n"
  },
  {
    "path": "target/linux/bcm53xx/patches-5.15/031-v5.17-0007-ARM-dts-NSP-Fixed-iProc-PCIe-MSI-sub-node.patch",
    "content": "From 69c4e53bdd055ecc27761f6971a50c631ff9072e Mon Sep 17 00:00:00 2001\nFrom: Florian Fainelli <f.fainelli@gmail.com>\nDate: Thu, 2 Dec 2021 15:16:27 -0800\nSubject: [PATCH] ARM: dts: NSP: Fixed iProc PCIe MSI sub-node\n\nRename the msi controller unit name to 'msi' to avoid collisions with\nthe 'msi-controller' boolean property.\n\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n arch/arm/boot/dts/bcm-nsp.dtsi | 6 +++---\n 1 file changed, 3 insertions(+), 3 deletions(-)\n\n--- a/arch/arm/boot/dts/bcm-nsp.dtsi\n+++ b/arch/arm/boot/dts/bcm-nsp.dtsi\n@@ -587,7 +587,7 @@\n \t\tstatus = \"disabled\";\n \n \t\tmsi-parent = <&msi0>;\n-\t\tmsi0: msi-controller {\n+\t\tmsi0: msi {\n \t\t\tcompatible = \"brcm,iproc-msi\";\n \t\t\tmsi-controller;\n \t\t\tinterrupt-parent = <&gic>;\n@@ -624,7 +624,7 @@\n \t\tstatus = \"disabled\";\n \n \t\tmsi-parent = <&msi1>;\n-\t\tmsi1: msi-controller {\n+\t\tmsi1: msi {\n \t\t\tcompatible = \"brcm,iproc-msi\";\n \t\t\tmsi-controller;\n \t\t\tinterrupt-parent = <&gic>;\n@@ -661,7 +661,7 @@\n \t\tstatus = \"disabled\";\n \n \t\tmsi-parent = <&msi2>;\n-\t\tmsi2: msi-controller {\n+\t\tmsi2: msi {\n \t\t\tcompatible = \"brcm,iproc-msi\";\n \t\t\tmsi-controller;\n \t\t\tinterrupt-parent = <&gic>;\n"
  },
  {
    "path": "target/linux/bcm53xx/patches-5.15/031-v5.17-0008-ARM-dts-NSP-Rename-SATA-unit-name.patch",
    "content": "From 9a68c53f875e88edd3403c001ad85f4ac0ed3486 Mon Sep 17 00:00:00 2001\nFrom: Florian Fainelli <f.fainelli@gmail.com>\nDate: Tue, 7 Dec 2021 10:19:09 -0800\nSubject: [PATCH] ARM: dts: NSP: Rename SATA unit name\n\nRename the SATA controller unit name from ahci to sata in preparation\nfor adding the Broadcom SATA3 controller YAML binding which will bring\nvalidation.\n\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n arch/arm/boot/dts/bcm-nsp.dtsi | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/arch/arm/boot/dts/bcm-nsp.dtsi\n+++ b/arch/arm/boot/dts/bcm-nsp.dtsi\n@@ -534,7 +534,7 @@\n \t\t\t};\n \t\t};\n \n-\t\tsata: ahci@41000 {\n+\t\tsata: sata@41000 {\n \t\t\tcompatible = \"brcm,bcm-nsp-ahci\";\n \t\t\treg-names = \"ahci\", \"top-ctrl\";\n \t\t\treg = <0x41000 0x1000>, <0x40020 0x1c>;\n"
  },
  {
    "path": "target/linux/bcm53xx/patches-5.15/031-v5.17-0009-ARM-dts-BCM5301X-correct-RX-delay-and-enable-flow-co.patch",
    "content": "From 5e33f1c4a7cb914a003a304ab8eef705b17aabb7 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>\nDate: Fri, 17 Dec 2021 00:03:19 +0800\nSubject: [PATCH] ARM: dts: BCM5301X: correct RX delay and enable flow control\n on Asus RT-AC88U\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nThe current 'rx-internal-delay-ps' property value on the Realtek switch\nnode, 2000, will be divided by 300, resulting in 6.66, which will be\nrounded to the closest step value, 7. Change it to 2100 to be accurate.\nSee ef136837aaf6 (\"net: dsa: rtl8365mb: set RGMII RX delay in steps of\n0.3 ns\") for reference.\n\nFlow control needs to be enabled on both sides of the internal and\nexternal switch. It is already enabled on the CPU port of the Realtek\nswitch so we also enable it on the external switch port of the Broadcom\nswitch as well.\n\nSigned-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts | 3 ++-\n 1 file changed, 2 insertions(+), 1 deletion(-)\n\n--- a/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts\n+++ b/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts\n@@ -138,7 +138,7 @@\n \t\t\t\tethernet = <&sw0_p5>;\n \t\t\t\tphy-mode = \"rgmii\";\n \t\t\t\ttx-internal-delay-ps = <2000>;\n-\t\t\t\trx-internal-delay-ps = <2000>;\n+\t\t\t\trx-internal-delay-ps = <2100>;\n \n \t\t\t\tfixed-link {\n \t\t\t\t\tspeed = <1000>;\n@@ -213,6 +213,7 @@\n \t\t\tfixed-link {\n \t\t\t\tspeed = <1000>;\n \t\t\t\tfull-duplex;\n+\t\t\t\tpause;\n \t\t\t};\n \t\t};\n \n"
  },
  {
    "path": "target/linux/bcm53xx/patches-5.15/031-v5.17-0010-Revert-ARM-dts-BCM5301X-define-RTL8365MB-switch-on-A.patch",
    "content": "From 8b0c59c622dc4dab970ec63264fb5b152944ac80 Mon Sep 17 00:00:00 2001\nFrom: Arnd Bergmann <arnd@arndb.de>\nDate: Thu, 23 Dec 2021 00:17:17 +0100\nSubject: [PATCH] Revert \"ARM: dts: BCM5301X: define RTL8365MB switch on Asus\n RT-AC88U\"\n\nThis reverts commit 3d2d52a0d1835b56f6bd67d268f6c39df0e41692, it caused\na build regression:\n\narch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts:109.4-14: Warning (reg_format): /switch/ports:reg: property has invalid length (4 bytes) (#address-cells == 2, #size-cells == 1)\narch/arm/boot/dts/bcm47094-asus-rt-ac88u.dtb: Warning (pci_device_reg): Failed prerequisite 'reg_format'\narch/arm/boot/dts/bcm47094-asus-rt-ac88u.dtb: Warning (pci_device_bus_num): Failed prerequisite 'reg_format'\narch/arm/boot/dts/bcm47094-asus-rt-ac88u.dtb: Warning (i2c_bus_reg): Failed prerequisite 'reg_format'\narch/arm/boot/dts/bcm47094-asus-rt-ac88u.dtb: Warning (spi_bus_reg): Failed prerequisite 'reg_format'\narch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts:106.9-149.5: Warning (avoid_default_addr_size): /switch/ports: Relying on default #address-cells value\narch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts:106.9-149.5: Warning (avoid_default_addr_size): /switch/ports: Relying on default #size-cells value\n\nReported-by: Stephen Rothwell <sfr@canb.auug.org.au>\nSigned-off-by: Arnd Bergmann <arnd@arndb.de>\n---\n arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts | 77 --------------------\n 1 file changed, 77 deletions(-)\n\n--- a/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts\n+++ b/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts\n@@ -93,83 +93,6 @@\n \t\t\tgpios = <&chipcommon 4 GPIO_ACTIVE_LOW>;\n \t\t};\n \t};\n-\n-\tswitch {\n-\t\tcompatible = \"realtek,rtl8365mb\";\n-\t\t/* 7 = MDIO (has input reads), 6 = MDC (clock, output only) */\n-\t\tmdc-gpios = <&chipcommon 6 GPIO_ACTIVE_HIGH>;\n-\t\tmdio-gpios = <&chipcommon 7 GPIO_ACTIVE_HIGH>;\n-\t\treset-gpios = <&chipcommon 10 GPIO_ACTIVE_LOW>;\n-\t\trealtek,disable-leds;\n-\t\tdsa,member = <1 0>;\n-\n-\t\tports {\n-\t\t\t#address-cells = <1>;\n-\t\t\t#size-cells = <0>;\n-\t\t\treg = <0>;\n-\n-\t\t\tport@0 {\n-\t\t\t\treg = <0>;\n-\t\t\t\tlabel = \"lan5\";\n-\t\t\t\tphy-handle = <&ethphy0>;\n-\t\t\t};\n-\n-\t\t\tport@1 {\n-\t\t\t\treg = <1>;\n-\t\t\t\tlabel = \"lan6\";\n-\t\t\t\tphy-handle = <&ethphy1>;\n-\t\t\t};\n-\n-\t\t\tport@2 {\n-\t\t\t\treg = <2>;\n-\t\t\t\tlabel = \"lan7\";\n-\t\t\t\tphy-handle = <&ethphy2>;\n-\t\t\t};\n-\n-\t\t\tport@3 {\n-\t\t\t\treg = <3>;\n-\t\t\t\tlabel = \"lan8\";\n-\t\t\t\tphy-handle = <&ethphy3>;\n-\t\t\t};\n-\n-\t\t\tport@6 {\n-\t\t\t\treg = <6>;\n-\t\t\t\tlabel = \"cpu\";\n-\t\t\t\tethernet = <&sw0_p5>;\n-\t\t\t\tphy-mode = \"rgmii\";\n-\t\t\t\ttx-internal-delay-ps = <2000>;\n-\t\t\t\trx-internal-delay-ps = <2100>;\n-\n-\t\t\t\tfixed-link {\n-\t\t\t\t\tspeed = <1000>;\n-\t\t\t\t\tfull-duplex;\n-\t\t\t\t\tpause;\n-\t\t\t\t};\n-\t\t\t};\n-\t\t};\n-\n-\t\tmdio {\n-\t\t\tcompatible = \"realtek,smi-mdio\";\n-\t\t\t#address-cells = <1>;\n-\t\t\t#size-cells = <0>;\n-\n-\t\t\tethphy0: ethernet-phy@0 {\n-\t\t\t\treg = <0>;\n-\t\t\t};\n-\n-\t\t\tethphy1: ethernet-phy@1 {\n-\t\t\t\treg = <1>;\n-\t\t\t};\n-\n-\t\t\tethphy2: ethernet-phy@2 {\n-\t\t\t\treg = <2>;\n-\t\t\t};\n-\n-\t\t\tethphy3: ethernet-phy@3 {\n-\t\t\t\treg = <3>;\n-\t\t\t};\n-\t\t};\n-\t};\n };\n \n &srab {\n"
  },
  {
    "path": "target/linux/bcm53xx/patches-5.15/032-v5.18-0001-ARM-dts-BCM5301X-define-RTL8365MB-switch-on-Asus-RT-.patch",
    "content": "From 441d531ec9b766f49e01c107a3043235daa4493f Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>\nDate: Sun, 2 Jan 2022 23:33:04 +0300\nSubject: [PATCH] ARM: dts: BCM5301X: define RTL8365MB switch on Asus RT-AC88U\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nDefine the Realtek RTL8365MB switch without interrupt support on the device\ntree of Asus RT-AC88U.\n\nSigned-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>\nAcked-by: Alvin Šipraga <alsi@bang-olufsen.dk>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts | 76 ++++++++++++++++++++\n 1 file changed, 76 insertions(+)\n\n--- a/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts\n+++ b/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts\n@@ -93,6 +93,82 @@\n \t\t\tgpios = <&chipcommon 4 GPIO_ACTIVE_LOW>;\n \t\t};\n \t};\n+\n+\tswitch {\n+\t\tcompatible = \"realtek,rtl8365mb\";\n+\t\t/* 7 = MDIO (has input reads), 6 = MDC (clock, output only) */\n+\t\tmdc-gpios = <&chipcommon 6 GPIO_ACTIVE_HIGH>;\n+\t\tmdio-gpios = <&chipcommon 7 GPIO_ACTIVE_HIGH>;\n+\t\treset-gpios = <&chipcommon 10 GPIO_ACTIVE_LOW>;\n+\t\trealtek,disable-leds;\n+\t\tdsa,member = <1 0>;\n+\n+\t\tports {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tport@0 {\n+\t\t\t\treg = <0>;\n+\t\t\t\tlabel = \"lan5\";\n+\t\t\t\tphy-handle = <&ethphy0>;\n+\t\t\t};\n+\n+\t\t\tport@1 {\n+\t\t\t\treg = <1>;\n+\t\t\t\tlabel = \"lan6\";\n+\t\t\t\tphy-handle = <&ethphy1>;\n+\t\t\t};\n+\n+\t\t\tport@2 {\n+\t\t\t\treg = <2>;\n+\t\t\t\tlabel = \"lan7\";\n+\t\t\t\tphy-handle = <&ethphy2>;\n+\t\t\t};\n+\n+\t\t\tport@3 {\n+\t\t\t\treg = <3>;\n+\t\t\t\tlabel = \"lan8\";\n+\t\t\t\tphy-handle = <&ethphy3>;\n+\t\t\t};\n+\n+\t\t\tport@6 {\n+\t\t\t\treg = <6>;\n+\t\t\t\tlabel = \"cpu\";\n+\t\t\t\tethernet = <&sw0_p5>;\n+\t\t\t\tphy-mode = \"rgmii\";\n+\t\t\t\ttx-internal-delay-ps = <2000>;\n+\t\t\t\trx-internal-delay-ps = <2100>;\n+\n+\t\t\t\tfixed-link {\n+\t\t\t\t\tspeed = <1000>;\n+\t\t\t\t\tfull-duplex;\n+\t\t\t\t\tpause;\n+\t\t\t\t};\n+\t\t\t};\n+\t\t};\n+\n+\t\tmdio {\n+\t\t\tcompatible = \"realtek,smi-mdio\";\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tethphy0: ethernet-phy@0 {\n+\t\t\t\treg = <0>;\n+\t\t\t};\n+\n+\t\t\tethphy1: ethernet-phy@1 {\n+\t\t\t\treg = <1>;\n+\t\t\t};\n+\n+\t\t\tethphy2: ethernet-phy@2 {\n+\t\t\t\treg = <2>;\n+\t\t\t};\n+\n+\t\t\tethphy3: ethernet-phy@3 {\n+\t\t\t\treg = <3>;\n+\t\t\t};\n+\t\t};\n+\t};\n };\n \n &srab {\n"
  },
  {
    "path": "target/linux/bcm53xx/patches-5.15/032-v5.18-0002-ARM-dts-NSP-MX6X-get-mac-address-from-eeprom.patch",
    "content": "From 66848aff05f669e95795b5f3a163f4762781333e Mon Sep 17 00:00:00 2001\nFrom: Matthew Hagan <mnhagan88@gmail.com>\nDate: Wed, 23 Feb 2022 23:50:39 +0000\nSubject: [PATCH] ARM: dts: NSP: MX6X: get mac-address from eeprom\n\nThe MAC address on the MX64/MX65 series is located on the AT24 EEPROM.\nThis is the same as other Meraki devices such as the MR32 [1].\n\n[1] https://lore.kernel.org/linux-arm-kernel/fa8271d02ef74a687f365cebe5c55ec846963ab7.1631986106.git.chunkeey@gmail.com/\n\nSigned-off-by: Matthew Hagan <mnhagan88@gmail.com>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n arch/arm/boot/dts/bcm958625-meraki-mx6x-common.dtsi | 8 ++++++++\n 1 file changed, 8 insertions(+)\n\n--- a/arch/arm/boot/dts/bcm958625-meraki-mx6x-common.dtsi\n+++ b/arch/arm/boot/dts/bcm958625-meraki-mx6x-common.dtsi\n@@ -39,6 +39,8 @@\n \n &amac2 {\n \tstatus = \"okay\";\n+\tnvmem-cells = <&mac_address>;\n+\tnvmem-cell-names = \"mac-address\";\n };\n \n &ehci0 {\n@@ -53,6 +55,12 @@\n \t\treg = <0x50>;\n \t\tpagesize = <32>;\n \t\tread-only;\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <1>;\n+\n+\t\tmac_address: mac-address@66 {\n+\t\t\treg = <0x66 0x6>;\n+\t\t};\n \t};\n };\n \n"
  },
  {
    "path": "target/linux/bcm53xx/patches-5.15/032-v5.18-0003-ARM-dts-NSP-MX6X-correct-LED-function-types.patch",
    "content": "From 482c85c7fc95c572d368b2214b9e9d2c4a2e5789 Mon Sep 17 00:00:00 2001\nFrom: Matthew Hagan <mnhagan88@gmail.com>\nDate: Wed, 23 Feb 2022 23:50:40 +0000\nSubject: [PATCH] ARM: dts: NSP: MX6X: correct LED function types\n\nCurrently, the amber LED will remain always on. This is due to a\nmisinterpretation of the LED sub-node properties, where-by \"default-state\"\nwas used to indicate the initial state when powering on the device. When in\nuse, however, this resulted in the amber LED always being on. Instead change\nthis to only indicate a fault state.\n\nAssign LED_FUNCTION_POWER to the green PWM LED.\n\nThese changes bring the MX64/65 in line with the MR32's devicetree.\n\nSigned-off-by: Matthew Hagan <mnhagan88@gmail.com>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi       | 3 +--\n arch/arm/boot/dts/bcm958625-meraki-kingpin.dtsi     | 3 +--\n arch/arm/boot/dts/bcm958625-meraki-mx6x-common.dtsi | 2 +-\n 3 files changed, 3 insertions(+), 5 deletions(-)\n\n--- a/arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi\n+++ b/arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi\n@@ -57,10 +57,9 @@\n \n \t\tled-4 {\n \t\t\t/* amber:power */\n-\t\t\tfunction = LED_FUNCTION_POWER;\n+\t\t\tfunction = LED_FUNCTION_FAULT;\n \t\t\tcolor = <LED_COLOR_ID_AMBER>;\n \t\t\tgpios = <&gpioa 3 GPIO_ACTIVE_HIGH>;\n-\t\t\tdefault-state = \"on\";\n \t\t};\n \n \t\tled-5 {\n--- a/arch/arm/boot/dts/bcm958625-meraki-kingpin.dtsi\n+++ b/arch/arm/boot/dts/bcm958625-meraki-kingpin.dtsi\n@@ -106,10 +106,9 @@\n \n \t\tled-a {\n \t\t\t/* amber:power */\n-\t\t\tfunction = LED_FUNCTION_POWER;\n+\t\t\tfunction = LED_FUNCTION_FAULT;\n \t\t\tcolor = <LED_COLOR_ID_AMBER>;\n \t\t\tgpios = <&gpioa 0 GPIO_ACTIVE_LOW>;\n-\t\t\tdefault-state = \"on\";\n \t\t};\n \n \t\tled-b {\n--- a/arch/arm/boot/dts/bcm958625-meraki-mx6x-common.dtsi\n+++ b/arch/arm/boot/dts/bcm958625-meraki-mx6x-common.dtsi\n@@ -22,7 +22,7 @@\n \t\t};\n \n \t\tled-2 {\n-\t\t\tfunction = LED_FUNCTION_INDICATOR;\n+\t\t\tfunction = LED_FUNCTION_POWER;\n \t\t\tcolor = <LED_COLOR_ID_GREEN>;\n \t\t\tpwms = <&pwm 2 50000>;\n \t\t\tmax-brightness = <255>;\n"
  },
  {
    "path": "target/linux/bcm53xx/patches-5.15/032-v5.18-0004-ARM-dts-BCM5301X-Add-Ethernet-MAC-address-to-Luxul-X.patch",
    "content": "From c8442f0fb09ca3d842b9b23d1d0650f649fd10f8 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Mon, 28 Feb 2022 10:52:07 +0100\nSubject: [PATCH] ARM: dts: BCM5301X: Add Ethernet MAC address to Luxul\n XWR-3150\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nLuxul XWR-3150 stores MAC as NVRAM variable. Add NVMEM cell for it and\nreference it in the Ethernet interface node.\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts | 8 ++++++++\n 1 file changed, 8 insertions(+)\n\n--- a/arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts\n+++ b/arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts\n@@ -25,6 +25,9 @@\n \tnvram@1eff0000 {\n \t\tcompatible = \"brcm,nvram\";\n \t\treg = <0x1eff0000 0x10000>;\n+\n+\t\tet0macaddr: et0macaddr {\n+\t\t};\n \t};\n \n \tleds {\n@@ -72,6 +75,11 @@\n \t};\n };\n \n+&gmac0 {\n+\tnvmem-cells = <&et0macaddr>;\n+\tnvmem-cell-names = \"mac-address\";\n+};\n+\n &usb3 {\n \tvcc-gpio = <&chipcommon 18 GPIO_ACTIVE_HIGH>;\n };\n"
  },
  {
    "path": "target/linux/bcm53xx/patches-5.15/070-v5.17-phy-bcm-ns-usb2-support-updated-DT-binding-with-PHY-.patch",
    "content": "From d3bc6269e21fc474763708e79c7a118740befb94 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Tue, 26 Oct 2021 11:37:16 +0200\nSubject: [PATCH] phy: bcm-ns-usb2: support updated DT binding with PHY reg\n space\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nUpdated DT binding maps just a PHY's register space instead of the whole\nDMU block. Accessing a common CRU reg is handled using syscon &\nregmap.\n\nThe old binding has been deprecated and remains supported as a fallback\nmethod.\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nLink: https://lore.kernel.org/r/20211026093716.5567-1-zajec5@gmail.com\nSigned-off-by: Vinod Koul <vkoul@kernel.org>\n---\n drivers/phy/broadcom/phy-bcm-ns-usb2.c | 52 +++++++++++++++++++++-----\n 1 file changed, 43 insertions(+), 9 deletions(-)\n\n--- a/drivers/phy/broadcom/phy-bcm-ns-usb2.c\n+++ b/drivers/phy/broadcom/phy-bcm-ns-usb2.c\n@@ -9,17 +9,23 @@\n #include <linux/clk.h>\n #include <linux/delay.h>\n #include <linux/err.h>\n+#include <linux/mfd/syscon.h>\n #include <linux/module.h>\n #include <linux/of_address.h>\n #include <linux/of_platform.h>\n #include <linux/phy/phy.h>\n #include <linux/platform_device.h>\n+#include <linux/regmap.h>\n #include <linux/slab.h>\n \n struct bcm_ns_usb2 {\n \tstruct device *dev;\n \tstruct clk *ref_clk;\n \tstruct phy *phy;\n+\tstruct regmap *clkset;\n+\tvoid __iomem *base;\n+\n+\t/* Deprecated binding */\n \tvoid __iomem *dmu;\n };\n \n@@ -27,7 +33,6 @@ static int bcm_ns_usb2_phy_init(struct p\n {\n \tstruct bcm_ns_usb2 *usb2 = phy_get_drvdata(phy);\n \tstruct device *dev = usb2->dev;\n-\tvoid __iomem *dmu = usb2->dmu;\n \tu32 ref_clk_rate, usb2ctl, usb_pll_ndiv, usb_pll_pdiv;\n \tint err = 0;\n \n@@ -44,7 +49,10 @@ static int bcm_ns_usb2_phy_init(struct p\n \t\tgoto err_clk_off;\n \t}\n \n-\tusb2ctl = readl(dmu + BCMA_DMU_CRU_USB2_CONTROL);\n+\tif (usb2->base)\n+\t\tusb2ctl = readl(usb2->base);\n+\telse\n+\t\tusb2ctl = readl(usb2->dmu + BCMA_DMU_CRU_USB2_CONTROL);\n \n \tif (usb2ctl & BCMA_DMU_CRU_USB2_CONTROL_USB_PLL_PDIV_MASK) {\n \t\tusb_pll_pdiv = usb2ctl;\n@@ -58,15 +66,24 @@ static int bcm_ns_usb2_phy_init(struct p\n \tusb_pll_ndiv = (1920000000 * usb_pll_pdiv) / ref_clk_rate;\n \n \t/* Unlock DMU PLL settings with some magic value */\n-\twritel(0x0000ea68, dmu + BCMA_DMU_CRU_CLKSET_KEY);\n+\tif (usb2->clkset)\n+\t\tregmap_write(usb2->clkset, 0, 0x0000ea68);\n+\telse\n+\t\twritel(0x0000ea68, usb2->dmu + BCMA_DMU_CRU_CLKSET_KEY);\n \n \t/* Write USB 2.0 PLL control setting */\n \tusb2ctl &= ~BCMA_DMU_CRU_USB2_CONTROL_USB_PLL_NDIV_MASK;\n \tusb2ctl |= usb_pll_ndiv << BCMA_DMU_CRU_USB2_CONTROL_USB_PLL_NDIV_SHIFT;\n-\twritel(usb2ctl, dmu + BCMA_DMU_CRU_USB2_CONTROL);\n+\tif (usb2->base)\n+\t\twritel(usb2ctl, usb2->base);\n+\telse\n+\t\twritel(usb2ctl, usb2->dmu + BCMA_DMU_CRU_USB2_CONTROL);\n \n \t/* Lock DMU PLL settings */\n-\twritel(0x00000000, dmu + BCMA_DMU_CRU_CLKSET_KEY);\n+\tif (usb2->clkset)\n+\t\tregmap_write(usb2->clkset, 0, 0x00000000);\n+\telse\n+\t\twritel(0x00000000, usb2->dmu + BCMA_DMU_CRU_CLKSET_KEY);\n \n err_clk_off:\n \tclk_disable_unprepare(usb2->ref_clk);\n@@ -90,10 +107,27 @@ static int bcm_ns_usb2_probe(struct plat\n \t\treturn -ENOMEM;\n \tusb2->dev = dev;\n \n-\tusb2->dmu = devm_platform_ioremap_resource_byname(pdev, \"dmu\");\n-\tif (IS_ERR(usb2->dmu)) {\n-\t\tdev_err(dev, \"Failed to map DMU regs\\n\");\n-\t\treturn PTR_ERR(usb2->dmu);\n+\tif (of_find_property(dev->of_node, \"brcm,syscon-clkset\", NULL)) {\n+\t\tusb2->base = devm_platform_ioremap_resource(pdev, 0);\n+\t\tif (IS_ERR(usb2->base)) {\n+\t\t\tdev_err(dev, \"Failed to map control reg\\n\");\n+\t\t\treturn PTR_ERR(usb2->base);\n+\t\t}\n+\n+\t\tusb2->clkset = syscon_regmap_lookup_by_phandle(dev->of_node,\n+\t\t\t\t\t\t\t       \"brcm,syscon-clkset\");\n+\t\tif (IS_ERR(usb2->clkset)) {\n+\t\t\tdev_err(dev, \"Failed to lookup clkset regmap\\n\");\n+\t\t\treturn PTR_ERR(usb2->clkset);\n+\t\t}\n+\t} else {\n+\t\tusb2->dmu = devm_platform_ioremap_resource_byname(pdev, \"dmu\");\n+\t\tif (IS_ERR(usb2->dmu)) {\n+\t\t\tdev_err(dev, \"Failed to map DMU regs\\n\");\n+\t\t\treturn PTR_ERR(usb2->dmu);\n+\t\t}\n+\n+\t\tdev_warn(dev, \"using deprecated DT binding\\n\");\n \t}\n \n \tusb2->ref_clk = devm_clk_get(dev, \"phy-ref-clk\");\n"
  },
  {
    "path": "target/linux/bcm53xx/patches-5.15/140-mtd-parsers-trx-parse-firmware-MTD-partitions-only.patch",
    "content": "From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Tue, 13 Apr 2021 18:25:20 +0200\nSubject: [PATCH] mtd: parsers: trx: parse \"firmware\" MTD partitions only\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nParsing every partition with \"compatible\" set to \"brcm,trx\" results in\nparsing both: firmware partition and failsafe partition on devices that\nimplement failsafe booting. This affects e.g. Linksys EA9500 which has:\n\npartition@200000 {\n\treg = <0x0200000 0x01d00000>;\n\tcompatible = \"linksys,ns-firmware\", \"brcm,trx\";\n};\n\npartition@1f00000 {\n\treg = <0x01f00000 0x01d00000>;\n\tcompatible = \"linksys,ns-firmware\", \"brcm,trx\";\n};\n\nCheck for MTD partition name \"firmware\" before parsing. Recently added\nofpart_linksys_ns.c creates \"firmware\" and \"failsafe\" depending on\nbootloader setup.\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\n---\n drivers/mtd/parsers/parser_trx.c | 4 ++++\n 1 file changed, 4 insertions(+)\n\n--- a/drivers/mtd/parsers/parser_trx.c\n+++ b/drivers/mtd/parsers/parser_trx.c\n@@ -92,6 +92,10 @@ static int parser_trx_parse(struct mtd_i\n \tif (err != 0 && err != -EINVAL)\n \t\tpr_err(\"failed to parse \\\"brcm,trx-magic\\\" DT attribute, using default: %d\\n\", err);\n \n+\t/* Don't parse any failsafe / backup partitions */\n+\tif (strcmp(mtd->name, \"firmware\"))\n+\t\treturn -EINVAL;\n+\n \tparts = kcalloc(TRX_PARSER_MAX_PARTS, sizeof(struct mtd_partition),\n \t\t\tGFP_KERNEL);\n \tif (!parts)\n"
  },
  {
    "path": "target/linux/bcm53xx/patches-5.15/180-usb-xhci-add-support-for-performing-fake-doorbell.patch",
    "content": "From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Sat, 1 Oct 2016 22:54:48 +0200\nSubject: [PATCH] usb: xhci: add support for performing fake doorbell\n\nBroadcom's Northstar XHCI controllers seem to need a special start\nprocedure to work correctly. There isn't any official documentation of\nthis, the problem is that controller doesn't detect any connected\ndevices with default setup. Moreover connecting USB device to controller\nthat doesn't run properly can cause SoC's watchdog issues.\n\nA workaround that was successfully tested on multiple devices is to\nperform a fake doorbell. This patch adds code for doing this and enables\nit on BCM4708 family.\n---\n drivers/usb/host/xhci-plat.c |  6 +++++\n drivers/usb/host/xhci.c      | 63 +++++++++++++++++++++++++++++++++++++++++---\n drivers/usb/host/xhci.h      |  1 +\n 3 files changed, 67 insertions(+), 3 deletions(-)\n\n--- a/drivers/usb/host/xhci-plat.c\n+++ b/drivers/usb/host/xhci-plat.c\n@@ -77,6 +77,8 @@ static int xhci_priv_resume_quirk(struct\n static void xhci_plat_quirks(struct device *dev, struct xhci_hcd *xhci)\n {\n \tstruct xhci_plat_priv *priv = xhci_to_priv(xhci);\n+\tstruct platform_device*pdev = to_platform_device(dev);\n+\tstruct device_node *node = pdev->dev.of_node;\n \n \t/*\n \t * As of now platform drivers don't provide MSI support so we ensure\n@@ -84,6 +86,9 @@ static void xhci_plat_quirks(struct devi\n \t * dev struct in order to setup MSI\n \t */\n \txhci->quirks |= XHCI_PLAT | priv->quirks;\n+\n+\tif (node && of_machine_is_compatible(\"brcm,bcm4708\"))\n+\t\txhci->quirks |= XHCI_FAKE_DOORBELL;\n }\n \n /* called during probe() after chip reset completes */\n--- a/drivers/usb/host/xhci.c\n+++ b/drivers/usb/host/xhci.c\n@@ -155,6 +155,49 @@ int xhci_start(struct xhci_hcd *xhci)\n \treturn ret;\n }\n \n+/**\n+ * xhci_fake_doorbell - Perform a fake doorbell on a specified slot\n+ *\n+ * Some controllers require a fake doorbell to start correctly. Without that\n+ * they simply don't detect any devices.\n+ */\n+static int xhci_fake_doorbell(struct xhci_hcd *xhci, int slot_id)\n+{\n+\tu32 temp;\n+\n+\t/* Alloc a virt device for that slot */\n+\tif (!xhci_alloc_virt_device(xhci, slot_id, NULL, GFP_NOIO)) {\n+\t\txhci_warn(xhci, \"Could not allocate xHCI USB device data structures\\n\");\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\t/* Ring fake doorbell for slot_id ep 0 */\n+\txhci_ring_ep_doorbell(xhci, slot_id, 0, 0);\n+\tusleep_range(1000, 1500);\n+\n+\t/* Read the status to check if HSE is set or not */\n+\ttemp = readl(&xhci->op_regs->status);\n+\n+\t/* Clear HSE if set */\n+\tif (temp & STS_FATAL) {\n+\t\txhci_dbg(xhci, \"HSE problem detected, status: 0x%08x\\n\", temp);\n+\t\ttemp &= ~0x1fff;\n+\t\ttemp |= STS_FATAL;\n+\t\twritel(temp, &xhci->op_regs->status);\n+\t\tusleep_range(1000, 1500);\n+\t\treadl(&xhci->op_regs->status);\n+\t}\n+\n+\t/* Free virt device */\n+\txhci_free_virt_device(xhci, slot_id);\n+\n+\t/* We're done if controller is already running */\n+\tif (readl(&xhci->op_regs->command) & CMD_RUN)\n+\t\treturn 0;\n+\n+\treturn xhci_start(xhci);\n+}\n+\n /*\n  * Reset a halted HC.\n  *\n@@ -605,10 +648,20 @@ static int xhci_init(struct usb_hcd *hcd\n \n static int xhci_run_finished(struct xhci_hcd *xhci)\n {\n-\tif (xhci_start(xhci)) {\n-\t\txhci_halt(xhci);\n-\t\treturn -ENODEV;\n+\tint err;\n+\n+\terr = xhci_start(xhci);\n+\tif (err) {\n+\t\terr = -ENODEV;\n+\t\tgoto err_halt;\n \t}\n+\n+\tif (xhci->quirks & XHCI_FAKE_DOORBELL) {\n+\t\terr = xhci_fake_doorbell(xhci, 1);\n+\t\tif (err)\n+\t\t\tgoto err_halt;\n+\t}\n+\n \txhci->shared_hcd->state = HC_STATE_RUNNING;\n \txhci->cmd_ring_state = CMD_RING_STATE_RUNNING;\n \n@@ -618,6 +671,10 @@ static int xhci_run_finished(struct xhci\n \txhci_dbg_trace(xhci, trace_xhci_dbg_init,\n \t\t\t\"Finished xhci_run for USB3 roothub\");\n \treturn 0;\n+\n+err_halt:\n+\txhci_halt(xhci);\n+\treturn err;\n }\n \n /*\n--- a/drivers/usb/host/xhci.h\n+++ b/drivers/usb/host/xhci.h\n@@ -1903,6 +1903,7 @@ struct xhci_hcd {\n #define XHCI_NO_SOFT_RETRY\tBIT_ULL(40)\n #define XHCI_BROKEN_D3COLD\tBIT_ULL(41)\n #define XHCI_EP_CTX_BROKEN_DCS\tBIT_ULL(42)\n+#define XHCI_FAKE_DOORBELL\tBIT_ULL(44)\n \n \tunsigned int\t\tnum_active_eps;\n \tunsigned int\t\tlimit_active_eps;\n"
  },
  {
    "path": "target/linux/bcm53xx/patches-5.15/300-ARM-BCM5301X-Disable-MMU-and-Dcache-during-decompres.patch",
    "content": "From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Wed, 24 Sep 2014 22:14:07 +0200\nSubject: [PATCH] ARM: BCM5301X: Disable MMU and Dcache during decompression\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nBroadcom devices have broken CFE (bootloader) that leaves hardware in an\ninvalid state. It causes problems with booting Linux. On Northstar\ndevices kernel was randomly hanging in ~25% of tries during early init.\nHangs used to happen at random places in the start_kernel. On BCM53573\nkernel doesn't even seem to start booting.\n\nTo workaround this problem we need to do following very early:\n1) Clear 2 following bits in the SCTLR register:\n#define CR_M    (1 << 0)        /* MMU enable */\n#define CR_C    (1 << 2)        /* Dcache enable */\n2) Flush the whole D-cache\n3) Disable L2 cache\n\nUnfortunately this patch is not upstreamable as it does above things\nunconditionally. We can't check if we are running on Broadcom platform\nin any safe way and doing such hacks with ARCH_MULTI_V7 is unacceptable\nas it could break other devices support.\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\n---\n\n--- a/arch/arm/boot/compressed/Makefile\n+++ b/arch/arm/boot/compressed/Makefile\n@@ -36,6 +36,11 @@ ifeq ($(CONFIG_ARCH_ACORN),y)\n OBJS\t\t+= ll_char_wr.o font.o\n endif\n \n+ifeq ($(CONFIG_ARCH_BCM_5301X),y)\n+OBJS\t\t+= head-bcm_5301x-mpcore.o\n+OBJS\t\t+= cache-v7-min.o\n+endif\n+\n ifeq ($(CONFIG_ARCH_SA1100),y)\n OBJS\t\t+= head-sa1100.o\n endif\n--- /dev/null\n+++ b/arch/arm/boot/compressed/head-bcm_5301x-mpcore.S\n@@ -0,0 +1,37 @@\n+/*\n+ *\n+ * Platform specific tweaks.  This is merged into head.S by the linker.\n+ *\n+ */\n+\n+#include <linux/linkage.h>\n+#include <asm/assembler.h>\n+#include <asm/cp15.h>\n+\n+\t\t.section        \".start\", \"ax\"\n+\n+/*\n+ * This code section is spliced into the head code by the linker\n+ */\n+\n+__plat_uncompress_start:\n+\n+\t@ Preserve r8/r7 i.e. kernel entry values\n+\tmov\tr12, r8\n+\n+\t@ Clear MMU enable and Dcache enable bits\n+\tmrc\tp15, 0, r0, c1, c0, 0\t\t@ Read SCTLR\n+\tbic\tr0, #CR_C|CR_M\n+\tmcr\tp15, 0, r0, c1, c0, 0\t\t@ Write SCTLR\n+\tnop\n+\n+\t@ Call the cache invalidation routine\n+\tbl\tv7_flush_dcache_all\n+\tnop\n+\tmov\tr0,#0\n+\tldr\tr3, =0x19022000\t\t\t@ L2 cache controller, control reg\n+\tstr\tr0, [r3, #0x100]\t\t@ Disable L2 cache\n+\tnop\n+\n+\t@ Restore\n+\tmov\tr8, r12\n--- a/arch/arm/boot/compressed/cache-v7-min.S\n+++ b/arch/arm/boot/compressed/cache-v7-min.S\n@@ -12,6 +12,7 @@\n \n #include <linux/linkage.h>\n #include <linux/init.h>\n+#include <asm/assembler.h>\n \n \t__INIT\n \n@@ -63,7 +64,7 @@ loop2:\n  ARM(\torr\tr11, r11, r9, lsl r2\t)\t@ factor index number into r11\n  THUMB(\tlsl\tr6, r9, r2\t\t)\n  THUMB(\torr\tr11, r11, r6\t\t)\t@ factor index number into r11\n-\tmcr\tp15, 0, r11, c7, c14, 2\t\t@ clean & invalidate by set/way\n+\tmcr     p15, 0, r11, c7, c6, 2\t\t@ clean & invalidate by set/way\n \tsubs\tr9, r9, #1\t\t\t@ decrement the index\n \tbge\tloop2\n \tsubs\tr4, r4, #1\t\t\t@ decrement the way\n"
  },
  {
    "path": "target/linux/bcm53xx/patches-5.15/304-ARM-dts-BCM5301X-Specify-switch-ports-for-remaining-.patch",
    "content": "From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nSubject: [PATCH] ARM: dts: BCM5301X: Specify switch ports for remaining\n devices\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\n---\n\n--- a/arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dts\n+++ b/arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dts\n@@ -93,3 +93,40 @@\n &usb3_phy {\n \tstatus = \"okay\";\n };\n+\n+&srab {\n+\tstatus = \"okay\";\n+\n+\tports {\n+\t\tport@0 {\n+\t\t\treg = <0>;\n+\t\t\tlabel = \"lan1\";\n+\t\t};\n+\n+\t\tport@1 {\n+\t\t\treg = <1>;\n+\t\t\tlabel = \"lan2\";\n+\t\t};\n+\n+\t\tport@2 {\n+\t\t\treg = <2>;\n+\t\t\tlabel = \"lan3\";\n+\t\t};\n+\n+\t\tport@3 {\n+\t\t\treg = <3>;\n+\t\t\tlabel = \"lan4\";\n+\t\t};\n+\n+\t\tport@4 {\n+\t\t\treg = <4>;\n+\t\t\tlabel = \"wan\";\n+\t\t};\n+\n+\t\tport@5 {\n+\t\t\treg = <5>;\n+\t\t\tlabel = \"cpu\";\n+\t\t\tethernet = <&gmac0>;\n+\t\t};\n+\t};\n+};\n--- a/arch/arm/boot/dts/bcm4708-asus-rt-ac68u.dts\n+++ b/arch/arm/boot/dts/bcm4708-asus-rt-ac68u.dts\n@@ -83,3 +83,40 @@\n &usb3_phy {\n \tstatus = \"okay\";\n };\n+\n+&srab {\n+\tstatus = \"okay\";\n+\n+\tports {\n+\t\tport@0 {\n+\t\t\treg = <0>;\n+\t\t\tlabel = \"wan\";\n+\t\t};\n+\n+\t\tport@1 {\n+\t\t\treg = <1>;\n+\t\t\tlabel = \"lan1\";\n+\t\t};\n+\n+\t\tport@2 {\n+\t\t\treg = <2>;\n+\t\t\tlabel = \"lan2\";\n+\t\t};\n+\n+\t\tport@3 {\n+\t\t\treg = <3>;\n+\t\t\tlabel = \"lan3\";\n+\t\t};\n+\n+\t\tport@4 {\n+\t\t\treg = <4>;\n+\t\t\tlabel = \"lan4\";\n+\t\t};\n+\n+\t\tport@5 {\n+\t\t\treg = <5>;\n+\t\t\tlabel = \"cpu\";\n+\t\t\tethernet = <&gmac0>;\n+\t\t};\n+\t};\n+};\n--- a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts\n+++ b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts\n@@ -149,3 +149,40 @@\n &usb3_phy {\n \tstatus = \"okay\";\n };\n+\n+&srab {\n+\tstatus = \"okay\";\n+\n+\tports {\n+\t\tport@0 {\n+\t\t\treg = <0>;\n+\t\t\tlabel = \"lan1\";\n+\t\t};\n+\n+\t\tport@1 {\n+\t\t\treg = <1>;\n+\t\t\tlabel = \"lan2\";\n+\t\t};\n+\n+\t\tport@2 {\n+\t\t\treg = <2>;\n+\t\t\tlabel = \"lan3\";\n+\t\t};\n+\n+\t\tport@3 {\n+\t\t\treg = <3>;\n+\t\t\tlabel = \"lan4\";\n+\t\t};\n+\n+\t\tport@4 {\n+\t\t\treg = <4>;\n+\t\t\tlabel = \"wan\";\n+\t\t};\n+\n+\t\tport@5 {\n+\t\t\treg = <5>;\n+\t\t\tlabel = \"cpu\";\n+\t\t\tethernet = <&gmac0>;\n+\t\t};\n+\t};\n+};\n--- a/arch/arm/boot/dts/bcm4708-linksys-ea6300-v1.dts\n+++ b/arch/arm/boot/dts/bcm4708-linksys-ea6300-v1.dts\n@@ -46,3 +46,40 @@\n &usb3_phy {\n \tstatus = \"okay\";\n };\n+\n+&srab {\n+\tstatus = \"okay\";\n+\n+\tports {\n+\t\tport@0 {\n+\t\t\treg = <0>;\n+\t\t\tlabel = \"lan1\";\n+\t\t};\n+\n+\t\tport@1 {\n+\t\t\treg = <1>;\n+\t\t\tlabel = \"lan2\";\n+\t\t};\n+\n+\t\tport@2 {\n+\t\t\treg = <2>;\n+\t\t\tlabel = \"lan3\";\n+\t\t};\n+\n+\t\tport@3 {\n+\t\t\treg = <3>;\n+\t\t\tlabel = \"lan4\";\n+\t\t};\n+\n+\t\tport@4 {\n+\t\t\treg = <4>;\n+\t\t\tlabel = \"wan\";\n+\t\t};\n+\n+\t\tport@5 {\n+\t\t\treg = <5>;\n+\t\t\tlabel = \"cpu\";\n+\t\t\tethernet = <&gmac0>;\n+\t\t};\n+\t};\n+};\n--- a/arch/arm/boot/dts/bcm4708-linksys-ea6500-v2.dts\n+++ b/arch/arm/boot/dts/bcm4708-linksys-ea6500-v2.dts\n@@ -42,3 +42,40 @@\n &usb3_phy {\n \tstatus = \"okay\";\n };\n+\n+&srab {\n+\tstatus = \"okay\";\n+\n+\tports {\n+\t\tport@0 {\n+\t\t\treg = <0>;\n+\t\t\tlabel = \"lan1\";\n+\t\t};\n+\n+\t\tport@1 {\n+\t\t\treg = <1>;\n+\t\t\tlabel = \"lan2\";\n+\t\t};\n+\n+\t\tport@2 {\n+\t\t\treg = <2>;\n+\t\t\tlabel = \"lan3\";\n+\t\t};\n+\n+\t\tport@3 {\n+\t\t\treg = <3>;\n+\t\t\tlabel = \"lan4\";\n+\t\t};\n+\n+\t\tport@4 {\n+\t\t\treg = <4>;\n+\t\t\tlabel = \"wan\";\n+\t\t};\n+\n+\t\tport@5 {\n+\t\t\treg = <5>;\n+\t\t\tlabel = \"cpu\";\n+\t\t\tethernet = <&gmac0>;\n+\t\t};\n+\t};\n+};\n--- a/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts\n+++ b/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts\n@@ -86,3 +86,40 @@\n &usb3_phy {\n \tstatus = \"okay\";\n };\n+\n+&srab {\n+\tstatus = \"okay\";\n+\n+\tports {\n+\t\tport@0 {\n+\t\t\treg = <0>;\n+\t\t\tlabel = \"lan1\";\n+\t\t};\n+\n+\t\tport@1 {\n+\t\t\treg = <1>;\n+\t\t\tlabel = \"lan2\";\n+\t\t};\n+\n+\t\tport@2 {\n+\t\t\treg = <2>;\n+\t\t\tlabel = \"lan3\";\n+\t\t};\n+\n+\t\tport@3 {\n+\t\t\treg = <3>;\n+\t\t\tlabel = \"lan4\";\n+\t\t};\n+\n+\t\tport@4 {\n+\t\t\treg = <4>;\n+\t\t\tlabel = \"wan\";\n+\t\t};\n+\n+\t\tport@5 {\n+\t\t\treg = <5>;\n+\t\t\tlabel = \"cpu\";\n+\t\t\tethernet = <&gmac0>;\n+\t\t};\n+\t};\n+};\n--- a/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts\n+++ b/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts\n@@ -77,3 +77,40 @@\n &usb3_phy {\n \tstatus = \"okay\";\n };\n+\n+&srab {\n+\tstatus = \"okay\";\n+\n+\tports {\n+\t\tport@0 {\n+\t\t\treg = <0>;\n+\t\t\tlabel = \"wan\";\n+\t\t};\n+\n+\t\tport@1 {\n+\t\t\treg = <1>;\n+\t\t\tlabel = \"lan1\";\n+\t\t};\n+\n+\t\tport@2 {\n+\t\t\treg = <2>;\n+\t\t\tlabel = \"lan2\";\n+\t\t};\n+\n+\t\tport@3 {\n+\t\t\treg = <3>;\n+\t\t\tlabel = \"lan3\";\n+\t\t};\n+\n+\t\tport@4 {\n+\t\t\treg = <4>;\n+\t\t\tlabel = \"lan4\";\n+\t\t};\n+\n+\t\tport@5 {\n+\t\t\treg = <5>;\n+\t\t\tlabel = \"cpu\";\n+\t\t\tethernet = <&gmac0>;\n+\t\t};\n+\t};\n+};\n--- a/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts\n+++ b/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts\n@@ -68,6 +68,38 @@\n \tstatus = \"okay\";\n };\n \n+&srab {\n+\tstatus = \"okay\";\n+\n+\tports {\n+\t\tport@0 {\n+\t\t\treg = <0>;\n+\t\t\tlabel = \"wan\";\n+\t\t};\n+\n+\t\tport@1 {\n+\t\t\treg = <1>;\n+\t\t\tlabel = \"lan1\";\n+\t\t};\n+\n+\t\tport@2 {\n+\t\t\treg = <2>;\n+\t\t\tlabel = \"lan2\";\n+\t\t};\n+\n+\t\tport@3 {\n+\t\t\treg = <3>;\n+\t\t\tlabel = \"lan3\";\n+\t\t};\n+\n+\t\tport@7 {\n+\t\t\treg = <7>;\n+\t\t\tlabel = \"cpu\";\n+\t\t\tethernet = <&gmac1>;\n+\t\t};\n+\t};\n+};\n+\n &nandcs {\n \tpartitions {\n \t\tcompatible = \"fixed-partitions\";\n--- a/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts\n+++ b/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts\n@@ -132,3 +132,40 @@\n &usb3_phy {\n \tstatus = \"okay\";\n };\n+\n+&srab {\n+\tstatus = \"okay\";\n+\n+\tports {\n+\t\tport@0 {\n+\t\t\treg = <0>;\n+\t\t\tlabel = \"lan1\";\n+\t\t};\n+\n+\t\tport@1 {\n+\t\t\treg = <1>;\n+\t\t\tlabel = \"lan2\";\n+\t\t};\n+\n+\t\tport@2 {\n+\t\t\treg = <2>;\n+\t\t\tlabel = \"lan3\";\n+\t\t};\n+\n+\t\tport@3 {\n+\t\t\treg = <3>;\n+\t\t\tlabel = \"lan4\";\n+\t\t};\n+\n+\t\tport@4 {\n+\t\t\treg = <4>;\n+\t\t\tlabel = \"wan\";\n+\t\t};\n+\n+\t\tport@5 {\n+\t\t\treg = <5>;\n+\t\t\tlabel = \"cpu\";\n+\t\t\tethernet = <&gmac0>;\n+\t\t};\n+\t};\n+};\n--- a/arch/arm/boot/dts/bcm4709-linksys-ea9200.dts\n+++ b/arch/arm/boot/dts/bcm4709-linksys-ea9200.dts\n@@ -49,3 +49,45 @@\n &usb3_phy {\n \tstatus = \"okay\";\n };\n+\n+&srab {\n+\tstatus = \"okay\";\n+\n+\tports {\n+\t\tport@0 {\n+\t\t\treg = <0>;\n+\t\t\tlabel = \"lan1\";\n+\t\t};\n+\n+\t\tport@1 {\n+\t\t\treg = <1>;\n+\t\t\tlabel = \"lan2\";\n+\t\t};\n+\n+\t\tport@2 {\n+\t\t\treg = <2>;\n+\t\t\tlabel = \"lan3\";\n+\t\t};\n+\n+\t\tport@3 {\n+\t\t\treg = <3>;\n+\t\t\tlabel = \"lan4\";\n+\t\t};\n+\n+\t\tport@4 {\n+\t\t\treg = <4>;\n+\t\t\tlabel = \"wan\";\n+\t\t};\n+\n+\t\tport@8 {\n+\t\t\treg = <8>;\n+\t\t\tlabel = \"cpu\";\n+\t\t\tethernet = <&gmac2>;\n+\n+\t\t\tfixed-link {\n+\t\t\t\tspeed = <1000>;\n+\t\t\t\tfull-duplex;\n+\t\t\t};\n+\t\t};\n+\t};\n+};\n--- a/arch/arm/boot/dts/bcm4709-netgear-r7000.dts\n+++ b/arch/arm/boot/dts/bcm4709-netgear-r7000.dts\n@@ -106,3 +106,40 @@\n &usb3_phy {\n \tstatus = \"okay\";\n };\n+\n+&srab {\n+\tstatus = \"okay\";\n+\n+\tports {\n+\t\tport@0 {\n+\t\t\treg = <0>;\n+\t\t\tlabel = \"wan\";\n+\t\t};\n+\n+\t\tport@1 {\n+\t\t\treg = <1>;\n+\t\t\tlabel = \"lan1\";\n+\t\t};\n+\n+\t\tport@2 {\n+\t\t\treg = <2>;\n+\t\t\tlabel = \"lan2\";\n+\t\t};\n+\n+\t\tport@3 {\n+\t\t\treg = <3>;\n+\t\t\tlabel = \"lan3\";\n+\t\t};\n+\n+\t\tport@4 {\n+\t\t\treg = <4>;\n+\t\t\tlabel = \"lan4\";\n+\t\t};\n+\n+\t\tport@5 {\n+\t\t\treg = <5>;\n+\t\t\tlabel = \"cpu\";\n+\t\t\tethernet = <&gmac0>;\n+\t\t};\n+\t};\n+};\n--- a/arch/arm/boot/dts/bcm47094-netgear-r8500.dts\n+++ b/arch/arm/boot/dts/bcm47094-netgear-r8500.dts\n@@ -94,3 +94,45 @@\n &usb3_phy {\n \tstatus = \"okay\";\n };\n+\n+&srab {\n+\tstatus = \"okay\";\n+\n+\tports {\n+\t\tport@0 {\n+\t\t\treg = <0>;\n+\t\t\tlabel = \"wan\";\n+\t\t};\n+\n+\t\tport@1 {\n+\t\t\treg = <1>;\n+\t\t\tlabel = \"lan1\";\n+\t\t};\n+\n+\t\tport@2 {\n+\t\t\treg = <2>;\n+\t\t\tlabel = \"lan2\";\n+\t\t};\n+\n+\t\tport@3 {\n+\t\t\treg = <3>;\n+\t\t\tlabel = \"lan3\";\n+\t\t};\n+\n+\t\tport@4 {\n+\t\t\treg = <4>;\n+\t\t\tlabel = \"lan4\";\n+\t\t};\n+\n+\t\tport@8 {\n+\t\t\treg = <8>;\n+\t\t\tlabel = \"cpu\";\n+\t\t\tethernet = <&gmac2>;\n+\n+\t\t\tfixed-link {\n+\t\t\t\tspeed = <1000>;\n+\t\t\t\tfull-duplex;\n+\t\t\t};\n+\t\t};\n+\t};\n+};\n--- a/arch/arm/boot/dts/bcm47094-phicomm-k3.dts\n+++ b/arch/arm/boot/dts/bcm47094-phicomm-k3.dts\n@@ -38,6 +38,38 @@\n \tstatus = \"okay\";\n };\n \n+&srab {\n+\tstatus = \"okay\";\n+\n+\tports {\n+\t\tport@0 {\n+\t\t\treg = <0>;\n+\t\t\tlabel = \"lan1\";\n+\t\t};\n+\n+\t\tport@1 {\n+\t\t\treg = <1>;\n+\t\t\tlabel = \"lan2\";\n+\t\t};\n+\n+\t\tport@2 {\n+\t\t\treg = <2>;\n+\t\t\tlabel = \"lan3\";\n+\t\t};\n+\n+\t\tport@3 {\n+\t\t\treg = <3>;\n+\t\t\tlabel = \"wan\";\n+\t\t};\n+\n+\t\tport@5 {\n+\t\t\treg = <5>;\n+\t\t\tlabel = \"cpu\";\n+\t\t\tethernet = <&gmac0>;\n+\t\t};\n+\t};\n+};\n+\n &nandcs {\n \tpartitions {\n \t\tcompatible = \"fixed-partitions\";\n--- a/arch/arm/boot/dts/bcm47081-tplink-archer-c5-v2.dts\n+++ b/arch/arm/boot/dts/bcm47081-tplink-archer-c5-v2.dts\n@@ -91,6 +91,43 @@\n \t};\n };\n \n+&srab {\n+\tstatus = \"okay\";\n+\n+\tports {\n+\t\tport@0 {\n+\t\t\treg = <0>;\n+\t\t\tlabel = \"wan\";\n+\t\t};\n+\n+\t\tport@1 {\n+\t\t\treg = <1>;\n+\t\t\tlabel = \"lan1\";\n+\t\t};\n+\n+\t\tport@2 {\n+\t\t\treg = <2>;\n+\t\t\tlabel = \"lan2\";\n+\t\t};\n+\n+\t\tport@3 {\n+\t\t\treg = <3>;\n+\t\t\tlabel = \"lan3\";\n+\t\t};\n+\n+\t\tport@4 {\n+\t\t\treg = <4>;\n+\t\t\tlabel = \"lan4\";\n+\t\t};\n+\n+\t\tport@5 {\n+\t\t\treg = <5>;\n+\t\t\tlabel = \"cpu\";\n+\t\t\tethernet = <&gmac0>;\n+\t\t};\n+\t};\n+};\n+\n &spi_nor {\n \tstatus = \"okay\";\n \n--- a/arch/arm/boot/dts/bcm4709-tplink-archer-c9-v1.dts\n+++ b/arch/arm/boot/dts/bcm4709-tplink-archer-c9-v1.dts\n@@ -102,6 +102,43 @@\n \tvcc-gpio = <&chipcommon 12 GPIO_ACTIVE_HIGH>;\n };\n \n+&srab {\n+\tstatus = \"okay\";\n+\n+\tports {\n+\t\tport@0 {\n+\t\t\treg = <0>;\n+\t\t\tlabel = \"wan\";\n+\t\t};\n+\n+\t\tport@1 {\n+\t\t\treg = <1>;\n+\t\t\tlabel = \"lan1\";\n+\t\t};\n+\n+\t\tport@2 {\n+\t\t\treg = <2>;\n+\t\t\tlabel = \"lan2\";\n+\t\t};\n+\n+\t\tport@3 {\n+\t\t\treg = <3>;\n+\t\t\tlabel = \"lan3\";\n+\t\t};\n+\n+\t\tport@4 {\n+\t\t\treg = <4>;\n+\t\t\tlabel = \"lan4\";\n+\t\t};\n+\n+\t\tport@5 {\n+\t\t\treg = <5>;\n+\t\t\tlabel = \"cpu\";\n+\t\t\tethernet = <&gmac0>;\n+\t\t};\n+\t};\n+};\n+\n &spi_nor {\n \tstatus = \"okay\";\n \n--- a/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts\n+++ b/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts\n@@ -107,3 +107,41 @@\n &usb3_phy {\n \tstatus = \"okay\";\n };\n+\n+&srab {\n+\tstatus = \"okay\";\n+\n+\tports {\n+\t\tport@0 {\n+\t\t\treg = <0>;\n+\t\t\tlabel = \"lan1\";\n+\t\t};\n+\n+\t\tport@1 {\n+\t\t\treg = <1>;\n+\t\t\tlabel = \"lan2\";\n+\t\t};\n+\n+\t\tport@2 {\n+\t\t\treg = <2>;\n+\t\t\tlabel = \"lan3\";\n+\t\t};\n+\n+\t\tport@3 {\n+\t\t\treg = <3>;\n+\t\t\tlabel = \"lan4\";\n+\t\t};\n+\n+\t\tport@4 {\n+\t\t\treg = <4>;\n+\t\t\tlabel = \"wan\";\n+\t\t};\n+\n+\t\tport@5 {\n+\t\t\treg = <5>;\n+\t\t\tlabel = \"cpu\";\n+\t\t\tethernet = <&gmac0>;\n+\t\t};\n+\t};\n+};\n+\n"
  },
  {
    "path": "target/linux/bcm53xx/patches-5.15/310-ARM-BCM5301X-Add-DT-for-Netgear-R7900.patch",
    "content": "From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <zajec5@gmail.com>\nSubject: [PATCH] ARM: BCM5301X: Add DT for Netgear R7900\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nSigned-off-by: Rafał Miłecki <zajec5@gmail.com>\n---\n\n--- a/arch/arm/boot/dts/Makefile\n+++ b/arch/arm/boot/dts/Makefile\n@@ -115,6 +115,7 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \\\n \tbcm4709-buffalo-wxr-1900dhp.dtb \\\n \tbcm4709-linksys-ea9200.dtb \\\n \tbcm4709-netgear-r7000.dtb \\\n+\tbcm4709-netgear-r7900.dtb \\\n \tbcm4709-netgear-r8000.dtb \\\n \tbcm4709-tplink-archer-c9-v1.dtb \\\n \tbcm47094-asus-rt-ac88u.dtb \\\n--- /dev/null\n+++ b/arch/arm/boot/dts/bcm4709-netgear-r7900.dts\n@@ -0,0 +1,42 @@\n+/*\n+ * Broadcom BCM470X / BCM5301X ARM platform code.\n+ * DTS for Netgear R7900\n+ *\n+ * Copyright (C) 2016 Rafał Miłecki <zajec5@gmail.com>\n+ *\n+ * Licensed under the GNU/GPL. See COPYING for details.\n+ */\n+\n+/dts-v1/;\n+\n+#include \"bcm4709.dtsi\"\n+#include \"bcm5301x-nand-cs0-bch8.dtsi\"\n+\n+/ {\n+\tcompatible = \"netgear,r7900\", \"brcm,bcm4709\", \"brcm,bcm4708\";\n+\tmodel = \"Netgear R7900\";\n+\n+\tchosen {\n+\t\tbootargs = \"console=ttyS0,115200\";\n+\t};\n+\n+\tmemory {\n+\t\treg = <0x00000000 0x08000000\n+\t\t       0x88000000 0x08000000>;\n+\t};\n+\n+\taxi@18000000 {\n+\t\tusb3@23000 {\n+\t\t\treg = <0x00023000 0x1000>;\n+\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <1>;\n+\n+\t\t\tvcc-gpio = <&chipcommon 0 GPIO_ACTIVE_HIGH>;\n+\t\t};\n+\t};\n+};\n+\n+&uart0 {\n+\tstatus = \"okay\";\n+};\n"
  },
  {
    "path": "target/linux/bcm53xx/patches-5.15/320-ARM-dts-BCM5301X-Switch-back-to-old-clock-nodes-name.patch",
    "content": "From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Tue, 23 Nov 2021 13:13:05 +0100\nSubject: [PATCH] ARM: dts: BCM5301X: Switch back to old clock nodes names\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nFirst of all using the same node name prefix resulted in trying to\nregister 2 clocks under the same \"clock-controller\" name:\n\n[    0.000000] __clk_core_init: clk clock-controller already initialized\n[    0.000000] ------------[ cut here ]------------\n[    0.000000] WARNING: CPU: 0 PID: 0 at drivers/clk/bcm/clk-iproc-pll.c:802 iproc_pll_clk_setup+0x4c8/0x4f4\n[    0.000000] Modules linked in:\n[    0.000000] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 5.10.80 #0\n[    0.000000] Hardware name: BCM5301X\n[    0.000000] [<c0108410>] (unwind_backtrace) from [<c0104bc4>] (show_stack+0x10/0x14)\n[    0.000000] [<c0104bc4>] (show_stack) from [<c03dca28>] (dump_stack+0x94/0xa8)\n[    0.000000] [<c03dca28>] (dump_stack) from [<c0118440>] (__warn+0xb8/0x114)\n[    0.000000] [<c0118440>] (__warn) from [<c0118504>] (warn_slowpath_fmt+0x68/0x78)\n[    0.000000] [<c0118504>] (warn_slowpath_fmt) from [<c043281c>] (iproc_pll_clk_setup+0x4c8/0x4f4)\n[    0.000000] [<c043281c>] (iproc_pll_clk_setup) from [<c0818c04>] (nsp_genpll_clk_init+0x30/0x38)\n[    0.000000] [<c0818c04>] (nsp_genpll_clk_init) from [<c0818634>] (of_clk_init+0x118/0x1f8)\n[    0.000000] [<c0818634>] (of_clk_init) from [<c08039b0>] (time_init+0x24/0x30)\n[    0.000000] [<c08039b0>] (time_init) from [<c0800d14>] (start_kernel+0x398/0x50c)\n[    0.000000] [<c0800d14>] (start_kernel) from [<00000000>] (0x0)\n[    0.000000] ---[ end trace fe236bfe9559ee50 ]---\n\nSecondly using any other names than \"lcpll0\" and \"genpll\" breaks output\nclocks:\n\n$ cat /sys/kernel/debug/clk/usbclk/clk_rate\n0\n\nFor some reason iproc_clk_recalc_rate() gets called with \"parent_rate\"\nargument 0 whenever clocks aren't named \"lcpll0\" and \"genpll\".\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\n---\n arch/arm/boot/dts/bcm5301x.dtsi | 4 ++--\n 1 file changed, 2 insertions(+), 2 deletions(-)\n\n--- a/arch/arm/boot/dts/bcm5301x.dtsi\n+++ b/arch/arm/boot/dts/bcm5301x.dtsi\n@@ -421,7 +421,7 @@\n \t\t\t#address-cells = <1>;\n \t\t\t#size-cells = <1>;\n \n-\t\t\tlcpll0: clock-controller@100 {\n+\t\t\tlcpll0: lcpll0@100 {\n \t\t\t\t#clock-cells = <1>;\n \t\t\t\tcompatible = \"brcm,nsp-lcpll0\";\n \t\t\t\treg = <0x100 0x14>;\n@@ -430,7 +430,7 @@\n \t\t\t\t\t\t     \"sdio\", \"ddr_phy\";\n \t\t\t};\n \n-\t\t\tgenpll: clock-controller@140 {\n+\t\t\tgenpll: genpll@140 {\n \t\t\t\t#clock-cells = <1>;\n \t\t\t\tcompatible = \"brcm,nsp-genpll\";\n \t\t\t\treg = <0x140 0x24>;\n"
  },
  {
    "path": "target/linux/bcm53xx/patches-5.15/321-ARM-dts-BCM5301X-Describe-partition-formats.patch",
    "content": "From 7166207bd1d8c46d09d640d46afc685df9bb9083 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Thu, 22 Nov 2018 09:21:49 +0100\nSubject: [PATCH] ARM: dts: BCM5301X: Describe partition formats\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nIt's needed by OpenWrt for custom partitioning.\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\n---\n arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts | 1 +\n 1 file changed, 1 insertion(+)\n\n--- a/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts\n+++ b/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts\n@@ -35,6 +35,7 @@\n \t\t\t\tpartition@0 {\n \t\t\t\t\tlabel = \"firmware\";\n \t\t\t\t\treg = <0x00000000 0x08000000>;\n+\t\t\t\t\tcompatible = \"seama\";\n \t\t\t\t};\n \t\t\t};\n \t\t};\n"
  },
  {
    "path": "target/linux/bcm53xx/patches-5.15/331-Meraki-MR32-Status-LEDs.patch",
    "content": "From: Christian Lamparter <chunkeey@gmail.com>\nDate: Thu, 7 Jun 2018 19:29:12 +0200\nSubject: bcm53xx: add LED status label alias for Meraki MR32\n\nadd an led-status alias label. This is used by OpenWrt's LED\nDTS lookup function to identifiy the indicator LED\n\nSigned-off-by: Christian Lamparter <chunkeey@gmail.com>\n\n--- a/arch/arm/boot/dts/bcm53016-meraki-mr32.dts\n+++ b/arch/arm/boot/dts/bcm53016-meraki-mr32.dts\n@@ -27,6 +27,7 @@\n \n \taliases {\n \t\tserial1 = &uart2;\n+\t\tled-status = &led_status;\n \t};\n \n \tleds {\n@@ -68,7 +69,7 @@\n \t\t\tmax-brightness = <255>;\n \t\t};\n \n-\t\tgreen {\n+\t\tled_status: green {\n \t\t\t/* SYS-LED 1 - Tricolor */\n \t\t\tfunction = LED_FUNCTION_POWER;\n \t\t\tcolor = <LED_COLOR_ID_GREEN>;\n"
  },
  {
    "path": "target/linux/bcm53xx/patches-5.15/500-UBI-Detect-EOF-mark-and-erase-all-remaining-blocks.patch",
    "content": "From 2a2af518266a29323cf30c3f9ba9ef2ceb1dd84b Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <zajec5@gmail.com>\nDate: Thu, 16 Oct 2014 20:52:16 +0200\nSubject: [PATCH] UBI: Detect EOF mark and erase all remaining blocks\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nSigned-off-by: Rafał Miłecki <zajec5@gmail.com>\n---\n drivers/mtd/ubi/attach.c | 5 +++++\n drivers/mtd/ubi/io.c     | 4 ++++\n drivers/mtd/ubi/ubi.h    | 1 +\n 3 files changed, 10 insertions(+)\n\n--- a/drivers/mtd/ubi/attach.c\n+++ b/drivers/mtd/ubi/attach.c\n@@ -82,6 +82,9 @@ static int self_check_ai(struct ubi_devi\n #define AV_ADD\t\tBIT(1)\n #define AV_FIND_OR_ADD\t(AV_FIND | AV_ADD)\n \n+/* Set on finding block with 0xdeadc0de, indicates erasing all blocks behind */\n+bool erase_all_next;\n+\n /**\n  * find_or_add_av - internal function to find a volume, add a volume or do\n  *\t\t    both (find and add if missing).\n@@ -1580,6 +1583,8 @@ int ubi_attach(struct ubi_device *ubi, i\n \tif (!ai)\n \t\treturn -ENOMEM;\n \n+\terase_all_next = false;\n+\n #ifdef CONFIG_MTD_UBI_FASTMAP\n \t/* On small flash devices we disable fastmap in any case. */\n \tif ((int)mtd_div_by_eb(ubi->mtd->size, ubi->mtd) <= UBI_FM_MAX_START) {\n--- a/drivers/mtd/ubi/io.c\n+++ b/drivers/mtd/ubi/io.c\n@@ -717,6 +717,10 @@ int ubi_io_read_ec_hdr(struct ubi_device\n \t}\n \n \tmagic = be32_to_cpu(ec_hdr->magic);\n+\tif (magic == 0xdeadc0de)\n+\t\terase_all_next = true;\n+\tif (erase_all_next)\n+\t\treturn read_err ? UBI_IO_FF_BITFLIPS : UBI_IO_FF;\n \tif (magic != UBI_EC_HDR_MAGIC) {\n \t\tif (mtd_is_eccerr(read_err))\n \t\t\treturn UBI_IO_BAD_HDR_EBADMSG;\n--- a/drivers/mtd/ubi/ubi.h\n+++ b/drivers/mtd/ubi/ubi.h\n@@ -822,6 +822,7 @@ extern struct mutex ubi_devices_mutex;\n extern struct blocking_notifier_head ubi_notifiers;\n \n /* attach.c */\n+extern bool erase_all_next;\n struct ubi_ainf_peb *ubi_alloc_aeb(struct ubi_attach_info *ai, int pnum,\n \t\t\t\t   int ec);\n void ubi_free_aeb(struct ubi_attach_info *ai, struct ubi_ainf_peb *aeb);\n"
  },
  {
    "path": "target/linux/bcm53xx/patches-5.15/800-0001-firmware-bcm47xx_nvram-support-init-from-IO-memory.patch",
    "content": "From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Thu, 11 Mar 2021 08:24:44 +0100\nSubject: [PATCH] firmware: bcm47xx_nvram: support init from IO memory\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\n---\n drivers/firmware/broadcom/bcm47xx_nvram.c | 17 +++++++++++++++++\n include/linux/bcm47xx_nvram.h             |  6 ++++++\n 2 files changed, 23 insertions(+)\n\n--- a/drivers/firmware/broadcom/bcm47xx_nvram.c\n+++ b/drivers/firmware/broadcom/bcm47xx_nvram.c\n@@ -110,6 +110,23 @@ found:\n \treturn 0;\n }\n \n+int bcm47xx_nvram_init_from_iomem(void __iomem *nvram_start, size_t res_size)\n+{\n+\tif (nvram_len) {\n+\t\tpr_warn(\"nvram already initialized\\n\");\n+\t\treturn -EEXIST;\n+\t}\n+\n+\tif (!bcm47xx_nvram_is_valid(nvram_start)) {\n+\t\tpr_err(\"No valid NVRAM found\\n\");\n+\t\treturn -ENOENT;\n+\t}\n+\n+\tbcm47xx_nvram_copy(nvram_start, res_size);\n+\n+\treturn 0;\n+}\n+\n /*\n  * On bcm47xx we need access to the NVRAM very early, so we can't use mtd\n  * subsystem to access flash. We can't even use platform device / driver to\n--- a/include/linux/bcm47xx_nvram.h\n+++ b/include/linux/bcm47xx_nvram.h\n@@ -11,6 +11,7 @@\n #include <linux/vmalloc.h>\n \n #ifdef CONFIG_BCM47XX_NVRAM\n+int bcm47xx_nvram_init_from_iomem(void __iomem *nvram_start, size_t res_size);\n int bcm47xx_nvram_init_from_mem(u32 base, u32 lim);\n int bcm47xx_nvram_getenv(const char *name, char *val, size_t val_len);\n int bcm47xx_nvram_gpio_pin(const char *name);\n@@ -20,6 +21,11 @@ static inline void bcm47xx_nvram_release\n \tvfree(nvram);\n };\n #else\n+static inline int bcm47xx_nvram_init_from_iomem(void __iomem *nvram_start,\n+\t\t\t\t\t\tsize_t res_size)\n+{\n+\treturn -ENOTSUPP;\n+}\n static inline int bcm47xx_nvram_init_from_mem(u32 base, u32 lim)\n {\n \treturn -ENOTSUPP;\n"
  },
  {
    "path": "target/linux/bcm53xx/patches-5.15/800-0002-nvmem-brcm_nvram-provide-NVMEM-content-to-the-NVRAM-.patch",
    "content": "From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Thu, 11 Mar 2021 08:26:14 +0100\nSubject: [PATCH] nvmem: brcm_nvram: provide NVMEM content to the NVRAM driver\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\n---\n drivers/nvmem/brcm_nvram.c | 3 +++\n 1 file changed, 3 insertions(+)\n\n--- a/drivers/nvmem/brcm_nvram.c\n+++ b/drivers/nvmem/brcm_nvram.c\n@@ -3,6 +3,7 @@\n  * Copyright (C) 2021 Rafał Miłecki <rafal@milecki.pl>\n  */\n \n+#include <linux/bcm47xx_nvram.h>\n #include <linux/io.h>\n #include <linux/mod_devicetable.h>\n #include <linux/module.h>\n@@ -46,6 +47,8 @@ static int brcm_nvram_probe(struct platf\n \tif (IS_ERR(priv->base))\n \t\treturn PTR_ERR(priv->base);\n \n+\tbcm47xx_nvram_init_from_iomem(priv->base, resource_size(res));\n+\n \tconfig.dev = dev;\n \tconfig.priv = priv;\n \tconfig.size = resource_size(res);\n"
  },
  {
    "path": "target/linux/bcm53xx/patches-5.15/905-BCM53573-minor-hacks.patch",
    "content": "From 6f1c62440eb6846cb8045d7a5480ec7bbe47c96f Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Mon, 15 Aug 2016 10:30:41 +0200\nSubject: [PATCH] BCM53573 minor hacks\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\n---\n\n--- a/arch/arm/boot/dts/bcm53573.dtsi\n+++ b/arch/arm/boot/dts/bcm53573.dtsi\n@@ -54,6 +54,7 @@\n \t\t\t     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,\n \t\t\t     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,\n \t\t\t     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;\n+\t\tclocks = <&ilp>;\n \t};\n \n \tclocks {\n--- a/drivers/bcma/main.c\n+++ b/drivers/bcma/main.c\n@@ -330,14 +330,6 @@ static int bcma_register_devices(struct\n \t}\n #endif\n \n-#ifdef CONFIG_BCMA_SFLASH\n-\tif (bus->drv_cc.sflash.present) {\n-\t\terr = platform_device_register(&bcma_sflash_dev);\n-\t\tif (err)\n-\t\t\tbcma_err(bus, \"Error registering serial flash\\n\");\n-\t}\n-#endif\n-\n #ifdef CONFIG_BCMA_NFLASH\n \tif (bus->drv_cc.nflash.present) {\n \t\terr = platform_device_register(&bcma_nflash_dev);\n@@ -415,6 +407,14 @@ int bcma_bus_register(struct bcma_bus *b\n \t\t\tbcma_register_core(bus, core);\n \t}\n \n+#ifdef CONFIG_BCMA_SFLASH\n+\tif (bus->drv_cc.sflash.present) {\n+\t\terr = platform_device_register(&bcma_sflash_dev);\n+\t\tif (err)\n+\t\t\tbcma_err(bus, \"Error registering serial flash\\n\");\n+\t}\n+#endif\n+\n \t/* Try to get SPROM */\n \terr = bcma_sprom_get(bus);\n \tif (err == -ENOENT) {\n--- a/drivers/clocksource/arm_arch_timer.c\n+++ b/drivers/clocksource/arm_arch_timer.c\n@@ -14,6 +14,7 @@\n #include <linux/smp.h>\n #include <linux/cpu.h>\n #include <linux/cpu_pm.h>\n+#include <linux/clk.h>\n #include <linux/clockchips.h>\n #include <linux/clocksource.h>\n #include <linux/clocksource_ids.h>\n@@ -946,6 +947,16 @@ static void __init arch_timer_of_configu\n \tif (of_property_read_u32(np, \"clock-frequency\", &arch_timer_rate))\n \t\tarch_timer_rate = rate;\n \n+\t/* Get clk rate through clk driver if present */\n+\tif (!arch_timer_rate) {\n+\t\tstruct clk *clk = of_clk_get(np, 0);\n+\n+\t\tif (!IS_ERR(clk)) {\n+\t\t\tif (!clk_prepare_enable(clk))\n+\t\t\t\tarch_timer_rate = clk_get_rate(clk);\n+\t\t}\n+\t}\n+\n \t/* Check the timer frequency. */\n \tif (validate_timer_rate())\n \t\tpr_warn(\"frequency not available\\n\");\n"
  },
  {
    "path": "target/linux/bcm53xx/profiles/100-Generic.mk",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2013 OpenWrt.org\n\ndefine Profile/Generic\n  NAME:=Broadcom SoC, BCM43xx WiFi (b43, brcmfmac, default)\n  PACKAGES:=kmod-b43 kmod-brcmfmac\nendef\n\ndefine Profile/Generic/Description\n\tPackage set compatible with any hardware using Broadcom BCM47xx or\n\tBCM535x SoCs with an ARM CPU like the BCM4707, BCM4708, BCM4709,\n\tBCM53010\nendef\n\n$(eval $(call Profile,Generic))\n\n"
  },
  {
    "path": "target/linux/bcm63xx/Makefile",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2006-2019 OpenWrt.org\n# Copyright (C) 2016 LEDE project\n\ninclude $(TOPDIR)/rules.mk\n\nARCH:=mips\nBOARD:=bcm63xx\nBOARDNAME:=Broadcom BCM63xx\nSUBTARGETS:=generic smp\nFEATURES:=squashfs usb atm pci pcmcia usbgadget\n\nKERNEL_PATCHVER:=5.10\n\ndefine Target/Description\n\tBuild firmware images for Broadcom based xDSL/routers\n\tcurrently supports BCM6338, BCM6348 and BCM6358 based devices.\n\t(e.g. Inventel Livebox, Siemens SE515, Neufbox 4)\nendef\n\ninclude $(INCLUDE_DIR)/target.mk\n\nDEFAULT_PACKAGES += swconfig kmod-gpio-button-hotplug\n\n$(eval $(call BuildTarget))\n"
  },
  {
    "path": "target/linux/bcm63xx/base-files/etc/board.d/01_leds",
    "content": "#\n# Copyright (C) 2013-2015 OpenWrt.org\n#\n\n. /lib/functions/uci-defaults.sh\n\nboard_config_update\n\nboard=$(board_name)\n\ncase \"$board\" in\nactiontec,r1000h)\n\tucidef_set_led_usbport \"usb\" \"USB\" \"green:usb\" \"usb1-port1\" \"usb2-port1\"\n\t;;\nadb,a4001n|\\\nadb,pdg-a4101n-a-000-1a1-ae|\\\ncomtrend,ar-5315u|\\\ncomtrend,vr-3032u|\\\nd-link,dsl-2750u-c1|\\\nhuawei,hg253s-v2|\\\nnucom,r5010un-v2|\\\nsagem,fast-2704-v2)\n\tucidef_set_led_usbdev \"usb\" \"USB\" \"green:usb\" \"1-1\"\n\t;;\nadb,a4001n1)\n\tucidef_set_led_netdev \"lan\" \"LAN\" \"green:eth\" \"eth0\"\n\tucidef_set_led_usbdev \"usb\" \"USB\" \"green:3g\" \"1-1\"\n\t;;\nadb,pdg-a4001n-a-000-1a1-ax|\\\ntechnicolor,tg582n|\\\ntechnicolor,tg582n-telecom-italia)\n\tucidef_set_led_netdev \"wlan0\" \"WIFI\" \"green:wifi\" \"wlan0\"\n\t;;\nadb,av4202n)\n\tucidef_set_led_netdev \"wlan0\" \"WLAN\" \"blue:wifi\" \"wlan0\"\n\t;;\nbt,home-hub-2-a)\n\tucidef_set_led_netdev \"lan\" \"LAN\" \"blue:broadband\" \"eth0.1\"\n\tucidef_set_led_netdev \"wlan0\" \"WIFI\" \"green:wireless\" \"wlan0\"\n\tucidef_set_led_usbdev \"usb1\" \"USB1\" \"blue:phone\" \"1-1\"\n\tucidef_set_led_usbdev \"usb2\" \"USB2\" \"green:phone\" \"2-1\"\n\t;;\nhuawei,echolife-hg553)\n\tucidef_set_led_netdev \"lan\" \"LAN\" \"blue:lan\" \"eth0\"\n\tucidef_set_led_usbdev \"usb1\" \"USB1\" \"red:hspa\" \"1-1\"\n\tucidef_set_led_usbdev \"usb2\" \"USB2\" \"blue:hspa\" \"1-2\"\n\t;;\nhuawei,echolife-hg556a-a|\\\nhuawei,echolife-hg556a-b|\\\nhuawei,echolife-hg556a-c)\n\tucidef_set_led_netdev \"lan\" \"LAN\" \"red:dsl\" \"eth0\"\n\tucidef_set_led_usbdev \"usb\" \"USB\" \"red:hspa\" \"1-2\"\n\t;;\nhuawei,echolife-hg622|\\\nhuawei,echolife-hg655b)\n\tucidef_set_led_usbdev \"usb\" \"USB\" \"green:usb\" \"1-2\"\n\t;;\ninventel,livebox-1)\n\tucidef_set_led_netdev \"lan\" \"LAN\" \"red:traffic\" \"eth0\"\n\tucidef_set_led_netdev \"wan\" \"WAN\" \"red:adsl\" \"eth1\"\n\tucidef_set_led_netdev \"wlan0\" \"WIFI\" \"red:wifi\" \"wlan0\"\n\t;;\nnetgear,dgnd3700-v1)\n\tucidef_set_led_netdev \"lan\" \"LAN\" \"green:lan\" \"eth0.1\"\n\tucidef_set_led_netdev \"wan\" \"WAN\" \"green:inet\" \"eth0.2\"\n\tucidef_set_led_netdev \"wlan0\" \"WIFI2G\" \"green:wifi2g\" \"wlan0\"\n\tucidef_set_led_netdev \"wlan1\" \"WIFI5G\" \"blue:wifi5g\" \"wlan1\"\n\tucidef_set_led_usbdev \"usb1\" \"USB1\" \"green:usb-back\" \"1-1\"\n\tucidef_set_led_usbdev \"usb2\" \"USB2\" \"green:usb-front\" \"1-2\"\n\t;;\nnetgear,dgnd3700-v2)\n\tucidef_set_led_netdev \"lan\" \"LAN\" \"green:ethernet\" \"eth0\"\n\tucidef_set_led_usbdev \"usb1\" \"USB1\" \"green:usb1\" \"1-1\"\n\tucidef_set_led_usbdev \"usb2\" \"USB2\" \"green:usb2\" \"1-2\"\n\t;;\nnetgear,evg2000)\n\tucidef_set_led_netdev \"lan\" \"LAN\" \"green:lan\" \"eth0\"\n\tucidef_set_led_netdev \"wan\" \"WAN\" \"green:wan\" \"eth1\"\n\tucidef_set_led_netdev \"wlan0\" \"WIFI\" \"green:wireless\" \"wlan0\"\n\tucidef_set_led_usbdev \"usb1\" \"USB1\" \"green:voip1\" \"1-1\"\n\tucidef_set_led_usbdev \"usb2\" \"USB2\" \"green:voip2\" \"1-2\"\n\t;;\nsagem,fast-2704n)\n\tucidef_set_led_netdev \"wan\" \"WAN\" \"green:inet\" \"eth0.2\"\n\t;;\nsercomm,ad1018|\\\nsercomm,ad1018-nor)\n\tucidef_set_led_netdev \"wlan0\" \"WLAN\" \"green:wifi\" \"wlan0\"\n\t;;\nsercomm,h500-s-lowi|\\\nsercomm,h500-s-vfes)\n\tucidef_set_led_netdev \"wan\" \"WAN\" \"green:internet\" \"eth0.2\"\n\t;;\ntelsey,cpva502plus)\n\tucidef_set_led_netdev \"lan\" \"LAN\" \"amber:link\" \"eth0\"\n\t;;\nesac\n\nboard_config_flush\n\nexit 0\n"
  },
  {
    "path": "target/linux/bcm63xx/base-files/etc/board.d/02_network",
    "content": "#\n# Copyright (C) 2012-2015 OpenWrt.org\n#\n\n. /lib/functions/uci-defaults.sh\n\nboard_config_update\n\ncase \"$(board_name)\" in\nactiontec,r1000h|\\\ndynalink,rta770bw|\\\ndynalink,rta770w|\\\nnetgear,cvg834g|\\\nnetgear,dgnd3700-v2|\\\nnetgear,evg2000|\\\nt-com,speedport-w-303v|\\\nt-com,speedport-w-500v)\n\tucidef_set_interface_lan \"eth0\"\n\t;;\nadb,a4001n1|\\\nadb,a4001n|\\\nadb,pdg-a4001n-a-000-1a1-ax|\\\nadb,pdg-a4101n-a-000-1a1-ae|\\\nadb,av4202n|\\\nbrcm,bcm963281tan|\\\nbrcm,bcm96328avng|\\\nbrcm,bcm96368mvngr|\\\ncomtrend,ar-5381u|\\\ncomtrend,ar-5387un|\\\ncomtrend,vr-3025u|\\\ncomtrend,vr-3025un|\\\ncomtrend,vr-3026e|\\\nd-link,dsl-274xb-f1|\\\nd-link,dsl-2750u-c1|\\\nd-link,dsl-275xb-d1|\\\nhuawei,echolife-hg622|\\\nhuawei,echolife-hg655b|\\\nnucom,r5010un-v2|\\\nsagem,fast-2504n|\\\nsagem,fast-2704-v2|\\\ntechnicolor,tg582n|\\\ntechnicolor,tg582n-telecom-italia|\\\nzyxel,p870hw-51a-v2)\n\tucidef_add_switch \"switch0\" \\\n\t\t\"0:lan:1\" \"1:lan:2\" \"2:lan:3\" \"3:lan:4\" \"8t@eth0\"\n\t;;\nalcatel,rg100a|\\\nbelkin,f5d7633|\\\nbrcm,bcm96348gw|\\\nbrcm,bcm96348gw-10|\\\nbrcm,bcm96348gw-11|\\\nbrcm,bcm96358vw|\\\nbrcm,bcm96358vw2|\\\nbt,voyager-2500v-bb|\\\ndavolink,dv-201amr|\\\nd-link,dsl-2650u|\\\ndynalink,rta1025w|\\\nnetgear,dg834gt-pn|\\\npirelli,agpf-s0|\\\nsagem,fast-2404|\\\ntelsey,magic|\\\ntp-link,td-w8900gb|\\\nusrobotics,usr9108)\n\tucidef_set_interfaces_lan_wan \"eth1\" \"eth0\"\n\tucidef_add_switch \"switch0\" \\\n\t\t\"0:lan:4\" \"1:lan:3\" \"2:lan:2\" \"3:lan:1\" \"5u@eth1\"\n\t;;\nasmax,ar-1004g|\\\nbrcm,bcm96338gw|\\\nbrcm,bcm96338w|\\\nbt,voyager-2110|\\\ncomtrend,ct-5365|\\\ncomtrend,ct-536plus|\\\ncomtrend,ct-6373|\\\nd-link,dsl-2640b-b|\\\nd-link,dsl-2640u|\\\ndynalink,rta1320|\\\nnetgear,dg834g-v4|\\\nsagem,fast-2604|\\\ntelsey,cpva642)\n\tucidef_add_switch \"switch0\" \\\n\t\t\"0:lan:4\" \"1:lan:3\" \"2:lan:2\" \"3:lan:1\" \"5u@eth0\"\n\t;;\nbrcm,bcm963268bu-p300)\n\tucidef_add_switch \"switch0\" \\\n\t\t\"0:lan\" \"3:lan\" \"4:lan\" \"5:lan\" \"6:lan\" \"7:lan\" \"8t@eth0\"\n\t;;\nbrcm,bcm96368mvwg)\n\tucidef_add_switch \"switch0\" \\\n\t\t\"1:lan\" \"2:lan\" \"4:lan\" \"5:lan\" \"8t@eth0\"\n\t;;\nbt,home-hub-2-a|\\\nd-link,dsl-274xb-c2|\\\nhuawei,echolife-hg553|\\\nhuawei,echolife-hg556a-a|\\\nhuawei,echolife-hg556a-b|\\\nhuawei,echolife-hg556a-c)\n\tucidef_add_switch \"switch0\" \\\n\t\t\"0:lan:1\" \"1:lan:2\" \"2:lan:3\" \"3:lan:4\" \"5t@eth0\"\n\t;;\ncomtrend,ar-5315u|\\\ninnacomm,w3400v6|\\\nobserva,vh4032n)\n\tucidef_add_switch \"switch0\" \\\n\t\t\"0:lan:4\" \"1:lan:3\" \"2:lan:2\" \"3:lan:1\" \"8t@eth0\"\n\t;;\ncomtrend,vg-8050)\n\tucidef_add_switch \"switch0\" \\\n\t\t\"0:lan:4\" \"1:lan:3\" \"2:lan:2\" \"3:lan:1\" \"4:wan\" \"8t@eth0\"\n\t;;\ncomtrend,vr-3032u)\n\tucidef_add_switch \"switch0\" \\\n\t\t\"0:lan:2\" \"1:lan:3\" \"2:lan:4\" \"3:lan:1\" \"8t@eth0\"\n\t;;\ncomtrend,wap-5813n)\n\tucidef_add_switch \"switch0\" \\\n\t\t\"0:lan\" \"1:lan\" \"2:lan\" \"3:lan\" \"4:wan\" \"5t@eth0\"\n\t;;\nd-link,dva-g3810bn-tl|\\\nhuawei,echolife-hg520v|\\\nsfr,neufbox-4-foxconn-r1|\\\nsfr,neufbox-4-sercomm-r0)\n\tucidef_set_interfaces_lan_wan \"eth1.1\" \"eth0\"\n\tucidef_add_switch \"switch0\" \\\n\t\t\"0:lan:4\" \"1:lan:3\" \"2:lan:2\" \"3:lan:1\" \"5t@eth1\"\n\t;;\nhuawei,hg253s-v2)\n\tucidef_add_switch \"switch0\" \\\n\t\t\"1:lan:4\" \"2:lan:3\" \"3:lan:2\" \"4:lan:1\" \"8t@eth0\"\n\t;;\ninteno,vg50)\n\tucidef_add_switch \"switch0\" \\\n\t\t\"0:lan\" \"1:lan\" \"2:lan\" \"3:lan\" \"4:wan\" \"8t@eth0\"\n\t;;\ninventel,livebox-1|\\\ntelsey,cpva502plus)\n\tucidef_set_interfaces_lan_wan \"eth0\" \"eth1\"\n\t;;\nnetgear,dgnd3700-v1)\n\tucidef_add_switch \"switch0\" \\\n\t\t\"1:lan:4\" \"2:lan:3\" \"3:lan:2\" \"4:lan:1\" \"0:wan\" \"8t@eth0\"\n\t;;\nsagem,fast-2704n|\\\nsercomm,ad1018|\\\nsercomm,ad1018-nor)\n\tucidef_add_switch \"switch0\" \\\n\t\t\"1:lan:3\" \"2:lan:2\" \"3:lan:1\" \"0:wan\" \"8t@eth0\"\n\t;;\nsercomm,h500-s-lowi|\\\nsercomm,h500-s-vfes)\n\tucidef_add_switch \"switch0\" \"4:lan\" \"3:wan\" \"8t@eth0\"\n\t;;\nsfr,neufbox-6-sercomm-r0)\n\tucidef_add_switch \"switch0\" \\\n\t\t\"1:lan\" \"2:lan\" \"3:lan\" \"4:lan\" \"0:wan\" \"9t@eth0\"\n\t;;\nsky,sr102)\n\tucidef_set_interfaces_lan_wan \"eth0.1\" \"eth0.2\"\n\tucidef_add_switch \"switch0\" \\\n\t\t\"0:lan\" \"1:lan\" \"2:lan\" \"3:wan\" \"8t@eth0\"\n\t;;\n*)\n\tucidef_set_interfaces_lan_wan \"eth1\" \"eth0\"\n\t;;\nesac\n\nboard_config_flush\n\nexit 0\n"
  },
  {
    "path": "target/linux/bcm63xx/base-files/etc/hotplug.d/firmware/10-rt2x00-eeprom",
    "content": "#!/bin/sh\n# Based on gabors ralink wisoc implementation.\n\n[ -e /lib/firmware/$FIRMWARE ] && exit 0\n\n. /lib/functions/caldata.sh\n\nboard=$(board_name)\n\ncase \"$FIRMWARE\" in\n\"rt2x00.eeprom\" )\n\tcase $board in\n\thuawei,echolife-hg556a-c)\n\t\tcaldata_extract \"cal_data\" 0x1fe00 0x200\n\t\t;;\n\thuawei,echolife-hg622|\\\n\thuawei,echolife-hg655b)\n\t\tcaldata_extract \"cal_data\" 0x0 0x200\n\t\t;;\n\t*)\n\t\tcaldata_die \"board $board is not supported yet\"\n\t\t;;\n\tesac\n\t;;\nesac\n"
  },
  {
    "path": "target/linux/bcm63xx/base-files/etc/uci-defaults/04_led_migration",
    "content": ". /lib/functions/migrations.sh\n\nboard=$(board_name)\n\ncase \"$board\" in\nbrcm,bcm96318ref-p300|\\\nbrcm,bcm963281tan|\\\nbrcm,bcm96328avng|\\\nd-link,dsl-2640b-b|\\\nd-link,dva-g3810bn-tl|\\\nnetgear,dg834g-v4|\\\nusrobotics,usr9108)\n\tmigrate_leds \"^.*::=\"\n\t;;\nesac\n\nremove_devicename_leds\n\nmigrations_apply system\n\nexit 0\n"
  },
  {
    "path": "target/linux/bcm63xx/base-files/etc/uci-defaults/09_fix_crc",
    "content": "#\n# Copyright (C) 2007 OpenWrt.org\n#\n\n. /lib/functions.sh\n\ndo_fixcrc() {\n\tmtd fixtrx linux\n}\n\ncase \"$(board_name)\" in\n\tactiontec,r1000h|\\\n\tadb,a4001n|\\\n\tadb,a4001n1|\\\n\tadb,pdg-a4001n-a-000-1a1-ax|\\\n\tadb,pdg-a4101n-a-000-1a1-ae|\\\n\tbrcm,bcm96328avng|\\\n\tbrcm,bcm963281tan|\\\n\tbt,voyager-2110|\\\n\tbt,voyager-2500v-bb|\\\n\tcomtrend,ar-5315u|\\\n\tcomtrend,ar-5381u|\\\n\tcomtrend,ar-5387un|\\\n\tcomtrend,vr-3025u|\\\n\tcomtrend,vr-3025un|\\\n\tcomtrend,vr-3026e|\\\n\tcomtrend,wap-5813n|\\\n\tcomtrend,ct-6373|\\\n\td-link,dsl-274xb-f1|\\\n\tdynalink,rta770bw|\\\n\tdynalink,rta770w|\\\n\thuawei,echolife-hg622|\\\n\tnetgear,evg2000|\\\n\tnucom,r5010un-v2|\\\n\tobserva,vh4032n|\\\n\tt-com,speedport-w-303v|\\\n\ttechnicolor,tg582n|\\\n\ttechnicolor,tg582n-telecom-italia|\\\n\ttelsey,cpva502plus|\\\n\ttelsey,cpva642|\\\n\ttelsey,magic|\\\n\tzyxel,p870hw-51a-v2)\n\t\tdo_fixcrc\n\t\t;;\nesac\n"
  },
  {
    "path": "target/linux/bcm63xx/base-files/lib/upgrade/platform.sh",
    "content": "PART_NAME=linux\nREQUIRE_IMAGE_METADATA=0\n\nplatform_check_image() {\n\t[ \"$#\" -gt 1 ] && return 1\n\n\tcase \"$(board_name)\" in\n\t\tcomtrend,vg-8050|\\\n\t\tcomtrend,vr-3032u|\\\n\t\thuawei,hg253s-v2|\\\n\t\tnetgear,dgnd3700-v2|\\\n\t\tsercomm,ad1018|\\\n\t\tsercomm,h500-s-lowi|\\\n\t\tsercomm,h500-s-vfes)\n\t\t\t# NAND sysupgrade\n\t\t\treturn 0\n\t\t\t;;\n\tesac\n\n\tcase \"$(get_magic_word \"$1\")\" in\n\t\t3600|3700|3800)\n\t\t\t# CFE tag versions\n\t\t\treturn 0\n\t\t\t;;\n\t\t*)\n\t\t\techo \"Invalid image type. Please use only .bin files\"\n\t\t\treturn 1\n\t\t\t;;\n\tesac\n}\n\ncfe_jffs2_upgrade_tar() {\n\tlocal tar_file=\"$1\"\n\tlocal kernel_mtd=\"$(find_mtd_index $CI_KERNPART)\"\n\n\tif [ -z \"$kernel_mtd\" ]; then\n\t\techo \"$CI_KERNPART partition not found\"\n\t\treturn 1\n\tfi\n\n\tlocal board_dir=$(tar tf $tar_file | grep -m 1 '^sysupgrade-.*/$')\n\tboard_dir=${board_dir%/}\n\n\tlocal kernel_length=$(tar xf $tar_file ${board_dir}/kernel -O | wc -c 2> /dev/null)\n\tlocal rootfs_length=$(tar xf $tar_file ${board_dir}/root -O | wc -c 2> /dev/null)\n\n\tif [ \"$kernel_length\" = 0 ]; then\n\t\techo \"kernel cannot be empty\"\n\t\treturn 1\n\tfi\n\n\tflash_erase -j /dev/mtd${kernel_mtd} 0 0\n\ttar xf $tar_file ${board_dir}/kernel -O | nandwrite /dev/mtd${kernel_mtd} -\n\n\tlocal rootfs_type=\"$(identify_tar \"$tar_file\" ${board_dir}/root)\"\n\n\tnand_upgrade_prepare_ubi \"$rootfs_length\" \"$rootfs_type\" \"0\" \"0\"\n\n\tlocal ubidev=\"$( nand_find_ubi \"$CI_UBIPART\" )\"\n\n\tlocal root_ubivol=\"$(nand_find_volume $ubidev $CI_ROOTPART)\"\n\ttar xf $tar_file ${board_dir}/root -O | \\\n\t\tubiupdatevol /dev/$root_ubivol -s $rootfs_length -\n\n\tnand_do_upgrade_success\n}\n\nplatform_do_upgrade() {\n\tcase \"$(board_name)\" in\n\t\tcomtrend,vg-8050|\\\n\t\tcomtrend,vr-3032u|\\\n\t\thuawei,hg253s-v2|\\\n\t\tnetgear,dgnd3700-v2)\n\t\t\tREQUIRE_IMAGE_METADATA=1\n\t\t\tcfe_jffs2_upgrade_tar \"$1\"\n\t\t\t;;\n\t\tsercomm,ad1018|\\\n\t\tsercomm,h500-s-lowi|\\\n\t\tsercomm,h500-s-vfes)\n\t\t\tREQUIRE_IMAGE_METADATA=1\n\t\t\tnand_do_upgrade \"$1\"\n\t\t\t;;\n\t\t*)\n\t\t\tdefault_do_upgrade \"$1\"\n\t\t\t;;\n\tesac\n}\n"
  },
  {
    "path": "target/linux/bcm63xx/config-5.10",
    "content": "CONFIG_ARCH_32BIT_OFF_T=y\nCONFIG_ARCH_HIBERNATION_POSSIBLE=y\nCONFIG_ARCH_MMAP_RND_BITS_MAX=15\nCONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15\nCONFIG_ARCH_SUSPEND_POSSIBLE=y\nCONFIG_BCM6345_EXT_IRQ=y\nCONFIG_BCM6345_PERIPH_IRQ=y\nCONFIG_BCM63XX=y\nCONFIG_BCM63XX_CPU_3368=y\nCONFIG_BCM63XX_CPU_6318=y\nCONFIG_BCM63XX_CPU_63268=y\nCONFIG_BCM63XX_CPU_6328=y\nCONFIG_BCM63XX_CPU_6338=y\nCONFIG_BCM63XX_CPU_6345=y\nCONFIG_BCM63XX_CPU_6348=y\nCONFIG_BCM63XX_CPU_6358=y\nCONFIG_BCM63XX_CPU_6362=y\nCONFIG_BCM63XX_CPU_6368=y\nCONFIG_BCM63XX_EHCI=y\nCONFIG_BCM63XX_ENET=y\nCONFIG_BCM63XX_OHCI=y\nCONFIG_BCM63XX_PHY=y\nCONFIG_BCM63XX_WDT=y\nCONFIG_BCMA=y\nCONFIG_BCMA_BLOCKIO=y\n# CONFIG_BCMA_DEBUG is not set\n# CONFIG_BCMA_DRIVER_GMAC_CMN is not set\n# CONFIG_BCMA_DRIVER_MIPS is not set\nCONFIG_BCMA_DRIVER_PCI=y\n# CONFIG_BCMA_DRIVER_PCI_HOSTMODE is not set\nCONFIG_BCMA_HOST_PCI=y\nCONFIG_BCMA_HOST_PCI_POSSIBLE=y\n# CONFIG_BCMA_HOST_SOC is not set\nCONFIG_BCM_NET_PHYLIB=y\nCONFIG_BLK_MQ_PCI=y\nCONFIG_BOARD_BCM63XX_DT=y\nCONFIG_BOARD_BCM963XX=y\nCONFIG_BOARD_LIVEBOX=y\nCONFIG_CEVT_R4K=y\nCONFIG_CLKDEV_LOOKUP=y\nCONFIG_CLONE_BACKWARDS=y\nCONFIG_COMPAT_32BIT_TIME=y\nCONFIG_CPU_BIG_ENDIAN=y\nCONFIG_CPU_BMIPS=y\nCONFIG_CPU_BMIPS32_3300=y\nCONFIG_CPU_BMIPS4350=y\nCONFIG_CPU_GENERIC_DUMP_TLB=y\nCONFIG_CPU_HAS_PREFETCH=y\nCONFIG_CPU_HAS_SYNC=y\nCONFIG_CPU_MIPS32=y\nCONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y\nCONFIG_CPU_NO_EFFICIENT_FFS=y\nCONFIG_CPU_R4K_CACHE_TLB=y\nCONFIG_CPU_SUPPORTS_32BIT_KERNEL=y\nCONFIG_CPU_SUPPORTS_CPUFREQ=y\nCONFIG_CPU_SUPPORTS_HIGHMEM=y\nCONFIG_CRASH_CORE=y\nCONFIG_CRYPTO_LIB_POLY1305_RSIZE=2\nCONFIG_CRYPTO_RNG2=y\nCONFIG_CSRC_R4K=y\nCONFIG_DMA_NONCOHERENT=y\nCONFIG_DTC=y\nCONFIG_EARLY_PRINTK=y\nCONFIG_FIXED_PHY=y\nCONFIG_FW_LOADER_PAGED_BUF=y\nCONFIG_GENERIC_ATOMIC64=y\nCONFIG_GENERIC_CLOCKEVENTS=y\nCONFIG_GENERIC_CMOS_UPDATE=y\nCONFIG_GENERIC_CPU_AUTOPROBE=y\nCONFIG_GENERIC_GETTIMEOFDAY=y\nCONFIG_GENERIC_IOMAP=y\nCONFIG_GENERIC_IRQ_CHIP=y\nCONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y\nCONFIG_GENERIC_IRQ_SHOW=y\nCONFIG_GENERIC_LIB_ASHLDI3=y\nCONFIG_GENERIC_LIB_ASHRDI3=y\nCONFIG_GENERIC_LIB_CMPDI2=y\nCONFIG_GENERIC_LIB_LSHRDI3=y\nCONFIG_GENERIC_LIB_UCMPDI2=y\nCONFIG_GENERIC_PCI_IOMAP=y\nCONFIG_GENERIC_PINCONF=y\nCONFIG_GENERIC_PINCTRL_GROUPS=y\nCONFIG_GENERIC_PINMUX_FUNCTIONS=y\nCONFIG_GENERIC_SCHED_CLOCK=y\nCONFIG_GENERIC_SMP_IDLE_THREAD=y\nCONFIG_GENERIC_TIME_VSYSCALL=y\nCONFIG_GPIOLIB=y\nCONFIG_GPIO_BCM63XX=y\nCONFIG_GPIO_GENERIC=y\nCONFIG_HANDLE_DOMAIN_IRQ=y\nCONFIG_HAS_DMA=y\nCONFIG_HAS_IOMEM=y\nCONFIG_HAS_IOPORT_MAP=y\nCONFIG_HW_RANDOM=y\nCONFIG_HW_RANDOM_BCM2835=y\nCONFIG_HZ_PERIODIC=y\nCONFIG_INITRAMFS_SOURCE=\"\"\nCONFIG_IRQCHIP=y\nCONFIG_IRQ_DOMAIN=y\nCONFIG_IRQ_FORCED_THREADING=y\nCONFIG_IRQ_MIPS_CPU=y\nCONFIG_IRQ_WORK=y\nCONFIG_KEXEC=y\nCONFIG_KEXEC_CORE=y\nCONFIG_LEDS_BCM6328=y\nCONFIG_LEDS_BCM6358=y\nCONFIG_LEDS_GPIO=y\nCONFIG_LIBFDT=y\nCONFIG_LOCK_DEBUGGING_SUPPORT=y\nCONFIG_MDIO_BUS=y\nCONFIG_MDIO_DEVICE=y\nCONFIG_MEMFD_CREATE=y\nCONFIG_MFD_SYSCON=y\nCONFIG_MIGRATION=y\nCONFIG_MIPS=y\nCONFIG_MIPS_ASID_BITS=8\nCONFIG_MIPS_ASID_SHIFT=0\nCONFIG_MIPS_CBPF_JIT=y\nCONFIG_MIPS_CLOCK_VSYSCALL=y\n# CONFIG_MIPS_CMDLINE_DTB_EXTEND is not set\n# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set\nCONFIG_MIPS_CMDLINE_FROM_DTB=y\n# CONFIG_MIPS_ELF_APPENDED_DTB is not set\nCONFIG_MIPS_EXTERNAL_TIMER=y\nCONFIG_MIPS_L1_CACHE_SHIFT=4\nCONFIG_MIPS_L1_CACHE_SHIFT_4=y\nCONFIG_MIPS_LD_CAN_LINK_VDSO=y\n# CONFIG_MIPS_NO_APPENDED_DTB is not set\nCONFIG_MIPS_RAW_APPENDED_DTB=y\nCONFIG_MODULES_USE_ELF_REL=y\nCONFIG_MODULE_FORCE_LOAD=y\nCONFIG_MODULE_FORCE_UNLOAD=y\nCONFIG_MTD_BCM63XX_PARTS=y\nCONFIG_MTD_CFI_ADV_OPTIONS=y\nCONFIG_MTD_CFI_BE_BYTE_SWAP=y\n# CONFIG_MTD_CFI_GEOMETRY is not set\n# CONFIG_MTD_CFI_NOSWAP is not set\nCONFIG_MTD_CFI_STAA=y\n# CONFIG_MTD_COMPLEX_MAPPINGS is not set\nCONFIG_MTD_JEDECPROBE=y\nCONFIG_MTD_PARSER_IMAGETAG=y\nCONFIG_MTD_PHYSMAP=y\nCONFIG_MTD_REDBOOT_PARTS=y\nCONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y\nCONFIG_MTD_SPI_NOR=y\nCONFIG_NEED_DMA_MAP_STATE=y\nCONFIG_NEED_PER_CPU_KM=y\nCONFIG_NO_GENERIC_PCI_IOPORT_MAP=y\nCONFIG_NVMEM=y\nCONFIG_OF=y\nCONFIG_OF_ADDRESS=y\nCONFIG_OF_EARLY_FLATTREE=y\nCONFIG_OF_FLATTREE=y\nCONFIG_OF_GPIO=y\nCONFIG_OF_IRQ=y\nCONFIG_OF_KOBJ=y\nCONFIG_OF_MDIO=y\nCONFIG_OF_NET=y\nCONFIG_PCI=y\nCONFIG_PCIEPORTBUS=y\nCONFIG_PCI_DOMAINS=y\nCONFIG_PCI_DRIVERS_LEGACY=y\nCONFIG_PERF_USE_VMALLOC=y\nCONFIG_PGTABLE_LEVELS=2\nCONFIG_PHYLIB=y\nCONFIG_PINCTRL=y\nCONFIG_PINCTRL_BCM6318=y\nCONFIG_PINCTRL_BCM63268=y\nCONFIG_PINCTRL_BCM6328=y\nCONFIG_PINCTRL_BCM6348=y\nCONFIG_PINCTRL_BCM6358=y\nCONFIG_PINCTRL_BCM6362=y\nCONFIG_PINCTRL_BCM6368=y\nCONFIG_PINCTRL_BCM63XX=y\nCONFIG_POSIX_MQUEUE=y\nCONFIG_POSIX_MQUEUE_SYSCTL=y\nCONFIG_REGMAP=y\nCONFIG_REGMAP_MMIO=y\nCONFIG_RELAY=y\nCONFIG_RTL8366_SMI=y\nCONFIG_RTL8367_PHY=y\n# CONFIG_SERIAL_8250 is not set\nCONFIG_SERIAL_BCM63XX=y\nCONFIG_SERIAL_BCM63XX_CONSOLE=y\nCONFIG_SPI=y\nCONFIG_SPI_BCM63XX=y\nCONFIG_SPI_BCM63XX_HSSPI=y\nCONFIG_SPI_MASTER=y\nCONFIG_SPI_MEM=y\nCONFIG_SRCU=y\nCONFIG_SSB=y\nCONFIG_SSB_B43_PCI_BRIDGE=y\nCONFIG_SSB_BLOCKIO=y\n# CONFIG_SSB_DRIVER_MIPS is not set\nCONFIG_SSB_DRIVER_PCICORE=y\nCONFIG_SSB_DRIVER_PCICORE_POSSIBLE=y\nCONFIG_SSB_PCIHOST=y\nCONFIG_SSB_PCIHOST_POSSIBLE=y\nCONFIG_SSB_SPROM=y\nCONFIG_SWAP_IO_SPACE=y\nCONFIG_SWCONFIG=y\nCONFIG_SWCONFIG_B53=y\nCONFIG_SWCONFIG_B53_MMAP_DRIVER=y\nCONFIG_SWCONFIG_B53_PHY_DRIVER=y\nCONFIG_SWCONFIG_B53_PHY_FIXUP=y\nCONFIG_SWCONFIG_B53_SPI_DRIVER=y\nCONFIG_SWPHY=y\nCONFIG_SYNC_R4K=y\nCONFIG_SYSCTL_EXCEPTION_TRACE=y\nCONFIG_SYS_HAS_CPU_BMIPS=y\nCONFIG_SYS_HAS_CPU_BMIPS32_3300=y\nCONFIG_SYS_HAS_CPU_BMIPS4350=y\nCONFIG_SYS_HAS_EARLY_PRINTK=y\nCONFIG_SYS_SUPPORTS_32BIT_KERNEL=y\nCONFIG_SYS_SUPPORTS_ARBIT_HZ=y\nCONFIG_SYS_SUPPORTS_BIG_ENDIAN=y\nCONFIG_SYS_SUPPORTS_HOTPLUG_CPU=y\nCONFIG_SYS_SUPPORTS_SMP=y\nCONFIG_TARGET_ISA_REV=0\nCONFIG_TICK_CPU_ACCOUNTING=y\nCONFIG_TINY_SRCU=y\nCONFIG_USB_SUPPORT=y\nCONFIG_USE_OF=y\nCONFIG_VM_EVENT_COUNTERS=y\nCONFIG_WATCHDOG_NOWAYOUT=y\nCONFIG_WEAK_ORDERING=y\n"
  },
  {
    "path": "target/linux/bcm63xx/dts/bcm3368-netgear-cvg834g.dts",
    "content": "#include \"bcm3368.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"Netgear CVG834G\";\n\tcompatible = \"netgear,cvg834g\", \"brcm,bcm3368\";\n\n\taliases {\n\t\tled-boot = &led_power_green;\n\t\tled-failsafe = &led_power_green;\n\t\tled-running = &led_power_green;\n\t\tled-upgrade = &led_power_green;\n\t};\n\n\tchosen {\n\t\tbootargs = \"rootfstype=squashfs,jffs2 noinitrd console=ttyS0,115200\";\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power_green: power_green {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio1 5 0>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n};\n\n&pflash {\n\tstatus = \"okay\";\n\n\tpartitions {\n\t\tcompatible = \"fixed-partitions\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tcfe@0 {\n\t\t\tlabel = \"CFE\";\n\t\t\treg = <0x000000 0x010000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tlinux@10000 {\n\t\t\tlabel = \"linux\";\n\t\t\treg = <0x010000 0x3e0000>;\n\t\t\tcompatible = \"brcm,bcm963xx-imagetag\";\n\t\t};\n\n\t\tnvram@3f0000 {\n\t\t\tlabel = \"nvram\";\n\t\t\treg = <0x3f0000 0x010000>;\n\t\t};\n\t};\n};\n\n&uart0 {\n\tstatus = \"okay\";\n};\n\n&uart1 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/bcm63xx/dts/bcm3368.dtsi",
    "content": "/dts-v1/;\n\n/ {\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\tcompatible = \"brcm,bcm3368\";\n\n\taliases {\n\t\tpflash = &pflash;\n\t\tgpio0 = &gpio0;\n\t\tgpio1 = &gpio1;\n\t\tserial0 = &uart0;\n\t\tserial1 = &uart1;\n\t\tspi0 = &lsspi;\n\t};\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu@0 {\n\t\t\tcompatible = \"brcm,bmips4350\", \"mips,mips4Kc\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\treg = <0>;\n\t\t};\n\n\t\tcpu@1 {\n\t\t\tcompatible = \"brcm,bmips4350\", \"mips,mips4Kc\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\treg = <1>;\n\t\t};\n\t};\n\n\tcpu_intc: interrupt-controller {\n\t\t#address-cells = <0>;\n\t\tcompatible = \"mti,cpu-interrupt-controller\";\n\n\t\tinterrupt-controller;\n\t\t#interrupt-cells = <1>;\n\t};\n\n\tmemory { device_type = \"memory\"; reg = <0 0>; };\n\n\tpflash: nor@1e000000 {\n\t\tcompatible = \"cfi-flash\";\n\t\treg = <0x1e000000 0x2000000>;\n\t\tbank-width = <2>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tstatus = \"disabled\";\n\t};\n\n\tubus@fff00000 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tranges;\n\t\tcompatible = \"simple-bus\";\n\t\tinterrupt-parent = <&periph_intc>;\n\n\t\tperiph_intc: interrupt-controller@fff8c00c {\n\t\t\tcompatible = \"brcm,bcm6345-l1-intc\";\n\t\t\treg = <0xfff8c00c 0x8>;\n\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <1>;\n\n\t\t\tinterrupt-parent = <&cpu_intc>;\n\t\t\tinterrupts = <2>;\n\t\t};\n\n\t\text_intc0: interrupt-controller@fff8c014 {\n\t\t\tcompatible = \"brcm,bcm6345-ext-intc\";\n\t\t\treg = <0xfff8c014 0x4>;\n\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <2>;\n\n\t\t\tinterrupts = <25>, <26>, <27>, <28>;\n\t\t};\n\n\t\tgpio1: gpio-controller@fff8c080 {\n\t\t\tcompatible = \"brcm,bcm6345-gpio\";\n\t\t\treg = <0xfff8c080 4>, <0xfff8c088 4>;\n\n\t\t\tgpio-controller;\n\t\t\t#gpio-cells = <2>;\n\n\t\t\tngpios = <8>;\n\t\t};\n\n\t\tgpio0: gpio-controller@fff8c084 {\n\t\t\tcompatible = \"brcm,bcm6345-gpio\";\n\t\t\treg = <0xfff8c084 4>, <0xfff8c08c 4>;\n\n\t\t\tgpio-controller;\n\t\t\t#gpio-cells = <2>;\n\t\t};\n\n\t\tuart0: serial@fff8c100 {\n\t\t\tcompatible = \"brcm,bcm6345-uart\";\n\t\t\treg = <0xfff8c100 0x18>;\n\n\t\t\tinterrupt-parent = <&periph_intc>;\n\t\t\tinterrupts = <2>;\n\n\t\t\t/* clocks = <&periph_clk>; */\n\t\t\t/* clock-names = \"refclk\"; */\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tuart1: serial@fff8c120 {\n\t\t\tcompatible = \"brcm,bcm6345-uart\";\n\t\t\treg = <0xfff8c120 0x18>;\n\n\t\t\tinterrupt-parent = <&periph_intc>;\n\t\t\tinterrupts = <3>;\n\n\t\t\t/* clocks = <&periph_clk>; */\n\t\t\t/* clock-names = \"refclk\"; */\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tlsspi: spi@fff8c800 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tcompatible = \"brcm,bcm6358-spi\";\n\t\t\treg = <0xfff8c800 0x70c>;\n\t\t\tinterrupts = <1>;\n\t\t\t/* clocks = <&clkctl 9>; */\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/bcm63xx/dts/bcm63167-sercomm-h500-s-lowi.dts",
    "content": "// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)\n/*\n * Device Tree file for Sercomm H500-s lowi\n *\n * Copyright (C) 2020 Daniel González Cabanelas <dgcbueu@gmail.com>\n */\n\n#include \"bcm63167-sercomm-h500-s.dtsi\"\n\n/ {\n\tmodel = \"Sercomm H500-s lowi\";\n\tcompatible = \"sercomm,h500-s-lowi\", \"brcm,bcm63167\", \"brcm,bcm63268\";\n};\n"
  },
  {
    "path": "target/linux/bcm63xx/dts/bcm63167-sercomm-h500-s-vfes.dts",
    "content": "// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)\n/*\n * Device Tree file for Sercomm H500-s vfes\n *\n * Copyright (C) 2020 Daniel González Cabanelas <dgcbueu@gmail.com>\n */\n \n#include \"bcm63167-sercomm-h500-s.dtsi\"\n\n/ {\n\tmodel = \"Sercomm H500-s vfes\";\n\tcompatible = \"sercomm,h500-s-vfes\", \"brcm,bcm63167\", \"brcm,bcm63268\";\n};\n"
  },
  {
    "path": "target/linux/bcm63xx/dts/bcm63167-sercomm-h500-s.dtsi",
    "content": "// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)\n/*\n * Device Tree file for Sercomm H500-s\n *\n * Copyright (C) 2020 Daniel González Cabanelas <dgcbueu@gmail.com>\n */\n\n#include \"bcm63268.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\taliases {\n\t\tled-boot = &led_power_green;\n\t\tled-failsafe = &led_power_red;\n\t\tled-running = &led_power_green;\n\t\tled-upgrade = &led_power_green;\n\t};\n\n\tchosen {\n\t\tbootargs = \"rootfstype=squashfs,ubifs noinitrd console=ttyS0,115200\";\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tpoll-interval = <20>;\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&pinctrl 34 1>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&pinctrl 35 1>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n};\n\n&leds {\n\tstatus = \"okay\";\n\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_leds>;\n\n\tmobile_red {\n\t\treg = <0>;\n\t\tlabel = \"red:mobile\";\n\t};\n\n\tmobile_green {\n\t\treg = <1>;\n\t\tlabel = \"green:mobile\";\n\t};\n\n\tled_power_red: power_red {\n\t\treg = <8>;\n\t\tlabel = \"red:power\";\n\t};\n\n\twifi_green {\n\t\treg = <9>;\n\t\tlabel = \"green:wifi\";\n\t};\n\n\tphone_red {\n\t\treg = <12>;\n\t\tlabel = \"red:phone\";\n\t};\n\n\twifi_red {\n\t\treg = <13>;\n\t\tlabel = \"red:wifi\";\n\t};\n\n\tinternet_red {\n\t\treg = <14>;\n\t\tlabel = \"red:internet\";\n\t};\n\n\tinternet_green {\n\t\treg = <15>;\n\t\tlabel = \"green:internet\";\n\t};\n\n\tphone_green {\n\t\treg = <16>;\n\t\tlabel = \"green:phone\";\n\t};\n\n\tled_power_green: power_green {\n\t\treg = <17>;\n\t\tlabel = \"green:power\";\n\t\tdefault-state = \"on\";\n\t};\n\n\tmobile_blue {\n\t\treg = <23>;\n\t\tlabel = \"blue:mobile\";\n\t};\n};\n\n&nflash {\n\tstatus = \"okay\";\n\n\tnandcs@0 {\n\t\tcompatible = \"brcm,nandcs\";\n\t\t#size-cells = <1>;\n\t\t#address-cells = <1>;\n\t\treg = <0>;\n\t\tnand-ecc-step-size = <512>;\n\t\tnand-ecc-strength = <4>;\n\t\tnand-on-flash-bbt;\n\t\tbrcm,nand-oob-sector-size = <64>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"cferom\";\n\t\t\t\treg = <0x0000000 0x0020000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tlabel = \"part_map\";\n\t\t\t\treg = <0x0020000 0x00a0000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@c0000 {\n\t\t\t\tlabel = \"cferam1\";\n\t\t\t\treg = <0x00c0000 0x0140000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@200000 {\n\t\t\t\tlabel = \"cferam2\";\n\t\t\t\treg = <0x0200000 0x0140000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@6920000 {\n\t\t\t\tlabel = \"bootflag1\";\n\t\t\t\treg = <0x6920000 0x0140000>;\n\t\t\t};\n\n\t\t\tpartition@6a60000 {\n\t\t\t\tlabel = \"bootflag2\";\n\t\t\t\treg = <0x6a60000 0x0140000>;\n\t\t\t};\n\n\t\t\tpartition@520000 {\n\t\t\t\tcompatible = \"sercomm,wfi\";\n\t\t\t\tlabel = \"wfi\";\n\t\t\t\treg = <0x0520000 0x6400000>; /* 2 images, 97152 KiB */\n\t\t\t};\n\n\t\t\tpartition@6ba0000 {\n\t\t\t\tlabel = \"xml_cfg\";\n\t\t\t\treg = <0x6ba0000 0x0280000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@6e20000 {\n\t\t\t\tlabel = \"app_data\";\n\t\t\t\treg = <0x6e20000 0x0280000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pinctrl {\n\tpinctrl_leds: leds {\n\t\tfunction = \"led\";\n\t\tpins = \"gpio0\",  \"gpio1\",  \"gpio8\",  \"gpio9\",\n\t\t       \"gpio12\", \"gpio13\", \"gpio14\", \"gpio15\",\n\t\t       \"gpio16\", \"gpio17\", \"gpio23\";\n\t};\n};\n\n&uart0 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/bcm63xx/dts/bcm63168-comtrend-vr-3032u.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later\n\n#include \"bcm63268.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"Comtrend VR-3032u\";\n\tcompatible = \"comtrend,vr-3032u\", \"brcm,bcm63168\", \"brcm,bcm63268\";\n\n\taliases {\n\t\tled-boot = &led_power_green;\n\t\tled-failsafe = &led_power_green;\n\t\tled-running = &led_power_green;\n\t\tled-upgrade = &led_power_green;\n\t};\n\n\tchosen {\n\t\tbootargs = \"rootfstype=squashfs,ubifs noinitrd console=ttyS0,115200\";\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&pinctrl 33 1>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&pinctrl 34 1>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n};\n\n&leds {\n\tstatus = \"okay\";\n\tbrcm,serial-leds;\n\tbrcm,serial-dat-low;\n\tbrcm,serial-shift-inv;\n\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_serial_led>;\n\n\tled@0 {\n\t\t/* GPHY0 Spd 0 */\n\t\treg = <0>;\n\t\tbrcm,hardware-controlled;\n\t\tbrcm,link-signal-sources = <0>;\n\t};\n\n\tled@1 {\n\t\t/* GPHY0 Spd 1 */\n\t\treg = <1>;\n\t\tbrcm,hardware-controlled;\n\t\tbrcm,link-signal-sources = <1>;\n\t};\n\n\tled@2 {\n\t\treg = <2>;\n\t\tactive-low;\n\t\tlabel = \"red:inet\";\n\t};\n\n\tled@3 {\n\t\treg = <3>;\n\t\tactive-low;\n\t\tlabel = \"green:dsl\";\n\t};\n\n\tled@4 {\n\t\treg = <4>;\n\t\tactive-low;\n\t\tlabel = \"green:usb\";\n\t};\n\n\tled@7 {\n\t\treg = <7>;\n\t\tactive-low;\n\t\tlabel = \"green:wps\";\n\t};\n\n\tled@8 {\n\t\treg = <8>;\n\t\tactive-low;\n\t\tlabel = \"green:inet\";\n\t};\n\n\tled@9 {\n\t\t/* EPHY0 Act */\n\t\treg = <9>;\n\t\tbrcm,hardware-controlled;\n\t};\n\n\tled@10 {\n\t\t/* EPHY1 Act */\n\t\treg = <10>;\n\t\tbrcm,hardware-controlled;\n\t};\n\n\tled@11 {\n\t\t/* EPHY2 Act */\n\t\treg = <11>;\n\t\tbrcm,hardware-controlled;\n\t};\n\n\tled@12 {\n\t\t/* GPHY0 Act */\n\t\treg = <12>;\n\t\tbrcm,hardware-controlled;\n\t};\n\n\tled@13 {\n\t\t/* EPHY0 Spd */\n\t\treg = <13>;\n\t\tbrcm,hardware-controlled;\n\t};\n\n\tled@14 {\n\t\t/* EPHY1 Spd */\n\t\treg = <14>;\n\t\tbrcm,hardware-controlled;\n\t};\n\n\tled@15 {\n\t\t/* EPHY2 Spd */\n\t\treg = <15>;\n\t\tbrcm,hardware-controlled;\n\t};\n\n\tled_power_green: led@20 {\n\t\treg = <20>;\n\t\tactive-low;\n\t\tlabel = \"green:power\";\n\t\tdefault-state = \"on\";\n\t};\n};\n\n&nflash {\n\tstatus = \"okay\";\n\n\tnandcs@0 {\n\t\tcompatible = \"brcm,nandcs\";\n\t\t#size-cells = <1>;\n\t\t#address-cells = <1>;\n\t\treg = <0>;\n\t\tnand-ecc-step-size = <512>;\n\t\tnand-ecc-strength = <15>;\n\t\tnand-on-flash-bbt;\n\t\tbrcm,nand-oob-sector-size = <64>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"cferom\";\n\t\t\t\treg = <0x0000000 0x0020000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tcompatible = \"brcm,wfi-split\";\n\t\t\t\tlabel = \"wfi\";\n\t\t\t\treg = <0x0020000 0x7ac0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&uart0 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/bcm63xx/dts/bcm63168-sky-sr102.dts",
    "content": "#include \"bcm63268.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"SKY SR102\";\n\tcompatible = \"sky,sr102\", \"brcm,bcm63168\", \"brcm,bcm63268\";\n\n\taliases {\n\t\tled-boot = &led_power_white;\n\t\tled-failsafe = &led_power_white;\n\t\tled-running = &led_power_white;\n\t\tled-upgrade = &led_power_white;\n\t};\n\n\tchosen {\n\t\tbootargs = \"rootfstype=squashfs,jffs2 noinitrd console=ttyS0,115200\";\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tpoll-interval = <20>;\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&pinctrl 33 0>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tlan1_green {\n\t\t\tlabel = \"green:lan1\";\n\t\t\tgpios = <&pinctrl 1 1>;\n\t\t};\n\t\tpower_red {\n\t\t\tlabel = \"red:power\";\n\t\t\tgpios = <&pinctrl 2 1>;\n\t\t};\n\t\twifi_red {\n\t\t\tlabel = \"red:wifi\";\n\t\t\tgpios = <&pinctrl 3 1>;\n\t\t};\n\t\tinet_red {\n\t\t\tlabel = \"red:inet\";\n\t\t\tgpios = <&pinctrl 4 1>;\n\t\t};\n\t\tinet_white {\n\t\t\tlabel = \"white:inet\";\n\t\t\tgpios = <&pinctrl 5 0>;\n\t\t};\n\t\tled_power_white: power_white {\n\t\t\tlabel = \"white:power\";\n\t\t\tgpios = <&pinctrl 6 0>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t\twifi_white {\n\t\t\tlabel = \"white:wifi\";\n\t\t\tgpios = <&pinctrl 8 0>;\n\t\t};\n\t\tlan2_red {\n\t\t\tlabel = \"red:lan2\";\n\t\t\tgpios = <&pinctrl 9 1>;\n\t\t};\n\t\tlan3_red {\n\t\t\tlabel = \"red:lan3\";\n\t\t\tgpios = <&pinctrl 10 1>;\n\t\t};\n\t\tlan4_red {\n\t\t\tlabel = \"red:lan4\";\n\t\t\tgpios = <&pinctrl 11 1>;\n\t\t};\n\t\tlan1_red {\n\t\t\tlabel = \"red:lan1\";\n\t\t\tgpios = <&pinctrl 12 1>;\n\t\t};\n\t\tlan2_green {\n\t\t\tlabel = \"green:lan2\";\n\t\t\tgpios = <&pinctrl 13 0>;\n\t\t};\n\t\tlan3_green {\n\t\t\tlabel = \"green:lan3\";\n\t\t\tgpios = <&pinctrl 14 1>;\n\t\t};\n\t\tlan4_green {\n\t\t\tlabel = \"green:lan4\";\n\t\t\tgpios = <&pinctrl 15 1>;\n\t\t};\n\t\thd_white {\n\t\t\tlabel = \"white:hd\";\n\t\t\tgpios = <&pinctrl 18 0>;\n\t\t};\n\t};\n};\n\n&hsspi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\tspi-max-frequency = <16666667>;\n\t\tspi-tx-bus-width = <2>;\n\t\tspi-rx-bus-width = <2>;\n\t\treg = <0>;\n\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"brcm,bcm963xx-cfe-nor-partitions\";\n\t\t};\n\t};\n};\n\n&uart0 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/bcm63xx/dts/bcm63169-comtrend-vg-8050.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later\n\n#include \"bcm63268.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"Comtrend VG-8050\";\n\tcompatible = \"comtrend,vg-8050\", \"brcm,bcm63169\", \"brcm,bcm63268\";\n\n\taliases {\n\t\tled-boot = &led_power_green;\n\t\tled-failsafe = &led_power_green;\n\t\tled-running = &led_power_green;\n\t\tled-upgrade = &led_power_green;\n\t};\n\n\tchosen {\n\t\tbootargs = \"rootfstype=squashfs,ubifs noinitrd console=ttyS0,115200\";\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&pinctrl 33 1>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&pinctrl 34 1>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n};\n\n&leds {\n\tstatus = \"okay\";\n\tbrcm,serial-leds;\n\tbrcm,serial-dat-low;\n\tbrcm,serial-shift-inv;\n\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_serial_led>;\n\n\tled@2 {\n\t\treg = <2>;\n\t\tactive-low;\n\t\tlabel = \"red:internet\";\n\t};\n\n\tled@3 {\n\t\treg = <3>;\n\t\tactive-low;\n\t\tlabel = \"red:power\";\n\t};\n\n\tled_power_green: led@6 {\n\t\treg = <6>;\n\t\tactive-low;\n\t\tlabel = \"green:power\";\n\t\tdefault-state = \"on\";\n\t};\n\n\tled@7 {\n\t\treg = <7>;\n\t\tactive-low;\n\t\tlabel = \"green:wps\";\n\t};\n\n\tled@8 {\n\t\treg = <8>;\n\t\tactive-low;\n\t\tlabel = \"green:internet\";\n\t};\n\n\tled@10 {\n\t\treg = <10>;\n\t\tactive-low;\n\t\tlabel = \"green:voip\";\n\t};\n\n\tled@12 {\n\t\treg = <12>;\n\t\tactive-low;\n\t\tlabel = \"red:voip\";\n\t};\n\n\tled@14 {\n\t\treg = <14>;\n\t\tactive-low;\n\t\tlabel = \"red:wps\";\n\t};\n};\n\n&hsspi {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_hsspi_cs5>;\n\n\tswitch@5 {\n\t\tcompatible = \"brcm,bcm53125\";\n\t\treg = <5>;\n\t\tspi-max-frequency = <781000>;\n\t\tspi-cpha;\n\t\tspi-cpol;\n\n\t\tlede,alias = \"eth0\";\n\n\t\tports {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\n\t\t\tlan@0 {\n\t\t\t\treg = <0>;\n\t\t\t\tlabel = \"lan4\";\n\t\t\t};\n\n\t\t\tlan@1 {\n\t\t\t\treg = <1>;\n\t\t\t\tlabel = \"lan3\";\n\t\t\t};\n\n\t\t\tlan@2 {\n\t\t\t\treg = <2>;\n\t\t\t\tlabel = \"lan2\";\n\t\t\t};\n\n\t\t\tlan@3 {\n\t\t\t\treg = <3>;\n\t\t\t\tlabel = \"lan1\";\n\t\t\t};\n\n\t\t\twan@4 {\n\t\t\t\treg = <4>;\n\t\t\t\tlabel = \"wan\";\n\t\t\t};\n\n\t\t\tcpu@8 {\n\t\t\t\treg = <8>;\n\t\t\t\tlabel = \"cpu\";\n\n\t\t\t\tfixed-link {\n\t\t\t\t\tspeed = <1000>;\n\t\t\t\t\tfull-duplex;\n\t\t\t\t\tasym-pause;\n\t\t\t\t\tpause;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t};\n};\n\n&nflash {\n\tstatus = \"okay\";\n\n\tnandcs@0 {\n\t\tcompatible = \"brcm,nandcs\";\n\t\t#size-cells = <1>;\n\t\t#address-cells = <1>;\n\t\treg = <0>;\n\t\tnand-ecc-step-size = <512>;\n\t\tnand-ecc-strength = <15>;\n\t\tnand-on-flash-bbt;\n\t\tbrcm,nand-oob-sector-size = <64>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"cferom\";\n\t\t\t\treg = <0x0000000 0x0020000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tcompatible = \"brcm,wfi-split\";\n\t\t\t\tlabel = \"wfi\";\n\t\t\t\treg = <0x0020000 0x7ac0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&uart0 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/bcm63xx/dts/bcm6318-brcm-bcm96318ref-p300.dts",
    "content": "#include \"bcm6318.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"Broadcom BCM96318REF_P300 reference board\";\n\tcompatible = \"brcm,bcm96318ref-p300\", \"brcm,bcm6318\";\n\n\tchosen {\n\t\tbootargs = \"rootfstype=squashfs,jffs2 noinitrd console=ttyS0,115200\";\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tpoll-interval = <20>;\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&pinctrl 33 1>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&pinctrl 34 1>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tinet {\n\t\t\tlabel = \"green:inet\";\n\t\t\tgpios = <&pinctrl 8 1>;\n\t\t};\n\n\t\tinet_fail {\n\t\t\tlabel = \"red:inet-fail\";\n\t\t\tgpios = <&pinctrl 9 1>;\n\t\t};\n\n\t\tpost_failed {\n\t\t\tlabel = \"red:post-failed\";\n\t\t\tgpios = <&pinctrl 11 1>;\n\t\t};\n\n\t\tusb_pwron {\n\t\t\tlabel = \"usb-pwron\";\n\t\t\tgpios = <&pinctrl 13 1>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n};\n\n&hsspi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\tspi-max-frequency = <62500000>;\n\t\tspi-tx-bus-width = <2>;\n\t\tspi-rx-bus-width = <2>;\n\t\treg = <0>;\n\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"brcm,bcm963xx-cfe-nor-partitions\";\n\t\t};\n\t};\n};\n\n&pinctrl {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb_pwron>;\n};\n\n&uart0 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/bcm63xx/dts/bcm6318-brcm-bcm96318ref.dts",
    "content": "#include \"bcm6318.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"Broadcom BCM96318REF reference board\";\n\tcompatible = \"brcm,bcm96318ref\", \"brcm,bcm6318\";\n\n\tchosen {\n\t\tbootargs = \"rootfstype=squashfs,jffs2 noinitrd console=ttyS0,115200\";\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tpoll-interval = <20>;\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&pinctrl 33 1>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&pinctrl 34 1>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tinet {\n\t\t\tlabel = \"green:inet\";\n\t\t\tgpios = <&pinctrl 8 1>;\n\t\t};\n\n\t\tinet_fail {\n\t\t\tlabel = \"red:inet-fail\";\n\t\t\tgpios = <&pinctrl 9 1>;\n\t\t};\n\n\t\tpost_failed {\n\t\t\tlabel = \"red:post-failed\";\n\t\t\tgpios = <&pinctrl 11 1>;\n\t\t};\n\t};\n};\n\n&hsspi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\tspi-max-frequency = <62500000>;\n\t\tspi-tx-bus-width = <2>;\n\t\tspi-rx-bus-width = <2>;\n\t\treg = <0>;\n\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"brcm,bcm963xx-cfe-nor-partitions\";\n\t\t};\n\t};\n};\n\n&pinctrl {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb_pwron>;\n};\n\n&uart0 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/bcm63xx/dts/bcm6318-comtrend-ar-5315u.dts",
    "content": "#include \"bcm6318.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"Comtrend AR-5315u\";\n\tcompatible = \"comtrend,ar-5315u\", \"brcm,bcm6318\";\n\n\taliases {\n\t\tled-boot = &led_power_green;\n\t\tled-failsafe = &led_power_green;\n\t\tled-running = &led_power_green;\n\t\tled-upgrade = &led_power_green;\n\t};\n\n\tchosen {\n\t\tbootargs = \"rootfstype=squashfs,jffs2 noinitrd console=ttyS0,115200\";\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tpoll-interval = <20>;\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&pinctrl 3 1>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&pinctrl 33 1>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n};\n\n&hsspi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\tspi-max-frequency = <62500000>;\n\t\tspi-tx-bus-width = <2>;\n\t\tspi-rx-bus-width = <2>;\n\t\treg = <0>;\n\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tcfe@0 {\n\t\t\t\treg = <0x000000 0x010000>;\n\t\t\t\tlabel = \"cfe\";\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tlinux@10000 {\n\t\t\t\treg = <0x010000 0xfe0000>;\n\t\t\t\tlabel = \"linux\";\n\t\t\t\tcompatible = \"brcm,bcm963xx-imagetag\";\n\t\t\t};\n\n\t\t\tnvram@ff0000 {\n\t\t\t\treg = <0xff0000 0x010000>;\n\t\t\t\tlabel = \"nvram\";\n\t\t\t};\n\t\t};\n\t};\n};\n\n&leds {\n\tstatus = \"okay\";\n\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_leds\n\t\t     &pinctrl_ephy0_act_led &pinctrl_ephy1_act_led\n\t\t     &pinctrl_ephy2_act_led &pinctrl_ephy3_act_led>;\n\n\tled@0 {\n\t\treg = <0>;\n\t\tactive-low;\n\t\tlabel = \"green:wps\";\n\t};\n\n\tled_power_green: led@1 {\n\t\treg = <1>;\n\t\tactive-low;\n\t\tlabel = \"green:power\";\n\t\tdefault-state = \"on\";\n\t};\n\n\tled@2 {\n\t\treg = <2>;\n\t\tactive-low;\n\t\tlabel = \"green:usb\";\n\t};\n\n\tled@4 {\n\t\treg = <4>;\n\t\tbrcm,hardware-controlled;\n\t\tbrcm,link-signal-sources = <4>;\n\t\t/* EPHY0 Act */\n\t};\n\n\tled@5 {\n\t\treg = <5>;\n\t\tbrcm,hardware-controlled;\n\t\tbrcm,link-signal-sources = <5>;\n\t\t/* EPHY1 Act */\n\t};\n\n\tled@6 {\n\t\treg = <6>;\n\t\tbrcm,hardware-controlled;\n\t\tbrcm,link-signal-sources = <6>;\n\t\t/* EPHY2 Act */\n\t};\n\n\tled@7 {\n\t\treg = <7>;\n\t\tbrcm,hardware-controlled;\n\t\tbrcm,link-signal-sources = <7>;\n\t\t/* EPHY3 Act */\n\t};\n\n\tled@8 {\n\t\treg = <8>;\n\t\tactive-low;\n\t\tlabel = \"green:inet\";\n\t};\n\n\tled@9 {\n\t\treg = <9>;\n\t\tactive-low;\n\t\tlabel = \"red:inet\";\n\t};\n\n\tled@10 {\n\t\treg = <10>;\n\t\tactive-low;\n\t\tlabel = \"green:dsl\";\n\t};\n\n\tled@11 {\n\t\treg = <11>;\n\t\tactive-low;\n\t\tlabel = \"red:power\";\n\t};\n};\n\n&pinctrl {\n\tpinctrl_leds: leds {\n\t\tfunction = \"led\";\n\t\tpins = \"gpio0\", \"gpio1\",\n\t\t       \"gpio2\", \"gpio8\",\n\t\t       \"gpio9\", \"gpio10\",\n\t\t       \"gpio11\";\n\t};\n};\n\n&uart0 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/bcm63xx/dts/bcm6318-d-link-dsl-275xb-d1.dts",
    "content": "#include \"bcm6318.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"D-Link DSL-2750B/DSL-2751 rev D1\";\n\tcompatible = \"d-link,dsl-275xb-d1\", \"brcm,bcm6318\";\n\n\taliases {\n\t\tled-boot = &led_power_green;\n\t\tled-failsafe = &led_power_green;\n\t\tled-running = &led_power_green;\n\t\tled-upgrade = &led_power_green;\n\t};\n\n\tchosen {\n\t\tbootargs = \"rootfstype=squashfs,jffs2 noinitrd console=ttyS0,115200\";\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tpoll-interval = <20>;\n\n\t\twifi {\n\t\t\tlabel = \"wifi\";\n\t\t\tgpios = <&pinctrl 2 1>;\n\t\t\tlinux,code = <KEY_WLAN>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&pinctrl 33 1>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&pinctrl 34 1>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power_green: power_green {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&pinctrl 3 1>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\tinet_green {\n\t\t\tlabel = \"green:inet\";\n\t\t\tgpios = <&pinctrl 8 1>;\n\t\t};\n\n\t\tinet_red {\n\t\t\tlabel = \"red:inet-fail\";\n\t\t\tgpios = <&pinctrl 9 1>;\n\t\t};\n\n\t\tpower_red {\n\t\t\tlabel = \"red:post-failed\";\n\t\t\tgpios = <&pinctrl 11 1>;\n\t\t};\n\n\t\twps_blue {\n\t\t\tlabel = \"blue:wps\";\n\t\t\tgpios = <&pinctrl 16 1>;\n\t\t};\n\n\t\tdsl_green {\n\t\t\tlabel = \"green:dsl\";\n\t\t\tgpios = <&pinctrl 17 1>;\n\t\t};\n\n\t\tusb_green {\n\t\t\t/* not user controllable? */\n\t\t\tlabel = \"green:usb\";\n\t\t\tgpios = <&pinctrl 49 1>;\n\t\t};\n\t};\n};\n\n&hsspi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\tspi-max-frequency = <62500000>;\n\t\tspi-tx-bus-width = <2>;\n\t\tspi-rx-bus-width = <2>;\n\t\treg = <0>;\n\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tcfe@0 {\n\t\t\t\treg = <0x000000 0x010000>;\n\t\t\t\tlabel = \"cfe\";\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tlinux@10000 {\n\t\t\t\treg = <0x010000 0x7e0000>;\n\t\t\t\tlabel = \"linux\";\n\t\t\t\tcompatible = \"brcm,bcm963xx-imagetag\";\n\t\t\t};\n\n\t\t\tnvram@7f0000 {\n\t\t\t\treg = <0x7f0000 0x010000>;\n\t\t\t\tlabel = \"nvram\";\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pinctrl {\n\tpinctrl-names = \"default\";\n\n\tpinctrl-0 = <&pinctrl_ephy0_act_led &pinctrl_ephy1_act_led\n\t\t     &pinctrl_ephy2_act_led &pinctrl_ephy3_act_led>;\n};\n\n&uart0 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/bcm63xx/dts/bcm6318-sagem-fast-2704n.dts",
    "content": "#include \"bcm6318.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"Sagem F@st 2704N\";\n\tcompatible = \"sagem,fast-2704n\", \"brcm,bcm6318\";\n\n\taliases {\n\t\tled-boot = &led_power_red;\n\t\tled-failsafe = &led_power_red;\n\t\tled-running = &led_power_red;\n\t\tled-upgrade = &led_power_red;\n\t};\n\n\tchosen {\n\t\tbootargs = \"rootfstype=squashfs,jffs2 noinitrd console=ttyS0,115200\";\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tpoll-interval = <20>;\n\n\t\twlan {\n\t\t\tlabel = \"wlan\";\n\t\t\tgpios = <&pinctrl 1 0>;\n\t\t\tlinux,code = <KEY_WLAN>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&pinctrl 33 1>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&pinctrl 34 1>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twps_green {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&pinctrl 2 1>;\n\t\t};\n\t\tlan1_green {\n\t\t\tlabel = \"green:lan1\";\n\t\t\tgpios = <&pinctrl 4 1>;\n\t\t};\n\t\tlan2_green {\n\t\t\tlabel = \"green:lan2\";\n\t\t\tgpios = <&pinctrl 5 1>;\n\t\t};\n\t\tlan3_green {\n\t\t\tlabel = \"green:lan3\";\n\t\t\tgpios = <&pinctrl 6 1>;\n\t\t};\n\t\tlan4_green {\n\t\t\tlabel = \"green:lan4\";\n\t\t\tgpios = <&pinctrl 7 1>;\n\t\t};\n\t\tinet_green {\n\t\t\tlabel = \"green:inet\";\n\t\t\tgpios = <&pinctrl 8 1>;\n\t\t};\n\t\tinet_red {\n\t\t\tlabel = \"red:inet\";\n\t\t\tgpios = <&pinctrl 9 1>;\n\t\t};\n\t\tdsl_green {\n\t\t\tlabel = \"green:dsl\";\n\t\t\tgpios = <&pinctrl 10 1>;\n\t\t};\n\t\tled_power_red: power_red {\n\t\t\tlabel = \"red:power\";\n\t\t\tgpios = <&pinctrl 11 1>;\n\t\t};\n\t\tpower_green {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&pinctrl 47 1>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t\tusb_green {\n\t\t\tlabel = \"green:usb\";\n\t\t\tgpios = <&pinctrl 49 1>;\n\t\t};\n\t};\n};\n\n&hsspi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\tspi-max-frequency = <62500000>;\n\t\tspi-tx-bus-width = <2>;\n\t\tspi-rx-bus-width = <2>;\n\t\treg = <0>;\n\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tcfe@0 {\n\t\t\t\treg = <0x000000 0x010000>;\n\t\t\t\tlabel = \"cfe\";\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tlinux@10000 {\n\t\t\t\treg = <0x010000 0x7e0000>;\n\t\t\t\tlabel = \"linux\";\n\t\t\t\tcompatible = \"brcm,bcm963xx-imagetag\";\n\t\t\t};\n\n\t\t\tnvram@7f0000 {\n\t\t\t\treg = <0x7f0000 0x010000>;\n\t\t\t\tlabel = \"nvram\";\n\t\t\t};\n\t\t};\n\t};\n};\n\n&uart0 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/bcm63xx/dts/bcm6318.dtsi",
    "content": "/dts-v1/;\n\n/ {\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\tcompatible = \"brcm,bcm6318\";\n\n\taliases {\n\t\tpinctrl = &pinctrl;\n\t\tserial0 = &uart0;\n\t\tspi1 = &hsspi;\n\t};\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu@0 {\n\t\t\tcompatible = \"brcm,bmips3300\", \"mips,mips4Kc\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\treg = <0>;\n\t\t};\n\t};\n\n\tcpu_intc: interrupt-controller {\n\t\t#address-cells = <0>;\n\t\tcompatible = \"mti,cpu-interrupt-controller\";\n\n\t\tinterrupt-controller;\n\t\t#interrupt-cells = <1>;\n\t};\n\n\tmemory { device_type = \"memory\"; reg = <0 0>; };\n\n\tubus@10000000 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tranges;\n\t\tcompatible = \"simple-bus\";\n\t\tinterrupt-parent = <&periph_intc>;\n\n\t\text_intc: interrupt-controller@10000018 {\n\t\t\tcompatible = \"brcm,bcm6318-ext-intc\";\n\t\t\treg = <0x10000018 0x4>;\n\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <2>;\n\n\t\t\tinterrupts = <24>, <25>, <26>, <27>;\n\t\t};\n\n\t\tperiph_intc: interrupt-controller@10000020 {\n\t\t\tcompatible = \"brcm,bcm6345-l1-intc\";\n\t\t\treg = <0x10000020 0x20>;\n\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <1>;\n\n\t\t\tinterrupt-parent = <&cpu_intc>;\n\t\t\tinterrupts = <2>;\n\t\t};\n\n\t\tpinctrl: pin-controller@10000080 {\n\t\t\tcompatible = \"brcm,bcm6318-pinctrl\";\n\t\t\treg = <0x10000080 0x08>,\n\t\t\t      <0x10000088 0x08>,\n\t\t\t      <0x10000098 0x04>,\n\t\t\t      <0x1000009c 0x0c>,\n\t\t\t      <0x100000d4 0x18>;\n\t\t\treg-names = \"dirout\", \"dat\", \"mode\", \"mux\", \"pad\";\n\n\t\t\tgpio-controller;\n\t\t\t#gpio-cells = <2>;\n\n\t\t\tinterrupt-parent = <&ext_intc>;\n\t\t\tinterrupts = <0 0>, <1 0>;\n\t\t\tinterrupt-names = \"gpio33\", \"gpio34\";\n\n\t\t\tpinctrl_ephy0_spd_led: ephy0_spd_led {\n\t\t\t\tfunction = \"ephy0_spd_led\";\n\t\t\t\tpins = \"gpio0\";\n\t\t\t};\n\n\t\t\tpinctrl_ephy1_spd_led: ephy1_spd_led {\n\t\t\t\tfunction = \"ephy1_spd_led\";\n\t\t\t\tpins = \"gpio1\";\n\t\t\t};\n\n\t\t\tpinctrl_ephy2_spd_led: ephy2_spd_led {\n\t\t\t\tfunction = \"ephy2_spd_led\";\n\t\t\t\tpins = \"gpio2\";\n\t\t\t};\n\n\t\t\tpinctrl_ephy3_spd_led: ephy3_spd_led {\n\t\t\t\tfunction = \"ephy3_spd_led\";\n\t\t\t\tpins = \"gpio3\";\n\t\t\t};\n\n\t\t\tpinctrl_ephy0_act_led: ephy0_act_led {\n\t\t\t\tfunction = \"ephy0_act_led\";\n\t\t\t\tpins = \"gpio4\";\n\t\t\t};\n\n\t\t\tpinctrl_ephy1_act_led: ephy1_act_led {\n\t\t\t\tfunction = \"ephy1_act_led\";\n\t\t\t\tpins = \"gpio5\";\n\t\t\t};\n\n\t\t\tpinctrl_ephy2_act_led: ephy2_act_led {\n\t\t\t\tfunction = \"ephy2_act_led\";\n\t\t\t\tpins = \"gpio6\";\n\t\t\t};\n\n\t\t\tpinctrl_ephy3_act_led: ephy3_act_led {\n\t\t\t\tfunction = \"ephy3_act_led\";\n\t\t\t\tpins = \"gpio7\";\n\t\t\t};\n\n\t\t\tpinctrl_serial_led: serial_led {\n\t\t\t\tpinctrl_serial_led_data: serial_led_data {\n\t\t\t\t\tfunction = \"serial_led_data\";\n\t\t\t\t\tpins = \"gpio6\";\n\t\t\t\t};\n\n\t\t\t\tpinctrl_serial_led_clk: serial_led_clk {\n\t\t\t\t\tfunction = \"serial_led_clk\";\n\t\t\t\t\tpins = \"gpio7\";\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tpinctrl_inet_act_led: inet_act_led {\n\t\t\t\tfunction = \"inet_act_led\";\n\t\t\t\tpins = \"gpio8\";\n\t\t\t};\n\n\t\t\tpinctrl_inet_fail_led: inet_fail_led {\n\t\t\t\tfunction = \"inet_fail_led\";\n\t\t\t\tpins = \"gpio9\";\n\t\t\t};\n\n\t\t\tpinctrl_dsl_led: dsl_led {\n\t\t\t\tfunction = \"dsl_led\";\n\t\t\t\tpins = \"gpio10\";\n\t\t\t};\n\n\t\t\tpinctrl_post_fail_led: post_fail_led {\n\t\t\t\tfunction = \"post_fail_led\";\n\t\t\t\tpins = \"gpio11\";\n\t\t\t};\n\n\t\t\tpinctrl_wlan_wps_led: wlan_wps_led {\n\t\t\t\tfunction = \"wlan_wps_led\";\n\t\t\t\tpins = \"gpio12\";\n\t\t\t};\n\n\t\t\tpinctrl_usb_pwron: usb_pwron {\n\t\t\t\tfunction = \"usb_pwron\";\n\t\t\t\tpins = \"gpio13\";\n\t\t\t};\n\n\t\t\tpinctrl_usb_device_led: usb_device_led {\n\t\t\t\tfunction = \"usb_device_led\";\n\t\t\t\tpins = \"gpio13\";\n\t\t\t};\n\n\t\t\tpinctrl_usb_active: usb_active {\n\t\t\t\tfunction = \"usb_active\";\n\t\t\t\tpins = \"gpio40\";\n\t\t\t};\n\t\t};\n\n\t\tuart0: serial@10000100 {\n\t\t\tcompatible = \"brcm,bcm6345-uart\";\n\t\t\treg = <0x10000100 0x18>;\n\n\t\t\tinterrupt-parent = <&periph_intc>;\n\t\t\tinterrupts = <28>;\n\n\t\t\t/* clocks = <&periph_clk>; */\n\t\t\t/* clock-names = \"refclk\"; */\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tleds: led-controller@10000200 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tcompatible = \"brcm,bcm6328-leds\";\n\t\t\treg = <0x10000200 0x24>;\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\thsspi: spi@10003000 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tcompatible = \"brcm,bcm6328-hsspi\";\n\t\t\treg = <0x10003000 0x600>;\n\t\t\tinterrupts = <29>;\n\t\t\t/* clocks = <&clkctl 25>; */\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/bcm63xx/dts/bcm63268-brcm-bcm963268bu-p300.dts",
    "content": "#include \"bcm63268.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"Broadcom BCM963268BU_P300 reference board\";\n\tcompatible = \"brcm,bcm963268bu-p300\", \"brcm,bcm63268\";\n\n\tchosen {\n\t\tbootargs = \"rootfstype=squashfs,jffs2 noinitrd console=ttyS0,115200\";\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&pinctrl 32 0>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&pinctrl 33 0>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n};\n\n&hsspi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\tspi-max-frequency = <20000000>;\n\t\tspi-tx-bus-width = <2>;\n\t\tspi-rx-bus-width = <2>;\n\t\treg = <0>;\n\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"brcm,bcm963xx-cfe-nor-partitions\";\n\t\t};\n\t};\n};\n\n&uart0 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/bcm63xx/dts/bcm63268-inteno-vg50.dts",
    "content": "#include \"bcm63268.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"Inteno VG50\";\n\tcompatible = \"inteno,vg50\", \"brcm,bcm63268\";\n\n\tchosen {\n\t\tbootargs = \"rootfstype=squashfs,jffs2 noinitrd console=ttyS0,115200\";\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&pinctrl 32 0>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&pinctrl 34 0>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n};\n\n&hsspi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\tspi-max-frequency = <20000000>;\n\t\tspi-tx-bus-width = <2>;\n\t\tspi-rx-bus-width = <2>;\n\t\treg = <0>;\n\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"brcm,bcm963xx-cfe-nor-partitions\";\n\t\t};\n\t};\n};\n\n&uart0 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/bcm63xx/dts/bcm63268.dtsi",
    "content": "/dts-v1/;\n\n/ {\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\tcompatible = \"brcm,bcm63268\";\n\n\taliases {\n\t\tnflash = &nflash;\n\t\tpinctrl = &pinctrl;\n\t\tserial0 = &uart0;\n\t\tserial1 = &uart1;\n\t\tspi0 = &lsspi;\n\t\tspi1 = &hsspi;\n\t};\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu@0 {\n\t\t\tcompatible = \"brcm,bmips4350\", \"mips,mips4Kc\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\treg = <0>;\n\t\t};\n\n\t\tcpu@1 {\n\t\t\tcompatible = \"brcm,bmips4350\", \"mips,mips4Kc\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\treg = <1>;\n\t\t};\n\t};\n\n\tcpu_intc: interrupt-controller {\n\t\t#address-cells = <0>;\n\t\tcompatible = \"mti,cpu-interrupt-controller\";\n\n\t\tinterrupt-controller;\n\t\t#interrupt-cells = <1>;\n\t};\n\n\tmemory { device_type = \"memory\"; reg = <0 0>; };\n\n\tubus@10000000 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tranges;\n\t\tcompatible = \"simple-bus\";\n\t\tinterrupt-parent = <&periph_intc>;\n\n\t\text_intc: interrupt-controller@10000018 {\n\t\t\tcompatible = \"brcm,bcm6345-ext-intc\";\n\t\t\treg = <0x10000018 0x4>;\n\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <2>;\n\n\t\t\tinterrupts = <44>, <45>, <46>, <47>;\n\t\t};\n\n\t\tperiph_intc: interrupt-controller@10000020 {\n\t\t\tcompatible = \"brcm,bcm6345-l1-intc\";\n\t\t\treg = <0x10000020 0x20>,\n\t\t\t      <0x10000040 0x20>;\n\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <1>;\n\n\t\t\tinterrupt-parent = <&cpu_intc>;\n\t\t\tinterrupts = <2>, <3>;\n\t\t};\n\n\t\tpinctrl: pin-controller@100000c0 {\n\t\t\tcompatible = \"brcm,bcm63268-pinctrl\";\n\t\t\treg = <0x100000c0 0x8>,\n\t\t\t      <0x100000c8 0x8>,\n\t\t\t      <0x100000d0 0x4>,\n\t\t\t      <0x100000d8 0x4>,\n\t\t\t      <0x100000dc 0x4>,\n\t\t\t      <0x100000f8 0x4>;\n\t\t\treg-names = \"dirout\", \"dat\", \"led\", \"mode\",\n\t\t\t\t    \"ctrl\", \"basemode\";\n\n\t\t\tgpio-controller;\n\t\t\t#gpio-cells = <2>;\n\n\t\t\tinterrupt-parent = <&ext_intc>;\n\t\t\tinterrupts = <0 0>, <1 0>, <2 0>, <3 0>;\n\t\t\tinterrupt-names = \"gpio32\", \"gpio33\", \"gpio34\", \"gpio35\";\n\n\t\t\tpinctrl_serial_led: serial_led {\n\t\t\t\tpinctrl_serial_led_clk: serial_led_clk {\n\t\t\t\t\tfunction = \"serial_led_clk\";\n\t\t\t\t\tpins = \"gpio0\";\n\t\t\t\t};\n\n\t\t\t\tpinctrl_serial_led_data: serial_led_data {\n\t\t\t\t\tfunction = \"serial_led_data\";\n\t\t\t\t\tpins = \"gpio1\";\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tpinctrl_hsspi_cs4: hsspi_cs4 {\n\t\t\t\tfunction = \"hsspi_cs4\";\n\t\t\t\tpins = \"gpio16\";\n\t\t\t};\n\n\t\t\tpinctrl_hsspi_cs5: hsspi_cs5 {\n\t\t\t\tfunction = \"hsspi_cs5\";\n\t\t\t\tpins = \"gpio17\";\n\t\t\t};\n\n\t\t\tpinctrl_hsspi_cs6: hsspi_cs6 {\n\t\t\t\tfunction = \"hsspi_cs6\";\n\t\t\t\tpins = \"gpio8\";\n\t\t\t};\n\n\t\t\tpinctrl_hsspi_cs7: hsspi_cs7 {\n\t\t\t\tfunction = \"hsspi_cs7\";\n\t\t\t\tpins = \"gpio9\";\n\t\t\t};\n\n\t\t\tpinctrl_adsl_spi: adsl_spi {\n\t\t\t\tpinctrl_adsl_spi_miso: adsl_spi_miso {\n\t\t\t\t\tfunction = \"adsl_spi_miso\";\n\t\t\t\t\tpins = \"gpio18\";\n\t\t\t\t};\n\n\t\t\t\tpinctrl_adsl_spi_mosi: adsl_spi_mosi {\n\t\t\t\t\tfunction = \"adsl_spi_mosi\";\n\t\t\t\t\tpins = \"gpio19\";\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tpinctrl_vreq_clk: vreq_clk {\n\t\t\t\tfunction = \"vreq_clk\";\n\t\t\t\tpins = \"gpio22\";\n\t\t\t};\n\n\t\t\tpinctrl_pcie_clkreq_b: pcie_clkreq_b {\n\t\t\t\tfunction = \"pcie_clkreq_b\";\n\t\t\t\tpins = \"gpio23\";\n\t\t\t};\n\n\t\t\tpinctrl_robosw_led_clk: robosw_led_clk {\n\t\t\t\tfunction = \"robosw_led_clk\";\n\t\t\t\tpins = \"gpio30\";\n\t\t\t};\n\n\t\t\tpinctrl_robosw_led_data: robosw_led_data {\n\t\t\t\tfunction = \"robosw_led_data\";\n\t\t\t\tpins = \"gpio31\";\n\t\t\t};\n\n\t\t\tpinctrl_nand: nand {\n\t\t\t\tfunction = \"nand\";\n\t\t\t\tgroup = \"nand_grp\";\n\t\t\t};\n\n\t\t\tpinctrl_gpio35_alt: gpio35_alt {\n\t\t\t\tfunction = \"gpio35_alt\";\n\t\t\t\tpin = \"gpio35\";\n\t\t\t};\n\n\t\t\tpinctrl_dectpd: dectpd {\n\t\t\t\tfunction = \"dectpd\";\n\t\t\t\tgroup = \"dectpd_grp\";\n\t\t\t};\n\n\t\t\tpinctrl_vdsl_phy_override_0: vdsl_phy_override_0 {\n\t\t\t\tfunction = \"vdsl_phy_override_0\";\n\t\t\t\tgroup = \"vdsl_phy_override_0_grp\";\n\t\t\t};\n\n\t\t\tpinctrl_vdsl_phy_override_1: vdsl_phy_override_1 {\n\t\t\t\tfunction = \"vdsl_phy_override_1\";\n\t\t\t\tgroup = \"vdsl_phy_override_1_grp\";\n\t\t\t};\n\n\t\t\tpinctrl_vdsl_phy_override_2: vdsl_phy_override_2 {\n\t\t\t\tfunction = \"vdsl_phy_override_2\";\n\t\t\t\tgroup = \"vdsl_phy_override_2_grp\";\n\t\t\t};\n\n\t\t\tpinctrl_vdsl_phy_override_3: vdsl_phy_override_3 {\n\t\t\t\tfunction = \"vdsl_phy_override_3\";\n\t\t\t\tgroup = \"vdsl_phy_override_3_grp\";\n\t\t\t};\n\n\t\t\tpinctrl_dsl_gpio8: dsl_gpio8 {\n\t\t\t\tfunction = \"dsl_gpio8\";\n\t\t\t\tgroup = \"dsl_gpio8\";\n\t\t\t};\n\n\t\t\tpinctrl_dsl_gpio9: dsl_gpio9 {\n\t\t\t\tfunction = \"dsl_gpio9\";\n\t\t\t\tgroup = \"dsl_gpio9\";\n\t\t\t};\n\t\t};\n\n\t\tuart0: serial@10000180 {\n\t\t\tcompatible = \"brcm,bcm6345-uart\";\n\t\t\treg = <0x10000180 0x18>;\n\n\t\t\tinterrupt-parent = <&periph_intc>;\n\t\t\tinterrupts = <5>;\n\n\t\t\t/* clocks = <&periph_clk>; */\n\t\t\t/* clock-names = \"refclk\"; */\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tuart1: serial@100001a0 {\n\t\t\tcompatible = \"brcm,bcm6345-uart\";\n\t\t\treg = <0x100001a0 0x18>;\n\n\t\t\tinterrupt-parent = <&periph_intc>;\n\t\t\tinterrupts = <34>;\n\n\t\t\t/* clocks = <&periph_clk>; */\n\t\t\t/* clock-names = \"refclk\"; */\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tlsspi: spi@10000800 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tcompatible = \"brcm,bcm6358-spi\";\n\t\t\treg = <0x10000800 0x70c>;\n\t\t\tinterrupts = <80>;\n\t\t\t/* clocks = <&clkctl 15>; */\n\t\t};\n\n\t\thsspi: spi@10001000 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tcompatible = \"brcm,bcm6328-hsspi\";\n\t\t\treg = <0x10001000 0x600>;\n\t\t\tinterrupts = <6>;\n\t\t\t/* clocks = <&clkctl 16>; */\n\t\t};\n\n\t\tnflash: nand@10000200 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tcompatible = \"brcm,nand-bcm6368\",\n\t\t\t\t     \"brcm,brcmnand-v4.0\",\n\t\t\t\t     \"brcm,brcmnand\";\n\t\t\treg = <0x10000200 0x180>,\n\t\t\t      <0x10000600 0x200>,\n\t\t\t      <0x100000b0 0x10>;\n\t\t\treg-names = \"nand\",\n\t\t\t\t    \"nand-cache\",\n\t\t\t\t    \"nand-int-base\";\n\n\t\t\tinterrupt-parent = <&periph_intc>;\n\t\t\tinterrupts = <50>;\n\n\t\t\t/* clocks = <&clkctl 20>; */\n\n\t\t\tpinctrl-names = \"default\";\n\t\t\tpinctrl-0 = <&pinctrl_nand>;\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tleds: led-controller@10001900 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tcompatible = \"brcm,bcm6328-leds\";\n\t\t\treg = <0x10001900 0x24>;\n\t\t\tstatus = \"disabled\";\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/bcm63xx/dts/bcm63269-brcm-bcm963269bhr.dts",
    "content": "#include \"bcm63268.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"Broadcom BCM963269BHR reference board\";\n\tcompatible = \"brcm,bcm963269bhr\", \"brcm,bcm63269\", \"brcm,bcm63268\";\n\n\tchosen {\n\t\tbootargs = \"rootfstype=squashfs,jffs2 noinitrd console=ttyS0,115200\";\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&pinctrl 32 0>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tusb1 {\n\t\t\tlabel = \"green:usb1\";\n\t\t\tgpios = <&pinctrl 9 1>;\n\t\t};\n\n\t\tusb2 {\n\t\t\tlabel = \"green:usb2\";\n\t\t\tgpios = <&pinctrl 10 1>;\n\t\t};\n\t};\n};\n\n&hsspi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\tspi-max-frequency = <20000000>;\n\t\tspi-tx-bus-width = <2>;\n\t\tspi-rx-bus-width = <2>;\n\t\treg = <0>;\n\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"brcm,bcm963xx-cfe-nor-partitions\";\n\t\t};\n\t};\n};\n\n&uart0 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/bcm63xx/dts/bcm6328-adb-a4001n.dts",
    "content": "#include \"bcm6328.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"ADB P.DG A4001N\";\n\tcompatible = \"adb,a4001n\", \"brcm,bcm6328\";\n\n\taliases {\n\t\tled-boot = &led_power_green;\n\t\tled-failsafe = &led_power_green;\n\t\tled-running = &led_power_green;\n\t\tled-upgrade = &led_power_green;\n\t};\n\n\tchosen {\n\t\tbootargs = \"rootfstype=squashfs,jffs2 noinitrd console=ttyS0,115200\";\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&pinctrl 23 1>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&pinctrl 24 1>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tinet_red {\n\t\t\tlabel = \"red:inet\";\n\t\t\tgpios = <&pinctrl 1 0>;\n\t\t};\n\t\tpower_red {\n\t\t\tlabel = \"red:power\";\n\t\t\tgpios = <&pinctrl 4 0>;\n\t\t};\n\t\tled_power_green: power_green {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&pinctrl 8 0>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t\tusb_green {\n\t\t\tlabel = \"green:usb\";\n\t\t\tgpios = <&pinctrl 10 1>;\n\t\t};\n\t\tdsl_green {\n\t\t\tlabel = \"green:dsl\";\n\t\t\tgpios = <&pinctrl 11 1>;\n\t\t};\n\t};\n};\n\n&hsspi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\tspi-max-frequency = <16666667>;\n\t\tspi-tx-bus-width = <2>;\n\t\tspi-rx-bus-width = <2>;\n\t\treg = <0>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tcfe@0 {\n\t\t\t\treg = <0x000000 0x010000>;\n\t\t\t\tlabel = \"cfe\";\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tlinux@10000 {\n\t\t\t\treg = <0x010000 0x7e0000>;\n\t\t\t\tlabel = \"linux\";\n\t\t\t\tcompatible = \"brcm,bcm963xx-imagetag\";\n\t\t\t};\n\n\t\t\tnvram@7f0000 {\n\t\t\t\treg = <0x7f0000 0x010000>;\n\t\t\t\tlabel = \"nvram\";\n\t\t\t};\n\t\t};\n\t};\n};\n\n&uart0 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/bcm63xx/dts/bcm6328-adb-a4001n1.dts",
    "content": "#include \"bcm6328.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"ADB P.DG A4001N1\";\n\tcompatible = \"adb,a4001n1\", \"brcm,bcm6328\";\n\n\taliases {\n\t\tled-boot = &led_power_green;\n\t\tled-failsafe = &led_power_green;\n\t\tled-running = &led_power_green;\n\t\tled-upgrade = &led_power_green;\n\t};\n\n\tchosen {\n\t\tbootargs = \"rootfstype=squashfs,jffs2 noinitrd console=ttyS0,115200\";\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&pinctrl 23 1>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wlan\";\n\t\t\tgpios = <&pinctrl 24 1>;\n\t\t\tlinux,code = <KEY_WLAN>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tinet_red {\n\t\t\tlabel = \"red:inet\";\n\t\t\tgpios = <&pinctrl 2 1>;\n\t\t};\n\t\tppp_green {\n\t\t\tlabel = \"green:ppp\";\n\t\t\tgpios = <&pinctrl 3 1>;\n\t\t};\n\t\tled_power_green: power_green {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&pinctrl 4 1>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t\tppp_red {\n\t\t\tlabel = \"red:ppp\";\n\t\t\tgpios = <&pinctrl 5 1>;\n\t\t};\n\t\tusb_green {\n\t\t\tlabel = \"green:3g\";\n\t\t\tgpios = <&pinctrl 6 1>;\n\t\t};\n\t\tusb_red {\n\t\t\tlabel = \"red:3g\";\n\t\t\tgpios = <&pinctrl 7 1>;\n\t\t};\n\t\tpower_red {\n\t\t\tlabel = \"red:power\";\n\t\t\tgpios = <&pinctrl 8 1>;\n\t\t};\n\t\twlan_green {\n\t\t\tlabel = \"green:wlan\";\n\t\t\tgpios = <&pinctrl 9 1>;\n\t\t};\n\t\twlan_red {\n\t\t\tlabel = \"red:wlan\";\n\t\t\tgpios = <&pinctrl 10 1>;\n\t\t};\n\t\tinet_green {\n\t\t\tlabel = \"green:inet\";\n\t\t\tgpios = <&pinctrl 11 1>;\n\t\t};\n\t\teth_red {\n\t\t\tlabel = \"red:eth\";\n\t\t\tgpios = <&pinctrl 20 1>;\n\t\t};\n\t\teth_green {\n\t\t\tlabel = \"green:eth\";\n\t\t\tgpios = <&pinctrl 31 1>;\n\t\t};\n\t};\n};\n\n&hsspi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\tspi-max-frequency = <16666667>;\n\t\tspi-tx-bus-width = <2>;\n\t\tspi-rx-bus-width = <2>;\n\t\treg = <0>;\n\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tcfe@0 {\n\t\t\t\treg = <0x000000 0x010000>;\n\t\t\t\tlabel = \"cfe\";\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tlinux@10000 {\n\t\t\t\treg = <0x010000 0xfe0000>;\n\t\t\t\tlabel = \"linux\";\n\t\t\t\tcompatible = \"brcm,bcm963xx-imagetag\";\n\t\t\t};\n\n\t\t\tnvram@ff0000 {\n\t\t\t\treg = <0xff0000 0x010000>;\n\t\t\t\tlabel = \"nvram\";\n\t\t\t};\n\t\t};\n\t};\n};\n\n&uart0 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/bcm63xx/dts/bcm6328-adb-pdg-a4001n-a-000-1a1-ax.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"bcm6328.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"ADB P.DG A4001N A-000-1A1-AX\";\n\tcompatible = \"adb,pdg-a4001n-a-000-1a1-ax\", \"brcm,bcm6328\";\n\n\taliases {\n\t\tled-boot = &led_power_green;\n\t\tled-failsafe = &led_power_green;\n\t\tled-running = &led_power_green;\n\t\tled-upgrade = &led_power_green;\n\t};\n\n\tchosen {\n\t\tbootargs = \"rootfstype=squashfs,jffs2 noinitrd console=ttyS0,115200\";\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&pinctrl 23 1>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wifi-led\";\n\t\t\tgpios = <&pinctrl 24 1>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n};\n\n&leds {\n\tstatus = \"okay\";\n\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_leds>;\n\n\tled@2 {\n\t\treg = <2>;\n\t\tactive-low;\n\t\tlabel = \"red:internet\";\n\t};\n\n\tled@3 {\n\t\treg = <3>;\n\t\tactive-low;\n\t\tlabel = \"green:adsl\";\n\t};\n\n\tled@5 {\n\t\treg = <5>;\n\t\tactive-low;\n\t\tlabel = \"red:adsl\";\n\t};\n\n\tled@6 {\n\t\treg = <6>;\n\t\tactive-low;\n\t\tlabel = \"green:service\";\n\t};\n\n\tled@7 {\n\t\treg = <7>;\n\t\tactive-low;\n\t\tlabel = \"red:service\";\n\t};\n\n\tled@8 {\n\t\treg = <8>;\n\t\tactive-low;\n\t\tlabel = \"red:power\";\n\t};\n\n\tled@9 {\n\t\treg = <9>;\n\t\tactive-low;\n\t\tlabel = \"green:wifi\";\n\t};\n\n\tled@10 {\n\t\treg = <10>;\n\t\tactive-low;\n\t\tlabel = \"red:wifi\";\n\t};\n\n\tled@11 {\n\t\treg = <11>;\n\t\tactive-low;\n\t\tlabel = \"green:internet\";\n\t};\n\n\tled_power_green: led@12 {\n\t\treg = <12>;\n\t\tactive-low;\n\t\tlabel = \"green:power\";\n\t\tdefault-state = \"on\";\n\t};\n};\n\n&hsspi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\tspi-max-frequency = <16666667>;\n\t\tspi-tx-bus-width = <2>;\n\t\tspi-rx-bus-width = <2>;\n\t\treg = <0>;\n\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\treg = <0x000000 0x010000>;\n\t\t\t\tlabel = \"cfe\";\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@10000 {\n\t\t\t\treg = <0x010000 0xff0000>;\n\t\t\t\tlabel = \"linux\";\n\t\t\t\tcompatible = \"brcm,bcm963xx-imagetag\";\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pinctrl {\n\tpinctrl_leds: leds {\n\t\tfunction = \"led\";\n\t\tpins = \"gpio2\", \"gpio3\",\n\t\t       \"gpio5\", \"gpio6\",\n\t\t       \"gpio7\", \"gpio8\",\n\t\t       \"gpio9\", \"gpio10\",\n\t\t       \"gpio11\", \"gpio12\";\n\t};\n};\n\n&uart0 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/bcm63xx/dts/bcm6328-adb-pdg-a4101n-a-000-1a1-ae.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"bcm6328.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"ADB P.DG A4101N A-000-1A1-AE\";\n\tcompatible = \"adb,pdg-a4101n-a-000-1a1-ae\", \"brcm,bcm6328\";\n\n\taliases {\n\t\tled-boot = &led_dsl_green;\n\t\tled-failsafe = &led_dsl_green;\n\t\tled-upgrade = &led_dsl_green;\n\t};\n\n\tchosen {\n\t\tbootargs = \"rootfstype=squashfs,jffs2 noinitrd console=ttyS0,115200\";\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tpoll-interval = <20>;\n\n\t\twifi {\n\t\t\tlabel = \"wifi\";\n\t\t\tgpios = <&pinctrl 12 1>;\n\t\t\tlinux,code = <KEY_WLAN>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&pinctrl 23 1>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&pinctrl 24 1>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled@31 {\n\t\t\tlabel = \"green:tel\";\n\t\t\tgpios = <&pinctrl 31 1>;\n\t\t};\n\t};\n};\n\n&leds {\n\tstatus = \"okay\";\n\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_leds>;\n\n\tled_dsl_green: led@3 {\n\t\treg = <3>;\n\t\tactive-low;\n\t\tlabel = \"green:dsl\";\n\t};\n\n\tled@9 {\n\t\treg = <9>;\n\t\tactive-low;\n\t\tlabel = \"green:wps\";\n\t};\n\n\tled@10 {\n\t\treg = <10>;\n\t\tactive-low;\n\t\tlabel = \"green:usb\";\n\t};\n\n\tled@11 {\n\t\treg = <11>;\n\t\tactive-low;\n\t\tlabel = \"green:internet\";\n\t};\n};\n\n&hsspi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\tspi-max-frequency = <16666667>;\n\t\tspi-tx-bus-width = <2>;\n\t\tspi-rx-bus-width = <2>;\n\t\treg = <0>;\n\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\treg = <0x000000 0x010000>;\n\t\t\t\tlabel = \"cfe\";\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@10000 {\n\t\t\t\treg = <0x010000 0xff0000>;\n\t\t\t\tlabel = \"linux\";\n\t\t\t\tcompatible = \"brcm,bcm963xx-imagetag\";\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pinctrl {\n\tpinctrl_leds: leds {\n\t\tfunction = \"led\";\n\t\tpins = \"gpio3\", \"gpio9\", \"gpio10\",\n\t\t       \"gpio11\";\n\t};\n\n\tgreen_internet_switch {\n\t\tgpio-hog;\n\t\tgpios = <2 1>;\n\t\toutput-low;\n\t\tline-name = \"green:internet-switch\";\n\t};\n};\n\n&uart0 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/bcm63xx/dts/bcm6328-brcm-bcm963281tan.dts",
    "content": "#include \"bcm6328.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"Broadcom bcm963281TAN reference board\";\n\tcompatible = \"brcm,bcm963281tan\", \"brcm,bcm6328\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tchosen {\n\t\tbootargs = \"rootfstype=squashfs,jffs2 noinitrd console=ttyS0,115200\";\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tinet {\n\t\t\tlabel = \"internet\";\n\t\t\tgpios = <&pinctrl 1 1>;\n\t\t};\n\t\tled_power: power {\n\t\t\tlabel = \"power\";\n\t\t\tgpios = <&pinctrl 4 1>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t\tinet_fail {\n\t\t\tlabel = \"internet-fail\";\n\t\t\tgpios = <&pinctrl 7 1>;\n\t\t};\n\t\tpower_fail {\n\t\t\tlabel = \"power-fail\";\n\t\t\tgpios = <&pinctrl 8 1>;\n\t\t};\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&pinctrl 9 1>;\n\t\t};\n\t\tdsl {\n\t\t\tlabel = \"dsl\";\n\t\t\tgpios = <&pinctrl 11 1>;\n\t\t};\n\t};\n};\n\n&hsspi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\tspi-max-frequency = <16666667>;\n\t\tspi-tx-bus-width = <2>;\n\t\tspi-rx-bus-width = <2>;\n\t\treg = <0>;\n\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"brcm,bcm963xx-cfe-nor-partitions\";\n\t\t};\n\t};\n};\n\n&uart0 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/bcm63xx/dts/bcm6328-brcm-bcm96328avng.dts",
    "content": "#include \"bcm6328.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"Broadcom BCM96328avng reference board\";\n\tcompatible = \"brcm,bcm96328avng\", \"brcm,bcm6328\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tchosen {\n\t\tbootargs = \"rootfstype=squashfs,jffs2 noinitrd console=ttyS0,115200\";\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tinet_fail {\n\t\t\tlabel = \"internet-fail\";\n\t\t\tgpios = <&pinctrl 2 1>;\n\t\t};\n\t\tdsl {\n\t\t\tlabel = \"dsl\";\n\t\t\tgpios = <&pinctrl 3 1>;\n\t\t};\n\t\tled_power: power {\n\t\t\tlabel = \"power\";\n\t\t\tgpios = <&pinctrl 4 1>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t\tpower_fail {\n\t\t\tlabel = \"power-fail\";\n\t\t\tgpios = <&pinctrl 8 1>;\n\t\t};\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&pinctrl 9 1>;\n\t\t};\n\t\tinet {\n\t\t\tlabel = \"internet\";\n\t\t\tgpios = <&pinctrl 11 1>;\n\t\t};\n\t};\n};\n\n&hsspi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\tspi-max-frequency = <16666667>;\n\t\tspi-tx-bus-width = <2>;\n\t\tspi-rx-bus-width = <2>;\n\t\treg = <0>;\n\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"brcm,bcm963xx-cfe-nor-partitions\";\n\t\t};\n\t};\n};\n\n&pinctrl {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_usb_port1_device>;\n};\n\n&uart0 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/bcm63xx/dts/bcm6328-comtrend-ar-5381u.dts",
    "content": "#include \"bcm6328.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"Comtrend AR-5381u\";\n\tcompatible = \"comtrend,ar-5381u\", \"brcm,bcm6328\";\n\n\taliases {\n\t\tled-boot = &led_power_green;\n\t\tled-failsafe = &led_alarm_red;\n\t\tled-running = &led_power_green;\n\t\tled-upgrade = &led_power_green;\n\t};\n\n\tchosen {\n\t\tbootargs = \"rootfstype=squashfs,jffs2 noinitrd console=ttyS0,115200\";\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&pinctrl 23 1>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n};\n\n&hsspi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\tspi-max-frequency = <16666667>;\n\t\tspi-tx-bus-width = <2>;\n\t\tspi-rx-bus-width = <2>;\n\t\treg = <0>;\n\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tcfe@0 {\n\t\t\t\treg = <0x000000 0x010000>;\n\t\t\t\tlabel = \"cfe\";\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tlinux@10000 {\n\t\t\t\treg = <0x010000 0xfe0000>;\n\t\t\t\tlabel = \"linux\";\n\t\t\t\tcompatible = \"brcm,bcm963xx-imagetag\";\n\t\t\t};\n\n\t\t\tnvram@ff0000 {\n\t\t\t\treg = <0xff0000 0x010000>;\n\t\t\t\tlabel = \"nvram\";\n\t\t\t};\n\t\t};\n\t};\n};\n\n&leds {\n\tstatus = \"okay\";\n\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_leds>;\n\n\tled_alarm_red: led@2 {\n\t\treg = <2>;\n\t\tactive-low;\n\t\tlabel = \"red:alarm\";\n\t};\n\n\tled@3 {\n\t\treg = <3>;\n\t\tactive-low;\n\t\tlabel = \"green:inet\";\n\t};\n\n\tled_power_green: led@4 {\n\t\treg = <4>;\n\t\tactive-low;\n\t\tlabel = \"green:power\";\n\t\tdefault-state = \"on\";\n\t};\n};\n\n&pinctrl {\n\tpinctrl_leds: leds {\n\t\tfunction = \"led\";\n\t\tpins = \"gpio2\", \"gpio3\", \"gpio4\";\n\t};\n};\n\n&uart0 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/bcm63xx/dts/bcm6328-comtrend-ar-5387un.dts",
    "content": "#include \"bcm6328.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"Comtrend AR-5387un\";\n\tcompatible = \"comtrend,ar-5387un\", \"brcm,bcm6328\";\n\n\taliases {\n\t\tled-boot = &led_power_green;\n\t\tled-failsafe = &led_power_green;\n\t\tled-running = &led_power_green;\n\t\tled-upgrade = &led_power_green;\n\t};\n\n\tchosen {\n\t\tbootargs = \"rootfstype=squashfs,jffs2 noinitrd console=ttyS0,115200\";\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&pinctrl 23 1>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n};\n\n&hsspi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\tspi-max-frequency = <16666667>;\n\t\tspi-tx-bus-width = <2>;\n\t\tspi-rx-bus-width = <2>;\n\t\treg = <0>;\n\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tcfe@0 {\n\t\t\t\treg = <0x000000 0x010000>;\n\t\t\t\tlabel = \"cfe\";\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tlinux@10000 {\n\t\t\t\treg = <0x010000 0xfe0000>;\n\t\t\t\tlabel = \"linux\";\n\t\t\t\tcompatible = \"brcm,bcm963xx-imagetag\";\n\t\t\t};\n\n\t\t\tnvram@ff0000 {\n\t\t\t\treg = <0xff0000 0x010000>;\n\t\t\t\tlabel = \"nvram\";\n\t\t\t};\n\t\t};\n\t};\n};\n\n&leds {\n\tstatus = \"okay\";\n\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_leds>;\n\n\tled@1 {\n\t\treg = <1>;\n\t\tlabel = \"red:inet\";\n\t};\n\n\tled@4 {\n\t\treg = <4>;\n\t\tlabel = \"red:power\";\n\t};\n\n\tled@7 {\n\t\treg = <7>;\n\t\tlabel = \"green:inet\";\n\t};\n\n\tled_power_green: led@8 {\n\t\treg = <8>;\n\t\tlabel = \"green:power\";\n\t\tdefault-state = \"on\";\n\t};\n\n\tled@11 {\n\t\treg = <11>;\n\t\tactive-low;\n\t\tlabel = \"green:dsl\";\n\t};\n};\n\n&pinctrl {\n\tpinctrl_leds: leds {\n\t\tfunction = \"led\";\n\t\tpins = \"gpio1\", \"gpio4\", \"gpio7\",\n\t\t       \"gpio8\", \"gpio11\";\n\t};\n};\n\n&uart0 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/bcm63xx/dts/bcm6328-d-link-dsl-274xb-f1.dts",
    "content": "#include \"bcm6328.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"D-Link DSL-2740B/DSL-2741B rev F1\";\n\tcompatible = \"d-link,dsl-274xb-f1\", \"brcm,bcm6328\";\n\n\taliases {\n\t\tled-boot = &led_power_green;\n\t\tled-failsafe = &led_power_green;\n\t\tled-running = &led_power_green;\n\t\tled-upgrade = &led_power_green;\n\t};\n\n\tchosen {\n\t\tbootargs = \"rootfstype=squashfs,jffs2 noinitrd console=ttyS0,115200\";\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tpoll-interval = <20>;\n\n\t\twifi {\n\t\t\tlabel = \"wifi\";\n\t\t\tgpios = <&pinctrl 10 1>;\n\t\t\tlinux,code = <KEY_WLAN>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&pinctrl 23 1>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&pinctrl 24 1>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tinet_red {\n\t\t\tlabel = \"red:internet\";\n\t\t\tgpios = <&pinctrl 2 1>;\n\t\t};\n\t\tdsl_green {\n\t\t\tlabel = \"green:dsl\";\n\t\t\tgpios = <&pinctrl 3 1>;\n\t\t};\n\t\tled_power_green: power_green {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&pinctrl 4 1>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t\tpower_red {\n\t\t\tlabel = \"red:power\";\n\t\t\tgpios = <&pinctrl 8 1>;\n\t\t};\n\t\twps_blue {\n\t\t\tlabel = \"blue:wps\";\n\t\t\tgpios = <&pinctrl 9 1>;\n\t\t};\n\t\tinet_green {\n\t\t\tlabel = \"green:internet\";\n\t\t\tgpios = <&pinctrl 11 1>;\n\t\t};\n\t};\n};\n\n&hsspi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\tspi-max-frequency = <16666667>;\n\t\tspi-tx-bus-width = <2>;\n\t\tspi-rx-bus-width = <2>;\n\t\treg = <0>;\n\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tcfe@0 {\n\t\t\t\treg = <0x000000 0x010000>;\n\t\t\t\tlabel = \"cfe\";\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tlinux@10000 {\n\t\t\t\treg = <0x010000 0x7c0000>;\n\t\t\t\tlabel = \"linux\";\n\t\t\t\tcompatible = \"brcm,bcm963xx-imagetag\";\n\t\t\t};\n\n\t\t\tcal_data@7d0000 {\n\t\t\t\treg = <0x7d0000 0x010000>;\n\t\t\t\tlabel = \"cal_data\";\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tnvram@7e0000 {\n\t\t\t\treg = <0x7e0000 0x020000>;\n\t\t\t\tlabel = \"nvram\";\n\t\t\t};\n\t\t};\n\t};\n};\n\n&uart0 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/bcm63xx/dts/bcm6328-d-link-dsl-2750u-c1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"bcm6328.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"D-Link DSL-2750U rev C1\";\n\tcompatible = \"d-link,dsl-2750u-c1\", \"brcm,bcm6328\";\n\n\taliases {\n\t\tled-boot = &led_power_green;\n\t\tled-failsafe = &led_power_green;\n\t\tled-running = &led_power_green;\n\t\tled-upgrade = &led_power_green;\n\t};\n\n\tchosen {\n\t\tbootargs = \"rootfstype=squashfs,jffs2 noinitrd console=ttyS0,115200\";\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <20>;\n\n\t\twifi {\n\t\t\tlabel = \"wifi\";\n\t\t\tgpios = <&pinctrl 12 1>;\n\t\t\tlinux,code = <KEY_WLAN>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&pinctrl 23 1>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&pinctrl 24 1>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n};\n\n&hsspi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\tspi-max-frequency = <16666667>;\n\t\tspi-tx-bus-width = <2>;\n\t\tspi-rx-bus-width = <2>;\n\t\treg = <0>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tcfe@0 {\n\t\t\t\treg = <0x000000 0x010000>;\n\t\t\t\tlabel = \"cfe\";\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tlinux@10000 {\n\t\t\t\treg = <0x010000 0x7e0000>;\n\t\t\t\tlabel = \"linux\";\n\t\t\t\tcompatible = \"brcm,bcm963xx-imagetag\";\n\t\t\t};\n\n\t\t\tnvram@7f0000 {\n\t\t\t\treg = <0x7f0000 0x010000>;\n\t\t\t\tlabel = \"nvram\";\n\t\t\t};\n\t\t};\n\t};\n};\n\n&leds {\n\tstatus = \"okay\";\n\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_leds>;\n\n\tled@1 {\n\t\treg = <1>;\n\t\tactive-low;\n\t\tlabel = \"green:inet\";\n\t};\n\n\tled_power_green: led@4 {\n\t\treg = <4>;\n\t\tactive-low;\n\t\tlabel = \"green:power\";\n\t\tdefault-state = \"on\";\n\t};\n\n\tled@7 {\n\t\treg = <7>;\n\t\tactive-low;\n\t\tlabel = \"red:inet\";\n\t};\n\n\tled@8 {\n\t\treg = <8>;\n\t\tactive-low;\n\t\tlabel = \"red:power\";\n\t};\n\n\tled@9 {\n\t\treg = <9>;\n\t\tactive-low;\n\t\tlabel = \"green:wps\";\n\t};\n\n\tled@10 {\n\t\treg = <10>;\n\t\tactive-low;\n\t\tlabel = \"green:usb\";\n\t};\n\n\tled@11 {\n\t\treg = <11>;\n\t\tactive-low;\n\t\tlabel = \"green:dsl\";\n\t};\n};\n\n&pinctrl {\n\tpinctrl_leds: leds {\n\t\tfunction = \"led\";\n\t\tpins = \"gpio1\", \"gpio4\", \"gpio7\",\n\t\t       \"gpio8\", \"gpio9\", \"gpio10\",\n\t\t       \"gpio11\";\n\t};\n};\n\n&uart0 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/bcm63xx/dts/bcm6328-innacomm-w3400v6.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later\n\n#include \"bcm6328.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"Innacomm W3400V6\";\n\tcompatible = \"innacomm,w3400v6\", \"brcm,bcm6328\";\n\n\taliases {\n\t\tled-boot = &led_power_green;\n\t\tled-failsafe = &led_power_red;\n\t\tled-running = &led_power_green;\n\t\tled-upgrade = &led_power_green;\n\t};\n\n\tchosen {\n\t\tbootargs = \"rootfstype=squashfs,jffs2 noinitrd console=ttyS0,115200\";\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tpoll-interval = <20>;\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&pinctrl 15 1>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&pinctrl 23 1>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n};\n\n&hsspi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\tspi-max-frequency = <16666667>;\n\t\tspi-tx-bus-width = <2>;\n\t\tspi-rx-bus-width = <2>;\n\t\treg = <0>;\n\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"brcm,bcm963xx-cfe-nor-partitions\";\n\t\t};\n\t};\n};\n\n&leds {\n\tstatus = \"okay\";\n\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_leds>;\n\n\tled@1 {\n\t\treg = <1>;\n\t\tactive-low;\n\t\tlabel = \"green:inet\";\n\t};\n\n\tled@2 {\n\t\treg = <2>;\n\t\tactive-low;\n\t\tlabel = \"red:inet\";\n\t};\n\n\tled@3 {\n\t\treg = <3>;\n\t\tactive-low;\n\t\tlabel = \"green:dsl\";\n\t};\n\n\tled_power_green: led@4 {\n\t\treg = <4>;\n\t\tactive-low;\n\t\tlabel = \"green:power\";\n\t\tdefault-state = \"on\";\n\t};\n\n\tled_power_red: led@5 {\n\t\treg = <5>;\n\t\tactive-low;\n\t\tlabel = \"red:power\";\n\t};\n\n\tled@11 {\n\t\treg = <11>;\n\t\tactive-low;\n\t\tlabel = \"green:wps\";\n\t};\n};\n\n&pinctrl {\n\tpinctrl_leds: leds {\n\t\tfunction = \"led\";\n\t\tpins = \"gpio1\", \"gpio2\", \"gpio3\",\n\t\t       \"gpio4\", \"gpio5\", \"gpio11\";\n\t};\n};\n\n&uart0 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/bcm63xx/dts/bcm6328-nucom-r5010un-v2.dts",
    "content": "#include \"bcm6328.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"NuCom R5010UN v2\";\n\tcompatible = \"nucom,r5010un-v2\", \"brcm,bcm6328\";\n\n\taliases {\n\t\tled-boot = &led_power_green;\n\t\tled-failsafe = &led_power_green;\n\t\tled-running = &led_power_green;\n\t\tled-upgrade = &led_power_green;\n\t};\n\n\tchosen {\n\t\tbootargs = \"rootfstype=squashfs,jffs2 noinitrd console=ttyS0,115200\";\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&pinctrl 23 1>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&pinctrl 24 1>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tinet_green {\n\t\t\tlabel = \"green:inet\";\n\t\t\tgpios = <&pinctrl 1 1>;\n\t\t};\n\t\tinet_fail_red {\n\t\t\tlabel = \"red:inet-fail\";\n\t\t\tgpios = <&pinctrl 2 1>;\n\t\t};\n\t\tdsl_red {\n\t\t\tlabel = \"green:dsl\";\n\t\t\tgpios = <&pinctrl 3 1>;\n\t\t};\n\t\tled_power_green: power_green {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&pinctrl 4 1>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t\tpower_fail_red {\n\t\t\tlabel = \"red:power-fail\";\n\t\t\tgpios = <&pinctrl 5 1>;\n\t\t};\n\t\twps_green {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&pinctrl 10 1>;\n\t\t};\n\t\tusb_green {\n\t\t\tlabel = \"green:usb\";\n\t\t\tgpios = <&pinctrl 11 1>;\n\t\t};\n\t};\n};\n\n&hsspi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\tspi-max-frequency = <16666667>;\n\t\tspi-tx-bus-width = <2>;\n\t\tspi-rx-bus-width = <2>;\n\t\treg = <0>;\n\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\treg = <0x000000 0x010000>;\n\t\t\t\tlabel = \"cfe\";\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@10000 {\n\t\t\t\treg = <0x010000 0xfe0000>;\n\t\t\t\tlabel = \"linux\";\n\t\t\t\tcompatible = \"brcm,bcm963xx-imagetag\";\n\t\t\t};\n\n\t\t\tpartition@ff0000 {\n\t\t\t\treg = <0xff0000 0x010000>;\n\t\t\t\tlabel = \"nvram\";\n\t\t\t};\n\t\t};\n\t};\n};\n\n&uart0 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/bcm63xx/dts/bcm6328-sagem-fast-2704-v2.dts",
    "content": "#include \"bcm6328.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"Sagem F@st 2704 V2\";\n\tcompatible = \"sagem,fast-2704-v2\", \"brcm,bcm6328\";\n\n\taliases {\n\t\tled-boot = &led_power_green;\n\t\tled-failsafe = &led_power_green;\n\t\tled-running = &led_power_green;\n\t\tled-upgrade = &led_power_green;\n\t};\n\n\tchosen {\n\t\tbootargs = \"rootfstype=squashfs,jffs2 noinitrd console=ttyS0,115200\";\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tpoll-interval = <20>;\n\n\t\trfkill {\n\t\t\tlabel = \"rfkill\";\n\t\t\tgpios = <&pinctrl 15 1>;\n\t\t\tlinux,code = <KEY_WLAN>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&pinctrl 23 1>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&pinctrl 24 1>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tusb_green {\n\t\t\tlabel = \"green:usb\";\n\t\t\tgpios = <&pinctrl 1 1>;\n\t\t};\n\t\tinet_red {\n\t\t\tlabel = \"red:inet\";\n\t\t\tgpios = <&pinctrl 2 1>;\n\t\t};\n\t\tdsl_green {\n\t\t\tlabel = \"green:dsl\";\n\t\t\tgpios = <&pinctrl 3 1>;\n\t\t};\n\t\tled_power_green: power_green {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&pinctrl 4 1>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t\tpower_red {\n\t\t\tlabel = \"red:power\";\n\t\t\tgpios = <&pinctrl 5 1>;\n\t\t};\n\t\twps_green {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&pinctrl 10 1>;\n\t\t};\n\t\tinet_green {\n\t\t\tlabel = \"green:inet\";\n\t\t\tgpios = <&pinctrl 11 1>;\n\t\t};\n\t};\n};\n\n&hsspi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\tspi-max-frequency = <16666667>;\n\t\tspi-tx-bus-width = <2>;\n\t\tspi-rx-bus-width = <2>;\n\t\treg = <0>;\n\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tcfe@0 {\n\t\t\t\treg = <0x000000 0x010000>;\n\t\t\t\tlabel = \"cfe\";\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tlinux@10000 {\n\t\t\t\treg = <0x010000 0x7e0000>;\n\t\t\t\tlabel = \"linux\";\n\t\t\t\tcompatible = \"brcm,bcm963xx-imagetag\";\n\t\t\t};\n\n\t\t\tnvram@7f0000 {\n\t\t\t\treg = <0x7f0000 0x010000>;\n\t\t\t\tlabel = \"nvram\";\n\t\t\t};\n\t\t};\n\t};\n};\n\n&uart0 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/bcm63xx/dts/bcm6328-sercomm-ad1018-nor.dts",
    "content": "#include \"bcm6328.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"Sercomm AD1018 (SPI flash mod)\";\n\tcompatible = \"sercomm,ad1018-nor\", \"brcm,bcm6328\";\n\n\taliases {\n\t\tled-boot = &led_power_green;\n\t\tled-failsafe = &led_power_green;\n\t\tled-running = &led_power_green;\n\t\tled-upgrade = &led_power_green;\n\t};\n\n\tchosen {\n\t\tbootargs = \"rootfstype=squashfs,jffs2 noinitrd console=ttyS0,115200\";\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tpoll-interval = <20>;\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&pinctrl 24 1>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\twifi {\n\t\t\tlabel = \"wifi\";\n\t\t\tgpios = <&pinctrl 25 1>;\n\t\t\tlinux,code = <KEY_WLAN>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&pinctrl 31 1>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n};\n\n&pinctrl {\n\tpinctrl_leds: leds {\n\t\tfunction = \"led\";\n\t\tpins = \"gpio0\", \"gpio1\";\n\t};\n};\n\n&leds {\n\tstatus = \"okay\";\n\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_leds &pinctrl_serial_led\n\t\t     &pinctrl_ephy0_spd_led &pinctrl_ephy1_act_led\n\t\t     &pinctrl_ephy2_act_led &pinctrl_ephy3_act_led>;\n\n\tbrcm,serial-leds;\n\tbrcm,serial-shift-inv;\n\tbrcm,serial-dat-low;\n\n\tinet_red@0 {\n\t\treg = <0>;\n\t\tactive-low;\n\t\tlabel = \"red:internet\";\n\t};\n\n\tinet_green@1 {\n\t\treg = <1>;\n\t\tactive-low;\n\t\tlabel = \"green:internet\";\n\t};\n\n\tled_power_green: power_green@8 {\n\t\treg = <8>;\n\t\tactive-low;\n\t\tlabel = \"green:power\";\n\t\tdefault-state = \"on\";\n\t};\n\n\tadsl_green@10 {\n\t\treg = <10>;\n\t\tactive-low;\n\t\tlabel = \"green:adsl\";\n\t};\n\n\tadsl_red@11 {\n\t\treg = <11>;\n\t\tactive-low;\n\t\tlabel = \"red:adsl\";\n\t};\n\n\tphone_green@12 {\n\t\treg = <12>;\n\t\tactive-low;\n\t\tlabel = \"green:phone\";\n\t};\n\n\twps_green@13 {\n\t\treg = <13>;\n\t\tactive-low;\n\t\tlabel = \"green:wps\";\n\t};\n\n\twifi_green@14 {\n\t\treg = <14>;\n\t\tactive-low;\n\t\tlabel = \"green:wifi\";\n\t};\n\n\tusb_green@15 {\n\t\treg = <15>;\n\t\tactive-low;\n\t\tlabel = \"green:usb\";\n\t};\n\n\tephy0_spd@17 {\n\t\treg = <17>;\n\t\tbrcm,hardware-controlled;\n\t};\n};\n\n&hsspi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\tspi-max-frequency = <16666667>;\n\t\tspi-tx-bus-width = <2>;\n\t\tspi-rx-bus-width = <2>;\n\t\treg = <0>;\n\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"brcm,bcm963xx-cfe-nor-partitions\";\n\t\t};\n\t};\n};\n\n&nflash {\n\tstatus = \"okay\";\n\n\tnandcs@0 {\n\t\tcompatible = \"brcm,nandcs\";\n\t\treg = <0>;\n\t\tnand-ecc-step-size = <512>;\n\t\tnand-ecc-strength = <15>;\n\t\tnand-on-flash-bbt;\n\t\tbrcm,nand-oob-sector-size = <64>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"storage\";\n\t\t\t\treg = <0 0>; /* autodetected size */\n\t\t\t};\n\t\t};\n\t};\n};\n\n&uart0 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/bcm63xx/dts/bcm6328-sercomm-ad1018.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later\n\n#include \"bcm6328.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"Sercomm AD1018\";\n\tcompatible = \"sercomm,ad1018\", \"brcm,bcm6328\";\n\n\taliases {\n\t\tled-boot = &led_power_green;\n\t\tled-failsafe = &led_power_green;\n\t\tled-running = &led_power_green;\n\t\tled-upgrade = &led_power_green;\n\t};\n\n\tchosen {\n\t\tbootargs = \"rootfstype=squashfs,jffs2 noinitrd console=ttyS0,115200\";\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tpoll-interval = <20>;\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&pinctrl 24 1>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\twifi {\n\t\t\tlabel = \"wifi\";\n\t\t\tgpios = <&pinctrl 25 1>;\n\t\t\tlinux,code = <KEY_WLAN>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&pinctrl 31 1>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n};\n\n&leds {\n\tstatus = \"okay\";\n\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_leds &pinctrl_serial_led\n\t\t     &pinctrl_ephy0_spd_led &pinctrl_ephy1_act_led\n\t\t     &pinctrl_ephy2_act_led &pinctrl_ephy3_act_led>;\n\n\tbrcm,serial-leds;\n\tbrcm,serial-shift-inv;\n\tbrcm,serial-dat-low;\n\n\tled@0 {\n\t\treg = <0>;\n\t\tactive-low;\n\t\tlabel = \"red:internet\";\n\t};\n\n\tled@1 {\n\t\treg = <1>;\n\t\tactive-low;\n\t\tlabel = \"green:internet\";\n\t};\n\n\tled_power_green: led@8 {\n\t\treg = <8>;\n\t\tactive-low;\n\t\tlabel = \"green:power\";\n\t\tdefault-state = \"on\";\n\t};\n\n\tled@10 {\n\t\treg = <10>;\n\t\tactive-low;\n\t\tlabel = \"green:adsl\";\n\t};\n\n\tled@11 {\n\t\treg = <11>;\n\t\tactive-low;\n\t\tlabel = \"red:adsl\";\n\t};\n\n\tled@12 {\n\t\treg = <12>;\n\t\tactive-low;\n\t\tlabel = \"green:phone\";\n\t};\n\n\tled@13 {\n\t\treg = <13>;\n\t\tactive-low;\n\t\tlabel = \"green:wps\";\n\t};\n\n\tled@14 {\n\t\treg = <14>;\n\t\tactive-low;\n\t\tlabel = \"green:wifi\";\n\t};\n\n\tled@15 {\n\t\treg = <15>;\n\t\tactive-low;\n\t\tlabel = \"green:usb\";\n\t};\n\n\tled@17 {\n\t\t/* EPHY0 Spd */\n\t\treg = <17>;\n\t\tbrcm,hardware-controlled;\n\t};\n};\n\n&nflash {\n\tstatus = \"okay\";\n\n\tnandcs@0 {\n\t\tcompatible = \"brcm,nandcs\";\n\t\t#size-cells = <1>;\n\t\t#address-cells = <1>;\n\t\treg = <0>;\n\t\tnand-ecc-step-size = <512>;\n\t\tnand-ecc-strength = <15>;\n\t\tnand-on-flash-bbt;\n\t\tbrcm,nand-oob-sector-size = <64>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"cferom\";\n\t\t\t\treg = <0x0000000 0x0020000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tlabel = \"mmap\";\n\t\t\t\treg = <0x0020000 0x00a0000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@c0000 {\n\t\t\t\tlabel = \"cferam1\";\n\t\t\t\treg = <0x00c0000 0x0140000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@200000 {\n\t\t\t\tlabel = \"cferam2\";\n\t\t\t\treg = <0x0200000 0x0140000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@340000 {\n\t\t\t\tlabel = \"serial\";\n\t\t\t\treg = <0x0340000 0x00a0000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@3e0000 {\n\t\t\t\tlabel = \"protect\";\n\t\t\t\treg = <0x03e0000 0x0140000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@6920000 {\n\t\t\t\tlabel = \"bootflag1\";\n\t\t\t\treg = <0x6920000 0x0140000>;\n\t\t\t};\n\n\t\t\tpartition@6a60000 {\n\t\t\t\tlabel = \"bootflag2\";\n\t\t\t\treg = <0x6a60000 0x0140000>;\n\t\t\t};\n\n\t\t\tpartition@520000 {\n\t\t\t\tcompatible = \"sercomm,wfi\";\n\t\t\t\tlabel = \"wfi\";\n\t\t\t\treg = <0x0520000 0x6400000>;\n\t\t\t};\n\n\t\t\tpartition@6ba0000 {\n\t\t\t\tlabel = \"xml_cfg\";\n\t\t\t\treg = <0x6ba0000 0x0280000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@6e20000 {\n\t\t\t\tlabel = \"app_dat\";\n\t\t\t\treg = <0x6e20000 0x0280000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pinctrl {\n\tpinctrl_leds: leds {\n\t\tfunction = \"led\";\n\t\tpins = \"gpio0\", \"gpio1\";\n\t};\n};\n\n&uart0 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/bcm63xx/dts/bcm6328-technicolor-tg582n-telecom-italia.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"bcm6328.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"Technicolor TG582n Telecom Italia\";\n\tcompatible = \"technicolor,tg582n-telecom-italia\", \"brcm,bcm6328\";\n\n\taliases {\n\t\tled-boot = &led_power_green;\n\t\tled-failsafe = &led_power_green;\n\t\tled-running = &led_power_green;\n\t\tled-upgrade = &led_power_green;\n\t};\n\n\tchosen {\n\t\tbootargs = \"rootfstype=squashfs,jffs2 noinitrd console=ttyS0,115200\";\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&pinctrl 23 1>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&pinctrl 24 1>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n};\n\n&leds {\n\tstatus = \"okay\";\n\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_leds>;\n\n\tled@1 {\n\t\treg = <1>;\n\t\tactive-low;\n\t\tlabel = \"green:wifi\";\n\t};\n\n\tled_power_green: led@4 {\n\t\treg = <4>;\n\t\tactive-low;\n\t\tlabel = \"green:power\";\n\t\tdefault-state = \"on\";\n\t};\n\n\tled@5 {\n\t\treg = <5>;\n\t\tactive-low;\n\t\tlabel = \"green:adsl\";\n\t};\n\n\tled@7 {\n\t\treg = <7>;\n\t\tactive-low;\n\t\tlabel = \"red:wifi\";\n\t};\n\n\tled@8 {\n\t\treg = <8>;\n\t\tactive-low;\n\t\tlabel = \"red:power\";\n\t};\n\n\tled@11 {\n\t\treg = <11>;\n\t\tactive-low;\n\t\tlabel = \"green:internet\";\n\t};\n\n\tled@14 {\n\t\treg = <14>;\n\t\tactive-low;\n\t\tlabel = \"red:internet\";\n\t};\n\n\tled@18 {\n\t\treg = <18>;\n\t\tactive-low;\n\t\tlabel = \"red:service\";\n\t};\n\n\tled@19 {\n\t\treg = <19>;\n\t\tactive-low;\n\t\tlabel = \"green:service\";\n\t};\n};\n\n&hsspi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\tspi-max-frequency = <16666667>;\n\t\tspi-tx-bus-width = <2>;\n\t\tspi-rx-bus-width = <2>;\n\t\treg = <0>;\n\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\treg = <0x000000 0x010000>;\n\t\t\t\tlabel = \"cfe\";\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@10000 {\n\t\t\t\treg = <0x010000 0xff0000>;\n\t\t\t\tlabel = \"linux\";\n\t\t\t\tcompatible = \"brcm,bcm963xx-imagetag\";\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pinctrl {\n\tpinctrl_leds: leds {\n\t\tfunction = \"led\";\n\t\tpins = \"gpio1\", \"gpio4\",\n\t\t       \"gpio5\", \"gpio7\",\n\t\t       \"gpio8\", \"gpio11\",\n\t\t       \"gpio14\", \"gpio18\",\n\t\t       \"gpio19\";\n\t};\n};\n\n&uart0 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/bcm63xx/dts/bcm6328-technicolor-tg582n.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"bcm6328.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"Technicolor TG582n\";\n\tcompatible = \"technicolor,tg582n\", \"brcm,bcm6328\";\n\n\taliases {\n\t\tled-boot = &led_power_green;\n\t\tled-failsafe = &led_power_green;\n\t\tled-running = &led_power_green;\n\t\tled-upgrade = &led_power_green;\n\t};\n\n\tchosen {\n\t\tbootargs = \"rootfstype=squashfs,jffs2 noinitrd console=ttyS0,115200\";\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tpoll-interval = <20>;\n\n\t\twifi {\n\t\t\tlabel = \"wifi\";\n\t\t\tgpios = <&pinctrl 15 1>;\n\t\t\tlinux,code = <KEY_WLAN>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&pinctrl 23 1>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&pinctrl 24 1>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n};\n\n&leds {\n\tstatus = \"okay\";\n\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_leds>;\n\n\tled@1 {\n\t\treg = <1>;\n\t\tactive-low;\n\t\tlabel = \"green:internet\";\n\t};\n\n\tled@2 {\n\t\treg = <2>;\n\t\tactive-low;\n\t\tlabel = \"red:wifi\";\n\t};\n\n\tled@3 {\n\t\treg = <3>;\n\t\tactive-low;\n\t\tlabel = \"green:wifi\";\n\t};\n\n\tled_power_green: led@4 {\n\t\treg = <4>;\n\t\tactive-low;\n\t\tlabel = \"green:power\";\n\t\tdefault-state = \"on\";\n\t};\n\n\tled@5 {\n\t\treg = <5>;\n\t\tactive-low;\n\t\tlabel = \"green:ethernet\";\n\t};\n\n\tled@7 {\n\t\treg = <7>;\n\t\tactive-low;\n\t\tlabel = \"red:internet\";\n\t};\n\n\tled@8 {\n\t\treg = <8>;\n\t\tactive-low;\n\t\tlabel = \"red:power\";\n\t};\n\n\tled@9 {\n\t\treg = <9>;\n\t\tactive-low;\n\t\tlabel = \"green:wps\";\n\t};\n\n\tled@10 {\n\t\treg = <10>;\n\t\tactive-low;\n\t\tlabel = \"red:wps\";\n\t};\n\n\tled@11 {\n\t\treg = <11>;\n\t\tactive-low;\n\t\tlabel = \"green:broadband\";\n\t};\n};\n\n&hsspi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\tspi-max-frequency = <16666667>;\n\t\tspi-tx-bus-width = <2>;\n\t\tspi-rx-bus-width = <2>;\n\t\treg = <0>;\n\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\treg = <0x000000 0x010000>;\n\t\t\t\tlabel = \"cfe\";\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@10000 {\n\t\t\t\treg = <0x010000 0xff0000>;\n\t\t\t\tlabel = \"linux\";\n\t\t\t\tcompatible = \"brcm,bcm963xx-imagetag\";\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pinctrl {\n\tpinctrl_leds: leds {\n\t\tfunction = \"led\";\n\t\tpins = \"gpio1\", \"gpio2\",\n\t\t       \"gpio3\", \"gpio4\",\n\t\t       \"gpio5\", \"gpio7\",\n\t\t       \"gpio8\", \"gpio9\",\n\t\t       \"gpio10\", \"gpio11\";\n\t};\n};\n\n&uart0 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/bcm63xx/dts/bcm6328.dtsi",
    "content": "/dts-v1/;\n\n/ {\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\tcompatible = \"brcm,bcm6328\";\n\n\taliases {\n\t\tnflash = &nflash;\n\t\tpinctrl = &pinctrl;\n\t\tserial0 = &uart0;\n\t\tserial1 = &uart1;\n\t\tspi1 = &hsspi;\n\t};\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu@0 {\n\t\t\tcompatible = \"brcm,bmips4350\", \"mips,mips4Kc\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\treg = <0>;\n\t\t};\n\t};\n\n\tcpu_intc: interrupt-controller {\n\t\t#address-cells = <0>;\n\t\tcompatible = \"mti,cpu-interrupt-controller\";\n\n\t\tinterrupt-controller;\n\t\t#interrupt-cells = <1>;\n\t};\n\n\tmemory { device_type = \"memory\"; reg = <0 0>; };\n\n\tubus@10000000 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tranges;\n\t\tcompatible = \"simple-bus\";\n\t\tinterrupt-parent = <&periph_intc>;\n\n\t\text_intc: interrupt-controller@10000018 {\n\t\t\tcompatible = \"brcm,bcm6345-ext-intc\";\n\t\t\treg = <0x10000018 0x4>;\n\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <2>;\n\n\t\t\tinterrupts = <24>, <25>, <26>, <27>;\n\t\t};\n\n\t\tperiph_intc: interrupt-controller@10000020 {\n\t\t\tcompatible = \"brcm,bcm6345-l1-intc\";\n\t\t\treg = <0x10000020 0x10>;\n\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <1>;\n\n\t\t\tinterrupt-parent = <&cpu_intc>;\n\t\t\tinterrupts = <2>;\n\t\t};\n\n\t\tpinctrl: pin-controller@10000080 {\n\t\t\tcompatible = \"brcm,bcm6328-pinctrl\";\n\t\t\treg = <0x10000080 0x8>,\n\t\t\t      <0x10000088 0x8>,\n\t\t\t      <0x10000098 0x4>,\n\t\t\t      <0x1000009c 0xc>;\n\t\t\treg-names = \"dirout\", \"dat\", \"mode\", \"mux\";\n\n\t\t\tgpio-controller;\n\t\t\t#gpio-cells = <2>;\n\n\t\t\tinterrupt-parent = <&ext_intc>;\n\t\t\tinterrupts = <3 0>, <2 0>, <0 0>, <1 0>;\n\t\t\tinterrupt-names = \"gpio12\", \"gpio15\",\n\t\t\t\t\t  \"gpio23\", \"gpio24\";\n\n\t\t\tpinctrl_serial_led: serial_led {\n\t\t\t\tpinctrl_serial_led_data: serial_led_data {\n\t\t\t\t\tfunction = \"serial_led_data\";\n\t\t\t\t\tpins = \"gpio6\";\n\t\t\t\t};\n\n\t\t\t\tpinctrl_serial_led_clk: serial_led_clk {\n\t\t\t\t\tfunction = \"serial_led_clk\";\n\t\t\t\t\tpins = \"gpio7\";\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tpinctrl_inet_act_led: inet_act_led {\n\t\t\t\tfunction = \"inet_act_led\";\n\t\t\t\tpins = \"gpio11\";\n\t\t\t};\n\n\t\t\tpinctrl_pcie_clkreq: pcie_clkreq {\n\t\t\t\tfunction = \"pcie_clkreq\";\n\t\t\t\tpins = \"gpio16\";\n\t\t\t};\n\n\t\t\tpinctrl_ephy0_spd_led: ephy0_spd_led {\n\t\t\t\tfunction = \"led\";\n\t\t\t\tpins = \"gpio17\";\n\t\t\t};\n\n\t\t\tpinctrl_ephy1_spd_led: ephy1_spd_led {\n\t\t\t\tfunction = \"led\";\n\t\t\t\tpins = \"gpio18\";\n\t\t\t};\n\n\t\t\tpinctrl_ephy2_spd_led: ephy2_spd_led {\n\t\t\t\tfunction = \"led\";\n\t\t\t\tpins = \"gpio19\";\n\t\t\t};\n\n\t\t\tpinctrl_ephy3_spd_led: ephy3_spd_led {\n\t\t\t\tfunction = \"led\";\n\t\t\t\tpins = \"gpio20\";\n\t\t\t};\n\n\t\t\tpinctrl_ephy0_act_led: ephy0_act_led {\n\t\t\t\tfunction = \"ephy0_act_led\";\n\t\t\t\tpins = \"gpio25\";\n\t\t\t};\n\n\t\t\tpinctrl_ephy1_act_led: ephy1_act_led {\n\t\t\t\tfunction = \"ephy1_act_led\";\n\t\t\t\tpins = \"gpio26\";\n\t\t\t};\n\n\t\t\tpinctrl_ephy2_act_led: ephy2_act_led {\n\t\t\t\tfunction = \"ephy2_act_led\";\n\t\t\t\tpins = \"gpio27\";\n\t\t\t};\n\n\t\t\tpinctrl_ephy3_act_led: ephy3_act_led {\n\t\t\t\tfunction = \"ephy3_act_led\";\n\t\t\t\tpins = \"gpio28\";\n\t\t\t};\n\n\t\t\tpinctrl_hsspi_cs1: hsspi_cs1 {\n\t\t\t\tfunction = \"hsspi_cs1\";\n\t\t\t\tpins = \"hsspi_cs1\";\n\t\t\t};\n\n\t\t\tpinctrl_usb_port1_device: usb_port1_device {\n\t\t\t\tfunction = \"usb_device_port\";\n\t\t\t\tpins = \"usb_port1\";\n\t\t\t};\n\n\t\t\tpinctrl_usb_port1_host: usb_port1_host {\n\t\t\t\tfunction = \"usb_host_port\";\n\t\t\t\tpins = \"usb_port1\";\n\t\t\t};\n\t\t};\n\n\t\tuart0: serial@10000100 {\n\t\t\tcompatible = \"brcm,bcm6345-uart\";\n\t\t\treg = <0x10000100 0x18>;\n\n\t\t\tinterrupt-parent = <&periph_intc>;\n\t\t\tinterrupts = <28>;\n\n\t\t\t/* clocks = <&periph_clk>; */\n\t\t\t/* clock-names = \"refclk\"; */\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tuart1: serial@10000120 {\n\t\t\tcompatible = \"brcm,bcm6345-uart\";\n\t\t\treg = <0x10000120 0x18>;\n\n\t\t\tinterrupt-parent = <&periph_intc>;\n\t\t\tinterrupts = <39>;\n\n\t\t\t/* clocks = <&periph_clk>; */\n\t\t\t/* clock-names = \"refclk\"; */\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tnflash: nand@10000200 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tcompatible = \"brcm,nand-bcm6368\",\n\t\t\t\t     \"brcm,brcmnand-v2.2\",\n\t\t\t\t     \"brcm,brcmnand\";\n\t\t\treg = <0x10000200 0x180>,\n\t\t\t      <0x10000400 0x200>,\n\t\t\t      <0x10000070 0x10>;\n\t\t\treg-names = \"nand\",\n\t\t\t\t    \"nand-cache\",\n\t\t\t\t    \"nand-int-base\";\n\n\t\t\tinterrupt-parent = <&periph_intc>;\n\t\t\tinterrupts = <0>;\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tleds: led-controller@10000800 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tcompatible = \"brcm,bcm6328-leds\";\n\t\t\treg = <0x10000800 0x24>;\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\thsspi: spi@10001000 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tcompatible = \"brcm,bcm6328-hsspi\";\n\t\t\treg = <0x10001000 0x600>;\n\t\t\tinterrupts = <29>;\n\t\t\t/* clocks = <&clkctl 9>; */\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/bcm63xx/dts/bcm6338-brcm-bcm96338gw.dts",
    "content": "#include \"bcm6338.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"Broadcom BCM96338GW reference board\";\n\tcompatible = \"brcm,bcm96338gw\", \"brcm,bcm6338\";\n\n\tchosen {\n\t\tbootargs = \"rootfstype=squashfs,jffs2 noinitrd console=ttyS0,115200\";\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tpower_green {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio0 0 1>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t\tstop_green {\n\t\t\tlabel = \"green:stop\";\n\t\t\tgpios = <&gpio0 1 1>;\n\t\t};\n\t\tdsl_green {\n\t\t\tlabel = \"green:adsl\";\n\t\t\tgpios = <&gpio0 3 1>;\n\t\t};\n\t\tppp_fail_green {\n\t\t\tlabel = \"green:ppp-fail\";\n\t\t\tgpios = <&gpio0 4 1>;\n\t\t};\n\t\tses_green {\n\t\t\tlabel = \"green:ses\";\n\t\t\tgpios = <&gpio0 5 1>;\n\t\t};\n\t};\n};\n\n&pflash {\n\tstatus = \"okay\";\n\n\tpartitions {\n\t\tcompatible = \"brcm,bcm963xx-cfe-nor-partitions\";\n\t};\n};\n\n&uart0 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/bcm63xx/dts/bcm6338-brcm-bcm96338w.dts",
    "content": "#include \"bcm6338.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"Broadcom BCM96338W reference board\";\n\tcompatible = \"brcm,bcm96338w\", \"brcm,bcm6338\";\n\n\tchosen {\n\t\tbootargs = \"rootfstype=squashfs,jffs2 noinitrd console=ttyS0,115200\";\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tpower_green {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio0 0 1>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t\tstop_green {\n\t\t\tlabel = \"green:stop\";\n\t\t\tgpios = <&gpio0 1 1>;\n\t\t};\n\t\tdsl_green {\n\t\t\tlabel = \"green:adsl\";\n\t\t\tgpios = <&gpio0 3 1>;\n\t\t};\n\t\tppp_fail_green {\n\t\t\tlabel = \"green:ppp-fail\";\n\t\t\tgpios = <&gpio0 4 1>;\n\t\t};\n\t\tses_green {\n\t\t\tlabel = \"green:ses\";\n\t\t\tgpios = <&gpio0 5 1>;\n\t\t};\n\t};\n};\n\n&pflash {\n\tstatus = \"okay\";\n\n\tpartitions {\n\t\tcompatible = \"brcm,bcm963xx-cfe-nor-partitions\";\n\t};\n};\n\n&uart0 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/bcm63xx/dts/bcm6338-d-link-dsl-2640u.dts",
    "content": "#include \"bcm6338.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"D-Link DSL-2640U/BRU/C\";\n\tcompatible = \"d-link,dsl-2640u\", \"brcm,bcm6338\";\n\n\tchosen {\n\t\tbootargs = \"rootfstype=squashfs,jffs2 noinitrd console=ttyS0,115200\";\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tgreen_power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio0 0 1>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\tgreen_stop {\n\t\t\tlabel = \"green:ppp\";\n\t\t\tgpios = <&gpio0 4 1>;\n\t\t};\n\n\t\tgreen_adsl {\n\t\t\tlabel = \"green:ppp-fail\";\n\t\t\tgpios = <&gpio0 5 1>;\n\t\t};\n\t};\n};\n\n&pflash {\n\tstatus = \"okay\";\n\n\tpartitions {\n\t\tcompatible = \"fixed-partitions\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tcfe@0 {\n\t\t\tlabel = \"CFE\";\n\t\t\treg = <0x000000 0x010000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tlinux@10000 {\n\t\t\tlabel = \"linux\";\n\t\t\treg = <0x010000 0x3e0000>;\n\t\t\tcompatible = \"brcm,bcm963xx-imagetag\";\n\t\t};\n\n\t\tnvram@3f0000 {\n\t\t\tlabel = \"nvram\";\n\t\t\treg = <0x3f0000 0x010000>;\n\t\t};\n\t};\n};\n\n&uart0 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/bcm63xx/dts/bcm6338-dynalink-rta1320.dts",
    "content": "#include \"bcm6338.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"Dynalink RTA1320\";\n\tcompatible = \"dynalink,rta1320\", \"brcm,bcm6338\";\n\n\tchosen {\n\t\tbootargs = \"rootfstype=squashfs,jffs2 noinitrd console=ttyS0,115200\";\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tgreen_power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio0 0 1>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t\tgreen_stop {\n\t\t\tlabel = \"green:stop\";\n\t\t\tgpios = <&gpio0 1 1>;\n\t\t};\n\t\tgreen_adsl {\n\t\t\tlabel = \"green:adsl\";\n\t\t\tgpios = <&gpio0 3 1>;\n\t\t};\n\t\tgreen_ppp {\n\t\t\tlabel = \"green:ppp\";\n\t\t\tgpios = <&gpio0 4 1>;\n\t\t};\n\t};\n};\n\n&pflash {\n\tstatus = \"okay\";\n\n\tpartitions {\n\t\tcompatible = \"fixed-partitions\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tcfe@0 {\n\t\t\tlabel = \"CFE\";\n\t\t\treg = <0x000000 0x010000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tlinux@10000 {\n\t\t\tlabel = \"linux\";\n\t\t\treg = <0x010000 0x3e0000>;\n\t\t\tcompatible = \"brcm,bcm963xx-imagetag\";\n\t\t};\n\n\t\tnvram@3f0000 {\n\t\t\tlabel = \"nvram\";\n\t\t\treg = <0x3f0000 0x010000>;\n\t\t};\n\t};\n};\n\n&uart0 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/bcm63xx/dts/bcm6338.dtsi",
    "content": "/dts-v1/;\n\n/ {\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\tcompatible = \"brcm,bcm6338\";\n\n\taliases {\n\t\tpflash = &pflash;\n\t\tgpio0 = &gpio0;\n\t\tserial0 = &uart0;\n\t\tspi0 = &lsspi;\n\t};\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu@0 {\n\t\t\tcompatible = \"brcm,bmips3300\", \"mips,mips4Kc\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\treg = <0>;\n\t\t};\n\t};\n\n\tcpu_intc: interrupt-controller {\n\t\t#address-cells = <0>;\n\t\tcompatible = \"mti,cpu-interrupt-controller\";\n\n\t\tinterrupt-controller;\n\t\t#interrupt-cells = <1>;\n\t};\n\n\tmemory { device_type = \"memory\"; reg = <0 0>; };\n\n\tpflash: nor@1fc00000 {\n\t\tcompatible = \"cfi-flash\";\n\t\treg = <0x1fc00000 0x400000>;\n\t\tbank-width = <2>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tstatus = \"disabled\";\n\t};\n\n\tubus@fff00000 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tranges;\n\t\tcompatible = \"simple-bus\";\n\t\tinterrupt-parent = <&periph_intc>;\n\n\t\tperiph_intc: interrupt-controller@fffe000c {\n\t\t\tcompatible = \"brcm,bcm6345-l1-intc\";\n\t\t\treg = <0xfffe000c 0x8>;\n\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <1>;\n\n\t\t\tinterrupt-parent = <&cpu_intc>;\n\t\t\tinterrupts = <2>;\n\t\t};\n\n\t\text_intc: interrupt-controller@fffe0014 {\n\t\t\tcompatible = \"brcm,bcm6345-ext-intc\";\n\t\t\treg = <0xfffe0014 0x4>;\n\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <2>;\n\n\t\t\tinterrupt-parent = <&cpu_intc>;\n\t\t\tinterrupts = <3>, <4>, <5>, <6>;\n\t\t};\n\n\t\tgpio0: gpio-controller@fffe0404 {\n\t\t\tcompatible = \"brcm,bcm6345-gpio\";\n\t\t\treg = <0xfffe0404 4>, <0xfffe040c 4>;\n\n\t\t\tgpio-controller;\n\t\t\t#gpio-cells = <2>;\n\n\t\t\tngpios = <8>;\n\t\t};\n\n\t\tuart0: serial@fffe0300 {\n\t\t\tcompatible = \"brcm,bcm6345-uart\";\n\t\t\treg = <0xfffe0300 0x18>;\n\n\t\t\tinterrupt-parent = <&periph_intc>;\n\t\t\tinterrupts = <2>;\n\n\t\t\t/* clocks = <&periph_clk>; */\n\t\t\t/* clock-names = \"refclk\"; */\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tlsspi: spi@fffe0c00 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tcompatible = \"brcm,bcm6348-spi\";\n\t\t\treg = <0xfffe0c00 0x40>;\n\t\t\tinterrupts = <1>;\n\t\t\t/* clocks = <&clkctl 9>; */\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/bcm63xx/dts/bcm6345-brcm-bcm96345gw2.dts",
    "content": "#include \"bcm6345.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"Broadcom BCM96345GW2 reference board\";\n\tcompatible = \"brcm,bcm96345gw2\", \"brcm,bcm6345\";\n\n\tchosen {\n\t\tbootargs = \"rootfstype=squashfs,jffs2 noinitrd console=ttyS0,115200\";\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n};\n\n&pflash {\n\tstatus = \"okay\";\n\n\tpartitions {\n\t\tcompatible = \"brcm,bcm963xx-cfe-nor-partitions\";\n\t};\n};\n\n&uart0 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/bcm63xx/dts/bcm6345-dynalink-rta770bw.dts",
    "content": "#include \"bcm6345.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"Siemens Gigaset SE515\";\n\tcompatible = \"dynalink,rta770bw\", \"brcm,bcm6345\";\n\n\taliases {\n\t\tled-boot = &led_diag;\n\t\tled-failsafe = &led_diag;\n\t\tled-running = &led_diag;\n\t\tled-upgrade = &led_diag;\n\t};\n\n\tchosen {\n\t\tbootargs = \"rootfstype=squashfs,jffs2 noinitrd console=ttyS0,115200\";\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 13 1>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tusb {\n\t\t\tlabel = \"green:usb\";\n\t\t\tgpios = <&gpio0 7 1>;\n\t\t};\n\n\t\tadsl {\n\t\t\tlabel = \"green:adsl\";\n\t\t\tgpios = <&gpio0 8 0>;\n\t\t};\n\n\t\tled_diag: diag {\n\t\t\tlabel = \"green:diag\";\n\t\t\tgpios = <&gpio0 10 1>;\n\t\t};\n\n\t\twlan {\n\t\t\tlabel = \"green:wlan\";\n\t\t\tgpios = <&gpio0 11 1>;\n\t\t};\n\t};\n};\n\n&pflash {\n\tstatus = \"okay\";\n\n\tpartitions {\n\t\tcompatible = \"fixed-partitions\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tcfe@0 {\n\t\t\tlabel = \"CFE\";\n\t\t\treg = <0x000000 0x010000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tlinux@10000 {\n\t\t\tlabel = \"linux\";\n\t\t\treg = <0x010000 0x3e0000>;\n\t\t\tcompatible = \"brcm,bcm963xx-imagetag\";\n\t\t};\n\n\t\tnvram@3f0000 {\n\t\t\tlabel = \"nvram\";\n\t\t\treg = <0x3f0000 0x010000>;\n\t\t};\n\t};\n};\n\n&uart0 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/bcm63xx/dts/bcm6345-dynalink-rta770w.dts",
    "content": "#include \"bcm6345.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"Dynalink RTA770W\";\n\tcompatible = \"dynalink,rta770w\", \"brcm,bcm6345\";\n\n\taliases {\n\t\tled-boot = &led_diag;\n\t\tled-failsafe = &led_diag;\n\t\tled-running = &led_diag;\n\t\tled-upgrade = &led_diag;\n\t};\n\n\tchosen {\n\t\tbootargs = \"rootfstype=squashfs,jffs2 noinitrd console=ttyS0,115200\";\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 13 1>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tusb {\n\t\t\tlabel = \"green:usb\";\n\t\t\tgpios = <&gpio0 7 1>;\n\t\t};\n\n\t\tadsl {\n\t\t\tlabel = \"green:adsl\";\n\t\t\tgpios = <&gpio0 8 0>;\n\t\t};\n\n\t\tled_diag: diag {\n\t\t\tlabel = \"green:diag\";\n\t\t\tgpios = <&gpio0 10 1>;\n\t\t};\n\n\t\twlan {\n\t\t\tlabel = \"green:wlan\";\n\t\t\tgpios = <&gpio0 11 1>;\n\t\t};\n\t};\n};\n\n&pflash {\n\tstatus = \"okay\";\n\n\tpartitions {\n\t\tcompatible = \"fixed-partitions\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tcfe@0 {\n\t\t\tlabel = \"CFE\";\n\t\t\treg = <0x000000 0x010000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tlinux@10000 {\n\t\t\tlabel = \"linux\";\n\t\t\treg = <0x010000 0x3e0000>;\n\t\t\tcompatible = \"brcm,bcm963xx-imagetag\";\n\t\t};\n\n\t\tnvram@3f0000 {\n\t\t\tlabel = \"nvram\";\n\t\t\treg = <0x3f0000 0x010000>;\n\t\t};\n\t};\n};\n\n&uart0 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/bcm63xx/dts/bcm6345.dtsi",
    "content": "/dts-v1/;\n\n/ {\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\tcompatible = \"brcm,bcm6345\";\n\n\taliases {\n\t\tpflash = &pflash;\n\t\tserial0 = &uart0;\n\t\tgpio0 = &gpio0;\n\t};\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu@0 {\n\t\t\tcompatible = \"brcm,bmips32\", \"mips,mips4Kc\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\treg = <0>;\n\t\t};\n\t};\n\n\tcpu_intc: interrupt-controller {\n\t\t#address-cells = <0>;\n\t\tcompatible = \"mti,cpu-interrupt-controller\";\n\n\t\tinterrupt-controller;\n\t\t#interrupt-cells = <1>;\n\t};\n\n\tmemory { device_type = \"memory\"; reg = <0 0>; };\n\n\tpflash: nor@1fc00000 {\n\t\tcompatible = \"cfi-flash\";\n\t\treg = <0x1fc00000 0x400000>;\n\t\tbank-width = <2>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tstatus = \"disabled\";\n\t};\n\n\tubus@fff00000 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tranges;\n\t\tcompatible = \"simple-bus\";\n\n\t\tperiph_intc: interrupt-controller@fffe000c {\n\t\t\tcompatible = \"brcm,bcm6345-l1-intc\";\n\t\t\treg = <0xfffe000c 0x9>;\n\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <1>;\n\n\t\t\tinterrupt-parent = <&cpu_intc>;\n\t\t\tinterrupts = <2>;\n\t\t};\n\n\t\text_intc: interrupt-controller@fffe0014 {\n\t\t\tcompatible = \"brcm,bcm6345-ext-intc\";\n\t\t\treg = <0xfffe0014 0x4>;\n\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <2>;\n\n\t\t\tinterrupt-parent = <&cpu_intc>;\n\t\t\tinterrupts = <3>, <4>, <5>, <6>;\n\t\t};\n\n\t\tuart0: serial@fffe0300 {\n\t\t\tcompatible = \"brcm,bcm6345-uart\";\n\t\t\treg = <0xfffe0300 0x18>;\n\n\t\t\tinterrupt-parent = <&periph_intc>;\n\t\t\tinterrupts = <2>;\n\n\t\t\t/* clocks = <&periph_clk>; */\n\t\t\t/* clock-names = \"refclk\"; */\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tgpio0: gpio-controller@fffe0404 {\n\t\t\tcompatible = \"brcm,bcm6345-gpio\";\n\t\t\treg = <0xfffe0404 4>, <0xfffe0408 4>;\n\n\t\t\tgpio-controller;\n\t\t\t#gpio-cells = <2>;\n\n\t\t\tngpios = <16>;\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/bcm63xx/dts/bcm6348-asmax-ar-1004g.dts",
    "content": "#include \"bcm6348.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"ASMAX AR 1004g\";\n\tcompatible = \"asmax,ar-1004g\", \"brcm,bcm6348\";\n\n\taliases {\n\t\tled-boot = &led_power_green;\n\t\tled-failsafe = &led_power_green;\n\t\tled-running = &led_power_green;\n\t\tled-upgrade = &led_power_green;\n\t};\n\n\tchosen {\n\t\tbootargs = \"rootfstype=squashfs,jffs2 noinitrd console=ttyS0,115200\";\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&pinctrl 33 1>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power_green: power_green {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&pinctrl 0 1>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t\tinet_green {\n\t\t\tlabel = \"green:inet\";\n\t\t\tgpios = <&pinctrl 3 1>;\n\t\t};\n\t\tpower_red {\n\t\t\tlabel = \"red:power\";\n\t\t\tgpios = <&pinctrl 6 1>;\n\t\t};\n\t};\n};\n\n&pflash {\n\tstatus = \"okay\";\n\n\tpartitions {\n\t\tcompatible = \"fixed-partitions\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tcfe@0 {\n\t\t\tlabel = \"CFE\";\n\t\t\treg = <0x000000 0x010000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tlinux@10000 {\n\t\t\tlabel = \"linux\";\n\t\t\treg = <0x010000 0x3e0000>;\n\t\t\tcompatible = \"brcm,bcm963xx-imagetag\";\n\t\t};\n\n\t\tnvram@3f0000 {\n\t\t\tlabel = \"nvram\";\n\t\t\treg = <0x3f0000 0x010000>;\n\t\t};\n\t};\n};\n\n&pinctrl {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_ext_mii &pinctrl_pci>;\n};\n\n&uart0 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/bcm63xx/dts/bcm6348-belkin-f5d7633.dts",
    "content": "#include \"bcm6348.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"Belkin F5D7633\";\n\tcompatible = \"belkin,f5d7633\", \"brcm,bcm6348\";\n\n\tchosen {\n\t\tbootargs = \"rootfstype=squashfs,jffs2 noinitrd console=ttyS0,115200\";\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&pinctrl 6 1>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tpower_green {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&pinctrl 0 1>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t\tstop_green {\n\t\t\tlabel = \"green:stop\";\n\t\t\tgpios = <&pinctrl 1 1>;\n\t\t};\n\t\tadsl_fail_green {\n\t\t\tlabel = \"green:adsl-fail\";\n\t\t\tgpios = <&pinctrl 2 1>;\n\t\t};\n\t\tppp_green {\n\t\t\tlabel = \"green:ppp\";\n\t\t\tgpios = <&pinctrl 3 1>;\n\t\t};\n\t\tppp_fail_green {\n\t\t\tlabel = \"green:ppp-fail\";\n\t\t\tgpios = <&pinctrl 4 1>;\n\t\t};\n\t};\n};\n\n&pflash {\n\tstatus = \"okay\";\n\n\tpartitions {\n\t\tcompatible = \"fixed-partitions\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tcfe@0 {\n\t\t\tlabel = \"CFE\";\n\t\t\treg = <0x000000 0x020000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tlinux@20000 {\n\t\t\tlabel = \"linux\";\n\t\t\treg = <0x020000 0x3c0000>;\n\t\t\tcompatible = \"brcm,bcm963xx-imagetag\";\n\t\t};\n\n\t\tnvram@3e0000 {\n\t\t\tlabel = \"nvram\";\n\t\t\treg = <0x3e0000 0x020000>;\n\t\t};\n\t};\n};\n\n&pinctrl {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_pci &pinctrl_ext_mii &pinctrl_mii_pccard>;\n};\n\n&uart0 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/bcm63xx/dts/bcm6348-brcm-bcm96348gw-10.dts",
    "content": "#include \"bcm6348.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"Broadcom BCM96348GW-10 reference board\";\n\tcompatible = \"brcm,bcm96348gw-10\", \"brcm,bcm6348\";\n\n\tchosen {\n\t\tbootargs = \"rootfstype=squashfs,jffs2 noinitrd console=ttyS0,115200\";\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&pinctrl 6 1>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tpower_green {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&pinctrl 0 1>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t\tstop_green {\n\t\t\tlabel = \"green:stop\";\n\t\t\tgpios = <&pinctrl 1 1>;\n\t\t};\n\t\tadsl_fail_green {\n\t\t\tlabel = \"green:adsl-fail\";\n\t\t\tgpios = <&pinctrl 2 1>;\n\t\t};\n\t\tppp_green {\n\t\t\tlabel = \"green:ppp\";\n\t\t\tgpios = <&pinctrl 3 1>;\n\t\t};\n\t\tppp_fail_green {\n\t\t\tlabel = \"green:ppp-fail\";\n\t\t\tgpios = <&pinctrl 4 1>;\n\t\t};\n\t};\n};\n\n&pflash {\n\tstatus = \"okay\";\n\n\tpartitions {\n\t\tcompatible = \"brcm,bcm963xx-cfe-nor-partitions\";\n\t};\n};\n\n&pinctrl {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_pci &pinctrl_ext_mii &pinctrl_mii_pccard>;\n};\n\n&uart0 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/bcm63xx/dts/bcm6348-brcm-bcm96348gw-11.dts",
    "content": "#include \"bcm6348.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"Broadcom BCM96348GW-11 reference board\";\n\tcompatible = \"brcm,bcm96348gw-11\", \"brcm,bcm6348\";\n\n\taliases {\n\t\tled-boot = &led_power_green;\n\t\tled-failsafe = &led_power_green;\n\t\tled-running = &led_power_green;\n\t\tled-upgrade = &led_power_green;\n\t};\n\n\tchosen {\n\t\tbootargs = \"rootfstype=squashfs,jffs2 noinitrd console=ttyS0,115200\";\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&pinctrl 33 1>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power_green: power_green {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&pinctrl 0 1>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t\tstop_green {\n\t\t\tlabel = \"green:stop\";\n\t\t\tgpios = <&pinctrl 1 1>;\n\t\t};\n\t\tadsl_fail_green {\n\t\t\tlabel = \"green:adsl-fail\";\n\t\t\tgpios = <&pinctrl 2 1>;\n\t\t};\n\t\tppp_green {\n\t\t\tlabel = \"green:ppp\";\n\t\t\tgpios = <&pinctrl 3 1>;\n\t\t};\n\t\tppp_fail_green {\n\t\t\tlabel = \"green:ppp-fail\";\n\t\t\tgpios = <&pinctrl 4 1>;\n\t\t};\n\t};\n};\n\n&pflash {\n\tstatus = \"okay\";\n\n\tpartitions {\n\t\tcompatible = \"brcm,bcm963xx-cfe-nor-partitions\";\n\t};\n};\n\n&pinctrl {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_pci &pinctrl_ext_mii &pinctrl_mii_pccard>;\n};\n\n&uart0 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/bcm63xx/dts/bcm6348-brcm-bcm96348gw.dts",
    "content": "#include \"bcm6348.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"Broadcom BCM96348GW reference board\";\n\tcompatible = \"brcm,bcm96348gw\", \"brcm,bcm6348\";\n\n\taliases {\n\t\tled-boot = &led_power_green;\n\t\tled-failsafe = &led_power_green;\n\t\tled-running = &led_power_green;\n\t\tled-upgrade = &led_power_green;\n\t};\n\n\tchosen {\n\t\tbootargs = \"rootfstype=squashfs,jffs2 noinitrd console=ttyS0,115200\";\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&pinctrl 36 1>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power_green: power_green {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&pinctrl 0 1>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t\tstop_green {\n\t\t\tlabel = \"green:stop\";\n\t\t\tgpios = <&pinctrl 1 1>;\n\t\t};\n\t\tadsl_fail_green {\n\t\t\tlabel = \"green:adsl-fail\";\n\t\t\tgpios = <&pinctrl 2 1>;\n\t\t};\n\t\tppp_green {\n\t\t\tlabel = \"green:ppp\";\n\t\t\tgpios = <&pinctrl 3 1>;\n\t\t};\n\t\tppp_fail_green {\n\t\t\tlabel = \"green:ppp-fail\";\n\t\t\tgpios = <&pinctrl 4 1>;\n\t\t};\n\t};\n};\n\n&pflash {\n\tstatus = \"okay\";\n\n\tpartitions {\n\t\tcompatible = \"brcm,bcm963xx-cfe-nor-partitions\";\n\t};\n};\n\n&pinctrl {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_pci &pinctrl_ext_mii>;\n};\n\n&uart0 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/bcm63xx/dts/bcm6348-brcm-bcm96348r.dts",
    "content": "#include \"bcm6348.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"Broadcom 96348R reference board\";\n\tcompatible = \"brcm,bcm96348r\", \"brcm,bcm6348\";\n\n\tchosen {\n\t\tbootargs = \"rootfstype=squashfs,jffs2 noinitrd console=ttyS0,115200\";\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tpower_green {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&pinctrl 0 1>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t\tstop_green {\n\t\t\tlabel = \"green:stop\";\n\t\t\tgpios = <&pinctrl 1 1>;\n\t\t};\n\t\tadsl_fail_green {\n\t\t\tlabel = \"green:adsl-fail\";\n\t\t\tgpios = <&pinctrl 2 1>;\n\t\t};\n\t\tppp_green {\n\t\t\tlabel = \"green:ppp\";\n\t\t\tgpios = <&pinctrl 3 1>;\n\t\t};\n\t\tppp_fail_green {\n\t\t\tlabel = \"green:ppp-fail\";\n\t\t\tgpios = <&pinctrl 4 1>;\n\t\t};\n\t};\n};\n\n&pflash {\n\tstatus = \"okay\";\n\n\tpartitions {\n\t\tcompatible = \"brcm,bcm963xx-cfe-nor-partitions\";\n\t};\n};\n\n&pinctrl {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_pci>;\n};\n\n&uart0 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/bcm63xx/dts/bcm6348-bt-voyager-2110.dts",
    "content": "#include \"bcm6348.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"BT Voyager 2110\";\n\tcompatible = \"bt,voyager-2110\", \"brcm,bcm6348\";\n\n\taliases {\n\t\tled-boot = &led_power_green;\n\t\tled-failsafe = &led_power_green;\n\t\tled-running = &led_power_green;\n\t\tled-upgrade = &led_power_green;\n\t};\n\n\tchosen {\n\t\tbootargs = \"rootfstype=squashfs,jffs2 noinitrd console=ttyS0,115200\";\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&pinctrl 33 1>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power_green: power_green {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&pinctrl 0 1>;\n\t\t};\n\t\tpower_red {\n\t\t\tlabel = \"red:power\";\n\t\t\tgpios = <&pinctrl 1 1>;\n\t\t};\n\t\tadsl_green {\n\t\t\tlabel = \"green:adsl\";\n\t\t\tgpios = <&pinctrl 2 1>;\n\t\t};\n\t\tppp_green {\n\t\t\tlabel = \"green:ppp\";\n\t\t\tgpios = <&pinctrl 3 1>;\n\t\t};\n\t\twireless_green {\n\t\t\tlabel = \"green:wireless\";\n\t\t\tgpios = <&pinctrl 6 1>;\n\t\t};\n\t};\n};\n\n&pflash {\n\tstatus = \"okay\";\n\n\tpartitions {\n\t\tcompatible = \"fixed-partitions\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tcfe@0 {\n\t\t\tlabel = \"CFE\";\n\t\t\treg = <0x000000 0x010000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tlinux@10000 {\n\t\t\tlabel = \"linux\";\n\t\t\treg = <0x010000 0x3e0000>;\n\t\t\tcompatible = \"brcm,bcm963xx-imagetag\";\n\t\t};\n\n\t\tnvram@3f0000 {\n\t\t\tlabel = \"nvram\";\n\t\t\treg = <0x3f0000 0x010000>;\n\t\t};\n\t};\n};\n\n&pinctrl {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_pci &pinctrl_ext_mii>;\n};\n\n&uart0 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/bcm63xx/dts/bcm6348-bt-voyager-2500v-bb.dts",
    "content": "#include \"bcm6348.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"BT Voyager 2500V\";\n\tcompatible = \"bt,voyager-2500v-bb\", \"brcm,bcm6348\";\n\n\tchosen {\n\t\tbootargs = \"rootfstype=squashfs,jffs2 noinitrd console=ttyS0,115200\";\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&pinctrl 31 1>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tpower_green {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&pinctrl 0 1>;\n\t\t};\n\t\tpower_red {\n\t\t\tlabel = \"red:power\";\n\t\t\tgpios = <&pinctrl 1 1>;\n\t\t};\n\t\tadsl_green {\n\t\t\tlabel = \"green:adsl\";\n\t\t\tgpios = <&pinctrl 2 1>;\n\t\t};\n\t\tppp_green {\n\t\t\tlabel = \"green:ppp\";\n\t\t\tgpios = <&pinctrl 3 1>;\n\t\t};\n\t\twireless_green {\n\t\t\tlabel = \"green:wireless\";\n\t\t\tgpios = <&pinctrl 6 1>;\n\t\t};\n\t};\n};\n\n&pflash {\n\tstatus = \"okay\";\n\n\tpartitions {\n\t\tcompatible = \"fixed-partitions\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tcfe@0 {\n\t\t\tlabel = \"CFE\";\n\t\t\treg = <0x000000 0x010000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tlinux@10000 {\n\t\t\tlabel = \"linux\";\n\t\t\treg = <0x010000 0x3e0000>;\n\t\t\tcompatible = \"brcm,bcm963xx-imagetag\";\n\t\t};\n\n\t\tnvram@3f0000 {\n\t\t\tlabel = \"nvram\";\n\t\t\treg = <0x3f0000 0x010000>;\n\t\t};\n\t};\n};\n\n&pinctrl {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_pci &pinctrl_ext_mii>;\n};\n\n&uart0 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/bcm63xx/dts/bcm6348-comtrend-ct-5365.dts",
    "content": "#include \"bcm6348.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"Comtrend CT-5365\";\n\tcompatible = \"comtrend,ct-5365\", \"brcm,bcm6348\";\n\n\tchosen {\n\t\tbootargs = \"rootfstype=squashfs,jffs2 noinitrd console=ttyS0,115200\";\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&pinctrl 33 1>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\twlan {\n\t\t\tlabel = \"wlan\";\n\t\t\tgpios = <&pinctrl 34 1>;\n\t\t\tlinux,code = <KEY_WLAN>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&pinctrl 35 1>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tpower_green {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&pinctrl 0 1>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t\talarm_red {\n\t\t\tlabel = \"red:alarm\";\n\t\t\tgpios = <&pinctrl 2 1>;\n\t\t};\n\t\twps_green {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&pinctrl 6 1>;\n\t\t};\n\t};\n};\n\n&pflash {\n\tstatus = \"okay\";\n\n\tpartitions {\n\t\tcompatible = \"fixed-partitions\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tcfe@0 {\n\t\t\tlabel = \"CFE\";\n\t\t\treg = <0x000000 0x010000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tlinux@10000 {\n\t\t\tlabel = \"linux\";\n\t\t\treg = <0x010000 0x3e0000>;\n\t\t\tcompatible = \"brcm,bcm963xx-imagetag\";\n\t\t};\n\n\t\tnvram@3f0000 {\n\t\t\tlabel = \"nvram\";\n\t\t\treg = <0x3f0000 0x010000>;\n\t\t};\n\t};\n};\n\n&pinctrl {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_pci &pinctrl_ext_mii>;\n};\n\n&uart0 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/bcm63xx/dts/bcm6348-comtrend-ct-536plus.dts",
    "content": "#include \"bcm6348.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"Comtrend CT-536+/CT-5621T\";\n\tcompatible = \"comtrend,ct-536plus\", \"brcm,bcm6348\";\n\n\taliases {\n\t\tled-boot = &led_power_green;\n\t\tled-failsafe = &led_power_green;\n\t\tled-running = &led_power_green;\n\t\tled-upgrade = &led_power_green;\n\t};\n\n\tchosen {\n\t\tbootargs = \"rootfstype=squashfs,jffs2 noinitrd console=ttyS0,115200\";\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&pinctrl 33 1>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power_green: power_green {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&pinctrl 0 1>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t\tadsl_fail_green {\n\t\t\tlabel = \"green:adsl-fail\";\n\t\t\tgpios = <&pinctrl 2 1>;\n\t\t};\n\t};\n};\n\n&pflash {\n\tstatus = \"okay\";\n\n\tpartitions {\n\t\tcompatible = \"fixed-partitions\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tcfe@0 {\n\t\t\tlabel = \"CFE\";\n\t\t\treg = <0x000000 0x010000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tlinux@10000 {\n\t\t\tlabel = \"linux\";\n\t\t\treg = <0x010000 0x3e0000>;\n\t\t\tcompatible = \"brcm,bcm963xx-imagetag\";\n\t\t};\n\n\t\tnvram@3f0000 {\n\t\t\tlabel = \"nvram\";\n\t\t\treg = <0x3f0000 0x010000>;\n\t\t};\n\t};\n};\n\n&pinctrl {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_pci &pinctrl_ext_mii &pinctrl_mii_pccard>;\n};\n\n&uart0 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/bcm63xx/dts/bcm6348-d-link-dsl-2640b-b.dts",
    "content": "#include \"bcm6348.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"D-Link DSL-2640B rev B2\";\n\tcompatible = \"d-link,dsl-2640b-b\", \"brcm,bcm6348\";\n\n\taliases {\n\t\tled-boot = &led_power_green;\n\t\tled-failsafe = &led_power_green;\n\t\tled-running = &led_power_green;\n\t\tled-upgrade = &led_power_green;\n\t};\n\n\tchosen {\n\t\tbootargs = \"rootfstype=squashfs,jffs2 noinitrd console=ttyS0,115200\";\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&pinctrl 7 1>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power_green: power_green {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&pinctrl 0 1>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t\tstatus {\n\t\t\tlabel = \"status\";\n\t\t\tgpios = <&pinctrl 3 1>;\n\t\t};\n\t\tinet_green {\n\t\t\tlabel = \"green:internet\";\n\t\t\tgpios = <&pinctrl 4 1>;\n\t\t};\n\t\tinet_red {\n\t\t\tlabel = \"red:internet\";\n\t\t\tgpios = <&pinctrl 5 1>;\n\t\t};\n\t};\n};\n\n&pflash {\n\tstatus = \"okay\";\n\n\tpartitions {\n\t\tcompatible = \"fixed-partitions\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tcfe@0 {\n\t\t\tlabel = \"CFE\";\n\t\t\treg = <0x000000 0x010000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tlinux@10000 {\n\t\t\tlabel = \"linux\";\n\t\t\treg = <0x010000 0x3e0000>;\n\t\t\tcompatible = \"brcm,bcm963xx-imagetag\";\n\t\t};\n\n\t\tnvram@3f0000 {\n\t\t\tlabel = \"nvram\";\n\t\t\treg = <0x3f0000 0x010000>;\n\t\t};\n\t};\n};\n\n&pinctrl {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_pci &pinctrl_ext_mii>;\n};\n\n&uart0 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/bcm63xx/dts/bcm6348-davolink-dv-201amr.dts",
    "content": "#include \"bcm6348.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"Davolink DV-201AMR\";\n\tcompatible = \"davolink,dv-201amr\", \"brcm,bcm6348\";\n\n\tchosen {\n\t\tbootargs = \"rootfstype=squashfs,jffs2 noinitrd console=ttyS0,115200\";\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n};\n\n&pflash {\n\tstatus = \"okay\";\n\n\tpartitions {\n\t\tcompatible = \"fixed-partitions\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tbackup@0 {\n\t\t\tlabel = \"backup\";\n\t\t\treg = <0x000000 0x400000>;\n\t\t};\n\n\t\tcfe@400000 {\n\t\t\tlabel = \"cfe\";\n\t\t\treg = <0x400000 0x010000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tlinux@410000 {\n\t\t\tlabel = \"linux\";\n\t\t\treg = <0x410000 0x3f0000>;\n\t\t\tcompatible = \"brcm,bcm963xx-imagetag\";\n\t\t};\n\t};\n};\n\n&pinctrl {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_pci &pinctrl_ext_mii>;\n};\n\n&uart0 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/bcm63xx/dts/bcm6348-dynalink-rta1025w.dts",
    "content": "#include \"bcm6348.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"Dynalink RTA1025W\";\n\tcompatible = \"dynalink,rta1025w\", \"brcm,bcm6348\";\n\n\tchosen {\n\t\tbootargs = \"rootfstype=squashfs,jffs2 noinitrd console=ttyS0,115200\";\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n};\n\n&pflash {\n\tstatus = \"okay\";\n\n\tpartitions {\n\t\tcompatible = \"fixed-partitions\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tcfe@0 {\n\t\t\tlabel = \"CFE\";\n\t\t\treg = <0x000000 0x010000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tlinux@10000 {\n\t\t\tlabel = \"linux\";\n\t\t\treg = <0x010000 0x3e0000>;\n\t\t\tcompatible = \"brcm,bcm963xx-imagetag\";\n\t\t};\n\n\t\tnvram@3f0000 {\n\t\t\tlabel = \"nvram\";\n\t\t\treg = <0x3f0000 0x010000>;\n\t\t};\n\t};\n};\n\n&pinctrl {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_pci &pinctrl_ext_mii>;\n};\n\n&uart0 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/bcm63xx/dts/bcm6348-inventel-livebox-1.dts",
    "content": "#include \"bcm6348.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"Inventel Livebox 1\";\n\tcompatible = \"inventel,livebox-1\", \"brcm,bcm6348\";\n\n\taliases {\n\t\tled-boot = &led_red_adsl_fail;\n\t\tled-failsafe = &led_red_adsl_fail;\n\t\tled-running = &led_red_adsl_fail;\n\t\tled-upgrade = &led_red_adsl_fail;\n\t};\n\n\tchosen {\n\t\tbootargs = \"rootfstype=squashfs,jffs2 noinitrd console=ttyS0,115200\";\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tpoll-interval = <20>;\n\n\t\tbutton1 {\n\t\t\tlabel = \"1\";\n\t\t\tgpios = <&pinctrl 36 1>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\tbutton2 {\n\t\t\tlabel = \"2\";\n\t\t\tgpios = <&pinctrl 7 1>;\n\t\t\tlinux,code = <BTN_2>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_red_adsl_fail: red_adsl_fail {\n\t\t\tlabel = \"red:adsl-fail-power\";\n\t\t\tgpios = <&pinctrl 0 0>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\tred_adsl {\n\t\t\tlabel = \"red:adsl\";\n\t\t\tgpios = <&pinctrl 1 0>;\n\t\t};\n\n\t\tred_traffic {\n\t\t\tlabel = \"red:traffic\";\n\t\t\tgpios = <&pinctrl 2 0>;\n\t\t};\n\n\t\tred_phone {\n\t\t\tlabel = \"red:phone\";\n\t\t\tgpios = <&pinctrl 3 0>;\n\t\t};\n\n\t\tred_wifi {\n\t\t\tlabel = \"red:wifi\";\n\t\t\tgpios = <&pinctrl 4 0>;\n\t\t};\n\t};\n};\n\n&pflash {\n\treg = <0x1e400000 0x800000>;\n\tstatus = \"okay\";\n\n\tpartitions {\n\t\tcompatible = \"ecoscentric,redboot-fis-partitions\";\n\t};\n};\n\n&pinctrl {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_pci &pinctrl_ext_mii &pinctrl_mii_pccard>;\n};\n\n&uart0 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/bcm63xx/dts/bcm6348-netgear-dg834g-v4.dts",
    "content": "#include \"bcm6348.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"Netgear DG834G v4\";\n\tcompatible = \"netgear,dg834g-v4\", \"brcm,bcm6348\";\n\n\tchosen {\n\t\tbootargs = \"rootfstype=squashfs,jffs2 noinitrd console=ttyS0,115200\";\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&pinctrl 6 1>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tpower_green {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&pinctrl 0 1>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t\tstatus {\n\t\t\tlabel = \"red:power\";\n\t\t\tgpios = <&pinctrl 1 1>;\n\t\t};\n\t\tinet_green {\n\t\t\tlabel = \"adsl\";\n\t\t\tgpios = <&pinctrl 2 1>;\n\t\t};\n\t\tinet_red {\n\t\t\tlabel = \"internet\";\n\t\t\tgpios = <&pinctrl 3 1>;\n\t\t};\n\t};\n};\n\n&pflash {\n\tstatus = \"okay\";\n\n\tpartitions {\n\t\tcompatible = \"fixed-partitions\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tcfe@0 {\n\t\t\tlabel = \"CFE\";\n\t\t\treg = <0x000000 0x010000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tlinux@10000 {\n\t\t\tlabel = \"linux\";\n\t\t\treg = <0x010000 0x3e0000>;\n\t\t\tcompatible = \"brcm,bcm963xx-imagetag\";\n\t\t};\n\n\t\tnvram@3f0000 {\n\t\t\tlabel = \"nvram\";\n\t\t\treg = <0x3f0000 0x010000>;\n\t\t};\n\t};\n};\n\n&pinctrl {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_pci &pinctrl_ext_mii>;\n};\n\n&uart0 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/bcm63xx/dts/bcm6348-netgear-dg834gt-pn.dts",
    "content": "#include \"bcm6348.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"Netgear DG834GT/PN\";\n\tcompatible = \"netgear,dg834gt-pn\", \"brcm,bcm6348\";\n\n\tchosen {\n\t\tbootargs = \"rootfstype=squashfs,jffs2 noinitrd console=ttyS0,115200\";\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&pinctrl 6 1>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tpower_green {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&pinctrl 0 1>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t\tstop_green {\n\t\t\tlabel = \"green:stop\";\n\t\t\tgpios = <&pinctrl 1 1>;\n\t\t};\n\t\tadsl_fail_green {\n\t\t\tlabel = \"green:adsl-fail\";\n\t\t\tgpios = <&pinctrl 2 1>;\n\t\t};\n\t\tppp_green {\n\t\t\tlabel = \"green:ppp\";\n\t\t\tgpios = <&pinctrl 3 1>;\n\t\t};\n\t\tppp_fail_green {\n\t\t\tlabel = \"green:ppp-fail\";\n\t\t\tgpios = <&pinctrl 4 1>;\n\t\t};\n\t};\n};\n\n&pflash {\n\tstatus = \"okay\";\n\n\tpartitions {\n\t\tcompatible = \"fixed-partitions\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tcfe@0 {\n\t\t\tlabel = \"CFE\";\n\t\t\treg = <0x000000 0x010000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tlinux@10000 {\n\t\t\tlabel = \"linux\";\n\t\t\treg = <0x010000 0x3e0000>;\n\t\t\tcompatible = \"brcm,bcm963xx-imagetag\";\n\t\t};\n\n\t\tnvram@3f0000 {\n\t\t\tlabel = \"nvram\";\n\t\t\treg = <0x3f0000 0x010000>;\n\t\t};\n\t};\n};\n\n&pinctrl {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_pci &pinctrl_ext_mii &pinctrl_mii_pccard>;\n};\n\n&uart0 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/bcm63xx/dts/bcm6348-sagem-fast-2404.dts",
    "content": "#include \"bcm6348.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"Sagem F@st 2404\";\n\tcompatible = \"sagem,fast-2404\", \"brcm,bcm6348\";\n\n\tchosen {\n\t\tbootargs = \"rootfstype=squashfs,jffs2 noinitrd console=ttyS0,115200\";\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n};\n\n&pflash {\n\tstatus = \"okay\";\n\n\tpartitions {\n\t\tcompatible = \"fixed-partitions\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tcfe@0 {\n\t\t\tlabel = \"CFE\";\n\t\t\treg = <0x000000 0x010000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tlinux@10000 {\n\t\t\tlabel = \"linux\";\n\t\t\treg = <0x010000 0x3e0000>;\n\t\t\tcompatible = \"brcm,bcm963xx-imagetag\";\n\t\t};\n\n\t\tnvram@3f0000 {\n\t\t\tlabel = \"nvram\";\n\t\t\treg = <0x3f0000 0x010000>;\n\t\t};\n\t};\n};\n\n&pinctrl {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_pci &pinctrl_ext_mii &pinctrl_mii_pccard>;\n};\n\n&uart0 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/bcm63xx/dts/bcm6348-sagem-fast-2604.dts",
    "content": "#include \"bcm6348.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"Sagem F@st 2604\";\n\tcompatible = \"sagem,fast-2604\", \"brcm,bcm6348\";\n\n\tchosen {\n\t\tbootargs = \"rootfstype=squashfs,jffs2 noinitrd console=ttyS0,115200\";\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&pinctrl 33 1>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tpower_green {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&pinctrl 0 1>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t\tpower_red {\n\t\t\tlabel = \"red:power\";\n\t\t\tgpios = <&pinctrl 1 1>;\n\t\t};\n\t\tinet_red {\n\t\t\tlabel = \"red:inet\";\n\t\t\tgpios = <&pinctrl 4 1>;\n\t\t};\n\t\twps_green {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&pinctrl 5 1>;\n\t\t};\n\t};\n};\n\n&pflash {\n\tstatus = \"okay\";\n\n\tpartitions {\n\t\tcompatible = \"fixed-partitions\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tcfe@0 {\n\t\t\tlabel = \"CFE\";\n\t\t\treg = <0x000000 0x010000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tlinux@10000 {\n\t\t\tlabel = \"linux\";\n\t\t\treg = <0x010000 0x3e0000>;\n\t\t\tcompatible = \"brcm,bcm963xx-imagetag\";\n\t\t};\n\n\t\tnvram@3f0000 {\n\t\t\tlabel = \"nvram\";\n\t\t\treg = <0x3f0000 0x010000>;\n\t\t};\n\t};\n};\n\n&pinctrl {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_pci &pinctrl_ext_mii>;\n};\n\n&uart0 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/bcm63xx/dts/bcm6348-t-com-speedport-w-500v.dts",
    "content": "#include \"bcm6348.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"T-Com Speedport W 500V\";\n\tcompatible = \"t-com,speedport-w-500v\", \"brcm,bcm6348\";\n\n\taliases {\n\t\tled-boot = &led_power_green;\n\t\tled-failsafe = &led_power_green;\n\t\tled-running = &led_power_green;\n\t\tled-upgrade = &led_power_green;\n\t};\n\n\tchosen {\n\t\tbootargs = \"rootfstype=squashfs,jffs2 noinitrd console=ttyS0,115200\";\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&pinctrl 33 1>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power_green: power_green {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&pinctrl 0 1>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t\tpower_red {\n\t\t\tlabel = \"red:power\";\n\t\t\tgpios = <&pinctrl 1 1>;\n\t\t};\n\t\tppp_green {\n\t\t\tlabel = \"green:ppp\";\n\t\t\tgpios = <&pinctrl 3 1>;\n\t\t};\n\t\tpstn_green {\n\t\t\tlabel = \"green:pstn\";\n\t\t\tgpios = <&pinctrl 28 1>;\n\t\t};\n\t\tvoip_green {\n\t\t\tlabel = \"green:voip\";\n\t\t\tgpios = <&pinctrl 32 1>;\n\t\t};\n\t};\n};\n\n&pflash {\n\tstatus = \"okay\";\n\n\tpartitions {\n\t\tcompatible = \"fixed-partitions\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tcfe@0 {\n\t\t\tlabel = \"CFE\";\n\t\t\treg = <0x000000 0x010000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tlinux@10000 {\n\t\t\tlabel = \"linux\";\n\t\t\treg = <0x010000 0x3e0000>;\n\t\t\tcompatible = \"brcm,bcm963xx-imagetag\";\n\t\t};\n\n\t\tnvram@3f0000 {\n\t\t\tlabel = \"nvram\";\n\t\t\treg = <0x3f0000 0x010000>;\n\t\t};\n\t};\n};\n\n&pinctrl {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_pci>;\n};\n\n&uart0 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/bcm63xx/dts/bcm6348-tecom-gw6000.dts",
    "content": "#include \"bcm6348.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"TECOM GW6000\";\n\tcompatible = \"tecom,gw6000\", \"brcm,bcm6348\";\n\n\tchosen {\n\t\tbootargs = \"rootfstype=squashfs,jffs2 noinitrd console=ttyS0,115200\";\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&pinctrl 36 1>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n};\n\n&pflash {\n\tstatus = \"okay\";\n\n\tpartitions {\n\t\tcompatible = \"fixed-partitions\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tcfe@0 {\n\t\t\tlabel = \"CFE\";\n\t\t\treg = <0x000000 0x010000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tlinux@10000 {\n\t\t\tlabel = \"linux\";\n\t\t\treg = <0x010000 0x3e0000>;\n\t\t\tcompatible = \"brcm,bcm963xx-imagetag\";\n\t\t};\n\n\t\tnvram@3f0000 {\n\t\t\tlabel = \"nvram\";\n\t\t\treg = <0x3f0000 0x010000>;\n\t\t};\n\t};\n};\n\n&pinctrl {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_pci &pinctrl_ext_mii>;\n};\n\n&uart0 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/bcm63xx/dts/bcm6348-tecom-gw6200.dts",
    "content": "#include \"bcm6348.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"TECOM GW6200\";\n\tcompatible = \"tecom,gw6200\", \"brcm,bcm6348\";\n\n\taliases {\n\t\tled-boot = &led_line1_green;\n\t\tled-failsafe = &led_line1_green;\n\t\tled-running = &led_line1_green;\n\t\tled-upgrade = &led_line1_green;\n\t};\n\n\tchosen {\n\t\tbootargs = \"rootfstype=squashfs,jffs2 noinitrd console=ttyS0,115200\";\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&pinctrl 36 1>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_line1_green: line1_green {\n\t\t\tlabel = \"green:line1\";\n\t\t\tgpios = <&pinctrl 4 1>;\n\t\t};\n\t\tline2_green {\n\t\t\tlabel = \"green:line2\";\n\t\t\tgpios = <&pinctrl 5 1>;\n\t\t};\n\t\tline3_green {\n\t\t\tlabel = \"green:line3\";\n\t\t\tgpios = <&pinctrl 6 1>;\n\t\t};\n\t\ttel_green {\n\t\t\tlabel = \"green:tel\";\n\t\t\tgpios = <&pinctrl 7 1>;\n\t\t};\n\t};\n};\n\n&pflash {\n\tstatus = \"okay\";\n\n\tpartitions {\n\t\tcompatible = \"fixed-partitions\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tcfe@0 {\n\t\t\tlabel = \"CFE\";\n\t\t\treg = <0x000000 0x010000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tlinux@10000 {\n\t\t\tlabel = \"linux\";\n\t\t\treg = <0x010000 0x7e0000>;\n\t\t\tcompatible = \"brcm,bcm963xx-imagetag\";\n\t\t};\n\n\t\tnvram@7f0000 {\n\t\t\tlabel = \"nvram\";\n\t\t\treg = <0x7f0000 0x010000>;\n\t\t};\n\t};\n};\n\n&pinctrl {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_pci &pinctrl_ext_mii &pinctrl_mii_pccard>;\n};\n\n&uart0 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/bcm63xx/dts/bcm6348-telsey-cpva502plus.dts",
    "content": "#include \"bcm6348.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"Telsey CPVA502+\";\n\tcompatible = \"telsey,cpva502plus\", \"brcm,bcm6348\";\n\n\tchosen {\n\t\tbootargs = \"rootfstype=squashfs,jffs2 noinitrd console=ttyS0,115200\";\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&pinctrl 36 1>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tphone_green {\n\t\t\tlabel = \"green:phone\";\n\t\t\tgpios = <&pinctrl 0 1>;\n\t\t};\n\n\t\tlink_amber {\n\t\t\tlabel = \"amber:link\";\n\t\t\tgpios = <&pinctrl 5 1>;\n\t\t};\n\t};\n};\n\n&pflash {\n\tstatus = \"okay\";\n\n\tpartitions {\n\t\tcompatible = \"fixed-partitions\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tcfe@0 {\n\t\t\tlabel = \"CFE\";\n\t\t\treg = <0x000000 0x010000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tlinux@10000 {\n\t\t\tlabel = \"linux\";\n\t\t\treg = <0x010000 0x3e0000>;\n\t\t\tcompatible = \"brcm,bcm963xx-imagetag\";\n\t\t};\n\n\t\tnvram@3f0000 {\n\t\t\tlabel = \"nvram\";\n\t\t\treg = <0x3f0000 0x010000>;\n\t\t};\n\t};\n};\n\n&pinctrl {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_pci &pinctrl_ext_mii>;\n};\n\n&uart0 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/bcm63xx/dts/bcm6348-telsey-magic.dts",
    "content": "#include \"bcm6348.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"Alice W-Gate\";\n\tcompatible = \"telsey,magic\", \"brcm,bcm6348\";\n\n\tchosen {\n\t\tbootargs = \"rootfstype=squashfs,jffs2 noinitrd console=ttyS0,115200\";\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tpower {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&pinctrl 0 1>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\tstop {\n\t\t\tlabel = \"green:stop\";\n\t\t\tgpios = <&pinctrl 1 1>;\n\t\t};\n\n\t\thpna {\n\t\t\tlabel = \"green:hpna\";\n\t\t\tgpios = <&pinctrl 4 1>;\n\t\t};\n\n\t\tstatus {\n\t\t\tlabel = \"green:adsl\";\n\t\t\tgpios = <&pinctrl 5 1>;\n\t\t};\n\n\t\tvoip {\n\t\t\tlabel = \"green:voip\";\n\t\t\tgpios = <&pinctrl 22 1>;\n\t\t};\n\n\t\twifi {\n\t\t\tlabel = \"green:wifi\";\n\t\t\tgpios = <&pinctrl 28 0>;\n\t\t};\n\n\t\tusb {\n\t\t\tlabel = \"green:usb\";\n\t\t\tgpios = <&pinctrl 35 1>;\n\t\t};\n\t};\n};\n\n&pflash {\n\tstatus = \"okay\";\n\n\tpartitions {\n\t\tcompatible = \"fixed-partitions\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tcfe@0 {\n\t\t\tlabel = \"CFE\";\n\t\t\treg = <0x000000 0x010000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tlinux@10000 {\n\t\t\tlabel = \"linux\";\n\t\t\treg = <0x010000 0x3e0000>;\n\t\t\tcompatible = \"brcm,bcm963xx-imagetag\";\n\t\t};\n\n\t\tnvram@3f0000 {\n\t\t\tlabel = \"nvram\";\n\t\t\treg = <0x3f0000 0x010000>;\n\t\t};\n\t};\n};\n\n&pinctrl {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_pci &pinctrl_ext_mii &pinctrl_mii_pccard>;\n};\n\n&uart0 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/bcm63xx/dts/bcm6348-tp-link-td-w8900gb.dts",
    "content": "#include \"bcm6348.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"TP-Link TD-W8900GB\";\n\tcompatible = \"tp-link,td-w8900gb\", \"brcm,bcm6348\";\n\n\tchosen {\n\t\tbootargs = \"rootfstype=squashfs,jffs2 noinitrd console=ttyS0,115200\";\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&pinctrl 33 1>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tpower_green {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&pinctrl 0 1>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t\tstop_green {\n\t\t\tlabel = \"green:stop\";\n\t\t\tgpios = <&pinctrl 1 1>;\n\t\t};\n\t\tadsl_fail_green {\n\t\t\tlabel = \"green:adsl-fail\";\n\t\t\tgpios = <&pinctrl 2 1>;\n\t\t};\n\t\tppp_green {\n\t\t\tlabel = \"green:ppp\";\n\t\t\tgpios = <&pinctrl 3 1>;\n\t\t};\n\t\tppp_fail_green {\n\t\t\tlabel = \"green:ppp-fail\";\n\t\t\tgpios = <&pinctrl 4 1>;\n\t\t};\n\t};\n};\n\n&pflash {\n\tstatus = \"okay\";\n\n\tpartitions {\n\t\tcompatible = \"fixed-partitions\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tcfe@0 {\n\t\t\tlabel = \"CFE\";\n\t\t\treg = <0x000000 0x020000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tlinux@20000 {\n\t\t\tlabel = \"linux\";\n\t\t\treg = <0x020000 0x3d0000>;\n\t\t\tcompatible = \"brcm,bcm963xx-imagetag\";\n\t\t};\n\n\t\tnvram@3e0000 {\n\t\t\tlabel = \"nvram\";\n\t\t\treg = <0x3f0000 0x010000>;\n\t\t};\n\t};\n};\n\n&pinctrl {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_pci &pinctrl_ext_mii &pinctrl_mii_pccard>;\n};\n\n&uart0 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/bcm63xx/dts/bcm6348-usrobotics-usr9108.dts",
    "content": "#include \"bcm6348.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"USRobotics USR9108\";\n\tcompatible = \"usrobotics,usr9108\", \"brcm,bcm6348\";\n\n\tchosen {\n\t\tbootargs = \"rootfstype=squashfs,jffs2 noinitrd console=ttyS0,115200\";\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tusb {\n\t\t\tlabel = \"usb\";\n\t\t\tgpios = <&pinctrl 0 1>;\n\t\t};\n\t\tdsl {\n\t\t\tlabel = \"adsl\";\n\t\t\tgpios = <&pinctrl 3 1>;\n\t\t};\n\t};\n};\n\n&pflash {\n\tstatus = \"okay\";\n\n\tpartitions {\n\t\tcompatible = \"fixed-partitions\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tcfe@0 {\n\t\t\tlabel = \"CFE\";\n\t\t\treg = <0x000000 0x010000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tlinux@10000 {\n\t\t\tlabel = \"linux\";\n\t\t\treg = <0x010000 0x3e0000>;\n\t\t\tcompatible = \"brcm,bcm963xx-imagetag\";\n\t\t};\n\n\t\tnvram@3f0000 {\n\t\t\tlabel = \"nvram\";\n\t\t\treg = <0x3f0000 0x010000>;\n\t\t};\n\t};\n};\n\n&pinctrl {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_pci &pinctrl_ext_mii>;\n};\n\n&uart0 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/bcm63xx/dts/bcm6348.dtsi",
    "content": "/dts-v1/;\n\n/ {\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\tcompatible = \"brcm,bcm6348\";\n\n\taliases {\n\t\tpflash = &pflash;\n\t\tpinctrl = &pinctrl;\n\t\tserial0 = &uart0;\n\t\tspi0 = &lsspi;\n\t};\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu@0 {\n\t\t\tcompatible = \"brcm,bmips3300\", \"mips,mips4Kc\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\treg = <0>;\n\t\t};\n\t};\n\n\tcpu_intc: interrupt-controller {\n\t\t#address-cells = <0>;\n\t\tcompatible = \"mti,cpu-interrupt-controller\";\n\n\t\tinterrupt-controller;\n\t\t#interrupt-cells = <1>;\n\t};\n\n\tmemory { device_type = \"memory\"; reg = <0 0>; };\n\n\tpflash: nor@1fc00000 {\n\t\tcompatible = \"cfi-flash\";\n\t\treg = <0x1fc00000 0x400000>;\n\t\tbank-width = <2>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tstatus = \"disabled\";\n\t};\n\n\tubus@fff00000 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tranges;\n\t\tcompatible = \"simple-bus\";\n\t\tinterrupt-parent = <&periph_intc>;\n\n\t\tperiph_intc: interrupt-controller@fffe000c {\n\t\t\tcompatible = \"brcm,bcm6345-l1-intc\";\n\t\t\treg = <0xfffe000c 0x8>;\n\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <1>;\n\n\t\t\tinterrupt-parent = <&cpu_intc>;\n\t\t\tinterrupts = <2>;\n\t\t};\n\n\t\text_intc: interrupt-controller@fffe0014 {\n\t\t\tcompatible = \"brcm,bcm6345-ext-intc\";\n\t\t\treg = <0xfffe0014 0x4>;\n\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <2>;\n\n\t\t\tinterrupt-parent = <&cpu_intc>;\n\t\t\tinterrupts = <3>, <4>, <5>, <6>;\n\n\t\t\tbrcm,field-width = <5>;\n\t\t};\n\n\t\tpinctrl: pin-controller@fffe0400 {\n\t\t\tcompatible = \"brcm,bcm6348-pinctrl\";\n\t\t\treg = <0xfffe0400 0x8>,\n\t\t\t      <0xfffe0408 0x8>,\n\t\t\t      <0xfffe0418 0x4>;\n\t\t\treg-names = \"dirout\", \"dat\", \"mode\";\n\n\t\t\tgpio-controller;\n\t\t\t#gpio-cells = <2>;\n\n\t\t\tinterrupt-parent = <&ext_intc>;\n\t\t\tinterrupts = <0 0>, <1 0>, <2 0>, <3 0>;\n\t\t\tinterrupt-names = \"gpio32\", \"gpio33\", \"gpio34\", \"gpio35\";\n\n\t\t\tpinctrl_ext_ephy: ext_ephy {\n\t\t\t\tfunction = \"ext_ephy\";\n\t\t\t\tgroups = \"group1\", \"group4\";\n\t\t\t};\n\n\t\t\tpinctrl_mii_snoop: mii_snoop {\n\t\t\t\tfunction = \"mii_snoop\";\n\t\t\t\tgroups = \"group1\", \"group4\";\n\t\t\t};\n\n\t\t\tpinctrl_legacy_led: legacy_led {\n\t\t\t\tfunction = \"legacy_led\";\n\t\t\t\tgroups = \"group4\";\n\t\t\t};\n\n\t\t\tpinctrl_mii_pccard: mii_pccard {\n\t\t\t\tfunction = \"mii_pccard\";\n\t\t\t\tgroups = \"group1\";\n\t\t\t};\n\n\t\t\tpinctrl_pci: pci {\n\t\t\t\tfunction = \"pci\";\n\t\t\t\tgroups = \"group2\";\n\t\t\t};\n\n\t\t\tpinctrl_spi_master_uart: spi_master_uart {\n\t\t\t\tfunction = \"spi_master_uart\";\n\t\t\t\tgroups = \"group1\";\n\t\t\t};\n\n\t\t\tpinctrl_ext_mii: ext_mii {\n\t\t\t\tfunction = \"ext_mii\";\n\t\t\t\tgroups = \"group0\", \"group3\";\n\t\t\t};\n\n\t\t\tpinctrl_utopia: utopia {\n\t\t\t\tfunction = \"utopia\";\n\t\t\t\tgroups = \"group1\", \"group3\", \"group4\";\n\t\t\t};\n\n\t\t\tpinctrl_diag: diag {\n\t\t\t\tfunction = \"diag\";\n\t\t\t\tgroups = \"group0\", \"group1\", \"group2\", \"group3\", \"group4\";\n\t\t\t};\n\t\t};\n\n\t\tuart0: serial@fffe0300 {\n\t\t\tcompatible = \"brcm,bcm6345-uart\";\n\t\t\treg = <0xfffe0300 0x18>;\n\n\t\t\tinterrupt-parent = <&periph_intc>;\n\t\t\tinterrupts = <2>;\n\n\t\t\t/* clocks = <&periph_clk>; */\n\t\t\t/* clock-names = \"refclk\"; */\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tlsspi: spi@fffe0c00 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tcompatible = \"brcm,bcm6348-spi\";\n\t\t\treg = <0xfffe0c00 0x40>;\n\t\t\tinterrupts = <1>;\n\t\t\t/* clocks = <&clkctl 9>; */\n\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/bcm63xx/dts/bcm6358-alcatel-rg100a.dts",
    "content": "#include \"bcm6358.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"Alcatel RG100A\";\n\tcompatible = \"alcatel,rg100a\", \"brcm,bcm6358\";\n\n\tchosen {\n\t\tbootargs = \"rootfstype=squashfs,jffs2 noinitrd console=ttyS0,115200\";\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tstop_green {\n\t\t\tlabel = \"green:stop\";\n\t\t\tgpios = <&pinctrl 4 1>;\n\t\t};\n\t\tpower_green {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&pinctrl 5 1>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t\tadsl_green {\n\t\t\tlabel = \"green:adsl\";\n\t\t\tgpios = <&pinctrl 22 1>;\n\t\t};\n\t\tppp_fail_green {\n\t\t\tlabel = \"green:ppp-fail\";\n\t\t\tgpios = <&pinctrl 23 0>;\n\t\t};\n\t};\n};\n\n&pflash {\n\tstatus = \"okay\";\n\n\tpartitions {\n\t\tcompatible = \"fixed-partitions\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tcfe@0 {\n\t\t\tlabel = \"CFE\";\n\t\t\treg = <0x000000 0x020000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tlinux@20000 {\n\t\t\tlabel = \"linux\";\n\t\t\treg = <0x020000 0xfc0000>;\n\t\t\tcompatible = \"brcm,bcm963xx-imagetag\";\n\t\t};\n\n\t\tnvram@fe0000 {\n\t\t\tlabel = \"nvram\";\n\t\t\treg = <0xfe0000 0x020000>;\n\t\t};\n\t};\n};\n\n&uart0 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/bcm63xx/dts/bcm6358-brcm-bcm96358vw.dts",
    "content": "#include \"bcm6358.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"Broadcom BCM96358VW reference board\";\n\tcompatible = \"brcm,bcm96358vw\", \"brcm,bcm6358\";\n\n\tchosen {\n\t\tbootargs = \"rootfstype=squashfs,jffs2 noinitrd console=ttyS0,115200\";\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tpower_green {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&pinctrl 4 0>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t\tstop_green {\n\t\t\tlabel = \"green:stop\";\n\t\t\tgpios = <&pinctrl 5 0>;\n\t\t};\n\t\tadsl_fail_green {\n\t\t\tlabel = \"green:adsl-fail\";\n\t\t\tgpios = <&pinctrl 15 1>;\n\t\t};\n\t\tppp_green {\n\t\t\tlabel = \"green:ppp\";\n\t\t\tgpios = <&pinctrl 22 1>;\n\t\t};\n\t\tppp_fail_green {\n\t\t\tlabel = \"green:ppp-fail\";\n\t\t\tgpios = <&pinctrl 23 1>;\n\t\t};\n\t};\n};\n\n&pflash {\n\tstatus = \"okay\";\n\n\tpartitions {\n\t\tcompatible = \"brcm,bcm963xx-cfe-nor-partitions\";\n\t};\n};\n\n&uart0 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/bcm63xx/dts/bcm6358-brcm-bcm96358vw2.dts",
    "content": "#include \"bcm6358.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"Broadcom BCM96358VW2 reference board\";\n\tcompatible = \"brcm,bcm96358vw2\", \"brcm,bcm6358\";\n\n\tchosen {\n\t\tbootargs = \"rootfstype=squashfs,jffs2 noinitrd console=ttyS0,115200\";\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tstop_green {\n\t\t\tlabel = \"green:stop\";\n\t\t\tgpios = <&pinctrl 4 1>;\n\t\t};\n\t\tpower_green {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&pinctrl 5 1>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t\tadsl_green {\n\t\t\tlabel = \"green:adsl\";\n\t\t\tgpios = <&pinctrl 22 1>;\n\t\t};\n\t\tppp_fail_green {\n\t\t\tlabel = \"green:ppp-fail\";\n\t\t\tgpios = <&pinctrl 23 0>;\n\t\t};\n\t};\n};\n\n&pflash {\n\tstatus = \"okay\";\n\n\tpartitions {\n\t\tcompatible = \"brcm,bcm963xx-cfe-nor-partitions\";\n\t};\n};\n\n&uart0 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/bcm63xx/dts/bcm6358-bt-home-hub-2-a.dts",
    "content": "#include \"bcm6358.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"BT Home Hub 2.0 Type A\";\n\tcompatible = \"bt,home-hub-2-a\", \"brcm,bcm6358\";\n\n\taliases {\n\t\tled-boot = &led_power_green;\n\t\tled-failsafe = &led_power_green;\n\t\tled-running = &led_power_green;\n\t\tled-upgrade = &led_upgrading_green;\n\t};\n\n\tchosen {\n\t\tbootargs = \"rootfstype=squashfs,jffs2 noinitrd console=ttyS0,115200\";\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tpoll-interval = <20>;\n\n\t\tphone {\n\t\t\tlabel = \"phone\";\n\t\t\tgpios = <&pinctrl 1 1>;\n\t\t\tlinux,code = <KEY_PHONE>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&pinctrl 9 1>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&pinctrl 11 1>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n};\n\n&leds {\n\tstatus = \"okay\";\n\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_serial_led>;\n\n\tled@0 {\n\t\treg = <0>;\n\t\tactive-low;\n\t\tlabel = \"red:power\";\n\t};\n\n\tled_power_green: led@1 {\n\t\treg = <0>;\n\t\tactive-low;\n\t\tlabel = \"green:power\";\n\t\tdefault-state = \"on\";\n\t};\n\n\tled@2 {\n\t\treg = <2>;\n\t\tactive-low;\n\t\tlabel = \"blue:power\";\n\t};\n\n\tled@3 {\n\t\treg = <3>;\n\t\tactive-low;\n\t\tlabel = \"red:broadband\";\n\t};\n\n\tled@4 {\n\t\treg = <4>;\n\t\tactive-low;\n\t\tlabel = \"green:broadband\";\n\t};\n\n\tled@5 {\n\t\treg = <5>;\n\t\tactive-low;\n\t\tlabel = \"blue:broadband\";\n\t};\n\n\tled@6 {\n\t\treg = <6>;\n\t\tactive-low;\n\t\tlabel = \"red:wireless\";\n\t};\n\n\tled@7 {\n\t\treg = <7>;\n\t\tactive-low;\n\t\tlabel = \"green:wireless\";\n\t};\n\n\tled@8 {\n\t\treg = <8>;\n\t\tactive-low;\n\t\tlabel = \"blue:wireless\";\n\t};\n\n\tled@9 {\n\t\treg = <9>;\n\t\tactive-low;\n\t\tlabel = \"red:phone\";\n\t};\n\n\tled@10 {\n\t\treg = <10>;\n\t\tactive-low;\n\t\tlabel = \"green:phone\";\n\t};\n\n\tled@11 {\n\t\treg = <11>;\n\t\tactive-low;\n\t\tlabel = \"blue:phone\";\n\t};\n\n\tled@12 {\n\t\treg = <12>;\n\t\tactive-low;\n\t\tlabel = \"red:upgrading\";\n\t};\n\n\tled_upgrading_green: led@13 {\n\t\treg = <13>;\n\t\tactive-low;\n\t\tlabel = \"green:upgrading\";\n\t};\n\n\tled@14 {\n\t\treg = <14>;\n\t\tactive-low;\n\t\tlabel = \"blue:upgrading\";\n\t};\n};\n\n&pflash {\n\tstatus = \"okay\";\n\n\tpartitions {\n\t\tcompatible = \"fixed-partitions\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tcfe@0 {\n\t\t\tlabel = \"CFE\";\n\t\t\treg = <0x000000 0x020000>;\n\t\t};\n\n\t\tlinux@20000 {\n\t\t\tlabel = \"linux\";\n\t\t\treg = <0x020000 0xfc0000>;\n\t\t\tcompatible = \"brcm,bcm963xx-imagetag\";\n\t\t};\n\n\t\tnvram@fe0000 {\n\t\t\tlabel = \"nvram\";\n\t\t\treg = <0xfe0000 0x020000>;\n\t\t};\n\t};\n};\n\n&uart0 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/bcm63xx/dts/bcm6358-comtrend-ct-6373.dts",
    "content": "#include \"bcm6358.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"Comtrend CT-6373\";\n\tcompatible = \"comtrend,ct-6373\", \"brcm,bcm6358\";\n\n\tchosen {\n\t\tbootargs = \"rootfstype=squashfs,jffs2 noinitrd console=ttyS0,115200\";\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&pinctrl 35 1>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tpower_green {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&pinctrl 0 0>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t\tusb_green {\n\t\t\tlabel = \"green:usb\";\n\t\t\tgpios = <&pinctrl 3 1>;\n\t\t};\n\t\twlan_green {\n\t\t\tlabel = \"green:wlan\";\n\t\t\tgpios = <&pinctrl 9 1>;\n\t\t};\n\t};\n};\n\n&leds {\n\tstatus = \"okay\";\n\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_serial_led>;\n\n\tled@0 {\n\t\treg = <0>;\n\t\tactive-low;\n\t\tlabel = \"green:adsl\";\n\t};\n\n\tled@1 {\n\t\treg = <1>;\n\t\tactive-low;\n\t\tlabel = \"green:line\";\n\t};\n\n\tled@2 {\n\t\treg = <2>;\n\t\tactive-low;\n\t\tlabel = \"green:fxs1\";\n\t};\n\n\tled@3 {\n\t\treg = <3>;\n\t\tactive-low;\n\t\tlabel = \"green:fxs2\";\n\t};\n};\n\n&pflash {\n\tstatus = \"okay\";\n\n\tpartitions {\n\t\tcompatible = \"fixed-partitions\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tcfe@0 {\n\t\t\tlabel = \"CFE\";\n\t\t\treg = <0x000000 0x010000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tlinux@10000 {\n\t\t\tlabel = \"linux\";\n\t\t\treg = <0x010000 0x7e0000>;\n\t\t\tcompatible = \"brcm,bcm963xx-imagetag\";\n\t\t};\n\n\t\tnvram@7f0000 {\n\t\t\tlabel = \"nvram\";\n\t\t\treg = <0x7f0000 0x010000>;\n\t\t};\n\t};\n};\n\n&uart0 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/bcm63xx/dts/bcm6358-d-link-dsl-2650u.dts",
    "content": "#include \"bcm6358.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"D-Link DSL-2650U\";\n\tcompatible = \"d-link,dsl-2650u\", \"brcm,bcm6358\";\n\n\tchosen {\n\t\tbootargs = \"rootfstype=squashfs,jffs2 noinitrd console=ttyS0,115200\";\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tstop_green {\n\t\t\tlabel = \"green:stop\";\n\t\t\tgpios = <&pinctrl 4 1>;\n\t\t};\n\t\tpower_green {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&pinctrl 5 1>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t\tadsl_green {\n\t\t\tlabel = \"green:adsl\";\n\t\t\tgpios = <&pinctrl 22 1>;\n\t\t};\n\t\tppp_fail_green {\n\t\t\tlabel = \"green:ppp-fail\";\n\t\t\tgpios = <&pinctrl 23 0>;\n\t\t};\n\t};\n};\n\n&pflash {\n\tstatus = \"okay\";\n\n\tpartitions {\n\t\tcompatible = \"fixed-partitions\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tcfe@0 {\n\t\t\tlabel = \"CFE\";\n\t\t\treg = <0x000000 0x010000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tlinux@10000 {\n\t\t\tlabel = \"linux\";\n\t\t\treg = <0x010000 0x7e0000>;\n\t\t\tcompatible = \"brcm,bcm963xx-imagetag\";\n\t\t};\n\n\t\tnvram@7f0000 {\n\t\t\tlabel = \"nvram\";\n\t\t\treg = <0x7f0000 0x010000>;\n\t\t};\n\t};\n};\n\n&uart0 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/bcm63xx/dts/bcm6358-d-link-dsl-274xb-c2.dts",
    "content": "#include \"bcm6358.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"D-Link DSL-2740B/DSL-2741B rev C2/3\";\n\tcompatible = \"d-link,dsl-274xb-c2\", \"brcm,bcm6358\";\n\n\taliases {\n\t\tled-boot = &led_power_green;\n\t\tled-failsafe = &led_power_green;\n\t\tled-running = &led_power_green;\n\t\tled-upgrade = &led_power_green;\n\t};\n\n\tchosen {\n\t\tbootargs = \"rootfstype=squashfs,jffs2 noinitrd console=ttyS0,115200\";\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&pinctrl 34 1>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tinet_green {\n\t\t\tlabel = \"green:internet\";\n\t\t\tgpios = <&pinctrl 2 0>;\n\t\t};\n\t\tpower_red {\n\t\t\tlabel = \"red:power\";\n\t\t\tgpios = <&pinctrl 4 1>;\n\t\t};\n\t\tled_power_green: power_green {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&pinctrl 5 1>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t\tdsl_green {\n\t\t\tlabel = \"green:adsl\";\n\t\t\tgpios = <&pinctrl 9 1>;\n\t\t};\n\t\tinet_red {\n\t\t\tlabel = \"red:internet\";\n\t\t\tgpios = <&pinctrl 10 0>;\n\t\t};\n\t};\n};\n\n&pflash {\n\tstatus = \"okay\";\n\n\tpartitions {\n\t\tcompatible = \"fixed-partitions\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tcfe@0 {\n\t\t\tlabel = \"CFE\";\n\t\t\treg = <0x000000 0x010000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tlinux@10000 {\n\t\t\tlabel = \"linux\";\n\t\t\treg = <0x010000 0x3e0000>;\n\t\t\tcompatible = \"brcm,bcm963xx-imagetag\";\n\t\t};\n\n\t\tnvram@3f0000 {\n\t\t\tlabel = \"nvram\";\n\t\t\treg = <0x3f0000 0x010000>;\n\t\t};\n\t};\n};\n\n&uart0 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/bcm63xx/dts/bcm6358-d-link-dva-g3810bn-tl.dts",
    "content": "#include \"bcm6358.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"D-Link DVA-G3810BN/TL\";\n\tcompatible = \"d-link,dva-g3810bn-tl\", \"brcm,bcm6358\";\n\n\tchosen {\n\t\tbootargs = \"rootfstype=squashfs,jffs2 noinitrd console=ttyS0,115200\";\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&pinctrl 34 1>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tvoip {\n\t\t\tlabel = \"voip\";\n\t\t\tgpios = <&pinctrl 1 0>;\n\t\t};\n\t\tpower {\n\t\t\tlabel = \"power\";\n\t\t\tgpios = <&pinctrl 4 0>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t\tstop {\n\t\t\tlabel = \"stop\";\n\t\t\tgpios = <&pinctrl 5 0>;\n\t\t};\n\t\tdsl {\n\t\t\tlabel = \"dsl\";\n\t\t\tgpios = <&pinctrl 22 1>;\n\t\t};\n\t\tinet {\n\t\t\tlabel = \"internet\";\n\t\t\tgpios = <&pinctrl 23 1>;\n\t\t};\n\t};\n};\n\n&pflash {\n\tstatus = \"okay\";\n\n\tpartitions {\n\t\tcompatible = \"fixed-partitions\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tcfe@0 {\n\t\t\tlabel = \"CFE\";\n\t\t\treg = <0x000000 0x010000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tlinux@10000 {\n\t\t\tlabel = \"linux\";\n\t\t\treg = <0x010000 0x7e0000>;\n\t\t\tcompatible = \"brcm,bcm963xx-imagetag\";\n\t\t};\n\n\t\tnvram@7f0000 {\n\t\t\tlabel = \"nvram\";\n\t\t\treg = <0x7f0000 0x010000>;\n\t\t};\n\t};\n};\n\n&uart0 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/bcm63xx/dts/bcm6358-huawei-echolife-hg553.dts",
    "content": "#include \"bcm6358.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"Huawei EchoLife HG553\";\n\tcompatible = \"huawei,echolife-hg553\", \"brcm,bcm6358\";\n\n\taliases {\n\t\tled-boot = &led_power_blue;\n\t\tled-failsafe = &led_power_blue;\n\t\tled-running = &led_power_blue;\n\t\tled-upgrade = &led_power_blue;\n\t};\n\n\tchosen {\n\t\tbootargs = \"rootfstype=squashfs,jffs2 noinitrd console=ttyS0,115200\";\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tpoll-interval = <20>;\n\n\t\trfkill {\n\t\t\tlabel = \"rfkill\";\n\t\t\tgpios = <&pinctrl 9 1>;\n\t\t\tlinux,code = <KEY_RFKILL>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&pinctrl 37 1>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power_blue: power_blue {\n\t\t\tlabel = \"blue:power\";\n\t\t\tgpios = <&pinctrl 4 1>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t\tpower_red {\n\t\t\tlabel = \"red:power\";\n\t\t\tgpios = <&pinctrl 5 1>;\n\t\t};\n\t\thspa_red {\n\t\t\tlabel = \"red:hspa\";\n\t\t\tgpios = <&pinctrl 12 1>;\n\t\t};\n\t\thspa_blue {\n\t\t\tlabel = \"blue:hspa\";\n\t\t\tgpios = <&pinctrl 13 1>;\n\t\t};\n\t\tlan_red {\n\t\t\tlabel = \"red:lan\";\n\t\t\tgpios = <&pinctrl 22 1>;\n\t\t};\n\t\tlan_blue {\n\t\t\tlabel = \"blue:lan\";\n\t\t\tgpios = <&pinctrl 23 1>;\n\t\t};\n\t\twifi_red {\n\t\t\tlabel = \"red:wifi\";\n\t\t\tgpios = <&pinctrl 25 1>;\n\t\t};\n\t\tdsl_red {\n\t\t\tlabel = \"red:adsl\";\n\t\t\tgpios = <&pinctrl 34 1>;\n\t\t};\n\t\tdsl_blue {\n\t\t\tlabel = \"blue:adsl\";\n\t\t\tgpios = <&pinctrl 35 1>;\n\t\t};\n\t};\n};\n\n&pflash {\n\tstatus = \"okay\";\n\n\tpartitions {\n\t\tcompatible = \"fixed-partitions\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tcfe@0 {\n\t\t\tlabel = \"CFE\";\n\t\t\treg = <0x000000 0x020000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tlinux@20000 {\n\t\t\tlabel = \"linux\";\n\t\t\treg = <0x020000 0xfc0000>;\n\t\t\tcompatible = \"brcm,bcm963xx-imagetag\";\n\t\t};\n\n\t\tnvram@fe0000 {\n\t\t\tlabel = \"nvram\";\n\t\t\treg = <0xfe0000 0x020000>;\n\t\t};\n\t};\n};\n\n&uart0 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/bcm63xx/dts/bcm6358-huawei-echolife-hg556a-a.dts",
    "content": "#include \"bcm6358-huawei-echolife-hg556a.dtsi\"\n\n/ {\n\tmodel = \"Huawei EchoLife HG556a (version A)\";\n\tcompatible = \"huawei,echolife-hg556a-a\", \"brcm,bcm6358\";\n};\n\n&gpiokeys {\n\thelp {\n\t\tlabel = \"help\";\n\t\tgpios = <&pinctrl 8 1>;\n\t\tlinux,code = <KEY_HELP>;\n\t\tdebounce-interval = <60>;\n\t};\n};\n\n&gpioleds {\n\tmessage_red {\n\t\tlabel = \"red:message\";\n\t\tgpios = <&pinctrl 0 1>;\n\t};\n\n\thspa_red {\n\t\tlabel = \"red:hspa\";\n\t\tgpios = <&pinctrl 1 1>;\n\t};\n\n\tall_red {\n\t\tlabel = \"red:all\";\n\t\tgpios = <&pinctrl 6 1>;\n\t\tdefault-state = \"on\";\n\t};\n\n\tlan1_green {\n\t\tlabel = \"green:lan1\";\n\t\tgpios = <&pinctrl 12 1>;\n\t};\n\n\tlan2_green {\n\t\tlabel = \"green:lan2\";\n\t\tgpios = <&pinctrl 15 1>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/bcm63xx/dts/bcm6358-huawei-echolife-hg556a-b.dts",
    "content": "#include \"bcm6358-huawei-echolife-hg556a.dtsi\"\n\n/ {\n\tmodel = \"Huawei EchoLife HG556a (version B)\";\n\tcompatible = \"huawei,echolife-hg556a-b\", \"brcm,bcm6358\";\n};\n\n&gpiokeys {\n\thelp {\n\t\tlabel = \"help\";\n\t\tgpios = <&pinctrl 8 1>;\n\t\tlinux,code = <KEY_HELP>;\n\t\tdebounce-interval = <60>;\n\t};\n};\n\n&gpioleds {\n\tmessage_red {\n\t\tlabel = \"red:message\";\n\t\tgpios = <&pinctrl 0 1>;\n\t};\n\n\thspa_red {\n\t\tlabel = \"red:hspa\";\n\t\tgpios = <&pinctrl 1 1>;\n\t};\n\n\tall_red {\n\t\tlabel = \"red:all\";\n\t\tgpios = <&pinctrl 6 1>;\n\t\tdefault-state = \"on\";\n\t};\n\n\tlan1_green {\n\t\tlabel = \"green:lan1\";\n\t\tgpios = <&pinctrl 12 1>;\n\t};\n\n\tlan2_green {\n\t\tlabel = \"green:lan2\";\n\t\tgpios = <&pinctrl 15 1>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/bcm63xx/dts/bcm6358-huawei-echolife-hg556a-c.dts",
    "content": "#include \"bcm6358-huawei-echolife-hg556a.dtsi\"\n\n/ {\n\tmodel = \"Huawei EchoLife HG556a (version C)\";\n\tcompatible = \"huawei,echolife-hg556a-c\", \"brcm,bcm6358\";\n};\n\n&gpiokeys {\n\thelp {\n\t\tlabel = \"help\";\n\t\tgpios = <&pinctrl 36 1>;\n\t\tlinux,code = <KEY_HELP>;\n\t\tdebounce-interval = <60>;\n\t};\n};\n\n&gpioleds {\n\tlan1_green {\n\t\tlabel = \"green:lan1\";\n\t\tgpios = <&pinctrl 0 1>;\n\t};\n\n\tlan2_green {\n\t\tlabel = \"green:lan2\";\n\t\tgpios = <&pinctrl 1 1>;\n\t};\n\n\tmessage_red {\n\t\tlabel = \"red:message\";\n\t\tgpios = <&pinctrl 12 1>;\n\t};\n\n\thspa_red {\n\t\tlabel = \"red:hspa\";\n\t\tgpios = <&pinctrl 15 1>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/bcm63xx/dts/bcm6358-huawei-echolife-hg556a.dtsi",
    "content": "#include \"bcm6358.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\taliases {\n\t\tled-boot = &led_power_red;\n\t\tled-failsafe = &led_power_red;\n\t\tled-running = &led_power_red;\n\t\tled-upgrade = &led_power_red;\n\t};\n\n\tchosen {\n\t\tbootargs = \"rootfstype=squashfs,jffs2 noinitrd console=ttyS0,115200\";\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\tgpiokeys: keys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tpoll-interval = <20>;\n\n\t\twlan {\n\t\t\tlabel = \"wlan\";\n\t\t\tgpios = <&pinctrl 9 1>;\n\t\t\tlinux,code = <KEY_WLAN>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\trestart {\n\t\t\tlabel = \"restart\";\n\t\t\tgpios = <&pinctrl 10 1>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&pinctrl 11 1>;\n\t\t\tlinux,code = <KEY_CONFIG>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tgpioleds: leds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tdsl_red {\n\t\t\tlabel = \"red:dsl\";\n\t\t\tgpios = <&pinctrl 2 1>;\n\t\t};\n\n\t\tled_power_red: power_red {\n\t\t\tlabel = \"red:power\";\n\t\t\tgpios = <&pinctrl 3 1>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\tlan1_red {\n\t\t\tlabel = \"red:lan1\";\n\t\t\tgpios = <&pinctrl 13 1>;\n\t\t};\n\n\t\tlan2_red {\n\t\t\tlabel = \"red:lan2\";\n\t\t\tgpios = <&pinctrl 22 1>;\n\t\t};\n\n\t\tlan3_green {\n\t\t\tlabel = \"green:lan3\";\n\t\t\tgpios = <&pinctrl 23 1>;\n\t\t};\n\n\t\tlan3_red {\n\t\t\tlabel = \"red:lan3\";\n\t\t\tgpios = <&pinctrl 26 1>;\n\t\t};\n\n\t\tlan4_green {\n\t\t\tlabel = \"green:lan4\";\n\t\t\tgpios = <&pinctrl 27 1>;\n\t\t};\n\n\t\tlan4_red {\n\t\t\tlabel = \"red:lan4\";\n\t\t\tgpios = <&pinctrl 28 1>;\n\t\t};\n\t};\n};\n\n&pflash {\n\tstatus = \"okay\";\n\n\tpartitions {\n\t\tcompatible = \"fixed-partitions\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tcfe@0 {\n\t\t\tlabel = \"CFE\";\n\t\t\treg = <0x000000 0x020000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tlinux@20000 {\n\t\t\tlabel = \"linux\";\n\t\t\treg = <0x020000 0xec0000>;\n\t\t\tcompatible = \"brcm,bcm963xx-imagetag\";\n\t\t};\n\n\t\tcal_data@ee0000 {\n\t\t\tlabel = \"cal_data\";\n\t\t\treg = <0xee0000 0x100000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tnvram@fe0000 {\n\t\t\tlabel = \"nvram\";\n\t\t\treg = <0xfe0000 0x020000>;\n\t\t};\n\t};\n};\n\n&uart0 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/bcm63xx/dts/bcm6358-pirelli-a226.dtsi",
    "content": "#include \"bcm6358.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tchosen {\n\t\tbootargs = \"rootfstype=squashfs,jffs2 noinitrd console=ttyS0,115200\";\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tpoll-interval = <20>;\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&pinctrl 34 1>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&pinctrl 37 1>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tvoip_red {\n\t\t\tlabel = \"red:VoIP\";\n\t\t\tgpios = <&pinctrl 0 1>;\n\t\t};\n\t\teth_red {\n\t\t\tlabel = \"red:ethernet\";\n\t\t\tgpios = <&pinctrl 1 1>;\n\t\t};\n\t\tdsl_green {\n\t\t\tlabel = \"green:ADSL\";\n\t\t\tgpios = <&pinctrl 2 1>;\n\t\t};\n\t\tusb_green {\n\t\t\tlabel = \"green:USB\";\n\t\t\tgpios = <&pinctrl 3 1>;\n\t\t};\n\t\tpower_green {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&pinctrl 4 1>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t\tpower_red {\n\t\t\tlabel = \"red:power\";\n\t\t\tgpios = <&pinctrl 5 1>;\n\t\t};\n\t\tinet_red {\n\t\t\tlabel = \"red:internet\";\n\t\t\tgpios = <&pinctrl 6 1>;\n\t\t};\n\t\tinet_green {\n\t\t\tlabel = \"green:internet\";\n\t\t\tgpios = <&pinctrl 7 1>;\n\t\t};\n\t\teth_green {\n\t\t\tlabel = \"green:ethernet\";\n\t\t\tgpios = <&pinctrl 8 1>;\n\t\t};\n\t\tvoip_green {\n\t\t\tlabel = \"green:VoIP\";\n\t\t\tgpios = <&pinctrl 9 1>;\n\t\t};\n\t\twifi_red {\n\t\t\tlabel = \"red:wifi\";\n\t\t\tgpios = <&pinctrl 10 1>;\n\t\t};\n\t\tusb_red {\n\t\t\tlabel = \"red:USB\";\n\t\t\tgpios = <&pinctrl 11 1>;\n\t\t};\n\t\tdsl_red {\n\t\t\tlabel = \"red:ADSL\";\n\t\t\tgpios = <&pinctrl 12 1>;\n\t\t};\n\t};\n};\n\n&uart0 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/bcm63xx/dts/bcm6358-pirelli-a226g.dts",
    "content": "#include \"bcm6358-pirelli-a226.dtsi\"\n\n/ {\n\tmodel = \"Pirelli A226G\";\n\tcompatible = \"pirelli,a226g\", \"brcm,bcm6358\";\n};\n\n&pflash {\n\tstatus = \"okay\";\n\n\tpartitions {\n\t\tcompatible = \"fixed-partitions\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tcfe@0 {\n\t\t\tlabel = \"CFE\";\n\t\t\treg = <0x000000 0x010000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tlinux@10000 {\n\t\t\tlabel = \"linux\";\n\t\t\treg = <0x010000 0x7e0000>;\n\t\t\tcompatible = \"brcm,bcm963xx-imagetag\";\n\t\t};\n\n\t\tnvram@7f0000 {\n\t\t\tlabel = \"nvram\";\n\t\t\treg = <0x7f0000 0x010000>;\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/bcm63xx/dts/bcm6358-pirelli-a226m-fwb.dts",
    "content": "#include \"bcm6358-pirelli-a226.dtsi\"\n\n/ {\n\tmodel = \"Pirelli A226M-FWB\";\n\tcompatible = \"pirelli,a226m-fwb\", \"brcm,bcm6358\";\n};\n\n&pflash {\n\tstatus = \"okay\";\n\n\tpartitions {\n\t\tcompatible = \"fixed-partitions\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"CFE\";\n\t\t\treg = <0x000000 0x020000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@20000 {\n\t\t\tlabel = \"linux\";\n\t\t\treg = <0x020000 0xfc0000>;\n\t\t\tcompatible = \"brcm,bcm963xx-imagetag\";\n\t\t};\n\n\t\tpartition@fe0000 {\n\t\t\tlabel = \"nvram\";\n\t\t\treg = <0xfe0000 0x020000>;\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/bcm63xx/dts/bcm6358-pirelli-a226m.dts",
    "content": "#include \"bcm6358-pirelli-a226.dtsi\"\n\n/ {\n\tmodel = \"Pirelli A226M\";\n\tcompatible = \"pirelli,a226m\", \"brcm,bcm6358\";\n};\n\n&pflash {\n\tstatus = \"okay\";\n\n\tpartitions {\n\t\tcompatible = \"fixed-partitions\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tcfe@0 {\n\t\t\tlabel = \"CFE\";\n\t\t\treg = <0x000000 0x010000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tlinux@10000 {\n\t\t\tlabel = \"linux\";\n\t\t\treg = <0x010000 0x7e0000>;\n\t\t\tcompatible = \"brcm,bcm963xx-imagetag\";\n\t\t};\n\n\t\tnvram@7f0000 {\n\t\t\tlabel = \"nvram\";\n\t\t\treg = <0x7f0000 0x010000>;\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/bcm63xx/dts/bcm6358-pirelli-agpf-s0.dts",
    "content": "#include \"bcm6358.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"Pirelli Alice Gate AGPF-S0\";\n\tcompatible = \"pirelli,agpf-s0\", \"brcm,bcm6358\";\n\n\tchosen {\n\t\tbootargs = \"rootfstype=squashfs,jffs2 noinitrd console=ttyS0,115200\";\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tpoll-interval = <20>;\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&pinctrl 34 1>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&pinctrl 37 1>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tpower_green {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&pinctrl 4 1>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t\tpower_red {\n\t\t\tlabel = \"red:power\";\n\t\t\tgpios = <&pinctrl 5 1>;\n\t\t};\n\t\tservice_green {\n\t\t\tlabel = \"green:service\";\n\t\t\tgpios = <&pinctrl 6 1>;\n\t\t};\n\t\tservice_red {\n\t\t\tlabel = \"red:service\";\n\t\t\tgpios = <&pinctrl 7 1>;\n\t\t};\n\t\tdsl_green {\n\t\t\tlabel = \"green:adsl\";\n\t\t\tgpios = <&pinctrl 9 1>;\n\t\t};\n\t\tdsl_red {\n\t\t\tlabel = \"red:adsl\";\n\t\t\tgpios = <&pinctrl 10 1>;\n\t\t};\n\t\twifi_green {\n\t\t\tlabel = \"green:wifi\";\n\t\t\tgpios = <&pinctrl 22 1>;\n\t\t};\n\t\twifi_red {\n\t\t\tlabel = \"red:wifi\";\n\t\t\tgpios = <&pinctrl 23 1>;\n\t\t};\n\t\tinet_red {\n\t\t\tlabel = \"red:internet\";\n\t\t\tgpios = <&pinctrl 24 1>;\n\t\t};\n\t\tinet_green {\n\t\t\tlabel = \"green:internet\";\n\t\t\tgpios = <&pinctrl 25 1>;\n\t\t};\n\t\tusr1_green {\n\t\t\tlabel = \"green:usr1\";\n\t\t\tgpios = <&pinctrl 26 1>;\n\t\t};\n\t\tusr1_red {\n\t\t\tlabel = \"red:usr1\";\n\t\t\tgpios = <&pinctrl 27 1>;\n\t\t};\n\t\tusr2_green {\n\t\t\tlabel = \"green:usr2\";\n\t\t\tgpios = <&pinctrl 29 1>;\n\t\t};\n\t\tusr2_red {\n\t\t\tlabel = \"red:usr2\";\n\t\t\tgpios = <&pinctrl 30 1>;\n\t\t};\n\t};\n};\n\n&pflash {\n\tstatus = \"okay\";\n\n\tpartitions {\n\t\tcompatible = \"fixed-partitions\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tcfe@0 {\n\t\t\tlabel = \"CFE\";\n\t\t\treg = <0x000000 0x020000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tlinux@20000 {\n\t\t\tlabel = \"linux\";\n\t\t\treg = <0x020000 0xfc0000>;\n\t\t\tcompatible = \"brcm,bcm963xx-imagetag\";\n\t\t};\n\n\t\tnvram@fe0000 {\n\t\t\tlabel = \"nvram\";\n\t\t\treg = <0xfe0000 0x020000>;\n\t\t};\n\t};\n};\n\n&uart0 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/bcm63xx/dts/bcm6358-sfr-neufbox-4-foxconn-r1.dts",
    "content": "#include \"bcm6358-sfr-neufbox-4.dtsi\"\n\n/ {\n\tmodel = \"SFR Neufbox 4 (Foxconn)\";\n\tcompatible = \"sfr,neufbox-4-foxconn-r1\", \"brcm,bcm6358\";\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\ttraffic_white {\n\t\t\tlabel = \"white:traffic\";\n\t\t\tgpios = <&pinctrl 2 0>;\n\t\t};\n\t\tservice_blue {\n\t\t\tlabel = \"blue:service\";\n\t\t\tgpios = <&pinctrl 4 0>;\n\t\t};\n\t\twifi_white {\n\t\t\tlabel = \"white:wifi\";\n\t\t\tgpios = <&pinctrl 15 0>;\n\t\t};\n\t\tservice_red {\n\t\t\tlabel = \"red:service\";\n\t\t\tgpios = <&pinctrl 29 0>;\n\t\t};\n\t\tservice_green {\n\t\t\tlabel = \"green:service\";\n\t\t\tgpios = <&pinctrl 30 0>;\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/bcm63xx/dts/bcm6358-sfr-neufbox-4-sercomm-r0.dts",
    "content": "#include \"bcm6358-sfr-neufbox-4.dtsi\"\n\n/ {\n\tmodel = \"SFR Neufbox 4 (Sercomm)\";\n\tcompatible = \"sfr,neufbox-4-sercomm-r0\", \"brcm,bcm6358\";\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\ttraffic_white {\n\t\t\tlabel = \"white:traffic\";\n\t\t\tgpios = <&pinctrl 2 1>;\n\t\t};\n\t\tservice_blue {\n\t\t\tlabel = \"blue:service\";\n\t\t\tgpios = <&pinctrl 4 1>;\n\t\t};\n\t\twifi_white {\n\t\t\tlabel = \"white:wifi\";\n\t\t\tgpios = <&pinctrl 15 1>;\n\t\t};\n\t\tservice_red {\n\t\t\tlabel = \"red:service\";\n\t\t\tgpios = <&pinctrl 29 1>;\n\t\t};\n\t\tservice_green {\n\t\t\tlabel = \"green:service\";\n\t\t\tgpios = <&pinctrl 30 1>;\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/bcm63xx/dts/bcm6358-sfr-neufbox-4.dtsi",
    "content": "#include \"bcm6358.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tchosen {\n\t\tbootargs = \"rootfstype=squashfs,jffs2 noinitrd console=ttyS0,115200\";\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tpoll-interval = <20>;\n\n\t\tservice {\n\t\t\tlabel = \"service\";\n\t\t\tgpios = <&pinctrl 27 1>;\n\t\t\tlinux,code = <BTN_0>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\tclip {\n\t\t\tlabel = \"clip\";\n\t\t\tgpios = <&pinctrl 31 1>;\n\t\t\tlinux,code = <BTN_1>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&pinctrl 34 1>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&pinctrl 37 1>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n};\n\n&leds {\n\tstatus = \"okay\";\n\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_serial_led>;\n\n\tled@0 {\n\t\treg = <0>;\n\t\tactive-low;\n\t\tlabel = \"white:alarm\";\n\t};\n\n\tled@2 {\n\t\treg = <2>;\n\t\tactive-low;\n\t\tlabel = \"white:tv\";\n\t};\n\n\tled@3 {\n\t\treg = <3>;\n\t\tactive-low;\n\t\tlabel = \"white:tel\";\n\t};\n\n\tled@4 {\n\t\treg = <4>;\n\t\tactive-low;\n\t\tlabel = \"white:adsl\";\n\t};\n};\n\n&pflash {\n\tstatus = \"okay\";\n\n\tpartitions {\n\t\tcompatible = \"brcm,bcm963xx-cfe-nor-partitions\";\n\t};\n};\n\n&uart0 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/bcm63xx/dts/bcm6358-t-com-speedport-w-303v.dts",
    "content": "#include \"bcm6358.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"T-Com Speedport W 303V\";\n\tcompatible = \"t-com,speedport-w-303v\", \"brcm,bcm6358\";\n\n\taliases {\n\t\tled-boot = &led_power_adsl_green;\n\t\tled-failsafe = &led_power_adsl_green;\n\t\tled-running = &led_power_adsl_green;\n\t\tled-upgrade = &led_power_adsl_green;\n\t};\n\n\tchosen {\n\t\tbootargs = \"rootfstype=squashfs,jffs2 noinitrd console=ttyS0,115200\";\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&pinctrl 11 0>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\tses {\n\t\t\tlabel = \"ses\";\n\t\t\tgpios = <&pinctrl 37 1>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tses_green {\n\t\t\tlabel = \"green:ses\";\n\t\t\tgpios = <&pinctrl 0 1>;\n\t\t};\n\t\tpower_adsl_red {\n\t\t\tlabel = \"red:power+adsl\";\n\t\t\tgpios = <&pinctrl 2 1>;\n\t\t};\n\t\tppp_green {\n\t\t\tlabel = \"green:ppp\";\n\t\t\tgpios = <&pinctrl 5 1>;\n\t\t};\n\t\tled_power_adsl_green: power_adsl_green {\n\t\t\tlabel = \"green:power+adsl\";\n\t\t\tgpios = <&pinctrl 22 1>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t\tvoip_green {\n\t\t\tlabel = \"green:voip\";\n\t\t\tgpios = <&pinctrl 27 1>;\n\t\t};\n\t\tpots_green {\n\t\t\tlabel = \"green:pots\";\n\t\t\tgpios = <&pinctrl 31 1>;\n\t\t};\n\t};\n};\n\n&pflash {\n\tstatus = \"okay\";\n\n\tpartitions {\n\t\tcompatible = \"fixed-partitions\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tcfe@0 {\n\t\t\tlabel = \"CFE\";\n\t\t\treg = <0x000000 0x010000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tlinux@10000 {\n\t\t\tlabel = \"linux\";\n\t\t\treg = <0x010000 0x7e0000>;\n\t\t\tcompatible = \"brcm,bcm963xx-imagetag\";\n\t\t};\n\n\t\tnvram@7f0000 {\n\t\t\tlabel = \"nvram\";\n\t\t\treg = <0x7f0000 0x010000>;\n\t\t};\n\t};\n};\n\n&uart0 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/bcm63xx/dts/bcm6358-telsey-cpva642.dts",
    "content": "#include \"bcm6358.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"Telsey CPVA642-type (CPA-ZNTE60T)\";\n\tcompatible = \"telsey,cpva642\", \"brcm,bcm6358\";\n\n\taliases {\n\t\tled-boot = &led_power_green;\n\t\tled-failsafe = &led_power_green;\n\t\tled-running = &led_power_green;\n\t\tled-upgrade = &led_power_green;\n\t};\n\n\tchosen {\n\t\tbootargs = \"rootfstype=squashfs,jffs2 noinitrd console=ttyS0,115200\";\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&pinctrl 36 1>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&pinctrl 37 0>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\teth_green {\n\t\t\tlabel = \"green:ether\";\n\t\t\tgpios = <&pinctrl 1 1>;\n\t\t};\n\t\tphone2_green {\n\t\t\tlabel = \"green:phone2\";\n\t\t\tgpios = <&pinctrl 2 1>;\n\t\t};\n\t\tusb_green {\n\t\t\tlabel = \"green:usb\";\n\t\t\tgpios = <&pinctrl 3 1>;\n\t\t};\n\t\tphone1_green {\n\t\t\tlabel = \"green:phone1\";\n\t\t\tgpios = <&pinctrl 4 1>;\n\t\t};\n\t\twifi_red {\n\t\t\tlabel = \"red:wifi\";\n\t\t\tgpios = <&pinctrl 6 1>;\n\t\t};\n\t\tlink_red {\n\t\t\tlabel = \"red:link\";\n\t\t\tgpios = <&pinctrl 9 1>;\n\t\t};\n\t\tlink_green {\n\t\t\tlabel = \"green:link\";\n\t\t\tgpios = <&pinctrl 10 1>;\n\t\t};\n\t\tled_power_green: power_green {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&pinctrl 11 1>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t\tpower_red {\n\t\t\tlabel = \"red:power\";\n\t\t\tgpios = <&pinctrl 14 1>;\n\t\t};\n\t\twifi_green {\n\t\t\tlabel = \"green:wifi\";\n\t\t\tgpios = <&pinctrl 28 0>;\n\t\t};\n\t};\n};\n\n&pflash {\n\tstatus = \"okay\";\n\n\tpartitions {\n\t\tcompatible = \"fixed-partitions\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tcfe@0 {\n\t\t\tlabel = \"CFE\";\n\t\t\treg = <0x000000 0x010000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tlinux@10000 {\n\t\t\tlabel = \"linux\";\n\t\t\treg = <0x010000 0x7e0000>;\n\t\t\tcompatible = \"brcm,bcm963xx-imagetag\";\n\t\t};\n\n\t\tnvram@7f0000 {\n\t\t\tlabel = \"nvram\";\n\t\t\treg = <0x7f0000 0x010000>;\n\t\t};\n\t};\n};\n\n&uart0 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/bcm63xx/dts/bcm6358.dtsi",
    "content": "/dts-v1/;\n\n/ {\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\tcompatible = \"brcm,bcm6358\";\n\n\taliases {\n\t\tpflash = &pflash;\n\t\tpinctrl = &pinctrl;\n\t\tserial0 = &uart0;\n\t\tserial1 = &uart1;\n\t\tspi0 = &lsspi;\n\t};\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu@0 {\n\t\t\tcompatible = \"brcm,bmips4350\", \"mips,mips4Kc\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\treg = <0>;\n\t\t};\n\n\t\tcpu@1 {\n\t\t\tcompatible = \"brcm,bmips4350\", \"mips,mips4Kc\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\treg = <1>;\n\t\t};\n\t};\n\n\tcpu_intc: interrupt-controller {\n\t\t#address-cells = <0>;\n\t\tcompatible = \"mti,cpu-interrupt-controller\";\n\n\t\tinterrupt-controller;\n\t\t#interrupt-cells = <1>;\n\t};\n\n\tmemory { device_type = \"memory\"; reg = <0 0>; };\n\n\tpflash: nor@1e000000 {\n\t\tcompatible = \"cfi-flash\";\n\t\treg = <0x1e000000 0x2000000>;\n\t\tbank-width = <2>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tstatus = \"disabled\";\n\t};\n\n\tubus@fff00000 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tranges;\n\t\tcompatible = \"simple-bus\";\n\t\tinterrupt-parent = <&periph_intc>;\n\n\t\tperiph_intc: interrupt-controller@fffe000c {\n\t\t\tcompatible = \"brcm,bcm6345-l1-intc\";\n\t\t\treg = <0xfffe000c 0x8>,\n\t\t\t      <0xfffe0038 0x8>;\n\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <1>;\n\n\t\t\tinterrupt-parent = <&cpu_intc>;\n\t\t\tinterrupts = <2>, <3>;\n\t\t};\n\n\t\text_intc0: interrupt-controller@fffe0014 {\n\t\t\tcompatible = \"brcm,bcm6345-ext-intc\";\n\t\t\treg = <0xfffe0014 0x4>;\n\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <2>;\n\n\t\t\tinterrupts = <25>, <26>, <27>, <28>;\n\t\t};\n\n\t\text_intc1: interrupt-controller@fffe001c {\n\t\t\tcompatible = \"brcm,bcm6345-ext-intc\";\n\t\t\treg = <0xfffe001c 0x4>;\n\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <2>;\n\n\t\t\tinterrupts = <20>, <21>;\n\t\t};\n\n\t\tpinctrl: pin-controller@fffe0080 {\n\t\t\tcompatible = \"brcm,bcm6358-pinctrl\";\n\t\t\treg = <0xfffe0080 0x8>,\n\t\t\t      <0xfffe0088 0x8>;\n\t\t\treg-names = \"dirout\", \"dat\", \"mode\";\n\t\t\tbrcm,gpiomode = <&gpiomode>;\n\n\t\t\tgpio-controller;\n\t\t\t#gpio-cells = <2>;\n\n\t\t\tinterrupts-extended = <&ext_intc1 0 0>,\n\t\t\t\t\t      <&ext_intc1 1 0>,\n\t\t\t\t\t      <&ext_intc0 0 0>,\n\t\t\t\t\t      <&ext_intc0 1 0>,\n\t\t\t\t\t      <&ext_intc0 2 0>,\n\t\t\t\t\t      <&ext_intc0 3 0>;\n\t\t\tinterrupt-names = \"gpio32\", \"gpio33\", \"gpio34\", \"gpio35\",\n\t\t\t\t\t  \"gpio36\", \"gpio37\";\n\n\t\t\tpinctrl_ebi_cs: ebi_cs {\n\t\t\t\tfunction = \"ebi_cs\";\n\t\t\t\tgroups = \"ebi_cs_grp\";\n\t\t\t};\n\n\t\t\tpinctrl_uart1: uart1 {\n\t\t\t\tfunction = \"uart1\";\n\t\t\t\tgroups = \"uart1_grp\";\n\t\t\t};\n\n\t\t\tpinctrl_serial_led: serial_led {\n\t\t\t\tfunction = \"serial_led\";\n\t\t\t\tgroups = \"serial_led_grp\";\n\t\t\t};\n\n\t\t\tpinctrl_legacy_led: legacy_led {\n\t\t\t\tfunction = \"legacy_led\";\n\t\t\t\tgroups = \"legacy_led_grp\";\n\t\t\t};\n\n\t\t\tpinctrl_led: led {\n\t\t\t\tfunction = \"led\";\n\t\t\t\tgroups = \"led_grp\";\n\t\t\t};\n\n\t\t\tpinctrl_spi_cs_23: spi_cs {\n\t\t\t\tfunction = \"spi_cs\";\n\t\t\t\tgroups = \"spi_cs_grp\";\n\t\t\t};\n\n\t\t\tpinctrl_utopia: utopia {\n\t\t\t\tfunction = \"utopia\";\n\t\t\t\tgroups = \"utopia_grp\";\n\t\t\t};\n\n\t\t\tpinctrl_pwm_syn_clk: pwm_syn_clk {\n\t\t\t\tfunction = \"pwm_syn_clk\";\n\t\t\t\tgroups = \"pwm_syn_clk_grp\";\n\t\t\t};\n\n\t\t\tpinctrl_sys_irq: sys_irq {\n\t\t\t\tfunction = \"sys_irq\";\n\t\t\t\tgroups = \"sys_irq_grp\";\n\t\t\t};\n\t\t};\n\n\t\tgpiomode: gpiomode@fffe0098 {\n\t\t\tcompatible = \"brcm,bcm6358-gpiomode\", \"syscon\";\n\t\t\treg = <0xfffe0098 0x4>;\n\t\t};\n\n\t\tleds: led-controller@fffe00d0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tcompatible = \"brcm,bcm6358-leds\";\n\t\t\treg = <0xfffe00d0 0x8>;\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tuart0: serial@fffe0100 {\n\t\t\tcompatible = \"brcm,bcm6345-uart\";\n\t\t\treg = <0xfffe0100 0x18>;\n\n\t\t\tinterrupt-parent = <&periph_intc>;\n\t\t\tinterrupts = <2>;\n\n\t\t\t/* clocks = <&periph_clk>; */\n\t\t\t/* clock-names = \"refclk\"; */\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tuart1: serial@fffe0120 {\n\t\t\tcompatible = \"brcm,bcm6345-uart\";\n\t\t\treg = <0xfffe0120 0x18>;\n\n\t\t\tinterrupt-parent = <&periph_intc>;\n\t\t\tinterrupts = <3>;\n\n\t\t\t/* clocks = <&periph_clk>; */\n\t\t\t/* clock-names = \"refclk\"; */\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tlsspi: spi@fffe0800 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tcompatible = \"brcm,bcm6358-spi\";\n\t\t\treg = <0xfffe0800 0x70c>;\n\t\t\tinterrupts = <1>;\n\t\t\t/* clocks = <&clkctl 9>; */\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/bcm63xx/dts/bcm6359-huawei-echolife-hg520v.dts",
    "content": "#include \"bcm6358.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"Huawei EchoLife HG520v\";\n\tcompatible = \"huawei,echolife-hg520v\", \"brcm,bcm6359\", \"brcm,bcm6358\";\n\n\taliases {\n\t\tled-boot = &led_inet_green;\n\t\tled-failsafe = &led_inet_green;\n\t\tled-running = &led_inet_green;\n\t\tled-upgrade = &led_inet_green;\n\t};\n\n\tchosen {\n\t\tbootargs = \"rootfstype=squashfs,jffs2 noinitrd console=ttyS0,115200\";\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&pinctrl 37 1>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_inet_green: inet_green {\n\t\t\tlabel = \"green:net\";\n\t\t\tgpios = <&pinctrl 32 1>;\n\t\t};\n\t};\n};\n\n&pflash {\n\tstatus = \"okay\";\n\n\tpartitions {\n\t\tcompatible = \"fixed-partitions\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tcfe@0 {\n\t\t\tlabel = \"CFE\";\n\t\t\treg = <0x000000 0x010000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tlinux@10000 {\n\t\t\tlabel = \"linux\";\n\t\t\treg = <0x010000 0x3e0000>;\n\t\t\tcompatible = \"brcm,bcm963xx-imagetag\";\n\t\t};\n\n\t\tnvram@3f0000 {\n\t\t\tlabel = \"nvram\";\n\t\t\treg = <0x3f0000 0x010000>;\n\t\t};\n\t};\n};\n\n&uart0 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/bcm63xx/dts/bcm6361-sfr-neufbox-6-sercomm-r0.dts",
    "content": "#include \"bcm6362.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"SFR Neufbox 6 (Sercomm)\";\n\tcompatible = \"sfr,neufbox-6-sercomm-r0\", \"brcm,bcm6361\", \"brcm,bcm6362\";\n\n\tchosen {\n\t\tbootargs = \"rootfstype=squashfs,jffs2 noinitrd console=ttyS0,115200\";\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tpoll-interval = <20>;\n\n\t\tservice {\n\t\t\tlabel = \"service\";\n\t\t\tgpios = <&pinctrl 10 1>;\n\t\t\tlinux,code = <BTN_0>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\twlan {\n\t\t\tlabel = \"wlan\";\n\t\t\tgpios = <&pinctrl 12 1>;\n\t\t\tlinux,code = <KEY_WLAN>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&pinctrl 24 1>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&pinctrl 25 1>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tswitch {\n\t\tcompatible = \"realtek,rtl8367\";\n\t\tgpio-sda = <&pinctrl 18 0>;\n\t\tgpio-sck = <&pinctrl 20 0>;\n\n\t\trealtek,extif0 = <1 5 1 1 1 1 1 1 2>;\n\t};\n};\n\n&hsspi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\tspi-max-frequency = <20000000>;\n\t\tspi-tx-bus-width = <2>;\n\t\tspi-rx-bus-width = <2>;\n\t\treg = <0>;\n\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tcfe@0 {\n\t\t\t\treg = <0x000000 0x010000>;\n\t\t\t\tlabel = \"cfe\";\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tlinux@10000 {\n\t\t\t\treg = <0x010000 0xfe0000>;\n\t\t\t\tlabel = \"linux\";\n\t\t\t\tcompatible = \"brcm,bcm963xx-imagetag\";\n\t\t\t};\n\n\t\t\tnvram@ff0000 {\n\t\t\t\treg = <0xff0000 0x010000>;\n\t\t\t\tlabel = \"nvram\";\n\t\t\t};\n\t\t};\n\t};\n};\n\n&uart0 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/bcm63xx/dts/bcm6362-huawei-hg253s-v2.dts",
    "content": "#include \"bcm6362.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"Huawei HG253s v2\";\n\tcompatible = \"huawei,hg253s-v2\", \"brcm,bcm6362\";\n\n\taliases {\n\t\tled-boot = &led_phone_green;\n\t\tled-failsafe = &led_phone_green;\n\t\tled-upgrade = &led_phone_green;\n\t};\n\n\tchosen {\n\t\tbootargs = \"rootfstype=squashfs,ubifs noinitrd console=ttyS0,115200\";\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&pinctrl 24 1>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\twlan {\n\t\t\tlabel = \"wlan\";\n\t\t\tgpios = <&pinctrl 25 1>;\n\t\t\tlinux,code = <KEY_WLAN>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&pinctrl 26 1>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_phone_green: led@28 {\n\t\t\tlabel = \"green:phone\";\n\t\t\tgpios = <&pinctrl 28 1>;\n\t\t};\n\n\t\tled@30 {\n\t\t\tlabel = \"green:usb\";\n\t\t\tgpios = <&pinctrl 30 1>;\n\t\t};\n\t};\n};\n\n&leds {\n\tstatus = \"okay\";\n\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_leds>;\n\n\tled@3 {\n\t\treg = <3>;\n\t\tactive-low;\n\t\tlabel = \"green:internet\";\n\t};\n\n\tled@5 {\n\t\treg = <5>;\n\t\tactive-low;\n\t\tlabel = \"green:wifi\";\n\t};\n};\n\n&lsspi {\n\tswitch@0 {\n\t\tcompatible = \"brcm,bcm53125\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <781000>;\n\n\t\tlede,alias = \"eth0\";\n\n\t\tports {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\n\t\t\tlan@1 {\n\t\t\t\treg = <1>;\n\t\t\t\tlabel = \"lan4\";\n\t\t\t};\n\n\t\t\tlan@2 {\n\t\t\t\treg = <2>;\n\t\t\t\tlabel = \"lan3\";\n\t\t\t};\n\n\t\t\tlan@3 {\n\t\t\t\treg = <3>;\n\t\t\t\tlabel = \"lan2\";\n\t\t\t};\n\n\t\t\tlan@4 {\n\t\t\t\treg = <4>;\n\t\t\t\tlabel = \"lan1\";\n\t\t\t};\n\n\t\t\tcpu@8 {\n\t\t\t\treg = <8>;\n\t\t\t\tlabel = \"cpu\";\n\n\t\t\t\tfixed-link {\n\t\t\t\t\tspeed = <1000>;\n\t\t\t\t\tfull-duplex;\n\t\t\t\t\tasym-pause;\n\t\t\t\t\tpause;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t};\n};\n\n&nflash {\n\tstatus = \"okay\";\n\n\tnandcs@0 {\n\t\tcompatible = \"brcm,nandcs\";\n\t\t#size-cells = <1>;\n\t\t#address-cells = <1>;\n\t\treg = <0>;\n\t\tnand-ecc-step-size = <512>;\n\t\tnand-ecc-strength = <15>;\n\t\tnand-on-flash-bbt;\n\t\tbrcm,nand-oob-sector-size = <64>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"cferom\";\n\t\t\t\treg = <0x0000000 0x0020000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tcompatible = \"brcm,wfi\";\n\t\t\t\tlabel = \"wfi\";\n\t\t\t\treg = <0x0020000 0x7d80000>;\n\t\t\t};\n\n\t\t\tpartition@7da0000 {\n\t\t\t\tlabel = \"nvram\";\n\t\t\t\treg = <0x7da0000 0x160000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pinctrl {\n\tpinctrl_leds: leds {\n\t\tfunction = \"led\";\n\t\tpins = \"gpio3\", \"gpio5\";\n\t};\n};\n\n&uart0 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/bcm63xx/dts/bcm6362-netgear-dgnd3700-v2.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later\n\n#include \"bcm6362.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"Netgear DGND3700v2\";\n\tcompatible = \"netgear,dgnd3700-v2\", \"brcm,bcm6362\";\n\n\taliases {\n\t\tled-boot = &led_power_green;\n\t\tled-failsafe = &led_power_green;\n\t\tled-running = &led_power_green;\n\t\tled-upgrade = &led_power_green;\n\t};\n\n\tchosen {\n\t\tbootargs = \"rootfstype=squashfs,ubifs noinitrd console=ttyS0,115200\";\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&pinctrl 24 1>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\twlan {\n\t\t\tlabel = \"wlan\";\n\t\t\tgpios = <&pinctrl 25 1>;\n\t\t\tlinux,code = <KEY_WLAN>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&pinctrl 26 1>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled@28 {\n\t\t\tlabel = \"green:dsl\";\n\t\t\tgpios = <&pinctrl 28 1>;\n\t\t};\n\n\t\tled@34 {\n\t\t\tlabel = \"red:power\";\n\t\t\tgpios = <&pinctrl 34 1>;\n\t\t};\n\t};\n};\n\n&leds {\n\tstatus = \"okay\";\n\tbrcm,serial-leds;\n\tbrcm,serial-dat-low;\n\tbrcm,serial-shift-inv;\n\tbrcm,serial-mux;\n\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_leds &pinctrl_serial_led>;\n\n\tled@1 {\n\t\treg = <1>;\n\t\tactive-low;\n\t\tlabel = \"green:internet\";\n\t};\n\n\tled_power_green: led@8 {\n\t\treg = <8>;\n\t\tlabel = \"green:power\";\n\t\tdefault-state = \"on\";\n\t};\n\n\tled@9 {\n\t\treg = <9>;\n\t\tactive-low;\n\t\tlabel = \"green:wps\";\n\t};\n\n\tled@10 {\n\t\treg = <10>;\n\t\tactive-low;\n\t\tlabel = \"green:usb1\";\n\t};\n\n\tled@11 {\n\t\treg = <11>;\n\t\tactive-low;\n\t\tlabel = \"green:usb2\";\n\t};\n\n\tled@12 {\n\t\treg = <12>;\n\t\tactive-low;\n\t\tlabel = \"amber:internet\";\n\t};\n\n\tled@13 {\n\t\treg = <13>;\n\t\tactive-low;\n\t\tlabel = \"green:ethernet\";\n\t};\n\n\tled@14 {\n\t\treg = <14>;\n\t\tactive-low;\n\t\tlabel = \"amber:dsl\";\n\t};\n\n\tled@16 {\n\t\treg = <16>;\n\t\tactive-low;\n\t\tlabel = \"amber:usb1\";\n\t};\n\n\tled@17 {\n\t\treg = <17>;\n\t\tactive-low;\n\t\tlabel = \"amber:usb2\";\n\t};\n\n\tled@18 {\n\t\treg = <18>;\n\t\tactive-low;\n\t\tlabel = \"amber:ethernet\";\n\t};\n};\n\n&nflash {\n\tstatus = \"okay\";\n\n\tnandcs@0 {\n\t\tcompatible = \"brcm,nandcs\";\n\t\t#size-cells = <1>;\n\t\t#address-cells = <1>;\n\t\treg = <0>;\n\t\tnand-ecc-step-size = <512>;\n\t\tnand-ecc-strength = <15>;\n\t\tnand-on-flash-bbt;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"cferom\";\n\t\t\t\treg = <0x0000000 0x0004000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@4000 {\n\t\t\t\tcompatible = \"brcm,wfi\";\n\t\t\t\tlabel = \"wfi\";\n\t\t\t\treg = <0x0004000 0x1c7c000>;\n\t\t\t};\n\n\t\t\tpartition@1c80000 {\n\t\t\t\tlabel = \"flag\";\n\t\t\t\treg = <0x1c80000 0x0040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@1cc0000 {\n\t\t\t\tlabel = \"pcbasn\";\n\t\t\t\treg = <0x1cc0000 0x0040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@1d00000 {\n\t\t\t\tlabel = \"xxx\";\n\t\t\t\treg = <0x1d00000 0x0080000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@1d80000 {\n\t\t\t\tlabel = \"language_dev\";\n\t\t\t\treg = <0x1d80000 0x0040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@1dc0000 {\n\t\t\t\tlabel = \"scnvram\";\n\t\t\t\treg = <0x1dc0000 0x0100000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pinctrl {\n\tpinctrl_leds: leds {\n\t\tfunction = \"led\";\n\t\tpins = \"gpio1\";\n\t};\n};\n\n&uart0 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/bcm63xx/dts/bcm6362-sagem-fast-2504n.dts",
    "content": "#include \"bcm6362.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"Sagem F@st 2504N\";\n\tcompatible = \"sagem,fast-2504n\", \"brcm,bcm6362\";\n\n\taliases {\n\t\tled-boot = &led_ok_green;\n\t\tled-failsafe = &led_ok_green;\n\t\tled-running = &led_ok_green;\n\t\tled-upgrade = &led_ok_green;\n\t};\n\n\tchosen {\n\t\tbootargs = \"rootfstype=squashfs,jffs2 noinitrd console=ttyS0,115200\";\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&pinctrl 24 1>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&pinctrl 25 1>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tpower_orange {\n\t\t\tlabel = \"orange:power\";\n\t\t\tgpios = <&pinctrl 2 1>;\n\t\t};\n\t\tpower_green {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&pinctrl 10 1>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t\tinet_red {\n\t\t\tlabel = \"red:internet\";\n\t\t\tgpios = <&pinctrl 26 1>;\n\t\t};\n\t\tled_ok_green: ok_green {\n\t\t\tlabel = \"green:ok\";\n\t\t\tgpios = <&pinctrl 28 1>;\n\t\t};\n\t\tok_orange {\n\t\t\tlabel = \"orange:ok\";\n\t\t\tgpios = <&pinctrl 29 1>;\n\t\t};\n\t\twlan_orangee {\n\t\t\tlabel = \"orange:wlan\";\n\t\t\tgpios = <&pinctrl 30 1>;\n\t\t};\n\t};\n};\n\n&hsspi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\tspi-max-frequency = <20000000>;\n\t\tspi-tx-bus-width = <2>;\n\t\tspi-rx-bus-width = <2>;\n\t\treg = <0>;\n\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tcfe@0 {\n\t\t\t\treg = <0x000000 0x010000>;\n\t\t\t\tlabel = \"cfe\";\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tlinux@10000 {\n\t\t\t\treg = <0x010000 0x7e0000>;\n\t\t\t\tlabel = \"linux\";\n\t\t\t\tcompatible = \"brcm,bcm963xx-imagetag\";\n\t\t\t};\n\n\t\t\tnvram@7f0000 {\n\t\t\t\treg = <0x7f0000 0x010000>;\n\t\t\t\tlabel = \"nvram\";\n\t\t\t};\n\t\t};\n\t};\n};\n\n&uart0 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/bcm63xx/dts/bcm6362.dtsi",
    "content": "/dts-v1/;\n\n/ {\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\tcompatible = \"brcm,bcm6362\";\n\n\taliases {\n\t\tnflash = &nflash;\n\t\tpinctrl = &pinctrl;\n\t\tserial0 = &uart0;\n\t\tserial1 = &uart1;\n\t\tspi0 = &lsspi;\n\t\tspi1 = &hsspi;\n\t};\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu@0 {\n\t\t\tcompatible = \"brcm,bmips4350\", \"mips,mips4Kc\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\treg = <0>;\n\t\t};\n\n\t\tcpu@1 {\n\t\t\tcompatible = \"brcm,bmips4350\", \"mips,mips4Kc\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\treg = <1>;\n\t\t};\n\t};\n\n\tcpu_intc: interrupt-controller {\n\t\t#address-cells = <0>;\n\t\tcompatible = \"mti,cpu-interrupt-controller\";\n\n\t\tinterrupt-controller;\n\t\t#interrupt-cells = <1>;\n\t};\n\n\tmemory { device_type = \"memory\"; reg = <0 0>; };\n\n\tubus@10000000 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tranges;\n\t\tcompatible = \"simple-bus\";\n\t\tinterrupt-parent = <&periph_intc>;\n\n\t\text_intc: interrupt-controller@10000018 {\n\t\t\tcompatible = \"brcm,bcm6345-ext-intc\";\n\t\t\treg = <0x10000018 0x4>;\n\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <2>;\n\n\t\t\tinterrupts = <40>, <41>, <42>, <43>;\n\t\t};\n\n\t\tperiph_intc: interrupt-controller@10000020 {\n\t\t\tcompatible = \"brcm,bcm6345-l1-intc\";\n\t\t\treg = <0x10000020 0x10>,\n\t\t\t      <0x10000030 0x10>;\n\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <1>;\n\n\t\t\tinterrupt-parent = <&cpu_intc>;\n\t\t\tinterrupts = <2>, <3>;\n\t\t};\n\n\t\tpinctrl: pin-controller@10000080 {\n\t\t\tcompatible = \"brcm,bcm6362-pinctrl\";\n\t\t\treg = <0x10000080 0x8>,\n\t\t\t      <0x10000088 0x8>,\n\t\t\t      <0x10000090 0x4>,\n\t\t\t      <0x10000098 0x4>,\n\t\t\t      <0x1000009c 0x4>,\n\t\t\t      <0x100000b8 0x4>;\n\t\t\treg-names = \"dirout\", \"dat\", \"led\",\n\t\t\t\t    \"mode\", \"ctrl\", \"basemode\";\n\n\t\t\tgpio-controller;\n\t\t\t#gpio-cells = <2>;\n\n\t\t\tinterrupt-parent = <&ext_intc>;\n\t\t\tinterrupts = <0 0>, <1 0>, <2 0>, <3 0>;\n\t\t\tinterrupt-names = \"gpio24\", \"gpio25\",\n\t\t\t\t\t  \"gpio26\", \"gpio27\";\n\n\t\t\tpinctrl_usb_device_led: usb_device_led {\n\t\t\t\tfunction = \"usb_device_led\";\n\t\t\t\tpins = \"gpio0\";\n\t\t\t};\n\n\t\t\tpinctrl_sys_irq: sys_irq {\n\t\t\t\tfunction = \"sys_irq\";\n\t\t\t\tpins = \"gpio1\";\n\t\t\t};\n\n\t\t\tpinctrl_serial_led: serial_led {\n\t\t\t\tpinctrl_serial_led_clk: serial_led_clk {\n\t\t\t\t\tfunction = \"serial_led_clk\";\n\t\t\t\t\tpins = \"gpio2\";\n\t\t\t\t};\n\n\t\t\t\tpinctrl_serial_led_data: serial_led_data {\n\t\t\t\t\tfunction = \"serial_led_data\";\n\t\t\t\t\tpins = \"gpio3\";\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tpinctrl_robosw_led_data: robosw_led_data {\n\t\t\t\tfunction = \"robosw_led_data\";\n\t\t\t\tpins = \"gpio4\";\n\t\t\t};\n\n\t\t\tpinctrl_robosw_led_clk: robosw_led_clk {\n\t\t\t\tfunction = \"robosw_led_clk\";\n\t\t\t\tpins = \"gpio5\";\n\t\t\t};\n\n\t\t\tpinctrl_robosw_led0: robosw_led0 {\n\t\t\t\tfunction = \"robosw_led0\";\n\t\t\t\tpins = \"gpio6\";\n\t\t\t};\n\n\t\t\tpinctrl_robosw_led1: robosw_led1 {\n\t\t\t\tfunction = \"robosw_led1\";\n\t\t\t\tpins = \"gpio7\";\n\t\t\t};\n\n\t\t\tpinctrl_inet_led: inet_led {\n\t\t\t\tfunction = \"inet_led\";\n\t\t\t\tpins = \"gpio8\";\n\t\t\t};\n\n\t\t\tpinctrl_spi_cs2: spi_cs2 {\n\t\t\t\tfunction = \"spi_cs2\";\n\t\t\t\tpins = \"gpio9\";\n\t\t\t};\n\n\t\t\tpinctrl_spi_cs3: spi_cs3 {\n\t\t\t\tfunction = \"spi_cs3\";\n\t\t\t\tpins = \"gpio10\";\n\t\t\t};\n\n\t\t\tpinctrl_ntr_pulse: ntr_pulse {\n\t\t\t\tfunction = \"ntr_pulse\";\n\t\t\t\tpins = \"gpio11\";\n\t\t\t};\n\n\t\t\tpinctrl_uart1_scts: uart1_scts {\n\t\t\t\tfunction = \"uart1_scts\";\n\t\t\t\tpins = \"gpio12\";\n\t\t\t};\n\n\t\t\tpinctrl_uart1_srts: uart1_srts {\n\t\t\t\tfunction = \"uart1_srts\";\n\t\t\t\tpins = \"gpio13\";\n\t\t\t};\n\n\n\t\t\tpinctrl_uart1: uart1 {\n\t\t\t\tpinctrl_uart1_sdin: uart1_sdin {\n\t\t\t\t\tfunction = \"uart1_sdin\";\n\t\t\t\t\tpins = \"gpio14\";\n\t\t\t\t};\n\n\t\t\t\tpinctrl_uart1_sdout: uart1_sdout {\n\t\t\t\t\tfunction = \"uart1_sdout\";\n\t\t\t\t\tpins = \"gpio15\";\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tpinctrl_adsl_spi: adsl_spi {\n\t\t\t\tpinctrl_adsl_spi_miso: adsl_spi_miso {\n\t\t\t\t\tfunction = \"adsl_spi_miso\";\n\t\t\t\t\tpins = \"gpio16\";\n\t\t\t\t};\n\n\t\t\t\tpinctrl_adsl_spi_mosi: adsl_spi_mosi {\n\t\t\t\t\tfunction = \"adsl_spi_mosi\";\n\t\t\t\t\tpins = \"gpio17\";\n\t\t\t\t};\n\n\t\t\t\tpinctrl_adsl_spi_clk: adsl_spi_clk {\n\t\t\t\t\tfunction = \"adsl_spi_clk\";\n\t\t\t\t\tpins = \"gpio18\";\n\t\t\t\t};\n\n\t\t\t\tpinctrl_adsl_spi_cs: adsl_spi_cs {\n\t\t\t\t\tfunction = \"adsl_spi_cs\";\n\t\t\t\t\tpins = \"gpio19\";\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tpinctrl_ephy0_led: ephy0_led {\n\t\t\t\tfunction = \"ephy0_led\";\n\t\t\t\tpins = \"gpio20\";\n\t\t\t};\n\n\t\t\tpinctrl_ephy1_led: ephy1_led {\n\t\t\t\tfunction = \"ephy1_led\";\n\t\t\t\tpins = \"gpio21\";\n\t\t\t};\n\n\t\t\tpinctrl_ephy2_led: ephy2_led {\n\t\t\t\tfunction = \"ephy2_led\";\n\t\t\t\tpins = \"gpio22\";\n\t\t\t};\n\n\t\t\tpinctrl_ephy3_led: ephy3_led {\n\t\t\t\tfunction = \"ephy3_led\";\n\t\t\t\tpins = \"gpio23\";\n\t\t\t};\n\n\t\t\tpinctrl_ext_irq0: ext_irq0 {\n\t\t\t\tfunction = \"ext_irq0\";\n\t\t\t\tpins = \"gpio24\";\n\t\t\t};\n\n\t\t\tpinctrl_ext_irq1: ext_irq1 {\n\t\t\t\tfunction = \"ext_irq1\";\n\t\t\t\tpins = \"gpio25\";\n\t\t\t};\n\n\t\t\tpinctrl_ext_irq2: ext_irq2 {\n\t\t\t\tfunction = \"ext_irq2\";\n\t\t\t\tpins = \"gpio26\";\n\t\t\t};\n\n\t\t\tpinctrl_ext_irq3: ext_irq3 {\n\t\t\t\tfunction = \"ext_irq3\";\n\t\t\t\tpins = \"gpio27\";\n\t\t\t};\n\n\t\t\tpinctrl_nand: nand {\n\t\t\t\tfunction = \"nand\";\n\t\t\t\tgroup = \"nand_grp\";\n\t\t\t};\n\t\t};\n\n\t\tuart0: serial@10000100 {\n\t\t\tcompatible = \"brcm,bcm6345-uart\";\n\t\t\treg = <0x10000100 0x18>;\n\n\t\t\tinterrupt-parent = <&periph_intc>;\n\t\t\tinterrupts = <3>;\n\n\t\t\t/* clocks = <&periph_clk>; */\n\t\t\t/* clock-names = \"refclk\"; */\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tuart1: serial@10000120 {\n\t\t\tcompatible = \"brcm,bcm6345-uart\";\n\t\t\treg = <0x10000120 0x18>;\n\n\t\t\tinterrupt-parent = <&periph_intc>;\n\t\t\tinterrupts = <4>;\n\n\t\t\t/* clocks = <&periph_clk>; */\n\t\t\t/* clock-names = \"refclk\"; */\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tlsspi: spi@10000800 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tcompatible = \"brcm,bcm6358-spi\";\n\t\t\treg = <0x10000800 0x70c>;\n\t\t\tinterrupts = <2>;\n\t\t\t/* clocks = <&clkctl 15>; */\n\t\t};\n\n\t\thsspi: spi@10001000 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tcompatible = \"brcm,bcm6328-hsspi\";\n\t\t\treg = <0x10001000 0x600>;\n\t\t\tinterrupts = <5>;\n\t\t\t/* clocks = <&clkctl 16>; */\n\t\t};\n\n\t\tnflash: nand@10000200 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tcompatible = \"brcm,nand-bcm6368\",\n\t\t\t\t     \"brcm,brcmnand-v2.2\",\n\t\t\t\t     \"brcm,brcmnand\";\n\t\t\treg = <0x10000200 0x180>,\n\t\t\t      <0x10000600 0x200>,\n\t\t\t      <0x10000070 0x10>;\n\t\t\treg-names = \"nand\",\n\t\t\t\t    \"nand-cache\",\n\t\t\t\t    \"nand-int-base\";\n\n\t\t\tinterrupt-parent = <&periph_intc>;\n\t\t\tinterrupts = <12>;\n\n\t\t\t/* clocks = <&clkctl 20>; */\n\n\t\t\tpinctrl-names = \"default\";\n\t\t\tpinctrl-0 = <&pinctrl_nand>;\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tleds: led-controller@10001900 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tcompatible = \"brcm,bcm6328-leds\";\n\t\t\treg = <0x10001900 0x24>;\n\t\t\tstatus = \"disabled\";\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/bcm63xx/dts/bcm6368-actiontec-r1000h.dts",
    "content": "#include \"bcm6368.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"Actiontec R1000H\";\n\tcompatible = \"actiontec,r1000h\", \"brcm,bcm6368\";\n\n\taliases {\n\t\tled-boot = &led_power_green;\n\t\tled-failsafe = &led_power_green;\n\t\tled-running = &led_power_green;\n\t\tled-upgrade = &led_power_green;\n\t};\n\n\tchosen {\n\t\tbootargs = \"rootfstype=squashfs noinitrd console=ttyS0,115200\";\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&pinctrl 34 1>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&pinctrl 35 1>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tinet_green {\n\t\t\tlabel = \"green:inet\";\n\t\t\tgpios = <&pinctrl 5 0>;\n\t\t};\n\n\t\tusb_green {\n\t\t\tlabel = \"green:usb\";\n\t\t\tgpios = <&pinctrl 21 1>;\n\t\t};\n\n\t\tled_power_green: power_green {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&pinctrl 22 0>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\twps_green {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&pinctrl 23 1>;\n\t\t};\n\n\t\tpower_red {\n\t\t\tlabel = \"red:power\";\n\t\t\tgpios = <&pinctrl 24 0>;\n\t\t};\n\n\t\twps_red {\n\t\t\tlabel = \"red:wps\";\n\t\t\tgpios = <&pinctrl 30 1>;\n\t\t};\n\n\t\tinet_red {\n\t\t\tlabel = \"red:inet\";\n\t\t\tgpios = <&pinctrl 31 0>;\n\t\t};\n\t};\n};\n\n&pflash {\n\tstatus = \"okay\";\n\n\tpartitions {\n\t\tcompatible = \"fixed-partitions\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tCFE@0 {\n\t\t\treg = <0x000000 0x020000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tlinux@20000 {\n\t\t\treg = <0x020000 0x1fc0000>;\n\t\t\tcompatible = \"brcm,bcm963xx-imagetag\";\n\t\t};\n\n\t\tnvram@1fe0000 {\n\t\t\treg = <0x1fe0000 0x20000>;\n\t\t};\n\t};\n};\n\n&uart0 {\n\tstatus = \"okay\";\n};\n\n&uart1 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/bcm63xx/dts/bcm6368-adb-av4202n.dts",
    "content": "#include \"bcm6368.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"ADB P.DG AV4202N\";\n\tcompatible = \"adb,av4202n\", \"brcm,bcm6368\";\n\n\taliases {\n\t\tled-boot = &led_power_white;\n\t\tled-failsafe = &led_power_white;\n\t\tled-running = &led_power_white;\n\t\tled-upgrade = &led_power_white;\n\t};\n\n\tchosen {\n\t\tbootargs = \"rootfstype=squashfs,jffs2 noinitrd console=ttyS0,115200\";\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&pinctrl 34 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\twlan {\n\t\t\tlabel = \"wlan\";\n\t\t\tgpios = <&pinctrl 37 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WLAN>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power_white: power_white {\n\t\t\tlabel = \"white:power\";\n\t\t\tgpios = <&pinctrl 10 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t\tpower_red {\n\t\t\tlabel = \"red:power\";\n\t\t\tgpios = <&pinctrl 11 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\twan_white {\n\t\t\tlabel = \"white:wan\";\n\t\t\tgpios = <&pinctrl 26 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\twan_red {\n\t\t\tlabel = \"red:wan\";\n\t\t\tgpios = <&pinctrl 27 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tphone_white {\n\t\t\tlabel = \"white:phone\";\n\t\t\tgpios = <&pinctrl 24 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tphone_red {\n\t\t\tlabel = \"red:phone\";\n\t\t\tgpios = <&pinctrl 25 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\twifi {\n\t\t\tlabel = \"blue:wifi\";\n\t\t\tgpios = <&pinctrl 22 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&pflash {\n\tstatus = \"okay\";\n\n\tpartitions {\n\t\tcompatible = \"fixed-partitions\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tcfe@0 {\n\t\t\tlabel = \"CFE\";\n\t\t\treg = <0x000000 0x020000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tlinux@20000 {\n\t\t\tlabel = \"linux\";\n\t\t\treg = <0x020000 0xfc0000>;\n\t\t\tcompatible = \"brcm,bcm963xx-imagetag\";\n\t\t};\n\n\t\tnvram@fe0000 {\n\t\t\tlabel = \"nvram\";\n\t\t\treg = <0xfe0000 0x020000>;\n\t\t};\n\t};\n};\n\n&pinctrl {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_pci>;\n};\n\n&uart0 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/bcm63xx/dts/bcm6368-brcm-bcm96368mvngr.dts",
    "content": "#include \"bcm6368.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"Broadcom BCM96368MVNgr reference board\";\n\tcompatible = \"brcm,bcm96368mvngr\", \"brcm,bcm6368\";\n\n\tchosen {\n\t\tbootargs = \"rootfstype=squashfs,jffs2 noinitrd console=ttyS0,115200\";\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tdsl_green {\n\t\t\tlabel = \"green:adsl\";\n\t\t\tgpios = <&pinctrl 2 1>;\n\t\t};\n\t\tinet_fail_green {\n\t\t\tlabel = \"green:inet-fail\";\n\t\t\tgpios = <&pinctrl 3 0>;\n\t\t};\n\t\tinet_green {\n\t\t\tlabel = \"green:inet\";\n\t\t\tgpios = <&pinctrl 5 0>;\n\t\t};\n\t\tpower_green {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&pinctrl 22 0>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t\twps_green {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&pinctrl 23 1>;\n\t\t};\n\t};\n};\n\n&pflash {\n\tstatus = \"okay\";\n\n\tpartitions {\n\t\tcompatible = \"brcm,bcm963xx-cfe-nor-partitions\";\n\t};\n};\n\n&pinctrl {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_pci>;\n};\n\n&uart0 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/bcm63xx/dts/bcm6368-brcm-bcm96368mvwg.dts",
    "content": "#include \"bcm6368.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"Broadcom BCM96368MVWG reference board\";\n\tcompatible = \"brcm,bcm96368mvwg\", \"brcm,bcm6368\";\n\n\tchosen {\n\t\tbootargs = \"rootfstype=squashfs,jffs2 noinitrd console=ttyS0,115200\";\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tdsl_green {\n\t\t\tlabel = \"green:adsl\";\n\t\t\tgpios = <&pinctrl 2 1>;\n\t\t};\n\t\tppp_green {\n\t\t\tlabel = \"green:ppp\";\n\t\t\tgpios = <&pinctrl 5 0>;\n\t\t};\n\t\tpower_green {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&pinctrl 22 0>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t\twps_green {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&pinctrl 23 1>;\n\t\t};\n\t\tppp_fail_red {\n\t\t\tlabel = \"red:ppp-fail\";\n\t\t\tgpios = <&pinctrl 31 0>;\n\t\t};\n\t};\n};\n\n&pflash {\n\tstatus = \"okay\";\n\n\tpartitions {\n\t\tcompatible = \"brcm,bcm963xx-cfe-nor-partitions\";\n\t};\n};\n\n&pinctrl {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_pci>;\n};\n\n&uart0 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/bcm63xx/dts/bcm6368-comtrend-vr-3025u.dts",
    "content": "#include \"bcm6368.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"Comtrend VR-3025u\";\n\tcompatible = \"comtrend,vr-3025u\", \"brcm,bcm6368\";\n\n\taliases {\n\t\tled-boot = &led_power_green;\n\t\tled-failsafe = &led_power_green;\n\t\tled-running = &led_power_green;\n\t\tled-upgrade = &led_power_green;\n\t};\n\n\tchosen {\n\t\tbootargs = \"rootfstype=squashfs,jffs2 noinitrd console=ttyS0,115200\";\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&pinctrl 34 1>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tdsl_green {\n\t\t\tlabel = \"green:dsl\";\n\t\t\tgpios = <&pinctrl 2 1>;\n\t\t};\n\t\tinet_green {\n\t\t\tlabel = \"green:inet\";\n\t\t\tgpios = <&pinctrl 5 0>;\n\t\t};\n\t\tled_power_green: power_green {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&pinctrl 22 0>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t\tpower_red {\n\t\t\tlabel = \"red:power\";\n\t\t\tgpios = <&pinctrl 24 0>;\n\t\t};\n\t\tinet_red {\n\t\t\tlabel = \"red:inet\";\n\t\t\tgpios = <&pinctrl 31 0>;\n\t\t};\n\t};\n};\n\n&pflash {\n\tstatus = \"okay\";\n\n\tpartitions {\n\t\tcompatible = \"fixed-partitions\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tcfe@0 {\n\t\t\tlabel = \"CFE\";\n\t\t\treg = <0x0000000 0x0020000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tlinux@20000 {\n\t\t\tlabel = \"linux\";\n\t\t\treg = <0x0020000 0x1fc0000>;\n\t\t\tcompatible = \"brcm,bcm963xx-imagetag\";\n\t\t};\n\n\t\tnvram@1fe0000 {\n\t\t\tlabel = \"nvram\";\n\t\t\treg = <0x1fe0000 0x020000>;\n\t\t};\n\t};\n};\n\n&pinctrl {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_pci &pinctrl_ephy0_led &pinctrl_ephy1_led\n\t\t     &pinctrl_ephy2_led &pinctrl_ephy3_led>;\n};\n\n&uart0 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/bcm63xx/dts/bcm6368-comtrend-vr-3025un.dts",
    "content": "#include \"bcm6368.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"Comtrend VR-3025un\";\n\tcompatible = \"comtrend,vr-3025un\", \"brcm,bcm6368\";\n\n\taliases {\n\t\tled-boot = &led_power_green;\n\t\tled-failsafe = &led_power_green;\n\t\tled-running = &led_power_green;\n\t\tled-upgrade = &led_power_green;\n\t};\n\n\tchosen {\n\t\tbootargs = \"rootfstype=squashfs,jffs2 noinitrd console=ttyS0,115200\";\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&pinctrl 34 1>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tdsl_green {\n\t\t\tlabel = \"green:dsl\";\n\t\t\tgpios = <&pinctrl 2 1>;\n\t\t};\n\t\tinet_green {\n\t\t\tlabel = \"green:inet\";\n\t\t\tgpios = <&pinctrl 5 0>;\n\t\t};\n\t\tled_power_green: power_green {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&pinctrl 22 0>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t\tpower_red {\n\t\t\tlabel = \"red:power\";\n\t\t\tgpios = <&pinctrl 24 0>;\n\t\t};\n\t\tinet_red {\n\t\t\tlabel = \"red:inet\";\n\t\t\tgpios = <&pinctrl 31 0>;\n\t\t};\n\t};\n};\n\n&pflash {\n\tstatus = \"okay\";\n\n\tpartitions {\n\t\tcompatible = \"fixed-partitions\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tcfe@0 {\n\t\t\tlabel = \"CFE\";\n\t\t\treg = <0x000000 0x010000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tlinux@10000 {\n\t\t\tlabel = \"linux\";\n\t\t\treg = <0x010000 0x7e0000>;\n\t\t\tcompatible = \"brcm,bcm963xx-imagetag\";\n\t\t};\n\n\t\tnvram@7f0000 {\n\t\t\tlabel = \"nvram\";\n\t\t\treg = <0x7f0000 0x010000>;\n\t\t};\n\t};\n};\n\n&pinctrl {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_pci &pinctrl_ephy0_led &pinctrl_ephy1_led\n\t\t     &pinctrl_ephy2_led &pinctrl_ephy3_led>;\n};\n\n&uart0 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/bcm63xx/dts/bcm6368-comtrend-vr-3026e.dts",
    "content": "#include \"bcm6368.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"Comtrend VR-3026e\";\n\tcompatible = \"comtrend,vr-3026e\", \"brcm,bcm6368\";\n\n\taliases {\n\t\tled-boot = &led_power_green;\n\t\tled-failsafe = &led_power_green;\n\t\tled-running = &led_power_green;\n\t\tled-upgrade = &led_power_green;\n\t};\n\n\tchosen {\n\t\tbootargs = \"rootfstype=squashfs,jffs2 noinitrd console=ttyS0,115200\";\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&pinctrl 34 1>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tdsl_green {\n\t\t\tlabel = \"green:dsl\";\n\t\t\tgpios = <&pinctrl 2 1>;\n\t\t};\n\t\tinet_green {\n\t\t\tlabel = \"green:inet\";\n\t\t\tgpios = <&pinctrl 5 0>;\n\t\t};\n\t\tled_power_green: power_green {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&pinctrl 22 0>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t\tpower_red {\n\t\t\tlabel = \"red:power\";\n\t\t\tgpios = <&pinctrl 24 0>;\n\t\t};\n\t\tinet_red {\n\t\t\tlabel = \"red:inet\";\n\t\t\tgpios = <&pinctrl 31 0>;\n\t\t};\n\t};\n};\n\n&pflash {\n\tstatus = \"okay\";\n\n\tpartitions {\n\t\tcompatible = \"fixed-partitions\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tcfe@0 {\n\t\t\tlabel = \"CFE\";\n\t\t\treg = <0x000000 0x010000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tlinux@10000 {\n\t\t\tlabel = \"linux\";\n\t\t\treg = <0x010000 0x7e0000>;\n\t\t\tcompatible = \"brcm,bcm963xx-imagetag\";\n\t\t};\n\n\t\tnvram@7f0000 {\n\t\t\tlabel = \"nvram\";\n\t\t\treg = <0x7f0000 0x010000>;\n\t\t};\n\t};\n};\n\n&pinctrl {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_pci &pinctrl_ephy0_led &pinctrl_ephy1_led\n\t\t     &pinctrl_ephy2_led &pinctrl_ephy3_led>;\n};\n\n&uart0 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/bcm63xx/dts/bcm6368-huawei-echolife-hg622.dts",
    "content": "#include \"bcm6368.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"Huawei EchoLife HG622\";\n\tcompatible = \"huawei,echolife-hg622\", \"brcm,bcm6368\";\n\n\tchosen {\n\t\tbootargs = \"rootfstype=squashfs,jffs2 noinitrd console=ttyS0,115200\";\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&pinctrl 34 1>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tdsl_green {\n\t\t\tlabel = \"green:dsl\";\n\t\t\tgpios = <&pinctrl 2 1>;\n\t\t};\n\t\tinet_green {\n\t\t\tlabel = \"green:inet\";\n\t\t\tgpios = <&pinctrl 5 1>;\n\t\t};\n\t\tusb_green {\n\t\t\tlabel = \"green:usb\";\n\t\t\tgpios = <&pinctrl 11 1>;\n\t\t};\n\t\tpower_green {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&pinctrl 22 1>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n};\n\n&pflash {\n\tstatus = \"okay\";\n\n\tpartitions {\n\t\tcompatible = \"fixed-partitions\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tcfe@0 {\n\t\t\tlabel = \"CFE\";\n\t\t\treg = <0x000000 0x020000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tlinux@20000 {\n\t\t\tlabel = \"linux\";\n\t\t\treg = <0x020000 0xf80000>;\n\t\t\tcompatible = \"brcm,bcm963xx-imagetag\";\n\t\t};\n\n\t\tcal_data@fa0000 {\n\t\t\tlabel = \"cal_data\";\n\t\t\treg = <0xfa0000 0x020000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tnvram@fe0000 {\n\t\t\tlabel = \"nvram\";\n\t\t\treg = <0xfe0000 0x020000>;\n\t\t};\n\t};\n};\n\n&pinctrl {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_ephy0_led &pinctrl_ephy1_led\n\t\t     &pinctrl_ephy2_led &pinctrl_ephy3_led\n\t\t     &pinctrl_pci_gnt0 &pinctrl_pci_req0\n\t\t     &pinctrl_pci_intb &pinctrl_pci_gnt1\n\t\t     &pinctrl_pci_req1>;\n};\n\n&uart0 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/bcm63xx/dts/bcm6368-huawei-echolife-hg655b.dts",
    "content": "#include \"bcm6368.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"Huawei EchoLife HG655b\";\n\tcompatible = \"huawei,echolife-hg655b\", \"brcm,bcm6368\";\n\n\taliases {\n\t\tled-boot = &led_power_green;\n\t\tled-failsafe = &led_power_green;\n\t\tled-running = &led_power_green;\n\t\tled-upgrade = &led_power_green;\n\t};\n\n\tchosen {\n\t\tbootargs = \"rootfstype=squashfs,jffs2 noinitrd console=ttyS0,115200\";\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tpoll-interval = <20>;\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&pinctrl 12 1>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\twlan {\n\t\t\tlabel = \"wlan\";\n\t\t\tgpios = <&pinctrl 23 1>;\n\t\t\tlinux,code = <KEY_WLAN>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&pinctrl 34 1>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tdsl_green {\n\t\t\tlabel = \"green:dsl\";\n\t\t\tgpios = <&pinctrl 2 1>;\n\t\t};\n\t\tinternet_green {\n\t\t\tlabel = \"green:internet\";\n\t\t\tgpios = <&pinctrl 5 1>;\n\t\t};\n\n\t\tusb_green {\n\t\t\tlabel = \"green:usb\";\n\t\t\tgpios = <&pinctrl 14 1>;\n\t\t};\n\t\tled_power_green: power_green {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&pinctrl 22 1>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t\tvoip_green {\n\t\t\tlabel = \"green:voip\";\n\t\t\tgpios = <&pinctrl 25 1>;\n\t\t};\n\t\twps_green {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&pinctrl 27 1>;\n\t\t};\n\t};\n};\n\n&pflash {\n\tstatus = \"okay\";\n\n\tpartitions {\n\t\tcompatible = \"fixed-partitions\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tcfe@0 {\n\t\t\tlabel = \"CFE\";\n\t\t\treg = <0x000000 0x020000>;\n\t\t};\n\n\t\tlinux@20000 {\n\t\t\tlabel = \"linux\";\n\t\t\treg = <0x020000 0x770000>;\n\t\t\tcompatible = \"brcm,bcm963xx-imagetag\";\n\t\t};\n\n\t\tboard_data@790000 {\n\t\t\tlabel = \"board_data\";\n\t\t\treg = <0x790000 0x030000>;\n\t\t};\n\n\t\tcal_data@7c0000 {\n\t\t\tlabel = \"cal_data\";\n\t\t\treg = <0x7c0000 0x020000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tnvram@7d0000 {\n\t\t\tlabel = \"nvram\";\n\t\t\treg = <0x7e0000 0x020000>;\n\t\t};\n\t};\n};\n\n&pinctrl {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_pci &pinctrl_ephy0_led &pinctrl_ephy1_led\n\t\t     &pinctrl_ephy2_led &pinctrl_ephy3_led>;\n};\n\n&uart0 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/bcm63xx/dts/bcm6368-netgear-dgnd3700-v1.dts",
    "content": "#include \"bcm6368.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"Netgear DGND3700v1/DGND3800B\";\n\tcompatible = \"netgear,dgnd3700-v1\", \"brcm,bcm6368\";\n\n\taliases {\n\t\tled-boot = &led_power_green;\n\t\tled-failsafe = &led_power_green;\n\t\tled-running = &led_power_green;\n\t\tled-upgrade = &led_power_green;\n\t};\n\n\tchosen {\n\t\tbootargs = \"rootfstype=squashfs,jffs2 noinitrd console=ttyS0,115200\";\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tpoll-interval = <20>;\n\n\t\twlan {\n\t\t\tlabel = \"wlan\";\n\t\t\tgpios = <&pinctrl 10 1>;\n\t\t\tlinux,code = <KEY_WLAN>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&pinctrl 12 1>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&pinctrl 35 1>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tdsl_green {\n\t\t\tlabel = \"green:dsl\";\n\t\t\tgpios = <&pinctrl 2 1>;\n\t\t};\n\t\tinet_red {\n\t\t\tlabel = \"red:inet\";\n\t\t\tgpios = <&pinctrl 4 1>;\n\t\t};\n\t\tinet_green {\n\t\t\tlabel = \"green:inet\";\n\t\t\tgpios = <&pinctrl 5 1>;\n\t\t};\n\t\twps_green {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&pinctrl 11 1>;\n\t\t};\n\t\tusbfront_green {\n\t\t\tlabel = \"green:usb-front\";\n\t\t\tgpios = <&pinctrl 13 1>;\n\t\t};\n\t\tusbback_green {\n\t\t\tlabel = \"green:usb-back\";\n\t\t\tgpios = <&pinctrl 14 1>;\n\t\t};\n\t\tpower_red {\n\t\t\tlabel = \"red:power\";\n\t\t\tgpios = <&pinctrl 22 1>;\n\t\t};\n\t\tlan_green {\n\t\t\tlabel = \"green:lan\";\n\t\t\tgpios = <&pinctrl 23 1>;\n\t\t};\n\t\tled_power_green: power_green {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&pinctrl 24 1>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t\twifi2g_green {\n\t\t\tlabel = \"green:wifi2g\";\n\t\t\tgpios = <&pinctrl 26 1>;\n\t\t};\n\t\twifi5g_blue {\n\t\t\tlabel = \"blue:wifi5g\";\n\t\t\tgpios = <&pinctrl 27 1>;\n\t\t};\n\t};\n};\n\n&pflash {\n\tstatus = \"okay\";\n\n\tpartitions {\n\t\tcompatible = \"fixed-partitions\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tcfe@0 {\n\t\t\tlabel = \"CFE\";\n\t\t\treg = <0x000000 0x020000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tlinux@20000 {\n\t\t\tlabel = \"linux\";\n\t\t\treg = <0x020000 0x1e20000>;\n\t\t\tcompatible = \"brcm,bcm963xx-imagetag\";\n\t\t};\n\n\t\tboard_data@1e40000 {\n\t\t\tlabel = \"board_data\";\n\t\t\treg = <0x1e40000 0x1a0000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tnvram@1fe0000 {\n\t\t\tlabel = \"nvram\";\n\t\t\treg = <0x1fe0000 0x20000>;\n\t\t};\n\t};\n};\n\n&pinctrl {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_pci>;\n};\n\n&lsspi {\n\tswitch@1 {\n\t\tcompatible = \"brcm,bcm53115\";\n\t\treg = <1>;\n\t\tspi-max-frequency = <781000>;\n\n\t\tlede,alias = \"eth0\";\n\n\t\tports {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\n\t\t\twan@0 {\n\t\t\t\treg = <0>;\n\t\t\t\tlabel = \"wan\";\n\t\t\t};\n\n\t\t\tlan@1 {\n\t\t\t\treg = <1>;\n\t\t\t\tlabel = \"lan4\";\n\t\t\t};\n\n\t\t\tlan@2 {\n\t\t\t\treg = <2>;\n\t\t\t\tlabel = \"lan3\";\n\t\t\t};\n\n\t\t\tlan@3 {\n\t\t\t\treg = <3>;\n\t\t\t\tlabel = \"lan2\";\n\t\t\t};\n\n\t\t\tlan@4 {\n\t\t\t\treg = <4>;\n\t\t\t\tlabel = \"lan1\";\n\t\t\t};\n\n\t\t\tcpu@8 {\n\t\t\t\treg = <8>;\n\t\t\t\tlabel = \"cpu\";\n\n\t\t\t\tfixed-link {\n\t\t\t\t\tspeed = <1000>;\n\t\t\t\t\tfull-duplex;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t};\n};\n\n&nflash {\n\tstatus = \"okay\";\n\n\tnandcs@0 {\n\t\tcompatible = \"brcm,nandcs\";\n\t\t#size-cells = <1>;\n\t\t#address-cells = <1>;\n\t\treg = <0>;\n\t\tnand-ecc-step-size = <512>;\n\t\tnand-ecc-strength = <15>;\n\t\tnand-on-flash-bbt;\n\t\tbrcm,nand-oob-sector-size = <64>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"storage\";\n\t\t\t\treg = <0x0000000 0x8000000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&uart0 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/bcm63xx/dts/bcm6368-observa-vh4032n.dts",
    "content": "#include \"bcm6368.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"Observa VH4032N\";\n\tcompatible = \"observa,vh4032n\", \"brcm,bcm6368\";\n\n\taliases {\n\t\tled-boot = &led_power_blue;\n\t\tled-failsafe = &led_power_blue;\n\t\tled-running = &led_power_blue;\n\t\tled-upgrade = &led_power_blue;\n\t};\n\n\tchosen {\n\t\tbootargs = \"rootfstype=squashfs,jffs2 noinitrd console=ttyS0,115200\";\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&pinctrl 34 1>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\twlan {\n\t\t\tlabel = \"wlan\";\n\t\t\tgpios = <&pinctrl 35 1>;\n\t\t\tlinux,code = <KEY_WLAN>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tdsl_blue {\n\t\t\tlabel = \"blue:dsl\";\n\t\t\tgpios = <&pinctrl 2 1>;\n\t\t};\n\t\tdsl_red {\n\t\t\tlabel = \"red:dsl\";\n\t\t\tgpios = <&pinctrl 5 1>;\n\t\t};\n\t\thspa_blue {\n\t\t\tlabel = \"blue:hspa\";\n\t\t\tgpios = <&pinctrl 11 1>;\n\t\t};\n\t\thspa_red {\n\t\t\tlabel = \"red:hspa\";\n\t\t\tgpios = <&pinctrl 12 1>;\n\t\t};\n\t\tled_power_blue: power_blue {\n\t\t\tlabel = \"blue:power\";\n\t\t\tgpios = <&pinctrl 22 0>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t\tpower_red {\n\t\t\tlabel = \"red:power\";\n\t\t\tgpios = <&pinctrl 24 0>;\n\t\t};\n\t\tvoice_blue {\n\t\t\tlabel = \"blue:voice\";\n\t\t\tgpios = <&pinctrl 25 1>;\n\t\t};\n\t\tvoice_red {\n\t\t\tlabel = \"red:voice\";\n\t\t\tgpios = <&pinctrl 26 1>;\n\t\t};\n\t};\n};\n\n&pinctrl {\n       pinctrl-names = \"default\";\n       pinctrl-0 = <&pinctrl_pci &pinctrl_ephy0_led &pinctrl_ephy1_led\n\t\t    &pinctrl_ephy2_led &pinctrl_ephy3_led>;\n\n\tusb_hub_reset {\n\t\tgpio-hog;\n\t\tgpios = <27 0>;\n\t\toutput-high;\n\t\tline-name = \"usb-hub-reset-gpio\";\n\t};\n};\n\n&pflash {\n\tstatus = \"okay\";\n\n\tpartitions {\n\t\tcompatible = \"fixed-partitions\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tcfe@0 {\n\t\t\tlabel = \"CFE\";\n\t\t\treg = <0x0000000 0x0020000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tlinux@20000 {\n\t\t\tlabel = \"linux\";\n\t\t\treg = <0x0020000 0x1fc0000>;\n\t\t\tcompatible = \"brcm,bcm963xx-imagetag\";\n\t\t};\n\n\t\tnvram@1fe0000 {\n\t\t\tlabel = \"nvram\";\n\t\t\treg = <0x1fe0000 0x020000>;\n\t\t};\n\t};\n};\n\n&uart0 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/bcm63xx/dts/bcm6368-zyxel-p870hw-51a-v2.dts",
    "content": "#include \"bcm6368.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"Zyxel P870HW-51a v2\";\n\tcompatible = \"zyxel,p870hw-51a-v2\", \"brcm,bcm6368\";\n\n\taliases {\n\t\tled-boot = &led_power_green;\n\t\tled-failsafe = &led_power_green;\n\t\tled-running = &led_power_green;\n\t\tled-upgrade = &led_power_green;\n\t};\n\n\tchosen {\n\t\tbootargs = \"rootfstype=squashfs,jffs2 noinitrd console=ttyS0,115200\";\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&pinctrl 35 1>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&pinctrl 36 1>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power_green: power_green {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&pinctrl 0 0>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t\tdsl_green {\n\t\t\tlabel = \"green:dsl\";\n\t\t\tgpios = <&pinctrl 2 1>;\n\t\t};\n\t\tinet_green {\n\t\t\tlabel = \"green:inet\";\n\t\t\tgpios = <&pinctrl 22 1>;\n\t\t};\n\t\twps_orange {\n\t\t\tlabel = \"orange:wps\";\n\t\t\tgpios = <&pinctrl 24 1>;\n\t\t};\n\t\tinet_red {\n\t\t\tlabel = \"red:inet\";\n\t\t\tgpios = <&pinctrl 33 1>;\n\t\t};\n\t};\n};\n\n&pflash {\n\tstatus = \"okay\";\n\n\tpartitions {\n\t\tcompatible = \"fixed-partitions\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tcfe@0 {\n\t\t\tlabel = \"CFE\";\n\t\t\treg = <0x000000 0x010000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tlinux@10000 {\n\t\t\tlabel = \"linux\";\n\t\t\treg = <0x010000 0x3e0000>;\n\t\t\tcompatible = \"brcm,bcm963xx-imagetag\";\n\t\t};\n\n\t\tnvram@3f0000 {\n\t\t\tlabel = \"nvram\";\n\t\t\treg = <0x3f0000 0x010000>;\n\t\t};\n\t};\n};\n\n&pinctrl {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_pci>;\n};\n\n&uart0 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/bcm63xx/dts/bcm6368.dtsi",
    "content": "/dts-v1/;\n\n/ {\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\tcompatible = \"brcm,bcm6368\";\n\n\taliases {\n\t\tnflash = &nflash;\n\t\tpflash = &pflash;\n\t\tpinctrl = &pinctrl;\n\t\tserial0 = &uart0;\n\t\tserial1 = &uart1;\n\t\tspi0 = &lsspi;\n\t};\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu@0 {\n\t\t\tcompatible = \"brcm,bmips4350\", \"mips,mips4Kc\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\treg = <0>;\n\t\t};\n\n\t\tcpu@1 {\n\t\t\tcompatible = \"brcm,bmips4350\", \"mips,mips4Kc\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\treg = <1>;\n\t\t};\n\t};\n\n\tcpu_intc: interrupt-controller {\n\t\t#address-cells = <0>;\n\t\tcompatible = \"mti,cpu-interrupt-controller\";\n\n\t\tinterrupt-controller;\n\t\t#interrupt-cells = <1>;\n\t};\n\n\tmemory { device_type = \"memory\"; reg = <0 0>; };\n\n\tubus@10000000 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tranges;\n\t\tcompatible = \"simple-bus\";\n\t\tinterrupt-parent = <&periph_intc>;\n\n\t\text_intc0: interrupt-controller@10000018 {\n\t\t\tcompatible = \"brcm,bcm6345-ext-intc\";\n\t\t\treg = <0x10000018 0x4>;\n\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <2>;\n\n\t\t\tinterrupts = <20>, <21>, <22>, <23>;\n\t\t};\n\n\t\text_intc1: interrupt-controller@1000001c {\n\t\t\tcompatible = \"brcm,bcm6345-ext-intc\";\n\t\t\treg = <0x1000001c 0x4>;\n\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <2>;\n\n\t\t\tinterrupts = <24>, <25>;\n\t\t};\n\n\t\tperiph_intc: interrupt-controller@10000020 {\n\t\t\tcompatible = \"brcm,bcm6345-l1-intc\";\n\t\t\treg = <0x10000020 0x10>,\n\t\t\t      <0x10000030 0x10>;\n\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <1>;\n\n\t\t\tinterrupt-parent = <&cpu_intc>;\n\t\t\tinterrupts = <2>, <3>;\n\t\t};\n\n\t\tpinctrl: pin-controller@10000080 {\n\t\t\tcompatible = \"brcm,bcm6368-pinctrl\";\n\t\t\treg = <0x10000080 0x8>,\n\t\t\t      <0x10000088 0x8>,\n\t\t\t      <0x10000098 0x4>;\n\t\t\treg-names = \"dirout\", \"dat\", \"mode\";\n\t\t\tbrcm,gpiobasemode = <&gpiobasemode>;\n\n\t\t\tgpio-controller;\n\t\t\t#gpio-cells = <2>;\n\n\t\t\tinterrupts-extended = <&ext_intc1 0 0>,\n\t\t\t\t\t      <&ext_intc1 1 0>,\n\t\t\t\t\t      <&ext_intc0 0 0>,\n\t\t\t\t\t      <&ext_intc0 1 0>,\n\t\t\t\t\t      <&ext_intc0 2 0>,\n\t\t\t\t\t      <&ext_intc0 3 0>;\n\t\t\tinterrupt-names = \"gpio32\", \"gpio33\", \"gpio34\", \"gpio35\",\n\t\t\t\t\t  \"gpio36\", \"gpio37\";\n\n\t\t\tpinctrl_analog_afe_0: analog_afe_0 {\n\t\t\t\tfunction = \"analog_afe_0\";\n\t\t\t\tpins = \"gpio0\";\n\t\t\t};\n\n\t\t\tpinctrl_analog_afe_1: analog_afe_1 {\n\t\t\t\tfunction = \"analog_afe_1\";\n\t\t\t\tpins = \"gpio1\";\n\t\t\t};\n\n\t\t\tpinctrl_sys_irq: sys_irq {\n\t\t\t\tfunction = \"sys_irq\";\n\t\t\t\tpins = \"gpio2\";\n\t\t\t};\n\n\t\t\tpinctrl_serial_led: serial_led {\n\t\t\t\tpinctrl_serial_led_data: serial_led_data {\n\t\t\t\t\tfunction = \"serial_led_data\";\n\t\t\t\t\tpins = \"gpio3\";\n\t\t\t\t};\n\n\t\t\t\tpinctrl_serial_led_clk: serial_led_clk {\n\t\t\t\t\tfunction = \"serial_led_clk\";\n\t\t\t\t\tpins = \"gpio4\";\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tpinctrl_inet_led: inet_led {\n\t\t\t\tfunction = \"inet_led\";\n\t\t\t\tpins = \"gpio5\";\n\t\t\t};\n\n\t\t\tpinctrl_ephy0_led: ephy0_led {\n\t\t\t\tfunction = \"ephy0_led\";\n\t\t\t\tpins = \"gpio6\";\n\t\t\t};\n\n\t\t\tpinctrl_ephy1_led: ephy1_led {\n\t\t\t\tfunction = \"ephy1_led\";\n\t\t\t\tpins = \"gpio7\";\n\t\t\t};\n\n\t\t\tpinctrl_ephy2_led: ephy2_led {\n\t\t\t\tfunction = \"ephy2_led\";\n\t\t\t\tpins = \"gpio8\";\n\t\t\t};\n\n\t\t\tpinctrl_ephy3_led: ephy3_led {\n\t\t\t\tfunction = \"ephy3_led\";\n\t\t\t\tpins = \"gpio9\";\n\t\t\t};\n\n\t\t\tpinctrl_robosw_led_data: robosw_led_data {\n\t\t\t\tfunction = \"robosw_led_data\";\n\t\t\t\tpins = \"gpio10\";\n\t\t\t};\n\n\t\t\tpinctrl_robosw_led_clk: robosw_led_clk {\n\t\t\t\tfunction = \"robosw_led_clk\";\n\t\t\t\tpins = \"gpio11\";\n\t\t\t};\n\n\t\t\tpinctrl_robosw_led0: robosw_led0 {\n\t\t\t\tfunction = \"robosw_led0\";\n\t\t\t\tpins = \"gpio12\";\n\t\t\t};\n\n\t\t\tpinctrl_robosw_led1: robosw_led1 {\n\t\t\t\tfunction = \"robosw_led1\";\n\t\t\t\tpins = \"gpio13\";\n\t\t\t};\n\n\t\t\tpinctrl_usb_device_led: usb_device_led {\n\t\t\t\tfunction = \"usb_device_led\";\n\t\t\t\tpins = \"gpio14\";\n\t\t\t};\n\n\t\t\tpinctrl_pci: pci {\n\t\t\t\tpinctrl_pci_req1: pci_req1 {\n\t\t\t\t\tfunction = \"pci_req1\";\n\t\t\t\t\tpins = \"gpio16\";\n\t\t\t\t};\n\n\t\t\t\tpinctrl_pci_gnt1: pci_gnt1 {\n\t\t\t\t\tfunction = \"pci_gnt1\";\n\t\t\t\t\tpins = \"gpio17\";\n\t\t\t\t};\n\n\t\t\t\tpinctrl_pci_intb: pci_intb {\n\t\t\t\t\tfunction = \"pci_intb\";\n\t\t\t\t\tpins = \"gpio18\";\n\t\t\t\t};\n\n\t\t\t\tpinctrl_pci_req0: pci_req0 {\n\t\t\t\t\tfunction = \"pci_req0\";\n\t\t\t\t\tpins = \"gpio19\";\n\t\t\t\t};\n\n\t\t\t\tpinctrl_pci_gnt0: pci_gnt0 {\n\t\t\t\t\tfunction = \"pci_gnt0\";\n\t\t\t\t\tpins = \"gpio20\";\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tpinctrl_pcmcia: pcmcia {\n\t\t\t\tpinctrl_pcmcia_cd1: pcmcia_cd1 {\n\t\t\t\t\tfunction = \"pcmcia_cd1\";\n\t\t\t\t\tpins = \"gpio22\";\n\t\t\t\t};\n\n\t\t\t\tpinctrl_pcmcia_cd2: pcmcia_cd2 {\n\t\t\t\t\tfunction = \"pcmcia_cd2\";\n\t\t\t\t\tpins = \"gpio23\";\n\t\t\t\t};\n\n\t\t\t\tpinctrl_pcmcia_vs1: pcmcia_vs1 {\n\t\t\t\t\tfunction = \"pcmcia_vs1\";\n\t\t\t\t\tpins = \"gpio24\";\n\t\t\t\t};\n\n\t\t\t\tpinctrl_pcmcia_vs2: pcmcia_vs2 {\n\t\t\t\t\tfunction = \"pcmcia_vs2\";\n\t\t\t\t\tpins = \"gpio25\";\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tpinctrl_ebi_cs2: ebi_cs2 {\n\t\t\t\tfunction = \"ebi_cs2\";\n\t\t\t\tpins = \"gpio26\";\n\t\t\t};\n\n\t\t\tpinctrl_ebi_cs3: ebi_cs3 {\n\t\t\t\tfunction = \"ebi_cs2\";\n\t\t\t\tpins = \"gpio27\";\n\t\t\t};\n\n\t\t\tpinctrl_spi_cs2: spi_cs2 {\n\t\t\t\tfunction = \"spi_cs2\";\n\t\t\t\tpins = \"gpio28\";\n\t\t\t};\n\n\t\t\tpinctrl_spi_cs3: spi_cs3 {\n\t\t\t\tfunction = \"spi_cs3\";\n\t\t\t\tpins = \"gpio29\";\n\t\t\t};\n\n\t\t\tpinctrl_spi_cs4: spi_cs4 {\n\t\t\t\tfunction = \"spi_cs4\";\n\t\t\t\tpins = \"gpio30\";\n\t\t\t};\n\n\t\t\tpinctrl_spi_cs5: spi_cs5 {\n\t\t\t\tfunction = \"spi_cs5\";\n\t\t\t\tpins = \"gpio31\";\n\t\t\t};\n\n\t\t\tpinctrl_uart1: uart1 {\n\t\t\t\tfunction = \"uart1\";\n\t\t\t\tgroup = \"uart1_grp\";\n\t\t\t};\n\t\t};\n\n\t\tgpiobasemode: gpiobasemode@100000b8 {\n\t\t\tcompatible = \"brcm,bcm6368-gpiobasemode\", \"syscon\";\n\t\t\treg = <0x100000b8 0x4>;\n\t\t};\n\n\t\tleds: led-controller@100000d0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tcompatible = \"brcm,bcm6358-leds\";\n\t\t\treg = <0x100000d0 0x8>;\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tuart0: serial@10000100 {\n\t\t\tcompatible = \"brcm,bcm6345-uart\";\n\t\t\treg = <0x10000100 0x18>;\n\n\t\t\tinterrupt-parent = <&periph_intc>;\n\t\t\tinterrupts = <2>;\n\n\t\t\t/* clocks = <&periph_clk>; */\n\t\t\t/* clock-names = \"refclk\"; */\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tuart1: serial@10000120 {\n\t\t\tcompatible = \"brcm,bcm6345-uart\";\n\t\t\treg = <0x10000120 0x18>;\n\n\t\t\tinterrupt-parent = <&periph_intc>;\n\t\t\tinterrupts = <3>;\n\n\t\t\t/* clocks = <&periph_clk>; */\n\t\t\t/* clock-names = \"refclk\"; */\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tnflash: nand@10000200 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tcompatible = \"brcm,nand-bcm6368\",\n\t\t\t\t     \"brcm,brcmnand-v2.1\",\n\t\t\t\t     \"brcm,brcmnand\";\n\t\t\treg = <0x10000200 0x180>,\n\t\t\t      <0x10000600 0x200>,\n\t\t\t      <0x10000070 0x10>;\n\t\t\treg-names = \"nand\",\n\t\t\t\t    \"nand-cache\",\n\t\t\t\t    \"nand-int-base\";\n\n\t\t\tinterrupt-parent = <&periph_intc>;\n\t\t\tinterrupts = <10>;\n\n\t\t\t/* clocks = <&clkctl 17>; */\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tlsspi: spi@10000800 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tcompatible = \"brcm,bcm6358-spi\";\n\t\t\treg = <0x10000800 0x70c>;\n\t\t\tinterrupts = <1>;\n\t\t\t/* clocks = <&clkctl 9>; */\n\t\t};\n\t};\n\n\tpflash: nor@18000000 {\n\t\tcompatible = \"cfi-flash\";\n\t\treg = <0x18000000 0x2000000>;\n\t\tbank-width = <2>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tstatus = \"disabled\";\n\t};\n};\n"
  },
  {
    "path": "target/linux/bcm63xx/dts/bcm6369-comtrend-wap-5813n.dts",
    "content": "#include \"bcm6368.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"Comtrend WAP-5813n\";\n\tcompatible = \"comtrend,wap-5813n\", \"brcm,bcm6369\", \"brcm,bcm6368\";\n\n\taliases {\n\t\tled-boot = &led_power_green;\n\t\tled-failsafe = &led_power_green;\n\t\tled-running = &led_power_green;\n\t\tled-upgrade = &led_power_green;\n\t};\n\n\tchosen {\n\t\tbootargs = \"rootfstype=squashfs,jffs2 noinitrd console=ttyS0,115200\";\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tpoll-interval = <20>;\n\n\t\twlan {\n\t\t\tlabel = \"wlan\";\n\t\t\tgpios = <&pinctrl 32 1>;\n\t\t\tlinux,code = <KEY_WLAN>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&pinctrl 34 1>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&pinctrl 35 1>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tinet_green {\n\t\t\tlabel = \"green:inet\";\n\t\t\tgpios = <&pinctrl 5 0>;\n\t\t};\n\t\tled_power_green: power_green {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&pinctrl 22 0>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t\twps_green {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&pinctrl 23 1>;\n\t\t};\n\t\tpower_red {\n\t\t\tlabel = \"red:power\";\n\t\t\tgpios = <&pinctrl 24 0>;\n\t\t};\n\t\tinet_red {\n\t\t\tlabel = \"red:inet\";\n\t\t\tgpios = <&pinctrl 31 0>;\n\t\t};\n\t};\n};\n\n&pflash {\n\tstatus = \"okay\";\n\n\tpartitions {\n\t\tcompatible = \"fixed-partitions\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tcfe@0 {\n\t\t\tlabel = \"CFE\";\n\t\t\treg = <0x000000 0x010000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tlinux@10000 {\n\t\t\tlabel = \"linux\";\n\t\t\treg = <0x010000 0x7e0000>;\n\t\t\tcompatible = \"brcm,bcm963xx-imagetag\";\n\t\t};\n\n\t\tnvram@7f0000 {\n\t\t\tlabel = \"nvram\";\n\t\t\treg = <0x7f0000 0x010000>;\n\t\t};\n\t};\n};\n\n&lsspi {\n\tswitch@0 {\n\t\tcompatible = \"brcm,bcm53115\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <781000>;\n\n\t\tlede,alias = \"eth0\";\n\n\t\tports {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\n\t\t\tlan@0 {\n\t\t\t\treg = <0>;\n\t\t\t\tlabel = \"lan4\";\n\t\t\t};\n\n\t\t\tlan@1 {\n\t\t\t\treg = <1>;\n\t\t\t\tlabel = \"lan3\";\n\t\t\t};\n\n\t\t\tlan@2 {\n\t\t\t\treg = <2>;\n\t\t\t\tlabel = \"lan2\";\n\t\t\t};\n\n\t\t\tlan@3 {\n\t\t\t\treg = <3>;\n\t\t\t\tlabel = \"lan1\";\n\t\t\t};\n\n\t\t\twan@4 {\n\t\t\t\treg = <4>;\n\t\t\t\tlabel = \"wan\";\n\t\t\t};\n\n\t\t\tcpu@5 {\n\t\t\t\treg = <5>;\n\t\t\t\tlabel = \"cpu\";\n\n\t\t\t\tfixed-link {\n\t\t\t\t\tspeed = <1000>;\n\t\t\t\t\tfull-duplex;\n\t\t\t\t\tasym-pause;\n\t\t\t\t\tpause;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pinctrl {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_pci>;\n};\n\n&uart0 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/bcm63xx/dts/bcm6369-netgear-evg2000.dts",
    "content": "#include \"bcm6368.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"Netgear EVG2000\";\n\tcompatible = \"netgear,evg2000\", \"brcm,bcm6369\", \"brcm,bcm6368\";\n\n\taliases {\n\t\tled-boot = &led_power_green;\n\t\tled-failsafe = &led_power_green;\n\t\tled-running = &led_power_green;\n\t\tled-upgrade = &led_power_green;\n\t};\n\n\tchosen {\n\t\tbootargs = \"rootfstype=squashfs,jffs2 noinitrd console=ttyS0,115200\";\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&pinctrl 25 1>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&pinctrl 26 1>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tvoip1_green {\n\t\t\tlabel = \"green:voip1\";\n\t\t\tgpios = <&pinctrl 14 1>;\n\t\t};\n\t\tvoip2_green {\n\t\t\tlabel = \"green:voip2\";\n\t\t\tgpios = <&pinctrl 2 1>;\n\t\t};\n\t\tinet_red {\n\t\t\tlabel = \"red:inet\";\n\t\t\tgpios = <&pinctrl 4 1>;\n\t\t};\n\t\tinet_green {\n\t\t\tlabel = \"green:inet\";\n\t\t\tgpios = <&pinctrl 5 1>;\n\t\t};\n\t\tusb_green {\n\t\t\tlabel = \"green:usb\";\n\t\t\tgpios = <&pinctrl 15 1>;\n\t\t};\n\t\tled_power_green: power_green {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&pinctrl 22 1>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t\tpower_red {\n\t\t\tlabel = \"red:power\";\n\t\t\tgpios = <&pinctrl 23 1>;\n\t\t};\n\t\tlan_green {\n\t\t\tlabel = \"green:lan\";\n\t\t\tgpios = <&pinctrl 24 1>;\n\t\t};\n\t\twireless_green {\n\t\t\tlabel = \"green:wireless\";\n\t\t\tgpios = <&pinctrl 26 1>;\n\t\t};\n\t\twan_green {\n\t\t\tlabel = \"green:wan\";\n\t\t\tgpios = <&pinctrl 27 1>;\n\t\t};\n\t};\n};\n\n&pflash {\n\tstatus = \"okay\";\n\n\tpartitions {\n\t\tcompatible = \"fixed-partitions\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tcfe@0 {\n\t\t\tlabel = \"CFE\";\n\t\t\treg = <0x00000000 0x00020000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tlinux@20000 {\n\t\t\tlabel = \"linux\";\n\t\t\treg = <0x00020000 0x00f40000>;\n\t\t\tcompatible = \"brcm,bcm963xx-imagetag\";\n\t\t};\n\n\t\tboard_data@f60000 {\n\t\t\tlabel = \"board_data\";\n\t\t\treg = <0x00f60000 0x00080000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tnvram@fe0000 {\n\t\t\tlabel = \"nvram\";\n\t\t\treg = <0x00fe0000 0x00020000>;\n\t\t};\n\t};\n};\n\n&pinctrl {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_pci>;\n};\n\n&uart0 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/bcm63xx/generic/target.mk",
    "content": "BOARDNAME:=generic\n\ndefine Target/Description\n\tBuild firmware images for BCM63XX boards without SMP support.\nendef\n\n\n"
  },
  {
    "path": "target/linux/bcm63xx/image/Makefile",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2006-2015 OpenWrt.org\n# Copyright (C) 2016 LEDE project\n\ninclude $(TOPDIR)/rules.mk\ninclude $(INCLUDE_DIR)/image.mk\n\nKERNEL_LOADADDR = 0x80010000\t\t# RAM start + 64K\nLOADER_ENTRY = 0x80a00000\t\t# RAM start + 10M, for relocate\nRAMSIZE = 0x02000000\t\t\t# 32MB\nLZMA_TEXT_START = 0x81800000\t\t# 32MB - 8MB\n\nRELOCATE_MAKEOPTS= \\\n\t\tCACHELINE_SIZE=16 \\\n\t\tKERNEL_ADDR=$(KERNEL_LOADADDR) \\\n\t\tCROSS_COMPILE=$(TARGET_CROSS) \\\n\t\tLZMA_TEXT_START=$(LOADER_ENTRY)\n\ndefine Build/Compile\n\trm -rf $(KDIR)/relocate\n\t$(CP) ../../generic/image/relocate $(KDIR)\n\t$(MAKE) -C $(KDIR)/relocate $(RELOCATE_MAKEOPTS)\nendef\n\n### Kernel scripts ###\ndefine Build/hcs-initramfs\n\t$(STAGING_DIR_HOST)/bin/hcsmakeimage --magic_bytes=$(HCS_MAGIC_BYTES) \\\n\t\t--rev_maj=$(HCS_REV_MAJ) --rev_min=$(HCS_REV_MIN) --input_file=$@ \\\n\t\t--output_file=$@.hcs --ldaddress=$(KERNEL_LOADADDR)\n\tmv $@.hcs $@\nendef\n\ndefine Build/loader-lzma\n\trm -rf $@.src\n\t$(MAKE) -C lzma-loader \\\n\t\tKDIR=$(KDIR) \\\n\t\tLOADER_ADDR=$(if $(DEVICE_LOADADDR),$(DEVICE_LOADADDR),$(LOADER_ENTRY)) \\\n\t\tKERNEL_ADDR=$(KERNEL_LOADADDR) \\\n\t\tRAMSIZE=$(RAMSIZE) \\\n\t\tLZMA_TEXT_START=$(LZMA_TEXT_START) \\\n\t\tCHIP_ID=$(CHIP_ID) \\\n\t\tPKG_BUILD_DIR=\"$@.src\" \\\n\t\tTARGET_DIR=\"$(dir $@)\" \\\n\t\tLOADER_DATA=\"$@\" \\\n\t\tLOADER_NAME=\"$(notdir $@)\" \\\n\t\tcompile loader.$(1)\n\tmv \"$@.$(1)\" \"$@\"\n\trm -rf $@.src\nendef\n\ndefine Build/lzma-cfe\n\t# CFE is a LZMA nazi! It took me hours to find out the parameters!\n\t# Also I think lzma has a bug cause it generates different output depending on\n\t# if you use stdin / stdout or not. Use files instead of stdio here, cause\n\t# otherwise CFE will complain and not boot the image.\n\t$(call Build/lzma-no-dict,-d22 -fb64 -a1)\n\t# Strip out the length, CFE doesn't like this\n\tdd if=$@ of=$@.new bs=5 count=1\n\tdd if=$@ of=$@.new ibs=13 obs=5 skip=1 seek=1 conv=notrunc\n\tmv $@.new $@\nendef\n\ndefine Build/relocate-kernel\n\t# CFE only allows ~4 MiB for the uncompressed kernels, but uncompressed\n\t# kernel might get larger than that, so let CFE unpack and load at a\n\t# higher address and make the kernel relocate itself to the expected\n\t# location.\n\t( \\\n\t\tdd if=$(KDIR)/relocate/loader.bin bs=32 conv=sync && \\\n\t\tperl -e '@s = stat(\"$@\"); print pack(\"N\", @s[7])' && \\\n\t\tcat $@ \\\n\t) > $@.relocate\n\tmv $@.relocate $@\nendef\n\n### Image scripts ###\ndefine rootfspad/jffs2-128k\n--align-rootfs\nendef\ndefine rootfspad/jffs2-64k\n--align-rootfs\nendef\ndefine rootfspad/squashfs\nendef\n\ndefine Image/FileSystemStrip\n$(firstword $(subst +,$(space),$(subst root.,,$(notdir $(1)))))\nendef\n\ndefine Build/cfe-bin\n\t$(STAGING_DIR_HOST)/bin/imagetag -i $(IMAGE_KERNEL) -f $(IMAGE_ROOTFS) \\\n\t\t--output $@ --boardid $(CFE_BOARD_ID) --chipid $(CHIP_ID) \\\n\t\t--entry $(LOADER_ENTRY) --load-addr $(LOADER_ENTRY) \\\n\t\t--info1 \"$(call ModelNameLimit16,$(DEVICE_NAME))\" \\\n\t\t--info2 \"$(call Image/FileSystemStrip,$(IMAGE_ROOTFS))\" \\\n\t\t$(call rootfspad/$(call Image/FileSystemStrip,$(IMAGE_ROOTFS))) \\\n\t\t$(CFE_EXTRAS) $(1)\nendef\n\ndefine Build/cfe-jffs2\n\t$(STAGING_DIR_HOST)/bin/mkfs.jffs2 \\\n\t\t--big-endian \\\n\t\t--pad \\\n\t\t--no-cleanmarkers \\\n\t\t--eraseblock=$(patsubst %k,%KiB,$(BLOCKSIZE)) \\\n\t\t--root=$(1) \\\n\t\t--output=$@ \\\n\t\t--compression-mode=none\n\n\t$(call Build/pad-to,$(BLOCKSIZE))\nendef\n\ndefine Build/cfe-jffs2-cferam\n\tmv $@ $@.kernel\n\n\trm -rf $@-cferam\n\tmkdir -p $@-cferam\n\n\t# CFE ROM checks JFFS2 dirent version of cferam.\n\t# If version is not > 0 it will ignore the fs entry.\n\t# JFFS2 sets version 0 to the first fs entry and increments\n\t# it on the following ones, so let's create a dummy file that\n\t# will have version 0 and let cferam be the second (version 1).\n\ttouch $@-cferam/1-openwrt\n\t# Add cferam as the last file in the JFFS2 partition\n\tcp $(KDIR)/bcm63xx-cfe/$(CFE_RAM_FILE) $@-cferam/$(CFE_RAM_JFFS2_NAME)\n\n\t# The JFFS2 partition creation should result in the following\n\t# layout:\n\t# 1) 1-openwrt (version 0, ino 2)\n\t# 2) cferam.000 (version 1, ino 3)\n\t$(call Build/cfe-jffs2,$@-cferam)\n\n\t# Some devices need padding between CFE RAM and kernel\n\t$(if $(CFE_RAM_JFFS2_PAD),$(call Build/pad-to,$(CFE_RAM_JFFS2_PAD)))\n\n\t# Add CFE partition tag\n\t$(if $(CFE_PART_ID),$(call Build/cfe-part-tag))\n\n\t# Append kernel\n\tdd if=$@.kernel >> $@\n\trm -f $@.kernel\nendef\n\ndefine Build/cfe-jffs2-kernel\n\trm -rf $@-kernel\n\tmkdir -p $@-kernel\n\n\t# CFE RAM checks JFFS2 dirent version of vmlinux.\n\t# If version is not > 0 it will ignore the fs entry.\n\t# JFFS2 sets version 0 to the first fs entry and increments\n\t# it on the following ones, so let's create a dummy file that\n\t# will have version 0 and let cferam be the second (version 1).\n\ttouch $@-kernel/1-openwrt\n\t# vmlinux is located on a different JFFS2 partition, but CFE RAM\n\t# ignores it, so let's create another dummy file that will match\n\t# the JFFS2 ino of cferam entry on the first JFFS2 partition.\n\t# CFE RAM won't be able to find vmlinux if cferam has the same\n\t# ino as vmlinux.\n\ttouch $@-kernel/2-openwrt\n\t# Add vmlinux as the last file in the JFFS2 partition\n\t$(TOPDIR)/scripts/cfe-bin-header.py \\\n\t\t--input-file $@ \\\n\t\t--output-file $@-kernel/vmlinux.lz \\\n\t\t--load-addr $(if $(DEVICE_LOADADDR),$(DEVICE_LOADADDR),$(LOADER_ENTRY)) \\\n\t\t--entry-addr $(if $(DEVICE_LOADADDR),$(DEVICE_LOADADDR),$(LOADER_ENTRY))\n\n\t# The JFFS2 partition creation should result in the following\n\t# layout:\n\t# 1) 1-openwrt (version 0, ino 2)\n\t# 2) 2-openwrt (version 1, ino 3)\n\t# 3) vmlinux.lz (version 2, ino 4)\n\t$(call Build/cfe-jffs2,$@-kernel)\nendef\n\ndefine Build/cfe-part-tag\n\tmv $@ $@.part\n\n\t$(TOPDIR)/scripts/cfe-partition-tag.py \\\n\t\t--input-file $@.part \\\n\t\t--output-file $@ \\\n\t\t--flags $(CFE_PART_FLAGS) \\\n\t\t--id $(CFE_PART_ID) \\\n\t\t--name $(VERSION_CODE) \\\n\t\t--version $(DEVICE_NAME)\n\n\t$(call Build/pad-to,$(BLOCKSIZE))\n\n\tdd if=$@.part >> $@\nendef\n\ndefine Build/cfe-sercomm-part\n\t$(TOPDIR)/scripts/sercomm-partition-tag.py \\\n\t\t--input-file $@ \\\n\t\t--output-file $@.kernel_rootfs \\\n\t\t--part-name kernel_rootfs \\\n\t\t--part-version OpenWrt \\\n\t\t--rootfs-version $(SERCOMM_VERSION)\n\n\trm -rf $@-rootfs_lib\n\tmkdir -p $@-rootfs_lib\n\techo $(SERCOMM_VERSION) > $@-rootfs_lib/lib_ver\n\t$(call Build/cfe-jffs2,$@-rootfs_lib)\n\t$(call Build/pad-to,$(BLOCKSIZE))\n\t$(TOPDIR)/scripts/sercomm-partition-tag.py \\\n\t\t--input-file $@ \\\n\t\t--output-file $@.rootfs_lib \\\n\t\t--part-name rootfs_lib \\\n\t\t--part-version $(SERCOMM_VERSION)\n\n\tmv $@.kernel_rootfs $@\n\tdd if=$@.rootfs_lib >> $@\nendef\n\ndefine Build/cfe-sercomm-load\n\t$(TOPDIR)/scripts/sercomm-payload.py \\\n\t\t--input-file $@ \\\n\t\t--output-file $@.new \\\n\t\t--pid \"$(SERCOMM_PID)\"\n\n\tmv $@.new $@\nendef\n\ndefine Build/cfe-sercomm-crypto\n\t$(TOPDIR)/scripts/sercomm-crypto.py \\\n\t\t--input-file $@ \\\n\t\t--key-file $@.key \\\n\t\t--output-file $@.ser \\\n\t\t--version OpenWrt\n\t$(STAGING_DIR_HOST)/bin/openssl enc -md md5 -aes-256-cbc \\\n\t\t-in $@ -out $@.enc \\\n\t\t-K `cat $@.key` \\\n\t\t-iv 00000000000000000000000000000000\n\tdd if=$@.enc >> $@.ser\n\tmv $@.ser $@\n\trm -f $@.enc $@.key\nendef\n\ndefine Build/cfe-old-bin\n\t$(TOPDIR)/scripts/brcmImage.pl -t -p \\\n\t\t-o $@ -b $(CFE_BOARD_ID) -c $(CHIP_ID) \\\n\t\t-e $(LOADER_ENTRY) -a $(LOADER_ENTRY) \\\n\t\t-k $(IMAGE_KERNEL) -r $(IMAGE_ROOTFS) \\\n\t\t$(CFE_EXTRAS)\nendef\n\ndefine Build/cfe-spw303v-bin\n\t$(STAGING_DIR_HOST)/bin/imagetag -i $(IMAGE_KERNEL) -f $(IMAGE_ROOTFS) \\\n\t\t--output $@ --boardid $(CFE_BOARD_ID) --chipid $(CHIP_ID) \\\n\t\t--entry $(LOADER_ENTRY) --load-addr $(LOADER_ENTRY) \\\n\t\t$(call rootfspad/$(call Image/FileSystemStrip,$(IMAGE_ROOTFS))) \\\n\t\t$(CFE_EXTRAS) $(1)\nendef\n\ndefine Build/cfe-wfi-tag\n\t$(TOPDIR)/scripts/cfe-wfi-tag.py \\\n\t\t--input-file $@ \\\n\t\t--output-file $@.new \\\n\t\t--version $(if $(1),$(1),$(CFE_WFI_VERSION)) \\\n\t\t--chip-id $(CFE_WFI_CHIP_ID) \\\n\t\t--flash-type $(CFE_WFI_FLASH_TYPE) \\\n\t\t$(if $(CFE_WFI_FLAGS),--flags $(CFE_WFI_FLAGS))\n\tmv $@.new $@\nendef\n\ndefine Build/spw303v-bin\n\t$(STAGING_DIR_HOST)/bin/spw303v -i $@ -o $@.spw303v\n\tmv $@.spw303v $@\nendef\n\ndefine Build/zyxel-bin\n\t$(STAGING_DIR_HOST)/bin/zyxbcm -i $@ -o $@.zyxel\n\tmv $@.zyxel $@\nendef\n\ndefine Build/redboot-bin\n\t# Prepare kernel and rootfs\n\tdd if=$(IMAGE_KERNEL) of=$(BIN_DIR)/$(REDBOOT_PREFIX)-vmlinux.gz bs=65536 conv=sync\n\tdd if=$(IMAGE_ROOTFS) of=$(BIN_DIR)/$(REDBOOT_PREFIX)-$(notdir $(IMAGE_ROOTFS)) bs=64k conv=sync\n\techo -ne \\\\xDE\\\\xAD\\\\xC0\\\\xDE >> $(BIN_DIR)/$(REDBOOT_PREFIX)-$(notdir $(IMAGE_ROOTFS))\n\t# Generate the scripted image\n\t$(TOPDIR)/scripts/redboot-script.pl \\\n\t\t-k $(BIN_DIR)/$(REDBOOT_PREFIX)-vmlinux.gz \\\n\t\t-r $(BIN_DIR)/$(REDBOOT_PREFIX)-$(notdir $(IMAGE_ROOTFS)) \\\n\t\t-a $(strip $(LOADER_ENTRY)) -f 0xbe430000 -l 0x7c0000 \\\n\t\t-s 0x1000 -t 20 -o $@.redbootscript\n\tdd if=\"$@.redbootscript\" of=\"$@.redbootscript.padded\" bs=4096 conv=sync\n\tcat \\\n\t\t\"$@.redbootscript.padded\" \\\n\t\t\"$(BIN_DIR)/$(REDBOOT_PREFIX)-vmlinux.gz\" \\\n\t\t\"$(BIN_DIR)/$(REDBOOT_PREFIX)-$(notdir $(IMAGE_ROOTFS))\" \\\n\t\t> \"$@\"\nendef\n\ndefine Device/Default\n  PROFILES = Default $$(DEVICE_NAME)\n  KERNEL_DEPENDS = $$(wildcard ../dts/$$(DEVICE_DTS).dts)\n  KERNEL_INITRAMFS_SUFFIX := .elf\n  DEVICE_DTS_DIR := ../dts\n  CHIP_ID :=\n  SOC = bcm$$(CHIP_ID)\n  DEVICE_DTS = $$(SOC)-$(subst _,-,$(1))\n  DEVICE_LOADADDR :=\nendef\nDEVICE_VARS += CHIP_ID DEVICE_LOADADDR\n\nATH5K_PACKAGES := kmod-ath5k wpad-basic-wolfssl\nATH9K_PACKAGES := kmod-ath9k wpad-basic-wolfssl\nB43_PACKAGES := kmod-b43 wpad-basic-wolfssl\nBRCMWL_PACKAGES := kmod-brcm-wl nas wlc\nRT28_PACKAGES := kmod-rt2800-pci wpad-basic-wolfssl\nRT61_PACKAGES := kmod-rt61-pci wpad-basic-wolfssl\nUSB1_PACKAGES := kmod-usb-ohci kmod-usb-ledtrig-usbport\nUSB2_PACKAGES := kmod-usb2 kmod-usb-ohci kmod-usb-ledtrig-usbport\n\ninclude bcm63xx.mk\n\nifeq ($(SUBTARGET),smp)\ninclude bcm63xx_nand.mk\nendif\n\n$(eval $(call BuildImage))\n"
  },
  {
    "path": "target/linux/bcm63xx/image/README.images-bcm63xx",
    "content": "The image neede to flash onto a Broadcom 63xx-series board depends on the\nboard, method you are using to flash, and, for web-based flash, on the version\nof the Broadcom code your router uses.\n\nThere are two major revisions of the Broadcom code as far as imagetags are\nconcerned, before 3.08 and after 3.08, however there are some variations \nwithin in that, either due to vendor differences or due to changes at \nBroadcom (it's not clear yet which is the case).  In addtion Pirelli modified\nthe Broadcom code, so Alice Gate models use a different imagetag than any \nother vendor.\n\nThe imagetag format for flashing via CFE is the same for almost all the \nboards, and is the same for all images generated by the imagetag utility.\nImages flashable using cfe are labelled openwrt-<board>-<filesystem>-cfe.bin\n\nThe imagetags for tftp/ftp flashing is based on Broadcom 3.00-3.04 imagetags\nand is known to be correct as the source code GPL and is available for reading.\n\nBroadcom code 2.21 is based on the BT Voyager firmware image I looked at.  It\nmay in fact be BT Voyager-specific.  2.21 is actually more difficult to deal\nwith the imagetag from 3.00 as it has three different CRC calculations in\naddtition to the header CRC.\n\nBroadcom 3.00-3.02 flashing has been tested on Comtrend CT-5261, CT-536 and \nTecom GW6000, and is the version of the flashing that was present before the\nimagetags were split by broadcom code version (early June 2009)\n\n3.04 is guessed to be the same as 3.00-3.02 based on available information\n\nBroadom 3.06 is thought to be the same as 3.00-3.02, however the only 3.06 \nthis author (Daniel Dickinson) has seen is the Alice Gate (Pirelli) firmware\nwhich is known to be different due to vendor (Pirelli) modifications to the\nBroadcom code.\n\nBroadcom 3.10 uses an imagetag that is believed to apply to all 3.10 and 3.12\nversions, and has been tested on the Tecom GW6200.  This version introdec changes to\nthe imagetag to deal with TR69 (a remote rouer management system developed by the\nDSL forum).  There is a field for vendor-specific information, that at least in some\ncases is not optional.  It is based on the hexedit of a neufbox4 firmware image, the\ninformation in https://dev.openwrt.org/ticket/4987, and the hexedit of a Tecom\nGW6200 image.\n\nSome boards share the same tag format, but require vendor-specific fields in\nthe board.  In that case the tagid is shared, but the filename of the generated\nimage reflects the router for which the image was created.\n\nrouter        |method       | codever |filename\n+-------------+-------------+---------+---------------------------------------\n|any          |cfe+most web |   any   |openwrt-<board>-<fs>-cfe.bin\n|AGVoIP2+WiFi |cfe          |alice3.06|openwrt-AGV2+W-cfe-<fs>-cfe.bin\n|AGVoIP2+WiFi |web          |alice3.06|openwrt-AGV2+W-cfe-<fs>-cfe.bin\n|CT536        |web          |3.02     |openwrt-CT536_CT5621-<fs>-cfe.bin\n|CT5621       |web          |3.02     |openwrt-CT536_CT5621-<fs>-cfe.bin\n|DG834GT      |web          |3.02     |openwrt-DG834GT_DG834PN-<fs>-cfe.bin\n|DG834PN      |web          |3.02     |openwrt-DG834GT_DG834PN-<fs>-cfe.bin\n|DSL-2640B    |web          |3.10     |openwrt-DSL2640B-<fs>-cfe.bin\n|DSL-2740B    |web          |3.10     |openwrt-DSL2670B-<fs>-cfe.bin\n|F5D7633      |web          |3.10     |openwrt-F5D7633-<fs>-cfe.bin\n|F@ST2404     |web          |3.0X?    |openwrt-F@ST2404-cfe-<fs>-cfe.bin\n|F@ST2404     |web          |3.1X?    |openwrt-F@ST2404-<fs>-cfe.bin\n|GW6000       |web          |3.00     |openwrt-GW6000-<fs>-cfe.bin\n|GW6200       |web          |3.10     |openwrt-GW6200-<fs>-cfe.bin\n|Neufbox4     |web          |3.12     |openwrt-NEUFBOX4-<fs>-cfe.bin\n|TD8810A      |web          |3.06     |openwrt-TD8810-<fs>-cfe.bin\n|TD8810B      |web          |3.06     |openwrt-TD8810-<fs>-cfe.bin\n|TD8811A      |web          |3.06     |openwrt-TD8811-<fs>-cfe.bin\n|TD8811B      |web          |3.06     |openwrt-TD881-<fs>-cfe.bin\n|TD8900GB     |web          |3.06     |openwrt-TD8900DB<fs>-cfe.bin\n|USR9108      |web          |3.0X?    |openwrt-USR9108-<fs>-cfe.bin\n|V2091_BTR    |web          |2.21     |openwrt-V2091_BTR-<fs>-cfe.bin\n|V2091_ROI    |web          |2.21     |openwrt-V2091-<fs>-cfe.bin\n|V2091_WB     |web          |2.21     |openwrt-V2091-<fs>-cfe.bin\n|V210_BTR     |web          |2.21     |openwrt-V210_BTR-<fs>-cfe.bin\n|V210_ROI     |web          |2.21     |openwrt-V210-ROI_WB<fs>-cfe.bin\n|V210_WB      |web          |2.21     |openwrt-V210-ROI_WB<fs>-cfe.bin\n|V2110        |web          |2.21     |openwrt-V2110-<fs>-cfe.bin\n|V2110_AA     |web          |2.21     |openwrt-V2110-<fs>-cfe.bin\n|V2110_ROI    |web          |2.21     |openwrt-V2110-<fs>-cfe.bin\n|V2500V       |web          |2.21     |openwrt-V2500V<fs>-cfe.bin\n|V2500V_AA    |web          |2.21     |openwrt-V2500V-<fs>-cfe.bin\n|V2500V_SIP_CLUB |web       |2.21     |openwrt-V2500V-<fs>-cfe.bin\n\nOld imagetag routers\n--------------------\nDavolink DV201AMR\n\nRedboot routers\n---------------\nInventel Livebox\n\nKnown router->code versions\n---------------------------\n\nVendor                     |Model                                     |Code Ver\n---------------------------+------------------------------------------+--------\nBelkin                     |F5D7633                                   |3.10\nBritish Telecom (BT)       |Voyager V2091_BTR                         |2.21\nBritish Telecom (BT)       |Voyager V2091_ROI                         |2.21\nBritish Telecom (BT)       |Voyager V2091_WB                          |2.21\nBritish Telecom (BT)       |Voyager V210_BTR                          |2.21\nBritish Telecom (BT)       |Voyager V210_ROI                          |2.21\nBritish Telecom (BT)       |Voyager V210_WB                           |2.21\nBritish Telecom (BT)       |Voyager V2110                             |2.21\nBritish Telecom (BT)       |Voyager V2110_AA                          |2.21\nBritish Telecom (BT)       |Voyager V2110_ROI                         |2.21\nBritish Telecom (BT)       |Voyager V220V                             |2.21\nBritish Telecom (BT)       |Voyager V2500V                            |2.21\nBritish Telecom (BT)       |Voyager V2500V_AA                         |2.21\nBritish Telecom (BT)       |Voyager V2500V_SIP_CLUB                   |2.21\nComtrend                   |CT-5261                                   |3.02\nComtrend                   |CT-536                                    |3.02\nD-Link                     |DSL-2640B                                 |3.10\nD-Link                     |DSL-2670B                                 |3.10\nNetGear\t\t\t   |DG834GT\t\t\t\t      |3.02\nNetGear\t\t\t   |DG834PN\t\t\t\t      |3.02\nNeuf Cegetel               |Neufbox 4                                 |3.12\nPirelli                    |Alice Gate Wi-Fi (+VoIP models?)          |ag 3.06\nSagem\t\t\t   |F@ST2404\t\t\t\t      |?\nTP-Link                    |TD-8810A                                  |3.06\nTP-Link\t\t\t   |TD-8810B\t\t\t\t      |3.06\nTP-Link\t\t\t   |TD-8811A\t\t\t\t      |3.06\nTP-Link\t\t\t   |TD-8811B\t\t\t\t      |3.06\nTP-Link\t\t\t   |TD-W8900GB\t\t\t\t      |3.06\nTecom                      |GW6000                                    |3.00\nTecom                      |GW6200                                    |3.10\nUSR\t\t\t   |9108\t\t\t\t      |?\n\n"
  },
  {
    "path": "target/linux/bcm63xx/image/bcm63xx.mk",
    "content": "\n#\n# BCM33XX/BCM63XX Profiles\n#\n\nDEVICE_VARS += HCS_MAGIC_BYTES HCS_REV_MIN HCS_REV_MAJ\nDEVICE_VARS += BLOCK_SIZE FLASH_MB IMAGE_OFFSET\nDEVICE_VARS += CFE_BOARD_ID CFE_EXTRAS\nDEVICE_VARS += NETGEAR_BOARD_ID NETGEAR_REGION\nDEVICE_VARS += REDBOOT_PREFIX\n\ndefine Device/bcm33xx\n  KERNEL_INITRAMFS := kernel-bin | append-dtb | lzma | loader-lzma bin | hcs-initramfs\n  IMAGES :=\n  HCS_MAGIC_BYTES :=\n  HCS_REV_MIN :=\n  HCS_REV_MAJ :=\nendef\n\ndefine Device/bcm63xx\n  FILESYSTEMS := squashfs jffs2-64k jffs2-128k\n  KERNEL := kernel-bin | append-dtb | relocate-kernel | lzma\n  KERNEL_INITRAMFS := kernel-bin | append-dtb | lzma | loader-lzma elf\n  IMAGES := cfe.bin\n  IMAGE/cfe.bin := cfe-bin --pad $$$$(shell expr $$$$(FLASH_MB) / 2)\n  IMAGE/cfe-4M.bin := cfe-bin --pad 2\n  IMAGE/cfe-8M.bin := cfe-bin --pad 4\n  IMAGE/cfe-16M.bin := cfe-bin --pad 8\n  IMAGE/cfe-bc221.bin := cfe-bin --layoutver 5\n  IMAGE/cfe-old.bin := cfe-old-bin\n  IMAGE/sysupgrade.bin := cfe-bin\n  BLOCK_SIZE := 0x10000\n  IMAGE_OFFSET :=\n  FLASH_MB := 4\n  CFE_BOARD_ID :=\n  CFE_EXTRAS = --block-size $$(BLOCK_SIZE) --image-offset $$(if $$(IMAGE_OFFSET),$$(IMAGE_OFFSET),$$(BLOCK_SIZE))\nendef\n\ndefine Device/bcm63xx-legacy\n  $(Device/bcm63xx)\n  KERNEL := kernel-bin | append-dtb | relocate-kernel | lzma-cfe\nendef\n\ndefine Device/bcm63xx_netgear\n  $(Device/bcm63xx)\n  DEVICE_VENDOR := NETGEAR\n  IMAGES := factory.chk sysupgrade.bin\n  IMAGE/factory.chk := cfe-bin | netgear-chk\n  NETGEAR_BOARD_ID :=\n  NETGEAR_REGION :=\nendef\n\ndefine Device/bcm63xx_redboot\n  FILESYSTEMS := squashfs\n  KERNEL := kernel-bin | append-dtb | relocate-kernel | gzip\n  KERNEL_INITRAMFS := kernel-bin | append-dtb | lzma | loader-lzma elf\n  IMAGES := redboot.bin\n  IMAGE/redboot.bin := redboot-bin\n  REDBOOT_PREFIX := $$(DEVICE_IMG_PREFIX)\nendef\n\n### Generic ###\ndefine Device/brcm_bcm963281tan\n  $(Device/bcm63xx)\n  DEVICE_VENDOR := Generic\n  DEVICE_MODEL := 963281TAN\n  IMAGES := cfe-4M.bin cfe-8M.bin cfe-16M.bin\n  CFE_BOARD_ID := 963281TAN\n  CHIP_ID := 6328\nendef\nTARGET_DEVICES += brcm_bcm963281tan\n\ndefine Device/brcm_bcm96328avng\n  $(Device/bcm63xx)\n  DEVICE_VENDOR := Generic\n  DEVICE_MODEL := 96328avng\n  IMAGES := cfe-4M.bin cfe-8M.bin cfe-16M.bin\n  CFE_BOARD_ID := 96328avng\n  CHIP_ID := 6328\nendef\nTARGET_DEVICES += brcm_bcm96328avng\n\ndefine Device/brcm_bcm96338gw\n  $(Device/bcm63xx-legacy)\n  DEVICE_VENDOR := Generic\n  DEVICE_MODEL := 96338GW\n  CFE_BOARD_ID := 6338GW\n  CHIP_ID := 6338\nendef\nTARGET_DEVICES += brcm_bcm96338gw\n\ndefine Device/brcm_bcm96338w\n  $(Device/bcm63xx-legacy)\n  DEVICE_VENDOR := Generic\n  DEVICE_MODEL := 96338W\n  CFE_BOARD_ID := 6338W\n  CHIP_ID := 6338\n  DEFAULT := n\nendef\nTARGET_DEVICES += brcm_bcm96338w\n\ndefine Device/brcm_bcm96345gw2\n  $(Device/bcm63xx-legacy)\n  DEVICE_VENDOR := Generic\n  DEVICE_MODEL := 96345GW2\n  IMAGES += cfe-bc221.bin\n  CFE_BOARD_ID := 96345GW2\n  CHIP_ID := 6345\n  DEFAULT := n\nendef\nTARGET_DEVICES += brcm_bcm96345gw2\n\ndefine Device/brcm_bcm96348gw\n  $(Device/bcm63xx-legacy)\n  DEVICE_VENDOR := Generic\n  DEVICE_MODEL := 96348GW\n  IMAGES += cfe-bc221.bin\n  CFE_BOARD_ID := 96348GW\n  CHIP_ID := 6348\n  DEFAULT := n\nendef\nTARGET_DEVICES += brcm_bcm96348gw\n\ndefine Device/brcm_bcm96348gw-10\n  $(Device/bcm63xx-legacy)\n  DEVICE_VENDOR := Generic\n  DEVICE_MODEL := 96348GW-10\n  CFE_BOARD_ID := 96348GW-10\n  CHIP_ID := 6348\n  DEFAULT := n\nendef\nTARGET_DEVICES += brcm_bcm96348gw-10\n\ndefine Device/brcm_bcm96348gw-11\n  $(Device/bcm63xx-legacy)\n  DEVICE_VENDOR := Generic\n  DEVICE_MODEL := 96348GW-11\n  CFE_BOARD_ID := 96348GW-11\n  CHIP_ID := 6348\n  DEFAULT := n\nendef\nTARGET_DEVICES += brcm_bcm96348gw-11\n\ndefine Device/brcm_bcm96348r\n  $(Device/bcm63xx-legacy)\n  DEVICE_VENDOR := Generic\n  DEVICE_MODEL := 96348R\n  CFE_BOARD_ID := 96348R\n  CHIP_ID := 6348\n  DEFAULT := n\nendef\nTARGET_DEVICES += brcm_bcm96348r\n\ndefine Device/brcm_bcm96358vw\n  $(Device/bcm63xx-legacy)\n  DEVICE_VENDOR := Generic\n  DEVICE_MODEL := 96358VW\n  CFE_BOARD_ID := 96358VW\n  CHIP_ID := 6358\nendef\nTARGET_DEVICES += brcm_bcm96358vw\n\ndefine Device/brcm_bcm96358vw2\n  $(Device/bcm63xx-legacy)\n  DEVICE_VENDOR := Generic\n  DEVICE_MODEL := 96358VW2\n  CFE_BOARD_ID := 96358VW2\n  CHIP_ID := 6358\nendef\nTARGET_DEVICES += brcm_bcm96358vw2\n\ndefine Device/brcm_bcm96368mvngr\n  $(Device/bcm63xx)\n  DEVICE_VENDOR := Generic\n  DEVICE_MODEL := 96368MVNgr\n  CFE_BOARD_ID := 96368MVNgr\n  CHIP_ID := 6368\nendef\nTARGET_DEVICES += brcm_bcm96368mvngr\n\ndefine Device/brcm_bcm96368mvwg\n  $(Device/bcm63xx)\n  DEVICE_VENDOR := Generic\n  DEVICE_MODEL := 96368MVWG\n  CFE_BOARD_ID := 96368MVWG\n  CHIP_ID := 6368\nendef\nTARGET_DEVICES += brcm_bcm96368mvwg\n\n### Actiontec ###\ndefine Device/actiontec_r1000h\n  $(Device/bcm63xx)\n  DEVICE_VENDOR := Actiontec\n  DEVICE_MODEL := R1000H\n  FILESYSTEMS := squashfs\n  CFE_BOARD_ID := 96368MVWG\n  CHIP_ID := 6368\n  FLASH_MB := 32\n  IMAGE_OFFSET := 0x20000\n  DEVICE_PACKAGES := $(USB2_PACKAGES) $(BRCMWL_PACKAGES)\nendef\nTARGET_DEVICES += actiontec_r1000h\n\n### ADB ###\ndefine Device/adb_a4001n\n  $(Device/bcm63xx)\n  DEVICE_VENDOR := ADB\n  DEVICE_MODEL := P.DG A4001N\n  CFE_BOARD_ID := 96328dg2x2\n  CHIP_ID := 6328\n  FLASH_MB := 8\n  DEVICE_PACKAGES := $(USB2_PACKAGES) $(B43_PACKAGES)\nendef\nTARGET_DEVICES += adb_a4001n\n\ndefine Device/adb_a4001n1\n  $(Device/bcm63xx)\n  DEVICE_VENDOR := ADB\n  DEVICE_MODEL := P.DG A4001N1\n  IMAGES += sysupgrade.bin\n  CFE_BOARD_ID := 963281T_TEF\n  CHIP_ID := 6328\n  FLASH_MB := 16\n  DEVICE_PACKAGES := $(USB2_PACKAGES) $(B43_PACKAGES)\nendef\nTARGET_DEVICES += adb_a4001n1\n\ndefine Device/adb_pdg-a4001n-a-000-1a1-ax\n  $(Device/bcm63xx)\n  DEVICE_VENDOR := ADB\n  DEVICE_MODEL := P.DG A4001N A-000-1A1-AX\n  IMAGES += sysupgrade.bin\n  CFE_BOARD_ID := 96328avng\n  CHIP_ID := 6328\n  FLASH_MB := 16\n  DEVICE_PACKAGES := $(USB2_PACKAGES) $(B43_PACKAGES)\nendef\nTARGET_DEVICES += adb_pdg-a4001n-a-000-1a1-ax\n\ndefine Device/adb_pdg-a4101n-a-000-1a1-ae\n  $(Device/bcm63xx)\n  DEVICE_VENDOR := ADB\n  DEVICE_MODEL := P.DG A4101N A-000-1A1-AE\n  IMAGES += sysupgrade.bin\n  CFE_BOARD_ID := 96328avngv\n  CHIP_ID := 6328\n  FLASH_MB := 16\n  DEVICE_PACKAGES := $(USB2_PACKAGES) $(B43_PACKAGES)\nendef\nTARGET_DEVICES += adb_pdg-a4101n-a-000-1a1-ae\n\ndefine Device/adb_av4202n\n  $(Device/bcm63xx)\n  DEVICE_VENDOR := ADB\n  DEVICE_MODEL := P.DG AV4202N\n  IMAGE_OFFSET := 0x20000\n  CFE_BOARD_ID := 96368_Swiss_S1\n  CHIP_ID := 6368\n  DEVICE_PACKAGES := $(USB2_PACKAGES) $(B43_PACKAGES)\nendef\nTARGET_DEVICES += adb_av4202n\n\n### Alcatel ###\ndefine Device/alcatel_rg100a\n  $(Device/bcm63xx-legacy)\n  DEVICE_VENDOR := Alcatel\n  DEVICE_MODEL := RG100A\n  CFE_BOARD_ID := 96358VW2\n  CHIP_ID := 6358\n  BLOCK_SIZE := 0x20000\n  DEVICE_PACKAGES := $(USB2_PACKAGES) $(B43_PACKAGES)\nendef\nTARGET_DEVICES += alcatel_rg100a\n\n### Asmax ###\ndefine Device/asmax_ar-1004g\n  $(Device/bcm63xx-legacy)\n  DEVICE_VENDOR := Asmax\n  DEVICE_MODEL := AR 1004g\n  CFE_BOARD_ID := 96348GW-10\n  CHIP_ID := 6348\n  DEVICE_PACKAGES := $(B43_PACKAGES)\n  DEFAULT := n\nendef\nTARGET_DEVICES += asmax_ar-1004g\n\n### Belkin ###\ndefine Device/belkin_f5d7633\n  $(Device/bcm63xx-legacy)\n  DEVICE_VENDOR := Belkin\n  DEVICE_MODEL := F5D7633\n  CFE_BOARD_ID := 96348GW-10\n  CHIP_ID := 6348\n  BLOCK_SIZE := 0x20000\n  DEVICE_PACKAGES := $(B43_PACKAGES)\n  DEFAULT := n\nendef\nTARGET_DEVICES += belkin_f5d7633\n\n### Broadcom ###\ndefine Device/brcm_bcm96318ref\n  $(Device/bcm63xx)\n  DEVICE_VENDOR := Broadcom\n  DEVICE_MODEL := BCM96318REF reference board\n  IMAGES :=\n  CFE_BOARD_ID := 96318REF\n  CHIP_ID := 6318\n  DEVICE_PACKAGES := $(B43_PACKAGES) $(USB2_PACKAGES) kmod-bcm63xx-udc\nendef\nTARGET_DEVICES += brcm_bcm96318ref\n\ndefine Device/brcm_bcm96318ref-p300\n  $(Device/bcm63xx)\n  DEVICE_VENDOR := Broadcom\n  DEVICE_MODEL := BCM96318REF_P300 reference board\n  IMAGES :=\n  CFE_BOARD_ID := 96318REF_P300\n  CHIP_ID := 6318\n  DEVICE_PACKAGES := $(B43_PACKAGES) $(USB2_PACKAGES) kmod-bcm63xx-udc\nendef\nTARGET_DEVICES += brcm_bcm96318ref-p300\n\ndefine Device/brcm_bcm963268bu-p300\n  $(Device/bcm63xx)\n  DEVICE_VENDOR := Broadcom\n  DEVICE_MODEL := BCM963268BU_P300 reference board\n  IMAGES :=\n  CFE_BOARD_ID := 963268BU_P300\n  CHIP_ID := 63268\n  DEVICE_PACKAGES := $(USB2_PACKAGES) kmod-bcm63xx-udc\nendef\nTARGET_DEVICES += brcm_bcm963268bu-p300\n\ndefine Device/brcm_bcm963269bhr\n  $(Device/bcm63xx)\n  DEVICE_VENDOR := Broadcom\n  DEVICE_MODEL := BCM963269BHR reference board\n  IMAGES :=\n  CFE_BOARD_ID := 963269BHR\n  CHIP_ID := 63268\n  SOC := bcm63269\n  DEVICE_PACKAGES := $(USB2_PACKAGES) kmod-bcm63xx-udc\nendef\nTARGET_DEVICES += brcm_bcm963269bhr\n\n### BT ###\ndefine Device/bt_home-hub-2-a\n  $(Device/bcm63xx-legacy)\n  DEVICE_VENDOR := British Telecom (BT)\n  DEVICE_MODEL := Home Hub 2.0\n  DEVICE_VARIANT := A\n  CFE_BOARD_ID := HOMEHUB2A\n  CHIP_ID := 6358\n  BLOCK_SIZE := 0x20000\n  DEVICE_PACKAGES := $(B43_PACKAGES) $(USB2_PACKAGES)\nendef\nTARGET_DEVICES += bt_home-hub-2-a\n\ndefine Device/bt_voyager-2110\n  $(Device/bcm63xx-legacy)\n  DEVICE_VENDOR := British Telecom (BT)\n  DEVICE_MODEL := Voyager 2110\n  CFE_BOARD_ID := V2110\n  CHIP_ID := 6348\n  CFE_EXTRAS += --layoutver 5\n  DEVICE_PACKAGES := $(B43_PACKAGES)\n  DEFAULT := n\nendef\nTARGET_DEVICES += bt_voyager-2110\n\ndefine Device/bt_voyager-2500v-bb\n  $(Device/bcm63xx-legacy)\n  DEVICE_VENDOR := British Telecom (BT)\n  DEVICE_MODEL := Voyager 2500V\n  CFE_BOARD_ID := V2500V_BB\n  CHIP_ID := 6348\n  CFE_EXTRAS += --layoutver 5\n  DEVICE_PACKAGES := $(B43_PACKAGES)\n  DEFAULT := n\nendef\nTARGET_DEVICES += bt_voyager-2500v-bb\n\n### Comtrend ###\ndefine Device/comtrend_ar-5315u\n  $(Device/bcm63xx)\n  DEVICE_VENDOR := Comtrend\n  DEVICE_MODEL := AR-5315u\n  IMAGES += sysupgrade.bin\n  CFE_BOARD_ID := 96318A-1441N1\n  CHIP_ID := 6318\n  FLASH_MB := 16\n  DEVICE_PACKAGES := $(B43_PACKAGES) $(USB2_PACKAGES)\nendef\nTARGET_DEVICES += comtrend_ar-5315u\n\ndefine Device/comtrend_ar-5381u\n  $(Device/bcm63xx)\n  DEVICE_VENDOR := Comtrend\n  DEVICE_MODEL := AR-5381u\n  IMAGES += sysupgrade.bin\n  CFE_BOARD_ID := 96328A-1241N\n  CHIP_ID := 6328\n  FLASH_MB := 16\n  DEVICE_PACKAGES := $(B43_PACKAGES) $(USB2_PACKAGES)\nendef\nTARGET_DEVICES += comtrend_ar-5381u\n\ndefine Device/comtrend_ar-5387un\n  $(Device/bcm63xx)\n  DEVICE_VENDOR := Comtrend\n  DEVICE_MODEL := AR-5387un\n  IMAGES += sysupgrade.bin\n  CFE_BOARD_ID := 96328A-1441N1\n  CHIP_ID := 6328\n  FLASH_MB := 16\n  DEVICE_PACKAGES := $(B43_PACKAGES) $(USB2_PACKAGES)\nendef\nTARGET_DEVICES += comtrend_ar-5387un\n\ndefine Device/comtrend_ct-536plus\n  $(Device/bcm63xx-legacy)\n  DEVICE_VENDOR := Comtrend\n  DEVICE_MODEL := CT-536+\n  DEVICE_ALT0_VENDOR := Comtrend\n  DEVICE_ALT0_MODEL := CT-5621\n  CFE_BOARD_ID := 96348GW-11\n  CHIP_ID := 6348\n  DEVICE_PACKAGES := $(B43_PACKAGES)\n  DEFAULT := n\nendef\nTARGET_DEVICES += comtrend_ct-536plus\n\ndefine Device/comtrend_ct-5365\n  $(Device/bcm63xx-legacy)\n  DEVICE_VENDOR := Comtrend\n  DEVICE_MODEL := CT-5365\n  CFE_BOARD_ID := 96348A-122\n  CHIP_ID := 6348\n  DEVICE_PACKAGES := $(B43_PACKAGES)\n  DEFAULT := n\nendef\nTARGET_DEVICES += comtrend_ct-5365\n\ndefine Device/comtrend_ct-6373\n  $(Device/bcm63xx-legacy)\n  DEVICE_VENDOR := Comtrend\n  DEVICE_MODEL := CT-6373\n  CFE_BOARD_ID := CT6373-1\n  CHIP_ID := 6358\n  DEVICE_PACKAGES := $(B43_PACKAGES) $(USB2_PACKAGES)\nendef\nTARGET_DEVICES += comtrend_ct-6373\n\ndefine Device/comtrend_vr-3025u\n  $(Device/bcm63xx)\n  DEVICE_VENDOR := Comtrend\n  DEVICE_MODEL := VR-3025u\n  IMAGES += sysupgrade.bin\n  CFE_BOARD_ID := 96368M-1541N\n  CHIP_ID := 6368\n  BLOCK_SIZE := 0x20000\n  FLASH_MB := 32\n  DEVICE_PACKAGES := $(B43_PACKAGES) $(USB2_PACKAGES)\nendef\nTARGET_DEVICES += comtrend_vr-3025u\n\ndefine Device/comtrend_vr-3025un\n  $(Device/bcm63xx)\n  DEVICE_VENDOR := Comtrend\n  DEVICE_MODEL := VR-3025un\n  CFE_BOARD_ID := 96368M-1341N\n  CHIP_ID := 6368\n  FLASH_MB := 8\n  DEVICE_PACKAGES := $(B43_PACKAGES) $(USB2_PACKAGES)\nendef\nTARGET_DEVICES += comtrend_vr-3025un\n\ndefine Device/comtrend_vr-3026e\n  $(Device/bcm63xx)\n  DEVICE_VENDOR := Comtrend\n  DEVICE_MODEL := VR-3026e\n  CFE_BOARD_ID := 96368MT-1341N1\n  CHIP_ID := 6368\n  FLASH_MB := 8\n  DEVICE_PACKAGES := $(B43_PACKAGES)\nendef\nTARGET_DEVICES += comtrend_vr-3026e\n\ndefine Device/comtrend_wap-5813n\n  $(Device/bcm63xx)\n  DEVICE_VENDOR := Comtrend\n  DEVICE_MODEL := WAP-5813n\n  CFE_BOARD_ID := 96369R-1231N\n  CHIP_ID := 6368\n  FLASH_MB := 8\n  SOC := bcm6369\n  DEVICE_PACKAGES := $(B43_PACKAGES) $(USB2_PACKAGES)\nendef\nTARGET_DEVICES += comtrend_wap-5813n\n\n### D-Link ###\ndefine Device/d-link_dsl-2640b-b\n  $(Device/bcm63xx-legacy)\n  DEVICE_VENDOR := D-Link\n  DEVICE_MODEL := DSL-2640B\n  DEVICE_VARIANT := B2\n  CFE_BOARD_ID := D-4P-W\n  CHIP_ID := 6348\n  DEVICE_PACKAGES := $(B43_PACKAGES)\n  DEFAULT := n\nendef\nTARGET_DEVICES += d-link_dsl-2640b-b\n\ndefine Device/d-link_dsl-2640u\n  $(Device/bcm63xx-legacy)\n  DEVICE_VENDOR := D-Link\n  DEVICE_MODEL := DSL-2640U\n  DEVICE_VARIANT := C1\n  DEVICE_ALT0_VENDOR := D-Link\n  DEVICE_ALT0_MODEL := DSL-2640U/BRU/C\n  CFE_BOARD_ID := 96338W2_E7T\n  CHIP_ID := 6338\n  DEVICE_PACKAGES := $(B43_PACKAGES)\n  DEFAULT := n\nendef\nTARGET_DEVICES += d-link_dsl-2640u\n\ndefine Device/d-link_dsl-2650u\n  $(Device/bcm63xx-legacy)\n  DEVICE_VENDOR := D-Link\n  DEVICE_MODEL := DSL-2650U\n  CFE_BOARD_ID := 96358VW2\n  CHIP_ID := 6358\n  DEVICE_PACKAGES := $(B43_PACKAGES) $(USB2_PACKAGES)\nendef\nTARGET_DEVICES += d-link_dsl-2650u\n\ndefine Device/d-link_dsl-274xb-c2\n  $(Device/bcm63xx-legacy)\n  DEVICE_VENDOR := D-Link\n  DEVICE_MODEL := DSL-2740B\n  DEVICE_VARIANT := C2\n  DEVICE_ALT0_VENDOR := D-Link\n  DEVICE_ALT0_MODEL := DSL-2741B\n  DEVICE_ALT0_VARIANT := C2\n  CFE_BOARD_ID := 96358GW\n  CHIP_ID := 6358\n  DEVICE_PACKAGES := $(B43_PACKAGES)\n  DEFAULT := n\nendef\nTARGET_DEVICES += d-link_dsl-274xb-c2\n\ndefine Device/d-link_dsl-274xb-c3\n  $(Device/bcm63xx-legacy)\n  DEVICE_VENDOR := D-Link\n  DEVICE_MODEL := DSL-2740B\n  DEVICE_VARIANT := C3\n  DEVICE_ALT0_VENDOR := D-Link\n  DEVICE_ALT0_MODEL := DSL-2741B\n  DEVICE_ALT0_VARIANT := C3\n  DEVICE_DTS := bcm6358-d-link-dsl-274xb-c2\n  CFE_BOARD_ID := AW4139\n  CHIP_ID := 6358\n  DEVICE_PACKAGES := $(B43_PACKAGES)\n  DEFAULT := n\nendef\nTARGET_DEVICES += d-link_dsl-274xb-c3\n\ndefine Device/d-link_dsl-274xb-f1\n  $(Device/bcm63xx)\n  DEVICE_VENDOR := D-Link\n  DEVICE_MODEL := DSL-2740B\n  DEVICE_VARIANT := F1\n  DEVICE_ALT0_VENDOR := D-Link\n  DEVICE_ALT0_MODEL := DSL-2741B\n  DEVICE_ALT0_VARIANT := F1\n  CFE_BOARD_ID := AW4339U\n  CHIP_ID := 6328\n  IMAGES := cfe-EU.bin cfe-AU.bin\n  IMAGE/cfe-AU.bin := cfe-bin --signature2 \"4.06.01.AUF1\" --pad 4\n  IMAGE/cfe-EU.bin := cfe-bin --signature2 \"4.06.01.EUF1\" --pad 4\n  DEVICE_PACKAGES := $(ATH9K_PACKAGES)\nendef\nTARGET_DEVICES += d-link_dsl-274xb-f1\n\ndefine Device/d-link_dsl-2750u-c1\n  $(Device/bcm63xx)\n  DEVICE_VENDOR := D-Link\n  DEVICE_MODEL := DSL-2750U\n  DEVICE_VARIANT := C1\n  IMAGES += sysupgrade.bin\n  CFE_BOARD_ID := 963281TAVNG\n  CHIP_ID := 6328\n  FLASH_MB := 8\n  DEVICE_PACKAGES := $(USB2_PACKAGES) $(B43_PACKAGES)\nendef\nTARGET_DEVICES += d-link_dsl-2750u-c1\n\ndefine Device/d-link_dsl-275xb-d1\n  $(Device/bcm63xx)\n  DEVICE_VENDOR := D-Link\n  DEVICE_MODEL := DSL-2750B\n  DEVICE_VARIANT := D1\n  DEVICE_ALT0_VENDOR := D-Link\n  DEVICE_ALT0_MODEL := DSL-2751\n  DEVICE_ALT0_VARIANT := D1\n  CFE_BOARD_ID := AW5200B\n  CHIP_ID := 6318\n  FLASH_MB := 8\n  DEVICE_PACKAGES := $(B43_PACKAGES) $(USB2_PACKAGES)\nendef\nTARGET_DEVICES += d-link_dsl-275xb-d1\n\ndefine Device/d-link_dva-g3810bn-tl\n  $(Device/bcm63xx-legacy)\n  DEVICE_VENDOR := D-Link\n  DEVICE_MODEL := DVA-G3810BN/TL\n  CFE_BOARD_ID := 96358VW\n  CHIP_ID := 6358\n  DEVICE_PACKAGES := $(B43_PACKAGES) $(USB2_PACKAGES)\nendef\nTARGET_DEVICES += d-link_dva-g3810bn-tl\n\n### Davolink ###\ndefine Device/davolink_dv-201amr\n  $(Device/bcm63xx-legacy)\n  DEVICE_VENDOR := Davolink\n  DEVICE_MODEL := DV-201AMR\n  IMAGES := cfe-old.bin\n  CFE_BOARD_ID := DV201AMR\n  CHIP_ID := 6348\n  DEVICE_PACKAGES := $(B43_PACKAGES)\n  DEFAULT := n\nendef\nTARGET_DEVICES += davolink_dv-201amr\n\n### Dynalink ###\ndefine Device/dynalink_rta770bw\n  $(Device/bcm63xx-legacy)\n  DEVICE_VENDOR := Dynalink\n  DEVICE_MODEL := RTA770BW\n  DEVICE_ALT0_VENDOR := Siemens\n  DEVICE_ALT0_MODEL := SE515\n  IMAGES =\n  CFE_BOARD_ID := RTA770BW\n  CHIP_ID := 6345\n  CFE_EXTRAS += --layoutver 5\n  DEVICE_PACKAGES := $(B43_PACKAGES)\n  DEFAULT := n\nendef\nTARGET_DEVICES += dynalink_rta770bw\n\ndefine Device/dynalink_rta770w\n  $(Device/bcm63xx-legacy)\n  DEVICE_VENDOR := Dynalink\n  DEVICE_MODEL := RTA770W\n  IMAGES =\n  CFE_BOARD_ID := RTA770W\n  CHIP_ID := 6345\n  CFE_EXTRAS += --layoutver 5\n  DEVICE_PACKAGES := $(B43_PACKAGES)\n  DEFAULT := n\nendef\nTARGET_DEVICES += dynalink_rta770w\n\ndefine Device/dynalink_rta1025w\n  $(Device/bcm63xx-legacy)\n  DEVICE_VENDOR := Dynalink\n  DEVICE_MODEL := RTA1025W\n  CFE_BOARD_ID := RTA1025W_16\n  CHIP_ID := 6348\n  CFE_EXTRAS += --layoutver 5\n  DEVICE_PACKAGES := $(B43_PACKAGES)\n  DEFAULT := n\nendef\nTARGET_DEVICES += dynalink_rta1025w\n\ndefine Device/dynalink_rta1320\n  $(Device/bcm63xx-legacy)\n  DEVICE_VENDOR := Dynalink\n  DEVICE_MODEL := RTA1320\n  CFE_BOARD_ID := RTA1320_16M\n  CHIP_ID := 6338\n  CFE_EXTRAS += --layoutver 5\n  DEFAULT := n\nendef\nTARGET_DEVICES += dynalink_rta1320\n\n### Huawei ###\ndefine Device/huawei_echolife-hg520v\n  $(Device/bcm63xx-legacy)\n  DEVICE_VENDOR := Huawei\n  DEVICE_MODEL := EchoLife HG520v\n  CFE_BOARD_ID := HW6358GW_B\n  CHIP_ID := 6358\n  CFE_EXTRAS += --rsa-signature \"EchoLife_HG520v\"\n  SOC := bcm6359\n  DEVICE_PACKAGES := $(B43_PACKAGES)\n  DEFAULT := n\nendef\nTARGET_DEVICES += huawei_echolife-hg520v\n\ndefine Device/huawei_echolife-hg553\n  $(Device/bcm63xx-legacy)\n  DEVICE_VENDOR := Huawei\n  DEVICE_MODEL := EchoLife HG553\n  CFE_BOARD_ID := HW553\n  CHIP_ID := 6358\n  CFE_EXTRAS += --rsa-signature \"EchoLife_HG553\" --tag-version 7\n  BLOCK_SIZE := 0x20000\n  DEVICE_PACKAGES := $(B43_PACKAGES) $(USB2_PACKAGES)\nendef\nTARGET_DEVICES += huawei_echolife-hg553\n\ndefine Device/huawei_echolife-hg556a-a\n  $(Device/bcm63xx-legacy)\n  DEVICE_VENDOR := Huawei\n  DEVICE_MODEL := EchoLife HG556a\n  DEVICE_VARIANT := A\n  DEVICE_DESCRIPTION = Build firmware images for Huawei HG556a version A (Atheros)\n  CFE_BOARD_ID := HW556\n  CHIP_ID := 6358\n  CFE_EXTRAS += --rsa-signature \"EchoLife_HG556a\" --tag-version 8\n  IMAGE_OFFSET := 0x20000\n  DEVICE_PACKAGES := $(ATH9K_PACKAGES) $(USB2_PACKAGES)\nendef\nTARGET_DEVICES += huawei_echolife-hg556a-a\n\ndefine Device/huawei_echolife-hg556a-b\n  $(Device/bcm63xx-legacy)\n  DEVICE_VENDOR := Huawei\n  DEVICE_MODEL := EchoLife HG556a\n  DEVICE_VARIANT := B\n  DEVICE_DESCRIPTION = Build firmware images for Huawei HG556a version B (Atheros)\n  CFE_BOARD_ID := HW556\n  CHIP_ID := 6358\n  CFE_EXTRAS += --rsa-signature \"EchoLife_HG556a\" --tag-version 8\n  BLOCK_SIZE := 0x20000\n  DEVICE_PACKAGES := $(ATH9K_PACKAGES) $(USB2_PACKAGES)\nendef\nTARGET_DEVICES += huawei_echolife-hg556a-b\n\ndefine Device/huawei_echolife-hg556a-c\n  $(Device/bcm63xx-legacy)\n  DEVICE_VENDOR := Huawei\n  DEVICE_MODEL := EchoLife HG556a\n  DEVICE_VARIANT := C\n  DEVICE_DESCRIPTION = Build firmware images for Huawei HG556a version C (Ralink)\n  CFE_BOARD_ID := HW556\n  CHIP_ID := 6358\n  CFE_EXTRAS += --rsa-signature \"EchoLife_HG556a\" --tag-version 8\n  BLOCK_SIZE := 0x20000\n  DEVICE_PACKAGES := $(RT28_PACKAGES) $(USB2_PACKAGES)\nendef\nTARGET_DEVICES += huawei_echolife-hg556a-c\n\ndefine Device/huawei_echolife-hg622\n  $(Device/bcm63xx)\n  DEVICE_VENDOR := Huawei\n  DEVICE_MODEL := EchoLife HG622\n  IMAGES += sysupgrade.bin\n  CFE_BOARD_ID := 96368MVWG_hg622\n  CHIP_ID := 6368\n  CFE_EXTRAS += --tag-version 7\n  BLOCK_SIZE := 0x20000\n  FLASH_MB := 16\n  DEVICE_PACKAGES := $(RT28_PACKAGES) $(USB2_PACKAGES)\nendef\nTARGET_DEVICES += huawei_echolife-hg622\n\ndefine Device/huawei_echolife-hg655b\n  $(Device/bcm63xx)\n  DEVICE_VENDOR := Huawei\n  DEVICE_MODEL := EchoLife HG655b\n  CFE_BOARD_ID := HW65x\n  CHIP_ID := 6368\n  CFE_EXTRAS += --tag-version 7\n  IMAGE_OFFSET := 0x20000\n  FLASH_MB := 8\n  DEVICE_PACKAGES := $(RT28_PACKAGES) $(USB2_PACKAGES)\nendef\nTARGET_DEVICES += huawei_echolife-hg655b\n\n### Innacomm ###\ndefine Device/innacomm_w3400v6\n  $(Device/bcm63xx)\n  DEVICE_VENDOR := Innacomm\n  DEVICE_MODEL := W3400V6\n  CFE_BOARD_ID := 96328ang\n  CHIP_ID := 6328\n  FLASH_MB := 8\n  DEVICE_PACKAGES := $(B43_PACKAGES)\nendef\nTARGET_DEVICES += innacomm_w3400v6\n\n### Inteno ###\ndefine Device/inteno_vg50\n  $(Device/bcm63xx)\n  DEVICE_VENDOR := Inteno\n  DEVICE_MODEL := VG50 Multi-WAN CPE\n  IMAGES :=\n  CFE_BOARD_ID := VW6339GU\n  CHIP_ID := 63268\n  DEVICE_PACKAGES := $(USB2_PACKAGES)\nendef\nTARGET_DEVICES += inteno_vg50\n\n### Inventel ###\ndefine Device/inventel_livebox-1\n  $(Device/bcm63xx_redboot)\n  DEVICE_VENDOR := Inventel\n  DEVICE_MODEL := Livebox 1\n  SOC := bcm6348\n  DEVICE_PACKAGES := $(B43_PACKAGES) $(USB1_PACKAGES)\n  DEFAULT := n\nendef\nTARGET_DEVICES += inventel_livebox-1\n\n### Netgear ###\ndefine Device/netgear_cvg834g\n  $(Device/bcm33xx)\n  DEVICE_VENDOR := NETGEAR\n  DEVICE_MODEL := CVG834G\n  CHIP_ID := 3368\n  HCS_MAGIC_BYTES := 0xa020\n  HCS_REV_MIN := 0001\n  HCS_REV_MAJ := 0022\nendef\nTARGET_DEVICES += netgear_cvg834g\n\ndefine Device/netgear_dg834gt-pn\n  $(Device/bcm63xx-legacy)\n  DEVICE_VENDOR := NETGEAR\n  DEVICE_MODEL := DG834GT\n  DEVICE_ALT0_VENDOR := NETGEAR\n  DEVICE_ALT0_MODEL := DG834PN\n  CFE_BOARD_ID := 96348GW-10\n  CHIP_ID := 6348\n  DEVICE_PACKAGES := $(ATH5K_PACKAGES)\n  DEFAULT := n\nendef\nTARGET_DEVICES += netgear_dg834gt-pn\n\ndefine Device/netgear_dg834g-v4\n  $(Device/bcm63xx-legacy)\n  DEVICE_VENDOR := NETGEAR\n  DEVICE_MODEL := DG834G\n  DEVICE_VARIANT := v4\n  IMAGES :=\n  CFE_BOARD_ID := 96348W3\n  CHIP_ID := 6348\n  DEVICE_PACKAGES := $(B43_PACKAGES)\n  DEFAULT := n\nendef\nTARGET_DEVICES += netgear_dg834g-v4\n\ndefine Device/netgear_dgnd3700-v1\n  $(Device/bcm63xx_netgear)\n  DEVICE_MODEL := DGND3700\n  DEVICE_VARIANT := v1\n  CFE_BOARD_ID := 96368MVWG\n  CHIP_ID := 6368\n  BLOCK_SIZE := 0x20000\n  NETGEAR_BOARD_ID := U12L144T01_NETGEAR_NEWLED\n  NETGEAR_REGION := 1\n  DEVICE_PACKAGES := $(B43_PACKAGES) $(USB2_PACKAGES)\nendef\nTARGET_DEVICES += netgear_dgnd3700-v1\n\ndefine Device/netgear_dgnd3800b\n  $(Device/bcm63xx_netgear)\n  DEVICE_MODEL := DGND3800B\n  DEVICE_DTS := bcm6368-netgear-dgnd3700-v1\n  CFE_BOARD_ID := 96368MVWG\n  CHIP_ID := 6368\n  BLOCK_SIZE := 0x20000\n  NETGEAR_BOARD_ID := U12L144T11_NETGEAR_NEWLED\n  NETGEAR_REGION := 1\n  DEVICE_PACKAGES := $(B43_PACKAGES) $(USB2_PACKAGES)\nendef\nTARGET_DEVICES += netgear_dgnd3800b\n\ndefine Device/netgear_evg2000\n  $(Device/bcm63xx_netgear)\n  DEVICE_MODEL := EVG2000\n  CFE_BOARD_ID := 96369PVG\n  CHIP_ID := 6368\n  BLOCK_SIZE := 0x20000\n  NETGEAR_BOARD_ID := U12H154T90_NETGEAR\n  NETGEAR_REGION := 1\n  SOC := bcm6369\n  DEVICE_PACKAGES := $(B43_PACKAGES) $(USB2_PACKAGES)\nendef\nTARGET_DEVICES += netgear_evg2000\n\n### NuCom ###\ndefine Device/nucom_r5010un-v2\n  $(Device/bcm63xx)\n  DEVICE_VENDOR := NuCom\n  DEVICE_MODEL := R5010UN\n  DEVICE_VARIANT := v2\n  IMAGES += sysupgrade.bin\n  CFE_BOARD_ID := 96328ang\n  CHIP_ID := 6328\n  FLASH_MB := 16\n  DEVICE_PACKAGES := $(B43_PACKAGES)\nendef\nTARGET_DEVICES += nucom_r5010un-v2\n\n### Observa ###\ndefine Device/observa_vh4032n\n  $(Device/bcm63xx)\n  DEVICE_VENDOR := Observa\n  DEVICE_MODEL := VH4032N\n  IMAGES += sysupgrade.bin\n  CFE_BOARD_ID := 96368VVW\n  CHIP_ID := 6368\n  BLOCK_SIZE := 0x20000\n  FLASH_MB := 32\n  DEVICE_PACKAGES := $(B43_PACKAGES) $(USB2_PACKAGES)\nendef\nTARGET_DEVICES += observa_vh4032n\n\n### Pirelli ###\ndefine Device/pirelli_a226g\n  $(Device/bcm63xx-legacy)\n  DEVICE_VENDOR := Pirelli\n  DEVICE_MODEL := A226G\n  CFE_BOARD_ID := DWV-S0\n  CHIP_ID := 6358\n  CFE_EXTRAS += --signature2 IMAGE --tag-version 8\n  DEVICE_PACKAGES := $(B43_PACKAGES) $(USB2_PACKAGES)\nendef\nTARGET_DEVICES += pirelli_a226g\n\ndefine Device/pirelli_a226m\n  $(Device/bcm63xx-legacy)\n  DEVICE_VENDOR := Pirelli\n  DEVICE_MODEL := A226M\n  CFE_BOARD_ID := DWV-S0\n  CHIP_ID := 6358\n  CFE_EXTRAS += --signature2 IMAGE --tag-version 8\n  DEVICE_PACKAGES := $(USB2_PACKAGES)\nendef\nTARGET_DEVICES += pirelli_a226m\n\ndefine Device/pirelli_a226m-fwb\n  $(Device/bcm63xx-legacy)\n  DEVICE_VENDOR := Pirelli\n  DEVICE_MODEL := A226M-FWB\n  CFE_BOARD_ID := DWV-S0\n  CHIP_ID := 6358\n  CFE_EXTRAS += --signature2 IMAGE --tag-version 8\n  BLOCK_SIZE := 0x20000\n  DEVICE_PACKAGES := $(USB2_PACKAGES)\nendef\nTARGET_DEVICES += pirelli_a226m-fwb\n\ndefine Device/pirelli_agpf-s0\n  $(Device/bcm63xx-legacy)\n  DEVICE_VENDOR := Pirelli\n  DEVICE_MODEL := Alice Gate VoIP 2 Plus Wi-Fi AGPF-S0\n  CFE_BOARD_ID := AGPF-S0\n  CHIP_ID := 6358\n  CFE_EXTRAS += --signature2 IMAGE --tag-version 8\n  BLOCK_SIZE := 0x20000\n  DEVICE_PACKAGES := $(B43_PACKAGES) $(USB2_PACKAGES)\nendef\nTARGET_DEVICES += pirelli_agpf-s0\n\n### Sagem ###\ndefine Device/sagem_fast-2404\n  $(Device/bcm63xx-legacy)\n  DEVICE_VENDOR := Sagemcom\n  DEVICE_MODEL := F@st 2404\n  CFE_BOARD_ID := F@ST2404\n  CHIP_ID := 6348\n  DEVICE_PACKAGES := $(B43_PACKAGES)\n  DEFAULT := n\nendef\nTARGET_DEVICES += sagem_fast-2404\n\ndefine Device/sagem_fast-2504n\n  $(Device/bcm63xx)\n  DEVICE_VENDOR := Sagemcom\n  DEVICE_MODEL := F@st 2504N\n  CFE_BOARD_ID := F@ST2504n\n  CHIP_ID := 6362\n  DEVICE_PACKAGES := $(B43_PACKAGES)\nendef\nTARGET_DEVICES += sagem_fast-2504n\n\ndefine Device/sagem_fast-2604\n  $(Device/bcm63xx-legacy)\n  DEVICE_VENDOR := Sagemcom\n  DEVICE_MODEL := F@st 2604\n  CFE_BOARD_ID := F@ST2604\n  CHIP_ID := 6348\n  DEVICE_PACKAGES := $(B43_PACKAGES)\n  DEFAULT := n\nendef\nTARGET_DEVICES += sagem_fast-2604\n\ndefine Device/sagem_fast-2704n\n  $(Device/bcm63xx)\n  DEVICE_VENDOR := Sagemcom\n  DEVICE_MODEL := F@st 2704N\n  CFE_BOARD_ID := F@ST2704N\n  CHIP_ID := 6318\n  FLASH_MB := 8\n  DEVICE_PACKAGES := $(B43_PACKAGES) $(USB2_PACKAGES)\nendef\nTARGET_DEVICES += sagem_fast-2704n\n\ndefine Device/sagem_fast-2704-v2\n  $(Device/bcm63xx)\n  DEVICE_VENDOR := Sagemcom\n  DEVICE_MODEL := F@st 2704\n  DEVICE_VARIANT := V2\n  CFE_BOARD_ID := F@ST2704V2\n  CHIP_ID := 6328\n  FLASH_MB := 8\n  DEVICE_PACKAGES := $(B43_PACKAGES) $(USB2_PACKAGES)\nendef\nTARGET_DEVICES += sagem_fast-2704-v2\n\n### Sercomm ###\ndefine Device/sercomm_ad1018-nor\n  $(Device/bcm63xx)\n  DEVICE_VENDOR := Sercomm\n  DEVICE_MODEL := AD1018\n  DEVICE_VARIANT := SPI flash mod\n  CFE_BOARD_ID := 96328avngr\n  CHIP_ID := 6328\n  DEVICE_PACKAGES := $(B43_PACKAGES) $(USB2_PACKAGES)\nendef\nTARGET_DEVICES += sercomm_ad1018-nor\n\n### SFR ###\ndefine Device/sfr_neufbox-4-sercomm-r0\n  $(Device/bcm63xx-legacy)\n  DEVICE_VENDOR := SFR\n  DEVICE_MODEL := Neufbox 4\n  DEVICE_VARIANT := Sercomm\n  CFE_BOARD_ID := 96358VW\n  CHIP_ID := 6358\n  CFE_EXTRAS += --rsa-signature \"$(VERSION_DIST)-$(firstword $(subst -,$(space),$(REVISION)))\"\n  DEVICE_PACKAGES := $(B43_PACKAGES) $(USB2_PACKAGES)\nendef\nTARGET_DEVICES += sfr_neufbox-4-sercomm-r0\n\ndefine Device/sfr_neufbox-4-foxconn-r1\n  $(Device/bcm63xx-legacy)\n  DEVICE_VENDOR := SFR\n  DEVICE_MODEL := Neufbox 4\n  DEVICE_VARIANT := Foxconn\n  CFE_BOARD_ID := 96358VW\n  CHIP_ID := 6358\n  CFE_EXTRAS += --rsa-signature \"$(VERSION_DIST)-$(firstword $(subst -,$(space),$(REVISION)))\"\n  DEVICE_PACKAGES := $(B43_PACKAGES) $(USB2_PACKAGES)\nendef\nTARGET_DEVICES += sfr_neufbox-4-foxconn-r1\n\ndefine Device/sfr_neufbox-6-sercomm-r0\n  $(Device/bcm63xx)\n  DEVICE_VENDOR := SFR\n  DEVICE_MODEL := Neufbox 6\n  CFE_BOARD_ID := NB6-SER-r0\n  CHIP_ID := 6362\n  CFE_EXTRAS += --rsa-signature \"$(VERSION_DIST)-$(firstword $(subst -,$(space),$(REVISION)))\"\n  SOC := bcm6361\n  DEVICE_PACKAGES := $(USB2_PACKAGES)\nendef\nTARGET_DEVICES += sfr_neufbox-6-sercomm-r0\n\ndefine Device/sky_sr102\n  $(Device/bcm63xx)\n  DEVICE_VENDOR := SKY\n  DEVICE_MODEL := SR102\n  CFE_BOARD_ID := BSKYB_63168\n  CHIP_ID := 63268\n  CFE_EXTRAS += --rsa-signature \"$(VERSION_DIST)-$(firstword $(subst -,$(space),$(REVISION)))\"\n  SOC := bcm63168\n  DEVICE_PACKAGES := $(USB2_PACKAGES)\nendef\nTARGET_DEVICES += sky_sr102\n\n### T-Com ###\ndefine Device/t-com_speedport-w-303v\n  $(Device/bcm63xx-legacy)\n  DEVICE_VENDOR := T-Com\n  DEVICE_MODEL := Speedport W 303V\n  IMAGES := factory.bin sysupgrade.bin\n  IMAGE/factory.bin := cfe-spw303v-bin --pad 4 | spw303v-bin | xor-image\n  IMAGE/sysupgrade.bin := cfe-spw303v-bin | spw303v-bin\n  CFE_BOARD_ID := 96358-502V\n  CHIP_ID := 6358\n  DEVICE_PACKAGES := $(B43_PACKAGES)\nendef\nTARGET_DEVICES += t-com_speedport-w-303v\n\ndefine Device/t-com_speedport-w-500v\n  $(Device/bcm63xx-legacy)\n  DEVICE_VENDOR := T-Com\n  DEVICE_MODEL := Speedport W 500V\n  CFE_BOARD_ID := 96348GW\n  CHIP_ID := 6348\n  DEVICE_PACKAGES := $(B43_PACKAGES)\n  DEFAULT := n\nendef\nTARGET_DEVICES += t-com_speedport-w-500v\n\n### Technicolor ###\ndefine Device/technicolor_tg582n\n  $(Device/bcm63xx)\n  DEVICE_VENDOR := Technicolor\n  DEVICE_MODEL := TG582n\n  IMAGES += sysupgrade.bin\n  CFE_BOARD_ID := DANT-1\n  CHIP_ID := 6328\n  FLASH_MB := 16\n  DEVICE_PACKAGES := $(USB2_PACKAGES) $(B43_PACKAGES)\nendef\nTARGET_DEVICES += technicolor_tg582n\n\ndefine Device/technicolor_tg582n-telecom-italia\n  $(Device/bcm63xx)\n  DEVICE_VENDOR := Technicolor\n  DEVICE_MODEL := TG582n\n  DEVICE_VARIANT := Telecom Italia\n  IMAGES += sysupgrade.bin\n  CFE_BOARD_ID := DANT-V\n  CHIP_ID := 6328\n  FLASH_MB := 16\n  DEVICE_PACKAGES := $(USB2_PACKAGES) $(B43_PACKAGES)\nendef\nTARGET_DEVICES += technicolor_tg582n-telecom-italia\n\n### Tecom ###\ndefine Device/tecom_gw6000\n  $(Device/bcm63xx-legacy)\n  DEVICE_VENDOR := Tecom\n  DEVICE_MODEL := GW6000\n  CFE_BOARD_ID := 96348GW\n  CHIP_ID := 6348\n  DEVICE_PACKAGES := $(BRCMWL_PACKAGES) $(USB1_PACKAGES)\n  DEFAULT := n\nendef\nTARGET_DEVICES += tecom_gw6000\n\ndefine Device/tecom_gw6200\n  $(Device/bcm63xx-legacy)\n  DEVICE_VENDOR := Tecom\n  DEVICE_MODEL := GW6200\n  CFE_BOARD_ID := 96348GW\n  CHIP_ID := 6348\n  CFE_EXTRAS += --rsa-signature \"$(shell printf '\\x99')\"\n  DEVICE_PACKAGES := $(BRCMWL_PACKAGES) $(USB1_PACKAGES)\n  DEFAULT := n\nendef\nTARGET_DEVICES += tecom_gw6200\n\n### Telsey ###\ndefine Device/telsey_cpva502plus\n  $(Device/bcm63xx-legacy)\n  DEVICE_VENDOR := Telsey\n  DEVICE_MODEL := CPVA502+\n  CFE_BOARD_ID := CPVA502+\n  CHIP_ID := 6348\n  CFE_EXTRAS += --signature \"Telsey Tlc\" --signature2 \"99.99.999\"\n  DEVICE_PACKAGES := $(B43_PACKAGES)\n  DEFAULT := n\nendef\nTARGET_DEVICES += telsey_cpva502plus\n\ndefine Device/telsey_cpva642\n  $(Device/bcm63xx-legacy)\n  DEVICE_VENDOR := Telsey\n  DEVICE_MODEL := CPVA642-type (CPA-ZNTE60T)\n  CFE_BOARD_ID := CPVA642\n  CHIP_ID := 6358\n  CFE_EXTRAS += --signature \"Telsey Tlc\" --signature2 \"99.99.999\" --second-image-flag \"0\"\n  FLASH_MB := 8\n  DEVICE_PACKAGES := $(RT63_PACKAGES) $(USB2_PACKAGES)\nendef\nTARGET_DEVICES += telsey_cpva642\n\ndefine Device/telsey_magic\n  $(Device/bcm63xx-legacy)\n  DEVICE_VENDOR := Alice\n  DEVICE_MODEL := W-Gate\n  DEVICE_ALT0_VENDOR := Telsey\n  DEVICE_ALT0_MODEL := MAGIC\n  IMAGES :=\n  CFE_BOARD_ID := MAGIC\n  CHIP_ID := 6348\n  DEVICE_PACKAGES := $(RT63_PACKAGES)\n  DEFAULT := n\nendef\nTARGET_DEVICES += telsey_magic\n\n### TP-Link ###\ndefine Device/tp-link_td-w8900gb\n  $(Device/bcm63xx-legacy)\n  DEVICE_VENDOR := TP-Link\n  DEVICE_MODEL := TD-W8900GB\n  CFE_BOARD_ID := 96348GW-11\n  CHIP_ID := 6348\n  CFE_EXTRAS += --rsa-signature \"$(shell printf 'PRID\\x89\\x10\\x00\\x02')\"\n  IMAGE_OFFSET := 0x20000\n  DEVICE_PACKAGES := $(B43_PACKAGES)\n  DEFAULT := n\nendef\nTARGET_DEVICES += tp-link_td-w8900gb\n\n### USRobotics ###\ndefine Device/usrobotics_usr9108\n  $(Device/bcm63xx-legacy)\n  DEVICE_VENDOR := USRobotics\n  DEVICE_MODEL := USR9108\n  CFE_BOARD_ID := 96348GW-A\n  CHIP_ID := 6348\n  DEVICE_PACKAGES := $(B43_PACKAGES) $(USB1_PACKAGES)\n  DEFAULT := n\nendef\nTARGET_DEVICES += usrobotics_usr9108\n\n### ZyXEL ###\ndefine Device/zyxel_p870hw-51a-v2\n  $(Device/bcm63xx)\n  DEVICE_VENDOR := ZyXEL\n  DEVICE_MODEL := P870HW-51a\n  DEVICE_VARIANT := v2\n  IMAGES := factory.bin\n  IMAGE/factory.bin := cfe-bin | zyxel-bin\n  CFE_BOARD_ID := 96368VVW\n  CHIP_ID := 6368\n  CFE_EXTRAS += --rsa-signature \"ZyXEL\" --signature \"ZyXEL_0001\"\n  DEVICE_PACKAGES := $(B43_PACKAGES)\n  DEFAULT := n\nendef\nTARGET_DEVICES += zyxel_p870hw-51a-v2\n"
  },
  {
    "path": "target/linux/bcm63xx/image/bcm63xx_nand.mk",
    "content": "#\n# BCM63XX NAND Profiles\n#\n\nDEVICE_VARS += CFE_PART_FLAGS CFE_PART_ID\nDEVICE_VARS += CFE_RAM_FILE\nDEVICE_VARS += CFE_RAM_JFFS2_NAME CFE_RAM_JFFS2_PAD\nDEVICE_VARS += CFE_WFI_CHIP_ID CFE_WFI_FLASH_TYPE\nDEVICE_VARS += CFE_WFI_FLAGS CFE_WFI_VERSION\nDEVICE_VARS += SERCOMM_PID SERCOMM_VERSION\n\n# CFE expects a single JFFS2 partition with cferam and kernel. However,\n# it's possible to fool CFE into properly loading both cferam and kernel\n# from two different JFFS2 partitions by adding dummy files (see\n# cfe-jffs2-cferam and cfe-jffs2-kernel).\n# Separate JFFS2 partitions allow upgrading openwrt without reflashing cferam\n# JFFS2 partition, which is much safer in case anything goes wrong.\ndefine Device/bcm63xx-nand\n  FILESYSTEMS := squashfs ubifs\n  KERNEL := kernel-bin | append-dtb | relocate-kernel | lzma | cfe-jffs2-kernel\n  KERNEL_INITRAMFS := kernel-bin | append-dtb | lzma | loader-lzma elf\n  IMAGES := cfe.bin sysupgrade.bin\n  IMAGE/cfe.bin := append-kernel | pad-to $$$$(KERNEL_SIZE) | cfe-jffs2-cferam | append-ubi | cfe-wfi-tag\n  IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata\n  KERNEL_SIZE := 5120k\n  CFE_PART_FLAGS :=\n  CFE_PART_ID :=\n  CFE_RAM_FILE :=\n  CFE_RAM_JFFS2_NAME :=\n  CFE_RAM_JFFS2_PAD :=\n  CFE_WFI_VERSION :=\n  CFE_WFI_CHIP_ID = 0x$$(CHIP_ID)\n  CFE_WFI_FLASH_TYPE :=\n  CFE_WFI_FLAGS :=\n  UBINIZE_OPTS := -E 5\n  DEVICE_PACKAGES += nand-utils\nendef\n\ndefine Device/sercomm-nand\n  $(Device/bcm63xx-nand)\n  IMAGES := factory.img sysupgrade.bin\n  IMAGE/factory.img := append-kernel | pad-to $$$$(KERNEL_SIZE) | append-ubi | cfe-sercomm-part | gzip | cfe-sercomm-load | cfe-sercomm-crypto\n  SERCOM_PID :=\n  SERCOMM_VERSION :=\nendef\n\n### Comtrend ###\ndefine Device/comtrend_vg-8050\n  $(Device/bcm63xx-nand)\n  DEVICE_VENDOR := Comtrend\n  DEVICE_MODEL := VG-8050\n  CHIP_ID := 63268\n  SOC := bcm63169\n  CFE_RAM_FILE := comtrend,vg-8050/cferam.000\n  CFE_RAM_JFFS2_NAME := cferam.000\n  BLOCKSIZE := 128k\n  PAGESIZE := 2048\n  SUBPAGESIZE := 512\n  VID_HDR_OFFSET := 2048\n  DEVICE_PACKAGES += $(USB2_PACKAGES)\n  CFE_WFI_VERSION := 0x5732\n  CFE_WFI_FLASH_TYPE := 3\nendef\nTARGET_DEVICES += comtrend_vg-8050\n\ndefine Device/comtrend_vr-3032u\n  $(Device/bcm63xx-nand)\n  DEVICE_VENDOR := Comtrend\n  DEVICE_MODEL := VR-3032u\n  CHIP_ID := 63268\n  SOC := bcm63168\n  CFE_RAM_FILE := comtrend,vr-3032u/cferam.000\n  CFE_RAM_JFFS2_NAME := cferam.000\n  BLOCKSIZE := 128k\n  PAGESIZE := 2048\n  SUBPAGESIZE := 512\n  VID_HDR_OFFSET := 2048\n  DEVICE_PACKAGES += $(USB2_PACKAGES)\n  CFE_WFI_VERSION := 0x5732\n  CFE_WFI_FLASH_TYPE := 3\nendef\nTARGET_DEVICES += comtrend_vr-3032u\n\n### Huawei ###\ndefine Device/huawei_hg253s-v2\n  $(Device/bcm63xx-nand)\n  IMAGES := flash.bin sysupgrade.bin\n  IMAGE/flash.bin := append-kernel | pad-to $$$$(KERNEL_SIZE) | cfe-jffs2-cferam | append-ubi\n  DEVICE_VENDOR := Huawei\n  DEVICE_MODEL := HG253s\n  DEVICE_VARIANT := v2\n  CHIP_ID := 6362\n  CFE_PART_FLAGS := 1\n  CFE_PART_ID := 0x0001EFEE\n  CFE_RAM_FILE := huawei,hg253s-v2/cferam.000\n  CFE_RAM_JFFS2_NAME := cferam.000\n  BLOCKSIZE := 128k\n  PAGESIZE := 2048\n  SUBPAGESIZE := 512\n  VID_HDR_OFFSET := 2048\n  DEVICE_PACKAGES += $(USB2_PACKAGES)\n  CFE_WFI_FLASH_TYPE := 3\nendef\nTARGET_DEVICES += huawei_hg253s-v2\n\n### Netgear ###\ndefine Device/netgear_dgnd3700-v2\n  $(Device/bcm63xx-nand)\n  DEVICE_VENDOR := NETGEAR\n  DEVICE_MODEL := DGND3700\n  DEVICE_VARIANT := v2\n  CHIP_ID := 6362\n  CFE_RAM_FILE := netgear,dgnd3700-v2/cferam\n  CFE_RAM_JFFS2_NAME := cferam\n  CFE_RAM_JFFS2_PAD := 496k\n  BLOCKSIZE := 16k\n  PAGESIZE := 512\n  DEVICE_PACKAGES += $(B43_PACKAGES) $(USB2_PACKAGES)\n  CFE_WFI_VERSION := 0x5731\n  CFE_WFI_FLASH_TYPE := 2\nendef\nTARGET_DEVICES += netgear_dgnd3700-v2\n\n### Sercomm ###\ndefine Device/sercomm_ad1018\n  $(Device/sercomm-nand)\n  DEVICE_VENDOR := Sercomm\n  DEVICE_MODEL := AD1018\n  CHIP_ID := 6328\n  CFE_RAM_FILE := sercomm,ad1018/cferam\n  CFE_RAM_JFFS2_NAME := cferam\n  BLOCKSIZE := 128k\n  PAGESIZE := 2048\n  SUBPAGESIZE := 512\n  VID_HDR_OFFSET := 2048\n  DEVICE_PACKAGES += $(B43_PACKAGES) $(USB2_PACKAGES)\n  CFE_WFI_FLASH_TYPE := 3\n  CFE_WFI_VERSION := 0x5731\n  SERCOMM_PID := \\\n    30 30 30 30 30 30 30 31 34 31 35 31 35 33 30 30 \\\n    30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 \\\n    30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 \\\n    30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 \\\n    30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 \\\n    30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 \\\n    30 30 30 30 33 30 31 33 30 30 30 30 30 30 30 30 \\\n    0D 0A 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n  SERCOMM_VERSION := 1001\nendef\nTARGET_DEVICES += sercomm_ad1018\n\ndefine Device/sercomm_h500-s-lowi\n  $(Device/sercomm-nand)\n  DEVICE_VENDOR := Sercomm\n  DEVICE_MODEL := H500-s\n  DEVICE_VARIANT := lowi\n  DEVICE_LOADADDR := $(KERNEL_LOADADDR)\n  KERNEL := kernel-bin | append-dtb | lzma | cfe-jffs2-kernel\n  CHIP_ID := 63268\n  SOC := bcm63167\n  BLOCKSIZE := 128k\n  PAGESIZE := 2048\n  SUBPAGESIZE := 512\n  VID_HDR_OFFSET := 2048\n  DEVICE_PACKAGES += $(USB2_PACKAGES)\n  SERCOMM_PID := \\\n    30 30 30 30 30 30 30 31 34 33 34 62 33 31 30 30 \\\n    30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 \\\n    30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 \\\n    30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 \\\n    30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 \\\n    30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 \\\n    30 30 30 30 33 33 30 35 30 30 30 30 30 30 30 30 \\\n    0D 0A 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n  SERCOMM_VERSION := 1001\nendef\nTARGET_DEVICES += sercomm_h500-s-lowi\n\ndefine Device/sercomm_h500-s-vfes\n  $(Device/sercomm-nand)\n  DEVICE_VENDOR := Sercomm\n  DEVICE_MODEL := H500-s\n  DEVICE_VARIANT := vfes\n  DEVICE_LOADADDR := $(KERNEL_LOADADDR)\n  KERNEL := kernel-bin | append-dtb | lzma | cfe-jffs2-kernel\n  CHIP_ID := 63268\n  SOC := bcm63167\n  BLOCKSIZE := 128k\n  PAGESIZE := 2048\n  SUBPAGESIZE := 512\n  VID_HDR_OFFSET := 2048\n  DEVICE_PACKAGES += $(USB2_PACKAGES)\n  SERCOMM_PID := \\\n    30 30 30 30 30 30 30 31 34 32 35 38 34 62 30 30 \\\n    30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 \\\n    30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 \\\n    30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 \\\n    30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 \\\n    30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 \\\n    30 30 30 30 33 34 31 37 30 30 30 30 30 30 30 30 \\\n    0D 0A 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n  SERCOMM_VERSION := 1001\nendef\nTARGET_DEVICES += sercomm_h500-s-vfes\n"
  },
  {
    "path": "target/linux/bcm63xx/image/lzma-loader/Makefile",
    "content": "#\n# Copyright (C) 2020 Álvaro Fernández Rojas <noltari@gmail.com>\n# Copyright (C) 2014 Jonas Gorski <jogo@openwrt.org>\n# Copyright (C) 2011 OpenWrt.org\n# Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nLZMA_TEXT_START\t:= 0x80a00000\nLOADER\t\t:= loader.bin\nLOADER_NAME\t:= $(basename $(notdir $(LOADER)))\nLOADER_DATA \t:=\nTARGET_DIR\t:=\n\nUART_BASE_3329 := 0xb0000100\nUART_BASE_3368 := 0xfff8c100\nUART_BASE_3380 := 0xb4e00200\nUART_BASE_3383 := 0xb4e00500\nUART_BASE_3384 := 0xb4e00500\nUART_BASE_6318 := 0xb0000100\nUART_BASE_6328 := 0xb0000100\nUART_BASE_6338 := 0xfffe0300\nUART_BASE_6345 := 0xfffe0300\nUART_BASE_6348 := 0xfffe0300\nUART_BASE_6358 := 0xfffe0100\nUART_BASE_6362 := 0xb0000100\nUART_BASE_6368 := 0xb0000100\nUART_BASE_63268 := 0xb0000180\nUART_BASE_6816 := 0xb0000100\nUART_BASE_6818 := 0xb0000100\nUART_BASE_6828 := 0xb0000180\nUART_BASE := $(if $(UART_BASE_$(CHIP_ID)),$(UART_BASE_$(CHIP_ID)),0)\n\nifeq ($(TARGET_DIR),)\nTARGET_DIR\t:= $(KDIR)\nendif\n\nLOADER_BIN\t:= $(TARGET_DIR)/$(LOADER_NAME).bin\nLOADER_ELF\t:= $(TARGET_DIR)/$(LOADER_NAME).elf\n\nPKG_NAME := lzma-loader\nPKG_BUILD_DIR := $(KDIR)/$(PKG_NAME)\n\n.PHONY : loader-compile loader.bin loader.elf\n\n$(PKG_BUILD_DIR)/.prepared:\n\tmkdir $(PKG_BUILD_DIR)\n\t$(CP) ./src/* $(PKG_BUILD_DIR)/\n\ttouch $@\n\nloader-compile: $(PKG_BUILD_DIR)/.prepared\n\t$(MAKE) -C $(PKG_BUILD_DIR) CROSS_COMPILE=\"$(TARGET_CROSS)\" \\\n\t\tLZMA_TEXT_START=$(LZMA_TEXT_START) \\\n\t\tLOADER_DATA=$(LOADER_DATA) \\\n\t\tUART_BASE=$(UART_BASE) \\\n\t\tclean all\n\nloader.elf: $(PKG_BUILD_DIR)/loader.elf\n\t$(CP) $< $(LOADER_ELF)\n\nloader.bin: $(PKG_BUILD_DIR)/loader.bin\n\t$(CP) $< $(LOADER_BIN)\n\ndownload:\nprepare: $(PKG_BUILD_DIR)/.prepared\ncompile: loader-compile\n\ninstall:\n\nclean:\n\trm -rf $(PKG_BUILD_DIR)\n"
  },
  {
    "path": "target/linux/bcm63xx/image/lzma-loader/src/LzmaDecode.c",
    "content": "/*\n  LzmaDecode.c\n  LZMA Decoder (optimized for Speed version)\n  \n  LZMA SDK 4.40 Copyright (c) 1999-2006 Igor Pavlov (2006-05-01)\n  http://www.7-zip.org/\n\n  LZMA SDK is licensed under two licenses:\n  1) GNU Lesser General Public License (GNU LGPL)\n  2) Common Public License (CPL)\n  It means that you can select one of these two licenses and \n  follow rules of that license.\n\n  SPECIAL EXCEPTION:\n  Igor Pavlov, as the author of this Code, expressly permits you to \n  statically or dynamically link your Code (or bind by name) to the \n  interfaces of this file without subjecting your linked Code to the \n  terms of the CPL or GNU LGPL. Any modifications or additions \n  to this file, however, are subject to the LGPL or CPL terms.\n*/\n\n#include \"LzmaDecode.h\"\n\n#define kNumTopBits 24\n#define kTopValue ((UInt32)1 << kNumTopBits)\n\n#define kNumBitModelTotalBits 11\n#define kBitModelTotal (1 << kNumBitModelTotalBits)\n#define kNumMoveBits 5\n\n#define RC_READ_BYTE (*Buffer++)\n\n#define RC_INIT2 Code = 0; Range = 0xFFFFFFFF; \\\n  { int i; for(i = 0; i < 5; i++) { RC_TEST; Code = (Code << 8) | RC_READ_BYTE; }}\n\n#ifdef _LZMA_IN_CB\n\n#define RC_TEST { if (Buffer == BufferLim) \\\n  { SizeT size; int result = InCallback->Read(InCallback, &Buffer, &size); if (result != LZMA_RESULT_OK) return result; \\\n  BufferLim = Buffer + size; if (size == 0) return LZMA_RESULT_DATA_ERROR; }}\n\n#define RC_INIT Buffer = BufferLim = 0; RC_INIT2\n\n#else\n\n#define RC_TEST { if (Buffer == BufferLim) return LZMA_RESULT_DATA_ERROR; }\n\n#define RC_INIT(buffer, bufferSize) Buffer = buffer; BufferLim = buffer + bufferSize; RC_INIT2\n \n#endif\n\n#define RC_NORMALIZE if (Range < kTopValue) { RC_TEST; Range <<= 8; Code = (Code << 8) | RC_READ_BYTE; }\n\n#define IfBit0(p) RC_NORMALIZE; bound = (Range >> kNumBitModelTotalBits) * *(p); if (Code < bound)\n#define UpdateBit0(p) Range = bound; *(p) += (kBitModelTotal - *(p)) >> kNumMoveBits;\n#define UpdateBit1(p) Range -= bound; Code -= bound; *(p) -= (*(p)) >> kNumMoveBits;\n\n#define RC_GET_BIT2(p, mi, A0, A1) IfBit0(p) \\\n  { UpdateBit0(p); mi <<= 1; A0; } else \\\n  { UpdateBit1(p); mi = (mi + mi) + 1; A1; } \n  \n#define RC_GET_BIT(p, mi) RC_GET_BIT2(p, mi, ; , ;)               \n\n#define RangeDecoderBitTreeDecode(probs, numLevels, res) \\\n  { int i = numLevels; res = 1; \\\n  do { CProb *p = probs + res; RC_GET_BIT(p, res) } while(--i != 0); \\\n  res -= (1 << numLevels); }\n\n\n#define kNumPosBitsMax 4\n#define kNumPosStatesMax (1 << kNumPosBitsMax)\n\n#define kLenNumLowBits 3\n#define kLenNumLowSymbols (1 << kLenNumLowBits)\n#define kLenNumMidBits 3\n#define kLenNumMidSymbols (1 << kLenNumMidBits)\n#define kLenNumHighBits 8\n#define kLenNumHighSymbols (1 << kLenNumHighBits)\n\n#define LenChoice 0\n#define LenChoice2 (LenChoice + 1)\n#define LenLow (LenChoice2 + 1)\n#define LenMid (LenLow + (kNumPosStatesMax << kLenNumLowBits))\n#define LenHigh (LenMid + (kNumPosStatesMax << kLenNumMidBits))\n#define kNumLenProbs (LenHigh + kLenNumHighSymbols) \n\n\n#define kNumStates 12\n#define kNumLitStates 7\n\n#define kStartPosModelIndex 4\n#define kEndPosModelIndex 14\n#define kNumFullDistances (1 << (kEndPosModelIndex >> 1))\n\n#define kNumPosSlotBits 6\n#define kNumLenToPosStates 4\n\n#define kNumAlignBits 4\n#define kAlignTableSize (1 << kNumAlignBits)\n\n#define kMatchMinLen 2\n\n#define IsMatch 0\n#define IsRep (IsMatch + (kNumStates << kNumPosBitsMax))\n#define IsRepG0 (IsRep + kNumStates)\n#define IsRepG1 (IsRepG0 + kNumStates)\n#define IsRepG2 (IsRepG1 + kNumStates)\n#define IsRep0Long (IsRepG2 + kNumStates)\n#define PosSlot (IsRep0Long + (kNumStates << kNumPosBitsMax))\n#define SpecPos (PosSlot + (kNumLenToPosStates << kNumPosSlotBits))\n#define Align (SpecPos + kNumFullDistances - kEndPosModelIndex)\n#define LenCoder (Align + kAlignTableSize)\n#define RepLenCoder (LenCoder + kNumLenProbs)\n#define Literal (RepLenCoder + kNumLenProbs)\n\n#if Literal != LZMA_BASE_SIZE\nStopCompilingDueBUG\n#endif\n\nint LzmaDecodeProperties(CLzmaProperties *propsRes, const unsigned char *propsData, int size)\n{\n  unsigned char prop0;\n  if (size < LZMA_PROPERTIES_SIZE)\n    return LZMA_RESULT_DATA_ERROR;\n  prop0 = propsData[0];\n  if (prop0 >= (9 * 5 * 5))\n    return LZMA_RESULT_DATA_ERROR;\n  {\n    for (propsRes->pb = 0; prop0 >= (9 * 5); propsRes->pb++, prop0 -= (9 * 5));\n    for (propsRes->lp = 0; prop0 >= 9; propsRes->lp++, prop0 -= 9);\n    propsRes->lc = prop0;\n    /*\n    unsigned char remainder = (unsigned char)(prop0 / 9);\n    propsRes->lc = prop0 % 9;\n    propsRes->pb = remainder / 5;\n    propsRes->lp = remainder % 5;\n    */\n  }\n\n  #ifdef _LZMA_OUT_READ\n  {\n    int i;\n    propsRes->DictionarySize = 0;\n    for (i = 0; i < 4; i++)\n      propsRes->DictionarySize += (UInt32)(propsData[1 + i]) << (i * 8);\n    if (propsRes->DictionarySize == 0)\n      propsRes->DictionarySize = 1;\n  }\n  #endif\n  return LZMA_RESULT_OK;\n}\n\n#define kLzmaStreamWasFinishedId (-1)\n\nint LzmaDecode(CLzmaDecoderState *vs,\n    #ifdef _LZMA_IN_CB\n    ILzmaInCallback *InCallback,\n    #else\n    const unsigned char *inStream, SizeT inSize, SizeT *inSizeProcessed,\n    #endif\n    unsigned char *outStream, SizeT outSize, SizeT *outSizeProcessed)\n{\n  CProb *p = vs->Probs;\n  SizeT nowPos = 0;\n  Byte previousByte = 0;\n  UInt32 posStateMask = (1 << (vs->Properties.pb)) - 1;\n  UInt32 literalPosMask = (1 << (vs->Properties.lp)) - 1;\n  int lc = vs->Properties.lc;\n\n  #ifdef _LZMA_OUT_READ\n  \n  UInt32 Range = vs->Range;\n  UInt32 Code = vs->Code;\n  #ifdef _LZMA_IN_CB\n  const Byte *Buffer = vs->Buffer;\n  const Byte *BufferLim = vs->BufferLim;\n  #else\n  const Byte *Buffer = inStream;\n  const Byte *BufferLim = inStream + inSize;\n  #endif\n  int state = vs->State;\n  UInt32 rep0 = vs->Reps[0], rep1 = vs->Reps[1], rep2 = vs->Reps[2], rep3 = vs->Reps[3];\n  int len = vs->RemainLen;\n  UInt32 globalPos = vs->GlobalPos;\n  UInt32 distanceLimit = vs->DistanceLimit;\n\n  Byte *dictionary = vs->Dictionary;\n  UInt32 dictionarySize = vs->Properties.DictionarySize;\n  UInt32 dictionaryPos = vs->DictionaryPos;\n\n  Byte tempDictionary[4];\n\n  #ifndef _LZMA_IN_CB\n  *inSizeProcessed = 0;\n  #endif\n  *outSizeProcessed = 0;\n  if (len == kLzmaStreamWasFinishedId)\n    return LZMA_RESULT_OK;\n\n  if (dictionarySize == 0)\n  {\n    dictionary = tempDictionary;\n    dictionarySize = 1;\n    tempDictionary[0] = vs->TempDictionary[0];\n  }\n\n  if (len == kLzmaNeedInitId)\n  {\n    {\n      UInt32 numProbs = Literal + ((UInt32)LZMA_LIT_SIZE << (lc + vs->Properties.lp));\n      UInt32 i;\n      for (i = 0; i < numProbs; i++)\n        p[i] = kBitModelTotal >> 1; \n      rep0 = rep1 = rep2 = rep3 = 1;\n      state = 0;\n      globalPos = 0;\n      distanceLimit = 0;\n      dictionaryPos = 0;\n      dictionary[dictionarySize - 1] = 0;\n      #ifdef _LZMA_IN_CB\n      RC_INIT;\n      #else\n      RC_INIT(inStream, inSize);\n      #endif\n    }\n    len = 0;\n  }\n  while(len != 0 && nowPos < outSize)\n  {\n    UInt32 pos = dictionaryPos - rep0;\n    if (pos >= dictionarySize)\n      pos += dictionarySize;\n    outStream[nowPos++] = dictionary[dictionaryPos] = dictionary[pos];\n    if (++dictionaryPos == dictionarySize)\n      dictionaryPos = 0;\n    len--;\n  }\n  if (dictionaryPos == 0)\n    previousByte = dictionary[dictionarySize - 1];\n  else\n    previousByte = dictionary[dictionaryPos - 1];\n\n  #else /* if !_LZMA_OUT_READ */\n\n  int state = 0;\n  UInt32 rep0 = 1, rep1 = 1, rep2 = 1, rep3 = 1;\n  int len = 0;\n  const Byte *Buffer;\n  const Byte *BufferLim;\n  UInt32 Range;\n  UInt32 Code;\n\n  #ifndef _LZMA_IN_CB\n  *inSizeProcessed = 0;\n  #endif\n  *outSizeProcessed = 0;\n\n  {\n    UInt32 i;\n    UInt32 numProbs = Literal + ((UInt32)LZMA_LIT_SIZE << (lc + vs->Properties.lp));\n    for (i = 0; i < numProbs; i++)\n      p[i] = kBitModelTotal >> 1;\n  }\n  \n  #ifdef _LZMA_IN_CB\n  RC_INIT;\n  #else\n  RC_INIT(inStream, inSize);\n  #endif\n\n  #endif /* _LZMA_OUT_READ */\n\n  while(nowPos < outSize)\n  {\n    CProb *prob;\n    UInt32 bound;\n    int posState = (int)(\n        (nowPos \n        #ifdef _LZMA_OUT_READ\n        + globalPos\n        #endif\n        )\n        & posStateMask);\n\n    prob = p + IsMatch + (state << kNumPosBitsMax) + posState;\n    IfBit0(prob)\n    {\n      int symbol = 1;\n      UpdateBit0(prob)\n      prob = p + Literal + (LZMA_LIT_SIZE * \n        (((\n        (nowPos \n        #ifdef _LZMA_OUT_READ\n        + globalPos\n        #endif\n        )\n        & literalPosMask) << lc) + (previousByte >> (8 - lc))));\n\n      if (state >= kNumLitStates)\n      {\n        int matchByte;\n        #ifdef _LZMA_OUT_READ\n        UInt32 pos = dictionaryPos - rep0;\n        if (pos >= dictionarySize)\n          pos += dictionarySize;\n        matchByte = dictionary[pos];\n        #else\n        matchByte = outStream[nowPos - rep0];\n        #endif\n        do\n        {\n          int bit;\n          CProb *probLit;\n          matchByte <<= 1;\n          bit = (matchByte & 0x100);\n          probLit = prob + 0x100 + bit + symbol;\n          RC_GET_BIT2(probLit, symbol, if (bit != 0) break, if (bit == 0) break)\n        }\n        while (symbol < 0x100);\n      }\n      while (symbol < 0x100)\n      {\n        CProb *probLit = prob + symbol;\n        RC_GET_BIT(probLit, symbol)\n      }\n      previousByte = (Byte)symbol;\n\n      outStream[nowPos++] = previousByte;\n      #ifdef _LZMA_OUT_READ\n      if (distanceLimit < dictionarySize)\n        distanceLimit++;\n\n      dictionary[dictionaryPos] = previousByte;\n      if (++dictionaryPos == dictionarySize)\n        dictionaryPos = 0;\n      #endif\n      if (state < 4) state = 0;\n      else if (state < 10) state -= 3;\n      else state -= 6;\n    }\n    else             \n    {\n      UpdateBit1(prob);\n      prob = p + IsRep + state;\n      IfBit0(prob)\n      {\n        UpdateBit0(prob);\n        rep3 = rep2;\n        rep2 = rep1;\n        rep1 = rep0;\n        state = state < kNumLitStates ? 0 : 3;\n        prob = p + LenCoder;\n      }\n      else\n      {\n        UpdateBit1(prob);\n        prob = p + IsRepG0 + state;\n        IfBit0(prob)\n        {\n          UpdateBit0(prob);\n          prob = p + IsRep0Long + (state << kNumPosBitsMax) + posState;\n          IfBit0(prob)\n          {\n            #ifdef _LZMA_OUT_READ\n            UInt32 pos;\n            #endif\n            UpdateBit0(prob);\n            \n            #ifdef _LZMA_OUT_READ\n            if (distanceLimit == 0)\n            #else\n            if (nowPos == 0)\n            #endif\n              return LZMA_RESULT_DATA_ERROR;\n            \n            state = state < kNumLitStates ? 9 : 11;\n            #ifdef _LZMA_OUT_READ\n            pos = dictionaryPos - rep0;\n            if (pos >= dictionarySize)\n              pos += dictionarySize;\n            previousByte = dictionary[pos];\n            dictionary[dictionaryPos] = previousByte;\n            if (++dictionaryPos == dictionarySize)\n              dictionaryPos = 0;\n            #else\n            previousByte = outStream[nowPos - rep0];\n            #endif\n            outStream[nowPos++] = previousByte;\n            #ifdef _LZMA_OUT_READ\n            if (distanceLimit < dictionarySize)\n              distanceLimit++;\n            #endif\n\n            continue;\n          }\n          else\n          {\n            UpdateBit1(prob);\n          }\n        }\n        else\n        {\n          UInt32 distance;\n          UpdateBit1(prob);\n          prob = p + IsRepG1 + state;\n          IfBit0(prob)\n          {\n            UpdateBit0(prob);\n            distance = rep1;\n          }\n          else \n          {\n            UpdateBit1(prob);\n            prob = p + IsRepG2 + state;\n            IfBit0(prob)\n            {\n              UpdateBit0(prob);\n              distance = rep2;\n            }\n            else\n            {\n              UpdateBit1(prob);\n              distance = rep3;\n              rep3 = rep2;\n            }\n            rep2 = rep1;\n          }\n          rep1 = rep0;\n          rep0 = distance;\n        }\n        state = state < kNumLitStates ? 8 : 11;\n        prob = p + RepLenCoder;\n      }\n      {\n        int numBits, offset;\n        CProb *probLen = prob + LenChoice;\n        IfBit0(probLen)\n        {\n          UpdateBit0(probLen);\n          probLen = prob + LenLow + (posState << kLenNumLowBits);\n          offset = 0;\n          numBits = kLenNumLowBits;\n        }\n        else\n        {\n          UpdateBit1(probLen);\n          probLen = prob + LenChoice2;\n          IfBit0(probLen)\n          {\n            UpdateBit0(probLen);\n            probLen = prob + LenMid + (posState << kLenNumMidBits);\n            offset = kLenNumLowSymbols;\n            numBits = kLenNumMidBits;\n          }\n          else\n          {\n            UpdateBit1(probLen);\n            probLen = prob + LenHigh;\n            offset = kLenNumLowSymbols + kLenNumMidSymbols;\n            numBits = kLenNumHighBits;\n          }\n        }\n        RangeDecoderBitTreeDecode(probLen, numBits, len);\n        len += offset;\n      }\n\n      if (state < 4)\n      {\n        int posSlot;\n        state += kNumLitStates;\n        prob = p + PosSlot +\n            ((len < kNumLenToPosStates ? len : kNumLenToPosStates - 1) << \n            kNumPosSlotBits);\n        RangeDecoderBitTreeDecode(prob, kNumPosSlotBits, posSlot);\n        if (posSlot >= kStartPosModelIndex)\n        {\n          int numDirectBits = ((posSlot >> 1) - 1);\n          rep0 = (2 | ((UInt32)posSlot & 1));\n          if (posSlot < kEndPosModelIndex)\n          {\n            rep0 <<= numDirectBits;\n            prob = p + SpecPos + rep0 - posSlot - 1;\n          }\n          else\n          {\n            numDirectBits -= kNumAlignBits;\n            do\n            {\n              RC_NORMALIZE\n              Range >>= 1;\n              rep0 <<= 1;\n              if (Code >= Range)\n              {\n                Code -= Range;\n                rep0 |= 1;\n              }\n            }\n            while (--numDirectBits != 0);\n            prob = p + Align;\n            rep0 <<= kNumAlignBits;\n            numDirectBits = kNumAlignBits;\n          }\n          {\n            int i = 1;\n            int mi = 1;\n            do\n            {\n              CProb *prob3 = prob + mi;\n              RC_GET_BIT2(prob3, mi, ; , rep0 |= i);\n              i <<= 1;\n            }\n            while(--numDirectBits != 0);\n          }\n        }\n        else\n          rep0 = posSlot;\n        if (++rep0 == (UInt32)(0))\n        {\n          /* it's for stream version */\n          len = kLzmaStreamWasFinishedId;\n          break;\n        }\n      }\n\n      len += kMatchMinLen;\n      #ifdef _LZMA_OUT_READ\n      if (rep0 > distanceLimit) \n      #else\n      if (rep0 > nowPos)\n      #endif\n        return LZMA_RESULT_DATA_ERROR;\n\n      #ifdef _LZMA_OUT_READ\n      if (dictionarySize - distanceLimit > (UInt32)len)\n        distanceLimit += len;\n      else\n        distanceLimit = dictionarySize;\n      #endif\n\n      do\n      {\n        #ifdef _LZMA_OUT_READ\n        UInt32 pos = dictionaryPos - rep0;\n        if (pos >= dictionarySize)\n          pos += dictionarySize;\n        previousByte = dictionary[pos];\n        dictionary[dictionaryPos] = previousByte;\n        if (++dictionaryPos == dictionarySize)\n          dictionaryPos = 0;\n        #else\n        previousByte = outStream[nowPos - rep0];\n        #endif\n        len--;\n        outStream[nowPos++] = previousByte;\n      }\n      while(len != 0 && nowPos < outSize);\n    }\n  }\n  RC_NORMALIZE;\n\n  #ifdef _LZMA_OUT_READ\n  vs->Range = Range;\n  vs->Code = Code;\n  vs->DictionaryPos = dictionaryPos;\n  vs->GlobalPos = globalPos + (UInt32)nowPos;\n  vs->DistanceLimit = distanceLimit;\n  vs->Reps[0] = rep0;\n  vs->Reps[1] = rep1;\n  vs->Reps[2] = rep2;\n  vs->Reps[3] = rep3;\n  vs->State = state;\n  vs->RemainLen = len;\n  vs->TempDictionary[0] = tempDictionary[0];\n  #endif\n\n  #ifdef _LZMA_IN_CB\n  vs->Buffer = Buffer;\n  vs->BufferLim = BufferLim;\n  #else\n  *inSizeProcessed = (SizeT)(Buffer - inStream);\n  #endif\n  *outSizeProcessed = nowPos;\n  return LZMA_RESULT_OK;\n}\n"
  },
  {
    "path": "target/linux/bcm63xx/image/lzma-loader/src/LzmaDecode.h",
    "content": "/* \n  LzmaDecode.h\n  LZMA Decoder interface\n\n  LZMA SDK 4.40 Copyright (c) 1999-2006 Igor Pavlov (2006-05-01)\n  http://www.7-zip.org/\n\n  LZMA SDK is licensed under two licenses:\n  1) GNU Lesser General Public License (GNU LGPL)\n  2) Common Public License (CPL)\n  It means that you can select one of these two licenses and \n  follow rules of that license.\n\n  SPECIAL EXCEPTION:\n  Igor Pavlov, as the author of this code, expressly permits you to \n  statically or dynamically link your code (or bind by name) to the \n  interfaces of this file without subjecting your linked code to the \n  terms of the CPL or GNU LGPL. Any modifications or additions \n  to this file, however, are subject to the LGPL or CPL terms.\n*/\n\n#ifndef __LZMADECODE_H\n#define __LZMADECODE_H\n\n#include \"LzmaTypes.h\"\n\n/* #define _LZMA_IN_CB */\n/* Use callback for input data */\n\n/* #define _LZMA_OUT_READ */\n/* Use read function for output data */\n\n/* #define _LZMA_PROB32 */\n/* It can increase speed on some 32-bit CPUs, \n   but memory usage will be doubled in that case */\n\n/* #define _LZMA_LOC_OPT */\n/* Enable local speed optimizations inside code */\n\n#ifdef _LZMA_PROB32\n#define CProb UInt32\n#else\n#define CProb UInt16\n#endif\n\n#define LZMA_RESULT_OK 0\n#define LZMA_RESULT_DATA_ERROR 1\n\n#ifdef _LZMA_IN_CB\ntypedef struct _ILzmaInCallback\n{\n  int (*Read)(void *object, const unsigned char **buffer, SizeT *bufferSize);\n} ILzmaInCallback;\n#endif\n\n#define LZMA_BASE_SIZE 1846\n#define LZMA_LIT_SIZE 768\n\n#define LZMA_PROPERTIES_SIZE 5\n\ntypedef struct _CLzmaProperties\n{\n  int lc;\n  int lp;\n  int pb;\n  #ifdef _LZMA_OUT_READ\n  UInt32 DictionarySize;\n  #endif\n}CLzmaProperties;\n\nint LzmaDecodeProperties(CLzmaProperties *propsRes, const unsigned char *propsData, int size);\n\n#define LzmaGetNumProbs(Properties) (LZMA_BASE_SIZE + (LZMA_LIT_SIZE << ((Properties)->lc + (Properties)->lp)))\n\n#define kLzmaNeedInitId (-2)\n\ntypedef struct _CLzmaDecoderState\n{\n  CLzmaProperties Properties;\n  CProb *Probs;\n\n  #ifdef _LZMA_IN_CB\n  const unsigned char *Buffer;\n  const unsigned char *BufferLim;\n  #endif\n\n  #ifdef _LZMA_OUT_READ\n  unsigned char *Dictionary;\n  UInt32 Range;\n  UInt32 Code;\n  UInt32 DictionaryPos;\n  UInt32 GlobalPos;\n  UInt32 DistanceLimit;\n  UInt32 Reps[4];\n  int State;\n  int RemainLen;\n  unsigned char TempDictionary[4];\n  #endif\n} CLzmaDecoderState;\n\n#ifdef _LZMA_OUT_READ\n#define LzmaDecoderInit(vs) { (vs)->RemainLen = kLzmaNeedInitId; }\n#endif\n\nint LzmaDecode(CLzmaDecoderState *vs,\n    #ifdef _LZMA_IN_CB\n    ILzmaInCallback *inCallback,\n    #else\n    const unsigned char *inStream, SizeT inSize, SizeT *inSizeProcessed,\n    #endif\n    unsigned char *outStream, SizeT outSize, SizeT *outSizeProcessed);\n\n#endif\n"
  },
  {
    "path": "target/linux/bcm63xx/image/lzma-loader/src/LzmaTypes.h",
    "content": "/* \nLzmaTypes.h \n\nTypes for LZMA Decoder\n\nThis file written and distributed to public domain by Igor Pavlov.\nThis file is part of LZMA SDK 4.40 (2006-05-01)\n*/\n\n#ifndef __LZMATYPES_H\n#define __LZMATYPES_H\n\n#ifndef _7ZIP_BYTE_DEFINED\n#define _7ZIP_BYTE_DEFINED\ntypedef unsigned char Byte;\n#endif \n\n#ifndef _7ZIP_UINT16_DEFINED\n#define _7ZIP_UINT16_DEFINED\ntypedef unsigned short UInt16;\n#endif \n\n#ifndef _7ZIP_UINT32_DEFINED\n#define _7ZIP_UINT32_DEFINED\n#ifdef _LZMA_UINT32_IS_ULONG\ntypedef unsigned long UInt32;\n#else\ntypedef unsigned int UInt32;\n#endif\n#endif \n\n/* #define _LZMA_NO_SYSTEM_SIZE_T */\n/* You can use it, if you don't want <stddef.h> */\n\n#ifndef _7ZIP_SIZET_DEFINED\n#define _7ZIP_SIZET_DEFINED\n#ifdef _LZMA_NO_SYSTEM_SIZE_T\ntypedef UInt32 SizeT;\n#else\n#include <stddef.h>\ntypedef size_t SizeT;\n#endif\n#endif\n\n#endif\n"
  },
  {
    "path": "target/linux/bcm63xx/image/lzma-loader/src/Makefile",
    "content": "#\n# Makefile for the LZMA compressed kernel loader for\n# Atheros AR7XXX/AR9XXX based boards\n#\n# Copyright (C) 2020 Álvaro Fernández Rojas <noltari@gmail.com>\n# Copyright (C) 2014 Jonas Gorski <jogo@openwrt.org>\n# Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>\n#\n# Some parts of this file was based on the OpenWrt specific lzma-loader\n# for the BCM47xx and ADM5120 based boards:\n#\tCopyright (C) 2004 Manuel Novoa III (mjn3@codepoet.org)\n#\tCopyright (C) 2005 Mineharu Takahara <mtakahar@yahoo.com>\n#\tCopyright (C) 2005 by Oleg I. Vdovikin <oleg@cs.msu.su>\n#\n# This program is free software; you can redistribute it and/or modify it\n# under the terms of the GNU General Public License version 2 as published\n# by the Free Software Foundation.\n#\n\nLOADER_ADDR\t:=\nKERNEL_ADDR\t:=\nLZMA_TEXT_START\t:= 0x80a00000\nLOADER_DATA\t:=\n\nCC\t\t:= $(CROSS_COMPILE)gcc\nLD\t\t:= $(CROSS_COMPILE)ld\nOBJCOPY\t\t:= $(CROSS_COMPILE)objcopy\nOBJDUMP\t\t:= $(CROSS_COMPILE)objdump\n\nBIN_FLAGS\t:= -O binary -R .reginfo -R .note -R .comment -R .mdebug \\\n\t\t   -R .MIPS.abiflags -S\n\nCFLAGS\t\t= -D__KERNEL__ -Wall -Wstrict-prototypes -Wno-trigraphs -Os \\\n\t\t  -fno-strict-aliasing -fno-common -fomit-frame-pointer -G 0 \\\n\t\t  -mno-abicalls -fno-pic -ffunction-sections -pipe \\\n\t\t  -ffreestanding -fhonour-copts \\\n\t\t  -mabi=32 -march=mips32 \\\n\t\t  -Wa,-32 -Wa,-march=mips32 -Wa,-mips32 -Wa,--trap\nCFLAGS\t\t+= -D_LZMA_PROB32\nCFLAGS\t\t+= -DUART_BASE=$(UART_BASE)\n\nASFLAGS\t\t= $(CFLAGS) -D__ASSEMBLY__\n\nLDFLAGS\t\t= -static --gc-sections -no-warn-mismatch\nLDFLAGS\t\t+= -e startup -T loader.lds -Ttext $(LZMA_TEXT_START)\n\nO_FORMAT \t= $(shell $(OBJDUMP) -i | head -2 | grep elf32)\n\nOBJECTS\t\t:= head.o loader.o cache.o board.o printf.o LzmaDecode.o\n\nifneq ($(strip $(LOADER_DATA)),)\nOBJECTS\t\t+= data.o\nCFLAGS\t\t+= -DLZMA_WRAPPER=1 -DLOADADDR=$(KERNEL_ADDR)\nendif\n\n\nall: loader.elf\n\n# Don't build dependencies, this may die if $(CC) isn't gcc\ndep:\n\ninstall:\n\n%.o : %.c\n\t$(CC) $(CFLAGS) -c -o $@ $<\n\n%.o : %.S\n\t$(CC) $(ASFLAGS) -c -o $@ $<\n\ndata.o: $(LOADER_DATA)\n\t$(LD) -r -b binary --oformat $(O_FORMAT) -T lzma-data.lds -o $@ $<\n\nloader: $(OBJECTS)\n\t$(LD) $(LDFLAGS) -o $@ $(OBJECTS)\n\nloader.bin: loader\n\t$(OBJCOPY) $(BIN_FLAGS) $< $@\n\nloader2.o: loader.bin\n\t$(LD) -r -b binary --oformat $(O_FORMAT) -o $@ $<\n\nloader.elf: loader2.o\n\t$(LD) -e startup -T loader2.lds -Ttext $(LOADER_ADDR) -o $@ $<\n\nmrproper: clean\n\nclean:\n\trm -f loader *.elf *.bin *.o\n"
  },
  {
    "path": "target/linux/bcm63xx/image/lzma-loader/src/board.c",
    "content": "/*\n * BCM63XX specific implementation parts\n *\n * Copyright (C) 2020 Álvaro Fernández Rojas <noltari@gmail.com>\n * Copyright (C) 2014 Jonas Gorski <jogo@openwrt.org>\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of the GNU General Public License version 2 as published\n * by the Free Software Foundation.\n */\n\n#include <stddef.h>\n#include \"config.h\"\n\n#define READREG(r)\t*(volatile unsigned int *)(r)\n#define WRITEREG(r,v)\t*(volatile unsigned int *)(r) = v\n\n#define UART_IR_REG\t0x10\n#define UART_FIFO_REG\t0x14\n\nstatic void wait_xfered(void)\n{\n        unsigned int val;\n\n        do {\n                val = READREG(UART_BASE + UART_IR_REG);\n                if (val & (1 << 5))\n                        break;\n        } while (1);\n}\n\nvoid board_putc(int ch)\n{\n\tif (!UART_BASE)\n\t\treturn;\n\n\twait_xfered();\n\tWRITEREG(UART_BASE + UART_FIFO_REG, ch);\n\twait_xfered();\n}\n"
  },
  {
    "path": "target/linux/bcm63xx/image/lzma-loader/src/cache.c",
    "content": "/*\n * LZMA compressed kernel loader for Atheros AR7XXX/AR9XXX based boards\n *\n * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>\n *\n * The cache manipulation routine has been taken from the U-Boot project.\n *\t(C) Copyright 2003\n *\tWolfgang Denk, DENX Software Engineering, <wd@denx.de>\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of the GNU General Public License version 2 as published\n * by the Free Software Foundation.\n *\n */\n\n#include \"cache.h\"\n#include \"cacheops.h\"\n#include \"config.h\"\n#include \"printf.h\"\n\n#define cache_op(op,addr)\t\t\t\t\t\t\\\n\t__asm__ __volatile__(\t\t\t\t\t\t\\\n\t\"\t.set\tpush\t\t\t\t\t\\n\"\t\\\n\t\"\t.set\tnoreorder\t\t\t\t\\n\"\t\\\n\t\"\t.set\tmips3\\n\\t\t\t\t\t\\n\"\t\\\n\t\"\tcache\t%0, %1\t\t\t\t\t\\n\"\t\\\n\t\"\t.set\tpop\t\t\t\t\t\\n\"\t\\\n\t:\t\t\t\t\t\t\t\t\\\n\t: \"i\" (op), \"R\" (*(unsigned char *)(addr)))\n\nvoid flush_cache(unsigned long start_addr, unsigned long size)\n{\n\tunsigned long lsize = CONFIG_CACHELINE_SIZE;\n\tunsigned long addr = start_addr & ~(lsize - 1);\n\tunsigned long aend = (start_addr + size + (lsize - 1)) & ~(lsize - 1);\n\n\tprintf(\"blasting from 0x%08x to 0x%08x (0x%08x - 0x%08x)\\n\", start_addr, size, addr, aend);\n\n\twhile (1) {\n\t\tcache_op(Hit_Writeback_Inv_D, addr);\n\t\tcache_op(Hit_Invalidate_I, addr);\n\t\tif (addr == aend)\n\t\t\tbreak;\n\t\taddr += lsize;\n\t}\n}\n"
  },
  {
    "path": "target/linux/bcm63xx/image/lzma-loader/src/cache.h",
    "content": "/*\n * LZMA compressed kernel loader for Atheros AR7XXX/AR9XXX based boards\n *\n * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of the GNU General Public License version 2 as published\n * by the Free Software Foundation.\n *\n */\n\n#ifndef __CACHE_H\n#define __CACHE_H\n\nvoid flush_cache(unsigned long start_addr, unsigned long size);\n\n#endif /* __CACHE_H */\n"
  },
  {
    "path": "target/linux/bcm63xx/image/lzma-loader/src/cacheops.h",
    "content": "/*\n * Cache operations for the cache instruction.\n *\n * This file is subject to the terms and conditions of the GNU General Public\n * License.  See the file \"COPYING\" in the main directory of this archive\n * for more details.\n *\n * (C) Copyright 1996, 97, 99, 2002, 03 Ralf Baechle\n * (C) Copyright 1999 Silicon Graphics, Inc.\n */\n#ifndef\t__ASM_CACHEOPS_H\n#define\t__ASM_CACHEOPS_H\n\n/*\n * Cache Operations available on all MIPS processors with R4000-style caches\n */\n#define Index_Invalidate_I      0x00\n#define Index_Writeback_Inv_D   0x01\n#define Index_Load_Tag_I\t0x04\n#define Index_Load_Tag_D\t0x05\n#define Index_Store_Tag_I\t0x08\n#define Index_Store_Tag_D\t0x09\n#if defined(CONFIG_CPU_LOONGSON2)\n#define Hit_Invalidate_I\t0x00\n#else\n#define Hit_Invalidate_I\t0x10\n#endif\n#define Hit_Invalidate_D\t0x11\n#define Hit_Writeback_Inv_D\t0x15\n\n/*\n * R4000-specific cacheops\n */\n#define Create_Dirty_Excl_D\t0x0d\n#define Fill\t\t\t0x14\n#define Hit_Writeback_I\t\t0x18\n#define Hit_Writeback_D\t\t0x19\n\n/*\n * R4000SC and R4400SC-specific cacheops\n */\n#define Index_Invalidate_SI     0x02\n#define Index_Writeback_Inv_SD  0x03\n#define Index_Load_Tag_SI\t0x06\n#define Index_Load_Tag_SD\t0x07\n#define Index_Store_Tag_SI\t0x0A\n#define Index_Store_Tag_SD\t0x0B\n#define Create_Dirty_Excl_SD\t0x0f\n#define Hit_Invalidate_SI\t0x12\n#define Hit_Invalidate_SD\t0x13\n#define Hit_Writeback_Inv_SD\t0x17\n#define Hit_Writeback_SD\t0x1b\n#define Hit_Set_Virtual_SI\t0x1e\n#define Hit_Set_Virtual_SD\t0x1f\n\n/*\n * R5000-specific cacheops\n */\n#define R5K_Page_Invalidate_S\t0x17\n\n/*\n * RM7000-specific cacheops\n */\n#define Page_Invalidate_T\t0x16\n\n/*\n * R10000-specific cacheops\n *\n * Cacheops 0x02, 0x06, 0x0a, 0x0c-0x0e, 0x16, 0x1a and 0x1e are unused.\n * Most of the _S cacheops are identical to the R4000SC _SD cacheops.\n */\n#define Index_Writeback_Inv_S\t0x03\n#define Index_Load_Tag_S\t0x07\n#define Index_Store_Tag_S\t0x0B\n#define Hit_Invalidate_S\t0x13\n#define Cache_Barrier\t\t0x14\n#define Hit_Writeback_Inv_S\t0x17\n#define Index_Load_Data_I\t0x18\n#define Index_Load_Data_D\t0x19\n#define Index_Load_Data_S\t0x1b\n#define Index_Store_Data_I\t0x1c\n#define Index_Store_Data_D\t0x1d\n#define Index_Store_Data_S\t0x1f\n\n#endif\t/* __ASM_CACHEOPS_H */\n"
  },
  {
    "path": "target/linux/bcm63xx/image/lzma-loader/src/config.h",
    "content": "/*\n * LZMA compressed kernel loader for Atheros AR7XXX/AR9XXX based boards\n *\n * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of the GNU General Public License version 2 as published\n * by the Free Software Foundation.\n *\n */\n\n#ifndef _CONFIG_H_\n#define _CONFIG_H_\n\n#define CONFIG_ICACHE_SIZE\t(32 * 1024)\n#define CONFIG_DCACHE_SIZE\t(32 * 1024)\n#define CONFIG_CACHELINE_SIZE\t16\n\n#endif /* _CONFIG_H_ */\n"
  },
  {
    "path": "target/linux/bcm63xx/image/lzma-loader/src/cp0regdef.h",
    "content": "/*\n * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle\n *\n * Copyright (C) 2001, Monta Vista Software\n * Author: jsun@mvista.com or jsun@junsun.net\n */\n#ifndef _cp0regdef_h_\n#define _cp0regdef_h_\n\n#define CP0_INDEX $0\n#define CP0_RANDOM $1\n#define CP0_ENTRYLO0 $2\n#define CP0_ENTRYLO1 $3\n#define CP0_CONTEXT $4\n#define CP0_PAGEMASK $5\n#define CP0_WIRED $6\n#define CP0_BADVADDR $8\n#define CP0_COUNT $9\n#define CP0_ENTRYHI $10\n#define CP0_COMPARE $11\n#define CP0_STATUS $12\n#define CP0_CAUSE $13\n#define CP0_EPC $14\n#define CP0_PRID $15\n#define CP0_CONFIG $16\n#define CP0_LLADDR $17\n#define CP0_WATCHLO $18\n#define CP0_WATCHHI $19\n#define CP0_XCONTEXT $20\n#define CP0_FRAMEMASK $21\n#define CP0_DIAGNOSTIC $22\n#define CP0_PERFORMANCE $25\n#define CP0_ECC $26\n#define CP0_CACHEERR $27\n#define CP0_TAGLO $28\n#define CP0_TAGHI $29\n#define CP0_ERROREPC $30\n\n#define read_32bit_c0_register(reg,sel)\t\t\t\t\t\\\n({\tint __res;\t\t\t\t\t\t\t\\\n\tif (sel == 0)\t\t\t\t\t\t\t\\\n\t\t__asm__ __volatile__(\t\t\t\t\t\\\n\t\t\t\"mfc0\\t%0, \" #reg \"\\n\\t\"\t\t\t\\\n\t\t\t: \"=r\" (__res));\t\t\t\t\\\n\telse\t\t\t\t\t\t\t\t\\\n\t\t__asm__ __volatile__(\t\t\t\t\t\\\n\t\t\t\".set\\tmips32\\n\\t\"\t\t\t\t\\\n\t\t\t\"mfc0\\t%0, \" #reg \", \" #sel \"\\n\\t\"\t\t\\\n\t\t\t\".set mips0\\n\\t\"\t\t\t\t\\\n\t\t\t: \"=r\" (__res));\t\t\t\t\\\n\t__res;\t\t\t\t\t\t\t\t\\\n})\n\n#endif\n"
  },
  {
    "path": "target/linux/bcm63xx/image/lzma-loader/src/head.S",
    "content": "/*\n * LZMA compressed kernel loader for Atheros AR7XXX/AR9XXX based boards\n *\n * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>\n *\n * Some parts of this code was based on the OpenWrt specific lzma-loader\n * for the BCM47xx and ADM5120 based boards:\n *\tCopyright (C) 2004 Manuel Novoa III (mjn3@codepoet.org)\n *\tCopyright (C) 2005 by Oleg I. Vdovikin <oleg@cs.msu.su>\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of the GNU General Public License version 2 as published\n * by the Free Software Foundation.\n */\n\n#include <asm/asm.h>\n#include <asm/regdef.h>\n#include \"cp0regdef.h\"\n#include \"cacheops.h\"\n#include \"config.h\"\n\n#define KSEG0\t\t0x80000000\n\n\t.macro\tehb\n\tsll     zero, 3\n\t.endm\n\n\t.text\n\nLEAF(startup)\n\t.set noreorder\n\t.set mips32\n\n\tmtc0\tzero, CP0_WATCHLO\t# clear watch registers\n\tmtc0\tzero, CP0_WATCHHI\n\tmtc0\tzero, CP0_CAUSE\t\t# clear before writing status register\n\n\tmfc0\tt0, CP0_STATUS\n\tli\tt1, 0x1000001f\n\tor\tt0, t1\n\txori\tt0, 0x1f\n\tmtc0\tt0, CP0_STATUS\n\tehb\n\n\tmtc0\tzero, CP0_COUNT\n\tmtc0\tzero, CP0_COMPARE\n\tehb\n\n\tla\tt0, __reloc_label\t# get linked address of label\n\tbal\t__reloc_label\t\t# branch and link to label to\n\tnop\t\t\t\t# get actual address\n__reloc_label:\n\tsubu\tt0, ra, t0\t\t# get reloc_delta\n\n\tbeqz\tt0, __reloc_done         # if delta is 0 we are in the right place\n\tnop\n\n\t/* Copy our code to the right place */\n\tla\tt1, _code_start\t\t# get linked address of _code_start\n\tla\tt2, _code_end\t\t# get linked address of _code_end\n\taddu\tt0, t0, t1\t\t# calculate actual address of _code_start\n\n__reloc_copy:\n\tlw\tt3, 0(t0)\n\tsw\tt3, 0(t1)\n\tadd\tt1, 4\n\tblt\tt1, t2, __reloc_copy\n\tadd\tt0, 4\n\n\t/* flush cache */\n\tla\tt0, _code_start\n\tla\tt1, _code_end\n\n\tli\tt2, ~(CONFIG_CACHELINE_SIZE - 1)\n\tand\tt0, t2\n\tand\tt1, t2\n\tli\tt2, CONFIG_CACHELINE_SIZE\n\n\tb\t__flush_check\n\tnop\n\n__flush_line:\n\tcache\tHit_Writeback_Inv_D, 0(t0)\n\tcache\tHit_Invalidate_I, 0(t0)\n\tadd\tt0, t2\n\n__flush_check:\n\tbne\tt0, t1, __flush_line\n\tnop\n\n\tsync\n\n__reloc_done:\n\n\t/* clear bss */\n\tla\tt0, _bss_start\n\tla\tt1, _bss_end\n\tb\t__bss_check\n\tnop\n\n__bss_fill:\n\tsw\tzero, 0(t0)\n\taddi\tt0, 4\n\n__bss_check:\n\tbne\tt0, t1, __bss_fill\n\tnop\n\n\t/* Setup new \"C\" stack */\n\tla\tsp, _stack\n\n\t/* reserve stack space for a0-a3 registers */\n\tsubu\tsp, 16\n\n\t/* jump to the decompressor routine */\n\tla\tt0, loader_main\n\tjr\tt0\n\tnop\n\n\t.set reorder\nEND(startup)\n"
  },
  {
    "path": "target/linux/bcm63xx/image/lzma-loader/src/loader.c",
    "content": "/*\n * LZMA compressed kernel loader for Atheros AR7XXX/AR9XXX based boards\n *\n * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>\n *\n * Some parts of this code was based on the OpenWrt specific lzma-loader\n * for the BCM47xx and ADM5120 based boards:\n *\tCopyright (C) 2004 Manuel Novoa III (mjn3@codepoet.org)\n *\tCopyright (C) 2005 Mineharu Takahara <mtakahar@yahoo.com>\n *\tCopyright (C) 2005 by Oleg I. Vdovikin <oleg@cs.msu.su>\n *\n * The image_header structure has been taken from the U-Boot project.\n *\t(C) Copyright 2008 Semihalf\n *\t(C) Copyright 2000-2005\n *\tWolfgang Denk, DENX Software Engineering, wd@denx.de.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of the GNU General Public License version 2 as published\n * by the Free Software Foundation.\n */\n\n#include <stddef.h>\n#include <stdint.h>\n\n#include \"config.h\"\n#include \"cache.h\"\n#include \"printf.h\"\n#include \"LzmaDecode.h\"\n\n#define KSEG0\t\t\t0x80000000\n#define KSEG1\t\t\t0xa0000000\n\n#define KSEG1ADDR(a)\t\t((((unsigned)(a)) & 0x1fffffffU) | KSEG1)\n\n#undef LZMA_DEBUG\n\n#ifdef LZMA_DEBUG\n#  define DBG(f, a...)\tprintf(f, ## a)\n#else\n#  define DBG(f, a...)\tdo {} while (0)\n#endif\n\n/* beyond the image end, size not known in advance */\nextern unsigned char workspace[];\n\n\nstatic CLzmaDecoderState lzma_state;\nstatic unsigned char *lzma_data;\nstatic unsigned long lzma_datasize;\nstatic unsigned long lzma_outsize;\nstatic unsigned long kernel_la;\n\nstatic void halt(void)\n{\n\tprintf(\"\\nSystem halted!\\n\");\n\tfor(;;);\n}\n\nstatic __inline__ unsigned char lzma_get_byte(void)\n{\n\tunsigned char c;\n\n\tlzma_datasize--;\n\tc = *lzma_data++;\n\n\treturn c;\n}\n\nstatic int lzma_init_props(void)\n{\n\tunsigned char props[LZMA_PROPERTIES_SIZE];\n\tint res;\n\tint i;\n\n\t/* read lzma properties */\n\tfor (i = 0; i < LZMA_PROPERTIES_SIZE; i++)\n\t\tprops[i] = lzma_get_byte();\n\n\t/* read the lower half of uncompressed size in the header */\n\tlzma_outsize = ((SizeT) lzma_get_byte()) +\n\t\t       ((SizeT) lzma_get_byte() << 8) +\n\t\t       ((SizeT) lzma_get_byte() << 16) +\n\t\t       ((SizeT) lzma_get_byte() << 24);\n\n\t/* skip rest of the header (upper half of uncompressed size) */\n\tfor (i = 0; i < 4; i++)\n\t\tlzma_get_byte();\n\n\tres = LzmaDecodeProperties(&lzma_state.Properties, props,\n\t\t\t\t\tLZMA_PROPERTIES_SIZE);\n\treturn res;\n}\n\nstatic int lzma_decompress(unsigned char *outStream)\n{\n\tSizeT ip, op;\n\tint ret;\n\n\tlzma_state.Probs = (CProb *) workspace;\n\n\tret = LzmaDecode(&lzma_state, lzma_data, lzma_datasize, &ip, outStream,\n\t\t\t lzma_outsize, &op);\n\n\tif (ret != LZMA_RESULT_OK) {\n\t\tint i;\n\n\t\tDBG(\"LzmaDecode error %d at %08x, osize:%d ip:%d op:%d\\n\",\n\t\t    ret, lzma_data + ip, lzma_outsize, ip, op);\n\n\t\tfor (i = 0; i < 16; i++)\n\t\t\tDBG(\"%02x \", lzma_data[ip + i]);\n\n\t\tDBG(\"\\n\");\n\t}\n\n\treturn ret;\n}\n\nstatic void lzma_init_data(void)\n{\n\textern unsigned char _lzma_data_start[];\n\textern unsigned char _lzma_data_end[];\n\n\tkernel_la = LOADADDR;\n\tlzma_data = _lzma_data_start;\n\tlzma_datasize = _lzma_data_end - _lzma_data_start;\n}\n\nvoid loader_main(unsigned long reg_a0, unsigned long reg_a1,\n\t\t unsigned long reg_a2, unsigned long reg_a3)\n{\n\tvoid (*kernel_entry) (unsigned long, unsigned long, unsigned long,\n\t\t\t      unsigned long);\n\tint res;\n\n\tprintf(\"\\n\\nOpenWrt kernel loader for BCM63XX\\n\");\n\tprintf(\"Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>\\n\");\n\tprintf(\"Copyright (C) 2014 Jonas Gorski <jogo@openwrt.org>\\n\");\n\tprintf(\"Copyright (C) 2020 Alvaro Fernandez Rojas <noltari@gmail.com>\\n\");\n\n\tlzma_init_data();\n\n\tres = lzma_init_props();\n\tif (res != LZMA_RESULT_OK) {\n\t\tprintf(\"Incorrect LZMA stream properties!\\n\");\n\t\thalt();\n\t}\n\n\tprintf(\"Decompressing kernel... \");\n\n\tres = lzma_decompress((unsigned char *) kernel_la);\n\tif (res != LZMA_RESULT_OK) {\n\t\tprintf(\"failed, \");\n\t\tswitch (res) {\n\t\tcase LZMA_RESULT_DATA_ERROR:\n\t\t\tprintf(\"data error!\\n\");\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tprintf(\"unknown error %d!\\n\", res);\n\t\t}\n\t\thalt();\n\t} else {\n\t\tprintf(\"done!\\n\");\n\t}\n\n\tflush_cache(kernel_la, lzma_outsize);\n\n\tprintf(\"Starting kernel at %08x...\\n\\n\", kernel_la);\n\n\tkernel_entry = (void *) kernel_la;\n\tkernel_entry(reg_a0, reg_a1, reg_a2, reg_a3);\n}\n"
  },
  {
    "path": "target/linux/bcm63xx/image/lzma-loader/src/loader.lds",
    "content": "OUTPUT_ARCH(mips)\nSECTIONS {\n\t.text : {\n\t\t_code_start = .;\n\t\t*(.text)\n\t\t*(.text.*)\n\t\t*(.rodata)\n\t\t*(.rodata.*)\n\t\t*(.data.lzma)\n\t}\n\n\t. = ALIGN(32);\n\t.data : {\n\t\t*(.data)\n\t\t*(.data.*)\n\t}\n\n\t. = ALIGN(32);\n\t_code_end = .;\n\n\t_bss_start = .;\n\t.bss : {\n\t\t*(.bss)\n\t\t*(.bss.*)\n\t}\n\n\t. = ALIGN(32);\n\t_bss_end = .;\n\n\t. = . + 8192;\n\t_stack = .;\n\n\tworkspace = .;\n}\n"
  },
  {
    "path": "target/linux/bcm63xx/image/lzma-loader/src/loader2.lds",
    "content": "OUTPUT_ARCH(mips)\nSECTIONS {\n\t.text : {\n\t\tstartup = .;\n\t\t*(.text)\n\t\t*(.text.*)\n\t\t*(.data)\n\t\t*(.data.*)\n\t}\n}\n"
  },
  {
    "path": "target/linux/bcm63xx/image/lzma-loader/src/lzma-data.lds",
    "content": "OUTPUT_ARCH(mips)\nSECTIONS {\n\t.data.lzma : {\n\t\t_lzma_data_start = .;\n\t\t*(.data)\n\t\t_lzma_data_end = .;\n\t}\n}\n"
  },
  {
    "path": "target/linux/bcm63xx/image/lzma-loader/src/printf.c",
    "content": "/*\n * Copyright (C) 2001 MontaVista Software Inc.\n * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net\n *\n * This program is free software; you can redistribute  it and/or modify it\n * under  the terms of  the GNU General  Public License as published by the\n * Free Software Foundation;  either version 2 of the  License, or (at your\n * option) any later version.\n *\n */\n\n#include\t\"printf.h\"\n\nextern void board_putc(int ch);\n\n/* this is the maximum width for a variable */\n#define\t\tLP_MAX_BUF\t256\n\n/* macros */\n#define\t\tIsDigit(x)\t( ((x) >= '0') && ((x) <= '9') )\n#define\t\tCtod(x)\t\t( (x) - '0')\n\n/* forward declaration */\nstatic int PrintChar(char *, char, int, int);\nstatic int PrintString(char *, char *, int, int);\nstatic int PrintNum(char *, unsigned long, int, int, int, int, char, int);\n\n/* private variable */\nstatic const char theFatalMsg[] = \"fatal error in lp_Print!\";\n\n/* -*-\n * A low level printf() function.\n */\nstatic void\nlp_Print(void (*output)(void *, char *, int),\n\t void * arg,\n\t char *fmt,\n\t va_list ap)\n{\n\n#define \tOUTPUT(arg, s, l)  \\\n  { if (((l) < 0) || ((l) > LP_MAX_BUF)) { \\\n       (*output)(arg, (char*)theFatalMsg, sizeof(theFatalMsg)-1); for(;;); \\\n    } else { \\\n      (*output)(arg, s, l); \\\n    } \\\n  }\n\n    char buf[LP_MAX_BUF];\n\n    char c;\n    char *s;\n    long int num;\n\n    int longFlag;\n    int negFlag;\n    int width;\n    int prec;\n    int ladjust;\n    char padc;\n\n    int length;\n\n    for(;;) {\n\t{\n\t    /* scan for the next '%' */\n\t    char *fmtStart = fmt;\n\t    while ( (*fmt != '\\0') && (*fmt != '%')) {\n\t\tfmt ++;\n\t    }\n\n\t    /* flush the string found so far */\n\t    OUTPUT(arg, fmtStart, fmt-fmtStart);\n\n\t    /* are we hitting the end? */\n\t    if (*fmt == '\\0') break;\n\t}\n\n\t/* we found a '%' */\n\tfmt ++;\n\n\t/* check for long */\n\tif (*fmt == 'l') {\n\t    longFlag = 1;\n\t    fmt ++;\n\t} else {\n\t    longFlag = 0;\n\t}\n\n\t/* check for other prefixes */\n\twidth = 0;\n\tprec = -1;\n\tladjust = 0;\n\tpadc = ' ';\n\n\tif (*fmt == '-') {\n\t    ladjust = 1;\n\t    fmt ++;\n\t}\n\n\tif (*fmt == '0') {\n\t    padc = '0';\n\t    fmt++;\n\t}\n\n\tif (IsDigit(*fmt)) {\n\t    while (IsDigit(*fmt)) {\n\t\twidth = 10 * width + Ctod(*fmt++);\n\t    }\n\t}\n\n\tif (*fmt == '.') {\n\t    fmt ++;\n\t    if (IsDigit(*fmt)) {\n\t\tprec = 0;\n\t\twhile (IsDigit(*fmt)) {\n\t\t    prec = prec*10 + Ctod(*fmt++);\n\t\t}\n\t    }\n\t}\n\n\n\t/* check format flag */\n\tnegFlag = 0;\n\tswitch (*fmt) {\n\t case 'b':\n\t    if (longFlag) {\n\t\tnum = va_arg(ap, long int);\n\t    } else {\n\t\tnum = va_arg(ap, int);\n\t    }\n\t    length = PrintNum(buf, num, 2, 0, width, ladjust, padc, 0);\n\t    OUTPUT(arg, buf, length);\n\t    break;\n\n\t case 'd':\n\t case 'D':\n\t    if (longFlag) {\n\t\tnum = va_arg(ap, long int);\n\t    } else {\n\t\tnum = va_arg(ap, int);\n\t    }\n\t    if (num < 0) {\n\t\tnum = - num;\n\t\tnegFlag = 1;\n\t    }\n\t    length = PrintNum(buf, num, 10, negFlag, width, ladjust, padc, 0);\n\t    OUTPUT(arg, buf, length);\n\t    break;\n\n\t case 'o':\n\t case 'O':\n\t    if (longFlag) {\n\t\tnum = va_arg(ap, long int);\n\t    } else {\n\t\tnum = va_arg(ap, int);\n\t    }\n\t    length = PrintNum(buf, num, 8, 0, width, ladjust, padc, 0);\n\t    OUTPUT(arg, buf, length);\n\t    break;\n\n\t case 'u':\n\t case 'U':\n\t    if (longFlag) {\n\t\tnum = va_arg(ap, long int);\n\t    } else {\n\t\tnum = va_arg(ap, int);\n\t    }\n\t    length = PrintNum(buf, num, 10, 0, width, ladjust, padc, 0);\n\t    OUTPUT(arg, buf, length);\n\t    break;\n\n\t case 'x':\n\t    if (longFlag) {\n\t\tnum = va_arg(ap, long int);\n\t    } else {\n\t\tnum = va_arg(ap, int);\n\t    }\n\t    length = PrintNum(buf, num, 16, 0, width, ladjust, padc, 0);\n\t    OUTPUT(arg, buf, length);\n\t    break;\n\n\t case 'X':\n\t    if (longFlag) {\n\t\tnum = va_arg(ap, long int);\n\t    } else {\n\t\tnum = va_arg(ap, int);\n\t    }\n\t    length = PrintNum(buf, num, 16, 0, width, ladjust, padc, 1);\n\t    OUTPUT(arg, buf, length);\n\t    break;\n\n\t case 'c':\n\t    c = (char)va_arg(ap, int);\n\t    length = PrintChar(buf, c, width, ladjust);\n\t    OUTPUT(arg, buf, length);\n\t    break;\n\n\t case 's':\n\t    s = (char*)va_arg(ap, char *);\n\t    length = PrintString(buf, s, width, ladjust);\n\t    OUTPUT(arg, buf, length);\n\t    break;\n\n\t case '\\0':\n\t    fmt --;\n\t    break;\n\n\t default:\n\t    /* output this char as it is */\n\t    OUTPUT(arg, fmt, 1);\n\t}\t/* switch (*fmt) */\n\n\tfmt ++;\n    }\t\t/* for(;;) */\n\n    /* special termination call */\n    OUTPUT(arg, \"\\0\", 1);\n}\n\n\n/* --------------- local help functions --------------------- */\nstatic int\nPrintChar(char * buf, char c, int length, int ladjust)\n{\n    int i;\n\n    if (length < 1) length = 1;\n    if (ladjust) {\n\t*buf = c;\n\tfor (i=1; i< length; i++) buf[i] = ' ';\n    } else {\n\tfor (i=0; i< length-1; i++) buf[i] = ' ';\n\tbuf[length - 1] = c;\n    }\n    return length;\n}\n\nstatic int\nPrintString(char * buf, char* s, int length, int ladjust)\n{\n    int i;\n    int len=0;\n    char* s1 = s;\n    while (*s1++) len++;\n    if (length < len) length = len;\n\n    if (ladjust) {\n\tfor (i=0; i< len; i++) buf[i] = s[i];\n\tfor (i=len; i< length; i++) buf[i] = ' ';\n    } else {\n\tfor (i=0; i< length-len; i++) buf[i] = ' ';\n\tfor (i=length-len; i < length; i++) buf[i] = s[i-length+len];\n    }\n    return length;\n}\n\nstatic int\nPrintNum(char * buf, unsigned long u, int base, int negFlag,\n\t int length, int ladjust, char padc, int upcase)\n{\n    /* algorithm :\n     *  1. prints the number from left to right in reverse form.\n     *  2. fill the remaining spaces with padc if length is longer than\n     *     the actual length\n     *     TRICKY : if left adjusted, no \"0\" padding.\n     *\t\t    if negtive, insert  \"0\" padding between \"0\" and number.\n     *  3. if (!ladjust) we reverse the whole string including paddings\n     *  4. otherwise we only reverse the actual string representing the num.\n     */\n\n    int actualLength =0;\n    char *p = buf;\n    int i;\n\n    do {\n\tint tmp = u %base;\n\tif (tmp <= 9) {\n\t    *p++ = '0' + tmp;\n\t} else if (upcase) {\n\t    *p++ = 'A' + tmp - 10;\n\t} else {\n\t    *p++ = 'a' + tmp - 10;\n\t}\n\tu /= base;\n    } while (u != 0);\n\n    if (negFlag) {\n\t*p++ = '-';\n    }\n\n    /* figure out actual length and adjust the maximum length */\n    actualLength = p - buf;\n    if (length < actualLength) length = actualLength;\n\n    /* add padding */\n    if (ladjust) {\n\tpadc = ' ';\n    }\n    if (negFlag && !ladjust && (padc == '0')) {\n\tfor (i = actualLength-1; i< length-1; i++) buf[i] = padc;\n\tbuf[length -1] = '-';\n    } else {\n\tfor (i = actualLength; i< length; i++) buf[i] = padc;\n    }\n\n\n    /* prepare to reverse the string */\n    {\n\tint begin = 0;\n\tint end;\n\tif (ladjust) {\n\t    end = actualLength - 1;\n\t} else {\n\t    end = length -1;\n\t}\n\n\twhile (end > begin) {\n\t    char tmp = buf[begin];\n\t    buf[begin] = buf[end];\n\t    buf[end] = tmp;\n\t    begin ++;\n\t    end --;\n\t}\n    }\n\n    /* adjust the string pointer */\n    return length;\n}\n\nstatic void printf_output(void *arg, char *s, int l)\n{\n    int i;\n\n    // special termination call\n    if ((l==1) && (s[0] == '\\0')) return;\n\n    for (i=0; i< l; i++) {\n\tboard_putc(s[i]);\n\tif (s[i] == '\\n') board_putc('\\r');\n    }\n}\n\nvoid printf(char *fmt, ...)\n{\n    va_list ap;\n    va_start(ap, fmt);\n    lp_Print(printf_output, 0, fmt, ap);\n    va_end(ap);\n}\n"
  },
  {
    "path": "target/linux/bcm63xx/image/lzma-loader/src/printf.h",
    "content": "/*\n * Copyright (C) 2001 MontaVista Software Inc.\n * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net\n *\n * This program is free software; you can redistribute  it and/or modify it\n * under  the terms of  the GNU General  Public License as published by the\n * Free Software Foundation;  either version 2 of the  License, or (at your\n * option) any later version.\n *\n */\n\n#ifndef _printf_h_\n#define _printf_h_\n\n#include <stdarg.h>\nvoid printf(char *fmt, ...);\n\n#endif /* _printf_h_ */\n"
  },
  {
    "path": "target/linux/bcm63xx/modules.mk",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2010 OpenWrt.org\n\ndefine KernelPackage/pcmcia-bcm63xx\n  SUBMENU:=$(PCMCIA_MENU)\n  TITLE:=Broadcom BCM63xx PCMCIA support\n  DEPENDS:=@TARGET_bcm63xx +kmod-pcmcia-rsrc\n  KCONFIG:=CONFIG_PCMCIA_BCM63XX\n  FILES:=$(LINUX_DIR)/drivers/pcmcia/bcm63xx_pcmcia.ko\n  AUTOLOAD:=$(call AutoLoad,41,bcm63xx_pcmcia)\nendef\n\ndefine KernelPackage/pcmcia-bcm63xx/description\n  Kernel support for PCMCIA/CardBus controller on the BCM63xx SoC\nendef\n\n$(eval $(call KernelPackage,pcmcia-bcm63xx))\n\ndefine KernelPackage/bcm63xx-udc\n  SUBMENU:=$(USB_MENU)\n  TITLE:=Broadcom BCM63xx UDC support\n  DEPENDS:=@TARGET_bcm63xx +kmod-usb-gadget\n  KCONFIG:=CONFIG_USB_BCM63XX_UDC\n  FILES:= \\\n\t$(LINUX_DIR)/drivers/usb/gadget/udc/bcm63xx_udc.ko\n  AUTOLOAD:=$(call AutoLoad,51,bcm63xx_udc)\n  $(call AddDepends/usb)\nendef\n\ndefine KernelPackage/bcm63xx-udc/description\n  Kernel support for the USB gadget (device) controller on the BCM63xx SoC\nendef\n\n$(eval $(call KernelPackage,bcm63xx-udc))\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/020-v5.12-bcm63xx_enet-batch-process-rx-path.patch",
    "content": "From 9cbfea02c1dbee0afb9128f065e6e793672b9ff7 Mon Sep 17 00:00:00 2001\nFrom: Sieng Piaw Liew <liew.s.piaw@gmail.com>\nDate: Wed, 6 Jan 2021 22:42:02 +0800\nSubject: [PATCH 1/7] bcm63xx_enet: batch process rx path\n\nUse netif_receive_skb_list to batch process rx skb.\nTested on BCM6328 320 MHz using iperf3 -M 512, increasing performance\nby 12.5%.\n\nBefore:\n[ ID] Interval           Transfer     Bandwidth       Retr\n[  4]   0.00-30.00  sec   120 MBytes  33.7 Mbits/sec  277         sender\n[  4]   0.00-30.00  sec   120 MBytes  33.5 Mbits/sec            receiver\n\nAfter:\n[ ID] Interval           Transfer     Bandwidth       Retr\n[  4]   0.00-30.00  sec   136 MBytes  37.9 Mbits/sec  203         sender\n[  4]   0.00-30.00  sec   135 MBytes  37.7 Mbits/sec            receiver\n\nSigned-off-by: Sieng Piaw Liew <liew.s.piaw@gmail.com>\nAcked-by: Florian Fainelli <f.fainelli@gmail.com>\nSigned-off-by: Jakub Kicinski <kuba@kernel.org>\n---\n drivers/net/ethernet/broadcom/bcm63xx_enet.c | 6 +++++-\n 1 file changed, 5 insertions(+), 1 deletion(-)\n\n--- a/drivers/net/ethernet/broadcom/bcm63xx_enet.c\n+++ b/drivers/net/ethernet/broadcom/bcm63xx_enet.c\n@@ -297,10 +297,12 @@ static void bcm_enet_refill_rx_timer(str\n static int bcm_enet_receive_queue(struct net_device *dev, int budget)\n {\n \tstruct bcm_enet_priv *priv;\n+\tstruct list_head rx_list;\n \tstruct device *kdev;\n \tint processed;\n \n \tpriv = netdev_priv(dev);\n+\tINIT_LIST_HEAD(&rx_list);\n \tkdev = &priv->pdev->dev;\n \tprocessed = 0;\n \n@@ -391,10 +393,12 @@ static int bcm_enet_receive_queue(struct\n \t\tskb->protocol = eth_type_trans(skb, dev);\n \t\tdev->stats.rx_packets++;\n \t\tdev->stats.rx_bytes += len;\n-\t\tnetif_receive_skb(skb);\n+\t\tlist_add_tail(&skb->list, &rx_list);\n \n \t} while (--budget > 0);\n \n+\tnetif_receive_skb_list(&rx_list);\n+\n \tif (processed || !priv->rx_desc_count) {\n \t\tbcm_enet_refill_rx(dev);\n \n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/021-v5.12-bcm63xx_enet-add-BQL-support.patch",
    "content": "From 4c59b0f5543db80abbbe9efdd9b25e7899501db5 Mon Sep 17 00:00:00 2001\nFrom: Sieng Piaw Liew <liew.s.piaw@gmail.com>\nDate: Wed, 6 Jan 2021 22:42:03 +0800\nSubject: [PATCH 2/7] bcm63xx_enet: add BQL support\n\nAdd Byte Queue Limits support to reduce/remove bufferbloat in\nbcm63xx_enet.\n\nSigned-off-by: Sieng Piaw Liew <liew.s.piaw@gmail.com>\nAcked-by: Florian Fainelli <f.fainelli@gmail.com>\nSigned-off-by: Jakub Kicinski <kuba@kernel.org>\n---\n drivers/net/ethernet/broadcom/bcm63xx_enet.c | 9 +++++++++\n 1 file changed, 9 insertions(+)\n\n--- a/drivers/net/ethernet/broadcom/bcm63xx_enet.c\n+++ b/drivers/net/ethernet/broadcom/bcm63xx_enet.c\n@@ -417,9 +417,11 @@ static int bcm_enet_receive_queue(struct\n static int bcm_enet_tx_reclaim(struct net_device *dev, int force)\n {\n \tstruct bcm_enet_priv *priv;\n+\tunsigned int bytes;\n \tint released;\n \n \tpriv = netdev_priv(dev);\n+\tbytes = 0;\n \treleased = 0;\n \n \twhile (priv->tx_desc_count < priv->tx_ring_size) {\n@@ -456,10 +458,13 @@ static int bcm_enet_tx_reclaim(struct ne\n \t\tif (desc->len_stat & DMADESC_UNDER_MASK)\n \t\t\tdev->stats.tx_errors++;\n \n+\t\tbytes += skb->len;\n \t\tdev_kfree_skb(skb);\n \t\treleased++;\n \t}\n \n+\tnetdev_completed_queue(dev, released, bytes);\n+\n \tif (netif_queue_stopped(dev) && released)\n \t\tnetif_wake_queue(dev);\n \n@@ -626,6 +631,8 @@ bcm_enet_start_xmit(struct sk_buff *skb,\n \tdesc->len_stat = len_stat;\n \twmb();\n \n+\tnetdev_sent_queue(dev, skb->len);\n+\n \t/* kick tx dma */\n \tenet_dmac_writel(priv, priv->dma_chan_en_mask,\n \t\t\t\t ENETDMAC_CHANCFG, priv->tx_chan);\n@@ -1169,6 +1176,7 @@ static int bcm_enet_stop(struct net_devi\n \tkdev = &priv->pdev->dev;\n \n \tnetif_stop_queue(dev);\n+\tnetdev_reset_queue(dev);\n \tnapi_disable(&priv->napi);\n \tif (priv->has_phy)\n \t\tphy_stop(dev->phydev);\n@@ -2338,6 +2346,7 @@ static int bcm_enetsw_stop(struct net_de\n \n \tdel_timer_sync(&priv->swphy_poll);\n \tnetif_stop_queue(dev);\n+\tnetdev_reset_queue(dev);\n \tnapi_disable(&priv->napi);\n \tdel_timer_sync(&priv->rx_timeout);\n \n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/022-v5.12-bcm63xx_enet-add-xmit_more-support.patch",
    "content": "From 375281d3a6dcabaa98f489ee412aedca6d99dffb Mon Sep 17 00:00:00 2001\nFrom: Sieng Piaw Liew <liew.s.piaw@gmail.com>\nDate: Wed, 6 Jan 2021 22:42:04 +0800\nSubject: [PATCH 3/7] bcm63xx_enet: add xmit_more support\n\nSupport bulking hardware TX queue by using netdev_xmit_more().\n\nSigned-off-by: Sieng Piaw Liew <liew.s.piaw@gmail.com>\nAcked-by: Florian Fainelli <f.fainelli@gmail.com>\nSigned-off-by: Jakub Kicinski <kuba@kernel.org>\n---\n drivers/net/ethernet/broadcom/bcm63xx_enet.c | 3 ++-\n 1 file changed, 2 insertions(+), 1 deletion(-)\n\n--- a/drivers/net/ethernet/broadcom/bcm63xx_enet.c\n+++ b/drivers/net/ethernet/broadcom/bcm63xx_enet.c\n@@ -634,7 +634,8 @@ bcm_enet_start_xmit(struct sk_buff *skb,\n \tnetdev_sent_queue(dev, skb->len);\n \n \t/* kick tx dma */\n-\tenet_dmac_writel(priv, priv->dma_chan_en_mask,\n+\tif (!netdev_xmit_more() || !priv->tx_desc_count)\n+\t\tenet_dmac_writel(priv, priv->dma_chan_en_mask,\n \t\t\t\t ENETDMAC_CHANCFG, priv->tx_chan);\n \n \t/* stop queue if no more desc available */\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/023-v5.12-bcm63xx_enet-alloc-rx-skb-with-NET_IP_ALIGN.patch",
    "content": "From c4a207865e7ea310dc146ff4aa1b0aa0c78d3fe1 Mon Sep 17 00:00:00 2001\nFrom: Sieng Piaw Liew <liew.s.piaw@gmail.com>\nDate: Wed, 6 Jan 2021 22:42:05 +0800\nSubject: [PATCH 4/7] bcm63xx_enet: alloc rx skb with NET_IP_ALIGN\n\nUse netdev_alloc_skb_ip_align on newer SoCs with integrated switch\n(enetsw) when refilling RX. Increases packet processing performance\nby 30% (with netif_receive_skb_list).\n\nNon-enetsw SoCs cannot function with the extra pad so continue to use\nthe regular netdev_alloc_skb.\n\nTested on BCM6328 320 MHz and iperf3 -M 512 to measure packet/sec\nperformance.\n\nBefore:\n[ ID] Interval Transfer Bandwidth Retr\n[ 4] 0.00-30.00 sec 120 MBytes 33.7 Mbits/sec 277 sender\n[ 4] 0.00-30.00 sec 120 MBytes 33.5 Mbits/sec receiver\n\nAfter (+netif_receive_skb_list):\n[ 4] 0.00-30.00 sec 155 MBytes 43.3 Mbits/sec 354 sender\n[ 4] 0.00-30.00 sec 154 MBytes 43.1 Mbits/sec receiver\n\nSigned-off-by: Sieng Piaw Liew <liew.s.piaw@gmail.com>\nAcked-by: Florian Fainelli <f.fainelli@gmail.com>\nSigned-off-by: Jakub Kicinski <kuba@kernel.org>\n---\n drivers/net/ethernet/broadcom/bcm63xx_enet.c | 5 ++++-\n 1 file changed, 4 insertions(+), 1 deletion(-)\n\n--- a/drivers/net/ethernet/broadcom/bcm63xx_enet.c\n+++ b/drivers/net/ethernet/broadcom/bcm63xx_enet.c\n@@ -237,7 +237,10 @@ static int bcm_enet_refill_rx(struct net\n \t\tdesc = &priv->rx_desc_cpu[desc_idx];\n \n \t\tif (!priv->rx_skb[desc_idx]) {\n-\t\t\tskb = netdev_alloc_skb(dev, priv->rx_skb_size);\n+\t\t\tif (priv->enet_is_sw)\n+\t\t\t\tskb = netdev_alloc_skb_ip_align(dev, priv->rx_skb_size);\n+\t\t\telse\n+\t\t\t\tskb = netdev_alloc_skb(dev, priv->rx_skb_size);\n \t\t\tif (!skb)\n \t\t\t\tbreak;\n \t\t\tpriv->rx_skb[desc_idx] = skb;\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/024-v5.12-bcm63xx_enet-consolidate-rx-SKB-ring-cleanup-code.patch",
    "content": "From 3d0b72654b0c8304424503e7560ee8635dd56340 Mon Sep 17 00:00:00 2001\nFrom: Sieng Piaw Liew <liew.s.piaw@gmail.com>\nDate: Wed, 6 Jan 2021 22:42:06 +0800\nSubject: [PATCH 5/7] bcm63xx_enet: consolidate rx SKB ring cleanup code\n\nThe rx SKB ring use the same code for cleanup at various points.\nCombine them into a function to reduce lines of code.\n\nSigned-off-by: Sieng Piaw Liew <liew.s.piaw@gmail.com>\nAcked-by: Florian Fainelli <f.fainelli@gmail.com>\nSigned-off-by: Jakub Kicinski <kuba@kernel.org>\n---\n drivers/net/ethernet/broadcom/bcm63xx_enet.c | 72 ++++++--------------\n 1 file changed, 22 insertions(+), 50 deletions(-)\n\n--- a/drivers/net/ethernet/broadcom/bcm63xx_enet.c\n+++ b/drivers/net/ethernet/broadcom/bcm63xx_enet.c\n@@ -860,6 +860,24 @@ static void bcm_enet_adjust_link(struct\n \t\tpriv->pause_tx ? \"tx\" : \"off\");\n }\n \n+static void bcm_enet_free_rx_skb_ring(struct device *kdev, struct bcm_enet_priv *priv)\n+{\n+\tint i;\n+\n+\tfor (i = 0; i < priv->rx_ring_size; i++) {\n+\t\tstruct bcm_enet_desc *desc;\n+\n+\t\tif (!priv->rx_skb[i])\n+\t\t\tcontinue;\n+\n+\t\tdesc = &priv->rx_desc_cpu[i];\n+\t\tdma_unmap_single(kdev, desc->address, priv->rx_skb_size,\n+\t\t\t\t DMA_FROM_DEVICE);\n+\t\tkfree_skb(priv->rx_skb[i]);\n+\t}\n+\tkfree(priv->rx_skb);\n+}\n+\n /*\n  * open callback, allocate dma rings & buffers and start rx operation\n  */\n@@ -1084,18 +1102,7 @@ static int bcm_enet_open(struct net_devi\n \treturn 0;\n \n out:\n-\tfor (i = 0; i < priv->rx_ring_size; i++) {\n-\t\tstruct bcm_enet_desc *desc;\n-\n-\t\tif (!priv->rx_skb[i])\n-\t\t\tcontinue;\n-\n-\t\tdesc = &priv->rx_desc_cpu[i];\n-\t\tdma_unmap_single(kdev, desc->address, priv->rx_skb_size,\n-\t\t\t\t DMA_FROM_DEVICE);\n-\t\tkfree_skb(priv->rx_skb[i]);\n-\t}\n-\tkfree(priv->rx_skb);\n+\tbcm_enet_free_rx_skb_ring(kdev, priv);\n \n out_free_tx_skb:\n \tkfree(priv->tx_skb);\n@@ -1174,7 +1181,6 @@ static int bcm_enet_stop(struct net_devi\n {\n \tstruct bcm_enet_priv *priv;\n \tstruct device *kdev;\n-\tint i;\n \n \tpriv = netdev_priv(dev);\n \tkdev = &priv->pdev->dev;\n@@ -1203,20 +1209,9 @@ static int bcm_enet_stop(struct net_devi\n \tbcm_enet_tx_reclaim(dev, 1);\n \n \t/* free the rx skb ring */\n-\tfor (i = 0; i < priv->rx_ring_size; i++) {\n-\t\tstruct bcm_enet_desc *desc;\n-\n-\t\tif (!priv->rx_skb[i])\n-\t\t\tcontinue;\n-\n-\t\tdesc = &priv->rx_desc_cpu[i];\n-\t\tdma_unmap_single(kdev, desc->address, priv->rx_skb_size,\n-\t\t\t\t DMA_FROM_DEVICE);\n-\t\tkfree_skb(priv->rx_skb[i]);\n-\t}\n+\tbcm_enet_free_rx_skb_ring(kdev, priv);\n \n \t/* free remaining allocated memory */\n-\tkfree(priv->rx_skb);\n \tkfree(priv->tx_skb);\n \tdma_free_coherent(kdev, priv->rx_desc_alloc_size,\n \t\t\t  priv->rx_desc_cpu, priv->rx_desc_dma);\n@@ -2303,18 +2298,7 @@ static int bcm_enetsw_open(struct net_de\n \treturn 0;\n \n out:\n-\tfor (i = 0; i < priv->rx_ring_size; i++) {\n-\t\tstruct bcm_enet_desc *desc;\n-\n-\t\tif (!priv->rx_skb[i])\n-\t\t\tcontinue;\n-\n-\t\tdesc = &priv->rx_desc_cpu[i];\n-\t\tdma_unmap_single(kdev, desc->address, priv->rx_skb_size,\n-\t\t\t\t DMA_FROM_DEVICE);\n-\t\tkfree_skb(priv->rx_skb[i]);\n-\t}\n-\tkfree(priv->rx_skb);\n+\tbcm_enet_free_rx_skb_ring(kdev, priv);\n \n out_free_tx_skb:\n \tkfree(priv->tx_skb);\n@@ -2343,7 +2327,6 @@ static int bcm_enetsw_stop(struct net_de\n {\n \tstruct bcm_enet_priv *priv;\n \tstruct device *kdev;\n-\tint i;\n \n \tpriv = netdev_priv(dev);\n \tkdev = &priv->pdev->dev;\n@@ -2366,20 +2349,9 @@ static int bcm_enetsw_stop(struct net_de\n \tbcm_enet_tx_reclaim(dev, 1);\n \n \t/* free the rx skb ring */\n-\tfor (i = 0; i < priv->rx_ring_size; i++) {\n-\t\tstruct bcm_enet_desc *desc;\n-\n-\t\tif (!priv->rx_skb[i])\n-\t\t\tcontinue;\n-\n-\t\tdesc = &priv->rx_desc_cpu[i];\n-\t\tdma_unmap_single(kdev, desc->address, priv->rx_skb_size,\n-\t\t\t\t DMA_FROM_DEVICE);\n-\t\tkfree_skb(priv->rx_skb[i]);\n-\t}\n+\tbcm_enet_free_rx_skb_ring(kdev, priv);\n \n \t/* free remaining allocated memory */\n-\tkfree(priv->rx_skb);\n \tkfree(priv->tx_skb);\n \tdma_free_coherent(kdev, priv->rx_desc_alloc_size,\n \t\t\t  priv->rx_desc_cpu, priv->rx_desc_dma);\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/025-v5.12-bcm63xx_enet-convert-to-build_skb.patch",
    "content": "From d27de0ef5ef995df2cc5f5c006c0efcf0a62b6af Mon Sep 17 00:00:00 2001\nFrom: Sieng Piaw Liew <liew.s.piaw@gmail.com>\nDate: Wed, 6 Jan 2021 22:42:07 +0800\nSubject: [PATCH 6/7] bcm63xx_enet: convert to build_skb\n\nWe can increase the efficiency of rx path by using buffers to receive\npackets then build SKBs around them just before passing into the network\nstack. In contrast, preallocating SKBs too early reduces CPU cache\nefficiency.\n\nCheck if we're in NAPI context when refilling RX. Normally we're almost\nalways running in NAPI context. Dispatch to napi_alloc_frag directly\ninstead of relying on netdev_alloc_frag which does the same but\nwith the overhead of local_bh_disable/enable.\n\nTested on BCM6328 320 MHz and iperf3 -M 512 to measure packet/sec\nperformance. Included netif_receive_skb_list and NET_IP_ALIGN\noptimizations.\n\nBefore:\n[ ID] Interval           Transfer     Bandwidth       Retr\n[  4]   0.00-10.00  sec  49.9 MBytes  41.9 Mbits/sec  197         sender\n[  4]   0.00-10.00  sec  49.3 MBytes  41.3 Mbits/sec            receiver\n\nAfter:\n[ ID] Interval           Transfer     Bandwidth       Retr\n[  4]   0.00-30.00  sec   171 MBytes  47.8 Mbits/sec  272         sender\n[  4]   0.00-30.00  sec   170 MBytes  47.6 Mbits/sec            receiver\n\nSigned-off-by: Sieng Piaw Liew <liew.s.piaw@gmail.com>\nAcked-by: Florian Fainelli <f.fainelli@gmail.com>\nSigned-off-by: Jakub Kicinski <kuba@kernel.org>\n---\n drivers/net/ethernet/broadcom/bcm63xx_enet.c | 111 ++++++++++---------\n drivers/net/ethernet/broadcom/bcm63xx_enet.h |  14 ++-\n 2 files changed, 71 insertions(+), 54 deletions(-)\n\n--- a/drivers/net/ethernet/broadcom/bcm63xx_enet.c\n+++ b/drivers/net/ethernet/broadcom/bcm63xx_enet.c\n@@ -220,7 +220,7 @@ static void bcm_enet_mdio_write_mii(stru\n /*\n  * refill rx queue\n  */\n-static int bcm_enet_refill_rx(struct net_device *dev)\n+static int bcm_enet_refill_rx(struct net_device *dev, bool napi_mode)\n {\n \tstruct bcm_enet_priv *priv;\n \n@@ -228,29 +228,29 @@ static int bcm_enet_refill_rx(struct net\n \n \twhile (priv->rx_desc_count < priv->rx_ring_size) {\n \t\tstruct bcm_enet_desc *desc;\n-\t\tstruct sk_buff *skb;\n-\t\tdma_addr_t p;\n \t\tint desc_idx;\n \t\tu32 len_stat;\n \n \t\tdesc_idx = priv->rx_dirty_desc;\n \t\tdesc = &priv->rx_desc_cpu[desc_idx];\n \n-\t\tif (!priv->rx_skb[desc_idx]) {\n-\t\t\tif (priv->enet_is_sw)\n-\t\t\t\tskb = netdev_alloc_skb_ip_align(dev, priv->rx_skb_size);\n+\t\tif (!priv->rx_buf[desc_idx]) {\n+\t\t\tvoid *buf;\n+\n+\t\t\tif (likely(napi_mode))\n+\t\t\t\tbuf = napi_alloc_frag(priv->rx_frag_size);\n \t\t\telse\n-\t\t\t\tskb = netdev_alloc_skb(dev, priv->rx_skb_size);\n-\t\t\tif (!skb)\n+\t\t\t\tbuf = netdev_alloc_frag(priv->rx_frag_size);\n+\t\t\tif (unlikely(!buf))\n \t\t\t\tbreak;\n-\t\t\tpriv->rx_skb[desc_idx] = skb;\n-\t\t\tp = dma_map_single(&priv->pdev->dev, skb->data,\n-\t\t\t\t\t   priv->rx_skb_size,\n-\t\t\t\t\t   DMA_FROM_DEVICE);\n-\t\t\tdesc->address = p;\n+\t\t\tpriv->rx_buf[desc_idx] = buf;\n+\t\t\tdesc->address = dma_map_single(&priv->pdev->dev,\n+\t\t\t\t\t\t       buf + priv->rx_buf_offset,\n+\t\t\t\t\t\t       priv->rx_buf_size,\n+\t\t\t\t\t\t       DMA_FROM_DEVICE);\n \t\t}\n \n-\t\tlen_stat = priv->rx_skb_size << DMADESC_LENGTH_SHIFT;\n+\t\tlen_stat = priv->rx_buf_size << DMADESC_LENGTH_SHIFT;\n \t\tlen_stat |= DMADESC_OWNER_MASK;\n \t\tif (priv->rx_dirty_desc == priv->rx_ring_size - 1) {\n \t\t\tlen_stat |= (DMADESC_WRAP_MASK >> priv->dma_desc_shift);\n@@ -290,7 +290,7 @@ static void bcm_enet_refill_rx_timer(str\n \tstruct net_device *dev = priv->net_dev;\n \n \tspin_lock(&priv->rx_lock);\n-\tbcm_enet_refill_rx(dev);\n+\tbcm_enet_refill_rx(dev, false);\n \tspin_unlock(&priv->rx_lock);\n }\n \n@@ -320,6 +320,7 @@ static int bcm_enet_receive_queue(struct\n \t\tint desc_idx;\n \t\tu32 len_stat;\n \t\tunsigned int len;\n+\t\tvoid *buf;\n \n \t\tdesc_idx = priv->rx_curr_desc;\n \t\tdesc = &priv->rx_desc_cpu[desc_idx];\n@@ -365,16 +366,14 @@ static int bcm_enet_receive_queue(struct\n \t\t}\n \n \t\t/* valid packet */\n-\t\tskb = priv->rx_skb[desc_idx];\n+\t\tbuf = priv->rx_buf[desc_idx];\n \t\tlen = (len_stat & DMADESC_LENGTH_MASK) >> DMADESC_LENGTH_SHIFT;\n \t\t/* don't include FCS */\n \t\tlen -= 4;\n \n \t\tif (len < copybreak) {\n-\t\t\tstruct sk_buff *nskb;\n-\n-\t\t\tnskb = napi_alloc_skb(&priv->napi, len);\n-\t\t\tif (!nskb) {\n+\t\t\tskb = napi_alloc_skb(&priv->napi, len);\n+\t\t\tif (unlikely(!skb)) {\n \t\t\t\t/* forget packet, just rearm desc */\n \t\t\t\tdev->stats.rx_dropped++;\n \t\t\t\tcontinue;\n@@ -382,14 +381,21 @@ static int bcm_enet_receive_queue(struct\n \n \t\t\tdma_sync_single_for_cpu(kdev, desc->address,\n \t\t\t\t\t\tlen, DMA_FROM_DEVICE);\n-\t\t\tmemcpy(nskb->data, skb->data, len);\n+\t\t\tmemcpy(skb->data, buf + priv->rx_buf_offset, len);\n \t\t\tdma_sync_single_for_device(kdev, desc->address,\n \t\t\t\t\t\t   len, DMA_FROM_DEVICE);\n-\t\t\tskb = nskb;\n \t\t} else {\n-\t\t\tdma_unmap_single(&priv->pdev->dev, desc->address,\n-\t\t\t\t\t priv->rx_skb_size, DMA_FROM_DEVICE);\n-\t\t\tpriv->rx_skb[desc_idx] = NULL;\n+\t\t\tdma_unmap_single(kdev, desc->address,\n+\t\t\t\t\t priv->rx_buf_size, DMA_FROM_DEVICE);\n+\t\t\tpriv->rx_buf[desc_idx] = NULL;\n+\n+\t\t\tskb = build_skb(buf, priv->rx_frag_size);\n+\t\t\tif (unlikely(!skb)) {\n+\t\t\t\tskb_free_frag(buf);\n+\t\t\t\tdev->stats.rx_dropped++;\n+\t\t\t\tcontinue;\n+\t\t\t}\n+\t\t\tskb_reserve(skb, priv->rx_buf_offset);\n \t\t}\n \n \t\tskb_put(skb, len);\n@@ -403,7 +409,7 @@ static int bcm_enet_receive_queue(struct\n \tnetif_receive_skb_list(&rx_list);\n \n \tif (processed || !priv->rx_desc_count) {\n-\t\tbcm_enet_refill_rx(dev);\n+\t\tbcm_enet_refill_rx(dev, true);\n \n \t\t/* kick rx dma */\n \t\tenet_dmac_writel(priv, priv->dma_chan_en_mask,\n@@ -860,22 +866,22 @@ static void bcm_enet_adjust_link(struct\n \t\tpriv->pause_tx ? \"tx\" : \"off\");\n }\n \n-static void bcm_enet_free_rx_skb_ring(struct device *kdev, struct bcm_enet_priv *priv)\n+static void bcm_enet_free_rx_buf_ring(struct device *kdev, struct bcm_enet_priv *priv)\n {\n \tint i;\n \n \tfor (i = 0; i < priv->rx_ring_size; i++) {\n \t\tstruct bcm_enet_desc *desc;\n \n-\t\tif (!priv->rx_skb[i])\n+\t\tif (!priv->rx_buf[i])\n \t\t\tcontinue;\n \n \t\tdesc = &priv->rx_desc_cpu[i];\n-\t\tdma_unmap_single(kdev, desc->address, priv->rx_skb_size,\n+\t\tdma_unmap_single(kdev, desc->address, priv->rx_buf_size,\n \t\t\t\t DMA_FROM_DEVICE);\n-\t\tkfree_skb(priv->rx_skb[i]);\n+\t\tskb_free_frag(priv->rx_buf[i]);\n \t}\n-\tkfree(priv->rx_skb);\n+\tkfree(priv->rx_buf);\n }\n \n /*\n@@ -987,10 +993,10 @@ static int bcm_enet_open(struct net_devi\n \tpriv->tx_curr_desc = 0;\n \tspin_lock_init(&priv->tx_lock);\n \n-\t/* init & fill rx ring with skbs */\n-\tpriv->rx_skb = kcalloc(priv->rx_ring_size, sizeof(struct sk_buff *),\n+\t/* init & fill rx ring with buffers */\n+\tpriv->rx_buf = kcalloc(priv->rx_ring_size, sizeof(void *),\n \t\t\t       GFP_KERNEL);\n-\tif (!priv->rx_skb) {\n+\tif (!priv->rx_buf) {\n \t\tret = -ENOMEM;\n \t\tgoto out_free_tx_skb;\n \t}\n@@ -1007,8 +1013,8 @@ static int bcm_enet_open(struct net_devi\n \t\tenet_dmac_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0,\n \t\t\t\tENETDMAC_BUFALLOC, priv->rx_chan);\n \n-\tif (bcm_enet_refill_rx(dev)) {\n-\t\tdev_err(kdev, \"cannot allocate rx skb queue\\n\");\n+\tif (bcm_enet_refill_rx(dev, false)) {\n+\t\tdev_err(kdev, \"cannot allocate rx buffer queue\\n\");\n \t\tret = -ENOMEM;\n \t\tgoto out;\n \t}\n@@ -1102,7 +1108,7 @@ static int bcm_enet_open(struct net_devi\n \treturn 0;\n \n out:\n-\tbcm_enet_free_rx_skb_ring(kdev, priv);\n+\tbcm_enet_free_rx_buf_ring(kdev, priv);\n \n out_free_tx_skb:\n \tkfree(priv->tx_skb);\n@@ -1208,8 +1214,8 @@ static int bcm_enet_stop(struct net_devi\n \t/* force reclaim of all tx buffers */\n \tbcm_enet_tx_reclaim(dev, 1);\n \n-\t/* free the rx skb ring */\n-\tbcm_enet_free_rx_skb_ring(kdev, priv);\n+\t/* free the rx buffer ring */\n+\tbcm_enet_free_rx_buf_ring(kdev, priv);\n \n \t/* free remaining allocated memory */\n \tkfree(priv->tx_skb);\n@@ -1633,9 +1639,12 @@ static int bcm_enet_change_mtu(struct ne\n \t * align rx buffer size to dma burst len, account FCS since\n \t * it's appended\n \t */\n-\tpriv->rx_skb_size = ALIGN(actual_mtu + ETH_FCS_LEN,\n+\tpriv->rx_buf_size = ALIGN(actual_mtu + ETH_FCS_LEN,\n \t\t\t\t  priv->dma_maxburst * 4);\n \n+\tpriv->rx_frag_size = SKB_DATA_ALIGN(priv->rx_buf_offset + priv->rx_buf_size) +\n+\t\t\t\t\t    SKB_DATA_ALIGN(sizeof(struct skb_shared_info));\n+\n \tdev->mtu = new_mtu;\n \treturn 0;\n }\n@@ -1720,6 +1729,7 @@ static int bcm_enet_probe(struct platfor\n \n \tpriv->enet_is_sw = false;\n \tpriv->dma_maxburst = BCMENET_DMA_MAXBURST;\n+\tpriv->rx_buf_offset = NET_SKB_PAD;\n \n \tret = bcm_enet_change_mtu(dev, dev->mtu);\n \tif (ret)\n@@ -2137,7 +2147,7 @@ static int bcm_enetsw_open(struct net_de\n \tpriv->tx_skb = kcalloc(priv->tx_ring_size, sizeof(struct sk_buff *),\n \t\t\t       GFP_KERNEL);\n \tif (!priv->tx_skb) {\n-\t\tdev_err(kdev, \"cannot allocate rx skb queue\\n\");\n+\t\tdev_err(kdev, \"cannot allocate tx skb queue\\n\");\n \t\tret = -ENOMEM;\n \t\tgoto out_free_tx_ring;\n \t}\n@@ -2147,11 +2157,11 @@ static int bcm_enetsw_open(struct net_de\n \tpriv->tx_curr_desc = 0;\n \tspin_lock_init(&priv->tx_lock);\n \n-\t/* init & fill rx ring with skbs */\n-\tpriv->rx_skb = kcalloc(priv->rx_ring_size, sizeof(struct sk_buff *),\n+\t/* init & fill rx ring with buffers */\n+\tpriv->rx_buf = kcalloc(priv->rx_ring_size, sizeof(void *),\n \t\t\t       GFP_KERNEL);\n-\tif (!priv->rx_skb) {\n-\t\tdev_err(kdev, \"cannot allocate rx skb queue\\n\");\n+\tif (!priv->rx_buf) {\n+\t\tdev_err(kdev, \"cannot allocate rx buffer queue\\n\");\n \t\tret = -ENOMEM;\n \t\tgoto out_free_tx_skb;\n \t}\n@@ -2198,8 +2208,8 @@ static int bcm_enetsw_open(struct net_de\n \tenet_dma_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0,\n \t\t\tENETDMA_BUFALLOC_REG(priv->rx_chan));\n \n-\tif (bcm_enet_refill_rx(dev)) {\n-\t\tdev_err(kdev, \"cannot allocate rx skb queue\\n\");\n+\tif (bcm_enet_refill_rx(dev, false)) {\n+\t\tdev_err(kdev, \"cannot allocate rx buffer queue\\n\");\n \t\tret = -ENOMEM;\n \t\tgoto out;\n \t}\n@@ -2298,7 +2308,7 @@ static int bcm_enetsw_open(struct net_de\n \treturn 0;\n \n out:\n-\tbcm_enet_free_rx_skb_ring(kdev, priv);\n+\tbcm_enet_free_rx_buf_ring(kdev, priv);\n \n out_free_tx_skb:\n \tkfree(priv->tx_skb);\n@@ -2348,8 +2358,8 @@ static int bcm_enetsw_stop(struct net_de\n \t/* force reclaim of all tx buffers */\n \tbcm_enet_tx_reclaim(dev, 1);\n \n-\t/* free the rx skb ring */\n-\tbcm_enet_free_rx_skb_ring(kdev, priv);\n+\t/* free the rx buffer ring */\n+\tbcm_enet_free_rx_buf_ring(kdev, priv);\n \n \t/* free remaining allocated memory */\n \tkfree(priv->tx_skb);\n@@ -2648,6 +2658,7 @@ static int bcm_enetsw_probe(struct platf\n \tpriv->rx_ring_size = BCMENET_DEF_RX_DESC;\n \tpriv->tx_ring_size = BCMENET_DEF_TX_DESC;\n \tpriv->dma_maxburst = BCMENETSW_DMA_MAXBURST;\n+\tpriv->rx_buf_offset = NET_SKB_PAD + NET_IP_ALIGN;\n \n \tpd = dev_get_platdata(&pdev->dev);\n \tif (pd) {\n--- a/drivers/net/ethernet/broadcom/bcm63xx_enet.h\n+++ b/drivers/net/ethernet/broadcom/bcm63xx_enet.h\n@@ -230,11 +230,17 @@ struct bcm_enet_priv {\n \t/* next dirty rx descriptor to refill */\n \tint rx_dirty_desc;\n \n-\t/* size of allocated rx skbs */\n-\tunsigned int rx_skb_size;\n+\t/* size of allocated rx buffers */\n+\tunsigned int rx_buf_size;\n \n-\t/* list of skb given to hw for rx */\n-\tstruct sk_buff **rx_skb;\n+\t/* allocated rx buffer offset */\n+\tunsigned int rx_buf_offset;\n+\n+\t/* size of allocated rx frag */\n+\tunsigned int rx_frag_size;\n+\n+\t/* list of buffer given to hw for rx */\n+\tvoid **rx_buf;\n \n \t/* used when rx skb allocation failed, so we defer rx queue\n \t * refill */\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/026-v5.12-bcm63xx_enet-improve-rx-loop.patch",
    "content": "From ae2259eebeacb7753e3043278957b45840123972 Mon Sep 17 00:00:00 2001\nFrom: Sieng Piaw Liew <liew.s.piaw@gmail.com>\nDate: Wed, 6 Jan 2021 22:42:08 +0800\nSubject: [PATCH 7/7] bcm63xx_enet: improve rx loop\n\nUse existing rx processed count to track against budget, thereby making\nbudget decrement operation redundant.\n\nrx_desc_count can be calculated outside the rx loop, making the loop a\nbit smaller.\n\nSigned-off-by: Sieng Piaw Liew <liew.s.piaw@gmail.com>\nAcked-by: Florian Fainelli <f.fainelli@gmail.com>\nSigned-off-by: Jakub Kicinski <kuba@kernel.org>\n---\n drivers/net/ethernet/broadcom/bcm63xx_enet.c | 4 ++--\n 1 file changed, 2 insertions(+), 2 deletions(-)\n\n--- a/drivers/net/ethernet/broadcom/bcm63xx_enet.c\n+++ b/drivers/net/ethernet/broadcom/bcm63xx_enet.c\n@@ -339,7 +339,6 @@ static int bcm_enet_receive_queue(struct\n \t\tpriv->rx_curr_desc++;\n \t\tif (priv->rx_curr_desc == priv->rx_ring_size)\n \t\t\tpriv->rx_curr_desc = 0;\n-\t\tpriv->rx_desc_count--;\n \n \t\t/* if the packet does not have start of packet _and_\n \t\t * end of packet flag set, then just recycle it */\n@@ -404,9 +403,10 @@ static int bcm_enet_receive_queue(struct\n \t\tdev->stats.rx_bytes += len;\n \t\tlist_add_tail(&skb->list, &rx_list);\n \n-\t} while (--budget > 0);\n+\t} while (processed < budget);\n \n \tnetif_receive_skb_list(&rx_list);\n+\tpriv->rx_desc_count -= processed;\n \n \tif (processed || !priv->rx_desc_count) {\n \t\tbcm_enet_refill_rx(dev, true);\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/027-v5.12-bcm63xx_enet-fix-kernel-panic.patch",
    "content": "From 90eda07518ea7e8d1b3e6445eb3633eef9f65218 Mon Sep 17 00:00:00 2001\nFrom: Sieng Piaw Liew <liew.s.piaw@gmail.com>\nDate: Mon, 22 Feb 2021 09:15:12 +0800\nSubject: [PATCH net] bcm63xx_enet: fix sporadic kernel panic\n\nIn ndo_stop functions, netdev_completed_queue() is called during forced\ntx reclaim, after netdev_reset_queue(). This may trigger kernel panic if\nthere is any tx skb left.\n\nThis patch moves netdev_reset_queue() to after tx reclaim, so BQL can\ncomplete successfully then reset.\n\nSigned-off-by: Sieng Piaw Liew <liew.s.piaw@gmail.com>\nAcked-by: Florian Fainelli <f.fainelli@gmail.com>\nFixes: 4c59b0f5543d (\"bcm63xx_enet: add BQL support\")\nSigned-off-by: Jakub Kicinski <kuba@kernel.org>\n---\n drivers/net/ethernet/broadcom/bcm63xx_enet.c | 8 ++++++--\n 1 file changed, 6 insertions(+), 2 deletions(-)\n\n--- a/drivers/net/ethernet/broadcom/bcm63xx_enet.c\n+++ b/drivers/net/ethernet/broadcom/bcm63xx_enet.c\n@@ -1192,7 +1192,6 @@ static int bcm_enet_stop(struct net_devi\n \tkdev = &priv->pdev->dev;\n \n \tnetif_stop_queue(dev);\n-\tnetdev_reset_queue(dev);\n \tnapi_disable(&priv->napi);\n \tif (priv->has_phy)\n \t\tphy_stop(dev->phydev);\n@@ -1231,6 +1230,9 @@ static int bcm_enet_stop(struct net_devi\n \tif (priv->has_phy)\n \t\tphy_disconnect(dev->phydev);\n \n+\t/* reset BQL after forced tx reclaim to not kernel panic */\n+\tnetdev_reset_queue(dev);\n+\n \treturn 0;\n }\n \n@@ -2343,7 +2345,6 @@ static int bcm_enetsw_stop(struct net_de\n \n \tdel_timer_sync(&priv->swphy_poll);\n \tnetif_stop_queue(dev);\n-\tnetdev_reset_queue(dev);\n \tnapi_disable(&priv->napi);\n \tdel_timer_sync(&priv->rx_timeout);\n \n@@ -2371,6 +2372,9 @@ static int bcm_enetsw_stop(struct net_de\n \t\tfree_irq(priv->irq_tx, dev);\n \tfree_irq(priv->irq_rx, dev);\n \n+\t/* reset BQL after forced tx reclaim to not kernel panic */\n+\tnetdev_reset_queue(dev);\n+\n \treturn 0;\n }\n \n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/100-MIPS-BCM63XX-add-USB-host-clock-enable-delay.patch",
    "content": "From 80a2f983e9f44dbc3e01ae31c62d877846a7f791 Mon Sep 17 00:00:00 2001\nFrom: Florian Fainelli <florian@openwrt.org>\nDate: Mon, 28 Jan 2013 20:06:19 +0100\nSubject: [PATCH 01/11] MIPS: BCM63XX: add USB host clock enable delay\n\nKnowledge of the clock setup delay should remain at the clock level (so\nit can be clock specific and CPU specific). Add the 100 milliseconds\nrequired clock delay for the USB host clock when it gets enabled.\n\nSigned-off-by: Florian Fainelli <florian@openwrt.org>\n---\n arch/mips/bcm63xx/clk.c |    5 +++++\n 1 file changed, 5 insertions(+)\n\n--- a/arch/mips/bcm63xx/clk.c\n+++ b/arch/mips/bcm63xx/clk.c\n@@ -214,6 +214,11 @@ static void usbh_set(struct clk *clk, in\n \t\tbcm_hwclock_set(CKCTL_6362_USBH_EN, enable);\n \telse if (BCMCPU_IS_6368())\n \t\tbcm_hwclock_set(CKCTL_6368_USBH_EN, enable);\n+\telse\n+\t\treturn;\n+\n+\tif (enable)\n+\t\tmsleep(100);\n }\n \n static struct clk clk_usbh = {\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/100-macronix_nand_block_protection_support.patch",
    "content": "bcm63xx: fix booting with Kernel 5.10\n\nThis is a workaround to make the target overall bootable. With this more\npeople should be able to test the Kernel 5.10 and report further issues.\n\nSuggested-by: Daniel González Cabanelas <dgcbueu@gmail.com>\nSigned-off-by: Paul Spooren <mail@aparcar.org>\n--- a/drivers/mtd/nand/raw/nand_macronix.c\n+++ b/drivers/mtd/nand/raw/nand_macronix.c\n@@ -323,7 +323,7 @@ static int macronix_nand_init(struct nan\n \n \tmacronix_nand_fix_broken_get_timings(chip);\n \tmacronix_nand_onfi_init(chip);\n-\tmacronix_nand_block_protection_support(chip);\n+\t//macronix_nand_block_protection_support(chip);\n \tmacronix_nand_deep_power_down_support(chip);\n \n \treturn 0;\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/101-MIPS-BCM63XX-add-USB-device-clock-enable-delay-to-cl.patch",
    "content": "From 8e9bf528a122741f0171b89c297b63041116d704 Mon Sep 17 00:00:00 2001\nFrom: Florian Fainelli <florian@openwrt.org>\nDate: Mon, 28 Jan 2013 20:06:20 +0100\nSubject: [PATCH 02/11] MIPS: BCM63XX: add USB device clock enable delay to\n clock code\n\nThis patch adds the required 10 micro seconds delay to the USB device\nclock enable operation. Put this where the correct clock knowledege is,\nwhich is in the clock code, and remove this delay from the bcm63xx_udc\ngadget driver where it was before.\n\nSigned-off-by: Florian Fainelli <florian@openwrt.org>\n---\n arch/mips/bcm63xx/clk.c          |    5 +++++\n drivers/usb/gadget/bcm63xx_udc.c |    1 -\n 2 files changed, 5 insertions(+), 1 deletion(-)\n\n--- a/arch/mips/bcm63xx/clk.c\n+++ b/arch/mips/bcm63xx/clk.c\n@@ -236,6 +236,11 @@ static void usbd_set(struct clk *clk, in\n \t\tbcm_hwclock_set(CKCTL_6362_USBD_EN, enable);\n \telse if (BCMCPU_IS_6368())\n \t\tbcm_hwclock_set(CKCTL_6368_USBD_EN, enable);\n+\telse\n+\t\treturn;\n+\n+\tif (enable)\n+\t\tudelay(10);\n }\n \n static struct clk clk_usbd = {\n--- a/drivers/usb/gadget/udc/bcm63xx_udc.c\n+++ b/drivers/usb/gadget/udc/bcm63xx_udc.c\n@@ -403,7 +403,6 @@ static inline void set_clocks(struct bcm\n \tif (is_enabled) {\n \t\tclk_enable(udc->usbh_clk);\n \t\tclk_enable(udc->usbd_clk);\n-\t\tudelay(10);\n \t} else {\n \t\tclk_disable(udc->usbd_clk);\n \t\tclk_disable(udc->usbh_clk);\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/102-MIPS-BCM63XX-move-code-touching-the-USB-private-regi.patch",
    "content": "From ac9b0b574d54be28b300bf99ffe092a2c589484f Mon Sep 17 00:00:00 2001\nFrom: Florian Fainelli <florian@openwrt.org>\nDate: Mon, 28 Jan 2013 20:06:21 +0100\nSubject: [PATCH 03/11] MIPS: BCM63XX: move code touching the USB private\n register\n\nThis patch moves the code touching the USB private register in the\nbcm63xx USB gadget driver to arch/mips/bcm63xx/usb-common.c in\npreparation for adding support for OHCI and EHCI host controllers which\nwill also touch the USB private register.\n\nSigned-off-by: Florian Fainelli <florian@openwrt.org>\n---\n arch/mips/bcm63xx/Makefile                         |    2 +-\n arch/mips/bcm63xx/usb-common.c                     |   53 ++++++++++++++++++++\n .../include/asm/mach-bcm63xx/bcm63xx_usb_priv.h    |    9 ++++\n drivers/usb/gadget/bcm63xx_udc.c                   |   27 ++--------\n 4 files changed, 67 insertions(+), 24 deletions(-)\n create mode 100644 arch/mips/bcm63xx/usb-common.c\n create mode 100644 arch/mips/include/asm/mach-bcm63xx/bcm63xx_usb_priv.h\n\n--- a/arch/mips/bcm63xx/Makefile\n+++ b/arch/mips/bcm63xx/Makefile\n@@ -2,7 +2,7 @@\n obj-y\t\t+= clk.o cpu.o cs.o gpio.o irq.o nvram.o prom.o reset.o \\\n \t\t   setup.o timer.o dev-enet.o dev-flash.o dev-pcmcia.o \\\n \t\t   dev-rng.o dev-spi.o dev-hsspi.o dev-uart.o dev-wdt.o \\\n-\t\t   dev-usb-usbd.o\n+\t\t   dev-usb-usbd.o usb-common.o\n obj-$(CONFIG_EARLY_PRINTK)\t+= early_printk.o\n \n obj-y\t\t+= boards/\n--- /dev/null\n+++ b/arch/mips/bcm63xx/usb-common.c\n@@ -0,0 +1,53 @@\n+/*\n+ * Broadcom BCM63xx common USB device configuration code\n+ *\n+ * This file is subject to the terms and conditions of the GNU General Public\n+ * License.  See the file \"COPYING\" in the main directory of this archive\n+ * for more details.\n+ *\n+ * Copyright (C) 2012 Kevin Cernekee <cernekee@gmail.com>\n+ * Copyright (C) 2012 Broadcom Corporation\n+ *\n+ */\n+#include <linux/export.h>\n+\n+#include <bcm63xx_cpu.h>\n+#include <bcm63xx_regs.h>\n+#include <bcm63xx_io.h>\n+#include <bcm63xx_usb_priv.h>\n+\n+void bcm63xx_usb_priv_select_phy_mode(u32 portmask, bool is_device)\n+{\n+\tu32 val;\n+\n+\tval = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_UTMI_CTL_6368_REG);\n+\tif (is_device) {\n+\t\tval |= (portmask << USBH_PRIV_UTMI_CTL_HOSTB_SHIFT);\n+\t\tval |= (portmask << USBH_PRIV_UTMI_CTL_NODRIV_SHIFT);\n+\t} else {\n+\t\tval &= ~(portmask << USBH_PRIV_UTMI_CTL_HOSTB_SHIFT);\n+\t\tval &= ~(portmask << USBH_PRIV_UTMI_CTL_NODRIV_SHIFT);\n+\t}\n+\tbcm_rset_writel(RSET_USBH_PRIV, val, USBH_PRIV_UTMI_CTL_6368_REG);\n+\n+\tval = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SWAP_6368_REG);\n+\tif (is_device)\n+\t\tval |= USBH_PRIV_SWAP_USBD_MASK;\n+\telse\n+\t\tval &= ~USBH_PRIV_SWAP_USBD_MASK;\n+\tbcm_rset_writel(RSET_USBH_PRIV, val, USBH_PRIV_SWAP_6368_REG);\n+}\n+EXPORT_SYMBOL(bcm63xx_usb_priv_select_phy_mode);\n+\n+void bcm63xx_usb_priv_select_pullup(u32 portmask, bool is_on)\n+{\n+\tu32 val;\n+\n+\tval = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_UTMI_CTL_6368_REG);\n+\tif (is_on)\n+\t\tval &= ~(portmask << USBH_PRIV_UTMI_CTL_NODRIV_SHIFT);\n+\telse\n+\t\tval |= (portmask << USBH_PRIV_UTMI_CTL_NODRIV_SHIFT);\n+\tbcm_rset_writel(RSET_USBH_PRIV, val, USBH_PRIV_UTMI_CTL_6368_REG);\n+}\n+EXPORT_SYMBOL(bcm63xx_usb_priv_select_pullup);\n--- /dev/null\n+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_usb_priv.h\n@@ -0,0 +1,9 @@\n+#ifndef BCM63XX_USB_PRIV_H_\n+#define BCM63XX_USB_PRIV_H_\n+\n+#include <linux/types.h>\n+\n+void bcm63xx_usb_priv_select_phy_mode(u32 portmask, bool is_device);\n+void bcm63xx_usb_priv_select_pullup(u32 portmask, bool is_on);\n+\n+#endif /* BCM63XX_USB_PRIV_H_ */\n--- a/drivers/usb/gadget/udc/bcm63xx_udc.c\n+++ b/drivers/usb/gadget/udc/bcm63xx_udc.c\n@@ -36,6 +36,7 @@\n #include <bcm63xx_dev_usb_usbd.h>\n #include <bcm63xx_io.h>\n #include <bcm63xx_regs.h>\n+#include <bcm63xx_usb_priv.h>\n \n #define DRV_MODULE_NAME\t\t\"bcm63xx_udc\"\n \n@@ -880,22 +881,7 @@ static void bcm63xx_select_phy_mode(stru\n \t\tbcm_gpio_writel(val, GPIO_PINMUX_OTHR_REG);\n \t}\n \n-\tval = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_UTMI_CTL_6368_REG);\n-\tif (is_device) {\n-\t\tval |= (portmask << USBH_PRIV_UTMI_CTL_HOSTB_SHIFT);\n-\t\tval |= (portmask << USBH_PRIV_UTMI_CTL_NODRIV_SHIFT);\n-\t} else {\n-\t\tval &= ~(portmask << USBH_PRIV_UTMI_CTL_HOSTB_SHIFT);\n-\t\tval &= ~(portmask << USBH_PRIV_UTMI_CTL_NODRIV_SHIFT);\n-\t}\n-\tbcm_rset_writel(RSET_USBH_PRIV, val, USBH_PRIV_UTMI_CTL_6368_REG);\n-\n-\tval = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SWAP_6368_REG);\n-\tif (is_device)\n-\t\tval |= USBH_PRIV_SWAP_USBD_MASK;\n-\telse\n-\t\tval &= ~USBH_PRIV_SWAP_USBD_MASK;\n-\tbcm_rset_writel(RSET_USBH_PRIV, val, USBH_PRIV_SWAP_6368_REG);\n+\tbcm63xx_usb_priv_select_phy_mode(portmask, is_device);\n }\n \n /**\n@@ -909,14 +895,9 @@ static void bcm63xx_select_phy_mode(stru\n  */\n static void bcm63xx_select_pullup(struct bcm63xx_udc *udc, bool is_on)\n {\n-\tu32 val, portmask = BIT(udc->pd->port_no);\n+\tu32 portmask = BIT(udc->pd->port_no);\n \n-\tval = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_UTMI_CTL_6368_REG);\n-\tif (is_on)\n-\t\tval &= ~(portmask << USBH_PRIV_UTMI_CTL_NODRIV_SHIFT);\n-\telse\n-\t\tval |= (portmask << USBH_PRIV_UTMI_CTL_NODRIV_SHIFT);\n-\tbcm_rset_writel(RSET_USBH_PRIV, val, USBH_PRIV_UTMI_CTL_6368_REG);\n+\tbcm63xx_usb_priv_select_pullup(portmask, is_on);\n }\n \n /**\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/103-MIPS-BCM63XX-add-OHCI-EHCI-configuration-bits-to-com.patch",
    "content": "From 28758a9da77954ed323f86123ef448c6a563c037 Mon Sep 17 00:00:00 2001\nFrom: Florian Fainelli <florian@openwrt.org>\nDate: Mon, 28 Jan 2013 20:06:22 +0100\nSubject: [PATCH 04/11] MIPS: BCM63XX: add OHCI/EHCI configuration bits to\n common USB code\n\nThis patch updates the common USB code touching the USB private\nregisters with the specific bits to properly enable OHCI and EHCI\ncontrollers on BCM63xx SoCs. As a result we now need to protect access\nto Read Modify Write sequences using a spinlock because we cannot\nguarantee that any of the exposed helper will not be called\nconcurrently.\n\nSigned-off-by: Maxime Bizon <mbizon@freebox.fr>\nSigned-off-by: Florian Fainelli <florian@openwrt.org>\n---\n arch/mips/bcm63xx/usb-common.c                     |   97 ++++++++++++++++++++\n .../include/asm/mach-bcm63xx/bcm63xx_usb_priv.h    |    2 +\n 2 files changed, 99 insertions(+)\n\n--- a/arch/mips/bcm63xx/usb-common.c\n+++ b/arch/mips/bcm63xx/usb-common.c\n@@ -5,10 +5,12 @@\n  * License.  See the file \"COPYING\" in the main directory of this archive\n  * for more details.\n  *\n+ * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>\n  * Copyright (C) 2012 Kevin Cernekee <cernekee@gmail.com>\n  * Copyright (C) 2012 Broadcom Corporation\n  *\n  */\n+#include <linux/spinlock.h>\n #include <linux/export.h>\n \n #include <bcm63xx_cpu.h>\n@@ -16,9 +18,14 @@\n #include <bcm63xx_io.h>\n #include <bcm63xx_usb_priv.h>\n \n+static DEFINE_SPINLOCK(usb_priv_reg_lock);\n+\n void bcm63xx_usb_priv_select_phy_mode(u32 portmask, bool is_device)\n {\n \tu32 val;\n+\tunsigned long flags;\n+\n+\tspin_lock_irqsave(&usb_priv_reg_lock, flags);\n \n \tval = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_UTMI_CTL_6368_REG);\n \tif (is_device) {\n@@ -36,12 +43,17 @@ void bcm63xx_usb_priv_select_phy_mode(u3\n \telse\n \t\tval &= ~USBH_PRIV_SWAP_USBD_MASK;\n \tbcm_rset_writel(RSET_USBH_PRIV, val, USBH_PRIV_SWAP_6368_REG);\n+\n+\tspin_unlock_irqrestore(&usb_priv_reg_lock, flags);\n }\n EXPORT_SYMBOL(bcm63xx_usb_priv_select_phy_mode);\n \n void bcm63xx_usb_priv_select_pullup(u32 portmask, bool is_on)\n {\n \tu32 val;\n+\tunsigned long flags;\n+\n+\tspin_lock_irqsave(&usb_priv_reg_lock, flags);\n \n \tval = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_UTMI_CTL_6368_REG);\n \tif (is_on)\n@@ -49,5 +61,90 @@ void bcm63xx_usb_priv_select_pullup(u32\n \telse\n \t\tval |= (portmask << USBH_PRIV_UTMI_CTL_NODRIV_SHIFT);\n \tbcm_rset_writel(RSET_USBH_PRIV, val, USBH_PRIV_UTMI_CTL_6368_REG);\n+\n+\tspin_unlock_irqrestore(&usb_priv_reg_lock, flags);\n }\n EXPORT_SYMBOL(bcm63xx_usb_priv_select_pullup);\n+\n+/* The following array represents the meaning of the DESC/DATA\n+ * endian swapping with respect to the CPU configured endianness\n+ *\n+ * DATA\tENDN\tmmio\tdescriptor\n+ * 0\t0\tBE\tinvalid\n+ * 0\t1\tBE\tLE\n+ * 1\t0\tBE\tBE\n+ * 1\t1\tBE\tinvalid\n+ *\n+ * Since BCM63XX SoCs are configured to be in big-endian mode\n+ * we want configuration at line 3.\n+ */\n+void bcm63xx_usb_priv_ohci_cfg_set(void)\n+{\n+\tu32 reg;\n+\tunsigned long flags;\n+\n+\tspin_lock_irqsave(&usb_priv_reg_lock, flags);\n+\n+\tif (BCMCPU_IS_6348())\n+\t\tbcm_rset_writel(RSET_OHCI_PRIV, 0, OHCI_PRIV_REG);\n+\telse if (BCMCPU_IS_6358()) {\n+\t\treg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SWAP_6358_REG);\n+\t\treg &= ~USBH_PRIV_SWAP_OHCI_ENDN_MASK;\n+\t\treg |= USBH_PRIV_SWAP_OHCI_DATA_MASK;\n+\t\tbcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SWAP_6358_REG);\n+\t\t/*\n+\t\t * The magic value comes for the original vendor BSP\n+\t\t * and is needed for USB to work. Datasheet does not\n+\t\t * help, so the magic value is used as-is.\n+\t\t */\n+\t\tbcm_rset_writel(RSET_USBH_PRIV, 0x1c0020,\n+\t\t\t\tUSBH_PRIV_TEST_6358_REG);\n+\n+\t} else if (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_6368()) {\n+\t\treg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SWAP_6368_REG);\n+\t\treg &= ~USBH_PRIV_SWAP_OHCI_ENDN_MASK;\n+\t\treg |= USBH_PRIV_SWAP_OHCI_DATA_MASK;\n+\t\tbcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SWAP_6368_REG);\n+\n+\t\treg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SETUP_6368_REG);\n+\t\treg |= USBH_PRIV_SETUP_IOC_MASK;\n+\t\tbcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SETUP_6368_REG);\n+\t}\n+\n+\tspin_unlock_irqrestore(&usb_priv_reg_lock, flags);\n+}\n+\n+void bcm63xx_usb_priv_ehci_cfg_set(void)\n+{\n+\tu32 reg;\n+\tunsigned long flags;\n+\n+\tspin_lock_irqsave(&usb_priv_reg_lock, flags);\n+\n+\tif (BCMCPU_IS_6358()) {\n+\t\treg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SWAP_6358_REG);\n+\t\treg &= ~USBH_PRIV_SWAP_EHCI_ENDN_MASK;\n+\t\treg |= USBH_PRIV_SWAP_EHCI_DATA_MASK;\n+\t\tbcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SWAP_6358_REG);\n+\n+\t\t/*\n+\t\t * The magic value comes for the original vendor BSP\n+\t\t * and is needed for USB to work. Datasheet does not\n+\t\t * help, so the magic value is used as-is.\n+\t\t */\n+\t\tbcm_rset_writel(RSET_USBH_PRIV, 0x1c0020,\n+\t\t\t\tUSBH_PRIV_TEST_6358_REG);\n+\n+\t} else if (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_6368()) {\n+\t\treg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SWAP_6368_REG);\n+\t\treg &= ~USBH_PRIV_SWAP_EHCI_ENDN_MASK;\n+\t\treg |= USBH_PRIV_SWAP_EHCI_DATA_MASK;\n+\t\tbcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SWAP_6368_REG);\n+\n+\t\treg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SETUP_6368_REG);\n+\t\treg |= USBH_PRIV_SETUP_IOC_MASK;\n+\t\tbcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SETUP_6368_REG);\n+\t}\n+\n+\tspin_unlock_irqrestore(&usb_priv_reg_lock, flags);\n+}\n--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_usb_priv.h\n+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_usb_priv.h\n@@ -5,5 +5,7 @@\n \n void bcm63xx_usb_priv_select_phy_mode(u32 portmask, bool is_device);\n void bcm63xx_usb_priv_select_pullup(u32 portmask, bool is_on);\n+void bcm63xx_usb_priv_ohci_cfg_set(void);\n+void bcm63xx_usb_priv_ehci_cfg_set(void);\n \n #endif /* BCM63XX_USB_PRIV_H_ */\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/104-MIPS-BCM63XX-introduce-BCM63XX_OHCI-configuration-sy.patch",
    "content": "From 94ec618bd1a6b07fafbbfc9bcc54e7f9360ff9a0 Mon Sep 17 00:00:00 2001\nFrom: Florian Fainelli <florian@openwrt.org>\nDate: Mon, 28 Jan 2013 20:06:23 +0100\nSubject: [PATCH 05/11] MIPS: BCM63XX: introduce BCM63XX_OHCI configuration\n symbol\n\nThis configuration symbol can be used by CPUs supporting the on-chip\nOHCI controller, and ensures that all relevant OHCI-related\nconfiguration options are correctly selected. So far, OHCI support is\navailable for the 6328, 6348, 6358 and 6358 SoCs.\n\nSigned-off-by: Florian Fainelli <florian@openwrt.org>\n---\n arch/mips/bcm63xx/Kconfig |   15 ++++++++++-----\n 1 file changed, 10 insertions(+), 5 deletions(-)\n\n--- a/arch/mips/bcm63xx/Kconfig\n+++ b/arch/mips/bcm63xx/Kconfig\n@@ -7,10 +7,17 @@ config BCM63XX_CPU_3368\n \tselect SYS_HAS_CPU_BMIPS4350\n \tselect HAVE_PCI\n \n+config BCM63XX_OHCI\n+\tbool\n+\tselect USB_ARCH_HAS_OHCI\n+\tselect USB_OHCI_BIG_ENDIAN_DESC if USB_OHCI_HCD\n+\tselect USB_OHCI_BIG_ENDIAN_MMIO if USB_OHCI_HCD\n+\n config BCM63XX_CPU_6328\n \tbool \"support 6328 CPU\"\n \tselect SYS_HAS_CPU_BMIPS4350\n \tselect HAVE_PCI\n+\tselect BCM63XX_OHCI\n \n config BCM63XX_CPU_6338\n \tbool \"support 6338 CPU\"\n@@ -25,21 +32,25 @@ config BCM63XX_CPU_6348\n \tbool \"support 6348 CPU\"\n \tselect SYS_HAS_CPU_BMIPS32_3300\n \tselect HAVE_PCI\n+\tselect BCM63XX_OHCI\n \n config BCM63XX_CPU_6358\n \tbool \"support 6358 CPU\"\n \tselect SYS_HAS_CPU_BMIPS4350\n \tselect HAVE_PCI\n+\tselect BCM63XX_OHCI\n \n config BCM63XX_CPU_6362\n \tbool \"support 6362 CPU\"\n \tselect SYS_HAS_CPU_BMIPS4350\n \tselect HAVE_PCI\n+\tselect BCM63XX_OHCI\n \n config BCM63XX_CPU_6368\n \tbool \"support 6368 CPU\"\n \tselect SYS_HAS_CPU_BMIPS4350\n \tselect HAVE_PCI\n+\tselect BCM63XX_OHCI\n endmenu\n \n source \"arch/mips/bcm63xx/boards/Kconfig\"\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/105-MIPS-BCM63XX-add-support-for-the-on-chip-OHCI-contro.patch",
    "content": "From 30d22baef255c99a12c4858ce4ab0d45f0d8c9ae Mon Sep 17 00:00:00 2001\nFrom: Florian Fainelli <florian@openwrt.org>\nDate: Mon, 28 Jan 2013 20:06:24 +0100\nSubject: [PATCH 06/11] MIPS: BCM63XX: add support for the on-chip OHCI\n controller\n\nBroadcom BCM63XX SoCs include an on-chip OHCI controller which can be\ndriven by the ohci-platform generic driver by using specific power\non/off/suspend callback to manage clocks and hardware specific\nconfiguration.\n\nSigned-off-by: Maxime Bizon <mbizon@freebox.fr>\nSigned-off-by: Florian Fainelli <florian@openwrt.org>\n---\n arch/mips/bcm63xx/Makefile                         |    2 +-\n arch/mips/bcm63xx/dev-usb-ohci.c                   |   94 ++++++++++++++++++++\n .../asm/mach-bcm63xx/bcm63xx_dev_usb_ohci.h        |    6 ++\n 3 files changed, 101 insertions(+), 1 deletion(-)\n create mode 100644 arch/mips/bcm63xx/dev-usb-ohci.c\n create mode 100644 arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_usb_ohci.h\n\n--- a/arch/mips/bcm63xx/Makefile\n+++ b/arch/mips/bcm63xx/Makefile\n@@ -2,7 +2,7 @@\n obj-y\t\t+= clk.o cpu.o cs.o gpio.o irq.o nvram.o prom.o reset.o \\\n \t\t   setup.o timer.o dev-enet.o dev-flash.o dev-pcmcia.o \\\n \t\t   dev-rng.o dev-spi.o dev-hsspi.o dev-uart.o dev-wdt.o \\\n-\t\t   dev-usb-usbd.o usb-common.o\n+\t\t   dev-usb-ohci.o dev-usb-usbd.o usb-common.o\n obj-$(CONFIG_EARLY_PRINTK)\t+= early_printk.o\n \n obj-y\t\t+= boards/\n--- /dev/null\n+++ b/arch/mips/bcm63xx/dev-usb-ohci.c\n@@ -0,0 +1,94 @@\n+/*\n+ * This file is subject to the terms and conditions of the GNU General Public\n+ * License.  See the file \"COPYING\" in the main directory of this archive\n+ * for more details.\n+ *\n+ * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>\n+ * Copyright (C) 2013 Florian Fainelli <florian@openwrt.org>\n+ */\n+\n+#include <linux/init.h>\n+#include <linux/kernel.h>\n+#include <linux/platform_device.h>\n+#include <linux/usb/ohci_pdriver.h>\n+#include <linux/dma-mapping.h>\n+#include <linux/clk.h>\n+#include <linux/delay.h>\n+\n+#include <bcm63xx_cpu.h>\n+#include <bcm63xx_regs.h>\n+#include <bcm63xx_io.h>\n+#include <bcm63xx_usb_priv.h>\n+#include <bcm63xx_dev_usb_ohci.h>\n+\n+static struct resource ohci_resources[] = {\n+\t{\n+\t\t.start\t\t= -1, /* filled at runtime */\n+\t\t.end\t\t= -1, /* filled at runtime */\n+\t\t.flags\t\t= IORESOURCE_MEM,\n+\t},\n+\t{\n+\t\t.start\t\t= -1, /* filled at runtime */\n+\t\t.flags\t\t= IORESOURCE_IRQ,\n+\t},\n+};\n+\n+static u64 ohci_dmamask = DMA_BIT_MASK(32);\n+\n+static struct clk *usb_host_clock;\n+\n+static int bcm63xx_ohci_power_on(struct platform_device *pdev)\n+{\n+\tusb_host_clock = clk_get(&pdev->dev, \"usbh\");\n+\tif (IS_ERR_OR_NULL(usb_host_clock))\n+\t\treturn -ENODEV;\n+\n+\tclk_prepare_enable(usb_host_clock);\n+\n+\tbcm63xx_usb_priv_ohci_cfg_set();\n+\n+\treturn 0;\n+}\n+\n+static void bcm63xx_ohci_power_off(struct platform_device *pdev)\n+{\n+\tif (!IS_ERR_OR_NULL(usb_host_clock)) {\n+\t\tclk_disable_unprepare(usb_host_clock);\n+\t\tclk_put(usb_host_clock);\n+\t}\n+}\n+\n+static struct usb_ohci_pdata bcm63xx_ohci_pdata = {\n+\t.big_endian_desc\t= 1,\n+\t.big_endian_mmio\t= 1,\n+\t.no_big_frame_no\t= 1,\n+\t.num_ports\t\t= 1,\n+\t.power_on\t\t= bcm63xx_ohci_power_on,\n+\t.power_off\t\t= bcm63xx_ohci_power_off,\n+\t.power_suspend\t\t= bcm63xx_ohci_power_off,\n+};\n+\n+static struct platform_device bcm63xx_ohci_device = {\n+\t.name\t\t= \"ohci-platform\",\n+\t.id\t\t= -1,\n+\t.num_resources\t= ARRAY_SIZE(ohci_resources),\n+\t.resource\t= ohci_resources,\n+\t.dev\t\t= {\n+\t\t.platform_data\t\t= &bcm63xx_ohci_pdata,\n+\t\t.dma_mask\t\t= &ohci_dmamask,\n+\t\t.coherent_dma_mask\t= DMA_BIT_MASK(32),\n+\t},\n+};\n+\n+int __init bcm63xx_ohci_register(void)\n+{\n+\tif (BCMCPU_IS_6345() || BCMCPU_IS_6338())\n+\t\treturn -ENODEV;\n+\n+\tohci_resources[0].start = bcm63xx_regset_address(RSET_OHCI0);\n+\tohci_resources[0].end = ohci_resources[0].start;\n+\tohci_resources[0].end += RSET_OHCI_SIZE - 1;\n+\tohci_resources[1].start = bcm63xx_get_irq_number(IRQ_OHCI0);\n+\n+\treturn platform_device_register(&bcm63xx_ohci_device);\n+}\n--- /dev/null\n+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_usb_ohci.h\n@@ -0,0 +1,6 @@\n+#ifndef BCM63XX_DEV_USB_OHCI_H_\n+#define BCM63XX_DEV_USB_OHCI_H_\n+\n+int bcm63xx_ohci_register(void);\n+\n+#endif /* BCM63XX_DEV_USB_OHCI_H_ */\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/106-MIPS-BCM63XX-register-OHCI-controller-if-board-enabl.patch",
    "content": "From 33ef960aed15f9a98a2c51d8d794cd72418e0be4 Mon Sep 17 00:00:00 2001\nFrom: Florian Fainelli <florian@openwrt.org>\nDate: Mon, 28 Jan 2013 20:06:25 +0100\nSubject: [PATCH 07/11] MIPS: BCM63XX: register OHCI controller if board\n enables it\n\nBCM63XX-based boards can control the registration of the OHCI controller\nby setting their has_ohci0 flag to 1. Handle this in the generic\ncode dealing with board registration and call the actual helper to\nregister the OHCI controller.\n\nSigned-off-by: Florian Fainelli <florian@openwrt.org>\n---\n arch/mips/bcm63xx/boards/board_bcm963xx.c |    4 ++++\n 1 file changed, 4 insertions(+)\n\n--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c\n+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c\n@@ -24,6 +24,7 @@\n #include <bcm63xx_dev_hsspi.h>\n #include <bcm63xx_dev_pcmcia.h>\n #include <bcm63xx_dev_spi.h>\n+#include <bcm63xx_dev_usb_ohci.h>\n #include <bcm63xx_dev_usb_usbd.h>\n #include <board_bcm963xx.h>\n \n@@ -879,6 +880,9 @@ int __init board_register_devices(void)\n \tif (board.has_usbd)\n \t\tbcm63xx_usbd_register(&board.usbd);\n \n+\tif (board.has_ohci0)\n+\t\tbcm63xx_ohci_register();\n+\n \t/* Generate MAC address for WLAN and register our SPROM,\n \t * do this after registering enet devices\n \t */\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/107-MIPS-BCM63XX-introduce-BCM63XX_EHCI-configuration-sy.patch",
    "content": "From 00da1683364e58c6430a4577123d01037f8faddc Mon Sep 17 00:00:00 2001\nFrom: Florian Fainelli <florian@openwrt.org>\nDate: Mon, 28 Jan 2013 20:06:26 +0100\nSubject: [PATCH 08/11] MIPS: BCM63XX: introduce BCM63XX_EHCI configuration\n symbol\n\nThis configuration symbol can be used by CPUs supporting the on-chip\nEHCI controller, and ensures that all relevant EHCI-related\nconfiguration options are selected. So far BCM6328, BCM6358 and BCM6368\nhave an EHCI controller and do select this symbol. Update\ndrivers/usb/host/Kconfig with BCM63XX to update direct unmet\ndependencies.\n\nSigned-off-by: Florian Fainelli <florian@openwrt.org>\n---\n arch/mips/bcm63xx/Kconfig |    9 +++++++++\n drivers/usb/host/Kconfig  |    5 +++--\n 2 files changed, 12 insertions(+), 2 deletions(-)\n\n--- a/arch/mips/bcm63xx/Kconfig\n+++ b/arch/mips/bcm63xx/Kconfig\n@@ -13,11 +13,18 @@ config BCM63XX_OHCI\n \tselect USB_OHCI_BIG_ENDIAN_DESC if USB_OHCI_HCD\n \tselect USB_OHCI_BIG_ENDIAN_MMIO if USB_OHCI_HCD\n \n+config BCM63XX_EHCI\n+\tbool\n+\tselect USB_ARCH_HAS_EHCI\n+\tselect USB_EHCI_BIG_ENDIAN_DESC if USB_EHCI_HCD\n+\tselect USB_EHCI_BIG_ENDIAN_MMIO if USB_EHCI_HCD\n+\n config BCM63XX_CPU_6328\n \tbool \"support 6328 CPU\"\n \tselect SYS_HAS_CPU_BMIPS4350\n \tselect HAVE_PCI\n \tselect BCM63XX_OHCI\n+\tselect BCM63XX_EHCI\n \n config BCM63XX_CPU_6338\n \tbool \"support 6338 CPU\"\n@@ -39,18 +46,21 @@ config BCM63XX_CPU_6358\n \tselect SYS_HAS_CPU_BMIPS4350\n \tselect HAVE_PCI\n \tselect BCM63XX_OHCI\n+\tselect BCM63XX_EHCI\n \n config BCM63XX_CPU_6362\n \tbool \"support 6362 CPU\"\n \tselect SYS_HAS_CPU_BMIPS4350\n \tselect HAVE_PCI\n \tselect BCM63XX_OHCI\n+\tselect BCM63XX_EHCI\n \n config BCM63XX_CPU_6368\n \tbool \"support 6368 CPU\"\n \tselect SYS_HAS_CPU_BMIPS4350\n \tselect HAVE_PCI\n \tselect BCM63XX_OHCI\n+\tselect BCM63XX_EHCI\n endmenu\n \n source \"arch/mips/bcm63xx/boards/Kconfig\"\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/108-MIPS-BCM63XX-add-support-for-the-on-chip-EHCI-contro.patch",
    "content": "From e38f13bd6408769c0b565bb1079024f496eee121 Mon Sep 17 00:00:00 2001\nFrom: Florian Fainelli <florian@openwrt.org>\nDate: Mon, 28 Jan 2013 20:06:27 +0100\nSubject: [PATCH 09/11] MIPS: BCM63XX: add support for the on-chip EHCI\n controller\n\nBroadcom BCM63XX SoCs include an on-chip EHCI controller which can be\ndriven by the generic ehci-platform driver by using specific power\non/off/suspend callbacks to manage clocks and hardware specific\nconfiguration.\n\nSigned-off-by: Maxime Bizon <mbizon@freebox.fr>\nSigned-off-by: Florian Fainelli <florian@openwrt.org>\n---\n arch/mips/bcm63xx/Makefile                         |    2 +-\n arch/mips/bcm63xx/dev-usb-ehci.c                   |   92 ++++++++++++++++++++\n .../asm/mach-bcm63xx/bcm63xx_dev_usb_ehci.h        |    6 ++\n 3 files changed, 99 insertions(+), 1 deletion(-)\n create mode 100644 arch/mips/bcm63xx/dev-usb-ehci.c\n create mode 100644 arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_usb_ehci.h\n\n--- a/arch/mips/bcm63xx/Makefile\n+++ b/arch/mips/bcm63xx/Makefile\n@@ -2,7 +2,7 @@\n obj-y\t\t+= clk.o cpu.o cs.o gpio.o irq.o nvram.o prom.o reset.o \\\n \t\t   setup.o timer.o dev-enet.o dev-flash.o dev-pcmcia.o \\\n \t\t   dev-rng.o dev-spi.o dev-hsspi.o dev-uart.o dev-wdt.o \\\n-\t\t   dev-usb-ohci.o dev-usb-usbd.o usb-common.o\n+\t\t   dev-usb-ehci.o dev-usb-ohci.o dev-usb-usbd.o usb-common.o\n obj-$(CONFIG_EARLY_PRINTK)\t+= early_printk.o\n \n obj-y\t\t+= boards/\n--- /dev/null\n+++ b/arch/mips/bcm63xx/dev-usb-ehci.c\n@@ -0,0 +1,92 @@\n+/*\n+ * This file is subject to the terms and conditions of the GNU General Public\n+ * License.  See the file \"COPYING\" in the main directory of this archive\n+ * for more details.\n+ *\n+ * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>\n+ * Copyright (C) 2013 Florian Fainelli <florian@openwrt.org>\n+ */\n+\n+#include <linux/init.h>\n+#include <linux/kernel.h>\n+#include <linux/platform_device.h>\n+#include <linux/clk.h>\n+#include <linux/delay.h>\n+#include <linux/usb/ehci_pdriver.h>\n+#include <linux/dma-mapping.h>\n+\n+#include <bcm63xx_cpu.h>\n+#include <bcm63xx_regs.h>\n+#include <bcm63xx_io.h>\n+#include <bcm63xx_usb_priv.h>\n+#include <bcm63xx_dev_usb_ehci.h>\n+\n+static struct resource ehci_resources[] = {\n+\t{\n+\t\t.start\t\t= -1, /* filled at runtime */\n+\t\t.end\t\t= -1, /* filled at runtime */\n+\t\t.flags\t\t= IORESOURCE_MEM,\n+\t},\n+\t{\n+\t\t.start\t\t= -1, /* filled at runtime */\n+\t\t.flags\t\t= IORESOURCE_IRQ,\n+\t},\n+};\n+\n+static u64 ehci_dmamask = DMA_BIT_MASK(32);\n+\n+static struct clk *usb_host_clock;\n+\n+static int bcm63xx_ehci_power_on(struct platform_device *pdev)\n+{\n+\tusb_host_clock = clk_get(&pdev->dev, \"usbh\");\n+\tif (IS_ERR_OR_NULL(usb_host_clock))\n+\t\treturn -ENODEV;\n+\n+\tclk_prepare_enable(usb_host_clock);\n+\n+\tbcm63xx_usb_priv_ehci_cfg_set();\n+\n+\treturn 0;\n+}\n+\n+static void bcm63xx_ehci_power_off(struct platform_device *pdev)\n+{\n+\tif (!IS_ERR_OR_NULL(usb_host_clock)) {\n+\t\tclk_disable_unprepare(usb_host_clock);\n+\t\tclk_put(usb_host_clock);\n+\t}\n+}\n+\n+static struct usb_ehci_pdata bcm63xx_ehci_pdata = {\n+\t.big_endian_desc\t= 1,\n+\t.big_endian_mmio\t= 1,\n+\t.power_on\t\t= bcm63xx_ehci_power_on,\n+\t.power_off\t\t= bcm63xx_ehci_power_off,\n+\t.power_suspend\t\t= bcm63xx_ehci_power_off,\n+};\n+\n+static struct platform_device bcm63xx_ehci_device = {\n+\t.name\t\t= \"ehci-platform\",\n+\t.id\t\t= -1,\n+\t.num_resources\t= ARRAY_SIZE(ehci_resources),\n+\t.resource\t= ehci_resources,\n+\t.dev\t\t= {\n+\t\t.platform_data\t\t= &bcm63xx_ehci_pdata,\n+\t\t.dma_mask\t\t= &ehci_dmamask,\n+\t\t.coherent_dma_mask\t= DMA_BIT_MASK(32),\n+\t},\n+};\n+\n+int __init bcm63xx_ehci_register(void)\n+{\n+\tif (!BCMCPU_IS_6328() && !BCMCPU_IS_6358() && !BCMCPU_IS_6362() && !BCMCPU_IS_6368())\n+\t\treturn 0;\n+\n+\tehci_resources[0].start = bcm63xx_regset_address(RSET_EHCI0);\n+\tehci_resources[0].end = ehci_resources[0].start;\n+\tehci_resources[0].end += RSET_EHCI_SIZE - 1;\n+\tehci_resources[1].start = bcm63xx_get_irq_number(IRQ_EHCI0);\n+\n+\treturn platform_device_register(&bcm63xx_ehci_device);\n+}\n--- /dev/null\n+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_usb_ehci.h\n@@ -0,0 +1,6 @@\n+#ifndef BCM63XX_DEV_USB_EHCI_H_\n+#define BCM63XX_DEV_USB_EHCI_H_\n+\n+int bcm63xx_ehci_register(void);\n+\n+#endif /* BCM63XX_DEV_USB_EHCI_H_ */\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/109-MIPS-BCM63XX-register-EHCI-controller-if-board-enabl.patch",
    "content": "From 709ef2034f5ba06da35f89856ad7baf2b7a41287 Mon Sep 17 00:00:00 2001\nFrom: Florian Fainelli <florian@openwrt.org>\nDate: Mon, 28 Jan 2013 20:06:28 +0100\nSubject: [PATCH 10/11] MIPS: BCM63XX: register EHCI controller if board\n enables it\n\nBCM63XX-based board can control the registration of the EHCI controller\nby setting their has_ehci0 flag to 1. Handle this in the generic\ncode dealing with board registration and call the actual helper to register\nthe EHCI controller.\n\nSigned-off-by: Florian Fainelli <florian@openwrt.org>\n---\n arch/mips/bcm63xx/boards/board_bcm963xx.c |    4 ++++\n 1 file changed, 4 insertions(+)\n\n--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c\n+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c\n@@ -24,6 +24,7 @@\n #include <bcm63xx_dev_hsspi.h>\n #include <bcm63xx_dev_pcmcia.h>\n #include <bcm63xx_dev_spi.h>\n+#include <bcm63xx_dev_usb_ehci.h>\n #include <bcm63xx_dev_usb_ohci.h>\n #include <bcm63xx_dev_usb_usbd.h>\n #include <board_bcm963xx.h>\n@@ -880,6 +881,9 @@ int __init board_register_devices(void)\n \tif (board.has_usbd)\n \t\tbcm63xx_usbd_register(&board.usbd);\n \n+\tif (board.has_ehci0)\n+\t\tbcm63xx_ehci_register();\n+\n \tif (board.has_ohci0)\n \t\tbcm63xx_ohci_register();\n \n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/110-MIPS-BCM63XX-EHCI-controller-does-not-support-overcu.patch",
    "content": "From 111bbd770441ab34f9da5bb1d85767a9b75227b4 Mon Sep 17 00:00:00 2001\nFrom: Florian Fainelli <florian@openwrt.org>\nDate: Mon, 28 Jan 2013 20:06:30 +0100\nSubject: [PATCH 12/12] MIPS: BCM63XX: EHCI controller does not support\n overcurrent\n\nThis patch sets the spurious_oc flag for the BCM63XX EHCI controller as it\ndoes not support proper overcurrent reporting.\n\nSigned-off-by: Florian Fainelli <florian@openwrt.org>\n---\n arch/mips/bcm63xx/dev-usb-ehci.c |    1 +\n 1 file changed, 1 insertion(+)\n\n--- a/arch/mips/bcm63xx/dev-usb-ehci.c\n+++ b/arch/mips/bcm63xx/dev-usb-ehci.c\n@@ -61,6 +61,7 @@ static void bcm63xx_ehci_power_off(struc\n static struct usb_ehci_pdata bcm63xx_ehci_pdata = {\n \t.big_endian_desc\t= 1,\n \t.big_endian_mmio\t= 1,\n+\t.spurious_oc\t\t= 1,\n \t.power_on\t\t= bcm63xx_ehci_power_on,\n \t.power_off\t\t= bcm63xx_ehci_power_off,\n \t.power_suspend\t\t= bcm63xx_ehci_power_off,\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/130-pinctrl-add-bcm63xx-base-code.patch",
    "content": "From ab2f33e35e35905a76204138143875251f3e1088 Mon Sep 17 00:00:00 2001\nFrom: Jonas Gorski <jonas.gorski@gmail.com>\nDate: Fri, 24 Jun 2016 22:07:42 +0200\nSubject: [PATCH 01/13] pinctrl: add bcm63xx base code\n\nSetup directory and add a helper for bcm63xx pinctrl support.\n\nSigned-off-by: Jonas Gorski <jonas.gorski@gmail.com>\n---\n drivers/pinctrl/Kconfig                   |   1 +\n drivers/pinctrl/Makefile                  |   1 +\n drivers/pinctrl/bcm63xx/Kconfig           |   3 +\n drivers/pinctrl/bcm63xx/Makefile          |   1 +\n drivers/pinctrl/bcm63xx/pinctrl-bcm63xx.c | 142 ++++++++++++++++++++++++++++++\n drivers/pinctrl/bcm63xx/pinctrl-bcm63xx.h |  14 +++\n 7 files changed, 163 insertions(+)\n create mode 100644 drivers/pinctrl/bcm63xx/Kconfig\n create mode 100644 drivers/pinctrl/bcm63xx/Makefile\n create mode 100644 drivers/pinctrl/bcm63xx/pinctrl-bcm63xx.c\n create mode 100644 drivers/pinctrl/bcm63xx/pinctrl-bcm63xx.h\n\n--- a/drivers/pinctrl/Kconfig\n+++ b/drivers/pinctrl/Kconfig\n@@ -377,6 +377,7 @@ config PINCTRL_OCELOT\n source \"drivers/pinctrl/actions/Kconfig\"\n source \"drivers/pinctrl/aspeed/Kconfig\"\n source \"drivers/pinctrl/bcm/Kconfig\"\n+source \"drivers/pinctrl/bcm63xx/Kconfig\"\n source \"drivers/pinctrl/berlin/Kconfig\"\n source \"drivers/pinctrl/freescale/Kconfig\"\n source \"drivers/pinctrl/intel/Kconfig\"\n--- a/drivers/pinctrl/Makefile\n+++ b/drivers/pinctrl/Makefile\n@@ -51,6 +51,7 @@ obj-$(CONFIG_PINCTRL_EQUILIBRIUM)   += p\n obj-y\t\t\t\t+= actions/\n obj-$(CONFIG_ARCH_ASPEED)\t+= aspeed/\n obj-y\t\t\t\t+= bcm/\n+obj-y\t\t\t\t+= bcm63xx/\n obj-$(CONFIG_PINCTRL_BERLIN)\t+= berlin/\n obj-y\t\t\t\t+= freescale/\n obj-$(CONFIG_X86)\t\t+= intel/\n--- /dev/null\n+++ b/drivers/pinctrl/bcm63xx/Kconfig\n@@ -0,0 +1,3 @@\n+config PINCTRL_BCM63XX\n+\tbool\n+\tselect GPIO_GENERIC\n--- /dev/null\n+++ b/drivers/pinctrl/bcm63xx/Makefile\n@@ -0,0 +1 @@\n+obj-$(CONFIG_PINCTRL_BCM63XX)\t+= pinctrl-bcm63xx.o\n--- /dev/null\n+++ b/drivers/pinctrl/bcm63xx/pinctrl-bcm63xx.c\n@@ -0,0 +1,155 @@\n+/*\n+ * This file is subject to the terms and conditions of the GNU General Public\n+ * License.  See the file \"COPYING\" in the main directory of this archive\n+ * for more details.\n+ *\n+ * Copyright (C) 2016 Jonas Gorski <jonas.gorski@gmail.com>\n+ */\n+\n+#include <linux/bitops.h>\n+#include <linux/device.h>\n+#include <linux/gpio/driver.h>\n+#include <linux/of_irq.h>\n+\n+#include \"pinctrl-bcm63xx.h\"\n+#include \"../core.h\"\n+\n+#define BANK_SIZE\tsizeof(u32)\n+#define PINS_PER_BANK\t(BANK_SIZE * BITS_PER_BYTE)\n+\n+#ifdef CONFIG_OF\n+static int bcm63xx_gpio_of_xlate(struct gpio_chip *gc,\n+\t\t\t\t const struct of_phandle_args *gpiospec,\n+\t\t\t\t u32 *flags)\n+{\n+\tstruct gpio_chip *base = gpiochip_get_data(gc);\n+\tint pin = gpiospec->args[0];\n+\n+\tif (gc != &base[pin / PINS_PER_BANK])\n+\t\treturn -EINVAL;\n+\n+\tpin = pin % PINS_PER_BANK;\n+\n+\tif (pin >= gc->ngpio)\n+\t\treturn -EINVAL;\n+\n+\tif (flags)\n+\t\t*flags = gpiospec->args[1];\n+\n+\treturn pin;\n+}\n+#endif\n+\n+static int bcm63xx_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)\n+{\n+\tstruct gpio_chip *base = gpiochip_get_data(chip);\n+\tchar irq_name[7]; /* \"gpioXX\" */\n+\n+\t/* FIXME: this is ugly */\n+\tsprintf(irq_name, \"gpio%d\", gpio + PINS_PER_BANK * (chip - base));\n+\treturn of_irq_get_byname(chip->of_node, irq_name);\n+}\n+\n+static int bcm63xx_setup_gpio(struct device *dev, struct gpio_chip *gc,\n+\t\t\t      void __iomem *dirout, void __iomem *data,\n+\t\t\t      size_t sz, int ngpio)\n+\n+{\n+\tint banks, chips, i, ret = -EINVAL;\n+\n+\tchips = DIV_ROUND_UP(ngpio, PINS_PER_BANK);\n+\tbanks = sz / BANK_SIZE;\n+\n+\tfor (i = 0; i < chips; i++) {\n+\t\tint offset, pins;\n+\t\tint reg_offset;\n+\t\tchar *label;\n+\n+\t\tlabel = devm_kasprintf(dev, GFP_KERNEL, \"bcm63xx-gpio.%i\", i);\n+\t\tif (!label)\n+\t\t\treturn -ENOMEM;\n+\n+\t\toffset = i * PINS_PER_BANK;\n+\t\tpins = min_t(int, ngpio - offset, PINS_PER_BANK);\n+\n+\t\t/* the registers are treated like a huge big endian register */\n+\t\treg_offset = (banks - i - 1) * BANK_SIZE;\n+\n+\t\tret = bgpio_init(&gc[i], dev, BANK_SIZE, data + reg_offset,\n+\t\t\t\t NULL, NULL, dirout + reg_offset, NULL,\n+\t\t\t\t BGPIOF_BIG_ENDIAN_BYTE_ORDER);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\n+\t\tgc[i].request = gpiochip_generic_request;\n+\t\tgc[i].free = gpiochip_generic_free;\n+\n+\t\tif (of_get_property(dev->of_node, \"interrupt-names\", NULL))\n+\t\t\tgc[i].to_irq = bcm63xx_gpio_to_irq;\n+\n+#ifdef CONFIG_OF\n+\t\tgc[i].of_gpio_n_cells = 2;\n+\t\tgc[i].of_xlate = bcm63xx_gpio_of_xlate;\n+#endif\n+\n+\t\tgc[i].label = label;\n+\t\tgc[i].ngpio = pins;\n+\n+\t\tdevm_gpiochip_add_data(dev, &gc[i], gc);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static void bcm63xx_setup_pinranges(struct gpio_chip *gc, const char *name,\n+\t\t\t\t    int ngpio)\n+{\n+\tint i, chips = DIV_ROUND_UP(ngpio, PINS_PER_BANK);\n+\n+\tfor (i = 0; i < chips; i++) {\n+\t\tint offset, pins;\n+\n+\t\toffset = i * PINS_PER_BANK;\n+\t\tpins = min_t(int, ngpio - offset, PINS_PER_BANK);\n+\n+\t\tgpiochip_add_pin_range(&gc[i], name, 0, offset, pins);\n+\t}\n+}\n+\n+struct pinctrl_dev *bcm63xx_pinctrl_register(struct platform_device *pdev,\n+\t\t\t\t\t     struct pinctrl_desc *desc,\n+\t\t\t\t\t     void *priv, struct gpio_chip *gc,\n+\t\t\t\t\t     int ngpio)\n+{\n+\tstruct pinctrl_dev *pctldev;\n+\tstruct resource *res;\n+\tvoid __iomem *dirout, *data;\n+\tsize_t sz;\n+\tint ret;\n+\n+\tres = platform_get_resource_byname(pdev, IORESOURCE_MEM, \"dirout\");\n+\tdirout = devm_ioremap_resource(&pdev->dev, res);\n+\tif (IS_ERR(dirout))\n+\t\treturn ERR_CAST(dirout);\n+\n+\tres = platform_get_resource_byname(pdev, IORESOURCE_MEM, \"dat\");\n+\tdata = devm_ioremap_resource(&pdev->dev, res);\n+\tif (IS_ERR(data))\n+\t\treturn ERR_CAST(data);\n+\n+\tsz = resource_size(res);\n+\n+\tret = bcm63xx_setup_gpio(&pdev->dev, gc, dirout, data, sz, ngpio);\n+\tif (ret)\n+\t\treturn ERR_PTR(ret);\n+\n+\tpctldev = devm_pinctrl_register(&pdev->dev, desc, priv);\n+\tif (IS_ERR(pctldev))\n+\t\treturn pctldev;\n+\n+\tbcm63xx_setup_pinranges(gc, pinctrl_dev_get_devname(pctldev), ngpio);\n+\n+\tdev_info(&pdev->dev, \"registered at mmio %p\\n\", dirout);\n+\n+\treturn pctldev;\n+}\n--- /dev/null\n+++ b/drivers/pinctrl/bcm63xx/pinctrl-bcm63xx.h\n@@ -0,0 +1,14 @@\n+#ifndef __PINCTRL_BCM63XX\n+#define __PINCTRL_BCM63XX\n+\n+#include <linux/kernel.h>\n+#include <linux/gpio.h>\n+#include <linux/pinctrl/pinctrl.h>\n+#include <linux/platform_device.h>\n+\n+struct pinctrl_dev *bcm63xx_pinctrl_register(struct platform_device *pdev,\n+\t\t\t\t\t     struct pinctrl_desc *desc,\n+\t\t\t\t\t     void *priv, struct gpio_chip *gc,\n+\t\t\t\t\t     int ngpio);\n+\n+#endif\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/131-Documentation-add-BCM6328-pincontroller-binding-docu.patch",
    "content": "From 4bdd40849632608d5cb7d3a64380cd76e7eea07b Mon Sep 17 00:00:00 2001\nFrom: Jonas Gorski <jonas.gorski@gmail.com>\nDate: Wed, 27 Jul 2016 11:33:56 +0200\nSubject: [PATCH 02/16] Documentation: add BCM6328 pincontroller binding\n documentation\n\nAdd binding documentation for the pincontrol core found in BCM6328 SoCs.\n\nSigned-off-by: Jonas Gorski <jonas.gorski@gmail.com>\n---\n .../bindings/pinctrl/brcm,bcm6328-pinctrl.txt      | 61 ++++++++++++++++++++++\n 1 file changed, 61 insertions(+)\n create mode 100644 Documentation/devicetree/bindings/pinctrl/brcm,bcm6328-pinctrl.txt\n\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/pinctrl/brcm,bcm6328-pinctrl.txt\n@@ -0,0 +1,61 @@\n+* Broadcom BCM6328 pin controller\n+\n+Required properties:\n+- compatible: Must be \"brcm,bcm6328-pinctrl\".\n+- reg: Register specifies of dirout, dat, mode, mux registers.\n+- reg-names: Must be \"dirout\", \"dat\", \"mode\", \"mux\".\n+- gpio-controller: Identifies this node as a GPIO controller.\n+- #gpio-cells: Must be <2>\n+\n+Example:\n+\n+pinctrl: pin-controller@10000080 {\n+\tcompatible = \"brcm,bcm6328-pinctrl\";\n+\treg = <0x10000080 0x8>,\n+\t      <0x10000088 0x8>,\n+\t      <0x10000098 0x4>,\n+\t      <0x1000009c 0xc>;\n+\treg-names = \"dirout\", \"dat\", \"mode\", \"mux\";\n+\n+\tgpio-controller;\n+\t#gpio-cells = <2>;\n+};\n+\n+Available pins/groups and functions:\n+\n+name\t\tpins\tfunctions\n+-----------------------------------------------------------\n+gpio0\t\t0\tled\n+gpio1\t\t1\tled\n+gpio2\t\t2\tled\n+gpio3\t\t3\tled\n+gpio4\t\t4\tled\n+gpio5\t\t5\tled\n+gpio6\t\t6\tled, serial_led_data\n+gpio7\t\t7\tled, serial_led_clk\n+gpio8\t\t8\tled\n+gpio9\t\t9\tled\n+gpio10\t\t10\tled\n+gpio11\t\t11\tled\n+gpio12\t\t12\tled\n+gpio13\t\t13\tled\n+gpio14\t\t14\tled\n+gpio15\t\t15\tled\n+gpio16\t\t16\tled, pcie_clkreq\n+gpio17\t\t17\tled\n+gpio18\t\t18\tled\n+gpio19\t\t19\tled\n+gpio20\t\t20\tled\n+gpio21\t\t21\tled\n+gpio22\t\t22\tled\n+gpio23\t\t23\tled\n+gpio24\t\t24\t-\n+gpio25\t\t25\tephy0_act_led\n+gpio26\t\t26\tephy1_act_led\n+gpio27\t\t27\tephy2_act_led\n+gpio28\t\t28\tephy3_act_led\n+gpio29\t\t29\t-\n+gpio30\t\t30\t-\n+gpio31\t\t31\t-\n+hsspi_cs1\t-\thsspi_cs1\n+usb_port1\t-\tusb_host_port, usb_device_port\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/132-pinctrl-add-a-pincontrol-driver-for-BCM6328.patch",
    "content": "From 393e9753f6492c1fdf55891ddee60d955ae8b119 Mon Sep 17 00:00:00 2001\nFrom: Jonas Gorski <jonas.gorski@gmail.com>\nDate: Fri, 24 Jun 2016 22:12:50 +0200\nSubject: [PATCH 03/16] pinctrl: add a pincontrol driver for BCM6328\n\nAdd a pincontrol driver for BCM6328. BCM628 supports muxing 32 pins as\nGPIOs, as LEDs for the integrated LED controller, or various other\nfunctions. Its pincontrol mux registers also control other aspects, like\nswitching the second USB port between host and device mode.\n\nSigned-off-by: Jonas Gorski <jonas.gorski@gmail.com>\n---\n drivers/pinctrl/bcm63xx/Kconfig           |   7 +\n drivers/pinctrl/bcm63xx/Makefile          |   1 +\n drivers/pinctrl/bcm63xx/pinctrl-bcm6328.c | 456 ++++++++++++++++++++++++++++++\n 3 files changed, 464 insertions(+)\n create mode 100644 drivers/pinctrl/bcm63xx/pinctrl-bcm6328.c\n\n--- a/drivers/pinctrl/bcm63xx/Kconfig\n+++ b/drivers/pinctrl/bcm63xx/Kconfig\n@@ -1,3 +1,10 @@\n config PINCTRL_BCM63XX\n \tbool\n \tselect GPIO_GENERIC\n+\n+config PINCTRL_BCM6328\n+\tbool \"BCM6328 pincontrol driver\" if COMPILE_TEST\n+\tselect PINMUX\n+\tselect PINCONF\n+\tselect PINCTRL_BCM63XX\n+\tselect GENERIC_PINCONF\n--- a/drivers/pinctrl/bcm63xx/Makefile\n+++ b/drivers/pinctrl/bcm63xx/Makefile\n@@ -1 +1,2 @@\n obj-$(CONFIG_PINCTRL_BCM63XX)\t+= pinctrl-bcm63xx.o\n+obj-$(CONFIG_PINCTRL_BCM6328)\t+= pinctrl-bcm6328.o\n--- /dev/null\n+++ b/drivers/pinctrl/bcm63xx/pinctrl-bcm6328.c\n@@ -0,0 +1,456 @@\n+/*\n+ * This file is subject to the terms and conditions of the GNU General Public\n+ * License.  See the file \"COPYING\" in the main directory of this archive\n+ * for more details.\n+ *\n+ * Copyright (C) 2016 Jonas Gorski <jonas.gorski@gmail.com>\n+ */\n+\n+#include <linux/bitops.h>\n+#include <linux/gpio.h>\n+#include <linux/kernel.h>\n+#include <linux/slab.h>\n+#include <linux/spinlock.h>\n+#include <linux/of.h>\n+#include <linux/of_gpio.h>\n+#include <linux/platform_device.h>\n+\n+#include <linux/pinctrl/machine.h>\n+#include <linux/pinctrl/pinconf.h>\n+#include <linux/pinctrl/pinconf-generic.h>\n+#include <linux/pinctrl/pinmux.h>\n+\n+#include \"../core.h\"\n+#include \"../pinctrl-utils.h\"\n+\n+#include \"pinctrl-bcm63xx.h\"\n+\n+#define BCM6328_MUX_LO_REG\t0x4\n+#define BCM6328_MUX_HI_REG\t0x0\n+#define BCM6328_MUX_OTHER_REG\t0x8\n+\n+#define BCM6328_NGPIO\t\t32\n+\n+struct bcm6328_pingroup {\n+\tconst char *name;\n+\tconst unsigned * const pins;\n+\tconst unsigned num_pins;\n+};\n+\n+struct bcm6328_function {\n+\tconst char *name;\n+\tconst char * const *groups;\n+\tconst unsigned num_groups;\n+\n+\tunsigned mode_val:1;\n+\tunsigned mux_val:2;\n+};\n+\n+struct bcm6328_pinctrl {\n+\tstruct pinctrl_dev *pctldev;\n+\tstruct pinctrl_desc desc;\n+\n+\tvoid __iomem *mode;\n+\tvoid __iomem *mux[3];\n+\n+\t/* register access lock */\n+\tspinlock_t lock;\n+\n+\tstruct gpio_chip gpio;\n+};\n+\n+static const struct pinctrl_pin_desc bcm6328_pins[] = {\n+\tPINCTRL_PIN(0, \"gpio0\"),\n+\tPINCTRL_PIN(1, \"gpio1\"),\n+\tPINCTRL_PIN(2, \"gpio2\"),\n+\tPINCTRL_PIN(3, \"gpio3\"),\n+\tPINCTRL_PIN(4, \"gpio4\"),\n+\tPINCTRL_PIN(5, \"gpio5\"),\n+\tPINCTRL_PIN(6, \"gpio6\"),\n+\tPINCTRL_PIN(7, \"gpio7\"),\n+\tPINCTRL_PIN(8, \"gpio8\"),\n+\tPINCTRL_PIN(9, \"gpio9\"),\n+\tPINCTRL_PIN(10, \"gpio10\"),\n+\tPINCTRL_PIN(11, \"gpio11\"),\n+\tPINCTRL_PIN(12, \"gpio12\"),\n+\tPINCTRL_PIN(13, \"gpio13\"),\n+\tPINCTRL_PIN(14, \"gpio14\"),\n+\tPINCTRL_PIN(15, \"gpio15\"),\n+\tPINCTRL_PIN(16, \"gpio16\"),\n+\tPINCTRL_PIN(17, \"gpio17\"),\n+\tPINCTRL_PIN(18, \"gpio18\"),\n+\tPINCTRL_PIN(19, \"gpio19\"),\n+\tPINCTRL_PIN(20, \"gpio20\"),\n+\tPINCTRL_PIN(21, \"gpio21\"),\n+\tPINCTRL_PIN(22, \"gpio22\"),\n+\tPINCTRL_PIN(23, \"gpio23\"),\n+\tPINCTRL_PIN(24, \"gpio24\"),\n+\tPINCTRL_PIN(25, \"gpio25\"),\n+\tPINCTRL_PIN(26, \"gpio26\"),\n+\tPINCTRL_PIN(27, \"gpio27\"),\n+\tPINCTRL_PIN(28, \"gpio28\"),\n+\tPINCTRL_PIN(29, \"gpio29\"),\n+\tPINCTRL_PIN(30, \"gpio30\"),\n+\tPINCTRL_PIN(31, \"gpio31\"),\n+\n+\t/*\n+\t * No idea where they really are; so let's put them according\n+\t * to their mux offsets.\n+\t */\n+\tPINCTRL_PIN(36, \"hsspi_cs1\"),\n+\tPINCTRL_PIN(38, \"usb_p2\"),\n+};\n+\n+static unsigned gpio0_pins[] = { 0 };\n+static unsigned gpio1_pins[] = { 1 };\n+static unsigned gpio2_pins[] = { 2 };\n+static unsigned gpio3_pins[] = { 3 };\n+static unsigned gpio4_pins[] = { 4 };\n+static unsigned gpio5_pins[] = { 5 };\n+static unsigned gpio6_pins[] = { 6 };\n+static unsigned gpio7_pins[] = { 7 };\n+static unsigned gpio8_pins[] = { 8 };\n+static unsigned gpio9_pins[] = { 9 };\n+static unsigned gpio10_pins[] = { 10 };\n+static unsigned gpio11_pins[] = { 11 };\n+static unsigned gpio12_pins[] = { 12 };\n+static unsigned gpio13_pins[] = { 13 };\n+static unsigned gpio14_pins[] = { 14 };\n+static unsigned gpio15_pins[] = { 15 };\n+static unsigned gpio16_pins[] = { 16 };\n+static unsigned gpio17_pins[] = { 17 };\n+static unsigned gpio18_pins[] = { 18 };\n+static unsigned gpio19_pins[] = { 19 };\n+static unsigned gpio20_pins[] = { 20 };\n+static unsigned gpio21_pins[] = { 21 };\n+static unsigned gpio22_pins[] = { 22 };\n+static unsigned gpio23_pins[] = { 23 };\n+static unsigned gpio24_pins[] = { 24 };\n+static unsigned gpio25_pins[] = { 25 };\n+static unsigned gpio26_pins[] = { 26 };\n+static unsigned gpio27_pins[] = { 27 };\n+static unsigned gpio28_pins[] = { 28 };\n+static unsigned gpio29_pins[] = { 29 };\n+static unsigned gpio30_pins[] = { 30 };\n+static unsigned gpio31_pins[] = { 31 };\n+\n+static unsigned hsspi_cs1_pins[] = { 36 };\n+static unsigned usb_port1_pins[] = { 38 };\n+\n+#define BCM6328_GROUP(n)\t\t\t\t\t\\\n+\t{\t\t\t\t\t\t\t\\\n+\t\t.name = #n,\t\t\t\t\t\\\n+\t\t.pins = n##_pins,\t\t\t\t\\\n+\t\t.num_pins = ARRAY_SIZE(n##_pins),\t\t\\\n+\t}\n+\n+static struct bcm6328_pingroup bcm6328_groups[] = {\n+\tBCM6328_GROUP(gpio0),\n+\tBCM6328_GROUP(gpio1),\n+\tBCM6328_GROUP(gpio2),\n+\tBCM6328_GROUP(gpio3),\n+\tBCM6328_GROUP(gpio4),\n+\tBCM6328_GROUP(gpio5),\n+\tBCM6328_GROUP(gpio6),\n+\tBCM6328_GROUP(gpio7),\n+\tBCM6328_GROUP(gpio8),\n+\tBCM6328_GROUP(gpio9),\n+\tBCM6328_GROUP(gpio10),\n+\tBCM6328_GROUP(gpio11),\n+\tBCM6328_GROUP(gpio12),\n+\tBCM6328_GROUP(gpio13),\n+\tBCM6328_GROUP(gpio14),\n+\tBCM6328_GROUP(gpio15),\n+\tBCM6328_GROUP(gpio16),\n+\tBCM6328_GROUP(gpio17),\n+\tBCM6328_GROUP(gpio18),\n+\tBCM6328_GROUP(gpio19),\n+\tBCM6328_GROUP(gpio20),\n+\tBCM6328_GROUP(gpio21),\n+\tBCM6328_GROUP(gpio22),\n+\tBCM6328_GROUP(gpio23),\n+\tBCM6328_GROUP(gpio24),\n+\tBCM6328_GROUP(gpio25),\n+\tBCM6328_GROUP(gpio26),\n+\tBCM6328_GROUP(gpio27),\n+\tBCM6328_GROUP(gpio28),\n+\tBCM6328_GROUP(gpio29),\n+\tBCM6328_GROUP(gpio30),\n+\tBCM6328_GROUP(gpio31),\n+\n+\tBCM6328_GROUP(hsspi_cs1),\n+\tBCM6328_GROUP(usb_port1),\n+};\n+\n+/* GPIO_MODE */\n+static const char * const led_groups[] = {\n+\t\"gpio0\",\n+\t\"gpio1\",\n+\t\"gpio2\",\n+\t\"gpio3\",\n+\t\"gpio4\",\n+\t\"gpio5\",\n+\t\"gpio6\",\n+\t\"gpio7\",\n+\t\"gpio8\",\n+\t\"gpio9\",\n+\t\"gpio10\",\n+\t\"gpio11\",\n+\t\"gpio12\",\n+\t\"gpio13\",\n+\t\"gpio14\",\n+\t\"gpio15\",\n+\t\"gpio16\",\n+\t\"gpio17\",\n+\t\"gpio18\",\n+\t\"gpio19\",\n+\t\"gpio20\",\n+\t\"gpio21\",\n+\t\"gpio22\",\n+\t\"gpio23\",\n+};\n+\n+/* PINMUX_SEL */\n+static const char * const serial_led_data_groups[] = {\n+\t\"gpio6\",\n+};\n+\n+static const char * const serial_led_clk_groups[] = {\n+\t\"gpio7\",\n+};\n+\n+static const char * const inet_act_led_groups[] = {\n+\t\"gpio11\",\n+};\n+\n+static const char * const pcie_clkreq_groups[] = {\n+\t\"gpio16\",\n+};\n+\n+static const char * const ephy0_act_led_groups[] = {\n+\t\"gpio25\",\n+};\n+\n+static const char * const ephy1_act_led_groups[] = {\n+\t\"gpio26\",\n+};\n+\n+static const char * const ephy2_act_led_groups[] = {\n+\t\"gpio27\",\n+};\n+\n+static const char * const ephy3_act_led_groups[] = {\n+\t\"gpio28\",\n+};\n+\n+static const char * const hsspi_cs1_groups[] = {\n+\t\"hsspi_cs1\"\n+};\n+\n+static const char * const usb_host_port_groups[] = {\n+\t\"usb_port1\",\n+};\n+\n+static const char * const usb_device_port_groups[] = {\n+\t\"usb_port1\",\n+};\n+\n+#define BCM6328_MODE_FUN(n)\t\t\t\t\\\n+\t{\t\t\t\t\t\t\\\n+\t\t.name = #n,\t\t\t\t\\\n+\t\t.groups = n##_groups,\t\t\t\\\n+\t\t.num_groups = ARRAY_SIZE(n##_groups),\t\\\n+\t\t.mode_val = 1,\t\t\t\t\\\n+\t}\n+\n+#define BCM6328_MUX_FUN(n, mux)\t\t\t\t\\\n+\t{\t\t\t\t\t\t\\\n+\t\t.name = #n,\t\t\t\t\\\n+\t\t.groups = n##_groups,\t\t\t\\\n+\t\t.num_groups = ARRAY_SIZE(n##_groups),\t\\\n+\t\t.mux_val = mux,\t\t\t\t\\\n+\t}\n+\n+static const struct bcm6328_function bcm6328_funcs[] = {\n+\tBCM6328_MODE_FUN(led),\n+\tBCM6328_MUX_FUN(serial_led_data, 2),\n+\tBCM6328_MUX_FUN(serial_led_clk, 2),\n+\tBCM6328_MUX_FUN(inet_act_led, 1),\n+\tBCM6328_MUX_FUN(pcie_clkreq, 2),\n+\tBCM6328_MUX_FUN(ephy0_act_led, 1),\n+\tBCM6328_MUX_FUN(ephy1_act_led, 1),\n+\tBCM6328_MUX_FUN(ephy2_act_led, 1),\n+\tBCM6328_MUX_FUN(ephy3_act_led, 1),\n+\tBCM6328_MUX_FUN(hsspi_cs1, 2),\n+\tBCM6328_MUX_FUN(usb_host_port, 1),\n+\tBCM6328_MUX_FUN(usb_device_port, 2),\n+};\n+\n+static int bcm6328_pinctrl_get_group_count(struct pinctrl_dev *pctldev)\n+{\n+\treturn ARRAY_SIZE(bcm6328_groups);\n+}\n+\n+static const char *bcm6328_pinctrl_get_group_name(struct pinctrl_dev *pctldev,\n+\t\t\t\t\t\t  unsigned group)\n+{\n+\treturn bcm6328_groups[group].name;\n+}\n+\n+static int bcm6328_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,\n+\t\t\t\t\t  unsigned group, const unsigned **pins,\n+\t\t\t\t\t  unsigned *num_pins)\n+{\n+\t*pins = bcm6328_groups[group].pins;\n+\t*num_pins = bcm6328_groups[group].num_pins;\n+\n+\treturn 0;\n+}\n+\n+static int bcm6328_pinctrl_get_func_count(struct pinctrl_dev *pctldev)\n+{\n+\treturn ARRAY_SIZE(bcm6328_funcs);\n+}\n+\n+static const char *bcm6328_pinctrl_get_func_name(struct pinctrl_dev *pctldev,\n+\t\t\t\t\t\t unsigned selector)\n+{\n+\treturn bcm6328_funcs[selector].name;\n+}\n+\n+static int bcm6328_pinctrl_get_groups(struct pinctrl_dev *pctldev,\n+\t\t\t\t      unsigned selector,\n+\t\t\t\t      const char * const **groups,\n+\t\t\t\t      unsigned * const num_groups)\n+{\n+\t*groups = bcm6328_funcs[selector].groups;\n+\t*num_groups = bcm6328_funcs[selector].num_groups;\n+\n+\treturn 0;\n+}\n+\n+static void bcm6328_rmw_mux(struct bcm6328_pinctrl *pctl, unsigned pin,\n+\t\t\t    u32 mode, u32 mux)\n+{\n+\tunsigned long flags;\n+\tu32 reg;\n+\n+\tspin_lock_irqsave(&pctl->lock, flags);\n+\tif (pin < 32) {\n+\t\treg = __raw_readl(pctl->mode);\n+\t\treg &= ~BIT(pin);\n+\t\tif (mode)\n+\t\t\treg |= BIT(pin);\n+\t\t__raw_writel(reg, pctl->mode);\n+\t}\n+\n+\treg = __raw_readl(pctl->mux[pin / 16]);\n+\treg &= ~(3UL << ((pin % 16) * 2));\n+\treg |= mux << ((pin % 16) * 2);\n+\t__raw_writel(reg, pctl->mux[pin / 16]);\n+\n+\tspin_unlock_irqrestore(&pctl->lock, flags);\n+}\n+\n+static int bcm6328_pinctrl_set_mux(struct pinctrl_dev *pctldev,\n+\t\t\t\t   unsigned selector, unsigned group)\n+{\n+\tstruct bcm6328_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);\n+\tconst struct bcm6328_pingroup *grp = &bcm6328_groups[group];\n+\tconst struct bcm6328_function *f = &bcm6328_funcs[selector];\n+\n+\tbcm6328_rmw_mux(pctl, grp->pins[0], f->mode_val, f->mux_val);\n+\n+\treturn 0;\n+}\n+\n+static int bcm6328_gpio_request_enable(struct pinctrl_dev *pctldev,\n+\t\t\t\t       struct pinctrl_gpio_range *range,\n+\t\t\t\t       unsigned offset)\n+{\n+\tstruct bcm6328_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);\n+\n+\t/* disable all functions using this pin */\n+\tbcm6328_rmw_mux(pctl, offset, 0, 0);\n+\n+\treturn 0;\n+}\n+\n+static struct pinctrl_ops bcm6328_pctl_ops = {\n+\t.get_groups_count\t= bcm6328_pinctrl_get_group_count,\n+\t.get_group_name\t\t= bcm6328_pinctrl_get_group_name,\n+\t.get_group_pins\t\t= bcm6328_pinctrl_get_group_pins,\n+#ifdef CONFIG_OF\n+\t.dt_node_to_map\t\t= pinconf_generic_dt_node_to_map_pin,\n+\t.dt_free_map\t\t= pinctrl_utils_free_map,\n+#endif\n+};\n+\n+static struct pinmux_ops bcm6328_pmx_ops = {\n+\t.get_functions_count\t= bcm6328_pinctrl_get_func_count,\n+\t.get_function_name\t= bcm6328_pinctrl_get_func_name,\n+\t.get_function_groups\t= bcm6328_pinctrl_get_groups,\n+\t.set_mux\t\t= bcm6328_pinctrl_set_mux,\n+\t.gpio_request_enable\t= bcm6328_gpio_request_enable,\n+\t.strict\t\t\t= true,\n+};\n+\n+static int bcm6328_pinctrl_probe(struct platform_device *pdev)\n+{\n+\tstruct bcm6328_pinctrl *pctl;\n+\tstruct resource *res;\n+\tvoid __iomem *mode, *mux;\n+\n+\tres = platform_get_resource_byname(pdev, IORESOURCE_MEM, \"mode\");\n+\tmode = devm_ioremap_resource(&pdev->dev, res);\n+\tif (IS_ERR(mode))\n+\t\treturn PTR_ERR(mode);\n+\n+\tres = platform_get_resource_byname(pdev, IORESOURCE_MEM, \"mux\");\n+\tmux = devm_ioremap_resource(&pdev->dev, res);\n+\tif (IS_ERR(mux))\n+\t\treturn PTR_ERR(mux);\n+\n+\tpctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);\n+\tif (!pctl)\n+\t\treturn -ENOMEM;\n+\n+\tspin_lock_init(&pctl->lock);\n+\n+\tpctl->mode = mode;\n+\tpctl->mux[0] = mux + BCM6328_MUX_LO_REG;\n+\tpctl->mux[1] = mux + BCM6328_MUX_HI_REG;\n+\tpctl->mux[2] = mux + BCM6328_MUX_OTHER_REG;\n+\n+\tpctl->desc.name = dev_name(&pdev->dev);\n+\tpctl->desc.owner = THIS_MODULE;\n+\tpctl->desc.pctlops = &bcm6328_pctl_ops;\n+\tpctl->desc.pmxops = &bcm6328_pmx_ops;\n+\n+\tpctl->desc.npins = ARRAY_SIZE(bcm6328_pins);\n+\tpctl->desc.pins = bcm6328_pins;\n+\n+\tplatform_set_drvdata(pdev, pctl);\n+\n+\tpctl->pctldev = bcm63xx_pinctrl_register(pdev, &pctl->desc, pctl,\n+\t\t\t\t\t\t &pctl->gpio, BCM6328_NGPIO);\n+\tif (IS_ERR(pctl->pctldev))\n+\t\treturn PTR_ERR(pctl->pctldev);\n+\n+\treturn 0;\n+}\n+\n+static const struct of_device_id bcm6328_pinctrl_match[] = {\n+\t{ .compatible = \"brcm,bcm6328-pinctrl\", },\n+\t{ },\n+};\n+\n+static struct platform_driver bcm6328_pinctrl_driver = {\n+\t.probe = bcm6328_pinctrl_probe,\n+\t.driver = {\n+\t\t.name = \"bcm6328-pinctrl\",\n+\t\t.of_match_table = bcm6328_pinctrl_match,\n+\t},\n+};\n+\n+builtin_platform_driver(bcm6328_pinctrl_driver);\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/133-Documentation-add-BCM6348-pincontroller-binding-docu.patch",
    "content": "From 962c46bf7f43df730e2d3698930e77958cc6b191 Mon Sep 17 00:00:00 2001\nFrom: Jonas Gorski <jonas.gorski@gmail.com>\nDate: Wed, 27 Jul 2016 11:35:45 +0200\nSubject: [PATCH 04/16] Documentation: add BCM6348 pincontroller binding\n documentation\n\nAdd binding documentation for the pincontrol core found in BCM6348 SoCs.\n\nSigned-off-by: Jonas Gorski <jonas.gorski@gmail.com>\n---\n .../bindings/pinctrl/brcm,bcm6348-pinctrl.txt      | 32 ++++++++++++++++++++++\n 1 file changed, 32 insertions(+)\n create mode 100644 Documentation/devicetree/bindings/pinctrl/brcm,bcm6348-pinctrl.txt\n\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/pinctrl/brcm,bcm6348-pinctrl.txt\n@@ -0,0 +1,32 @@\n+* Broadcom BCM6348 pin controller\n+\n+Required properties:\n+- compatible: Must be \"brcm,bcm6348-pinctrl\".\n+- reg: register Specifiers of dirout, dat, mode registers.\n+- reg-names: Must be \"dirout\", \"dat\", \"mode\".\n+- gpio-controller: Identifies this node as a GPIO controller.\n+- #gpio-cells: Must be <2>.\n+\n+Example:\n+\n+pinctrl: pin-controller@fffe0080 {\n+\tcompatible = \"brcm,bcm6348-pinctrl\";\n+\treg = <0xfffe0080 0x8>,\n+\t      <0xfffe0088 0x8>,\n+\t      <0xfffe0098 0x4>;\n+\treg-names = \"dirout\", \"dat\", \"mode\";\n+\n+\tgpio-controller;\n+\t#gpio-cells = <2>;\n+};\n+\n+Available pins/groups and functions:\n+\n+name\t\tpins\tfunctions\n+-----------------------------------------------------------\n+group0\t\t32-36\text_mii, diag\n+group1\t\t22-31\text_ephy, mii_snoop, mii_pccard,\n+\t\t\tspi_master_uart, utopia, diag\n+group2\t\t16-21\tpci, diag\n+group3\t\t8-15\text_mii, utopia, diag\n+group4\t\t0-7\text_ephy, mii_snoop, legacy_led, utopia, diag\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/134-pinctrl-add-a-pincontrol-driver-for-BCM6348.patch",
    "content": "From 45444cb631555e2dc16b95d779b10aa075c7482e Mon Sep 17 00:00:00 2001\nFrom: Jonas Gorski <jonas.gorski@gmail.com>\nDate: Fri, 24 Jun 2016 22:14:13 +0200\nSubject: [PATCH 05/16] pinctrl: add a pincontrol driver for BCM6348\n\nAdd a pincotrol driver for BCM6348. BCM6348 allow muxing five groups of\nup to ten gpios into fourteen potential functions. It does not allow\nmuxing individual pins. Some functions require more than one group to be\nmuxed to the same function.\n\nSigned-off-by: Jonas Gorski <jonas.gorski@gmail.com>\n---\n drivers/pinctrl/bcm63xx/Kconfig           |   7 +\n drivers/pinctrl/bcm63xx/Makefile          |   1 +\n drivers/pinctrl/bcm63xx/pinctrl-bcm6348.c | 391 ++++++++++++++++++++++++++++++\n 3 files changed, 399 insertions(+)\n create mode 100644 drivers/pinctrl/bcm63xx/pinctrl-bcm6348.c\n\n--- a/drivers/pinctrl/bcm63xx/Kconfig\n+++ b/drivers/pinctrl/bcm63xx/Kconfig\n@@ -8,3 +8,10 @@ config PINCTRL_BCM6328\n \tselect PINCONF\n \tselect PINCTRL_BCM63XX\n \tselect GENERIC_PINCONF\n+\n+config PINCTRL_BCM6348\n+\tbool \"BCM6348 pincontrol driver\" if COMPILE_TEST\n+\tselect PINMUX\n+\tselect PINCONF\n+\tselect PINCTRL_BCM63XX\n+\tselect GENERIC_PINCONF\n--- a/drivers/pinctrl/bcm63xx/Makefile\n+++ b/drivers/pinctrl/bcm63xx/Makefile\n@@ -1,2 +1,3 @@\n obj-$(CONFIG_PINCTRL_BCM63XX)\t+= pinctrl-bcm63xx.o\n obj-$(CONFIG_PINCTRL_BCM6328)\t+= pinctrl-bcm6328.o\n+obj-$(CONFIG_PINCTRL_BCM6348)\t+= pinctrl-bcm6348.o\n--- /dev/null\n+++ b/drivers/pinctrl/bcm63xx/pinctrl-bcm6348.c\n@@ -0,0 +1,370 @@\n+/*\n+ * This file is subject to the terms and conditions of the GNU General Public\n+ * License.  See the file \"COPYING\" in the main directory of this archive\n+ * for more details.\n+ *\n+ * Copyright (C) 2016 Jonas Gorski <jonas.gorski@gmail.com>\n+ */\n+\n+#include <linux/kernel.h>\n+#include <linux/spinlock.h>\n+#include <linux/bitops.h>\n+#include <linux/gpio.h>\n+#include <linux/of.h>\n+#include <linux/of_gpio.h>\n+#include <linux/slab.h>\n+#include <linux/platform_device.h>\n+\n+#include <linux/pinctrl/machine.h>\n+#include <linux/pinctrl/pinconf.h>\n+#include <linux/pinctrl/pinconf-generic.h>\n+#include <linux/pinctrl/pinmux.h>\n+\n+#include \"../core.h\"\n+#include \"../pinctrl-utils.h\"\n+\n+#include \"pinctrl-bcm63xx.h\"\n+\n+#define BCM6348_NGPIO\t\t37\n+\n+#define MAX_GROUP\t\t4\n+#define PINS_PER_GROUP\t\t8\n+#define PIN_TO_GROUP(pin)\t(MAX_GROUP - ((pin) / PINS_PER_GROUP))\n+#define GROUP_SHIFT(pin)\t(PIN_TO_GROUP(pin) * 4)\n+#define GROUP_MASK(pin)\t\t(0xf << GROUP_SHIFT(pin))\n+\n+struct bcm6348_pingroup {\n+\tconst char *name;\n+\tconst unsigned * const pins;\n+\tconst unsigned num_pins;\n+};\n+\n+struct bcm6348_function {\n+\tconst char *name;\n+\tconst char * const *groups;\n+\tconst unsigned num_groups;\n+\tunsigned int value;\n+};\n+\n+struct bcm6348_pinctrl {\n+\tstruct pinctrl_dev *pctldev;\n+\tstruct pinctrl_desc desc;\n+\n+\tvoid __iomem *mode;\n+\n+\t/* register access lock */\n+\tspinlock_t lock;\n+\n+\tstruct gpio_chip gpio[2];\n+};\n+\n+#define BCM6348_PIN(a, b, group)\t\t\\\n+\t{\t\t\t\t\t\\\n+\t\t.number = a,\t\t\t\\\n+\t\t.name = b,\t\t\t\\\n+\t\t.drv_data = (void *)(group),\t\\\n+\t}\n+\n+static const struct pinctrl_pin_desc bcm6348_pins[] = {\n+\tBCM6348_PIN(0, \"gpio0\", 4),\n+\tBCM6348_PIN(1, \"gpio1\", 4),\n+\tBCM6348_PIN(2, \"gpio2\", 4),\n+\tBCM6348_PIN(3, \"gpio3\", 4),\n+\tBCM6348_PIN(4, \"gpio4\", 4),\n+\tBCM6348_PIN(5, \"gpio5\", 4),\n+\tBCM6348_PIN(6, \"gpio6\", 4),\n+\tBCM6348_PIN(7, \"gpio7\", 4),\n+\tBCM6348_PIN(8, \"gpio8\", 3),\n+\tBCM6348_PIN(9, \"gpio9\", 3),\n+\tBCM6348_PIN(10, \"gpio10\", 3),\n+\tBCM6348_PIN(11, \"gpio11\", 3),\n+\tBCM6348_PIN(12, \"gpio12\", 3),\n+\tBCM6348_PIN(13, \"gpio13\", 3),\n+\tBCM6348_PIN(14, \"gpio14\", 3),\n+\tBCM6348_PIN(15, \"gpio15\", 3),\n+\tBCM6348_PIN(16, \"gpio16\", 2),\n+\tBCM6348_PIN(17, \"gpio17\", 2),\n+\tBCM6348_PIN(18, \"gpio18\", 2),\n+\tBCM6348_PIN(19, \"gpio19\", 2),\n+\tBCM6348_PIN(20, \"gpio20\", 2),\n+\tBCM6348_PIN(21, \"gpio21\", 2),\n+\tBCM6348_PIN(22, \"gpio22\", 1),\n+\tBCM6348_PIN(23, \"gpio23\", 1),\n+\tBCM6348_PIN(24, \"gpio24\", 1),\n+\tBCM6348_PIN(25, \"gpio25\", 1),\n+\tBCM6348_PIN(26, \"gpio26\", 1),\n+\tBCM6348_PIN(27, \"gpio27\", 1),\n+\tBCM6348_PIN(28, \"gpio28\", 1),\n+\tBCM6348_PIN(29, \"gpio29\", 1),\n+\tBCM6348_PIN(30, \"gpio30\", 1),\n+\tBCM6348_PIN(31, \"gpio31\", 1),\n+\tBCM6348_PIN(32, \"gpio32\", 0),\n+\tBCM6348_PIN(33, \"gpio33\", 0),\n+\tBCM6348_PIN(34, \"gpio34\", 0),\n+\tBCM6348_PIN(35, \"gpio35\", 0),\n+\tBCM6348_PIN(36, \"gpio36\", 0),\n+};\n+\n+enum bcm6348_muxes {\n+\tBCM6348_MUX_GPIO = 0,\n+\tBCM6348_MUX_EXT_EPHY,\n+\tBCM6348_MUX_MII_SNOOP,\n+\tBCM6348_MUX_LEGACY_LED,\n+\tBCM6348_MUX_MII_PCCARD,\n+\tBCM6348_MUX_PCI,\n+\tBCM6348_MUX_SPI_MASTER_UART,\n+\tBCM6348_MUX_EXT_MII,\n+\tBCM6348_MUX_UTOPIA,\n+\tBCM6348_MUX_DIAG,\n+};\n+\n+static unsigned group0_pins[] = {\n+\t32, 33, 34, 35, 36,\n+};\n+\n+static unsigned group1_pins[] = {\n+\t22, 23, 24, 25, 26, 27, 28, 29, 30, 31,\n+};\n+\n+static unsigned group2_pins[] = {\n+\t16, 17, 18, 19, 20, 21,\n+};\n+\n+static unsigned group3_pins[] = {\n+\t8, 9, 10, 11, 12, 13, 14, 15,\n+};\n+\n+static unsigned group4_pins[] = {\n+\t0, 1, 2, 3, 4, 5, 6, 7,\n+};\n+\n+#define BCM6348_GROUP(n)\t\t\t\t\\\n+\t{\t\t\t\t\t\t\\\n+\t\t.name = #n,\t\t\t\t\\\n+\t\t.pins = n##_pins,\t\t\t\\\n+\t\t.num_pins = ARRAY_SIZE(n##_pins),\t\\\n+\t} \\\n+\n+static struct bcm6348_pingroup bcm6348_groups[] = {\n+\tBCM6348_GROUP(group0),\n+\tBCM6348_GROUP(group1),\n+\tBCM6348_GROUP(group2),\n+\tBCM6348_GROUP(group3),\n+\tBCM6348_GROUP(group4),\n+};\n+\n+static const char * const ext_mii_groups[] = {\n+\t\"group0\",\n+\t\"group3\",\n+};\n+\n+static const char * const ext_ephy_groups[] = {\n+\t\"group1\",\n+\t\"group4\"\n+};\n+\n+static const char * const mii_snoop_groups[] = {\n+\t\"group1\",\n+\t\"group4\",\n+};\n+\n+static const char * const legacy_led_groups[] = {\n+\t\"group4\",\n+};\n+\n+static const char * const mii_pccard_groups[] = {\n+\t\"group1\",\n+};\n+\n+static const char * const pci_groups[] = {\n+\t\"group2\",\n+};\n+\n+static const char * const spi_master_uart_groups[] = {\n+\t\"group1\",\n+};\n+\n+static const char * const utopia_groups[] = {\n+\t\"group1\",\n+\t\"group3\",\n+\t\"group4\",\n+};\n+\n+static const char * const diag_groups[] = {\n+\t\"group0\",\n+\t\"group1\",\n+\t\"group2\",\n+\t\"group3\",\n+\t\"group4\",\n+};\n+\n+#define BCM6348_FUN(n, f)\t\t\t\t\\\n+\t{\t\t\t\t\t\t\\\n+\t\t.name = #n,\t\t\t\t\\\n+\t\t.groups = n##_groups,\t\t\t\\\n+\t\t.num_groups = ARRAY_SIZE(n##_groups),\t\\\n+\t\t.value = BCM6348_MUX_##f,\t\t\\\n+\t}\n+\n+static const struct bcm6348_function bcm6348_funcs[] = {\n+\tBCM6348_FUN(ext_mii, EXT_MII),\n+\tBCM6348_FUN(ext_ephy, EXT_EPHY),\n+\tBCM6348_FUN(mii_snoop, MII_SNOOP),\n+\tBCM6348_FUN(legacy_led, LEGACY_LED),\n+\tBCM6348_FUN(mii_pccard, MII_PCCARD),\n+\tBCM6348_FUN(pci, PCI),\n+\tBCM6348_FUN(spi_master_uart, SPI_MASTER_UART),\n+\tBCM6348_FUN(utopia, UTOPIA),\n+\tBCM6348_FUN(diag, DIAG),\n+};\n+\n+static int bcm6348_pinctrl_get_group_count(struct pinctrl_dev *pctldev)\n+{\n+\treturn ARRAY_SIZE(bcm6348_groups);\n+}\n+\n+static const char *bcm6348_pinctrl_get_group_name(struct pinctrl_dev *pctldev,\n+\t\t\t\t\t\t  unsigned group)\n+{\n+\treturn bcm6348_groups[group].name;\n+}\n+\n+static int bcm6348_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,\n+\t\t\t\t\t  unsigned group, const unsigned **pins,\n+\t\t\t\t\t  unsigned *num_pins)\n+{\n+\t*pins = bcm6348_groups[group].pins;\n+\t*num_pins = bcm6348_groups[group].num_pins;\n+\n+\treturn 0;\n+}\n+\n+static int bcm6348_pinctrl_get_func_count(struct pinctrl_dev *pctldev)\n+{\n+\treturn ARRAY_SIZE(bcm6348_funcs);\n+}\n+\n+static const char *bcm6348_pinctrl_get_func_name(struct pinctrl_dev *pctldev,\n+\t\t\t\t\t\t unsigned selector)\n+{\n+\treturn bcm6348_funcs[selector].name;\n+}\n+\n+static int bcm6348_pinctrl_get_groups(struct pinctrl_dev *pctldev,\n+\t\t\t\t      unsigned selector,\n+\t\t\t\t      const char * const **groups,\n+\t\t\t\t      unsigned * const num_groups)\n+{\n+\t*groups = bcm6348_funcs[selector].groups;\n+\t*num_groups = bcm6348_funcs[selector].num_groups;\n+\n+\treturn 0;\n+}\n+\n+static void bcm6348_rmw_mux(struct bcm6348_pinctrl *pctl, u32 mask, u32 val)\n+{\n+\tunsigned long flags;\n+\tu32 reg;\n+\n+\tspin_lock_irqsave(&pctl->lock, flags);\n+\n+\treg = __raw_readl(pctl->mode);\n+\treg &= ~mask;\n+\treg |= val & mask;\n+\t__raw_writel(reg, pctl->mode);\n+\n+\tspin_unlock_irqrestore(&pctl->lock, flags);\n+}\n+\n+static int bcm6348_pinctrl_set_mux(struct pinctrl_dev *pctldev,\n+\t\t\t\t   unsigned selector, unsigned group)\n+{\n+\tstruct bcm6348_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);\n+\tconst struct bcm6348_pingroup *grp = &bcm6348_groups[group];\n+\tconst struct bcm6348_function *f = &bcm6348_funcs[selector];\n+\tu32 mask, val;\n+\n+\t/*\n+\t * pins n..(n+7) share the same group, so we only need to look at\n+\t * the first pin.\n+\t */\n+\tmask = GROUP_MASK(grp->pins[0]);\n+\tval = f->value << GROUP_SHIFT(grp->pins[0]);\n+\n+\tbcm6348_rmw_mux(pctl, mask, val);\n+\n+\treturn 0;\n+}\n+\n+static struct pinctrl_ops bcm6348_pctl_ops = {\n+\t.get_groups_count\t= bcm6348_pinctrl_get_group_count,\n+\t.get_group_name\t\t= bcm6348_pinctrl_get_group_name,\n+\t.get_group_pins\t\t= bcm6348_pinctrl_get_group_pins,\n+#ifdef CONFIG_OF\n+\t.dt_node_to_map\t\t= pinconf_generic_dt_node_to_map_pin,\n+\t.dt_free_map\t\t= pinctrl_utils_free_map,\n+#endif\n+};\n+\n+static struct pinmux_ops bcm6348_pmx_ops = {\n+\t.get_functions_count\t= bcm6348_pinctrl_get_func_count,\n+\t.get_function_name\t= bcm6348_pinctrl_get_func_name,\n+\t.get_function_groups\t= bcm6348_pinctrl_get_groups,\n+\t.set_mux\t\t= bcm6348_pinctrl_set_mux,\n+\t.strict\t\t\t= false,\n+};\n+\n+static int bcm6348_pinctrl_probe(struct platform_device *pdev)\n+{\n+\tstruct bcm6348_pinctrl *pctl;\n+\tstruct resource *res;\n+\tvoid __iomem *mode;\n+\n+\tres = platform_get_resource_byname(pdev, IORESOURCE_MEM, \"mode\");\n+\tmode = devm_ioremap_resource(&pdev->dev, res);\n+\tif (IS_ERR(mode))\n+\t\treturn PTR_ERR(mode);\n+\n+\tpctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);\n+\tif (!pctl)\n+\t\treturn -ENOMEM;\n+\n+\tspin_lock_init(&pctl->lock);\n+\n+\tpctl->mode = mode;\n+\n+\t/* disable all muxes by default */\n+\t__raw_writel(0, pctl->mode);\n+\n+\tpctl->desc.name = dev_name(&pdev->dev);\n+\tpctl->desc.owner = THIS_MODULE;\n+\tpctl->desc.pctlops = &bcm6348_pctl_ops;\n+\tpctl->desc.pmxops = &bcm6348_pmx_ops;\n+\n+\tpctl->desc.npins = ARRAY_SIZE(bcm6348_pins);\n+\tpctl->desc.pins = bcm6348_pins;\n+\n+\tplatform_set_drvdata(pdev, pctl);\n+\n+\tpctl->pctldev = bcm63xx_pinctrl_register(pdev, &pctl->desc, pctl,\n+\t\t\t\t\t\t pctl->gpio, BCM6348_NGPIO);\n+\tif (IS_ERR(pctl->pctldev))\n+\t\treturn PTR_ERR(pctl->pctldev);\n+\n+\treturn 0;\n+}\n+\n+static const struct of_device_id bcm6348_pinctrl_match[] = {\n+\t{ .compatible = \"brcm,bcm6348-pinctrl\", },\n+\t{ },\n+};\n+\n+static struct platform_driver bcm6348_pinctrl_driver = {\n+\t.probe = bcm6348_pinctrl_probe,\n+\t.driver = {\n+\t\t.name = \"bcm6348-pinctrl\",\n+\t\t.of_match_table = bcm6348_pinctrl_match,\n+\t},\n+};\n+\n+builtin_platform_driver(bcm6348_pinctrl_driver);\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/135-Documentation-add-BCM6358-pincontroller-binding-docu.patch",
    "content": "From c7c8fa7f5b5ee9bea751fa7bdae8ff4acde8f26e Mon Sep 17 00:00:00 2001\nFrom: Jonas Gorski <jonas.gorski@gmail.com>\nDate: Wed, 27 Jul 2016 11:36:00 +0200\nSubject: [PATCH 06/16] Documentation: add BCM6358 pincontroller binding\n documentation\n\nAdd binding documentation for the pincontrol core found in BCM6358 SoCs.\n\nSigned-off-by: Jonas Gorski <jonas.gorski@gmail.com>\n---\n .../bindings/pinctrl/brcm,bcm6358-pinctrl.txt      | 44 ++++++++++++++++++++++\n 1 file changed, 44 insertions(+)\n create mode 100644 Documentation/devicetree/bindings/pinctrl/brcm,bcm6358-pinctrl.txt\n\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/pinctrl/brcm,bcm6358-pinctrl.txt\n@@ -0,0 +1,44 @@\n+* Broadcom BCM6358 pin controller\n+\n+Required properties:\n+- compatible: Must be \"brcm,bcm6358-pinctrl\".\n+- reg: Register specifiers of dirout, dat registers.\n+- reg-names: Must be \"dirout\", \"dat\".\n+- brcm,gpiomode: Phandle to the shared gpiomode register.\n+- gpio-controller: Identifies this node as a gpio-controller.\n+- #gpio-cells: Must be <2>.\n+\n+Example:\n+\n+pinctrl: pin-controller@fffe0080 {\n+\tcompatible = \"brcm,bcm6358-pinctrl\";\n+\treg = <0xfffe0080 0x8>,\n+\t      <0xfffe0088 0x8>,\n+\t      <0xfffe0098 0x4>;\n+\treg-names = \"dirout\", \"dat\";\n+\tbrcm,gpiomode = <&gpiomode>;\n+\n+\tgpio-controller;\n+\t#gpio-cells = <2>;\n+};\n+\n+gpiomode: syscon@fffe0098 {\n+\tcompatible = \"brcm,bcm6358-gpiomode\", \"syscon\";\n+\treg = <0xfffe0098 0x4>;\n+\tnative-endian;\n+};\n+\n+Available pins/groups and functions:\n+\n+name\t\tpins\t\tfunctions\n+-----------------------------------------------------------\n+ebi_cs_grp\t30-31\t\tebi_cs\n+uart1_grp\t28-31\t\tuart1\n+spi_cs_grp\t32-33\t\tspi_cs\n+async_modem_grp\t12-15\t\tasync_modem\n+legacy_led_grp\t9-15\t\tlegacy_led\n+serial_led_grp\t6-7\t\tserial_led\n+led_grp\t\t0-3\t\tled\n+utopia_grp\t12-15, 22-31\tutopia\n+pwm_syn_clk_grp\t8\t\tpwm_syn_clk\n+sys_irq_grp\t5\t\tsys_irq\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/136-pinctrl-add-a-pincontrol-driver-for-BCM6358.patch",
    "content": "From fb00ef462f3f8b70ea8902151cc72810fe90b999 Mon Sep 17 00:00:00 2001\nFrom: Jonas Gorski <jonas.gorski@gmail.com>\nDate: Fri, 24 Jun 2016 22:16:01 +0200\nSubject: [PATCH 07/16] pinctrl: add a pincontrol driver for BCM6358\n\nAdd a pincotrol driver for BCM6358. BCM6358 allow overlaying different\nfunctions onto the GPIO pins. It does not support configuring individual\npins but only whole groups. These groups may overlap, and still require\nthe directions to be set correctly in the GPIO register. In addition the\nfunctions register controls other, not directly mux related functions.\n\nSigned-off-by: Jonas Gorski <jonas.gorski@gmail.com>\n---\n drivers/pinctrl/bcm63xx/Kconfig           |   8 +\n drivers/pinctrl/bcm63xx/Makefile          |   1 +\n drivers/pinctrl/bcm63xx/pinctrl-bcm6358.c | 393 ++++++++++++++++++++++++++++++\n 3 files changed, 402 insertions(+)\n create mode 100644 drivers/pinctrl/bcm63xx/pinctrl-bcm6358.c\n\n--- a/drivers/pinctrl/bcm63xx/Kconfig\n+++ b/drivers/pinctrl/bcm63xx/Kconfig\n@@ -15,3 +15,11 @@ config PINCTRL_BCM6348\n \tselect PINCONF\n \tselect PINCTRL_BCM63XX\n \tselect GENERIC_PINCONF\n+\n+config PINCTRL_BCM6358\n+\tbool \"BCM6358 pincontrol driver\" if COMPILE_TEST\n+\tselect PINMUX\n+\tselect PINCONF\n+\tselect PINCTRL_BCM63XX\n+\tselect GENERIC_PINCONF\n+\tselect MFD_SYSCON\n--- a/drivers/pinctrl/bcm63xx/Makefile\n+++ b/drivers/pinctrl/bcm63xx/Makefile\n@@ -1,3 +1,4 @@\n obj-$(CONFIG_PINCTRL_BCM63XX)\t+= pinctrl-bcm63xx.o\n obj-$(CONFIG_PINCTRL_BCM6328)\t+= pinctrl-bcm6328.o\n obj-$(CONFIG_PINCTRL_BCM6348)\t+= pinctrl-bcm6348.o\n+obj-$(CONFIG_PINCTRL_BCM6358)\t+= pinctrl-bcm6358.o\n--- /dev/null\n+++ b/drivers/pinctrl/bcm63xx/pinctrl-bcm6358.c\n@@ -0,0 +1,393 @@\n+/*\n+ * This file is subject to the terms and conditions of the GNU General Public\n+ * License.  See the file \"COPYING\" in the main directory of this archive\n+ * for more details.\n+ *\n+ * Copyright (C) 2016 Jonas Gorski <jonas.gorski@gmail.com>\n+ */\n+\n+#include <linux/kernel.h>\n+#include <linux/bitops.h>\n+#include <linux/gpio.h>\n+#include <linux/gpio/driver.h>\n+#include <linux/mfd/syscon.h>\n+#include <linux/of.h>\n+#include <linux/of_gpio.h>\n+#include <linux/of_address.h>\n+#include <linux/slab.h>\n+#include <linux/regmap.h>\n+#include <linux/platform_device.h>\n+\n+#include <linux/pinctrl/pinconf.h>\n+#include <linux/pinctrl/pinconf-generic.h>\n+#include <linux/pinctrl/pinmux.h>\n+#include <linux/pinctrl/machine.h>\n+\n+#include \"../core.h\"\n+#include \"../pinctrl-utils.h\"\n+\n+#include \"pinctrl-bcm63xx.h\"\n+\n+/* GPIO_MODE register */\n+#define BCM6358_MODE_MUX_NONE\t\t0\n+\n+/* overlays on gpio pins */\n+#define BCM6358_MODE_MUX_EBI_CS\t\tBIT(5)\n+#define BCM6358_MODE_MUX_UART1\t\tBIT(6)\n+#define BCM6358_MODE_MUX_SPI_CS\t\tBIT(7)\n+#define BCM6358_MODE_MUX_ASYNC_MODEM\tBIT(8)\n+#define BCM6358_MODE_MUX_LEGACY_LED\tBIT(9)\n+#define BCM6358_MODE_MUX_SERIAL_LED\tBIT(10)\n+#define BCM6358_MODE_MUX_LED\t\tBIT(11)\n+#define BCM6358_MODE_MUX_UTOPIA\t\tBIT(12)\n+#define BCM6358_MODE_MUX_CLKRST\t\tBIT(13)\n+#define BCM6358_MODE_MUX_PWM_SYN_CLK\tBIT(14)\n+#define BCM6358_MODE_MUX_SYS_IRQ\tBIT(15)\n+\n+#define BCM6358_NGPIO\t\t\t40\n+\n+struct bcm6358_pingroup {\n+\tconst char *name;\n+\tconst unsigned * const pins;\n+\tconst unsigned num_pins;\n+\n+\tconst u16 mode_val;\n+\n+\t/* non-GPIO function muxes require the gpio direction to be set */\n+\tconst u16 direction;\n+};\n+\n+struct bcm6358_function {\n+\tconst char *name;\n+\tconst char * const *groups;\n+\tconst unsigned num_groups;\n+};\n+\n+struct bcm6358_pinctrl {\n+\tstruct device *dev;\n+\tstruct pinctrl_dev *pctldev;\n+\tstruct pinctrl_desc desc;\n+\n+\tstruct regmap_field *overlays;\n+\n+\tstruct gpio_chip gpio[2];\n+};\n+\n+#define BCM6358_GPIO_PIN(a, b, bit1, bit2, bit3)\t\t\\\n+\t{\t\t\t\t\t\t\t\\\n+\t\t.number = a,\t\t\t\t\t\\\n+\t\t.name = b,\t\t\t\t\t\\\n+\t\t.drv_data = (void *)(BCM6358_MODE_MUX_##bit1 |\t\\\n+\t\t\t\t     BCM6358_MODE_MUX_##bit2 |\t\\\n+\t\t\t\t     BCM6358_MODE_MUX_##bit3),\t\\\n+\t}\n+\n+static const struct pinctrl_pin_desc bcm6358_pins[] = {\n+\tBCM6358_GPIO_PIN(0, \"gpio0\", LED, NONE, NONE),\n+\tBCM6358_GPIO_PIN(1, \"gpio1\", LED, NONE, NONE),\n+\tBCM6358_GPIO_PIN(2, \"gpio2\", LED, NONE, NONE),\n+\tBCM6358_GPIO_PIN(3, \"gpio3\", LED, NONE, NONE),\n+\tPINCTRL_PIN(4, \"gpio4\"),\n+\tBCM6358_GPIO_PIN(5, \"gpio5\", SYS_IRQ, NONE, NONE),\n+\tBCM6358_GPIO_PIN(6, \"gpio6\", SERIAL_LED, NONE, NONE),\n+\tBCM6358_GPIO_PIN(7, \"gpio7\", SERIAL_LED, NONE, NONE),\n+\tBCM6358_GPIO_PIN(8, \"gpio8\", PWM_SYN_CLK, NONE, NONE),\n+\tBCM6358_GPIO_PIN(9, \"gpio09\", LEGACY_LED, NONE, NONE),\n+\tBCM6358_GPIO_PIN(10, \"gpio10\", LEGACY_LED, NONE, NONE),\n+\tBCM6358_GPIO_PIN(11, \"gpio11\", LEGACY_LED, NONE, NONE),\n+\tBCM6358_GPIO_PIN(12, \"gpio12\", LEGACY_LED, ASYNC_MODEM, UTOPIA),\n+\tBCM6358_GPIO_PIN(13, \"gpio13\", LEGACY_LED, ASYNC_MODEM, UTOPIA),\n+\tBCM6358_GPIO_PIN(14, \"gpio14\", LEGACY_LED, ASYNC_MODEM, UTOPIA),\n+\tBCM6358_GPIO_PIN(15, \"gpio15\", LEGACY_LED, ASYNC_MODEM, UTOPIA),\n+\tPINCTRL_PIN(16, \"gpio16\"),\n+\tPINCTRL_PIN(17, \"gpio17\"),\n+\tPINCTRL_PIN(18, \"gpio18\"),\n+\tPINCTRL_PIN(19, \"gpio19\"),\n+\tPINCTRL_PIN(20, \"gpio20\"),\n+\tPINCTRL_PIN(21, \"gpio21\"),\n+\tBCM6358_GPIO_PIN(22, \"gpio22\", UTOPIA, NONE, NONE),\n+\tBCM6358_GPIO_PIN(23, \"gpio23\", UTOPIA, NONE, NONE),\n+\tBCM6358_GPIO_PIN(24, \"gpio24\", UTOPIA, NONE, NONE),\n+\tBCM6358_GPIO_PIN(25, \"gpio25\", UTOPIA, NONE, NONE),\n+\tBCM6358_GPIO_PIN(26, \"gpio26\", UTOPIA, NONE, NONE),\n+\tBCM6358_GPIO_PIN(27, \"gpio27\", UTOPIA, NONE, NONE),\n+\tBCM6358_GPIO_PIN(28, \"gpio28\", UTOPIA, UART1, NONE),\n+\tBCM6358_GPIO_PIN(29, \"gpio29\", UTOPIA, UART1, NONE),\n+\tBCM6358_GPIO_PIN(30, \"gpio30\", UTOPIA, UART1, EBI_CS),\n+\tBCM6358_GPIO_PIN(31, \"gpio31\", UTOPIA, UART1, EBI_CS),\n+\tBCM6358_GPIO_PIN(32, \"gpio32\", SPI_CS, NONE, NONE),\n+\tBCM6358_GPIO_PIN(33, \"gpio33\", SPI_CS, NONE, NONE),\n+\tPINCTRL_PIN(34, \"gpio34\"),\n+\tPINCTRL_PIN(35, \"gpio35\"),\n+\tPINCTRL_PIN(36, \"gpio36\"),\n+\tPINCTRL_PIN(37, \"gpio37\"),\n+\tPINCTRL_PIN(38, \"gpio38\"),\n+\tPINCTRL_PIN(39, \"gpio39\"),\n+};\n+\n+static unsigned ebi_cs_grp_pins[] = { 30, 31 };\n+\n+static unsigned uart1_grp_pins[] = { 28, 29, 30, 31 };\n+\n+static unsigned spi_cs_grp_pins[] = { 32, 33 };\n+\n+static unsigned async_modem_grp_pins[] = { 12, 13, 14, 15 };\n+\n+static unsigned serial_led_grp_pins[] = { 6, 7 };\n+\n+static unsigned legacy_led_grp_pins[] = { 9, 10, 11, 12, 13, 14, 15 };\n+\n+static unsigned led_grp_pins[] = { 0, 1, 2, 3 };\n+\n+static unsigned utopia_grp_pins[] = {\n+\t12, 13, 14, 15, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,\n+};\n+\n+static unsigned pwm_syn_clk_grp_pins[] = { 8 };\n+\n+static unsigned sys_irq_grp_pins[] = { 5 };\n+\n+#define BCM6358_GPIO_MUX_GROUP(n, bit, dir)\t\t\t\\\n+\t{\t\t\t\t\t\t\t\\\n+\t\t.name = #n,\t\t\t\t\t\\\n+\t\t.pins = n##_pins,\t\t\t\t\\\n+\t\t.num_pins = ARRAY_SIZE(n##_pins),\t\t\\\n+\t\t.mode_val = BCM6358_MODE_MUX_##bit,\t\t\\\n+\t\t.direction = dir,\t\t\t\t\\\n+\t}\n+\n+static const struct bcm6358_pingroup bcm6358_groups[] = {\n+\tBCM6358_GPIO_MUX_GROUP(ebi_cs_grp, EBI_CS, 0x3),\n+\tBCM6358_GPIO_MUX_GROUP(uart1_grp, UART1, 0x2),\n+\tBCM6358_GPIO_MUX_GROUP(spi_cs_grp, SPI_CS, 0x6),\n+\tBCM6358_GPIO_MUX_GROUP(async_modem_grp, ASYNC_MODEM, 0x6),\n+\tBCM6358_GPIO_MUX_GROUP(legacy_led_grp, LEGACY_LED, 0x7f),\n+\tBCM6358_GPIO_MUX_GROUP(serial_led_grp, SERIAL_LED, 0x3),\n+\tBCM6358_GPIO_MUX_GROUP(led_grp, LED, 0xf),\n+\tBCM6358_GPIO_MUX_GROUP(utopia_grp, UTOPIA, 0x000f),\n+\tBCM6358_GPIO_MUX_GROUP(pwm_syn_clk_grp, PWM_SYN_CLK, 0x1),\n+\tBCM6358_GPIO_MUX_GROUP(sys_irq_grp, SYS_IRQ, 0x1),\n+};\n+\n+static const char * const ebi_cs_groups[] = {\n+\t\"ebi_cs_grp\"\n+};\n+\n+static const char * const uart1_groups[] = {\n+\t\"uart1_grp\"\n+};\n+\n+static const char * const spi_cs_2_3_groups[] = {\n+\t\"spi_cs_2_3_grp\"\n+};\n+\n+static const char * const async_modem_groups[] = {\n+\t\"async_modem_grp\"\n+};\n+\n+static const char * const legacy_led_groups[] = {\n+\t\"legacy_led_grp\",\n+};\n+\n+static const char * const serial_led_groups[] = {\n+\t\"serial_led_grp\",\n+};\n+\n+static const char * const led_groups[] = {\n+\t\"led_grp\",\n+};\n+\n+static const char * const clkrst_groups[] = {\n+\t\"clkrst_grp\",\n+};\n+\n+static const char * const pwm_syn_clk_groups[] = {\n+\t\"pwm_syn_clk_grp\",\n+};\n+\n+static const char * const sys_irq_groups[] = {\n+\t\"sys_irq_grp\",\n+};\n+\n+#define BCM6358_FUN(n)\t\t\t\t\t\\\n+\t{\t\t\t\t\t\t\\\n+\t\t.name = #n,\t\t\t\t\\\n+\t\t.groups = n##_groups,\t\t\t\\\n+\t\t.num_groups = ARRAY_SIZE(n##_groups),\t\\\n+\t}\n+\n+static const struct bcm6358_function bcm6358_funcs[] = {\n+\tBCM6358_FUN(ebi_cs),\n+\tBCM6358_FUN(uart1),\n+\tBCM6358_FUN(spi_cs_2_3),\n+\tBCM6358_FUN(async_modem),\n+\tBCM6358_FUN(legacy_led),\n+\tBCM6358_FUN(serial_led),\n+\tBCM6358_FUN(led),\n+\tBCM6358_FUN(clkrst),\n+\tBCM6358_FUN(pwm_syn_clk),\n+\tBCM6358_FUN(sys_irq),\n+};\n+\n+static int bcm6358_pinctrl_get_group_count(struct pinctrl_dev *pctldev)\n+{\n+\treturn ARRAY_SIZE(bcm6358_groups);\n+}\n+\n+static const char *bcm6358_pinctrl_get_group_name(struct pinctrl_dev *pctldev,\n+\t\t\t\t\t\t  unsigned group)\n+{\n+\treturn bcm6358_groups[group].name;\n+}\n+\n+static int bcm6358_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,\n+\t\t\t\t\t  unsigned group, const unsigned **pins,\n+\t\t\t\t\t  unsigned *num_pins)\n+{\n+\t*pins = bcm6358_groups[group].pins;\n+\t*num_pins = bcm6358_groups[group].num_pins;\n+\n+\treturn 0;\n+}\n+\n+static int bcm6358_pinctrl_get_func_count(struct pinctrl_dev *pctldev)\n+{\n+\treturn ARRAY_SIZE(bcm6358_funcs);\n+}\n+\n+static const char *bcm6358_pinctrl_get_func_name(struct pinctrl_dev *pctldev,\n+\t\t\t\t\t\t unsigned selector)\n+{\n+\treturn bcm6358_funcs[selector].name;\n+}\n+\n+static int bcm6358_pinctrl_get_groups(struct pinctrl_dev *pctldev,\n+\t\t\t\t      unsigned selector,\n+\t\t\t\t      const char * const **groups,\n+\t\t\t\t      unsigned * const num_groups)\n+{\n+\t*groups = bcm6358_funcs[selector].groups;\n+\t*num_groups = bcm6358_funcs[selector].num_groups;\n+\n+\treturn 0;\n+}\n+\n+static int bcm6358_pinctrl_set_mux(struct pinctrl_dev *pctldev,\n+\t\t\t\t   unsigned selector, unsigned group)\n+{\n+\tstruct bcm6358_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);\n+\tconst struct bcm6358_pingroup *grp = &bcm6358_groups[group];\n+\tu32 val = grp->mode_val;\n+\tu32 mask = val;\n+\tunsigned pin;\n+\n+\tfor (pin = 0; pin < grp->num_pins; pin++)\n+\t\tmask |= (unsigned long)bcm6358_pins[pin].drv_data;\n+\n+\tregmap_field_update_bits(pctl->overlays, mask, val);\n+\n+\tfor (pin = 0; pin < grp->num_pins; pin++) {\n+\t\tint hw_gpio = bcm6358_pins[pin].number;\n+\t\tstruct gpio_chip *gc = &pctl->gpio[hw_gpio / 32];\n+\n+\t\tif (grp->direction & BIT(pin))\n+\t\t\tgc->direction_output(gc, hw_gpio % 32, 0);\n+\t\telse\n+\t\t\tgc->direction_input(gc, hw_gpio % 32);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int bcm6358_gpio_request_enable(struct pinctrl_dev *pctldev,\n+\t\t\t\t       struct pinctrl_gpio_range *range,\n+\t\t\t\t       unsigned offset)\n+{\n+\tstruct bcm6358_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);\n+\tu32 mask;\n+\n+\tmask = (unsigned long)bcm6358_pins[offset].drv_data;\n+\tif (!mask)\n+\t\treturn 0;\n+\n+\t/* disable all functions using this pin */\n+\treturn regmap_field_update_bits(pctl->overlays, mask, 0);\n+}\n+\n+static struct pinctrl_ops bcm6358_pctl_ops = {\n+\t.get_groups_count\t= bcm6358_pinctrl_get_group_count,\n+\t.get_group_name\t\t= bcm6358_pinctrl_get_group_name,\n+\t.get_group_pins\t\t= bcm6358_pinctrl_get_group_pins,\n+#ifdef CONFIG_OF\n+\t.dt_node_to_map\t\t= pinconf_generic_dt_node_to_map_pin,\n+\t.dt_free_map\t\t= pinctrl_utils_free_map,\n+#endif\n+};\n+\n+static struct pinmux_ops bcm6358_pmx_ops = {\n+\t.get_functions_count\t= bcm6358_pinctrl_get_func_count,\n+\t.get_function_name\t= bcm6358_pinctrl_get_func_name,\n+\t.get_function_groups\t= bcm6358_pinctrl_get_groups,\n+\t.set_mux\t\t= bcm6358_pinctrl_set_mux,\n+\t.gpio_request_enable\t= bcm6358_gpio_request_enable,\n+\t.strict\t\t\t= true,\n+};\n+\n+static int bcm6358_pinctrl_probe(struct platform_device *pdev)\n+{\n+\tstruct bcm6358_pinctrl *pctl;\n+\tstruct regmap *mode;\n+\tstruct reg_field overlays = REG_FIELD(0, 0, 15);\n+\n+\tif (pdev->dev.of_node)\n+\t\tmode = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,\n+\t\t\t\t\t\t       \"brcm,gpiomode\");\n+\telse\n+\t\tmode = syscon_regmap_lookup_by_pdevname(\"syscon.fffe0098\");\n+\n+\tif (IS_ERR(mode))\n+\t\treturn PTR_ERR(mode);\n+\n+\tpctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);\n+\tif (!pctl)\n+\t\treturn -ENOMEM;\n+\n+\tpctl->overlays = devm_regmap_field_alloc(&pdev->dev, mode, overlays);\n+\tif (IS_ERR(pctl->overlays))\n+\t\treturn PTR_ERR(pctl->overlays);\n+\n+\t/* disable all muxes by default */\n+\tregmap_field_write(pctl->overlays, 0);\n+\n+\tpctl->desc.name = dev_name(&pdev->dev);\n+\tpctl->desc.owner = THIS_MODULE;\n+\tpctl->desc.pctlops = &bcm6358_pctl_ops;\n+\tpctl->desc.pmxops = &bcm6358_pmx_ops;\n+\n+\tpctl->desc.npins = ARRAY_SIZE(bcm6358_pins);\n+\tpctl->desc.pins = bcm6358_pins;\n+\n+\tplatform_set_drvdata(pdev, pctl);\n+\n+\tpctl->pctldev = bcm63xx_pinctrl_register(pdev, &pctl->desc, pctl,\n+\t\t\t\t\t\t pctl->gpio, BCM6358_NGPIO);\n+\tif (IS_ERR(pctl->pctldev))\n+\t\treturn PTR_ERR(pctl->pctldev);\n+\n+\treturn 0;\n+}\n+\n+static const struct of_device_id bcm6358_pinctrl_match[] = {\n+\t{ .compatible = \"brcm,bcm6358-pinctrl\", },\n+\t{ },\n+};\n+\n+static struct platform_driver bcm6358_pinctrl_driver = {\n+\t.probe = bcm6358_pinctrl_probe,\n+\t.driver = {\n+\t\t.name = \"bcm6358-pinctrl\",\n+\t\t.of_match_table = bcm6358_pinctrl_match,\n+\t},\n+};\n+\n+builtin_platform_driver(bcm6358_pinctrl_driver);\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/137-Documentation-add-BCM6362-pincontroller-binding-docu.patch",
    "content": "From ba03ea8ada2ca71c9095d96a1e4085c2c5cf0e69 Mon Sep 17 00:00:00 2001\nFrom: Jonas Gorski <jonas.gorski@gmail.com>\nDate: Wed, 27 Jul 2016 11:36:18 +0200\nSubject: [PATCH 08/16] Documentation: add BCM6362 pincontroller binding\n documentation\n\nAdd binding documentation for the pincontrol core found in BCM6362 SoCs.\n\nSigned-off-by: Jonas Gorski <jonas.gorski@gmail.com>\n---\n .../bindings/pinctrl/brcm,bcm6362-pinctrl.txt      | 79 ++++++++++++++++++++++\n 1 file changed, 79 insertions(+)\n create mode 100644 Documentation/devicetree/bindings/pinctrl/brcm,bcm6362-pinctrl.txt\n\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/pinctrl/brcm,bcm6362-pinctrl.txt\n@@ -0,0 +1,79 @@\n+* Broadcom BCM6362 pin controller\n+\n+Required properties:\n+- compatible: Must be \"brcm,bcm6362-pinctrl\"\n+- reg: Register specifiers of dirout, dat, led, mode, ctrl, basemode registers.\n+- reg-names: Must be \"dirout\", \"dat\", \"led\", \"mode\", \"ctrl\", \"basemode\".\n+- gpio-controller: Identifies this node as a GPIO controller.\n+- #gpio-cells: Must be <2>.\n+\n+Example:\n+\n+pinctrl: pin-controller@10000080 {\n+\tcompatible = \"brcm,bcm6362-pinctrl\";\n+\treg = <0x10000080 0x8>,\n+\t      <0x10000088 0x8>,\n+\t      <0x10000090 0x4>,\n+\t      <0x10000098 0x4>,\n+\t      <0x1000009c 0x4>,\n+\t      <0x100000b8 0x4>;\n+\treg-names = \"dirout\", \"dat\", \"led\",\n+\t\t    \"mode\", \"ctrl\", \"basemode\";\n+\n+\tgpio-controller;\n+\t#gpio-cells = <2>;\n+};\n+\n+Available pins/groups and functions:\n+\n+name\t\tpins\t\tfunctions\n+-----------------------------------------------------------\n+gpio0\t\t0\t\tled, usb_device_led\n+gpio1\t\t1\t\tled, sys_irq\n+gpio2\t\t2\t\tled, serial_led_clk\n+gpio3\t\t3\t\tled, serial_led_data\n+gpio4\t\t4\t\tled, robosw_led_data\n+gpio5\t\t5\t\tled, robosw_led_clk\n+gpio6\t\t6\t\tled, robosw_led0\n+gpio7\t\t7\t\tled, robosw_led1\n+gpio8\t\t8\t\tled, inet_led\n+gpio9\t\t9\t\tled, spi_cs2\n+gpio10\t\t10\t\tled, spi_cs3\n+gpio11\t\t11\t\tled, ntr_pulse\n+gpio12\t\t12\t\tled, uart1_scts\n+gpio13\t\t13\t\tled, uart1_srts\n+gpio14\t\t14\t\tled, uart1_sdin\n+gpio15\t\t15\t\tled, uart1_sdout\n+gpio16\t\t16\t\tled, adsl_spi_miso\n+gpio17\t\t17\t\tled, adsl_spi_mosi\n+gpio18\t\t18\t\tled, adsl_spi_clk\n+gpio19\t\t19\t\tled, adsl_spi_cs\n+gpio20\t\t20\t\tled, ephy0_led\n+gpio21\t\t21\t\tled, ephy1_led\n+gpio22\t\t22\t\tled, ephy2_led\n+gpio23\t\t23\t\tled, ephy3_led\n+gpio24\t\t24\t\text_irq0\n+gpio25\t\t25\t\text_irq1\n+gpio26\t\t26\t\text_irq2\n+gpio27\t\t27\t\text_irq3\n+gpio28\t\t28\t\t-\n+gpio29\t\t29\t\t-\n+gpio30\t\t30\t\t-\n+gpio31\t\t31\t\t-\n+gpio32\t\t32\t\twifi\n+gpio33\t\t33\t\twifi\n+gpio34\t\t34\t\twifi\n+gpio35\t\t35\t\twifi\n+gpio36\t\t36\t\twifi\n+gpio37\t\t37\t\twifi\n+gpio38\t\t38\t\twifi\n+gpio39\t\t39\t\twifi\n+gpio40\t\t40\t\twifi\n+gpio41\t\t41\t\twifi\n+gpio42\t\t42\t\twifi\n+gpio43\t\t43\t\twifi\n+gpio44\t\t44\t\twifi\n+gpio45\t\t45\t\twifi\n+gpio46\t\t46\t\twifi\n+gpio47\t\t47\t\twifi\n+nand_grp\t8, 12-23, 27\tnand\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/138-pinctrl-add-a-pincontrol-driver-for-BCM6362.patch",
    "content": "From eea6b96701d734095e2f823f3a82d9b063f553ae Mon Sep 17 00:00:00 2001\nFrom: Jonas Gorski <jonas.gorski@gmail.com>\nDate: Fri, 24 Jun 2016 22:17:20 +0200\nSubject: [PATCH 09/16] pinctrl: add a pincontrol driver for BCM6362\n\nAdd a pincotrol driver for BCM6362. BCM6362 allows muxing individual\nGPIO pins to the LED controller, to be available by the integrated\nwifi, or other functions. It also supports overlay groups, of which\nonly NAND is documented.\n\nSigned-off-by: Jonas Gorski <jonas.gorski@gmail.com>\n---\n drivers/pinctrl/bcm63xx/Kconfig           |   7 +\n drivers/pinctrl/bcm63xx/Makefile          |   1 +\n drivers/pinctrl/bcm63xx/pinctrl-bcm6362.c | 692 ++++++++++++++++++++++++++++++\n 3 files changed, 700 insertions(+)\n create mode 100644 drivers/pinctrl/bcm63xx/pinctrl-bcm6362.c\n\n--- a/drivers/pinctrl/bcm63xx/Kconfig\n+++ b/drivers/pinctrl/bcm63xx/Kconfig\n@@ -23,3 +23,10 @@ config PINCTRL_BCM6358\n \tselect PINCTRL_BCM63XX\n \tselect GENERIC_PINCONF\n \tselect MFD_SYSCON\n+\n+config PINCTRL_BCM6362\n+\tbool \"BCM6362 pincontrol driver\" if COMPILE_TEST\n+\tselect PINMUX\n+\tselect PINCONF\n+\tselect PINCTRL_BCM63XX\n+\tselect GENERIC_PINCONF\n--- a/drivers/pinctrl/bcm63xx/Makefile\n+++ b/drivers/pinctrl/bcm63xx/Makefile\n@@ -2,3 +2,4 @@ obj-$(CONFIG_PINCTRL_BCM63XX)\t+= pinctrl\n obj-$(CONFIG_PINCTRL_BCM6328)\t+= pinctrl-bcm6328.o\n obj-$(CONFIG_PINCTRL_BCM6348)\t+= pinctrl-bcm6348.o\n obj-$(CONFIG_PINCTRL_BCM6358)\t+= pinctrl-bcm6358.o\n+obj-$(CONFIG_PINCTRL_BCM6362)\t+= pinctrl-bcm6362.o\n--- /dev/null\n+++ b/drivers/pinctrl/bcm63xx/pinctrl-bcm6362.c\n@@ -0,0 +1,692 @@\n+/*\n+ * This file is subject to the terms and conditions of the GNU General Public\n+ * License.  See the file \"COPYING\" in the main directory of this archive\n+ * for more details.\n+ *\n+ * Copyright (C) 2016 Jonas Gorski <jonas.gorski@gmail.com>\n+ */\n+\n+#include <linux/kernel.h>\n+#include <linux/spinlock.h>\n+#include <linux/bitops.h>\n+#include <linux/gpio.h>\n+#include <linux/of.h>\n+#include <linux/of_gpio.h>\n+#include <linux/slab.h>\n+#include <linux/platform_device.h>\n+\n+#include <linux/pinctrl/pinconf.h>\n+#include <linux/pinctrl/pinconf-generic.h>\n+#include <linux/pinctrl/pinmux.h>\n+#include <linux/pinctrl/machine.h>\n+\n+#include \"../core.h\"\n+#include \"../pinctrl-utils.h\"\n+\n+#include \"pinctrl-bcm63xx.h\"\n+\n+#define BCM6362_NGPIO\t48\n+\n+/* GPIO_BASEMODE register */\n+#define BASEMODE_NAND\tBIT(2)\n+\n+enum bcm6362_pinctrl_reg {\n+\tBCM6362_LEDCTRL,\n+\tBCM6362_MODE,\n+\tBCM6362_CTRL,\n+\tBCM6362_BASEMODE,\n+};\n+\n+struct bcm6362_pingroup {\n+\tconst char *name;\n+\tconst unsigned * const pins;\n+\tconst unsigned num_pins;\n+};\n+\n+struct bcm6362_function {\n+\tconst char *name;\n+\tconst char * const *groups;\n+\tconst unsigned num_groups;\n+\n+\tenum bcm6362_pinctrl_reg reg;\n+\tu32 basemode_mask;\n+};\n+\n+struct bcm6362_pinctrl {\n+\tstruct pinctrl_dev *pctldev;\n+\tstruct pinctrl_desc desc;\n+\n+\tvoid __iomem *led;\n+\tvoid __iomem *mode;\n+\tvoid __iomem *ctrl;\n+\tvoid __iomem *basemode;\n+\n+\t/* register access lock */\n+\tspinlock_t lock;\n+\n+\tstruct gpio_chip gpio[2];\n+};\n+\n+#define BCM6362_PIN(a, b, mask)\t\t\t\\\n+\t{\t\t\t\t\t\\\n+\t\t.number = a,\t\t\t\\\n+\t\t.name = b,\t\t\t\\\n+\t\t.drv_data = (void *)(mask),\t\\\n+\t}\n+\n+static const struct pinctrl_pin_desc bcm6362_pins[] = {\n+\tPINCTRL_PIN(0, \"gpio0\"),\n+\tPINCTRL_PIN(1, \"gpio1\"),\n+\tPINCTRL_PIN(2, \"gpio2\"),\n+\tPINCTRL_PIN(3, \"gpio3\"),\n+\tPINCTRL_PIN(4, \"gpio4\"),\n+\tPINCTRL_PIN(5, \"gpio5\"),\n+\tPINCTRL_PIN(6, \"gpio6\"),\n+\tPINCTRL_PIN(7, \"gpio7\"),\n+\tBCM6362_PIN(8, \"gpio8\", BASEMODE_NAND),\n+\tPINCTRL_PIN(9, \"gpio9\"),\n+\tPINCTRL_PIN(10, \"gpio10\"),\n+\tPINCTRL_PIN(11, \"gpio11\"),\n+\tBCM6362_PIN(12, \"gpio12\", BASEMODE_NAND),\n+\tBCM6362_PIN(13, \"gpio13\", BASEMODE_NAND),\n+\tBCM6362_PIN(14, \"gpio14\", BASEMODE_NAND),\n+\tBCM6362_PIN(15, \"gpio15\", BASEMODE_NAND),\n+\tBCM6362_PIN(16, \"gpio16\", BASEMODE_NAND),\n+\tBCM6362_PIN(17, \"gpio17\", BASEMODE_NAND),\n+\tBCM6362_PIN(18, \"gpio18\", BASEMODE_NAND),\n+\tBCM6362_PIN(19, \"gpio19\", BASEMODE_NAND),\n+\tBCM6362_PIN(20, \"gpio20\", BASEMODE_NAND),\n+\tBCM6362_PIN(21, \"gpio21\", BASEMODE_NAND),\n+\tBCM6362_PIN(22, \"gpio22\", BASEMODE_NAND),\n+\tBCM6362_PIN(23, \"gpio23\", BASEMODE_NAND),\n+\tPINCTRL_PIN(24, \"gpio24\"),\n+\tPINCTRL_PIN(25, \"gpio25\"),\n+\tPINCTRL_PIN(26, \"gpio26\"),\n+\tBCM6362_PIN(27, \"gpio27\", BASEMODE_NAND),\n+\tPINCTRL_PIN(28, \"gpio28\"),\n+\tPINCTRL_PIN(29, \"gpio29\"),\n+\tPINCTRL_PIN(30, \"gpio30\"),\n+\tPINCTRL_PIN(31, \"gpio31\"),\n+\tPINCTRL_PIN(32, \"gpio32\"),\n+\tPINCTRL_PIN(33, \"gpio33\"),\n+\tPINCTRL_PIN(34, \"gpio34\"),\n+\tPINCTRL_PIN(35, \"gpio35\"),\n+\tPINCTRL_PIN(36, \"gpio36\"),\n+\tPINCTRL_PIN(37, \"gpio37\"),\n+\tPINCTRL_PIN(38, \"gpio38\"),\n+\tPINCTRL_PIN(39, \"gpio39\"),\n+\tPINCTRL_PIN(40, \"gpio40\"),\n+\tPINCTRL_PIN(41, \"gpio41\"),\n+\tPINCTRL_PIN(42, \"gpio42\"),\n+\tPINCTRL_PIN(43, \"gpio43\"),\n+\tPINCTRL_PIN(44, \"gpio44\"),\n+\tPINCTRL_PIN(45, \"gpio45\"),\n+\tPINCTRL_PIN(46, \"gpio46\"),\n+\tPINCTRL_PIN(47, \"gpio47\"),\n+};\n+\n+static unsigned gpio0_pins[] = { 0 };\n+static unsigned gpio1_pins[] = { 1 };\n+static unsigned gpio2_pins[] = { 2 };\n+static unsigned gpio3_pins[] = { 3 };\n+static unsigned gpio4_pins[] = { 4 };\n+static unsigned gpio5_pins[] = { 5 };\n+static unsigned gpio6_pins[] = { 6 };\n+static unsigned gpio7_pins[] = { 7 };\n+static unsigned gpio8_pins[] = { 8 };\n+static unsigned gpio9_pins[] = { 9 };\n+static unsigned gpio10_pins[] = { 10 };\n+static unsigned gpio11_pins[] = { 11 };\n+static unsigned gpio12_pins[] = { 12 };\n+static unsigned gpio13_pins[] = { 13 };\n+static unsigned gpio14_pins[] = { 14 };\n+static unsigned gpio15_pins[] = { 15 };\n+static unsigned gpio16_pins[] = { 16 };\n+static unsigned gpio17_pins[] = { 17 };\n+static unsigned gpio18_pins[] = { 18 };\n+static unsigned gpio19_pins[] = { 19 };\n+static unsigned gpio20_pins[] = { 20 };\n+static unsigned gpio21_pins[] = { 21 };\n+static unsigned gpio22_pins[] = { 22 };\n+static unsigned gpio23_pins[] = { 23 };\n+static unsigned gpio24_pins[] = { 24 };\n+static unsigned gpio25_pins[] = { 25 };\n+static unsigned gpio26_pins[] = { 26 };\n+static unsigned gpio27_pins[] = { 27 };\n+static unsigned gpio28_pins[] = { 28 };\n+static unsigned gpio29_pins[] = { 29 };\n+static unsigned gpio30_pins[] = { 30 };\n+static unsigned gpio31_pins[] = { 31 };\n+static unsigned gpio32_pins[] = { 32 };\n+static unsigned gpio33_pins[] = { 33 };\n+static unsigned gpio34_pins[] = { 34 };\n+static unsigned gpio35_pins[] = { 35 };\n+static unsigned gpio36_pins[] = { 36 };\n+static unsigned gpio37_pins[] = { 37 };\n+static unsigned gpio38_pins[] = { 38 };\n+static unsigned gpio39_pins[] = { 39 };\n+static unsigned gpio40_pins[] = { 40 };\n+static unsigned gpio41_pins[] = { 41 };\n+static unsigned gpio42_pins[] = { 42 };\n+static unsigned gpio43_pins[] = { 43 };\n+static unsigned gpio44_pins[] = { 44 };\n+static unsigned gpio45_pins[] = { 45 };\n+static unsigned gpio46_pins[] = { 46 };\n+static unsigned gpio47_pins[] = { 47 };\n+\n+static unsigned nand_grp_pins[] = {\n+\t8, 12, 13, 14, 15, 16, 17,\n+\t18, 19, 20, 21, 22, 23, 27,\n+};\n+\n+#define BCM6362_GROUP(n)\t\t\t\t\\\n+\t{\t\t\t\t\t\t\\\n+\t\t.name = #n,\t\t\t\t\\\n+\t\t.pins = n##_pins,\t\t\t\\\n+\t\t.num_pins = ARRAY_SIZE(n##_pins),\t\\\n+\t}\n+\n+static struct bcm6362_pingroup bcm6362_groups[] = {\n+\tBCM6362_GROUP(gpio0),\n+\tBCM6362_GROUP(gpio1),\n+\tBCM6362_GROUP(gpio2),\n+\tBCM6362_GROUP(gpio3),\n+\tBCM6362_GROUP(gpio4),\n+\tBCM6362_GROUP(gpio5),\n+\tBCM6362_GROUP(gpio6),\n+\tBCM6362_GROUP(gpio7),\n+\tBCM6362_GROUP(gpio8),\n+\tBCM6362_GROUP(gpio9),\n+\tBCM6362_GROUP(gpio10),\n+\tBCM6362_GROUP(gpio11),\n+\tBCM6362_GROUP(gpio12),\n+\tBCM6362_GROUP(gpio13),\n+\tBCM6362_GROUP(gpio14),\n+\tBCM6362_GROUP(gpio15),\n+\tBCM6362_GROUP(gpio16),\n+\tBCM6362_GROUP(gpio17),\n+\tBCM6362_GROUP(gpio18),\n+\tBCM6362_GROUP(gpio19),\n+\tBCM6362_GROUP(gpio20),\n+\tBCM6362_GROUP(gpio21),\n+\tBCM6362_GROUP(gpio22),\n+\tBCM6362_GROUP(gpio23),\n+\tBCM6362_GROUP(gpio24),\n+\tBCM6362_GROUP(gpio25),\n+\tBCM6362_GROUP(gpio26),\n+\tBCM6362_GROUP(gpio27),\n+\tBCM6362_GROUP(gpio28),\n+\tBCM6362_GROUP(gpio29),\n+\tBCM6362_GROUP(gpio30),\n+\tBCM6362_GROUP(gpio31),\n+\tBCM6362_GROUP(gpio32),\n+\tBCM6362_GROUP(gpio33),\n+\tBCM6362_GROUP(gpio34),\n+\tBCM6362_GROUP(gpio35),\n+\tBCM6362_GROUP(gpio36),\n+\tBCM6362_GROUP(gpio37),\n+\tBCM6362_GROUP(gpio38),\n+\tBCM6362_GROUP(gpio39),\n+\tBCM6362_GROUP(gpio40),\n+\tBCM6362_GROUP(gpio41),\n+\tBCM6362_GROUP(gpio42),\n+\tBCM6362_GROUP(gpio43),\n+\tBCM6362_GROUP(gpio44),\n+\tBCM6362_GROUP(gpio45),\n+\tBCM6362_GROUP(gpio46),\n+\tBCM6362_GROUP(gpio47),\n+\tBCM6362_GROUP(nand_grp),\n+};\n+\n+static const char * const led_groups[] = {\n+\t\"gpio0\",\n+\t\"gpio1\",\n+\t\"gpio2\",\n+\t\"gpio3\",\n+\t\"gpio4\",\n+\t\"gpio5\",\n+\t\"gpio6\",\n+\t\"gpio7\",\n+\t\"gpio8\",\n+\t\"gpio9\",\n+\t\"gpio10\",\n+\t\"gpio11\",\n+\t\"gpio12\",\n+\t\"gpio13\",\n+\t\"gpio14\",\n+\t\"gpio15\",\n+\t\"gpio16\",\n+\t\"gpio17\",\n+\t\"gpio18\",\n+\t\"gpio19\",\n+\t\"gpio20\",\n+\t\"gpio21\",\n+\t\"gpio22\",\n+\t\"gpio23\",\n+};\n+\n+static const char * const usb_device_led_groups[] = {\n+\t\"gpio0\",\n+};\n+\n+static const char * const sys_irq_groups[] = {\n+\t\"gpio1\",\n+};\n+\n+static const char * const serial_led_clk_groups[] = {\n+\t\"gpio2\",\n+};\n+\n+static const char * const serial_led_data_groups[] = {\n+\t\"gpio3\",\n+};\n+\n+static const char * const robosw_led_data_groups[] = {\n+\t\"gpio4\",\n+};\n+\n+static const char * const robosw_led_clk_groups[] = {\n+\t\"gpio5\",\n+};\n+\n+static const char * const robosw_led0_groups[] = {\n+\t\"gpio6\",\n+};\n+\n+static const char * const robosw_led1_groups[] = {\n+\t\"gpio7\",\n+};\n+\n+static const char * const inet_led_groups[] = {\n+\t\"gpio8\",\n+};\n+\n+static const char * const spi_cs2_groups[] = {\n+\t\"gpio9\",\n+};\n+\n+static const char * const spi_cs3_groups[] = {\n+\t\"gpio10\",\n+};\n+\n+static const char * const ntr_pulse_groups[] = {\n+\t\"gpio11\",\n+};\n+\n+static const char * const uart1_scts_groups[] = {\n+\t\"gpio12\",\n+};\n+\n+static const char * const uart1_srts_groups[] = {\n+\t\"gpio13\",\n+};\n+\n+static const char * const uart1_sdin_groups[] = {\n+\t\"gpio14\",\n+};\n+\n+static const char * const uart1_sdout_groups[] = {\n+\t\"gpio15\",\n+};\n+\n+static const char * const adsl_spi_miso_groups[] = {\n+\t\"gpio16\",\n+};\n+\n+static const char * const adsl_spi_mosi_groups[] = {\n+\t\"gpio17\",\n+};\n+\n+static const char * const adsl_spi_clk_groups[] = {\n+\t\"gpio18\",\n+};\n+\n+static const char * const adsl_spi_cs_groups[] = {\n+\t\"gpio19\",\n+};\n+\n+static const char * const ephy0_led_groups[] = {\n+\t\"gpio20\",\n+};\n+\n+static const char * const ephy1_led_groups[] = {\n+\t\"gpio21\",\n+};\n+\n+static const char * const ephy2_led_groups[] = {\n+\t\"gpio22\",\n+};\n+\n+static const char * const ephy3_led_groups[] = {\n+\t\"gpio23\",\n+};\n+\n+static const char * const ext_irq0_groups[] = {\n+\t\"gpio24\",\n+};\n+\n+static const char * const ext_irq1_groups[] = {\n+\t\"gpio25\",\n+};\n+\n+static const char * const ext_irq2_groups[] = {\n+\t\"gpio26\",\n+};\n+\n+static const char * const ext_irq3_groups[] = {\n+\t\"gpio27\",\n+};\n+\n+static const char * const wifi_groups[] = {\n+\t\"gpio32\",\n+\t\"gpio33\",\n+\t\"gpio34\",\n+\t\"gpio35\",\n+\t\"gpio36\",\n+\t\"gpio37\",\n+\t\"gpio38\",\n+\t\"gpio39\",\n+\t\"gpio40\",\n+\t\"gpio41\",\n+\t\"gpio42\",\n+\t\"gpio43\",\n+\t\"gpio44\",\n+\t\"gpio45\",\n+\t\"gpio46\",\n+\t\"gpio47\",\n+};\n+\n+static const char * const nand_groups[] = {\n+\t\"nand_grp\",\n+};\n+\n+#define BCM6362_LED_FUN(n)\t\t\t\t\\\n+\t{\t\t\t\t\t\t\\\n+\t\t.name = #n,\t\t\t\t\\\n+\t\t.groups = n##_groups,\t\t\t\\\n+\t\t.num_groups = ARRAY_SIZE(n##_groups),\t\\\n+\t\t.reg = BCM6362_LEDCTRL,\t\t\t\\\n+\t}\n+\n+#define BCM6362_MODE_FUN(n)\t\t\t\t\\\n+\t{\t\t\t\t\t\t\\\n+\t\t.name = #n,\t\t\t\t\\\n+\t\t.groups = n##_groups,\t\t\t\\\n+\t\t.num_groups = ARRAY_SIZE(n##_groups),\t\\\n+\t\t.reg = BCM6362_MODE,\t\t\t\\\n+\t}\n+\n+#define BCM6362_CTRL_FUN(n)\t\t\t\t\\\n+\t{\t\t\t\t\t\t\\\n+\t\t.name = #n,\t\t\t\t\\\n+\t\t.groups = n##_groups,\t\t\t\\\n+\t\t.num_groups = ARRAY_SIZE(n##_groups),\t\\\n+\t\t.reg = BCM6362_CTRL,\t\t\t\\\n+\t}\n+\n+#define BCM6362_BASEMODE_FUN(n, mask)\t\t\t\\\n+\t{\t\t\t\t\t\t\\\n+\t\t.name = #n,\t\t\t\t\\\n+\t\t.groups = n##_groups,\t\t\t\\\n+\t\t.num_groups = ARRAY_SIZE(n##_groups),\t\\\n+\t\t.reg = BCM6362_BASEMODE,\t\t\\\n+\t\t.basemode_mask = (mask),\t\t\\\n+\t}\n+\n+static const struct bcm6362_function bcm6362_funcs[] = {\n+\tBCM6362_LED_FUN(led),\n+\tBCM6362_MODE_FUN(usb_device_led),\n+\tBCM6362_MODE_FUN(sys_irq),\n+\tBCM6362_MODE_FUN(serial_led_clk),\n+\tBCM6362_MODE_FUN(serial_led_data),\n+\tBCM6362_MODE_FUN(robosw_led_data),\n+\tBCM6362_MODE_FUN(robosw_led_clk),\n+\tBCM6362_MODE_FUN(robosw_led0),\n+\tBCM6362_MODE_FUN(robosw_led1),\n+\tBCM6362_MODE_FUN(inet_led),\n+\tBCM6362_MODE_FUN(spi_cs2),\n+\tBCM6362_MODE_FUN(spi_cs3),\n+\tBCM6362_MODE_FUN(ntr_pulse),\n+\tBCM6362_MODE_FUN(uart1_scts),\n+\tBCM6362_MODE_FUN(uart1_srts),\n+\tBCM6362_MODE_FUN(uart1_sdin),\n+\tBCM6362_MODE_FUN(uart1_sdout),\n+\tBCM6362_MODE_FUN(adsl_spi_miso),\n+\tBCM6362_MODE_FUN(adsl_spi_mosi),\n+\tBCM6362_MODE_FUN(adsl_spi_clk),\n+\tBCM6362_MODE_FUN(adsl_spi_cs),\n+\tBCM6362_MODE_FUN(ephy0_led),\n+\tBCM6362_MODE_FUN(ephy1_led),\n+\tBCM6362_MODE_FUN(ephy2_led),\n+\tBCM6362_MODE_FUN(ephy3_led),\n+\tBCM6362_MODE_FUN(ext_irq0),\n+\tBCM6362_MODE_FUN(ext_irq1),\n+\tBCM6362_MODE_FUN(ext_irq2),\n+\tBCM6362_MODE_FUN(ext_irq3),\n+\tBCM6362_CTRL_FUN(wifi),\n+\tBCM6362_BASEMODE_FUN(nand, BASEMODE_NAND),\n+};\n+\n+static int bcm6362_pinctrl_get_group_count(struct pinctrl_dev *pctldev)\n+{\n+\treturn ARRAY_SIZE(bcm6362_groups);\n+}\n+\n+static const char *bcm6362_pinctrl_get_group_name(struct pinctrl_dev *pctldev,\n+\t\t\t\t\t\t  unsigned group)\n+{\n+\treturn bcm6362_groups[group].name;\n+}\n+\n+static int bcm6362_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,\n+\t\t\t\t\t  unsigned group, const unsigned **pins,\n+\t\t\t\t\t  unsigned *num_pins)\n+{\n+\t*pins = bcm6362_groups[group].pins;\n+\t*num_pins = bcm6362_groups[group].num_pins;\n+\n+\treturn 0;\n+}\n+\n+static int bcm6362_pinctrl_get_func_count(struct pinctrl_dev *pctldev)\n+{\n+\treturn ARRAY_SIZE(bcm6362_funcs);\n+}\n+\n+static const char *bcm6362_pinctrl_get_func_name(struct pinctrl_dev *pctldev,\n+\t\t\t\t\t\t unsigned selector)\n+{\n+\treturn bcm6362_funcs[selector].name;\n+}\n+\n+static int bcm6362_pinctrl_get_groups(struct pinctrl_dev *pctldev,\n+\t\t\t\t      unsigned selector,\n+\t\t\t\t      const char * const **groups,\n+\t\t\t\t      unsigned * const num_groups)\n+{\n+\t*groups = bcm6362_funcs[selector].groups;\n+\t*num_groups = bcm6362_funcs[selector].num_groups;\n+\n+\treturn 0;\n+}\n+\n+static void bcm6362_rmw_mux(struct bcm6362_pinctrl *pctl, void __iomem *reg,\n+\t\t\t    u32 mask, u32 val)\n+{\n+\tunsigned long flags;\n+\tu32 tmp;\n+\n+\tspin_lock_irqsave(&pctl->lock, flags);\n+\ttmp = __raw_readl(reg);\n+\ttmp &= ~mask;\n+\ttmp |= val & mask;\n+\t__raw_writel(tmp, reg);\n+\n+\tspin_unlock_irqrestore(&pctl->lock, flags);\n+}\n+\n+static void bcm6362_set_gpio(struct bcm6362_pinctrl *pctl, unsigned pin)\n+{\n+\tconst struct pinctrl_pin_desc *desc = &bcm6362_pins[pin];\n+\tu32 mask = BIT(pin % 32);\n+\n+\tif (desc->drv_data)\n+\t\tbcm6362_rmw_mux(pctl, pctl->basemode, (u32)desc->drv_data, 0);\n+\n+\tif (pin < 32) {\n+\t\t/* base mode 0 => gpio 1 => mux function */\n+\t\tbcm6362_rmw_mux(pctl, pctl->mode, mask, 0);\n+\n+\t\t/* pins 0-23 might be muxed to led */\n+\t\tif (pin < 24)\n+\t\t\tbcm6362_rmw_mux(pctl, pctl->led, mask, 0);\n+\t} else {\n+\t\t/* ctrl reg 0 => wifi function 1 => gpio */\n+\t\tbcm6362_rmw_mux(pctl, pctl->ctrl, mask, mask);\n+\t}\n+}\n+\n+static int bcm6362_pinctrl_set_mux(struct pinctrl_dev *pctldev,\n+\t\t\t\t   unsigned selector, unsigned group)\n+{\n+\tstruct bcm6362_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);\n+\tconst struct bcm6362_pingroup *grp = &bcm6362_groups[group];\n+\tconst struct bcm6362_function *f = &bcm6362_funcs[selector];\n+\tunsigned i;\n+\tvoid __iomem *reg;\n+\tu32 val, mask;\n+\n+\tfor (i = 0; i < grp->num_pins; i++)\n+\t\tbcm6362_set_gpio(pctl, grp->pins[i]);\n+\n+\tswitch (f->reg) {\n+\tcase BCM6362_LEDCTRL:\n+\t\treg = pctl->led;\n+\t\tmask = BIT(grp->pins[0]);\n+\t\tval = BIT(grp->pins[0]);\n+\t\tbreak;\n+\tcase BCM6362_MODE:\n+\t\treg = pctl->ctrl;\n+\t\tmask = BIT(grp->pins[0]);\n+\t\tval = BIT(grp->pins[0]);\n+\t\tbreak;\n+\tcase BCM6362_CTRL:\n+\t\treg = pctl->ctrl;\n+\t\tmask = BIT(grp->pins[0]);\n+\t\tval = 0;\n+\t\tbreak;\n+\tcase BCM6362_BASEMODE:\n+\t\treg = pctl->basemode;\n+\t\tmask = f->basemode_mask;\n+\t\tval = f->basemode_mask;\n+\t\tbreak;\n+\tdefault:\n+\t\tWARN_ON(1);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tbcm6362_rmw_mux(pctl, reg, mask, val);\n+\n+\treturn 0;\n+}\n+\n+static int bcm6362_gpio_request_enable(struct pinctrl_dev *pctldev,\n+\t\t\t\t       struct pinctrl_gpio_range *range,\n+\t\t\t\t       unsigned offset)\n+{\n+\tstruct bcm6362_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);\n+\n+\t/* disable all functions using this pin */\n+\tbcm6362_set_gpio(pctl, offset);\n+\n+\treturn 0;\n+}\n+\n+static struct pinctrl_ops bcm6362_pctl_ops = {\n+\t.get_groups_count\t= bcm6362_pinctrl_get_group_count,\n+\t.get_group_name\t\t= bcm6362_pinctrl_get_group_name,\n+\t.get_group_pins\t\t= bcm6362_pinctrl_get_group_pins,\n+#ifdef CONFIG_OF\n+\t.dt_node_to_map\t\t= pinconf_generic_dt_node_to_map_pin,\n+\t.dt_free_map\t\t= pinctrl_utils_free_map,\n+#endif\n+};\n+\n+static struct pinmux_ops bcm6362_pmx_ops = {\n+\t.get_functions_count\t= bcm6362_pinctrl_get_func_count,\n+\t.get_function_name\t= bcm6362_pinctrl_get_func_name,\n+\t.get_function_groups\t= bcm6362_pinctrl_get_groups,\n+\t.set_mux\t\t= bcm6362_pinctrl_set_mux,\n+\t.gpio_request_enable\t= bcm6362_gpio_request_enable,\n+\t.strict\t\t\t= true,\n+};\n+\n+static int bcm6362_pinctrl_probe(struct platform_device *pdev)\n+{\n+\tstruct bcm6362_pinctrl *pctl;\n+\tstruct resource *res;\n+\tvoid __iomem *led, *mode, *ctrl, *basemode;\n+\n+\tres = platform_get_resource_byname(pdev, IORESOURCE_MEM, \"led\");\n+\tled = devm_ioremap_resource(&pdev->dev, res);\n+\tif (IS_ERR(led))\n+\t\treturn PTR_ERR(led);\n+\n+\tres = platform_get_resource_byname(pdev, IORESOURCE_MEM, \"mode\");\n+\tmode = devm_ioremap_resource(&pdev->dev, res);\n+\tif (IS_ERR(mode))\n+\t\treturn PTR_ERR(mode);\n+\n+\tres = platform_get_resource_byname(pdev, IORESOURCE_MEM, \"ctrl\");\n+\tctrl = devm_ioremap_resource(&pdev->dev, res);\n+\tif (IS_ERR(ctrl))\n+\t\treturn PTR_ERR(ctrl);\n+\n+\tres = platform_get_resource_byname(pdev, IORESOURCE_MEM, \"basemode\");\n+\tbasemode = devm_ioremap_resource(&pdev->dev, res);\n+\tif (IS_ERR(basemode))\n+\t\treturn PTR_ERR(basemode);\n+\n+\tpctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);\n+\tif (!pctl)\n+\t\treturn -ENOMEM;\n+\n+\tspin_lock_init(&pctl->lock);\n+\n+\tpctl->led = led;\n+\tpctl->mode = mode;\n+\tpctl->ctrl = ctrl;\n+\tpctl->basemode = basemode;\n+\n+\tpctl->desc.name = dev_name(&pdev->dev);\n+\tpctl->desc.owner = THIS_MODULE;\n+\tpctl->desc.pctlops = &bcm6362_pctl_ops;\n+\tpctl->desc.pmxops = &bcm6362_pmx_ops;\n+\n+\tpctl->desc.npins = ARRAY_SIZE(bcm6362_pins);\n+\tpctl->desc.pins = bcm6362_pins;\n+\n+\tplatform_set_drvdata(pdev, pctl);\n+\n+\tpctl->pctldev = bcm63xx_pinctrl_register(pdev, &pctl->desc, pctl,\n+\t\t\t\t\t\t pctl->gpio, BCM6362_NGPIO);\n+\tif (IS_ERR(pctl->pctldev))\n+\t\treturn PTR_ERR(pctl->pctldev);\n+\n+\treturn 0;\n+}\n+\n+static const struct of_device_id bcm6362_pinctrl_match[] = {\n+\t{ .compatible = \"brcm,bcm6362-pinctrl\", },\n+\t{ },\n+};\n+\n+static struct platform_driver bcm6362_pinctrl_driver = {\n+\t.probe = bcm6362_pinctrl_probe,\n+\t.driver = {\n+\t\t.name = \"bcm6362-pinctrl\",\n+\t\t.of_match_table = bcm6362_pinctrl_match,\n+\t},\n+};\n+\n+builtin_platform_driver(bcm6362_pinctrl_driver);\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/139-Documentation-add-BCM6368-pincontroller-binding-docu.patch",
    "content": "From 30594cf9bfff176a9e4b14c50dcd8b9d0cc3edec Mon Sep 17 00:00:00 2001\nFrom: Jonas Gorski <jonas.gorski@gmail.com>\nDate: Wed, 27 Jul 2016 11:36:51 +0200\nSubject: [PATCH 10/16] Documentation: add BCM6368 pincontroller binding\n documentation\n\nAdd binding documentation for the pincontrol core found in BCM6368 SoCs.\n\nSigned-off-by: Jonas Gorski <jonas.gorski@gmail.com>\n---\n .../bindings/pinctrl/brcm,bcm6368-pinctrl.txt      | 67 ++++++++++++++++++++++\n 1 file changed, 67 insertions(+)\n create mode 100644 Documentation/devicetree/bindings/pinctrl/brcm,bcm6368-pinctrl.txt\n\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/pinctrl/brcm,bcm6368-pinctrl.txt\n@@ -0,0 +1,67 @@\n+* Broadcom BCM6368 pin controller\n+\n+Required properties:\n+- compatible: Must be \"brcm,bcm6368-pinctrl\".\n+- reg: Register specifiers of dirout, dat, mode registers.\n+- reg-names: Must be \"dirout\", \"dat\", \"mode\".\n+- brcm,gpiobasemode: Phandle to the gpio basemode register.\n+- gpio-controller: Identifies this node as a GPIO controller.\n+- #gpio-cells: Must be <2>.\n+\n+Example:\n+\n+pinctrl: pin-controller@10000080 {\n+\tcompatible = \"brcm,bcm6368-pinctrl\";\n+\treg = <0x10000080 0x08>,\n+\t      <0x10000088 0x08>,\n+\t      <0x10000098 0x04>;\n+\treg-names = \"dirout\", \"dat\", \"mode\";\n+\tbrcm,gpiobasemode = <&gpiobasemode>;\n+\n+\tgpio-controller;\n+\t#gpio-cells = <2>;\n+};\n+\n+gpiobasemode: syscon@100000b8 {\n+\tcompatible = \"brcm,bcm6368-gpiobasemode\", \"syscon\";\n+\treg = <0x100000b8 4>;\n+\tnative-endian;\n+};\n+\n+Available pins/groups and functions:\n+\n+name\t\tpins\tfunctions\n+-----------------------------------------------------------\n+gpio0\t\t0\tanalog_afe0\n+gpio1\t\t1\tanalog_afe1\n+gpio2\t\t2\tsys_irq\n+gpio3\t\t3\tserial_led_data\n+gpio4\t\t4\tserial_led_clk\n+gpio5\t\t5\tinet_led\n+gpio6\t\t6\tephy0_led\n+gpio7\t\t7\tephy1_led\n+gpio8\t\t8\tephy2_led\n+gpio9\t\t9\tephy3_led\n+gpio10\t\t10\trobosw_led_data\n+gpio11\t\t11\trobosw_led_clk\n+gpio12\t\t12\trobosw_led0\n+gpio13\t\t13\trobosw_led1\n+gpio14\t\t14\tusb_device_led\n+gpio15\t\t15\t-\n+gpio16\t\t16\tpci_req1\n+gpio17\t\t17\tpci_gnt1\n+gpio18\t\t18\tpci_intb\n+gpio19\t\t19\tpci_req0\n+gpio20\t\t20\tpci_gnt0\n+gpio21\t\t21\t-\n+gpio22\t\t22\tpcmcia_cd1\n+gpio23\t\t23\tpcmcia_cd2\n+gpio24\t\t24\tpcmcia_vs1\n+gpio25\t\t25\tpcmcia_vs2\n+gpio26\t\t26\tebi_cs2\n+gpio27\t\t27\tebi_cs3\n+gpio28\t\t28\tspi_cs2\n+gpio29\t\t29\tspi_cs3\n+gpio30\t\t30\tspi_cs4\n+gpio31\t\t31\tspi_cs5\n+uart1_grp\t30-33\tuart1\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/140-pinctrl-add-a-pincontrol-driver-for-BCM6368.patch",
    "content": "From 90be3cb4f1a45b8be4a4ec264cd66c2f8e893fcb Mon Sep 17 00:00:00 2001\nFrom: Jonas Gorski <jonas.gorski@gmail.com>\nDate: Fri, 24 Jun 2016 22:18:25 +0200\nSubject: [PATCH 11/16] pinctrl: add a pincontrol driver for BCM6368\n\nAdd a pincontrol driver for BCM6368. BCM6368 allows muxing the first 32\nGPIOs onto alternative functions. Not all are documented.\n\nSigned-off-by: Jonas Gorski <jonas.gorski@gmail.com>\n---\n drivers/pinctrl/bcm63xx/Kconfig           |  15 +\n drivers/pinctrl/bcm63xx/Makefile          |   1 +\n drivers/pinctrl/bcm63xx/pinctrl-bcm6368.c | 573 ++++++++++++++++++++++++++++++\n 3 files changed, 589 insertions(+)\n create mode 100644 drivers/pinctrl/bcm63xx/pinctrl-bcm6368.c\n\n--- a/drivers/pinctrl/bcm63xx/Kconfig\n+++ b/drivers/pinctrl/bcm63xx/Kconfig\n@@ -30,3 +30,18 @@ config PINCTRL_BCM6362\n \tselect PINCONF\n \tselect PINCTRL_BCM63XX\n \tselect GENERIC_PINCONF\n+\n+config PINCTRL_BCM6368\n+\tbool \"BCM6368 pincontrol driver\" if COMPILE_TEST\n+\tselect PINMUX\n+\tselect PINCONF\n+\tselect PINCTRL_BCM63XX\n+\tselect GENERIC_PINCONF\n+\tselect MFD_SYSCON\n+\n+config PINCTRL_BCM63268\n+\tbool \"BCM63268 pincontrol driver\" if COMPILE_TEST\n+\tselect PINMUX\n+\tselect PINCONF\n+\tselect PINCTRL_BCM63XX\n+\tselect GENERIC_PINCONF\n--- a/drivers/pinctrl/bcm63xx/Makefile\n+++ b/drivers/pinctrl/bcm63xx/Makefile\n@@ -3,3 +3,4 @@ obj-$(CONFIG_PINCTRL_BCM6328)\t+= pinctrl\n obj-$(CONFIG_PINCTRL_BCM6348)\t+= pinctrl-bcm6348.o\n obj-$(CONFIG_PINCTRL_BCM6358)\t+= pinctrl-bcm6358.o\n obj-$(CONFIG_PINCTRL_BCM6362)\t+= pinctrl-bcm6362.o\n+obj-$(CONFIG_PINCTRL_BCM6368)\t+= pinctrl-bcm6368.o\n--- /dev/null\n+++ b/drivers/pinctrl/bcm63xx/pinctrl-bcm6368.c\n@@ -0,0 +1,573 @@\n+/*\n+ * This file is subject to the terms and conditions of the GNU General Public\n+ * License.  See the file \"COPYING\" in the main directory of this archive\n+ * for more details.\n+ *\n+ * Copyright (C) 2016 Jonas Gorski <jonas.gorski@gmail.com>\n+ */\n+\n+#include <linux/bitops.h>\n+#include <linux/kernel.h>\n+#include <linux/gpio.h>\n+#include <linux/mfd/syscon.h>\n+#include <linux/of.h>\n+#include <linux/of_address.h>\n+#include <linux/of_gpio.h>\n+#include <linux/pinctrl/pinconf.h>\n+#include <linux/pinctrl/pinconf-generic.h>\n+#include <linux/pinctrl/pinmux.h>\n+#include <linux/pinctrl/machine.h>\n+#include <linux/platform_device.h>\n+#include <linux/regmap.h>\n+#include <linux/slab.h>\n+#include <linux/spinlock.h>\n+\n+#include \"../core.h\"\n+#include \"../pinctrl-utils.h\"\n+\n+#include \"pinctrl-bcm63xx.h\"\n+\n+#define BCM6368_NGPIO\t38\n+\n+#define BCM6368_BASEMODE_MASK\t0x7\n+#define BCM6368_BASEMODE_GPIO\t0x0\n+#define BCM6368_BASEMODE_UART1\t0x1\n+\n+struct bcm6368_pingroup {\n+\tconst char *name;\n+\tconst unsigned * const pins;\n+\tconst unsigned num_pins;\n+};\n+\n+struct bcm6368_function {\n+\tconst char *name;\n+\tconst char * const *groups;\n+\tconst unsigned num_groups;\n+\n+\tunsigned dir_out:16;\n+\tunsigned basemode:3;\n+};\n+\n+struct bcm6368_pinctrl {\n+\tstruct pinctrl_dev *pctldev;\n+\tstruct pinctrl_desc desc;\n+\n+\tvoid __iomem *mode;\n+\tstruct regmap_field *overlay;\n+\n+\t/* register access lock */\n+\tspinlock_t lock;\n+\n+\tstruct gpio_chip gpio[2];\n+};\n+\n+#define BCM6368_BASEMODE_PIN(a, b)\t\t\\\n+\t{\t\t\t\t\t\\\n+\t\t.number = a,\t\t\t\\\n+\t\t.name = b,\t\t\t\\\n+\t\t.drv_data = (void *)true\t\\\n+\t}\n+\n+static const struct pinctrl_pin_desc bcm6368_pins[] = {\n+\tPINCTRL_PIN(0, \"gpio0\"),\n+\tPINCTRL_PIN(1, \"gpio1\"),\n+\tPINCTRL_PIN(2, \"gpio2\"),\n+\tPINCTRL_PIN(3, \"gpio3\"),\n+\tPINCTRL_PIN(4, \"gpio4\"),\n+\tPINCTRL_PIN(5, \"gpio5\"),\n+\tPINCTRL_PIN(6, \"gpio6\"),\n+\tPINCTRL_PIN(7, \"gpio7\"),\n+\tPINCTRL_PIN(8, \"gpio8\"),\n+\tPINCTRL_PIN(9, \"gpio9\"),\n+\tPINCTRL_PIN(10, \"gpio10\"),\n+\tPINCTRL_PIN(11, \"gpio11\"),\n+\tPINCTRL_PIN(12, \"gpio12\"),\n+\tPINCTRL_PIN(13, \"gpio13\"),\n+\tPINCTRL_PIN(14, \"gpio14\"),\n+\tPINCTRL_PIN(15, \"gpio15\"),\n+\tPINCTRL_PIN(16, \"gpio16\"),\n+\tPINCTRL_PIN(17, \"gpio17\"),\n+\tPINCTRL_PIN(18, \"gpio18\"),\n+\tPINCTRL_PIN(19, \"gpio19\"),\n+\tPINCTRL_PIN(20, \"gpio20\"),\n+\tPINCTRL_PIN(21, \"gpio21\"),\n+\tPINCTRL_PIN(22, \"gpio22\"),\n+\tPINCTRL_PIN(23, \"gpio23\"),\n+\tPINCTRL_PIN(24, \"gpio24\"),\n+\tPINCTRL_PIN(25, \"gpio25\"),\n+\tPINCTRL_PIN(26, \"gpio26\"),\n+\tPINCTRL_PIN(27, \"gpio27\"),\n+\tPINCTRL_PIN(28, \"gpio28\"),\n+\tPINCTRL_PIN(29, \"gpio29\"),\n+\tBCM6368_BASEMODE_PIN(30, \"gpio30\"),\n+\tBCM6368_BASEMODE_PIN(31, \"gpio31\"),\n+\tBCM6368_BASEMODE_PIN(32, \"gpio32\"),\n+\tBCM6368_BASEMODE_PIN(33, \"gpio33\"),\n+\tPINCTRL_PIN(34, \"gpio34\"),\n+\tPINCTRL_PIN(35, \"gpio35\"),\n+\tPINCTRL_PIN(36, \"gpio36\"),\n+\tPINCTRL_PIN(37, \"gpio37\"),\n+};\n+\n+static unsigned gpio0_pins[] = { 0 };\n+static unsigned gpio1_pins[] = { 1 };\n+static unsigned gpio2_pins[] = { 2 };\n+static unsigned gpio3_pins[] = { 3 };\n+static unsigned gpio4_pins[] = { 4 };\n+static unsigned gpio5_pins[] = { 5 };\n+static unsigned gpio6_pins[] = { 6 };\n+static unsigned gpio7_pins[] = { 7 };\n+static unsigned gpio8_pins[] = { 8 };\n+static unsigned gpio9_pins[] = { 9 };\n+static unsigned gpio10_pins[] = { 10 };\n+static unsigned gpio11_pins[] = { 11 };\n+static unsigned gpio12_pins[] = { 12 };\n+static unsigned gpio13_pins[] = { 13 };\n+static unsigned gpio14_pins[] = { 14 };\n+static unsigned gpio15_pins[] = { 15 };\n+static unsigned gpio16_pins[] = { 16 };\n+static unsigned gpio17_pins[] = { 17 };\n+static unsigned gpio18_pins[] = { 18 };\n+static unsigned gpio19_pins[] = { 19 };\n+static unsigned gpio20_pins[] = { 20 };\n+static unsigned gpio21_pins[] = { 21 };\n+static unsigned gpio22_pins[] = { 22 };\n+static unsigned gpio23_pins[] = { 23 };\n+static unsigned gpio24_pins[] = { 24 };\n+static unsigned gpio25_pins[] = { 25 };\n+static unsigned gpio26_pins[] = { 26 };\n+static unsigned gpio27_pins[] = { 27 };\n+static unsigned gpio28_pins[] = { 28 };\n+static unsigned gpio29_pins[] = { 29 };\n+static unsigned gpio30_pins[] = { 30 };\n+static unsigned gpio31_pins[] = { 31 };\n+static unsigned uart1_grp_pins[] = { 30, 31, 32, 33 };\n+\n+#define BCM6368_GROUP(n)\t\t\t\t\\\n+\t{\t\t\t\t\t\t\\\n+\t\t.name = #n,\t\t\t\t\\\n+\t\t.pins = n##_pins,\t\t\t\\\n+\t\t.num_pins = ARRAY_SIZE(n##_pins),\t\\\n+\t}\n+\n+static struct bcm6368_pingroup bcm6368_groups[] = {\n+\tBCM6368_GROUP(gpio0),\n+\tBCM6368_GROUP(gpio1),\n+\tBCM6368_GROUP(gpio2),\n+\tBCM6368_GROUP(gpio3),\n+\tBCM6368_GROUP(gpio4),\n+\tBCM6368_GROUP(gpio5),\n+\tBCM6368_GROUP(gpio6),\n+\tBCM6368_GROUP(gpio7),\n+\tBCM6368_GROUP(gpio8),\n+\tBCM6368_GROUP(gpio9),\n+\tBCM6368_GROUP(gpio10),\n+\tBCM6368_GROUP(gpio11),\n+\tBCM6368_GROUP(gpio12),\n+\tBCM6368_GROUP(gpio13),\n+\tBCM6368_GROUP(gpio14),\n+\tBCM6368_GROUP(gpio15),\n+\tBCM6368_GROUP(gpio16),\n+\tBCM6368_GROUP(gpio17),\n+\tBCM6368_GROUP(gpio18),\n+\tBCM6368_GROUP(gpio19),\n+\tBCM6368_GROUP(gpio20),\n+\tBCM6368_GROUP(gpio21),\n+\tBCM6368_GROUP(gpio22),\n+\tBCM6368_GROUP(gpio23),\n+\tBCM6368_GROUP(gpio24),\n+\tBCM6368_GROUP(gpio25),\n+\tBCM6368_GROUP(gpio26),\n+\tBCM6368_GROUP(gpio27),\n+\tBCM6368_GROUP(gpio28),\n+\tBCM6368_GROUP(gpio29),\n+\tBCM6368_GROUP(gpio30),\n+\tBCM6368_GROUP(gpio31),\n+\tBCM6368_GROUP(uart1_grp),\n+};\n+\n+static const char * const analog_afe_0_groups[] = {\n+\t\"gpio0\",\n+};\n+\n+static const char * const analog_afe_1_groups[] = {\n+\t\"gpio1\",\n+};\n+\n+static const char * const sys_irq_groups[] = {\n+\t\"gpio2\",\n+};\n+\n+static const char * const serial_led_data_groups[] = {\n+\t\"gpio3\",\n+};\n+\n+static const char * const serial_led_clk_groups[] = {\n+\t\"gpio4\",\n+};\n+\n+static const char * const inet_led_groups[] = {\n+\t\"gpio5\",\n+};\n+\n+static const char * const ephy0_led_groups[] = {\n+\t\"gpio6\",\n+};\n+\n+static const char * const ephy1_led_groups[] = {\n+\t\"gpio7\",\n+};\n+\n+static const char * const ephy2_led_groups[] = {\n+\t\"gpio8\",\n+};\n+\n+static const char * const ephy3_led_groups[] = {\n+\t\"gpio9\",\n+};\n+\n+static const char * const robosw_led_data_groups[] = {\n+\t\"gpio10\",\n+};\n+\n+static const char * const robosw_led_clk_groups[] = {\n+\t\"gpio11\",\n+};\n+\n+static const char * const robosw_led0_groups[] = {\n+\t\"gpio12\",\n+};\n+\n+static const char * const robosw_led1_groups[] = {\n+\t\"gpio13\",\n+};\n+\n+static const char * const usb_device_led_groups[] = {\n+\t\"gpio14\",\n+};\n+\n+static const char * const pci_req1_groups[] = {\n+\t\"gpio16\",\n+};\n+\n+static const char * const pci_gnt1_groups[] = {\n+\t\"gpio17\",\n+};\n+\n+static const char * const pci_intb_groups[] = {\n+\t\"gpio18\",\n+};\n+\n+static const char * const pci_req0_groups[] = {\n+\t\"gpio19\",\n+};\n+\n+static const char * const pci_gnt0_groups[] = {\n+\t\"gpio20\",\n+};\n+\n+static const char * const pcmcia_cd1_groups[] = {\n+\t\"gpio22\",\n+};\n+\n+static const char * const pcmcia_cd2_groups[] = {\n+\t\"gpio23\",\n+};\n+\n+static const char * const pcmcia_vs1_groups[] = {\n+\t\"gpio24\",\n+};\n+\n+static const char * const pcmcia_vs2_groups[] = {\n+\t\"gpio25\",\n+};\n+\n+static const char * const ebi_cs2_groups[] = {\n+\t\"gpio26\",\n+};\n+\n+static const char * const ebi_cs3_groups[] = {\n+\t\"gpio27\",\n+};\n+\n+static const char * const spi_cs2_groups[] = {\n+\t\"gpio28\",\n+};\n+\n+static const char * const spi_cs3_groups[] = {\n+\t\"gpio29\",\n+};\n+\n+static const char * const spi_cs4_groups[] = {\n+\t\"gpio30\",\n+};\n+\n+static const char * const spi_cs5_groups[] = {\n+\t\"gpio31\",\n+};\n+\n+static const char * const uart1_groups[] = {\n+\t\"uart1_grp\",\n+};\n+\n+#define BCM6368_FUN(n, out)\t\t\t\t\\\n+\t{\t\t\t\t\t\t\\\n+\t\t.name = #n,\t\t\t\t\\\n+\t\t.groups = n##_groups,\t\t\t\\\n+\t\t.num_groups = ARRAY_SIZE(n##_groups),\t\\\n+\t\t.dir_out = out,\t\t\t\t\\\n+\t}\n+\n+#define BCM6368_BASEMODE_FUN(n, val, out)\t\t\\\n+\t{\t\t\t\t\t\t\\\n+\t\t.name = #n,\t\t\t\t\\\n+\t\t.groups = n##_groups,\t\t\t\\\n+\t\t.num_groups = ARRAY_SIZE(n##_groups),\t\\\n+\t\t.basemode = BCM6368_BASEMODE_##val,\t\\\n+\t\t.dir_out = out,\t\t\t\t\\\n+\t}\n+\n+static const struct bcm6368_function bcm6368_funcs[] = {\n+\tBCM6368_FUN(analog_afe_0, 1),\n+\tBCM6368_FUN(analog_afe_1, 1),\n+\tBCM6368_FUN(sys_irq, 1),\n+\tBCM6368_FUN(serial_led_data, 1),\n+\tBCM6368_FUN(serial_led_clk, 1),\n+\tBCM6368_FUN(inet_led, 1),\n+\tBCM6368_FUN(ephy0_led, 1),\n+\tBCM6368_FUN(ephy1_led, 1),\n+\tBCM6368_FUN(ephy2_led, 1),\n+\tBCM6368_FUN(ephy3_led, 1),\n+\tBCM6368_FUN(robosw_led_data, 1),\n+\tBCM6368_FUN(robosw_led_clk, 1),\n+\tBCM6368_FUN(robosw_led0, 1),\n+\tBCM6368_FUN(robosw_led1, 1),\n+\tBCM6368_FUN(usb_device_led, 1),\n+\tBCM6368_FUN(pci_req1, 0),\n+\tBCM6368_FUN(pci_gnt1, 0),\n+\tBCM6368_FUN(pci_intb, 0),\n+\tBCM6368_FUN(pci_req0, 0),\n+\tBCM6368_FUN(pci_gnt0, 0),\n+\tBCM6368_FUN(pcmcia_cd1, 0),\n+\tBCM6368_FUN(pcmcia_cd2, 0),\n+\tBCM6368_FUN(pcmcia_vs1, 0),\n+\tBCM6368_FUN(pcmcia_vs2, 0),\n+\tBCM6368_FUN(ebi_cs2, 1),\n+\tBCM6368_FUN(ebi_cs3, 1),\n+\tBCM6368_FUN(spi_cs2, 1),\n+\tBCM6368_FUN(spi_cs3, 1),\n+\tBCM6368_FUN(spi_cs4, 1),\n+\tBCM6368_FUN(spi_cs5, 1),\n+\tBCM6368_BASEMODE_FUN(uart1, UART1, 0x6),\n+};\n+\n+static int bcm6368_pinctrl_get_group_count(struct pinctrl_dev *pctldev)\n+{\n+\treturn ARRAY_SIZE(bcm6368_groups);\n+}\n+\n+static const char *bcm6368_pinctrl_get_group_name(struct pinctrl_dev *pctldev,\n+\t\t\t\t\t\t  unsigned group)\n+{\n+\treturn bcm6368_groups[group].name;\n+}\n+\n+static int bcm6368_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,\n+\t\t\t\t\t  unsigned group, const unsigned **pins,\n+\t\t\t\t\t  unsigned *num_pins)\n+{\n+\t*pins = bcm6368_groups[group].pins;\n+\t*num_pins = bcm6368_groups[group].num_pins;\n+\n+\treturn 0;\n+}\n+\n+static int bcm6368_pinctrl_get_func_count(struct pinctrl_dev *pctldev)\n+{\n+\treturn ARRAY_SIZE(bcm6368_funcs);\n+}\n+\n+static const char *bcm6368_pinctrl_get_func_name(struct pinctrl_dev *pctldev,\n+\t\t\t\t\t\t unsigned selector)\n+{\n+\treturn bcm6368_funcs[selector].name;\n+}\n+\n+static int bcm6368_pinctrl_get_groups(struct pinctrl_dev *pctldev,\n+\t\t\t\t      unsigned selector,\n+\t\t\t\t      const char * const **groups,\n+\t\t\t\t      unsigned * const num_groups)\n+{\n+\t*groups = bcm6368_funcs[selector].groups;\n+\t*num_groups = bcm6368_funcs[selector].num_groups;\n+\n+\treturn 0;\n+}\n+\n+static void bcm6368_rmw_mux(struct bcm6368_pinctrl *pctl, void __iomem *reg,\n+\t\t\t    u32 mask, u32 val)\n+{\n+\tu32 tmp;\n+\n+\ttmp = __raw_readl(reg);\n+\ttmp &= ~mask;\n+\ttmp |= (val & mask);\n+\t__raw_writel(tmp, reg);\n+}\n+\n+static int bcm6368_pinctrl_set_mux(struct pinctrl_dev *pctldev,\n+\t\t\t\t   unsigned selector, unsigned group)\n+{\n+\tstruct bcm6368_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);\n+\tconst struct bcm6368_pingroup *grp = &bcm6368_groups[group];\n+\tconst struct bcm6368_function *fun = &bcm6368_funcs[selector];\n+\tunsigned long flags;\n+\tint i, pin;\n+\n+\tspin_lock_irqsave(&pctl->lock, flags);\n+\tif (fun->basemode) {\n+\t\tu32 mask = 0;\n+\n+\t\tfor (i = 0; i < grp->num_pins; i++) {\n+\t\t\tpin = grp->pins[i];\n+\t\t\tif (pin < 32)\n+\t\t\t\tmask |= BIT(pin);\n+\t\t}\n+\n+\t\tbcm6368_rmw_mux(pctl, pctl->mode, mask, 0);\n+\t\tregmap_field_write(pctl->overlay, fun->basemode);\n+\t} else {\n+\t\tpin = grp->pins[0];\n+\n+\t\tif (bcm6368_pins[pin].drv_data)\n+\t\t\tregmap_field_write(pctl->overlay,\n+\t\t\t\t\t   BCM6368_BASEMODE_GPIO);\n+\n+\t\tbcm6368_rmw_mux(pctl, pctl->mode, BIT(pin), BIT(pin));\n+\t}\n+\tspin_unlock_irqrestore(&pctl->lock, flags);\n+\n+\tfor (pin = 0; pin < grp->num_pins; pin++) {\n+\t\tint hw_gpio = bcm6368_pins[pin].number;\n+\t\tstruct gpio_chip *gc = &pctl->gpio[hw_gpio / 32];\n+\n+\t\tif (fun->dir_out & BIT(pin))\n+\t\t\tgc->direction_output(gc, hw_gpio % 32, 0);\n+\t\telse\n+\t\t\tgc->direction_input(gc, hw_gpio % 32);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int bcm6368_gpio_request_enable(struct pinctrl_dev *pctldev,\n+\t\t\t\t       struct pinctrl_gpio_range *range,\n+\t\t\t\t       unsigned offset)\n+{\n+\tstruct bcm6368_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);\n+\tunsigned long flags;\n+\n+\tif (offset >= 32 && !bcm6368_pins[offset].drv_data)\n+\t\treturn 0;\n+\n+\tspin_lock_irqsave(&pctl->lock, flags);\n+\t/* disable all functions using this pin */\n+\tif (offset < 32)\n+\t\tbcm6368_rmw_mux(pctl, pctl->mode, BIT(offset), 0);\n+\n+\tif (bcm6368_pins[offset].drv_data)\n+\t\tregmap_field_write(pctl->overlay, BCM6368_BASEMODE_GPIO);\n+\n+\tspin_unlock_irqrestore(&pctl->lock, flags);\n+\n+\treturn 0;\n+}\n+\n+static struct pinctrl_ops bcm6368_pctl_ops = {\n+\t.get_groups_count\t= bcm6368_pinctrl_get_group_count,\n+\t.get_group_name\t\t= bcm6368_pinctrl_get_group_name,\n+\t.get_group_pins\t\t= bcm6368_pinctrl_get_group_pins,\n+#ifdef CONFIG_OF\n+\t.dt_node_to_map\t\t= pinconf_generic_dt_node_to_map_pin,\n+\t.dt_free_map\t\t= pinctrl_utils_free_map,\n+#endif\n+};\n+\n+static struct pinmux_ops bcm6368_pmx_ops = {\n+\t.get_functions_count\t= bcm6368_pinctrl_get_func_count,\n+\t.get_function_name\t= bcm6368_pinctrl_get_func_name,\n+\t.get_function_groups\t= bcm6368_pinctrl_get_groups,\n+\t.set_mux\t\t= bcm6368_pinctrl_set_mux,\n+\t.gpio_request_enable\t= bcm6368_gpio_request_enable,\n+\t.strict\t\t\t= true,\n+};\n+\n+static int bcm6368_pinctrl_probe(struct platform_device *pdev)\n+{\n+\tstruct bcm6368_pinctrl *pctl;\n+\tstruct resource *res;\n+\tvoid __iomem *mode;\n+\tstruct regmap *basemode;\n+\tstruct reg_field overlay = REG_FIELD(0, 0, 3);\n+\n+\tif (pdev->dev.of_node)\n+\t\tbasemode = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,\n+\t\t\t\t\t\t\t   \"brcm,gpiobasemode\");\n+\telse\n+\t\tbasemode = syscon_regmap_lookup_by_pdevname(\"syscon.b00000b8\");\n+\n+\tif (IS_ERR(basemode))\n+\t\treturn PTR_ERR(basemode);\n+\n+\tres = platform_get_resource_byname(pdev, IORESOURCE_MEM, \"mode\");\n+\tmode = devm_ioremap_resource(&pdev->dev, res);\n+\tif (IS_ERR(mode))\n+\t\treturn PTR_ERR(mode);\n+\n+\tpctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);\n+\tif (!pctl)\n+\t\treturn -ENOMEM;\n+\n+\tpctl->overlay = devm_regmap_field_alloc(&pdev->dev, basemode, overlay);\n+\tif (IS_ERR(pctl->overlay))\n+\t\treturn PTR_ERR(pctl->overlay);\n+\n+\tspin_lock_init(&pctl->lock);\n+\n+\tpctl->mode = mode;\n+\n+\t/* disable all muxes by default */\n+\t__raw_writel(0, pctl->mode);\n+\n+\tpctl->desc.name = dev_name(&pdev->dev);\n+\tpctl->desc.owner = THIS_MODULE;\n+\tpctl->desc.pctlops = &bcm6368_pctl_ops;\n+\tpctl->desc.pmxops = &bcm6368_pmx_ops;\n+\n+\tpctl->desc.npins = ARRAY_SIZE(bcm6368_pins);\n+\tpctl->desc.pins = bcm6368_pins;\n+\n+\tplatform_set_drvdata(pdev, pctl);\n+\n+\tpctl->pctldev = bcm63xx_pinctrl_register(pdev, &pctl->desc, pctl,\n+\t\t\t\t\t\t pctl->gpio, BCM6368_NGPIO);\n+\tif (IS_ERR(pctl->pctldev))\n+\t\treturn PTR_ERR(pctl->pctldev);\n+\n+\treturn 0;\n+}\n+\n+static const struct of_device_id bcm6368_pinctrl_match[] = {\n+\t{ .compatible = \"brcm,bcm6368-pinctrl\", },\n+\t{ },\n+};\n+\n+static struct platform_driver bcm6368_pinctrl_driver = {\n+\t.probe = bcm6368_pinctrl_probe,\n+\t.driver = {\n+\t\t.name = \"bcm6368-pinctrl\",\n+\t\t.of_match_table = bcm6368_pinctrl_match,\n+\t},\n+};\n+\n+builtin_platform_driver(bcm6368_pinctrl_driver);\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/141-Documentation-add-BCM63268-pincontroller-binding-doc.patch",
    "content": "From 28cc80e4ada5d73d5305fd268297825cd8d01936 Mon Sep 17 00:00:00 2001\nFrom: Jonas Gorski <jonas.gorski@gmail.com>\nDate: Wed, 27 Jul 2016 11:37:08 +0200\nSubject: [PATCH 12/16] Documentation: add BCM63268 pincontroller binding\n documentation\n\nAdd binding documentation for the pincontrol core found in the BCM63268\nfamily SoCs.\n\nSigned-off-by: Jonas Gorski <jonas.gorski@gmail.com>\n---\n .../bindings/pinctrl/brcm,bcm63268-pinctrl.txt     | 88 ++++++++++++++++++++++\n 1 file changed, 88 insertions(+)\n create mode 100644 Documentation/devicetree/bindings/pinctrl/brcm,bcm63268-pinctrl.txt\n\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/pinctrl/brcm,bcm63268-pinctrl.txt\n@@ -0,0 +1,88 @@\n+* Broadcom BCM63268 pin controller\n+\n+Required properties:\n+- compatible: Must be \"brcm,bcm6362-pinctrl\".\n+- reg: Register specifiers of dirout, dat, led, mode, ctrl, basemode registers.\n+- reg-names: Must be \"dirout\", \"dat\", \"led\", \"mode\", \"ctrl\", \"basemode\".\n+- gpio-controller: Identifies this node as a GPIO controller.\n+- #gpio-cells: Must be <2>.\n+\n+Example:\n+\n+pinctrl: pin-controller@100000c0 {\n+\tcompatible = \"brcm,bcm63268-pinctrl\";\n+\treg = <0x100000c0 0x8>,\n+\t      <0x100000c8 0x8>,\n+\t      <0x100000d0 0x4>,\n+\t      <0x100000d8 0x4>,\n+\t      <0x100000dc 0x4>,\n+\t      <0x100000f8 0x4>;\n+\treg-names = \"dirout\", \"dat\", \"led\", \"mode\",\n+\t\t    \"ctrl\", \"basemode\";\n+\n+\tgpio-controller;\n+\t#gpio-cells = <2>;\n+};\n+\n+Available pins/groups and functions:\n+\n+name\t\tpins\t\tfunctions\n+-----------------------------------------------------------\n+gpio0\t\t0\t\tled, serial_led_clk\n+gpio1\t\t1\t\tled, serial_led_data\n+gpio2\t\t2\t\tled,\n+gpio3\t\t3\t\tled,\n+gpio4\t\t4\t\tled,\n+gpio5\t\t5\t\tled,\n+gpio6\t\t6\t\tled,\n+gpio7\t\t7\t\tled,\n+gpio8\t\t8\t\tled, hsspi_cs6\n+gpio9\t\t9\t\tled, hsspi_cs7\n+gpio10\t\t10\t\tled, uart1_scts\n+gpio11\t\t11\t\tled, uart1_srts\n+gpio12\t\t12\t\tled, uart1_sdin\n+gpio13\t\t13\t\tled, uart1_sdout\n+gpio14\t\t14\t\tled, ntr_pulse_in\n+gpio15\t\t15\t\tled, dsl_ntr_pulse_out\n+gpio16\t\t16\t\tled, hsspi_cs4\n+gpio17\t\t17\t\tled, hsspi_cs5\n+gpio18\t\t18\t\tled, adsl_spi_miso\n+gpio19\t\t19\t\tled, adsl_spi_mosi\n+gpio20\t\t20\t\tled,\n+gpio21\t\t21\t\tled,\n+gpio22\t\t22\t\tled, vreg_clk\n+gpio23\t\t23\t\tled, pcie_clkreq_b\n+gpio24\t\t24\t\tuart1_scts\n+gpio25\t\t25\t\tuart1_srts\n+gpio26\t\t26\t\tuart1_sdin\n+gpio27\t\t27\t\tuart1_sdout\n+gpio28\t\t28\t\tntr_pulse_in\n+gpio29\t\t29\t\tdsl_ntr_pulse_out\n+gpio30\t\t30\t\tswitch_led_clk\n+gpio31\t\t31\t\tswitch_led_data\n+gpio32\t\t32\t\twifi\n+gpio33\t\t33\t\twifi\n+gpio34\t\t34\t\twifi\n+gpio35\t\t35\t\twifi\n+gpio36\t\t36\t\twifi\n+gpio37\t\t37\t\twifi\n+gpio38\t\t38\t\twifi\n+gpio39\t\t39\t\twifi\n+gpio40\t\t40\t\twifi\n+gpio41\t\t41\t\twifi\n+gpio42\t\t42\t\twifi\n+gpio43\t\t43\t\twifi\n+gpio44\t\t44\t\twifi\n+gpio45\t\t45\t\twifi\n+gpio46\t\t46\t\twifi\n+gpio47\t\t47\t\twifi\n+gpio48\t\t48\t\twifi\n+gpio49\t\t49\t\twifi\n+gpio50\t\t50\t\twifi\n+gpio51\t\t51\t\twifi\n+nand_grp\t2-7,24-31\tnand\n+dect_pd_grp\t8-9\t\tdect_pd\n+vdsl_phy0_grp\t10-11\t\tvdsl_phy0\n+vdsl_phy1_grp\t12-13\t\tvdsl_phy1\n+vdsl_phy2_grp\t24-25\t\tvdsl_phy2\n+vdsl_phy3_grp\t26-27\t\tvdsl_phy3\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/142-pinctrl-add-a-pincontrol-driver-for-BCM63268.patch",
    "content": "From 8665d3ea63649cc155286c75f83f694a930580e5 Mon Sep 17 00:00:00 2001\nFrom: Jonas Gorski <jonas.gorski@gmail.com>\nDate: Fri, 24 Jun 2016 22:19:12 +0200\nSubject: [PATCH 13/16] pinctrl: add a pincontrol driver for BCM63268\n\nAdd a pincontrol driver for BCM63268. BCM63268 allows muxing GPIOs\nto different functions. Depending on the mux, these are either single\npin configurations or whole pin groups.\n\nSigned-off-by: Jonas Gorski <jonas.gorski@gmail.com>\n---\n drivers/pinctrl/bcm63xx/Makefile           |   1 +\n drivers/pinctrl/bcm63xx/pinctrl-bcm63268.c | 710 +++++++++++++++++++++++++++++\n 2 files changed, 711 insertions(+)\n create mode 100644 drivers/pinctrl/bcm63xx/pinctrl-bcm63268.c\n\n--- a/drivers/pinctrl/bcm63xx/Makefile\n+++ b/drivers/pinctrl/bcm63xx/Makefile\n@@ -4,3 +4,4 @@ obj-$(CONFIG_PINCTRL_BCM6348)\t+= pinctrl\n obj-$(CONFIG_PINCTRL_BCM6358)\t+= pinctrl-bcm6358.o\n obj-$(CONFIG_PINCTRL_BCM6362)\t+= pinctrl-bcm6362.o\n obj-$(CONFIG_PINCTRL_BCM6368)\t+= pinctrl-bcm6368.o\n+obj-$(CONFIG_PINCTRL_BCM63268)\t+= pinctrl-bcm63268.o\n--- /dev/null\n+++ b/drivers/pinctrl/bcm63xx/pinctrl-bcm63268.c\n@@ -0,0 +1,710 @@\n+/*\n+ * This file is subject to the terms and conditions of the GNU General Public\n+ * License.  See the file \"COPYING\" in the main directory of this archive\n+ * for more details.\n+ *\n+ * Copyright (C) 2016 Jonas Gorski <jonas.gorski@gmail.com>\n+ */\n+\n+#include <linux/kernel.h>\n+#include <linux/spinlock.h>\n+#include <linux/bitops.h>\n+#include <linux/gpio.h>\n+#include <linux/of.h>\n+#include <linux/of_gpio.h>\n+#include <linux/slab.h>\n+#include <linux/platform_device.h>\n+\n+#include <linux/pinctrl/pinconf.h>\n+#include <linux/pinctrl/pinconf-generic.h>\n+#include <linux/pinctrl/pinmux.h>\n+#include <linux/pinctrl/machine.h>\n+\n+#include \"../core.h\"\n+#include \"../pinctrl-utils.h\"\n+\n+#include \"pinctrl-bcm63xx.h\"\n+\n+#define BCM63268_NGPIO\t\t\t52\n+\n+/* GPIO_BASEMODE register */\n+#define BASEMODE_NAND\t\t\tBIT(2) /* GPIOs 2-7, 24-31 */\n+#define BASEMODE_GPIO35\t\t\tBIT(4) /* GPIO 35 */\n+#define BASEMODE_DECTPD\t\t\tBIT(5) /* GPIOs 8/9 */\n+#define BASEMODE_VDSL_PHY_0\t\tBIT(6) /* GPIOs 10/11 */\n+#define BASEMODE_VDSL_PHY_1\t\tBIT(7) /* GPIOs 12/13 */\n+#define BASEMODE_VDSL_PHY_2\t\tBIT(8) /* GPIOs 24/25 */\n+#define BASEMODE_VDSL_PHY_3\t\tBIT(9) /* GPIOs 26/27 */\n+\n+enum bcm63268_pinctrl_reg {\n+\tBCM63268_LEDCTRL,\n+\tBCM63268_MODE,\n+\tBCM63268_CTRL,\n+\tBCM63268_BASEMODE,\n+};\n+\n+struct bcm63268_pingroup {\n+\tconst char *name;\n+\tconst unsigned * const pins;\n+\tconst unsigned num_pins;\n+};\n+\n+struct bcm63268_function {\n+\tconst char *name;\n+\tconst char * const *groups;\n+\tconst unsigned num_groups;\n+\n+\tenum bcm63268_pinctrl_reg reg;\n+\tu32 mask;\n+};\n+\n+struct bcm63268_pinctrl {\n+\tstruct pinctrl_dev *pctldev;\n+\tstruct pinctrl_desc desc;\n+\n+\tvoid __iomem *led;\n+\tvoid __iomem *mode;\n+\tvoid __iomem *ctrl;\n+\tvoid __iomem *basemode;\n+\n+\t/* register access lock */\n+\tspinlock_t lock;\n+\n+\tstruct gpio_chip gpio[2];\n+};\n+\n+#define BCM63268_PIN(a, b, basemode)\t\t\t\\\n+\t{\t\t\t\t\t\t\\\n+\t\t.number = a,\t\t\t\t\\\n+\t\t.name = b,\t\t\t\t\\\n+\t\t.drv_data = (void *)(basemode)\t\t\\\n+\t}\n+\n+static const struct pinctrl_pin_desc bcm63268_pins[] = {\n+\tPINCTRL_PIN(0, \"gpio0\"),\n+\tPINCTRL_PIN(1, \"gpio1\"),\n+\tBCM63268_PIN(2, \"gpio2\", BASEMODE_NAND),\n+\tBCM63268_PIN(3, \"gpio3\", BASEMODE_NAND),\n+\tBCM63268_PIN(4, \"gpio4\", BASEMODE_NAND),\n+\tBCM63268_PIN(5, \"gpio5\", BASEMODE_NAND),\n+\tBCM63268_PIN(6, \"gpio6\", BASEMODE_NAND),\n+\tBCM63268_PIN(7, \"gpio7\", BASEMODE_NAND),\n+\tBCM63268_PIN(8, \"gpio8\", BASEMODE_DECTPD),\n+\tBCM63268_PIN(9, \"gpio9\", BASEMODE_DECTPD),\n+\tBCM63268_PIN(10, \"gpio10\", BASEMODE_VDSL_PHY_0),\n+\tBCM63268_PIN(11, \"gpio11\", BASEMODE_VDSL_PHY_0),\n+\tBCM63268_PIN(12, \"gpio12\", BASEMODE_VDSL_PHY_1),\n+\tBCM63268_PIN(13, \"gpio13\", BASEMODE_VDSL_PHY_1),\n+\tPINCTRL_PIN(14, \"gpio14\"),\n+\tPINCTRL_PIN(15, \"gpio15\"),\n+\tPINCTRL_PIN(16, \"gpio16\"),\n+\tPINCTRL_PIN(17, \"gpio17\"),\n+\tPINCTRL_PIN(18, \"gpio18\"),\n+\tPINCTRL_PIN(19, \"gpio19\"),\n+\tPINCTRL_PIN(20, \"gpio20\"),\n+\tPINCTRL_PIN(21, \"gpio21\"),\n+\tPINCTRL_PIN(22, \"gpio22\"),\n+\tPINCTRL_PIN(23, \"gpio23\"),\n+\tBCM63268_PIN(24, \"gpio24\", BASEMODE_NAND | BASEMODE_VDSL_PHY_2),\n+\tBCM63268_PIN(25, \"gpio25\", BASEMODE_NAND | BASEMODE_VDSL_PHY_2),\n+\tBCM63268_PIN(26, \"gpio26\", BASEMODE_NAND | BASEMODE_VDSL_PHY_3),\n+\tBCM63268_PIN(27, \"gpio27\", BASEMODE_NAND | BASEMODE_VDSL_PHY_3),\n+\tBCM63268_PIN(28, \"gpio28\", BASEMODE_NAND),\n+\tBCM63268_PIN(29, \"gpio29\", BASEMODE_NAND),\n+\tBCM63268_PIN(30, \"gpio30\", BASEMODE_NAND),\n+\tBCM63268_PIN(31, \"gpio31\", BASEMODE_NAND),\n+\tPINCTRL_PIN(32, \"gpio32\"),\n+\tPINCTRL_PIN(33, \"gpio33\"),\n+\tPINCTRL_PIN(34, \"gpio34\"),\n+\tPINCTRL_PIN(35, \"gpio35\"),\n+\tPINCTRL_PIN(36, \"gpio36\"),\n+\tPINCTRL_PIN(37, \"gpio37\"),\n+\tPINCTRL_PIN(38, \"gpio38\"),\n+\tPINCTRL_PIN(39, \"gpio39\"),\n+\tPINCTRL_PIN(40, \"gpio40\"),\n+\tPINCTRL_PIN(41, \"gpio41\"),\n+\tPINCTRL_PIN(42, \"gpio42\"),\n+\tPINCTRL_PIN(43, \"gpio43\"),\n+\tPINCTRL_PIN(44, \"gpio44\"),\n+\tPINCTRL_PIN(45, \"gpio45\"),\n+\tPINCTRL_PIN(46, \"gpio46\"),\n+\tPINCTRL_PIN(47, \"gpio47\"),\n+\tPINCTRL_PIN(48, \"gpio48\"),\n+\tPINCTRL_PIN(49, \"gpio49\"),\n+\tPINCTRL_PIN(50, \"gpio50\"),\n+\tPINCTRL_PIN(51, \"gpio51\"),\n+};\n+\n+static unsigned gpio0_pins[] = { 0 };\n+static unsigned gpio1_pins[] = { 1 };\n+static unsigned gpio2_pins[] = { 2 };\n+static unsigned gpio3_pins[] = { 3 };\n+static unsigned gpio4_pins[] = { 4 };\n+static unsigned gpio5_pins[] = { 5 };\n+static unsigned gpio6_pins[] = { 6 };\n+static unsigned gpio7_pins[] = { 7 };\n+static unsigned gpio8_pins[] = { 8 };\n+static unsigned gpio9_pins[] = { 9 };\n+static unsigned gpio10_pins[] = { 10 };\n+static unsigned gpio11_pins[] = { 11 };\n+static unsigned gpio12_pins[] = { 12 };\n+static unsigned gpio13_pins[] = { 13 };\n+static unsigned gpio14_pins[] = { 14 };\n+static unsigned gpio15_pins[] = { 15 };\n+static unsigned gpio16_pins[] = { 16 };\n+static unsigned gpio17_pins[] = { 17 };\n+static unsigned gpio18_pins[] = { 18 };\n+static unsigned gpio19_pins[] = { 19 };\n+static unsigned gpio20_pins[] = { 20 };\n+static unsigned gpio21_pins[] = { 21 };\n+static unsigned gpio22_pins[] = { 22 };\n+static unsigned gpio23_pins[] = { 23 };\n+static unsigned gpio24_pins[] = { 24 };\n+static unsigned gpio25_pins[] = { 25 };\n+static unsigned gpio26_pins[] = { 26 };\n+static unsigned gpio27_pins[] = { 27 };\n+static unsigned gpio28_pins[] = { 28 };\n+static unsigned gpio29_pins[] = { 29 };\n+static unsigned gpio30_pins[] = { 30 };\n+static unsigned gpio31_pins[] = { 31 };\n+static unsigned gpio32_pins[] = { 32 };\n+static unsigned gpio33_pins[] = { 33 };\n+static unsigned gpio34_pins[] = { 34 };\n+static unsigned gpio35_pins[] = { 35 };\n+static unsigned gpio36_pins[] = { 36 };\n+static unsigned gpio37_pins[] = { 37 };\n+static unsigned gpio38_pins[] = { 38 };\n+static unsigned gpio39_pins[] = { 39 };\n+static unsigned gpio40_pins[] = { 40 };\n+static unsigned gpio41_pins[] = { 41 };\n+static unsigned gpio42_pins[] = { 42 };\n+static unsigned gpio43_pins[] = { 43 };\n+static unsigned gpio44_pins[] = { 44 };\n+static unsigned gpio45_pins[] = { 45 };\n+static unsigned gpio46_pins[] = { 46 };\n+static unsigned gpio47_pins[] = { 47 };\n+static unsigned gpio48_pins[] = { 48 };\n+static unsigned gpio49_pins[] = { 49 };\n+static unsigned gpio50_pins[] = { 50 };\n+static unsigned gpio51_pins[] = { 51 };\n+\n+static unsigned nand_grp_pins[] = {\n+\t2, 3, 4, 5, 6, 7, 24,\n+\t25, 26, 27, 28, 29, 30, 31,\n+};\n+\n+static unsigned dectpd_grp_pins[] = { 8, 9 };\n+static unsigned vdsl_phy0_grp_pins[] = { 10, 11 };\n+static unsigned vdsl_phy1_grp_pins[] = { 12, 13 };\n+static unsigned vdsl_phy2_grp_pins[] = { 24, 25 };\n+static unsigned vdsl_phy3_grp_pins[] = { 26, 27 };\n+\n+#define BCM63268_GROUP(n)\t\t\t\t\t\\\n+\t{\t\t\t\t\t\t\t\\\n+\t\t.name = #n,\t\t\t\t\t\\\n+\t\t.pins = n##_pins,\t\t\t\t\\\n+\t\t.num_pins = ARRAY_SIZE(n##_pins),\t\t\\\n+\t}\n+\n+static struct bcm63268_pingroup bcm63268_groups[] = {\n+\tBCM63268_GROUP(gpio0),\n+\tBCM63268_GROUP(gpio1),\n+\tBCM63268_GROUP(gpio2),\n+\tBCM63268_GROUP(gpio3),\n+\tBCM63268_GROUP(gpio4),\n+\tBCM63268_GROUP(gpio5),\n+\tBCM63268_GROUP(gpio6),\n+\tBCM63268_GROUP(gpio7),\n+\tBCM63268_GROUP(gpio8),\n+\tBCM63268_GROUP(gpio9),\n+\tBCM63268_GROUP(gpio10),\n+\tBCM63268_GROUP(gpio11),\n+\tBCM63268_GROUP(gpio12),\n+\tBCM63268_GROUP(gpio13),\n+\tBCM63268_GROUP(gpio14),\n+\tBCM63268_GROUP(gpio15),\n+\tBCM63268_GROUP(gpio16),\n+\tBCM63268_GROUP(gpio17),\n+\tBCM63268_GROUP(gpio18),\n+\tBCM63268_GROUP(gpio19),\n+\tBCM63268_GROUP(gpio20),\n+\tBCM63268_GROUP(gpio21),\n+\tBCM63268_GROUP(gpio22),\n+\tBCM63268_GROUP(gpio23),\n+\tBCM63268_GROUP(gpio24),\n+\tBCM63268_GROUP(gpio25),\n+\tBCM63268_GROUP(gpio26),\n+\tBCM63268_GROUP(gpio27),\n+\tBCM63268_GROUP(gpio28),\n+\tBCM63268_GROUP(gpio29),\n+\tBCM63268_GROUP(gpio30),\n+\tBCM63268_GROUP(gpio31),\n+\tBCM63268_GROUP(gpio32),\n+\tBCM63268_GROUP(gpio33),\n+\tBCM63268_GROUP(gpio34),\n+\tBCM63268_GROUP(gpio35),\n+\tBCM63268_GROUP(gpio36),\n+\tBCM63268_GROUP(gpio37),\n+\tBCM63268_GROUP(gpio38),\n+\tBCM63268_GROUP(gpio39),\n+\tBCM63268_GROUP(gpio40),\n+\tBCM63268_GROUP(gpio41),\n+\tBCM63268_GROUP(gpio42),\n+\tBCM63268_GROUP(gpio43),\n+\tBCM63268_GROUP(gpio44),\n+\tBCM63268_GROUP(gpio45),\n+\tBCM63268_GROUP(gpio46),\n+\tBCM63268_GROUP(gpio47),\n+\tBCM63268_GROUP(gpio48),\n+\tBCM63268_GROUP(gpio49),\n+\tBCM63268_GROUP(gpio50),\n+\tBCM63268_GROUP(gpio51),\n+\n+\t/* multi pin groups */\n+\tBCM63268_GROUP(nand_grp),\n+\tBCM63268_GROUP(dectpd_grp),\n+\tBCM63268_GROUP(vdsl_phy0_grp),\n+\tBCM63268_GROUP(vdsl_phy1_grp),\n+\tBCM63268_GROUP(vdsl_phy2_grp),\n+\tBCM63268_GROUP(vdsl_phy3_grp),\n+};\n+\n+static const char * const led_groups[] = {\n+\t\"gpio0\",\n+\t\"gpio1\",\n+\t\"gpio2\",\n+\t\"gpio3\",\n+\t\"gpio4\",\n+\t\"gpio5\",\n+\t\"gpio6\",\n+\t\"gpio7\",\n+\t\"gpio8\",\n+\t\"gpio9\",\n+\t\"gpio10\",\n+\t\"gpio11\",\n+\t\"gpio12\",\n+\t\"gpio13\",\n+\t\"gpio14\",\n+\t\"gpio15\",\n+\t\"gpio16\",\n+\t\"gpio17\",\n+\t\"gpio18\",\n+\t\"gpio19\",\n+\t\"gpio20\",\n+\t\"gpio21\",\n+\t\"gpio22\",\n+\t\"gpio23\",\n+};\n+\n+static const char * const serial_led_clk_groups[] = {\n+\t\"gpio0\",\n+};\n+\n+static const char * const serial_led_data_groups[] = {\n+\t\"gpio1\",\n+};\n+\n+static const char * const hsspi_cs4_groups[] = {\n+\t\"gpio16\",\n+};\n+\n+static const char * const hsspi_cs5_groups[] = {\n+\t\"gpio17\",\n+};\n+\n+static const char * const hsspi_cs6_groups[] = {\n+\t\"gpio8\",\n+};\n+\n+static const char * const hsspi_cs7_groups[] = {\n+\t\"gpio9\",\n+};\n+\n+static const char * const uart1_scts_groups[] = {\n+\t\"gpio10\",\n+\t\"gpio24\",\n+};\n+\n+static const char * const uart1_srts_groups[] = {\n+\t\"gpio11\",\n+\t\"gpio25\",\n+};\n+\n+static const char * const uart1_sdin_groups[] = {\n+\t\"gpio12\",\n+\t\"gpio26\",\n+};\n+\n+static const char * const uart1_sdout_groups[] = {\n+\t\"gpio13\",\n+\t\"gpio27\",\n+};\n+\n+static const char * const ntr_pulse_in_groups[] = {\n+\t\"gpio14\",\n+\t\"gpio28\",\n+};\n+\n+static const char * const dsl_ntr_pulse_out_groups[] = {\n+\t\"gpio15\",\n+\t\"gpio29\",\n+};\n+\n+static const char * const adsl_spi_miso_groups[] = {\n+\t\"gpio18\",\n+};\n+\n+static const char * const adsl_spi_mosi_groups[] = {\n+\t\"gpio19\",\n+};\n+\n+static const char * const vreg_clk_groups[] = {\n+\t\"gpio22\",\n+};\n+\n+static const char * const pcie_clkreq_b_groups[] = {\n+\t\"gpio23\",\n+};\n+\n+static const char * const switch_led_clk_groups[] = {\n+\t\"gpio30\",\n+};\n+\n+static const char * const switch_led_data_groups[] = {\n+\t\"gpio31\",\n+};\n+\n+static const char * const wifi_groups[] = {\n+\t\"gpio32\",\n+\t\"gpio33\",\n+\t\"gpio34\",\n+\t\"gpio35\",\n+\t\"gpio36\",\n+\t\"gpio37\",\n+\t\"gpio38\",\n+\t\"gpio39\",\n+\t\"gpio40\",\n+\t\"gpio41\",\n+\t\"gpio42\",\n+\t\"gpio43\",\n+\t\"gpio44\",\n+\t\"gpio45\",\n+\t\"gpio46\",\n+\t\"gpio47\",\n+\t\"gpio48\",\n+\t\"gpio49\",\n+\t\"gpio50\",\n+\t\"gpio51\",\n+};\n+\n+static const char * const nand_groups[] = {\n+\t\"nand_grp\",\n+};\n+\n+static const char * const dectpd_groups[] = {\n+\t\"dectpd_grp\",\n+};\n+\n+static const char * const vdsl_phy_override_0_groups[] = {\n+\t\"vdsl_phy_override_0_grp\",\n+};\n+\n+static const char * const vdsl_phy_override_1_groups[] = {\n+\t\"vdsl_phy_override_1_grp\",\n+};\n+\n+static const char * const vdsl_phy_override_2_groups[] = {\n+\t\"vdsl_phy_override_2_grp\",\n+};\n+\n+static const char * const vdsl_phy_override_3_groups[] = {\n+\t\"vdsl_phy_override_3_grp\",\n+};\n+\n+#define BCM63268_LED_FUN(n)\t\t\t\t\\\n+\t{\t\t\t\t\t\t\\\n+\t\t.name = #n,\t\t\t\t\\\n+\t\t.groups = n##_groups,\t\t\t\\\n+\t\t.num_groups = ARRAY_SIZE(n##_groups),\t\\\n+\t\t.reg = BCM63268_LEDCTRL,\t\t\\\n+\t}\n+\n+#define BCM63268_MODE_FUN(n)\t\t\t\t\\\n+\t{\t\t\t\t\t\t\\\n+\t\t.name = #n,\t\t\t\t\\\n+\t\t.groups = n##_groups,\t\t\t\\\n+\t\t.num_groups = ARRAY_SIZE(n##_groups),\t\\\n+\t\t.reg = BCM63268_MODE,\t\t\t\\\n+\t}\n+\n+#define BCM63268_CTRL_FUN(n)\t\t\t\t\\\n+\t{\t\t\t\t\t\t\\\n+\t\t.name = #n,\t\t\t\t\\\n+\t\t.groups = n##_groups,\t\t\t\\\n+\t\t.num_groups = ARRAY_SIZE(n##_groups),\t\\\n+\t\t.reg = BCM63268_CTRL,\t\t\t\\\n+\t}\n+\n+#define BCM63268_BASEMODE_FUN(n, val)\t\t\t\\\n+\t{\t\t\t\t\t\t\\\n+\t\t.name = #n,\t\t\t\t\\\n+\t\t.groups = n##_groups,\t\t\t\\\n+\t\t.num_groups = ARRAY_SIZE(n##_groups),\t\\\n+\t\t.reg = BCM63268_BASEMODE,\t\t\\\n+\t\t.mask = val,\t\t\t\t\\\n+\t}\n+\n+static const struct bcm63268_function bcm63268_funcs[] = {\n+\tBCM63268_LED_FUN(led),\n+\tBCM63268_MODE_FUN(serial_led_clk),\n+\tBCM63268_MODE_FUN(serial_led_data),\n+\tBCM63268_MODE_FUN(hsspi_cs6),\n+\tBCM63268_MODE_FUN(hsspi_cs7),\n+\tBCM63268_MODE_FUN(uart1_scts),\n+\tBCM63268_MODE_FUN(uart1_srts),\n+\tBCM63268_MODE_FUN(uart1_sdin),\n+\tBCM63268_MODE_FUN(uart1_sdout),\n+\tBCM63268_MODE_FUN(ntr_pulse_in),\n+\tBCM63268_MODE_FUN(dsl_ntr_pulse_out),\n+\tBCM63268_MODE_FUN(hsspi_cs4),\n+\tBCM63268_MODE_FUN(hsspi_cs5),\n+\tBCM63268_MODE_FUN(adsl_spi_miso),\n+\tBCM63268_MODE_FUN(adsl_spi_mosi),\n+\tBCM63268_MODE_FUN(vreg_clk),\n+\tBCM63268_MODE_FUN(pcie_clkreq_b),\n+\tBCM63268_MODE_FUN(switch_led_clk),\n+\tBCM63268_MODE_FUN(switch_led_data),\n+\tBCM63268_CTRL_FUN(wifi),\n+\tBCM63268_BASEMODE_FUN(nand, BASEMODE_NAND),\n+\tBCM63268_BASEMODE_FUN(dectpd, BASEMODE_DECTPD),\n+\tBCM63268_BASEMODE_FUN(vdsl_phy_override_0, BASEMODE_VDSL_PHY_0),\n+\tBCM63268_BASEMODE_FUN(vdsl_phy_override_1, BASEMODE_VDSL_PHY_1),\n+\tBCM63268_BASEMODE_FUN(vdsl_phy_override_2, BASEMODE_VDSL_PHY_2),\n+\tBCM63268_BASEMODE_FUN(vdsl_phy_override_3, BASEMODE_VDSL_PHY_3),\n+};\n+\n+static int bcm63268_pinctrl_get_group_count(struct pinctrl_dev *pctldev)\n+{\n+\treturn ARRAY_SIZE(bcm63268_groups);\n+}\n+\n+static const char *bcm63268_pinctrl_get_group_name(struct pinctrl_dev *pctldev,\n+\t\t\t\t\t\t   unsigned group)\n+{\n+\treturn bcm63268_groups[group].name;\n+}\n+\n+static int bcm63268_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,\n+\t\t\t\t\t   unsigned group,\n+\t\t\t\t\t   const unsigned **pins,\n+\t\t\t\t\t   unsigned *num_pins)\n+{\n+\t*pins = bcm63268_groups[group].pins;\n+\t*num_pins = bcm63268_groups[group].num_pins;\n+\n+\treturn 0;\n+}\n+\n+static int bcm63268_pinctrl_get_func_count(struct pinctrl_dev *pctldev)\n+{\n+\treturn ARRAY_SIZE(bcm63268_funcs);\n+}\n+\n+static const char *bcm63268_pinctrl_get_func_name(struct pinctrl_dev *pctldev,\n+\t\t\t\t\t\t  unsigned selector)\n+{\n+\treturn bcm63268_funcs[selector].name;\n+}\n+\n+static int bcm63268_pinctrl_get_groups(struct pinctrl_dev *pctldev,\n+\t\t\t\t       unsigned selector,\n+\t\t\t\t       const char * const **groups,\n+\t\t\t\t       unsigned * const num_groups)\n+{\n+\t*groups = bcm63268_funcs[selector].groups;\n+\t*num_groups = bcm63268_funcs[selector].num_groups;\n+\n+\treturn 0;\n+}\n+\n+static void bcm63268_rmw_mux(struct bcm63268_pinctrl *pctl, void __iomem *reg,\n+\t\t\t     u32 mask, u32 val)\n+{\n+\tunsigned long flags;\n+\tu32 tmp;\n+\n+\tspin_lock_irqsave(&pctl->lock, flags);\n+\ttmp = __raw_readl(reg);\n+\ttmp &= ~mask;\n+\ttmp |= val;\n+\t__raw_writel(tmp, reg);\n+\n+\tspin_unlock_irqrestore(&pctl->lock, flags);\n+}\n+\n+static void bcm63268_set_gpio(struct bcm63268_pinctrl *pctl, unsigned pin)\n+{\n+\tconst struct pinctrl_pin_desc *desc = &bcm63268_pins[pin];\n+\tu32 basemode = (unsigned long)desc->drv_data;\n+\tu32 mask = BIT(pin % 32);\n+\n+\tif (basemode)\n+\t\tbcm63268_rmw_mux(pctl, pctl->basemode, basemode, 0);\n+\n+\tif (pin < 32) {\n+\t\t/* base mode: 0 => gpio, 1 => mux function */\n+\t\tbcm63268_rmw_mux(pctl, pctl->mode, mask, 0);\n+\n+\t\t/* pins 0-23 might be muxed to led */\n+\t\tif (pin < 24)\n+\t\t\tbcm63268_rmw_mux(pctl, pctl->led, mask, 0);\n+\t} else if (pin < 52) {\n+\t\t/* ctrl reg: 0 => wifi function, 1 => gpio */\n+\t\tbcm63268_rmw_mux(pctl, pctl->ctrl, mask, mask);\n+\t}\n+}\n+\n+static int bcm63268_pinctrl_set_mux(struct pinctrl_dev *pctldev,\n+\t\t\t\t    unsigned selector, unsigned group)\n+{\n+\tstruct bcm63268_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);\n+\tconst struct bcm63268_pingroup *grp = &bcm63268_groups[group];\n+\tconst struct bcm63268_function *f = &bcm63268_funcs[selector];\n+\tunsigned i;\n+\tvoid __iomem *reg;\n+\tu32 val, mask;\n+\n+\tfor (i = 0; i < grp->num_pins; i++)\n+\t\tbcm63268_set_gpio(pctl, grp->pins[i]);\n+\n+\tswitch (f->reg) {\n+\tcase BCM63268_LEDCTRL:\n+\t\treg = pctl->led;\n+\t\tmask = BIT(grp->pins[0]);\n+\t\tval = BIT(grp->pins[0]);\n+\t\tbreak;\n+\tcase BCM63268_MODE:\n+\t\treg = pctl->mode;\n+\t\tmask = BIT(grp->pins[0]);\n+\t\tval = BIT(grp->pins[0]);\n+\t\tbreak;\n+\tcase BCM63268_CTRL:\n+\t\treg = pctl->ctrl;\n+\t\tmask = BIT(grp->pins[0]);\n+\t\tval = 0;\n+\t\tbreak;\n+\tcase BCM63268_BASEMODE:\n+\t\treg = pctl->basemode;\n+\t\tmask = f->mask;\n+\t\tval = f->mask;\n+\t\tbreak;\n+\tdefault:\n+\t\tWARN_ON(1);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tbcm63268_rmw_mux(pctl, reg, mask, val);\n+\n+\treturn 0;\n+}\n+\n+static int bcm63268_gpio_request_enable(struct pinctrl_dev *pctldev,\n+\t\t\t\t\tstruct pinctrl_gpio_range *range,\n+\t\t\t\t\tunsigned offset)\n+{\n+\tstruct bcm63268_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);\n+\n+\t/* disable all functions using this pin */\n+\tbcm63268_set_gpio(pctl, offset);\n+\n+\treturn 0;\n+}\n+\n+static struct pinctrl_ops bcm63268_pctl_ops = {\n+\t.get_groups_count\t= bcm63268_pinctrl_get_group_count,\n+\t.get_group_name\t\t= bcm63268_pinctrl_get_group_name,\n+\t.get_group_pins\t\t= bcm63268_pinctrl_get_group_pins,\n+#ifdef CONFIG_OF\n+\t.dt_node_to_map\t\t= pinconf_generic_dt_node_to_map_pin,\n+\t.dt_free_map\t\t= pinctrl_utils_free_map,\n+#endif\n+};\n+\n+static struct pinmux_ops bcm63268_pmx_ops = {\n+\t.get_functions_count\t= bcm63268_pinctrl_get_func_count,\n+\t.get_function_name\t= bcm63268_pinctrl_get_func_name,\n+\t.get_function_groups\t= bcm63268_pinctrl_get_groups,\n+\t.set_mux\t\t= bcm63268_pinctrl_set_mux,\n+\t.gpio_request_enable\t= bcm63268_gpio_request_enable,\n+\t.strict\t\t\t= true,\n+};\n+\n+static int bcm63268_pinctrl_probe(struct platform_device *pdev)\n+{\n+\tstruct bcm63268_pinctrl *pctl;\n+\tstruct resource *res;\n+\tvoid __iomem *led, *mode, *ctrl, *basemode;\n+\n+\tres = platform_get_resource_byname(pdev, IORESOURCE_MEM, \"led\");\n+\tled = devm_ioremap_resource(&pdev->dev, res);\n+\tif (IS_ERR(led))\n+\t\treturn PTR_ERR(led);\n+\n+\tres = platform_get_resource_byname(pdev, IORESOURCE_MEM, \"mode\");\n+\tmode = devm_ioremap_resource(&pdev->dev, res);\n+\tif (IS_ERR(mode))\n+\t\treturn PTR_ERR(mode);\n+\n+\tres = platform_get_resource_byname(pdev, IORESOURCE_MEM, \"ctrl\");\n+\tctrl = devm_ioremap_resource(&pdev->dev, res);\n+\tif (IS_ERR(ctrl))\n+\t\treturn PTR_ERR(ctrl);\n+\n+\tres = platform_get_resource_byname(pdev, IORESOURCE_MEM, \"basemode\");\n+\tbasemode = devm_ioremap_resource(&pdev->dev, res);\n+\tif (IS_ERR(basemode))\n+\t\treturn PTR_ERR(basemode);\n+\n+\tpctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);\n+\tif (!pctl)\n+\t\treturn -ENOMEM;\n+\n+\tspin_lock_init(&pctl->lock);\n+\n+\tpctl->led = led;\n+\tpctl->mode = mode;\n+\tpctl->ctrl = ctrl;\n+\tpctl->basemode = basemode;\n+\n+\tpctl->desc.name = dev_name(&pdev->dev);\n+\tpctl->desc.owner = THIS_MODULE;\n+\tpctl->desc.pctlops = &bcm63268_pctl_ops;\n+\tpctl->desc.pmxops = &bcm63268_pmx_ops;\n+\n+\tpctl->desc.npins = ARRAY_SIZE(bcm63268_pins);\n+\tpctl->desc.pins = bcm63268_pins;\n+\n+\tplatform_set_drvdata(pdev, pctl);\n+\n+\tpctl->pctldev = bcm63xx_pinctrl_register(pdev, &pctl->desc, pctl,\n+\t\t\t\t\t\t pctl->gpio, BCM63268_NGPIO);\n+\tif (IS_ERR(pctl->pctldev))\n+\t\treturn PTR_ERR(pctl->pctldev);\n+\n+\treturn 0;\n+}\n+\n+static const struct of_device_id bcm63268_pinctrl_match[] = {\n+\t{ .compatible = \"brcm,bcm63268-pinctrl\", },\n+\t{ },\n+};\n+\n+static struct platform_driver bcm63268_pinctrl_driver = {\n+\t.probe = bcm63268_pinctrl_probe,\n+\t.driver = {\n+\t\t.name = \"bcm63268-pinctrl\",\n+\t\t.of_match_table = bcm63268_pinctrl_match,\n+\t},\n+};\n+\n+builtin_platform_driver(bcm63268_pinctrl_driver);\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/143-gpio-fix-device-tree-gpio-hogs-on-dual-role-gpio-pin.patch",
    "content": "From e058fa1969019c2f6705c53c4130e364a877d4e6 Mon Sep 17 00:00:00 2001\nFrom: Jonas Gorski <jonas.gorski@gmail.com>\nDate: Sun, 26 Nov 2017 12:07:31 +0100\nSubject: [PATCH] gpio: fix device tree gpio hogs on dual role gpio/pincontrol\n controllers\n\nFor dual role gpio and pincontrol controller, the device registration\npath is often:\n\n  pinctrl_register(...);\n  gpiochip_add_data(...);\n  gpiochip_add_pin_range(...);\n\nIf the device tree node has any gpio-hogs, the code will try to apply them\nin the gpiochip_add_data step, but fail as they cannot be requested, as the\nranges are missing. But we also cannot first add the pinranges, as the\nappropriate data structures are only initialized in gpiochip_add_data.\n\nTo fix this, defer gpio-hogs to the time pin ranges get added instead of\ndirectly at chip request time, if the gpio-chip has a request method.\n\nSigned-off-by: Jonas Gorski <jonas.gorski@gmail.com>\n---\n\n drivers/gpio/gpiolib-of.c | 20 +++++++++++++++-----\n drivers/gpio/gpiolib.c    |  5 +++--\n drivers/gpio/gpiolib.h    |  8 ++++++++\n 3 files changed, 26 insertions(+), 7 deletions(-)\n\n--- a/drivers/gpio/gpiolib-of.c\n+++ b/drivers/gpio/gpiolib-of.c\n@@ -646,23 +646,30 @@ static struct gpio_desc *of_parse_own_gp\n  * of_gpiochip_add_hog - Add all hogs in a hog device node\n  * @chip:\tgpio chip to act on\n  * @hog:\tdevice node describing the hogs\n+ * @start:\tfirst gpio to check\n+ * @num:\tnumber of gpios to check\n  *\n  * Returns error if it fails otherwise 0 on success.\n  */\n-static int of_gpiochip_add_hog(struct gpio_chip *chip, struct device_node *hog)\n+static int of_gpiochip_add_hog(struct gpio_chip *chip, struct device_node *hog,\n+\t\t\t       unsigned int start, unsigned int num)\n {\n \tenum gpiod_flags dflags;\n \tstruct gpio_desc *desc;\n \tunsigned long lflags;\n \tconst char *name;\n \tunsigned int i;\n-\tint ret;\n+\tint ret, hwgpio;\n \n \tfor (i = 0;; i++) {\n \t\tdesc = of_parse_own_gpio(hog, chip, i, &name, &lflags, &dflags);\n \t\tif (IS_ERR(desc))\n \t\t\tbreak;\n \n+\t\thwgpio = gpio_chip_hwgpio(desc);\n+\t\tif (hwgpio < start || hwgpio >= (start + num))\n+\t\t\tcontinue;\n+\n \t\tret = gpiod_hog(desc, name, lflags, dflags);\n \t\tif (ret < 0)\n \t\t\treturn ret;\n@@ -678,12 +685,15 @@ static int of_gpiochip_add_hog(struct gp\n /**\n  * of_gpiochip_scan_gpios - Scan gpio-controller for gpio definitions\n  * @chip:\tgpio chip to act on\n+ * @start:\tfirst gpio to check\n+ * @num:\tnumber of gpios to check\n  *\n- * This is only used by of_gpiochip_add to request/set GPIO initial\n- * configuration.\n+ * This is used by of_gpiochip_add, gpiochip_add_pingroup_range and\n+ * gpiochip_add_pin_range to request/set GPIO initial configuration.\n  * It returns error if it fails otherwise 0 on success.\n  */\n-static int of_gpiochip_scan_gpios(struct gpio_chip *chip)\n+int of_gpiochip_scan_gpios(struct gpio_chip *chip, unsigned int start,\n+\t\t\t   unsigned int num)\n {\n \tstruct device_node *np;\n \tint ret;\n@@ -692,7 +702,7 @@ static int of_gpiochip_scan_gpios(struct\n \t\tif (!of_property_read_bool(np, \"gpio-hog\"))\n \t\t\tcontinue;\n \n-\t\tret = of_gpiochip_add_hog(chip, np);\n+\t\tret = of_gpiochip_add_hog(chip, np, start, num);\n \t\tif (ret < 0) {\n \t\t\tof_node_put(np);\n \t\t\treturn ret;\n@@ -758,7 +768,7 @@ static int of_gpio_notify(struct notifie\n \t\tif (chip == NULL)\n \t\t\treturn NOTIFY_OK;\t/* not for us */\n \n-\t\tret = of_gpiochip_add_hog(chip, rd->dn);\n+\t\tret = of_gpiochip_add_hog(chip, rd->dn, 0, chip->ngpio);\n \t\tif (ret < 0) {\n \t\t\tpr_err(\"%s: failed to add hogs for %pOF\\n\", __func__,\n \t\t\t       rd->dn);\n@@ -1030,9 +1040,11 @@ int of_gpiochip_add(struct gpio_chip *ch\n \n \tof_node_get(chip->of_node);\n \n-\tret = of_gpiochip_scan_gpios(chip);\n-\tif (ret)\n-\t\tof_node_put(chip->of_node);\n+\tif (!chip->request) {\n+\t\tret = of_gpiochip_scan_gpios(chip, 0, chip->ngpio);\n+\t\tif (ret)\n+\t\t\tof_node_put(chip->of_node);\n+\t}\n \n \treturn ret;\n }\n--- a/drivers/gpio/gpiolib.c\n+++ b/drivers/gpio/gpiolib.c\n@@ -1912,7 +1912,8 @@ int gpiochip_add_pingroup_range(struct g\n \n \tlist_add_tail(&pin_range->node, &gdev->pin_ranges);\n \n-\treturn 0;\n+\treturn of_gpiochip_scan_gpios(gc, gpio_offset,\n+\t\t\t\t      pin_range->range.npins);\n }\n EXPORT_SYMBOL_GPL(gpiochip_add_pingroup_range);\n \n@@ -1969,7 +1970,7 @@ int gpiochip_add_pin_range(struct gpio_c\n \n \tlist_add_tail(&pin_range->node, &gdev->pin_ranges);\n \n-\treturn 0;\n+\treturn of_gpiochip_scan_gpios(gc, gpio_offset, npins);\n }\n EXPORT_SYMBOL_GPL(gpiochip_add_pin_range);\n \n--- a/drivers/gpio/gpiolib-of.h\n+++ b/drivers/gpio/gpiolib-of.h\n@@ -13,6 +13,8 @@ struct gpio_desc *of_find_gpio(struct de\n \t\t\t       unsigned long *lookupflags);\n int of_gpiochip_add(struct gpio_chip *gc);\n void of_gpiochip_remove(struct gpio_chip *gc);\n+int of_gpiochip_scan_gpios(struct gpio_chip *chip, unsigned int start,\n+\t\t\t   unsigned int num);\n int of_gpio_get_count(struct device *dev, const char *con_id);\n bool of_gpio_need_valid_mask(const struct gpio_chip *gc);\n #else\n@@ -25,6 +27,12 @@ static inline struct gpio_desc *of_find_\n }\n static inline int of_gpiochip_add(struct gpio_chip *gc) { return 0; }\n static inline void of_gpiochip_remove(struct gpio_chip *gc) { }\n+static inline int of_gpiochip_scan_gpios(struct gpio_chip *chip,\n+\t\t\t\t\t unsigned int start,\n+\t\t\t\t\t unsigned int num)\n+{\n+\treturn 0;\n+}\n static inline int of_gpio_get_count(struct device *dev, const char *con_id)\n {\n \treturn 0;\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/144-add-removed-syscon_regmap_lookup_by_pdevname.patch",
    "content": "From: Adrian Schmutzler <freifunk@adrianschmutzler.de>\nDate: Fri, 03 Apr 2020 19:50:03 +0200\nSubject: add removed helper syscon_regmap_lookup_by_pdevname\n\nThe helper syscon_regmap_lookup_by_pdevname has been removed in 29d14b668d2f\n(\"mfd: Remove unused helper syscon_regmap_lookup_by_pdevname\") due to lack\nof users.\n\nThus, we have to maintain it locally.\n\nThis patch includes a fix due to changes in driver_find_device;\nkernel commit: 92ce7e83b4e5 (\"driver_find_device: Unify the match function\nwith class_find_device()\")\n\nSigned-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>\n\n--- a/drivers/mfd/syscon.c\n+++ b/drivers/mfd/syscon.c\n@@ -205,6 +205,27 @@ struct regmap *syscon_regmap_lookup_by_c\n }\n EXPORT_SYMBOL_GPL(syscon_regmap_lookup_by_compatible);\n \n+static int syscon_match_pdevname(struct device *dev, const void *data)\n+{\n+\treturn !strcmp(dev_name(dev), (const char *)data);\n+}\n+\n+struct regmap *syscon_regmap_lookup_by_pdevname(const char *s)\n+{\n+\tstruct device *dev;\n+\tstruct syscon *syscon;\n+\n+\tdev = driver_find_device(&syscon_driver.driver, NULL, (void *)s,\n+\t\t\t\t syscon_match_pdevname);\n+\tif (!dev)\n+\t\treturn ERR_PTR(-EPROBE_DEFER);\n+\n+\tsyscon = dev_get_drvdata(dev);\n+\n+\treturn syscon->regmap;\n+}\n+EXPORT_SYMBOL_GPL(syscon_regmap_lookup_by_pdevname);\n+\n struct regmap *syscon_regmap_lookup_by_phandle(struct device_node *np,\n \t\t\t\t\tconst char *property)\n {\n--- a/include/linux/mfd/syscon.h\n+++ b/include/linux/mfd/syscon.h\n@@ -20,6 +20,7 @@ struct device_node;\n extern struct regmap *device_node_to_regmap(struct device_node *np);\n extern struct regmap *syscon_node_to_regmap(struct device_node *np);\n extern struct regmap *syscon_regmap_lookup_by_compatible(const char *s);\n+extern struct regmap *syscon_regmap_lookup_by_pdevname(const char *s);\n extern struct regmap *syscon_regmap_lookup_by_phandle(\n \t\t\t\t\tstruct device_node *np,\n \t\t\t\t\tconst char *property);\n@@ -43,6 +44,11 @@ static inline struct regmap *syscon_regm\n {\n \treturn ERR_PTR(-ENOTSUPP);\n }\n+\n+static inline struct regmap *syscon_regmap_lookup_by_pdevname(const char *s)\n+{\n+\treturn ERR_PTR(-ENOTSUPP);\n+}\n \n static inline struct regmap *syscon_regmap_lookup_by_phandle(\n \t\t\t\t\tstruct device_node *np,\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/145-pinctrl-BCM6362-fix-gpio-mode.patch",
    "content": "--- a/drivers/pinctrl/bcm63xx/pinctrl-bcm6362.c\n+++ b/drivers/pinctrl/bcm63xx/pinctrl-bcm6362.c\n@@ -566,7 +566,7 @@ static int bcm6362_pinctrl_set_mux(struc\n \t\tval = BIT(grp->pins[0]);\n \t\tbreak;\n \tcase BCM6362_MODE:\n-\t\treg = pctl->ctrl;\n+\t\treg = pctl->mode;\n \t\tmask = BIT(grp->pins[0]);\n \t\tval = BIT(grp->pins[0]);\n \t\tbreak;\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/206-USB-EHCI-allow-limiting-ports-for-ehci-platform.patch",
    "content": "From 6ac09efa8f0e189ffe7dd7b0889289de56ee44cc Mon Sep 17 00:00:00 2001\nFrom: Jonas Gorski <jogo@openwrt.org>\nDate: Sun, 19 Jan 2014 12:18:03 +0100\nSubject: [PATCH] USB: EHCI: allow limiting ports for ehci-platform\n\nIn the same way as the ohci platform driver allows limiting ports,\nenable the same for ehci. This prevents a mismatch in the available\nports between ehci/ohci on USB 2.0 controllers.\n\nThis is needed if the USB host controller always reports the maximum\nnumber of ports regardless of the number of available ports (because\none might be set to be usb device).\n\nSigned-off-by: Jonas Gorski <jogo@openwrt.org>\n---\n drivers/usb/host/ehci-hcd.c      | 4 ++++\n drivers/usb/host/ehci-platform.c | 2 ++\n drivers/usb/host/ehci.h          | 1 +\n include/linux/usb/ehci_pdriver.h | 1 +\n 4 files changed, 8 insertions(+)\n\n--- a/drivers/usb/host/ehci-hcd.c\n+++ b/drivers/usb/host/ehci-hcd.c\n@@ -687,6 +687,10 @@ int ehci_setup(struct usb_hcd *hcd)\n \n \t/* cache this readonly data; minimize chip reads */\n \tehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params);\n+\tif (ehci->num_ports) {\n+\t\tehci->hcs_params &= ~0xf; /* bits 3:0, ports on HC */\n+\t\tehci->hcs_params |= ehci->num_ports;\n+\t}\n \n \tehci->sbrn = HCD_USB2;\n \n--- a/drivers/usb/host/ehci-platform.c\n+++ b/drivers/usb/host/ehci-platform.c\n@@ -65,6 +65,9 @@ static int ehci_platform_reset(struct us\n \n \tehci->has_synopsys_hc_bug = pdata->has_synopsys_hc_bug;\n \n+\tif (pdata->num_ports && pdata->num_ports <= 15)\n+\t\tehci->num_ports = pdata->num_ports;\n+\n \tif (pdata->pre_setup) {\n \t\tretval = pdata->pre_setup(hcd);\n \t\tif (retval < 0)\n--- a/drivers/usb/host/ehci.h\n+++ b/drivers/usb/host/ehci.h\n@@ -203,6 +203,7 @@ struct ehci_hcd {\t\t\t/* one per controlle\n \tu32\t\t\tcommand;\n \n \t/* SILICON QUIRKS */\n+\tunsigned int\t\tnum_ports;\n \tunsigned\t\tno_selective_suspend:1;\n \tunsigned\t\thas_fsl_port_bug:1; /* FreeScale */\n \tunsigned\t\thas_fsl_hs_errata:1;\t/* Freescale HS quirk */\n--- a/include/linux/usb/ehci_pdriver.h\n+++ b/include/linux/usb/ehci_pdriver.h\n@@ -43,6 +43,7 @@ struct usb_hcd;\n  */\n struct usb_ehci_pdata {\n \tint\t\tcaps_offset;\n+\tunsigned int\tnum_ports;\n \tunsigned\thas_tt:1;\n \tunsigned\thas_synopsys_hc_bug:1;\n \tunsigned\tbig_endian_desc:1;\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/207-MIPS-BCM63XX-move-device-registration-code-into-its-.patch",
    "content": "From 5a50cb0d53344a2429831b00925d6183d4d332e1 Mon Sep 17 00:00:00 2001\nFrom: Jonas Gorski <jogo@openwrt.org>\nDate: Sun, 9 Mar 2014 03:54:05 +0100\nSubject: [PATCH 40/44] MIPS: BCM63XX: move device registration code into its\n own file\n\nMove device registration code into its own file to allow sharing it\nbetween board implementations.\n\nSigned-off-by: Jonas Gorski <jogo@openwrt.org>\n---\n arch/mips/bcm63xx/boards/Makefile         |   1 +\n arch/mips/bcm63xx/boards/board_bcm963xx.c | 188 +-------------------------\n arch/mips/bcm63xx/boards/board_common.c   | 215 ++++++++++++++++++++++++++++++\n arch/mips/bcm63xx/boards/board_common.h   |   8 ++\n 4 files changed, 223 insertions(+), 183 deletions(-)\n create mode 100644 arch/mips/bcm63xx/boards/board_common.c\n create mode 100644 arch/mips/bcm63xx/boards/board_common.h\n\n--- a/arch/mips/bcm63xx/boards/Makefile\n+++ b/arch/mips/bcm63xx/boards/Makefile\n@@ -1,2 +1,3 @@\n # SPDX-License-Identifier: GPL-2.0-only\n+obj-y\t\t\t\t\t+= board_common.o\n obj-$(CONFIG_BOARD_BCM963XX)\t\t+= board_bcm963xx.o\n--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c\n+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c\n@@ -9,32 +9,20 @@\n #include <linux/init.h>\n #include <linux/kernel.h>\n #include <linux/string.h>\n-#include <linux/platform_device.h>\n-#include <linux/ssb/ssb.h>\n #include <asm/addrspace.h>\n #include <bcm63xx_board.h>\n #include <bcm63xx_cpu.h>\n-#include <bcm63xx_dev_uart.h>\n #include <bcm63xx_regs.h>\n #include <bcm63xx_io.h>\n #include <bcm63xx_nvram.h>\n-#include <bcm63xx_dev_pci.h>\n-#include <bcm63xx_dev_enet.h>\n-#include <bcm63xx_dev_flash.h>\n-#include <bcm63xx_dev_hsspi.h>\n-#include <bcm63xx_dev_pcmcia.h>\n-#include <bcm63xx_dev_spi.h>\n-#include <bcm63xx_dev_usb_ehci.h>\n-#include <bcm63xx_dev_usb_ohci.h>\n-#include <bcm63xx_dev_usb_usbd.h>\n #include <board_bcm963xx.h>\n \n+#include \"board_common.h\"\n+\n #include <uapi/linux/bcm933xx_hcs.h>\n \n #define HCS_OFFSET_128K\t\t\t0x20000\n \n-static struct board_info board;\n-\n /*\n  * known 3368 boards\n  */\n@@ -679,52 +667,6 @@ static const struct board_info __initcon\n };\n \n /*\n- * Register a sane SPROMv2 to make the on-board\n- * bcm4318 WLAN work\n- */\n-#ifdef CONFIG_SSB_PCIHOST\n-static struct ssb_sprom bcm63xx_sprom = {\n-\t.revision\t\t= 0x02,\n-\t.board_rev\t\t= 0x17,\n-\t.country_code\t\t= 0x0,\n-\t.ant_available_bg\t= 0x3,\n-\t.pa0b0\t\t\t= 0x15ae,\n-\t.pa0b1\t\t\t= 0xfa85,\n-\t.pa0b2\t\t\t= 0xfe8d,\n-\t.pa1b0\t\t\t= 0xffff,\n-\t.pa1b1\t\t\t= 0xffff,\n-\t.pa1b2\t\t\t= 0xffff,\n-\t.gpio0\t\t\t= 0xff,\n-\t.gpio1\t\t\t= 0xff,\n-\t.gpio2\t\t\t= 0xff,\n-\t.gpio3\t\t\t= 0xff,\n-\t.maxpwr_bg\t\t= 0x004c,\n-\t.itssi_bg\t\t= 0x00,\n-\t.boardflags_lo\t\t= 0x2848,\n-\t.boardflags_hi\t\t= 0x0000,\n-};\n-\n-int bcm63xx_get_fallback_sprom(struct ssb_bus *bus, struct ssb_sprom *out)\n-{\n-\tif (bus->bustype == SSB_BUSTYPE_PCI) {\n-\t\tmemcpy(out, &bcm63xx_sprom, sizeof(struct ssb_sprom));\n-\t\treturn 0;\n-\t} else {\n-\t\tpr_err(\"unable to fill SPROM for given bustype\\n\");\n-\t\treturn -EINVAL;\n-\t}\n-}\n-#endif /* CONFIG_SSB_PCIHOST */\n-\n-/*\n- * return board name for /proc/cpuinfo\n- */\n-const char *board_get_name(void)\n-{\n-\treturn board.name;\n-}\n-\n-/*\n  * early init callback, read nvram data from flash and checksum it\n  */\n void __init board_prom_init(void)\n@@ -783,137 +725,15 @@ void __init board_prom_init(void)\n \t\tif (strncmp(board_name, bcm963xx_boards[i]->name, 16))\n \t\t\tcontinue;\n \t\t/* copy, board desc array is marked initdata */\n-\t\tmemcpy(&board, bcm963xx_boards[i], sizeof(board));\n+\t\tboard_early_setup(bcm963xx_boards[i]);\n \t\tbreak;\n \t}\n \n-\t/* bail out if board is not found, will complain later */\n-\tif (!board.name[0]) {\n+\t/* warn if board is not found, will complain later */\n+\tif (i == ARRAY_SIZE(bcm963xx_boards)) {\n \t\tchar name[17];\n \t\tmemcpy(name, board_name, 16);\n \t\tname[16] = 0;\n \t\tpr_err(\"unknown bcm963xx board: %s\\n\", name);\n-\t\treturn;\n-\t}\n-\n-\t/* setup pin multiplexing depending on board enabled device,\n-\t * this has to be done this early since PCI init is done\n-\t * inside arch_initcall */\n-\tval = 0;\n-\n-#ifdef CONFIG_PCI\n-\tif (board.has_pci) {\n-\t\tbcm63xx_pci_enabled = 1;\n-\t\tif (BCMCPU_IS_6348())\n-\t\t\tval |= GPIO_MODE_6348_G2_PCI;\n-\t}\n-#endif /* CONFIG_PCI */\n-\n-\tif (board.has_pccard) {\n-\t\tif (BCMCPU_IS_6348())\n-\t\t\tval |= GPIO_MODE_6348_G1_MII_PCCARD;\n-\t}\n-\n-\tif (board.has_enet0 && !board.enet0.use_internal_phy) {\n-\t\tif (BCMCPU_IS_6348())\n-\t\t\tval |= GPIO_MODE_6348_G3_EXT_MII |\n-\t\t\t\tGPIO_MODE_6348_G0_EXT_MII;\n-\t}\n-\n-\tif (board.has_enet1 && !board.enet1.use_internal_phy) {\n-\t\tif (BCMCPU_IS_6348())\n-\t\t\tval |= GPIO_MODE_6348_G3_EXT_MII |\n-\t\t\t\tGPIO_MODE_6348_G0_EXT_MII;\n-\t}\n-\n-\tbcm_gpio_writel(val, GPIO_MODE_REG);\n-}\n-\n-/*\n- * second stage init callback, good time to panic if we couldn't\n- * identify on which board we're running since early printk is working\n- */\n-void __init board_setup(void)\n-{\n-\tif (!board.name[0])\n-\t\tpanic(\"unable to detect bcm963xx board\");\n-\tpr_info(\"board name: %s\\n\", board.name);\n-\n-\t/* make sure we're running on expected cpu */\n-\tif (bcm63xx_get_cpu_id() != board.expected_cpu_id)\n-\t\tpanic(\"unexpected CPU for bcm963xx board\");\n-}\n-\n-static struct gpio_led_platform_data bcm63xx_led_data;\n-\n-static struct platform_device bcm63xx_gpio_leds = {\n-\t.name\t\t\t= \"leds-gpio\",\n-\t.id\t\t\t= 0,\n-\t.dev.platform_data\t= &bcm63xx_led_data,\n-};\n-\n-/*\n- * third stage init callback, register all board devices.\n- */\n-int __init board_register_devices(void)\n-{\n-\tif (board.has_uart0)\n-\t\tbcm63xx_uart_register(0);\n-\n-\tif (board.has_uart1)\n-\t\tbcm63xx_uart_register(1);\n-\n-\tif (board.has_pccard)\n-\t\tbcm63xx_pcmcia_register();\n-\n-\tif (board.has_enet0 &&\n-\t    !bcm63xx_nvram_get_mac_address(board.enet0.mac_addr))\n-\t\tbcm63xx_enet_register(0, &board.enet0);\n-\n-\tif (board.has_enet1 &&\n-\t    !bcm63xx_nvram_get_mac_address(board.enet1.mac_addr))\n-\t\tbcm63xx_enet_register(1, &board.enet1);\n-\n-\tif (board.has_enetsw &&\n-\t    !bcm63xx_nvram_get_mac_address(board.enetsw.mac_addr))\n-\t\tbcm63xx_enetsw_register(&board.enetsw);\n-\n-\tif (board.has_usbd)\n-\t\tbcm63xx_usbd_register(&board.usbd);\n-\n-\tif (board.has_ehci0)\n-\t\tbcm63xx_ehci_register();\n-\n-\tif (board.has_ohci0)\n-\t\tbcm63xx_ohci_register();\n-\n-\t/* Generate MAC address for WLAN and register our SPROM,\n-\t * do this after registering enet devices\n-\t */\n-#ifdef CONFIG_SSB_PCIHOST\n-\tif (!bcm63xx_nvram_get_mac_address(bcm63xx_sprom.il0mac)) {\n-\t\tmemcpy(bcm63xx_sprom.et0mac, bcm63xx_sprom.il0mac, ETH_ALEN);\n-\t\tmemcpy(bcm63xx_sprom.et1mac, bcm63xx_sprom.il0mac, ETH_ALEN);\n-\t\tif (ssb_arch_register_fallback_sprom(\n-\t\t\t\t&bcm63xx_get_fallback_sprom) < 0)\n-\t\t\tpr_err(\"failed to register fallback SPROM\\n\");\n \t}\n-#endif /* CONFIG_SSB_PCIHOST */\n-\n-\tbcm63xx_spi_register();\n-\n-\tbcm63xx_hsspi_register();\n-\n-\tbcm63xx_flash_register();\n-\n-\tbcm63xx_led_data.num_leds = ARRAY_SIZE(board.leds);\n-\tbcm63xx_led_data.leds = board.leds;\n-\n-\tplatform_device_register(&bcm63xx_gpio_leds);\n-\n-\tif (board.ephy_reset_gpio && board.ephy_reset_gpio_flags)\n-\t\tgpio_request_one(board.ephy_reset_gpio,\n-\t\t\t\tboard.ephy_reset_gpio_flags, \"ephy-reset\");\n-\n-\treturn 0;\n }\n--- /dev/null\n+++ b/arch/mips/bcm63xx/boards/board_common.c\n@@ -0,0 +1,214 @@\n+/*\n+ * This file is subject to the terms and conditions of the GNU General Public\n+ * License.  See the file \"COPYING\" in the main directory of this archive\n+ * for more details.\n+ *\n+ * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>\n+ * Copyright (C) 2008 Florian Fainelli <florian@openwrt.org>\n+ */\n+\n+#include <linux/init.h>\n+#include <linux/kernel.h>\n+#include <linux/string.h>\n+#include <linux/platform_device.h>\n+#include <linux/ssb/ssb.h>\n+#include <asm/addrspace.h>\n+#include <bcm63xx_board.h>\n+#include <bcm63xx_cpu.h>\n+#include <bcm63xx_dev_uart.h>\n+#include <bcm63xx_regs.h>\n+#include <bcm63xx_io.h>\n+#include <bcm63xx_nvram.h>\n+#include <bcm63xx_gpio.h>\n+#include <bcm63xx_dev_pci.h>\n+#include <bcm63xx_dev_enet.h>\n+#include <bcm63xx_dev_flash.h>\n+#include <bcm63xx_dev_hsspi.h>\n+#include <bcm63xx_dev_pcmcia.h>\n+#include <bcm63xx_dev_spi.h>\n+#include <bcm63xx_dev_usb_ehci.h>\n+#include <bcm63xx_dev_usb_ohci.h>\n+#include <bcm63xx_dev_usb_usbd.h>\n+#include <board_bcm963xx.h>\n+\n+#define PFX\t\"board: \"\n+\n+static struct board_info board;\n+\n+/*\n+ * Register a sane SPROMv2 to make the on-board\n+ * bcm4318 WLAN work\n+ */\n+#ifdef CONFIG_SSB_PCIHOST\n+static struct ssb_sprom bcm63xx_sprom = {\n+\t.revision\t\t= 0x02,\n+\t.board_rev\t\t= 0x17,\n+\t.country_code\t\t= 0x0,\n+\t.ant_available_bg\t= 0x3,\n+\t.pa0b0\t\t\t= 0x15ae,\n+\t.pa0b1\t\t\t= 0xfa85,\n+\t.pa0b2\t\t\t= 0xfe8d,\n+\t.pa1b0\t\t\t= 0xffff,\n+\t.pa1b1\t\t\t= 0xffff,\n+\t.pa1b2\t\t\t= 0xffff,\n+\t.gpio0\t\t\t= 0xff,\n+\t.gpio1\t\t\t= 0xff,\n+\t.gpio2\t\t\t= 0xff,\n+\t.gpio3\t\t\t= 0xff,\n+\t.maxpwr_bg\t\t= 0x004c,\n+\t.itssi_bg\t\t= 0x00,\n+\t.boardflags_lo\t\t= 0x2848,\n+\t.boardflags_hi\t\t= 0x0000,\n+};\n+\n+int bcm63xx_get_fallback_sprom(struct ssb_bus *bus, struct ssb_sprom *out)\n+{\n+\tif (bus->bustype == SSB_BUSTYPE_PCI) {\n+\t\tmemcpy(out, &bcm63xx_sprom, sizeof(struct ssb_sprom));\n+\t\treturn 0;\n+\t} else {\n+\t\tprintk(KERN_ERR PFX \"unable to fill SPROM for given bustype.\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+}\n+#endif\n+\n+/*\n+ * return board name for /proc/cpuinfo\n+ */\n+const char *board_get_name(void)\n+{\n+\treturn board.name;\n+}\n+\n+/*\n+ * setup board for device registration\n+ */\n+void __init board_early_setup(const struct board_info *target)\n+{\n+\tu32 val;\n+\n+\tmemcpy(&board, target, sizeof(board));\n+\n+\t/* setup pin multiplexing depending on board enabled device,\n+\t * this has to be done this early since PCI init is done\n+\t * inside arch_initcall */\n+\tval = 0;\n+\n+#ifdef CONFIG_PCI\n+\tif (board.has_pci) {\n+\t\tbcm63xx_pci_enabled = 1;\n+\t\tif (BCMCPU_IS_6348())\n+\t\t\tval |= GPIO_MODE_6348_G2_PCI;\n+\t}\n+#endif\n+\n+\tif (board.has_pccard) {\n+\t\tif (BCMCPU_IS_6348())\n+\t\t\tval |= GPIO_MODE_6348_G1_MII_PCCARD;\n+\t}\n+\n+\tif (board.has_enet0 && !board.enet0.use_internal_phy) {\n+\t\tif (BCMCPU_IS_6348())\n+\t\t\tval |= GPIO_MODE_6348_G3_EXT_MII |\n+\t\t\t\tGPIO_MODE_6348_G0_EXT_MII;\n+\t}\n+\n+\tif (board.has_enet1 && !board.enet1.use_internal_phy) {\n+\t\tif (BCMCPU_IS_6348())\n+\t\t\tval |= GPIO_MODE_6348_G3_EXT_MII |\n+\t\t\t\tGPIO_MODE_6348_G0_EXT_MII;\n+\t}\n+\n+\tbcm_gpio_writel(val, GPIO_MODE_REG);\n+}\n+\n+\n+/*\n+ * second stage init callback, good time to panic if we couldn't\n+ * identify on which board we're running since early printk is working\n+ */\n+void __init board_setup(void)\n+{\n+\tif (!board.name[0])\n+\t\tpanic(\"unable to detect bcm963xx board\");\n+\tprintk(KERN_INFO PFX \"board name: %s\\n\", board.name);\n+\n+\t/* make sure we're running on expected cpu */\n+\tif (bcm63xx_get_cpu_id() != board.expected_cpu_id)\n+\t\tpanic(\"unexpected CPU for bcm963xx board\");\n+}\n+\n+static struct gpio_led_platform_data bcm63xx_led_data;\n+\n+static struct platform_device bcm63xx_gpio_leds = {\n+\t.name\t\t\t= \"leds-gpio\",\n+\t.id\t\t\t= 0,\n+\t.dev.platform_data\t= &bcm63xx_led_data,\n+};\n+\n+/*\n+ * third stage init callback, register all board devices.\n+ */\n+int __init board_register_devices(void)\n+{\n+\tif (board.has_uart0)\n+\t\tbcm63xx_uart_register(0);\n+\n+\tif (board.has_uart1)\n+\t\tbcm63xx_uart_register(1);\n+\n+\tif (board.has_pccard)\n+\t\tbcm63xx_pcmcia_register();\n+\n+\tif (board.has_enet0 &&\n+\t    !bcm63xx_nvram_get_mac_address(board.enet0.mac_addr))\n+\t\tbcm63xx_enet_register(0, &board.enet0);\n+\n+\tif (board.has_enet1 &&\n+\t    !bcm63xx_nvram_get_mac_address(board.enet1.mac_addr))\n+\t\tbcm63xx_enet_register(1, &board.enet1);\n+\n+\tif (board.has_enetsw &&\n+\t    !bcm63xx_nvram_get_mac_address(board.enetsw.mac_addr))\n+\t\tbcm63xx_enetsw_register(&board.enetsw);\n+\n+\tif (board.has_usbd)\n+\t\tbcm63xx_usbd_register(&board.usbd);\n+\n+\tif (board.has_ehci0)\n+\t\tbcm63xx_ehci_register();\n+\n+\tif (board.has_ohci0)\n+\t\tbcm63xx_ohci_register();\n+\n+\t/* Generate MAC address for WLAN and register our SPROM,\n+\t * do this after registering enet devices\n+\t */\n+#ifdef CONFIG_SSB_PCIHOST\n+\tif (!bcm63xx_nvram_get_mac_address(bcm63xx_sprom.il0mac)) {\n+\t\tmemcpy(bcm63xx_sprom.et0mac, bcm63xx_sprom.il0mac, ETH_ALEN);\n+\t\tmemcpy(bcm63xx_sprom.et1mac, bcm63xx_sprom.il0mac, ETH_ALEN);\n+\t\tif (ssb_arch_register_fallback_sprom(\n+\t\t\t\t&bcm63xx_get_fallback_sprom) < 0)\n+\t\t\tpr_err(PFX \"failed to register fallback SPROM\\n\");\n+\t}\n+#endif\n+\n+\tbcm63xx_spi_register();\n+\n+\tbcm63xx_hsspi_register();\n+\n+\tbcm63xx_flash_register();\n+\n+\tbcm63xx_led_data.num_leds = ARRAY_SIZE(board.leds);\n+\tbcm63xx_led_data.leds = board.leds;\n+\n+\tplatform_device_register(&bcm63xx_gpio_leds);\n+\n+\tif (board.ephy_reset_gpio && board.ephy_reset_gpio_flags)\n+\t\tgpio_request_one(board.ephy_reset_gpio,\n+\t\t\t\tboard.ephy_reset_gpio_flags, \"ephy-reset\");\n+\n+\treturn 0;\n+}\n--- /dev/null\n+++ b/arch/mips/bcm63xx/boards/board_common.h\n@@ -0,0 +1,8 @@\n+#ifndef __BOARD_COMMON_H\n+#define __BOARD_COMMON_H\n+\n+#include <board_bcm963xx.h>\n+\n+void board_early_setup(const struct board_info *board);\n+\n+#endif /* __BOARD_COMMON_H */\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/208-MIPS-BCM63XX-pass-a-mac-addresss-allocator-to-board-.patch",
    "content": "From 4e9c34a37bd3442b286ba55441bfe22c1ac5b65f Mon Sep 17 00:00:00 2001\nFrom: Jonas Gorski <jogo@openwrt.org>\nDate: Sun, 9 Mar 2014 04:08:06 +0100\nSubject: [PATCH 41/44] MIPS: BCM63XX: pass a mac addresss allocator to board\n setup\n\nPass a mac address allocator to board setup code to allow board\nimplementations to work with third party bootloaders not using nvram\nfor configuration storage.\n\nSigned-off-by: Jonas Gorski <jogo@openwrt.org>\n---\n arch/mips/bcm63xx/boards/board_bcm963xx.c |  3 ++-\n arch/mips/bcm63xx/boards/board_common.c   | 16 ++++++++++------\n arch/mips/bcm63xx/boards/board_common.h   |  3 ++-\n 3 files changed, 14 insertions(+), 8 deletions(-)\n\n--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c\n+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c\n@@ -725,7 +725,8 @@ void __init board_prom_init(void)\n \t\tif (strncmp(board_name, bcm963xx_boards[i]->name, 16))\n \t\t\tcontinue;\n \t\t/* copy, board desc array is marked initdata */\n-\t\tboard_early_setup(bcm963xx_boards[i]);\n+\t\tboard_early_setup(bcm963xx_boards[i],\n+\t\t\t\t  bcm63xx_nvram_get_mac_address);\n \t\tbreak;\n \t}\n \n--- a/arch/mips/bcm63xx/boards/board_common.c\n+++ b/arch/mips/bcm63xx/boards/board_common.c\n@@ -18,7 +18,6 @@\n #include <bcm63xx_dev_uart.h>\n #include <bcm63xx_regs.h>\n #include <bcm63xx_io.h>\n-#include <bcm63xx_nvram.h>\n #include <bcm63xx_gpio.h>\n #include <bcm63xx_dev_pci.h>\n #include <bcm63xx_dev_enet.h>\n@@ -81,15 +80,20 @@ const char *board_get_name(void)\n \treturn board.name;\n }\n \n+static int (*board_get_mac_address)(u8 mac[ETH_ALEN]);\n+\n /*\n  * setup board for device registration\n  */\n-void __init board_early_setup(const struct board_info *target)\n+void __init board_early_setup(const struct board_info *target,\n+\t\t\t      int (*get_mac_address)(u8 mac[ETH_ALEN]))\n {\n \tu32 val;\n \n \tmemcpy(&board, target, sizeof(board));\n \n+\tboard_get_mac_address = get_mac_address;\n+\n \t/* setup pin multiplexing depending on board enabled device,\n \t * this has to be done this early since PCI init is done\n \t * inside arch_initcall */\n@@ -162,15 +166,15 @@ int __init board_register_devices(void)\n \t\tbcm63xx_pcmcia_register();\n \n \tif (board.has_enet0 &&\n-\t    !bcm63xx_nvram_get_mac_address(board.enet0.mac_addr))\n+\t    !board_get_mac_address(board.enet0.mac_addr))\n \t\tbcm63xx_enet_register(0, &board.enet0);\n \n \tif (board.has_enet1 &&\n-\t    !bcm63xx_nvram_get_mac_address(board.enet1.mac_addr))\n+\t    !board_get_mac_address(board.enet1.mac_addr))\n \t\tbcm63xx_enet_register(1, &board.enet1);\n \n \tif (board.has_enetsw &&\n-\t    !bcm63xx_nvram_get_mac_address(board.enetsw.mac_addr))\n+\t    !board_get_mac_address(board.enetsw.mac_addr))\n \t\tbcm63xx_enetsw_register(&board.enetsw);\n \n \tif (board.has_usbd)\n@@ -186,7 +190,7 @@ int __init board_register_devices(void)\n \t * do this after registering enet devices\n \t */\n #ifdef CONFIG_SSB_PCIHOST\n-\tif (!bcm63xx_nvram_get_mac_address(bcm63xx_sprom.il0mac)) {\n+\tif (!board_get_mac_address(bcm63xx_sprom.il0mac)) {\n \t\tmemcpy(bcm63xx_sprom.et0mac, bcm63xx_sprom.il0mac, ETH_ALEN);\n \t\tmemcpy(bcm63xx_sprom.et1mac, bcm63xx_sprom.il0mac, ETH_ALEN);\n \t\tif (ssb_arch_register_fallback_sprom(\n--- a/arch/mips/bcm63xx/boards/board_common.h\n+++ b/arch/mips/bcm63xx/boards/board_common.h\n@@ -3,6 +3,7 @@\n \n #include <board_bcm963xx.h>\n \n-void board_early_setup(const struct board_info *board);\n+void board_early_setup(const struct board_info *board,\n+\t\t       int (*get_mac_address)(u8 mac[ETH_ALEN]));\n \n #endif /* __BOARD_COMMON_H */\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/320-irqchip-add-support-for-bcm6345-style-periphery-irq-.patch",
    "content": "From 301744ecbeece89ab3a9d6beef7802fa22598f00 Mon Sep 17 00:00:00 2001\nFrom: Jonas Gorski <jogo@openwrt.org>\nDate: Sun, 30 Nov 2014 14:53:12 +0100\nSubject: [PATCH 1/5] irqchip: add support for bcm6345-style periphery irq\n controller\n\nSigned-off-by: Jonas Gorski <jogo@openwrt.org>\n---\n .../brcm,bcm6345-periph-intc.txt                   |   50 +++\n drivers/irqchip/Kconfig                            |    4 +\n drivers/irqchip/Makefile                           |    1 +\n drivers/irqchip/irq-bcm6345-periph.c               |  339 ++++++++++++++++++++\n include/linux/irqchip/irq-bcm6345-periph.h         |   16 +\n 5 files changed, 410 insertions(+)\n create mode 100644 Documentation/devicetree/bindings/interrupt-controller/brcm,bcm6345-periph-intc.txt\n create mode 100644 drivers/irqchip/irq-bcm6345-periph.c\n create mode 100644 include/linux/irqchip/irq-bcm6345-periph.h\n\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm6345-periph-intc.txt\n@@ -0,0 +1,50 @@\n+Broadcom BCM6345 Level 1 periphery interrupt controller\n+\n+This block is a  interrupt controller that is typically connected directly\n+to one of the HW INT lines on each CPU.  Every BCM63XX xDSL chip since\n+BCM6345 has contained this hardware.\n+\n+Key elements of the hardware design include:\n+\n+- 32, 64, or 128 incoming level IRQ lines\n+\n+- All onchip peripherals are wired directly to an L2 input\n+\n+- A separate instance of the register set for each CPU, allowing individual\n+  peripheral IRQs to be routed to any CPU\n+\n+- No atomic mask/unmask operations\n+\n+- No polarity/level/edge settings\n+\n+- No FIFO or priority encoder logic; software is expected to read all\n+  1-4 status words to determine which IRQs are pending\n+\n+Required properties:\n+\n+- compatible: Should be \"brcm,bcm6345-periph-intc\".\n+- reg: Specifies the base physical address and size of the registers.\n+  Multiple register addresses may be specified, and must match the amount of\n+  parent interrupts.\n+- interrupt-controller: Identifies the node as an interrupt controller.\n+- #interrupt-cells: Specifies the number of cells needed to encode an interrupt\n+  source, should be 1.\n+- interrupt-parent: Specifies the phandle to the parent interrupt controller\n+  this one is cascaded from.\n+- interrupts: Specifies the interrupt line(s) in the interrupt-parent controller\n+  node, valid values depend on the type of parent interrupt controller.\n+  Multiple lines are used to route interrupts to different cpus, with the first\n+  assumed to be for the boot CPU.\n+\n+Example:\n+\n+periph_intc: interrupt-controller@f0406800 {\n+\tcompatible = \"brcm,bcm6345-periph-intc\";\n+\treg = <0x10000020 0x10>, <0x10000030 0x10>;\n+\n+\tinterrupt-controller;\n+\t#interrupt-cells = <1>;\n+\n+\tinterrupt-parent = <&cpu_intc>;\n+\tinterrupts = <2>, <3>;\n+};\n--- a/drivers/irqchip/Kconfig\n+++ b/drivers/irqchip/Kconfig\n@@ -145,6 +145,10 @@ config DAVINCI_CP_INTC\n \tselect GENERIC_IRQ_CHIP\n \tselect IRQ_DOMAIN\n \n+config BCM6345_PERIPH_IRQ\n+\tbool\n+\tselect IRQ_DOMAIN\n+\n config DW_APB_ICTL\n \tbool\n \tselect GENERIC_IRQ_CHIP\n--- a/drivers/irqchip/Makefile\n+++ b/drivers/irqchip/Makefile\n@@ -17,6 +17,7 @@ obj-$(CONFIG_ARCH_LPC32XX)\t\t+= irq-lpc32\n obj-$(CONFIG_ARCH_MMP)\t\t\t+= irq-mmp.o\n obj-$(CONFIG_IRQ_MXS)\t\t\t+= irq-mxs.o\n obj-$(CONFIG_ARCH_TEGRA)\t\t+= irq-tegra.o\n+obj-$(CONFIG_BCM6345_PERIPH_IRQ)\t+= irq-bcm6345-periph.o\n obj-$(CONFIG_DW_APB_ICTL)\t\t+= irq-dw-apb-ictl.o\n obj-$(CONFIG_CLPS711X_IRQCHIP)\t\t+= irq-clps711x.o\n obj-$(CONFIG_OMPIC)\t\t\t+= irq-ompic.o\n--- /dev/null\n+++ b/drivers/irqchip/irq-bcm6345-periph.c\n@@ -0,0 +1,339 @@\n+/*\n+ * This file is subject to the terms and conditions of the GNU General Public\n+ * License.  See the file \"COPYING\" in the main directory of this archive\n+ * for more details.\n+ *\n+ * Copyright (C) 2014 Jonas Gorski <jogo@openwrt.org>\n+ */\n+\n+#include <linux/ioport.h>\n+#include <linux/irq.h>\n+#include <linux/irqchip.h>\n+#include <linux/irqchip/chained_irq.h>\n+#include <linux/irqchip/irq-bcm6345-periph.h>\n+#include <linux/kernel.h>\n+#include <linux/of.h>\n+#include <linux/of_irq.h>\n+#include <linux/of_address.h>\n+#include <linux/slab.h>\n+#include <linux/spinlock.h>\n+\n+#ifdef CONFIG_BCM63XX\n+#include <asm/mach-bcm63xx/bcm63xx_irq.h>\n+\n+#define VIRQ_BASE\tIRQ_INTERNAL_BASE\n+#else\n+#define VIRQ_BASE\t0\n+#endif\n+\n+#define MAX_WORDS\t4\n+#define MAX_PARENT_IRQS\t2\n+#define IRQS_PER_WORD\t32\n+\n+struct intc_block {\n+\tint parent_irq;\n+\tvoid __iomem *base;\n+\tvoid __iomem *en_reg[MAX_WORDS];\n+\tvoid __iomem *status_reg[MAX_WORDS];\n+\tu32 mask_cache[MAX_WORDS];\n+};\n+\n+struct intc_data {\n+\tstruct irq_chip chip;\n+\tstruct intc_block block[MAX_PARENT_IRQS];\n+\n+\tint num_words;\n+\n+\tstruct irq_domain *domain;\n+\traw_spinlock_t lock;\n+};\n+\n+static void bcm6345_periph_irq_handle(struct irq_desc *desc)\n+{\n+\tstruct intc_data *data = irq_desc_get_handler_data(desc);\n+\tstruct irq_chip *chip = irq_desc_get_chip(desc);\n+\tstruct intc_block *block;\n+\tunsigned int irq = irq_desc_get_irq(desc);\n+\tunsigned int idx;\n+\n+\tchained_irq_enter(chip, desc);\n+\n+\tfor (idx = 0; idx < MAX_PARENT_IRQS; idx++)\n+\t\tif (irq == data->block[idx].parent_irq)\n+\t\t\tblock = &data->block[idx];\n+\n+\tfor (idx = 0; idx < data->num_words; idx++) {\n+\t\tint base = idx * IRQS_PER_WORD;\n+\t\tunsigned long pending;\n+\t\tint hw_irq;\n+\n+\t\traw_spin_lock(&data->lock);\n+\t\tpending = __raw_readl(block->en_reg[idx]) &\n+\t\t\t  __raw_readl(block->status_reg[idx]);\n+\t\traw_spin_unlock(&data->lock);\n+\n+\t\tfor_each_set_bit(hw_irq, &pending, IRQS_PER_WORD) {\n+\t\t\tint virq;\n+\n+\t\t\tvirq  = irq_find_mapping(data->domain, base + hw_irq);\n+\t\t\tgeneric_handle_irq(virq);\n+\t\t}\n+\t}\n+\n+\tchained_irq_exit(chip, desc);\n+}\n+\n+static void __bcm6345_periph_enable(struct intc_block *block, int reg, int bit,\n+\t\t\t\t    bool enable)\n+{\n+\tu32 val;\n+\n+\tval = __raw_readl(block->en_reg[reg]);\n+\tif (enable)\n+\t\tval |= BIT(bit);\n+\telse\n+\t\tval &= ~BIT(bit);\n+\t__raw_writel(val, block->en_reg[reg]);\n+}\n+\n+static void bcm6345_periph_irq_mask(struct irq_data *data)\n+{\n+\tunsigned int i, reg, bit;\n+\tstruct intc_data *priv = data->domain->host_data;\n+\tirq_hw_number_t hwirq = irqd_to_hwirq(data);\n+\n+\treg = hwirq / IRQS_PER_WORD;\n+\tbit = hwirq % IRQS_PER_WORD;\n+\n+\traw_spin_lock(&priv->lock);\n+\tfor (i = 0; i < MAX_PARENT_IRQS; i++) {\n+\t\tstruct intc_block *block = &priv->block[i];\n+\n+\t\tif (!block->parent_irq)\n+\t\t\tbreak;\n+\n+\t\t__bcm6345_periph_enable(block, reg, bit, false);\n+\t}\n+\traw_spin_unlock(&priv->lock);\n+}\n+\n+static void bcm6345_periph_irq_unmask(struct irq_data *data)\n+{\n+\tstruct intc_data *priv = data->domain->host_data;\n+\tirq_hw_number_t hwirq = irqd_to_hwirq(data);\n+\tunsigned int i, reg, bit;\n+\n+\treg = hwirq / IRQS_PER_WORD;\n+\tbit = hwirq % IRQS_PER_WORD;\n+\n+\traw_spin_lock(&priv->lock);\n+\tfor (i = 0; i < MAX_PARENT_IRQS; i++) {\n+\t\tstruct intc_block *block = &priv->block[i];\n+\n+\t\tif (!block->parent_irq)\n+\t\t\tbreak;\n+\n+\t\tif (block->mask_cache[reg] & BIT(bit))\n+\t\t\t__bcm6345_periph_enable(block, reg, bit, true);\n+\t\telse\n+\t\t\t__bcm6345_periph_enable(block, reg, bit, false);\n+\t}\n+\traw_spin_unlock(&priv->lock);\n+}\n+\n+#ifdef CONFIG_SMP\n+static int bcm6345_periph_set_affinity(struct irq_data *data,\n+\t\t\t\t       const struct cpumask *mask, bool force)\n+{\n+\tirq_hw_number_t hwirq = irqd_to_hwirq(data);\n+\tstruct intc_data *priv = data->domain->host_data;\n+\tunsigned int i, reg, bit;\n+\tunsigned long flags;\n+\tbool enabled;\n+\tint cpu;\n+\n+\treg = hwirq / IRQS_PER_WORD;\n+\tbit = hwirq % IRQS_PER_WORD;\n+\n+\t/* we could route to more than one cpu, but performance\n+\t   suffers, so fix it to one.\n+\t */\n+\tcpu = cpumask_any_and(mask, cpu_online_mask);\n+\tif (cpu >= nr_cpu_ids)\n+\t\treturn -EINVAL;\n+\n+\tif (cpu >= MAX_PARENT_IRQS)\n+\t\treturn -EINVAL;\n+\n+\tif (!priv->block[cpu].parent_irq)\n+\t\treturn -EINVAL;\n+\n+\traw_spin_lock_irqsave(&priv->lock, flags);\n+\tenabled = !irqd_irq_masked(data);\n+\tfor (i = 0; i < MAX_PARENT_IRQS; i++) {\n+\t\tstruct intc_block *block = &priv->block[i];\n+\n+\t\tif (!block->parent_irq)\n+\t\t\tbreak;\n+\n+\t\tif (i == cpu) {\n+\t\t\tblock->mask_cache[reg] |= BIT(bit);\n+\t\t\t__bcm6345_periph_enable(block, reg, bit, enabled);\n+\t\t} else {\n+\t\t\tblock->mask_cache[reg] &= ~BIT(bit);\n+\t\t\t__bcm6345_periph_enable(block, reg, bit, false);\n+\t\t}\n+\t}\n+\traw_spin_unlock_irqrestore(&priv->lock, flags);\n+\n+\treturn 0;\n+}\n+#endif\n+\n+static int bcm6345_periph_map(struct irq_domain *d, unsigned int irq,\n+\t\t\t      irq_hw_number_t hw)\n+{\n+\tstruct intc_data *priv = d->host_data;\n+\n+\tirq_set_chip_and_handler(irq, &priv->chip, handle_level_irq);\n+\n+\treturn 0;\n+}\n+\n+static const struct irq_domain_ops bcm6345_periph_domain_ops = {\n+\t.xlate = irq_domain_xlate_onecell,\n+\t.map = bcm6345_periph_map,\n+};\n+\n+static int __init __bcm6345_periph_intc_init(struct device_node *node,\n+\t\t\t\t\t     int num_blocks, int *irq,\n+\t\t\t\t\t     void __iomem **base, int num_words)\n+{\n+\tstruct intc_data *data;\n+\tunsigned int i, w, status_offset;\n+\n+\tdata = kzalloc(sizeof(*data), GFP_KERNEL);\n+\tif (!data)\n+\t\treturn -ENOMEM;\n+\n+\traw_spin_lock_init(&data->lock);\n+\n+\tstatus_offset = num_words * sizeof(u32);\n+\n+\tfor (i = 0; i < num_blocks; i++) {\n+\t\tstruct intc_block *block = &data->block[i];\n+\n+\t\tblock->parent_irq = irq[i];\n+\t\tblock->base = base[i];\n+\n+\t\tfor (w = 0; w < num_words; w++) {\n+\t\t\tint word_offset = sizeof(u32) * ((num_words - w) - 1);\n+\n+\t\t\tblock->en_reg[w] = base[i] + word_offset;\n+\t\t\tblock->status_reg[w] = base[i] + status_offset;\n+\t\t\tblock->status_reg[w] += word_offset;\n+\n+\t\t\t/* route all interrupts to line 0 by default */\n+\t\t\tif (i == 0)\n+\t\t\t\tblock->mask_cache[w] = 0xffffffff;\n+\t\t}\n+\n+\t\tirq_set_handler_data(block->parent_irq, data);\n+\t\tirq_set_chained_handler(block->parent_irq,\n+\t\t\t\t\tbcm6345_periph_irq_handle);\n+\t}\n+\n+\tdata->num_words = num_words;\n+\n+\tdata->chip.name = \"bcm6345-periph-intc\";\n+\tdata->chip.irq_mask = bcm6345_periph_irq_mask;\n+\tdata->chip.irq_unmask = bcm6345_periph_irq_unmask;\n+\n+#ifdef CONFIG_SMP\n+\tif (num_blocks > 1)\n+\t\tdata->chip.irq_set_affinity = bcm6345_periph_set_affinity;\n+#endif\n+\n+\tdata->domain = irq_domain_add_simple(node, IRQS_PER_WORD * num_words,\n+\t\t\t\t\t     VIRQ_BASE,\n+\t\t\t\t\t     &bcm6345_periph_domain_ops, data);\n+\tif (!data->domain) {\n+\t\tkfree(data);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+void __init bcm6345_periph_intc_init(int num_blocks, int *irq,\n+\t\t\t\t     void __iomem **base, int num_words)\n+{\n+\t__bcm6345_periph_intc_init(NULL, num_blocks, irq, base, num_words);\n+}\n+\n+#ifdef CONFIG_OF\n+static int __init bcm6345_periph_of_init(struct device_node *node,\n+\t\t\t\t\t struct device_node *parent)\n+{\n+\tstruct resource res;\n+\tint num_irqs, ret = -EINVAL;\n+\tint irqs[MAX_PARENT_IRQS] = { 0 };\n+\tvoid __iomem *bases[MAX_PARENT_IRQS] = { NULL };\n+\tint words = 0;\n+\tint i;\n+\n+\tnum_irqs = of_irq_count(node);\n+\n+\tif (num_irqs < 1 || num_irqs > MAX_PARENT_IRQS)\n+\t\treturn -EINVAL;\n+\n+\tfor (i = 0; i < num_irqs; i++) {\n+\t\tresource_size_t size;\n+\n+\t\tirqs[i] = irq_of_parse_and_map(node, i);\n+\t\tif (!irqs[i])\n+\t\t\tgoto out_unmap;\n+\n+\t\tif (of_address_to_resource(node, i, &res))\n+\t\t\tgoto out_unmap;\n+\n+\t\tsize = resource_size(&res);\n+\t\tswitch (size) {\n+\t\tcase 8:\n+\t\tcase 16:\n+\t\tcase 32:\n+\t\t\tsize = size / 8;\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tgoto out_unmap;\n+\t\t}\n+\n+\t\tif (words && words != size) {\n+\t\t\tret = -EINVAL;\n+\t\t\tgoto out_unmap;\n+\t\t}\n+\t\twords = size;\n+\n+\t\tbases[i] = of_iomap(node, i);\n+\t\tif (!bases[i]) {\n+\t\t\tret = -ENOMEM;\n+\t\t\tgoto out_unmap;\n+\t\t}\n+\t}\n+\n+\tret = __bcm6345_periph_intc_init(node, num_irqs, irqs, bases, words);\n+\tif (!ret)\n+\t\treturn 0;\n+\n+out_unmap:\n+\tfor (i = 0; i < num_irqs; i++) {\n+\t\tiounmap(bases[i]);\n+\t\tirq_dispose_mapping(irqs[i]);\n+\t}\n+\n+\treturn ret;\n+}\n+\n+IRQCHIP_DECLARE(bcm6345_periph_intc, \"brcm,bcm6345-l1-intc\",\n+\t\tbcm6345_periph_of_init);\n+#endif\n--- /dev/null\n+++ b/include/linux/irqchip/irq-bcm6345-periph.h\n@@ -0,0 +1,16 @@\n+/*\n+ * This file is subject to the terms and conditions of the GNU General Public\n+ * License.  See the file \"COPYING\" in the main directory of this archive\n+ * for more details.\n+ *\n+ * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>\n+ * Copyright (C) 2008 Nicolas Schichan <nschichan@freebox.fr>\n+ */\n+\n+#ifndef __INCLUDE_LINUX_IRQCHIP_IRQ_BCM6345_PERIPH_H\n+#define __INCLUDE_LINUX_IRQCHIP_IRQ_BCM6345_PERIPH_H\n+\n+void bcm6345_periph_intc_init(int num_blocks, int *irq, void __iomem **base,\n+\t\t\t      int num_words);\n+\n+#endif /* __INCLUDE_LINUX_IRQCHIP_IRQ_BCM6345_PERIPH_H */\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/321-irqchip-add-support-for-bcm6345-style-external-inter.patch",
    "content": "From cf908990d4a8ccdb73ee4484aa8cadad379ca314 Mon Sep 17 00:00:00 2001\nFrom: Jonas Gorski <jogo@openwrt.org>\nDate: Sun, 30 Nov 2014 14:54:27 +0100\nSubject: [PATCH 2/5] irqchip: add support for bcm6345-style external\n interrupt controller\n\nSigned-off-by: Jonas Gorski <jogo@openwrt.org>\n---\n .../interrupt-controller/brcm,bcm6345-ext-intc.txt |   29 ++\n drivers/irqchip/Kconfig                            |    4 +\n drivers/irqchip/Makefile                           |    1 +\n drivers/irqchip/irq-bcm6345-ext.c                  |  287 ++++++++++++++++++++\n include/linux/irqchip/irq-bcm6345-ext.h            |   14 +\n 5 files changed, 335 insertions(+)\n create mode 100644 Documentation/devicetree/bindings/interrupt-controller/brcm,bcm6345-ext-intc.txt\n create mode 100644 drivers/irqchip/irq-bcm6345-ext.c\n create mode 100644 include/linux/irqchip/irq-bcm6345-ext.h\n\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm6345-ext-intc.txt\n@@ -0,0 +1,29 @@\n+Broadcom BCM6345-style external interrupt controller\n+\n+Required properties:\n+\n+- compatible: Should be \"brcm,bcm6345-ext-intc\" or \"brcm,bcm6318-ext-intc\".\n+- reg: Specifies the base physical addresses and size of the registers.\n+- interrupt-controller: identifies the node as an interrupt controller.\n+- #interrupt-cells: Specifies the number of cells needed to encode an interrupt\n+  source, Should be 2.\n+- interrupt-parent: Specifies the phandle to the parent interrupt controller\n+  this one is cascaded from.\n+- interrupts: Specifies the interrupt line(s) in the interrupt-parent controller\n+  node, valid values depend on the type of parent interrupt controller.\n+\n+Optional properties:\n+\n+- brcm,field-width: Size of each field (mask, clear, sense, ...) in bits in the\n+  register. Defaults to 4.\n+\n+Example:\n+\n+ext_intc: interrupt-controller@10000018 {\n+\tcompatible = \"brcm,bcm6345-ext-intc\";\n+\tinterrupt-parent = <&periph_intc>;\n+\t#interrupt-cells = <2>;\n+\treg = <0x10000018 0x4>;\n+\tinterrupt-controller;\n+\tinterrupts = <24>, <25>, <26>, <27>;\n+};\n--- a/drivers/irqchip/Kconfig\n+++ b/drivers/irqchip/Kconfig\n@@ -145,6 +145,10 @@ config DAVINCI_CP_INTC\n \tselect GENERIC_IRQ_CHIP\n \tselect IRQ_DOMAIN\n \n+config BCM6345_EXT_IRQ\n+\tbool\n+\tselect IRQ_DOMAIN\n+\n config BCM6345_PERIPH_IRQ\n \tbool\n \tselect IRQ_DOMAIN\n--- a/drivers/irqchip/Makefile\n+++ b/drivers/irqchip/Makefile\n@@ -17,6 +17,7 @@ obj-$(CONFIG_ARCH_LPC32XX)\t\t+= irq-lpc32\n obj-$(CONFIG_ARCH_MMP)\t\t\t+= irq-mmp.o\n obj-$(CONFIG_IRQ_MXS)\t\t\t+= irq-mxs.o\n obj-$(CONFIG_ARCH_TEGRA)\t\t+= irq-tegra.o\n+obj-$(CONFIG_BCM6345_EXT_IRQ)\t\t+= irq-bcm6345-ext.o\n obj-$(CONFIG_BCM6345_PERIPH_IRQ)\t+= irq-bcm6345-periph.o\n obj-$(CONFIG_DW_APB_ICTL)\t\t+= irq-dw-apb-ictl.o\n obj-$(CONFIG_CLPS711X_IRQCHIP)\t\t+= irq-clps711x.o\n--- /dev/null\n+++ b/drivers/irqchip/irq-bcm6345-ext.c\n@@ -0,0 +1,301 @@\n+/*\n+ * This file is subject to the terms and conditions of the GNU General Public\n+ * License.  See the file \"COPYING\" in the main directory of this archive\n+ * for more details.\n+ *\n+ * Copyright (C) 2014 Jonas Gorski <jogo@openwrt.org>\n+ */\n+\n+#include <linux/ioport.h>\n+#include <linux/irq.h>\n+#include <linux/irqchip.h>\n+#include <linux/irqchip/chained_irq.h>\n+#include <linux/irqchip/irq-bcm6345-ext.h>\n+#include <linux/kernel.h>\n+#include <linux/of.h>\n+#include <linux/of_irq.h>\n+#include <linux/of_address.h>\n+#include <linux/slab.h>\n+#include <linux/spinlock.h>\n+\n+#ifdef CONFIG_BCM63XX\n+#include <asm/mach-bcm63xx/bcm63xx_irq.h>\n+\n+#define VIRQ_BASE\t\tIRQ_EXTERNAL_BASE\n+#else\n+#define VIRQ_BASE\t\t0\n+#endif\n+\n+#define MAX_IRQS\t\t4\n+\n+#define EXTIRQ_CFG_SENSE\t0\n+#define EXTIRQ_CFG_STAT\t\t1\n+#define EXTIRQ_CFG_CLEAR\t2\n+#define EXTIRQ_CFG_MASK\t\t3\n+#define EXTIRQ_CFG_BOTHEDGE\t4\n+#define EXTIRQ_CFG_LEVELSENSE\t5\n+\n+struct intc_data {\n+\tstruct irq_chip chip;\n+\tstruct irq_domain *domain;\n+\traw_spinlock_t lock;\n+\n+\tint parent_irq[MAX_IRQS];\n+\tvoid __iomem *reg;\n+\tint shift;\n+\tunsigned int toggle_clear_on_ack:1;\n+};\n+\n+static void bcm6345_ext_intc_irq_handle(struct irq_desc *desc)\n+{\n+\tstruct intc_data *data = irq_desc_get_handler_data(desc);\n+\tstruct irq_chip *chip = irq_desc_get_chip(desc);\n+\tunsigned int irq = irq_desc_get_irq(desc);\n+\tunsigned int idx;\n+\n+\tchained_irq_enter(chip, desc);\n+\n+\tfor (idx = 0; idx < MAX_IRQS; idx++) {\n+\t\tif (data->parent_irq[idx] != irq)\n+\t\t\tcontinue;\n+\n+\t\tgeneric_handle_irq(irq_find_mapping(data->domain, idx));\n+\t}\n+\n+\tchained_irq_exit(chip, desc);\n+}\n+\n+static void bcm6345_ext_intc_irq_ack(struct irq_data *data)\n+{\n+\tstruct intc_data *priv = data->domain->host_data;\n+\tirq_hw_number_t hwirq = irqd_to_hwirq(data);\n+\tu32 reg;\n+\n+\traw_spin_lock(&priv->lock);\n+\treg = __raw_readl(priv->reg);\n+\t__raw_writel(reg | (1 << (hwirq + EXTIRQ_CFG_CLEAR * priv->shift)),\n+\t\t     priv->reg);\n+\tif (priv->toggle_clear_on_ack)\n+\t\t__raw_writel(reg, priv->reg);\n+\traw_spin_unlock(&priv->lock);\n+}\n+\n+static void bcm6345_ext_intc_irq_mask(struct irq_data *data)\n+{\n+\tstruct intc_data *priv = data->domain->host_data;\n+\tirq_hw_number_t hwirq = irqd_to_hwirq(data);\n+\tu32 reg;\n+\n+\traw_spin_lock(&priv->lock);\n+\treg = __raw_readl(priv->reg);\n+\treg &= ~(1 << (hwirq + EXTIRQ_CFG_MASK * priv->shift));\n+\t__raw_writel(reg, priv->reg);\n+\traw_spin_unlock(&priv->lock);\n+}\n+\n+static void bcm6345_ext_intc_irq_unmask(struct irq_data *data)\n+{\n+\tstruct intc_data *priv = data->domain->host_data;\n+\tirq_hw_number_t hwirq = irqd_to_hwirq(data);\n+\tu32 reg;\n+\n+\traw_spin_lock(&priv->lock);\n+\treg = __raw_readl(priv->reg);\n+\treg |= 1 << (hwirq + EXTIRQ_CFG_MASK * priv->shift);\n+\t__raw_writel(reg, priv->reg);\n+\traw_spin_unlock(&priv->lock);\n+}\n+\n+static int bcm6345_ext_intc_set_type(struct irq_data *data,\n+\t\t\t\t     unsigned int flow_type)\n+{\n+\tstruct intc_data *priv = data->domain->host_data;\n+\tirq_hw_number_t hwirq = irqd_to_hwirq(data);\n+\tbool levelsense = 0, sense = 0, bothedge = 0;\n+\tu32 reg;\n+\n+\tflow_type &= IRQ_TYPE_SENSE_MASK;\n+\n+\tif (flow_type == IRQ_TYPE_NONE)\n+\t\tflow_type = IRQ_TYPE_LEVEL_LOW;\n+\n+\tswitch (flow_type) {\n+\tcase IRQ_TYPE_EDGE_BOTH:\n+\t\tbothedge = 1;\n+\t\tbreak;\n+\n+\tcase IRQ_TYPE_EDGE_RISING:\n+\t\tsense = 1;\n+\t\tbreak;\n+\n+\tcase IRQ_TYPE_EDGE_FALLING:\n+\t\tbreak;\n+\n+\tcase IRQ_TYPE_LEVEL_HIGH:\n+\t\tlevelsense = 1;\n+\t\tsense = 1;\n+\t\tbreak;\n+\n+\tcase IRQ_TYPE_LEVEL_LOW:\n+\t\tlevelsense = 1;\n+\t\tbreak;\n+\n+\tdefault:\n+\t\tpr_err(\"bogus flow type combination given!\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\traw_spin_lock(&priv->lock);\n+\treg = __raw_readl(priv->reg);\n+\n+\tif (levelsense)\n+\t\treg |= 1 << (hwirq + EXTIRQ_CFG_LEVELSENSE * priv->shift);\n+\telse\n+\t\treg &= ~(1 << (hwirq + EXTIRQ_CFG_LEVELSENSE * priv->shift));\n+\tif (sense)\n+\t\treg |= 1 << (hwirq + EXTIRQ_CFG_SENSE * priv->shift);\n+\telse\n+\t\treg &= ~(1 << (hwirq + EXTIRQ_CFG_SENSE * priv->shift));\n+\tif (bothedge)\n+\t\treg |= 1 << (hwirq + EXTIRQ_CFG_BOTHEDGE * priv->shift);\n+\telse\n+\t\treg &= ~(1 << (hwirq + EXTIRQ_CFG_BOTHEDGE * priv->shift));\n+\n+\t__raw_writel(reg, priv->reg);\n+\traw_spin_unlock(&priv->lock);\n+\n+\tirqd_set_trigger_type(data, flow_type);\n+\tif (flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))\n+\t\tirq_set_handler_locked(data, handle_level_irq);\n+\telse\n+\t\tirq_set_handler_locked(data, handle_edge_irq);\n+\n+\treturn 0;\n+}\n+\n+static int bcm6345_ext_intc_map(struct irq_domain *d, unsigned int irq,\n+\t\t\t\tirq_hw_number_t hw)\n+{\n+\tstruct intc_data *priv = d->host_data;\n+\n+\tirq_set_chip_and_handler(irq, &priv->chip, handle_level_irq);\n+\n+\treturn 0;\n+}\n+\n+static const struct irq_domain_ops bcm6345_ext_domain_ops = {\n+\t.xlate = irq_domain_xlate_twocell,\n+\t.map = bcm6345_ext_intc_map,\n+};\n+\n+static int __init __bcm6345_ext_intc_init(struct device_node *node,\n+\t\t\t\t\t  int num_irqs, int *irqs,\n+\t\t\t\t\t  void __iomem *reg, int shift,\n+\t\t\t\t\t  bool toggle_clear_on_ack)\n+{\n+\tstruct intc_data *data;\n+\tunsigned int i;\n+\tint start = VIRQ_BASE;\n+\n+\tdata = kzalloc(sizeof(*data), GFP_KERNEL);\n+\tif (!data)\n+\t\treturn -ENOMEM;\n+\n+\traw_spin_lock_init(&data->lock);\n+\n+\tfor (i = 0; i < num_irqs; i++) {\n+\t\tdata->parent_irq[i] = irqs[i];\n+\n+\t\tirq_set_handler_data(irqs[i], data);\n+\t\tirq_set_chained_handler(irqs[i], bcm6345_ext_intc_irq_handle);\n+\t}\n+\n+\tdata->reg = reg;\n+\tdata->shift = shift;\n+\tdata->toggle_clear_on_ack = toggle_clear_on_ack;\n+\n+\tdata->chip.name = \"bcm6345-ext-intc\";\n+\tdata->chip.irq_ack = bcm6345_ext_intc_irq_ack;\n+\tdata->chip.irq_mask = bcm6345_ext_intc_irq_mask;\n+\tdata->chip.irq_unmask = bcm6345_ext_intc_irq_unmask;\n+\tdata->chip.irq_set_type = bcm6345_ext_intc_set_type;\n+\n+\t/*\n+\t * If we have less than 4 irqs, this is the second controller on\n+\t * bcm63xx. So increase the VIRQ start to not overlap with the first\n+\t * one, but only do so if we actually use a non-zero start.\n+\t *\n+\t * This can be removed when bcm63xx has no legacy users anymore.\n+\t */\n+\tif (start && num_irqs < 4)\n+\t\tstart += 4;\n+\n+\tdata->domain = irq_domain_add_simple(node, num_irqs, start,\n+\t\t\t\t\t     &bcm6345_ext_domain_ops, data);\n+\tif (!data->domain) {\n+\t\tkfree(data);\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+void __init bcm6345_ext_intc_init(int num_irqs, int *irqs, void __iomem *reg,\n+\t\t\t\t  int shift)\n+{\n+\t__bcm6345_ext_intc_init(NULL, num_irqs, irqs, reg, shift, false);\n+}\n+\n+#ifdef CONFIG_OF\n+static int __init bcm6345_ext_intc_of_init(struct device_node *node,\n+\t\t\t\t\t   struct device_node *parent)\n+{\n+\tint num_irqs, ret = -EINVAL;\n+\tunsigned i;\n+\tvoid __iomem *base;\n+\tint irqs[MAX_IRQS] = { 0 };\n+\tu32 shift;\n+\tbool toggle_clear_on_ack = false;\n+\n+\tnum_irqs = of_irq_count(node);\n+\n+\tif (!num_irqs || num_irqs > MAX_IRQS)\n+\t\treturn -EINVAL;\n+\n+\tif (of_property_read_u32(node, \"brcm,field-width\", &shift))\n+\t\tshift = 4;\n+\n+\t/* on BCM6318 setting CLEAR seems to continuously mask interrupts */\n+\tif (of_device_is_compatible(node, \"brcm,bcm6318-ext-intc\"))\n+\t\ttoggle_clear_on_ack = true;\n+\n+\tfor (i = 0; i < num_irqs; i++) {\n+\t\tirqs[i] = irq_of_parse_and_map(node, i);\n+\t\tif (!irqs[i]) {\n+\t\t\tret = -ENOMEM;\n+\t\t\tgoto out_unmap;\n+\t\t}\n+\t}\n+\n+\tbase = of_iomap(node, 0);\n+\tif (!base)\n+\t\tgoto out_unmap;\n+\n+\tret = __bcm6345_ext_intc_init(node, num_irqs, irqs, base, shift,\n+\t\t\t\t      toggle_clear_on_ack);\n+\tif (!ret)\n+\t\treturn 0;\n+out_unmap:\n+\tiounmap(base);\n+\n+\tfor (i = 0; i < num_irqs; i++)\n+\t\tirq_dispose_mapping(irqs[i]);\n+\n+\treturn ret;\n+}\n+\n+IRQCHIP_DECLARE(bcm6318_ext_intc, \"brcm,bcm6318-ext-intc\",\n+\t\tbcm6345_ext_intc_of_init);\n+IRQCHIP_DECLARE(bcm6345_ext_intc, \"brcm,bcm6345-ext-intc\",\n+\t\tbcm6345_ext_intc_of_init);\n+#endif\n--- /dev/null\n+++ b/include/linux/irqchip/irq-bcm6345-ext.h\n@@ -0,0 +1,14 @@\n+/*\n+ * This file is subject to the terms and conditions of the GNU General Public\n+ * License.  See the file \"COPYING\" in the main directory of this archive\n+ * for more details.\n+ *\n+ * Copyright (C) 2014 Jonas Gorski <jogo@openwrt.org>\n+ */\n+\n+#ifndef __INCLUDE_LINUX_IRQCHIP_IRQ_BCM6345_EXT_H\n+#define __INCLUDE_LINUX_IRQCHIP_IRQ_BCM6345_EXT_H\n+\n+void bcm6345_ext_intc_init(int n_irqs, int *irqs, void __iomem *reg, int shift);\n+\n+#endif /* __INCLUDE_LINUX_IRQCHIP_IRQ_BCM6345_EXT_H */\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/322-MIPS-BCM63XX-switch-to-IRQ_DOMAIN.patch",
    "content": "From d2d2489e0a4b740abd980e9d1cad952d15bc2d9e Mon Sep 17 00:00:00 2001\nFrom: Jonas Gorski <jogo@openwrt.org>\nDate: Sun, 30 Nov 2014 14:55:02 +0100\nSubject: [PATCH] MIPS: BCM63XX: switch to IRQ_DOMAIN\n\nNow that we have working IRQ_DOMAIN drivers for both interrupt controllers,\nswitch to using them.\n\nSigned-off-by: Jonas Gorski <jogo@openwrt.org>\n---\n arch/mips/Kconfig       |   3 +\n arch/mips/bcm63xx/irq.c | 612 +++++++++---------------------------------------\n 2 files changed, 108 insertions(+), 507 deletions(-)\n\n--- a/arch/mips/Kconfig\n+++ b/arch/mips/Kconfig\n@@ -319,6 +319,9 @@ config BCM63XX\n \tselect SYNC_R4K\n \tselect DMA_NONCOHERENT\n \tselect IRQ_MIPS_CPU\n+\tselect BCM6345_EXT_IRQ\n+\tselect BCM6345_PERIPH_IRQ\n+\tselect IRQ_DOMAIN\n \tselect SYS_SUPPORTS_32BIT_KERNEL\n \tselect SYS_SUPPORTS_BIG_ENDIAN\n \tselect SYS_HAS_EARLY_PRINTK\n--- a/arch/mips/bcm63xx/irq.c\n+++ b/arch/mips/bcm63xx/irq.c\n@@ -11,7 +11,9 @@\n #include <linux/init.h>\n #include <linux/interrupt.h>\n #include <linux/irq.h>\n-#include <linux/spinlock.h>\n+#include <linux/irqchip.h>\n+#include <linux/irqchip/irq-bcm6345-ext.h>\n+#include <linux/irqchip/irq-bcm6345-periph.h>\n #include <asm/irq_cpu.h>\n #include <asm/mipsregs.h>\n #include <bcm63xx_cpu.h>\n@@ -19,535 +21,140 @@\n #include <bcm63xx_io.h>\n #include <bcm63xx_irq.h>\n \n-\n-static DEFINE_SPINLOCK(ipic_lock);\n-static DEFINE_SPINLOCK(epic_lock);\n-\n-static u32 irq_stat_addr[2];\n-static u32 irq_mask_addr[2];\n-static void (*dispatch_internal)(int cpu);\n-static int is_ext_irq_cascaded;\n-static unsigned int ext_irq_count;\n-static unsigned int ext_irq_start, ext_irq_end;\n-static unsigned int ext_irq_cfg_reg1, ext_irq_cfg_reg2;\n-static void (*internal_irq_mask)(struct irq_data *d);\n-static void (*internal_irq_unmask)(struct irq_data *d, const struct cpumask *m);\n-\n-\n-static inline u32 get_ext_irq_perf_reg(int irq)\n-{\n-\tif (irq < 4)\n-\t\treturn ext_irq_cfg_reg1;\n-\treturn ext_irq_cfg_reg2;\n-}\n-\n-static inline void handle_internal(int intbit)\n-{\n-\tif (is_ext_irq_cascaded &&\n-\t    intbit >= ext_irq_start && intbit <= ext_irq_end)\n-\t\tdo_IRQ(intbit - ext_irq_start + IRQ_EXTERNAL_BASE);\n-\telse\n-\t\tdo_IRQ(intbit + IRQ_INTERNAL_BASE);\n-}\n-\n-static inline int enable_irq_for_cpu(int cpu, struct irq_data *d,\n-\t\t\t\t     const struct cpumask *m)\n-{\n-\tbool enable = cpu_online(cpu);\n-\n-#ifdef CONFIG_SMP\n-\tif (m)\n-\t\tenable &= cpumask_test_cpu(cpu, m);\n-\telse if (irqd_affinity_was_set(d))\n-\t\tenable &= cpumask_test_cpu(cpu, irq_data_get_affinity_mask(d));\n-#endif\n-\treturn enable;\n-}\n-\n-/*\n- * dispatch internal devices IRQ (uart, enet, watchdog, ...). do not\n- * prioritize any interrupt relatively to another. the static counter\n- * will resume the loop where it ended the last time we left this\n- * function.\n- */\n-\n-#define BUILD_IPIC_INTERNAL(width)\t\t\t\t\t\\\n-void __dispatch_internal_##width(int cpu)\t\t\t\t\\\n-{\t\t\t\t\t\t\t\t\t\\\n-\tu32 pending[width / 32];\t\t\t\t\t\\\n-\tunsigned int src, tgt;\t\t\t\t\t\t\\\n-\tbool irqs_pending = false;\t\t\t\t\t\\\n-\tstatic unsigned int i[2];\t\t\t\t\t\\\n-\tunsigned int *next = &i[cpu];\t\t\t\t\t\\\n-\tunsigned long flags;\t\t\t\t\t\t\\\n-\t\t\t\t\t\t\t\t\t\\\n-\t/* read registers in reverse order */\t\t\t\t\\\n-\tspin_lock_irqsave(&ipic_lock, flags);\t\t\t\t\\\n-\tfor (src = 0, tgt = (width / 32); src < (width / 32); src++) {\t\\\n-\t\tu32 val;\t\t\t\t\t\t\\\n-\t\t\t\t\t\t\t\t\t\\\n-\t\tval = bcm_readl(irq_stat_addr[cpu] + src * sizeof(u32)); \\\n-\t\tval &= bcm_readl(irq_mask_addr[cpu] + src * sizeof(u32)); \\\n-\t\tpending[--tgt] = val;\t\t\t\t\t\\\n-\t\t\t\t\t\t\t\t\t\\\n-\t\tif (val)\t\t\t\t\t\t\\\n-\t\t\tirqs_pending = true;\t\t\t\t\\\n-\t}\t\t\t\t\t\t\t\t\\\n-\tspin_unlock_irqrestore(&ipic_lock, flags);\t\t\t\\\n-\t\t\t\t\t\t\t\t\t\\\n-\tif (!irqs_pending)\t\t\t\t\t\t\\\n-\t\treturn;\t\t\t\t\t\t\t\\\n-\t\t\t\t\t\t\t\t\t\\\n-\twhile (1) {\t\t\t\t\t\t\t\\\n-\t\tunsigned int to_call = *next;\t\t\t\t\\\n-\t\t\t\t\t\t\t\t\t\\\n-\t\t*next = (*next + 1) & (width - 1);\t\t\t\\\n-\t\tif (pending[to_call / 32] & (1 << (to_call & 0x1f))) {\t\\\n-\t\t\thandle_internal(to_call);\t\t\t\\\n-\t\t\tbreak;\t\t\t\t\t\t\\\n-\t\t}\t\t\t\t\t\t\t\\\n-\t}\t\t\t\t\t\t\t\t\\\n-}\t\t\t\t\t\t\t\t\t\\\n-\t\t\t\t\t\t\t\t\t\\\n-static void __internal_irq_mask_##width(struct irq_data *d)\t\t\\\n-{\t\t\t\t\t\t\t\t\t\\\n-\tu32 val;\t\t\t\t\t\t\t\\\n-\tunsigned irq = d->irq - IRQ_INTERNAL_BASE;\t\t\t\\\n-\tunsigned reg = (irq / 32) ^ (width/32 - 1);\t\t\t\\\n-\tunsigned bit = irq & 0x1f;\t\t\t\t\t\\\n-\tunsigned long flags;\t\t\t\t\t\t\\\n-\tint cpu;\t\t\t\t\t\t\t\\\n-\t\t\t\t\t\t\t\t\t\\\n-\tspin_lock_irqsave(&ipic_lock, flags);\t\t\t\t\\\n-\tfor_each_present_cpu(cpu) {\t\t\t\t\t\\\n-\t\tif (!irq_mask_addr[cpu])\t\t\t\t\\\n-\t\t\tbreak;\t\t\t\t\t\t\\\n-\t\t\t\t\t\t\t\t\t\\\n-\t\tval = bcm_readl(irq_mask_addr[cpu] + reg * sizeof(u32));\\\n-\t\tval &= ~(1 << bit);\t\t\t\t\t\\\n-\t\tbcm_writel(val, irq_mask_addr[cpu] + reg * sizeof(u32));\\\n-\t}\t\t\t\t\t\t\t\t\\\n-\tspin_unlock_irqrestore(&ipic_lock, flags);\t\t\t\\\n-}\t\t\t\t\t\t\t\t\t\\\n-\t\t\t\t\t\t\t\t\t\\\n-static void __internal_irq_unmask_##width(struct irq_data *d,\t\t\\\n-\t\t\t\t\t  const struct cpumask *m)\t\\\n-{\t\t\t\t\t\t\t\t\t\\\n-\tu32 val;\t\t\t\t\t\t\t\\\n-\tunsigned irq = d->irq - IRQ_INTERNAL_BASE;\t\t\t\\\n-\tunsigned reg = (irq / 32) ^ (width/32 - 1);\t\t\t\\\n-\tunsigned bit = irq & 0x1f;\t\t\t\t\t\\\n-\tunsigned long flags;\t\t\t\t\t\t\\\n-\tint cpu;\t\t\t\t\t\t\t\\\n-\t\t\t\t\t\t\t\t\t\\\n-\tspin_lock_irqsave(&ipic_lock, flags);\t\t\t\t\\\n-\tfor_each_present_cpu(cpu) {\t\t\t\t\t\\\n-\t\tif (!irq_mask_addr[cpu])\t\t\t\t\\\n-\t\t\tbreak;\t\t\t\t\t\t\\\n-\t\t\t\t\t\t\t\t\t\\\n-\t\tval = bcm_readl(irq_mask_addr[cpu] + reg * sizeof(u32));\\\n-\t\tif (enable_irq_for_cpu(cpu, d, m))\t\t\t\\\n-\t\t\tval |= (1 << bit);\t\t\t\t\\\n-\t\telse\t\t\t\t\t\t\t\\\n-\t\t\tval &= ~(1 << bit);\t\t\t\t\\\n-\t\tbcm_writel(val, irq_mask_addr[cpu] + reg * sizeof(u32));\\\n-\t}\t\t\t\t\t\t\t\t\\\n-\tspin_unlock_irqrestore(&ipic_lock, flags);\t\t\t\\\n-}\n-\n-BUILD_IPIC_INTERNAL(32);\n-BUILD_IPIC_INTERNAL(64);\n-\n-asmlinkage void plat_irq_dispatch(void)\n-{\n-\tu32 cause;\n-\n-\tdo {\n-\t\tcause = read_c0_cause() & read_c0_status() & ST0_IM;\n-\n-\t\tif (!cause)\n-\t\t\tbreak;\n-\n-\t\tif (cause & CAUSEF_IP7)\n-\t\t\tdo_IRQ(7);\n-\t\tif (cause & CAUSEF_IP0)\n-\t\t\tdo_IRQ(0);\n-\t\tif (cause & CAUSEF_IP1)\n-\t\t\tdo_IRQ(1);\n-\t\tif (cause & CAUSEF_IP2)\n-\t\t\tdispatch_internal(0);\n-\t\tif (is_ext_irq_cascaded) {\n-\t\t\tif (cause & CAUSEF_IP3)\n-\t\t\t\tdispatch_internal(1);\n-\t\t} else {\n-\t\t\tif (cause & CAUSEF_IP3)\n-\t\t\t\tdo_IRQ(IRQ_EXT_0);\n-\t\t\tif (cause & CAUSEF_IP4)\n-\t\t\t\tdo_IRQ(IRQ_EXT_1);\n-\t\t\tif (cause & CAUSEF_IP5)\n-\t\t\t\tdo_IRQ(IRQ_EXT_2);\n-\t\t\tif (cause & CAUSEF_IP6)\n-\t\t\t\tdo_IRQ(IRQ_EXT_3);\n-\t\t}\n-\t} while (1);\n-}\n-\n-/*\n- * internal IRQs operations: only mask/unmask on PERF irq mask\n- * register.\n- */\n-static void bcm63xx_internal_irq_mask(struct irq_data *d)\n-{\n-\tinternal_irq_mask(d);\n-}\n-\n-static void bcm63xx_internal_irq_unmask(struct irq_data *d)\n-{\n-\tinternal_irq_unmask(d, NULL);\n-}\n-\n-/*\n- * external IRQs operations: mask/unmask and clear on PERF external\n- * irq control register.\n- */\n-static void bcm63xx_external_irq_mask(struct irq_data *d)\n-{\n-\tunsigned int irq = d->irq - IRQ_EXTERNAL_BASE;\n-\tu32 reg, regaddr;\n-\tunsigned long flags;\n-\n-\tregaddr = get_ext_irq_perf_reg(irq);\n-\tspin_lock_irqsave(&epic_lock, flags);\n-\treg = bcm_perf_readl(regaddr);\n-\n-\tif (BCMCPU_IS_6348())\n-\t\treg &= ~EXTIRQ_CFG_MASK_6348(irq % 4);\n-\telse\n-\t\treg &= ~EXTIRQ_CFG_MASK(irq % 4);\n-\n-\tbcm_perf_writel(reg, regaddr);\n-\tspin_unlock_irqrestore(&epic_lock, flags);\n-\n-\tif (is_ext_irq_cascaded)\n-\t\tinternal_irq_mask(irq_get_irq_data(irq + ext_irq_start));\n-}\n-\n-static void bcm63xx_external_irq_unmask(struct irq_data *d)\n-{\n-\tunsigned int irq = d->irq - IRQ_EXTERNAL_BASE;\n-\tu32 reg, regaddr;\n-\tunsigned long flags;\n-\n-\tregaddr = get_ext_irq_perf_reg(irq);\n-\tspin_lock_irqsave(&epic_lock, flags);\n-\treg = bcm_perf_readl(regaddr);\n-\n-\tif (BCMCPU_IS_6348())\n-\t\treg |= EXTIRQ_CFG_MASK_6348(irq % 4);\n-\telse\n-\t\treg |= EXTIRQ_CFG_MASK(irq % 4);\n-\n-\tbcm_perf_writel(reg, regaddr);\n-\tspin_unlock_irqrestore(&epic_lock, flags);\n-\n-\tif (is_ext_irq_cascaded)\n-\t\tinternal_irq_unmask(irq_get_irq_data(irq + ext_irq_start),\n-\t\t\t\t    NULL);\n-}\n-\n-static void bcm63xx_external_irq_clear(struct irq_data *d)\n-{\n-\tunsigned int irq = d->irq - IRQ_EXTERNAL_BASE;\n-\tu32 reg, regaddr;\n-\tunsigned long flags;\n-\n-\tregaddr = get_ext_irq_perf_reg(irq);\n-\tspin_lock_irqsave(&epic_lock, flags);\n-\treg = bcm_perf_readl(regaddr);\n-\n-\tif (BCMCPU_IS_6348())\n-\t\treg |= EXTIRQ_CFG_CLEAR_6348(irq % 4);\n-\telse\n-\t\treg |= EXTIRQ_CFG_CLEAR(irq % 4);\n-\n-\tbcm_perf_writel(reg, regaddr);\n-\tspin_unlock_irqrestore(&epic_lock, flags);\n-}\n-\n-static int bcm63xx_external_irq_set_type(struct irq_data *d,\n-\t\t\t\t\t unsigned int flow_type)\n-{\n-\tunsigned int irq = d->irq - IRQ_EXTERNAL_BASE;\n-\tu32 reg, regaddr;\n-\tint levelsense, sense, bothedge;\n-\tunsigned long flags;\n-\n-\tflow_type &= IRQ_TYPE_SENSE_MASK;\n-\n-\tif (flow_type == IRQ_TYPE_NONE)\n-\t\tflow_type = IRQ_TYPE_LEVEL_LOW;\n-\n-\tlevelsense = sense = bothedge = 0;\n-\tswitch (flow_type) {\n-\tcase IRQ_TYPE_EDGE_BOTH:\n-\t\tbothedge = 1;\n-\t\tbreak;\n-\n-\tcase IRQ_TYPE_EDGE_RISING:\n-\t\tsense = 1;\n-\t\tbreak;\n-\n-\tcase IRQ_TYPE_EDGE_FALLING:\n-\t\tbreak;\n-\n-\tcase IRQ_TYPE_LEVEL_HIGH:\n-\t\tlevelsense = 1;\n-\t\tsense = 1;\n-\t\tbreak;\n-\n-\tcase IRQ_TYPE_LEVEL_LOW:\n-\t\tlevelsense = 1;\n-\t\tbreak;\n-\n-\tdefault:\n-\t\tpr_err(\"bogus flow type combination given !\\n\");\n-\t\treturn -EINVAL;\n-\t}\n-\n-\tregaddr = get_ext_irq_perf_reg(irq);\n-\tspin_lock_irqsave(&epic_lock, flags);\n-\treg = bcm_perf_readl(regaddr);\n-\tirq %= 4;\n-\n-\tswitch (bcm63xx_get_cpu_id()) {\n-\tcase BCM6348_CPU_ID:\n-\t\tif (levelsense)\n-\t\t\treg |= EXTIRQ_CFG_LEVELSENSE_6348(irq);\n-\t\telse\n-\t\t\treg &= ~EXTIRQ_CFG_LEVELSENSE_6348(irq);\n-\t\tif (sense)\n-\t\t\treg |= EXTIRQ_CFG_SENSE_6348(irq);\n-\t\telse\n-\t\t\treg &= ~EXTIRQ_CFG_SENSE_6348(irq);\n-\t\tif (bothedge)\n-\t\t\treg |= EXTIRQ_CFG_BOTHEDGE_6348(irq);\n-\t\telse\n-\t\t\treg &= ~EXTIRQ_CFG_BOTHEDGE_6348(irq);\n-\t\tbreak;\n-\n-\tcase BCM3368_CPU_ID:\n-\tcase BCM6328_CPU_ID:\n-\tcase BCM6338_CPU_ID:\n-\tcase BCM6345_CPU_ID:\n-\tcase BCM6358_CPU_ID:\n-\tcase BCM6362_CPU_ID:\n-\tcase BCM6368_CPU_ID:\n-\t\tif (levelsense)\n-\t\t\treg |= EXTIRQ_CFG_LEVELSENSE(irq);\n-\t\telse\n-\t\t\treg &= ~EXTIRQ_CFG_LEVELSENSE(irq);\n-\t\tif (sense)\n-\t\t\treg |= EXTIRQ_CFG_SENSE(irq);\n-\t\telse\n-\t\t\treg &= ~EXTIRQ_CFG_SENSE(irq);\n-\t\tif (bothedge)\n-\t\t\treg |= EXTIRQ_CFG_BOTHEDGE(irq);\n-\t\telse\n-\t\t\treg &= ~EXTIRQ_CFG_BOTHEDGE(irq);\n-\t\tbreak;\n-\tdefault:\n-\t\tBUG();\n-\t}\n-\n-\tbcm_perf_writel(reg, regaddr);\n-\tspin_unlock_irqrestore(&epic_lock, flags);\n-\n-\tirqd_set_trigger_type(d, flow_type);\n-\tif (flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))\n-\t\tirq_set_handler_locked(d, handle_level_irq);\n-\telse\n-\t\tirq_set_handler_locked(d, handle_edge_irq);\n-\n-\treturn IRQ_SET_MASK_OK_NOCOPY;\n-}\n-\n-#ifdef CONFIG_SMP\n-static int bcm63xx_internal_set_affinity(struct irq_data *data,\n-\t\t\t\t\t const struct cpumask *dest,\n-\t\t\t\t\t bool force)\n-{\n-\tif (!irqd_irq_disabled(data))\n-\t\tinternal_irq_unmask(data, dest);\n-\n-\treturn 0;\n-}\n-#endif\n-\n-static struct irq_chip bcm63xx_internal_irq_chip = {\n-\t.name\t\t= \"bcm63xx_ipic\",\n-\t.irq_mask\t= bcm63xx_internal_irq_mask,\n-\t.irq_unmask\t= bcm63xx_internal_irq_unmask,\n-};\n-\n-static struct irq_chip bcm63xx_external_irq_chip = {\n-\t.name\t\t= \"bcm63xx_epic\",\n-\t.irq_ack\t= bcm63xx_external_irq_clear,\n-\n-\t.irq_mask\t= bcm63xx_external_irq_mask,\n-\t.irq_unmask\t= bcm63xx_external_irq_unmask,\n-\n-\t.irq_set_type\t= bcm63xx_external_irq_set_type,\n-};\n-\n-static void bcm63xx_init_irq(void)\n+void __init arch_init_irq(void)\n {\n-\tint irq_bits;\n-\n-\tirq_stat_addr[0] = bcm63xx_regset_address(RSET_PERF);\n-\tirq_mask_addr[0] = bcm63xx_regset_address(RSET_PERF);\n-\tirq_stat_addr[1] = bcm63xx_regset_address(RSET_PERF);\n-\tirq_mask_addr[1] = bcm63xx_regset_address(RSET_PERF);\n+\tvoid __iomem *periph_bases[2];\n+\tvoid __iomem *ext_intc_bases[2];\n+\tint periph_irq_count, periph_width, ext_irq_count, ext_shift;\n+\tint periph_irqs[2] = { 2, 3 };\n+\tint ext_irqs[6];\n+\n+\tperiph_bases[0] = (void __iomem *)bcm63xx_regset_address(RSET_PERF);\n+\tperiph_bases[1] = (void __iomem *)bcm63xx_regset_address(RSET_PERF);\n+\text_intc_bases[0] = (void __iomem *)bcm63xx_regset_address(RSET_PERF);\n+\text_intc_bases[1] = (void __iomem *)bcm63xx_regset_address(RSET_PERF);\n \n \tswitch (bcm63xx_get_cpu_id()) {\n \tcase BCM3368_CPU_ID:\n-\t\tirq_stat_addr[0] += PERF_IRQSTAT_3368_REG;\n-\t\tirq_mask_addr[0] += PERF_IRQMASK_3368_REG;\n-\t\tirq_stat_addr[1] = 0;\n-\t\tirq_mask_addr[1] = 0;\n-\t\tirq_bits = 32;\n-\t\text_irq_count = 4;\n-\t\text_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_3368;\n+\t\tperiph_bases[0] += PERF_IRQMASK_3368_REG;\n+\t\tperiph_irq_count = 1;\n+\t\tperiph_width = 1;\n+\n+\t\text_intc_bases[0] += PERF_EXTIRQ_CFG_REG_3368;\n+\t\text_irq_count = 4;\n+\t\text_irqs[0] = BCM_3368_EXT_IRQ0;\n+\t\text_irqs[1] = BCM_3368_EXT_IRQ1;\n+\t\text_irqs[2] = BCM_3368_EXT_IRQ2;\n+\t\text_irqs[3] = BCM_3368_EXT_IRQ3;\n+\t\text_shift = 4;\n \t\tbreak;\n \tcase BCM6328_CPU_ID:\n-\t\tirq_stat_addr[0] += PERF_IRQSTAT_6328_REG(0);\n-\t\tirq_mask_addr[0] += PERF_IRQMASK_6328_REG(0);\n-\t\tirq_stat_addr[1] += PERF_IRQSTAT_6328_REG(1);\n-\t\tirq_mask_addr[1] += PERF_IRQMASK_6328_REG(1);\n-\t\tirq_bits = 64;\n-\t\text_irq_count = 4;\n-\t\tis_ext_irq_cascaded = 1;\n-\t\text_irq_start = BCM_6328_EXT_IRQ0 - IRQ_INTERNAL_BASE;\n-\t\text_irq_end = BCM_6328_EXT_IRQ3 - IRQ_INTERNAL_BASE;\n-\t\text_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6328;\n+\t\tperiph_bases[0] += PERF_IRQMASK_6328_REG(0);\n+\t\tperiph_bases[1] += PERF_IRQMASK_6328_REG(1);\n+\t\tperiph_irq_count = 2;\n+\t\tperiph_width = 2;\n+\n+\t\text_intc_bases[0] += PERF_EXTIRQ_CFG_REG_6328;\n+\t\text_irq_count = 4;\n+\t\text_irqs[0] = BCM_6328_EXT_IRQ0;\n+\t\text_irqs[1] = BCM_6328_EXT_IRQ1;\n+\t\text_irqs[2] = BCM_6328_EXT_IRQ2;\n+\t\text_irqs[3] = BCM_6328_EXT_IRQ3;\n+\t\text_shift = 4;\n \t\tbreak;\n \tcase BCM6338_CPU_ID:\n-\t\tirq_stat_addr[0] += PERF_IRQSTAT_6338_REG;\n-\t\tirq_mask_addr[0] += PERF_IRQMASK_6338_REG;\n-\t\tirq_stat_addr[1] = 0;\n-\t\tirq_mask_addr[1] = 0;\n-\t\tirq_bits = 32;\n-\t\text_irq_count = 4;\n-\t\text_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6338;\n+\t\tperiph_bases[0] += PERF_IRQMASK_6338_REG;\n+\t\tperiph_irq_count = 1;\n+\t\tperiph_width = 1;\n+\n+\t\text_intc_bases[0] += PERF_EXTIRQ_CFG_REG_6338;\n+\t\text_irq_count = 4;\n+\t\text_irqs[0] = 3;\n+\t\text_irqs[1] = 4;\n+\t\text_irqs[2] = 5;\n+\t\text_irqs[3] = 6;\n+\t\text_shift = 4;\n \t\tbreak;\n \tcase BCM6345_CPU_ID:\n-\t\tirq_stat_addr[0] += PERF_IRQSTAT_6345_REG;\n-\t\tirq_mask_addr[0] += PERF_IRQMASK_6345_REG;\n-\t\tirq_stat_addr[1] = 0;\n-\t\tirq_mask_addr[1] = 0;\n-\t\tirq_bits = 32;\n-\t\text_irq_count = 4;\n-\t\text_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6345;\n+\t\tperiph_bases[0] += PERF_IRQMASK_6345_REG;\n+\t\tperiph_irq_count = 1;\n+\t\tperiph_width = 1;\n+\n+\t\text_intc_bases[0] += PERF_EXTIRQ_CFG_REG_6345;\n+\t\text_irq_count = 4;\n+\t\text_irqs[0] = 3;\n+\t\text_irqs[1] = 4;\n+\t\text_irqs[2] = 5;\n+\t\text_irqs[3] = 6;\n+\t\text_shift = 4;\n \t\tbreak;\n \tcase BCM6348_CPU_ID:\n-\t\tirq_stat_addr[0] += PERF_IRQSTAT_6348_REG;\n-\t\tirq_mask_addr[0] += PERF_IRQMASK_6348_REG;\n-\t\tirq_stat_addr[1] = 0;\n-\t\tirq_mask_addr[1] = 0;\n-\t\tirq_bits = 32;\n-\t\text_irq_count = 4;\n-\t\text_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6348;\n+\t\tperiph_bases[0] += PERF_IRQMASK_6348_REG;\n+\t\tperiph_irq_count = 1;\n+\t\tperiph_width = 1;\n+\n+\t\text_intc_bases[0] += PERF_EXTIRQ_CFG_REG_6348;\n+\t\text_irq_count = 4;\n+\t\text_irqs[0] = 3;\n+\t\text_irqs[1] = 4;\n+\t\text_irqs[2] = 5;\n+\t\text_irqs[3] = 6;\n+\t\text_shift = 5;\n \t\tbreak;\n \tcase BCM6358_CPU_ID:\n-\t\tirq_stat_addr[0] += PERF_IRQSTAT_6358_REG(0);\n-\t\tirq_mask_addr[0] += PERF_IRQMASK_6358_REG(0);\n-\t\tirq_stat_addr[1] += PERF_IRQSTAT_6358_REG(1);\n-\t\tirq_mask_addr[1] += PERF_IRQMASK_6358_REG(1);\n-\t\tirq_bits = 32;\n-\t\text_irq_count = 4;\n-\t\tis_ext_irq_cascaded = 1;\n-\t\text_irq_start = BCM_6358_EXT_IRQ0 - IRQ_INTERNAL_BASE;\n-\t\text_irq_end = BCM_6358_EXT_IRQ3 - IRQ_INTERNAL_BASE;\n-\t\text_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6358;\n+\t\tperiph_bases[0] += PERF_IRQMASK_6358_REG(0);\n+\t\tperiph_bases[1] += PERF_IRQMASK_6358_REG(1);\n+\t\tperiph_irq_count = 2;\n+\t\tperiph_width = 1;\n+\n+\t\text_intc_bases[0] += PERF_EXTIRQ_CFG_REG_6358;\n+\t\text_irq_count = 4;\n+\t\text_irqs[0] = BCM_6358_EXT_IRQ0;\n+\t\text_irqs[1] = BCM_6358_EXT_IRQ1;\n+\t\text_irqs[2] = BCM_6358_EXT_IRQ2;\n+\t\text_irqs[3] = BCM_6358_EXT_IRQ3;\n+\t\text_shift = 4;\n \t\tbreak;\n \tcase BCM6362_CPU_ID:\n-\t\tirq_stat_addr[0] += PERF_IRQSTAT_6362_REG(0);\n-\t\tirq_mask_addr[0] += PERF_IRQMASK_6362_REG(0);\n-\t\tirq_stat_addr[1] += PERF_IRQSTAT_6362_REG(1);\n-\t\tirq_mask_addr[1] += PERF_IRQMASK_6362_REG(1);\n-\t\tirq_bits = 64;\n-\t\text_irq_count = 4;\n-\t\tis_ext_irq_cascaded = 1;\n-\t\text_irq_start = BCM_6362_EXT_IRQ0 - IRQ_INTERNAL_BASE;\n-\t\text_irq_end = BCM_6362_EXT_IRQ3 - IRQ_INTERNAL_BASE;\n-\t\text_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6362;\n+\t\tperiph_bases[0] += PERF_IRQMASK_6362_REG(0);\n+\t\tperiph_bases[1] += PERF_IRQMASK_6362_REG(1);\n+\t\tperiph_irq_count = 2;\n+\t\tperiph_width = 2;\n+\n+\t\text_intc_bases[0] += PERF_EXTIRQ_CFG_REG_6362;\n+\t\text_irq_count = 4;\n+\t\text_irqs[0] = BCM_6362_EXT_IRQ0;\n+\t\text_irqs[1] = BCM_6362_EXT_IRQ1;\n+\t\text_irqs[2] = BCM_6362_EXT_IRQ2;\n+\t\text_irqs[3] = BCM_6362_EXT_IRQ3;\n+\t\text_shift = 4;\n \t\tbreak;\n \tcase BCM6368_CPU_ID:\n-\t\tirq_stat_addr[0] += PERF_IRQSTAT_6368_REG(0);\n-\t\tirq_mask_addr[0] += PERF_IRQMASK_6368_REG(0);\n-\t\tirq_stat_addr[1] += PERF_IRQSTAT_6368_REG(1);\n-\t\tirq_mask_addr[1] += PERF_IRQMASK_6368_REG(1);\n-\t\tirq_bits = 64;\n-\t\text_irq_count = 6;\n-\t\tis_ext_irq_cascaded = 1;\n-\t\text_irq_start = BCM_6368_EXT_IRQ0 - IRQ_INTERNAL_BASE;\n-\t\text_irq_end = BCM_6368_EXT_IRQ5 - IRQ_INTERNAL_BASE;\n-\t\text_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6368;\n-\t\text_irq_cfg_reg2 = PERF_EXTIRQ_CFG_REG2_6368;\n+\t\tperiph_bases[0] += PERF_IRQMASK_6368_REG(0);\n+\t\tperiph_bases[1] += PERF_IRQMASK_6368_REG(1);\n+\t\tperiph_irq_count = 2;\n+\t\tperiph_width = 2;\n+\n+\t\text_intc_bases[0] += PERF_EXTIRQ_CFG_REG_6368;\n+\t\text_intc_bases[1] += PERF_EXTIRQ_CFG_REG2_6368;\n+ \t\text_irq_count = 6;\n+\t\text_irqs[0] = BCM_6368_EXT_IRQ0;\n+\t\text_irqs[1] = BCM_6368_EXT_IRQ1;\n+\t\text_irqs[2] = BCM_6368_EXT_IRQ2;\n+\t\text_irqs[3] = BCM_6368_EXT_IRQ3;\n+\t\text_irqs[4] = BCM_6368_EXT_IRQ4;\n+\t\text_irqs[5] = BCM_6368_EXT_IRQ5;\n+\t\text_shift = 4;\n \t\tbreak;\n \tdefault:\n \t\tBUG();\n \t}\n \n-\tif (irq_bits == 32) {\n-\t\tdispatch_internal = __dispatch_internal_32;\n-\t\tinternal_irq_mask = __internal_irq_mask_32;\n-\t\tinternal_irq_unmask = __internal_irq_unmask_32;\n-\t} else {\n-\t\tdispatch_internal = __dispatch_internal_64;\n-\t\tinternal_irq_mask = __internal_irq_mask_64;\n-\t\tinternal_irq_unmask = __internal_irq_unmask_64;\n-\t}\n-}\n-\n-void __init arch_init_irq(void)\n-{\n-\tint i, irq;\n-\n-\tbcm63xx_init_irq();\n \tmips_cpu_irq_init();\n-\tfor (i = IRQ_INTERNAL_BASE; i < NR_IRQS; ++i)\n-\t\tirq_set_chip_and_handler(i, &bcm63xx_internal_irq_chip,\n-\t\t\t\t\t handle_level_irq);\n-\n-\tfor (i = IRQ_EXTERNAL_BASE; i < IRQ_EXTERNAL_BASE + ext_irq_count; ++i)\n-\t\tirq_set_chip_and_handler(i, &bcm63xx_external_irq_chip,\n-\t\t\t\t\t handle_edge_irq);\n-\n-\tif (!is_ext_irq_cascaded) {\n-\t\tfor (i = 3; i < 3 + ext_irq_count; ++i) {\n-\t\t\tirq = MIPS_CPU_IRQ_BASE + i;\n-\t\t\tif (request_irq(irq, no_action, IRQF_NO_THREAD,\n-\t\t\t\t\t\"cascade_extirq\", NULL)) {\n-\t\t\t\tpr_err(\"Failed to request irq %d (cascade_extirq)\\n\",\n-\t\t\t\t       irq);\n-\t\t\t}\n-\t\t}\n-\t}\n-\n-\tirq = MIPS_CPU_IRQ_BASE + 2;\n-\tif (request_irq(irq, no_action, IRQF_NO_THREAD,\t\"cascade_ip2\", NULL))\n-\t\tpr_err(\"Failed to request irq %d (cascade_ip2)\\n\", irq);\n-#ifdef CONFIG_SMP\n-\tif (is_ext_irq_cascaded) {\n-\t\tirq = MIPS_CPU_IRQ_BASE + 3;\n-\t\tif (request_irq(irq, no_action,\tIRQF_NO_THREAD, \"cascade_ip3\",\n-\t\t\t\tNULL))\n-\t\t\tpr_err(\"Failed to request irq %d (cascade_ip3)\\n\", irq);\n-\t\tbcm63xx_internal_irq_chip.irq_set_affinity =\n-\t\t\tbcm63xx_internal_set_affinity;\n-\n-\t\tcpumask_clear(irq_default_affinity);\n-\t\tcpumask_set_cpu(smp_processor_id(), irq_default_affinity);\n-\t}\n-#endif\n+\tbcm6345_periph_intc_init(periph_irq_count, periph_irqs, periph_bases,\n+\t\t\t\t periph_width);\n+\tbcm6345_ext_intc_init(4, ext_irqs, ext_intc_bases[0], ext_shift);\n+\tif (ext_irq_count > 4)\n+\t\tbcm6345_ext_intc_init(2, &ext_irqs[4], ext_intc_bases[1],\n+\t\t\t\t      ext_shift);\n }\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/323-MIPS-BCM63XX-wire-up-BCM6358-s-external-interrupts-4.patch",
    "content": "From 4fd286c3e5a5bebab0391cf1937695b3ed6721a3 Mon Sep 17 00:00:00 2001\nFrom: Jonas Gorski <jogo@openwrt.org>\nDate: Sun, 30 Nov 2014 20:20:30 +0100\nSubject: [PATCH 4/5] MIPS: BCM63XX: wire up BCM6358's external interrupts 4\n and 5\n\nDue to the external interrupts being non consecutive, the previous\nimplementation did not support them. Now that we treat both registers\nas separate irq controllers, there is no such limitation anymore and\nwe can expose them for drivers to use.\n\nSigned-off-by: Jonas Gorski <jogo@openwrt.org>\n---\n arch/mips/bcm63xx/irq.c                           |    5 ++++-\n arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h  |    2 ++\n arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h |    1 +\n 3 files changed, 7 insertions(+), 1 deletion(-)\n\n--- a/arch/mips/bcm63xx/irq.c\n+++ b/arch/mips/bcm63xx/irq.c\n@@ -108,11 +108,14 @@ void __init arch_init_irq(void)\n \t\tperiph_width = 1;\n \n \t\text_intc_bases[0] += PERF_EXTIRQ_CFG_REG_6358;\n-\t\text_irq_count = 4;\n+\t\text_intc_bases[1] += PERF_EXTIRQ_CFG_REG2_6358;\n+\t\text_irq_count = 6;\n \t\text_irqs[0] = BCM_6358_EXT_IRQ0;\n \t\text_irqs[1] = BCM_6358_EXT_IRQ1;\n \t\text_irqs[2] = BCM_6358_EXT_IRQ2;\n \t\text_irqs[3] = BCM_6358_EXT_IRQ3;\n+\t\text_irqs[4] = BCM_6358_EXT_IRQ4;\n+\t\text_irqs[5] = BCM_6358_EXT_IRQ5;\n \t\text_shift = 4;\n \t\tbreak;\n \tcase BCM6362_CPU_ID:\n--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h\n+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h\n@@ -896,6 +896,8 @@ enum bcm63xx_irq {\n #define BCM_6358_EXT_IRQ1\t\t(IRQ_INTERNAL_BASE + 26)\n #define BCM_6358_EXT_IRQ2\t\t(IRQ_INTERNAL_BASE + 27)\n #define BCM_6358_EXT_IRQ3\t\t(IRQ_INTERNAL_BASE + 28)\n+#define BCM_6358_EXT_IRQ4\t\t(IRQ_INTERNAL_BASE + 20)\n+#define BCM_6358_EXT_IRQ5\t\t(IRQ_INTERNAL_BASE + 21)\n \n /*\n  * 6362 irqs\n--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h\n+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h\n@@ -244,6 +244,7 @@\n #define PERF_EXTIRQ_CFG_REG_6362\t0x18\n #define PERF_EXTIRQ_CFG_REG_6368\t0x18\n \n+#define PERF_EXTIRQ_CFG_REG2_6358\t0x1c\n #define PERF_EXTIRQ_CFG_REG2_6368\t0x1c\n \n /* for 6348 only */\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/324-irqchip-bcm6345-periph-fix-block-uninitialized.patch",
    "content": "--- a/drivers/irqchip/irq-bcm6345-periph.c\n+++ b/drivers/irqchip/irq-bcm6345-periph.c\n@@ -52,7 +52,7 @@ static void bcm6345_periph_irq_handle(st\n {\n \tstruct intc_data *data = irq_desc_get_handler_data(desc);\n \tstruct irq_chip *chip = irq_desc_get_chip(desc);\n-\tstruct intc_block *block;\n+\tstruct intc_block *block = NULL;\n \tunsigned int irq = irq_desc_get_irq(desc);\n \tunsigned int idx;\n \n@@ -62,7 +62,7 @@ static void bcm6345_periph_irq_handle(st\n \t\tif (irq == data->block[idx].parent_irq)\n \t\t\tblock = &data->block[idx];\n \n-\tfor (idx = 0; idx < data->num_words; idx++) {\n+\tfor (idx = 0; block && idx < data->num_words; idx++) {\n \t\tint base = idx * IRQS_PER_WORD;\n \t\tunsigned long pending;\n \t\tint hw_irq;\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/325-irqchip-bcm6345-external-fix-base-uninitialized.patch",
    "content": "--- a/drivers/irqchip/irq-bcm6345-ext.c\n+++ b/drivers/irqchip/irq-bcm6345-ext.c\n@@ -271,21 +271,19 @@ static int __init bcm6345_ext_intc_of_in\n \n \tfor (i = 0; i < num_irqs; i++) {\n \t\tirqs[i] = irq_of_parse_and_map(node, i);\n-\t\tif (!irqs[i]) {\n-\t\t\tret = -ENOMEM;\n-\t\t\tgoto out_unmap;\n-\t\t}\n+\t\tif (!irqs[i])\n+\t\t\treturn -ENOMEM;\n \t}\n \n \tbase = of_iomap(node, 0);\n \tif (!base)\n-\t\tgoto out_unmap;\n+\t\treturn -ENXIO;\n \n \tret = __bcm6345_ext_intc_init(node, num_irqs, irqs, base, shift,\n \t\t\t\t      toggle_clear_on_ack);\n \tif (!ret)\n \t\treturn 0;\n-out_unmap:\n+\n \tiounmap(base);\n \n \tfor (i = 0; i < num_irqs; i++)\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/326-irqchip-bcm6345-report-eff-affinity.patch",
    "content": "--- a/drivers/irqchip/irq-bcm6345-periph.c\n+++ b/drivers/irqchip/irq-bcm6345-periph.c\n@@ -186,6 +186,8 @@ static int bcm6345_periph_set_affinity(s\n \t}\n \traw_spin_unlock_irqrestore(&priv->lock, flags);\n \n+\tirq_data_update_effective_affinity(data, cpumask_of(cpu));\n+\n \treturn 0;\n }\n #endif\n@@ -197,6 +199,8 @@ static int bcm6345_periph_map(struct irq\n \n \tirq_set_chip_and_handler(irq, &priv->chip, handle_level_irq);\n \n+\tirqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(irq)));\n+\n \treturn 0;\n }\n \n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/327-irqchip-bcm6345-periph-clear-on-init.patch",
    "content": "--- a/drivers/irqchip/irq-bcm6345-periph.c\n+++ b/drivers/irqchip/irq-bcm6345-periph.c\n@@ -240,6 +240,9 @@ static int __init __bcm6345_periph_intc_\n \t\t\t/* route all interrupts to line 0 by default */\n \t\t\tif (i == 0)\n \t\t\t\tblock->mask_cache[w] = 0xffffffff;\n+\n+\t\t\t/* mask all interrupts */\n+\t\t\t__raw_writel(0, block->en_reg[w]);\n \t\t}\n \n \t\tirq_set_handler_data(block->parent_irq, data);\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/330-MIPS-BCM63XX-add-a-new-cpu-variant-helper.patch",
    "content": "From c50acd37b425a8a907a6f7f93aa2e658256e79ce Mon Sep 17 00:00:00 2001\nFrom: Jonas Gorski <jogo@openwrt.org>\nDate: Sat, 7 Dec 2013 14:08:36 +0100\nSubject: [PATCH 40/53] MIPS: BCM63XX: add a new cpu variant helper\n\n---\n arch/mips/bcm63xx/cpu.c                          | 10 ++++++++++\n arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 18 ++++++++++++++++++\n 2 files changed, 28 insertions(+)\n\n--- a/arch/mips/bcm63xx/cpu.c\n+++ b/arch/mips/bcm63xx/cpu.c\n@@ -27,6 +27,8 @@ EXPORT_SYMBOL(bcm63xx_irqs);\n u16 bcm63xx_cpu_id __read_mostly;\n EXPORT_SYMBOL(bcm63xx_cpu_id);\n \n+static u32 bcm63xx_cpu_variant __read_mostly;\n+\n static u8 bcm63xx_cpu_rev;\n static unsigned int bcm63xx_cpu_freq;\n static unsigned int bcm63xx_memory_size;\n@@ -99,6 +101,13 @@ static const int bcm6368_irqs[] = {\n \n };\n \n+u32 bcm63xx_get_cpu_variant(void)\n+{\n+\treturn bcm63xx_cpu_variant;\n+}\n+\n+EXPORT_SYMBOL(bcm63xx_get_cpu_variant);\n+\n u8 bcm63xx_get_cpu_rev(void)\n {\n \treturn bcm63xx_cpu_rev;\n@@ -333,6 +342,7 @@ void __init bcm63xx_cpu_init(void)\n \t/* read out CPU type */\n \ttmp = bcm_readl(chipid_reg);\n \tbcm63xx_cpu_id = (tmp & REV_CHIPID_MASK) >> REV_CHIPID_SHIFT;\n+\tbcm63xx_cpu_variant = bcm63xx_cpu_id;\n \tbcm63xx_cpu_rev = (tmp & REV_REVID_MASK) >> REV_REVID_SHIFT;\n \n \tswitch (bcm63xx_cpu_id) {\n--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h\n+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h\n@@ -20,6 +20,7 @@\n #define BCM6368_CPU_ID\t\t0x6368\n \n void __init bcm63xx_cpu_init(void);\n+u32 bcm63xx_get_cpu_variant(void);\n u8 bcm63xx_get_cpu_rev(void);\n unsigned int bcm63xx_get_cpu_freq(void);\n \n@@ -83,6 +84,23 @@ static inline u16 __pure bcm63xx_get_cpu\n #define BCMCPU_IS_6362()\t(bcm63xx_get_cpu_id() == BCM6362_CPU_ID)\n #define BCMCPU_IS_6368()\t(bcm63xx_get_cpu_id() == BCM6368_CPU_ID)\n \n+#define BCMCPU_VARIANT_IS_3368() \\\n+\t(bcm63xx_get_cpu_variant() == BCM3368_CPU_ID)\n+#define BCMCPU_VARIANT_IS_6328() \\\n+\t(bcm63xx_get_cpu_variant() == BCM6328_CPU_ID)\n+#define BCMCPU_VARIANT_IS_6338() \\\n+\t(bcm63xx_get_cpu_variant() == BCM6338_CPU_ID)\n+#define BCMCPU_VARIANT_IS_6345() \\\n+\t(bcm63xx_get_cpu_variant() == BCM6345_CPU_ID)\n+#define BCMCPU_VARIANT_IS_6348() \\\n+\t(bcm63xx_get_cpu_variant() == BCM6348_CPU_ID)\n+#define BCMCPU_VARIANT_IS_6358() \\\n+\t(bcm63xx_get_cpu_cariant() == BCM6358_CPU_ID)\n+#define BCMCPU_VARIANT_IS_6362() \\\n+\t(bcm63xx_get_cpu_variant() == BCM6362_CPU_ID)\n+#define BCMCPU_VARIANT_IS_6368() \\\n+\t(bcm63xx_get_cpu_variant() == BCM6368_CPU_ID)\n+\n /*\n  * While registers sets are (mostly) the same across 63xx CPU, base\n  * address of these sets do change.\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/331-MIPS-BCM63XX-define-variant-id-field.patch",
    "content": "From 3bd8e2535265f06f79ed9c0ad788405441e091dc Mon Sep 17 00:00:00 2001\nFrom: Jonas Gorski <jogo@openwrt.org>\nDate: Sat, 7 Dec 2013 14:22:41 +0100\nSubject: [PATCH 21/45] MIPS: BCM63XX: define variant id field\n\nSome SoC have a variant id field in the chip id register.\n\nSigned-off-by: Jonas Gorski <jogo@openwrt.org>\n---\n arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 2 ++\n 1 file changed, 2 insertions(+)\n\n--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h\n+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h\n@@ -10,6 +10,8 @@\n #define PERF_REV_REG\t\t\t0x0\n #define REV_CHIPID_SHIFT\t\t16\n #define REV_CHIPID_MASK\t\t\t(0xffff << REV_CHIPID_SHIFT)\n+#define REV_VARID_SHIFT\t\t\t12\n+#define REV_VARID_MASK\t\t\t(0xf << REV_VARID_SHIFT)\n #define REV_REVID_SHIFT\t\t\t0\n #define REV_REVID_MASK\t\t\t(0xff << REV_REVID_SHIFT)\n \n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/332-MIPS-BCM63XX-detect-BCM6328-variants.patch",
    "content": "From d59120f23279ef62a48d9f94847254b061d0a8b6 Mon Sep 17 00:00:00 2001\nFrom: Jonas Gorski <jogo@openwrt.org>\nDate: Sat, 7 Dec 2013 14:30:59 +0100\nSubject: [PATCH 22/45] MIPS: BCM63XX: detect BCM6328 variants\n\nSigned-off-by: Jonas Gorski <jogo@openwrt.org>\n---\n arch/mips/bcm63xx/cpu.c                          | 10 ++++++++++\n arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h |  8 ++++++--\n 2 files changed, 16 insertions(+), 2 deletions(-)\n\n--- a/arch/mips/bcm63xx/cpu.c\n+++ b/arch/mips/bcm63xx/cpu.c\n@@ -305,6 +305,7 @@ void __init bcm63xx_cpu_init(void)\n \tunsigned int tmp;\n \tunsigned int cpu = smp_processor_id();\n \tu32 chipid_reg;\n+\tu8 __maybe_unused varid = 0;\n \n \t/* soc registers location depends on cpu type */\n \tchipid_reg = 0;\n@@ -344,6 +345,7 @@ void __init bcm63xx_cpu_init(void)\n \tbcm63xx_cpu_id = (tmp & REV_CHIPID_MASK) >> REV_CHIPID_SHIFT;\n \tbcm63xx_cpu_variant = bcm63xx_cpu_id;\n \tbcm63xx_cpu_rev = (tmp & REV_REVID_MASK) >> REV_REVID_SHIFT;\n+\tvarid = (tmp & REV_VARID_MASK) >> REV_VARID_SHIFT;\n \n \tswitch (bcm63xx_cpu_id) {\n \tcase BCM3368_CPU_ID:\n@@ -353,6 +355,14 @@ void __init bcm63xx_cpu_init(void)\n \tcase BCM6328_CPU_ID:\n \t\tbcm63xx_regs_base = bcm6328_regs_base;\n \t\tbcm63xx_irqs = bcm6328_irqs;\n+\n+\t\tif (varid == 1)\n+\t\t\tbcm63xx_cpu_variant = BCM63281_CPU_ID;\n+\t\telse if (varid == 3)\n+\t\t\tbcm63xx_cpu_variant = BCM63283_CPU_ID;\n+\t\telse\n+\t\t\tpr_warn(\"unknown BCM6328 variant: %x\\n\", varid);\n+\n \t\tbreak;\n \tcase BCM6338_CPU_ID:\n \t\tbcm63xx_regs_base = bcm6338_regs_base;\n--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h\n+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h\n@@ -12,6 +12,8 @@\n  */\n #define BCM3368_CPU_ID\t\t0x3368\n #define BCM6328_CPU_ID\t\t0x6328\n+#define BCM63281_CPU_ID\t\t0x63281\n+#define BCM63283_CPU_ID\t\t0x63283\n #define BCM6338_CPU_ID\t\t0x6338\n #define BCM6345_CPU_ID\t\t0x6345\n #define BCM6348_CPU_ID\t\t0x6348\n@@ -86,8 +88,10 @@ static inline u16 __pure bcm63xx_get_cpu\n \n #define BCMCPU_VARIANT_IS_3368() \\\n \t(bcm63xx_get_cpu_variant() == BCM3368_CPU_ID)\n-#define BCMCPU_VARIANT_IS_6328() \\\n-\t(bcm63xx_get_cpu_variant() == BCM6328_CPU_ID)\n+#define BCMCPU_VARIANT_IS_63281() \\\n+\t(bcm63xx_get_cpu_variant() == BCM63281_CPU_ID)\n+#define BCMCPU_VARIANT_IS_63283() \\\n+\t(bcm63xx_get_cpu_variant() == BCM63283_CPU_ID)\n #define BCMCPU_VARIANT_IS_6338() \\\n \t(bcm63xx_get_cpu_variant() == BCM6338_CPU_ID)\n #define BCMCPU_VARIANT_IS_6345() \\\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/333-MIPS-BCM63XX-detect-BCM6362-variants.patch",
    "content": "From 04458c3db8eb79da21ecde40ab36a1dde52bef06 Mon Sep 17 00:00:00 2001\nFrom: Jonas Gorski <jogo@openwrt.org>\nDate: Sat, 7 Dec 2013 14:33:28 +0100\nSubject: [PATCH 23/45] MIPS: BCM63XX: detect BCM6362 variants\n\n---\n arch/mips/bcm63xx/cpu.c                          | 8 ++++++++\n arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 3 +++\n 2 files changed, 11 insertions(+)\n\n--- a/arch/mips/bcm63xx/cpu.c\n+++ b/arch/mips/bcm63xx/cpu.c\n@@ -383,6 +383,14 @@ void __init bcm63xx_cpu_init(void)\n \tcase BCM6362_CPU_ID:\n \t\tbcm63xx_regs_base = bcm6362_regs_base;\n \t\tbcm63xx_irqs = bcm6362_irqs;\n+\n+\t\tif (varid == 1)\n+\t\t\tbcm63xx_cpu_variant = BCM6362_CPU_ID;\n+\t\telse if (varid == 2)\n+\t\t\tbcm63xx_cpu_variant = BCM6361_CPU_ID;\n+\t\telse\n+\t\t\tpr_warn(\"unknown BCM6362 variant: %x\\n\", varid);\n+\n \t\tbreak;\n \tcase BCM6368_CPU_ID:\n \t\tbcm63xx_regs_base = bcm6368_regs_base;\n--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h\n+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h\n@@ -18,6 +18,7 @@\n #define BCM6345_CPU_ID\t\t0x6345\n #define BCM6348_CPU_ID\t\t0x6348\n #define BCM6358_CPU_ID\t\t0x6358\n+#define BCM6361_CPU_ID\t\t0x6361\n #define BCM6362_CPU_ID\t\t0x6362\n #define BCM6368_CPU_ID\t\t0x6368\n \n@@ -100,6 +101,8 @@ static inline u16 __pure bcm63xx_get_cpu\n \t(bcm63xx_get_cpu_variant() == BCM6348_CPU_ID)\n #define BCMCPU_VARIANT_IS_6358() \\\n \t(bcm63xx_get_cpu_cariant() == BCM6358_CPU_ID)\n+#define BCMCPU_VARIANT_IS_6361() \\\n+\t(bcm63xx_get_cpu_variant() == BCM6361_CPU_ID)\n #define BCMCPU_VARIANT_IS_6362() \\\n \t(bcm63xx_get_cpu_variant() == BCM6362_CPU_ID)\n #define BCMCPU_VARIANT_IS_6368() \\\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/334-MIPS-BCM63XX-detect-BCM6368-variants.patch",
    "content": "From 825cc67e56b5e624a05f6850a86d91508b786848 Mon Sep 17 00:00:00 2001\nFrom: Jonas Gorski <jogo@openwrt.org>\nDate: Sat, 7 Dec 2013 14:36:56 +0100\nSubject: [PATCH 24/44] MIPS: BCM63XX: detect BCM6368 variants\n\nThe DSL-less BCM6368 variant BCM6367 uses a different chip id. Apart\nfrom missing DSL, there is no difference to BCM6368, so treat it such.\n\nSigned-off-by: Jonas Gorski <jogo@openwrt.org>\n---\n arch/mips/bcm63xx/cpu.c                          | 4 ++++\n arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 3 +++\n 2 files changed, 7 insertions(+)\n\n--- a/arch/mips/bcm63xx/cpu.c\n+++ b/arch/mips/bcm63xx/cpu.c\n@@ -393,8 +393,12 @@ void __init bcm63xx_cpu_init(void)\n \n \t\tbreak;\n \tcase BCM6368_CPU_ID:\n+\tcase BCM6369_CPU_ID:\n \t\tbcm63xx_regs_base = bcm6368_regs_base;\n \t\tbcm63xx_irqs = bcm6368_irqs;\n+\n+\t\t/* BCM6369 is a BCM6368 without xDSL, so treat it the same */\n+\t\tbcm63xx_cpu_id = BCM6368_CPU_ID;\n \t\tbreak;\n \tdefault:\n \t\tpanic(\"unsupported broadcom CPU %x\", bcm63xx_cpu_id);\n--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h\n+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h\n@@ -21,6 +21,7 @@\n #define BCM6361_CPU_ID\t\t0x6361\n #define BCM6362_CPU_ID\t\t0x6362\n #define BCM6368_CPU_ID\t\t0x6368\n+#define BCM6369_CPU_ID\t\t0x6369\n \n void __init bcm63xx_cpu_init(void);\n u32 bcm63xx_get_cpu_variant(void);\n@@ -107,6 +108,8 @@ static inline u16 __pure bcm63xx_get_cpu\n \t(bcm63xx_get_cpu_variant() == BCM6362_CPU_ID)\n #define BCMCPU_VARIANT_IS_6368() \\\n \t(bcm63xx_get_cpu_variant() == BCM6368_CPU_ID)\n+#define BCMCPU_VARIANT_IS_6369() \\\n+\t(bcm63xx_get_cpu_variant() == BCM6369_CPU_ID)\n \n /*\n  * While registers sets are (mostly) the same across 63xx CPU, base\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/335-MIPS-BCM63XX-fix-PCIe-memory-window-size.patch",
    "content": "From f67f8134b4537c8bbafe7e1975edfe808b813997 Mon Sep 17 00:00:00 2001\nFrom: Jonas Gorski <jogo@openwrt.org>\nDate: Sun, 8 Dec 2013 03:05:54 +0100\nSubject: [PATCH 45/53] MIPS: BCM63XX: fix PCIe memory window size\n\n---\n arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h\n+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h\n@@ -42,7 +42,7 @@\n \t\t\t\t\tBCM_CB_MEM_SIZE - 1)\n \n #define BCM_PCIE_MEM_BASE_PA\t\t0x10f00000\n-#define BCM_PCIE_MEM_SIZE\t\t(16 * 1024 * 1024)\n+#define BCM_PCIE_MEM_SIZE\t\t(1 * 1024 * 1024)\n #define BCM_PCIE_MEM_END_PA\t\t(BCM_PCIE_MEM_BASE_PA +\t\t\\\n \t\t\t\t\tBCM_PCIE_MEM_SIZE - 1)\n \n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/336-MIPS-BCM63XX-dynamically-set-the-pcie-memory-windows.patch",
    "content": "From aa05464973bc176478af462ca7c53a9239c651d4 Mon Sep 17 00:00:00 2001\nFrom: Jonas Gorski <jogo@openwrt.org>\nDate: Sun, 8 Dec 2013 03:13:06 +0100\nSubject: [PATCH 46/53] MIPS: BCM63XX: dynamically set the pcie memory windows\n\nDifferent SoCs use different memory windows (and sizes), so don't\nhardcode it.\n---\n arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h |  8 ++++----\n arch/mips/pci/pci-bcm63xx.c                     | 15 ++++++++++-----\n 2 files changed, 14 insertions(+), 9 deletions(-)\n\n--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h\n+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h\n@@ -41,10 +41,10 @@\n #define BCM_CB_MEM_END_PA\t\t(BCM_CB_MEM_BASE_PA +\t\t\\\n \t\t\t\t\tBCM_CB_MEM_SIZE - 1)\n \n-#define BCM_PCIE_MEM_BASE_PA\t\t0x10f00000\n-#define BCM_PCIE_MEM_SIZE\t\t(1 * 1024 * 1024)\n-#define BCM_PCIE_MEM_END_PA\t\t(BCM_PCIE_MEM_BASE_PA +\t\t\\\n-\t\t\t\t\tBCM_PCIE_MEM_SIZE - 1)\n+#define BCM_PCIE_MEM_BASE_PA_6328\t0x10f00000\n+#define BCM_PCIE_MEM_SIZE_6328\t\t(1 * 1024 * 1024)\n+#define BCM_PCIE_MEM_END_PA_6328\t(BCM_PCIE_MEM_BASE_PA_6328 +\t\\\n+\t\t\t\t\tBCM_PCIE_MEM_SIZE_6328 - 1)\n \n /*\n  * Internal registers are accessed through KSEG3\n--- a/arch/mips/pci/pci-bcm63xx.c\n+++ b/arch/mips/pci/pci-bcm63xx.c\n@@ -77,8 +77,8 @@ struct pci_controller bcm63xx_cb_control\n \n static struct resource bcm_pcie_mem_resource = {\n \t.name\t= \"bcm63xx PCIe memory space\",\n-\t.start\t= BCM_PCIE_MEM_BASE_PA,\n-\t.end\t= BCM_PCIE_MEM_END_PA,\n+\t.start\t= 0,\n+\t.end\t= 0,\n \t.flags\t= IORESOURCE_MEM,\n };\n \n@@ -195,12 +195,12 @@ static int __init bcm63xx_register_pcie(\n \tbcm_pcie_writel(val, PCIE_CONFIG2_REG);\n \n \t/* set bar0 to little endian */\n-\tval = (BCM_PCIE_MEM_BASE_PA >> 20) << BASEMASK_BASE_SHIFT;\n-\tval |= (BCM_PCIE_MEM_BASE_PA >> 20) << BASEMASK_MASK_SHIFT;\n+\tval = (bcm_pcie_mem_resource.start >> 20) << BASEMASK_BASE_SHIFT;\n+\tval |= (bcm_pcie_mem_resource.end >> 20) << BASEMASK_MASK_SHIFT;\n \tval |= BASEMASK_REMAP_EN;\n \tbcm_pcie_writel(val, PCIE_BRIDGE_BAR0_BASEMASK_REG);\n \n-\tval = (BCM_PCIE_MEM_BASE_PA >> 20) << REBASE_ADDR_BASE_SHIFT;\n+\tval = (bcm_pcie_mem_resource.start >> 20) << REBASE_ADDR_BASE_SHIFT;\n \tbcm_pcie_writel(val, PCIE_BRIDGE_BAR0_REBASE_ADDR_REG);\n \n \tregister_pci_controller(&bcm63xx_pcie_controller);\n@@ -334,6 +334,11 @@ static int __init bcm63xx_pci_init(void)\n \tif (!bcm63xx_pci_enabled)\n \t\treturn -ENODEV;\n \n+\tif (BCMCPU_IS_6328() || BCMCPU_IS_6362()) {\n+\t\tbcm_pcie_mem_resource.start = BCM_PCIE_MEM_BASE_PA_6328;\n+\t\tbcm_pcie_mem_resource.end = BCM_PCIE_MEM_END_PA_6328;\n+\t}\n+\n \tswitch (bcm63xx_get_cpu_id()) {\n \tcase BCM6328_CPU_ID:\n \tcase BCM6362_CPU_ID:\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/337-MIPS-BCM63XX-widen-cpuid-field.patch",
    "content": "From f1477f6e3551fd6beecfee5368fed1325dcd421f Mon Sep 17 00:00:00 2001\nFrom: Jonas Gorski <jogo@openwrt.org>\nDate: Sat, 7 Dec 2013 14:54:51 +0100\nSubject: [PATCH 47/53] MIPS: BCM63XX: widen cpuid field\n\n---\n arch/mips/bcm63xx/cpu.c                          | 2 +-\n arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 8 ++++----\n 2 files changed, 5 insertions(+), 5 deletions(-)\n\n--- a/arch/mips/bcm63xx/cpu.c\n+++ b/arch/mips/bcm63xx/cpu.c\n@@ -24,7 +24,7 @@ EXPORT_SYMBOL(bcm63xx_regs_base);\n const int *bcm63xx_irqs;\n EXPORT_SYMBOL(bcm63xx_irqs);\n \n-u16 bcm63xx_cpu_id __read_mostly;\n+u32 bcm63xx_cpu_id __read_mostly;\n EXPORT_SYMBOL(bcm63xx_cpu_id);\n \n static u32 bcm63xx_cpu_variant __read_mostly;\n@@ -127,7 +127,7 @@ unsigned int bcm63xx_get_memory_size(voi\n \n static unsigned int detect_cpu_clock(void)\n {\n-\tu16 cpu_id = bcm63xx_get_cpu_id();\n+\tu32 cpu_id = bcm63xx_get_cpu_id();\n \n \tswitch (cpu_id) {\n \tcase BCM3368_CPU_ID:\n--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h\n+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h\n@@ -28,7 +28,7 @@ u32 bcm63xx_get_cpu_variant(void);\n u8 bcm63xx_get_cpu_rev(void);\n unsigned int bcm63xx_get_cpu_freq(void);\n \n-static inline u16 __pure __bcm63xx_get_cpu_id(const u16 cpu_id)\n+static inline u32 __pure __bcm63xx_get_cpu_id(const u32 cpu_id)\n {\n \tswitch (cpu_id) {\n #ifdef CONFIG_BCM63XX_CPU_3368\n@@ -70,11 +70,11 @@ static inline u16 __pure __bcm63xx_get_c\n \treturn cpu_id;\n }\n \n-extern u16 bcm63xx_cpu_id;\n+extern u32 bcm63xx_cpu_id;\n \n-static inline u16 __pure bcm63xx_get_cpu_id(void)\n+static inline u32 __pure bcm63xx_get_cpu_id(void)\n {\n-\tconst u16 cpu_id = bcm63xx_cpu_id;\n+\tconst u32 cpu_id = bcm63xx_cpu_id;\n \n \treturn __bcm63xx_get_cpu_id(cpu_id);\n }\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/338-MIPS-BCM63XX-increase-number-of-IRQs.patch",
    "content": "From 6f5658c845cf1f79213b1d20423a04967259fdaa Mon Sep 17 00:00:00 2001\nFrom: Jonas Gorski <jogo@openwrt.org>\nDate: Sun, 15 Dec 2013 20:46:26 +0100\nSubject: [PATCH 48/53] MIPS: BCM63XX: increase number of IRQs\n\nNewer SoCs have 128 bit wide irq registers, thus 128 available internal\ninterupts.\n---\n arch/mips/include/asm/mach-bcm63xx/bcm63xx_irq.h | 4 +++-\n arch/mips/include/asm/mach-bcm63xx/irq.h         | 2 +-\n 2 files changed, 4 insertions(+), 2 deletions(-)\n\n--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_irq.h\n+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_irq.h\n@@ -2,10 +2,12 @@\n #ifndef BCM63XX_IRQ_H_\n #define BCM63XX_IRQ_H_\n \n+#include <irq.h>\n #include <bcm63xx_cpu.h>\n \n #define IRQ_INTERNAL_BASE\t\t8\n-#define IRQ_EXTERNAL_BASE\t\t100\n+#define NR_INTERNAL_IRQS\t\t128\n+#define IRQ_EXTERNAL_BASE\t\t(IRQ_INTERNAL_BASE + NR_INTERNAL_IRQS)\n #define IRQ_EXT_0\t\t\t(IRQ_EXTERNAL_BASE + 0)\n #define IRQ_EXT_1\t\t\t(IRQ_EXTERNAL_BASE + 1)\n #define IRQ_EXT_2\t\t\t(IRQ_EXTERNAL_BASE + 2)\n--- a/arch/mips/include/asm/mach-bcm63xx/irq.h\n+++ b/arch/mips/include/asm/mach-bcm63xx/irq.h\n@@ -2,7 +2,7 @@\n #ifndef __ASM_MACH_BCM63XX_IRQ_H\n #define __ASM_MACH_BCM63XX_IRQ_H\n \n-#define NR_IRQS 128\n+#define NR_IRQS 256\n #define MIPS_CPU_IRQ_BASE 0\n \n #endif\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/339-MIPS-BCM63XX-add-support-for-BCM63268.patch",
    "content": "From 98f63141190ac02c58b78d58f771bd263c61d756 Mon Sep 17 00:00:00 2001\nFrom: Jonas Gorski <jogo@openwrt.org>\nDate: Sat, 7 Dec 2013 17:14:17 +0100\nSubject: [PATCH 48/56] MIPS: BCM63XX: add support for BCM63268\n\nSigned-off-by: Jonas Gorski <jogo@openwrt.org>\n---\n arch/mips/bcm63xx/Kconfig                         |   5 +\n arch/mips/bcm63xx/boards/board_bcm963xx.c         |   2 +-\n arch/mips/bcm63xx/clk.c                           |  25 ++++-\n arch/mips/bcm63xx/cpu.c                           |  59 +++++++++-\n arch/mips/bcm63xx/dev-flash.c                     |   6 +\n arch/mips/bcm63xx/dev-spi.c                       |   4 +-\n arch/mips/bcm63xx/irq.c                           |  20 +++-\n arch/mips/bcm63xx/reset.c                         |  21 ++++\n arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h  | 130 ++++++++++++++++++++++\n arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h |   2 +\n arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h |  79 +++++++++++++\n arch/mips/include/asm/mach-bcm63xx/ioremap.h      |   1 +\n 12 files changed, 342 insertions(+), 12 deletions(-)\n\n--- a/arch/mips/bcm63xx/Kconfig\n+++ b/arch/mips/bcm63xx/Kconfig\n@@ -61,6 +61,11 @@ config BCM63XX_CPU_6368\n \tselect HAVE_PCI\n \tselect BCM63XX_OHCI\n \tselect BCM63XX_EHCI\n+\n+config BCM63XX_CPU_63268\n+\tbool \"support 63268 CPU\"\n+\tselect SYS_HAS_CPU_BMIPS4350\n+\tselect HAVE_PCI\n endmenu\n \n source \"arch/mips/bcm63xx/boards/Kconfig\"\n--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c\n+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c\n@@ -681,7 +681,7 @@ void __init board_prom_init(void)\n \t/* read base address of boot chip select (0)\n \t * 6328/6362 do not have MPI but boot from a fixed address\n \t */\n-\tif (BCMCPU_IS_6328() || BCMCPU_IS_6362()) {\n+\tif (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_63268()) {\n \t\tval = 0x18000000;\n \t} else {\n \t\tval = bcm_mpi_readl(MPI_CSBASE_REG(0));\n--- a/arch/mips/bcm63xx/clk.c\n+++ b/arch/mips/bcm63xx/clk.c\n@@ -169,6 +169,8 @@ static void enetsw_set(struct clk *clk,\n \t\t\tclk_disable_unlocked(&clk_swpkt_sar);\n \t\t}\n \t\tbcm_hwclock_set(CKCTL_6368_ROBOSW_EN, enable);\n+\t} else if (BCMCPU_IS_63268()) {\n+\t\tbcm_hwclock_set(CKCTL_63268_ROBOSW_EN, enable);\n \t} else {\n \t\treturn;\n \t}\n@@ -214,6 +216,8 @@ static void usbh_set(struct clk *clk, in\n \t\tbcm_hwclock_set(CKCTL_6362_USBH_EN, enable);\n \telse if (BCMCPU_IS_6368())\n \t\tbcm_hwclock_set(CKCTL_6368_USBH_EN, enable);\n+\telse if (BCMCPU_IS_63268())\n+\t\tbcm_hwclock_set(CKCTL_63268_USBH_EN, enable);\n \telse\n \t\treturn;\n \n@@ -236,6 +240,8 @@ static void usbd_set(struct clk *clk, in\n \t\tbcm_hwclock_set(CKCTL_6362_USBD_EN, enable);\n \telse if (BCMCPU_IS_6368())\n \t\tbcm_hwclock_set(CKCTL_6368_USBD_EN, enable);\n+\telse if (BCMCPU_IS_63268())\n+\t\tbcm_hwclock_set(CKCTL_63268_USBD_EN, enable);\n \telse\n \t\treturn;\n \n@@ -262,9 +268,13 @@ static void spi_set(struct clk *clk, int\n \t\tmask = CKCTL_6358_SPI_EN;\n \telse if (BCMCPU_IS_6362())\n \t\tmask = CKCTL_6362_SPI_EN;\n-\telse\n-\t\t/* BCMCPU_IS_6368 */\n+\telse if (BCMCPU_IS_6368())\n \t\tmask = CKCTL_6368_SPI_EN;\n+\telse if (BCMCPU_IS_63268())\n+\t\tmask = CKCTL_63268_SPI_EN;\n+\telse\n+\t\treturn;\n+\n \tbcm_hwclock_set(mask, enable);\n }\n \n@@ -283,6 +293,8 @@ static void hsspi_set(struct clk *clk, i\n \t\tmask = CKCTL_6328_HSSPI_EN;\n \telse if (BCMCPU_IS_6362())\n \t\tmask = CKCTL_6362_HSSPI_EN;\n+\telse if (BCMCPU_IS_63268())\n+\t\tmask = CKCTL_63268_HSSPI_EN;\n \telse\n \t\treturn;\n \n@@ -352,6 +364,8 @@ static void pcie_set(struct clk *clk, in\n \t\tbcm_hwclock_set(CKCTL_6328_PCIE_EN, enable);\n \telse if (BCMCPU_IS_6362())\n \t\tbcm_hwclock_set(CKCTL_6362_PCIE_EN, enable);\n+\telse if (BCMCPU_IS_63268())\n+\t\tbcm_hwclock_set(CKCTL_63268_PCIE_EN, enable);\n }\n \n static struct clk clk_pcie = {\n@@ -548,6 +562,21 @@ static struct clk_lookup bcm6368_clks[]\n \tCLKDEV_INIT(NULL, \"ipsec\", &clk_ipsec),\n };\n \n+static struct clk_lookup bcm63268_clks[] = {\n+\t/* fixed rate clocks */\n+\tCLKDEV_INIT(NULL, \"periph\", &clk_periph),\n+\tCLKDEV_INIT(\"bcm63xx_uart.0\", \"refclk\", &clk_periph),\n+\tCLKDEV_INIT(\"bcm63xx_uart.1\", \"refclk\", &clk_periph),\n+\tCLKDEV_INIT(\"bcm63xx-hsspi.0\", \"pll\", &clk_hsspi_pll),\n+\t/* gated clocks */\n+\tCLKDEV_INIT(NULL, \"enetsw\", &clk_enetsw),\n+\tCLKDEV_INIT(NULL, \"usbh\", &clk_usbh),\n+\tCLKDEV_INIT(NULL, \"usbd\", &clk_usbd),\n+\tCLKDEV_INIT(NULL, \"spi\", &clk_spi),\n+\tCLKDEV_INIT(NULL, \"hsspi\", &clk_hsspi),\n+\tCLKDEV_INIT(NULL, \"pcie\", &clk_pcie),\n+};\n+\n #define HSSPI_PLL_HZ_6328\t133333333\n #define HSSPI_PLL_HZ_6362\t400000000\n \n@@ -580,6 +609,10 @@ static int __init bcm63xx_clk_init(void)\n \tcase BCM6368_CPU_ID:\n \t\tclkdev_add_table(bcm6368_clks, ARRAY_SIZE(bcm6368_clks));\n \t\tbreak;\n+\tcase BCM63268_CPU_ID:\n+\t\tclk_hsspi_pll.rate = HSSPI_PLL_HZ_6362;\n+\t\tclkdev_add_table(bcm63268_clks, ARRAY_SIZE(bcm63268_clks));\n+\t\tbreak;\n \t}\n \n \treturn 0;\n--- a/arch/mips/bcm63xx/cpu.c\n+++ b/arch/mips/bcm63xx/cpu.c\n@@ -101,6 +101,15 @@ static const int bcm6368_irqs[] = {\n \n };\n \n+static const unsigned long bcm63268_regs_base[] = {\n+\t__GEN_CPU_REGS_TABLE(63268)\n+};\n+\n+static const int bcm63268_irqs[] = {\n+\t__GEN_CPU_IRQ_TABLE(63268)\n+\n+};\n+\n u32 bcm63xx_get_cpu_variant(void)\n {\n \treturn bcm63xx_cpu_variant;\n@@ -253,6 +262,27 @@ static unsigned int detect_cpu_clock(voi\n \n \t\treturn (((64 * 1000000) / p1) * p2 * ndiv) / m1;\n \t}\n+\tcase BCM63268_CPU_ID:\n+\t{\n+\t\tunsigned int tmp, mips_pll_fcvo;\n+\n+\t\ttmp = bcm_misc_readl(MISC_STRAPBUS_63268_REG);\n+\t\tmips_pll_fcvo = (tmp & STRAPBUS_63268_FCVO_MASK) >>\n+\t\t\t\tSTRAPBUS_63268_FCVO_SHIFT;\n+\t\tswitch (mips_pll_fcvo) {\n+\t\tcase 0x3:\n+\t\tcase 0xe:\n+\t\t\treturn 320000000;\n+\t\tcase 0xa:\n+\t\t\treturn 333000000;\n+\t\tcase 0x2:\n+\t\tcase 0xb:\n+\t\tcase 0xf:\n+\t\t\treturn 400000000;\n+\t\tdefault:\n+\t\t\treturn 0;\n+\t\t}\n+\t}\n \n \tdefault:\n \t\tpanic(\"Failed to detect clock for CPU with id=%04X\\n\", cpu_id);\n@@ -267,7 +297,7 @@ static unsigned int detect_memory_size(v\n \tunsigned int cols = 0, rows = 0, is_32bits = 0, banks = 0;\n \tu32 val;\n \n-\tif (BCMCPU_IS_6328() || BCMCPU_IS_6362())\n+\tif (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_63268())\n \t\treturn bcm_ddr_readl(DDR_CSEND_REG) << 24;\n \n \tif (BCMCPU_IS_6345()) {\n@@ -305,6 +335,7 @@ void __init bcm63xx_cpu_init(void)\n \tunsigned int tmp;\n \tunsigned int cpu = smp_processor_id();\n \tu32 chipid_reg;\n+\tbool long_chipid = false;\n \tu8 __maybe_unused varid = 0;\n \n \t/* soc registers location depends on cpu type */\n@@ -326,6 +357,9 @@ void __init bcm63xx_cpu_init(void)\n \t\tcase 0x10:\n \t\t\tchipid_reg = BCM_6345_PERF_BASE;\n \t\t\tbreak;\n+\t\tcase 0x80:\n+\t\t\tlong_chipid = true;\n+\t\t\t/* fall-through */\n \t\tdefault:\n \t\t\tchipid_reg = BCM_6368_PERF_BASE;\n \t\t\tbreak;\n@@ -333,6 +367,7 @@ void __init bcm63xx_cpu_init(void)\n \t\tbreak;\n \t}\n \n+\n \t/*\n \t * really early to panic, but delaying panic would not help since we\n \t * will never get any working console\n@@ -342,10 +377,17 @@ void __init bcm63xx_cpu_init(void)\n \n \t/* read out CPU type */\n \ttmp = bcm_readl(chipid_reg);\n-\tbcm63xx_cpu_id = (tmp & REV_CHIPID_MASK) >> REV_CHIPID_SHIFT;\n-\tbcm63xx_cpu_variant = bcm63xx_cpu_id;\n+\n+\tif (long_chipid) {\n+\t\tbcm63xx_cpu_id = tmp & REV_LONG_CHIPID_MASK;\n+\t\tbcm63xx_cpu_id >>= REV_LONG_CHIPID_SHIFT;\n+\t} else {\n+\t\tbcm63xx_cpu_id = (tmp & REV_CHIPID_MASK) >> REV_CHIPID_SHIFT;\n+\t\tvarid = (tmp & REV_VARID_MASK) >> REV_VARID_SHIFT;\n+\t}\n+\n \tbcm63xx_cpu_rev = (tmp & REV_REVID_MASK) >> REV_REVID_SHIFT;\n-\tvarid = (tmp & REV_VARID_MASK) >> REV_VARID_SHIFT;\n+\tbcm63xx_cpu_variant = bcm63xx_cpu_id;\n \n \tswitch (bcm63xx_cpu_id) {\n \tcase BCM3368_CPU_ID:\n@@ -400,6 +442,16 @@ void __init bcm63xx_cpu_init(void)\n \t\t/* BCM6369 is a BCM6368 without xDSL, so treat it the same */\n \t\tbcm63xx_cpu_id = BCM6368_CPU_ID;\n \t\tbreak;\n+\tcase BCM63167_CPU_ID:\n+\tcase BCM63168_CPU_ID:\n+\tcase BCM63169_CPU_ID:\n+\tcase BCM63268_CPU_ID:\n+\tcase BCM63269_CPU_ID:\n+\t\tbcm63xx_regs_base = bcm63268_regs_base;\n+\t\tbcm63xx_irqs = bcm63268_irqs;\n+\n+\t\tbcm63xx_cpu_id = BCM63268_CPU_ID;\n+\t\tbreak;\n \tdefault:\n \t\tpanic(\"unsupported broadcom CPU %x\", bcm63xx_cpu_id);\n \t\tbreak;\n--- a/arch/mips/bcm63xx/dev-flash.c\n+++ b/arch/mips/bcm63xx/dev-flash.c\n@@ -84,6 +84,12 @@ static int __init bcm63xx_detect_flash_t\n \t\t\treturn BCM63XX_FLASH_TYPE_SERIAL;\n \t\telse\n \t\t\treturn BCM63XX_FLASH_TYPE_NAND;\n+\tcase BCM63268_CPU_ID:\n+\t\tval = bcm_misc_readl(MISC_STRAPBUS_63268_REG);\n+\t\tif (val & STRAPBUS_63268_BOOT_SEL_SERIAL)\n+\t\t\treturn BCM63XX_FLASH_TYPE_SERIAL;\n+\t\telse\n+\t\t\treturn BCM63XX_FLASH_TYPE_NAND;\n \tcase BCM6368_CPU_ID:\n \t\tval = bcm_gpio_readl(GPIO_STRAPBUS_REG);\n \t\tswitch (val & STRAPBUS_6368_BOOT_SEL_MASK) {\n--- a/arch/mips/bcm63xx/dev-spi.c\n+++ b/arch/mips/bcm63xx/dev-spi.c\n@@ -51,7 +51,7 @@ int __init bcm63xx_spi_register(void)\n \t}\n \n \tif (BCMCPU_IS_3368() || BCMCPU_IS_6358() || BCMCPU_IS_6362() ||\n-\t\tBCMCPU_IS_6368()) {\n+\t\tBCMCPU_IS_6368() || BCMCPU_IS_63268()) {\n \t\tbcm63xx_spi_device.name = \"bcm6358-spi\",\n \t\tspi_resources[0].end += BCM_6358_RSET_SPI_SIZE - 1;\n \t}\n--- a/arch/mips/bcm63xx/irq.c\n+++ b/arch/mips/bcm63xx/irq.c\n@@ -149,6 +149,20 @@ void __init arch_init_irq(void)\n \t\text_irqs[5] = BCM_6368_EXT_IRQ5;\n \t\text_shift = 4;\n \t\tbreak;\n+\tcase BCM63268_CPU_ID:\n+\t\tperiph_bases[0] += PERF_IRQMASK_63268_REG(0);\n+\t\tperiph_bases[1] += PERF_IRQMASK_63268_REG(1);\n+\t\tperiph_irq_count = 2;\n+\t\tperiph_width = 4;\n+\n+\t\text_intc_bases[0] += PERF_EXTIRQ_CFG_REG_63268;\n+\t\text_irq_count = 4;\n+\t\text_irqs[0] = BCM_63268_EXT_IRQ0;\n+\t\text_irqs[1] = BCM_63268_EXT_IRQ1;\n+\t\text_irqs[2] = BCM_63268_EXT_IRQ2;\n+\t\text_irqs[3] = BCM_63268_EXT_IRQ3;\n+\t\text_shift = 4;\n+\t\tbreak;\n \tdefault:\n \t\tBUG();\n \t}\n--- a/arch/mips/bcm63xx/reset.c\n+++ b/arch/mips/bcm63xx/reset.c\n@@ -126,6 +126,20 @@\n #define BCM6368_RESET_PCIE\t0\n #define BCM6368_RESET_PCIE_EXT\t0\n \n+#define BCM63268_RESET_SPI\tSOFTRESET_63268_SPI_MASK\n+#define BCM63268_RESET_ENET\t0\n+#define BCM63268_RESET_USBH\tSOFTRESET_63268_USBH_MASK\n+#define BCM63268_RESET_USBD\tSOFTRESET_63268_USBS_MASK\n+#define BCM63268_RESET_DSL\t0\n+#define BCM63268_RESET_SAR\tSOFTRESET_63268_SAR_MASK\n+#define BCM63268_RESET_EPHY\t0\n+#define BCM63268_RESET_ENETSW\tSOFTRESET_63268_ENETSW_MASK\n+#define BCM63268_RESET_PCM\tSOFTRESET_63268_PCM_MASK\n+#define BCM63268_RESET_MPI\t0\n+#define BCM63268_RESET_PCIE\t(SOFTRESET_63268_PCIE_MASK | \\\n+\t\t\t\t SOFTRESET_63268_PCIE_CORE_MASK)\n+#define BCM63268_RESET_PCIE_EXT\tSOFTRESET_63268_PCIE_EXT_MASK\n+\n /*\n  * core reset bits\n  */\n@@ -157,6 +171,10 @@ static const u32 bcm6368_reset_bits[] =\n \t__GEN_RESET_BITS_TABLE(6368)\n };\n \n+static const u32 bcm63268_reset_bits[] = {\n+\t__GEN_RESET_BITS_TABLE(63268)\n+};\n+\n const u32 *bcm63xx_reset_bits;\n static int reset_reg;\n \n@@ -183,6 +201,9 @@ static int __init bcm63xx_reset_bits_ini\n \t} else if (BCMCPU_IS_6368()) {\n \t\treset_reg = PERF_SOFTRESET_6368_REG;\n \t\tbcm63xx_reset_bits = bcm6368_reset_bits;\n+\t} else if (BCMCPU_IS_63268()) {\n+\t\treset_reg = PERF_SOFTRESET_63268_REG;\n+\t\tbcm63xx_reset_bits = bcm63268_reset_bits;\n \t}\n \n \treturn 0;\n--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h\n+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h\n@@ -22,6 +22,11 @@\n #define BCM6362_CPU_ID\t\t0x6362\n #define BCM6368_CPU_ID\t\t0x6368\n #define BCM6369_CPU_ID\t\t0x6369\n+#define BCM63167_CPU_ID\t\t0x63167\n+#define BCM63168_CPU_ID\t\t0x63168\n+#define BCM63169_CPU_ID\t\t0x63169\n+#define BCM63268_CPU_ID\t\t0x63268\n+#define BCM63269_CPU_ID\t\t0x63269\n \n void __init bcm63xx_cpu_init(void);\n u32 bcm63xx_get_cpu_variant(void);\n@@ -62,6 +67,10 @@ static inline u32 __pure __bcm63xx_get_c\n #ifdef CONFIG_BCM63XX_CPU_6368\n \t\tcase BCM6368_CPU_ID:\n #endif\n+\n+#ifdef CONFIG_BCM63XX_CPU_63268\n+\t\tcase BCM63268_CPU_ID:\n+#endif\n \t\tbreak;\n \tdefault:\n \t\tunreachable();\n@@ -87,6 +96,7 @@ static inline u32 __pure bcm63xx_get_cpu\n #define BCMCPU_IS_6358()\t(bcm63xx_get_cpu_id() == BCM6358_CPU_ID)\n #define BCMCPU_IS_6362()\t(bcm63xx_get_cpu_id() == BCM6362_CPU_ID)\n #define BCMCPU_IS_6368()\t(bcm63xx_get_cpu_id() == BCM6368_CPU_ID)\n+#define BCMCPU_IS_63268()\t(bcm63xx_get_cpu_id() == BCM63268_CPU_ID)\n \n #define BCMCPU_VARIANT_IS_3368() \\\n \t(bcm63xx_get_cpu_variant() == BCM3368_CPU_ID)\n@@ -110,6 +120,16 @@ static inline u32 __pure bcm63xx_get_cpu\n \t(bcm63xx_get_cpu_variant() == BCM6368_CPU_ID)\n #define BCMCPU_VARIANT_IS_6369() \\\n \t(bcm63xx_get_cpu_variant() == BCM6369_CPU_ID)\n+#define BCMCPU_VARIANT_IS_63167() \\\n+\t(bcm63xx_get_cpu_variant() == BCM63167_CPU_ID)\n+#define BCMCPU_VARIANT_IS_63168() \\\n+\t(bcm63xx_get_cpu_variant() == BCM63168_CPU_ID)\n+#define BCMCPU_VARIANT_IS_63169() \\\n+\t(bcm63xx_get_cpu_variant() == BCM63169_CPU_ID)\n+#define BCMCPU_VARIANT_IS_63268() \\\n+\t(bcm63xx_get_cpu_variant() == BCM63268_CPU_ID)\n+#define BCMCPU_VARIANT_IS_63269() \\\n+\t(bcm63xx_get_cpu_variant() == BCM63269_CPU_ID)\n \n /*\n  * While registers sets are (mostly) the same across 63xx CPU, base\n@@ -574,6 +594,52 @@ enum bcm63xx_regs_set {\n #define BCM_6368_RNG_BASE\t\t(0xb0004180)\n #define BCM_6368_MISC_BASE\t\t(0xdeadbeef)\n \n+/*\n+ * 63268 register sets base address\n+ */\n+#define BCM_63268_DSL_LMEM_BASE\t\t(0xdeadbeef)\n+#define BCM_63268_PERF_BASE\t\t(0xb0000000)\n+#define BCM_63268_TIMER_BASE\t\t(0xb0000080)\n+#define BCM_63268_WDT_BASE\t\t(0xb000009c)\n+#define BCM_63268_UART0_BASE\t\t(0xb0000180)\n+#define BCM_63268_UART1_BASE\t\t(0xb00001a0)\n+#define BCM_63268_GPIO_BASE\t\t(0xb00000c0)\n+#define BCM_63268_SPI_BASE\t\t(0xb0000800)\n+#define BCM_63268_HSSPI_BASE\t\t(0xb0001000)\n+#define BCM_63268_UDC0_BASE\t\t(0xdeadbeef)\n+#define BCM_63268_USBDMA_BASE\t\t(0xb000c800)\n+#define BCM_63268_OHCI0_BASE\t\t(0xb0002600)\n+#define BCM_63268_OHCI_PRIV_BASE\t(0xdeadbeef)\n+#define BCM_63268_USBH_PRIV_BASE\t(0xb0002700)\n+#define BCM_63268_USBD_BASE\t\t(0xb0002400)\n+#define BCM_63268_MPI_BASE\t\t(0xdeadbeef)\n+#define BCM_63268_PCMCIA_BASE\t\t(0xdeadbeef)\n+#define BCM_63268_PCIE_BASE\t\t(0xb06e0000)\n+#define BCM_63268_SDRAM_REGS_BASE\t(0xdeadbeef)\n+#define BCM_63268_DSL_BASE\t\t(0xdeadbeef)\n+#define BCM_63268_UBUS_BASE\t\t(0xdeadbeef)\n+#define BCM_63268_ENET0_BASE\t\t(0xdeadbeef)\n+#define BCM_63268_ENET1_BASE\t\t(0xdeadbeef)\n+#define BCM_63268_ENETDMA_BASE\t\t(0xb000d800)\n+#define BCM_63268_ENETDMAC_BASE\t\t(0xb000da00)\n+#define BCM_63268_ENETDMAS_BASE\t\t(0xb000dc00)\n+#define BCM_63268_ENETSW_BASE\t\t(0xb0700000)\n+#define BCM_63268_EHCI0_BASE\t\t(0xb0002500)\n+#define BCM_63268_SDRAM_BASE\t\t(0xdeadbeef)\n+#define BCM_63268_MEMC_BASE\t\t(0xdeadbeef)\n+#define BCM_63268_DDR_BASE\t\t(0xb0003000)\n+#define BCM_63268_M2M_BASE\t\t(0xdeadbeef)\n+#define BCM_63268_ATM_BASE\t\t(0xdeadbeef)\n+#define BCM_63268_XTM_BASE\t\t(0xb0007000)\n+#define BCM_63268_XTMDMA_BASE\t\t(0xb000b800)\n+#define BCM_63268_XTMDMAC_BASE\t\t(0xdeadbeef)\n+#define BCM_63268_XTMDMAS_BASE\t\t(0xdeadbeef)\n+#define BCM_63268_PCM_BASE\t\t(0xb000b000)\n+#define BCM_63268_PCMDMA_BASE\t\t(0xb000b800)\n+#define BCM_63268_PCMDMAC_BASE\t\t(0xdeadbeef)\n+#define BCM_63268_PCMDMAS_BASE\t\t(0xdeadbeef)\n+#define BCM_63268_RNG_BASE\t\t(0xdeadbeef)\n+#define BCM_63268_MISC_BASE\t\t(0xb0001800)\n \n extern const unsigned long *bcm63xx_regs_base;\n \n@@ -1042,6 +1108,73 @@ enum bcm63xx_irq {\n #define BCM_6368_EXT_IRQ4\t\t(IRQ_INTERNAL_BASE + 24)\n #define BCM_6368_EXT_IRQ5\t\t(IRQ_INTERNAL_BASE + 25)\n \n+/*\n+ * 63268 irqs\n+ */\n+#define BCM_63268_HIGH_IRQ_BASE\t\t(IRQ_INTERNAL_BASE + 32)\n+#define BCM_63268_VERY_HIGH_IRQ_BASE\t(BCM_63268_HIGH_IRQ_BASE + 32)\n+\n+#define BCM_63268_TIMER_IRQ\t\t(IRQ_INTERNAL_BASE + 0)\n+#define BCM_63268_SPI_IRQ\t\t(BCM_63268_VERY_HIGH_IRQ_BASE + 16)\n+#define BCM_63268_UART0_IRQ\t\t(IRQ_INTERNAL_BASE + 5)\n+#define BCM_63268_UART1_IRQ\t\t(BCM_63268_HIGH_IRQ_BASE + 2)\n+#define BCM_63268_DSL_IRQ\t\t(IRQ_INTERNAL_BASE + 23)\n+#define BCM_63268_UDC0_IRQ\t\t0\n+#define BCM_63268_ENET0_IRQ\t\t0\n+#define BCM_63268_ENET1_IRQ\t\t0\n+#define BCM_63268_ENET_PHY_IRQ\t\t(IRQ_INTERNAL_BASE + 13)\n+#define BCM_63268_HSSPI_IRQ\t\t(IRQ_INTERNAL_BASE + 6)\n+#define BCM_63268_OHCI0_IRQ\t\t(IRQ_INTERNAL_BASE + 9)\n+#define BCM_63268_EHCI0_IRQ\t\t(IRQ_INTERNAL_BASE + 10)\n+#define BCM_63268_USBD_IRQ\t\t(IRQ_INTERNAL_BASE + 11)\n+#define BCM_63268_USBD_RXDMA0_IRQ\t(IRQ_INTERNAL_BASE + 19)\n+#define BCM_63268_USBD_TXDMA0_IRQ\t(BCM_63268_HIGH_IRQ_BASE + 4)\n+#define BCM_63268_USBD_RXDMA1_IRQ\t(IRQ_INTERNAL_BASE + 20)\n+#define BCM_63268_USBD_TXDMA1_IRQ\t(BCM_63268_HIGH_IRQ_BASE + 5)\n+#define BCM_63268_USBD_RXDMA2_IRQ\t(IRQ_INTERNAL_BASE + 21)\n+#define BCM_63268_USBD_TXDMA2_IRQ\t(BCM_63268_HIGH_IRQ_BASE + 6)\n+#define BCM_63268_PCMCIA_IRQ\t\t0\n+#define BCM_63268_ENET0_RXDMA_IRQ\t0\n+#define BCM_63268_ENET0_TXDMA_IRQ\t0\n+#define BCM_63268_ENET1_RXDMA_IRQ\t0\n+#define BCM_63268_ENET1_TXDMA_IRQ\t0\n+#define BCM_63268_PCI_IRQ\t\t(BCM_63268_HIGH_IRQ_BASE + 8)\n+#define BCM_63268_ATM_IRQ\t\t0\n+#define BCM_63268_ENETSW_RXDMA0_IRQ\t(IRQ_INTERNAL_BASE + 1)\n+#define BCM_63268_ENETSW_RXDMA1_IRQ\t(IRQ_INTERNAL_BASE + 2)\n+#define BCM_63268_ENETSW_RXDMA2_IRQ\t(IRQ_INTERNAL_BASE + 3)\n+#define BCM_63268_ENETSW_RXDMA3_IRQ\t(IRQ_INTERNAL_BASE + 4)\n+#define BCM_63268_ENETSW_TXDMA0_IRQ\t(BCM_63268_VERY_HIGH_IRQ_BASE + 0)\n+#define BCM_63268_ENETSW_TXDMA1_IRQ\t(BCM_63268_VERY_HIGH_IRQ_BASE + 1)\n+#define BCM_63268_ENETSW_TXDMA2_IRQ\t(BCM_63268_VERY_HIGH_IRQ_BASE + 2)\n+#define BCM_63268_ENETSW_TXDMA3_IRQ\t(BCM_63268_VERY_HIGH_IRQ_BASE + 3)\n+#define BCM_63268_XTM_IRQ\t\t(BCM_63268_HIGH_IRQ_BASE + 17)\n+#define BCM_63268_XTM_DMA0_IRQ\t\t(IRQ_INTERNAL_BASE + 26)\n+\n+#define BCM_63268_RING_OSC_IRQ\t\t(BCM_63268_HIGH_IRQ_BASE + 20)\n+#define BCM_63268_WLAN_GPIO_IRQ\t\t(BCM_63268_HIGH_IRQ_BASE + 3)\n+#define BCM_63268_WLAN_IRQ\t\t(IRQ_INTERNAL_BASE + 7)\n+#define BCM_63268_IPSEC_IRQ\t\t(IRQ_INTERNAL_BASE + 8)\n+#define BCM_63268_NAND_IRQ\t\t(BCM_63268_HIGH_IRQ_BASE + 18)\n+#define BCM_63268_PCM_IRQ\t\t(IRQ_INTERNAL_BASE + 13)\n+#define BCM_63268_DG_IRQ\t\t(IRQ_INTERNAL_BASE + 15)\n+#define BCM_63268_EPHY_ENERGY0_IRQ\t(IRQ_INTERNAL_BASE + 16)\n+#define BCM_63268_EPHY_ENERGY1_IRQ\t(IRQ_INTERNAL_BASE + 17)\n+#define BCM_63268_EPHY_ENERGY2_IRQ\t(IRQ_INTERNAL_BASE + 18)\n+#define BCM_63268_EPHY_ENERGY3_IRQ\t(IRQ_INTERNAL_BASE + 19)\n+#define BCM_63268_IPSEC_DMA0_IRQ\t(IRQ_INTERNAL_BASE + 22)\n+#define BCM_63268_IPSEC_DMA1_IRQ\t(BCM_63268_HIGH_IRQ_BASE + 7)\n+#define BCM_63268_FAP0_IRQ\t\t(IRQ_INTERNAL_BASE + 24)\n+#define BCM_63268_FAP1_IRQ\t\t(IRQ_INTERNAL_BASE + 25)\n+#define BCM_63268_PCM_DMA0_IRQ\t\t(BCM_63268_HIGH_IRQ_BASE + 10)\n+#define BCM_63268_PCM_DMA1_IRQ\t\t(BCM_63268_HIGH_IRQ_BASE + 11)\n+#define BCM_63268_DECT0_IRQ\t\t(BCM_63268_HIGH_IRQ_BASE + 0)\n+#define BCM_63268_DECT1_IRQ\t\t(BCM_63268_HIGH_IRQ_BASE + 1)\n+#define BCM_63268_EXT_IRQ0\t\t(BCM_63268_HIGH_IRQ_BASE + 12)\n+#define BCM_63268_EXT_IRQ1\t\t(BCM_63268_HIGH_IRQ_BASE + 13)\n+#define BCM_63268_EXT_IRQ2\t\t(BCM_63268_HIGH_IRQ_BASE + 14)\n+#define BCM_63268_EXT_IRQ3\t\t(BCM_63268_HIGH_IRQ_BASE + 15)\n+\n extern const int *bcm63xx_irqs;\n \n #define __GEN_CPU_IRQ_TABLE(__cpu)\t\t\t\t\t\\\n--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h\n+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h\n@@ -23,6 +23,8 @@ static inline unsigned long bcm63xx_gpio\n \t\treturn 38;\n \tcase BCM6362_CPU_ID:\n \t\treturn 48;\n+\tcase BCM63268_CPU_ID:\n+\t\treturn 52;\n \tcase BCM6348_CPU_ID:\n \tdefault:\n \t\treturn 37;\n--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h\n+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h\n@@ -10,6 +10,8 @@\n #define PERF_REV_REG\t\t\t0x0\n #define REV_CHIPID_SHIFT\t\t16\n #define REV_CHIPID_MASK\t\t\t(0xffff << REV_CHIPID_SHIFT)\n+#define REV_LONG_CHIPID_SHIFT\t\t12\n+#define REV_LONG_CHIPID_MASK\t\t(0xfffff << REV_LONG_CHIPID_SHIFT)\n #define REV_VARID_SHIFT\t\t\t12\n #define REV_VARID_MASK\t\t\t(0xf << REV_VARID_SHIFT)\n #define REV_REVID_SHIFT\t\t\t0\n@@ -212,6 +214,52 @@\n \t\t\t\t\tCKCTL_6368_NAND_EN |\t\t\\\n \t\t\t\t\tCKCTL_6368_IPSEC_EN)\n \n+#define CKCTL_63268_DISABLE_GLESS\t(1 << 0)\n+#define CKCTL_63268_VDSL_QPROC_EN\t(1 << 1)\n+#define CKCTL_63268_VDSL_AFE_EN\t\t(1 << 2)\n+#define CKCTL_63268_VDSL_EN\t\t(1 << 3)\n+#define CKCTL_63268_MIPS_EN\t\t(1 << 4)\n+#define CKCTL_63268_WLAN_OCP_EN\t\t(1 << 5)\n+#define CKCTL_63268_DECT_EN\t\t(1 << 6)\n+#define CKCTL_63268_FAP0_EN\t\t(1 << 7)\n+#define CKCTL_63268_FAP1_EN\t\t(1 << 8)\n+#define CKCTL_63268_SAR_EN\t\t(1 << 9)\n+#define CKCTL_63268_ROBOSW_EN\t\t(1 << 10)\n+#define CKCTL_63268_PCM_EN\t\t(1 << 11)\n+#define CKCTL_63268_USBD_EN\t\t(1 << 12)\n+#define CKCTL_63268_USBH_EN\t\t(1 << 13)\n+#define CKCTL_63268_IPSEC_EN\t\t(1 << 14)\n+#define CKCTL_63268_SPI_EN\t\t(1 << 15)\n+#define CKCTL_63268_HSSPI_EN\t\t(1 << 16)\n+#define CKCTL_63268_PCIE_EN\t\t(1 << 17)\n+#define CKCTL_63268_PHYMIPS_EN\t\t(1 << 18)\n+#define CKCTL_63268_GMAC_EN\t\t(1 << 19)\n+#define CKCTL_63268_NAND_EN\t\t(1 << 20)\n+#define CKCTL_63268_TBUS_EN\t\t(1 << 27)\n+#define CKCTL_63268_ROBOSW250_EN\t(1 << 31)\n+\n+#define CKCTL_63268_ALL_SAFE_EN\t\t(CKCTL_63268_VDSL_QPROC_EN |\t\\\n+\t\t\t\t\tCKCTL_63268_VDSL_AFE_EN |\t\\\n+\t\t\t\t\tCKCTL_63268_VDSL_EN |\t\t\\\n+\t\t\t\t\tCKCTL_63268_WLAN_OCP_EN |\t\\\n+\t\t\t\t\tCKCTL_63268_DECT_EN |\t\t\\\n+\t\t\t\t\tCKCTL_63268_FAP0_EN |\t\t\\\n+\t\t\t\t\tCKCTL_63268_FAP1_EN |\t\t\\\n+\t\t\t\t\tCKCTL_63268_SAR_EN |\t\t\\\n+\t\t\t\t\tCKCTL_63268_ROBOSW_EN |\t\t\\\n+\t\t\t\t\tCKCTL_63268_PCM_EN |\t\t\\\n+\t\t\t\t\tCKCTL_63268_USBD_EN |\t\t\\\n+\t\t\t\t\tCKCTL_63268_USBH_EN |\t\t\\\n+\t\t\t\t\tCKCTL_63268_IPSEC_EN |\t\t\\\n+\t\t\t\t\tCKCTL_63268_SPI_EN |\t\t\\\n+\t\t\t\t\tCKCTL_63268_HSSPI_EN |\t\t\\\n+\t\t\t\t\tCKCTL_63268_PCIE_EN |\t\t\\\n+\t\t\t\t\tCKCTL_63268_PHYMIPS_EN |\t\\\n+\t\t\t\t\tCKCTL_63268_GMAC_EN |\t\t\\\n+\t\t\t\t\tCKCTL_63268_NAND_EN |\t\t\\\n+\t\t\t\t\tCKCTL_63268_TBUS_EN |\t\t\\\n+\t\t\t\t\tCKCTL_63268_ROBOSW250_EN)\n+\n /* System PLL Control register\t*/\n #define PERF_SYS_PLL_CTL_REG\t\t0x8\n #define SYS_PLL_SOFT_RESET\t\t0x1\n@@ -225,6 +273,7 @@\n #define PERF_IRQMASK_6358_REG(x)\t(0xc + (x) * 0x2c)\n #define PERF_IRQMASK_6362_REG(x)\t(0x20 + (x) * 0x10)\n #define PERF_IRQMASK_6368_REG(x)\t(0x20 + (x) * 0x10)\n+#define PERF_IRQMASK_63268_REG(x)\t(0x20 + (x) * 0x20)\n \n /* Interrupt Status register */\n #define PERF_IRQSTAT_3368_REG\t\t0x10\n@@ -235,6 +284,7 @@\n #define PERF_IRQSTAT_6358_REG(x)\t(0x10 + (x) * 0x2c)\n #define PERF_IRQSTAT_6362_REG(x)\t(0x28 + (x) * 0x10)\n #define PERF_IRQSTAT_6368_REG(x)\t(0x28 + (x) * 0x10)\n+#define PERF_IRQSTAT_63268_REG(x)\t(0x30 + (x) * 0x20)\n \n /* External Interrupt Configuration register */\n #define PERF_EXTIRQ_CFG_REG_3368\t0x14\n@@ -245,6 +295,7 @@\n #define PERF_EXTIRQ_CFG_REG_6358\t0x14\n #define PERF_EXTIRQ_CFG_REG_6362\t0x18\n #define PERF_EXTIRQ_CFG_REG_6368\t0x18\n+#define PERF_EXTIRQ_CFG_REG_63268\t0x18\n \n #define PERF_EXTIRQ_CFG_REG2_6358\t0x1c\n #define PERF_EXTIRQ_CFG_REG2_6368\t0x1c\n@@ -275,6 +326,7 @@\n #define PERF_SOFTRESET_6358_REG\t\t0x34\n #define PERF_SOFTRESET_6362_REG\t\t0x10\n #define PERF_SOFTRESET_6368_REG\t\t0x10\n+#define PERF_SOFTRESET_63268_REG\t0x10\n \n #define SOFTRESET_3368_SPI_MASK\t\t(1 << 0)\n #define SOFTRESET_3368_ENET_MASK\t(1 << 2)\n@@ -368,6 +420,26 @@\n #define SOFTRESET_6368_USBH_MASK\t(1 << 12)\n #define SOFTRESET_6368_PCM_MASK\t\t(1 << 13)\n \n+#define SOFTRESET_63268_SPI_MASK\t(1 << 0)\n+#define SOFTRESET_63268_IPSEC_MASK\t(1 << 1)\n+#define SOFTRESET_63268_EPHY_MASK\t(1 << 2)\n+#define SOFTRESET_63268_SAR_MASK\t(1 << 3)\n+#define SOFTRESET_63268_ENETSW_MASK\t(1 << 4)\n+#define SOFTRESET_63268_USBS_MASK\t(1 << 5)\n+#define SOFTRESET_63268_USBH_MASK\t(1 << 6)\n+#define SOFTRESET_63268_PCM_MASK\t(1 << 7)\n+#define SOFTRESET_63268_PCIE_CORE_MASK\t(1 << 8)\n+#define SOFTRESET_63268_PCIE_MASK\t(1 << 9)\n+#define SOFTRESET_63268_PCIE_EXT_MASK\t(1 << 10)\n+#define SOFTRESET_63268_WLAN_SHIM_MASK\t(1 << 11)\n+#define SOFTRESET_63268_DDR_PHY_MASK\t(1 << 12)\n+#define SOFTRESET_63268_FAP0_MASK\t(1 << 13)\n+#define SOFTRESET_63268_WLAN_UBUS_MASK\t(1 << 14)\n+#define SOFTRESET_63268_DECT_MASK\t(1 << 15)\n+#define SOFTRESET_63268_FAP1_MASK\t(1 << 16)\n+#define SOFTRESET_63268_PCIE_HARD_MASK\t(1 << 17)\n+#define SOFTRESET_63268_GPHY_MASK\t(1 << 18)\n+\n /* MIPS PLL control register */\n #define PERF_MIPSPLLCTL_REG\t\t0x34\n #define MIPSPLLCTL_N1_SHIFT\t\t20\n@@ -1367,6 +1439,13 @@\n #define STRAPBUS_6362_BOOT_SEL_SERIAL\t(1 << 15)\n #define STRAPBUS_6362_BOOT_SEL_NAND\t(0 << 15)\n \n+#define MISC_STRAPBUS_63268_REG\t\t0x14\n+#define STRAPBUS_63268_HSSPI_CLK_FAST\t(1 << 9)\n+#define STRAPBUS_63268_BOOT_SEL_SERIAL\t(1 << 11)\n+#define STRAPBUS_63268_BOOT_SEL_NAND\t(0 << 11)\n+#define STRAPBUS_63268_FCVO_SHIFT\t21\n+#define STRAPBUS_63268_FCVO_MASK\t(0xf << STRAPBUS_63268_FCVO_SHIFT)\n+\n #define MISC_STRAPBUS_6328_REG\t\t0x240\n #define STRAPBUS_6328_FCVO_SHIFT\t7\n #define STRAPBUS_6328_FCVO_MASK\t\t(0x1f << STRAPBUS_6328_FCVO_SHIFT)\n--- a/arch/mips/include/asm/mach-bcm63xx/ioremap.h\n+++ b/arch/mips/include/asm/mach-bcm63xx/ioremap.h\n@@ -21,6 +21,7 @@ static inline int is_bcm63xx_internal_re\n \tcase BCM6328_CPU_ID:\n \tcase BCM6362_CPU_ID:\n \tcase BCM6368_CPU_ID:\n+\tcase BCM63268_CPU_ID:\n \t\tif (offset >= 0xb0000000 && offset < 0xb1000000)\n \t\t\treturn 1;\n \t\tbreak;\n--- a/arch/mips/bcm63xx/dev-hsspi.c\n+++ b/arch/mips/bcm63xx/dev-hsspi.c\n@@ -35,7 +35,7 @@ static struct platform_device bcm63xx_hs\n \n int __init bcm63xx_hsspi_register(void)\n {\n-\tif (!BCMCPU_IS_6328() && !BCMCPU_IS_6362())\n+\tif (!BCMCPU_IS_6328() && !BCMCPU_IS_6362() && !BCMCPU_IS_63268())\n \t\treturn -ENODEV;\n \n \tspi_resources[0].start = bcm63xx_regset_address(RSET_HSSPI);\n--- a/arch/mips/bcm63xx/dev-enet.c\n+++ b/arch/mips/bcm63xx/dev-enet.c\n@@ -184,7 +184,8 @@ static int __init register_shared(void)\n \telse\n \t\tshared_res[0].end += (RSET_ENETDMA_SIZE)  - 1;\n \n-\tif (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_6368())\n+\tif (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_6368() ||\n+\t\tBCMCPU_IS_63268())\n \t\tchan_count = 32;\n \telse if (BCMCPU_IS_6345())\n \t\tchan_count = 8;\n@@ -292,7 +293,8 @@ bcm63xx_enetsw_register(const struct bcm\n {\n \tint ret;\n \n-\tif (!BCMCPU_IS_6328() && !BCMCPU_IS_6362() && !BCMCPU_IS_6368())\n+\tif (!BCMCPU_IS_6328() && !BCMCPU_IS_6362() && !BCMCPU_IS_6368() &&\n+\t\t!BCMCPU_IS_63268())\n \t\treturn -ENODEV;\n \n \tret = register_shared();\n@@ -313,6 +315,8 @@ bcm63xx_enetsw_register(const struct bcm\n \t\tenetsw_pd.num_ports = ENETSW_PORTS_6328;\n \telse if (BCMCPU_IS_6362() || BCMCPU_IS_6368())\n \t\tenetsw_pd.num_ports = ENETSW_PORTS_6368;\n+\telse if (BCMCPU_IS_63268())\n+\t\tenetsw_pd.num_ports = ENETSW_PORTS_63268;\n \n \tenetsw_pd.dma_has_sram = true;\n \tenetsw_pd.dma_chan_width = ENETDMA_CHAN_WIDTH;\n--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h\n+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h\n@@ -67,6 +67,7 @@ struct bcm63xx_enet_platform_data {\n #define ENETSW_MAX_PORT\t8\n #define ENETSW_PORTS_6328 5 /* 4 FE PHY + 1 RGMII */\n #define ENETSW_PORTS_6368 6 /* 4 FE PHY + 2 RGMII */\n+#define ENETSW_PORTS_63268 8 /* 3 FE PHY + 1 GE PHY + 4 RGMII */\n \n #define ENETSW_RGMII_PORT0\t4\n \n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/340-MIPS-BCM63XX-add-pcie-support-for-BCM63268.patch",
    "content": "From 5c290c81dbdb4433600593fe80c88eb4af86e791 Mon Sep 17 00:00:00 2001\nFrom: Jonas Gorski <jogo@openwrt.org>\nDate: Sun, 8 Dec 2013 03:22:40 +0100\nSubject: [PATCH 50/53] MIPS: BCM63XX: add pcie support for BCM63268\n\n---\n arch/mips/bcm63xx/reset.c                       | 3 ++-\n arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h | 5 +++++\n arch/mips/pci/pci-bcm63xx.c                     | 4 ++++\n 3 files changed, 11 insertions(+), 1 deletion(-)\n\n--- a/arch/mips/bcm63xx/reset.c\n+++ b/arch/mips/bcm63xx/reset.c\n@@ -137,7 +137,8 @@\n #define BCM63268_RESET_PCM\tSOFTRESET_63268_PCM_MASK\n #define BCM63268_RESET_MPI\t0\n #define BCM63268_RESET_PCIE\t(SOFTRESET_63268_PCIE_MASK | \\\n-\t\t\t\t SOFTRESET_63268_PCIE_CORE_MASK)\n+\t\t\t\t SOFTRESET_63268_PCIE_CORE_MASK | \\\n+\t\t\t\t SOFTRESET_63268_PCIE_HARD_MASK)\n #define BCM63268_RESET_PCIE_EXT\tSOFTRESET_63268_PCIE_EXT_MASK\n \n /*\n--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h\n+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h\n@@ -46,6 +46,11 @@\n #define BCM_PCIE_MEM_END_PA_6328\t(BCM_PCIE_MEM_BASE_PA_6328 +\t\\\n \t\t\t\t\tBCM_PCIE_MEM_SIZE_6328 - 1)\n \n+#define BCM_PCIE_MEM_BASE_PA_63268\t0x11000000\n+#define BCM_PCIE_MEM_SIZE_63268\t\t(15 * 1024 * 1024)\n+#define BCM_PCIE_MEM_END_PA_63268\t(BCM_PCIE_MEM_BASE_PA_63268 +\t\\\n+\t\t\t\t\tBCM_PCIE_MEM_SIZE_63268 - 1)\n+\n /*\n  * Internal registers are accessed through KSEG3\n  */\n--- a/arch/mips/pci/pci-bcm63xx.c\n+++ b/arch/mips/pci/pci-bcm63xx.c\n@@ -337,11 +337,15 @@ static int __init bcm63xx_pci_init(void)\n \tif (BCMCPU_IS_6328() || BCMCPU_IS_6362()) {\n \t\tbcm_pcie_mem_resource.start = BCM_PCIE_MEM_BASE_PA_6328;\n \t\tbcm_pcie_mem_resource.end = BCM_PCIE_MEM_END_PA_6328;\n+\t} else if (BCMCPU_IS_63268()) {\n+\t\tbcm_pcie_mem_resource.start = BCM_PCIE_MEM_BASE_PA_63268;\n+\t\tbcm_pcie_mem_resource.end = BCM_PCIE_MEM_END_PA_63268;\n \t}\n \n \tswitch (bcm63xx_get_cpu_id()) {\n \tcase BCM6328_CPU_ID:\n \tcase BCM6362_CPU_ID:\n+\tcase BCM63268_CPU_ID:\n \t\treturn bcm63xx_register_pcie();\n \tcase BCM3368_CPU_ID:\n \tcase BCM6348_CPU_ID:\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/341-MIPS-BCM63XX-add-support-for-BCM6318.patch",
    "content": "From 60c29522a8c77d96145d965589c56befda7d4c3d Mon Sep 17 00:00:00 2001\nFrom: Jonas Gorski <jogo@openwrt.org>\nDate: Sun, 8 Dec 2013 01:24:09 +0100\nSubject: [PATCH 51/53] MIPS: BCM63XX: add support for BCM6318\n\n---\n arch/mips/bcm63xx/Kconfig                         |   5 +\n arch/mips/bcm63xx/boards/board_bcm963xx.c         |   2 +-\n arch/mips/bcm63xx/clk.c                           |   8 +-\n arch/mips/bcm63xx/cpu.c                           |  53 +++++++++++\n arch/mips/bcm63xx/dev-flash.c                     |   3 +\n arch/mips/bcm63xx/dev-spi.c                       |   2 +-\n arch/mips/bcm63xx/irq.c                           |  10 ++\n arch/mips/bcm63xx/prom.c                          |   2 +-\n arch/mips/bcm63xx/reset.c                         |  24 +++++\n arch/mips/bcm63xx/setup.c                         |   5 +-\n arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h  | 107 ++++++++++++++++++++++\n arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h |  75 ++++++++++++++-\n arch/mips/include/asm/mach-bcm63xx/ioremap.h      |   1 +\n 13 files changed, 291 insertions(+), 6 deletions(-)\n\n--- a/arch/mips/bcm63xx/Kconfig\n+++ b/arch/mips/bcm63xx/Kconfig\n@@ -19,6 +19,11 @@ config BCM63XX_EHCI\n \tselect USB_EHCI_BIG_ENDIAN_DESC if USB_EHCI_HCD\n \tselect USB_EHCI_BIG_ENDIAN_MMIO if USB_EHCI_HCD\n \n+config BCM63XX_CPU_6318\n+\tbool \"support 6318 CPU\"\n+\tselect SYS_HAS_CPU_BMIPS32_3300\n+\tselect HAVE_PCI\n+\n config BCM63XX_CPU_6328\n \tbool \"support 6328 CPU\"\n \tselect SYS_HAS_CPU_BMIPS4350\n--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c\n+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c\n@@ -681,7 +681,7 @@ void __init board_prom_init(void)\n \t/* read base address of boot chip select (0)\n \t * 6328/6362 do not have MPI but boot from a fixed address\n \t */\n-\tif (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_63268()) {\n+\tif (BCMCPU_IS_6318() || BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_63268()) {\n \t\tval = 0x18000000;\n \t} else {\n \t\tval = bcm_mpi_readl(MPI_CSBASE_REG(0));\n--- a/arch/mips/bcm63xx/clk.c\n+++ b/arch/mips/bcm63xx/clk.c\n@@ -289,7 +289,9 @@ static void hsspi_set(struct clk *clk, i\n {\n \tu32 mask;\n \n-\tif (BCMCPU_IS_6328())\n+\tif (BCMCPU_IS_6318())\n+\t\tmask = CKCTL_6318_HSSPI_EN;\n+\telse if (BCMCPU_IS_6328())\n \t\tmask = CKCTL_6328_HSSPI_EN;\n \telse if (BCMCPU_IS_6362())\n \t\tmask = CKCTL_6362_HSSPI_EN;\n@@ -456,6 +458,19 @@ static struct clk_lookup bcm3368_clks[]\n \tCLKDEV_INIT(\"bcm63xx_enet.1\", \"enet\", &clk_enet1),\n };\n \n+static struct clk_lookup bcm6318_clks[] = {\n+\t/* fixed rate clocks */\n+\tCLKDEV_INIT(NULL, \"periph\", &clk_periph),\n+\tCLKDEV_INIT(\"bcm63xx_uart.0\", \"refclk\", &clk_periph),\n+\tCLKDEV_INIT(\"bcm63xx-hsspi.0\", \"pll\", &clk_hsspi_pll),\n+\t/* gated clocks */\n+\tCLKDEV_INIT(NULL, \"enetsw\", &clk_enetsw),\n+\tCLKDEV_INIT(NULL, \"usbh\", &clk_usbh),\n+\tCLKDEV_INIT(NULL, \"usbd\", &clk_usbh),\n+\tCLKDEV_INIT(NULL, \"hsspi\", &clk_hsspi),\n+\tCLKDEV_INIT(NULL, \"pcie\", &clk_pcie),\n+};\n+\n static struct clk_lookup bcm6328_clks[] = {\n \t/* fixed rate clocks */\n \tCLKDEV_INIT(NULL, \"periph\", &clk_periph),\n@@ -577,6 +592,7 @@ static struct clk_lookup bcm63268_clks[]\n \tCLKDEV_INIT(NULL, \"pcie\", &clk_pcie),\n };\n \n+#define HSSPI_PLL_HZ_6318\t250000000\n #define HSSPI_PLL_HZ_6328\t133333333\n #define HSSPI_PLL_HZ_6362\t400000000\n \n@@ -586,6 +602,10 @@ static int __init bcm63xx_clk_init(void)\n \tcase BCM3368_CPU_ID:\n \t\tclkdev_add_table(bcm3368_clks, ARRAY_SIZE(bcm3368_clks));\n \t\tbreak;\n+\tcase BCM6318_CPU_ID:\n+\t\tclk_hsspi_pll.rate = HSSPI_PLL_HZ_6318;\n+\t\tclkdev_add_table(bcm6318_clks, ARRAY_SIZE(bcm6318_clks));\n+\t\tbreak;\n \tcase BCM6328_CPU_ID:\n \t\tclk_hsspi_pll.rate = HSSPI_PLL_HZ_6328;\n \t\tclkdev_add_table(bcm6328_clks, ARRAY_SIZE(bcm6328_clks));\n--- a/arch/mips/bcm63xx/cpu.c\n+++ b/arch/mips/bcm63xx/cpu.c\n@@ -41,6 +41,14 @@ static const int bcm3368_irqs[] = {\n \t__GEN_CPU_IRQ_TABLE(3368)\n };\n \n+static const unsigned long bcm6318_regs_base[] = {\n+\t__GEN_CPU_REGS_TABLE(6318)\n+};\n+\n+static const int bcm6318_irqs[] = {\n+\t__GEN_CPU_IRQ_TABLE(6318)\n+};\n+\n static const unsigned long bcm6328_regs_base[] = {\n \t__GEN_CPU_REGS_TABLE(6328)\n };\n@@ -134,6 +142,10 @@ unsigned int bcm63xx_get_memory_size(voi\n \treturn bcm63xx_memory_size;\n }\n \n+#define STRAP_OVERRIDE_BUS_REG\t\t0x0\n+#define OVERRIDE_BUS_MIPS_FREQ_SHIFT\t23\n+#define OVERRIDE_BUS_MIPS_FREQ_MASK\t(0x3 << OVERRIDE_BUS_MIPS_FREQ_SHIFT)\n+\n static unsigned int detect_cpu_clock(void)\n {\n \tu32 cpu_id = bcm63xx_get_cpu_id();\n@@ -142,6 +154,30 @@ static unsigned int detect_cpu_clock(voi\n \tcase BCM3368_CPU_ID:\n \t\treturn 300000000;\n \n+\tcase BCM6318_CPU_ID:\n+\t{\n+\t\tunsigned int tmp, mips_pll_fcvo;\n+\n+\t\ttmp = bcm_readl(BCM_6318_STRAP_BASE + STRAP_OVERRIDE_BUS_REG);\n+\n+\t\tpr_info(\"strap_override_bus = %08x\\n\", tmp);\n+\n+\t\tmips_pll_fcvo = (tmp & OVERRIDE_BUS_MIPS_FREQ_MASK)\n+\t\t\t\t>> OVERRIDE_BUS_MIPS_FREQ_SHIFT;\n+\n+\t\tswitch (mips_pll_fcvo) {\n+\t\tcase 0:\n+\t\t\treturn 166000000;\n+\t\tcase 1:\n+\t\t\treturn 400000000;\n+\t\tcase 2:\n+\t\t\treturn 250000000;\n+\t\tcase 3:\n+\t\t\treturn 333000000;\n+\t\tdefault:\n+\t\t\treturn 320000000;\n+\t\t}\n+\t}\n \tcase BCM6328_CPU_ID:\n \t{\n \t\tunsigned int tmp, mips_pll_fcvo;\n@@ -297,6 +333,13 @@ static unsigned int detect_memory_size(v\n \tunsigned int cols = 0, rows = 0, is_32bits = 0, banks = 0;\n \tu32 val;\n \n+\tif (BCMCPU_IS_6318()) {\n+\t\tval = bcm_sdram_readl(SDRAM_CFG_REG);\n+\t\tval = val & SDRAM_CFG_6318_SPACE_MASK;\n+\t\tval >>= SDRAM_CFG_6318_SPACE_SHIFT;\n+\t\treturn 1 << (val + 20);\n+\t}\n+\n \tif (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_63268())\n \t\treturn bcm_ddr_readl(DDR_CSEND_REG) << 24;\n \n@@ -343,6 +386,12 @@ void __init bcm63xx_cpu_init(void)\n \n \tswitch (current_cpu_type()) {\n \tcase CPU_BMIPS3300:\n+\t\tif ((read_c0_prid() & 0xff) >= 0x33) {\n+\t\t\t/* BCM6318 */\n+\t\t\tchipid_reg = BCM_6368_PERF_BASE;\n+\t\t\tbreak;\n+\t\t}\n+\n \t\tif ((read_c0_prid() & PRID_IMP_MASK) != PRID_IMP_BMIPS3300_ALT)\n \t\t\t__cpu_name[cpu] = \"Broadcom BCM6338\";\n \t\tfallthrough;\n@@ -390,6 +439,10 @@ void __init bcm63xx_cpu_init(void)\n \tbcm63xx_cpu_variant = bcm63xx_cpu_id;\n \n \tswitch (bcm63xx_cpu_id) {\n+\tcase BCM6318_CPU_ID:\n+\t\tbcm63xx_regs_base = bcm6318_regs_base;\n+\t\tbcm63xx_irqs = bcm6318_irqs;\n+\t\tbreak;\n \tcase BCM3368_CPU_ID:\n \t\tbcm63xx_regs_base = bcm3368_regs_base;\n \t\tbcm63xx_irqs = bcm3368_irqs;\n--- a/arch/mips/bcm63xx/dev-flash.c\n+++ b/arch/mips/bcm63xx/dev-flash.c\n@@ -60,6 +60,9 @@ static int __init bcm63xx_detect_flash_t\n \tu32 val;\n \n \tswitch (bcm63xx_get_cpu_id()) {\n+\tcase BCM6318_CPU_ID:\n+\t\t/* only support serial flash */\n+\t\treturn BCM63XX_FLASH_TYPE_SERIAL;\n \tcase BCM6328_CPU_ID:\n \t\tval = bcm_misc_readl(MISC_STRAPBUS_6328_REG);\n \t\tif (val & STRAPBUS_6328_BOOT_SEL_SERIAL)\n--- a/arch/mips/bcm63xx/dev-spi.c\n+++ b/arch/mips/bcm63xx/dev-spi.c\n@@ -38,7 +38,7 @@ static struct platform_device bcm63xx_sp\n \n int __init bcm63xx_spi_register(void)\n {\n-\tif (BCMCPU_IS_6328() || BCMCPU_IS_6345())\n+\tif (BCMCPU_IS_6318() || BCMCPU_IS_6328() || BCMCPU_IS_6345())\n \t\treturn -ENODEV;\n \n \tspi_resources[0].start = bcm63xx_regset_address(RSET_SPI);\n--- a/arch/mips/bcm63xx/irq.c\n+++ b/arch/mips/bcm63xx/irq.c\n@@ -48,6 +48,19 @@ void __init arch_init_irq(void)\n \t\text_irqs[3] = BCM_3368_EXT_IRQ3;\n \t\text_shift = 4;\n \t\tbreak;\n+\tcase BCM6318_CPU_ID:\n+\t\tperiph_bases[0] += PERF_IRQMASK_6318_REG;\n+\t\tperiph_irq_count = 1;\n+\t\tperiph_width = 4;\n+\n+\t\text_intc_bases[0] += PERF_EXTIRQ_CFG_REG_6318;\n+\t\text_irq_count = 4;\n+\t\text_irqs[0] = BCM_6318_EXT_IRQ0;\n+\t\text_irqs[1] = BCM_6318_EXT_IRQ0;\n+\t\text_irqs[2] = BCM_6318_EXT_IRQ0;\n+\t\text_irqs[3] = BCM_6318_EXT_IRQ0;\n+\t\text_shift = 4;\n+\t\tbreak;\n \tcase BCM6328_CPU_ID:\n \t\tperiph_bases[0] += PERF_IRQMASK_6328_REG(0);\n \t\tperiph_bases[1] += PERF_IRQMASK_6328_REG(1);\n--- a/arch/mips/bcm63xx/prom.c\n+++ b/arch/mips/bcm63xx/prom.c\n@@ -68,7 +68,7 @@ void __init prom_init(void)\n \n \t\t\tif (reg & OTP_6328_REG3_TP1_DISABLED)\n \t\t\t\tbmips_smp_enabled = 0;\n-\t\t} else if (BCMCPU_IS_3368() || BCMCPU_IS_6358()) {\n+\t\t} else if (BCMCPU_IS_6318() || BCMCPU_IS_3368() || BCMCPU_IS_6358()) {\n \t\t\tbmips_smp_enabled = 0;\n \t\t}\n \n--- a/arch/mips/bcm63xx/reset.c\n+++ b/arch/mips/bcm63xx/reset.c\n@@ -44,6 +44,23 @@\n #define BCM3368_RESET_PCIE\t0\n #define BCM3368_RESET_PCIE_EXT\t0\n \n+\n+#define BCM6318_RESET_SPI\tSOFTRESET_6318_SPI_MASK\n+#define BCM6318_RESET_ENET\t0\n+#define BCM6318_RESET_USBH\tSOFTRESET_6318_USBH_MASK\n+#define BCM6318_RESET_USBD\tSOFTRESET_6318_USBS_MASK\n+#define BCM6318_RESET_DSL\t0\n+#define BCM6318_RESET_SAR\tSOFTRESET_6318_SAR_MASK\n+#define BCM6318_RESET_EPHY\tSOFTRESET_6318_EPHY_MASK\n+#define BCM6318_RESET_ENETSW\tSOFTRESET_6318_ENETSW_MASK\n+#define BCM6318_RESET_PCM\t0\n+#define BCM6318_RESET_MPI\t0\n+#define BCM6318_RESET_PCIE\t\\\n+\t\t\t\t(SOFTRESET_6318_PCIE_MASK |\t\t\\\n+\t\t\t\t SOFTRESET_6318_PCIE_CORE_MASK |\t\\\n+\t\t\t\t SOFTRESET_6318_PCIE_HARD_MASK)\n+#define BCM6318_RESET_PCIE_EXT\tSOFTRESET_6318_PCIE_EXT_MASK\n+\n #define BCM6328_RESET_SPI\tSOFTRESET_6328_SPI_MASK\n #define BCM6328_RESET_ENET\t0\n #define BCM6328_RESET_USBH\tSOFTRESET_6328_USBH_MASK\n@@ -148,6 +165,10 @@ static const u32 bcm3368_reset_bits[] =\n \t__GEN_RESET_BITS_TABLE(3368)\n };\n \n+static const u32 bcm6318_reset_bits[] = {\n+\t__GEN_RESET_BITS_TABLE(6318)\n+};\n+\n static const u32 bcm6328_reset_bits[] = {\n \t__GEN_RESET_BITS_TABLE(6328)\n };\n@@ -184,6 +205,9 @@ static int __init bcm63xx_reset_bits_ini\n \tif (BCMCPU_IS_3368()) {\n \t\treset_reg = PERF_SOFTRESET_6358_REG;\n \t\tbcm63xx_reset_bits = bcm3368_reset_bits;\n+\t} else if (BCMCPU_IS_6318()) {\n+\t\treset_reg = PERF_SOFTRESET_6318_REG;\n+\t\tbcm63xx_reset_bits = bcm6318_reset_bits;\n \t} else if (BCMCPU_IS_6328()) {\n \t\treset_reg = PERF_SOFTRESET_6328_REG;\n \t\tbcm63xx_reset_bits = bcm6328_reset_bits;\n--- a/arch/mips/bcm63xx/setup.c\n+++ b/arch/mips/bcm63xx/setup.c\n@@ -72,6 +72,9 @@ void bcm63xx_machine_reboot(void)\n \tcase BCM3368_CPU_ID:\n \t\tperf_regs[0] = PERF_EXTIRQ_CFG_REG_3368;\n \t\tbreak;\n+\tcase BCM6318_CPU_ID:\n+\t\tperf_regs[0] = PERF_EXTIRQ_CFG_REG_6318;\n+\t\tbreak;\n \tcase BCM6328_CPU_ID:\n \t\tperf_regs[0] = PERF_EXTIRQ_CFG_REG_6328;\n \t\tbreak;\n@@ -111,7 +114,7 @@ void bcm63xx_machine_reboot(void)\n \t\tbcm6348_a1_reboot();\n \n \tpr_info(\"triggering watchdog soft-reset...\\n\");\n-\tif (BCMCPU_IS_6328()) {\n+\tif (BCMCPU_IS_6318() || BCMCPU_IS_6328()) {\n \t\tbcm_wdt_writel(1, WDT_SOFTRESET_REG);\n \t} else {\n \t\treg = bcm_perf_readl(PERF_SYS_PLL_CTL_REG);\n--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h\n+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h\n@@ -11,6 +11,7 @@\n  * arm mach-types)\n  */\n #define BCM3368_CPU_ID\t\t0x3368\n+#define BCM6318_CPU_ID\t\t0x6318\n #define BCM6328_CPU_ID\t\t0x6328\n #define BCM63281_CPU_ID\t\t0x63281\n #define BCM63283_CPU_ID\t\t0x63283\n@@ -40,6 +41,10 @@ static inline u32 __pure __bcm63xx_get_c\n \t\tcase BCM3368_CPU_ID:\n #endif\n \n+#ifdef CONFIG_BCM63XX_CPU_6318\n+\t\tcase BCM6318_CPU_ID:\n+#endif\n+\n #ifdef CONFIG_BCM63XX_CPU_6328\n \t\tcase BCM6328_CPU_ID:\n #endif\n@@ -89,6 +94,7 @@ static inline u32 __pure bcm63xx_get_cpu\n }\n \n #define BCMCPU_IS_3368()\t(bcm63xx_get_cpu_id() == BCM3368_CPU_ID)\n+#define BCMCPU_IS_6318()\t(bcm63xx_get_cpu_id() == BCM6318_CPU_ID)\n #define BCMCPU_IS_6328()\t(bcm63xx_get_cpu_id() == BCM6328_CPU_ID)\n #define BCMCPU_IS_6338()\t(bcm63xx_get_cpu_id() == BCM6338_CPU_ID)\n #define BCMCPU_IS_6345()\t(bcm63xx_get_cpu_id() == BCM6345_CPU_ID)\n@@ -100,6 +106,8 @@ static inline u32 __pure bcm63xx_get_cpu\n \n #define BCMCPU_VARIANT_IS_3368() \\\n \t(bcm63xx_get_cpu_variant() == BCM3368_CPU_ID)\n+#define BCMCPU_VARIANT_IS_6318() \\\n+\t(bcm63xx_get_cpu_variant() == BCM6318_CPU_ID)\n #define BCMCPU_VARIANT_IS_63281() \\\n \t(bcm63xx_get_cpu_variant() == BCM63281_CPU_ID)\n #define BCMCPU_VARIANT_IS_63283() \\\n@@ -256,6 +264,56 @@ enum bcm63xx_regs_set {\n #define BCM_3368_MISC_BASE\t\t(0xdeadbeef)\n \n /*\n+ * 6318 register sets base address\n+ */\n+#define BCM_6318_DSL_LMEM_BASE\t\t(0xdeadbeef)\n+#define BCM_6318_PERF_BASE\t\t(0xb0000000)\n+#define BCM_6318_TIMER_BASE\t\t(0xb0000040)\n+#define BCM_6318_WDT_BASE\t\t(0xb0000068)\n+#define BCM_6318_UART0_BASE\t\t(0xb0000100)\n+#define BCM_6318_UART1_BASE\t\t(0xdeadbeef)\n+#define BCM_6318_GPIO_BASE\t\t(0xb0000080)\n+#define BCM_6318_SPI_BASE\t\t(0xdeadbeef)\n+#define BCM_6318_HSSPI_BASE\t\t(0xb0003000)\n+#define BCM_6318_UDC0_BASE\t\t(0xdeadbeef)\n+#define BCM_6318_USBDMA_BASE\t\t(0xb0006800)\n+#define BCM_6318_OHCI0_BASE\t\t(0xb0005100)\n+#define BCM_6318_OHCI_PRIV_BASE\t\t(0xdeadbeef)\n+#define BCM_6318_USBH_PRIV_BASE\t\t(0xb0005200)\n+#define BCM_6318_USBD_BASE\t\t(0xb0006000)\n+#define BCM_6318_MPI_BASE\t\t(0xdeadbeef)\n+#define BCM_6318_PCMCIA_BASE\t\t(0xdeadbeef)\n+#define BCM_6318_PCIE_BASE\t\t(0xb0010000)\n+#define BCM_6318_SDRAM_REGS_BASE\t(0xdeadbeef)\n+#define BCM_6318_DSL_BASE\t\t(0xdeadbeef)\n+#define BCM_6318_UBUS_BASE\t\t(0xdeadbeef)\n+#define BCM_6318_ENET0_BASE\t\t(0xdeadbeef)\n+#define BCM_6318_ENET1_BASE\t\t(0xdeadbeef)\n+#define BCM_6318_ENETDMA_BASE\t\t(0xb0088000)\n+#define BCM_6318_ENETDMAC_BASE\t\t(0xb0088200)\n+#define BCM_6318_ENETDMAS_BASE\t\t(0xb0088400)\n+#define BCM_6318_ENETSW_BASE\t\t(0xb0080000)\n+#define BCM_6318_EHCI0_BASE\t\t(0xb0005000)\n+#define BCM_6318_SDRAM_BASE\t\t(0xb0004000)\n+#define BCM_6318_MEMC_BASE\t\t(0xdeadbeef)\n+#define BCM_6318_DDR_BASE\t\t(0xdeadbeef)\n+#define BCM_6318_M2M_BASE\t\t(0xdeadbeef)\n+#define BCM_6318_ATM_BASE\t\t(0xdeadbeef)\n+#define BCM_6318_XTM_BASE\t\t(0xdeadbeef)\n+#define BCM_6318_XTMDMA_BASE\t\t(0xb000c000)\n+#define BCM_6318_XTMDMAC_BASE\t\t(0xdeadbeef)\n+#define BCM_6318_XTMDMAS_BASE\t\t(0xdeadbeef)\n+#define BCM_6318_PCM_BASE\t\t(0xdeadbeef)\n+#define BCM_6318_PCMDMA_BASE\t\t(0xdeadbeef)\n+#define BCM_6318_PCMDMAC_BASE\t\t(0xdeadbeef)\n+#define BCM_6318_PCMDMAS_BASE\t\t(0xdeadbeef)\n+#define BCM_6318_RNG_BASE\t\t(0xdeadbeef)\n+#define BCM_6318_MISC_BASE\t\t(0xb0000280)\n+#define BCM_6318_OTP_BASE\t\t(0xdeadbeef)\n+\n+#define BCM_6318_STRAP_BASE\t\t(0xb0000900)\n+\n+/*\n  * 6328 register sets base address\n  */\n #define BCM_6328_DSL_LMEM_BASE\t\t(0xdeadbeef)\n@@ -778,6 +836,55 @@ enum bcm63xx_irq {\n #define BCM_3368_EXT_IRQ2\t\t(IRQ_INTERNAL_BASE + 27)\n #define BCM_3368_EXT_IRQ3\t\t(IRQ_INTERNAL_BASE + 28)\n \n+/*\n+ * 6318 irqs\n+ */\n+#define BCM_6318_HIGH_IRQ_BASE\t\t(IRQ_INTERNAL_BASE + 32)\n+#define BCM_6318_VERY_HIGH_IRQ_BASE\t(BCM_6318_HIGH_IRQ_BASE + 32)\n+\n+#define BCM_6318_TIMER_IRQ\t\t(IRQ_INTERNAL_BASE + 31)\n+#define BCM_6318_SPI_IRQ\t\t0\n+#define BCM_6318_UART0_IRQ\t\t(IRQ_INTERNAL_BASE + 28)\n+#define BCM_6318_UART1_IRQ\t\t0\n+#define BCM_6318_DSL_IRQ\t\t(IRQ_INTERNAL_BASE + 21)\n+#define BCM_6318_UDC0_IRQ\t\t0\n+#define BCM_6318_ENET0_IRQ\t\t0\n+#define BCM_6318_ENET1_IRQ\t\t0\n+#define BCM_6318_ENET_PHY_IRQ\t\t(IRQ_INTERNAL_BASE + 12)\n+#define BCM_6318_HSSPI_IRQ\t\t(IRQ_INTERNAL_BASE + 29)\n+#define BCM_6318_OHCI0_IRQ\t\t(BCM_6318_HIGH_IRQ_BASE + 9)\n+#define BCM_6318_EHCI0_IRQ\t\t(BCM_6318_HIGH_IRQ_BASE + 10)\n+#define BCM_6318_USBD_IRQ\t\t(IRQ_INTERNAL_BASE + 4)\n+#define BCM_6318_USBD_RXDMA0_IRQ\t(IRQ_INTERNAL_BASE + 5)\n+#define BCM_6318_USBD_TXDMA0_IRQ\t(IRQ_INTERNAL_BASE + 6)\n+#define BCM_6318_USBD_RXDMA1_IRQ\t(IRQ_INTERNAL_BASE + 7)\n+#define BCM_6318_USBD_TXDMA1_IRQ\t(IRQ_INTERNAL_BASE + 8)\n+#define BCM_6318_USBD_RXDMA2_IRQ\t(IRQ_INTERNAL_BASE + 9)\n+#define BCM_6318_USBD_TXDMA2_IRQ\t(IRQ_INTERNAL_BASE + 10)\n+#define BCM_6318_PCMCIA_IRQ\t\t0\n+#define BCM_6318_ENET0_RXDMA_IRQ\t0\n+#define BCM_6318_ENET0_TXDMA_IRQ\t0\n+#define BCM_6318_ENET1_RXDMA_IRQ\t0\n+#define BCM_6318_ENET1_TXDMA_IRQ\t0\n+#define BCM_6318_PCI_IRQ\t\t(IRQ_INTERNAL_BASE + 23)\n+#define BCM_6318_ATM_IRQ\t\t0\n+#define BCM_6318_ENETSW_RXDMA0_IRQ\t(BCM_6318_HIGH_IRQ_BASE + 0)\n+#define BCM_6318_ENETSW_RXDMA1_IRQ\t(BCM_6318_HIGH_IRQ_BASE + 1)\n+#define BCM_6318_ENETSW_RXDMA2_IRQ\t(BCM_6318_HIGH_IRQ_BASE + 2)\n+#define BCM_6318_ENETSW_RXDMA3_IRQ\t(BCM_6318_HIGH_IRQ_BASE + 3)\n+#define BCM_6318_ENETSW_TXDMA0_IRQ\t(BCM_6318_VERY_HIGH_IRQ_BASE + 10)\n+#define BCM_6318_ENETSW_TXDMA1_IRQ\t(BCM_6318_VERY_HIGH_IRQ_BASE + 11)\n+#define BCM_6318_ENETSW_TXDMA2_IRQ\t(BCM_6318_VERY_HIGH_IRQ_BASE + 12)\n+#define BCM_6318_ENETSW_TXDMA3_IRQ\t(BCM_6318_VERY_HIGH_IRQ_BASE + 13)\n+#define BCM_6318_XTM_IRQ\t\t(BCM_6318_HIGH_IRQ_BASE + 31)\n+#define BCM_6318_XTM_DMA0_IRQ\t\t(BCM_6318_HIGH_IRQ_BASE + 11)\n+\n+#define BCM_6318_PCM_DMA0_IRQ\t\t(IRQ_INTERNAL_BASE + 2)\n+#define BCM_6318_PCM_DMA1_IRQ\t\t(IRQ_INTERNAL_BASE + 3)\n+#define BCM_6318_EXT_IRQ0\t\t(IRQ_INTERNAL_BASE + 24)\n+#define BCM_6318_EXT_IRQ1\t\t(IRQ_INTERNAL_BASE + 25)\n+#define BCM_6318_EXT_IRQ2\t\t(IRQ_INTERNAL_BASE + 26)\n+#define BCM_6318_EXT_IRQ3\t\t(IRQ_INTERNAL_BASE + 27)\n \n /*\n  * 6328 irqs\n--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h\n+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h\n@@ -53,6 +53,39 @@\n \t\t\t\t\t CKCTL_3368_EMUSB_EN | \\\n \t\t\t\t\t CKCTL_3368_USBU_EN)\n \n+#define CKCTL_6318_ADSL_ASB_EN\t\t(1 << 0)\n+#define CKCTL_6318_USB_ASB_EN\t\t(1 << 1)\n+#define CKCTL_6318_MIPS_ASB_EN\t\t(1 << 2)\n+#define CKCTL_6318_PCIE_ASB_EN\t\t(1 << 3)\n+#define CKCTL_6318_PHYMIPS_ASB_EN\t(1 << 4)\n+#define CKCTL_6318_ROBOSW_ASB_EN\t(1 << 5)\n+#define CKCTL_6318_SAR_ASB_EN\t\t(1 << 6)\n+#define CKCTL_6318_SDR_ASB_EN\t\t(1 << 7)\n+#define CKCTL_6318_SWREG_ASB_EN\t\t(1 << 8)\n+#define CKCTL_6318_PERIPH_ASB_EN\t(1 << 9)\n+#define CKCTL_6318_CPUBUS160_EN\t\t(1 << 10)\n+#define CKCTL_6318_ADSL_EN\t\t(1 << 11)\n+#define CKCTL_6318_SAR125_EN\t\t(1 << 12)\n+#define CKCTL_6318_MIPS_EN\t\t(1 << 13)\n+#define CKCTL_6318_PCIE_EN\t\t(1 << 14)\n+#define CKCTL_6318_ROBOSW250_EN\t\t(1 << 16)\n+#define CKCTL_6318_ROBOSW025_EN\t\t(1 << 17)\n+#define CKCTL_6318_SDR_EN\t\t(1 << 19)\n+#define CKCTL_6318_USB_EN\t\t(1 << 20) /* both device and host */\n+#define CKCTL_6318_HSSPI_EN\t\t(1 << 25)\n+#define CKCTL_6318_PCIE25_EN\t\t(1 << 27)\n+#define CKCTL_6318_PHYMIPS_EN\t\t(1 << 28)\n+#define CKCTL_6318_ADSL_AFE_EN\t\t(1 << 29)\n+#define CKCTL_6318_ADSL_QPROC_EN\t(1 << 30)\n+\n+#define CKCTL_6318_ALL_SAFE_EN\t\t(CKCTL_6318_PHYMIPS_EN |\t\\\n+\t\t\t\t\tCKCTL_6318_ADSL_QPROC_EN |\t\\\n+\t\t\t\t\tCKCTL_6318_ADSL_AFE_EN |\t\\\n+\t\t\t\t\tCKCTL_6318_ADSL_EN |\t\t\\\n+\t\t\t\t\tCKCTL_6318_SAR_EN  |\t\t\\\n+\t\t\t\t\tCKCTL_6318_USB_EN |\t\t\\\n+\t\t\t\t\tCKCTL_6318_PCIE_EN)\n+\n #define CKCTL_6328_PHYMIPS_EN\t\t(1 << 0)\n #define CKCTL_6328_ADSL_QPROC_EN\t(1 << 1)\n #define CKCTL_6328_ADSL_AFE_EN\t\t(1 << 2)\n@@ -260,12 +293,27 @@\n \t\t\t\t\tCKCTL_63268_TBUS_EN |\t\t\\\n \t\t\t\t\tCKCTL_63268_ROBOSW250_EN)\n \n+/* UBUS Clock Control register */\n+#define PERF_UB_CKCTL_REG\t\t0x10\n+\n+#define UB_CKCTL_6318_ADSL_EN\t\t(1 << 0)\n+#define UB_CKCTL_6318_ARB_EN\t\t(1 << 1)\n+#define UB_CKCTL_6318_MIPS_EN\t\t(1 << 2)\n+#define UB_CKCTL_6318_PCIE_EN\t\t(1 << 3)\n+#define UB_CKCTL_6318_PERIPH_EN\t\t(1 << 4)\n+#define UB_CKCTL_6318_PHYMIPS_EN\t(1 << 5)\n+#define UB_CKCTL_6318_ROBOSW_EN\t\t(1 << 6)\n+#define UB_CKCTL_6318_SAR_EN\t\t(1 << 7)\n+#define UB_CKCTL_6318_SDR_EN\t\t(1 << 8)\n+#define UB_CKCTL_6318_USB_EN\t\t(1 << 9)\n+\n /* System PLL Control register\t*/\n #define PERF_SYS_PLL_CTL_REG\t\t0x8\n #define SYS_PLL_SOFT_RESET\t\t0x1\n \n /* Interrupt Mask register */\n #define PERF_IRQMASK_3368_REG\t\t0xc\n+#define PERF_IRQMASK_6318_REG\t\t0x20\n #define PERF_IRQMASK_6328_REG(x)\t(0x20 + (x) * 0x10)\n #define PERF_IRQMASK_6338_REG\t\t0xc\n #define PERF_IRQMASK_6345_REG\t\t0xc\n@@ -277,6 +325,7 @@\n \n /* Interrupt Status register */\n #define PERF_IRQSTAT_3368_REG\t\t0x10\n+#define PERF_IRQSTAT_6318_REG\t\t0x30\n #define PERF_IRQSTAT_6328_REG(x)\t(0x28 + (x) * 0x10)\n #define PERF_IRQSTAT_6338_REG\t\t0x10\n #define PERF_IRQSTAT_6345_REG\t\t0x10\n@@ -288,6 +337,7 @@\n \n /* External Interrupt Configuration register */\n #define PERF_EXTIRQ_CFG_REG_3368\t0x14\n+#define PERF_EXTIRQ_CFG_REG_6318\t0x18\n #define PERF_EXTIRQ_CFG_REG_6328\t0x18\n #define PERF_EXTIRQ_CFG_REG_6338\t0x14\n #define PERF_EXTIRQ_CFG_REG_6345\t0x14\n@@ -322,6 +372,7 @@\n \n /* Soft Reset register */\n #define PERF_SOFTRESET_REG\t\t0x28\n+#define PERF_SOFTRESET_6318_REG\t\t0x10\n #define PERF_SOFTRESET_6328_REG\t\t0x10\n #define PERF_SOFTRESET_6358_REG\t\t0x34\n #define PERF_SOFTRESET_6362_REG\t\t0x10\n@@ -335,6 +386,18 @@\n #define SOFTRESET_3368_USBS_MASK\t(1 << 11)\n #define SOFTRESET_3368_PCM_MASK\t\t(1 << 13)\n \n+#define SOFTRESET_6318_SPI_MASK\t\t(1 << 0)\n+#define SOFTRESET_6318_EPHY_MASK\t(1 << 1)\n+#define SOFTRESET_6318_SAR_MASK\t\t(1 << 2)\n+#define SOFTRESET_6318_ENETSW_MASK\t(1 << 3)\n+#define SOFTRESET_6318_USBS_MASK\t(1 << 4)\n+#define SOFTRESET_6318_USBH_MASK\t(1 << 5)\n+#define SOFTRESET_6318_PCIE_CORE_MASK\t(1 << 6)\n+#define SOFTRESET_6318_PCIE_MASK\t(1 << 7)\n+#define SOFTRESET_6318_PCIE_EXT_MASK\t(1 << 8)\n+#define SOFTRESET_6318_PCIE_HARD_MASK\t(1 << 9)\n+#define SOFTRESET_6318_ADSL_MASK\t(1 << 10)\n+\n #define SOFTRESET_6328_SPI_MASK\t\t(1 << 0)\n #define SOFTRESET_6328_EPHY_MASK\t(1 << 1)\n #define SOFTRESET_6328_SAR_MASK\t\t(1 << 2)\n@@ -506,8 +569,17 @@\n #define TIMER_IRQSTAT_TIMER1_IR_EN\t(1 << 9)\n #define TIMER_IRQSTAT_TIMER2_IR_EN\t(1 << 10)\n \n+#define TIMER_IRQMASK_6318_REG\t\t0x0\n+#define TIMER_IRQSTAT_6318_REG\t\t0x4\n+#define IRQSTATMASK_TIMER0\t\t(1 << 0)\n+#define IRQSTATMASK_TIMER1\t\t(1 << 1)\n+#define IRQSTATMASK_TIMER2\t\t(1 << 2)\n+#define IRQSTATMASK_TIMER3\t\t(1 << 3)\n+#define IRQSTATMASK_WDT\t\t\t(1 << 4)\n+\n /* Timer control register */\n #define TIMER_CTLx_REG(x)\t\t(0x4 + (x * 4))\n+#define TIMER_CTRx_6318_REG(x)\t\t(0x8 + (x * 4))\n #define TIMER_CTL0_REG\t\t\t0x4\n #define TIMER_CTL1_REG\t\t\t0x8\n #define TIMER_CTL2_REG\t\t\t0xC\n@@ -1254,6 +1326,8 @@\n #define SDRAM_CFG_32B_MASK\t\t(1 << SDRAM_CFG_32B_SHIFT)\n #define SDRAM_CFG_BANK_SHIFT\t\t13\n #define SDRAM_CFG_BANK_MASK\t\t(1 << SDRAM_CFG_BANK_SHIFT)\n+#define SDRAM_CFG_6318_SPACE_SHIFT\t4\n+#define SDRAM_CFG_6318_SPACE_MASK\t(0xf << SDRAM_CFG_6318_SPACE_SHIFT)\n \n #define SDRAM_MBASE_REG\t\t\t0xc\n \n--- a/arch/mips/include/asm/mach-bcm63xx/ioremap.h\n+++ b/arch/mips/include/asm/mach-bcm63xx/ioremap.h\n@@ -18,6 +18,7 @@ static inline int is_bcm63xx_internal_re\n \t\tif (offset >= 0xfff00000)\n \t\t\treturn 1;\n \t\tbreak;\n+\tcase BCM6318_CPU_ID:\n \tcase BCM6328_CPU_ID:\n \tcase BCM6362_CPU_ID:\n \tcase BCM6368_CPU_ID:\n--- a/arch/mips/bcm63xx/dev-hsspi.c\n+++ b/arch/mips/bcm63xx/dev-hsspi.c\n@@ -35,7 +35,8 @@ static struct platform_device bcm63xx_hs\n \n int __init bcm63xx_hsspi_register(void)\n {\n-\tif (!BCMCPU_IS_6328() && !BCMCPU_IS_6362() && !BCMCPU_IS_63268())\n+\tif (!BCMCPU_IS_6318() && !BCMCPU_IS_6328() && !BCMCPU_IS_6362() &&\n+\t\t!BCMCPU_IS_63268())\n \t\treturn -ENODEV;\n \n \tspi_resources[0].start = bcm63xx_regset_address(RSET_HSSPI);\n--- a/arch/mips/bcm63xx/dev-usb-usbd.c\n+++ b/arch/mips/bcm63xx/dev-usb-usbd.c\n@@ -41,7 +41,7 @@ int __init bcm63xx_usbd_register(const s\n \t\tIRQ_USBD_RXDMA2, IRQ_USBD_TXDMA2 };\n \tint i;\n \n-\tif (!BCMCPU_IS_6328() && !BCMCPU_IS_6368())\n+\tif (!BCMCPU_IS_6318() && !BCMCPU_IS_6328() && !BCMCPU_IS_6368())\n \t\treturn 0;\n \n \tusbd_resources[0].start = bcm63xx_regset_address(RSET_USBD);\n--- a/arch/mips/bcm63xx/dev-enet.c\n+++ b/arch/mips/bcm63xx/dev-enet.c\n@@ -184,8 +184,8 @@ static int __init register_shared(void)\n \telse\n \t\tshared_res[0].end += (RSET_ENETDMA_SIZE)  - 1;\n \n-\tif (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_6368() ||\n-\t\tBCMCPU_IS_63268())\n+\tif (BCMCPU_IS_6318() || BCMCPU_IS_6328() || BCMCPU_IS_6362() ||\n+\t\tBCMCPU_IS_6368() || BCMCPU_IS_63268())\n \t\tchan_count = 32;\n \telse if (BCMCPU_IS_6345())\n \t\tchan_count = 8;\n@@ -293,8 +293,8 @@ bcm63xx_enetsw_register(const struct bcm\n {\n \tint ret;\n \n-\tif (!BCMCPU_IS_6328() && !BCMCPU_IS_6362() && !BCMCPU_IS_6368() &&\n-\t\t!BCMCPU_IS_63268())\n+\tif (!BCMCPU_IS_6318() && !BCMCPU_IS_6328() && !BCMCPU_IS_6362() &&\n+\t\t!BCMCPU_IS_6368() && !BCMCPU_IS_63268())\n \t\treturn -ENODEV;\n \n \tret = register_shared();\n@@ -311,7 +311,7 @@ bcm63xx_enetsw_register(const struct bcm\n \n \tmemcpy(bcm63xx_enetsw_device.dev.platform_data, pd, sizeof(*pd));\n \n-\tif (BCMCPU_IS_6328())\n+\tif (BCMCPU_IS_6318() || BCMCPU_IS_6328())\n \t\tenetsw_pd.num_ports = ENETSW_PORTS_6328;\n \telse if (BCMCPU_IS_6362() || BCMCPU_IS_6368())\n \t\tenetsw_pd.num_ports = ENETSW_PORTS_6368;\n--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h\n+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h\n@@ -10,6 +10,8 @@ int __init bcm63xx_gpio_init(void);\n static inline unsigned long bcm63xx_gpio_count(void)\n {\n \tswitch (bcm63xx_get_cpu_id()) {\n+\tcase BCM6318_CPU_ID:\n+\t\treturn 50;\n \tcase BCM6328_CPU_ID:\n \t\treturn 32;\n \tcase BCM3368_CPU_ID:\n--- a/arch/mips/bcm63xx/dev-usb-ehci.c\n+++ b/arch/mips/bcm63xx/dev-usb-ehci.c\n@@ -81,7 +81,8 @@ static struct platform_device bcm63xx_eh\n \n int __init bcm63xx_ehci_register(void)\n {\n-\tif (!BCMCPU_IS_6328() && !BCMCPU_IS_6358() && !BCMCPU_IS_6362() && !BCMCPU_IS_6368())\n+\tif (!BCMCPU_IS_6318() && !BCMCPU_IS_6328() && !BCMCPU_IS_6358() &&\n+\t\t!BCMCPU_IS_6362() && !BCMCPU_IS_6368())\n \t\treturn 0;\n \n \tehci_resources[0].start = bcm63xx_regset_address(RSET_EHCI0);\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/342-MIPS-BCM63XX-split-PCIe-reset-signals.patch",
    "content": "From 4bdfacdeaf3c988c4f3256c88118893eac640b03 Mon Sep 17 00:00:00 2001\nFrom: Jonas Gorski <jogo@openwrt.org>\nDate: Sun, 8 Dec 2013 14:17:50 +0100\nSubject: [PATCH 52/53] MIPS: BCM63XX: split PCIE reset signals\n\n---\n arch/mips/bcm63xx/reset.c                          | 39 ++++++++++++++--------\n arch/mips/include/asm/mach-bcm63xx/bcm63xx_reset.h |  2 ++\n arch/mips/pci/pci-bcm63xx.c                        |  7 ++++\n 3 files changed, 34 insertions(+), 14 deletions(-)\n\n--- a/arch/mips/bcm63xx/reset.c\n+++ b/arch/mips/bcm63xx/reset.c\n@@ -29,7 +29,9 @@\n \t[BCM63XX_RESET_PCM]\t\t= BCM## __cpu ##_RESET_PCM,\t\\\n \t[BCM63XX_RESET_MPI]\t\t= BCM## __cpu ##_RESET_MPI,\t\\\n \t[BCM63XX_RESET_PCIE]\t\t= BCM## __cpu ##_RESET_PCIE,\t\\\n-\t[BCM63XX_RESET_PCIE_EXT]\t= BCM## __cpu ##_RESET_PCIE_EXT,\n+\t[BCM63XX_RESET_PCIE_EXT]\t= BCM## __cpu ##_RESET_PCIE_EXT, \\\n+\t[BCM63XX_RESET_PCIE_CORE]\t= BCM## __cpu ##_RESET_PCIE_CORE, \\\n+\t[BCM63XX_RESET_PCIE_HARD]\t= BCM## __cpu ##_RESET_PCIE_HARD,\n \n #define BCM3368_RESET_SPI\tSOFTRESET_3368_SPI_MASK\n #define BCM3368_RESET_ENET\tSOFTRESET_3368_ENET_MASK\n@@ -43,6 +45,8 @@\n #define BCM3368_RESET_MPI\tSOFTRESET_3368_MPI_MASK\n #define BCM3368_RESET_PCIE\t0\n #define BCM3368_RESET_PCIE_EXT\t0\n+#define BCM3368_RESET_PCIE_CORE\t0\n+#define BCM3368_RESET_PCIE_HARD\t0\n \n \n #define BCM6318_RESET_SPI\tSOFTRESET_6318_SPI_MASK\n@@ -55,11 +59,10 @@\n #define BCM6318_RESET_ENETSW\tSOFTRESET_6318_ENETSW_MASK\n #define BCM6318_RESET_PCM\t0\n #define BCM6318_RESET_MPI\t0\n-#define BCM6318_RESET_PCIE\t\\\n-\t\t\t\t(SOFTRESET_6318_PCIE_MASK |\t\t\\\n-\t\t\t\t SOFTRESET_6318_PCIE_CORE_MASK |\t\\\n-\t\t\t\t SOFTRESET_6318_PCIE_HARD_MASK)\n+#define BCM6318_RESET_PCIE\tSOFTRESET_6318_PCIE_MASK\n #define BCM6318_RESET_PCIE_EXT\tSOFTRESET_6318_PCIE_EXT_MASK\n+#define BCM6318_RESET_PCIE_CORE\tSOFTRESET_6318_PCIE_CORE_MASK\n+#define BCM6318_RESET_PCIE_HARD\tSOFTRESET_6318_PCIE_HARD_MASK\n \n #define BCM6328_RESET_SPI\tSOFTRESET_6328_SPI_MASK\n #define BCM6328_RESET_ENET\t0\n@@ -71,11 +74,10 @@\n #define BCM6328_RESET_ENETSW\tSOFTRESET_6328_ENETSW_MASK\n #define BCM6328_RESET_PCM\tSOFTRESET_6328_PCM_MASK\n #define BCM6328_RESET_MPI\t0\n-#define BCM6328_RESET_PCIE\t\\\n-\t\t\t\t(SOFTRESET_6328_PCIE_MASK |\t\t\\\n-\t\t\t\t SOFTRESET_6328_PCIE_CORE_MASK |\t\\\n-\t\t\t\t SOFTRESET_6328_PCIE_HARD_MASK)\n+#define BCM6328_RESET_PCIE\tSOFTRESET_6328_PCIE_MASK\n #define BCM6328_RESET_PCIE_EXT\tSOFTRESET_6328_PCIE_EXT_MASK\n+#define BCM6328_RESET_PCIE_CORE\tSOFTRESET_6328_PCIE_CORE_MASK\n+#define BCM6328_RESET_PCIE_HARD\tSOFTRESET_6328_PCIE_HARD_MASK\n \n #define BCM6338_RESET_SPI\tSOFTRESET_6338_SPI_MASK\n #define BCM6338_RESET_ENET\tSOFTRESET_6338_ENET_MASK\n@@ -89,6 +91,8 @@\n #define BCM6338_RESET_MPI\t0\n #define BCM6338_RESET_PCIE\t0\n #define BCM6338_RESET_PCIE_EXT\t0\n+#define BCM6338_RESET_PCIE_CORE\t0\n+#define BCM6338_RESET_PCIE_HARD\t0\n \n #define BCM6348_RESET_SPI\tSOFTRESET_6348_SPI_MASK\n #define BCM6348_RESET_ENET\tSOFTRESET_6348_ENET_MASK\n@@ -102,6 +106,8 @@\n #define BCM6348_RESET_MPI\t0\n #define BCM6348_RESET_PCIE\t0\n #define BCM6348_RESET_PCIE_EXT\t0\n+#define BCM6348_RESET_PCIE_CORE\t0\n+#define BCM6348_RESET_PCIE_HARD\t0\n \n #define BCM6358_RESET_SPI\tSOFTRESET_6358_SPI_MASK\n #define BCM6358_RESET_ENET\tSOFTRESET_6358_ENET_MASK\n@@ -115,6 +121,8 @@\n #define BCM6358_RESET_MPI\tSOFTRESET_6358_MPI_MASK\n #define BCM6358_RESET_PCIE\t0\n #define BCM6358_RESET_PCIE_EXT\t0\n+#define BCM6358_RESET_PCIE_CORE\t0\n+#define BCM6358_RESET_PCIE_HARD\t0\n \n #define BCM6362_RESET_SPI\tSOFTRESET_6362_SPI_MASK\n #define BCM6362_RESET_ENET\t0\n@@ -126,9 +134,10 @@\n #define BCM6362_RESET_ENETSW\tSOFTRESET_6362_ENETSW_MASK\n #define BCM6362_RESET_PCM\tSOFTRESET_6362_PCM_MASK\n #define BCM6362_RESET_MPI\t0\n-#define BCM6362_RESET_PCIE      (SOFTRESET_6362_PCIE_MASK | \\\n-\t\t\t\t SOFTRESET_6362_PCIE_CORE_MASK)\n+#define BCM6362_RESET_PCIE      SOFTRESET_6362_PCIE_MASK\n #define BCM6362_RESET_PCIE_EXT\tSOFTRESET_6362_PCIE_EXT_MASK\n+#define BCM6362_RESET_PCIE_CORE\tSOFTRESET_6362_PCIE_CORE_MASK\n+#define BCM6362_RESET_PCIE_HARD\t0\n \n #define BCM6368_RESET_SPI\tSOFTRESET_6368_SPI_MASK\n #define BCM6368_RESET_ENET\t0\n@@ -142,6 +151,8 @@\n #define BCM6368_RESET_MPI\tSOFTRESET_6368_MPI_MASK\n #define BCM6368_RESET_PCIE\t0\n #define BCM6368_RESET_PCIE_EXT\t0\n+#define BCM6368_RESET_PCIE_CORE\t0\n+#define BCM6368_RESET_PCIE_HARD\t0\n \n #define BCM63268_RESET_SPI\tSOFTRESET_63268_SPI_MASK\n #define BCM63268_RESET_ENET\t0\n@@ -153,10 +164,10 @@\n #define BCM63268_RESET_ENETSW\tSOFTRESET_63268_ENETSW_MASK\n #define BCM63268_RESET_PCM\tSOFTRESET_63268_PCM_MASK\n #define BCM63268_RESET_MPI\t0\n-#define BCM63268_RESET_PCIE\t(SOFTRESET_63268_PCIE_MASK | \\\n-\t\t\t\t SOFTRESET_63268_PCIE_CORE_MASK | \\\n-\t\t\t\t SOFTRESET_63268_PCIE_HARD_MASK)\n+#define BCM63268_RESET_PCIE\tSOFTRESET_63268_PCIE_MASK\n #define BCM63268_RESET_PCIE_EXT\tSOFTRESET_63268_PCIE_EXT_MASK\n+#define BCM63268_RESET_PCIE_CORE\tSOFTRESET_63268_PCIE_CORE_MASK\n+#define BCM63268_RESET_PCIE_HARD\tSOFTRESET_63268_PCIE_HARD_MASK\n \n /*\n  * core reset bits\n--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_reset.h\n+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_reset.h\n@@ -15,6 +15,8 @@ enum bcm63xx_core_reset {\n \tBCM63XX_RESET_MPI,\n \tBCM63XX_RESET_PCIE,\n \tBCM63XX_RESET_PCIE_EXT,\n+\tBCM63XX_RESET_PCIE_CORE,\n+\tBCM63XX_RESET_PCIE_HARD,\n };\n \n void bcm63xx_core_set_reset(enum bcm63xx_core_reset, int reset);\n--- a/arch/mips/pci/pci-bcm63xx.c\n+++ b/arch/mips/pci/pci-bcm63xx.c\n@@ -135,9 +135,16 @@ static void __init bcm63xx_reset_pcie(vo\n \n \t/* reset the PCIe core */\n \tbcm63xx_core_set_reset(BCM63XX_RESET_PCIE, 1);\n+\tbcm63xx_core_set_reset(BCM63XX_RESET_PCIE_CORE, 1);\n \tbcm63xx_core_set_reset(BCM63XX_RESET_PCIE_EXT, 1);\n+\tif (BCMCPU_IS_6328() || BCMCPU_IS_63268()) {\n+\t\tbcm63xx_core_set_reset(BCM63XX_RESET_PCIE_HARD, 1);\n+\t\tmdelay(10);\n+\t\tbcm63xx_core_set_reset(BCM63XX_RESET_PCIE_HARD, 0);\n+\t}\n \tmdelay(10);\n \n+\tbcm63xx_core_set_reset(BCM63XX_RESET_PCIE_CORE, 0);\n \tbcm63xx_core_set_reset(BCM63XX_RESET_PCIE, 0);\n \tmdelay(10);\n \n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/343-MIPS-BCM63XX-add-PCIe-support-for-BCM6318.patch",
    "content": "From 11a8ab8dac4ef5d0d70199843043927edce1d4db Mon Sep 17 00:00:00 2001\nFrom: Jonas Gorski <jogo@openwrt.org>\nDate: Sun, 15 Dec 2013 20:47:34 +0100\nSubject: [PATCH 53/53] MIPS: BCM63XX: add PCIe support for BCM6318\n\n---\n arch/mips/bcm63xx/clk.c                           |  25 ++++-\n arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h   |   6 ++\n arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h |  60 +++++++++++-\n arch/mips/pci/ops-bcm63xx.c                       |  16 +++-\n arch/mips/pci/pci-bcm63xx.c                       | 106 ++++++++++++++++++----\n 5 files changed, 184 insertions(+), 29 deletions(-)\n\n--- a/arch/mips/bcm63xx/clk.c\n+++ b/arch/mips/bcm63xx/clk.c\n@@ -52,6 +52,18 @@ static void bcm_hwclock_set(u32 mask, in\n \tbcm_perf_writel(reg, PERF_CKCTL_REG);\n }\n \n+static void bcm_ub_hwclock_set(u32 mask, int enable)\n+{\n+\tu32 reg;\n+\n+\treg = bcm_perf_readl(PERF_UB_CKCTL_REG);\n+\tif (enable)\n+\t\treg |= mask;\n+\telse\n+\t\treg &= ~mask;\n+\tbcm_perf_writel(reg, PERF_UB_CKCTL_REG);\n+}\n+\n /*\n  * Ethernet MAC \"misc\" clock: dma clocks and main clock on 6348\n  */\n@@ -362,12 +374,17 @@ static struct clk clk_ipsec = {\n \n static void pcie_set(struct clk *clk, int enable)\n {\n-\tif (BCMCPU_IS_6328())\n+\tif (BCMCPU_IS_6318()) {\n+\t\tbcm_hwclock_set(CKCTL_6318_PCIE_EN, enable);\n+\t\tbcm_hwclock_set(CKCTL_6318_PCIE25_EN, enable);\n+\t\tbcm_ub_hwclock_set(UB_CKCTL_6318_PCIE_EN, enable);\n+\t} else if (BCMCPU_IS_6328()) {\n \t\tbcm_hwclock_set(CKCTL_6328_PCIE_EN, enable);\n-\telse if (BCMCPU_IS_6362())\n+\t} else if (BCMCPU_IS_6362()) {\n \t\tbcm_hwclock_set(CKCTL_6362_PCIE_EN, enable);\n-\telse if (BCMCPU_IS_63268())\n+\t} else if (BCMCPU_IS_63268()) {\n \t\tbcm_hwclock_set(CKCTL_63268_PCIE_EN, enable);\n+\t}\n }\n \n static struct clk clk_pcie = {\n--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h\n+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h\n@@ -41,6 +41,12 @@\n #define BCM_CB_MEM_END_PA\t\t(BCM_CB_MEM_BASE_PA +\t\t\\\n \t\t\t\t\tBCM_CB_MEM_SIZE - 1)\n \n+#define BCM_PCIE_MEM_BASE_PA_6318\t0x10200000\n+#define BCM_PCIE_MEM_SIZE_6318\t\t(1 * 1024 * 1024)\n+#define BCM_PCIE_MEM_END_PA_6318\t(BCM_PCIE_MEM_BASE_PA_6318 +\t\\\n+\t\t\t\t\tBCM_PCIE_MEM_SIZE_6318 - 1)\n+\n+\n #define BCM_PCIE_MEM_BASE_PA_6328\t0x10f00000\n #define BCM_PCIE_MEM_SIZE_6328\t\t(1 * 1024 * 1024)\n #define BCM_PCIE_MEM_END_PA_6328\t(BCM_PCIE_MEM_BASE_PA_6328 +\t\\\n--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h\n+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h\n@@ -1530,6 +1530,17 @@\n  * _REG relative to RSET_PCIE\n  *************************************************************************/\n \n+#define PCIE_SPECIFIC_REG\t\t0x188\n+#define SPECIFIC_ENDIAN_MODE_BAR1_SHIFT\t0\n+#define SPECIFIC_ENDIAN_MODE_BAR1_MASK\t(0x3 << SPECIFIC_ENDIAN_MODE_BAR1_SHIFT)\n+#define SPECIFIC_ENDIAN_MODE_BAR2_SHIFT\t2\n+#define SPECIFIC_ENDIAN_MODE_BAR2_MASK\t(0x3 << SPECIFIC_ENDIAN_MODE_BAR1_SHIFT)\n+#define SPECIFIC_ENDIAN_MODE_BAR3_SHIFT\t4\n+#define SPECIFIC_ENDIAN_MODE_BAR3_MASK\t(0x3 << SPECIFIC_ENDIAN_MODE_BAR1_SHIFT)\n+#define SPECIFIC_ENDIAN_MODE_WORD_ALIGN\t0\n+#define SPECIFIC_ENDIAN_MODE_HALFWORD_ALIGN 1\n+#define SPECIFIC_ENDIAN_MODE_BYTE_ALIGN\t2\n+\n #define PCIE_CONFIG2_REG\t\t0x408\n #define CONFIG2_BAR1_SIZE_EN\t\t1\n #define CONFIG2_BAR1_SIZE_MASK\t\t0xf\n@@ -1575,7 +1586,54 @@\n #define PCIE_RC_INT_C\t\t\t(1 << 2)\n #define PCIE_RC_INT_D\t\t\t(1 << 3)\n \n-#define PCIE_DEVICE_OFFSET\t\t0x8000\n+#define PCIE_CPU_2_PCIE_MEM_WIN0_LO_REG\t0x400c\n+#define C2P_MEM_WIN_ENDIAN_MODE_MASK\t0x3\n+#define C2P_MEM_WIN_ENDIAN_NO_SWAP\t0\n+#define C2P_MEM_WIN_ENDIAN_HALF_WORD_SWAP 1\n+#define C2P_MEM_WIN_ENDIAN_HALF_BYTE_SWAP 2\n+#define C2P_MEM_WIN_BASE_ADDR_SHIFT\t20\n+#define C2P_MEM_WIN_BASE_ADDR_MASK\t(0xfff << C2P_MEM_WIN_BASE_ADDR_SHIFT)\n+\n+#define PCIE_RC_BAR1_CONFIG_LO_REG\t0x402c\n+#define RC_BAR_CFG_LO_SIZE_256MB\t0xd\n+#define RC_BAR_CFG_LO_MATCH_ADDR_SHIFT\t20\n+#define RC_BAR_CFG_LO_MATCH_ADDR_MASK\t(0xfff << RC_BAR_CFG_LO_MATCH_ADDR_SHIFT)\n+\n+#define PCIE_CPU_2_PCIE_MEM_WIN0_BASELIMIT_REG 0x4070\n+#define C2P_BASELIMIT_LIMIT_SHIFT\t20\n+#define C2P_BASELIMIT_LIMIT_MASK\t(0xfff << C2P_BASELIMIT_LIMIT_SHIFT)\n+#define C2P_BASELIMIT_BASE_SHIFT\t4\n+#define C2P_BASELIMIT_BASE_MASK\t\t(0xfff << C2P_BASELIMIT_BASE_SHIFT)\n+\n+#define PCIE_UBUS_BAR1_CFG_REMAP_REG\t0x4088\n+#define BAR1_CFG_REMAP_OFFSET_SHIFT\t20\n+#define BAR1_CFG_REMAP_OFFSET_MASK\t(0xfff << BAR1_CFG_REMAP_OFFSET_SHIFT)\n+#define BAR1_CFG_REMAP_ACCESS_EN\t1\n+\n+#define PCIE_HARD_DEBUG_REG\t\t0x4204\n+#define HARD_DEBUG_SERDES_IDDQ\t\t(1 << 23)\n+\n+#define PCIE_CPU_INT1_MASK_CLEAR_REG\t0x830c\n+#define CPU_INT_PCIE_ERR_ATTN_CPU\t(1 << 0)\n+#define CPU_INT_PCIE_INTA\t\t(1 << 1)\n+#define CPU_INT_PCIE_INTB\t\t(1 << 2)\n+#define CPU_INT_PCIE_INTC\t\t(1 << 3)\n+#define CPU_INT_PCIE_INTD\t\t(1 << 4)\n+#define CPU_INT_PCIE_INTR\t\t(1 << 5)\n+#define CPU_INT_PCIE_NMI\t\t(1 << 6)\n+#define CPU_INT_PCIE_UBUS\t\t(1 << 7)\n+#define CPU_INT_IPI\t\t\t(1 << 8)\n+\n+#define PCIE_EXT_CFG_INDEX_REG\t\t0x8400\n+#define EXT_CFG_FUNC_NUM_SHIFT\t\t12\n+#define EXT_CFG_FUNC_NUM_MASK\t\t(0x7 << EXT_CFG_FUNC_NUM_SHIFT)\n+#define EXT_CFG_DEV_NUM_SHIFT\t\t15\n+#define EXT_CFG_DEV_NUM_MASK\t\t(0xf << EXT_CFG_DEV_NUM_SHIFT)\n+#define EXT_CFG_BUS_NUM_SHIFT\t\t20\n+#define EXT_CFG_BUS_NUM_MASK\t\t(0xff << EXT_CFG_BUS_NUM_SHIFT)\n+\n+#define PCIE_DEVICE_OFFSET_6318\t\t0x9000\n+#define PCIE_DEVICE_OFFSET_6328\t\t0x8000\n \n /*************************************************************************\n  * _REG relative to RSET_OTP\n--- a/arch/mips/pci/ops-bcm63xx.c\n+++ b/arch/mips/pci/ops-bcm63xx.c\n@@ -489,8 +489,12 @@ static int bcm63xx_pcie_read(struct pci_\n \tif (!bcm63xx_pcie_can_access(bus, devfn))\n \t\treturn PCIBIOS_DEVICE_NOT_FOUND;\n \n-\tif (bus->number == PCIE_BUS_DEVICE)\n-\t\treg += PCIE_DEVICE_OFFSET;\n+\tif (bus->number == PCIE_BUS_DEVICE) {\n+\t\tif (BCMCPU_IS_6318())\n+\t\t\treg += PCIE_DEVICE_OFFSET_6318;\n+\t\telse\n+\t\t\treg += PCIE_DEVICE_OFFSET_6328;\n+\t}\n \n \tdata = bcm_pcie_readl(reg);\n \n@@ -509,8 +513,12 @@ static int bcm63xx_pcie_write(struct pci\n \tif (!bcm63xx_pcie_can_access(bus, devfn))\n \t\treturn PCIBIOS_DEVICE_NOT_FOUND;\n \n-\tif (bus->number == PCIE_BUS_DEVICE)\n-\t\treg += PCIE_DEVICE_OFFSET;\n+\tif (bus->number == PCIE_BUS_DEVICE) {\n+\t\tif (BCMCPU_IS_6318())\n+\t\t\treg += PCIE_DEVICE_OFFSET_6318;\n+\t\telse\n+\t\t\treg += PCIE_DEVICE_OFFSET_6328;\n+\t}\n \n \n \tdata = bcm_pcie_readl(reg);\n--- a/arch/mips/pci/pci-bcm63xx.c\n+++ b/arch/mips/pci/pci-bcm63xx.c\n@@ -118,7 +118,7 @@ static void bcm63xx_int_cfg_writel(u32 v\n \n void __iomem *pci_iospace_start;\n \n-static void __init bcm63xx_reset_pcie(void)\n+static void __init bcm63xx_reset_pcie_gen1(void)\n {\n \tu32 val;\n \tu32 reg;\n@@ -152,20 +152,32 @@ static void __init bcm63xx_reset_pcie(vo\n \tmdelay(200);\n }\n \n-static struct clk *pcie_clk;\n-\n-static int __init bcm63xx_register_pcie(void)\n+static void __init bcm63xx_reset_pcie_gen2(void)\n {\n \tu32 val;\n \n-\t/* enable clock */\n-\tpcie_clk = clk_get(NULL, \"pcie\");\n-\tif (IS_ERR_OR_NULL(pcie_clk))\n-\t\treturn -ENODEV;\n+\tbcm63xx_core_set_reset(BCM63XX_RESET_PCIE_HARD, 0);\n \n-\tclk_prepare_enable(pcie_clk);\n+\t/* reset the PCIe core */\n+\tbcm63xx_core_set_reset(BCM63XX_RESET_PCIE, 1);\n+\tbcm63xx_core_set_reset(BCM63XX_RESET_PCIE_EXT, 1);\n+\tbcm63xx_core_set_reset(BCM63XX_RESET_PCIE_CORE, 1);\n+\tmdelay(10);\n+\tbcm63xx_core_set_reset(BCM63XX_RESET_PCIE_EXT, 0);\n+\tmdelay(10);\n+\tbcm63xx_core_set_reset(BCM63XX_RESET_PCIE, 0);\n+\tmdelay(10);\n+\tval = bcm_pcie_readl(PCIE_HARD_DEBUG_REG);\n+\tval &= ~HARD_DEBUG_SERDES_IDDQ;\n+\tbcm_pcie_writel(val, PCIE_HARD_DEBUG_REG);\n+\tmdelay(10);\n+\tbcm63xx_core_set_reset(BCM63XX_RESET_PCIE_CORE, 0);\n+\tmdelay(200);\n+}\n \n-\tbcm63xx_reset_pcie();\n+static void __init bcm63xx_init_pcie_gen1(void)\n+{\n+\tu32 val;\n \n \t/* configure the PCIe bridge */\n \tval = bcm_pcie_readl(PCIE_BRIDGE_OPT1_REG);\n@@ -190,6 +202,65 @@ static int __init bcm63xx_register_pcie(\n \tval |= OPT2_CFG_TYPE1_BD_SEL;\n \tbcm_pcie_writel(val, PCIE_BRIDGE_OPT2_REG);\n \n+\t/* set bar0 to little endian */\n+\tval = (bcm_pcie_mem_resource.start >> 20) << BASEMASK_BASE_SHIFT;\n+\tval |= (bcm_pcie_mem_resource.end >> 20) << BASEMASK_MASK_SHIFT;\n+\tval |= BASEMASK_REMAP_EN;\n+\tbcm_pcie_writel(val, PCIE_BRIDGE_BAR0_BASEMASK_REG);\n+\n+\tval = (bcm_pcie_mem_resource.start >> 20) << REBASE_ADDR_BASE_SHIFT;\n+\tbcm_pcie_writel(val, PCIE_BRIDGE_BAR0_REBASE_ADDR_REG);\n+}\n+\n+static void __init bcm63xx_init_pcie_gen2(void)\n+{\n+\tu32 val;\n+\n+\tbcm_pcie_writel(CPU_INT_PCIE_INTA | CPU_INT_PCIE_INTB |\n+\t\t\tCPU_INT_PCIE_INTC | CPU_INT_PCIE_INTD,\n+\t\t\tPCIE_CPU_INT1_MASK_CLEAR_REG);\n+\n+\tval = bcm_pcie_mem_resource.end & C2P_BASELIMIT_LIMIT_MASK;\n+\tval |= (bcm_pcie_mem_resource.start >> C2P_BASELIMIT_LIMIT_SHIFT) <<\n+\t       C2P_BASELIMIT_BASE_SHIFT;\n+\n+\tbcm_pcie_writel(val, PCIE_CPU_2_PCIE_MEM_WIN0_BASELIMIT_REG);\n+\n+\t/* set bar0 to little endian */\n+\tval = bcm_pcie_readl(PCIE_CPU_2_PCIE_MEM_WIN0_LO_REG);\n+\tval |= bcm_pcie_mem_resource.start & C2P_MEM_WIN_BASE_ADDR_MASK;\n+\tval |= C2P_MEM_WIN_ENDIAN_HALF_BYTE_SWAP;\n+\tbcm_pcie_writel(val, PCIE_CPU_2_PCIE_MEM_WIN0_LO_REG);\n+\n+\tbcm_pcie_writel(SPECIFIC_ENDIAN_MODE_BYTE_ALIGN, PCIE_SPECIFIC_REG);\n+\tbcm_pcie_writel(RC_BAR_CFG_LO_SIZE_256MB, PCIE_RC_BAR1_CONFIG_LO_REG);\n+\tbcm_pcie_writel(BAR1_CFG_REMAP_ACCESS_EN, PCIE_UBUS_BAR1_CFG_REMAP_REG);\n+\n+\tbcm_pcie_writel(PCIE_BUS_DEVICE << EXT_CFG_BUS_NUM_SHIFT,\n+\t\t\tPCIE_EXT_CFG_INDEX_REG);\n+}\n+\n+static struct clk *pcie_clk;\n+\n+static int __init bcm63xx_register_pcie(void)\n+{\n+\tu32 val;\n+\n+\t/* enable clock */\n+\tpcie_clk = clk_get(NULL, \"pcie\");\n+\tif (IS_ERR_OR_NULL(pcie_clk))\n+\t\treturn -ENODEV;\n+\n+\tclk_prepare_enable(pcie_clk);\n+\n+\tif (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_63268()) {\n+\t\tbcm63xx_reset_pcie_gen1();\n+\t\tbcm63xx_init_pcie_gen1();\n+\t} else {\n+\t\tbcm63xx_reset_pcie_gen2();\n+\t\tbcm63xx_init_pcie_gen2();\n+\t}\n+\n \t/* setup class code as bridge */\n \tval = bcm_pcie_readl(PCIE_IDVAL3_REG);\n \tval &= ~IDVAL3_CLASS_CODE_MASK;\n@@ -201,15 +272,6 @@ static int __init bcm63xx_register_pcie(\n \tval &= ~CONFIG2_BAR1_SIZE_MASK;\n \tbcm_pcie_writel(val, PCIE_CONFIG2_REG);\n \n-\t/* set bar0 to little endian */\n-\tval = (bcm_pcie_mem_resource.start >> 20) << BASEMASK_BASE_SHIFT;\n-\tval |= (bcm_pcie_mem_resource.end >> 20) << BASEMASK_MASK_SHIFT;\n-\tval |= BASEMASK_REMAP_EN;\n-\tbcm_pcie_writel(val, PCIE_BRIDGE_BAR0_BASEMASK_REG);\n-\n-\tval = (bcm_pcie_mem_resource.start >> 20) << REBASE_ADDR_BASE_SHIFT;\n-\tbcm_pcie_writel(val, PCIE_BRIDGE_BAR0_REBASE_ADDR_REG);\n-\n \tregister_pci_controller(&bcm63xx_pcie_controller);\n \n \treturn 0;\n@@ -341,7 +403,10 @@ static int __init bcm63xx_pci_init(void)\n \tif (!bcm63xx_pci_enabled)\n \t\treturn -ENODEV;\n \n-\tif (BCMCPU_IS_6328() || BCMCPU_IS_6362()) {\n+\tif (BCMCPU_IS_6318()) {\n+\t\tbcm_pcie_mem_resource.start = BCM_PCIE_MEM_BASE_PA_6318;\n+\t\tbcm_pcie_mem_resource.end = BCM_PCIE_MEM_END_PA_6318;\n+\t} if (BCMCPU_IS_6328() || BCMCPU_IS_6362()) {\n \t\tbcm_pcie_mem_resource.start = BCM_PCIE_MEM_BASE_PA_6328;\n \t\tbcm_pcie_mem_resource.end = BCM_PCIE_MEM_END_PA_6328;\n \t} else if (BCMCPU_IS_63268()) {\n@@ -350,6 +415,7 @@ static int __init bcm63xx_pci_init(void)\n \t}\n \n \tswitch (bcm63xx_get_cpu_id()) {\n+\tcase BCM6318_CPU_ID:\n \tcase BCM6328_CPU_ID:\n \tcase BCM6362_CPU_ID:\n \tcase BCM63268_CPU_ID:\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/344-MIPS-BCM63XX-detect-flash-type-early-and-store-the-r.patch",
    "content": "From 9a97177b907330971aa7bf41855fafc2602e1c18 Mon Sep 17 00:00:00 2001\nFrom: Jonas Gorski <jogo@openwrt.org>\nDate: Sun, 22 Dec 2013 12:26:57 +0100\nSubject: [PATCH 51/56] MIPS: BCM63XX: detect flash type early and store the\n result\n\nSigned-off-by: Jonas Gorski <jogo@openwrt.org>\n---\n arch/mips/bcm63xx/dev-flash.c                          | 10 +++++++---\n arch/mips/bcm63xx/prom.c                               |  4 ++++\n arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_flash.h |  2 ++\n 3 files changed, 13 insertions(+), 3 deletions(-)\n\n--- a/arch/mips/bcm63xx/dev-flash.c\n+++ b/arch/mips/bcm63xx/dev-flash.c\n@@ -22,6 +22,8 @@\n #include <bcm63xx_regs.h>\n #include <bcm63xx_io.h>\n \n+static int flash_type;\n+\n static struct mtd_partition mtd_partitions[] = {\n \t{\n \t\t.name\t\t= \"cfe\",\n@@ -109,13 +111,15 @@ static int __init bcm63xx_detect_flash_t\n \t}\n }\n \n+void __init bcm63xx_flash_detect(void)\n+{\n+\tflash_type = bcm63xx_detect_flash_type();\n+}\n+\n int __init bcm63xx_flash_register(void)\n {\n-\tint flash_type;\n \tu32 val;\n \n-\tflash_type = bcm63xx_detect_flash_type();\n-\n \tswitch (flash_type) {\n \tcase BCM63XX_FLASH_TYPE_PARALLEL:\n \t\t/* read base address of boot chip select (0) */\n--- a/arch/mips/bcm63xx/prom.c\n+++ b/arch/mips/bcm63xx/prom.c\n@@ -17,6 +17,7 @@\n #include <bcm63xx_cpu.h>\n #include <bcm63xx_io.h>\n #include <bcm63xx_regs.h>\n+#include <bcm63xx_dev_flash.h>\n \n void __init prom_init(void)\n {\n@@ -52,6 +53,9 @@ void __init prom_init(void)\n \treg &= ~mask;\n \tbcm_perf_writel(reg, PERF_CKCTL_REG);\n \n+\t/* detect and setup flash access */\n+\tbcm63xx_flash_detect();\n+\n \t/* do low level board init */\n \tboard_prom_init();\n \n--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_flash.h\n+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_flash.h\n@@ -8,6 +8,8 @@ enum {\n \tBCM63XX_FLASH_TYPE_NAND,\n };\n \n+void bcm63xx_flash_detect(void);\n+\n int __init bcm63xx_flash_register(void);\n \n #endif /* __BCM63XX_FLASH_H */\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/345-MIPS-BCM63XX-fixup-mapped-SPI-flash-access-on-boot.patch",
    "content": "From 1cacd0f7b0d35f8e3d3f8a69ecb3b5e436d6b9e8 Mon Sep 17 00:00:00 2001\nFrom: Jonas Gorski <jogo@openwrt.org>\nDate: Sun, 22 Dec 2013 13:25:25 +0100\nSubject: [PATCH 52/56] MIPS: BCM63XX: fixup mapped SPI flash access on boot\n\nSome bootloaders leave the flash access in an invalid state with dual\nread enabled; fix it by disabling it and falling back to simple fast\nreads.\n\nSigned-off-by: Jonas Gorski <jogo@openwrt.org>\n---\n arch/mips/bcm63xx/dev-flash.c | 51 ++++++++++++++++++++++++++++++++++++\n 1 file changed, 51 insertions(+)\n\n--- a/arch/mips/bcm63xx/dev-flash.c\n+++ b/arch/mips/bcm63xx/dev-flash.c\n@@ -16,6 +16,7 @@\n #include <linux/mtd/mtd.h>\n #include <linux/mtd/partitions.h>\n #include <linux/mtd/physmap.h>\n+#include <linux/mtd/spi-nor.h>\n \n #include <bcm63xx_cpu.h>\n #include <bcm63xx_dev_flash.h>\n@@ -111,9 +112,59 @@ static int __init bcm63xx_detect_flash_t\n \t}\n }\n \n+#define HSSPI_FLASH_CTRL_REG\t\t0x14\n+#define FLASH_CTRL_READ_OPCODE_MASK\t0xff\n+#define FLASH_CTRL_ADDR_BYTES_MASK\t(0x3 << 8)\n+#define FLASH_CTRL_ADDR_BYTES_2\t\t(0 << 8)\n+#define FLASH_CTRL_ADDR_BYTES_3\t\t(1 << 8)\n+#define FLASH_CTRL_ADDR_BYTES_4\t\t(2 << 8)\n+#define FLASH_CTRL_DUMMY_BYTES_SHIFT\t10\n+#define FLASH_CTRL_DUMMY_BYTES_MASK\t(0x3 << FLASH_CTRL_DUMMY_BYTES_SHIFT)\n+#define FLASH_CTRL_MB_EN\t\t(1 << 23)\n+\n void __init bcm63xx_flash_detect(void)\n {\n \tflash_type = bcm63xx_detect_flash_type();\n+\n+\t/* ensure flash mapping has sane values */\n+\tif (flash_type == BCM63XX_FLASH_TYPE_SERIAL &&\n+\t    (BCMCPU_IS_6318() || BCMCPU_IS_6328() || BCMCPU_IS_6362() ||\n+\t     BCMCPU_IS_63268())) {\n+\t\tu32 val = bcm_rset_readl(RSET_HSSPI, HSSPI_FLASH_CTRL_REG);\n+\n+\t\tif (val & FLASH_CTRL_MB_EN) {\n+\t\t\t/* cfe might configure non working dual-io mode */\n+\t\t\tval &= ~FLASH_CTRL_MB_EN;\n+\t\t\tval &= ~FLASH_CTRL_READ_OPCODE_MASK;\n+\t\t\tval &= ~FLASH_CTRL_DUMMY_BYTES_MASK;\n+\t\t\tval |= 1 << FLASH_CTRL_DUMMY_BYTES_SHIFT;\n+\n+\t\t\tswitch (val & FLASH_CTRL_ADDR_BYTES_MASK) {\n+\t\t\tcase FLASH_CTRL_ADDR_BYTES_3:\n+\t\t\t\tval |= SPINOR_OP_READ_FAST;\n+\t\t\t\tbreak;\n+\t\t\tcase FLASH_CTRL_ADDR_BYTES_4:\n+\t\t\t\tval |= SPINOR_OP_READ_FAST_4B;\n+\t\t\t\tbreak;\n+\t\t\tcase FLASH_CTRL_ADDR_BYTES_2:\n+\t\t\tdefault:\n+\t\t\t\tpr_warn(\"unsupported address byte mode (%x), not fixing up\\n\",\n+\t\t\t\t\tval & FLASH_CTRL_ADDR_BYTES_MASK);\n+\t\t\t\treturn;\n+\t\t\t}\n+\t\t} else {\n+\t\t\t/* ensure dummy bytes is set to 1 for _FAST reads */\n+\t\t\tu8 cmd = val & FLASH_CTRL_READ_OPCODE_MASK;\n+\n+\t\t\tif (cmd != SPINOR_OP_READ_FAST && cmd != SPINOR_OP_READ_FAST_4B)\n+\t\t\t\treturn;\n+\n+\t\t\tval &= ~FLASH_CTRL_DUMMY_BYTES_MASK;\n+\t\t\tval |= 1 << FLASH_CTRL_DUMMY_BYTES_SHIFT;\n+\t\t}\n+\n+\t\tbcm_rset_writel(RSET_HSSPI, val, HSSPI_FLASH_CTRL_REG);\n+\t}\n }\n \n int __init bcm63xx_flash_register(void)\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/346-MIPS-BCM63XX-USB-ENETSW-6318-clocks.patch",
    "content": "--- a/arch/mips/bcm63xx/clk.c\n+++ b/arch/mips/bcm63xx/clk.c\n@@ -168,7 +168,11 @@ static struct clk clk_swpkt_usb = {\n  */\n static void enetsw_set(struct clk *clk, int enable)\n {\n-\tif (BCMCPU_IS_6328()) {\n+\tif (BCMCPU_IS_6318()) {\n+\t\tbcm_hwclock_set(CKCTL_6318_ROBOSW250_EN |\n+\t\t\t\tCKCTL_6318_ROBOSW025_EN, enable);\n+\t\tbcm_ub_hwclock_set(UB_CKCTL_6318_ROBOSW_EN, enable);\n+\t} else if (BCMCPU_IS_6328()) {\n \t\tbcm_hwclock_set(CKCTL_6328_ROBOSW_EN, enable);\n \t} else if (BCMCPU_IS_6362()) {\n \t\tbcm_hwclock_set(CKCTL_6362_ROBOSW_EN, enable);\n@@ -220,18 +224,22 @@ static struct clk clk_pcm = {\n  */\n static void usbh_set(struct clk *clk, int enable)\n {\n-\tif (BCMCPU_IS_6328())\n+\tif (BCMCPU_IS_6318()) {\n+\t\tbcm_hwclock_set(CKCTL_6318_USB_EN, enable);\n+\t\tbcm_ub_hwclock_set(UB_CKCTL_6318_USB_EN, enable);\n+\t} else if (BCMCPU_IS_6328()) {\n \t\tbcm_hwclock_set(CKCTL_6328_USBH_EN, enable);\n-\telse if (BCMCPU_IS_6348())\n+\t} else if (BCMCPU_IS_6348()) {\n \t\tbcm_hwclock_set(CKCTL_6348_USBH_EN, enable);\n-\telse if (BCMCPU_IS_6362())\n+\t} else if (BCMCPU_IS_6362()) {\n \t\tbcm_hwclock_set(CKCTL_6362_USBH_EN, enable);\n-\telse if (BCMCPU_IS_6368())\n+\t} else if (BCMCPU_IS_6368()) {\n \t\tbcm_hwclock_set(CKCTL_6368_USBH_EN, enable);\n-\telse if (BCMCPU_IS_63268())\n+\t} else if (BCMCPU_IS_63268()) {\n \t\tbcm_hwclock_set(CKCTL_63268_USBH_EN, enable);\n-\telse\n+\t} else {\n \t\treturn;\n+\t}\n \n \tif (enable)\n \t\tmsleep(100);\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/347-MIPS-BCM6318-USB-support.patch",
    "content": "--- a/arch/mips/bcm63xx/usb-common.c\n+++ b/arch/mips/bcm63xx/usb-common.c\n@@ -109,6 +109,27 @@ void bcm63xx_usb_priv_ohci_cfg_set(void)\n \t\treg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SETUP_6368_REG);\n \t\treg |= USBH_PRIV_SETUP_IOC_MASK;\n \t\tbcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SETUP_6368_REG);\n+\t} else if (BCMCPU_IS_6318()) {\n+\t\treg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_PLL_CTRL1_6318_REG);\n+\t\treg |= USBH_PRIV_PLL_CTRL1_SUSP_EN;\n+\t\tbcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_PLL_CTRL1_6318_REG);\n+\n+\t\treg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SWAP_6318_REG);\n+\t\treg &= ~USBH_PRIV_SWAP_OHCI_ENDN_MASK;\n+\t\treg |= USBH_PRIV_SWAP_OHCI_DATA_MASK;\n+\t\tbcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SWAP_6318_REG);\n+\n+\t\treg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SETUP_6318_REG);\n+\t\treg |= USBH_PRIV_SETUP_IOC_MASK;\n+\t\tbcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SETUP_6318_REG);\n+\n+\t\treg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_PLL_CTRL1_6318_REG);\n+\t\treg &= ~USBH_PRIV_PLL_CTRL1_IDDQ_PWRDN;\n+\t\tbcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_PLL_CTRL1_6318_REG);\n+\n+\t\treg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SIM_CTRL_6318_REG);\n+\t\treg |= USBH_PRIV_SIM_CTRL_LADDR_SEL;\n+\t\tbcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SIM_CTRL_6318_REG);\n \t}\n \n \tspin_unlock_irqrestore(&usb_priv_reg_lock, flags);\n@@ -144,6 +165,27 @@ void bcm63xx_usb_priv_ehci_cfg_set(void)\n \t\treg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SETUP_6368_REG);\n \t\treg |= USBH_PRIV_SETUP_IOC_MASK;\n \t\tbcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SETUP_6368_REG);\n+\t} else if (BCMCPU_IS_6318()) {\n+\t\treg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_PLL_CTRL1_6318_REG);\n+\t\treg |= USBH_PRIV_PLL_CTRL1_SUSP_EN;\n+\t\tbcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_PLL_CTRL1_6318_REG);\n+\n+\t\treg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SWAP_6318_REG);\n+\t\treg &= ~USBH_PRIV_SWAP_EHCI_ENDN_MASK;\n+\t\treg |= USBH_PRIV_SWAP_EHCI_DATA_MASK;\n+\t\tbcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SWAP_6318_REG);\n+\n+\t\treg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SETUP_6318_REG);\n+\t\treg |= USBH_PRIV_SETUP_IOC_MASK;\n+\t\tbcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SETUP_6318_REG);\n+\n+\t\treg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_PLL_CTRL1_6318_REG);\n+\t\treg &= ~USBH_PRIV_PLL_CTRL1_IDDQ_PWRDN;\n+\t\tbcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_PLL_CTRL1_6318_REG);\n+\n+\t\treg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SIM_CTRL_6318_REG);\n+\t\treg |= USBH_PRIV_SIM_CTRL_LADDR_SEL;\n+\t\tbcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SIM_CTRL_6318_REG);\n \t}\n \n \tspin_unlock_irqrestore(&usb_priv_reg_lock, flags);\n--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h\n+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h\n@@ -682,6 +682,12 @@\n #define GPIO_MODE_6368_SPI_SSN4\t\t(1 << 30)\n #define GPIO_MODE_6368_SPI_SSN5\t\t(1 << 31)\n \n+#define GPIO_PINMUX_SEL0_6318\t\t0x1c\n+#define GPIO_PINMUX_SEL0_GPIO13_SHIFT\t26\n+#define GPIO_PINMUX_SEL0_GPIO13_MASK\t(0x3 << GPIO_PINMUX_SEL0_GPIO13_SHIFT)\n+#define GPIO_PINMUX_SEL0_GPIO13_PWRON\t(1 << GPIO_PINMUX_SEL0_GPIO13_SHIFT)\n+#define GPIO_PINMUX_SEL0_GPIO13_LED\t(2 << GPIO_PINMUX_SEL0_GPIO13_SHIFT)\n+#define GPIO_PINMUX_SEL0_GPIO13_GPIO\t(3 << GPIO_PINMUX_SEL0_GPIO13_SHIFT)\n \n #define GPIO_PINMUX_OTHR_REG\t\t0x24\n #define GPIO_PINMUX_OTHR_6328_USB_SHIFT 12\n@@ -1000,6 +1006,7 @@\n \n #define USBH_PRIV_SWAP_6358_REG\t\t0x0\n #define USBH_PRIV_SWAP_6368_REG\t\t0x1c\n+#define USBH_PRIV_SWAP_6318_REG\t\t0x0c\n \n #define USBH_PRIV_SWAP_USBD_SHIFT\t6\n #define USBH_PRIV_SWAP_USBD_MASK\t(1 << USBH_PRIV_SWAP_USBD_SHIFT)\n@@ -1025,6 +1032,13 @@\n #define USBH_PRIV_SETUP_IOC_SHIFT\t4\n #define USBH_PRIV_SETUP_IOC_MASK\t(1 << USBH_PRIV_SETUP_IOC_SHIFT)\n \n+#define USBH_PRIV_SETUP_6318_REG\t0x00\n+#define USBH_PRIV_PLL_CTRL1_6318_REG\t0x04\n+#define USBH_PRIV_PLL_CTRL1_SUSP_EN\t(1 << 27)\n+#define USBH_PRIV_PLL_CTRL1_IDDQ_PWRDN\t(1 << 31)\n+#define USBH_PRIV_SIM_CTRL_6318_REG\t0x20\n+#define USBH_PRIV_SIM_CTRL_LADDR_SEL\t(1 << 5)\n+\n \n /*************************************************************************\n  * _REG relative to RSET_USBD\n--- a/arch/mips/bcm63xx/boards/board_common.c\n+++ b/arch/mips/bcm63xx/boards/board_common.c\n@@ -125,6 +125,15 @@ void __init board_early_setup(const stru\n \t}\n \n \tbcm_gpio_writel(val, GPIO_MODE_REG);\n+\n+#if IS_ENABLED(CONFIG_USB)\n+\tif (BCMCPU_IS_6318() && (board.has_ehci0 || board.has_ohci0)) {\n+\t\tval = bcm_gpio_readl(GPIO_PINMUX_SEL0_6318);\n+\t\tval &= ~GPIO_PINMUX_SEL0_GPIO13_MASK;\n+\t\tval |= GPIO_PINMUX_SEL0_GPIO13_PWRON;\n+\t\tbcm_gpio_writel(val, GPIO_PINMUX_SEL0_6318);\n+\t}\n+#endif\n }\n \n \n--- a/arch/mips/bcm63xx/Kconfig\n+++ b/arch/mips/bcm63xx/Kconfig\n@@ -23,6 +23,8 @@ config BCM63XX_CPU_6318\n \tbool \"support 6318 CPU\"\n \tselect SYS_HAS_CPU_BMIPS32_3300\n \tselect HAVE_PCI\n+\tselect BCM63XX_OHCI\n+\tselect BCM63XX_EHCI\n \n config BCM63XX_CPU_6328\n \tbool \"support 6328 CPU\"\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/348-MIPS-BCM63XX-fix-BCM63268-USB-clock.patch",
    "content": "--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h\n+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h\n@@ -587,6 +587,9 @@\n #define TIMER_CTL_MONOTONIC_MASK\t(1 << 30)\n #define TIMER_CTL_ENABLE_MASK\t\t(1 << 31)\n \n+/* Clock reset control (63268 only) */\n+#define TIMER_CLK_RST_CTL_REG\t\t0x2c\n+#define CLK_RST_CTL_USB_REF_CLK_EN\t(1 << 18)\n \n /*************************************************************************\n  * _REG relative to RSET_WDT\n@@ -1534,6 +1537,11 @@\n #define STRAPBUS_63268_FCVO_SHIFT\t21\n #define STRAPBUS_63268_FCVO_MASK\t(0xf << STRAPBUS_63268_FCVO_SHIFT)\n \n+#define MISC_IDDQ_CTRL_6328_REG\t\t0x48\n+#define MISC_IDDQ_CTRL_63268_REG\t0x4c\n+\n+#define IDDQ_CTRL_63268_USBH\t\t(1 << 4)\n+\n #define MISC_STRAPBUS_6328_REG\t\t0x240\n #define STRAPBUS_6328_FCVO_SHIFT\t7\n #define STRAPBUS_6328_FCVO_MASK\t\t(0x1f << STRAPBUS_6328_FCVO_SHIFT)\n--- a/arch/mips/bcm63xx/clk.c\n+++ b/arch/mips/bcm63xx/clk.c\n@@ -64,6 +64,26 @@ static void bcm_ub_hwclock_set(u32 mask,\n \tbcm_perf_writel(reg, PERF_UB_CKCTL_REG);\n }\n \n+static void bcm_misc_iddq_set(u32 mask, int enable)\n+{\n+\tu32 offset;\n+\tu32 reg;\n+\n+\tif (BCMCPU_IS_6328() || BCMCPU_IS_6362())\n+\t\toffset = MISC_IDDQ_CTRL_6328_REG;\n+\telse if (BCMCPU_IS_63268())\n+\t\toffset = MISC_IDDQ_CTRL_63268_REG;\n+\telse\n+\t\treturn;\n+\n+\treg = bcm_misc_readl(offset);\n+\tif (enable)\n+\t\treg &= ~mask;\n+\telse\n+\t\treg |= mask;\n+\tbcm_misc_writel(reg, offset);\n+}\n+\n /*\n  * Ethernet MAC \"misc\" clock: dma clocks and main clock on 6348\n  */\n@@ -236,7 +256,17 @@ static void usbh_set(struct clk *clk, in\n \t} else if (BCMCPU_IS_6368()) {\n \t\tbcm_hwclock_set(CKCTL_6368_USBH_EN, enable);\n \t} else if (BCMCPU_IS_63268()) {\n+\t\tu32 reg;\n+\n \t\tbcm_hwclock_set(CKCTL_63268_USBH_EN, enable);\n+\t\tbcm_misc_iddq_set(IDDQ_CTRL_63268_USBH, enable);\n+\t\tbcm63xx_core_set_reset(BCM63XX_RESET_USBH, !enable);\n+\t\treg = bcm_timer_readl(TIMER_CLK_RST_CTL_REG);\n+\t\tif (enable)\n+\t\t\treg |= CLK_RST_CTL_USB_REF_CLK_EN;\n+\t\telse\n+\t\t\treg &= ~CLK_RST_CTL_USB_REF_CLK_EN;\n+\t\tbcm_timer_writel(reg, TIMER_CLK_RST_CTL_REG);\n \t} else {\n \t\treturn;\n \t}\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/349-MIPS-BCM63XX-add-BCM63268-USB-support.patch",
    "content": "--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h\n+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h\n@@ -1034,11 +1034,18 @@\n #define USBH_PRIV_SETUP_6368_REG\t0x28\n #define USBH_PRIV_SETUP_IOC_SHIFT\t4\n #define USBH_PRIV_SETUP_IOC_MASK\t(1 << USBH_PRIV_SETUP_IOC_SHIFT)\n+#define USBH_PRIV_SETUP_IPP_SHIFT\t5\n+#define USBH_PRIV_SETUP_IPP_MASK\t(1 << USBH_PRIV_SETUP_IPP_SHIFT)\n \n #define USBH_PRIV_SETUP_6318_REG\t0x00\n+#define USBH_PRIV_PLL_CTRL1_6368_REG\t0x18\n #define USBH_PRIV_PLL_CTRL1_6318_REG\t0x04\n-#define USBH_PRIV_PLL_CTRL1_SUSP_EN\t(1 << 27)\n-#define USBH_PRIV_PLL_CTRL1_IDDQ_PWRDN\t(1 << 31)\n+\n+#define USBH_PRIV_PLL_CTRL1_6318_SUSP_EN\t(1 << 27)\n+#define USBH_PRIV_PLL_CTRL1_6318_IDDQ_PWRDN\t(1 << 31)\n+#define USBH_PRIV_PLL_CTRL1_63268_IDDQ_PWRDN\t(1 << 9)\n+#define USBH_PRIV_PLL_CTRL1_63268_PWRDN_DELAY\t(1 << 10)\n+\n #define USBH_PRIV_SIM_CTRL_6318_REG\t0x20\n #define USBH_PRIV_SIM_CTRL_LADDR_SEL\t(1 << 5)\n \n--- a/arch/mips/bcm63xx/Kconfig\n+++ b/arch/mips/bcm63xx/Kconfig\n@@ -73,6 +73,8 @@ config BCM63XX_CPU_63268\n \tbool \"support 63268 CPU\"\n \tselect SYS_HAS_CPU_BMIPS4350\n \tselect HAVE_PCI\n+\tselect BCM63XX_OHCI\n+\tselect BCM63XX_EHCI\n endmenu\n \n source \"arch/mips/bcm63xx/boards/Kconfig\"\n--- a/arch/mips/bcm63xx/dev-usb-ehci.c\n+++ b/arch/mips/bcm63xx/dev-usb-ehci.c\n@@ -82,7 +82,7 @@ static struct platform_device bcm63xx_eh\n int __init bcm63xx_ehci_register(void)\n {\n \tif (!BCMCPU_IS_6318() && !BCMCPU_IS_6328() && !BCMCPU_IS_6358() &&\n-\t\t!BCMCPU_IS_6362() && !BCMCPU_IS_6368())\n+\t\t!BCMCPU_IS_6362() && !BCMCPU_IS_6368() && !BCMCPU_IS_63268())\n \t\treturn 0;\n \n \tehci_resources[0].start = bcm63xx_regset_address(RSET_EHCI0);\n--- a/arch/mips/bcm63xx/usb-common.c\n+++ b/arch/mips/bcm63xx/usb-common.c\n@@ -109,9 +109,24 @@ void bcm63xx_usb_priv_ohci_cfg_set(void)\n \t\treg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SETUP_6368_REG);\n \t\treg |= USBH_PRIV_SETUP_IOC_MASK;\n \t\tbcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SETUP_6368_REG);\n+\t} else if (BCMCPU_IS_63268()) {\n+\t\treg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SWAP_6368_REG);\n+\t\treg &= ~USBH_PRIV_SWAP_OHCI_ENDN_MASK;\n+\t\treg |= USBH_PRIV_SWAP_OHCI_DATA_MASK;\n+\t\tbcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SWAP_6368_REG);\n+\n+\t\treg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SETUP_6368_REG);\n+\t\treg |= USBH_PRIV_SETUP_IOC_MASK;\n+\t\treg &= ~USBH_PRIV_SETUP_IPP_MASK;\n+\t\tbcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SETUP_6368_REG);\n+\n+\t\treg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_PLL_CTRL1_6368_REG);\n+\t\treg &= ~(USBH_PRIV_PLL_CTRL1_63268_IDDQ_PWRDN |\n+\t\t\t USBH_PRIV_PLL_CTRL1_63268_PWRDN_DELAY);\n+\t\tbcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_PLL_CTRL1_6368_REG);\n \t} else if (BCMCPU_IS_6318()) {\n \t\treg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_PLL_CTRL1_6318_REG);\n-\t\treg |= USBH_PRIV_PLL_CTRL1_SUSP_EN;\n+\t\treg |= USBH_PRIV_PLL_CTRL1_6318_SUSP_EN;\n \t\tbcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_PLL_CTRL1_6318_REG);\n \n \t\treg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SWAP_6318_REG);\n@@ -124,7 +139,7 @@ void bcm63xx_usb_priv_ohci_cfg_set(void)\n \t\tbcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SETUP_6318_REG);\n \n \t\treg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_PLL_CTRL1_6318_REG);\n-\t\treg &= ~USBH_PRIV_PLL_CTRL1_IDDQ_PWRDN;\n+\t\treg &= ~USBH_PRIV_PLL_CTRL1_6318_IDDQ_PWRDN;\n \t\tbcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_PLL_CTRL1_6318_REG);\n \n \t\treg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SIM_CTRL_6318_REG);\n@@ -165,9 +180,24 @@ void bcm63xx_usb_priv_ehci_cfg_set(void)\n \t\treg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SETUP_6368_REG);\n \t\treg |= USBH_PRIV_SETUP_IOC_MASK;\n \t\tbcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SETUP_6368_REG);\n+\t} else if (BCMCPU_IS_63268()) {\n+\t\treg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SWAP_6368_REG);\n+\t\treg &= ~USBH_PRIV_SWAP_EHCI_ENDN_MASK;\n+\t\treg |= USBH_PRIV_SWAP_EHCI_DATA_MASK;\n+\t\tbcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SWAP_6368_REG);\n+\n+\t\treg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SETUP_6368_REG);\n+\t\treg |= USBH_PRIV_SETUP_IOC_MASK;\n+\t\treg &= ~USBH_PRIV_SETUP_IPP_MASK;\n+\t\tbcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SETUP_6368_REG);\n+\n+\t\treg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_PLL_CTRL1_6368_REG);\n+\t\treg &= ~(USBH_PRIV_PLL_CTRL1_63268_IDDQ_PWRDN |\n+\t\t\t USBH_PRIV_PLL_CTRL1_63268_PWRDN_DELAY);\n+\t\tbcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_PLL_CTRL1_6368_REG);\n \t} else if (BCMCPU_IS_6318()) {\n \t\treg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_PLL_CTRL1_6318_REG);\n-\t\treg |= USBH_PRIV_PLL_CTRL1_SUSP_EN;\n+\t\treg |= USBH_PRIV_PLL_CTRL1_6318_SUSP_EN;\n \t\tbcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_PLL_CTRL1_6318_REG);\n \n \t\treg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SWAP_6318_REG);\n@@ -180,7 +210,7 @@ void bcm63xx_usb_priv_ehci_cfg_set(void)\n \t\tbcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SETUP_6318_REG);\n \n \t\treg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_PLL_CTRL1_6318_REG);\n-\t\treg &= ~USBH_PRIV_PLL_CTRL1_IDDQ_PWRDN;\n+\t\treg &= ~USBH_PRIV_PLL_CTRL1_6318_IDDQ_PWRDN;\n \t\tbcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_PLL_CTRL1_6318_REG);\n \n \t\treg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SIM_CTRL_6318_REG);\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/350-MIPS-BCM63XX-support-settings-num-usbh-ports.patch",
    "content": "--- a/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h\n+++ b/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h\n@@ -40,6 +40,7 @@ struct board_info {\n \n \t/* USB config */\n \tstruct bcm63xx_usbd_platform_data usbd;\n+\tunsigned int num_usbh_ports:2;\n \n \t/* GPIO LEDs */\n \tstruct gpio_led leds[5];\n--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_usb_ehci.h\n+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_usb_ehci.h\n@@ -1,6 +1,6 @@\n #ifndef BCM63XX_DEV_USB_EHCI_H_\n #define BCM63XX_DEV_USB_EHCI_H_\n \n-int bcm63xx_ehci_register(void);\n+int bcm63xx_ehci_register(unsigned int num_ports);\n \n #endif /* BCM63XX_DEV_USB_EHCI_H_ */\n--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_usb_ohci.h\n+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_usb_ohci.h\n@@ -1,6 +1,6 @@\n #ifndef BCM63XX_DEV_USB_OHCI_H_\n #define BCM63XX_DEV_USB_OHCI_H_\n \n-int bcm63xx_ohci_register(void);\n+int bcm63xx_ohci_register(unsigned int num_ports);\n \n #endif /* BCM63XX_DEV_USB_OHCI_H_ */\n--- a/arch/mips/bcm63xx/boards/board_common.c\n+++ b/arch/mips/bcm63xx/boards/board_common.c\n@@ -165,6 +165,8 @@ static struct platform_device bcm63xx_gp\n  */\n int __init board_register_devices(void)\n {\n+\tint usbh_ports = 0;\n+\n \tif (board.has_uart0)\n \t\tbcm63xx_uart_register(0);\n \n@@ -186,14 +188,21 @@ int __init board_register_devices(void)\n \t    !board_get_mac_address(board.enetsw.mac_addr))\n \t\tbcm63xx_enetsw_register(&board.enetsw);\n \n+\tif ((board.has_ohci0 || board.has_ehci0)) {\n+\t\tusbh_ports = board.num_usbh_ports;\n+\n+\t\tif (!usbh_ports || WARN_ON(usbh_ports > 1 && board.has_usbd))\n+\t\t\tusbh_ports = 1;\n+\t}\n+\n \tif (board.has_usbd)\n \t\tbcm63xx_usbd_register(&board.usbd);\n \n \tif (board.has_ehci0)\n-\t\tbcm63xx_ehci_register();\n+\t\tbcm63xx_ehci_register(usbh_ports);\n \n \tif (board.has_ohci0)\n-\t\tbcm63xx_ohci_register();\n+\t\tbcm63xx_ohci_register(usbh_ports);\n \n \t/* Generate MAC address for WLAN and register our SPROM,\n \t * do this after registering enet devices\n--- a/arch/mips/bcm63xx/dev-usb-ehci.c\n+++ b/arch/mips/bcm63xx/dev-usb-ehci.c\n@@ -79,12 +79,14 @@ static struct platform_device bcm63xx_eh\n \t},\n };\n \n-int __init bcm63xx_ehci_register(void)\n+int __init bcm63xx_ehci_register(unsigned int num_ports)\n {\n \tif (!BCMCPU_IS_6318() && !BCMCPU_IS_6328() && !BCMCPU_IS_6358() &&\n \t\t!BCMCPU_IS_6362() && !BCMCPU_IS_6368() && !BCMCPU_IS_63268())\n \t\treturn 0;\n \n+\tbcm63xx_ehci_pdata.num_ports = num_ports;\t\n+\n \tehci_resources[0].start = bcm63xx_regset_address(RSET_EHCI0);\n \tehci_resources[0].end = ehci_resources[0].start;\n \tehci_resources[0].end += RSET_EHCI_SIZE - 1;\n--- a/arch/mips/bcm63xx/dev-usb-ohci.c\n+++ b/arch/mips/bcm63xx/dev-usb-ohci.c\n@@ -62,7 +62,6 @@ static struct usb_ohci_pdata bcm63xx_ohc\n \t.big_endian_desc\t= 1,\n \t.big_endian_mmio\t= 1,\n \t.no_big_frame_no\t= 1,\n-\t.num_ports\t\t= 1,\n \t.power_on\t\t= bcm63xx_ohci_power_on,\n \t.power_off\t\t= bcm63xx_ohci_power_off,\n \t.power_suspend\t\t= bcm63xx_ohci_power_off,\n@@ -80,11 +79,13 @@ static struct platform_device bcm63xx_oh\n \t},\n };\n \n-int __init bcm63xx_ohci_register(void)\n+int __init bcm63xx_ohci_register(unsigned int num_ports)\n {\n \tif (BCMCPU_IS_6345() || BCMCPU_IS_6338())\n \t\treturn -ENODEV;\n \n+\tbcm63xx_ohci_pdata.num_ports = num_ports;\n+\n \tohci_resources[0].start = bcm63xx_regset_address(RSET_OHCI0);\n \tohci_resources[0].end = ohci_resources[0].start;\n \tohci_resources[0].end += RSET_OHCI_SIZE - 1;\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/351-set-board-usbh-ports.patch",
    "content": "--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c\n+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c\n@@ -547,6 +547,7 @@ static struct board_info __initdata boar\n \n \t.has_ehci0 = 1,\n \t.has_ohci0 = 1,\n+\t.num_usbh_ports = 2,\n \t.has_pccard = 1,\n \t.has_pci = 1,\n \t.has_uart0 = 1,\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/354-MIPS-BCM63XX-allow-building-support-for-more-than-on.patch",
    "content": "From 0daf361ea799fba0af5a232036d0f06cea85ad24 Mon Sep 17 00:00:00 2001\nFrom: Jonas Gorski <jogo@openwrt.org>\nDate: Sat, 21 Jun 2014 12:47:49 +0200\nSubject: [PATCH 42/44] MIPS: BCM63XX: allow building support for more than one\n board type\n\nUse the arguments passed to the kernel to detect being booted with\nCFE as the indicator for bcm963xx board support, allowing the\nnon presence of CFE_EPTSEAL to assume a different board type.\n\nSigned-off-by: Jonas Gorski <jogo@openwrt.org>\n---\n arch/mips/bcm63xx/boards/Kconfig          |  7 +++----\n arch/mips/bcm63xx/boards/board_bcm963xx.c |  2 +-\n arch/mips/bcm63xx/boards/board_common.c   | 13 +++++++++++++\n arch/mips/bcm63xx/boards/board_common.h   |  6 ++++++\n 4 files changed, 23 insertions(+), 5 deletions(-)\n\n--- a/arch/mips/bcm63xx/boards/Kconfig\n+++ b/arch/mips/bcm63xx/boards/Kconfig\n@@ -1,11 +1,10 @@\n # SPDX-License-Identifier: GPL-2.0\n-choice\n-\tprompt \"Board support\"\n+menu \"Board support\"\n \tdepends on BCM63XX\n-\tdefault BOARD_BCM963XX\n \n config BOARD_BCM963XX\n \tbool \"Generic Broadcom 963xx boards\"\n \tselect SSB\n+\tdefault y\n \n-endchoice\n+endmenu\n--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c\n+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c\n@@ -670,7 +670,7 @@ static const struct board_info __initcon\n /*\n  * early init callback, read nvram data from flash and checksum it\n  */\n-void __init board_prom_init(void)\n+void __init board_bcm963xx_init(void)\n {\n \tunsigned int i;\n \tu8 *boot_addr, *cfe;\n--- a/arch/mips/bcm63xx/boards/board_common.c\n+++ b/arch/mips/bcm63xx/boards/board_common.c\n@@ -13,6 +13,8 @@\n #include <linux/platform_device.h>\n #include <linux/ssb/ssb.h>\n #include <asm/addrspace.h>\n+#include <asm/bootinfo.h>\n+#include <asm/fw/cfe/cfe_api.h>\n #include <bcm63xx_board.h>\n #include <bcm63xx_cpu.h>\n #include <bcm63xx_dev_uart.h>\n@@ -30,6 +32,8 @@\n #include <bcm63xx_dev_usb_usbd.h>\n #include <board_bcm963xx.h>\n \n+#include \"board_common.h\"\n+\n #define PFX\t\"board: \"\n \n static struct board_info board;\n@@ -80,6 +84,15 @@ const char *board_get_name(void)\n \treturn board.name;\n }\n \n+void __init board_prom_init(void)\n+{\n+\t/* detect bootloader */\n+\tif (fw_arg3 == CFE_EPTSEAL)\n+\t\tboard_bcm963xx_init();\n+\telse\n+\t\tpanic(\"unsupported bootloader detected\");\n+}\n+\n static int (*board_get_mac_address)(u8 mac[ETH_ALEN]);\n \n /*\n--- a/arch/mips/bcm63xx/boards/board_common.h\n+++ b/arch/mips/bcm63xx/boards/board_common.h\n@@ -6,4 +6,10 @@\n void board_early_setup(const struct board_info *board,\n \t\t       int (*get_mac_address)(u8 mac[ETH_ALEN]));\n \n+#if defined(CONFIG_BOARD_BCM963XX)\n+void board_bcm963xx_init(void);\n+#else\n+static inline void board_bcm963xx_init(void) { }\n+#endif\n+\n #endif /* __BOARD_COMMON_H */\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/355-MIPS-BCM63XX-allow-board-implementations-to-force-fl.patch",
    "content": "From 8a30097a899b975709f728666d5ad20c8b832d21 Mon Sep 17 00:00:00 2001\nFrom: Jonas Gorski <jogo@openwrt.org>\nDate: Sun, 9 Mar 2014 04:28:14 +0100\nSubject: [PATCH 43/44] MIPS: BCM63XX: allow board implementations to force\n flash address\n\nAllow board implementations to force the physmap address.\n\nSigned-off-by: Jonas Gorski <jogo@openwrt.org>\n---\n arch/mips/bcm63xx/dev-flash.c                         | 19 ++++++++++++++-----\n .../mips/include/asm/mach-bcm63xx/bcm63xx_dev_flash.h |  2 ++\n 2 files changed, 16 insertions(+), 5 deletions(-)\n\n--- a/arch/mips/bcm63xx/dev-flash.c\n+++ b/arch/mips/bcm63xx/dev-flash.c\n@@ -58,6 +58,12 @@ static struct platform_device mtd_dev =\n \t},\n };\n \n+void __init bcm63xx_flash_force_phys_base_address(u32 start, u32 end)\n+{\n+\tmtd_resources[0].start = start;\n+\tmtd_resources[0].end = end;\n+}\n+\n static int __init bcm63xx_detect_flash_type(void)\n {\n \tu32 val;\n@@ -173,12 +179,15 @@ int __init bcm63xx_flash_register(void)\n \n \tswitch (flash_type) {\n \tcase BCM63XX_FLASH_TYPE_PARALLEL:\n-\t\t/* read base address of boot chip select (0) */\n-\t\tval = bcm_mpi_readl(MPI_CSBASE_REG(0));\n-\t\tval &= MPI_CSBASE_BASE_MASK;\n \n-\t\tmtd_resources[0].start = val;\n-\t\tmtd_resources[0].end = 0x1FFFFFFF;\n+\t\tif (!mtd_resources[0].start) {\n+\t\t\t/* read base address of boot chip select (0) */\n+\t\t\tval = bcm_mpi_readl(MPI_CSBASE_REG(0));\n+\t\t\tval &= MPI_CSBASE_BASE_MASK;\n+\n+\t\t\tmtd_resources[0].start = val;\n+\t\t\tmtd_resources[0].end = 0x1FFFFFFF;\n+\t\t}\n \n \t\treturn platform_device_register(&mtd_dev);\n \tcase BCM63XX_FLASH_TYPE_SERIAL:\n--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_flash.h\n+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_flash.h\n@@ -10,6 +10,8 @@ enum {\n \n void bcm63xx_flash_detect(void);\n \n+void bcm63xx_flash_force_phys_base_address(u32 start, u32 end);\n+\n int __init bcm63xx_flash_register(void);\n \n #endif /* __BCM63XX_FLASH_H */\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/356-MIPS-BCM63XX-move-fallback-sprom-support-into-its-ow.patch",
    "content": "From cc025e749a1fece61a6cc0d64bbe7b12472259cc Mon Sep 17 00:00:00 2001\nFrom: Jonas Gorski <jogo@openwrt.org>\nDate: Tue, 29 Jul 2014 21:31:12 +0200\nSubject: [PATCH 01/10] MIPS: BCM63XX: move fallback sprom support into its own\n unit\n\nIn preparation for enhancing it, move it into its own file. Require a\nmac address to be passed as the argument to always \"reserve\" the mac\nregardless of the inclusion state of SSB.\n\nSigned-off-by: Jonas Gorski <jogo@openwrt.org>\n---\n arch/mips/bcm63xx/Makefile                         |  2 +-\n arch/mips/bcm63xx/boards/board_common.c            | 53 ++--------------\n arch/mips/bcm63xx/sprom.c                          | 70 ++++++++++++++++++++++\n .../asm/mach-bcm63xx/bcm63xx_fallback_sprom.h      |  6 ++\n 4 files changed, 83 insertions(+), 48 deletions(-)\n create mode 100644 arch/mips/bcm63xx/sprom.c\n create mode 100644 arch/mips/include/asm/mach-bcm63xx/bcm63xx_fallback_sprom.h\n\n--- a/arch/mips/bcm63xx/Makefile\n+++ b/arch/mips/bcm63xx/Makefile\n@@ -2,7 +2,8 @@\n obj-y\t\t+= clk.o cpu.o cs.o gpio.o irq.o nvram.o prom.o reset.o \\\n \t\t   setup.o timer.o dev-enet.o dev-flash.o dev-pcmcia.o \\\n \t\t   dev-rng.o dev-spi.o dev-hsspi.o dev-uart.o dev-wdt.o \\\n-\t\t   dev-usb-ehci.o dev-usb-ohci.o dev-usb-usbd.o usb-common.o\n+\t\t   dev-usb-ehci.o dev-usb-ohci.o dev-usb-usbd.o usb-common.o \\\n+\t\t   sprom.o\n obj-$(CONFIG_EARLY_PRINTK)\t+= early_printk.o\n \n obj-y\t\t+= boards/\n--- a/arch/mips/bcm63xx/boards/board_common.c\n+++ b/arch/mips/bcm63xx/boards/board_common.c\n@@ -39,44 +39,6 @@\n static struct board_info board;\n \n /*\n- * Register a sane SPROMv2 to make the on-board\n- * bcm4318 WLAN work\n- */\n-#ifdef CONFIG_SSB_PCIHOST\n-static struct ssb_sprom bcm63xx_sprom = {\n-\t.revision\t\t= 0x02,\n-\t.board_rev\t\t= 0x17,\n-\t.country_code\t\t= 0x0,\n-\t.ant_available_bg\t= 0x3,\n-\t.pa0b0\t\t\t= 0x15ae,\n-\t.pa0b1\t\t\t= 0xfa85,\n-\t.pa0b2\t\t\t= 0xfe8d,\n-\t.pa1b0\t\t\t= 0xffff,\n-\t.pa1b1\t\t\t= 0xffff,\n-\t.pa1b2\t\t\t= 0xffff,\n-\t.gpio0\t\t\t= 0xff,\n-\t.gpio1\t\t\t= 0xff,\n-\t.gpio2\t\t\t= 0xff,\n-\t.gpio3\t\t\t= 0xff,\n-\t.maxpwr_bg\t\t= 0x004c,\n-\t.itssi_bg\t\t= 0x00,\n-\t.boardflags_lo\t\t= 0x2848,\n-\t.boardflags_hi\t\t= 0x0000,\n-};\n-\n-int bcm63xx_get_fallback_sprom(struct ssb_bus *bus, struct ssb_sprom *out)\n-{\n-\tif (bus->bustype == SSB_BUSTYPE_PCI) {\n-\t\tmemcpy(out, &bcm63xx_sprom, sizeof(struct ssb_sprom));\n-\t\treturn 0;\n-\t} else {\n-\t\tprintk(KERN_ERR PFX \"unable to fill SPROM for given bustype.\\n\");\n-\t\treturn -EINVAL;\n-\t}\n-}\n-#endif\n-\n-/*\n  * return board name for /proc/cpuinfo\n  */\n const char *board_get_name(void)\n@@ -179,6 +141,7 @@ static struct platform_device bcm63xx_gp\n int __init board_register_devices(void)\n {\n \tint usbh_ports = 0;\n+\tu8 mac[ETH_ALEN];\n \n \tif (board.has_uart0)\n \t\tbcm63xx_uart_register(0);\n@@ -220,15 +183,10 @@ int __init board_register_devices(void)\n \t/* Generate MAC address for WLAN and register our SPROM,\n \t * do this after registering enet devices\n \t */\n-#ifdef CONFIG_SSB_PCIHOST\n-\tif (!board_get_mac_address(bcm63xx_sprom.il0mac)) {\n-\t\tmemcpy(bcm63xx_sprom.et0mac, bcm63xx_sprom.il0mac, ETH_ALEN);\n-\t\tmemcpy(bcm63xx_sprom.et1mac, bcm63xx_sprom.il0mac, ETH_ALEN);\n-\t\tif (ssb_arch_register_fallback_sprom(\n-\t\t\t\t&bcm63xx_get_fallback_sprom) < 0)\n-\t\t\tpr_err(PFX \"failed to register fallback SPROM\\n\");\n-\t}\n-#endif\n+\n+\tif (board_get_mac_address(mac) ||\n+\t    bcm63xx_register_fallback_sprom(mac))\n+\t\tpr_err(PFX \"failed to register fallback SPROM\\n\");\n \n \tbcm63xx_spi_register();\n \n--- /dev/null\n+++ b/arch/mips/bcm63xx/sprom.c\n@@ -0,0 +1,70 @@\n+/*\n+ * This file is subject to the terms and conditions of the GNU General Public\n+ * License.  See the file \"COPYING\" in the main directory of this archive\n+ * for more details.\n+ *\n+ * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>\n+ * Copyright (C) 2008 Florian Fainelli <florian@openwrt.org>\n+ */\n+\n+#include <linux/init.h>\n+#include <linux/kernel.h>\n+#include <linux/string.h>\n+#include <linux/platform_device.h>\n+#include <linux/ssb/ssb.h>\n+#include <bcm63xx_fallback_sprom.h>\n+#include <board_bcm963xx.h>\n+\n+#define PFX\t\"sprom: \"\n+\n+/*\n+ * Register a sane SPROMv2 to make the on-board\n+ * bcm4318 WLAN work\n+ */\n+#ifdef CONFIG_SSB_PCIHOST\n+static struct ssb_sprom bcm63xx_sprom = {\n+\t.revision\t\t= 0x02,\n+\t.board_rev\t\t= 0x17,\n+\t.country_code\t\t= 0x0,\n+\t.ant_available_bg\t= 0x3,\n+\t.pa0b0\t\t\t= 0x15ae,\n+\t.pa0b1\t\t\t= 0xfa85,\n+\t.pa0b2\t\t\t= 0xfe8d,\n+\t.pa1b0\t\t\t= 0xffff,\n+\t.pa1b1\t\t\t= 0xffff,\n+\t.pa1b2\t\t\t= 0xffff,\n+\t.gpio0\t\t\t= 0xff,\n+\t.gpio1\t\t\t= 0xff,\n+\t.gpio2\t\t\t= 0xff,\n+\t.gpio3\t\t\t= 0xff,\n+\t.maxpwr_bg\t\t= 0x004c,\n+\t.itssi_bg\t\t= 0x00,\n+\t.boardflags_lo\t\t= 0x2848,\n+\t.boardflags_hi\t\t= 0x0000,\n+};\n+\n+int bcm63xx_get_fallback_sprom(struct ssb_bus *bus, struct ssb_sprom *out)\n+{\n+\tif (bus->bustype == SSB_BUSTYPE_PCI) {\n+\t\tmemcpy(out, &bcm63xx_sprom, sizeof(struct ssb_sprom));\n+\t\treturn 0;\n+\t} else {\n+\t\tprintk(KERN_ERR PFX \"unable to fill SPROM for given bustype.\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+}\n+#endif\n+\n+int __init bcm63xx_register_fallback_sprom(u8 *mac)\n+{\n+\tint ret = 0;\n+\n+#ifdef CONFIG_SSB_PCIHOST\n+\tmemcpy(bcm63xx_sprom.il0mac, mac, ETH_ALEN);\n+\tmemcpy(bcm63xx_sprom.et0mac, mac, ETH_ALEN);\n+\tmemcpy(bcm63xx_sprom.et1mac, mac, ETH_ALEN);\n+\n+\tret = ssb_arch_register_fallback_sprom(&bcm63xx_get_fallback_sprom);\n+#endif\n+\treturn ret;\n+}\n--- /dev/null\n+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_fallback_sprom.h\n@@ -0,0 +1,6 @@\n+#ifndef __BCM63XX_FALLBACK_SPROM\n+#define __BCM63XX_FALLBACK_SPROM\n+\n+int bcm63xx_register_fallback_sprom(u8 *mac);\n+\n+#endif\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/357-MIPS-BCM63XX-use-platform-data-for-the-sprom.patch",
    "content": "From 9912a8b3c240a9b0af01ff496b7e8ed9e4cc5b82 Mon Sep 17 00:00:00 2001\nFrom: Jonas Gorski <jogo@openwrt.org>\nDate: Tue, 29 Jul 2014 21:43:49 +0200\nSubject: [PATCH 02/10] MIPS: BCM63XX: use platform data for the sprom\n\nSimilar to ethernet setup, use a platform data struct for passing\nthe mac. This eliminates the requirement to allocate an array on\nstack for the mac passed.\n\nSigned-off-by: Jonas Gorski <jogo@openwrt.org>\n---\n arch/mips/bcm63xx/boards/board_common.c                     | 6 ++----\n arch/mips/bcm63xx/sprom.c                                   | 8 ++++----\n arch/mips/include/asm/mach-bcm63xx/bcm63xx_fallback_sprom.h | 8 +++++++-\n arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h         | 4 ++++\n 4 files changed, 17 insertions(+), 9 deletions(-)\n\n--- a/arch/mips/bcm63xx/boards/board_common.c\n+++ b/arch/mips/bcm63xx/boards/board_common.c\n@@ -141,7 +141,6 @@ static struct platform_device bcm63xx_gp\n int __init board_register_devices(void)\n {\n \tint usbh_ports = 0;\n-\tu8 mac[ETH_ALEN];\n \n \tif (board.has_uart0)\n \t\tbcm63xx_uart_register(0);\n@@ -184,8 +183,8 @@ int __init board_register_devices(void)\n \t * do this after registering enet devices\n \t */\n \n-\tif (board_get_mac_address(mac) ||\n-\t    bcm63xx_register_fallback_sprom(mac))\n+\tif (board_get_mac_address(board.fallback_sprom.mac_addr) ||\n+\t    bcm63xx_register_fallback_sprom(&board.fallback_sprom))\n \t\tpr_err(PFX \"failed to register fallback SPROM\\n\");\n \n \tbcm63xx_spi_register();\n--- a/arch/mips/bcm63xx/sprom.c\n+++ b/arch/mips/bcm63xx/sprom.c\n@@ -55,14 +55,14 @@ int bcm63xx_get_fallback_sprom(struct ss\n }\n #endif\n \n-int __init bcm63xx_register_fallback_sprom(u8 *mac)\n+int __init bcm63xx_register_fallback_sprom(struct fallback_sprom_data *data)\n {\n \tint ret = 0;\n \n #ifdef CONFIG_SSB_PCIHOST\n-\tmemcpy(bcm63xx_sprom.il0mac, mac, ETH_ALEN);\n-\tmemcpy(bcm63xx_sprom.et0mac, mac, ETH_ALEN);\n-\tmemcpy(bcm63xx_sprom.et1mac, mac, ETH_ALEN);\n+\tmemcpy(bcm63xx_sprom.il0mac, data->mac_addr, ETH_ALEN);\n+\tmemcpy(bcm63xx_sprom.et0mac, data->mac_addr, ETH_ALEN);\n+\tmemcpy(bcm63xx_sprom.et1mac, data->mac_addr, ETH_ALEN);\n \n \tret = ssb_arch_register_fallback_sprom(&bcm63xx_get_fallback_sprom);\n #endif\n--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_fallback_sprom.h\n+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_fallback_sprom.h\n@@ -1,6 +1,12 @@\n #ifndef __BCM63XX_FALLBACK_SPROM\n #define __BCM63XX_FALLBACK_SPROM\n \n-int bcm63xx_register_fallback_sprom(u8 *mac);\n+#include <linux/if_ether.h>\n+\n+struct fallback_sprom_data {\n+\tu8 mac_addr[ETH_ALEN];\n+};\n+\n+int bcm63xx_register_fallback_sprom(struct fallback_sprom_data *data);\n \n #endif\n--- a/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h\n+++ b/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h\n@@ -7,6 +7,7 @@\n #include <linux/leds.h>\n #include <bcm63xx_dev_enet.h>\n #include <bcm63xx_dev_usb_usbd.h>\n+#include <bcm63xx_fallback_sprom.h>\n \n /*\n  * flash mapping\n@@ -50,6 +51,9 @@ struct board_info {\n \n \t/* External PHY reset GPIO flags from gpio.h */\n \tunsigned long ephy_reset_gpio_flags;\n+\n+\t/* fallback sprom config */\n+\tstruct fallback_sprom_data fallback_sprom;\n };\n \n #endif /* ! BOARD_BCM963XX_H_ */\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/358-MIPS-BCM63XX-make-fallback-sprom-optional.patch",
    "content": "From 83131acbfb59760a19f3711c09526e191c8aad54 Mon Sep 17 00:00:00 2001\nFrom: Jonas Gorski <jogo@openwrt.org>\nDate: Tue, 29 Jul 2014 21:52:56 +0200\nSubject: [PATCH 03/10] MIPS: BCM63XX: make fallback sprom optional\n\nSome devices do not provide enough mac addresses to populate wifi in\naddition to ethernet.\n\nUse having pci enabled as a rough heuristic which boards should have it\nenabled.\n\nSigned-off-by: Jonas Gorski <jogo@openwrt.org>\n---\n arch/mips/bcm63xx/boards/board_bcm963xx.c           | 12 ++++++++++++\n arch/mips/bcm63xx/boards/board_common.c             |  5 +++--\n arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h |  1 +\n 3 files changed, 16 insertions(+), 2 deletions(-)\n\n--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c\n+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c\n@@ -63,6 +63,7 @@ static struct board_info __initdata boar\n \n \t.has_pci = 1,\n \t.has_uart0 = 1,\n+\t.use_fallback_sprom = 1,\n \n \t.has_usbd = 0,\n \t.usbd = {\n@@ -213,6 +214,7 @@ static struct board_info __initdata boar\n \n \t.has_pci = 1,\n \t.has_uart0 = 1,\n+\t.use_fallback_sprom = 1,\n \n \t.has_enet0 = 1,\n \t.enet0 = {\n@@ -259,6 +261,7 @@ static struct board_info __initdata boar\n \t.has_pccard = 1,\n \t.has_pci = 1,\n \t.has_uart0 = 1,\n+\t.use_fallback_sprom = 1,\n \n \t.has_enet0 = 1,\n \t.enet0 = {\n@@ -310,6 +313,7 @@ static struct board_info __initdata boar\n \t.has_pccard = 1,\n \t.has_pci = 1,\n \t.has_uart0 = 1,\n+\t.use_fallback_sprom = 1,\n \n \t.has_enet0 = 1,\n \t.enet0 = {\n@@ -360,6 +364,7 @@ static struct board_info __initdata boar\n \t.has_ohci0 = 1,\n \t.has_pci = 1,\n \t.has_uart0 = 1,\n+\t.use_fallback_sprom = 1,\n \n \t.has_enet0 = 1,\n \t.enet0 = {\n@@ -411,6 +416,7 @@ static struct board_info __initdata boar\n \t.has_pccard = 1,\n \t.has_pci = 1,\n \t.has_uart0 = 1,\n+\t.use_fallback_sprom = 1,\n \n \t.has_enet0 = 1,\n \t.enet0 = {\n@@ -430,6 +436,7 @@ static struct board_info __initdata boar\n \t.expected_cpu_id = 0x6348,\n \n \t.has_pci = 1,\n+\t.use_fallback_sprom = 1,\n \n \t.has_enet0 = 1,\n \t.enet0 = {\n@@ -451,6 +458,7 @@ static struct board_info __initdata boar\n \t.has_ohci0 = 1,\n \t.has_pci = 1,\n \t.has_uart0 = 1,\n+\t.use_fallback_sprom = 1,\n \n \t.has_enet0 = 1,\n \t.enet0 = {\n@@ -472,6 +480,7 @@ static struct board_info __initdata boar\n \t.has_ohci0 = 1,\n \t.has_pci = 1,\n \t.has_uart0 = 1,\n+\t.use_fallback_sprom = 1,\n \n \t.has_enet0 = 1,\n \t.enet0 = {\n@@ -500,6 +509,7 @@ static struct board_info __initdata boar\n \t.has_pccard = 1,\n \t.has_pci = 1,\n \t.has_uart0 = 1,\n+\t.use_fallback_sprom = 1,\n \n \t.has_enet0 = 1,\n \t.enet0 = {\n@@ -551,6 +561,7 @@ static struct board_info __initdata boar\n \t.has_pccard = 1,\n \t.has_pci = 1,\n \t.has_uart0 = 1,\n+\t.use_fallback_sprom = 1,\n \n \t.has_enet0 = 1,\n \t.enet0 = {\n@@ -617,6 +628,7 @@ static struct board_info __initdata boar\n \t.has_ehci0 = 1,\n \t.has_ohci0 = 1,\n \t.has_pci = 1,\n+\t.use_fallback_sprom = 1,\n \n \t.has_enet0 = 1,\n \t.enet0 = {\n--- a/arch/mips/bcm63xx/boards/board_common.c\n+++ b/arch/mips/bcm63xx/boards/board_common.c\n@@ -183,8 +183,9 @@ int __init board_register_devices(void)\n \t * do this after registering enet devices\n \t */\n \n-\tif (board_get_mac_address(board.fallback_sprom.mac_addr) ||\n-\t    bcm63xx_register_fallback_sprom(&board.fallback_sprom))\n+\tif (board.use_fallback_sprom &&\n+\t    (board_get_mac_address(board.fallback_sprom.mac_addr) ||\n+\t     bcm63xx_register_fallback_sprom(&board.fallback_sprom)))\n \t\tpr_err(PFX \"failed to register fallback SPROM\\n\");\n \n \tbcm63xx_spi_register();\n--- a/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h\n+++ b/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h\n@@ -33,6 +33,7 @@ struct board_info {\n \tunsigned int\thas_usbd:1;\n \tunsigned int\thas_uart0:1;\n \tunsigned int\thas_uart1:1;\n+\tunsigned int\tuse_fallback_sprom:1;\n \n \t/* ethernet config */\n \tstruct bcm63xx_enet_platform_data enet0;\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/359-MIPS-BCM63XX-allow-different-types-of-sprom.patch",
    "content": "From 1cece9f7aca1f0c193edce201f77a87008c5a405 Mon Sep 17 00:00:00 2001\nFrom: Jonas Gorski <jogo@openwrt.org>\nDate: Tue, 29 Jul 2014 21:58:38 +0200\nSubject: [PATCH 04/10] MIPS: BCM63XX: allow different types of sprom\n\nDifferent chips require different sprom contents, so prepare for\nsupplying the appropriate sprom type.\n\nSigned-off-by: Jonas Gorski <jogo@openwrt.org>\n---\n arch/mips/bcm63xx/sprom.c                                   | 13 ++++++++++++-\n arch/mips/include/asm/mach-bcm63xx/bcm63xx_fallback_sprom.h |  5 +++++\n 2 files changed, 17 insertions(+), 1 deletion(-)\n\n--- a/arch/mips/bcm63xx/sprom.c\n+++ b/arch/mips/bcm63xx/sprom.c\n@@ -22,7 +22,7 @@\n  * bcm4318 WLAN work\n  */\n #ifdef CONFIG_SSB_PCIHOST\n-static struct ssb_sprom bcm63xx_sprom = {\n+static __initconst struct ssb_sprom bcm63xx_default_sprom = {\n \t.revision\t\t= 0x02,\n \t.board_rev\t\t= 0x17,\n \t.country_code\t\t= 0x0,\n@@ -43,6 +43,8 @@ static struct ssb_sprom bcm63xx_sprom =\n \t.boardflags_hi\t\t= 0x0000,\n };\n \n+static struct ssb_sprom bcm63xx_sprom;\n+\n int bcm63xx_get_fallback_sprom(struct ssb_bus *bus, struct ssb_sprom *out)\n {\n \tif (bus->bustype == SSB_BUSTYPE_PCI) {\n@@ -60,6 +62,15 @@ int __init bcm63xx_register_fallback_spr\n \tint ret = 0;\n \n #ifdef CONFIG_SSB_PCIHOST\n+\tswitch (data->type) {\n+\tcase SPROM_DEFAULT:\n+\t\tmemcpy(&bcm63xx_sprom, &bcm63xx_default_sprom,\n+\t\t       sizeof(bcm63xx_sprom));\n+\t\tbreak;\n+\tdefault:\n+\t\treturn -EINVAL;\n+\t}\n+\n \tmemcpy(bcm63xx_sprom.il0mac, data->mac_addr, ETH_ALEN);\n \tmemcpy(bcm63xx_sprom.et0mac, data->mac_addr, ETH_ALEN);\n \tmemcpy(bcm63xx_sprom.et1mac, data->mac_addr, ETH_ALEN);\n--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_fallback_sprom.h\n+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_fallback_sprom.h\n@@ -3,8 +3,13 @@\n \n #include <linux/if_ether.h>\n \n+enum sprom_type {\n+\tSPROM_DEFAULT, /* default fallback sprom */\n+};\n+\n struct fallback_sprom_data {\n \tu8 mac_addr[ETH_ALEN];\n+\tenum sprom_type type;\n };\n \n int bcm63xx_register_fallback_sprom(struct fallback_sprom_data *data);\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/360-MIPS-BCM63XX-add-support-for-raw-sproms.patch",
    "content": "From cedee63bc73f8b7d45b8c0cba1236986812c1f83 Mon Sep 17 00:00:00 2001\nFrom: Jonas Gorski <jogo@openwrt.org>\nDate: Tue, 29 Jul 2014 22:16:36 +0200\nSubject: [PATCH 05/10] MIPS: BCM63XX: add support for \"raw\" sproms\n\nAllow using raw sprom content as templates.\n\nSigned-off-by: Jonas Gorski <jogo@openwrt.org>\n---\n arch/mips/bcm63xx/sprom.c | 482 ++++++++++++++++++++++++++++++++++++++++++++++\n 1 file changed, 482 insertions(+)\n\n--- a/arch/mips/bcm63xx/sprom.c\n+++ b/arch/mips/bcm63xx/sprom.c\n@@ -55,13 +55,556 @@ int bcm63xx_get_fallback_sprom(struct ss\n \t\treturn -EINVAL;\n \t}\n }\n+\n+/* FIXME: use lib_sprom after submission upstream */\n+\n+/* Get the word-offset for a SSB_SPROM_XXX define. */\n+#define SPOFF(offset)\t((offset) / sizeof(u16))\n+/* Helper to extract some _offset, which is one of the SSB_SPROM_XXX defines. */\n+#define SPEX16(_outvar, _offset, _mask, _shift)\t\\\n+\tout->_outvar = ((in[SPOFF(_offset)] & (_mask)) >> (_shift))\n+#define SPEX32(_outvar, _offset, _mask, _shift)\t\\\n+\tout->_outvar = ((((u32)in[SPOFF((_offset)+2)] << 16 | \\\n+\t\t\t   in[SPOFF(_offset)]) & (_mask)) >> (_shift))\n+#define SPEX(_outvar, _offset, _mask, _shift) \\\n+\tSPEX16(_outvar, _offset, _mask, _shift)\n+\n+#define SPEX_ARRAY8(_field, _offset, _mask, _shift)\t\\\n+\tdo {\t\\\n+\t\tSPEX(_field[0], _offset +  0, _mask, _shift);\t\\\n+\t\tSPEX(_field[1], _offset +  2, _mask, _shift);\t\\\n+\t\tSPEX(_field[2], _offset +  4, _mask, _shift);\t\\\n+\t\tSPEX(_field[3], _offset +  6, _mask, _shift);\t\\\n+\t\tSPEX(_field[4], _offset +  8, _mask, _shift);\t\\\n+\t\tSPEX(_field[5], _offset + 10, _mask, _shift);\t\\\n+\t\tSPEX(_field[6], _offset + 12, _mask, _shift);\t\\\n+\t\tSPEX(_field[7], _offset + 14, _mask, _shift);\t\\\n+\t} while (0)\n+\n+\n+static s8 sprom_extract_antgain(u8 sprom_revision, const u16 *in, u16 offset,\n+\t\t\t\tu16 mask, u16 shift)\n+{\n+\tu16 v;\n+\tu8 gain;\n+\n+\tv = in[SPOFF(offset)];\n+\tgain = (v & mask) >> shift;\n+\tif (gain == 0xFF)\n+\t\tgain = 2; /* If unset use 2dBm */\n+\tif (sprom_revision == 1) {\n+\t\t/* Convert to Q5.2 */\n+\t\tgain <<= 2;\n+\t} else {\n+\t\t/* Q5.2 Fractional part is stored in 0xC0 */\n+\t\tgain = ((gain & 0xC0) >> 6) | ((gain & 0x3F) << 2);\n+\t}\n+\n+\treturn (s8)gain;\n+}\n+\n+static void sprom_extract_r23(struct ssb_sprom *out, const u16 *in)\n+{\n+\tSPEX(boardflags_hi, SSB_SPROM2_BFLHI, 0xFFFF, 0);\n+\tSPEX(opo, SSB_SPROM2_OPO, SSB_SPROM2_OPO_VALUE, 0);\n+\tSPEX(pa1lob0, SSB_SPROM2_PA1LOB0, 0xFFFF, 0);\n+\tSPEX(pa1lob1, SSB_SPROM2_PA1LOB1, 0xFFFF, 0);\n+\tSPEX(pa1lob2, SSB_SPROM2_PA1LOB2, 0xFFFF, 0);\n+\tSPEX(pa1hib0, SSB_SPROM2_PA1HIB0, 0xFFFF, 0);\n+\tSPEX(pa1hib1, SSB_SPROM2_PA1HIB1, 0xFFFF, 0);\n+\tSPEX(pa1hib2, SSB_SPROM2_PA1HIB2, 0xFFFF, 0);\n+\tSPEX(maxpwr_ah, SSB_SPROM2_MAXP_A, SSB_SPROM2_MAXP_A_HI, 0);\n+\tSPEX(maxpwr_al, SSB_SPROM2_MAXP_A, SSB_SPROM2_MAXP_A_LO,\n+\t     SSB_SPROM2_MAXP_A_LO_SHIFT);\n+}\n+\n+static void sprom_extract_r123(struct ssb_sprom *out, const u16 *in)\n+{\n+\tu16 loc[3];\n+\n+\tif (out->revision == 3)\t\t\t/* rev 3 moved MAC */\n+\t\tloc[0] = SSB_SPROM3_IL0MAC;\n+\telse {\n+\t\tloc[0] = SSB_SPROM1_IL0MAC;\n+\t\tloc[1] = SSB_SPROM1_ET0MAC;\n+\t\tloc[2] = SSB_SPROM1_ET1MAC;\n+\t}\n+\n+\tSPEX(et0phyaddr, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET0A, 0);\n+\tSPEX(et1phyaddr, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET1A,\n+\t     SSB_SPROM1_ETHPHY_ET1A_SHIFT);\n+\tSPEX(et0mdcport, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET0M, 14);\n+\tSPEX(et1mdcport, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET1M, 15);\n+\tSPEX(board_rev, SSB_SPROM1_BINF, SSB_SPROM1_BINF_BREV, 0);\n+\tSPEX(board_type, SSB_SPROM1_SPID, 0xFFFF, 0);\n+\tif (out->revision == 1)\n+\t\tSPEX(country_code, SSB_SPROM1_BINF, SSB_SPROM1_BINF_CCODE,\n+\t\t     SSB_SPROM1_BINF_CCODE_SHIFT);\n+\tSPEX(ant_available_a, SSB_SPROM1_BINF, SSB_SPROM1_BINF_ANTA,\n+\t     SSB_SPROM1_BINF_ANTA_SHIFT);\n+\tSPEX(ant_available_bg, SSB_SPROM1_BINF, SSB_SPROM1_BINF_ANTBG,\n+\t     SSB_SPROM1_BINF_ANTBG_SHIFT);\n+\tSPEX(pa0b0, SSB_SPROM1_PA0B0, 0xFFFF, 0);\n+\tSPEX(pa0b1, SSB_SPROM1_PA0B1, 0xFFFF, 0);\n+\tSPEX(pa0b2, SSB_SPROM1_PA0B2, 0xFFFF, 0);\n+\tSPEX(pa1b0, SSB_SPROM1_PA1B0, 0xFFFF, 0);\n+\tSPEX(pa1b1, SSB_SPROM1_PA1B1, 0xFFFF, 0);\n+\tSPEX(pa1b2, SSB_SPROM1_PA1B2, 0xFFFF, 0);\n+\tSPEX(gpio0, SSB_SPROM1_GPIOA, SSB_SPROM1_GPIOA_P0, 0);\n+\tSPEX(gpio1, SSB_SPROM1_GPIOA, SSB_SPROM1_GPIOA_P1,\n+\t     SSB_SPROM1_GPIOA_P1_SHIFT);\n+\tSPEX(gpio2, SSB_SPROM1_GPIOB, SSB_SPROM1_GPIOB_P2, 0);\n+\tSPEX(gpio3, SSB_SPROM1_GPIOB, SSB_SPROM1_GPIOB_P3,\n+\t     SSB_SPROM1_GPIOB_P3_SHIFT);\n+\tSPEX(maxpwr_a, SSB_SPROM1_MAXPWR, SSB_SPROM1_MAXPWR_A,\n+\t     SSB_SPROM1_MAXPWR_A_SHIFT);\n+\tSPEX(maxpwr_bg, SSB_SPROM1_MAXPWR, SSB_SPROM1_MAXPWR_BG, 0);\n+\tSPEX(itssi_a, SSB_SPROM1_ITSSI, SSB_SPROM1_ITSSI_A,\n+\t     SSB_SPROM1_ITSSI_A_SHIFT);\n+\tSPEX(itssi_bg, SSB_SPROM1_ITSSI, SSB_SPROM1_ITSSI_BG, 0);\n+\tSPEX(boardflags_lo, SSB_SPROM1_BFLLO, 0xFFFF, 0);\n+\n+\tSPEX(alpha2[0], SSB_SPROM1_CCODE, 0xff00, 8);\n+\tSPEX(alpha2[1], SSB_SPROM1_CCODE, 0x00ff, 0);\n+\n+\t/* Extract the antenna gain values. */\n+\tout->antenna_gain.a0 = sprom_extract_antgain(out->revision, in,\n+\t\t\t\t\t\t     SSB_SPROM1_AGAIN,\n+\t\t\t\t\t\t     SSB_SPROM1_AGAIN_BG,\n+\t\t\t\t\t\t     SSB_SPROM1_AGAIN_BG_SHIFT);\n+\tout->antenna_gain.a1 = sprom_extract_antgain(out->revision, in,\n+\t\t\t\t\t\t     SSB_SPROM1_AGAIN,\n+\t\t\t\t\t\t     SSB_SPROM1_AGAIN_A,\n+\t\t\t\t\t\t     SSB_SPROM1_AGAIN_A_SHIFT);\n+\tif (out->revision >= 2)\n+\t\tsprom_extract_r23(out, in);\n+}\n+\n+/* Revs 4 5 and 8 have partially shared layout */\n+static void sprom_extract_r458(struct ssb_sprom *out, const u16 *in)\n+{\n+\tSPEX(txpid2g[0], SSB_SPROM4_TXPID2G01,\n+\t     SSB_SPROM4_TXPID2G0, SSB_SPROM4_TXPID2G0_SHIFT);\n+\tSPEX(txpid2g[1], SSB_SPROM4_TXPID2G01,\n+\t     SSB_SPROM4_TXPID2G1, SSB_SPROM4_TXPID2G1_SHIFT);\n+\tSPEX(txpid2g[2], SSB_SPROM4_TXPID2G23,\n+\t     SSB_SPROM4_TXPID2G2, SSB_SPROM4_TXPID2G2_SHIFT);\n+\tSPEX(txpid2g[3], SSB_SPROM4_TXPID2G23,\n+\t     SSB_SPROM4_TXPID2G3, SSB_SPROM4_TXPID2G3_SHIFT);\n+\n+\tSPEX(txpid5gl[0], SSB_SPROM4_TXPID5GL01,\n+\t     SSB_SPROM4_TXPID5GL0, SSB_SPROM4_TXPID5GL0_SHIFT);\n+\tSPEX(txpid5gl[1], SSB_SPROM4_TXPID5GL01,\n+\t     SSB_SPROM4_TXPID5GL1, SSB_SPROM4_TXPID5GL1_SHIFT);\n+\tSPEX(txpid5gl[2], SSB_SPROM4_TXPID5GL23,\n+\t     SSB_SPROM4_TXPID5GL2, SSB_SPROM4_TXPID5GL2_SHIFT);\n+\tSPEX(txpid5gl[3], SSB_SPROM4_TXPID5GL23,\n+\t     SSB_SPROM4_TXPID5GL3, SSB_SPROM4_TXPID5GL3_SHIFT);\n+\n+\tSPEX(txpid5g[0], SSB_SPROM4_TXPID5G01,\n+\t     SSB_SPROM4_TXPID5G0, SSB_SPROM4_TXPID5G0_SHIFT);\n+\tSPEX(txpid5g[1], SSB_SPROM4_TXPID5G01,\n+\t     SSB_SPROM4_TXPID5G1, SSB_SPROM4_TXPID5G1_SHIFT);\n+\tSPEX(txpid5g[2], SSB_SPROM4_TXPID5G23,\n+\t     SSB_SPROM4_TXPID5G2, SSB_SPROM4_TXPID5G2_SHIFT);\n+\tSPEX(txpid5g[3], SSB_SPROM4_TXPID5G23,\n+\t     SSB_SPROM4_TXPID5G3, SSB_SPROM4_TXPID5G3_SHIFT);\n+\n+\tSPEX(txpid5gh[0], SSB_SPROM4_TXPID5GH01,\n+\t     SSB_SPROM4_TXPID5GH0, SSB_SPROM4_TXPID5GH0_SHIFT);\n+\tSPEX(txpid5gh[1], SSB_SPROM4_TXPID5GH01,\n+\t     SSB_SPROM4_TXPID5GH1, SSB_SPROM4_TXPID5GH1_SHIFT);\n+\tSPEX(txpid5gh[2], SSB_SPROM4_TXPID5GH23,\n+\t     SSB_SPROM4_TXPID5GH2, SSB_SPROM4_TXPID5GH2_SHIFT);\n+\tSPEX(txpid5gh[3], SSB_SPROM4_TXPID5GH23,\n+\t     SSB_SPROM4_TXPID5GH3, SSB_SPROM4_TXPID5GH3_SHIFT);\n+}\n+\n+static void sprom_extract_r45(struct ssb_sprom *out, const u16 *in)\n+{\n+\tstatic const u16 pwr_info_offset[] = {\n+\t\tSSB_SPROM4_PWR_INFO_CORE0, SSB_SPROM4_PWR_INFO_CORE1,\n+\t\tSSB_SPROM4_PWR_INFO_CORE2, SSB_SPROM4_PWR_INFO_CORE3\n+\t};\n+\tu16 il0mac_offset;\n+\tint i;\n+\n+\tBUILD_BUG_ON(ARRAY_SIZE(pwr_info_offset) !=\n+\t\t     ARRAY_SIZE(out->core_pwr_info));\n+\n+\tif (out->revision == 4)\n+\t\til0mac_offset = SSB_SPROM4_IL0MAC;\n+\telse\n+\t\til0mac_offset = SSB_SPROM5_IL0MAC;\n+\n+\tSPEX(et0phyaddr, SSB_SPROM4_ETHPHY, SSB_SPROM4_ETHPHY_ET0A, 0);\n+\tSPEX(et1phyaddr, SSB_SPROM4_ETHPHY, SSB_SPROM4_ETHPHY_ET1A,\n+\t     SSB_SPROM4_ETHPHY_ET1A_SHIFT);\n+\tSPEX(board_rev, SSB_SPROM4_BOARDREV, 0xFFFF, 0);\n+\tSPEX(board_type, SSB_SPROM1_SPID, 0xFFFF, 0);\n+\tif (out->revision == 4) {\n+\t\tSPEX(alpha2[0], SSB_SPROM4_CCODE, 0xff00, 8);\n+\t\tSPEX(alpha2[1], SSB_SPROM4_CCODE, 0x00ff, 0);\n+\t\tSPEX(boardflags_lo, SSB_SPROM4_BFLLO, 0xFFFF, 0);\n+\t\tSPEX(boardflags_hi, SSB_SPROM4_BFLHI, 0xFFFF, 0);\n+\t\tSPEX(boardflags2_lo, SSB_SPROM4_BFL2LO, 0xFFFF, 0);\n+\t\tSPEX(boardflags2_hi, SSB_SPROM4_BFL2HI, 0xFFFF, 0);\n+\t} else {\n+\t\tSPEX(alpha2[0], SSB_SPROM5_CCODE, 0xff00, 8);\n+\t\tSPEX(alpha2[1], SSB_SPROM5_CCODE, 0x00ff, 0);\n+\t\tSPEX(boardflags_lo, SSB_SPROM5_BFLLO, 0xFFFF, 0);\n+\t\tSPEX(boardflags_hi, SSB_SPROM5_BFLHI, 0xFFFF, 0);\n+\t\tSPEX(boardflags2_lo, SSB_SPROM5_BFL2LO, 0xFFFF, 0);\n+\t\tSPEX(boardflags2_hi, SSB_SPROM5_BFL2HI, 0xFFFF, 0);\n+\t}\n+\tSPEX(ant_available_a, SSB_SPROM4_ANTAVAIL, SSB_SPROM4_ANTAVAIL_A,\n+\t     SSB_SPROM4_ANTAVAIL_A_SHIFT);\n+\tSPEX(ant_available_bg, SSB_SPROM4_ANTAVAIL, SSB_SPROM4_ANTAVAIL_BG,\n+\t     SSB_SPROM4_ANTAVAIL_BG_SHIFT);\n+\tSPEX(maxpwr_bg, SSB_SPROM4_MAXP_BG, SSB_SPROM4_MAXP_BG_MASK, 0);\n+\tSPEX(itssi_bg, SSB_SPROM4_MAXP_BG, SSB_SPROM4_ITSSI_BG,\n+\t     SSB_SPROM4_ITSSI_BG_SHIFT);\n+\tSPEX(maxpwr_a, SSB_SPROM4_MAXP_A, SSB_SPROM4_MAXP_A_MASK, 0);\n+\tSPEX(itssi_a, SSB_SPROM4_MAXP_A, SSB_SPROM4_ITSSI_A,\n+\t     SSB_SPROM4_ITSSI_A_SHIFT);\n+\tif (out->revision == 4) {\n+\t\tSPEX(gpio0, SSB_SPROM4_GPIOA, SSB_SPROM4_GPIOA_P0, 0);\n+\t\tSPEX(gpio1, SSB_SPROM4_GPIOA, SSB_SPROM4_GPIOA_P1,\n+\t\t     SSB_SPROM4_GPIOA_P1_SHIFT);\n+\t\tSPEX(gpio2, SSB_SPROM4_GPIOB, SSB_SPROM4_GPIOB_P2, 0);\n+\t\tSPEX(gpio3, SSB_SPROM4_GPIOB, SSB_SPROM4_GPIOB_P3,\n+\t\t     SSB_SPROM4_GPIOB_P3_SHIFT);\n+\t} else {\n+\t\tSPEX(gpio0, SSB_SPROM5_GPIOA, SSB_SPROM5_GPIOA_P0, 0);\n+\t\tSPEX(gpio1, SSB_SPROM5_GPIOA, SSB_SPROM5_GPIOA_P1,\n+\t\t     SSB_SPROM5_GPIOA_P1_SHIFT);\n+\t\tSPEX(gpio2, SSB_SPROM5_GPIOB, SSB_SPROM5_GPIOB_P2, 0);\n+\t\tSPEX(gpio3, SSB_SPROM5_GPIOB, SSB_SPROM5_GPIOB_P3,\n+\t\t     SSB_SPROM5_GPIOB_P3_SHIFT);\n+\t}\n+\n+\t/* Extract the antenna gain values. */\n+\tout->antenna_gain.a0 = sprom_extract_antgain(out->revision, in,\n+\t\t\t\t\t\t     SSB_SPROM4_AGAIN01,\n+\t\t\t\t\t\t     SSB_SPROM4_AGAIN0,\n+\t\t\t\t\t\t     SSB_SPROM4_AGAIN0_SHIFT);\n+\tout->antenna_gain.a1 = sprom_extract_antgain(out->revision, in,\n+\t\t\t\t\t\t     SSB_SPROM4_AGAIN01,\n+\t\t\t\t\t\t     SSB_SPROM4_AGAIN1,\n+\t\t\t\t\t\t     SSB_SPROM4_AGAIN1_SHIFT);\n+\tout->antenna_gain.a2 = sprom_extract_antgain(out->revision, in,\n+\t\t\t\t\t\t     SSB_SPROM4_AGAIN23,\n+\t\t\t\t\t\t     SSB_SPROM4_AGAIN2,\n+\t\t\t\t\t\t     SSB_SPROM4_AGAIN2_SHIFT);\n+\tout->antenna_gain.a3 = sprom_extract_antgain(out->revision, in,\n+\t\t\t\t\t\t     SSB_SPROM4_AGAIN23,\n+\t\t\t\t\t\t     SSB_SPROM4_AGAIN3,\n+\t\t\t\t\t\t     SSB_SPROM4_AGAIN3_SHIFT);\n+\n+\t/* Extract cores power info info */\n+\tfor (i = 0; i < ARRAY_SIZE(pwr_info_offset); i++) {\n+\t\tu16 o = pwr_info_offset[i];\n+\n+\t\tSPEX(core_pwr_info[i].itssi_2g, o + SSB_SPROM4_2G_MAXP_ITSSI,\n+\t\t\tSSB_SPROM4_2G_ITSSI, SSB_SPROM4_2G_ITSSI_SHIFT);\n+\t\tSPEX(core_pwr_info[i].maxpwr_2g, o + SSB_SPROM4_2G_MAXP_ITSSI,\n+\t\t\tSSB_SPROM4_2G_MAXP, 0);\n+\n+\t\tSPEX(core_pwr_info[i].pa_2g[0], o + SSB_SPROM4_2G_PA_0, ~0, 0);\n+\t\tSPEX(core_pwr_info[i].pa_2g[1], o + SSB_SPROM4_2G_PA_1, ~0, 0);\n+\t\tSPEX(core_pwr_info[i].pa_2g[2], o + SSB_SPROM4_2G_PA_2, ~0, 0);\n+\t\tSPEX(core_pwr_info[i].pa_2g[3], o + SSB_SPROM4_2G_PA_3, ~0, 0);\n+\n+\t\tSPEX(core_pwr_info[i].itssi_5g, o + SSB_SPROM4_5G_MAXP_ITSSI,\n+\t\t\tSSB_SPROM4_5G_ITSSI, SSB_SPROM4_5G_ITSSI_SHIFT);\n+\t\tSPEX(core_pwr_info[i].maxpwr_5g, o + SSB_SPROM4_5G_MAXP_ITSSI,\n+\t\t\tSSB_SPROM4_5G_MAXP, 0);\n+\t\tSPEX(core_pwr_info[i].maxpwr_5gh, o + SSB_SPROM4_5GHL_MAXP,\n+\t\t\tSSB_SPROM4_5GH_MAXP, 0);\n+\t\tSPEX(core_pwr_info[i].maxpwr_5gl, o + SSB_SPROM4_5GHL_MAXP,\n+\t\t\tSSB_SPROM4_5GL_MAXP, SSB_SPROM4_5GL_MAXP_SHIFT);\n+\n+\t\tSPEX(core_pwr_info[i].pa_5gl[0], o + SSB_SPROM4_5GL_PA_0, ~0, 0);\n+\t\tSPEX(core_pwr_info[i].pa_5gl[1], o + SSB_SPROM4_5GL_PA_1, ~0, 0);\n+\t\tSPEX(core_pwr_info[i].pa_5gl[2], o + SSB_SPROM4_5GL_PA_2, ~0, 0);\n+\t\tSPEX(core_pwr_info[i].pa_5gl[3], o + SSB_SPROM4_5GL_PA_3, ~0, 0);\n+\t\tSPEX(core_pwr_info[i].pa_5g[0], o + SSB_SPROM4_5G_PA_0, ~0, 0);\n+\t\tSPEX(core_pwr_info[i].pa_5g[1], o + SSB_SPROM4_5G_PA_1, ~0, 0);\n+\t\tSPEX(core_pwr_info[i].pa_5g[2], o + SSB_SPROM4_5G_PA_2, ~0, 0);\n+\t\tSPEX(core_pwr_info[i].pa_5g[3], o + SSB_SPROM4_5G_PA_3, ~0, 0);\n+\t\tSPEX(core_pwr_info[i].pa_5gh[0], o + SSB_SPROM4_5GH_PA_0, ~0, 0);\n+\t\tSPEX(core_pwr_info[i].pa_5gh[1], o + SSB_SPROM4_5GH_PA_1, ~0, 0);\n+\t\tSPEX(core_pwr_info[i].pa_5gh[2], o + SSB_SPROM4_5GH_PA_2, ~0, 0);\n+\t\tSPEX(core_pwr_info[i].pa_5gh[3], o + SSB_SPROM4_5GH_PA_3, ~0, 0);\n+\t}\n+\n+\tsprom_extract_r458(out, in);\n+\n+\t/* TODO - get remaining rev 4 stuff needed */\n+}\n+\n+static void sprom_extract_r8(struct ssb_sprom *out, const u16 *in)\n+{\n+\tint i;\n+\tu16 o;\n+\tstatic const u16 pwr_info_offset[] = {\n+\t\tSSB_SROM8_PWR_INFO_CORE0, SSB_SROM8_PWR_INFO_CORE1,\n+\t\tSSB_SROM8_PWR_INFO_CORE2, SSB_SROM8_PWR_INFO_CORE3\n+\t};\n+\tBUILD_BUG_ON(ARRAY_SIZE(pwr_info_offset) !=\n+\t\t\tARRAY_SIZE(out->core_pwr_info));\n+\n+\tSPEX(board_rev, SSB_SPROM8_BOARDREV, 0xFFFF, 0);\n+\tSPEX(board_type, SSB_SPROM1_SPID, 0xFFFF, 0);\n+\tSPEX(alpha2[0], SSB_SPROM8_CCODE, 0xff00, 8);\n+\tSPEX(alpha2[1], SSB_SPROM8_CCODE, 0x00ff, 0);\n+\tSPEX(boardflags_lo, SSB_SPROM8_BFLLO, 0xFFFF, 0);\n+\tSPEX(boardflags_hi, SSB_SPROM8_BFLHI, 0xFFFF, 0);\n+\tSPEX(boardflags2_lo, SSB_SPROM8_BFL2LO, 0xFFFF, 0);\n+\tSPEX(boardflags2_hi, SSB_SPROM8_BFL2HI, 0xFFFF, 0);\n+\tSPEX(ant_available_a, SSB_SPROM8_ANTAVAIL, SSB_SPROM8_ANTAVAIL_A,\n+\t     SSB_SPROM8_ANTAVAIL_A_SHIFT);\n+\tSPEX(ant_available_bg, SSB_SPROM8_ANTAVAIL, SSB_SPROM8_ANTAVAIL_BG,\n+\t     SSB_SPROM8_ANTAVAIL_BG_SHIFT);\n+\tSPEX(maxpwr_bg, SSB_SPROM8_MAXP_BG, SSB_SPROM8_MAXP_BG_MASK, 0);\n+\tSPEX(itssi_bg, SSB_SPROM8_MAXP_BG, SSB_SPROM8_ITSSI_BG,\n+\t     SSB_SPROM8_ITSSI_BG_SHIFT);\n+\tSPEX(maxpwr_a, SSB_SPROM8_MAXP_A, SSB_SPROM8_MAXP_A_MASK, 0);\n+\tSPEX(itssi_a, SSB_SPROM8_MAXP_A, SSB_SPROM8_ITSSI_A,\n+\t     SSB_SPROM8_ITSSI_A_SHIFT);\n+\tSPEX(maxpwr_ah, SSB_SPROM8_MAXP_AHL, SSB_SPROM8_MAXP_AH_MASK, 0);\n+\tSPEX(maxpwr_al, SSB_SPROM8_MAXP_AHL, SSB_SPROM8_MAXP_AL_MASK,\n+\t     SSB_SPROM8_MAXP_AL_SHIFT);\n+\tSPEX(gpio0, SSB_SPROM8_GPIOA, SSB_SPROM8_GPIOA_P0, 0);\n+\tSPEX(gpio1, SSB_SPROM8_GPIOA, SSB_SPROM8_GPIOA_P1,\n+\t     SSB_SPROM8_GPIOA_P1_SHIFT);\n+\tSPEX(gpio2, SSB_SPROM8_GPIOB, SSB_SPROM8_GPIOB_P2, 0);\n+\tSPEX(gpio3, SSB_SPROM8_GPIOB, SSB_SPROM8_GPIOB_P3,\n+\t     SSB_SPROM8_GPIOB_P3_SHIFT);\n+\tSPEX(tri2g, SSB_SPROM8_TRI25G, SSB_SPROM8_TRI2G, 0);\n+\tSPEX(tri5g, SSB_SPROM8_TRI25G, SSB_SPROM8_TRI5G,\n+\t     SSB_SPROM8_TRI5G_SHIFT);\n+\tSPEX(tri5gl, SSB_SPROM8_TRI5GHL, SSB_SPROM8_TRI5GL, 0);\n+\tSPEX(tri5gh, SSB_SPROM8_TRI5GHL, SSB_SPROM8_TRI5GH,\n+\t     SSB_SPROM8_TRI5GH_SHIFT);\n+\tSPEX(rxpo2g, SSB_SPROM8_RXPO, SSB_SPROM8_RXPO2G, 0);\n+\tSPEX(rxpo5g, SSB_SPROM8_RXPO, SSB_SPROM8_RXPO5G,\n+\t     SSB_SPROM8_RXPO5G_SHIFT);\n+\tSPEX(rssismf2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_RSSISMF2G, 0);\n+\tSPEX(rssismc2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_RSSISMC2G,\n+\t     SSB_SPROM8_RSSISMC2G_SHIFT);\n+\tSPEX(rssisav2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_RSSISAV2G,\n+\t     SSB_SPROM8_RSSISAV2G_SHIFT);\n+\tSPEX(bxa2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_BXA2G,\n+\t     SSB_SPROM8_BXA2G_SHIFT);\n+\tSPEX(rssismf5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_RSSISMF5G, 0);\n+\tSPEX(rssismc5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_RSSISMC5G,\n+\t     SSB_SPROM8_RSSISMC5G_SHIFT);\n+\tSPEX(rssisav5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_RSSISAV5G,\n+\t     SSB_SPROM8_RSSISAV5G_SHIFT);\n+\tSPEX(bxa5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_BXA5G,\n+\t     SSB_SPROM8_BXA5G_SHIFT);\n+\tSPEX(pa0b0, SSB_SPROM8_PA0B0, 0xFFFF, 0);\n+\tSPEX(pa0b1, SSB_SPROM8_PA0B1, 0xFFFF, 0);\n+\tSPEX(pa0b2, SSB_SPROM8_PA0B2, 0xFFFF, 0);\n+\tSPEX(pa1b0, SSB_SPROM8_PA1B0, 0xFFFF, 0);\n+\tSPEX(pa1b1, SSB_SPROM8_PA1B1, 0xFFFF, 0);\n+\tSPEX(pa1b2, SSB_SPROM8_PA1B2, 0xFFFF, 0);\n+\tSPEX(pa1lob0, SSB_SPROM8_PA1LOB0, 0xFFFF, 0);\n+\tSPEX(pa1lob1, SSB_SPROM8_PA1LOB1, 0xFFFF, 0);\n+\tSPEX(pa1lob2, SSB_SPROM8_PA1LOB2, 0xFFFF, 0);\n+\tSPEX(pa1hib0, SSB_SPROM8_PA1HIB0, 0xFFFF, 0);\n+\tSPEX(pa1hib1, SSB_SPROM8_PA1HIB1, 0xFFFF, 0);\n+\tSPEX(pa1hib2, SSB_SPROM8_PA1HIB2, 0xFFFF, 0);\n+\tSPEX(cck2gpo, SSB_SPROM8_CCK2GPO, 0xFFFF, 0);\n+\tSPEX32(ofdm2gpo, SSB_SPROM8_OFDM2GPO, 0xFFFFFFFF, 0);\n+\tSPEX32(ofdm5glpo, SSB_SPROM8_OFDM5GLPO, 0xFFFFFFFF, 0);\n+\tSPEX32(ofdm5gpo, SSB_SPROM8_OFDM5GPO, 0xFFFFFFFF, 0);\n+\tSPEX32(ofdm5ghpo, SSB_SPROM8_OFDM5GHPO, 0xFFFFFFFF, 0);\n+\n+\t/* Extract the antenna gain values. */\n+\tout->antenna_gain.a0 = sprom_extract_antgain(out->revision, in,\n+\t\t\t\t\t\t     SSB_SPROM8_AGAIN01,\n+\t\t\t\t\t\t     SSB_SPROM8_AGAIN0,\n+\t\t\t\t\t\t     SSB_SPROM8_AGAIN0_SHIFT);\n+\tout->antenna_gain.a1 = sprom_extract_antgain(out->revision, in,\n+\t\t\t\t\t\t     SSB_SPROM8_AGAIN01,\n+\t\t\t\t\t\t     SSB_SPROM8_AGAIN1,\n+\t\t\t\t\t\t     SSB_SPROM8_AGAIN1_SHIFT);\n+\tout->antenna_gain.a2 = sprom_extract_antgain(out->revision, in,\n+\t\t\t\t\t\t     SSB_SPROM8_AGAIN23,\n+\t\t\t\t\t\t     SSB_SPROM8_AGAIN2,\n+\t\t\t\t\t\t     SSB_SPROM8_AGAIN2_SHIFT);\n+\tout->antenna_gain.a3 = sprom_extract_antgain(out->revision, in,\n+\t\t\t\t\t\t     SSB_SPROM8_AGAIN23,\n+\t\t\t\t\t\t     SSB_SPROM8_AGAIN3,\n+\t\t\t\t\t\t     SSB_SPROM8_AGAIN3_SHIFT);\n+\n+\t/* Extract cores power info info */\n+\tfor (i = 0; i < ARRAY_SIZE(pwr_info_offset); i++) {\n+\t\to = pwr_info_offset[i];\n+\t\tSPEX(core_pwr_info[i].itssi_2g, o + SSB_SROM8_2G_MAXP_ITSSI,\n+\t\t\tSSB_SPROM8_2G_ITSSI, SSB_SPROM8_2G_ITSSI_SHIFT);\n+\t\tSPEX(core_pwr_info[i].maxpwr_2g, o + SSB_SROM8_2G_MAXP_ITSSI,\n+\t\t\tSSB_SPROM8_2G_MAXP, 0);\n+\n+\t\tSPEX(core_pwr_info[i].pa_2g[0], o + SSB_SROM8_2G_PA_0, ~0, 0);\n+\t\tSPEX(core_pwr_info[i].pa_2g[1], o + SSB_SROM8_2G_PA_1, ~0, 0);\n+\t\tSPEX(core_pwr_info[i].pa_2g[2], o + SSB_SROM8_2G_PA_2, ~0, 0);\n+\n+\t\tSPEX(core_pwr_info[i].itssi_5g, o + SSB_SROM8_5G_MAXP_ITSSI,\n+\t\t\tSSB_SPROM8_5G_ITSSI, SSB_SPROM8_5G_ITSSI_SHIFT);\n+\t\tSPEX(core_pwr_info[i].maxpwr_5g, o + SSB_SROM8_5G_MAXP_ITSSI,\n+\t\t\tSSB_SPROM8_5G_MAXP, 0);\n+\t\tSPEX(core_pwr_info[i].maxpwr_5gh, o + SSB_SPROM8_5GHL_MAXP,\n+\t\t\tSSB_SPROM8_5GH_MAXP, 0);\n+\t\tSPEX(core_pwr_info[i].maxpwr_5gl, o + SSB_SPROM8_5GHL_MAXP,\n+\t\t\tSSB_SPROM8_5GL_MAXP, SSB_SPROM8_5GL_MAXP_SHIFT);\n+\n+\t\tSPEX(core_pwr_info[i].pa_5gl[0], o + SSB_SROM8_5GL_PA_0, ~0, 0);\n+\t\tSPEX(core_pwr_info[i].pa_5gl[1], o + SSB_SROM8_5GL_PA_1, ~0, 0);\n+\t\tSPEX(core_pwr_info[i].pa_5gl[2], o + SSB_SROM8_5GL_PA_2, ~0, 0);\n+\t\tSPEX(core_pwr_info[i].pa_5g[0], o + SSB_SROM8_5G_PA_0, ~0, 0);\n+\t\tSPEX(core_pwr_info[i].pa_5g[1], o + SSB_SROM8_5G_PA_1, ~0, 0);\n+\t\tSPEX(core_pwr_info[i].pa_5g[2], o + SSB_SROM8_5G_PA_2, ~0, 0);\n+\t\tSPEX(core_pwr_info[i].pa_5gh[0], o + SSB_SROM8_5GH_PA_0, ~0, 0);\n+\t\tSPEX(core_pwr_info[i].pa_5gh[1], o + SSB_SROM8_5GH_PA_1, ~0, 0);\n+\t\tSPEX(core_pwr_info[i].pa_5gh[2], o + SSB_SROM8_5GH_PA_2, ~0, 0);\n+\t}\n+\n+\t/* Extract FEM info */\n+\tSPEX(fem.ghz2.tssipos, SSB_SPROM8_FEM2G,\n+\t\tSSB_SROM8_FEM_TSSIPOS, SSB_SROM8_FEM_TSSIPOS_SHIFT);\n+\tSPEX(fem.ghz2.extpa_gain, SSB_SPROM8_FEM2G,\n+\t\tSSB_SROM8_FEM_EXTPA_GAIN, SSB_SROM8_FEM_EXTPA_GAIN_SHIFT);\n+\tSPEX(fem.ghz2.pdet_range, SSB_SPROM8_FEM2G,\n+\t\tSSB_SROM8_FEM_PDET_RANGE, SSB_SROM8_FEM_PDET_RANGE_SHIFT);\n+\tSPEX(fem.ghz2.tr_iso, SSB_SPROM8_FEM2G,\n+\t\tSSB_SROM8_FEM_TR_ISO, SSB_SROM8_FEM_TR_ISO_SHIFT);\n+\tSPEX(fem.ghz2.antswlut, SSB_SPROM8_FEM2G,\n+\t\tSSB_SROM8_FEM_ANTSWLUT, SSB_SROM8_FEM_ANTSWLUT_SHIFT);\n+\n+\tSPEX(fem.ghz5.tssipos, SSB_SPROM8_FEM5G,\n+\t\tSSB_SROM8_FEM_TSSIPOS, SSB_SROM8_FEM_TSSIPOS_SHIFT);\n+\tSPEX(fem.ghz5.extpa_gain, SSB_SPROM8_FEM5G,\n+\t\tSSB_SROM8_FEM_EXTPA_GAIN, SSB_SROM8_FEM_EXTPA_GAIN_SHIFT);\n+\tSPEX(fem.ghz5.pdet_range, SSB_SPROM8_FEM5G,\n+\t\tSSB_SROM8_FEM_PDET_RANGE, SSB_SROM8_FEM_PDET_RANGE_SHIFT);\n+\tSPEX(fem.ghz5.tr_iso, SSB_SPROM8_FEM5G,\n+\t\tSSB_SROM8_FEM_TR_ISO, SSB_SROM8_FEM_TR_ISO_SHIFT);\n+\tSPEX(fem.ghz5.antswlut, SSB_SPROM8_FEM5G,\n+\t\tSSB_SROM8_FEM_ANTSWLUT, SSB_SROM8_FEM_ANTSWLUT_SHIFT);\n+\n+\tSPEX(leddc_on_time, SSB_SPROM8_LEDDC, SSB_SPROM8_LEDDC_ON,\n+\t     SSB_SPROM8_LEDDC_ON_SHIFT);\n+\tSPEX(leddc_off_time, SSB_SPROM8_LEDDC, SSB_SPROM8_LEDDC_OFF,\n+\t     SSB_SPROM8_LEDDC_OFF_SHIFT);\n+\n+\tSPEX(txchain, SSB_SPROM8_TXRXC, SSB_SPROM8_TXRXC_TXCHAIN,\n+\t     SSB_SPROM8_TXRXC_TXCHAIN_SHIFT);\n+\tSPEX(rxchain, SSB_SPROM8_TXRXC, SSB_SPROM8_TXRXC_RXCHAIN,\n+\t     SSB_SPROM8_TXRXC_RXCHAIN_SHIFT);\n+\tSPEX(antswitch, SSB_SPROM8_TXRXC, SSB_SPROM8_TXRXC_SWITCH,\n+\t     SSB_SPROM8_TXRXC_SWITCH_SHIFT);\n+\n+\tSPEX(opo, SSB_SPROM8_OFDM2GPO, 0x00ff, 0);\n+\n+\tSPEX_ARRAY8(mcs2gpo, SSB_SPROM8_2G_MCSPO, ~0, 0);\n+\tSPEX_ARRAY8(mcs5gpo, SSB_SPROM8_5G_MCSPO, ~0, 0);\n+\tSPEX_ARRAY8(mcs5glpo, SSB_SPROM8_5GL_MCSPO, ~0, 0);\n+\tSPEX_ARRAY8(mcs5ghpo, SSB_SPROM8_5GH_MCSPO, ~0, 0);\n+\n+\tSPEX(rawtempsense, SSB_SPROM8_RAWTS, SSB_SPROM8_RAWTS_RAWTEMP,\n+\t     SSB_SPROM8_RAWTS_RAWTEMP_SHIFT);\n+\tSPEX(measpower, SSB_SPROM8_RAWTS, SSB_SPROM8_RAWTS_MEASPOWER,\n+\t     SSB_SPROM8_RAWTS_MEASPOWER_SHIFT);\n+\tSPEX(tempsense_slope, SSB_SPROM8_OPT_CORRX,\n+\t     SSB_SPROM8_OPT_CORRX_TEMP_SLOPE,\n+\t     SSB_SPROM8_OPT_CORRX_TEMP_SLOPE_SHIFT);\n+\tSPEX(tempcorrx, SSB_SPROM8_OPT_CORRX, SSB_SPROM8_OPT_CORRX_TEMPCORRX,\n+\t     SSB_SPROM8_OPT_CORRX_TEMPCORRX_SHIFT);\n+\tSPEX(tempsense_option, SSB_SPROM8_OPT_CORRX,\n+\t     SSB_SPROM8_OPT_CORRX_TEMP_OPTION,\n+\t     SSB_SPROM8_OPT_CORRX_TEMP_OPTION_SHIFT);\n+\tSPEX(freqoffset_corr, SSB_SPROM8_HWIQ_IQSWP,\n+\t     SSB_SPROM8_HWIQ_IQSWP_FREQ_CORR,\n+\t     SSB_SPROM8_HWIQ_IQSWP_FREQ_CORR_SHIFT);\n+\tSPEX(iqcal_swp_dis, SSB_SPROM8_HWIQ_IQSWP,\n+\t     SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP,\n+\t     SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP_SHIFT);\n+\tSPEX(hw_iqcal_en, SSB_SPROM8_HWIQ_IQSWP, SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL,\n+\t     SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL_SHIFT);\n+\n+\tSPEX(bw40po, SSB_SPROM8_BW40PO, ~0, 0);\n+\tSPEX(cddpo, SSB_SPROM8_CDDPO, ~0, 0);\n+\tSPEX(stbcpo, SSB_SPROM8_STBCPO, ~0, 0);\n+\tSPEX(bwduppo, SSB_SPROM8_BWDUPPO, ~0, 0);\n+\n+\tSPEX(tempthresh, SSB_SPROM8_THERMAL, SSB_SPROM8_THERMAL_TRESH,\n+\t     SSB_SPROM8_THERMAL_TRESH_SHIFT);\n+\tSPEX(tempoffset, SSB_SPROM8_THERMAL, SSB_SPROM8_THERMAL_OFFSET,\n+\t     SSB_SPROM8_THERMAL_OFFSET_SHIFT);\n+\tSPEX(phycal_tempdelta, SSB_SPROM8_TEMPDELTA,\n+\t     SSB_SPROM8_TEMPDELTA_PHYCAL,\n+\t     SSB_SPROM8_TEMPDELTA_PHYCAL_SHIFT);\n+\tSPEX(temps_period, SSB_SPROM8_TEMPDELTA, SSB_SPROM8_TEMPDELTA_PERIOD,\n+\t     SSB_SPROM8_TEMPDELTA_PERIOD_SHIFT);\n+\tSPEX(temps_hysteresis, SSB_SPROM8_TEMPDELTA,\n+\t     SSB_SPROM8_TEMPDELTA_HYSTERESIS,\n+\t     SSB_SPROM8_TEMPDELTA_HYSTERESIS_SHIFT);\n+\tsprom_extract_r458(out, in);\n+\n+\t/* TODO - get remaining rev 8 stuff needed */\n+}\n+\n+static int sprom_extract(struct ssb_sprom *out, const u16 *in, u16 size)\n+{\n+\tmemset(out, 0, sizeof(*out));\n+\n+\tout->revision = in[size - 1] & 0x00FF;\n+\n+\tmemset(out->et0mac, 0xFF, 6);\t\t/* preset et0 and et1 mac */\n+\tmemset(out->et1mac, 0xFF, 6);\n+\n+\tswitch (out->revision) {\n+\tcase 1:\n+\tcase 2:\n+\tcase 3:\n+\t\tsprom_extract_r123(out, in);\n+\t\tbreak;\n+\tcase 4:\n+\tcase 5:\n+\t\tsprom_extract_r45(out, in);\n+\t\tbreak;\n+\tcase 8:\n+\t\tsprom_extract_r8(out, in);\n+\t\tbreak;\n+\tdefault:\n+\t\tpr_warn(\"Unsupported SPROM revision %d detected. Will extract v1\\n\",\n+\t\t\tout->revision);\n+\t\tout->revision = 1;\n+\t\tsprom_extract_r123(out, in);\n+\t}\n+\n+\tif (out->boardflags_lo == 0xFFFF)\n+\t\tout->boardflags_lo = 0;  /* per specs */\n+\tif (out->boardflags_hi == 0xFFFF)\n+\t\tout->boardflags_hi = 0;  /* per specs */\n+\n+\treturn 0;\n+}\n+\n+static __initdata u16 template_sprom[220];\n #endif\n \n+\n int __init bcm63xx_register_fallback_sprom(struct fallback_sprom_data *data)\n {\n \tint ret = 0;\n \n #ifdef CONFIG_SSB_PCIHOST\n+\tu16 size = 0;\n+\n \tswitch (data->type) {\n \tcase SPROM_DEFAULT:\n \t\tmemcpy(&bcm63xx_sprom, &bcm63xx_default_sprom,\n@@ -71,6 +614,9 @@ int __init bcm63xx_register_fallback_spr\n \t\treturn -EINVAL;\n \t}\n \n+\tif (size > 0)\n+\t\tsprom_extract(&bcm63xx_sprom, template_sprom, size);\n+\n \tmemcpy(bcm63xx_sprom.il0mac, data->mac_addr, ETH_ALEN);\n \tmemcpy(bcm63xx_sprom.et0mac, data->mac_addr, ETH_ALEN);\n \tmemcpy(bcm63xx_sprom.et1mac, data->mac_addr, ETH_ALEN);\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/361-MIPS-BCM63XX-add-raw-fallback-sproms-for-most-common.patch",
    "content": "From 7be5bb46003295c9e04fd4e795593b2deaacd783 Mon Sep 17 00:00:00 2001\nFrom: Jonas Gorski <jogo@openwrt.org>\nDate: Tue, 29 Jul 2014 22:33:38 +0200\nSubject: [PATCH 06/10] MIPS: BCM63XX: add raw fallback sproms for most common\n ssb cards\n\nAdd template sproms for BCM4306, BCM4318, BCM4321, BCM4322, and BCM43222.\n\nSigned-off-by: Jonas Gorski <jogo@openwrt.org>\n---\n arch/mips/bcm63xx/sprom.c                          | 136 +++++++++++++++++++++\n .../asm/mach-bcm63xx/bcm63xx_fallback_sprom.h      |   6 +\n 2 files changed, 142 insertions(+)\n\n--- a/arch/mips/bcm63xx/sprom.c\n+++ b/arch/mips/bcm63xx/sprom.c\n@@ -43,6 +43,122 @@ static __initconst struct ssb_sprom bcm6\n \t.boardflags_hi\t\t= 0x0000,\n };\n \n+\n+static __initconst u16 bcm4306_sprom[] = {\n+\t0x4001, 0x0000, 0x0453, 0x14e4, 0x4320, 0x8000, 0x0002, 0x0002,\n+\t0x1000, 0x1800, 0x0000, 0x0000, 0xffff, 0xffff, 0xffff, 0xffff,\n+\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n+\t0xffff, 0xffff, 0xffff, 0xffff, 0x0000, 0xffff, 0xffff, 0xffff,\n+\t0xffff, 0xffff, 0xffff, 0xffff, 0x0000, 0x0000, 0x0000, 0xffff,\n+\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0x3034, 0x14d4,\n+\t0xfa91, 0xfe60, 0xffff, 0xffff, 0x004c, 0xffff, 0xffff, 0xffff,\n+\t0x003e, 0x0a49, 0xff02, 0x0000, 0xff10, 0xffff, 0xffff, 0x0002,\n+};\n+\n+static __initconst u16 bcm4318_sprom[] = {\n+\t0x2001, 0x0000, 0x0449, 0x14e4, 0x4318, 0x8000, 0x0002, 0x0000,\n+\t0x1000, 0x1800, 0x0000, 0x0000, 0xffff, 0xffff, 0xffff, 0xffff,\n+\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n+\t0xffff, 0xffff, 0xffff, 0xffff, 0x0000, 0xffff, 0xffff, 0xffff,\n+\t0xffff, 0xffff, 0xffff, 0xffff, 0x0000, 0x0000, 0x0000, 0xffff,\n+\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0x3046, 0x15a7,\n+\t0xfab0, 0xfe97, 0xffff, 0xffff, 0x0048, 0xffff, 0xffff, 0xffff,\n+\t0x003e, 0xea49, 0xff02, 0x0000, 0xff08, 0xffff, 0xffff, 0x0002,\n+};\n+\n+static __initconst u16 bcm4321_sprom[] = {\n+\t0x3001, 0x0000, 0x046c, 0x14e4, 0x4328, 0x8000, 0x0002, 0x0000,\n+\t0x1000, 0x1800, 0x0000, 0x0000, 0xffff, 0xffff, 0xffff, 0xffff,\n+\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n+\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n+\t0x5372, 0x0032, 0x4a01, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n+\t0x0000, 0x0000, 0x0000, 0xffff, 0xffff, 0xffff, 0x0303, 0x0202,\n+\t0xffff, 0x2728, 0x5b5b, 0x222b, 0x5b5b, 0x1927, 0x5b5b, 0x1e36,\n+\t0x5b5b, 0x303c, 0x3030, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n+\t0x3e4c, 0x0000, 0x0000, 0x0000, 0x0000, 0x7838, 0x3a34, 0x0000,\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n+\t0x0000, 0x0000, 0x0000, 0xffff, 0xffff, 0xffff, 0xffff, 0x3e4c,\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x7838, 0x3a34, 0x0000, 0x0000,\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n+\t0x0000, 0x0000, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n+\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n+\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n+\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n+\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n+\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n+\t0xffff, 0xffff, 0xffff, 0xffff, 0x0008, 0x0000, 0x0000, 0x0000,\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n+\t0x0000, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n+\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n+\t0xffff, 0xffff, 0xffff, 0x0004,\n+};\n+\n+static __initconst u16 bcm4322_sprom[] = {\n+\t0x3001, 0x0000, 0x04bc, 0x14e4, 0x432c, 0x8000, 0x0002, 0x0000,\n+\t0x1730, 0x1800, 0x0000, 0x0000, 0xffff, 0xffff, 0xffff, 0xffff,\n+\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n+\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n+\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n+\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n+\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n+\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n+\t0x5372, 0x1209, 0x0200, 0x0000, 0x0400, 0x0000, 0x0000, 0x0000,\n+\t0x0000, 0x0000, 0x0000, 0xffff, 0xffff, 0xffff, 0x0303, 0x0202,\n+\t0xffff, 0x0033, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0x0301,\n+\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n+\t0x2048, 0xfe9a, 0x1571, 0xfabd, 0xffff, 0xffff, 0xffff, 0xffff,\n+\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n+\t0x2048, 0xfeb9, 0x159f, 0xfadd, 0xffff, 0xffff, 0xffff, 0xffff,\n+\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n+\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n+\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n+\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n+\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n+\t0x0000, 0x0000, 0x0000, 0x3333, 0x5555, 0xffff, 0xffff, 0xffff,\n+\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n+\t0xffff, 0xffff, 0xffff, 0x0008,\n+};\n+\n+static __initconst u16 bcm43222_sprom[] = {\n+\t0x2001, 0x0000, 0x04d4, 0x14e4, 0x4351, 0x8000, 0x0002, 0x0000,\n+\t0x1730, 0x1800, 0x0000, 0x0000, 0xffff, 0xffff, 0xffff, 0xffff,\n+\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n+\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n+\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n+\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n+\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n+\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n+\t0x5372, 0x2305, 0x0200, 0x0000, 0x2400, 0x0000, 0x0000, 0x0000,\n+\t0x0000, 0x0000, 0x0000, 0xffff, 0xffff, 0xffff, 0x0303, 0x0202,\n+\t0xffff, 0x0033, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0x0325,\n+\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n+\t0x204c, 0xfea6, 0x1717, 0xfa6d, 0xffff, 0xffff, 0xffff, 0xffff,\n+\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n+\t0x204c, 0xfeb8, 0x167c, 0xfa9e, 0xffff, 0xffff, 0xffff, 0xffff,\n+\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n+\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n+\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n+\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n+\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n+\t0x0000, 0x3333, 0x3333, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n+\t0x0000, 0x3333, 0x3333, 0x3333, 0x3333, 0x3333, 0x3333, 0x3333,\n+\t0x3333, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n+\t0x0000, 0x0000, 0x0000, 0x0004, 0x0000, 0xffff, 0xffff, 0xffff,\n+\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n+\t0xffff, 0xffff, 0xffff, 0x0008,\n+};\n+\n static struct ssb_sprom bcm63xx_sprom;\n \n int bcm63xx_get_fallback_sprom(struct ssb_bus *bus, struct ssb_sprom *out)\n@@ -606,6 +722,26 @@ int __init bcm63xx_register_fallback_spr\n \tu16 size = 0;\n \n \tswitch (data->type) {\n+\tcase SPROM_BCM4306:\n+\t\tmemcpy(&template_sprom, &bcm4306_sprom, sizeof(bcm4306_sprom));\n+\t\tsize = ARRAY_SIZE(bcm4306_sprom);\n+\t\tbreak;\n+\tcase SPROM_BCM4318:\n+\t\tmemcpy(&template_sprom, &bcm4318_sprom, sizeof(bcm4318_sprom));\n+\t\tsize = ARRAY_SIZE(bcm4318_sprom);\n+\t\tbreak;\n+\tcase SPROM_BCM4321:\n+\t\tmemcpy(&template_sprom, &bcm4321_sprom, sizeof(bcm4321_sprom));\n+\t\tsize = ARRAY_SIZE(bcm4321_sprom);\n+\t\tbreak;\n+\tcase SPROM_BCM4322:\n+\t\tmemcpy(&template_sprom, &bcm4322_sprom, sizeof(bcm4322_sprom));\n+\t\tsize = ARRAY_SIZE(bcm4322_sprom);\n+\t\tbreak;\n+\tcase SPROM_BCM43222:\n+\t\tmemcpy(&template_sprom, &bcm43222_sprom, sizeof(bcm43222_sprom));\n+\t\tsize = ARRAY_SIZE(bcm43222_sprom);\n+\t\tbreak;\n \tcase SPROM_DEFAULT:\n \t\tmemcpy(&bcm63xx_sprom, &bcm63xx_default_sprom,\n \t\t       sizeof(bcm63xx_sprom));\n--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_fallback_sprom.h\n+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_fallback_sprom.h\n@@ -5,6 +5,12 @@\n \n enum sprom_type {\n \tSPROM_DEFAULT, /* default fallback sprom */\n+\t/* SSB based */\n+\tSPROM_BCM4306,\n+\tSPROM_BCM4318,\n+\tSPROM_BCM4321,\n+\tSPROM_BCM4322,\n+\tSPROM_BCM43222,\n };\n \n struct fallback_sprom_data {\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/362-MIPS-BCM63XX-also-register-a-fallback-sprom-for-bcma.patch",
    "content": "From 03feb9db77fba3eef3d83e17a87a56979659b248 Mon Sep 17 00:00:00 2001\nFrom: Jonas Gorski <jogo@openwrt.org>\nDate: Tue, 29 Jul 2014 22:48:26 +0200\nSubject: [PATCH 07/10] MIPS: BCM63XX: also register a fallback sprom for bcma\n\nSimilar to SSB, register a fallback sprom handler for BCMA.\n\nSigned-off-by: Jonas Gorski <jogo@openwrt.org>\n---\n arch/mips/bcm63xx/boards/Kconfig |  1 +\n arch/mips/bcm63xx/sprom.c        | 40 +++++++++++++++++++++++++++++++++++-----\n 2 files changed, 36 insertions(+), 5 deletions(-)\n\n--- a/arch/mips/bcm63xx/boards/Kconfig\n+++ b/arch/mips/bcm63xx/boards/Kconfig\n@@ -5,6 +5,7 @@ menu \"Board support\"\n config BOARD_BCM963XX\n \tbool \"Generic Broadcom 963xx boards\"\n \tselect SSB\n+\tselect BCMA\n \tdefault y\n \n endmenu\n--- a/arch/mips/bcm63xx/sprom.c\n+++ b/arch/mips/bcm63xx/sprom.c\n@@ -12,6 +12,7 @@\n #include <linux/string.h>\n #include <linux/platform_device.h>\n #include <linux/ssb/ssb.h>\n+#include <linux/bcma/bcma.h>\n #include <bcm63xx_fallback_sprom.h>\n #include <board_bcm963xx.h>\n \n@@ -21,7 +22,7 @@\n  * Register a sane SPROMv2 to make the on-board\n  * bcm4318 WLAN work\n  */\n-#ifdef CONFIG_SSB_PCIHOST\n+#if defined(CONFIG_SSB_PCIHOST) || defined(CONFIG_BCMA_HOST_PCI)\n static __initconst struct ssb_sprom bcm63xx_default_sprom = {\n \t.revision\t\t= 0x02,\n \t.board_rev\t\t= 0x17,\n@@ -43,7 +44,7 @@ static __initconst struct ssb_sprom bcm6\n \t.boardflags_hi\t\t= 0x0000,\n };\n \n-\n+#if defined (CONFIG_SSB_PCIHOST)\n static __initconst u16 bcm4306_sprom[] = {\n \t0x4001, 0x0000, 0x0453, 0x14e4, 0x4320, 0x8000, 0x0002, 0x0002,\n \t0x1000, 0x1800, 0x0000, 0x0000, 0xffff, 0xffff, 0xffff, 0xffff,\n@@ -158,10 +159,12 @@ static __initconst u16 bcm43222_sprom[]\n \t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n \t0xffff, 0xffff, 0xffff, 0x0008,\n };\n+#endif /* CONFIG_SSB_PCIHOST */\n \n static struct ssb_sprom bcm63xx_sprom;\n \n-int bcm63xx_get_fallback_sprom(struct ssb_bus *bus, struct ssb_sprom *out)\n+#if defined(CONFIG_SSB_PCIHOST)\n+int bcm63xx_get_fallback_ssb_sprom(struct ssb_bus *bus, struct ssb_sprom *out)\n {\n \tif (bus->bustype == SSB_BUSTYPE_PCI) {\n \t\tmemcpy(out, &bcm63xx_sprom, sizeof(struct ssb_sprom));\n@@ -171,6 +174,20 @@ int bcm63xx_get_fallback_sprom(struct ss\n \t\treturn -EINVAL;\n \t}\n }\n+#endif\n+\n+#if defined(CONFIG_BCMA_HOST_PCI)\n+int bcm63xx_get_fallback_bcma_sprom(struct bcma_bus *bus, struct ssb_sprom *out)\n+{\n+\tif (bus->hosttype == BCMA_HOSTTYPE_PCI) {\n+\t\tmemcpy(out, &bcm63xx_sprom, sizeof(struct ssb_sprom));\n+\t\treturn 0;\n+\t} else {\n+\t\tprintk(KERN_ERR PFX \"unable to fill SPROM for given bustype.\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+}\n+#endif\n \n /* FIXME: use lib_sprom after submission upstream */\n \n@@ -718,10 +735,11 @@ int __init bcm63xx_register_fallback_spr\n {\n \tint ret = 0;\n \n-#ifdef CONFIG_SSB_PCIHOST\n+#if defined(CONFIG_SSB_PCIHOST) || defined(CONFIG_BCMA_HOST_PCI)\n \tu16 size = 0;\n \n \tswitch (data->type) {\n+#if defined(CONFIG_SSB_PCIHOST)\n \tcase SPROM_BCM4306:\n \t\tmemcpy(&template_sprom, &bcm4306_sprom, sizeof(bcm4306_sprom));\n \t\tsize = ARRAY_SIZE(bcm4306_sprom);\n@@ -742,6 +760,7 @@ int __init bcm63xx_register_fallback_spr\n \t\tmemcpy(&template_sprom, &bcm43222_sprom, sizeof(bcm43222_sprom));\n \t\tsize = ARRAY_SIZE(bcm43222_sprom);\n \t\tbreak;\n+#endif\n \tcase SPROM_DEFAULT:\n \t\tmemcpy(&bcm63xx_sprom, &bcm63xx_default_sprom,\n \t\t       sizeof(bcm63xx_sprom));\n@@ -756,8 +775,19 @@ int __init bcm63xx_register_fallback_spr\n \tmemcpy(bcm63xx_sprom.il0mac, data->mac_addr, ETH_ALEN);\n \tmemcpy(bcm63xx_sprom.et0mac, data->mac_addr, ETH_ALEN);\n \tmemcpy(bcm63xx_sprom.et1mac, data->mac_addr, ETH_ALEN);\n+#endif /* defined(CONFIG_SSB_PCIHOST) || defined(CONFIG_BCMA_HOST_PCI) */\n+\n+#if defined(CONFIG_SSB_PCIHOST)\n+\tret = ssb_arch_register_fallback_sprom(&bcm63xx_get_fallback_ssb_sprom);\n+\tif (ret)\n+\t\treturn ret;\n+\n+#endif\n \n-\tret = ssb_arch_register_fallback_sprom(&bcm63xx_get_fallback_sprom);\n+#if defined(CONFIG_BCMA_HOST_PCI)\n+\tret = bcma_arch_register_fallback_sprom(bcm63xx_get_fallback_bcma_sprom);\n+\tif (ret)\n+\t\treturn ret;\n #endif\n \treturn ret;\n }\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/363-MIPS-BCM63XX-add-BCMA-based-sprom-templates.patch",
    "content": "From 27bf70e3fe797691b17df07ecbfaf9f5a4419f49 Mon Sep 17 00:00:00 2001\nFrom: Jonas Gorski <jogo@openwrt.org>\nDate: Wed, 30 Jul 2014 23:14:27 +0200\nSubject: [PATCH 08/10] MIPS: BCM63XX: add BCMA based sprom templates\n\nAdd fallback sproms for BCM4313, BCM43131, BCM43217, BCM43225, BCM43227,\nBCM43228, and BCM4331.\n\nSigned-off-by: Jonas Gorski <jogo@openwrt.org>\n---\n arch/mips/bcm63xx/sprom.c                          | 256 +++++++++++++++++++++\n .../asm/mach-bcm63xx/bcm63xx_fallback_sprom.h      |   8 +\n 2 files changed, 264 insertions(+)\n\n--- a/arch/mips/bcm63xx/sprom.c\n+++ b/arch/mips/bcm63xx/sprom.c\n@@ -161,6 +161,226 @@ static __initconst u16 bcm43222_sprom[]\n };\n #endif /* CONFIG_SSB_PCIHOST */\n \n+#if defined(CONFIG_BCMA_HOST_PCI)\n+static __initconst u16 bcm4313_sprom[] = {\n+\t0x2801, 0x0000, 0x0510, 0x14e4, 0x0078, 0xedbe, 0x0000, 0x2bc4,\n+\t0x2a64, 0x2964, 0x2c64, 0x3ce7, 0x46ff, 0x47ff, 0x0c00, 0x0820,\n+\t0x0030, 0x1002, 0x9f28, 0x5d44, 0x8080, 0x1d8f, 0x0032, 0x0100,\n+\t0xdf00, 0x71f5, 0x8400, 0x0083, 0x8500, 0x2010, 0x0001, 0x0000,\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n+\t0x0000, 0x0000, 0x1008, 0x0305, 0x0000, 0x0000, 0x0000, 0x0000,\n+\t0x4727, 0x8000, 0x0002, 0x0000, 0x1f30, 0x1800, 0x0000, 0x0000,\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n+\t0x5372, 0x1215, 0x2a00, 0x0800, 0x0800, 0x0000, 0x0000, 0x0000,\n+\t0x0000, 0x0000, 0x0003, 0xffff, 0x88ff, 0xffff, 0x0003, 0x0202,\n+\t0xffff, 0x0011, 0x007a, 0x0000, 0x0000, 0x0000, 0x0000, 0x0201,\n+\t0x0000, 0x7800, 0x7c0a, 0x0398, 0x0008, 0x0000, 0x0000, 0x0000,\n+\t0x0044, 0x1684, 0xfd0d, 0xff35, 0x0000, 0x0000, 0x0000, 0x0000,\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n+\t0x0048, 0xfed2, 0x15d9, 0xfac6, 0x0000, 0x0000, 0x0000, 0x0000,\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n+\t0x0000, 0x0000, 0x0000, 0x0008,\n+};\n+\n+static __initconst u16 bcm43131_sprom[] = {\n+\t0x2801, 0x0000, 0x05f7, 0x14e4, 0x0070, 0xedbe, 0x1c00, 0x2bc4,\n+\t0x2a64, 0x2964, 0x2c64, 0x3ce7, 0x46ff, 0x47ff, 0x0c00, 0x0820,\n+\t0x0030, 0x1002, 0x9f28, 0x5d44, 0x8080, 0x1d8f, 0x0032, 0x0100,\n+\t0xdf00, 0x71f5, 0x8400, 0x0083, 0x8500, 0x2010, 0x0001, 0x0000,\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n+\t0x0000, 0x0000, 0x1008, 0x0305, 0x0000, 0x0000, 0x0000, 0x0000,\n+\t0x43aa, 0x8000, 0x0002, 0x0000, 0x1f30, 0x1800, 0x0000, 0x0000,\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n+\t0x5372, 0x1280, 0x0200, 0x0000, 0x8800, 0x0000, 0x0000, 0x0000,\n+\t0x0000, 0x0000, 0x0003, 0xffff, 0x88ff, 0xffff, 0x0002, 0x0202,\n+\t0xffff, 0x0022, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0415,\n+\t0x0000, 0x7800, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n+\t0x204c, 0xfe96, 0x192c, 0xfa15, 0x0000, 0x0000, 0x0000, 0x0000,\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n+\t0x204c, 0xfe91, 0x1950, 0xfa0a, 0x0000, 0x0000, 0x0000, 0x0000,\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n+\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n+\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n+\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n+\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n+\t0x0000, 0x4444, 0x4444, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n+\t0x0000, 0x4444, 0x4444, 0x4444, 0x4444, 0x6666, 0x6666, 0x6666,\n+\t0x6666, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0xffff, 0xffff, 0xffff,\n+\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n+\t0xffff, 0xffff, 0xffff, 0x0008,\n+};\n+\n+static __initconst u16 bcm43217_sprom[] = {\n+\t0x2801, 0x0000, 0x05e9, 0x14e4, 0x0070, 0xedbe, 0x0000, 0x2bc4,\n+\t0x2a64, 0x2964, 0x2c64, 0x3ce7, 0x46ff, 0x47ff, 0x0c00, 0x0820,\n+\t0x0030, 0x1002, 0x9f28, 0x5d44, 0x8080, 0x1d8f, 0x0032, 0x0100,\n+\t0xdf00, 0x71f5, 0x8400, 0x0083, 0x8500, 0x2010, 0x0001, 0x0000,\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n+\t0x0000, 0x0000, 0x1008, 0x0305, 0x0000, 0x0000, 0x0000, 0x0000,\n+\t0x43a9, 0x8000, 0x0002, 0x0000, 0x1f30, 0x1800, 0x0000, 0x0000,\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n+\t0x5372, 0x1252, 0x0200, 0x0000, 0x9800, 0x0000, 0x0000, 0x0000,\n+\t0x0000, 0x0000, 0x0003, 0xffff, 0x88ff, 0xffff, 0x0003, 0x0202,\n+\t0xffff, 0x0033, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0415,\n+\t0x0000, 0x7800, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n+\t0x204c, 0xfe96, 0x192c, 0xfa15, 0x0000, 0x0000, 0x0000, 0x0000,\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n+\t0x204c, 0xfe91, 0x1950, 0xfa0a, 0x0000, 0x0000, 0x0000, 0x0000,\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n+\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n+\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n+\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n+\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n+\t0x0000, 0x4444, 0x4444, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n+\t0x0000, 0x4444, 0x4444, 0x4444, 0x4444, 0x6666, 0x6666, 0x6666,\n+\t0x6666, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0xffff, 0xffff, 0xffff,\n+\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n+\t0xffff, 0xffff, 0xffff, 0x7a08,\n+};\n+\n+static __initconst u16 bcm43225_sprom[] = {\n+\t0x2801, 0x0000, 0x04da, 0x14e4, 0x0078, 0xedbe, 0x0000, 0x2bc4,\n+\t0x2a64, 0x2964, 0x2c64, 0x3ce7, 0x46ff, 0x47ff, 0x0c00, 0x0820,\n+\t0x0030, 0x1002, 0x9f28, 0x5d44, 0x8080, 0x1d8f, 0x0032, 0x0100,\n+\t0xdf00, 0x71f5, 0x8400, 0x0083, 0x8500, 0x2010, 0x0001, 0xffff,\n+\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n+\t0xffff, 0xffff, 0x1008, 0x0005, 0xffff, 0xffff, 0xffff, 0xffff,\n+\t0x4357, 0x8000, 0x0002, 0x0000, 0x1f30, 0x1800, 0x0000, 0x0000,\n+\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n+\t0x5372, 0x1200, 0x0200, 0x0000, 0x1000, 0x0000, 0x0000, 0x0000,\n+\t0x0000, 0x0000, 0x0000, 0x88ff, 0xffff, 0xffff, 0x0303, 0x0202,\n+\t0xffff, 0x0033, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0x0325,\n+\t0xffff, 0x7800, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n+\t0x204e, 0xfead, 0x1611, 0xfa9a, 0xffff, 0xffff, 0xffff, 0xffff,\n+\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n+\t0x204e, 0xfec1, 0x1674, 0xfab2, 0xffff, 0xffff, 0xffff, 0xffff,\n+\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n+\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n+\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n+\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n+\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n+\t0x0000, 0x5555, 0x5555, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n+\t0x0000, 0x5555, 0x7555, 0x5555, 0x7555, 0x5555, 0x7555, 0x5555,\n+\t0x7555, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n+\t0x0000, 0x0000, 0x0000, 0x0002, 0x0000, 0xffff, 0xffff, 0xffff,\n+\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n+\t0xffff, 0xffff, 0xffff, 0x0008,\n+};\n+\n+static __initconst u16 bcm43227_sprom[] = {\n+\t0x2801, 0x0000, 0x0543, 0x14e4, 0x0070, 0xedbe, 0x0000, 0x2bc4,\n+\t0x2a64, 0x2964, 0x2c64, 0x3ce7, 0x46ff, 0x47ff, 0x0c00, 0x0820,\n+\t0x0030, 0x1002, 0x9f28, 0x5d44, 0x8080, 0x1d8f, 0x0032, 0x0100,\n+\t0xdf00, 0x71f5, 0x8400, 0x0083, 0x8500, 0x2010, 0x0001, 0x0000,\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n+\t0x0000, 0x0000, 0x1008, 0x0305, 0x0000, 0x0000, 0x0000, 0x0000,\n+\t0x4358, 0x8000, 0x0002, 0x0000, 0x1f30, 0x1800, 0x0000, 0x0000,\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n+\t0x5372, 0x1402, 0x0200, 0x0000, 0x0800, 0x0000, 0x0000, 0x0000,\n+\t0x0000, 0x0000, 0x0003, 0xffff, 0x88ff, 0xffff, 0x0003, 0x0202,\n+\t0xffff, 0x0033, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0415,\n+\t0x0000, 0x7800, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n+\t0x204c, 0xff36, 0x16d2, 0xfaae, 0x0000, 0x0000, 0x0000, 0x0000,\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n+\t0x204c, 0xfeca, 0x159b, 0xfa80, 0x0000, 0x0000, 0x0000, 0x0000,\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n+\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n+\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n+\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n+\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n+\t0x0000, 0x4444, 0x4444, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n+\t0x0000, 0x4444, 0x4444, 0x4444, 0x4444, 0x6666, 0x6666, 0x6666,\n+\t0x6666, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0xffff, 0xffff, 0xffff,\n+\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n+\t0xffff, 0xffff, 0xffff, 0x0008,\n+};\n+\n+static __initconst u16 bcm43228_sprom[] = {\n+\t0x2801, 0x0000, 0x0011, 0x1028, 0x0070, 0xedbe, 0x0000, 0x2bc4,\n+\t0x2a64, 0x2964, 0x2c64, 0x3ce7, 0x46ff, 0x47ff, 0x0c00, 0x0820,\n+\t0x0030, 0x1002, 0x9f28, 0x5d44, 0x8080, 0x1d8f, 0x0032, 0x0100,\n+\t0xdf00, 0x71f5, 0x8400, 0x0083, 0x8500, 0x2010, 0x0001, 0x0000,\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n+\t0x0000, 0x0000, 0x1008, 0x0305, 0x0000, 0x0000, 0x0000, 0x0000,\n+\t0x4359, 0x8000, 0x0002, 0x0000, 0x1f30, 0x1800, 0x0000, 0x0000,\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n+\t0x5372, 0x1203, 0x0200, 0x0000, 0x0800, 0x0000, 0x0000, 0x0000,\n+\t0x0000, 0x0000, 0x0003, 0xffff, 0x88ff, 0xffff, 0x0303, 0x0202,\n+\t0xffff, 0x0033, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0215,\n+\t0x0215, 0x7800, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n+\t0x204c, 0xff73, 0x1762, 0xfaa4, 0x3e34, 0x3434, 0xfea1, 0x154c,\n+\t0xfad0, 0xfea1, 0x144c, 0xfafb, 0xfe7b, 0x13fe, 0xfafc, 0x0000,\n+\t0x204c, 0xff41, 0x16a3, 0xfa8f, 0x3e34, 0x3434, 0xfe97, 0x1446,\n+\t0xfb05, 0xfe97, 0x1346, 0xfb32, 0xfeb9, 0x1516, 0xfaee, 0x0000,\n+\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n+\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n+\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n+\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n+\t0x0000, 0x4444, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n+\t0x0000, 0x4444, 0x4444, 0x4444, 0x4444, 0x8888, 0x8888, 0x8888,\n+\t0x8888, 0x0000, 0x0000, 0x0000, 0x0000, 0x3333, 0x3333, 0x3333,\n+\t0x3333, 0x0000, 0x0000, 0x0000, 0x0000, 0x3333, 0x3333, 0x3333,\n+\t0x3333, 0x0000, 0x0000, 0x0000, 0x0000, 0x3333, 0x3333, 0x3333,\n+\t0x3333, 0x0000, 0x0000, 0x0000, 0x0000, 0xffff, 0xffff, 0xffff,\n+\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n+\t0xffff, 0xffff, 0xffff, 0xf008,\n+};\n+\n+static __initconst u16 bcm4331_sprom[] = {\n+\t0x2801, 0x0000, 0x0525, 0x14e4, 0x0078, 0xedbe, 0x0000, 0x2bc4,\n+\t0x2a64, 0x2964, 0x2c64, 0x3ce7, 0x46ff, 0x47ff, 0x0c00, 0x0820,\n+\t0x0030, 0x1002, 0x9f28, 0x5d44, 0x8080, 0x1d8f, 0x0032, 0x0100,\n+\t0xdf00, 0x71f5, 0x8400, 0x0083, 0x8500, 0x2010, 0x0001, 0xffff,\n+\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n+\t0xffff, 0xffff, 0x1010, 0x0005, 0xffff, 0xffff, 0xffff, 0xffff,\n+\t0x4331, 0x8000, 0x0002, 0x0000, 0x1f30, 0x1800, 0x0000, 0x0000,\n+\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n+\t0x5372, 0x1104, 0x0200, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n+\t0x0000, 0x0000, 0x0000, 0xffff, 0x88ff, 0xffff, 0x0707, 0x0202,\n+\t0xff02, 0x0077, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0x0325,\n+\t0x0325, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n+\t0x2048, 0xfe56, 0x16f2, 0xfa44, 0x3e3c, 0x3c3c, 0xfe77, 0x1657,\n+\t0xfa75, 0xffff, 0xffff, 0xffff, 0xfe76, 0x15da, 0xfa85, 0x0000,\n+\t0x2048, 0xfe5c, 0x16b5, 0xfa56, 0x3e3c, 0x3c3c, 0xfe7c, 0x169d,\n+\t0xfa6b, 0xffff, 0xffff, 0xffff, 0xfe7a, 0x1597, 0xfa97, 0x0000,\n+\t0x2048, 0xfe68, 0x1734, 0xfa46, 0x3e3c, 0x3c3c, 0xfe7f, 0x15e4,\n+\t0xfa94, 0xffff, 0xffff, 0xffff, 0xfe7d, 0x1582, 0xfa9f, 0x0000,\n+\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n+\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0xffff, 0xffff, 0xffff, 0xffff,\n+\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n+\t0xffff, 0xffff, 0xffff, 0x0009,\n+};\n+\n+#endif  /* CONFIG_BCMA_HOST_PCI */\n+\n static struct ssb_sprom bcm63xx_sprom;\n \n #if defined(CONFIG_SSB_PCIHOST)\n@@ -761,6 +981,42 @@ int __init bcm63xx_register_fallback_spr\n \t\tsize = ARRAY_SIZE(bcm43222_sprom);\n \t\tbreak;\n #endif\n+#if defined(CONFIG_BCMA_HOST_PCI)\n+\tcase SPROM_BCM4313:\n+\t\tmemcpy(&template_sprom, &bcm4313_sprom,\n+                       sizeof(bcm4313_sprom));\n+\t\tsize = ARRAY_SIZE(bcm4313_sprom);\n+\t\tbreak;\n+\tcase SPROM_BCM43131:\n+\t\tmemcpy(&template_sprom, &bcm43131_sprom,\n+\t\t       sizeof(bcm43131_sprom));\n+\t\tsize = ARRAY_SIZE(bcm43131_sprom);\n+\t\tbreak;\n+\tcase SPROM_BCM43217:\n+\t\tmemcpy(&template_sprom, &bcm43217_sprom,\n+\t\t       sizeof(bcm43217_sprom));\n+\t\tsize = ARRAY_SIZE(bcm43217_sprom);\n+\t\tbreak;\n+\tcase SPROM_BCM43225:\n+\t\tmemcpy(&template_sprom, &bcm43225_sprom,\n+\t\t       sizeof(bcm43225_sprom));\n+\t\tsize = ARRAY_SIZE(bcm43225_sprom);\n+\t\tbreak;\n+\tcase SPROM_BCM43227:\n+\t\tmemcpy(&template_sprom, &bcm43227_sprom,\n+\t\t       sizeof(bcm43227_sprom));\n+\t\tsize = ARRAY_SIZE(bcm43227_sprom);\n+\t\tbreak;\n+\tcase SPROM_BCM43228:\n+\t\tmemcpy(&template_sprom, &bcm43228_sprom,\n+\t\t       sizeof(bcm43228_sprom));\n+\t\tsize = ARRAY_SIZE(bcm43228_sprom);\n+\t\tbreak;\n+\tcase SPROM_BCM4331:\n+\t\tmemcpy(&template_sprom, &bcm4331_sprom, sizeof(&bcm4331_sprom));\n+\t\tsize = ARRAY_SIZE(bcm4331_sprom);\n+\t\tbreak;\n+#endif\n \tcase SPROM_DEFAULT:\n \t\tmemcpy(&bcm63xx_sprom, &bcm63xx_default_sprom,\n \t\t       sizeof(bcm63xx_sprom));\n--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_fallback_sprom.h\n+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_fallback_sprom.h\n@@ -11,6 +11,14 @@ enum sprom_type {\n \tSPROM_BCM4321,\n \tSPROM_BCM4322,\n \tSPROM_BCM43222,\n+\t/* BCMA based */\n+\tSPROM_BCM4313,\n+\tSPROM_BCM43131,\n+\tSPROM_BCM43217,\n+\tSPROM_BCM43225,\n+\tSPROM_BCM43227,\n+\tSPROM_BCM43228,\n+\tSPROM_BCM4331,\n };\n \n struct fallback_sprom_data {\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/364-MIPS-BCM63XX-allow-board-files-to-provide-sprom-fixu.patch",
    "content": "From 8575548b08e33c9ff4fd540abec09dd177e33682 Mon Sep 17 00:00:00 2001\nFrom: Jonas Gorski <jogo@openwrt.org>\nDate: Thu, 31 Jul 2014 19:12:33 +0200\nSubject: [PATCH 09/10] MIPS: BCM63XX: allow board files to provide sprom\n fixups\n\nAllow board_info files to supply fixups for the base sproms to adapt\nthem to the actual used sprom contents in case they do not use the\ndefault ones.\n\nSigned-off-by: Jonas Gorski <jogo@openwrt.org>\n---\n arch/mips/bcm63xx/sprom.c                                  | 14 +++++++++++++-\n .../mips/include/asm/mach-bcm63xx/bcm63xx_fallback_sprom.h |  8 ++++++++\n 2 files changed, 21 insertions(+), 1 deletion(-)\n\n--- a/arch/mips/bcm63xx/sprom.c\n+++ b/arch/mips/bcm63xx/sprom.c\n@@ -947,6 +947,14 @@ static int sprom_extract(struct ssb_spro\n \treturn 0;\n }\n \n+void sprom_apply_fixups(u16 *sprom, struct sprom_fixup *fixups, int n)\n+{\n+\tunsigned int i;\n+\n+\tfor (i = 0; i < n; i++)\n+\t\tsprom[fixups[i].offset] = fixups[i].value;\n+}\n+\n static __initdata u16 template_sprom[220];\n #endif\n \n@@ -1025,8 +1033,12 @@ int __init bcm63xx_register_fallback_spr\n \t\treturn -EINVAL;\n \t}\n \n-\tif (size > 0)\n+\tif (size > 0) {\n+\t\tsprom_apply_fixups(template_sprom, data->board_fixups,\n+\t\t\t\t   data->num_board_fixups);\n+\n \t\tsprom_extract(&bcm63xx_sprom, template_sprom, size);\n+\t}\n \n \tmemcpy(bcm63xx_sprom.il0mac, data->mac_addr, ETH_ALEN);\n \tmemcpy(bcm63xx_sprom.et0mac, data->mac_addr, ETH_ALEN);\n--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_fallback_sprom.h\n+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_fallback_sprom.h\n@@ -21,9 +21,17 @@ enum sprom_type {\n \tSPROM_BCM4331,\n };\n \n+struct sprom_fixup {\n+\tu16 offset;\n+\tu16 value;\n+};\n+\n struct fallback_sprom_data {\n \tu8 mac_addr[ETH_ALEN];\n \tenum sprom_type type;\n+\n+\tstruct sprom_fixup *board_fixups;\n+\tunsigned int num_board_fixups;\n };\n \n int bcm63xx_register_fallback_sprom(struct fallback_sprom_data *data);\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/365-MIPS-BCM63XX-allow-setting-a-pci-bus-device-for-fall.patch",
    "content": "From f393eaacf178e7e8a61eb11a96edd7dfb35cb49d Mon Sep 17 00:00:00 2001\nFrom: Jonas Gorski <jogo@openwrt.org>\nDate: Thu, 31 Jul 2014 20:39:44 +0200\nSubject: [PATCH 10/10] MIPS: BCM63XX: allow setting a pci bus/device for\n fallback sprom\n\nWarn if the set pci bus/slot does not match the actual request.\n\nSigned-off-by: Jonas Gorski <jogo@openwrt.org>\n---\n arch/mips/bcm63xx/sprom.c                          | 31 ++++++++++++++++++----\n .../asm/mach-bcm63xx/bcm63xx_fallback_sprom.h      |  3 +++\n 2 files changed, 29 insertions(+), 5 deletions(-)\n\n--- a/arch/mips/bcm63xx/sprom.c\n+++ b/arch/mips/bcm63xx/sprom.c\n@@ -381,13 +381,25 @@ static __initconst u16 bcm4331_sprom[] =\n \n #endif  /* CONFIG_BCMA_HOST_PCI */\n \n-static struct ssb_sprom bcm63xx_sprom;\n+struct fallback_sprom_match {\n+\tu8 pci_bus;\n+\tu8 pci_dev;\n+\tstruct ssb_sprom sprom;\n+};\n+\n+static struct fallback_sprom_match fallback_sprom;\n \n #if defined(CONFIG_SSB_PCIHOST)\n int bcm63xx_get_fallback_ssb_sprom(struct ssb_bus *bus, struct ssb_sprom *out)\n {\n \tif (bus->bustype == SSB_BUSTYPE_PCI) {\n-\t\tmemcpy(out, &bcm63xx_sprom, sizeof(struct ssb_sprom));\n+\t\tif (bus->host_pci->bus->number != fallback_sprom.pci_bus ||\n+\t\t    PCI_SLOT(bus->host_pci->devfn) != fallback_sprom.pci_dev)\n+\t\t\tpr_warn(\"ssb_fallback_sprom: pci bus/device num mismatch: expected %i/%i, but got %i/%i\\n\",\n+\t\t\t\tfallback_sprom.pci_bus, fallback_sprom.pci_dev,\n+\t\t\t\tbus->host_pci->bus->number,\n+\t\t\t\tPCI_SLOT(bus->host_pci->devfn));\n+\t\tmemcpy(out, &fallback_sprom.sprom, sizeof(struct ssb_sprom));\n \t\treturn 0;\n \t} else {\n \t\tprintk(KERN_ERR PFX \"unable to fill SPROM for given bustype.\\n\");\n@@ -400,7 +412,13 @@ int bcm63xx_get_fallback_ssb_sprom(struc\n int bcm63xx_get_fallback_bcma_sprom(struct bcma_bus *bus, struct ssb_sprom *out)\n {\n \tif (bus->hosttype == BCMA_HOSTTYPE_PCI) {\n-\t\tmemcpy(out, &bcm63xx_sprom, sizeof(struct ssb_sprom));\n+\t\tif (bus->host_pci->bus->number != fallback_sprom.pci_bus ||\n+\t\t    PCI_SLOT(bus->host_pci->devfn) != fallback_sprom.pci_dev)\n+\t\t\tpr_warn(\"bcma_fallback_sprom: pci bus/device num mismatch: expected %i/%i, but got %i/%i\\n\",\n+\t\t\t\tfallback_sprom.pci_bus, fallback_sprom.pci_dev,\n+\t\t\t\tbus->host_pci->bus->number,\n+\t\t\t\tPCI_SLOT(bus->host_pci->devfn));\n+\t\tmemcpy(out, &fallback_sprom.sprom, sizeof(struct ssb_sprom));\n \t\treturn 0;\n \t} else {\n \t\tprintk(KERN_ERR PFX \"unable to fill SPROM for given bustype.\\n\");\n@@ -1026,8 +1044,8 @@ int __init bcm63xx_register_fallback_spr\n \t\tbreak;\n #endif\n \tcase SPROM_DEFAULT:\n-\t\tmemcpy(&bcm63xx_sprom, &bcm63xx_default_sprom,\n-\t\t       sizeof(bcm63xx_sprom));\n+\t\tmemcpy(&fallback_sprom.sprom, &bcm63xx_default_sprom,\n+\t\t       sizeof(bcm63xx_default_sprom));\n \t\tbreak;\n \tdefault:\n \t\treturn -EINVAL;\n@@ -1037,12 +1055,15 @@ int __init bcm63xx_register_fallback_spr\n \t\tsprom_apply_fixups(template_sprom, data->board_fixups,\n \t\t\t\t   data->num_board_fixups);\n \n-\t\tsprom_extract(&bcm63xx_sprom, template_sprom, size);\n+\t\tsprom_extract(&fallback_sprom.sprom, template_sprom, size);\n \t}\n \n-\tmemcpy(bcm63xx_sprom.il0mac, data->mac_addr, ETH_ALEN);\n-\tmemcpy(bcm63xx_sprom.et0mac, data->mac_addr, ETH_ALEN);\n-\tmemcpy(bcm63xx_sprom.et1mac, data->mac_addr, ETH_ALEN);\n+\tmemcpy(fallback_sprom.sprom.il0mac, data->mac_addr, ETH_ALEN);\n+\tmemcpy(fallback_sprom.sprom.et0mac, data->mac_addr, ETH_ALEN);\n+\tmemcpy(fallback_sprom.sprom.et1mac, data->mac_addr, ETH_ALEN);\n+\n+\tfallback_sprom.pci_bus = data->pci_bus;\n+\tfallback_sprom.pci_dev = data->pci_dev;\n #endif /* defined(CONFIG_SSB_PCIHOST) || defined(CONFIG_BCMA_HOST_PCI) */\n \n #if defined(CONFIG_SSB_PCIHOST)\n--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_fallback_sprom.h\n+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_fallback_sprom.h\n@@ -30,6 +30,9 @@ struct fallback_sprom_data {\n \tu8 mac_addr[ETH_ALEN];\n \tenum sprom_type type;\n \n+\tu8 pci_bus;\n+\tu8 pci_dev;\n+\n \tstruct sprom_fixup *board_fixups;\n \tunsigned int num_board_fixups;\n };\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/366-MIPS-BCM63XX-fallback-sprom-override-devid.patch",
    "content": "--- a/arch/mips/bcm63xx/sprom.c\n+++ b/arch/mips/bcm63xx/sprom.c\n@@ -384,6 +384,7 @@ static __initconst u16 bcm4331_sprom[] =\n struct fallback_sprom_match {\n \tu8 pci_bus;\n \tu8 pci_dev;\n+\tint override_devid;\n \tstruct ssb_sprom sprom;\n };\n \n@@ -399,6 +400,8 @@ int bcm63xx_get_fallback_ssb_sprom(struc\n \t\t\t\tfallback_sprom.pci_bus, fallback_sprom.pci_dev,\n \t\t\t\tbus->host_pci->bus->number,\n \t\t\t\tPCI_SLOT(bus->host_pci->devfn));\n+\t\tif (fallback_sprom.override_devid)\n+\t\t\tbus->host_pci->device = fallback_sprom.sprom.dev_id;\n \t\tmemcpy(out, &fallback_sprom.sprom, sizeof(struct ssb_sprom));\n \t\treturn 0;\n \t} else {\n@@ -418,6 +421,8 @@ int bcm63xx_get_fallback_bcma_sprom(stru\n \t\t\t\tfallback_sprom.pci_bus, fallback_sprom.pci_dev,\n \t\t\t\tbus->host_pci->bus->number,\n \t\t\t\tPCI_SLOT(bus->host_pci->devfn));\n+\t\tif (fallback_sprom.override_devid)\n+\t\t\tbus->host_pci->device = fallback_sprom.sprom.dev_id;\n \t\tmemcpy(out, &fallback_sprom.sprom, sizeof(struct ssb_sprom));\n \t\treturn 0;\n \t} else {\n@@ -965,6 +970,37 @@ static int sprom_extract(struct ssb_spro\n \treturn 0;\n }\n \n+int sprom_override_devid(struct fallback_sprom_data *data,\n+\t\t\t struct ssb_sprom *out, const u16 *in)\n+{\n+\tswitch (data->type) {\n+#if defined(CONFIG_SSB_PCIHOST)\n+\t\tcase SPROM_BCM4306:\n+\t\tcase SPROM_BCM4318:\n+\t\tcase SPROM_BCM4321:\n+\t\tcase SPROM_BCM4322:\n+\t\tcase SPROM_BCM43222:\n+\t\t\tSPEX(dev_id, SSB_SPROM1_PID, 0xFFFF, 0);\n+\t\t\treturn !!out->dev_id;\n+#endif /* CONFIG_SSB_PCIHOST */\n+#if defined(CONFIG_BCMA_HOST_PCI)\n+\t\tcase SPROM_BCM4313:\n+\t\tcase SPROM_BCM43131:\n+\t\tcase SPROM_BCM43217:\n+\t\tcase SPROM_BCM43225:\n+\t\tcase SPROM_BCM43227:\n+\t\tcase SPROM_BCM43228:\n+\t\tcase SPROM_BCM4331:\n+\t\t\tSPEX(dev_id, 0x0060, 0xFFFF, 0);\n+\t\t\treturn !!out->dev_id;\n+#endif /* CONFIG_BCMA_HOST_PCI */\n+\t\tcase SPROM_DEFAULT:\n+\t\t\treturn 0;\n+\t}\n+\n+\treturn 0;\n+}\n+\n void sprom_apply_fixups(u16 *sprom, struct sprom_fixup *fixups, int n)\n {\n \tunsigned int i;\n@@ -1056,6 +1092,11 @@ int __init bcm63xx_register_fallback_spr\n \t\t\t\t   data->num_board_fixups);\n \n \t\tsprom_extract(&fallback_sprom.sprom, template_sprom, size);\n+\n+\t\tfallback_sprom.override_devid = \n+\t\t\tsprom_override_devid(data, &fallback_sprom.sprom, template_sprom);\n+\t} else {\n+\t\tfallback_sprom.override_devid = 0;\n \t}\n \n \tmemcpy(fallback_sprom.sprom.il0mac, data->mac_addr, ETH_ALEN);\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/367-MIPS-BCM63XX-add-support-for-loading-DTB.patch",
    "content": "From 26546e5499d98616322fb3472b977e2e86603f3a Mon Sep 17 00:00:00 2001\nFrom: Jonas Gorski <jogo@openwrt.org>\nDate: Tue, 24 Jun 2014 10:57:51 +0200\nSubject: [PATCH 45/48] MIPS: BCM63XX: add support for loading DTB\n\nSigned-off-by: Jonas Gorski <jogo@openwrt.org>\n---\n arch/mips/bcm63xx/boards/Kconfig        |    4 ++++\n arch/mips/bcm63xx/boards/board_common.c |   34 +++++++++++++++++++++++++++++++\n arch/mips/bcm63xx/prom.c                |    6 ++++++\n 3 files changed, 44 insertions(+)\n\n--- a/arch/mips/bcm63xx/boards/Kconfig\n+++ b/arch/mips/bcm63xx/boards/Kconfig\n@@ -2,6 +2,10 @@\n menu \"Board support\"\n \tdepends on BCM63XX\n \n+config BOARD_BCM63XX_DT\n+\tbool \"Device Tree boards (experimential)\"\n+\tselect USE_OF\n+\n config BOARD_BCM963XX\n \tbool \"Generic Broadcom 963xx boards\"\n \tselect SSB\n--- a/arch/mips/bcm63xx/boards/board_common.c\n+++ b/arch/mips/bcm63xx/boards/board_common.c\n@@ -10,11 +10,14 @@\n #include <linux/init.h>\n #include <linux/kernel.h>\n #include <linux/string.h>\n+#include <linux/of_fdt.h>\n+#include <linux/of_platform.h>\n #include <linux/platform_device.h>\n #include <linux/ssb/ssb.h>\n #include <asm/addrspace.h>\n #include <asm/bootinfo.h>\n #include <asm/fw/cfe/cfe_api.h>\n+#include <asm/prom.h>\n #include <bcm63xx_board.h>\n #include <bcm63xx_cpu.h>\n #include <bcm63xx_dev_uart.h>\n@@ -125,8 +128,23 @@ void __init board_setup(void)\n \t/* make sure we're running on expected cpu */\n \tif (bcm63xx_get_cpu_id() != board.expected_cpu_id)\n \t\tpanic(\"unexpected CPU for bcm963xx board\");\n+\n+#if CONFIG_OF\n+\tif (initial_boot_params)\n+\t\t__dt_setup_arch(initial_boot_params);\n+#endif\n }\n \n+#if CONFIG_OF\n+void __init device_tree_init(void)\n+{\n+\tif (!initial_boot_params)\n+\t\treturn;\n+\n+\tunflatten_and_copy_device_tree();\n+}\n+#endif\n+\n static struct gpio_led_platform_data bcm63xx_led_data;\n \n static struct platform_device bcm63xx_gpio_leds = {\n@@ -135,6 +153,13 @@ static struct platform_device bcm63xx_gp\n \t.dev.platform_data\t= &bcm63xx_led_data,\n };\n \n+#if CONFIG_OF\n+static struct of_device_id of_ids[] = {\n+\t{ /* filled at runtime */ },\n+\t{ .compatible = \"simple-bus\" },\n+\t{ },\n+};\n+#endif\n /*\n  * third stage init callback, register all board devices.\n  */\n@@ -142,6 +167,15 @@ int __init board_register_devices(void)\n {\n \tint usbh_ports = 0;\n \n+#if CONFIG_OF\n+\tif (of_have_populated_dt()) {\n+\t\tsnprintf(of_ids[0].compatible, sizeof(of_ids[0].compatible),\n+\t\t\t \"brcm,bcm%x\", bcm63xx_get_cpu_id());\n+\n+\t\tof_platform_populate(NULL, of_ids, NULL, NULL);\n+\t}\n+#endif\n+\n \tif (board.has_uart0)\n \t\tbcm63xx_uart_register(0);\n \n--- a/arch/mips/bcm63xx/prom.c\n+++ b/arch/mips/bcm63xx/prom.c\n@@ -8,6 +8,7 @@\n \n #include <linux/init.h>\n #include <linux/memblock.h>\n+#include <linux/of_fdt.h>\n #include <linux/smp.h>\n #include <asm/bootinfo.h>\n #include <asm/bmips.h>\n@@ -23,6 +24,11 @@ void __init prom_init(void)\n {\n \tu32 reg, mask;\n \n+#if CONFIG_OF\n+\tif (fw_passed_dtb)\n+\t\tearly_init_dt_verify((void *)fw_passed_dtb);\n+#endif\n+\n \tbcm63xx_cpu_init();\n \n \t/* stop any running watchdog */\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/368-MIPS-BCM63XX-add-support-for-matching-the-board_info.patch",
    "content": "From 25bf2b5836c892f091651d8a3384c9c57ce1b400 Mon Sep 17 00:00:00 2001\nFrom: Jonas Gorski <jogo@openwrt.org>\nDate: Thu, 26 Jun 2014 12:51:00 +0200\nSubject: [PATCH 46/48] MIPS: BCM63XX: add support for matching the board_info\n by dtb\n\nAllow using the passed dtb's compatible property to match board_info\nstructs instead of nvram's boardname field, which is not unique anyway.\n\nSigned-off-by: Jonas Gorski <jogo@openwrt.org>\n---\n arch/mips/bcm63xx/boards/board_bcm963xx.c |   15 +++++++++++++++\n arch/mips/bcm63xx/boards/board_common.c   |   18 ++++++++++++++++++\n arch/mips/bcm63xx/boards/board_common.h   |    3 +++\n 3 files changed, 36 insertions(+)\n\n--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c\n+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c\n@@ -679,6 +679,10 @@ static const struct board_info __initcon\n #endif /* CONFIG_BCM63XX_CPU_6358 */\n };\n \n+static struct of_device_id const bcm963xx_boards_dt[] = {\n+\t{ },\n+};\n+\n /*\n  * early init callback, read nvram data from flash and checksum it\n  */\n@@ -690,6 +694,7 @@ void __init board_bcm963xx_init(void)\n \tchar *board_name = NULL;\n \tu32 val;\n \tstruct bcm_hcs *hcs;\n+\tconst struct of_device_id *board_match;\n \n \t/* read base address of boot chip select (0)\n \t * 6328/6362 do not have MPI but boot from a fixed address\n@@ -733,6 +738,16 @@ void __init board_bcm963xx_init(void)\n \t} else {\n \t\tboard_name = bcm63xx_nvram_get_name();\n \t}\n+\n+\t/* find board by compat */\n+\tboard_match = bcm63xx_match_board(bcm963xx_boards_dt);\n+\tif (board_match) {\n+\t\tboard_early_setup(board_match->data,\n+\t\t\t\t  bcm63xx_nvram_get_mac_address);\n+\n+\t\treturn;\n+\t}\n+\n \t/* find board by name */\n \tfor (i = 0; i < ARRAY_SIZE(bcm963xx_boards); i++) {\n \t\tif (strncmp(board_name, bcm963xx_boards[i]->name, 16))\n--- a/arch/mips/bcm63xx/boards/board_common.c\n+++ b/arch/mips/bcm63xx/boards/board_common.c\n@@ -239,3 +239,21 @@ int __init board_register_devices(void)\n \n \treturn 0;\n }\n+\n+const struct of_device_id * __init bcm63xx_match_board(const struct of_device_id *m)\n+{\n+\tconst struct of_device_id *match;\n+\tunsigned long dt_root;\n+\n+\tif (!IS_ENABLED(CONFIG_OF) || !initial_boot_params)\n+\t\treturn NULL;\n+\n+\tdt_root = of_get_flat_dt_root();\n+\n+\tfor (match = m; match->compatible[0]; match++) {\n+\t\tif (of_flat_dt_is_compatible(dt_root, match->compatible))\n+\t\t\treturn match;\n+\t}\n+\n+\treturn NULL;\n+}\n--- a/arch/mips/bcm63xx/boards/board_common.h\n+++ b/arch/mips/bcm63xx/boards/board_common.h\n@@ -1,11 +1,14 @@\n #ifndef __BOARD_COMMON_H\n #define __BOARD_COMMON_H\n \n+#include <linux/of.h>\n #include <board_bcm963xx.h>\n \n void board_early_setup(const struct board_info *board,\n \t\t       int (*get_mac_address)(u8 mac[ETH_ALEN]));\n \n+const struct of_device_id *bcm63xx_match_board(const struct of_device_id *);\n+\n #if defined(CONFIG_BOARD_BCM963XX)\n void board_bcm963xx_init(void);\n #else\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/371_add_of_node_available_by_alias.patch",
    "content": "--- a/arch/mips/bcm63xx/boards/board_common.c\n+++ b/arch/mips/bcm63xx/boards/board_common.c\n@@ -143,6 +143,18 @@ void __init device_tree_init(void)\n \n \tunflatten_and_copy_device_tree();\n }\n+\n+int board_of_device_present(const char *alias)\n+{\n+\tbool present;\n+\tstruct device_node *np;\n+\n+\tnp = of_find_node_by_path(alias);\n+\tpresent = of_device_is_available(np);\n+\tof_node_put(np);\n+\n+\treturn present;\n+}\n #endif\n \n static struct gpio_led_platform_data bcm63xx_led_data;\n--- a/arch/mips/bcm63xx/boards/board_common.h\n+++ b/arch/mips/bcm63xx/boards/board_common.h\n@@ -15,4 +15,13 @@ void board_bcm963xx_init(void);\n static inline void board_bcm963xx_init(void) { }\n #endif\n \n+#if defined(CONFIG_OF)\n+int board_of_device_present(const char *alias);\n+#else\n+static inline void board_of_device_present(const char *alias)\n+{\n+\treturn 0;\n+}\n+#endif\n+\n #endif /* __BOARD_COMMON_H */\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/372_dont_register_pflash_when_available_in_dtb.patch",
    "content": "--- a/arch/mips/bcm63xx/dev-flash.c\n+++ b/arch/mips/bcm63xx/dev-flash.c\n@@ -23,6 +23,8 @@\n #include <bcm63xx_regs.h>\n #include <bcm63xx_io.h>\n \n+#include \"boards/board_common.h\"\n+\n static int flash_type;\n \n static struct mtd_partition mtd_partitions[] = {\n@@ -179,6 +181,9 @@ int __init bcm63xx_flash_register(void)\n \n \tswitch (flash_type) {\n \tcase BCM63XX_FLASH_TYPE_PARALLEL:\n+\t\t/* don't register when already registered through from dtb */\n+\t\tif (board_of_device_present(\"pflash\"))\n+\t\t\treturn 0;\n \n \t\tif (!mtd_resources[0].start) {\n \t\t\t/* read base address of boot chip select (0) */\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/373-MIPS-BCM63XX-register-interrupt-controllers-through-.patch",
    "content": "From 8a0803979163c647736cb234ee1620c049c4915c Mon Sep 17 00:00:00 2001\nFrom: Jonas Gorski <jogo@openwrt.org>\nDate: Mon, 1 Dec 2014 00:20:07 +0100\nSubject: [PATCH 5/5] MIPS: BCM63XX: register interrupt controllers through DT\n\nSigned-off-by: Jonas Gorski <jogo@openwrt.org>\n---\n arch/mips/bcm63xx/irq.c |   12 ++++++++++++\n 1 file changed, 12 insertions(+)\n\n--- a/arch/mips/bcm63xx/irq.c\n+++ b/arch/mips/bcm63xx/irq.c\n@@ -14,6 +14,8 @@\n #include <linux/irqchip.h>\n #include <linux/irqchip/irq-bcm6345-ext.h>\n #include <linux/irqchip/irq-bcm6345-periph.h>\n+#include <linux/of.h>\n+#include <linux/of_fdt.h>\n #include <asm/irq_cpu.h>\n #include <asm/mipsregs.h>\n #include <bcm63xx_cpu.h>\n@@ -21,6 +23,9 @@\n #include <bcm63xx_io.h>\n #include <bcm63xx_irq.h>\n \n+IRQCHIP_DECLARE(mips_cpu_intc, \"mti,cpu-interrupt-controller\",\n+\t     mips_cpu_irq_of_init);\n+\n void __init arch_init_irq(void)\n {\n \tvoid __iomem *periph_bases[2];\n@@ -29,6 +34,13 @@ void __init arch_init_irq(void)\n \tint periph_irqs[2] = { 2, 3 };\n \tint ext_irqs[6];\n \n+#ifdef CONFIG_OF\n+\tif (initial_boot_params) {\n+\t\tirqchip_init();\n+\t\treturn;\n+\t}\n+#endif\n+\n \tperiph_bases[0] = (void __iomem *)bcm63xx_regset_address(RSET_PERF);\n \tperiph_bases[1] = (void __iomem *)bcm63xx_regset_address(RSET_PERF);\n \text_intc_bases[0] = (void __iomem *)bcm63xx_regset_address(RSET_PERF);\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/374-gpio-add-a-simple-GPIO-driver-for-bcm63xx.patch",
    "content": "From dbe94a8daaa63ef81b7414f2a17bca8e36dd6daa Mon Sep 17 00:00:00 2001\nFrom: Jonas Gorski <jogo@openwrt.org>\nDate: Fri, 20 Feb 2015 19:55:32 +0100\nSubject: [PATCH 1/6] gpio: add a simple GPIO driver for bcm63xx\n\n\nSigned-off-by: Jonas Gorski <jogo@openwrt.org>\n---\n drivers/gpio/Kconfig        |    8 +++\n drivers/gpio/Makefile       |    1 +\n drivers/gpio/gpio-bcm63xx.c |  135 +++++++++++++++++++++++++++++++++++++++++++\n 3 files changed, 131 insertions(+)\n create mode 100644 drivers/gpio/gpio-bcm63xx.c\n\n--- a/drivers/gpio/Kconfig\n+++ b/drivers/gpio/Kconfig\n@@ -193,6 +193,13 @@ config GPIO_BCM_XGS_IPROC\n \thelp\n \t  Say yes here to enable GPIO support for Broadcom XGS iProc SoCs.\n \n+config GPIO_BCM63XX\n+\tbool \"Broadcom BCM63XX GPIO\"\n+\tdepends on MIPS || COMPILE_TEST\n+\tselect GPIO_GENERIC\n+\thelp\n+\t  Turn on GPIO support for Broadcom BCM63XX xDSL chips.\n+\n config GPIO_BRCMSTB\n \ttristate \"BRCMSTB GPIO support\"\n \tdefault y if (ARCH_BRCMSTB || BMIPS_GENERIC)\n--- a/drivers/gpio/Makefile\n+++ b/drivers/gpio/Makefile\n@@ -38,6 +38,7 @@ obj-$(CONFIG_GPIO_ASPEED_SGPIO)\t\t+= gpio\n obj-$(CONFIG_GPIO_ATH79)\t\t+= gpio-ath79.o\n obj-$(CONFIG_GPIO_BCM_KONA)\t\t+= gpio-bcm-kona.o\n obj-$(CONFIG_GPIO_BCM_XGS_IPROC)\t+= gpio-xgs-iproc.o\n+obj-$(CONFIG_GPIO_BCM63XX)\t\t+= gpio-bcm63xx.o\n obj-$(CONFIG_GPIO_BD70528)\t\t+= gpio-bd70528.o\n obj-$(CONFIG_GPIO_BD71828)\t\t+= gpio-bd71828.o\n obj-$(CONFIG_GPIO_BD9571MWV)\t\t+= gpio-bd9571mwv.o\n--- /dev/null\n+++ b/drivers/gpio/gpio-bcm63xx.c\n@@ -0,0 +1,135 @@\n+/*\n+ * Driver for BCM63XX memory-mapped GPIO controllers, based on\n+ * Generic driver for memory-mapped GPIO controllers.\n+ *\n+ * Copyright 2008 MontaVista Software, Inc.\n+ * Copyright 2008,2010 Anton Vorontsov <cbouatmailru@gmail.com>\n+ * Copyright 2015 Jonas Gorski <jogo@openwrt.org>\n+ *\n+ * This program is free software; you can redistribute  it and/or modify it\n+ * under  the terms of  the GNU General  Public License as published by the\n+ * Free Software Foundation;  either version 2 of the  License, or (at your\n+ * option) any later version.\n+ */\n+\n+#include <linux/init.h>\n+#include <linux/err.h>\n+#include <linux/bug.h>\n+#include <linux/kernel.h>\n+#include <linux/module.h>\n+#include <linux/spinlock.h>\n+#include <linux/compiler.h>\n+#include <linux/types.h>\n+#include <linux/errno.h>\n+#include <linux/log2.h>\n+#include <linux/ioport.h>\n+#include <linux/io.h>\n+#include <linux/gpio.h>\n+#include <linux/gpio/driver.h>\n+#include <linux/slab.h>\n+#include <linux/platform_device.h>\n+#include <linux/mod_devicetable.h>\n+#include <linux/of.h>\n+#include <linux/of_irq.h>\n+#include <linux/of_gpio.h>\n+\n+static int bcm63xx_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)\n+{\n+\tchar irq_name[7]; /* \"gpioXX\" */\n+\n+\tsprintf(irq_name, \"gpio%d\", gpio);\n+\treturn of_irq_get_byname(chip->of_node, irq_name);\n+}\n+\n+static int bcm63xx_gpio_probe(struct platform_device *pdev)\n+{\n+\tstruct device *dev = &pdev->dev;\n+\tstruct resource *dat_r, *dirout_r;\n+\tvoid __iomem *dat;\n+\tvoid __iomem *dirout;\n+\tunsigned long sz;\n+\tint err;\n+\tstruct gpio_chip *gc;\n+\tstruct bgpio_pdata *pdata = dev_get_platdata(dev);\n+\n+\tdirout_r = platform_get_resource(pdev, IORESOURCE_MEM, 0);\n+\tdat_r = platform_get_resource(pdev, IORESOURCE_MEM, 1);\n+\tif (!dat_r || !dirout_r)\n+\t\treturn -EINVAL;\n+\n+\tif (resource_size(dat_r) != resource_size(dirout_r))\n+\t\treturn -EINVAL;\n+\n+\tsz = resource_size(dat_r);\n+\n+\tdat = devm_ioremap_resource(dev, dat_r);\n+\tif (IS_ERR(dat))\n+\t\treturn PTR_ERR(dat);\n+\n+\tdirout = devm_ioremap_resource(dev, dirout_r);\n+\tif (IS_ERR(dirout))\n+\t\treturn PTR_ERR(dirout);\n+\n+\tgc = devm_kzalloc(&pdev->dev, sizeof(*gc), GFP_KERNEL);\n+\tif (!gc)\n+\t\treturn -ENOMEM;\n+\n+\terr = bgpio_init(gc, dev, sz, dat, NULL, NULL, dirout, NULL,\n+\t\t\t BGPIOF_BIG_ENDIAN_BYTE_ORDER);\n+\tif (err)\n+\t\treturn err;\n+\n+\tplatform_set_drvdata(pdev, gc);\n+\n+\tif (dev->of_node) {\n+\t\tint id = of_alias_get_id(dev->of_node, \"gpio\");\n+\t\tu32 ngpios;\n+\n+\t\tif (id >= 0)\n+\t\t\tgc->label = devm_kasprintf(dev, GFP_KERNEL,\n+\t\t\t\t\t\t   \"bcm63xx-gpio.%d\", id);\n+\n+\t\tif (!of_property_read_u32(dev->of_node, \"ngpios\", &ngpios))\n+\t\t\tgc->ngpio = ngpios;\n+\n+\t\tif (of_get_property(dev->of_node, \"interrupt-names\", NULL))\n+\t\t\tgc->to_irq = bcm63xx_gpio_to_irq;\n+\n+\t} else if (pdata) {\n+\t\tgc->base = pdata->base;\n+\t\tif (pdata->ngpio > 0)\n+\t\t\tgc->ngpio = pdata->ngpio;\n+\t}\n+\n+\treturn gpiochip_add(gc);\n+}\n+\n+static int bcm63xx_gpio_remove(struct platform_device *pdev)\n+{\n+\tstruct gpio_chip *gc = platform_get_drvdata(pdev);\n+\n+\tgpiochip_remove(gc);\n+\treturn 0;\n+}\n+\n+#ifdef CONFIG_OF\n+static struct of_device_id bcm63xx_gpio_of_match[] = {\n+\t{ .compatible = \"brcm,bcm6345-gpio\" },\n+\t{ },\n+};\n+#endif\n+\n+static struct platform_driver bcm63xx_gpio_driver = {\n+\t.probe = bcm63xx_gpio_probe,\n+\t.remove = bcm63xx_gpio_remove,\n+\t.driver = {\n+\t\t.name = \"bcm63xx-gpio\",\n+\t\t.of_match_table = of_match_ptr(bcm63xx_gpio_of_match),\n+\t},\n+};\n+\n+module_platform_driver(bcm63xx_gpio_driver);\n+\n+MODULE_DESCRIPTION(\"Driver for BCM63XX memory-mapped GPIO controllers\");\n+MODULE_AUTHOR(\"Jonas Gorski <jogo@openwrt.org>\");\n+MODULE_LICENSE(\"GPL\");\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/375-MIPS-BCM63XX-switch-to-new-gpio-driver.patch",
    "content": "From 302f69453721e5ee19f583339a3a646821d4a173 Mon Sep 17 00:00:00 2001\nFrom: Jonas Gorski <jogo@openwrt.org>\nDate: Fri, 20 Feb 2015 23:58:54 +0100\nSubject: [PATCH 2/6] MIPS: BCM63XX: switch to new gpio driver\n\nSigned-off-by: Jonas Gorski <jogo@openwrt.org>\n---\n arch/mips/bcm63xx/boards/board_common.c |    2 +\n arch/mips/bcm63xx/gpio.c  | 145 ++++++++++------------------------------------\n arch/mips/bcm63xx/setup.c |   3 -\n 3 files changed, 32 insertions(+), 118 deletions(-)\n\n--- a/arch/mips/bcm63xx/boards/board_common.c\n+++ b/arch/mips/bcm63xx/boards/board_common.c\n@@ -188,6 +188,8 @@ int __init board_register_devices(void)\n \t}\n #endif\n \n+\tbcm63xx_gpio_init();\n+\n \tif (board.has_uart0)\n \t\tbcm63xx_uart_register(0);\n \n--- a/arch/mips/bcm63xx/gpio.c\n+++ b/arch/mips/bcm63xx/gpio.c\n@@ -5,147 +5,62 @@\n  *\n  * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>\n  * Copyright (C) 2008-2011 Florian Fainelli <florian@openwrt.org>\n+ * Copyright (C) Jonas Gorski <jogo@openwrt.org>\n  */\n \n #include <linux/kernel.h>\n #include <linux/init.h>\n-#include <linux/spinlock.h>\n #include <linux/platform_device.h>\n #include <linux/gpio/driver.h>\n \n #include <bcm63xx_cpu.h>\n #include <bcm63xx_gpio.h>\n-#include <bcm63xx_io.h>\n #include <bcm63xx_regs.h>\n \n-static u32 gpio_out_low_reg;\n-\n-static void bcm63xx_gpio_out_low_reg_init(void)\n+static void __init bcm63xx_gpio_init_one(int id, int dir, int data, int ngpio)\n {\n-\tswitch (bcm63xx_get_cpu_id()) {\n-\tcase BCM6345_CPU_ID:\n-\t\tgpio_out_low_reg = GPIO_DATA_LO_REG_6345;\n-\t\tbreak;\n-\tdefault:\n-\t\tgpio_out_low_reg = GPIO_DATA_LO_REG;\n-\t\tbreak;\n-\t}\n-}\n-\n-static DEFINE_SPINLOCK(bcm63xx_gpio_lock);\n-static u32 gpio_out_low, gpio_out_high;\n+\tstruct resource res[2];\n+\tstruct bgpio_pdata pdata;\n \n-static void bcm63xx_gpio_set(struct gpio_chip *chip,\n-\t\t\t     unsigned gpio, int val)\n-{\n-\tu32 reg;\n-\tu32 mask;\n-\tu32 *v;\n-\tunsigned long flags;\n-\n-\tif (gpio >= chip->ngpio)\n-\t\tBUG();\n-\n-\tif (gpio < 32) {\n-\t\treg = gpio_out_low_reg;\n-\t\tmask = 1 << gpio;\n-\t\tv = &gpio_out_low;\n-\t} else {\n-\t\treg = GPIO_DATA_HI_REG;\n-\t\tmask = 1 << (gpio - 32);\n-\t\tv = &gpio_out_high;\n-\t}\n-\n-\tspin_lock_irqsave(&bcm63xx_gpio_lock, flags);\n-\tif (val)\n-\t\t*v |= mask;\n-\telse\n-\t\t*v &= ~mask;\n-\tbcm_gpio_writel(*v, reg);\n-\tspin_unlock_irqrestore(&bcm63xx_gpio_lock, flags);\n-}\n+\tmemset(res, 0, sizeof(res));\n+\tmemset(&pdata, 0, sizeof(pdata));\n \n-static int bcm63xx_gpio_get(struct gpio_chip *chip, unsigned gpio)\n-{\n-\tu32 reg;\n-\tu32 mask;\n+\tres[0].flags = IORESOURCE_MEM;\n+\tres[0].start = bcm63xx_regset_address(RSET_GPIO);\n+\tres[0].start += dir;\n \n-\tif (gpio >= chip->ngpio)\n-\t\tBUG();\n+\tres[0].end = res[0].start + 3;\n \n-\tif (gpio < 32) {\n-\t\treg = gpio_out_low_reg;\n-\t\tmask = 1 << gpio;\n-\t} else {\n-\t\treg = GPIO_DATA_HI_REG;\n-\t\tmask = 1 << (gpio - 32);\n-\t}\n+\tres[1].flags = IORESOURCE_MEM;\n+\tres[1].start = bcm63xx_regset_address(RSET_GPIO);\n+\tres[1].start += data;\n \n-\treturn !!(bcm_gpio_readl(reg) & mask);\n-}\n+\tres[1].end = res[1].start + 3;\n \n-static int bcm63xx_gpio_set_direction(struct gpio_chip *chip,\n-\t\t\t\t      unsigned gpio, int dir)\n-{\n-\tu32 reg;\n-\tu32 mask;\n-\tu32 tmp;\n-\tunsigned long flags;\n-\n-\tif (gpio >= chip->ngpio)\n-\t\tBUG();\n-\n-\tif (gpio < 32) {\n-\t\treg = GPIO_CTL_LO_REG;\n-\t\tmask = 1 << gpio;\n-\t} else {\n-\t\treg = GPIO_CTL_HI_REG;\n-\t\tmask = 1 << (gpio - 32);\n-\t}\n-\n-\tspin_lock_irqsave(&bcm63xx_gpio_lock, flags);\n-\ttmp = bcm_gpio_readl(reg);\n-\tif (dir == BCM63XX_GPIO_DIR_IN)\n-\t\ttmp &= ~mask;\n-\telse\n-\t\ttmp |= mask;\n-\tbcm_gpio_writel(tmp, reg);\n-\tspin_unlock_irqrestore(&bcm63xx_gpio_lock, flags);\n+\tpdata.base = id * 32;\n+\tpdata.ngpio = ngpio;\n \n-\treturn 0;\n+\tplatform_device_register_resndata(NULL, \"bcm63xx-gpio\", id, res, 2,\n+\t\t\t\t\t  &pdata, sizeof(pdata));\n }\n \n-static int bcm63xx_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)\n+int __init bcm63xx_gpio_init(void)\n {\n-\treturn bcm63xx_gpio_set_direction(chip, gpio, BCM63XX_GPIO_DIR_IN);\n-}\n+\tint ngpio = bcm63xx_gpio_count();\n+\tint data_low_reg;\n \n-static int bcm63xx_gpio_direction_output(struct gpio_chip *chip,\n-\t\t\t\t\t unsigned gpio, int value)\n-{\n-\tbcm63xx_gpio_set(chip, gpio, value);\n-\treturn bcm63xx_gpio_set_direction(chip, gpio, BCM63XX_GPIO_DIR_OUT);\n-}\n+\tif (BCMCPU_IS_6345())\n+\t\tdata_low_reg = GPIO_DATA_LO_REG_6345;\n+\telse\n+\t\tdata_low_reg = GPIO_DATA_LO_REG;\n \n+\tbcm63xx_gpio_init_one(0, GPIO_CTL_LO_REG, data_low_reg, min(ngpio, 32));\n \n-static struct gpio_chip bcm63xx_gpio_chip = {\n-\t.label\t\t\t= \"bcm63xx-gpio\",\n-\t.direction_input\t= bcm63xx_gpio_direction_input,\n-\t.direction_output\t= bcm63xx_gpio_direction_output,\n-\t.get\t\t\t= bcm63xx_gpio_get,\n-\t.set\t\t\t= bcm63xx_gpio_set,\n-\t.base\t\t\t= 0,\n-};\n+\tif (ngpio <= 32)\n+\t\treturn 0;\n \n-int __init bcm63xx_gpio_init(void)\n-{\n-\tbcm63xx_gpio_out_low_reg_init();\n+\tbcm63xx_gpio_init_one(1, GPIO_CTL_HI_REG, GPIO_DATA_HI_REG, ngpio - 32);\n \n-\tgpio_out_low = bcm_gpio_readl(gpio_out_low_reg);\n-\tif (!BCMCPU_IS_6345())\n-\t\tgpio_out_high = bcm_gpio_readl(GPIO_DATA_HI_REG);\n-\tbcm63xx_gpio_chip.ngpio = bcm63xx_gpio_count();\n-\tpr_info(\"registering %d GPIOs\\n\", bcm63xx_gpio_chip.ngpio);\n+\treturn 0;\n \n-\treturn gpiochip_add_data(&bcm63xx_gpio_chip, NULL);\n }\n--- a/arch/mips/bcm63xx/setup.c\n+++ b/arch/mips/bcm63xx/setup.c\n@@ -164,9 +164,6 @@ void __init plat_mem_setup(void)\n \n int __init bcm63xx_register_devices(void)\n {\n-\t/* register gpiochip */\n-\tbcm63xx_gpio_init();\n-\n \treturn board_register_devices();\n }\n \n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/377-MIPS-BCM63XX-register-lookup-for-ephy-reset-gpio.patch",
    "content": "From d13bdf92ec885105cf107183f8464c40e5f3b93b Mon Sep 17 00:00:00 2001\nFrom: Jonas Gorski <jogo@openwrt.org>\nDate: Sat, 21 Feb 2015 17:21:59 +0100\nSubject: [PATCH 4/6] MIPS: BCM63XX: register lookup for ephy-reset gpio\n\n\nSigned-off-by: Jonas Gorski <jogo@openwrt.org>\n---\n arch/mips/bcm63xx/boards/board_bcm963xx.c          |    2 +-\n arch/mips/bcm63xx/boards/board_common.c            |    7 +++--\n arch/mips/bcm63xx/gpio.c                           |   32 ++++++++++++++++++++\n arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h  |    2 ++\n .../mips/include/asm/mach-bcm63xx/board_bcm963xx.h |    5 +--\n 5 files changed, 42 insertions(+), 6 deletions(-)\n\n--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c\n+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c\n@@ -32,7 +32,7 @@ static struct board_info __initdata boar\n \t.expected_cpu_id = 0x3368,\n \n \t.ephy_reset_gpio = 36,\n-\t.ephy_reset_gpio_flags = GPIOF_INIT_HIGH,\n+\t.ephy_reset_gpio_flags = GPIO_ACTIVE_LOW,\n \t.has_pci = 1,\n \t.has_uart0 = 1,\n \t.has_uart1 = 1,\n--- a/arch/mips/bcm63xx/boards/board_common.c\n+++ b/arch/mips/bcm63xx/boards/board_common.c\n@@ -247,9 +247,10 @@ int __init board_register_devices(void)\n \n \tplatform_device_register(&bcm63xx_gpio_leds);\n \n-\tif (board.ephy_reset_gpio && board.ephy_reset_gpio_flags)\n-\t\tgpio_request_one(board.ephy_reset_gpio,\n-\t\t\t\tboard.ephy_reset_gpio_flags, \"ephy-reset\");\n+\tif (board.ephy_reset_gpio && board.ephy_reset_gpio_flags) {\n+\t\tbcm63xx_gpio_ephy_reset(board.ephy_reset_gpio,\n+\t\t\t\t\tboard.ephy_reset_gpio_flags);\n+\t}\n \n \treturn 0;\n }\n--- a/arch/mips/bcm63xx/gpio.c\n+++ b/arch/mips/bcm63xx/gpio.c\n@@ -8,15 +8,23 @@\n  * Copyright (C) Jonas Gorski <jogo@openwrt.org>\n  */\n \n+#include <asm/addrspace.h>\n+\n #include <linux/kernel.h>\n #include <linux/init.h>\n #include <linux/platform_device.h>\n #include <linux/gpio/driver.h>\n+#include <linux/gpio/machine.h>\n \n #include <bcm63xx_cpu.h>\n #include <bcm63xx_gpio.h>\n #include <bcm63xx_regs.h>\n \n+static const char * const gpio_chip_labels[] = {\n+\t\"bcm63xx-gpio.0\",\n+\t\"bcm63xx-gpio.1\",\n+};\n+\n static void __init bcm63xx_gpio_init_one(int id, int dir, int data, int ngpio)\n {\n \tstruct resource res[2];\n@@ -64,3 +72,25 @@ int __init bcm63xx_gpio_init(void)\n \treturn 0;\n \n }\n+\n+static struct gpiod_lookup_table ephy_reset = {\n+\t.dev_id = \"bcm63xx_enet-0\",\n+\t.table = {\n+\t\t{ /* filled at runtime */ },\n+\t\t{ },\n+\t},\n+};\n+\n+\n+void bcm63xx_gpio_ephy_reset(int hw_gpio, enum gpio_lookup_flags flags)\n+{\n+\tif (ephy_reset.table[0].key)\n+\t\treturn;\n+\n+\tephy_reset.table[0].key = gpio_chip_labels[hw_gpio / 32];\n+\tephy_reset.table[0].chip_hwnum = hw_gpio % 32;\n+\tephy_reset.table[0].con_id = \"reset\";\n+\tephy_reset.table[0].flags = flags;\n+\n+\tgpiod_add_lookup_table(&ephy_reset);\n+}\n--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h\n+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h\n@@ -3,9 +3,11 @@\n #define BCM63XX_GPIO_H\n \n #include <linux/init.h>\n+#include <linux/gpio/machine.h>\n #include <bcm63xx_cpu.h>\n \n int __init bcm63xx_gpio_init(void);\n+void bcm63xx_gpio_ephy_reset(int hw_gpio, enum gpio_lookup_flags flags);\n \n static inline unsigned long bcm63xx_gpio_count(void)\n {\n--- a/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h\n+++ b/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h\n@@ -4,6 +4,7 @@\n \n #include <linux/types.h>\n #include <linux/gpio.h>\n+#include <linux/gpio/machine.h>\n #include <linux/leds.h>\n #include <bcm63xx_dev_enet.h>\n #include <bcm63xx_dev_usb_usbd.h>\n@@ -50,8 +51,8 @@ struct board_info {\n \t/* External PHY reset GPIO */\n \tunsigned int ephy_reset_gpio;\n \n-\t/* External PHY reset GPIO flags from gpio.h */\n-\tunsigned long ephy_reset_gpio_flags;\n+\t/* External PHY reset GPIO flags from gpio/machine.h */\n+\tenum gpio_lookup_flags ephy_reset_gpio_flags;\n \n \t/* fallback sprom config */\n \tstruct fallback_sprom_data fallback_sprom;\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/378-MIPS-BCM63XX-do-not-register-gpio-controller-if-pres.patch",
    "content": "From e55892aac9d5508a000647ca66f0e678e02be3bb Mon Sep 17 00:00:00 2001\nFrom: Jonas Gorski <jogo@openwrt.org>\nDate: Sat, 21 Feb 2015 17:26:50 +0100\nSubject: [PATCH 5/6] MIPS: BCM63XX: do not register gpio-controller if\npresent in dtb\n\nSigned-off-by: Jonas Gorski <jogo@openwrt.org>\n---\n arch/mips/bcm63xx/gpio.c |   7 +++++--\n 1 file changed, 5 insertions(+), 2 deletions(-)\n\n--- a/arch/mips/bcm63xx/gpio.c\n+++ b/arch/mips/bcm63xx/gpio.c\n@@ -20,6 +20,8 @@\n #include <bcm63xx_gpio.h>\n #include <bcm63xx_regs.h>\n \n+#include \"boards/board_common.h\"\n+\n static const char * const gpio_chip_labels[] = {\n \t\"bcm63xx-gpio.0\",\n \t\"bcm63xx-gpio.1\",\n@@ -48,8 +50,10 @@ static void __init bcm63xx_gpio_init_one\n \tpdata.base = id * 32;\n \tpdata.ngpio = ngpio;\n \n-\tplatform_device_register_resndata(NULL, \"bcm63xx-gpio\", id, res, 2,\n-\t\t\t\t\t  &pdata, sizeof(pdata));\n+\tif (!board_of_device_present(\"gpio0\") &&\n+\t    !board_of_device_present(\"pinctrl\"))\n+\t\tplatform_device_register_resndata(NULL, \"bcm63xx-gpio\", id, res,\n+\t\t\t\t\t\t  2, &pdata, sizeof(pdata));\n }\n \n int __init bcm63xx_gpio_init(void)\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/379-MIPS-BCM63XX-provide-a-gpio-lookup-for-the-pcmcia-re.patch",
    "content": "From 1647cccc871bf43876c3df9852869680880d054c Mon Sep 17 00:00:00 2001\nFrom: Jonas Gorski <jogo@openwrt.org>\nDate: Wed, 25 Mar 2015 13:52:02 +0100\nSubject: [PATCH 1/2] MIPS: BCM63XX: provide a gpio lookup for the pcmcia\n ready gpio\n\nTo prepare for a time when gpiobases don't need to be fixed anymore.\n\nSigned-off-by: Jonas Gorski <jogo@openwrt.org>\n---\n arch/mips/bcm63xx/dev-pcmcia.c |   13 +++++++++++++\n 1 file changed, 13 insertions(+)\n\n--- a/arch/mips/bcm63xx/dev-pcmcia.c\n+++ b/arch/mips/bcm63xx/dev-pcmcia.c\n@@ -10,6 +10,7 @@\n #include <linux/kernel.h>\n #include <asm/bootinfo.h>\n #include <linux/platform_device.h>\n+#include <linux/gpio/machine.h>\n #include <bcm63xx_cs.h>\n #include <bcm63xx_cpu.h>\n #include <bcm63xx_dev_pcmcia.h>\n@@ -101,6 +102,14 @@ static const struct {\n \t},\n };\n \n+static struct gpiod_lookup_table pcmcia_gpios_table = {\n+\t.dev_id = \"bcm63xx_pcmcia.0\",\n+\t.table = {\n+\t\tGPIO_LOOKUP(\"bcm63xx-gpio.0\", 0, \"ready\", GPIO_ACTIVE_HIGH),\n+\t\t{ },\n+\t},\n+};\n+\n int __init bcm63xx_pcmcia_register(void)\n {\n \tint ret, i;\n@@ -112,16 +121,20 @@ int __init bcm63xx_pcmcia_register(void)\n \tswitch (bcm63xx_get_cpu_id()) {\n \tcase BCM6348_CPU_ID:\n \t\tpd.ready_gpio = 22;\n+\t\tpcmcia_gpios_table.table[0].chip_hwnum = 22;\n \t\tbreak;\n \n \tcase BCM6358_CPU_ID:\n \t\tpd.ready_gpio = 18;\n+\t\tpcmcia_gpios_table.table[0].chip_hwnum = 18;\n \t\tbreak;\n \n \tdefault:\n \t\treturn -ENODEV;\n \t}\n \n+\tgpiod_add_lookup_table(&pcmcia_gpios_table);\n+\n \tpcmcia_resources[0].start = bcm63xx_regset_address(RSET_PCMCIA);\n \tpcmcia_resources[0].end = pcmcia_resources[0].start +\n \t\tRSET_PCMCIA_SIZE - 1;\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/380-pcmcia-bcm63xx_pmcia-use-the-new-named-gpio.patch",
    "content": "From c4e04f1c54928a49b227a5420d38b18226838775 Mon Sep 17 00:00:00 2001\nFrom: Jonas Gorski <jogo@openwrt.org>\nDate: Wed, 25 Mar 2015 13:54:56 +0100\nSubject: [PATCH 2/2] pcmcia: bcm63xx_pmcia: use the new named gpio\n\nUse the new named gpio instead of relying on the hardware gpio numbers\nmatching the virtual gpio numbers.\n\nSigned-off-by: Jonas Gorski <jogo@openwrt.org>\n---\n drivers/pcmcia/bcm63xx_pcmcia.c |    9 ++++++++-\n drivers/pcmcia/bcm63xx_pcmcia.h |    4 ++++\n 2 files changed, 12 insertions(+), 1 deletion(-)\n\n--- a/drivers/pcmcia/bcm63xx_pcmcia.c\n+++ b/drivers/pcmcia/bcm63xx_pcmcia.c\n@@ -237,7 +237,7 @@ static unsigned int __get_socket_status(\n \t\tstat |= SS_XVCARD;\n \tstat |= SS_POWERON;\n \n-\tif (gpio_get_value(skt->pd->ready_gpio))\n+\tif (gpiod_get_value(skt->ready_gpio))\n \t\tstat |= SS_READY;\n \n \treturn stat;\n@@ -373,6 +373,13 @@ static int bcm63xx_drv_pcmcia_probe(stru\n \t\tgoto err;\n \t}\n \n+\t/* get ready gpio */\n+\tskt->ready_gpio = devm_gpiod_get(&pdev->dev, \"ready\", GPIOD_IN);\n+\tif (IS_ERR(skt->ready_gpio)) {\n+\t\tret = PTR_ERR(skt->ready_gpio);\n+\t\tgoto err;\n+\t}\n+\n \t/* resources are static */\n \tsock->resource_ops = &pccard_static_ops;\n \tsock->ops = &bcm63xx_pcmcia_operations;\n--- a/drivers/pcmcia/bcm63xx_pcmcia.h\n+++ b/drivers/pcmcia/bcm63xx_pcmcia.h\n@@ -4,6 +4,7 @@\n \n #include <linux/types.h>\n #include <linux/timer.h>\n+#include <linux/gpio/consumer.h>\n #include <pcmcia/ss.h>\n #include <bcm63xx_dev_pcmcia.h>\n \n@@ -56,6 +57,9 @@ struct bcm63xx_pcmcia_socket {\n \n \t/* base address of io memory */\n \tvoid __iomem *io_base;\n+\n+\t/* ready gpio */\n+\tstruct gpio_desc *ready_gpio;\n };\n \n #endif /* BCM63XX_PCMCIA_H_ */\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/381-Documentation-add-BCM6318-pincontroller-binding-docu.patch",
    "content": "From 8439e5d2e69f54a532bb5f8ec001b4b5a3035574 Mon Sep 17 00:00:00 2001\nFrom: Jonas Gorski <jonas.gorski@gmail.com>\nDate: Wed, 27 Jul 2016 11:38:05 +0200\nSubject: [PATCH 14/16] Documentation: add BCM6318 pincontroller binding\n documentation\n\nAdd binding documentation for the pincontrol core found in BCM6318 SoCs.\n\nSigned-off-by: Jonas Gorski <jonas.gorski@gmail.com>\n---\n .../bindings/pinctrl/brcm,bcm6318-pinctrl.txt      | 79 ++++++++++++++++++++++\n 1 file changed, 79 insertions(+)\n create mode 100644 Documentation/devicetree/bindings/pinctrl/brcm,bcm6318-pinctrl.txt\n\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/pinctrl/brcm,bcm6318-pinctrl.txt\n@@ -0,0 +1,79 @@\n+* Broadcom BCM6318 pin controller\n+\n+Required properties:\n+- compatible: Must be \"brcm,bcm6318-pinctrl\".\n+- regs: Register specifiers of dirout, dat, mode, mux, and pad registers.\n+- reg-names: Must be \"dirout\", \"dat\", \"mode\", \"mux\", \"pad\".\n+- gpio-controller: Identifies this node as a gpio controller.\n+- #gpio-cells: Must be <2>.\n+\n+Example:\n+\n+pinctrl: pin-controller@10000080 {\n+\tcompatible = \"brcm,bcm6318-pinctrl\";\n+\treg = <0x10000080 0x08>,\n+\t      <0x10000088 0x08>,\n+\t      <0x10000098 0x04>,\n+\t      <0x1000009c 0x0c>,\n+\t      <0x100000d4 0x18>;\n+\treg-names = \"dirout\", \"dat\", \"mode\", \"mux\", \"pad\";\n+\n+\tgpio-controller;\n+\t#gpio-cells = <2>;\n+};\n+\n+\n+Available pins/groups and functions:\n+\n+name\t\tpins\tfunctions\n+-----------------------------------------------------------\n+gpio0\t\t0\tled, ephy0_spd_led\n+gpio1\t\t1\tled, ephy1_spd_led\n+gpio2\t\t2\tled, ephy2_spd_led\n+gpio3\t\t3\tled, ephy3_spd_led\n+gpio4\t\t4\tled, ephy0_act_led\n+gpio5\t\t5\tled, ephy1_act_led\n+gpio6\t\t6\tled, ephy2_act_led, serial_led_data\n+gpio7\t\t7\tled, ephy3_act_led, serial_led_clk\n+gpio8\t\t8\tled, inet_act_led\n+gpio9\t\t9\tled, inet_fail_led\n+gpio10\t\t10\tled, dsl_led\n+gpio11\t\t11\tled, post_fail_led\n+gpio12\t\t12\tled, wlan_wps_led\n+gpio13\t\t13\tled, usb_pwron, usb_device_led\n+gpio14\t\t14\tled\n+gpio15\t\t15\tled\n+gpio16\t\t16\tled\n+gpio17\t\t17\tled\n+gpio18\t\t18\tled\n+gpio19\t\t19\tled\n+gpio20\t\t20\tled\n+gpio21\t\t21\tled\n+gpio22\t\t22\tled\n+gpio23\t\t23\tled\n+gpio24\t\t24\t-\n+gpio25\t\t25\t-\n+gpio26\t\t26\t-\n+gpio27\t\t27\t-\n+gpio28\t\t28\t-\n+gpio29\t\t29\t-\n+gpio30\t\t30\t-\n+gpio31\t\t31\t-\n+gpio32\t\t32\t-\n+gpio33\t\t33\t-\n+gpio34\t\t34\t-\n+gpio35\t\t35\t-\n+gpio36\t\t36\t-\n+gpio37\t\t37\t-\n+gpio38\t\t38\t-\n+gpio39\t\t39\t-\n+gpio40\t\t40\tusb_active\n+gpio41\t\t41\t-\n+gpio42\t\t42\t-\n+gpio43\t\t43\t-\n+gpio44\t\t44\t-\n+gpio45\t\t45\t-\n+gpio46\t\t46\t-\n+gpio47\t\t47\t-\n+gpio48\t\t48\t-\n+gpio49\t\t49\t-\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/382-pinctrl-add-a-pincontrol-driver-for-BCM6318.patch",
    "content": "From bd9c250ef85e6f99aa5d59b21abb87d0a48f2f61 Mon Sep 17 00:00:00 2001\nFrom: Jonas Gorski <jonas.gorski@gmail.com>\nDate: Fri, 24 Jun 2016 22:20:39 +0200\nSubject: [PATCH 15/16] pinctrl: add a pincontrol driver for BCM6318\n\nAdd a pincontrol driver for BCM6318. BCM6318 allows muxing most GPIOs\nto different functions. BCM6318 is similar to BCM6328 with the addition\nof a pad register, and the GPIO meaning of the mux register changes\nbased on the GPIO number.\n\nSigned-off-by: Jonas Gorski <jonas.gorski@gmail.com>\n---\n drivers/pinctrl/bcm63xx/Kconfig           |   7 +\n drivers/pinctrl/bcm63xx/Makefile          |   1 +\n drivers/pinctrl/bcm63xx/pinctrl-bcm6318.c | 564 ++++++++++++++++++++++++++++++\n 3 files changed, 572 insertions(+)\n create mode 100644 drivers/pinctrl/bcm63xx/pinctrl-bcm6318.c\n\n--- a/drivers/pinctrl/bcm63xx/Kconfig\n+++ b/drivers/pinctrl/bcm63xx/Kconfig\n@@ -2,6 +2,13 @@ config PINCTRL_BCM63XX\n \tbool\n \tselect GPIO_GENERIC\n \n+config PINCTRL_BCM6318\n+\tbool \"BCM6318 pincontrol driver\" if COMPILE_TEST\n+\tselect PINMUX\n+\tselect PINCONF\n+\tselect PINCTRL_BCM63XX\n+\tselect GENERIC_PINCONF\n+\n config PINCTRL_BCM6328\n \tbool \"BCM6328 pincontrol driver\" if COMPILE_TEST\n \tselect PINMUX\n--- a/drivers/pinctrl/bcm63xx/Makefile\n+++ b/drivers/pinctrl/bcm63xx/Makefile\n@@ -1,4 +1,5 @@\n obj-$(CONFIG_PINCTRL_BCM63XX)\t+= pinctrl-bcm63xx.o\n+obj-$(CONFIG_PINCTRL_BCM6318)\t+= pinctrl-bcm6318.o\n obj-$(CONFIG_PINCTRL_BCM6328)\t+= pinctrl-bcm6328.o\n obj-$(CONFIG_PINCTRL_BCM6348)\t+= pinctrl-bcm6348.o\n obj-$(CONFIG_PINCTRL_BCM6358)\t+= pinctrl-bcm6358.o\n--- /dev/null\n+++ b/drivers/pinctrl/bcm63xx/pinctrl-bcm6318.c\n@@ -0,0 +1,564 @@\n+/*\n+ * This file is subject to the terms and conditions of the GNU General Public\n+ * License.  See the file \"COPYING\" in the main directory of this archive\n+ * for more details.\n+ *\n+ * Copyright (C) 2016 Jonas Gorski <jonas.gorski@gmail.com>\n+ */\n+\n+#include <linux/kernel.h>\n+#include <linux/spinlock.h>\n+#include <linux/bitops.h>\n+#include <linux/gpio.h>\n+#include <linux/gpio/driver.h>\n+#include <linux/of.h>\n+#include <linux/of_gpio.h>\n+#include <linux/slab.h>\n+#include <linux/platform_device.h>\n+\n+#include <linux/pinctrl/pinconf.h>\n+#include <linux/pinctrl/pinconf-generic.h>\n+#include <linux/pinctrl/pinmux.h>\n+#include <linux/pinctrl/machine.h>\n+\n+#include \"../core.h\"\n+#include \"../pinctrl-utils.h\"\n+\n+#include \"pinctrl-bcm63xx.h\"\n+\n+#define BCM6318_NGPIO\t\t50\n+\n+struct bcm6318_pingroup {\n+\tconst char *name;\n+\tconst unsigned * const pins;\n+\tconst unsigned num_pins;\n+};\n+\n+struct bcm6318_function {\n+\tconst char *name;\n+\tconst char * const *groups;\n+\tconst unsigned num_groups;\n+\n+\tunsigned mode_val:1;\n+\tunsigned mux_val:2;\n+};\n+\n+struct bcm6318_pinctrl {\n+\tstruct pinctrl_dev *pctldev;\n+\tstruct pinctrl_desc desc;\n+\n+\tvoid __iomem *mode;\n+\tvoid __iomem *mux[3];\n+\tvoid __iomem *pad[6];\n+\n+\t/* register access lock */\n+\tspinlock_t lock;\n+\n+\tstruct gpio_chip gpio[2];\n+};\n+\n+static const struct pinctrl_pin_desc bcm6318_pins[] = {\n+\tPINCTRL_PIN(0, \"gpio0\"),\n+\tPINCTRL_PIN(1, \"gpio1\"),\n+\tPINCTRL_PIN(2, \"gpio2\"),\n+\tPINCTRL_PIN(3, \"gpio3\"),\n+\tPINCTRL_PIN(4, \"gpio4\"),\n+\tPINCTRL_PIN(5, \"gpio5\"),\n+\tPINCTRL_PIN(6, \"gpio6\"),\n+\tPINCTRL_PIN(7, \"gpio7\"),\n+\tPINCTRL_PIN(8, \"gpio8\"),\n+\tPINCTRL_PIN(9, \"gpio9\"),\n+\tPINCTRL_PIN(10, \"gpio10\"),\n+\tPINCTRL_PIN(11, \"gpio11\"),\n+\tPINCTRL_PIN(12, \"gpio12\"),\n+\tPINCTRL_PIN(13, \"gpio13\"),\n+\tPINCTRL_PIN(14, \"gpio14\"),\n+\tPINCTRL_PIN(15, \"gpio15\"),\n+\tPINCTRL_PIN(16, \"gpio16\"),\n+\tPINCTRL_PIN(17, \"gpio17\"),\n+\tPINCTRL_PIN(18, \"gpio18\"),\n+\tPINCTRL_PIN(19, \"gpio19\"),\n+\tPINCTRL_PIN(20, \"gpio20\"),\n+\tPINCTRL_PIN(21, \"gpio21\"),\n+\tPINCTRL_PIN(22, \"gpio22\"),\n+\tPINCTRL_PIN(23, \"gpio23\"),\n+\tPINCTRL_PIN(24, \"gpio24\"),\n+\tPINCTRL_PIN(25, \"gpio25\"),\n+\tPINCTRL_PIN(26, \"gpio26\"),\n+\tPINCTRL_PIN(27, \"gpio27\"),\n+\tPINCTRL_PIN(28, \"gpio28\"),\n+\tPINCTRL_PIN(29, \"gpio29\"),\n+\tPINCTRL_PIN(30, \"gpio30\"),\n+\tPINCTRL_PIN(31, \"gpio31\"),\n+\tPINCTRL_PIN(32, \"gpio32\"),\n+\tPINCTRL_PIN(33, \"gpio33\"),\n+\tPINCTRL_PIN(34, \"gpio34\"),\n+\tPINCTRL_PIN(35, \"gpio35\"),\n+\tPINCTRL_PIN(36, \"gpio36\"),\n+\tPINCTRL_PIN(37, \"gpio37\"),\n+\tPINCTRL_PIN(38, \"gpio38\"),\n+\tPINCTRL_PIN(39, \"gpio39\"),\n+\tPINCTRL_PIN(40, \"gpio40\"),\n+\tPINCTRL_PIN(41, \"gpio41\"),\n+\tPINCTRL_PIN(42, \"gpio42\"),\n+\tPINCTRL_PIN(43, \"gpio43\"),\n+\tPINCTRL_PIN(44, \"gpio44\"),\n+\tPINCTRL_PIN(45, \"gpio45\"),\n+\tPINCTRL_PIN(46, \"gpio46\"),\n+\tPINCTRL_PIN(47, \"gpio47\"),\n+\tPINCTRL_PIN(48, \"gpio48\"),\n+\tPINCTRL_PIN(49, \"gpio49\"),\n+};\n+\n+static unsigned gpio0_pins[] = { 0 };\n+static unsigned gpio1_pins[] = { 1 };\n+static unsigned gpio2_pins[] = { 2 };\n+static unsigned gpio3_pins[] = { 3 };\n+static unsigned gpio4_pins[] = { 4 };\n+static unsigned gpio5_pins[] = { 5 };\n+static unsigned gpio6_pins[] = { 6 };\n+static unsigned gpio7_pins[] = { 7 };\n+static unsigned gpio8_pins[] = { 8 };\n+static unsigned gpio9_pins[] = { 9 };\n+static unsigned gpio10_pins[] = { 10 };\n+static unsigned gpio11_pins[] = { 11 };\n+static unsigned gpio12_pins[] = { 12 };\n+static unsigned gpio13_pins[] = { 13 };\n+static unsigned gpio14_pins[] = { 14 };\n+static unsigned gpio15_pins[] = { 15 };\n+static unsigned gpio16_pins[] = { 16 };\n+static unsigned gpio17_pins[] = { 17 };\n+static unsigned gpio18_pins[] = { 18 };\n+static unsigned gpio19_pins[] = { 19 };\n+static unsigned gpio20_pins[] = { 20 };\n+static unsigned gpio21_pins[] = { 21 };\n+static unsigned gpio22_pins[] = { 22 };\n+static unsigned gpio23_pins[] = { 23 };\n+static unsigned gpio24_pins[] = { 24 };\n+static unsigned gpio25_pins[] = { 25 };\n+static unsigned gpio26_pins[] = { 26 };\n+static unsigned gpio27_pins[] = { 27 };\n+static unsigned gpio28_pins[] = { 28 };\n+static unsigned gpio29_pins[] = { 29 };\n+static unsigned gpio30_pins[] = { 30 };\n+static unsigned gpio31_pins[] = { 31 };\n+static unsigned gpio32_pins[] = { 32 };\n+static unsigned gpio33_pins[] = { 33 };\n+static unsigned gpio34_pins[] = { 34 };\n+static unsigned gpio35_pins[] = { 35 };\n+static unsigned gpio36_pins[] = { 36 };\n+static unsigned gpio37_pins[] = { 37 };\n+static unsigned gpio38_pins[] = { 38 };\n+static unsigned gpio39_pins[] = { 39 };\n+static unsigned gpio40_pins[] = { 40 };\n+static unsigned gpio41_pins[] = { 41 };\n+static unsigned gpio42_pins[] = { 42 };\n+static unsigned gpio43_pins[] = { 43 };\n+static unsigned gpio44_pins[] = { 44 };\n+static unsigned gpio45_pins[] = { 45 };\n+static unsigned gpio46_pins[] = { 46 };\n+static unsigned gpio47_pins[] = { 47 };\n+static unsigned gpio48_pins[] = { 48 };\n+static unsigned gpio49_pins[] = { 49 };\n+\n+#define BCM6318_GROUP(n)\t\t\t\t\t\\\n+\t{\t\t\t\t\t\t\t\\\n+\t\t.name = #n,\t\t\t\t\t\\\n+\t\t.pins = n##_pins,\t\t\t\t\\\n+\t\t.num_pins = ARRAY_SIZE(n##_pins),\t\t\\\n+\t}\n+\n+static struct bcm6318_pingroup bcm6318_groups[] = {\n+\tBCM6318_GROUP(gpio0),\n+\tBCM6318_GROUP(gpio1),\n+\tBCM6318_GROUP(gpio2),\n+\tBCM6318_GROUP(gpio3),\n+\tBCM6318_GROUP(gpio4),\n+\tBCM6318_GROUP(gpio5),\n+\tBCM6318_GROUP(gpio6),\n+\tBCM6318_GROUP(gpio7),\n+\tBCM6318_GROUP(gpio8),\n+\tBCM6318_GROUP(gpio9),\n+\tBCM6318_GROUP(gpio10),\n+\tBCM6318_GROUP(gpio11),\n+\tBCM6318_GROUP(gpio12),\n+\tBCM6318_GROUP(gpio13),\n+\tBCM6318_GROUP(gpio14),\n+\tBCM6318_GROUP(gpio15),\n+\tBCM6318_GROUP(gpio16),\n+\tBCM6318_GROUP(gpio17),\n+\tBCM6318_GROUP(gpio18),\n+\tBCM6318_GROUP(gpio19),\n+\tBCM6318_GROUP(gpio20),\n+\tBCM6318_GROUP(gpio21),\n+\tBCM6318_GROUP(gpio22),\n+\tBCM6318_GROUP(gpio23),\n+\tBCM6318_GROUP(gpio24),\n+\tBCM6318_GROUP(gpio25),\n+\tBCM6318_GROUP(gpio26),\n+\tBCM6318_GROUP(gpio27),\n+\tBCM6318_GROUP(gpio28),\n+\tBCM6318_GROUP(gpio29),\n+\tBCM6318_GROUP(gpio30),\n+\tBCM6318_GROUP(gpio31),\n+\tBCM6318_GROUP(gpio32),\n+\tBCM6318_GROUP(gpio33),\n+\tBCM6318_GROUP(gpio34),\n+\tBCM6318_GROUP(gpio35),\n+\tBCM6318_GROUP(gpio36),\n+\tBCM6318_GROUP(gpio37),\n+\tBCM6318_GROUP(gpio38),\n+\tBCM6318_GROUP(gpio39),\n+\tBCM6318_GROUP(gpio40),\n+\tBCM6318_GROUP(gpio41),\n+\tBCM6318_GROUP(gpio42),\n+\tBCM6318_GROUP(gpio43),\n+\tBCM6318_GROUP(gpio44),\n+\tBCM6318_GROUP(gpio45),\n+\tBCM6318_GROUP(gpio46),\n+\tBCM6318_GROUP(gpio47),\n+\tBCM6318_GROUP(gpio48),\n+\tBCM6318_GROUP(gpio49),\n+};\n+\n+/* GPIO_MODE */\n+static const char * const led_groups[] = {\n+\t\"gpio0\",\n+\t\"gpio1\",\n+\t\"gpio2\",\n+\t\"gpio3\",\n+\t\"gpio4\",\n+\t\"gpio5\",\n+\t\"gpio6\",\n+\t\"gpio7\",\n+\t\"gpio8\",\n+\t\"gpio9\",\n+\t\"gpio10\",\n+\t\"gpio11\",\n+\t\"gpio12\",\n+\t\"gpio13\",\n+\t\"gpio14\",\n+\t\"gpio15\",\n+\t\"gpio16\",\n+\t\"gpio17\",\n+\t\"gpio18\",\n+\t\"gpio19\",\n+\t\"gpio20\",\n+\t\"gpio21\",\n+\t\"gpio22\",\n+\t\"gpio23\",\n+};\n+\n+/* PINMUX_SEL */\n+static const char * const ephy0_spd_led_groups[] = {\n+\t\"gpio0\",\n+};\n+\n+static const char * const ephy1_spd_led_groups[] = {\n+\t\"gpio1\",\n+};\n+\n+static const char * const ephy2_spd_led_groups[] = {\n+\t\"gpio2\",\n+};\n+\n+static const char * const ephy3_spd_led_groups[] = {\n+\t\"gpio3\",\n+};\n+\n+static const char * const ephy0_act_led_groups[] = {\n+\t\"gpio4\",\n+};\n+\n+static const char * const ephy1_act_led_groups[] = {\n+\t\"gpio5\",\n+};\n+\n+static const char * const ephy2_act_led_groups[] = {\n+\t\"gpio6\",\n+};\n+\n+static const char * const ephy3_act_led_groups[] = {\n+\t\"gpio7\",\n+};\n+\n+static const char * const serial_led_data_groups[] = {\n+\t\"gpio6\",\n+};\n+\n+static const char * const serial_led_clk_groups[] = {\n+\t\"gpio7\",\n+};\n+\n+static const char * const inet_act_led_groups[] = {\n+\t\"gpio8\",\n+};\n+\n+static const char * const inet_fail_led_groups[] = {\n+\t\"gpio9\",\n+};\n+\n+static const char * const dsl_led_groups[] = {\n+\t\"gpio10\",\n+};\n+\n+static const char * const post_fail_led_groups[] = {\n+\t\"gpio11\",\n+};\n+\n+static const char * const wlan_wps_led_groups[] = {\n+\t\"gpio12\",\n+};\n+\n+static const char * const usb_pwron_groups[] = {\n+\t\"gpio13\",\n+};\n+\n+static const char * const usb_device_led_groups[] = {\n+\t\"gpio13\",\n+};\n+\n+static const char * const usb_active_groups[] = {\n+\t\"gpio40\",\n+};\n+\n+#define BCM6318_MODE_FUN(n)\t\t\t\t\\\n+\t{\t\t\t\t\t\t\\\n+\t\t.name = #n,\t\t\t\t\\\n+\t\t.groups = n##_groups,\t\t\t\\\n+\t\t.num_groups = ARRAY_SIZE(n##_groups),\t\\\n+\t\t.mode_val = 1,\t\t\t\t\\\n+\t}\n+\n+#define BCM6318_MUX_FUN(n, mux)\t\t\t\t\\\n+\t{\t\t\t\t\t\t\\\n+\t\t.name = #n,\t\t\t\t\\\n+\t\t.groups = n##_groups,\t\t\t\\\n+\t\t.num_groups = ARRAY_SIZE(n##_groups),\t\\\n+\t\t.mux_val = mux,\t\t\t\t\\\n+\t}\n+\n+static const struct bcm6318_function bcm6318_funcs[] = {\n+\tBCM6318_MODE_FUN(led),\n+\tBCM6318_MUX_FUN(ephy0_spd_led, 1),\n+\tBCM6318_MUX_FUN(ephy1_spd_led, 1),\n+\tBCM6318_MUX_FUN(ephy2_spd_led, 1),\n+\tBCM6318_MUX_FUN(ephy3_spd_led, 1),\n+\tBCM6318_MUX_FUN(ephy0_act_led, 1),\n+\tBCM6318_MUX_FUN(ephy1_act_led, 1),\n+\tBCM6318_MUX_FUN(ephy2_act_led, 1),\n+\tBCM6318_MUX_FUN(ephy3_act_led, 1),\n+\tBCM6318_MUX_FUN(serial_led_data, 3),\n+\tBCM6318_MUX_FUN(serial_led_clk, 3),\n+\tBCM6318_MUX_FUN(inet_act_led, 1),\n+\tBCM6318_MUX_FUN(inet_fail_led, 1),\n+\tBCM6318_MUX_FUN(dsl_led, 1),\n+\tBCM6318_MUX_FUN(post_fail_led, 1),\n+\tBCM6318_MUX_FUN(wlan_wps_led, 1),\n+\tBCM6318_MUX_FUN(usb_pwron, 1),\n+\tBCM6318_MUX_FUN(usb_device_led, 2),\n+\tBCM6318_MUX_FUN(usb_active, 2),\n+};\n+\n+static int bcm6318_pinctrl_get_group_count(struct pinctrl_dev *pctldev)\n+{\n+\treturn ARRAY_SIZE(bcm6318_groups);\n+}\n+\n+static const char *bcm6318_pinctrl_get_group_name(struct pinctrl_dev *pctldev,\n+\t\t\t\t\t\t  unsigned group)\n+{\n+\treturn bcm6318_groups[group].name;\n+}\n+\n+static int bcm6318_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,\n+\t\t\t\t\t  unsigned group, const unsigned **pins,\n+\t\t\t\t\t  unsigned *num_pins)\n+{\n+\t*pins = bcm6318_groups[group].pins;\n+\t*num_pins = bcm6318_groups[group].num_pins;\n+\n+\treturn 0;\n+}\n+\n+static int bcm6318_pinctrl_get_func_count(struct pinctrl_dev *pctldev)\n+{\n+\treturn ARRAY_SIZE(bcm6318_funcs);\n+}\n+\n+static const char *bcm6318_pinctrl_get_func_name(struct pinctrl_dev *pctldev,\n+\t\t\t\t\t\t unsigned selector)\n+{\n+\treturn bcm6318_funcs[selector].name;\n+}\n+\n+static int bcm6318_pinctrl_get_groups(struct pinctrl_dev *pctldev,\n+\t\t\t\t      unsigned selector,\n+\t\t\t\t      const char * const **groups,\n+\t\t\t\t      unsigned * const num_groups)\n+{\n+\t*groups = bcm6318_funcs[selector].groups;\n+\t*num_groups = bcm6318_funcs[selector].num_groups;\n+\n+\treturn 0;\n+}\n+\n+static void bcm6318_rmw_mux(struct bcm6318_pinctrl *pctl, unsigned pin,\n+\t\t\t    u32 mode, u32 mux)\n+{\n+\tunsigned long flags;\n+\tu32 reg;\n+\n+\tspin_lock_irqsave(&pctl->lock, flags);\n+\tif (pin < 32) {\n+\t\treg = __raw_readl(pctl->mode);\n+\t\treg &= ~BIT(pin);\n+\t\tif (mode)\n+\t\t\treg |= BIT(pin);\n+\t\t__raw_writel(reg, pctl->mode);\n+\t}\n+\n+\tif (pin < 48) {\n+\t\treg = __raw_readl(pctl->mux[pin / 16]);\n+\t\treg &= ~(3UL << ((pin % 16) * 2));\n+\t\treg |= mux << ((pin % 16) * 2);\n+\t\t__raw_writel(reg, pctl->mux[pin / 16]);\n+\t}\n+\tspin_unlock_irqrestore(&pctl->lock, flags);\n+}\n+\n+static void bcm6318_set_pad(struct bcm6318_pinctrl *pctl, unsigned pin, u8 val)\n+{\n+\tunsigned long flags;\n+\tu32 reg;\n+\n+\tspin_lock_irqsave(&pctl->lock, flags);\n+\treg = __raw_readl(pctl->pad[pin / 8]);\n+\treg &= ~(0xfUL << ((pin % 8) * 4));\n+\treg |= val << ((pin % 8) * 4);\n+\t__raw_writel(reg, pctl->pad[pin / 8]);\n+\tspin_unlock_irqrestore(&pctl->lock, flags);\n+}\n+\n+static int bcm6318_pinctrl_set_mux(struct pinctrl_dev *pctldev,\n+\t\t\t\t   unsigned selector, unsigned group)\n+{\n+\tstruct bcm6318_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);\n+\tconst struct bcm6318_pingroup *grp = &bcm6318_groups[group];\n+\tconst struct bcm6318_function *f = &bcm6318_funcs[selector];\n+\n+\tbcm6318_rmw_mux(pctl, grp->pins[0], f->mode_val, f->mux_val);\n+\n+\treturn 0;\n+}\n+\n+static int bcm6318_gpio_request_enable(struct pinctrl_dev *pctldev,\n+\t\t\t\t       struct pinctrl_gpio_range *range,\n+\t\t\t\t       unsigned offset)\n+{\n+\tstruct bcm6318_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);\n+\n+\t/* disable all functions using this pin */\n+\tif (offset < 13) {\n+\t\t/* GPIOs 0-12 use mux 0 as GPIO function */\n+\t\tbcm6318_rmw_mux(pctl, offset, 0, 0);\n+\t} else if (offset < 42) {\n+\t\t/* GPIOs 13-41 use mux 3 as GPIO function */\n+\t\tbcm6318_rmw_mux(pctl, offset, 0, 3);\n+\n+\t\t/* FIXME: revert to old value for non gpio? */\n+\t\tbcm6318_set_pad(pctl, offset, 0);\n+\t} else {\n+\t\t/* no idea, really */\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static struct pinctrl_ops bcm6318_pctl_ops = {\n+\t.get_groups_count\t= bcm6318_pinctrl_get_group_count,\n+\t.get_group_name\t\t= bcm6318_pinctrl_get_group_name,\n+\t.get_group_pins\t\t= bcm6318_pinctrl_get_group_pins,\n+#ifdef CONFIG_OF\n+\t.dt_node_to_map\t\t= pinconf_generic_dt_node_to_map_pin,\n+\t.dt_free_map\t\t= pinctrl_utils_free_map,\n+#endif\n+};\n+\n+static struct pinmux_ops bcm6318_pmx_ops = {\n+\t.get_functions_count\t= bcm6318_pinctrl_get_func_count,\n+\t.get_function_name\t= bcm6318_pinctrl_get_func_name,\n+\t.get_function_groups\t= bcm6318_pinctrl_get_groups,\n+\t.set_mux\t\t= bcm6318_pinctrl_set_mux,\n+\t.gpio_request_enable\t= bcm6318_gpio_request_enable,\n+\t.strict \t\t= true,\n+};\n+\n+static int bcm6318_pinctrl_probe(struct platform_device *pdev)\n+{\n+\tstruct bcm6318_pinctrl *pctl;\n+\tstruct resource *res;\n+\tvoid __iomem *mode, *mux, *pad;\n+\tunsigned i;\n+\n+\tres = platform_get_resource_byname(pdev, IORESOURCE_MEM, \"mode\");\n+\tmode = devm_ioremap_resource(&pdev->dev, res);\n+\tif (IS_ERR(mode))\n+\t\treturn PTR_ERR(mode);\n+\n+\tres = platform_get_resource_byname(pdev, IORESOURCE_MEM, \"mux\");\n+\tmux = devm_ioremap_resource(&pdev->dev, res);\n+\tif (IS_ERR(mux))\n+\t\treturn PTR_ERR(mux);\n+\n+\tres = platform_get_resource_byname(pdev, IORESOURCE_MEM, \"pad\");\n+\tpad = devm_ioremap_resource(&pdev->dev, res);\n+\tif (IS_ERR(pad))\n+\t\treturn PTR_ERR(pad);\n+\n+\tpctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);\n+\tif (!pctl)\n+\t\treturn -ENOMEM;\n+\n+\tspin_lock_init(&pctl->lock);\n+\n+\tpctl->mode = mode;\n+\n+\tfor (i = 0; i < 3; i++)\n+\t\tpctl->mux[i] = mux + (i * 4);\n+\n+\tfor (i = 0; i < 6; i++)\n+\t\tpctl->pad[i] = pad + (i * 4);\n+\n+\tpctl->desc.name = dev_name(&pdev->dev);\n+\tpctl->desc.owner = THIS_MODULE;\n+\tpctl->desc.pctlops = &bcm6318_pctl_ops;\n+\tpctl->desc.pmxops = &bcm6318_pmx_ops;\n+\n+\tpctl->desc.npins = ARRAY_SIZE(bcm6318_pins);\n+\tpctl->desc.pins = bcm6318_pins;\n+\n+\tplatform_set_drvdata(pdev, pctl);\n+\n+\tpctl->pctldev = bcm63xx_pinctrl_register(pdev, &pctl->desc, pctl,\n+\t\t\t\t\t\t pctl->gpio, BCM6318_NGPIO);\n+\tif (IS_ERR(pctl->pctldev))\n+\t\treturn PTR_ERR(pctl->pctldev);\n+\n+\treturn 0;\n+}\n+\n+static const struct of_device_id bcm6318_pinctrl_match[] = {\n+\t{ .compatible = \"brcm,bcm6318-pinctrl\", },\n+\t{ },\n+};\n+\n+static struct platform_driver bcm6318_pinctrl_driver = {\n+\t.probe = bcm6318_pinctrl_probe,\n+\t.driver = {\n+\t\t.name = \"bcm6318-pinctrl\",\n+\t\t.of_match_table = bcm6318_pinctrl_match,\n+\t},\n+};\n+\n+builtin_platform_driver(bcm6318_pinctrl_driver);\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/383-bcm63xx_select_pinctrl.patch",
    "content": "--- a/arch/mips/bcm63xx/Kconfig\n+++ b/arch/mips/bcm63xx/Kconfig\n@@ -25,6 +25,8 @@ config BCM63XX_CPU_6318\n \tselect HAVE_PCI\n \tselect BCM63XX_OHCI\n \tselect BCM63XX_EHCI\n+\tselect PINCTRL\n+\tselect PINCTRL_BCM6318\n \n config BCM63XX_CPU_6328\n \tbool \"support 6328 CPU\"\n@@ -32,6 +34,8 @@ config BCM63XX_CPU_6328\n \tselect HAVE_PCI\n \tselect BCM63XX_OHCI\n \tselect BCM63XX_EHCI\n+\tselect PINCTRL\n+\tselect PINCTRL_BCM6328\n \n config BCM63XX_CPU_6338\n \tbool \"support 6338 CPU\"\n@@ -47,6 +51,8 @@ config BCM63XX_CPU_6348\n \tselect SYS_HAS_CPU_BMIPS32_3300\n \tselect HAVE_PCI\n \tselect BCM63XX_OHCI\n+\tselect PINCTRL\n+\tselect PINCTRL_BCM6348\n \n config BCM63XX_CPU_6358\n \tbool \"support 6358 CPU\"\n@@ -54,6 +60,8 @@ config BCM63XX_CPU_6358\n \tselect HAVE_PCI\n \tselect BCM63XX_OHCI\n \tselect BCM63XX_EHCI\n+\tselect PINCTRL\n+\tselect PINCTRL_BCM6358\n \n config BCM63XX_CPU_6362\n \tbool \"support 6362 CPU\"\n@@ -61,6 +69,8 @@ config BCM63XX_CPU_6362\n \tselect HAVE_PCI\n \tselect BCM63XX_OHCI\n \tselect BCM63XX_EHCI\n+\tselect PINCTRL\n+\tselect PINCTRL_BCM6362\n \n config BCM63XX_CPU_6368\n \tbool \"support 6368 CPU\"\n@@ -68,6 +78,8 @@ config BCM63XX_CPU_6368\n \tselect HAVE_PCI\n \tselect BCM63XX_OHCI\n \tselect BCM63XX_EHCI\n+\tselect PINCTRL\n+\tselect PINCTRL_BCM6368\n \n config BCM63XX_CPU_63268\n \tbool \"support 63268 CPU\"\n@@ -75,6 +87,8 @@ config BCM63XX_CPU_63268\n \tselect HAVE_PCI\n \tselect BCM63XX_OHCI\n \tselect BCM63XX_EHCI\n+\tselect PINCTRL\n+\tselect PINCTRL_BCM63268\n endmenu\n \n source \"arch/mips/bcm63xx/boards/Kconfig\"\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/389-MIPS-BCM63XX-add-clkdev-lookups-for-device-tree.patch",
    "content": "From cad8f63047c0691e8185d3c9c6a2705b83310c9c Mon Sep 17 00:00:00 2001\nFrom: Jonas Gorski <jonas.gorski@gmail.com>\nDate: Mon, 31 Jul 2017 20:10:36 +0200\nSubject: [PATCH] MIPS: BCM63XX: add clkdev lookups for device tree\n\n---\n arch/mips/bcm63xx/clk.c | 15 +++++++++++++++\n 1 file changed, 15 insertions(+)\n\n--- a/arch/mips/bcm63xx/clk.c\n+++ b/arch/mips/bcm63xx/clk.c\n@@ -501,6 +501,8 @@ static struct clk_lookup bcm3368_clks[]\n \tCLKDEV_INIT(NULL, \"periph\", &clk_periph),\n \tCLKDEV_INIT(\"bcm63xx_uart.0\", \"refclk\", &clk_periph),\n \tCLKDEV_INIT(\"bcm63xx_uart.1\", \"refclk\", &clk_periph),\n+\tCLKDEV_INIT(\"fff8c100.serial\", \"refclk\", &clk_periph),\n+\tCLKDEV_INIT(\"fff8c120.serial\", \"refclk\", &clk_periph),\n \t/* gated clocks */\n \tCLKDEV_INIT(NULL, \"enet0\", &clk_enet0),\n \tCLKDEV_INIT(NULL, \"enet1\", &clk_enet1),\n@@ -517,7 +519,9 @@ static struct clk_lookup bcm6318_clks[]\n \t/* fixed rate clocks */\n \tCLKDEV_INIT(NULL, \"periph\", &clk_periph),\n \tCLKDEV_INIT(\"bcm63xx_uart.0\", \"refclk\", &clk_periph),\n+\tCLKDEV_INIT(\"10000100.serial\", \"refclk\", &clk_periph),\n \tCLKDEV_INIT(\"bcm63xx-hsspi.0\", \"pll\", &clk_hsspi_pll),\n+\tCLKDEV_INIT(\"10003000.spi\", \"pll\", &clk_hsspi_pll),\n \t/* gated clocks */\n \tCLKDEV_INIT(NULL, \"enetsw\", &clk_enetsw),\n \tCLKDEV_INIT(NULL, \"usbh\", &clk_usbh),\n@@ -531,7 +535,10 @@ static struct clk_lookup bcm6328_clks[]\n \tCLKDEV_INIT(NULL, \"periph\", &clk_periph),\n \tCLKDEV_INIT(\"bcm63xx_uart.0\", \"refclk\", &clk_periph),\n \tCLKDEV_INIT(\"bcm63xx_uart.1\", \"refclk\", &clk_periph),\n+\tCLKDEV_INIT(\"10000100.serial\", \"refclk\", &clk_periph),\n+\tCLKDEV_INIT(\"10000120.serial\", \"refclk\", &clk_periph),\n \tCLKDEV_INIT(\"bcm63xx-hsspi.0\", \"pll\", &clk_hsspi_pll),\n+\tCLKDEV_INIT(\"10001000.spi\", \"pll\", &clk_hsspi_pll),\n \t/* gated clocks */\n \tCLKDEV_INIT(NULL, \"enetsw\", &clk_enetsw),\n \tCLKDEV_INIT(NULL, \"usbh\", &clk_usbh),\n@@ -544,6 +551,7 @@ static struct clk_lookup bcm6338_clks[]\n \t/* fixed rate clocks */\n \tCLKDEV_INIT(NULL, \"periph\", &clk_periph),\n \tCLKDEV_INIT(\"bcm63xx_uart.0\", \"refclk\", &clk_periph),\n+\tCLKDEV_INIT(\"fffe0300.serial\", \"refclk\", &clk_periph),\n \t/* gated clocks */\n \tCLKDEV_INIT(NULL, \"enet0\", &clk_enet0),\n \tCLKDEV_INIT(NULL, \"enet1\", &clk_enet1),\n@@ -558,6 +566,7 @@ static struct clk_lookup bcm6345_clks[]\n \t/* fixed rate clocks */\n \tCLKDEV_INIT(NULL, \"periph\", &clk_periph),\n \tCLKDEV_INIT(\"bcm63xx_uart.0\", \"refclk\", &clk_periph),\n+\tCLKDEV_INIT(\"fffe0300.serial\", \"refclk\", &clk_periph),\n \t/* gated clocks */\n \tCLKDEV_INIT(NULL, \"enet0\", &clk_enet0),\n \tCLKDEV_INIT(NULL, \"enet1\", &clk_enet1),\n@@ -572,6 +581,7 @@ static struct clk_lookup bcm6348_clks[]\n \t/* fixed rate clocks */\n \tCLKDEV_INIT(NULL, \"periph\", &clk_periph),\n \tCLKDEV_INIT(\"bcm63xx_uart.0\", \"refclk\", &clk_periph),\n+\tCLKDEV_INIT(\"fffe0300.serial\", \"refclk\", &clk_periph),\n \t/* gated clocks */\n \tCLKDEV_INIT(NULL, \"enet0\", &clk_enet0),\n \tCLKDEV_INIT(NULL, \"enet1\", &clk_enet1),\n@@ -588,6 +598,8 @@ static struct clk_lookup bcm6358_clks[]\n \tCLKDEV_INIT(NULL, \"periph\", &clk_periph),\n \tCLKDEV_INIT(\"bcm63xx_uart.0\", \"refclk\", &clk_periph),\n \tCLKDEV_INIT(\"bcm63xx_uart.1\", \"refclk\", &clk_periph),\n+\tCLKDEV_INIT(\"fffe0100.serial\", \"refclk\", &clk_periph),\n+\tCLKDEV_INIT(\"fffe0120.serial\", \"refclk\", &clk_periph),\n \t/* gated clocks */\n \tCLKDEV_INIT(NULL, \"enet0\", &clk_enet0),\n \tCLKDEV_INIT(NULL, \"enet1\", &clk_enet1),\n@@ -607,7 +619,10 @@ static struct clk_lookup bcm6362_clks[]\n \tCLKDEV_INIT(NULL, \"periph\", &clk_periph),\n \tCLKDEV_INIT(\"bcm63xx_uart.0\", \"refclk\", &clk_periph),\n \tCLKDEV_INIT(\"bcm63xx_uart.1\", \"refclk\", &clk_periph),\n+\tCLKDEV_INIT(\"10000100.serial\", \"refclk\", &clk_periph),\n+\tCLKDEV_INIT(\"10000120.serial\", \"refclk\", &clk_periph),\n \tCLKDEV_INIT(\"bcm63xx-hsspi.0\", \"pll\", &clk_hsspi_pll),\n+\tCLKDEV_INIT(\"10001000.spi\", \"pll\", &clk_hsspi_pll),\n \t/* gated clocks */\n \tCLKDEV_INIT(NULL, \"enetsw\", &clk_enetsw),\n \tCLKDEV_INIT(NULL, \"usbh\", &clk_usbh),\n@@ -623,6 +638,8 @@ static struct clk_lookup bcm6368_clks[]\n \tCLKDEV_INIT(NULL, \"periph\", &clk_periph),\n \tCLKDEV_INIT(\"bcm63xx_uart.0\", \"refclk\", &clk_periph),\n \tCLKDEV_INIT(\"bcm63xx_uart.1\", \"refclk\", &clk_periph),\n+\tCLKDEV_INIT(\"10000100.serial\", \"refclk\", &clk_periph),\n+\tCLKDEV_INIT(\"10000120.serial\", \"refclk\", &clk_periph),\n \t/* gated clocks */\n \tCLKDEV_INIT(NULL, \"enetsw\", &clk_enetsw),\n \tCLKDEV_INIT(NULL, \"usbh\", &clk_usbh),\n@@ -637,7 +654,10 @@ static struct clk_lookup bcm63268_clks[]\n \tCLKDEV_INIT(NULL, \"periph\", &clk_periph),\n \tCLKDEV_INIT(\"bcm63xx_uart.0\", \"refclk\", &clk_periph),\n \tCLKDEV_INIT(\"bcm63xx_uart.1\", \"refclk\", &clk_periph),\n+\tCLKDEV_INIT(\"10000180.serial\", \"refclk\", &clk_periph),\n+\tCLKDEV_INIT(\"100001a0.serial\", \"refclk\", &clk_periph),\n \tCLKDEV_INIT(\"bcm63xx-hsspi.0\", \"pll\", &clk_hsspi_pll),\n+\tCLKDEV_INIT(\"10001000.spi\", \"pll\", &clk_hsspi_pll),\n \t/* gated clocks */\n \tCLKDEV_INIT(NULL, \"enetsw\", &clk_enetsw),\n \tCLKDEV_INIT(NULL, \"usbh\", &clk_usbh),\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/390-MIPS-BCM63XX-do-not-register-SPI-controllers.patch",
    "content": "From 39d2882058345b5994680b8731848a0343878019 Mon Sep 17 00:00:00 2001\nFrom: Jonas Gorski <jonas.gorski@gmail.com>\nDate: Sat, 4 Feb 2017 12:58:50 +0100\nSubject: [PATCH 7/8] MIPS: BCM63XX: do not register SPI controllers\n\nWe now register them through DT, so no need to keep them here.\n\nSigned-off-by: Jonas Gorski <jonas.gorski@gmail.com>\n---\n arch/mips/bcm63xx/boards/board_bcm963xx.c | 7 -------\n 1 file changed, 7 deletions(-)\n\n--- a/arch/mips/bcm63xx/boards/board_common.c\n+++ b/arch/mips/bcm63xx/boards/board_common.c\n@@ -27,9 +27,7 @@\n #include <bcm63xx_dev_pci.h>\n #include <bcm63xx_dev_enet.h>\n #include <bcm63xx_dev_flash.h>\n-#include <bcm63xx_dev_hsspi.h>\n #include <bcm63xx_dev_pcmcia.h>\n-#include <bcm63xx_dev_spi.h>\n #include <bcm63xx_dev_usb_ehci.h>\n #include <bcm63xx_dev_usb_ohci.h>\n #include <bcm63xx_dev_usb_usbd.h>\n@@ -236,10 +234,6 @@ int __init board_register_devices(void)\n \t     bcm63xx_register_fallback_sprom(&board.fallback_sprom)))\n \t\tpr_err(PFX \"failed to register fallback SPROM\\n\");\n \n-\tbcm63xx_spi_register();\n-\n-\tbcm63xx_hsspi_register();\n-\n \tbcm63xx_flash_register();\n \n \tbcm63xx_led_data.num_leds = ARRAY_SIZE(board.leds);\n--- a/arch/mips/bcm63xx/Makefile\n+++ b/arch/mips/bcm63xx/Makefile\n@@ -1,7 +1,7 @@\n # SPDX-License-Identifier: GPL-2.0\n obj-y\t\t+= clk.o cpu.o cs.o gpio.o irq.o nvram.o prom.o reset.o \\\n \t\t   setup.o timer.o dev-enet.o dev-flash.o dev-pcmcia.o \\\n-\t\t   dev-rng.o dev-spi.o dev-hsspi.o dev-uart.o dev-wdt.o \\\n+\t\t   dev-rng.o dev-uart.o dev-wdt.o \\\n \t\t   dev-usb-ehci.o dev-usb-ohci.o dev-usb-usbd.o usb-common.o \\\n \t\t   sprom.o\n obj-$(CONFIG_EARLY_PRINTK)\t+= early_printk.o\n--- a/arch/mips/bcm63xx/dev-hsspi.c\n+++ /dev/null\n@@ -1,48 +0,0 @@\n-/*\n- * This file is subject to the terms and conditions of the GNU General Public\n- * License.  See the file \"COPYING\" in the main directory of this archive\n- * for more details.\n- *\n- * Copyright (C) 2012 Jonas Gorski <jonas.gorski@gmail.com>\n- */\n-\n-#include <linux/init.h>\n-#include <linux/kernel.h>\n-#include <linux/platform_device.h>\n-\n-#include <bcm63xx_cpu.h>\n-#include <bcm63xx_dev_hsspi.h>\n-#include <bcm63xx_regs.h>\n-\n-static struct resource spi_resources[] = {\n-\t{\n-\t\t.start\t\t= -1, /* filled at runtime */\n-\t\t.end\t\t= -1, /* filled at runtime */\n-\t\t.flags\t\t= IORESOURCE_MEM,\n-\t},\n-\t{\n-\t\t.start\t\t= -1, /* filled at runtime */\n-\t\t.flags\t\t= IORESOURCE_IRQ,\n-\t},\n-};\n-\n-static struct platform_device bcm63xx_hsspi_device = {\n-\t.name\t\t= \"bcm63xx-hsspi\",\n-\t.id\t\t= 0,\n-\t.num_resources\t= ARRAY_SIZE(spi_resources),\n-\t.resource\t= spi_resources,\n-};\n-\n-int __init bcm63xx_hsspi_register(void)\n-{\n-\tif (!BCMCPU_IS_6318() && !BCMCPU_IS_6328() && !BCMCPU_IS_6362() &&\n-\t\t!BCMCPU_IS_63268())\n-\t\treturn -ENODEV;\n-\n-\tspi_resources[0].start = bcm63xx_regset_address(RSET_HSSPI);\n-\tspi_resources[0].end = spi_resources[0].start;\n-\tspi_resources[0].end += RSET_HSSPI_SIZE - 1;\n-\tspi_resources[1].start = bcm63xx_get_irq_number(IRQ_HSSPI);\n-\n-\treturn platform_device_register(&bcm63xx_hsspi_device);\n-}\n--- a/arch/mips/bcm63xx/dev-spi.c\n+++ /dev/null\n@@ -1,60 +0,0 @@\n-/*\n- * This file is subject to the terms and conditions of the GNU General Public\n- * License.  See the file \"COPYING\" in the main directory of this archive\n- * for more details.\n- *\n- * Copyright (C) 2009-2011 Florian Fainelli <florian@openwrt.org>\n- * Copyright (C) 2010 Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>\n- */\n-\n-#include <linux/init.h>\n-#include <linux/kernel.h>\n-#include <linux/export.h>\n-#include <linux/platform_device.h>\n-#include <linux/err.h>\n-#include <linux/clk.h>\n-\n-#include <bcm63xx_cpu.h>\n-#include <bcm63xx_dev_spi.h>\n-#include <bcm63xx_regs.h>\n-\n-static struct resource spi_resources[] = {\n-\t{\n-\t\t.start\t\t= -1, /* filled at runtime */\n-\t\t.end\t\t= -1, /* filled at runtime */\n-\t\t.flags\t\t= IORESOURCE_MEM,\n-\t},\n-\t{\n-\t\t.start\t\t= -1, /* filled at runtime */\n-\t\t.flags\t\t= IORESOURCE_IRQ,\n-\t},\n-};\n-\n-static struct platform_device bcm63xx_spi_device = {\n-\t.id\t\t= -1,\n-\t.num_resources\t= ARRAY_SIZE(spi_resources),\n-\t.resource\t= spi_resources,\n-};\n-\n-int __init bcm63xx_spi_register(void)\n-{\n-\tif (BCMCPU_IS_6318() || BCMCPU_IS_6328() || BCMCPU_IS_6345())\n-\t\treturn -ENODEV;\n-\n-\tspi_resources[0].start = bcm63xx_regset_address(RSET_SPI);\n-\tspi_resources[0].end = spi_resources[0].start;\n-\tspi_resources[1].start = bcm63xx_get_irq_number(IRQ_SPI);\n-\n-\tif (BCMCPU_IS_6338() || BCMCPU_IS_6348()) {\n-\t\tbcm63xx_spi_device.name = \"bcm6348-spi\",\n-\t\tspi_resources[0].end += BCM_6348_RSET_SPI_SIZE - 1;\n-\t}\n-\n-\tif (BCMCPU_IS_3368() || BCMCPU_IS_6358() || BCMCPU_IS_6362() ||\n-\t\tBCMCPU_IS_6368() || BCMCPU_IS_63268()) {\n-\t\tbcm63xx_spi_device.name = \"bcm6358-spi\",\n-\t\tspi_resources[0].end += BCM_6358_RSET_SPI_SIZE - 1;\n-\t}\n-\n-\treturn platform_device_register(&bcm63xx_spi_device);\n-}\n--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_hsspi.h\n+++ /dev/null\n@@ -1,9 +0,0 @@\n-/* SPDX-License-Identifier: GPL-2.0 */\n-#ifndef BCM63XX_DEV_HSSPI_H\n-#define BCM63XX_DEV_HSSPI_H\n-\n-#include <linux/types.h>\n-\n-int bcm63xx_hsspi_register(void);\n-\n-#endif /* BCM63XX_DEV_HSSPI_H */\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/391-MIPS-BCM63XX-do-not-register-uart.patch",
    "content": "--- a/arch/mips/bcm63xx/Makefile\n+++ b/arch/mips/bcm63xx/Makefile\n@@ -1,7 +1,7 @@\n # SPDX-License-Identifier: GPL-2.0\n obj-y\t\t+= clk.o cpu.o cs.o gpio.o irq.o nvram.o prom.o reset.o \\\n \t\t   setup.o timer.o dev-enet.o dev-flash.o dev-pcmcia.o \\\n-\t\t   dev-rng.o dev-uart.o dev-wdt.o \\\n+\t\t   dev-rng.o dev-wdt.o \\\n \t\t   dev-usb-ehci.o dev-usb-ohci.o dev-usb-usbd.o usb-common.o \\\n \t\t   sprom.o\n obj-$(CONFIG_EARLY_PRINTK)\t+= early_printk.o\n--- a/arch/mips/bcm63xx/dev-uart.c\n+++ /dev/null\n@@ -1,76 +0,0 @@\n-/*\n- * This file is subject to the terms and conditions of the GNU General Public\n- * License.  See the file \"COPYING\" in the main directory of this archive\n- * for more details.\n- *\n- * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>\n- */\n-\n-#include <linux/init.h>\n-#include <linux/kernel.h>\n-#include <linux/platform_device.h>\n-#include <bcm63xx_cpu.h>\n-\n-static struct resource uart0_resources[] = {\n-\t{\n-\t\t/* start & end filled at runtime */\n-\t\t.flags\t\t= IORESOURCE_MEM,\n-\t},\n-\t{\n-\t\t/* start filled at runtime */\n-\t\t.flags\t\t= IORESOURCE_IRQ,\n-\t},\n-};\n-\n-static struct resource uart1_resources[] = {\n-\t{\n-\t\t/* start & end filled at runtime */\n-\t\t.flags\t\t= IORESOURCE_MEM,\n-\t},\n-\t{\n-\t\t/* start filled at runtime */\n-\t\t.flags\t\t= IORESOURCE_IRQ,\n-\t},\n-};\n-\n-static struct platform_device bcm63xx_uart_devices[] = {\n-\t{\n-\t\t.name\t\t= \"bcm63xx_uart\",\n-\t\t.id\t\t= 0,\n-\t\t.num_resources\t= ARRAY_SIZE(uart0_resources),\n-\t\t.resource\t= uart0_resources,\n-\t},\n-\n-\t{\n-\t\t.name\t\t= \"bcm63xx_uart\",\n-\t\t.id\t\t= 1,\n-\t\t.num_resources\t= ARRAY_SIZE(uart1_resources),\n-\t\t.resource\t= uart1_resources,\n-\t}\n-};\n-\n-int __init bcm63xx_uart_register(unsigned int id)\n-{\n-\tif (id >= ARRAY_SIZE(bcm63xx_uart_devices))\n-\t\treturn -ENODEV;\n-\n-\tif (id == 1 && (!BCMCPU_IS_3368() && !BCMCPU_IS_6358() &&\n-\t\t!BCMCPU_IS_6368()))\n-\t\treturn -ENODEV;\n-\n-\tif (id == 0) {\n-\t\tuart0_resources[0].start = bcm63xx_regset_address(RSET_UART0);\n-\t\tuart0_resources[0].end = uart0_resources[0].start +\n-\t\t\tRSET_UART_SIZE - 1;\n-\t\tuart0_resources[1].start = bcm63xx_get_irq_number(IRQ_UART0);\n-\t}\n-\n-\tif (id == 1) {\n-\t\tuart1_resources[0].start = bcm63xx_regset_address(RSET_UART1);\n-\t\tuart1_resources[0].end = uart1_resources[0].start +\n-\t\t\tRSET_UART_SIZE - 1;\n-\t\tuart1_resources[1].start = bcm63xx_get_irq_number(IRQ_UART1);\n-\t}\n-\n-\treturn platform_device_register(&bcm63xx_uart_devices[id]);\n-}\n--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_uart.h\n+++ /dev/null\n@@ -1,7 +0,0 @@\n-/* SPDX-License-Identifier: GPL-2.0 */\n-#ifndef BCM63XX_DEV_UART_H_\n-#define BCM63XX_DEV_UART_H_\n-\n-int bcm63xx_uart_register(unsigned int id);\n-\n-#endif /* BCM63XX_DEV_UART_H_ */\n--- a/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h\n+++ b/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h\n@@ -32,8 +32,6 @@ struct board_info {\n \tunsigned int\thas_ohci0:1;\n \tunsigned int\thas_ehci0:1;\n \tunsigned int\thas_usbd:1;\n-\tunsigned int\thas_uart0:1;\n-\tunsigned int\thas_uart1:1;\n \tunsigned int\tuse_fallback_sprom:1;\n \n \t/* ethernet config */\n--- a/arch/mips/bcm63xx/boards/board_common.c\n+++ b/arch/mips/bcm63xx/boards/board_common.c\n@@ -20,7 +20,6 @@\n #include <asm/prom.h>\n #include <bcm63xx_board.h>\n #include <bcm63xx_cpu.h>\n-#include <bcm63xx_dev_uart.h>\n #include <bcm63xx_regs.h>\n #include <bcm63xx_io.h>\n #include <bcm63xx_gpio.h>\n@@ -188,12 +187,6 @@ int __init board_register_devices(void)\n \n \tbcm63xx_gpio_init();\n \n-\tif (board.has_uart0)\n-\t\tbcm63xx_uart_register(0);\n-\n-\tif (board.has_uart1)\n-\t\tbcm63xx_uart_register(1);\n-\n \tif (board.has_pccard)\n \t\tbcm63xx_pcmcia_register();\n \n--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c\n+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c\n@@ -34,8 +34,6 @@ static struct board_info __initdata boar\n \t.ephy_reset_gpio = 36,\n \t.ephy_reset_gpio_flags = GPIO_ACTIVE_LOW,\n \t.has_pci = 1,\n-\t.has_uart0 = 1,\n-\t.has_uart1 = 1,\n \n \t.has_enet0 = 1,\n \t.enet0 = {\n@@ -62,7 +60,6 @@ static struct board_info __initdata boar\n \t.expected_cpu_id = 0x6328,\n \n \t.has_pci = 1,\n-\t.has_uart0 = 1,\n \t.use_fallback_sprom = 1,\n \n \t.has_usbd = 0,\n@@ -111,7 +108,6 @@ static struct board_info __initdata boar\n \t.expected_cpu_id = 0x6338,\n \n \t.has_ohci0 = 1,\n-\t.has_uart0 = 1,\n \n \t.has_enet0 = 1,\n \t.enet0 = {\n@@ -153,8 +149,6 @@ static struct board_info __initdata boar\n \t.name = \"96338W\",\n \t.expected_cpu_id = 0x6338,\n \n-\t.has_uart0 = 1,\n-\n \t.has_enet0 = 1,\n \t.enet0 = {\n \t\t.force_speed_100 = 1,\n@@ -199,8 +193,6 @@ static struct board_info __initdata boar\n static struct board_info __initdata board_96345gw2 = {\n \t.name = \"96345GW2\",\n \t.expected_cpu_id = 0x6345,\n-\n-\t.has_uart0 = 1,\n };\n #endif /* CONFIG_BCM63XX_CPU_6345 */\n \n@@ -213,7 +205,6 @@ static struct board_info __initdata boar\n \t.expected_cpu_id = 0x6348,\n \n \t.has_pci = 1,\n-\t.has_uart0 = 1,\n \t.use_fallback_sprom = 1,\n \n \t.has_enet0 = 1,\n@@ -260,7 +251,6 @@ static struct board_info __initdata boar\n \t.has_ohci0 = 1,\n \t.has_pccard = 1,\n \t.has_pci = 1,\n-\t.has_uart0 = 1,\n \t.use_fallback_sprom = 1,\n \n \t.has_enet0 = 1,\n@@ -312,7 +302,6 @@ static struct board_info __initdata boar\n \t.has_ohci0 = 1,\n \t.has_pccard = 1,\n \t.has_pci = 1,\n-\t.has_uart0 = 1,\n \t.use_fallback_sprom = 1,\n \n \t.has_enet0 = 1,\n@@ -363,7 +352,6 @@ static struct board_info __initdata boar\n \n \t.has_ohci0 = 1,\n \t.has_pci = 1,\n-\t.has_uart0 = 1,\n \t.use_fallback_sprom = 1,\n \n \t.has_enet0 = 1,\n@@ -415,7 +403,6 @@ static struct board_info __initdata boar\n \t.has_ohci0 = 1,\n \t.has_pccard = 1,\n \t.has_pci = 1,\n-\t.has_uart0 = 1,\n \t.use_fallback_sprom = 1,\n \n \t.has_enet0 = 1,\n@@ -457,7 +444,6 @@ static struct board_info __initdata boar\n \n \t.has_ohci0 = 1,\n \t.has_pci = 1,\n-\t.has_uart0 = 1,\n \t.use_fallback_sprom = 1,\n \n \t.has_enet0 = 1,\n@@ -479,7 +465,6 @@ static struct board_info __initdata boar\n \n \t.has_ohci0 = 1,\n \t.has_pci = 1,\n-\t.has_uart0 = 1,\n \t.use_fallback_sprom = 1,\n \n \t.has_enet0 = 1,\n@@ -508,7 +493,6 @@ static struct board_info __initdata boar\n \t.has_ohci0 = 1,\n \t.has_pccard = 1,\n \t.has_pci = 1,\n-\t.has_uart0 = 1,\n \t.use_fallback_sprom = 1,\n \n \t.has_enet0 = 1,\n@@ -560,7 +544,6 @@ static struct board_info __initdata boar\n \t.num_usbh_ports = 2,\n \t.has_pccard = 1,\n \t.has_pci = 1,\n-\t.has_uart0 = 1,\n \t.use_fallback_sprom = 1,\n \n \t.has_enet0 = 1,\n@@ -606,7 +589,6 @@ static struct board_info __initdata boar\n \t.has_ehci0 = 1,\n \t.has_ohci0 = 1,\n \t.has_pci = 1,\n-\t.has_uart0 = 1,\n \n \t.has_enet0 = 1,\n \t.enet0 = {\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/392-MIPS-BCM63XX-remove-leds-and-buttons.patch",
    "content": "From 997f53b174c63153335508c22dc4493e8e5808d6 Mon Sep 17 00:00:00 2001\nFrom: Jonas Gorski <jogo@openwrt.org>\nDate: Sun, 22 Feb 2015 17:52:32 +0100\nSubject: [PATCH] MIPS: BCM63XX: remove leds and buttons\n\n---\n arch/mips/bcm63xx/boards/board_bcm963xx.c |  262 -----------------------------\n 1 file changed, 262 deletions(-)\n\n--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c\n+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c\n@@ -40,14 +40,6 @@ static struct board_info __initdata boar\n \t\t.has_phy = 1,\n \t\t.use_internal_phy = 1,\n \t},\n-\n-\t.leds = {\n-\t\t{\n-\t\t\t.name = \"CVG834G:green:power\",\n-\t\t\t.gpio = 37,\n-\t\t\t.default_trigger= \"default-on\",\n-\t\t},\n-\t},\n };\n #endif /* CONFIG_BCM63XX_CPU_3368 */\n \n@@ -67,35 +59,6 @@ static struct board_info __initdata boar\n \t\t.use_fullspeed = 0,\n \t\t.port_no = 0,\n \t},\n-\n-\t.leds = {\n-\t\t{\n-\t\t\t.name = \"96328avng::ppp-fail\",\n-\t\t\t.gpio = 2,\n-\t\t\t.active_low = 1,\n-\t\t},\n-\t\t{\n-\t\t\t.name = \"96328avng::power\",\n-\t\t\t.gpio = 4,\n-\t\t\t.active_low = 1,\n-\t\t\t.default_trigger = \"default-on\",\n-\t\t},\n-\t\t{\n-\t\t\t.name = \"96328avng::power-fail\",\n-\t\t\t.gpio = 8,\n-\t\t\t.active_low = 1,\n-\t\t},\n-\t\t{\n-\t\t\t.name = \"96328avng::wps\",\n-\t\t\t.gpio = 9,\n-\t\t\t.active_low = 1,\n-\t\t},\n-\t\t{\n-\t\t\t.name = \"96328avng::ppp\",\n-\t\t\t.gpio = 11,\n-\t\t\t.active_low = 1,\n-\t\t},\n-\t},\n };\n #endif /* CONFIG_BCM63XX_CPU_6328 */\n \n@@ -114,35 +77,6 @@ static struct board_info __initdata boar\n \t\t.force_speed_100 = 1,\n \t\t.force_duplex_full = 1,\n \t},\n-\n-\t.leds = {\n-\t\t{\n-\t\t\t.name = \"adsl\",\n-\t\t\t.gpio = 3,\n-\t\t\t.active_low = 1,\n-\t\t},\n-\t\t{\n-\t\t\t.name = \"ses\",\n-\t\t\t.gpio = 5,\n-\t\t\t.active_low = 1,\n-\t\t},\n-\t\t{\n-\t\t\t.name = \"ppp-fail\",\n-\t\t\t.gpio = 4,\n-\t\t\t.active_low = 1,\n-\t\t},\n-\t\t{\n-\t\t\t.name = \"power\",\n-\t\t\t.gpio = 0,\n-\t\t\t.active_low = 1,\n-\t\t\t.default_trigger = \"default-on\",\n-\t\t},\n-\t\t{\n-\t\t\t.name = \"stop\",\n-\t\t\t.gpio = 1,\n-\t\t\t.active_low = 1,\n-\t\t}\n-\t},\n };\n \n static struct board_info __initdata board_96338w = {\n@@ -154,35 +88,6 @@ static struct board_info __initdata boar\n \t\t.force_speed_100 = 1,\n \t\t.force_duplex_full = 1,\n \t},\n-\n-\t.leds = {\n-\t\t{\n-\t\t\t.name = \"adsl\",\n-\t\t\t.gpio = 3,\n-\t\t\t.active_low = 1,\n-\t\t},\n-\t\t{\n-\t\t\t.name = \"ses\",\n-\t\t\t.gpio = 5,\n-\t\t\t.active_low = 1,\n-\t\t},\n-\t\t{\n-\t\t\t.name = \"ppp-fail\",\n-\t\t\t.gpio = 4,\n-\t\t\t.active_low = 1,\n-\t\t},\n-\t\t{\n-\t\t\t.name = \"power\",\n-\t\t\t.gpio = 0,\n-\t\t\t.active_low = 1,\n-\t\t\t.default_trigger = \"default-on\",\n-\t\t},\n-\t\t{\n-\t\t\t.name = \"stop\",\n-\t\t\t.gpio = 1,\n-\t\t\t.active_low = 1,\n-\t\t},\n-\t},\n };\n #endif /* CONFIG_BCM63XX_CPU_6338 */\n \n@@ -212,36 +117,6 @@ static struct board_info __initdata boar\n \t\t.has_phy = 1,\n \t\t.use_internal_phy = 1,\n \t},\n-\n-\t.leds = {\n-\t\t{\n-\t\t\t.name = \"adsl-fail\",\n-\t\t\t.gpio = 2,\n-\t\t\t.active_low = 1,\n-\t\t},\n-\t\t{\n-\t\t\t.name = \"ppp\",\n-\t\t\t.gpio = 3,\n-\t\t\t.active_low = 1,\n-\t\t},\n-\t\t{\n-\t\t\t.name = \"ppp-fail\",\n-\t\t\t.gpio = 4,\n-\t\t\t.active_low = 1,\n-\t\t},\n-\t\t{\n-\t\t\t.name = \"power\",\n-\t\t\t.gpio = 0,\n-\t\t\t.active_low = 1,\n-\t\t\t.default_trigger = \"default-on\",\n-\n-\t\t},\n-\t\t{\n-\t\t\t.name = \"stop\",\n-\t\t\t.gpio = 1,\n-\t\t\t.active_low = 1,\n-\t\t},\n-\t},\n };\n \n static struct board_info __initdata board_96348gw_10 = {\n@@ -264,35 +139,6 @@ static struct board_info __initdata boar\n \t\t.force_speed_100 = 1,\n \t\t.force_duplex_full = 1,\n \t},\n-\n-\t.leds = {\n-\t\t{\n-\t\t\t.name = \"adsl-fail\",\n-\t\t\t.gpio = 2,\n-\t\t\t.active_low = 1,\n-\t\t},\n-\t\t{\n-\t\t\t.name = \"ppp\",\n-\t\t\t.gpio = 3,\n-\t\t\t.active_low = 1,\n-\t\t},\n-\t\t{\n-\t\t\t.name = \"ppp-fail\",\n-\t\t\t.gpio = 4,\n-\t\t\t.active_low = 1,\n-\t\t},\n-\t\t{\n-\t\t\t.name = \"power\",\n-\t\t\t.gpio = 0,\n-\t\t\t.active_low = 1,\n-\t\t\t.default_trigger = \"default-on\",\n-\t\t},\n-\t\t{\n-\t\t\t.name = \"stop\",\n-\t\t\t.gpio = 1,\n-\t\t\t.active_low = 1,\n-\t\t},\n-\t},\n };\n \n static struct board_info __initdata board_96348gw_11 = {\n@@ -315,35 +161,6 @@ static struct board_info __initdata boar\n \t\t.force_speed_100 = 1,\n \t\t.force_duplex_full = 1,\n \t},\n-\n-\t.leds = {\n-\t\t{\n-\t\t\t.name = \"adsl-fail\",\n-\t\t\t.gpio = 2,\n-\t\t\t.active_low = 1,\n-\t\t},\n-\t\t{\n-\t\t\t.name = \"ppp\",\n-\t\t\t.gpio = 3,\n-\t\t\t.active_low = 1,\n-\t\t},\n-\t\t{\n-\t\t\t.name = \"ppp-fail\",\n-\t\t\t.gpio = 4,\n-\t\t\t.active_low = 1,\n-\t\t},\n-\t\t{\n-\t\t\t.name = \"power\",\n-\t\t\t.gpio = 0,\n-\t\t\t.active_low = 1,\n-\t\t\t.default_trigger = \"default-on\",\n-\t\t},\n-\t\t{\n-\t\t\t.name = \"stop\",\n-\t\t\t.gpio = 1,\n-\t\t\t.active_low = 1,\n-\t\t},\n-\t},\n };\n \n static struct board_info __initdata board_96348gw = {\n@@ -365,35 +182,6 @@ static struct board_info __initdata boar\n \t\t.force_speed_100 = 1,\n \t\t.force_duplex_full = 1,\n \t},\n-\n-\t.leds = {\n-\t\t{\n-\t\t\t.name = \"adsl-fail\",\n-\t\t\t.gpio = 2,\n-\t\t\t.active_low = 1,\n-\t\t},\n-\t\t{\n-\t\t\t.name = \"ppp\",\n-\t\t\t.gpio = 3,\n-\t\t\t.active_low = 1,\n-\t\t},\n-\t\t{\n-\t\t\t.name = \"ppp-fail\",\n-\t\t\t.gpio = 4,\n-\t\t\t.active_low = 1,\n-\t\t},\n-\t\t{\n-\t\t\t.name = \"power\",\n-\t\t\t.gpio = 0,\n-\t\t\t.active_low = 1,\n-\t\t\t.default_trigger = \"default-on\",\n-\t\t},\n-\t\t{\n-\t\t\t.name = \"stop\",\n-\t\t\t.gpio = 1,\n-\t\t\t.active_low = 1,\n-\t\t},\n-\t},\n };\n \n static struct board_info __initdata board_FAST2404 = {\n@@ -506,33 +294,6 @@ static struct board_info __initdata boar\n \t\t.force_speed_100 = 1,\n \t\t.force_duplex_full = 1,\n \t},\n-\n-\t.leds = {\n-\t\t{\n-\t\t\t.name = \"adsl-fail\",\n-\t\t\t.gpio = 15,\n-\t\t\t.active_low = 1,\n-\t\t},\n-\t\t{\n-\t\t\t.name = \"ppp\",\n-\t\t\t.gpio = 22,\n-\t\t\t.active_low = 1,\n-\t\t},\n-\t\t{\n-\t\t\t.name = \"ppp-fail\",\n-\t\t\t.gpio = 23,\n-\t\t\t.active_low = 1,\n-\t\t},\n-\t\t{\n-\t\t\t.name = \"power\",\n-\t\t\t.gpio = 4,\n-\t\t\t.default_trigger = \"default-on\",\n-\t\t},\n-\t\t{\n-\t\t\t.name = \"stop\",\n-\t\t\t.gpio = 5,\n-\t\t},\n-\t},\n };\n \n static struct board_info __initdata board_96358vw2 = {\n@@ -557,29 +318,6 @@ static struct board_info __initdata boar\n \t\t.force_speed_100 = 1,\n \t\t.force_duplex_full = 1,\n \t},\n-\n-\t.leds = {\n-\t\t{\n-\t\t\t.name = \"adsl\",\n-\t\t\t.gpio = 22,\n-\t\t\t.active_low = 1,\n-\t\t},\n-\t\t{\n-\t\t\t.name = \"ppp-fail\",\n-\t\t\t.gpio = 23,\n-\t\t},\n-\t\t{\n-\t\t\t.name = \"power\",\n-\t\t\t.gpio = 5,\n-\t\t\t.active_low = 1,\n-\t\t\t.default_trigger = \"default-on\",\n-\t\t},\n-\t\t{\n-\t\t\t.name = \"stop\",\n-\t\t\t.gpio = 4,\n-\t\t\t.active_low = 1,\n-\t\t},\n-\t},\n };\n \n static struct board_info __initdata board_AGPFS0 = {\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/400-bcm963xx_flashmap.patch",
    "content": "From a4d005c91d403d9f3d0272db6cc46202c06ec774 Mon Sep 17 00:00:00 2001\nFrom: Axel Gembe <ago@bastart.eu.org>\nDate: Mon, 12 May 2008 18:54:09 +0200\nSubject: [PATCH] bcm963xx: flashmap support\n\nSigned-off-by: Axel Gembe <ago@bastart.eu.org>\n---\n arch/mips/bcm63xx/boards/board_bcm963xx.c |   19 +----------------\n drivers/mtd/maps/bcm963xx-flash.c         |   32 ++++++++++++++++++++++++----\n drivers/mtd/redboot.c                     |   13 +++++++++--\n 3 files changed, 38 insertions(+), 26 deletions(-)\n\n--- a/arch/mips/bcm63xx/dev-flash.c\n+++ b/arch/mips/bcm63xx/dev-flash.c\n@@ -35,7 +35,7 @@ static struct mtd_partition mtd_partitio\n \t}\n };\n \n-static const char *bcm63xx_part_types[] = { \"bcm63xxpart\", NULL };\n+static const char *bcm63xx_part_types[] = { \"bcm63xxpart\", \"RedBoot\", NULL };\n \n static struct physmap_flash_data flash_data = {\n \t.width\t\t\t= 2,\n--- a/drivers/mtd/parsers/redboot.c\n+++ b/drivers/mtd/parsers/redboot.c\n@@ -84,6 +84,7 @@ static int parse_redboot_partitions(stru\n \tint nulllen = 0;\n \tint numslots;\n \tunsigned long offset;\n+\tunsigned long fis_origin = 0;\n #ifdef CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED\n \tstatic char nullstring[] = \"unallocated\";\n #endif\n@@ -190,6 +191,16 @@ static int parse_redboot_partitions(stru\n \t\tgoto out;\n \t}\n \n+\tif (data && data->origin) {\n+\t\tfis_origin = data->origin;\n+\t} else {\n+\t\tfor (i = 0; i < numslots; i++) {\n+\t\t\tif (!strncmp(buf[i].name, \"RedBoot\", 8)) {\n+\t\t\t\tfis_origin = (buf[i].flash_base & ((master->size << 1) - 1));\n+\t\t\t}\n+\t\t}\n+\t}\n+\n \tfor (i = 0; i < numslots; i++) {\n \t\tstruct fis_list *new_fl, **prev;\n \n@@ -210,10 +221,10 @@ static int parse_redboot_partitions(stru\n \t\t\tgoto out;\n \t\t}\n \t\tnew_fl->img = &buf[i];\n-\t\tif (data && data->origin)\n-\t\t\tbuf[i].flash_base -= data->origin;\n-\t\telse\n-\t\t\tbuf[i].flash_base &= master->size-1;\n+\t\tif (fis_origin)\n+\t\t\tbuf[i].flash_base -= fis_origin;\n+\n+\t\tbuf[i].flash_base &= (master->size << 1) - 1;\n \n \t\t/* I'm sure the JFFS2 code has done me permanent damage.\n \t\t * I now think the following is _normal_\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/401-bcm963xx_real_rootfs_length.patch",
    "content": "--- a/include/linux/bcm963xx_tag.h\n+++ b/include/linux/bcm963xx_tag.h\n@@ -92,8 +92,10 @@ struct bcm_tag {\n \t__u32 rootfs_crc;\n \t/* 224-227: CRC32 of kernel partition */\n \t__u32 kernel_crc;\n-\t/* 228-235: Unused at present */\n-\tchar reserved1[8];\n+\t/* 228-231: Unused at present */\n+\tchar reserved1[4];\n+\t/* 222-235: Openwrt: real rootfs length */\n+\t__u32 real_rootfs_length;\n \t/* 236-239: CRC32 of header excluding last 20 bytes */\n \t__u32 header_crc;\n \t/* 240-255: Unused at present */\n--- a/drivers/mtd/parsers/parser_imagetag.c\n+++ b/drivers/mtd/parsers/parser_imagetag.c\n@@ -136,7 +136,8 @@ static int bcm963xx_parse_imagetag_parti\n \t\t} else {\n \t\t\t/* OpenWrt layout */\n \t\t\trootfsaddr = kerneladdr + kernellen;\n-\t\t\trootfslen = spareaddr - rootfsaddr;\n+\t\t\trootfslen = buf->real_rootfs_length;\n+\t\t\tspareaddr = rootfsaddr + rootfslen;\n \t\t}\n \t} else {\n \t\tgoto out;\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/402_bcm63xx_enet_vlan_incoming_fixed.patch",
    "content": "--- a/drivers/net/ethernet/broadcom/bcm63xx_enet.c\n+++ b/drivers/net/ethernet/broadcom/bcm63xx_enet.c\n@@ -1627,7 +1627,7 @@ static int bcm_enet_change_mtu(struct ne\n \t\treturn -EBUSY;\n \n \t/* add ethernet header + vlan tag size */\n-\tactual_mtu += VLAN_ETH_HLEN;\n+\tactual_mtu += VLAN_ETH_HLEN + VLAN_HLEN;\n \n \t/*\n \t * setup maximum size before we get overflow mark in\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/403-6358-enet1-external-mii-clk.patch",
    "content": "--- a/arch/mips/bcm63xx/boards/board_common.c\n+++ b/arch/mips/bcm63xx/boards/board_common.c\n@@ -97,6 +97,8 @@ void __init board_early_setup(const stru\n \t\tif (BCMCPU_IS_6348())\n \t\t\tval |= GPIO_MODE_6348_G3_EXT_MII |\n \t\t\t\tGPIO_MODE_6348_G0_EXT_MII;\n+\t\telse if (BCMCPU_IS_6358())\n+\t\t\tval |= GPIO_MODE_6358_ENET1_MII_CLK_INV;\n \t}\n \n \tbcm_gpio_writel(val, GPIO_MODE_REG);\n--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h\n+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h\n@@ -652,6 +652,8 @@\n #define GPIO_MODE_6358_EXTRA_SPI_SS\t(1 << 7)\n #define GPIO_MODE_6358_SERIAL_LED\t(1 << 10)\n #define GPIO_MODE_6358_UTOPIA\t\t(1 << 12)\n+#define GPIO_MODE_6358_ENET1_MII_CLK_INV (1 << 30)\n+#define GPIO_MODE_6358_ENET0_MII_CLK_INV (1 << 31)\n \n #define GPIO_MODE_6368_ANALOG_AFE_0\t(1 << 0)\n #define GPIO_MODE_6368_ANALOG_AFE_1\t(1 << 1)\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/404-NET-bcm63xx_enet-move-phy_-dis-connect-into-probe-re.patch",
    "content": "From 7fa63fdde703aaabaa7199ae879219737a98a3f3 Mon Sep 17 00:00:00 2001\nFrom: Jonas Gorski <jonas.gorski@gmail.com>\nDate: Fri, 6 Jan 2012 12:24:18 +0100\nSubject: [PATCH] NET: bcm63xx_enet: move phy_(dis)connect into probe/remove\n\nOnly connect/disconnect the phy during probe and remove, not during any\nopen/close. The phy seldom changes during the runtime, and disconnecting\nthe phy during close will prevent it from keeping any configuration over\na down/up cycle.\n\nSigned-off-by: Jonas Gorski <jonas.gorski@gmail.com>\n---\n drivers/net/ethernet/broadcom/bcm63xx_enet.c | 158 +++++++++++++--------------\n 1 file changed, 78 insertions(+), 80 deletions(-)\n\n--- a/drivers/net/ethernet/broadcom/bcm63xx_enet.c\n+++ b/drivers/net/ethernet/broadcom/bcm63xx_enet.c\n@@ -892,10 +892,8 @@ static int bcm_enet_open(struct net_devi\n \tstruct bcm_enet_priv *priv;\n \tstruct sockaddr addr;\n \tstruct device *kdev;\n-\tstruct phy_device *phydev;\n \tint i, ret;\n \tunsigned int size;\n-\tchar phy_id[MII_BUS_ID_SIZE + 3];\n \tvoid *p;\n \tu32 val;\n \n@@ -903,31 +901,10 @@ static int bcm_enet_open(struct net_devi\n \tkdev = &priv->pdev->dev;\n \n \tif (priv->has_phy) {\n-\t\t/* connect to PHY */\n-\t\tsnprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,\n-\t\t\t priv->mii_bus->id, priv->phy_id);\n-\n-\t\tphydev = phy_connect(dev, phy_id, bcm_enet_adjust_phy_link,\n-\t\t\t\t     PHY_INTERFACE_MODE_MII);\n-\n-\t\tif (IS_ERR(phydev)) {\n-\t\t\tdev_err(kdev, \"could not attach to PHY\\n\");\n-\t\t\treturn PTR_ERR(phydev);\n-\t\t}\n-\n-\t\t/* mask with MAC supported features */\n-\t\tphy_support_sym_pause(phydev);\n-\t\tphy_set_max_speed(phydev, SPEED_100);\n-\t\tphy_set_sym_pause(phydev, priv->pause_rx, priv->pause_rx,\n-\t\t\t\t  priv->pause_auto);\n-\n-\t\tphy_attached_info(phydev);\n-\n+\t\t/* Reset state */\n \t\tpriv->old_link = 0;\n \t\tpriv->old_duplex = -1;\n \t\tpriv->old_pause = -1;\n-\t} else {\n-\t\tphydev = NULL;\n \t}\n \n \t/* mask all interrupts and request them */\n@@ -937,7 +914,7 @@ static int bcm_enet_open(struct net_devi\n \n \tret = request_irq(dev->irq, bcm_enet_isr_mac, 0, dev->name, dev);\n \tif (ret)\n-\t\tgoto out_phy_disconnect;\n+\t\treturn ret;\n \n \tret = request_irq(priv->irq_rx, bcm_enet_isr_dma, 0,\n \t\t\t  dev->name, dev);\n@@ -1099,8 +1076,8 @@ static int bcm_enet_open(struct net_devi\n \tenet_dmac_writel(priv, priv->dma_chan_int_mask,\n \t\t\t ENETDMAC_IRMASK, priv->tx_chan);\n \n-\tif (phydev)\n-\t\tphy_start(phydev);\n+\tif (priv->has_phy)\n+\t\tphy_start(dev->phydev);\n \telse\n \t\tbcm_enet_adjust_link(dev);\n \n@@ -1130,10 +1107,6 @@ out_freeirq_rx:\n out_freeirq:\n \tfree_irq(dev->irq, dev);\n \n-out_phy_disconnect:\n-\tif (phydev)\n-\t\tphy_disconnect(phydev);\n-\n \treturn ret;\n }\n \n@@ -1226,10 +1199,6 @@ static int bcm_enet_stop(struct net_devi\n \tfree_irq(priv->irq_rx, dev);\n \tfree_irq(dev->irq, dev);\n \n-\t/* release phy */\n-\tif (priv->has_phy)\n-\t\tphy_disconnect(dev->phydev);\n-\n \t/* reset BQL after forced tx reclaim to not kernel panic */\n \tnetdev_reset_queue(dev);\n \n@@ -1797,14 +1766,47 @@ static int bcm_enet_probe(struct platfor\n \n \t/* do minimal hardware init to be able to probe mii bus */\n \tbcm_enet_hw_preinit(priv);\n+\tspin_lock_init(&priv->rx_lock);\n+\n+\t/* init rx timeout (used for oom) */\n+\ttimer_setup(&priv->rx_timeout, bcm_enet_refill_rx_timer, 0);\n+\n+\t/* init the mib update lock&work */\n+\tmutex_init(&priv->mib_update_lock);\n+\tINIT_WORK(&priv->mib_update_task, bcm_enet_update_mib_counters_defer);\n+\n+\t/* zero mib counters */\n+\tfor (i = 0; i < ENET_MIB_REG_COUNT; i++)\n+\t\tenet_writel(priv, 0, ENET_MIB_REG(i));\n+\n+\t/* register netdevice */\n+\tdev->netdev_ops = &bcm_enet_ops;\n+\tnetif_napi_add(dev, &priv->napi, bcm_enet_poll, 16);\n+\n+\tdev->ethtool_ops = &bcm_enet_ethtool_ops;\n+\t/* MTU range: 46 - 2028 */\n+\tdev->min_mtu = ETH_ZLEN - ETH_HLEN;\n+\tdev->max_mtu = BCMENET_MAX_MTU - VLAN_ETH_HLEN;\n+\tSET_NETDEV_DEV(dev, &pdev->dev);\n+\n+\tret = register_netdev(dev);\n+\tif (ret)\n+\t\tgoto out_uninit_hw;\n+\n+\tnetif_carrier_off(dev);\n+\tplatform_set_drvdata(pdev, dev);\n+\tpriv->pdev = pdev;\n+\tpriv->net_dev = dev;\n \n \t/* MII bus registration */\n \tif (priv->has_phy) {\n+\t\tstruct phy_device *phydev;\n+\t\tchar phy_id[MII_BUS_ID_SIZE + 3];\n \n \t\tpriv->mii_bus = mdiobus_alloc();\n \t\tif (!priv->mii_bus) {\n \t\t\tret = -ENOMEM;\n-\t\t\tgoto out_uninit_hw;\n+\t\t\tgoto out_unregister_netdev;\n \t\t}\n \n \t\tbus = priv->mii_bus;\n@@ -1828,6 +1830,26 @@ static int bcm_enet_probe(struct platfor\n \t\t\tdev_err(&pdev->dev, \"unable to register mdio bus\\n\");\n \t\t\tgoto out_free_mdio;\n \t\t}\n+\n+\t\t/* connect to PHY */\n+\t\tsnprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,\n+\t\t\t priv->mii_bus->id, priv->phy_id);\n+\n+\t\tphydev = phy_connect(dev, phy_id, bcm_enet_adjust_phy_link,\n+\t\t\t\t     PHY_INTERFACE_MODE_MII);\n+\n+\t\tif (IS_ERR(phydev)) {\n+\t\t\tdev_err(&pdev->dev, \"could not attach to PHY\\n\");\n+\t\t\tgoto out_unregister_mdio;\n+\t\t}\n+\n+\t\t/* mask with MAC supported features */\n+\t\tphy_support_sym_pause(phydev);\n+\t\tphy_set_max_speed(phydev, SPEED_100);\n+\t\tphy_set_sym_pause(phydev, priv->pause_rx, priv->pause_rx,\n+\t\t\t\t  priv->pause_auto);\n+\n+\t\tphy_attached_info(phydev);\n \t} else {\n \n \t\t/* run platform code to initialize PHY device */\n@@ -1835,45 +1857,16 @@ static int bcm_enet_probe(struct platfor\n \t\t    pd->mii_config(dev, 1, bcm_enet_mdio_read_mii,\n \t\t\t\t   bcm_enet_mdio_write_mii)) {\n \t\t\tdev_err(&pdev->dev, \"unable to configure mdio bus\\n\");\n-\t\t\tgoto out_uninit_hw;\n+\t\t\tgoto out_unregister_netdev;\n \t\t}\n \t}\n \n-\tspin_lock_init(&priv->rx_lock);\n-\n-\t/* init rx timeout (used for oom) */\n-\ttimer_setup(&priv->rx_timeout, bcm_enet_refill_rx_timer, 0);\n-\n-\t/* init the mib update lock&work */\n-\tmutex_init(&priv->mib_update_lock);\n-\tINIT_WORK(&priv->mib_update_task, bcm_enet_update_mib_counters_defer);\n-\n-\t/* zero mib counters */\n-\tfor (i = 0; i < ENET_MIB_REG_COUNT; i++)\n-\t\tenet_writel(priv, 0, ENET_MIB_REG(i));\n-\n-\t/* register netdevice */\n-\tdev->netdev_ops = &bcm_enet_ops;\n-\tnetif_napi_add(dev, &priv->napi, bcm_enet_poll, 16);\n-\n-\tdev->ethtool_ops = &bcm_enet_ethtool_ops;\n-\t/* MTU range: 46 - 2028 */\n-\tdev->min_mtu = ETH_ZLEN - ETH_HLEN;\n-\tdev->max_mtu = BCMENET_MAX_MTU - VLAN_ETH_HLEN;\n-\tSET_NETDEV_DEV(dev, &pdev->dev);\n-\n-\tret = register_netdev(dev);\n-\tif (ret)\n-\t\tgoto out_unregister_mdio;\n-\n-\tnetif_carrier_off(dev);\n-\tplatform_set_drvdata(pdev, dev);\n-\tpriv->pdev = pdev;\n-\tpriv->net_dev = dev;\n-\n \treturn 0;\n \n out_unregister_mdio:\n+\tif (dev->phydev)\n+\t\tphy_disconnect(dev->phydev);\n+\n \tif (priv->mii_bus)\n \t\tmdiobus_unregister(priv->mii_bus);\n \n@@ -1881,6 +1874,9 @@ out_free_mdio:\n \tif (priv->mii_bus)\n \t\tmdiobus_free(priv->mii_bus);\n \n+out_unregister_netdev:\n+\tunregister_netdev(dev);\n+\n out_uninit_hw:\n \t/* turn off mdc clock */\n \tenet_writel(priv, 0, ENET_MIISC_REG);\n@@ -1911,6 +1907,7 @@ static int bcm_enet_remove(struct platfo\n \tenet_writel(priv, 0, ENET_MIISC_REG);\n \n \tif (priv->has_phy) {\n+\t\tphy_disconnect(dev->phydev);\n \t\tmdiobus_unregister(priv->mii_bus);\n \t\tmdiobus_free(priv->mii_bus);\n \t} else {\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/408-bcm63xx_enet-enable-rgmii-clock-on-external-ports.patch",
    "content": "From d8237d704fc25eb2fc25ef4403608b78c6a6d4be Mon Sep 17 00:00:00 2001\nFrom: Jonas Gorski <jonas.gorski@gmail.com>\nDate: Sun, 15 Jul 2012 20:08:57 +0200\nSubject: [PATCH 54/81] bcm63xx_enet: enable rgmii clock on external ports\n\n---\n arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h |   13 +++++++++++++\n drivers/net/ethernet/broadcom/bcm63xx_enet.c      |   12 ++++++++++++\n 2 files changed, 25 insertions(+), 0 deletions(-)\n\n--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h\n+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h\n@@ -968,6 +968,19 @@\n #define ENETSW_PORTOV_FDX_MASK\t\t(1 << 1)\n #define ENETSW_PORTOV_LINKUP_MASK\t(1 << 0)\n \n+/* Port RGMII control register */\n+#define ENETSW_RGMII_CTRL_REG(x)\t(0x60 + (x))\n+#define ENETSW_RGMII_CTRL_GMII_CLK_EN\t(1 << 7)\n+#define ENETSW_RGMII_CTRL_MII_OVERRIDE_EN (1 << 6)\n+#define ENETSW_RGMII_CTRL_MII_MODE_MASK\t(3 << 4)\n+#define ENETSW_RGMII_CTRL_RGMII_MODE\t(0 << 4)\n+#define ENETSW_RGMII_CTRL_MII_MODE\t(1 << 4)\n+#define ENETSW_RGMII_CTRL_RVMII_MODE\t(2 << 4)\n+#define ENETSW_RGMII_CTRL_TIMING_SEL_EN\t(1 << 0)\n+\n+/* Port RGMII timing register */\n+#define ENETSW_RGMII_TIMING_REG(x)\t(0x68 + (x))\n+\n /* MDIO control register */\n #define ENETSW_MDIOC_REG\t\t(0xb0)\n #define ENETSW_MDIOC_EXT_MASK\t\t(1 << 16)\n--- a/drivers/net/ethernet/broadcom/bcm63xx_enet.c\n+++ b/drivers/net/ethernet/broadcom/bcm63xx_enet.c\n@@ -2180,6 +2180,18 @@ static int bcm_enetsw_open(struct net_de\n \t\tpriv->sw_port_link[i] = 0;\n \t}\n \n+\t/* enable external ports */\n+\tfor (i = ENETSW_RGMII_PORT0; i < priv->num_ports; i++) {\n+\t\tu8 rgmii_ctrl;\n+\n+\t\tif (!priv->used_ports[i].used)\n+\t\t\tcontinue;\n+\n+\t\trgmii_ctrl = enetsw_readb(priv, ENETSW_RGMII_CTRL_REG(i));\n+\t\trgmii_ctrl |= ENETSW_RGMII_CTRL_GMII_CLK_EN;\n+\t\tenetsw_writeb(priv, rgmii_ctrl, ENETSW_RGMII_CTRL_REG(i));\n+\t}\n+\n \t/* reset mib */\n \tval = enetsw_readb(priv, ENETSW_GMCR_REG);\n \tval |= ENETSW_GMCR_RST_MIB_MASK;\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/411-MIPS-BCM63XX-Register-SPI-flash-if-present.patch",
    "content": "From d135d94b3d1fe599d13e7198d5f502912d694c13 Mon Sep 17 00:00:00 2001\nFrom: Jonas Gorski <jonas.gorski@gmail.com>\nDate: Sun, 3 Jul 2011 15:00:38 +0200\nSubject: [PATCH 29/60] MIPS: BCM63XX: Register SPI flash if present\n\nSigned-off-by: Jonas Gorski <jonas.gorski@gmail.com>\n---\n arch/mips/bcm63xx/dev-flash.c                     |   35 +++++++++++++++++++-\n arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h |    2 +\n 2 files changed, 33 insertions(+), 2 deletions(-)\n\n--- a/arch/mips/bcm63xx/dev-flash.c\n+++ b/arch/mips/bcm63xx/dev-flash.c\n@@ -17,6 +17,9 @@\n #include <linux/mtd/partitions.h>\n #include <linux/mtd/physmap.h>\n #include <linux/mtd/spi-nor.h>\n+#include <linux/of.h>\n+#include <linux/spi/spi.h>\n+#include <linux/spi/flash.h>\n \n #include <bcm63xx_cpu.h>\n #include <bcm63xx_dev_flash.h>\n@@ -66,6 +69,41 @@ void __init bcm63xx_flash_force_phys_bas\n \tmtd_resources[0].end = end;\n }\n \n+static struct spi_board_info bcm63xx_spi_flash_info[] = {\n+\t{\n+\t\t.bus_num\t= 0,\n+\t\t.chip_select\t= 0,\n+\t\t.mode\t\t= 0,\n+\t\t.max_speed_hz\t= 781000,\n+\t\t.modalias\t= \"m25p80\",\n+\t},\n+};\n+\n+static void bcm63xx_of_update_spi_flash_speed(struct device_node *np,\n+\t\t\t\t\t       unsigned int new_hz)\n+{\n+\tstruct property *max_hz;\n+\t__be32 *hz;\n+\n+\tmax_hz = kzalloc(sizeof(*max_hz) + sizeof(*hz), GFP_KERNEL);\n+\tif (!max_hz)\n+\t\treturn;\n+\n+\tmax_hz->name = kstrdup(\"spi-max-frequency\", GFP_KERNEL);\n+\tif (!max_hz->name) {\n+\t\tkfree(max_hz);\n+\t\treturn;\n+\t}\n+\n+\tmax_hz->value = max_hz + 1;\n+\tmax_hz->length = sizeof(*hz);\n+\n+\thz = max_hz->value;\n+\t*hz = cpu_to_be32(new_hz);\n+\n+\tof_update_property(np, max_hz);\n+}\n+\n static int __init bcm63xx_detect_flash_type(void)\n {\n \tu32 val;\n@@ -73,9 +111,15 @@ static int __init bcm63xx_detect_flash_t\n \tswitch (bcm63xx_get_cpu_id()) {\n \tcase BCM6318_CPU_ID:\n \t\t/* only support serial flash */\n+\t\tbcm63xx_spi_flash_info[0].max_speed_hz = 62500000;\n \t\treturn BCM63XX_FLASH_TYPE_SERIAL;\n \tcase BCM6328_CPU_ID:\n \t\tval = bcm_misc_readl(MISC_STRAPBUS_6328_REG);\n+\t\tif (val & STRAPBUS_6328_HSSPI_CLK_FAST)\n+\t\t\tbcm63xx_spi_flash_info[0].max_speed_hz = 33333334;\n+\t\telse\n+\t\t\tbcm63xx_spi_flash_info[0].max_speed_hz = 16666667;\n+\n \t\tif (val & STRAPBUS_6328_BOOT_SEL_SERIAL)\n \t\t\treturn BCM63XX_FLASH_TYPE_SERIAL;\n \t\telse\n@@ -94,18 +138,31 @@ static int __init bcm63xx_detect_flash_t\n \t\t\treturn BCM63XX_FLASH_TYPE_SERIAL;\n \tcase BCM6362_CPU_ID:\n \t\tval = bcm_misc_readl(MISC_STRAPBUS_6362_REG);\n+\t\tif (val & STRAPBUS_6362_HSSPI_CLK_FAST)\n+\t\t\tbcm63xx_spi_flash_info[0].max_speed_hz = 50000000;\n+\t\telse\n+\t\t\tbcm63xx_spi_flash_info[0].max_speed_hz = 20000000;\n+\n \t\tif (val & STRAPBUS_6362_BOOT_SEL_SERIAL)\n \t\t\treturn BCM63XX_FLASH_TYPE_SERIAL;\n \t\telse\n \t\t\treturn BCM63XX_FLASH_TYPE_NAND;\n \tcase BCM63268_CPU_ID:\n \t\tval = bcm_misc_readl(MISC_STRAPBUS_63268_REG);\n+\t\tif (val & STRAPBUS_63268_HSSPI_CLK_FAST)\n+\t\t\tbcm63xx_spi_flash_info[0].max_speed_hz = 50000000;\n+\t\telse\n+\t\t\tbcm63xx_spi_flash_info[0].max_speed_hz = 20000000;\n+\n \t\tif (val & STRAPBUS_63268_BOOT_SEL_SERIAL)\n \t\t\treturn BCM63XX_FLASH_TYPE_SERIAL;\n \t\telse\n \t\t\treturn BCM63XX_FLASH_TYPE_NAND;\n \tcase BCM6368_CPU_ID:\n \t\tval = bcm_gpio_readl(GPIO_STRAPBUS_REG);\n+\t\tif (val & STRAPBUS_6368_SPI_CLK_FAST)\n+\t\t\tbcm63xx_spi_flash_info[0].max_speed_hz = 20000000;\n+\n \t\tswitch (val & STRAPBUS_6368_BOOT_SEL_MASK) {\n \t\tcase STRAPBUS_6368_BOOT_SEL_NAND:\n \t\t\treturn BCM63XX_FLASH_TYPE_NAND;\n@@ -177,6 +234,7 @@ void __init bcm63xx_flash_detect(void)\n \n int __init bcm63xx_flash_register(void)\n {\n+\tstruct device_node *np;\n \tu32 val;\n \n \tswitch (flash_type) {\n@@ -196,8 +254,14 @@ int __init bcm63xx_flash_register(void)\n \n \t\treturn platform_device_register(&mtd_dev);\n \tcase BCM63XX_FLASH_TYPE_SERIAL:\n-\t\tpr_warn(\"unsupported serial flash detected\\n\");\n-\t\treturn -ENODEV;\n+\t\tnp = of_find_compatible_node(NULL, NULL, \"jedec,spi-nor\");\n+\t\tif (np) {\n+\t\t\tbcm63xx_of_update_spi_flash_speed(np, bcm63xx_spi_flash_info[0].max_speed_hz);\n+\t\t\tof_node_put(np);\n+\t\t\treturn 0;\n+\t\t} else {\n+\t\t\treturn -ENODEV;\n+\t\t}\n \tcase BCM63XX_FLASH_TYPE_NAND:\n \t\tpr_warn(\"unsupported NAND flash detected\\n\");\n \t\treturn -ENODEV;\n--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h\n+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h\n@@ -709,6 +709,7 @@\n #define GPIO_STRAPBUS_REG\t\t0x40\n #define STRAPBUS_6358_BOOT_SEL_PARALLEL (1 << 1)\n #define STRAPBUS_6358_BOOT_SEL_SERIAL\t(0 << 1)\n+#define STRAPBUS_6368_SPI_CLK_FAST\t(1 << 6)\n #define STRAPBUS_6368_BOOT_SEL_MASK\t0x3\n #define STRAPBUS_6368_BOOT_SEL_NAND\t0\n #define STRAPBUS_6368_BOOT_SEL_SERIAL\t1\n@@ -1565,6 +1566,7 @@\n #define IDDQ_CTRL_63268_USBH\t\t(1 << 4)\n \n #define MISC_STRAPBUS_6328_REG\t\t0x240\n+#define STRAPBUS_6328_HSSPI_CLK_FAST\t(1 << 4)\n #define STRAPBUS_6328_FCVO_SHIFT\t7\n #define STRAPBUS_6328_FCVO_MASK\t\t(0x1f << STRAPBUS_6328_FCVO_SHIFT)\n #define STRAPBUS_6328_BOOT_SEL_SERIAL\t(1 << 18)\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/413-BCM63XX-allow-providing-fixup-data-in-board-data.patch",
    "content": "From 8879e209111192c5e9752d7bd203cf7582693328 Mon Sep 17 00:00:00 2001\nFrom: Jonas Gorski <jonas.gorski@gmail.com>\nDate: Thu, 3 May 2012 14:40:03 +0200\nSubject: [PATCH 58/72] BCM63XX: allow providing fixup data in board data\n\n---\n arch/mips/bcm63xx/boards/board_bcm963xx.c           |    9 ++++++++-\n arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h |   10 ++++++++++\n 2 files changed, 18 insertions(+), 1 deletion(-)\n\n--- a/arch/mips/bcm63xx/boards/board_common.c\n+++ b/arch/mips/bcm63xx/boards/board_common.c\n@@ -31,6 +31,7 @@\n #include <bcm63xx_dev_usb_ohci.h>\n #include <bcm63xx_dev_usb_usbd.h>\n #include <board_bcm963xx.h>\n+#include <pci_ath9k_fixup.h>\n \n #include \"board_common.h\"\n \n@@ -177,6 +178,7 @@ static struct of_device_id of_ids[] = {\n int __init board_register_devices(void)\n {\n \tint usbh_ports = 0;\n+\tint i;\n \n #if CONFIG_OF\n \tif (of_have_populated_dt()) {\n@@ -241,6 +243,10 @@ int __init board_register_devices(void)\n \t\t\t\t\tboard.ephy_reset_gpio_flags);\n \t}\n \n+\t/* register any fixups */\n+\tfor (i = 0; i < board.has_caldata; i++)\n+\t\tpci_enable_ath9k_fixup(board.caldata[i].slot, board.caldata[i].caldata_offset);\n+\n \treturn 0;\n }\n \n--- a/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h\n+++ b/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h\n@@ -9,6 +9,7 @@\n #include <bcm63xx_dev_enet.h>\n #include <bcm63xx_dev_usb_usbd.h>\n #include <bcm63xx_fallback_sprom.h>\n+#include <pci_ath9k_fixup.h>\n \n /*\n  * flash mapping\n@@ -16,6 +17,11 @@\n #define BCM963XX_CFE_VERSION_OFFSET\t0x570\n #define BCM963XX_NVRAM_OFFSET\t\t0x580\n \n+struct ath9k_caldata {\n+\tunsigned int\tslot;\n+\tu32\t\tcaldata_offset;\n+};\n+\n /*\n  * board definition\n  */\n@@ -33,6 +39,10 @@ struct board_info {\n \tunsigned int\thas_ehci0:1;\n \tunsigned int\thas_usbd:1;\n \tunsigned int\tuse_fallback_sprom:1;\n+\tunsigned int\thas_caldata:2;\n+\n+\t/* wifi calibration data config */\n+\tstruct ath9k_caldata caldata[2];\n \n \t/* ethernet config */\n \tstruct bcm63xx_enet_platform_data enet0;\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/415-MIPS-BCM63XX-export-the-attached-flash-type.patch",
    "content": "From 066f1e37742ee434496d32a41a9284458de96742 Mon Sep 17 00:00:00 2001\nFrom: Jonas Gorski <jogo@openwrt.org>\nDate: Mon, 13 Jan 2014 12:12:30 +0100\nSubject: [PATCH] MIPS: BCM63XX: export the attached flash type\n\nSigned-off-by: Jonas Gorski <jogo@openwrt.org>\n---\n arch/mips/bcm63xx/dev-flash.c                          | 5 +++++\n arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_flash.h | 2 ++\n 2 files changed, 7 insertions(+)\n\n--- a/arch/mips/bcm63xx/dev-flash.c\n+++ b/arch/mips/bcm63xx/dev-flash.c\n@@ -271,3 +271,8 @@ int __init bcm63xx_flash_register(void)\n \t\treturn -ENODEV;\n \t}\n }\n+\n+int bcm63xx_flash_get_type(void)\n+{\n+\treturn flash_type;\n+}\n--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_flash.h\n+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_flash.h\n@@ -14,4 +14,6 @@ void bcm63xx_flash_force_phys_base_addre\n \n int __init bcm63xx_flash_register(void);\n \n+int bcm63xx_flash_get_type(void);\n+\n #endif /* __BCM63XX_FLASH_H */\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/416-BCM63XX-add-a-fixup-for-ath9k-devices.patch",
    "content": "From bbebbf735a02b6d044ed928978ab4bd5f1833364 Mon Sep 17 00:00:00 2001\nFrom: Jonas Gorski <jonas.gorski@gmail.com>\nDate: Thu, 3 May 2012 14:36:11 +0200\nSubject: [PATCH 61/72] BCM63XX: add a fixup for ath9k devices\n\n---\n arch/mips/bcm63xx/Makefile                         |    3 +-\n arch/mips/bcm63xx/pci-ath9k-fixup.c                |  190 ++++++++++++++++++++\n .../include/asm/mach-bcm63xx/pci_ath9k_fixup.h     |    7 +\n 3 files changed, 199 insertions(+), 1 deletion(-)\n create mode 100644 arch/mips/bcm63xx/pci-ath9k-fixup.c\n create mode 100644 arch/mips/include/asm/mach-bcm63xx/pci_ath9k_fixup.h\n\n--- a/arch/mips/bcm63xx/Makefile\n+++ b/arch/mips/bcm63xx/Makefile\n@@ -3,7 +3,7 @@ obj-y\t\t+= clk.o cpu.o cs.o gpio.o irq.o\n \t\t   setup.o timer.o dev-enet.o dev-flash.o dev-pcmcia.o \\\n \t\t   dev-rng.o dev-wdt.o \\\n \t\t   dev-usb-ehci.o dev-usb-ohci.o dev-usb-usbd.o usb-common.o \\\n-\t\t   sprom.o\n+\t\t   pci-ath9k-fixup.o sprom.o\n obj-$(CONFIG_EARLY_PRINTK)\t+= early_printk.o\n \n obj-y\t\t+= boards/\n--- /dev/null\n+++ b/arch/mips/bcm63xx/pci-ath9k-fixup.c\n@@ -0,0 +1,201 @@\n+/*\n+ *  Broadcom BCM63XX Ath9k EEPROM fixup helper.\n+ *\n+ *  Copytight (C) 2012 Jonas Gorski <jonas.gorski@gmail.com>\n+ *\n+ *  Based on\n+ *\n+ *  Atheros AP94 reference board PCI initialization\n+ *\n+ *  Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>\n+ *\n+ *  This program is free software; you can redistribute it and/or modify it\n+ *  under the terms of the GNU General Public License version 2 as published\n+ *  by the Free Software Foundation.\n+ */\n+\n+#include <linux/if_ether.h>\n+#include <linux/pci.h>\n+#include <linux/delay.h>\n+#include <linux/ath9k_platform.h>\n+\n+#include <bcm63xx_cpu.h>\n+#include <bcm63xx_regs.h>\n+#include <bcm63xx_io.h>\n+#include <bcm63xx_nvram.h>\n+#include <bcm63xx_dev_pci.h>\n+#include <bcm63xx_dev_flash.h>\n+#include <pci_ath9k_fixup.h>\n+\n+#define bcm_hsspi_writel(v, o)\tbcm_rset_writel(RSET_HSSPI, (v), (o))\n+\n+struct ath9k_fixup {\n+\tunsigned slot;\n+\tu8 mac[ETH_ALEN];\n+\tstruct ath9k_platform_data pdata;\n+};\n+\n+static int ath9k_num_fixups;\n+static struct ath9k_fixup ath9k_fixups[2] = {\n+\t{\n+\t\t.slot = 255,\n+\t\t.pdata = {\n+\t\t\t.led_pin\t= -1,\n+\t\t},\n+\t},\n+\t{\n+\t\t.slot = 255,\n+\t\t.pdata = {\n+\t\t\t.led_pin\t= -1,\n+\t\t},\n+\t},\n+};\n+\n+static u16 *bcm63xx_read_eeprom(u16 *eeprom, u32 offset)\n+{\n+\tu32 addr;\n+\n+\tif (BCMCPU_IS_6328()) {\n+\t\taddr = 0x18000000;\n+\t} else {\n+\t\taddr = bcm_mpi_readl(MPI_CSBASE_REG(0));\n+\t\taddr &= MPI_CSBASE_BASE_MASK;\n+\t}\n+\n+\tswitch (bcm63xx_flash_get_type()) {\n+\tcase BCM63XX_FLASH_TYPE_PARALLEL:\n+\t\tmemcpy(eeprom, (void *)KSEG1ADDR(addr + offset), ATH9K_PLAT_EEP_MAX_WORDS * sizeof(u16));\n+\t\treturn eeprom;\n+\tcase BCM63XX_FLASH_TYPE_SERIAL:\n+\t\t/* the first megabyte is memory mapped */\n+\t\tif (offset < 0x100000) {\n+\t\t\tmemcpy(eeprom, (void *)KSEG1ADDR(addr + offset), ATH9K_PLAT_EEP_MAX_WORDS * sizeof(u16));\n+\t\t\treturn eeprom;\n+\t\t}\n+\n+\t\tif (BCMCPU_IS_6328()) {\n+\t\t\t/* we can change the memory mapped megabyte */\n+\t\t\tbcm_hsspi_writel(offset & 0xf00000, 0x18);\n+\t\t\tmemcpy(eeprom, (void *)KSEG1ADDR(addr + (offset & 0xfffff)), ATH9K_PLAT_EEP_MAX_WORDS * sizeof(u16));\n+\t\t\tbcm_hsspi_writel(0, 0x18);\n+\t\t\treturn eeprom;\n+\t\t}\n+\t\t/* can't do anything here without talking to the SPI controller. */\n+\t\t/* Fall through */\n+\tcase BCM63XX_FLASH_TYPE_NAND:\n+\tdefault:\n+\t\treturn NULL;\n+\t}\n+}\n+\n+static void ath9k_pci_fixup(struct pci_dev *dev)\n+{\n+\tvoid __iomem *mem;\n+\tstruct ath9k_platform_data *pdata = NULL;\n+\tstruct pci_dev *bridge = pci_upstream_bridge(dev);\n+\tu16 *cal_data = NULL;\n+\tu16 cmd;\n+\tu32 bar0;\n+\tu32 val;\n+\tunsigned i;\n+\n+\tfor (i = 0; i < ath9k_num_fixups; i++) {\n+\t\tif (ath9k_fixups[i].slot != PCI_SLOT(dev->devfn))\n+\t\t\tcontinue;\n+\n+\t\tcal_data = ath9k_fixups[i].pdata.eeprom_data;\n+\t\tpdata = &ath9k_fixups[i].pdata;\n+\t\tbreak;\n+\t}\n+\n+\tif (cal_data == NULL)\n+\t\treturn;\n+\n+\tif (*cal_data != 0xa55a) {\n+\t\tpr_err(\"pci %s: invalid calibration data\\n\", pci_name(dev));\n+\t\treturn;\n+\t}\n+\n+\tpr_info(\"pci %s: fixup device configuration\\n\", pci_name(dev));\n+\n+\tswitch (bcm63xx_get_cpu_id()) {\n+\tcase BCM6328_CPU_ID:\n+\t\tval = BCM_PCIE_MEM_BASE_PA_6328;\n+\t\tbreak;\n+\tcase BCM6348_CPU_ID:\n+\tcase BCM6358_CPU_ID:\n+\tcase BCM6368_CPU_ID:\n+\t\tval = BCM_PCI_MEM_BASE_PA;\n+\t\tbreak;\n+\tdefault:\n+\t\tBUG();\n+\t}\n+\n+\tmem = ioremap(val, 0x10000);\n+\tif (!mem) {\n+\t\tpr_err(\"pci %s: ioremap error\\n\", pci_name(dev));\n+\t\treturn;\n+\t}\n+\n+\tif (bridge)\n+\t\tpci_enable_device(bridge);\n+\n+\tpci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &bar0);\n+\tpci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &bar0);\n+\tpci_write_config_dword(dev, PCI_BASE_ADDRESS_0, val);\n+\n+\tpci_read_config_word(dev, PCI_COMMAND, &cmd);\n+\tcmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;\n+\tpci_write_config_word(dev, PCI_COMMAND, cmd);\n+\n+\t/* set offset to first reg address */\n+\tcal_data += 3;\n+\twhile(*cal_data != 0xffff) {\n+\t\tu32 reg;\n+\t\treg = *cal_data++;\n+\t\tval = *cal_data++;\n+\t\tval |= (*cal_data++) << 16;\n+\n+\t\twritel(val, mem + reg);\n+\t\tudelay(100);\n+\t}\n+\n+\tpci_read_config_dword(dev, PCI_VENDOR_ID, &val);\n+\tdev->vendor = val & 0xffff;\n+\tdev->device = (val >> 16) & 0xffff;\n+\n+\tpci_read_config_dword(dev, PCI_CLASS_REVISION, &val);\n+\tdev->revision = val & 0xff;\n+\tdev->class = val >> 8; /* upper 3 bytes */\n+\n+\tpci_read_config_word(dev, PCI_COMMAND, &cmd);\n+\tcmd &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);\n+\tpci_write_config_word(dev, PCI_COMMAND, cmd);\n+\n+\tpci_write_config_dword(dev, PCI_BASE_ADDRESS_0, bar0);\n+\n+\tif (bridge)\n+\t\tpci_disable_device(bridge);\n+\n+\tiounmap(mem);\n+\n+\tdev->dev.platform_data = pdata;\n+}\n+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATHEROS, PCI_ANY_ID, ath9k_pci_fixup);\n+\n+void __init pci_enable_ath9k_fixup(unsigned slot, u32 offset)\n+{\n+\tif (ath9k_num_fixups >= ARRAY_SIZE(ath9k_fixups))\n+\t\treturn;\n+\n+\tath9k_fixups[ath9k_num_fixups].slot = slot;\n+\n+\tif (!bcm63xx_read_eeprom(ath9k_fixups[ath9k_num_fixups].pdata.eeprom_data, offset))\n+\t\treturn;\n+\n+\tif (bcm63xx_nvram_get_mac_address(ath9k_fixups[ath9k_num_fixups].mac))\n+\t\treturn;\n+\n+\tath9k_fixups[ath9k_num_fixups].pdata.macaddr = ath9k_fixups[ath9k_num_fixups].mac;\n+\tath9k_num_fixups++;\n+}\n--- /dev/null\n+++ b/arch/mips/include/asm/mach-bcm63xx/pci_ath9k_fixup.h\n@@ -0,0 +1,7 @@\n+#ifndef _PCI_ATH9K_FIXUP\n+#define _PCI_ATH9K_FIXUP\n+\n+\n+void pci_enable_ath9k_fixup(unsigned slot, u32 offset) __init;\n+\n+#endif /* _PCI_ATH9K_FIXUP */\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/420-BCM63XX-add-endian-check-for-ath9k.patch",
    "content": "--- a/arch/mips/include/asm/mach-bcm63xx/pci_ath9k_fixup.h\n+++ b/arch/mips/include/asm/mach-bcm63xx/pci_ath9k_fixup.h\n@@ -2,6 +2,7 @@\n #define _PCI_ATH9K_FIXUP\n \n \n-void pci_enable_ath9k_fixup(unsigned slot, u32 offset) __init;\n+void pci_enable_ath9k_fixup(unsigned slot, u32 offset,\n+\tunsigned endian_check) __init;\n \n #endif /* _PCI_ATH9K_FIXUP */\n--- a/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h\n+++ b/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h\n@@ -20,6 +20,7 @@\n struct ath9k_caldata {\n \tunsigned int\tslot;\n \tu32\t\tcaldata_offset;\n+\tunsigned int\tendian_check:1;\n };\n \n /*\n--- a/arch/mips/bcm63xx/pci-ath9k-fixup.c\n+++ b/arch/mips/bcm63xx/pci-ath9k-fixup.c\n@@ -183,12 +183,14 @@ static void ath9k_pci_fixup(struct pci_d\n }\n DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATHEROS, PCI_ANY_ID, ath9k_pci_fixup);\n \n-void __init pci_enable_ath9k_fixup(unsigned slot, u32 offset)\n+void __init pci_enable_ath9k_fixup(unsigned slot, u32 offset,\n+\tunsigned endian_check)\n {\n \tif (ath9k_num_fixups >= ARRAY_SIZE(ath9k_fixups))\n \t\treturn;\n \n \tath9k_fixups[ath9k_num_fixups].slot = slot;\n+\tath9k_fixups[ath9k_num_fixups].pdata.endian_check = endian_check;\n \n \tif (!bcm63xx_read_eeprom(ath9k_fixups[ath9k_num_fixups].pdata.eeprom_data, offset))\n \t\treturn;\n--- a/arch/mips/bcm63xx/boards/board_common.c\n+++ b/arch/mips/bcm63xx/boards/board_common.c\n@@ -245,7 +245,8 @@ int __init board_register_devices(void)\n \n \t/* register any fixups */\n \tfor (i = 0; i < board.has_caldata; i++)\n-\t\tpci_enable_ath9k_fixup(board.caldata[i].slot, board.caldata[i].caldata_offset);\n+\t\tpci_enable_ath9k_fixup(board.caldata[i].slot, board.caldata[i].caldata_offset,\n+\t\t\tboard.caldata[i].endian_check);\n \n \treturn 0;\n }\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/421-BCM63XX-add-led-pin-for-ath9k.patch",
    "content": "--- a/arch/mips/bcm63xx/boards/board_common.c\n+++ b/arch/mips/bcm63xx/boards/board_common.c\n@@ -246,7 +246,7 @@ int __init board_register_devices(void)\n \t/* register any fixups */\n \tfor (i = 0; i < board.has_caldata; i++)\n \t\tpci_enable_ath9k_fixup(board.caldata[i].slot, board.caldata[i].caldata_offset,\n-\t\t\tboard.caldata[i].endian_check);\n+\t\t\tboard.caldata[i].endian_check, board.caldata[i].led_pin, board.caldata[i].led_active_high);\n \n \treturn 0;\n }\n--- a/arch/mips/bcm63xx/pci-ath9k-fixup.c\n+++ b/arch/mips/bcm63xx/pci-ath9k-fixup.c\n@@ -184,13 +184,15 @@ static void ath9k_pci_fixup(struct pci_d\n DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATHEROS, PCI_ANY_ID, ath9k_pci_fixup);\n \n void __init pci_enable_ath9k_fixup(unsigned slot, u32 offset,\n-\tunsigned endian_check)\n+\tunsigned endian_check, int led_pin, bool led_active_high)\n {\n \tif (ath9k_num_fixups >= ARRAY_SIZE(ath9k_fixups))\n \t\treturn;\n \n \tath9k_fixups[ath9k_num_fixups].slot = slot;\n \tath9k_fixups[ath9k_num_fixups].pdata.endian_check = endian_check;\n+\tath9k_fixups[ath9k_num_fixups].pdata.led_pin = led_pin;\n+\tath9k_fixups[ath9k_num_fixups].pdata.led_active_high = led_active_high;\n \n \tif (!bcm63xx_read_eeprom(ath9k_fixups[ath9k_num_fixups].pdata.eeprom_data, offset))\n \t\treturn;\n--- a/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h\n+++ b/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h\n@@ -21,6 +21,8 @@ struct ath9k_caldata {\n \tunsigned int\tslot;\n \tu32\t\tcaldata_offset;\n \tunsigned int\tendian_check:1;\n+\tint\t\tled_pin;\n+\tbool\t\tled_active_high;\n };\n \n /*\n--- a/arch/mips/include/asm/mach-bcm63xx/pci_ath9k_fixup.h\n+++ b/arch/mips/include/asm/mach-bcm63xx/pci_ath9k_fixup.h\n@@ -3,6 +3,6 @@\n \n \n void pci_enable_ath9k_fixup(unsigned slot, u32 offset,\n-\tunsigned endian_check) __init;\n+\tunsigned endian_check, int led_pin, bool led_active_high) __init;\n \n #endif /* _PCI_ATH9K_FIXUP */\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/422-BCM63XX-add-a-fixup-for-rt2x00-devices.patch",
    "content": "From 5ed5b5e9614fa5b02da699ab565af76c7e63d64d Mon Sep 17 00:00:00 2001\nFrom: Jonas Gorski <jogo@openwrt.org>\nDate: Mon, 7 Jan 2013 17:45:39 +0100\nSubject: [PATCH 72/72] 446-BCM63XX-add-a-fixup-for-rt2x00-devices\n\n---\n arch/mips/bcm63xx/Makefile                         |    2 +-\n arch/mips/bcm63xx/boards/board_bcm963xx.c          |   17 ++++-\n arch/mips/bcm63xx/dev-flash.c                      |    2 +-\n arch/mips/bcm63xx/pci-rt2x00-fixup.c               |   71 ++++++++++++++++++++\n .../include/asm/mach-bcm63xx/bcm63xx_dev_flash.h   |    2 +-\n .../mips/include/asm/mach-bcm63xx/board_bcm963xx.h |    9 ++-\n .../include/asm/mach-bcm63xx/pci_rt2x00_fixup.h    |    9 +++\n 7 files changed, 104 insertions(+), 8 deletions(-)\n create mode 100644 arch/mips/bcm63xx/pci-rt2x00-fixup.c\n create mode 100644 arch/mips/include/asm/mach-bcm63xx/pci_rt2x00_fixup.h\n\n--- a/arch/mips/bcm63xx/Makefile\n+++ b/arch/mips/bcm63xx/Makefile\n@@ -3,7 +3,7 @@ obj-y\t\t+= clk.o cpu.o cs.o gpio.o irq.o\n \t\t   setup.o timer.o dev-enet.o dev-flash.o dev-pcmcia.o \\\n \t\t   dev-rng.o dev-wdt.o \\\n \t\t   dev-usb-ehci.o dev-usb-ohci.o dev-usb-usbd.o usb-common.o \\\n-\t\t   pci-ath9k-fixup.o sprom.o\n+\t\t   pci-ath9k-fixup.o pci-rt2x00-fixup.o sprom.o\n obj-$(CONFIG_EARLY_PRINTK)\t+= early_printk.o\n \n obj-y\t\t+= boards/\n--- a/arch/mips/bcm63xx/boards/board_common.c\n+++ b/arch/mips/bcm63xx/boards/board_common.c\n@@ -32,6 +32,7 @@\n #include <bcm63xx_dev_usb_usbd.h>\n #include <board_bcm963xx.h>\n #include <pci_ath9k_fixup.h>\n+#include <pci_rt2x00_fixup.h>\n \n #include \"board_common.h\"\n \n@@ -244,9 +245,19 @@ int __init board_register_devices(void)\n \t}\n \n \t/* register any fixups */\n-\tfor (i = 0; i < board.has_caldata; i++)\n-\t\tpci_enable_ath9k_fixup(board.caldata[i].slot, board.caldata[i].caldata_offset,\n-\t\t\tboard.caldata[i].endian_check, board.caldata[i].led_pin, board.caldata[i].led_active_high);\n+\tfor (i = 0; i < board.has_caldata; i++) {\n+\t\tswitch (board.caldata[i].vendor) {\n+\t\tcase PCI_VENDOR_ID_ATHEROS:\n+\t\t\tpci_enable_ath9k_fixup(board.caldata[i].slot,\n+\t\t\t\tboard.caldata[i].caldata_offset, board.caldata[i].endian_check,\n+\t\t\t\tboard.caldata[i].led_pin, board.caldata[i].led_active_high);\n+\t\t\tbreak;\n+\t\tcase PCI_VENDOR_ID_RALINK:\n+\t\t\tpci_enable_rt2x00_fixup(board.caldata[i].slot,\n+\t\t\t\tboard.caldata[i].eeprom);\n+\t\t\tbreak;\n+\t\t}\n+\t}\n \n \treturn 0;\n }\n--- /dev/null\n+++ b/arch/mips/bcm63xx/pci-rt2x00-fixup.c\n@@ -0,0 +1,72 @@\n+/*\n+ *  Broadcom BCM63XX RT2x00 EEPROM fixup helper.\n+ *\n+ *  Copyright (C) 2012 Álvaro Fernández Rojas <noltari@gmail.com>\n+ *\n+ *  Based on\n+ *\n+ *  Broadcom BCM63XX Ath9k EEPROM fixup helper.\n+ *\n+ *  Copyright (C) 2012 Jonas Gorski <jonas.gorski@gmail.com>\n+ *\n+ *  This program is free software; you can redistribute it and/or modify it\n+ *  under the terms of the GNU General Public License version 2 as published\n+ *  by the Free Software Foundation.\n+ */\n+\n+#include <linux/if_ether.h>\n+#include <linux/pci.h>\n+#include <linux/platform_device.h>\n+#include <linux/rt2x00_platform.h>\n+\n+#include <bcm63xx_nvram.h>\n+#include <pci_rt2x00_fixup.h>\n+\n+struct rt2x00_fixup {\n+\tunsigned slot;\n+\tu8 mac[ETH_ALEN];\n+\tstruct rt2x00_platform_data pdata;\n+};\n+\n+static int rt2x00_num_fixups;\n+static struct rt2x00_fixup rt2x00_fixups[2] = {\n+\t{\n+\t\t.slot = 255,\n+\t},\n+\t{\n+\t\t.slot = 255,\n+\t},\n+};\n+\n+static void rt2x00_pci_fixup(struct pci_dev *dev)\n+{\n+\tunsigned i;\n+\tstruct rt2x00_platform_data *pdata = NULL;\n+\n+\tfor (i = 0; i < rt2x00_num_fixups; i++) {\n+\t\tif (rt2x00_fixups[i].slot != PCI_SLOT(dev->devfn))\n+\t\t\tcontinue;\n+\n+\t\tpdata = &rt2x00_fixups[i].pdata;\n+\t\tbreak;\n+\t}\n+\n+\tdev->dev.platform_data = pdata;\n+}\n+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_RALINK, PCI_ANY_ID, rt2x00_pci_fixup);\n+\n+void __init pci_enable_rt2x00_fixup(unsigned slot, char* eeprom)\n+{\n+\tif (rt2x00_num_fixups >= ARRAY_SIZE(rt2x00_fixups))\n+\t\treturn;\n+\n+\trt2x00_fixups[rt2x00_num_fixups].slot = slot;\n+\trt2x00_fixups[rt2x00_num_fixups].pdata.eeprom_file_name = kstrdup(eeprom, GFP_KERNEL);\n+\n+\tif (bcm63xx_nvram_get_mac_address(rt2x00_fixups[rt2x00_num_fixups].mac))\n+\t\treturn;\n+\n+\trt2x00_fixups[rt2x00_num_fixups].pdata.mac_address = rt2x00_fixups[rt2x00_num_fixups].mac;\n+\trt2x00_num_fixups++;\n+}\n+\n--- a/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h\n+++ b/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h\n@@ -10,6 +10,7 @@\n #include <bcm63xx_dev_usb_usbd.h>\n #include <bcm63xx_fallback_sprom.h>\n #include <pci_ath9k_fixup.h>\n+#include <pci_rt2x00_fixup.h>\n \n /*\n  * flash mapping\n@@ -17,12 +18,16 @@\n #define BCM963XX_CFE_VERSION_OFFSET\t0x570\n #define BCM963XX_NVRAM_OFFSET\t\t0x580\n \n-struct ath9k_caldata {\n+struct bcm63xx_caldata {\n+\tunsigned int\tvendor;\n \tunsigned int\tslot;\n \tu32\t\tcaldata_offset;\n+\t/* Atheros */\n \tunsigned int\tendian_check:1;\n \tint\t\tled_pin;\n \tbool\t\tled_active_high;\n+\t/* Ralink */\n+\tchar*\t\teeprom;\n };\n \n /*\n@@ -45,7 +50,7 @@ struct board_info {\n \tunsigned int\thas_caldata:2;\n \n \t/* wifi calibration data config */\n-\tstruct ath9k_caldata caldata[2];\n+\tstruct bcm63xx_caldata caldata[2];\n \n \t/* ethernet config */\n \tstruct bcm63xx_enet_platform_data enet0;\n--- /dev/null\n+++ b/arch/mips/include/asm/mach-bcm63xx/pci_rt2x00_fixup.h\n@@ -0,0 +1,9 @@\n+#ifndef _PCI_RT2X00_FIXUP\n+#define _PCI_RT2X00_FIXUP\n+\n+#define PCI_VENDOR_ID_RALINK 0x1814\n+\n+void pci_enable_rt2x00_fixup(unsigned slot, char* eeprom) __init;\n+\n+#endif /* _PCI_RT2X00_FIXUP */\n+\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/423-bcm63xx_enet_add_b53_support.patch",
    "content": "--- a/drivers/net/ethernet/broadcom/bcm63xx_enet.h\n+++ b/drivers/net/ethernet/broadcom/bcm63xx_enet.h\n@@ -338,6 +338,9 @@ struct bcm_enet_priv {\n \tstruct bcm63xx_enetsw_port used_ports[ENETSW_MAX_PORT];\n \tint sw_port_link[ENETSW_MAX_PORT];\n \n+\t/* platform device for associated switch */\n+\tstruct platform_device *b53_device;\n+\n \t/* used to poll switch port state */\n \tstruct timer_list swphy_poll;\n \tspinlock_t enetsw_mdio_lock;\n--- a/drivers/net/ethernet/broadcom/bcm63xx_enet.c\n+++ b/drivers/net/ethernet/broadcom/bcm63xx_enet.c\n@@ -17,6 +17,7 @@\n #include <linux/dma-mapping.h>\n #include <linux/platform_device.h>\n #include <linux/if_vlan.h>\n+#include <linux/platform_data/b53.h>\n \n #include <bcm63xx_dev_enet.h>\n #include \"bcm63xx_enet.h\"\n@@ -1927,7 +1928,8 @@ static int bcm_enet_remove(struct platfo\n \treturn 0;\n }\n \n-struct platform_driver bcm63xx_enet_driver = {\n+\n+static struct platform_driver bcm63xx_enet_driver = {\n \t.probe\t= bcm_enet_probe,\n \t.remove\t= bcm_enet_remove,\n \t.driver\t= {\n@@ -1936,6 +1938,42 @@ struct platform_driver bcm63xx_enet_driv\n \t},\n };\n \n+struct b53_platform_data bcm63xx_b53_pdata = {\n+\t.chip_id = 0x6300,\n+\t.big_endian = 1,\n+};\n+\n+struct platform_device bcm63xx_b53_dev = {\n+\t.name\t\t= \"b53-switch\",\n+\t.id\t\t= -1,\n+\t.dev\t\t= {\n+\t\t.platform_data = &bcm63xx_b53_pdata,\n+\t},\n+};\n+\n+static int bcmenet_switch_register(struct bcm_enet_priv *priv, u16 port_mask)\n+{\n+\tint ret;\n+\n+\tbcm63xx_b53_pdata.regs = priv->base;\n+\tbcm63xx_b53_pdata.enabled_ports = port_mask;\n+\tbcm63xx_b53_pdata.alias = priv->net_dev->name;\n+\n+\tret = platform_device_register(&bcm63xx_b53_dev);\n+\tif (!ret)\n+\t\tpriv->b53_device = &bcm63xx_b53_dev;\n+\n+\treturn ret;\n+}\n+\n+static void bcmenet_switch_unregister(struct bcm_enet_priv *priv)\n+{\n+\tif (priv->b53_device)\n+\t\tplatform_device_unregister(&bcm63xx_b53_dev);\n+\n+\tpriv->b53_device = NULL;\n+}\n+\n /*\n  * switch mii access callbacks\n  */\n@@ -2192,29 +2230,6 @@ static int bcm_enetsw_open(struct net_de\n \t\tenetsw_writeb(priv, rgmii_ctrl, ENETSW_RGMII_CTRL_REG(i));\n \t}\n \n-\t/* reset mib */\n-\tval = enetsw_readb(priv, ENETSW_GMCR_REG);\n-\tval |= ENETSW_GMCR_RST_MIB_MASK;\n-\tenetsw_writeb(priv, val, ENETSW_GMCR_REG);\n-\tmdelay(1);\n-\tval &= ~ENETSW_GMCR_RST_MIB_MASK;\n-\tenetsw_writeb(priv, val, ENETSW_GMCR_REG);\n-\tmdelay(1);\n-\n-\t/* force CPU port state */\n-\tval = enetsw_readb(priv, ENETSW_IMPOV_REG);\n-\tval |= ENETSW_IMPOV_FORCE_MASK | ENETSW_IMPOV_LINKUP_MASK;\n-\tenetsw_writeb(priv, val, ENETSW_IMPOV_REG);\n-\n-\t/* enable switch forward engine */\n-\tval = enetsw_readb(priv, ENETSW_SWMODE_REG);\n-\tval |= ENETSW_SWMODE_FWD_EN_MASK;\n-\tenetsw_writeb(priv, val, ENETSW_SWMODE_REG);\n-\n-\t/* enable jumbo on all ports */\n-\tenetsw_writel(priv, 0x1ff, ENETSW_JMBCTL_PORT_REG);\n-\tenetsw_writew(priv, 9728, ENETSW_JMBCTL_MAXSIZE_REG);\n-\n \t/* initialize flow control buffer allocation */\n \tenet_dma_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0,\n \t\t\tENETDMA_BUFALLOC_REG(priv->rx_chan));\n@@ -2648,6 +2663,9 @@ static int bcm_enetsw_probe(struct platf\n \tstruct bcm63xx_enetsw_platform_data *pd;\n \tstruct resource *res_mem;\n \tint ret, irq_rx, irq_tx;\n+\tunsigned i, num_ports = 0;\n+\tu16 port_mask = BIT(8);\n+\tu8 val;\n \n \tif (!bcm_enet_shared_base[0])\n \t\treturn -EPROBE_DEFER;\n@@ -2728,6 +2746,43 @@ static int bcm_enetsw_probe(struct platf\n \tpriv->pdev = pdev;\n \tpriv->net_dev = dev;\n \n+\t/* reset mib */\n+\tval = enetsw_readb(priv, ENETSW_GMCR_REG);\n+\tval |= ENETSW_GMCR_RST_MIB_MASK;\n+\tenetsw_writeb(priv, val, ENETSW_GMCR_REG);\n+\tmdelay(1);\n+\tval &= ~ENETSW_GMCR_RST_MIB_MASK;\n+\tenetsw_writeb(priv, val, ENETSW_GMCR_REG);\n+\tmdelay(1);\n+\n+\t/* force CPU port state */\n+\tval = enetsw_readb(priv, ENETSW_IMPOV_REG);\n+\tval |= ENETSW_IMPOV_FORCE_MASK | ENETSW_IMPOV_LINKUP_MASK;\n+\tenetsw_writeb(priv, val, ENETSW_IMPOV_REG);\n+\n+\t/* enable switch forward engine */\n+\tval = enetsw_readb(priv, ENETSW_SWMODE_REG);\n+\tval |= ENETSW_SWMODE_FWD_EN_MASK;\n+\tenetsw_writeb(priv, val, ENETSW_SWMODE_REG);\n+\n+\t/* enable jumbo on all ports */\n+\tenetsw_writel(priv, 0x1ff, ENETSW_JMBCTL_PORT_REG);\n+\tenetsw_writew(priv, 9728, ENETSW_JMBCTL_MAXSIZE_REG);\n+\n+\tfor (i = 0; i < priv->num_ports; i++) {\n+\t\tstruct bcm63xx_enetsw_port *port = &priv->used_ports[i];\n+\n+\t\tif (!port->used)\n+\t\t\tcontinue;\n+\n+\t\tnum_ports++;\n+\t\tport_mask |= BIT(i);\n+\t}\n+\n+\t/* only register if there is more than one external port */\n+\tif (num_ports > 1)\n+\t\tbcmenet_switch_register(priv, port_mask);\n+\n \treturn 0;\n \n out_disable_clk:\n@@ -2749,6 +2804,9 @@ static int bcm_enetsw_remove(struct plat\n \tpriv = netdev_priv(dev);\n \tunregister_netdev(dev);\n \n+\t/* remove switch */\n+\tbcmenet_switch_unregister(priv);\n+\n \tclk_disable_unprepare(priv->mac_clk);\n \n \tfree_netdev(dev);\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/424-bcm63xx_enet_no_request_mem_region.patch",
    "content": "--- a/drivers/net/ethernet/broadcom/bcm63xx_enet.c\n+++ b/drivers/net/ethernet/broadcom/bcm63xx_enet.c\n@@ -2707,9 +2707,9 @@ static int bcm_enetsw_probe(struct platf\n \tif (ret)\n \t\tgoto out;\n \n-\tpriv->base = devm_ioremap_resource(&pdev->dev, res_mem);\n-\tif (IS_ERR(priv->base)) {\n-\t\tret = PTR_ERR(priv->base);\n+ \tpriv->base = devm_ioremap(&pdev->dev, res_mem->start, resource_size(res_mem));\n+ \tif (priv->base == NULL) {\n+\t\tret = -ENOMEM;\n \t\tgoto out;\n \t}\n \n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/427-boards_probe_switch.patch",
    "content": "--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c\n+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c\n@@ -74,6 +74,8 @@ static struct board_info __initdata boar\n \n \t.has_enet0 = 1,\n \t.enet0 = {\n+\t\t.has_phy = 1,\n+\t\t.phy_id = 0,\n \t\t.force_speed_100 = 1,\n \t\t.force_duplex_full = 1,\n \t},\n@@ -85,6 +87,8 @@ static struct board_info __initdata boar\n \n \t.has_enet0 = 1,\n \t.enet0 = {\n+\t\t.has_phy = 1,\n+\t\t.phy_id = 0,\n \t\t.force_speed_100 = 1,\n \t\t.force_duplex_full = 1,\n \t},\n@@ -136,6 +140,8 @@ static struct board_info __initdata boar\n \n \t.has_enet1 = 1,\n \t.enet1 = {\n+\t\t.has_phy = 1,\n+\t\t.phy_id = 0,\n \t\t.force_speed_100 = 1,\n \t\t.force_duplex_full = 1,\n \t},\n@@ -158,6 +164,8 @@ static struct board_info __initdata boar\n \n \t.has_enet1 = 1,\n \t.enet1 = {\n+\t\t.has_phy = 1,\n+\t\t.phy_id = 0,\n \t\t.force_speed_100 = 1,\n \t\t.force_duplex_full = 1,\n \t},\n@@ -179,6 +187,8 @@ static struct board_info __initdata boar\n \n \t.has_enet1 = 1,\n \t.enet1 = {\n+\t\t.has_phy = 1,\n+\t\t.phy_id = 0,\n \t\t.force_speed_100 = 1,\n \t\t.force_duplex_full = 1,\n \t},\n@@ -201,6 +211,8 @@ static struct board_info __initdata boar\n \n \t.has_enet1 = 1,\n \t.enet1 = {\n+\t\t.has_phy = 1,\n+\t\t.phy_id = 0,\n \t\t.force_speed_100 = 1,\n \t\t.force_duplex_full = 1,\n \t},\n@@ -221,6 +233,8 @@ static struct board_info __initdata boar\n \n \t.has_enet1 = 1,\n \t.enet1 = {\n+\t\t.has_phy = 1,\n+\t\t.phy_id = 0,\n \t\t.force_speed_100 = 1,\n \t\t.force_duplex_full = 1,\n \t},\n@@ -242,6 +256,8 @@ static struct board_info __initdata boar\n \n \t.has_enet1 = 1,\n \t.enet1 = {\n+\t\t.has_phy = 1,\n+\t\t.phy_id = 0,\n \t\t.force_speed_100 = 1,\n \t\t.force_duplex_full = 1,\n \t},\n@@ -263,6 +279,8 @@ static struct board_info __initdata boar\n \n \t.has_enet1 = 1,\n \t.enet1 = {\n+\t\t.has_phy = 1,\n+\t\t.phy_id = 0,\n \t\t.force_speed_100 = 1,\n \t\t.force_duplex_full = 1,\n \t},\n@@ -291,6 +309,8 @@ static struct board_info __initdata boar\n \n \t.has_enet1 = 1,\n \t.enet1 = {\n+\t\t.has_phy = 1,\n+\t\t.phy_id = 0,\n \t\t.force_speed_100 = 1,\n \t\t.force_duplex_full = 1,\n \t},\n@@ -315,6 +335,8 @@ static struct board_info __initdata boar\n \n \t.has_enet1 = 1,\n \t.enet1 = {\n+\t\t.has_phy = 1,\n+\t\t.phy_id = 0,\n \t\t.force_speed_100 = 1,\n \t\t.force_duplex_full = 1,\n \t},\n@@ -336,6 +358,8 @@ static struct board_info __initdata boar\n \n \t.has_enet1 = 1,\n \t.enet1 = {\n+\t\t.has_phy = 1,\n+\t\t.phy_id = 0,\n \t\t.force_speed_100 = 1,\n \t\t.force_duplex_full = 1,\n \t},\n@@ -358,6 +382,8 @@ static struct board_info __initdata boar\n \n \t.has_enet1 = 1,\n \t.enet1 = {\n+\t\t.has_phy = 1,\n+\t\t.phy_id = 0,\n \t\t.force_speed_100 = 1,\n \t\t.force_duplex_full = 1,\n \t},\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/428-bcm63xx_enet-rgmii-ctrl-fix.patch",
    "content": "--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h\n+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h\n@@ -79,6 +79,9 @@ struct bcm63xx_enetsw_port {\n \tint\t\tforce_speed;\n \tint\t\tforce_duplex_full;\n \n+\tint\t\tmii_override;\n+\tint\t\ttiming_sel;\n+\n \tconst char\t*name;\n };\n \n--- a/drivers/net/ethernet/broadcom/bcm63xx_enet.c\n+++ b/drivers/net/ethernet/broadcom/bcm63xx_enet.c\n@@ -2227,6 +2227,10 @@ static int bcm_enetsw_open(struct net_de\n \n \t\trgmii_ctrl = enetsw_readb(priv, ENETSW_RGMII_CTRL_REG(i));\n \t\trgmii_ctrl |= ENETSW_RGMII_CTRL_GMII_CLK_EN;\n+\t\tif (priv->used_ports[i].mii_override)\n+\t\t\trgmii_ctrl |= ENETSW_RGMII_CTRL_MII_OVERRIDE_EN;\n+\t\tif (priv->used_ports[i].timing_sel)\n+\t\t\trgmii_ctrl |= ENETSW_RGMII_CTRL_TIMING_SEL_EN;\n \t\tenetsw_writeb(priv, rgmii_ctrl, ENETSW_RGMII_CTRL_REG(i));\n \t}\n \n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/430-MIPS-BCM63XX-add-nand-clocks.patch",
    "content": "--- a/arch/mips/bcm63xx/clk.c\n+++ b/arch/mips/bcm63xx/clk.c\n@@ -430,6 +430,23 @@ static struct clk clk_pcie = {\n };\n \n /*\n+ * NAND clock\n+ */\n+static void nand_set(struct clk *clk, int enable)\n+{\n+\tif (BCMCPU_IS_6362())\n+\t\tbcm_hwclock_set(CKCTL_6362_NAND_EN, enable);\n+\telse if (BCMCPU_IS_6368())\n+\t\tbcm_hwclock_set(CKCTL_6368_NAND_EN, enable);\n+\telse if (BCMCPU_IS_63268())\n+\t\tbcm_hwclock_set(CKCTL_63268_NAND_EN, enable);\n+}\n+\n+static struct clk clk_nand = {\n+\t.set\t= nand_set,\n+};\n+\n+/*\n  * Internal peripheral clock\n  */\n static struct clk clk_periph = {\n@@ -624,6 +641,7 @@ static struct clk_lookup bcm6362_clks[]\n \tCLKDEV_INIT(\"bcm63xx-hsspi.0\", \"pll\", &clk_hsspi_pll),\n \tCLKDEV_INIT(\"10001000.spi\", \"pll\", &clk_hsspi_pll),\n \t/* gated clocks */\n+\tCLKDEV_INIT(NULL, \"nand\", &clk_nand),\n \tCLKDEV_INIT(NULL, \"enetsw\", &clk_enetsw),\n \tCLKDEV_INIT(NULL, \"usbh\", &clk_usbh),\n \tCLKDEV_INIT(NULL, \"usbd\", &clk_usbd),\n@@ -641,6 +659,7 @@ static struct clk_lookup bcm6368_clks[]\n \tCLKDEV_INIT(\"10000100.serial\", \"refclk\", &clk_periph),\n \tCLKDEV_INIT(\"10000120.serial\", \"refclk\", &clk_periph),\n \t/* gated clocks */\n+\tCLKDEV_INIT(NULL, \"nand\", &clk_nand),\n \tCLKDEV_INIT(NULL, \"enetsw\", &clk_enetsw),\n \tCLKDEV_INIT(NULL, \"usbh\", &clk_usbh),\n \tCLKDEV_INIT(NULL, \"usbd\", &clk_usbd),\n@@ -659,6 +678,7 @@ static struct clk_lookup bcm63268_clks[]\n \tCLKDEV_INIT(\"bcm63xx-hsspi.0\", \"pll\", &clk_hsspi_pll),\n \tCLKDEV_INIT(\"10001000.spi\", \"pll\", &clk_hsspi_pll),\n \t/* gated clocks */\n+\tCLKDEV_INIT(NULL, \"nand\", &clk_nand),\n \tCLKDEV_INIT(NULL, \"enetsw\", &clk_enetsw),\n \tCLKDEV_INIT(NULL, \"usbh\", &clk_usbh),\n \tCLKDEV_INIT(NULL, \"usbd\", &clk_usbd),\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/431-MIPS-BCM63XX-add-nand-rset.patch",
    "content": "--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h\n+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h\n@@ -184,7 +184,8 @@ enum bcm63xx_regs_set {\n \tRSET_PCMDMAC,\n \tRSET_PCMDMAS,\n \tRSET_RNG,\n-\tRSET_MISC\n+\tRSET_MISC,\n+\tRSET_NAND\n };\n \n #define RSET_DSL_LMEM_SIZE\t\t(64 * 1024 * 4)\n@@ -262,6 +263,7 @@ enum bcm63xx_regs_set {\n #define BCM_3368_PCMDMAS_BASE\t\t(0xdeadbeef)\n #define BCM_3368_RNG_BASE\t\t(0xdeadbeef)\n #define BCM_3368_MISC_BASE\t\t(0xdeadbeef)\n+#define BCM_3368_NAND_BASE\t\t(0xdeadbeef)\n \n /*\n  * 6318 register sets base address\n@@ -309,6 +311,7 @@ enum bcm63xx_regs_set {\n #define BCM_6318_PCMDMAS_BASE\t\t(0xdeadbeef)\n #define BCM_6318_RNG_BASE\t\t(0xdeadbeef)\n #define BCM_6318_MISC_BASE\t\t(0xb0000280)\n+#define BCM_6318_NAND_BASE\t\t(0xdeadbeef)\n #define BCM_6318_OTP_BASE\t\t(0xdeadbeef)\n \n #define BCM_6318_STRAP_BASE\t\t(0xb0000900)\n@@ -359,6 +362,7 @@ enum bcm63xx_regs_set {\n #define BCM_6328_PCMDMAS_BASE\t\t(0xdeadbeef)\n #define BCM_6328_RNG_BASE\t\t(0xdeadbeef)\n #define BCM_6328_MISC_BASE\t\t(0xb0001800)\n+#define BCM_6328_NAND_BASE\t\t(0xb0000200)\n #define BCM_6328_OTP_BASE\t\t(0xb0000600)\n \n /*\n@@ -408,6 +412,7 @@ enum bcm63xx_regs_set {\n #define BCM_6338_PCMDMAS_BASE\t\t(0xdeadbeef)\n #define BCM_6338_RNG_BASE\t\t(0xdeadbeef)\n #define BCM_6338_MISC_BASE\t\t(0xdeadbeef)\n+#define BCM_6338_NAND_BASE\t\t(0xdeadbeef)\n \n /*\n  * 6345 register sets base address\n@@ -456,6 +461,7 @@ enum bcm63xx_regs_set {\n #define BCM_6345_PCMDMAS_BASE\t\t(0xdeadbeef)\n #define BCM_6345_RNG_BASE\t\t(0xdeadbeef)\n #define BCM_6345_MISC_BASE\t\t(0xdeadbeef)\n+#define BCM_6345_NAND_BASE\t\t(0xdeadbeef)\n \n /*\n  * 6348 register sets base address\n@@ -502,6 +508,7 @@ enum bcm63xx_regs_set {\n #define BCM_6348_PCMDMAS_BASE\t\t(0xdeadbeef)\n #define BCM_6348_RNG_BASE\t\t(0xdeadbeef)\n #define BCM_6348_MISC_BASE\t\t(0xdeadbeef)\n+#define BCM_6348_NAND_BASE\t\t(0xdeadbeef)\n \n /*\n  * 6358 register sets base address\n@@ -548,7 +555,7 @@ enum bcm63xx_regs_set {\n #define BCM_6358_PCMDMAS_BASE\t\t(0xfffe1a00)\n #define BCM_6358_RNG_BASE\t\t(0xdeadbeef)\n #define BCM_6358_MISC_BASE\t\t(0xdeadbeef)\n-\n+#define BCM_6358_NAND_BASE\t\t(0xdeadbeef)\n \n /*\n  * 6362 register sets base address\n@@ -596,6 +603,7 @@ enum bcm63xx_regs_set {\n #define BCM_6362_PCMDMAS_BASE\t\t(0xdeadbeef)\n #define BCM_6362_RNG_BASE\t\t(0xdeadbeef)\n #define BCM_6362_MISC_BASE\t\t(0xb0001800)\n+#define BCM_6362_NAND_BASE\t\t(0xb0000200)\n \n #define BCM_6362_NAND_REG_BASE\t\t(0xb0000200)\n #define BCM_6362_NAND_CACHE_BASE\t(0xb0000600)\n@@ -651,6 +659,7 @@ enum bcm63xx_regs_set {\n #define BCM_6368_PCMDMAS_BASE\t\t(0xb0005c00)\n #define BCM_6368_RNG_BASE\t\t(0xb0004180)\n #define BCM_6368_MISC_BASE\t\t(0xdeadbeef)\n+#define BCM_6368_NAND_BASE\t\t(0xb0000200)\n \n /*\n  * 63268 register sets base address\n@@ -698,6 +707,7 @@ enum bcm63xx_regs_set {\n #define BCM_63268_PCMDMAS_BASE\t\t(0xdeadbeef)\n #define BCM_63268_RNG_BASE\t\t(0xdeadbeef)\n #define BCM_63268_MISC_BASE\t\t(0xb0001800)\n+#define BCM_63268_NAND_BASE\t\t(0xb0000200)\n \n extern const unsigned long *bcm63xx_regs_base;\n \n@@ -743,6 +753,7 @@ extern const unsigned long *bcm63xx_regs\n \t[RSET_PCMDMAS]\t\t= BCM_## __cpu ##_PCMDMAS_BASE,\t\t\\\n \t[RSET_RNG]\t\t= BCM_## __cpu ##_RNG_BASE,\t\t\\\n \t[RSET_MISC]\t\t= BCM_## __cpu ##_MISC_BASE,\t\t\\\n+\t[RSET_NAND]\t\t= BCM_## __cpu ##_NAND_BASE,\t\t\\\n \n \n static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)\n--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h\n+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h\n@@ -111,5 +111,7 @@\n #define bcm_ddr_writel(v, o)\tbcm_rset_writel(RSET_DDR, (v), (o))\n #define bcm_misc_readl(o)\tbcm_rset_readl(RSET_MISC, (o))\n #define bcm_misc_writel(v, o)\tbcm_rset_writel(RSET_MISC, (v), (o))\n+#define bcm_nand_readl(o)\tbcm_rset_readl(RSET_NAND, (o))\n+#define bcm_nand_writel(v, o)\tbcm_rset_writel(RSET_NAND, (v), (o))\n \n #endif /* ! BCM63XX_IO_H_ */\n--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h\n+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h\n@@ -1688,4 +1688,31 @@\n #define OTP_USER_BITS_6328_REG(i)\t(0x20 + (i) * 4)\n #define   OTP_6328_REG3_TP1_DISABLED\tBIT(9)\n \n+/*************************************************************************\n+ * _REG relative to RSET_NAND\n+ *************************************************************************/\n+\n+#define NAND_CS_SEL_REG\t\t0x14\n+#define NAND_CS_SEL_EBC_CS0_SEL\t(1 << 0)\n+#define NAND_CS_SEL_EBC_CS1_SEL\t(1 << 1)\n+#define NAND_CS_SEL_EBC_CS2_SEL\t(1 << 2)\n+#define NAND_CS_SEL_EBC_CS3_SEL\t(1 << 3)\n+#define NAND_CS_SEL_EBC_CS4_SEL\t(1 << 4)\n+#define NAND_CS_SEL_EBC_CS5_SEL\t(1 << 5)\n+#define NAND_CS_SEL_EBC_CS6_SEL\t(1 << 6)\n+#define NAND_CS_SEL_EBC_CS7_SEL\t(1 << 7)\n+#define NAND_CS_SEL_EBI_CS0_USES_NAND\t(1 << 8)\n+#define NAND_CS_SEL_EBI_CS1_USES_NAND\t(1 << 9)\n+#define NAND_CS_SEL_EBI_CS2_USES_NAND\t(1 << 10)\n+#define NAND_CS_SEL_EBI_CS3_USES_NAND\t(1 << 11)\n+#define NAND_CS_SEL_EBI_CS4_USES_NAND\t(1 << 12)\n+#define NAND_CS_SEL_EBI_CS5_USES_NAND\t(1 << 13)\n+#define NAND_CS_SEL_EBI_CS6_USES_NAND\t(1 << 14)\n+#define NAND_CS_SEL_EBI_CS7_USES_NAND\t(1 << 15)\n+#define NAND_CS_SEL_WR_PROT_BLK0\t(1 << 28)\n+#define NAND_CS_SEL_AUTO_DEV_ID\t(1 << 30)\n+#define NAND_CS_SEL_CS_LOCK\t\t(1 << 31)\n+\n+#define NAND_CS_XOR_REG\t\t\t0x18\n+\n #endif /* BCM63XX_REGS_H_ */\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/432-MIPS-BCM63XX-detect-nand-nvram.patch",
    "content": "--- a/arch/mips/bcm63xx/dev-flash.c\n+++ b/arch/mips/bcm63xx/dev-flash.c\n@@ -229,6 +229,14 @@ void __init bcm63xx_flash_detect(void)\n \t\t}\n \n \t\tbcm_rset_writel(RSET_HSSPI, val, HSSPI_FLASH_CTRL_REG);\n+\t} else if (flash_type == BCM63XX_FLASH_TYPE_NAND &&\n+\t\t   (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_6368() ||\n+\t\t    BCMCPU_IS_63268())) {\n+\t\tbcm_nand_writel(NAND_CS_SEL_AUTO_DEV_ID\n+\t\t\t\t| NAND_CS_SEL_EBI_CS0_USES_NAND\n+\t\t\t\t| NAND_CS_SEL_EBC_CS0_SEL,\n+\t\t\t\tNAND_CS_SEL_REG);\n+\t\tbcm_nand_writel(1, NAND_CS_XOR_REG);\n \t}\n }\n \n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/433-MIPS-BCM63XX-enable-nand-support.patch",
    "content": "--- a/arch/mips/bcm63xx/dev-flash.c\n+++ b/arch/mips/bcm63xx/dev-flash.c\n@@ -271,8 +271,12 @@ int __init bcm63xx_flash_register(void)\n \t\t\treturn -ENODEV;\n \t\t}\n \tcase BCM63XX_FLASH_TYPE_NAND:\n-\t\tpr_warn(\"unsupported NAND flash detected\\n\");\n-\t\treturn -ENODEV;\n+\t\tif (board_of_device_present(\"nflash\")) {\n+\t\t\treturn 0;\n+\t\t} else {\n+\t\t\tpr_warn(\"unsupported NAND flash detected\\n\");\n+\t\t\treturn -ENODEV;\n+\t\t}\n \tdefault:\n \t\tpr_err(\"flash detection failed for BCM%x: %d\\n\",\n \t\t       bcm63xx_get_cpu_id(), flash_type);\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/500-MIPS-BCM63XX-populate-the-compatible-to-board_info-l.patch",
    "content": "From e71eea9953c774dfadb754258824fb1888c279f4 Mon Sep 17 00:00:00 2001\nFrom: Jonas Gorski <jogo@openwrt.org>\nDate: Fri, 21 Nov 2014 16:54:06 +0100\nSubject: [PATCH 47/48] MIPS: BCM63XX: populate the compatible to board_info\n list\n\nPopulate the compatible to board_info list to allow dtbs to be used\nfor known boards.\n\nSigned-off-by: Jonas Gorski <jogo@openwrt.org>\n---\n arch/mips/bcm63xx/boards/board_bcm963xx.c |   34 +++++++++++++++++++++++++++++\n 1 file changed, 34 insertions(+)\n\n--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c\n+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c\n@@ -426,6 +426,52 @@ static const struct board_info __initcon\n };\n \n static struct of_device_id const bcm963xx_boards_dt[] = {\n+#ifdef CONFIG_OF\n+#ifdef CONFIG_BCM63XX_CPU_3368\n+\t{ .compatible = \"netgear,cvg834g\", .data = &board_cvg834g, },\n+#endif /* CONFIG_BCM63XX_CPU_3368 */\n+#ifdef CONFIG_BCM63XX_CPU_6318\n+#endif /* CONFIG_BCM63XX_CPU_6318 */\n+#ifdef CONFIG_BCM63XX_CPU_6328\n+\t{ .compatible = \"brcm,bcm96328avng\", .data = &board_96328avng, },\n+#endif /* CONFIG_BCM63XX_CPU_6328 */\n+#ifdef CONFIG_BCM63XX_CPU_6338\n+\t{ .compatible = \"brcm,bcm96338gw\", .data = &board_96338gw, },\n+\t{ .compatible = \"brcm,bcm96338w\", .data = &board_96338w, },\n+#endif /* CONFIG_BCM63XX_CPU_6338 */\n+#ifdef CONFIG_BCM63XX_CPU_6345\n+\t{ .compatible = \"brcm,bcm96345gw2\", .data = &board_96345gw2, },\n+#endif /* CONFIG_BCM63XX_CPU_6345 */\n+#ifdef CONFIG_BCM63XX_CPU_6348\n+\t{ .compatible = \"belkin,f5d7633\", .data = &board_96348gw_10, },\n+\t{ .compatible = \"brcm,bcm96348r\", .data = &board_96348r, },\n+\t{ .compatible = \"brcm,bcm96348gw-10\", .data = &board_96348gw_10, },\n+\t{ .compatible = \"brcm,bcm96348gw-11\", .data = &board_96348gw_11, },\n+\t{ .compatible = \"brcm,bcm96348gw-a\", .data = &board_96348gw_a, },\n+\t{ .compatible = \"davolink,dv-201amr\", .data = &board_DV201AMR, },\n+\t{ .compatible = \"dynalink,rta1025w\", .data = &board_rta1025w_16, },\n+\t{ .compatible = \"netgear,dg834gt-pn\", .data = &board_96348gw_10, },\n+\t{ .compatible = \"sagem,fast-2404\", .data = &board_FAST2404, },\n+\t{ .compatible = \"tp-link,td-w8900gb\", .data = &board_96348gw_11, },\n+\t{ .compatible = \"usrobotics,usr9108\", .data = &board_96348gw_a, },\n+#endif /* CONFIG_BCM63XX_CPU_6348 */\n+#ifdef CONFIG_BCM63XX_CPU_6358\n+\t{ .compatible = \"alcatel,rg100a\", .data = &board_96358vw2, },\n+\t{ .compatible = \"brcm,bcm96358vw\", .data = &board_96358vw, },\n+\t{ .compatible = \"brcm,bcm96358vw2\", .data = &board_96358vw2, },\n+\t{ .compatible = \"d-link,dsl-2650u\", .data = &board_96358vw2, },\n+\t{ .compatible = \"pirelli,a226g\", .data = &board_DWVS0, },\n+\t{ .compatible = \"pirelli,a226m\", .data = &board_DWVS0, },\n+\t{ .compatible = \"pirelli,a226m-fwb\", .data = &board_DWVS0, },\n+\t{ .compatible = \"pirelli,agpf-s0\", .data = &board_AGPFS0, },\n+#endif /* CONFIG_BCM63XX_CPU_6358 */\n+#ifdef CONFIG_BCM63XX_CPU_6362\n+#endif /* CONFIG_BCM63XX_CPU_6362 */\n+#ifdef CONFIG_BCM63XX_CPU_6368\n+#endif /* CONFIG_BCM63XX_CPU_6368 */\n+#ifdef CONFIG_BCM63XX_CPU_63268\n+#endif /* CONFIG_BCM63XX_CPU_63268 */\n+#endif /* CONFIG_OF */\n \t{ },\n };\n \n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/501-board_bcm6328-extend-96328avng-reference-board.patch",
    "content": "--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c\n+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c\n@@ -59,6 +59,32 @@ static struct board_info __initdata boar\n \t\t.use_fullspeed = 0,\n \t\t.port_no = 0,\n \t},\n+\n+\t.has_enetsw = 1,\n+\t.enetsw = {\n+\t\t.used_ports = {\n+\t\t\t[0] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 1,\n+\t\t\t\t.name = \"Port 1\",\n+\t\t\t},\n+\t\t\t[1] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 2,\n+\t\t\t\t.name = \"Port 2\",\n+\t\t\t},\n+\t\t\t[2] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 3,\n+\t\t\t\t.name = \"Port 3\",\n+\t\t\t},\n+\t\t\t[3] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 4,\n+\t\t\t\t.name = \"Port 4\",\n+\t\t\t},\n+\t\t},\n+\t},\n };\n #endif /* CONFIG_BCM63XX_CPU_6328 */\n \n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/511-board_bcm6318.patch",
    "content": "--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c\n+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c\n@@ -44,6 +44,263 @@ static struct board_info __initdata boar\n #endif /* CONFIG_BCM63XX_CPU_3368 */\n \n /*\n+ * known 6318 boards\n+ */\n+#ifdef CONFIG_BCM63XX_CPU_6318\n+static struct board_info __initdata board_96318ref = {\n+\t.name = \"96318REF\",\n+\t.expected_cpu_id = 0x6318,\n+\n+\t.has_pci = 1,\n+\t.has_ohci0 = 1,\n+\t.has_ehci0 = 1,\n+\t.num_usbh_ports = 1,\n+\n+\t.has_usbd = 1,\n+\t.usbd = {\n+\t\t.use_fullspeed = 0,\n+\t\t.port_no = 0,\n+\t},\n+\n+\t.has_enetsw = 1,\n+\t.enetsw = {\n+\t\t.used_ports = {\n+\t\t\t[0] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 1,\n+\t\t\t\t.name = \"Port 1\",\n+\t\t\t},\n+\t\t\t[1] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 2,\n+\t\t\t\t.name = \"Port 2\",\n+\t\t\t},\n+\t\t\t[2] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 3,\n+\t\t\t\t.name = \"Port 3\",\n+\t\t\t},\n+\t\t\t[3] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 4,\n+\t\t\t\t.name = \"Port 4\",\n+\t\t\t},\n+\t\t},\n+\t},\n+};\n+\n+static struct board_info __initdata board_96318ref_p300 = {\n+\t.name = \"96318REF_P300\",\n+\t.expected_cpu_id = 0x6318,\n+\n+\t.has_pci = 1,\n+\t.has_ohci0 = 1,\n+\t.has_ehci0 = 1,\n+\t.num_usbh_ports = 1,\n+\n+\t.has_usbd = 1,\n+\t.usbd = {\n+\t\t.use_fullspeed = 0,\n+\t\t.port_no = 0,\n+\t},\n+\n+\t.has_enetsw = 1,\n+\t.enetsw = {\n+\t\t.used_ports = {\n+\t\t\t[0] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 1,\n+\t\t\t\t.name = \"Port 1\",\n+\t\t\t},\n+\t\t\t[1] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 2,\n+\t\t\t\t.name = \"Port 2\",\n+\t\t\t},\n+\t\t\t[2] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 3,\n+\t\t\t\t.name = \"Port 3\",\n+\t\t\t},\n+\t\t\t[3] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 4,\n+\t\t\t\t.name = \"Port 4\",\n+\t\t\t},\n+\t\t},\n+\t},\n+};\n+\n+static struct sprom_fixup __initdata ar5315u_fixups[] = {\n+\t{ .offset = 6, .value = 0x1c00 },\n+\t{ .offset = 65, .value = 0x1255 },\n+\t{ .offset = 97, .value = 0xfe55 },\n+\t{ .offset = 98, .value = 0x171d },\n+\t{ .offset = 99, .value = 0xfa42 },\n+\t{ .offset = 113, .value = 0xfeb7 },\n+\t{ .offset = 114, .value = 0x18cd },\n+\t{ .offset = 115, .value = 0xfa4f },\n+\t{ .offset = 162, .value = 0x6444 },\n+\t{ .offset = 170, .value = 0x6444 },\n+\t{ .offset = 172, .value = 0x6444 },\n+};\n+\n+static struct board_info __initdata board_AR5315u = {\n+\t.name = \"96318A-1441N1\",\n+\t.expected_cpu_id = 0x6318,\n+\n+\t.has_pci = 1,\n+\t.has_ohci0 = 1,\n+\t.has_ehci0 = 1,\n+\t.num_usbh_ports = 1,\n+\n+\t.has_enetsw = 1,\n+\t.enetsw = {\n+\t\t.used_ports = {\n+\t\t\t[0] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 1,\n+\t\t\t\t.name = \"LAN4\",\n+\t\t\t},\n+\t\t\t[1] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 2,\n+\t\t\t\t.name = \"LAN3\",\n+\t\t\t},\n+\t\t\t[2] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 3,\n+\t\t\t\t.name = \"LAN2\",\n+\t\t\t},\n+\t\t\t[3] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 4,\n+\t\t\t\t.name = \"LAN1\",\n+\t\t\t},\n+\t\t},\n+\t},\n+\n+\t.use_fallback_sprom = 1,\n+\t.fallback_sprom = {\n+\t\t.type = SPROM_BCM43217,\n+\t\t.pci_bus = 1,\n+\t\t.pci_dev = 0,\n+\t\t.board_fixups = ar5315u_fixups,\n+\t\t.num_board_fixups = ARRAY_SIZE(ar5315u_fixups),\n+\t},\n+};\n+\n+static struct sprom_fixup __initdata dsl2751b_e1_fixups[] = {\n+\t{ .offset = 96, .value = 0x2046 },\n+\t{ .offset = 97, .value = 0xfe9d },\n+\t{ .offset = 98, .value = 0x1854 },\n+\t{ .offset = 99, .value = 0xfa59 },\n+\t{ .offset = 112, .value = 0x2046 },\n+\t{ .offset = 113, .value = 0xfe79 },\n+\t{ .offset = 114, .value = 0x17f5 },\n+\t{ .offset = 115, .value = 0xfa47 },\n+\t{ .offset = 161, .value = 0x2222 },\n+\t{ .offset = 162, .value = 0x2222 },\n+\t{ .offset = 169, .value = 0x2222 },\n+\t{ .offset = 170, .value = 0x2222 },\n+\t{ .offset = 171, .value = 0x5555 },\n+\t{ .offset = 172, .value = 0x5555 },\n+\t{ .offset = 173, .value = 0x4444 },\n+\t{ .offset = 174, .value = 0x4444 },\n+\t{ .offset = 175, .value = 0x5555 },\n+\t{ .offset = 176, .value = 0x5555 },\n+};\n+\n+static struct board_info __initdata board_dsl_2751b_d1 = {\n+\t.name = \"AW5200B\",\n+\t.expected_cpu_id = 0x6318,\n+\n+\t.has_pci = 1,\n+\t.has_ohci0 = 1,\n+\t.has_ehci0 = 1,\n+\t.num_usbh_ports = 1,\n+\n+\t.has_enetsw = 1,\n+\t.enetsw = {\n+\t\t.used_ports = {\n+\t\t\t[0] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 1,\n+\t\t\t\t.name = \"Port 1\",\n+\t\t\t},\n+\t\t\t[1] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 2,\n+\t\t\t\t.name = \"Port 2\",\n+\t\t\t},\n+\t\t\t[2] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 3,\n+\t\t\t\t.name = \"Port 3\",\n+\t\t\t},\n+\t\t\t[3] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 4,\n+\t\t\t\t.name = \"Port 4\",\n+\t\t\t},\n+\t\t},\n+\t},\n+\n+\t.use_fallback_sprom = 1,\n+\t.fallback_sprom = {\n+\t\t.type = SPROM_BCM43217,\n+\t\t.pci_bus = 1,\n+\t\t.pci_dev = 0,\n+\t\t.board_fixups = dsl2751b_e1_fixups,\n+\t\t.num_board_fixups = ARRAY_SIZE(dsl2751b_e1_fixups),\n+\t},\n+};\n+\n+static struct board_info __initdata board_FAST2704N = {\n+\t.name = \"F@ST2704N\",\n+\t.expected_cpu_id = 0x6318,\n+\n+\t.has_pci = 1,\n+\t.has_ohci0 = 1,\n+\t.has_ehci0 = 1,\n+\t.num_usbh_ports = 1,\n+\n+\t.has_enetsw = 1,\n+\t.enetsw = {\n+\t\t.used_ports = {\n+\t\t\t[0] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 1,\n+\t\t\t\t.name = \"Port 1\",\n+\t\t\t},\n+\t\t\t[1] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 2,\n+\t\t\t\t.name = \"Port 2\",\n+\t\t\t},\n+\t\t\t[2] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 3,\n+\t\t\t\t.name = \"Port 3\",\n+\t\t\t},\n+\t\t\t[3] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 4,\n+\t\t\t\t.name = \"Port 4\",\n+\t\t\t},\n+\t\t},\n+\t},\n+\n+\t.use_fallback_sprom = 1,\n+\t.fallback_sprom = {\n+\t\t.type = SPROM_BCM43217,\n+\t\t.pci_bus = 1,\n+\t\t.pci_dev = 0,\n+\t},\n+};\n+#endif /* CONFIG_BCM63XX_CPU_6318 */\n+\n+/*\n  * known 6328 boards\n  */\n #ifdef CONFIG_BCM63XX_CPU_6328\n@@ -423,6 +680,13 @@ static const struct board_info __initcon\n #ifdef CONFIG_BCM63XX_CPU_3368\n \t&board_cvg834g,\n #endif /* CONFIG_BCM63XX_CPU_3368 */\n+#ifdef CONFIG_BCM63XX_CPU_6318\n+\t&board_96318ref,\n+\t&board_96318ref_p300,\n+\t&board_AR5315u,\n+\t&board_dsl_2751b_d1,\n+\t&board_FAST2704N,\n+#endif /* CONFIG_BCM63XX_CPU_6318 */\n #ifdef CONFIG_BCM63XX_CPU_6328\n \t&board_96328avng,\n #endif /* CONFIG_BCM63XX_CPU_6328 */\n@@ -457,6 +721,11 @@ static struct of_device_id const bcm963x\n \t{ .compatible = \"netgear,cvg834g\", .data = &board_cvg834g, },\n #endif /* CONFIG_BCM63XX_CPU_3368 */\n #ifdef CONFIG_BCM63XX_CPU_6318\n+\t{ .compatible = \"brcm,bcm96318ref\", .data = &board_96318ref, },\n+\t{ .compatible = \"brcm,bcm96318ref-p300\", .data = &board_96318ref_p300, },\n+\t{ .compatible = \"comtrend,ar-5315u\", .data = &board_AR5315u, },\n+\t{ .compatible = \"d-link,dsl-275xb-d1\", .data = &board_dsl_2751b_d1, },\n+\t{ .compatible = \"sagem,fast-2704n\", .data = &board_FAST2704N, },\n #endif /* CONFIG_BCM63XX_CPU_6318 */\n #ifdef CONFIG_BCM63XX_CPU_6328\n \t{ .compatible = \"brcm,bcm96328avng\", .data = &board_96328avng, },\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/512-board_bcm6328.patch",
    "content": "--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c\n+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c\n@@ -343,6 +343,651 @@ static struct board_info __initdata boar\n \t\t},\n \t},\n };\n+\n+static struct board_info __initdata board_963281TAN = {\n+\t.name = \"963281TAN\",\n+\t.expected_cpu_id = 0x6328,\n+\n+\t.has_pci = 1,\n+\n+\t.has_enetsw = 1,\n+\t.enetsw = {\n+\t\t.used_ports = {\n+\t\t\t[0] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 1,\n+\t\t\t\t.name = \"Port 1\",\n+\t\t\t},\n+\t\t\t[1] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 2,\n+\t\t\t\t.name = \"Port 2\",\n+\t\t\t},\n+\t\t\t[2] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 3,\n+\t\t\t\t.name = \"Port 3\",\n+\t\t\t},\n+\t\t\t[3] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 4,\n+\t\t\t\t.name = \"Port 4\",\n+\t\t\t},\n+\t\t},\n+\t},\n+};\n+\n+static struct board_info __initdata board_A4001N = {\n+\t.name = \"96328dg2x2\",\n+\t.expected_cpu_id = 0x6328,\n+\n+\t.has_pci = 1,\n+\t.has_ohci0 = 1,\n+\t.has_ehci0 = 1,\n+\t.num_usbh_ports = 1,\n+\n+\t.has_enetsw = 1,\n+\t.enetsw = {\n+\t\t.used_ports = {\n+\t\t\t[0] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 1,\n+\t\t\t\t.name = \"Port 1\",\n+\t\t\t},\n+\t\t\t[1] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 2,\n+\t\t\t\t.name = \"Port 2\",\n+\t\t\t},\n+\t\t\t[2] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 3,\n+\t\t\t\t.name = \"Port 3\",\n+\t\t\t},\n+\t\t\t[3] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 4,\n+\t\t\t\t.name = \"Port 4\",\n+\t\t\t},\n+\t\t},\n+\t},\n+\n+\t.use_fallback_sprom = 1,\n+\t.fallback_sprom = {\n+\t\t.type = SPROM_BCM43225,\n+\t\t.pci_bus = 1,\n+\t\t.pci_dev = 0,\n+\t},\n+};\n+\n+static struct board_info __initdata board_A4001N1 = {\n+\t.name = \"963281T_TEF\",\n+\t.expected_cpu_id = 0x6328,\n+\n+\t.has_pci = 1,\n+\t.has_ohci0 = 1,\n+\t.has_ehci0 = 1,\n+\t.num_usbh_ports = 1,\n+\n+\t.has_enetsw = 1,\n+\t.enetsw = {\n+\t\t.used_ports = {\n+\t\t\t[0] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 1,\n+\t\t\t\t.name = \"Port 1\",\n+\t\t\t},\n+\t\t\t[1] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 2,\n+\t\t\t\t.name = \"Port 2\",\n+\t\t\t},\n+\t\t\t[2] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 3,\n+\t\t\t\t.name = \"Port 3\",\n+\t\t\t},\n+\t\t\t[3] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 4,\n+\t\t\t\t.name = \"Port 4\",\n+\t\t\t},\n+\t\t},\n+\t},\n+\n+\t.use_fallback_sprom = 1,\n+\t.fallback_sprom = {\n+\t\t.type = SPROM_BCM43225,\n+\t\t.pci_bus = 1,\n+\t\t.pci_dev = 0,\n+\t},\n+};\n+\n+static struct sprom_fixup __initdata ad1018_fixups[] = {\n+\t{ .offset = 6, .value = 0x1c00 },\n+\t{ .offset = 65, .value = 0x1256 },\n+\t{ .offset = 96, .value = 0x2046 },\n+\t{ .offset = 97, .value = 0xfe69 },\n+\t{ .offset = 98, .value = 0x1726 },\n+\t{ .offset = 99, .value = 0xfa5c },\n+\t{ .offset = 112, .value = 0x2046 },\n+\t{ .offset = 113, .value = 0xfea8 },\n+\t{ .offset = 114, .value = 0x1978 },\n+\t{ .offset = 115, .value = 0xfa26 },\n+\t{ .offset = 161, .value = 0x2222 },\n+\t{ .offset = 169, .value = 0x2222 },\n+\t{ .offset = 171, .value = 0x2222 },\n+\t{ .offset = 173, .value = 0x2222 },\n+\t{ .offset = 174, .value = 0x4444 },\n+\t{ .offset = 175, .value = 0x2222 },\n+\t{ .offset = 176, .value = 0x4444 },\n+};\n+\n+static struct board_info __initdata board_AD1018 = {\n+\t.name = \"96328avngr\",\n+\t.expected_cpu_id = 0x6328,\n+\n+\t.has_pci = 1,\n+\t.has_ohci0 = 1,\n+\t.has_ehci0 = 1,\n+\t.num_usbh_ports = 1,\n+\n+\t.has_enetsw = 1,\n+\t.enetsw = {\n+\t\t.used_ports = {\n+\t\t\t[0] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 1,\n+\t\t\t\t.name = \"FIBRE\",\n+\t\t\t},\n+\t\t\t[1] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 2,\n+\t\t\t\t.name = \"LAN3\",\n+\t\t\t},\n+\t\t\t[2] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 3,\n+\t\t\t\t.name = \"LAN2\",\n+\t\t\t},\n+\t\t\t[3] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 4,\n+\t\t\t\t.name = \"LAN1\",\n+\t\t\t},\n+\t\t},\n+\t},\n+\n+\t.use_fallback_sprom = 1,\n+\t.fallback_sprom = {\n+\t\t.type = SPROM_BCM43217,\n+\t\t.pci_bus = 1,\n+\t\t.pci_dev = 0,\n+\t\t.board_fixups = ad1018_fixups,\n+\t\t.num_board_fixups = ARRAY_SIZE(ad1018_fixups),\n+\t},\n+};\n+\n+static struct sprom_fixup __initdata ar5381u_fixups[] = {\n+\t{ .offset = 97, .value = 0xfee5 },\n+\t{ .offset = 98, .value = 0x157c },\n+\t{ .offset = 99, .value = 0xfae7 },\n+\t{ .offset = 113, .value = 0xfefa },\n+\t{ .offset = 114, .value = 0x15d6 },\n+\t{ .offset = 115, .value = 0xfaf8 },\n+};\n+\n+static struct board_info __initdata board_AR5381u = {\n+\t.name = \"96328A-1241N\",\n+\t.expected_cpu_id = 0x6328,\n+\n+\t.has_pci = 1,\n+\t.has_ohci0 = 1,\n+\t.has_ehci0 = 1,\n+\t.num_usbh_ports = 1,\n+\n+\t.has_enetsw = 1,\n+\t.enetsw = {\n+\t\t.used_ports = {\n+\t\t\t[0] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 1,\n+\t\t\t\t.name = \"Port 1\",\n+\t\t\t},\n+\t\t\t[1] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 2,\n+\t\t\t\t.name = \"Port 2\",\n+\t\t\t},\n+\t\t\t[2] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 3,\n+\t\t\t\t.name = \"Port 3\",\n+\t\t\t},\n+\t\t\t[3] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 4,\n+\t\t\t\t.name = \"Port 4\",\n+\t\t\t},\n+\t\t},\n+\t},\n+\n+\t.use_fallback_sprom = 1,\n+\t.fallback_sprom = {\n+\t\t.type = SPROM_BCM43225,\n+\t\t.pci_bus = 1,\n+\t\t.pci_dev = 0,\n+\t\t.board_fixups = ar5381u_fixups,\n+\t\t.num_board_fixups = ARRAY_SIZE(ar5381u_fixups),\n+\t},\n+};\n+\n+static struct sprom_fixup __initdata ar5387un_fixups[] = {\n+\t{ .offset = 2, .value = 0x05bb },\n+\t{ .offset = 65, .value = 0x1204 },\n+\t{ .offset = 78, .value = 0x0303 },\n+\t{ .offset = 79, .value = 0x0202 },\n+\t{ .offset = 80, .value = 0xff02 },\n+\t{ .offset = 87, .value = 0x0315 },\n+\t{ .offset = 88, .value = 0x0315 },\n+\t{ .offset = 96, .value = 0x2048 },\n+\t{ .offset = 97, .value = 0xff11 },\n+\t{ .offset = 98, .value = 0x1567 },\n+\t{ .offset = 99, .value = 0xfb24 },\n+\t{ .offset = 100, .value = 0x3e3c },\n+\t{ .offset = 101, .value = 0x4038 },\n+\t{ .offset = 102, .value = 0xfe7f },\n+\t{ .offset = 103, .value = 0x1279 },\n+\t{ .offset = 112, .value = 0x2048 },\n+\t{ .offset = 113, .value = 0xff03 },\n+\t{ .offset = 114, .value = 0x154c },\n+\t{ .offset = 115, .value = 0xfb27 },\n+\t{ .offset = 116, .value = 0x3e3c },\n+\t{ .offset = 117, .value = 0x4038 },\n+\t{ .offset = 118, .value = 0xfe87 },\n+\t{ .offset = 119, .value = 0x1233 },\n+\t{ .offset = 203, .value = 0x2226 },\n+};\n+\n+static struct board_info __initdata board_AR5387un = {\n+\t.name = \"96328A-1441N1\",\n+\t.expected_cpu_id = 0x6328,\n+\n+\t.has_pci = 1,\n+\t.has_ohci0 = 1,\n+\t.has_ehci0 = 1,\n+\t.num_usbh_ports = 1,\n+\n+\t.has_enetsw = 1,\n+\t.enetsw = {\n+\t\t.used_ports = {\n+\t\t\t[0] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 1,\n+\t\t\t\t.name = \"Port 1\",\n+\t\t\t},\n+\t\t\t[1] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 2,\n+\t\t\t\t.name = \"Port 2\",\n+\t\t\t},\n+\t\t\t[2] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 3,\n+\t\t\t\t.name = \"Port 3\",\n+\t\t\t},\n+\t\t\t[3] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 4,\n+\t\t\t\t.name = \"Port 4\",\n+\t\t\t},\n+\t\t},\n+\t},\n+\n+\t.use_fallback_sprom = 1,\n+\t.fallback_sprom = {\n+\t\t.type = SPROM_BCM43225,\n+\t\t.pci_bus = 1,\n+\t\t.pci_dev = 0,\n+\t\t.board_fixups = ar5387un_fixups,\n+\t\t.num_board_fixups = ARRAY_SIZE(ar5387un_fixups),\n+\t},\n+};\n+\n+static struct board_info __initdata board_dsl_274xb_f1 = {\n+\t.name = \"AW4339U\",\n+\t.expected_cpu_id = 0x6328,\n+\n+\t.has_pci = 1,\n+\n+\t.has_caldata = 1,\n+\t.caldata = {\n+\t\t{\n+\t\t\t.vendor = PCI_VENDOR_ID_ATHEROS,\n+\t\t\t.caldata_offset = 0x7d1000,\n+\t\t\t.slot = 0,\n+\t\t\t.led_pin = -1,\n+\t\t\t.led_active_high = 1,\n+\t\t},\n+\t},\n+\n+\t.has_enetsw = 1,\n+\t.enetsw = {\n+\t\t.used_ports = {\n+\t\t\t[0] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 1,\n+\t\t\t\t.name = \"Port 4\",\n+\t\t\t},\n+\t\t\t[1] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 2,\n+\t\t\t\t.name = \"Port 3\",\n+\t\t\t},\n+\t\t\t[2] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 3,\n+\t\t\t\t.name = \"Port 2\",\n+\t\t\t},\n+\t\t\t[3] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 4,\n+\t\t\t\t.name = \"Port 1\",\n+\t\t\t},\n+\t\t},\n+\t},\n+};\n+\n+static struct board_info __initdata board_FAST2704V2 = {\n+\t.name = \"F@ST2704V2\",\n+\t.expected_cpu_id = 0x6328,\n+\n+\t.has_pci = 1,\n+\t.has_ohci0 = 1,\n+\t.has_ehci0 = 1,\n+\t.has_usbd = 1,\n+\n+\t.has_enetsw = 1,\n+\t.enetsw = {\n+\t\t.used_ports = {\n+\t\t\t[0] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 1,\n+\t\t\t\t.name = \"Port 1\",\n+\t\t\t},\n+\t\t\t[1] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 2,\n+\t\t\t\t.name = \"Port 2\",\n+\t\t\t},\n+\t\t\t[2] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 3,\n+\t\t\t\t.name = \"Port 3\",\n+\t\t\t},\n+\t\t\t[3] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 4,\n+\t\t\t\t.name = \"Port 4\",\n+\t\t\t},\n+\t\t},\n+\t},\n+};\n+\n+static struct board_info __initdata board_PDG_A4001N_A_000_1A1_AX = {\n+\t.name = \"96328avng\",\n+\t.expected_cpu_id = 0x6328,\n+\n+\t.has_pci = 1,\n+\t.has_ohci0 = 1,\n+\t.has_ehci0 = 1,\n+\t.num_usbh_ports = 1,\n+\n+\t.has_enetsw = 1,\n+\t.enetsw = {\n+\t\t.used_ports = {\n+\t\t\t[0] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 1,\n+\t\t\t\t.name = \"Port 1\",\n+\t\t\t},\n+\t\t\t[1] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 2,\n+\t\t\t\t.name = \"Port 2\",\n+\t\t\t},\n+\t\t\t[2] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 3,\n+\t\t\t\t.name = \"Port 3\",\n+\t\t\t},\n+\t\t\t[3] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 4,\n+\t\t\t\t.name = \"Port 4\",\n+\t\t\t},\n+\t\t},\n+\t},\n+\n+\t.use_fallback_sprom = 1,\n+\t.fallback_sprom = {\n+\t\t.type = SPROM_BCM43225,\n+\t\t.pci_bus = 1,\n+\t\t.pci_dev = 0,\n+\t},\n+};\n+\n+static struct board_info __initdata board_PDG_A4101N_A_000_1A1_AE = {\n+\t.name = \"96328avngv\",\n+\t.expected_cpu_id = 0x6328,\n+\n+\t.has_pci = 1,\n+\t.has_ohci0 = 1,\n+\t.has_ehci0 = 1,\n+\t.num_usbh_ports = 1,\n+\n+\t.has_enetsw = 1,\n+\t.enetsw = {\n+\t\t.used_ports = {\n+\t\t\t[0] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 1,\n+\t\t\t\t.name = \"Port 1\",\n+\t\t\t},\n+\t\t\t[1] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 2,\n+\t\t\t\t.name = \"Port 2\",\n+\t\t\t},\n+\t\t\t[2] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 3,\n+\t\t\t\t.name = \"Port 3\",\n+\t\t\t},\n+\t\t\t[3] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 4,\n+\t\t\t\t.name = \"Port 4\",\n+\t\t\t},\n+\t\t},\n+\t},\n+\n+\t.use_fallback_sprom = 1,\n+\t.fallback_sprom = {\n+\t\t.type = SPROM_BCM43225,\n+\t\t.pci_bus = 1,\n+\t\t.pci_dev = 0,\n+\t},\n+};\n+\n+static struct board_info __initdata board_R5010UNV2 = {\n+\t.name = \"96328ang\",\n+\t.expected_cpu_id = 0x6328,\n+\n+\t.has_pci = 1,\n+\t.has_ohci0 = 1,\n+\t.has_ehci0 = 1,\n+\t.num_usbh_ports = 1,\n+\n+\t.has_enetsw = 1,\n+\t.enetsw = {\n+\t\t.used_ports = {\n+\t\t\t[0] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 1,\n+\t\t\t\t.name = \"Port 1\",\n+\t\t\t},\n+\t\t\t[1] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 2,\n+\t\t\t\t.name = \"Port 2\",\n+\t\t\t},\n+\t\t\t[2] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 3,\n+\t\t\t\t.name = \"Port 3\",\n+\t\t\t},\n+\t\t\t[3] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 4,\n+\t\t\t\t.name = \"Port 4\",\n+\t\t\t},\n+\t\t},\n+\t},\n+\n+\t.use_fallback_sprom = 1,\n+\t.fallback_sprom = {\n+\t\t.type = SPROM_BCM43217,\n+\t\t.pci_bus = 1,\n+\t\t.pci_dev = 0,\n+\t},\n+};\n+\n+static struct board_info __initdata board_TG582N = {\n+\t.name = \"DANT-1\",\n+\t.expected_cpu_id = 0x6328,\n+\n+\t.has_pci = 1,\n+\t.has_ohci0 = 1,\n+\t.has_ehci0 = 1,\n+\t.num_usbh_ports = 1,\n+\n+\t.has_enetsw = 1,\n+\t.enetsw = {\n+\t\t.used_ports = {\n+\t\t\t[0] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 1,\n+\t\t\t\t.name = \"Port 1\",\n+\t\t\t},\n+\t\t\t[1] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 2,\n+\t\t\t\t.name = \"Port 2\",\n+\t\t\t},\n+\t\t\t[2] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 3,\n+\t\t\t\t.name = \"Port 3\",\n+\t\t\t},\n+\t\t\t[3] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 4,\n+\t\t\t\t.name = \"Port 4\",\n+\t\t\t},\n+\t\t},\n+\t},\n+\n+\t.use_fallback_sprom = 1,\n+\t.fallback_sprom = {\n+\t\t.type = SPROM_BCM43225,\n+\t\t.pci_bus = 1,\n+\t\t.pci_dev = 0,\n+\t},\n+};\n+\n+static struct board_info __initdata board_TG582N_TELECOM_ITALIA = {\n+\t.name = \"DANT-V\",\n+\t.expected_cpu_id = 0x6328,\n+\n+\t.has_pci = 1,\n+\t.has_ohci0 = 1,\n+\t.has_ehci0 = 1,\n+\t.num_usbh_ports = 1,\n+\n+\t.has_enetsw = 1,\n+\t.enetsw = {\n+\t\t.used_ports = {\n+\t\t\t[0] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 1,\n+\t\t\t\t.name = \"Port 1\",\n+\t\t\t},\n+\t\t\t[1] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 2,\n+\t\t\t\t.name = \"Port 2\",\n+\t\t\t},\n+\t\t\t[2] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 3,\n+\t\t\t\t.name = \"Port 3\",\n+\t\t\t},\n+\t\t\t[3] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 4,\n+\t\t\t\t.name = \"Port 4\",\n+\t\t\t},\n+\t\t},\n+\t},\n+\n+\t.use_fallback_sprom = 1,\n+\t.fallback_sprom = {\n+\t\t.type = SPROM_BCM43225,\n+\t\t.pci_bus = 1,\n+\t\t.pci_dev = 0,\n+\t},\n+};\n+\n+static struct board_info __initdata board_W3400V6 = {\n+\t.name = \"96328ang\",\n+\t.expected_cpu_id = 0x6328,\n+\n+\t.has_pci = 1,\n+\n+\t.has_enetsw = 1,\n+\t.enetsw = {\n+\t\t.used_ports = {\n+\t\t\t[0] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 1,\n+\t\t\t\t.name = \"Port 1\",\n+\t\t\t},\n+\t\t\t[1] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 2,\n+\t\t\t\t.name = \"Port 2\",\n+\t\t\t},\n+\t\t\t[2] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 3,\n+\t\t\t\t.name = \"Port 3\",\n+\t\t\t},\n+\t\t\t[3] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 4,\n+\t\t\t\t.name = \"Port 4\",\n+\t\t\t},\n+\t\t},\n+\t},\n+\n+\t.use_fallback_sprom = 1,\n+\t.fallback_sprom = {\n+\t\t.type = SPROM_BCM4318,\n+\t\t.pci_bus = 1,\n+\t\t.pci_dev = 0,\n+\t},\n+};\n #endif /* CONFIG_BCM63XX_CPU_6328 */\n \n /*\n@@ -689,6 +1334,20 @@ static const struct board_info __initcon\n #endif /* CONFIG_BCM63XX_CPU_6318 */\n #ifdef CONFIG_BCM63XX_CPU_6328\n \t&board_96328avng,\n+\t&board_963281TAN,\n+\t&board_A4001N,\n+\t&board_A4001N1,\n+\t&board_AD1018,\n+\t&board_AR5381u,\n+\t&board_AR5387un,\n+\t&board_dsl_274xb_f1,\n+\t&board_FAST2704V2,\n+\t&board_PDG_A4001N_A_000_1A1_AX,\n+\t&board_PDG_A4101N_A_000_1A1_AE,\n+\t&board_TG582N,\n+\t&board_TG582N_TELECOM_ITALIA,\n+\t&board_R5010UNV2,\n+\t&board_W3400V6,\n #endif /* CONFIG_BCM63XX_CPU_6328 */\n #ifdef CONFIG_BCM63XX_CPU_6338\n \t&board_96338gw,\n@@ -728,7 +1387,23 @@ static struct of_device_id const bcm963x\n \t{ .compatible = \"sagem,fast-2704n\", .data = &board_FAST2704N, },\n #endif /* CONFIG_BCM63XX_CPU_6318 */\n #ifdef CONFIG_BCM63XX_CPU_6328\n+\t{ .compatible = \"adb,a4001n\", .data = &board_A4001N, },\n+\t{ .compatible = \"adb,a4001n1\", .data = &board_A4001N1, },\n+\t{ .compatible = \"adb,pdg-a4001n-a-000-1a1-ax\", .data = &board_PDG_A4001N_A_000_1A1_AX, },\n+\t{ .compatible = \"adb,pdg-a4101n-a-000-1a1-ae\", .data = &board_PDG_A4101N_A_000_1A1_AE, },\n \t{ .compatible = \"brcm,bcm96328avng\", .data = &board_96328avng, },\n+\t{ .compatible = \"brcm,bcm963281tan\", .data = &board_963281TAN, },\n+\t{ .compatible = \"comtrend,ar-5381u\", .data = &board_AR5381u, },\n+\t{ .compatible = \"comtrend,ar-5387un\", .data = &board_AR5387un, },\n+\t{ .compatible = \"d-link,dsl-274xb-f1\", .data = &board_dsl_274xb_f1, },\n+\t{ .compatible = \"d-link,dsl-2750u-c1\", .data = &board_A4001N, },\n+\t{ .compatible = \"innacomm,w3400v6\", .data = &board_W3400V6, },\n+\t{ .compatible = \"nucom,r5010un-v2\", .data = &board_R5010UNV2, },\n+\t{ .compatible = \"sagem,fast-2704-v2\", .data = &board_FAST2704V2, },\n+\t{ .compatible = \"sercomm,ad1018\", .data = &board_AD1018, },\n+\t{ .compatible = \"sercomm,ad1018-nor\", .data = &board_AD1018, },\n+\t{ .compatible = \"technicolor,tg582n\", .data = &board_TG582N, },\n+\t{ .compatible = \"technicolor,tg582n-telecom-italia\", .data = &board_TG582N_TELECOM_ITALIA, },\n #endif /* CONFIG_BCM63XX_CPU_6328 */\n #ifdef CONFIG_BCM63XX_CPU_6338\n \t{ .compatible = \"brcm,bcm96338gw\", .data = &board_96338gw, },\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/513-board-bcm6338.patch",
    "content": "--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c\n+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c\n@@ -1021,6 +1021,32 @@ static struct board_info __initdata boar\n \t\t.force_duplex_full = 1,\n \t},\n };\n+\n+static struct board_info __initdata board_96338w2_e7t = {\n+\t.name = \"96338W2_E7T\",\n+\t.expected_cpu_id = 0x6338,\n+\n+\t.has_enet0 = 1,\n+\t.enet0 = {\n+\t\t.has_phy = 1,\n+\t\t.phy_id = 0,\n+\t\t.force_speed_100 = 1,\n+\t\t.force_duplex_full = 1,\n+\t},\n+};\n+\n+static struct board_info __initdata board_rta1320_16m = {\n+\t.name = \"RTA1320_16M\",\n+\t.expected_cpu_id = 0x6338,\n+\n+\t.has_enet0 = 1,\n+\t.enet0 = {\n+\t\t.has_phy = 1,\n+\t\t.phy_id = 0,\n+\t\t.force_speed_100 = 1,\n+\t\t.force_duplex_full = 1,\n+\t},\n+};\n #endif /* CONFIG_BCM63XX_CPU_6338 */\n \n /*\n@@ -1352,6 +1378,8 @@ static const struct board_info __initcon\n #ifdef CONFIG_BCM63XX_CPU_6338\n \t&board_96338gw,\n \t&board_96338w,\n+\t&board_96338w2_e7t,\n+\t&board_rta1320_16m,\n #endif /* CONFIG_BCM63XX_CPU_6338 */\n #ifdef CONFIG_BCM63XX_CPU_6345\n \t&board_96345gw2,\n@@ -1408,6 +1436,8 @@ static struct of_device_id const bcm963x\n #ifdef CONFIG_BCM63XX_CPU_6338\n \t{ .compatible = \"brcm,bcm96338gw\", .data = &board_96338gw, },\n \t{ .compatible = \"brcm,bcm96338w\", .data = &board_96338w, },\n+\t{ .compatible = \"d-link,dsl-2640u\", .data = &board_96338w2_e7t, },\n+\t{ .compatible = \"dynalink,rta1320\", .data = &board_rta1320_16m, },\n #endif /* CONFIG_BCM63XX_CPU_6338 */\n #ifdef CONFIG_BCM63XX_CPU_6345\n \t{ .compatible = \"brcm,bcm96345gw2\", .data = &board_96345gw2, },\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/514-board_bcm6345.patch",
    "content": "--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c\n+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c\n@@ -1057,6 +1057,19 @@ static struct board_info __initdata boar\n \t.name = \"96345GW2\",\n \t.expected_cpu_id = 0x6345,\n };\n+\n+static struct board_info __initdata board_rta770w = {\n+\t.name = \"RTA770BW\",\n+\t.expected_cpu_id = 0x6345,\n+\n+\t.has_enet0 = 1,\n+\t.enet0 = {\n+\t\t.has_phy = 1,\n+\t\t.phy_id = 0,\n+\t\t.force_speed_100 = 1,\n+\t\t.force_duplex_full = 1,\n+\t},\n+};\n #endif /* CONFIG_BCM63XX_CPU_6345 */\n \n /*\n@@ -1383,6 +1396,7 @@ static const struct board_info __initcon\n #endif /* CONFIG_BCM63XX_CPU_6338 */\n #ifdef CONFIG_BCM63XX_CPU_6345\n \t&board_96345gw2,\n+\t&board_rta770w,\n #endif /* CONFIG_BCM63XX_CPU_6345 */\n #ifdef CONFIG_BCM63XX_CPU_6348\n \t&board_96348r,\n@@ -1441,6 +1455,8 @@ static struct of_device_id const bcm963x\n #endif /* CONFIG_BCM63XX_CPU_6338 */\n #ifdef CONFIG_BCM63XX_CPU_6345\n \t{ .compatible = \"brcm,bcm96345gw2\", .data = &board_96345gw2, },\n+\t{ .compatible = \"dynalink,rta770bw\", .data = &board_rta770w, },\n+\t{ .compatible = \"dynalink,rta770w\", .data = &board_rta770w, },\n #endif /* CONFIG_BCM63XX_CPU_6345 */\n #ifdef CONFIG_BCM63XX_CPU_6348\n \t{ .compatible = \"belkin,f5d7633\", .data = &board_96348gw_10, },\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/515-board-bcm6348.patch",
    "content": "--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c\n+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c\n@@ -1252,6 +1252,275 @@ static struct board_info __initdata boar\n \t\t.force_duplex_full = 1,\n \t},\n };\n+\n+static struct board_info __initdata board_96348A_122 = {\n+\t.name = \"96348A-122\",\n+\t.expected_cpu_id = 0x6348,\n+\n+\t.has_pci = 1,\n+\t.has_ohci0 = 1,\n+\n+\t.has_enet1 = 1,\n+\t.enet1 = {\n+\t\t.has_phy = 1,\n+\t\t.phy_id = 0,\n+\t\t.force_speed_100 = 1,\n+\t\t.force_duplex_full = 1,\n+\t},\n+\n+\t.use_fallback_sprom = 1,\n+\t.fallback_sprom = {\n+\t\t.type = SPROM_BCM4318,\n+\t\t.pci_bus = 0,\n+\t\t.pci_dev = 1,\n+\t},\n+};\n+\n+static struct board_info __initdata board_96348_D4PW = {\n+\t.name = \"D-4P-W\",\n+\t.expected_cpu_id = 0x6348,\n+\n+\t.has_pci = 1,\n+\n+\t.has_enet1 = 1,\n+\t.enet1 = {\n+\t\t.has_phy = 1,\n+\t\t.phy_id = 0,\n+\t\t.force_speed_100 = 1,\n+\t\t.force_duplex_full = 1,\n+\t},\n+};\n+\n+static struct board_info __initdata board_96348gw_10_AR1004G = {\n+\t.name = \"AR1004G\",\n+\t.expected_cpu_id = 0x6348,\n+\n+\t.has_pci = 1,\n+\n+\t.has_enet1 = 1,\n+\t.enet1 = {\n+\t\t.has_phy = 1,\n+\t\t.phy_id = 0,\n+\t\t.force_speed_100 = 1,\n+\t\t.force_duplex_full = 1,\n+\t},\n+};\n+\n+static struct board_info __initdata board_96348sv = {\n+\t.name = \"MAGIC\",\n+\t.expected_cpu_id = 0x6348,\n+\n+\t.has_pccard = 1,\n+\t.has_pci = 1,\n+\t.has_ohci0 = 1,\n+\n+\t.has_enet0 = 1,\n+\t.enet0 = {\n+\t\t.has_phy = 1,\n+\t\t.use_internal_phy = 1,\n+\t},\n+\n+\t.has_enet1 = 1,\n+\t.enet1 = {\n+\t\t/* it has BP_ENET_EXTERNAL_PHY */\n+\t\t.has_phy = 1,\n+\t\t.phy_id = 0,\n+\t\t.force_speed_100 = 1,\n+\t\t.force_duplex_full = 1,\n+\t},\n+};\n+\n+/* NetGear DG834G v4 */\n+static struct board_info __initdata board_96348W3 = {\n+ \t.name = \"96348W3\",\n+\t.expected_cpu_id = 0x6348,\n+\n+\t.has_pci = 1,\n+\t.has_ohci0 = 1,\n+\n+\t.has_enet1 = 1,\n+\t.enet1 = {\n+\t\t.has_phy = 1,\n+\t\t.phy_id = 0,\n+\t\t.force_speed_100 = 1,\n+\t\t.force_duplex_full = 1,\n+\t},\n+};\n+\n+static struct board_info __initdata board_CPVA502plus = {\n+\t.name = \"CPVA502+\",\n+\t.expected_cpu_id = 0x6348,\n+\n+\t.has_pci = 1,\n+\t.ephy_reset_gpio = 4,\n+\t.ephy_reset_gpio_flags = GPIO_ACTIVE_LOW,\n+\n+\t.has_enet0 = 1,\n+\t.enet0 = {\n+\t\t.has_phy = 1,\n+\t\t.use_internal_phy = 1,\n+\t},\n+\n+\t.has_enet1 = 1,\n+\t.enet1 = {\n+\t\t.has_phy = 1,\n+\t\t.phy_id = 0,\n+\t},\n+\n+\t.use_fallback_sprom = 1,\n+\t.fallback_sprom = {\n+\t\t.type = SPROM_BCM4318,\n+\t\t.pci_bus = 0,\n+\t\t.pci_dev = 1,\n+\t},\n+};\n+\n+static struct board_info __initdata board_ct536_ct5621 = {\n+\t.name = \"CT536_CT5621\",\n+\t.expected_cpu_id = 0x6348,\n+\n+\t.has_pccard = 1,\n+\t.has_pci = 1,\n+\t.has_ohci0 = 1,\n+\n+\t.has_enet1 = 1,\n+\t.enet1 = {\n+\t\t.has_phy = 1,\n+\t\t.phy_id = 0,\n+\t\t.force_speed_100 = 1,\n+\t\t.force_duplex_full = 1,\n+\t},\n+\n+\t.use_fallback_sprom = 1,\n+\t.fallback_sprom = {\n+\t\t.type = SPROM_BCM4318,\n+\t\t.pci_bus = 0,\n+\t\t.pci_dev = 1,\n+\t},\n+};\n+\n+static struct board_info __initdata board_FAST2604 = {\n+\t.name = \"F@ST2604\",\n+\t.expected_cpu_id = 0x6348,\n+\n+\t.has_pci = 1,\n+\t.has_ohci0 = 1,\n+\n+\t.has_enet1 = 1,\n+\t.enet1 = {\n+\t\t.has_phy = 1,\n+\t\t.phy_id = 0,\n+\t\t.force_speed_100 = 1,\n+\t\t.force_duplex_full = 1,\n+\t},\n+};\n+\n+static struct board_info __initdata board_gw6000 = {\n+\t.name = \"GW6000\",\n+\t.expected_cpu_id = 0x6348,\n+\n+\t.has_pci = 1,\n+\t.has_ohci0 = 1,\n+\n+\t.has_enet0 = 1,\n+\t.enet0 = {\n+\t\t.has_phy = 1,\n+\t\t.use_internal_phy = 1,\n+\t},\n+\n+\t.has_enet1 = 1,\n+\t.enet1 = {\n+\t\t.force_speed_100 = 1,\n+\t\t.force_duplex_full = 1,\n+\t},\n+};\n+\n+static struct board_info __initdata board_gw6200 = {\n+\t.name = \"GW6200\",\n+\t.expected_cpu_id = 0x6348,\n+\n+\t.has_pci = 1,\n+\t.has_ohci0 = 1,\n+\n+\t.has_enet0 = 1,\n+\t.enet0 = {\n+\t\t.has_phy = 1,\n+\t\t.use_internal_phy = 1,\n+\t},\n+\n+\t.has_enet1 = 1,\n+\t.enet1 = {\n+\t\t.force_speed_100 = 1,\n+\t\t.force_duplex_full = 1,\n+\t},\n+};\n+\n+static struct sprom_fixup __initdata spw500v_fixups[] = {\n+\t{ .offset = 46, .value = 0x3046 },\n+\t{ .offset = 47, .value = 0x15a7 },\n+\t{ .offset = 48, .value = 0xfa89 },\n+\t{ .offset = 49, .value = 0xfe79 },\n+\t{ .offset = 57, .value = 0x6a49 },\n+};\n+\n+static struct board_info __initdata board_spw500v = {\n+\t.name = \"SPW500V\",\n+\t.expected_cpu_id = 0x6348,\n+\n+\t.has_pci = 1,\n+\n+\t.has_enet0 = 1,\n+\t.enet0 = {\n+\t\t.has_phy = 1,\n+\t\t.use_internal_phy = 1,\n+\t},\n+\n+\t.use_fallback_sprom = 1,\n+\t.fallback_sprom = {\n+\t\t.type = SPROM_BCM4318,\n+\t\t.pci_bus = 0,\n+\t\t.pci_dev = 1,\n+\t\t.board_fixups = spw500v_fixups,\n+\t\t.num_board_fixups = ARRAY_SIZE(spw500v_fixups),\n+\t},\n+};\n+\n+/* BT Voyager 2110 */\n+static struct board_info __initdata board_V2110 = {\n+\t.name = \"V2110\",\n+\t.expected_cpu_id = 0x6348,\n+\n+\t.has_pci = 1,\n+\n+\t.has_enet1 = 1,\n+\t.enet1 = {\n+\t\t.has_phy = 1,\n+\t\t.phy_id = 0,\n+\t\t.force_speed_100 = 1,\n+\t\t.force_duplex_full = 1,\n+\t},\n+};\n+\n+static struct board_info __initdata board_V2500V_BB = {\n+\t.name = \"V2500V_BB\",\n+\t.expected_cpu_id = 0x6348,\n+\n+\t.has_pci = 1,\n+\n+\t.has_enet0 = 1,\n+\t.enet0 = {\n+\t\t.has_phy = 1,\n+\t\t.use_internal_phy = 1,\n+\t},\n+\n+\t.has_enet1 = 1,\n+\t.enet1 = {\n+\t\t.has_phy = 1,\n+\t\t.phy_id = 0,\n+\t\t.force_speed_100 = 1,\n+\t\t.force_duplex_full = 1,\n+\t},\n+};\n #endif /* CONFIG_BCM63XX_CPU_6348 */\n \n /*\n@@ -1407,6 +1676,19 @@ static const struct board_info __initcon\n \t&board_DV201AMR,\n \t&board_96348gw_a,\n \t&board_rta1025w_16,\n+\t&board_96348A_122,\n+\t&board_96348_D4PW,\n+\t&board_96348gw_10_AR1004G,\n+\t&board_96348sv,\n+\t&board_96348W3,\n+\t&board_CPVA502plus,\n+\t&board_ct536_ct5621,\n+\t&board_FAST2604,\n+\t&board_gw6000,\n+\t&board_gw6200,\n+\t&board_spw500v,\n+\t&board_V2110,\n+\t&board_V2500V_BB,\n #endif /* CONFIG_BCM63XX_CPU_6348 */\n #ifdef CONFIG_BCM63XX_CPU_6358\n \t&board_96358vw,\n@@ -1459,15 +1741,29 @@ static struct of_device_id const bcm963x\n \t{ .compatible = \"dynalink,rta770w\", .data = &board_rta770w, },\n #endif /* CONFIG_BCM63XX_CPU_6345 */\n #ifdef CONFIG_BCM63XX_CPU_6348\n+\t{ .compatible = \"asmax,ar-1004g\", .data = &board_96348gw_10_AR1004G, },\n \t{ .compatible = \"belkin,f5d7633\", .data = &board_96348gw_10, },\n \t{ .compatible = \"brcm,bcm96348r\", .data = &board_96348r, },\n \t{ .compatible = \"brcm,bcm96348gw-10\", .data = &board_96348gw_10, },\n \t{ .compatible = \"brcm,bcm96348gw-11\", .data = &board_96348gw_11, },\n \t{ .compatible = \"brcm,bcm96348gw-a\", .data = &board_96348gw_a, },\n+\t{ .compatible = \"bt,voyager-2110\", .data = &board_V2110, },\n+\t{ .compatible = \"bt,voyager-2500v-bb\", .data = &board_V2500V_BB, },\n+\t{ .compatible = \"comtrend,ct-5365\", .data = &board_96348A_122, },\n+\t{ .compatible = \"comtrend,ct-536plus\", .data = &board_ct536_ct5621, },\n+\t{ .compatible = \"comtrend,ct-5621\", .data = &board_ct536_ct5621, },\n+\t{ .compatible = \"d-link,dsl-2640b-b\", .data = &board_96348_D4PW, },\n \t{ .compatible = \"davolink,dv-201amr\", .data = &board_DV201AMR, },\n \t{ .compatible = \"dynalink,rta1025w\", .data = &board_rta1025w_16, },\n \t{ .compatible = \"netgear,dg834gt-pn\", .data = &board_96348gw_10, },\n+ \t{ .compatible = \"netgear,dg834g-v4\", .data = &board_96348W3, },\n \t{ .compatible = \"sagem,fast-2404\", .data = &board_FAST2404, },\n+ \t{ .compatible = \"sagem,fast-2604\", .data = &board_FAST2604, },\n+\t{ .compatible = \"t-com,speedport-w-500v\", .data = &board_spw500v, },\n+\t{ .compatible = \"tecom,gw6000\", .data = &board_gw6000, },\n+\t{ .compatible = \"tecom,gw6200\", .data = &board_gw6200, },\n+\t{ .compatible = \"telsey,cpva502plus\", .data = &board_CPVA502plus, },\n+\t{ .compatible = \"telsey,magic\", .data = &board_96348sv, },\n \t{ .compatible = \"tp-link,td-w8900gb\", .data = &board_96348gw_11, },\n \t{ .compatible = \"usrobotics,usr9108\", .data = &board_96348gw_a, },\n #endif /* CONFIG_BCM63XX_CPU_6348 */\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/516-board-bcm6358.patch",
    "content": "--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c\n+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c\n@@ -9,6 +9,7 @@\n #include <linux/init.h>\n #include <linux/kernel.h>\n #include <linux/string.h>\n+#include <linux/pci_ids.h>\n #include <asm/addrspace.h>\n #include <bcm63xx_board.h>\n #include <bcm63xx_cpu.h>\n@@ -1601,6 +1602,88 @@ static struct board_info __initdata boar\n \t},\n };\n \n+static struct board_info __initdata board_CPVA642 = {\n+\t.name = \"CPVA642\",\n+\t.expected_cpu_id = 0x6358,\n+\n+\t.has_pci = 1,\n+\t.has_ohci0 = 1,\n+\t.has_ehci0 = 1,\n+\n+\t.has_enet1 = 1,\n+\t.enet1 = {\n+\t\t.has_phy = 1,\n+\t\t.phy_id = 0,\n+\t\t.force_speed_100 = 1,\n+\t\t.force_duplex_full = 1,\n+ \t},\n+};\n+\n+static struct board_info __initdata board_ct6373_1 = {\n+\t.name = \"CT6373-1\",\n+\t.expected_cpu_id = 0x6358,\n+\n+\t.has_pci = 1,\n+\t.has_ohci0 = 1,\n+\t.has_ehci0 = 1,\n+\n+\t.has_enet1 = 1,\n+\t.enet1 = {\n+\t\t.has_phy = 1,\n+\t\t.phy_id = 0,\n+\t\t.force_speed_100 = 1,\n+\t\t.force_duplex_full = 1,\n+\t},\n+\n+\t.use_fallback_sprom = 1,\n+\t.fallback_sprom = {\n+\t\t.type = SPROM_BCM4318,\n+\t\t.pci_bus = 0,\n+\t\t.pci_dev = 1,\n+\t},\n+};\n+\n+/* D-Link DSL-274xB revison C2/C3 */\n+static struct board_info __initdata board_dsl_274xb_rev_c = {\n+\t.name = \"AW4139\",\n+\t.expected_cpu_id = 0x6358,\n+\n+\t.has_pci = 1,\n+\n+\t.has_enet1 = 1,\n+\t.enet1 = {\n+\t\t.has_phy = 1,\n+\t\t.phy_id = 0,\n+\t\t.force_speed_100 = 1,\n+\t\t.force_duplex_full = 1,\n+\t},\n+};\n+\n+/* D-Link DVA-G3810BN/TL */\n+static struct board_info __initdata board_DVAG3810BN = {\n+\t.name = \"DVAG3810BN\",\n+\t.expected_cpu_id = 0x6358,\n+\n+\t.has_pccard = 1,\n+\t.has_pci = 1,\n+\t.has_ohci0 = 1,\n+\t.has_ehci0 = 1,\n+\n+\t.has_enet0 = 1,\n+\t.enet0 = {\n+\t\t.has_phy = 1,\n+\t\t.use_internal_phy = 1,\n+\t},\n+\n+\t.has_enet1 = 1,\n+\t.enet1 = {\n+\t\t.has_phy = 1,\n+\t\t.phy_id = 0,\n+\t\t.force_speed_100 = 1,\n+\t\t.force_duplex_full = 1,\n+\t},\n+};\n+\n static struct board_info __initdata board_DWVS0 = {\n \t.name = \"DWV-S0\",\n \t.expected_cpu_id = 0x6358,\n@@ -1624,6 +1707,238 @@ static struct board_info __initdata boar\n \t\t.force_duplex_full = 1,\n \t},\n };\n+\n+static struct board_info __initdata board_homehub2a = {\n+\t.name = \"HOMEHUB2A\",\n+\t.expected_cpu_id = 0x6358,\n+\n+\t.has_pci = 1,\n+\t.has_ohci0 = 1,\n+\t.has_ehci0 = 1,\n+\t.num_usbh_ports = 2,\n+\n+\t.has_enet1 = 1,\n+\t.enet1 = {\n+\t\t.has_phy = 1,\n+\t\t.phy_id = 0,\n+\t\t.force_speed_100 = 1,\n+\t\t.force_duplex_full = 1,\n+\t},\n+\n+\t.use_fallback_sprom = 1,\n+\t.fallback_sprom = {\n+\t\t.type = SPROM_BCM4322,\n+\t\t.pci_bus = 0,\n+\t\t.pci_dev = 1,\n+\t},\n+};\n+\n+static struct board_info __initdata board_HW520 = {\n+\t.name = \"HW6358GW_B\",\n+\t.expected_cpu_id = 0x6358,\n+\n+\t.has_pci = 1,\n+\t.has_ohci0 = 1,\n+\t.has_ehci0 = 1,\n+\n+\t.has_enet0 = 1,\n+\t.enet0 = {\n+\t\t.has_phy = 1,\n+\t\t.use_internal_phy = 1,\n+\t},\n+\n+\t.has_enet1 = 1,\n+\t.enet1 = {\n+\t\t.has_phy = 1,\n+\t\t.phy_id = 0,\n+\t\t.force_speed_100 = 1,\n+\t\t.force_duplex_full = 1,\n+\t},\n+\n+\t.use_fallback_sprom = 1,\n+\t.fallback_sprom = {\n+\t\t.type = SPROM_BCM4318,\n+\t\t.pci_bus = 0,\n+\t\t.pci_dev = 1,\n+\t},\n+};\n+\n+static struct board_info __initdata board_HW553 = {\n+\t.name = \"HW553\",\n+\t.expected_cpu_id = 0x6358,\n+\n+\t.has_pci = 1,\n+\t.has_ohci0 = 1,\n+\t.has_ehci0 = 1,\n+\t.num_usbh_ports = 2,\n+\n+\t.has_enet1 = 1,\n+\t.enet1 = {\n+\t\t.has_phy = 1,\n+\t\t.phy_id = 0,\n+\t\t.force_speed_100 = 1,\n+\t\t.force_duplex_full = 1,\n+\t},\n+\n+\t.use_fallback_sprom = 1,\n+\t.fallback_sprom = {\n+\t\t.type = SPROM_BCM4318,\n+\t\t.pci_bus = 0,\n+\t\t.pci_dev = 1,\n+\t},\n+};\n+\n+static struct board_info __initdata board_HW556_A = {\n+\t.name = \"HW556_A\",\n+\t.expected_cpu_id = 0x6358,\n+\n+\t.has_pci = 1,\n+\t.has_ohci0 = 1,\n+\t.has_ehci0 = 1,\n+\t.num_usbh_ports = 2,\n+\n+\t.has_caldata = 1,\n+\t.caldata = {\n+\t\t{\n+\t\t\t.vendor = PCI_VENDOR_ID_ATHEROS,\n+\t\t\t.caldata_offset = 0xf7e000,\n+\t\t\t.slot = 1,\n+\t\t\t.endian_check = 1,\n+\t\t\t.led_pin = 2,\n+\t\t\t.led_active_high = 1,\n+\t\t},\n+\t},\n+\n+\t.has_enet1 = 1,\n+\t.enet1 = {\n+\t\t.has_phy = 1,\n+\t\t.phy_id = 0,\n+\t\t.force_speed_100 = 1,\n+\t\t.force_duplex_full = 1,\n+\t},\n+};\n+\n+static struct board_info __initdata board_HW556_B = {\n+\t.name = \"HW556_B\",\n+\t.expected_cpu_id = 0x6358,\n+\n+\t.has_pci = 1,\n+\t.has_ohci0 = 1,\n+\t.has_ehci0 = 1,\n+\t.num_usbh_ports = 2,\n+\n+\t.has_caldata = 1,\n+\t.caldata = {\n+\t\t{\n+\t\t\t.vendor = PCI_VENDOR_ID_ATHEROS,\n+\t\t\t.caldata_offset = 0xefe000,\n+\t\t\t.slot = 1,\n+\t\t\t.endian_check = 1,\n+\t\t\t.led_pin = 2,\n+\t\t\t.led_active_high = 1,\n+\t\t},\n+\t},\n+\n+\t.has_enet1 = 1,\n+\t.enet1 = {\n+\t\t.has_phy = 1,\n+\t\t.phy_id = 0,\n+\t\t.force_speed_100 = 1,\n+\t\t.force_duplex_full = 1,\n+\t},\n+};\n+\n+static struct board_info __initdata board_HW556_C = {\n+\t.name = \"HW556_C\",\n+\t.expected_cpu_id = 0x6358,\n+\n+\t.has_pci = 1,\n+\t.has_ohci0 = 1,\n+\t.has_ehci0 = 1,\n+\t.num_usbh_ports = 2,\n+\n+\t.has_caldata = 1,\n+\t.caldata = {\n+\t\t{\n+\t\t\t.vendor = PCI_VENDOR_ID_RALINK,\n+\t\t\t.caldata_offset = 0xeffe00,\n+\t\t\t.slot = 1,\n+\t\t\t.eeprom = \"rt2x00.eeprom\",\n+\t\t},\n+\t},\n+\n+\t.has_enet1 = 1,\n+\t.enet1 = {\n+\t\t.has_phy = 1,\n+\t\t.phy_id = 0,\n+\t\t.force_speed_100 = 1,\n+\t\t.force_duplex_full = 1,\n+\t},\n+};\n+\n+static struct board_info __initdata board_nb4_ser_r0 = {\n+\t.name = \"NB4-SER-r0\",\n+\t.expected_cpu_id = 0x6358,\n+\n+\t.has_pccard = 1,\n+\t.has_pci = 1,\n+\t.has_ohci0 = 1,\n+\t.has_ehci0 = 1,\n+\t.num_usbh_ports = 2,\n+\n+\t.has_enet0 = 1,\n+\t.enet0 = {\n+\t\t.has_phy = 1,\n+\t\t.use_internal_phy = 1,\n+\t},\n+\n+\t.has_enet1 = 1,\n+\t.enet1 = {\n+\t\t.has_phy = 1,\n+\t\t.phy_id = 0,\n+\t\t.force_speed_100 = 1,\n+\t\t.force_duplex_full = 1,\n+\t},\n+};\n+\n+static struct board_info __initdata board_nb4_fxc_r1 = {\n+\t.name = \"NB4-FXC-r1\",\n+\t.expected_cpu_id = 0x6358,\n+\n+\t.has_pccard = 1,\n+\t.has_pci = 1,\n+\t.has_ohci0 = 1,\n+\t.has_ehci0 = 1,\n+\t.num_usbh_ports = 2,\n+\n+\t.has_enet0 = 1,\n+\t.enet0 = {\n+\t\t.has_phy = 1,\n+\t\t.use_internal_phy = 1,\n+\t},\n+\n+\t.has_enet1 = 1,\n+\t.enet1 = {\n+\t\t.has_phy = 1,\n+\t\t.phy_id = 0,\n+\t\t.force_speed_100 = 1,\n+\t\t.force_duplex_full = 1,\n+\t},\n+};\n+\n+ /* T-Home Speedport W 303V Typ B */\n+static struct board_info __initdata board_spw303v = {\n+\t.name = \"96358-502V\",\n+\t.expected_cpu_id = 0x6358,\n+\n+\t.has_pci = 1,\n+\n+\t.has_enet0 = 1,\n+\t.enet0 = {\n+\t\t.has_phy = 1,\n+\t\t.use_internal_phy = 1,\n+\t},\n+};\n #endif /* CONFIG_BCM63XX_CPU_6358 */\n \n /*\n@@ -1694,7 +2009,20 @@ static const struct board_info __initcon\n \t&board_96358vw,\n \t&board_96358vw2,\n \t&board_AGPFS0,\n+\t&board_CPVA642,\n+\t&board_ct6373_1,\n+\t&board_dsl_274xb_rev_c,\n+\t&board_DVAG3810BN,\n \t&board_DWVS0,\n+\t&board_homehub2a,\n+\t&board_HW520,\n+\t&board_HW553,\n+\t&board_HW556_A,\n+\t&board_HW556_B,\n+\t&board_HW556_C,\n+\t&board_nb4_ser_r0,\n+\t&board_nb4_fxc_r1,\n+\t&board_spw303v,\n #endif /* CONFIG_BCM63XX_CPU_6358 */\n };\n \n@@ -1771,11 +2099,24 @@ static struct of_device_id const bcm963x\n \t{ .compatible = \"alcatel,rg100a\", .data = &board_96358vw2, },\n \t{ .compatible = \"brcm,bcm96358vw\", .data = &board_96358vw, },\n \t{ .compatible = \"brcm,bcm96358vw2\", .data = &board_96358vw2, },\n+\t{ .compatible = \"bt,home-hub-2-a\", .data = &board_homehub2a, },\n+\t{ .compatible = \"comtrend,ct-6373\", .data = &board_ct6373_1, },\n \t{ .compatible = \"d-link,dsl-2650u\", .data = &board_96358vw2, },\n+\t{ .compatible = \"d-link,dsl-274xb-c2\", .data = &board_dsl_274xb_rev_c, },\n+\t{ .compatible = \"d-link,dva-g3810bn-tl\", .data = &board_DVAG3810BN, },\n+\t{ .compatible = \"huawei,echolife-hg520v\", .data = &board_HW520, },\n+\t{ .compatible = \"huawei,echolife-hg553\", .data = &board_HW553, },\n+\t{ .compatible = \"huawei,echolife-hg556a-a\", .data = &board_HW556_A, },\n+\t{ .compatible = \"huawei,echolife-hg556a-b\", .data = &board_HW556_B, },\n+\t{ .compatible = \"huawei,echolife-hg556a-c\", .data = &board_HW556_C, },\n \t{ .compatible = \"pirelli,a226g\", .data = &board_DWVS0, },\n \t{ .compatible = \"pirelli,a226m\", .data = &board_DWVS0, },\n \t{ .compatible = \"pirelli,a226m-fwb\", .data = &board_DWVS0, },\n \t{ .compatible = \"pirelli,agpf-s0\", .data = &board_AGPFS0, },\n+\t{ .compatible = \"sfr,neufbox-4-sercomm-r0\", .data = &board_nb4_ser_r0, },\n+\t{ .compatible = \"sfr,neufbox-4-foxconn-r1\", .data = &board_nb4_fxc_r1, },\n+\t{ .compatible = \"t-com,speedport-w-303v\", .data = &board_spw303v, },\n+\t{ .compatible = \"telsey,cpva642\", .data = &board_CPVA642, },\n #endif /* CONFIG_BCM63XX_CPU_6358 */\n #ifdef CONFIG_BCM63XX_CPU_6362\n #endif /* CONFIG_BCM63XX_CPU_6362 */\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/517-board_bcm6362.patch",
    "content": "--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c\n+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c\n@@ -1941,6 +1941,117 @@ static struct board_info __initdata boar\n };\n #endif /* CONFIG_BCM63XX_CPU_6358 */\n \n+#ifdef CONFIG_BCM63XX_CPU_6362\n+static struct board_info __initdata board_dgnd3700v2 = {\n+\t.name = \"96362ADVN2xh\",\n+\t.expected_cpu_id = 0x6362,\n+\n+\t.has_pci = 1,\n+\t.has_ohci0 = 1,\n+\t.has_ehci0 = 1,\n+\t.num_usbh_ports = 2,\n+\n+\t.has_enetsw = 1,\n+\t.enetsw = {\n+\t\t.used_ports = {\n+\t\t\t[4] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 0xff,\n+\t\t\t\t.bypass_link = 1,\n+\t\t\t\t.force_speed = 1000,\n+\t\t\t\t.force_duplex_full = 1,\n+\t\t\t\t.name = \"RGMII\",\n+\t\t\t},\n+\t\t},\n+\t},\n+};\n+\n+static struct board_info __initdata board_fast2504n = {\n+\t.name = \"F@ST2504n\",\n+\t.expected_cpu_id = 0x6362,\n+\n+\t.has_enetsw = 1,\n+\t.enetsw = {\n+\t\t.used_ports = {\n+\t\t\t[0] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 1,\n+\t\t\t\t.name = \"Port 1\",\n+\t\t\t},\n+\t\t\t[1] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 2,\n+\t\t\t\t.name = \"Port 2\",\n+\t\t\t},\n+\t\t\t[2] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 3,\n+\t\t\t\t.name = \"Port 3\",\n+\t\t\t},\n+\t\t\t[3] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 4,\n+\t\t\t\t.name = \"Port 4\",\n+\t\t\t},\n+\t\t},\n+\t},\n+};\n+\n+static struct board_info __initdata board_hg253s_v2 = {\n+\t.name = \"hg253s\",\n+\t.expected_cpu_id = 0x6362,\n+\n+\t.has_ohci0 = 1,\n+\t.has_ehci0 = 1,\n+\t.num_usbh_ports = 1,\n+\n+\t.has_enetsw = 1,\n+\t.enetsw = {\n+\t\t.used_ports = {\n+\t\t\t[4] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 0xff,\n+\t\t\t\t.bypass_link = 1,\n+\t\t\t\t.force_speed = 1000,\n+\t\t\t\t.force_duplex_full = 1,\n+\t\t\t\t.timing_sel = 1,\n+\t\t\t\t.name = \"RGMII\",\n+\t\t\t},\n+\n+\t\t\t[5] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 24,\n+\t\t\t\t.timing_sel = 1,\n+\t\t\t\t.name = \"WAN\",\n+\t\t\t},\n+\t\t},\n+\t},\n+};\n+\n+static struct board_info __initdata board_nb6 = {\n+\t.name = \"NB6\",\n+\t.expected_cpu_id = 0x6362,\n+\n+\t.has_ohci0 = 1,\n+\t.has_ehci0 = 1,\n+\t.num_usbh_ports = 2,\n+\n+\t.has_enetsw = 1,\n+\t.enetsw = {\n+\t\t.used_ports = {\n+\t\t\t[4] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 0xff,\n+\t\t\t\t.bypass_link = 1,\n+\t\t\t\t.force_speed = 1000,\n+\t\t\t\t.force_duplex_full = 1,\n+\t\t\t\t.name = \"RGMII\",\n+\t\t\t},\n+\t\t},\n+\t},\n+};\n+#endif /* CONFIG_BCM63XX_CPU_6362 */\n+\n /*\n  * all boards\n  */\n@@ -2024,6 +2135,12 @@ static const struct board_info __initcon\n \t&board_nb4_fxc_r1,\n \t&board_spw303v,\n #endif /* CONFIG_BCM63XX_CPU_6358 */\n+#ifdef CONFIG_BCM63XX_CPU_6362\n+\t&board_dgnd3700v2,\n+\t&board_fast2504n,\n+\t&board_hg253s_v2,\n+\t&board_nb6,\n+#endif /* CONFIG_BCM63XX_CPU_6362 */\n };\n \n static struct of_device_id const bcm963xx_boards_dt[] = {\n@@ -2119,6 +2236,10 @@ static struct of_device_id const bcm963x\n \t{ .compatible = \"telsey,cpva642\", .data = &board_CPVA642, },\n #endif /* CONFIG_BCM63XX_CPU_6358 */\n #ifdef CONFIG_BCM63XX_CPU_6362\n+\t{ .compatible = \"huawei,hg253s-v2\", .data = &board_hg253s_v2, },\n+\t{ .compatible = \"netgear,dgnd3700-v2\", .data = &board_dgnd3700v2, },\n+\t{ .compatible = \"sagem,fast-2504n\", .data = &board_fast2504n, },\n+\t{ .compatible = \"sfr,neufbox-6-sercomm-r0\", .data = &board_nb6, },\n #endif /* CONFIG_BCM63XX_CPU_6362 */\n #ifdef CONFIG_BCM63XX_CPU_6368\n #endif /* CONFIG_BCM63XX_CPU_6368 */\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/518-board_bcm6368.patch",
    "content": "--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c\n+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c\n@@ -10,6 +10,8 @@\n #include <linux/kernel.h>\n #include <linux/string.h>\n #include <linux/pci_ids.h>\n+#include <linux/platform_data/b53.h>\n+#include <linux/spi/spi.h>\n #include <asm/addrspace.h>\n #include <bcm63xx_board.h>\n #include <bcm63xx_cpu.h>\n@@ -2053,6 +2055,648 @@ static struct board_info __initdata boar\n #endif /* CONFIG_BCM63XX_CPU_6362 */\n \n /*\n+ * known 6368 boards\n+ */\n+#ifdef CONFIG_BCM63XX_CPU_6368\n+static struct board_info __initdata board_96368mvngr = {\n+\t.name = \"96368MVNgr\",\n+\t.expected_cpu_id = 0x6368,\n+\n+\t.has_pci = 1,\n+\t.has_ohci0 = 1,\n+\t.has_ehci0 = 1,\n+\n+\t.has_enetsw = 1,\n+\t.enetsw = {\n+\t\t.used_ports = {\n+\t\t\t[0] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 1,\n+\t\t\t\t.name = \"port1\",\n+\t\t\t},\n+\t\t\t[1] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 2,\n+\t\t\t\t.name = \"port2\",\n+\t\t\t},\n+\t\t\t[2] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 3,\n+\t\t\t\t.name = \"port3\",\n+\t\t\t},\n+\t\t\t[3] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 4,\n+\t\t\t\t.name = \"port4\",\n+\t\t\t},\n+\t\t},\n+\t},\n+};\n+\n+static struct board_info __initdata board_96368mvwg = {\n+\t.name = \"96368MVWG\",\n+\t.expected_cpu_id = 0x6368,\n+\n+\t.has_pci = 1,\n+\t.has_ohci0 = 1,\n+\t.has_ehci0 = 1,\n+\n+\t.has_usbd = 1,\n+\t.usbd = {\n+\t\t.use_fullspeed = 0,\n+\t\t.port_no = 0,\n+\t},\n+\n+\t.has_enetsw = 1,\n+\t.enetsw = {\n+\t\t.used_ports = {\n+\t\t\t[1] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 2,\n+\t\t\t\t.name = \"port1\",\n+\t\t\t},\n+\t\t\t[2] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 3,\n+\t\t\t\t.name = \"port2\",\n+\t\t\t},\n+\t\t\t[4] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 0x12,\n+\t\t\t\t.name = \"port0\",\n+\t\t\t},\n+\t\t\t[5] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 0x11,\n+\t\t\t\t.name = \"port3\",\n+\t\t\t},\n+\t\t},\n+\t},\n+};\n+\n+static struct board_info __initdata board_AV4202N = {\n+\t.name = \"96368_Swiss_S1\",\n+\t.expected_cpu_id = 0x6368,\n+\n+\t.has_pci = 1,\n+\t.has_ohci0 = 1,\n+\t.has_ehci0 = 1,\n+\t.num_usbh_ports = 2,\n+\n+\t.has_enetsw = 1,\n+\t.enetsw = {\n+\t\t.used_ports = {\n+\t\t\t[0] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 1,\n+\t\t\t\t.name = \"port1\",\n+\t\t\t},\n+\t\t\t[1] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 2,\n+\t\t\t\t.name = \"port2\",\n+\t\t\t},\n+\t\t\t[2] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 3,\n+\t\t\t\t.name = \"port3\",\n+\t\t\t},\n+\t\t\t[3] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 4,\n+\t\t\t\t.name = \"port4\",\n+\t\t\t},\n+\t\t},\n+\t},\n+\n+\t.use_fallback_sprom = 1,\n+\t.fallback_sprom = {\n+\t\t.type = SPROM_BCM4322,\n+\t\t.pci_bus = 0,\n+\t\t.pci_dev = 1,\n+\t},\n+};\n+\n+static struct board_info __initdata board_DGND3700v1_3800B = {\n+\t.name = \"U12L144T01\",\n+\t.expected_cpu_id = 0x6368,\n+\n+\t.has_pci = 1,\n+\t.has_ohci0 = 1,\n+\t.has_ehci0 = 1,\n+\t.num_usbh_ports = 2,\n+\n+\t.has_enetsw = 1,\n+\t.enetsw = {\n+\t\t.used_ports = {\n+\t\t\t[5] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 0xff,\n+\t\t\t\t.bypass_link = 1,\n+\t\t\t\t.force_speed = 1000,\n+\t\t\t\t.force_duplex_full = 1,\n+\t\t\t\t.name = \"RGMII\",\n+\t\t\t},\n+\t\t},\n+\t},\n+};\n+\n+static struct sprom_fixup __initdata EVG2000_fixups[] = {\n+  { .offset = 219, .value = 0xec08 },\n+};\n+\n+static struct board_info __initdata board_EVG2000 = {\n+\t.name = \"96369PVG\",\n+\t.expected_cpu_id = 0x6368,\n+\n+\t.has_pci = 1,\n+\t.has_ohci0 = 1,\n+\t.has_ehci0 = 1,\n+\t.num_usbh_ports = 2,\n+\n+\t.has_enetsw = 1,\n+\t.enetsw = {\n+\t\t.used_ports = {\n+\t\t\t[5] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 0xff,\n+\t\t\t\t.bypass_link = 1,\n+\t\t\t\t.force_speed = 1000,\n+\t\t\t\t.force_duplex_full = 1,\n+\t\t\t\t.name = \"RGMII\",\n+\t\t\t},\n+\t\t},\n+\t},\n+\n+\t.use_fallback_sprom = 1,\n+\t.fallback_sprom = {\n+\t\t.type = SPROM_BCM4322,\n+\t\t.pci_bus = 0,\n+\t\t.pci_dev = 1,\n+\t\t.board_fixups = EVG2000_fixups,\n+\t\t.num_board_fixups = ARRAY_SIZE(EVG2000_fixups),\n+\t},\n+};\n+\n+static struct board_info __initdata board_HG622 = {\n+\t.name = \"96368MVWG_hg622\",\n+\t.expected_cpu_id = 0x6368,\n+\n+\t.has_pci = 1,\n+\t.has_ohci0 = 1,\n+\t.has_ehci0 = 1,\n+\t.num_usbh_ports = 2,\n+\n+\t.has_caldata = 1,\n+\t.caldata = {\n+\t\t{\n+\t\t\t.vendor = PCI_VENDOR_ID_RALINK,\n+\t\t\t.caldata_offset = 0xfa0000,\n+\t\t\t.slot = 1,\n+\t\t\t.eeprom = \"rt2x00.eeprom\",\n+\t\t},\n+\t},\n+\n+\t.has_enetsw = 1,\n+\t.enetsw = {\n+\t\t.used_ports = {\n+\t\t\t[0] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 1,\n+\t\t\t\t.name = \"port1\",\n+\t\t\t},\n+\t\t\t[1] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 2,\n+\t\t\t\t.name = \"port2\",\n+\t\t\t},\n+\t\t\t[2] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 3,\n+\t\t\t\t.name = \"port3\",\n+\t\t\t},\n+\t\t\t[3] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 4,\n+\t\t\t\t.name = \"port4\",\n+\t\t\t},\n+\t\t},\n+\t},\n+};\n+\n+static struct board_info __initdata board_HG655b = {\n+\t.name = \"HW65x\",\n+\t.expected_cpu_id = 0x6368,\n+\n+\t.has_pci = 1,\n+\t.has_ohci0 = 1,\n+\t.has_ehci0 = 1,\n+\t.num_usbh_ports = 2,\n+\n+\t.has_caldata = 1,\n+\t.caldata = {\n+\t\t{\n+\t\t\t.vendor = PCI_VENDOR_ID_RALINK,\n+\t\t\t.caldata_offset = 0x7c0000,\n+\t\t\t.slot = 1,\n+\t\t\t.eeprom = \"rt2x00.eeprom\",\n+\t\t},\n+\t},\n+\n+\t.has_enetsw = 1,\n+\t.enetsw = {\n+\t\t.used_ports = {\n+\t\t\t[0] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 1,\n+\t\t\t\t.name = \"port1\",\n+\t\t\t},\n+\t\t\t[1] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 2,\n+\t\t\t\t.name = \"port2\",\n+\t\t\t},\n+\t\t\t[2] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 3,\n+\t\t\t\t.name = \"port3\",\n+\t\t\t},\n+\t\t\t[3] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 4,\n+\t\t\t\t.name = \"port4\",\n+\t\t\t},\n+\t\t},\n+\t},\n+};\n+\n+static struct board_info __initdata board_P870HW51A_V2 = {\n+\t.name = \"P870HW-51a_v2\",\n+\t.expected_cpu_id = 0x6368,\n+\n+\t.has_pci = 1,\n+\t.has_ohci0 = 1,\n+\t.has_ehci0 = 1,\n+\n+\t.has_enetsw = 1,\n+\t.enetsw = {\n+\t\t.used_ports = {\n+\t\t\t[0] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 1,\n+\t\t\t\t.name = \"port1\",\n+\t\t\t},\n+\t\t\t[1] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 2,\n+\t\t\t\t.name = \"port2\",\n+\t\t\t},\n+\t\t\t[2] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 3,\n+\t\t\t\t.name = \"port3\",\n+\t\t\t},\n+\t\t\t[3] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 4,\n+\t\t\t\t.name = \"port4\",\n+\t\t\t},\n+\t\t},\n+\t},\n+\n+\t.use_fallback_sprom = 1,\n+\t.fallback_sprom = {\n+\t\t.type = SPROM_BCM4318,\n+\t\t.pci_bus = 0,\n+\t\t.pci_dev = 1,\n+\t},\n+};\n+\n+static struct board_info __initdata board_R1000H = {\n+\t.name = \"R1000H\",\n+\t.expected_cpu_id = 0x6368,\n+\n+\t.has_pci = 1,\n+\t.has_ohci0 = 1,\n+\t.has_ehci0 = 1,\n+\n+\t.has_enetsw = 1,\n+\t.enetsw = {\n+\t\t.used_ports = {\n+\t\t\t[5] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 0xff,\n+\t\t\t\t.bypass_link = 1,\n+\t\t\t\t.force_speed = 1000,\n+\t\t\t\t.force_duplex_full = 1,\n+\t\t\t\t.name = \"RGMII\",\n+\t\t\t},\n+\t\t},\n+\t},\n+};\n+\n+static struct sprom_fixup __initdata vh4032n_fixups[] = {\n+\t{ .offset = 2, .value = 0x04d2 },\n+\t{ .offset = 4, .value = 0x4350 },\n+\t{ .offset = 65, .value = 0x1300 },\n+\t{ .offset = 68, .value = 0x0402 },\n+\t{ .offset = 70, .value = 0x0090 },\n+\t{ .offset = 71, .value = 0x4c19 },\n+\t{ .offset = 72, .value = 0x2345 },\n+\t{ .offset = 87, .value = 0x0315 },\n+\t{ .offset = 88, .value = 0x0315 },\n+\t{ .offset = 96, .value = 0x2048 },\n+\t{ .offset = 97, .value = 0xfed7 },\n+\t{ .offset = 98, .value = 0x15a6 },\n+\t{ .offset = 99, .value = 0xfaee },\n+\t{ .offset = 100, .value = 0x3e3a },\n+\t{ .offset = 101, .value = 0x3a36 },\n+\t{ .offset = 102, .value = 0xff7f },\n+\t{ .offset = 103, .value = 0x11b9 },\n+\t{ .offset = 104, .value = 0xfc53 },\n+\t{ .offset = 105, .value = 0xffe6 },\n+\t{ .offset = 106, .value = 0xfdd2 },\n+\t{ .offset = 107, .value = 0xfe49 },\n+\t{ .offset = 108, .value = 0xff6a },\n+\t{ .offset = 109, .value = 0x136e },\n+\t{ .offset = 110, .value = 0xfbed },\n+\t{ .offset = 111, .value = 0x0000 },\n+\t{ .offset = 112, .value = 0x2048 },\n+\t{ .offset = 113, .value = 0xfee2 },\n+\t{ .offset = 114, .value = 0x15e5 },\n+\t{ .offset = 115, .value = 0xfaed },\n+\t{ .offset = 116, .value = 0x3e3a },\n+\t{ .offset = 117, .value = 0x3a36 },\n+\t{ .offset = 118, .value = 0xffc8 },\n+\t{ .offset = 119, .value = 0x12b8 },\n+\t{ .offset = 120, .value = 0xfca1 },\n+\t{ .offset = 121, .value = 0xff9b },\n+\t{ .offset = 122, .value = 0x122a },\n+\t{ .offset = 123, .value = 0xfcc8 },\n+\t{ .offset = 124, .value = 0xff95 },\n+\t{ .offset = 125, .value = 0x146b },\n+\t{ .offset = 126, .value = 0xfbba },\n+\t{ .offset = 127, .value = 0x0000 },\n+\t{ .offset = 161, .value = 0x0000 },\n+\t{ .offset = 162, .value = 0x0000 },\n+\t{ .offset = 169, .value = 0x0000 },\n+\t{ .offset = 170, .value = 0x0000 },\n+\t{ .offset = 171, .value = 0x0000 },\n+\t{ .offset = 172, .value = 0x0000 },\n+\t{ .offset = 173, .value = 0x0000 },\n+\t{ .offset = 174, .value = 0x0000 },\n+\t{ .offset = 175, .value = 0x0000 },\n+\t{ .offset = 176, .value = 0x0000 },\n+\t{ .offset = 219, .value = 0x1108 },\n+};\n+\n+static struct board_info __initdata board_VH4032N = {\n+\t.name = \"VH4032N\",\n+\t.expected_cpu_id = 0x6368,\n+\n+\t.has_pci = 1,\n+\t.has_ohci0 = 1,\n+\t.has_ehci0 = 1,\n+\t.num_usbh_ports = 2,\n+\n+\t.has_enetsw = 1,\n+\t.enetsw = {\n+\t\t.used_ports = {\n+\t\t\t[0] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 1,\n+\t\t\t\t.name = \"LAN4\",\n+\t\t\t},\n+\t\t\t[1] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 2,\n+\t\t\t\t.name = \"LAN3\",\n+\t\t\t},\n+\t\t\t[2] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 3,\n+\t\t\t\t.name = \"LAN2\",\n+\t\t\t},\n+\t\t\t[3] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 4,\n+\t\t\t\t.name = \"LAN1\",\n+\t\t\t},\n+\t\t},\n+\t},\n+\n+\t.use_fallback_sprom = 1,\n+\t.fallback_sprom = {\n+\t\t.type = SPROM_BCM43222,\n+\t\t.pci_bus = 0,\n+\t\t.pci_dev = 1,\n+\t\t.board_fixups = vh4032n_fixups,\n+\t\t.num_board_fixups = ARRAY_SIZE(vh4032n_fixups),\n+\t},\n+};\n+\n+static struct sprom_fixup __initdata vr3025u_fixups[] = {\n+\t{ .offset = 97, .value = 0xfeb3 },\n+\t{ .offset = 98, .value = 0x1618 },\n+\t{ .offset = 99, .value = 0xfab0 },\n+\t{ .offset = 113, .value = 0xfed1 },\n+\t{ .offset = 114, .value = 0x1609 },\n+\t{ .offset = 115, .value = 0xfad9 },\n+};\n+\n+static struct board_info __initdata board_VR3025u = {\n+\t.name = \"96368M-1541N\",\n+\t.expected_cpu_id = 0x6368,\n+\n+\t.has_pci = 1,\n+\t.has_ohci0 = 1,\n+\t.has_ehci0 = 1,\n+\n+\t.has_enetsw = 1,\n+\t.enetsw = {\n+\t\t.used_ports = {\n+\t\t\t[0] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 1,\n+\t\t\t\t.name = \"port1\",\n+\t\t\t},\n+\t\t\t[1] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 2,\n+\t\t\t\t.name = \"port2\",\n+\t\t\t},\n+\t\t\t[2] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 3,\n+\t\t\t\t.name = \"port3\",\n+\t\t\t},\n+\t\t\t[3] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 4,\n+\t\t\t\t.name = \"port4\",\n+\t\t\t},\n+\t\t},\n+\t},\n+\n+\t.use_fallback_sprom = 1,\n+\t.fallback_sprom = {\n+\t\t.type = SPROM_BCM43222,\n+\t\t.pci_bus = 0,\n+\t\t.pci_dev = 1,\n+\t\t.board_fixups = vr3025u_fixups,\n+\t\t.num_board_fixups = ARRAY_SIZE(vr3025u_fixups),\n+\t},\n+};\n+\n+static struct sprom_fixup __initdata vr3025un_fixups[] = {\n+\t{ .offset = 97, .value = 0xfeb3 },\n+\t{ .offset = 98, .value = 0x1618 },\n+\t{ .offset = 99, .value = 0xfab0 },\n+\t{ .offset = 113, .value = 0xfed1 },\n+\t{ .offset = 114, .value = 0x1609 },\n+\t{ .offset = 115, .value = 0xfad9 },\n+};\n+\n+static struct board_info __initdata board_VR3025un = {\n+\t.name = \"96368M-1341N\",\n+\t.expected_cpu_id = 0x6368,\n+\n+\t.has_pci = 1,\n+\t.has_ohci0 = 1,\n+\t.has_ehci0 = 1,\n+\n+\t.has_enetsw = 1,\n+\t.enetsw = {\n+\t\t.used_ports = {\n+\t\t\t[0] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 1,\n+\t\t\t\t.name = \"port1\",\n+\t\t\t},\n+\t\t\t[1] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 2,\n+\t\t\t\t.name = \"port2\",\n+\t\t\t},\n+\t\t\t[2] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 3,\n+\t\t\t\t.name = \"port3\",\n+\t\t\t},\n+\t\t\t[3] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 4,\n+\t\t\t\t.name = \"port4\",\n+\t\t\t},\n+\t\t},\n+\t},\n+\n+\t.use_fallback_sprom = 1,\n+\t.fallback_sprom = {\n+\t\t.type = SPROM_BCM43222,\n+\t\t.pci_bus = 0,\n+\t\t.pci_dev = 1,\n+\t\t.board_fixups = vr3025un_fixups,\n+\t\t.num_board_fixups = ARRAY_SIZE(vr3025un_fixups),\n+\t},\n+};\n+\n+static struct sprom_fixup __initdata vr3026e_fixups[] = {\n+\t{ .offset = 97, .value = 0xfeb3 },\n+\t{ .offset = 98, .value = 0x1618 },\n+\t{ .offset = 99, .value = 0xfab0 },\n+\t{ .offset = 113, .value = 0xfed1 },\n+\t{ .offset = 114, .value = 0x1609 },\n+\t{ .offset = 115, .value = 0xfad9 },\n+};\n+\n+static struct board_info __initdata board_VR3026e = {\n+\t.name = \"96368MT-1341N1\",\n+\t.expected_cpu_id = 0x6368,\n+\n+\t.has_pci = 1,\n+\t.has_ohci0 = 1,\n+\t.has_ehci0 = 1,\n+\n+\t.has_enetsw = 1,\n+\t.enetsw = {\n+\t\t.used_ports = {\n+\t\t\t[0] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 1,\n+\t\t\t\t.name = \"port1\",\n+\t\t\t},\n+\t\t\t[1] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 2,\n+\t\t\t\t.name = \"port2\",\n+\t\t\t},\n+\t\t\t[2] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 3,\n+\t\t\t\t.name = \"port3\",\n+\t\t\t},\n+\t\t\t[3] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 4,\n+\t\t\t\t.name = \"port4\",\n+\t\t\t},\n+\t\t},\n+\t},\n+\n+\t.use_fallback_sprom = 1,\n+\t.fallback_sprom = {\n+\t\t.type = SPROM_BCM43222,\n+\t\t.pci_bus = 0,\n+\t\t.pci_dev = 1,\n+\t\t.board_fixups = vr3026e_fixups,\n+\t\t.num_board_fixups = ARRAY_SIZE(vr3026e_fixups),\n+\t},\n+};\n+\n+static struct sprom_fixup __initdata wap5813n_fixups[] = {\n+\t{ .offset = 97, .value = 0xfeed },\n+\t{ .offset = 98, .value = 0x15d1 },\n+\t{ .offset = 99, .value = 0xfb0d },\n+\t{ .offset = 113, .value = 0xfef7 },\n+\t{ .offset = 114, .value = 0x15f7 },\n+\t{ .offset = 115, .value = 0xfb1a },\n+};\n+\n+static struct board_info __initdata board_WAP5813n = {\n+\t.name = \"96369R-1231N\",\n+\t.expected_cpu_id = 0x6368,\n+\n+\t.has_pci = 1,\n+\t.has_ohci0 = 1,\n+\t.has_ehci0 = 1,\n+\n+\t.has_enetsw = 1,\n+\t.enetsw = {\n+\t\t.used_ports = {\n+\t\t\t[4] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 0xff,\n+\t\t\t\t.bypass_link = 1,\n+\t\t\t\t.force_speed = 1000,\n+\t\t\t\t.force_duplex_full = 1,\n+\t\t\t\t.name = \"RGMII\",\n+\t\t\t},\n+\t\t},\n+\t},\n+\n+\t.use_fallback_sprom = 1,\n+\t.fallback_sprom = {\n+\t\t.type = SPROM_BCM43222,\n+\t\t.pci_bus = 0,\n+\t\t.pci_dev = 1,\n+\t\t.board_fixups = wap5813n_fixups,\n+\t\t.num_board_fixups = ARRAY_SIZE(wap5813n_fixups),\n+\t},\n+};\n+#endif /* CONFIG_BCM63XX_CPU_6368 */\n+\n+/*\n  * all boards\n  */\n static const struct board_info __initconst *bcm963xx_boards[] = {\n@@ -2141,6 +2785,22 @@ static const struct board_info __initcon\n \t&board_hg253s_v2,\n \t&board_nb6,\n #endif /* CONFIG_BCM63XX_CPU_6362 */\n+#ifdef CONFIG_BCM63XX_CPU_6368\n+\t&board_96368mvngr,\n+\t&board_96368mvwg,\n+\t&board_AV4202N,\n+\t&board_DGND3700v1_3800B,\n+\t&board_EVG2000,\n+\t&board_HG622,\n+\t&board_HG655b,\n+\t&board_P870HW51A_V2,\n+\t&board_R1000H,\n+\t&board_VH4032N,\n+\t&board_VR3025u,\n+\t&board_VR3025un,\n+\t&board_VR3026e,\n+\t&board_WAP5813n,\n+#endif /* CONFIG_BCM63XX_CPU_6368 */\n };\n \n static struct of_device_id const bcm963xx_boards_dt[] = {\n@@ -2242,6 +2902,20 @@ static struct of_device_id const bcm963x\n \t{ .compatible = \"sfr,neufbox-6-sercomm-r0\", .data = &board_nb6, },\n #endif /* CONFIG_BCM63XX_CPU_6362 */\n #ifdef CONFIG_BCM63XX_CPU_6368\n+\t{ .compatible = \"actiontec,r1000h\", .data = &board_R1000H, },\n+\t{ .compatible = \"adb,av4202n\", .data = &board_AV4202N, },\n+\t{ .compatible = \"brcm,bcm96368mvngr\", .data = &board_96368mvngr, },\n+\t{ .compatible = \"brcm,bcm96368mvwg\", .data = &board_96368mvwg, },\n+\t{ .compatible = \"comtrend,vr-3025u\", .data = &board_VR3025u, },\n+\t{ .compatible = \"comtrend,vr-3025un\", .data = &board_VR3025un, },\n+\t{ .compatible = \"comtrend,vr-3026e\", .data = &board_VR3026e, },\n+\t{ .compatible = \"comtrend,wap-5813n\", .data = &board_WAP5813n, },\n+\t{ .compatible = \"huawei,echolife-hg622\", .data = &board_HG622, },\n+\t{ .compatible = \"huawei,echolife-hg655b\", .data = &board_HG655b, },\n+\t{ .compatible = \"netgear,dgnd3700-v1\", .data = &board_DGND3700v1_3800B, },\n+\t{ .compatible = \"netgear,evg2000\", .data = &board_EVG2000, },\n+\t{ .compatible = \"observa,vh4032n\", .data = &board_VH4032N, },\n+\t{ .compatible = \"zyxel,p870hw-51a-v2\", .data = &board_P870HW51A_V2, },\n #endif /* CONFIG_BCM63XX_CPU_6368 */\n #ifdef CONFIG_BCM63XX_CPU_63268\n #endif /* CONFIG_BCM63XX_CPU_63268 */\n--- a/arch/mips/bcm63xx/boards/board_common.c\n+++ b/arch/mips/bcm63xx/boards/board_common.c\n@@ -81,12 +81,25 @@ void __init board_early_setup(const stru\n \t\tbcm63xx_pci_enabled = 1;\n \t\tif (BCMCPU_IS_6348())\n \t\t\tval |= GPIO_MODE_6348_G2_PCI;\n+\n+\t\tif (BCMCPU_IS_6368())\n+\t\t\tval |= GPIO_MODE_6368_PCI_REQ1 |\n+\t\t\t\tGPIO_MODE_6368_PCI_GNT1 |\n+\t\t\t\tGPIO_MODE_6368_PCI_INTB |\n+\t\t\t\tGPIO_MODE_6368_PCI_REQ0 |\n+\t\t\t\tGPIO_MODE_6368_PCI_GNT0;\n \t}\n #endif\n \n \tif (board.has_pccard) {\n \t\tif (BCMCPU_IS_6348())\n \t\t\tval |= GPIO_MODE_6348_G1_MII_PCCARD;\n+\n+\t\tif (BCMCPU_IS_6368())\n+\t\t\tval |= GPIO_MODE_6368_PCMCIA_CD1 |\n+\t\t\t\tGPIO_MODE_6368_PCMCIA_CD2 |\n+\t\t\t\tGPIO_MODE_6368_PCMCIA_VS1 |\n+\t\t\t\tGPIO_MODE_6368_PCMCIA_VS2;\n \t}\n \n \tif (board.has_enet0 && !board.enet0.use_internal_phy) {\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/519-board_bcm63268.patch",
    "content": "--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c\n+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c\n@@ -2697,6 +2697,273 @@ static struct board_info __initdata boar\n #endif /* CONFIG_BCM63XX_CPU_6368 */\n \n /*\n+ * known 63268/63269 boards\n+ */\n+#ifdef CONFIG_BCM63XX_CPU_63268\n+static struct board_info __initdata board_963268bu_p300 = {\n+\t.name = \"963268BU_P300\",\n+\t.expected_cpu_id = 0x63268,\n+\n+\t.has_ohci0 = 1,\n+\t.has_ehci0 = 1,\n+\t.num_usbh_ports = 1,\n+\n+\t.has_usbd = 1,\n+\t.usbd = {\n+\t\t.use_fullspeed = 0,\n+\t\t.port_no = 0,\n+\t},\n+\n+\t.has_enetsw = 1,\n+\t.enetsw = {\n+\t\t.used_ports = {\n+\t\t\t[0] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 17,\n+\t\t\t\t.name = \"FE1\",\n+\t\t\t},\n+\t\t\t[3] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 4,\n+\t\t\t\t.name = \"GbE2\",\n+\t\t\t},\n+\t\t\t[4] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 0,\n+\t\t\t\t.name = \"GbE3\",\n+\t\t\t\t.mii_override = 1,\n+\t\t\t\t.timing_sel = 1,\n+\t\t\t},\n+\t\t\t[5] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 1,\n+\t\t\t\t.name = \"GbE1\",\n+\t\t\t\t.mii_override = 1,\n+\t\t\t\t.timing_sel = 1,\n+\t\t\t},\n+\t\t\t[6] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 24,\n+\t\t\t\t.name = \"GbE4\",\n+\t\t\t\t.mii_override = 1,\n+\t\t\t\t.timing_sel = 1,\n+\t\t\t},\n+\t\t\t[7] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 25,\n+\t\t\t\t.name = \"GbE5\",\n+\t\t\t\t.mii_override = 1,\n+\t\t\t\t.timing_sel = 1,\n+\t\t\t},\n+\t\t},\n+\t},\n+};\n+\n+static struct board_info __initdata board_963269bhr = {\n+\t.name = \"963269BHR\",\n+\t.expected_cpu_id = 0x63268,\n+\n+\t.has_pci = 1,\n+\t.has_ohci0 = 1,\n+\t.has_ehci0 = 1,\n+\n+\t.has_enetsw = 1,\n+\t.enetsw = {\n+\t\t.used_ports = {\n+\t\t\t[0] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 1,\n+\t\t\t\t.name = \"port1\",\n+\t\t\t},\n+\t\t\t[1] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 2,\n+\t\t\t\t.name = \"port2\",\n+\t\t\t},\n+\t\t\t[2] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 3,\n+\t\t\t\t.name = \"port3\",\n+\t\t\t},\n+\t\t\t[3] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 4,\n+\t\t\t\t.name = \"port4\",\n+\t\t\t},\n+\t\t},\n+\t},\n+};\n+\n+static struct board_info __initdata board_BSKYB_63168 = {\n+\t.name = \"BSKYB_63168\",\n+\t.expected_cpu_id = 0x63268,\n+\n+\t.has_pci = 1,\n+\t.has_ohci0 = 1,\n+\t.has_ehci0 = 1,\n+\t.num_usbh_ports = 2,\n+\n+\t.has_enetsw = 1,\n+\t.enetsw = {\n+\t\t.used_ports = {\n+\t\t\t[0] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 1,\n+\t\t\t\t.name = \"Port 1\",\n+\t\t\t},\n+\t\t\t[1] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 2,\n+\t\t\t\t.name = \"Port 2\",\n+\t\t\t},\n+\t\t\t[2] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 3,\n+\t\t\t\t.name = \"Port 3\",\n+\t\t\t},\n+\t\t\t[3] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 4,\n+\t\t\t\t.name = \"Port 4\",\n+\t\t\t},\n+\t\t},\n+\t},\n+};\n+\n+static struct board_info __initdata board_H500s = {\n+\t.name = \"BXK00C-1.6\",\n+\t.expected_cpu_id = 0x63268,\n+\n+\t.has_ohci0 = 1,\n+\t.has_ehci0 = 1,\n+\t.num_usbh_ports = 1,\n+\n+\t.has_enetsw = 1,\n+\t.enetsw = {\n+\t\t.used_ports = {\n+\t\t\t[3] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 12,\n+\t\t\t\t.name = \"WAN\",\n+\t\t\t},\n+\t\t\t[4] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 0,\n+\t\t\t\t.bypass_link = 1,\n+\t\t\t\t.force_speed = 1000,\n+\t\t\t\t.force_duplex_full = 1,\n+\t\t\t\t.mii_override = 1,\n+\t\t\t\t.timing_sel = 1,\n+\t\t\t\t.name = \"RGMII\",\n+\t\t\t},\n+\t\t},\n+\t},\n+};\n+\n+static struct board_info __initdata board_VG8050 = {\n+\t.name = \"963169P-1861N5\",\n+\t.expected_cpu_id = 0x63268,\n+\n+\t.has_ohci0 = 1,\n+\t.has_ehci0 = 1,\n+\t.num_usbh_ports = 2,\n+\n+\t.has_enetsw = 1,\n+\t.enetsw = {\n+\t\t.used_ports = {\n+\t\t\t[6] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 0xff,\n+\t\t\t\t.bypass_link = 1,\n+\t\t\t\t.force_speed = 1000,\n+\t\t\t\t.force_duplex_full = 1,\n+\t\t\t\t.mii_override = 1,\n+\t\t\t\t.timing_sel = 1,\n+\t\t\t\t.name = \"RGMII\",\n+\t\t\t},\n+\t\t},\n+\t},\n+};\n+\n+static struct board_info __initdata board_VR3032u = {\n+\t.name = \"963168M-1841N1\",\n+\t.expected_cpu_id = 0x63268,\n+\n+\t.has_ohci0 = 1,\n+\t.has_ehci0 = 1,\n+\t.num_usbh_ports = 1,\n+\n+\t.has_enetsw = 1,\n+\t.enetsw = {\n+\t\t.used_ports = {\n+\t\t\t[0] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 1,\n+\t\t\t\t.name = \"LAN2\",\n+\t\t\t},\n+\t\t\t[1] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 2,\n+\t\t\t\t.name = \"LAN3\",\n+\t\t\t},\n+\t\t\t[2] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 3,\n+\t\t\t\t.name = \"LAN4\",\n+\t\t\t},\n+\t\t\t[3] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 4,\n+\t\t\t\t.name = \"LAN1\",\n+\t\t\t},\n+\t\t},\n+\t},\n+};\n+\n+static struct board_info __initdata board_vw6339gu = {\n+\t.name = \"VW6339GU\",\n+\t.expected_cpu_id = 0x63268,\n+\n+\t.has_ohci0 = 1,\n+\t.has_ehci0 = 1,\n+\t.num_usbh_ports = 1,\n+\n+\t.has_enetsw = 1,\n+\t.enetsw = {\n+\t\t.used_ports = {\n+\t\t\t[0] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 1,\n+\t\t\t\t.name = \"LAN2\",\n+\t\t\t},\n+\t\t\t[1] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 2,\n+\t\t\t\t.name = \"LAN3\",\n+\t\t\t},\n+\t\t\t[2] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 3,\n+\t\t\t\t.name = \"LAN4\",\n+\t\t\t},\n+\t\t\t[3] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 4,\n+\t\t\t\t.name = \"LAN1\",\n+\t\t\t},\n+\t\t\t[4] = {\n+\t\t\t\t.used = 1,\n+\t\t\t\t.phy_id = 7,\n+\t\t\t\t.name = \"WAN\",\n+\t\t\t\t.mii_override = 1,\n+\t\t\t\t.timing_sel = 1,\n+\t\t\t},\n+\t\t},\n+\t},\n+};\n+#endif /* CONFIG_BCM63XX_CPU_63268 */\n+\n+/*\n  * all boards\n  */\n static const struct board_info __initconst *bcm963xx_boards[] = {\n@@ -2801,6 +3068,15 @@ static const struct board_info __initcon\n \t&board_VR3026e,\n \t&board_WAP5813n,\n #endif /* CONFIG_BCM63XX_CPU_6368 */\n+#ifdef CONFIG_BCM63XX_CPU_63268\n+\t&board_963268bu_p300,\n+\t&board_963269bhr,\n+\t&board_BSKYB_63168,\n+\t&board_H500s,\n+\t&board_VG8050,\n+\t&board_VR3032u,\n+\t&board_vw6339gu,\n+#endif /* CONFIG_BCM63XX_CPU_63268 */\n };\n \n static struct of_device_id const bcm963xx_boards_dt[] = {\n@@ -2918,6 +3194,14 @@ static struct of_device_id const bcm963x\n \t{ .compatible = \"zyxel,p870hw-51a-v2\", .data = &board_P870HW51A_V2, },\n #endif /* CONFIG_BCM63XX_CPU_6368 */\n #ifdef CONFIG_BCM63XX_CPU_63268\n+\t{ .compatible = \"brcm,bcm963268bu-p300\", .data = &board_963268bu_p300, },\n+\t{ .compatible = \"brcm,bcm963269bhr\", .data = &board_963269bhr, },\n+\t{ .compatible = \"comtrend,vg-8050\", .data = &board_VG8050, },\n+\t{ .compatible = \"comtrend,vr-3032u\", .data = &board_VR3032u, },\n+\t{ .compatible = \"inteno,vg50\", .data = &board_vw6339gu, },\n+\t{ .compatible = \"sercomm,h500-s-lowi\", .data = &board_H500s, },\n+\t{ .compatible = \"sercomm,h500-s-vfes\", .data = &board_H500s, },\n+\t{ .compatible = \"sky,sr102\", .data = &board_BSKYB_63168, },\n #endif /* CONFIG_BCM63XX_CPU_63268 */\n #endif /* CONFIG_OF */\n \t{ },\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/531-board_bcm6348-bt-voyager-2500v-bb.patch",
    "content": "--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c\n+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c\n@@ -3230,6 +3230,22 @@ void __init board_bcm963xx_init(void)\n \t\tval &= MPI_CSBASE_BASE_MASK;\n \t}\n \tboot_addr = (u8 *)KSEG1ADDR(val);\n+\tpr_info(\"Boot address 0x%08x\\n\",(unsigned int)boot_addr);\n+\n+\t/* BT Voyager 2500V (RTA1046VW PCB) has 8 Meg flash used as two */\n+\t/* banks of 4 Meg. The byte at 0xBF800000 identifies the back to use.*/\n+\t/* Loading firmware from the CFE Prompt always loads to Bank 0 */\n+\t/* Do an early check of CFE and then select bank 0 */\n+\n+\tif (boot_addr == (u8 *)0xbf800000) {\n+\t\tu8 *tmp_boot_addr = (u8*)0xbfc00000;\n+\n+\t\tbcm63xx_nvram_init(tmp_boot_addr + BCM963XX_NVRAM_OFFSET);\n+\t\tif (!strcmp(bcm63xx_nvram_get_name(), \"V2500V_BB\")) {\n+\t\t\tpr_info(\"V2500V: nvram bank 0\\n\");\n+\t\t\tboot_addr = tmp_boot_addr;\n+\t\t}\n+\t}\n \n \t/* dump cfe version */\n \tcfe = boot_addr + BCM963XX_CFE_VERSION_OFFSET;\n--- a/arch/mips/bcm63xx/dev-flash.c\n+++ b/arch/mips/bcm63xx/dev-flash.c\n@@ -21,6 +21,7 @@\n #include <linux/spi/spi.h>\n #include <linux/spi/flash.h>\n \n+#include <bcm63xx_board.h>\n #include <bcm63xx_cpu.h>\n #include <bcm63xx_dev_flash.h>\n #include <bcm63xx_regs.h>\n@@ -256,6 +257,13 @@ int __init bcm63xx_flash_register(void)\n \t\t\tval = bcm_mpi_readl(MPI_CSBASE_REG(0));\n \t\t\tval &= MPI_CSBASE_BASE_MASK;\n \n+\t\t\t/* BT Voyager 2500V has 8 Meg flash in two 4 Meg banks */\n+\t\t\t/* Loading from CFE always uses Bank 0 */\n+\t\t\tif (!strcmp(board_get_name(), \"V2500V_BB\")) {\n+\t\t\t\tpr_info(\"V2500V: Start in Bank 0\\n\");\n+\t\t\t\tval = val + 0x400000; // Select Bank 0 start address\n+\t\t\t}\n+\n \t\t\tmtd_resources[0].start = val;\n \t\t\tmtd_resources[0].end = 0x1FFFFFFF;\n \t\t}\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/532-MIPS-BCM63XX-add-inventel-Livebox-support.patch",
    "content": "From e796582b499f0ba6acaa1ac3a10c09cceaab7702 Mon Sep 17 00:00:00 2001\nFrom: Jonas Gorski <jogo@openwrt.org>\nDate: Sun, 9 Mar 2014 04:55:52 +0100\nSubject: [PATCH] MIPS: BCM63XX: add inventel Livebox support\n\n---\n arch/mips/bcm63xx/boards/Kconfig         |    6 +\n arch/mips/bcm63xx/boards/Makefile        |    1 +\n arch/mips/bcm63xx/boards/board_common.c  |    2 +-\n arch/mips/bcm63xx/boards/board_common.h  |    6 +\n arch/mips/bcm63xx/boards/board_livebox.c |  215 ++++++++++++++++++++++++++++++\n 5 files changed, 229 insertions(+), 1 deletion(-)\n create mode 100644 arch/mips/bcm63xx/boards/board_livebox.c\n\n--- a/arch/mips/bcm63xx/boards/Kconfig\n+++ b/arch/mips/bcm63xx/boards/Kconfig\n@@ -12,4 +12,10 @@ config BOARD_BCM963XX\n \tselect BCMA\n \tdefault y\n \n+config BOARD_LIVEBOX\n+\tbool \"Inventel Livebox(es) boards\"\n+\tselect SSB\n+\thelp\n+\t  Inventel Livebox boards using the RedBoot bootloader.\n+\n endmenu\n--- a/arch/mips/bcm63xx/boards/Makefile\n+++ b/arch/mips/bcm63xx/boards/Makefile\n@@ -1,3 +1,4 @@\n # SPDX-License-Identifier: GPL-2.0-only\n obj-y\t\t\t\t\t+= board_common.o\n obj-$(CONFIG_BOARD_BCM963XX)\t\t+= board_bcm963xx.o\n+obj-$(CONFIG_BOARD_LIVEBOX)\t\t+= board_livebox.o\n--- a/arch/mips/bcm63xx/boards/board_common.c\n+++ b/arch/mips/bcm63xx/boards/board_common.c\n@@ -54,7 +54,7 @@ void __init board_prom_init(void)\n \tif (fw_arg3 == CFE_EPTSEAL)\n \t\tboard_bcm963xx_init();\n \telse\n-\t\tpanic(\"unsupported bootloader detected\");\n+\t\tboard_livebox_init();\n }\n \n static int (*board_get_mac_address)(u8 mac[ETH_ALEN]);\n--- a/arch/mips/bcm63xx/boards/board_common.h\n+++ b/arch/mips/bcm63xx/boards/board_common.h\n@@ -24,4 +24,10 @@ static inline void board_of_device_prese\n }\n #endif\n \n+#if defined(CONFIG_BOARD_LIVEBOX)\n+void board_livebox_init(void);\n+#else\n+static inline void board_livebox_init(void) { }\n+#endif\n+\n #endif /* __BOARD_COMMON_H */\n--- /dev/null\n+++ b/arch/mips/bcm63xx/boards/board_livebox.c\n@@ -0,0 +1,158 @@\n+/*\n+ * This file is subject to the terms and conditions of the GNU General Public\n+ * License. See the file \"COPYING\" in the main directory of this archive\n+ * for more details.\n+ *\n+ * Copyright (C) 2008 Florian Fainelli <florian@openwrt.org>\n+ */\n+\n+#include <linux/init.h>\n+#include <linux/kernel.h>\n+#include <linux/string.h>\n+#include <linux/input.h>\n+#include <asm/addrspace.h>\n+#include <bcm63xx_board.h>\n+#include <bcm63xx_cpu.h>\n+#include <bcm63xx_regs.h>\n+#include <bcm63xx_io.h>\n+#include <bcm63xx_dev_flash.h>\n+#include <board_bcm963xx.h>\n+\n+#include \"board_common.h\"\n+\n+#define PFX\t\"board_livebox: \"\n+\n+static unsigned int mac_addr_used = 0;\n+\n+/*\n+ * known 6348 boards\n+ */\n+#ifdef CONFIG_BCM63XX_CPU_6348\n+static struct board_info __initdata board_livebox_blue5g = {\n+\t.name = \"Livebox-blue-5g\",\n+\t.expected_cpu_id = 0x6348,\n+\n+\t.has_pccard = 1,\n+\t.has_pci = 1,\n+\t.has_ohci0 = 1,\n+\t.ephy_reset_gpio = 6,\n+\t.ephy_reset_gpio_flags = GPIO_ACTIVE_LOW,\n+\n+\t.has_enet0 = 1,\n+\t.enet0 = {\n+\t\t.has_phy = 1,\n+\t\t.use_internal_phy = 1,\n+\t},\n+\n+\t.has_enet1 = 1,\n+\t.enet1 = {\n+\t\t.has_phy = 1,\n+\t\t.phy_id = 31,\n+\t},\n+};\n+#endif\n+\n+/*\n+ * all boards\n+ */\n+static const struct board_info __initdata *bcm963xx_boards[] = {\n+#ifdef CONFIG_BCM63XX_CPU_6348\n+\t&board_livebox_blue5g\n+#endif /* CONFIG_BCM63XX_CPU_6348 */\n+};\n+\n+static struct of_device_id const livebox_boards_dt[] = {\n+\t{ .compatible = \"inventel,livebox-1\", .data = &board_livebox_blue5g, },\n+\t{ }\n+};\n+\n+/*\n+ * register & return a new board mac address\n+ */\n+static int livebox_get_mac_address(u8 mac[ETH_ALEN])\n+{\n+\tu8 *p;\n+\tint count;\n+\tvoid __iomem *volatile mmio;\n+\n+\tmmio = ioremap(0x1ebff377, 0x8);\n+\tif (!mmio)\n+\t\treturn -EIO;\n+\tmemcpy_fromio(mac, mmio, ETH_ALEN);\n+\tiounmap(mmio);\n+\n+\tp = mac + ETH_ALEN - 1;\n+\tcount = mac_addr_used;\n+\n+\twhile (count--) {\n+\t\tdo {\n+\t\t\t(*p)++;\n+\t\t\tif (*p != 0)\n+\t\t\t\tbreak;\n+\t\t\tp--;\n+\t\t} while (p != mac);\n+\t}\n+\n+\tif (p == mac) {\n+\t\tprintk(KERN_ERR PFX \"unable to fetch mac address\\n\");\n+\t\treturn -ENODEV;\n+\t}\n+\tmac_addr_used++;\n+\n+\treturn 0;\n+}\n+\n+/*\n+ * early init callback\n+ */\n+#define LIVEBOX_GPIO_DETECT_MASK\t0x000000ff\n+#define LIVEBOX_BOOT_ADDR\t\t0x1e400000\n+\n+#define LIVEBOX_HW_BLUE5G_9\t\t0x90\n+\n+void __init board_livebox_init(void)\n+{\n+\tu32 val;\n+\tu8 hw_version;\n+\tconst struct board_info *board;\n+\tconst struct of_device_id *board_match;\n+\n+\t/* find board by compat */\n+\tboard_match = bcm63xx_match_board(livebox_boards_dt);\n+\tif (board_match) {\n+\t\tboard = board_match->data;\n+\t} else {\n+\t\t/* Get hardware version */\n+\t\tval = bcm_gpio_readl(GPIO_CTL_LO_REG);\n+\t\tval &= ~LIVEBOX_GPIO_DETECT_MASK;\n+\t\tbcm_gpio_writel(val, GPIO_CTL_LO_REG);\n+\n+\t\thw_version = bcm_gpio_readl(GPIO_DATA_LO_REG);\n+\t\thw_version &= LIVEBOX_GPIO_DETECT_MASK;\n+\n+\t\tswitch (hw_version) {\n+\t\tcase LIVEBOX_HW_BLUE5G_9:\n+\t\t\tprintk(KERN_INFO PFX \"Livebox BLUE5G.9\\n\");\n+\t\t\tboard = bcm963xx_boards[0];\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tprintk(KERN_INFO PFX \"Unknown livebox version: %02x\\n\",\n+\t\t\t       hw_version);\n+\t\t\t/* use default livebox configuration */\n+\t\t\tboard = bcm963xx_boards[0];\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\n+\t/* use default livebox configuration */\n+\tboard_early_setup(board, livebox_get_mac_address);\n+\n+\t/* read base address of boot chip select (0) */\n+\tval = bcm_mpi_readl(MPI_CSBASE_REG(0));\n+\tval &= MPI_CSBASE_BASE_MASK;\n+\tif (val != LIVEBOX_BOOT_ADDR) {\n+\t\tprintk(KERN_NOTICE PFX \"flash address is: 0x%08x, forcing to: 0x%08x\\n\",\n+\t\t\tval, LIVEBOX_BOOT_ADDR);\n+\t\tbcm63xx_flash_force_phys_base_address(LIVEBOX_BOOT_ADDR, 0x1ebfffff);\n+\t}\n+}\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/800-wl_exports.patch",
    "content": "--- a/arch/mips/bcm63xx/nvram.c\n+++ b/arch/mips/bcm63xx/nvram.c\n@@ -24,6 +24,12 @@\n static struct bcm963xx_nvram nvram;\n static int mac_addr_used;\n \n+/*\n+ * Required export for WL\n+ */\n+u32 nvram_buf[5] = { 0, cpu_to_le32(20), 0, 0, 0 };\n+EXPORT_SYMBOL(nvram_buf);\n+\n void __init bcm63xx_nvram_init(void *addr)\n {\n \tu32 crc, expected_crc;\n--- a/arch/mips/mm/cache.c\n+++ b/arch/mips/mm/cache.c\n@@ -61,6 +61,9 @@ void (*_dma_cache_wback_inv)(unsigned lo\n void (*_dma_cache_wback)(unsigned long start, unsigned long size);\n void (*_dma_cache_inv)(unsigned long start, unsigned long size);\n \n+EXPORT_SYMBOL(_dma_cache_wback_inv);\n+EXPORT_SYMBOL(_dma_cache_inv);\n+\n #endif /* CONFIG_DMA_NONCOHERENT */\n \n /*\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/801-ssb_export_fallback_sprom.patch",
    "content": "--- a/arch/mips/bcm63xx/sprom.c\n+++ b/arch/mips/bcm63xx/sprom.c\n@@ -8,6 +8,7 @@\n  */\n \n #include <linux/init.h>\n+#include <linux/export.h>\n #include <linux/kernel.h>\n #include <linux/string.h>\n #include <linux/platform_device.h>\n@@ -388,7 +389,19 @@ struct fallback_sprom_match {\n \tstruct ssb_sprom sprom;\n };\n \n-static struct fallback_sprom_match fallback_sprom;\n+struct fallback_sprom_match fallback_sprom;\n+\n+int bcm63xx_get_fallback_sprom(uint pci_bus, uint pci_slot, struct ssb_sprom *out)\n+{\n+\tif (pci_bus != fallback_sprom.pci_bus ||\n+\t    pci_slot != fallback_sprom.pci_dev)\n+\t\tpr_warn(\"fallback_sprom: pci bus/device num mismatch: expected %i/%i, but got %i/%i\\n\",\n+\t\t\tfallback_sprom.pci_bus, fallback_sprom.pci_dev,\n+\t\t\tpci_bus, pci_slot);\n+\tmemcpy(out, &fallback_sprom.sprom, sizeof(struct ssb_sprom));\n+\treturn 0;\n+}\n+EXPORT_SYMBOL(bcm63xx_get_fallback_sprom);\n \n #if defined(CONFIG_SSB_PCIHOST)\n int bcm63xx_get_fallback_ssb_sprom(struct ssb_bus *bus, struct ssb_sprom *out)\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/802-rtl8367r_fix_RGMII_support.patch",
    "content": "From e3208e6087642b95a5bab3101fc9c6e34892c861 Mon Sep 17 00:00:00 2001\nFrom: Miguel GAIO <miguel.gaio@efixo.com>\nDate: Fri, 6 Jul 2012 14:12:33 +0200\nSubject: [PATCH 6/8] * [rtl8367r] Fix RGMII support\n\n---\n drivers/net/phy/rtl8367.c  |    5 +++++\n 1 files changed, 5 insertions(+), 0 deletions(-)\n\n--- a/drivers/net/phy/rtl8367.c\n+++ b/drivers/net/phy/rtl8367.c\n@@ -146,6 +146,10 @@\n #define   RTL8367_EXT_RGMXF_TXDELAY_MASK\t1\n #define   RTL8367_EXT_RGMXF_RXDELAY_MASK\t0x7\n \n+#define RTL8367_PHY_AD_REG\t\t\t0x130f\n+#define    RTL8370_PHY_AD_DUMMY_1_OFFSET\t5\n+#define    RTL8370_PHY_AD_DUMMY_1_MASK\t\t0xe0\n+\n #define RTL8367_DI_FORCE_REG(_x)\t\t(0x1310 + (_x))\n #define   RTL8367_DI_FORCE_MODE\t\t\tBIT(12)\n #define   RTL8367_DI_FORCE_NWAY\t\t\tBIT(7)\n@@ -897,6 +901,7 @@ static int rtl8367_extif_set_mode(struct\n \tcase RTL8367_EXTIF_MODE_RGMII_33V:\n \t\tREG_WR(smi, RTL8367_CHIP_DEBUG0_REG, 0x0367);\n \t\tREG_WR(smi, RTL8367_CHIP_DEBUG1_REG, 0x7777);\n+\t\tREG_RMW(smi, RTL8367_PHY_AD_REG, BIT(5), 0);\n \t\tbreak;\n \n \tcase RTL8367_EXTIF_MODE_TMII_MAC:\n"
  },
  {
    "path": "target/linux/bcm63xx/patches-5.10/803-jffs2-work-around-unaligned-accesses-failing-on-bcm6.patch",
    "content": "From ff3409ab17d56450943364ba49a16960e3cdda9b Mon Sep 17 00:00:00 2001\nFrom: Jonas Gorski <jogo@openwrt.org>\nDate: Sun, 6 Apr 2014 22:33:16 +0200\nSubject: [RFC] jffs2: work around unaligned accesses failing on bcm63xx/smp\n\nUnligned memcpy_fromio randomly fails with an unaligned dst. Work around\nit by ensuring we are always doing aligned copies.\n\nShould fix filename corruption in jffs2 with SMP.\n\nSigned-off-by: Jonas Gorski <jogo@openwrt.org>\n---\n fs/jffs2/nodelist.h | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/fs/jffs2/nodelist.h\n+++ b/fs/jffs2/nodelist.h\n@@ -259,7 +259,7 @@ struct jffs2_full_dirent\n \tuint32_t ino; /* == zero for unlink */\n \tunsigned int nhash;\n \tunsigned char type;\n-\tunsigned char name[];\n+\tunsigned char name[] __attribute__((aligned((sizeof(long)))));\n };\n \n /*\n"
  },
  {
    "path": "target/linux/bcm63xx/profiles/default.mk",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2016 LEDE project\n\ndefine Profile/Default\n  NAME:=Default Profile\n  PACKAGES:=kmod-b43 wpad-basic-wolfssl\n  PRIORITY:=1\nendef\n\ndefine Profile/Default/Description\n  Package set compatible with most boards.\nendef\n\n$(eval $(call Profile,Default))\n"
  },
  {
    "path": "target/linux/bcm63xx/smp/config-default",
    "content": "CONFIG_CPU_RMAP=y\nCONFIG_CRC16=y\nCONFIG_CRYPTO_ACOMP2=y\nCONFIG_CRYPTO_AEAD=y\nCONFIG_CRYPTO_AEAD2=y\nCONFIG_CRYPTO_DEFLATE=y\nCONFIG_CRYPTO_HASH_INFO=y\nCONFIG_CRYPTO_HASH2=y\nCONFIG_CRYPTO_LZO=y\nCONFIG_CRYPTO_MANAGER=y\nCONFIG_CRYPTO_MANAGER2=y\nCONFIG_CRYPTO_NULL2=y\nCONFIG_CRYPTO_ZSTD=y\nCONFIG_JFFS2_FS_NAND=y\nCONFIG_LZO_COMPRESS=y\nCONFIG_LZO_DECOMPRESS=y\nCONFIG_MTD_NAND_BRCMNAND=y\nCONFIG_MTD_NAND_CORE=y\nCONFIG_MTD_NAND_ECC_SW_HAMMING=y\nCONFIG_MTD_RAW_NAND=y\nCONFIG_MTD_SPLIT_BCM_WFI_FW=y\nCONFIG_MTD_UBI=y\nCONFIG_MTD_UBI_BEB_LIMIT=20\nCONFIG_MTD_UBI_BLOCK=y\nCONFIG_MTD_UBI_WL_THRESHOLD=4096\nCONFIG_NET_FLOW_LIMIT=y\nCONFIG_NR_CPUS=2\nCONFIG_PADATA=y\nCONFIG_RFS_ACCEL=y\nCONFIG_RPS=y\nCONFIG_SGL_ALLOC=y\nCONFIG_SMP=y\nCONFIG_SMP_UP=y\nCONFIG_TREE_RCU=y\nCONFIG_UBIFS_FS=y\nCONFIG_XPS=y\nCONFIG_XXHASH=y\nCONFIG_ZLIB_DEFLATE=y\nCONFIG_ZLIB_INFLATE=y\nCONFIG_ZSTD_COMPRESS=y\nCONFIG_ZSTD_DECOMPRESS=y\n"
  },
  {
    "path": "target/linux/bcm63xx/smp/target.mk",
    "content": "BOARDNAME:=smp\nFEATURES+=nand\n\ndefine Target/Description\n  Build firmware images for BCM63XX boards with SMP and NAND support.\n  SoCs with 2 cores:\n    - BCM6328 (some boards only have 1 core)\n    - BCM6358 (SMP unsupported due to shared TLB)\n    - BCM6362\n    - BCM6368\n    - BCM63268\n  SoCs with NAND controller:\n    - BCM6328 (v2.2)\n    - BCM6362 (v2.2)\n    - BCM6368 (v2.1)\n    - BCM63268 (v4.0)\nendef\n"
  },
  {
    "path": "target/linux/bmips/Makefile",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\ninclude $(TOPDIR)/rules.mk\n\nARCH:=mips\nCPU_TYPE:=mips32\nBOARD:=bmips\nBOARDNAME:=Broadcom BMIPS\nSUBTARGETS:=generic nand\nFEATURES:=gpio source-only squashfs usb\n\nKERNEL_PATCHVER:=5.10\n\ndefine Target/Description\n\tBuild firmware images for BCM33xx cable modem chips,\n\tBCM63xx DSL chips and BCM7xxx set-top box chips.\nendef\n\ninclude $(INCLUDE_DIR)/target.mk\n\nDEFAULT_PACKAGES += ethtool kmod-gpio-button-hotplug\n\n$(eval $(call BuildTarget))\n"
  },
  {
    "path": "target/linux/bmips/config-5.10",
    "content": "CONFIG_ARCH_32BIT_OFF_T=y\nCONFIG_ARCH_HIBERNATION_POSSIBLE=y\nCONFIG_ARCH_MMAP_RND_BITS_MAX=15\nCONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15\nCONFIG_ARCH_SUSPEND_POSSIBLE=y\nCONFIG_B53=y\nCONFIG_B53_MDIO_DRIVER=y\nCONFIG_B53_MMAP_DRIVER=y\nCONFIG_B53_SPI_DRIVER=y\nCONFIG_BCM6345_EXT_IRQ=y\nCONFIG_BCM6345_L1_IRQ=y\nCONFIG_BCM6368_ENETSW=y\nCONFIG_BCM63XX_POWER=y\nCONFIG_BCM7038_L1_IRQ=y\nCONFIG_BCM7038_WDT=y\nCONFIG_BCM7120_L2_IRQ=y\nCONFIG_BCMA=y\nCONFIG_BCMA_BLOCKIO=y\n# CONFIG_BCMA_DEBUG is not set\n# CONFIG_BCMA_DRIVER_GMAC_CMN is not set\n# CONFIG_BCMA_DRIVER_MIPS is not set\nCONFIG_BCMA_DRIVER_PCI=y\n# CONFIG_BCMA_DRIVER_PCI_HOSTMODE is not set\nCONFIG_BCMA_HOST_PCI=y\nCONFIG_BCMA_HOST_PCI_POSSIBLE=y\n# CONFIG_BCMA_HOST_SOC is not set\nCONFIG_BLK_MQ_PCI=y\nCONFIG_BLK_PM=y\nCONFIG_BMIPS_GENERIC=y\nCONFIG_BOARD_SCACHE=y\nCONFIG_BRCMSTB_L2_IRQ=y\nCONFIG_CEVT_R4K=y\nCONFIG_CLKDEV_LOOKUP=y\nCONFIG_CLK_BCM63268_TIMER=y\nCONFIG_CLK_BCM_63XX_GATE=y\nCONFIG_CLONE_BACKWARDS=y\nCONFIG_COMMON_CLK=y\n# CONFIG_COMMON_CLK_BOSTON is not set\nCONFIG_COMPAT_32BIT_TIME=y\nCONFIG_CPU_BIG_ENDIAN=y\nCONFIG_CPU_BMIPS=y\nCONFIG_CPU_BMIPS32_3300=y\nCONFIG_CPU_BMIPS4350=y\nCONFIG_CPU_BMIPS4380=y\nCONFIG_CPU_BMIPS5000=y\nCONFIG_CPU_GENERIC_DUMP_TLB=y\nCONFIG_CPU_HAS_PREFETCH=y\nCONFIG_CPU_HAS_RIXI=y\nCONFIG_CPU_HAS_SYNC=y\n# CONFIG_CPU_LITTLE_ENDIAN is not set\nCONFIG_CPU_MIPS32=y\nCONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y\nCONFIG_CPU_NO_EFFICIENT_FFS=y\nCONFIG_CPU_R4K_CACHE_TLB=y\nCONFIG_CPU_RMAP=y\nCONFIG_CPU_SUPPORTS_32BIT_KERNEL=y\nCONFIG_CPU_SUPPORTS_CPUFREQ=y\nCONFIG_CPU_SUPPORTS_HIGHMEM=y\nCONFIG_CRASH_DUMP=y\nCONFIG_CRC16=y\nCONFIG_CRYPTO_ACOMP2=y\nCONFIG_CRYPTO_DEFLATE=y\nCONFIG_CRYPTO_LIB_POLY1305_RSIZE=2\nCONFIG_CRYPTO_LZO=y\nCONFIG_CRYPTO_RNG2=y\nCONFIG_CRYPTO_ZSTD=y\nCONFIG_CSRC_R4K=y\nCONFIG_DEBUG_INFO=y\nCONFIG_DMA_NONCOHERENT=y\nCONFIG_DTC=y\n# CONFIG_DT_BCM93384WVG is not set\n# CONFIG_DT_BCM93384WVG_VIPER is not set\n# CONFIG_DT_BCM96368MVWG is not set\n# CONFIG_DT_BCM97125CBMB is not set\n# CONFIG_DT_BCM97346DBSMB is not set\n# CONFIG_DT_BCM97358SVMB is not set\n# CONFIG_DT_BCM97360SVMB is not set\n# CONFIG_DT_BCM97362SVMB is not set\n# CONFIG_DT_BCM97420C is not set\n# CONFIG_DT_BCM97425SVMB is not set\n# CONFIG_DT_BCM97435SVMB is not set\n# CONFIG_DT_BCM9EJTAGPRB is not set\n# CONFIG_DT_COMTREND_VR3032U is not set\n# CONFIG_DT_NETGEAR_CVG834G is not set\nCONFIG_DT_NONE=y\n# CONFIG_DT_SFR_NEUFBOX4_SERCOMM is not set\n# CONFIG_DT_SFR_NEUFBOX6_SERCOMM is not set\nCONFIG_FIXED_PHY=y\nCONFIG_FW_LOADER_PAGED_BUF=y\nCONFIG_GENERIC_ATOMIC64=y\nCONFIG_GENERIC_CLOCKEVENTS=y\nCONFIG_GENERIC_CMOS_UPDATE=y\nCONFIG_GENERIC_CPU_AUTOPROBE=y\nCONFIG_GENERIC_GETTIMEOFDAY=y\nCONFIG_GENERIC_IOMAP=y\nCONFIG_GENERIC_IRQ_CHIP=y\nCONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y\nCONFIG_GENERIC_IRQ_SHOW=y\nCONFIG_GENERIC_LIB_ASHLDI3=y\nCONFIG_GENERIC_LIB_ASHRDI3=y\nCONFIG_GENERIC_LIB_CMPDI2=y\nCONFIG_GENERIC_LIB_LSHRDI3=y\nCONFIG_GENERIC_LIB_UCMPDI2=y\nCONFIG_GENERIC_PCI_IOMAP=y\nCONFIG_GENERIC_PHY=y\nCONFIG_GENERIC_PINCONF=y\nCONFIG_GENERIC_PINCTRL_GROUPS=y\nCONFIG_GENERIC_PINMUX_FUNCTIONS=y\nCONFIG_GENERIC_SCHED_CLOCK=y\nCONFIG_GENERIC_SMP_IDLE_THREAD=y\nCONFIG_GENERIC_TIME_VSYSCALL=y\nCONFIG_GPIOLIB=y\n# CONFIG_GPIO_BRCMSTB is not set\nCONFIG_GPIO_GENERIC=y\nCONFIG_GPIO_GENERIC_PLATFORM=y\nCONFIG_GRO_CELLS=y\nCONFIG_HANDLE_DOMAIN_IRQ=y\nCONFIG_HARDIRQS_SW_RESEND=y\nCONFIG_HAS_DMA=y\nCONFIG_HAS_IOMEM=y\nCONFIG_HAS_IOPORT_MAP=y\nCONFIG_HW_RANDOM=y\nCONFIG_HW_RANDOM_BCM2835=y\nCONFIG_HZ_PERIODIC=y\nCONFIG_INITRAMFS_SOURCE=\"\"\nCONFIG_IRQCHIP=y\nCONFIG_IRQ_DOMAIN=y\nCONFIG_IRQ_FORCED_THREADING=y\nCONFIG_IRQ_MIPS_CPU=y\nCONFIG_IRQ_WORK=y\nCONFIG_LEDS_BCM6328=y\nCONFIG_LEDS_BCM6358=y\nCONFIG_LEDS_GPIO=y\nCONFIG_LIBFDT=y\nCONFIG_LOCK_DEBUGGING_SUPPORT=y\nCONFIG_LZO_COMPRESS=y\nCONFIG_LZO_DECOMPRESS=y\nCONFIG_MDIO_BUS=y\nCONFIG_MDIO_BUS_MUX=y\nCONFIG_MDIO_BUS_MUX_BCM6368=y\nCONFIG_MDIO_DEVICE=y\nCONFIG_MDIO_DEVRES=y\nCONFIG_MEMFD_CREATE=y\nCONFIG_MFD_SYSCON=y\nCONFIG_MIGRATION=y\nCONFIG_MIPS=y\nCONFIG_MIPS_ASID_BITS=8\nCONFIG_MIPS_ASID_SHIFT=0\nCONFIG_MIPS_CBPF_JIT=y\nCONFIG_MIPS_CLOCK_VSYSCALL=y\n# CONFIG_MIPS_CMDLINE_DTB_EXTEND is not set\n# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set\nCONFIG_MIPS_CMDLINE_FROM_DTB=y\nCONFIG_MIPS_CPU_SCACHE=y\n# CONFIG_MIPS_ELF_APPENDED_DTB is not set\nCONFIG_MIPS_EXTERNAL_TIMER=y\nCONFIG_MIPS_L1_CACHE_SHIFT=7\nCONFIG_MIPS_L1_CACHE_SHIFT_6=y\nCONFIG_MIPS_L1_CACHE_SHIFT_7=y\nCONFIG_MIPS_LD_CAN_LINK_VDSO=y\n# CONFIG_MIPS_NO_APPENDED_DTB is not set\nCONFIG_MIPS_NR_CPU_NR_MAP=2\nCONFIG_MIPS_O32_FP64_SUPPORT=y\nCONFIG_MIPS_RAW_APPENDED_DTB=y\nCONFIG_MODULES_USE_ELF_REL=y\nCONFIG_MODULE_FORCE_LOAD=y\nCONFIG_MODULE_FORCE_UNLOAD=y\n# CONFIG_MTD_BCM63XX_PARTS is not set\nCONFIG_MTD_CFI_ADV_OPTIONS=y\nCONFIG_MTD_CFI_BE_BYTE_SWAP=y\n# CONFIG_MTD_CFI_GEOMETRY is not set\n# CONFIG_MTD_CFI_NOSWAP is not set\nCONFIG_MTD_CFI_STAA=y\nCONFIG_MTD_JEDECPROBE=y\n# CONFIG_MTD_PARSER_IMAGETAG is not set\nCONFIG_NEED_DMA_MAP_STATE=y\nCONFIG_NET_DEVLINK=y\nCONFIG_NET_DSA=y\nCONFIG_NET_DSA_TAG_BRCM=y\nCONFIG_NET_DSA_TAG_BRCM_COMMON=y\nCONFIG_NET_DSA_TAG_BRCM_LEGACY=y\nCONFIG_NET_DSA_TAG_BRCM_PREPEND=y\nCONFIG_NET_FLOW_LIMIT=y\nCONFIG_NET_SWITCHDEV=y\nCONFIG_NO_EXCEPT_FILL=y\nCONFIG_NO_GENERIC_PCI_IOPORT_MAP=y\nCONFIG_NR_CPUS=2\nCONFIG_NVMEM=y\nCONFIG_OF=y\nCONFIG_OF_ADDRESS=y\nCONFIG_OF_EARLY_FLATTREE=y\nCONFIG_OF_FLATTREE=y\nCONFIG_OF_GPIO=y\nCONFIG_OF_IRQ=y\nCONFIG_OF_KOBJ=y\nCONFIG_OF_MDIO=y\nCONFIG_OF_NET=y\nCONFIG_PADATA=y\nCONFIG_PCI=y\nCONFIG_PCIEPORTBUS=y\nCONFIG_PCIE_BCM6318=y\nCONFIG_PCIE_BCM6328=y\nCONFIG_PCIE_PME=y\nCONFIG_PCI_BCM6348=y\nCONFIG_PCI_DOMAINS=y\nCONFIG_PCI_DRIVERS_LEGACY=y\nCONFIG_PERF_USE_VMALLOC=y\nCONFIG_PGTABLE_LEVELS=2\nCONFIG_PHYLIB=y\nCONFIG_PHYLINK=y\nCONFIG_PHYSICAL_START=0x80010000\nCONFIG_PHY_BCM63XX_USBH=y\n# CONFIG_PHY_BRCM_SATA is not set\nCONFIG_PINCTRL=y\nCONFIG_PINCTRL_BCM6318=y\nCONFIG_PINCTRL_BCM63268=y\nCONFIG_PINCTRL_BCM6328=y\nCONFIG_PINCTRL_BCM6358=y\nCONFIG_PINCTRL_BCM6362=y\nCONFIG_PINCTRL_BCM6368=y\nCONFIG_PM=y\nCONFIG_PM_CLK=y\nCONFIG_PM_GENERIC_DOMAINS=y\nCONFIG_PM_GENERIC_DOMAINS_OF=y\nCONFIG_POSIX_MQUEUE=y\nCONFIG_POSIX_MQUEUE_SYSCTL=y\nCONFIG_POWER_RESET=y\nCONFIG_POWER_RESET_SYSCON=y\nCONFIG_POWER_SUPPLY=y\nCONFIG_PROC_VMCORE=y\nCONFIG_QUEUED_RWLOCKS=y\nCONFIG_QUEUED_SPINLOCKS=y\nCONFIG_RATIONAL=y\nCONFIG_REGMAP=y\nCONFIG_REGMAP_MMIO=y\nCONFIG_RELAY=y\nCONFIG_RESET_BCM6345=y\nCONFIG_RESET_CONTROLLER=y\nCONFIG_RFS_ACCEL=y\nCONFIG_RPS=y\n# CONFIG_SERIAL_8250 is not set\nCONFIG_SERIAL_BCM63XX=y\nCONFIG_SERIAL_BCM63XX_CONSOLE=y\nCONFIG_SGL_ALLOC=y\nCONFIG_SMP=y\nCONFIG_SMP_UP=y\nCONFIG_SOC_BCM63XX=y\nCONFIG_SPI=y\nCONFIG_SPI_BCM63XX=y\nCONFIG_SPI_BCM63XX_HSSPI=y\nCONFIG_SPI_MASTER=y\nCONFIG_SPI_MEM=y\nCONFIG_SRCU=y\nCONFIG_SSB=y\nCONFIG_SSB_B43_PCI_BRIDGE=y\nCONFIG_SSB_BLOCKIO=y\n# CONFIG_SSB_DRIVER_MIPS is not set\nCONFIG_SSB_DRIVER_PCICORE=y\nCONFIG_SSB_DRIVER_PCICORE_POSSIBLE=y\nCONFIG_SSB_PCIHOST=y\nCONFIG_SSB_PCIHOST_POSSIBLE=y\nCONFIG_SSB_SPROM=y\nCONFIG_SWAP_IO_SPACE=y\nCONFIG_SWPHY=y\nCONFIG_SYNC_R4K=y\nCONFIG_SYSCTL_EXCEPTION_TRACE=y\nCONFIG_SYS_HAS_CPU_BMIPS=y\nCONFIG_SYS_HAS_CPU_BMIPS32_3300=y\nCONFIG_SYS_HAS_CPU_BMIPS4350=y\nCONFIG_SYS_HAS_CPU_BMIPS4380=y\nCONFIG_SYS_HAS_CPU_BMIPS5000=y\nCONFIG_SYS_SUPPORTS_32BIT_KERNEL=y\nCONFIG_SYS_SUPPORTS_ARBIT_HZ=y\nCONFIG_SYS_SUPPORTS_BIG_ENDIAN=y\nCONFIG_SYS_SUPPORTS_HIGHMEM=y\nCONFIG_SYS_SUPPORTS_HOTPLUG_CPU=y\nCONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y\nCONFIG_SYS_SUPPORTS_SMP=y\nCONFIG_TARGET_ISA_REV=0\nCONFIG_TICK_CPU_ACCOUNTING=y\nCONFIG_TREE_RCU=y\nCONFIG_TREE_SRCU=y\nCONFIG_USB_EHCI_BIG_ENDIAN_DESC=y\nCONFIG_USB_EHCI_BIG_ENDIAN_MMIO=y\nCONFIG_USB_OHCI_BIG_ENDIAN_DESC=y\nCONFIG_USB_OHCI_BIG_ENDIAN_MMIO=y\nCONFIG_USB_SUPPORT=y\nCONFIG_USE_OF=y\nCONFIG_VM_EVENT_COUNTERS=y\nCONFIG_WATCHDOG_CORE=y\nCONFIG_WATCHDOG_NOWAYOUT=y\nCONFIG_WEAK_ORDERING=y\nCONFIG_XPS=y\nCONFIG_XXHASH=y\nCONFIG_ZLIB_DEFLATE=y\nCONFIG_ZLIB_INFLATE=y\nCONFIG_ZSTD_COMPRESS=y\nCONFIG_ZSTD_DECOMPRESS=y\n"
  },
  {
    "path": "target/linux/bmips/dts/bcm63168-comtrend-vr-3032u.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later\n\n#include \"bcm63268.dtsi\"\n\n/ {\n\tmodel = \"Comtrend VR-3032u\";\n\tcompatible = \"comtrend,vr-3032u\", \"brcm,bcm63168\", \"brcm,bcm63268\";\n\n\taliases {\n\t\tled-boot = &led_power_green;\n\t\tled-failsafe = &led_power_green;\n\t\tled-running = &led_power_green;\n\t\tled-upgrade = &led_power_green;\n\n\t\tled-dsl = &led_dsl_green;\n\t\tled-internet = &led_internet_green;\n\t\tled-usb = &led_usb_green;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 32 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio 33 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n};\n\n&ehci {\n\tstatus = \"okay\";\n};\n\n&ethernet {\n\tstatus = \"okay\";\n\n\tnvmem-cells = <&macaddr_cferom_6a0>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&leds {\n\tstatus = \"okay\";\n\n\tbrcm,serial-leds;\n\tbrcm,serial-dat-low;\n\tbrcm,serial-shift-inv;\n\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_serial_led>;\n\n\tled@0 {\n\t\t/* GPHY0 Spd 0 */\n\t\treg = <0>;\n\t\tbrcm,hardware-controlled;\n\t\tbrcm,link-signal-sources = <0>;\n\t};\n\n\tled@1 {\n\t\t/* GPHY0 Spd 1 */\n\t\treg = <1>;\n\t\tbrcm,hardware-controlled;\n\t\tbrcm,link-signal-sources = <1>;\n\t};\n\n\tled@2 {\n\t\treg = <2>;\n\t\tactive-low;\n\t\tlabel = \"red:internet\";\n\t};\n\n\tled_dsl_green: led@3 {\n\t\treg = <3>;\n\t\tactive-low;\n\t\tlabel = \"green:dsl\";\n\t};\n\n\tled_usb_green: led@4 {\n\t\treg = <4>;\n\t\tactive-low;\n\t\tlabel = \"green:usb\";\n\t};\n\n\tled@7 {\n\t\treg = <7>;\n\t\tactive-low;\n\t\tlabel = \"green:wps\";\n\t};\n\n\tled_internet_green: led@8 {\n\t\treg = <8>;\n\t\tactive-low;\n\t\tlabel = \"green:internet\";\n\t};\n\n\tled@9 {\n\t\t/* EPHY0 Act */\n\t\treg = <9>;\n\t\tbrcm,hardware-controlled;\n\t};\n\n\tled@10 {\n\t\t/* EPHY1 Act */\n\t\treg = <10>;\n\t\tbrcm,hardware-controlled;\n\t};\n\n\tled@11 {\n\t\t/* EPHY2 Act */\n\t\treg = <11>;\n\t\tbrcm,hardware-controlled;\n\t};\n\n\tled@12 {\n\t\t/* GPHY0 Act */\n\t\treg = <12>;\n\t\tbrcm,hardware-controlled;\n\t};\n\n\tled@13 {\n\t\t/* EPHY0 Spd */\n\t\treg = <13>;\n\t\tbrcm,hardware-controlled;\n\t};\n\n\tled@14 {\n\t\t/* EPHY1 Spd */\n\t\treg = <14>;\n\t\tbrcm,hardware-controlled;\n\t};\n\n\tled@15 {\n\t\t/* EPHY2 Spd */\n\t\treg = <15>;\n\t\tbrcm,hardware-controlled;\n\t};\n\n\tled_power_green: led@20 {\n\t\treg = <20>;\n\t\tactive-low;\n\t\tlabel = \"green:power\";\n\t};\n};\n\n&nflash {\n\tstatus = \"okay\";\n\n\tnandcs@0 {\n\t\tcompatible = \"brcm,nandcs\";\n\t\treg = <0>;\n\t\tnand-ecc-step-size = <512>;\n\t\tnand-ecc-strength = <15>;\n\t\tnand-on-flash-bbt;\n\t\tbrcm,nand-oob-sector-size = <64>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tcferom: partition@0 {\n\t\t\t\tlabel = \"cferom\";\n\t\t\t\treg = <0x0000000 0x0020000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tcompatible = \"brcm,wfi-split\";\n\t\t\t\tlabel = \"wfi\";\n\t\t\t\treg = <0x0020000 0x7ac0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&ohci {\n\tstatus = \"okay\";\n};\n\n&switch0 {\n\tports {\n\t\tport@0 {\n\t\t\treg = <0>;\n\t\t\tlabel = \"lan2\";\n\n\t\t\tphy-handle = <&phy1>;\n\t\t};\n\n\t\tport@1 {\n\t\t\treg = <1>;\n\t\t\tlabel = \"lan3\";\n\n\t\t\tphy-handle = <&phy2>;\n\t\t};\n\n\t\tport@2 {\n\t\t\treg = <2>;\n\t\t\tlabel = \"lan4\";\n\n\t\t\tphy-handle = <&phy3>;\n\t\t};\n\n\t\tport@3 {\n\t\t\treg = <3>;\n\t\t\tlabel = \"lan1\";\n\n\t\t\tphy-handle = <&phy4>;\n\t\t};\n\t};\n};\n\n&uart0 {\n\tstatus = \"okay\";\n};\n\n&usbh {\n\tstatus = \"okay\";\n};\n\n&cferom {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_cferom_6a0: macaddr@6a0 {\n\t\treg = <0x6a0 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/bmips/dts/bcm6318-comtrend-ar-5315u.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later\n\n#include \"bcm6318.dtsi\"\n\n/ {\n\tmodel = \"Comtrend AR-5315u\";\n\tcompatible = \"comtrend,ar-5315u\", \"brcm,bcm6318\";\n\n\taliases {\n\t\tled-boot = &led_power_green;\n\t\tled-failsafe = &led_power_red;\n\t\tled-running = &led_power_green;\n\t\tled-upgrade = &led_power_green;\n\n\t\tled-dsl = &led_dsl_green;\n\t\tled-internet = &led_internet_green;\n\t\tled-usb = &led_usb_green;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <20>;\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&pinctrl 3 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&pinctrl 33 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tbcm43217-sprom {\n\t\tcompatible = \"brcm,bcm43217-sprom\";\n\n\t\tpci-bus = <1>;\n\t\tpci-dev = <0>;\n\n\t\tnvmem-cells = <&macaddr_cfe_6a0>;\n\t\tnvmem-cell-names = \"mac-address\";\n\t\tmac-address-increment = <1>;\n\n\t\tbrcm,sprom-fixups = <6 0x1c00>,\n\t\t\t\t    <65 0x1255>,\n\t\t\t\t    <97 0xfe55>,\n\t\t\t\t    <98 0x171d>,\n\t\t\t\t    <99 0xfa42>,\n\t\t\t\t    <113 0xfeb7>,\n\t\t\t\t    <114 0x18cd>,\n\t\t\t\t    <115 0xfa4f>,\n\t\t\t\t    <162 0x6444>,\n\t\t\t\t    <170 0x6444>,\n\t\t\t\t    <172 0x6444>;\n\t};\n};\n\n&ehci {\n\tstatus = \"okay\";\n};\n\n&ethernet {\n\tstatus = \"okay\";\n\n\tnvmem-cells = <&macaddr_cfe_6a0>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&hsspi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\tspi-max-frequency = <62500000>;\n\t\tspi-tx-bus-width = <2>;\n\t\tspi-rx-bus-width = <2>;\n\t\treg = <0>;\n\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tcfe: partition@0 {\n\t\t\t\treg = <0x000000 0x010000>;\n\t\t\t\tlabel = \"cfe\";\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@10000 {\n\t\t\t\tcompatible = \"brcm,bcm963xx-imagetag\";\n\t\t\t\treg = <0x010000 0xfe0000>;\n\t\t\t\tlabel = \"firmware\";\n\t\t\t};\n\n\t\t\tpartition@ff0000 {\n\t\t\t\treg = <0xff0000 0x010000>;\n\t\t\t\tlabel = \"nvram\";\n\t\t\t};\n\t\t};\n\t};\n};\n\n&leds {\n\tstatus = \"okay\";\n\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_leds\n\t\t     &pinctrl_ephy0_act_led &pinctrl_ephy1_act_led\n\t\t     &pinctrl_ephy2_act_led &pinctrl_ephy3_act_led>;\n\n\tled@0 {\n\t\treg = <0>;\n\t\tactive-low;\n\t\tlabel = \"green:wps\";\n\t};\n\n\tled_power_green: led@1 {\n\t\treg = <1>;\n\t\tactive-low;\n\t\tlabel = \"green:power\";\n\t};\n\n\tled_usb_green: led@2 {\n\t\treg = <2>;\n\t\tactive-low;\n\t\tlabel = \"green:usb\";\n\t};\n\n\tled@4 {\n\t\treg = <4>;\n\t\tbrcm,hardware-controlled;\n\t\tbrcm,link-signal-sources = <4>;\n\t\t/* EPHY0 Act */\n\t};\n\n\tled@5 {\n\t\treg = <5>;\n\t\tbrcm,hardware-controlled;\n\t\tbrcm,link-signal-sources = <5>;\n\t\t/* EPHY1 Act */\n\t};\n\n\tled@6 {\n\t\treg = <6>;\n\t\tbrcm,hardware-controlled;\n\t\tbrcm,link-signal-sources = <6>;\n\t\t/* EPHY2 Act */\n\t};\n\n\tled@7 {\n\t\treg = <7>;\n\t\tbrcm,hardware-controlled;\n\t\tbrcm,link-signal-sources = <7>;\n\t\t/* EPHY3 Act */\n\t};\n\n\tled_internet_green: led@8 {\n\t\treg = <8>;\n\t\tactive-low;\n\t\tlabel = \"green:internet\";\n\t};\n\n\tled@9 {\n\t\treg = <9>;\n\t\tactive-low;\n\t\tlabel = \"red:internet\";\n\t};\n\n\tled_dsl_green: led@10 {\n\t\treg = <10>;\n\t\tactive-low;\n\t\tlabel = \"green:dsl\";\n\t};\n\n\tled_power_red: led@11 {\n\t\treg = <11>;\n\t\tactive-low;\n\t\tlabel = \"red:power\";\n\t};\n};\n\n&ohci {\n\tstatus = \"okay\";\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pinctrl {\n\tpinctrl_leds: leds {\n\t\tfunction = \"led\";\n\t\tpins = \"gpio0\", \"gpio1\",\n\t\t       \"gpio2\", \"gpio8\",\n\t\t       \"gpio9\", \"gpio10\",\n\t\t       \"gpio11\";\n\t};\n};\n\n&switch0 {\n\tports {\n\t\tport@0 {\n\t\t\treg = <0>;\n\t\t\tlabel = \"lan4\";\n\n\t\t\tphy-handle = <&phy1>;\n\t\t};\n\n\t\tport@1 {\n\t\t\treg = <1>;\n\t\t\tlabel = \"lan3\";\n\n\t\t\tphy-handle = <&phy2>;\n\t\t};\n\n\t\tport@2 {\n\t\t\treg = <2>;\n\t\t\tlabel = \"lan2\";\n\n\t\t\tphy-handle = <&phy3>;\n\t\t};\n\n\t\tport@3 {\n\t\t\treg = <3>;\n\t\t\tlabel = \"lan1\";\n\n\t\t\tphy-handle = <&phy4>;\n\t\t};\n\t};\n};\n\n&uart0 {\n\tstatus = \"okay\";\n};\n\n&usbh {\n\tstatus = \"okay\";\n};\n\n&cfe {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_cfe_6a0: macaddr@6a0 {\n\t\treg = <0x6a0 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/bmips/dts/bcm6318.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later\n\n/dts-v1/;\n\n#include <dt-bindings/clock/bcm6318-clock.h>\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/interrupt-controller/bcm6318-interrupt-controller.h>\n#include <dt-bindings/reset/bcm6318-reset.h>\n#include <dt-bindings/soc/bcm6318-pm.h>\n\n/ {\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\tcompatible = \"brcm,bcm6318\";\n\n\taliases {\n\t\tpinctrl = &pinctrl;\n\t\tserial0 = &uart0;\n\t\tspi1 = &hsspi;\n\t};\n\n\tchosen {\n\t\tbootargs = \"earlycon\";\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\tclocks {\n\t\tperiph_osc: periph-osc {\n\t\t\tcompatible = \"fixed-clock\";\n\n\t\t\t#clock-cells = <0>;\n\n\t\t\tclock-frequency = <50000000>;\n\t\t\tclock-output-names = \"periph\";\n\t\t};\n\n\t\thsspi_osc: hsspi-osc {\n\t\t\tcompatible = \"fixed-clock\";\n\n\t\t\t#clock-cells = <0>;\n\n\t\t\tclock-frequency = <250000000>;\n\t\t\tclock-output-names = \"hsspi_osc\";\n\t\t};\n\t};\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tmips-hpt-frequency = <166500000>;\n\n\t\tcpu@0 {\n\t\t\tcompatible = \"brcm,bmips3300\", \"mips,mips4Kc\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\treg = <0>;\n\t\t};\n\t};\n\n\tcpu_intc: interrupt-controller {\n\t\t#address-cells = <0>;\n\t\tcompatible = \"mti,cpu-interrupt-controller\";\n\n\t\tinterrupt-controller;\n\t\t#interrupt-cells = <1>;\n\t};\n\n\tmemory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0 0>;\n\t};\n\n\tubus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tcompatible = \"simple-bus\";\n\t\tranges;\n\n\t\tperiph_clk: clock-controller@10000004 {\n\t\t\tcompatible = \"brcm,bcm6318-clocks\";\n\t\t\treg = <0x10000004 0x4>;\n\t\t\t#clock-cells = <1>;\n\t\t};\n\n\t\tubus_clk: clock-controller@10000008 {\n\t\t\tcompatible = \"brcm,bcm6318-ubus-clocks\";\n\t\t\treg = <0x10000008 0x4>;\n\t\t\t#clock-cells = <1>;\n\t\t};\n\n\t\tperiph_rst: reset-controller@10000010 {\n\t\t\tcompatible = \"brcm,bcm6345-reset\";\n\t\t\treg = <0x10000010 0x4>;\n\t\t\t#reset-cells = <1>;\n\t\t};\n\n\t\text_intc: interrupt-controller@10000018 {\n\t\t\t#address-cells = <1>;\n\t\t\tcompatible = \"brcm,bcm6318-ext-intc\";\n\t\t\treg = <0x10000018 0x4>;\n\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <2>;\n\n\t\t\tinterrupts = <BCM6318_IRQ_EXT0>,\n\t\t\t\t     <BCM6318_IRQ_EXT1>,\n\t\t\t\t     <BCM6318_IRQ_EXT2>,\n\t\t\t\t     <BCM6318_IRQ_EXT3>;\n\t\t};\n\n\t\tperiph_intc: interrupt-controller@10000020 {\n\t\t\t#address-cells = <1>;\n\t\t\tcompatible = \"brcm,bcm6345-l1-intc\";\n\t\t\treg = <0x10000020 0x20>;\n\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <1>;\n\n\t\t\tinterrupt-parent = <&cpu_intc>;\n\t\t\tinterrupts = <2>, <3>;\n\t\t};\n\n\t\twdt: watchdog@10000068 {\n\t\t\tcompatible = \"brcm,bcm7038-wdt\";\n\t\t\treg = <0x10000068 0xc>;\n\n\t\t\tclocks = <&periph_osc>;\n\n\t\t\ttimeout-sec = <30>;\n\t\t};\n\n\t\tpll_cntl: syscon@10000074 {\n\t\t\tcompatible = \"syscon\", \"simple-mfd\";\n\t\t\treg = <0x10000074 0x4>;\n\t\t\tnative-endian;\n\n\t\t\tsyscon-reboot {\n\t\t\t\tcompatible = \"syscon-reboot\";\n\t\t\t\toffset = <0>;\n\t\t\t\tmask = <0x1>;\n\t\t\t};\n\t\t};\n\n\t\tgpio_cntl: syscon@10000080 {\n\t\t\tcompatible = \"brcm,bcm6318-gpio-sysctl\",\n\t\t\t\t     \"syscon\", \"simple-mfd\";\n\t\t\treg = <0x10000080 0x80>;\n\t\t\tranges = <0 0x10000080 0x80>;\n\t\t\tnative-endian;\n\n\t\t\tgpio: gpio@0 {\n\t\t\t\tcompatible = \"brcm,bcm6318-gpio\";\n\t\t\t\treg-names = \"dirout\", \"dat\";\n\t\t\t\treg = <0x0 0x8>, <0x8 0x8>;\n\n\t\t\t\tgpio-controller;\n\t\t\t\tgpio-ranges = <&pinctrl 0 0 50>;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t};\n\n\t\t\tpinctrl: pinctrl@18 {\n\t\t\t\tcompatible = \"brcm,bcm6318-pinctrl\";\n\t\t\t\treg = <0x18 0x10>, <0x54 0x18>;\n\n\t\t\t\tpinctrl_ephy0_spd_led: ephy0_spd_led-pins {\n\t\t\t\t\tfunction = \"ephy0_spd_led\";\n\t\t\t\t\tpins = \"gpio0\";\n\t\t\t\t};\n\n\t\t\t\tpinctrl_ephy1_spd_led: ephy1_spd_led-pins {\n\t\t\t\t\tfunction = \"ephy1_spd_led\";\n\t\t\t\t\tpins = \"gpio1\";\n\t\t\t\t};\n\n\t\t\t\tpinctrl_ephy2_spd_led: ephy2_spd_led-pins {\n\t\t\t\t\tfunction = \"ephy2_spd_led\";\n\t\t\t\t\tpins = \"gpio2\";\n\t\t\t\t};\n\n\t\t\t\tpinctrl_ephy3_spd_led: ephy3_spd_led-pins {\n\t\t\t\t\tfunction = \"ephy3_spd_led\";\n\t\t\t\t\tpins = \"gpio3\";\n\t\t\t\t};\n\n\t\t\t\tpinctrl_ephy0_act_led: ephy0_act_led-pins {\n\t\t\t\t\tfunction = \"ephy0_act_led\";\n\t\t\t\t\tpins = \"gpio4\";\n\t\t\t\t};\n\n\t\t\t\tpinctrl_ephy1_act_led: ephy1_act_led-pins {\n\t\t\t\t\tfunction = \"ephy1_act_led\";\n\t\t\t\t\tpins = \"gpio5\";\n\t\t\t\t};\n\n\t\t\t\tpinctrl_ephy2_act_led: ephy2_act_led-pins {\n\t\t\t\t\tfunction = \"ephy2_act_led\";\n\t\t\t\t\tpins = \"gpio6\";\n\t\t\t\t};\n\n\t\t\t\tpinctrl_ephy3_act_led: ephy3_act_led-pins {\n\t\t\t\t\tfunction = \"ephy3_act_led\";\n\t\t\t\t\tpins = \"gpio7\";\n\t\t\t\t};\n\n\t\t\t\tpinctrl_serial_led: serial_led-pins {\n\t\t\t\t\tpinctrl_serial_led_data: serial_led_data-pins {\n\t\t\t\t\t\tfunction = \"serial_led_data\";\n\t\t\t\t\t\tpins = \"gpio6\";\n\t\t\t\t\t};\n\n\t\t\t\t\tpinctrl_serial_led_clk: serial_led_clk-pins {\n\t\t\t\t\t\tfunction = \"serial_led_clk\";\n\t\t\t\t\t\tpins = \"gpio7\";\n\t\t\t\t\t};\n\t\t\t\t};\n\n\t\t\t\tpinctrl_inet_act_led: inet_act_led-pins {\n\t\t\t\t\tfunction = \"inet_act_led\";\n\t\t\t\t\tpins = \"gpio8\";\n\t\t\t\t};\n\n\t\t\t\tpinctrl_inet_fail_led: inet_fail_led-pins {\n\t\t\t\t\tfunction = \"inet_fail_led\";\n\t\t\t\t\tpins = \"gpio9\";\n\t\t\t\t};\n\n\t\t\t\tpinctrl_dsl_led: dsl_led-pins {\n\t\t\t\t\tfunction = \"dsl_led\";\n\t\t\t\t\tpins = \"gpio10\";\n\t\t\t\t};\n\n\t\t\t\tpinctrl_post_fail_led: post_fail_led-pins {\n\t\t\t\t\tfunction = \"post_fail_led\";\n\t\t\t\t\tpins = \"gpio11\";\n\t\t\t\t};\n\n\t\t\t\tpinctrl_wlan_wps_led: wlan_wps_led-pins {\n\t\t\t\t\tfunction = \"wlan_wps_led\";\n\t\t\t\t\tpins = \"gpio12\";\n\t\t\t\t};\n\n\t\t\t\tpinctrl_usb_pwron: usb_pwron-pins {\n\t\t\t\t\tfunction = \"usb_pwron\";\n\t\t\t\t\tpins = \"gpio13\";\n\t\t\t\t};\n\n\t\t\t\tpinctrl_usb_device_led: usb_device_led-pins {\n\t\t\t\t\tfunction = \"usb_device_led\";\n\t\t\t\t\tpins = \"gpio13\";\n\t\t\t\t};\n\n\t\t\t\tpinctrl_usb_active: usb_active-pins {\n\t\t\t\t\tfunction = \"usb_active\";\n\t\t\t\t\tpins = \"gpio40\";\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tuart0: serial@10000100 {\n\t\t\tcompatible = \"brcm,bcm6345-uart\";\n\t\t\treg = <0x10000100 0x18>;\n\n\t\t\tinterrupt-parent = <&periph_intc>;\n\t\t\tinterrupts = <BCM6318_IRQ_UART0>;\n\n\t\t\tclocks = <&periph_osc>;\n\t\t\tclock-names = \"periph\";\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tleds: led-controller@10000200 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tcompatible = \"brcm,bcm6328-leds\";\n\t\t\treg = <0x10000200 0x24>;\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tperiph_pwr: power-controller@100008e8 {\n\t\t\tcompatible = \"brcm,bcm6318-power-controller\";\n\t\t\treg = <0x100008e8 0x4>;\n\n\t\t\t#power-domain-cells = <1>;\n\t\t};\n\n\t\thsspi: spi@10003000 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tcompatible = \"brcm,bcm6328-hsspi\";\n\t\t\treg = <0x10003000 0x600>;\n\n\t\t\tinterrupt-parent = <&periph_intc>;\n\t\t\tinterrupts = <BCM6318_IRQ_HSSPI>;\n\n\t\t\tclocks = <&periph_clk BCM6318_CLK_HSSPI>,\n\t\t\t\t <&hsspi_osc>;\n\t\t\tclock-names = \"hsspi\",\n\t\t\t\t      \"pll\";\n\n\t\t\tresets = <&periph_rst BCM6318_RST_SPI>;\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tehci: usb@10005000 {\n\t\t\tcompatible = \"brcm,bcm6318-ehci\", \"generic-ehci\";\n\t\t\treg = <0x10005000 0x100>;\n\t\t\tbig-endian;\n\t\t\tspurious-oc;\n\n\t\t\tinterrupt-parent = <&periph_intc>;\n\t\t\tinterrupts = <BCM6318_IRQ_EHCI>;\n\n\t\t\tphys = <&usbh 0>;\n\t\t\tphy-names = \"usb\";\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tohci: usb@10005100 {\n\t\t\tcompatible = \"brcm,bcm6318-ohci\", \"generic-ohci\";\n\t\t\treg = <0x10005100 0x100>;\n\t\t\tbig-endian;\n\t\t\tno-big-frame-no;\n\n\t\t\tinterrupt-parent = <&periph_intc>;\n\t\t\tinterrupts = <BCM6318_IRQ_OHCI>;\n\n\t\t\tphys = <&usbh 0>;\n\t\t\tphy-names = \"usb\";\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tusbh: usb-phy@10005200 {\n\t\t\tcompatible = \"brcm,bcm6318-usbh-phy\";\n\t\t\treg = <0x10005200 0x38>;\n\n\t\t\t#phy-cells = <1>;\n\n\t\t\tclocks = <&periph_clk BCM6318_CLK_USBD>,\n\t\t\t\t <&ubus_clk BCM6318_UCLK_USB>;\n\t\t\tclock-names = \"usbh\",\n\t\t\t\t      \"usb_ref\";\n\n\t\t\tpower-domains = <&periph_pwr BCM6318_POWER_DOMAIN_USB>;\n\t\t\tresets = <&periph_rst BCM6318_RST_USBH>;\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tpcie: pcie@10010000 {\n\t\t\tcompatible = \"brcm,bcm6318-pcie\";\n\t\t\treg = <0x10010000 0x10000>;\n\t\t\t#address-cells = <3>;\n\t\t\t#size-cells = <2>;\n\n\t\t\tdevice_type = \"pci\";\n\t\t\tbus-range = <0x00 0x01>;\n\t\t\tranges = <0x2000000 0 0x10200000 0x10200000 0 0x100000>;\n\t\t\tlinux,pci-probe-only = <1>;\n\n\t\t\tinterrupt-parent = <&periph_intc>;\n\t\t\tinterrupts = <BCM6318_IRQ_PCIE_RC>;\n\n\t\t\tclocks = <&periph_clk BCM6318_CLK_PCIE>,\n\t\t\t\t <&periph_clk BCM6318_CLK_PCIE25>,\n\t\t\t\t <&ubus_clk BCM6318_UCLK_PCIE>;\n\t\t\tclock-names = \"pcie\",\n\t\t\t\t      \"pcie25\",\n\t\t\t\t      \"pcie-ubus\";\n\n\t\t\tresets = <&periph_rst BCM6318_RST_PCIE>,\n\t\t\t\t <&periph_rst BCM6318_RST_PCIE_EXT>,\n\t\t\t\t <&periph_rst BCM6318_RST_PCIE_CORE>,\n\t\t\t\t <&periph_rst BCM6318_RST_PCIE_HARD>;\n\t\t\treset-names = \"pcie\",\n\t\t\t\t      \"pcie-ext\",\n\t\t\t\t      \"pcie-core\",\n\t\t\t\t      \"pcie-hard\";\n\n\t\t\tpower-domains = <&periph_pwr BCM6318_POWER_DOMAIN_PCIE>;\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tswitch0: switch@10080000 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tcompatible = \"brcm,bcm6328-switch\";\n\t\t\treg = <0x10080000 0x8000>;\n\t\t\tbig-endian;\n\n\t\t\tports {\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\n\t\t\t\tport@8 {\n\t\t\t\t\treg = <8>;\n\t\t\t\t\tlabel = \"cpu\";\n\n\t\t\t\t\tphy-mode = \"internal\";\n\t\t\t\t\tethernet = <&ethernet>;\n\n\t\t\t\t\tfixed-link {\n\t\t\t\t\t\tspeed = <1000>;\n\t\t\t\t\t\tfull-duplex;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tmdio: mdio@100800b0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tcompatible = \"brcm,bcm6368-mdio-mux\";\n\t\t\treg = <0x100800b0 0x8>;\n\n\t\t\tmdio_int: mdio@0 {\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\t\t\t\treg = <0>;\n\n\t\t\t\tphy1: ethernet-phy@1 {\n\t\t\t\t\tcompatible = \"ethernet-phy-ieee802.3-c22\";\n\t\t\t\t\treg = <1>;\n\t\t\t\t};\n\n\t\t\t\tphy2: ethernet-phy@2 {\n\t\t\t\t\tcompatible = \"ethernet-phy-ieee802.3-c22\";\n\t\t\t\t\treg = <2>;\n\t\t\t\t};\n\n\t\t\t\tphy3: ethernet-phy@3 {\n\t\t\t\t\tcompatible = \"ethernet-phy-ieee802.3-c22\";\n\t\t\t\t\treg = <3>;\n\t\t\t\t};\n\n\t\t\t\tphy4: ethernet-phy@4 {\n\t\t\t\t\tcompatible = \"ethernet-phy-ieee802.3-c22\";\n\t\t\t\t\treg = <4>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tmdio_ext: mdio@1 {\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\t\t\t\treg = <1>;\n\t\t\t};\n\t\t};\n\n\t\tethernet: ethernet@10088000 {\n\t\t\tcompatible = \"brcm,bcm6318-enetsw\";\n\t\t\treg = <0x10088000 0x80>,\n\t\t\t      <0x10088200 0x80>,\n\t\t\t      <0x10088400 0x80>;\n\t\t\treg-names = \"dma\",\n\t\t\t\t    \"dma-channels\",\n\t\t\t\t    \"dma-sram\";\n\n\t\t\tinterrupt-parent = <&periph_intc>;\n\t\t\tinterrupts = <BCM6318_IRQ_ENETSW_RX_DMA0>,\n\t\t\t\t     <BCM6318_IRQ_ENETSW_TX_DMA0>;\n\t\t\tinterrupt-names = \"rx\",\n\t\t\t\t\t  \"tx\";\n\n\t\t\tclocks = <&periph_clk BCM6318_CLK_ROBOSW250>,\n\t\t\t\t <&periph_clk BCM6318_CLK_ROBOSW025>,\n\t\t\t\t <&ubus_clk BCM6318_UCLK_ROBOSW>;\n\n\t\t\tresets = <&periph_rst BCM6318_RST_ENETSW>,\n\t\t\t\t <&periph_rst BCM6318_RST_EPHY>;\n\n\t\t\tpower-domains = <&periph_pwr BCM6318_POWER_DOMAIN_EPHY0>,\n\t\t\t\t\t<&periph_pwr BCM6318_POWER_DOMAIN_EPHY1>,\n\t\t\t\t\t<&periph_pwr BCM6318_POWER_DOMAIN_EPHY2>,\n\t\t\t\t\t<&periph_pwr BCM6318_POWER_DOMAIN_EPHY3>;\n\n\t\t\tdma-rx = <0>;\n\t\t\tdma-tx = <1>;\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/bmips/dts/bcm63268.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later\n\n/dts-v1/;\n\n#include <dt-bindings/clock/bcm63268-clock.h>\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/interrupt-controller/bcm63268-interrupt-controller.h>\n#include <dt-bindings/reset/bcm63268-reset.h>\n#include <dt-bindings/soc/bcm63268-pm.h>\n\n/ {\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\tcompatible = \"brcm,bcm63268\";\n\n\taliases {\n\t\tnflash = &nflash;\n\t\tpinctrl = &pinctrl;\n\t\tserial0 = &uart0;\n\t\tserial1 = &uart1;\n\t\tspi0 = &lsspi;\n\t\tspi1 = &hsspi;\n\t};\n\n\tchosen {\n\t\tbootargs = \"earlycon\";\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\tclocks {\n\t\tperiph_osc: periph-osc {\n\t\t\tcompatible = \"fixed-clock\";\n\n\t\t\t#clock-cells = <0>;\n\n\t\t\tclock-frequency = <50000000>;\n\t\t\tclock-output-names = \"periph\";\n\t\t};\n\n\t\thsspi_osc: hsspi-osc {\n\t\t\tcompatible = \"fixed-clock\";\n\n\t\t\t#clock-cells = <0>;\n\n\t\t\tclock-frequency = <400000000>;\n\t\t\tclock-output-names = \"hsspi_osc\";\n\t\t};\n\t};\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tmips-hpt-frequency = <200000000>;\n\n\t\tcpu@0 {\n\t\t\tcompatible = \"brcm,bmips4350\", \"mips,mips4Kc\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\treg = <0>;\n\t\t};\n\n\t\tcpu@1 {\n\t\t\tcompatible = \"brcm,bmips4350\", \"mips,mips4Kc\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\treg = <1>;\n\t\t};\n\t};\n\n\tcpu_intc: interrupt-controller {\n\t\t#address-cells = <0>;\n\t\tcompatible = \"mti,cpu-interrupt-controller\";\n\n\t\tinterrupt-controller;\n\t\t#interrupt-cells = <1>;\n\t};\n\n\tmemory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0 0>;\n\t};\n\n\tubus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tcompatible = \"simple-bus\";\n\t\tranges;\n\n\t\tperiph_clk: clock-controller@10000004 {\n\t\t\tcompatible = \"brcm,bcm63268-clocks\";\n\t\t\treg = <0x10000004 0x4>;\n\t\t\t#clock-cells = <1>;\n\t\t};\n\n\t\tpll_cntl: syscon@10000008 {\n\t\t\tcompatible = \"syscon\", \"simple-mfd\";\n\t\t\treg = <0x10000008 0x4>;\n\t\t\tnative-endian;\n\n\t\t\tsyscon-reboot {\n\t\t\t\tcompatible = \"syscon-reboot\";\n\t\t\t\toffset = <0x0>;\n\t\t\t\tmask = <0x1>;\n\t\t\t};\n\t\t};\n\n\t\tperiph_rst: reset-controller@10000010 {\n\t\t\tcompatible = \"brcm,bcm6345-reset\";\n\t\t\treg = <0x10000010 0x4>;\n\t\t\t#reset-cells = <1>;\n\t\t};\n\n\t\text_intc: interrupt-controller@10000018 {\n\t\t\t#address-cells = <1>;\n\t\t\tcompatible = \"brcm,bcm6345-ext-intc\";\n\t\t\treg = <0x10000018 0x4>;\n\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <2>;\n\n\t\t\tinterrupts = <BCM63268_IRQ_EXT0>,\n\t\t\t\t     <BCM63268_IRQ_EXT1>,\n\t\t\t\t     <BCM63268_IRQ_EXT2>,\n\t\t\t\t     <BCM63268_IRQ_EXT3>;\n\t\t};\n\n\t\tperiph_intc: interrupt-controller@10000020 {\n\t\t\t#address-cells = <1>;\n\t\t\tcompatible = \"brcm,bcm6345-l1-intc\";\n\t\t\treg = <0x10000020 0x20>,\n\t\t\t      <0x10000040 0x20>;\n\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <1>;\n\n\t\t\tinterrupt-parent = <&cpu_intc>;\n\t\t\tinterrupts = <2>, <3>;\n\t\t};\n\n\t\twdt: watchdog@1000009c {\n\t\t\tcompatible = \"brcm,bcm7038-wdt\";\n\t\t\treg = <0x1000009c 0xc>;\n\n\t\t\tclocks = <&periph_osc>;\n\n\t\t\ttimeout-sec = <30>;\n\t\t};\n\n\t\ttimer_clk: clock-controller@100000ac {\n\t\t\tcompatible = \"brcm,bcm63268-timer-clocks\";\n\t\t\treg = <0x100000ac 0x4>;\n\t\t\t#clock-cells = <1>;\n\t\t\t#reset-cells = <1>;\n\t\t};\n\n\t\tgpio_cntl: syscon@100000c0 {\n\t\t\tcompatible = \"brcm,bcm63268-gpio-sysctl\",\n\t\t\t\t     \"syscon\", \"simple-mfd\";\n\t\t\treg = <0x100000c0 0x80>;\n\t\t\tranges = <0 0x100000c0 0x80>;\n\t\t\tnative-endian;\n\n\t\t\tgpio: gpio@0 {\n\t\t\t\tcompatible = \"brcm,bcm63268-gpio\";\n\t\t\t\treg-names = \"dirout\", \"dat\";\n\t\t\t\treg = <0x0 0x8>, <0x8 0x8>;\n\n\t\t\t\tgpio-controller;\n\t\t\t\tgpio-ranges = <&pinctrl 0 0 52>;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t};\n\n\t\t\tpinctrl: pinctrl@10 {\n\t\t\t\tcompatible = \"brcm,bcm63268-pinctrl\";\n\t\t\t\treg = <0x10 0x4>, <0x18 0x8>, <0x38 0x4>;\n\n\t\t\t\tpinctrl_serial_led: serial_led-pins {\n\t\t\t\t\tpinctrl_serial_led_clk: serial_led_clk-pins {\n\t\t\t\t\t\tfunction = \"serial_led_clk\";\n\t\t\t\t\t\tpins = \"gpio0\";\n\t\t\t\t\t};\n\n\t\t\t\t\tpinctrl_serial_led_data: serial_led_data-pins {\n\t\t\t\t\t\tfunction = \"serial_led_data\";\n\t\t\t\t\t\tpins = \"gpio1\";\n\t\t\t\t\t};\n\t\t\t\t};\n\n\t\t\t\tpinctrl_hsspi_cs4: hsspi_cs4-pins {\n\t\t\t\t\tfunction = \"hsspi_cs4\";\n\t\t\t\t\tpins = \"gpio16\";\n\t\t\t\t};\n\n\t\t\t\tpinctrl_hsspi_cs5: hsspi_cs5-pins {\n\t\t\t\t\tfunction = \"hsspi_cs5\";\n\t\t\t\t\tpins = \"gpio17\";\n\t\t\t\t};\n\n\t\t\t\tpinctrl_hsspi_cs6: hsspi_cs6-pins {\n\t\t\t\t\tfunction = \"hsspi_cs6\";\n\t\t\t\t\tpins = \"gpio8\";\n\t\t\t\t};\n\n\t\t\t\tpinctrl_hsspi_cs7: hsspi_cs7-pins {\n\t\t\t\t\tfunction = \"hsspi_cs7\";\n\t\t\t\t\tpins = \"gpio9\";\n\t\t\t\t};\n\n\t\t\t\tpinctrl_adsl_spi: adsl_spi {\n\t\t\t\t\tpinctrl_adsl_spi_miso: adsl_spi_miso-pins {\n\t\t\t\t\t\tfunction = \"adsl_spi_miso\";\n\t\t\t\t\t\tpins = \"gpio18\";\n\t\t\t\t\t};\n\n\t\t\t\t\tpinctrl_adsl_spi_mosi: adsl_spi_mosi-pins {\n\t\t\t\t\t\tfunction = \"adsl_spi_mosi\";\n\t\t\t\t\t\tpins = \"gpio19\";\n\t\t\t\t\t};\n\t\t\t\t};\n\n\t\t\t\tpinctrl_vreq_clk: vreq_clk-pins {\n\t\t\t\t\tfunction = \"vreq_clk\";\n\t\t\t\t\tpins = \"gpio22\";\n\t\t\t\t};\n\n\t\t\t\tpinctrl_pcie_clkreq_b: pcie_clkreq_b-pins {\n\t\t\t\t\tfunction = \"pcie_clkreq_b\";\n\t\t\t\t\tpins = \"gpio23\";\n\t\t\t\t};\n\n\t\t\t\tpinctrl_robosw_led_clk: robosw_led_clk-pins {\n\t\t\t\t\tfunction = \"robosw_led_clk\";\n\t\t\t\t\tpins = \"gpio30\";\n\t\t\t\t};\n\n\t\t\t\tpinctrl_robosw_led_data: robosw_led_data-pins {\n\t\t\t\t\tfunction = \"robosw_led_data\";\n\t\t\t\t\tpins = \"gpio31\";\n\t\t\t\t};\n\n\t\t\t\tpinctrl_nand: nand-pins {\n\t\t\t\t\tfunction = \"nand\";\n\t\t\t\t\tgroup = \"nand_grp\";\n\t\t\t\t};\n\n\t\t\t\tpinctrl_gpio35_alt: gpio35_alt-pins {\n\t\t\t\t\tfunction = \"gpio35_alt\";\n\t\t\t\t\tpin = \"gpio35\";\n\t\t\t\t};\n\n\t\t\t\tpinctrl_dectpd: dectpd-pins {\n\t\t\t\t\tfunction = \"dectpd\";\n\t\t\t\t\tgroup = \"dectpd_grp\";\n\t\t\t\t};\n\n\t\t\t\tpinctrl_vdsl_phy_override_0: vdsl_phy_override_0-pins {\n\t\t\t\t\tfunction = \"vdsl_phy_override_0\";\n\t\t\t\t\tgroup = \"vdsl_phy_override_0_grp\";\n\t\t\t\t};\n\n\t\t\t\tpinctrl_vdsl_phy_override_1: vdsl_phy_override_1-pins {\n\t\t\t\t\tfunction = \"vdsl_phy_override_1\";\n\t\t\t\t\tgroup = \"vdsl_phy_override_1_grp\";\n\t\t\t\t};\n\n\t\t\t\tpinctrl_vdsl_phy_override_2: vdsl_phy_override_2-pins {\n\t\t\t\t\tfunction = \"vdsl_phy_override_2\";\n\t\t\t\t\tgroup = \"vdsl_phy_override_2_grp\";\n\t\t\t\t};\n\n\t\t\t\tpinctrl_vdsl_phy_override_3: vdsl_phy_override_3-pins {\n\t\t\t\t\tfunction = \"vdsl_phy_override_3\";\n\t\t\t\t\tgroup = \"vdsl_phy_override_3_grp\";\n\t\t\t\t};\n\n\t\t\t\tpinctrl_dsl_gpio8: dsl_gpio8-pins {\n\t\t\t\t\tfunction = \"dsl_gpio8\";\n\t\t\t\t\tgroup = \"dsl_gpio8\";\n\t\t\t\t};\n\n\t\t\t\tpinctrl_dsl_gpio9: dsl_gpio9-pins {\n\t\t\t\t\tfunction = \"dsl_gpio9\";\n\t\t\t\t\tgroup = \"dsl_gpio9\";\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tuart0: serial@10000180 {\n\t\t\tcompatible = \"brcm,bcm6345-uart\";\n\t\t\treg = <0x10000180 0x18>;\n\n\t\t\tinterrupt-parent = <&periph_intc>;\n\t\t\tinterrupts = <BCM63268_IRQ_UART0>;\n\n\t\t\tclocks = <&periph_osc>;\n\t\t\tclock-names = \"periph\";\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tuart1: serial@100001a0 {\n\t\t\tcompatible = \"brcm,bcm6345-uart\";\n\t\t\treg = <0x100001a0 0x18>;\n\n\t\t\tinterrupt-parent = <&periph_intc>;\n\t\t\tinterrupts = <BCM63268_IRQ_UART1>;\n\n\t\t\tclocks = <&periph_osc>;\n\t\t\tclock-names = \"periph\";\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tnflash: nand@10000200 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tcompatible = \"brcm,nand-bcm6368\",\n\t\t\t\t     \"brcm,brcmnand-v4.0\",\n\t\t\t\t     \"brcm,brcmnand\";\n\t\t\treg = <0x10000200 0x180>,\n\t\t\t      <0x10000600 0x200>,\n\t\t\t      <0x100000b0 0x10>;\n\t\t\treg-names = \"nand\",\n\t\t\t\t    \"nand-cache\",\n\t\t\t\t    \"nand-int-base\";\n\n\t\t\tinterrupt-parent = <&periph_intc>;\n\t\t\tinterrupts = <BCM63268_IRQ_NAND>;\n\n\t\t\tclocks = <&periph_clk BCM63268_CLK_NAND>;\n\t\t\tclock-names = \"nand\";\n\n\t\t\tpinctrl-names = \"default\";\n\t\t\tpinctrl-0 = <&pinctrl_nand>;\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tlsspi: spi@10000800 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tcompatible = \"brcm,bcm6358-spi\";\n\t\t\treg = <0x10000800 0x70c>;\n\n\t\t\tinterrupt-parent = <&periph_intc>;\n\t\t\tinterrupts = <BCM63268_IRQ_LSSPI>;\n\n\t\t\tclocks = <&periph_clk BCM63268_CLK_SPI>;\n\t\t\tclock-names = \"spi\";\n\n\t\t\tresets = <&periph_rst BCM63268_RST_SPI>;\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\thsspi: spi@10001000 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tcompatible = \"brcm,bcm6328-hsspi\";\n\t\t\treg = <0x10001000 0x600>;\n\n\t\t\tinterrupt-parent = <&periph_intc>;\n\t\t\tinterrupts = <BCM63268_IRQ_HSSPI>;\n\n\t\t\tclocks = <&periph_clk BCM63268_CLK_HSSPI>,\n\t\t\t\t <&hsspi_osc>;\n\t\t\tclock-names = \"hsspi\",\n\t\t\t\t      \"pll\";\n\n\t\t\tresets = <&periph_rst BCM63268_RST_SPI>;\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tserdes_cntl: syscon@10001804 {\n\t\t\tcompatible = \"syscon\";\n\t\t\treg = <0x10001804 0x4>;\n\t\t\tnative-endian;\n\t\t};\n\n\t\tperiph_pwr: power-controller@1000184c {\n\t\t\tcompatible = \"brcm,bcm63268-power-controller\";\n\t\t\treg = <0x1000184c 0x4>;\n\t\t\t#power-domain-cells = <1>;\n\t\t};\n\n\t\tleds: led-controller@10001900 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tcompatible = \"brcm,bcm6328-leds\";\n\t\t\treg = <0x10001900 0x24>;\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tehci: usb@10002500 {\n\t\t\tcompatible = \"brcm,bcm63268-ehci\", \"generic-ehci\";\n\t\t\treg = <0x10002500 0x100>;\n\t\t\tbig-endian;\n\t\t\tspurious-oc;\n\n\t\t\tinterrupt-parent = <&periph_intc>;\n\t\t\tinterrupts = <BCM63268_IRQ_EHCI>;\n\n\t\t\tphys = <&usbh 0>;\n\t\t\tphy-names = \"usb\";\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tohci: usb@10002600 {\n\t\t\tcompatible = \"brcm,bcm63268-ohci\", \"generic-ohci\";\n\t\t\treg = <0x10002600 0x100>;\n\t\t\tbig-endian;\n\t\t\tno-big-frame-no;\n\n\t\t\tinterrupt-parent = <&periph_intc>;\n\t\t\tinterrupts = <BCM63268_IRQ_OHCI>;\n\n\t\t\tphys = <&usbh 0>;\n\t\t\tphy-names = \"usb\";\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tusbh: usb-phy@10002700 {\n\t\t\tcompatible = \"brcm,bcm63268-usbh-phy\";\n\t\t\treg = <0x10002700 0x38>;\n\n\t\t\t#phy-cells = <1>;\n\n\t\t\tclocks = <&periph_clk BCM63268_CLK_USBH>,\n\t\t\t\t <&timer_clk BCM63268_TCLK_USB_REF>;\n\t\t\tclock-names = \"usbh\",\n\t\t\t\t      \"usb_ref\";\n\n\t\t\tpower-domains = <&periph_pwr BCM63268_POWER_DOMAIN_USBH>;\n\t\t\tresets = <&periph_rst BCM63268_RST_USBH>;\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tethernet: ethernet@1000d800 {\n\t\t\tcompatible = \"brcm,bcm63268-enetsw\";\n\t\t\treg = <0x1000d800 0x80>,\n\t\t\t      <0x1000da00 0x80>,\n\t\t\t      <0x1000dc00 0x80>;\n\t\t\treg-names = \"dma\",\n\t\t\t\t    \"dma-channels\",\n\t\t\t\t    \"dma-sram\";\n\n\t\t\tinterrupt-parent = <&periph_intc>;\n\t\t\tinterrupts = <BCM63268_IRQ_ENETSW_RX_DMA0>,\n\t\t\t\t     <BCM63268_IRQ_ENETSW_TX_DMA0>;\n\t\t\tinterrupt-names = \"rx\",\n\t\t\t\t\t  \"tx\";\n\n\t\t\tclocks = <&periph_clk BCM63268_CLK_GMAC>,\n\t\t\t\t <&periph_clk BCM63268_CLK_ROBOSW>,\n\t\t\t\t <&periph_clk BCM63268_CLK_ROBOSW250>,\n\t\t\t\t <&timer_clk BCM63268_TCLK_EPHY1>,\n\t\t\t\t <&timer_clk BCM63268_TCLK_EPHY2>,\n\t\t\t\t <&timer_clk BCM63268_TCLK_EPHY3>,\n\t\t\t\t <&timer_clk BCM63268_TCLK_GPHY1>;\n\n\t\t\tresets = <&periph_rst BCM63268_RST_ENETSW>,\n\t\t\t\t <&periph_rst BCM63268_RST_EPHY>,\n\t\t\t\t <&periph_rst BCM63268_RST_GPHY>;\n\n\t\t\tpower-domains = <&periph_pwr BCM63268_POWER_DOMAIN_ROBOSW>;\n\n\t\t\tdma-rx = <0>;\n\t\t\tdma-tx = <1>;\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tpcie: pcie@106e0000 {\n\t\t\tcompatible = \"brcm,bcm6328-pcie\";\n\t\t\treg = <0x106e0000 0x10000>;\n\t\t\t#address-cells = <3>;\n\t\t\t#size-cells = <2>;\n\n\t\t\tdevice_type = \"pci\";\n\t\t\tbus-range = <0x00 0x01>;\n\t\t\tranges = <0x2000000 0 0x11000000 0x11000000 0 0xf00000>;\n\t\t\tlinux,pci-probe-only = <1>;\n\n\t\t\tinterrupt-parent = <&periph_intc>;\n\t\t\tinterrupts = <BCM63268_IRQ_PCIE_RC>;\n\n\t\t\tclocks = <&periph_clk BCM63268_CLK_PCIE>;\n\t\t\tclock-names = \"pcie\";\n\n\t\t\tresets = <&periph_rst BCM63268_RST_PCIE>,\n\t\t\t\t <&periph_rst BCM63268_RST_PCIE_EXT>,\n\t\t\t\t <&periph_rst BCM63268_RST_PCIE_CORE>,\n\t\t\t\t <&periph_rst BCM63268_RST_PCIE_HARD>;\n\t\t\treset-names = \"pcie\",\n\t\t\t\t      \"pcie-ext\",\n\t\t\t\t      \"pcie-core\",\n\t\t\t\t      \"pcie-hard\";\n\n\t\t\tpower-domains = <&periph_pwr BCM63268_POWER_DOMAIN_PCIE>;\n\n\t\t\tbrcm,serdes = <&serdes_cntl>;\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tswitch0: switch@10700000 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tcompatible = \"brcm,bcm6328-switch\";\n\t\t\treg = <0x10700000 0x8000>;\n\t\t\tbig-endian;\n\n\t\t\tports {\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\n\t\t\t\tport@8 {\n\t\t\t\t\treg = <8>;\n\t\t\t\t\tlabel = \"cpu\";\n\n\t\t\t\t\tphy-mode = \"internal\";\n\t\t\t\t\tethernet = <&ethernet>;\n\n\t\t\t\t\tfixed-link {\n\t\t\t\t\t\tspeed = <1000>;\n\t\t\t\t\t\tfull-duplex;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tmdio: mdio@107000b0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tcompatible = \"brcm,bcm6368-mdio-mux\";\n\t\t\treg = <0x107000b0 0x8>;\n\n\t\t\tmdio_int: mdio@0 {\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\t\t\t\treg = <0>;\n\n\t\t\t\tphy1: ethernet-phy@1 {\n\t\t\t\t\tcompatible = \"ethernet-phy-ieee802.3-c22\";\n\t\t\t\t\treg = <1>;\n\t\t\t\t};\n\n\t\t\t\tphy2: ethernet-phy@2 {\n\t\t\t\t\tcompatible = \"ethernet-phy-ieee802.3-c22\";\n\t\t\t\t\treg = <2>;\n\t\t\t\t};\n\n\t\t\t\tphy3: ethernet-phy@3 {\n\t\t\t\t\tcompatible = \"ethernet-phy-ieee802.3-c22\";\n\t\t\t\t\treg = <3>;\n\t\t\t\t};\n\n\t\t\t\tphy4: ethernet-phy@4 {\n\t\t\t\t\tcompatible = \"ethernet-phy-ieee802.3-c22\";\n\t\t\t\t\treg = <4>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tmdio_ext: mdio@1 {\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\t\t\t\treg = <1>;\n\t\t\t};\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/bmips/dts/bcm6328-comtrend-ar-5387un.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later\n\n#include \"bcm6328.dtsi\"\n\n/ {\n\tmodel = \"Comtrend AR-5387un\";\n\tcompatible = \"comtrend,ar-5387un\", \"brcm,bcm6328\";\n\n\taliases {\n\t\tled-boot = &led_power_green;\n\t\tled-failsafe = &led_power_red;\n\t\tled-running = &led_power_green;\n\t\tled-upgrade = &led_power_green;\n\n\t\tled-dsl = &led_dsl_green;\n\t\tled-internet = &led_internet_green;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tbcm43225-sprom {\n\t\tcompatible = \"brcm,bcm43225-sprom\";\n\n\t\tpci-bus = <1>;\n\t\tpci-dev = <0>;\n\n\t\tnvmem-cells = <&macaddr_cfe_6a0>;\n\t\tnvmem-cell-names = \"mac-address\";\n\t\tmac-address-increment = <1>;\n\n\t\tbrcm,sprom-fixups = <2 0x05bb>,\n\t\t\t\t    <65 0x1204>,\n\t\t\t\t    <78 0x0303>,\n\t\t\t\t    <79 0x0202>,\n\t\t\t\t    <80 0xff02>,\n\t\t\t\t    <87 0x0315>,\n\t\t\t\t    <88 0x0315>,\n\t\t\t\t    <96 0x2048>,\n\t\t\t\t    <97 0xff11>,\n\t\t\t\t    <98 0x1567>,\n\t\t\t\t    <99 0xfb24>,\n\t\t\t\t    <100 0x3e3c>,\n\t\t\t\t    <101 0x4038>,\n\t\t\t\t    <102 0xfe7f>,\n\t\t\t\t    <103 0x1279>,\n\t\t\t\t    <112 0x2048>,\n\t\t\t\t    <113 0xff03>,\n\t\t\t\t    <114 0x154c>,\n\t\t\t\t    <115 0xfb27>,\n\t\t\t\t    <116 0x3e3c>,\n\t\t\t\t    <117 0x4038>,\n\t\t\t\t    <118 0xfe87>,\n\t\t\t\t    <119 0x1233>,\n\t\t\t\t    <203 0x2226>;\n\t};\n};\n\n&ehci {\n\tstatus = \"okay\";\n};\n\n&ethernet {\n\tstatus = \"okay\";\n\n\tnvmem-cells = <&macaddr_cfe_6a0>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&hsspi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\tspi-max-frequency = <16666667>;\n\t\tspi-tx-bus-width = <2>;\n\t\tspi-rx-bus-width = <2>;\n\t\treg = <0>;\n\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tcfe: partition@0 {\n\t\t\t\treg = <0x000000 0x010000>;\n\t\t\t\tlabel = \"cfe\";\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@10000 {\n\t\t\t\tcompatible = \"brcm,bcm963xx-imagetag\";\n\t\t\t\treg = <0x010000 0xfe0000>;\n\t\t\t\tlabel = \"firmware\";\n\t\t\t};\n\n\t\t\tpartition@ff0000 {\n\t\t\t\treg = <0xff0000 0x010000>;\n\t\t\t\tlabel = \"nvram\";\n\t\t\t};\n\t\t};\n\t};\n};\n\n&leds {\n\tstatus = \"okay\";\n\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_leds>;\n\n\tled@1 {\n\t\treg = <1>;\n\t\tlabel = \"red:internet\";\n\t};\n\n\tled_power_red: led@4 {\n\t\treg = <4>;\n\t\tlabel = \"red:power\";\n\t};\n\n\tled_internet_green: led@7 {\n\t\treg = <7>;\n\t\tlabel = \"green:internet\";\n\t};\n\n\tled_power_green: led@8 {\n\t\treg = <8>;\n\t\tlabel = \"green:power\";\n\t};\n\n\tled_dsl_green: led@11 {\n\t\treg = <11>;\n\t\tactive-low;\n\t\tlabel = \"green:dsl\";\n\t};\n};\n\n&ohci {\n\tstatus = \"okay\";\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pinctrl {\n\tpinctrl_leds: leds {\n\t\tfunction = \"led\";\n\t\tpins = \"gpio1\", \"gpio4\", \"gpio7\",\n\t\t       \"gpio8\", \"gpio11\";\n\t};\n};\n\n&switch0 {\n\tports {\n\t\tport@0 {\n\t\t\treg = <0>;\n\t\t\tlabel = \"lan1\";\n\n\t\t\tphy-handle = <&phy1>;\n\t\t};\n\n\t\tport@1 {\n\t\t\treg = <1>;\n\t\t\tlabel = \"lan2\";\n\n\t\t\tphy-handle = <&phy2>;\n\t\t};\n\n\t\tport@2 {\n\t\t\treg = <2>;\n\t\t\tlabel = \"lan3\";\n\n\t\t\tphy-handle = <&phy3>;\n\t\t};\n\n\t\tport@3 {\n\t\t\treg = <3>;\n\t\t\tlabel = \"lan4\";\n\n\t\t\tphy-handle = <&phy4>;\n\t\t};\n\t};\n};\n\n&uart0 {\n\tstatus = \"okay\";\n};\n\n&usbh {\n\tstatus = \"okay\";\n};\n\n&cfe {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_cfe_6a0: macaddr@6a0 {\n\t\treg = <0x6a0 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/bmips/dts/bcm6328.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later\n\n/dts-v1/;\n\n#include <dt-bindings/clock/bcm6328-clock.h>\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/interrupt-controller/bcm6328-interrupt-controller.h>\n#include <dt-bindings/reset/bcm6328-reset.h>\n#include <dt-bindings/soc/bcm6328-pm.h>\n\n/ {\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\tcompatible = \"brcm,bcm6328\";\n\n\taliases {\n\t\tnflash = &nflash;\n\t\tpinctrl = &pinctrl;\n\t\tserial0 = &uart0;\n\t\tserial1 = &uart1;\n\t\tspi1 = &hsspi;\n\t};\n\n\tchosen {\n\t\tbootargs = \"earlycon\";\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\tclocks {\n\t\tperiph_osc: periph-osc {\n\t\t\tcompatible = \"fixed-clock\";\n\n\t\t\t#clock-cells = <0>;\n\n\t\t\tclock-frequency = <50000000>;\n\t\t\tclock-output-names = \"periph\";\n\t\t};\n\n\t\thsspi_osc: hsspi-osc {\n\t\t\tcompatible = \"fixed-clock\";\n\n\t\t\t#clock-cells = <0>;\n\n\t\t\tclock-frequency = <133333333>;\n\t\t\tclock-output-names = \"hsspi_osc\";\n\t\t};\n\t};\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tmips-hpt-frequency = <160000000>;\n\n\t\tcpu@0 {\n\t\t\tcompatible = \"brcm,bmips4350\", \"mips,mips4Kc\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\treg = <0>;\n\t\t};\n\n\t\tcpu@1 {\n\t\t\tcompatible = \"brcm,bmips4350\", \"mips,mips4Kc\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\treg = <1>;\n\t\t};\n\t};\n\n\tcpu_intc: interrupt-controller {\n\t\t#address-cells = <0>;\n\t\tcompatible = \"mti,cpu-interrupt-controller\";\n\n\t\tinterrupt-controller;\n\t\t#interrupt-cells = <1>;\n\t};\n\n\tmemory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0 0>;\n\t};\n\n\tubus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tcompatible = \"simple-bus\";\n\t\tranges;\n\n\t\tperiph_clk: clock-controller@10000004 {\n\t\t\tcompatible = \"brcm,bcm6328-clocks\";\n\t\t\treg = <0x10000004 0x4>;\n\t\t\t#clock-cells = <1>;\n\t\t};\n\n\t\tperiph_rst: reset-controller@10000010 {\n\t\t\tcompatible = \"brcm,bcm6345-reset\";\n\t\t\treg = <0x10000010 0x4>;\n\t\t\t#reset-cells = <1>;\n\t\t};\n\n\t\text_intc: interrupt-controller@10000018 {\n\t\t\t#address-cells = <1>;\n\t\t\tcompatible = \"brcm,bcm6345-ext-intc\";\n\t\t\treg = <0x10000018 0x4>;\n\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <2>;\n\n\t\t\tinterrupts = <BCM6328_IRQ_EXTO>,\n\t\t\t\t     <BCM6328_IRQ_EXT1>,\n\t\t\t\t     <BCM6328_IRQ_EXT2>,\n\t\t\t\t     <BCM6328_IRQ_EXT3>;\n\t\t};\n\n\t\tperiph_intc: interrupt-controller@10000020 {\n\t\t\t#address-cells = <1>;\n\t\t\tcompatible = \"brcm,bcm6345-l1-intc\";\n\t\t\treg = <0x10000020 0x10>,\n\t\t\t      <0x10000030 0x10>;\n\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <1>;\n\n\t\t\tinterrupt-parent = <&cpu_intc>;\n\t\t\tinterrupts = <2>, <3>;\n\t\t};\n\n\t\twdt: watchdog@1000005c {\n\t\t\tcompatible = \"brcm,bcm7038-wdt\";\n\t\t\treg = <0x1000005c 0xc>;\n\n\t\t\tclocks = <&periph_osc>;\n\n\t\t\ttimeout-sec = <30>;\n\t\t};\n\n\t\tpll_cntl: syscon@10000068 {\n\t\t\tcompatible = \"syscon\", \"simple-mfd\";\n\t\t\treg = <0x10000068 0x4>;\n\t\t\tnative-endian;\n\n\t\t\tsyscon-reboot {\n\t\t\t\tcompatible = \"syscon-reboot\";\n\t\t\t\toffset = <0>;\n\t\t\t\tmask = <0x1>;\n\t\t\t};\n\t\t};\n\n\t\tgpio_cntl: syscon@10000080 {\n\t\t\tcompatible = \"brcm,bcm6328-gpio-sysctl\",\n\t\t\t\t     \"syscon\", \"simple-mfd\";\n\t\t\treg = <0x10000080 0x80>;\n\t\t\tranges = <0 0x10000080 0x80>;\n\t\t\tnative-endian;\n\n\t\t\tgpio: gpio@0 {\n\t\t\t\tcompatible = \"brcm,bcm6328-gpio\";\n\t\t\t\treg-names = \"dirout\", \"dat\";\n\t\t\t\treg = <0x0 0x8>, <0x8 0x8>;\n\n\t\t\t\tgpio-controller;\n\t\t\t\tgpio-ranges = <&pinctrl 0 0 32>;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t};\n\n\t\t\tpinctrl: pinctrl@18 {\n\t\t\t\tcompatible = \"brcm,bcm6328-pinctrl\";\n\t\t\t\treg = <0x18 0x10>;\n\n\t\t\t\tpinctrl_serial_led: serial_led-pins {\n\t\t\t\t\tpinctrl_serial_led_data: serial_led_data-pins {\n\t\t\t\t\t\tfunction = \"serial_led_data\";\n\t\t\t\t\t\tpins = \"gpio6\";\n\t\t\t\t\t};\n\n\t\t\t\t\tpinctrl_serial_led_clk: serial_led_clk-pins {\n\t\t\t\t\t\tfunction = \"serial_led_clk\";\n\t\t\t\t\t\tpins = \"gpio7\";\n\t\t\t\t\t};\n\t\t\t\t};\n\n\t\t\t\tpinctrl_inet_act_led: inet_act_led-pins {\n\t\t\t\t\tfunction = \"inet_act_led\";\n\t\t\t\t\tpins = \"gpio11\";\n\t\t\t\t};\n\n\t\t\t\tpinctrl_pcie_clkreq: pcie_clkreq-pins {\n\t\t\t\t\tfunction = \"pcie_clkreq\";\n\t\t\t\t\tpins = \"gpio16\";\n\t\t\t\t};\n\n\t\t\t\tpinctrl_ephy0_spd_led: ephy0_spd_led-pins {\n\t\t\t\t\tfunction = \"led\";\n\t\t\t\t\tpins = \"gpio17\";\n\t\t\t\t};\n\n\t\t\t\tpinctrl_ephy1_spd_led: ephy1_spd_led-pins {\n\t\t\t\t\tfunction = \"led\";\n\t\t\t\t\tpins = \"gpio18\";\n\t\t\t\t};\n\n\t\t\t\tpinctrl_ephy2_spd_led: ephy2_spd_led-pins {\n\t\t\t\t\tfunction = \"led\";\n\t\t\t\t\tpins = \"gpio19\";\n\t\t\t\t};\n\n\t\t\t\tpinctrl_ephy3_spd_led: ephy3_spd_led-pins {\n\t\t\t\t\tfunction = \"led\";\n\t\t\t\t\tpins = \"gpio20\";\n\t\t\t\t};\n\n\t\t\t\tpinctrl_ephy0_act_led: ephy0_act_led-pins {\n\t\t\t\t\tfunction = \"ephy0_act_led\";\n\t\t\t\t\tpins = \"gpio25\";\n\t\t\t\t};\n\n\t\t\t\tpinctrl_ephy1_act_led: ephy1_act_led-pins {\n\t\t\t\t\tfunction = \"ephy1_act_led\";\n\t\t\t\t\tpins = \"gpio26\";\n\t\t\t\t};\n\n\t\t\t\tpinctrl_ephy2_act_led: ephy2_act_led-pins {\n\t\t\t\t\tfunction = \"ephy2_act_led\";\n\t\t\t\t\tpins = \"gpio27\";\n\t\t\t\t};\n\n\t\t\t\tpinctrl_ephy3_act_led: ephy3_act_led-pins {\n\t\t\t\t\tfunction = \"ephy3_act_led\";\n\t\t\t\t\tpins = \"gpio28\";\n\t\t\t\t};\n\n\t\t\t\tpinctrl_hsspi_cs1: hsspi_cs1-pins {\n\t\t\t\t\tfunction = \"hsspi_cs1\";\n\t\t\t\t\tpins = \"hsspi_cs1\";\n\t\t\t\t};\n\n\t\t\t\tpinctrl_usb_port1_device: usb_port1_device-pins {\n\t\t\t\t\tfunction = \"usb_device_port\";\n\t\t\t\t\tpins = \"usb_port1\";\n\t\t\t\t};\n\n\t\t\t\tpinctrl_usb_port1_host: usb_port1_host-pins {\n\t\t\t\t\tfunction = \"usb_host_port\";\n\t\t\t\t\tpins = \"usb_port1\";\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tuart0: serial@10000100 {\n\t\t\tcompatible = \"brcm,bcm6345-uart\";\n\t\t\treg = <0x10000100 0x18>;\n\n\t\t\tinterrupt-parent = <&periph_intc>;\n\t\t\tinterrupts = <BCM6328_IRQ_UART0>;\n\n\t\t\tclocks = <&periph_osc>;\n\t\t\tclock-names = \"periph\";\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tuart1: serial@10000120 {\n\t\t\tcompatible = \"brcm,bcm6345-uart\";\n\t\t\treg = <0x10000120 0x18>;\n\n\t\t\tinterrupt-parent = <&periph_intc>;\n\t\t\tinterrupts = <BCM6328_IRQ_UART1>;\n\n\t\t\tclocks = <&periph_osc>;\n\t\t\tclock-names = \"periph\";\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tnflash: nand@10000200 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tcompatible = \"brcm,nand-bcm6368\",\n\t\t\t\t     \"brcm,brcmnand-v2.2\",\n\t\t\t\t     \"brcm,brcmnand\";\n\t\t\treg = <0x10000200 0x180>,\n\t\t\t      <0x10000400 0x200>,\n\t\t\t      <0x10000070 0x10>;\n\t\t\treg-names = \"nand\",\n\t\t\t\t    \"nand-cache\",\n\t\t\t\t    \"nand-int-base\";\n\n\t\t\tinterrupt-parent = <&periph_intc>;\n\t\t\tinterrupts = <BCM6328_IRQ_NAND>;\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tleds: led-controller@10000800 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tcompatible = \"brcm,bcm6328-leds\";\n\t\t\treg = <0x10000800 0x24>;\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\thsspi: spi@10001000 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tcompatible = \"brcm,bcm6328-hsspi\";\n\t\t\treg = <0x10001000 0x600>;\n\n\t\t\tinterrupt-parent = <&periph_intc>;\n\t\t\tinterrupts = <BCM6328_IRQ_HSSPI>;\n\n\t\t\tclocks = <&periph_clk BCM6328_CLK_HSSPI>,\n\t\t\t\t <&hsspi_osc>;\n\t\t\tclock-names = \"hsspi\",\n\t\t\t\t      \"pll\";\n\n\t\t\tresets = <&periph_rst BCM6328_RST_SPI>;\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tserdes_cntl: syscon@10001800 {\n\t\t\tcompatible = \"syscon\";\n\t\t\treg = <0x10001800 0x4>;\n\t\t\tnative-endian;\n\t\t};\n\n\t\tperiph_pwr: power-controller@10001848 {\n\t\t\tcompatible = \"brcm,bcm6328-power-controller\";\n\t\t\treg = <0x10001848 0x4>;\n\n\t\t\t#power-domain-cells = <1>;\n\t\t};\n\n\t\tehci: usb@10002500 {\n\t\t\tcompatible = \"brcm,bcm6328-ehci\", \"generic-ehci\";\n\t\t\treg = <0x10002500 0x100>;\n\t\t\tbig-endian;\n\t\t\tspurious-oc;\n\n\t\t\tinterrupt-parent = <&periph_intc>;\n\t\t\tinterrupts = <BCM6328_IRQ_EHCI>;\n\n\t\t\tphys = <&usbh 0>;\n\t\t\tphy-names = \"usb\";\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tohci: usb@10002600 {\n\t\t\tcompatible = \"brcm,bcm6328-ohci\", \"generic-ohci\";\n\t\t\treg = <0x10002600 0x100>;\n\t\t\tbig-endian;\n\t\t\tno-big-frame-no;\n\n\t\t\tinterrupt-parent = <&periph_intc>;\n\t\t\tinterrupts = <BCM6328_IRQ_OHCI>;\n\n\t\t\tphys = <&usbh 0>;\n\t\t\tphy-names = \"usb\";\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tusbh: usb-phy@10002700 {\n\t\t\tcompatible = \"brcm,bcm6328-usbh-phy\";\n\t\t\treg = <0x10002700 0x38>;\n\n\t\t\t#phy-cells = <1>;\n\n\t\t\tclocks = <&periph_clk BCM6328_CLK_USBH>;\n\t\t\tclock-names = \"usbh\";\n\n\t\t\tpower-domains = <&periph_pwr BCM6328_POWER_DOMAIN_USBH>;\n\t\t\tresets = <&periph_rst BCM6328_RST_USBH>;\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tethernet: ethernet@1000d800 {\n\t\t\tcompatible = \"brcm,bcm6328-enetsw\";\n\t\t\treg = <0x1000d800 0x80>,\n\t\t\t      <0x1000da00 0x80>,\n\t\t\t      <0x1000dc00 0x80>;\n\t\t\treg-names = \"dma\",\n\t\t\t\t    \"dma-channels\",\n\t\t\t\t    \"dma-sram\";\n\n\t\t\tinterrupt-parent = <&periph_intc>;\n\t\t\tinterrupts = <BCM6328_IRQ_ENETSW_RX_DMA0>,\n\t\t\t\t     <BCM6328_IRQ_ENETSW_TX_DMA0>;\n\t\t\tinterrupt-names = \"rx\",\n\t\t\t\t\t  \"tx\";\n\n\t\t\tclocks = <&periph_clk BCM6328_CLK_ROBOSW>;\n\n\t\t\tresets = <&periph_rst BCM6328_RST_ENETSW>,\n\t\t\t\t <&periph_rst BCM6328_RST_EPHY>;\n\n\t\t\tpower-domains = <&periph_pwr BCM6328_POWER_DOMAIN_ROBOSW>,\n\t\t\t\t\t<&periph_pwr BCM6328_POWER_DOMAIN_EPHY>;\n\n\t\t\tdma-rx = <0>;\n\t\t\tdma-tx = <1>;\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tswitch0: switch@10e00000 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tcompatible = \"brcm,bcm6328-switch\";\n\t\t\treg = <0x10e00000 0x8000>;\n\t\t\tbig-endian;\n\n\t\t\tports {\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\n\t\t\t\tport@8 {\n\t\t\t\t\treg = <8>;\n\t\t\t\t\tlabel = \"cpu\";\n\n\t\t\t\t\tphy-mode = \"internal\";\n\t\t\t\t\tethernet = <&ethernet>;\n\n\t\t\t\t\tfixed-link {\n\t\t\t\t\t\tspeed = <1000>;\n\t\t\t\t\t\tfull-duplex;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tmdio: mdio@10e000b0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tcompatible = \"brcm,bcm6368-mdio-mux\";\n\t\t\treg = <0x10e000b0 0x8>;\n\n\t\t\tmdio_int: mdio@0 {\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\t\t\t\treg = <0>;\n\n\t\t\t\tphy1: ethernet-phy@1 {\n\t\t\t\t\tcompatible = \"ethernet-phy-ieee802.3-c22\";\n\t\t\t\t\treg = <1>;\n\t\t\t\t};\n\n\t\t\t\tphy2: ethernet-phy@2 {\n\t\t\t\t\tcompatible = \"ethernet-phy-ieee802.3-c22\";\n\t\t\t\t\treg = <2>;\n\t\t\t\t};\n\n\t\t\t\tphy3: ethernet-phy@3 {\n\t\t\t\t\tcompatible = \"ethernet-phy-ieee802.3-c22\";\n\t\t\t\t\treg = <3>;\n\t\t\t\t};\n\n\t\t\t\tphy4: ethernet-phy@4 {\n\t\t\t\t\tcompatible = \"ethernet-phy-ieee802.3-c22\";\n\t\t\t\t\treg = <4>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tmdio_ext: mdio@1 {\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\t\t\t\treg = <1>;\n\t\t\t};\n\t\t};\n\n\t\tpcie: pcie@10e40000 {\n\t\t\tcompatible = \"brcm,bcm6328-pcie\";\n\t\t\treg = <0x10e40000 0x10000>;\n\t\t\t#address-cells = <3>;\n\t\t\t#size-cells = <2>;\n\n\t\t\tdevice_type = \"pci\";\n\t\t\tbus-range = <0x00 0x01>;\n\t\t\tranges = <0x2000000 0 0x10f00000 0x10f00000 0 0x100000>;\n\t\t\tlinux,pci-probe-only = <1>;\n\n\t\t\tinterrupt-parent = <&periph_intc>;\n\t\t\tinterrupts = <BCM6328_IRQ_PCIE_RC>;\n\n\t\t\tclocks = <&periph_clk BCM6328_CLK_PCIE>;\n\t\t\tclock-names = \"pcie\";\n\n\t\t\tresets = <&periph_rst BCM6328_RST_PCIE>,\n\t\t\t\t <&periph_rst BCM6328_RST_PCIE_EXT>,\n\t\t\t\t <&periph_rst BCM6328_RST_PCIE_CORE>,\n\t\t\t\t <&periph_rst BCM6328_RST_PCIE_HARD>;\n\t\t\treset-names = \"pcie\",\n\t\t\t\t      \"pcie-ext\",\n\t\t\t\t      \"pcie-core\",\n\t\t\t\t      \"pcie-hard\";\n\n\t\t\tpower-domains = <&periph_pwr BCM6328_POWER_DOMAIN_PCIE>;\n\n\t\t\tbrcm,serdes = <&serdes_cntl>;\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/bmips/dts/bcm6358-huawei-hg556a-b.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later\n\n#include \"bcm6358.dtsi\"\n\n/ {\n\tcompatible = \"huawei,hg556a-b\", \"brcm,bcm6358\";\n\tmodel = \"Huawei EchoLife HG556a (version B)\";\n\n\taliases {\n\t\tled-boot = &led_power_red;\n\t\tled-failsafe = &led_power_red;\n\t\tled-running = &led_power_red;\n\t\tled-upgrade = &led_power_red;\n\n\t\tled-dsl = &led_dsl_red;\n\t\tled-usb = &led_hspa_red;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <20>;\n\n\t\thelp {\n\t\t\tlabel = \"help\";\n\t\t\tgpios = <&gpio 8 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_HELP>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\twlan {\n\t\t\tlabel = \"wlan\";\n\t\t\tgpios = <&gpio 9 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WLAN>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\trestart {\n\t\t\tlabel = \"restart\";\n\t\t\tgpios = <&gpio 10 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_CONFIG>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled@0 {\n\t\t\tlabel = \"red:message\";\n\t\t\tgpios = <&gpio 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_hspa_red: led@1 {\n\t\t\tlabel = \"red:hspa\";\n\t\t\tgpios = <&gpio 1 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_dsl_red: led@2 {\n\t\t\tlabel = \"red:dsl\";\n\t\t\tgpios = <&gpio 2 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_power_red: led@3 {\n\t\t\tlabel = \"red:power\";\n\t\t\tgpios = <&gpio 3 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled@6 {\n\t\t\tlabel = \"all\";\n\t\t\tgpios = <&gpio 6 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\tled@12 {\n\t\t\tlabel = \"green:lan1\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled@13 {\n\t\t\tlabel = \"red:lan1\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled@15 {\n\t\t\tlabel = \"green:lan2\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled@22 {\n\t\t\tlabel = \"red:lan2\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled@23 {\n\t\t\tlabel = \"green:lan3\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled@26 {\n\t\t\tlabel = \"red:lan3\";\n\t\t\tgpios = <&gpio 26 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled@27 {\n\t\t\tlabel = \"green:lan4\";\n\t\t\tgpios = <&gpio 27 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled@28 {\n\t\t\tlabel = \"red:lan4\";\n\t\t\tgpios = <&gpio 28 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tath9k-fixup {\n\t\tcompatible = \"brcm,ath9k-fixup\";\n\t\treg = <0x30000000 0x8000000>;\n\n\t\tpci-dev = <1>;\n\n\t\tnvmem-cells = <&macaddr_cfe_6a0>;\n\t\tnvmem-cell-names = \"mac-address\";\n\t\tmac-address-increment = <1>;\n\n\t\tath,eeprom = <&cal_data 0x1e000>;\n\t\tath,endian-check;\n\t\tath,led-pin = <2>;\n\t\tath,led-active-high;\n\t};\n};\n\n&ehci {\n\tstatus = \"okay\";\n};\n\n&ohci {\n\tstatus = \"okay\";\n};\n\n&pci {\n\tstatus = \"okay\";\n};\n\n&pflash {\n\tstatus = \"okay\";\n\n\tpartitions {\n\t\tcompatible = \"fixed-partitions\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tcfe: partition@0 {\n\t\t\tlabel = \"cfe\";\n\t\t\treg = <0x000000 0x020000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@20000 {\n\t\t\tlabel = \"firmware\";\n\t\t\treg = <0x020000 0xec0000>;\n\t\t\tcompatible = \"brcm,bcm963xx-imagetag\";\n\t\t};\n\n\t\tcal_data: partition@ee0000 {\n\t\t\tlabel = \"cal_data\";\n\t\t\treg = <0xee0000 0x100000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@fe0000 {\n\t\t\tlabel = \"nvram\";\n\t\t\treg = <0xfe0000 0x020000>;\n\t\t};\n\t};\n};\n\n&uart0 {\n\tstatus = \"okay\";\n};\n\n&usbh {\n\tstatus = \"okay\";\n};\n\n&cfe {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_cfe_6a0: macaddr@6a0 {\n\t\treg = <0x6a0 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/bmips/dts/bcm6358.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later\n\n/dts-v1/;\n\n#include <dt-bindings/clock/bcm6358-clock.h>\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/interrupt-controller/bcm6358-interrupt-controller.h>\n#include <dt-bindings/reset/bcm6358-reset.h>\n\n/ {\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\tcompatible = \"brcm,bcm6358\";\n\n\taliases {\n\t\tpflash = &pflash;\n\t\tpinctrl = &pinctrl;\n\t\tserial0 = &uart0;\n\t\tserial1 = &uart1;\n\t\tspi0 = &lsspi;\n\t};\n\n\tchosen {\n\t\tbootargs = \"earlycon\";\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\tclocks {\n\t\tperiph_osc: periph-osc {\n\t\t\tcompatible = \"fixed-clock\";\n\n\t\t\t#clock-cells = <0>;\n\n\t\t\tclock-frequency = <50000000>;\n\t\t\tclock-output-names = \"periph\";\n\t\t};\n\t};\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tmips-hpt-frequency = <150000000>;\n\n\t\tcpu@0 {\n\t\t\tcompatible = \"brcm,bmips4350\", \"mips,mips4Kc\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\treg = <0>;\n\t\t};\n\n\t\tcpu@1 {\n\t\t\tcompatible = \"brcm,bmips4350\", \"mips,mips4Kc\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\treg = <1>;\n\t\t};\n\t};\n\n\tcpu_intc: interrupt-controller {\n\t\t#address-cells = <0>;\n\t\tcompatible = \"mti,cpu-interrupt-controller\";\n\n\t\tinterrupt-controller;\n\t\t#interrupt-cells = <1>;\n\t};\n\n\tmemory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0 0>;\n\t};\n\n\tpflash: nor@1e000000 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"cfi-flash\";\n\t\treg = <0x1e000000 0x2000000>;\n\t\tbank-width = <2>;\n\n\t\tstatus = \"disabled\";\n\t};\n\n\tubus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tcompatible = \"simple-bus\";\n\t\tranges;\n\n\t\tperiph_clk: clock-controller@fffe0004 {\n\t\t\tcompatible = \"brcm,bcm6358-clocks\";\n\t\t\treg = <0xfffe0004 0x4>;\n\t\t\t#clock-cells = <1>;\n\t\t};\n\n\t\tpll_cntl: syscon@fffe0008 {\n\t\t\tcompatible = \"syscon\", \"simple-mfd\";\n\t\t\treg = <0xfffe0008 0x4>;\n\t\t\tnative-endian;\n\n\t\t\tsyscon-reboot {\n\t\t\t\tcompatible = \"syscon-reboot\";\n\t\t\t\toffset = <0x0>;\n\t\t\t\tmask = <0x1>;\n\t\t\t};\n\t\t};\n\n\t\tperiph_intc: interrupt-controller@fffe000c {\n\t\t\t#address-cells = <1>;\n\t\t\tcompatible = \"brcm,bcm6345-l1-intc\";\n\t\t\treg = <0xfffe000c 0x8>,\n\t\t\t      <0xfffe0038 0x8>;\n\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <1>;\n\n\t\t\tinterrupt-parent = <&cpu_intc>;\n\t\t\tinterrupts = <2>, <3>;\n\t\t};\n\n\t\text_intc0: interrupt-controller@fffe0014 {\n\t\t\t#address-cells = <1>;\n\t\t\tcompatible = \"brcm,bcm6345-ext-intc\";\n\t\t\treg = <0xfffe0014 0x4>;\n\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <2>;\n\n\t\t\tinterrupts = <BCM6358_IRQ_EXT0>,\n\t\t\t\t     <BCM6358_IRQ_EXT1>,\n\t\t\t\t     <BCM6358_IRQ_EXT2>,\n\t\t\t\t     <BCM6358_IRQ_EXT3>;\n\t\t};\n\n\t\text_intc1: interrupt-controller@fffe001c {\n\t\t\t#address-cells = <1>;\n\t\t\tcompatible = \"brcm,bcm6345-ext-intc\";\n\t\t\treg = <0xfffe001c 0x4>;\n\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <2>;\n\n\t\t\tinterrupts = <BCM6358_IRQ_EXT4>,\n\t\t\t\t     <BCM6358_IRQ_EXT5>;\n\t\t};\n\n\t\tperiph_rst: reset-controller@fffe0034 {\n\t\t\tcompatible = \"brcm,bcm6345-reset\";\n\t\t\treg = <0xfffe0034 0x4>;\n\t\t\t#reset-cells = <1>;\n\t\t};\n\n\t\twdt: watchdog@fffe005c {\n\t\t\tcompatible = \"brcm,bcm7038-wdt\";\n\t\t\treg = <0xfffe005c 0xc>;\n\n\t\t\tclocks = <&periph_osc>;\n\n\t\t\ttimeout-sec = <30>;\n\t\t};\n\n\t\tgpio_cntl: syscon@fffe0080 {\n\t\t\tcompatible = \"brcm,bcm6358-gpio-sysctl\",\n\t\t\t\t     \"syscon\", \"simple-mfd\";\n\t\t\treg = <0xfffe0080 0x50>;\n\t\t\tranges = <0 0xfffe0080 0x80>;\n\t\t\tnative-endian;\n\n\t\t\tgpio: gpio@0 {\n\t\t\t\tcompatible = \"brcm,bcm6358-gpio\";\n\t\t\t\treg-names = \"dirout\", \"dat\";\n\t\t\t\treg = <0x0 0x8>, <0x8 0x8>;\n\n\t\t\t\tgpio-controller;\n\t\t\t\tgpio-ranges = <&pinctrl 0 0 40>;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t};\n\n\t\t\tpinctrl: pinctrl@18 {\n\t\t\t\tcompatible = \"brcm,bcm6358-pinctrl\";\n\t\t\t\treg = <0x18 0x4>;\n\n\t\t\t\tpinctrl_ebi_cs: ebi_cs-pins {\n\t\t\t\t\tfunction = \"ebi_cs\";\n\t\t\t\t\tgroups = \"ebi_cs_grp\";\n\t\t\t\t};\n\n\t\t\t\tpinctrl_uart1: uart1-pins {\n\t\t\t\t\tfunction = \"uart1\";\n\t\t\t\t\tgroups = \"uart1_grp\";\n\t\t\t\t};\n\n\t\t\t\tpinctrl_serial_led: serial_led-pins {\n\t\t\t\t\tfunction = \"serial_led\";\n\t\t\t\t\tgroups = \"serial_led_grp\";\n\t\t\t\t};\n\n\t\t\t\tpinctrl_legacy_led: legacy_led-pins {\n\t\t\t\t\tfunction = \"legacy_led\";\n\t\t\t\t\tgroups = \"legacy_led_grp\";\n\t\t\t\t};\n\n\t\t\t\tpinctrl_led: led-pins {\n\t\t\t\t\tfunction = \"led\";\n\t\t\t\t\tgroups = \"led_grp\";\n\t\t\t\t};\n\n\t\t\t\tpinctrl_spi_cs_23: spi_cs-pins {\n\t\t\t\t\tfunction = \"spi_cs\";\n\t\t\t\t\tgroups = \"spi_cs_grp\";\n\t\t\t\t};\n\n\t\t\t\tpinctrl_utopia: utopia-pins {\n\t\t\t\t\tfunction = \"utopia\";\n\t\t\t\t\tgroups = \"utopia_grp\";\n\t\t\t\t};\n\n\t\t\t\tpinctrl_pwm_syn_clk: pwm_syn_clk-pins {\n\t\t\t\t\tfunction = \"pwm_syn_clk\";\n\t\t\t\t\tgroups = \"pwm_syn_clk_grp\";\n\t\t\t\t};\n\n\t\t\t\tpinctrl_sys_irq: sys_irq-pins {\n\t\t\t\t\tfunction = \"sys_irq\";\n\t\t\t\t\tgroups = \"sys_irq_grp\";\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tleds: led-controller@fffe00d0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tcompatible = \"brcm,bcm6358-leds\";\n\t\t\treg = <0xfffe00d0 0x8>;\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tuart0: serial@fffe0100 {\n\t\t\tcompatible = \"brcm,bcm6345-uart\";\n\t\t\treg = <0xfffe0100 0x18>;\n\n\t\t\tinterrupt-parent = <&periph_intc>;\n\t\t\tinterrupts = <BCM6358_IRQ_UART0>;\n\n\t\t\tclocks = <&periph_osc>;\n\t\t\tclock-names = \"periph\";\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tuart1: serial@fffe0120 {\n\t\t\tcompatible = \"brcm,bcm6345-uart\";\n\t\t\treg = <0xfffe0120 0x18>;\n\n\t\t\tinterrupt-parent = <&periph_intc>;\n\t\t\tinterrupts = <BCM6358_IRQ_UART1>;\n\n\t\t\tclocks = <&periph_osc>;\n\t\t\tclock-names = \"periph\";\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tlsspi: spi@fffe0800 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tcompatible = \"brcm,bcm6358-spi\";\n\t\t\treg = <0xfffe0800 0x70c>;\n\n\t\t\tinterrupt-parent = <&periph_intc>;\n\t\t\tinterrupts = <BCM6358_IRQ_SPI>;\n\n\t\t\tclocks = <&periph_clk BCM6358_CLK_SPI>;\n\t\t\tclock-names = \"spi\";\n\n\t\t\tresets = <&periph_rst BCM6358_RST_SPI>;\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tpci: pci@fffe1000 {\n\t\t\tcompatible = \"brcm,bcm6348-pci\";\n\t\t\treg = <0xfffe1000 0x200>,\n\t\t\t      <0x08000000 0x10000>;\n\t\t\treg-names = \"pci\",\n\t\t\t\t    \"pci-io\";\n\t\t\t#address-cells = <3>;\n\t\t\t#size-cells = <2>;\n\n\t\t\tdevice_type = \"pci\";\n\t\t\tbus-range = <0x00 0x01>;\n\t\t\tranges = <0x2000000 0 0x30000000 0x30000000 0 0x8000000>;\n\t\t\tlinux,pci-probe-only = <1>;\n\n\t\t\tinterrupt-parent = <&periph_intc>;\n\t\t\tinterrupts = <BCM6358_IRQ_MPI>;\n\n\t\t\tresets = <&periph_rst BCM6358_RST_MPI>;\n\t\t\treset-names = \"pci\";\n\n\t\t\tbrcm,remap;\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tehci: usb@fffe1300 {\n\t\t\tcompatible = \"brcm,bcm6358-ehci\", \"generic-ehci\";\n\t\t\treg = <0xfffe1300 0x100>;\n\t\t\tbig-endian;\n\t\t\tspurious-oc;\n\n\t\t\tinterrupt-parent = <&periph_intc>;\n\t\t\tinterrupts = <BCM6358_IRQ_EHCI>;\n\n\t\t\tphys = <&usbh 0>;\n\t\t\tphy-names = \"usb\";\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tohci: usb@fffe1400 {\n\t\t\tcompatible = \"brcm,bcm6358-ohci\", \"generic-ohci\";\n\t\t\treg = <0xfffe1400 0x100>;\n\t\t\tbig-endian;\n\t\t\tno-big-frame-no;\n\n\t\t\tinterrupt-parent = <&periph_intc>;\n\t\t\tinterrupts = <BCM6358_IRQ_OHCI>;\n\n\t\t\tphys = <&usbh 0>;\n\t\t\tphy-names = \"usb\";\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tusbh: usb-phy@fffe1500 {\n\t\t\tcompatible = \"brcm,bcm6358-usbh-phy\";\n\t\t\treg = <0xfffe1500 0x38>;\n\n\t\t\t#phy-cells = <1>;\n\n\t\t\tresets = <&periph_rst BCM6358_RST_USBH>;\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/bmips/dts/bcm6362-netgear-dgnd3700-v2.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later\n\n#include \"bcm6362.dtsi\"\n\n/ {\n\tmodel = \"Netgear DGND3700 v2\";\n\tcompatible = \"netgear,dgnd3700-v2\", \"brcm,bcm6362\";\n\n\taliases {\n\t\tled-boot = &led_power_green;\n\t\tled-failsafe = &led_power_red;\n\t\tled-running = &led_power_green;\n\t\tled-upgrade = &led_power_green;\n\n\t\tled-dsl = &led_dsl_green;\n\t\tled-ethernet = &led_ethernet_green;\n\t\tled-internet = &led_internet_green;\n\t\tled-usb = &led_usb1_green;\n\t\tled-usb2 = &led_usb2_green;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <20>;\n\n\t\twlan {\n\t\t\tlabel = \"wlan\";\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WLAN>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio 25 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 31 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_dsl_green: led@28 {\n\t\t\tlabel = \"green:dsl\";\n\t\t\tgpios = <&gpio 28 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_power_red: led@34 {\n\t\t\tlabel = \"red:power\";\n\t\t\tgpios = <&gpio 34 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&ehci {\n\tstatus = \"okay\";\n};\n\n&ethernet {\n\tstatus = \"okay\";\n\n\tnvmem-cells = <&macaddr_cferom_6a0>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&leds {\n\tstatus = \"okay\";\n\n\tbrcm,serial-leds;\n\tbrcm,serial-dat-low;\n\tbrcm,serial-shift-inv;\n\tbrcm,serial-mux;\n\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_leds &pinctrl_serial_led>;\n\n\tled_internet_green: led@1 {\n\t\treg = <1>;\n\t\tactive-low;\n\t\tlabel = \"green:internet\";\n\t};\n\n\tled_power_green: led@8 {\n\t\treg = <8>;\n\t\tlabel = \"green:power\";\n\t};\n\n\tled@9 {\n\t\treg = <9>;\n\t\tactive-low;\n\t\tlabel = \"green:wps\";\n\t};\n\n\tled_usb1_green: led@10 {\n\t\treg = <10>;\n\t\tactive-low;\n\t\tlabel = \"green:usb1\";\n\t};\n\n\tled_usb2_green: led@11 {\n\t\treg = <11>;\n\t\tactive-low;\n\t\tlabel = \"green:usb2\";\n\t};\n\n\tled@12 {\n\t\treg = <12>;\n\t\tactive-low;\n\t\tlabel = \"amber:internet\";\n\t};\n\n\tled_ethernet_green: led@13 {\n\t\treg = <13>;\n\t\tactive-low;\n\t\tlabel = \"green:ethernet\";\n\t};\n\n\tled@14 {\n\t\treg = <14>;\n\t\tactive-low;\n\t\tlabel = \"amber:dsl\";\n\t};\n\n\tled@16 {\n\t\treg = <16>;\n\t\tactive-low;\n\t\tlabel = \"amber:usb1\";\n\t};\n\n\tled@17 {\n\t\treg = <17>;\n\t\tactive-low;\n\t\tlabel = \"amber:usb2\";\n\t};\n\n\tled@18 {\n\t\treg = <18>;\n\t\tactive-low;\n\t\tlabel = \"amber:ethernet\";\n\t};\n};\n\n&nflash {\n\tstatus = \"okay\";\n\n\tnandcs@0 {\n\t\tcompatible = \"brcm,nandcs\";\n\t\treg = <0>;\n\t\tnand-ecc-step-size = <512>;\n\t\tnand-ecc-strength = <15>;\n\t\tnand-on-flash-bbt;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tcferom: partition@0 {\n\t\t\t\tlabel = \"cferom\";\n\t\t\t\treg = <0x0000000 0x0004000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@4000 {\n\t\t\t\tcompatible = \"brcm,wfi\";\n\t\t\t\tlabel = \"wfi\";\n\t\t\t\treg = <0x0004000 0x1c7c000>;\n\t\t\t};\n\n\t\t\tpartition@1c80000 {\n\t\t\t\tlabel = \"flag\";\n\t\t\t\treg = <0x1c80000 0x0040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@1cc0000 {\n\t\t\t\tlabel = \"pcbasn\";\n\t\t\t\treg = <0x1cc0000 0x0040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@1d00000 {\n\t\t\t\tlabel = \"xxx\";\n\t\t\t\treg = <0x1d00000 0x0080000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@1d80000 {\n\t\t\t\tlabel = \"language_dev\";\n\t\t\t\treg = <0x1d80000 0x0040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@1dc0000 {\n\t\t\t\tlabel = \"scnvram\";\n\t\t\t\treg = <0x1dc0000 0x0100000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&ohci {\n\tstatus = \"okay\";\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pinctrl {\n\tpinctrl_leds: leds {\n\t\tfunction = \"led\";\n\t\tpins = \"gpio1\";\n\t};\n};\n\n&switch0 {\n\tports {\n\t\tport@4 {\n\t\t\treg = <4>;\n\t\t\tlabel = \"extsw\";\n\n\t\t\tphy-mode = \"rgmii\";\n\n\t\t\tfixed-link {\n\t\t\t\tspeed = <1000>;\n\t\t\t\tfull-duplex;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&uart0 {\n\tstatus = \"okay\";\n};\n\n&usbh {\n\tstatus = \"okay\";\n};\n\n&cferom {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_cferom_6a0: macaddr@6a0 {\n\t\treg = <0x6a0 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/bmips/dts/bcm6362.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later\n\n/dts-v1/;\n\n#include <dt-bindings/clock/bcm6362-clock.h>\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/interrupt-controller/bcm6362-interrupt-controller.h>\n#include <dt-bindings/reset/bcm6362-reset.h>\n#include <dt-bindings/soc/bcm6362-pm.h>\n\n/ {\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\tcompatible = \"brcm,bcm6362\";\n\n\taliases {\n\t\tnflash = &nflash;\n\t\tpinctrl = &pinctrl;\n\t\tserial0 = &uart0;\n\t\tserial1 = &uart1;\n\t\tspi0 = &lsspi;\n\t\tspi1 = &hsspi;\n\t};\n\n\tchosen {\n\t\tbootargs = \"earlycon\";\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\tclocks {\n\t\tperiph_osc: periph-osc {\n\t\t\tcompatible = \"fixed-clock\";\n\n\t\t\t#clock-cells = <0>;\n\n\t\t\tclock-frequency = <50000000>;\n\t\t\tclock-output-names = \"periph\";\n\t\t};\n\n\t\thsspi_osc: hsspi-osc {\n\t\t\tcompatible = \"fixed-clock\";\n\n\t\t\t#clock-cells = <0>;\n\n\t\t\tclock-frequency = <400000000>;\n\t\t\tclock-output-names = \"hsspi_osc\";\n\t\t};\n\t};\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tmips-hpt-frequency = <200000000>;\n\n\t\tcpu@0 {\n\t\t\tcompatible = \"brcm,bmips4350\", \"mips,mips4Kc\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\treg = <0>;\n\t\t};\n\n\t\tcpu@1 {\n\t\t\tcompatible = \"brcm,bmips4350\", \"mips,mips4Kc\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\treg = <1>;\n\t\t};\n\t};\n\n\tcpu_intc: interrupt-controller {\n\t\t#address-cells = <0>;\n\t\tcompatible = \"mti,cpu-interrupt-controller\";\n\n\t\tinterrupt-controller;\n\t\t#interrupt-cells = <1>;\n\t};\n\n\tmemory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0 0>;\n\t};\n\n\tubus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tcompatible = \"simple-bus\";\n\t\tranges;\n\n\t\tperiph_clk: clock-controller@10000004 {\n\t\t\tcompatible = \"brcm,bcm6362-clocks\";\n\t\t\treg = <0x10000004 0x4>;\n\t\t\t#clock-cells = <1>;\n\t\t};\n\n\t\tpll_cntl: syscon@10000008 {\n\t\t\tcompatible = \"syscon\", \"simple-mfd\";\n\t\t\treg = <0x10000008 0x4>;\n\t\t\tnative-endian;\n\n\t\t\tsyscon-reboot {\n\t\t\t\tcompatible = \"syscon-reboot\";\n\t\t\t\toffset = <0x0>;\n\t\t\t\tmask = <0x1>;\n\t\t\t};\n\t\t};\n\n\t\tperiph_rst: reset-controller@10000010 {\n\t\t\tcompatible = \"brcm,bcm6345-reset\";\n\t\t\treg = <0x10000010 0x4>;\n\t\t\t#reset-cells = <1>;\n\t\t};\n\n\t\text_intc: interrupt-controller@10000018 {\n\t\t\t#address-cells = <1>;\n\t\t\tcompatible = \"brcm,bcm6345-ext-intc\";\n\t\t\treg = <0x10000018 0x4>;\n\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <2>;\n\n\t\t\tinterrupts = <BCM6362_IRQ_EXT0>,\n\t\t\t\t     <BCM6362_IRQ_EXT1>,\n\t\t\t\t     <BCM6362_IRQ_EXT2>,\n\t\t\t\t     <BCM6362_IRQ_EXT3>;\n\t\t};\n\n\t\tperiph_intc: interrupt-controller@10000020 {\n\t\t\t#address-cells = <1>;\n\t\t\tcompatible = \"brcm,bcm6345-l1-intc\";\n\t\t\treg = <0x10000020 0x10>,\n\t\t\t      <0x10000030 0x10>;\n\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <1>;\n\n\t\t\tinterrupt-parent = <&cpu_intc>;\n\t\t\tinterrupts = <2>, <3>;\n\t\t};\n\n\t\twdt: watchdog@1000005c {\n\t\t\tcompatible = \"brcm,bcm7038-wdt\";\n\t\t\treg = <0x1000005c 0xc>;\n\n\t\t\tclocks = <&periph_osc>;\n\n\t\t\ttimeout-sec = <30>;\n\t\t};\n\n\t\tgpio_cntl: syscon@10000080 {\n\t\t\tcompatible = \"brcm,bcm6362-gpio-sysctl\",\n\t\t\t\t     \"syscon\", \"simple-mfd\";\n\t\t\treg = <0x10000080 0x80>;\n\t\t\tranges = <0 0x10000080 0x80>;\n\t\t\tnative-endian;\n\n\t\t\tgpio: gpio@0 {\n\t\t\t\tcompatible = \"brcm,bcm6362-gpio\";\n\t\t\t\treg-names = \"dirout\", \"dat\";\n\t\t\t\treg = <0x0 0x8>, <0x8 0x8>;\n\n\t\t\t\tgpio-controller;\n\t\t\t\tgpio-ranges = <&pinctrl 0 0 48>;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t};\n\n\t\t\tpinctrl: pinctrl@18 {\n\t\t\t\tcompatible = \"brcm,bcm6362-pinctrl\";\n\t\t\t\treg = <0x18 0x10>, <0x38 0x4>;\n\n\t\t\t\tpinctrl_usb_device_led: usb_device_led-pins {\n\t\t\t\t\tfunction = \"usb_device_led\";\n\t\t\t\t\tpins = \"gpio0\";\n\t\t\t\t};\n\n\t\t\t\tpinctrl_sys_irq: sys_irq-pins {\n\t\t\t\t\tfunction = \"sys_irq\";\n\t\t\t\t\tpins = \"gpio1\";\n\t\t\t\t};\n\n\t\t\t\tpinctrl_serial_led: serial_led-pins {\n\t\t\t\t\tpinctrl_serial_led_clk: serial_led_clk-pins {\n\t\t\t\t\t\tfunction = \"serial_led_clk\";\n\t\t\t\t\t\tpins = \"gpio2\";\n\t\t\t\t\t};\n\n\t\t\t\t\tpinctrl_serial_led_data: serial_led_data-pins {\n\t\t\t\t\t\tfunction = \"serial_led_data\";\n\t\t\t\t\t\tpins = \"gpio3\";\n\t\t\t\t\t};\n\t\t\t\t};\n\n\t\t\t\tpinctrl_robosw_led_data: robosw_led_data-pins {\n\t\t\t\t\tfunction = \"robosw_led_data\";\n\t\t\t\t\tpins = \"gpio4\";\n\t\t\t\t};\n\n\t\t\t\tpinctrl_robosw_led_clk: robosw_led_clk-pins {\n\t\t\t\t\tfunction = \"robosw_led_clk\";\n\t\t\t\t\tpins = \"gpio5\";\n\t\t\t\t};\n\n\t\t\t\tpinctrl_robosw_led0: robosw_led0-pins {\n\t\t\t\t\tfunction = \"robosw_led0\";\n\t\t\t\t\tpins = \"gpio6\";\n\t\t\t\t};\n\n\t\t\t\tpinctrl_robosw_led1: robosw_led1-pins {\n\t\t\t\t\tfunction = \"robosw_led1\";\n\t\t\t\t\tpins = \"gpio7\";\n\t\t\t\t};\n\n\t\t\t\tpinctrl_inet_led: inet_led-pins {\n\t\t\t\t\tfunction = \"inet_led\";\n\t\t\t\t\tpins = \"gpio8\";\n\t\t\t\t};\n\n\t\t\t\tpinctrl_spi_cs2: spi_cs2-pins {\n\t\t\t\t\tfunction = \"spi_cs2\";\n\t\t\t\t\tpins = \"gpio9\";\n\t\t\t\t};\n\n\t\t\t\tpinctrl_spi_cs3: spi_cs3-pins {\n\t\t\t\t\tfunction = \"spi_cs3\";\n\t\t\t\t\tpins = \"gpio10\";\n\t\t\t\t};\n\n\t\t\t\tpinctrl_ntr_pulse: ntr_pulse-pins {\n\t\t\t\t\tfunction = \"ntr_pulse\";\n\t\t\t\t\tpins = \"gpio11\";\n\t\t\t\t};\n\n\t\t\t\tpinctrl_uart1_scts: uart1_scts-pins {\n\t\t\t\t\tfunction = \"uart1_scts\";\n\t\t\t\t\tpins = \"gpio12\";\n\t\t\t\t};\n\n\t\t\t\tpinctrl_uart1_srts: uart1_srts-pins {\n\t\t\t\t\tfunction = \"uart1_srts\";\n\t\t\t\t\tpins = \"gpio13\";\n\t\t\t\t};\n\n\t\t\t\tpinctrl_uart1: uart1-pins {\n\t\t\t\t\tpinctrl_uart1_sdin: uart1_sdin-pins {\n\t\t\t\t\t\tfunction = \"uart1_sdin\";\n\t\t\t\t\t\tpins = \"gpio14\";\n\t\t\t\t\t};\n\n\t\t\t\t\tpinctrl_uart1_sdout: uart1_sdout-pins {\n\t\t\t\t\t\tfunction = \"uart1_sdout\";\n\t\t\t\t\t\tpins = \"gpio15\";\n\t\t\t\t\t};\n\t\t\t\t};\n\n\t\t\t\tpinctrl_adsl_spi: adsl_spi-pins {\n\t\t\t\t\tpinctrl_adsl_spi_miso: adsl_spi_miso-pins {\n\t\t\t\t\t\tfunction = \"adsl_spi_miso\";\n\t\t\t\t\t\tpins = \"gpio16\";\n\t\t\t\t\t};\n\n\t\t\t\t\tpinctrl_adsl_spi_mosi: adsl_spi_mosi-pins {\n\t\t\t\t\t\tfunction = \"adsl_spi_mosi\";\n\t\t\t\t\t\tpins = \"gpio17\";\n\t\t\t\t\t};\n\n\t\t\t\t\tpinctrl_adsl_spi_clk: adsl_spi_clk-pins {\n\t\t\t\t\t\tfunction = \"adsl_spi_clk\";\n\t\t\t\t\t\tpins = \"gpio18\";\n\t\t\t\t\t};\n\n\t\t\t\t\tpinctrl_adsl_spi_cs: adsl_spi_cs-pins {\n\t\t\t\t\t\tfunction = \"adsl_spi_cs\";\n\t\t\t\t\t\tpins = \"gpio19\";\n\t\t\t\t\t};\n\t\t\t\t};\n\n\t\t\t\tpinctrl_ephy0_led: ephy0_led-pins {\n\t\t\t\t\tfunction = \"ephy0_led\";\n\t\t\t\t\tpins = \"gpio20\";\n\t\t\t\t};\n\n\t\t\t\tpinctrl_ephy1_led: ephy1_led-pins {\n\t\t\t\t\tfunction = \"ephy1_led\";\n\t\t\t\t\tpins = \"gpio21\";\n\t\t\t\t};\n\n\t\t\t\tpinctrl_ephy2_led: ephy2_led-pins {\n\t\t\t\t\tfunction = \"ephy2_led\";\n\t\t\t\t\tpins = \"gpio22\";\n\t\t\t\t};\n\n\t\t\t\tpinctrl_ephy3_led: ephy3_led-pins {\n\t\t\t\t\tfunction = \"ephy3_led\";\n\t\t\t\t\tpins = \"gpio23\";\n\t\t\t\t};\n\n\t\t\t\tpinctrl_ext_irq0: ext_irq0-pins {\n\t\t\t\t\tfunction = \"ext_irq0\";\n\t\t\t\t\tpins = \"gpio24\";\n\t\t\t\t};\n\n\t\t\t\tpinctrl_ext_irq1: ext_irq1-pins {\n\t\t\t\t\tfunction = \"ext_irq1\";\n\t\t\t\t\tpins = \"gpio25\";\n\t\t\t\t};\n\n\t\t\t\tpinctrl_ext_irq2: ext_irq2-pins {\n\t\t\t\t\tfunction = \"ext_irq2\";\n\t\t\t\t\tpins = \"gpio26\";\n\t\t\t\t};\n\n\t\t\t\tpinctrl_ext_irq3: ext_irq3-pins {\n\t\t\t\t\tfunction = \"ext_irq3\";\n\t\t\t\t\tpins = \"gpio27\";\n\t\t\t\t};\n\n\t\t\t\tpinctrl_nand: nand-pins {\n\t\t\t\t\tfunction = \"nand\";\n\t\t\t\t\tgroup = \"nand_grp\";\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tuart0: serial@10000100 {\n\t\t\tcompatible = \"brcm,bcm6345-uart\";\n\t\t\treg = <0x10000100 0x18>;\n\n\t\t\tinterrupt-parent = <&periph_intc>;\n\t\t\tinterrupts = <BCM6362_IRQ_UART0>;\n\n\t\t\tclocks = <&periph_osc>;\n\t\t\tclock-names = \"periph\";\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tuart1: serial@10000120 {\n\t\t\tcompatible = \"brcm,bcm6345-uart\";\n\t\t\treg = <0x10000120 0x18>;\n\n\t\t\tinterrupt-parent = <&periph_intc>;\n\t\t\tinterrupts = <BCM6362_IRQ_UART1>;\n\n\t\t\tclocks = <&periph_osc>;\n\t\t\tclock-names = \"periph\";\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tnflash: nand@10000200 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tcompatible = \"brcm,nand-bcm6368\",\n\t\t\t\t     \"brcm,brcmnand-v2.2\",\n\t\t\t\t     \"brcm,brcmnand\";\n\t\t\treg = <0x10000200 0x180>,\n\t\t\t      <0x10000600 0x200>,\n\t\t\t      <0x10000070 0x10>;\n\t\t\treg-names = \"nand\",\n\t\t\t\t    \"nand-cache\",\n\t\t\t\t    \"nand-int-base\";\n\n\t\t\tinterrupt-parent = <&periph_intc>;\n\t\t\tinterrupts = <BCM6362_IRQ_NAND>;\n\n\t\t\tclocks = <&periph_clk BCM6362_CLK_NAND>;\n\t\t\tclock-names = \"nand\";\n\n\t\t\tpinctrl-names = \"default\";\n\t\t\tpinctrl-0 = <&pinctrl_nand>;\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tlsspi: spi@10000800 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tcompatible = \"brcm,bcm6358-spi\";\n\t\t\treg = <0x10000800 0x70c>;\n\n\t\t\tinterrupt-parent = <&periph_intc>;\n\t\t\tinterrupts = <BCM6362_IRQ_LSSPI>;\n\n\t\t\tclocks = <&periph_clk BCM6362_CLK_SPI>;\n\t\t\tclock-names = \"spi\";\n\n\t\t\tresets = <&periph_rst BCM6362_RST_SPI>;\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\thsspi: spi@10001000 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tcompatible = \"brcm,bcm6328-hsspi\";\n\t\t\treg = <0x10001000 0x600>;\n\n\t\t\tinterrupt-parent = <&periph_intc>;\n\t\t\tinterrupts = <BCM6362_IRQ_HSSPI>;\n\n\t\t\tclocks = <&periph_clk BCM6362_CLK_HSSPI>,\n\t\t\t\t <&hsspi_osc>;\n\t\t\tclock-names = \"hsspi\",\n\t\t\t\t      \"pll\";\n\n\t\t\tresets = <&periph_rst BCM6362_RST_SPI>;\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tserdes_cntl: syscon@10001804 {\n\t\t\tcompatible = \"syscon\";\n\t\t\treg = <0x10001804 0x4>;\n\t\t\tnative-endian;\n\t\t};\n\n\t\tperiph_pwr: power-controller@10001848 {\n\t\t\tcompatible = \"brcm,bcm6362-power-controller\";\n\t\t\treg = <0x10001848 0x4>;\n\t\t\t#power-domain-cells = <1>;\n\t\t};\n\n\t\tleds: led-controller@10001900 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tcompatible = \"brcm,bcm6328-leds\";\n\t\t\treg = <0x10001900 0x24>;\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tehci: usb@10002500 {\n\t\t\tcompatible = \"brcm,bcm6362-ehci\", \"generic-ehci\";\n\t\t\treg = <0x10002500 0x100>;\n\t\t\tbig-endian;\n\t\t\tspurious-oc;\n\n\t\t\tinterrupt-parent = <&periph_intc>;\n\t\t\tinterrupts = <BCM6362_IRQ_EHCI>;\n\n\t\t\tphys = <&usbh 0>;\n\t\t\tphy-names = \"usb\";\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tohci: usb@10002600 {\n\t\t\tcompatible = \"brcm,bcm6362-ohci\", \"generic-ohci\";\n\t\t\treg = <0x10002600 0x100>;\n\t\t\tbig-endian;\n\t\t\tno-big-frame-no;\n\n\t\t\tinterrupt-parent = <&periph_intc>;\n\t\t\tinterrupts = <BCM6362_IRQ_OHCI>;\n\n\t\t\tphys = <&usbh 0>;\n\t\t\tphy-names = \"usb\";\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tusbh: usb-phy@10002700 {\n\t\t\tcompatible = \"brcm,bcm6362-usbh-phy\";\n\t\t\treg = <0x10002700 0x38>;\n\n\t\t\t#phy-cells = <1>;\n\n\t\t\tclocks = <&periph_clk BCM6362_CLK_USBH>;\n\t\t\tclock-names = \"usbh\";\n\n\t\t\tpower-domains = <&periph_pwr BCM6362_POWER_DOMAIN_USBH>;\n\t\t\tresets = <&periph_rst BCM6362_RST_USBH>;\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tethernet: ethernet@1000d800 {\n\t\t\tcompatible = \"brcm,bcm6362-enetsw\";\n\t\t\treg = <0x1000d800 0x80>,\n\t\t\t      <0x1000da00 0x80>,\n\t\t\t      <0x1000dc00 0x80>;\n\t\t\treg-names = \"dma\",\n\t\t\t\t    \"dma-channels\",\n\t\t\t\t    \"dma-sram\";\n\n\t\t\tinterrupt-parent = <&periph_intc>;\n\t\t\tinterrupts = <BCM6362_IRQ_ENETSW_RX_DMA0>;\n\t\t\tinterrupt-names = \"rx\";\n\n\t\t\tclocks = <&periph_clk BCM6362_CLK_SWPKT_USB>,\n\t\t\t\t <&periph_clk BCM6362_CLK_SWPKT_SAR>,\n\t\t\t\t <&periph_clk BCM6362_CLK_ROBOSW>;\n\n\t\t\tresets = <&periph_rst BCM6362_RST_ENETSW>,\n\t\t\t\t <&periph_rst BCM6362_RST_EPHY>;\n\n\t\t\tpower-domains = <&periph_pwr BCM6362_POWER_DOMAIN_ROBOSW>,\n\t\t\t\t\t<&periph_pwr BCM6362_POWER_DOMAIN_GMII_PADS>;\n\n\t\t\tdma-rx = <0>;\n\t\t\tdma-tx = <1>;\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tswitch0: switch@10e00000 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tcompatible = \"brcm,bcm6328-switch\";\n\t\t\treg = <0x10e00000 0x8000>;\n\t\t\tbig-endian;\n\n\t\t\tports {\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\n\t\t\t\tport@8 {\n\t\t\t\t\treg = <8>;\n\t\t\t\t\tlabel = \"cpu\";\n\n\t\t\t\t\tphy-mode = \"internal\";\n\t\t\t\t\tethernet = <&ethernet>;\n\n\t\t\t\t\tfixed-link {\n\t\t\t\t\t\tspeed = <1000>;\n\t\t\t\t\t\tfull-duplex;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tmdio: mdio@10e000b0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tcompatible = \"brcm,bcm6368-mdio-mux\";\n\t\t\treg = <0x10e000b0 0x8>;\n\n\t\t\tmdio_int: mdio@0 {\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\t\t\t\treg = <0>;\n\n\t\t\t\tphy1: ethernet-phy@1 {\n\t\t\t\t\tcompatible = \"ethernet-phy-ieee802.3-c22\";\n\t\t\t\t\treg = <1>;\n\t\t\t\t};\n\n\t\t\t\tphy2: ethernet-phy@2 {\n\t\t\t\t\tcompatible = \"ethernet-phy-ieee802.3-c22\";\n\t\t\t\t\treg = <2>;\n\t\t\t\t};\n\n\t\t\t\tphy3: ethernet-phy@3 {\n\t\t\t\t\tcompatible = \"ethernet-phy-ieee802.3-c22\";\n\t\t\t\t\treg = <3>;\n\t\t\t\t};\n\n\t\t\t\tphy4: ethernet-phy@4 {\n\t\t\t\t\tcompatible = \"ethernet-phy-ieee802.3-c22\";\n\t\t\t\t\treg = <4>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tmdio_ext: mdio@1 {\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\t\t\t\treg = <1>;\n\t\t\t};\n\t\t};\n\n\t\tpcie: pcie@10e40000 {\n\t\t\tcompatible = \"brcm,bcm6328-pcie\";\n\t\t\treg = <0x10e40000 0x10000>;\n\t\t\t#address-cells = <3>;\n\t\t\t#size-cells = <2>;\n\n\t\t\tdevice_type = \"pci\";\n\t\t\tbus-range = <0x00 0x01>;\n\t\t\tranges = <0x2000000 0 0x10f00000 0x10f00000 0 0x100000>;\n\t\t\tlinux,pci-probe-only = <1>;\n\n\t\t\tinterrupt-parent = <&periph_intc>;\n\t\t\tinterrupts = <BCM6362_IRQ_PCIE_RC>;\n\n\t\t\tclocks = <&periph_clk BCM6362_CLK_PCIE>;\n\t\t\tclock-names = \"pcie\";\n\n\t\t\tresets = <&periph_rst BCM6362_RST_PCIE>,\n\t\t\t\t <&periph_rst BCM6362_RST_PCIE_EXT>,\n\t\t\t\t <&periph_rst BCM6362_RST_PCIE_CORE>;\n\t\t\treset-names = \"pcie\",\n\t\t\t\t      \"pcie-ext\",\n\t\t\t\t      \"pcie-core\";\n\n\t\t\tpower-domains = <&periph_pwr BCM6362_POWER_DOMAIN_PCIE>;\n\n\t\t\tbrcm,serdes = <&serdes_cntl>;\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/bmips/dts/bcm6368-comtrend-vr-3025u.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later\n\n#include \"bcm6368.dtsi\"\n\n/ {\n\tmodel = \"Comtrend VR-3025u\";\n\tcompatible = \"comtrend,vr-3025u\", \"brcm,bcm6368\";\n\n\taliases {\n\t\tled-boot = &led_power_green;\n\t\tled-failsafe = &led_power_red;\n\t\tled-running = &led_power_green;\n\t\tled-upgrade = &led_power_green;\n\n\t\tled-dsl = &led_dsl_green;\n\t\tled-internet = &led_internet_green;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 34 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_dsl_green: led@2 {\n\t\t\tlabel = \"green:dsl\";\n\t\t\tgpios = <&gpio 2 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_internet_green: led@5 {\n\t\t\tlabel = \"green:internet\";\n\t\t\tgpios = <&gpio 5 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tled_power_green: led@22 {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tled_power_red: led@24 {\n\t\t\tlabel = \"red:power\";\n\t\t\tgpios = <&gpio 24 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tled@31 {\n\t\t\tlabel = \"red:internet\";\n\t\t\tgpios = <&gpio 31 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n\n\tbcm43222-sprom {\n\t\tcompatible = \"brcm,bcm43222-sprom\";\n\n\t\tpci-bus = <0>;\n\t\tpci-dev = <1>;\n\n\t\tnvmem-cells = <&macaddr_cfe_6a0>;\n\t\tnvmem-cell-names = \"mac-address\";\n\t\tmac-address-increment = <1>;\n\n\t\tbrcm,sprom-fixups = <97 0xfeb3>,\n\t\t\t\t    <98 0x1618>,\n\t\t\t\t    <99 0xfab0>,\n\t\t\t\t    <113 0xfed1>,\n\t\t\t\t    <114 0x1609>,\n\t\t\t\t    <115 0xfad9>;\n\t};\n};\n\n&ehci {\n\tstatus = \"okay\";\n};\n\n&ethernet {\n\tstatus = \"okay\";\n\n\tnvmem-cells = <&macaddr_cfe_6a0>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&ohci {\n\tstatus = \"okay\";\n};\n\n&pci {\n\tstatus = \"okay\";\n};\n\n&pflash {\n\tstatus = \"okay\";\n\n\tpartitions {\n\t\tcompatible = \"fixed-partitions\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tcfe: partition@0 {\n\t\t\tlabel = \"CFE\";\n\t\t\treg = <0x0000000 0x0020000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@20000 {\n\t\t\tcompatible = \"brcm,bcm963xx-imagetag\";\n\t\t\tlabel = \"firmware\";\n\t\t\treg = <0x0020000 0x1fc0000>;\n\t\t};\n\n\t\tpartition@1fe0000 {\n\t\t\tlabel = \"nvram\";\n\t\t\treg = <0x1fe0000 0x020000>;\n\t\t};\n\t};\n};\n\n&pinctrl {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_ephy0_led &pinctrl_ephy1_led\n\t\t     &pinctrl_ephy2_led &pinctrl_ephy3_led>;\n};\n\n&switch0 {\n\tports {\n\t\tport@0 {\n\t\t\treg = <0>;\n\t\t\tlabel = \"lan1\";\n\n\t\t\tphy-handle = <&phy1>;\n\t\t};\n\n\t\tport@1 {\n\t\t\treg = <1>;\n\t\t\tlabel = \"lan2\";\n\n\t\t\tphy-handle = <&phy2>;\n\t\t};\n\n\t\tport@2 {\n\t\t\treg = <2>;\n\t\t\tlabel = \"lan3\";\n\n\t\t\tphy-handle = <&phy3>;\n\t\t};\n\n\t\tport@3 {\n\t\t\treg = <3>;\n\t\t\tlabel = \"lan4\";\n\n\t\t\tphy-handle = <&phy4>;\n\t\t};\n\t};\n};\n\n&uart0 {\n\tstatus = \"okay\";\n};\n\n&usbh {\n\tstatus = \"okay\";\n};\n\n&cfe {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_cfe_6a0: macaddr@6a0 {\n\t\treg = <0x6a0 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/bmips/dts/bcm6368.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later\n\n/dts-v1/;\n\n#include <dt-bindings/clock/bcm6368-clock.h>\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/interrupt-controller/bcm6368-interrupt-controller.h>\n#include <dt-bindings/reset/bcm6368-reset.h>\n\n/ {\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\tcompatible = \"brcm,bcm6368\";\n\n\taliases {\n\t\tnflash = &nflash;\n\t\tpflash = &pflash;\n\t\tpinctrl = &pinctrl;\n\t\tserial0 = &uart0;\n\t\tserial1 = &uart1;\n\t\tspi0 = &lsspi;\n\t};\n\n\tchosen {\n\t\tbootargs = \"earlycon\";\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\tclocks {\n\t\tperiph_osc: periph-osc {\n\t\t\tcompatible = \"fixed-clock\";\n\n\t\t\t#clock-cells = <0>;\n\n\t\t\tclock-frequency = <50000000>;\n\t\t\tclock-output-names = \"periph\";\n\t\t};\n\t};\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tmips-hpt-frequency = <200000000>;\n\n\t\tcpu@0 {\n\t\t\tcompatible = \"brcm,bmips4350\", \"mips,mips4Kc\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\treg = <0>;\n\t\t};\n\n\t\tcpu@1 {\n\t\t\tcompatible = \"brcm,bmips4350\", \"mips,mips4Kc\";\n\t\t\tdevice_type = \"cpu\";\n\t\t\treg = <1>;\n\t\t};\n\t};\n\n\tcpu_intc: interrupt-controller {\n\t\t#address-cells = <0>;\n\t\tcompatible = \"mti,cpu-interrupt-controller\";\n\n\t\tinterrupt-controller;\n\t\t#interrupt-cells = <1>;\n\t};\n\n\tmemory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0 0>;\n\t};\n\n\tubus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tcompatible = \"simple-bus\";\n\t\tranges;\n\n\t\tperiph_clk: clock-controller@10000004 {\n\t\t\tcompatible = \"brcm,bcm6368-clocks\";\n\t\t\treg = <0x10000004 0x4>;\n\t\t\t#clock-cells = <1>;\n\t\t};\n\n\t\tpll_cntl: syscon@10000008 {\n\t\t\tcompatible = \"syscon\", \"simple-mfd\";\n\t\t\treg = <0x10000008 0x4>;\n\t\t\tnative-endian;\n\n\t\t\tsyscon-reboot {\n\t\t\t\tcompatible = \"syscon-reboot\";\n\t\t\t\toffset = <0x0>;\n\t\t\t\tmask = <0x1>;\n\t\t\t};\n\t\t};\n\n\t\tperiph_rst: reset-controller@10000010 {\n\t\t\tcompatible = \"brcm,bcm6345-reset\";\n\t\t\treg = <0x10000010 0x4>;\n\t\t\t#reset-cells = <1>;\n\t\t};\n\n\t\text_intc0: interrupt-controller@10000018 {\n\t\t\t#address-cells = <1>;\n\t\t\tcompatible = \"brcm,bcm6345-ext-intc\";\n\t\t\treg = <0x10000018 0x4>;\n\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <2>;\n\n\t\t\tinterrupts = <BCM6368_IRQ_EXT0>,\n\t\t\t\t     <BCM6368_IRQ_EXT1>,\n\t\t\t\t     <BCM6368_IRQ_EXT2>,\n\t\t\t\t     <BCM6368_IRQ_EXT3>;\n\t\t};\n\n\t\text_intc1: interrupt-controller@1000001c {\n\t\t\t#address-cells = <1>;\n\t\t\tcompatible = \"brcm,bcm6345-ext-intc\";\n\t\t\treg = <0x1000001c 0x4>;\n\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <2>;\n\n\t\t\tinterrupts = <BCM6368_IRQ_EXT4>,\n\t\t\t\t     <BCM6368_IRQ_EXT5>;\n\t\t};\n\n\t\tperiph_intc: interrupt-controller@10000020 {\n\t\t\t#address-cells = <1>;\n\t\t\tcompatible = \"brcm,bcm6345-l1-intc\";\n\t\t\treg = <0x10000020 0x10>,\n\t\t\t      <0x10000030 0x10>;\n\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <1>;\n\n\t\t\tinterrupt-parent = <&cpu_intc>;\n\t\t\tinterrupts = <2>, <3>;\n\t\t};\n\n\t\twdt: watchdog@1000005c {\n\t\t\tcompatible = \"brcm,bcm7038-wdt\";\n\t\t\treg = <0x1000005c 0xc>;\n\n\t\t\tclocks = <&periph_osc>;\n\n\t\t\ttimeout-sec = <30>;\n\t\t};\n\n\t\tgpio_cntl: syscon@10000080 {\n\t\t\tcompatible = \"brcm,bcm6368-gpio-sysctl\",\n\t\t\t\t     \"syscon\", \"simple-mfd\";\n\t\t\treg = <0x10000080 0x80>;\n\t\t\tranges = <0 0x10000080 0x80>;\n\t\t\tnative-endian;\n\n\t\t\tgpio: gpio@0 {\n\t\t\t\tcompatible = \"brcm,bcm6368-gpio\";\n\t\t\t\treg-names = \"dirout\", \"dat\";\n\t\t\t\treg = <0x0 0x8>, <0x8 0x8>;\n\n\t\t\t\tgpio-controller;\n\t\t\t\tgpio-ranges = <&pinctrl 0 0 38>;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t};\n\n\t\t\tpinctrl: pinctrl@18 {\n\t\t\t\tcompatible = \"brcm,bcm6368-pinctrl\";\n\t\t\t\treg = <0x18 0x4>, <0x38 0x4>;\n\n\t\t\t\tpinctrl_analog_afe_0: analog_afe_0-pins {\n\t\t\t\t\tfunction = \"analog_afe_0\";\n\t\t\t\t\tpins = \"gpio0\";\n\t\t\t\t};\n\n\t\t\t\tpinctrl_analog_afe_1: analog_afe_1-pins {\n\t\t\t\t\tfunction = \"analog_afe_1\";\n\t\t\t\t\tpins = \"gpio1\";\n\t\t\t\t};\n\n\t\t\t\tpinctrl_sys_irq: sys_irq-pins {\n\t\t\t\t\tfunction = \"sys_irq\";\n\t\t\t\t\tpins = \"gpio2\";\n\t\t\t\t};\n\n\t\t\t\tpinctrl_serial_led: serial_led-pins {\n\t\t\t\t\tpinctrl_serial_led_data: serial_led_data-pins {\n\t\t\t\t\t\tfunction = \"serial_led_data\";\n\t\t\t\t\t\tpins = \"gpio3\";\n\t\t\t\t\t};\n\n\t\t\t\t\tpinctrl_serial_led_clk: serial_led_clk-pins {\n\t\t\t\t\t\tfunction = \"serial_led_clk\";\n\t\t\t\t\t\tpins = \"gpio4\";\n\t\t\t\t\t};\n\t\t\t\t};\n\n\t\t\t\tpinctrl_inet_led: inet_led-pins {\n\t\t\t\t\tfunction = \"inet_led\";\n\t\t\t\t\tpins = \"gpio5\";\n\t\t\t\t};\n\n\t\t\t\tpinctrl_ephy0_led: ephy0_led-pins {\n\t\t\t\t\tfunction = \"ephy0_led\";\n\t\t\t\t\tpins = \"gpio6\";\n\t\t\t\t};\n\n\t\t\t\tpinctrl_ephy1_led: ephy1_led-pins {\n\t\t\t\t\tfunction = \"ephy1_led\";\n\t\t\t\t\tpins = \"gpio7\";\n\t\t\t\t};\n\n\t\t\t\tpinctrl_ephy2_led: ephy2_led-pins {\n\t\t\t\t\tfunction = \"ephy2_led\";\n\t\t\t\t\tpins = \"gpio8\";\n\t\t\t\t};\n\n\t\t\t\tpinctrl_ephy3_led: ephy3_led-pins {\n\t\t\t\t\tfunction = \"ephy3_led\";\n\t\t\t\t\tpins = \"gpio9\";\n\t\t\t\t};\n\n\t\t\t\tpinctrl_robosw_led_data: robosw_led_data-pins {\n\t\t\t\t\tfunction = \"robosw_led_data\";\n\t\t\t\t\tpins = \"gpio10\";\n\t\t\t\t};\n\n\t\t\t\tpinctrl_robosw_led_clk: robosw_led_clk-pins {\n\t\t\t\t\tfunction = \"robosw_led_clk\";\n\t\t\t\t\tpins = \"gpio11\";\n\t\t\t\t};\n\n\t\t\t\tpinctrl_robosw_led0: robosw_led0-pins {\n\t\t\t\t\tfunction = \"robosw_led0\";\n\t\t\t\t\tpins = \"gpio12\";\n\t\t\t\t};\n\n\t\t\t\tpinctrl_robosw_led1: robosw_led1-pins {\n\t\t\t\t\tfunction = \"robosw_led1\";\n\t\t\t\t\tpins = \"gpio13\";\n\t\t\t\t};\n\n\t\t\t\tpinctrl_usb_device_led: usb_device_led-pins {\n\t\t\t\t\tfunction = \"usb_device_led\";\n\t\t\t\t\tpins = \"gpio14\";\n\t\t\t\t};\n\n\t\t\t\tpinctrl_pci: pci-pins {\n\t\t\t\t\tpinctrl_pci_req1: pci_req1-pins {\n\t\t\t\t\t\tfunction = \"pci_req1\";\n\t\t\t\t\t\tpins = \"gpio16\";\n\t\t\t\t\t};\n\n\t\t\t\t\tpinctrl_pci_gnt1: pci_gnt1-pins {\n\t\t\t\t\t\tfunction = \"pci_gnt1\";\n\t\t\t\t\t\tpins = \"gpio17\";\n\t\t\t\t\t};\n\n\t\t\t\t\tpinctrl_pci_intb: pci_intb-pins {\n\t\t\t\t\t\tfunction = \"pci_intb\";\n\t\t\t\t\t\tpins = \"gpio18\";\n\t\t\t\t\t};\n\n\t\t\t\t\tpinctrl_pci_req0: pci_req0-pins {\n\t\t\t\t\t\tfunction = \"pci_req0\";\n\t\t\t\t\t\tpins = \"gpio19\";\n\t\t\t\t\t};\n\n\t\t\t\t\tpinctrl_pci_gnt0: pci_gnt0-pins {\n\t\t\t\t\t\tfunction = \"pci_gnt0\";\n\t\t\t\t\t\tpins = \"gpio20\";\n\t\t\t\t\t};\n\t\t\t\t};\n\n\t\t\t\tpinctrl_pcmcia: pcmcia-pins {\n\t\t\t\t\tpinctrl_pcmcia_cd1: pcmcia_cd1-pins {\n\t\t\t\t\t\tfunction = \"pcmcia_cd1\";\n\t\t\t\t\t\tpins = \"gpio22\";\n\t\t\t\t\t};\n\n\t\t\t\t\tpinctrl_pcmcia_cd2: pcmcia_cd2-pins {\n\t\t\t\t\t\tfunction = \"pcmcia_cd2\";\n\t\t\t\t\t\tpins = \"gpio23\";\n\t\t\t\t\t};\n\n\t\t\t\t\tpinctrl_pcmcia_vs1: pcmcia_vs1-pins {\n\t\t\t\t\t\tfunction = \"pcmcia_vs1\";\n\t\t\t\t\t\tpins = \"gpio24\";\n\t\t\t\t\t};\n\n\t\t\t\t\tpinctrl_pcmcia_vs2: pcmcia_vs2-pins {\n\t\t\t\t\t\tfunction = \"pcmcia_vs2\";\n\t\t\t\t\t\tpins = \"gpio25\";\n\t\t\t\t\t};\n\t\t\t\t};\n\n\t\t\t\tpinctrl_ebi_cs2: ebi_cs2-pins {\n\t\t\t\t\tfunction = \"ebi_cs2\";\n\t\t\t\t\tpins = \"gpio26\";\n\t\t\t\t};\n\n\t\t\t\tpinctrl_ebi_cs3: ebi_cs3-pins {\n\t\t\t\t\tfunction = \"ebi_cs3\";\n\t\t\t\t\tpins = \"gpio27\";\n\t\t\t\t};\n\n\t\t\t\tpinctrl_spi_cs2: spi_cs2-pins {\n\t\t\t\t\tfunction = \"spi_cs2\";\n\t\t\t\t\tpins = \"gpio28\";\n\t\t\t\t};\n\n\t\t\t\tpinctrl_spi_cs3: spi_cs3-pins {\n\t\t\t\t\tfunction = \"spi_cs3\";\n\t\t\t\t\tpins = \"gpio29\";\n\t\t\t\t};\n\n\t\t\t\tpinctrl_spi_cs4: spi_cs4-pins {\n\t\t\t\t\tfunction = \"spi_cs4\";\n\t\t\t\t\tpins = \"gpio30\";\n\t\t\t\t};\n\n\t\t\t\tpinctrl_spi_cs5: spi_cs5-pins {\n\t\t\t\t\tfunction = \"spi_cs5\";\n\t\t\t\t\tpins = \"gpio31\";\n\t\t\t\t};\n\n\t\t\t\tpinctrl_uart1: uart1-pins {\n\t\t\t\t\tfunction = \"uart1\";\n\t\t\t\t\tgroup = \"uart1_grp\";\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tleds: led-controller@100000d0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tcompatible = \"brcm,bcm6358-leds\";\n\t\t\treg = <0x100000d0 0x8>;\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tuart0: serial@10000100 {\n\t\t\tcompatible = \"brcm,bcm6345-uart\";\n\t\t\treg = <0x10000100 0x18>;\n\n\t\t\tinterrupt-parent = <&periph_intc>;\n\t\t\tinterrupts = <BCM6368_IRQ_UART0>;\n\n\t\t\tclocks = <&periph_osc>;\n\t\t\tclock-names = \"periph\";\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tuart1: serial@10000120 {\n\t\t\tcompatible = \"brcm,bcm6345-uart\";\n\t\t\treg = <0x10000120 0x18>;\n\n\t\t\tinterrupt-parent = <&periph_intc>;\n\t\t\tinterrupts = <BCM6368_IRQ_UART1>;\n\n\t\t\tclocks = <&periph_osc>;\n\t\t\tclock-names = \"periph\";\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tnflash: nand@10000200 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tcompatible = \"brcm,nand-bcm6368\",\n\t\t\t\t     \"brcm,brcmnand-v2.1\",\n\t\t\t\t     \"brcm,brcmnand\";\n\t\t\treg = <0x10000200 0x180>,\n\t\t\t      <0x10000600 0x200>,\n\t\t\t      <0x10000070 0x10>;\n\t\t\treg-names = \"nand\",\n\t\t\t\t    \"nand-cache\",\n\t\t\t\t    \"nand-int-base\";\n\n\t\t\tinterrupt-parent = <&periph_intc>;\n\t\t\tinterrupts = <BCM6368_IRQ_NAND>;\n\n\t\t\tclocks = <&periph_clk BCM6368_CLK_NAND>;\n\t\t\tclock-names = \"nand\";\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tlsspi: spi@10000800 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tcompatible = \"brcm,bcm6358-spi\";\n\t\t\treg = <0x10000800 0x70c>;\n\n\t\t\tinterrupt-parent = <&periph_intc>;\n\t\t\tinterrupts = <BCM6368_IRQ_SPI>;\n\n\t\t\tclocks = <&periph_clk BCM6368_CLK_SPI>;\n\t\t\tclock-names = \"spi\";\n\n\t\t\tresets = <&periph_rst BCM6368_RST_SPI>;\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tpci: pci@10001000 {\n\t\t\tcompatible = \"brcm,bcm6348-pci\";\n\t\t\treg = <0x10001000 0x200>,\n\t\t\t      <0x08000000 0x10000>;\n\t\t\treg-names = \"pci\",\n\t\t\t\t    \"pci-io\";\n\t\t\t#address-cells = <3>;\n\t\t\t#size-cells = <2>;\n\n\t\t\tdevice_type = \"pci\";\n\t\t\tbus-range = <0x00 0x01>;\n\t\t\tranges = <0x2000000 0 0x30000000 0x30000000 0 0x8000000>;\n\t\t\tlinux,pci-probe-only = <1>;\n\n\t\t\tinterrupt-parent = <&periph_intc>;\n\t\t\tinterrupts = <BCM6368_IRQ_MPI>;\n\n\t\t\tresets = <&periph_rst BCM6368_RST_MPI>;\n\t\t\treset-names = \"pci\";\n\n\t\t\tpinctrl-names = \"default\";\n\t\t\tpinctrl-0 = <&pinctrl_pci>;\n\n\t\t\tbrcm,remap;\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tehci: usb@10001500 {\n\t\t\tcompatible = \"brcm,bcm6368-ehci\", \"generic-ehci\";\n\t\t\treg = <0x10001500 0x100>;\n\t\t\tbig-endian;\n\t\t\tspurious-oc;\n\n\t\t\tinterrupt-parent = <&periph_intc>;\n\t\t\tinterrupts = <BCM6368_IRQ_EHCI>;\n\n\t\t\tphys = <&usbh 0>;\n\t\t\tphy-names = \"usb\";\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tohci: usb@10001600 {\n\t\t\tcompatible = \"brcm,bcm6368-ohci\", \"generic-ohci\";\n\t\t\treg = <0x10001600 0x100>;\n\t\t\tbig-endian;\n\t\t\tno-big-frame-no;\n\n\t\t\tinterrupt-parent = <&periph_intc>;\n\t\t\tinterrupts = <BCM6368_IRQ_OHCI>;\n\n\t\t\tphys = <&usbh 0>;\n\t\t\tphy-names = \"usb\";\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tusbh: usb-phy@10001700 {\n\t\t\tcompatible = \"brcm,bcm6368-usbh-phy\";\n\t\t\treg = <0x10001700 0x38>;\n\n\t\t\t#phy-cells = <1>;\n\n\t\t\tclocks = <&periph_clk BCM6368_CLK_USBH>;\n\t\t\tclock-names = \"usbh\";\n\n\t\t\tresets = <&periph_rst BCM6368_RST_USBH>;\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\trandom: rng@10004180 {\n\t\t\tcompatible = \"brcm,bcm6368-rng\";\n\t\t\treg = <0x10004180 0x14>;\n\n\t\t\tclocks = <&periph_clk BCM6368_CLK_IPSEC>;\n\t\t\tclock-names = \"ipsec\";\n\n\t\t\tresets = <&periph_rst BCM6368_RST_IPSEC>;\n\t\t};\n\n\t\tethernet: ethernet@10006800 {\n\t\t\tcompatible = \"brcm,bcm6368-enetsw\";\n\t\t\treg = <0x10006800 0x80>,\n\t\t\t      <0x10006a00 0x80>,\n\t\t\t      <0x10006c00 0x80>;\n\t\t\treg-names = \"dma\",\n\t\t\t\t    \"dma-channels\",\n\t\t\t\t    \"dma-sram\";\n\n\t\t\tinterrupt-parent = <&periph_intc>;\n\t\t\tinterrupts = <BCM6368_IRQ_ENETSW_RX_DMA0>,\n\t\t\t\t     <BCM6368_IRQ_ENETSW_TX_DMA0>;\n\t\t\tinterrupt-names = \"rx\",\n\t\t\t\t\t  \"tx\";\n\n\t\t\tclocks = <&periph_clk BCM6368_CLK_SWPKT_USB>,\n\t\t\t\t <&periph_clk BCM6368_CLK_SWPKT_SAR>,\n\t\t\t\t <&periph_clk BCM6368_CLK_ROBOSW>;\n\n\t\t\tresets = <&periph_rst BCM6368_RST_SWITCH>,\n\t\t\t\t <&periph_rst BCM6368_RST_EPHY>;\n\n\t\t\tdma-rx = <0>;\n\t\t\tdma-tx = <1>;\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tswitch0: switch@10f00000 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tcompatible = \"brcm,bcm6328-switch\";\n\t\t\treg = <0x10f00000 0x8000>;\n\t\t\tbig-endian;\n\n\t\t\tports {\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\n\t\t\t\tport@8 {\n\t\t\t\t\treg = <8>;\n\t\t\t\t\tlabel = \"cpu\";\n\n\t\t\t\t\tphy-mode = \"internal\";\n\t\t\t\t\tethernet = <&ethernet>;\n\n\t\t\t\t\tfixed-link {\n\t\t\t\t\t\tspeed = <1000>;\n\t\t\t\t\t\tfull-duplex;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tmdio: mdio@10f000b0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tcompatible = \"brcm,bcm6368-mdio-mux\";\n\t\t\treg = <0x10f000b0 0x8>;\n\n\t\t\tmdio_int: mdio@0 {\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\t\t\t\treg = <0>;\n\n\t\t\t\tphy1: ethernet-phy@1 {\n\t\t\t\t\tcompatible = \"ethernet-phy-ieee802.3-c22\";\n\t\t\t\t\treg = <1>;\n\t\t\t\t};\n\n\t\t\t\tphy2: ethernet-phy@2 {\n\t\t\t\t\tcompatible = \"ethernet-phy-ieee802.3-c22\";\n\t\t\t\t\treg = <2>;\n\t\t\t\t};\n\n\t\t\t\tphy3: ethernet-phy@3 {\n\t\t\t\t\tcompatible = \"ethernet-phy-ieee802.3-c22\";\n\t\t\t\t\treg = <3>;\n\t\t\t\t};\n\n\t\t\t\tphy4: ethernet-phy@4 {\n\t\t\t\t\tcompatible = \"ethernet-phy-ieee802.3-c22\";\n\t\t\t\t\treg = <4>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tmdio_ext: mdio@1 {\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\t\t\t\treg = <1>;\n\t\t\t};\n\t\t};\n\t};\n\n\tpflash: nor@18000000 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"cfi-flash\";\n\t\treg = <0x18000000 0x2000000>;\n\t\tbank-width = <2>;\n\n\t\tstatus = \"disabled\";\n\t};\n};\n"
  },
  {
    "path": "target/linux/bmips/files/arch/mips/bmips/ath9k-fixup.c",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later\n/*\n * ATH9K Fixup Driver\n *\n * Copyright (C) 2020 Álvaro Fernández Rojas <noltari@gmail.com>\n * Copyright (C) 2014 Jonas Gorski <jonas.gorski@gmail.com>\n * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>\n * Copyright (C) 2008 Florian Fainelli <f.fainelli@gmail.com>\n */\n\n#include <linux/delay.h>\n#include <linux/etherdevice.h>\n#include <linux/init.h>\n#include <linux/kernel.h>\n#include <linux/mtd/mtd.h>\n#include <linux/of_net.h>\n#include <linux/of_platform.h>\n#include <linux/pci.h>\n#include <linux/types.h>\n#include <linux/ath9k_platform.h>\n\n#define ATH9K_MAX_FIXUPS\t2\n\n#define ATH9K_DEF_LED_PIN\t-1\n#define ATH9K_DEF_PCI_DEV\t255\n\nstruct ath9k_fixup {\n\tstruct device *dev;\n\tstruct resource *mem_res;\n\tu32 pci_dev;\n\tu8 mac[ETH_ALEN];\n\tstruct ath9k_platform_data pdata;\n};\n\nstatic int ath9k_num_fixups;\nstatic struct ath9k_fixup *ath9k_fixups[ATH9K_MAX_FIXUPS];\n\nstatic void ath9k_pci_fixup(struct pci_dev *dev)\n{\n\tvoid __iomem *mem;\n\tstruct ath9k_fixup *priv = NULL;\n\tstruct ath9k_platform_data *pdata = NULL;\n\tstruct pci_dev *bridge = pci_upstream_bridge(dev);\n\tu16 *cal_data = NULL;\n\tu16 cmd;\n\tu32 bar0;\n\tu32 val;\n\tunsigned i;\n\n\tfor (i = 0; i < ath9k_num_fixups; i++) {\n\t\tif (ath9k_fixups[i]->pci_dev != PCI_SLOT(dev->devfn))\n\t\t\tcontinue;\n\n\t\tpriv = ath9k_fixups[i];\n\t\tcal_data = priv->pdata.eeprom_data;\n\t\tpdata = &priv->pdata;\n\t\tbreak;\n\t}\n\n\tif (cal_data == NULL)\n\t\treturn;\n\n\tif (*cal_data != 0xa55a) {\n\t\tpr_err(\"pci %s: invalid calibration data\\n\", pci_name(dev));\n\t\treturn;\n\t}\n\n\tpr_info(\"pci %s: fixup device configuration\\n\", pci_name(dev));\n\n\tval = priv->mem_res->start;\n\tmem = ioremap(priv->mem_res->start, resource_size(priv->mem_res));\n\tif (!mem) {\n\t\tpr_err(\"pci %s: ioremap error\\n\", pci_name(dev));\n\t\treturn;\n\t}\n\n\tif (bridge)\n\t\tpci_enable_device(bridge);\n\n\tpci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &bar0);\n\tpci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &bar0);\n\tpci_write_config_dword(dev, PCI_BASE_ADDRESS_0, val);\n\n\tpci_read_config_word(dev, PCI_COMMAND, &cmd);\n\tcmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;\n\tpci_write_config_word(dev, PCI_COMMAND, cmd);\n\n\t/* set offset to first reg address */\n\tcal_data += 3;\n\twhile(*cal_data != 0xffff) {\n\t\tu32 reg;\n\n\t\treg = *cal_data++;\n\t\tval = *cal_data++;\n\t\tval |= (*cal_data++) << 16;\n\n\t\twritel(val, mem + reg);\n\t\tudelay(100);\n\t}\n\n\tpci_read_config_dword(dev, PCI_VENDOR_ID, &val);\n\tdev->vendor = val & 0xffff;\n\tdev->device = (val >> 16) & 0xffff;\n\n\tpci_read_config_dword(dev, PCI_CLASS_REVISION, &val);\n\tdev->revision = val & 0xff;\n\tdev->class = val >> 8; /* upper 3 bytes */\n\n\tpci_read_config_word(dev, PCI_COMMAND, &cmd);\n\tcmd &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);\n\tpci_write_config_word(dev, PCI_COMMAND, cmd);\n\n\tpci_write_config_dword(dev, PCI_BASE_ADDRESS_0, bar0);\n\n\tif (bridge)\n\t\tpci_disable_device(bridge);\n\n\tiounmap(mem);\n\n\tdev->dev.platform_data = pdata;\n}\nDECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATHEROS, PCI_ANY_ID, ath9k_pci_fixup);\n\nstatic int ath9k_mtd_eeprom(struct ath9k_fixup *priv)\n{\n\tstruct device *dev = priv->dev;\n\tstruct device_node *node = dev->of_node;\n\tstruct device_node *mtd_np = NULL;\n\tstruct mtd_info *the_mtd;\n\tphandle phandle;\n\tsize_t eeprom_readlen;\n\tconst char *part;\n\tconst __be32 *list;\n\tint ret, i;\n\n\tlist = of_get_property(node, \"ath,eeprom\", &i);\n\tif (!list || (i != (2 * sizeof(*list))))\n\t\treturn -ENODEV;\n\n\tphandle = be32_to_cpup(list++);\n\tif (phandle)\n\t\tmtd_np = of_find_node_by_phandle(phandle);\n\tif (!mtd_np)\n\t\treturn -ENODEV;\n\n\tpart = of_get_property(mtd_np, \"label\", NULL);\n\tif (!part)\n\t\tpart = mtd_np->name;\n\n\tthe_mtd = get_mtd_device_nm(part);\n\tif (IS_ERR(the_mtd))\n\t\treturn -ENODEV;\n\n\tret = mtd_read(the_mtd, be32_to_cpup(list),\n\t\t       ATH9K_PLAT_EEP_MAX_WORDS * sizeof(u16),\n\t\t       &eeprom_readlen, (void *) priv->pdata.eeprom_data);\n\tput_mtd_device(the_mtd);\n\tif (ret)\n\t\treturn ret;\n\n\treturn 0;\n}\n\nstatic int ath9k_fixup_probe(struct platform_device *pdev)\n{\n\tstruct device *dev = &pdev->dev;\n\tstruct device_node *node = dev->of_node;\n\tstruct ath9k_fixup *priv;\n\tstruct resource *res;\n\tint ret;\n\n\tif (ath9k_num_fixups >= ATH9K_MAX_FIXUPS)\n\t\treturn -ENOMEM;\n\n\tres = platform_get_resource(pdev, IORESOURCE_MEM, 0);\n\tif (!res)\n\t\treturn -EINVAL;\n\n\tpriv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);\n\tif (!priv)\n\t\treturn -ENOMEM;\n\n\tpriv->dev = dev;\n\tpriv->mem_res = res;\n\n\tret = of_property_read_u32(node, \"pci-dev\", &priv->pci_dev);\n\tif (ret)\n\t\tpriv->pci_dev = ATH9K_DEF_PCI_DEV;\n\n\tret = ath9k_mtd_eeprom(priv);\n\tif (ret)\n\t\treturn ret;\n\n\tpriv->pdata.endian_check = of_property_read_bool(node,\n\t\t\"ath,endian-check\");\n\tret = of_property_read_s32(node, \"ath,led-pin\", &priv->pdata.led_pin);\n\tif (ret)\n\t\tpriv->pdata.led_pin = ATH9K_DEF_LED_PIN;\n\tpriv->pdata.led_active_high = of_property_read_bool(node,\n\t\t\"ath,led-active-high\");\n\n\tof_get_mac_address(node, priv->mac);\n\tif (is_valid_ether_addr(priv->mac)) {\n\t\tdev_info(dev, \"mtd mac %pM\\n\", priv->mac);\n\t} else {\n\t\trandom_ether_addr(priv->mac);\n\t\tdev_info(dev, \"random mac %pM\\n\", priv->mac);\n\t}\n\n\tpriv->pdata.macaddr = priv->mac;\n\n\tath9k_fixups[ath9k_num_fixups] = priv;\n\tath9k_num_fixups++;\n\n\treturn 0;\n}\n\nstatic const struct of_device_id ath9k_fixup_of_match[] = {\n\t{ .compatible = \"brcm,ath9k-fixup\" },\n\t{ /* sentinel */ }\n};\n\nstatic struct platform_driver ath9k_fixup_driver = {\n\t.probe = ath9k_fixup_probe,\n\t.driver\t= {\n\t\t.name = \"ath9k-fixup\",\n\t\t.of_match_table = ath9k_fixup_of_match,\n\t},\n};\n\nint __init ath9k_fixup_init(void)\n{\n\tint ret = platform_driver_register(&ath9k_fixup_driver);\n\tif (ret)\n\t\tpr_err(\"ath9k_fixup: Error registering platform driver!\\n\");\n\treturn ret;\n}\nlate_initcall(ath9k_fixup_init);\n"
  },
  {
    "path": "target/linux/bmips/files/arch/mips/bmips/b43-sprom.c",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later\n/*\n * B43 Fallback SPROM Driver\n *\n * Copyright (C) 2020 Álvaro Fernández Rojas <noltari@gmail.com>\n * Copyright (C) 2014 Jonas Gorski <jonas.gorski@gmail.com>\n * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>\n * Copyright (C) 2008 Florian Fainelli <f.fainelli@gmail.com>\n */\n\n#include <linux/bcma/bcma.h>\n#include <linux/etherdevice.h>\n#include <linux/init.h>\n#include <linux/kernel.h>\n#include <linux/mtd/mtd.h>\n#include <linux/of_net.h>\n#include <linux/of_platform.h>\n#include <linux/ssb/ssb.h>\n\nenum b43_sprom_type {\n\tB43_SPROM_SSB,\n\tB43_SPROM_BCMA,\n\tB43_SPROM_NUM\n};\n\nstruct b43_sprom_raw {\n\tu16 *map;\n\tsize_t size;\n\tu8 type;\n};\n\nstruct b43_sprom {\n\tstruct device *dev;\n\tstruct ssb_sprom sprom;\n\tu32 pci_bus;\n\tu32 pci_dev;\n\tu8 mac[ETH_ALEN];\n\tint devid_override;\n};\n\nstatic struct b43_sprom b43_sprom;\n\n#if defined (CONFIG_SSB_PCIHOST)\nstatic u16 bcm4306_sprom_map[] = {\n\t0x4001, 0x0000, 0x0453, 0x14e4, 0x4320, 0x8000, 0x0002, 0x0002,\n\t0x1000, 0x1800, 0x0000, 0x0000, 0xffff, 0xffff, 0xffff, 0xffff,\n\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n\t0xffff, 0xffff, 0xffff, 0xffff, 0x0000, 0xffff, 0xffff, 0xffff,\n\t0xffff, 0xffff, 0xffff, 0xffff, 0x0000, 0x0000, 0x0000, 0xffff,\n\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0x3034, 0x14d4,\n\t0xfa91, 0xfe60, 0xffff, 0xffff, 0x004c, 0xffff, 0xffff, 0xffff,\n\t0x003e, 0x0a49, 0xff02, 0x0000, 0xff10, 0xffff, 0xffff, 0x0002,\n};\n\nstruct b43_sprom_raw bcm4306_sprom = {\n\t.map = bcm4306_sprom_map,\n\t.size = ARRAY_SIZE(bcm4306_sprom_map),\n\t.type = B43_SPROM_SSB,\n};\n\nstatic u16 bcm4318_sprom_map[] = {\n\t0x2001, 0x0000, 0x0449, 0x14e4, 0x4318, 0x8000, 0x0002, 0x0000,\n\t0x1000, 0x1800, 0x0000, 0x0000, 0xffff, 0xffff, 0xffff, 0xffff,\n\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n\t0xffff, 0xffff, 0xffff, 0xffff, 0x0000, 0xffff, 0xffff, 0xffff,\n\t0xffff, 0xffff, 0xffff, 0xffff, 0x0000, 0x0000, 0x0000, 0xffff,\n\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0x3046, 0x15a7,\n\t0xfab0, 0xfe97, 0xffff, 0xffff, 0x0048, 0xffff, 0xffff, 0xffff,\n\t0x003e, 0xea49, 0xff02, 0x0000, 0xff08, 0xffff, 0xffff, 0x0002,\n};\n\nstruct b43_sprom_raw bcm4318_sprom = {\n\t.map = bcm4318_sprom_map,\n\t.size = ARRAY_SIZE(bcm4318_sprom_map),\n\t.type = B43_SPROM_SSB,\n};\n\nstatic u16 bcm4321_sprom_map[] = {\n\t0x3001, 0x0000, 0x046c, 0x14e4, 0x4328, 0x8000, 0x0002, 0x0000,\n\t0x1000, 0x1800, 0x0000, 0x0000, 0xffff, 0xffff, 0xffff, 0xffff,\n\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n\t0x5372, 0x0032, 0x4a01, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n\t0x0000, 0x0000, 0x0000, 0xffff, 0xffff, 0xffff, 0x0303, 0x0202,\n\t0xffff, 0x2728, 0x5b5b, 0x222b, 0x5b5b, 0x1927, 0x5b5b, 0x1e36,\n\t0x5b5b, 0x303c, 0x3030, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n\t0x3e4c, 0x0000, 0x0000, 0x0000, 0x0000, 0x7838, 0x3a34, 0x0000,\n\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n\t0x0000, 0x0000, 0x0000, 0xffff, 0xffff, 0xffff, 0xffff, 0x3e4c,\n\t0x0000, 0x0000, 0x0000, 0x0000, 0x7838, 0x3a34, 0x0000, 0x0000,\n\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n\t0x0000, 0x0000, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n\t0xffff, 0xffff, 0xffff, 0xffff, 0x0008, 0x0000, 0x0000, 0x0000,\n\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n\t0x0000, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n\t0xffff, 0xffff, 0xffff, 0x0004,\n};\n\nstruct b43_sprom_raw bcm4321_sprom = {\n\t.map = bcm4321_sprom_map,\n\t.size = ARRAY_SIZE(bcm4321_sprom_map),\n\t.type = B43_SPROM_SSB,\n};\n\nstatic u16 bcm4322_sprom_map[] = {\n\t0x3001, 0x0000, 0x04bc, 0x14e4, 0x432c, 0x8000, 0x0002, 0x0000,\n\t0x1730, 0x1800, 0x0000, 0x0000, 0xffff, 0xffff, 0xffff, 0xffff,\n\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n\t0x5372, 0x1209, 0x0200, 0x0000, 0x0400, 0x0000, 0x0000, 0x0000,\n\t0x0000, 0x0000, 0x0000, 0xffff, 0xffff, 0xffff, 0x0303, 0x0202,\n\t0xffff, 0x0033, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0x0301,\n\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n\t0x2048, 0xfe9a, 0x1571, 0xfabd, 0xffff, 0xffff, 0xffff, 0xffff,\n\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n\t0x2048, 0xfeb9, 0x159f, 0xfadd, 0xffff, 0xffff, 0xffff, 0xffff,\n\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n\t0x0000, 0x0000, 0x0000, 0x3333, 0x5555, 0xffff, 0xffff, 0xffff,\n\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n\t0xffff, 0xffff, 0xffff, 0x0008,\n};\n\nstruct b43_sprom_raw bcm4322_sprom = {\n\t.map = bcm4322_sprom_map,\n\t.size = ARRAY_SIZE(bcm4322_sprom_map),\n\t.type = B43_SPROM_SSB,\n};\n\nstatic u16 bcm43222_sprom_map[] = {\n\t0x2001, 0x0000, 0x04d4, 0x14e4, 0x4351, 0x8000, 0x0002, 0x0000,\n\t0x1730, 0x1800, 0x0000, 0x0000, 0xffff, 0xffff, 0xffff, 0xffff,\n\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n\t0x5372, 0x2305, 0x0200, 0x0000, 0x2400, 0x0000, 0x0000, 0x0000,\n\t0x0000, 0x0000, 0x0000, 0xffff, 0xffff, 0xffff, 0x0303, 0x0202,\n\t0xffff, 0x0033, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0x0325,\n\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n\t0x204c, 0xfea6, 0x1717, 0xfa6d, 0xffff, 0xffff, 0xffff, 0xffff,\n\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n\t0x204c, 0xfeb8, 0x167c, 0xfa9e, 0xffff, 0xffff, 0xffff, 0xffff,\n\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n\t0x0000, 0x3333, 0x3333, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n\t0x0000, 0x3333, 0x3333, 0x3333, 0x3333, 0x3333, 0x3333, 0x3333,\n\t0x3333, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n\t0x0000, 0x0000, 0x0000, 0x0004, 0x0000, 0xffff, 0xffff, 0xffff,\n\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n\t0xffff, 0xffff, 0xffff, 0x0008,\n};\n\nstruct b43_sprom_raw bcm43222_sprom = {\n\t.map = bcm43222_sprom_map,\n\t.size = ARRAY_SIZE(bcm43222_sprom_map),\n\t.type = B43_SPROM_SSB,\n};\n#endif /* CONFIG_SSB_PCIHOST */\n\n#if defined(CONFIG_BCMA_HOST_PCI)\nstatic u16 bcm4313_sprom_map[] = {\n\t0x2801, 0x0000, 0x0510, 0x14e4, 0x0078, 0xedbe, 0x0000, 0x2bc4,\n\t0x2a64, 0x2964, 0x2c64, 0x3ce7, 0x46ff, 0x47ff, 0x0c00, 0x0820,\n\t0x0030, 0x1002, 0x9f28, 0x5d44, 0x8080, 0x1d8f, 0x0032, 0x0100,\n\t0xdf00, 0x71f5, 0x8400, 0x0083, 0x8500, 0x2010, 0x0001, 0x0000,\n\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n\t0x0000, 0x0000, 0x1008, 0x0305, 0x0000, 0x0000, 0x0000, 0x0000,\n\t0x4727, 0x8000, 0x0002, 0x0000, 0x1f30, 0x1800, 0x0000, 0x0000,\n\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n\t0x5372, 0x1215, 0x2a00, 0x0800, 0x0800, 0x0000, 0x0000, 0x0000,\n\t0x0000, 0x0000, 0x0003, 0xffff, 0x88ff, 0xffff, 0x0003, 0x0202,\n\t0xffff, 0x0011, 0x007a, 0x0000, 0x0000, 0x0000, 0x0000, 0x0201,\n\t0x0000, 0x7800, 0x7c0a, 0x0398, 0x0008, 0x0000, 0x0000, 0x0000,\n\t0x0044, 0x1684, 0xfd0d, 0xff35, 0x0000, 0x0000, 0x0000, 0x0000,\n\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n\t0x0048, 0xfed2, 0x15d9, 0xfac6, 0x0000, 0x0000, 0x0000, 0x0000,\n\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n\t0x0000, 0x0000, 0x0000, 0x0008,\n};\n\nstruct b43_sprom_raw bcm4313_sprom = {\n\t.map = bcm4313_sprom_map,\n\t.size = ARRAY_SIZE(bcm4313_sprom_map),\n\t.type = B43_SPROM_BCMA,\n};\n\nstatic u16 bcm4331_sprom_map[] = {\n\t0x2801, 0x0000, 0x0525, 0x14e4, 0x0078, 0xedbe, 0x0000, 0x2bc4,\n\t0x2a64, 0x2964, 0x2c64, 0x3ce7, 0x46ff, 0x47ff, 0x0c00, 0x0820,\n\t0x0030, 0x1002, 0x9f28, 0x5d44, 0x8080, 0x1d8f, 0x0032, 0x0100,\n\t0xdf00, 0x71f5, 0x8400, 0x0083, 0x8500, 0x2010, 0x0001, 0xffff,\n\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n\t0xffff, 0xffff, 0x1010, 0x0005, 0xffff, 0xffff, 0xffff, 0xffff,\n\t0x4331, 0x8000, 0x0002, 0x0000, 0x1f30, 0x1800, 0x0000, 0x0000,\n\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n\t0x5372, 0x1104, 0x0200, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n\t0x0000, 0x0000, 0x0000, 0xffff, 0x88ff, 0xffff, 0x0707, 0x0202,\n\t0xff02, 0x0077, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0x0325,\n\t0x0325, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n\t0x2048, 0xfe56, 0x16f2, 0xfa44, 0x3e3c, 0x3c3c, 0xfe77, 0x1657,\n\t0xfa75, 0xffff, 0xffff, 0xffff, 0xfe76, 0x15da, 0xfa85, 0x0000,\n\t0x2048, 0xfe5c, 0x16b5, 0xfa56, 0x3e3c, 0x3c3c, 0xfe7c, 0x169d,\n\t0xfa6b, 0xffff, 0xffff, 0xffff, 0xfe7a, 0x1597, 0xfa97, 0x0000,\n\t0x2048, 0xfe68, 0x1734, 0xfa46, 0x3e3c, 0x3c3c, 0xfe7f, 0x15e4,\n\t0xfa94, 0xffff, 0xffff, 0xffff, 0xfe7d, 0x1582, 0xfa9f, 0x0000,\n\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n\t0x0000, 0x0000, 0x0000, 0x0000, 0xffff, 0xffff, 0xffff, 0xffff,\n\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n\t0xffff, 0xffff, 0xffff, 0x0009,\n};\n\nstruct b43_sprom_raw bcm4331_sprom = {\n\t.map = bcm4331_sprom_map,\n\t.size = ARRAY_SIZE(bcm4331_sprom_map),\n\t.type = B43_SPROM_BCMA,\n};\n\nstatic u16 bcm43131_sprom_map[] = {\n\t0x2801, 0x0000, 0x05f7, 0x14e4, 0x0070, 0xedbe, 0x1c00, 0x2bc4,\n\t0x2a64, 0x2964, 0x2c64, 0x3ce7, 0x46ff, 0x47ff, 0x0c00, 0x0820,\n\t0x0030, 0x1002, 0x9f28, 0x5d44, 0x8080, 0x1d8f, 0x0032, 0x0100,\n\t0xdf00, 0x71f5, 0x8400, 0x0083, 0x8500, 0x2010, 0x0001, 0x0000,\n\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n\t0x0000, 0x0000, 0x1008, 0x0305, 0x0000, 0x0000, 0x0000, 0x0000,\n\t0x43aa, 0x8000, 0x0002, 0x0000, 0x1f30, 0x1800, 0x0000, 0x0000,\n\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n\t0x5372, 0x1280, 0x0200, 0x0000, 0x8800, 0x0000, 0x0000, 0x0000,\n\t0x0000, 0x0000, 0x0003, 0xffff, 0x88ff, 0xffff, 0x0002, 0x0202,\n\t0xffff, 0x0022, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0415,\n\t0x0000, 0x7800, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n\t0x204c, 0xfe96, 0x192c, 0xfa15, 0x0000, 0x0000, 0x0000, 0x0000,\n\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n\t0x204c, 0xfe91, 0x1950, 0xfa0a, 0x0000, 0x0000, 0x0000, 0x0000,\n\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n\t0x0000, 0x4444, 0x4444, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n\t0x0000, 0x4444, 0x4444, 0x4444, 0x4444, 0x6666, 0x6666, 0x6666,\n\t0x6666, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0xffff, 0xffff, 0xffff,\n\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n\t0xffff, 0xffff, 0xffff, 0x0008,\n};\n\nstruct b43_sprom_raw bcm43131_sprom = {\n\t.map = bcm43131_sprom_map,\n\t.size = ARRAY_SIZE(bcm43131_sprom_map),\n\t.type = B43_SPROM_BCMA,\n};\n\nstatic u16 bcm43217_sprom_map[] = {\n\t0x2801, 0x0000, 0x05e9, 0x14e4, 0x0070, 0xedbe, 0x0000, 0x2bc4,\n\t0x2a64, 0x2964, 0x2c64, 0x3ce7, 0x46ff, 0x47ff, 0x0c00, 0x0820,\n\t0x0030, 0x1002, 0x9f28, 0x5d44, 0x8080, 0x1d8f, 0x0032, 0x0100,\n\t0xdf00, 0x71f5, 0x8400, 0x0083, 0x8500, 0x2010, 0x0001, 0x0000,\n\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n\t0x0000, 0x0000, 0x1008, 0x0305, 0x0000, 0x0000, 0x0000, 0x0000,\n\t0x43a9, 0x8000, 0x0002, 0x0000, 0x1f30, 0x1800, 0x0000, 0x0000,\n\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n\t0x5372, 0x1252, 0x0200, 0x0000, 0x9800, 0x0000, 0x0000, 0x0000,\n\t0x0000, 0x0000, 0x0003, 0xffff, 0x88ff, 0xffff, 0x0003, 0x0202,\n\t0xffff, 0x0033, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0415,\n\t0x0000, 0x7800, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n\t0x204c, 0xfe96, 0x192c, 0xfa15, 0x0000, 0x0000, 0x0000, 0x0000,\n\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n\t0x204c, 0xfe91, 0x1950, 0xfa0a, 0x0000, 0x0000, 0x0000, 0x0000,\n\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n\t0x0000, 0x4444, 0x4444, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n\t0x0000, 0x4444, 0x4444, 0x4444, 0x4444, 0x6666, 0x6666, 0x6666,\n\t0x6666, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0xffff, 0xffff, 0xffff,\n\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n\t0xffff, 0xffff, 0xffff, 0x7a08,\n};\n\nstruct b43_sprom_raw bcm43217_sprom = {\n\t.map = bcm43217_sprom_map,\n\t.size = ARRAY_SIZE(bcm43217_sprom_map),\n\t.type = B43_SPROM_BCMA,\n};\n\nstatic u16 bcm43225_sprom_map[] = {\n\t0x2801, 0x0000, 0x04da, 0x14e4, 0x0078, 0xedbe, 0x0000, 0x2bc4,\n\t0x2a64, 0x2964, 0x2c64, 0x3ce7, 0x46ff, 0x47ff, 0x0c00, 0x0820,\n\t0x0030, 0x1002, 0x9f28, 0x5d44, 0x8080, 0x1d8f, 0x0032, 0x0100,\n\t0xdf00, 0x71f5, 0x8400, 0x0083, 0x8500, 0x2010, 0x0001, 0xffff,\n\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n\t0xffff, 0xffff, 0x1008, 0x0005, 0xffff, 0xffff, 0xffff, 0xffff,\n\t0x4357, 0x8000, 0x0002, 0x0000, 0x1f30, 0x1800, 0x0000, 0x0000,\n\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n\t0x5372, 0x1200, 0x0200, 0x0000, 0x1000, 0x0000, 0x0000, 0x0000,\n\t0x0000, 0x0000, 0x0000, 0x88ff, 0xffff, 0xffff, 0x0303, 0x0202,\n\t0xffff, 0x0033, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0x0325,\n\t0xffff, 0x7800, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n\t0x204e, 0xfead, 0x1611, 0xfa9a, 0xffff, 0xffff, 0xffff, 0xffff,\n\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n\t0x204e, 0xfec1, 0x1674, 0xfab2, 0xffff, 0xffff, 0xffff, 0xffff,\n\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n\t0x0000, 0x5555, 0x5555, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n\t0x0000, 0x5555, 0x7555, 0x5555, 0x7555, 0x5555, 0x7555, 0x5555,\n\t0x7555, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n\t0x0000, 0x0000, 0x0000, 0x0002, 0x0000, 0xffff, 0xffff, 0xffff,\n\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n\t0xffff, 0xffff, 0xffff, 0x0008,\n};\n\nstruct b43_sprom_raw bcm43225_sprom = {\n\t.map = bcm43225_sprom_map,\n\t.size = ARRAY_SIZE(bcm43225_sprom_map),\n\t.type = B43_SPROM_BCMA,\n};\n\nstatic u16 bcm43227_sprom_map[] = {\n\t0x2801, 0x0000, 0x0543, 0x14e4, 0x0070, 0xedbe, 0x0000, 0x2bc4,\n\t0x2a64, 0x2964, 0x2c64, 0x3ce7, 0x46ff, 0x47ff, 0x0c00, 0x0820,\n\t0x0030, 0x1002, 0x9f28, 0x5d44, 0x8080, 0x1d8f, 0x0032, 0x0100,\n\t0xdf00, 0x71f5, 0x8400, 0x0083, 0x8500, 0x2010, 0x0001, 0x0000,\n\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n\t0x0000, 0x0000, 0x1008, 0x0305, 0x0000, 0x0000, 0x0000, 0x0000,\n\t0x4358, 0x8000, 0x0002, 0x0000, 0x1f30, 0x1800, 0x0000, 0x0000,\n\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n\t0x5372, 0x1402, 0x0200, 0x0000, 0x0800, 0x0000, 0x0000, 0x0000,\n\t0x0000, 0x0000, 0x0003, 0xffff, 0x88ff, 0xffff, 0x0003, 0x0202,\n\t0xffff, 0x0033, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0415,\n\t0x0000, 0x7800, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n\t0x204c, 0xff36, 0x16d2, 0xfaae, 0x0000, 0x0000, 0x0000, 0x0000,\n\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n\t0x204c, 0xfeca, 0x159b, 0xfa80, 0x0000, 0x0000, 0x0000, 0x0000,\n\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n\t0x0000, 0x4444, 0x4444, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n\t0x0000, 0x4444, 0x4444, 0x4444, 0x4444, 0x6666, 0x6666, 0x6666,\n\t0x6666, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0xffff, 0xffff, 0xffff,\n\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n\t0xffff, 0xffff, 0xffff, 0x0008,\n};\n\nstruct b43_sprom_raw bcm43227_sprom = {\n\t.map = bcm43227_sprom_map,\n\t.size = ARRAY_SIZE(bcm43227_sprom_map),\n\t.type = B43_SPROM_BCMA,\n};\n\nstatic u16 bcm43228_sprom_map[] = {\n\t0x2801, 0x0000, 0x0011, 0x1028, 0x0070, 0xedbe, 0x0000, 0x2bc4,\n\t0x2a64, 0x2964, 0x2c64, 0x3ce7, 0x46ff, 0x47ff, 0x0c00, 0x0820,\n\t0x0030, 0x1002, 0x9f28, 0x5d44, 0x8080, 0x1d8f, 0x0032, 0x0100,\n\t0xdf00, 0x71f5, 0x8400, 0x0083, 0x8500, 0x2010, 0x0001, 0x0000,\n\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n\t0x0000, 0x0000, 0x1008, 0x0305, 0x0000, 0x0000, 0x0000, 0x0000,\n\t0x4359, 0x8000, 0x0002, 0x0000, 0x1f30, 0x1800, 0x0000, 0x0000,\n\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n\t0x5372, 0x1203, 0x0200, 0x0000, 0x0800, 0x0000, 0x0000, 0x0000,\n\t0x0000, 0x0000, 0x0003, 0xffff, 0x88ff, 0xffff, 0x0303, 0x0202,\n\t0xffff, 0x0033, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0215,\n\t0x0215, 0x7800, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n\t0x204c, 0xff73, 0x1762, 0xfaa4, 0x3e34, 0x3434, 0xfea1, 0x154c,\n\t0xfad0, 0xfea1, 0x144c, 0xfafb, 0xfe7b, 0x13fe, 0xfafc, 0x0000,\n\t0x204c, 0xff41, 0x16a3, 0xfa8f, 0x3e34, 0x3434, 0xfe97, 0x1446,\n\t0xfb05, 0xfe97, 0x1346, 0xfb32, 0xfeb9, 0x1516, 0xfaee, 0x0000,\n\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n\t0x0000, 0x4444, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\n\t0x0000, 0x4444, 0x4444, 0x4444, 0x4444, 0x8888, 0x8888, 0x8888,\n\t0x8888, 0x0000, 0x0000, 0x0000, 0x0000, 0x3333, 0x3333, 0x3333,\n\t0x3333, 0x0000, 0x0000, 0x0000, 0x0000, 0x3333, 0x3333, 0x3333,\n\t0x3333, 0x0000, 0x0000, 0x0000, 0x0000, 0x3333, 0x3333, 0x3333,\n\t0x3333, 0x0000, 0x0000, 0x0000, 0x0000, 0xffff, 0xffff, 0xffff,\n\t0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\n\t0xffff, 0xffff, 0xffff, 0xf008,\n};\n\nstruct b43_sprom_raw bcm43228_sprom = {\n\t.map = bcm43228_sprom_map,\n\t.size = ARRAY_SIZE(bcm43228_sprom_map),\n\t.type = B43_SPROM_BCMA,\n};\n#endif /* CONFIG_BCMA_HOST_PCI */\n\n/* Get the word-offset for a SSB_SPROM_XXX define. */\n#define SPOFF(offset)\t((offset) / sizeof(u16))\n/* Helper to extract some _offset, which is one of the SSB_SPROM_XXX defines. */\n#define SPEX16(_outvar, _offset, _mask, _shift)\t\\\n\tout->_outvar = ((in[SPOFF(_offset)] & (_mask)) >> (_shift))\n#define SPEX32(_outvar, _offset, _mask, _shift)\t\\\n\tout->_outvar = ((((u32)in[SPOFF((_offset)+2)] << 16 | \\\n\t\t\t   in[SPOFF(_offset)]) & (_mask)) >> (_shift))\n#define SPEX(_outvar, _offset, _mask, _shift) \\\n\tSPEX16(_outvar, _offset, _mask, _shift)\n\n#define SPEX_ARRAY8(_field, _offset, _mask, _shift)\t\\\n\tdo {\t\\\n\t\tSPEX(_field[0], _offset +  0, _mask, _shift);\t\\\n\t\tSPEX(_field[1], _offset +  2, _mask, _shift);\t\\\n\t\tSPEX(_field[2], _offset +  4, _mask, _shift);\t\\\n\t\tSPEX(_field[3], _offset +  6, _mask, _shift);\t\\\n\t\tSPEX(_field[4], _offset +  8, _mask, _shift);\t\\\n\t\tSPEX(_field[5], _offset + 10, _mask, _shift);\t\\\n\t\tSPEX(_field[6], _offset + 12, _mask, _shift);\t\\\n\t\tSPEX(_field[7], _offset + 14, _mask, _shift);\t\\\n\t} while (0)\n\n\nstatic s8 sprom_extract_antgain(u8 sprom_revision, const u16 *in, u16 offset,\n\t\t\t\tu16 mask, u16 shift)\n{\n\tu16 v;\n\tu8 gain;\n\n\tv = in[SPOFF(offset)];\n\tgain = (v & mask) >> shift;\n\tif (gain == 0xFF)\n\t\tgain = 2; /* If unset use 2dBm */\n\tif (sprom_revision == 1) {\n\t\t/* Convert to Q5.2 */\n\t\tgain <<= 2;\n\t} else {\n\t\t/* Q5.2 Fractional part is stored in 0xC0 */\n\t\tgain = ((gain & 0xC0) >> 6) | ((gain & 0x3F) << 2);\n\t}\n\n\treturn (s8)gain;\n}\n\nstatic void sprom_extract_r23(struct ssb_sprom *out, const u16 *in)\n{\n\tSPEX(boardflags_hi, SSB_SPROM2_BFLHI, 0xFFFF, 0);\n\tSPEX(opo, SSB_SPROM2_OPO, SSB_SPROM2_OPO_VALUE, 0);\n\tSPEX(pa1lob0, SSB_SPROM2_PA1LOB0, 0xFFFF, 0);\n\tSPEX(pa1lob1, SSB_SPROM2_PA1LOB1, 0xFFFF, 0);\n\tSPEX(pa1lob2, SSB_SPROM2_PA1LOB2, 0xFFFF, 0);\n\tSPEX(pa1hib0, SSB_SPROM2_PA1HIB0, 0xFFFF, 0);\n\tSPEX(pa1hib1, SSB_SPROM2_PA1HIB1, 0xFFFF, 0);\n\tSPEX(pa1hib2, SSB_SPROM2_PA1HIB2, 0xFFFF, 0);\n\tSPEX(maxpwr_ah, SSB_SPROM2_MAXP_A, SSB_SPROM2_MAXP_A_HI, 0);\n\tSPEX(maxpwr_al, SSB_SPROM2_MAXP_A, SSB_SPROM2_MAXP_A_LO,\n\t     SSB_SPROM2_MAXP_A_LO_SHIFT);\n}\n\nstatic void sprom_extract_r123(struct ssb_sprom *out, const u16 *in)\n{\n\tu16 loc[3];\n\n\tif (out->revision == 3)\t\t\t/* rev 3 moved MAC */\n\t\tloc[0] = SSB_SPROM3_IL0MAC;\n\telse {\n\t\tloc[0] = SSB_SPROM1_IL0MAC;\n\t\tloc[1] = SSB_SPROM1_ET0MAC;\n\t\tloc[2] = SSB_SPROM1_ET1MAC;\n\t}\n\n\tSPEX(et0phyaddr, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET0A, 0);\n\tSPEX(et1phyaddr, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET1A,\n\t     SSB_SPROM1_ETHPHY_ET1A_SHIFT);\n\tSPEX(et0mdcport, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET0M, 14);\n\tSPEX(et1mdcport, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET1M, 15);\n\tSPEX(board_rev, SSB_SPROM1_BINF, SSB_SPROM1_BINF_BREV, 0);\n\tSPEX(board_type, SSB_SPROM1_SPID, 0xFFFF, 0);\n\tif (out->revision == 1)\n\t\tSPEX(country_code, SSB_SPROM1_BINF, SSB_SPROM1_BINF_CCODE,\n\t\t     SSB_SPROM1_BINF_CCODE_SHIFT);\n\tSPEX(ant_available_a, SSB_SPROM1_BINF, SSB_SPROM1_BINF_ANTA,\n\t     SSB_SPROM1_BINF_ANTA_SHIFT);\n\tSPEX(ant_available_bg, SSB_SPROM1_BINF, SSB_SPROM1_BINF_ANTBG,\n\t     SSB_SPROM1_BINF_ANTBG_SHIFT);\n\tSPEX(pa0b0, SSB_SPROM1_PA0B0, 0xFFFF, 0);\n\tSPEX(pa0b1, SSB_SPROM1_PA0B1, 0xFFFF, 0);\n\tSPEX(pa0b2, SSB_SPROM1_PA0B2, 0xFFFF, 0);\n\tSPEX(pa1b0, SSB_SPROM1_PA1B0, 0xFFFF, 0);\n\tSPEX(pa1b1, SSB_SPROM1_PA1B1, 0xFFFF, 0);\n\tSPEX(pa1b2, SSB_SPROM1_PA1B2, 0xFFFF, 0);\n\tSPEX(gpio0, SSB_SPROM1_GPIOA, SSB_SPROM1_GPIOA_P0, 0);\n\tSPEX(gpio1, SSB_SPROM1_GPIOA, SSB_SPROM1_GPIOA_P1,\n\t     SSB_SPROM1_GPIOA_P1_SHIFT);\n\tSPEX(gpio2, SSB_SPROM1_GPIOB, SSB_SPROM1_GPIOB_P2, 0);\n\tSPEX(gpio3, SSB_SPROM1_GPIOB, SSB_SPROM1_GPIOB_P3,\n\t     SSB_SPROM1_GPIOB_P3_SHIFT);\n\tSPEX(maxpwr_a, SSB_SPROM1_MAXPWR, SSB_SPROM1_MAXPWR_A,\n\t     SSB_SPROM1_MAXPWR_A_SHIFT);\n\tSPEX(maxpwr_bg, SSB_SPROM1_MAXPWR, SSB_SPROM1_MAXPWR_BG, 0);\n\tSPEX(itssi_a, SSB_SPROM1_ITSSI, SSB_SPROM1_ITSSI_A,\n\t     SSB_SPROM1_ITSSI_A_SHIFT);\n\tSPEX(itssi_bg, SSB_SPROM1_ITSSI, SSB_SPROM1_ITSSI_BG, 0);\n\tSPEX(boardflags_lo, SSB_SPROM1_BFLLO, 0xFFFF, 0);\n\n\tSPEX(alpha2[0], SSB_SPROM1_CCODE, 0xff00, 8);\n\tSPEX(alpha2[1], SSB_SPROM1_CCODE, 0x00ff, 0);\n\n\t/* Extract the antenna gain values. */\n\tout->antenna_gain.a0 = sprom_extract_antgain(out->revision, in,\n\t\t\t\t\t\t     SSB_SPROM1_AGAIN,\n\t\t\t\t\t\t     SSB_SPROM1_AGAIN_BG,\n\t\t\t\t\t\t     SSB_SPROM1_AGAIN_BG_SHIFT);\n\tout->antenna_gain.a1 = sprom_extract_antgain(out->revision, in,\n\t\t\t\t\t\t     SSB_SPROM1_AGAIN,\n\t\t\t\t\t\t     SSB_SPROM1_AGAIN_A,\n\t\t\t\t\t\t     SSB_SPROM1_AGAIN_A_SHIFT);\n\tif (out->revision >= 2)\n\t\tsprom_extract_r23(out, in);\n}\n\n/* Revs 4 5 and 8 have partially shared layout */\nstatic void sprom_extract_r458(struct ssb_sprom *out, const u16 *in)\n{\n\tSPEX(txpid2g[0], SSB_SPROM4_TXPID2G01,\n\t     SSB_SPROM4_TXPID2G0, SSB_SPROM4_TXPID2G0_SHIFT);\n\tSPEX(txpid2g[1], SSB_SPROM4_TXPID2G01,\n\t     SSB_SPROM4_TXPID2G1, SSB_SPROM4_TXPID2G1_SHIFT);\n\tSPEX(txpid2g[2], SSB_SPROM4_TXPID2G23,\n\t     SSB_SPROM4_TXPID2G2, SSB_SPROM4_TXPID2G2_SHIFT);\n\tSPEX(txpid2g[3], SSB_SPROM4_TXPID2G23,\n\t     SSB_SPROM4_TXPID2G3, SSB_SPROM4_TXPID2G3_SHIFT);\n\n\tSPEX(txpid5gl[0], SSB_SPROM4_TXPID5GL01,\n\t     SSB_SPROM4_TXPID5GL0, SSB_SPROM4_TXPID5GL0_SHIFT);\n\tSPEX(txpid5gl[1], SSB_SPROM4_TXPID5GL01,\n\t     SSB_SPROM4_TXPID5GL1, SSB_SPROM4_TXPID5GL1_SHIFT);\n\tSPEX(txpid5gl[2], SSB_SPROM4_TXPID5GL23,\n\t     SSB_SPROM4_TXPID5GL2, SSB_SPROM4_TXPID5GL2_SHIFT);\n\tSPEX(txpid5gl[3], SSB_SPROM4_TXPID5GL23,\n\t     SSB_SPROM4_TXPID5GL3, SSB_SPROM4_TXPID5GL3_SHIFT);\n\n\tSPEX(txpid5g[0], SSB_SPROM4_TXPID5G01,\n\t     SSB_SPROM4_TXPID5G0, SSB_SPROM4_TXPID5G0_SHIFT);\n\tSPEX(txpid5g[1], SSB_SPROM4_TXPID5G01,\n\t     SSB_SPROM4_TXPID5G1, SSB_SPROM4_TXPID5G1_SHIFT);\n\tSPEX(txpid5g[2], SSB_SPROM4_TXPID5G23,\n\t     SSB_SPROM4_TXPID5G2, SSB_SPROM4_TXPID5G2_SHIFT);\n\tSPEX(txpid5g[3], SSB_SPROM4_TXPID5G23,\n\t     SSB_SPROM4_TXPID5G3, SSB_SPROM4_TXPID5G3_SHIFT);\n\n\tSPEX(txpid5gh[0], SSB_SPROM4_TXPID5GH01,\n\t     SSB_SPROM4_TXPID5GH0, SSB_SPROM4_TXPID5GH0_SHIFT);\n\tSPEX(txpid5gh[1], SSB_SPROM4_TXPID5GH01,\n\t     SSB_SPROM4_TXPID5GH1, SSB_SPROM4_TXPID5GH1_SHIFT);\n\tSPEX(txpid5gh[2], SSB_SPROM4_TXPID5GH23,\n\t     SSB_SPROM4_TXPID5GH2, SSB_SPROM4_TXPID5GH2_SHIFT);\n\tSPEX(txpid5gh[3], SSB_SPROM4_TXPID5GH23,\n\t     SSB_SPROM4_TXPID5GH3, SSB_SPROM4_TXPID5GH3_SHIFT);\n}\n\nstatic void sprom_extract_r45(struct ssb_sprom *out, const u16 *in)\n{\n\tstatic const u16 pwr_info_offset[] = {\n\t\tSSB_SPROM4_PWR_INFO_CORE0, SSB_SPROM4_PWR_INFO_CORE1,\n\t\tSSB_SPROM4_PWR_INFO_CORE2, SSB_SPROM4_PWR_INFO_CORE3\n\t};\n\tint i;\n\n\tBUILD_BUG_ON(ARRAY_SIZE(pwr_info_offset) !=\n\t\t     ARRAY_SIZE(out->core_pwr_info));\n\n\tSPEX(et0phyaddr, SSB_SPROM4_ETHPHY, SSB_SPROM4_ETHPHY_ET0A, 0);\n\tSPEX(et1phyaddr, SSB_SPROM4_ETHPHY, SSB_SPROM4_ETHPHY_ET1A,\n\t     SSB_SPROM4_ETHPHY_ET1A_SHIFT);\n\tSPEX(board_rev, SSB_SPROM4_BOARDREV, 0xFFFF, 0);\n\tSPEX(board_type, SSB_SPROM1_SPID, 0xFFFF, 0);\n\tif (out->revision == 4) {\n\t\tSPEX(alpha2[0], SSB_SPROM4_CCODE, 0xff00, 8);\n\t\tSPEX(alpha2[1], SSB_SPROM4_CCODE, 0x00ff, 0);\n\t\tSPEX(boardflags_lo, SSB_SPROM4_BFLLO, 0xFFFF, 0);\n\t\tSPEX(boardflags_hi, SSB_SPROM4_BFLHI, 0xFFFF, 0);\n\t\tSPEX(boardflags2_lo, SSB_SPROM4_BFL2LO, 0xFFFF, 0);\n\t\tSPEX(boardflags2_hi, SSB_SPROM4_BFL2HI, 0xFFFF, 0);\n\t} else {\n\t\tSPEX(alpha2[0], SSB_SPROM5_CCODE, 0xff00, 8);\n\t\tSPEX(alpha2[1], SSB_SPROM5_CCODE, 0x00ff, 0);\n\t\tSPEX(boardflags_lo, SSB_SPROM5_BFLLO, 0xFFFF, 0);\n\t\tSPEX(boardflags_hi, SSB_SPROM5_BFLHI, 0xFFFF, 0);\n\t\tSPEX(boardflags2_lo, SSB_SPROM5_BFL2LO, 0xFFFF, 0);\n\t\tSPEX(boardflags2_hi, SSB_SPROM5_BFL2HI, 0xFFFF, 0);\n\t}\n\tSPEX(ant_available_a, SSB_SPROM4_ANTAVAIL, SSB_SPROM4_ANTAVAIL_A,\n\t     SSB_SPROM4_ANTAVAIL_A_SHIFT);\n\tSPEX(ant_available_bg, SSB_SPROM4_ANTAVAIL, SSB_SPROM4_ANTAVAIL_BG,\n\t     SSB_SPROM4_ANTAVAIL_BG_SHIFT);\n\tSPEX(maxpwr_bg, SSB_SPROM4_MAXP_BG, SSB_SPROM4_MAXP_BG_MASK, 0);\n\tSPEX(itssi_bg, SSB_SPROM4_MAXP_BG, SSB_SPROM4_ITSSI_BG,\n\t     SSB_SPROM4_ITSSI_BG_SHIFT);\n\tSPEX(maxpwr_a, SSB_SPROM4_MAXP_A, SSB_SPROM4_MAXP_A_MASK, 0);\n\tSPEX(itssi_a, SSB_SPROM4_MAXP_A, SSB_SPROM4_ITSSI_A,\n\t     SSB_SPROM4_ITSSI_A_SHIFT);\n\tif (out->revision == 4) {\n\t\tSPEX(gpio0, SSB_SPROM4_GPIOA, SSB_SPROM4_GPIOA_P0, 0);\n\t\tSPEX(gpio1, SSB_SPROM4_GPIOA, SSB_SPROM4_GPIOA_P1,\n\t\t     SSB_SPROM4_GPIOA_P1_SHIFT);\n\t\tSPEX(gpio2, SSB_SPROM4_GPIOB, SSB_SPROM4_GPIOB_P2, 0);\n\t\tSPEX(gpio3, SSB_SPROM4_GPIOB, SSB_SPROM4_GPIOB_P3,\n\t\t     SSB_SPROM4_GPIOB_P3_SHIFT);\n\t} else {\n\t\tSPEX(gpio0, SSB_SPROM5_GPIOA, SSB_SPROM5_GPIOA_P0, 0);\n\t\tSPEX(gpio1, SSB_SPROM5_GPIOA, SSB_SPROM5_GPIOA_P1,\n\t\t     SSB_SPROM5_GPIOA_P1_SHIFT);\n\t\tSPEX(gpio2, SSB_SPROM5_GPIOB, SSB_SPROM5_GPIOB_P2, 0);\n\t\tSPEX(gpio3, SSB_SPROM5_GPIOB, SSB_SPROM5_GPIOB_P3,\n\t\t     SSB_SPROM5_GPIOB_P3_SHIFT);\n\t}\n\n\t/* Extract the antenna gain values. */\n\tout->antenna_gain.a0 = sprom_extract_antgain(out->revision, in,\n\t\t\t\t\t\t     SSB_SPROM4_AGAIN01,\n\t\t\t\t\t\t     SSB_SPROM4_AGAIN0,\n\t\t\t\t\t\t     SSB_SPROM4_AGAIN0_SHIFT);\n\tout->antenna_gain.a1 = sprom_extract_antgain(out->revision, in,\n\t\t\t\t\t\t     SSB_SPROM4_AGAIN01,\n\t\t\t\t\t\t     SSB_SPROM4_AGAIN1,\n\t\t\t\t\t\t     SSB_SPROM4_AGAIN1_SHIFT);\n\tout->antenna_gain.a2 = sprom_extract_antgain(out->revision, in,\n\t\t\t\t\t\t     SSB_SPROM4_AGAIN23,\n\t\t\t\t\t\t     SSB_SPROM4_AGAIN2,\n\t\t\t\t\t\t     SSB_SPROM4_AGAIN2_SHIFT);\n\tout->antenna_gain.a3 = sprom_extract_antgain(out->revision, in,\n\t\t\t\t\t\t     SSB_SPROM4_AGAIN23,\n\t\t\t\t\t\t     SSB_SPROM4_AGAIN3,\n\t\t\t\t\t\t     SSB_SPROM4_AGAIN3_SHIFT);\n\n\t/* Extract cores power info info */\n\tfor (i = 0; i < ARRAY_SIZE(pwr_info_offset); i++) {\n\t\tu16 o = pwr_info_offset[i];\n\n\t\tSPEX(core_pwr_info[i].itssi_2g, o + SSB_SPROM4_2G_MAXP_ITSSI,\n\t\t\tSSB_SPROM4_2G_ITSSI, SSB_SPROM4_2G_ITSSI_SHIFT);\n\t\tSPEX(core_pwr_info[i].maxpwr_2g, o + SSB_SPROM4_2G_MAXP_ITSSI,\n\t\t\tSSB_SPROM4_2G_MAXP, 0);\n\n\t\tSPEX(core_pwr_info[i].pa_2g[0], o + SSB_SPROM4_2G_PA_0, ~0, 0);\n\t\tSPEX(core_pwr_info[i].pa_2g[1], o + SSB_SPROM4_2G_PA_1, ~0, 0);\n\t\tSPEX(core_pwr_info[i].pa_2g[2], o + SSB_SPROM4_2G_PA_2, ~0, 0);\n\t\tSPEX(core_pwr_info[i].pa_2g[3], o + SSB_SPROM4_2G_PA_3, ~0, 0);\n\n\t\tSPEX(core_pwr_info[i].itssi_5g, o + SSB_SPROM4_5G_MAXP_ITSSI,\n\t\t\tSSB_SPROM4_5G_ITSSI, SSB_SPROM4_5G_ITSSI_SHIFT);\n\t\tSPEX(core_pwr_info[i].maxpwr_5g, o + SSB_SPROM4_5G_MAXP_ITSSI,\n\t\t\tSSB_SPROM4_5G_MAXP, 0);\n\t\tSPEX(core_pwr_info[i].maxpwr_5gh, o + SSB_SPROM4_5GHL_MAXP,\n\t\t\tSSB_SPROM4_5GH_MAXP, 0);\n\t\tSPEX(core_pwr_info[i].maxpwr_5gl, o + SSB_SPROM4_5GHL_MAXP,\n\t\t\tSSB_SPROM4_5GL_MAXP, SSB_SPROM4_5GL_MAXP_SHIFT);\n\n\t\tSPEX(core_pwr_info[i].pa_5gl[0], o + SSB_SPROM4_5GL_PA_0, ~0, 0);\n\t\tSPEX(core_pwr_info[i].pa_5gl[1], o + SSB_SPROM4_5GL_PA_1, ~0, 0);\n\t\tSPEX(core_pwr_info[i].pa_5gl[2], o + SSB_SPROM4_5GL_PA_2, ~0, 0);\n\t\tSPEX(core_pwr_info[i].pa_5gl[3], o + SSB_SPROM4_5GL_PA_3, ~0, 0);\n\t\tSPEX(core_pwr_info[i].pa_5g[0], o + SSB_SPROM4_5G_PA_0, ~0, 0);\n\t\tSPEX(core_pwr_info[i].pa_5g[1], o + SSB_SPROM4_5G_PA_1, ~0, 0);\n\t\tSPEX(core_pwr_info[i].pa_5g[2], o + SSB_SPROM4_5G_PA_2, ~0, 0);\n\t\tSPEX(core_pwr_info[i].pa_5g[3], o + SSB_SPROM4_5G_PA_3, ~0, 0);\n\t\tSPEX(core_pwr_info[i].pa_5gh[0], o + SSB_SPROM4_5GH_PA_0, ~0, 0);\n\t\tSPEX(core_pwr_info[i].pa_5gh[1], o + SSB_SPROM4_5GH_PA_1, ~0, 0);\n\t\tSPEX(core_pwr_info[i].pa_5gh[2], o + SSB_SPROM4_5GH_PA_2, ~0, 0);\n\t\tSPEX(core_pwr_info[i].pa_5gh[3], o + SSB_SPROM4_5GH_PA_3, ~0, 0);\n\t}\n\n\tsprom_extract_r458(out, in);\n\n\t/* TODO - get remaining rev 4 stuff needed */\n}\n\nstatic void sprom_extract_r8(struct ssb_sprom *out, const u16 *in)\n{\n\tint i;\n\tu16 o;\n\tstatic const u16 pwr_info_offset[] = {\n\t\tSSB_SROM8_PWR_INFO_CORE0, SSB_SROM8_PWR_INFO_CORE1,\n\t\tSSB_SROM8_PWR_INFO_CORE2, SSB_SROM8_PWR_INFO_CORE3\n\t};\n\tBUILD_BUG_ON(ARRAY_SIZE(pwr_info_offset) !=\n\t\t\tARRAY_SIZE(out->core_pwr_info));\n\n\tSPEX(board_rev, SSB_SPROM8_BOARDREV, 0xFFFF, 0);\n\tSPEX(board_type, SSB_SPROM1_SPID, 0xFFFF, 0);\n\tSPEX(alpha2[0], SSB_SPROM8_CCODE, 0xff00, 8);\n\tSPEX(alpha2[1], SSB_SPROM8_CCODE, 0x00ff, 0);\n\tSPEX(boardflags_lo, SSB_SPROM8_BFLLO, 0xFFFF, 0);\n\tSPEX(boardflags_hi, SSB_SPROM8_BFLHI, 0xFFFF, 0);\n\tSPEX(boardflags2_lo, SSB_SPROM8_BFL2LO, 0xFFFF, 0);\n\tSPEX(boardflags2_hi, SSB_SPROM8_BFL2HI, 0xFFFF, 0);\n\tSPEX(ant_available_a, SSB_SPROM8_ANTAVAIL, SSB_SPROM8_ANTAVAIL_A,\n\t     SSB_SPROM8_ANTAVAIL_A_SHIFT);\n\tSPEX(ant_available_bg, SSB_SPROM8_ANTAVAIL, SSB_SPROM8_ANTAVAIL_BG,\n\t     SSB_SPROM8_ANTAVAIL_BG_SHIFT);\n\tSPEX(maxpwr_bg, SSB_SPROM8_MAXP_BG, SSB_SPROM8_MAXP_BG_MASK, 0);\n\tSPEX(itssi_bg, SSB_SPROM8_MAXP_BG, SSB_SPROM8_ITSSI_BG,\n\t     SSB_SPROM8_ITSSI_BG_SHIFT);\n\tSPEX(maxpwr_a, SSB_SPROM8_MAXP_A, SSB_SPROM8_MAXP_A_MASK, 0);\n\tSPEX(itssi_a, SSB_SPROM8_MAXP_A, SSB_SPROM8_ITSSI_A,\n\t     SSB_SPROM8_ITSSI_A_SHIFT);\n\tSPEX(maxpwr_ah, SSB_SPROM8_MAXP_AHL, SSB_SPROM8_MAXP_AH_MASK, 0);\n\tSPEX(maxpwr_al, SSB_SPROM8_MAXP_AHL, SSB_SPROM8_MAXP_AL_MASK,\n\t     SSB_SPROM8_MAXP_AL_SHIFT);\n\tSPEX(gpio0, SSB_SPROM8_GPIOA, SSB_SPROM8_GPIOA_P0, 0);\n\tSPEX(gpio1, SSB_SPROM8_GPIOA, SSB_SPROM8_GPIOA_P1,\n\t     SSB_SPROM8_GPIOA_P1_SHIFT);\n\tSPEX(gpio2, SSB_SPROM8_GPIOB, SSB_SPROM8_GPIOB_P2, 0);\n\tSPEX(gpio3, SSB_SPROM8_GPIOB, SSB_SPROM8_GPIOB_P3,\n\t     SSB_SPROM8_GPIOB_P3_SHIFT);\n\tSPEX(tri2g, SSB_SPROM8_TRI25G, SSB_SPROM8_TRI2G, 0);\n\tSPEX(tri5g, SSB_SPROM8_TRI25G, SSB_SPROM8_TRI5G,\n\t     SSB_SPROM8_TRI5G_SHIFT);\n\tSPEX(tri5gl, SSB_SPROM8_TRI5GHL, SSB_SPROM8_TRI5GL, 0);\n\tSPEX(tri5gh, SSB_SPROM8_TRI5GHL, SSB_SPROM8_TRI5GH,\n\t     SSB_SPROM8_TRI5GH_SHIFT);\n\tSPEX(rxpo2g, SSB_SPROM8_RXPO, SSB_SPROM8_RXPO2G, 0);\n\tSPEX(rxpo5g, SSB_SPROM8_RXPO, SSB_SPROM8_RXPO5G,\n\t     SSB_SPROM8_RXPO5G_SHIFT);\n\tSPEX(rssismf2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_RSSISMF2G, 0);\n\tSPEX(rssismc2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_RSSISMC2G,\n\t     SSB_SPROM8_RSSISMC2G_SHIFT);\n\tSPEX(rssisav2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_RSSISAV2G,\n\t     SSB_SPROM8_RSSISAV2G_SHIFT);\n\tSPEX(bxa2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_BXA2G,\n\t     SSB_SPROM8_BXA2G_SHIFT);\n\tSPEX(rssismf5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_RSSISMF5G, 0);\n\tSPEX(rssismc5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_RSSISMC5G,\n\t     SSB_SPROM8_RSSISMC5G_SHIFT);\n\tSPEX(rssisav5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_RSSISAV5G,\n\t     SSB_SPROM8_RSSISAV5G_SHIFT);\n\tSPEX(bxa5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_BXA5G,\n\t     SSB_SPROM8_BXA5G_SHIFT);\n\tSPEX(pa0b0, SSB_SPROM8_PA0B0, 0xFFFF, 0);\n\tSPEX(pa0b1, SSB_SPROM8_PA0B1, 0xFFFF, 0);\n\tSPEX(pa0b2, SSB_SPROM8_PA0B2, 0xFFFF, 0);\n\tSPEX(pa1b0, SSB_SPROM8_PA1B0, 0xFFFF, 0);\n\tSPEX(pa1b1, SSB_SPROM8_PA1B1, 0xFFFF, 0);\n\tSPEX(pa1b2, SSB_SPROM8_PA1B2, 0xFFFF, 0);\n\tSPEX(pa1lob0, SSB_SPROM8_PA1LOB0, 0xFFFF, 0);\n\tSPEX(pa1lob1, SSB_SPROM8_PA1LOB1, 0xFFFF, 0);\n\tSPEX(pa1lob2, SSB_SPROM8_PA1LOB2, 0xFFFF, 0);\n\tSPEX(pa1hib0, SSB_SPROM8_PA1HIB0, 0xFFFF, 0);\n\tSPEX(pa1hib1, SSB_SPROM8_PA1HIB1, 0xFFFF, 0);\n\tSPEX(pa1hib2, SSB_SPROM8_PA1HIB2, 0xFFFF, 0);\n\tSPEX(cck2gpo, SSB_SPROM8_CCK2GPO, 0xFFFF, 0);\n\tSPEX32(ofdm2gpo, SSB_SPROM8_OFDM2GPO, 0xFFFFFFFF, 0);\n\tSPEX32(ofdm5glpo, SSB_SPROM8_OFDM5GLPO, 0xFFFFFFFF, 0);\n\tSPEX32(ofdm5gpo, SSB_SPROM8_OFDM5GPO, 0xFFFFFFFF, 0);\n\tSPEX32(ofdm5ghpo, SSB_SPROM8_OFDM5GHPO, 0xFFFFFFFF, 0);\n\n\t/* Extract the antenna gain values. */\n\tout->antenna_gain.a0 = sprom_extract_antgain(out->revision, in,\n\t\t\t\t\t\t     SSB_SPROM8_AGAIN01,\n\t\t\t\t\t\t     SSB_SPROM8_AGAIN0,\n\t\t\t\t\t\t     SSB_SPROM8_AGAIN0_SHIFT);\n\tout->antenna_gain.a1 = sprom_extract_antgain(out->revision, in,\n\t\t\t\t\t\t     SSB_SPROM8_AGAIN01,\n\t\t\t\t\t\t     SSB_SPROM8_AGAIN1,\n\t\t\t\t\t\t     SSB_SPROM8_AGAIN1_SHIFT);\n\tout->antenna_gain.a2 = sprom_extract_antgain(out->revision, in,\n\t\t\t\t\t\t     SSB_SPROM8_AGAIN23,\n\t\t\t\t\t\t     SSB_SPROM8_AGAIN2,\n\t\t\t\t\t\t     SSB_SPROM8_AGAIN2_SHIFT);\n\tout->antenna_gain.a3 = sprom_extract_antgain(out->revision, in,\n\t\t\t\t\t\t     SSB_SPROM8_AGAIN23,\n\t\t\t\t\t\t     SSB_SPROM8_AGAIN3,\n\t\t\t\t\t\t     SSB_SPROM8_AGAIN3_SHIFT);\n\n\t/* Extract cores power info info */\n\tfor (i = 0; i < ARRAY_SIZE(pwr_info_offset); i++) {\n\t\to = pwr_info_offset[i];\n\t\tSPEX(core_pwr_info[i].itssi_2g, o + SSB_SROM8_2G_MAXP_ITSSI,\n\t\t\tSSB_SPROM8_2G_ITSSI, SSB_SPROM8_2G_ITSSI_SHIFT);\n\t\tSPEX(core_pwr_info[i].maxpwr_2g, o + SSB_SROM8_2G_MAXP_ITSSI,\n\t\t\tSSB_SPROM8_2G_MAXP, 0);\n\n\t\tSPEX(core_pwr_info[i].pa_2g[0], o + SSB_SROM8_2G_PA_0, ~0, 0);\n\t\tSPEX(core_pwr_info[i].pa_2g[1], o + SSB_SROM8_2G_PA_1, ~0, 0);\n\t\tSPEX(core_pwr_info[i].pa_2g[2], o + SSB_SROM8_2G_PA_2, ~0, 0);\n\n\t\tSPEX(core_pwr_info[i].itssi_5g, o + SSB_SROM8_5G_MAXP_ITSSI,\n\t\t\tSSB_SPROM8_5G_ITSSI, SSB_SPROM8_5G_ITSSI_SHIFT);\n\t\tSPEX(core_pwr_info[i].maxpwr_5g, o + SSB_SROM8_5G_MAXP_ITSSI,\n\t\t\tSSB_SPROM8_5G_MAXP, 0);\n\t\tSPEX(core_pwr_info[i].maxpwr_5gh, o + SSB_SPROM8_5GHL_MAXP,\n\t\t\tSSB_SPROM8_5GH_MAXP, 0);\n\t\tSPEX(core_pwr_info[i].maxpwr_5gl, o + SSB_SPROM8_5GHL_MAXP,\n\t\t\tSSB_SPROM8_5GL_MAXP, SSB_SPROM8_5GL_MAXP_SHIFT);\n\n\t\tSPEX(core_pwr_info[i].pa_5gl[0], o + SSB_SROM8_5GL_PA_0, ~0, 0);\n\t\tSPEX(core_pwr_info[i].pa_5gl[1], o + SSB_SROM8_5GL_PA_1, ~0, 0);\n\t\tSPEX(core_pwr_info[i].pa_5gl[2], o + SSB_SROM8_5GL_PA_2, ~0, 0);\n\t\tSPEX(core_pwr_info[i].pa_5g[0], o + SSB_SROM8_5G_PA_0, ~0, 0);\n\t\tSPEX(core_pwr_info[i].pa_5g[1], o + SSB_SROM8_5G_PA_1, ~0, 0);\n\t\tSPEX(core_pwr_info[i].pa_5g[2], o + SSB_SROM8_5G_PA_2, ~0, 0);\n\t\tSPEX(core_pwr_info[i].pa_5gh[0], o + SSB_SROM8_5GH_PA_0, ~0, 0);\n\t\tSPEX(core_pwr_info[i].pa_5gh[1], o + SSB_SROM8_5GH_PA_1, ~0, 0);\n\t\tSPEX(core_pwr_info[i].pa_5gh[2], o + SSB_SROM8_5GH_PA_2, ~0, 0);\n\t}\n\n\t/* Extract FEM info */\n\tSPEX(fem.ghz2.tssipos, SSB_SPROM8_FEM2G,\n\t\tSSB_SROM8_FEM_TSSIPOS, SSB_SROM8_FEM_TSSIPOS_SHIFT);\n\tSPEX(fem.ghz2.extpa_gain, SSB_SPROM8_FEM2G,\n\t\tSSB_SROM8_FEM_EXTPA_GAIN, SSB_SROM8_FEM_EXTPA_GAIN_SHIFT);\n\tSPEX(fem.ghz2.pdet_range, SSB_SPROM8_FEM2G,\n\t\tSSB_SROM8_FEM_PDET_RANGE, SSB_SROM8_FEM_PDET_RANGE_SHIFT);\n\tSPEX(fem.ghz2.tr_iso, SSB_SPROM8_FEM2G,\n\t\tSSB_SROM8_FEM_TR_ISO, SSB_SROM8_FEM_TR_ISO_SHIFT);\n\tSPEX(fem.ghz2.antswlut, SSB_SPROM8_FEM2G,\n\t\tSSB_SROM8_FEM_ANTSWLUT, SSB_SROM8_FEM_ANTSWLUT_SHIFT);\n\n\tSPEX(fem.ghz5.tssipos, SSB_SPROM8_FEM5G,\n\t\tSSB_SROM8_FEM_TSSIPOS, SSB_SROM8_FEM_TSSIPOS_SHIFT);\n\tSPEX(fem.ghz5.extpa_gain, SSB_SPROM8_FEM5G,\n\t\tSSB_SROM8_FEM_EXTPA_GAIN, SSB_SROM8_FEM_EXTPA_GAIN_SHIFT);\n\tSPEX(fem.ghz5.pdet_range, SSB_SPROM8_FEM5G,\n\t\tSSB_SROM8_FEM_PDET_RANGE, SSB_SROM8_FEM_PDET_RANGE_SHIFT);\n\tSPEX(fem.ghz5.tr_iso, SSB_SPROM8_FEM5G,\n\t\tSSB_SROM8_FEM_TR_ISO, SSB_SROM8_FEM_TR_ISO_SHIFT);\n\tSPEX(fem.ghz5.antswlut, SSB_SPROM8_FEM5G,\n\t\tSSB_SROM8_FEM_ANTSWLUT, SSB_SROM8_FEM_ANTSWLUT_SHIFT);\n\n\tSPEX(leddc_on_time, SSB_SPROM8_LEDDC, SSB_SPROM8_LEDDC_ON,\n\t     SSB_SPROM8_LEDDC_ON_SHIFT);\n\tSPEX(leddc_off_time, SSB_SPROM8_LEDDC, SSB_SPROM8_LEDDC_OFF,\n\t     SSB_SPROM8_LEDDC_OFF_SHIFT);\n\n\tSPEX(txchain, SSB_SPROM8_TXRXC, SSB_SPROM8_TXRXC_TXCHAIN,\n\t     SSB_SPROM8_TXRXC_TXCHAIN_SHIFT);\n\tSPEX(rxchain, SSB_SPROM8_TXRXC, SSB_SPROM8_TXRXC_RXCHAIN,\n\t     SSB_SPROM8_TXRXC_RXCHAIN_SHIFT);\n\tSPEX(antswitch, SSB_SPROM8_TXRXC, SSB_SPROM8_TXRXC_SWITCH,\n\t     SSB_SPROM8_TXRXC_SWITCH_SHIFT);\n\n\tSPEX(opo, SSB_SPROM8_OFDM2GPO, 0x00ff, 0);\n\n\tSPEX_ARRAY8(mcs2gpo, SSB_SPROM8_2G_MCSPO, ~0, 0);\n\tSPEX_ARRAY8(mcs5gpo, SSB_SPROM8_5G_MCSPO, ~0, 0);\n\tSPEX_ARRAY8(mcs5glpo, SSB_SPROM8_5GL_MCSPO, ~0, 0);\n\tSPEX_ARRAY8(mcs5ghpo, SSB_SPROM8_5GH_MCSPO, ~0, 0);\n\n\tSPEX(rawtempsense, SSB_SPROM8_RAWTS, SSB_SPROM8_RAWTS_RAWTEMP,\n\t     SSB_SPROM8_RAWTS_RAWTEMP_SHIFT);\n\tSPEX(measpower, SSB_SPROM8_RAWTS, SSB_SPROM8_RAWTS_MEASPOWER,\n\t     SSB_SPROM8_RAWTS_MEASPOWER_SHIFT);\n\tSPEX(tempsense_slope, SSB_SPROM8_OPT_CORRX,\n\t     SSB_SPROM8_OPT_CORRX_TEMP_SLOPE,\n\t     SSB_SPROM8_OPT_CORRX_TEMP_SLOPE_SHIFT);\n\tSPEX(tempcorrx, SSB_SPROM8_OPT_CORRX, SSB_SPROM8_OPT_CORRX_TEMPCORRX,\n\t     SSB_SPROM8_OPT_CORRX_TEMPCORRX_SHIFT);\n\tSPEX(tempsense_option, SSB_SPROM8_OPT_CORRX,\n\t     SSB_SPROM8_OPT_CORRX_TEMP_OPTION,\n\t     SSB_SPROM8_OPT_CORRX_TEMP_OPTION_SHIFT);\n\tSPEX(freqoffset_corr, SSB_SPROM8_HWIQ_IQSWP,\n\t     SSB_SPROM8_HWIQ_IQSWP_FREQ_CORR,\n\t     SSB_SPROM8_HWIQ_IQSWP_FREQ_CORR_SHIFT);\n\tSPEX(iqcal_swp_dis, SSB_SPROM8_HWIQ_IQSWP,\n\t     SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP,\n\t     SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP_SHIFT);\n\tSPEX(hw_iqcal_en, SSB_SPROM8_HWIQ_IQSWP, SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL,\n\t     SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL_SHIFT);\n\n\tSPEX(bw40po, SSB_SPROM8_BW40PO, ~0, 0);\n\tSPEX(cddpo, SSB_SPROM8_CDDPO, ~0, 0);\n\tSPEX(stbcpo, SSB_SPROM8_STBCPO, ~0, 0);\n\tSPEX(bwduppo, SSB_SPROM8_BWDUPPO, ~0, 0);\n\n\tSPEX(tempthresh, SSB_SPROM8_THERMAL, SSB_SPROM8_THERMAL_TRESH,\n\t     SSB_SPROM8_THERMAL_TRESH_SHIFT);\n\tSPEX(tempoffset, SSB_SPROM8_THERMAL, SSB_SPROM8_THERMAL_OFFSET,\n\t     SSB_SPROM8_THERMAL_OFFSET_SHIFT);\n\tSPEX(phycal_tempdelta, SSB_SPROM8_TEMPDELTA,\n\t     SSB_SPROM8_TEMPDELTA_PHYCAL,\n\t     SSB_SPROM8_TEMPDELTA_PHYCAL_SHIFT);\n\tSPEX(temps_period, SSB_SPROM8_TEMPDELTA, SSB_SPROM8_TEMPDELTA_PERIOD,\n\t     SSB_SPROM8_TEMPDELTA_PERIOD_SHIFT);\n\tSPEX(temps_hysteresis, SSB_SPROM8_TEMPDELTA,\n\t     SSB_SPROM8_TEMPDELTA_HYSTERESIS,\n\t     SSB_SPROM8_TEMPDELTA_HYSTERESIS_SHIFT);\n\tsprom_extract_r458(out, in);\n\n\t/* TODO - get remaining rev 8 stuff needed */\n}\n\nstatic int sprom_extract(struct ssb_sprom *out, const u16 *in, u16 size)\n{\n\tmemset(out, 0, sizeof(*out));\n\n\tout->revision = in[size - 1] & 0x00FF;\n\tmemset(out->et0mac, 0xFF, 6);\t\t/* preset et0 and et1 mac */\n\tmemset(out->et1mac, 0xFF, 6);\n\n\tswitch (out->revision) {\n\tcase 1:\n\tcase 2:\n\tcase 3:\n\t\tsprom_extract_r123(out, in);\n\t\tbreak;\n\tcase 4:\n\tcase 5:\n\t\tsprom_extract_r45(out, in);\n\t\tbreak;\n\tcase 8:\n\t\tsprom_extract_r8(out, in);\n\t\tbreak;\n\tdefault:\n\t\tpr_warn(\"Unsupported SPROM revision %d detected. Will extract v1\\n\",\n\t\t\tout->revision);\n\t\tout->revision = 1;\n\t\tsprom_extract_r123(out, in);\n\t}\n\n\tif (out->boardflags_lo == 0xFFFF)\n\t\tout->boardflags_lo = 0;  /* per specs */\n\tif (out->boardflags_hi == 0xFFFF)\n\t\tout->boardflags_hi = 0;  /* per specs */\n\n\treturn 0;\n}\n\nstatic void b43_sprom_fixup(struct b43_sprom *priv, u16 *sprom)\n{\n\tstruct device_node *node = priv->dev->of_node;\n\tu32 fixups, off, val;\n\tint i = 0;\n\n\tif (!of_get_property(node, \"brcm,sprom-fixups\", &fixups))\n\t\treturn;\n\n\tfixups /= sizeof(u32);\n\n\tdev_info(priv->dev, \"patching SPROM with %u fixups...\\n\", fixups >> 1);\n\n\twhile (i < fixups) {\n\t\tif (of_property_read_u32_index(node, \"brcm,sprom-fixups\",\n\t\t\t\t\t       i++, &off)) {\n\t\t\tdev_err(priv->dev, \"error reading fixup[%u] offset\\n\",\n\t\t\t\ti - 1);\n\t\t\treturn;\n\t\t}\n\n\t\tif (of_property_read_u32_index(node, \"brcm,sprom-fixups\",\n\t\t\t\t\t       i++, &val)) {\n\t\t\tdev_err(priv->dev, \"error reading fixup[%u] value\\n\",\n\t\t\t\ti - 1);\n\t\t\treturn;\n\t\t}\n\n\t\tdev_dbg(priv->dev, \"fixup[%d]=0x%04x\\n\", off, val);\n\n\t\tsprom[off] = val;\n\t}\n}\n\nint sprom_override_devid(struct b43_sprom *priv, struct ssb_sprom *out,\n\t\t\t const u16 *in)\n{\n\tconst struct b43_sprom_raw *raw = of_device_get_match_data(priv->dev);\n\n\tif (raw->type == B43_SPROM_SSB) {\n\t\tSPEX(dev_id, SSB_SPROM1_PID, 0xFFFF, 0);\n\t\treturn !!out->dev_id;\n\t} else if (raw->type == B43_SPROM_BCMA) {\n\t\tSPEX(dev_id, 0x0060, 0xFFFF, 0);\n\t\treturn !!out->dev_id;\n\t}\n\n\treturn 0;\n}\n\nstatic void b43_sprom_set(struct b43_sprom *priv)\n{\n\tconst struct b43_sprom_raw *raw = of_device_get_match_data(priv->dev);\n\tstruct ssb_sprom *sprom = &priv->sprom;\n\n\tif (raw) {\n\t\tu16 template_sprom[220];\n\n\t\tmemcpy(template_sprom, raw->map, raw->size * sizeof(u16));\n\t\tb43_sprom_fixup(priv, template_sprom);\n\t\tsprom_extract(sprom, template_sprom, raw->size);\n\n\t\tpriv->devid_override = sprom_override_devid(priv, sprom,\n\t\t\t\t\t\t\t    template_sprom);\n\t} else {\n\t\tsprom->revision = 0x02;\n\t\tsprom->board_rev = 0x0017;\n\t\tsprom->country_code = 0x00;\n\t\tsprom->ant_available_bg = 0x03;\n\t\tsprom->pa0b0 = 0x15ae;\n\t\tsprom->pa0b1 = 0xfa85;\n\t\tsprom->pa0b2 = 0xfe8d;\n\t\tsprom->pa1b0 = 0xffff;\n\t\tsprom->pa1b1 = 0xffff;\n\t\tsprom->pa1b2 = 0xffff;\n\t\tsprom->gpio0 = 0xff;\n\t\tsprom->gpio1 = 0xff;\n\t\tsprom->gpio2 = 0xff;\n\t\tsprom->gpio3 = 0xff;\n\t\tsprom->maxpwr_bg = 0x4c;\n\t\tsprom->itssi_bg = 0x00;\n\t\tsprom->boardflags_lo = 0x2848;\n\t\tsprom->boardflags_hi = 0x0000;\n\t\tpriv->devid_override = 0;\n\t}\n}\n\n#if defined(CONFIG_SSB_PCIHOST)\nint b43_get_fallback_ssb_sprom(struct ssb_bus *bus, struct ssb_sprom *out)\n{\n\tstruct b43_sprom *priv = &b43_sprom;\n\n\tif (bus->bustype == SSB_BUSTYPE_PCI) {\n\t\tif (bus->host_pci->bus->number != priv->pci_bus ||\n\t\t    PCI_SLOT(bus->host_pci->devfn) != priv->pci_dev)\n\t\t\tpr_warn(\"ssb_fallback_sprom: pci bus/device num \"\n\t\t\t\t\"mismatch: expected %i/%i, but got %i/%i\\n\",\n\t\t\t\tpriv->pci_bus, priv->pci_dev,\n\t\t\t\tbus->host_pci->bus->number,\n\t\t\t\tPCI_SLOT(bus->host_pci->devfn));\n\t\tif (priv->devid_override)\n\t\t\tbus->host_pci->device = priv->sprom.dev_id;\n\t\tmemcpy(out, &priv->sprom, sizeof(struct ssb_sprom));\n\t\treturn 0;\n\t} else {\n\t\tpr_err(\"%s: unable to fill SPROM for given bustype.\\n\",\n\t\t       __func__);\n\t\treturn -EINVAL;\n\t}\n}\n#endif /* CONFIG_SSB_PCIHOST */\n\n#if defined(CONFIG_BCMA_HOST_PCI)\nint b43_get_fallback_bcma_sprom(struct bcma_bus *bus, struct ssb_sprom *out)\n{\n\tstruct b43_sprom *priv = &b43_sprom;\n\n\tif (bus->hosttype == BCMA_HOSTTYPE_PCI) {\n\t\tif (bus->host_pci->bus->number != priv->pci_bus ||\n\t\t    PCI_SLOT(bus->host_pci->devfn) != priv->pci_dev)\n\t\t\tpr_warn(\"bcma_fallback_sprom: pci bus/device num \"\n\t\t\t\t\"mismatch: expected %i/%i, but got %i/%i\\n\",\n\t\t\t\tpriv->pci_bus, priv->pci_dev,\n\t\t\t\tbus->host_pci->bus->number,\n\t\t\t\tPCI_SLOT(bus->host_pci->devfn));\n\t\tif (priv->devid_override)\n\t\t\tbus->host_pci->device = priv->sprom.dev_id;\n\t\tmemcpy(out, &priv->sprom, sizeof(struct ssb_sprom));\n\t\treturn 0;\n\t} else {\n\t\tpr_err(\"%s: unable to fill SPROM for given bustype.\\n\",\n\t\t       __func__);\n\t\treturn -EINVAL;\n\t}\n}\n#endif /* CONFIG_BCMA_HOST_PCI */\n\nstatic int b43_sprom_probe(struct platform_device *pdev)\n{\n\tstruct device *dev = &pdev->dev;\n\tstruct device_node *node = dev->of_node;\n\tstruct b43_sprom *priv = &b43_sprom;\n\tint ret;\n\n\tpriv->dev = dev;\n\n\tb43_sprom_set(priv);\n\n\tof_property_read_u32(node, \"pci-bus\", &priv->pci_bus);\n\tof_property_read_u32(node, \"pci-dev\", &priv->pci_dev);\n\n\tof_get_mac_address(node, priv->mac);\n\tif (is_valid_ether_addr(priv->mac)) {\n\t\tdev_info(dev, \"mtd mac %pM\\n\", priv->mac);\n\t} else {\n\t\trandom_ether_addr(priv->mac);\n\t\tdev_info(dev, \"random mac %pM\\n\", priv->mac);\n\t}\n\n\tmemcpy(priv->sprom.il0mac, priv->mac, ETH_ALEN);\n \tmemcpy(priv->sprom.et0mac, priv->mac, ETH_ALEN);\n \tmemcpy(priv->sprom.et1mac, priv->mac, ETH_ALEN);\n\n#if defined(CONFIG_SSB_PCIHOST)\n\tret = ssb_arch_register_fallback_sprom(&b43_get_fallback_ssb_sprom);\n\tif (ret)\n\t\treturn ret;\n#endif /* CONFIG_SSB_PCIHOST */\n\n#if defined(CONFIG_BCMA_HOST_PCI)\n\tret = bcma_arch_register_fallback_sprom(b43_get_fallback_bcma_sprom);\n\tif (ret)\n\t\treturn ret;\n#endif /* CONFIG_BCMA_HOST_PCI */\n\n\treturn 0;\n}\n\nstatic const struct of_device_id b43_sprom_of_match[] = {\n\t{ .compatible = \"brcm,bcm43xx-sprom\", .data = NULL },\n#if defined (CONFIG_SSB_PCIHOST)\n\t{ .compatible = \"brcm,bcm4306-sprom\", .data = &bcm4306_sprom, },\n\t{ .compatible = \"brcm,bcm4321-sprom\", .data = &bcm4321_sprom, },\n\t{ .compatible = \"brcm,bcm4322-sprom\", .data = &bcm4322_sprom, },\n\t{ .compatible = \"brcm,bcm43222-sprom\", .data = &bcm43222_sprom, },\n#endif /* CONFIG_BCMA_HOST_PCI */\n#if defined(CONFIG_BCMA_HOST_PCI)\n\t{ .compatible = \"brcm,bcm4313-sprom\", .data = &bcm4313_sprom, },\n\t{ .compatible = \"brcm,bcm4331-sprom\", .data = &bcm4331_sprom, },\n\t{ .compatible = \"brcm,bcm43131-sprom\", .data = &bcm43131_sprom, },\n\t{ .compatible = \"brcm,bcm43217-sprom\", .data = &bcm43217_sprom, },\n\t{ .compatible = \"brcm,bcm43225-sprom\", .data = &bcm43225_sprom, },\n\t{ .compatible = \"brcm,bcm43227-sprom\", .data = &bcm43227_sprom, },\n\t{ .compatible = \"brcm,bcm43228-sprom\", .data = &bcm43228_sprom, },\n#endif /* CONFIG_BCMA_HOST_PCI */\n\t{ /* sentinel */ }\n};\n\nstatic struct platform_driver b43_sprom_driver = {\n\t.probe = b43_sprom_probe,\n\t.driver\t= {\n\t\t.name = \"b43-sprom\",\n\t\t.of_match_table = b43_sprom_of_match,\n\t},\n};\n\nint __init b43_sprom_init(void)\n{\n\tint ret = platform_driver_register(&b43_sprom_driver);\n\tif (ret)\n\t\tpr_err(\"b43-sprom: Error registering platform driver!\\n\");\n\treturn ret;\n}\nlate_initcall(b43_sprom_init);\n"
  },
  {
    "path": "target/linux/bmips/files/arch/mips/pci/fixup-bmips.c",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later\n/*\n *  Copyright (C) 2020 Álvaro Fernández Rojas <noltari@gmail.com>\n */\n\n#include <linux/pci.h>\n\nint bmips_pci_irq = -1;\n\nint pcibios_plat_dev_init(struct pci_dev *pci_dev)\n{\n\treturn PCIBIOS_SUCCESSFUL;\n}\n\nint pcibios_map_irq(const struct pci_dev *pci_dev, u8 slot, u8 pin)\n{\n\treturn bmips_pci_irq;\n}\n"
  },
  {
    "path": "target/linux/bmips/files/drivers/net/ethernet/broadcom/bcm6368-enetsw.c",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later\n/*\n * BCM6368 Ethernet Switch Controller Driver\n *\n * Copyright (C) 2021 Álvaro Fernández Rojas <noltari@gmail.com>\n * Copyright (C) 2015 Jonas Gorski <jonas.gorski@gmail.com>\n * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>\n */\n\n#include <linux/clk.h>\n#include <linux/delay.h>\n#include <linux/dma-mapping.h>\n#include <linux/err.h>\n#include <linux/ethtool.h>\n#include <linux/if_vlan.h>\n#include <linux/interrupt.h>\n#include <linux/of_clk.h>\n#include <linux/of_net.h>\n#include <linux/platform_device.h>\n#include <linux/pm_domain.h>\n#include <linux/pm_runtime.h>\n#include <linux/reset.h>\n\n/* MTU */\n#define ENETSW_TAG_SIZE\t\t\t6\n#define ENETSW_MTU_OVERHEAD\t\t(VLAN_ETH_HLEN + VLAN_HLEN + \\\n\t\t\t\t\t ENETSW_TAG_SIZE)\n\n/* default number of descriptor */\n#define ENETSW_DEF_RX_DESC\t\t64\n#define ENETSW_DEF_TX_DESC\t\t32\n#define ENETSW_DEF_CPY_BREAK\t\t128\n\n/* maximum burst len for dma (4 bytes unit) */\n#define ENETSW_DMA_MAXBURST\t\t8\n\n/* DMA channels */\n#define DMA_CHAN_WIDTH\t\t\t0x10\n\n/* Controller Configuration Register */\n#define DMA_CFG_REG\t\t\t0x0\n#define DMA_CFG_EN_SHIFT\t\t0\n#define DMA_CFG_EN_MASK\t\t\t(1 << DMA_CFG_EN_SHIFT)\n#define DMA_CFG_FLOWCH_MASK(x)\t\t(1 << ((x >> 1) + 1))\n\n/* Flow Control Descriptor Low Threshold register */\n#define DMA_FLOWCL_REG(x)\t\t(0x4 + (x) * 6)\n\n/* Flow Control Descriptor High Threshold register */\n#define DMA_FLOWCH_REG(x)\t\t(0x8 + (x) * 6)\n\n/* Flow Control Descriptor Buffer Alloca Threshold register */\n#define DMA_BUFALLOC_REG(x)\t\t(0xc + (x) * 6)\n#define DMA_BUFALLOC_FORCE_SHIFT\t31\n#define DMA_BUFALLOC_FORCE_MASK\t\t(1 << DMA_BUFALLOC_FORCE_SHIFT)\n\n/* Channel Configuration register */\n#define DMAC_CHANCFG_REG\t\t0x0\n#define DMAC_CHANCFG_EN_SHIFT\t\t0\n#define DMAC_CHANCFG_EN_MASK\t\t(1 << DMAC_CHANCFG_EN_SHIFT)\n#define DMAC_CHANCFG_PKTHALT_SHIFT\t1\n#define DMAC_CHANCFG_PKTHALT_MASK\t(1 << DMAC_CHANCFG_PKTHALT_SHIFT)\n#define DMAC_CHANCFG_BUFHALT_SHIFT\t2\n#define DMAC_CHANCFG_BUFHALT_MASK\t(1 << DMAC_CHANCFG_BUFHALT_SHIFT)\n#define DMAC_CHANCFG_CHAINING_SHIFT\t2\n#define DMAC_CHANCFG_CHAINING_MASK\t(1 << DMAC_CHANCFG_CHAINING_SHIFT)\n#define DMAC_CHANCFG_WRAP_EN_SHIFT\t3\n#define DMAC_CHANCFG_WRAP_EN_MASK\t(1 << DMAC_CHANCFG_WRAP_EN_SHIFT)\n#define DMAC_CHANCFG_FLOWC_EN_SHIFT\t4\n#define DMAC_CHANCFG_FLOWC_EN_MASK\t(1 << DMAC_CHANCFG_FLOWC_EN_SHIFT)\n\n/* Interrupt Control/Status register */\n#define DMAC_IR_REG\t\t\t0x4\n#define DMAC_IR_BUFDONE_MASK\t\t(1 << 0)\n#define DMAC_IR_PKTDONE_MASK\t\t(1 << 1)\n#define DMAC_IR_NOTOWNER_MASK\t\t(1 << 2)\n\n/* Interrupt Mask register */\n#define DMAC_IRMASK_REG\t\t\t0x8\n\n/* Maximum Burst Length */\n#define DMAC_MAXBURST_REG\t\t0xc\n\n/* Ring Start Address register */\n#define DMAS_RSTART_REG\t\t\t0x0\n\n/* State Ram Word 2 */\n#define DMAS_SRAM2_REG\t\t\t0x4\n\n/* State Ram Word 3 */\n#define DMAS_SRAM3_REG\t\t\t0x8\n\n/* State Ram Word 4 */\n#define DMAS_SRAM4_REG\t\t\t0xc\n\nstruct bcm6368_enetsw_desc {\n\tu32 len_stat;\n\tu32 address;\n};\n\n/* control */\n#define DMADESC_LENGTH_SHIFT\t\t16\n#define DMADESC_LENGTH_MASK\t\t(0xfff << DMADESC_LENGTH_SHIFT)\n#define DMADESC_OWNER_MASK\t\t(1 << 15)\n#define DMADESC_EOP_MASK\t\t(1 << 14)\n#define DMADESC_SOP_MASK\t\t(1 << 13)\n#define DMADESC_ESOP_MASK\t\t(DMADESC_EOP_MASK | DMADESC_SOP_MASK)\n#define DMADESC_WRAP_MASK\t\t(1 << 12)\n#define DMADESC_USB_NOZERO_MASK \t(1 << 1)\n#define DMADESC_USB_ZERO_MASK\t\t(1 << 0)\n\n/* status */\n#define DMADESC_UNDER_MASK\t\t(1 << 9)\n#define DMADESC_APPEND_CRC\t\t(1 << 8)\n#define DMADESC_OVSIZE_MASK\t\t(1 << 4)\n#define DMADESC_RXER_MASK\t\t(1 << 2)\n#define DMADESC_CRC_MASK\t\t(1 << 1)\n#define DMADESC_OV_MASK\t\t\t(1 << 0)\n#define DMADESC_ERR_MASK\t\t(DMADESC_UNDER_MASK | \\\n\t\t\t\t\t DMADESC_OVSIZE_MASK | \\\n\t\t\t\t\t DMADESC_RXER_MASK | \\\n\t\t\t\t\t DMADESC_CRC_MASK | \\\n\t\t\t\t\t DMADESC_OV_MASK)\n\nstruct bcm6368_enetsw {\n\tvoid __iomem *dma_base;\n\tvoid __iomem *dma_chan;\n\tvoid __iomem *dma_sram;\n\n\tstruct device **pm;\n\tstruct device_link **link_pm;\n\tint num_pms;\n\n\tstruct clk **clock;\n\tunsigned int num_clocks;\n\n\tstruct reset_control **reset;\n\tunsigned int num_resets;\n\n\tint copybreak;\n\n\tint irq_rx;\n\tint irq_tx;\n\n\t/* hw view of rx & tx dma ring */\n\tdma_addr_t rx_desc_dma;\n\tdma_addr_t tx_desc_dma;\n\n\t/* allocated size (in bytes) for rx & tx dma ring */\n\tunsigned int rx_desc_alloc_size;\n\tunsigned int tx_desc_alloc_size;\n\n\tstruct napi_struct napi;\n\n\t/* dma channel id for rx */\n\tint rx_chan;\n\n\t/* number of dma desc in rx ring */\n\tint rx_ring_size;\n\n\t/* cpu view of rx dma ring */\n\tstruct bcm6368_enetsw_desc *rx_desc_cpu;\n\n\t/* current number of armed descriptor given to hardware for rx */\n\tint rx_desc_count;\n\n\t/* next rx descriptor to fetch from hardware */\n\tint rx_curr_desc;\n\n\t/* next dirty rx descriptor to refill */\n\tint rx_dirty_desc;\n\n\t/* size of allocated rx skbs */\n\tunsigned int rx_skb_size;\n\n\t/* list of skb given to hw for rx */\n\tstruct sk_buff **rx_skb;\n\n\t/* used when rx skb allocation failed, so we defer rx queue\n\t * refill */\n\tstruct timer_list rx_timeout;\n\n\t/* lock rx_timeout against rx normal operation */\n\tspinlock_t rx_lock;\n\n\t/* dma channel id for tx */\n\tint tx_chan;\n\n\t/* number of dma desc in tx ring */\n\tint tx_ring_size;\n\n\t/* maximum dma burst size */\n\tint dma_maxburst;\n\n\t/* cpu view of rx dma ring */\n\tstruct bcm6368_enetsw_desc *tx_desc_cpu;\n\n\t/* number of available descriptor for tx */\n\tint tx_desc_count;\n\n\t/* next tx descriptor avaiable */\n\tint tx_curr_desc;\n\n\t/* next dirty tx descriptor to reclaim */\n\tint tx_dirty_desc;\n\n\t/* list of skb given to hw for tx */\n\tstruct sk_buff **tx_skb;\n\n\t/* lock used by tx reclaim and xmit */\n\tspinlock_t tx_lock;\n\n\t/* network device reference */\n\tstruct net_device *net_dev;\n\n\t/* platform device reference */\n\tstruct platform_device *pdev;\n\n\t/* dma channel enable mask */\n\tu32 dma_chan_en_mask;\n\n\t/* dma channel interrupt mask */\n\tu32 dma_chan_int_mask;\n\n\t/* dma channel width */\n\tunsigned int dma_chan_width;\n};\n\nstatic inline void dma_writel(struct bcm6368_enetsw *priv, u32 val, u32 off)\n{\n\t__raw_writel(val, priv->dma_base + off);\n}\n\nstatic inline u32 dma_readl(struct bcm6368_enetsw *priv, u32 off, int chan)\n{\n\treturn __raw_readl(priv->dma_chan + off + chan * priv->dma_chan_width);\n}\n\nstatic inline void dmac_writel(struct bcm6368_enetsw *priv, u32 val,\n\t\t\t\t    u32 off, int chan)\n{\n\t__raw_writel(val, priv->dma_chan + off + chan * priv->dma_chan_width);\n}\n\nstatic inline void dmas_writel(struct bcm6368_enetsw *priv, u32 val,\n\t\t\t\t    u32 off, int chan)\n{\n\t__raw_writel(val, priv->dma_sram + off + chan * priv->dma_chan_width);\n}\n\n/*\n * refill rx queue\n */\nstatic int bcm6368_enetsw_refill_rx(struct net_device *dev)\n{\n\tstruct bcm6368_enetsw *priv = netdev_priv(dev);\n\n\twhile (priv->rx_desc_count < priv->rx_ring_size) {\n\t\tstruct bcm6368_enetsw_desc *desc;\n\t\tstruct sk_buff *skb;\n\t\tdma_addr_t p;\n\t\tint desc_idx;\n\t\tu32 len_stat;\n\n\t\tdesc_idx = priv->rx_dirty_desc;\n\t\tdesc = &priv->rx_desc_cpu[desc_idx];\n\n\t\tif (!priv->rx_skb[desc_idx]) {\n\t\t\tskb = netdev_alloc_skb(dev, priv->rx_skb_size);\n\t\t\tif (!skb)\n\t\t\t\tbreak;\n\t\t\tpriv->rx_skb[desc_idx] = skb;\n\t\t\tp = dma_map_single(&priv->pdev->dev, skb->data,\n\t\t\t\t\t   priv->rx_skb_size,\n\t\t\t\t\t   DMA_FROM_DEVICE);\n\t\t\tdesc->address = p;\n\t\t}\n\n\t\tlen_stat = priv->rx_skb_size << DMADESC_LENGTH_SHIFT;\n\t\tlen_stat |= DMADESC_OWNER_MASK;\n\t\tif (priv->rx_dirty_desc == priv->rx_ring_size - 1) {\n\t\t\tlen_stat |= DMADESC_WRAP_MASK;\n\t\t\tpriv->rx_dirty_desc = 0;\n\t\t} else {\n\t\t\tpriv->rx_dirty_desc++;\n\t\t}\n\t\twmb();\n\t\tdesc->len_stat = len_stat;\n\n\t\tpriv->rx_desc_count++;\n\n\t\t/* tell dma engine we allocated one buffer */\n\t\tdma_writel(priv, 1, DMA_BUFALLOC_REG(priv->rx_chan));\n\t}\n\n\t/* If rx ring is still empty, set a timer to try allocating\n\t * again at a later time. */\n\tif (priv->rx_desc_count == 0 && netif_running(dev)) {\n\t\tdev_warn(&priv->pdev->dev, \"unable to refill rx ring\\n\");\n\t\tpriv->rx_timeout.expires = jiffies + HZ;\n\t\tadd_timer(&priv->rx_timeout);\n\t}\n\n\treturn 0;\n}\n\n/*\n * timer callback to defer refill rx queue in case we're OOM\n */\nstatic void bcm6368_enetsw_refill_rx_timer(struct timer_list *t)\n{\n\tstruct bcm6368_enetsw *priv = from_timer(priv, t, rx_timeout);\n\tstruct net_device *dev = priv->net_dev;\n\n\tspin_lock(&priv->rx_lock);\n\tbcm6368_enetsw_refill_rx(dev);\n\tspin_unlock(&priv->rx_lock);\n}\n\n/*\n * extract packet from rx queue\n */\nstatic int bcm6368_enetsw_receive_queue(struct net_device *dev, int budget)\n{\n\tstruct bcm6368_enetsw *priv = netdev_priv(dev);\n\tstruct device *kdev = &priv->pdev->dev;\n\tint processed = 0;\n\n\t/* don't scan ring further than number of refilled\n\t * descriptor */\n\tif (budget > priv->rx_desc_count)\n\t\tbudget = priv->rx_desc_count;\n\n\tdo {\n\t\tstruct bcm6368_enetsw_desc *desc;\n\t\tstruct sk_buff *skb;\n\t\tint desc_idx;\n\t\tu32 len_stat;\n\t\tunsigned int len;\n\n\t\tdesc_idx = priv->rx_curr_desc;\n\t\tdesc = &priv->rx_desc_cpu[desc_idx];\n\n\t\t/* make sure we actually read the descriptor status at\n\t\t * each loop */\n\t\trmb();\n\n\t\tlen_stat = desc->len_stat;\n\n\t\t/* break if dma ownership belongs to hw */\n\t\tif (len_stat & DMADESC_OWNER_MASK)\n\t\t\tbreak;\n\n\t\tprocessed++;\n\t\tpriv->rx_curr_desc++;\n\t\tif (priv->rx_curr_desc == priv->rx_ring_size)\n\t\t\tpriv->rx_curr_desc = 0;\n\t\tpriv->rx_desc_count--;\n\n\t\t/* if the packet does not have start of packet _and_\n\t\t * end of packet flag set, then just recycle it */\n\t\tif ((len_stat & DMADESC_ESOP_MASK) != DMADESC_ESOP_MASK) {\n\t\t\tdev->stats.rx_dropped++;\n\t\t\tcontinue;\n\t\t}\n\n\t\t/* valid packet */\n\t\tskb = priv->rx_skb[desc_idx];\n\t\tlen = (len_stat & DMADESC_LENGTH_MASK)\n\t\t      >> DMADESC_LENGTH_SHIFT;\n\t\t/* don't include FCS */\n\t\tlen -= 4;\n\n\t\tif (len < priv->copybreak) {\n\t\t\tstruct sk_buff *nskb;\n\n\t\t\tnskb = napi_alloc_skb(&priv->napi, len);\n\t\t\tif (!nskb) {\n\t\t\t\t/* forget packet, just rearm desc */\n\t\t\t\tdev->stats.rx_dropped++;\n\t\t\t\tcontinue;\n\t\t\t}\n\n\t\t\tdma_sync_single_for_cpu(kdev, desc->address,\n\t\t\t\t\t\tlen, DMA_FROM_DEVICE);\n\t\t\tmemcpy(nskb->data, skb->data, len);\n\t\t\tdma_sync_single_for_device(kdev, desc->address,\n\t\t\t\t\t\t   len, DMA_FROM_DEVICE);\n\t\t\tskb = nskb;\n\t\t} else {\n\t\t\tdma_unmap_single(&priv->pdev->dev, desc->address,\n\t\t\t\t\t priv->rx_skb_size, DMA_FROM_DEVICE);\n\t\t\tpriv->rx_skb[desc_idx] = NULL;\n\t\t}\n\n\t\tskb_put(skb, len);\n\t\tskb->protocol = eth_type_trans(skb, dev);\n\t\tdev->stats.rx_packets++;\n\t\tdev->stats.rx_bytes += len;\n\t\tnetif_receive_skb(skb);\n\t} while (--budget > 0);\n\n\tif (processed || !priv->rx_desc_count) {\n\t\tbcm6368_enetsw_refill_rx(dev);\n\n\t\t/* kick rx dma */\n\t\tdmac_writel(priv, priv->dma_chan_en_mask,\n\t\t\t    DMAC_CHANCFG_REG, priv->rx_chan);\n\t}\n\n\treturn processed;\n}\n\n/*\n * try to or force reclaim of transmitted buffers\n */\nstatic int bcm6368_enetsw_tx_reclaim(struct net_device *dev, int force)\n{\n\tstruct bcm6368_enetsw *priv = netdev_priv(dev);\n\tint released = 0;\n\n\twhile (priv->tx_desc_count < priv->tx_ring_size) {\n\t\tstruct bcm6368_enetsw_desc *desc;\n\t\tstruct sk_buff *skb;\n\n\t\t/* We run in a bh and fight against start_xmit, which\n\t\t * is called with bh disabled */\n\t\tspin_lock(&priv->tx_lock);\n\n\t\tdesc = &priv->tx_desc_cpu[priv->tx_dirty_desc];\n\n\t\tif (!force && (desc->len_stat & DMADESC_OWNER_MASK)) {\n\t\t\tspin_unlock(&priv->tx_lock);\n\t\t\tbreak;\n\t\t}\n\n\t\t/* ensure other field of the descriptor were not read\n\t\t * before we checked ownership */\n\t\trmb();\n\n\t\tskb = priv->tx_skb[priv->tx_dirty_desc];\n\t\tpriv->tx_skb[priv->tx_dirty_desc] = NULL;\n\t\tdma_unmap_single(&priv->pdev->dev, desc->address, skb->len,\n\t\t\t\t DMA_TO_DEVICE);\n\n\t\tpriv->tx_dirty_desc++;\n\t\tif (priv->tx_dirty_desc == priv->tx_ring_size)\n\t\t\tpriv->tx_dirty_desc = 0;\n\t\tpriv->tx_desc_count++;\n\n\t\tspin_unlock(&priv->tx_lock);\n\n\t\tif (desc->len_stat & DMADESC_UNDER_MASK)\n\t\t\tdev->stats.tx_errors++;\n\n\t\tdev_kfree_skb(skb);\n\t\treleased++;\n\t}\n\n\tif (netif_queue_stopped(dev) && released)\n\t\tnetif_wake_queue(dev);\n\n\treturn released;\n}\n\n/*\n * poll func, called by network core\n */\nstatic int bcm6368_enetsw_poll(struct napi_struct *napi, int budget)\n{\n\tstruct bcm6368_enetsw *priv = container_of(napi, struct bcm6368_enetsw, napi);\n\tstruct net_device *dev = priv->net_dev;\n\tint rx_work_done;\n\n\t/* ack interrupts */\n\tdmac_writel(priv, priv->dma_chan_int_mask,\n\t\t\t DMAC_IR_REG, priv->rx_chan);\n\tdmac_writel(priv, priv->dma_chan_int_mask,\n\t\t\t DMAC_IR_REG, priv->tx_chan);\n\n\t/* reclaim sent skb */\n\tbcm6368_enetsw_tx_reclaim(dev, 0);\n\n\tspin_lock(&priv->rx_lock);\n\trx_work_done = bcm6368_enetsw_receive_queue(dev, budget);\n\tspin_unlock(&priv->rx_lock);\n\n\tif (rx_work_done >= budget) {\n\t\t/* rx queue is not yet empty/clean */\n\t\treturn rx_work_done;\n\t}\n\n\t/* no more packet in rx/tx queue, remove device from poll\n\t * queue */\n\tnapi_complete_done(napi, rx_work_done);\n\n\t/* restore rx/tx interrupt */\n\tdmac_writel(priv, priv->dma_chan_int_mask,\n\t\t\t DMAC_IRMASK_REG, priv->rx_chan);\n\tdmac_writel(priv, priv->dma_chan_int_mask,\n\t\t\t DMAC_IRMASK_REG, priv->tx_chan);\n\n\treturn rx_work_done;\n}\n\n/*\n * rx/tx dma interrupt handler\n */\nstatic irqreturn_t bcm6368_enetsw_isr_dma(int irq, void *dev_id)\n{\n\tstruct net_device *dev = dev_id;\n\tstruct bcm6368_enetsw *priv = netdev_priv(dev);\n\n\t/* mask rx/tx interrupts */\n\tdmac_writel(priv, 0, DMAC_IRMASK_REG, priv->rx_chan);\n\tdmac_writel(priv, 0, DMAC_IRMASK_REG, priv->tx_chan);\n\n\tnapi_schedule(&priv->napi);\n\n\treturn IRQ_HANDLED;\n}\n\n/*\n * tx request callback\n */\nstatic netdev_tx_t\nbcm6368_enetsw_start_xmit(struct sk_buff *skb, struct net_device *dev)\n{\n\tstruct bcm6368_enetsw *priv = netdev_priv(dev);\n\tstruct bcm6368_enetsw_desc *desc;\n\tu32 len_stat;\n\tnetdev_tx_t ret;\n\n\t/* lock against tx reclaim */\n\tspin_lock(&priv->tx_lock);\n\n\t/* make sure the tx hw queue is not full, should not happen\n\t * since we stop queue before it's the case */\n\tif (unlikely(!priv->tx_desc_count)) {\n\t\tnetif_stop_queue(dev);\n\t\tdev_err(&priv->pdev->dev, \"xmit called with no tx desc \"\n\t\t\t\"available?\\n\");\n\t\tret = NETDEV_TX_BUSY;\n\t\tgoto out_unlock;\n\t}\n\n\t/* pad small packets */\n\tif (skb->len < (ETH_ZLEN + ETH_FCS_LEN)) {\n\t\tint needed = (ETH_ZLEN + ETH_FCS_LEN) - skb->len;\n\t\tchar *data;\n\n\t\tif (unlikely(skb_tailroom(skb) < needed)) {\n\t\t\tstruct sk_buff *nskb;\n\n\t\t\tnskb = skb_copy_expand(skb, 0, needed, GFP_ATOMIC);\n\t\t\tif (!nskb) {\n\t\t\t\tret = NETDEV_TX_BUSY;\n\t\t\t\tgoto out_unlock;\n\t\t\t}\n\n\t\t\tdev_kfree_skb(skb);\n\t\t\tskb = nskb;\n\t\t}\n\t\tdata = skb_put_zero(skb, needed);\n\t}\n\n\t/* point to the next available desc */\n\tdesc = &priv->tx_desc_cpu[priv->tx_curr_desc];\n\tpriv->tx_skb[priv->tx_curr_desc] = skb;\n\n\t/* fill descriptor */\n\tdesc->address = dma_map_single(&priv->pdev->dev, skb->data, skb->len,\n\t\t\t\t       DMA_TO_DEVICE);\n\n\tlen_stat = (skb->len << DMADESC_LENGTH_SHIFT) & DMADESC_LENGTH_MASK;\n\tlen_stat |= DMADESC_ESOP_MASK | DMADESC_APPEND_CRC |\n\t\t    DMADESC_OWNER_MASK;\n\n\tpriv->tx_curr_desc++;\n\tif (priv->tx_curr_desc == priv->tx_ring_size) {\n\t\tpriv->tx_curr_desc = 0;\n\t\tlen_stat |= DMADESC_WRAP_MASK;\n\t}\n\tpriv->tx_desc_count--;\n\n\t/* dma might be already polling, make sure we update desc\n\t * fields in correct order */\n\twmb();\n\tdesc->len_stat = len_stat;\n\twmb();\n\n\t/* kick tx dma */\n\tdmac_writel(priv, priv->dma_chan_en_mask, DMAC_CHANCFG_REG,\n\t\t    priv->tx_chan);\n\n\t/* stop queue if no more desc available */\n\tif (!priv->tx_desc_count)\n\t\tnetif_stop_queue(dev);\n\n\tdev->stats.tx_bytes += skb->len;\n\tdev->stats.tx_packets++;\n\tret = NETDEV_TX_OK;\n\nout_unlock:\n\tspin_unlock(&priv->tx_lock);\n\treturn ret;\n}\n\n/*\n * disable dma in given channel\n */\nstatic void bcm6368_enetsw_disable_dma(struct bcm6368_enetsw *priv, int chan)\n{\n\tint limit = 1000;\n\n\tdmac_writel(priv, 0, DMAC_CHANCFG_REG, chan);\n\n\tdo {\n\t\tu32 val;\n\n\t\tval = dma_readl(priv, DMAC_CHANCFG_REG, chan);\n\t\tif (!(val & DMAC_CHANCFG_EN_MASK))\n\t\t\tbreak;\n\n\t\tudelay(1);\n\t} while (limit--);\n}\n\nstatic int bcm6368_enetsw_open(struct net_device *dev)\n{\n\tstruct bcm6368_enetsw *priv = netdev_priv(dev);\n\tstruct device *kdev = &priv->pdev->dev;\n\tint i, ret;\n\tunsigned int size;\n\tvoid *p;\n\tu32 val;\n\n\t/* mask all interrupts and request them */\n\tdmac_writel(priv, 0, DMAC_IRMASK_REG, priv->rx_chan);\n\tdmac_writel(priv, 0, DMAC_IRMASK_REG, priv->tx_chan);\n\n\tret = request_irq(priv->irq_rx, bcm6368_enetsw_isr_dma,\n\t\t\t  0, dev->name, dev);\n\tif (ret)\n\t\tgoto out_freeirq;\n\n\tif (priv->irq_tx != -1) {\n\t\tret = request_irq(priv->irq_tx, bcm6368_enetsw_isr_dma,\n\t\t\t\t  0, dev->name, dev);\n\t\tif (ret)\n\t\t\tgoto out_freeirq_rx;\n\t}\n\n\t/* allocate rx dma ring */\n\tsize = priv->rx_ring_size * sizeof(struct bcm6368_enetsw_desc);\n\tp = dma_alloc_coherent(kdev, size, &priv->rx_desc_dma, GFP_KERNEL);\n\tif (!p) {\n\t\tdev_err(kdev, \"cannot allocate rx ring %u\\n\", size);\n\t\tret = -ENOMEM;\n\t\tgoto out_freeirq_tx;\n\t}\n\n\tmemset(p, 0, size);\n\tpriv->rx_desc_alloc_size = size;\n\tpriv->rx_desc_cpu = p;\n\n\t/* allocate tx dma ring */\n\tsize = priv->tx_ring_size * sizeof(struct bcm6368_enetsw_desc);\n\tp = dma_alloc_coherent(kdev, size, &priv->tx_desc_dma, GFP_KERNEL);\n\tif (!p) {\n\t\tdev_err(kdev, \"cannot allocate tx ring\\n\");\n\t\tret = -ENOMEM;\n\t\tgoto out_free_rx_ring;\n\t}\n\n\tmemset(p, 0, size);\n\tpriv->tx_desc_alloc_size = size;\n\tpriv->tx_desc_cpu = p;\n\n\tpriv->tx_skb = kzalloc(sizeof(struct sk_buff *) * priv->tx_ring_size,\n\t\t\t       GFP_KERNEL);\n\tif (!priv->tx_skb) {\n\t\tdev_err(kdev, \"cannot allocate rx skb queue\\n\");\n\t\tret = -ENOMEM;\n\t\tgoto out_free_tx_ring;\n\t}\n\n\tpriv->tx_desc_count = priv->tx_ring_size;\n\tpriv->tx_dirty_desc = 0;\n\tpriv->tx_curr_desc = 0;\n\tspin_lock_init(&priv->tx_lock);\n\n\t/* init & fill rx ring with skbs */\n\tpriv->rx_skb = kzalloc(sizeof(struct sk_buff *) * priv->rx_ring_size,\n\t\t\t       GFP_KERNEL);\n\tif (!priv->rx_skb) {\n\t\tdev_err(kdev, \"cannot allocate rx skb queue\\n\");\n\t\tret = -ENOMEM;\n\t\tgoto out_free_tx_skb;\n\t}\n\n\tpriv->rx_desc_count = 0;\n\tpriv->rx_dirty_desc = 0;\n\tpriv->rx_curr_desc = 0;\n\n\t/* initialize flow control buffer allocation */\n\tdma_writel(priv, DMA_BUFALLOC_FORCE_MASK | 0,\n\t\t   DMA_BUFALLOC_REG(priv->rx_chan));\n\n\tif (bcm6368_enetsw_refill_rx(dev)) {\n\t\tdev_err(kdev, \"cannot allocate rx skb queue\\n\");\n\t\tret = -ENOMEM;\n\t\tgoto out;\n\t}\n\n\t/* write rx & tx ring addresses */\n\tdmas_writel(priv, priv->rx_desc_dma,\n\t\t    DMAS_RSTART_REG, priv->rx_chan);\n\tdmas_writel(priv, priv->tx_desc_dma,\n\t\t    DMAS_RSTART_REG, priv->tx_chan);\n\n\t/* clear remaining state ram for rx & tx channel */\n\tdmas_writel(priv, 0, DMAS_SRAM2_REG, priv->rx_chan);\n\tdmas_writel(priv, 0, DMAS_SRAM2_REG, priv->tx_chan);\n\tdmas_writel(priv, 0, DMAS_SRAM3_REG, priv->rx_chan);\n\tdmas_writel(priv, 0, DMAS_SRAM3_REG, priv->tx_chan);\n\tdmas_writel(priv, 0, DMAS_SRAM4_REG, priv->rx_chan);\n\tdmas_writel(priv, 0, DMAS_SRAM4_REG, priv->tx_chan);\n\n\t/* set dma maximum burst len */\n\tdmac_writel(priv, priv->dma_maxburst,\n\t\t    DMAC_MAXBURST_REG, priv->rx_chan);\n\tdmac_writel(priv, priv->dma_maxburst,\n\t\t    DMAC_MAXBURST_REG, priv->tx_chan);\n\n\t/* set flow control low/high threshold to 1/3 / 2/3 */\n\tval = priv->rx_ring_size / 3;\n\tdma_writel(priv, val, DMA_FLOWCL_REG(priv->rx_chan));\n\tval = (priv->rx_ring_size * 2) / 3;\n\tdma_writel(priv, val, DMA_FLOWCH_REG(priv->rx_chan));\n\n\t/* all set, enable mac and interrupts, start dma engine and\n\t * kick rx dma channel\n\t */\n\twmb();\n\tdma_writel(priv, DMA_CFG_EN_MASK, DMA_CFG_REG);\n\tdmac_writel(priv, DMAC_CHANCFG_EN_MASK,\n\t\t    DMAC_CHANCFG_REG, priv->rx_chan);\n\n\t/* watch \"packet transferred\" interrupt in rx and tx */\n\tdmac_writel(priv, DMAC_IR_PKTDONE_MASK,\n\t\t    DMAC_IR_REG, priv->rx_chan);\n\tdmac_writel(priv, DMAC_IR_PKTDONE_MASK,\n\t\t    DMAC_IR_REG, priv->tx_chan);\n\n\t/* make sure we enable napi before rx interrupt  */\n\tnapi_enable(&priv->napi);\n\n\tdmac_writel(priv, DMAC_IR_PKTDONE_MASK,\n\t\t    DMAC_IRMASK_REG, priv->rx_chan);\n\tdmac_writel(priv, DMAC_IR_PKTDONE_MASK,\n\t\t    DMAC_IRMASK_REG, priv->tx_chan);\n\n\tnetif_carrier_on(dev);\n\tnetif_start_queue(dev);\n\n\treturn 0;\n\nout:\n\tfor (i = 0; i < priv->rx_ring_size; i++) {\n\t\tstruct bcm6368_enetsw_desc *desc;\n\n\t\tif (!priv->rx_skb[i])\n\t\t\tcontinue;\n\n\t\tdesc = &priv->rx_desc_cpu[i];\n\t\tdma_unmap_single(kdev, desc->address, priv->rx_skb_size,\n\t\t\t\t DMA_FROM_DEVICE);\n\t\tkfree_skb(priv->rx_skb[i]);\n\t}\n\tkfree(priv->rx_skb);\n\nout_free_tx_skb:\n\tkfree(priv->tx_skb);\n\nout_free_tx_ring:\n\tdma_free_coherent(kdev, priv->tx_desc_alloc_size,\n\t\t\t  priv->tx_desc_cpu, priv->tx_desc_dma);\n\nout_free_rx_ring:\n\tdma_free_coherent(kdev, priv->rx_desc_alloc_size,\n\t\t\t  priv->rx_desc_cpu, priv->rx_desc_dma);\n\nout_freeirq_tx:\n\tif (priv->irq_tx != -1)\n\t\tfree_irq(priv->irq_tx, dev);\n\nout_freeirq_rx:\n\tfree_irq(priv->irq_rx, dev);\n\nout_freeirq:\n\treturn ret;\n}\n\nstatic int bcm6368_enetsw_stop(struct net_device *dev)\n{\n\tstruct bcm6368_enetsw *priv = netdev_priv(dev);\n\tstruct device *kdev = &priv->pdev->dev;\n\tint i;\n\n\tnetif_stop_queue(dev);\n\tnapi_disable(&priv->napi);\n\tdel_timer_sync(&priv->rx_timeout);\n\n\t/* mask all interrupts */\n\tdmac_writel(priv, 0, DMAC_IRMASK_REG, priv->rx_chan);\n\tdmac_writel(priv, 0, DMAC_IRMASK_REG, priv->tx_chan);\n\n\t/* disable dma & mac */\n\tbcm6368_enetsw_disable_dma(priv, priv->tx_chan);\n\tbcm6368_enetsw_disable_dma(priv, priv->rx_chan);\n\n\t/* force reclaim of all tx buffers */\n\tbcm6368_enetsw_tx_reclaim(dev, 1);\n\n\t/* free the rx skb ring */\n\tfor (i = 0; i < priv->rx_ring_size; i++) {\n\t\tstruct bcm6368_enetsw_desc *desc;\n\n\t\tif (!priv->rx_skb[i])\n\t\t\tcontinue;\n\n\t\tdesc = &priv->rx_desc_cpu[i];\n\t\tdma_unmap_single_attrs(kdev, desc->address, priv->rx_skb_size,\n\t\t\t\t       DMA_FROM_DEVICE,\n\t\t\t\t       DMA_ATTR_SKIP_CPU_SYNC);\n\t\tkfree_skb(priv->rx_skb[i]);\n\t}\n\n\t/* free remaining allocated memory */\n\tkfree(priv->rx_skb);\n\tkfree(priv->tx_skb);\n\tdma_free_coherent(kdev, priv->rx_desc_alloc_size,\n\t\t\t  priv->rx_desc_cpu, priv->rx_desc_dma);\n\tdma_free_coherent(kdev, priv->tx_desc_alloc_size,\n\t\t\t  priv->tx_desc_cpu, priv->tx_desc_dma);\n\tif (priv->irq_tx != -1)\n\t\tfree_irq(priv->irq_tx, dev);\n\tfree_irq(priv->irq_rx, dev);\n\n\treturn 0;\n}\n\nstatic const struct net_device_ops bcm6368_enetsw_ops = {\n\t.ndo_open = bcm6368_enetsw_open,\n\t.ndo_stop = bcm6368_enetsw_stop,\n\t.ndo_start_xmit = bcm6368_enetsw_start_xmit,\n};\n\nstatic int bcm6368_enetsw_probe(struct platform_device *pdev)\n{\n\tstruct bcm6368_enetsw *priv;\n\tstruct device *dev = &pdev->dev;\n\tstruct device_node *node = dev->of_node;\n\tstruct net_device *ndev;\n\tstruct resource *res;\n\tunsigned i;\n\tint ret;\n\n\tndev = alloc_etherdev(sizeof(*priv));\n\tif (!ndev)\n\t\treturn -ENOMEM;\n\n\tpriv = netdev_priv(ndev);\n\n\tpriv->num_pms = of_count_phandle_with_args(node, \"power-domains\",\n\t\t\t\t\t\t   \"#power-domain-cells\");\n\tif (priv->num_pms > 1) {\n\t\tpriv->pm = devm_kcalloc(dev, priv->num_pms,\n\t\t\t\t\tsizeof(struct device *), GFP_KERNEL);\n\t\tif (!priv->pm)\n\t\t\treturn -ENOMEM;\n\n\t\tpriv->link_pm = devm_kcalloc(dev, priv->num_pms,\n\t\t\t\t\t     sizeof(struct device_link *),\n\t\t\t\t\t     GFP_KERNEL);\n\t\tif (!priv->link_pm)\n\t\t\treturn -ENOMEM;\n\n\t\tfor (i = 0; i < priv->num_pms; i++) {\n\t\t\tpriv->pm[i] = genpd_dev_pm_attach_by_id(dev, i);\n\t\t\tif (IS_ERR(priv->pm[i])) {\n\t\t\t\tdev_err(dev, \"error getting pm %d\\n\", i);\n\t\t\t\treturn -EINVAL;\n\t\t\t}\n\n\t\t\tpriv->link_pm[i] = device_link_add(dev, priv->pm[i],\n\t\t\t\tDL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME |\n\t\t\t\tDL_FLAG_RPM_ACTIVE);\n\t\t}\n\t}\n\n\tpm_runtime_enable(dev);\n\tpm_runtime_no_callbacks(dev);\n\tret = pm_runtime_get_sync(dev);\n\tif (ret < 0) {\n\t\tpm_runtime_disable(dev);\n\t\tdev_info(dev, \"PM prober defer: ret=%d\\n\", ret);\n\t\treturn -EPROBE_DEFER;\n\t}\n\n\tres = platform_get_resource_byname(pdev, IORESOURCE_MEM, \"dma\");\n\tpriv->dma_base = devm_ioremap_resource(dev, res);\n\tif (IS_ERR(priv->dma_base))\n\t\treturn PTR_ERR(priv->dma_base);\n\n\tres = platform_get_resource_byname(pdev, IORESOURCE_MEM,\n\t\t\t\t\t   \"dma-channels\");\n\tpriv->dma_chan = devm_ioremap_resource(dev, res);\n\tif (IS_ERR(priv->dma_chan))\n\t\treturn PTR_ERR(priv->dma_chan);\n\n\tres = platform_get_resource_byname(pdev, IORESOURCE_MEM, \"dma-sram\");\n\tpriv->dma_sram = devm_ioremap_resource(dev, res);\n\tif (IS_ERR(priv->dma_sram))\n\t\treturn PTR_ERR(priv->dma_sram);\n\n\tpriv->irq_rx = platform_get_irq_byname(pdev, \"rx\");\n\tif (!priv->irq_rx)\n\t\treturn -ENODEV;\n\n\tpriv->irq_tx = platform_get_irq_byname(pdev, \"tx\");\n\tif (!priv->irq_tx)\n\t\treturn -ENODEV;\n\telse if (priv->irq_tx < 0)\n\t\tpriv->irq_tx = -1;\n\n\tif (device_property_read_u32(dev, \"dma-rx\", &priv->rx_chan))\n\t\treturn -ENODEV;\n\n\tif (device_property_read_u32(dev, \"dma-tx\", &priv->tx_chan))\n\t\treturn -ENODEV;\n\n\tpriv->rx_ring_size = ENETSW_DEF_RX_DESC;\n\tpriv->tx_ring_size = ENETSW_DEF_TX_DESC;\n\n\tpriv->dma_maxburst = ENETSW_DMA_MAXBURST;\n\n\tpriv->copybreak = ENETSW_DEF_CPY_BREAK;\n\n\tpriv->dma_chan_en_mask = DMAC_CHANCFG_EN_MASK;\n\tpriv->dma_chan_int_mask = DMAC_IR_PKTDONE_MASK;\n\tpriv->dma_chan_width = DMA_CHAN_WIDTH;\n\n\tof_get_mac_address(node, ndev->dev_addr);\n\tif (is_valid_ether_addr(ndev->dev_addr)) {\n\t\tdev_info(dev, \"mtd mac %pM\\n\", ndev->dev_addr);\n\t} else {\n\t\trandom_ether_addr(ndev->dev_addr);\n\t\tdev_info(dev, \"random mac %pM\\n\", ndev->dev_addr);\n\t}\n\n\tpriv->rx_skb_size = ALIGN(ndev->mtu + ENETSW_MTU_OVERHEAD,\n\t\t\t\t  priv->dma_maxburst * 4);\n\n\tpriv->num_clocks = of_clk_get_parent_count(node);\n\tif (priv->num_clocks) {\n\t\tpriv->clock = devm_kcalloc(dev, priv->num_clocks,\n\t\t\t\t\t   sizeof(struct clk *), GFP_KERNEL);\n\t\tif (!priv->clock)\n\t\t\treturn -ENOMEM;\n\t}\n\tfor (i = 0; i < priv->num_clocks; i++) {\n\t\tpriv->clock[i] = of_clk_get(node, i);\n\t\tif (IS_ERR(priv->clock[i])) {\n\t\t\tdev_err(dev, \"error getting clock %d\\n\", i);\n\t\t\treturn -EINVAL;\n\t\t}\n\n\t\tret = clk_prepare_enable(priv->clock[i]);\n\t\tif (ret) {\n\t\t\tdev_err(dev, \"error enabling clock %d\\n\", i);\n\t\t\treturn ret;\n\t\t}\n\t}\n\n\tpriv->num_resets = of_count_phandle_with_args(node, \"resets\",\n\t\t\t\t\t\t      \"#reset-cells\");\n\tif (priv->num_resets) {\n\t\tpriv->reset = devm_kcalloc(dev, priv->num_resets,\n\t\t\t\t\t   sizeof(struct reset_control *),\n\t\t\t\t\t   GFP_KERNEL);\n\t\tif (!priv->reset)\n\t\t\treturn -ENOMEM;\n\t}\n\tfor (i = 0; i < priv->num_resets; i++) {\n\t\tpriv->reset[i] = devm_reset_control_get_by_index(dev, i);\n\t\tif (IS_ERR(priv->reset[i])) {\n\t\t\tdev_err(dev, \"error getting reset %d\\n\", i);\n\t\t\treturn -EINVAL;\n\t\t}\n\n\t\tret = reset_control_reset(priv->reset[i]);\n\t\tif (ret) {\n\t\t\tdev_err(dev, \"error performing reset %d\\n\", i);\n\t\t\treturn ret;\n\t\t}\n\t}\n\n\tspin_lock_init(&priv->rx_lock);\n\n\ttimer_setup(&priv->rx_timeout, bcm6368_enetsw_refill_rx_timer, 0);\n\n\t/* register netdevice */\n\tndev->netdev_ops = &bcm6368_enetsw_ops;\n\tndev->min_mtu = ETH_ZLEN;\n\tndev->mtu = ETH_DATA_LEN + ENETSW_TAG_SIZE;\n\tndev->max_mtu = ETH_DATA_LEN + ENETSW_TAG_SIZE;\n\tnetif_napi_add(ndev, &priv->napi, bcm6368_enetsw_poll, 16);\n\tSET_NETDEV_DEV(ndev, dev);\n\n\tret = register_netdev(ndev);\n\tif (ret)\n\t\tgoto out_disable_clk;\n\n\tnetif_carrier_off(ndev);\n\tplatform_set_drvdata(pdev, ndev);\n\tpriv->pdev = pdev;\n\tpriv->net_dev = ndev;\n\n\treturn 0;\n\nout_disable_clk:\n\tfor (i = 0; i < priv->num_resets; i++)\n\t\treset_control_assert(priv->reset[i]);\n\n\tfor (i = 0; i < priv->num_clocks; i++)\n\t\tclk_disable_unprepare(priv->clock[i]);\n\n\treturn ret;\n}\n\nstatic int bcm6368_enetsw_remove(struct platform_device *pdev)\n{\n\tstruct device *dev = &pdev->dev;\n\tstruct net_device *ndev = platform_get_drvdata(pdev);\n\tstruct bcm6368_enetsw *priv = netdev_priv(ndev);\n\tunsigned int i;\n\n\tunregister_netdev(ndev);\n\n\tpm_runtime_put_sync(dev);\n\tfor (i = 0; priv->pm && i < priv->num_pms; i++) {\n\t\tdev_pm_domain_detach(priv->pm[i], true);\n\t\tdevice_link_del(priv->link_pm[i]);\n\t}\n\n\tfor (i = 0; i < priv->num_resets; i++)\n\t\treset_control_assert(priv->reset[i]);\n\n\tfor (i = 0; i < priv->num_clocks; i++)\n\t\tclk_disable_unprepare(priv->clock[i]);\n\n\tfree_netdev(ndev);\n\n\treturn 0;\n}\n\nstatic const struct of_device_id bcm6368_enetsw_of_match[] = {\n\t{ .compatible = \"brcm,bcm6318-enetsw\", },\n\t{ .compatible = \"brcm,bcm6328-enetsw\", },\n\t{ .compatible = \"brcm,bcm6362-enetsw\", },\n\t{ .compatible = \"brcm,bcm6368-enetsw\", },\n\t{ .compatible = \"brcm,bcm63268-enetsw\", },\n\t{ /* sentinel */ }\n};\nMODULE_DEVICE_TABLE(of, bcm6368_enetsw_of_match);\n\nstatic struct platform_driver bcm6368_enetsw_driver = {\n\t.driver = {\n\t\t.name = \"bcm6368-enetsw\",\n\t\t.of_match_table = of_match_ptr(bcm6368_enetsw_of_match),\n\t},\n\t.probe\t= bcm6368_enetsw_probe,\n\t.remove\t= bcm6368_enetsw_remove,\n};\nmodule_platform_driver(bcm6368_enetsw_driver);\n"
  },
  {
    "path": "target/linux/bmips/files/drivers/pci/controller/pci-bcm6348.c",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later\n/*\n * BCM6348 PCI Controller Driver\n *\n * Copyright (C) 2020 Álvaro Fernández Rojas <noltari@gmail.com>\n * Copyright (C) 2015 Jonas Gorski <jonas.gorski@gmail.com>\n * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>\n */\n\n#include <linux/clk.h>\n#include <linux/init.h>\n#include <linux/delay.h>\n#include <linux/kernel.h>\n#include <linux/memblock.h>\n#include <linux/mm.h>\n#include <linux/of_address.h>\n#include <linux/of_gpio.h>\n#include <linux/of_irq.h>\n#include <linux/of_pci.h>\n#include <linux/of_platform.h>\n#include <linux/pci.h>\n#include <linux/reset.h>\n#include <linux/types.h>\n#include <linux/vmalloc.h>\n\n#include \"../pci.h\"\n\n#define CARDBUS_DUMMY_ID\t\t0x6348\n#define CARDBUS_PCI_IDSEL\t\t0x8\n#define FAKE_CB_BRIDGE_SLOT\t\t0x1e\n\n#define BCMPCI_REG_TIMERS\t\t0x40\n#define REG_TIMER_TRDY_SHIFT\t\t0\n#define REG_TIMER_TRDY_MASK\t\t(0xff << REG_TIMER_TRDY_SHIFT)\n#define REG_TIMER_RETRY_SHIFT\t\t8\n#define REG_TIMER_RETRY_MASK\t\t(0xff << REG_TIMER_RETRY_SHIFT)\n\n#define MPI_SP0_RANGE_REG\t\t0x100\n#define MPI_SP0_REMAP_REG\t\t0x104\n#define MPI_SP0_REMAP_ENABLE_MASK\t(1 << 0)\n#define MPI_SP1_RANGE_REG\t\t0x10C\n#define MPI_SP1_REMAP_REG\t\t0x110\n#define MPI_SP1_REMAP_ENABLE_MASK\t(1 << 0)\n\n#define MPI_L2PCFG_REG\t\t\t0x11c\n#define MPI_L2PCFG_CFG_TYPE_SHIFT\t0\n#define MPI_L2PCFG_CFG_TYPE_MASK\t(0x3 << MPI_L2PCFG_CFG_TYPE_SHIFT)\n#define MPI_L2PCFG_REG_SHIFT\t\t2\n#define MPI_L2PCFG_REG_MASK\t\t(0x3f << MPI_L2PCFG_REG_SHIFT)\n#define MPI_L2PCFG_FUNC_SHIFT\t\t8\n#define MPI_L2PCFG_FUNC_MASK\t\t(0x7 << MPI_L2PCFG_FUNC_SHIFT)\n#define MPI_L2PCFG_DEVNUM_SHIFT\t\t11\n#define MPI_L2PCFG_DEVNUM_MASK\t\t(0x1f << MPI_L2PCFG_DEVNUM_SHIFT)\n#define MPI_L2PCFG_CFG_USEREG_MASK\t(1 << 30)\n#define MPI_L2PCFG_CFG_SEL_MASK\t\t(1 << 31)\n\n#define MPI_L2PMEMRANGE1_REG\t\t0x120\n#define MPI_L2PMEMBASE1_REG\t\t0x124\n#define MPI_L2PMEMREMAP1_REG\t\t0x128\n#define MPI_L2PMEMRANGE2_REG\t\t0x12C\n#define MPI_L2PMEMBASE2_REG\t\t0x130\n#define MPI_L2PMEMREMAP2_REG\t\t0x134\n#define MPI_L2PIORANGE_REG\t\t0x138\n#define MPI_L2PIOBASE_REG\t\t0x13C\n#define MPI_L2PIOREMAP_REG\t\t0x140\n#define MPI_L2P_BASE_MASK\t\t(0xffff8000)\n#define MPI_L2PREMAP_ENABLED_MASK\t(1 << 0)\n#define MPI_L2PREMAP_IS_CARDBUS_MASK\t(1 << 2)\n\n#define MPI_PCIMODESEL_REG\t\t0x144\n#define MPI_PCIMODESEL_BAR1_NOSWAP_MASK (1 << 0)\n#define MPI_PCIMODESEL_BAR2_NOSWAP_MASK (1 << 1)\n#define MPI_PCIMODESEL_EXT_ARB_MASK\t(1 << 2)\n#define MPI_PCIMODESEL_PREFETCH_SHIFT\t4\n#define MPI_PCIMODESEL_PREFETCH_MASK\t(0xf << MPI_PCIMODESEL_PREFETCH_SHIFT)\n\n#define MPI_LOCBUSCTL_REG\t\t0x14c\n#define MPI_LOCBUSCTL_EN_PCI_GPIO_MASK\t(1 << 0)\n#define MPI_LOCBUSCTL_U2P_NOSWAP_MASK\t(1 << 1)\n\n#define MPI_LOCINT_REG\t\t\t0x150\n#define MPI_LOCINT_MASK(x)\t\t(1 << (x + 16))\n#define MPI_LOCINT_STAT(x)\t\t(1 << (x))\n#define MPI_LOCINT_DIR_FAILED\t\t6\n#define MPI_LOCINT_EXT_PCI_INT\t\t7\n#define MPI_LOCINT_SERR\t\t\t8\n#define MPI_LOCINT_CSERR\t\t9\n\n#define MPI_PCICFGCTL_REG\t\t0x178\n#define MPI_PCICFGCTL_CFGADDR_SHIFT\t2\n#define MPI_PCICFGCTL_CFGADDR_MASK\t(0x1f << MPI_PCICFGCTL_CFGADDR_SHIFT)\n#define MPI_PCICFGCTL_WRITEEN_MASK\t(1 << 7)\n\n#define MPI_PCICFGDATA_REG\t\t0x17c\n\n#define PCMCIA_OFFSET\t\t\t0x54\n\n#define PCMCIA_C1_REG\t\t\t0x0\n#define PCMCIA_C1_CD1_MASK\t\t(1 << 0)\n#define PCMCIA_C1_CD2_MASK\t\t(1 << 1)\n#define PCMCIA_C1_VS1_MASK\t\t(1 << 2)\n#define PCMCIA_C1_VS2_MASK\t\t(1 << 3)\n#define PCMCIA_C1_VS1OE_MASK\t\t(1 << 6)\n#define PCMCIA_C1_VS2OE_MASK\t\t(1 << 7)\n#define PCMCIA_C1_CBIDSEL_SHIFT\t\t(8)\n#define PCMCIA_C1_CBIDSEL_MASK\t\t(0x1f << PCMCIA_C1_CBIDSEL_SHIFT)\n#define PCMCIA_C1_EN_PCMCIA_GPIO_MASK\t(1 << 13)\n#define PCMCIA_C1_EN_PCMCIA_MASK\t(1 << 14)\n#define PCMCIA_C1_EN_CARDBUS_MASK\t(1 << 15)\n#define PCMCIA_C1_RESET_MASK\t\t(1 << 18)\n\n#ifdef CONFIG_CARDBUS\nstruct bcm6348_cb {\n\tu16 pci_command;\n\tu8 cb_latency;\n\tu8 subordinate_busn;\n\tu8 cardbus_busn;\n\tu8 pci_busn;\n\tint bus_assigned;\n\tu16 bridge_control;\n\n\tu32 mem_base0;\n\tu32 mem_limit0;\n\tu32 mem_base1;\n\tu32 mem_limit1;\n\n\tu32 io_base0;\n\tu32 io_limit0;\n\tu32 io_base1;\n\tu32 io_limit1;\n};\n#endif /* CONFIG_CARDBUS */\n\nstruct bcm6348_pci {\n\tvoid __iomem *pci;\n\tvoid __iomem *pcmcia;\n\tvoid __iomem *io;\n\tint irq;\n\tstruct reset_control *reset;\n\tbool remap;\n#ifdef CONFIG_CARDBUS\n\tstruct bcm6348_cb cb;\n\tint cb_bus;\n#endif /* CONFIG_CARDBUS */\n};\n\nstatic struct bcm6348_pci bcm6348_pci;\n\nextern int bmips_pci_irq;\n\nstatic u32 bcm6348_int_cfg_readl(u32 reg)\n{\n\tstruct bcm6348_pci *priv = &bcm6348_pci;\n\tu32 tmp;\n\n\ttmp = reg & MPI_PCICFGCTL_CFGADDR_MASK;\n\ttmp |= MPI_PCICFGCTL_WRITEEN_MASK;\n\t__raw_writel(tmp, priv->pci + MPI_PCICFGCTL_REG);\n\tiob();\n\treturn __raw_readl(priv->pci + MPI_PCICFGDATA_REG);\n}\n\nstatic void bcm6348_int_cfg_writel(u32 val, u32 reg)\n{\n\tstruct bcm6348_pci *priv = &bcm6348_pci;\n\tu32 tmp;\n\n\ttmp = reg & MPI_PCICFGCTL_CFGADDR_MASK;\n\ttmp |= MPI_PCICFGCTL_WRITEEN_MASK;\n\t__raw_writel(tmp, priv->pci + MPI_PCICFGCTL_REG);\n\t__raw_writel(val, priv->pci + MPI_PCICFGDATA_REG);\n}\n\n/*\n * swizzle 32bits data to return only the needed part\n */\nstatic int postprocess_read(u32 data, int where, unsigned int size)\n{\n\tu32 ret = 0;\n\n\tswitch (size) {\n\tcase 1:\n\t\tret = (data >> ((where & 3) << 3)) & 0xff;\n\t\tbreak;\n\tcase 2:\n\t\tret = (data >> ((where & 3) << 3)) & 0xffff;\n\t\tbreak;\n\tcase 4:\n\t\tret = data;\n\t\tbreak;\n\t}\n\n\treturn ret;\n}\n\nstatic int preprocess_write(u32 orig_data, u32 val, int where,\n\t\t\t    unsigned int size)\n{\n\tu32 ret = 0;\n\n\tswitch (size) {\n\tcase 1:\n\t\tret = (orig_data & ~(0xff << ((where & 3) << 3))) |\n\t\t\t(val << ((where & 3) << 3));\n\t\tbreak;\n\tcase 2:\n\t\tret = (orig_data & ~(0xffff << ((where & 3) << 3))) |\n\t\t\t(val << ((where & 3) << 3));\n\t\tbreak;\n\tcase 4:\n\t\tret = val;\n\t\tbreak;\n\t}\n\n\treturn ret;\n}\n\nstatic int bcm6348_setup_cfg_access(int type, unsigned int busn,\n\t\t\t\t    unsigned int devfn, int where)\n{\n\tstruct bcm6348_pci *priv = &bcm6348_pci;\n\tunsigned int slot, func, reg;\n\tu32 val;\n\n\tslot = PCI_SLOT(devfn);\n\tfunc = PCI_FUNC(devfn);\n\treg = where >> 2;\n\n\t/* sanity check */\n\tif (slot > (MPI_L2PCFG_DEVNUM_MASK >> MPI_L2PCFG_DEVNUM_SHIFT))\n\t\treturn 1;\n\n\tif (func > (MPI_L2PCFG_FUNC_MASK >> MPI_L2PCFG_FUNC_SHIFT))\n\t\treturn 1;\n\n\tif (reg > (MPI_L2PCFG_REG_MASK >> MPI_L2PCFG_REG_SHIFT))\n\t\treturn 1;\n\n\t/* ok, setup config access */\n\tval = (reg << MPI_L2PCFG_REG_SHIFT);\n\tval |= (func << MPI_L2PCFG_FUNC_SHIFT);\n\tval |= (slot << MPI_L2PCFG_DEVNUM_SHIFT);\n\tval |= MPI_L2PCFG_CFG_USEREG_MASK;\n\tval |= MPI_L2PCFG_CFG_SEL_MASK;\n\t/* type 0 cycle for local bus, type 1 cycle for anything else */\n\tif (type != 0) {\n\t\t/* FIXME: how to specify bus ??? */\n\t\tval |= (1 << MPI_L2PCFG_CFG_TYPE_SHIFT);\n\t}\n\t__raw_writel(val, priv->pci + MPI_L2PCFG_REG);\n\n\treturn 0;\n}\n\n\nstatic int bcm6348_do_cfg_read(int type, unsigned int busn,\n\t\t\t       unsigned int devfn, int where, int size,\n\t\t\t       u32 *val)\n{\n\tstruct bcm6348_pci *priv = &bcm6348_pci;\n\tu32 data;\n\n\t/* two phase cycle, first we write address, then read data at\n\t * another location, caller already has a spinlock so no need\n\t * to add one here */\n\tif (bcm6348_setup_cfg_access(type, busn, devfn, where))\n\t\treturn PCIBIOS_DEVICE_NOT_FOUND;\n\tiob();\n\tdata = le32_to_cpu(__raw_readl(priv->io));\n\t/* restore IO space normal behaviour */\n\t__raw_writel(0, priv->pci + MPI_L2PCFG_REG);\n\n\t*val = postprocess_read(data, where, size);\n\n\treturn PCIBIOS_SUCCESSFUL;\n}\n\nstatic int bcm6348_do_cfg_write(int type, unsigned int busn,\n\t\t\t\tunsigned int devfn, int where, int size,\n\t\t\t\tu32 val)\n{\n\tstruct bcm6348_pci *priv = &bcm6348_pci;\n\tu32 data;\n\n\t/* two phase cycle, first we write address, then write data to\n\t * another location, caller already has a spinlock so no need\n\t * to add one here */\n\tif (bcm6348_setup_cfg_access(type, busn, devfn, where))\n\t\treturn PCIBIOS_DEVICE_NOT_FOUND;\n\tiob();\n\n\tdata = le32_to_cpu(__raw_readl(priv->io));\n\tdata = preprocess_write(data, val, where, size);\n\n\t__raw_writel(cpu_to_le32(data), priv->io);\n\twmb();\n\t/* no way to know the access is done, we have to wait */\n\tudelay(500);\n\t/* restore IO space normal behaviour */\n\t__raw_writel(0, priv->pci + MPI_L2PCFG_REG);\n\n\treturn PCIBIOS_SUCCESSFUL;\n}\n\nstatic int bcm6348_pci_read(struct pci_bus *bus, unsigned int devfn,\n\t\t\t     int where, int size, u32 *val)\n{\n\tint type;\n\n\ttype = bus->parent ? 1 : 0;\n\n\tif (type == 0 && PCI_SLOT(devfn) == CARDBUS_PCI_IDSEL)\n\t\treturn PCIBIOS_DEVICE_NOT_FOUND;\n\n\treturn bcm6348_do_cfg_read(type, bus->number, devfn,\n\t\t\t\t   where, size, val);\n}\n\nstatic int bcm6348_pci_write(struct pci_bus *bus, unsigned int devfn,\n\t\t\t      int where, int size, u32 val)\n{\n\tint type;\n\n\ttype = bus->parent ? 1 : 0;\n\n\tif (type == 0 && PCI_SLOT(devfn) == CARDBUS_PCI_IDSEL)\n\t\treturn PCIBIOS_DEVICE_NOT_FOUND;\n\n\treturn bcm6348_do_cfg_write(type, bus->number, devfn,\n\t\t\t\t    where, size, val);\n}\n\nstatic struct pci_ops bcm6348_pci_ops = {\n\t.read = bcm6348_pci_read,\n\t.write = bcm6348_pci_write,\n};\n\nstatic struct resource bcm6348_pci_io_resource = {\n\t.name = \"BCM6348 PCI IO space\",\n\t.flags = IORESOURCE_IO,\n};\nstatic struct resource bcm6348_pci_mem_resource;\nstatic struct resource bcm6348_pci_busn_resource;\n\nstatic struct pci_controller bcm6348_pci_controller = {\n\t.pci_ops = &bcm6348_pci_ops,\n\t.io_resource = &bcm6348_pci_io_resource,\n\t.mem_resource = &bcm6348_pci_mem_resource,\n\t.busn_resource = &bcm6348_pci_busn_resource,\n};\n\n#ifdef CONFIG_CARDBUS\nstatic int bcm6348_cb_bridge_read(int where, int size, u32 *val)\n{\n\tstruct bcm6348_cb *cb = &bcm6348_pci.cb;\n\tunsigned int reg;\n\tu32 data;\n\n\tdata = 0;\n\treg = where >> 2;\n\tswitch (reg) {\n\tcase (PCI_VENDOR_ID >> 2):\n\tcase (PCI_CB_SUBSYSTEM_VENDOR_ID >> 2):\n\t\t/* create dummy vendor/device id from our cpu id */\n\t\tdata = (CARDBUS_DUMMY_ID << 16) | PCI_VENDOR_ID_BROADCOM;\n\t\tbreak;\n\n\tcase (PCI_COMMAND >> 2):\n\t\tdata = (PCI_STATUS_DEVSEL_SLOW << 16);\n\t\tdata |= cb->pci_command;\n\t\tbreak;\n\n\tcase (PCI_CLASS_REVISION >> 2):\n\t\tdata = (PCI_CLASS_BRIDGE_CARDBUS << 16);\n\t\tbreak;\n\n\tcase (PCI_CACHE_LINE_SIZE >> 2):\n\t\tdata = (PCI_HEADER_TYPE_CARDBUS << 16);\n\t\tbreak;\n\n\tcase (PCI_INTERRUPT_LINE >> 2):\n\t\t/* bridge control */\n\t\tdata = (cb->bridge_control << 16);\n\t\t/* pin:intA line:0xff */\n\t\tdata |= (0x1 << 8) | 0xff;\n\t\tbreak;\n\n\tcase (PCI_CB_PRIMARY_BUS >> 2):\n\t\tdata = (cb->cb_latency << 24);\n\t\tdata |= (cb->subordinate_busn << 16);\n\t\tdata |= (cb->cardbus_busn << 8);\n\t\tdata |= cb->pci_busn;\n\t\tbreak;\n\n\tcase (PCI_CB_MEMORY_BASE_0 >> 2):\n\t\tdata = cb->mem_base0;\n\t\tbreak;\n\n\tcase (PCI_CB_MEMORY_LIMIT_0 >> 2):\n\t\tdata = cb->mem_limit0;\n\t\tbreak;\n\n\tcase (PCI_CB_MEMORY_BASE_1 >> 2):\n\t\tdata = cb->mem_base1;\n\t\tbreak;\n\n\tcase (PCI_CB_MEMORY_LIMIT_1 >> 2):\n\t\tdata = cb->mem_limit1;\n\t\tbreak;\n\n\tcase (PCI_CB_IO_BASE_0 >> 2):\n\t\t/* | 1 for 32bits io support */\n\t\tdata = cb->io_base0 | 0x1;\n\t\tbreak;\n\n\tcase (PCI_CB_IO_LIMIT_0 >> 2):\n\t\tdata = cb->io_limit0;\n\t\tbreak;\n\n\tcase (PCI_CB_IO_BASE_1 >> 2):\n\t\t/* | 1 for 32bits io support */\n\t\tdata = cb->io_base1 | 0x1;\n\t\tbreak;\n\n\tcase (PCI_CB_IO_LIMIT_1 >> 2):\n\t\tdata = cb->io_limit1;\n\t\tbreak;\n\t}\n\n\t*val = postprocess_read(data, where, size);\n\treturn PCIBIOS_SUCCESSFUL;\n}\n\n/*\n * emulate configuration write access on a cardbus bridge\n */\nstatic int bcm6348_cb_bridge_write(int where, int size, u32 val)\n{\n\tstruct bcm6348_cb *cb = &bcm6348_pci.cb;\n\tunsigned int reg;\n\tu32 data, tmp;\n\tint ret;\n\n\tret = bcm6348_cb_bridge_read((where & ~0x3), 4, &data);\n\tif (ret != PCIBIOS_SUCCESSFUL)\n\t\treturn ret;\n\n\tdata = preprocess_write(data, val, where, size);\n\n\treg = where >> 2;\n\tswitch (reg) {\n\tcase (PCI_COMMAND >> 2):\n\t\tcb->pci_command = (data & 0xffff);\n\t\tbreak;\n\n\tcase (PCI_CB_PRIMARY_BUS >> 2):\n\t\tcb->cb_latency = (data >> 24) & 0xff;\n\t\tcb->subordinate_busn = (data >> 16) & 0xff;\n\t\tcb->cardbus_busn = (data >> 8) & 0xff;\n\t\tcb->pci_busn = data & 0xff;\n\t\tif (cb->cardbus_busn)\n\t\t\tcb->bus_assigned = 1;\n\t\tbreak;\n\n\tcase (PCI_INTERRUPT_LINE >> 2):\n\t\ttmp = (data >> 16) & 0xffff;\n\t\t/* Disable memory prefetch support */\n\t\ttmp &= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM0;\n\t\ttmp &= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM1;\n\t\tcb->bridge_control = tmp;\n\t\tbreak;\n\n\tcase (PCI_CB_MEMORY_BASE_0 >> 2):\n\t\tcb->mem_base0 = data;\n\t\tbreak;\n\n\tcase (PCI_CB_MEMORY_LIMIT_0 >> 2):\n\t\tcb->mem_limit0 = data;\n\t\tbreak;\n\n\tcase (PCI_CB_MEMORY_BASE_1 >> 2):\n\t\tcb->mem_base1 = data;\n\t\tbreak;\n\n\tcase (PCI_CB_MEMORY_LIMIT_1 >> 2):\n\t\tcb->mem_limit1 = data;\n\t\tbreak;\n\n\tcase (PCI_CB_IO_BASE_0 >> 2):\n\t\tcb->io_base0 = data;\n\t\tbreak;\n\n\tcase (PCI_CB_IO_LIMIT_0 >> 2):\n\t\tcb->io_limit0 = data;\n\t\tbreak;\n\n\tcase (PCI_CB_IO_BASE_1 >> 2):\n\t\tcb->io_base1 = data;\n\t\tbreak;\n\n\tcase (PCI_CB_IO_LIMIT_1 >> 2):\n\t\tcb->io_limit1 = data;\n\t\tbreak;\n\t}\n\n\treturn PCIBIOS_SUCCESSFUL;\n}\n\nstatic int bcm6348_cb_read(struct pci_bus *bus, unsigned int devfn,\n\t\t\t   int where, int size, u32 *val)\n{\n\tstruct bcm6348_pci *priv = &bcm6348_pci;\n\tstruct bcm6348_cb *cb = &priv->cb;\n\n\t/* Snoop access to slot 0x1e on root bus, we fake a cardbus\n\t * bridge at this location */\n\tif (!bus->parent && PCI_SLOT(devfn) == FAKE_CB_BRIDGE_SLOT) {\n\t\tpriv->cb_bus = bus->number;\n\t\treturn bcm6348_cb_bridge_read(where, size, val);\n\t}\n\n\t/* A configuration cycle for the device behind the cardbus\n\t * bridge is actually done as a type 0 cycle on the primary\n\t * bus. This means that only one device can be on the cardbus\n\t * bus */\n\tif (cb->bus_assigned &&\n\t    bus->number == cb->cardbus_busn &&\n\t    PCI_SLOT(devfn) == 0)\n\t\treturn bcm6348_do_cfg_read(0, 0,\n\t\t\t\t\t   PCI_DEVFN(CARDBUS_PCI_IDSEL, 0),\n\t\t\t\t\t   where, size, val);\n\n\treturn PCIBIOS_DEVICE_NOT_FOUND;\n}\n\nstatic int bcm6348_cb_write(struct pci_bus *bus, unsigned int devfn,\n\t\t\t    int where, int size, u32 val)\n{\n\tstruct bcm6348_pci *priv = &bcm6348_pci;\n\tstruct bcm6348_cb *cb = &priv->cb;\n\n\tif (!bus->parent && PCI_SLOT(devfn) == FAKE_CB_BRIDGE_SLOT) {\n\t\tpriv->cb_bus = bus->number;\n\t\treturn bcm6348_cb_bridge_write(where, size, val);\n\t}\n\n\tif (cb->bus_assigned &&\n\t    bus->number == cb->cardbus_busn &&\n\t    PCI_SLOT(devfn) == 0)\n\t\treturn bcm6348_do_cfg_write(0, 0,\n\t\t\t\t\t    PCI_DEVFN(CARDBUS_PCI_IDSEL, 0),\n\t\t\t\t\t    where, size, val);\n\n\treturn PCIBIOS_DEVICE_NOT_FOUND;\n}\n\nstatic struct pci_ops bcm6348_cb_ops = {\n\t.read = bcm6348_cb_read,\n\t.write = bcm6348_cb_write,\n};\n\n/*\n * only one IO window, so it  cannot be shared by PCI and cardbus, use\n * fixup to choose and detect unhandled configuration\n */\nstatic void bcm6348_pci_fixup(struct pci_dev *dev)\n{\n\tstruct bcm6348_pci *priv = &bcm6348_pci;\n\tstruct bcm6348_cb *cb = &priv->cb;\n\tstatic int io_window = -1;\n\tint i, found, new_io_window;\n\tu32 val;\n\n\t/* look for any io resource */\n\tfound = 0;\n\tfor (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {\n\t\tif (pci_resource_flags(dev, i) & IORESOURCE_IO) {\n\t\t\tfound = 1;\n\t\t\tbreak;\n\t\t}\n\t}\n\n\tif (!found)\n\t\treturn;\n\n\t/* skip our fake bus with only cardbus bridge on it */\n\tif (dev->bus->number == priv->cb_bus)\n\t\treturn;\n\n\t/* find on which bus the device is */\n\tif (cb->bus_assigned &&\n\t    dev->bus->number == cb->cardbus_busn &&\n\t    PCI_SLOT(dev->devfn) == 0)\n\t\tnew_io_window = 1;\n\telse\n\t\tnew_io_window = 0;\n\n\tif (new_io_window == io_window)\n\t\treturn;\n\n\tif (io_window != -1) {\n\t\tpr_err(\"bcm63xx: both PCI and cardbus devices \"\n\t\t       \"need IO, which hardware cannot do\\n\");\n\t\treturn;\n\t}\n\n\tpr_info(\"bcm63xx: PCI IO window assigned to %s\\n\",\n\t       (new_io_window == 0) ? \"PCI\" : \"cardbus\");\n\n\tval = __raw_readl(priv->pci + MPI_L2PIOREMAP_REG);\n\tif (io_window)\n\t\tval |= MPI_L2PREMAP_IS_CARDBUS_MASK;\n\telse\n\t\tval &= ~MPI_L2PREMAP_IS_CARDBUS_MASK;\n\t__raw_writel(val, priv->pci + MPI_L2PIOREMAP_REG);\n\n\tio_window = new_io_window;\n}\nDECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, bcm6348_pci_fixup);\n\nstatic struct resource bcm6348_cb_io_resource = {\n\t.name = \"bcm6348 CB IO space\",\n\t.flags = IORESOURCE_IO,\n};\nstatic struct resource bcm6348_cb_mem_resource;\n\nstatic struct pci_controller bcm6348_cb_controller = {\n\t.pci_ops = &bcm6348_cb_ops,\n\t.io_resource = &bcm6348_cb_io_resource,\n\t.mem_resource = &bcm6348_cb_mem_resource,\n};\n#endif /* CONFIG_CARDBUS */\n\nstatic void bcm6348_pci_setup(struct bcm6348_pci *priv)\n{\n\tu32 val;\n\n\t/* Setup local bus to PCI access (PCI memory) */\n\tval = bcm6348_pci_mem_resource.start & MPI_L2P_BASE_MASK;\n\t__raw_writel(val, priv->pci + MPI_L2PMEMBASE1_REG);\n\t__raw_writel(~(resource_size(&bcm6348_pci_mem_resource) - 1),\n\t\t     priv->pci + MPI_L2PMEMRANGE1_REG);\n\t__raw_writel(val | MPI_L2PREMAP_ENABLED_MASK,\n\t\t     priv->pci + MPI_L2PMEMREMAP1_REG);\n\n\t/* Set Cardbus IDSEL (type 0 cfg access on primary bus for\n\t * this IDSEL will be done on Cardbus instead) */\n\tval = __raw_readl(priv->pcmcia + PCMCIA_C1_REG);\n\tval &= ~PCMCIA_C1_CBIDSEL_MASK;\n\tval |= (CARDBUS_PCI_IDSEL << PCMCIA_C1_CBIDSEL_SHIFT);\n\t__raw_writel(val, priv->pcmcia + PCMCIA_C1_REG);\n\n#ifdef CONFIG_CARDBUS\n\t/* setup local bus to PCI access (Cardbus memory) */\n\tval = bcm6348_cb_mem_resource.start & MPI_L2P_BASE_MASK;\n\t__raw_writel(val, priv->pci + MPI_L2PMEMBASE2_REG);\n\t__raw_writel(~(resource_size(&bcm6348_cb_mem_resource) - 1),\n\t\t     priv->pci + MPI_L2PMEMRANGE2_REG);\n\tval |= MPI_L2PREMAP_ENABLED_MASK | MPI_L2PREMAP_IS_CARDBUS_MASK;\n\t__raw_writel(val, priv->pci + MPI_L2PMEMREMAP2_REG);\n#else\n\t/* disable second access windows */\n\t__raw_writel(0, priv->pci + MPI_L2PMEMREMAP2_REG);\n#endif\n\n\t/* setup local bus to PCI access (IO memory), we have only 1\n\t * IO window for both PCI and cardbus, but it cannot handle\n\t * both at the same time, assume standard PCI for now, if\n\t * cardbus card has IO zone, PCI fixup will change window to\n\t * cardbus */\n\tval = bcm6348_pci_io_resource.start & MPI_L2P_BASE_MASK;\n\t__raw_writel(val, priv->pci + MPI_L2PIOBASE_REG);\n\t__raw_writel(~(resource_size(&bcm6348_pci_io_resource) - 1),\n\t\t     priv->pci + MPI_L2PIORANGE_REG);\n\t__raw_writel(val | MPI_L2PREMAP_ENABLED_MASK,\n\t\t     priv->pci + MPI_L2PIOREMAP_REG);\n\n\t/* Enable PCI related GPIO pins */\n\t__raw_writel(MPI_LOCBUSCTL_EN_PCI_GPIO_MASK,\n\t\t     priv->pci + MPI_LOCBUSCTL_REG);\n\n\t/* Setup PCI to local bus access, used by PCI device to target\n\t * local RAM while bus mastering */\n\tbcm6348_int_cfg_writel(0, PCI_BASE_ADDRESS_3);\n\tif (priv->remap)\n\t\tval = MPI_SP0_REMAP_ENABLE_MASK;\n\telse\n\t\tval = 0;\n\t__raw_writel(val, priv->pci + MPI_SP0_REMAP_REG);\n\n\tbcm6348_int_cfg_writel(0, PCI_BASE_ADDRESS_4);\n\t__raw_writel(0, priv->pci + MPI_SP1_REMAP_REG);\n\n\t/* Setup sp0 range to local RAM size */\n\t__raw_writel(~(memblock_phys_mem_size() - 1),\n\t\t     priv->pci + MPI_SP0_RANGE_REG);\n\t__raw_writel(0, priv->pci + MPI_SP1_RANGE_REG);\n\n\t/* Change host bridge retry counter to infinite number of\n\t * retries, needed for some broadcom wifi cards with Silicon\n\t * Backplane bus where access to srom seems very slow */\n\tval = bcm6348_int_cfg_readl(BCMPCI_REG_TIMERS);\n\tval &= ~REG_TIMER_RETRY_MASK;\n\tbcm6348_int_cfg_writel(val, BCMPCI_REG_TIMERS);\n\n\t/* EEnable memory decoder and bus mastering */\n\tval = bcm6348_int_cfg_readl(PCI_COMMAND);\n\tval |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);\n\tbcm6348_int_cfg_writel(val, PCI_COMMAND);\n\n\t/* Enable read prefetching & disable byte swapping for bus\n\t * mastering transfers */\n\tval = __raw_readl(priv->pci + MPI_PCIMODESEL_REG);\n\tval &= ~MPI_PCIMODESEL_BAR1_NOSWAP_MASK;\n\tval &= ~MPI_PCIMODESEL_BAR2_NOSWAP_MASK;\n\tval &= ~MPI_PCIMODESEL_PREFETCH_MASK;\n\tval |= (8 << MPI_PCIMODESEL_PREFETCH_SHIFT);\n\t__raw_writel(val, priv->pci + MPI_PCIMODESEL_REG);\n\n\t/* Enable pci interrupt */\n\tval = __raw_readl(priv->pci + MPI_LOCINT_REG);\n\tval |= MPI_LOCINT_MASK(MPI_LOCINT_EXT_PCI_INT);\n\t__raw_writel(val, priv->pci + MPI_LOCINT_REG);\n}\n\nstatic int bcm6348_pci_probe(struct platform_device *pdev)\n{\n\tstruct device *dev = &pdev->dev;\n\tstruct device_node *np = dev->of_node;\n\tstruct bcm6348_pci *priv = &bcm6348_pci;\n\tstruct resource *res;\n\n\tof_pci_check_probe_only();\n\n\tres = platform_get_resource_byname(pdev, IORESOURCE_MEM, \"pci\");\n\tpriv->pci = devm_ioremap_resource(dev, res);\n\tif (IS_ERR(priv->pci))\n\t\treturn PTR_ERR(priv->pci);\n\n\tpriv->pcmcia = priv->pci + PCMCIA_OFFSET;\n\n\tres = platform_get_resource_byname(pdev, IORESOURCE_MEM, \"pci-io\");\n\tif (!res)\n\t\treturn -EINVAL;\n#ifdef CONFIG_CARDBUS\n\tbcm6348_pci_io_resource.start = res->start;\n\tbcm6348_pci_io_resource.end = res->end - (resource_size(res) >> 1);\n\tbcm6348_cb_io_resource.start = res->start + (resource_size(res) >> 1);\n\tbcm6348_cb_io_resource.end = res->end;\n#else\n\tbcm6348_pci_io_resource.start = res->start;\n\tbcm6348_pci_io_resource.end = res->end;\n#endif\n\n\tpriv->irq = platform_get_irq(pdev, 0);\n\tif (!priv->irq)\n\t\treturn -ENODEV;\n\n\tbmips_pci_irq = priv->irq;\n\n\tpriv->reset = devm_reset_control_get(dev, \"pci\");\n\tif (IS_ERR(priv->reset))\n\t\treturn PTR_ERR(priv->reset);\n\n\tpriv->remap = of_property_read_bool(np, \"brcm,remap\");\n\n\treset_control_reset(priv->reset);\n\n\tpci_load_of_ranges(&bcm6348_pci_controller, np);\n\tif (!bcm6348_pci_mem_resource.start)\n\t\treturn -EINVAL;\n\n\tof_pci_parse_bus_range(np, &bcm6348_pci_busn_resource);\n\n\t/*\n\t * Configuration accesses are done through IO space, remap 4\n\t * first bytes to access it from CPU.\n\t *\n\t * This means that no IO access from CPU should happen while\n\t * we do a configuration cycle, but there's no way we can add\n\t * a spinlock for each io access, so this is currently kind of\n\t * broken on SMP.\n\t */\n\tpriv->io = ioremap(bcm6348_pci_io_resource.start, sizeof(u32));\n\tif (!priv->io)\n\t\treturn -ENOMEM;\n\n\tbcm6348_pci_setup(priv);\n\n\tregister_pci_controller(&bcm6348_pci_controller);\n\n#ifdef CONFIG_CARDBUS\n\tpriv->cb_bus = -1;\n\tregister_pci_controller(&bcm6348_cb_controller);\n#endif /* CONFIG_CARDBUS */\n\n\t/* Mark memory space used for IO mapping as reserved */\n\trequest_mem_region(bcm6348_pci_io_resource.start,\n\t\t\t   resource_size(&bcm6348_pci_io_resource),\n\t\t\t   \"BCM6348 PCI IO space\");\n\n\treturn 0;\n}\n\nstatic const struct of_device_id bcm6348_pci_of_match[] = {\n\t{ .compatible = \"brcm,bcm6348-pci\", },\n\t{ /* sentinel */ }\n};\n\nstatic struct platform_driver bcm6348_pci_driver = {\n\t.probe = bcm6348_pci_probe,\n\t.driver\t= {\n\t\t.name = \"bcm6348-pci\",\n\t\t.of_match_table = bcm6348_pci_of_match,\n\t},\n};\n\nint __init bcm6348_pci_init(void)\n{\n\tint ret = platform_driver_register(&bcm6348_pci_driver);\n\tif (ret)\n\t\tpr_err(\"pci-bcm6348: Error registering platform driver!\\n\");\n\treturn ret;\n}\nlate_initcall_sync(bcm6348_pci_init);\n"
  },
  {
    "path": "target/linux/bmips/files/drivers/pci/controller/pcie-bcm6318.c",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later\n/*\n * BCM6318 PCIe Controller Driver\n *\n * Copyright (C) 2020 Álvaro Fernández Rojas <noltari@gmail.com>\n * Copyright (C) 2015 Jonas Gorski <jonas.gorski@gmail.com>\n * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>\n */\n\n#include <linux/clk.h>\n#include <linux/init.h>\n#include <linux/delay.h>\n#include <linux/kernel.h>\n#include <linux/mm.h>\n#include <linux/of_gpio.h>\n#include <linux/of_irq.h>\n#include <linux/of_pci.h>\n#include <linux/of_platform.h>\n#include <linux/pci.h>\n#include <linux/reset.h>\n#include <linux/types.h>\n#include <linux/vmalloc.h>\n\n#include \"../pci.h\"\n\n#define PCIE_BUS_BRIDGE\t\t\t0\n#define PCIE_BUS_DEVICE\t\t\t1\n\n#define PCIE_SPECIFIC_REG\t\t0x188\n#define SPECIFIC_ENDIAN_MODE_BAR1_SHIFT\t0\n#define SPECIFIC_ENDIAN_MODE_BAR1_MASK\t(0x3 << SPECIFIC_ENDIAN_MODE_BAR1_SHIFT)\n#define SPECIFIC_ENDIAN_MODE_BAR2_SHIFT\t2\n#define SPECIFIC_ENDIAN_MODE_BAR2_MASK\t(0x3 << SPECIFIC_ENDIAN_MODE_BAR1_SHIFT)\n#define SPECIFIC_ENDIAN_MODE_BAR3_SHIFT\t4\n#define SPECIFIC_ENDIAN_MODE_BAR3_MASK\t(0x3 << SPECIFIC_ENDIAN_MODE_BAR1_SHIFT)\n#define SPECIFIC_ENDIAN_MODE_WORD_ALIGN\t0\n#define SPECIFIC_ENDIAN_MODE_HALFWORD_ALIGN 1\n#define SPECIFIC_ENDIAN_MODE_BYTE_ALIGN\t2\n\n#define PCIE_CONFIG2_REG\t\t0x408\n#define CONFIG2_BAR1_SIZE_EN\t\t1\n#define CONFIG2_BAR1_SIZE_MASK\t\t0xf\n\n#define PCIE_IDVAL3_REG\t\t\t0x43c\n#define IDVAL3_CLASS_CODE_MASK\t\t0xffffff\n#define IDVAL3_SUBCLASS_SHIFT\t\t8\n#define IDVAL3_CLASS_SHIFT\t\t16\n\n#define PCIE_DLSTATUS_REG\t\t0x1048\n#define DLSTATUS_PHYLINKUP\t\t(1 << 13)\n\n#define PCIE_CPU_2_PCIE_MEM_WIN0_LO_REG\t0x400c\n#define C2P_MEM_WIN_ENDIAN_MODE_MASK\t0x3\n#define C2P_MEM_WIN_ENDIAN_NO_SWAP\t0\n#define C2P_MEM_WIN_ENDIAN_HALF_WORD_SWAP 1\n#define C2P_MEM_WIN_ENDIAN_HALF_BYTE_SWAP 2\n#define C2P_MEM_WIN_BASE_ADDR_SHIFT\t20\n#define C2P_MEM_WIN_BASE_ADDR_MASK\t(0xfff << C2P_MEM_WIN_BASE_ADDR_SHIFT)\n\n#define PCIE_RC_BAR1_CONFIG_LO_REG\t0x402c\n#define RC_BAR_CFG_LO_SIZE_256MB\t0xd\n#define RC_BAR_CFG_LO_MATCH_ADDR_SHIFT\t20\n#define RC_BAR_CFG_LO_MATCH_ADDR_MASK\t(0xfff << RC_BAR_CFG_LO_MATCH_ADDR_SHIFT)\n\n#define PCIE_CPU_2_PCIE_MEM_WIN0_BASELIMIT_REG 0x4070\n#define C2P_BASELIMIT_LIMIT_SHIFT\t20\n#define C2P_BASELIMIT_LIMIT_MASK\t(0xfff << C2P_BASELIMIT_LIMIT_SHIFT)\n#define C2P_BASELIMIT_BASE_SHIFT\t4\n#define C2P_BASELIMIT_BASE_MASK\t\t(0xfff << C2P_BASELIMIT_BASE_SHIFT)\n\n#define PCIE_UBUS_BAR1_CFG_REMAP_REG\t0x4088\n#define BAR1_CFG_REMAP_OFFSET_SHIFT\t20\n#define BAR1_CFG_REMAP_OFFSET_MASK\t(0xfff << BAR1_CFG_REMAP_OFFSET_SHIFT)\n#define BAR1_CFG_REMAP_ACCESS_EN\t1\n\n#define PCIE_HARD_DEBUG_REG\t\t0x4204\n#define HARD_DEBUG_SERDES_IDDQ\t\t(1 << 23)\n\n#define PCIE_CPU_INT1_MASK_CLEAR_REG\t0x830c\n#define CPU_INT_PCIE_ERR_ATTN_CPU\t(1 << 0)\n#define CPU_INT_PCIE_INTA\t\t(1 << 1)\n#define CPU_INT_PCIE_INTB\t\t(1 << 2)\n#define CPU_INT_PCIE_INTC\t\t(1 << 3)\n#define CPU_INT_PCIE_INTD\t\t(1 << 4)\n#define CPU_INT_PCIE_INTR\t\t(1 << 5)\n#define CPU_INT_PCIE_NMI\t\t(1 << 6)\n#define CPU_INT_PCIE_UBUS\t\t(1 << 7)\n#define CPU_INT_IPI\t\t\t(1 << 8)\n\n#define PCIE_EXT_CFG_INDEX_REG\t\t0x8400\n#define EXT_CFG_FUNC_NUM_SHIFT\t\t12\n#define EXT_CFG_FUNC_NUM_MASK\t\t(0x7 << EXT_CFG_FUNC_NUM_SHIFT)\n#define EXT_CFG_DEV_NUM_SHIFT\t\t15\n#define EXT_CFG_DEV_NUM_MASK\t\t(0xf << EXT_CFG_DEV_NUM_SHIFT)\n#define EXT_CFG_BUS_NUM_SHIFT\t\t20\n#define EXT_CFG_BUS_NUM_MASK\t\t(0xff << EXT_CFG_BUS_NUM_SHIFT)\n\n#define PCIE_DEVICE_OFFSET\t\t0x9000\n\nstruct bcm6318_pcie {\n\tvoid __iomem *base;\n\tint irq;\n\tstruct clk *clk;\n\tstruct clk *clk25;\n\tstruct clk *clk_ubus;\n\tstruct reset_control *reset;\n\tstruct reset_control *reset_ext;\n\tstruct reset_control *reset_core;\n\tstruct reset_control *reset_hard;\n};\n\nstatic struct bcm6318_pcie bcm6318_pcie;\n\nextern int bmips_pci_irq;\n\n/*\n * swizzle 32bits data to return only the needed part\n */\nstatic int postprocess_read(u32 data, int where, unsigned int size)\n{\n\tu32 ret = 0;\n\n\tswitch (size) {\n\tcase 1:\n\t\tret = (data >> ((where & 3) << 3)) & 0xff;\n\t\tbreak;\n\tcase 2:\n\t\tret = (data >> ((where & 3) << 3)) & 0xffff;\n\t\tbreak;\n\tcase 4:\n\t\tret = data;\n\t\tbreak;\n\t}\n\n\treturn ret;\n}\n\nstatic int preprocess_write(u32 orig_data, u32 val, int where,\n\t\t\t    unsigned int size)\n{\n\tu32 ret = 0;\n\n\tswitch (size) {\n\tcase 1:\n\t\tret = (orig_data & ~(0xff << ((where & 3) << 3))) |\n\t\t\t(val << ((where & 3) << 3));\n\t\tbreak;\n\tcase 2:\n\t\tret = (orig_data & ~(0xffff << ((where & 3) << 3))) |\n\t\t\t(val << ((where & 3) << 3));\n\t\tbreak;\n\tcase 4:\n\t\tret = val;\n\t\tbreak;\n\t}\n\n\treturn ret;\n}\n\nstatic int bcm6318_pcie_can_access(struct pci_bus *bus, int devfn)\n{\n\tstruct bcm6318_pcie *priv = &bcm6318_pcie;\n\n\tswitch (bus->number) {\n\tcase PCIE_BUS_BRIDGE:\n\t\treturn PCI_SLOT(devfn) == 0;\n\tcase PCIE_BUS_DEVICE:\n\t\tif (PCI_SLOT(devfn) == 0)\n\t\t\treturn __raw_readl(priv->base + PCIE_DLSTATUS_REG)\n\t\t\t\t\t& DLSTATUS_PHYLINKUP;\n\t\t/* else, fall through */\n\tdefault:\n\t\treturn false;\n\t}\n}\n\nstatic int bcm6318_pcie_read(struct pci_bus *bus, unsigned int devfn,\n\t\t\t     int where, int size, u32 *val)\n{\n\tstruct bcm6318_pcie *priv = &bcm6318_pcie;\n\tu32 data;\n\tu32 reg = where & ~3;\n\n\tif (!bcm6318_pcie_can_access(bus, devfn))\n\t\treturn PCIBIOS_DEVICE_NOT_FOUND;\n\n\tif (bus->number == PCIE_BUS_DEVICE)\n\t\treg += PCIE_DEVICE_OFFSET;\n\n\tdata = __raw_readl(priv->base + reg);\n\t*val = postprocess_read(data, where, size);\n\n\treturn PCIBIOS_SUCCESSFUL;\n}\n\nstatic int bcm6318_pcie_write(struct pci_bus *bus, unsigned int devfn,\n\t\t\t      int where, int size, u32 val)\n{\n\tstruct bcm6318_pcie *priv = &bcm6318_pcie;\n\tu32 data;\n\tu32 reg = where & ~3;\n\n\tif (!bcm6318_pcie_can_access(bus, devfn))\n\t\treturn PCIBIOS_DEVICE_NOT_FOUND;\n\n\tif (bus->number == PCIE_BUS_DEVICE)\n\t\treg += PCIE_DEVICE_OFFSET;\n\n\tdata = __raw_readl(priv->base + reg);\n\tdata = preprocess_write(data, val, where, size);\n\t__raw_writel(data, priv->base + reg);\n\n\treturn PCIBIOS_SUCCESSFUL;\n}\n\nstatic struct pci_ops bcm6318_pcie_ops = {\n\t.read = bcm6318_pcie_read,\n\t.write = bcm6318_pcie_write,\n};\n\nstatic struct resource bcm6318_pcie_io_resource;\nstatic struct resource bcm6318_pcie_mem_resource;\nstatic struct resource bcm6318_pcie_busn_resource;\n\nstatic struct pci_controller bcm6318_pcie_controller = {\n\t.pci_ops = &bcm6318_pcie_ops,\n\t.io_resource = &bcm6318_pcie_io_resource,\n\t.mem_resource = &bcm6318_pcie_mem_resource,\n\t.busn_resource = &bcm6318_pcie_busn_resource,\n};\n\nstatic void bcm6318_pcie_reset(struct bcm6318_pcie *priv)\n{\n\tu32 val;\n\n\treset_control_deassert(priv->reset_hard);\n\n\treset_control_assert(priv->reset);\n\treset_control_assert(priv->reset_core);\n\treset_control_assert(priv->reset_ext);\n\tmdelay(10);\n\n\treset_control_deassert(priv->reset_ext);\n\tmdelay(10);\n\n\treset_control_deassert(priv->reset);\n\tmdelay(10);\n\n\tval = __raw_readl(priv->base + PCIE_HARD_DEBUG_REG);\n\tval &= ~HARD_DEBUG_SERDES_IDDQ;\n\t__raw_writel(val, priv->base + PCIE_HARD_DEBUG_REG);\n\tmdelay(10);\n\n\treset_control_deassert(priv->reset_core);\n\tmdelay(200);\n}\n\nstatic void bcm6318_pcie_setup(struct bcm6318_pcie *priv)\n{\n\tu32 val;\n\n\t__raw_writel(CPU_INT_PCIE_INTA | CPU_INT_PCIE_INTB |\n\t\t     CPU_INT_PCIE_INTC | CPU_INT_PCIE_INTD,\n\t\t     priv->base + PCIE_CPU_INT1_MASK_CLEAR_REG);\n\n\tval = bcm6318_pcie_mem_resource.end & C2P_BASELIMIT_LIMIT_MASK;\n\tval |= (bcm6318_pcie_mem_resource.start >> C2P_BASELIMIT_LIMIT_SHIFT)\n\t       << C2P_BASELIMIT_BASE_SHIFT;\n\t__raw_writel(val, priv->base + PCIE_CPU_2_PCIE_MEM_WIN0_BASELIMIT_REG);\n\n\t/* setup class code as bridge */\n\tval = __raw_readl(priv->base + PCIE_IDVAL3_REG);\n\tval &= ~IDVAL3_CLASS_CODE_MASK;\n\tval |= (PCI_CLASS_BRIDGE_PCI << IDVAL3_SUBCLASS_SHIFT);\n\t__raw_writel(val, priv->base + PCIE_IDVAL3_REG);\n\n\t/* disable bar1 size */\n\tval = __raw_readl(priv->base + PCIE_CONFIG2_REG);\n\tval &= ~CONFIG2_BAR1_SIZE_MASK;\n\t__raw_writel(val, priv->base + PCIE_CONFIG2_REG);\n\n\t/* set bar0 to little endian */\n\tval = __raw_readl(priv->base + PCIE_CPU_2_PCIE_MEM_WIN0_LO_REG);\n\tval |= bcm6318_pcie_mem_resource.start & C2P_MEM_WIN_BASE_ADDR_MASK;\n\tval |= C2P_MEM_WIN_ENDIAN_HALF_BYTE_SWAP;\n\t__raw_writel(val, priv->base + PCIE_CPU_2_PCIE_MEM_WIN0_LO_REG);\n\n\t__raw_writel(SPECIFIC_ENDIAN_MODE_BYTE_ALIGN,\n\t\t     priv->base + PCIE_SPECIFIC_REG);\n\n\t__raw_writel(RC_BAR_CFG_LO_SIZE_256MB,\n\t\t     priv->base + PCIE_RC_BAR1_CONFIG_LO_REG);\n\n\t__raw_writel(BAR1_CFG_REMAP_ACCESS_EN,\n\t\t     priv->base + PCIE_UBUS_BAR1_CFG_REMAP_REG);\n\n\t__raw_writel(PCIE_BUS_DEVICE << EXT_CFG_BUS_NUM_SHIFT,\n\t\t     priv->base + PCIE_EXT_CFG_INDEX_REG);\n}\n\nstatic int bcm6318_pcie_probe(struct platform_device *pdev)\n{\n\tstruct device *dev = &pdev->dev;\n\tstruct device_node *np = dev->of_node;\n\tstruct bcm6318_pcie *priv = &bcm6318_pcie;\n\tstruct resource *res;\n\tint ret;\n\n\tof_pci_check_probe_only();\n\n\tres = platform_get_resource(pdev, IORESOURCE_MEM, 0);\n\tpriv->base = devm_ioremap_resource(dev, res);\n\tif (IS_ERR(priv->base))\n\t\treturn PTR_ERR(priv->base);\n\n\tpriv->irq = platform_get_irq(pdev, 0);\n\tif (!priv->irq)\n\t\treturn -ENODEV;\n\n\tbmips_pci_irq = priv->irq;\n\n\tpriv->reset = devm_reset_control_get(dev, \"pcie\");\n\tif (IS_ERR(priv->reset))\n\t\treturn PTR_ERR(priv->reset);\n\n\tpriv->reset_ext = devm_reset_control_get(dev, \"pcie-ext\");\n\tif (IS_ERR(priv->reset_ext))\n\t\treturn PTR_ERR(priv->reset_ext);\n\n\tpriv->reset_core = devm_reset_control_get(dev, \"pcie-core\");\n\tif (IS_ERR(priv->reset_core))\n\t\treturn PTR_ERR(priv->reset_core);\n\n\tpriv->reset_hard = devm_reset_control_get(dev, \"pcie-hard\");\n\tif (IS_ERR(priv->reset_hard))\n\t\treturn PTR_ERR(priv->reset_hard);\n\n\tpriv->clk = devm_clk_get(dev, \"pcie\");\n\tif (IS_ERR(priv->clk))\n\t\treturn PTR_ERR(priv->clk);\n\n\tpriv->clk25 = devm_clk_get(dev, \"pcie25\");\n\tif (IS_ERR(priv->clk25))\n\t\treturn PTR_ERR(priv->clk25);\n\n\tpriv->clk_ubus = devm_clk_get(dev, \"pcie-ubus\");\n\tif (IS_ERR(priv->clk_ubus))\n\t\treturn PTR_ERR(priv->clk_ubus);\n\n\tret = clk_prepare_enable(priv->clk);\n\tif (ret) {\n\t\tdev_err(dev, \"could not enable clock\\n\");\n\t\treturn ret;\n\t}\n\n\tret = clk_prepare_enable(priv->clk25);\n\tif (ret) {\n\t\tdev_err(dev, \"could not enable clock\\n\");\n\t\treturn ret;\n\t}\n\n\tret = clk_prepare_enable(priv->clk_ubus);\n\tif (ret) {\n\t\tdev_err(dev, \"could not enable clock\\n\");\n\t\treturn ret;\n\t}\n\n\tpci_load_of_ranges(&bcm6318_pcie_controller, np);\n\tif (!bcm6318_pcie_mem_resource.start)\n\t\treturn -EINVAL;\n\n\tof_pci_parse_bus_range(np, &bcm6318_pcie_busn_resource);\n\n\tbcm6318_pcie_reset(priv);\n\tbcm6318_pcie_setup(priv);\n\n\tregister_pci_controller(&bcm6318_pcie_controller);\n\n\treturn 0;\n}\n\nstatic const struct of_device_id bcm6318_pcie_of_match[] = {\n\t{ .compatible = \"brcm,bcm6318-pcie\", },\n\t{ /* sentinel */ }\n};\n\nstatic struct platform_driver bcm6318_pcie_driver = {\n\t.probe = bcm6318_pcie_probe,\n\t.driver\t= {\n\t\t.name = \"bcm6318-pcie\",\n\t\t.of_match_table = bcm6318_pcie_of_match,\n\t},\n};\n\nint __init bcm6318_pcie_init(void)\n{\n\tint ret = platform_driver_register(&bcm6318_pcie_driver);\n\tif (ret)\n\t\tpr_err(\"pci-bcm6318: Error registering platform driver!\\n\");\n\treturn ret;\n}\nlate_initcall_sync(bcm6318_pcie_init);\n"
  },
  {
    "path": "target/linux/bmips/files/drivers/pci/controller/pcie-bcm6328.c",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later\n/*\n * BCM6328 PCIe Controller Driver\n *\n * Copyright (C) 2020 Álvaro Fernández Rojas <noltari@gmail.com>\n * Copyright (C) 2015 Jonas Gorski <jonas.gorski@gmail.com>\n * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>\n */\n\n#include <linux/clk.h>\n#include <linux/init.h>\n#include <linux/delay.h>\n#include <linux/kernel.h>\n#include <linux/mfd/syscon.h>\n#include <linux/mm.h>\n#include <linux/of_gpio.h>\n#include <linux/of_irq.h>\n#include <linux/of_pci.h>\n#include <linux/of_platform.h>\n#include <linux/pci.h>\n#include <linux/pm_domain.h>\n#include <linux/pm_runtime.h>\n#include <linux/reset.h>\n#include <linux/regmap.h>\n#include <linux/types.h>\n#include <linux/vmalloc.h>\n\n#include \"../pci.h\"\n\n#define SERDES_PCIE_EXD_EN\t\tBIT(15)\n#define SERDES_PCIE_EN\t\t\tBIT(0)\n\n#define PCIE_BUS_BRIDGE\t\t\t0\n#define PCIE_BUS_DEVICE\t\t\t1\n\n#define PCIE_CONFIG2_REG\t\t0x408\n#define CONFIG2_BAR1_SIZE_EN\t\t1\n#define CONFIG2_BAR1_SIZE_MASK\t\t0xf\n\n#define PCIE_IDVAL3_REG\t\t\t0x43c\n#define IDVAL3_CLASS_CODE_MASK\t\t0xffffff\n#define IDVAL3_SUBCLASS_SHIFT\t\t8\n#define IDVAL3_CLASS_SHIFT\t\t16\n\n#define PCIE_DLSTATUS_REG\t\t0x1048\n#define DLSTATUS_PHYLINKUP\t\t(1 << 13)\n\n#define PCIE_BRIDGE_OPT1_REG\t\t0x2820\n#define OPT1_RD_BE_OPT_EN\t\t(1 << 7)\n#define OPT1_RD_REPLY_BE_FIX_EN\t\t(1 << 9)\n#define OPT1_PCIE_BRIDGE_HOLE_DET_EN\t(1 << 11)\n#define OPT1_L1_INT_STATUS_MASK_POL\t(1 << 12)\n\n#define PCIE_BRIDGE_OPT2_REG\t\t0x2824\n#define OPT2_UBUS_UR_DECODE_DIS\t\t(1 << 2)\n#define OPT2_TX_CREDIT_CHK_EN\t\t(1 << 4)\n#define OPT2_CFG_TYPE1_BD_SEL\t\t(1 << 7)\n#define OPT2_CFG_TYPE1_BUS_NO_SHIFT\t16\n#define OPT2_CFG_TYPE1_BUS_NO_MASK\t(0xff << OPT2_CFG_TYPE1_BUS_NO_SHIFT)\n\n#define PCIE_BRIDGE_BAR0_BASEMASK_REG\t0x2828\n#define BASEMASK_REMAP_EN\t\t(1 << 0)\n#define BASEMASK_SWAP_EN\t\t(1 << 1)\n#define BASEMASK_MASK_SHIFT\t\t4\n#define BASEMASK_MASK_MASK\t\t(0xfff << BASEMASK_MASK_SHIFT)\n#define BASEMASK_BASE_SHIFT\t\t20\n#define BASEMASK_BASE_MASK\t\t(0xfff << BASEMASK_BASE_SHIFT)\n\n#define PCIE_BRIDGE_BAR0_REBASE_ADDR_REG 0x282c\n#define REBASE_ADDR_BASE_SHIFT\t\t20\n#define REBASE_ADDR_BASE_MASK\t\t(0xfff << REBASE_ADDR_BASE_SHIFT)\n\n#define PCIE_BRIDGE_RC_INT_MASK_REG\t0x2854\n#define PCIE_RC_INT_A\t\t\t(1 << 0)\n#define PCIE_RC_INT_B\t\t\t(1 << 1)\n#define PCIE_RC_INT_C\t\t\t(1 << 2)\n#define PCIE_RC_INT_D\t\t\t(1 << 3)\n\n#define PCIE_DEVICE_OFFSET\t\t0x8000\n\nstruct bcm6328_pcie {\n\tvoid __iomem *base;\n\tint irq;\n\tstruct regmap *serdes;\n\tstruct device **pm;\n\tstruct device_link **link_pm;\n\tunsigned int num_pms;\n\tstruct clk *clk;\n\tstruct reset_control *reset;\n\tstruct reset_control *reset_ext;\n\tstruct reset_control *reset_core;\n\tstruct reset_control *reset_hard;\n};\n\nstatic struct bcm6328_pcie bcm6328_pcie;\n\nextern int bmips_pci_irq;\n\n/*\n * swizzle 32bits data to return only the needed part\n */\nstatic int postprocess_read(u32 data, int where, unsigned int size)\n{\n\tu32 ret = 0;\n\n\tswitch (size) {\n\tcase 1:\n\t\tret = (data >> ((where & 3) << 3)) & 0xff;\n\t\tbreak;\n\tcase 2:\n\t\tret = (data >> ((where & 3) << 3)) & 0xffff;\n\t\tbreak;\n\tcase 4:\n\t\tret = data;\n\t\tbreak;\n\t}\n\n\treturn ret;\n}\n\nstatic int preprocess_write(u32 orig_data, u32 val, int where,\n\t\t\t    unsigned int size)\n{\n\tu32 ret = 0;\n\n\tswitch (size) {\n\tcase 1:\n\t\tret = (orig_data & ~(0xff << ((where & 3) << 3))) |\n\t\t      (val << ((where & 3) << 3));\n\t\tbreak;\n\tcase 2:\n\t\tret = (orig_data & ~(0xffff << ((where & 3) << 3))) |\n\t\t      (val << ((where & 3) << 3));\n\t\tbreak;\n\tcase 4:\n\t\tret = val;\n\t\tbreak;\n\t}\n\n\treturn ret;\n}\n\nstatic int bcm6328_pcie_can_access(struct pci_bus *bus, int devfn)\n{\n\tstruct bcm6328_pcie *priv = &bcm6328_pcie;\n\n\tswitch (bus->number) {\n\tcase PCIE_BUS_BRIDGE:\n\t\treturn PCI_SLOT(devfn) == 0;\n\tcase PCIE_BUS_DEVICE:\n\t\tif (PCI_SLOT(devfn) == 0)\n\t\t\treturn __raw_readl(priv->base + PCIE_DLSTATUS_REG)\n\t\t\t       & DLSTATUS_PHYLINKUP;\n\t\t/* else, fall through */\n\tdefault:\n\t\treturn false;\n\t}\n}\n\nstatic int bcm6328_pcie_read(struct pci_bus *bus, unsigned int devfn,\n\t\t\t     int where, int size, u32 *val)\n{\n\tstruct bcm6328_pcie *priv = &bcm6328_pcie;\n\tu32 data;\n\tu32 reg = where & ~3;\n\n\tif (!bcm6328_pcie_can_access(bus, devfn))\n\t\treturn PCIBIOS_DEVICE_NOT_FOUND;\n\n\tif (bus->number == PCIE_BUS_DEVICE)\n\t\treg += PCIE_DEVICE_OFFSET;\n\n\tdata = __raw_readl(priv->base + reg);\n\t*val = postprocess_read(data, where, size);\n\n\treturn PCIBIOS_SUCCESSFUL;\n}\n\nstatic int bcm6328_pcie_write(struct pci_bus *bus, unsigned int devfn,\n\t\t\t      int where, int size, u32 val)\n{\n\tstruct bcm6328_pcie *priv = &bcm6328_pcie;\n\tu32 data;\n\tu32 reg = where & ~3;\n\n\tif (!bcm6328_pcie_can_access(bus, devfn))\n\t\treturn PCIBIOS_DEVICE_NOT_FOUND;\n\n\tif (bus->number == PCIE_BUS_DEVICE)\n\t\treg += PCIE_DEVICE_OFFSET;\n\n\tdata = __raw_readl(priv->base + reg);\n\tdata = preprocess_write(data, val, where, size);\n\t__raw_writel(data, priv->base + reg);\n\n\treturn PCIBIOS_SUCCESSFUL;\n}\n\nstatic struct pci_ops bcm6328_pcie_ops = {\n\t.read = bcm6328_pcie_read,\n\t.write = bcm6328_pcie_write,\n};\n\nstatic struct resource bcm6328_pcie_io_resource;\nstatic struct resource bcm6328_pcie_mem_resource;\nstatic struct resource bcm6328_pcie_busn_resource;\n\nstatic struct pci_controller bcm6328_pcie_controller = {\n\t.pci_ops = &bcm6328_pcie_ops,\n\t.io_resource = &bcm6328_pcie_io_resource,\n\t.mem_resource = &bcm6328_pcie_mem_resource,\n\t.busn_resource = &bcm6328_pcie_busn_resource,\n};\n\nstatic void bcm6328_pcie_reset(struct bcm6328_pcie *priv)\n{\n\tregmap_write_bits(priv->serdes, 0,\n\t\t\t  SERDES_PCIE_EXD_EN | SERDES_PCIE_EN,\n\t\t\t  SERDES_PCIE_EXD_EN | SERDES_PCIE_EN);\n\n\treset_control_assert(priv->reset);\n\treset_control_assert(priv->reset_core);\n\treset_control_assert(priv->reset_ext);\n\tif (priv->reset_hard) {\n\t\treset_control_assert(priv->reset_hard);\n\t\tmdelay(10);\n\t\treset_control_deassert(priv->reset_hard);\n\t}\n\tmdelay(10);\n\n\treset_control_deassert(priv->reset_core);\n\treset_control_deassert(priv->reset);\n\tmdelay(10);\n\n\treset_control_deassert(priv->reset_ext);\n\tmdelay(200);\n}\n\nstatic void bcm6328_pcie_setup(struct bcm6328_pcie *priv)\n{\n\tu32 val;\n\n\tval = __raw_readl(priv->base + PCIE_BRIDGE_OPT1_REG);\n\tval |= OPT1_RD_BE_OPT_EN;\n\tval |= OPT1_RD_REPLY_BE_FIX_EN;\n\tval |= OPT1_PCIE_BRIDGE_HOLE_DET_EN;\n\tval |= OPT1_L1_INT_STATUS_MASK_POL;\n\t__raw_writel(val, priv->base + PCIE_BRIDGE_OPT1_REG);\n\n\tval = __raw_readl(priv->base + PCIE_BRIDGE_RC_INT_MASK_REG);\n\tval |= PCIE_RC_INT_A;\n\tval |= PCIE_RC_INT_B;\n\tval |= PCIE_RC_INT_C;\n\tval |= PCIE_RC_INT_D;\n\t__raw_writel(val, priv->base + PCIE_BRIDGE_RC_INT_MASK_REG);\n\n\tval = __raw_readl(priv->base + PCIE_BRIDGE_OPT2_REG);\n\t/* enable credit checking and error checking */\n\tval |= OPT2_TX_CREDIT_CHK_EN;\n\tval |= OPT2_UBUS_UR_DECODE_DIS;\n\t/* set device bus/func for the pcie device */\n\tval |= (PCIE_BUS_DEVICE << OPT2_CFG_TYPE1_BUS_NO_SHIFT);\n\tval |= OPT2_CFG_TYPE1_BD_SEL;\n\t__raw_writel(val, priv->base + PCIE_BRIDGE_OPT2_REG);\n\n\t/* setup class code as bridge */\n\tval = __raw_readl(priv->base + PCIE_IDVAL3_REG);\n\tval &= ~IDVAL3_CLASS_CODE_MASK;\n\tval |= (PCI_CLASS_BRIDGE_PCI << IDVAL3_SUBCLASS_SHIFT);\n\t__raw_writel(val, priv->base + PCIE_IDVAL3_REG);\n\n\t/* disable bar1 size */\n\tval = __raw_readl(priv->base + PCIE_CONFIG2_REG);\n\tval &= ~CONFIG2_BAR1_SIZE_MASK;\n\t__raw_writel(val, priv->base + PCIE_CONFIG2_REG);\n\n\t/* set bar0 to little endian */\n\tval = (bcm6328_pcie_mem_resource.start >> 20)\n\t      << BASEMASK_BASE_SHIFT;\n\tval |= (bcm6328_pcie_mem_resource.end >> 20) << BASEMASK_MASK_SHIFT;\n\tval |= BASEMASK_REMAP_EN;\n\t__raw_writel(val, priv->base + PCIE_BRIDGE_BAR0_BASEMASK_REG);\n\n\tval = (bcm6328_pcie_mem_resource.start >> 20)\n\t      << REBASE_ADDR_BASE_SHIFT;\n\t__raw_writel(val, priv->base + PCIE_BRIDGE_BAR0_REBASE_ADDR_REG);\n}\n\nstatic int bcm6328_pcie_probe(struct platform_device *pdev)\n{\n\tstruct device *dev = &pdev->dev;\n\tstruct device_node *np = dev->of_node;\n\tstruct bcm6328_pcie *priv = &bcm6328_pcie;\n\tstruct resource *res;\n\tunsigned int i;\n\tint ret;\n\n\tpm_runtime_enable(dev);\n\tpm_runtime_no_callbacks(dev);\n\n\tpriv->num_pms = of_count_phandle_with_args(np, \"power-domains\",\n\t\t\t\t\t\t   \"#power-domain-cells\");\n\tif (priv->num_pms > 1) {\n\t\tpriv->pm = devm_kcalloc(dev, priv->num_pms,\n\t\t\t\t\tsizeof(struct device *), GFP_KERNEL);\n\t\tif (!priv->pm)\n\t\t\treturn -ENOMEM;\n\n\t\tpriv->link_pm = devm_kcalloc(dev, priv->num_pms,\n\t\t\t\t\t     sizeof(struct device_link *),\n\t\t\t\t\t     GFP_KERNEL);\n\t\tif (!priv->link_pm)\n\t\t\treturn -ENOMEM;\n\n\t\tfor (i = 0; i < priv->num_pms; i++) {\n\t\t\tpriv->pm[i] = genpd_dev_pm_attach_by_id(dev, i);\n\t\t\tif (IS_ERR(priv->pm[i])) {\n\t\t\t\tdev_err(dev, \"error getting pm %d\\n\", i);\n\t\t\t\treturn -EINVAL;\n\t\t\t}\n\n\t\t\tpriv->link_pm[i] = device_link_add(dev, priv->pm[i],\n\t\t\t\tDL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME |\n\t\t\t\tDL_FLAG_RPM_ACTIVE);\n\t\t}\n\t}\n\n\tret = pm_runtime_get_sync(dev);\n\tif (ret < 0) {\n\t\tpm_runtime_disable(dev);\n\t\tdev_info(dev, \"PM prober defer: ret=%d\\n\", ret);\n\t\treturn -EPROBE_DEFER;\n\t}\n\n\tof_pci_check_probe_only();\n\n\tres = platform_get_resource(pdev, IORESOURCE_MEM, 0);\n\tpriv->base = devm_ioremap_resource(dev, res);\n\tif (IS_ERR(priv->base))\n\t\treturn PTR_ERR(priv->base);\n\n\tpriv->irq = platform_get_irq(pdev, 0);\n\tif (!priv->irq)\n\t\treturn -ENODEV;\n\n\tbmips_pci_irq = priv->irq;\n\n\tpriv->serdes = syscon_regmap_lookup_by_phandle(np, \"brcm,serdes\");\n\tif (IS_ERR(priv->serdes))\n\t\treturn PTR_ERR(priv->serdes);\n\n\tpriv->reset = devm_reset_control_get(dev, \"pcie\");\n\tif (IS_ERR(priv->reset))\n\t\treturn PTR_ERR(priv->reset);\n\n\tpriv->reset_ext = devm_reset_control_get(dev, \"pcie-ext\");\n\tif (IS_ERR(priv->reset_ext))\n\t\treturn PTR_ERR(priv->reset_ext);\n\n\tpriv->reset_core = devm_reset_control_get(dev, \"pcie-core\");\n\tif (IS_ERR(priv->reset_core))\n\t\treturn PTR_ERR(priv->reset_core);\n\n\tpriv->reset_hard = devm_reset_control_get_optional(dev, \"pcie-hard\");\n\tif (IS_ERR(priv->reset_hard))\n\t\treturn PTR_ERR(priv->reset_hard);\n\n\tpriv->clk = devm_clk_get(dev, \"pcie\");\n\tif (IS_ERR(priv->clk))\n\t\treturn PTR_ERR(priv->clk);\n\n\tret = clk_prepare_enable(priv->clk);\n\tif (ret) {\n\t\tdev_err(dev, \"could not enable clock\\n\");\n\t\treturn ret;\n\t}\n\n\tpci_load_of_ranges(&bcm6328_pcie_controller, np);\n\tif (!bcm6328_pcie_mem_resource.start)\n\t\treturn -EINVAL;\n\n\tof_pci_parse_bus_range(np, &bcm6328_pcie_busn_resource);\n\n\tbcm6328_pcie_reset(priv);\n\tbcm6328_pcie_setup(priv);\n\n\tregister_pci_controller(&bcm6328_pcie_controller);\n\n\treturn 0;\n}\n\nstatic const struct of_device_id bcm6328_pcie_of_match[] = {\n\t{ .compatible = \"brcm,bcm6328-pcie\", },\n\t{ /* sentinel */ }\n};\n\nstatic struct platform_driver bcm6328_pcie_driver = {\n\t.probe = bcm6328_pcie_probe,\n\t.driver\t= {\n\t\t.name = \"bcm6328-pcie\",\n\t\t.of_match_table = bcm6328_pcie_of_match,\n\t},\n};\n\nint __init bcm6328_pcie_init(void)\n{\n\tint ret = platform_driver_register(&bcm6328_pcie_driver);\n\tif (ret)\n\t\tpr_err(\"pci-bcm6328: Error registering platform driver!\\n\");\n\treturn ret;\n}\nlate_initcall_sync(bcm6328_pcie_init);\n"
  },
  {
    "path": "target/linux/bmips/files/include/dt-bindings/interrupt-controller/bcm6318-interrupt-controller.h",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later\n\n#ifndef __DT_BINDINGS_INTERRUPT_CONTROLLER_BCM6318_H\n#define __DT_BINDINGS_INTERRUPT_CONTROLLER_BCM6318_H\n\n#define BCM6318_IRQ_TIMER0\t\t0\n#define BCM6318_IRQ_TIMER1\t\t1\n#define BCM6318_IRQ_TIMER2\t\t2\n#define BCM6318_IRQ_TIMER3\t\t3\n#define BCM6318_IRQ_USBS\t\t4\n#define BCM6318_IRQ_USB_CTL_RX_DMA\t5\n#define BCM6318_IRQ_USB_CTL_TX_DMA\t6\n#define BCM6318_IRQ_USB_BULK_RX_DMA\t7\n#define BCM6318_IRQ_USB_BULK_TX_DMA\t8\n#define BCM6318_IRQ_USB_ISO_RX_DMA\t9\n#define BCM6318_IRQ_USB_ISO_TX_DMA\t10\n#define BCM6318_IRQ_DG\t\t\t11\n#define BCM6318_IRQ_EPHY\t\t12\n#define BCM6318_IRQ_EPHY_EN0N\t\t13\n#define BCM6318_IRQ_EPHY_EN1N\t\t14\n#define BCM6318_IRQ_EPHY_EN2N\t\t15\n#define BCM6318_IRQ_EPHY_EN3N\t\t16\n#define BCM6318_IRQ_EPHY_EN0\t\t17\n#define BCM6318_IRQ_EPHY_EN1\t\t18\n#define BCM6318_IRQ_EPHY_EN2\t\t19\n#define BCM6318_IRQ_EPHY_EN3\t\t20\n#define BCM6318_IRQ_XDSL\t\t21\n#define BCM6318_IRQ_SDR\t\t\t22\n#define BCM6318_IRQ_PCIE_RC\t\t23\n#define BCM6318_IRQ_EXT0\t\t24\n#define BCM6318_IRQ_EXT1\t\t25\n#define BCM6318_IRQ_EXT2\t\t26\n#define BCM6318_IRQ_EXT3\t\t27\n#define BCM6318_IRQ_UART0\t\t28\n#define BCM6318_IRQ_HSSPI\t\t29\n#define BCM6318_IRQ_WAKE_ON_IRQ\t\t30\n#define BCM6318_IRQ_TIMER\t\t31\n#define BCM6318_IRQ_ENETSW_RX_DMA0\t32\n#define BCM6318_IRQ_ENETSW_RX_DMA1\t33\n#define BCM6318_IRQ_ENETSW_RX_DMA2\t34\n#define BCM6318_IRQ_ENETSW_RX_DMA3\t35\n#define BCM6318_IRQ_WDTIMER\t\t37\n#define BCM6318_IRQ_ENETSW\t\t40\n#define BCM6318_IRQ_OHCI\t\t41\n#define BCM6318_IRQ_EHCI\t\t42\n#define BCM6318_IRQ_ATM_DMA0\t\t43\n#define BCM6318_IRQ_ATM_DMA1\t\t44\n#define BCM6318_IRQ_ATM_DMA2\t\t45\n#define BCM6318_IRQ_ATM_DMA3\t\t46\n#define BCM6318_IRQ_ATM_DMA4\t\t47\n#define BCM6318_IRQ_ATM_DMA5\t\t48\n#define BCM6318_IRQ_ATM_DMA6\t\t49\n#define BCM6318_IRQ_ATM_DMA7\t\t50\n#define BCM6318_IRQ_ATM_DMA8\t\t51\n#define BCM6318_IRQ_ATM_DMA9\t\t52\n#define BCM6318_IRQ_ATM_DMA10\t\t53\n#define BCM6318_IRQ_ATM_DMA11\t\t54\n#define BCM6318_IRQ_ATM_DMA12\t\t55\n#define BCM6318_IRQ_ATM_DMA13\t\t56\n#define BCM6318_IRQ_ATM_DMA14\t\t57\n#define BCM6318_IRQ_ATM_DMA15\t\t58\n#define BCM6318_IRQ_ATM_DMA16\t\t59\n#define BCM6318_IRQ_ATM_DMA17\t\t60\n#define BCM6318_IRQ_ATM_DMA18\t\t61\n#define BCM6318_IRQ_ATM_DMA19\t\t62\n#define BCM6318_IRQ_SAR\t\t\t63\n#define BCM6318_IRQ_ADSL_ENERGY\t\t64\n#define BCM6318_IRQ_ADSL_ENERGY_N\t65\n#define BCM6318_IRQ_USB_ENERGY_ON\t66\n#define BCM6318_IRQ_USB_ENERGY_OFF\t67\n#define BCM6318_IRQ_PVTMON_TEMP\t\t68\n#define BCM6318_IRQ_SYSPLL_LOCK\t\t69\n#define BCM6318_IRQ_LCPLL_LOCK\t\t70\n#define BCM6318_IRQ_PMU_STABLE\t\t71\n#define BCM6318_IRQ_ENETSW_TX_DMA0\t72\n#define BCM6318_IRQ_ENETSW_TX_DMA1\t73\n#define BCM6318_IRQ_ENETSW_TX_DMA2\t74\n#define BCM6318_IRQ_ENETSW_TX_DMA3\t75\n#define BCM6318_IRQ_EPHY0_IDDQ_ENERGY\t76\n#define BCM6318_IRQ_EPHY1_IDDQ_ENERGY\t77\n#define BCM6318_IRQ_EPHY2_IDDQ_ENERGY\t78\n#define BCM6318_IRQ_EPHY3_IDDQ_ENERGY\t79\n\n#endif /* __DT_BINDINGS_INTERRUPT_CONTROLLER_BCM6318_H */\n"
  },
  {
    "path": "target/linux/bmips/files/include/dt-bindings/interrupt-controller/bcm63268-interrupt-controller.h",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later\n\n#ifndef __DT_BINDINGS_INTERRUPT_CONTROLLER_BCM63268_H\n#define __DT_BINDINGS_INTERRUPT_CONTROLLER_BCM63268_H\n\n#define BCM63268_IRQ_TIMER\t\t0\n#define BCM63268_IRQ_ENETSW_RX_DMA0\t1\n#define BCM63268_IRQ_ENETSW_RX_DMA1\t2\n#define BCM63268_IRQ_ENETSW_RX_DMA2\t3\n#define BCM63268_IRQ_ENETSW_RX_DMA3\t4\n#define BCM63268_IRQ_UART0\t\t5\n#define BCM63268_IRQ_HSSPI\t\t6\n#define BCM63268_IRQ_WLAN\t\t7\n#define BCM63268_IRQ_IPSEC\t\t8\n#define BCM63268_IRQ_OHCI\t\t9\n#define BCM63268_IRQ_EHCI\t\t10\n#define BCM63268_IRQ_USBS\t\t11\n#define BCM63268_IRQ_PCM\t\t12\n#define BCM63268_IRQ_EPHY\t\t13\n#define BCM63268_IRQ_DG\t\t\t14\n#define BCM63268_IRQ_EPHY0_EN\t\t15\n#define BCM63268_IRQ_EPHY1_EN\t\t16\n#define BCM63268_IRQ_EPHY2_EN\t\t17\n#define BCM63268_IRQ_GPHY_EN\t\t18\n#define BCM63268_IRQ_USB_CTL_RX_DMA\t19\n#define BCM63268_IRQ_USB_BULK_RX_DMA\t20\n#define BCM63268_IRQ_ISO_RX_DMA\t\t21\n#define BCM63268_IRQ_IPSEC_DMA0\t\t22\n#define BCM63268_IRQ_XDSL\t\t23\n#define BCM63268_IRQ_FAP0\t\t24\n#define BCM63268_IRQ_FAP1\t\t25\n#define BCM63268_IRQ_ATM_DMA0\t\t26\n#define BCM63268_IRQ_ATM_DMA1\t\t27\n#define BCM63268_IRQ_ATM_DMA2\t\t28\n#define BCM63268_IRQ_ATM_DMA3\t\t29\n#define BCM63268_IRQ_WAKE_ON_IRQ\t30\n#define BCM63268_IRQ_GPHY\t\t31\n#define BCM63268_IRQ_DECT0              32\t\t\n#define BCM63268_IRQ_DECT1\t\t33\n#define BCM63268_IRQ_UART1              34\t\t\n#define BCM63268_IRQ_WLAN_GPIO\t\t35\n#define BCM63268_IRQ_USB_CTL_TX_DMA\t36\n#define BCM63268_IRQ_USB_BULK_TX_DMA\t37\n#define BCM63268_IRQ_ISO_TX_DMA\t\t38\n#define BCM63268_IRQ_IPSEC_DMA1\t\t39\n#define BCM63268_IRQ_PCIE_RC\t\t40\n#define BCM63268_IRQ_PCIE_EP\t\t41\n#define BCM63268_IRQ_PCM_DMA0\t\t42\n#define BCM63268_IRQ_PCM_DMA1\t\t43\n#define BCM63268_IRQ_EXT0\t\t44\n#define BCM63268_IRQ_EXT1\t\t45\n#define BCM63268_IRQ_EXT2\t\t46\n#define BCM63268_IRQ_EXT3\t\t47\n#define BCM63268_IRQ_ENETSW\t\t48\n#define BCM63268_IRQ_SAR\t\t49\n#define BCM63268_IRQ_NAND\t\t50\n#define BCM63268_IRQ_RING_OSC\t\t52\n#define BCM63268_IRQ_USB_CONNECT\t53\n#define BCM63268_IRQ_USB_DISCONNECT\t54\n#define BCM63268_IRQ_PER_MBOX0\t\t55\n#define BCM63268_IRQ_PER_MBOX1\t\t56\n#define BCM63268_IRQ_PER_MBOX2\t\t57\n#define BCM63268_IRQ_PER_MBOX3\t\t58\n#define BCM63268_IRQ_ATM_DMA4\t\t59\n#define BCM63268_IRQ_ATM_DMA5\t\t60\n#define BCM63268_IRQ_ATM_DMA6\t\t61\n#define BCM63268_IRQ_ATM_DMA7\t\t62\n#define BCM63268_IRQ_ENETSW_TX_DMA0\t64\n#define BCM63268_IRQ_ENETSW_TX_DMA1\t65\n#define BCM63268_IRQ_ENETSW_TX_DMA2\t66\n#define BCM63268_IRQ_ENETSW_TX_DMA3\t67\n#define BCM63268_IRQ_ATM_DMA8\t\t68\n#define BCM63268_IRQ_ATM_DMA9\t\t69\n#define BCM63268_IRQ_ATM_DMA10\t\t70\n#define BCM63268_IRQ_ATM_DMA11\t\t71\n#define BCM63268_IRQ_ATM_DMA12\t\t72\n#define BCM63268_IRQ_ATM_DMA13\t\t73\n#define BCM63268_IRQ_ATM_DMA14\t\t74\n#define BCM63268_IRQ_ATM_DMA15\t\t75\n#define BCM63268_IRQ_ATM_DMA16\t\t76\n#define BCM63268_IRQ_ATM_DMA17\t\t77\n#define BCM63268_IRQ_ATM_DMA18\t\t78\n#define BCM63268_IRQ_ATM_DMA19\t\t79\n#define BCM63268_IRQ_LSSPI\t\t80\n\n#endif /* __DT_BINDINGS_INTERRUPT_CONTROLLER_BCM63268_H */\n"
  },
  {
    "path": "target/linux/bmips/files/include/dt-bindings/interrupt-controller/bcm6328-interrupt-controller.h",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later\n\n#ifndef __DT_BINDINGS_INTERRUPT_CONTROLLER_BCM6328_H\n#define __DT_BINDINGS_INTERRUPT_CONTROLLER_BCM6328_H\n\n#define BCM6328_IRQ_NAND\t\t0\n#define BCM6328_IRQ_PCM\t\t\t1\n#define BCM6328_IRQ_PCM_DMA0\t\t2\n#define BCM6328_IRQ_PCM_DMA1\t\t3\n#define BCM6328_IRQ_USBS\t\t4\n#define BCM6328_IRQ_USB_CTL_RX_DMA\t5\n#define BCM6328_IRQ_USB_CTL_TX_DMA\t6\n#define BCM6328_IRQ_USB_BULK_RX_DMA\t7\n#define BCM6328_IRQ_USB_BULK_TX_DMA\t8\n#define BCM6328_IRQ_USB_ISO_RX_DMA\t9\n#define BCM6328_IRQ_USB_ISO_TX_DMA\t10\n#define BCM6328_IRQ_DG\t\t\t11\n#define BCM6328_IRQ_EPHY\t\t12\n#define BCM6328_IRQ_EPHY_EN0N\t\t13\n#define BCM6328_IRQ_EPHY_EN1N\t\t14\n#define BCM6328_IRQ_EPHY_EN2N\t\t15\n#define BCM6328_IRQ_EPHY_EN3N\t\t16\n#define BCM6328_IRQ_EPHY_EN0\t\t17\n#define BCM6328_IRQ_EPHY_EN1\t\t18\n#define BCM6328_IRQ_EPHY_EN2\t\t19\n#define BCM6328_IRQ_EPHY_EN3\t\t20\n#define BCM6328_IRQ_XDSL\t\t21\n#define BCM6328_IRQ_PCIE_EP\t\t22\n#define BCM6328_IRQ_PCIE_RC\t\t23\n#define BCM6328_IRQ_EXTO\t\t24\n#define BCM6328_IRQ_EXT1\t\t25\n#define BCM6328_IRQ_EXT2\t\t26\n#define BCM6328_IRQ_EXT3\t\t27\n#define BCM6328_IRQ_UART0\t\t28\n#define BCM6328_IRQ_HSSPI\t\t29\n#define BCM6328_IRQ_WAKE_ON_IRQ\t\t30\n#define BCM6328_IRQ_TIMER\t\t31\n#define BCM6328_IRQ_ENETSW_RX_DMA0\t32\n#define BCM6328_IRQ_ENETSW_RX_DMA1\t33\n#define BCM6328_IRQ_ENETSW_TX_DMA0\t34\n#define BCM6328_IRQ_ENETSW_TX_DMA1\t35\n#define BCM6328_IRQ_UART1\t\t39\n#define BCM6328_IRQ_ENETSW\t\t40\n#define BCM6328_IRQ_OHCI\t\t41\n#define BCM6328_IRQ_EHCI\t\t42\n#define BCM6328_IRQ_ATM_DMA0\t\t43\n#define BCM6328_IRQ_ATM_DMA1\t\t44\n#define BCM6328_IRQ_ATM_DMA2\t\t45\n#define BCM6328_IRQ_ATM_DMA3\t\t46\n#define BCM6328_IRQ_ATM_DMA4\t\t47\n#define BCM6328_IRQ_ATM_DMA5\t\t48\n#define BCM6328_IRQ_ATM_DMA6\t\t49\n#define BCM6328_IRQ_ATM_DMA7\t\t50\n#define BCM6328_IRQ_ATM_DMA8\t\t51\n#define BCM6328_IRQ_ATM_DMA9\t\t52\n#define BCM6328_IRQ_ATM_DMA10\t\t53\n#define BCM6328_IRQ_ATM_DMA11\t\t54\n#define BCM6328_IRQ_ATM_DMA12\t\t55\n#define BCM6328_IRQ_ATM_DMA13\t\t56\n#define BCM6328_IRQ_ATM_DMA14\t\t57\n#define BCM6328_IRQ_ATM_DMA15\t\t58\n#define BCM6328_IRQ_ATM_DMA16\t\t59\n#define BCM6328_IRQ_ATM_DMA17\t\t60\n#define BCM6328_IRQ_ATM_DMA18\t\t61\n#define BCM6328_IRQ_ATM_DMA19\t\t62\n#define BCM6328_IRQ_SAR\t\t\t63\n\n#endif /* __DT_BINDINGS_INTERRUPT_CONTROLLER_BCM6328_H */\n"
  },
  {
    "path": "target/linux/bmips/files/include/dt-bindings/interrupt-controller/bcm6358-interrupt-controller.h",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later\n\n#ifndef __DT_BINDINGS_INTERRUPT_CONTROLLER_BCM6358_H\n#define __DT_BINDINGS_INTERRUPT_CONTROLLER_BCM6358_H\n\n#define BCM6358_IRQ_TIMER\t\t0\n#define BCM6358_IRQ_SPI\t\t\t1\n#define BCM6358_IRQ_UART0\t\t2\n#define BCM6358_IRQ_UART1\t\t3\n#define BCM6358_IRQ_OHCI\t\t5\n#define BCM6358_IRQ_EMAC1\t\t6\n#define BCM6358_IRQ_USBS\t\t7\n#define BCM6358_IRQ_EMAC0\t\t8\n#define BCM6358_IRQ_EPHY\t\t9\n#define BCM6358_IRQ_EHCI\t\t10\n#define BCM6358_IRQ_USB_CTL_RX_DMA\t11\n#define BCM6358_IRQ_USB_CTL_TX_DMA\t12\n#define BCM6358_IRQ_USB_BULK_RX_DMA\t13\n#define BCM6358_IRQ_USB_BULK_TX_DMA\t14\n#define BCM6358_IRQ_EMAC0_RX_DMA\t15\n#define BCM6358_IRQ_EMAC0_TX_DMA\t16\n#define BCM6358_IRQ_EMAC1_RX_DMA\t17\n#define BCM6358_IRQ_EMAC1_TX_DMA\t18\n#define BCM6358_IRQ_ATM\t\t        19\n#define BCM6358_IRQ_EXT4\t\t20\n#define BCM6358_IRQ_EXT5\t\t21\n#define BCM6358_IRQ_PCM\t\t\t22\n#define BCM6358_IRQ_PCM_RX_DMA\t\t23\n#define BCM6358_IRQ_PCM_TX_DMA\t\t24\n#define BCM6358_IRQ_EXT0\t\t25\n#define BCM6358_IRQ_EXT1\t\t26\n#define BCM6358_IRQ_EXT2\t\t27\n#define BCM6358_IRQ_EXT3\t\t28\n#define BCM6358_IRQ_ADSL\t\t29\n#define BCM6358_IRQ_DG\t\t\t30\n#define BCM6358_IRQ_MPI\t\t\t31\n\n#endif /* __DT_BINDINGS_INTERRUPT_CONTROLLER_BCM6358_H */\n"
  },
  {
    "path": "target/linux/bmips/files/include/dt-bindings/interrupt-controller/bcm6362-interrupt-controller.h",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later\n\n#ifndef __DT_BINDINGS_INTERRUPT_CONTROLLER_BCM6362_H\n#define __DT_BINDINGS_INTERRUPT_CONTROLLER_BCM6362_H\n\n#define BCM6362_IRQ_TIMER\t\t0\n#define BCM6362_IRQ_RING_OSC\t\t1\n#define BCM6362_IRQ_LSSPI\t\t2\n#define BCM6362_IRQ_UART0\t\t3\n#define BCM6362_IRQ_UART1\t\t4\n#define BCM6362_IRQ_HSSPI\t\t5\n#define BCM6362_IRQ_WLAN_GPIO\t\t6\n#define BCM6362_IRQ_WLAN\t\t7\n#define BCM6362_IRQ_IPSEC\t\t8\n#define BCM6362_IRQ_OHCI\t\t9\n#define BCM6362_IRQ_EHCI\t\t10\n#define BCM6362_IRQ_USBS\t\t11\n#define BCM6362_IRQ_NAND\t\t12\n#define BCM6362_IRQ_PCM\t\t\t13\n#define BCM6362_IRQ_EPHY\t\t14\n#define BCM6362_IRQ_DF\t\t\t15\n#define BCM6362_IRQ_EPHY_EN0\t\t16\n#define BCM6362_IRQ_EPHY_EN1\t\t17\n#define BCM6362_IRQ_EPHY_EN2\t\t18\n#define BCM6362_IRQ_EPHY_EN3\t\t19\n#define BCM6362_IRQ_USB_CTL_RX_DMA\t20\n#define BCM6362_IRQ_USB_CTL_TX_DMA\t21\n#define BCM6362_IRQ_USB_BULK_RX_DMA\t22\n#define BCM6362_IRQ_USB_BULK_TX_DMA\t23\n#define BCM6362_IRQ_USB_ISO_RX_DMA\t24\n#define BCM6362_IRQ_USB_ISO_TX_DMA\t25\n#define BCM6362_IRQ_IPSEC_DMA0\t\t26\n#define BCM6362_IRQ_IPSEC_DMA1\t\t27\n#define BCM6362_IRQ_XDSL\t\t28\n#define BCM6362_IRQ_FAP\t\t\t29\n#define BCM6362_IRQ_PCIE_RC\t\t30\n#define BCM6362_IRQ_PCIE_EP\t\t31\n#define BCM6362_IRQ_ENETSW_RX_DMA0\t32\n#define BCM6362_IRQ_ENETSW_RX_DMA1\t33\n#define BCM6362_IRQ_ENETSW_RX_DMA2\t34\n#define BCM6362_IRQ_ENETSW_RX_DMA3\t35\n#define BCM6362_IRQ_PCM_DMA0\t\t36\n#define BCM6362_IRQ_PCM_DMA1\t\t37\n#define BCM6362_IRQ_DECT0\t\t38\n#define BCM6362_IRQ_DECT1\t\t39\n#define BCM6362_IRQ_EXT0\t\t40\n#define BCM6362_IRQ_EXT1\t\t41\n#define BCM6362_IRQ_EXT2\t\t42\n#define BCM6362_IRQ_EXT3\t\t43\n#define BCM6362_IRQ_ATM_DMA0\t\t44\n#define BCM6362_IRQ_ATM_DMA1\t\t45\n#define BCM6362_IRQ_ATM_DMA2\t\t46\n#define BCM6362_IRQ_ATM_DMA3\t\t47\n#define BCM6362_IRQ_ATM_DMA4\t\t48\n#define BCM6362_IRQ_ATM_DMA5\t\t49\n#define BCM6362_IRQ_ATM_DMA6\t\t50\n#define BCM6362_IRQ_ATM_DMA7\t\t51\n#define BCM6362_IRQ_ATM_DMA8\t\t52\n#define BCM6362_IRQ_ATM_DMA9\t\t53\n#define BCM6362_IRQ_ATM_DMA10\t\t54\n#define BCM6362_IRQ_ATM_DMA11\t\t55\n#define BCM6362_IRQ_ATM_DMA12\t\t56\n#define BCM6362_IRQ_ATM_DMA13\t\t57\n#define BCM6362_IRQ_ATM_DMA14\t\t58\n#define BCM6362_IRQ_ATM_DMA15\t\t59\n#define BCM6362_IRQ_ATM_DMA16\t\t60\n#define BCM6362_IRQ_ATM_DMA17\t\t61\n#define BCM6362_IRQ_ATM_DMA18\t\t62\t\t\n#define BCM6362_IRQ_ATM_DMA19\t\t63\n\n#endif /* __DT_BINDINGS_INTERRUPT_CONTROLLER_BCM6362_H */\n"
  },
  {
    "path": "target/linux/bmips/files/include/dt-bindings/interrupt-controller/bcm6368-interrupt-controller.h",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later\n\n#ifndef __DT_BINDINGS_INTERRUPT_CONTROLLER_BCM6368_H\n#define __DT_BINDINGS_INTERRUPT_CONTROLLER_BCM6368_H\n\n#define BCM6368_IRQ_TIMER\t\t0\n#define BCM6368_IRQ_SPI\t\t\t1\n#define BCM6368_IRQ_UART0\t\t2\n#define BCM6368_IRQ_UART1\t\t3\n#define BCM6368_IRQ_XDSL\t\t4\n#define BCM6368_IRQ_OHCI\t\t5\n#define BCM6368_IRQ_IPSEC\t\t6\n#define BCM6368_IRQ_EHCI\t\t7\n#define BCM6368_IRQ_USBS\t\t8\n#define BCM6368_IRQ_RING_OSC\t\t9\n#define BCM6368_IRQ_NAND\t\t10\n#define BCM6368_IRQ_ATM\t\t\t11\n#define BCM6368_IRQ_PCM\t\t\t12\n#define BCM6368_IRQ_MPI\t\t\t13\n#define BCM6368_IRQ_DG\t\t\t14\n#define BCM6368_IRQ_EPHY\t\t15\n#define BCM6368_IRQ_EPHY_EN0\t\t16\n#define BCM6368_IRQ_EPHY_EN1\t\t17\n#define BCM6368_IRQ_EPHY_EN2\t\t18\n#define BCM6368_IRQ_EPHY_EN3\t\t19\n#define BCM6368_IRQ_EXT0\t\t20\n#define BCM6368_IRQ_EXT1\t\t21\n#define BCM6368_IRQ_EXT2\t\t22\n#define BCM6368_IRQ_EXT3\t\t23\n#define BCM6368_IRQ_EXT4\t\t24\n#define BCM6368_IRQ_EXT5\t\t25\n#define BCM6368_IRQ_USB_CTL_RX_DMA\t26\n#define BCM6368_IRQ_USB_CTL_TX_DMA\t27\n#define BCM6368_IRQ_USB_BULK_RX_DMA\t28\n#define BCM6368_IRQ_USB_BULK_TX_DMA\t29\n#define BCM6368_IRQ_USB_ISO_RX_DMA\t30\n#define BCM6368_IRQ_USB_ISO_TX_DMA\t31\n#define BCM6368_IRQ_ENETSW_RX_DMA0\t32\t\n#define BCM6368_IRQ_ENETSW_RX_DMA1\t33\t\n#define BCM6368_IRQ_ENETSW_RX_DMA2\t34\t\n#define BCM6368_IRQ_ENETSW_RX_DMA3\t35\t\n#define BCM6368_IRQ_ENETSW_TX_DMA0\t36\t\n#define BCM6368_IRQ_ENETSW_TX_DMA1\t37\t\n#define BCM6368_IRQ_ENETSW_TX_DMA2\t38\t\n#define BCM6368_IRQ_ENETSW_TX_DMA3\t39\t\n#define BCM6368_IRQ_ATM_DMA0\t\t40\n#define BCM6368_IRQ_ATM_DMA1\t\t41\n#define BCM6368_IRQ_ATM_DMA2\t\t42\n#define BCM6368_IRQ_ATM_DMA3\t\t43\n#define BCM6368_IRQ_ATM_DMA4\t\t44\n#define BCM6368_IRQ_ATM_DMA5\t\t45\n#define BCM6368_IRQ_ATM_DMA6\t\t46\n#define BCM6368_IRQ_ATM_DMA7\t\t47\n#define BCM6368_IRQ_ATM_DMA8\t\t48\n#define BCM6368_IRQ_ATM_DMA9\t\t49\n#define BCM6368_IRQ_ATM_DMA10\t\t50\n#define BCM6368_IRQ_ATM_DMA11\t\t51\n#define BCM6368_IRQ_ATM_DMA12\t\t52\n#define BCM6368_IRQ_ATM_DMA13\t\t53\n#define BCM6368_IRQ_ATM_DMA14\t\t54\n#define BCM6368_IRQ_ATM_DMA15\t\t55\n#define BCM6368_IRQ_ATM_DMA16\t\t56\n#define BCM6368_IRQ_ATM_DMA17\t\t57\n#define BCM6368_IRQ_ATM_DMA18\t\t58\n#define BCM6368_IRQ_ATM_DMA19\t\t59\n#define BCM6368_IRQ_IPSEC_DMA0\t\t60\n#define BCM6368_IRQ_IPSEC_DMA1\t\t61\n#define BCM6368_IRQ_PCM_DMA0\t\t62\n#define BCM6368_IRQ_PCM_DMA1\t\t63\n\n#endif /* __DT_BINDINGS_INTERRUPT_CONTROLLER_BCM6368_H */\n"
  },
  {
    "path": "target/linux/bmips/generic/base-files/etc/board.d/01_leds",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n. /lib/functions/leds.sh\n. /lib/functions/uci-defaults.sh\n\nboard_config_update\n\nled_usb=\"$(get_dt_led usb)\"\n[ -n \"$led_usb\" ] && ucidef_set_led_usbdev \"usb\" \"usb\" \"$led_usb\" \"1-1\"\n\nled_usb2=\"$(get_dt_led usb2)\"\n[ -n \"$led_usb2\" ] && ucidef_set_led_usbdev \"usb2\" \"usb2\" \"$led_usb2\" \"2-1\"\n\nboard_config_flush\n\nexit 0\n"
  },
  {
    "path": "target/linux/bmips/generic/base-files/etc/board.d/02_network",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n. /lib/functions/uci-defaults.sh\n\nboard_config_update\n\ncase \"$(board_name)\" in\ncomtrend,ar-5315u |\\\ncomtrend,ar-5387un |\\\ncomtrend,vr-3025u)\n\tucidef_set_interface_lan \"lan1 lan2 lan3 lan4\"\n\t;;\nesac\n\nboard_config_flush\n\nexit 0\n"
  },
  {
    "path": "target/linux/bmips/generic/base-files/etc/uci-defaults/09_fix_crc",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n. /lib/functions.sh\n\ncase \"$(board_name)\" in\n\tcomtrend,ar-5315u|\\\n\tcomtrend,ar-5387un|\\\n\tcomtrend,vr-3025u)\n\t\tmtd fixtrx firmware\n\t\t;;\nesac\n\nexit 0\n"
  },
  {
    "path": "target/linux/bmips/generic/base-files/lib/upgrade/platform.sh",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\nPART_NAME=firmware\nREQUIRE_IMAGE_METADATA=1\n\nplatform_check_image() {\n\treturn 0\n}\n\nplatform_do_upgrade() {\n\tcase \"$(board_name)\" in\n\t\t*)\n\t\t\tdefault_do_upgrade \"$1\"\n\t\t\t;;\n\tesac\n}\n"
  },
  {
    "path": "target/linux/bmips/generic/config-default",
    "content": "CONFIG_MTD_PHYSMAP=y\nCONFIG_MTD_SPI_NOR=y\nCONFIG_MTD_SPLIT_BCM63XX_FW=y\n"
  },
  {
    "path": "target/linux/bmips/generic/target.mk",
    "content": "BOARDNAME:=generic\n\ndefine Target/Description\n  BMIPS boards without NAND support \nendef\n"
  },
  {
    "path": "target/linux/bmips/image/Makefile",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\ninclude $(TOPDIR)/rules.mk\ninclude $(INCLUDE_DIR)/image.mk\n\nKERNEL_LOADADDR := 0x80010000\t\t# RAM start + 64K\nLOADER_ENTRY := 0x80a00000\t\t# RAM start + 10M, for relocate\nRAMSIZE := 0x02000000\t\t\t# 32MB\nLZMA_TEXT_START := 0x81800000\t\t# 32MB - 8MB\n\nDEVICE_VARS += CHIP_ID DEVICE_LOADADDR\n\ndefine Build/Compile\n\trm -rf $(KDIR)/relocate\n\t$(CP) ../../generic/image/relocate $(KDIR)\n\t$(MAKE) -C $(KDIR)/relocate \\\n\t\tCACHELINE_SIZE=16 \\\n\t\tCROSS_COMPILE=$(TARGET_CROSS) \\\n\t\tKERNEL_ADDR=$(KERNEL_LOADADDR) \\\n\t\tLZMA_TEXT_START=$(LOADER_ENTRY)\nendef\n\n### Kernel scripts ###\ndefine Build/loader-lzma\n\t@rm -rf $@.src\n\t$(MAKE) -C lzma-loader \\\n\t\tCHIP_ID=$(CHIP_ID) \\\n\t\tKERNEL_ADDR=$(KERNEL_LOADADDR) \\\n\t\tKDIR=$(KDIR) \\\n\t\tLOADER_ADDR=$(if $(DEVICE_LOADADDR),$(DEVICE_LOADADDR),$(LOADER_ENTRY)) \\\n\t\tLOADER_DATA=\"$@\" \\\n\t\tLOADER_NAME=\"$(notdir $@)\" \\\n\t\tLZMA_TEXT_START=$(LZMA_TEXT_START) \\\n\t\tPKG_BUILD_DIR=\"$@.src\" \\\n\t\tRAMSIZE=$(RAMSIZE) \\\n\t\tTARGET_DIR=\"$(dir $@)\" \\\n\t\tcompile loader.$(1)\n\t@mv \"$@.$(1)\" \"$@\"\n\t@rm -rf $@.src\nendef\n\ndefine Build/lzma-cfe\n\t# CFE is a LZMA nazi! It took me hours to find out the parameters!\n\t# Also I think lzma has a bug cause it generates different output depending on\n\t# if you use stdin / stdout or not. Use files instead of stdio here, cause\n\t# otherwise CFE will complain and not boot the image.\n\t$(call Build/lzma-no-dict,-d22 -fb64 -a1)\n\t# Strip out the length, CFE doesn't like this\n\tdd if=$@ of=$@.new bs=5 count=1\n\tdd if=$@ of=$@.new ibs=13 obs=5 skip=1 seek=1 conv=notrunc\n\t@mv $@.new $@\nendef\n\ndefine Build/relocate-kernel\n\t# CFE only allows ~4 MiB for the uncompressed kernels, but uncompressed\n\t# kernel might get larger than that, so let CFE unpack and load at a\n\t# higher address and make the kernel relocate itself to the expected\n\t# location.\n\t( \\\n\t\tdd if=$(KDIR)/relocate/loader.bin bs=32 conv=sync && \\\n\t\tperl -e '@s = stat(\"$@\"); print pack(\"N\", @s[7])' && \\\n\t\tcat $@ \\\n\t) > $@.relocate\n\t@mv $@.relocate $@\nendef\n\n### Image scripts ###\ndefine rootfspad/jffs2-128k\n--align-rootfs\nendef\ndefine rootfspad/jffs2-64k\n--align-rootfs\nendef\ndefine rootfspad/squashfs\nendef\n\ndefine Image/FileSystemStrip\n$(firstword $(subst +,$(space),$(subst root.,,$(notdir $(1)))))\nendef\n\ndefine Build/cfe-bin\n\t$(STAGING_DIR_HOST)/bin/imagetag -i $(IMAGE_KERNEL) -f $(IMAGE_ROOTFS) \\\n\t\t--output $@ --boardid $(CFE_BOARD_ID) --chipid $(CHIP_ID) \\\n\t\t--entry $(LOADER_ENTRY) --load-addr $(LOADER_ENTRY) \\\n\t\t--info1 \"$(call ModelNameLimit16,$(DEVICE_NAME))\" \\\n\t\t--info2 \"$(call Image/FileSystemStrip,$(IMAGE_ROOTFS))\" \\\n\t\t$(call rootfspad/$(call Image/FileSystemStrip,$(IMAGE_ROOTFS))) \\\n\t\t$(CFE_EXTRAS) $(1)\nendef\n\ndefine Build/cfe-jffs2\n\t$(STAGING_DIR_HOST)/bin/mkfs.jffs2 \\\n\t\t--big-endian \\\n\t\t--pad \\\n\t\t--no-cleanmarkers \\\n\t\t--eraseblock=$(patsubst %k,%KiB,$(BLOCKSIZE)) \\\n\t\t--root=$(1) \\\n\t\t--output=$@ \\\n\t\t--compression-mode=none\n\n\t$(call Build/pad-to,$(BLOCKSIZE))\nendef\n\ndefine Build/cfe-jffs2-cferam\n\tmv $@ $@.kernel\n\n\trm -rf $@-cferam\n\tmkdir -p $@-cferam\n\n\t# CFE ROM checks JFFS2 dirent version of cferam.\n\t# If version is not > 0 it will ignore the fs entry.\n\t# JFFS2 sets version 0 to the first fs entry and increments\n\t# it on the following ones, so let's create a dummy file that\n\t# will have version 0 and let cferam be the second (version 1).\n\ttouch $@-cferam/1-openwrt\n\t# Add cferam as the last file in the JFFS2 partition\n\tcp $(KDIR)/bcm63xx-cfe/$(CFE_RAM_FILE) $@-cferam/$(CFE_RAM_JFFS2_NAME)\n\n\t# The JFFS2 partition creation should result in the following\n\t# layout:\n\t# 1) 1-openwrt (version 0, ino 2)\n\t# 2) cferam.000 (version 1, ino 3)\n\t$(call Build/cfe-jffs2,$@-cferam)\n\n\t# Some devices need padding between CFE RAM and kernel\n\t$(if $(CFE_RAM_JFFS2_PAD),$(call Build/pad-to,$(CFE_RAM_JFFS2_PAD)))\n\n\t# Add CFE partition tag\n\t$(if $(CFE_PART_ID),$(call Build/cfe-part-tag))\n\n\t# Append kernel\n\tdd if=$@.kernel >> $@\n\trm -f $@.kernel\nendef\n\ndefine Build/cfe-jffs2-kernel\n\trm -rf $@-kernel\n\tmkdir -p $@-kernel\n\n\t# CFE RAM checks JFFS2 dirent version of vmlinux.\n\t# If version is not > 0 it will ignore the fs entry.\n\t# JFFS2 sets version 0 to the first fs entry and increments\n\t# it on the following ones, so let's create a dummy file that\n\t# will have version 0 and let cferam be the second (version 1).\n\ttouch $@-kernel/1-openwrt\n\t# vmlinux is located on a different JFFS2 partition, but CFE RAM\n\t# ignores it, so let's create another dummy file that will match\n\t# the JFFS2 ino of cferam entry on the first JFFS2 partition.\n\t# CFE RAM won't be able to find vmlinux if cferam has the same\n\t# ino as vmlinux.\n\ttouch $@-kernel/2-openwrt\n\t# Add vmlinux as the last file in the JFFS2 partition\n\t$(TOPDIR)/scripts/cfe-bin-header.py \\\n\t\t--input-file $@ \\\n\t\t--output-file $@-kernel/vmlinux.lz \\\n\t\t--load-addr $(if $(DEVICE_LOADADDR),$(DEVICE_LOADADDR),$(LOADER_ENTRY)) \\\n\t\t--entry-addr $(if $(DEVICE_LOADADDR),$(DEVICE_LOADADDR),$(LOADER_ENTRY))\n\n\t# The JFFS2 partition creation should result in the following\n\t# layout:\n\t# 1) 1-openwrt (version 0, ino 2)\n\t# 2) 2-openwrt (version 1, ino 3)\n\t# 3) vmlinux.lz (version 2, ino 4)\n\t$(call Build/cfe-jffs2,$@-kernel)\nendef\n\ndefine Build/cfe-part-tag\n\tmv $@ $@.part\n\n\t$(TOPDIR)/scripts/cfe-partition-tag.py \\\n\t\t--input-file $@.part \\\n\t\t--output-file $@ \\\n\t\t--flags $(CFE_PART_FLAGS) \\\n\t\t--id $(CFE_PART_ID) \\\n\t\t--name $(VERSION_CODE) \\\n\t\t--version $(DEVICE_NAME)\n\n\t$(call Build/pad-to,$(BLOCKSIZE))\n\n\tdd if=$@.part >> $@\nendef\n\ndefine Build/cfe-sercomm-crypto\n\t$(TOPDIR)/scripts/sercomm-crypto.py \\\n\t\t--input-file $@ \\\n\t\t--key-file $@.key \\\n\t\t--output-file $@.ser \\\n\t\t--version OpenWrt\n\t$(STAGING_DIR_HOST)/bin/openssl enc -md md5 -aes-256-cbc \\\n\t\t-in $@ -out $@.enc \\\n\t\t-K `cat $@.key` \\\n\t\t-iv 00000000000000000000000000000000\n\tdd if=$@.enc >> $@.ser\n\tmv $@.ser $@\n\trm -f $@.enc $@.key\nendef\n\ndefine Build/cfe-sercomm-load\n\t$(TOPDIR)/scripts/sercomm-payload.py \\\n\t\t--input-file $@ \\\n\t\t--output-file $@.new \\\n\t\t--pid \"$(SERCOMM_PID)\"\n\n\tmv $@.new $@\nendef\n\ndefine Build/cfe-sercomm-part\n\t$(TOPDIR)/scripts/sercomm-partition-tag.py \\\n\t\t--input-file $@ \\\n\t\t--output-file $@.kernel_rootfs \\\n\t\t--part-name kernel_rootfs \\\n\t\t--part-version OpenWrt \\\n\t\t--rootfs-version $(SERCOMM_VERSION)\n\n\trm -rf $@-rootfs_lib\n\tmkdir -p $@-rootfs_lib\n\techo $(SERCOMM_VERSION) > $@-rootfs_lib/lib_ver\n\t$(call Build/cfe-jffs2,$@-rootfs_lib)\n\t$(call Build/pad-to,$(BLOCKSIZE))\n\t$(TOPDIR)/scripts/sercomm-partition-tag.py \\\n\t\t--input-file $@ \\\n\t\t--output-file $@.rootfs_lib \\\n\t\t--part-name rootfs_lib \\\n\t\t--part-version $(SERCOMM_VERSION)\n\n\tmv $@.kernel_rootfs $@\n\tdd if=$@.rootfs_lib >> $@\nendef\n\ndefine Build/cfe-wfi-tag\n\t$(TOPDIR)/scripts/cfe-wfi-tag.py \\\n\t\t--input-file $@ \\\n\t\t--output-file $@.new \\\n\t\t--version $(if $(1),$(1),$(CFE_WFI_VERSION)) \\\n\t\t--chip-id $(CFE_WFI_CHIP_ID) \\\n\t\t--flash-type $(CFE_WFI_FLASH_TYPE) \\\n\t\t$(if $(CFE_WFI_FLAGS),--flags $(CFE_WFI_FLAGS))\n\tmv $@.new $@\nendef\n\n### Device scripts ###\ndefine Device/Default\n  PROFILES = Default $$(DEVICE_NAME)\n  KERNEL_DEPENDS = $$(wildcard ../dts/$$(DEVICE_DTS).dts)\n  DEVICE_DTS_DIR := ../dts\n  CHIP_ID :=\n  SOC = bcm$$(CHIP_ID)\n  DEVICE_DTS = $$(SOC)-$(subst _,-,$(1))\n  DEVICE_LOADADDR :=\nendef\n\nATH9K_PACKAGES := kmod-ath9k wpad-basic-wolfssl\nB43_PACKAGES := kmod-b43 wpad-basic-wolfssl\nUSB1_PACKAGES := kmod-usb-ohci kmod-ledtrig-usbdev\nUSB2_PACKAGES := $(USB1_PACKAGES) kmod-usb2\n\ninclude bcm63xx_$(SUBTARGET).mk\n\n$(eval $(call BuildImage))\n"
  },
  {
    "path": "target/linux/bmips/image/bcm63xx_generic.mk",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\nDEVICE_VARS += CFE_BOARD_ID CFE_EXTRAS\nDEVICE_VARS += FLASH_MB IMAGE_OFFSET\n\ndefine Device/bcm63xx-cfe\n  FILESYSTEMS := squashfs jffs2-64k jffs2-128k\n  KERNEL := kernel-bin | append-dtb | relocate-kernel | lzma\n  KERNEL_INITRAMFS := kernel-bin | append-dtb | lzma | loader-lzma elf\n  KERNEL_INITRAMFS_SUFFIX := .elf\n  IMAGES := cfe.bin sysupgrade.bin\n  IMAGE/cfe.bin := \\\n    cfe-bin $$$$(if $$$$(FLASH_MB),--pad $$$$(shell expr $$$$(FLASH_MB) / 2))\n  IMAGE/sysupgrade.bin := cfe-bin | append-metadata\n  BLOCKSIZE := 0x10000\n  IMAGE_OFFSET :=\n  FLASH_MB :=\n  CFE_BOARD_ID :=\n  CFE_EXTRAS = --block-size $$(BLOCKSIZE) \\\n    --image-offset $$(if $$(IMAGE_OFFSET),$$(IMAGE_OFFSET),$$(BLOCKSIZE))\nendef\n\n# Legacy CFEs with specific LZMA parameters and no length\ndefine Device/bcm63xx-cfe-legacy\n  $(Device/bcm63xx-cfe)\n  KERNEL := kernel-bin | append-dtb | relocate-kernel | lzma-cfe\nendef\n\ndefine Device/comtrend_ar-5315u\n  $(Device/bcm63xx-cfe)\n  DEVICE_VENDOR := Comtrend\n  DEVICE_MODEL := AR-5315u\n  CHIP_ID := 6318\n  CFE_BOARD_ID := 96318A-1441N1\n  FLASH_MB := 16\n  DEVICE_PACKAGES += $(USB2_PACKAGES) $(B43_PACKAGES)\nendef\nTARGET_DEVICES += comtrend_ar-5315u\n\ndefine Device/comtrend_ar-5387un\n  $(Device/bcm63xx-cfe)\n  DEVICE_VENDOR := Comtrend\n  DEVICE_MODEL := AR-5387un\n  CHIP_ID := 6328\n  CFE_BOARD_ID := 96328A-1441N1\n  FLASH_MB := 16\n  DEVICE_PACKAGES += $(USB2_PACKAGES) $(B43_PACKAGES)\nendef\nTARGET_DEVICES += comtrend_ar-5387un\n\ndefine Device/comtrend_vr-3025u\n  $(Device/bcm63xx-cfe)\n  DEVICE_VENDOR := Comtrend\n  DEVICE_MODEL := VR-3025u\n  CHIP_ID := 6368\n  CFE_BOARD_ID := 96368M-1541N\n  BLOCKSIZE := 0x20000\n  FLASH_MB := 32\n  DEVICE_PACKAGES += $(USB2_PACKAGES) $(B43_PACKAGES)\nendef\nTARGET_DEVICES += comtrend_vr-3025u\n\ndefine Device/huawei_hg556a-b\n  $(Device/bcm63xx-cfe-legacy)\n  DEVICE_VENDOR := Huawei\n  DEVICE_MODEL := EchoLife HG556a\n  DEVICE_VARIANT := B\n  CHIP_ID := 6358\n  CFE_BOARD_ID := HW556\n  CFE_EXTRAS += --rsa-signature \"EchoLife_HG556a\" --tag-version 8\n  BLOCKSIZE := 0x20000\n  DEVICE_PACKAGES += $(USB2_PACKAGES) $(ATH9K_PACKAGES)\nendef\nTARGET_DEVICES += huawei_hg556a-b\n"
  },
  {
    "path": "target/linux/bmips/image/bcm63xx_nand.mk",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\nDEVICE_VARS += CFE_PART_FLAGS CFE_PART_ID\nDEVICE_VARS += CFE_RAM_FILE\nDEVICE_VARS += CFE_RAM_JFFS2_NAME CFE_RAM_JFFS2_PAD\nDEVICE_VARS += CFE_WFI_CHIP_ID CFE_WFI_FLASH_TYPE\nDEVICE_VARS += CFE_WFI_FLAGS CFE_WFI_VERSION\nDEVICE_VARS += SERCOMM_PID SERCOMM_VERSION\n\n# CFE expects a single JFFS2 partition with cferam and kernel. However,\n# it's possible to fool CFE into properly loading both cferam and kernel\n# from two different JFFS2 partitions by adding dummy files (see\n# cfe-jffs2-cferam and cfe-jffs2-kernel).\n# Separate JFFS2 partitions allow upgrading openwrt without reflashing cferam\n# JFFS2 partition, which is much safer in case anything goes wrong.\ndefine Device/bcm63xx-nand\n  FILESYSTEMS := squashfs ubifs\n  KERNEL := kernel-bin | append-dtb | relocate-kernel | lzma | cfe-jffs2-kernel\n  KERNEL_INITRAMFS := kernel-bin | append-dtb | lzma | loader-lzma elf\n  KERNEL_INITRAMFS_SUFFIX := .elf\n  IMAGES := cfe.bin sysupgrade.bin\n  IMAGE/cfe.bin := append-kernel | pad-to $$$$(KERNEL_SIZE) |\\\n    cfe-jffs2-cferam | append-ubi | cfe-wfi-tag\n  IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata\n  KERNEL_SIZE := 5120k\n  CFE_PART_FLAGS :=\n  CFE_PART_ID :=\n  CFE_RAM_FILE :=\n  CFE_RAM_JFFS2_NAME :=\n  CFE_RAM_JFFS2_PAD :=\n  CFE_WFI_VERSION :=\n  CFE_WFI_CHIP_ID = 0x$$(CHIP_ID)\n  CFE_WFI_FLASH_TYPE :=\n  CFE_WFI_FLAGS :=\n  UBINIZE_OPTS := -E 5\n  DEVICE_PACKAGES += nand-utils\nendef\n\ndefine Device/sercomm-nand\n  $(Device/bcm63xx-nand)\n  IMAGES := factory.img sysupgrade.bin\n  IMAGE/factory.img := append-kernel | pad-to $$$$(KERNEL_SIZE) | append-ubi |\\\n    cfe-sercomm-part | gzip | cfe-sercomm-load | cfe-sercomm-crypto\n  SERCOM_PID :=\n  SERCOMM_VERSION :=\nendef\n\ndefine Device/comtrend_vr-3032u\n  $(Device/bcm63xx-nand)\n  DEVICE_VENDOR := Comtrend\n  DEVICE_MODEL := VR-3032u\n  CHIP_ID := 63268\n  SOC := bcm63168\n  CFE_RAM_FILE := comtrend,vr-3032u/cferam.000\n  CFE_RAM_JFFS2_NAME := cferam.000\n  BLOCKSIZE := 128k\n  PAGESIZE := 2048\n  SUBPAGESIZE := 512\n  VID_HDR_OFFSET := 2048\n  DEVICE_PACKAGES += $(USB2_PACKAGES)\n  CFE_WFI_FLASH_TYPE := 3\n  CFE_WFI_VERSION := 0x5732\nendef\nTARGET_DEVICES += comtrend_vr-3032u\n\ndefine Device/netgear_dgnd3700-v2\n  $(Device/bcm63xx-nand)\n  DEVICE_VENDOR := NETGEAR\n  DEVICE_MODEL := DGND3700\n  DEVICE_VARIANT := v2\n  CHIP_ID := 6362\n  CFE_RAM_FILE := netgear,dgnd3700-v2/cferam\n  CFE_RAM_JFFS2_NAME := cferam\n  CFE_RAM_JFFS2_PAD := 496k\n  BLOCKSIZE := 16k\n  PAGESIZE := 512\n  DEVICE_PACKAGES += $(USB2_PACKAGES) $(B43_PACKAGES)\n  CFE_WFI_FLASH_TYPE := 2\n  CFE_WFI_VERSION := 0x5731\nendef\nTARGET_DEVICES += netgear_dgnd3700-v2\n"
  },
  {
    "path": "target/linux/bmips/image/lzma-loader/Makefile",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Copyright (C) 2020 Álvaro Fernández Rojas <noltari@gmail.com>\n# Copyright (C) 2014 Jonas Gorski <jogo@openwrt.org>\n# Copyright (C) 2011 OpenWrt.org\n# Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>\n#\n\ninclude $(TOPDIR)/rules.mk\n\nLZMA_TEXT_START\t:= 0x80a00000\nLOADER\t\t:= loader.bin\nLOADER_NAME\t:= $(basename $(notdir $(LOADER)))\nLOADER_DATA \t:=\nTARGET_DIR\t:=\n\nUART_BASE_3329 := 0xb0000100\nUART_BASE_3368 := 0xfff8c100\nUART_BASE_3380 := 0xb4e00200\nUART_BASE_3383 := 0xb4e00500\nUART_BASE_3384 := 0xb4e00500\nUART_BASE_6318 := 0xb0000100\nUART_BASE_6328 := 0xb0000100\nUART_BASE_6338 := 0xfffe0300\nUART_BASE_6345 := 0xfffe0300\nUART_BASE_6348 := 0xfffe0300\nUART_BASE_6358 := 0xfffe0100\nUART_BASE_6362 := 0xb0000100\nUART_BASE_6368 := 0xb0000100\nUART_BASE_63268 := 0xb0000180\nUART_BASE_6816 := 0xb0000100\nUART_BASE_6818 := 0xb0000100\nUART_BASE_6828 := 0xb0000180\nUART_BASE := $(if $(UART_BASE_$(CHIP_ID)),$(UART_BASE_$(CHIP_ID)),0)\n\nifeq ($(TARGET_DIR),)\nTARGET_DIR\t:= $(KDIR)\nendif\n\nLOADER_BIN\t:= $(TARGET_DIR)/$(LOADER_NAME).bin\nLOADER_ELF\t:= $(TARGET_DIR)/$(LOADER_NAME).elf\n\nPKG_NAME := lzma-loader\nPKG_BUILD_DIR := $(KDIR)/$(PKG_NAME)\n\n.PHONY : loader-compile loader.bin loader.elf\n\n$(PKG_BUILD_DIR)/.prepared:\n\tmkdir $(PKG_BUILD_DIR)\n\t$(CP) ./src/* $(PKG_BUILD_DIR)/\n\ttouch $@\n\nloader-compile: $(PKG_BUILD_DIR)/.prepared\n\t$(MAKE) -C $(PKG_BUILD_DIR) CROSS_COMPILE=\"$(TARGET_CROSS)\" \\\n\t\tLZMA_TEXT_START=$(LZMA_TEXT_START) \\\n\t\tLOADER_DATA=$(LOADER_DATA) \\\n\t\tUART_BASE=$(UART_BASE) \\\n\t\tclean all\n\nloader.elf: $(PKG_BUILD_DIR)/loader.elf\n\t$(CP) $< $(LOADER_ELF)\n\nloader.bin: $(PKG_BUILD_DIR)/loader.bin\n\t$(CP) $< $(LOADER_BIN)\n\ndownload:\nprepare: $(PKG_BUILD_DIR)/.prepared\ncompile: loader-compile\n\ninstall:\n\nclean:\n\trm -rf $(PKG_BUILD_DIR)\n"
  },
  {
    "path": "target/linux/bmips/image/lzma-loader/src/LzmaDecode.c",
    "content": "/*\n  LzmaDecode.c\n  LZMA Decoder (optimized for Speed version)\n  \n  LZMA SDK 4.40 Copyright (c) 1999-2006 Igor Pavlov (2006-05-01)\n  http://www.7-zip.org/\n\n  LZMA SDK is licensed under two licenses:\n  1) GNU Lesser General Public License (GNU LGPL)\n  2) Common Public License (CPL)\n  It means that you can select one of these two licenses and \n  follow rules of that license.\n\n  SPECIAL EXCEPTION:\n  Igor Pavlov, as the author of this Code, expressly permits you to \n  statically or dynamically link your Code (or bind by name) to the \n  interfaces of this file without subjecting your linked Code to the \n  terms of the CPL or GNU LGPL. Any modifications or additions \n  to this file, however, are subject to the LGPL or CPL terms.\n*/\n\n#include \"LzmaDecode.h\"\n\n#define kNumTopBits 24\n#define kTopValue ((UInt32)1 << kNumTopBits)\n\n#define kNumBitModelTotalBits 11\n#define kBitModelTotal (1 << kNumBitModelTotalBits)\n#define kNumMoveBits 5\n\n#define RC_READ_BYTE (*Buffer++)\n\n#define RC_INIT2 Code = 0; Range = 0xFFFFFFFF; \\\n  { int i; for(i = 0; i < 5; i++) { RC_TEST; Code = (Code << 8) | RC_READ_BYTE; }}\n\n#ifdef _LZMA_IN_CB\n\n#define RC_TEST { if (Buffer == BufferLim) \\\n  { SizeT size; int result = InCallback->Read(InCallback, &Buffer, &size); if (result != LZMA_RESULT_OK) return result; \\\n  BufferLim = Buffer + size; if (size == 0) return LZMA_RESULT_DATA_ERROR; }}\n\n#define RC_INIT Buffer = BufferLim = 0; RC_INIT2\n\n#else\n\n#define RC_TEST { if (Buffer == BufferLim) return LZMA_RESULT_DATA_ERROR; }\n\n#define RC_INIT(buffer, bufferSize) Buffer = buffer; BufferLim = buffer + bufferSize; RC_INIT2\n \n#endif\n\n#define RC_NORMALIZE if (Range < kTopValue) { RC_TEST; Range <<= 8; Code = (Code << 8) | RC_READ_BYTE; }\n\n#define IfBit0(p) RC_NORMALIZE; bound = (Range >> kNumBitModelTotalBits) * *(p); if (Code < bound)\n#define UpdateBit0(p) Range = bound; *(p) += (kBitModelTotal - *(p)) >> kNumMoveBits;\n#define UpdateBit1(p) Range -= bound; Code -= bound; *(p) -= (*(p)) >> kNumMoveBits;\n\n#define RC_GET_BIT2(p, mi, A0, A1) IfBit0(p) \\\n  { UpdateBit0(p); mi <<= 1; A0; } else \\\n  { UpdateBit1(p); mi = (mi + mi) + 1; A1; } \n  \n#define RC_GET_BIT(p, mi) RC_GET_BIT2(p, mi, ; , ;)               \n\n#define RangeDecoderBitTreeDecode(probs, numLevels, res) \\\n  { int i = numLevels; res = 1; \\\n  do { CProb *p = probs + res; RC_GET_BIT(p, res) } while(--i != 0); \\\n  res -= (1 << numLevels); }\n\n\n#define kNumPosBitsMax 4\n#define kNumPosStatesMax (1 << kNumPosBitsMax)\n\n#define kLenNumLowBits 3\n#define kLenNumLowSymbols (1 << kLenNumLowBits)\n#define kLenNumMidBits 3\n#define kLenNumMidSymbols (1 << kLenNumMidBits)\n#define kLenNumHighBits 8\n#define kLenNumHighSymbols (1 << kLenNumHighBits)\n\n#define LenChoice 0\n#define LenChoice2 (LenChoice + 1)\n#define LenLow (LenChoice2 + 1)\n#define LenMid (LenLow + (kNumPosStatesMax << kLenNumLowBits))\n#define LenHigh (LenMid + (kNumPosStatesMax << kLenNumMidBits))\n#define kNumLenProbs (LenHigh + kLenNumHighSymbols) \n\n\n#define kNumStates 12\n#define kNumLitStates 7\n\n#define kStartPosModelIndex 4\n#define kEndPosModelIndex 14\n#define kNumFullDistances (1 << (kEndPosModelIndex >> 1))\n\n#define kNumPosSlotBits 6\n#define kNumLenToPosStates 4\n\n#define kNumAlignBits 4\n#define kAlignTableSize (1 << kNumAlignBits)\n\n#define kMatchMinLen 2\n\n#define IsMatch 0\n#define IsRep (IsMatch + (kNumStates << kNumPosBitsMax))\n#define IsRepG0 (IsRep + kNumStates)\n#define IsRepG1 (IsRepG0 + kNumStates)\n#define IsRepG2 (IsRepG1 + kNumStates)\n#define IsRep0Long (IsRepG2 + kNumStates)\n#define PosSlot (IsRep0Long + (kNumStates << kNumPosBitsMax))\n#define SpecPos (PosSlot + (kNumLenToPosStates << kNumPosSlotBits))\n#define Align (SpecPos + kNumFullDistances - kEndPosModelIndex)\n#define LenCoder (Align + kAlignTableSize)\n#define RepLenCoder (LenCoder + kNumLenProbs)\n#define Literal (RepLenCoder + kNumLenProbs)\n\n#if Literal != LZMA_BASE_SIZE\nStopCompilingDueBUG\n#endif\n\nint LzmaDecodeProperties(CLzmaProperties *propsRes, const unsigned char *propsData, int size)\n{\n  unsigned char prop0;\n  if (size < LZMA_PROPERTIES_SIZE)\n    return LZMA_RESULT_DATA_ERROR;\n  prop0 = propsData[0];\n  if (prop0 >= (9 * 5 * 5))\n    return LZMA_RESULT_DATA_ERROR;\n  {\n    for (propsRes->pb = 0; prop0 >= (9 * 5); propsRes->pb++, prop0 -= (9 * 5));\n    for (propsRes->lp = 0; prop0 >= 9; propsRes->lp++, prop0 -= 9);\n    propsRes->lc = prop0;\n    /*\n    unsigned char remainder = (unsigned char)(prop0 / 9);\n    propsRes->lc = prop0 % 9;\n    propsRes->pb = remainder / 5;\n    propsRes->lp = remainder % 5;\n    */\n  }\n\n  #ifdef _LZMA_OUT_READ\n  {\n    int i;\n    propsRes->DictionarySize = 0;\n    for (i = 0; i < 4; i++)\n      propsRes->DictionarySize += (UInt32)(propsData[1 + i]) << (i * 8);\n    if (propsRes->DictionarySize == 0)\n      propsRes->DictionarySize = 1;\n  }\n  #endif\n  return LZMA_RESULT_OK;\n}\n\n#define kLzmaStreamWasFinishedId (-1)\n\nint LzmaDecode(CLzmaDecoderState *vs,\n    #ifdef _LZMA_IN_CB\n    ILzmaInCallback *InCallback,\n    #else\n    const unsigned char *inStream, SizeT inSize, SizeT *inSizeProcessed,\n    #endif\n    unsigned char *outStream, SizeT outSize, SizeT *outSizeProcessed)\n{\n  CProb *p = vs->Probs;\n  SizeT nowPos = 0;\n  Byte previousByte = 0;\n  UInt32 posStateMask = (1 << (vs->Properties.pb)) - 1;\n  UInt32 literalPosMask = (1 << (vs->Properties.lp)) - 1;\n  int lc = vs->Properties.lc;\n\n  #ifdef _LZMA_OUT_READ\n  \n  UInt32 Range = vs->Range;\n  UInt32 Code = vs->Code;\n  #ifdef _LZMA_IN_CB\n  const Byte *Buffer = vs->Buffer;\n  const Byte *BufferLim = vs->BufferLim;\n  #else\n  const Byte *Buffer = inStream;\n  const Byte *BufferLim = inStream + inSize;\n  #endif\n  int state = vs->State;\n  UInt32 rep0 = vs->Reps[0], rep1 = vs->Reps[1], rep2 = vs->Reps[2], rep3 = vs->Reps[3];\n  int len = vs->RemainLen;\n  UInt32 globalPos = vs->GlobalPos;\n  UInt32 distanceLimit = vs->DistanceLimit;\n\n  Byte *dictionary = vs->Dictionary;\n  UInt32 dictionarySize = vs->Properties.DictionarySize;\n  UInt32 dictionaryPos = vs->DictionaryPos;\n\n  Byte tempDictionary[4];\n\n  #ifndef _LZMA_IN_CB\n  *inSizeProcessed = 0;\n  #endif\n  *outSizeProcessed = 0;\n  if (len == kLzmaStreamWasFinishedId)\n    return LZMA_RESULT_OK;\n\n  if (dictionarySize == 0)\n  {\n    dictionary = tempDictionary;\n    dictionarySize = 1;\n    tempDictionary[0] = vs->TempDictionary[0];\n  }\n\n  if (len == kLzmaNeedInitId)\n  {\n    {\n      UInt32 numProbs = Literal + ((UInt32)LZMA_LIT_SIZE << (lc + vs->Properties.lp));\n      UInt32 i;\n      for (i = 0; i < numProbs; i++)\n        p[i] = kBitModelTotal >> 1; \n      rep0 = rep1 = rep2 = rep3 = 1;\n      state = 0;\n      globalPos = 0;\n      distanceLimit = 0;\n      dictionaryPos = 0;\n      dictionary[dictionarySize - 1] = 0;\n      #ifdef _LZMA_IN_CB\n      RC_INIT;\n      #else\n      RC_INIT(inStream, inSize);\n      #endif\n    }\n    len = 0;\n  }\n  while(len != 0 && nowPos < outSize)\n  {\n    UInt32 pos = dictionaryPos - rep0;\n    if (pos >= dictionarySize)\n      pos += dictionarySize;\n    outStream[nowPos++] = dictionary[dictionaryPos] = dictionary[pos];\n    if (++dictionaryPos == dictionarySize)\n      dictionaryPos = 0;\n    len--;\n  }\n  if (dictionaryPos == 0)\n    previousByte = dictionary[dictionarySize - 1];\n  else\n    previousByte = dictionary[dictionaryPos - 1];\n\n  #else /* if !_LZMA_OUT_READ */\n\n  int state = 0;\n  UInt32 rep0 = 1, rep1 = 1, rep2 = 1, rep3 = 1;\n  int len = 0;\n  const Byte *Buffer;\n  const Byte *BufferLim;\n  UInt32 Range;\n  UInt32 Code;\n\n  #ifndef _LZMA_IN_CB\n  *inSizeProcessed = 0;\n  #endif\n  *outSizeProcessed = 0;\n\n  {\n    UInt32 i;\n    UInt32 numProbs = Literal + ((UInt32)LZMA_LIT_SIZE << (lc + vs->Properties.lp));\n    for (i = 0; i < numProbs; i++)\n      p[i] = kBitModelTotal >> 1;\n  }\n  \n  #ifdef _LZMA_IN_CB\n  RC_INIT;\n  #else\n  RC_INIT(inStream, inSize);\n  #endif\n\n  #endif /* _LZMA_OUT_READ */\n\n  while(nowPos < outSize)\n  {\n    CProb *prob;\n    UInt32 bound;\n    int posState = (int)(\n        (nowPos \n        #ifdef _LZMA_OUT_READ\n        + globalPos\n        #endif\n        )\n        & posStateMask);\n\n    prob = p + IsMatch + (state << kNumPosBitsMax) + posState;\n    IfBit0(prob)\n    {\n      int symbol = 1;\n      UpdateBit0(prob)\n      prob = p + Literal + (LZMA_LIT_SIZE * \n        (((\n        (nowPos \n        #ifdef _LZMA_OUT_READ\n        + globalPos\n        #endif\n        )\n        & literalPosMask) << lc) + (previousByte >> (8 - lc))));\n\n      if (state >= kNumLitStates)\n      {\n        int matchByte;\n        #ifdef _LZMA_OUT_READ\n        UInt32 pos = dictionaryPos - rep0;\n        if (pos >= dictionarySize)\n          pos += dictionarySize;\n        matchByte = dictionary[pos];\n        #else\n        matchByte = outStream[nowPos - rep0];\n        #endif\n        do\n        {\n          int bit;\n          CProb *probLit;\n          matchByte <<= 1;\n          bit = (matchByte & 0x100);\n          probLit = prob + 0x100 + bit + symbol;\n          RC_GET_BIT2(probLit, symbol, if (bit != 0) break, if (bit == 0) break)\n        }\n        while (symbol < 0x100);\n      }\n      while (symbol < 0x100)\n      {\n        CProb *probLit = prob + symbol;\n        RC_GET_BIT(probLit, symbol)\n      }\n      previousByte = (Byte)symbol;\n\n      outStream[nowPos++] = previousByte;\n      #ifdef _LZMA_OUT_READ\n      if (distanceLimit < dictionarySize)\n        distanceLimit++;\n\n      dictionary[dictionaryPos] = previousByte;\n      if (++dictionaryPos == dictionarySize)\n        dictionaryPos = 0;\n      #endif\n      if (state < 4) state = 0;\n      else if (state < 10) state -= 3;\n      else state -= 6;\n    }\n    else             \n    {\n      UpdateBit1(prob);\n      prob = p + IsRep + state;\n      IfBit0(prob)\n      {\n        UpdateBit0(prob);\n        rep3 = rep2;\n        rep2 = rep1;\n        rep1 = rep0;\n        state = state < kNumLitStates ? 0 : 3;\n        prob = p + LenCoder;\n      }\n      else\n      {\n        UpdateBit1(prob);\n        prob = p + IsRepG0 + state;\n        IfBit0(prob)\n        {\n          UpdateBit0(prob);\n          prob = p + IsRep0Long + (state << kNumPosBitsMax) + posState;\n          IfBit0(prob)\n          {\n            #ifdef _LZMA_OUT_READ\n            UInt32 pos;\n            #endif\n            UpdateBit0(prob);\n            \n            #ifdef _LZMA_OUT_READ\n            if (distanceLimit == 0)\n            #else\n            if (nowPos == 0)\n            #endif\n              return LZMA_RESULT_DATA_ERROR;\n            \n            state = state < kNumLitStates ? 9 : 11;\n            #ifdef _LZMA_OUT_READ\n            pos = dictionaryPos - rep0;\n            if (pos >= dictionarySize)\n              pos += dictionarySize;\n            previousByte = dictionary[pos];\n            dictionary[dictionaryPos] = previousByte;\n            if (++dictionaryPos == dictionarySize)\n              dictionaryPos = 0;\n            #else\n            previousByte = outStream[nowPos - rep0];\n            #endif\n            outStream[nowPos++] = previousByte;\n            #ifdef _LZMA_OUT_READ\n            if (distanceLimit < dictionarySize)\n              distanceLimit++;\n            #endif\n\n            continue;\n          }\n          else\n          {\n            UpdateBit1(prob);\n          }\n        }\n        else\n        {\n          UInt32 distance;\n          UpdateBit1(prob);\n          prob = p + IsRepG1 + state;\n          IfBit0(prob)\n          {\n            UpdateBit0(prob);\n            distance = rep1;\n          }\n          else \n          {\n            UpdateBit1(prob);\n            prob = p + IsRepG2 + state;\n            IfBit0(prob)\n            {\n              UpdateBit0(prob);\n              distance = rep2;\n            }\n            else\n            {\n              UpdateBit1(prob);\n              distance = rep3;\n              rep3 = rep2;\n            }\n            rep2 = rep1;\n          }\n          rep1 = rep0;\n          rep0 = distance;\n        }\n        state = state < kNumLitStates ? 8 : 11;\n        prob = p + RepLenCoder;\n      }\n      {\n        int numBits, offset;\n        CProb *probLen = prob + LenChoice;\n        IfBit0(probLen)\n        {\n          UpdateBit0(probLen);\n          probLen = prob + LenLow + (posState << kLenNumLowBits);\n          offset = 0;\n          numBits = kLenNumLowBits;\n        }\n        else\n        {\n          UpdateBit1(probLen);\n          probLen = prob + LenChoice2;\n          IfBit0(probLen)\n          {\n            UpdateBit0(probLen);\n            probLen = prob + LenMid + (posState << kLenNumMidBits);\n            offset = kLenNumLowSymbols;\n            numBits = kLenNumMidBits;\n          }\n          else\n          {\n            UpdateBit1(probLen);\n            probLen = prob + LenHigh;\n            offset = kLenNumLowSymbols + kLenNumMidSymbols;\n            numBits = kLenNumHighBits;\n          }\n        }\n        RangeDecoderBitTreeDecode(probLen, numBits, len);\n        len += offset;\n      }\n\n      if (state < 4)\n      {\n        int posSlot;\n        state += kNumLitStates;\n        prob = p + PosSlot +\n            ((len < kNumLenToPosStates ? len : kNumLenToPosStates - 1) << \n            kNumPosSlotBits);\n        RangeDecoderBitTreeDecode(prob, kNumPosSlotBits, posSlot);\n        if (posSlot >= kStartPosModelIndex)\n        {\n          int numDirectBits = ((posSlot >> 1) - 1);\n          rep0 = (2 | ((UInt32)posSlot & 1));\n          if (posSlot < kEndPosModelIndex)\n          {\n            rep0 <<= numDirectBits;\n            prob = p + SpecPos + rep0 - posSlot - 1;\n          }\n          else\n          {\n            numDirectBits -= kNumAlignBits;\n            do\n            {\n              RC_NORMALIZE\n              Range >>= 1;\n              rep0 <<= 1;\n              if (Code >= Range)\n              {\n                Code -= Range;\n                rep0 |= 1;\n              }\n            }\n            while (--numDirectBits != 0);\n            prob = p + Align;\n            rep0 <<= kNumAlignBits;\n            numDirectBits = kNumAlignBits;\n          }\n          {\n            int i = 1;\n            int mi = 1;\n            do\n            {\n              CProb *prob3 = prob + mi;\n              RC_GET_BIT2(prob3, mi, ; , rep0 |= i);\n              i <<= 1;\n            }\n            while(--numDirectBits != 0);\n          }\n        }\n        else\n          rep0 = posSlot;\n        if (++rep0 == (UInt32)(0))\n        {\n          /* it's for stream version */\n          len = kLzmaStreamWasFinishedId;\n          break;\n        }\n      }\n\n      len += kMatchMinLen;\n      #ifdef _LZMA_OUT_READ\n      if (rep0 > distanceLimit) \n      #else\n      if (rep0 > nowPos)\n      #endif\n        return LZMA_RESULT_DATA_ERROR;\n\n      #ifdef _LZMA_OUT_READ\n      if (dictionarySize - distanceLimit > (UInt32)len)\n        distanceLimit += len;\n      else\n        distanceLimit = dictionarySize;\n      #endif\n\n      do\n      {\n        #ifdef _LZMA_OUT_READ\n        UInt32 pos = dictionaryPos - rep0;\n        if (pos >= dictionarySize)\n          pos += dictionarySize;\n        previousByte = dictionary[pos];\n        dictionary[dictionaryPos] = previousByte;\n        if (++dictionaryPos == dictionarySize)\n          dictionaryPos = 0;\n        #else\n        previousByte = outStream[nowPos - rep0];\n        #endif\n        len--;\n        outStream[nowPos++] = previousByte;\n      }\n      while(len != 0 && nowPos < outSize);\n    }\n  }\n  RC_NORMALIZE;\n\n  #ifdef _LZMA_OUT_READ\n  vs->Range = Range;\n  vs->Code = Code;\n  vs->DictionaryPos = dictionaryPos;\n  vs->GlobalPos = globalPos + (UInt32)nowPos;\n  vs->DistanceLimit = distanceLimit;\n  vs->Reps[0] = rep0;\n  vs->Reps[1] = rep1;\n  vs->Reps[2] = rep2;\n  vs->Reps[3] = rep3;\n  vs->State = state;\n  vs->RemainLen = len;\n  vs->TempDictionary[0] = tempDictionary[0];\n  #endif\n\n  #ifdef _LZMA_IN_CB\n  vs->Buffer = Buffer;\n  vs->BufferLim = BufferLim;\n  #else\n  *inSizeProcessed = (SizeT)(Buffer - inStream);\n  #endif\n  *outSizeProcessed = nowPos;\n  return LZMA_RESULT_OK;\n}\n"
  },
  {
    "path": "target/linux/bmips/image/lzma-loader/src/LzmaDecode.h",
    "content": "/* \n  LzmaDecode.h\n  LZMA Decoder interface\n\n  LZMA SDK 4.40 Copyright (c) 1999-2006 Igor Pavlov (2006-05-01)\n  http://www.7-zip.org/\n\n  LZMA SDK is licensed under two licenses:\n  1) GNU Lesser General Public License (GNU LGPL)\n  2) Common Public License (CPL)\n  It means that you can select one of these two licenses and \n  follow rules of that license.\n\n  SPECIAL EXCEPTION:\n  Igor Pavlov, as the author of this code, expressly permits you to \n  statically or dynamically link your code (or bind by name) to the \n  interfaces of this file without subjecting your linked code to the \n  terms of the CPL or GNU LGPL. Any modifications or additions \n  to this file, however, are subject to the LGPL or CPL terms.\n*/\n\n#ifndef __LZMADECODE_H\n#define __LZMADECODE_H\n\n#include \"LzmaTypes.h\"\n\n/* #define _LZMA_IN_CB */\n/* Use callback for input data */\n\n/* #define _LZMA_OUT_READ */\n/* Use read function for output data */\n\n/* #define _LZMA_PROB32 */\n/* It can increase speed on some 32-bit CPUs, \n   but memory usage will be doubled in that case */\n\n/* #define _LZMA_LOC_OPT */\n/* Enable local speed optimizations inside code */\n\n#ifdef _LZMA_PROB32\n#define CProb UInt32\n#else\n#define CProb UInt16\n#endif\n\n#define LZMA_RESULT_OK 0\n#define LZMA_RESULT_DATA_ERROR 1\n\n#ifdef _LZMA_IN_CB\ntypedef struct _ILzmaInCallback\n{\n  int (*Read)(void *object, const unsigned char **buffer, SizeT *bufferSize);\n} ILzmaInCallback;\n#endif\n\n#define LZMA_BASE_SIZE 1846\n#define LZMA_LIT_SIZE 768\n\n#define LZMA_PROPERTIES_SIZE 5\n\ntypedef struct _CLzmaProperties\n{\n  int lc;\n  int lp;\n  int pb;\n  #ifdef _LZMA_OUT_READ\n  UInt32 DictionarySize;\n  #endif\n}CLzmaProperties;\n\nint LzmaDecodeProperties(CLzmaProperties *propsRes, const unsigned char *propsData, int size);\n\n#define LzmaGetNumProbs(Properties) (LZMA_BASE_SIZE + (LZMA_LIT_SIZE << ((Properties)->lc + (Properties)->lp)))\n\n#define kLzmaNeedInitId (-2)\n\ntypedef struct _CLzmaDecoderState\n{\n  CLzmaProperties Properties;\n  CProb *Probs;\n\n  #ifdef _LZMA_IN_CB\n  const unsigned char *Buffer;\n  const unsigned char *BufferLim;\n  #endif\n\n  #ifdef _LZMA_OUT_READ\n  unsigned char *Dictionary;\n  UInt32 Range;\n  UInt32 Code;\n  UInt32 DictionaryPos;\n  UInt32 GlobalPos;\n  UInt32 DistanceLimit;\n  UInt32 Reps[4];\n  int State;\n  int RemainLen;\n  unsigned char TempDictionary[4];\n  #endif\n} CLzmaDecoderState;\n\n#ifdef _LZMA_OUT_READ\n#define LzmaDecoderInit(vs) { (vs)->RemainLen = kLzmaNeedInitId; }\n#endif\n\nint LzmaDecode(CLzmaDecoderState *vs,\n    #ifdef _LZMA_IN_CB\n    ILzmaInCallback *inCallback,\n    #else\n    const unsigned char *inStream, SizeT inSize, SizeT *inSizeProcessed,\n    #endif\n    unsigned char *outStream, SizeT outSize, SizeT *outSizeProcessed);\n\n#endif\n"
  },
  {
    "path": "target/linux/bmips/image/lzma-loader/src/LzmaTypes.h",
    "content": "/* \nLzmaTypes.h \n\nTypes for LZMA Decoder\n\nThis file written and distributed to public domain by Igor Pavlov.\nThis file is part of LZMA SDK 4.40 (2006-05-01)\n*/\n\n#ifndef __LZMATYPES_H\n#define __LZMATYPES_H\n\n#ifndef _7ZIP_BYTE_DEFINED\n#define _7ZIP_BYTE_DEFINED\ntypedef unsigned char Byte;\n#endif \n\n#ifndef _7ZIP_UINT16_DEFINED\n#define _7ZIP_UINT16_DEFINED\ntypedef unsigned short UInt16;\n#endif \n\n#ifndef _7ZIP_UINT32_DEFINED\n#define _7ZIP_UINT32_DEFINED\n#ifdef _LZMA_UINT32_IS_ULONG\ntypedef unsigned long UInt32;\n#else\ntypedef unsigned int UInt32;\n#endif\n#endif \n\n/* #define _LZMA_NO_SYSTEM_SIZE_T */\n/* You can use it, if you don't want <stddef.h> */\n\n#ifndef _7ZIP_SIZET_DEFINED\n#define _7ZIP_SIZET_DEFINED\n#ifdef _LZMA_NO_SYSTEM_SIZE_T\ntypedef UInt32 SizeT;\n#else\n#include <stddef.h>\ntypedef size_t SizeT;\n#endif\n#endif\n\n#endif\n"
  },
  {
    "path": "target/linux/bmips/image/lzma-loader/src/Makefile",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n#\n# Makefile for the LZMA compressed kernel loader for BMIPS based boards\n#\n# Copyright (C) 2020 Álvaro Fernández Rojas <noltari@gmail.com>\n# Copyright (C) 2014 Jonas Gorski <jogo@openwrt.org>\n# Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>\n#\n# Some parts of this file was based on the OpenWrt specific lzma-loader\n# for the BCM47xx and ADM5120 based boards:\n#\tCopyright (C) 2004 Manuel Novoa III (mjn3@codepoet.org)\n#\tCopyright (C) 2005 Mineharu Takahara <mtakahar@yahoo.com>\n#\tCopyright (C) 2005 by Oleg I. Vdovikin <oleg@cs.msu.su>\n#\n\nLOADER_ADDR\t:=\nKERNEL_ADDR\t:=\nLZMA_TEXT_START\t:= 0x80a00000\nLOADER_DATA\t:=\n\nCC\t\t:= $(CROSS_COMPILE)gcc\nLD\t\t:= $(CROSS_COMPILE)ld\nOBJCOPY\t\t:= $(CROSS_COMPILE)objcopy\nOBJDUMP\t\t:= $(CROSS_COMPILE)objdump\n\nBIN_FLAGS\t:= -O binary -R .reginfo -R .note -R .comment -R .mdebug \\\n\t\t   -R .MIPS.abiflags -S\n\nCFLAGS\t\t= -D__KERNEL__ -Wall -Wstrict-prototypes -Wno-trigraphs -Os \\\n\t\t  -fno-strict-aliasing -fno-common -fomit-frame-pointer -G 0 \\\n\t\t  -mno-abicalls -fno-pic -ffunction-sections -pipe \\\n\t\t  -ffreestanding -fhonour-copts \\\n\t\t  -mabi=32 -march=mips32 \\\n\t\t  -Wa,-32 -Wa,-march=mips32 -Wa,-mips32 -Wa,--trap\nCFLAGS\t\t+= -D_LZMA_PROB32\nCFLAGS\t\t+= -DUART_BASE=$(UART_BASE)\n\nASFLAGS\t\t= $(CFLAGS) -D__ASSEMBLY__\n\nLDFLAGS\t\t= -static --gc-sections -no-warn-mismatch\nLDFLAGS\t\t+= -e startup -T loader.lds -Ttext $(LZMA_TEXT_START)\n\nO_FORMAT \t= $(shell $(OBJDUMP) -i | head -2 | grep elf32)\n\nOBJECTS\t\t:= head.o loader.o cache.o board.o printf.o LzmaDecode.o\n\nifneq ($(strip $(LOADER_DATA)),)\nOBJECTS\t\t+= data.o\nCFLAGS\t\t+= -DLZMA_WRAPPER=1 -DLOADADDR=$(KERNEL_ADDR)\nendif\n\n\nall: loader.elf\n\n# Don't build dependencies, this may die if $(CC) isn't gcc\ndep:\n\ninstall:\n\n%.o : %.c\n\t$(CC) $(CFLAGS) -c -o $@ $<\n\n%.o : %.S\n\t$(CC) $(ASFLAGS) -c -o $@ $<\n\ndata.o: $(LOADER_DATA)\n\t$(LD) -r -b binary --oformat $(O_FORMAT) -T lzma-data.lds -o $@ $<\n\nloader: $(OBJECTS)\n\t$(LD) $(LDFLAGS) -o $@ $(OBJECTS)\n\nloader.bin: loader\n\t$(OBJCOPY) $(BIN_FLAGS) $< $@\n\nloader2.o: loader.bin\n\t$(LD) -r -b binary --oformat $(O_FORMAT) -o $@ $<\n\nloader.elf: loader2.o\n\t$(LD) -e startup -T loader2.lds -Ttext $(LOADER_ADDR) -o $@ $<\n\nmrproper: clean\n\nclean:\n\trm -f loader *.elf *.bin *.o\n"
  },
  {
    "path": "target/linux/bmips/image/lzma-loader/src/board.c",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later\n/*\n * BCM63XX specific implementation parts\n *\n * Copyright (C) 2020 Álvaro Fernández Rojas <noltari@gmail.com>\n * Copyright (C) 2014 Jonas Gorski <jogo@openwrt.org>\n */\n\n#include <stddef.h>\n#include \"config.h\"\n\n#define READREG(r)\t*(volatile unsigned int *)(r)\n#define WRITEREG(r,v)\t*(volatile unsigned int *)(r) = v\n\n#define UART_IR_REG\t0x10\n#define UART_FIFO_REG\t0x14\n\nstatic void wait_xfered(void)\n{\n        unsigned int val;\n\n        do {\n                val = READREG(UART_BASE + UART_IR_REG);\n                if (val & (1 << 5))\n                        break;\n        } while (1);\n}\n\nvoid board_putc(int ch)\n{\n\tif (!UART_BASE)\n\t\treturn;\n\n\twait_xfered();\n\tWRITEREG(UART_BASE + UART_FIFO_REG, ch);\n\twait_xfered();\n}\n"
  },
  {
    "path": "target/linux/bmips/image/lzma-loader/src/cache.c",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later\n/*\n * LZMA compressed kernel loader for Atheros AR7XXX/AR9XXX based boards\n *\n * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>\n *\n * The cache manipulation routine has been taken from the U-Boot project.\n *\t(C) Copyright 2003\n *\tWolfgang Denk, DENX Software Engineering, <wd@denx.de>\n */\n\n#include \"cache.h\"\n#include \"cacheops.h\"\n#include \"config.h\"\n#include \"printf.h\"\n\n#define cache_op(op,addr)\t\t\t\t\t\t\\\n\t__asm__ __volatile__(\t\t\t\t\t\t\\\n\t\"\t.set\tpush\t\t\t\t\t\\n\"\t\\\n\t\"\t.set\tnoreorder\t\t\t\t\\n\"\t\\\n\t\"\t.set\tmips3\\n\\t\t\t\t\t\\n\"\t\\\n\t\"\tcache\t%0, %1\t\t\t\t\t\\n\"\t\\\n\t\"\t.set\tpop\t\t\t\t\t\\n\"\t\\\n\t:\t\t\t\t\t\t\t\t\\\n\t: \"i\" (op), \"R\" (*(unsigned char *)(addr)))\n\nvoid flush_cache(unsigned long start_addr, unsigned long size)\n{\n\tunsigned long lsize = CONFIG_CACHELINE_SIZE;\n\tunsigned long addr = start_addr & ~(lsize - 1);\n\tunsigned long aend = (start_addr + size + (lsize - 1)) & ~(lsize - 1);\n\n\tprintf(\"blasting from 0x%08x to 0x%08x (0x%08x - 0x%08x)\\n\", start_addr, size, addr, aend);\n\n\twhile (1) {\n\t\tcache_op(Hit_Writeback_Inv_D, addr);\n\t\tcache_op(Hit_Invalidate_I, addr);\n\t\tif (addr == aend)\n\t\t\tbreak;\n\t\taddr += lsize;\n\t}\n}\n"
  },
  {
    "path": "target/linux/bmips/image/lzma-loader/src/cache.h",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later\n/*\n * LZMA compressed kernel loader for Atheros AR7XXX/AR9XXX based boards\n *\n * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>\n */\n\n#ifndef __CACHE_H\n#define __CACHE_H\n\nvoid flush_cache(unsigned long start_addr, unsigned long size);\n\n#endif /* __CACHE_H */\n"
  },
  {
    "path": "target/linux/bmips/image/lzma-loader/src/cacheops.h",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later\n/*\n * Cache operations for the cache instruction.\n *\n * (C) Copyright 1996, 97, 99, 2002, 03 Ralf Baechle\n * (C) Copyright 1999 Silicon Graphics, Inc.\n */\n#ifndef\t__ASM_CACHEOPS_H\n#define\t__ASM_CACHEOPS_H\n\n/*\n * Cache Operations available on all MIPS processors with R4000-style caches\n */\n#define Index_Invalidate_I      0x00\n#define Index_Writeback_Inv_D   0x01\n#define Index_Load_Tag_I\t0x04\n#define Index_Load_Tag_D\t0x05\n#define Index_Store_Tag_I\t0x08\n#define Index_Store_Tag_D\t0x09\n#if defined(CONFIG_CPU_LOONGSON2)\n#define Hit_Invalidate_I\t0x00\n#else\n#define Hit_Invalidate_I\t0x10\n#endif\n#define Hit_Invalidate_D\t0x11\n#define Hit_Writeback_Inv_D\t0x15\n\n/*\n * R4000-specific cacheops\n */\n#define Create_Dirty_Excl_D\t0x0d\n#define Fill\t\t\t0x14\n#define Hit_Writeback_I\t\t0x18\n#define Hit_Writeback_D\t\t0x19\n\n/*\n * R4000SC and R4400SC-specific cacheops\n */\n#define Index_Invalidate_SI     0x02\n#define Index_Writeback_Inv_SD  0x03\n#define Index_Load_Tag_SI\t0x06\n#define Index_Load_Tag_SD\t0x07\n#define Index_Store_Tag_SI\t0x0A\n#define Index_Store_Tag_SD\t0x0B\n#define Create_Dirty_Excl_SD\t0x0f\n#define Hit_Invalidate_SI\t0x12\n#define Hit_Invalidate_SD\t0x13\n#define Hit_Writeback_Inv_SD\t0x17\n#define Hit_Writeback_SD\t0x1b\n#define Hit_Set_Virtual_SI\t0x1e\n#define Hit_Set_Virtual_SD\t0x1f\n\n/*\n * R5000-specific cacheops\n */\n#define R5K_Page_Invalidate_S\t0x17\n\n/*\n * RM7000-specific cacheops\n */\n#define Page_Invalidate_T\t0x16\n\n/*\n * R10000-specific cacheops\n *\n * Cacheops 0x02, 0x06, 0x0a, 0x0c-0x0e, 0x16, 0x1a and 0x1e are unused.\n * Most of the _S cacheops are identical to the R4000SC _SD cacheops.\n */\n#define Index_Writeback_Inv_S\t0x03\n#define Index_Load_Tag_S\t0x07\n#define Index_Store_Tag_S\t0x0B\n#define Hit_Invalidate_S\t0x13\n#define Cache_Barrier\t\t0x14\n#define Hit_Writeback_Inv_S\t0x17\n#define Index_Load_Data_I\t0x18\n#define Index_Load_Data_D\t0x19\n#define Index_Load_Data_S\t0x1b\n#define Index_Store_Data_I\t0x1c\n#define Index_Store_Data_D\t0x1d\n#define Index_Store_Data_S\t0x1f\n\n#endif\t/* __ASM_CACHEOPS_H */\n"
  },
  {
    "path": "target/linux/bmips/image/lzma-loader/src/config.h",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later\n/*\n * LZMA compressed kernel loader for Atheros AR7XXX/AR9XXX based boards\n *\n * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>\n */\n\n#ifndef _CONFIG_H_\n#define _CONFIG_H_\n\n#define CONFIG_ICACHE_SIZE\t(32 * 1024)\n#define CONFIG_DCACHE_SIZE\t(32 * 1024)\n#define CONFIG_CACHELINE_SIZE\t16\n\n#endif /* _CONFIG_H_ */\n"
  },
  {
    "path": "target/linux/bmips/image/lzma-loader/src/cp0regdef.h",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later\n/*\n * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle\n *\n * Copyright (C) 2001, Monta Vista Software\n * Author: jsun@mvista.com or jsun@junsun.net\n */\n#ifndef _cp0regdef_h_\n#define _cp0regdef_h_\n\n#define CP0_INDEX $0\n#define CP0_RANDOM $1\n#define CP0_ENTRYLO0 $2\n#define CP0_ENTRYLO1 $3\n#define CP0_CONTEXT $4\n#define CP0_PAGEMASK $5\n#define CP0_WIRED $6\n#define CP0_BADVADDR $8\n#define CP0_COUNT $9\n#define CP0_ENTRYHI $10\n#define CP0_COMPARE $11\n#define CP0_STATUS $12\n#define CP0_CAUSE $13\n#define CP0_EPC $14\n#define CP0_PRID $15\n#define CP0_CONFIG $16\n#define CP0_LLADDR $17\n#define CP0_WATCHLO $18\n#define CP0_WATCHHI $19\n#define CP0_XCONTEXT $20\n#define CP0_FRAMEMASK $21\n#define CP0_DIAGNOSTIC $22\n#define CP0_PERFORMANCE $25\n#define CP0_ECC $26\n#define CP0_CACHEERR $27\n#define CP0_TAGLO $28\n#define CP0_TAGHI $29\n#define CP0_ERROREPC $30\n\n#define read_32bit_c0_register(reg,sel)\t\t\t\t\t\\\n({\tint __res;\t\t\t\t\t\t\t\\\n\tif (sel == 0)\t\t\t\t\t\t\t\\\n\t\t__asm__ __volatile__(\t\t\t\t\t\\\n\t\t\t\"mfc0\\t%0, \" #reg \"\\n\\t\"\t\t\t\\\n\t\t\t: \"=r\" (__res));\t\t\t\t\\\n\telse\t\t\t\t\t\t\t\t\\\n\t\t__asm__ __volatile__(\t\t\t\t\t\\\n\t\t\t\".set\\tmips32\\n\\t\"\t\t\t\t\\\n\t\t\t\"mfc0\\t%0, \" #reg \", \" #sel \"\\n\\t\"\t\t\\\n\t\t\t\".set mips0\\n\\t\"\t\t\t\t\\\n\t\t\t: \"=r\" (__res));\t\t\t\t\\\n\t__res;\t\t\t\t\t\t\t\t\\\n})\n\n#endif\n"
  },
  {
    "path": "target/linux/bmips/image/lzma-loader/src/head.S",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later\n/*\n * LZMA compressed kernel loader for Atheros AR7XXX/AR9XXX based boards\n *\n * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>\n *\n * Some parts of this code was based on the OpenWrt specific lzma-loader\n * for the BCM47xx and ADM5120 based boards:\n *\tCopyright (C) 2004 Manuel Novoa III (mjn3@codepoet.org)\n *\tCopyright (C) 2005 by Oleg I. Vdovikin <oleg@cs.msu.su>\n */\n\n#include <asm/asm.h>\n#include <asm/regdef.h>\n#include \"cp0regdef.h\"\n#include \"cacheops.h\"\n#include \"config.h\"\n\n#define KSEG0\t\t0x80000000\n\n\t.macro\tehb\n\tsll     zero, 3\n\t.endm\n\n\t.text\n\nLEAF(startup)\n\t.set noreorder\n\t.set mips32\n\n\tmtc0\tzero, CP0_WATCHLO\t# clear watch registers\n\tmtc0\tzero, CP0_WATCHHI\n\tmtc0\tzero, CP0_CAUSE\t\t# clear before writing status register\n\n\tmfc0\tt0, CP0_STATUS\n\tli\tt1, 0x1000001f\n\tor\tt0, t1\n\txori\tt0, 0x1f\n\tmtc0\tt0, CP0_STATUS\n\tehb\n\n\tmtc0\tzero, CP0_COUNT\n\tmtc0\tzero, CP0_COMPARE\n\tehb\n\n\tla\tt0, __reloc_label\t# get linked address of label\n\tbal\t__reloc_label\t\t# branch and link to label to\n\tnop\t\t\t\t# get actual address\n__reloc_label:\n\tsubu\tt0, ra, t0\t\t# get reloc_delta\n\n\tbeqz\tt0, __reloc_done         # if delta is 0 we are in the right place\n\tnop\n\n\t/* Copy our code to the right place */\n\tla\tt1, _code_start\t\t# get linked address of _code_start\n\tla\tt2, _code_end\t\t# get linked address of _code_end\n\taddu\tt0, t0, t1\t\t# calculate actual address of _code_start\n\n__reloc_copy:\n\tlw\tt3, 0(t0)\n\tsw\tt3, 0(t1)\n\tadd\tt1, 4\n\tblt\tt1, t2, __reloc_copy\n\tadd\tt0, 4\n\n\t/* flush cache */\n\tla\tt0, _code_start\n\tla\tt1, _code_end\n\n\tli\tt2, ~(CONFIG_CACHELINE_SIZE - 1)\n\tand\tt0, t2\n\tand\tt1, t2\n\tli\tt2, CONFIG_CACHELINE_SIZE\n\n\tb\t__flush_check\n\tnop\n\n__flush_line:\n\tcache\tHit_Writeback_Inv_D, 0(t0)\n\tcache\tHit_Invalidate_I, 0(t0)\n\tadd\tt0, t2\n\n__flush_check:\n\tbne\tt0, t1, __flush_line\n\tnop\n\n\tsync\n\n__reloc_done:\n\n\t/* clear bss */\n\tla\tt0, _bss_start\n\tla\tt1, _bss_end\n\tb\t__bss_check\n\tnop\n\n__bss_fill:\n\tsw\tzero, 0(t0)\n\taddi\tt0, 4\n\n__bss_check:\n\tbne\tt0, t1, __bss_fill\n\tnop\n\n\t/* Setup new \"C\" stack */\n\tla\tsp, _stack\n\n\t/* reserve stack space for a0-a3 registers */\n\tsubu\tsp, 16\n\n\t/* jump to the decompressor routine */\n\tla\tt0, loader_main\n\tjr\tt0\n\tnop\n\n\t.set reorder\nEND(startup)\n"
  },
  {
    "path": "target/linux/bmips/image/lzma-loader/src/loader.c",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later\n/*\n * LZMA compressed kernel loader for Atheros AR7XXX/AR9XXX based boards\n *\n * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>\n *\n * Some parts of this code was based on the OpenWrt specific lzma-loader\n * for the BCM47xx and ADM5120 based boards:\n *\tCopyright (C) 2004 Manuel Novoa III (mjn3@codepoet.org)\n *\tCopyright (C) 2005 Mineharu Takahara <mtakahar@yahoo.com>\n *\tCopyright (C) 2005 by Oleg I. Vdovikin <oleg@cs.msu.su>\n *\n * The image_header structure has been taken from the U-Boot project.\n *\t(C) Copyright 2008 Semihalf\n *\t(C) Copyright 2000-2005\n *\tWolfgang Denk, DENX Software Engineering, wd@denx.de.\n */\n\n#include <stddef.h>\n#include <stdint.h>\n\n#include \"config.h\"\n#include \"cache.h\"\n#include \"printf.h\"\n#include \"LzmaDecode.h\"\n\n#define KSEG0\t\t\t0x80000000\n#define KSEG1\t\t\t0xa0000000\n\n#define KSEG1ADDR(a)\t\t((((unsigned)(a)) & 0x1fffffffU) | KSEG1)\n\n#undef LZMA_DEBUG\n\n#ifdef LZMA_DEBUG\n#  define DBG(f, a...)\tprintf(f, ## a)\n#else\n#  define DBG(f, a...)\tdo {} while (0)\n#endif\n\n/* beyond the image end, size not known in advance */\nextern unsigned char workspace[];\n\n\nstatic CLzmaDecoderState lzma_state;\nstatic unsigned char *lzma_data;\nstatic unsigned long lzma_datasize;\nstatic unsigned long lzma_outsize;\nstatic unsigned long kernel_la;\n\nstatic void halt(void)\n{\n\tprintf(\"\\nSystem halted!\\n\");\n\tfor(;;);\n}\n\nstatic __inline__ unsigned char lzma_get_byte(void)\n{\n\tunsigned char c;\n\n\tlzma_datasize--;\n\tc = *lzma_data++;\n\n\treturn c;\n}\n\nstatic int lzma_init_props(void)\n{\n\tunsigned char props[LZMA_PROPERTIES_SIZE];\n\tint res;\n\tint i;\n\n\t/* read lzma properties */\n\tfor (i = 0; i < LZMA_PROPERTIES_SIZE; i++)\n\t\tprops[i] = lzma_get_byte();\n\n\t/* read the lower half of uncompressed size in the header */\n\tlzma_outsize = ((SizeT) lzma_get_byte()) +\n\t\t       ((SizeT) lzma_get_byte() << 8) +\n\t\t       ((SizeT) lzma_get_byte() << 16) +\n\t\t       ((SizeT) lzma_get_byte() << 24);\n\n\t/* skip rest of the header (upper half of uncompressed size) */\n\tfor (i = 0; i < 4; i++)\n\t\tlzma_get_byte();\n\n\tres = LzmaDecodeProperties(&lzma_state.Properties, props,\n\t\t\t\t\tLZMA_PROPERTIES_SIZE);\n\treturn res;\n}\n\nstatic int lzma_decompress(unsigned char *outStream)\n{\n\tSizeT ip, op;\n\tint ret;\n\n\tlzma_state.Probs = (CProb *) workspace;\n\n\tret = LzmaDecode(&lzma_state, lzma_data, lzma_datasize, &ip, outStream,\n\t\t\t lzma_outsize, &op);\n\n\tif (ret != LZMA_RESULT_OK) {\n\t\tint i;\n\n\t\tDBG(\"LzmaDecode error %d at %08x, osize:%d ip:%d op:%d\\n\",\n\t\t    ret, lzma_data + ip, lzma_outsize, ip, op);\n\n\t\tfor (i = 0; i < 16; i++)\n\t\t\tDBG(\"%02x \", lzma_data[ip + i]);\n\n\t\tDBG(\"\\n\");\n\t}\n\n\treturn ret;\n}\n\nstatic void lzma_init_data(void)\n{\n\textern unsigned char _lzma_data_start[];\n\textern unsigned char _lzma_data_end[];\n\n\tkernel_la = LOADADDR;\n\tlzma_data = _lzma_data_start;\n\tlzma_datasize = _lzma_data_end - _lzma_data_start;\n}\n\nvoid loader_main(unsigned long reg_a0, unsigned long reg_a1,\n\t\t unsigned long reg_a2, unsigned long reg_a3)\n{\n\tvoid (*kernel_entry) (unsigned long, unsigned long, unsigned long,\n\t\t\t      unsigned long);\n\tint res;\n\n\tprintf(\"\\n\\nOpenWrt kernel loader for BMIPS\\n\");\n\tprintf(\"Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>\\n\");\n\tprintf(\"Copyright (C) 2014 Jonas Gorski <jogo@openwrt.org>\\n\");\n\tprintf(\"Copyright (C) 2020 Alvaro Fernandez Rojas <noltari@gmail.com>\\n\");\n\n\tlzma_init_data();\n\n\tres = lzma_init_props();\n\tif (res != LZMA_RESULT_OK) {\n\t\tprintf(\"Incorrect LZMA stream properties!\\n\");\n\t\thalt();\n\t}\n\n\tprintf(\"Decompressing kernel... \");\n\n\tres = lzma_decompress((unsigned char *) kernel_la);\n\tif (res != LZMA_RESULT_OK) {\n\t\tprintf(\"failed, \");\n\t\tswitch (res) {\n\t\tcase LZMA_RESULT_DATA_ERROR:\n\t\t\tprintf(\"data error!\\n\");\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tprintf(\"unknown error %d!\\n\", res);\n\t\t}\n\t\thalt();\n\t} else {\n\t\tprintf(\"done!\\n\");\n\t}\n\n\tflush_cache(kernel_la, lzma_outsize);\n\n\tprintf(\"Starting kernel at %08x...\\n\\n\", kernel_la);\n\n\tkernel_entry = (void *) kernel_la;\n\tkernel_entry(reg_a0, reg_a1, reg_a2, reg_a3);\n}\n"
  },
  {
    "path": "target/linux/bmips/image/lzma-loader/src/loader.lds",
    "content": "/* SPDX-License-Identifier: GPL-2.0-or-later */\n\nOUTPUT_ARCH(mips)\nSECTIONS {\n\t.text : {\n\t\t_code_start = .;\n\t\t*(.text)\n\t\t*(.text.*)\n\t\t*(.rodata)\n\t\t*(.rodata.*)\n\t\t*(.data.lzma)\n\t}\n\n\t. = ALIGN(32);\n\t.data : {\n\t\t*(.data)\n\t\t*(.data.*)\n\t}\n\n\t. = ALIGN(32);\n\t_code_end = .;\n\n\t_bss_start = .;\n\t.bss : {\n\t\t*(.bss)\n\t\t*(.bss.*)\n\t}\n\n\t. = ALIGN(32);\n\t_bss_end = .;\n\n\t. = . + 8192;\n\t_stack = .;\n\n\tworkspace = .;\n}\n"
  },
  {
    "path": "target/linux/bmips/image/lzma-loader/src/loader2.lds",
    "content": "/* SPDX-License-Identifier: GPL-2.0-or-later */\n\nOUTPUT_ARCH(mips)\nSECTIONS {\n\t.text : {\n\t\tstartup = .;\n\t\t*(.text)\n\t\t*(.text.*)\n\t\t*(.data)\n\t\t*(.data.*)\n\t}\n}\n"
  },
  {
    "path": "target/linux/bmips/image/lzma-loader/src/lzma-data.lds",
    "content": "/* SPDX-License-Identifier: GPL-2.0-or-later */\n\nOUTPUT_ARCH(mips)\nSECTIONS {\n\t.data.lzma : {\n\t\t_lzma_data_start = .;\n\t\t*(.data)\n\t\t_lzma_data_end = .;\n\t}\n}\n"
  },
  {
    "path": "target/linux/bmips/image/lzma-loader/src/printf.c",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later\n/*\n * Copyright (C) 2001 MontaVista Software Inc.\n * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net\n */\n\n#include\t\"printf.h\"\n\nextern void board_putc(int ch);\n\n/* this is the maximum width for a variable */\n#define\t\tLP_MAX_BUF\t256\n\n/* macros */\n#define\t\tIsDigit(x)\t( ((x) >= '0') && ((x) <= '9') )\n#define\t\tCtod(x)\t\t( (x) - '0')\n\n/* forward declaration */\nstatic int PrintChar(char *, char, int, int);\nstatic int PrintString(char *, char *, int, int);\nstatic int PrintNum(char *, unsigned long, int, int, int, int, char, int);\n\n/* private variable */\nstatic const char theFatalMsg[] = \"fatal error in lp_Print!\";\n\n/* -*-\n * A low level printf() function.\n */\nstatic void\nlp_Print(void (*output)(void *, char *, int),\n\t void * arg,\n\t char *fmt,\n\t va_list ap)\n{\n\n#define \tOUTPUT(arg, s, l)  \\\n  { if (((l) < 0) || ((l) > LP_MAX_BUF)) { \\\n       (*output)(arg, (char*)theFatalMsg, sizeof(theFatalMsg)-1); for(;;); \\\n    } else { \\\n      (*output)(arg, s, l); \\\n    } \\\n  }\n\n    char buf[LP_MAX_BUF];\n\n    char c;\n    char *s;\n    long int num;\n\n    int longFlag;\n    int negFlag;\n    int width;\n    int prec;\n    int ladjust;\n    char padc;\n\n    int length;\n\n    for(;;) {\n\t{\n\t    /* scan for the next '%' */\n\t    char *fmtStart = fmt;\n\t    while ( (*fmt != '\\0') && (*fmt != '%')) {\n\t\tfmt ++;\n\t    }\n\n\t    /* flush the string found so far */\n\t    OUTPUT(arg, fmtStart, fmt-fmtStart);\n\n\t    /* are we hitting the end? */\n\t    if (*fmt == '\\0') break;\n\t}\n\n\t/* we found a '%' */\n\tfmt ++;\n\n\t/* check for long */\n\tif (*fmt == 'l') {\n\t    longFlag = 1;\n\t    fmt ++;\n\t} else {\n\t    longFlag = 0;\n\t}\n\n\t/* check for other prefixes */\n\twidth = 0;\n\tprec = -1;\n\tladjust = 0;\n\tpadc = ' ';\n\n\tif (*fmt == '-') {\n\t    ladjust = 1;\n\t    fmt ++;\n\t}\n\n\tif (*fmt == '0') {\n\t    padc = '0';\n\t    fmt++;\n\t}\n\n\tif (IsDigit(*fmt)) {\n\t    while (IsDigit(*fmt)) {\n\t\twidth = 10 * width + Ctod(*fmt++);\n\t    }\n\t}\n\n\tif (*fmt == '.') {\n\t    fmt ++;\n\t    if (IsDigit(*fmt)) {\n\t\tprec = 0;\n\t\twhile (IsDigit(*fmt)) {\n\t\t    prec = prec*10 + Ctod(*fmt++);\n\t\t}\n\t    }\n\t}\n\n\n\t/* check format flag */\n\tnegFlag = 0;\n\tswitch (*fmt) {\n\t case 'b':\n\t    if (longFlag) {\n\t\tnum = va_arg(ap, long int);\n\t    } else {\n\t\tnum = va_arg(ap, int);\n\t    }\n\t    length = PrintNum(buf, num, 2, 0, width, ladjust, padc, 0);\n\t    OUTPUT(arg, buf, length);\n\t    break;\n\n\t case 'd':\n\t case 'D':\n\t    if (longFlag) {\n\t\tnum = va_arg(ap, long int);\n\t    } else {\n\t\tnum = va_arg(ap, int);\n\t    }\n\t    if (num < 0) {\n\t\tnum = - num;\n\t\tnegFlag = 1;\n\t    }\n\t    length = PrintNum(buf, num, 10, negFlag, width, ladjust, padc, 0);\n\t    OUTPUT(arg, buf, length);\n\t    break;\n\n\t case 'o':\n\t case 'O':\n\t    if (longFlag) {\n\t\tnum = va_arg(ap, long int);\n\t    } else {\n\t\tnum = va_arg(ap, int);\n\t    }\n\t    length = PrintNum(buf, num, 8, 0, width, ladjust, padc, 0);\n\t    OUTPUT(arg, buf, length);\n\t    break;\n\n\t case 'u':\n\t case 'U':\n\t    if (longFlag) {\n\t\tnum = va_arg(ap, long int);\n\t    } else {\n\t\tnum = va_arg(ap, int);\n\t    }\n\t    length = PrintNum(buf, num, 10, 0, width, ladjust, padc, 0);\n\t    OUTPUT(arg, buf, length);\n\t    break;\n\n\t case 'x':\n\t    if (longFlag) {\n\t\tnum = va_arg(ap, long int);\n\t    } else {\n\t\tnum = va_arg(ap, int);\n\t    }\n\t    length = PrintNum(buf, num, 16, 0, width, ladjust, padc, 0);\n\t    OUTPUT(arg, buf, length);\n\t    break;\n\n\t case 'X':\n\t    if (longFlag) {\n\t\tnum = va_arg(ap, long int);\n\t    } else {\n\t\tnum = va_arg(ap, int);\n\t    }\n\t    length = PrintNum(buf, num, 16, 0, width, ladjust, padc, 1);\n\t    OUTPUT(arg, buf, length);\n\t    break;\n\n\t case 'c':\n\t    c = (char)va_arg(ap, int);\n\t    length = PrintChar(buf, c, width, ladjust);\n\t    OUTPUT(arg, buf, length);\n\t    break;\n\n\t case 's':\n\t    s = (char*)va_arg(ap, char *);\n\t    length = PrintString(buf, s, width, ladjust);\n\t    OUTPUT(arg, buf, length);\n\t    break;\n\n\t case '\\0':\n\t    fmt --;\n\t    break;\n\n\t default:\n\t    /* output this char as it is */\n\t    OUTPUT(arg, fmt, 1);\n\t}\t/* switch (*fmt) */\n\n\tfmt ++;\n    }\t\t/* for(;;) */\n\n    /* special termination call */\n    OUTPUT(arg, \"\\0\", 1);\n}\n\n\n/* --------------- local help functions --------------------- */\nstatic int\nPrintChar(char * buf, char c, int length, int ladjust)\n{\n    int i;\n\n    if (length < 1) length = 1;\n    if (ladjust) {\n\t*buf = c;\n\tfor (i=1; i< length; i++) buf[i] = ' ';\n    } else {\n\tfor (i=0; i< length-1; i++) buf[i] = ' ';\n\tbuf[length - 1] = c;\n    }\n    return length;\n}\n\nstatic int\nPrintString(char * buf, char* s, int length, int ladjust)\n{\n    int i;\n    int len=0;\n    char* s1 = s;\n    while (*s1++) len++;\n    if (length < len) length = len;\n\n    if (ladjust) {\n\tfor (i=0; i< len; i++) buf[i] = s[i];\n\tfor (i=len; i< length; i++) buf[i] = ' ';\n    } else {\n\tfor (i=0; i< length-len; i++) buf[i] = ' ';\n\tfor (i=length-len; i < length; i++) buf[i] = s[i-length+len];\n    }\n    return length;\n}\n\nstatic int\nPrintNum(char * buf, unsigned long u, int base, int negFlag,\n\t int length, int ladjust, char padc, int upcase)\n{\n    /* algorithm :\n     *  1. prints the number from left to right in reverse form.\n     *  2. fill the remaining spaces with padc if length is longer than\n     *     the actual length\n     *     TRICKY : if left adjusted, no \"0\" padding.\n     *\t\t    if negtive, insert  \"0\" padding between \"0\" and number.\n     *  3. if (!ladjust) we reverse the whole string including paddings\n     *  4. otherwise we only reverse the actual string representing the num.\n     */\n\n    int actualLength =0;\n    char *p = buf;\n    int i;\n\n    do {\n\tint tmp = u %base;\n\tif (tmp <= 9) {\n\t    *p++ = '0' + tmp;\n\t} else if (upcase) {\n\t    *p++ = 'A' + tmp - 10;\n\t} else {\n\t    *p++ = 'a' + tmp - 10;\n\t}\n\tu /= base;\n    } while (u != 0);\n\n    if (negFlag) {\n\t*p++ = '-';\n    }\n\n    /* figure out actual length and adjust the maximum length */\n    actualLength = p - buf;\n    if (length < actualLength) length = actualLength;\n\n    /* add padding */\n    if (ladjust) {\n\tpadc = ' ';\n    }\n    if (negFlag && !ladjust && (padc == '0')) {\n\tfor (i = actualLength-1; i< length-1; i++) buf[i] = padc;\n\tbuf[length -1] = '-';\n    } else {\n\tfor (i = actualLength; i< length; i++) buf[i] = padc;\n    }\n\n\n    /* prepare to reverse the string */\n    {\n\tint begin = 0;\n\tint end;\n\tif (ladjust) {\n\t    end = actualLength - 1;\n\t} else {\n\t    end = length -1;\n\t}\n\n\twhile (end > begin) {\n\t    char tmp = buf[begin];\n\t    buf[begin] = buf[end];\n\t    buf[end] = tmp;\n\t    begin ++;\n\t    end --;\n\t}\n    }\n\n    /* adjust the string pointer */\n    return length;\n}\n\nstatic void printf_output(void *arg, char *s, int l)\n{\n    int i;\n\n    // special termination call\n    if ((l==1) && (s[0] == '\\0')) return;\n\n    for (i=0; i< l; i++) {\n\tboard_putc(s[i]);\n\tif (s[i] == '\\n') board_putc('\\r');\n    }\n}\n\nvoid printf(char *fmt, ...)\n{\n    va_list ap;\n    va_start(ap, fmt);\n    lp_Print(printf_output, 0, fmt, ap);\n    va_end(ap);\n}\n"
  },
  {
    "path": "target/linux/bmips/image/lzma-loader/src/printf.h",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later\n/*\n * Copyright (C) 2001 MontaVista Software Inc.\n * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net\n */\n\n#ifndef _printf_h_\n#define _printf_h_\n\n#include <stdarg.h>\nvoid printf(char *fmt, ...);\n\n#endif /* _printf_h_ */\n"
  },
  {
    "path": "target/linux/bmips/nand/base-files/etc/board.d/01_leds",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n. /lib/functions/leds.sh\n. /lib/functions/uci-defaults.sh\n\nboard_config_update\n\nled_usb=\"$(get_dt_led usb)\"\n[ -n \"$led_usb\" ] && ucidef_set_led_usbdev \"usb\" \"usb\" \"$led_usb\" \"1-1\"\n\nled_usb2=\"$(get_dt_led usb2)\"\n[ -n \"$led_usb2\" ] && ucidef_set_led_usbdev \"usb2\" \"usb2\" \"$led_usb2\" \"2-1\"\n\nboard_config_flush\n\nexit 0\n"
  },
  {
    "path": "target/linux/bmips/nand/base-files/etc/board.d/02_network",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n. /lib/functions/uci-defaults.sh\n\nboard_config_update\n\ncase \"$(board_name)\" in\ncomtrend,vr-3032u)\n\tucidef_set_interface_lan \"lan1 lan2 lan3 lan4\"\n\t;;\nnetgear,dgnd3700-v2)\n\tucidef_set_interface_lan \"extsw\"\n\t;;\nesac\n\nboard_config_flush\n\nexit 0\n"
  },
  {
    "path": "target/linux/bmips/nand/base-files/lib/upgrade/platform.sh",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\nPART_NAME=firmware\nREQUIRE_IMAGE_METADATA=1\n\nplatform_check_image() {\n\treturn 0\n}\n\ncfe_jffs2_nand_upgrade() {\n\tlocal tar_file=\"$1\"\n\tlocal kernel_mtd=\"$(find_mtd_index $CI_KERNPART)\"\n\n\tif [ -z \"$kernel_mtd\" ]; then\n\t\techo \"$CI_KERNPART partition not found\"\n\t\treturn 1\n\tfi\n\n\tlocal board_dir=$(tar tf $tar_file | grep -m 1 '^sysupgrade-.*/$')\n\tboard_dir=${board_dir%/}\n\n\tlocal kernel_length=$(tar xf $tar_file ${board_dir}/kernel -O | wc -c 2> /dev/null)\n\tlocal rootfs_length=$(tar xf $tar_file ${board_dir}/root -O | wc -c 2> /dev/null)\n\n\tif [ \"$kernel_length\" = 0 ]; then\n\t\techo \"kernel cannot be empty\"\n\t\treturn 1\n\tfi\n\n\tflash_erase -j /dev/mtd${kernel_mtd} 0 0\n\ttar xf $tar_file ${board_dir}/kernel -O | nandwrite /dev/mtd${kernel_mtd} -\n\n\tlocal rootfs_type=\"$(identify_tar \"$tar_file\" ${board_dir}/root)\"\n\n\tnand_upgrade_prepare_ubi \"$rootfs_length\" \"$rootfs_type\" \"0\" \"0\"\n\n\tlocal ubidev=\"$( nand_find_ubi \"$CI_UBIPART\" )\"\n\n\tlocal root_ubivol=\"$(nand_find_volume $ubidev $CI_ROOTPART)\"\n\ttar xf $tar_file ${board_dir}/root -O | \\\n\t\tubiupdatevol /dev/$root_ubivol -s $rootfs_length -\n\n\tnand_do_upgrade_success\n}\n\nplatform_do_upgrade() {\n\tcase \"$(board_name)\" in\n\t\tcomtrend,vr-3032u|\\\n\t\tnetgear,dgnd3700-v2)\n\t\t\tcfe_jffs2_nand_upgrade \"$1\"\n\t\t\t;;\n\t\t*)\n\t\t\tnand_do_upgrade \"$1\"\n\t\t\t;;\n\tesac\n}\n"
  },
  {
    "path": "target/linux/bmips/nand/config-default",
    "content": "CONFIG_CRC16=y\nCONFIG_CRYPTO_ACOMP2=y\nCONFIG_CRYPTO_DEFLATE=y\nCONFIG_CRYPTO_HASH_INFO=y\nCONFIG_CRYPTO_LZO=y\nCONFIG_CRYPTO_ZSTD=y\nCONFIG_JFFS2_FS_NAND=y\nCONFIG_LZO_COMPRESS=y\nCONFIG_LZO_DECOMPRESS=y\nCONFIG_MTD_NAND_BRCMNAND=y\nCONFIG_MTD_NAND_CORE=y\nCONFIG_MTD_NAND_ECC_SW_HAMMING=y\nCONFIG_MTD_RAW_NAND=y\nCONFIG_MTD_SPLIT_BCM_WFI_FW=y\nCONFIG_MTD_UBI=y\nCONFIG_MTD_UBI_BEB_LIMIT=20\nCONFIG_MTD_UBI_BLOCK=y\n# CONFIG_MTD_UBI_FASTMAP is not set\n# CONFIG_MTD_UBI_GLUEBI is not set\nCONFIG_MTD_UBI_WL_THRESHOLD=4096\nCONFIG_SGL_ALLOC=y\nCONFIG_UBIFS_FS=y\nCONFIG_XXHASH=y\nCONFIG_ZLIB_DEFLATE=y\nCONFIG_ZLIB_INFLATE=y\nCONFIG_ZSTD_COMPRESS=y\nCONFIG_ZSTD_DECOMPRESS=y\n"
  },
  {
    "path": "target/linux/bmips/nand/target.mk",
    "content": "BOARDNAME:=nand\nFEATURES+=nand\n\ndefine Target/Description\n  BMIPS boards with NAND support \nendef\n"
  },
  {
    "path": "target/linux/bmips/patches-5.10/001-v5.11-mips-bmips-select-ARCH_HAS_RESET_CONTROLLER.patch",
    "content": "From 29906e1aac11bf9907e26608216dc7970e73a70e Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com>\nDate: Wed, 17 Jun 2020 12:50:33 +0200\nSubject: [PATCH 1/9] mips: bmips: select ARCH_HAS_RESET_CONTROLLER\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nThis allows to add reset controllers support.\n\nSigned-off-by: Álvaro Fernández Rojas <noltari@gmail.com>\nAcked-by: Florian Fainelli <f.fainelli@gmail.com>\nSigned-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>\n---\n arch/mips/Kconfig | 1 +\n 1 file changed, 1 insertion(+)\n\n--- a/arch/mips/Kconfig\n+++ b/arch/mips/Kconfig\n@@ -252,6 +252,7 @@ config ATH79\n \n config BMIPS_GENERIC\n \tbool \"Broadcom Generic BMIPS kernel\"\n+\tselect ARCH_HAS_RESET_CONTROLLER\n \tselect ARCH_HAS_SYNC_DMA_FOR_CPU_ALL\n \tselect ARCH_HAS_PHYS_TO_DMA\n \tselect BOOT_RAW\n"
  },
  {
    "path": "target/linux/bmips/patches-5.10/002-v5.11-dt-bindings-reset-add-BCM6345-reset-controller-bindi.patch",
    "content": "From 10c1e714a68b45b124157aa02d80abe244a2a61a Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com>\nDate: Wed, 17 Jun 2020 12:50:34 +0200\nSubject: [PATCH 2/9] dt-bindings: reset: add BCM6345 reset controller bindings\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nAdd device tree binding documentation for BCM6345 reset controller.\n\nSigned-off-by: Álvaro Fernández Rojas <noltari@gmail.com>\nReviewed-by: Florian Fainelli <f.fainelli@gmail.com>\nReviewed-by: Rob Herring <robh@kernel.org>\nSigned-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>\n---\n .../bindings/reset/brcm,bcm6345-reset.yaml    | 37 +++++++++++++++++++\n 1 file changed, 37 insertions(+)\n create mode 100644 Documentation/devicetree/bindings/reset/brcm,bcm6345-reset.yaml\n\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/reset/brcm,bcm6345-reset.yaml\n@@ -0,0 +1,37 @@\n+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)\n+%YAML 1.2\n+---\n+$id: \"http://devicetree.org/schemas/reset/brcm,bcm6345-reset.yaml#\"\n+$schema: \"http://devicetree.org/meta-schemas/core.yaml#\"\n+\n+title: BCM6345 reset controller\n+\n+description: This document describes the BCM6345 reset controller.\n+\n+maintainers:\n+  - Álvaro Fernández Rojas <noltari@gmail.com>\n+\n+properties:\n+  compatible:\n+    const: brcm,bcm6345-reset\n+\n+  reg:\n+    maxItems: 1\n+\n+  \"#reset-cells\":\n+    const: 1\n+\n+required:\n+  - compatible\n+  - reg\n+  - \"#reset-cells\"\n+\n+additionalProperties: false\n+\n+examples:\n+  - |\n+    reset-controller@10000010 {\n+      compatible = \"brcm,bcm6345-reset\";\n+      reg = <0x10000010 0x4>;\n+      #reset-cells = <1>;\n+    };\n"
  },
  {
    "path": "target/linux/bmips/patches-5.10/003-v5.11-reset-add-BCM6345-reset-controller-driver.patch",
    "content": "From aac025437f14c1647dc6054b95daeebed34f6971 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com>\nDate: Wed, 17 Jun 2020 12:50:35 +0200\nSubject: [PATCH 3/9] reset: add BCM6345 reset controller driver\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nAdd support for resetting blocks through the Linux reset controller\nsubsystem for BCM63xx SoCs.\n\nSigned-off-by: Álvaro Fernández Rojas <noltari@gmail.com>\nReviewed-by: Florian Fainelli <F.fainelli@gmail.com>\nReviewed-by: Philipp Zabel <p.zabel@pengutronix.de>\nSigned-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>\n---\n drivers/reset/Kconfig         |   7 ++\n drivers/reset/Makefile        |   1 +\n drivers/reset/reset-bcm6345.c | 135 ++++++++++++++++++++++++++++++++++\n 3 files changed, 143 insertions(+)\n create mode 100644 drivers/reset/reset-bcm6345.c\n\n--- a/drivers/reset/Kconfig\n+++ b/drivers/reset/Kconfig\n@@ -35,6 +35,13 @@ config RESET_AXS10X\n \thelp\n \t  This enables the reset controller driver for AXS10x.\n \n+config RESET_BCM6345\n+\tbool \"BCM6345 Reset Controller\"\n+\tdepends on BMIPS_GENERIC || COMPILE_TEST\n+\tdefault BMIPS_GENERIC\n+\thelp\n+\t  This enables the reset controller driver for BCM6345 SoCs.\n+\n config RESET_BERLIN\n \tbool \"Berlin Reset Driver\" if COMPILE_TEST\n \tdefault ARCH_BERLIN\n--- a/drivers/reset/Makefile\n+++ b/drivers/reset/Makefile\n@@ -6,6 +6,7 @@ obj-$(CONFIG_ARCH_TEGRA) += tegra/\n obj-$(CONFIG_RESET_A10SR) += reset-a10sr.o\n obj-$(CONFIG_RESET_ATH79) += reset-ath79.o\n obj-$(CONFIG_RESET_AXS10X) += reset-axs10x.o\n+obj-$(CONFIG_RESET_BCM6345) += reset-bcm6345.o\n obj-$(CONFIG_RESET_BERLIN) += reset-berlin.o\n obj-$(CONFIG_RESET_BRCMSTB) += reset-brcmstb.o\n obj-$(CONFIG_RESET_BRCMSTB_RESCAL) += reset-brcmstb-rescal.o\n--- /dev/null\n+++ b/drivers/reset/reset-bcm6345.c\n@@ -0,0 +1,135 @@\n+// SPDX-License-Identifier: GPL-2.0-or-later\n+/*\n+ * BCM6345 Reset Controller Driver\n+ *\n+ * Copyright (C) 2020 Álvaro Fernández Rojas <noltari@gmail.com>\n+ */\n+\n+#include <linux/delay.h>\n+#include <linux/init.h>\n+#include <linux/io.h>\n+#include <linux/mod_devicetable.h>\n+#include <linux/platform_device.h>\n+#include <linux/reset-controller.h>\n+\n+#define BCM6345_RESET_NUM\t\t32\n+#define BCM6345_RESET_SLEEP_MIN_US\t10000\n+#define BCM6345_RESET_SLEEP_MAX_US\t20000\n+\n+struct bcm6345_reset {\n+\tstruct reset_controller_dev rcdev;\n+\tvoid __iomem *base;\n+\tspinlock_t lock;\n+};\n+\n+static inline struct bcm6345_reset *\n+to_bcm6345_reset(struct reset_controller_dev *rcdev)\n+{\n+\treturn container_of(rcdev, struct bcm6345_reset, rcdev);\n+}\n+\n+static int bcm6345_reset_update(struct reset_controller_dev *rcdev,\n+\t\t\t\tunsigned long id, bool assert)\n+{\n+\tstruct bcm6345_reset *bcm6345_reset = to_bcm6345_reset(rcdev);\n+\tunsigned long flags;\n+\tuint32_t val;\n+\n+\tspin_lock_irqsave(&bcm6345_reset->lock, flags);\n+\tval = __raw_readl(bcm6345_reset->base);\n+\tif (assert)\n+\t\tval &= ~BIT(id);\n+\telse\n+\t\tval |= BIT(id);\n+\t__raw_writel(val, bcm6345_reset->base);\n+\tspin_unlock_irqrestore(&bcm6345_reset->lock, flags);\n+\n+\treturn 0;\n+}\n+\n+static int bcm6345_reset_assert(struct reset_controller_dev *rcdev,\n+\t\t\t\tunsigned long id)\n+{\n+\treturn bcm6345_reset_update(rcdev, id, true);\n+}\n+\n+static int bcm6345_reset_deassert(struct reset_controller_dev *rcdev,\n+\t\t\t\t  unsigned long id)\n+{\n+\treturn bcm6345_reset_update(rcdev, id, false);\n+}\n+\n+static int bcm6345_reset_reset(struct reset_controller_dev *rcdev,\n+\t\t\t       unsigned long id)\n+{\n+\tbcm6345_reset_update(rcdev, id, true);\n+\tusleep_range(BCM6345_RESET_SLEEP_MIN_US,\n+\t\t     BCM6345_RESET_SLEEP_MAX_US);\n+\n+\tbcm6345_reset_update(rcdev, id, false);\n+\t/*\n+\t * Ensure component is taken out reset state by sleeping also after\n+\t * deasserting the reset. Otherwise, the component may not be ready\n+\t * for operation.\n+\t */\n+\tusleep_range(BCM6345_RESET_SLEEP_MIN_US,\n+\t\t     BCM6345_RESET_SLEEP_MAX_US);\n+\n+\treturn 0;\n+}\n+\n+static int bcm6345_reset_status(struct reset_controller_dev *rcdev,\n+\t\t\t\tunsigned long id)\n+{\n+\tstruct bcm6345_reset *bcm6345_reset = to_bcm6345_reset(rcdev);\n+\n+\treturn !(__raw_readl(bcm6345_reset->base) & BIT(id));\n+}\n+\n+static struct reset_control_ops bcm6345_reset_ops = {\n+\t.assert = bcm6345_reset_assert,\n+\t.deassert = bcm6345_reset_deassert,\n+\t.reset = bcm6345_reset_reset,\n+\t.status = bcm6345_reset_status,\n+};\n+\n+static int bcm6345_reset_probe(struct platform_device *pdev)\n+{\n+\tstruct bcm6345_reset *bcm6345_reset;\n+\n+\tbcm6345_reset = devm_kzalloc(&pdev->dev,\n+\t\t\t\t     sizeof(*bcm6345_reset), GFP_KERNEL);\n+\tif (!bcm6345_reset)\n+\t\treturn -ENOMEM;\n+\n+\tplatform_set_drvdata(pdev, bcm6345_reset);\n+\n+\tbcm6345_reset->base = devm_platform_ioremap_resource(pdev, 0);\n+\tif (IS_ERR(bcm6345_reset->base))\n+\t\treturn PTR_ERR(bcm6345_reset->base);\n+\n+\tspin_lock_init(&bcm6345_reset->lock);\n+\tbcm6345_reset->rcdev.ops = &bcm6345_reset_ops;\n+\tbcm6345_reset->rcdev.owner = THIS_MODULE;\n+\tbcm6345_reset->rcdev.of_node = pdev->dev.of_node;\n+\tbcm6345_reset->rcdev.of_reset_n_cells = 1;\n+\tbcm6345_reset->rcdev.nr_resets = BCM6345_RESET_NUM;\n+\n+\treturn devm_reset_controller_register(&pdev->dev,\n+\t\t\t\t\t      &bcm6345_reset->rcdev);\n+}\n+\n+static const struct of_device_id bcm6345_reset_of_match[] = {\n+\t{ .compatible = \"brcm,bcm6345-reset\" },\n+\t{ /* sentinel */ },\n+};\n+\n+static struct platform_driver bcm6345_reset_driver = {\n+\t.probe = bcm6345_reset_probe,\n+\t.driver\t= {\n+\t\t.name = \"bcm6345-reset\",\n+\t\t.of_match_table = bcm6345_reset_of_match,\n+\t\t.suppress_bind_attrs = true,\n+\t},\n+};\n+builtin_platform_driver(bcm6345_reset_driver);\n"
  },
  {
    "path": "target/linux/bmips/patches-5.10/004-v5.11-mips-bmips-dts-add-BCM6328-reset-controller-support.patch",
    "content": "From 83f865d7e32e40b4903b1f83537c63fc5cdf1eb8 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com>\nDate: Wed, 17 Jun 2020 12:50:36 +0200\nSubject: [PATCH 4/9] mips: bmips: dts: add BCM6328 reset controller support\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nBCM6328 SoCs have a reset controller for certain components.\n\nSigned-off-by: Álvaro Fernández Rojas <noltari@gmail.com>\nAcked-by: Florian Fainelli <f.fainelli@gmail.com>\nReviewed-by: Rob Herring <robh@kernel.org>\nSigned-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>\n---\n arch/mips/boot/dts/brcm/bcm6328.dtsi      |  6 ++++++\n include/dt-bindings/reset/bcm6328-reset.h | 18 ++++++++++++++++++\n 2 files changed, 24 insertions(+)\n create mode 100644 include/dt-bindings/reset/bcm6328-reset.h\n\n--- a/arch/mips/boot/dts/brcm/bcm6328.dtsi\n+++ b/arch/mips/boot/dts/brcm/bcm6328.dtsi\n@@ -57,6 +57,12 @@\n \t\t\t#clock-cells = <1>;\n \t\t};\n \n+\t\tperiph_rst: reset-controller@10000010 {\n+\t\t\tcompatible = \"brcm,bcm6345-reset\";\n+\t\t\treg = <0x10000010 0x4>;\n+\t\t\t#reset-cells = <1>;\n+\t\t};\n+\n \t\tperiph_intc: interrupt-controller@10000020 {\n \t\t\tcompatible = \"brcm,bcm6345-l1-intc\";\n \t\t\treg = <0x10000020 0x10>,\n--- /dev/null\n+++ b/include/dt-bindings/reset/bcm6328-reset.h\n@@ -0,0 +1,18 @@\n+/* SPDX-License-Identifier: GPL-2.0+ */\n+\n+#ifndef __DT_BINDINGS_RESET_BCM6328_H\n+#define __DT_BINDINGS_RESET_BCM6328_H\n+\n+#define BCM6328_RST_SPI\t\t0\n+#define BCM6328_RST_EPHY\t1\n+#define BCM6328_RST_SAR\t\t2\n+#define BCM6328_RST_ENETSW\t3\n+#define BCM6328_RST_USBS\t4\n+#define BCM6328_RST_USBH\t5\n+#define BCM6328_RST_PCM\t\t6\n+#define BCM6328_RST_PCIE_CORE\t7\n+#define BCM6328_RST_PCIE\t8\n+#define BCM6328_RST_PCIE_EXT\t9\n+#define BCM6328_RST_PCIE_HARD\t10\n+\n+#endif /* __DT_BINDINGS_RESET_BCM6328_H */\n"
  },
  {
    "path": "target/linux/bmips/patches-5.10/005-v5.11-mips-bmips-dts-add-BCM6358-reset-controller-support.patch",
    "content": "From 8079cfba4c7b8cae900c27104b4512fa5ed1f021 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com>\nDate: Wed, 17 Jun 2020 12:50:37 +0200\nSubject: [PATCH 5/9] mips: bmips: dts: add BCM6358 reset controller support\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nBCM6358 SoCs have a reset controller for certain components.\n\nSigned-off-by: Álvaro Fernández Rojas <noltari@gmail.com>\nAcked-by: Florian Fainelli <f.fainelli@gmail.com>\nReviewed-by: Rob Herring <robh@kernel.org>\nSigned-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>\n---\n arch/mips/boot/dts/brcm/bcm6358.dtsi      |  6 ++++++\n include/dt-bindings/reset/bcm6358-reset.h | 15 +++++++++++++++\n 2 files changed, 21 insertions(+)\n create mode 100644 include/dt-bindings/reset/bcm6358-reset.h\n\n--- a/arch/mips/boot/dts/brcm/bcm6358.dtsi\n+++ b/arch/mips/boot/dts/brcm/bcm6358.dtsi\n@@ -82,6 +82,12 @@\n \t\t\tinterrupts = <2>, <3>;\n \t\t};\n \n+\t\tperiph_rst: reset-controller@fffe0034 {\n+\t\t\tcompatible = \"brcm,bcm6345-reset\";\n+\t\t\treg = <0xfffe0034 0x4>;\n+\t\t\t#reset-cells = <1>;\n+\t\t};\n+\n \t\tleds0: led-controller@fffe00d0 {\n \t\t\t#address-cells = <1>;\n \t\t\t#size-cells = <0>;\n--- /dev/null\n+++ b/include/dt-bindings/reset/bcm6358-reset.h\n@@ -0,0 +1,15 @@\n+/* SPDX-License-Identifier: GPL-2.0+ */\n+\n+#ifndef __DT_BINDINGS_RESET_BCM6358_H\n+#define __DT_BINDINGS_RESET_BCM6358_H\n+\n+#define BCM6358_RST_SPI\t\t0\n+#define BCM6358_RST_ENET\t2\n+#define BCM6358_RST_MPI\t\t3\n+#define BCM6358_RST_EPHY\t6\n+#define BCM6358_RST_SAR\t\t7\n+#define BCM6358_RST_USBH\t12\n+#define BCM6358_RST_PCM\t\t13\n+#define BCM6358_RST_ADSL\t14\n+\n+#endif /* __DT_BINDINGS_RESET_BCM6358_H */\n"
  },
  {
    "path": "target/linux/bmips/patches-5.10/006-v5.11-mips-bmips-dts-add-BCM6362-reset-controller-support.patch",
    "content": "From 226383600be58dcf2e070e4ac8a371640024fe54 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com>\nDate: Wed, 17 Jun 2020 12:50:38 +0200\nSubject: [PATCH 6/9] mips: bmips: dts: add BCM6362 reset controller support\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nBCM6362 SoCs have a reset controller for certain components.\n\nSigned-off-by: Álvaro Fernández Rojas <noltari@gmail.com>\nAcked-by: Florian Fainelli <f.fainelli@gmail.com>\nReviewed-by: Rob Herring <robh@kernel.org>\nSigned-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>\n---\n arch/mips/boot/dts/brcm/bcm6362.dtsi      |  6 ++++++\n include/dt-bindings/reset/bcm6362-reset.h | 22 ++++++++++++++++++++++\n 2 files changed, 28 insertions(+)\n create mode 100644 include/dt-bindings/reset/bcm6362-reset.h\n\n--- a/arch/mips/boot/dts/brcm/bcm6362.dtsi\n+++ b/arch/mips/boot/dts/brcm/bcm6362.dtsi\n@@ -70,6 +70,12 @@\n \t\t\tmask = <0x1>;\n \t\t};\n \n+\t\tperiph_rst: reset-controller@10000010 {\n+\t\t\tcompatible = \"brcm,bcm6345-reset\";\n+\t\t\treg = <0x10000010 0x4>;\n+\t\t\t#reset-cells = <1>;\n+\t\t};\n+\n \t\tperiph_intc: interrupt-controller@10000020 {\n \t\t\tcompatible = \"brcm,bcm6345-l1-intc\";\n \t\t\treg = <0x10000020 0x10>,\n--- /dev/null\n+++ b/include/dt-bindings/reset/bcm6362-reset.h\n@@ -0,0 +1,22 @@\n+/* SPDX-License-Identifier: GPL-2.0+ */\n+\n+#ifndef __DT_BINDINGS_RESET_BCM6362_H\n+#define __DT_BINDINGS_RESET_BCM6362_H\n+\n+#define BCM6362_RST_SPI\t\t0\n+#define BCM6362_RST_IPSEC\t1\n+#define BCM6362_RST_EPHY\t2\n+#define BCM6362_RST_SAR\t\t3\n+#define BCM6362_RST_ENETSW\t4\n+#define BCM6362_RST_USBD\t5\n+#define BCM6362_RST_USBH\t6\n+#define BCM6362_RST_PCM\t\t7\n+#define BCM6362_RST_PCIE_CORE\t8\n+#define BCM6362_RST_PCIE\t9\n+#define BCM6362_RST_PCIE_EXT\t10\n+#define BCM6362_RST_WLAN_SHIM\t11\n+#define BCM6362_RST_DDR_PHY\t12\n+#define BCM6362_RST_FAP\t\t13\n+#define BCM6362_RST_WLAN_UBUS\t14\n+\n+#endif /* __DT_BINDINGS_RESET_BCM6362_H */\n"
  },
  {
    "path": "target/linux/bmips/patches-5.10/007-v5.11-mips-bmips-dts-add-BCM6368-reset-controller-support.patch",
    "content": "From 7acf84e87857721d66a1ba800c2c50669089f43d Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com>\nDate: Wed, 17 Jun 2020 12:50:39 +0200\nSubject: [PATCH 7/9] mips: bmips: dts: add BCM6368 reset controller support\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nBCM6368 SoCs have a reset controller for certain components.\n\nSigned-off-by: Álvaro Fernández Rojas <noltari@gmail.com>\nAcked-by: Florian Fainelli <f.fainelli@gmail.com>\nReviewed-by: Rob Herring <robh@kernel.org>\nSigned-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>\n---\n arch/mips/boot/dts/brcm/bcm6368.dtsi      |  6 ++++++\n include/dt-bindings/reset/bcm6368-reset.h | 16 ++++++++++++++++\n 2 files changed, 22 insertions(+)\n create mode 100644 include/dt-bindings/reset/bcm6368-reset.h\n\n--- a/arch/mips/boot/dts/brcm/bcm6368.dtsi\n+++ b/arch/mips/boot/dts/brcm/bcm6368.dtsi\n@@ -70,6 +70,12 @@\n \t\t\tmask = <0x1>;\n \t\t};\n \n+\t\tperiph_rst: reset-controller@10000010 {\n+\t\t\tcompatible = \"brcm,bcm6345-reset\";\n+\t\t\treg = <0x10000010 0x4>;\n+\t\t\t#reset-cells = <1>;\n+\t\t};\n+\n \t\tperiph_intc: interrupt-controller@10000020 {\n \t\t\tcompatible = \"brcm,bcm6345-l1-intc\";\n \t\t\treg = <0x10000020 0x10>,\n--- /dev/null\n+++ b/include/dt-bindings/reset/bcm6368-reset.h\n@@ -0,0 +1,16 @@\n+/* SPDX-License-Identifier: GPL-2.0+ */\n+\n+#ifndef __DT_BINDINGS_RESET_BCM6368_H\n+#define __DT_BINDINGS_RESET_BCM6368_H\n+\n+#define BCM6368_RST_SPI\t\t0\n+#define BCM6368_RST_MPI\t\t3\n+#define BCM6368_RST_IPSEC\t4\n+#define BCM6368_RST_EPHY\t6\n+#define BCM6368_RST_SAR\t\t7\n+#define BCM6368_RST_SWITCH\t10\n+#define BCM6368_RST_USBD\t11\n+#define BCM6368_RST_USBH\t12\n+#define BCM6368_RST_PCM\t\t13\n+\n+#endif /* __DT_BINDINGS_RESET_BCM6368_H */\n"
  },
  {
    "path": "target/linux/bmips/patches-5.10/008-v5.11-mips-bmips-dts-add-BCM63268-reset-controller-support.patch",
    "content": "From b7aa228813bdf014d6ad173ca3abfced30f1ed37 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com>\nDate: Wed, 17 Jun 2020 12:50:40 +0200\nSubject: [PATCH 8/9] mips: bmips: dts: add BCM63268 reset controller support\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nBCM63268 SoCs have a reset controller for certain components.\n\nSigned-off-by: Álvaro Fernández Rojas <noltari@gmail.com>\nAcked-by: Florian Fainelli <f.fainelli@gmail.com>\nReviewed-by: Rob Herring <robh@kernel.org>\nSigned-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>\n---\n arch/mips/boot/dts/brcm/bcm63268.dtsi      |  6 +++++\n include/dt-bindings/reset/bcm63268-reset.h | 26 ++++++++++++++++++++++\n 2 files changed, 32 insertions(+)\n create mode 100644 include/dt-bindings/reset/bcm63268-reset.h\n\n--- a/arch/mips/boot/dts/brcm/bcm63268.dtsi\n+++ b/arch/mips/boot/dts/brcm/bcm63268.dtsi\n@@ -70,6 +70,12 @@\n \t\t\tmask = <0x1>;\n \t\t};\n \n+\t\tperiph_rst: reset-controller@10000010 {\n+\t\t\tcompatible = \"brcm,bcm6345-reset\";\n+\t\t\treg = <0x10000010 0x4>;\n+\t\t\t#reset-cells = <1>;\n+\t\t};\n+\n \t\tperiph_intc: interrupt-controller@10000020 {\n \t\t\tcompatible = \"brcm,bcm6345-l1-intc\";\n \t\t\treg = <0x10000020 0x20>,\n--- /dev/null\n+++ b/include/dt-bindings/reset/bcm63268-reset.h\n@@ -0,0 +1,26 @@\n+/* SPDX-License-Identifier: GPL-2.0+ */\n+\n+#ifndef __DT_BINDINGS_RESET_BCM63268_H\n+#define __DT_BINDINGS_RESET_BCM63268_H\n+\n+#define BCM63268_RST_SPI\t0\n+#define BCM63268_RST_IPSEC\t1\n+#define BCM63268_RST_EPHY\t2\n+#define BCM63268_RST_SAR\t3\n+#define BCM63268_RST_ENETSW\t4\n+#define BCM63268_RST_USBS\t5\n+#define BCM63268_RST_USBH\t6\n+#define BCM63268_RST_PCM\t7\n+#define BCM63268_RST_PCIE_CORE\t8\n+#define BCM63268_RST_PCIE\t9\n+#define BCM63268_RST_PCIE_EXT\t10\n+#define BCM63268_RST_WLAN_SHIM\t11\n+#define BCM63268_RST_DDR_PHY\t12\n+#define BCM63268_RST_FAP0\t13\n+#define BCM63268_RST_WLAN_UBUS\t14\n+#define BCM63268_RST_DECT\t15\n+#define BCM63268_RST_FAP1\t16\n+#define BCM63268_RST_PCIE_HARD\t17\n+#define BCM63268_RST_GPHY\t18\n+\n+#endif /* __DT_BINDINGS_RESET_BCM63268_H */\n"
  },
  {
    "path": "target/linux/bmips/patches-5.10/009-v5.11-mips-bmips-add-BCM6318-reset-controller-definitions.patch",
    "content": "From 8c9e8b0a28225c46f2cca0a09a3a111bb043e874 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com>\nDate: Wed, 17 Jun 2020 12:50:41 +0200\nSubject: [PATCH 9/9] mips: bmips: add BCM6318 reset controller definitions\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nBCM6318 SoCs have a reset controller for certain components.\n\nSigned-off-by: Álvaro Fernández Rojas <noltari@gmail.com>\nAcked-by: Florian Fainelli <F.fainelli@gmail.com>\nReviewed-by: Rob Herring <robh@kernel.org>\nSigned-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>\n---\n include/dt-bindings/reset/bcm6318-reset.h | 20 ++++++++++++++++++++\n 1 file changed, 20 insertions(+)\n create mode 100644 include/dt-bindings/reset/bcm6318-reset.h\n\n--- /dev/null\n+++ b/include/dt-bindings/reset/bcm6318-reset.h\n@@ -0,0 +1,20 @@\n+/* SPDX-License-Identifier: GPL-2.0+ */\n+\n+#ifndef __DT_BINDINGS_RESET_BCM6318_H\n+#define __DT_BINDINGS_RESET_BCM6318_H\n+\n+#define BCM6318_RST_SPI\t\t0\n+#define BCM6318_RST_EPHY\t1\n+#define BCM6318_RST_SAR\t\t2\n+#define BCM6318_RST_ENETSW\t3\n+#define BCM6318_RST_USBD\t4\n+#define BCM6318_RST_USBH\t5\n+#define BCM6318_RST_PCIE_CORE\t6\n+#define BCM6318_RST_PCIE\t7\n+#define BCM6318_RST_PCIE_EXT\t8\n+#define BCM6318_RST_PCIE_HARD\t9\n+#define BCM6318_RST_ADSL\t10\n+#define BCM6318_RST_PHYMIPS\t11\n+#define BCM6318_RST_HOSTMIPS\t12\n+\n+#endif /* __DT_BINDINGS_RESET_BCM6318_H */\n"
  },
  {
    "path": "target/linux/bmips/patches-5.10/020-v5.12-mips-bmips-init-clocks-earlier.patch",
    "content": "From faf3c25e51a7e91b69ea26da72c74a8786af7968 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com>\nDate: Mon, 22 Feb 2021 21:33:50 +0100\nSubject: [PATCH] mips: bmips: init clocks earlier\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\ndevice_initcall() is too late for bcm63xx.\nWe need to call of_clk_init() earlier in order to properly boot.\n\nSigned-off-by: Álvaro Fernández Rojas <noltari@gmail.com>\nSigned-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>\n---\n arch/mips/bmips/setup.c | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/arch/mips/bmips/setup.c\n+++ b/arch/mips/bmips/setup.c\n@@ -201,4 +201,4 @@ static int __init plat_dev_init(void)\n \treturn 0;\n }\n \n-device_initcall(plat_dev_init);\n+arch_initcall(plat_dev_init);\n"
  },
  {
    "path": "target/linux/bmips/patches-5.10/021-v5.12-spi-bcm63xx-spi-fix-pm_runtime.patch",
    "content": "From 73ae625da5c36300fccd809738e7c68f49ebce35 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com>\nDate: Tue, 23 Feb 2021 16:18:50 +0100\nSubject: [PATCH 1/2] spi: bcm63xx-spi: fix pm_runtime\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nThe driver sets auto_runtime_pm to true, but it doesn't call\npm_runtime_enable(), which results in \"Failed to power device\" when PM support\nis enabled.\n\nSigned-off-by: Álvaro Fernández Rojas <noltari@gmail.com>\nLink: https://lore.kernel.org/r/20210223151851.4110-2-noltari@gmail.com\nSigned-off-by: Mark Brown <broonie@kernel.org>\n---\n drivers/spi/spi-bcm63xx.c | 6 +++++-\n 1 file changed, 5 insertions(+), 1 deletion(-)\n\n--- a/drivers/spi/spi-bcm63xx.c\n+++ b/drivers/spi/spi-bcm63xx.c\n@@ -593,11 +593,13 @@ static int bcm63xx_spi_probe(struct plat\n \n \tbcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS);\n \n+\tpm_runtime_enable(&pdev->dev);\n+\n \t/* register and we are done */\n \tret = devm_spi_register_master(dev, master);\n \tif (ret) {\n \t\tdev_err(dev, \"spi register failed\\n\");\n-\t\tgoto out_clk_disable;\n+\t\tgoto out_pm_disable;\n \t}\n \n \tdev_info(dev, \"at %pr (irq %d, FIFOs size %d)\\n\",\n@@ -605,6 +607,8 @@ static int bcm63xx_spi_probe(struct plat\n \n \treturn 0;\n \n+out_pm_disable:\n+\tpm_runtime_disable(&pdev->dev);\n out_clk_disable:\n \tclk_disable_unprepare(clk);\n out_err:\n"
  },
  {
    "path": "target/linux/bmips/patches-5.10/022-v5.12-spi-bcm63xx-hsspi-fix-pm_runtime.patch",
    "content": "From 216e8e80057a9f0b6366327881acf88eaf9f1fd4 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com>\nDate: Tue, 23 Feb 2021 16:18:51 +0100\nSubject: [PATCH 2/2] spi: bcm63xx-hsspi: fix pm_runtime\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nThe driver sets auto_runtime_pm to true, but it doesn't call\npm_runtime_enable(), which results in \"Failed to power device\" when PM support\nis enabled.\n\nSigned-off-by: Álvaro Fernández Rojas <noltari@gmail.com>\nLink: https://lore.kernel.org/r/20210223151851.4110-3-noltari@gmail.com\nSigned-off-by: Mark Brown <broonie@kernel.org>\n---\n drivers/spi/spi-bcm63xx-hsspi.c | 7 ++++++-\n 1 file changed, 6 insertions(+), 1 deletion(-)\n\n--- a/drivers/spi/spi-bcm63xx-hsspi.c\n+++ b/drivers/spi/spi-bcm63xx-hsspi.c\n@@ -21,6 +21,7 @@\n #include <linux/mutex.h>\n #include <linux/of.h>\n #include <linux/reset.h>\n+#include <linux/pm_runtime.h>\n \n #define HSSPI_GLOBAL_CTRL_REG\t\t\t0x0\n #define GLOBAL_CTRL_CS_POLARITY_SHIFT\t\t0\n@@ -439,13 +440,17 @@ static int bcm63xx_hsspi_probe(struct pl\n \tif (ret)\n \t\tgoto out_put_master;\n \n+\tpm_runtime_enable(&pdev->dev);\n+\n \t/* register and we are done */\n \tret = devm_spi_register_master(dev, master);\n \tif (ret)\n-\t\tgoto out_put_master;\n+\t\tgoto out_pm_disable;\n \n \treturn 0;\n \n+out_pm_disable:\n+\tpm_runtime_disable(&pdev->dev);\n out_put_master:\n \tspi_master_put(master);\n out_disable_pll_clk:\n"
  },
  {
    "path": "target/linux/bmips/patches-5.10/040-v5.13-mips-smp-bmips-fix-CPU-mappings.patch",
    "content": "From c0f41a0dac1f3db6c40aabc0f3ac8868709ba6a6 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com>\nDate: Wed, 24 Feb 2021 08:33:36 +0100\nSubject: [PATCH] mips: smp-bmips: fix CPU mappings\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nWhen booting bmips with SMP enabled on a BCM6358 running on CPU #1 instead of\nCPU #0, the current CPU mapping code produces the following:\n- smp_processor_id(): 0\n- cpu_logical_map(0): 1\n- cpu_number_map(0): 1\n\nThis is because SMP isn't supported on BCM6358 since it has a shared TLB, so\nit is disabled and max_cpus is decreased from 2 to 1.\n\nSigned-off-by: Álvaro Fernández Rojas <noltari@gmail.com>\nReviewed-by: Florian Fainelli <f.fainelli@gmail.com>\nSigned-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>\n---\n arch/mips/kernel/smp-bmips.c | 27 +++++++++++++++++----------\n 1 file changed, 17 insertions(+), 10 deletions(-)\n\n--- a/arch/mips/kernel/smp-bmips.c\n+++ b/arch/mips/kernel/smp-bmips.c\n@@ -134,17 +134,24 @@ static void __init bmips_smp_setup(void)\n \tif (!board_ebase_setup)\n \t\tboard_ebase_setup = &bmips_ebase_setup;\n \n-\t__cpu_number_map[boot_cpu] = 0;\n-\t__cpu_logical_map[0] = boot_cpu;\n+\tif (max_cpus > 1) {\n+\t\t__cpu_number_map[boot_cpu] = 0;\n+\t\t__cpu_logical_map[0] = boot_cpu;\n \n-\tfor (i = 0; i < max_cpus; i++) {\n-\t\tif (i != boot_cpu) {\n-\t\t\t__cpu_number_map[i] = cpu;\n-\t\t\t__cpu_logical_map[cpu] = i;\n-\t\t\tcpu++;\n+\t\tfor (i = 0; i < max_cpus; i++) {\n+\t\t\tif (i != boot_cpu) {\n+\t\t\t\t__cpu_number_map[i] = cpu;\n+\t\t\t\t__cpu_logical_map[cpu] = i;\n+\t\t\t\tcpu++;\n+\t\t\t}\n+\t\t\tset_cpu_possible(i, 1);\n+\t\t\tset_cpu_present(i, 1);\n \t\t}\n-\t\tset_cpu_possible(i, 1);\n-\t\tset_cpu_present(i, 1);\n+\t} else {\n+\t\t__cpu_number_map[0] = boot_cpu;\n+\t\t__cpu_logical_map[0] = 0;\n+\t\tset_cpu_possible(0, 1);\n+\t\tset_cpu_present(0, 1);\n \t}\n }\n \n"
  },
  {
    "path": "target/linux/bmips/patches-5.10/042-v5.13-dt-bindings-rng-bcm2835-add-clock-constraints.patch",
    "content": "From 0618e07ea3e0981d7765b43d3f7db39e739842eb Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com>\nDate: Fri, 5 Mar 2021 08:01:30 +0100\nSubject: [PATCH 1/3] dt-bindings: rng: bcm2835: add clock constraints\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nbrcm,bcm6368-rng controllers require enabling the IPSEC clock in order to get\na functional RNG.\n\nSigned-off-by: Álvaro Fernández Rojas <noltari@gmail.com>\nReviewed-by: Rob Herring <robh@kernel.org>\nAcked-by: Florian Fainelli <f.fainelli@gmail.com>\nSigned-off-by: Herbert Xu <herbert@gondor.apana.org.au>\n---\n .../devicetree/bindings/rng/brcm,bcm2835.yaml          | 10 ++++++++++\n 1 file changed, 10 insertions(+)\n\n--- a/Documentation/devicetree/bindings/rng/brcm,bcm2835.yaml\n+++ b/Documentation/devicetree/bindings/rng/brcm,bcm2835.yaml\n@@ -35,6 +35,16 @@ required:\n   - compatible\n   - reg\n \n+if:\n+  properties:\n+    compatible:\n+      enum:\n+        - brcm,bcm6368-rng\n+then:\n+  required:\n+    - clocks\n+    - clock-names\n+\n additionalProperties: false\n \n examples:\n"
  },
  {
    "path": "target/linux/bmips/patches-5.10/043-v5.13-dt-bindings-rng-bcm2835-document-reset-support.patch",
    "content": "From 381345820db55bf8e7289de047c24c00a2e3690d Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com>\nDate: Fri, 5 Mar 2021 08:01:31 +0100\nSubject: [PATCH 2/3] dt-bindings: rng: bcm2835: document reset support\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nbrcm,bcm6368-rng controllers require resetting the IPSEC clock in order to get\na functional RNG.\n\nSigned-off-by: Álvaro Fernández Rojas <noltari@gmail.com>\nReviewed-by: Rob Herring <robh@kernel.org>\nAcked-by: Florian Fainelli <f.fainelli@gmail.com>\nSigned-off-by: Herbert Xu <herbert@gondor.apana.org.au>\n---\n .../devicetree/bindings/rng/brcm,bcm2835.yaml         | 11 +++++++++++\n 1 file changed, 11 insertions(+)\n\n--- a/Documentation/devicetree/bindings/rng/brcm,bcm2835.yaml\n+++ b/Documentation/devicetree/bindings/rng/brcm,bcm2835.yaml\n@@ -28,6 +28,12 @@ properties:\n   clock-names:\n     const: ipsec\n \n+  resets:\n+    maxItems: 1\n+\n+  reset-names:\n+    const: ipsec\n+\n   interrupts:\n     maxItems: 1\n \n@@ -44,6 +50,8 @@ then:\n   required:\n     - clocks\n     - clock-names\n+    - resets\n+    - reset-names\n \n additionalProperties: false\n \n@@ -68,4 +76,7 @@ examples:\n \n         clocks = <&periph_clk 18>;\n         clock-names = \"ipsec\";\n+\n+        resets = <&periph_rst 4>;\n+        reset-names = \"ipsec\";\n     };\n"
  },
  {
    "path": "target/linux/bmips/patches-5.10/044-v5.13-hwrng-bcm2835-add-reset-support.patch",
    "content": "From e5f9f41d5e62004c913bfd4ddf06abe032f5ce1c Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com>\nDate: Fri, 5 Mar 2021 08:01:32 +0100\nSubject: [PATCH 3/3] hwrng: bcm2835 - add reset support\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nBCM6368 devices need to reset the IPSEC controller in order to generate true\nrandom numbers.\n\nThis is what BCM6368 produces without a reset:\nroot@OpenWrt:/# cat /dev/hwrng | rngtest -c 1000\nrngtest 6.10\nCopyright (c) 2004 by Henrique de Moraes Holschuh\nThis is free software; see the source for copying conditions.  There is NO warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.\n\nrngtest: starting FIPS tests...\nrngtest: bits received from input: 20000032\nrngtest: FIPS 140-2 successes: 0\nrngtest: FIPS 140-2 failures: 1000\nrngtest: FIPS 140-2(2001-10-10) Monobit: 2\nrngtest: FIPS 140-2(2001-10-10) Poker: 1000\nrngtest: FIPS 140-2(2001-10-10) Runs: 1000\nrngtest: FIPS 140-2(2001-10-10) Long run: 30\nrngtest: FIPS 140-2(2001-10-10) Continuous run: 0\nrngtest: input channel speed: (min=37.253; avg=320.827; max=635.783)Mibits/s\nrngtest: FIPS tests speed: (min=12.141; avg=15.034; max=16.428)Mibits/s\nrngtest: Program run time: 1336176 microseconds\n\nSigned-off-by: Álvaro Fernández Rojas <noltari@gmail.com>\nReviewed-by: Philipp Zabel <p.zabel@pengutronix.de>\nAcked-by: Florian Fainelli <f.fainelli@gmail.com>\nSigned-off-by: Herbert Xu <herbert@gondor.apana.org.au>\n---\n drivers/char/hw_random/bcm2835-rng.c | 10 ++++++++++\n 1 file changed, 10 insertions(+)\n\n--- a/drivers/char/hw_random/bcm2835-rng.c\n+++ b/drivers/char/hw_random/bcm2835-rng.c\n@@ -13,6 +13,7 @@\n #include <linux/platform_device.h>\n #include <linux/printk.h>\n #include <linux/clk.h>\n+#include <linux/reset.h>\n \n #define RNG_CTRL\t0x0\n #define RNG_STATUS\t0x4\n@@ -32,6 +33,7 @@ struct bcm2835_rng_priv {\n \tvoid __iomem *base;\n \tbool mask_interrupts;\n \tstruct clk *clk;\n+\tstruct reset_control *reset;\n };\n \n static inline struct bcm2835_rng_priv *to_rng_priv(struct hwrng *rng)\n@@ -94,6 +96,10 @@ static int bcm2835_rng_init(struct hwrng\n \t\t\treturn ret;\n \t}\n \n+\tret = reset_control_reset(priv->reset);\n+\tif (ret)\n+\t\treturn ret;\n+\n \tif (priv->mask_interrupts) {\n \t\t/* mask the interrupt */\n \t\tval = rng_readl(priv, RNG_INT_MASK);\n@@ -159,6 +165,10 @@ static int bcm2835_rng_probe(struct plat\n \tif (PTR_ERR(priv->clk) == -EPROBE_DEFER)\n \t\treturn -EPROBE_DEFER;\n \n+\tpriv->reset = devm_reset_control_get_optional_exclusive(dev, NULL);\n+\tif (IS_ERR(priv->reset))\n+\t\treturn PTR_ERR(priv->reset);\n+\n \tpriv->rng.name = pdev->name;\n \tpriv->rng.init = bcm2835_rng_init;\n \tpriv->rng.read = bcm2835_rng_read;\n"
  },
  {
    "path": "target/linux/bmips/patches-5.10/046-v5.13-dt-bindings-net-Add-bcm6368-mdio-mux-bindings.patch",
    "content": "From da6557edb9f3f4513b01d9a20a36c2fbc31810a1 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com>\nDate: Mon, 15 Mar 2021 16:45:27 +0100\nSubject: [PATCH 1/2] dt-bindings: net: Add bcm6368-mdio-mux bindings\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nAdd documentations for bcm6368 mdio mux driver.\n\nSigned-off-by: Álvaro Fernández Rojas <noltari@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n .../bindings/net/brcm,bcm6368-mdio-mux.yaml   | 76 +++++++++++++++++++\n 1 file changed, 76 insertions(+)\n create mode 100644 Documentation/devicetree/bindings/net/brcm,bcm6368-mdio-mux.yaml\n\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/net/brcm,bcm6368-mdio-mux.yaml\n@@ -0,0 +1,76 @@\n+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause\n+%YAML 1.2\n+---\n+$id: http://devicetree.org/schemas/net/brcm,bcm6368-mdio-mux.yaml#\n+$schema: http://devicetree.org/meta-schemas/core.yaml#\n+\n+title: Broadcom BCM6368 MDIO bus multiplexer\n+\n+maintainers:\n+  - Álvaro Fernández Rojas <noltari@gmail.com>\n+\n+description:\n+  This MDIO bus multiplexer defines buses that could be internal as well as\n+  external to SoCs. When child bus is selected, one needs to select these two\n+  properties as well to generate desired MDIO transaction on appropriate bus.\n+\n+allOf:\n+  - $ref: \"mdio.yaml#\"\n+\n+properties:\n+  compatible:\n+    const: brcm,bcm6368-mdio-mux\n+\n+  \"#address-cells\":\n+    const: 1\n+\n+  \"#size-cells\":\n+    const: 0\n+\n+  reg:\n+    maxItems: 1\n+\n+required:\n+  - compatible\n+  - reg\n+\n+patternProperties:\n+  '^mdio@[0-1]$':\n+    type: object\n+    properties:\n+      reg:\n+        maxItems: 1\n+\n+      \"#address-cells\":\n+        const: 1\n+\n+      \"#size-cells\":\n+        const: 0\n+\n+    required:\n+      - reg\n+      - \"#address-cells\"\n+      - \"#size-cells\"\n+\n+unevaluatedProperties: false\n+\n+examples:\n+  - |\n+    mdio0: mdio@10e000b0 {\n+      #address-cells = <1>;\n+      #size-cells = <0>;\n+      compatible = \"brcm,bcm6368-mdio-mux\";\n+      reg = <0x10e000b0 0x6>;\n+\n+      mdio_int: mdio@0 {\n+        #address-cells = <1>;\n+        #size-cells = <0>;\n+        reg = <0>;\n+      };\n+\n+      mdio_ext: mdio@1 {\n+        #address-cells = <1>;\n+        #size-cells = <0>;\n+        reg = <1>;\n+      };\n+    };\n"
  },
  {
    "path": "target/linux/bmips/patches-5.10/047-v5.13-net-mdio-Add-BCM6368-MDIO-mux-bus-controller.patch",
    "content": "From e239756717b5c866958823a1609e2ccf268435be Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com>\nDate: Mon, 15 Mar 2021 16:45:28 +0100\nSubject: [PATCH 2/2] net: mdio: Add BCM6368 MDIO mux bus controller\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nThis controller is present on BCM6318, BCM6328, BCM6362, BCM6368 and BCM63268\nSoCs.\n\nSigned-off-by: Álvaro Fernández Rojas <noltari@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/mdio/Kconfig            |  11 ++\n drivers/net/mdio/Makefile           |   1 +\n drivers/net/mdio/mdio-mux-bcm6368.c | 184 ++++++++++++++++++++++++++++\n 3 files changed, 196 insertions(+)\n create mode 100644 drivers/net/mdio/mdio-mux-bcm6368.c\n\n--- a/drivers/net/mdio/Kconfig\n+++ b/drivers/net/mdio/Kconfig\n@@ -200,6 +200,17 @@ config MDIO_BUS_MUX_MESON_G12A\n \t  the amlogic g12a SoC. The multiplexers connects either the external\n \t  or the internal MDIO bus to the parent bus.\n \n+config MDIO_BUS_MUX_BCM6368\n+\ttristate \"Broadcom BCM6368 MDIO bus multiplexers\"\n+\tdepends on OF && OF_MDIO && (BMIPS_GENERIC || COMPILE_TEST)\n+\tselect MDIO_BUS_MUX\n+\tdefault BMIPS_GENERIC\n+\thelp\n+\t  This module provides a driver for MDIO bus multiplexers found in\n+\t  BCM6368 based Broadcom SoCs. This multiplexer connects one of several\n+\t  child MDIO bus to a parent bus. Buses could be internal as well as\n+\t  external and selection logic lies inside the same multiplexer.\n+\n config MDIO_BUS_MUX_BCM_IPROC\n \ttristate \"Broadcom iProc based MDIO bus multiplexers\"\n \tdepends on OF && OF_MDIO && (ARCH_BCM_IPROC || COMPILE_TEST)\n--- a/drivers/net/mdio/Makefile\n+++ b/drivers/net/mdio/Makefile\n@@ -22,6 +22,7 @@ obj-$(CONFIG_MDIO_THUNDER)\t\t+= mdio-thun\n obj-$(CONFIG_MDIO_XGENE)\t\t+= mdio-xgene.o\n \n obj-$(CONFIG_MDIO_BUS_MUX)\t\t+= mdio-mux.o\n+obj-$(CONFIG_MDIO_BUS_MUX_BCM6368)\t+= mdio-mux-bcm6368.o\n obj-$(CONFIG_MDIO_BUS_MUX_BCM_IPROC)\t+= mdio-mux-bcm-iproc.o\n obj-$(CONFIG_MDIO_BUS_MUX_GPIO)\t\t+= mdio-mux-gpio.o\n obj-$(CONFIG_MDIO_BUS_MUX_MESON_G12A)\t+= mdio-mux-meson-g12a.o\n--- /dev/null\n+++ b/drivers/net/mdio/mdio-mux-bcm6368.c\n@@ -0,0 +1,184 @@\n+// SPDX-License-Identifier: GPL-2.0+\n+/*\n+ * Broadcom BCM6368 mdiomux bus controller driver\n+ *\n+ * Copyright (C) 2021 Álvaro Fernández Rojas <noltari@gmail.com>\n+ */\n+\n+#include <linux/delay.h>\n+#include <linux/io.h>\n+#include <linux/kernel.h>\n+#include <linux/mdio-mux.h>\n+#include <linux/module.h>\n+#include <linux/of.h>\n+#include <linux/of_platform.h>\n+#include <linux/of_mdio.h>\n+#include <linux/phy.h>\n+#include <linux/platform_device.h>\n+#include <linux/sched.h>\n+\n+#define MDIOC_REG\t\t0x0\n+#define MDIOC_EXT_MASK\t\tBIT(16)\n+#define MDIOC_REG_SHIFT\t\t20\n+#define MDIOC_PHYID_SHIFT\t25\n+#define MDIOC_RD_MASK\t\tBIT(30)\n+#define MDIOC_WR_MASK\t\tBIT(31)\n+\n+#define MDIOD_REG\t\t0x4\n+\n+struct bcm6368_mdiomux_desc {\n+\tvoid *mux_handle;\n+\tvoid __iomem *base;\n+\tstruct device *dev;\n+\tstruct mii_bus *mii_bus;\n+\tint ext_phy;\n+};\n+\n+static int bcm6368_mdiomux_read(struct mii_bus *bus, int phy_id, int loc)\n+{\n+\tstruct bcm6368_mdiomux_desc *md = bus->priv;\n+\tuint32_t reg;\n+\tint ret;\n+\n+\t__raw_writel(0, md->base + MDIOC_REG);\n+\n+\treg = MDIOC_RD_MASK |\n+\t      (phy_id << MDIOC_PHYID_SHIFT) |\n+\t      (loc << MDIOC_REG_SHIFT);\n+\tif (md->ext_phy)\n+\t\treg |= MDIOC_EXT_MASK;\n+\n+\t__raw_writel(reg, md->base + MDIOC_REG);\n+\tudelay(50);\n+\tret = __raw_readw(md->base + MDIOD_REG);\n+\n+\treturn ret;\n+}\n+\n+static int bcm6368_mdiomux_write(struct mii_bus *bus, int phy_id, int loc,\n+\t\t\t\t uint16_t val)\n+{\n+\tstruct bcm6368_mdiomux_desc *md = bus->priv;\n+\tuint32_t reg;\n+\n+\t__raw_writel(0, md->base + MDIOC_REG);\n+\n+\treg = MDIOC_WR_MASK |\n+\t      (phy_id << MDIOC_PHYID_SHIFT) |\n+\t      (loc << MDIOC_REG_SHIFT);\n+\tif (md->ext_phy)\n+\t\treg |= MDIOC_EXT_MASK;\n+\treg |= val;\n+\n+\t__raw_writel(reg, md->base + MDIOC_REG);\n+\tudelay(50);\n+\n+\treturn 0;\n+}\n+\n+static int bcm6368_mdiomux_switch_fn(int current_child, int desired_child,\n+\t\t\t\t     void *data)\n+{\n+\tstruct bcm6368_mdiomux_desc *md = data;\n+\n+\tmd->ext_phy = desired_child;\n+\n+\treturn 0;\n+}\n+\n+static int bcm6368_mdiomux_probe(struct platform_device *pdev)\n+{\n+\tstruct bcm6368_mdiomux_desc *md;\n+\tstruct mii_bus *bus;\n+\tstruct resource *res;\n+\tint rc;\n+\n+\tmd = devm_kzalloc(&pdev->dev, sizeof(*md), GFP_KERNEL);\n+\tif (!md)\n+\t\treturn -ENOMEM;\n+\tmd->dev = &pdev->dev;\n+\n+\tres = platform_get_resource(pdev, IORESOURCE_MEM, 0);\n+\tif (!res)\n+\t\treturn -EINVAL;\n+\n+\t/*\n+\t * Just ioremap, as this MDIO block is usually integrated into an\n+\t * Ethernet MAC controller register range\n+\t */\n+\tmd->base = devm_ioremap(&pdev->dev, res->start, resource_size(res));\n+\tif (!md->base) {\n+\t\tdev_err(&pdev->dev, \"failed to ioremap register\\n\");\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\tmd->mii_bus = devm_mdiobus_alloc(&pdev->dev);\n+\tif (!md->mii_bus) {\n+\t\tdev_err(&pdev->dev, \"mdiomux bus alloc failed\\n\");\n+\t\treturn ENOMEM;\n+\t}\n+\n+\tbus = md->mii_bus;\n+\tbus->priv = md;\n+\tbus->name = \"BCM6368 MDIO mux bus\";\n+\tsnprintf(bus->id, MII_BUS_ID_SIZE, \"%s-%d\", pdev->name, pdev->id);\n+\tbus->parent = &pdev->dev;\n+\tbus->read = bcm6368_mdiomux_read;\n+\tbus->write = bcm6368_mdiomux_write;\n+\tbus->phy_mask = 0x3f;\n+\tbus->dev.of_node = pdev->dev.of_node;\n+\n+\trc = mdiobus_register(bus);\n+\tif (rc) {\n+\t\tdev_err(&pdev->dev, \"mdiomux registration failed\\n\");\n+\t\treturn rc;\n+\t}\n+\n+\tplatform_set_drvdata(pdev, md);\n+\n+\trc = mdio_mux_init(md->dev, md->dev->of_node,\n+\t\t\t   bcm6368_mdiomux_switch_fn, &md->mux_handle, md,\n+\t\t\t   md->mii_bus);\n+\tif (rc) {\n+\t\tdev_info(md->dev, \"mdiomux initialization failed\\n\");\n+\t\tgoto out_register;\n+\t}\n+\n+\tdev_info(&pdev->dev, \"Broadcom BCM6368 MDIO mux bus\\n\");\n+\n+\treturn 0;\n+\n+out_register:\n+\tmdiobus_unregister(bus);\n+\treturn rc;\n+}\n+\n+static int bcm6368_mdiomux_remove(struct platform_device *pdev)\n+{\n+\tstruct bcm6368_mdiomux_desc *md = platform_get_drvdata(pdev);\n+\n+\tmdio_mux_uninit(md->mux_handle);\n+\tmdiobus_unregister(md->mii_bus);\n+\n+\treturn 0;\n+}\n+\n+static const struct of_device_id bcm6368_mdiomux_ids[] = {\n+\t{ .compatible = \"brcm,bcm6368-mdio-mux\", },\n+\t{ /* sentinel */ }\n+};\n+MODULE_DEVICE_TABLE(of, bcm6368_mdiomux_ids);\n+\n+static struct platform_driver bcm6368_mdiomux_driver = {\n+\t.driver = {\n+\t\t.name = \"bcm6368-mdio-mux\",\n+\t\t.of_match_table = bcm6368_mdiomux_ids,\n+\t},\n+\t.probe\t= bcm6368_mdiomux_probe,\n+\t.remove\t= bcm6368_mdiomux_remove,\n+};\n+module_platform_driver(bcm6368_mdiomux_driver);\n+\n+MODULE_AUTHOR(\"Álvaro Fernández Rojas <noltari@gmail.com>\");\n+MODULE_DESCRIPTION(\"BCM6368 mdiomux bus controller driver\");\n+MODULE_LICENSE(\"GPL v2\");\n"
  },
  {
    "path": "target/linux/bmips/patches-5.10/053-v5.13-gpio-regmap-set-gpio_chip-of_node.patch",
    "content": "From d46bf9ec4596654f36245e3b14765bcb422be6ad Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com>\nDate: Wed, 24 Mar 2021 09:19:03 +0100\nSubject: [PATCH 02/22] gpio: regmap: set gpio_chip of_node\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nThis is needed for properly registering GPIO regmap as a child of a regmap\npin controller.\n\nSigned-off-by: Álvaro Fernández Rojas <noltari@gmail.com>\nReviewed-by: Michael Walle <michael@walle.cc>\nReviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>\nAcked-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>\nLink: https://lore.kernel.org/r/20210324081923.20379-3-noltari@gmail.com\nSigned-off-by: Linus Walleij <linus.walleij@linaro.org>\n---\n drivers/gpio/gpio-regmap.c  | 5 +++++\n include/linux/gpio/regmap.h | 4 ++++\n 2 files changed, 9 insertions(+)\n\n--- a/drivers/gpio/gpio-regmap.c\n+++ b/drivers/gpio/gpio-regmap.c\n@@ -254,6 +254,11 @@ struct gpio_regmap *gpio_regmap_register\n \tchip->names = config->names;\n \tchip->label = config->label ?: dev_name(config->parent);\n \n+#if defined(CONFIG_OF_GPIO)\n+\t/* gpiolib will use of_node of the parent if chip->of_node is NULL */\n+\tchip->of_node = to_of_node(config->fwnode);\n+#endif /* CONFIG_OF_GPIO */\n+\n \t/*\n \t * If our regmap is fast_io we should probably set can_sleep to false.\n \t * Right now, the regmap doesn't save this property, nor is there any\n--- a/include/linux/gpio/regmap.h\n+++ b/include/linux/gpio/regmap.h\n@@ -4,6 +4,7 @@\n #define _LINUX_GPIO_REGMAP_H\n \n struct device;\n+struct fwnode_handle;\n struct gpio_regmap;\n struct irq_domain;\n struct regmap;\n@@ -16,6 +17,8 @@ struct regmap;\n  * @parent:\t\tThe parent device\n  * @regmap:\t\tThe regmap used to access the registers\n  *\t\t\tgiven, the name of the device is used\n+ * @fwnode:\t\t(Optional) The firmware node.\n+ *\t\t\tIf not given, the fwnode of the parent is used.\n  * @label:\t\t(Optional) Descriptive name for GPIO controller.\n  *\t\t\tIf not given, the name of the device is used.\n  * @ngpio:\t\tNumber of GPIOs\n@@ -57,6 +60,7 @@ struct regmap;\n struct gpio_regmap_config {\n \tstruct device *parent;\n \tstruct regmap *regmap;\n+\tstruct fwnode_handle *fwnode;\n \n \tconst char *label;\n \tint ngpio;\n"
  },
  {
    "path": "target/linux/bmips/patches-5.10/054-v5.13-dt-bindings-improve-BCM6345-GPIO-binding-documentati.patch",
    "content": "From fb9da17bd26552f48cda4f2f658379e7f5860691 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com>\nDate: Wed, 24 Mar 2021 09:19:04 +0100\nSubject: [PATCH 03/22] dt-bindings: improve BCM6345 GPIO binding documentation\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nConvert existing BCM6345 GPIO binding documentation to YAML and add binding\ndocumentation for the GPIO controller found in BCM6318, BCM6328, BCM6358,\nBCM6362, BCM6368 and BCM63268 SoCs.\n\nCo-developed-by: Jonas Gorski <jonas.gorski@gmail.com>\nSigned-off-by: Jonas Gorski <jonas.gorski@gmail.com>\nSigned-off-by: Álvaro Fernández Rojas <noltari@gmail.com>\nReviewed-by: Rob Herring <robh@kernel.org>\nLink: https://lore.kernel.org/r/20210324081923.20379-4-noltari@gmail.com\nSigned-off-by: Linus Walleij <linus.walleij@linaro.org>\n---\n .../bindings/gpio/brcm,bcm6345-gpio.txt       | 46 ----------\n .../bindings/gpio/brcm,bcm6345-gpio.yaml      | 86 +++++++++++++++++++\n 2 files changed, 86 insertions(+), 46 deletions(-)\n delete mode 100644 Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.txt\n create mode 100644 Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.yaml\n\n--- a/Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.txt\n+++ /dev/null\n@@ -1,46 +0,0 @@\n-Bindings for the Broadcom's brcm,bcm6345-gpio memory-mapped GPIO controllers.\n-\n-These bindings can be used on any BCM63xx SoC. However, BCM6338 and BCM6345\n-are the only ones which don't need a pinctrl driver.\n-BCM6338 have 8-bit data and dirout registers, where GPIO state can be read\n-and/or written, and the direction changed from input to output.\n-BCM6345 have 16-bit data and dirout registers, where GPIO state can be read\n-and/or written, and the direction changed from input to output.\n-\n-Required properties:\n-\t- compatible: should be \"brcm,bcm6345-gpio\"\n-\t- reg-names: must contain\n-\t\t\"dat\" - data register\n-\t\t\"dirout\" - direction (output) register\n-\t- reg: address + size pairs describing the GPIO register sets;\n-\t\torder must correspond with the order of entries in reg-names\n-\t- #gpio-cells: must be set to 2. The first cell is the pin number and\n-\t\t\tthe second cell is used to specify the gpio polarity:\n-\t\t\t0 = active high\n-\t\t\t1 = active low\n-\t- gpio-controller: Marks the device node as a gpio controller.\n-\n-Optional properties:\n-\t- native-endian: use native endian memory.\n-\n-Examples:\n-\t- BCM6338:\n-\tgpio: gpio-controller@fffe0407 {\n-\t\tcompatible = \"brcm,bcm6345-gpio\";\n-\t\treg-names = \"dirout\", \"dat\";\n-\t\treg = <0xfffe0407 1>, <0xfffe040f 1>;\n-\n-\t\t#gpio-cells = <2>;\n-\t\tgpio-controller;\n-\t};\n-\n-\t- BCM6345:\n-\tgpio: gpio-controller@fffe0406 {\n-\t\tcompatible = \"brcm,bcm6345-gpio\";\n-\t\treg-names = \"dirout\", \"dat\";\n-\t\treg = <0xfffe0406 2>, <0xfffe040a 2>;\n-\t\tnative-endian;\n-\n-\t\t#gpio-cells = <2>;\n-\t\tgpio-controller;\n-\t};\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.yaml\n@@ -0,0 +1,86 @@\n+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause\n+%YAML 1.2\n+---\n+$id: http://devicetree.org/schemas/gpio/brcm,bcm6345-gpio.yaml#\n+$schema: http://devicetree.org/meta-schemas/core.yaml#\n+\n+title: Broadcom BCM6345 GPIO controller\n+\n+maintainers:\n+  - Álvaro Fernández Rojas <noltari@gmail.com>\n+  - Jonas Gorski <jonas.gorski@gmail.com>\n+\n+description: |+\n+  Bindings for Broadcom's BCM63xx memory-mapped GPIO controllers.\n+\n+  These bindings can be used on any BCM63xx SoC. However, BCM6338 and BCM6345\n+  are the only ones which don't need a pinctrl driver.\n+\n+  BCM6338 have 8-bit data and dirout registers, where GPIO state can be read\n+  and/or written, and the direction changed from input to output.\n+  BCM6345 have 16-bit data and dirout registers, where GPIO state can be read\n+  and/or written, and the direction changed from input to output.\n+  BCM6318, BCM6328, BCM6358, BCM6362, BCM6368 and BCM63268 have 32-bit data\n+  and dirout registers, where GPIO state can be read and/or written, and the\n+  direction changed from input to output.\n+\n+properties:\n+  compatible:\n+    enum:\n+      - brcm,bcm6318-gpio\n+      - brcm,bcm6328-gpio\n+      - brcm,bcm6345-gpio\n+      - brcm,bcm6358-gpio\n+      - brcm,bcm6362-gpio\n+      - brcm,bcm6368-gpio\n+      - brcm,bcm63268-gpio\n+\n+  gpio-controller: true\n+\n+  \"#gpio-cells\":\n+    const: 2\n+\n+  gpio-ranges:\n+    maxItems: 1\n+\n+  native-endian: true\n+\n+  reg:\n+    maxItems: 2\n+\n+  reg-names:\n+    items:\n+      - const: dirout\n+      - const: dat\n+\n+required:\n+  - compatible\n+  - reg\n+  - reg-names\n+  - gpio-controller\n+  - '#gpio-cells'\n+\n+additionalProperties: false\n+\n+examples:\n+  - |\n+    gpio@fffe0406 {\n+      compatible = \"brcm,bcm6345-gpio\";\n+      reg-names = \"dirout\", \"dat\";\n+      reg = <0xfffe0406 2>, <0xfffe040a 2>;\n+      native-endian;\n+\n+      gpio-controller;\n+      #gpio-cells = <2>;\n+    };\n+\n+  - |\n+    gpio@0 {\n+      compatible = \"brcm,bcm63268-gpio\";\n+      reg-names = \"dirout\", \"dat\";\n+      reg = <0x0 0x8>, <0x8 0x8>;\n+\n+      gpio-controller;\n+      gpio-ranges = <&pinctrl 0 0 52>;\n+      #gpio-cells = <2>;\n+    };\n"
  },
  {
    "path": "target/linux/bmips/patches-5.10/055-v5.13-pinctrl-bcm-add-bcm63xx-base-code.patch",
    "content": "From 132f95016db0a0a0659e99b471a7d3fd0c60f961 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com>\nDate: Wed, 24 Mar 2021 09:19:05 +0100\nSubject: [PATCH 04/22] pinctrl: bcm: add bcm63xx base code\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nAdd a helper for registering BCM63XX pin controllers.\n\nCo-developed-by: Jonas Gorski <jonas.gorski@gmail.com>\nSigned-off-by: Jonas Gorski <jonas.gorski@gmail.com>\nSigned-off-by: Álvaro Fernández Rojas <noltari@gmail.com>\nLink: https://lore.kernel.org/r/20210324081923.20379-5-noltari@gmail.com\nSigned-off-by: Linus Walleij <linus.walleij@linaro.org>\n---\n drivers/pinctrl/bcm/Kconfig           |   7 ++\n drivers/pinctrl/bcm/Makefile          |   1 +\n drivers/pinctrl/bcm/pinctrl-bcm63xx.c | 109 ++++++++++++++++++++++++++\n drivers/pinctrl/bcm/pinctrl-bcm63xx.h |  43 ++++++++++\n 4 files changed, 160 insertions(+)\n create mode 100644 drivers/pinctrl/bcm/pinctrl-bcm63xx.c\n create mode 100644 drivers/pinctrl/bcm/pinctrl-bcm63xx.h\n\n--- a/drivers/pinctrl/bcm/Kconfig\n+++ b/drivers/pinctrl/bcm/Kconfig\n@@ -29,6 +29,13 @@ config PINCTRL_BCM2835\n \thelp\n \t   Say Y here to enable the Broadcom BCM2835 GPIO driver.\n \n+config PINCTRL_BCM63XX\n+\tbool\n+\tselect GENERIC_PINCONF\n+\tselect GPIO_REGMAP\n+\tselect PINCONF\n+\tselect PINMUX\n+\n config PINCTRL_IPROC_GPIO\n \tbool \"Broadcom iProc GPIO (with PINCONF) driver\"\n \tdepends on OF_GPIO && (ARCH_BCM_IPROC || COMPILE_TEST)\n--- a/drivers/pinctrl/bcm/Makefile\n+++ b/drivers/pinctrl/bcm/Makefile\n@@ -3,6 +3,7 @@\n \n obj-$(CONFIG_PINCTRL_BCM281XX)\t\t+= pinctrl-bcm281xx.o\n obj-$(CONFIG_PINCTRL_BCM2835)\t\t+= pinctrl-bcm2835.o\n+obj-$(CONFIG_PINCTRL_BCM63XX)\t\t+= pinctrl-bcm63xx.o\n obj-$(CONFIG_PINCTRL_IPROC_GPIO)\t+= pinctrl-iproc-gpio.o\n obj-$(CONFIG_PINCTRL_CYGNUS_MUX)\t+= pinctrl-cygnus-mux.o\n obj-$(CONFIG_PINCTRL_NS)\t\t+= pinctrl-ns.o\n--- /dev/null\n+++ b/drivers/pinctrl/bcm/pinctrl-bcm63xx.c\n@@ -0,0 +1,109 @@\n+// SPDX-License-Identifier: GPL-2.0+\n+/*\n+ * Driver for BCM63xx GPIO unit (pinctrl + GPIO)\n+ *\n+ * Copyright (C) 2021 Álvaro Fernández Rojas <noltari@gmail.com>\n+ * Copyright (C) 2016 Jonas Gorski <jonas.gorski@gmail.com>\n+ */\n+\n+#include <linux/gpio/regmap.h>\n+#include <linux/mfd/syscon.h>\n+#include <linux/mod_devicetable.h>\n+#include <linux/of.h>\n+#include <linux/platform_device.h>\n+\n+#include \"pinctrl-bcm63xx.h\"\n+\n+#define BCM63XX_BANK_SIZE\t4\n+\n+#define BCM63XX_DIROUT_REG\t0x04\n+#define BCM63XX_DATA_REG\t0x0c\n+\n+static int bcm63xx_reg_mask_xlate(struct gpio_regmap *gpio,\n+\t\t\t\t  unsigned int base, unsigned int offset,\n+\t\t\t\t  unsigned int *reg, unsigned int *mask)\n+{\n+\tunsigned int line = offset % BCM63XX_BANK_GPIOS;\n+\tunsigned int stride = offset / BCM63XX_BANK_GPIOS;\n+\n+\t*reg = base - stride * BCM63XX_BANK_SIZE;\n+\t*mask = BIT(line);\n+\n+\treturn 0;\n+}\n+\n+static const struct of_device_id bcm63xx_gpio_of_match[] = {\n+\t{ .compatible = \"brcm,bcm6318-gpio\", },\n+\t{ .compatible = \"brcm,bcm6328-gpio\", },\n+\t{ .compatible = \"brcm,bcm6358-gpio\", },\n+\t{ .compatible = \"brcm,bcm6362-gpio\", },\n+\t{ .compatible = \"brcm,bcm6368-gpio\", },\n+\t{ .compatible = \"brcm,bcm63268-gpio\", },\n+\t{ /* sentinel */ }\n+};\n+\n+static int bcm63xx_gpio_probe(struct device *dev, struct device_node *node,\n+\t\t\t      const struct bcm63xx_pinctrl_soc *soc,\n+\t\t\t      struct bcm63xx_pinctrl *pc)\n+{\n+\tstruct gpio_regmap_config grc = {0};\n+\n+\tgrc.parent = dev;\n+\tgrc.fwnode = &node->fwnode;\n+\tgrc.ngpio = soc->ngpios;\n+\tgrc.ngpio_per_reg = BCM63XX_BANK_GPIOS;\n+\tgrc.regmap = pc->regs;\n+\tgrc.reg_dat_base = BCM63XX_DATA_REG;\n+\tgrc.reg_dir_out_base = BCM63XX_DIROUT_REG;\n+\tgrc.reg_set_base = BCM63XX_DATA_REG;\n+\tgrc.reg_mask_xlate = bcm63xx_reg_mask_xlate;\n+\n+\treturn PTR_ERR_OR_ZERO(devm_gpio_regmap_register(dev, &grc));\n+}\n+\n+int bcm63xx_pinctrl_probe(struct platform_device *pdev,\n+\t\t\t  const struct bcm63xx_pinctrl_soc *soc,\n+\t\t\t  void *driver_data)\n+{\n+\tstruct device *dev = &pdev->dev;\n+\tstruct bcm63xx_pinctrl *pc;\n+\tstruct device_node *node;\n+\tint err;\n+\n+\tpc = devm_kzalloc(dev, sizeof(*pc), GFP_KERNEL);\n+\tif (!pc)\n+\t\treturn -ENOMEM;\n+\n+\tplatform_set_drvdata(pdev, pc);\n+\n+\tpc->dev = dev;\n+\tpc->driver_data = driver_data;\n+\n+\tpc->regs = syscon_node_to_regmap(dev->parent->of_node);\n+\tif (IS_ERR(pc->regs))\n+\t\treturn PTR_ERR(pc->regs);\n+\n+\tpc->pctl_desc.name = dev_name(dev);\n+\tpc->pctl_desc.pins = soc->pins;\n+\tpc->pctl_desc.npins = soc->npins;\n+\tpc->pctl_desc.pctlops = soc->pctl_ops;\n+\tpc->pctl_desc.pmxops = soc->pmx_ops;\n+\tpc->pctl_desc.owner = THIS_MODULE;\n+\n+\tpc->pctl_dev = devm_pinctrl_register(dev, &pc->pctl_desc, pc);\n+\tif (IS_ERR(pc->pctl_dev))\n+\t\treturn PTR_ERR(pc->pctl_dev);\n+\n+\tfor_each_child_of_node(dev->parent->of_node, node) {\n+\t\tif (of_match_node(bcm63xx_gpio_of_match, node)) {\n+\t\t\terr = bcm63xx_gpio_probe(dev, node, soc, pc);\n+\t\t\tif (err) {\n+\t\t\t\tdev_err(dev, \"could not add GPIO chip\\n\");\n+\t\t\t\tof_node_put(node);\n+\t\t\t\treturn err;\n+\t\t\t}\n+\t\t}\n+\t}\n+\n+\treturn 0;\n+}\n--- /dev/null\n+++ b/drivers/pinctrl/bcm/pinctrl-bcm63xx.h\n@@ -0,0 +1,43 @@\n+// SPDX-License-Identifier: GPL-2.0+\n+/*\n+ * Copyright (C) 2021 Álvaro Fernández Rojas <noltari@gmail.com>\n+ * Copyright (C) 2016 Jonas Gorski <jonas.gorski@gmail.com>\n+ */\n+\n+#ifndef __PINCTRL_BCM63XX_H__\n+#define __PINCTRL_BCM63XX_H__\n+\n+#include <linux/pinctrl/pinctrl.h>\n+\n+#define BCM63XX_BANK_GPIOS 32\n+\n+struct bcm63xx_pinctrl_soc {\n+\tstruct pinctrl_ops *pctl_ops;\n+\tstruct pinmux_ops *pmx_ops;\n+\n+\tconst struct pinctrl_pin_desc *pins;\n+\tunsigned npins;\n+\n+\tunsigned int ngpios;\n+};\n+\n+struct bcm63xx_pinctrl {\n+\tstruct device *dev;\n+\tstruct regmap *regs;\n+\n+\tstruct pinctrl_desc pctl_desc;\n+\tstruct pinctrl_dev *pctl_dev;\n+\n+\tvoid *driver_data;\n+};\n+\n+static inline unsigned int bcm63xx_bank_pin(unsigned int pin)\n+{\n+\treturn pin % BCM63XX_BANK_GPIOS;\n+}\n+\n+int bcm63xx_pinctrl_probe(struct platform_device *pdev,\n+\t\t\t  const struct bcm63xx_pinctrl_soc *soc,\n+\t\t\t  void *driver_data);\n+\n+#endif /* __PINCTRL_BCM63XX_H__ */\n"
  },
  {
    "path": "target/linux/bmips/patches-5.10/056-v5.13-dt-bindings-add-BCM6328-pincontroller-binding-docume.patch",
    "content": "From 44dbcd8eb08a0febbb46ac7b9331f28a320bdf9a Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com>\nDate: Wed, 24 Mar 2021 09:19:06 +0100\nSubject: [PATCH 05/22] dt-bindings: add BCM6328 pincontroller binding\n documentation\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nAdd binding documentation for the pincontrol core found in BCM6328 SoCs.\n\nCo-developed-by: Jonas Gorski <jonas.gorski@gmail.com>\nSigned-off-by: Jonas Gorski <jonas.gorski@gmail.com>\nSigned-off-by: Álvaro Fernández Rojas <noltari@gmail.com>\nReviewed-by: Rob Herring <robh@kernel.org>\nLink: https://lore.kernel.org/r/20210324081923.20379-6-noltari@gmail.com\nSigned-off-by: Linus Walleij <linus.walleij@linaro.org>\n---\n .../pinctrl/brcm,bcm6328-pinctrl.yaml         | 127 ++++++++++++++++++\n 1 file changed, 127 insertions(+)\n create mode 100644 Documentation/devicetree/bindings/pinctrl/brcm,bcm6328-pinctrl.yaml\n\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/pinctrl/brcm,bcm6328-pinctrl.yaml\n@@ -0,0 +1,127 @@\n+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause\n+%YAML 1.2\n+---\n+$id: http://devicetree.org/schemas/pinctrl/brcm,bcm6328-pinctrl.yaml#\n+$schema: http://devicetree.org/meta-schemas/core.yaml#\n+\n+title: Broadcom BCM6328 pin controller\n+\n+maintainers:\n+  - Álvaro Fernández Rojas <noltari@gmail.com>\n+  - Jonas Gorski <jonas.gorski@gmail.com>\n+\n+description:\n+  Bindings for Broadcom's BCM6328 memory-mapped pin controller.\n+\n+properties:\n+  compatible:\n+    const: brcm,bcm6328-pinctrl\n+\n+  reg:\n+    maxItems: 1\n+\n+patternProperties:\n+  '-pins$':\n+    type: object\n+    $ref: pinmux-node.yaml#\n+\n+    properties:\n+      function:\n+        enum: [ serial_led_data, serial_led_clk, inet_act_led, pcie_clkreq,\n+                led, ephy0_act_led, ephy1_act_led, ephy2_act_led,\n+                ephy3_act_led, hsspi_cs1, usb_device_port, usb_host_port ]\n+\n+      pins:\n+        enum: [ gpio6, gpio7, gpio11, gpio16, gpio17, gpio18, gpio19,\n+                gpio20, gpio25, gpio26, gpio27, gpio28, hsspi_cs1,\n+                usb_port1 ]\n+\n+required:\n+  - compatible\n+  - reg\n+\n+additionalProperties: false\n+\n+examples:\n+  - |\n+    pinctrl@18 {\n+      compatible = \"brcm,bcm6328-pinctrl\";\n+      reg = <0x18 0x10>;\n+\n+      pinctrl_serial_led: serial_led-pins {\n+        pinctrl_serial_led_data: serial_led_data-pins {\n+          function = \"serial_led_data\";\n+          pins = \"gpio6\";\n+        };\n+\n+        pinctrl_serial_led_clk: serial_led_clk-pins {\n+          function = \"serial_led_clk\";\n+          pins = \"gpio7\";\n+        };\n+      };\n+\n+      pinctrl_inet_act_led: inet_act_led-pins {\n+        function = \"inet_act_led\";\n+        pins = \"gpio11\";\n+      };\n+\n+      pinctrl_pcie_clkreq: pcie_clkreq-pins {\n+        function = \"pcie_clkreq\";\n+        pins = \"gpio16\";\n+      };\n+\n+      pinctrl_ephy0_spd_led: ephy0_spd_led-pins {\n+        function = \"led\";\n+        pins = \"gpio17\";\n+      };\n+\n+      pinctrl_ephy1_spd_led: ephy1_spd_led-pins {\n+        function = \"led\";\n+        pins = \"gpio18\";\n+      };\n+\n+      pinctrl_ephy2_spd_led: ephy2_spd_led-pins {\n+        function = \"led\";\n+        pins = \"gpio19\";\n+      };\n+\n+      pinctrl_ephy3_spd_led: ephy3_spd_led-pins {\n+        function = \"led\";\n+        pins = \"gpio20\";\n+      };\n+\n+      pinctrl_ephy0_act_led: ephy0_act_led-pins {\n+        function = \"ephy0_act_led\";\n+        pins = \"gpio25\";\n+      };\n+\n+      pinctrl_ephy1_act_led: ephy1_act_led-pins {\n+        function = \"ephy1_act_led\";\n+        pins = \"gpio26\";\n+      };\n+\n+      pinctrl_ephy2_act_led: ephy2_act_led-pins {\n+        function = \"ephy2_act_led\";\n+        pins = \"gpio27\";\n+      };\n+\n+      pinctrl_ephy3_act_led: ephy3_act_led-pins {\n+        function = \"ephy3_act_led\";\n+        pins = \"gpio28\";\n+      };\n+\n+      pinctrl_hsspi_cs1: hsspi_cs1-pins {\n+        function = \"hsspi_cs1\";\n+        pins = \"hsspi_cs1\";\n+      };\n+\n+      pinctrl_usb_port1_device: usb_port1_device-pins {\n+        function = \"usb_device_port\";\n+        pins = \"usb_port1\";\n+      };\n+\n+      pinctrl_usb_port1_host: usb_port1_host-pins {\n+        function = \"usb_host_port\";\n+        pins = \"usb_port1\";\n+      };\n+    };\n"
  },
  {
    "path": "target/linux/bmips/patches-5.10/057-v5.13-dt-bindings-add-BCM6328-GPIO-sysctl-binding-document.patch",
    "content": "From 7f9dfaa2afb6bc3481e531c405b05acf6091af29 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com>\nDate: Wed, 24 Mar 2021 09:19:07 +0100\nSubject: [PATCH 06/22] dt-bindings: add BCM6328 GPIO sysctl binding\n documentation\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nAdd binding documentation for the GPIO sysctl found in BCM6328 SoCs.\n\nSigned-off-by: Álvaro Fernández Rojas <noltari@gmail.com>\nReviewed-by: Rob Herring <robh@kernel.org>\nLink: https://lore.kernel.org/r/20210324081923.20379-7-noltari@gmail.com\nSigned-off-by: Linus Walleij <linus.walleij@linaro.org>\n---\n .../mfd/brcm,bcm6328-gpio-sysctl.yaml         | 162 ++++++++++++++++++\n 1 file changed, 162 insertions(+)\n create mode 100644 Documentation/devicetree/bindings/mfd/brcm,bcm6328-gpio-sysctl.yaml\n\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/mfd/brcm,bcm6328-gpio-sysctl.yaml\n@@ -0,0 +1,162 @@\n+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)\n+%YAML 1.2\n+---\n+$id: http://devicetree.org/schemas/mfd/brcm,bcm6328-gpio-sysctl.yaml#\n+$schema: http://devicetree.org/meta-schemas/core.yaml#\n+\n+title: Broadcom BCM6328 GPIO System Controller Device Tree Bindings\n+\n+maintainers:\n+  - Álvaro Fernández Rojas <noltari@gmail.com>\n+  - Jonas Gorski <jonas.gorski@gmail.com>\n+\n+description:\n+  Broadcom BCM6328 SoC GPIO system controller which provides a register map\n+  for controlling the GPIO and pins of the SoC.\n+\n+properties:\n+  \"#address-cells\": true\n+\n+  \"#size-cells\": true\n+\n+  compatible:\n+    items:\n+      - const: brcm,bcm6328-gpio-sysctl\n+      - const: syscon\n+      - const: simple-mfd\n+\n+  ranges:\n+    maxItems: 1\n+\n+  reg:\n+    maxItems: 1\n+\n+patternProperties:\n+  \"^gpio@[0-9a-f]+$\":\n+    # Child node\n+    type: object\n+    $ref: \"../gpio/brcm,bcm6345-gpio.yaml\"\n+    description:\n+      GPIO controller for the SoC GPIOs. This child node definition\n+      should follow the bindings specified in\n+      Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.yaml.\n+\n+  \"^pinctrl@[0-9a-f]+$\":\n+    # Child node\n+    type: object\n+    $ref: \"../pinctrl/brcm,bcm6328-pinctrl.yaml\"\n+    description:\n+      Pin controller for the SoC pins. This child node definition\n+      should follow the bindings specified in\n+      Documentation/devicetree/bindings/pinctrl/brcm,bcm6328-pinctrl.yaml.\n+\n+required:\n+  - \"#address-cells\"\n+  - compatible\n+  - ranges\n+  - reg\n+  - \"#size-cells\"\n+\n+additionalProperties: false\n+\n+examples:\n+  - |\n+    syscon@10000080 {\n+      #address-cells = <1>;\n+      #size-cells = <1>;\n+      compatible = \"brcm,bcm6328-gpio-sysctl\", \"syscon\", \"simple-mfd\";\n+      reg = <0x10000080 0x80>;\n+      ranges = <0 0x10000080 0x80>;\n+\n+      gpio@0 {\n+        compatible = \"brcm,bcm6328-gpio\";\n+        reg-names = \"dirout\", \"dat\";\n+        reg = <0x0 0x8>, <0x8 0x8>;\n+\n+        gpio-controller;\n+        gpio-ranges = <&pinctrl 0 0 32>;\n+        #gpio-cells = <2>;\n+      };\n+\n+      pinctrl: pinctrl@18 {\n+        compatible = \"brcm,bcm6328-pinctrl\";\n+        reg = <0x18 0x10>;\n+\n+        pinctrl_serial_led: serial_led-pins {\n+          pinctrl_serial_led_data: serial_led_data-pins {\n+            function = \"serial_led_data\";\n+            pins = \"gpio6\";\n+          };\n+\n+          pinctrl_serial_led_clk: serial_led_clk-pins {\n+            function = \"serial_led_clk\";\n+            pins = \"gpio7\";\n+          };\n+        };\n+\n+        pinctrl_inet_act_led: inet_act_led-pins {\n+          function = \"inet_act_led\";\n+          pins = \"gpio11\";\n+        };\n+\n+        pinctrl_pcie_clkreq: pcie_clkreq-pins {\n+          function = \"pcie_clkreq\";\n+          pins = \"gpio16\";\n+        };\n+\n+        pinctrl_ephy0_spd_led: ephy0_spd_led-pins {\n+          function = \"led\";\n+          pins = \"gpio17\";\n+        };\n+\n+        pinctrl_ephy1_spd_led: ephy1_spd_led-pins {\n+          function = \"led\";\n+          pins = \"gpio18\";\n+        };\n+\n+        pinctrl_ephy2_spd_led: ephy2_spd_led-pins {\n+          function = \"led\";\n+          pins = \"gpio19\";\n+        };\n+\n+        pinctrl_ephy3_spd_led: ephy3_spd_led-pins {\n+          function = \"led\";\n+          pins = \"gpio20\";\n+        };\n+\n+        pinctrl_ephy0_act_led: ephy0_act_led-pins {\n+          function = \"ephy0_act_led\";\n+          pins = \"gpio25\";\n+        };\n+\n+        pinctrl_ephy1_act_led: ephy1_act_led-pins {\n+          function = \"ephy1_act_led\";\n+          pins = \"gpio26\";\n+        };\n+\n+        pinctrl_ephy2_act_led: ephy2_act_led-pins {\n+          function = \"ephy2_act_led\";\n+          pins = \"gpio27\";\n+        };\n+\n+        pinctrl_ephy3_act_led: ephy3_act_led-pins {\n+          function = \"ephy3_act_led\";\n+          pins = \"gpio28\";\n+        };\n+\n+        pinctrl_hsspi_cs1: hsspi_cs1-pins {\n+          function = \"hsspi_cs1\";\n+          pins = \"hsspi_cs1\";\n+        };\n+\n+        pinctrl_usb_port1_device: usb_port1_device-pins {\n+          function = \"usb_device_port\";\n+          pins = \"usb_port1\";\n+        };\n+\n+        pinctrl_usb_port1_host: usb_port1_host-pins {\n+          function = \"usb_host_port\";\n+          pins = \"usb_port1\";\n+        };\n+      };\n+    };\n"
  },
  {
    "path": "target/linux/bmips/patches-5.10/058-v5.13-pinctrl-add-a-pincontrol-driver-for-BCM6328.patch",
    "content": "From 9bf34ac5ab5805f0a798d40423c05596b7a0cee6 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com>\nDate: Wed, 24 Mar 2021 09:19:08 +0100\nSubject: [PATCH 07/22] pinctrl: add a pincontrol driver for BCM6328\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nAdd a pincontrol driver for BCM6328. BCM6328 supports muxing 32 pins as\nGPIOs, as LEDs for the integrated LED controller, or various other\nfunctions. Its pincontrol mux registers also control other aspects, like\nswitching the second USB port between host and device mode.\n\nCo-developed-by: Jonas Gorski <jonas.gorski@gmail.com>\nSigned-off-by: Jonas Gorski <jonas.gorski@gmail.com>\nSigned-off-by: Álvaro Fernández Rojas <noltari@gmail.com>\nLink: https://lore.kernel.org/r/20210324081923.20379-8-noltari@gmail.com\nSigned-off-by: Linus Walleij <linus.walleij@linaro.org>\n---\n drivers/pinctrl/bcm/Kconfig           |   8 +\n drivers/pinctrl/bcm/Makefile          |   1 +\n drivers/pinctrl/bcm/pinctrl-bcm6328.c | 404 ++++++++++++++++++++++++++\n 3 files changed, 413 insertions(+)\n create mode 100644 drivers/pinctrl/bcm/pinctrl-bcm6328.c\n\n--- a/drivers/pinctrl/bcm/Kconfig\n+++ b/drivers/pinctrl/bcm/Kconfig\n@@ -36,6 +36,14 @@ config PINCTRL_BCM63XX\n \tselect PINCONF\n \tselect PINMUX\n \n+config PINCTRL_BCM6328\n+\tbool \"Broadcom BCM6328 GPIO driver\"\n+\tdepends on (BMIPS_GENERIC || COMPILE_TEST)\n+\tselect PINCTRL_BCM63XX\n+\tdefault BMIPS_GENERIC\n+\thelp\n+\t   Say Y here to enable the Broadcom BCM6328 GPIO driver.\n+\n config PINCTRL_IPROC_GPIO\n \tbool \"Broadcom iProc GPIO (with PINCONF) driver\"\n \tdepends on OF_GPIO && (ARCH_BCM_IPROC || COMPILE_TEST)\n--- a/drivers/pinctrl/bcm/Makefile\n+++ b/drivers/pinctrl/bcm/Makefile\n@@ -4,6 +4,7 @@\n obj-$(CONFIG_PINCTRL_BCM281XX)\t\t+= pinctrl-bcm281xx.o\n obj-$(CONFIG_PINCTRL_BCM2835)\t\t+= pinctrl-bcm2835.o\n obj-$(CONFIG_PINCTRL_BCM63XX)\t\t+= pinctrl-bcm63xx.o\n+obj-$(CONFIG_PINCTRL_BCM6328)\t\t+= pinctrl-bcm6328.o\n obj-$(CONFIG_PINCTRL_IPROC_GPIO)\t+= pinctrl-iproc-gpio.o\n obj-$(CONFIG_PINCTRL_CYGNUS_MUX)\t+= pinctrl-cygnus-mux.o\n obj-$(CONFIG_PINCTRL_NS)\t\t+= pinctrl-ns.o\n--- /dev/null\n+++ b/drivers/pinctrl/bcm/pinctrl-bcm6328.c\n@@ -0,0 +1,404 @@\n+// SPDX-License-Identifier: GPL-2.0+\n+/*\n+ * Driver for BCM6328 GPIO unit (pinctrl + GPIO)\n+ *\n+ * Copyright (C) 2021 Álvaro Fernández Rojas <noltari@gmail.com>\n+ * Copyright (C) 2016 Jonas Gorski <jonas.gorski@gmail.com>\n+ */\n+\n+#include <linux/bits.h>\n+#include <linux/gpio/driver.h>\n+#include <linux/kernel.h>\n+#include <linux/of.h>\n+#include <linux/pinctrl/pinmux.h>\n+#include <linux/platform_device.h>\n+#include <linux/regmap.h>\n+\n+#include \"../pinctrl-utils.h\"\n+\n+#include \"pinctrl-bcm63xx.h\"\n+\n+#define BCM6328_NUM_GPIOS\t32\n+\n+#define BCM6328_MODE_REG\t0x18\n+#define BCM6328_MUX_HI_REG\t0x1c\n+#define BCM6328_MUX_LO_REG\t0x20\n+#define BCM6328_MUX_OTHER_REG\t0x24\n+#define  BCM6328_MUX_MASK\tGENMASK(1, 0)\n+\n+struct bcm6328_pingroup {\n+\tconst char *name;\n+\tconst unsigned * const pins;\n+\tconst unsigned num_pins;\n+};\n+\n+struct bcm6328_function {\n+\tconst char *name;\n+\tconst char * const *groups;\n+\tconst unsigned num_groups;\n+\n+\tunsigned mode_val:1;\n+\tunsigned mux_val:2;\n+};\n+\n+static const unsigned int bcm6328_mux[] = {\n+\tBCM6328_MUX_LO_REG,\n+\tBCM6328_MUX_HI_REG,\n+\tBCM6328_MUX_OTHER_REG\n+};\n+\n+static const struct pinctrl_pin_desc bcm6328_pins[] = {\n+\tPINCTRL_PIN(0, \"gpio0\"),\n+\tPINCTRL_PIN(1, \"gpio1\"),\n+\tPINCTRL_PIN(2, \"gpio2\"),\n+\tPINCTRL_PIN(3, \"gpio3\"),\n+\tPINCTRL_PIN(4, \"gpio4\"),\n+\tPINCTRL_PIN(5, \"gpio5\"),\n+\tPINCTRL_PIN(6, \"gpio6\"),\n+\tPINCTRL_PIN(7, \"gpio7\"),\n+\tPINCTRL_PIN(8, \"gpio8\"),\n+\tPINCTRL_PIN(9, \"gpio9\"),\n+\tPINCTRL_PIN(10, \"gpio10\"),\n+\tPINCTRL_PIN(11, \"gpio11\"),\n+\tPINCTRL_PIN(12, \"gpio12\"),\n+\tPINCTRL_PIN(13, \"gpio13\"),\n+\tPINCTRL_PIN(14, \"gpio14\"),\n+\tPINCTRL_PIN(15, \"gpio15\"),\n+\tPINCTRL_PIN(16, \"gpio16\"),\n+\tPINCTRL_PIN(17, \"gpio17\"),\n+\tPINCTRL_PIN(18, \"gpio18\"),\n+\tPINCTRL_PIN(19, \"gpio19\"),\n+\tPINCTRL_PIN(20, \"gpio20\"),\n+\tPINCTRL_PIN(21, \"gpio21\"),\n+\tPINCTRL_PIN(22, \"gpio22\"),\n+\tPINCTRL_PIN(23, \"gpio23\"),\n+\tPINCTRL_PIN(24, \"gpio24\"),\n+\tPINCTRL_PIN(25, \"gpio25\"),\n+\tPINCTRL_PIN(26, \"gpio26\"),\n+\tPINCTRL_PIN(27, \"gpio27\"),\n+\tPINCTRL_PIN(28, \"gpio28\"),\n+\tPINCTRL_PIN(29, \"gpio29\"),\n+\tPINCTRL_PIN(30, \"gpio30\"),\n+\tPINCTRL_PIN(31, \"gpio31\"),\n+\n+\t/*\n+\t * No idea where they really are; so let's put them according\n+\t * to their mux offsets.\n+\t */\n+\tPINCTRL_PIN(36, \"hsspi_cs1\"),\n+\tPINCTRL_PIN(38, \"usb_p2\"),\n+};\n+\n+static unsigned gpio0_pins[] = { 0 };\n+static unsigned gpio1_pins[] = { 1 };\n+static unsigned gpio2_pins[] = { 2 };\n+static unsigned gpio3_pins[] = { 3 };\n+static unsigned gpio4_pins[] = { 4 };\n+static unsigned gpio5_pins[] = { 5 };\n+static unsigned gpio6_pins[] = { 6 };\n+static unsigned gpio7_pins[] = { 7 };\n+static unsigned gpio8_pins[] = { 8 };\n+static unsigned gpio9_pins[] = { 9 };\n+static unsigned gpio10_pins[] = { 10 };\n+static unsigned gpio11_pins[] = { 11 };\n+static unsigned gpio12_pins[] = { 12 };\n+static unsigned gpio13_pins[] = { 13 };\n+static unsigned gpio14_pins[] = { 14 };\n+static unsigned gpio15_pins[] = { 15 };\n+static unsigned gpio16_pins[] = { 16 };\n+static unsigned gpio17_pins[] = { 17 };\n+static unsigned gpio18_pins[] = { 18 };\n+static unsigned gpio19_pins[] = { 19 };\n+static unsigned gpio20_pins[] = { 20 };\n+static unsigned gpio21_pins[] = { 21 };\n+static unsigned gpio22_pins[] = { 22 };\n+static unsigned gpio23_pins[] = { 23 };\n+static unsigned gpio24_pins[] = { 24 };\n+static unsigned gpio25_pins[] = { 25 };\n+static unsigned gpio26_pins[] = { 26 };\n+static unsigned gpio27_pins[] = { 27 };\n+static unsigned gpio28_pins[] = { 28 };\n+static unsigned gpio29_pins[] = { 29 };\n+static unsigned gpio30_pins[] = { 30 };\n+static unsigned gpio31_pins[] = { 31 };\n+\n+static unsigned hsspi_cs1_pins[] = { 36 };\n+static unsigned usb_port1_pins[] = { 38 };\n+\n+#define BCM6328_GROUP(n)\t\t\t\t\t\\\n+\t{\t\t\t\t\t\t\t\\\n+\t\t.name = #n,\t\t\t\t\t\\\n+\t\t.pins = n##_pins,\t\t\t\t\\\n+\t\t.num_pins = ARRAY_SIZE(n##_pins),\t\t\\\n+\t}\n+\n+static struct bcm6328_pingroup bcm6328_groups[] = {\n+\tBCM6328_GROUP(gpio0),\n+\tBCM6328_GROUP(gpio1),\n+\tBCM6328_GROUP(gpio2),\n+\tBCM6328_GROUP(gpio3),\n+\tBCM6328_GROUP(gpio4),\n+\tBCM6328_GROUP(gpio5),\n+\tBCM6328_GROUP(gpio6),\n+\tBCM6328_GROUP(gpio7),\n+\tBCM6328_GROUP(gpio8),\n+\tBCM6328_GROUP(gpio9),\n+\tBCM6328_GROUP(gpio10),\n+\tBCM6328_GROUP(gpio11),\n+\tBCM6328_GROUP(gpio12),\n+\tBCM6328_GROUP(gpio13),\n+\tBCM6328_GROUP(gpio14),\n+\tBCM6328_GROUP(gpio15),\n+\tBCM6328_GROUP(gpio16),\n+\tBCM6328_GROUP(gpio17),\n+\tBCM6328_GROUP(gpio18),\n+\tBCM6328_GROUP(gpio19),\n+\tBCM6328_GROUP(gpio20),\n+\tBCM6328_GROUP(gpio21),\n+\tBCM6328_GROUP(gpio22),\n+\tBCM6328_GROUP(gpio23),\n+\tBCM6328_GROUP(gpio24),\n+\tBCM6328_GROUP(gpio25),\n+\tBCM6328_GROUP(gpio26),\n+\tBCM6328_GROUP(gpio27),\n+\tBCM6328_GROUP(gpio28),\n+\tBCM6328_GROUP(gpio29),\n+\tBCM6328_GROUP(gpio30),\n+\tBCM6328_GROUP(gpio31),\n+\n+\tBCM6328_GROUP(hsspi_cs1),\n+\tBCM6328_GROUP(usb_port1),\n+};\n+\n+/* GPIO_MODE */\n+static const char * const led_groups[] = {\n+\t\"gpio0\",\n+\t\"gpio1\",\n+\t\"gpio2\",\n+\t\"gpio3\",\n+\t\"gpio4\",\n+\t\"gpio5\",\n+\t\"gpio6\",\n+\t\"gpio7\",\n+\t\"gpio8\",\n+\t\"gpio9\",\n+\t\"gpio10\",\n+\t\"gpio11\",\n+\t\"gpio12\",\n+\t\"gpio13\",\n+\t\"gpio14\",\n+\t\"gpio15\",\n+\t\"gpio16\",\n+\t\"gpio17\",\n+\t\"gpio18\",\n+\t\"gpio19\",\n+\t\"gpio20\",\n+\t\"gpio21\",\n+\t\"gpio22\",\n+\t\"gpio23\",\n+};\n+\n+/* PINMUX_SEL */\n+static const char * const serial_led_data_groups[] = {\n+\t\"gpio6\",\n+};\n+\n+static const char * const serial_led_clk_groups[] = {\n+\t\"gpio7\",\n+};\n+\n+static const char * const inet_act_led_groups[] = {\n+\t\"gpio11\",\n+};\n+\n+static const char * const pcie_clkreq_groups[] = {\n+\t\"gpio16\",\n+};\n+\n+static const char * const ephy0_act_led_groups[] = {\n+\t\"gpio25\",\n+};\n+\n+static const char * const ephy1_act_led_groups[] = {\n+\t\"gpio26\",\n+};\n+\n+static const char * const ephy2_act_led_groups[] = {\n+\t\"gpio27\",\n+};\n+\n+static const char * const ephy3_act_led_groups[] = {\n+\t\"gpio28\",\n+};\n+\n+static const char * const hsspi_cs1_groups[] = {\n+\t\"hsspi_cs1\"\n+};\n+\n+static const char * const usb_host_port_groups[] = {\n+\t\"usb_port1\",\n+};\n+\n+static const char * const usb_device_port_groups[] = {\n+\t\"usb_port1\",\n+};\n+\n+#define BCM6328_MODE_FUN(n)\t\t\t\t\\\n+\t{\t\t\t\t\t\t\\\n+\t\t.name = #n,\t\t\t\t\\\n+\t\t.groups = n##_groups,\t\t\t\\\n+\t\t.num_groups = ARRAY_SIZE(n##_groups),\t\\\n+\t\t.mode_val = 1,\t\t\t\t\\\n+\t}\n+\n+#define BCM6328_MUX_FUN(n, mux)\t\t\t\t\\\n+\t{\t\t\t\t\t\t\\\n+\t\t.name = #n,\t\t\t\t\\\n+\t\t.groups = n##_groups,\t\t\t\\\n+\t\t.num_groups = ARRAY_SIZE(n##_groups),\t\\\n+\t\t.mux_val = mux,\t\t\t\t\\\n+\t}\n+\n+static const struct bcm6328_function bcm6328_funcs[] = {\n+\tBCM6328_MODE_FUN(led),\n+\tBCM6328_MUX_FUN(serial_led_data, 2),\n+\tBCM6328_MUX_FUN(serial_led_clk, 2),\n+\tBCM6328_MUX_FUN(inet_act_led, 1),\n+\tBCM6328_MUX_FUN(pcie_clkreq, 2),\n+\tBCM6328_MUX_FUN(ephy0_act_led, 1),\n+\tBCM6328_MUX_FUN(ephy1_act_led, 1),\n+\tBCM6328_MUX_FUN(ephy2_act_led, 1),\n+\tBCM6328_MUX_FUN(ephy3_act_led, 1),\n+\tBCM6328_MUX_FUN(hsspi_cs1, 2),\n+\tBCM6328_MUX_FUN(usb_host_port, 1),\n+\tBCM6328_MUX_FUN(usb_device_port, 2),\n+};\n+\n+static inline unsigned int bcm6328_mux_off(unsigned int pin)\n+{\n+\treturn bcm6328_mux[pin / 16];\n+}\n+\n+static int bcm6328_pinctrl_get_group_count(struct pinctrl_dev *pctldev)\n+{\n+\treturn ARRAY_SIZE(bcm6328_groups);\n+}\n+\n+static const char *bcm6328_pinctrl_get_group_name(struct pinctrl_dev *pctldev,\n+\t\t\t\t\t\t  unsigned group)\n+{\n+\treturn bcm6328_groups[group].name;\n+}\n+\n+static int bcm6328_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,\n+\t\t\t\t\t  unsigned group, const unsigned **pins,\n+\t\t\t\t\t  unsigned *num_pins)\n+{\n+\t*pins = bcm6328_groups[group].pins;\n+\t*num_pins = bcm6328_groups[group].num_pins;\n+\n+\treturn 0;\n+}\n+\n+static int bcm6328_pinctrl_get_func_count(struct pinctrl_dev *pctldev)\n+{\n+\treturn ARRAY_SIZE(bcm6328_funcs);\n+}\n+\n+static const char *bcm6328_pinctrl_get_func_name(struct pinctrl_dev *pctldev,\n+\t\t\t\t\t\t unsigned selector)\n+{\n+\treturn bcm6328_funcs[selector].name;\n+}\n+\n+static int bcm6328_pinctrl_get_groups(struct pinctrl_dev *pctldev,\n+\t\t\t\t      unsigned selector,\n+\t\t\t\t      const char * const **groups,\n+\t\t\t\t      unsigned * const num_groups)\n+{\n+\t*groups = bcm6328_funcs[selector].groups;\n+\t*num_groups = bcm6328_funcs[selector].num_groups;\n+\n+\treturn 0;\n+}\n+\n+static void bcm6328_rmw_mux(struct bcm63xx_pinctrl *pc, unsigned pin,\n+\t\t\t    unsigned int mode, unsigned int mux)\n+{\n+\tif (pin < BCM6328_NUM_GPIOS)\n+\t\tregmap_update_bits(pc->regs, BCM6328_MODE_REG, BIT(pin),\n+\t\t\t\t   mode ? BIT(pin) : 0);\n+\n+\tregmap_update_bits(pc->regs, bcm6328_mux_off(pin),\n+\t\t\t   BCM6328_MUX_MASK << ((pin % 16) * 2),\n+\t\t\t   mux << ((pin % 16) * 2));\n+}\n+\n+static int bcm6328_pinctrl_set_mux(struct pinctrl_dev *pctldev,\n+\t\t\t\t   unsigned selector, unsigned group)\n+{\n+\tstruct bcm63xx_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);\n+\tconst struct bcm6328_pingroup *pg = &bcm6328_groups[group];\n+\tconst struct bcm6328_function *f = &bcm6328_funcs[selector];\n+\n+\tbcm6328_rmw_mux(pc, pg->pins[0], f->mode_val, f->mux_val);\n+\n+\treturn 0;\n+}\n+\n+static int bcm6328_gpio_request_enable(struct pinctrl_dev *pctldev,\n+\t\t\t\t       struct pinctrl_gpio_range *range,\n+\t\t\t\t       unsigned offset)\n+{\n+\tstruct bcm63xx_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);\n+\n+\t/* disable all functions using this pin */\n+\tbcm6328_rmw_mux(pc, offset, 0, 0);\n+\n+\treturn 0;\n+}\n+\n+static struct pinctrl_ops bcm6328_pctl_ops = {\n+\t.dt_free_map = pinctrl_utils_free_map,\n+\t.dt_node_to_map = pinconf_generic_dt_node_to_map_pin,\n+\t.get_group_name = bcm6328_pinctrl_get_group_name,\n+\t.get_group_pins = bcm6328_pinctrl_get_group_pins,\n+\t.get_groups_count = bcm6328_pinctrl_get_group_count,\n+};\n+\n+static struct pinmux_ops bcm6328_pmx_ops = {\n+\t.get_function_groups = bcm6328_pinctrl_get_groups,\n+\t.get_function_name = bcm6328_pinctrl_get_func_name,\n+\t.get_functions_count = bcm6328_pinctrl_get_func_count,\n+\t.gpio_request_enable = bcm6328_gpio_request_enable,\n+\t.set_mux = bcm6328_pinctrl_set_mux,\n+\t.strict = true,\n+};\n+\n+static const struct bcm63xx_pinctrl_soc bcm6328_soc = {\n+\t.ngpios = BCM6328_NUM_GPIOS,\n+\t.npins = ARRAY_SIZE(bcm6328_pins),\n+\t.pctl_ops = &bcm6328_pctl_ops,\n+\t.pins = bcm6328_pins,\n+\t.pmx_ops = &bcm6328_pmx_ops,\n+};\n+\n+static int bcm6328_pinctrl_probe(struct platform_device *pdev)\n+{\n+\treturn bcm63xx_pinctrl_probe(pdev, &bcm6328_soc, NULL);\n+}\n+\n+static const struct of_device_id bcm6328_pinctrl_match[] = {\n+\t{ .compatible = \"brcm,bcm6328-pinctrl\", },\n+\t{ /* sentinel */ }\n+};\n+\n+static struct platform_driver bcm6328_pinctrl_driver = {\n+\t.probe = bcm6328_pinctrl_probe,\n+\t.driver = {\n+\t\t.name = \"bcm6328-pinctrl\",\n+\t\t.of_match_table = bcm6328_pinctrl_match,\n+\t},\n+};\n+\n+builtin_platform_driver(bcm6328_pinctrl_driver);\n"
  },
  {
    "path": "target/linux/bmips/patches-5.10/059-v5.13-dt-bindings-add-BCM6358-pincontroller-binding-docume.patch",
    "content": "From 6d591614bfe881bb7664c9bebb6a48231c059411 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com>\nDate: Wed, 24 Mar 2021 09:19:09 +0100\nSubject: [PATCH 08/22] dt-bindings: add BCM6358 pincontroller binding\n documentation\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nAdd binding documentation for the pincontrol core found in BCM6358 SoCs.\n\nCo-developed-by: Jonas Gorski <jonas.gorski@gmail.com>\nSigned-off-by: Jonas Gorski <jonas.gorski@gmail.com>\nSigned-off-by: Álvaro Fernández Rojas <noltari@gmail.com>\nReviewed-by: Rob Herring <robh@kernel.org>\nLink: https://lore.kernel.org/r/20210324081923.20379-9-noltari@gmail.com\nSigned-off-by: Linus Walleij <linus.walleij@linaro.org>\n---\n .../pinctrl/brcm,bcm6358-pinctrl.yaml         | 93 +++++++++++++++++++\n 1 file changed, 93 insertions(+)\n create mode 100644 Documentation/devicetree/bindings/pinctrl/brcm,bcm6358-pinctrl.yaml\n\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/pinctrl/brcm,bcm6358-pinctrl.yaml\n@@ -0,0 +1,93 @@\n+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause\n+%YAML 1.2\n+---\n+$id: http://devicetree.org/schemas/pinctrl/brcm,bcm6358-pinctrl.yaml#\n+$schema: http://devicetree.org/meta-schemas/core.yaml#\n+\n+title: Broadcom BCM6358 pin controller\n+\n+maintainers:\n+  - Álvaro Fernández Rojas <noltari@gmail.com>\n+  - Jonas Gorski <jonas.gorski@gmail.com>\n+\n+description:\n+  Bindings for Broadcom's BCM6358 memory-mapped pin controller.\n+\n+properties:\n+  compatible:\n+    const: brcm,bcm6358-pinctrl\n+\n+  reg:\n+    maxItems: 1\n+\n+patternProperties:\n+  '-pins$':\n+    type: object\n+    $ref: pinmux-node.yaml#\n+\n+    properties:\n+      function:\n+        enum: [ ebi_cs, uart1, serial_led, legacy_led, led, spi_cs, utopia,\n+                pwm_syn_clk, sys_irq ]\n+\n+      pins:\n+        enum: [ ebi_cs_grp, uart1_grp, serial_led_grp, legacy_led_grp,\n+                led_grp, spi_cs_grp, utopia_grp, pwm_syn_clk, sys_irq_grp ]\n+\n+required:\n+  - compatible\n+  - reg\n+\n+additionalProperties: false\n+\n+examples:\n+  - |\n+    pinctrl@18 {\n+      compatible = \"brcm,bcm6358-pinctrl\";\n+      reg = <0x18 0x4>;\n+\n+      pinctrl_ebi_cs: ebi_cs-pins {\n+        function = \"ebi_cs\";\n+        groups = \"ebi_cs_grp\";\n+      };\n+\n+      pinctrl_uart1: uart1-pins {\n+        function = \"uart1\";\n+        groups = \"uart1_grp\";\n+      };\n+\n+      pinctrl_serial_led: serial_led-pins {\n+        function = \"serial_led\";\n+        groups = \"serial_led_grp\";\n+      };\n+\n+      pinctrl_legacy_led: legacy_led-pins {\n+        function = \"legacy_led\";\n+        groups = \"legacy_led_grp\";\n+      };\n+\n+      pinctrl_led: led-pins {\n+        function = \"led\";\n+        groups = \"led_grp\";\n+      };\n+\n+      pinctrl_spi_cs_23: spi_cs-pins {\n+        function = \"spi_cs\";\n+        groups = \"spi_cs_grp\";\n+      };\n+\n+      pinctrl_utopia: utopia-pins {\n+        function = \"utopia\";\n+        groups = \"utopia_grp\";\n+      };\n+\n+      pinctrl_pwm_syn_clk: pwm_syn_clk-pins {\n+        function = \"pwm_syn_clk\";\n+        groups = \"pwm_syn_clk_grp\";\n+      };\n+\n+      pinctrl_sys_irq: sys_irq-pins {\n+        function = \"sys_irq\";\n+        groups = \"sys_irq_grp\";\n+      };\n+    };\n"
  },
  {
    "path": "target/linux/bmips/patches-5.10/060-v5.13-dt-bindings-add-BCM6358-GPIO-sysctl-binding-document.patch",
    "content": "From cfb1b98bc8d5ffd813428cb03c63b54cf63dd785 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com>\nDate: Wed, 24 Mar 2021 09:19:10 +0100\nSubject: [PATCH 09/22] dt-bindings: add BCM6358 GPIO sysctl binding\n documentation\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nAdd binding documentation for the GPIO sysctl found in BCM6358 SoCs.\n\nSigned-off-by: Álvaro Fernández Rojas <noltari@gmail.com>\nReviewed-by: Rob Herring <robh@kernel.org>\nLink: https://lore.kernel.org/r/20210324081923.20379-10-noltari@gmail.com\nSigned-off-by: Linus Walleij <linus.walleij@linaro.org>\n---\n .../mfd/brcm,bcm6358-gpio-sysctl.yaml         | 130 ++++++++++++++++++\n 1 file changed, 130 insertions(+)\n create mode 100644 Documentation/devicetree/bindings/mfd/brcm,bcm6358-gpio-sysctl.yaml\n\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/mfd/brcm,bcm6358-gpio-sysctl.yaml\n@@ -0,0 +1,130 @@\n+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)\n+%YAML 1.2\n+---\n+$id: http://devicetree.org/schemas/mfd/brcm,bcm6358-gpio-sysctl.yaml#\n+$schema: http://devicetree.org/meta-schemas/core.yaml#\n+\n+title: Broadcom BCM6358 GPIO System Controller Device Tree Bindings\n+\n+maintainers:\n+  - Álvaro Fernández Rojas <noltari@gmail.com>\n+  - Jonas Gorski <jonas.gorski@gmail.com>\n+\n+description:\n+  Broadcom BCM6358 SoC GPIO system controller which provides a register map\n+  for controlling the GPIO and pins of the SoC.\n+\n+properties:\n+  \"#address-cells\": true\n+\n+  \"#size-cells\": true\n+\n+  compatible:\n+    items:\n+      - const: brcm,bcm6358-gpio-sysctl\n+      - const: syscon\n+      - const: simple-mfd\n+\n+  ranges:\n+    maxItems: 1\n+\n+  reg:\n+    maxItems: 1\n+\n+patternProperties:\n+  \"^gpio@[0-9a-f]+$\":\n+    # Child node\n+    type: object\n+    $ref: \"../gpio/brcm,bcm6345-gpio.yaml\"\n+    description:\n+      GPIO controller for the SoC GPIOs. This child node definition\n+      should follow the bindings specified in\n+      Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.yaml.\n+\n+  \"^pinctrl@[0-9a-f]+$\":\n+    # Child node\n+    type: object\n+    $ref: \"../pinctrl/brcm,bcm6358-pinctrl.yaml\"\n+    description:\n+      Pin controller for the SoC pins. This child node definition\n+      should follow the bindings specified in\n+      Documentation/devicetree/bindings/pinctrl/brcm,bcm6358-pinctrl.yaml.\n+\n+required:\n+  - \"#address-cells\"\n+  - compatible\n+  - ranges\n+  - reg\n+  - \"#size-cells\"\n+\n+additionalProperties: false\n+\n+examples:\n+  - |\n+    syscon@fffe0080 {\n+      #address-cells = <1>;\n+      #size-cells = <1>;\n+      compatible = \"brcm,bcm6358-gpio-sysctl\", \"syscon\", \"simple-mfd\";\n+      reg = <0xfffe0080 0x80>;\n+      ranges = <0 0xfffe0080 0x80>;\n+\n+      gpio@0 {\n+        compatible = \"brcm,bcm6358-gpio\";\n+        reg-names = \"dirout\", \"dat\";\n+        reg = <0x0 0x8>, <0x8 0x8>;\n+\n+        gpio-controller;\n+        gpio-ranges = <&pinctrl 0 0 40>;\n+        #gpio-cells = <2>;\n+      };\n+\n+      pinctrl: pinctrl@18 {\n+        compatible = \"brcm,bcm6358-pinctrl\";\n+        reg = <0x18 0x4>;\n+\n+        pinctrl_ebi_cs: ebi_cs-pins {\n+          function = \"ebi_cs\";\n+          groups = \"ebi_cs_grp\";\n+        };\n+\n+        pinctrl_uart1: uart1-pins {\n+          function = \"uart1\";\n+          groups = \"uart1_grp\";\n+        };\n+\n+        pinctrl_serial_led: serial_led-pins {\n+          function = \"serial_led\";\n+          groups = \"serial_led_grp\";\n+        };\n+\n+        pinctrl_legacy_led: legacy_led-pins {\n+          function = \"legacy_led\";\n+          groups = \"legacy_led_grp\";\n+        };\n+\n+        pinctrl_led: led-pins {\n+          function = \"led\";\n+          groups = \"led_grp\";\n+        };\n+\n+        pinctrl_spi_cs_23: spi_cs-pins {\n+          function = \"spi_cs\";\n+          groups = \"spi_cs_grp\";\n+        };\n+\n+        pinctrl_utopia: utopia-pins {\n+          function = \"utopia\";\n+          groups = \"utopia_grp\";\n+        };\n+\n+        pinctrl_pwm_syn_clk: pwm_syn_clk-pins {\n+          function = \"pwm_syn_clk\";\n+          groups = \"pwm_syn_clk_grp\";\n+        };\n+\n+        pinctrl_sys_irq: sys_irq-pins {\n+          function = \"sys_irq\";\n+          groups = \"sys_irq_grp\";\n+        };\n+      };\n+    };\n"
  },
  {
    "path": "target/linux/bmips/patches-5.10/061-v5.13-pinctrl-add-a-pincontrol-driver-for-BCM6358.patch",
    "content": "From 9494b16976e1ae3afc643abf638a25f2ce4c3f2b Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com>\nDate: Wed, 24 Mar 2021 09:19:11 +0100\nSubject: [PATCH 10/22] pinctrl: add a pincontrol driver for BCM6358\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nAdd a pincotrol driver for BCM6358. BCM6358 allow overlaying different\nfunctions onto the GPIO pins. It does not support configuring individual\npins but only whole groups. These groups may overlap, and still require\nthe directions to be set correctly in the GPIO register. In addition the\nfunctions register controls other, not directly mux related functions.\n\nCo-developed-by: Jonas Gorski <jonas.gorski@gmail.com>\nSigned-off-by: Jonas Gorski <jonas.gorski@gmail.com>\nSigned-off-by: Álvaro Fernández Rojas <noltari@gmail.com>\nLink: https://lore.kernel.org/r/20210324081923.20379-11-noltari@gmail.com\nSigned-off-by: Linus Walleij <linus.walleij@linaro.org>\n---\n drivers/pinctrl/bcm/Kconfig           |   8 +\n drivers/pinctrl/bcm/Makefile          |   1 +\n drivers/pinctrl/bcm/pinctrl-bcm6358.c | 369 ++++++++++++++++++++++++++\n 3 files changed, 378 insertions(+)\n create mode 100644 drivers/pinctrl/bcm/pinctrl-bcm6358.c\n\n--- a/drivers/pinctrl/bcm/Kconfig\n+++ b/drivers/pinctrl/bcm/Kconfig\n@@ -44,6 +44,14 @@ config PINCTRL_BCM6328\n \thelp\n \t   Say Y here to enable the Broadcom BCM6328 GPIO driver.\n \n+config PINCTRL_BCM6358\n+\tbool \"Broadcom BCM6358 GPIO driver\"\n+\tdepends on (BMIPS_GENERIC || COMPILE_TEST)\n+\tselect PINCTRL_BCM63XX\n+\tdefault BMIPS_GENERIC\n+\thelp\n+\t   Say Y here to enable the Broadcom BCM6358 GPIO driver.\n+\n config PINCTRL_IPROC_GPIO\n \tbool \"Broadcom iProc GPIO (with PINCONF) driver\"\n \tdepends on OF_GPIO && (ARCH_BCM_IPROC || COMPILE_TEST)\n--- a/drivers/pinctrl/bcm/Makefile\n+++ b/drivers/pinctrl/bcm/Makefile\n@@ -5,6 +5,7 @@ obj-$(CONFIG_PINCTRL_BCM281XX)\t\t+= pinct\n obj-$(CONFIG_PINCTRL_BCM2835)\t\t+= pinctrl-bcm2835.o\n obj-$(CONFIG_PINCTRL_BCM63XX)\t\t+= pinctrl-bcm63xx.o\n obj-$(CONFIG_PINCTRL_BCM6328)\t\t+= pinctrl-bcm6328.o\n+obj-$(CONFIG_PINCTRL_BCM6358)\t\t+= pinctrl-bcm6358.o\n obj-$(CONFIG_PINCTRL_IPROC_GPIO)\t+= pinctrl-iproc-gpio.o\n obj-$(CONFIG_PINCTRL_CYGNUS_MUX)\t+= pinctrl-cygnus-mux.o\n obj-$(CONFIG_PINCTRL_NS)\t\t+= pinctrl-ns.o\n--- /dev/null\n+++ b/drivers/pinctrl/bcm/pinctrl-bcm6358.c\n@@ -0,0 +1,369 @@\n+// SPDX-License-Identifier: GPL-2.0+\n+/*\n+ * Driver for BCM6358 GPIO unit (pinctrl + GPIO)\n+ *\n+ * Copyright (C) 2021 Álvaro Fernández Rojas <noltari@gmail.com>\n+ * Copyright (C) 2016 Jonas Gorski <jonas.gorski@gmail.com>\n+ */\n+\n+#include <linux/bits.h>\n+#include <linux/gpio/driver.h>\n+#include <linux/kernel.h>\n+#include <linux/of.h>\n+#include <linux/pinctrl/pinmux.h>\n+#include <linux/platform_device.h>\n+#include <linux/regmap.h>\n+\n+#include \"../pinctrl-utils.h\"\n+\n+#include \"pinctrl-bcm63xx.h\"\n+\n+#define BCM6358_NUM_GPIOS\t\t40\n+\n+#define BCM6358_MODE_REG\t\t0x18\n+#define  BCM6358_MODE_MUX_NONE\t\t0\n+#define  BCM6358_MODE_MUX_EBI_CS\tBIT(5)\n+#define  BCM6358_MODE_MUX_UART1\t\tBIT(6)\n+#define  BCM6358_MODE_MUX_SPI_CS\tBIT(7)\n+#define  BCM6358_MODE_MUX_ASYNC_MODEM\tBIT(8)\n+#define  BCM6358_MODE_MUX_LEGACY_LED\tBIT(9)\n+#define  BCM6358_MODE_MUX_SERIAL_LED\tBIT(10)\n+#define  BCM6358_MODE_MUX_LED\t\tBIT(11)\n+#define  BCM6358_MODE_MUX_UTOPIA\tBIT(12)\n+#define  BCM6358_MODE_MUX_CLKRST\tBIT(13)\n+#define  BCM6358_MODE_MUX_PWM_SYN_CLK\tBIT(14)\n+#define  BCM6358_MODE_MUX_SYS_IRQ\tBIT(15)\n+\n+struct bcm6358_pingroup {\n+\tconst char *name;\n+\tconst unsigned * const pins;\n+\tconst unsigned num_pins;\n+\n+\tconst uint16_t mode_val;\n+\n+\t/* non-GPIO function muxes require the gpio direction to be set */\n+\tconst uint16_t direction;\n+};\n+\n+struct bcm6358_function {\n+\tconst char *name;\n+\tconst char * const *groups;\n+\tconst unsigned num_groups;\n+};\n+\n+struct bcm6358_priv {\n+\tstruct regmap_field *overlays;\n+};\n+\n+#define BCM6358_GPIO_PIN(a, b, bit1, bit2, bit3)\t\t\\\n+\t{\t\t\t\t\t\t\t\\\n+\t\t.number = a,\t\t\t\t\t\\\n+\t\t.name = b,\t\t\t\t\t\\\n+\t\t.drv_data = (void *)(BCM6358_MODE_MUX_##bit1 |\t\\\n+\t\t\t\t     BCM6358_MODE_MUX_##bit2 |\t\\\n+\t\t\t\t     BCM6358_MODE_MUX_##bit3),\t\\\n+\t}\n+\n+static const struct pinctrl_pin_desc bcm6358_pins[] = {\n+\tBCM6358_GPIO_PIN(0, \"gpio0\", LED, NONE, NONE),\n+\tBCM6358_GPIO_PIN(1, \"gpio1\", LED, NONE, NONE),\n+\tBCM6358_GPIO_PIN(2, \"gpio2\", LED, NONE, NONE),\n+\tBCM6358_GPIO_PIN(3, \"gpio3\", LED, NONE, NONE),\n+\tPINCTRL_PIN(4, \"gpio4\"),\n+\tBCM6358_GPIO_PIN(5, \"gpio5\", SYS_IRQ, NONE, NONE),\n+\tBCM6358_GPIO_PIN(6, \"gpio6\", SERIAL_LED, NONE, NONE),\n+\tBCM6358_GPIO_PIN(7, \"gpio7\", SERIAL_LED, NONE, NONE),\n+\tBCM6358_GPIO_PIN(8, \"gpio8\", PWM_SYN_CLK, NONE, NONE),\n+\tBCM6358_GPIO_PIN(9, \"gpio09\", LEGACY_LED, NONE, NONE),\n+\tBCM6358_GPIO_PIN(10, \"gpio10\", LEGACY_LED, NONE, NONE),\n+\tBCM6358_GPIO_PIN(11, \"gpio11\", LEGACY_LED, NONE, NONE),\n+\tBCM6358_GPIO_PIN(12, \"gpio12\", LEGACY_LED, ASYNC_MODEM, UTOPIA),\n+\tBCM6358_GPIO_PIN(13, \"gpio13\", LEGACY_LED, ASYNC_MODEM, UTOPIA),\n+\tBCM6358_GPIO_PIN(14, \"gpio14\", LEGACY_LED, ASYNC_MODEM, UTOPIA),\n+\tBCM6358_GPIO_PIN(15, \"gpio15\", LEGACY_LED, ASYNC_MODEM, UTOPIA),\n+\tPINCTRL_PIN(16, \"gpio16\"),\n+\tPINCTRL_PIN(17, \"gpio17\"),\n+\tPINCTRL_PIN(18, \"gpio18\"),\n+\tPINCTRL_PIN(19, \"gpio19\"),\n+\tPINCTRL_PIN(20, \"gpio20\"),\n+\tPINCTRL_PIN(21, \"gpio21\"),\n+\tBCM6358_GPIO_PIN(22, \"gpio22\", UTOPIA, NONE, NONE),\n+\tBCM6358_GPIO_PIN(23, \"gpio23\", UTOPIA, NONE, NONE),\n+\tBCM6358_GPIO_PIN(24, \"gpio24\", UTOPIA, NONE, NONE),\n+\tBCM6358_GPIO_PIN(25, \"gpio25\", UTOPIA, NONE, NONE),\n+\tBCM6358_GPIO_PIN(26, \"gpio26\", UTOPIA, NONE, NONE),\n+\tBCM6358_GPIO_PIN(27, \"gpio27\", UTOPIA, NONE, NONE),\n+\tBCM6358_GPIO_PIN(28, \"gpio28\", UTOPIA, UART1, NONE),\n+\tBCM6358_GPIO_PIN(29, \"gpio29\", UTOPIA, UART1, NONE),\n+\tBCM6358_GPIO_PIN(30, \"gpio30\", UTOPIA, UART1, EBI_CS),\n+\tBCM6358_GPIO_PIN(31, \"gpio31\", UTOPIA, UART1, EBI_CS),\n+\tBCM6358_GPIO_PIN(32, \"gpio32\", SPI_CS, NONE, NONE),\n+\tBCM6358_GPIO_PIN(33, \"gpio33\", SPI_CS, NONE, NONE),\n+\tPINCTRL_PIN(34, \"gpio34\"),\n+\tPINCTRL_PIN(35, \"gpio35\"),\n+\tPINCTRL_PIN(36, \"gpio36\"),\n+\tPINCTRL_PIN(37, \"gpio37\"),\n+\tPINCTRL_PIN(38, \"gpio38\"),\n+\tPINCTRL_PIN(39, \"gpio39\"),\n+};\n+\n+static unsigned ebi_cs_grp_pins[] = { 30, 31 };\n+\n+static unsigned uart1_grp_pins[] = { 28, 29, 30, 31 };\n+\n+static unsigned spi_cs_grp_pins[] = { 32, 33 };\n+\n+static unsigned async_modem_grp_pins[] = { 12, 13, 14, 15 };\n+\n+static unsigned serial_led_grp_pins[] = { 6, 7 };\n+\n+static unsigned legacy_led_grp_pins[] = { 9, 10, 11, 12, 13, 14, 15 };\n+\n+static unsigned led_grp_pins[] = { 0, 1, 2, 3 };\n+\n+static unsigned utopia_grp_pins[] = {\n+\t12, 13, 14, 15, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,\n+};\n+\n+static unsigned pwm_syn_clk_grp_pins[] = { 8 };\n+\n+static unsigned sys_irq_grp_pins[] = { 5 };\n+\n+#define BCM6358_GPIO_MUX_GROUP(n, bit, dir)\t\t\t\\\n+\t{\t\t\t\t\t\t\t\\\n+\t\t.name = #n,\t\t\t\t\t\\\n+\t\t.pins = n##_pins,\t\t\t\t\\\n+\t\t.num_pins = ARRAY_SIZE(n##_pins),\t\t\\\n+\t\t.mode_val = BCM6358_MODE_MUX_##bit,\t\t\\\n+\t\t.direction = dir,\t\t\t\t\\\n+\t}\n+\n+static const struct bcm6358_pingroup bcm6358_groups[] = {\n+\tBCM6358_GPIO_MUX_GROUP(ebi_cs_grp, EBI_CS, 0x3),\n+\tBCM6358_GPIO_MUX_GROUP(uart1_grp, UART1, 0x2),\n+\tBCM6358_GPIO_MUX_GROUP(spi_cs_grp, SPI_CS, 0x6),\n+\tBCM6358_GPIO_MUX_GROUP(async_modem_grp, ASYNC_MODEM, 0x6),\n+\tBCM6358_GPIO_MUX_GROUP(legacy_led_grp, LEGACY_LED, 0x7f),\n+\tBCM6358_GPIO_MUX_GROUP(serial_led_grp, SERIAL_LED, 0x3),\n+\tBCM6358_GPIO_MUX_GROUP(led_grp, LED, 0xf),\n+\tBCM6358_GPIO_MUX_GROUP(utopia_grp, UTOPIA, 0x000f),\n+\tBCM6358_GPIO_MUX_GROUP(pwm_syn_clk_grp, PWM_SYN_CLK, 0x1),\n+\tBCM6358_GPIO_MUX_GROUP(sys_irq_grp, SYS_IRQ, 0x1),\n+};\n+\n+static const char * const ebi_cs_groups[] = {\n+\t\"ebi_cs_grp\"\n+};\n+\n+static const char * const uart1_groups[] = {\n+\t\"uart1_grp\"\n+};\n+\n+static const char * const spi_cs_2_3_groups[] = {\n+\t\"spi_cs_2_3_grp\"\n+};\n+\n+static const char * const async_modem_groups[] = {\n+\t\"async_modem_grp\"\n+};\n+\n+static const char * const legacy_led_groups[] = {\n+\t\"legacy_led_grp\",\n+};\n+\n+static const char * const serial_led_groups[] = {\n+\t\"serial_led_grp\",\n+};\n+\n+static const char * const led_groups[] = {\n+\t\"led_grp\",\n+};\n+\n+static const char * const clkrst_groups[] = {\n+\t\"clkrst_grp\",\n+};\n+\n+static const char * const pwm_syn_clk_groups[] = {\n+\t\"pwm_syn_clk_grp\",\n+};\n+\n+static const char * const sys_irq_groups[] = {\n+\t\"sys_irq_grp\",\n+};\n+\n+#define BCM6358_FUN(n)\t\t\t\t\t\\\n+\t{\t\t\t\t\t\t\\\n+\t\t.name = #n,\t\t\t\t\\\n+\t\t.groups = n##_groups,\t\t\t\\\n+\t\t.num_groups = ARRAY_SIZE(n##_groups),\t\\\n+\t}\n+\n+static const struct bcm6358_function bcm6358_funcs[] = {\n+\tBCM6358_FUN(ebi_cs),\n+\tBCM6358_FUN(uart1),\n+\tBCM6358_FUN(spi_cs_2_3),\n+\tBCM6358_FUN(async_modem),\n+\tBCM6358_FUN(legacy_led),\n+\tBCM6358_FUN(serial_led),\n+\tBCM6358_FUN(led),\n+\tBCM6358_FUN(clkrst),\n+\tBCM6358_FUN(pwm_syn_clk),\n+\tBCM6358_FUN(sys_irq),\n+};\n+\n+static int bcm6358_pinctrl_get_group_count(struct pinctrl_dev *pctldev)\n+{\n+\treturn ARRAY_SIZE(bcm6358_groups);\n+}\n+\n+static const char *bcm6358_pinctrl_get_group_name(struct pinctrl_dev *pctldev,\n+\t\t\t\t\t\t  unsigned group)\n+{\n+\treturn bcm6358_groups[group].name;\n+}\n+\n+static int bcm6358_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,\n+\t\t\t\t\t  unsigned group, const unsigned **pins,\n+\t\t\t\t\t  unsigned *num_pins)\n+{\n+\t*pins = bcm6358_groups[group].pins;\n+\t*num_pins = bcm6358_groups[group].num_pins;\n+\n+\treturn 0;\n+}\n+\n+static int bcm6358_pinctrl_get_func_count(struct pinctrl_dev *pctldev)\n+{\n+\treturn ARRAY_SIZE(bcm6358_funcs);\n+}\n+\n+static const char *bcm6358_pinctrl_get_func_name(struct pinctrl_dev *pctldev,\n+\t\t\t\t\t\t unsigned selector)\n+{\n+\treturn bcm6358_funcs[selector].name;\n+}\n+\n+static int bcm6358_pinctrl_get_groups(struct pinctrl_dev *pctldev,\n+\t\t\t\t      unsigned selector,\n+\t\t\t\t      const char * const **groups,\n+\t\t\t\t      unsigned * const num_groups)\n+{\n+\t*groups = bcm6358_funcs[selector].groups;\n+\t*num_groups = bcm6358_funcs[selector].num_groups;\n+\n+\treturn 0;\n+}\n+\n+static int bcm6358_pinctrl_set_mux(struct pinctrl_dev *pctldev,\n+\t\t\t\t   unsigned selector, unsigned group)\n+{\n+\tstruct bcm63xx_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);\n+\tstruct bcm6358_priv *priv = pc->driver_data;\n+\tconst struct bcm6358_pingroup *pg = &bcm6358_groups[group];\n+\tunsigned int val = pg->mode_val;\n+\tunsigned int mask = val;\n+\tunsigned pin;\n+\n+\tfor (pin = 0; pin < pg->num_pins; pin++)\n+\t\tmask |= (unsigned long)bcm6358_pins[pin].drv_data;\n+\n+\tregmap_field_update_bits(priv->overlays, mask, val);\n+\n+\tfor (pin = 0; pin < pg->num_pins; pin++) {\n+\t\tstruct pinctrl_gpio_range *range;\n+\t\tunsigned int hw_gpio = bcm6358_pins[pin].number;\n+\n+\t\trange = pinctrl_find_gpio_range_from_pin(pctldev, hw_gpio);\n+\t\tif (range) {\n+\t\t\tstruct gpio_chip *gc = range->gc;\n+\n+\t\t\tif (pg->direction & BIT(pin))\n+\t\t\t\tgc->direction_output(gc, hw_gpio, 0);\n+\t\t\telse\n+\t\t\t\tgc->direction_input(gc, hw_gpio);\n+\t\t}\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int bcm6358_gpio_request_enable(struct pinctrl_dev *pctldev,\n+\t\t\t\t       struct pinctrl_gpio_range *range,\n+\t\t\t\t       unsigned offset)\n+{\n+\tstruct bcm63xx_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);\n+\tstruct bcm6358_priv *priv = pc->driver_data;\n+\tunsigned int mask;\n+\n+\tmask = (unsigned long) bcm6358_pins[offset].drv_data;\n+\tif (!mask)\n+\t\treturn 0;\n+\n+\t/* disable all functions using this pin */\n+\treturn regmap_field_update_bits(priv->overlays, mask, 0);\n+}\n+\n+static struct pinctrl_ops bcm6358_pctl_ops = {\n+\t.dt_free_map = pinctrl_utils_free_map,\n+\t.dt_node_to_map = pinconf_generic_dt_node_to_map_pin,\n+\t.get_group_name = bcm6358_pinctrl_get_group_name,\n+\t.get_group_pins = bcm6358_pinctrl_get_group_pins,\n+\t.get_groups_count = bcm6358_pinctrl_get_group_count,\n+};\n+\n+static struct pinmux_ops bcm6358_pmx_ops = {\n+\t.get_function_groups = bcm6358_pinctrl_get_groups,\n+\t.get_function_name = bcm6358_pinctrl_get_func_name,\n+\t.get_functions_count = bcm6358_pinctrl_get_func_count,\n+\t.gpio_request_enable = bcm6358_gpio_request_enable,\n+\t.set_mux = bcm6358_pinctrl_set_mux,\n+\t.strict = true,\n+};\n+\n+static const struct bcm63xx_pinctrl_soc bcm6358_soc = {\n+\t.ngpios = BCM6358_NUM_GPIOS,\n+\t.npins = ARRAY_SIZE(bcm6358_pins),\n+\t.pctl_ops = &bcm6358_pctl_ops,\n+\t.pins = bcm6358_pins,\n+\t.pmx_ops = &bcm6358_pmx_ops,\n+};\n+\n+static int bcm6358_pinctrl_probe(struct platform_device *pdev)\n+{\n+\tstruct reg_field overlays = REG_FIELD(BCM6358_MODE_REG, 0, 15);\n+\tstruct device *dev = &pdev->dev;\n+\tstruct bcm63xx_pinctrl *pc;\n+\tstruct bcm6358_priv *priv;\n+\tint err;\n+\n+\tpriv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);\n+\tif (!priv)\n+\t\treturn -ENOMEM;\n+\n+\terr = bcm63xx_pinctrl_probe(pdev, &bcm6358_soc, (void *) priv);\n+\tif (err)\n+\t\treturn err;\n+\n+\tpc = platform_get_drvdata(pdev);\n+\n+\tpriv->overlays = devm_regmap_field_alloc(dev, pc->regs, overlays);\n+\tif (IS_ERR(priv->overlays))\n+\t\treturn PTR_ERR(priv->overlays);\n+\n+\treturn 0;\n+}\n+\n+static const struct of_device_id bcm6358_pinctrl_match[] = {\n+\t{ .compatible = \"brcm,bcm6358-pinctrl\", },\n+\t{ /* sentinel */ }\n+};\n+\n+static struct platform_driver bcm6358_pinctrl_driver = {\n+\t.probe = bcm6358_pinctrl_probe,\n+\t.driver = {\n+\t\t.name = \"bcm6358-pinctrl\",\n+\t\t.of_match_table = bcm6358_pinctrl_match,\n+\t},\n+};\n+\n+builtin_platform_driver(bcm6358_pinctrl_driver);\n"
  },
  {
    "path": "target/linux/bmips/patches-5.10/062-v5.13-dt-bindings-add-BCM6362-pincontroller-binding-docume.patch",
    "content": "From 6e4b5e1fc77513359989112e002e08553d0d8d5c Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com>\nDate: Wed, 24 Mar 2021 09:19:12 +0100\nSubject: [PATCH 11/22] dt-bindings: add BCM6362 pincontroller binding\n documentation\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nAdd binding documentation for the pincontrol core found in BCM6362 SoCs.\n\nCo-developed-by: Jonas Gorski <jonas.gorski@gmail.com>\nSigned-off-by: Jonas Gorski <jonas.gorski@gmail.com>\nSigned-off-by: Álvaro Fernández Rojas <noltari@gmail.com>\nReviewed-by: Rob Herring <robh@kernel.org>\nLink: https://lore.kernel.org/r/20210324081923.20379-12-noltari@gmail.com\nSigned-off-by: Linus Walleij <linus.walleij@linaro.org>\n---\n .../pinctrl/brcm,bcm6362-pinctrl.yaml         | 206 ++++++++++++++++++\n 1 file changed, 206 insertions(+)\n create mode 100644 Documentation/devicetree/bindings/pinctrl/brcm,bcm6362-pinctrl.yaml\n\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/pinctrl/brcm,bcm6362-pinctrl.yaml\n@@ -0,0 +1,206 @@\n+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause\n+%YAML 1.2\n+---\n+$id: http://devicetree.org/schemas/pinctrl/brcm,bcm6362-pinctrl.yaml#\n+$schema: http://devicetree.org/meta-schemas/core.yaml#\n+\n+title: Broadcom BCM6362 pin controller\n+\n+maintainers:\n+  - Álvaro Fernández Rojas <noltari@gmail.com>\n+  - Jonas Gorski <jonas.gorski@gmail.com>\n+\n+description:\n+  Bindings for Broadcom's BCM6362 memory-mapped pin controller.\n+\n+properties:\n+  compatible:\n+    const: brcm,bcm6362-pinctrl\n+\n+  reg:\n+    maxItems: 2\n+\n+patternProperties:\n+  '-pins$':\n+    type: object\n+    $ref: pinmux-node.yaml#\n+\n+    properties:\n+      function:\n+        enum: [ usb_device_led, sys_irq, serial_led_clk, serial_led_data,\n+                robosw_led_data, robosw_led_clk, robosw_led0, robosw_led1,\n+                inet_led, spi_cs2, spi_cs3, ntr_pulse, uart1_scts,\n+                uart1_srts, uart1_sdin, uart1_sdout, adsl_spi_miso,\n+                adsl_spi_mosi, adsl_spi_clk, adsl_spi_cs, ephy0_led,\n+                ephy1_led, ephy2_led, ephy3_led, ext_irq0, ext_irq1,\n+                ext_irq2, ext_irq3, nand ]\n+\n+      pins:\n+        enum: [ gpio0, gpio1, gpio2, gpio3, gpio4, gpio5, gpio6, gpio7,\n+                gpio8, gpio9, gpio10, gpio11, gpio12, gpio13, gpio14,\n+                gpio15, gpio16, gpio17, gpio18, gpio19, gpio20, gpio21,\n+                gpio22, gpio23, gpio24, gpio25, gpio26, gpio27, nand_grp ]\n+\n+required:\n+  - compatible\n+  - reg\n+\n+additionalProperties: false\n+\n+examples:\n+  - |\n+    pinctrl@18 {\n+      compatible = \"brcm,bcm6362-pinctrl\";\n+      reg = <0x18 0x10>, <0x38 0x4>;\n+\n+      pinctrl_usb_device_led: usb_device_led-pins {\n+        function = \"usb_device_led\";\n+        pins = \"gpio0\";\n+      };\n+\n+      pinctrl_sys_irq: sys_irq-pins {\n+        function = \"sys_irq\";\n+        pins = \"gpio1\";\n+      };\n+\n+      pinctrl_serial_led: serial_led-pins {\n+        pinctrl_serial_led_clk: serial_led_clk-pins {\n+          function = \"serial_led_clk\";\n+          pins = \"gpio2\";\n+        };\n+\n+        pinctrl_serial_led_data: serial_led_data-pins {\n+          function = \"serial_led_data\";\n+          pins = \"gpio3\";\n+        };\n+      };\n+\n+      pinctrl_robosw_led_data: robosw_led_data-pins {\n+        function = \"robosw_led_data\";\n+        pins = \"gpio4\";\n+      };\n+\n+      pinctrl_robosw_led_clk: robosw_led_clk-pins {\n+        function = \"robosw_led_clk\";\n+        pins = \"gpio5\";\n+      };\n+\n+      pinctrl_robosw_led0: robosw_led0-pins {\n+        function = \"robosw_led0\";\n+        pins = \"gpio6\";\n+      };\n+\n+      pinctrl_robosw_led1: robosw_led1-pins {\n+        function = \"robosw_led1\";\n+        pins = \"gpio7\";\n+      };\n+\n+      pinctrl_inet_led: inet_led-pins {\n+        function = \"inet_led\";\n+        pins = \"gpio8\";\n+      };\n+\n+      pinctrl_spi_cs2: spi_cs2-pins {\n+        function = \"spi_cs2\";\n+        pins = \"gpio9\";\n+      };\n+\n+      pinctrl_spi_cs3: spi_cs3-pins {\n+        function = \"spi_cs3\";\n+        pins = \"gpio10\";\n+      };\n+\n+      pinctrl_ntr_pulse: ntr_pulse-pins {\n+        function = \"ntr_pulse\";\n+        pins = \"gpio11\";\n+      };\n+\n+      pinctrl_uart1_scts: uart1_scts-pins {\n+        function = \"uart1_scts\";\n+        pins = \"gpio12\";\n+      };\n+\n+      pinctrl_uart1_srts: uart1_srts-pins {\n+        function = \"uart1_srts\";\n+        pins = \"gpio13\";\n+      };\n+\n+      pinctrl_uart1: uart1-pins {\n+        pinctrl_uart1_sdin: uart1_sdin-pins {\n+          function = \"uart1_sdin\";\n+          pins = \"gpio14\";\n+        };\n+\n+        pinctrl_uart1_sdout: uart1_sdout-pins {\n+          function = \"uart1_sdout\";\n+          pins = \"gpio15\";\n+        };\n+      };\n+\n+      pinctrl_adsl_spi: adsl_spi-pins {\n+        pinctrl_adsl_spi_miso: adsl_spi_miso-pins {\n+          function = \"adsl_spi_miso\";\n+          pins = \"gpio16\";\n+        };\n+\n+        pinctrl_adsl_spi_mosi: adsl_spi_mosi-pins {\n+          function = \"adsl_spi_mosi\";\n+          pins = \"gpio17\";\n+        };\n+\n+        pinctrl_adsl_spi_clk: adsl_spi_clk-pins {\n+          function = \"adsl_spi_clk\";\n+          pins = \"gpio18\";\n+        };\n+\n+        pinctrl_adsl_spi_cs: adsl_spi_cs-pins {\n+          function = \"adsl_spi_cs\";\n+          pins = \"gpio19\";\n+        };\n+      };\n+\n+      pinctrl_ephy0_led: ephy0_led-pins {\n+        function = \"ephy0_led\";\n+        pins = \"gpio20\";\n+      };\n+\n+      pinctrl_ephy1_led: ephy1_led-pins {\n+        function = \"ephy1_led\";\n+        pins = \"gpio21\";\n+      };\n+\n+      pinctrl_ephy2_led: ephy2_led-pins {\n+        function = \"ephy2_led\";\n+        pins = \"gpio22\";\n+      };\n+\n+      pinctrl_ephy3_led: ephy3_led-pins {\n+        function = \"ephy3_led\";\n+        pins = \"gpio23\";\n+      };\n+\n+      pinctrl_ext_irq0: ext_irq0-pins {\n+        function = \"ext_irq0\";\n+        pins = \"gpio24\";\n+      };\n+\n+      pinctrl_ext_irq1: ext_irq1-pins {\n+        function = \"ext_irq1\";\n+        pins = \"gpio25\";\n+      };\n+\n+      pinctrl_ext_irq2: ext_irq2-pins {\n+        function = \"ext_irq2\";\n+        pins = \"gpio26\";\n+      };\n+\n+      pinctrl_ext_irq3: ext_irq3-pins {\n+        function = \"ext_irq3\";\n+        pins = \"gpio27\";\n+      };\n+\n+      pinctrl_nand: nand-pins {\n+        function = \"nand\";\n+        group = \"nand_grp\";\n+      };\n+    };\n"
  },
  {
    "path": "target/linux/bmips/patches-5.10/063-v5.13-dt-bindings-add-BCM6362-GPIO-sysctl-binding-document.patch",
    "content": "From 7ca989eafbd6ce1c216a775556c4893baab1959b Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com>\nDate: Wed, 24 Mar 2021 09:19:13 +0100\nSubject: [PATCH 12/22] dt-bindings: add BCM6362 GPIO sysctl binding\n documentation\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nAdd binding documentation for the GPIO sysctl found in BCM6362 SoCs.\n\nSigned-off-by: Álvaro Fernández Rojas <noltari@gmail.com>\nReviewed-by: Rob Herring <robh@kernel.org>\nLink: https://lore.kernel.org/r/20210324081923.20379-13-noltari@gmail.com\nSigned-off-by: Linus Walleij <linus.walleij@linaro.org>\n---\n .../mfd/brcm,bcm6362-gpio-sysctl.yaml         | 236 ++++++++++++++++++\n 1 file changed, 236 insertions(+)\n create mode 100644 Documentation/devicetree/bindings/mfd/brcm,bcm6362-gpio-sysctl.yaml\n\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/mfd/brcm,bcm6362-gpio-sysctl.yaml\n@@ -0,0 +1,236 @@\n+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)\n+%YAML 1.2\n+---\n+$id: http://devicetree.org/schemas/mfd/brcm,bcm6362-gpio-sysctl.yaml#\n+$schema: http://devicetree.org/meta-schemas/core.yaml#\n+\n+title: Broadcom BCM6362 GPIO System Controller Device Tree Bindings\n+\n+maintainers:\n+  - Álvaro Fernández Rojas <noltari@gmail.com>\n+  - Jonas Gorski <jonas.gorski@gmail.com>\n+\n+description:\n+  Broadcom BCM6362 SoC GPIO system controller which provides a register map\n+  for controlling the GPIO and pins of the SoC.\n+\n+properties:\n+  \"#address-cells\": true\n+\n+  \"#size-cells\": true\n+\n+  compatible:\n+    items:\n+      - const: brcm,bcm6362-gpio-sysctl\n+      - const: syscon\n+      - const: simple-mfd\n+\n+  ranges:\n+    maxItems: 1\n+\n+  reg:\n+    maxItems: 1\n+\n+patternProperties:\n+  \"^gpio@[0-9a-f]+$\":\n+    # Child node\n+    type: object\n+    $ref: \"../gpio/brcm,bcm6345-gpio.yaml\"\n+    description:\n+      GPIO controller for the SoC GPIOs. This child node definition\n+      should follow the bindings specified in\n+      Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.yaml.\n+\n+  \"^pinctrl@[0-9a-f]+$\":\n+    # Child node\n+    type: object\n+    $ref: \"../pinctrl/brcm,bcm6362-pinctrl.yaml\"\n+    description:\n+      Pin controller for the SoC pins. This child node definition\n+      should follow the bindings specified in\n+      Documentation/devicetree/bindings/pinctrl/brcm,bcm6362-pinctrl.yaml.\n+\n+required:\n+  - \"#address-cells\"\n+  - compatible\n+  - ranges\n+  - reg\n+  - \"#size-cells\"\n+\n+additionalProperties: false\n+\n+examples:\n+  - |\n+    syscon@10000080 {\n+      #address-cells = <1>;\n+      #size-cells = <1>;\n+      compatible = \"brcm,bcm6362-gpio-sysctl\", \"syscon\", \"simple-mfd\";\n+      reg = <0x10000080 0x80>;\n+      ranges = <0 0x10000080 0x80>;\n+\n+      gpio@0 {\n+        compatible = \"brcm,bcm6362-gpio\";\n+        reg-names = \"dirout\", \"dat\";\n+        reg = <0x0 0x8>, <0x8 0x8>;\n+\n+        gpio-controller;\n+        gpio-ranges = <&pinctrl 0 0 48>;\n+        #gpio-cells = <2>;\n+      };\n+\n+      pinctrl: pinctrl@18 {\n+        compatible = \"brcm,bcm6362-pinctrl\";\n+        reg = <0x18 0x10>, <0x38 0x4>;\n+\n+        pinctrl_usb_device_led: usb_device_led-pins {\n+          function = \"usb_device_led\";\n+          pins = \"gpio0\";\n+        };\n+\n+        pinctrl_sys_irq: sys_irq-pins {\n+          function = \"sys_irq\";\n+          pins = \"gpio1\";\n+        };\n+\n+        pinctrl_serial_led: serial_led-pins {\n+          pinctrl_serial_led_clk: serial_led_clk-pins {\n+            function = \"serial_led_clk\";\n+            pins = \"gpio2\";\n+          };\n+\n+          pinctrl_serial_led_data: serial_led_data-pins {\n+            function = \"serial_led_data\";\n+            pins = \"gpio3\";\n+          };\n+        };\n+\n+        pinctrl_robosw_led_data: robosw_led_data-pins {\n+          function = \"robosw_led_data\";\n+          pins = \"gpio4\";\n+        };\n+\n+        pinctrl_robosw_led_clk: robosw_led_clk-pins {\n+          function = \"robosw_led_clk\";\n+          pins = \"gpio5\";\n+        };\n+\n+        pinctrl_robosw_led0: robosw_led0-pins {\n+          function = \"robosw_led0\";\n+          pins = \"gpio6\";\n+        };\n+\n+        pinctrl_robosw_led1: robosw_led1-pins {\n+          function = \"robosw_led1\";\n+          pins = \"gpio7\";\n+        };\n+\n+        pinctrl_inet_led: inet_led-pins {\n+          function = \"inet_led\";\n+          pins = \"gpio8\";\n+        };\n+\n+        pinctrl_spi_cs2: spi_cs2-pins {\n+          function = \"spi_cs2\";\n+          pins = \"gpio9\";\n+        };\n+\n+        pinctrl_spi_cs3: spi_cs3-pins {\n+          function = \"spi_cs3\";\n+          pins = \"gpio10\";\n+        };\n+\n+        pinctrl_ntr_pulse: ntr_pulse-pins {\n+          function = \"ntr_pulse\";\n+          pins = \"gpio11\";\n+        };\n+\n+        pinctrl_uart1_scts: uart1_scts-pins {\n+          function = \"uart1_scts\";\n+          pins = \"gpio12\";\n+        };\n+\n+        pinctrl_uart1_srts: uart1_srts-pins {\n+          function = \"uart1_srts\";\n+          pins = \"gpio13\";\n+        };\n+\n+        pinctrl_uart1: uart1-pins {\n+          pinctrl_uart1_sdin: uart1_sdin-pins {\n+            function = \"uart1_sdin\";\n+            pins = \"gpio14\";\n+          };\n+\n+          pinctrl_uart1_sdout: uart1_sdout-pins {\n+            function = \"uart1_sdout\";\n+            pins = \"gpio15\";\n+          };\n+        };\n+\n+        pinctrl_adsl_spi: adsl_spi-pins {\n+          pinctrl_adsl_spi_miso: adsl_spi_miso-pins {\n+            function = \"adsl_spi_miso\";\n+            pins = \"gpio16\";\n+          };\n+\n+          pinctrl_adsl_spi_mosi: adsl_spi_mosi-pins {\n+            function = \"adsl_spi_mosi\";\n+            pins = \"gpio17\";\n+          };\n+\n+          pinctrl_adsl_spi_clk: adsl_spi_clk-pins {\n+            function = \"adsl_spi_clk\";\n+            pins = \"gpio18\";\n+          };\n+\n+          pinctrl_adsl_spi_cs: adsl_spi_cs-pins {\n+            function = \"adsl_spi_cs\";\n+            pins = \"gpio19\";\n+          };\n+        };\n+\n+        pinctrl_ephy0_led: ephy0_led-pins {\n+          function = \"ephy0_led\";\n+          pins = \"gpio20\";\n+        };\n+\n+        pinctrl_ephy1_led: ephy1_led-pins {\n+          function = \"ephy1_led\";\n+          pins = \"gpio21\";\n+        };\n+\n+        pinctrl_ephy2_led: ephy2_led-pins {\n+          function = \"ephy2_led\";\n+          pins = \"gpio22\";\n+        };\n+\n+        pinctrl_ephy3_led: ephy3_led-pins {\n+          function = \"ephy3_led\";\n+          pins = \"gpio23\";\n+        };\n+\n+        pinctrl_ext_irq0: ext_irq0-pins {\n+          function = \"ext_irq0\";\n+          pins = \"gpio24\";\n+        };\n+\n+        pinctrl_ext_irq1: ext_irq1-pins {\n+          function = \"ext_irq1\";\n+          pins = \"gpio25\";\n+        };\n+\n+        pinctrl_ext_irq2: ext_irq2-pins {\n+          function = \"ext_irq2\";\n+          pins = \"gpio26\";\n+        };\n+\n+        pinctrl_ext_irq3: ext_irq3-pins {\n+          function = \"ext_irq3\";\n+          pins = \"gpio27\";\n+        };\n+\n+        pinctrl_nand: nand-pins {\n+          function = \"nand\";\n+          group = \"nand_grp\";\n+        };\n+      };\n+    };\n"
  },
  {
    "path": "target/linux/bmips/patches-5.10/064-v5.13-pinctrl-add-a-pincontrol-driver-for-BCM6362.patch",
    "content": "From 705791e23ecd93d6c2697234fdf0c22b499c0a5b Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com>\nDate: Wed, 24 Mar 2021 09:19:14 +0100\nSubject: [PATCH 13/22] pinctrl: add a pincontrol driver for BCM6362\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nAdd a pincotrol driver for BCM6362. BCM6362 allows muxing individual\nGPIO pins to the LED controller, to be available by the integrated\nwifi, or other functions. It also supports overlay groups, of which\nonly NAND is documented.\n\nCo-developed-by: Jonas Gorski <jonas.gorski@gmail.com>\nSigned-off-by: Jonas Gorski <jonas.gorski@gmail.com>\nSigned-off-by: Álvaro Fernández Rojas <noltari@gmail.com>\nLink: https://lore.kernel.org/r/20210324081923.20379-14-noltari@gmail.com\nSigned-off-by: Linus Walleij <linus.walleij@linaro.org>\n---\n drivers/pinctrl/bcm/Kconfig           |   8 +\n drivers/pinctrl/bcm/Makefile          |   1 +\n drivers/pinctrl/bcm/pinctrl-bcm6362.c | 617 ++++++++++++++++++++++++++\n 3 files changed, 626 insertions(+)\n create mode 100644 drivers/pinctrl/bcm/pinctrl-bcm6362.c\n\n--- a/drivers/pinctrl/bcm/Kconfig\n+++ b/drivers/pinctrl/bcm/Kconfig\n@@ -52,6 +52,14 @@ config PINCTRL_BCM6358\n \thelp\n \t   Say Y here to enable the Broadcom BCM6358 GPIO driver.\n \n+config PINCTRL_BCM6362\n+\tbool \"Broadcom BCM6362 GPIO driver\"\n+\tdepends on (BMIPS_GENERIC || COMPILE_TEST)\n+\tselect PINCTRL_BCM63XX\n+\tdefault BMIPS_GENERIC\n+\thelp\n+\t   Say Y here to enable the Broadcom BCM6362 GPIO driver.\n+\n config PINCTRL_IPROC_GPIO\n \tbool \"Broadcom iProc GPIO (with PINCONF) driver\"\n \tdepends on OF_GPIO && (ARCH_BCM_IPROC || COMPILE_TEST)\n--- a/drivers/pinctrl/bcm/Makefile\n+++ b/drivers/pinctrl/bcm/Makefile\n@@ -6,6 +6,7 @@ obj-$(CONFIG_PINCTRL_BCM2835)\t\t+= pinctr\n obj-$(CONFIG_PINCTRL_BCM63XX)\t\t+= pinctrl-bcm63xx.o\n obj-$(CONFIG_PINCTRL_BCM6328)\t\t+= pinctrl-bcm6328.o\n obj-$(CONFIG_PINCTRL_BCM6358)\t\t+= pinctrl-bcm6358.o\n+obj-$(CONFIG_PINCTRL_BCM6362)\t\t+= pinctrl-bcm6362.o\n obj-$(CONFIG_PINCTRL_IPROC_GPIO)\t+= pinctrl-iproc-gpio.o\n obj-$(CONFIG_PINCTRL_CYGNUS_MUX)\t+= pinctrl-cygnus-mux.o\n obj-$(CONFIG_PINCTRL_NS)\t\t+= pinctrl-ns.o\n--- /dev/null\n+++ b/drivers/pinctrl/bcm/pinctrl-bcm6362.c\n@@ -0,0 +1,617 @@\n+// SPDX-License-Identifier: GPL-2.0+\n+/*\n+ * Driver for BCM6362 GPIO unit (pinctrl + GPIO)\n+ *\n+ * Copyright (C) 2021 Álvaro Fernández Rojas <noltari@gmail.com>\n+ * Copyright (C) 2016 Jonas Gorski <jonas.gorski@gmail.com>\n+ */\n+\n+#include <linux/bits.h>\n+#include <linux/gpio/driver.h>\n+#include <linux/kernel.h>\n+#include <linux/of.h>\n+#include <linux/pinctrl/pinmux.h>\n+#include <linux/platform_device.h>\n+#include <linux/regmap.h>\n+\n+#include \"../pinctrl-utils.h\"\n+\n+#include \"pinctrl-bcm63xx.h\"\n+\n+#define BCM6362_BANK_GPIOS\t32\n+#define BCM6362_NUM_GPIOS\t48\n+#define BCM6362_NUM_LEDS\t24\n+\n+#define BCM6362_LED_REG\t\t0x10\n+#define BCM6362_MODE_REG\t0x18\n+#define BCM6362_CTRL_REG\t0x1c\n+#define BCM6362_BASEMODE_REG\t0x38\n+#define  BASEMODE_NAND\t\tBIT(2)\n+\n+enum bcm6362_pinctrl_reg {\n+\tBCM6362_LEDCTRL,\n+\tBCM6362_MODE,\n+\tBCM6362_CTRL,\n+\tBCM6362_BASEMODE,\n+};\n+\n+struct bcm6362_pingroup {\n+\tconst char *name;\n+\tconst unsigned * const pins;\n+\tconst unsigned num_pins;\n+};\n+\n+struct bcm6362_function {\n+\tconst char *name;\n+\tconst char * const *groups;\n+\tconst unsigned num_groups;\n+\n+\tenum bcm6362_pinctrl_reg reg;\n+\tuint32_t basemode_mask;\n+};\n+\n+#define BCM6362_PIN(a, b, mask)\t\t\t\\\n+\t{\t\t\t\t\t\\\n+\t\t.number = a,\t\t\t\\\n+\t\t.name = b,\t\t\t\\\n+\t\t.drv_data = (void *)(mask),\t\\\n+\t}\n+\n+static const struct pinctrl_pin_desc bcm6362_pins[] = {\n+\tPINCTRL_PIN(0, \"gpio0\"),\n+\tPINCTRL_PIN(1, \"gpio1\"),\n+\tPINCTRL_PIN(2, \"gpio2\"),\n+\tPINCTRL_PIN(3, \"gpio3\"),\n+\tPINCTRL_PIN(4, \"gpio4\"),\n+\tPINCTRL_PIN(5, \"gpio5\"),\n+\tPINCTRL_PIN(6, \"gpio6\"),\n+\tPINCTRL_PIN(7, \"gpio7\"),\n+\tBCM6362_PIN(8, \"gpio8\", BASEMODE_NAND),\n+\tPINCTRL_PIN(9, \"gpio9\"),\n+\tPINCTRL_PIN(10, \"gpio10\"),\n+\tPINCTRL_PIN(11, \"gpio11\"),\n+\tBCM6362_PIN(12, \"gpio12\", BASEMODE_NAND),\n+\tBCM6362_PIN(13, \"gpio13\", BASEMODE_NAND),\n+\tBCM6362_PIN(14, \"gpio14\", BASEMODE_NAND),\n+\tBCM6362_PIN(15, \"gpio15\", BASEMODE_NAND),\n+\tBCM6362_PIN(16, \"gpio16\", BASEMODE_NAND),\n+\tBCM6362_PIN(17, \"gpio17\", BASEMODE_NAND),\n+\tBCM6362_PIN(18, \"gpio18\", BASEMODE_NAND),\n+\tBCM6362_PIN(19, \"gpio19\", BASEMODE_NAND),\n+\tBCM6362_PIN(20, \"gpio20\", BASEMODE_NAND),\n+\tBCM6362_PIN(21, \"gpio21\", BASEMODE_NAND),\n+\tBCM6362_PIN(22, \"gpio22\", BASEMODE_NAND),\n+\tBCM6362_PIN(23, \"gpio23\", BASEMODE_NAND),\n+\tPINCTRL_PIN(24, \"gpio24\"),\n+\tPINCTRL_PIN(25, \"gpio25\"),\n+\tPINCTRL_PIN(26, \"gpio26\"),\n+\tBCM6362_PIN(27, \"gpio27\", BASEMODE_NAND),\n+\tPINCTRL_PIN(28, \"gpio28\"),\n+\tPINCTRL_PIN(29, \"gpio29\"),\n+\tPINCTRL_PIN(30, \"gpio30\"),\n+\tPINCTRL_PIN(31, \"gpio31\"),\n+\tPINCTRL_PIN(32, \"gpio32\"),\n+\tPINCTRL_PIN(33, \"gpio33\"),\n+\tPINCTRL_PIN(34, \"gpio34\"),\n+\tPINCTRL_PIN(35, \"gpio35\"),\n+\tPINCTRL_PIN(36, \"gpio36\"),\n+\tPINCTRL_PIN(37, \"gpio37\"),\n+\tPINCTRL_PIN(38, \"gpio38\"),\n+\tPINCTRL_PIN(39, \"gpio39\"),\n+\tPINCTRL_PIN(40, \"gpio40\"),\n+\tPINCTRL_PIN(41, \"gpio41\"),\n+\tPINCTRL_PIN(42, \"gpio42\"),\n+\tPINCTRL_PIN(43, \"gpio43\"),\n+\tPINCTRL_PIN(44, \"gpio44\"),\n+\tPINCTRL_PIN(45, \"gpio45\"),\n+\tPINCTRL_PIN(46, \"gpio46\"),\n+\tPINCTRL_PIN(47, \"gpio47\"),\n+};\n+\n+static unsigned gpio0_pins[] = { 0 };\n+static unsigned gpio1_pins[] = { 1 };\n+static unsigned gpio2_pins[] = { 2 };\n+static unsigned gpio3_pins[] = { 3 };\n+static unsigned gpio4_pins[] = { 4 };\n+static unsigned gpio5_pins[] = { 5 };\n+static unsigned gpio6_pins[] = { 6 };\n+static unsigned gpio7_pins[] = { 7 };\n+static unsigned gpio8_pins[] = { 8 };\n+static unsigned gpio9_pins[] = { 9 };\n+static unsigned gpio10_pins[] = { 10 };\n+static unsigned gpio11_pins[] = { 11 };\n+static unsigned gpio12_pins[] = { 12 };\n+static unsigned gpio13_pins[] = { 13 };\n+static unsigned gpio14_pins[] = { 14 };\n+static unsigned gpio15_pins[] = { 15 };\n+static unsigned gpio16_pins[] = { 16 };\n+static unsigned gpio17_pins[] = { 17 };\n+static unsigned gpio18_pins[] = { 18 };\n+static unsigned gpio19_pins[] = { 19 };\n+static unsigned gpio20_pins[] = { 20 };\n+static unsigned gpio21_pins[] = { 21 };\n+static unsigned gpio22_pins[] = { 22 };\n+static unsigned gpio23_pins[] = { 23 };\n+static unsigned gpio24_pins[] = { 24 };\n+static unsigned gpio25_pins[] = { 25 };\n+static unsigned gpio26_pins[] = { 26 };\n+static unsigned gpio27_pins[] = { 27 };\n+static unsigned gpio28_pins[] = { 28 };\n+static unsigned gpio29_pins[] = { 29 };\n+static unsigned gpio30_pins[] = { 30 };\n+static unsigned gpio31_pins[] = { 31 };\n+static unsigned gpio32_pins[] = { 32 };\n+static unsigned gpio33_pins[] = { 33 };\n+static unsigned gpio34_pins[] = { 34 };\n+static unsigned gpio35_pins[] = { 35 };\n+static unsigned gpio36_pins[] = { 36 };\n+static unsigned gpio37_pins[] = { 37 };\n+static unsigned gpio38_pins[] = { 38 };\n+static unsigned gpio39_pins[] = { 39 };\n+static unsigned gpio40_pins[] = { 40 };\n+static unsigned gpio41_pins[] = { 41 };\n+static unsigned gpio42_pins[] = { 42 };\n+static unsigned gpio43_pins[] = { 43 };\n+static unsigned gpio44_pins[] = { 44 };\n+static unsigned gpio45_pins[] = { 45 };\n+static unsigned gpio46_pins[] = { 46 };\n+static unsigned gpio47_pins[] = { 47 };\n+\n+static unsigned nand_grp_pins[] = {\n+\t8, 12, 13, 14, 15, 16, 17,\n+\t18, 19, 20, 21, 22, 23, 27,\n+};\n+\n+#define BCM6362_GROUP(n)\t\t\t\t\\\n+\t{\t\t\t\t\t\t\\\n+\t\t.name = #n,\t\t\t\t\\\n+\t\t.pins = n##_pins,\t\t\t\\\n+\t\t.num_pins = ARRAY_SIZE(n##_pins),\t\\\n+\t}\n+\n+static struct bcm6362_pingroup bcm6362_groups[] = {\n+\tBCM6362_GROUP(gpio0),\n+\tBCM6362_GROUP(gpio1),\n+\tBCM6362_GROUP(gpio2),\n+\tBCM6362_GROUP(gpio3),\n+\tBCM6362_GROUP(gpio4),\n+\tBCM6362_GROUP(gpio5),\n+\tBCM6362_GROUP(gpio6),\n+\tBCM6362_GROUP(gpio7),\n+\tBCM6362_GROUP(gpio8),\n+\tBCM6362_GROUP(gpio9),\n+\tBCM6362_GROUP(gpio10),\n+\tBCM6362_GROUP(gpio11),\n+\tBCM6362_GROUP(gpio12),\n+\tBCM6362_GROUP(gpio13),\n+\tBCM6362_GROUP(gpio14),\n+\tBCM6362_GROUP(gpio15),\n+\tBCM6362_GROUP(gpio16),\n+\tBCM6362_GROUP(gpio17),\n+\tBCM6362_GROUP(gpio18),\n+\tBCM6362_GROUP(gpio19),\n+\tBCM6362_GROUP(gpio20),\n+\tBCM6362_GROUP(gpio21),\n+\tBCM6362_GROUP(gpio22),\n+\tBCM6362_GROUP(gpio23),\n+\tBCM6362_GROUP(gpio24),\n+\tBCM6362_GROUP(gpio25),\n+\tBCM6362_GROUP(gpio26),\n+\tBCM6362_GROUP(gpio27),\n+\tBCM6362_GROUP(gpio28),\n+\tBCM6362_GROUP(gpio29),\n+\tBCM6362_GROUP(gpio30),\n+\tBCM6362_GROUP(gpio31),\n+\tBCM6362_GROUP(gpio32),\n+\tBCM6362_GROUP(gpio33),\n+\tBCM6362_GROUP(gpio34),\n+\tBCM6362_GROUP(gpio35),\n+\tBCM6362_GROUP(gpio36),\n+\tBCM6362_GROUP(gpio37),\n+\tBCM6362_GROUP(gpio38),\n+\tBCM6362_GROUP(gpio39),\n+\tBCM6362_GROUP(gpio40),\n+\tBCM6362_GROUP(gpio41),\n+\tBCM6362_GROUP(gpio42),\n+\tBCM6362_GROUP(gpio43),\n+\tBCM6362_GROUP(gpio44),\n+\tBCM6362_GROUP(gpio45),\n+\tBCM6362_GROUP(gpio46),\n+\tBCM6362_GROUP(gpio47),\n+\tBCM6362_GROUP(nand_grp),\n+};\n+\n+static const char * const led_groups[] = {\n+\t\"gpio0\",\n+\t\"gpio1\",\n+\t\"gpio2\",\n+\t\"gpio3\",\n+\t\"gpio4\",\n+\t\"gpio5\",\n+\t\"gpio6\",\n+\t\"gpio7\",\n+\t\"gpio8\",\n+\t\"gpio9\",\n+\t\"gpio10\",\n+\t\"gpio11\",\n+\t\"gpio12\",\n+\t\"gpio13\",\n+\t\"gpio14\",\n+\t\"gpio15\",\n+\t\"gpio16\",\n+\t\"gpio17\",\n+\t\"gpio18\",\n+\t\"gpio19\",\n+\t\"gpio20\",\n+\t\"gpio21\",\n+\t\"gpio22\",\n+\t\"gpio23\",\n+};\n+\n+static const char * const usb_device_led_groups[] = {\n+\t\"gpio0\",\n+};\n+\n+static const char * const sys_irq_groups[] = {\n+\t\"gpio1\",\n+};\n+\n+static const char * const serial_led_clk_groups[] = {\n+\t\"gpio2\",\n+};\n+\n+static const char * const serial_led_data_groups[] = {\n+\t\"gpio3\",\n+};\n+\n+static const char * const robosw_led_data_groups[] = {\n+\t\"gpio4\",\n+};\n+\n+static const char * const robosw_led_clk_groups[] = {\n+\t\"gpio5\",\n+};\n+\n+static const char * const robosw_led0_groups[] = {\n+\t\"gpio6\",\n+};\n+\n+static const char * const robosw_led1_groups[] = {\n+\t\"gpio7\",\n+};\n+\n+static const char * const inet_led_groups[] = {\n+\t\"gpio8\",\n+};\n+\n+static const char * const spi_cs2_groups[] = {\n+\t\"gpio9\",\n+};\n+\n+static const char * const spi_cs3_groups[] = {\n+\t\"gpio10\",\n+};\n+\n+static const char * const ntr_pulse_groups[] = {\n+\t\"gpio11\",\n+};\n+\n+static const char * const uart1_scts_groups[] = {\n+\t\"gpio12\",\n+};\n+\n+static const char * const uart1_srts_groups[] = {\n+\t\"gpio13\",\n+};\n+\n+static const char * const uart1_sdin_groups[] = {\n+\t\"gpio14\",\n+};\n+\n+static const char * const uart1_sdout_groups[] = {\n+\t\"gpio15\",\n+};\n+\n+static const char * const adsl_spi_miso_groups[] = {\n+\t\"gpio16\",\n+};\n+\n+static const char * const adsl_spi_mosi_groups[] = {\n+\t\"gpio17\",\n+};\n+\n+static const char * const adsl_spi_clk_groups[] = {\n+\t\"gpio18\",\n+};\n+\n+static const char * const adsl_spi_cs_groups[] = {\n+\t\"gpio19\",\n+};\n+\n+static const char * const ephy0_led_groups[] = {\n+\t\"gpio20\",\n+};\n+\n+static const char * const ephy1_led_groups[] = {\n+\t\"gpio21\",\n+};\n+\n+static const char * const ephy2_led_groups[] = {\n+\t\"gpio22\",\n+};\n+\n+static const char * const ephy3_led_groups[] = {\n+\t\"gpio23\",\n+};\n+\n+static const char * const ext_irq0_groups[] = {\n+\t\"gpio24\",\n+};\n+\n+static const char * const ext_irq1_groups[] = {\n+\t\"gpio25\",\n+};\n+\n+static const char * const ext_irq2_groups[] = {\n+\t\"gpio26\",\n+};\n+\n+static const char * const ext_irq3_groups[] = {\n+\t\"gpio27\",\n+};\n+\n+static const char * const wifi_groups[] = {\n+\t\"gpio32\",\n+\t\"gpio33\",\n+\t\"gpio34\",\n+\t\"gpio35\",\n+\t\"gpio36\",\n+\t\"gpio37\",\n+\t\"gpio38\",\n+\t\"gpio39\",\n+\t\"gpio40\",\n+\t\"gpio41\",\n+\t\"gpio42\",\n+\t\"gpio43\",\n+\t\"gpio44\",\n+\t\"gpio45\",\n+\t\"gpio46\",\n+\t\"gpio47\",\n+};\n+\n+static const char * const nand_groups[] = {\n+\t\"nand_grp\",\n+};\n+\n+#define BCM6362_LED_FUN(n)\t\t\t\t\\\n+\t{\t\t\t\t\t\t\\\n+\t\t.name = #n,\t\t\t\t\\\n+\t\t.groups = n##_groups,\t\t\t\\\n+\t\t.num_groups = ARRAY_SIZE(n##_groups),\t\\\n+\t\t.reg = BCM6362_LEDCTRL,\t\t\t\\\n+\t}\n+\n+#define BCM6362_MODE_FUN(n)\t\t\t\t\\\n+\t{\t\t\t\t\t\t\\\n+\t\t.name = #n,\t\t\t\t\\\n+\t\t.groups = n##_groups,\t\t\t\\\n+\t\t.num_groups = ARRAY_SIZE(n##_groups),\t\\\n+\t\t.reg = BCM6362_MODE,\t\t\t\\\n+\t}\n+\n+#define BCM6362_CTRL_FUN(n)\t\t\t\t\\\n+\t{\t\t\t\t\t\t\\\n+\t\t.name = #n,\t\t\t\t\\\n+\t\t.groups = n##_groups,\t\t\t\\\n+\t\t.num_groups = ARRAY_SIZE(n##_groups),\t\\\n+\t\t.reg = BCM6362_CTRL,\t\t\t\\\n+\t}\n+\n+#define BCM6362_BASEMODE_FUN(n, mask)\t\t\t\\\n+\t{\t\t\t\t\t\t\\\n+\t\t.name = #n,\t\t\t\t\\\n+\t\t.groups = n##_groups,\t\t\t\\\n+\t\t.num_groups = ARRAY_SIZE(n##_groups),\t\\\n+\t\t.reg = BCM6362_BASEMODE,\t\t\\\n+\t\t.basemode_mask = (mask),\t\t\\\n+\t}\n+\n+static const struct bcm6362_function bcm6362_funcs[] = {\n+\tBCM6362_LED_FUN(led),\n+\tBCM6362_MODE_FUN(usb_device_led),\n+\tBCM6362_MODE_FUN(sys_irq),\n+\tBCM6362_MODE_FUN(serial_led_clk),\n+\tBCM6362_MODE_FUN(serial_led_data),\n+\tBCM6362_MODE_FUN(robosw_led_data),\n+\tBCM6362_MODE_FUN(robosw_led_clk),\n+\tBCM6362_MODE_FUN(robosw_led0),\n+\tBCM6362_MODE_FUN(robosw_led1),\n+\tBCM6362_MODE_FUN(inet_led),\n+\tBCM6362_MODE_FUN(spi_cs2),\n+\tBCM6362_MODE_FUN(spi_cs3),\n+\tBCM6362_MODE_FUN(ntr_pulse),\n+\tBCM6362_MODE_FUN(uart1_scts),\n+\tBCM6362_MODE_FUN(uart1_srts),\n+\tBCM6362_MODE_FUN(uart1_sdin),\n+\tBCM6362_MODE_FUN(uart1_sdout),\n+\tBCM6362_MODE_FUN(adsl_spi_miso),\n+\tBCM6362_MODE_FUN(adsl_spi_mosi),\n+\tBCM6362_MODE_FUN(adsl_spi_clk),\n+\tBCM6362_MODE_FUN(adsl_spi_cs),\n+\tBCM6362_MODE_FUN(ephy0_led),\n+\tBCM6362_MODE_FUN(ephy1_led),\n+\tBCM6362_MODE_FUN(ephy2_led),\n+\tBCM6362_MODE_FUN(ephy3_led),\n+\tBCM6362_MODE_FUN(ext_irq0),\n+\tBCM6362_MODE_FUN(ext_irq1),\n+\tBCM6362_MODE_FUN(ext_irq2),\n+\tBCM6362_MODE_FUN(ext_irq3),\n+\tBCM6362_CTRL_FUN(wifi),\n+\tBCM6362_BASEMODE_FUN(nand, BASEMODE_NAND),\n+};\n+\n+static int bcm6362_pinctrl_get_group_count(struct pinctrl_dev *pctldev)\n+{\n+\treturn ARRAY_SIZE(bcm6362_groups);\n+}\n+\n+static const char *bcm6362_pinctrl_get_group_name(struct pinctrl_dev *pctldev,\n+\t\t\t\t\t\t  unsigned group)\n+{\n+\treturn bcm6362_groups[group].name;\n+}\n+\n+static int bcm6362_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,\n+\t\t\t\t\t  unsigned group, const unsigned **pins,\n+\t\t\t\t\t  unsigned *num_pins)\n+{\n+\t*pins = bcm6362_groups[group].pins;\n+\t*num_pins = bcm6362_groups[group].num_pins;\n+\n+\treturn 0;\n+}\n+\n+static int bcm6362_pinctrl_get_func_count(struct pinctrl_dev *pctldev)\n+{\n+\treturn ARRAY_SIZE(bcm6362_funcs);\n+}\n+\n+static const char *bcm6362_pinctrl_get_func_name(struct pinctrl_dev *pctldev,\n+\t\t\t\t\t\t unsigned selector)\n+{\n+\treturn bcm6362_funcs[selector].name;\n+}\n+\n+static int bcm6362_pinctrl_get_groups(struct pinctrl_dev *pctldev,\n+\t\t\t\t      unsigned selector,\n+\t\t\t\t      const char * const **groups,\n+\t\t\t\t      unsigned * const num_groups)\n+{\n+\t*groups = bcm6362_funcs[selector].groups;\n+\t*num_groups = bcm6362_funcs[selector].num_groups;\n+\n+\treturn 0;\n+}\n+\n+static void bcm6362_set_gpio(struct bcm63xx_pinctrl *pc, unsigned pin)\n+{\n+\tconst struct pinctrl_pin_desc *desc = &bcm6362_pins[pin];\n+\tunsigned int mask = bcm63xx_bank_pin(pin);\n+\n+\tif (desc->drv_data)\n+\t\tregmap_update_bits(pc->regs, BCM6362_BASEMODE_REG,\n+\t\t\t\t   (uint32_t) desc->drv_data, 0);\n+\n+\tif (pin < BCM63XX_BANK_GPIOS) {\n+\t\t/* base mode 0 => gpio 1 => mux function */\n+\t\tregmap_update_bits(pc->regs, BCM6362_MODE_REG, mask, 0);\n+\n+\t\t/* pins 0-23 might be muxed to led */\n+\t\tif (pin < BCM6362_NUM_LEDS)\n+\t\t\tregmap_update_bits(pc->regs, BCM6362_LED_REG, mask, 0);\n+\t} else {\n+\t\t/* ctrl reg 0 => wifi function 1 => gpio */\n+\t\tregmap_update_bits(pc->regs, BCM6362_CTRL_REG, mask, mask);\n+\t}\n+}\n+\n+static int bcm6362_pinctrl_set_mux(struct pinctrl_dev *pctldev,\n+\t\t\t\t   unsigned selector, unsigned group)\n+{\n+\tstruct bcm63xx_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);\n+\tconst struct bcm6362_pingroup *pg = &bcm6362_groups[group];\n+\tconst struct bcm6362_function *f = &bcm6362_funcs[selector];\n+\tunsigned i;\n+\tunsigned int reg;\n+\tunsigned int val, mask;\n+\n+\tfor (i = 0; i < pg->num_pins; i++)\n+\t\tbcm6362_set_gpio(pc, pg->pins[i]);\n+\n+\tswitch (f->reg) {\n+\tcase BCM6362_LEDCTRL:\n+\t\treg = BCM6362_LED_REG;\n+\t\tmask = BIT(pg->pins[0]);\n+\t\tval = BIT(pg->pins[0]);\n+\t\tbreak;\n+\tcase BCM6362_MODE:\n+\t\treg = BCM6362_MODE_REG;\n+\t\tmask = BIT(pg->pins[0]);\n+\t\tval = BIT(pg->pins[0]);\n+\t\tbreak;\n+\tcase BCM6362_CTRL:\n+\t\treg = BCM6362_CTRL_REG;\n+\t\tmask = BIT(pg->pins[0]);\n+\t\tval = 0;\n+\t\tbreak;\n+\tcase BCM6362_BASEMODE:\n+\t\treg = BCM6362_BASEMODE_REG;\n+\t\tmask = f->basemode_mask;\n+\t\tval = f->basemode_mask;\n+\t\tbreak;\n+\tdefault:\n+\t\tWARN_ON(1);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tregmap_update_bits(pc->regs, reg, mask, val);\n+\n+\treturn 0;\n+}\n+\n+static int bcm6362_gpio_request_enable(struct pinctrl_dev *pctldev,\n+\t\t\t\t       struct pinctrl_gpio_range *range,\n+\t\t\t\t       unsigned offset)\n+{\n+\tstruct bcm63xx_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);\n+\n+\t/* disable all functions using this pin */\n+\tbcm6362_set_gpio(pc, offset);\n+\n+\treturn 0;\n+}\n+\n+static struct pinctrl_ops bcm6362_pctl_ops = {\n+\t.dt_free_map = pinctrl_utils_free_map,\n+\t.dt_node_to_map = pinconf_generic_dt_node_to_map_pin,\n+\t.get_group_name = bcm6362_pinctrl_get_group_name,\n+\t.get_group_pins = bcm6362_pinctrl_get_group_pins,\n+\t.get_groups_count = bcm6362_pinctrl_get_group_count,\n+};\n+\n+static struct pinmux_ops bcm6362_pmx_ops = {\n+\t.get_function_groups = bcm6362_pinctrl_get_groups,\n+\t.get_function_name = bcm6362_pinctrl_get_func_name,\n+\t.get_functions_count = bcm6362_pinctrl_get_func_count,\n+\t.gpio_request_enable = bcm6362_gpio_request_enable,\n+\t.set_mux = bcm6362_pinctrl_set_mux,\n+\t.strict = true,\n+};\n+\n+static const struct bcm63xx_pinctrl_soc bcm6362_soc = {\n+\t.ngpios = BCM6362_NUM_GPIOS,\n+\t.npins = ARRAY_SIZE(bcm6362_pins),\n+\t.pctl_ops = &bcm6362_pctl_ops,\n+\t.pins = bcm6362_pins,\n+\t.pmx_ops = &bcm6362_pmx_ops,\n+};\n+\n+static int bcm6362_pinctrl_probe(struct platform_device *pdev)\n+{\n+\treturn bcm63xx_pinctrl_probe(pdev, &bcm6362_soc, NULL);\n+}\n+\n+static const struct of_device_id bcm6362_pinctrl_match[] = {\n+\t{ .compatible = \"brcm,bcm6362-pinctrl\", },\n+\t{ /* sentinel */ }\n+};\n+\n+static struct platform_driver bcm6362_pinctrl_driver = {\n+\t.probe = bcm6362_pinctrl_probe,\n+\t.driver = {\n+\t\t.name = \"bcm6362-pinctrl\",\n+\t\t.of_match_table = bcm6362_pinctrl_match,\n+\t},\n+};\n+\n+builtin_platform_driver(bcm6362_pinctrl_driver);\n"
  },
  {
    "path": "target/linux/bmips/patches-5.10/065-v5.13-dt-bindings-add-BCM6368-pincontroller-binding-docume.patch",
    "content": "From 9fbf8303796c89ecab026eb3dbadae7f98c49922 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com>\nDate: Wed, 24 Mar 2021 09:19:15 +0100\nSubject: [PATCH 14/22] dt-bindings: add BCM6368 pincontroller binding\n documentation\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nAdd binding documentation for the pincontrol core found in BCM6368 SoCs.\n\nCo-developed-by: Jonas Gorski <jonas.gorski@gmail.com>\nSigned-off-by: Jonas Gorski <jonas.gorski@gmail.com>\nSigned-off-by: Álvaro Fernández Rojas <noltari@gmail.com>\nReviewed-by: Rob Herring <robh@kernel.org>\nLink: https://lore.kernel.org/r/20210324081923.20379-15-noltari@gmail.com\nSigned-off-by: Linus Walleij <linus.walleij@linaro.org>\n---\n .../pinctrl/brcm,bcm6368-pinctrl.yaml         | 217 ++++++++++++++++++\n 1 file changed, 217 insertions(+)\n create mode 100644 Documentation/devicetree/bindings/pinctrl/brcm,bcm6368-pinctrl.yaml\n\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/pinctrl/brcm,bcm6368-pinctrl.yaml\n@@ -0,0 +1,217 @@\n+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause\n+%YAML 1.2\n+---\n+$id: http://devicetree.org/schemas/pinctrl/brcm,bcm6368-pinctrl.yaml#\n+$schema: http://devicetree.org/meta-schemas/core.yaml#\n+\n+title: Broadcom BCM6368 pin controller\n+\n+maintainers:\n+  - Álvaro Fernández Rojas <noltari@gmail.com>\n+  - Jonas Gorski <jonas.gorski@gmail.com>\n+\n+description:\n+  Bindings for Broadcom's BCM6368 memory-mapped pin controller.\n+\n+properties:\n+  compatible:\n+    const: brcm,bcm6368-pinctrl\n+\n+  reg:\n+    maxItems: 2\n+\n+patternProperties:\n+  '-pins$':\n+    type: object\n+    $ref: pinmux-node.yaml#\n+\n+    properties:\n+      function:\n+        enum: [ analog_afe_0, analog_afe_1, sys_irq, serial_led_data,\n+                serial_led_clk, inet_led, ephy0_led, ephy1_led, ephy2_led,\n+                ephy3_led, robosw_led_data, robosw_led_clk, robosw_led0,\n+                robosw_led1, usb_device_led, pci_req1, pci_gnt1, pci_intb,\n+                pci_req0, pci_gnt0, pcmcia_cd1, pcmcia_cd2, pcmcia_vs1,\n+                pcmcia_vs2, ebi_cs2, ebi_cs3, spi_cs2, spi_cs3, spi_cs4,\n+                spi_cs5, uart1 ]\n+\n+      pins:\n+        enum: [ gpio0, gpio1, gpio2, gpio3, gpio4, gpio5, gpio6, gpio7,\n+                gpio8, gpio9, gpio10, gpio11, gpio12, gpio13, gpio14,\n+                gpio16, gpio17, gpio18, gpio19, gpio20, gpio22, gpio23,\n+                gpio24, gpio25, gpio26, gpio27, gpio28, gpio29, gpio30,\n+                gpio31, uart1_grp ]\n+\n+required:\n+  - compatible\n+  - reg\n+\n+additionalProperties: false\n+\n+examples:\n+  - |\n+    pinctrl@18 {\n+      compatible = \"brcm,bcm6368-pinctrl\";\n+      reg = <0x18 0x4>, <0x38 0x4>;\n+\n+      pinctrl_analog_afe_0: analog_afe_0-pins {\n+        function = \"analog_afe_0\";\n+        pins = \"gpio0\";\n+      };\n+\n+      pinctrl_analog_afe_1: analog_afe_1-pins {\n+        function = \"analog_afe_1\";\n+        pins = \"gpio1\";\n+      };\n+\n+      pinctrl_sys_irq: sys_irq-pins {\n+        function = \"sys_irq\";\n+        pins = \"gpio2\";\n+      };\n+\n+      pinctrl_serial_led: serial_led-pins {\n+        pinctrl_serial_led_data: serial_led_data-pins {\n+          function = \"serial_led_data\";\n+          pins = \"gpio3\";\n+        };\n+\n+        pinctrl_serial_led_clk: serial_led_clk-pins {\n+          function = \"serial_led_clk\";\n+          pins = \"gpio4\";\n+        };\n+      };\n+\n+      pinctrl_inet_led: inet_led-pins {\n+        function = \"inet_led\";\n+        pins = \"gpio5\";\n+      };\n+\n+      pinctrl_ephy0_led: ephy0_led-pins {\n+        function = \"ephy0_led\";\n+        pins = \"gpio6\";\n+      };\n+\n+      pinctrl_ephy1_led: ephy1_led-pins {\n+        function = \"ephy1_led\";\n+        pins = \"gpio7\";\n+      };\n+\n+      pinctrl_ephy2_led: ephy2_led-pins {\n+        function = \"ephy2_led\";\n+        pins = \"gpio8\";\n+      };\n+\n+      pinctrl_ephy3_led: ephy3_led-pins {\n+        function = \"ephy3_led\";\n+        pins = \"gpio9\";\n+      };\n+\n+      pinctrl_robosw_led_data: robosw_led_data-pins {\n+        function = \"robosw_led_data\";\n+        pins = \"gpio10\";\n+      };\n+\n+      pinctrl_robosw_led_clk: robosw_led_clk-pins {\n+        function = \"robosw_led_clk\";\n+        pins = \"gpio11\";\n+      };\n+\n+      pinctrl_robosw_led0: robosw_led0-pins {\n+        function = \"robosw_led0\";\n+        pins = \"gpio12\";\n+      };\n+\n+      pinctrl_robosw_led1: robosw_led1-pins {\n+        function = \"robosw_led1\";\n+        pins = \"gpio13\";\n+      };\n+\n+      pinctrl_usb_device_led: usb_device_led-pins {\n+        function = \"usb_device_led\";\n+        pins = \"gpio14\";\n+      };\n+\n+      pinctrl_pci: pci-pins {\n+        pinctrl_pci_req1: pci_req1-pins {\n+          function = \"pci_req1\";\n+          pins = \"gpio16\";\n+        };\n+\n+        pinctrl_pci_gnt1: pci_gnt1-pins {\n+          function = \"pci_gnt1\";\n+          pins = \"gpio17\";\n+        };\n+\n+        pinctrl_pci_intb: pci_intb-pins {\n+          function = \"pci_intb\";\n+          pins = \"gpio18\";\n+        };\n+\n+        pinctrl_pci_req0: pci_req0-pins {\n+          function = \"pci_req0\";\n+          pins = \"gpio19\";\n+        };\n+\n+        pinctrl_pci_gnt0: pci_gnt0-pins {\n+          function = \"pci_gnt0\";\n+          pins = \"gpio20\";\n+        };\n+      };\n+\n+      pinctrl_pcmcia: pcmcia-pins {\n+        pinctrl_pcmcia_cd1: pcmcia_cd1-pins {\n+          function = \"pcmcia_cd1\";\n+          pins = \"gpio22\";\n+        };\n+\n+        pinctrl_pcmcia_cd2: pcmcia_cd2-pins {\n+          function = \"pcmcia_cd2\";\n+          pins = \"gpio23\";\n+        };\n+\n+        pinctrl_pcmcia_vs1: pcmcia_vs1-pins {\n+          function = \"pcmcia_vs1\";\n+          pins = \"gpio24\";\n+        };\n+\n+        pinctrl_pcmcia_vs2: pcmcia_vs2-pins {\n+          function = \"pcmcia_vs2\";\n+          pins = \"gpio25\";\n+        };\n+      };\n+\n+      pinctrl_ebi_cs2: ebi_cs2-pins {\n+        function = \"ebi_cs2\";\n+        pins = \"gpio26\";\n+      };\n+\n+      pinctrl_ebi_cs3: ebi_cs3-pins {\n+        function = \"ebi_cs3\";\n+        pins = \"gpio27\";\n+      };\n+\n+      pinctrl_spi_cs2: spi_cs2-pins {\n+        function = \"spi_cs2\";\n+        pins = \"gpio28\";\n+      };\n+\n+      pinctrl_spi_cs3: spi_cs3-pins {\n+        function = \"spi_cs3\";\n+        pins = \"gpio29\";\n+      };\n+\n+      pinctrl_spi_cs4: spi_cs4-pins {\n+        function = \"spi_cs4\";\n+        pins = \"gpio30\";\n+      };\n+\n+      pinctrl_spi_cs5: spi_cs5-pins {\n+        function = \"spi_cs5\";\n+        pins = \"gpio31\";\n+      };\n+\n+      pinctrl_uart1: uart1-pins {\n+        function = \"uart1\";\n+        group = \"uart1_grp\";\n+      };\n+    };\n"
  },
  {
    "path": "target/linux/bmips/patches-5.10/066-v5.13-dt-bindings-add-BCM6368-GPIO-sysctl-binding-document.patch",
    "content": "From fd22635f222f44dcb4dd6382d97de13144edad2b Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com>\nDate: Wed, 24 Mar 2021 09:19:16 +0100\nSubject: [PATCH 15/22] dt-bindings: add BCM6368 GPIO sysctl binding\n documentation\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nAdd binding documentation for the GPIO sysctl found in BCM6368 SoCs.\n\nSigned-off-by: Álvaro Fernández Rojas <noltari@gmail.com>\nReviewed-by: Rob Herring <robh@kernel.org>\nLink: https://lore.kernel.org/r/20210324081923.20379-16-noltari@gmail.com\nSigned-off-by: Linus Walleij <linus.walleij@linaro.org>\n---\n .../mfd/brcm,bcm6368-gpio-sysctl.yaml         | 246 ++++++++++++++++++\n 1 file changed, 246 insertions(+)\n create mode 100644 Documentation/devicetree/bindings/mfd/brcm,bcm6368-gpio-sysctl.yaml\n\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/mfd/brcm,bcm6368-gpio-sysctl.yaml\n@@ -0,0 +1,246 @@\n+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)\n+%YAML 1.2\n+---\n+$id: http://devicetree.org/schemas/mfd/brcm,bcm6368-gpio-sysctl.yaml#\n+$schema: http://devicetree.org/meta-schemas/core.yaml#\n+\n+title: Broadcom BCM6368 GPIO System Controller Device Tree Bindings\n+\n+maintainers:\n+  - Álvaro Fernández Rojas <noltari@gmail.com>\n+  - Jonas Gorski <jonas.gorski@gmail.com>\n+\n+description:\n+  Broadcom BCM6368 SoC GPIO system controller which provides a register map\n+  for controlling the GPIO and pins of the SoC.\n+\n+properties:\n+  \"#address-cells\": true\n+\n+  \"#size-cells\": true\n+\n+  compatible:\n+    items:\n+      - const: brcm,bcm6368-gpio-sysctl\n+      - const: syscon\n+      - const: simple-mfd\n+\n+  ranges:\n+    maxItems: 1\n+\n+  reg:\n+    maxItems: 1\n+\n+patternProperties:\n+  \"^gpio@[0-9a-f]+$\":\n+    # Child node\n+    type: object\n+    $ref: \"../gpio/brcm,bcm6345-gpio.yaml\"\n+    description:\n+      GPIO controller for the SoC GPIOs. This child node definition\n+      should follow the bindings specified in\n+      Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.yaml.\n+\n+  \"^pinctrl@[0-9a-f]+$\":\n+    # Child node\n+    type: object\n+    $ref: \"../pinctrl/brcm,bcm6368-pinctrl.yaml\"\n+    description:\n+      Pin controller for the SoC pins. This child node definition\n+      should follow the bindings specified in\n+      Documentation/devicetree/bindings/pinctrl/brcm,bcm6368-pinctrl.yaml.\n+\n+required:\n+  - \"#address-cells\"\n+  - compatible\n+  - ranges\n+  - reg\n+  - \"#size-cells\"\n+\n+additionalProperties: false\n+\n+examples:\n+  - |\n+    syscon@10000080 {\n+      #address-cells = <1>;\n+      #size-cells = <1>;\n+      compatible = \"brcm,bcm6368-gpio-sysctl\", \"syscon\", \"simple-mfd\";\n+      reg = <0x10000080 0x80>;\n+      ranges = <0 0x10000080 0x80>;\n+\n+      gpio@0 {\n+        compatible = \"brcm,bcm6368-gpio\";\n+        reg-names = \"dirout\", \"dat\";\n+        reg = <0x0 0x8>, <0x8 0x8>;\n+\n+        gpio-controller;\n+        gpio-ranges = <&pinctrl 0 0 38>;\n+        #gpio-cells = <2>;\n+      };\n+\n+      pinctrl: pinctrl@18 {\n+        compatible = \"brcm,bcm6368-pinctrl\";\n+        reg = <0x18 0x4>, <0x38 0x4>;\n+\n+        pinctrl_analog_afe_0: analog_afe_0-pins {\n+          function = \"analog_afe_0\";\n+          pins = \"gpio0\";\n+        };\n+\n+        pinctrl_analog_afe_1: analog_afe_1-pins {\n+          function = \"analog_afe_1\";\n+          pins = \"gpio1\";\n+        };\n+\n+        pinctrl_sys_irq: sys_irq-pins {\n+          function = \"sys_irq\";\n+          pins = \"gpio2\";\n+        };\n+\n+        pinctrl_serial_led: serial_led-pins {\n+          pinctrl_serial_led_data: serial_led_data-pins {\n+            function = \"serial_led_data\";\n+            pins = \"gpio3\";\n+          };\n+\n+          pinctrl_serial_led_clk: serial_led_clk-pins {\n+            function = \"serial_led_clk\";\n+            pins = \"gpio4\";\n+          };\n+        };\n+\n+        pinctrl_inet_led: inet_led-pins {\n+          function = \"inet_led\";\n+          pins = \"gpio5\";\n+        };\n+\n+        pinctrl_ephy0_led: ephy0_led-pins {\n+          function = \"ephy0_led\";\n+          pins = \"gpio6\";\n+        };\n+\n+        pinctrl_ephy1_led: ephy1_led-pins {\n+          function = \"ephy1_led\";\n+          pins = \"gpio7\";\n+        };\n+\n+        pinctrl_ephy2_led: ephy2_led-pins {\n+          function = \"ephy2_led\";\n+          pins = \"gpio8\";\n+        };\n+\n+        pinctrl_ephy3_led: ephy3_led-pins {\n+          function = \"ephy3_led\";\n+          pins = \"gpio9\";\n+        };\n+\n+        pinctrl_robosw_led_data: robosw_led_data-pins {\n+          function = \"robosw_led_data\";\n+          pins = \"gpio10\";\n+        };\n+\n+        pinctrl_robosw_led_clk: robosw_led_clk-pins {\n+          function = \"robosw_led_clk\";\n+          pins = \"gpio11\";\n+        };\n+\n+        pinctrl_robosw_led0: robosw_led0-pins {\n+          function = \"robosw_led0\";\n+          pins = \"gpio12\";\n+        };\n+\n+        pinctrl_robosw_led1: robosw_led1-pins {\n+          function = \"robosw_led1\";\n+          pins = \"gpio13\";\n+        };\n+\n+        pinctrl_usb_device_led: usb_device_led-pins {\n+          function = \"usb_device_led\";\n+          pins = \"gpio14\";\n+        };\n+\n+        pinctrl_pci: pci-pins {\n+          pinctrl_pci_req1: pci_req1-pins {\n+            function = \"pci_req1\";\n+            pins = \"gpio16\";\n+          };\n+\n+          pinctrl_pci_gnt1: pci_gnt1-pins {\n+            function = \"pci_gnt1\";\n+            pins = \"gpio17\";\n+          };\n+\n+          pinctrl_pci_intb: pci_intb-pins {\n+            function = \"pci_intb\";\n+            pins = \"gpio18\";\n+          };\n+\n+          pinctrl_pci_req0: pci_req0-pins {\n+            function = \"pci_req0\";\n+            pins = \"gpio19\";\n+          };\n+\n+          pinctrl_pci_gnt0: pci_gnt0-pins {\n+            function = \"pci_gnt0\";\n+            pins = \"gpio20\";\n+          };\n+        };\n+\n+        pinctrl_pcmcia: pcmcia-pins {\n+          pinctrl_pcmcia_cd1: pcmcia_cd1-pins {\n+            function = \"pcmcia_cd1\";\n+            pins = \"gpio22\";\n+          };\n+\n+          pinctrl_pcmcia_cd2: pcmcia_cd2-pins {\n+            function = \"pcmcia_cd2\";\n+            pins = \"gpio23\";\n+          };\n+\n+          pinctrl_pcmcia_vs1: pcmcia_vs1-pins {\n+            function = \"pcmcia_vs1\";\n+            pins = \"gpio24\";\n+          };\n+\n+          pinctrl_pcmcia_vs2: pcmcia_vs2-pins {\n+            function = \"pcmcia_vs2\";\n+            pins = \"gpio25\";\n+          };\n+        };\n+\n+        pinctrl_ebi_cs2: ebi_cs2-pins {\n+          function = \"ebi_cs2\";\n+          pins = \"gpio26\";\n+        };\n+\n+        pinctrl_ebi_cs3: ebi_cs3-pins {\n+          function = \"ebi_cs3\";\n+          pins = \"gpio27\";\n+        };\n+\n+        pinctrl_spi_cs2: spi_cs2-pins {\n+          function = \"spi_cs2\";\n+          pins = \"gpio28\";\n+        };\n+\n+        pinctrl_spi_cs3: spi_cs3-pins {\n+          function = \"spi_cs3\";\n+          pins = \"gpio29\";\n+        };\n+\n+        pinctrl_spi_cs4: spi_cs4-pins {\n+          function = \"spi_cs4\";\n+          pins = \"gpio30\";\n+        };\n+\n+        pinctrl_spi_cs5: spi_cs5-pins {\n+          function = \"spi_cs5\";\n+          pins = \"gpio31\";\n+        };\n+\n+        pinctrl_uart1: uart1-pins {\n+          function = \"uart1\";\n+          group = \"uart1_grp\";\n+        };\n+      };\n+    };\n"
  },
  {
    "path": "target/linux/bmips/patches-5.10/067-v5.13-pinctrl-add-a-pincontrol-driver-for-BCM6368.patch",
    "content": "From 50554accf7a79980cd04481e8903073bdb706daf Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com>\nDate: Wed, 24 Mar 2021 09:19:17 +0100\nSubject: [PATCH 16/22] pinctrl: add a pincontrol driver for BCM6368\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nAdd a pincontrol driver for BCM6368. BCM6368 allows muxing the first 32\nGPIOs onto alternative functions. Not all are documented.\n\nCo-developed-by: Jonas Gorski <jonas.gorski@gmail.com>\nSigned-off-by: Jonas Gorski <jonas.gorski@gmail.com>\nSigned-off-by: Álvaro Fernández Rojas <noltari@gmail.com>\nLink: https://lore.kernel.org/r/20210324081923.20379-17-noltari@gmail.com\nSigned-off-by: Linus Walleij <linus.walleij@linaro.org>\n---\n drivers/pinctrl/bcm/Kconfig           |   8 +\n drivers/pinctrl/bcm/Makefile          |   1 +\n drivers/pinctrl/bcm/pinctrl-bcm6368.c | 523 ++++++++++++++++++++++++++\n 3 files changed, 532 insertions(+)\n create mode 100644 drivers/pinctrl/bcm/pinctrl-bcm6368.c\n\n--- a/drivers/pinctrl/bcm/Kconfig\n+++ b/drivers/pinctrl/bcm/Kconfig\n@@ -60,6 +60,14 @@ config PINCTRL_BCM6362\n \thelp\n \t   Say Y here to enable the Broadcom BCM6362 GPIO driver.\n \n+config PINCTRL_BCM6368\n+\tbool \"Broadcom BCM6368 GPIO driver\"\n+\tdepends on (BMIPS_GENERIC || COMPILE_TEST)\n+\tselect PINCTRL_BCM63XX\n+\tdefault BMIPS_GENERIC\n+\thelp\n+\t   Say Y here to enable the Broadcom BCM6368 GPIO driver.\n+\n config PINCTRL_IPROC_GPIO\n \tbool \"Broadcom iProc GPIO (with PINCONF) driver\"\n \tdepends on OF_GPIO && (ARCH_BCM_IPROC || COMPILE_TEST)\n--- a/drivers/pinctrl/bcm/Makefile\n+++ b/drivers/pinctrl/bcm/Makefile\n@@ -7,6 +7,7 @@ obj-$(CONFIG_PINCTRL_BCM63XX)\t\t+= pinctr\n obj-$(CONFIG_PINCTRL_BCM6328)\t\t+= pinctrl-bcm6328.o\n obj-$(CONFIG_PINCTRL_BCM6358)\t\t+= pinctrl-bcm6358.o\n obj-$(CONFIG_PINCTRL_BCM6362)\t\t+= pinctrl-bcm6362.o\n+obj-$(CONFIG_PINCTRL_BCM6368)\t\t+= pinctrl-bcm6368.o\n obj-$(CONFIG_PINCTRL_IPROC_GPIO)\t+= pinctrl-iproc-gpio.o\n obj-$(CONFIG_PINCTRL_CYGNUS_MUX)\t+= pinctrl-cygnus-mux.o\n obj-$(CONFIG_PINCTRL_NS)\t\t+= pinctrl-ns.o\n--- /dev/null\n+++ b/drivers/pinctrl/bcm/pinctrl-bcm6368.c\n@@ -0,0 +1,523 @@\n+// SPDX-License-Identifier: GPL-2.0+\n+/*\n+ * Driver for BCM6368 GPIO unit (pinctrl + GPIO)\n+ *\n+ * Copyright (C) 2021 Álvaro Fernández Rojas <noltari@gmail.com>\n+ * Copyright (C) 2016 Jonas Gorski <jonas.gorski@gmail.com>\n+ */\n+\n+#include <linux/bits.h>\n+#include <linux/gpio/driver.h>\n+#include <linux/kernel.h>\n+#include <linux/of.h>\n+#include <linux/pinctrl/pinmux.h>\n+#include <linux/platform_device.h>\n+#include <linux/regmap.h>\n+\n+#include \"../pinctrl-utils.h\"\n+\n+#include \"pinctrl-bcm63xx.h\"\n+\n+#define BCM6368_NUM_GPIOS\t38\n+\n+#define BCM6368_MODE_REG\t0x18\n+#define BCM6368_BASEMODE_REG\t0x38\n+#define  BCM6368_BASEMODE_MASK\t0x7\n+#define  BCM6368_BASEMODE_GPIO\t0x0\n+#define  BCM6368_BASEMODE_UART1\t0x1\n+\n+struct bcm6368_pingroup {\n+\tconst char *name;\n+\tconst unsigned * const pins;\n+\tconst unsigned num_pins;\n+};\n+\n+struct bcm6368_function {\n+\tconst char *name;\n+\tconst char * const *groups;\n+\tconst unsigned num_groups;\n+\n+\tunsigned dir_out:16;\n+\tunsigned basemode:3;\n+};\n+\n+struct bcm6368_priv {\n+\tstruct regmap_field *overlays;\n+};\n+\n+#define BCM6368_BASEMODE_PIN(a, b)\t\t\\\n+\t{\t\t\t\t\t\\\n+\t\t.number = a,\t\t\t\\\n+\t\t.name = b,\t\t\t\\\n+\t\t.drv_data = (void *)true\t\\\n+\t}\n+\n+static const struct pinctrl_pin_desc bcm6368_pins[] = {\n+\tPINCTRL_PIN(0, \"gpio0\"),\n+\tPINCTRL_PIN(1, \"gpio1\"),\n+\tPINCTRL_PIN(2, \"gpio2\"),\n+\tPINCTRL_PIN(3, \"gpio3\"),\n+\tPINCTRL_PIN(4, \"gpio4\"),\n+\tPINCTRL_PIN(5, \"gpio5\"),\n+\tPINCTRL_PIN(6, \"gpio6\"),\n+\tPINCTRL_PIN(7, \"gpio7\"),\n+\tPINCTRL_PIN(8, \"gpio8\"),\n+\tPINCTRL_PIN(9, \"gpio9\"),\n+\tPINCTRL_PIN(10, \"gpio10\"),\n+\tPINCTRL_PIN(11, \"gpio11\"),\n+\tPINCTRL_PIN(12, \"gpio12\"),\n+\tPINCTRL_PIN(13, \"gpio13\"),\n+\tPINCTRL_PIN(14, \"gpio14\"),\n+\tPINCTRL_PIN(15, \"gpio15\"),\n+\tPINCTRL_PIN(16, \"gpio16\"),\n+\tPINCTRL_PIN(17, \"gpio17\"),\n+\tPINCTRL_PIN(18, \"gpio18\"),\n+\tPINCTRL_PIN(19, \"gpio19\"),\n+\tPINCTRL_PIN(20, \"gpio20\"),\n+\tPINCTRL_PIN(21, \"gpio21\"),\n+\tPINCTRL_PIN(22, \"gpio22\"),\n+\tPINCTRL_PIN(23, \"gpio23\"),\n+\tPINCTRL_PIN(24, \"gpio24\"),\n+\tPINCTRL_PIN(25, \"gpio25\"),\n+\tPINCTRL_PIN(26, \"gpio26\"),\n+\tPINCTRL_PIN(27, \"gpio27\"),\n+\tPINCTRL_PIN(28, \"gpio28\"),\n+\tPINCTRL_PIN(29, \"gpio29\"),\n+\tBCM6368_BASEMODE_PIN(30, \"gpio30\"),\n+\tBCM6368_BASEMODE_PIN(31, \"gpio31\"),\n+\tBCM6368_BASEMODE_PIN(32, \"gpio32\"),\n+\tBCM6368_BASEMODE_PIN(33, \"gpio33\"),\n+\tPINCTRL_PIN(34, \"gpio34\"),\n+\tPINCTRL_PIN(35, \"gpio35\"),\n+\tPINCTRL_PIN(36, \"gpio36\"),\n+\tPINCTRL_PIN(37, \"gpio37\"),\n+};\n+\n+static unsigned gpio0_pins[] = { 0 };\n+static unsigned gpio1_pins[] = { 1 };\n+static unsigned gpio2_pins[] = { 2 };\n+static unsigned gpio3_pins[] = { 3 };\n+static unsigned gpio4_pins[] = { 4 };\n+static unsigned gpio5_pins[] = { 5 };\n+static unsigned gpio6_pins[] = { 6 };\n+static unsigned gpio7_pins[] = { 7 };\n+static unsigned gpio8_pins[] = { 8 };\n+static unsigned gpio9_pins[] = { 9 };\n+static unsigned gpio10_pins[] = { 10 };\n+static unsigned gpio11_pins[] = { 11 };\n+static unsigned gpio12_pins[] = { 12 };\n+static unsigned gpio13_pins[] = { 13 };\n+static unsigned gpio14_pins[] = { 14 };\n+static unsigned gpio15_pins[] = { 15 };\n+static unsigned gpio16_pins[] = { 16 };\n+static unsigned gpio17_pins[] = { 17 };\n+static unsigned gpio18_pins[] = { 18 };\n+static unsigned gpio19_pins[] = { 19 };\n+static unsigned gpio20_pins[] = { 20 };\n+static unsigned gpio21_pins[] = { 21 };\n+static unsigned gpio22_pins[] = { 22 };\n+static unsigned gpio23_pins[] = { 23 };\n+static unsigned gpio24_pins[] = { 24 };\n+static unsigned gpio25_pins[] = { 25 };\n+static unsigned gpio26_pins[] = { 26 };\n+static unsigned gpio27_pins[] = { 27 };\n+static unsigned gpio28_pins[] = { 28 };\n+static unsigned gpio29_pins[] = { 29 };\n+static unsigned gpio30_pins[] = { 30 };\n+static unsigned gpio31_pins[] = { 31 };\n+static unsigned uart1_grp_pins[] = { 30, 31, 32, 33 };\n+\n+#define BCM6368_GROUP(n)\t\t\t\t\\\n+\t{\t\t\t\t\t\t\\\n+\t\t.name = #n,\t\t\t\t\\\n+\t\t.pins = n##_pins,\t\t\t\\\n+\t\t.num_pins = ARRAY_SIZE(n##_pins),\t\\\n+\t}\n+\n+static struct bcm6368_pingroup bcm6368_groups[] = {\n+\tBCM6368_GROUP(gpio0),\n+\tBCM6368_GROUP(gpio1),\n+\tBCM6368_GROUP(gpio2),\n+\tBCM6368_GROUP(gpio3),\n+\tBCM6368_GROUP(gpio4),\n+\tBCM6368_GROUP(gpio5),\n+\tBCM6368_GROUP(gpio6),\n+\tBCM6368_GROUP(gpio7),\n+\tBCM6368_GROUP(gpio8),\n+\tBCM6368_GROUP(gpio9),\n+\tBCM6368_GROUP(gpio10),\n+\tBCM6368_GROUP(gpio11),\n+\tBCM6368_GROUP(gpio12),\n+\tBCM6368_GROUP(gpio13),\n+\tBCM6368_GROUP(gpio14),\n+\tBCM6368_GROUP(gpio15),\n+\tBCM6368_GROUP(gpio16),\n+\tBCM6368_GROUP(gpio17),\n+\tBCM6368_GROUP(gpio18),\n+\tBCM6368_GROUP(gpio19),\n+\tBCM6368_GROUP(gpio20),\n+\tBCM6368_GROUP(gpio21),\n+\tBCM6368_GROUP(gpio22),\n+\tBCM6368_GROUP(gpio23),\n+\tBCM6368_GROUP(gpio24),\n+\tBCM6368_GROUP(gpio25),\n+\tBCM6368_GROUP(gpio26),\n+\tBCM6368_GROUP(gpio27),\n+\tBCM6368_GROUP(gpio28),\n+\tBCM6368_GROUP(gpio29),\n+\tBCM6368_GROUP(gpio30),\n+\tBCM6368_GROUP(gpio31),\n+\tBCM6368_GROUP(uart1_grp),\n+};\n+\n+static const char * const analog_afe_0_groups[] = {\n+\t\"gpio0\",\n+};\n+\n+static const char * const analog_afe_1_groups[] = {\n+\t\"gpio1\",\n+};\n+\n+static const char * const sys_irq_groups[] = {\n+\t\"gpio2\",\n+};\n+\n+static const char * const serial_led_data_groups[] = {\n+\t\"gpio3\",\n+};\n+\n+static const char * const serial_led_clk_groups[] = {\n+\t\"gpio4\",\n+};\n+\n+static const char * const inet_led_groups[] = {\n+\t\"gpio5\",\n+};\n+\n+static const char * const ephy0_led_groups[] = {\n+\t\"gpio6\",\n+};\n+\n+static const char * const ephy1_led_groups[] = {\n+\t\"gpio7\",\n+};\n+\n+static const char * const ephy2_led_groups[] = {\n+\t\"gpio8\",\n+};\n+\n+static const char * const ephy3_led_groups[] = {\n+\t\"gpio9\",\n+};\n+\n+static const char * const robosw_led_data_groups[] = {\n+\t\"gpio10\",\n+};\n+\n+static const char * const robosw_led_clk_groups[] = {\n+\t\"gpio11\",\n+};\n+\n+static const char * const robosw_led0_groups[] = {\n+\t\"gpio12\",\n+};\n+\n+static const char * const robosw_led1_groups[] = {\n+\t\"gpio13\",\n+};\n+\n+static const char * const usb_device_led_groups[] = {\n+\t\"gpio14\",\n+};\n+\n+static const char * const pci_req1_groups[] = {\n+\t\"gpio16\",\n+};\n+\n+static const char * const pci_gnt1_groups[] = {\n+\t\"gpio17\",\n+};\n+\n+static const char * const pci_intb_groups[] = {\n+\t\"gpio18\",\n+};\n+\n+static const char * const pci_req0_groups[] = {\n+\t\"gpio19\",\n+};\n+\n+static const char * const pci_gnt0_groups[] = {\n+\t\"gpio20\",\n+};\n+\n+static const char * const pcmcia_cd1_groups[] = {\n+\t\"gpio22\",\n+};\n+\n+static const char * const pcmcia_cd2_groups[] = {\n+\t\"gpio23\",\n+};\n+\n+static const char * const pcmcia_vs1_groups[] = {\n+\t\"gpio24\",\n+};\n+\n+static const char * const pcmcia_vs2_groups[] = {\n+\t\"gpio25\",\n+};\n+\n+static const char * const ebi_cs2_groups[] = {\n+\t\"gpio26\",\n+};\n+\n+static const char * const ebi_cs3_groups[] = {\n+\t\"gpio27\",\n+};\n+\n+static const char * const spi_cs2_groups[] = {\n+\t\"gpio28\",\n+};\n+\n+static const char * const spi_cs3_groups[] = {\n+\t\"gpio29\",\n+};\n+\n+static const char * const spi_cs4_groups[] = {\n+\t\"gpio30\",\n+};\n+\n+static const char * const spi_cs5_groups[] = {\n+\t\"gpio31\",\n+};\n+\n+static const char * const uart1_groups[] = {\n+\t\"uart1_grp\",\n+};\n+\n+#define BCM6368_FUN(n, out)\t\t\t\t\\\n+\t{\t\t\t\t\t\t\\\n+\t\t.name = #n,\t\t\t\t\\\n+\t\t.groups = n##_groups,\t\t\t\\\n+\t\t.num_groups = ARRAY_SIZE(n##_groups),\t\\\n+\t\t.dir_out = out,\t\t\t\t\\\n+\t}\n+\n+#define BCM6368_BASEMODE_FUN(n, val, out)\t\t\\\n+\t{\t\t\t\t\t\t\\\n+\t\t.name = #n,\t\t\t\t\\\n+\t\t.groups = n##_groups,\t\t\t\\\n+\t\t.num_groups = ARRAY_SIZE(n##_groups),\t\\\n+\t\t.basemode = BCM6368_BASEMODE_##val,\t\\\n+\t\t.dir_out = out,\t\t\t\t\\\n+\t}\n+\n+static const struct bcm6368_function bcm6368_funcs[] = {\n+\tBCM6368_FUN(analog_afe_0, 1),\n+\tBCM6368_FUN(analog_afe_1, 1),\n+\tBCM6368_FUN(sys_irq, 1),\n+\tBCM6368_FUN(serial_led_data, 1),\n+\tBCM6368_FUN(serial_led_clk, 1),\n+\tBCM6368_FUN(inet_led, 1),\n+\tBCM6368_FUN(ephy0_led, 1),\n+\tBCM6368_FUN(ephy1_led, 1),\n+\tBCM6368_FUN(ephy2_led, 1),\n+\tBCM6368_FUN(ephy3_led, 1),\n+\tBCM6368_FUN(robosw_led_data, 1),\n+\tBCM6368_FUN(robosw_led_clk, 1),\n+\tBCM6368_FUN(robosw_led0, 1),\n+\tBCM6368_FUN(robosw_led1, 1),\n+\tBCM6368_FUN(usb_device_led, 1),\n+\tBCM6368_FUN(pci_req1, 0),\n+\tBCM6368_FUN(pci_gnt1, 0),\n+\tBCM6368_FUN(pci_intb, 0),\n+\tBCM6368_FUN(pci_req0, 0),\n+\tBCM6368_FUN(pci_gnt0, 0),\n+\tBCM6368_FUN(pcmcia_cd1, 0),\n+\tBCM6368_FUN(pcmcia_cd2, 0),\n+\tBCM6368_FUN(pcmcia_vs1, 0),\n+\tBCM6368_FUN(pcmcia_vs2, 0),\n+\tBCM6368_FUN(ebi_cs2, 1),\n+\tBCM6368_FUN(ebi_cs3, 1),\n+\tBCM6368_FUN(spi_cs2, 1),\n+\tBCM6368_FUN(spi_cs3, 1),\n+\tBCM6368_FUN(spi_cs4, 1),\n+\tBCM6368_FUN(spi_cs5, 1),\n+\tBCM6368_BASEMODE_FUN(uart1, UART1, 0x6),\n+};\n+\n+static int bcm6368_pinctrl_get_group_count(struct pinctrl_dev *pctldev)\n+{\n+\treturn ARRAY_SIZE(bcm6368_groups);\n+}\n+\n+static const char *bcm6368_pinctrl_get_group_name(struct pinctrl_dev *pctldev,\n+\t\t\t\t\t\t  unsigned group)\n+{\n+\treturn bcm6368_groups[group].name;\n+}\n+\n+static int bcm6368_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,\n+\t\t\t\t\t  unsigned group, const unsigned **pins,\n+\t\t\t\t\t  unsigned *num_pins)\n+{\n+\t*pins = bcm6368_groups[group].pins;\n+\t*num_pins = bcm6368_groups[group].num_pins;\n+\n+\treturn 0;\n+}\n+\n+static int bcm6368_pinctrl_get_func_count(struct pinctrl_dev *pctldev)\n+{\n+\treturn ARRAY_SIZE(bcm6368_funcs);\n+}\n+\n+static const char *bcm6368_pinctrl_get_func_name(struct pinctrl_dev *pctldev,\n+\t\t\t\t\t\t unsigned selector)\n+{\n+\treturn bcm6368_funcs[selector].name;\n+}\n+\n+static int bcm6368_pinctrl_get_groups(struct pinctrl_dev *pctldev,\n+\t\t\t\t      unsigned selector,\n+\t\t\t\t      const char * const **groups,\n+\t\t\t\t      unsigned * const num_groups)\n+{\n+\t*groups = bcm6368_funcs[selector].groups;\n+\t*num_groups = bcm6368_funcs[selector].num_groups;\n+\n+\treturn 0;\n+}\n+\n+static int bcm6368_pinctrl_set_mux(struct pinctrl_dev *pctldev,\n+\t\t\t\t   unsigned selector, unsigned group)\n+{\n+\tstruct bcm63xx_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);\n+\tstruct bcm6368_priv *priv = pc->driver_data;\n+\tconst struct bcm6368_pingroup *pg = &bcm6368_groups[group];\n+\tconst struct bcm6368_function *fun = &bcm6368_funcs[selector];\n+\tint i, pin;\n+\n+\tif (fun->basemode) {\n+\t\tunsigned int mask = 0;\n+\n+\t\tfor (i = 0; i < pg->num_pins; i++) {\n+\t\t\tpin = pg->pins[i];\n+\t\t\tif (pin < BCM63XX_BANK_GPIOS)\n+\t\t\t\tmask |= BIT(pin);\n+\t\t}\n+\n+\t\tregmap_update_bits(pc->regs, BCM6368_MODE_REG, mask, 0);\n+\t\tregmap_field_write(priv->overlays, fun->basemode);\n+\t} else {\n+\t\tpin = pg->pins[0];\n+\n+\t\tif (bcm6368_pins[pin].drv_data)\n+\t\t\tregmap_field_write(priv->overlays,\n+\t\t\t\t\t   BCM6368_BASEMODE_GPIO);\n+\n+\t\tregmap_update_bits(pc->regs, BCM6368_MODE_REG, BIT(pin),\n+\t\t\t\t   BIT(pin));\n+\t}\n+\n+\tfor (pin = 0; pin < pg->num_pins; pin++) {\n+\t\tstruct pinctrl_gpio_range *range;\n+\t\tint hw_gpio = bcm6368_pins[pin].number;\n+\n+\t\trange = pinctrl_find_gpio_range_from_pin(pctldev, hw_gpio);\n+\t\tif (range) {\n+\t\t\tstruct gpio_chip *gc = range->gc;\n+\n+\t\t\tif (fun->dir_out & BIT(pin))\n+\t\t\t\tgc->direction_output(gc, hw_gpio, 0);\n+\t\t\telse\n+\t\t\t\tgc->direction_input(gc, hw_gpio);\n+\t\t}\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int bcm6368_gpio_request_enable(struct pinctrl_dev *pctldev,\n+\t\t\t\t       struct pinctrl_gpio_range *range,\n+\t\t\t\t       unsigned offset)\n+{\n+\tstruct bcm63xx_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);\n+\tstruct bcm6368_priv *priv = pc->driver_data;\n+\n+\tif (offset >= BCM63XX_BANK_GPIOS && !bcm6368_pins[offset].drv_data)\n+\t\treturn 0;\n+\n+\t/* disable all functions using this pin */\n+\tif (offset < BCM63XX_BANK_GPIOS)\n+\t\tregmap_update_bits(pc->regs, BCM6368_MODE_REG, BIT(offset), 0);\n+\n+\tif (bcm6368_pins[offset].drv_data)\n+\t\tregmap_field_write(priv->overlays, BCM6368_BASEMODE_GPIO);\n+\n+\treturn 0;\n+}\n+\n+static struct pinctrl_ops bcm6368_pctl_ops = {\n+\t.dt_free_map = pinctrl_utils_free_map,\n+\t.dt_node_to_map = pinconf_generic_dt_node_to_map_pin,\n+\t.get_group_name = bcm6368_pinctrl_get_group_name,\n+\t.get_group_pins = bcm6368_pinctrl_get_group_pins,\n+\t.get_groups_count = bcm6368_pinctrl_get_group_count,\n+};\n+\n+static struct pinmux_ops bcm6368_pmx_ops = {\n+\t.get_function_groups = bcm6368_pinctrl_get_groups,\n+\t.get_function_name = bcm6368_pinctrl_get_func_name,\n+\t.get_functions_count = bcm6368_pinctrl_get_func_count,\n+\t.gpio_request_enable = bcm6368_gpio_request_enable,\n+\t.set_mux = bcm6368_pinctrl_set_mux,\n+\t.strict = true,\n+};\n+\n+static const struct bcm63xx_pinctrl_soc bcm6368_soc = {\n+\t.ngpios = BCM6368_NUM_GPIOS,\n+\t.npins = ARRAY_SIZE(bcm6368_pins),\n+\t.pctl_ops = &bcm6368_pctl_ops,\n+\t.pins = bcm6368_pins,\n+\t.pmx_ops = &bcm6368_pmx_ops,\n+};\n+\n+static int bcm6368_pinctrl_probe(struct platform_device *pdev)\n+{\n+\tstruct reg_field overlays = REG_FIELD(BCM6368_BASEMODE_REG, 0, 15);\n+\tstruct device *dev = &pdev->dev;\n+\tstruct bcm63xx_pinctrl *pc;\n+\tstruct bcm6368_priv *priv;\n+\tint err;\n+\n+\tpriv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);\n+\tif (!priv)\n+\t\treturn -ENOMEM;\n+\n+\terr = bcm63xx_pinctrl_probe(pdev, &bcm6368_soc, (void *) priv);\n+\tif (err)\n+\t\treturn err;\n+\n+\tpc = platform_get_drvdata(pdev);\n+\n+\tpriv->overlays = devm_regmap_field_alloc(dev, pc->regs, overlays);\n+\tif (IS_ERR(priv->overlays))\n+\t\treturn PTR_ERR(priv->overlays);\n+\n+\treturn 0;\n+}\n+\n+static const struct of_device_id bcm6368_pinctrl_match[] = {\n+\t{ .compatible = \"brcm,bcm6368-pinctrl\", },\n+\t{ /* sentinel */ }\n+};\n+\n+static struct platform_driver bcm6368_pinctrl_driver = {\n+\t.probe = bcm6368_pinctrl_probe,\n+\t.driver = {\n+\t\t.name = \"bcm6368-pinctrl\",\n+\t\t.of_match_table = bcm6368_pinctrl_match,\n+\t},\n+};\n+\n+builtin_platform_driver(bcm6368_pinctrl_driver);\n"
  },
  {
    "path": "target/linux/bmips/patches-5.10/068-v5.13-dt-bindings-add-BCM63268-pincontroller-binding-docum.patch",
    "content": "From 9b3303413379af8bed307cd465fe7aa1bc3569ea Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com>\nDate: Wed, 24 Mar 2021 09:19:18 +0100\nSubject: [PATCH 17/22] dt-bindings: add BCM63268 pincontroller binding\n documentation\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nAdd binding documentation for the pincontrol core found in the BCM63268\nfamily SoCs.\n\nCo-developed-by: Jonas Gorski <jonas.gorski@gmail.com>\nSigned-off-by: Jonas Gorski <jonas.gorski@gmail.com>\nSigned-off-by: Álvaro Fernández Rojas <noltari@gmail.com>\nReviewed-by: Rob Herring <robh@kernel.org>\nLink: https://lore.kernel.org/r/20210324081923.20379-18-noltari@gmail.com\nSigned-off-by: Linus Walleij <linus.walleij@linaro.org>\n---\n .../pinctrl/brcm,bcm63268-pinctrl.yaml        | 164 ++++++++++++++++++\n 1 file changed, 164 insertions(+)\n create mode 100644 Documentation/devicetree/bindings/pinctrl/brcm,bcm63268-pinctrl.yaml\n\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/pinctrl/brcm,bcm63268-pinctrl.yaml\n@@ -0,0 +1,164 @@\n+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause\n+%YAML 1.2\n+---\n+$id: http://devicetree.org/schemas/pinctrl/brcm,bcm63268-pinctrl.yaml#\n+$schema: http://devicetree.org/meta-schemas/core.yaml#\n+\n+title: Broadcom BCM63268 pin controller\n+\n+maintainers:\n+  - Álvaro Fernández Rojas <noltari@gmail.com>\n+  - Jonas Gorski <jonas.gorski@gmail.com>\n+\n+description:\n+  Bindings for Broadcom's BCM63268 memory-mapped pin controller.\n+\n+properties:\n+  compatible:\n+    const: brcm,bcm63268-pinctrl\n+\n+  reg:\n+    maxItems: 3\n+\n+patternProperties:\n+  '-pins$':\n+    type: object\n+    $ref: pinmux-node.yaml#\n+\n+    properties:\n+      function:\n+        enum: [ serial_led_clk, serial_led_data, hsspi_cs4, hsspi_cs5,\n+                hsspi_cs6, hsspi_cs7, adsl_spi_miso, adsl_spi_mosi,\n+                vreq_clk, pcie_clkreq_b, robosw_led_clk, robosw_led_data,\n+                nand, gpio35_alt, dectpd, vdsl_phy_override_0,\n+                vdsl_phy_override_1, vdsl_phy_override_2,\n+                vdsl_phy_override_3, dsl_gpio8, dsl_gpio9 ]\n+\n+      pins:\n+        enum: [ gpio0, gpio1, gpio16, gpio17, gpio8, gpio9, gpio18, gpio19,\n+                gpio22, gpio23, gpio30, gpio31, nand_grp, gpio35\n+                dectpd_grp, vdsl_phy_override_0_grp,\n+                vdsl_phy_override_1_grp, vdsl_phy_override_2_grp,\n+                vdsl_phy_override_3_grp, dsl_gpio8, dsl_gpio9 ]\n+\n+required:\n+  - compatible\n+  - reg\n+\n+additionalProperties: false\n+\n+examples:\n+  - |\n+    pinctrl@10 {\n+      compatible = \"brcm,bcm63268-pinctrl\";\n+      reg = <0x10 0x4>, <0x18 0x8>, <0x38 0x4>;\n+\n+      pinctrl_serial_led: serial_led-pins {\n+        pinctrl_serial_led_clk: serial_led_clk-pins {\n+          function = \"serial_led_clk\";\n+          pins = \"gpio0\";\n+        };\n+\n+        pinctrl_serial_led_data: serial_led_data-pins {\n+          function = \"serial_led_data\";\n+          pins = \"gpio1\";\n+        };\n+      };\n+\n+      pinctrl_hsspi_cs4: hsspi_cs4-pins {\n+        function = \"hsspi_cs4\";\n+        pins = \"gpio16\";\n+      };\n+\n+      pinctrl_hsspi_cs5: hsspi_cs5-pins {\n+        function = \"hsspi_cs5\";\n+        pins = \"gpio17\";\n+      };\n+\n+      pinctrl_hsspi_cs6: hsspi_cs6-pins {\n+        function = \"hsspi_cs6\";\n+        pins = \"gpio8\";\n+      };\n+\n+      pinctrl_hsspi_cs7: hsspi_cs7-pins {\n+        function = \"hsspi_cs7\";\n+        pins = \"gpio9\";\n+      };\n+\n+      pinctrl_adsl_spi: adsl_spi-pins {\n+        pinctrl_adsl_spi_miso: adsl_spi_miso-pins {\n+          function = \"adsl_spi_miso\";\n+          pins = \"gpio18\";\n+        };\n+\n+        pinctrl_adsl_spi_mosi: adsl_spi_mosi-pins {\n+          function = \"adsl_spi_mosi\";\n+          pins = \"gpio19\";\n+        };\n+      };\n+\n+      pinctrl_vreq_clk: vreq_clk-pins {\n+        function = \"vreq_clk\";\n+        pins = \"gpio22\";\n+      };\n+\n+      pinctrl_pcie_clkreq_b: pcie_clkreq_b-pins {\n+        function = \"pcie_clkreq_b\";\n+        pins = \"gpio23\";\n+      };\n+\n+      pinctrl_robosw_led_clk: robosw_led_clk-pins {\n+        function = \"robosw_led_clk\";\n+        pins = \"gpio30\";\n+      };\n+\n+      pinctrl_robosw_led_data: robosw_led_data-pins {\n+        function = \"robosw_led_data\";\n+        pins = \"gpio31\";\n+      };\n+\n+      pinctrl_nand: nand-pins {\n+        function = \"nand\";\n+        group = \"nand_grp\";\n+      };\n+\n+      pinctrl_gpio35_alt: gpio35_alt-pins {\n+        function = \"gpio35_alt\";\n+        pin = \"gpio35\";\n+      };\n+\n+      pinctrl_dectpd: dectpd-pins {\n+        function = \"dectpd\";\n+        group = \"dectpd_grp\";\n+      };\n+\n+      pinctrl_vdsl_phy_override_0: vdsl_phy_override_0-pins {\n+        function = \"vdsl_phy_override_0\";\n+        group = \"vdsl_phy_override_0_grp\";\n+      };\n+\n+      pinctrl_vdsl_phy_override_1: vdsl_phy_override_1-pins {\n+        function = \"vdsl_phy_override_1\";\n+        group = \"vdsl_phy_override_1_grp\";\n+      };\n+\n+      pinctrl_vdsl_phy_override_2: vdsl_phy_override_2-pins {\n+        function = \"vdsl_phy_override_2\";\n+        group = \"vdsl_phy_override_2_grp\";\n+      };\n+\n+      pinctrl_vdsl_phy_override_3: vdsl_phy_override_3-pins {\n+        function = \"vdsl_phy_override_3\";\n+        group = \"vdsl_phy_override_3_grp\";\n+      };\n+\n+      pinctrl_dsl_gpio8: dsl_gpio8-pins {\n+        function = \"dsl_gpio8\";\n+        group = \"dsl_gpio8\";\n+      };\n+\n+      pinctrl_dsl_gpio9: dsl_gpio9-pins {\n+        function = \"dsl_gpio9\";\n+        group = \"dsl_gpio9\";\n+      };\n+    };\n"
  },
  {
    "path": "target/linux/bmips/patches-5.10/069-v5.13-dt-bindings-add-BCM63268-GPIO-sysctl-binding-documen.patch",
    "content": "From ff8324355d7ae2e4ebbd304de27bb5fa75e20c6a Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com>\nDate: Wed, 24 Mar 2021 09:19:19 +0100\nSubject: [PATCH 18/22] dt-bindings: add BCM63268 GPIO sysctl binding\n documentation\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nAdd binding documentation for the GPIO sysctl found in BCM63268 SoCs.\n\nSigned-off-by: Álvaro Fernández Rojas <noltari@gmail.com>\nReviewed-by: Rob Herring <robh@kernel.org>\nLink: https://lore.kernel.org/r/20210324081923.20379-19-noltari@gmail.com\nSigned-off-by: Linus Walleij <linus.walleij@linaro.org>\n---\n .../mfd/brcm,bcm63268-gpio-sysctl.yaml        | 194 ++++++++++++++++++\n 1 file changed, 194 insertions(+)\n create mode 100644 Documentation/devicetree/bindings/mfd/brcm,bcm63268-gpio-sysctl.yaml\n\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/mfd/brcm,bcm63268-gpio-sysctl.yaml\n@@ -0,0 +1,194 @@\n+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)\n+%YAML 1.2\n+---\n+$id: http://devicetree.org/schemas/mfd/brcm,bcm63268-gpio-sysctl.yaml#\n+$schema: http://devicetree.org/meta-schemas/core.yaml#\n+\n+title: Broadcom BCM63268 GPIO System Controller Device Tree Bindings\n+\n+maintainers:\n+  - Álvaro Fernández Rojas <noltari@gmail.com>\n+  - Jonas Gorski <jonas.gorski@gmail.com>\n+\n+description:\n+  Broadcom BCM63268 SoC GPIO system controller which provides a register map\n+  for controlling the GPIO and pins of the SoC.\n+\n+properties:\n+  \"#address-cells\": true\n+\n+  \"#size-cells\": true\n+\n+  compatible:\n+    items:\n+      - const: brcm,bcm63268-gpio-sysctl\n+      - const: syscon\n+      - const: simple-mfd\n+\n+  ranges:\n+    maxItems: 1\n+\n+  reg:\n+    maxItems: 1\n+\n+patternProperties:\n+  \"^gpio@[0-9a-f]+$\":\n+    # Child node\n+    type: object\n+    $ref: \"../gpio/brcm,bcm6345-gpio.yaml\"\n+    description:\n+      GPIO controller for the SoC GPIOs. This child node definition\n+      should follow the bindings specified in\n+      Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.yaml.\n+\n+  \"^pinctrl@[0-9a-f]+$\":\n+    # Child node\n+    type: object\n+    $ref: \"../pinctrl/brcm,bcm63268-pinctrl.yaml\"\n+    description:\n+      Pin controller for the SoC pins. This child node definition\n+      should follow the bindings specified in\n+      Documentation/devicetree/bindings/pinctrl/brcm,bcm63268-pinctrl.yaml.\n+\n+required:\n+  - \"#address-cells\"\n+  - compatible\n+  - ranges\n+  - reg\n+  - \"#size-cells\"\n+\n+additionalProperties: false\n+\n+examples:\n+  - |\n+    syscon@100000c0 {\n+      #address-cells = <1>;\n+      #size-cells = <1>;\n+      compatible = \"brcm,bcm63268-gpio-sysctl\", \"syscon\", \"simple-mfd\";\n+      reg = <0x100000c0 0x80>;\n+      ranges = <0 0x100000c0 0x80>;\n+\n+      gpio@0 {\n+        compatible = \"brcm,bcm63268-gpio\";\n+        reg-names = \"dirout\", \"dat\";\n+        reg = <0x0 0x8>, <0x8 0x8>;\n+\n+        gpio-controller;\n+        gpio-ranges = <&pinctrl 0 0 52>;\n+        #gpio-cells = <2>;\n+      };\n+\n+      pinctrl: pinctrl@10 {\n+        compatible = \"brcm,bcm63268-pinctrl\";\n+        reg = <0x10 0x4>, <0x18 0x8>, <0x38 0x4>;\n+\n+        pinctrl_serial_led: serial_led-pins {\n+          pinctrl_serial_led_clk: serial_led_clk-pins {\n+            function = \"serial_led_clk\";\n+            pins = \"gpio0\";\n+          };\n+\n+          pinctrl_serial_led_data: serial_led_data-pins {\n+            function = \"serial_led_data\";\n+            pins = \"gpio1\";\n+          };\n+        };\n+\n+        pinctrl_hsspi_cs4: hsspi_cs4-pins {\n+          function = \"hsspi_cs4\";\n+          pins = \"gpio16\";\n+        };\n+\n+        pinctrl_hsspi_cs5: hsspi_cs5-pins {\n+          function = \"hsspi_cs5\";\n+          pins = \"gpio17\";\n+        };\n+\n+        pinctrl_hsspi_cs6: hsspi_cs6-pins {\n+          function = \"hsspi_cs6\";\n+          pins = \"gpio8\";\n+        };\n+\n+        pinctrl_hsspi_cs7: hsspi_cs7-pins {\n+          function = \"hsspi_cs7\";\n+          pins = \"gpio9\";\n+        };\n+\n+        pinctrl_adsl_spi: adsl_spi-pins {\n+          pinctrl_adsl_spi_miso: adsl_spi_miso-pins {\n+            function = \"adsl_spi_miso\";\n+            pins = \"gpio18\";\n+          };\n+\n+          pinctrl_adsl_spi_mosi: adsl_spi_mosi-pins {\n+            function = \"adsl_spi_mosi\";\n+            pins = \"gpio19\";\n+          };\n+        };\n+\n+        pinctrl_vreq_clk: vreq_clk-pins {\n+          function = \"vreq_clk\";\n+          pins = \"gpio22\";\n+        };\n+\n+        pinctrl_pcie_clkreq_b: pcie_clkreq_b-pins {\n+          function = \"pcie_clkreq_b\";\n+          pins = \"gpio23\";\n+        };\n+\n+        pinctrl_robosw_led_clk: robosw_led_clk-pins {\n+          function = \"robosw_led_clk\";\n+          pins = \"gpio30\";\n+        };\n+\n+        pinctrl_robosw_led_data: robosw_led_data-pins {\n+          function = \"robosw_led_data\";\n+          pins = \"gpio31\";\n+        };\n+\n+        pinctrl_nand: nand-pins {\n+          function = \"nand\";\n+          group = \"nand_grp\";\n+        };\n+\n+        pinctrl_gpio35_alt: gpio35_alt-pins {\n+          function = \"gpio35_alt\";\n+          pin = \"gpio35\";\n+        };\n+\n+        pinctrl_dectpd: dectpd-pins {\n+          function = \"dectpd\";\n+          group = \"dectpd_grp\";\n+        };\n+\n+        pinctrl_vdsl_phy_override_0: vdsl_phy_override_0-pins {\n+          function = \"vdsl_phy_override_0\";\n+          group = \"vdsl_phy_override_0_grp\";\n+        };\n+\n+        pinctrl_vdsl_phy_override_1: vdsl_phy_override_1-pins {\n+          function = \"vdsl_phy_override_1\";\n+          group = \"vdsl_phy_override_1_grp\";\n+        };\n+\n+        pinctrl_vdsl_phy_override_2: vdsl_phy_override_2-pins {\n+          function = \"vdsl_phy_override_2\";\n+          group = \"vdsl_phy_override_2_grp\";\n+        };\n+\n+        pinctrl_vdsl_phy_override_3: vdsl_phy_override_3-pins {\n+          function = \"vdsl_phy_override_3\";\n+          group = \"vdsl_phy_override_3_grp\";\n+        };\n+\n+        pinctrl_dsl_gpio8: dsl_gpio8-pins {\n+          function = \"dsl_gpio8\";\n+          group = \"dsl_gpio8\";\n+        };\n+\n+        pinctrl_dsl_gpio9: dsl_gpio9-pins {\n+          function = \"dsl_gpio9\";\n+          group = \"dsl_gpio9\";\n+        };\n+      };\n+    };\n"
  },
  {
    "path": "target/linux/bmips/patches-5.10/070-v5.13-pinctrl-add-a-pincontrol-driver-for-BCM63268.patch",
    "content": "From 155cca1b0794a8f541e7eaa45be70df0a49964f3 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com>\nDate: Wed, 24 Mar 2021 09:19:20 +0100\nSubject: [PATCH 19/22] pinctrl: add a pincontrol driver for BCM63268\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nAdd a pincontrol driver for BCM63268. BCM63268 allows muxing GPIOs\nto different functions. Depending on the mux, these are either single\npin configurations or whole pin groups.\n\nCo-developed-by: Jonas Gorski <jonas.gorski@gmail.com>\nSigned-off-by: Jonas Gorski <jonas.gorski@gmail.com>\nSigned-off-by: Álvaro Fernández Rojas <noltari@gmail.com>\nLink: https://lore.kernel.org/r/20210324081923.20379-20-noltari@gmail.com\nSigned-off-by: Linus Walleij <linus.walleij@linaro.org>\n---\n drivers/pinctrl/bcm/Kconfig            |   8 +\n drivers/pinctrl/bcm/Makefile           |   1 +\n drivers/pinctrl/bcm/pinctrl-bcm63268.c | 643 +++++++++++++++++++++++++\n 3 files changed, 652 insertions(+)\n create mode 100644 drivers/pinctrl/bcm/pinctrl-bcm63268.c\n\n--- a/drivers/pinctrl/bcm/Kconfig\n+++ b/drivers/pinctrl/bcm/Kconfig\n@@ -68,6 +68,14 @@ config PINCTRL_BCM6368\n \thelp\n \t   Say Y here to enable the Broadcom BCM6368 GPIO driver.\n \n+config PINCTRL_BCM63268\n+\tbool \"Broadcom BCM63268 GPIO driver\"\n+\tdepends on (BMIPS_GENERIC || COMPILE_TEST)\n+\tselect PINCTRL_BCM63XX\n+\tdefault BMIPS_GENERIC\n+\thelp\n+\t   Say Y here to enable the Broadcom BCM63268 GPIO driver.\n+\n config PINCTRL_IPROC_GPIO\n \tbool \"Broadcom iProc GPIO (with PINCONF) driver\"\n \tdepends on OF_GPIO && (ARCH_BCM_IPROC || COMPILE_TEST)\n--- a/drivers/pinctrl/bcm/Makefile\n+++ b/drivers/pinctrl/bcm/Makefile\n@@ -8,6 +8,7 @@ obj-$(CONFIG_PINCTRL_BCM6328)\t\t+= pinctr\n obj-$(CONFIG_PINCTRL_BCM6358)\t\t+= pinctrl-bcm6358.o\n obj-$(CONFIG_PINCTRL_BCM6362)\t\t+= pinctrl-bcm6362.o\n obj-$(CONFIG_PINCTRL_BCM6368)\t\t+= pinctrl-bcm6368.o\n+obj-$(CONFIG_PINCTRL_BCM63268)\t\t+= pinctrl-bcm63268.o\n obj-$(CONFIG_PINCTRL_IPROC_GPIO)\t+= pinctrl-iproc-gpio.o\n obj-$(CONFIG_PINCTRL_CYGNUS_MUX)\t+= pinctrl-cygnus-mux.o\n obj-$(CONFIG_PINCTRL_NS)\t\t+= pinctrl-ns.o\n--- /dev/null\n+++ b/drivers/pinctrl/bcm/pinctrl-bcm63268.c\n@@ -0,0 +1,643 @@\n+// SPDX-License-Identifier: GPL-2.0+\n+/*\n+ * Driver for BCM63268 GPIO unit (pinctrl + GPIO)\n+ *\n+ * Copyright (C) 2021 Álvaro Fernández Rojas <noltari@gmail.com>\n+ * Copyright (C) 2016 Jonas Gorski <jonas.gorski@gmail.com>\n+ */\n+\n+#include <linux/bits.h>\n+#include <linux/gpio/driver.h>\n+#include <linux/kernel.h>\n+#include <linux/of.h>\n+#include <linux/pinctrl/pinmux.h>\n+#include <linux/platform_device.h>\n+#include <linux/regmap.h>\n+\n+#include \"../pinctrl-utils.h\"\n+\n+#include \"pinctrl-bcm63xx.h\"\n+\n+#define BCM63268_NUM_GPIOS\t\t52\n+#define BCM63268_NUM_LEDS\t\t24\n+\n+#define BCM63268_LED_REG\t\t0x10\n+#define BCM63268_MODE_REG\t\t0x18\n+#define BCM63268_CTRL_REG\t\t0x1c\n+#define BCM63268_BASEMODE_REG\t\t0x38\n+#define  BCM63268_BASEMODE_NAND\t\tBIT(2) /* GPIOs 2-7, 24-31 */\n+#define  BCM63268_BASEMODE_GPIO35\tBIT(4) /* GPIO 35 */\n+#define  BCM63268_BASEMODE_DECTPD\tBIT(5) /* GPIOs 8/9 */\n+#define  BCM63268_BASEMODE_VDSL_PHY_0\tBIT(6) /* GPIOs 10/11 */\n+#define  BCM63268_BASEMODE_VDSL_PHY_1\tBIT(7) /* GPIOs 12/13 */\n+#define  BCM63268_BASEMODE_VDSL_PHY_2\tBIT(8) /* GPIOs 24/25 */\n+#define  BCM63268_BASEMODE_VDSL_PHY_3\tBIT(9) /* GPIOs 26/27 */\n+\n+enum bcm63268_pinctrl_reg {\n+\tBCM63268_LEDCTRL,\n+\tBCM63268_MODE,\n+\tBCM63268_CTRL,\n+\tBCM63268_BASEMODE,\n+};\n+\n+struct bcm63268_pingroup {\n+\tconst char *name;\n+\tconst unsigned * const pins;\n+\tconst unsigned num_pins;\n+};\n+\n+struct bcm63268_function {\n+\tconst char *name;\n+\tconst char * const *groups;\n+\tconst unsigned num_groups;\n+\n+\tenum bcm63268_pinctrl_reg reg;\n+\tuint32_t mask;\n+};\n+\n+#define BCM63268_PIN(a, b, basemode)\t\t\t\\\n+\t{\t\t\t\t\t\t\\\n+\t\t.number = a,\t\t\t\t\\\n+\t\t.name = b,\t\t\t\t\\\n+\t\t.drv_data = (void *)(basemode)\t\t\\\n+\t}\n+\n+static const struct pinctrl_pin_desc bcm63268_pins[] = {\n+\tPINCTRL_PIN(0, \"gpio0\"),\n+\tPINCTRL_PIN(1, \"gpio1\"),\n+\tBCM63268_PIN(2, \"gpio2\", BCM63268_BASEMODE_NAND),\n+\tBCM63268_PIN(3, \"gpio3\", BCM63268_BASEMODE_NAND),\n+\tBCM63268_PIN(4, \"gpio4\", BCM63268_BASEMODE_NAND),\n+\tBCM63268_PIN(5, \"gpio5\", BCM63268_BASEMODE_NAND),\n+\tBCM63268_PIN(6, \"gpio6\", BCM63268_BASEMODE_NAND),\n+\tBCM63268_PIN(7, \"gpio7\", BCM63268_BASEMODE_NAND),\n+\tBCM63268_PIN(8, \"gpio8\", BCM63268_BASEMODE_DECTPD),\n+\tBCM63268_PIN(9, \"gpio9\", BCM63268_BASEMODE_DECTPD),\n+\tBCM63268_PIN(10, \"gpio10\", BCM63268_BASEMODE_VDSL_PHY_0),\n+\tBCM63268_PIN(11, \"gpio11\", BCM63268_BASEMODE_VDSL_PHY_0),\n+\tBCM63268_PIN(12, \"gpio12\", BCM63268_BASEMODE_VDSL_PHY_1),\n+\tBCM63268_PIN(13, \"gpio13\", BCM63268_BASEMODE_VDSL_PHY_1),\n+\tPINCTRL_PIN(14, \"gpio14\"),\n+\tPINCTRL_PIN(15, \"gpio15\"),\n+\tPINCTRL_PIN(16, \"gpio16\"),\n+\tPINCTRL_PIN(17, \"gpio17\"),\n+\tPINCTRL_PIN(18, \"gpio18\"),\n+\tPINCTRL_PIN(19, \"gpio19\"),\n+\tPINCTRL_PIN(20, \"gpio20\"),\n+\tPINCTRL_PIN(21, \"gpio21\"),\n+\tPINCTRL_PIN(22, \"gpio22\"),\n+\tPINCTRL_PIN(23, \"gpio23\"),\n+\tBCM63268_PIN(24, \"gpio24\",\n+\t\t     BCM63268_BASEMODE_NAND | BCM63268_BASEMODE_VDSL_PHY_2),\n+\tBCM63268_PIN(25, \"gpio25\",\n+\t\t     BCM63268_BASEMODE_NAND | BCM63268_BASEMODE_VDSL_PHY_2),\n+\tBCM63268_PIN(26, \"gpio26\",\n+\t\t     BCM63268_BASEMODE_NAND | BCM63268_BASEMODE_VDSL_PHY_3),\n+\tBCM63268_PIN(27, \"gpio27\",\n+\t\t     BCM63268_BASEMODE_NAND | BCM63268_BASEMODE_VDSL_PHY_3),\n+\tBCM63268_PIN(28, \"gpio28\", BCM63268_BASEMODE_NAND),\n+\tBCM63268_PIN(29, \"gpio29\", BCM63268_BASEMODE_NAND),\n+\tBCM63268_PIN(30, \"gpio30\", BCM63268_BASEMODE_NAND),\n+\tBCM63268_PIN(31, \"gpio31\", BCM63268_BASEMODE_NAND),\n+\tPINCTRL_PIN(32, \"gpio32\"),\n+\tPINCTRL_PIN(33, \"gpio33\"),\n+\tPINCTRL_PIN(34, \"gpio34\"),\n+\tPINCTRL_PIN(35, \"gpio35\"),\n+\tPINCTRL_PIN(36, \"gpio36\"),\n+\tPINCTRL_PIN(37, \"gpio37\"),\n+\tPINCTRL_PIN(38, \"gpio38\"),\n+\tPINCTRL_PIN(39, \"gpio39\"),\n+\tPINCTRL_PIN(40, \"gpio40\"),\n+\tPINCTRL_PIN(41, \"gpio41\"),\n+\tPINCTRL_PIN(42, \"gpio42\"),\n+\tPINCTRL_PIN(43, \"gpio43\"),\n+\tPINCTRL_PIN(44, \"gpio44\"),\n+\tPINCTRL_PIN(45, \"gpio45\"),\n+\tPINCTRL_PIN(46, \"gpio46\"),\n+\tPINCTRL_PIN(47, \"gpio47\"),\n+\tPINCTRL_PIN(48, \"gpio48\"),\n+\tPINCTRL_PIN(49, \"gpio49\"),\n+\tPINCTRL_PIN(50, \"gpio50\"),\n+\tPINCTRL_PIN(51, \"gpio51\"),\n+};\n+\n+static unsigned gpio0_pins[] = { 0 };\n+static unsigned gpio1_pins[] = { 1 };\n+static unsigned gpio2_pins[] = { 2 };\n+static unsigned gpio3_pins[] = { 3 };\n+static unsigned gpio4_pins[] = { 4 };\n+static unsigned gpio5_pins[] = { 5 };\n+static unsigned gpio6_pins[] = { 6 };\n+static unsigned gpio7_pins[] = { 7 };\n+static unsigned gpio8_pins[] = { 8 };\n+static unsigned gpio9_pins[] = { 9 };\n+static unsigned gpio10_pins[] = { 10 };\n+static unsigned gpio11_pins[] = { 11 };\n+static unsigned gpio12_pins[] = { 12 };\n+static unsigned gpio13_pins[] = { 13 };\n+static unsigned gpio14_pins[] = { 14 };\n+static unsigned gpio15_pins[] = { 15 };\n+static unsigned gpio16_pins[] = { 16 };\n+static unsigned gpio17_pins[] = { 17 };\n+static unsigned gpio18_pins[] = { 18 };\n+static unsigned gpio19_pins[] = { 19 };\n+static unsigned gpio20_pins[] = { 20 };\n+static unsigned gpio21_pins[] = { 21 };\n+static unsigned gpio22_pins[] = { 22 };\n+static unsigned gpio23_pins[] = { 23 };\n+static unsigned gpio24_pins[] = { 24 };\n+static unsigned gpio25_pins[] = { 25 };\n+static unsigned gpio26_pins[] = { 26 };\n+static unsigned gpio27_pins[] = { 27 };\n+static unsigned gpio28_pins[] = { 28 };\n+static unsigned gpio29_pins[] = { 29 };\n+static unsigned gpio30_pins[] = { 30 };\n+static unsigned gpio31_pins[] = { 31 };\n+static unsigned gpio32_pins[] = { 32 };\n+static unsigned gpio33_pins[] = { 33 };\n+static unsigned gpio34_pins[] = { 34 };\n+static unsigned gpio35_pins[] = { 35 };\n+static unsigned gpio36_pins[] = { 36 };\n+static unsigned gpio37_pins[] = { 37 };\n+static unsigned gpio38_pins[] = { 38 };\n+static unsigned gpio39_pins[] = { 39 };\n+static unsigned gpio40_pins[] = { 40 };\n+static unsigned gpio41_pins[] = { 41 };\n+static unsigned gpio42_pins[] = { 42 };\n+static unsigned gpio43_pins[] = { 43 };\n+static unsigned gpio44_pins[] = { 44 };\n+static unsigned gpio45_pins[] = { 45 };\n+static unsigned gpio46_pins[] = { 46 };\n+static unsigned gpio47_pins[] = { 47 };\n+static unsigned gpio48_pins[] = { 48 };\n+static unsigned gpio49_pins[] = { 49 };\n+static unsigned gpio50_pins[] = { 50 };\n+static unsigned gpio51_pins[] = { 51 };\n+\n+static unsigned nand_grp_pins[] = {\n+\t2, 3, 4, 5, 6, 7, 24,\n+\t25, 26, 27, 28, 29, 30, 31,\n+};\n+\n+static unsigned dectpd_grp_pins[] = { 8, 9 };\n+static unsigned vdsl_phy0_grp_pins[] = { 10, 11 };\n+static unsigned vdsl_phy1_grp_pins[] = { 12, 13 };\n+static unsigned vdsl_phy2_grp_pins[] = { 24, 25 };\n+static unsigned vdsl_phy3_grp_pins[] = { 26, 27 };\n+\n+#define BCM63268_GROUP(n)\t\t\t\t\t\\\n+\t{\t\t\t\t\t\t\t\\\n+\t\t.name = #n,\t\t\t\t\t\\\n+\t\t.pins = n##_pins,\t\t\t\t\\\n+\t\t.num_pins = ARRAY_SIZE(n##_pins),\t\t\\\n+\t}\n+\n+static struct bcm63268_pingroup bcm63268_groups[] = {\n+\tBCM63268_GROUP(gpio0),\n+\tBCM63268_GROUP(gpio1),\n+\tBCM63268_GROUP(gpio2),\n+\tBCM63268_GROUP(gpio3),\n+\tBCM63268_GROUP(gpio4),\n+\tBCM63268_GROUP(gpio5),\n+\tBCM63268_GROUP(gpio6),\n+\tBCM63268_GROUP(gpio7),\n+\tBCM63268_GROUP(gpio8),\n+\tBCM63268_GROUP(gpio9),\n+\tBCM63268_GROUP(gpio10),\n+\tBCM63268_GROUP(gpio11),\n+\tBCM63268_GROUP(gpio12),\n+\tBCM63268_GROUP(gpio13),\n+\tBCM63268_GROUP(gpio14),\n+\tBCM63268_GROUP(gpio15),\n+\tBCM63268_GROUP(gpio16),\n+\tBCM63268_GROUP(gpio17),\n+\tBCM63268_GROUP(gpio18),\n+\tBCM63268_GROUP(gpio19),\n+\tBCM63268_GROUP(gpio20),\n+\tBCM63268_GROUP(gpio21),\n+\tBCM63268_GROUP(gpio22),\n+\tBCM63268_GROUP(gpio23),\n+\tBCM63268_GROUP(gpio24),\n+\tBCM63268_GROUP(gpio25),\n+\tBCM63268_GROUP(gpio26),\n+\tBCM63268_GROUP(gpio27),\n+\tBCM63268_GROUP(gpio28),\n+\tBCM63268_GROUP(gpio29),\n+\tBCM63268_GROUP(gpio30),\n+\tBCM63268_GROUP(gpio31),\n+\tBCM63268_GROUP(gpio32),\n+\tBCM63268_GROUP(gpio33),\n+\tBCM63268_GROUP(gpio34),\n+\tBCM63268_GROUP(gpio35),\n+\tBCM63268_GROUP(gpio36),\n+\tBCM63268_GROUP(gpio37),\n+\tBCM63268_GROUP(gpio38),\n+\tBCM63268_GROUP(gpio39),\n+\tBCM63268_GROUP(gpio40),\n+\tBCM63268_GROUP(gpio41),\n+\tBCM63268_GROUP(gpio42),\n+\tBCM63268_GROUP(gpio43),\n+\tBCM63268_GROUP(gpio44),\n+\tBCM63268_GROUP(gpio45),\n+\tBCM63268_GROUP(gpio46),\n+\tBCM63268_GROUP(gpio47),\n+\tBCM63268_GROUP(gpio48),\n+\tBCM63268_GROUP(gpio49),\n+\tBCM63268_GROUP(gpio50),\n+\tBCM63268_GROUP(gpio51),\n+\n+\t/* multi pin groups */\n+\tBCM63268_GROUP(nand_grp),\n+\tBCM63268_GROUP(dectpd_grp),\n+\tBCM63268_GROUP(vdsl_phy0_grp),\n+\tBCM63268_GROUP(vdsl_phy1_grp),\n+\tBCM63268_GROUP(vdsl_phy2_grp),\n+\tBCM63268_GROUP(vdsl_phy3_grp),\n+};\n+\n+static const char * const led_groups[] = {\n+\t\"gpio0\",\n+\t\"gpio1\",\n+\t\"gpio2\",\n+\t\"gpio3\",\n+\t\"gpio4\",\n+\t\"gpio5\",\n+\t\"gpio6\",\n+\t\"gpio7\",\n+\t\"gpio8\",\n+\t\"gpio9\",\n+\t\"gpio10\",\n+\t\"gpio11\",\n+\t\"gpio12\",\n+\t\"gpio13\",\n+\t\"gpio14\",\n+\t\"gpio15\",\n+\t\"gpio16\",\n+\t\"gpio17\",\n+\t\"gpio18\",\n+\t\"gpio19\",\n+\t\"gpio20\",\n+\t\"gpio21\",\n+\t\"gpio22\",\n+\t\"gpio23\",\n+};\n+\n+static const char * const serial_led_clk_groups[] = {\n+\t\"gpio0\",\n+};\n+\n+static const char * const serial_led_data_groups[] = {\n+\t\"gpio1\",\n+};\n+\n+static const char * const hsspi_cs4_groups[] = {\n+\t\"gpio16\",\n+};\n+\n+static const char * const hsspi_cs5_groups[] = {\n+\t\"gpio17\",\n+};\n+\n+static const char * const hsspi_cs6_groups[] = {\n+\t\"gpio8\",\n+};\n+\n+static const char * const hsspi_cs7_groups[] = {\n+\t\"gpio9\",\n+};\n+\n+static const char * const uart1_scts_groups[] = {\n+\t\"gpio10\",\n+\t\"gpio24\",\n+};\n+\n+static const char * const uart1_srts_groups[] = {\n+\t\"gpio11\",\n+\t\"gpio25\",\n+};\n+\n+static const char * const uart1_sdin_groups[] = {\n+\t\"gpio12\",\n+\t\"gpio26\",\n+};\n+\n+static const char * const uart1_sdout_groups[] = {\n+\t\"gpio13\",\n+\t\"gpio27\",\n+};\n+\n+static const char * const ntr_pulse_in_groups[] = {\n+\t\"gpio14\",\n+\t\"gpio28\",\n+};\n+\n+static const char * const dsl_ntr_pulse_out_groups[] = {\n+\t\"gpio15\",\n+\t\"gpio29\",\n+};\n+\n+static const char * const adsl_spi_miso_groups[] = {\n+\t\"gpio18\",\n+};\n+\n+static const char * const adsl_spi_mosi_groups[] = {\n+\t\"gpio19\",\n+};\n+\n+static const char * const vreg_clk_groups[] = {\n+\t\"gpio22\",\n+};\n+\n+static const char * const pcie_clkreq_b_groups[] = {\n+\t\"gpio23\",\n+};\n+\n+static const char * const switch_led_clk_groups[] = {\n+\t\"gpio30\",\n+};\n+\n+static const char * const switch_led_data_groups[] = {\n+\t\"gpio31\",\n+};\n+\n+static const char * const wifi_groups[] = {\n+\t\"gpio32\",\n+\t\"gpio33\",\n+\t\"gpio34\",\n+\t\"gpio35\",\n+\t\"gpio36\",\n+\t\"gpio37\",\n+\t\"gpio38\",\n+\t\"gpio39\",\n+\t\"gpio40\",\n+\t\"gpio41\",\n+\t\"gpio42\",\n+\t\"gpio43\",\n+\t\"gpio44\",\n+\t\"gpio45\",\n+\t\"gpio46\",\n+\t\"gpio47\",\n+\t\"gpio48\",\n+\t\"gpio49\",\n+\t\"gpio50\",\n+\t\"gpio51\",\n+};\n+\n+static const char * const nand_groups[] = {\n+\t\"nand_grp\",\n+};\n+\n+static const char * const dectpd_groups[] = {\n+\t\"dectpd_grp\",\n+};\n+\n+static const char * const vdsl_phy_override_0_groups[] = {\n+\t\"vdsl_phy_override_0_grp\",\n+};\n+\n+static const char * const vdsl_phy_override_1_groups[] = {\n+\t\"vdsl_phy_override_1_grp\",\n+};\n+\n+static const char * const vdsl_phy_override_2_groups[] = {\n+\t\"vdsl_phy_override_2_grp\",\n+};\n+\n+static const char * const vdsl_phy_override_3_groups[] = {\n+\t\"vdsl_phy_override_3_grp\",\n+};\n+\n+#define BCM63268_LED_FUN(n)\t\t\t\t\\\n+\t{\t\t\t\t\t\t\\\n+\t\t.name = #n,\t\t\t\t\\\n+\t\t.groups = n##_groups,\t\t\t\\\n+\t\t.num_groups = ARRAY_SIZE(n##_groups),\t\\\n+\t\t.reg = BCM63268_LEDCTRL,\t\t\\\n+\t}\n+\n+#define BCM63268_MODE_FUN(n)\t\t\t\t\\\n+\t{\t\t\t\t\t\t\\\n+\t\t.name = #n,\t\t\t\t\\\n+\t\t.groups = n##_groups,\t\t\t\\\n+\t\t.num_groups = ARRAY_SIZE(n##_groups),\t\\\n+\t\t.reg = BCM63268_MODE,\t\t\t\\\n+\t}\n+\n+#define BCM63268_CTRL_FUN(n)\t\t\t\t\\\n+\t{\t\t\t\t\t\t\\\n+\t\t.name = #n,\t\t\t\t\\\n+\t\t.groups = n##_groups,\t\t\t\\\n+\t\t.num_groups = ARRAY_SIZE(n##_groups),\t\\\n+\t\t.reg = BCM63268_CTRL,\t\t\t\\\n+\t}\n+\n+#define BCM63268_BASEMODE_FUN(n, val)\t\t\t\\\n+\t{\t\t\t\t\t\t\\\n+\t\t.name = #n,\t\t\t\t\\\n+\t\t.groups = n##_groups,\t\t\t\\\n+\t\t.num_groups = ARRAY_SIZE(n##_groups),\t\\\n+\t\t.reg = BCM63268_BASEMODE,\t\t\\\n+\t\t.mask = val,\t\t\t\t\\\n+\t}\n+\n+static const struct bcm63268_function bcm63268_funcs[] = {\n+\tBCM63268_LED_FUN(led),\n+\tBCM63268_MODE_FUN(serial_led_clk),\n+\tBCM63268_MODE_FUN(serial_led_data),\n+\tBCM63268_MODE_FUN(hsspi_cs6),\n+\tBCM63268_MODE_FUN(hsspi_cs7),\n+\tBCM63268_MODE_FUN(uart1_scts),\n+\tBCM63268_MODE_FUN(uart1_srts),\n+\tBCM63268_MODE_FUN(uart1_sdin),\n+\tBCM63268_MODE_FUN(uart1_sdout),\n+\tBCM63268_MODE_FUN(ntr_pulse_in),\n+\tBCM63268_MODE_FUN(dsl_ntr_pulse_out),\n+\tBCM63268_MODE_FUN(hsspi_cs4),\n+\tBCM63268_MODE_FUN(hsspi_cs5),\n+\tBCM63268_MODE_FUN(adsl_spi_miso),\n+\tBCM63268_MODE_FUN(adsl_spi_mosi),\n+\tBCM63268_MODE_FUN(vreg_clk),\n+\tBCM63268_MODE_FUN(pcie_clkreq_b),\n+\tBCM63268_MODE_FUN(switch_led_clk),\n+\tBCM63268_MODE_FUN(switch_led_data),\n+\tBCM63268_CTRL_FUN(wifi),\n+\tBCM63268_BASEMODE_FUN(nand, BCM63268_BASEMODE_NAND),\n+\tBCM63268_BASEMODE_FUN(dectpd, BCM63268_BASEMODE_DECTPD),\n+\tBCM63268_BASEMODE_FUN(vdsl_phy_override_0,\n+\t\t\t      BCM63268_BASEMODE_VDSL_PHY_0),\n+\tBCM63268_BASEMODE_FUN(vdsl_phy_override_1,\n+\t\t\t      BCM63268_BASEMODE_VDSL_PHY_1),\n+\tBCM63268_BASEMODE_FUN(vdsl_phy_override_2,\n+\t\t\t      BCM63268_BASEMODE_VDSL_PHY_2),\n+\tBCM63268_BASEMODE_FUN(vdsl_phy_override_3,\n+\t\t\t      BCM63268_BASEMODE_VDSL_PHY_3),\n+};\n+\n+static int bcm63268_pinctrl_get_group_count(struct pinctrl_dev *pctldev)\n+{\n+\treturn ARRAY_SIZE(bcm63268_groups);\n+}\n+\n+static const char *bcm63268_pinctrl_get_group_name(struct pinctrl_dev *pctldev,\n+\t\t\t\t\t\t   unsigned group)\n+{\n+\treturn bcm63268_groups[group].name;\n+}\n+\n+static int bcm63268_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,\n+\t\t\t\t\t   unsigned group,\n+\t\t\t\t\t   const unsigned **pins,\n+\t\t\t\t\t   unsigned *num_pins)\n+{\n+\t*pins = bcm63268_groups[group].pins;\n+\t*num_pins = bcm63268_groups[group].num_pins;\n+\n+\treturn 0;\n+}\n+\n+static int bcm63268_pinctrl_get_func_count(struct pinctrl_dev *pctldev)\n+{\n+\treturn ARRAY_SIZE(bcm63268_funcs);\n+}\n+\n+static const char *bcm63268_pinctrl_get_func_name(struct pinctrl_dev *pctldev,\n+\t\t\t\t\t\t  unsigned selector)\n+{\n+\treturn bcm63268_funcs[selector].name;\n+}\n+\n+static int bcm63268_pinctrl_get_groups(struct pinctrl_dev *pctldev,\n+\t\t\t\t       unsigned selector,\n+\t\t\t\t       const char * const **groups,\n+\t\t\t\t       unsigned * const num_groups)\n+{\n+\t*groups = bcm63268_funcs[selector].groups;\n+\t*num_groups = bcm63268_funcs[selector].num_groups;\n+\n+\treturn 0;\n+}\n+\n+static void bcm63268_set_gpio(struct bcm63xx_pinctrl *pc, unsigned pin)\n+{\n+\tconst struct pinctrl_pin_desc *desc = &bcm63268_pins[pin];\n+\tunsigned int basemode = (unsigned long) desc->drv_data;\n+\tunsigned int mask = BIT(bcm63xx_bank_pin(pin));\n+\n+\tif (basemode)\n+\t\tregmap_update_bits(pc->regs, BCM63268_BASEMODE_REG, basemode,\n+\t\t\t\t   0);\n+\n+\tif (pin < BCM63XX_BANK_GPIOS) {\n+\t\t/* base mode: 0 => gpio, 1 => mux function */\n+\t\tregmap_update_bits(pc->regs, BCM63268_MODE_REG, mask, 0);\n+\n+\t\t/* pins 0-23 might be muxed to led */\n+\t\tif (pin < BCM63268_NUM_LEDS)\n+\t\t\tregmap_update_bits(pc->regs, BCM63268_LED_REG, mask,\n+\t\t\t\t\t   0);\n+\t} else if (pin < BCM63268_NUM_GPIOS) {\n+\t\t/* ctrl reg: 0 => wifi function, 1 => gpio */\n+\t\tregmap_update_bits(pc->regs, BCM63268_CTRL_REG, mask, mask);\n+\t}\n+}\n+\n+static int bcm63268_pinctrl_set_mux(struct pinctrl_dev *pctldev,\n+\t\t\t\t    unsigned selector, unsigned group)\n+{\n+\tstruct bcm63xx_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);\n+\tconst struct bcm63268_pingroup *pg = &bcm63268_groups[group];\n+\tconst struct bcm63268_function *f = &bcm63268_funcs[selector];\n+\tunsigned i;\n+\tunsigned int reg;\n+\tunsigned int val, mask;\n+\n+\tfor (i = 0; i < pg->num_pins; i++)\n+\t\tbcm63268_set_gpio(pc, pg->pins[i]);\n+\n+\tswitch (f->reg) {\n+\tcase BCM63268_LEDCTRL:\n+\t\treg = BCM63268_LED_REG;\n+\t\tmask = BIT(pg->pins[0]);\n+\t\tval = BIT(pg->pins[0]);\n+\t\tbreak;\n+\tcase BCM63268_MODE:\n+\t\treg = BCM63268_MODE_REG;\n+\t\tmask = BIT(pg->pins[0]);\n+\t\tval = BIT(pg->pins[0]);\n+\t\tbreak;\n+\tcase BCM63268_CTRL:\n+\t\treg = BCM63268_CTRL_REG;\n+\t\tmask = BIT(pg->pins[0]);\n+\t\tval = 0;\n+\t\tbreak;\n+\tcase BCM63268_BASEMODE:\n+\t\treg = BCM63268_BASEMODE_REG;\n+\t\tmask = f->mask;\n+\t\tval = f->mask;\n+\t\tbreak;\n+\tdefault:\n+\t\tWARN_ON(1);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tregmap_update_bits(pc->regs, reg, mask, val);\n+\n+\treturn 0;\n+}\n+\n+static int bcm63268_gpio_request_enable(struct pinctrl_dev *pctldev,\n+\t\t\t\t\tstruct pinctrl_gpio_range *range,\n+\t\t\t\t\tunsigned offset)\n+{\n+\tstruct bcm63xx_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);\n+\n+\t/* disable all functions using this pin */\n+\tbcm63268_set_gpio(pc, offset);\n+\n+\treturn 0;\n+}\n+\n+static struct pinctrl_ops bcm63268_pctl_ops = {\n+\t.dt_free_map = pinctrl_utils_free_map,\n+\t.dt_node_to_map = pinconf_generic_dt_node_to_map_pin,\n+\t.get_group_name = bcm63268_pinctrl_get_group_name,\n+\t.get_group_pins = bcm63268_pinctrl_get_group_pins,\n+\t.get_groups_count = bcm63268_pinctrl_get_group_count,\n+};\n+\n+static struct pinmux_ops bcm63268_pmx_ops = {\n+\t.get_function_groups = bcm63268_pinctrl_get_groups,\n+\t.get_function_name = bcm63268_pinctrl_get_func_name,\n+\t.get_functions_count = bcm63268_pinctrl_get_func_count,\n+\t.gpio_request_enable = bcm63268_gpio_request_enable,\n+\t.set_mux = bcm63268_pinctrl_set_mux,\n+\t.strict = true,\n+};\n+\n+static const struct bcm63xx_pinctrl_soc bcm63268_soc = {\n+\t.ngpios = BCM63268_NUM_GPIOS,\n+\t.npins = ARRAY_SIZE(bcm63268_pins),\n+\t.pctl_ops = &bcm63268_pctl_ops,\n+\t.pins = bcm63268_pins,\n+\t.pmx_ops = &bcm63268_pmx_ops,\n+};\n+\n+static int bcm63268_pinctrl_probe(struct platform_device *pdev)\n+{\n+\treturn bcm63xx_pinctrl_probe(pdev, &bcm63268_soc, NULL);\n+}\n+\n+static const struct of_device_id bcm63268_pinctrl_match[] = {\n+\t{ .compatible = \"brcm,bcm63268-pinctrl\", },\n+\t{ /* sentinel */ }\n+};\n+\n+static struct platform_driver bcm63268_pinctrl_driver = {\n+\t.probe = bcm63268_pinctrl_probe,\n+\t.driver = {\n+\t\t.name = \"bcm63268-pinctrl\",\n+\t\t.of_match_table = bcm63268_pinctrl_match,\n+\t},\n+};\n+\n+builtin_platform_driver(bcm63268_pinctrl_driver);\n"
  },
  {
    "path": "target/linux/bmips/patches-5.10/071-v5.13-dt-bindings-add-BCM6318-pincontroller-binding-docume.patch",
    "content": "From b2f215141b985d5d39ed16fe7e2089d5aa162302 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com>\nDate: Wed, 24 Mar 2021 09:19:21 +0100\nSubject: [PATCH 20/22] dt-bindings: add BCM6318 pincontroller binding\n documentation\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nAdd binding documentation for the pincontrol core found in BCM6318 SoCs.\n\nCo-developed-by: Jonas Gorski <jonas.gorski@gmail.com>\nSigned-off-by: Jonas Gorski <jonas.gorski@gmail.com>\nSigned-off-by: Álvaro Fernández Rojas <noltari@gmail.com>\nReviewed-by: Rob Herring <robh@kernel.org>\nLink: https://lore.kernel.org/r/20210324081923.20379-21-noltari@gmail.com\nSigned-off-by: Linus Walleij <linus.walleij@linaro.org>\n---\n .../pinctrl/brcm,bcm6318-pinctrl.yaml         | 143 ++++++++++++++++++\n 1 file changed, 143 insertions(+)\n create mode 100644 Documentation/devicetree/bindings/pinctrl/brcm,bcm6318-pinctrl.yaml\n\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/pinctrl/brcm,bcm6318-pinctrl.yaml\n@@ -0,0 +1,143 @@\n+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause\n+%YAML 1.2\n+---\n+$id: http://devicetree.org/schemas/pinctrl/brcm,bcm6318-pinctrl.yaml#\n+$schema: http://devicetree.org/meta-schemas/core.yaml#\n+\n+title: Broadcom BCM6318 pin controller\n+\n+maintainers:\n+  - Álvaro Fernández Rojas <noltari@gmail.com>\n+  - Jonas Gorski <jonas.gorski@gmail.com>\n+\n+description:\n+  Bindings for Broadcom's BCM6318 memory-mapped pin controller.\n+\n+properties:\n+  compatible:\n+    const: brcm,bcm6318-pinctrl\n+\n+  reg:\n+    maxItems: 2\n+\n+patternProperties:\n+  '-pins$':\n+    type: object\n+    $ref: pinmux-node.yaml#\n+\n+    properties:\n+      function:\n+        enum: [ ephy0_spd_led, ephy1_spd_led, ephy2_spd_led, ephy3_spd_led,\n+                ephy0_act_led, ephy1_act_led, ephy2_act_led, ephy3_act_led,\n+                serial_led_data, serial_led_clk, inet_act_led, inet_fail_led,\n+                dsl_led, post_fail_led, wlan_wps_led, usb_pwron,\n+                usb_device_led, usb_active ]\n+\n+      pins:\n+        enum: [ gpio0, gpio1, gpio2, gpio3, gpio4, gpio5, gpio6, gpio7,\n+                gpio8, gpio9, gpio10, gpio11, gpio12, gpio13, gpio40 ]\n+\n+required:\n+  - compatible\n+  - reg\n+\n+additionalProperties: false\n+\n+examples:\n+  - |\n+    pinctrl@18 {\n+      compatible = \"brcm,bcm6318-pinctrl\";\n+      reg = <0x18 0x10>, <0x54 0x18>;\n+\n+      pinctrl_ephy0_spd_led: ephy0_spd_led-pins {\n+        function = \"ephy0_spd_led\";\n+        pins = \"gpio0\";\n+      };\n+\n+      pinctrl_ephy1_spd_led: ephy1_spd_led-pins {\n+        function = \"ephy1_spd_led\";\n+        pins = \"gpio1\";\n+      };\n+\n+      pinctrl_ephy2_spd_led: ephy2_spd_led-pins {\n+        function = \"ephy2_spd_led\";\n+        pins = \"gpio2\";\n+      };\n+\n+      pinctrl_ephy3_spd_led: ephy3_spd_led-pins {\n+        function = \"ephy3_spd_led\";\n+        pins = \"gpio3\";\n+      };\n+\n+      pinctrl_ephy0_act_led: ephy0_act_led-pins {\n+        function = \"ephy0_act_led\";\n+        pins = \"gpio4\";\n+      };\n+\n+      pinctrl_ephy1_act_led: ephy1_act_led-pins {\n+        function = \"ephy1_act_led\";\n+        pins = \"gpio5\";\n+      };\n+\n+      pinctrl_ephy2_act_led: ephy2_act_led-pins {\n+        function = \"ephy2_act_led\";\n+        pins = \"gpio6\";\n+      };\n+\n+      pinctrl_ephy3_act_led: ephy3_act_led-pins {\n+        function = \"ephy3_act_led\";\n+        pins = \"gpio7\";\n+      };\n+\n+      pinctrl_serial_led: serial_led-pins {\n+        pinctrl_serial_led_data: serial_led_data-pins {\n+          function = \"serial_led_data\";\n+          pins = \"gpio6\";\n+        };\n+\n+        pinctrl_serial_led_clk: serial_led_clk-pins {\n+          function = \"serial_led_clk\";\n+          pins = \"gpio7\";\n+        };\n+      };\n+\n+      pinctrl_inet_act_led: inet_act_led-pins {\n+        function = \"inet_act_led\";\n+        pins = \"gpio8\";\n+      };\n+\n+      pinctrl_inet_fail_led: inet_fail_led-pins {\n+        function = \"inet_fail_led\";\n+        pins = \"gpio9\";\n+      };\n+\n+      pinctrl_dsl_led: dsl_led-pins {\n+        function = \"dsl_led\";\n+        pins = \"gpio10\";\n+      };\n+\n+      pinctrl_post_fail_led: post_fail_led-pins {\n+        function = \"post_fail_led\";\n+        pins = \"gpio11\";\n+      };\n+\n+      pinctrl_wlan_wps_led: wlan_wps_led-pins {\n+        function = \"wlan_wps_led\";\n+        pins = \"gpio12\";\n+      };\n+\n+      pinctrl_usb_pwron: usb_pwron-pins {\n+        function = \"usb_pwron\";\n+        pins = \"gpio13\";\n+      };\n+\n+      pinctrl_usb_device_led: usb_device_led-pins {\n+        function = \"usb_device_led\";\n+        pins = \"gpio13\";\n+      };\n+\n+      pinctrl_usb_active: usb_active-pins {\n+        function = \"usb_active\";\n+        pins = \"gpio40\";\n+      };\n+    };\n"
  },
  {
    "path": "target/linux/bmips/patches-5.10/072-v5.13-dt-bindings-add-BCM6318-GPIO-sysctl-binding-document.patch",
    "content": "From b6d46b9454742a25f9d923be072869e40b2ecebb Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com>\nDate: Wed, 24 Mar 2021 09:19:22 +0100\nSubject: [PATCH 21/22] dt-bindings: add BCM6318 GPIO sysctl binding\n documentation\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nAdd binding documentation for the GPIO sysctl found in BCM6318 SoCs.\n\nSigned-off-by: Álvaro Fernández Rojas <noltari@gmail.com>\nReviewed-by: Rob Herring <robh@kernel.org>\nLink: https://lore.kernel.org/r/20210324081923.20379-22-noltari@gmail.com\nSigned-off-by: Linus Walleij <linus.walleij@linaro.org>\n---\n .../mfd/brcm,bcm6318-gpio-sysctl.yaml         | 177 ++++++++++++++++++\n 1 file changed, 177 insertions(+)\n create mode 100644 Documentation/devicetree/bindings/mfd/brcm,bcm6318-gpio-sysctl.yaml\n\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/mfd/brcm,bcm6318-gpio-sysctl.yaml\n@@ -0,0 +1,177 @@\n+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)\n+%YAML 1.2\n+---\n+$id: http://devicetree.org/schemas/mfd/brcm,bcm6318-gpio-sysctl.yaml#\n+$schema: http://devicetree.org/meta-schemas/core.yaml#\n+\n+title: Broadcom BCM6318 GPIO System Controller Device Tree Bindings\n+\n+maintainers:\n+  - Álvaro Fernández Rojas <noltari@gmail.com>\n+  - Jonas Gorski <jonas.gorski@gmail.com>\n+\n+description:\n+  Broadcom BCM6318 SoC GPIO system controller which provides a register map\n+  for controlling the GPIO and pins of the SoC.\n+\n+properties:\n+  \"#address-cells\": true\n+\n+  \"#size-cells\": true\n+\n+  compatible:\n+    items:\n+      - const: brcm,bcm6318-gpio-sysctl\n+      - const: syscon\n+      - const: simple-mfd\n+\n+  ranges:\n+    maxItems: 1\n+\n+  reg:\n+    maxItems: 1\n+\n+patternProperties:\n+  \"^gpio@[0-9a-f]+$\":\n+    # Child node\n+    type: object\n+    $ref: \"../gpio/brcm,bcm6345-gpio.yaml\"\n+    description:\n+      GPIO controller for the SoC GPIOs. This child node definition\n+      should follow the bindings specified in\n+      Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.yaml.\n+\n+  \"^pinctrl@[0-9a-f]+$\":\n+    # Child node\n+    type: object\n+    $ref: \"../pinctrl/brcm,bcm6318-pinctrl.yaml\"\n+    description:\n+      Pin controller for the SoC pins. This child node definition\n+      should follow the bindings specified in\n+      Documentation/devicetree/bindings/pinctrl/brcm,bcm6318-pinctrl.yaml.\n+\n+required:\n+  - \"#address-cells\"\n+  - compatible\n+  - ranges\n+  - reg\n+  - \"#size-cells\"\n+\n+additionalProperties: false\n+\n+examples:\n+  - |\n+    syscon@10000080 {\n+      #address-cells = <1>;\n+      #size-cells = <1>;\n+      compatible = \"brcm,bcm6318-gpio-sysctl\", \"syscon\", \"simple-mfd\";\n+      reg = <0x10000080 0x80>;\n+      ranges = <0 0x10000080 0x80>;\n+\n+      gpio@0 {\n+        compatible = \"brcm,bcm6318-gpio\";\n+        reg-names = \"dirout\", \"dat\";\n+        reg = <0x0 0x8>, <0x8 0x8>;\n+\n+        gpio-controller;\n+        gpio-ranges = <&pinctrl 0 0 50>;\n+        #gpio-cells = <2>;\n+      };\n+\n+      pinctrl: pinctrl@10 {\n+        compatible = \"brcm,bcm6318-pinctrl\";\n+        reg = <0x18 0x10>, <0x54 0x18>;\n+\n+        pinctrl_ephy0_spd_led: ephy0_spd_led-pins {\n+          function = \"ephy0_spd_led\";\n+          pins = \"gpio0\";\n+        };\n+\n+        pinctrl_ephy1_spd_led: ephy1_spd_led-pins {\n+          function = \"ephy1_spd_led\";\n+          pins = \"gpio1\";\n+        };\n+\n+        pinctrl_ephy2_spd_led: ephy2_spd_led-pins {\n+          function = \"ephy2_spd_led\";\n+          pins = \"gpio2\";\n+        };\n+\n+        pinctrl_ephy3_spd_led: ephy3_spd_led-pins {\n+          function = \"ephy3_spd_led\";\n+          pins = \"gpio3\";\n+        };\n+\n+        pinctrl_ephy0_act_led: ephy0_act_led-pins {\n+          function = \"ephy0_act_led\";\n+          pins = \"gpio4\";\n+        };\n+\n+        pinctrl_ephy1_act_led: ephy1_act_led-pins {\n+          function = \"ephy1_act_led\";\n+          pins = \"gpio5\";\n+        };\n+\n+        pinctrl_ephy2_act_led: ephy2_act_led-pins {\n+          function = \"ephy2_act_led\";\n+          pins = \"gpio6\";\n+        };\n+\n+        pinctrl_ephy3_act_led: ephy3_act_led-pins {\n+          function = \"ephy3_act_led\";\n+          pins = \"gpio7\";\n+        };\n+\n+        pinctrl_serial_led: serial_led-pins {\n+          pinctrl_serial_led_data: serial_led_data-pins {\n+            function = \"serial_led_data\";\n+            pins = \"gpio6\";\n+          };\n+\n+          pinctrl_serial_led_clk: serial_led_clk-pins {\n+            function = \"serial_led_clk\";\n+            pins = \"gpio7\";\n+          };\n+        };\n+\n+        pinctrl_inet_act_led: inet_act_led-pins {\n+          function = \"inet_act_led\";\n+          pins = \"gpio8\";\n+        };\n+\n+        pinctrl_inet_fail_led: inet_fail_led-pins {\n+          function = \"inet_fail_led\";\n+          pins = \"gpio9\";\n+        };\n+\n+        pinctrl_dsl_led: dsl_led-pins {\n+          function = \"dsl_led\";\n+          pins = \"gpio10\";\n+        };\n+\n+        pinctrl_post_fail_led: post_fail_led-pins {\n+          function = \"post_fail_led\";\n+          pins = \"gpio11\";\n+        };\n+\n+        pinctrl_wlan_wps_led: wlan_wps_led-pins {\n+          function = \"wlan_wps_led\";\n+          pins = \"gpio12\";\n+        };\n+\n+        pinctrl_usb_pwron: usb_pwron-pins {\n+          function = \"usb_pwron\";\n+          pins = \"gpio13\";\n+        };\n+\n+        pinctrl_usb_device_led: usb_device_led-pins {\n+          function = \"usb_device_led\";\n+          pins = \"gpio13\";\n+        };\n+\n+        pinctrl_usb_active: usb_active-pins {\n+          function = \"usb_active\";\n+          pins = \"gpio40\";\n+        };\n+      };\n+    };\n"
  },
  {
    "path": "target/linux/bmips/patches-5.10/073-v5.13-pinctrl-add-a-pincontrol-driver-for-BCM6318.patch",
    "content": "From d28039fccf948a407de69106465caa465b1dcf32 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com>\nDate: Wed, 24 Mar 2021 09:19:23 +0100\nSubject: [PATCH 22/22] pinctrl: add a pincontrol driver for BCM6318\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nAdd a pincontrol driver for BCM6318. BCM6318 allows muxing most GPIOs\nto different functions. BCM6318 is similar to BCM6328 with the addition\nof a pad register, and the GPIO meaning of the mux register changes\nbased on the GPIO number.\n\nCo-developed-by: Jonas Gorski <jonas.gorski@gmail.com>\nSigned-off-by: Jonas Gorski <jonas.gorski@gmail.com>\nSigned-off-by: Álvaro Fernández Rojas <noltari@gmail.com>\nLink: https://lore.kernel.org/r/20210324081923.20379-23-noltari@gmail.com\nSigned-off-by: Linus Walleij <linus.walleij@linaro.org>\n---\n drivers/pinctrl/bcm/Kconfig           |   8 +\n drivers/pinctrl/bcm/Makefile          |   1 +\n drivers/pinctrl/bcm/pinctrl-bcm6318.c | 498 ++++++++++++++++++++++++++\n 3 files changed, 507 insertions(+)\n create mode 100644 drivers/pinctrl/bcm/pinctrl-bcm6318.c\n\n--- a/drivers/pinctrl/bcm/Kconfig\n+++ b/drivers/pinctrl/bcm/Kconfig\n@@ -36,6 +36,14 @@ config PINCTRL_BCM63XX\n \tselect PINCONF\n \tselect PINMUX\n \n+config PINCTRL_BCM6318\n+\tbool \"Broadcom BCM6318 GPIO driver\"\n+\tdepends on (BMIPS_GENERIC || COMPILE_TEST)\n+\tselect PINCTRL_BCM63XX\n+\tdefault BMIPS_GENERIC\n+\thelp\n+\t   Say Y here to enable the Broadcom BCM6318 GPIO driver.\n+\n config PINCTRL_BCM6328\n \tbool \"Broadcom BCM6328 GPIO driver\"\n \tdepends on (BMIPS_GENERIC || COMPILE_TEST)\n--- a/drivers/pinctrl/bcm/Makefile\n+++ b/drivers/pinctrl/bcm/Makefile\n@@ -4,6 +4,7 @@\n obj-$(CONFIG_PINCTRL_BCM281XX)\t\t+= pinctrl-bcm281xx.o\n obj-$(CONFIG_PINCTRL_BCM2835)\t\t+= pinctrl-bcm2835.o\n obj-$(CONFIG_PINCTRL_BCM63XX)\t\t+= pinctrl-bcm63xx.o\n+obj-$(CONFIG_PINCTRL_BCM6318)\t\t+= pinctrl-bcm6318.o\n obj-$(CONFIG_PINCTRL_BCM6328)\t\t+= pinctrl-bcm6328.o\n obj-$(CONFIG_PINCTRL_BCM6358)\t\t+= pinctrl-bcm6358.o\n obj-$(CONFIG_PINCTRL_BCM6362)\t\t+= pinctrl-bcm6362.o\n--- /dev/null\n+++ b/drivers/pinctrl/bcm/pinctrl-bcm6318.c\n@@ -0,0 +1,498 @@\n+// SPDX-License-Identifier: GPL-2.0+\n+/*\n+ * Driver for BCM6318 GPIO unit (pinctrl + GPIO)\n+ *\n+ * Copyright (C) 2021 Álvaro Fernández Rojas <noltari@gmail.com>\n+ * Copyright (C) 2016 Jonas Gorski <jonas.gorski@gmail.com>\n+ */\n+\n+#include <linux/bits.h>\n+#include <linux/gpio/driver.h>\n+#include <linux/kernel.h>\n+#include <linux/of.h>\n+#include <linux/pinctrl/pinmux.h>\n+#include <linux/platform_device.h>\n+#include <linux/regmap.h>\n+\n+#include \"../pinctrl-utils.h\"\n+\n+#include \"pinctrl-bcm63xx.h\"\n+\n+#define BCM6318_NUM_GPIOS\t50\n+#define BCM6318_NUM_MUX\t\t48\n+\n+#define BCM6318_MODE_REG\t0x18\n+#define BCM6318_MUX_REG\t\t0x1c\n+#define  BCM6328_MUX_MASK\tGENMASK(1, 0)\n+#define BCM6318_PAD_REG\t\t0x54\n+#define  BCM6328_PAD_MASK\tGENMASK(3, 0)\n+\n+struct bcm6318_pingroup {\n+\tconst char *name;\n+\tconst unsigned * const pins;\n+\tconst unsigned num_pins;\n+};\n+\n+struct bcm6318_function {\n+\tconst char *name;\n+\tconst char * const *groups;\n+\tconst unsigned num_groups;\n+\n+\tunsigned mode_val:1;\n+\tunsigned mux_val:2;\n+};\n+\n+static const struct pinctrl_pin_desc bcm6318_pins[] = {\n+\tPINCTRL_PIN(0, \"gpio0\"),\n+\tPINCTRL_PIN(1, \"gpio1\"),\n+\tPINCTRL_PIN(2, \"gpio2\"),\n+\tPINCTRL_PIN(3, \"gpio3\"),\n+\tPINCTRL_PIN(4, \"gpio4\"),\n+\tPINCTRL_PIN(5, \"gpio5\"),\n+\tPINCTRL_PIN(6, \"gpio6\"),\n+\tPINCTRL_PIN(7, \"gpio7\"),\n+\tPINCTRL_PIN(8, \"gpio8\"),\n+\tPINCTRL_PIN(9, \"gpio9\"),\n+\tPINCTRL_PIN(10, \"gpio10\"),\n+\tPINCTRL_PIN(11, \"gpio11\"),\n+\tPINCTRL_PIN(12, \"gpio12\"),\n+\tPINCTRL_PIN(13, \"gpio13\"),\n+\tPINCTRL_PIN(14, \"gpio14\"),\n+\tPINCTRL_PIN(15, \"gpio15\"),\n+\tPINCTRL_PIN(16, \"gpio16\"),\n+\tPINCTRL_PIN(17, \"gpio17\"),\n+\tPINCTRL_PIN(18, \"gpio18\"),\n+\tPINCTRL_PIN(19, \"gpio19\"),\n+\tPINCTRL_PIN(20, \"gpio20\"),\n+\tPINCTRL_PIN(21, \"gpio21\"),\n+\tPINCTRL_PIN(22, \"gpio22\"),\n+\tPINCTRL_PIN(23, \"gpio23\"),\n+\tPINCTRL_PIN(24, \"gpio24\"),\n+\tPINCTRL_PIN(25, \"gpio25\"),\n+\tPINCTRL_PIN(26, \"gpio26\"),\n+\tPINCTRL_PIN(27, \"gpio27\"),\n+\tPINCTRL_PIN(28, \"gpio28\"),\n+\tPINCTRL_PIN(29, \"gpio29\"),\n+\tPINCTRL_PIN(30, \"gpio30\"),\n+\tPINCTRL_PIN(31, \"gpio31\"),\n+\tPINCTRL_PIN(32, \"gpio32\"),\n+\tPINCTRL_PIN(33, \"gpio33\"),\n+\tPINCTRL_PIN(34, \"gpio34\"),\n+\tPINCTRL_PIN(35, \"gpio35\"),\n+\tPINCTRL_PIN(36, \"gpio36\"),\n+\tPINCTRL_PIN(37, \"gpio37\"),\n+\tPINCTRL_PIN(38, \"gpio38\"),\n+\tPINCTRL_PIN(39, \"gpio39\"),\n+\tPINCTRL_PIN(40, \"gpio40\"),\n+\tPINCTRL_PIN(41, \"gpio41\"),\n+\tPINCTRL_PIN(42, \"gpio42\"),\n+\tPINCTRL_PIN(43, \"gpio43\"),\n+\tPINCTRL_PIN(44, \"gpio44\"),\n+\tPINCTRL_PIN(45, \"gpio45\"),\n+\tPINCTRL_PIN(46, \"gpio46\"),\n+\tPINCTRL_PIN(47, \"gpio47\"),\n+\tPINCTRL_PIN(48, \"gpio48\"),\n+\tPINCTRL_PIN(49, \"gpio49\"),\n+};\n+\n+static unsigned gpio0_pins[] = { 0 };\n+static unsigned gpio1_pins[] = { 1 };\n+static unsigned gpio2_pins[] = { 2 };\n+static unsigned gpio3_pins[] = { 3 };\n+static unsigned gpio4_pins[] = { 4 };\n+static unsigned gpio5_pins[] = { 5 };\n+static unsigned gpio6_pins[] = { 6 };\n+static unsigned gpio7_pins[] = { 7 };\n+static unsigned gpio8_pins[] = { 8 };\n+static unsigned gpio9_pins[] = { 9 };\n+static unsigned gpio10_pins[] = { 10 };\n+static unsigned gpio11_pins[] = { 11 };\n+static unsigned gpio12_pins[] = { 12 };\n+static unsigned gpio13_pins[] = { 13 };\n+static unsigned gpio14_pins[] = { 14 };\n+static unsigned gpio15_pins[] = { 15 };\n+static unsigned gpio16_pins[] = { 16 };\n+static unsigned gpio17_pins[] = { 17 };\n+static unsigned gpio18_pins[] = { 18 };\n+static unsigned gpio19_pins[] = { 19 };\n+static unsigned gpio20_pins[] = { 20 };\n+static unsigned gpio21_pins[] = { 21 };\n+static unsigned gpio22_pins[] = { 22 };\n+static unsigned gpio23_pins[] = { 23 };\n+static unsigned gpio24_pins[] = { 24 };\n+static unsigned gpio25_pins[] = { 25 };\n+static unsigned gpio26_pins[] = { 26 };\n+static unsigned gpio27_pins[] = { 27 };\n+static unsigned gpio28_pins[] = { 28 };\n+static unsigned gpio29_pins[] = { 29 };\n+static unsigned gpio30_pins[] = { 30 };\n+static unsigned gpio31_pins[] = { 31 };\n+static unsigned gpio32_pins[] = { 32 };\n+static unsigned gpio33_pins[] = { 33 };\n+static unsigned gpio34_pins[] = { 34 };\n+static unsigned gpio35_pins[] = { 35 };\n+static unsigned gpio36_pins[] = { 36 };\n+static unsigned gpio37_pins[] = { 37 };\n+static unsigned gpio38_pins[] = { 38 };\n+static unsigned gpio39_pins[] = { 39 };\n+static unsigned gpio40_pins[] = { 40 };\n+static unsigned gpio41_pins[] = { 41 };\n+static unsigned gpio42_pins[] = { 42 };\n+static unsigned gpio43_pins[] = { 43 };\n+static unsigned gpio44_pins[] = { 44 };\n+static unsigned gpio45_pins[] = { 45 };\n+static unsigned gpio46_pins[] = { 46 };\n+static unsigned gpio47_pins[] = { 47 };\n+static unsigned gpio48_pins[] = { 48 };\n+static unsigned gpio49_pins[] = { 49 };\n+\n+#define BCM6318_GROUP(n)\t\t\t\t\t\\\n+\t{\t\t\t\t\t\t\t\\\n+\t\t.name = #n,\t\t\t\t\t\\\n+\t\t.pins = n##_pins,\t\t\t\t\\\n+\t\t.num_pins = ARRAY_SIZE(n##_pins),\t\t\\\n+\t}\n+\n+static struct bcm6318_pingroup bcm6318_groups[] = {\n+\tBCM6318_GROUP(gpio0),\n+\tBCM6318_GROUP(gpio1),\n+\tBCM6318_GROUP(gpio2),\n+\tBCM6318_GROUP(gpio3),\n+\tBCM6318_GROUP(gpio4),\n+\tBCM6318_GROUP(gpio5),\n+\tBCM6318_GROUP(gpio6),\n+\tBCM6318_GROUP(gpio7),\n+\tBCM6318_GROUP(gpio8),\n+\tBCM6318_GROUP(gpio9),\n+\tBCM6318_GROUP(gpio10),\n+\tBCM6318_GROUP(gpio11),\n+\tBCM6318_GROUP(gpio12),\n+\tBCM6318_GROUP(gpio13),\n+\tBCM6318_GROUP(gpio14),\n+\tBCM6318_GROUP(gpio15),\n+\tBCM6318_GROUP(gpio16),\n+\tBCM6318_GROUP(gpio17),\n+\tBCM6318_GROUP(gpio18),\n+\tBCM6318_GROUP(gpio19),\n+\tBCM6318_GROUP(gpio20),\n+\tBCM6318_GROUP(gpio21),\n+\tBCM6318_GROUP(gpio22),\n+\tBCM6318_GROUP(gpio23),\n+\tBCM6318_GROUP(gpio24),\n+\tBCM6318_GROUP(gpio25),\n+\tBCM6318_GROUP(gpio26),\n+\tBCM6318_GROUP(gpio27),\n+\tBCM6318_GROUP(gpio28),\n+\tBCM6318_GROUP(gpio29),\n+\tBCM6318_GROUP(gpio30),\n+\tBCM6318_GROUP(gpio31),\n+\tBCM6318_GROUP(gpio32),\n+\tBCM6318_GROUP(gpio33),\n+\tBCM6318_GROUP(gpio34),\n+\tBCM6318_GROUP(gpio35),\n+\tBCM6318_GROUP(gpio36),\n+\tBCM6318_GROUP(gpio37),\n+\tBCM6318_GROUP(gpio38),\n+\tBCM6318_GROUP(gpio39),\n+\tBCM6318_GROUP(gpio40),\n+\tBCM6318_GROUP(gpio41),\n+\tBCM6318_GROUP(gpio42),\n+\tBCM6318_GROUP(gpio43),\n+\tBCM6318_GROUP(gpio44),\n+\tBCM6318_GROUP(gpio45),\n+\tBCM6318_GROUP(gpio46),\n+\tBCM6318_GROUP(gpio47),\n+\tBCM6318_GROUP(gpio48),\n+\tBCM6318_GROUP(gpio49),\n+};\n+\n+/* GPIO_MODE */\n+static const char * const led_groups[] = {\n+\t\"gpio0\",\n+\t\"gpio1\",\n+\t\"gpio2\",\n+\t\"gpio3\",\n+\t\"gpio4\",\n+\t\"gpio5\",\n+\t\"gpio6\",\n+\t\"gpio7\",\n+\t\"gpio8\",\n+\t\"gpio9\",\n+\t\"gpio10\",\n+\t\"gpio11\",\n+\t\"gpio12\",\n+\t\"gpio13\",\n+\t\"gpio14\",\n+\t\"gpio15\",\n+\t\"gpio16\",\n+\t\"gpio17\",\n+\t\"gpio18\",\n+\t\"gpio19\",\n+\t\"gpio20\",\n+\t\"gpio21\",\n+\t\"gpio22\",\n+\t\"gpio23\",\n+};\n+\n+/* PINMUX_SEL */\n+static const char * const ephy0_spd_led_groups[] = {\n+\t\"gpio0\",\n+};\n+\n+static const char * const ephy1_spd_led_groups[] = {\n+\t\"gpio1\",\n+};\n+\n+static const char * const ephy2_spd_led_groups[] = {\n+\t\"gpio2\",\n+};\n+\n+static const char * const ephy3_spd_led_groups[] = {\n+\t\"gpio3\",\n+};\n+\n+static const char * const ephy0_act_led_groups[] = {\n+\t\"gpio4\",\n+};\n+\n+static const char * const ephy1_act_led_groups[] = {\n+\t\"gpio5\",\n+};\n+\n+static const char * const ephy2_act_led_groups[] = {\n+\t\"gpio6\",\n+};\n+\n+static const char * const ephy3_act_led_groups[] = {\n+\t\"gpio7\",\n+};\n+\n+static const char * const serial_led_data_groups[] = {\n+\t\"gpio6\",\n+};\n+\n+static const char * const serial_led_clk_groups[] = {\n+\t\"gpio7\",\n+};\n+\n+static const char * const inet_act_led_groups[] = {\n+\t\"gpio8\",\n+};\n+\n+static const char * const inet_fail_led_groups[] = {\n+\t\"gpio9\",\n+};\n+\n+static const char * const dsl_led_groups[] = {\n+\t\"gpio10\",\n+};\n+\n+static const char * const post_fail_led_groups[] = {\n+\t\"gpio11\",\n+};\n+\n+static const char * const wlan_wps_led_groups[] = {\n+\t\"gpio12\",\n+};\n+\n+static const char * const usb_pwron_groups[] = {\n+\t\"gpio13\",\n+};\n+\n+static const char * const usb_device_led_groups[] = {\n+\t\"gpio13\",\n+};\n+\n+static const char * const usb_active_groups[] = {\n+\t\"gpio40\",\n+};\n+\n+#define BCM6318_MODE_FUN(n)\t\t\t\t\\\n+\t{\t\t\t\t\t\t\\\n+\t\t.name = #n,\t\t\t\t\\\n+\t\t.groups = n##_groups,\t\t\t\\\n+\t\t.num_groups = ARRAY_SIZE(n##_groups),\t\\\n+\t\t.mode_val = 1,\t\t\t\t\\\n+\t}\n+\n+#define BCM6318_MUX_FUN(n, mux)\t\t\t\t\\\n+\t{\t\t\t\t\t\t\\\n+\t\t.name = #n,\t\t\t\t\\\n+\t\t.groups = n##_groups,\t\t\t\\\n+\t\t.num_groups = ARRAY_SIZE(n##_groups),\t\\\n+\t\t.mux_val = mux,\t\t\t\t\\\n+\t}\n+\n+static const struct bcm6318_function bcm6318_funcs[] = {\n+\tBCM6318_MODE_FUN(led),\n+\tBCM6318_MUX_FUN(ephy0_spd_led, 1),\n+\tBCM6318_MUX_FUN(ephy1_spd_led, 1),\n+\tBCM6318_MUX_FUN(ephy2_spd_led, 1),\n+\tBCM6318_MUX_FUN(ephy3_spd_led, 1),\n+\tBCM6318_MUX_FUN(ephy0_act_led, 1),\n+\tBCM6318_MUX_FUN(ephy1_act_led, 1),\n+\tBCM6318_MUX_FUN(ephy2_act_led, 1),\n+\tBCM6318_MUX_FUN(ephy3_act_led, 1),\n+\tBCM6318_MUX_FUN(serial_led_data, 3),\n+\tBCM6318_MUX_FUN(serial_led_clk, 3),\n+\tBCM6318_MUX_FUN(inet_act_led, 1),\n+\tBCM6318_MUX_FUN(inet_fail_led, 1),\n+\tBCM6318_MUX_FUN(dsl_led, 1),\n+\tBCM6318_MUX_FUN(post_fail_led, 1),\n+\tBCM6318_MUX_FUN(wlan_wps_led, 1),\n+\tBCM6318_MUX_FUN(usb_pwron, 1),\n+\tBCM6318_MUX_FUN(usb_device_led, 2),\n+\tBCM6318_MUX_FUN(usb_active, 2),\n+};\n+\n+static inline unsigned int bcm6318_mux_off(unsigned int pin)\n+{\n+\treturn BCM6318_MUX_REG + (pin / 16) * 4;\n+}\n+\n+static inline unsigned int bcm6318_pad_off(unsigned int pin)\n+{\n+\treturn BCM6318_PAD_REG + (pin / 8) * 4;\n+}\n+\n+static int bcm6318_pinctrl_get_group_count(struct pinctrl_dev *pctldev)\n+{\n+\treturn ARRAY_SIZE(bcm6318_groups);\n+}\n+\n+static const char *bcm6318_pinctrl_get_group_name(struct pinctrl_dev *pctldev,\n+\t\t\t\t\t\t  unsigned group)\n+{\n+\treturn bcm6318_groups[group].name;\n+}\n+\n+static int bcm6318_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,\n+\t\t\t\t\t  unsigned group, const unsigned **pins,\n+\t\t\t\t\t  unsigned *num_pins)\n+{\n+\t*pins = bcm6318_groups[group].pins;\n+\t*num_pins = bcm6318_groups[group].num_pins;\n+\n+\treturn 0;\n+}\n+\n+static int bcm6318_pinctrl_get_func_count(struct pinctrl_dev *pctldev)\n+{\n+\treturn ARRAY_SIZE(bcm6318_funcs);\n+}\n+\n+static const char *bcm6318_pinctrl_get_func_name(struct pinctrl_dev *pctldev,\n+\t\t\t\t\t\t unsigned selector)\n+{\n+\treturn bcm6318_funcs[selector].name;\n+}\n+\n+static int bcm6318_pinctrl_get_groups(struct pinctrl_dev *pctldev,\n+\t\t\t\t      unsigned selector,\n+\t\t\t\t      const char * const **groups,\n+\t\t\t\t      unsigned * const num_groups)\n+{\n+\t*groups = bcm6318_funcs[selector].groups;\n+\t*num_groups = bcm6318_funcs[selector].num_groups;\n+\n+\treturn 0;\n+}\n+\n+static inline void bcm6318_rmw_mux(struct bcm63xx_pinctrl *pc, unsigned pin,\n+\t\t\t\t   unsigned int mode, unsigned int mux)\n+{\n+\tif (pin < BCM63XX_BANK_GPIOS)\n+\t\tregmap_update_bits(pc->regs, BCM6318_MODE_REG, BIT(pin),\n+\t\t\t\t   mode ? BIT(pin) : 0);\n+\n+\tif (pin < BCM6318_NUM_MUX)\n+\t\tregmap_update_bits(pc->regs,\n+\t\t\t\t   bcm6318_mux_off(pin),\n+\t\t\t\t   BCM6328_MUX_MASK << ((pin % 16) * 2),\n+\t\t\t\t   mux << ((pin % 16) * 2));\n+}\n+\n+static inline void bcm6318_set_pad(struct bcm63xx_pinctrl *pc, unsigned pin,\n+\t\t\t\t   uint8_t val)\n+{\n+\tregmap_update_bits(pc->regs, bcm6318_pad_off(pin),\n+\t\t\t   BCM6328_PAD_MASK << ((pin % 8) * 4),\n+\t\t\t   val << ((pin % 8) * 4));\n+}\n+\n+static int bcm6318_pinctrl_set_mux(struct pinctrl_dev *pctldev,\n+\t\t\t\t   unsigned selector, unsigned group)\n+{\n+\tstruct bcm63xx_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);\n+\tconst struct bcm6318_pingroup *pg = &bcm6318_groups[group];\n+\tconst struct bcm6318_function *f = &bcm6318_funcs[selector];\n+\n+\tbcm6318_rmw_mux(pc, pg->pins[0], f->mode_val, f->mux_val);\n+\n+\treturn 0;\n+}\n+\n+static int bcm6318_gpio_request_enable(struct pinctrl_dev *pctldev,\n+\t\t\t\t       struct pinctrl_gpio_range *range,\n+\t\t\t\t       unsigned offset)\n+{\n+\tstruct bcm63xx_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);\n+\n+\t/* disable all functions using this pin */\n+\tif (offset < 13) {\n+\t\t/* GPIOs 0-12 use mux 0 as GPIO function */\n+\t\tbcm6318_rmw_mux(pc, offset, 0, 0);\n+\t} else if (offset < 42) {\n+\t\t/* GPIOs 13-41 use mux 3 as GPIO function */\n+\t\tbcm6318_rmw_mux(pc, offset, 0, 3);\n+\n+\t\tbcm6318_set_pad(pc, offset, 0);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static struct pinctrl_ops bcm6318_pctl_ops = {\n+\t.dt_free_map = pinctrl_utils_free_map,\n+\t.dt_node_to_map = pinconf_generic_dt_node_to_map_pin,\n+\t.get_group_name = bcm6318_pinctrl_get_group_name,\n+\t.get_group_pins = bcm6318_pinctrl_get_group_pins,\n+\t.get_groups_count = bcm6318_pinctrl_get_group_count,\n+};\n+\n+static struct pinmux_ops bcm6318_pmx_ops = {\n+\t.get_function_groups = bcm6318_pinctrl_get_groups,\n+\t.get_function_name = bcm6318_pinctrl_get_func_name,\n+\t.get_functions_count = bcm6318_pinctrl_get_func_count,\n+\t.gpio_request_enable = bcm6318_gpio_request_enable,\n+\t.set_mux = bcm6318_pinctrl_set_mux,\n+\t.strict = true,\n+};\n+\n+static const struct bcm63xx_pinctrl_soc bcm6318_soc = {\n+\t.ngpios = BCM6318_NUM_GPIOS,\n+\t.npins = ARRAY_SIZE(bcm6318_pins),\n+\t.pctl_ops = &bcm6318_pctl_ops,\n+\t.pins = bcm6318_pins,\n+\t.pmx_ops = &bcm6318_pmx_ops,\n+};\n+\n+static int bcm6318_pinctrl_probe(struct platform_device *pdev)\n+{\n+\treturn bcm63xx_pinctrl_probe(pdev, &bcm6318_soc, NULL);\n+}\n+\n+static const struct of_device_id bcm6318_pinctrl_match[] = {\n+\t{ .compatible = \"brcm,bcm6318-pinctrl\", },\n+\t{ /* sentinel */ }\n+};\n+\n+static struct platform_driver bcm6318_pinctrl_driver = {\n+\t.probe = bcm6318_pinctrl_probe,\n+\t.driver = {\n+\t\t.name = \"bcm6318-pinctrl\",\n+\t\t.of_match_table = bcm6318_pinctrl_match,\n+\t},\n+};\n+\n+builtin_platform_driver(bcm6318_pinctrl_driver);\n"
  },
  {
    "path": "target/linux/bmips/patches-5.10/074-v5.13-pinctrl-bcm-bcm6362-fix-warning.patch",
    "content": "From 1978d88cdc8eb0986d36cac0e9541220fa71d87d Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com>\nDate: Tue, 30 Mar 2021 12:32:25 +0200\nSubject: [PATCH] pinctrl: bcm: bcm6362: fix warning\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nThe current implementation of bcm6362_set_gpio() produces the following\nwarning on x86_64:\ndrivers/pinctrl/bcm/pinctrl-bcm6362.c: In function 'bcm6362_set_gpio':\ndrivers/pinctrl/bcm/pinctrl-bcm6362.c:503:8: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]\n  503 |        (uint32_t) desc->drv_data, 0);\n      |        ^\n\nModify the code to make it similar to bcm63268_set_gpio() in order to fix\nthe warning.\n\nFixes: 705791e23ecd (\"pinctrl: add a pincontrol driver for BCM6362\")\nSigned-off-by: Álvaro Fernández Rojas <noltari@gmail.com>\nLink: https://lore.kernel.org/r/20210330103225.3949-1-noltari@gmail.com\nReviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>\nSigned-off-by: Linus Walleij <linus.walleij@linaro.org>\n---\n drivers/pinctrl/bcm/pinctrl-bcm6362.c | 6 +++---\n 1 file changed, 3 insertions(+), 3 deletions(-)\n\n--- a/drivers/pinctrl/bcm/pinctrl-bcm6362.c\n+++ b/drivers/pinctrl/bcm/pinctrl-bcm6362.c\n@@ -496,11 +496,11 @@ static int bcm6362_pinctrl_get_groups(st\n static void bcm6362_set_gpio(struct bcm63xx_pinctrl *pc, unsigned pin)\n {\n \tconst struct pinctrl_pin_desc *desc = &bcm6362_pins[pin];\n+\tunsigned int basemode = (uintptr_t)desc->drv_data;\n \tunsigned int mask = bcm63xx_bank_pin(pin);\n \n-\tif (desc->drv_data)\n-\t\tregmap_update_bits(pc->regs, BCM6362_BASEMODE_REG,\n-\t\t\t\t   (uint32_t) desc->drv_data, 0);\n+\tif (basemode)\n+\t\tregmap_update_bits(pc->regs, BCM6362_BASEMODE_REG, basemode, 0);\n \n \tif (pin < BCM63XX_BANK_GPIOS) {\n \t\t/* base mode 0 => gpio 1 => mux function */\n"
  },
  {
    "path": "target/linux/bmips/patches-5.10/075-v5.13-pinctrl-bcm63xx-Fix-dependencies.patch",
    "content": "From 26ea7ac92836ba616f75a1ab57e64ffc21da7758 Mon Sep 17 00:00:00 2001\nFrom: Linus Walleij <linus.walleij@linaro.org>\nDate: Wed, 31 Mar 2021 14:45:05 +0200\nSubject: [PATCH] pinctrl: bcm63xx: Fix dependencies\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nAdd depends on OF so we don't get weird build errors on\nrandconfig.\n\nAlso order selects the same as the other drivers for\npure aestetic reasons.\n\nReported-by: Randy Dunlap <rdunlap@infradead.org>\nCc: Álvaro Fernández Rojas <noltari@gmail.com>\nSigned-off-by: Linus Walleij <linus.walleij@linaro.org>\n---\n drivers/pinctrl/bcm/Kconfig | 6 ++++--\n 1 file changed, 4 insertions(+), 2 deletions(-)\n\n--- a/drivers/pinctrl/bcm/Kconfig\n+++ b/drivers/pinctrl/bcm/Kconfig\n@@ -31,10 +31,12 @@ config PINCTRL_BCM2835\n \n config PINCTRL_BCM63XX\n \tbool\n+\tdepends on OF\n+\tselect PINMUX\n+\tselect PINCONF\n \tselect GENERIC_PINCONF\n+\tselect GPIOLIB\n \tselect GPIO_REGMAP\n-\tselect PINCONF\n-\tselect PINMUX\n \n config PINCTRL_BCM6318\n \tbool \"Broadcom BCM6318 GPIO driver\"\n"
  },
  {
    "path": "target/linux/bmips/patches-5.10/080-v5.14-watchdog-bcm7038_wdt-add-big-endian-support.patch",
    "content": "From e379c2199de4280243e43118dceb4ea5e97059a3 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com>\nDate: Tue, 23 Feb 2021 09:00:42 +0100\nSubject: [PATCH] watchdog: bcm7038_wdt: add big endian support\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nbcm7038_wdt can be used on bmips big endian (bcm63xx) devices too.\n\nSigned-off-by: Álvaro Fernández Rojas <noltari@gmail.com>\nReviewed-by: Guenter Roeck <linux@roeck-us.net>\nLink: https://lore.kernel.org/r/20210223080042.29569-1-noltari@gmail.com\nSigned-off-by: Guenter Roeck <linux@roeck-us.net>\nSigned-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>\n---\n drivers/watchdog/bcm7038_wdt.c | 31 +++++++++++++++++++++++++------\n 1 file changed, 25 insertions(+), 6 deletions(-)\n\n--- a/drivers/watchdog/bcm7038_wdt.c\n+++ b/drivers/watchdog/bcm7038_wdt.c\n@@ -34,6 +34,25 @@ struct bcm7038_watchdog {\n \n static bool nowayout = WATCHDOG_NOWAYOUT;\n \n+static inline void bcm7038_wdt_write(u32 value, void __iomem *addr)\n+{\n+\t/* MIPS chips strapped for BE will automagically configure the\n+\t * peripheral registers for CPU-native byte order.\n+\t */\n+\tif (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))\n+\t\t__raw_writel(value, addr);\n+\telse\n+\t\twritel_relaxed(value, addr);\n+}\n+\n+static inline u32 bcm7038_wdt_read(void __iomem *addr)\n+{\n+\tif (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))\n+\t\treturn __raw_readl(addr);\n+\telse\n+\t\treturn readl_relaxed(addr);\n+}\n+\n static void bcm7038_wdt_set_timeout_reg(struct watchdog_device *wdog)\n {\n \tstruct bcm7038_watchdog *wdt = watchdog_get_drvdata(wdog);\n@@ -41,15 +60,15 @@ static void bcm7038_wdt_set_timeout_reg(\n \n \ttimeout = wdt->rate * wdog->timeout;\n \n-\twritel(timeout, wdt->base + WDT_TIMEOUT_REG);\n+\tbcm7038_wdt_write(timeout, wdt->base + WDT_TIMEOUT_REG);\n }\n \n static int bcm7038_wdt_ping(struct watchdog_device *wdog)\n {\n \tstruct bcm7038_watchdog *wdt = watchdog_get_drvdata(wdog);\n \n-\twritel(WDT_START_1, wdt->base + WDT_CMD_REG);\n-\twritel(WDT_START_2, wdt->base + WDT_CMD_REG);\n+\tbcm7038_wdt_write(WDT_START_1, wdt->base + WDT_CMD_REG);\n+\tbcm7038_wdt_write(WDT_START_2, wdt->base + WDT_CMD_REG);\n \n \treturn 0;\n }\n@@ -66,8 +85,8 @@ static int bcm7038_wdt_stop(struct watch\n {\n \tstruct bcm7038_watchdog *wdt = watchdog_get_drvdata(wdog);\n \n-\twritel(WDT_STOP_1, wdt->base + WDT_CMD_REG);\n-\twritel(WDT_STOP_2, wdt->base + WDT_CMD_REG);\n+\tbcm7038_wdt_write(WDT_STOP_1, wdt->base + WDT_CMD_REG);\n+\tbcm7038_wdt_write(WDT_STOP_2, wdt->base + WDT_CMD_REG);\n \n \treturn 0;\n }\n@@ -88,7 +107,7 @@ static unsigned int bcm7038_wdt_get_time\n \tstruct bcm7038_watchdog *wdt = watchdog_get_drvdata(wdog);\n \tu32 time_left;\n \n-\ttime_left = readl(wdt->base + WDT_CMD_REG);\n+\ttime_left = bcm7038_wdt_read(wdt->base + WDT_CMD_REG);\n \n \treturn time_left / wdt->rate;\n }\n"
  },
  {
    "path": "target/linux/bmips/patches-5.10/100-irqchip-add-support-for-bcm6345-style-external-inter.patch",
    "content": "From cf908990d4a8ccdb73ee4484aa8cadad379ca314 Mon Sep 17 00:00:00 2001\nFrom: Jonas Gorski <jogo@openwrt.org>\nDate: Sun, 30 Nov 2014 14:54:27 +0100\nSubject: [PATCH 2/5] irqchip: add support for bcm6345-style external\n interrupt controller\n\nSigned-off-by: Jonas Gorski <jogo@openwrt.org>\n---\n .../interrupt-controller/brcm,bcm6345-ext-intc.txt |   29 ++\n drivers/irqchip/Kconfig                            |    4 +\n drivers/irqchip/Makefile                           |    1 +\n drivers/irqchip/irq-bcm6345-ext.c                  |  287 ++++++++++++++++++++\n include/linux/irqchip/irq-bcm6345-ext.h            |   14 +\n 5 files changed, 335 insertions(+)\n create mode 100644 Documentation/devicetree/bindings/interrupt-controller/brcm,bcm6345-ext-intc.txt\n create mode 100644 drivers/irqchip/irq-bcm6345-ext.c\n create mode 100644 include/linux/irqchip/irq-bcm6345-ext.h\n\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm6345-ext-intc.txt\n@@ -0,0 +1,29 @@\n+Broadcom BCM6345-style external interrupt controller\n+\n+Required properties:\n+\n+- compatible: Should be \"brcm,bcm6345-ext-intc\" or \"brcm,bcm6318-ext-intc\".\n+- reg: Specifies the base physical addresses and size of the registers.\n+- interrupt-controller: identifies the node as an interrupt controller.\n+- #interrupt-cells: Specifies the number of cells needed to encode an interrupt\n+  source, Should be 2.\n+- interrupt-parent: Specifies the phandle to the parent interrupt controller\n+  this one is cascaded from.\n+- interrupts: Specifies the interrupt line(s) in the interrupt-parent controller\n+  node, valid values depend on the type of parent interrupt controller.\n+\n+Optional properties:\n+\n+- brcm,field-width: Size of each field (mask, clear, sense, ...) in bits in the\n+  register. Defaults to 4.\n+\n+Example:\n+\n+ext_intc: interrupt-controller@10000018 {\n+\tcompatible = \"brcm,bcm6345-ext-intc\";\n+\tinterrupt-parent = <&periph_intc>;\n+\t#interrupt-cells = <2>;\n+\treg = <0x10000018 0x4>;\n+\tinterrupt-controller;\n+\tinterrupts = <24>, <25>, <26>, <27>;\n+};\n--- a/drivers/irqchip/Kconfig\n+++ b/drivers/irqchip/Kconfig\n@@ -113,6 +113,10 @@ config I8259\n \tbool\n \tselect IRQ_DOMAIN\n \n+config BCM6345_EXT_IRQ\n+\tbool \"BCM6345 External IRQ Controller\"\n+\tselect IRQ_DOMAIN\n+\n config BCM6345_L1_IRQ\n \tbool\n \tselect GENERIC_IRQ_CHIP\n--- a/drivers/irqchip/Makefile\n+++ b/drivers/irqchip/Makefile\n@@ -63,6 +63,7 @@ obj-$(CONFIG_XTENSA_MX)\t\t\t+= irq-xtensa-\n obj-$(CONFIG_XILINX_INTC)\t\t+= irq-xilinx-intc.o\n obj-$(CONFIG_IRQ_CROSSBAR)\t\t+= irq-crossbar.o\n obj-$(CONFIG_SOC_VF610)\t\t\t+= irq-vf610-mscm-ir.o\n+obj-$(CONFIG_BCM6345_EXT_IRQ)\t\t+= irq-bcm6345-ext.o\n obj-$(CONFIG_BCM6345_L1_IRQ)\t\t+= irq-bcm6345-l1.o\n obj-$(CONFIG_BCM7038_L1_IRQ)\t\t+= irq-bcm7038-l1.o\n obj-$(CONFIG_BCM7120_L2_IRQ)\t\t+= irq-bcm7120-l2.o\n--- /dev/null\n+++ b/drivers/irqchip/irq-bcm6345-ext.c\n@@ -0,0 +1,299 @@\n+/*\n+ * This file is subject to the terms and conditions of the GNU General Public\n+ * License.  See the file \"COPYING\" in the main directory of this archive\n+ * for more details.\n+ *\n+ * Copyright (C) 2014 Jonas Gorski <jogo@openwrt.org>\n+ */\n+\n+#include <linux/ioport.h>\n+#include <linux/irq.h>\n+#include <linux/irqchip.h>\n+#include <linux/irqchip/chained_irq.h>\n+#include <linux/irqchip/irq-bcm6345-ext.h>\n+#include <linux/kernel.h>\n+#include <linux/of.h>\n+#include <linux/of_irq.h>\n+#include <linux/of_address.h>\n+#include <linux/slab.h>\n+#include <linux/spinlock.h>\n+\n+#ifdef CONFIG_BCM63XX\n+#include <asm/mach-bcm63xx/bcm63xx_irq.h>\n+\n+#define VIRQ_BASE\t\tIRQ_EXTERNAL_BASE\n+#else\n+#define VIRQ_BASE\t\t0\n+#endif\n+\n+#define MAX_IRQS\t\t4\n+\n+#define EXTIRQ_CFG_SENSE\t0\n+#define EXTIRQ_CFG_STAT\t\t1\n+#define EXTIRQ_CFG_CLEAR\t2\n+#define EXTIRQ_CFG_MASK\t\t3\n+#define EXTIRQ_CFG_BOTHEDGE\t4\n+#define EXTIRQ_CFG_LEVELSENSE\t5\n+\n+struct intc_data {\n+\tstruct irq_chip chip;\n+\tstruct irq_domain *domain;\n+\traw_spinlock_t lock;\n+\n+\tint parent_irq[MAX_IRQS];\n+\tvoid __iomem *reg;\n+\tint shift;\n+\tunsigned int toggle_clear_on_ack:1;\n+};\n+\n+static void bcm6345_ext_intc_irq_handle(struct irq_desc *desc)\n+{\n+\tstruct intc_data *data = irq_desc_get_handler_data(desc);\n+\tstruct irq_chip *chip = irq_desc_get_chip(desc);\n+\tunsigned int irq = irq_desc_get_irq(desc);\n+\tunsigned int idx;\n+\n+\tchained_irq_enter(chip, desc);\n+\n+\tfor (idx = 0; idx < MAX_IRQS; idx++) {\n+\t\tif (data->parent_irq[idx] != irq)\n+\t\t\tcontinue;\n+\n+\t\tgeneric_handle_irq(irq_find_mapping(data->domain, idx));\n+\t}\n+\n+\tchained_irq_exit(chip, desc);\n+}\n+\n+static void bcm6345_ext_intc_irq_ack(struct irq_data *data)\n+{\n+\tstruct intc_data *priv = data->domain->host_data;\n+\tirq_hw_number_t hwirq = irqd_to_hwirq(data);\n+\tu32 reg;\n+\n+\traw_spin_lock(&priv->lock);\n+\treg = __raw_readl(priv->reg);\n+\t__raw_writel(reg | (1 << (hwirq + EXTIRQ_CFG_CLEAR * priv->shift)),\n+\t\t     priv->reg);\n+\tif (priv->toggle_clear_on_ack)\n+\t\t__raw_writel(reg, priv->reg);\n+\traw_spin_unlock(&priv->lock);\n+}\n+\n+static void bcm6345_ext_intc_irq_mask(struct irq_data *data)\n+{\n+\tstruct intc_data *priv = data->domain->host_data;\n+\tirq_hw_number_t hwirq = irqd_to_hwirq(data);\n+\tu32 reg;\n+\n+\traw_spin_lock(&priv->lock);\n+\treg = __raw_readl(priv->reg);\n+\treg &= ~(1 << (hwirq + EXTIRQ_CFG_MASK * priv->shift));\n+\t__raw_writel(reg, priv->reg);\n+\traw_spin_unlock(&priv->lock);\n+}\n+\n+static void bcm6345_ext_intc_irq_unmask(struct irq_data *data)\n+{\n+\tstruct intc_data *priv = data->domain->host_data;\n+\tirq_hw_number_t hwirq = irqd_to_hwirq(data);\n+\tu32 reg;\n+\n+\traw_spin_lock(&priv->lock);\n+\treg = __raw_readl(priv->reg);\n+\treg |= 1 << (hwirq + EXTIRQ_CFG_MASK * priv->shift);\n+\t__raw_writel(reg, priv->reg);\n+\traw_spin_unlock(&priv->lock);\n+}\n+\n+static int bcm6345_ext_intc_set_type(struct irq_data *data,\n+\t\t\t\t     unsigned int flow_type)\n+{\n+\tstruct intc_data *priv = data->domain->host_data;\n+\tirq_hw_number_t hwirq = irqd_to_hwirq(data);\n+\tbool levelsense = 0, sense = 0, bothedge = 0;\n+\tu32 reg;\n+\n+\tflow_type &= IRQ_TYPE_SENSE_MASK;\n+\n+\tif (flow_type == IRQ_TYPE_NONE)\n+\t\tflow_type = IRQ_TYPE_LEVEL_LOW;\n+\n+\tswitch (flow_type) {\n+\tcase IRQ_TYPE_EDGE_BOTH:\n+\t\tbothedge = 1;\n+\t\tbreak;\n+\n+\tcase IRQ_TYPE_EDGE_RISING:\n+\t\tsense = 1;\n+\t\tbreak;\n+\n+\tcase IRQ_TYPE_EDGE_FALLING:\n+\t\tbreak;\n+\n+\tcase IRQ_TYPE_LEVEL_HIGH:\n+\t\tlevelsense = 1;\n+\t\tsense = 1;\n+\t\tbreak;\n+\n+\tcase IRQ_TYPE_LEVEL_LOW:\n+\t\tlevelsense = 1;\n+\t\tbreak;\n+\n+\tdefault:\n+\t\tpr_err(\"bogus flow type combination given!\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\traw_spin_lock(&priv->lock);\n+\treg = __raw_readl(priv->reg);\n+\n+\tif (levelsense)\n+\t\treg |= 1 << (hwirq + EXTIRQ_CFG_LEVELSENSE * priv->shift);\n+\telse\n+\t\treg &= ~(1 << (hwirq + EXTIRQ_CFG_LEVELSENSE * priv->shift));\n+\tif (sense)\n+\t\treg |= 1 << (hwirq + EXTIRQ_CFG_SENSE * priv->shift);\n+\telse\n+\t\treg &= ~(1 << (hwirq + EXTIRQ_CFG_SENSE * priv->shift));\n+\tif (bothedge)\n+\t\treg |= 1 << (hwirq + EXTIRQ_CFG_BOTHEDGE * priv->shift);\n+\telse\n+\t\treg &= ~(1 << (hwirq + EXTIRQ_CFG_BOTHEDGE * priv->shift));\n+\n+\t__raw_writel(reg, priv->reg);\n+\traw_spin_unlock(&priv->lock);\n+\n+\tirqd_set_trigger_type(data, flow_type);\n+\tif (flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))\n+\t\tirq_set_handler_locked(data, handle_level_irq);\n+\telse\n+\t\tirq_set_handler_locked(data, handle_edge_irq);\n+\n+\treturn 0;\n+}\n+\n+static int bcm6345_ext_intc_map(struct irq_domain *d, unsigned int irq,\n+\t\t\t\tirq_hw_number_t hw)\n+{\n+\tstruct intc_data *priv = d->host_data;\n+\n+\tirq_set_chip_and_handler(irq, &priv->chip, handle_level_irq);\n+\n+\treturn 0;\n+}\n+\n+static const struct irq_domain_ops bcm6345_ext_domain_ops = {\n+\t.xlate = irq_domain_xlate_twocell,\n+\t.map = bcm6345_ext_intc_map,\n+};\n+\n+static int __init __bcm6345_ext_intc_init(struct device_node *node,\n+\t\t\t\t\t  int num_irqs, int *irqs,\n+\t\t\t\t\t  void __iomem *reg, int shift,\n+\t\t\t\t\t  bool toggle_clear_on_ack)\n+{\n+\tstruct intc_data *data;\n+\tunsigned int i;\n+\tint start = VIRQ_BASE;\n+\n+\tdata = kzalloc(sizeof(*data), GFP_KERNEL);\n+\tif (!data)\n+\t\treturn -ENOMEM;\n+\n+\traw_spin_lock_init(&data->lock);\n+\n+\tfor (i = 0; i < num_irqs; i++) {\n+\t\tdata->parent_irq[i] = irqs[i];\n+\n+\t\tirq_set_handler_data(irqs[i], data);\n+\t\tirq_set_chained_handler(irqs[i], bcm6345_ext_intc_irq_handle);\n+\t}\n+\n+\tdata->reg = reg;\n+\tdata->shift = shift;\n+\tdata->toggle_clear_on_ack = toggle_clear_on_ack;\n+\n+\tdata->chip.name = \"bcm6345-ext-intc\";\n+\tdata->chip.irq_ack = bcm6345_ext_intc_irq_ack;\n+\tdata->chip.irq_mask = bcm6345_ext_intc_irq_mask;\n+\tdata->chip.irq_unmask = bcm6345_ext_intc_irq_unmask;\n+\tdata->chip.irq_set_type = bcm6345_ext_intc_set_type;\n+\n+\t/*\n+\t * If we have less than 4 irqs, this is the second controller on\n+\t * bcm63xx. So increase the VIRQ start to not overlap with the first\n+\t * one, but only do so if we actually use a non-zero start.\n+\t *\n+\t * This can be removed when bcm63xx has no legacy users anymore.\n+\t */\n+\tif (start && num_irqs < 4)\n+\t\tstart += 4;\n+\n+\tdata->domain = irq_domain_add_simple(node, num_irqs, start,\n+\t\t\t\t\t     &bcm6345_ext_domain_ops, data);\n+\tif (!data->domain) {\n+\t\tkfree(data);\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+void __init bcm6345_ext_intc_init(int num_irqs, int *irqs, void __iomem *reg,\n+\t\t\t\t  int shift)\n+{\n+\t__bcm6345_ext_intc_init(NULL, num_irqs, irqs, reg, shift, false);\n+}\n+\n+#ifdef CONFIG_OF\n+static int __init bcm6345_ext_intc_of_init(struct device_node *node,\n+\t\t\t\t\t   struct device_node *parent)\n+{\n+\tint num_irqs, ret = -EINVAL;\n+\tunsigned i;\n+\tvoid __iomem *base;\n+\tint irqs[MAX_IRQS] = { 0 };\n+\tu32 shift;\n+\tbool toggle_clear_on_ack = false;\n+\n+\tnum_irqs = of_irq_count(node);\n+\n+\tif (!num_irqs || num_irqs > MAX_IRQS)\n+\t\treturn -EINVAL;\n+\n+\tif (of_property_read_u32(node, \"brcm,field-width\", &shift))\n+\t\tshift = 4;\n+\n+\t/* on BCM6318 setting CLEAR seems to continuously mask interrupts */\n+\tif (of_device_is_compatible(node, \"brcm,bcm6318-ext-intc\"))\n+\t\ttoggle_clear_on_ack = true;\n+\n+\tfor (i = 0; i < num_irqs; i++) {\n+\t\tirqs[i] = irq_of_parse_and_map(node, i);\n+\t\tif (!irqs[i])\n+\t\t\treturn -ENOMEM;\n+\t}\n+\n+\tbase = of_iomap(node, 0);\n+\tif (!base)\n+\t\treturn -ENXIO;\n+\n+\tret = __bcm6345_ext_intc_init(node, num_irqs, irqs, base, shift,\n+\t\t\t\t      toggle_clear_on_ack);\n+\tif (!ret)\n+\t\treturn 0;\n+\n+\tiounmap(base);\n+\n+\tfor (i = 0; i < num_irqs; i++)\n+\t\tirq_dispose_mapping(irqs[i]);\n+\n+\treturn ret;\n+}\n+\n+IRQCHIP_DECLARE(bcm6318_ext_intc, \"brcm,bcm6318-ext-intc\",\n+\t\tbcm6345_ext_intc_of_init);\n+IRQCHIP_DECLARE(bcm6345_ext_intc, \"brcm,bcm6345-ext-intc\",\n+\t\tbcm6345_ext_intc_of_init);\n+#endif\n--- /dev/null\n+++ b/include/linux/irqchip/irq-bcm6345-ext.h\n@@ -0,0 +1,14 @@\n+/*\n+ * This file is subject to the terms and conditions of the GNU General Public\n+ * License.  See the file \"COPYING\" in the main directory of this archive\n+ * for more details.\n+ *\n+ * Copyright (C) 2014 Jonas Gorski <jogo@openwrt.org>\n+ */\n+\n+#ifndef __INCLUDE_LINUX_IRQCHIP_IRQ_BCM6345_EXT_H\n+#define __INCLUDE_LINUX_IRQCHIP_IRQ_BCM6345_EXT_H\n+\n+void bcm6345_ext_intc_init(int n_irqs, int *irqs, void __iomem *reg, int shift);\n+\n+#endif /* __INCLUDE_LINUX_IRQCHIP_IRQ_BCM6345_EXT_H */\n"
  },
  {
    "path": "target/linux/bmips/patches-5.10/110-mips-bmips-add-BCM63268-timer-clock-definitions.patch",
    "content": "From 5a079515cb3066aeb658634301a98871b47c2af4 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com>\nDate: Thu, 25 Feb 2021 19:44:22 +0100\nSubject: [PATCH 1/4] mips: bmips: add BCM63268 timer clock definitions\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nAdd missing timer clock definitions for BCM63268.\n\nSigned-off-by: Álvaro Fernández Rojas <noltari@gmail.com>\n---\n include/dt-bindings/clock/bcm63268-clock.h | 13 +++++++++++++\n 1 file changed, 13 insertions(+)\n\n--- a/include/dt-bindings/clock/bcm63268-clock.h\n+++ b/include/dt-bindings/clock/bcm63268-clock.h\n@@ -27,4 +27,17 @@\n #define BCM63268_CLK_TBUS\t27\n #define BCM63268_CLK_ROBOSW250\t31\n \n+#define BCM63268_TCLK_EPHY1\t\t0\n+#define BCM63268_TCLK_EPHY2\t\t1\n+#define BCM63268_TCLK_EPHY3\t\t2\n+#define BCM63268_TCLK_GPHY1\t\t3\n+#define BCM63268_TCLK_DSL\t\t4\n+#define BCM63268_TCLK_WAKEON_EPHY\t6\n+#define BCM63268_TCLK_WAKEON_DSL\t7\n+#define BCM63268_TCLK_FAP1\t\t11\n+#define BCM63268_TCLK_FAP2\t\t15\n+#define BCM63268_TCLK_UTO_50\t\t16\n+#define BCM63268_TCLK_UTO_EXTIN\t\t17\n+#define BCM63268_TCLK_USB_REF\t\t18\n+\n #endif /* __DT_BINDINGS_CLOCK_BCM63268_H */\n"
  },
  {
    "path": "target/linux/bmips/patches-5.10/111-mips-bmips-add-BCM63268-timer-reset-definitions.patch",
    "content": "From 3327df17635dd9d24a855ac6b7247fac381514cf Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com>\nDate: Thu, 25 Feb 2021 19:45:04 +0100\nSubject: [PATCH 2/4] mips: bmips: add BCM63268 timer reset definitions\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nAdd missing timer reset definitions for BCM63268.\n\nSigned-off-by: Álvaro Fernández Rojas <noltari@gmail.com>\n---\n include/dt-bindings/reset/bcm63268-reset.h | 4 ++++\n 1 file changed, 4 insertions(+)\n\n--- a/include/dt-bindings/reset/bcm63268-reset.h\n+++ b/include/dt-bindings/reset/bcm63268-reset.h\n@@ -23,4 +23,8 @@\n #define BCM63268_RST_PCIE_HARD\t17\n #define BCM63268_RST_GPHY\t18\n \n+#define BCM63268_TRST_SW\t29\n+#define BCM63268_TRST_HW\t30\n+#define BCM63268_TRST_POR\t31\n+\n #endif /* __DT_BINDINGS_RESET_BCM63268_H */\n"
  },
  {
    "path": "target/linux/bmips/patches-5.10/112-dt-bindings-clock-Add-BCM63268-timer-binding.patch",
    "content": "From c17702bad18a085ae913752b45bcc20c2cea879e Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com>\nDate: Thu, 25 Feb 2021 19:53:08 +0100\nSubject: [PATCH 3/4] dt-bindings: clock: Add BCM63268 timer binding\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nDocument the Broadcom BCM63268 Clock and Reset controller.\n\nSigned-off-by: Álvaro Fernández Rojas <noltari@gmail.com>\n---\n .../clock/brcm,bcm63268-timer-clocks.yaml     | 40 +++++++++++++++++++\n 1 file changed, 40 insertions(+)\n create mode 100644 Documentation/devicetree/bindings/clock/brcm,bcm63268-timer-clocks.yaml\n\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/clock/brcm,bcm63268-timer-clocks.yaml\n@@ -0,0 +1,40 @@\n+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)\n+%YAML 1.2\n+---\n+$id: http://devicetree.org/schemas/clock/brcm,bcm63268-timer-clocks.yaml#\n+$schema: http://devicetree.org/meta-schemas/core.yaml#\n+\n+title: Broadcom BCM63268 Timer Clock and Reset Device Tree Bindings\n+\n+maintainers:\n+  - Álvaro Fernández Rojas <noltari@gmail.com>\n+\n+properties:\n+  compatible:\n+    const: brcm,bcm63268-timer-clocks\n+\n+  reg:\n+    maxItems: 1\n+\n+  \"#clock-cells\":\n+    const: 1\n+\n+  \"#reset-cells\":\n+    const: 1\n+\n+required:\n+  - compatible\n+  - reg\n+  - \"#clock-cells\"\n+  - \"#reset-cells\"\n+\n+additionalProperties: false\n+\n+examples:\n+  - |\n+    timer_clk: clock-controller@100000ac {\n+      compatible = \"brcm,bcm63268-timer-clocks\";\n+      reg = <0x100000ac 0x4>;\n+      #clock-cells = <1>;\n+      #reset-cells = <1>;\n+    };\n"
  },
  {
    "path": "target/linux/bmips/patches-5.10/113-clk-bcm-Add-BCM63268-timer-clock-and-reset-driver.patch",
    "content": "From 3c8dd9d0937a19f3f20f28ba0b0b64f448d50dd4 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com>\nDate: Thu, 25 Feb 2021 19:54:04 +0100\nSubject: [PATCH 4/4] clk: bcm: Add BCM63268 timer clock and reset driver\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nAdd driver for BCM63268 timer clock and reset controller.\n\nSigned-off-by: Álvaro Fernández Rojas <noltari@gmail.com>\n---\n drivers/clk/bcm/Kconfig              |   9 ++\n drivers/clk/bcm/Makefile             |   1 +\n drivers/clk/bcm/clk-bcm63268-timer.c | 232 +++++++++++++++++++++++++++\n 3 files changed, 242 insertions(+)\n create mode 100644 drivers/clk/bcm/clk-bcm63268-timer.c\n\n--- a/drivers/clk/bcm/Kconfig\n+++ b/drivers/clk/bcm/Kconfig\n@@ -37,6 +37,15 @@ config CLK_BCM_63XX_GATE\n \t  Enable common clock framework support for Broadcom BCM63xx DSL SoCs\n \t  based on the MIPS architecture\n \n+config CLK_BCM63268_TIMER\n+\tbool \"Broadcom BCM63268 timer clock and reset support\"\n+\tdepends on BMIPS_GENERIC || COMPILE_TEST\n+\tdefault BMIPS_GENERIC\n+\tselect RESET_CONTROLLER\n+\thelp\n+\t  Enable timer clock and reset support for Broadcom BCM63268 DSL SoCs\n+\t  based on the MIPS architecture.\n+\n config CLK_BCM_KONA\n \tbool \"Broadcom Kona CCU clock support\"\n \tdepends on ARCH_BCM_MOBILE || COMPILE_TEST\n--- a/drivers/clk/bcm/Makefile\n+++ b/drivers/clk/bcm/Makefile\n@@ -1,6 +1,7 @@\n # SPDX-License-Identifier: GPL-2.0\n obj-$(CONFIG_CLK_BCM_63XX)\t+= clk-bcm63xx.o\n obj-$(CONFIG_CLK_BCM_63XX_GATE)\t+= clk-bcm63xx-gate.o\n+obj-$(CONFIG_CLK_BCM63268_TIMER) += clk-bcm63268-timer.o\n obj-$(CONFIG_CLK_BCM_KONA)\t+= clk-kona.o\n obj-$(CONFIG_CLK_BCM_KONA)\t+= clk-kona-setup.o\n obj-$(CONFIG_CLK_BCM_KONA)\t+= clk-bcm281xx.o\n--- /dev/null\n+++ b/drivers/clk/bcm/clk-bcm63268-timer.c\n@@ -0,0 +1,232 @@\n+// SPDX-License-Identifier: GPL-2.0\n+/*\n+ * BCM63268 Timer Clock and Reset Controller Driver\n+ *\n+ * Copyright (C) 2021 Álvaro Fernández Rojas <noltari@gmail.com>\n+ */\n+\n+#include <linux/clk-provider.h>\n+#include <linux/delay.h>\n+#include <linux/init.h>\n+#include <linux/of.h>\n+#include <linux/of_device.h>\n+#include <linux/platform_device.h>\n+#include <linux/reset-controller.h>\n+\n+#include <dt-bindings/clock/bcm63268-clock.h>\n+\n+#define BCM63268_TIMER_RESET_SLEEP_MIN_US\t10000\n+#define BCM63268_TIMER_RESET_SLEEP_MAX_US\t20000\n+\n+struct bcm63268_tclkrst_hw {\n+\tvoid __iomem *regs;\n+\tspinlock_t lock;\n+\n+\tstruct reset_controller_dev rcdev;\n+\tstruct clk_hw_onecell_data data;\n+};\n+\n+struct bcm63268_tclk_table_entry {\n+\tconst char * const name;\n+\tu8 bit;\n+\tunsigned long flags;\n+};\n+\n+static const struct bcm63268_tclk_table_entry bcm63268_timer_clocks[] = {\n+\t{\n+\t\t.name = \"ephy1\",\n+\t\t.bit = BCM63268_TCLK_EPHY1,\n+\t}, {\n+\t\t.name = \"ephy2\",\n+\t\t.bit = BCM63268_TCLK_EPHY2,\n+\t}, {\n+\t\t.name = \"ephy3\",\n+\t\t.bit = BCM63268_TCLK_EPHY3,\n+\t}, {\n+\t\t.name = \"gphy1\",\n+\t\t.bit = BCM63268_TCLK_GPHY1,\n+\t}, {\n+\t\t.name = \"dsl\",\n+\t\t.bit = BCM63268_TCLK_DSL,\n+\t}, {\n+\t\t.name = \"wakeon_ephy\",\n+\t\t.bit = BCM63268_TCLK_WAKEON_EPHY,\n+\t}, {\n+\t\t.name = \"wakeon_dsl\",\n+\t\t.bit = BCM63268_TCLK_WAKEON_DSL,\n+\t}, {\n+\t\t.name = \"fap1_pll\",\n+\t\t.bit = BCM63268_TCLK_FAP1,\n+\t}, {\n+\t\t.name = \"fap2_pll\",\n+\t\t.bit = BCM63268_TCLK_FAP2,\n+\t}, {\n+\t\t.name = \"uto_50\",\n+\t\t.bit = BCM63268_TCLK_UTO_50,\n+\t}, {\n+\t\t.name = \"uto_extin\",\n+\t\t.bit = BCM63268_TCLK_UTO_EXTIN,\n+\t}, {\n+\t\t.name = \"usb_ref\",\n+\t\t.bit = BCM63268_TCLK_USB_REF,\n+\t}, {\n+\t\t/* sentinel */\n+\t}\n+};\n+\n+static inline struct bcm63268_tclkrst_hw *\n+to_bcm63268_timer_reset(struct reset_controller_dev *rcdev)\n+{\n+\treturn container_of(rcdev, struct bcm63268_tclkrst_hw, rcdev);\n+}\n+\n+static int bcm63268_timer_reset_update(struct reset_controller_dev *rcdev,\n+\t\t\t\tunsigned long id, bool assert)\n+{\n+\tstruct bcm63268_tclkrst_hw *reset = to_bcm63268_timer_reset(rcdev);\n+\tunsigned long flags;\n+\tuint32_t val;\n+\n+\tspin_lock_irqsave(&reset->lock, flags);\n+\tval = __raw_readl(reset->regs);\n+\tif (assert)\n+\t\tval &= ~BIT(id);\n+\telse\n+\t\tval |= BIT(id);\n+\t__raw_writel(val, reset->regs);\n+\tspin_unlock_irqrestore(&reset->lock, flags);\n+\n+\treturn 0;\n+}\n+\n+static int bcm63268_timer_reset_assert(struct reset_controller_dev *rcdev,\n+\t\t\t\tunsigned long id)\n+{\n+\treturn bcm63268_timer_reset_update(rcdev, id, true);\n+}\n+\n+static int bcm63268_timer_reset_deassert(struct reset_controller_dev *rcdev,\n+\t\t\t\t  unsigned long id)\n+{\n+\treturn bcm63268_timer_reset_update(rcdev, id, false);\n+}\n+\n+static int bcm63268_timer_reset_reset(struct reset_controller_dev *rcdev,\n+\t\t\t       unsigned long id)\n+{\n+\tbcm63268_timer_reset_update(rcdev, id, true);\n+\tusleep_range(BCM63268_TIMER_RESET_SLEEP_MIN_US,\n+\t\t     BCM63268_TIMER_RESET_SLEEP_MAX_US);\n+\n+\tbcm63268_timer_reset_update(rcdev, id, false);\n+\t/*\n+\t * Ensure component is taken out reset state by sleeping also after\n+\t * deasserting the reset. Otherwise, the component may not be ready\n+\t * for operation.\n+\t */\n+\tusleep_range(BCM63268_TIMER_RESET_SLEEP_MIN_US,\n+\t\t     BCM63268_TIMER_RESET_SLEEP_MAX_US);\n+\n+\treturn 0;\n+}\n+\n+static int bcm63268_timer_reset_status(struct reset_controller_dev *rcdev,\n+\t\t\t\tunsigned long id)\n+{\n+\tstruct bcm63268_tclkrst_hw *reset = to_bcm63268_timer_reset(rcdev);\n+\n+\treturn !(__raw_readl(reset->regs) & BIT(id));\n+}\n+\n+static struct reset_control_ops bcm63268_timer_reset_ops = {\n+\t.assert = bcm63268_timer_reset_assert,\n+\t.deassert = bcm63268_timer_reset_deassert,\n+\t.reset = bcm63268_timer_reset_reset,\n+\t.status = bcm63268_timer_reset_status,\n+};\n+\n+static int bcm63268_tclk_probe(struct platform_device *pdev)\n+{\n+\tstruct device *dev = &pdev->dev;\n+\tconst struct bcm63268_tclk_table_entry *entry, *table;\n+\tstruct bcm63268_tclkrst_hw *hw;\n+\tu8 maxbit = 0;\n+\tint i, ret;\n+\n+\ttable = of_device_get_match_data(dev);\n+\tif (!table)\n+\t\treturn -EINVAL;\n+\n+\tfor (entry = table; entry->name; entry++)\n+\t\tmaxbit = max_t(u8, maxbit, entry->bit);\n+\tmaxbit++;\n+\n+\thw = devm_kzalloc(&pdev->dev, struct_size(hw, data.hws, maxbit),\n+\t\t\t  GFP_KERNEL);\n+\tif (!hw)\n+\t\treturn -ENOMEM;\n+\n+\tplatform_set_drvdata(pdev, hw);\n+\n+\tspin_lock_init(&hw->lock);\n+\n+\thw->data.num = maxbit;\n+\tfor (i = 0; i < maxbit; i++)\n+\t\thw->data.hws[i] = ERR_PTR(-ENODEV);\n+\n+\thw->regs = devm_platform_ioremap_resource(pdev, 0);\n+\tif (IS_ERR(hw->regs))\n+\t\treturn PTR_ERR(hw->regs);\n+\n+\tfor (entry = table; entry->name; entry++) {\n+\t\tstruct clk_hw *clk;\n+\n+\t\tclk = clk_hw_register_gate(dev, entry->name, NULL,\n+\t\t\t\t\t   entry->flags, hw->regs, entry->bit,\n+\t\t\t\t\t   CLK_GATE_BIG_ENDIAN, &hw->lock);\n+\t\tif (IS_ERR(clk)) {\n+\t\t\tret = PTR_ERR(clk);\n+\t\t\tgoto out_err;\n+\t\t}\n+\n+\t\thw->data.hws[entry->bit] = clk;\n+\t}\n+\n+\tret = of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,\n+\t\t\t\t     &hw->data);\n+\tif (!ret)\n+\t\treturn 0;\n+\n+\thw->rcdev.of_node = dev->of_node;\n+\thw->rcdev.ops = &bcm63268_timer_reset_ops;\n+\n+\tret = devm_reset_controller_register(dev, &hw->rcdev);\n+\tif (ret)\n+\t\tdev_err(dev, \"Failed to register reset controller\\n\");\n+\n+out_err:\n+\tfor (i = 0; i < hw->data.num; i++) {\n+\t\tif (!IS_ERR(hw->data.hws[i]))\n+\t\t\tclk_hw_unregister_gate(hw->data.hws[i]);\n+\t}\n+\n+\treturn ret;\n+}\n+\n+static const struct of_device_id bcm63268_tclk_dt_ids[] = {\n+\t{\n+\t\t.compatible = \"brcm,bcm63268-timer-clocks\",\n+\t\t.data = &bcm63268_timer_clocks,\n+\t}, {\n+\t\t/* sentinel */\n+\t}\n+};\n+\n+static struct platform_driver bcm63268_tclk = {\n+\t.probe = bcm63268_tclk_probe,\n+\t.driver = {\n+\t\t.name = \"bcm63268-timer-clock\",\n+\t\t.of_match_table = bcm63268_tclk_dt_ids,\n+\t},\n+};\n+builtin_platform_driver(bcm63268_tclk);\n"
  },
  {
    "path": "target/linux/bmips/patches-5.10/200-mips-bmips-automatically-detect-CPU-frequency.patch",
    "content": "From 0377ad93031d3e51c2afe44231241185f684b6af Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com>\nDate: Fri, 5 Mar 2021 15:14:32 +0100\nSubject: [PATCH 1/2] mips: bmips: automatically detect CPU frequency\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nSome BCM63xx SoCs support multiple CPU frequencies depending on HW config.\n\nSigned-off-by: Álvaro Fernández Rojas <noltari@gmail.com>\n---\n arch/mips/bmips/setup.c | 198 ++++++++++++++++++++++++++++++++++++++--\n 1 file changed, 191 insertions(+), 7 deletions(-)\n\n--- a/arch/mips/bmips/setup.c\n+++ b/arch/mips/bmips/setup.c\n@@ -31,11 +31,51 @@\n \n #define RELO_NORMAL_VEC\t\tBIT(18)\n \n+#define REG_BCM6318_SOB\t\t((void __iomem *)CKSEG1ADDR(0x10000900))\n+#define BCM6318_FREQ_SHIFT\t23\n+#define BCM6318_FREQ_MASK\t(0x3 << BCM6318_FREQ_SHIFT)\n+\n #define REG_BCM6328_OTP\t\t((void __iomem *)CKSEG1ADDR(0x1000062c))\n #define BCM6328_TP1_DISABLED\tBIT(9)\n+#define REG_BCM6328_MISC_SB\t((void __iomem *)CKSEG1ADDR(0x10001a40))\n+#define BCM6328_FCVO_SHIFT\t7\n+#define BCM6328_FCVO_MASK\t(0x1f << BCM6328_FCVO_SHIFT)\n+\n+#define REG_BCM6358_DDR_PLLC\t((void __iomem *)0xfffe12b8)\n+#define BCM6358_PLLC_M1_SHIFT\t0\n+#define BCM6358_PLLC_M1_MASK\t(0xff << BCM6358_PLLC_M1_SHIFT)\n+#define BCM6358_PLLC_N1_SHIFT\t23\n+#define BCM6358_PLLC_N1_MASK\t(0x3f << BCM6358_PLLC_N1_SHIFT)\n+#define BCM6358_PLLC_N2_SHIFT\t29\n+#define BCM6358_PLLC_N2_MASK\t(0x7 << BCM6358_PLLC_N2_SHIFT)\n+\n+#define REG_BCM6362_MISC_SB\t((void __iomem *)CKSEG1ADDR(0x10001814))\n+#define BCM6362_FCVO_SHIFT\t1\n+#define BCM6362_FCVO_MASK\t(0x1f << BCM6362_FCVO_SHIFT)\n+\n+#define REG_BCM6368_DDR_PLLC\t((void __iomem *)CKSEG1ADDR(0x100012a0))\n+#define BCM6368_PLLC_P1_SHIFT\t0\n+#define BCM6368_PLLC_P1_MASK\t(0xf << BCM6368_PLLC_P1_SHIFT)\n+#define BCM6368_PLLC_P2_SHIFT\t4\n+#define BCM6368_PLLC_P2_MASK\t(0xf << BCM6368_PLLC_P2_SHIFT)\n+#define BCM6368_PLLC_NDIV_SHIFT\t16\n+#define BCM6368_PLLC_NDIV_MASK\t(0x1ff << BCM6368_PLLC_NDIV_SHIFT)\n+#define REG_BCM6368_DDR_PLLD\t((void __iomem *)CKSEG1ADDR(0x100012a4))\n+#define BCM6368_PLLD_MDIV_SHIFT\t0\n+#define BCM6368_PLLD_MDIV_MASK\t(0xff << BCM6368_PLLD_MDIV_SHIFT)\n+\n+#define REG_BCM63268_MISC_SB\t((void __iomem *)CKSEG1ADDR(0x10001814))\n+#define BCM63268_FCVO_SHIFT\t21\n+#define BCM63268_FCVO_MASK\t(0xf << BCM63268_FCVO_SHIFT)\n+\n \n static const unsigned long kbase = VMLINUX_LOAD_ADDRESS & 0xfff00000;\n \n+struct bmips_cpufreq {\n+\tconst char\t\t*compatible;\n+\tu32\t\t\t(*cpu_freq)(void);\n+};\n+\n struct bmips_quirk {\n \tconst char\t\t*compatible;\n \tvoid\t\t\t(*quirk_fn)(void);\n@@ -138,17 +178,161 @@ const char *get_system_type(void)\n \treturn \"Generic BMIPS kernel\";\n }\n \n+static u32 bcm6318_cpufreq(void)\n+{\n+\tu32 val = __raw_readl(REG_BCM6318_SOB);\n+\n+\tswitch ((val & BCM6318_FREQ_MASK) >> BCM6318_FREQ_SHIFT) {\n+\tcase 0:\n+\t\treturn 166000000;\n+\tcase 2:\n+\t\treturn 250000000;\n+\tcase 3:\n+\t\treturn 333000000;\n+\tcase 1:\n+\t\treturn 400000000;\n+\tdefault:\n+\t\treturn 0;\n+\t}\n+}\n+\n+static u32 bcm6328_cpufreq(void)\n+{\n+\tu32 val = __raw_readl(REG_BCM6328_MISC_SB);\n+\n+\tswitch ((val & BCM6328_FCVO_MASK) >> BCM6328_FCVO_SHIFT) {\n+\tcase 0x12:\n+\tcase 0x14:\n+\tcase 0x19:\n+\t\treturn 160000000;\n+\tcase 0x1c:\n+\t\treturn 192000000;\n+\tcase 0x13:\n+\tcase 0x15:\n+\t\treturn 200000000;\n+\tcase 0x1a:\n+\t\treturn 384000000;\n+\tcase 0x16:\n+\t\treturn 400000000;\n+\tdefault:\n+\t\treturn 320000000;\n+\t}\n+}\n+\n+static u32 bcm6358_cpufreq(void)\n+{\n+\tu32 val, n1, n2, m1;\n+\n+\tval = __raw_readl(REG_BCM6358_DDR_PLLC);\n+\tn1 = (val & BCM6358_PLLC_N1_MASK) >> BCM6358_PLLC_N1_SHIFT;\n+\tn2 = (val & BCM6358_PLLC_N2_MASK) >> BCM6358_PLLC_N2_SHIFT;\n+\tm1 = (val & BCM6358_PLLC_M1_MASK) >> BCM6358_PLLC_M1_SHIFT;\n+\n+\treturn (16 * 1000000 * n1 * n2) / m1;\n+}\n+\n+static u32 bcm6362_cpufreq(void)\n+{\n+\tu32 val = __raw_readl(REG_BCM6362_MISC_SB);\n+\n+\tswitch ((val & BCM6362_FCVO_MASK) >> BCM6362_FCVO_SHIFT) {\n+\tcase 0x04:\n+\tcase 0x0c:\n+\tcase 0x14:\n+\tcase 0x1c:\n+\t\treturn 160000000;\n+\tcase 0x15:\n+\tcase 0x1d:\n+\t\treturn 200000000;\n+\tcase 0x03:\n+\tcase 0x0b:\n+\tcase 0x13:\n+\tcase 0x1b:\n+\t\treturn 240000000;\n+\tcase 0x07:\n+\tcase 0x17:\n+\t\treturn 384000000;\n+\tcase 0x05:\n+\tcase 0x0e:\n+\tcase 0x16:\n+\tcase 0x1e:\n+\tcase 0x1f:\n+\t\treturn 400000000;\n+\tcase 0x06:\n+\t\treturn 440000000;\n+\tdefault:\n+\t\treturn 320000000;\n+\t}\n+}\n+\n+static u32 bcm6368_cpufreq(void)\n+{\n+\tu32 val, p1, p2, ndiv, m1;\n+\n+\tval = __raw_readl(REG_BCM6368_DDR_PLLC);\n+\tp1 = (val & BCM6368_PLLC_P1_MASK) >> BCM6368_PLLC_P1_SHIFT;\n+\tp2 = (val & BCM6368_PLLC_P2_MASK) >> BCM6368_PLLC_P2_SHIFT;\n+\tndiv = (val & BCM6368_PLLC_NDIV_MASK) >>\n+\t       BCM6368_PLLC_NDIV_SHIFT;\n+\n+\tval = __raw_readl(REG_BCM6368_DDR_PLLD);\n+\tm1 = (val & BCM6368_PLLD_MDIV_MASK) >> BCM6368_PLLD_MDIV_SHIFT;\n+\n+\treturn (((64 * 1000000) / p1) * p2 * ndiv) / m1;\n+}\n+\n+static u32 bcm63268_cpufreq(void)\n+{\n+\tu32 val = __raw_readl(REG_BCM63268_MISC_SB);\n+\n+\tswitch ((val & BCM63268_FCVO_MASK) >> BCM63268_FCVO_SHIFT) {\n+\tcase 0x3:\n+\tcase 0xe:\n+\t\treturn 320000000;\n+\tcase 0xa:\n+\t\treturn 333000000;\n+\tcase 0x2:\n+\tcase 0xb:\n+\tcase 0xf:\n+\t\treturn 400000000;\n+\tdefault:\n+\t\treturn 0;\n+\t}\n+}\n+\n+static const struct bmips_cpufreq bmips_cpufreq_list[] = {\n+\t{ \"brcm,bcm6318\", &bcm6318_cpufreq },\n+\t{ \"brcm,bcm6328\", &bcm6328_cpufreq },\n+\t{ \"brcm,bcm6358\", &bcm6358_cpufreq },\n+\t{ \"brcm,bcm6362\", &bcm6362_cpufreq },\n+\t{ \"brcm,bcm6368\", &bcm6368_cpufreq },\n+\t{ \"brcm,bcm63268\", &bcm63268_cpufreq },\n+\t{ /* sentinel */ }\n+};\n+\n void __init plat_time_init(void)\n {\n+\tconst struct bmips_cpufreq *cf;\n \tstruct device_node *np;\n-\tu32 freq;\n+\tu32 freq = 0;\n \n-\tnp = of_find_node_by_name(NULL, \"cpus\");\n-\tif (!np)\n-\t\tpanic(\"missing 'cpus' DT node\");\n-\tif (of_property_read_u32(np, \"mips-hpt-frequency\", &freq) < 0)\n-\t\tpanic(\"missing 'mips-hpt-frequency' property\");\n-\tof_node_put(np);\n+\tfor (cf = bmips_cpufreq_list; cf->cpu_freq; cf++) {\n+\t\tif (of_flat_dt_is_compatible(of_get_flat_dt_root(),\n+\t\t\t\t\t     cf->compatible)) {\n+\t\t\tfreq = cf->cpu_freq() / 2;\n+\t\t\tprintk(\"%s detected @ %u MHz\\n\", cf->compatible, freq / 500000);\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\n+\tif (!freq) {\n+\t\tnp = of_find_node_by_name(NULL, \"cpus\");\n+\t\tif (!np)\n+\t\t\tpanic(\"missing 'cpus' DT node\");\n+\t\tif (of_property_read_u32(np, \"mips-hpt-frequency\", &freq) < 0)\n+\t\t\tpanic(\"missing 'mips-hpt-frequency' property\");\n+\t\tof_node_put(np);\n+\t}\n \n \tmips_hpt_frequency = freq;\n }\n"
  },
  {
    "path": "target/linux/bmips/patches-5.10/201-mips-bmips-automatically-detect-RAM-size.patch",
    "content": "From f9ee3f28ecb979c77423be965ef9dd313bdb9e9b Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com>\nDate: Mon, 8 Mar 2021 16:58:34 +0100\nSubject: [PATCH 2/2] mips: bmips: automatically detect RAM size\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nSome devices have different amounts of RAM installed depending on HW revision.\n\nSigned-off-by: Álvaro Fernández Rojas <noltari@gmail.com>\n---\n arch/mips/bmips/setup.c | 118 ++++++++++++++++++++++++++++++++++++++++\n 1 file changed, 118 insertions(+)\n\n--- a/arch/mips/bmips/setup.c\n+++ b/arch/mips/bmips/setup.c\n@@ -19,6 +19,7 @@\n #include <linux/of_platform.h>\n #include <linux/libfdt.h>\n #include <linux/smp.h>\n+#include <linux/types.h>\n #include <asm/addrspace.h>\n #include <asm/bmips.h>\n #include <asm/bootinfo.h>\n@@ -34,13 +35,16 @@\n #define REG_BCM6318_SOB\t\t((void __iomem *)CKSEG1ADDR(0x10000900))\n #define BCM6318_FREQ_SHIFT\t23\n #define BCM6318_FREQ_MASK\t(0x3 << BCM6318_FREQ_SHIFT)\n+#define BCM6318_SDRAM_ADDR\t((void __iomem *)CKSEG1ADDR(0x10004000))\n \n #define REG_BCM6328_OTP\t\t((void __iomem *)CKSEG1ADDR(0x1000062c))\n #define BCM6328_TP1_DISABLED\tBIT(9)\n #define REG_BCM6328_MISC_SB\t((void __iomem *)CKSEG1ADDR(0x10001a40))\n #define BCM6328_FCVO_SHIFT\t7\n #define BCM6328_FCVO_MASK\t(0x1f << BCM6328_FCVO_SHIFT)\n+#define BCM6328_MEMC_ADDR\t((void __iomem *)CKSEG1ADDR(0x10003000))\n \n+#define BCM6358_MEMC_ADDR\t((void __iomem *)0xfffe1200)\n #define REG_BCM6358_DDR_PLLC\t((void __iomem *)0xfffe12b8)\n #define BCM6358_PLLC_M1_SHIFT\t0\n #define BCM6358_PLLC_M1_MASK\t(0xff << BCM6358_PLLC_M1_SHIFT)\n@@ -52,7 +56,9 @@\n #define REG_BCM6362_MISC_SB\t((void __iomem *)CKSEG1ADDR(0x10001814))\n #define BCM6362_FCVO_SHIFT\t1\n #define BCM6362_FCVO_MASK\t(0x1f << BCM6362_FCVO_SHIFT)\n+#define BCM6362_MEMC_ADDR\t((void __iomem *)CKSEG1ADDR(0x10003000))\n \n+#define BCM6368_MEMC_ADDR\t((void __iomem *)CKSEG1ADDR(0x10001200))\n #define REG_BCM6368_DDR_PLLC\t((void __iomem *)CKSEG1ADDR(0x100012a0))\n #define BCM6368_PLLC_P1_SHIFT\t0\n #define BCM6368_PLLC_P1_MASK\t(0xf << BCM6368_PLLC_P1_SHIFT)\n@@ -67,7 +73,21 @@\n #define REG_BCM63268_MISC_SB\t((void __iomem *)CKSEG1ADDR(0x10001814))\n #define BCM63268_FCVO_SHIFT\t21\n #define BCM63268_FCVO_MASK\t(0xf << BCM63268_FCVO_SHIFT)\n+#define BCM63268_MEMC_ADDR\t((void __iomem *)CKSEG1ADDR(0x10003000))\n \n+#define SDRAM_CFG_REG\t\t0x0\n+#define SDRAM_SPACE_SHIFT\t4\n+#define SDRAM_SPACE_MASK\t(0xf << SDRAM_SPACE_SHIFT)\n+\n+#define MEMC_CFG_REG\t\t0x4\n+#define MEMC_CFG_32B_SHIFT\t1\n+#define MEMC_CFG_32B_MASK\t(1 << MEMC_CFG_32B_SHIFT)\n+#define MEMC_CFG_COL_SHIFT\t3\n+#define MEMC_CFG_COL_MASK\t(0x3 << MEMC_CFG_COL_SHIFT)\n+#define MEMC_CFG_ROW_SHIFT\t6\n+#define MEMC_CFG_ROW_MASK\t(0x3 << MEMC_CFG_ROW_SHIFT)\n+\n+#define DDR_CSEND_REG\t\t0x8\n \n static const unsigned long kbase = VMLINUX_LOAD_ADDRESS & 0xfff00000;\n \n@@ -76,6 +96,11 @@ struct bmips_cpufreq {\n \tu32\t\t\t(*cpu_freq)(void);\n };\n \n+struct bmips_memsize {\n+\tconst char\t\t*compatible;\n+\tphys_addr_t\t\t(*mem_size)(void);\n+};\n+\n struct bmips_quirk {\n \tconst char\t\t*compatible;\n \tvoid\t\t\t(*quirk_fn)(void);\n@@ -337,9 +362,90 @@ void __init plat_time_init(void)\n \tmips_hpt_frequency = freq;\n }\n \n+static inline phys_addr_t bmips_dram_size(unsigned int cols,\n+\t\t\t\t\t  unsigned int rows,\n+\t\t\t\t\t  unsigned int is_32b,\n+\t\t\t\t\t  unsigned int banks)\n+{\n+\trows += 11; /* 0 => 11 address bits ... 2 => 13 address bits */\n+\tcols += 8; /* 0 => 8 address bits ... 2 => 10 address bits */\n+\tis_32b += 1;\n+\n+\treturn 1 << (cols + rows + is_32b + banks);\n+}\n+\n+static phys_addr_t _bcm6318_memsize(void __iomem *addr)\n+{\n+\tu32 val;\n+\n+\tval = __raw_readl(addr + SDRAM_CFG_REG);\n+\tval = (val & SDRAM_SPACE_MASK) >> SDRAM_SPACE_SHIFT;\n+\n+\treturn (1 << (val + 20));\n+}\n+\n+static phys_addr_t _bcm6328_memsize(void __iomem *addr)\n+{\n+\treturn __raw_readl(addr + DDR_CSEND_REG) << 24;\n+}\n+\n+static phys_addr_t _bcm6358_memsize(void __iomem *addr)\n+{\n+\tunsigned int cols, rows, is_32b;\n+\tu32 val;\n+\n+\tval = __raw_readl(addr + MEMC_CFG_REG);\n+\trows = (val & MEMC_CFG_ROW_MASK) >> MEMC_CFG_ROW_SHIFT;\n+\tcols = (val & MEMC_CFG_COL_MASK) >> MEMC_CFG_COL_SHIFT;\n+\tis_32b = (val & MEMC_CFG_32B_MASK) ? 0 : 1;\n+\n+\treturn bmips_dram_size(cols, rows, is_32b, 2);\n+}\n+\n+static phys_addr_t bcm6318_memsize(void)\n+{\n+\treturn _bcm6318_memsize(BCM6318_SDRAM_ADDR);\n+}\n+\n+static phys_addr_t bcm6328_memsize(void)\n+{\n+\treturn _bcm6328_memsize(BCM6328_MEMC_ADDR);\n+}\n+\n+static phys_addr_t bcm6358_memsize(void)\n+{\n+\treturn _bcm6358_memsize(BCM6358_MEMC_ADDR);\n+}\n+\n+static phys_addr_t bcm6362_memsize(void)\n+{\n+\treturn _bcm6328_memsize(BCM6362_MEMC_ADDR);\n+}\n+\n+static phys_addr_t bcm6368_memsize(void)\n+{\n+\treturn _bcm6358_memsize(BCM6368_MEMC_ADDR);\n+}\n+\n+static phys_addr_t bcm63268_memsize(void)\n+{\n+\treturn _bcm6328_memsize(BCM63268_MEMC_ADDR);\n+}\n+\n+static const struct bmips_memsize bmips_memsize_list[] = {\n+\t{ \"brcm,bcm6318\", &bcm6318_memsize },\n+\t{ \"brcm,bcm6328\", &bcm6328_memsize },\n+\t{ \"brcm,bcm6358\", &bcm6358_memsize },\n+\t{ \"brcm,bcm6362\", &bcm6362_memsize },\n+\t{ \"brcm,bcm6368\", &bcm6368_memsize },\n+\t{ \"brcm,bcm63268\", &bcm63268_memsize },\n+\t{ /* sentinel */ }\n+};\n+\n void __init plat_mem_setup(void)\n {\n \tvoid *dtb;\n+\tconst struct bmips_memsize *ms;\n \tconst struct bmips_quirk *q;\n \n \tset_io_port_base(0);\n@@ -358,6 +464,18 @@ void __init plat_mem_setup(void)\n \n \t__dt_setup_arch(dtb);\n \n+\tfor (ms = bmips_memsize_list; ms->mem_size; ms++) {\n+\t\tif (of_flat_dt_is_compatible(of_get_flat_dt_root(),\n+\t\t\t\t\t     ms->compatible)) {\n+\t\t\tphys_addr_t mem = ms->mem_size();\n+\t\t\tif (mem) {\n+\t\t\t\tmemblock_add(0, mem);\n+\t\t\t\tprintk(\"%uMB of RAM installed\\n\", mem >> 20);\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t}\n+\t}\n+\n \tfor (q = bmips_quirk_list; q->quirk_fn; q++) {\n \t\tif (of_flat_dt_is_compatible(of_get_flat_dt_root(),\n \t\t\t\t\t     q->compatible)) {\n"
  },
  {
    "path": "target/linux/bmips/patches-5.10/202-mips-bmips-disable-ARCH_HAS_SYNC_DMA_FOR_CPU_ALL.patch",
    "content": "From 84c06b4a1dfa3e021fdbcafaff8cebfdec462402 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com>\nDate: Tue, 23 Feb 2021 10:39:48 +0100\nSubject: [PATCH] mips: bmips: disable ARCH_HAS_SYNC_DMA_FOR_CPU_ALL\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nEnabling this option causes kernel panics on BCM6358 with EHCI/OHCI:\n[    3.881739] usb 1-1: new high-speed USB device number 2 using ehci-platform\n[    3.895011] Reserved instruction in kernel code[#1]:\n[    3.900113] CPU: 0 PID: 1 Comm: init Not tainted 5.10.16 #0\n[    3.905829] $ 0   : 00000000 10008700 00000000 77d94060\n[    3.911238] $ 4   : 7fd1f088 00000000 81431cac 81431ca0\n[    3.916641] $ 8   : 00000000 ffffefff 8075cd34 00000000\n[    3.922043] $12   : 806f8d40 f3e812b7 00000000 000d9aaa\n[    3.927446] $16   : 7fd1f068 7fd1f080 7ff559b8 81428470\n[    3.932848] $20   : 00000000 00000000 55590000 77d70000\n[    3.938251] $24   : 00000018 00000010\n[    3.943655] $28   : 81430000 81431e60 81431f28 800157fc\n[    3.949058] Hi    : 00000000\n[    3.952013] Lo    : 00000000\n[    3.955019] epc   : 80015808 setup_sigcontext+0x54/0x24c\n[    3.960464] ra    : 800157fc setup_sigcontext+0x48/0x24c\n[    3.965913] Status: 10008703\tKERNEL EXL IE\n[    3.970216] Cause : 00800028 (ExcCode 0a)\n[    3.974340] PrId  : 0002a010 (Broadcom BMIPS4350)\n[    3.979170] Modules linked in: ohci_platform ohci_hcd fsl_mph_dr_of ehci_platform ehci_fsl ehci_hcd gpio_button_hotplug usbcore nls_base usb_common\n[    3.992907] Process init (pid: 1, threadinfo=(ptrval), task=(ptrval), tls=77e22ec8)\n[    4.000776] Stack : 81431ef4 7fd1f080 81431f28 81428470 7fd1f068 81431edc 7ff559b8 81428470\n[    4.009467]         81431f28 7fd1f080 55590000 77d70000 77d5498c 80015c70 806f0000 8063ae74\n[    4.018149]         08100002 81431f28 0000000a 08100002 81431f28 0000000a 77d6b418 00000003\n[    4.026831]         ffffffff 80016414 80080734 81431ecc 81431ecc 00000001 00000000 04000000\n[    4.035512]         77d54874 00000000 00000000 00000000 00000000 00000012 00000002 00000000\n[    4.044196]         ...\n[    4.046706] Call Trace:\n[    4.049238] [<80015808>] setup_sigcontext+0x54/0x24c\n[    4.054356] [<80015c70>] setup_frame+0xdc/0x124\n[    4.059015] [<80016414>] do_notify_resume+0x1dc/0x288\n[    4.064207] [<80011b50>] work_notifysig+0x10/0x18\n[    4.069036]\n[    4.070538] Code: 8fc300b4  00001025  26240008 <ac820000> ac830004  3c048063  0c0228aa  24846a00  26240010\n[    4.080686]\n[    4.082517] ---[ end trace 22a8edb41f5f983b ]---\n[    4.087374] Kernel panic - not syncing: Fatal exception\n[    4.092753] Rebooting in 1 seconds..\n\nSigned-off-by: Álvaro Fernández Rojas <noltari@gmail.com>\n---\n arch/mips/Kconfig | 1 -\n 1 file changed, 1 deletion(-)\n\n--- a/arch/mips/Kconfig\n+++ b/arch/mips/Kconfig\n@@ -253,7 +253,6 @@ config ATH79\n config BMIPS_GENERIC\n \tbool \"Broadcom Generic BMIPS kernel\"\n \tselect ARCH_HAS_RESET_CONTROLLER\n-\tselect ARCH_HAS_SYNC_DMA_FOR_CPU_ALL\n \tselect ARCH_HAS_PHYS_TO_DMA\n \tselect BOOT_RAW\n \tselect NO_EXCEPT_FILL\n"
  },
  {
    "path": "target/linux/bmips/patches-5.10/500-net-broadcom-add-BCM6368-enetsw-controller-driver.patch",
    "content": "From 590b60fb08cb1e70fe02d3f407c6b3dbe9ad06ff Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com>\nDate: Mon, 1 Mar 2021 07:34:39 +0100\nSubject: [PATCH 3/4] net: broadcom: add BCM6368 enetsw controller driver\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nThis controller is present on BCM6318, BCM6328, BCM6362, BCM6368 and BCM63268\nSoCs.\n\nSigned-off-by: Álvaro Fernández Rojas <noltari@gmail.com>\n---\n drivers/net/ethernet/broadcom/Kconfig         |    8 +\n drivers/net/ethernet/broadcom/Makefile        |    1 +\n .../net/ethernet/broadcom/bcm6368-enetsw.c    | 1111 +++++++++++++++++\n 3 files changed, 1120 insertions(+)\n create mode 100644 drivers/net/ethernet/broadcom/bcm6368-enetsw.c\n\n--- a/drivers/net/ethernet/broadcom/Kconfig\n+++ b/drivers/net/ethernet/broadcom/Kconfig\n@@ -60,6 +60,14 @@ config BCM63XX_ENET\n \t  This driver supports the ethernet MACs in the Broadcom 63xx\n \t  MIPS chipset family (BCM63XX).\n \n+config BCM6368_ENETSW\n+\ttristate \"Broadcom BCM6368 internal mac support\"\n+\tdepends on BMIPS_GENERIC || COMPILE_TEST\n+\tdefault y\n+\thelp\n+\t  This driver supports Ethernet controller integrated into Broadcom\n+\t  BCM6368 family SoCs.\n+\n config BCMGENET\n \ttristate \"Broadcom GENET internal MAC support\"\n \tdepends on HAS_IOMEM\n--- a/drivers/net/ethernet/broadcom/Makefile\n+++ b/drivers/net/ethernet/broadcom/Makefile\n@@ -5,6 +5,7 @@\n \n obj-$(CONFIG_B44) += b44.o\n obj-$(CONFIG_BCM63XX_ENET) += bcm63xx_enet.o\n+obj-$(CONFIG_BCM6368_ENETSW) += bcm6368-enetsw.o\n obj-$(CONFIG_BCMGENET) += genet/\n obj-$(CONFIG_BNX2) += bnx2.o\n obj-$(CONFIG_CNIC) += cnic.o\n"
  },
  {
    "path": "target/linux/bmips/patches-5.10/510-net-dsa-b53-add-support-for-BCM63xx-RGMIIs.patch",
    "content": "From 32cf73d8c6485b7b97aca7e377a68436d09b7022 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com>\nDate: Sun, 14 Mar 2021 20:03:44 +0100\nSubject: [PATCH] net: dsa: b53: add support for BCM63xx RGMIIs\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nSigned-off-by: Álvaro Fernández Rojas <noltari@gmail.com>\n---\n drivers/net/dsa/b53/b53_common.c | 37 ++++++++++++++++++++++++++++++++\n 1 file changed, 37 insertions(+)\n\n--- a/drivers/net/dsa/b53/b53_common.c\n+++ b/drivers/net/dsa/b53/b53_common.c\n@@ -1174,6 +1174,36 @@ static void b53_force_port_config(struct\n \tb53_write8(dev, B53_CTRL_PAGE, off, reg);\n }\n \n+static void b53_adjust_63xx_rgmii(struct dsa_switch *ds, int port,\n+\t\t\t\t  phy_interface_t interface)\n+{\n+\tstruct b53_device *dev = ds->priv;\n+\tu8 rgmii_ctrl = 0, off;\n+\n+\tif (port == 8)\n+\t\toff = B53_RGMII_CTRL_IMP;\n+\telse\n+\t\toff = B53_RGMII_CTRL_P(port);\n+\n+\tb53_read8(dev, B53_CTRL_PAGE, off, &rgmii_ctrl);\n+\n+\trgmii_ctrl &= ~(RGMII_CTRL_DLL_RXC | RGMII_CTRL_DLL_TXC);\n+\tif (interface == PHY_INTERFACE_MODE_RGMII_ID)\n+\t\trgmii_ctrl |= (RGMII_CTRL_DLL_RXC | RGMII_CTRL_DLL_TXC);\n+\telse if (interface == PHY_INTERFACE_MODE_RGMII_RXID)\n+\t\trgmii_ctrl |= RGMII_CTRL_DLL_RXC;\n+\telse if (interface == PHY_INTERFACE_MODE_RGMII_TXID)\n+\t\trgmii_ctrl |= RGMII_CTRL_DLL_TXC;\n+\n+\tif (port != B53_CPU_PORT)\n+\t\trgmii_ctrl |= RGMII_CTRL_ENABLE_GMII;\n+\n+\tb53_write8(dev, B53_CTRL_PAGE, off, rgmii_ctrl);\n+\n+\tdev_info(ds->dev, \"Configured port %d for %s\\n\", port,\n+\t\t phy_modes(interface));\n+}\n+\n static void b53_adjust_link(struct dsa_switch *ds, int port,\n \t\t\t    struct phy_device *phydev)\n {\n@@ -1200,6 +1230,9 @@ static void b53_adjust_link(struct dsa_s\n \t\t\t      tx_pause, rx_pause);\n \tb53_force_link(dev, port, phydev->link);\n \n+\tif (is63xx(dev))\n+\t\tb53_adjust_63xx_rgmii(ds, port, phydev->interface);\n+\n \tif (is531x5(dev) && phy_interface_is_rgmii(phydev)) {\n \t\tif (port == dev->imp_port)\n \t\t\toff = B53_RGMII_CTRL_IMP;\n@@ -1386,6 +1419,9 @@ void b53_phylink_mac_link_up(struct dsa_\n {\n \tstruct b53_device *dev = ds->priv;\n \n+\tif (is63xx(dev) && port >= 4)\n+\t\tb53_adjust_63xx_rgmii(ds, port, interface);\n+\n \tif (mode == MLO_AN_PHY)\n \t\treturn;\n \n"
  },
  {
    "path": "target/linux/bmips/patches-5.10/600-mips-bmips-add-pci-support.patch",
    "content": "--- a/arch/mips/Kconfig\n+++ b/arch/mips/Kconfig\n@@ -265,6 +265,7 @@ config BMIPS_GENERIC\n \tselect BCM7038_L1_IRQ\n \tselect BCM7120_L2_IRQ\n \tselect BRCMSTB_L2_IRQ\n+\tselect HAVE_PCI\n \tselect IRQ_MIPS_CPU\n \tselect DMA_NONCOHERENT\n \tselect SYS_SUPPORTS_32BIT_KERNEL\n--- a/arch/mips/pci/Makefile\n+++ b/arch/mips/pci/Makefile\n@@ -28,6 +28,7 @@ obj-$(CONFIG_PCI_XTALK_BRIDGE)\t+= pci-xt\n # These are still pretty much in the old state, watch, go blind.\n #\n obj-$(CONFIG_ATH79)\t\t+= fixup-ath79.o\n+obj-$(CONFIG_BMIPS_GENERIC)\t+= fixup-bmips.o\n obj-$(CONFIG_MIPS_COBALT)\t+= fixup-cobalt.o\n obj-$(CONFIG_LEMOTE_FULOONG2E)\t+= fixup-fuloong2e.o ops-loongson2.o\n obj-$(CONFIG_LEMOTE_MACH2F)\t+= fixup-lemote2f.o ops-loongson2.o\n"
  },
  {
    "path": "target/linux/bmips/patches-5.10/601-pci-controllers-add-bcm6328-pcie-support.patch",
    "content": "--- a/drivers/pci/controller/Kconfig\n+++ b/drivers/pci/controller/Kconfig\n@@ -3,6 +3,11 @@\n menu \"PCI controller drivers\"\n \tdepends on PCI\n \n+config PCIE_BCM6328\n+\tbool \"BCM6328 PCIe controller\"\n+\tdepends on BMIPS_GENERIC || COMPILE_TEST\n+\tdepends on OF\n+\n config PCI_MVEBU\n \tbool \"Marvell EBU PCIe controller\"\n \tdepends on ARCH_MVEBU || ARCH_DOVE || COMPILE_TEST\n--- a/drivers/pci/controller/Makefile\n+++ b/drivers/pci/controller/Makefile\n@@ -1,4 +1,5 @@\n # SPDX-License-Identifier: GPL-2.0\n+obj-$(CONFIG_PCIE_BCM6328) += pcie-bcm6328.o\n obj-$(CONFIG_PCIE_CADENCE) += cadence/\n obj-$(CONFIG_PCI_FTPCI100) += pci-ftpci100.o\n obj-$(CONFIG_PCI_HYPERV) += pci-hyperv.o\n"
  },
  {
    "path": "target/linux/bmips/patches-5.10/602-pci-controllers-add-bcm6318-pcie-support.patch",
    "content": "--- a/drivers/pci/controller/Kconfig\n+++ b/drivers/pci/controller/Kconfig\n@@ -3,6 +3,11 @@\n menu \"PCI controller drivers\"\n \tdepends on PCI\n \n+config PCIE_BCM6318\n+\tbool \"BCM6318 PCIe controller\"\n+\tdepends on BMIPS_GENERIC || COMPILE_TEST\n+\tdepends on OF\n+\n config PCIE_BCM6328\n \tbool \"BCM6328 PCIe controller\"\n \tdepends on BMIPS_GENERIC || COMPILE_TEST\n--- a/drivers/pci/controller/Makefile\n+++ b/drivers/pci/controller/Makefile\n@@ -1,4 +1,5 @@\n # SPDX-License-Identifier: GPL-2.0\n+obj-$(CONFIG_PCIE_BCM6318) += pcie-bcm6318.o\n obj-$(CONFIG_PCIE_BCM6328) += pcie-bcm6328.o\n obj-$(CONFIG_PCIE_CADENCE) += cadence/\n obj-$(CONFIG_PCI_FTPCI100) += pci-ftpci100.o\n"
  },
  {
    "path": "target/linux/bmips/patches-5.10/603-pci-controllers-add-bcm6348-pci-support.patch",
    "content": "--- a/drivers/pci/controller/Kconfig\n+++ b/drivers/pci/controller/Kconfig\n@@ -3,6 +3,11 @@\n menu \"PCI controller drivers\"\n \tdepends on PCI\n \n+config PCI_BCM6348\n+\tbool \"BCM6348 PCI controller\"\n+\tdepends on BMIPS_GENERIC || COMPILE_TEST\n+\tdepends on OF\n+\n config PCIE_BCM6318\n \tbool \"BCM6318 PCIe controller\"\n \tdepends on BMIPS_GENERIC || COMPILE_TEST\n--- a/drivers/pci/controller/Makefile\n+++ b/drivers/pci/controller/Makefile\n@@ -1,4 +1,5 @@\n # SPDX-License-Identifier: GPL-2.0\n+obj-$(CONFIG_PCI_BCM6348) += pci-bcm6348.o\n obj-$(CONFIG_PCIE_BCM6318) += pcie-bcm6318.o\n obj-$(CONFIG_PCIE_BCM6328) += pcie-bcm6328.o\n obj-$(CONFIG_PCIE_CADENCE) += cadence/\n"
  },
  {
    "path": "target/linux/bmips/patches-5.10/610-mips-bmips-add-pci-fixups.patch",
    "content": "--- a/arch/mips/bmips/Makefile\n+++ b/arch/mips/bmips/Makefile\n@@ -1,2 +1,3 @@\n # SPDX-License-Identifier: GPL-2.0-only\n obj-y\t\t+= setup.o irq.o dma.o\n+obj-y\t\t+= ath9k-fixup.o b43-sprom.o\n"
  },
  {
    "path": "target/linux/bmips/patches-5.10/800-jffs2-work-around-unaligned-accesses-failing-on-bcm6.patch",
    "content": "From ff3409ab17d56450943364ba49a16960e3cdda9b Mon Sep 17 00:00:00 2001\nFrom: Jonas Gorski <jogo@openwrt.org>\nDate: Sun, 6 Apr 2014 22:33:16 +0200\nSubject: [RFC] jffs2: work around unaligned accesses failing on bcm63xx/smp\n\nUnligned memcpy_fromio randomly fails with an unaligned dst. Work around\nit by ensuring we are always doing aligned copies.\n\nShould fix filename corruption in jffs2 with SMP.\n\nSigned-off-by: Jonas Gorski <jogo@openwrt.org>\n---\n fs/jffs2/nodelist.h | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/fs/jffs2/nodelist.h\n+++ b/fs/jffs2/nodelist.h\n@@ -259,7 +259,7 @@ struct jffs2_full_dirent\n \tuint32_t ino; /* == zero for unlink */\n \tunsigned int nhash;\n \tunsigned char type;\n-\tunsigned char name[];\n+\tunsigned char name[] __attribute__((aligned((sizeof(long)))));\n };\n \n /*\n"
  },
  {
    "path": "target/linux/bmips/profiles/default.mk",
    "content": "define Profile/Default\n  NAME:=Default Profile\n  PRIORITY:=1\nendef\n\ndefine Profile/Default/Description\n  Default package set compatible with most boards.\nendef\n\n$(eval $(call Profile,Default))\n"
  },
  {
    "path": "target/linux/gemini/Makefile",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2009-2018 OpenWrt.org\n\ninclude $(TOPDIR)/rules.mk\n\nARCH:=arm\nBOARD:=gemini\nBOARDNAME:=Cortina Systems CS351x\nFEATURES:=squashfs pci rtc usb dt gpio display ext4 rootfs-part boot-part\nCPU_TYPE:=fa526\n\nKERNEL_PATCHVER:=5.15\n\ndefine Target/Description\n\tBuild firmware images for the StorLink/Cortina Gemini CS351x ARM FA526 CPU\nendef\n\nKERNELNAME:=zImage dtbs\n\ninclude $(INCLUDE_DIR)/target.mk\n\nDEFAULT_PACKAGES += \\\n\tkmod-usb-fotg210 \\\n\tkmod-usb-ledtrig-usbport \\\n\tkmod-leds-gpio \\\n\tkmod-gpio-button-hotplug\n\n$(eval $(call BuildTarget))\n"
  },
  {
    "path": "target/linux/gemini/base-files/etc/board.d/02_network",
    "content": "\n. /lib/functions/uci-defaults.sh\n\nboard_config_update\n\ncase \"$(board_name)\" in\ndlink,dir-685)\n\t# These are all connected to eth0 thru RTL8366RB\n\tucidef_set_interface \"eth\" device \"eth0\" protocol \"none\"\n\tucidef_set_interfaces_lan_wan \"lan0 lan1 lan2 lan3\" \"wan\"\n\t;;\nitian,sq201)\n\t# These are all connected to eth1 thru VSC7395\n\tucidef_set_interface \"eth\" device \"eth1\" protocol \"none\"\n\tucidef_set_interfaces_lan_wan \"lan1 lan2 lan3 lan4\" \"eth0\"\n\t;;\nstorlink,gemini324)\n\t# These are all connected to eth1 thru VSC7385\n\tucidef_set_interface \"eth\" device \"eth1\" protocol \"none\"\n\tucidef_set_interfaces_lan_wan \"lan1 lan2 lan3 lan4\" \"eth0\"\n\t;;\nesac\n\nboard_config_flush\n\nexit 0\n"
  },
  {
    "path": "target/linux/gemini/base-files/etc/board.d/03_hdparm",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n# Spin down drives after one minute if inactive\n\nif [ ! -n \"$(command -v hdparm)\" ]; then\n\texit 0\nfi\n\nDISKS=$(find /dev/sd[a-z] 2>/dev/null)\nfor DISK in $DISKS\ndo\n\tif [ -b $DISK ] ; then\n\t\thdparm -S 12 $DISK > /dev/null\n\tfi\ndone\n"
  },
  {
    "path": "target/linux/gemini/base-files/etc/board.d/03_splash",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n# OpenWRT splash screen if using framebuffer console\n\nif [ ! -d /sys/class/graphics/fbcon ] ; then\n\texit 0\nfi\n\necho 0 > /sys/class/graphics/fbcon/cursor_blink\ncat /etc/banner > /dev/tty0\n"
  },
  {
    "path": "target/linux/gemini/base-files/etc/uci-defaults/09_fix-checksum",
    "content": "#\n# Copyright (C) 2019 OpenWrt.org\n#\n\n. /lib/functions.sh\n\nboard=$(board_name)\n\nfixwrgg() {\n\tlocal kernel_size=$(sed -n 's/mtd[0-9]*: \\([0-9a-f]*\\).*\"kernel\".*/\\1/p' /proc/mtd)\n\n\t[ \"$kernel_size\" ] && mtd -c 0x$kernel_size fixwrgg firmware\n}\n\ncase \"$board\" in\ndlink,dir-685)\n\tfixwrgg\n\t;;\nesac\n"
  },
  {
    "path": "target/linux/gemini/base-files/lib/preinit/05_set_ether_mac_gemini",
    "content": ". /lib/functions.sh\n. /lib/functions/system.sh\n\nset_ether_mac() {\n\tlocal part\n\tlocal DEVID\n\tlocal MAC1\n\tlocal MAC2\n\n\tcase \"$(board_name)\" in\n\tdlink,dns-313)\n\t\t# The DNS-313 has a special field in its RedBoot\n\t\t# binary that we need to check\n\t\tpart=\"$(find_mtd_part RedBoot)\"\n\t\tif [ -n \"$part\" ]; then\n\t\t\tDEVID=\"$(dd if=$part bs=1 skip=119508 count=7 2>/dev/null)\"\n\t\t\tif [ \"$DEVID\" = \"dns-313\" ]; then\n\t\t\t\tMAC1=\"$(mtd_get_mac_binary RedBoot 0x1d2f4)\"\n\t\t\t\tip link set eth0 address \"$MAC1\" 2>/dev/null\n\t\t\t\treturn 0\n\t\t\tfi\n\t\tfi\n\t\t;;\n\tdlink,dir-685)\n\t\t# The DIR-685 has a special field in its RedBoot\n\t\t# binary that we need to check\n\t\tpart=$(find_mtd_part RedBoot)\n\t\tif [ -n \"$part\" ] ; then\n\t\t\tDEVID=\"$(dd if=$part bs=1 skip=81516 count=7 2>/dev/null)\"\n\t\t\tif [ \"$DEVID\" = \"ILI9322\" ] ; then\n\t\t\t\tMAC1=$(mtd_get_mac_binary RedBoot 0x17340)\n\t\t\t\tMAC2=$(mtd_get_mac_binary RedBoot 0x17346)\n\t\t\t\tip link set eth0 address \"$MAC1\" 2>/dev/null\n\t\t\t\tip link set eth1 address \"$MAC2\" 2>/dev/null\n\t\t\t\treturn 0\n\t\t\tfi\n\t\tfi\n\t\t;;\n\tesac\n\n\t# Most devices have a standard \"VCTL\" partition\n\tpart=\"$(find_mtd_part VCTL)\"\n\tif [ -n \"$part\" ]; then\n\t\tMAC1=\"$(strings $part |grep MAC|cut -d: -f2|cut -c3-14|sed -e 's,\\(..\\),:\\1,g' -e 's,^:,,')\"\n\t\tMAC2=\"$(strings $part |grep MAC|cut -d: -f8|cut -c3-14|sed -e 's,\\(..\\),:\\1,g' -e 's,^:,,')\"\n\n\t\tip link set eth0 address \"$MAC1\" 2>/dev/null\n\t\tip link set eth1 address \"$MAC2\" 2>/dev/null\n\t\treturn 0\n\tfi\n}\n\nboot_hook_add preinit_main set_ether_mac\n"
  },
  {
    "path": "target/linux/gemini/base-files/lib/upgrade/platform.sh",
    "content": "REQUIRE_IMAGE_METADATA=1\n\nplatform_check_image() {\n\tlocal board=$(board_name)\n\n\tcase \"$board\" in\n\tdlink,dir-685)\n\t\treturn 0\n\t\t;;\n\tesac\n\n\techo \"Sysupgrade is not yet supported on $board.\"\n\treturn 1\n}\n\nplatform_do_upgrade() {\n\tlocal board=$(board_name)\n\n\tcase \"$board\" in\n\tdlink,dir-685)\n\t\tPART_NAME=firmware\n\t\tdefault_do_upgrade \"$1\"\n\t\t;;\n\tesac\n}\n"
  },
  {
    "path": "target/linux/gemini/config-5.10",
    "content": "CONFIG_ALIGNMENT_TRAP=y\nCONFIG_AMBA_PL08X=y\nCONFIG_ARCH_32BIT_OFF_T=y\nCONFIG_ARCH_GEMINI=y\nCONFIG_ARCH_KEEP_MEMBLOCK=y\nCONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y\n# CONFIG_ARCH_MOXART is not set\nCONFIG_ARCH_MULTIPLATFORM=y\nCONFIG_ARCH_MULTI_V4=y\n# CONFIG_ARCH_MULTI_V4T is not set\nCONFIG_ARCH_MULTI_V4_V5=y\n# CONFIG_ARCH_MULTI_V5 is not set\nCONFIG_ARCH_NR_GPIO=0\nCONFIG_ARCH_OPTIONAL_KERNEL_RWX=y\nCONFIG_ARCH_SELECT_MEMORY_MODEL=y\nCONFIG_ARCH_SPARSEMEM_ENABLE=y\nCONFIG_ARM=y\nCONFIG_ARM_AMBA=y\nCONFIG_ARM_APPENDED_DTB=y\n# CONFIG_ARM_ATAG_DTB_COMPAT is not set\nCONFIG_ARM_HAS_SG_CHAIN=y\nCONFIG_ARM_L1_CACHE_SHIFT=5\nCONFIG_ARM_PATCH_PHYS_VIRT=y\n# CONFIG_ARM_SMMU is not set\nCONFIG_ARM_UNWIND=y\nCONFIG_ATA=y\nCONFIG_ATAGS=y\nCONFIG_ATA_FORCE=y\nCONFIG_ATA_VERBOSE_ERROR=y\nCONFIG_AUTO_ZRELADDR=y\nCONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y\nCONFIG_BLK_DEV_SD=y\nCONFIG_BLK_MQ_PCI=y\nCONFIG_BLK_PM=y\nCONFIG_BLK_SCSI_REQUEST=y\nCONFIG_BOUNCE=y\nCONFIG_CLKDEV_LOOKUP=y\nCONFIG_CLKSRC_MMIO=y\nCONFIG_CLONE_BACKWARDS=y\nCONFIG_CMA=y\nCONFIG_CMA_ALIGNMENT=8\nCONFIG_CMA_AREAS=7\n# CONFIG_CMA_DEBUG is not set\n# CONFIG_CMA_DEBUGFS is not set\nCONFIG_CMA_SIZE_PERCENTAGE=10\n# CONFIG_CMA_SIZE_SEL_MAX is not set\n# CONFIG_CMA_SIZE_SEL_MBYTES is not set\n# CONFIG_CMA_SIZE_SEL_MIN is not set\nCONFIG_CMA_SIZE_SEL_PERCENTAGE=y\nCONFIG_COMMON_CLK=y\nCONFIG_COMMON_CLK_GEMINI=y\nCONFIG_COMPAT_32BIT_TIME=y\nCONFIG_CONSOLE_TRANSLATIONS=y\nCONFIG_CONTIG_ALLOC=y\nCONFIG_COREDUMP=y\nCONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y\nCONFIG_CPU_32v4=y\nCONFIG_CPU_ABRT_EV4=y\nCONFIG_CPU_CACHE_FA=y\nCONFIG_CPU_CACHE_VIVT=y\nCONFIG_CPU_COPY_FA=y\nCONFIG_CPU_CP15=y\nCONFIG_CPU_CP15_MMU=y\n# CONFIG_CPU_DCACHE_WRITETHROUGH is not set\nCONFIG_CPU_FA526=y\nCONFIG_CPU_NO_EFFICIENT_FFS=y\nCONFIG_CPU_PABRT_LEGACY=y\nCONFIG_CPU_THERMAL=y\nCONFIG_CPU_TLB_FA=y\nCONFIG_CPU_USE_DOMAINS=y\nCONFIG_CRASH_CORE=y\nCONFIG_CRC16=y\n# CONFIG_CRC32_SARWATE is not set\nCONFIG_CRC32_SLICEBY8=y\nCONFIG_CRC_CCITT=y\nCONFIG_CRC_ITU_T=y\nCONFIG_CROSS_MEMORY_ATTACH=y\nCONFIG_CRYPTO_CCM=y\nCONFIG_CRYPTO_CMAC=y\nCONFIG_CRYPTO_CRC32C=y\nCONFIG_CRYPTO_CTR=y\nCONFIG_CRYPTO_DES=y\nCONFIG_CRYPTO_DRBG=y\nCONFIG_CRYPTO_DRBG_HMAC=y\nCONFIG_CRYPTO_DRBG_MENU=y\nCONFIG_CRYPTO_ECB=y\nCONFIG_CRYPTO_ECHAINIV=y\nCONFIG_CRYPTO_GCM=y\nCONFIG_CRYPTO_HMAC=y\nCONFIG_CRYPTO_HW=y\nCONFIG_CRYPTO_JITTERENTROPY=y\nCONFIG_CRYPTO_LIB_DES=y\nCONFIG_CRYPTO_LIB_SHA256=y\nCONFIG_CRYPTO_MD4=y\nCONFIG_CRYPTO_MD5=y\nCONFIG_CRYPTO_NULL=y\nCONFIG_CRYPTO_RNG=y\nCONFIG_CRYPTO_RNG2=y\nCONFIG_CRYPTO_RNG_DEFAULT=y\nCONFIG_CRYPTO_SEQIV=y\nCONFIG_CRYPTO_SHA256=y\nCONFIG_DEBUG_BUGVERBOSE=y\nCONFIG_DEBUG_LL_INCLUDE=\"mach/debug-macro.S\"\nCONFIG_DEBUG_MEMORY_INIT=y\nCONFIG_DECOMPRESS_BZIP2=y\nCONFIG_DECOMPRESS_GZIP=y\nCONFIG_DECOMPRESS_LZ4=y\nCONFIG_DECOMPRESS_LZMA=y\nCONFIG_DECOMPRESS_LZO=y\nCONFIG_DECOMPRESS_XZ=y\nCONFIG_DMADEVICES=y\nCONFIG_DMATEST=y\nCONFIG_DMA_CMA=y\nCONFIG_DMA_ENGINE=y\nCONFIG_DMA_ENGINE_RAID=y\nCONFIG_DMA_OF=y\nCONFIG_DMA_OPS=y\nCONFIG_DMA_REMAP=y\nCONFIG_DMA_SHARED_BUFFER=y\nCONFIG_DMA_VIRTUAL_CHANNELS=y\nCONFIG_DRM=y\nCONFIG_DRM_BRIDGE=y\nCONFIG_DRM_FBDEV_EMULATION=y\nCONFIG_DRM_FBDEV_OVERALLOC=100\nCONFIG_DRM_GEM_CMA_HELPER=y\nCONFIG_DRM_KMS_CMA_HELPER=y\nCONFIG_DRM_KMS_FB_HELPER=y\nCONFIG_DRM_KMS_HELPER=y\nCONFIG_DRM_PANEL=y\nCONFIG_DRM_PANEL_BRIDGE=y\nCONFIG_DRM_PANEL_ILITEK_IL9322=y\nCONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y\nCONFIG_DRM_TVE200=y\nCONFIG_DTC=y\nCONFIG_DUMMY_CONSOLE=y\nCONFIG_EDAC_ATOMIC_SCRUB=y\nCONFIG_EDAC_SUPPORT=y\nCONFIG_EEPROM_93CX6=y\nCONFIG_ELF_CORE=y\n# CONFIG_EMBEDDED is not set\n# CONFIG_EXPERT is not set\nCONFIG_EXT4_FS=y\nCONFIG_FARADAY_FTINTC010=y\nCONFIG_FB=y\nCONFIG_FB_CFB_COPYAREA=y\nCONFIG_FB_CFB_FILLRECT=y\nCONFIG_FB_CFB_IMAGEBLIT=y\nCONFIG_FB_CMDLINE=y\nCONFIG_FB_DEFERRED_IO=y\nCONFIG_FB_SYS_COPYAREA=y\nCONFIG_FB_SYS_FILLRECT=y\nCONFIG_FB_SYS_FOPS=y\nCONFIG_FB_SYS_IMAGEBLIT=y\nCONFIG_FHANDLE=y\nCONFIG_FIXED_PHY=y\nCONFIG_FIX_EARLYCON_MEM=y\nCONFIG_FONT_8x16=y\nCONFIG_FONT_8x8=y\nCONFIG_FONT_SUPPORT=y\nCONFIG_FRAMEBUFFER_CONSOLE=y\nCONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y\n# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set\nCONFIG_FS_IOMAP=y\nCONFIG_FS_MBCACHE=y\nCONFIG_FS_POSIX_ACL=y\nCONFIG_FTTMR010_TIMER=y\nCONFIG_FTWDT010_WATCHDOG=y\nCONFIG_FW_LOADER_PAGED_BUF=y\n# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set\nCONFIG_GEMINI_ETHERNET=y\nCONFIG_GENERIC_ALLOCATOR=y\nCONFIG_GENERIC_ATOMIC64=y\nCONFIG_GENERIC_BUG=y\nCONFIG_GENERIC_CLOCKEVENTS=y\nCONFIG_GENERIC_CPU_AUTOPROBE=y\nCONFIG_GENERIC_EARLY_IOREMAP=y\nCONFIG_GENERIC_IDLE_POLL_SETUP=y\nCONFIG_GENERIC_IRQ_MULTI_HANDLER=y\nCONFIG_GENERIC_IRQ_SHOW=y\nCONFIG_GENERIC_IRQ_SHOW_LEVEL=y\nCONFIG_GENERIC_PCI_IOMAP=y\nCONFIG_GENERIC_PINCONF=y\nCONFIG_GENERIC_SCHED_CLOCK=y\nCONFIG_GENERIC_SMP_IDLE_THREAD=y\nCONFIG_GENERIC_STRNCPY_FROM_USER=y\nCONFIG_GENERIC_STRNLEN_USER=y\nCONFIG_GLOB=y\nCONFIG_GPIOLIB=y\nCONFIG_GPIOLIB_IRQCHIP=y\nCONFIG_GPIO_CDEV=y\nCONFIG_GPIO_FTGPIO010=y\nCONFIG_GPIO_GENERIC=y\nCONFIG_GRO_CELLS=y\nCONFIG_HANDLE_DOMAIN_IRQ=y\nCONFIG_HARDIRQS_SW_RESEND=y\nCONFIG_HAS_DMA=y\nCONFIG_HAS_IOMEM=y\nCONFIG_HAS_IOPORT_MAP=y\nCONFIG_HDMI=y\nCONFIG_HIGHMEM=y\nCONFIG_HIGHPTE=y\nCONFIG_HWMON=y\nCONFIG_HW_CONSOLE=y\nCONFIG_HZ_FIXED=0\nCONFIG_I2C=y\nCONFIG_I2C_ALGOBIT=y\nCONFIG_I2C_BOARDINFO=y\nCONFIG_I2C_COMPAT=y\nCONFIG_I2C_GPIO=y\nCONFIG_I2C_HELPER_AUTO=y\nCONFIG_INITRAMFS_SOURCE=\"\"\nCONFIG_INPUT=y\nCONFIG_INPUT_KEYBOARD=y\n# CONFIG_IOMMU_DEBUGFS is not set\n# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set\n# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set\nCONFIG_IOMMU_SUPPORT=y\nCONFIG_IO_URING=y\nCONFIG_IPC_NS=y\nCONFIG_IRQCHIP=y\nCONFIG_IRQ_DOMAIN=y\nCONFIG_IRQ_FORCED_THREADING=y\nCONFIG_IRQ_WORK=y\n# CONFIG_ISDN is not set\nCONFIG_JBD2=y\nCONFIG_KALLSYMS=y\nCONFIG_KCMP=y\nCONFIG_KERNEL_LZMA=y\n# CONFIG_KERNEL_XZ is not set\nCONFIG_KEXEC=y\nCONFIG_KEXEC_CORE=y\nCONFIG_KEYBOARD_DLINK_DIR685=y\n# CONFIG_LDM_DEBUG is not set\nCONFIG_LDM_PARTITION=y\nCONFIG_LEDS_TRIGGER_DISK=y\nCONFIG_LIBFDT=y\nCONFIG_LOCK_DEBUGGING_SUPPORT=y\nCONFIG_LOGO=y\nCONFIG_LOGO_LINUX_CLUT224=y\n# CONFIG_LOGO_LINUX_MONO is not set\nCONFIG_LOGO_LINUX_VGA16=y\nCONFIG_LZ4_DECOMPRESS=y\nCONFIG_LZO_DECOMPRESS=y\nCONFIG_MANDATORY_FILE_LOCKING=y\nCONFIG_MARVELL_PHY=y\nCONFIG_MDIO_BITBANG=y\nCONFIG_MDIO_BUS=y\nCONFIG_MDIO_DEVICE=y\nCONFIG_MDIO_DEVRES=y\nCONFIG_MDIO_GPIO=y\nCONFIG_MEMFD_CREATE=y\nCONFIG_MEMORY_ISOLATION=y\nCONFIG_MFD_SYSCON=y\nCONFIG_MIGRATION=y\nCONFIG_MODULES_USE_ELF_REL=y\n# CONFIG_MODULE_UNLOAD is not set\nCONFIG_MQ_IOSCHED_DEADLINE=y\nCONFIG_MQ_IOSCHED_KYBER=y\nCONFIG_MTD_CFI_STAA=y\nCONFIG_MTD_JEDECPROBE=y\nCONFIG_MTD_PHYSMAP=y\nCONFIG_MTD_PHYSMAP_GEMINI=y\nCONFIG_MTD_REDBOOT_PARTS=y\nCONFIG_MTD_SPLIT_FIRMWARE=y\nCONFIG_MTD_SPLIT_WRGG_FW=y\nCONFIG_NAMESPACES=y\nCONFIG_NEED_DMA_MAP_STATE=y\nCONFIG_NEED_KUSER_HELPERS=y\nCONFIG_NEED_PER_CPU_KM=y\nCONFIG_NET_DEVLINK=y\nCONFIG_NET_DSA=y\nCONFIG_NET_DSA_REALTEK_SMI=y\nCONFIG_NET_DSA_TAG_RTL4_A=y\nCONFIG_NET_NS=y\nCONFIG_NET_SWITCHDEV=y\nCONFIG_NLS=y\nCONFIG_NO_HZ_COMMON=y\nCONFIG_NO_HZ_IDLE=y\nCONFIG_NVMEM=y\nCONFIG_OF=y\nCONFIG_OF_ADDRESS=y\nCONFIG_OF_EARLY_FLATTREE=y\nCONFIG_OF_FLATTREE=y\nCONFIG_OF_GPIO=y\nCONFIG_OF_IRQ=y\nCONFIG_OF_KOBJ=y\nCONFIG_OF_MDIO=y\nCONFIG_OF_NET=y\nCONFIG_OLD_SIGACTION=y\nCONFIG_OLD_SIGSUSPEND3=y\nCONFIG_PAGE_OFFSET=0xC0000000\n# CONFIG_PANIC_ON_OOPS is not set\nCONFIG_PANIC_ON_OOPS_VALUE=0\nCONFIG_PANIC_TIMEOUT=0\nCONFIG_PATA_FTIDE010=y\nCONFIG_PCI=y\nCONFIG_PCIEASPM=y\nCONFIG_PCIEASPM_DEFAULT=y\n# CONFIG_PCIEASPM_PERFORMANCE is not set\n# CONFIG_PCIEASPM_POWERSAVE is not set\n# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set\nCONFIG_PCI_DOMAINS=y\nCONFIG_PCI_DOMAINS_GENERIC=y\nCONFIG_PCI_FTPCI100=y\nCONFIG_PERF_USE_VMALLOC=y\nCONFIG_PGTABLE_LEVELS=2\nCONFIG_PHYLIB=y\nCONFIG_PHYLINK=y\nCONFIG_PID_NS=y\nCONFIG_PINCTRL=y\nCONFIG_PINCTRL_GEMINI=y\n# CONFIG_PINCTRL_SINGLE is not set\nCONFIG_PM=y\nCONFIG_PM_CLK=y\nCONFIG_POWER_RESET=y\nCONFIG_POWER_RESET_GEMINI_POWEROFF=y\nCONFIG_POWER_RESET_SYSCON=y\nCONFIG_PREEMPT=y\nCONFIG_PREEMPTION=y\nCONFIG_PREEMPT_COUNT=y\n# CONFIG_PREEMPT_NONE is not set\nCONFIG_PREEMPT_RCU=y\nCONFIG_PROC_PAGE_MONITOR=y\nCONFIG_RATIONAL=y\nCONFIG_RD_BZIP2=y\nCONFIG_RD_GZIP=y\nCONFIG_RD_LZ4=y\nCONFIG_RD_LZMA=y\nCONFIG_RD_LZO=y\nCONFIG_RD_XZ=y\nCONFIG_REALTEK_PHY=y\nCONFIG_REGMAP=y\nCONFIG_REGMAP_I2C=y\nCONFIG_REGMAP_MMIO=y\nCONFIG_REGULATOR=y\nCONFIG_REGULATOR_FIXED_VOLTAGE=y\nCONFIG_RELAY=y\nCONFIG_RESET_CONTROLLER=y\nCONFIG_RSEQ=y\nCONFIG_RTC_CLASS=y\nCONFIG_RTC_DRV_FTRTC010=y\nCONFIG_RTC_I2C_AND_SPI=y\nCONFIG_RTC_MC146818_LIB=y\nCONFIG_RTC_NVMEM=y\nCONFIG_SATA_GEMINI=y\nCONFIG_SATA_HOST=y\nCONFIG_SATA_PMP=y\nCONFIG_SCSI=y\n# CONFIG_SCSI_LOWLEVEL is not set\n# CONFIG_SCSI_PROC_FS is not set\nCONFIG_SENSORS_DRIVETEMP=y\nCONFIG_SENSORS_GPIO_FAN=y\nCONFIG_SENSORS_LM75=y\nCONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y\nCONFIG_SERIAL_8250_EXAR=y\nCONFIG_SERIAL_8250_FSL=y\nCONFIG_SERIAL_8250_NR_UARTS=1\nCONFIG_SERIAL_8250_PCI=y\nCONFIG_SERIAL_8250_RUNTIME_UARTS=1\nCONFIG_SERIAL_MCTRL_GPIO=y\nCONFIG_SERIAL_OF_PLATFORM=y\nCONFIG_SERIO=y\nCONFIG_SERIO_LIBPS2=y\nCONFIG_SERIO_SERPORT=y\nCONFIG_SG_POOL=y\nCONFIG_SLUB_DEBUG=y\nCONFIG_SPARSE_IRQ=y\nCONFIG_SPI=y\nCONFIG_SPI_BITBANG=y\nCONFIG_SPI_GPIO=y\nCONFIG_SPI_MASTER=y\nCONFIG_SPLIT_PTLOCK_CPUS=999999\nCONFIG_SRCU=y\n# CONFIG_STRIP_ASM_SYMS is not set\nCONFIG_SWPHY=y\nCONFIG_SYNC_FILE=y\nCONFIG_SYSFS_SYSCALL=y\nCONFIG_SYS_SUPPORTS_APM_EMULATION=y\nCONFIG_THERMAL=y\nCONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y\nCONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0\nCONFIG_THERMAL_GOV_STEP_WISE=y\nCONFIG_THERMAL_HWMON=y\nCONFIG_THERMAL_OF=y\nCONFIG_TICK_CPU_ACCOUNTING=y\nCONFIG_TIMER_OF=y\nCONFIG_TIMER_PROBE=y\nCONFIG_TMPFS_POSIX_ACL=y\nCONFIG_TREE_RCU=y\nCONFIG_TREE_SRCU=y\nCONFIG_UNCOMPRESS_INCLUDE=\"debug/uncompress.h\"\nCONFIG_UNINLINE_SPIN_UNLOCK=y\nCONFIG_UNWINDER_ARM=y\nCONFIG_USB_SUPPORT=y\nCONFIG_USER_NS=y\nCONFIG_USE_OF=y\nCONFIG_UTS_NS=y\nCONFIG_VGA_ARB=y\nCONFIG_VGA_ARB_MAX_GPUS=16\nCONFIG_VITESSE_PHY=y\nCONFIG_VM_EVENT_COUNTERS=y\nCONFIG_VT=y\nCONFIG_VT_CONSOLE=y\nCONFIG_VT_HW_CONSOLE_BINDING=y\nCONFIG_WATCHDOG_CORE=y\n# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set\nCONFIG_XZ_DEC_ARM=y\nCONFIG_XZ_DEC_ARMTHUMB=y\nCONFIG_XZ_DEC_BCJ=y\nCONFIG_XZ_DEC_IA64=y\nCONFIG_XZ_DEC_POWERPC=y\nCONFIG_XZ_DEC_SPARC=y\nCONFIG_XZ_DEC_X86=y\nCONFIG_ZBOOT_ROM_BSS=0\nCONFIG_ZBOOT_ROM_TEXT=0\nCONFIG_ZLIB_INFLATE=y\n"
  },
  {
    "path": "target/linux/gemini/config-5.15",
    "content": "CONFIG_ALIGNMENT_TRAP=y\nCONFIG_AMBA_PL08X=y\nCONFIG_ARCH_32BIT_OFF_T=y\nCONFIG_ARCH_GEMINI=y\nCONFIG_ARCH_KEEP_MEMBLOCK=y\nCONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y\n# CONFIG_ARCH_MOXART is not set\nCONFIG_ARCH_MULTIPLATFORM=y\nCONFIG_ARCH_MULTI_V4=y\n# CONFIG_ARCH_MULTI_V4T is not set\nCONFIG_ARCH_MULTI_V4_V5=y\n# CONFIG_ARCH_MULTI_V5 is not set\nCONFIG_ARCH_NR_GPIO=0\nCONFIG_ARCH_OPTIONAL_KERNEL_RWX=y\nCONFIG_ARCH_SELECT_MEMORY_MODEL=y\nCONFIG_ARCH_SPARSEMEM_ENABLE=y\nCONFIG_ARM=y\nCONFIG_ARM_AMBA=y\nCONFIG_ARM_APPENDED_DTB=y\n# CONFIG_ARM_ATAG_DTB_COMPAT is not set\nCONFIG_ARM_HAS_SG_CHAIN=y\nCONFIG_ARM_L1_CACHE_SHIFT=5\nCONFIG_ARM_PATCH_PHYS_VIRT=y\n# CONFIG_ARM_SMMU is not set\nCONFIG_ARM_UNWIND=y\nCONFIG_ATA=y\nCONFIG_ATAGS=y\nCONFIG_ATA_FORCE=y\nCONFIG_ATA_VERBOSE_ERROR=y\nCONFIG_AUTO_ZRELADDR=y\nCONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y\nCONFIG_BLK_DEV_SD=y\nCONFIG_BLK_MQ_PCI=y\nCONFIG_BLK_PM=y\nCONFIG_BOUNCE=y\nCONFIG_CLKSRC_MMIO=y\nCONFIG_CLONE_BACKWARDS=y\nCONFIG_CMA=y\nCONFIG_CMA_ALIGNMENT=8\nCONFIG_CMA_AREAS=7\n# CONFIG_CMA_DEBUG is not set\n# CONFIG_CMA_DEBUGFS is not set\nCONFIG_CMA_SIZE_PERCENTAGE=10\n# CONFIG_CMA_SIZE_SEL_MAX is not set\n# CONFIG_CMA_SIZE_SEL_MBYTES is not set\n# CONFIG_CMA_SIZE_SEL_MIN is not set\nCONFIG_CMA_SIZE_SEL_PERCENTAGE=y\n# CONFIG_CMA_SYSFS is not set\nCONFIG_COMMON_CLK=y\nCONFIG_COMMON_CLK_GEMINI=y\nCONFIG_COMPAT_32BIT_TIME=y\nCONFIG_CONSOLE_TRANSLATIONS=y\nCONFIG_CONTIG_ALLOC=y\nCONFIG_COREDUMP=y\nCONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y\nCONFIG_CPU_32v4=y\nCONFIG_CPU_ABRT_EV4=y\nCONFIG_CPU_CACHE_FA=y\nCONFIG_CPU_CACHE_VIVT=y\nCONFIG_CPU_COPY_FA=y\nCONFIG_CPU_CP15=y\nCONFIG_CPU_CP15_MMU=y\n# CONFIG_CPU_DCACHE_WRITETHROUGH is not set\nCONFIG_CPU_FA526=y\nCONFIG_CPU_NO_EFFICIENT_FFS=y\nCONFIG_CPU_PABRT_LEGACY=y\nCONFIG_CPU_THERMAL=y\nCONFIG_CPU_TLB_FA=y\nCONFIG_CPU_USE_DOMAINS=y\nCONFIG_CRASH_CORE=y\nCONFIG_CRC16=y\n# CONFIG_CRC32_SARWATE is not set\nCONFIG_CRC32_SLICEBY8=y\nCONFIG_CRC_CCITT=y\nCONFIG_CRC_ITU_T=y\nCONFIG_CROSS_MEMORY_ATTACH=y\nCONFIG_CRYPTO_CMAC=y\nCONFIG_CRYPTO_CRC32C=y\nCONFIG_CRYPTO_DES=y\nCONFIG_CRYPTO_DEV_SL3516=y\n# CONFIG_CRYPTO_DEV_SL3516_DEBUG is not set\nCONFIG_CRYPTO_DRBG=y\nCONFIG_CRYPTO_DRBG_HMAC=y\nCONFIG_CRYPTO_DRBG_MENU=y\nCONFIG_CRYPTO_ECB=y\nCONFIG_CRYPTO_ECHAINIV=y\nCONFIG_CRYPTO_ENGINE=y\nCONFIG_CRYPTO_HMAC=y\nCONFIG_CRYPTO_HW=y\nCONFIG_CRYPTO_JITTERENTROPY=y\nCONFIG_CRYPTO_LIB_DES=y\nCONFIG_CRYPTO_LIB_SHA256=y\nCONFIG_CRYPTO_MD4=y\nCONFIG_CRYPTO_MD5=y\nCONFIG_CRYPTO_RNG=y\nCONFIG_CRYPTO_RNG2=y\nCONFIG_CRYPTO_RNG_DEFAULT=y\nCONFIG_CRYPTO_SEQIV=y\nCONFIG_CRYPTO_SHA256=y\nCONFIG_CRYPTO_SHA512=y\nCONFIG_DEBUG_BUGVERBOSE=y\nCONFIG_DEBUG_LL_INCLUDE=\"mach/debug-macro.S\"\nCONFIG_DEBUG_MEMORY_INIT=y\nCONFIG_DECOMPRESS_BZIP2=y\nCONFIG_DECOMPRESS_GZIP=y\nCONFIG_DECOMPRESS_LZ4=y\nCONFIG_DECOMPRESS_LZMA=y\nCONFIG_DECOMPRESS_LZO=y\nCONFIG_DECOMPRESS_XZ=y\nCONFIG_DMADEVICES=y\nCONFIG_DMATEST=y\nCONFIG_DMA_CMA=y\nCONFIG_DMA_ENGINE=y\nCONFIG_DMA_ENGINE_RAID=y\nCONFIG_DMA_OF=y\nCONFIG_DMA_OPS=y\nCONFIG_DMA_REMAP=y\nCONFIG_DMA_SHARED_BUFFER=y\nCONFIG_DMA_VIRTUAL_CHANNELS=y\nCONFIG_DRM=y\nCONFIG_DRM_BRIDGE=y\nCONFIG_DRM_FBDEV_EMULATION=y\nCONFIG_DRM_FBDEV_OVERALLOC=100\nCONFIG_DRM_GEM_CMA_HELPER=y\nCONFIG_DRM_KMS_CMA_HELPER=y\nCONFIG_DRM_KMS_HELPER=y\nCONFIG_DRM_PANEL=y\nCONFIG_DRM_PANEL_BRIDGE=y\nCONFIG_DRM_PANEL_ILITEK_IL9322=y\nCONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y\nCONFIG_DRM_TVE200=y\nCONFIG_DTC=y\nCONFIG_DUMMY_CONSOLE=y\nCONFIG_EDAC_ATOMIC_SCRUB=y\nCONFIG_EDAC_SUPPORT=y\nCONFIG_EEPROM_93CX6=y\nCONFIG_ELF_CORE=y\n# CONFIG_EMBEDDED is not set\n# CONFIG_EXPERT is not set\nCONFIG_EXT4_FS=y\nCONFIG_FARADAY_FTINTC010=y\nCONFIG_FB=y\nCONFIG_FB_CFB_COPYAREA=y\nCONFIG_FB_CFB_FILLRECT=y\nCONFIG_FB_CFB_IMAGEBLIT=y\nCONFIG_FB_CMDLINE=y\nCONFIG_FB_DEFERRED_IO=y\nCONFIG_FB_SYS_COPYAREA=y\nCONFIG_FB_SYS_FILLRECT=y\nCONFIG_FB_SYS_FOPS=y\nCONFIG_FB_SYS_IMAGEBLIT=y\nCONFIG_FHANDLE=y\nCONFIG_FIXED_PHY=y\nCONFIG_FIX_EARLYCON_MEM=y\nCONFIG_FONT_8x16=y\nCONFIG_FONT_8x8=y\nCONFIG_FONT_SUPPORT=y\nCONFIG_FRAMEBUFFER_CONSOLE=y\nCONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y\n# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set\nCONFIG_FS_IOMAP=y\nCONFIG_FS_MBCACHE=y\nCONFIG_FS_POSIX_ACL=y\nCONFIG_FTTMR010_TIMER=y\nCONFIG_FTWDT010_WATCHDOG=y\nCONFIG_FWNODE_MDIO=y\nCONFIG_FW_LOADER_PAGED_BUF=y\n# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set\nCONFIG_GEMINI_ETHERNET=y\nCONFIG_GENERIC_ALLOCATOR=y\nCONFIG_GENERIC_ATOMIC64=y\nCONFIG_GENERIC_BUG=y\nCONFIG_GENERIC_CLOCKEVENTS=y\nCONFIG_GENERIC_CPU_AUTOPROBE=y\nCONFIG_GENERIC_EARLY_IOREMAP=y\nCONFIG_GENERIC_IDLE_POLL_SETUP=y\nCONFIG_GENERIC_IRQ_MULTI_HANDLER=y\nCONFIG_GENERIC_IRQ_SHOW=y\nCONFIG_GENERIC_IRQ_SHOW_LEVEL=y\nCONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y\nCONFIG_GENERIC_PCI_IOMAP=y\nCONFIG_GENERIC_PINCONF=y\nCONFIG_GENERIC_SCHED_CLOCK=y\nCONFIG_GENERIC_SMP_IDLE_THREAD=y\nCONFIG_GENERIC_STRNCPY_FROM_USER=y\nCONFIG_GENERIC_STRNLEN_USER=y\nCONFIG_GLOB=y\nCONFIG_GPIOLIB=y\nCONFIG_GPIOLIB_IRQCHIP=y\nCONFIG_GPIO_CDEV=y\nCONFIG_GPIO_FTGPIO010=y\nCONFIG_GPIO_GENERIC=y\nCONFIG_GRO_CELLS=y\nCONFIG_HANDLE_DOMAIN_IRQ=y\nCONFIG_HARDIRQS_SW_RESEND=y\nCONFIG_HAS_DMA=y\nCONFIG_HAS_IOMEM=y\nCONFIG_HAS_IOPORT_MAP=y\nCONFIG_HDMI=y\nCONFIG_HIGHMEM=y\nCONFIG_HIGHPTE=y\nCONFIG_HWMON=y\nCONFIG_HW_CONSOLE=y\nCONFIG_HW_RANDOM=y\nCONFIG_HZ_FIXED=0\nCONFIG_I2C=y\nCONFIG_I2C_ALGOBIT=y\nCONFIG_I2C_BOARDINFO=y\nCONFIG_I2C_COMPAT=y\nCONFIG_I2C_GPIO=y\nCONFIG_I2C_HELPER_AUTO=y\nCONFIG_INITRAMFS_SOURCE=\"\"\nCONFIG_INPUT=y\nCONFIG_INPUT_KEYBOARD=y\n# CONFIG_IOMMU_DEBUGFS is not set\n# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set\n# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set\nCONFIG_IOMMU_SUPPORT=y\nCONFIG_IO_URING=y\nCONFIG_IPC_NS=y\nCONFIG_IRQCHIP=y\nCONFIG_IRQ_DOMAIN=y\nCONFIG_IRQ_FORCED_THREADING=y\nCONFIG_IRQ_WORK=y\n# CONFIG_ISDN is not set\nCONFIG_JBD2=y\nCONFIG_KALLSYMS=y\nCONFIG_KCMP=y\nCONFIG_KERNEL_LZMA=y\n# CONFIG_KERNEL_XZ is not set\nCONFIG_KEXEC=y\nCONFIG_KEXEC_CORE=y\nCONFIG_KEYBOARD_DLINK_DIR685=y\nCONFIG_KMAP_LOCAL=y\nCONFIG_KMAP_LOCAL_NON_LINEAR_PTE_ARRAY=y\n# CONFIG_LDM_DEBUG is not set\nCONFIG_LDM_PARTITION=y\nCONFIG_LEDS_TRIGGER_DISK=y\nCONFIG_LIBFDT=y\nCONFIG_LOCK_DEBUGGING_SUPPORT=y\nCONFIG_LOGO=y\nCONFIG_LOGO_LINUX_CLUT224=y\n# CONFIG_LOGO_LINUX_MONO is not set\nCONFIG_LOGO_LINUX_VGA16=y\nCONFIG_LZ4_DECOMPRESS=y\nCONFIG_LZO_DECOMPRESS=y\nCONFIG_MARVELL_PHY=y\nCONFIG_MDIO_BITBANG=y\nCONFIG_MDIO_BUS=y\nCONFIG_MDIO_DEVICE=y\nCONFIG_MDIO_DEVRES=y\nCONFIG_MDIO_GPIO=y\nCONFIG_MEMFD_CREATE=y\nCONFIG_MEMORY_ISOLATION=y\nCONFIG_MFD_SYSCON=y\nCONFIG_MIGRATION=y\nCONFIG_MODULES_USE_ELF_REL=y\n# CONFIG_MODULE_UNLOAD is not set\nCONFIG_MQ_IOSCHED_DEADLINE=y\nCONFIG_MQ_IOSCHED_KYBER=y\nCONFIG_MTD_CFI_STAA=y\nCONFIG_MTD_JEDECPROBE=y\nCONFIG_MTD_PHYSMAP=y\nCONFIG_MTD_PHYSMAP_GEMINI=y\nCONFIG_MTD_REDBOOT_PARTS=y\nCONFIG_MTD_SPLIT_FIRMWARE=y\nCONFIG_MTD_SPLIT_WRGG_FW=y\nCONFIG_NAMESPACES=y\nCONFIG_NEED_DMA_MAP_STATE=y\nCONFIG_NEED_KUSER_HELPERS=y\nCONFIG_NEED_PER_CPU_KM=y\nCONFIG_NET_DEVLINK=y\nCONFIG_NET_DSA=y\nCONFIG_NET_DSA_REALTEK_SMI=y\nCONFIG_NET_DSA_TAG_RTL4_A=y\nCONFIG_NET_NS=y\nCONFIG_NET_SELFTESTS=y\nCONFIG_NET_SWITCHDEV=y\nCONFIG_NLS=y\nCONFIG_NO_HZ_COMMON=y\nCONFIG_NO_HZ_IDLE=y\nCONFIG_NVMEM=y\nCONFIG_OF=y\nCONFIG_OF_ADDRESS=y\nCONFIG_OF_EARLY_FLATTREE=y\nCONFIG_OF_FLATTREE=y\nCONFIG_OF_GPIO=y\nCONFIG_OF_IRQ=y\nCONFIG_OF_KOBJ=y\nCONFIG_OF_MDIO=y\nCONFIG_OLD_SIGACTION=y\nCONFIG_OLD_SIGSUSPEND3=y\nCONFIG_PAGE_OFFSET=0xC0000000\n# CONFIG_PANIC_ON_OOPS is not set\nCONFIG_PANIC_ON_OOPS_VALUE=0\nCONFIG_PANIC_TIMEOUT=0\nCONFIG_PATA_FTIDE010=y\nCONFIG_PCI=y\nCONFIG_PCIEASPM=y\nCONFIG_PCIEASPM_DEFAULT=y\n# CONFIG_PCIEASPM_PERFORMANCE is not set\n# CONFIG_PCIEASPM_POWERSAVE is not set\n# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set\nCONFIG_PCI_DOMAINS=y\nCONFIG_PCI_DOMAINS_GENERIC=y\nCONFIG_PCI_FTPCI100=y\nCONFIG_PERF_USE_VMALLOC=y\nCONFIG_PGTABLE_LEVELS=2\nCONFIG_PHYLIB=y\nCONFIG_PHYLINK=y\nCONFIG_PID_NS=y\nCONFIG_PINCTRL=y\nCONFIG_PINCTRL_GEMINI=y\n# CONFIG_PINCTRL_SINGLE is not set\nCONFIG_PM=y\nCONFIG_PM_CLK=y\nCONFIG_POWER_RESET=y\nCONFIG_POWER_RESET_GEMINI_POWEROFF=y\nCONFIG_POWER_RESET_SYSCON=y\nCONFIG_PREEMPT=y\nCONFIG_PREEMPTION=y\nCONFIG_PREEMPT_COUNT=y\n# CONFIG_PREEMPT_NONE is not set\nCONFIG_PREEMPT_RCU=y\nCONFIG_PROC_PAGE_MONITOR=y\nCONFIG_PTP_1588_CLOCK_OPTIONAL=y\nCONFIG_RATIONAL=y\nCONFIG_RD_BZIP2=y\nCONFIG_RD_GZIP=y\nCONFIG_RD_LZ4=y\nCONFIG_RD_LZMA=y\nCONFIG_RD_LZO=y\nCONFIG_RD_XZ=y\nCONFIG_REALTEK_PHY=y\nCONFIG_REGMAP=y\nCONFIG_REGMAP_I2C=y\nCONFIG_REGMAP_MMIO=y\nCONFIG_REGULATOR=y\nCONFIG_REGULATOR_FIXED_VOLTAGE=y\nCONFIG_RELAY=y\nCONFIG_RESET_CONTROLLER=y\nCONFIG_RSEQ=y\nCONFIG_RTC_CLASS=y\nCONFIG_RTC_DRV_FTRTC010=y\nCONFIG_RTC_I2C_AND_SPI=y\nCONFIG_RTC_MC146818_LIB=y\nCONFIG_RTC_NVMEM=y\nCONFIG_SATA_GEMINI=y\nCONFIG_SATA_HOST=y\nCONFIG_SATA_PMP=y\nCONFIG_SCSI=y\nCONFIG_SCSI_COMMON=y\n# CONFIG_SCSI_LOWLEVEL is not set\n# CONFIG_SCSI_PROC_FS is not set\nCONFIG_SENSORS_DRIVETEMP=y\nCONFIG_SENSORS_GPIO_FAN=y\nCONFIG_SENSORS_LM75=y\nCONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y\nCONFIG_SERIAL_8250_EXAR=y\nCONFIG_SERIAL_8250_FSL=y\nCONFIG_SERIAL_8250_NR_UARTS=1\nCONFIG_SERIAL_8250_PCI=y\nCONFIG_SERIAL_8250_RUNTIME_UARTS=1\nCONFIG_SERIAL_MCTRL_GPIO=y\nCONFIG_SERIAL_OF_PLATFORM=y\nCONFIG_SERIO=y\nCONFIG_SERIO_LIBPS2=y\nCONFIG_SERIO_SERPORT=y\nCONFIG_SG_POOL=y\nCONFIG_SLUB_DEBUG=y\nCONFIG_SPARSE_IRQ=y\nCONFIG_SPI=y\nCONFIG_SPI_BITBANG=y\nCONFIG_SPI_GPIO=y\nCONFIG_SPI_MASTER=y\nCONFIG_SPLIT_PTLOCK_CPUS=999999\nCONFIG_SRCU=y\n# CONFIG_STRIP_ASM_SYMS is not set\nCONFIG_SWPHY=y\nCONFIG_SYNC_FILE=y\nCONFIG_SYSFS_SYSCALL=y\nCONFIG_SYS_SUPPORTS_APM_EMULATION=y\nCONFIG_THERMAL=y\nCONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y\nCONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0\nCONFIG_THERMAL_GOV_STEP_WISE=y\nCONFIG_THERMAL_HWMON=y\nCONFIG_THERMAL_OF=y\nCONFIG_TICK_CPU_ACCOUNTING=y\nCONFIG_TIMER_OF=y\nCONFIG_TIMER_PROBE=y\nCONFIG_TMPFS_POSIX_ACL=y\nCONFIG_TREE_RCU=y\nCONFIG_TREE_SRCU=y\nCONFIG_UNCOMPRESS_INCLUDE=\"debug/uncompress.h\"\nCONFIG_UNINLINE_SPIN_UNLOCK=y\nCONFIG_UNWINDER_ARM=y\nCONFIG_USB_SUPPORT=y\nCONFIG_USER_NS=y\nCONFIG_USE_OF=y\nCONFIG_UTS_NS=y\nCONFIG_VGA_ARB=y\nCONFIG_VGA_ARB_MAX_GPUS=16\nCONFIG_VITESSE_PHY=y\nCONFIG_VM_EVENT_COUNTERS=y\nCONFIG_VT=y\nCONFIG_VT_CONSOLE=y\nCONFIG_VT_HW_CONSOLE_BINDING=y\nCONFIG_WATCHDOG_CORE=y\n# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set\nCONFIG_XZ_DEC_ARM=y\nCONFIG_XZ_DEC_ARMTHUMB=y\nCONFIG_XZ_DEC_BCJ=y\nCONFIG_XZ_DEC_IA64=y\nCONFIG_XZ_DEC_POWERPC=y\nCONFIG_XZ_DEC_SPARC=y\nCONFIG_XZ_DEC_X86=y\nCONFIG_ZBOOT_ROM_BSS=0\nCONFIG_ZBOOT_ROM_TEXT=0\nCONFIG_ZLIB_INFLATE=y\n"
  },
  {
    "path": "target/linux/gemini/image/ImageInfo-itian_sq201",
    "content": "UpgradeImages=\"zImage rd.gz hddapp.tgz\"\nProcduction=\"SL3516\"\nBOOT_VER=\"1.0.5\"\nFIRMWARE_VER=\"firmware-openwrt-DATESTR\"\nINTERNAL_FIRMWARE_VER=\"firmware-openwrt-DATESTR\"\nCONFIGURATION_VER=\"firmware-openwrt\"\nDESCRIPTION=\"Square One Router/Nas\"\nTSS=\"enabled\"\nDIRECT_MODE=\"disabled\"\nDEFAULT_LAN_IPADDR=\"192.168.1.1\"\nDEFAULT_LAN_NETMASK=\"255.255.255.0\"\nDEFAULT_LAN_BOOTPROTO=\"none\"\nDEFAULT_WAN_BOOTPROTO=\"dhcp\"\nDEFAULT_WAN_ENABLED=\"yes\"\nDEFAULT_WLAN_DEVICENAME=\"eth0\"\nVER_zImage=\"DATESTR\"\nVER_Ramdisk=\"DATESTR\"\nVER_hddapp=\"DATESTR\"\n"
  },
  {
    "path": "target/linux/gemini/image/ImageInfo-raidsonic_ib-4220-b",
    "content": "Distribution=\"OpenWrt\"\nLayout=\"Compact\"\nUpgradeImages=\"zImage rd.gz hddapp.tgz\"\nproductName=\"IB-NAS4220-B\"\nhardwareName=\"MP-LNU23SL\"\nproductVendor=\"   \"\nVendorID=\"macpower\"\nProductID=\"pddlan\"\nUpgradeVersion=\"300\"\nExtraVersion=\"\"\nmanufacturerURL=\"   \"\nDescription=\"IB-NAS4220-B\"\nhostname=\"IB-NAS4220-B\"\nsoftwareVersion=\"3.0\"\nTSS=\"enabled\"\nDIRECT_MODE=\"disabled\"\nRaid_Support=\"raid0_raid1_raid5_linear\"\nRaidTestDiskSize=\"0\"\nRaid_Show_Disk=\"2\"\n"
  },
  {
    "path": "target/linux/gemini/image/ImageInfo-storlink_sl93512r",
    "content": "UpgradeImages=\"zImage rd.gz hddapp.tgz\"\nProcduction=\"SL3516\"\nBOOT_VER=\"1.0.5\"\nFIRMWARE_VER=\"firmware-openwrt-DATESTR\"\nINTERNAL_FIRMWARE_VER=\"firmware-openwrt-DATESTR\"\nCONFIGURATION_VER=\"firmware-openwrt\"\nDESCRIPTION=\"Storlink SL93512r Reference Design\"\nTSS=\"enabled\"\nDIRECT_MODE=\"disabled\"\nDEFAULT_LAN_IPADDR=\"192.168.1.1\"\nDEFAULT_LAN_NETMASK=\"255.255.255.0\"\nDEFAULT_LAN_BOOTPROTO=\"none\"\nDEFAULT_WAN_BOOTPROTO=\"dhcp\"\nDEFAULT_WAN_ENABLED=\"yes\"\nDEFAULT_WLAN_DEVICENAME=\"eth0\"\nVER_zImage=\"DATESTR\"\nVER_Ramdisk=\"DATESTR\"\nVER_hddapp=\"DATESTR\"\n"
  },
  {
    "path": "target/linux/gemini/image/Makefile",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2009-2018 OpenWrt.org\n\ninclude $(TOPDIR)/rules.mk\ninclude $(INCLUDE_DIR)/image.mk\n\ndefine Build/copy-kernel.bin\n\t$(call locked,$(MAKE) -C copy-kernel CROSS_COMPILE=$(TARGET_CROSS) O=$(KDIR),gemini-copy-kernel.bin)\nendef\n\n# Cook a \"WRGG\" image, this board is apparently one in the D-Link\n# WRGG family and uses the exact same firmware format as other\n# D-Link devices.\ndefine Build/dir685-image\n\tmkwrggimg -i $@ \\\n\t-o $@.new \\\n\t-d /dev/mtdblock/1 \\\n\t-s wrgns01_dlwbr_dir685RBWW \\\n\t-v 'N/A' \\\n\t-m dir685 \\\n\t-B 96bb\n\n\tmv $@.new $@\nendef\n\n# Padding added after the rootfs to an even 128k boundary\n# as this is 128k eraseblocks flash.\ndefine Build/dir685-pad-rootfs\n\t$(STAGING_DIR_HOST)/bin/padjffs2 $(IMAGE_ROOTFS) -c 128 >>$@\nendef\n\n# Build D-Link DNS-313 images using the special header tool.\n# rootfs.tgz and rd.tgz contains nothing, we only need them\n# to satisfy the boot loader on the device. The zImage is\n# the only real content.\ndefine Build/dns313-images\n\tmkdir -p $@.tmp/.boot\n\tchmod 755 $@.tmp/.boot\n\n\techo \"dummy\" > $@.tmp/dummyfile\n\n\tdns313-header $@.tmp/dummyfile \\\n\t\t$@.tmp/.boot/rootfs.tgz\n\tdns313-header $@.tmp/dummyfile \\\n\t\t$@.tmp/.boot/rd.gz\n\tdns313-header $(IMAGE_KERNEL) \\\n\t\t$@.tmp/.boot/zImage\n\n\trm $@.tmp/dummyfile\n\n\tgenext2fs --block-size $(BLOCKSIZE:%k=%Ki) \\\n\t\t--size-in-blocks $$((1024 * $(CONFIG_TARGET_KERNEL_PARTSIZE))) \\\n\t\t--squash-uids \\\n\t\t--root $@.tmp $@.tmp-boot\n\n\t# The device firmware needs revision 1 of EXT2\n\ttune2fs -O filetype $@.tmp-boot\n\te2fsck -pDf $@.tmp-boot > /dev/null\n\n\t./dns313_gen_hdd_img.sh $@ $@.tmp-boot $(IMAGE_ROOTFS) \\\n\t\t$(CONFIG_TARGET_KERNEL_PARTSIZE) \\\n\t\t$(CONFIG_TARGET_ROOTFS_PARTSIZE)\n\n\trm -rf $@.tmp\nendef\n\ndefine Build/wiligear-image\n\t$(STAGING_DIR_HOST)/bin/mkfwimage2 \\\n\t\t-m GEOS -f 0x30000000 -z \\\n\t\t-v $(1).v5.00.SL3512.OpenWrt.00000.000000.000000 \\\n\t\t-p Kernel:0x020000:0x100000:0:0:$(IMAGE_KERNEL) \\\n\t\t-p Ramdisk:0x120000:0x500000:0:0:$@ \\\n\t\t-o $@.new\n\n\tmv $@.new $@\nendef\n\n# Create the default image format used by the StorLink reference design\n# SL93512r, Raidsonic NAS4220B and Itian Square One SQ201\n# with the squashfs and overlay inside the \"application\" partition.\n#\n# These devices have a hard-coded partition table that the boot loader\n# constantly reflashes back, so we need to work around it like this:\n#\n# 0x000000120000-0x000000320000 : \"Kern\" - small copy routine and first\n#                                 part of the kernel goes here\n# 0x000000320000-0x000000920000 : \"Ramdisk\" - second part of the kernel and\n#                                 some padding goes here\n# 0x000000920000-0x000000f20000 : \"Application\" - rootfs goes here\ndefine Build/storlink-default-images\n\tmkdir -p $@.tmp\n\n\t# \"App\" partition is the rootfs\n\tmv $@ $@.tmp/hddapp.tgz\n\t# 256 bytes copy routine\n\tdd if=$(KDIR)/copy-kernel.bin of=$@.tmp/zImage\n\t$(call Image/pad-to,$@.tmp/zImage,512)\n\t# Copy first part of the kernel into zImage\n\tdd if=$(IMAGE_KERNEL) of=$@.tmp/zImage bs=1 seek=512 count=2096640\n\t# Put the rest of the kernel into the \"ramdisk\"\n\tdd if=$(IMAGE_KERNEL) of=$@.tmp/rd.gz bs=1 skip=2096640 count=6144k conv=sync\n\tcp ./ImageInfo-$(1) $@.tmp/ImageInfo\n\n\tsed -i -e \"s/DATESTR/`date +%Y%m%d $(if $(SOURCE_DATE_EPOCH),--date \"@$(SOURCE_DATE_EPOCH)\")`/g\" $@.tmp/ImageInfo\n\n\t(cd $@.tmp; tar --sort=name --owner=0 --group=0 --numeric-owner -czf $@ * \\\n\t\t$(if $(SOURCE_DATE_EPOCH),--mtime=\"@$(SOURCE_DATE_EPOCH)\"))\n\n\trm -rf $@.tmp\nendef\n\n# WBD-111 and WBD-222:\n# work around the bootloader's bug with extra nops\n# FIXME: is this really needed now that we no longer append the code\n# to change the machine ID number? Needs testing on Wiliboard.\ndefine Build/wbd-nops\n\tmv $@ $@.tmp\n\techo -en \"\\x00\\x00\\xa0\\xe1\\x00\\x00\\xa0\\xe1\\x00\\x00\\xa0\\xe1\\x00\\x00\\xa0\\xe1\" > $@\n\tcat $@.tmp >> $@\n\trm -f $@.tmp\nendef\n\n# All DTB files are prefixed with \"gemini-\"\ndefine Device/Default\n\tPROFILES := Default\n\tKERNEL_DEPENDS = $$(wildcard $(DTS_DIR)/$$(DEVICE_DTS).dts)\n\tKERNEL_NAME := zImage\n\tKERNEL := kernel-bin | append-dtb\n\tBLOCKSIZE := 128k\nendef\n\n# A reasonable set of default packages handling the NAS type\n# of devices out of the box (former NAS42x0 IcyBox defaults)\nGEMINI_NAS_PACKAGES := $(DEFAULT_PACKAGES.nas) \\\n\t\tkmod-md-mod kmod-md-linear kmod-md-multipath \\\n\t\tkmod-md-raid0 kmod-md-raid1 kmod-md-raid10 kmod-md-raid456 \\\n\t\tkmod-fs-btrfs kmod-fs-cifs kmod-fs-nfs \\\n\t\tkmod-fs-nfsd kmod-fs-ntfs kmod-fs-reiserfs kmod-fs-vfat \\\n\t\tkmod-nls-utf8 kmod-usb-storage-extras kmod-hwmon-drivetemp \\\n\t\tcfdisk e2fsprogs badblocks \\\n\t\tpartx-utils\n\n# The DIR-685 flash layout is kernel in WRGG format, padded and followed\n# by the appended rootfs followed by some reasonable JFFS padding, the\n# remainder will be used by JFFS2 through overlayfs.\n#\n# - For the factory image, the WRGG image includes the rootfs so that the\n#   default firmware will flash it properly as all it knows is WRGG format.\n# - For the sysupgrade, we do not include the rootfs in the kernel image\n#   so it is not needelessly tossed into the RAM by the boot loader.\n#   This will be flashed from OpenWrt userland anyways so we only need\n#   the minimum to make the boot loader happy.\ndefine Device/dlink_dir-685\n\tDEVICE_VENDOR := D-Link\n\tDEVICE_MODEL := DIR-685 Xtreme N Storage Router\n\tDEVICE_DTS := gemini-dlink-dir-685\n\tDEVICE_PACKAGES := $(GEMINI_NAS_PACKAGES) \\\n\t\t\tkmod-rt2800-pci\n\tIMAGES := factory.bin sysupgrade.bin\n\t# Pad to 128k erase blocks with 160 bytes WRGG header\n\tIMAGE/factory.bin := append-kernel | pad-offset 128k 160 | append-rootfs | dir685-pad-rootfs | dir685-image\n\tIMAGE/sysupgrade.bin := append-kernel | pad-offset 128k 160 | dir685-image | append-rootfs | dir685-pad-rootfs | append-metadata\nendef\nTARGET_DEVICES += dlink_dir-685\n\ndefine Device/dlink_dns-313\n\tDEVICE_VENDOR := D-Link\n\tDEVICE_MODEL := DNS-313 1-Bay Network Storage Enclosure\n\tDEVICE_DTS := gemini-dlink-dns-313\n\tDEVICE_PACKAGES := $(GEMINI_NAS_PACKAGES)\n\tBLOCKSIZE := 1k\n\tFILESYSTEMS := ext4\n\tIMAGES := factory.bin.gz\n\tIMAGE/factory.bin.gz := dns313-images | gzip\nendef\nTARGET_DEVICES += dlink_dns-313\n\n# Default images setup used by the StorLink reference designs\ndefine Device/storlink-reference\n\tCOMPILE := copy-kernel-$(1).bin\n\tCOMPILE/copy-kernel-$(1).bin := copy-kernel.bin\n\tIMAGES := factory.bin\n\tFILESYSTEMS := squashfs\n\tIMAGE/factory.bin := append-rootfs | pad-rootfs | pad-to 6144k | \\\n\t\tstorlink-default-images $(1)\n\tDEVICE_PACKAGES := $(GEMINI_NAS_PACKAGES)\nendef\n\ndefine Device/itian_sq201\n\t$(Device/storlink-reference)\n\tDEVICE_VENDOR := ITian\n\tDEVICE_MODEL := Square One SQ201\n\tDEVICE_DTS := gemini-sq201\n\tDEVICE_PACKAGES += kmod-rt61-pci kmod-usb2-pci\nendef\nTARGET_DEVICES += itian_sq201\n\ndefine Device/raidsonic_ib-4220-b\n\t$(Device/storlink-reference)\n\tDEVICE_VENDOR := Raidsonic\n\tDEVICE_MODEL := NAS IB-4220-B\n\tDEVICE_DTS := gemini-nas4220b\nendef\nTARGET_DEVICES += raidsonic_ib-4220-b\n\ndefine Device/storlink_sl93512r\n\t$(Device/storlink-reference)\n\tDEVICE_VENDOR := StorLink\n\tDEVICE_MODEL := SL93512r\n\tDEVICE_DTS := gemini-sl93512r\nendef\nTARGET_DEVICES += storlink_sl93512r\n\n\n# The wiliboard images need some changes to be functional and buildable.\n#\n# The dts would need to use the ecoscentric,redboot-fis-partitions partition\n# parser to get the correct partition offsets and size.\n#\n# The mkfwimage2 call need to be adjusted to reflect the real size of kernel\n# and rootfs. It is expected that the OEM firmware adjusts the on flash\n# partition table with the values defined in the image header.\ndefine Device/wiliboard_wbd111\n\tDEVICE_VENDOR := Wiliboard\n\tDEVICE_MODEL := WBD-111\n\tDEVICE_DTS := gemini-wbd111\n\tKERNEL := kernel-bin | append-dtb | wbd-nops\n\tIMAGES := factory.bin\n\tIMAGE/factory.bin := append-rootfs | pad-rootfs | wiligear-image \"WILI-S.WILIBOARD\"\nendef\n\ndefine Device/wiliboard_wbd222\n\tDEVICE_VENDOR := Wiliboard\n\tDEVICE_MODEL := WBD-222\n\tDEVICE_DTS := gemini-wbd222\n\tKERNEL := kernel-bin | append-dtb | wbd-nops\n\tIMAGES := factory.bin\n\tIMAGE/factory.bin := append-rootfs | pad-rootfs | wiligear-image \"WILI-S.WBD222\"\nendef\n\n$(eval $(call BuildImage))\n"
  },
  {
    "path": "target/linux/gemini/image/copy-kernel/.gitignore",
    "content": "copy-kernel.bin\n"
  },
  {
    "path": "target/linux/gemini/image/copy-kernel/Makefile",
    "content": "#\n# Makefile for Gemin kernel copy stub\n#\n# Copyright (C) 2019 Linus Walleij <linus.walleij@linaro.org>\n#\n# This program is free software; you can redistribute it and/or modify it\n# under the terms of the GNU General Public License version 2 as published\n# by the Free Software Foundation.\n#\n\nAS\t\t:= $(CROSS_COMPILE)as\nOBJCOPY\t\t:= $(CROSS_COMPILE)objcopy\n\nBIN_FLAGS\t:= -O binary -S\n\nSRC_DIR\t\t:= $(CURDIR)/\nOUT_DIR\t\t:= $(if $(O),$(if $(patsubst %/,,$(O)),$(O)/,$(O)),$(SRC_DIR))\n\nall: $(OUT_DIR)copy-kernel.bin\n\n# Don't build dependencies, this may die if $(CC) isn't gcc\ndep:\n\ninstall:\n\n$(OUT_DIR):\n\tmkdir -p $(OUT_DIR)\n\n$(OUT_DIR)%.o : $(SRC_DIR)%.S | $(OUT_DIR)\n\t$(AS) $(ASFLAGS) -k -o $@ $<\n\n$(OUT_DIR)%.bin: $(OUT_DIR)%.o\n\t$(OBJCOPY) $(BIN_FLAGS) $< $@\n\nmrproper: clean\n\nclean:\n\trm -f $(OUT_DIR)copy-kernel.bin $(OUT_DIR)copy-kernel.o\n"
  },
  {
    "path": "target/linux/gemini/image/copy-kernel/copy-kernel.S",
    "content": "\t// Arm assembly to copy the Gemini kernel on Storlink reference\n\t// designs and derived devices with the same flash layout and\n\t// boot loader.\n\t//\n\t// This will execute at 0x01600000\n\t//\n\t// Copies the kernel from two fragments (originally zImage\n\t// and initramdisk) to 0x00400000 making space for a kernel\n\t// image of up to 8 MB except for these 512 bytes used for\n\t// this bootstrap.\n\t//\n\t// 0x01600200 .. 0x017fffff -> 0x00400000 .. 0x005ffdff\n\t// 0x00800000 .. 0x00dfffff -> 0x005ffe00 .. 0x00bffdff\n\n\t// Memory used for this bootstrap\n\t.equ BOOT_HEADROOM,\t0x200\n\n\t.global _start // Stand-alone assembly code\n_start:\n\tmov r1, #0x01600000\n\tmov r2, #0x00400000\n\tmov r3, #0x00200000\n\tadd r1, r1, #BOOT_HEADROOM\n\tsub r3, r3, #BOOT_HEADROOM\ncopyloop1:\n\tldr r0, [r1]\n\tstr r0, [r2]\n\tadd r1, r1, #4\n\tadd r2, r2, #4\n\tsub r3, r3, #4\n\tcmp r3, #0\n\tbne copyloop1\n\tmov r1, #0x00800000\n\tmov r3, #0x00600000\ncopyloop2:\n\tldr r0, [r1]\n\tstr r0, [r2]\n\tadd r1, r1, #4\n\tadd r2, r2, #4\n\tsub r3, r3, #4\n\tcmp r3, #0\n\tbne copyloop2\n\tmov r0, #0x00400000\n\t// Let's go\n\tmov pc, r0\n"
  },
  {
    "path": "target/linux/gemini/image/dns313_gen_hdd_img.sh",
    "content": "#!/bin/sh\n\nset -x\n[ $# -eq 5 ] || {\n\techo \"SYNTAX: $0 <file> <bootfs image> <rootfs image> <bootfs size> <rootfs size>\"\n\texit 1\n}\n\nOUTPUT=\"$1\"\nBOOTFS=\"$2\"\nROOTFS=\"$3\"\nBOOTFSSIZE=\"$4\"\nROOTFSSIZE=\"$5\"\n\nhead=4\nsect=63\n\n# Create one empty partitions followed by the swap partition, then the\n# boot partition with the ./boot/zImage and then the rootfs partition.\n# The swap partition with type 82 is 128 MB since the DNS-313 has 64 MB of\n# memory so we assign twice of that as swap.\n# The boot partition must always be the third partition.\n# The user should use the first (blank) partition for user data storage,\n# this will typically be named /dev/sda1\nset $(ptgen -o $OUTPUT -h $head -s $sect -n -t 83 -p 0 -t 82 -p 128M -t 83 -p ${BOOTFSSIZE}M -t 83 -p ${ROOTFSSIZE}M)\n\n# Swapoffset and swapsize will be $1 and $2\nBOOTOFFSET=\"$(($3 / 512))\"\nBOOTSIZE=\"$(($4 / 512))\"\nROOTFSOFFSET=\"$(($5 / 512))\"\nROOTFSSIZE=\"$(($6 / 512))\"\n\ndd bs=512 if=\"$BOOTFS\" of=\"$OUTPUT\" seek=\"$BOOTOFFSET\" conv=notrunc\ndd bs=512 if=\"$ROOTFS\" of=\"$OUTPUT\" seek=\"$ROOTFSOFFSET\" conv=notrunc\n"
  },
  {
    "path": "target/linux/gemini/patches-5.10/0001-usb-host-fotg2-add-Gemini-specific-handling.patch",
    "content": "From ff887de2f7af17d6264eb946f6b336e6e1521222 Mon Sep 17 00:00:00 2001\nFrom: Linus Walleij <linus.walleij@linaro.org>\nDate: Fri, 21 Apr 2017 22:19:00 +0200\nSubject: [PATCH 1/2] usb: host: fotg2: add Gemini-specific handling\n\nThe Cortina Systems Gemini has bolted on a PHY inside the\nsilicon that can be handled by six bits in a MISC register in\nthe system controller.\n\nIf we are running on Gemini, look up a syscon regmap through\na phandle and enable VBUS and optionally the Mini-B connector.\n\nIf the device is flagged as \"wakeup-source\" using the standard\nDT bindings, we also enable this in the global controller for\nrespective port.\n\nSigned-off-by: Linus Walleij <linus.walleij@linaro.org>\n---\n drivers/usb/host/Kconfig       |  1 +\n drivers/usb/host/fotg210-hcd.c | 76 ++++++++++++++++++++++++++++++++++\n 2 files changed, 77 insertions(+)\n\n--- a/drivers/usb/host/Kconfig\n+++ b/drivers/usb/host/Kconfig\n@@ -392,6 +392,7 @@ config USB_ISP1362_HCD\n config USB_FOTG210_HCD\n \ttristate \"FOTG210 HCD support\"\n \tdepends on USB && HAS_DMA && HAS_IOMEM\n+\tselect MFD_SYSCON\n \thelp\n \t  Faraday FOTG210 is an OTG controller which can be configured as\n \t  an USB2.0 host. It is designed to meet USB2.0 EHCI specification\n--- a/drivers/usb/host/fotg210-hcd.c\n+++ b/drivers/usb/host/fotg210-hcd.c\n@@ -34,6 +34,10 @@\n #include <linux/io.h>\n #include <linux/iopoll.h>\n #include <linux/clk.h>\n+#include <linux/bitops.h>\n+/* For Cortina Gemini */\n+#include <linux/mfd/syscon.h>\n+#include <linux/regmap.h>\n \n #include <asm/byteorder.h>\n #include <asm/irq.h>\n@@ -5553,6 +5557,72 @@ static void fotg210_init(struct fotg210_\n }\n \n /*\n+ * Gemini-specific initialization function, only executed on the\n+ * Gemini SoC using the global misc control register.\n+ */\n+#define GEMINI_GLOBAL_MISC_CTRL\t\t0x30\n+#define GEMINI_MISC_USB0_WAKEUP\t\tBIT(14)\n+#define GEMINI_MISC_USB1_WAKEUP\t\tBIT(15)\n+#define GEMINI_MISC_USB0_VBUS_ON\tBIT(22)\n+#define GEMINI_MISC_USB1_VBUS_ON\tBIT(23)\n+#define GEMINI_MISC_USB0_MINI_B\t\tBIT(29)\n+#define GEMINI_MISC_USB1_MINI_B\t\tBIT(30)\n+\n+static int fotg210_gemini_init(struct device *dev, struct usb_hcd *hcd)\n+{\n+\tstruct device_node *np = dev->of_node;\n+\tstruct regmap *map;\n+\tbool mini_b;\n+\tbool wakeup;\n+\tu32 mask, val;\n+\tint ret;\n+\n+\tmap = syscon_regmap_lookup_by_phandle(np, \"syscon\");\n+\tif (IS_ERR(map)) {\n+\t\tdev_err(dev, \"no syscon\\n\");\n+\t\treturn PTR_ERR(map);\n+\t}\n+\tmini_b = of_property_read_bool(np, \"cortina,gemini-mini-b\");\n+\twakeup = of_property_read_bool(np, \"wakeup-source\");\n+\n+\t/*\n+\t * Figure out if this is USB0 or USB1 by simply checking the\n+\t * physical base address.\n+\t */\n+\tmask = 0;\n+\tif (hcd->rsrc_start == 0x69000000) {\n+\t\tval = GEMINI_MISC_USB1_VBUS_ON;\n+\t\tif (mini_b)\n+\t\t\tval |= GEMINI_MISC_USB1_MINI_B;\n+\t\telse\n+\t\t\tmask |= GEMINI_MISC_USB1_MINI_B;\n+\t\tif (wakeup)\n+\t\t\tval |= GEMINI_MISC_USB1_WAKEUP;\n+\t\telse\n+\t\t\tmask |= GEMINI_MISC_USB1_WAKEUP;\n+\t} else {\n+\t\tval = GEMINI_MISC_USB0_VBUS_ON;\n+\t\tif (mini_b)\n+\t\t\tval |= GEMINI_MISC_USB0_MINI_B;\n+\t\telse\n+\t\t\tmask |= GEMINI_MISC_USB0_MINI_B;\n+\t\tif (wakeup)\n+\t\t\tval |= GEMINI_MISC_USB0_WAKEUP;\n+\t\telse\n+\t\t\tmask |= GEMINI_MISC_USB0_WAKEUP;\n+\t}\n+\n+\tret = regmap_update_bits(map, GEMINI_GLOBAL_MISC_CTRL, mask, val);\n+\tif (ret) {\n+\t\tdev_err(dev, \"failed to initialize Gemini PHY\\n\");\n+\t\treturn ret;\n+\t}\n+\n+\tdev_info(dev, \"initialized Gemini PHY\\n\");\n+\treturn 0;\n+}\n+\n+/**\n  * fotg210_hcd_probe - initialize faraday FOTG210 HCDs\n  *\n  * Allocates basic resources for this USB host controller, and\n@@ -5629,6 +5699,12 @@ static int fotg210_hcd_probe(struct plat\n \n \tfotg210_init(fotg210);\n \n+\tif (of_device_is_compatible(dev->of_node, \"cortina,gemini-usb\")) {\n+\t\tretval = fotg210_gemini_init(dev, hcd);\n+\t\tif (retval)\n+\t\t\tgoto failed_dis_clk;\n+\t}\n+\n \tretval = usb_add_hcd(hcd, irq, IRQF_SHARED);\n \tif (retval) {\n \t\tdev_err(dev, \"failed to add hcd with err %d\\n\", retval);\n"
  },
  {
    "path": "target/linux/gemini/patches-5.10/0002-ARM-dts-Augment-DIR-685-partition-table-for-OpenWrt.patch",
    "content": "From 36ee838bf83c01cff7cb47c7b07be278d2950ac0 Mon Sep 17 00:00:00 2001\nFrom: Linus Walleij <linus.walleij@linaro.org>\nDate: Mon, 11 Mar 2019 15:44:29 +0100\nSubject: [PATCH 2/2] ARM: dts: Augment DIR-685 partition table for OpenWrt\n\nRename the firmware partition so that the firmware MTD\nsplitter will do its job, drop the rootfs arguments as\nthe MTD splitter will set this up automatically.\n\nSigned-off-by: Linus Walleij <linus.walleij@linaro.org>\n---\n arch/arm/boot/dts/gemini-dlink-dir-685.dts | 6 +++---\n 1 file changed, 3 insertions(+), 3 deletions(-)\n\n--- a/arch/arm/boot/dts/gemini-dlink-dir-685.dts\n+++ b/arch/arm/boot/dts/gemini-dlink-dir-685.dts\n@@ -20,7 +20,7 @@\n \t};\n \n \tchosen {\n-\t\tbootargs = \"console=ttyS0,19200n8 root=/dev/sda1 rw rootwait consoleblank=300\";\n+\t\tbootargs = \"console=ttyS0,19200n8 consoleblank=300\";\n \t\tstdout-path = \"uart0:19200n8\";\n \t};\n \n@@ -317,9 +317,9 @@\n \t\t\t\t * this is called \"upgrade\" on the vendor system.\n \t\t\t\t */\n \t\t\t\tpartition@40000 {\n-\t\t\t\t\tlabel = \"upgrade\";\n+\t\t\t\t\tcompatible = \"wrg\";\n+\t\t\t\t\tlabel = \"firmware\";\n \t\t\t\t\treg = <0x00040000 0x01f40000>;\n-\t\t\t\t\tread-only;\n \t\t\t\t};\n \t\t\t\t/* RGDB, Residental Gateway Database? */\n \t\t\t\tpartition@1f80000 {\n"
  },
  {
    "path": "target/linux/gemini/patches-5.15/0001-usb-host-fotg2-add-Gemini-specific-handling.patch",
    "content": "From ff887de2f7af17d6264eb946f6b336e6e1521222 Mon Sep 17 00:00:00 2001\nFrom: Linus Walleij <linus.walleij@linaro.org>\nDate: Fri, 21 Apr 2017 22:19:00 +0200\nSubject: [PATCH 1/2] usb: host: fotg2: add Gemini-specific handling\n\nThe Cortina Systems Gemini has bolted on a PHY inside the\nsilicon that can be handled by six bits in a MISC register in\nthe system controller.\n\nIf we are running on Gemini, look up a syscon regmap through\na phandle and enable VBUS and optionally the Mini-B connector.\n\nIf the device is flagged as \"wakeup-source\" using the standard\nDT bindings, we also enable this in the global controller for\nrespective port.\n\nSigned-off-by: Linus Walleij <linus.walleij@linaro.org>\n---\n drivers/usb/host/Kconfig       |  1 +\n drivers/usb/host/fotg210-hcd.c | 76 ++++++++++++++++++++++++++++++++++\n 2 files changed, 77 insertions(+)\n\n--- a/drivers/usb/host/Kconfig\n+++ b/drivers/usb/host/Kconfig\n@@ -381,6 +381,7 @@ config USB_ISP1362_HCD\n config USB_FOTG210_HCD\n \ttristate \"FOTG210 HCD support\"\n \tdepends on USB && HAS_DMA && HAS_IOMEM\n+\tselect MFD_SYSCON\n \thelp\n \t  Faraday FOTG210 is an OTG controller which can be configured as\n \t  an USB2.0 host. It is designed to meet USB2.0 EHCI specification\n--- a/drivers/usb/host/fotg210-hcd.c\n+++ b/drivers/usb/host/fotg210-hcd.c\n@@ -34,6 +34,10 @@\n #include <linux/io.h>\n #include <linux/iopoll.h>\n #include <linux/clk.h>\n+#include <linux/bitops.h>\n+/* For Cortina Gemini */\n+#include <linux/mfd/syscon.h>\n+#include <linux/regmap.h>\n \n #include <asm/byteorder.h>\n #include <asm/irq.h>\n@@ -5557,6 +5561,72 @@ static void fotg210_init(struct fotg210_\n }\n \n /*\n+ * Gemini-specific initialization function, only executed on the\n+ * Gemini SoC using the global misc control register.\n+ */\n+#define GEMINI_GLOBAL_MISC_CTRL\t\t0x30\n+#define GEMINI_MISC_USB0_WAKEUP\t\tBIT(14)\n+#define GEMINI_MISC_USB1_WAKEUP\t\tBIT(15)\n+#define GEMINI_MISC_USB0_VBUS_ON\tBIT(22)\n+#define GEMINI_MISC_USB1_VBUS_ON\tBIT(23)\n+#define GEMINI_MISC_USB0_MINI_B\t\tBIT(29)\n+#define GEMINI_MISC_USB1_MINI_B\t\tBIT(30)\n+\n+static int fotg210_gemini_init(struct device *dev, struct usb_hcd *hcd)\n+{\n+\tstruct device_node *np = dev->of_node;\n+\tstruct regmap *map;\n+\tbool mini_b;\n+\tbool wakeup;\n+\tu32 mask, val;\n+\tint ret;\n+\n+\tmap = syscon_regmap_lookup_by_phandle(np, \"syscon\");\n+\tif (IS_ERR(map)) {\n+\t\tdev_err(dev, \"no syscon\\n\");\n+\t\treturn PTR_ERR(map);\n+\t}\n+\tmini_b = of_property_read_bool(np, \"cortina,gemini-mini-b\");\n+\twakeup = of_property_read_bool(np, \"wakeup-source\");\n+\n+\t/*\n+\t * Figure out if this is USB0 or USB1 by simply checking the\n+\t * physical base address.\n+\t */\n+\tmask = 0;\n+\tif (hcd->rsrc_start == 0x69000000) {\n+\t\tval = GEMINI_MISC_USB1_VBUS_ON;\n+\t\tif (mini_b)\n+\t\t\tval |= GEMINI_MISC_USB1_MINI_B;\n+\t\telse\n+\t\t\tmask |= GEMINI_MISC_USB1_MINI_B;\n+\t\tif (wakeup)\n+\t\t\tval |= GEMINI_MISC_USB1_WAKEUP;\n+\t\telse\n+\t\t\tmask |= GEMINI_MISC_USB1_WAKEUP;\n+\t} else {\n+\t\tval = GEMINI_MISC_USB0_VBUS_ON;\n+\t\tif (mini_b)\n+\t\t\tval |= GEMINI_MISC_USB0_MINI_B;\n+\t\telse\n+\t\t\tmask |= GEMINI_MISC_USB0_MINI_B;\n+\t\tif (wakeup)\n+\t\t\tval |= GEMINI_MISC_USB0_WAKEUP;\n+\t\telse\n+\t\t\tmask |= GEMINI_MISC_USB0_WAKEUP;\n+\t}\n+\n+\tret = regmap_update_bits(map, GEMINI_GLOBAL_MISC_CTRL, mask, val);\n+\tif (ret) {\n+\t\tdev_err(dev, \"failed to initialize Gemini PHY\\n\");\n+\t\treturn ret;\n+\t}\n+\n+\tdev_info(dev, \"initialized Gemini PHY\\n\");\n+\treturn 0;\n+}\n+\n+/**\n  * fotg210_hcd_probe - initialize faraday FOTG210 HCDs\n  *\n  * Allocates basic resources for this USB host controller, and\n@@ -5633,6 +5703,12 @@ static int fotg210_hcd_probe(struct plat\n \n \tfotg210_init(fotg210);\n \n+\tif (of_device_is_compatible(dev->of_node, \"cortina,gemini-usb\")) {\n+\t\tretval = fotg210_gemini_init(dev, hcd);\n+\t\tif (retval)\n+\t\t\tgoto failed_dis_clk;\n+\t}\n+\n \tretval = usb_add_hcd(hcd, irq, IRQF_SHARED);\n \tif (retval) {\n \t\tdev_err(dev, \"failed to add hcd with err %d\\n\", retval);\n"
  },
  {
    "path": "target/linux/gemini/patches-5.15/0002-ARM-dts-Augment-DIR-685-partition-table-for-OpenWrt.patch",
    "content": "From 36ee838bf83c01cff7cb47c7b07be278d2950ac0 Mon Sep 17 00:00:00 2001\nFrom: Linus Walleij <linus.walleij@linaro.org>\nDate: Mon, 11 Mar 2019 15:44:29 +0100\nSubject: [PATCH 2/2] ARM: dts: Augment DIR-685 partition table for OpenWrt\n\nRename the firmware partition so that the firmware MTD\nsplitter will do its job, drop the rootfs arguments as\nthe MTD splitter will set this up automatically.\n\nSigned-off-by: Linus Walleij <linus.walleij@linaro.org>\n---\n arch/arm/boot/dts/gemini-dlink-dir-685.dts | 6 +++---\n 1 file changed, 3 insertions(+), 3 deletions(-)\n\n--- a/arch/arm/boot/dts/gemini-dlink-dir-685.dts\n+++ b/arch/arm/boot/dts/gemini-dlink-dir-685.dts\n@@ -20,7 +20,7 @@\n \t};\n \n \tchosen {\n-\t\tbootargs = \"console=ttyS0,19200n8 root=/dev/sda1 rw rootwait consoleblank=300\";\n+\t\tbootargs = \"console=ttyS0,19200n8 consoleblank=300\";\n \t\tstdout-path = \"uart0:19200n8\";\n \t};\n \n@@ -317,9 +317,9 @@\n \t\t\t\t * this is called \"upgrade\" on the vendor system.\n \t\t\t\t */\n \t\t\t\tpartition@40000 {\n-\t\t\t\t\tlabel = \"upgrade\";\n+\t\t\t\t\tcompatible = \"wrg\";\n+\t\t\t\t\tlabel = \"firmware\";\n \t\t\t\t\treg = <0x00040000 0x01f40000>;\n-\t\t\t\t\tread-only;\n \t\t\t\t};\n \t\t\t\t/* RGDB, Residental Gateway Database? */\n \t\t\t\tpartition@1f80000 {\n"
  },
  {
    "path": "target/linux/generic/PATCHES",
    "content": "The patches-* subdirectories contain the kernel patches applied for every\nOpenWrt target. All patches should be named 'NNN-lowercase_shortname.patch'\nand sorted into the following categories:\n\n0xx - upstream backports\n1xx - code awaiting upstream merge\n2xx - kernel build / config / header patches\n3xx - architecture specific patches\n4xx - mtd related patches (subsystem and drivers)\n5xx - filesystem related patches\n6xx - generic network patches\n7xx - network / phy driver patches\n8xx - other drivers\n9xx - uncategorized other patches\n\nALL patches must be in a way that they are potentially upstreamable, meaning:\n\n- they must contain a proper subject\n- they must contain a proper commit message explaining what they change\n- they must contain a valid Signed-off-by line\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/010-Kbuild-don-t-hardcode-path-to-awk-in-scripts-ld-vers.patch",
    "content": "From 13b1ecc3401653a355798eb1dee10cc1608202f4 Mon Sep 17 00:00:00 2001\nFrom: Felix Fietkau <nbd@nbd.name>\nDate: Mon, 18 Jan 2016 12:27:49 +0100\nSubject: [PATCH 33/34] Kbuild: don't hardcode path to awk in\n scripts/ld-version.sh\n\nOn some systems /usr/bin/awk does not exist, or is broken. Find it via\n$PATH instead.\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n scripts/ld-version.sh | 4 +++-\n 1 file changed, 3 insertions(+), 1 deletion(-)\n\n--- a/scripts/ld-version.sh\n+++ b/scripts/ld-version.sh\n@@ -1,6 +1,7 @@\n-#!/usr/bin/awk -f\n+#!/bin/sh\n # SPDX-License-Identifier: GPL-2.0\n # extract linker version number from stdin and turn into single number\n+exec awk '\n \t{\n \tgsub(\".*\\\\)\", \"\");\n \tgsub(\".*version \", \"\");\n@@ -9,3 +10,4 @@\n \tprint a[1]*100000000 + a[2]*1000000 + a[3]*10000;\n \texit\n \t}\n+'\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/011-kbuild-export-SUBARCH.patch",
    "content": "From 173019b66dcc9d68ad9333aa744dad1e369b5aa8 Mon Sep 17 00:00:00 2001\nFrom: Felix Fietkau <nbd@nbd.name>\nDate: Sun, 9 Jul 2017 00:26:53 +0200\nSubject: [PATCH 34/34] kernel: add compile fix for linux 4.9 on x86\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n Makefile | 4 ++--\n 1 file changed, 2 insertions(+), 2 deletions(-)\n\n--- a/Makefile\n+++ b/Makefile\n@@ -507,7 +507,7 @@ KBUILD_LDFLAGS_MODULE :=\n KBUILD_LDFLAGS :=\n CLANG_FLAGS :=\n \n-export ARCH SRCARCH CONFIG_SHELL BASH HOSTCC KBUILD_HOSTCFLAGS CROSS_COMPILE LD CC\n+export ARCH SRCARCH SUBARCH CONFIG_SHELL BASH HOSTCC KBUILD_HOSTCFLAGS CROSS_COMPILE LD CC\n export CPP AR NM STRIP OBJCOPY OBJDUMP READELF PAHOLE RESOLVE_BTFIDS LEX YACC AWK INSTALLKERNEL\n export PERL PYTHON PYTHON3 CHECK CHECKFLAGS MAKE UTS_MACHINE HOSTCXX\n export KGZIP KBZIP2 KLZOP LZMA LZ4 XZ ZSTD\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/026-power-reset-linkstation-poweroff-add-missing-put_dev.patch",
    "content": "From 1027a42c25cbf8cfc4ade6503c5110aae04866af Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Daniel=20Gonz=C3=A1lez=20Cabanelas?= <dgcbueu@gmail.com>\nDate: Fri, 16 Oct 2020 20:22:37 +0200\nSubject: [PATCH] power: reset: linkstation-poweroff: add missing put_device()\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nThe of_mdio_find_bus() takes a reference to the underlying device\nstructure, we should release that reference using a put_device() call.\n\nSigned-off-by: Daniel González Cabanelas <dgcbueu@gmail.com>\nSigned-off-by: Sebastian Reichel <sre@kernel.org>\n---\n drivers/power/reset/linkstation-poweroff.c | 1 +\n 1 file changed, 1 insertion(+)\n\n--- a/drivers/power/reset/linkstation-poweroff.c\n+++ b/drivers/power/reset/linkstation-poweroff.c\n@@ -113,6 +113,7 @@ static int __init linkstation_poweroff_i\n \t\treturn -EPROBE_DEFER;\n \n \tphydev = phy_find_first(bus);\n+\tput_device(&bus->dev);\n \tif (!phydev)\n \t\treturn -EPROBE_DEFER;\n \n"
  },
  {
    "path": "target/linux/generic/backport-5.10/050-v5.16-00-MIPS-uasm-Enable-muhu-opcode-for-MIPS-R6.patch",
    "content": "From: Johan Almbladh <johan.almbladh@anyfinetworks.com>\nDate: Tue, 5 Oct 2021 18:54:02 +0200\nSubject: [PATCH] MIPS: uasm: Enable muhu opcode for MIPS R6\n\nEnable the 'muhu' instruction, complementing the existing 'mulu', needed\nto implement a MIPS32 BPF JIT.\n\nAlso fix a typo in the existing definition of 'dmulu'.\n\nSigned-off-by: Tony Ambardar <Tony.Ambardar@gmail.com>\n\nThis patch is a dependency for my 32-bit MIPS eBPF JIT.\n\nSigned-off-by: Johan Almbladh <johan.almbladh@anyfinetworks.com>\n---\n\n--- a/arch/mips/include/asm/uasm.h\n+++ b/arch/mips/include/asm/uasm.h\n@@ -145,6 +145,7 @@ Ip_u1(_mtlo);\n Ip_u3u1u2(_mul);\n Ip_u1u2(_multu);\n Ip_u3u1u2(_mulu);\n+Ip_u3u1u2(_muhu);\n Ip_u3u1u2(_nor);\n Ip_u3u1u2(_or);\n Ip_u2u1u3(_ori);\n--- a/arch/mips/mm/uasm-mips.c\n+++ b/arch/mips/mm/uasm-mips.c\n@@ -90,7 +90,7 @@ static const struct insn insn_table[insn\n \t\t\t\tRS | RT | RD},\n \t[insn_dmtc0]\t= {M(cop0_op, dmtc_op, 0, 0, 0, 0), RT | RD | SET},\n \t[insn_dmultu]\t= {M(spec_op, 0, 0, 0, 0, dmultu_op), RS | RT},\n-\t[insn_dmulu]\t= {M(spec_op, 0, 0, 0, dmult_dmul_op, dmultu_op),\n+\t[insn_dmulu]\t= {M(spec_op, 0, 0, 0, dmultu_dmulu_op, dmultu_op),\n \t\t\t\tRS | RT | RD},\n \t[insn_drotr]\t= {M(spec_op, 1, 0, 0, 0, dsrl_op), RT | RD | RE},\n \t[insn_drotr32]\t= {M(spec_op, 1, 0, 0, 0, dsrl32_op), RT | RD | RE},\n@@ -150,6 +150,8 @@ static const struct insn insn_table[insn\n \t[insn_mtlo]\t= {M(spec_op, 0, 0, 0, 0, mtlo_op), RS},\n \t[insn_mulu]\t= {M(spec_op, 0, 0, 0, multu_mulu_op, multu_op),\n \t\t\t\tRS | RT | RD},\n+\t[insn_muhu]\t= {M(spec_op, 0, 0, 0, multu_muhu_op, multu_op),\n+\t\t\t\tRS | RT | RD},\n #ifndef CONFIG_CPU_MIPSR6\n \t[insn_mul]\t= {M(spec2_op, 0, 0, 0, 0, mul_op), RS | RT | RD},\n #else\n--- a/arch/mips/mm/uasm.c\n+++ b/arch/mips/mm/uasm.c\n@@ -59,7 +59,7 @@ enum opcode {\n \tinsn_lddir, insn_ldpte, insn_ldx, insn_lh, insn_lhu, insn_ll, insn_lld,\n \tinsn_lui, insn_lw, insn_lwu, insn_lwx, insn_mfc0, insn_mfhc0, insn_mfhi,\n \tinsn_mflo, insn_modu, insn_movn, insn_movz, insn_mtc0, insn_mthc0,\n-\tinsn_mthi, insn_mtlo, insn_mul, insn_multu, insn_mulu, insn_nor,\n+\tinsn_mthi, insn_mtlo, insn_mul, insn_multu, insn_mulu, insn_muhu, insn_nor,\n \tinsn_or, insn_ori, insn_pref, insn_rfe, insn_rotr, insn_sb, insn_sc,\n \tinsn_scd, insn_seleqz, insn_selnez, insn_sd, insn_sh, insn_sll,\n \tinsn_sllv, insn_slt, insn_slti, insn_sltiu, insn_sltu, insn_sra,\n@@ -344,6 +344,7 @@ I_u1(_mtlo)\n I_u3u1u2(_mul)\n I_u1u2(_multu)\n I_u3u1u2(_mulu)\n+I_u3u1u2(_muhu)\n I_u3u1u2(_nor)\n I_u3u1u2(_or)\n I_u2u1u3(_ori)\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/050-v5.16-01-mips-uasm-Add-workaround-for-Loongson-2F-nop-CPU-err.patch",
    "content": "From: Johan Almbladh <johan.almbladh@anyfinetworks.com>\nDate: Tue, 5 Oct 2021 18:54:03 +0200\nSubject: [PATCH] mips: uasm: Add workaround for Loongson-2F nop CPU errata\n\nThis patch implements a workaround for the Loongson-2F nop in generated,\ncode, if the existing option CONFIG_CPU_NOP_WORKAROUND is set. Before,\nthe binutils option -mfix-loongson2f-nop was enabled, but no workaround\nwas done when emitting MIPS code. Now, the nop pseudo instruction is\nemitted as \"or ax,ax,zero\" instead of the default \"sll zero,zero,0\". This\nis consistent with the workaround implemented by binutils.\n\nLink: https://sourceware.org/legacy-ml/binutils/2009-11/msg00387.html\n\nSigned-off-by: Johan Almbladh <johan.almbladh@anyfinetworks.com>\nReviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>\n---\n\n--- a/arch/mips/include/asm/uasm.h\n+++ b/arch/mips/include/asm/uasm.h\n@@ -249,7 +249,11 @@ static inline void uasm_l##lb(struct uas\n #define uasm_i_bnezl(buf, rs, off) uasm_i_bnel(buf, rs, 0, off)\n #define uasm_i_ehb(buf) uasm_i_sll(buf, 0, 0, 3)\n #define uasm_i_move(buf, a, b) UASM_i_ADDU(buf, a, 0, b)\n+#ifdef CONFIG_CPU_NOP_WORKAROUNDS\n+#define uasm_i_nop(buf) uasm_i_or(buf, 1, 1, 0)\n+#else\n #define uasm_i_nop(buf) uasm_i_sll(buf, 0, 0, 0)\n+#endif\n #define uasm_i_ssnop(buf) uasm_i_sll(buf, 0, 0, 1)\n \n static inline void uasm_i_drotr_safe(u32 **p, unsigned int a1,\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/050-v5.16-02-mips-bpf-Add-eBPF-JIT-for-32-bit-MIPS.patch",
    "content": "From: Johan Almbladh <johan.almbladh@anyfinetworks.com>\nDate: Tue, 5 Oct 2021 18:54:04 +0200\nSubject: [PATCH] mips: bpf: Add eBPF JIT for 32-bit MIPS\n\nThis is an implementation of an eBPF JIT for 32-bit MIPS I-V and MIPS32.\nThe implementation supports all 32-bit and 64-bit ALU and JMP operations,\nincluding the recently-added atomics. 64-bit div/mod and 64-bit atomics\nare implemented using function calls to math64 and atomic64 functions,\nrespectively. All 32-bit operations are implemented natively by the JIT,\nexcept if the CPU lacks ll/sc instructions.\n\nRegister mapping\n================\nAll 64-bit eBPF registers are mapped to native 32-bit MIPS register pairs,\nand does not use any stack scratch space for register swapping. This means\nthat all eBPF register data is kept in CPU registers all the time, and\nthis simplifies the register management a lot. It also reduces the JIT's\npressure on temporary registers since we do not have to move data around.\n\nNative register pairs are ordered according to CPU endiannes, following\nthe O32 calling convention for passing 64-bit arguments and return values.\nThe eBPF return value, arguments and callee-saved registers are mapped to\ntheir native MIPS equivalents.\n\nSince the 32 highest bits in the eBPF FP (frame pointer) register are\nalways zero, only one general-purpose register is actually needed for the\nmapping. The MIPS fp register is used for this purpose. The high bits are\nmapped to MIPS register r0. This saves us one CPU register, which is much\nneeded for temporaries, while still allowing us to treat the R10 (FP)\nregister just like any other eBPF register in the JIT.\n\nThe MIPS gp (global pointer) and at (assembler temporary) registers are\nused as internal temporary registers for constant blinding. CPU registers\nt6-t9 are used internally by the JIT when constructing more complex 64-bit\noperations. This is precisely what is needed - two registers to store an\noperand value, and two more as scratch registers when performing the\noperation.\n\nThe register mapping is shown below.\n\n    R0 - $v1, $v0   return value\n    R1 - $a1, $a0   argument 1, passed in registers\n    R2 - $a3, $a2   argument 2, passed in registers\n    R3 - $t1, $t0   argument 3, passed on stack\n    R4 - $t3, $t2   argument 4, passed on stack\n    R5 - $t4, $t3   argument 5, passed on stack\n    R6 - $s1, $s0   callee-saved\n    R7 - $s3, $s2   callee-saved\n    R8 - $s5, $s4   callee-saved\n    R9 - $s7, $s6   callee-saved\n    FP - $r0, $fp   32-bit frame pointer\n    AX - $gp, $at   constant-blinding\n         $t6 - $t9  unallocated, JIT temporaries\n\nJump offsets\n============\nThe JIT tries to map all conditional JMP operations to MIPS conditional\nPC-relative branches. The MIPS branch offset field is 18 bits, in bytes,\nwhich is equivalent to the eBPF 16-bit instruction offset. However, since\nthe JIT may emit more than one CPU instruction per eBPF instruction, the\nfield width may overflow. If that happens, the JIT converts the long\nconditional jump to a short PC-relative branch with the condition\ninverted, jumping over a long unconditional absolute jmp (j).\n\nThis conversion will change the instruction offset mapping used for jumps,\nand may in turn result in more branch offset overflows. The JIT therefore\ndry-runs the translation until no more branches are converted and the\noffsets do not change anymore. There is an upper bound on this of course,\nand if the JIT hits that limit, the last two iterations are run with all\nbranches being converted.\n\nTail call count\n===============\nThe current tail call count is stored in the 16-byte area of the caller's\nstack frame that is reserved for the callee in the o32 ABI. The value is\ninitialized in the prologue, and propagated to the tail-callee by skipping\nthe initialization instructions when emitting the tail call.\n\nSigned-off-by: Johan Almbladh <johan.almbladh@anyfinetworks.com>\n---\n create mode 100644 arch/mips/net/bpf_jit_comp.c\n create mode 100644 arch/mips/net/bpf_jit_comp.h\n create mode 100644 arch/mips/net/bpf_jit_comp32.c\n\n--- a/arch/mips/net/Makefile\n+++ b/arch/mips/net/Makefile\n@@ -2,4 +2,9 @@\n # MIPS networking code\n \n obj-$(CONFIG_MIPS_CBPF_JIT) += bpf_jit.o bpf_jit_asm.o\n-obj-$(CONFIG_MIPS_EBPF_JIT) += ebpf_jit.o\n+\n+ifeq ($(CONFIG_32BIT),y)\n+        obj-$(CONFIG_MIPS_EBPF_JIT) += bpf_jit_comp.o bpf_jit_comp32.o\n+else\n+        obj-$(CONFIG_MIPS_EBPF_JIT) += ebpf_jit.o\n+endif\n--- /dev/null\n+++ b/arch/mips/net/bpf_jit_comp.c\n@@ -0,0 +1,1020 @@\n+// SPDX-License-Identifier: GPL-2.0-only\n+/*\n+ * Just-In-Time compiler for eBPF bytecode on MIPS.\n+ * Implementation of JIT functions common to 32-bit and 64-bit CPUs.\n+ *\n+ * Copyright (c) 2021 Anyfi Networks AB.\n+ * Author: Johan Almbladh <johan.almbladh@gmail.com>\n+ *\n+ * Based on code and ideas from\n+ * Copyright (c) 2017 Cavium, Inc.\n+ * Copyright (c) 2017 Shubham Bansal <illusionist.neo@gmail.com>\n+ * Copyright (c) 2011 Mircea Gherzan <mgherzan@gmail.com>\n+ */\n+\n+/*\n+ * Code overview\n+ * =============\n+ *\n+ * - bpf_jit_comp.h\n+ *   Common definitions and utilities.\n+ *\n+ * - bpf_jit_comp.c\n+ *   Implementation of JIT top-level logic and exported JIT API functions.\n+ *   Implementation of internal operations shared by 32-bit and 64-bit code.\n+ *   JMP and ALU JIT control code, register control code, shared ALU and\n+ *   JMP/JMP32 JIT operations.\n+ *\n+ * - bpf_jit_comp32.c\n+ *   Implementation of functions to JIT prologue, epilogue and a single eBPF\n+ *   instruction for 32-bit MIPS CPUs. The functions use shared operations\n+ *   where possible, and implement the rest for 32-bit MIPS such as ALU64\n+ *   operations.\n+ *\n+ * - bpf_jit_comp64.c\n+ *   Ditto, for 64-bit MIPS CPUs.\n+ *\n+ * Zero and sign extension\n+ * ========================\n+ * 32-bit MIPS instructions on 64-bit MIPS registers use sign extension,\n+ * but the eBPF instruction set mandates zero extension. We let the verifier\n+ * insert explicit zero-extensions after 32-bit ALU operations, both for\n+ * 32-bit and 64-bit MIPS JITs. Conditional JMP32 operations on 64-bit MIPs\n+ * are JITed with sign extensions inserted when so expected.\n+ *\n+ * ALU operations\n+ * ==============\n+ * ALU operations on 32/64-bit MIPS and ALU64 operations on 64-bit MIPS are\n+ * JITed in the following steps. ALU64 operations on 32-bit MIPS are more\n+ * complicated and therefore only processed by special implementations in\n+ * step (3).\n+ *\n+ * 1) valid_alu_i:\n+ *    Determine if an immediate operation can be emitted as such, or if\n+ *    we must fall back to the register version.\n+ *\n+ * 2) rewrite_alu_i:\n+ *    Convert BPF operation and immediate value to a canonical form for\n+ *    JITing. In some degenerate cases this form may be a no-op.\n+ *\n+ * 3) emit_alu_{i,i64,r,64}:\n+ *    Emit instructions for an ALU or ALU64 immediate or register operation.\n+ *\n+ * JMP operations\n+ * ==============\n+ * JMP and JMP32 operations require an JIT instruction offset table for\n+ * translating the jump offset. This table is computed by dry-running the\n+ * JIT without actually emitting anything. However, the computed PC-relative\n+ * offset may overflow the 18-bit offset field width of the native MIPS\n+ * branch instruction. In such cases, the long jump is converted into the\n+ * following sequence.\n+ *\n+ *    <branch> !<cond> +2    Inverted PC-relative branch\n+ *    nop                    Delay slot\n+ *    j <offset>             Unconditional absolute long jump\n+ *    nop                    Delay slot\n+ *\n+ * Since this converted sequence alters the offset table, all offsets must\n+ * be re-calculated. This may in turn trigger new branch conversions, so\n+ * the process is repeated until no further changes are made. Normally it\n+ * completes in 1-2 iterations. If JIT_MAX_ITERATIONS should reached, we\n+ * fall back to converting every remaining jump operation. The branch\n+ * conversion is independent of how the JMP or JMP32 condition is JITed.\n+ *\n+ * JMP32 and JMP operations are JITed as follows.\n+ *\n+ * 1) setup_jmp_{i,r}:\n+ *    Convert jump conditional and offset into a form that can be JITed.\n+ *    This form may be a no-op, a canonical form, or an inverted PC-relative\n+ *    jump if branch conversion is necessary.\n+ *\n+ * 2) valid_jmp_i:\n+ *    Determine if an immediate operations can be emitted as such, or if\n+ *    we must fall back to the register version. Applies to JMP32 for 32-bit\n+ *    MIPS, and both JMP and JMP32 for 64-bit MIPS.\n+ *\n+ * 3) emit_jmp_{i,i64,r,r64}:\n+ *    Emit instructions for an JMP or JMP32 immediate or register operation.\n+ *\n+ * 4) finish_jmp_{i,r}:\n+ *    Emit any instructions needed to finish the jump. This includes a nop\n+ *    for the delay slot if a branch was emitted, and a long absolute jump\n+ *    if the branch was converted.\n+ */\n+\n+#include <linux/limits.h>\n+#include <linux/bitops.h>\n+#include <linux/errno.h>\n+#include <linux/filter.h>\n+#include <linux/bpf.h>\n+#include <linux/slab.h>\n+#include <asm/bitops.h>\n+#include <asm/cacheflush.h>\n+#include <asm/cpu-features.h>\n+#include <asm/isa-rev.h>\n+#include <asm/uasm.h>\n+\n+#include \"bpf_jit_comp.h\"\n+\n+/* Convenience macros for descriptor access */\n+#define CONVERTED(desc)\t((desc) & JIT_DESC_CONVERT)\n+#define INDEX(desc)\t((desc) & ~JIT_DESC_CONVERT)\n+\n+/*\n+ * Push registers on the stack, starting at a given depth from the stack\n+ * pointer and increasing. The next depth to be written is returned.\n+ */\n+int push_regs(struct jit_context *ctx, u32 mask, u32 excl, int depth)\n+{\n+\tint reg;\n+\n+\tfor (reg = 0; reg < BITS_PER_BYTE * sizeof(mask); reg++)\n+\t\tif (mask & BIT(reg)) {\n+\t\t\tif ((excl & BIT(reg)) == 0) {\n+\t\t\t\tif (sizeof(long) == 4)\n+\t\t\t\t\temit(ctx, sw, reg, depth, MIPS_R_SP);\n+\t\t\t\telse /* sizeof(long) == 8 */\n+\t\t\t\t\temit(ctx, sd, reg, depth, MIPS_R_SP);\n+\t\t\t}\n+\t\t\tdepth += sizeof(long);\n+\t\t}\n+\n+\tctx->stack_used = max((int)ctx->stack_used, depth);\n+\treturn depth;\n+}\n+\n+/*\n+ * Pop registers from the stack, starting at a given depth from the stack\n+ * pointer and increasing. The next depth to be read is returned.\n+ */\n+int pop_regs(struct jit_context *ctx, u32 mask, u32 excl, int depth)\n+{\n+\tint reg;\n+\n+\tfor (reg = 0; reg < BITS_PER_BYTE * sizeof(mask); reg++)\n+\t\tif (mask & BIT(reg)) {\n+\t\t\tif ((excl & BIT(reg)) == 0) {\n+\t\t\t\tif (sizeof(long) == 4)\n+\t\t\t\t\temit(ctx, lw, reg, depth, MIPS_R_SP);\n+\t\t\t\telse /* sizeof(long) == 8 */\n+\t\t\t\t\temit(ctx, ld, reg, depth, MIPS_R_SP);\n+\t\t\t}\n+\t\t\tdepth += sizeof(long);\n+\t\t}\n+\n+\treturn depth;\n+}\n+\n+/* Compute the 28-bit jump target address from a BPF program location */\n+int get_target(struct jit_context *ctx, u32 loc)\n+{\n+\tu32 index = INDEX(ctx->descriptors[loc]);\n+\tunsigned long pc = (unsigned long)&ctx->target[ctx->jit_index];\n+\tunsigned long addr = (unsigned long)&ctx->target[index];\n+\n+\tif (!ctx->target)\n+\t\treturn 0;\n+\n+\tif ((addr ^ pc) & ~MIPS_JMP_MASK)\n+\t\treturn -1;\n+\n+\treturn addr & MIPS_JMP_MASK;\n+}\n+\n+/* Compute the PC-relative offset to relative BPF program offset */\n+int get_offset(const struct jit_context *ctx, int off)\n+{\n+\treturn (INDEX(ctx->descriptors[ctx->bpf_index + off]) -\n+\t\tctx->jit_index - 1) * sizeof(u32);\n+}\n+\n+/* dst = imm (register width) */\n+void emit_mov_i(struct jit_context *ctx, u8 dst, s32 imm)\n+{\n+\tif (imm >= -0x8000 && imm <= 0x7fff) {\n+\t\temit(ctx, addiu, dst, MIPS_R_ZERO, imm);\n+\t} else {\n+\t\temit(ctx, lui, dst, (s16)((u32)imm >> 16));\n+\t\temit(ctx, ori, dst, dst, (u16)(imm & 0xffff));\n+\t}\n+\tclobber_reg(ctx, dst);\n+}\n+\n+/* dst = src (register width) */\n+void emit_mov_r(struct jit_context *ctx, u8 dst, u8 src)\n+{\n+\temit(ctx, ori, dst, src, 0);\n+\tclobber_reg(ctx, dst);\n+}\n+\n+/* Validate ALU immediate range */\n+bool valid_alu_i(u8 op, s32 imm)\n+{\n+\tswitch (BPF_OP(op)) {\n+\tcase BPF_NEG:\n+\tcase BPF_LSH:\n+\tcase BPF_RSH:\n+\tcase BPF_ARSH:\n+\t\t/* All legal eBPF values are valid */\n+\t\treturn true;\n+\tcase BPF_ADD:\n+\t\t/* imm must be 16 bits */\n+\t\treturn imm >= -0x8000 && imm <= 0x7fff;\n+\tcase BPF_SUB:\n+\t\t/* -imm must be 16 bits */\n+\t\treturn imm >= -0x7fff && imm <= 0x8000;\n+\tcase BPF_AND:\n+\tcase BPF_OR:\n+\tcase BPF_XOR:\n+\t\t/* imm must be 16 bits unsigned */\n+\t\treturn imm >= 0 && imm <= 0xffff;\n+\tcase BPF_MUL:\n+\t\t/* imm must be zero or a positive power of two */\n+\t\treturn imm == 0 || (imm > 0 && is_power_of_2(imm));\n+\tcase BPF_DIV:\n+\tcase BPF_MOD:\n+\t\t/* imm must be an 17-bit power of two */\n+\t\treturn (u32)imm <= 0x10000 && is_power_of_2((u32)imm);\n+\t}\n+\treturn false;\n+}\n+\n+/* Rewrite ALU immediate operation */\n+bool rewrite_alu_i(u8 op, s32 imm, u8 *alu, s32 *val)\n+{\n+\tbool act = true;\n+\n+\tswitch (BPF_OP(op)) {\n+\tcase BPF_LSH:\n+\tcase BPF_RSH:\n+\tcase BPF_ARSH:\n+\tcase BPF_ADD:\n+\tcase BPF_SUB:\n+\tcase BPF_OR:\n+\tcase BPF_XOR:\n+\t\t/* imm == 0 is a no-op */\n+\t\tact = imm != 0;\n+\t\tbreak;\n+\tcase BPF_MUL:\n+\t\tif (imm == 1) {\n+\t\t\t/* dst * 1 is a no-op */\n+\t\t\tact = false;\n+\t\t} else if (imm == 0) {\n+\t\t\t/* dst * 0 is dst & 0 */\n+\t\t\top = BPF_AND;\n+\t\t} else {\n+\t\t\t/* dst * (1 << n) is dst << n */\n+\t\t\top = BPF_LSH;\n+\t\t\timm = ilog2(abs(imm));\n+\t\t}\n+\t\tbreak;\n+\tcase BPF_DIV:\n+\t\tif (imm == 1) {\n+\t\t\t/* dst / 1 is a no-op */\n+\t\t\tact = false;\n+\t\t} else {\n+\t\t\t/* dst / (1 << n) is dst >> n */\n+\t\t\top = BPF_RSH;\n+\t\t\timm = ilog2(imm);\n+\t\t}\n+\t\tbreak;\n+\tcase BPF_MOD:\n+\t\t/* dst % (1 << n) is dst & ((1 << n) - 1) */\n+\t\top = BPF_AND;\n+\t\timm--;\n+\t\tbreak;\n+\t}\n+\n+\t*alu = op;\n+\t*val = imm;\n+\treturn act;\n+}\n+\n+/* ALU immediate operation (32-bit) */\n+void emit_alu_i(struct jit_context *ctx, u8 dst, s32 imm, u8 op)\n+{\n+\tswitch (BPF_OP(op)) {\n+\t/* dst = -dst */\n+\tcase BPF_NEG:\n+\t\temit(ctx, subu, dst, MIPS_R_ZERO, dst);\n+\t\tbreak;\n+\t/* dst = dst & imm */\n+\tcase BPF_AND:\n+\t\temit(ctx, andi, dst, dst, (u16)imm);\n+\t\tbreak;\n+\t/* dst = dst | imm */\n+\tcase BPF_OR:\n+\t\temit(ctx, ori, dst, dst, (u16)imm);\n+\t\tbreak;\n+\t/* dst = dst ^ imm */\n+\tcase BPF_XOR:\n+\t\temit(ctx, xori, dst, dst, (u16)imm);\n+\t\tbreak;\n+\t/* dst = dst << imm */\n+\tcase BPF_LSH:\n+\t\temit(ctx, sll, dst, dst, imm);\n+\t\tbreak;\n+\t/* dst = dst >> imm */\n+\tcase BPF_RSH:\n+\t\temit(ctx, srl, dst, dst, imm);\n+\t\tbreak;\n+\t/* dst = dst >> imm (arithmetic) */\n+\tcase BPF_ARSH:\n+\t\temit(ctx, sra, dst, dst, imm);\n+\t\tbreak;\n+\t/* dst = dst + imm */\n+\tcase BPF_ADD:\n+\t\temit(ctx, addiu, dst, dst, imm);\n+\t\tbreak;\n+\t/* dst = dst - imm */\n+\tcase BPF_SUB:\n+\t\temit(ctx, addiu, dst, dst, -imm);\n+\t\tbreak;\n+\t}\n+\tclobber_reg(ctx, dst);\n+}\n+\n+/* ALU register operation (32-bit) */\n+void emit_alu_r(struct jit_context *ctx, u8 dst, u8 src, u8 op)\n+{\n+\tswitch (BPF_OP(op)) {\n+\t/* dst = dst & src */\n+\tcase BPF_AND:\n+\t\temit(ctx, and, dst, dst, src);\n+\t\tbreak;\n+\t/* dst = dst | src */\n+\tcase BPF_OR:\n+\t\temit(ctx, or, dst, dst, src);\n+\t\tbreak;\n+\t/* dst = dst ^ src */\n+\tcase BPF_XOR:\n+\t\temit(ctx, xor, dst, dst, src);\n+\t\tbreak;\n+\t/* dst = dst << src */\n+\tcase BPF_LSH:\n+\t\temit(ctx, sllv, dst, dst, src);\n+\t\tbreak;\n+\t/* dst = dst >> src */\n+\tcase BPF_RSH:\n+\t\temit(ctx, srlv, dst, dst, src);\n+\t\tbreak;\n+\t/* dst = dst >> src (arithmetic) */\n+\tcase BPF_ARSH:\n+\t\temit(ctx, srav, dst, dst, src);\n+\t\tbreak;\n+\t/* dst = dst + src */\n+\tcase BPF_ADD:\n+\t\temit(ctx, addu, dst, dst, src);\n+\t\tbreak;\n+\t/* dst = dst - src */\n+\tcase BPF_SUB:\n+\t\temit(ctx, subu, dst, dst, src);\n+\t\tbreak;\n+\t/* dst = dst * src */\n+\tcase BPF_MUL:\n+\t\tif (cpu_has_mips32r1 || cpu_has_mips32r6) {\n+\t\t\temit(ctx, mul, dst, dst, src);\n+\t\t} else {\n+\t\t\temit(ctx, multu, dst, src);\n+\t\t\temit(ctx, mflo, dst);\n+\t\t}\n+\t\tbreak;\n+\t/* dst = dst / src */\n+\tcase BPF_DIV:\n+\t\tif (cpu_has_mips32r6) {\n+\t\t\temit(ctx, divu_r6, dst, dst, src);\n+\t\t} else {\n+\t\t\temit(ctx, divu, dst, src);\n+\t\t\temit(ctx, mflo, dst);\n+\t\t}\n+\t\tbreak;\n+\t/* dst = dst % src */\n+\tcase BPF_MOD:\n+\t\tif (cpu_has_mips32r6) {\n+\t\t\temit(ctx, modu, dst, dst, src);\n+\t\t} else {\n+\t\t\temit(ctx, divu, dst, src);\n+\t\t\temit(ctx, mfhi, dst);\n+\t\t}\n+\t\tbreak;\n+\t}\n+\tclobber_reg(ctx, dst);\n+}\n+\n+/* Atomic read-modify-write (32-bit) */\n+void emit_atomic_r(struct jit_context *ctx, u8 dst, u8 src, s16 off, u8 code)\n+{\n+\temit(ctx, ll, MIPS_R_T9, off, dst);\n+\tswitch (code) {\n+\tcase BPF_ADD:\n+\t\temit(ctx, addu, MIPS_R_T8, MIPS_R_T9, src);\n+\t\tbreak;\n+\tcase BPF_AND:\n+\t\temit(ctx, and, MIPS_R_T8, MIPS_R_T9, src);\n+\t\tbreak;\n+\tcase BPF_OR:\n+\t\temit(ctx, or, MIPS_R_T8, MIPS_R_T9, src);\n+\t\tbreak;\n+\tcase BPF_XOR:\n+\t\temit(ctx, xor, MIPS_R_T8, MIPS_R_T9, src);\n+\t\tbreak;\n+\t}\n+\temit(ctx, sc, MIPS_R_T8, off, dst);\n+\temit(ctx, beqz, MIPS_R_T8, -16);\n+\temit(ctx, nop); /* Delay slot */\n+}\n+\n+/* Atomic compare-and-exchange (32-bit) */\n+void emit_cmpxchg_r(struct jit_context *ctx, u8 dst, u8 src, u8 res, s16 off)\n+{\n+\temit(ctx, ll, MIPS_R_T9, off, dst);\n+\temit(ctx, bne, MIPS_R_T9, res, 12);\n+\temit(ctx, move, MIPS_R_T8, src);     /* Delay slot */\n+\temit(ctx, sc, MIPS_R_T8, off, dst);\n+\temit(ctx, beqz, MIPS_R_T8, -20);\n+\temit(ctx, move, res, MIPS_R_T9);     /* Delay slot */\n+\tclobber_reg(ctx, res);\n+}\n+\n+/* Swap bytes and truncate a register word or half word */\n+void emit_bswap_r(struct jit_context *ctx, u8 dst, u32 width)\n+{\n+\tu8 tmp = MIPS_R_T8;\n+\tu8 msk = MIPS_R_T9;\n+\n+\tswitch (width) {\n+\t/* Swap bytes in a word */\n+\tcase 32:\n+\t\tif (cpu_has_mips32r2 || cpu_has_mips32r6) {\n+\t\t\temit(ctx, wsbh, dst, dst);\n+\t\t\temit(ctx, rotr, dst, dst, 16);\n+\t\t} else {\n+\t\t\temit(ctx, sll, tmp, dst, 16);    /* tmp  = dst << 16 */\n+\t\t\temit(ctx, srl, dst, dst, 16);    /* dst = dst >> 16  */\n+\t\t\temit(ctx, or, dst, dst, tmp);    /* dst = dst | tmp  */\n+\n+\t\t\temit(ctx, lui, msk, 0xff);       /* msk = 0x00ff0000 */\n+\t\t\temit(ctx, ori, msk, msk, 0xff);  /* msk = msk | 0xff */\n+\n+\t\t\temit(ctx, and, tmp, dst, msk);   /* tmp = dst & msk  */\n+\t\t\temit(ctx, sll, tmp, tmp, 8);     /* tmp = tmp << 8   */\n+\t\t\temit(ctx, srl, dst, dst, 8);     /* dst = dst >> 8   */\n+\t\t\temit(ctx, and, dst, dst, msk);   /* dst = dst & msk  */\n+\t\t\temit(ctx, or, dst, dst, tmp);    /* reg = dst | tmp  */\n+\t\t}\n+\t\tbreak;\n+\t/* Swap bytes in a half word */\n+\tcase 16:\n+\t\tif (cpu_has_mips32r2 || cpu_has_mips32r6) {\n+\t\t\temit(ctx, wsbh, dst, dst);\n+\t\t\temit(ctx, andi, dst, dst, 0xffff);\n+\t\t} else {\n+\t\t\temit(ctx, andi, tmp, dst, 0xff00); /* t = d & 0xff00 */\n+\t\t\temit(ctx, srl, tmp, tmp, 8);       /* t = t >> 8     */\n+\t\t\temit(ctx, andi, dst, dst, 0x00ff); /* d = d & 0x00ff */\n+\t\t\temit(ctx, sll, dst, dst, 8);       /* d = d << 8     */\n+\t\t\temit(ctx, or,  dst, dst, tmp);     /* d = d | t      */\n+\t\t}\n+\t\tbreak;\n+\t}\n+\tclobber_reg(ctx, dst);\n+}\n+\n+/* Validate jump immediate range */\n+bool valid_jmp_i(u8 op, s32 imm)\n+{\n+\tswitch (op) {\n+\tcase JIT_JNOP:\n+\t\t/* Immediate value not used */\n+\t\treturn true;\n+\tcase BPF_JEQ:\n+\tcase BPF_JNE:\n+\t\t/* No immediate operation */\n+\t\treturn false;\n+\tcase BPF_JSET:\n+\tcase JIT_JNSET:\n+\t\t/* imm must be 16 bits unsigned */\n+\t\treturn imm >= 0 && imm <= 0xffff;\n+\tcase BPF_JGE:\n+\tcase BPF_JLT:\n+\tcase BPF_JSGE:\n+\tcase BPF_JSLT:\n+\t\t/* imm must be 16 bits */\n+\t\treturn imm >= -0x8000 && imm <= 0x7fff;\n+\tcase BPF_JGT:\n+\tcase BPF_JLE:\n+\tcase BPF_JSGT:\n+\tcase BPF_JSLE:\n+\t\t/* imm + 1 must be 16 bits */\n+\t\treturn imm >= -0x8001 && imm <= 0x7ffe;\n+\t}\n+\treturn false;\n+}\n+\n+/* Invert a conditional jump operation */\n+static u8 invert_jmp(u8 op)\n+{\n+\tswitch (op) {\n+\tcase BPF_JA: return JIT_JNOP;\n+\tcase BPF_JEQ: return BPF_JNE;\n+\tcase BPF_JNE: return BPF_JEQ;\n+\tcase BPF_JSET: return JIT_JNSET;\n+\tcase BPF_JGT: return BPF_JLE;\n+\tcase BPF_JGE: return BPF_JLT;\n+\tcase BPF_JLT: return BPF_JGE;\n+\tcase BPF_JLE: return BPF_JGT;\n+\tcase BPF_JSGT: return BPF_JSLE;\n+\tcase BPF_JSGE: return BPF_JSLT;\n+\tcase BPF_JSLT: return BPF_JSGE;\n+\tcase BPF_JSLE: return BPF_JSGT;\n+\t}\n+\treturn 0;\n+}\n+\n+/* Prepare a PC-relative jump operation */\n+static void setup_jmp(struct jit_context *ctx, u8 bpf_op,\n+\t\t      s16 bpf_off, u8 *jit_op, s32 *jit_off)\n+{\n+\tu32 *descp = &ctx->descriptors[ctx->bpf_index];\n+\tint op = bpf_op;\n+\tint offset = 0;\n+\n+\t/* Do not compute offsets on the first pass */\n+\tif (INDEX(*descp) == 0)\n+\t\tgoto done;\n+\n+\t/* Skip jumps never taken */\n+\tif (bpf_op == JIT_JNOP)\n+\t\tgoto done;\n+\n+\t/* Convert jumps always taken */\n+\tif (bpf_op == BPF_JA)\n+\t\t*descp |= JIT_DESC_CONVERT;\n+\n+\t/*\n+\t * Current ctx->jit_index points to the start of the branch preamble.\n+\t * Since the preamble differs among different branch conditionals,\n+\t * the current index cannot be used to compute the branch offset.\n+\t * Instead, we use the offset table value for the next instruction,\n+\t * which gives the index immediately after the branch delay slot.\n+\t */\n+\tif (!CONVERTED(*descp)) {\n+\t\tint target = ctx->bpf_index + bpf_off + 1;\n+\t\tint origin = ctx->bpf_index + 1;\n+\n+\t\toffset = (INDEX(ctx->descriptors[target]) -\n+\t\t\t  INDEX(ctx->descriptors[origin]) + 1) * sizeof(u32);\n+\t}\n+\n+\t/*\n+\t * The PC-relative branch offset field on MIPS is 18 bits signed,\n+\t * so if the computed offset is larger than this we generate a an\n+\t * absolute jump that we skip with an inverted conditional branch.\n+\t */\n+\tif (CONVERTED(*descp) || offset < -0x20000 || offset > 0x1ffff) {\n+\t\toffset = 3 * sizeof(u32);\n+\t\top = invert_jmp(bpf_op);\n+\t\tctx->changes += !CONVERTED(*descp);\n+\t\t*descp |= JIT_DESC_CONVERT;\n+\t}\n+\n+done:\n+\t*jit_off = offset;\n+\t*jit_op = op;\n+}\n+\n+/* Prepare a PC-relative jump operation with immediate conditional */\n+void setup_jmp_i(struct jit_context *ctx, s32 imm, u8 width,\n+\t\t u8 bpf_op, s16 bpf_off, u8 *jit_op, s32 *jit_off)\n+{\n+\tbool always = false;\n+\tbool never = false;\n+\n+\tswitch (bpf_op) {\n+\tcase BPF_JEQ:\n+\tcase BPF_JNE:\n+\t\tbreak;\n+\tcase BPF_JSET:\n+\tcase BPF_JLT:\n+\t\tnever = imm == 0;\n+\t\tbreak;\n+\tcase BPF_JGE:\n+\t\talways = imm == 0;\n+\t\tbreak;\n+\tcase BPF_JGT:\n+\t\tnever = (u32)imm == U32_MAX;\n+\t\tbreak;\n+\tcase BPF_JLE:\n+\t\talways = (u32)imm == U32_MAX;\n+\t\tbreak;\n+\tcase BPF_JSGT:\n+\t\tnever = imm == S32_MAX && width == 32;\n+\t\tbreak;\n+\tcase BPF_JSGE:\n+\t\talways = imm == S32_MIN && width == 32;\n+\t\tbreak;\n+\tcase BPF_JSLT:\n+\t\tnever = imm == S32_MIN && width == 32;\n+\t\tbreak;\n+\tcase BPF_JSLE:\n+\t\talways = imm == S32_MAX && width == 32;\n+\t\tbreak;\n+\t}\n+\n+\tif (never)\n+\t\tbpf_op = JIT_JNOP;\n+\tif (always)\n+\t\tbpf_op = BPF_JA;\n+\tsetup_jmp(ctx, bpf_op, bpf_off, jit_op, jit_off);\n+}\n+\n+/* Prepare a PC-relative jump operation with register conditional */\n+void setup_jmp_r(struct jit_context *ctx, bool same_reg,\n+\t\t u8 bpf_op, s16 bpf_off, u8 *jit_op, s32 *jit_off)\n+{\n+\tswitch (bpf_op) {\n+\tcase BPF_JSET:\n+\t\tbreak;\n+\tcase BPF_JEQ:\n+\tcase BPF_JGE:\n+\tcase BPF_JLE:\n+\tcase BPF_JSGE:\n+\tcase BPF_JSLE:\n+\t\tif (same_reg)\n+\t\t\tbpf_op = BPF_JA;\n+\t\tbreak;\n+\tcase BPF_JNE:\n+\tcase BPF_JLT:\n+\tcase BPF_JGT:\n+\tcase BPF_JSGT:\n+\tcase BPF_JSLT:\n+\t\tif (same_reg)\n+\t\t\tbpf_op = JIT_JNOP;\n+\t\tbreak;\n+\t}\n+\tsetup_jmp(ctx, bpf_op, bpf_off, jit_op, jit_off);\n+}\n+\n+/* Finish a PC-relative jump operation */\n+int finish_jmp(struct jit_context *ctx, u8 jit_op, s16 bpf_off)\n+{\n+\t/* Emit conditional branch delay slot */\n+\tif (jit_op != JIT_JNOP)\n+\t\temit(ctx, nop);\n+\t/*\n+\t * Emit an absolute long jump with delay slot,\n+\t * if the PC-relative branch was converted.\n+\t */\n+\tif (CONVERTED(ctx->descriptors[ctx->bpf_index])) {\n+\t\tint target = get_target(ctx, ctx->bpf_index + bpf_off + 1);\n+\n+\t\tif (target < 0)\n+\t\t\treturn -1;\n+\t\temit(ctx, j, target);\n+\t\temit(ctx, nop);\n+\t}\n+\treturn 0;\n+}\n+\n+/* Jump immediate (32-bit) */\n+void emit_jmp_i(struct jit_context *ctx, u8 dst, s32 imm, s32 off, u8 op)\n+{\n+\tswitch (op) {\n+\t/* No-op, used internally for branch optimization */\n+\tcase JIT_JNOP:\n+\t\tbreak;\n+\t/* PC += off if dst & imm */\n+\tcase BPF_JSET:\n+\t\temit(ctx, andi, MIPS_R_T9, dst, (u16)imm);\n+\t\temit(ctx, bnez, MIPS_R_T9, off);\n+\t\tbreak;\n+\t/* PC += off if (dst & imm) == 0 (not in BPF, used for long jumps) */\n+\tcase JIT_JNSET:\n+\t\temit(ctx, andi, MIPS_R_T9, dst, (u16)imm);\n+\t\temit(ctx, beqz, MIPS_R_T9, off);\n+\t\tbreak;\n+\t/* PC += off if dst > imm */\n+\tcase BPF_JGT:\n+\t\temit(ctx, sltiu, MIPS_R_T9, dst, imm + 1);\n+\t\temit(ctx, beqz, MIPS_R_T9, off);\n+\t\tbreak;\n+\t/* PC += off if dst >= imm */\n+\tcase BPF_JGE:\n+\t\temit(ctx, sltiu, MIPS_R_T9, dst, imm);\n+\t\temit(ctx, beqz, MIPS_R_T9, off);\n+\t\tbreak;\n+\t/* PC += off if dst < imm */\n+\tcase BPF_JLT:\n+\t\temit(ctx, sltiu, MIPS_R_T9, dst, imm);\n+\t\temit(ctx, bnez, MIPS_R_T9, off);\n+\t\tbreak;\n+\t/* PC += off if dst <= imm */\n+\tcase BPF_JLE:\n+\t\temit(ctx, sltiu, MIPS_R_T9, dst, imm + 1);\n+\t\temit(ctx, bnez, MIPS_R_T9, off);\n+\t\tbreak;\n+\t/* PC += off if dst > imm (signed) */\n+\tcase BPF_JSGT:\n+\t\temit(ctx, slti, MIPS_R_T9, dst, imm + 1);\n+\t\temit(ctx, beqz, MIPS_R_T9, off);\n+\t\tbreak;\n+\t/* PC += off if dst >= imm (signed) */\n+\tcase BPF_JSGE:\n+\t\temit(ctx, slti, MIPS_R_T9, dst, imm);\n+\t\temit(ctx, beqz, MIPS_R_T9, off);\n+\t\tbreak;\n+\t/* PC += off if dst < imm (signed) */\n+\tcase BPF_JSLT:\n+\t\temit(ctx, slti, MIPS_R_T9, dst, imm);\n+\t\temit(ctx, bnez, MIPS_R_T9, off);\n+\t\tbreak;\n+\t/* PC += off if dst <= imm (signed) */\n+\tcase BPF_JSLE:\n+\t\temit(ctx, slti, MIPS_R_T9, dst, imm + 1);\n+\t\temit(ctx, bnez, MIPS_R_T9, off);\n+\t\tbreak;\n+\t}\n+}\n+\n+/* Jump register (32-bit) */\n+void emit_jmp_r(struct jit_context *ctx, u8 dst, u8 src, s32 off, u8 op)\n+{\n+\tswitch (op) {\n+\t/* No-op, used internally for branch optimization */\n+\tcase JIT_JNOP:\n+\t\tbreak;\n+\t/* PC += off if dst == src */\n+\tcase BPF_JEQ:\n+\t\temit(ctx, beq, dst, src, off);\n+\t\tbreak;\n+\t/* PC += off if dst != src */\n+\tcase BPF_JNE:\n+\t\temit(ctx, bne, dst, src, off);\n+\t\tbreak;\n+\t/* PC += off if dst & src */\n+\tcase BPF_JSET:\n+\t\temit(ctx, and, MIPS_R_T9, dst, src);\n+\t\temit(ctx, bnez, MIPS_R_T9, off);\n+\t\tbreak;\n+\t/* PC += off if (dst & imm) == 0 (not in BPF, used for long jumps) */\n+\tcase JIT_JNSET:\n+\t\temit(ctx, and, MIPS_R_T9, dst, src);\n+\t\temit(ctx, beqz, MIPS_R_T9, off);\n+\t\tbreak;\n+\t/* PC += off if dst > src */\n+\tcase BPF_JGT:\n+\t\temit(ctx, sltu, MIPS_R_T9, src, dst);\n+\t\temit(ctx, bnez, MIPS_R_T9, off);\n+\t\tbreak;\n+\t/* PC += off if dst >= src */\n+\tcase BPF_JGE:\n+\t\temit(ctx, sltu, MIPS_R_T9, dst, src);\n+\t\temit(ctx, beqz, MIPS_R_T9, off);\n+\t\tbreak;\n+\t/* PC += off if dst < src */\n+\tcase BPF_JLT:\n+\t\temit(ctx, sltu, MIPS_R_T9, dst, src);\n+\t\temit(ctx, bnez, MIPS_R_T9, off);\n+\t\tbreak;\n+\t/* PC += off if dst <= src */\n+\tcase BPF_JLE:\n+\t\temit(ctx, sltu, MIPS_R_T9, src, dst);\n+\t\temit(ctx, beqz, MIPS_R_T9, off);\n+\t\tbreak;\n+\t/* PC += off if dst > src (signed) */\n+\tcase BPF_JSGT:\n+\t\temit(ctx, slt, MIPS_R_T9, src, dst);\n+\t\temit(ctx, bnez, MIPS_R_T9, off);\n+\t\tbreak;\n+\t/* PC += off if dst >= src (signed) */\n+\tcase BPF_JSGE:\n+\t\temit(ctx, slt, MIPS_R_T9, dst, src);\n+\t\temit(ctx, beqz, MIPS_R_T9, off);\n+\t\tbreak;\n+\t/* PC += off if dst < src (signed) */\n+\tcase BPF_JSLT:\n+\t\temit(ctx, slt, MIPS_R_T9, dst, src);\n+\t\temit(ctx, bnez, MIPS_R_T9, off);\n+\t\tbreak;\n+\t/* PC += off if dst <= src (signed) */\n+\tcase BPF_JSLE:\n+\t\temit(ctx, slt, MIPS_R_T9, src, dst);\n+\t\temit(ctx, beqz, MIPS_R_T9, off);\n+\t\tbreak;\n+\t}\n+}\n+\n+/* Jump always */\n+int emit_ja(struct jit_context *ctx, s16 off)\n+{\n+\tint target = get_target(ctx, ctx->bpf_index + off + 1);\n+\n+\tif (target < 0)\n+\t\treturn -1;\n+\temit(ctx, j, target);\n+\temit(ctx, nop);\n+\treturn 0;\n+}\n+\n+/* Jump to epilogue */\n+int emit_exit(struct jit_context *ctx)\n+{\n+\tint target = get_target(ctx, ctx->program->len);\n+\n+\tif (target < 0)\n+\t\treturn -1;\n+\temit(ctx, j, target);\n+\temit(ctx, nop);\n+\treturn 0;\n+}\n+\n+/* Build the program body from eBPF bytecode */\n+static int build_body(struct jit_context *ctx)\n+{\n+\tconst struct bpf_prog *prog = ctx->program;\n+\tunsigned int i;\n+\n+\tctx->stack_used = 0;\n+\tfor (i = 0; i < prog->len; i++) {\n+\t\tconst struct bpf_insn *insn = &prog->insnsi[i];\n+\t\tu32 *descp = &ctx->descriptors[i];\n+\t\tint ret;\n+\n+\t\taccess_reg(ctx, insn->src_reg);\n+\t\taccess_reg(ctx, insn->dst_reg);\n+\n+\t\tctx->bpf_index = i;\n+\t\tif (ctx->target == NULL) {\n+\t\t\tctx->changes += INDEX(*descp) != ctx->jit_index;\n+\t\t\t*descp &= JIT_DESC_CONVERT;\n+\t\t\t*descp |= ctx->jit_index;\n+\t\t}\n+\n+\t\tret = build_insn(insn, ctx);\n+\t\tif (ret < 0)\n+\t\t\treturn ret;\n+\n+\t\tif (ret > 0) {\n+\t\t\ti++;\n+\t\t\tif (ctx->target == NULL)\n+\t\t\t\tdescp[1] = ctx->jit_index;\n+\t\t}\n+\t}\n+\n+\t/* Store the end offset, where the epilogue begins */\n+\tctx->descriptors[prog->len] = ctx->jit_index;\n+\treturn 0;\n+}\n+\n+/* Set the branch conversion flag on all instructions */\n+static void set_convert_flag(struct jit_context *ctx, bool enable)\n+{\n+\tconst struct bpf_prog *prog = ctx->program;\n+\tu32 flag = enable ? JIT_DESC_CONVERT : 0;\n+\tunsigned int i;\n+\n+\tfor (i = 0; i <= prog->len; i++)\n+\t\tctx->descriptors[i] = INDEX(ctx->descriptors[i]) | flag;\n+}\n+\n+static void jit_fill_hole(void *area, unsigned int size)\n+{\n+\tu32 *p;\n+\n+\t/* We are guaranteed to have aligned memory. */\n+\tfor (p = area; size >= sizeof(u32); size -= sizeof(u32))\n+\t\tuasm_i_break(&p, BRK_BUG); /* Increments p */\n+}\n+\n+bool bpf_jit_needs_zext(void)\n+{\n+\treturn true;\n+}\n+\n+struct bpf_prog *bpf_int_jit_compile(struct bpf_prog *prog)\n+{\n+\tstruct bpf_prog *tmp, *orig_prog = prog;\n+\tstruct bpf_binary_header *header = NULL;\n+\tstruct jit_context ctx;\n+\tbool tmp_blinded = false;\n+\tunsigned int tmp_idx;\n+\tunsigned int image_size;\n+\tu8 *image_ptr;\n+\tint tries;\n+\n+\t/*\n+\t * If BPF JIT was not enabled then we must fall back to\n+\t * the interpreter.\n+\t */\n+\tif (!prog->jit_requested)\n+\t\treturn orig_prog;\n+\t/*\n+\t * If constant blinding was enabled and we failed during blinding\n+\t * then we must fall back to the interpreter. Otherwise, we save\n+\t * the new JITed code.\n+\t */\n+\ttmp = bpf_jit_blind_constants(prog);\n+\tif (IS_ERR(tmp))\n+\t\treturn orig_prog;\n+\tif (tmp != prog) {\n+\t\ttmp_blinded = true;\n+\t\tprog = tmp;\n+\t}\n+\n+\tmemset(&ctx, 0, sizeof(ctx));\n+\tctx.program = prog;\n+\n+\t/*\n+\t * Not able to allocate memory for descriptors[], then\n+\t * we must fall back to the interpreter\n+\t */\n+\tctx.descriptors = kcalloc(prog->len + 1, sizeof(*ctx.descriptors),\n+\t\t\t\t  GFP_KERNEL);\n+\tif (ctx.descriptors == NULL)\n+\t\tgoto out_err;\n+\n+\t/* First pass discovers used resources */\n+\tif (build_body(&ctx) < 0)\n+\t\tgoto out_err;\n+\t/*\n+\t * Second pass computes instruction offsets.\n+\t * If any PC-relative branches are out of range, a sequence of\n+\t * a PC-relative branch + a jump is generated, and we have to\n+\t * try again from the beginning to generate the new offsets.\n+\t * This is done until no additional conversions are necessary.\n+\t * The last two iterations are done with all branches being\n+\t * converted, to guarantee offset table convergence within a\n+\t * fixed number of iterations.\n+\t */\n+\tctx.jit_index = 0;\n+\tbuild_prologue(&ctx);\n+\ttmp_idx = ctx.jit_index;\n+\n+\ttries = JIT_MAX_ITERATIONS;\n+\tdo {\n+\t\tctx.jit_index = tmp_idx;\n+\t\tctx.changes = 0;\n+\t\tif (tries == 2)\n+\t\t\tset_convert_flag(&ctx, true);\n+\t\tif (build_body(&ctx) < 0)\n+\t\t\tgoto out_err;\n+\t} while (ctx.changes > 0 && --tries > 0);\n+\n+\tif (WARN_ONCE(ctx.changes > 0, \"JIT offsets failed to converge\"))\n+\t\tgoto out_err;\n+\n+\tbuild_epilogue(&ctx, MIPS_R_RA);\n+\n+\t/* Now we know the size of the structure to make */\n+\timage_size = sizeof(u32) * ctx.jit_index;\n+\theader = bpf_jit_binary_alloc(image_size, &image_ptr,\n+\t\t\t\t      sizeof(u32), jit_fill_hole);\n+\t/*\n+\t * Not able to allocate memory for the structure then\n+\t * we must fall back to the interpretation\n+\t */\n+\tif (header == NULL)\n+\t\tgoto out_err;\n+\n+\t/* Actual pass to generate final JIT code */\n+\tctx.target = (u32 *)image_ptr;\n+\tctx.jit_index = 0;\n+\n+\t/*\n+\t * If building the JITed code fails somehow,\n+\t * we fall back to the interpretation.\n+\t */\n+\tbuild_prologue(&ctx);\n+\tif (build_body(&ctx) < 0)\n+\t\tgoto out_err;\n+\tbuild_epilogue(&ctx, MIPS_R_RA);\n+\n+\t/* Populate line info meta data */\n+\tset_convert_flag(&ctx, false);\n+\tbpf_prog_fill_jited_linfo(prog, &ctx.descriptors[1]);\n+\n+\t/* Set as read-only exec and flush instruction cache */\n+\tbpf_jit_binary_lock_ro(header);\n+\tflush_icache_range((unsigned long)header,\n+\t\t\t   (unsigned long)&ctx.target[ctx.jit_index]);\n+\n+\tif (bpf_jit_enable > 1)\n+\t\tbpf_jit_dump(prog->len, image_size, 2, ctx.target);\n+\n+\tprog->bpf_func = (void *)ctx.target;\n+\tprog->jited = 1;\n+\tprog->jited_len = image_size;\n+\n+out:\n+\tif (tmp_blinded)\n+\t\tbpf_jit_prog_release_other(prog, prog == orig_prog ?\n+\t\t\t\t\t   tmp : orig_prog);\n+\tkfree(ctx.descriptors);\n+\treturn prog;\n+\n+out_err:\n+\tprog = orig_prog;\n+\tif (header)\n+\t\tbpf_jit_binary_free(header);\n+\tgoto out;\n+}\n--- /dev/null\n+++ b/arch/mips/net/bpf_jit_comp.h\n@@ -0,0 +1,211 @@\n+/* SPDX-License-Identifier: GPL-2.0-only */\n+/*\n+ * Just-In-Time compiler for eBPF bytecode on 32-bit and 64-bit MIPS.\n+ *\n+ * Copyright (c) 2021 Anyfi Networks AB.\n+ * Author: Johan Almbladh <johan.almbladh@gmail.com>\n+ *\n+ * Based on code and ideas from\n+ * Copyright (c) 2017 Cavium, Inc.\n+ * Copyright (c) 2017 Shubham Bansal <illusionist.neo@gmail.com>\n+ * Copyright (c) 2011 Mircea Gherzan <mgherzan@gmail.com>\n+ */\n+\n+#ifndef _BPF_JIT_COMP_H\n+#define _BPF_JIT_COMP_H\n+\n+/* MIPS registers */\n+#define MIPS_R_ZERO\t0   /* Const zero */\n+#define MIPS_R_AT\t1   /* Asm temp   */\n+#define MIPS_R_V0\t2   /* Result     */\n+#define MIPS_R_V1\t3   /* Result     */\n+#define MIPS_R_A0\t4   /* Argument   */\n+#define MIPS_R_A1\t5   /* Argument   */\n+#define MIPS_R_A2\t6   /* Argument   */\n+#define MIPS_R_A3\t7   /* Argument   */\n+#define MIPS_R_A4\t8   /* Arg (n64)  */\n+#define MIPS_R_A5\t9   /* Arg (n64)  */\n+#define MIPS_R_A6\t10  /* Arg (n64)  */\n+#define MIPS_R_A7\t11  /* Arg (n64)  */\n+#define MIPS_R_T0\t8   /* Temp (o32) */\n+#define MIPS_R_T1\t9   /* Temp (o32) */\n+#define MIPS_R_T2\t10  /* Temp (o32) */\n+#define MIPS_R_T3\t11  /* Temp (o32) */\n+#define MIPS_R_T4\t12  /* Temporary  */\n+#define MIPS_R_T5\t13  /* Temporary  */\n+#define MIPS_R_T6\t14  /* Temporary  */\n+#define MIPS_R_T7\t15  /* Temporary  */\n+#define MIPS_R_S0\t16  /* Saved      */\n+#define MIPS_R_S1\t17  /* Saved      */\n+#define MIPS_R_S2\t18  /* Saved      */\n+#define MIPS_R_S3\t19  /* Saved      */\n+#define MIPS_R_S4\t20  /* Saved      */\n+#define MIPS_R_S5\t21  /* Saved      */\n+#define MIPS_R_S6\t22  /* Saved      */\n+#define MIPS_R_S7\t23  /* Saved      */\n+#define MIPS_R_T8\t24  /* Temporary  */\n+#define MIPS_R_T9\t25  /* Temporary  */\n+/*      MIPS_R_K0\t26     Reserved   */\n+/*      MIPS_R_K1\t27     Reserved   */\n+#define MIPS_R_GP\t28  /* Global ptr */\n+#define MIPS_R_SP\t29  /* Stack ptr  */\n+#define MIPS_R_FP\t30  /* Frame ptr  */\n+#define MIPS_R_RA\t31  /* Return     */\n+\n+/*\n+ * Jump address mask for immediate jumps. The four most significant bits\n+ * must be equal to PC.\n+ */\n+#define MIPS_JMP_MASK\t0x0fffffffUL\n+\n+/* Maximum number of iterations in offset table computation */\n+#define JIT_MAX_ITERATIONS\t8\n+\n+/*\n+ * Jump pseudo-instructions used internally\n+ * for branch conversion and branch optimization.\n+ */\n+#define JIT_JNSET\t0xe0\n+#define JIT_JNOP\t0xf0\n+\n+/* Descriptor flag for PC-relative branch conversion */\n+#define JIT_DESC_CONVERT\tBIT(31)\n+\n+/* JIT context for an eBPF program */\n+struct jit_context {\n+\tstruct bpf_prog *program;     /* The eBPF program being JITed        */\n+\tu32 *descriptors;             /* eBPF to JITed CPU insn descriptors  */\n+\tu32 *target;                  /* JITed code buffer                   */\n+\tu32 bpf_index;                /* Index of current BPF program insn   */\n+\tu32 jit_index;                /* Index of current JIT target insn    */\n+\tu32 changes;                  /* Number of PC-relative branch conv   */\n+\tu32 accessed;                 /* Bit mask of read eBPF registers     */\n+\tu32 clobbered;                /* Bit mask of modified CPU registers  */\n+\tu32 stack_size;               /* Total allocated stack size in bytes */\n+\tu32 saved_size;               /* Size of callee-saved registers      */\n+\tu32 stack_used;               /* Stack size used for function calls  */\n+};\n+\n+/* Emit the instruction if the JIT memory space has been allocated */\n+#define emit(ctx, func, ...)\t\t\t\t\t\\\n+do {\t\t\t\t\t\t\t\t\\\n+\tif ((ctx)->target != NULL) {\t\t\t\t\\\n+\t\tu32 *p = &(ctx)->target[ctx->jit_index];\t\\\n+\t\tuasm_i_##func(&p, ##__VA_ARGS__);\t\t\\\n+\t}\t\t\t\t\t\t\t\\\n+\t(ctx)->jit_index++;\t\t\t\t\t\\\n+} while (0)\n+\n+/*\n+ * Mark a BPF register as accessed, it needs to be\n+ * initialized by the program if expected, e.g. FP.\n+ */\n+static inline void access_reg(struct jit_context *ctx, u8 reg)\n+{\n+\tctx->accessed |= BIT(reg);\n+}\n+\n+/*\n+ * Mark a CPU register as clobbered, it needs to be\n+ * saved/restored by the program if callee-saved.\n+ */\n+static inline void clobber_reg(struct jit_context *ctx, u8 reg)\n+{\n+\tctx->clobbered |= BIT(reg);\n+}\n+\n+/*\n+ * Push registers on the stack, starting at a given depth from the stack\n+ * pointer and increasing. The next depth to be written is returned.\n+ */\n+int push_regs(struct jit_context *ctx, u32 mask, u32 excl, int depth);\n+\n+/*\n+ * Pop registers from the stack, starting at a given depth from the stack\n+ * pointer and increasing. The next depth to be read is returned.\n+ */\n+int pop_regs(struct jit_context *ctx, u32 mask, u32 excl, int depth);\n+\n+/* Compute the 28-bit jump target address from a BPF program location */\n+int get_target(struct jit_context *ctx, u32 loc);\n+\n+/* Compute the PC-relative offset to relative BPF program offset */\n+int get_offset(const struct jit_context *ctx, int off);\n+\n+/* dst = imm (32-bit) */\n+void emit_mov_i(struct jit_context *ctx, u8 dst, s32 imm);\n+\n+/* dst = src (32-bit) */\n+void emit_mov_r(struct jit_context *ctx, u8 dst, u8 src);\n+\n+/* Validate ALU/ALU64 immediate range */\n+bool valid_alu_i(u8 op, s32 imm);\n+\n+/* Rewrite ALU/ALU64 immediate operation */\n+bool rewrite_alu_i(u8 op, s32 imm, u8 *alu, s32 *val);\n+\n+/* ALU immediate operation (32-bit) */\n+void emit_alu_i(struct jit_context *ctx, u8 dst, s32 imm, u8 op);\n+\n+/* ALU register operation (32-bit) */\n+void emit_alu_r(struct jit_context *ctx, u8 dst, u8 src, u8 op);\n+\n+/* Atomic read-modify-write (32-bit) */\n+void emit_atomic_r(struct jit_context *ctx, u8 dst, u8 src, s16 off, u8 code);\n+\n+/* Atomic compare-and-exchange (32-bit) */\n+void emit_cmpxchg_r(struct jit_context *ctx, u8 dst, u8 src, u8 res, s16 off);\n+\n+/* Swap bytes and truncate a register word or half word */\n+void emit_bswap_r(struct jit_context *ctx, u8 dst, u32 width);\n+\n+/* Validate JMP/JMP32 immediate range */\n+bool valid_jmp_i(u8 op, s32 imm);\n+\n+/* Prepare a PC-relative jump operation with immediate conditional */\n+void setup_jmp_i(struct jit_context *ctx, s32 imm, u8 width,\n+\t\t u8 bpf_op, s16 bpf_off, u8 *jit_op, s32 *jit_off);\n+\n+/* Prepare a PC-relative jump operation with register conditional */\n+void setup_jmp_r(struct jit_context *ctx, bool same_reg,\n+\t\t u8 bpf_op, s16 bpf_off, u8 *jit_op, s32 *jit_off);\n+\n+/* Finish a PC-relative jump operation */\n+int finish_jmp(struct jit_context *ctx, u8 jit_op, s16 bpf_off);\n+\n+/* Conditional JMP/JMP32 immediate */\n+void emit_jmp_i(struct jit_context *ctx, u8 dst, s32 imm, s32 off, u8 op);\n+\n+/* Conditional JMP/JMP32 register */\n+void emit_jmp_r(struct jit_context *ctx, u8 dst, u8 src, s32 off, u8 op);\n+\n+/* Jump always */\n+int emit_ja(struct jit_context *ctx, s16 off);\n+\n+/* Jump to epilogue */\n+int emit_exit(struct jit_context *ctx);\n+\n+/*\n+ * Build program prologue to set up the stack and registers.\n+ * This function is implemented separately for 32-bit and 64-bit JITs.\n+ */\n+void build_prologue(struct jit_context *ctx);\n+\n+/*\n+ * Build the program epilogue to restore the stack and registers.\n+ * This function is implemented separately for 32-bit and 64-bit JITs.\n+ */\n+void build_epilogue(struct jit_context *ctx, int dest_reg);\n+\n+/*\n+ * Convert an eBPF instruction to native instruction, i.e\n+ * JITs an eBPF instruction.\n+ * Returns :\n+ *\t0  - Successfully JITed an 8-byte eBPF instruction\n+ *\t>0 - Successfully JITed a 16-byte eBPF instruction\n+ *\t<0 - Failed to JIT.\n+ * This function is implemented separately for 32-bit and 64-bit JITs.\n+ */\n+int build_insn(const struct bpf_insn *insn, struct jit_context *ctx);\n+\n+#endif /* _BPF_JIT_COMP_H */\n--- /dev/null\n+++ b/arch/mips/net/bpf_jit_comp32.c\n@@ -0,0 +1,1741 @@\n+// SPDX-License-Identifier: GPL-2.0-only\n+/*\n+ * Just-In-Time compiler for eBPF bytecode on MIPS.\n+ * Implementation of JIT functions for 32-bit CPUs.\n+ *\n+ * Copyright (c) 2021 Anyfi Networks AB.\n+ * Author: Johan Almbladh <johan.almbladh@gmail.com>\n+ *\n+ * Based on code and ideas from\n+ * Copyright (c) 2017 Cavium, Inc.\n+ * Copyright (c) 2017 Shubham Bansal <illusionist.neo@gmail.com>\n+ * Copyright (c) 2011 Mircea Gherzan <mgherzan@gmail.com>\n+ */\n+\n+#include <linux/math64.h>\n+#include <linux/errno.h>\n+#include <linux/filter.h>\n+#include <linux/bpf.h>\n+#include <asm/cpu-features.h>\n+#include <asm/isa-rev.h>\n+#include <asm/uasm.h>\n+\n+#include \"bpf_jit_comp.h\"\n+\n+/* MIPS a4-a7 are not available in the o32 ABI */\n+#undef MIPS_R_A4\n+#undef MIPS_R_A5\n+#undef MIPS_R_A6\n+#undef MIPS_R_A7\n+\n+/* Stack is 8-byte aligned in o32 ABI */\n+#define MIPS_STACK_ALIGNMENT 8\n+\n+/*\n+ * The top 16 bytes of a stack frame is reserved for the callee in O32 ABI.\n+ * This corresponds to stack space for register arguments a0-a3.\n+ */\n+#define JIT_RESERVED_STACK 16\n+\n+/* Temporary 64-bit register used by JIT */\n+#define JIT_REG_TMP MAX_BPF_JIT_REG\n+\n+/*\n+ * Number of prologue bytes to skip when doing a tail call.\n+ * Tail call count (TCC) initialization (8 bytes) always, plus\n+ * R0-to-v0 assignment (4 bytes) if big endian.\n+ */\n+#ifdef __BIG_ENDIAN\n+#define JIT_TCALL_SKIP 12\n+#else\n+#define JIT_TCALL_SKIP 8\n+#endif\n+\n+/* CPU registers holding the callee return value */\n+#define JIT_RETURN_REGS\t  \\\n+\t(BIT(MIPS_R_V0) | \\\n+\t BIT(MIPS_R_V1))\n+\n+/* CPU registers arguments passed to callee directly */\n+#define JIT_ARG_REGS      \\\n+\t(BIT(MIPS_R_A0) | \\\n+\t BIT(MIPS_R_A1) | \\\n+\t BIT(MIPS_R_A2) | \\\n+\t BIT(MIPS_R_A3))\n+\n+/* CPU register arguments passed to callee on stack */\n+#define JIT_STACK_REGS    \\\n+\t(BIT(MIPS_R_T0) | \\\n+\t BIT(MIPS_R_T1) | \\\n+\t BIT(MIPS_R_T2) | \\\n+\t BIT(MIPS_R_T3) | \\\n+\t BIT(MIPS_R_T4) | \\\n+\t BIT(MIPS_R_T5))\n+\n+/* Caller-saved CPU registers */\n+#define JIT_CALLER_REGS    \\\n+\t(JIT_RETURN_REGS | \\\n+\t JIT_ARG_REGS    | \\\n+\t JIT_STACK_REGS)\n+\n+/* Callee-saved CPU registers */\n+#define JIT_CALLEE_REGS   \\\n+\t(BIT(MIPS_R_S0) | \\\n+\t BIT(MIPS_R_S1) | \\\n+\t BIT(MIPS_R_S2) | \\\n+\t BIT(MIPS_R_S3) | \\\n+\t BIT(MIPS_R_S4) | \\\n+\t BIT(MIPS_R_S5) | \\\n+\t BIT(MIPS_R_S6) | \\\n+\t BIT(MIPS_R_S7) | \\\n+\t BIT(MIPS_R_GP) | \\\n+\t BIT(MIPS_R_FP) | \\\n+\t BIT(MIPS_R_RA))\n+\n+/*\n+ * Mapping of 64-bit eBPF registers to 32-bit native MIPS registers.\n+ *\n+ * 1) Native register pairs are ordered according to CPU endiannes, following\n+ *    the MIPS convention for passing 64-bit arguments and return values.\n+ * 2) The eBPF return value, arguments and callee-saved registers are mapped\n+ *    to their native MIPS equivalents.\n+ * 3) Since the 32 highest bits in the eBPF FP register are always zero,\n+ *    only one general-purpose register is actually needed for the mapping.\n+ *    We use the fp register for this purpose, and map the highest bits to\n+ *    the MIPS register r0 (zero).\n+ * 4) We use the MIPS gp and at registers as internal temporary registers\n+ *    for constant blinding. The gp register is callee-saved.\n+ * 5) One 64-bit temporary register is mapped for use when sign-extending\n+ *    immediate operands. MIPS registers t6-t9 are available to the JIT\n+ *    for as temporaries when implementing complex 64-bit operations.\n+ *\n+ * With this scheme all eBPF registers are being mapped to native MIPS\n+ * registers without having to use any stack scratch space. The direct\n+ * register mapping (2) simplifies the handling of function calls.\n+ */\n+static const u8 bpf2mips32[][2] = {\n+\t/* Return value from in-kernel function, and exit value from eBPF */\n+\t[BPF_REG_0] = {MIPS_R_V1, MIPS_R_V0},\n+\t/* Arguments from eBPF program to in-kernel function */\n+\t[BPF_REG_1] = {MIPS_R_A1, MIPS_R_A0},\n+\t[BPF_REG_2] = {MIPS_R_A3, MIPS_R_A2},\n+\t/* Remaining arguments, to be passed on the stack per O32 ABI */\n+\t[BPF_REG_3] = {MIPS_R_T1, MIPS_R_T0},\n+\t[BPF_REG_4] = {MIPS_R_T3, MIPS_R_T2},\n+\t[BPF_REG_5] = {MIPS_R_T5, MIPS_R_T4},\n+\t/* Callee-saved registers that in-kernel function will preserve */\n+\t[BPF_REG_6] = {MIPS_R_S1, MIPS_R_S0},\n+\t[BPF_REG_7] = {MIPS_R_S3, MIPS_R_S2},\n+\t[BPF_REG_8] = {MIPS_R_S5, MIPS_R_S4},\n+\t[BPF_REG_9] = {MIPS_R_S7, MIPS_R_S6},\n+\t/* Read-only frame pointer to access the eBPF stack */\n+#ifdef __BIG_ENDIAN\n+\t[BPF_REG_FP] = {MIPS_R_FP, MIPS_R_ZERO},\n+#else\n+\t[BPF_REG_FP] = {MIPS_R_ZERO, MIPS_R_FP},\n+#endif\n+\t/* Temporary register for blinding constants */\n+\t[BPF_REG_AX] = {MIPS_R_GP, MIPS_R_AT},\n+\t/* Temporary register for internal JIT use */\n+\t[JIT_REG_TMP] = {MIPS_R_T7, MIPS_R_T6},\n+};\n+\n+/* Get low CPU register for a 64-bit eBPF register mapping */\n+static inline u8 lo(const u8 reg[])\n+{\n+#ifdef __BIG_ENDIAN\n+\treturn reg[0];\n+#else\n+\treturn reg[1];\n+#endif\n+}\n+\n+/* Get high CPU register for a 64-bit eBPF register mapping */\n+static inline u8 hi(const u8 reg[])\n+{\n+#ifdef __BIG_ENDIAN\n+\treturn reg[1];\n+#else\n+\treturn reg[0];\n+#endif\n+}\n+\n+/*\n+ * Mark a 64-bit CPU register pair as clobbered, it needs to be\n+ * saved/restored by the program if callee-saved.\n+ */\n+static void clobber_reg64(struct jit_context *ctx, const u8 reg[])\n+{\n+\tclobber_reg(ctx, reg[0]);\n+\tclobber_reg(ctx, reg[1]);\n+}\n+\n+/* dst = imm (sign-extended) */\n+static void emit_mov_se_i64(struct jit_context *ctx, const u8 dst[], s32 imm)\n+{\n+\temit_mov_i(ctx, lo(dst), imm);\n+\tif (imm < 0)\n+\t\temit(ctx, addiu, hi(dst), MIPS_R_ZERO, -1);\n+\telse\n+\t\temit(ctx, move, hi(dst), MIPS_R_ZERO);\n+\tclobber_reg64(ctx, dst);\n+}\n+\n+/* Zero extension, if verifier does not do it for us  */\n+static void emit_zext_ver(struct jit_context *ctx, const u8 dst[])\n+{\n+\tif (!ctx->program->aux->verifier_zext) {\n+\t\temit(ctx, move, hi(dst), MIPS_R_ZERO);\n+\t\tclobber_reg(ctx, hi(dst));\n+\t}\n+}\n+\n+/* Load delay slot, if ISA mandates it */\n+static void emit_load_delay(struct jit_context *ctx)\n+{\n+\tif (!cpu_has_mips_2_3_4_5_r)\n+\t\temit(ctx, nop);\n+}\n+\n+/* ALU immediate operation (64-bit) */\n+static void emit_alu_i64(struct jit_context *ctx,\n+\t\t\t const u8 dst[], s32 imm, u8 op)\n+{\n+\tu8 src = MIPS_R_T6;\n+\n+\t/*\n+\t * ADD/SUB with all but the max negative imm can be handled by\n+\t * inverting the operation and the imm value, saving one insn.\n+\t */\n+\tif (imm > S32_MIN && imm < 0)\n+\t\tswitch (op) {\n+\t\tcase BPF_ADD:\n+\t\t\top = BPF_SUB;\n+\t\t\timm = -imm;\n+\t\t\tbreak;\n+\t\tcase BPF_SUB:\n+\t\t\top = BPF_ADD;\n+\t\t\timm = -imm;\n+\t\t\tbreak;\n+\t\t}\n+\n+\t/* Move immediate to temporary register */\n+\temit_mov_i(ctx, src, imm);\n+\n+\tswitch (op) {\n+\t/* dst = dst + imm */\n+\tcase BPF_ADD:\n+\t\temit(ctx, addu, lo(dst), lo(dst), src);\n+\t\temit(ctx, sltu, MIPS_R_T9, lo(dst), src);\n+\t\temit(ctx, addu, hi(dst), hi(dst), MIPS_R_T9);\n+\t\tif (imm < 0)\n+\t\t\temit(ctx, addiu, hi(dst), hi(dst), -1);\n+\t\tbreak;\n+\t/* dst = dst - imm */\n+\tcase BPF_SUB:\n+\t\temit(ctx, sltu, MIPS_R_T9, lo(dst), src);\n+\t\temit(ctx, subu, lo(dst), lo(dst), src);\n+\t\temit(ctx, subu, hi(dst), hi(dst), MIPS_R_T9);\n+\t\tif (imm < 0)\n+\t\t\temit(ctx, addiu, hi(dst), hi(dst), 1);\n+\t\tbreak;\n+\t/* dst = dst | imm */\n+\tcase BPF_OR:\n+\t\temit(ctx, or, lo(dst), lo(dst), src);\n+\t\tif (imm < 0)\n+\t\t\temit(ctx, addiu, hi(dst), MIPS_R_ZERO, -1);\n+\t\tbreak;\n+\t/* dst = dst & imm */\n+\tcase BPF_AND:\n+\t\temit(ctx, and, lo(dst), lo(dst), src);\n+\t\tif (imm >= 0)\n+\t\t\temit(ctx, move, hi(dst), MIPS_R_ZERO);\n+\t\tbreak;\n+\t/* dst = dst ^ imm */\n+\tcase BPF_XOR:\n+\t\temit(ctx, xor, lo(dst), lo(dst), src);\n+\t\tif (imm < 0) {\n+\t\t\temit(ctx, subu, hi(dst), MIPS_R_ZERO, hi(dst));\n+\t\t\temit(ctx, addiu, hi(dst), hi(dst), -1);\n+\t\t}\n+\t\tbreak;\n+\t}\n+\tclobber_reg64(ctx, dst);\n+}\n+\n+/* ALU register operation (64-bit) */\n+static void emit_alu_r64(struct jit_context *ctx,\n+\t\t\t const u8 dst[], const u8 src[], u8 op)\n+{\n+\tswitch (BPF_OP(op)) {\n+\t/* dst = dst + src */\n+\tcase BPF_ADD:\n+\t\tif (src == dst) {\n+\t\t\temit(ctx, srl, MIPS_R_T9, lo(dst), 31);\n+\t\t\temit(ctx, addu, lo(dst), lo(dst), lo(dst));\n+\t\t} else {\n+\t\t\temit(ctx, addu, lo(dst), lo(dst), lo(src));\n+\t\t\temit(ctx, sltu, MIPS_R_T9, lo(dst), lo(src));\n+\t\t}\n+\t\temit(ctx, addu, hi(dst), hi(dst), hi(src));\n+\t\temit(ctx, addu, hi(dst), hi(dst), MIPS_R_T9);\n+\t\tbreak;\n+\t/* dst = dst - src */\n+\tcase BPF_SUB:\n+\t\temit(ctx, sltu, MIPS_R_T9, lo(dst), lo(src));\n+\t\temit(ctx, subu, lo(dst), lo(dst), lo(src));\n+\t\temit(ctx, subu, hi(dst), hi(dst), hi(src));\n+\t\temit(ctx, subu, hi(dst), hi(dst), MIPS_R_T9);\n+\t\tbreak;\n+\t/* dst = dst | src */\n+\tcase BPF_OR:\n+\t\temit(ctx, or, lo(dst), lo(dst), lo(src));\n+\t\temit(ctx, or, hi(dst), hi(dst), hi(src));\n+\t\tbreak;\n+\t/* dst = dst & src */\n+\tcase BPF_AND:\n+\t\temit(ctx, and, lo(dst), lo(dst), lo(src));\n+\t\temit(ctx, and, hi(dst), hi(dst), hi(src));\n+\t\tbreak;\n+\t/* dst = dst ^ src */\n+\tcase BPF_XOR:\n+\t\temit(ctx, xor, lo(dst), lo(dst), lo(src));\n+\t\temit(ctx, xor, hi(dst), hi(dst), hi(src));\n+\t\tbreak;\n+\t}\n+\tclobber_reg64(ctx, dst);\n+}\n+\n+/* ALU invert (64-bit) */\n+static void emit_neg_i64(struct jit_context *ctx, const u8 dst[])\n+{\n+\temit(ctx, sltu, MIPS_R_T9, MIPS_R_ZERO, lo(dst));\n+\temit(ctx, subu, lo(dst), MIPS_R_ZERO, lo(dst));\n+\temit(ctx, subu, hi(dst), MIPS_R_ZERO, hi(dst));\n+\temit(ctx, subu, hi(dst), hi(dst), MIPS_R_T9);\n+\n+\tclobber_reg64(ctx, dst);\n+}\n+\n+/* ALU shift immediate (64-bit) */\n+static void emit_shift_i64(struct jit_context *ctx,\n+\t\t\t   const u8 dst[], u32 imm, u8 op)\n+{\n+\tswitch (BPF_OP(op)) {\n+\t/* dst = dst << imm */\n+\tcase BPF_LSH:\n+\t\tif (imm < 32) {\n+\t\t\temit(ctx, srl, MIPS_R_T9, lo(dst), 32 - imm);\n+\t\t\temit(ctx, sll, lo(dst), lo(dst), imm);\n+\t\t\temit(ctx, sll, hi(dst), hi(dst), imm);\n+\t\t\temit(ctx, or, hi(dst), hi(dst), MIPS_R_T9);\n+\t\t} else {\n+\t\t\temit(ctx, sll, hi(dst), lo(dst), imm - 32);\n+\t\t\temit(ctx, move, lo(dst), MIPS_R_ZERO);\n+\t\t}\n+\t\tbreak;\n+\t/* dst = dst >> imm */\n+\tcase BPF_RSH:\n+\t\tif (imm < 32) {\n+\t\t\temit(ctx, sll, MIPS_R_T9, hi(dst), 32 - imm);\n+\t\t\temit(ctx, srl, lo(dst), lo(dst), imm);\n+\t\t\temit(ctx, srl, hi(dst), hi(dst), imm);\n+\t\t\temit(ctx, or, lo(dst), lo(dst), MIPS_R_T9);\n+\t\t} else {\n+\t\t\temit(ctx, srl, lo(dst), hi(dst), imm - 32);\n+\t\t\temit(ctx, move, hi(dst), MIPS_R_ZERO);\n+\t\t}\n+\t\tbreak;\n+\t/* dst = dst >> imm (arithmetic) */\n+\tcase BPF_ARSH:\n+\t\tif (imm < 32) {\n+\t\t\temit(ctx, sll, MIPS_R_T9, hi(dst), 32 - imm);\n+\t\t\temit(ctx, srl, lo(dst), lo(dst), imm);\n+\t\t\temit(ctx, sra, hi(dst), hi(dst), imm);\n+\t\t\temit(ctx, or, lo(dst), lo(dst), MIPS_R_T9);\n+\t\t} else {\n+\t\t\temit(ctx, sra, lo(dst), hi(dst), imm - 32);\n+\t\t\temit(ctx, sra, hi(dst), hi(dst), 31);\n+\t\t}\n+\t\tbreak;\n+\t}\n+\tclobber_reg64(ctx, dst);\n+}\n+\n+/* ALU shift register (64-bit) */\n+static void emit_shift_r64(struct jit_context *ctx,\n+\t\t\t   const u8 dst[], u8 src, u8 op)\n+{\n+\tu8 t1 = MIPS_R_T8;\n+\tu8 t2 = MIPS_R_T9;\n+\n+\temit(ctx, andi, t1, src, 32);              /* t1 = src & 32          */\n+\temit(ctx, beqz, t1, 16);                   /* PC += 16 if t1 == 0    */\n+\temit(ctx, nor, t2, src, MIPS_R_ZERO);      /* t2 = ~src (delay slot) */\n+\n+\tswitch (BPF_OP(op)) {\n+\t/* dst = dst << src */\n+\tcase BPF_LSH:\n+\t\t/* Next: shift >= 32 */\n+\t\temit(ctx, sllv, hi(dst), lo(dst), src);    /* dh = dl << src */\n+\t\temit(ctx, move, lo(dst), MIPS_R_ZERO);     /* dl = 0         */\n+\t\temit(ctx, b, 20);                          /* PC += 20       */\n+\t\t/* +16: shift < 32 */\n+\t\temit(ctx, srl, t1, lo(dst), 1);            /* t1 = dl >> 1   */\n+\t\temit(ctx, srlv, t1, t1, t2);               /* t1 = t1 >> t2  */\n+\t\temit(ctx, sllv, lo(dst), lo(dst), src);    /* dl = dl << src */\n+\t\temit(ctx, sllv, hi(dst), hi(dst), src);    /* dh = dh << src */\n+\t\temit(ctx, or, hi(dst), hi(dst), t1);       /* dh = dh | t1   */\n+\t\tbreak;\n+\t/* dst = dst >> src */\n+\tcase BPF_RSH:\n+\t\t/* Next: shift >= 32 */\n+\t\temit(ctx, srlv, lo(dst), hi(dst), src);    /* dl = dh >> src */\n+\t\temit(ctx, move, hi(dst), MIPS_R_ZERO);     /* dh = 0         */\n+\t\temit(ctx, b, 20);                          /* PC += 20       */\n+\t\t/* +16: shift < 32 */\n+\t\temit(ctx, sll, t1, hi(dst), 1);            /* t1 = dl << 1   */\n+\t\temit(ctx, sllv, t1, t1, t2);               /* t1 = t1 << t2  */\n+\t\temit(ctx, srlv, lo(dst), lo(dst), src);    /* dl = dl >> src */\n+\t\temit(ctx, srlv, hi(dst), hi(dst), src);    /* dh = dh >> src */\n+\t\temit(ctx, or, lo(dst), lo(dst), t1);       /* dl = dl | t1   */\n+\t\tbreak;\n+\t/* dst = dst >> src (arithmetic) */\n+\tcase BPF_ARSH:\n+\t\t/* Next: shift >= 32 */\n+\t\temit(ctx, srav, lo(dst), hi(dst), src);   /* dl = dh >>a src */\n+\t\temit(ctx, sra, hi(dst), hi(dst), 31);     /* dh = dh >>a 31  */\n+\t\temit(ctx, b, 20);                         /* PC += 20        */\n+\t\t/* +16: shift < 32 */\n+\t\temit(ctx, sll, t1, hi(dst), 1);           /* t1 = dl << 1    */\n+\t\temit(ctx, sllv, t1, t1, t2);              /* t1 = t1 << t2   */\n+\t\temit(ctx, srlv, lo(dst), lo(dst), src);   /* dl = dl >>a src */\n+\t\temit(ctx, srav, hi(dst), hi(dst), src);   /* dh = dh >> src  */\n+\t\temit(ctx, or, lo(dst), lo(dst), t1);      /* dl = dl | t1    */\n+\t\tbreak;\n+\t}\n+\n+\t/* +20: Done */\n+\tclobber_reg64(ctx, dst);\n+}\n+\n+/* ALU mul immediate (64x32-bit) */\n+static void emit_mul_i64(struct jit_context *ctx, const u8 dst[], s32 imm)\n+{\n+\tu8 src = MIPS_R_T6;\n+\tu8 tmp = MIPS_R_T9;\n+\n+\tswitch (imm) {\n+\t/* dst = dst * 1 is a no-op */\n+\tcase 1:\n+\t\tbreak;\n+\t/* dst = dst * -1 */\n+\tcase -1:\n+\t\temit_neg_i64(ctx, dst);\n+\t\tbreak;\n+\tcase 0:\n+\t\temit_mov_r(ctx, lo(dst), MIPS_R_ZERO);\n+\t\temit_mov_r(ctx, hi(dst), MIPS_R_ZERO);\n+\t\tbreak;\n+\t/* Full 64x32 multiply */\n+\tdefault:\n+\t\t/* hi(dst) = hi(dst) * src(imm) */\n+\t\temit_mov_i(ctx, src, imm);\n+\t\tif (cpu_has_mips32r1 || cpu_has_mips32r6) {\n+\t\t\temit(ctx, mul, hi(dst), hi(dst), src);\n+\t\t} else {\n+\t\t\temit(ctx, multu, hi(dst), src);\n+\t\t\temit(ctx, mflo, hi(dst));\n+\t\t}\n+\n+\t\t/* hi(dst) = hi(dst) - lo(dst) */\n+\t\tif (imm < 0)\n+\t\t\temit(ctx, subu, hi(dst), hi(dst), lo(dst));\n+\n+\t\t/* tmp = lo(dst) * src(imm) >> 32 */\n+\t\t/* lo(dst) = lo(dst) * src(imm) */\n+\t\tif (cpu_has_mips32r6) {\n+\t\t\temit(ctx, muhu, tmp, lo(dst), src);\n+\t\t\temit(ctx, mulu, lo(dst), lo(dst), src);\n+\t\t} else {\n+\t\t\temit(ctx, multu, lo(dst), src);\n+\t\t\temit(ctx, mflo, lo(dst));\n+\t\t\temit(ctx, mfhi, tmp);\n+\t\t}\n+\n+\t\t/* hi(dst) += tmp */\n+\t\temit(ctx, addu, hi(dst), hi(dst), tmp);\n+\t\tclobber_reg64(ctx, dst);\n+\t\tbreak;\n+\t}\n+}\n+\n+/* ALU mul register (64x64-bit) */\n+static void emit_mul_r64(struct jit_context *ctx,\n+\t\t\t const u8 dst[], const u8 src[])\n+{\n+\tu8 acc = MIPS_R_T8;\n+\tu8 tmp = MIPS_R_T9;\n+\n+\t/* acc = hi(dst) * lo(src) */\n+\tif (cpu_has_mips32r1 || cpu_has_mips32r6) {\n+\t\temit(ctx, mul, acc, hi(dst), lo(src));\n+\t} else {\n+\t\temit(ctx, multu, hi(dst), lo(src));\n+\t\temit(ctx, mflo, acc);\n+\t}\n+\n+\t/* tmp = lo(dst) * hi(src) */\n+\tif (cpu_has_mips32r1 || cpu_has_mips32r6) {\n+\t\temit(ctx, mul, tmp, lo(dst), hi(src));\n+\t} else {\n+\t\temit(ctx, multu, lo(dst), hi(src));\n+\t\temit(ctx, mflo, tmp);\n+\t}\n+\n+\t/* acc += tmp */\n+\temit(ctx, addu, acc, acc, tmp);\n+\n+\t/* tmp = lo(dst) * lo(src) >> 32 */\n+\t/* lo(dst) = lo(dst) * lo(src) */\n+\tif (cpu_has_mips32r6) {\n+\t\temit(ctx, muhu, tmp, lo(dst), lo(src));\n+\t\temit(ctx, mulu, lo(dst), lo(dst), lo(src));\n+\t} else {\n+\t\temit(ctx, multu, lo(dst), lo(src));\n+\t\temit(ctx, mflo, lo(dst));\n+\t\temit(ctx, mfhi, tmp);\n+\t}\n+\n+\t/* hi(dst) = acc + tmp */\n+\temit(ctx, addu, hi(dst), acc, tmp);\n+\tclobber_reg64(ctx, dst);\n+}\n+\n+/* Helper function for 64-bit modulo */\n+static u64 jit_mod64(u64 a, u64 b)\n+{\n+\tu64 rem;\n+\n+\tdiv64_u64_rem(a, b, &rem);\n+\treturn rem;\n+}\n+\n+/* ALU div/mod register (64-bit) */\n+static void emit_divmod_r64(struct jit_context *ctx,\n+\t\t\t    const u8 dst[], const u8 src[], u8 op)\n+{\n+\tconst u8 *r0 = bpf2mips32[BPF_REG_0]; /* Mapped to v0-v1 */\n+\tconst u8 *r1 = bpf2mips32[BPF_REG_1]; /* Mapped to a0-a1 */\n+\tconst u8 *r2 = bpf2mips32[BPF_REG_2]; /* Mapped to a2-a3 */\n+\tint exclude, k;\n+\tu32 addr = 0;\n+\n+\t/* Push caller-saved registers on stack */\n+\tpush_regs(ctx, ctx->clobbered & JIT_CALLER_REGS,\n+\t\t  0, JIT_RESERVED_STACK);\n+\n+\t/* Put 64-bit arguments 1 and 2 in registers a0-a3 */\n+\tfor (k = 0; k < 2; k++) {\n+\t\temit(ctx, move, MIPS_R_T9, src[k]);\n+\t\temit(ctx, move, r1[k], dst[k]);\n+\t\temit(ctx, move, r2[k], MIPS_R_T9);\n+\t}\n+\n+\t/* Emit function call */\n+\tswitch (BPF_OP(op)) {\n+\t/* dst = dst / src */\n+\tcase BPF_DIV:\n+\t\taddr = (u32)&div64_u64;\n+\t\tbreak;\n+\t/* dst = dst % src */\n+\tcase BPF_MOD:\n+\t\taddr = (u32)&jit_mod64;\n+\t\tbreak;\n+\t}\n+\temit_mov_i(ctx, MIPS_R_T9, addr);\n+\temit(ctx, jalr, MIPS_R_RA, MIPS_R_T9);\n+\temit(ctx, nop); /* Delay slot */\n+\n+\t/* Store the 64-bit result in dst */\n+\temit(ctx, move, dst[0], r0[0]);\n+\temit(ctx, move, dst[1], r0[1]);\n+\n+\t/* Restore caller-saved registers, excluding the computed result */\n+\texclude = BIT(lo(dst)) | BIT(hi(dst));\n+\tpop_regs(ctx, ctx->clobbered & JIT_CALLER_REGS,\n+\t\t exclude, JIT_RESERVED_STACK);\n+\temit_load_delay(ctx);\n+\n+\tclobber_reg64(ctx, dst);\n+\tclobber_reg(ctx, MIPS_R_V0);\n+\tclobber_reg(ctx, MIPS_R_V1);\n+\tclobber_reg(ctx, MIPS_R_RA);\n+}\n+\n+/* Swap bytes in a register word */\n+static void emit_swap8_r(struct jit_context *ctx, u8 dst, u8 src, u8 mask)\n+{\n+\tu8 tmp = MIPS_R_T9;\n+\n+\temit(ctx, and, tmp, src, mask); /* tmp = src & 0x00ff00ff */\n+\temit(ctx, sll, tmp, tmp, 8);    /* tmp = tmp << 8         */\n+\temit(ctx, srl, dst, src, 8);    /* dst = src >> 8         */\n+\temit(ctx, and, dst, dst, mask); /* dst = dst & 0x00ff00ff */\n+\temit(ctx, or,  dst, dst, tmp);  /* dst = dst | tmp        */\n+}\n+\n+/* Swap half words in a register word */\n+static void emit_swap16_r(struct jit_context *ctx, u8 dst, u8 src)\n+{\n+\tu8 tmp = MIPS_R_T9;\n+\n+\temit(ctx, sll, tmp, src, 16);  /* tmp = src << 16 */\n+\temit(ctx, srl, dst, src, 16);  /* dst = src >> 16 */\n+\temit(ctx, or,  dst, dst, tmp); /* dst = dst | tmp */\n+}\n+\n+/* Swap bytes and truncate a register double word, word or half word */\n+static void emit_bswap_r64(struct jit_context *ctx, const u8 dst[], u32 width)\n+{\n+\tu8 tmp = MIPS_R_T8;\n+\n+\tswitch (width) {\n+\t/* Swap bytes in a double word */\n+\tcase 64:\n+\t\tif (cpu_has_mips32r2 || cpu_has_mips32r6) {\n+\t\t\temit(ctx, rotr, tmp, hi(dst), 16);\n+\t\t\temit(ctx, rotr, hi(dst), lo(dst), 16);\n+\t\t\temit(ctx, wsbh, lo(dst), tmp);\n+\t\t\temit(ctx, wsbh, hi(dst), hi(dst));\n+\t\t} else {\n+\t\t\temit_swap16_r(ctx, tmp, lo(dst));\n+\t\t\temit_swap16_r(ctx, lo(dst), hi(dst));\n+\t\t\temit(ctx, move, hi(dst), tmp);\n+\n+\t\t\temit(ctx, lui, tmp, 0xff);      /* tmp = 0x00ff0000 */\n+\t\t\temit(ctx, ori, tmp, tmp, 0xff); /* tmp = 0x00ff00ff */\n+\t\t\temit_swap8_r(ctx, lo(dst), lo(dst), tmp);\n+\t\t\temit_swap8_r(ctx, hi(dst), hi(dst), tmp);\n+\t\t}\n+\t\tbreak;\n+\t/* Swap bytes in a word */\n+\t/* Swap bytes in a half word */\n+\tcase 32:\n+\tcase 16:\n+\t\temit_bswap_r(ctx, lo(dst), width);\n+\t\temit(ctx, move, hi(dst), MIPS_R_ZERO);\n+\t\tbreak;\n+\t}\n+\tclobber_reg64(ctx, dst);\n+}\n+\n+/* Truncate a register double word, word or half word */\n+static void emit_trunc_r64(struct jit_context *ctx, const u8 dst[], u32 width)\n+{\n+\tswitch (width) {\n+\tcase 64:\n+\t\tbreak;\n+\t/* Zero-extend a word */\n+\tcase 32:\n+\t\temit(ctx, move, hi(dst), MIPS_R_ZERO);\n+\t\tclobber_reg(ctx, hi(dst));\n+\t\tbreak;\n+\t/* Zero-extend a half word */\n+\tcase 16:\n+\t\temit(ctx, move, hi(dst), MIPS_R_ZERO);\n+\t\temit(ctx, andi, lo(dst), lo(dst), 0xffff);\n+\t\tclobber_reg64(ctx, dst);\n+\t\tbreak;\n+\t}\n+}\n+\n+/* Load operation: dst = *(size*)(src + off) */\n+static void emit_ldx(struct jit_context *ctx,\n+\t\t     const u8 dst[], u8 src, s16 off, u8 size)\n+{\n+\tswitch (size) {\n+\t/* Load a byte */\n+\tcase BPF_B:\n+\t\temit(ctx, lbu, lo(dst), off, src);\n+\t\temit(ctx, move, hi(dst), MIPS_R_ZERO);\n+\t\tbreak;\n+\t/* Load a half word */\n+\tcase BPF_H:\n+\t\temit(ctx, lhu, lo(dst), off, src);\n+\t\temit(ctx, move, hi(dst), MIPS_R_ZERO);\n+\t\tbreak;\n+\t/* Load a word */\n+\tcase BPF_W:\n+\t\temit(ctx, lw, lo(dst), off, src);\n+\t\temit(ctx, move, hi(dst), MIPS_R_ZERO);\n+\t\tbreak;\n+\t/* Load a double word */\n+\tcase BPF_DW:\n+\t\tif (dst[1] == src) {\n+\t\t\temit(ctx, lw, dst[0], off + 4, src);\n+\t\t\temit(ctx, lw, dst[1], off, src);\n+\t\t} else {\n+\t\t\temit(ctx, lw, dst[1], off, src);\n+\t\t\temit(ctx, lw, dst[0], off + 4, src);\n+\t\t}\n+\t\temit_load_delay(ctx);\n+\t\tbreak;\n+\t}\n+\tclobber_reg64(ctx, dst);\n+}\n+\n+/* Store operation: *(size *)(dst + off) = src */\n+static void emit_stx(struct jit_context *ctx,\n+\t\t     const u8 dst, const u8 src[], s16 off, u8 size)\n+{\n+\tswitch (size) {\n+\t/* Store a byte */\n+\tcase BPF_B:\n+\t\temit(ctx, sb, lo(src), off, dst);\n+\t\tbreak;\n+\t/* Store a half word */\n+\tcase BPF_H:\n+\t\temit(ctx, sh, lo(src), off, dst);\n+\t\tbreak;\n+\t/* Store a word */\n+\tcase BPF_W:\n+\t\temit(ctx, sw, lo(src), off, dst);\n+\t\tbreak;\n+\t/* Store a double word */\n+\tcase BPF_DW:\n+\t\temit(ctx, sw, src[1], off, dst);\n+\t\temit(ctx, sw, src[0], off + 4, dst);\n+\t\tbreak;\n+\t}\n+}\n+\n+/* Atomic read-modify-write (32-bit, non-ll/sc fallback) */\n+static void emit_atomic_r32(struct jit_context *ctx,\n+\t\t\t    u8 dst, u8 src, s16 off, u8 code)\n+{\n+\tu32 exclude = 0;\n+\tu32 addr = 0;\n+\n+\t/* Push caller-saved registers on stack */\n+\tpush_regs(ctx, ctx->clobbered & JIT_CALLER_REGS,\n+\t\t  0, JIT_RESERVED_STACK);\n+\t/*\n+\t * Argument 1: dst+off if xchg, otherwise src, passed in register a0\n+\t * Argument 2: src if xchg, othersize dst+off, passed in register a1\n+\t */\n+\temit(ctx, move, MIPS_R_T9, dst);\n+\temit(ctx, move, MIPS_R_A0, src);\n+\temit(ctx, addiu, MIPS_R_A1, MIPS_R_T9, off);\n+\n+\t/* Emit function call */\n+\tswitch (code) {\n+\tcase BPF_ADD:\n+\t\taddr = (u32)&atomic_add;\n+\t\tbreak;\n+\tcase BPF_SUB:\n+\t\taddr = (u32)&atomic_sub;\n+\t\tbreak;\n+\tcase BPF_OR:\n+\t\taddr = (u32)&atomic_or;\n+\t\tbreak;\n+\tcase BPF_AND:\n+\t\taddr = (u32)&atomic_and;\n+\t\tbreak;\n+\tcase BPF_XOR:\n+\t\taddr = (u32)&atomic_xor;\n+\t\tbreak;\n+\t}\n+\temit_mov_i(ctx, MIPS_R_T9, addr);\n+\temit(ctx, jalr, MIPS_R_RA, MIPS_R_T9);\n+\temit(ctx, nop); /* Delay slot */\n+\n+\t/* Restore caller-saved registers, except any fetched value */\n+\tpop_regs(ctx, ctx->clobbered & JIT_CALLER_REGS,\n+\t\t exclude, JIT_RESERVED_STACK);\n+\temit_load_delay(ctx);\n+\tclobber_reg(ctx, MIPS_R_RA);\n+}\n+\n+/* Atomic read-modify-write (64-bit) */\n+static void emit_atomic_r64(struct jit_context *ctx,\n+\t\t\t    u8 dst, const u8 src[], s16 off, u8 code)\n+{\n+\tconst u8 *r1 = bpf2mips32[BPF_REG_1]; /* Mapped to a0-a1 */\n+\tu32 exclude = 0;\n+\tu32 addr = 0;\n+\n+\t/* Push caller-saved registers on stack */\n+\tpush_regs(ctx, ctx->clobbered & JIT_CALLER_REGS,\n+\t\t  0, JIT_RESERVED_STACK);\n+\t/*\n+\t * Argument 1: 64-bit src, passed in registers a0-a1\n+\t * Argument 2: 32-bit dst+off, passed in register a2\n+\t */\n+\temit(ctx, move, MIPS_R_T9, dst);\n+\temit(ctx, move, r1[0], src[0]);\n+\temit(ctx, move, r1[1], src[1]);\n+\temit(ctx, addiu, MIPS_R_A2, MIPS_R_T9, off);\n+\n+\t/* Emit function call */\n+\tswitch (code) {\n+\tcase BPF_ADD:\n+\t\taddr = (u32)&atomic64_add;\n+\t\tbreak;\n+\tcase BPF_SUB:\n+\t\taddr = (u32)&atomic64_sub;\n+\t\tbreak;\n+\tcase BPF_OR:\n+\t\taddr = (u32)&atomic64_or;\n+\t\tbreak;\n+\tcase BPF_AND:\n+\t\taddr = (u32)&atomic64_and;\n+\t\tbreak;\n+\tcase BPF_XOR:\n+\t\taddr = (u32)&atomic64_xor;\n+\t\tbreak;\n+\t}\n+\temit_mov_i(ctx, MIPS_R_T9, addr);\n+\temit(ctx, jalr, MIPS_R_RA, MIPS_R_T9);\n+\temit(ctx, nop); /* Delay slot */\n+\n+\t/* Restore caller-saved registers, except any fetched value */\n+\tpop_regs(ctx, ctx->clobbered & JIT_CALLER_REGS,\n+\t\t exclude, JIT_RESERVED_STACK);\n+\temit_load_delay(ctx);\n+\tclobber_reg(ctx, MIPS_R_RA);\n+}\n+\n+/*\n+ * Conditional movz or an emulated equivalent.\n+ * Note that the rs register may be modified.\n+ */\n+static void emit_movz_r(struct jit_context *ctx, u8 rd, u8 rs, u8 rt)\n+{\n+\tif (cpu_has_mips_2) {\n+\t\temit(ctx, movz, rd, rs, rt);           /* rd = rt ? rd : rs  */\n+\t} else if (cpu_has_mips32r6) {\n+\t\tif (rs != MIPS_R_ZERO)\n+\t\t\temit(ctx, seleqz, rs, rs, rt); /* rs = 0 if rt == 0  */\n+\t\temit(ctx, selnez, rd, rd, rt);         /* rd = 0 if rt != 0  */\n+\t\tif (rs != MIPS_R_ZERO)\n+\t\t\temit(ctx, or, rd, rd, rs);     /* rd = rd | rs       */\n+\t} else {\n+\t\temit(ctx, bnez, rt, 8);                /* PC += 8 if rd != 0 */\n+\t\temit(ctx, nop);                        /* +0: delay slot     */\n+\t\temit(ctx, or, rd, rs, MIPS_R_ZERO);    /* +4: rd = rs        */\n+\t}\n+\tclobber_reg(ctx, rd);\n+\tclobber_reg(ctx, rs);\n+}\n+\n+/*\n+ * Conditional movn or an emulated equivalent.\n+ * Note that the rs register may be modified.\n+ */\n+static void emit_movn_r(struct jit_context *ctx, u8 rd, u8 rs, u8 rt)\n+{\n+\tif (cpu_has_mips_2) {\n+\t\temit(ctx, movn, rd, rs, rt);           /* rd = rt ? rs : rd  */\n+\t} else if (cpu_has_mips32r6) {\n+\t\tif (rs != MIPS_R_ZERO)\n+\t\t\temit(ctx, selnez, rs, rs, rt); /* rs = 0 if rt == 0  */\n+\t\temit(ctx, seleqz, rd, rd, rt);         /* rd = 0 if rt != 0  */\n+\t\tif (rs != MIPS_R_ZERO)\n+\t\t\temit(ctx, or, rd, rd, rs);     /* rd = rd | rs       */\n+\t} else {\n+\t\temit(ctx, beqz, rt, 8);                /* PC += 8 if rd == 0 */\n+\t\temit(ctx, nop);                        /* +0: delay slot     */\n+\t\temit(ctx, or, rd, rs, MIPS_R_ZERO);    /* +4: rd = rs        */\n+\t}\n+\tclobber_reg(ctx, rd);\n+\tclobber_reg(ctx, rs);\n+}\n+\n+/* Emulation of 64-bit sltiu rd, rs, imm, where imm may be S32_MAX + 1 */\n+static void emit_sltiu_r64(struct jit_context *ctx, u8 rd,\n+\t\t\t   const u8 rs[], s64 imm)\n+{\n+\tu8 tmp = MIPS_R_T9;\n+\n+\tif (imm < 0) {\n+\t\temit_mov_i(ctx, rd, imm);                 /* rd = imm        */\n+\t\temit(ctx, sltu, rd, lo(rs), rd);          /* rd = rsl < rd   */\n+\t\temit(ctx, sltiu, tmp, hi(rs), -1);        /* tmp = rsh < ~0U */\n+\t\temit(ctx, or, rd, rd, tmp);               /* rd = rd | tmp   */\n+\t} else { /* imm >= 0 */\n+\t\tif (imm > 0x7fff) {\n+\t\t\temit_mov_i(ctx, rd, (s32)imm);     /* rd = imm       */\n+\t\t\temit(ctx, sltu, rd, lo(rs), rd);   /* rd = rsl < rd  */\n+\t\t} else {\n+\t\t\temit(ctx, sltiu, rd, lo(rs), imm); /* rd = rsl < imm */\n+\t\t}\n+\t\temit_movn_r(ctx, rd, MIPS_R_ZERO, hi(rs)); /* rd = 0 if rsh  */\n+\t}\n+}\n+\n+/* Emulation of 64-bit sltu rd, rs, rt */\n+static void emit_sltu_r64(struct jit_context *ctx, u8 rd,\n+\t\t\t  const u8 rs[], const u8 rt[])\n+{\n+\tu8 tmp = MIPS_R_T9;\n+\n+\temit(ctx, sltu, rd, lo(rs), lo(rt));           /* rd = rsl < rtl     */\n+\temit(ctx, subu, tmp, hi(rs), hi(rt));          /* tmp = rsh - rth    */\n+\temit_movn_r(ctx, rd, MIPS_R_ZERO, tmp);        /* rd = 0 if tmp != 0 */\n+\temit(ctx, sltu, tmp, hi(rs), hi(rt));          /* tmp = rsh < rth    */\n+\temit(ctx, or, rd, rd, tmp);                    /* rd = rd | tmp      */\n+}\n+\n+/* Emulation of 64-bit slti rd, rs, imm, where imm may be S32_MAX + 1 */\n+static void emit_slti_r64(struct jit_context *ctx, u8 rd,\n+\t\t\t  const u8 rs[], s64 imm)\n+{\n+\tu8 t1 = MIPS_R_T8;\n+\tu8 t2 = MIPS_R_T9;\n+\tu8 cmp;\n+\n+\t/*\n+\t * if ((rs < 0) ^ (imm < 0)) t1 = imm >u rsl\n+\t * else                      t1 = rsl <u imm\n+\t */\n+\temit_mov_i(ctx, rd, (s32)imm);\n+\temit(ctx, sltu, t1, lo(rs), rd);               /* t1 = rsl <u imm   */\n+\temit(ctx, sltu, t2, rd, lo(rs));               /* t2 = imm <u rsl   */\n+\temit(ctx, srl, rd, hi(rs), 31);                /* rd = rsh >> 31    */\n+\tif (imm < 0)\n+\t\temit_movz_r(ctx, t1, t2, rd);          /* t1 = rd ? t1 : t2 */\n+\telse\n+\t\temit_movn_r(ctx, t1, t2, rd);          /* t1 = rd ? t2 : t1 */\n+\t/*\n+\t * if ((imm < 0 && rsh != 0xffffffff) ||\n+\t *     (imm >= 0 && rsh != 0))\n+\t *      t1 = 0\n+\t */\n+\tif (imm < 0) {\n+\t\temit(ctx, addiu, rd, hi(rs), 1);       /* rd = rsh + 1 */\n+\t\tcmp = rd;\n+\t} else { /* imm >= 0 */\n+\t\tcmp = hi(rs);\n+\t}\n+\temit_movn_r(ctx, t1, MIPS_R_ZERO, cmp);        /* t1 = 0 if cmp != 0 */\n+\n+\t/*\n+\t * if (imm < 0) rd = rsh < -1\n+\t * else         rd = rsh != 0\n+\t * rd = rd | t1\n+\t */\n+\temit(ctx, slti, rd, hi(rs), imm < 0 ? -1 : 0); /* rd = rsh < hi(imm) */\n+\temit(ctx, or, rd, rd, t1);                     /* rd = rd | t1       */\n+}\n+\n+/* Emulation of 64-bit(slt rd, rs, rt) */\n+static void emit_slt_r64(struct jit_context *ctx, u8 rd,\n+\t\t\t const u8 rs[], const u8 rt[])\n+{\n+\tu8 t1 = MIPS_R_T7;\n+\tu8 t2 = MIPS_R_T8;\n+\tu8 t3 = MIPS_R_T9;\n+\n+\t/*\n+\t * if ((rs < 0) ^ (rt < 0)) t1 = rtl <u rsl\n+\t * else                     t1 = rsl <u rtl\n+\t * if (rsh == rth)          t1 = 0\n+\t */\n+\temit(ctx, sltu, t1, lo(rs), lo(rt));           /* t1 = rsl <u rtl   */\n+\temit(ctx, sltu, t2, lo(rt), lo(rs));           /* t2 = rtl <u rsl   */\n+\temit(ctx, xor, t3, hi(rs), hi(rt));            /* t3 = rlh ^ rth    */\n+\temit(ctx, srl, rd, t3, 31);                    /* rd = t3 >> 31     */\n+\temit_movn_r(ctx, t1, t2, rd);                  /* t1 = rd ? t2 : t1 */\n+\temit_movn_r(ctx, t1, MIPS_R_ZERO, t3);         /* t1 = 0 if t3 != 0 */\n+\n+\t/* rd = (rsh < rth) | t1 */\n+\temit(ctx, slt, rd, hi(rs), hi(rt));            /* rd = rsh <s rth   */\n+\temit(ctx, or, rd, rd, t1);                     /* rd = rd | t1      */\n+}\n+\n+/* Jump immediate (64-bit) */\n+static void emit_jmp_i64(struct jit_context *ctx,\n+\t\t\t const u8 dst[], s32 imm, s32 off, u8 op)\n+{\n+\tu8 tmp = MIPS_R_T6;\n+\n+\tswitch (op) {\n+\t/* No-op, used internally for branch optimization */\n+\tcase JIT_JNOP:\n+\t\tbreak;\n+\t/* PC += off if dst == imm */\n+\t/* PC += off if dst != imm */\n+\tcase BPF_JEQ:\n+\tcase BPF_JNE:\n+\t\tif (imm >= -0x7fff && imm <= 0x8000) {\n+\t\t\temit(ctx, addiu, tmp, lo(dst), -imm);\n+\t\t} else if ((u32)imm <= 0xffff) {\n+\t\t\temit(ctx, xori, tmp, lo(dst), imm);\n+\t\t} else {       /* Register fallback */\n+\t\t\temit_mov_i(ctx, tmp, imm);\n+\t\t\temit(ctx, xor, tmp, lo(dst), tmp);\n+\t\t}\n+\t\tif (imm < 0) { /* Compare sign extension */\n+\t\t\temit(ctx, addu, MIPS_R_T9, hi(dst), 1);\n+\t\t\temit(ctx, or, tmp, tmp, MIPS_R_T9);\n+\t\t} else {       /* Compare zero extension */\n+\t\t\temit(ctx, or, tmp, tmp, hi(dst));\n+\t\t}\n+\t\tif (op == BPF_JEQ)\n+\t\t\temit(ctx, beqz, tmp, off);\n+\t\telse   /* BPF_JNE */\n+\t\t\temit(ctx, bnez, tmp, off);\n+\t\tbreak;\n+\t/* PC += off if dst & imm */\n+\t/* PC += off if (dst & imm) == 0 (not in BPF, used for long jumps) */\n+\tcase BPF_JSET:\n+\tcase JIT_JNSET:\n+\t\tif ((u32)imm <= 0xffff) {\n+\t\t\temit(ctx, andi, tmp, lo(dst), imm);\n+\t\t} else {     /* Register fallback */\n+\t\t\temit_mov_i(ctx, tmp, imm);\n+\t\t\temit(ctx, and, tmp, lo(dst), tmp);\n+\t\t}\n+\t\tif (imm < 0) /* Sign-extension pulls in high word */\n+\t\t\temit(ctx, or, tmp, tmp, hi(dst));\n+\t\tif (op == BPF_JSET)\n+\t\t\temit(ctx, bnez, tmp, off);\n+\t\telse   /* JIT_JNSET */\n+\t\t\temit(ctx, beqz, tmp, off);\n+\t\tbreak;\n+\t/* PC += off if dst > imm */\n+\tcase BPF_JGT:\n+\t\temit_sltiu_r64(ctx, tmp, dst, (s64)imm + 1);\n+\t\temit(ctx, beqz, tmp, off);\n+\t\tbreak;\n+\t/* PC += off if dst >= imm */\n+\tcase BPF_JGE:\n+\t\temit_sltiu_r64(ctx, tmp, dst, imm);\n+\t\temit(ctx, beqz, tmp, off);\n+\t\tbreak;\n+\t/* PC += off if dst < imm */\n+\tcase BPF_JLT:\n+\t\temit_sltiu_r64(ctx, tmp, dst, imm);\n+\t\temit(ctx, bnez, tmp, off);\n+\t\tbreak;\n+\t/* PC += off if dst <= imm */\n+\tcase BPF_JLE:\n+\t\temit_sltiu_r64(ctx, tmp, dst, (s64)imm + 1);\n+\t\temit(ctx, bnez, tmp, off);\n+\t\tbreak;\n+\t/* PC += off if dst > imm (signed) */\n+\tcase BPF_JSGT:\n+\t\temit_slti_r64(ctx, tmp, dst, (s64)imm + 1);\n+\t\temit(ctx, beqz, tmp, off);\n+\t\tbreak;\n+\t/* PC += off if dst >= imm (signed) */\n+\tcase BPF_JSGE:\n+\t\temit_slti_r64(ctx, tmp, dst, imm);\n+\t\temit(ctx, beqz, tmp, off);\n+\t\tbreak;\n+\t/* PC += off if dst < imm (signed) */\n+\tcase BPF_JSLT:\n+\t\temit_slti_r64(ctx, tmp, dst, imm);\n+\t\temit(ctx, bnez, tmp, off);\n+\t\tbreak;\n+\t/* PC += off if dst <= imm (signed) */\n+\tcase BPF_JSLE:\n+\t\temit_slti_r64(ctx, tmp, dst, (s64)imm + 1);\n+\t\temit(ctx, bnez, tmp, off);\n+\t\tbreak;\n+\t}\n+}\n+\n+/* Jump register (64-bit) */\n+static void emit_jmp_r64(struct jit_context *ctx,\n+\t\t\t const u8 dst[], const u8 src[], s32 off, u8 op)\n+{\n+\tu8 t1 = MIPS_R_T6;\n+\tu8 t2 = MIPS_R_T7;\n+\n+\tswitch (op) {\n+\t/* No-op, used internally for branch optimization */\n+\tcase JIT_JNOP:\n+\t\tbreak;\n+\t/* PC += off if dst == src */\n+\t/* PC += off if dst != src */\n+\tcase BPF_JEQ:\n+\tcase BPF_JNE:\n+\t\temit(ctx, subu, t1, lo(dst), lo(src));\n+\t\temit(ctx, subu, t2, hi(dst), hi(src));\n+\t\temit(ctx, or, t1, t1, t2);\n+\t\tif (op == BPF_JEQ)\n+\t\t\temit(ctx, beqz, t1, off);\n+\t\telse   /* BPF_JNE */\n+\t\t\temit(ctx, bnez, t1, off);\n+\t\tbreak;\n+\t/* PC += off if dst & src */\n+\t/* PC += off if (dst & imm) == 0 (not in BPF, used for long jumps) */\n+\tcase BPF_JSET:\n+\tcase JIT_JNSET:\n+\t\temit(ctx, and, t1, lo(dst), lo(src));\n+\t\temit(ctx, and, t2, hi(dst), hi(src));\n+\t\temit(ctx, or, t1, t1, t2);\n+\t\tif (op == BPF_JSET)\n+\t\t\temit(ctx, bnez, t1, off);\n+\t\telse   /* JIT_JNSET */\n+\t\t\temit(ctx, beqz, t1, off);\n+\t\tbreak;\n+\t/* PC += off if dst > src */\n+\tcase BPF_JGT:\n+\t\temit_sltu_r64(ctx, t1, src, dst);\n+\t\temit(ctx, bnez, t1, off);\n+\t\tbreak;\n+\t/* PC += off if dst >= src */\n+\tcase BPF_JGE:\n+\t\temit_sltu_r64(ctx, t1, dst, src);\n+\t\temit(ctx, beqz, t1, off);\n+\t\tbreak;\n+\t/* PC += off if dst < src */\n+\tcase BPF_JLT:\n+\t\temit_sltu_r64(ctx, t1, dst, src);\n+\t\temit(ctx, bnez, t1, off);\n+\t\tbreak;\n+\t/* PC += off if dst <= src */\n+\tcase BPF_JLE:\n+\t\temit_sltu_r64(ctx, t1, src, dst);\n+\t\temit(ctx, beqz, t1, off);\n+\t\tbreak;\n+\t/* PC += off if dst > src (signed) */\n+\tcase BPF_JSGT:\n+\t\temit_slt_r64(ctx, t1, src, dst);\n+\t\temit(ctx, bnez, t1, off);\n+\t\tbreak;\n+\t/* PC += off if dst >= src (signed) */\n+\tcase BPF_JSGE:\n+\t\temit_slt_r64(ctx, t1, dst, src);\n+\t\temit(ctx, beqz, t1, off);\n+\t\tbreak;\n+\t/* PC += off if dst < src (signed) */\n+\tcase BPF_JSLT:\n+\t\temit_slt_r64(ctx, t1, dst, src);\n+\t\temit(ctx, bnez, t1, off);\n+\t\tbreak;\n+\t/* PC += off if dst <= src (signed) */\n+\tcase BPF_JSLE:\n+\t\temit_slt_r64(ctx, t1, src, dst);\n+\t\temit(ctx, beqz, t1, off);\n+\t\tbreak;\n+\t}\n+}\n+\n+/* Function call */\n+static int emit_call(struct jit_context *ctx, const struct bpf_insn *insn)\n+{\n+\tbool fixed;\n+\tu64 addr;\n+\n+\t/* Decode the call address */\n+\tif (bpf_jit_get_func_addr(ctx->program, insn, false,\n+\t\t\t\t  &addr, &fixed) < 0)\n+\t\treturn -1;\n+\tif (!fixed)\n+\t\treturn -1;\n+\n+\t/* Push stack arguments */\n+\tpush_regs(ctx, JIT_STACK_REGS, 0, JIT_RESERVED_STACK);\n+\n+\t/* Emit function call */\n+\temit_mov_i(ctx, MIPS_R_T9, addr);\n+\temit(ctx, jalr, MIPS_R_RA, MIPS_R_T9);\n+\temit(ctx, nop); /* Delay slot */\n+\n+\tclobber_reg(ctx, MIPS_R_RA);\n+\tclobber_reg(ctx, MIPS_R_V0);\n+\tclobber_reg(ctx, MIPS_R_V1);\n+\treturn 0;\n+}\n+\n+/* Function tail call */\n+static int emit_tail_call(struct jit_context *ctx)\n+{\n+\tu8 ary = lo(bpf2mips32[BPF_REG_2]);\n+\tu8 ind = lo(bpf2mips32[BPF_REG_3]);\n+\tu8 t1 = MIPS_R_T8;\n+\tu8 t2 = MIPS_R_T9;\n+\tint off;\n+\n+\t/*\n+\t * Tail call:\n+\t * eBPF R1   - function argument (context ptr), passed in a0-a1\n+\t * eBPF R2   - ptr to object with array of function entry points\n+\t * eBPF R3   - array index of function to be called\n+\t * stack[sz] - remaining tail call count, initialized in prologue\n+\t */\n+\n+\t/* if (ind >= ary->map.max_entries) goto out */\n+\toff = offsetof(struct bpf_array, map.max_entries);\n+\tif (off > 0x7fff)\n+\t\treturn -1;\n+\temit(ctx, lw, t1, off, ary);             /* t1 = ary->map.max_entries*/\n+\temit_load_delay(ctx);                    /* Load delay slot          */\n+\temit(ctx, sltu, t1, ind, t1);            /* t1 = ind < t1            */\n+\temit(ctx, beqz, t1, get_offset(ctx, 1)); /* PC += off(1) if t1 == 0  */\n+\t\t\t\t\t\t /* (next insn delay slot)   */\n+\t/* if (TCC-- <= 0) goto out */\n+\temit(ctx, lw, t2, ctx->stack_size, MIPS_R_SP);  /* t2 = *(SP + size) */\n+\temit_load_delay(ctx);                     /* Load delay slot         */\n+\temit(ctx, blez, t2, get_offset(ctx, 1));  /* PC += off(1) if t2 < 0  */\n+\temit(ctx, addiu, t2, t2, -1);             /* t2-- (delay slot)       */\n+\temit(ctx, sw, t2, ctx->stack_size, MIPS_R_SP);  /* *(SP + size) = t2 */\n+\n+\t/* prog = ary->ptrs[ind] */\n+\toff = offsetof(struct bpf_array, ptrs);\n+\tif (off > 0x7fff)\n+\t\treturn -1;\n+\temit(ctx, sll, t1, ind, 2);               /* t1 = ind << 2           */\n+\temit(ctx, addu, t1, t1, ary);             /* t1 += ary               */\n+\temit(ctx, lw, t2, off, t1);               /* t2 = *(t1 + off)        */\n+\temit_load_delay(ctx);                     /* Load delay slot         */\n+\n+\t/* if (prog == 0) goto out */\n+\temit(ctx, beqz, t2, get_offset(ctx, 1));  /* PC += off(1) if t2 == 0 */\n+\temit(ctx, nop);                           /* Delay slot              */\n+\n+\t/* func = prog->bpf_func + 8 (prologue skip offset) */\n+\toff = offsetof(struct bpf_prog, bpf_func);\n+\tif (off > 0x7fff)\n+\t\treturn -1;\n+\temit(ctx, lw, t1, off, t2);                /* t1 = *(t2 + off)       */\n+\temit_load_delay(ctx);                      /* Load delay slot        */\n+\temit(ctx, addiu, t1, t1, JIT_TCALL_SKIP);  /* t1 += skip (8 or 12)   */\n+\n+\t/* goto func */\n+\tbuild_epilogue(ctx, t1);\n+\treturn 0;\n+}\n+\n+/*\n+ * Stack frame layout for a JITed program (stack grows down).\n+ *\n+ * Higher address  : Caller's stack frame       :\n+ *                 :----------------------------:\n+ *                 : 64-bit eBPF args r3-r5     :\n+ *                 :----------------------------:\n+ *                 : Reserved / tail call count :\n+ *                 +============================+  <--- MIPS sp before call\n+ *                 | Callee-saved registers,    |\n+ *                 | including RA and FP        |\n+ *                 +----------------------------+  <--- eBPF FP (MIPS zero,fp)\n+ *                 | Local eBPF variables       |\n+ *                 | allocated by program       |\n+ *                 +----------------------------+\n+ *                 | Reserved for caller-saved  |\n+ *                 | registers                  |\n+ *                 +----------------------------+\n+ *                 | Reserved for 64-bit eBPF   |\n+ *                 | args r3-r5 & args passed   |\n+ *                 | on stack in kernel calls   |\n+ * Lower address   +============================+  <--- MIPS sp\n+ */\n+\n+/* Build program prologue to set up the stack and registers */\n+void build_prologue(struct jit_context *ctx)\n+{\n+\tconst u8 *r1 = bpf2mips32[BPF_REG_1];\n+\tconst u8 *fp = bpf2mips32[BPF_REG_FP];\n+\tint stack, saved, locals, reserved;\n+\n+\t/*\n+\t * The first two instructions initialize TCC in the reserved (for us)\n+\t * 16-byte area in the parent's stack frame. On a tail call, the\n+\t * calling function jumps into the prologue after these instructions.\n+\t */\n+\temit(ctx, ori, MIPS_R_T9, MIPS_R_ZERO,\n+\t     min(MAX_TAIL_CALL_CNT + 1, 0xffff));\n+\temit(ctx, sw, MIPS_R_T9, 0, MIPS_R_SP);\n+\n+\t/*\n+\t * Register eBPF R1 contains the 32-bit context pointer argument.\n+\t * A 32-bit argument is always passed in MIPS register a0, regardless\n+\t * of CPU endianness. Initialize R1 accordingly and zero-extend.\n+\t */\n+#ifdef __BIG_ENDIAN\n+\temit(ctx, move, lo(r1), MIPS_R_A0);\n+#endif\n+\n+\t/* === Entry-point for tail calls === */\n+\n+\t/* Zero-extend the 32-bit argument */\n+\temit(ctx, move, hi(r1), MIPS_R_ZERO);\n+\n+\t/* If the eBPF frame pointer was accessed it must be saved */\n+\tif (ctx->accessed & BIT(BPF_REG_FP))\n+\t\tclobber_reg64(ctx, fp);\n+\n+\t/* Compute the stack space needed for callee-saved registers */\n+\tsaved = hweight32(ctx->clobbered & JIT_CALLEE_REGS) * sizeof(u32);\n+\tsaved = ALIGN(saved, MIPS_STACK_ALIGNMENT);\n+\n+\t/* Stack space used by eBPF program local data */\n+\tlocals = ALIGN(ctx->program->aux->stack_depth, MIPS_STACK_ALIGNMENT);\n+\n+\t/*\n+\t * If we are emitting function calls, reserve extra stack space for\n+\t * caller-saved registers and function arguments passed on the stack.\n+\t * The required space is computed automatically during resource\n+\t * usage discovery (pass 1).\n+\t */\n+\treserved = ctx->stack_used;\n+\n+\t/* Allocate the stack frame */\n+\tstack = ALIGN(saved + locals + reserved, MIPS_STACK_ALIGNMENT);\n+\temit(ctx, addiu, MIPS_R_SP, MIPS_R_SP, -stack);\n+\n+\t/* Store callee-saved registers on stack */\n+\tpush_regs(ctx, ctx->clobbered & JIT_CALLEE_REGS, 0, stack - saved);\n+\n+\t/* Initialize the eBPF frame pointer if accessed */\n+\tif (ctx->accessed & BIT(BPF_REG_FP))\n+\t\temit(ctx, addiu, lo(fp), MIPS_R_SP, stack - saved);\n+\n+\tctx->saved_size = saved;\n+\tctx->stack_size = stack;\n+}\n+\n+/* Build the program epilogue to restore the stack and registers */\n+void build_epilogue(struct jit_context *ctx, int dest_reg)\n+{\n+\t/* Restore callee-saved registers from stack */\n+\tpop_regs(ctx, ctx->clobbered & JIT_CALLEE_REGS, 0,\n+\t\t ctx->stack_size - ctx->saved_size);\n+\t/*\n+\t * A 32-bit return value is always passed in MIPS register v0,\n+\t * but on big-endian targets the low part of R0 is mapped to v1.\n+\t */\n+#ifdef __BIG_ENDIAN\n+\temit(ctx, move, MIPS_R_V0, MIPS_R_V1);\n+#endif\n+\n+\t/* Jump to the return address and adjust the stack pointer */\n+\temit(ctx, jr, dest_reg);\n+\temit(ctx, addiu, MIPS_R_SP, MIPS_R_SP, ctx->stack_size);\n+}\n+\n+/* Build one eBPF instruction */\n+int build_insn(const struct bpf_insn *insn, struct jit_context *ctx)\n+{\n+\tconst u8 *dst = bpf2mips32[insn->dst_reg];\n+\tconst u8 *src = bpf2mips32[insn->src_reg];\n+\tconst u8 *tmp = bpf2mips32[JIT_REG_TMP];\n+\tu8 code = insn->code;\n+\ts16 off = insn->off;\n+\ts32 imm = insn->imm;\n+\ts32 val, rel;\n+\tu8 alu, jmp;\n+\n+\tswitch (code) {\n+\t/* ALU operations */\n+\t/* dst = imm */\n+\tcase BPF_ALU | BPF_MOV | BPF_K:\n+\t\temit_mov_i(ctx, lo(dst), imm);\n+\t\temit_zext_ver(ctx, dst);\n+\t\tbreak;\n+\t/* dst = src */\n+\tcase BPF_ALU | BPF_MOV | BPF_X:\n+\t\tif (imm == 1) {\n+\t\t\t/* Special mov32 for zext */\n+\t\t\temit_mov_i(ctx, hi(dst), 0);\n+\t\t} else {\n+\t\t\temit_mov_r(ctx, lo(dst), lo(src));\n+\t\t\temit_zext_ver(ctx, dst);\n+\t\t}\n+\t\tbreak;\n+\t/* dst = -dst */\n+\tcase BPF_ALU | BPF_NEG:\n+\t\temit_alu_i(ctx, lo(dst), 0, BPF_NEG);\n+\t\temit_zext_ver(ctx, dst);\n+\t\tbreak;\n+\t/* dst = dst & imm */\n+\t/* dst = dst | imm */\n+\t/* dst = dst ^ imm */\n+\t/* dst = dst << imm */\n+\t/* dst = dst >> imm */\n+\t/* dst = dst >> imm (arithmetic) */\n+\t/* dst = dst + imm */\n+\t/* dst = dst - imm */\n+\t/* dst = dst * imm */\n+\t/* dst = dst / imm */\n+\t/* dst = dst % imm */\n+\tcase BPF_ALU | BPF_OR | BPF_K:\n+\tcase BPF_ALU | BPF_AND | BPF_K:\n+\tcase BPF_ALU | BPF_XOR | BPF_K:\n+\tcase BPF_ALU | BPF_LSH | BPF_K:\n+\tcase BPF_ALU | BPF_RSH | BPF_K:\n+\tcase BPF_ALU | BPF_ARSH | BPF_K:\n+\tcase BPF_ALU | BPF_ADD | BPF_K:\n+\tcase BPF_ALU | BPF_SUB | BPF_K:\n+\tcase BPF_ALU | BPF_MUL | BPF_K:\n+\tcase BPF_ALU | BPF_DIV | BPF_K:\n+\tcase BPF_ALU | BPF_MOD | BPF_K:\n+\t\tif (!valid_alu_i(BPF_OP(code), imm)) {\n+\t\t\temit_mov_i(ctx, MIPS_R_T6, imm);\n+\t\t\temit_alu_r(ctx, lo(dst), MIPS_R_T6, BPF_OP(code));\n+\t\t} else if (rewrite_alu_i(BPF_OP(code), imm, &alu, &val)) {\n+\t\t\temit_alu_i(ctx, lo(dst), val, alu);\n+\t\t}\n+\t\temit_zext_ver(ctx, dst);\n+\t\tbreak;\n+\t/* dst = dst & src */\n+\t/* dst = dst | src */\n+\t/* dst = dst ^ src */\n+\t/* dst = dst << src */\n+\t/* dst = dst >> src */\n+\t/* dst = dst >> src (arithmetic) */\n+\t/* dst = dst + src */\n+\t/* dst = dst - src */\n+\t/* dst = dst * src */\n+\t/* dst = dst / src */\n+\t/* dst = dst % src */\n+\tcase BPF_ALU | BPF_AND | BPF_X:\n+\tcase BPF_ALU | BPF_OR | BPF_X:\n+\tcase BPF_ALU | BPF_XOR | BPF_X:\n+\tcase BPF_ALU | BPF_LSH | BPF_X:\n+\tcase BPF_ALU | BPF_RSH | BPF_X:\n+\tcase BPF_ALU | BPF_ARSH | BPF_X:\n+\tcase BPF_ALU | BPF_ADD | BPF_X:\n+\tcase BPF_ALU | BPF_SUB | BPF_X:\n+\tcase BPF_ALU | BPF_MUL | BPF_X:\n+\tcase BPF_ALU | BPF_DIV | BPF_X:\n+\tcase BPF_ALU | BPF_MOD | BPF_X:\n+\t\temit_alu_r(ctx, lo(dst), lo(src), BPF_OP(code));\n+\t\temit_zext_ver(ctx, dst);\n+\t\tbreak;\n+\t/* dst = imm (64-bit) */\n+\tcase BPF_ALU64 | BPF_MOV | BPF_K:\n+\t\temit_mov_se_i64(ctx, dst, imm);\n+\t\tbreak;\n+\t/* dst = src (64-bit) */\n+\tcase BPF_ALU64 | BPF_MOV | BPF_X:\n+\t\temit_mov_r(ctx, lo(dst), lo(src));\n+\t\temit_mov_r(ctx, hi(dst), hi(src));\n+\t\tbreak;\n+\t/* dst = -dst (64-bit) */\n+\tcase BPF_ALU64 | BPF_NEG:\n+\t\temit_neg_i64(ctx, dst);\n+\t\tbreak;\n+\t/* dst = dst & imm (64-bit) */\n+\tcase BPF_ALU64 | BPF_AND | BPF_K:\n+\t\temit_alu_i64(ctx, dst, imm, BPF_OP(code));\n+\t\tbreak;\n+\t/* dst = dst | imm (64-bit) */\n+\t/* dst = dst ^ imm (64-bit) */\n+\t/* dst = dst + imm (64-bit) */\n+\t/* dst = dst - imm (64-bit) */\n+\tcase BPF_ALU64 | BPF_OR | BPF_K:\n+\tcase BPF_ALU64 | BPF_XOR | BPF_K:\n+\tcase BPF_ALU64 | BPF_ADD | BPF_K:\n+\tcase BPF_ALU64 | BPF_SUB | BPF_K:\n+\t\tif (imm)\n+\t\t\temit_alu_i64(ctx, dst, imm, BPF_OP(code));\n+\t\tbreak;\n+\t/* dst = dst << imm (64-bit) */\n+\t/* dst = dst >> imm (64-bit) */\n+\t/* dst = dst >> imm (64-bit, arithmetic) */\n+\tcase BPF_ALU64 | BPF_LSH | BPF_K:\n+\tcase BPF_ALU64 | BPF_RSH | BPF_K:\n+\tcase BPF_ALU64 | BPF_ARSH | BPF_K:\n+\t\tif (imm)\n+\t\t\temit_shift_i64(ctx, dst, imm, BPF_OP(code));\n+\t\tbreak;\n+\t/* dst = dst * imm (64-bit) */\n+\tcase BPF_ALU64 | BPF_MUL | BPF_K:\n+\t\temit_mul_i64(ctx, dst, imm);\n+\t\tbreak;\n+\t/* dst = dst / imm (64-bit) */\n+\t/* dst = dst % imm (64-bit) */\n+\tcase BPF_ALU64 | BPF_DIV | BPF_K:\n+\tcase BPF_ALU64 | BPF_MOD | BPF_K:\n+\t\t/*\n+\t\t * Sign-extend the immediate value into a temporary register,\n+\t\t * and then do the operation on this register.\n+\t\t */\n+\t\temit_mov_se_i64(ctx, tmp, imm);\n+\t\temit_divmod_r64(ctx, dst, tmp, BPF_OP(code));\n+\t\tbreak;\n+\t/* dst = dst & src (64-bit) */\n+\t/* dst = dst | src (64-bit) */\n+\t/* dst = dst ^ src (64-bit) */\n+\t/* dst = dst + src (64-bit) */\n+\t/* dst = dst - src (64-bit) */\n+\tcase BPF_ALU64 | BPF_AND | BPF_X:\n+\tcase BPF_ALU64 | BPF_OR | BPF_X:\n+\tcase BPF_ALU64 | BPF_XOR | BPF_X:\n+\tcase BPF_ALU64 | BPF_ADD | BPF_X:\n+\tcase BPF_ALU64 | BPF_SUB | BPF_X:\n+\t\temit_alu_r64(ctx, dst, src, BPF_OP(code));\n+\t\tbreak;\n+\t/* dst = dst << src (64-bit) */\n+\t/* dst = dst >> src (64-bit) */\n+\t/* dst = dst >> src (64-bit, arithmetic) */\n+\tcase BPF_ALU64 | BPF_LSH | BPF_X:\n+\tcase BPF_ALU64 | BPF_RSH | BPF_X:\n+\tcase BPF_ALU64 | BPF_ARSH | BPF_X:\n+\t\temit_shift_r64(ctx, dst, lo(src), BPF_OP(code));\n+\t\tbreak;\n+\t/* dst = dst * src (64-bit) */\n+\tcase BPF_ALU64 | BPF_MUL | BPF_X:\n+\t\temit_mul_r64(ctx, dst, src);\n+\t\tbreak;\n+\t/* dst = dst / src (64-bit) */\n+\t/* dst = dst % src (64-bit) */\n+\tcase BPF_ALU64 | BPF_DIV | BPF_X:\n+\tcase BPF_ALU64 | BPF_MOD | BPF_X:\n+\t\temit_divmod_r64(ctx, dst, src, BPF_OP(code));\n+\t\tbreak;\n+\t/* dst = htole(dst) */\n+\t/* dst = htobe(dst) */\n+\tcase BPF_ALU | BPF_END | BPF_FROM_LE:\n+\tcase BPF_ALU | BPF_END | BPF_FROM_BE:\n+\t\tif (BPF_SRC(code) ==\n+#ifdef __BIG_ENDIAN\n+\t\t    BPF_FROM_LE\n+#else\n+\t\t    BPF_FROM_BE\n+#endif\n+\t\t    )\n+\t\t\temit_bswap_r64(ctx, dst, imm);\n+\t\telse\n+\t\t\temit_trunc_r64(ctx, dst, imm);\n+\t\tbreak;\n+\t/* dst = imm64 */\n+\tcase BPF_LD | BPF_IMM | BPF_DW:\n+\t\temit_mov_i(ctx, lo(dst), imm);\n+\t\temit_mov_i(ctx, hi(dst), insn[1].imm);\n+\t\treturn 1;\n+\t/* LDX: dst = *(size *)(src + off) */\n+\tcase BPF_LDX | BPF_MEM | BPF_W:\n+\tcase BPF_LDX | BPF_MEM | BPF_H:\n+\tcase BPF_LDX | BPF_MEM | BPF_B:\n+\tcase BPF_LDX | BPF_MEM | BPF_DW:\n+\t\temit_ldx(ctx, dst, lo(src), off, BPF_SIZE(code));\n+\t\tbreak;\n+\t/* ST: *(size *)(dst + off) = imm */\n+\tcase BPF_ST | BPF_MEM | BPF_W:\n+\tcase BPF_ST | BPF_MEM | BPF_H:\n+\tcase BPF_ST | BPF_MEM | BPF_B:\n+\tcase BPF_ST | BPF_MEM | BPF_DW:\n+\t\tswitch (BPF_SIZE(code)) {\n+\t\tcase BPF_DW:\n+\t\t\t/* Sign-extend immediate value into temporary reg */\n+\t\t\temit_mov_se_i64(ctx, tmp, imm);\n+\t\t\tbreak;\n+\t\tcase BPF_W:\n+\t\tcase BPF_H:\n+\t\tcase BPF_B:\n+\t\t\temit_mov_i(ctx, lo(tmp), imm);\n+\t\t\tbreak;\n+\t\t}\n+\t\temit_stx(ctx, lo(dst), tmp, off, BPF_SIZE(code));\n+\t\tbreak;\n+\t/* STX: *(size *)(dst + off) = src */\n+\tcase BPF_STX | BPF_MEM | BPF_W:\n+\tcase BPF_STX | BPF_MEM | BPF_H:\n+\tcase BPF_STX | BPF_MEM | BPF_B:\n+\tcase BPF_STX | BPF_MEM | BPF_DW:\n+\t\temit_stx(ctx, lo(dst), src, off, BPF_SIZE(code));\n+\t\tbreak;\n+\t/* Speculation barrier */\n+\tcase BPF_ST | BPF_NOSPEC:\n+\t\tbreak;\n+\t/* Atomics */\n+\tcase BPF_STX | BPF_XADD | BPF_W:\n+\t\tswitch (imm) {\n+\t\tcase BPF_ADD:\n+\t\tcase BPF_AND:\n+\t\tcase BPF_OR:\n+\t\tcase BPF_XOR:\n+\t\t\tif (cpu_has_llsc)\n+\t\t\t\temit_atomic_r(ctx, lo(dst), lo(src), off, imm);\n+\t\t\telse /* Non-ll/sc fallback */\n+\t\t\t\temit_atomic_r32(ctx, lo(dst), lo(src),\n+\t\t\t\t\t\toff, imm);\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tgoto notyet;\n+\t\t}\n+\t\tbreak;\n+\t/* Atomics (64-bit) */\n+\tcase BPF_STX | BPF_XADD | BPF_DW:\n+\t\tswitch (imm) {\n+\t\tcase BPF_ADD:\n+\t\tcase BPF_AND:\n+\t\tcase BPF_OR:\n+\t\tcase BPF_XOR:\n+\t\t\temit_atomic_r64(ctx, lo(dst), src, off, imm);\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tgoto notyet;\n+\t\t}\n+\t\tbreak;\n+\t/* PC += off if dst == src */\n+\t/* PC += off if dst != src */\n+\t/* PC += off if dst & src */\n+\t/* PC += off if dst > src */\n+\t/* PC += off if dst >= src */\n+\t/* PC += off if dst < src */\n+\t/* PC += off if dst <= src */\n+\t/* PC += off if dst > src (signed) */\n+\t/* PC += off if dst >= src (signed) */\n+\t/* PC += off if dst < src (signed) */\n+\t/* PC += off if dst <= src (signed) */\n+\tcase BPF_JMP32 | BPF_JEQ | BPF_X:\n+\tcase BPF_JMP32 | BPF_JNE | BPF_X:\n+\tcase BPF_JMP32 | BPF_JSET | BPF_X:\n+\tcase BPF_JMP32 | BPF_JGT | BPF_X:\n+\tcase BPF_JMP32 | BPF_JGE | BPF_X:\n+\tcase BPF_JMP32 | BPF_JLT | BPF_X:\n+\tcase BPF_JMP32 | BPF_JLE | BPF_X:\n+\tcase BPF_JMP32 | BPF_JSGT | BPF_X:\n+\tcase BPF_JMP32 | BPF_JSGE | BPF_X:\n+\tcase BPF_JMP32 | BPF_JSLT | BPF_X:\n+\tcase BPF_JMP32 | BPF_JSLE | BPF_X:\n+\t\tif (off == 0)\n+\t\t\tbreak;\n+\t\tsetup_jmp_r(ctx, dst == src, BPF_OP(code), off, &jmp, &rel);\n+\t\temit_jmp_r(ctx, lo(dst), lo(src), rel, jmp);\n+\t\tif (finish_jmp(ctx, jmp, off) < 0)\n+\t\t\tgoto toofar;\n+\t\tbreak;\n+\t/* PC += off if dst == imm */\n+\t/* PC += off if dst != imm */\n+\t/* PC += off if dst & imm */\n+\t/* PC += off if dst > imm */\n+\t/* PC += off if dst >= imm */\n+\t/* PC += off if dst < imm */\n+\t/* PC += off if dst <= imm */\n+\t/* PC += off if dst > imm (signed) */\n+\t/* PC += off if dst >= imm (signed) */\n+\t/* PC += off if dst < imm (signed) */\n+\t/* PC += off if dst <= imm (signed) */\n+\tcase BPF_JMP32 | BPF_JEQ | BPF_K:\n+\tcase BPF_JMP32 | BPF_JNE | BPF_K:\n+\tcase BPF_JMP32 | BPF_JSET | BPF_K:\n+\tcase BPF_JMP32 | BPF_JGT | BPF_K:\n+\tcase BPF_JMP32 | BPF_JGE | BPF_K:\n+\tcase BPF_JMP32 | BPF_JLT | BPF_K:\n+\tcase BPF_JMP32 | BPF_JLE | BPF_K:\n+\tcase BPF_JMP32 | BPF_JSGT | BPF_K:\n+\tcase BPF_JMP32 | BPF_JSGE | BPF_K:\n+\tcase BPF_JMP32 | BPF_JSLT | BPF_K:\n+\tcase BPF_JMP32 | BPF_JSLE | BPF_K:\n+\t\tif (off == 0)\n+\t\t\tbreak;\n+\t\tsetup_jmp_i(ctx, imm, 32, BPF_OP(code), off, &jmp, &rel);\n+\t\tif (valid_jmp_i(jmp, imm)) {\n+\t\t\temit_jmp_i(ctx, lo(dst), imm, rel, jmp);\n+\t\t} else {\n+\t\t\t/* Move large immediate to register */\n+\t\t\temit_mov_i(ctx, MIPS_R_T6, imm);\n+\t\t\temit_jmp_r(ctx, lo(dst), MIPS_R_T6, rel, jmp);\n+\t\t}\n+\t\tif (finish_jmp(ctx, jmp, off) < 0)\n+\t\t\tgoto toofar;\n+\t\tbreak;\n+\t/* PC += off if dst == src */\n+\t/* PC += off if dst != src */\n+\t/* PC += off if dst & src */\n+\t/* PC += off if dst > src */\n+\t/* PC += off if dst >= src */\n+\t/* PC += off if dst < src */\n+\t/* PC += off if dst <= src */\n+\t/* PC += off if dst > src (signed) */\n+\t/* PC += off if dst >= src (signed) */\n+\t/* PC += off if dst < src (signed) */\n+\t/* PC += off if dst <= src (signed) */\n+\tcase BPF_JMP | BPF_JEQ | BPF_X:\n+\tcase BPF_JMP | BPF_JNE | BPF_X:\n+\tcase BPF_JMP | BPF_JSET | BPF_X:\n+\tcase BPF_JMP | BPF_JGT | BPF_X:\n+\tcase BPF_JMP | BPF_JGE | BPF_X:\n+\tcase BPF_JMP | BPF_JLT | BPF_X:\n+\tcase BPF_JMP | BPF_JLE | BPF_X:\n+\tcase BPF_JMP | BPF_JSGT | BPF_X:\n+\tcase BPF_JMP | BPF_JSGE | BPF_X:\n+\tcase BPF_JMP | BPF_JSLT | BPF_X:\n+\tcase BPF_JMP | BPF_JSLE | BPF_X:\n+\t\tif (off == 0)\n+\t\t\tbreak;\n+\t\tsetup_jmp_r(ctx, dst == src, BPF_OP(code), off, &jmp, &rel);\n+\t\temit_jmp_r64(ctx, dst, src, rel, jmp);\n+\t\tif (finish_jmp(ctx, jmp, off) < 0)\n+\t\t\tgoto toofar;\n+\t\tbreak;\n+\t/* PC += off if dst == imm */\n+\t/* PC += off if dst != imm */\n+\t/* PC += off if dst & imm */\n+\t/* PC += off if dst > imm */\n+\t/* PC += off if dst >= imm */\n+\t/* PC += off if dst < imm */\n+\t/* PC += off if dst <= imm */\n+\t/* PC += off if dst > imm (signed) */\n+\t/* PC += off if dst >= imm (signed) */\n+\t/* PC += off if dst < imm (signed) */\n+\t/* PC += off if dst <= imm (signed) */\n+\tcase BPF_JMP | BPF_JEQ | BPF_K:\n+\tcase BPF_JMP | BPF_JNE | BPF_K:\n+\tcase BPF_JMP | BPF_JSET | BPF_K:\n+\tcase BPF_JMP | BPF_JGT | BPF_K:\n+\tcase BPF_JMP | BPF_JGE | BPF_K:\n+\tcase BPF_JMP | BPF_JLT | BPF_K:\n+\tcase BPF_JMP | BPF_JLE | BPF_K:\n+\tcase BPF_JMP | BPF_JSGT | BPF_K:\n+\tcase BPF_JMP | BPF_JSGE | BPF_K:\n+\tcase BPF_JMP | BPF_JSLT | BPF_K:\n+\tcase BPF_JMP | BPF_JSLE | BPF_K:\n+\t\tif (off == 0)\n+\t\t\tbreak;\n+\t\tsetup_jmp_i(ctx, imm, 64, BPF_OP(code), off, &jmp, &rel);\n+\t\temit_jmp_i64(ctx, dst, imm, rel, jmp);\n+\t\tif (finish_jmp(ctx, jmp, off) < 0)\n+\t\t\tgoto toofar;\n+\t\tbreak;\n+\t/* PC += off */\n+\tcase BPF_JMP | BPF_JA:\n+\t\tif (off == 0)\n+\t\t\tbreak;\n+\t\tif (emit_ja(ctx, off) < 0)\n+\t\t\tgoto toofar;\n+\t\tbreak;\n+\t/* Tail call */\n+\tcase BPF_JMP | BPF_TAIL_CALL:\n+\t\tif (emit_tail_call(ctx) < 0)\n+\t\t\tgoto invalid;\n+\t\tbreak;\n+\t/* Function call */\n+\tcase BPF_JMP | BPF_CALL:\n+\t\tif (emit_call(ctx, insn) < 0)\n+\t\t\tgoto invalid;\n+\t\tbreak;\n+\t/* Function return */\n+\tcase BPF_JMP | BPF_EXIT:\n+\t\t/*\n+\t\t * Optimization: when last instruction is EXIT\n+\t\t * simply continue to epilogue.\n+\t\t */\n+\t\tif (ctx->bpf_index == ctx->program->len - 1)\n+\t\t\tbreak;\n+\t\tif (emit_exit(ctx) < 0)\n+\t\t\tgoto toofar;\n+\t\tbreak;\n+\n+\tdefault:\n+invalid:\n+\t\tpr_err_once(\"unknown opcode %02x\\n\", code);\n+\t\treturn -EINVAL;\n+notyet:\n+\t\tpr_info_once(\"*** NOT YET: opcode %02x ***\\n\", code);\n+\t\treturn -EFAULT;\n+toofar:\n+\t\tpr_info_once(\"*** TOO FAR: jump at %u opcode %02x ***\\n\",\n+\t\t\t     ctx->bpf_index, code);\n+\t\treturn -E2BIG;\n+\t}\n+\treturn 0;\n+}\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/050-v5.16-03-mips-bpf-Add-new-eBPF-JIT-for-64-bit-MIPS.patch",
    "content": "From: Johan Almbladh <johan.almbladh@anyfinetworks.com>\nDate: Tue, 5 Oct 2021 18:54:05 +0200\nSubject: [PATCH] mips: bpf: Add new eBPF JIT for 64-bit MIPS\n\nThis is an implementation on of an eBPF JIT for 64-bit MIPS III-V and\nMIPS64r1-r6. It uses the same framework introduced by the 32-bit JIT.\n\nSigned-off-by: Johan Almbladh <johan.almbladh@anyfinetworks.com>\n---\n create mode 100644 arch/mips/net/bpf_jit_comp64.c\n\n--- /dev/null\n+++ b/arch/mips/net/bpf_jit_comp64.c\n@@ -0,0 +1,991 @@\n+// SPDX-License-Identifier: GPL-2.0-only\n+/*\n+ * Just-In-Time compiler for eBPF bytecode on MIPS.\n+ * Implementation of JIT functions for 64-bit CPUs.\n+ *\n+ * Copyright (c) 2021 Anyfi Networks AB.\n+ * Author: Johan Almbladh <johan.almbladh@gmail.com>\n+ *\n+ * Based on code and ideas from\n+ * Copyright (c) 2017 Cavium, Inc.\n+ * Copyright (c) 2017 Shubham Bansal <illusionist.neo@gmail.com>\n+ * Copyright (c) 2011 Mircea Gherzan <mgherzan@gmail.com>\n+ */\n+\n+#include <linux/errno.h>\n+#include <linux/filter.h>\n+#include <linux/bpf.h>\n+#include <asm/cpu-features.h>\n+#include <asm/isa-rev.h>\n+#include <asm/uasm.h>\n+\n+#include \"bpf_jit_comp.h\"\n+\n+/* MIPS t0-t3 are not available in the n64 ABI */\n+#undef MIPS_R_T0\n+#undef MIPS_R_T1\n+#undef MIPS_R_T2\n+#undef MIPS_R_T3\n+\n+/* Stack is 16-byte aligned in n64 ABI */\n+#define MIPS_STACK_ALIGNMENT 16\n+\n+/* Extra 64-bit eBPF registers used by JIT */\n+#define JIT_REG_TC (MAX_BPF_JIT_REG + 0)\n+#define JIT_REG_ZX (MAX_BPF_JIT_REG + 1)\n+\n+/* Number of prologue bytes to skip when doing a tail call */\n+#define JIT_TCALL_SKIP 4\n+\n+/* Callee-saved CPU registers that the JIT must preserve */\n+#define JIT_CALLEE_REGS   \\\n+\t(BIT(MIPS_R_S0) | \\\n+\t BIT(MIPS_R_S1) | \\\n+\t BIT(MIPS_R_S2) | \\\n+\t BIT(MIPS_R_S3) | \\\n+\t BIT(MIPS_R_S4) | \\\n+\t BIT(MIPS_R_S5) | \\\n+\t BIT(MIPS_R_S6) | \\\n+\t BIT(MIPS_R_S7) | \\\n+\t BIT(MIPS_R_GP) | \\\n+\t BIT(MIPS_R_FP) | \\\n+\t BIT(MIPS_R_RA))\n+\n+/* Caller-saved CPU registers available for JIT use */\n+#define JIT_CALLER_REGS\t  \\\n+\t(BIT(MIPS_R_A5) | \\\n+\t BIT(MIPS_R_A6) | \\\n+\t BIT(MIPS_R_A7))\n+/*\n+ * Mapping of 64-bit eBPF registers to 64-bit native MIPS registers.\n+ * MIPS registers t4 - t7 may be used by the JIT as temporary registers.\n+ * MIPS registers t8 - t9 are reserved for single-register common functions.\n+ */\n+static const u8 bpf2mips64[] = {\n+\t/* Return value from in-kernel function, and exit value from eBPF */\n+\t[BPF_REG_0] = MIPS_R_V0,\n+\t/* Arguments from eBPF program to in-kernel function */\n+\t[BPF_REG_1] = MIPS_R_A0,\n+\t[BPF_REG_2] = MIPS_R_A1,\n+\t[BPF_REG_3] = MIPS_R_A2,\n+\t[BPF_REG_4] = MIPS_R_A3,\n+\t[BPF_REG_5] = MIPS_R_A4,\n+\t/* Callee-saved registers that in-kernel function will preserve */\n+\t[BPF_REG_6] = MIPS_R_S0,\n+\t[BPF_REG_7] = MIPS_R_S1,\n+\t[BPF_REG_8] = MIPS_R_S2,\n+\t[BPF_REG_9] = MIPS_R_S3,\n+\t/* Read-only frame pointer to access the eBPF stack */\n+\t[BPF_REG_FP] = MIPS_R_FP,\n+\t/* Temporary register for blinding constants */\n+\t[BPF_REG_AX] = MIPS_R_AT,\n+\t/* Tail call count register, caller-saved */\n+\t[JIT_REG_TC] = MIPS_R_A5,\n+\t/* Constant for register zero-extension */\n+\t[JIT_REG_ZX] = MIPS_R_V1,\n+};\n+\n+/*\n+ * MIPS 32-bit operations on 64-bit registers generate a sign-extended\n+ * result. However, the eBPF ISA mandates zero-extension, so we rely on the\n+ * verifier to add that for us (emit_zext_ver). In addition, ALU arithmetic\n+ * operations, right shift and byte swap require properly sign-extended\n+ * operands or the result is unpredictable. We emit explicit sign-extensions\n+ * in those cases.\n+ */\n+\n+/* Sign extension */\n+static void emit_sext(struct jit_context *ctx, u8 dst, u8 src)\n+{\n+\temit(ctx, sll, dst, src, 0);\n+\tclobber_reg(ctx, dst);\n+}\n+\n+/* Zero extension */\n+static void emit_zext(struct jit_context *ctx, u8 dst)\n+{\n+\tif (cpu_has_mips64r2 || cpu_has_mips64r6) {\n+\t\temit(ctx, dinsu, dst, MIPS_R_ZERO, 32, 32);\n+\t} else {\n+\t\temit(ctx, and, dst, dst, bpf2mips64[JIT_REG_ZX]);\n+\t\taccess_reg(ctx, JIT_REG_ZX); /* We need the ZX register */\n+\t}\n+\tclobber_reg(ctx, dst);\n+}\n+\n+/* Zero extension, if verifier does not do it for us  */\n+static void emit_zext_ver(struct jit_context *ctx, u8 dst)\n+{\n+\tif (!ctx->program->aux->verifier_zext)\n+\t\temit_zext(ctx, dst);\n+}\n+\n+/* dst = imm (64-bit) */\n+static void emit_mov_i64(struct jit_context *ctx, u8 dst, u64 imm64)\n+{\n+\tif (imm64 >= 0xffffffffffff8000ULL || imm64 < 0x8000ULL) {\n+\t\temit(ctx, daddiu, dst, MIPS_R_ZERO, (s16)imm64);\n+\t} else if (imm64 >= 0xffffffff80000000ULL ||\n+\t\t   (imm64 < 0x80000000 && imm64 > 0xffff)) {\n+\t\temit(ctx, lui, dst, (s16)(imm64 >> 16));\n+\t\temit(ctx, ori, dst, dst, (u16)imm64 & 0xffff);\n+\t} else {\n+\t\tu8 acc = MIPS_R_ZERO;\n+\t\tint k;\n+\n+\t\tfor (k = 0; k < 4; k++) {\n+\t\t\tu16 half = imm64 >> (48 - 16 * k);\n+\n+\t\t\tif (acc == dst)\n+\t\t\t\temit(ctx, dsll, dst, dst, 16);\n+\n+\t\t\tif (half) {\n+\t\t\t\temit(ctx, ori, dst, acc, half);\n+\t\t\t\tacc = dst;\n+\t\t\t}\n+\t\t}\n+\t}\n+\tclobber_reg(ctx, dst);\n+}\n+\n+/* ALU immediate operation (64-bit) */\n+static void emit_alu_i64(struct jit_context *ctx, u8 dst, s32 imm, u8 op)\n+{\n+\tswitch (BPF_OP(op)) {\n+\t/* dst = dst | imm */\n+\tcase BPF_OR:\n+\t\temit(ctx, ori, dst, dst, (u16)imm);\n+\t\tbreak;\n+\t/* dst = dst ^ imm */\n+\tcase BPF_XOR:\n+\t\temit(ctx, xori, dst, dst, (u16)imm);\n+\t\tbreak;\n+\t/* dst = -dst */\n+\tcase BPF_NEG:\n+\t\temit(ctx, dsubu, dst, MIPS_R_ZERO, dst);\n+\t\tbreak;\n+\t/* dst = dst << imm */\n+\tcase BPF_LSH:\n+\t\temit(ctx, dsll_safe, dst, dst, imm);\n+\t\tbreak;\n+\t/* dst = dst >> imm */\n+\tcase BPF_RSH:\n+\t\temit(ctx, dsrl_safe, dst, dst, imm);\n+\t\tbreak;\n+\t/* dst = dst >> imm (arithmetic) */\n+\tcase BPF_ARSH:\n+\t\temit(ctx, dsra_safe, dst, dst, imm);\n+\t\tbreak;\n+\t/* dst = dst + imm */\n+\tcase BPF_ADD:\n+\t\temit(ctx, daddiu, dst, dst, imm);\n+\t\tbreak;\n+\t/* dst = dst - imm */\n+\tcase BPF_SUB:\n+\t\temit(ctx, daddiu, dst, dst, -imm);\n+\t\tbreak;\n+\tdefault:\n+\t\t/* Width-generic operations */\n+\t\temit_alu_i(ctx, dst, imm, op);\n+\t}\n+\tclobber_reg(ctx, dst);\n+}\n+\n+/* ALU register operation (64-bit) */\n+static void emit_alu_r64(struct jit_context *ctx, u8 dst, u8 src, u8 op)\n+{\n+\tswitch (BPF_OP(op)) {\n+\t/* dst = dst << src */\n+\tcase BPF_LSH:\n+\t\temit(ctx, dsllv, dst, dst, src);\n+\t\tbreak;\n+\t/* dst = dst >> src */\n+\tcase BPF_RSH:\n+\t\temit(ctx, dsrlv, dst, dst, src);\n+\t\tbreak;\n+\t/* dst = dst >> src (arithmetic) */\n+\tcase BPF_ARSH:\n+\t\temit(ctx, dsrav, dst, dst, src);\n+\t\tbreak;\n+\t/* dst = dst + src */\n+\tcase BPF_ADD:\n+\t\temit(ctx, daddu, dst, dst, src);\n+\t\tbreak;\n+\t/* dst = dst - src */\n+\tcase BPF_SUB:\n+\t\temit(ctx, dsubu, dst, dst, src);\n+\t\tbreak;\n+\t/* dst = dst * src */\n+\tcase BPF_MUL:\n+\t\tif (cpu_has_mips64r6) {\n+\t\t\temit(ctx, dmulu, dst, dst, src);\n+\t\t} else {\n+\t\t\temit(ctx, dmultu, dst, src);\n+\t\t\temit(ctx, mflo, dst);\n+\t\t}\n+\t\tbreak;\n+\t/* dst = dst / src */\n+\tcase BPF_DIV:\n+\t\tif (cpu_has_mips64r6) {\n+\t\t\temit(ctx, ddivu_r6, dst, dst, src);\n+\t\t} else {\n+\t\t\temit(ctx, ddivu, dst, src);\n+\t\t\temit(ctx, mflo, dst);\n+\t\t}\n+\t\tbreak;\n+\t/* dst = dst % src */\n+\tcase BPF_MOD:\n+\t\tif (cpu_has_mips64r6) {\n+\t\t\temit(ctx, dmodu, dst, dst, src);\n+\t\t} else {\n+\t\t\temit(ctx, ddivu, dst, src);\n+\t\t\temit(ctx, mfhi, dst);\n+\t\t}\n+\t\tbreak;\n+\tdefault:\n+\t\t/* Width-generic operations */\n+\t\temit_alu_r(ctx, dst, src, op);\n+\t}\n+\tclobber_reg(ctx, dst);\n+}\n+\n+/* Swap sub words in a register double word */\n+static void emit_swap_r64(struct jit_context *ctx, u8 dst, u8 mask, u32 bits)\n+{\n+\tu8 tmp = MIPS_R_T9;\n+\n+\temit(ctx, and, tmp, dst, mask);  /* tmp = dst & mask  */\n+\temit(ctx, dsll, tmp, tmp, bits); /* tmp = tmp << bits */\n+\temit(ctx, dsrl, dst, dst, bits); /* dst = dst >> bits */\n+\temit(ctx, and, dst, dst, mask);  /* dst = dst & mask  */\n+\temit(ctx, or, dst, dst, tmp);    /* dst = dst | tmp   */\n+}\n+\n+/* Swap bytes and truncate a register double word, word or half word */\n+static void emit_bswap_r64(struct jit_context *ctx, u8 dst, u32 width)\n+{\n+\tswitch (width) {\n+\t/* Swap bytes in a double word */\n+\tcase 64:\n+\t\tif (cpu_has_mips64r2 || cpu_has_mips64r6) {\n+\t\t\temit(ctx, dsbh, dst, dst);\n+\t\t\temit(ctx, dshd, dst, dst);\n+\t\t} else {\n+\t\t\tu8 t1 = MIPS_R_T6;\n+\t\t\tu8 t2 = MIPS_R_T7;\n+\n+\t\t\temit(ctx, dsll32, t2, dst, 0);  /* t2 = dst << 32    */\n+\t\t\temit(ctx, dsrl32, dst, dst, 0); /* dst = dst >> 32   */\n+\t\t\temit(ctx, or, dst, dst, t2);    /* dst = dst | t2    */\n+\n+\t\t\temit(ctx, ori, t2, MIPS_R_ZERO, 0xffff);\n+\t\t\temit(ctx, dsll32, t1, t2, 0);   /* t1 = t2 << 32     */\n+\t\t\temit(ctx, or, t1, t1, t2);      /* t1 = t1 | t2      */\n+\t\t\temit_swap_r64(ctx, dst, t1, 16);/* dst = swap16(dst) */\n+\n+\t\t\temit(ctx, lui, t2, 0xff);       /* t2 = 0x00ff0000   */\n+\t\t\temit(ctx, ori, t2, t2, 0xff);   /* t2 = t2 | 0x00ff  */\n+\t\t\temit(ctx, dsll32, t1, t2, 0);   /* t1 = t2 << 32     */\n+\t\t\temit(ctx, or, t1, t1, t2);      /* t1 = t1 | t2      */\n+\t\t\temit_swap_r64(ctx, dst, t1, 8); /* dst = swap8(dst)  */\n+\t\t}\n+\t\tbreak;\n+\t/* Swap bytes in a half word */\n+\t/* Swap bytes in a word */\n+\tcase 32:\n+\tcase 16:\n+\t\temit_sext(ctx, dst, dst);\n+\t\temit_bswap_r(ctx, dst, width);\n+\t\tif (cpu_has_mips64r2 || cpu_has_mips64r6)\n+\t\t\temit_zext(ctx, dst);\n+\t\tbreak;\n+\t}\n+\tclobber_reg(ctx, dst);\n+}\n+\n+/* Truncate a register double word, word or half word */\n+static void emit_trunc_r64(struct jit_context *ctx, u8 dst, u32 width)\n+{\n+\tswitch (width) {\n+\tcase 64:\n+\t\tbreak;\n+\t/* Zero-extend a word */\n+\tcase 32:\n+\t\temit_zext(ctx, dst);\n+\t\tbreak;\n+\t/* Zero-extend a half word */\n+\tcase 16:\n+\t\temit(ctx, andi, dst, dst, 0xffff);\n+\t\tbreak;\n+\t}\n+\tclobber_reg(ctx, dst);\n+}\n+\n+/* Load operation: dst = *(size*)(src + off) */\n+static void emit_ldx(struct jit_context *ctx, u8 dst, u8 src, s16 off, u8 size)\n+{\n+\tswitch (size) {\n+\t/* Load a byte */\n+\tcase BPF_B:\n+\t\temit(ctx, lbu, dst, off, src);\n+\t\tbreak;\n+\t/* Load a half word */\n+\tcase BPF_H:\n+\t\temit(ctx, lhu, dst, off, src);\n+\t\tbreak;\n+\t/* Load a word */\n+\tcase BPF_W:\n+\t\temit(ctx, lwu, dst, off, src);\n+\t\tbreak;\n+\t/* Load a double word */\n+\tcase BPF_DW:\n+\t\temit(ctx, ld, dst, off, src);\n+\t\tbreak;\n+\t}\n+\tclobber_reg(ctx, dst);\n+}\n+\n+/* Store operation: *(size *)(dst + off) = src */\n+static void emit_stx(struct jit_context *ctx, u8 dst, u8 src, s16 off, u8 size)\n+{\n+\tswitch (size) {\n+\t/* Store a byte */\n+\tcase BPF_B:\n+\t\temit(ctx, sb, src, off, dst);\n+\t\tbreak;\n+\t/* Store a half word */\n+\tcase BPF_H:\n+\t\temit(ctx, sh, src, off, dst);\n+\t\tbreak;\n+\t/* Store a word */\n+\tcase BPF_W:\n+\t\temit(ctx, sw, src, off, dst);\n+\t\tbreak;\n+\t/* Store a double word */\n+\tcase BPF_DW:\n+\t\temit(ctx, sd, src, off, dst);\n+\t\tbreak;\n+\t}\n+}\n+\n+/* Atomic read-modify-write */\n+static void emit_atomic_r64(struct jit_context *ctx,\n+\t\t\t    u8 dst, u8 src, s16 off, u8 code)\n+{\n+\tu8 t1 = MIPS_R_T6;\n+\tu8 t2 = MIPS_R_T7;\n+\n+\temit(ctx, lld, t1, off, dst);\n+\tswitch (code) {\n+\tcase BPF_ADD:\n+\t\temit(ctx, daddu, t2, t1, src);\n+\t\tbreak;\n+\tcase BPF_AND:\n+\t\temit(ctx, and, t2, t1, src);\n+\t\tbreak;\n+\tcase BPF_OR:\n+\t\temit(ctx, or, t2, t1, src);\n+\t\tbreak;\n+\tcase BPF_XOR:\n+\t\temit(ctx, xor, t2, t1, src);\n+\t\tbreak;\n+\t}\n+\temit(ctx, scd, t2, off, dst);\n+\temit(ctx, beqz, t2, -16);\n+\temit(ctx, nop); /* Delay slot */\n+}\n+\n+/* Function call */\n+static int emit_call(struct jit_context *ctx, const struct bpf_insn *insn)\n+{\n+\tu8 zx = bpf2mips64[JIT_REG_ZX];\n+\tu8 tmp = MIPS_R_T6;\n+\tbool fixed;\n+\tu64 addr;\n+\n+\t/* Decode the call address */\n+\tif (bpf_jit_get_func_addr(ctx->program, insn, false,\n+\t\t\t\t  &addr, &fixed) < 0)\n+\t\treturn -1;\n+\tif (!fixed)\n+\t\treturn -1;\n+\n+\t/* Push caller-saved registers on stack */\n+\tpush_regs(ctx, ctx->clobbered & JIT_CALLER_REGS, 0, 0);\n+\n+\t/* Emit function call */\n+\temit_mov_i64(ctx, tmp, addr);\n+\temit(ctx, jalr, MIPS_R_RA, tmp);\n+\temit(ctx, nop); /* Delay slot */\n+\n+\t/* Restore caller-saved registers */\n+\tpop_regs(ctx, ctx->clobbered & JIT_CALLER_REGS, 0, 0);\n+\n+\t/* Re-initialize the JIT zero-extension register if accessed */\n+\tif (ctx->accessed & BIT(JIT_REG_ZX)) {\n+\t\temit(ctx, daddiu, zx, MIPS_R_ZERO, -1);\n+\t\temit(ctx, dsrl32, zx, zx, 0);\n+\t}\n+\n+\tclobber_reg(ctx, MIPS_R_RA);\n+\tclobber_reg(ctx, MIPS_R_V0);\n+\tclobber_reg(ctx, MIPS_R_V1);\n+\treturn 0;\n+}\n+\n+/* Function tail call */\n+static int emit_tail_call(struct jit_context *ctx)\n+{\n+\tu8 ary = bpf2mips64[BPF_REG_2];\n+\tu8 ind = bpf2mips64[BPF_REG_3];\n+\tu8 tcc = bpf2mips64[JIT_REG_TC];\n+\tu8 tmp = MIPS_R_T6;\n+\tint off;\n+\n+\t/*\n+\t * Tail call:\n+\t * eBPF R1 - function argument (context ptr), passed in a0-a1\n+\t * eBPF R2 - ptr to object with array of function entry points\n+\t * eBPF R3 - array index of function to be called\n+\t */\n+\n+\t/* if (ind >= ary->map.max_entries) goto out */\n+\toff = offsetof(struct bpf_array, map.max_entries);\n+\tif (off > 0x7fff)\n+\t\treturn -1;\n+\temit(ctx, lwu, tmp, off, ary);            /* tmp = ary->map.max_entrs*/\n+\temit(ctx, sltu, tmp, ind, tmp);           /* tmp = ind < t1          */\n+\temit(ctx, beqz, tmp, get_offset(ctx, 1)); /* PC += off(1) if tmp == 0*/\n+\n+\t/* if (--TCC < 0) goto out */\n+\temit(ctx, daddiu, tcc, tcc, -1);          /* tcc-- (delay slot)      */\n+\temit(ctx, bltz, tcc, get_offset(ctx, 1)); /* PC += off(1) if tcc < 0 */\n+\t\t\t\t\t\t  /* (next insn delay slot)  */\n+\t/* prog = ary->ptrs[ind] */\n+\toff = offsetof(struct bpf_array, ptrs);\n+\tif (off > 0x7fff)\n+\t\treturn -1;\n+\temit(ctx, dsll, tmp, ind, 3);             /* tmp = ind << 3          */\n+\temit(ctx, daddu, tmp, tmp, ary);          /* tmp += ary              */\n+\temit(ctx, ld, tmp, off, tmp);             /* tmp = *(tmp + off)      */\n+\n+\t/* if (prog == 0) goto out */\n+\temit(ctx, beqz, tmp, get_offset(ctx, 1)); /* PC += off(1) if tmp == 0*/\n+\temit(ctx, nop);                           /* Delay slot              */\n+\n+\t/* func = prog->bpf_func + 8 (prologue skip offset) */\n+\toff = offsetof(struct bpf_prog, bpf_func);\n+\tif (off > 0x7fff)\n+\t\treturn -1;\n+\temit(ctx, ld, tmp, off, tmp);                /* tmp = *(tmp + off)   */\n+\temit(ctx, daddiu, tmp, tmp, JIT_TCALL_SKIP); /* tmp += skip (4)      */\n+\n+\t/* goto func */\n+\tbuild_epilogue(ctx, tmp);\n+\taccess_reg(ctx, JIT_REG_TC);\n+\treturn 0;\n+}\n+\n+/*\n+ * Stack frame layout for a JITed program (stack grows down).\n+ *\n+ * Higher address  : Previous stack frame      :\n+ *                 +===========================+  <--- MIPS sp before call\n+ *                 | Callee-saved registers,   |\n+ *                 | including RA and FP       |\n+ *                 +---------------------------+  <--- eBPF FP (MIPS fp)\n+ *                 | Local eBPF variables      |\n+ *                 | allocated by program      |\n+ *                 +---------------------------+\n+ *                 | Reserved for caller-saved |\n+ *                 | registers                 |\n+ * Lower address   +===========================+  <--- MIPS sp\n+ */\n+\n+/* Build program prologue to set up the stack and registers */\n+void build_prologue(struct jit_context *ctx)\n+{\n+\tu8 fp = bpf2mips64[BPF_REG_FP];\n+\tu8 tc = bpf2mips64[JIT_REG_TC];\n+\tu8 zx = bpf2mips64[JIT_REG_ZX];\n+\tint stack, saved, locals, reserved;\n+\n+\t/*\n+\t * The first instruction initializes the tail call count register.\n+\t * On a tail call, the calling function jumps into the prologue\n+\t * after this instruction.\n+\t */\n+\temit(ctx, addiu, tc, MIPS_R_ZERO, min(MAX_TAIL_CALL_CNT + 1, 0xffff));\n+\n+\t/* === Entry-point for tail calls === */\n+\n+\t/*\n+\t * If the eBPF frame pointer and tail call count registers were\n+\t * accessed they must be preserved. Mark them as clobbered here\n+\t * to save and restore them on the stack as needed.\n+\t */\n+\tif (ctx->accessed & BIT(BPF_REG_FP))\n+\t\tclobber_reg(ctx, fp);\n+\tif (ctx->accessed & BIT(JIT_REG_TC))\n+\t\tclobber_reg(ctx, tc);\n+\tif (ctx->accessed & BIT(JIT_REG_ZX))\n+\t\tclobber_reg(ctx, zx);\n+\n+\t/* Compute the stack space needed for callee-saved registers */\n+\tsaved = hweight32(ctx->clobbered & JIT_CALLEE_REGS) * sizeof(u64);\n+\tsaved = ALIGN(saved, MIPS_STACK_ALIGNMENT);\n+\n+\t/* Stack space used by eBPF program local data */\n+\tlocals = ALIGN(ctx->program->aux->stack_depth, MIPS_STACK_ALIGNMENT);\n+\n+\t/*\n+\t * If we are emitting function calls, reserve extra stack space for\n+\t * caller-saved registers needed by the JIT. The required space is\n+\t * computed automatically during resource usage discovery (pass 1).\n+\t */\n+\treserved = ctx->stack_used;\n+\n+\t/* Allocate the stack frame */\n+\tstack = ALIGN(saved + locals + reserved, MIPS_STACK_ALIGNMENT);\n+\tif (stack)\n+\t\temit(ctx, daddiu, MIPS_R_SP, MIPS_R_SP, -stack);\n+\n+\t/* Store callee-saved registers on stack */\n+\tpush_regs(ctx, ctx->clobbered & JIT_CALLEE_REGS, 0, stack - saved);\n+\n+\t/* Initialize the eBPF frame pointer if accessed */\n+\tif (ctx->accessed & BIT(BPF_REG_FP))\n+\t\temit(ctx, daddiu, fp, MIPS_R_SP, stack - saved);\n+\n+\t/* Initialize the ePF JIT zero-extension register if accessed */\n+\tif (ctx->accessed & BIT(JIT_REG_ZX)) {\n+\t\temit(ctx, daddiu, zx, MIPS_R_ZERO, -1);\n+\t\temit(ctx, dsrl32, zx, zx, 0);\n+\t}\n+\n+\tctx->saved_size = saved;\n+\tctx->stack_size = stack;\n+}\n+\n+/* Build the program epilogue to restore the stack and registers */\n+void build_epilogue(struct jit_context *ctx, int dest_reg)\n+{\n+\t/* Restore callee-saved registers from stack */\n+\tpop_regs(ctx, ctx->clobbered & JIT_CALLEE_REGS, 0,\n+\t\t ctx->stack_size - ctx->saved_size);\n+\n+\t/* Release the stack frame */\n+\tif (ctx->stack_size)\n+\t\temit(ctx, daddiu, MIPS_R_SP, MIPS_R_SP, ctx->stack_size);\n+\n+\t/* Jump to return address and sign-extend the 32-bit return value */\n+\temit(ctx, jr, dest_reg);\n+\temit(ctx, sll, MIPS_R_V0, MIPS_R_V0, 0); /* Delay slot */\n+}\n+\n+/* Build one eBPF instruction */\n+int build_insn(const struct bpf_insn *insn, struct jit_context *ctx)\n+{\n+\tu8 dst = bpf2mips64[insn->dst_reg];\n+\tu8 src = bpf2mips64[insn->src_reg];\n+\tu8 code = insn->code;\n+\ts16 off = insn->off;\n+\ts32 imm = insn->imm;\n+\ts32 val, rel;\n+\tu8 alu, jmp;\n+\n+\tswitch (code) {\n+\t/* ALU operations */\n+\t/* dst = imm */\n+\tcase BPF_ALU | BPF_MOV | BPF_K:\n+\t\temit_mov_i(ctx, dst, imm);\n+\t\temit_zext_ver(ctx, dst);\n+\t\tbreak;\n+\t/* dst = src */\n+\tcase BPF_ALU | BPF_MOV | BPF_X:\n+\t\tif (imm == 1) {\n+\t\t\t/* Special mov32 for zext */\n+\t\t\temit_zext(ctx, dst);\n+\t\t} else {\n+\t\t\temit_mov_r(ctx, dst, src);\n+\t\t\temit_zext_ver(ctx, dst);\n+\t\t}\n+\t\tbreak;\n+\t/* dst = -dst */\n+\tcase BPF_ALU | BPF_NEG:\n+\t\temit_sext(ctx, dst, dst);\n+\t\temit_alu_i(ctx, dst, 0, BPF_NEG);\n+\t\temit_zext_ver(ctx, dst);\n+\t\tbreak;\n+\t/* dst = dst & imm */\n+\t/* dst = dst | imm */\n+\t/* dst = dst ^ imm */\n+\t/* dst = dst << imm */\n+\tcase BPF_ALU | BPF_OR | BPF_K:\n+\tcase BPF_ALU | BPF_AND | BPF_K:\n+\tcase BPF_ALU | BPF_XOR | BPF_K:\n+\tcase BPF_ALU | BPF_LSH | BPF_K:\n+\t\tif (!valid_alu_i(BPF_OP(code), imm)) {\n+\t\t\temit_mov_i(ctx, MIPS_R_T4, imm);\n+\t\t\temit_alu_r(ctx, dst, MIPS_R_T4, BPF_OP(code));\n+\t\t} else if (rewrite_alu_i(BPF_OP(code), imm, &alu, &val)) {\n+\t\t\temit_alu_i(ctx, dst, val, alu);\n+\t\t}\n+\t\temit_zext_ver(ctx, dst);\n+\t\tbreak;\n+\t/* dst = dst >> imm */\n+\t/* dst = dst >> imm (arithmetic) */\n+\t/* dst = dst + imm */\n+\t/* dst = dst - imm */\n+\t/* dst = dst * imm */\n+\t/* dst = dst / imm */\n+\t/* dst = dst % imm */\n+\tcase BPF_ALU | BPF_RSH | BPF_K:\n+\tcase BPF_ALU | BPF_ARSH | BPF_K:\n+\tcase BPF_ALU | BPF_ADD | BPF_K:\n+\tcase BPF_ALU | BPF_SUB | BPF_K:\n+\tcase BPF_ALU | BPF_MUL | BPF_K:\n+\tcase BPF_ALU | BPF_DIV | BPF_K:\n+\tcase BPF_ALU | BPF_MOD | BPF_K:\n+\t\tif (!valid_alu_i(BPF_OP(code), imm)) {\n+\t\t\temit_sext(ctx, dst, dst);\n+\t\t\temit_mov_i(ctx, MIPS_R_T4, imm);\n+\t\t\temit_alu_r(ctx, dst, MIPS_R_T4, BPF_OP(code));\n+\t\t} else if (rewrite_alu_i(BPF_OP(code), imm, &alu, &val)) {\n+\t\t\temit_sext(ctx, dst, dst);\n+\t\t\temit_alu_i(ctx, dst, val, alu);\n+\t\t}\n+\t\temit_zext_ver(ctx, dst);\n+\t\tbreak;\n+\t/* dst = dst & src */\n+\t/* dst = dst | src */\n+\t/* dst = dst ^ src */\n+\t/* dst = dst << src */\n+\tcase BPF_ALU | BPF_AND | BPF_X:\n+\tcase BPF_ALU | BPF_OR | BPF_X:\n+\tcase BPF_ALU | BPF_XOR | BPF_X:\n+\tcase BPF_ALU | BPF_LSH | BPF_X:\n+\t\temit_alu_r(ctx, dst, src, BPF_OP(code));\n+\t\temit_zext_ver(ctx, dst);\n+\t\tbreak;\n+\t/* dst = dst >> src */\n+\t/* dst = dst >> src (arithmetic) */\n+\t/* dst = dst + src */\n+\t/* dst = dst - src */\n+\t/* dst = dst * src */\n+\t/* dst = dst / src */\n+\t/* dst = dst % src */\n+\tcase BPF_ALU | BPF_RSH | BPF_X:\n+\tcase BPF_ALU | BPF_ARSH | BPF_X:\n+\tcase BPF_ALU | BPF_ADD | BPF_X:\n+\tcase BPF_ALU | BPF_SUB | BPF_X:\n+\tcase BPF_ALU | BPF_MUL | BPF_X:\n+\tcase BPF_ALU | BPF_DIV | BPF_X:\n+\tcase BPF_ALU | BPF_MOD | BPF_X:\n+\t\temit_sext(ctx, dst, dst);\n+\t\temit_sext(ctx, MIPS_R_T4, src);\n+\t\temit_alu_r(ctx, dst, MIPS_R_T4, BPF_OP(code));\n+\t\temit_zext_ver(ctx, dst);\n+\t\tbreak;\n+\t/* dst = imm (64-bit) */\n+\tcase BPF_ALU64 | BPF_MOV | BPF_K:\n+\t\temit_mov_i(ctx, dst, imm);\n+\t\tbreak;\n+\t/* dst = src (64-bit) */\n+\tcase BPF_ALU64 | BPF_MOV | BPF_X:\n+\t\temit_mov_r(ctx, dst, src);\n+\t\tbreak;\n+\t/* dst = -dst (64-bit) */\n+\tcase BPF_ALU64 | BPF_NEG:\n+\t\temit_alu_i64(ctx, dst, 0, BPF_NEG);\n+\t\tbreak;\n+\t/* dst = dst & imm (64-bit) */\n+\t/* dst = dst | imm (64-bit) */\n+\t/* dst = dst ^ imm (64-bit) */\n+\t/* dst = dst << imm (64-bit) */\n+\t/* dst = dst >> imm (64-bit) */\n+\t/* dst = dst >> imm ((64-bit, arithmetic) */\n+\t/* dst = dst + imm (64-bit) */\n+\t/* dst = dst - imm (64-bit) */\n+\t/* dst = dst * imm (64-bit) */\n+\t/* dst = dst / imm (64-bit) */\n+\t/* dst = dst % imm (64-bit) */\n+\tcase BPF_ALU64 | BPF_AND | BPF_K:\n+\tcase BPF_ALU64 | BPF_OR | BPF_K:\n+\tcase BPF_ALU64 | BPF_XOR | BPF_K:\n+\tcase BPF_ALU64 | BPF_LSH | BPF_K:\n+\tcase BPF_ALU64 | BPF_RSH | BPF_K:\n+\tcase BPF_ALU64 | BPF_ARSH | BPF_K:\n+\tcase BPF_ALU64 | BPF_ADD | BPF_K:\n+\tcase BPF_ALU64 | BPF_SUB | BPF_K:\n+\tcase BPF_ALU64 | BPF_MUL | BPF_K:\n+\tcase BPF_ALU64 | BPF_DIV | BPF_K:\n+\tcase BPF_ALU64 | BPF_MOD | BPF_K:\n+\t\tif (!valid_alu_i(BPF_OP(code), imm)) {\n+\t\t\temit_mov_i(ctx, MIPS_R_T4, imm);\n+\t\t\temit_alu_r64(ctx, dst, MIPS_R_T4, BPF_OP(code));\n+\t\t} else if (rewrite_alu_i(BPF_OP(code), imm, &alu, &val)) {\n+\t\t\temit_alu_i64(ctx, dst, val, alu);\n+\t\t}\n+\t\tbreak;\n+\t/* dst = dst & src (64-bit) */\n+\t/* dst = dst | src (64-bit) */\n+\t/* dst = dst ^ src (64-bit) */\n+\t/* dst = dst << src (64-bit) */\n+\t/* dst = dst >> src (64-bit) */\n+\t/* dst = dst >> src (64-bit, arithmetic) */\n+\t/* dst = dst + src (64-bit) */\n+\t/* dst = dst - src (64-bit) */\n+\t/* dst = dst * src (64-bit) */\n+\t/* dst = dst / src (64-bit) */\n+\t/* dst = dst % src (64-bit) */\n+\tcase BPF_ALU64 | BPF_AND | BPF_X:\n+\tcase BPF_ALU64 | BPF_OR | BPF_X:\n+\tcase BPF_ALU64 | BPF_XOR | BPF_X:\n+\tcase BPF_ALU64 | BPF_LSH | BPF_X:\n+\tcase BPF_ALU64 | BPF_RSH | BPF_X:\n+\tcase BPF_ALU64 | BPF_ARSH | BPF_X:\n+\tcase BPF_ALU64 | BPF_ADD | BPF_X:\n+\tcase BPF_ALU64 | BPF_SUB | BPF_X:\n+\tcase BPF_ALU64 | BPF_MUL | BPF_X:\n+\tcase BPF_ALU64 | BPF_DIV | BPF_X:\n+\tcase BPF_ALU64 | BPF_MOD | BPF_X:\n+\t\temit_alu_r64(ctx, dst, src, BPF_OP(code));\n+\t\tbreak;\n+\t/* dst = htole(dst) */\n+\t/* dst = htobe(dst) */\n+\tcase BPF_ALU | BPF_END | BPF_FROM_LE:\n+\tcase BPF_ALU | BPF_END | BPF_FROM_BE:\n+\t\tif (BPF_SRC(code) ==\n+#ifdef __BIG_ENDIAN\n+\t\t    BPF_FROM_LE\n+#else\n+\t\t    BPF_FROM_BE\n+#endif\n+\t\t    )\n+\t\t\temit_bswap_r64(ctx, dst, imm);\n+\t\telse\n+\t\t\temit_trunc_r64(ctx, dst, imm);\n+\t\tbreak;\n+\t/* dst = imm64 */\n+\tcase BPF_LD | BPF_IMM | BPF_DW:\n+\t\temit_mov_i64(ctx, dst, (u32)imm | ((u64)insn[1].imm << 32));\n+\t\treturn 1;\n+\t/* LDX: dst = *(size *)(src + off) */\n+\tcase BPF_LDX | BPF_MEM | BPF_W:\n+\tcase BPF_LDX | BPF_MEM | BPF_H:\n+\tcase BPF_LDX | BPF_MEM | BPF_B:\n+\tcase BPF_LDX | BPF_MEM | BPF_DW:\n+\t\temit_ldx(ctx, dst, src, off, BPF_SIZE(code));\n+\t\tbreak;\n+\t/* ST: *(size *)(dst + off) = imm */\n+\tcase BPF_ST | BPF_MEM | BPF_W:\n+\tcase BPF_ST | BPF_MEM | BPF_H:\n+\tcase BPF_ST | BPF_MEM | BPF_B:\n+\tcase BPF_ST | BPF_MEM | BPF_DW:\n+\t\temit_mov_i(ctx, MIPS_R_T4, imm);\n+\t\temit_stx(ctx, dst, MIPS_R_T4, off, BPF_SIZE(code));\n+\t\tbreak;\n+\t/* STX: *(size *)(dst + off) = src */\n+\tcase BPF_STX | BPF_MEM | BPF_W:\n+\tcase BPF_STX | BPF_MEM | BPF_H:\n+\tcase BPF_STX | BPF_MEM | BPF_B:\n+\tcase BPF_STX | BPF_MEM | BPF_DW:\n+\t\temit_stx(ctx, dst, src, off, BPF_SIZE(code));\n+\t\tbreak;\n+\t/* Speculation barrier */\n+\tcase BPF_ST | BPF_NOSPEC:\n+\t\tbreak;\n+\t/* Atomics */\n+\tcase BPF_STX | BPF_XADD | BPF_W:\n+\tcase BPF_STX | BPF_XADD | BPF_DW:\n+\t\tswitch (imm) {\n+\t\tcase BPF_ADD:\n+\t\tcase BPF_AND:\n+\t\tcase BPF_OR:\n+\t\tcase BPF_XOR:\n+\t\t\tif (BPF_SIZE(code) == BPF_DW) {\n+\t\t\t\temit_atomic_r64(ctx, dst, src, off, imm);\n+\t\t\t} else { /* 32-bit, no fetch */\n+\t\t\t\temit_sext(ctx, MIPS_R_T4, src);\n+\t\t\t\temit_atomic_r(ctx, dst, MIPS_R_T4, off, imm);\n+\t\t\t}\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tgoto notyet;\n+\t\t}\n+\t\tbreak;\n+\t/* PC += off if dst == src */\n+\t/* PC += off if dst != src */\n+\t/* PC += off if dst & src */\n+\t/* PC += off if dst > src */\n+\t/* PC += off if dst >= src */\n+\t/* PC += off if dst < src */\n+\t/* PC += off if dst <= src */\n+\t/* PC += off if dst > src (signed) */\n+\t/* PC += off if dst >= src (signed) */\n+\t/* PC += off if dst < src (signed) */\n+\t/* PC += off if dst <= src (signed) */\n+\tcase BPF_JMP32 | BPF_JEQ | BPF_X:\n+\tcase BPF_JMP32 | BPF_JNE | BPF_X:\n+\tcase BPF_JMP32 | BPF_JSET | BPF_X:\n+\tcase BPF_JMP32 | BPF_JGT | BPF_X:\n+\tcase BPF_JMP32 | BPF_JGE | BPF_X:\n+\tcase BPF_JMP32 | BPF_JLT | BPF_X:\n+\tcase BPF_JMP32 | BPF_JLE | BPF_X:\n+\tcase BPF_JMP32 | BPF_JSGT | BPF_X:\n+\tcase BPF_JMP32 | BPF_JSGE | BPF_X:\n+\tcase BPF_JMP32 | BPF_JSLT | BPF_X:\n+\tcase BPF_JMP32 | BPF_JSLE | BPF_X:\n+\t\tif (off == 0)\n+\t\t\tbreak;\n+\t\tsetup_jmp_r(ctx, dst == src, BPF_OP(code), off, &jmp, &rel);\n+\t\temit_sext(ctx, MIPS_R_T4, dst); /* Sign-extended dst */\n+\t\temit_sext(ctx, MIPS_R_T5, src); /* Sign-extended src */\n+\t\temit_jmp_r(ctx, MIPS_R_T4, MIPS_R_T5, rel, jmp);\n+\t\tif (finish_jmp(ctx, jmp, off) < 0)\n+\t\t\tgoto toofar;\n+\t\tbreak;\n+\t/* PC += off if dst == imm */\n+\t/* PC += off if dst != imm */\n+\t/* PC += off if dst & imm */\n+\t/* PC += off if dst > imm */\n+\t/* PC += off if dst >= imm */\n+\t/* PC += off if dst < imm */\n+\t/* PC += off if dst <= imm */\n+\t/* PC += off if dst > imm (signed) */\n+\t/* PC += off if dst >= imm (signed) */\n+\t/* PC += off if dst < imm (signed) */\n+\t/* PC += off if dst <= imm (signed) */\n+\tcase BPF_JMP32 | BPF_JEQ | BPF_K:\n+\tcase BPF_JMP32 | BPF_JNE | BPF_K:\n+\tcase BPF_JMP32 | BPF_JSET | BPF_K:\n+\tcase BPF_JMP32 | BPF_JGT | BPF_K:\n+\tcase BPF_JMP32 | BPF_JGE | BPF_K:\n+\tcase BPF_JMP32 | BPF_JLT | BPF_K:\n+\tcase BPF_JMP32 | BPF_JLE | BPF_K:\n+\tcase BPF_JMP32 | BPF_JSGT | BPF_K:\n+\tcase BPF_JMP32 | BPF_JSGE | BPF_K:\n+\tcase BPF_JMP32 | BPF_JSLT | BPF_K:\n+\tcase BPF_JMP32 | BPF_JSLE | BPF_K:\n+\t\tif (off == 0)\n+\t\t\tbreak;\n+\t\tsetup_jmp_i(ctx, imm, 32, BPF_OP(code), off, &jmp, &rel);\n+\t\temit_sext(ctx, MIPS_R_T4, dst); /* Sign-extended dst */\n+\t\tif (valid_jmp_i(jmp, imm)) {\n+\t\t\temit_jmp_i(ctx, MIPS_R_T4, imm, rel, jmp);\n+\t\t} else {\n+\t\t\t/* Move large immediate to register, sign-extended */\n+\t\t\temit_mov_i(ctx, MIPS_R_T5, imm);\n+\t\t\temit_jmp_r(ctx, MIPS_R_T4, MIPS_R_T5, rel, jmp);\n+\t\t}\n+\t\tif (finish_jmp(ctx, jmp, off) < 0)\n+\t\t\tgoto toofar;\n+\t\tbreak;\n+\t/* PC += off if dst == src */\n+\t/* PC += off if dst != src */\n+\t/* PC += off if dst & src */\n+\t/* PC += off if dst > src */\n+\t/* PC += off if dst >= src */\n+\t/* PC += off if dst < src */\n+\t/* PC += off if dst <= src */\n+\t/* PC += off if dst > src (signed) */\n+\t/* PC += off if dst >= src (signed) */\n+\t/* PC += off if dst < src (signed) */\n+\t/* PC += off if dst <= src (signed) */\n+\tcase BPF_JMP | BPF_JEQ | BPF_X:\n+\tcase BPF_JMP | BPF_JNE | BPF_X:\n+\tcase BPF_JMP | BPF_JSET | BPF_X:\n+\tcase BPF_JMP | BPF_JGT | BPF_X:\n+\tcase BPF_JMP | BPF_JGE | BPF_X:\n+\tcase BPF_JMP | BPF_JLT | BPF_X:\n+\tcase BPF_JMP | BPF_JLE | BPF_X:\n+\tcase BPF_JMP | BPF_JSGT | BPF_X:\n+\tcase BPF_JMP | BPF_JSGE | BPF_X:\n+\tcase BPF_JMP | BPF_JSLT | BPF_X:\n+\tcase BPF_JMP | BPF_JSLE | BPF_X:\n+\t\tif (off == 0)\n+\t\t\tbreak;\n+\t\tsetup_jmp_r(ctx, dst == src, BPF_OP(code), off, &jmp, &rel);\n+\t\temit_jmp_r(ctx, dst, src, rel, jmp);\n+\t\tif (finish_jmp(ctx, jmp, off) < 0)\n+\t\t\tgoto toofar;\n+\t\tbreak;\n+\t/* PC += off if dst == imm */\n+\t/* PC += off if dst != imm */\n+\t/* PC += off if dst & imm */\n+\t/* PC += off if dst > imm */\n+\t/* PC += off if dst >= imm */\n+\t/* PC += off if dst < imm */\n+\t/* PC += off if dst <= imm */\n+\t/* PC += off if dst > imm (signed) */\n+\t/* PC += off if dst >= imm (signed) */\n+\t/* PC += off if dst < imm (signed) */\n+\t/* PC += off if dst <= imm (signed) */\n+\tcase BPF_JMP | BPF_JEQ | BPF_K:\n+\tcase BPF_JMP | BPF_JNE | BPF_K:\n+\tcase BPF_JMP | BPF_JSET | BPF_K:\n+\tcase BPF_JMP | BPF_JGT | BPF_K:\n+\tcase BPF_JMP | BPF_JGE | BPF_K:\n+\tcase BPF_JMP | BPF_JLT | BPF_K:\n+\tcase BPF_JMP | BPF_JLE | BPF_K:\n+\tcase BPF_JMP | BPF_JSGT | BPF_K:\n+\tcase BPF_JMP | BPF_JSGE | BPF_K:\n+\tcase BPF_JMP | BPF_JSLT | BPF_K:\n+\tcase BPF_JMP | BPF_JSLE | BPF_K:\n+\t\tif (off == 0)\n+\t\t\tbreak;\n+\t\tsetup_jmp_i(ctx, imm, 64, BPF_OP(code), off, &jmp, &rel);\n+\t\tif (valid_jmp_i(jmp, imm)) {\n+\t\t\temit_jmp_i(ctx, dst, imm, rel, jmp);\n+\t\t} else {\n+\t\t\t/* Move large immediate to register */\n+\t\t\temit_mov_i(ctx, MIPS_R_T4, imm);\n+\t\t\temit_jmp_r(ctx, dst, MIPS_R_T4, rel, jmp);\n+\t\t}\n+\t\tif (finish_jmp(ctx, jmp, off) < 0)\n+\t\t\tgoto toofar;\n+\t\tbreak;\n+\t/* PC += off */\n+\tcase BPF_JMP | BPF_JA:\n+\t\tif (off == 0)\n+\t\t\tbreak;\n+\t\tif (emit_ja(ctx, off) < 0)\n+\t\t\tgoto toofar;\n+\t\tbreak;\n+\t/* Tail call */\n+\tcase BPF_JMP | BPF_TAIL_CALL:\n+\t\tif (emit_tail_call(ctx) < 0)\n+\t\t\tgoto invalid;\n+\t\tbreak;\n+\t/* Function call */\n+\tcase BPF_JMP | BPF_CALL:\n+\t\tif (emit_call(ctx, insn) < 0)\n+\t\t\tgoto invalid;\n+\t\tbreak;\n+\t/* Function return */\n+\tcase BPF_JMP | BPF_EXIT:\n+\t\t/*\n+\t\t * Optimization: when last instruction is EXIT\n+\t\t * simply continue to epilogue.\n+\t\t */\n+\t\tif (ctx->bpf_index == ctx->program->len - 1)\n+\t\t\tbreak;\n+\t\tif (emit_exit(ctx) < 0)\n+\t\t\tgoto toofar;\n+\t\tbreak;\n+\n+\tdefault:\n+invalid:\n+\t\tpr_err_once(\"unknown opcode %02x\\n\", code);\n+\t\treturn -EINVAL;\n+notyet:\n+\t\tpr_info_once(\"*** NOT YET: opcode %02x ***\\n\", code);\n+\t\treturn -EFAULT;\n+toofar:\n+\t\tpr_info_once(\"*** TOO FAR: jump at %u opcode %02x ***\\n\",\n+\t\t\t     ctx->bpf_index, code);\n+\t\treturn -E2BIG;\n+\t}\n+\treturn 0;\n+}\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/050-v5.16-04-mips-bpf-Add-JIT-workarounds-for-CPU-errata.patch",
    "content": "From: Johan Almbladh <johan.almbladh@anyfinetworks.com>\nDate: Tue, 5 Oct 2021 18:54:06 +0200\nSubject: [PATCH] mips: bpf: Add JIT workarounds for CPU errata\n\nThis patch adds workarounds for the following CPU errata to the MIPS\neBPF JIT, if enabled in the kernel configuration.\n\n  - R10000 ll/sc weak ordering\n  - Loongson-3 ll/sc weak ordering\n  - Loongson-2F jump hang\n\nThe Loongson-2F nop errata is implemented in uasm, which the JIT uses,\nso no additional mitigations are needed for that.\n\nSigned-off-by: Johan Almbladh <johan.almbladh@anyfinetworks.com>\nReviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>\n---\n\n--- a/arch/mips/net/bpf_jit_comp.c\n+++ b/arch/mips/net/bpf_jit_comp.c\n@@ -404,6 +404,7 @@ void emit_alu_r(struct jit_context *ctx,\n /* Atomic read-modify-write (32-bit) */\n void emit_atomic_r(struct jit_context *ctx, u8 dst, u8 src, s16 off, u8 code)\n {\n+\tLLSC_sync(ctx);\n \temit(ctx, ll, MIPS_R_T9, off, dst);\n \tswitch (code) {\n \tcase BPF_ADD:\n@@ -420,18 +421,19 @@ void emit_atomic_r(struct jit_context *c\n \t\tbreak;\n \t}\n \temit(ctx, sc, MIPS_R_T8, off, dst);\n-\temit(ctx, beqz, MIPS_R_T8, -16);\n+\temit(ctx, LLSC_beqz, MIPS_R_T8, -16 - LLSC_offset);\n \temit(ctx, nop); /* Delay slot */\n }\n \n /* Atomic compare-and-exchange (32-bit) */\n void emit_cmpxchg_r(struct jit_context *ctx, u8 dst, u8 src, u8 res, s16 off)\n {\n+\tLLSC_sync(ctx);\n \temit(ctx, ll, MIPS_R_T9, off, dst);\n \temit(ctx, bne, MIPS_R_T9, res, 12);\n \temit(ctx, move, MIPS_R_T8, src);     /* Delay slot */\n \temit(ctx, sc, MIPS_R_T8, off, dst);\n-\temit(ctx, beqz, MIPS_R_T8, -20);\n+\temit(ctx, LLSC_beqz, MIPS_R_T8, -20 - LLSC_offset);\n \temit(ctx, move, res, MIPS_R_T9);     /* Delay slot */\n \tclobber_reg(ctx, res);\n }\n--- a/arch/mips/net/bpf_jit_comp.h\n+++ b/arch/mips/net/bpf_jit_comp.h\n@@ -87,7 +87,7 @@ struct jit_context {\n };\n \n /* Emit the instruction if the JIT memory space has been allocated */\n-#define emit(ctx, func, ...)\t\t\t\t\t\\\n+#define __emit(ctx, func, ...)\t\t\t\t\t\\\n do {\t\t\t\t\t\t\t\t\\\n \tif ((ctx)->target != NULL) {\t\t\t\t\\\n \t\tu32 *p = &(ctx)->target[ctx->jit_index];\t\\\n@@ -95,6 +95,30 @@ do {\t\t\t\t\t\t\t\t\\\n \t}\t\t\t\t\t\t\t\\\n \t(ctx)->jit_index++;\t\t\t\t\t\\\n } while (0)\n+#define emit(...) __emit(__VA_ARGS__)\n+\n+/* Workaround for R10000 ll/sc errata */\n+#ifdef CONFIG_WAR_R10000\n+#define LLSC_beqz\tbeqzl\n+#else\n+#define LLSC_beqz\tbeqz\n+#endif\n+\n+/* Workaround for Loongson-3 ll/sc errata */\n+#ifdef CONFIG_CPU_LOONGSON3_WORKAROUNDS\n+#define LLSC_sync(ctx)\temit(ctx, sync, 0)\n+#define LLSC_offset\t4\n+#else\n+#define LLSC_sync(ctx)\n+#define LLSC_offset\t0\n+#endif\n+\n+/* Workaround for Loongson-2F jump errata */\n+#ifdef CONFIG_CPU_JUMP_WORKAROUNDS\n+#define JALR_MASK\t0xffffffffcfffffffULL\n+#else\n+#define JALR_MASK\t(~0ULL)\n+#endif\n \n /*\n  * Mark a BPF register as accessed, it needs to be\n--- a/arch/mips/net/bpf_jit_comp64.c\n+++ b/arch/mips/net/bpf_jit_comp64.c\n@@ -375,6 +375,7 @@ static void emit_atomic_r64(struct jit_c\n \tu8 t1 = MIPS_R_T6;\n \tu8 t2 = MIPS_R_T7;\n \n+\tLLSC_sync(ctx);\n \temit(ctx, lld, t1, off, dst);\n \tswitch (code) {\n \tcase BPF_ADD:\n@@ -391,7 +392,7 @@ static void emit_atomic_r64(struct jit_c\n \t\tbreak;\n \t}\n \temit(ctx, scd, t2, off, dst);\n-\temit(ctx, beqz, t2, -16);\n+\temit(ctx, LLSC_beqz, t2, -16 - LLSC_offset);\n \temit(ctx, nop); /* Delay slot */\n }\n \n@@ -414,7 +415,7 @@ static int emit_call(struct jit_context\n \tpush_regs(ctx, ctx->clobbered & JIT_CALLER_REGS, 0, 0);\n \n \t/* Emit function call */\n-\temit_mov_i64(ctx, tmp, addr);\n+\temit_mov_i64(ctx, tmp, addr & JALR_MASK);\n \temit(ctx, jalr, MIPS_R_RA, tmp);\n \temit(ctx, nop); /* Delay slot */\n \n"
  },
  {
    "path": "target/linux/generic/backport-5.10/050-v5.16-05-mips-bpf-Enable-eBPF-JITs.patch",
    "content": "From: Johan Almbladh <johan.almbladh@anyfinetworks.com>\nDate: Tue, 5 Oct 2021 18:54:07 +0200\nSubject: [PATCH] mips: bpf: Enable eBPF JITs\n\nThis patch enables the new eBPF JITs for 32-bit and 64-bit MIPS. It also\ndisables the old cBPF JIT to so cBPF programs are converted to use the\nnew JIT.\n\nWorkarounds for R4000 CPU errata are not implemented by the JIT, so the\nJIT is disabled if any of those workarounds are configured.\n\nSigned-off-by: Johan Almbladh <johan.almbladh@anyfinetworks.com>\n---\n\n--- a/MAINTAINERS\n+++ b/MAINTAINERS\n@@ -3294,6 +3294,7 @@ S:\tSupported\n F:\tarch/arm64/net/\n \n BPF JIT for MIPS (32-BIT AND 64-BIT)\n+M:\tJohan Almbladh <johan.almbladh@anyfinetworks.com>\n M:\tPaul Burton <paulburton@kernel.org>\n L:\tnetdev@vger.kernel.org\n L:\tbpf@vger.kernel.org\n--- a/arch/mips/Kconfig\n+++ b/arch/mips/Kconfig\n@@ -49,7 +49,6 @@ config MIPS\n \tselect HAVE_ARCH_TRACEHOOK\n \tselect HAVE_ARCH_TRANSPARENT_HUGEPAGE if CPU_SUPPORTS_HUGEPAGES\n \tselect HAVE_ASM_MODVERSIONS\n-\tselect HAVE_CBPF_JIT if !64BIT && !CPU_MICROMIPS\n \tselect HAVE_CONTEXT_TRACKING\n \tselect HAVE_TIF_NOHZ\n \tselect HAVE_C_RECORDMCOUNT\n@@ -57,7 +56,10 @@ config MIPS\n \tselect HAVE_DEBUG_STACKOVERFLOW\n \tselect HAVE_DMA_CONTIGUOUS\n \tselect HAVE_DYNAMIC_FTRACE\n-\tselect HAVE_EBPF_JIT if 64BIT && !CPU_MICROMIPS && TARGET_ISA_REV >= 2\n+\tselect HAVE_EBPF_JIT if !CPU_MICROMIPS && \\\n+\t\t\t\t!CPU_DADDI_WORKAROUNDS && \\\n+\t\t\t\t!CPU_R4000_WORKAROUNDS && \\\n+\t\t\t\t!CPU_R4400_WORKAROUNDS\n \tselect HAVE_EXIT_THREAD\n \tselect HAVE_FAST_GUP\n \tselect HAVE_FTRACE_MCOUNT_RECORD\n--- a/arch/mips/net/Makefile\n+++ b/arch/mips/net/Makefile\n@@ -2,9 +2,10 @@\n # MIPS networking code\n \n obj-$(CONFIG_MIPS_CBPF_JIT) += bpf_jit.o bpf_jit_asm.o\n+obj-$(CONFIG_MIPS_EBPF_JIT) += bpf_jit_comp.o\n \n ifeq ($(CONFIG_32BIT),y)\n-        obj-$(CONFIG_MIPS_EBPF_JIT) += bpf_jit_comp.o bpf_jit_comp32.o\n+        obj-$(CONFIG_MIPS_EBPF_JIT) += bpf_jit_comp32.o\n else\n-        obj-$(CONFIG_MIPS_EBPF_JIT) += ebpf_jit.o\n+        obj-$(CONFIG_MIPS_EBPF_JIT) += bpf_jit_comp64.o\n endif\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/050-v5.16-06-mips-bpf-Remove-old-BPF-JIT-implementations.patch",
    "content": "From: Johan Almbladh <johan.almbladh@anyfinetworks.com>\nDate: Tue, 5 Oct 2021 18:54:08 +0200\nSubject: [PATCH] mips: bpf: Remove old BPF JIT implementations\n\nThis patch removes the old 32-bit cBPF and 64-bit eBPF JIT implementations.\nThey are replaced by a new eBPF implementation that supports both 32-bit\nand 64-bit MIPS CPUs.\n\nSigned-off-by: Johan Almbladh <johan.almbladh@anyfinetworks.com>\n---\n delete mode 100644 arch/mips/net/bpf_jit.c\n delete mode 100644 arch/mips/net/bpf_jit.h\n delete mode 100644 arch/mips/net/bpf_jit_asm.S\n delete mode 100644 arch/mips/net/ebpf_jit.c\n\n--- a/arch/mips/net/bpf_jit.h\n+++ /dev/null\n@@ -1,81 +0,0 @@\n-/* SPDX-License-Identifier: GPL-2.0-only */\n-/*\n- * Just-In-Time compiler for BPF filters on MIPS\n- *\n- * Copyright (c) 2014 Imagination Technologies Ltd.\n- * Author: Markos Chandras <markos.chandras@imgtec.com>\n- */\n-\n-#ifndef BPF_JIT_MIPS_OP_H\n-#define BPF_JIT_MIPS_OP_H\n-\n-/* Registers used by JIT */\n-#define MIPS_R_ZERO\t0\n-#define MIPS_R_V0\t2\n-#define MIPS_R_A0\t4\n-#define MIPS_R_A1\t5\n-#define MIPS_R_T4\t12\n-#define MIPS_R_T5\t13\n-#define MIPS_R_T6\t14\n-#define MIPS_R_T7\t15\n-#define MIPS_R_S0\t16\n-#define MIPS_R_S1\t17\n-#define MIPS_R_S2\t18\n-#define MIPS_R_S3\t19\n-#define MIPS_R_S4\t20\n-#define MIPS_R_S5\t21\n-#define MIPS_R_S6\t22\n-#define MIPS_R_S7\t23\n-#define MIPS_R_SP\t29\n-#define MIPS_R_RA\t31\n-\n-/* Conditional codes */\n-#define MIPS_COND_EQ\t0x1\n-#define MIPS_COND_GE\t(0x1 << 1)\n-#define MIPS_COND_GT\t(0x1 << 2)\n-#define MIPS_COND_NE\t(0x1 << 3)\n-#define MIPS_COND_ALL\t(0x1 << 4)\n-/* Conditionals on X register or K immediate */\n-#define MIPS_COND_X\t(0x1 << 5)\n-#define MIPS_COND_K\t(0x1 << 6)\n-\n-#define r_ret\tMIPS_R_V0\n-\n-/*\n- * Use 2 scratch registers to avoid pipeline interlocks.\n- * There is no overhead during epilogue and prologue since\n- * any of the $s0-$s6 registers will only be preserved if\n- * they are going to actually be used.\n- */\n-#define r_skb_hl\tMIPS_R_S0 /* skb header length */\n-#define r_skb_data\tMIPS_R_S1 /* skb actual data */\n-#define r_off\t\tMIPS_R_S2\n-#define r_A\t\tMIPS_R_S3\n-#define r_X\t\tMIPS_R_S4\n-#define r_skb\t\tMIPS_R_S5\n-#define r_M\t\tMIPS_R_S6\n-#define r_skb_len\tMIPS_R_S7\n-#define r_s0\t\tMIPS_R_T4 /* scratch reg 1 */\n-#define r_s1\t\tMIPS_R_T5 /* scratch reg 2 */\n-#define r_tmp_imm\tMIPS_R_T6 /* No need to preserve this */\n-#define r_tmp\t\tMIPS_R_T7 /* No need to preserve this */\n-#define r_zero\t\tMIPS_R_ZERO\n-#define r_sp\t\tMIPS_R_SP\n-#define r_ra\t\tMIPS_R_RA\n-\n-#ifndef __ASSEMBLY__\n-\n-/* Declare ASM helpers */\n-\n-#define DECLARE_LOAD_FUNC(func) \\\n-\textern u8 func(unsigned long *skb, int offset); \\\n-\textern u8 func##_negative(unsigned long *skb, int offset); \\\n-\textern u8 func##_positive(unsigned long *skb, int offset)\n-\n-DECLARE_LOAD_FUNC(sk_load_word);\n-DECLARE_LOAD_FUNC(sk_load_half);\n-DECLARE_LOAD_FUNC(sk_load_byte);\n-\n-#endif\n-\n-#endif /* BPF_JIT_MIPS_OP_H */\n--- a/arch/mips/net/bpf_jit_asm.S\n+++ /dev/null\n@@ -1,285 +0,0 @@\n-/*\n- * bpf_jib_asm.S: Packet/header access helper functions for MIPS/MIPS64 BPF\n- * compiler.\n- *\n- * Copyright (C) 2015 Imagination Technologies Ltd.\n- * Author: Markos Chandras <markos.chandras@imgtec.com>\n- *\n- * This program is free software; you can redistribute it and/or modify it\n- * under the terms of the GNU General Public License as published by the\n- * Free Software Foundation; version 2 of the License.\n- */\n-\n-#include <asm/asm.h>\n-#include <asm/isa-rev.h>\n-#include <asm/regdef.h>\n-#include \"bpf_jit.h\"\n-\n-/* ABI\n- *\n- * r_skb_hl\tskb header length\n- * r_skb_data\tskb data\n- * r_off(a1)\toffset register\n- * r_A\t\tBPF register A\n- * r_X\t\tPF register X\n- * r_skb(a0)\t*skb\n- * r_M\t\t*scratch memory\n- * r_skb_le\tskb length\n- * r_s0\t\tScratch register 0\n- * r_s1\t\tScratch register 1\n- *\n- * On entry:\n- * a0: *skb\n- * a1: offset (imm or imm + X)\n- *\n- * All non-BPF-ABI registers are free for use. On return, we only\n- * care about r_ret. The BPF-ABI registers are assumed to remain\n- * unmodified during the entire filter operation.\n- */\n-\n-#define skb\ta0\n-#define offset\ta1\n-#define SKF_LL_OFF  (-0x200000) /* Can't include linux/filter.h in assembly */\n-\n-\t/* We know better :) so prevent assembler reordering etc */\n-\t.set \tnoreorder\n-\n-#define is_offset_negative(TYPE)\t\t\t\t\\\n-\t/* If offset is negative we have more work to do */\t\\\n-\tslti\tt0, offset, 0;\t\t\t\t\t\\\n-\tbgtz\tt0, bpf_slow_path_##TYPE##_neg;\t\t\t\\\n-\t/* Be careful what follows in DS. */\n-\n-#define is_offset_in_header(SIZE, TYPE)\t\t\t\t\\\n-\t/* Reading from header? */\t\t\t\t\\\n-\taddiu\t$r_s0, $r_skb_hl, -SIZE;\t\t\t\\\n-\tslt\tt0, $r_s0, offset;\t\t\t\t\\\n-\tbgtz\tt0, bpf_slow_path_##TYPE;\t\t\t\\\n-\n-LEAF(sk_load_word)\n-\tis_offset_negative(word)\n-FEXPORT(sk_load_word_positive)\n-\tis_offset_in_header(4, word)\n-\t/* Offset within header boundaries */\n-\tPTR_ADDU t1, $r_skb_data, offset\n-\t.set\treorder\n-\tlw\t$r_A, 0(t1)\n-\t.set\tnoreorder\n-#ifdef CONFIG_CPU_LITTLE_ENDIAN\n-# if MIPS_ISA_REV >= 2\n-\twsbh\tt0, $r_A\n-\trotr\t$r_A, t0, 16\n-# else\n-\tsll\tt0, $r_A, 24\n-\tsrl\tt1, $r_A, 24\n-\tsrl\tt2, $r_A, 8\n-\tor\tt0, t0, t1\n-\tandi\tt2, t2, 0xff00\n-\tandi\tt1, $r_A, 0xff00\n-\tor\tt0, t0, t2\n-\tsll\tt1, t1, 8\n-\tor\t$r_A, t0, t1\n-# endif\n-#endif\n-\tjr\t$r_ra\n-\t move\t$r_ret, zero\n-\tEND(sk_load_word)\n-\n-LEAF(sk_load_half)\n-\tis_offset_negative(half)\n-FEXPORT(sk_load_half_positive)\n-\tis_offset_in_header(2, half)\n-\t/* Offset within header boundaries */\n-\tPTR_ADDU t1, $r_skb_data, offset\n-\tlhu\t$r_A, 0(t1)\n-#ifdef CONFIG_CPU_LITTLE_ENDIAN\n-# if MIPS_ISA_REV >= 2\n-\twsbh\t$r_A, $r_A\n-# else\n-\tsll\tt0, $r_A, 8\n-\tsrl\tt1, $r_A, 8\n-\tandi\tt0, t0, 0xff00\n-\tor\t$r_A, t0, t1\n-# endif\n-#endif\n-\tjr\t$r_ra\n-\t move\t$r_ret, zero\n-\tEND(sk_load_half)\n-\n-LEAF(sk_load_byte)\n-\tis_offset_negative(byte)\n-FEXPORT(sk_load_byte_positive)\n-\tis_offset_in_header(1, byte)\n-\t/* Offset within header boundaries */\n-\tPTR_ADDU t1, $r_skb_data, offset\n-\tlbu\t$r_A, 0(t1)\n-\tjr\t$r_ra\n-\t move\t$r_ret, zero\n-\tEND(sk_load_byte)\n-\n-/*\n- * call skb_copy_bits:\n- * (prototype in linux/skbuff.h)\n- *\n- * int skb_copy_bits(sk_buff *skb, int offset, void *to, int len)\n- *\n- * o32 mandates we leave 4 spaces for argument registers in case\n- * the callee needs to use them. Even though we don't care about\n- * the argument registers ourselves, we need to allocate that space\n- * to remain ABI compliant since the callee may want to use that space.\n- * We also allocate 2 more spaces for $r_ra and our return register (*to).\n- *\n- * n64 is a bit different. The *caller* will allocate the space to preserve\n- * the arguments. So in 64-bit kernels, we allocate the 4-arg space for no\n- * good reason but it does not matter that much really.\n- *\n- * (void *to) is returned in r_s0\n- *\n- */\n-#ifdef CONFIG_CPU_LITTLE_ENDIAN\n-#define DS_OFFSET(SIZE) (4 * SZREG)\n-#else\n-#define DS_OFFSET(SIZE) ((4 * SZREG) + (4 - SIZE))\n-#endif\n-#define bpf_slow_path_common(SIZE)\t\t\t\t\\\n-\t/* Quick check. Are we within reasonable boundaries? */ \\\n-\tLONG_ADDIU\t$r_s1, $r_skb_len, -SIZE;\t\t\\\n-\tsltu\t\t$r_s0, offset, $r_s1;\t\t\t\\\n-\tbeqz\t\t$r_s0, fault;\t\t\t\t\\\n-\t/* Load 4th argument in DS */\t\t\t\t\\\n-\t LONG_ADDIU\ta3, zero, SIZE;\t\t\t\t\\\n-\tPTR_ADDIU\t$r_sp, $r_sp, -(6 * SZREG);\t\t\\\n-\tPTR_LA\t\tt0, skb_copy_bits;\t\t\t\\\n-\tPTR_S\t\t$r_ra, (5 * SZREG)($r_sp);\t\t\\\n-\t/* Assign low slot to a2 */\t\t\t\t\\\n-\tPTR_ADDIU\ta2, $r_sp, DS_OFFSET(SIZE);\t\t\\\n-\tjalr\t\tt0;\t\t\t\t\t\\\n-\t/* Reset our destination slot (DS but it's ok) */\t\\\n-\t INT_S\t\tzero, (4 * SZREG)($r_sp);\t\t\\\n-\t/*\t\t\t\t\t\t\t\\\n-\t * skb_copy_bits returns 0 on success and -EFAULT\t\\\n-\t * on error. Our data live in a2. Do not bother with\t\\\n-\t * our data if an error has been returned.\t\t\\\n-\t */\t\t\t\t\t\t\t\\\n-\t/* Restore our frame */\t\t\t\t\t\\\n-\tPTR_L\t\t$r_ra, (5 * SZREG)($r_sp);\t\t\\\n-\tINT_L\t\t$r_s0, (4 * SZREG)($r_sp);\t\t\\\n-\tbltz\t\tv0, fault;\t\t\t\t\\\n-\t PTR_ADDIU\t$r_sp, $r_sp, 6 * SZREG;\t\t\\\n-\tmove\t\t$r_ret, zero;\t\t\t\t\\\n-\n-NESTED(bpf_slow_path_word, (6 * SZREG), $r_sp)\n-\tbpf_slow_path_common(4)\n-#ifdef CONFIG_CPU_LITTLE_ENDIAN\n-# if MIPS_ISA_REV >= 2\n-\twsbh\tt0, $r_s0\n-\tjr\t$r_ra\n-\t rotr\t$r_A, t0, 16\n-# else\n-\tsll\tt0, $r_s0, 24\n-\tsrl\tt1, $r_s0, 24\n-\tsrl\tt2, $r_s0, 8\n-\tor\tt0, t0, t1\n-\tandi\tt2, t2, 0xff00\n-\tandi\tt1, $r_s0, 0xff00\n-\tor\tt0, t0, t2\n-\tsll\tt1, t1, 8\n-\tjr\t$r_ra\n-\t or\t$r_A, t0, t1\n-# endif\n-#else\n-\tjr\t$r_ra\n-\t move\t$r_A, $r_s0\n-#endif\n-\n-\tEND(bpf_slow_path_word)\n-\n-NESTED(bpf_slow_path_half, (6 * SZREG), $r_sp)\n-\tbpf_slow_path_common(2)\n-#ifdef CONFIG_CPU_LITTLE_ENDIAN\n-# if MIPS_ISA_REV >= 2\n-\tjr\t$r_ra\n-\t wsbh\t$r_A, $r_s0\n-# else\n-\tsll\tt0, $r_s0, 8\n-\tandi\tt1, $r_s0, 0xff00\n-\tandi\tt0, t0, 0xff00\n-\tsrl\tt1, t1, 8\n-\tjr\t$r_ra\n-\t or\t$r_A, t0, t1\n-# endif\n-#else\n-\tjr\t$r_ra\n-\t move\t$r_A, $r_s0\n-#endif\n-\n-\tEND(bpf_slow_path_half)\n-\n-NESTED(bpf_slow_path_byte, (6 * SZREG), $r_sp)\n-\tbpf_slow_path_common(1)\n-\tjr\t$r_ra\n-\t move\t$r_A, $r_s0\n-\n-\tEND(bpf_slow_path_byte)\n-\n-/*\n- * Negative entry points\n- */\n-\t.macro bpf_is_end_of_data\n-\tli\tt0, SKF_LL_OFF\n-\t/* Reading link layer data? */\n-\tslt\tt1, offset, t0\n-\tbgtz\tt1, fault\n-\t/* Be careful what follows in DS. */\n-\t.endm\n-/*\n- * call skb_copy_bits:\n- * (prototype in linux/filter.h)\n- *\n- * void *bpf_internal_load_pointer_neg_helper(const struct sk_buff *skb,\n- *                                            int k, unsigned int size)\n- *\n- * see above (bpf_slow_path_common) for ABI restrictions\n- */\n-#define bpf_negative_common(SIZE)\t\t\t\t\t\\\n-\tPTR_ADDIU\t$r_sp, $r_sp, -(6 * SZREG);\t\t\t\\\n-\tPTR_LA\t\tt0, bpf_internal_load_pointer_neg_helper;\t\\\n-\tPTR_S\t\t$r_ra, (5 * SZREG)($r_sp);\t\t\t\\\n-\tjalr\t\tt0;\t\t\t\t\t\t\\\n-\t li\t\ta2, SIZE;\t\t\t\t\t\\\n-\tPTR_L\t\t$r_ra, (5 * SZREG)($r_sp);\t\t\t\\\n-\t/* Check return pointer */\t\t\t\t\t\\\n-\tbeqz\t\tv0, fault;\t\t\t\t\t\\\n-\t PTR_ADDIU\t$r_sp, $r_sp, 6 * SZREG;\t\t\t\\\n-\t/* Preserve our pointer */\t\t\t\t\t\\\n-\tmove\t\t$r_s0, v0;\t\t\t\t\t\\\n-\t/* Set return value */\t\t\t\t\t\t\\\n-\tmove\t\t$r_ret, zero;\t\t\t\t\t\\\n-\n-bpf_slow_path_word_neg:\n-\tbpf_is_end_of_data\n-NESTED(sk_load_word_negative, (6 * SZREG), $r_sp)\n-\tbpf_negative_common(4)\n-\tjr\t$r_ra\n-\t lw\t$r_A, 0($r_s0)\n-\tEND(sk_load_word_negative)\n-\n-bpf_slow_path_half_neg:\n-\tbpf_is_end_of_data\n-NESTED(sk_load_half_negative, (6 * SZREG), $r_sp)\n-\tbpf_negative_common(2)\n-\tjr\t$r_ra\n-\t lhu\t$r_A, 0($r_s0)\n-\tEND(sk_load_half_negative)\n-\n-bpf_slow_path_byte_neg:\n-\tbpf_is_end_of_data\n-NESTED(sk_load_byte_negative, (6 * SZREG), $r_sp)\n-\tbpf_negative_common(1)\n-\tjr\t$r_ra\n-\t lbu\t$r_A, 0($r_s0)\n-\tEND(sk_load_byte_negative)\n-\n-fault:\n-\tjr\t$r_ra\n-\t addiu $r_ret, zero, 1\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/071-crypto-arm-chacha-neon-optimize-for-non-block-size-m.patch",
    "content": "From 03662fcd41f4b764857f17b95f9a2a63c24bddd4 Mon Sep 17 00:00:00 2001\nFrom: Ard Biesheuvel <ardb@kernel.org>\nDate: Tue, 3 Nov 2020 17:28:09 +0100\nSubject: [PATCH 1/2] crypto: arm/chacha-neon - optimize for non-block size\n multiples\n\ncommit 86cd97ec4b943af35562a74688bc4e909b32c3d1 upstream.\n\nThe current NEON based ChaCha implementation for ARM is optimized for\nmultiples of 4x the ChaCha block size (64 bytes). This makes sense for\nblock encryption, but given that ChaCha is also often used in the\ncontext of networking, it makes sense to consider arbitrary length\ninputs as well.\n\nFor example, WireGuard typically uses 1420 byte packets, and performing\nChaCha encryption involves 5 invocations of chacha_4block_xor_neon()\nand 3 invocations of chacha_block_xor_neon(), where the last one also\ninvolves a memcpy() using a buffer on the stack to process the final\nchunk of 1420 % 64 == 12 bytes.\n\nLet's optimize for this case as well, by letting chacha_4block_xor_neon()\ndeal with any input size between 64 and 256 bytes, using NEON permutation\ninstructions and overlapping loads and stores. This way, the 140 byte\ntail of a 1420 byte input buffer can simply be processed in one go.\n\nThis results in the following performance improvements for 1420 byte\nblocks, without significant impact on power-of-2 input sizes. (Note\nthat Raspberry Pi is widely used in combination with a 32-bit kernel,\neven though the core is 64-bit capable)\n\n   Cortex-A8  (BeagleBone)       :   7%\n   Cortex-A15 (Calxeda Midway)   :  21%\n   Cortex-A53 (Raspberry Pi 3)   :   3%\n   Cortex-A72 (Raspberry Pi 4)   :  19%\n\nCc: Eric Biggers <ebiggers@google.com>\nCc: \"Jason A . Donenfeld\" <Jason@zx2c4.com>\nSigned-off-by: Ard Biesheuvel <ardb@kernel.org>\nSigned-off-by: Herbert Xu <herbert@gondor.apana.org.au>\nSigned-off-by: Jason A. Donenfeld <Jason@zx2c4.com>\n---\n arch/arm/crypto/chacha-glue.c      | 34 +++++------\n arch/arm/crypto/chacha-neon-core.S | 97 +++++++++++++++++++++++++++---\n 2 files changed, 107 insertions(+), 24 deletions(-)\n\n--- a/arch/arm/crypto/chacha-glue.c\n+++ b/arch/arm/crypto/chacha-glue.c\n@@ -23,7 +23,7 @@\n asmlinkage void chacha_block_xor_neon(const u32 *state, u8 *dst, const u8 *src,\n \t\t\t\t      int nrounds);\n asmlinkage void chacha_4block_xor_neon(const u32 *state, u8 *dst, const u8 *src,\n-\t\t\t\t       int nrounds);\n+\t\t\t\t       int nrounds, unsigned int nbytes);\n asmlinkage void hchacha_block_arm(const u32 *state, u32 *out, int nrounds);\n asmlinkage void hchacha_block_neon(const u32 *state, u32 *out, int nrounds);\n \n@@ -42,24 +42,24 @@ static void chacha_doneon(u32 *state, u8\n {\n \tu8 buf[CHACHA_BLOCK_SIZE];\n \n-\twhile (bytes >= CHACHA_BLOCK_SIZE * 4) {\n-\t\tchacha_4block_xor_neon(state, dst, src, nrounds);\n-\t\tbytes -= CHACHA_BLOCK_SIZE * 4;\n-\t\tsrc += CHACHA_BLOCK_SIZE * 4;\n-\t\tdst += CHACHA_BLOCK_SIZE * 4;\n-\t\tstate[12] += 4;\n-\t}\n-\twhile (bytes >= CHACHA_BLOCK_SIZE) {\n-\t\tchacha_block_xor_neon(state, dst, src, nrounds);\n-\t\tbytes -= CHACHA_BLOCK_SIZE;\n-\t\tsrc += CHACHA_BLOCK_SIZE;\n-\t\tdst += CHACHA_BLOCK_SIZE;\n-\t\tstate[12]++;\n+\twhile (bytes > CHACHA_BLOCK_SIZE) {\n+\t\tunsigned int l = min(bytes, CHACHA_BLOCK_SIZE * 4U);\n+\n+\t\tchacha_4block_xor_neon(state, dst, src, nrounds, l);\n+\t\tbytes -= l;\n+\t\tsrc += l;\n+\t\tdst += l;\n+\t\tstate[12] += DIV_ROUND_UP(l, CHACHA_BLOCK_SIZE);\n \t}\n \tif (bytes) {\n-\t\tmemcpy(buf, src, bytes);\n-\t\tchacha_block_xor_neon(state, buf, buf, nrounds);\n-\t\tmemcpy(dst, buf, bytes);\n+\t\tconst u8 *s = src;\n+\t\tu8 *d = dst;\n+\n+\t\tif (bytes != CHACHA_BLOCK_SIZE)\n+\t\t\ts = d = memcpy(buf, src, bytes);\n+\t\tchacha_block_xor_neon(state, d, s, nrounds);\n+\t\tif (d != dst)\n+\t\t\tmemcpy(dst, buf, bytes);\n \t}\n }\n \n--- a/arch/arm/crypto/chacha-neon-core.S\n+++ b/arch/arm/crypto/chacha-neon-core.S\n@@ -47,6 +47,7 @@\n   */\n \n #include <linux/linkage.h>\n+#include <asm/cache.h>\n \n \t.text\n \t.fpu\t\tneon\n@@ -205,7 +206,7 @@ ENDPROC(hchacha_block_neon)\n \n \t.align\t\t5\n ENTRY(chacha_4block_xor_neon)\n-\tpush\t\t{r4-r5}\n+\tpush\t\t{r4, lr}\n \tmov\t\tr4, sp\t\t\t// preserve the stack pointer\n \tsub\t\tip, sp, #0x20\t\t// allocate a 32 byte buffer\n \tbic\t\tip, ip, #0x1f\t\t// aligned to 32 bytes\n@@ -229,10 +230,10 @@ ENTRY(chacha_4block_xor_neon)\n \tvld1.32\t\t{q0-q1}, [r0]\n \tvld1.32\t\t{q2-q3}, [ip]\n \n-\tadr\t\tr5, .Lctrinc\n+\tadr\t\tlr, .Lctrinc\n \tvdup.32\t\tq15, d7[1]\n \tvdup.32\t\tq14, d7[0]\n-\tvld1.32\t\t{q4}, [r5, :128]\n+\tvld1.32\t\t{q4}, [lr, :128]\n \tvdup.32\t\tq13, d6[1]\n \tvdup.32\t\tq12, d6[0]\n \tvdup.32\t\tq11, d5[1]\n@@ -455,7 +456,7 @@ ENTRY(chacha_4block_xor_neon)\n \n \t// Re-interleave the words in the first two rows of each block (x0..7).\n \t// Also add the counter values 0-3 to x12[0-3].\n-\t  vld1.32\t{q8}, [r5, :128]\t// load counter values 0-3\n+\t  vld1.32\t{q8}, [lr, :128]\t// load counter values 0-3\n \tvzip.32\t\tq0, q1\t\t\t// => (0 1 0 1) (0 1 0 1)\n \tvzip.32\t\tq2, q3\t\t\t// => (2 3 2 3) (2 3 2 3)\n \tvzip.32\t\tq4, q5\t\t\t// => (4 5 4 5) (4 5 4 5)\n@@ -493,6 +494,8 @@ ENTRY(chacha_4block_xor_neon)\n \n \t// Re-interleave the words in the last two rows of each block (x8..15).\n \tvld1.32\t\t{q8-q9}, [sp, :256]\n+\t  mov\t\tsp, r4\t\t// restore original stack pointer\n+\t  ldr\t\tr4, [r4, #8]\t// load number of bytes\n \tvzip.32\t\tq12, q13\t// => (12 13 12 13) (12 13 12 13)\n \tvzip.32\t\tq14, q15\t// => (14 15 14 15) (14 15 14 15)\n \tvzip.32\t\tq8, q9\t\t// => (8 9 8 9) (8 9 8 9)\n@@ -520,41 +523,121 @@ ENTRY(chacha_4block_xor_neon)\n \t// XOR the rest of the data with the keystream\n \n \tvld1.8\t\t{q0-q1}, [r2]!\n+\tsubs\t\tr4, r4, #96\n \tveor\t\tq0, q0, q8\n \tveor\t\tq1, q1, q12\n+\tble\t\t.Lle96\n \tvst1.8\t\t{q0-q1}, [r1]!\n \n \tvld1.8\t\t{q0-q1}, [r2]!\n+\tsubs\t\tr4, r4, #32\n \tveor\t\tq0, q0, q2\n \tveor\t\tq1, q1, q6\n+\tble\t\t.Lle128\n \tvst1.8\t\t{q0-q1}, [r1]!\n \n \tvld1.8\t\t{q0-q1}, [r2]!\n+\tsubs\t\tr4, r4, #32\n \tveor\t\tq0, q0, q10\n \tveor\t\tq1, q1, q14\n+\tble\t\t.Lle160\n \tvst1.8\t\t{q0-q1}, [r1]!\n \n \tvld1.8\t\t{q0-q1}, [r2]!\n+\tsubs\t\tr4, r4, #32\n \tveor\t\tq0, q0, q4\n \tveor\t\tq1, q1, q5\n+\tble\t\t.Lle192\n \tvst1.8\t\t{q0-q1}, [r1]!\n \n \tvld1.8\t\t{q0-q1}, [r2]!\n+\tsubs\t\tr4, r4, #32\n \tveor\t\tq0, q0, q9\n \tveor\t\tq1, q1, q13\n+\tble\t\t.Lle224\n \tvst1.8\t\t{q0-q1}, [r1]!\n \n \tvld1.8\t\t{q0-q1}, [r2]!\n+\tsubs\t\tr4, r4, #32\n \tveor\t\tq0, q0, q3\n \tveor\t\tq1, q1, q7\n+\tblt\t\t.Llt256\n+.Lout:\n \tvst1.8\t\t{q0-q1}, [r1]!\n \n \tvld1.8\t\t{q0-q1}, [r2]\n-\t  mov\t\tsp, r4\t\t// restore original stack pointer\n \tveor\t\tq0, q0, q11\n \tveor\t\tq1, q1, q15\n \tvst1.8\t\t{q0-q1}, [r1]\n \n-\tpop\t\t{r4-r5}\n-\tbx\t\tlr\n+\tpop\t\t{r4, pc}\n+\n+.Lle192:\n+\tvmov\t\tq4, q9\n+\tvmov\t\tq5, q13\n+\n+.Lle160:\n+\t// nothing to do\n+\n+.Lfinalblock:\n+\t// Process the final block if processing less than 4 full blocks.\n+\t// Entered with 32 bytes of ChaCha cipher stream in q4-q5, and the\n+\t// previous 32 byte output block that still needs to be written at\n+\t// [r1] in q0-q1.\n+\tbeq\t\t.Lfullblock\n+\n+.Lpartialblock:\n+\tadr\t\tlr, .Lpermute + 32\n+\tadd\t\tr2, r2, r4\n+\tadd\t\tlr, lr, r4\n+\tadd\t\tr4, r4, r1\n+\n+\tvld1.8\t\t{q2-q3}, [lr]\n+\tvld1.8\t\t{q6-q7}, [r2]\n+\n+\tadd\t\tr4, r4, #32\n+\n+\tvtbl.8\t\td4, {q4-q5}, d4\n+\tvtbl.8\t\td5, {q4-q5}, d5\n+\tvtbl.8\t\td6, {q4-q5}, d6\n+\tvtbl.8\t\td7, {q4-q5}, d7\n+\n+\tveor\t\tq6, q6, q2\n+\tveor\t\tq7, q7, q3\n+\n+\tvst1.8\t\t{q6-q7}, [r4]\t// overlapping stores\n+\tvst1.8\t\t{q0-q1}, [r1]\n+\tpop\t\t{r4, pc}\n+\n+.Lfullblock:\n+\tvmov\t\tq11, q4\n+\tvmov\t\tq15, q5\n+\tb\t\t.Lout\n+.Lle96:\n+\tvmov\t\tq4, q2\n+\tvmov\t\tq5, q6\n+\tb\t\t.Lfinalblock\n+.Lle128:\n+\tvmov\t\tq4, q10\n+\tvmov\t\tq5, q14\n+\tb\t\t.Lfinalblock\n+.Lle224:\n+\tvmov\t\tq4, q3\n+\tvmov\t\tq5, q7\n+\tb\t\t.Lfinalblock\n+.Llt256:\n+\tvmov\t\tq4, q11\n+\tvmov\t\tq5, q15\n+\tb\t\t.Lpartialblock\n ENDPROC(chacha_4block_xor_neon)\n+\n+\t.align\t\tL1_CACHE_SHIFT\n+.Lpermute:\n+\t.byte\t\t0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07\n+\t.byte\t\t0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f\n+\t.byte\t\t0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17\n+\t.byte\t\t0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f\n+\t.byte\t\t0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07\n+\t.byte\t\t0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f\n+\t.byte\t\t0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17\n+\t.byte\t\t0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/072-crypto-arm-chacha-neon-add-missing-counter-increment.patch",
    "content": "From 7f63462faf9eab69132bea9abd48c2c05a93145b Mon Sep 17 00:00:00 2001\nFrom: Ard Biesheuvel <ardb@kernel.org>\nDate: Sun, 13 Dec 2020 15:39:29 +0100\nSubject: [PATCH 2/2] crypto: arm/chacha-neon - add missing counter increment\n\ncommit fd16931a2f518a32753920ff20895e5cf04c8ff1 upstream.\n\nCommit 86cd97ec4b943af3 (\"crypto: arm/chacha-neon - optimize for non-block\nsize multiples\") refactored the chacha block handling in the glue code in\na way that may result in the counter increment to be omitted when calling\nchacha_block_xor_neon() to process a full block. This violates the skcipher\nAPI, which requires that the output IV is suitable for handling more input\nas long as the preceding input has been presented in round multiples of the\nblock size. Also, the same code is exposed via the chacha library interface\nwhose callers may actually rely on this increment to occur even for final\nblocks that are smaller than the chacha block size.\n\nSo increment the counter after calling chacha_block_xor_neon().\n\nFixes: 86cd97ec4b943af3 (\"crypto: arm/chacha-neon - optimize for non-block size multiples\")\nReported-by: Eric Biggers <ebiggers@kernel.org>\nSigned-off-by: Ard Biesheuvel <ardb@kernel.org>\nSigned-off-by: Herbert Xu <herbert@gondor.apana.org.au>\nSigned-off-by: Jason A. Donenfeld <Jason@zx2c4.com>\n---\n arch/arm/crypto/chacha-glue.c | 1 +\n 1 file changed, 1 insertion(+)\n\n--- a/arch/arm/crypto/chacha-glue.c\n+++ b/arch/arm/crypto/chacha-glue.c\n@@ -60,6 +60,7 @@ static void chacha_doneon(u32 *state, u8\n \t\tchacha_block_xor_neon(state, d, s, nrounds);\n \t\tif (d != dst)\n \t\t\tmemcpy(dst, buf, bytes);\n+\t\tstate[12]++;\n \t}\n }\n \n"
  },
  {
    "path": "target/linux/generic/backport-5.10/080-wireguard-peer-put-frequently-used-members-above-cac.patch",
    "content": "From a13827e9091c07e25cdeec9a402d74a27e2a1111 Mon Sep 17 00:00:00 2001\nFrom: \"Jason A. Donenfeld\" <Jason@zx2c4.com>\nDate: Mon, 22 Feb 2021 17:25:46 +0100\nSubject: [PATCH] wireguard: peer: put frequently used members above cache\n lines\n\ncommit 5a0598695634a6bb4126818902dd9140cd9df8b6 upstream.\n\nThe is_dead boolean is checked for every single packet, while the\ninternal_id member is used basically only for pr_debug messages. So it\nmakes sense to hoist up is_dead into some space formerly unused by a\nstruct hole, while demoting internal_api to below the lowest struct\ncache line.\n\nSigned-off-by: Jason A. Donenfeld <Jason@zx2c4.com>\nSigned-off-by: Jakub Kicinski <kuba@kernel.org>\nSigned-off-by: Jason A. Donenfeld <Jason@zx2c4.com>\n---\n drivers/net/wireguard/peer.h | 4 ++--\n 1 file changed, 2 insertions(+), 2 deletions(-)\n\n--- a/drivers/net/wireguard/peer.h\n+++ b/drivers/net/wireguard/peer.h\n@@ -39,6 +39,7 @@ struct wg_peer {\n \tstruct prev_queue tx_queue, rx_queue;\n \tstruct sk_buff_head staged_packet_queue;\n \tint serial_work_cpu;\n+\tbool is_dead;\n \tstruct noise_keypairs keypairs;\n \tstruct endpoint endpoint;\n \tstruct dst_cache endpoint_cache;\n@@ -61,9 +62,8 @@ struct wg_peer {\n \tstruct rcu_head rcu;\n \tstruct list_head peer_list;\n \tstruct list_head allowedips_list;\n-\tu64 internal_id;\n \tstruct napi_struct napi;\n-\tbool is_dead;\n+\tu64 internal_id;\n };\n \n struct wg_peer *wg_peer_create(struct wg_device *wg,\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/081-net-next-regmap-allow-to-define-reg_update_bits-for-no-bus.patch",
    "content": "From 02d6fdecb9c38de19065f6bed8d5214556fd061d Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Thu, 4 Nov 2021 16:00:40 +0100\nSubject: regmap: allow to define reg_update_bits for no bus configuration\n\nSome device requires a special handling for reg_update_bits and can't use\nthe normal regmap read write logic. An example is when locking is\nhandled by the device and rmw operations requires to do atomic operations.\nAllow to declare a dedicated function in regmap_config for\nreg_update_bits in no bus configuration.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nLink: https://lore.kernel.org/r/20211104150040.1260-1-ansuelsmth@gmail.com\nSigned-off-by: Mark Brown <broonie@kernel.org>\n---\n drivers/base/regmap/regmap.c | 1 +\n include/linux/regmap.h       | 7 +++++++\n 2 files changed, 8 insertions(+)\n\n--- a/drivers/base/regmap/regmap.c\n+++ b/drivers/base/regmap/regmap.c\n@@ -842,6 +842,7 @@ struct regmap *__regmap_init(struct devi\n \tif (!bus) {\n \t\tmap->reg_read  = config->reg_read;\n \t\tmap->reg_write = config->reg_write;\n+\t\tmap->reg_update_bits = config->reg_update_bits;\n \n \t\tmap->defer_caching = false;\n \t\tgoto skip_format_initialization;\n--- a/include/linux/regmap.h\n+++ b/include/linux/regmap.h\n@@ -289,6 +289,11 @@ typedef void (*regmap_unlock)(void *);\n  *\t\t  read operation on a bus such as SPI, I2C, etc. Most of the\n  *\t\t  devices do not need this.\n  * @reg_write:\t  Same as above for writing.\n+ * @reg_update_bits: Optional callback that if filled will be used to perform\n+ *\t\t     all the update_bits(rmw) operation. Should only be provided\n+ *\t\t     if the function require special handling with lock and reg\n+ *\t\t     handling and the operation cannot be represented as a simple\n+ *\t\t     update_bits operation on a bus such as SPI, I2C, etc.\n  * @fast_io:\t  Register IO is fast. Use a spinlock instead of a mutex\n  *\t     \t  to perform locking. This field is ignored if custom lock/unlock\n  *\t     \t  functions are used (see fields lock/unlock of struct regmap_config).\n@@ -366,6 +371,8 @@ struct regmap_config {\n \n \tint (*reg_read)(void *context, unsigned int reg, unsigned int *val);\n \tint (*reg_write)(void *context, unsigned int reg, unsigned int val);\n+\tint (*reg_update_bits)(void *context, unsigned int reg,\n+\t\t\t       unsigned int mask, unsigned int val);\n \n \tbool fast_io;\n \n"
  },
  {
    "path": "target/linux/generic/backport-5.10/103-v5.13-MIPS-select-CPU_MIPS64-for-remaining-MIPS64-CPUs.patch",
    "content": "From 6523061868212473f63812a0c477a161742bed42 Mon Sep 17 00:00:00 2001\nFrom: \"Jason A. Donenfeld\" <Jason@zx2c4.com>\nDate: Sat, 27 Feb 2021 13:20:24 +0100\nSubject: [PATCH] MIPS: select CPU_MIPS64 for remaining MIPS64 CPUs\n\nThe CPU_MIPS64 and CPU_MIPS32 variables are supposed to be able to\ndistinguish broadly between 64-bit and 32-bit MIPS CPUs. However, they\nweren't selected by the specialty CPUs, Octeon and Loongson, which meant\nit was possible to hit a weird state of:\n\n    MIPS=y, CONFIG_64BIT=y, CPU_MIPS64=n\n\nThis commit rectifies the issue by having CPU_MIPS64 be selected when\nthe missing Octeon or Loongson models are selected.\n\nCc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>\nCc: Ralf Baechle <ralf@linux-mips.org>\nCc: George Cherian <gcherian@marvell.com>\nCc: Huacai Chen <chenhuacai@kernel.org>\nCc: Jiaxun Yang <jiaxun.yang@flygoat.com>\nSigned-off-by: Jason A. Donenfeld <Jason@zx2c4.com>\n---\n arch/mips/Kconfig | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/arch/mips/Kconfig\n+++ b/arch/mips/Kconfig\n@@ -2088,7 +2088,7 @@ config CPU_MIPS32\n config CPU_MIPS64\n \tbool\n \tdefault y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R5 || \\\n-\t\t     CPU_MIPS64_R6\n+\t\t     CPU_MIPS64_R6 || CPU_LOONGSON64 || CPU_CAVIUM_OCTEON\n \n #\n # These indicate the revision of the architecture\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/311-v5.11-MIPS-zboot-put-appended-dtb-into-a-section.patch",
    "content": "From 7d1531c81c0fb4c93bea8dc316043ad0e4d0c270 Mon Sep 17 00:00:00 2001\nFrom: Chuanhong Guo <gch981213@gmail.com>\nDate: Sun, 25 Oct 2020 23:19:40 +0800\nSubject: [PATCH] MIPS: zboot: put appended dtb into a section\n\nThis will make a separated section for dtb appear in ELF, and we can\nthen use objcopy to patch a dtb into vmlinuz when RAW_APPENDED_DTB\nis set in kernel config.\n\ncommand to patch a dtb:\nobjcopy --set-section-flags=.appended_dtb=alloc,contents \\\n        --update-section=.appended_dtb=<target>.dtb vmlinuz vmlinuz-dtb\n\nSigned-off-by: Chuanhong Guo <gch981213@gmail.com>\n---\n arch/mips/boot/compressed/ld.script | 9 ++++++---\n 1 file changed, 6 insertions(+), 3 deletions(-)\n\n--- a/arch/mips/boot/compressed/ld.script\n+++ b/arch/mips/boot/compressed/ld.script\n@@ -31,9 +31,12 @@ SECTIONS\n \t\tCONSTRUCTORS\n \t\t. = ALIGN(16);\n \t}\n-\t__appended_dtb = .;\n-\t/* leave space for appended DTB */\n-\t. += 0x100000;\n+\n+\t.appended_dtb : {\n+\t\t__appended_dtb = .;\n+\t\t/* leave space for appended DTB */\n+\t\t. += 0x100000;\n+\t}\n \n \t_edata = .;\n \t/* End of data section */\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/343-netfilter-nft_flow_offload-handle-netdevice-events-f.patch",
    "content": "From: Pablo Neira Ayuso <pablo@netfilter.org>\nDate: Thu, 25 Jan 2018 12:58:55 +0100\nSubject: [PATCH] netfilter: nft_flow_offload: handle netdevice events from\n nf_flow_table\n\nMove the code that deals with device events to the core.\n\nSigned-off-by: Pablo Neira Ayuso <pablo@netfilter.org>\n---\n\n--- a/net/netfilter/nf_flow_table_core.c\n+++ b/net/netfilter/nf_flow_table_core.c\n@@ -576,13 +576,41 @@ void nf_flow_table_free(struct nf_flowta\n }\n EXPORT_SYMBOL_GPL(nf_flow_table_free);\n \n+static int nf_flow_table_netdev_event(struct notifier_block *this,\n+\t\t\t\t      unsigned long event, void *ptr)\n+{\n+\tstruct net_device *dev = netdev_notifier_info_to_dev(ptr);\n+\n+\tif (event != NETDEV_DOWN)\n+\t\treturn NOTIFY_DONE;\n+\n+\tnf_flow_table_cleanup(dev);\n+\n+\treturn NOTIFY_DONE;\n+}\n+\n+static struct notifier_block flow_offload_netdev_notifier = {\n+\t.notifier_call\t= nf_flow_table_netdev_event,\n+};\n+\n static int __init nf_flow_table_module_init(void)\n {\n-\treturn nf_flow_table_offload_init();\n+\tint ret;\n+\n+\tret = nf_flow_table_offload_init();\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = register_netdevice_notifier(&flow_offload_netdev_notifier);\n+\tif (ret)\n+\t\tnf_flow_table_offload_exit();\n+\n+\treturn ret;\n }\n \n static void __exit nf_flow_table_module_exit(void)\n {\n+\tunregister_netdevice_notifier(&flow_offload_netdev_notifier);\n \tnf_flow_table_offload_exit();\n }\n \n--- a/net/netfilter/nft_flow_offload.c\n+++ b/net/netfilter/nft_flow_offload.c\n@@ -237,47 +237,14 @@ static struct nft_expr_type nft_flow_off\n \t.owner\t\t= THIS_MODULE,\n };\n \n-static int flow_offload_netdev_event(struct notifier_block *this,\n-\t\t\t\t     unsigned long event, void *ptr)\n-{\n-\tstruct net_device *dev = netdev_notifier_info_to_dev(ptr);\n-\n-\tif (event != NETDEV_DOWN)\n-\t\treturn NOTIFY_DONE;\n-\n-\tnf_flow_table_cleanup(dev);\n-\n-\treturn NOTIFY_DONE;\n-}\n-\n-static struct notifier_block flow_offload_netdev_notifier = {\n-\t.notifier_call\t= flow_offload_netdev_event,\n-};\n-\n static int __init nft_flow_offload_module_init(void)\n {\n-\tint err;\n-\n-\terr = register_netdevice_notifier(&flow_offload_netdev_notifier);\n-\tif (err)\n-\t\tgoto err;\n-\n-\terr = nft_register_expr(&nft_flow_offload_type);\n-\tif (err < 0)\n-\t\tgoto register_expr;\n-\n-\treturn 0;\n-\n-register_expr:\n-\tunregister_netdevice_notifier(&flow_offload_netdev_notifier);\n-err:\n-\treturn err;\n+\treturn nft_register_expr(&nft_flow_offload_type);\n }\n \n static void __exit nft_flow_offload_module_exit(void)\n {\n \tnft_unregister_expr(&nft_flow_offload_type);\n-\tunregister_netdevice_notifier(&flow_offload_netdev_notifier);\n }\n \n module_init(nft_flow_offload_module_init);\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/401-v5.11-dt-bindings-mtd-convert-fixed-partitions-to-the-json.patch",
    "content": "From 04e9ab75267489224364fa510a88ada83e11c325 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Thu, 10 Dec 2020 18:23:52 +0100\nSubject: [PATCH] dt-bindings: mtd: convert \"fixed-partitions\" to the\n json-schema\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nThis standardizes its documentation, allows validating with Makefile\nchecks and helps writing DTS files.\n\nNoticeable changes:\n1. Dropped \"Partitions can be represented by sub-nodes of a flash\n   device.\" as we also support subpartitions (don't have to be part of\n   flash device node)\n2. Dropped \"to Linux\" as bindings are meant to be os agnostic.\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nLink: https://lore.kernel.org/r/20201210172352.31632-1-zajec5@gmail.com\nSigned-off-by: Rob Herring <robh@kernel.org>\n---\n .../devicetree/bindings/mtd/partition.txt     | 131 +--------------\n .../mtd/partitions/fixed-partitions.yaml      | 152 ++++++++++++++++++\n 2 files changed, 154 insertions(+), 129 deletions(-)\n create mode 100644 Documentation/devicetree/bindings/mtd/partitions/fixed-partitions.yaml\n\n--- a/Documentation/devicetree/bindings/mtd/partition.txt\n+++ b/Documentation/devicetree/bindings/mtd/partition.txt\n@@ -24,137 +24,10 @@ another partitioning method.\n Available bindings are listed in the \"partitions\" subdirectory.\n \n \n-Fixed Partitions\n-================\n-\n-Partitions can be represented by sub-nodes of a flash device. This can be used\n-on platforms which have strong conventions about which portions of a flash are\n-used for what purposes, but which don't use an on-flash partition table such\n-as RedBoot.\n-\n-The partition table should be a subnode of the flash node and should be named\n-'partitions'. This node should have the following property:\n-- compatible : (required) must be \"fixed-partitions\"\n-Partitions are then defined in subnodes of the partitions node.\n+Deprecated: partitions defined in flash node\n+============================================\n \n For backwards compatibility partitions as direct subnodes of the flash device are\n supported. This use is discouraged.\n NOTE: also for backwards compatibility, direct subnodes that have a compatible\n string are not considered partitions, as they may be used for other bindings.\n-\n-#address-cells & #size-cells must both be present in the partitions subnode of the\n-flash device. There are two valid values for both:\n-<1>: for partitions that require a single 32-bit cell to represent their\n-     size/address (aka the value is below 4 GiB)\n-<2>: for partitions that require two 32-bit cells to represent their\n-     size/address (aka the value is 4 GiB or greater).\n-\n-Required properties:\n-- reg : The partition's offset and size within the flash\n-\n-Optional properties:\n-- label : The label / name for this partition.  If omitted, the label is taken\n-  from the node name (excluding the unit address).\n-- read-only : This parameter, if present, is a hint to Linux that this\n-  partition should only be mounted read-only. This is usually used for flash\n-  partitions containing early-boot firmware images or data which should not be\n-  clobbered.\n-- lock : Do not unlock the partition at initialization time (not supported on\n-  all devices)\n-- slc-mode: This parameter, if present, allows one to emulate SLC mode on a\n-  partition attached to an MLC NAND thus making this partition immune to\n-  paired-pages corruptions\n-\n-Examples:\n-\n-\n-flash@0 {\n-\tpartitions {\n-\t\tcompatible = \"fixed-partitions\";\n-\t\t#address-cells = <1>;\n-\t\t#size-cells = <1>;\n-\n-\t\tpartition@0 {\n-\t\t\tlabel = \"u-boot\";\n-\t\t\treg = <0x0000000 0x100000>;\n-\t\t\tread-only;\n-\t\t};\n-\n-\t\tuimage@100000 {\n-\t\t\treg = <0x0100000 0x200000>;\n-\t\t};\n-\t};\n-};\n-\n-flash@1 {\n-\tpartitions {\n-\t\tcompatible = \"fixed-partitions\";\n-\t\t#address-cells = <1>;\n-\t\t#size-cells = <2>;\n-\n-\t\t/* a 4 GiB partition */\n-\t\tpartition@0 {\n-\t\t\tlabel = \"filesystem\";\n-\t\t\treg = <0x00000000 0x1 0x00000000>;\n-\t\t};\n-\t};\n-};\n-\n-flash@2 {\n-\tpartitions {\n-\t\tcompatible = \"fixed-partitions\";\n-\t\t#address-cells = <2>;\n-\t\t#size-cells = <2>;\n-\n-\t\t/* an 8 GiB partition */\n-\t\tpartition@0 {\n-\t\t\tlabel = \"filesystem #1\";\n-\t\t\treg = <0x0 0x00000000 0x2 0x00000000>;\n-\t\t};\n-\n-\t\t/* a 4 GiB partition */\n-\t\tpartition@200000000 {\n-\t\t\tlabel = \"filesystem #2\";\n-\t\t\treg = <0x2 0x00000000 0x1 0x00000000>;\n-\t\t};\n-\t};\n-};\n-\n-flash@3 {\n-\tpartitions {\n-\t\tcompatible = \"fixed-partitions\";\n-\t\t#address-cells = <1>;\n-\t\t#size-cells = <1>;\n-\n-\t\tpartition@0 {\n-\t\t\tlabel = \"bootloader\";\n-\t\t\treg = <0x000000 0x100000>;\n-\t\t\tread-only;\n-\t\t};\n-\n-\t\tfirmware@100000 {\n-\t\t\tlabel = \"firmware\";\n-\t\t\treg = <0x100000 0xe00000>;\n-\t\t\tcompatible = \"brcm,trx\";\n-\t\t};\n-\n-\t\tcalibration@f00000 {\n-\t\t\tlabel = \"calibration\";\n-\t\t\treg = <0xf00000 0x100000>;\n-\t\t\tcompatible = \"fixed-partitions\";\n-\t\t\tranges = <0 0xf00000 0x100000>;\n-\t\t\t#address-cells = <1>;\n-\t\t\t#size-cells = <1>;\n-\n-\t\t\tpartition@0 {\n-\t\t\t\tlabel = \"wifi0\";\n-\t\t\t\treg = <0x000000 0x080000>;\n-\t\t\t};\n-\n-\t\t\tpartition@80000 {\n-\t\t\t\tlabel = \"wifi1\";\n-\t\t\t\treg = <0x080000 0x080000>;\n-\t\t\t};\n-\t\t};\n-\t};\n-};\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/mtd/partitions/fixed-partitions.yaml\n@@ -0,0 +1,152 @@\n+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause\n+%YAML 1.2\n+---\n+$id: http://devicetree.org/schemas/mtd/partitions/fixed-partitions.yaml#\n+$schema: http://devicetree.org/meta-schemas/core.yaml#\n+\n+title: Fixed partitions\n+\n+description: |\n+  This binding can be used on platforms which have strong conventions about\n+  which portions of a flash are used for what purposes, but which don't use an\n+  on-flash partition table such as RedBoot.\n+\n+  The partition table should be a node named \"partitions\". Partitions are then\n+  defined as subnodes.\n+\n+maintainers:\n+  - Rafał Miłecki <rafal@milecki.pl>\n+\n+properties:\n+  compatible:\n+    const: fixed-partitions\n+\n+  \"#address-cells\": true\n+\n+  \"#size-cells\": true\n+\n+patternProperties:\n+  \"@[0-9a-f]+$\":\n+    description: node describing a single flash partition\n+    type: object\n+\n+    properties:\n+      reg:\n+        description: partition's offset and size within the flash\n+        maxItems: 1\n+\n+      label:\n+        description: The label / name for this partition. If omitted, the label\n+          is taken from the node name (excluding the unit address).\n+\n+      read-only:\n+        description: This parameter, if present, is a hint that this partition\n+          should only be mounted read-only. This is usually used for flash\n+          partitions containing early-boot firmware images or data which should\n+          not be clobbered.\n+        type: boolean\n+\n+      lock:\n+        description: Do not unlock the partition at initialization time (not\n+          supported on all devices)\n+        type: boolean\n+\n+      slc-mode:\n+        description: This parameter, if present, allows one to emulate SLC mode\n+          on a partition attached to an MLC NAND thus making this partition\n+          immune to paired-pages corruptions\n+        type: boolean\n+\n+    required:\n+      - reg\n+\n+required:\n+  - \"#address-cells\"\n+  - \"#size-cells\"\n+\n+additionalProperties: true\n+\n+examples:\n+  - |\n+    partitions {\n+        compatible = \"fixed-partitions\";\n+        #address-cells = <1>;\n+        #size-cells = <1>;\n+\n+        partition@0 {\n+            label = \"u-boot\";\n+            reg = <0x0000000 0x100000>;\n+            read-only;\n+        };\n+\n+        uimage@100000 {\n+            reg = <0x0100000 0x200000>;\n+        };\n+    };\n+  - |\n+    partitions {\n+        compatible = \"fixed-partitions\";\n+        #address-cells = <1>;\n+        #size-cells = <2>;\n+\n+        /* a 4 GiB partition */\n+        partition@0 {\n+            label = \"filesystem\";\n+            reg = <0x00000000 0x1 0x00000000>;\n+        };\n+    };\n+  - |\n+    partitions {\n+        compatible = \"fixed-partitions\";\n+        #address-cells = <2>;\n+        #size-cells = <2>;\n+\n+        /* an 8 GiB partition */\n+        partition@0 {\n+            label = \"filesystem #1\";\n+            reg = <0x0 0x00000000 0x2 0x00000000>;\n+        };\n+\n+        /* a 4 GiB partition */\n+        partition@200000000 {\n+            label = \"filesystem #2\";\n+            reg = <0x2 0x00000000 0x1 0x00000000>;\n+        };\n+    };\n+  - |\n+    partitions {\n+        compatible = \"fixed-partitions\";\n+        #address-cells = <1>;\n+        #size-cells = <1>;\n+\n+        partition@0 {\n+            label = \"bootloader\";\n+            reg = <0x000000 0x100000>;\n+            read-only;\n+        };\n+\n+        firmware@100000 {\n+            compatible = \"brcm,trx\";\n+            label = \"firmware\";\n+            reg = <0x100000 0xe00000>;\n+        };\n+\n+        calibration@f00000 {\n+            compatible = \"fixed-partitions\";\n+            label = \"calibration\";\n+            reg = <0xf00000 0x100000>;\n+            ranges = <0 0xf00000 0x100000>;\n+            #address-cells = <1>;\n+            #size-cells = <1>;\n+\n+            partition@0 {\n+                label = \"wifi0\";\n+                reg = <0x000000 0x080000>;\n+            };\n+\n+            partition@80000 {\n+                label = \"wifi1\";\n+                reg = <0x080000 0x080000>;\n+            };\n+        };\n+    };\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/402-v5.12-0001-dt-bindings-mtd-move-partition-binding-to-its-own-fi.patch",
    "content": "From 6418522022c706fd867b00b2571edba48b8fa8c7 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Thu, 11 Feb 2021 23:04:25 +0100\nSubject: [PATCH] dt-bindings: mtd: move partition binding to its own file\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nSingle partition binding is quite common and may be:\n1. Used by multiple parsers\n2. Extended for more specific cases\n\nMove it to separated file to avoid code duplication.\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nReviewed-by: Rob Herring <robh@kernel.org>\nSigned-off-by: Richard Weinberger <richard@nod.at>\n---\n .../mtd/partitions/fixed-partitions.yaml      | 33 +------------\n .../bindings/mtd/partitions/partition.yaml    | 47 +++++++++++++++++++\n 2 files changed, 48 insertions(+), 32 deletions(-)\n create mode 100644 Documentation/devicetree/bindings/mtd/partitions/partition.yaml\n\n--- a/Documentation/devicetree/bindings/mtd/partitions/fixed-partitions.yaml\n+++ b/Documentation/devicetree/bindings/mtd/partitions/fixed-partitions.yaml\n@@ -27,38 +27,7 @@ properties:\n \n patternProperties:\n   \"@[0-9a-f]+$\":\n-    description: node describing a single flash partition\n-    type: object\n-\n-    properties:\n-      reg:\n-        description: partition's offset and size within the flash\n-        maxItems: 1\n-\n-      label:\n-        description: The label / name for this partition. If omitted, the label\n-          is taken from the node name (excluding the unit address).\n-\n-      read-only:\n-        description: This parameter, if present, is a hint that this partition\n-          should only be mounted read-only. This is usually used for flash\n-          partitions containing early-boot firmware images or data which should\n-          not be clobbered.\n-        type: boolean\n-\n-      lock:\n-        description: Do not unlock the partition at initialization time (not\n-          supported on all devices)\n-        type: boolean\n-\n-      slc-mode:\n-        description: This parameter, if present, allows one to emulate SLC mode\n-          on a partition attached to an MLC NAND thus making this partition\n-          immune to paired-pages corruptions\n-        type: boolean\n-\n-    required:\n-      - reg\n+    $ref: \"partition.yaml#\"\n \n required:\n   - \"#address-cells\"\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/mtd/partitions/partition.yaml\n@@ -0,0 +1,47 @@\n+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause\n+%YAML 1.2\n+---\n+$id: http://devicetree.org/schemas/mtd/partitions/partition.yaml#\n+$schema: http://devicetree.org/meta-schemas/core.yaml#\n+\n+title: Partition\n+\n+description: |\n+  This binding describes a single flash partition. Each partition must have its\n+  relative offset and size specified. Depending on partition function extra\n+  properties can be used.\n+\n+maintainers:\n+  - Rafał Miłecki <rafal@milecki.pl>\n+\n+properties:\n+  reg:\n+    description: partition's offset and size within the flash\n+    maxItems: 1\n+\n+  label:\n+    description: The label / name for this partition. If omitted, the label\n+      is taken from the node name (excluding the unit address).\n+\n+  read-only:\n+    description: This parameter, if present, is a hint that this partition\n+      should only be mounted read-only. This is usually used for flash\n+      partitions containing early-boot firmware images or data which should\n+      not be clobbered.\n+    type: boolean\n+\n+  lock:\n+    description: Do not unlock the partition at initialization time (not\n+      supported on all devices)\n+    type: boolean\n+\n+  slc-mode:\n+    description: This parameter, if present, allows one to emulate SLC mode\n+      on a partition attached to an MLC NAND thus making this partition\n+      immune to paired-pages corruptions\n+    type: boolean\n+\n+required:\n+  - reg\n+\n+additionalProperties: true\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/402-v5.12-0002-dt-bindings-mtd-add-binding-for-BCM4908-partitions.patch",
    "content": "From 6e9dff6fe3fbc452f16566e4a7e293b0decefdba Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Thu, 11 Feb 2021 23:04:26 +0100\nSubject: [PATCH] dt-bindings: mtd: add binding for BCM4908 partitions\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nBCM4908 uses fixed partitions layout but function of some partitions may\nvary. Some devices use multiple firmware partitions and those partitions\nshould be marked to let system discover their purpose.\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nSigned-off-by: Richard Weinberger <richard@nod.at>\n---\n .../partitions/brcm,bcm4908-partitions.yaml   | 70 +++++++++++++++++++\n 1 file changed, 70 insertions(+)\n create mode 100644 Documentation/devicetree/bindings/mtd/partitions/brcm,bcm4908-partitions.yaml\n\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/mtd/partitions/brcm,bcm4908-partitions.yaml\n@@ -0,0 +1,70 @@\n+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause\n+%YAML 1.2\n+---\n+$id: http://devicetree.org/schemas/mtd/partitions/brcm,bcm4908-partitions.yaml#\n+$schema: http://devicetree.org/meta-schemas/core.yaml#\n+\n+title: Broadcom BCM4908 partitioning\n+\n+description: |\n+  Broadcom BCM4908 CFE bootloader supports two firmware partitions. One is used\n+  for regular booting, the other is treated as fallback.\n+\n+  This binding allows defining all fixed partitions and marking those containing\n+  firmware. System can use that information e.g. for booting or flashing\n+  purposes.\n+\n+maintainers:\n+  - Rafał Miłecki <rafal@milecki.pl>\n+\n+properties:\n+  compatible:\n+    const: brcm,bcm4908-partitions\n+\n+  \"#address-cells\":\n+    enum: [ 1, 2 ]\n+\n+  \"#size-cells\":\n+    enum: [ 1, 2 ]\n+\n+patternProperties:\n+  \"^partition@[0-9a-f]+$\":\n+    $ref: \"partition.yaml#\"\n+    properties:\n+      compatible:\n+        const: brcm,bcm4908-firmware\n+    unevaluatedProperties: false\n+\n+required:\n+  - \"#address-cells\"\n+  - \"#size-cells\"\n+\n+additionalProperties: false\n+\n+examples:\n+  - |\n+    partitions {\n+        compatible = \"brcm,bcm4908-partitions\";\n+        #address-cells = <1>;\n+        #size-cells = <1>;\n+\n+        partition@0 {\n+            label = \"cferom\";\n+            reg = <0x0 0x100000>;\n+        };\n+\n+        partition@100000 {\n+            compatible = \"brcm,bcm4908-firmware\";\n+            reg = <0x100000 0xf00000>;\n+        };\n+\n+        partition@1000000 {\n+            compatible = \"brcm,bcm4908-firmware\";\n+            reg = <0x1000000 0xf00000>;\n+        };\n+\n+        partition@1f00000 {\n+            label = \"calibration\";\n+            reg = <0x1f00000 0x100000>;\n+        };\n+    };\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/403-v5.13-mtd-parsers-ofpart-support-BCM4908-fixed-partitions.patch",
    "content": "From afbef8efb591792579c633a7c545f914c6165f82 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Thu, 11 Feb 2021 23:04:27 +0100\nSubject: [PATCH] mtd: parsers: ofpart: support BCM4908 fixed partitions\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nSome devices use fixed partitioning with some partitions requiring some\nextra logic. E.g. BCM4908 may have multiple firmware partitions but\ndetecting currently used one requires checking bootloader parameters.\n\nTo support such cases without duplicating a lot of code (without copying\nmost of the ofpart.c code) support for post-parsing callback was added.\n\nBCM4908 support in ofpart can be enabled using config option and results\nin compiling & executing a specific callback. It simply reads offset of\ncurrently used firmware partition from the DT. Bootloader specifies it\nusing the \"brcm_blparms\" property.\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\n---\n drivers/mtd/parsers/Kconfig                   |  9 +++\n drivers/mtd/parsers/Makefile                  |  2 +\n drivers/mtd/parsers/ofpart_bcm4908.c          | 64 +++++++++++++++++++\n drivers/mtd/parsers/ofpart_bcm4908.h          | 15 +++++\n .../mtd/parsers/{ofpart.c => ofpart_core.c}   | 28 +++++++-\n 5 files changed, 116 insertions(+), 2 deletions(-)\n create mode 100644 drivers/mtd/parsers/ofpart_bcm4908.c\n create mode 100644 drivers/mtd/parsers/ofpart_bcm4908.h\n rename drivers/mtd/parsers/{ofpart.c => ofpart_core.c} (88%)\n\n--- a/drivers/mtd/parsers/Kconfig\n+++ b/drivers/mtd/parsers/Kconfig\n@@ -67,6 +67,15 @@ config MTD_OF_PARTS\n \t  flash memory node, as described in\n \t  Documentation/devicetree/bindings/mtd/partition.txt.\n \n+config MTD_OF_PARTS_BCM4908\n+\tbool \"BCM4908 partitioning support\"\n+\tdepends on MTD_OF_PARTS && (ARCH_BCM4908 || COMPILE_TEST)\n+\tdefault ARCH_BCM4908\n+\thelp\n+\t  This provides partitions parser for BCM4908 family devices\n+\t  that can have multiple \"firmware\" partitions. It takes care of\n+\t  finding currently used one and backup ones.\n+\n config MTD_PARSER_IMAGETAG\n \ttristate \"Parser for BCM963XX Image Tag format partitions\"\n \tdepends on BCM63XX || BMIPS_GENERIC || COMPILE_TEST\n--- a/drivers/mtd/parsers/Makefile\n+++ b/drivers/mtd/parsers/Makefile\n@@ -4,6 +4,8 @@ obj-$(CONFIG_MTD_BCM47XX_PARTS)\t\t+= bcm4\n obj-$(CONFIG_MTD_BCM63XX_PARTS)\t\t+= bcm63xxpart.o\n obj-$(CONFIG_MTD_CMDLINE_PARTS)\t\t+= cmdlinepart.o\n obj-$(CONFIG_MTD_OF_PARTS)\t\t+= ofpart.o\n+ofpart-y\t\t\t\t+= ofpart_core.o\n+ofpart-$(CONFIG_MTD_OF_PARTS_BCM4908)\t+= ofpart_bcm4908.o\n obj-$(CONFIG_MTD_PARSER_IMAGETAG)\t+= parser_imagetag.o\n obj-$(CONFIG_MTD_AFS_PARTS)\t\t+= afs.o\n obj-$(CONFIG_MTD_PARSER_TRX)\t\t+= parser_trx.o\n--- /dev/null\n+++ b/drivers/mtd/parsers/ofpart_bcm4908.c\n@@ -0,0 +1,64 @@\n+// SPDX-License-Identifier: GPL-2.0\n+/*\n+ * Copyright (C) 2021 Rafał Miłecki <rafal@milecki.pl>\n+ */\n+\n+#include <linux/module.h>\n+#include <linux/init.h>\n+#include <linux/of.h>\n+#include <linux/mtd/mtd.h>\n+#include <linux/slab.h>\n+#include <linux/mtd/partitions.h>\n+\n+#include \"ofpart_bcm4908.h\"\n+\n+#define BLPARAMS_FW_OFFSET\t\t\"NAND_RFS_OFS\"\n+\n+static long long bcm4908_partitions_fw_offset(void)\n+{\n+\tstruct device_node *root;\n+\tstruct property *prop;\n+\tconst char *s;\n+\n+\troot = of_find_node_by_path(\"/\");\n+\tif (!root)\n+\t\treturn -ENOENT;\n+\n+\tof_property_for_each_string(root, \"brcm_blparms\", prop, s) {\n+\t\tsize_t len = strlen(BLPARAMS_FW_OFFSET);\n+\t\tunsigned long offset;\n+\t\tint err;\n+\n+\t\tif (strncmp(s, BLPARAMS_FW_OFFSET, len) || s[len] != '=')\n+\t\t\tcontinue;\n+\n+\t\terr = kstrtoul(s + len + 1, 0, &offset);\n+\t\tif (err) {\n+\t\t\tpr_err(\"failed to parse %s\\n\", s + len + 1);\n+\t\t\treturn err;\n+\t\t}\n+\n+\t\treturn offset << 10;\n+\t}\n+\n+\treturn -ENOENT;\n+}\n+\n+int bcm4908_partitions_post_parse(struct mtd_info *mtd, struct mtd_partition *parts, int nr_parts)\n+{\n+\tlong long fw_offset;\n+\tint i;\n+\n+\tfw_offset = bcm4908_partitions_fw_offset();\n+\n+\tfor (i = 0; i < nr_parts; i++) {\n+\t\tif (of_device_is_compatible(parts[i].of_node, \"brcm,bcm4908-firmware\")) {\n+\t\t\tif (fw_offset < 0 || parts[i].offset == fw_offset)\n+\t\t\t\tparts[i].name = \"firmware\";\n+\t\t\telse\n+\t\t\t\tparts[i].name = \"backup\";\n+\t\t}\n+\t}\n+\n+\treturn 0;\n+}\n--- /dev/null\n+++ b/drivers/mtd/parsers/ofpart_bcm4908.h\n@@ -0,0 +1,15 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+#ifndef __BCM4908_PARTITIONS_H\n+#define __BCM4908_PARTITIONS_H\n+\n+#ifdef CONFIG_MTD_OF_PARTS_BCM4908\n+int bcm4908_partitions_post_parse(struct mtd_info *mtd, struct mtd_partition *parts, int nr_parts);\n+#else\n+static inline int bcm4908_partitions_post_parse(struct mtd_info *mtd, struct mtd_partition *parts,\n+\t\t\t\t\t\tint nr_parts)\n+{\n+\treturn -EOPNOTSUPP;\n+}\n+#endif\n+\n+#endif\n--- a/drivers/mtd/parsers/ofpart.c\n+++ /dev/null\n@@ -1,239 +0,0 @@\n-// SPDX-License-Identifier: GPL-2.0-or-later\n-/*\n- * Flash partitions described by the OF (or flattened) device tree\n- *\n- * Copyright © 2006 MontaVista Software Inc.\n- * Author: Vitaly Wool <vwool@ru.mvista.com>\n- *\n- * Revised to handle newer style flash binding by:\n- *   Copyright © 2007 David Gibson, IBM Corporation.\n- */\n-\n-#include <linux/module.h>\n-#include <linux/init.h>\n-#include <linux/of.h>\n-#include <linux/mtd/mtd.h>\n-#include <linux/slab.h>\n-#include <linux/mtd/partitions.h>\n-\n-static bool node_has_compatible(struct device_node *pp)\n-{\n-\treturn of_get_property(pp, \"compatible\", NULL);\n-}\n-\n-static int parse_fixed_partitions(struct mtd_info *master,\n-\t\t\t\t  const struct mtd_partition **pparts,\n-\t\t\t\t  struct mtd_part_parser_data *data)\n-{\n-\tstruct mtd_partition *parts;\n-\tstruct device_node *mtd_node;\n-\tstruct device_node *ofpart_node;\n-\tconst char *partname;\n-\tstruct device_node *pp;\n-\tint nr_parts, i, ret = 0;\n-\tbool dedicated = true;\n-\n-\n-\t/* Pull of_node from the master device node */\n-\tmtd_node = mtd_get_of_node(master);\n-\tif (!mtd_node)\n-\t\treturn 0;\n-\n-\tofpart_node = of_get_child_by_name(mtd_node, \"partitions\");\n-\tif (!ofpart_node) {\n-\t\t/*\n-\t\t * We might get here even when ofpart isn't used at all (e.g.,\n-\t\t * when using another parser), so don't be louder than\n-\t\t * KERN_DEBUG\n-\t\t */\n-\t\tpr_debug(\"%s: 'partitions' subnode not found on %pOF. Trying to parse direct subnodes as partitions.\\n\",\n-\t\t\t master->name, mtd_node);\n-\t\tofpart_node = mtd_node;\n-\t\tdedicated = false;\n-\t} else if (!of_device_is_compatible(ofpart_node, \"fixed-partitions\")) {\n-\t\t/* The 'partitions' subnode might be used by another parser */\n-\t\treturn 0;\n-\t}\n-\n-\t/* First count the subnodes */\n-\tnr_parts = 0;\n-\tfor_each_child_of_node(ofpart_node,  pp) {\n-\t\tif (!dedicated && node_has_compatible(pp))\n-\t\t\tcontinue;\n-\n-\t\tnr_parts++;\n-\t}\n-\n-\tif (nr_parts == 0)\n-\t\treturn 0;\n-\n-\tparts = kcalloc(nr_parts, sizeof(*parts), GFP_KERNEL);\n-\tif (!parts)\n-\t\treturn -ENOMEM;\n-\n-\ti = 0;\n-\tfor_each_child_of_node(ofpart_node,  pp) {\n-\t\tconst __be32 *reg;\n-\t\tint len;\n-\t\tint a_cells, s_cells;\n-\n-\t\tif (!dedicated && node_has_compatible(pp))\n-\t\t\tcontinue;\n-\n-\t\treg = of_get_property(pp, \"reg\", &len);\n-\t\tif (!reg) {\n-\t\t\tif (dedicated) {\n-\t\t\t\tpr_debug(\"%s: ofpart partition %pOF (%pOF) missing reg property.\\n\",\n-\t\t\t\t\t master->name, pp,\n-\t\t\t\t\t mtd_node);\n-\t\t\t\tgoto ofpart_fail;\n-\t\t\t} else {\n-\t\t\t\tnr_parts--;\n-\t\t\t\tcontinue;\n-\t\t\t}\n-\t\t}\n-\n-\t\ta_cells = of_n_addr_cells(pp);\n-\t\ts_cells = of_n_size_cells(pp);\n-\t\tif (len / 4 != a_cells + s_cells) {\n-\t\t\tpr_debug(\"%s: ofpart partition %pOF (%pOF) error parsing reg property.\\n\",\n-\t\t\t\t master->name, pp,\n-\t\t\t\t mtd_node);\n-\t\t\tgoto ofpart_fail;\n-\t\t}\n-\n-\t\tparts[i].offset = of_read_number(reg, a_cells);\n-\t\tparts[i].size = of_read_number(reg + a_cells, s_cells);\n-\t\tparts[i].of_node = pp;\n-\n-\t\tpartname = of_get_property(pp, \"label\", &len);\n-\t\tif (!partname)\n-\t\t\tpartname = of_get_property(pp, \"name\", &len);\n-\t\tparts[i].name = partname;\n-\n-\t\tif (of_get_property(pp, \"read-only\", &len))\n-\t\t\tparts[i].mask_flags |= MTD_WRITEABLE;\n-\n-\t\tif (of_get_property(pp, \"lock\", &len))\n-\t\t\tparts[i].mask_flags |= MTD_POWERUP_LOCK;\n-\n-\t\tif (of_property_read_bool(pp, \"slc-mode\"))\n-\t\t\tparts[i].add_flags |= MTD_SLC_ON_MLC_EMULATION;\n-\n-\t\ti++;\n-\t}\n-\n-\tif (!nr_parts)\n-\t\tgoto ofpart_none;\n-\n-\t*pparts = parts;\n-\treturn nr_parts;\n-\n-ofpart_fail:\n-\tpr_err(\"%s: error parsing ofpart partition %pOF (%pOF)\\n\",\n-\t       master->name, pp, mtd_node);\n-\tret = -EINVAL;\n-ofpart_none:\n-\tof_node_put(pp);\n-\tkfree(parts);\n-\treturn ret;\n-}\n-\n-static const struct of_device_id parse_ofpart_match_table[] = {\n-\t{ .compatible = \"fixed-partitions\" },\n-\t{},\n-};\n-MODULE_DEVICE_TABLE(of, parse_ofpart_match_table);\n-\n-static struct mtd_part_parser ofpart_parser = {\n-\t.parse_fn = parse_fixed_partitions,\n-\t.name = \"fixed-partitions\",\n-\t.of_match_table = parse_ofpart_match_table,\n-};\n-\n-static int parse_ofoldpart_partitions(struct mtd_info *master,\n-\t\t\t\t      const struct mtd_partition **pparts,\n-\t\t\t\t      struct mtd_part_parser_data *data)\n-{\n-\tstruct mtd_partition *parts;\n-\tstruct device_node *dp;\n-\tint i, plen, nr_parts;\n-\tconst struct {\n-\t\t__be32 offset, len;\n-\t} *part;\n-\tconst char *names;\n-\n-\t/* Pull of_node from the master device node */\n-\tdp = mtd_get_of_node(master);\n-\tif (!dp)\n-\t\treturn 0;\n-\n-\tpart = of_get_property(dp, \"partitions\", &plen);\n-\tif (!part)\n-\t\treturn 0; /* No partitions found */\n-\n-\tpr_warn(\"Device tree uses obsolete partition map binding: %pOF\\n\", dp);\n-\n-\tnr_parts = plen / sizeof(part[0]);\n-\n-\tparts = kcalloc(nr_parts, sizeof(*parts), GFP_KERNEL);\n-\tif (!parts)\n-\t\treturn -ENOMEM;\n-\n-\tnames = of_get_property(dp, \"partition-names\", &plen);\n-\n-\tfor (i = 0; i < nr_parts; i++) {\n-\t\tparts[i].offset = be32_to_cpu(part->offset);\n-\t\tparts[i].size   = be32_to_cpu(part->len) & ~1;\n-\t\t/* bit 0 set signifies read only partition */\n-\t\tif (be32_to_cpu(part->len) & 1)\n-\t\t\tparts[i].mask_flags = MTD_WRITEABLE;\n-\n-\t\tif (names && (plen > 0)) {\n-\t\t\tint len = strlen(names) + 1;\n-\n-\t\t\tparts[i].name = names;\n-\t\t\tplen -= len;\n-\t\t\tnames += len;\n-\t\t} else {\n-\t\t\tparts[i].name = \"unnamed\";\n-\t\t}\n-\n-\t\tpart++;\n-\t}\n-\n-\t*pparts = parts;\n-\treturn nr_parts;\n-}\n-\n-static struct mtd_part_parser ofoldpart_parser = {\n-\t.parse_fn = parse_ofoldpart_partitions,\n-\t.name = \"ofoldpart\",\n-};\n-\n-static int __init ofpart_parser_init(void)\n-{\n-\tregister_mtd_parser(&ofpart_parser);\n-\tregister_mtd_parser(&ofoldpart_parser);\n-\treturn 0;\n-}\n-\n-static void __exit ofpart_parser_exit(void)\n-{\n-\tderegister_mtd_parser(&ofpart_parser);\n-\tderegister_mtd_parser(&ofoldpart_parser);\n-}\n-\n-module_init(ofpart_parser_init);\n-module_exit(ofpart_parser_exit);\n-\n-MODULE_LICENSE(\"GPL\");\n-MODULE_DESCRIPTION(\"Parser for MTD partitioning information in device tree\");\n-MODULE_AUTHOR(\"Vitaly Wool, David Gibson\");\n-/*\n- * When MTD core cannot find the requested parser, it tries to load the module\n- * with the same name. Since we provide the ofoldpart parser, we should have\n- * the corresponding alias.\n- */\n-MODULE_ALIAS(\"fixed-partitions\");\n-MODULE_ALIAS(\"ofoldpart\");\n--- /dev/null\n+++ b/drivers/mtd/parsers/ofpart_core.c\n@@ -0,0 +1,263 @@\n+// SPDX-License-Identifier: GPL-2.0-or-later\n+/*\n+ * Flash partitions described by the OF (or flattened) device tree\n+ *\n+ * Copyright © 2006 MontaVista Software Inc.\n+ * Author: Vitaly Wool <vwool@ru.mvista.com>\n+ *\n+ * Revised to handle newer style flash binding by:\n+ *   Copyright © 2007 David Gibson, IBM Corporation.\n+ */\n+\n+#include <linux/module.h>\n+#include <linux/init.h>\n+#include <linux/of.h>\n+#include <linux/mtd/mtd.h>\n+#include <linux/slab.h>\n+#include <linux/mtd/partitions.h>\n+\n+#include \"ofpart_bcm4908.h\"\n+\n+struct fixed_partitions_quirks {\n+\tint (*post_parse)(struct mtd_info *mtd, struct mtd_partition *parts, int nr_parts);\n+};\n+\n+struct fixed_partitions_quirks bcm4908_partitions_quirks = {\n+\t.post_parse = bcm4908_partitions_post_parse,\n+};\n+\n+static const struct of_device_id parse_ofpart_match_table[];\n+\n+static bool node_has_compatible(struct device_node *pp)\n+{\n+\treturn of_get_property(pp, \"compatible\", NULL);\n+}\n+\n+static int parse_fixed_partitions(struct mtd_info *master,\n+\t\t\t\t  const struct mtd_partition **pparts,\n+\t\t\t\t  struct mtd_part_parser_data *data)\n+{\n+\tconst struct fixed_partitions_quirks *quirks;\n+\tconst struct of_device_id *of_id;\n+\tstruct mtd_partition *parts;\n+\tstruct device_node *mtd_node;\n+\tstruct device_node *ofpart_node;\n+\tconst char *partname;\n+\tstruct device_node *pp;\n+\tint nr_parts, i, ret = 0;\n+\tbool dedicated = true;\n+\n+\t/* Pull of_node from the master device node */\n+\tmtd_node = mtd_get_of_node(master);\n+\tif (!mtd_node)\n+\t\treturn 0;\n+\n+\tofpart_node = of_get_child_by_name(mtd_node, \"partitions\");\n+\tif (!ofpart_node) {\n+\t\t/*\n+\t\t * We might get here even when ofpart isn't used at all (e.g.,\n+\t\t * when using another parser), so don't be louder than\n+\t\t * KERN_DEBUG\n+\t\t */\n+\t\tpr_debug(\"%s: 'partitions' subnode not found on %pOF. Trying to parse direct subnodes as partitions.\\n\",\n+\t\t\t master->name, mtd_node);\n+\t\tofpart_node = mtd_node;\n+\t\tdedicated = false;\n+\t}\n+\n+\tof_id = of_match_node(parse_ofpart_match_table, ofpart_node);\n+\tif (dedicated && !of_id) {\n+\t\t/* The 'partitions' subnode might be used by another parser */\n+\t\treturn 0;\n+\t}\n+\n+\tquirks = of_id ? of_id->data : NULL;\n+\n+\t/* First count the subnodes */\n+\tnr_parts = 0;\n+\tfor_each_child_of_node(ofpart_node,  pp) {\n+\t\tif (!dedicated && node_has_compatible(pp))\n+\t\t\tcontinue;\n+\n+\t\tnr_parts++;\n+\t}\n+\n+\tif (nr_parts == 0)\n+\t\treturn 0;\n+\n+\tparts = kcalloc(nr_parts, sizeof(*parts), GFP_KERNEL);\n+\tif (!parts)\n+\t\treturn -ENOMEM;\n+\n+\ti = 0;\n+\tfor_each_child_of_node(ofpart_node,  pp) {\n+\t\tconst __be32 *reg;\n+\t\tint len;\n+\t\tint a_cells, s_cells;\n+\n+\t\tif (!dedicated && node_has_compatible(pp))\n+\t\t\tcontinue;\n+\n+\t\treg = of_get_property(pp, \"reg\", &len);\n+\t\tif (!reg) {\n+\t\t\tif (dedicated) {\n+\t\t\t\tpr_debug(\"%s: ofpart partition %pOF (%pOF) missing reg property.\\n\",\n+\t\t\t\t\t master->name, pp,\n+\t\t\t\t\t mtd_node);\n+\t\t\t\tgoto ofpart_fail;\n+\t\t\t} else {\n+\t\t\t\tnr_parts--;\n+\t\t\t\tcontinue;\n+\t\t\t}\n+\t\t}\n+\n+\t\ta_cells = of_n_addr_cells(pp);\n+\t\ts_cells = of_n_size_cells(pp);\n+\t\tif (len / 4 != a_cells + s_cells) {\n+\t\t\tpr_debug(\"%s: ofpart partition %pOF (%pOF) error parsing reg property.\\n\",\n+\t\t\t\t master->name, pp,\n+\t\t\t\t mtd_node);\n+\t\t\tgoto ofpart_fail;\n+\t\t}\n+\n+\t\tparts[i].offset = of_read_number(reg, a_cells);\n+\t\tparts[i].size = of_read_number(reg + a_cells, s_cells);\n+\t\tparts[i].of_node = pp;\n+\n+\t\tpartname = of_get_property(pp, \"label\", &len);\n+\t\tif (!partname)\n+\t\t\tpartname = of_get_property(pp, \"name\", &len);\n+\t\tparts[i].name = partname;\n+\n+\t\tif (of_get_property(pp, \"read-only\", &len))\n+\t\t\tparts[i].mask_flags |= MTD_WRITEABLE;\n+\n+\t\tif (of_get_property(pp, \"lock\", &len))\n+\t\t\tparts[i].mask_flags |= MTD_POWERUP_LOCK;\n+\n+\t\tif (of_property_read_bool(pp, \"slc-mode\"))\n+\t\t\tparts[i].add_flags |= MTD_SLC_ON_MLC_EMULATION;\n+\n+\t\ti++;\n+\t}\n+\n+\tif (!nr_parts)\n+\t\tgoto ofpart_none;\n+\n+\tif (quirks && quirks->post_parse)\n+\t\tquirks->post_parse(master, parts, nr_parts);\n+\n+\t*pparts = parts;\n+\treturn nr_parts;\n+\n+ofpart_fail:\n+\tpr_err(\"%s: error parsing ofpart partition %pOF (%pOF)\\n\",\n+\t       master->name, pp, mtd_node);\n+\tret = -EINVAL;\n+ofpart_none:\n+\tof_node_put(pp);\n+\tkfree(parts);\n+\treturn ret;\n+}\n+\n+static const struct of_device_id parse_ofpart_match_table[] = {\n+\t/* Generic */\n+\t{ .compatible = \"fixed-partitions\" },\n+\t/* Customized */\n+\t{ .compatible = \"brcm,bcm4908-partitions\", .data = &bcm4908_partitions_quirks, },\n+\t{},\n+};\n+MODULE_DEVICE_TABLE(of, parse_ofpart_match_table);\n+\n+static struct mtd_part_parser ofpart_parser = {\n+\t.parse_fn = parse_fixed_partitions,\n+\t.name = \"fixed-partitions\",\n+\t.of_match_table = parse_ofpart_match_table,\n+};\n+\n+static int parse_ofoldpart_partitions(struct mtd_info *master,\n+\t\t\t\t      const struct mtd_partition **pparts,\n+\t\t\t\t      struct mtd_part_parser_data *data)\n+{\n+\tstruct mtd_partition *parts;\n+\tstruct device_node *dp;\n+\tint i, plen, nr_parts;\n+\tconst struct {\n+\t\t__be32 offset, len;\n+\t} *part;\n+\tconst char *names;\n+\n+\t/* Pull of_node from the master device node */\n+\tdp = mtd_get_of_node(master);\n+\tif (!dp)\n+\t\treturn 0;\n+\n+\tpart = of_get_property(dp, \"partitions\", &plen);\n+\tif (!part)\n+\t\treturn 0; /* No partitions found */\n+\n+\tpr_warn(\"Device tree uses obsolete partition map binding: %pOF\\n\", dp);\n+\n+\tnr_parts = plen / sizeof(part[0]);\n+\n+\tparts = kcalloc(nr_parts, sizeof(*parts), GFP_KERNEL);\n+\tif (!parts)\n+\t\treturn -ENOMEM;\n+\n+\tnames = of_get_property(dp, \"partition-names\", &plen);\n+\n+\tfor (i = 0; i < nr_parts; i++) {\n+\t\tparts[i].offset = be32_to_cpu(part->offset);\n+\t\tparts[i].size   = be32_to_cpu(part->len) & ~1;\n+\t\t/* bit 0 set signifies read only partition */\n+\t\tif (be32_to_cpu(part->len) & 1)\n+\t\t\tparts[i].mask_flags = MTD_WRITEABLE;\n+\n+\t\tif (names && (plen > 0)) {\n+\t\t\tint len = strlen(names) + 1;\n+\n+\t\t\tparts[i].name = names;\n+\t\t\tplen -= len;\n+\t\t\tnames += len;\n+\t\t} else {\n+\t\t\tparts[i].name = \"unnamed\";\n+\t\t}\n+\n+\t\tpart++;\n+\t}\n+\n+\t*pparts = parts;\n+\treturn nr_parts;\n+}\n+\n+static struct mtd_part_parser ofoldpart_parser = {\n+\t.parse_fn = parse_ofoldpart_partitions,\n+\t.name = \"ofoldpart\",\n+};\n+\n+static int __init ofpart_parser_init(void)\n+{\n+\tregister_mtd_parser(&ofpart_parser);\n+\tregister_mtd_parser(&ofoldpart_parser);\n+\treturn 0;\n+}\n+\n+static void __exit ofpart_parser_exit(void)\n+{\n+\tderegister_mtd_parser(&ofpart_parser);\n+\tderegister_mtd_parser(&ofoldpart_parser);\n+}\n+\n+module_init(ofpart_parser_init);\n+module_exit(ofpart_parser_exit);\n+\n+MODULE_LICENSE(\"GPL\");\n+MODULE_DESCRIPTION(\"Parser for MTD partitioning information in device tree\");\n+MODULE_AUTHOR(\"Vitaly Wool, David Gibson\");\n+/*\n+ * When MTD core cannot find the requested parser, it tries to load the module\n+ * with the same name. Since we provide the ofoldpart parser, we should have\n+ * the corresponding alias.\n+ */\n+MODULE_ALIAS(\"fixed-partitions\");\n+MODULE_ALIAS(\"ofoldpart\");\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/404-v5.13-mtd-parsers-ofpart-limit-parsing-of-deprecated-DT-sy.patch",
    "content": "From 2d751203aacf86a1b301a188d8551c7da91043ab Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Tue, 2 Mar 2021 20:00:12 +0100\nSubject: [PATCH] mtd: parsers: ofpart: limit parsing of deprecated DT syntax\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nFor backward compatibility ofpart still supports the old syntax like:\nspi-flash@0 {\n\tcompatible = \"jedec,spi-nor\";\n\treg = <0x0>;\n\n\tpartition@0 {\n\t\tlabel = \"bootloader\";\n\t\treg = <0x0 0x100000>;\n\t};\n};\n(without \"partitions\" subnode).\n\nThere is no reason however to support nested partitions without a clear\n\"compatible\" string like:\npartitions {\n\tcompatible = \"fixed-partitions\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tpartition@0 {\n\t\tlabel = \"bootloader\";\n\t\treg = <0x0 0x100000>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"config\";\n\t\t\treg = <0x80000 0x80000>;\n\t\t};\n\t};\n};\n(we never officially supported or documented that).\n\nMake sure ofpart doesn't attempt to parse above.\n\nCc: Ansuel Smith <ansuelsmth@gmail.com>\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nSigned-off-by: Miquel Raynal <miquel.raynal@bootlin.com>\nLink: https://lore.kernel.org/linux-mtd/20210302190012.1255-1-zajec5@gmail.com\n---\n drivers/mtd/parsers/ofpart_core.c | 4 +++-\n 1 file changed, 3 insertions(+), 1 deletion(-)\n\n--- a/drivers/mtd/parsers/ofpart_core.c\n+++ b/drivers/mtd/parsers/ofpart_core.c\n@@ -53,7 +53,7 @@ static int parse_fixed_partitions(struct\n \t\treturn 0;\n \n \tofpart_node = of_get_child_by_name(mtd_node, \"partitions\");\n-\tif (!ofpart_node) {\n+\tif (!ofpart_node && !master->parent) {\n \t\t/*\n \t\t * We might get here even when ofpart isn't used at all (e.g.,\n \t\t * when using another parser), so don't be louder than\n@@ -64,6 +64,8 @@ static int parse_fixed_partitions(struct\n \t\tofpart_node = mtd_node;\n \t\tdedicated = false;\n \t}\n+\tif (!ofpart_node)\n+\t\treturn 0;\n \n \tof_id = of_match_node(parse_ofpart_match_table, ofpart_node);\n \tif (dedicated && !of_id) {\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/405-v5.13-mtd-parsers-ofpart-make-symbol-bcm4908_partitions_qu.patch",
    "content": "From b87b6d2d6f540e29c3f98e1572d64e560d73d6c1 Mon Sep 17 00:00:00 2001\nFrom: Wei Yongjun <weiyongjun1@huawei.com>\nDate: Thu, 4 Mar 2021 06:46:00 +0000\nSubject: [PATCH] mtd: parsers: ofpart: make symbol 'bcm4908_partitions_quirks'\n static\n\nThe sparse tool complains as follows:\n\ndrivers/mtd/parsers/ofpart_core.c:25:32: warning:\n symbol 'bcm4908_partitions_quirks' was not declared. Should it be static?\n\nThis symbol is not used outside of ofpart_core.c, so this\ncommit marks it static.\n\nFixes: 457da931b608 (\"mtd: parsers: ofpart: support BCM4908 fixed partitions\")\nReported-by: Hulk Robot <hulkci@huawei.com>\nSigned-off-by: Wei Yongjun <weiyongjun1@huawei.com>\nSigned-off-by: Miquel Raynal <miquel.raynal@bootlin.com>\nLink: https://lore.kernel.org/linux-mtd/20210304064600.3279138-1-weiyongjun1@huawei.com\n---\n drivers/mtd/parsers/ofpart_core.c | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/drivers/mtd/parsers/ofpart_core.c\n+++ b/drivers/mtd/parsers/ofpart_core.c\n@@ -22,7 +22,7 @@ struct fixed_partitions_quirks {\n \tint (*post_parse)(struct mtd_info *mtd, struct mtd_partition *parts, int nr_parts);\n };\n \n-struct fixed_partitions_quirks bcm4908_partitions_quirks = {\n+static struct fixed_partitions_quirks bcm4908_partitions_quirks = {\n \t.post_parse = bcm4908_partitions_post_parse,\n };\n \n"
  },
  {
    "path": "target/linux/generic/backport-5.10/406-v5.13-0001-mtd-core-add-nvmem-cells-compatible-to-parse-mtd-as-.patch",
    "content": "From a5d83d6e2bc747b13f347962d4b335d70b23559b Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Fri, 12 Mar 2021 07:28:19 +0100\nSubject: [PATCH] mtd: core: add nvmem-cells compatible to parse mtd as nvmem\n cells\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nPartitions that contains the nvmem-cells compatible will register\ntheir direct subonodes as nvmem cells and the node will be treated as a\nnvmem provider.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nTested-by: Rafał Miłecki <rafal@milecki.pl>\n---\n drivers/mtd/mtdcore.c | 3 ++-\n 1 file changed, 2 insertions(+), 1 deletion(-)\n\n--- a/drivers/mtd/mtdcore.c\n+++ b/drivers/mtd/mtdcore.c\n@@ -531,6 +531,7 @@ static int mtd_nvmem_reg_read(void *priv\n \n static int mtd_nvmem_add(struct mtd_info *mtd)\n {\n+\tstruct device_node *node = mtd_get_of_node(mtd);\n \tstruct nvmem_config config = {};\n \n \tconfig.id = -1;\n@@ -543,7 +544,7 @@ static int mtd_nvmem_add(struct mtd_info\n \tconfig.stride = 1;\n \tconfig.read_only = true;\n \tconfig.root_only = true;\n-\tconfig.no_of_node = true;\n+\tconfig.no_of_node = !of_device_is_compatible(node, \"nvmem-cells\");\n \tconfig.priv = mtd;\n \n \tmtd->nvmem = nvmem_register(&config);\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/406-v5.13-0002-dt-bindings-nvmem-drop-nodename-restriction.patch",
    "content": "From 42645976c3289b03a12f1bd2bc131fd98fc27170 Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Fri, 12 Mar 2021 07:28:20 +0100\nSubject: [PATCH] devicetree: nvmem: nvmem: drop $nodename restriction\n\nDrop $nodename restriction as now mtd partition can also be used as\nnvmem provider.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\n---\n Documentation/devicetree/bindings/nvmem/nvmem.yaml | 3 ---\n 1 file changed, 3 deletions(-)\n\n--- a/Documentation/devicetree/bindings/nvmem/nvmem.yaml\n+++ b/Documentation/devicetree/bindings/nvmem/nvmem.yaml\n@@ -20,9 +20,6 @@ description: |\n   storage device.\n \n properties:\n-  $nodename:\n-    pattern: \"^(eeprom|efuse|nvram)(@.*|-[0-9a-f])*$\"\n-\n   \"#address-cells\":\n     const: 1\n \n"
  },
  {
    "path": "target/linux/generic/backport-5.10/406-v5.13-0003-dt-bindings-mtd-Document-use-of-nvmem-cells-compatib.patch",
    "content": "From 377aa0135dc8489312edd3184d143ce3a89ff7ee Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Fri, 12 Mar 2021 07:28:21 +0100\nSubject: [PATCH] dt-bindings: mtd: Document use of nvmem-cells compatible\n\nDocument nvmem-cells compatible used to treat mtd partitions as a\nnvmem provider.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nReviewed-by: Rob Herring <robh@kernel.org>\n---\n .../bindings/mtd/partitions/nvmem-cells.yaml  | 99 +++++++++++++++++++\n 1 file changed, 99 insertions(+)\n create mode 100644 Documentation/devicetree/bindings/mtd/partitions/nvmem-cells.yaml\n\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/mtd/partitions/nvmem-cells.yaml\n@@ -0,0 +1,99 @@\n+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause\n+%YAML 1.2\n+---\n+$id: http://devicetree.org/schemas/mtd/partitions/nvmem-cells.yaml#\n+$schema: http://devicetree.org/meta-schemas/core.yaml#\n+\n+title: Nvmem cells\n+\n+description: |\n+  Any partition containing the compatible \"nvmem-cells\" will register as a\n+  nvmem provider.\n+  Each direct subnodes represents a nvmem cell following the nvmem binding.\n+  Nvmem binding to declare nvmem-cells can be found in:\n+  Documentation/devicetree/bindings/nvmem/nvmem.yaml\n+\n+maintainers:\n+  - Ansuel Smith <ansuelsmth@gmail.com>\n+\n+allOf:\n+  - $ref: /schemas/nvmem/nvmem.yaml#\n+\n+properties:\n+  compatible:\n+    const: nvmem-cells\n+\n+required:\n+  - compatible\n+\n+additionalProperties: true\n+\n+examples:\n+  - |\n+    partitions {\n+      compatible = \"fixed-partitions\";\n+      #address-cells = <1>;\n+      #size-cells = <1>;\n+\n+      /* ... */\n+\n+      };\n+      art: art@1200000 {\n+        compatible = \"nvmem-cells\";\n+        reg = <0x1200000 0x0140000>;\n+        label = \"art\";\n+        read-only;\n+        #address-cells = <1>;\n+        #size-cells = <1>;\n+\n+        macaddr_gmac1: macaddr_gmac1@0 {\n+          reg = <0x0 0x6>;\n+        };\n+\n+        macaddr_gmac2: macaddr_gmac2@6 {\n+          reg = <0x6 0x6>;\n+        };\n+\n+        pre_cal_24g: pre_cal_24g@1000 {\n+          reg = <0x1000 0x2f20>;\n+        };\n+\n+        pre_cal_5g: pre_cal_5g@5000{\n+          reg = <0x5000 0x2f20>;\n+        };\n+      };\n+  - |\n+    partitions {\n+        compatible = \"fixed-partitions\";\n+        #address-cells = <1>;\n+        #size-cells = <1>;\n+\n+        partition@0 {\n+            label = \"bootloader\";\n+            reg = <0x000000 0x100000>;\n+            read-only;\n+        };\n+\n+        firmware@100000 {\n+            compatible = \"brcm,trx\";\n+            label = \"firmware\";\n+            reg = <0x100000 0xe00000>;\n+        };\n+\n+        calibration@f00000 {\n+            compatible = \"nvmem-cells\";\n+            label = \"calibration\";\n+            reg = <0xf00000 0x100000>;\n+            ranges = <0 0xf00000 0x100000>;\n+            #address-cells = <1>;\n+            #size-cells = <1>;\n+\n+            wifi0@0 {\n+                reg = <0x000000 0x080000>;\n+            };\n+\n+            wifi1@80000 {\n+                reg = <0x080000 0x080000>;\n+            };\n+        };\n+    };\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/407-v5.13-0001-dt-bindings-mtd-add-binding-for-Linksys-Northstar-pa.patch",
    "content": "From 2fa7294175c76e1ec568aa75c1891fd908728c8d Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Fri, 12 Mar 2021 14:49:18 +0100\nSubject: [PATCH] dt-bindings: mtd: add binding for Linksys Northstar\n partitions\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nLinksys on Broadcom Northstar devices uses fixed flash layout with\nmultiple firmware partitions.\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nReviewed-by: Rob Herring <robh@kernel.org>\nSigned-off-by: Miquel Raynal <miquel.raynal@bootlin.com>\nLink: https://lore.kernel.org/linux-mtd/20210312134919.7767-1-zajec5@gmail.com\n---\n .../mtd/partitions/linksys,ns-partitions.yaml | 74 +++++++++++++++++++\n 1 file changed, 74 insertions(+)\n create mode 100644 Documentation/devicetree/bindings/mtd/partitions/linksys,ns-partitions.yaml\n\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/mtd/partitions/linksys,ns-partitions.yaml\n@@ -0,0 +1,74 @@\n+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause\n+%YAML 1.2\n+---\n+$id: http://devicetree.org/schemas/mtd/partitions/linksys,ns-partitions.yaml#\n+$schema: http://devicetree.org/meta-schemas/core.yaml#\n+\n+title: Linksys Northstar partitioning\n+\n+description: |\n+  Linksys devices based on Broadcom Northstar architecture often use two\n+  firmware partitions. One is used for regular booting, the other is treated as\n+  fallback.\n+\n+  This binding allows defining all fixed partitions and marking those containing\n+  firmware. System can use that information e.g. for booting or flashing\n+  purposes.\n+\n+maintainers:\n+  - Rafał Miłecki <rafal@milecki.pl>\n+\n+properties:\n+  compatible:\n+    const: linksys,ns-partitions\n+\n+  \"#address-cells\":\n+    enum: [ 1, 2 ]\n+\n+  \"#size-cells\":\n+    enum: [ 1, 2 ]\n+\n+patternProperties:\n+  \"^partition@[0-9a-f]+$\":\n+    $ref: \"partition.yaml#\"\n+    properties:\n+      compatible:\n+        items:\n+          - const: linksys,ns-firmware\n+          - const: brcm,trx\n+    unevaluatedProperties: false\n+\n+required:\n+  - \"#address-cells\"\n+  - \"#size-cells\"\n+\n+additionalProperties: false\n+\n+examples:\n+  - |\n+    partitions {\n+        compatible = \"linksys,ns-partitions\";\n+        #address-cells = <1>;\n+        #size-cells = <1>;\n+\n+        partition@0 {\n+            label = \"boot\";\n+            reg = <0x0 0x100000>;\n+            read-only;\n+        };\n+\n+        partition@100000 {\n+            label = \"nvram\";\n+            reg = <0x100000 0x100000>;\n+        };\n+\n+        partition@200000 {\n+            compatible = \"linksys,ns-firmware\", \"brcm,trx\";\n+            reg = <0x200000 0xf00000>;\n+        };\n+\n+        partition@1100000 {\n+            compatible = \"linksys,ns-firmware\", \"brcm,trx\";\n+            reg = <0x1100000 0xf00000>;\n+        };\n+    };\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/407-v5.13-0002-mtd-parsers-ofpart-support-Linksys-Northstar-partiti.patch",
    "content": "From 7134a2d026d942210b4d26d6059c9d979ca7866e Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Fri, 12 Mar 2021 14:49:19 +0100\nSubject: [PATCH] mtd: parsers: ofpart: support Linksys Northstar partitions\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nThis allows extending ofpart parser with support for Linksys Northstar\ndevices. That support uses recently added quirks mechanism.\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nSigned-off-by: Miquel Raynal <miquel.raynal@bootlin.com>\nLink: https://lore.kernel.org/linux-mtd/20210312134919.7767-2-zajec5@gmail.com\n---\n drivers/mtd/parsers/Kconfig             | 10 +++++\n drivers/mtd/parsers/Makefile            |  1 +\n drivers/mtd/parsers/ofpart_core.c       |  6 +++\n drivers/mtd/parsers/ofpart_linksys_ns.c | 50 +++++++++++++++++++++++++\n drivers/mtd/parsers/ofpart_linksys_ns.h | 18 +++++++++\n 5 files changed, 85 insertions(+)\n create mode 100644 drivers/mtd/parsers/ofpart_linksys_ns.c\n create mode 100644 drivers/mtd/parsers/ofpart_linksys_ns.h\n\n--- a/drivers/mtd/parsers/Kconfig\n+++ b/drivers/mtd/parsers/Kconfig\n@@ -76,6 +76,16 @@ config MTD_OF_PARTS_BCM4908\n \t  that can have multiple \"firmware\" partitions. It takes care of\n \t  finding currently used one and backup ones.\n \n+config MTD_OF_PARTS_LINKSYS_NS\n+\tbool \"Linksys Northstar partitioning support\"\n+\tdepends on MTD_OF_PARTS && (ARCH_BCM_5301X || ARCH_BCM4908 || COMPILE_TEST)\n+\tdefault ARCH_BCM_5301X\n+\thelp\n+\t  This provides partitions parser for Linksys devices based on Broadcom\n+\t  Northstar architecture. Linksys commonly uses fixed flash layout with\n+\t  two \"firmware\" partitions. Currently used firmware has to be detected\n+\t  using CFE environment variable.\n+\n config MTD_PARSER_IMAGETAG\n \ttristate \"Parser for BCM963XX Image Tag format partitions\"\n \tdepends on BCM63XX || BMIPS_GENERIC || COMPILE_TEST\n--- a/drivers/mtd/parsers/Makefile\n+++ b/drivers/mtd/parsers/Makefile\n@@ -6,6 +6,7 @@ obj-$(CONFIG_MTD_CMDLINE_PARTS)\t\t+= cmdl\n obj-$(CONFIG_MTD_OF_PARTS)\t\t+= ofpart.o\n ofpart-y\t\t\t\t+= ofpart_core.o\n ofpart-$(CONFIG_MTD_OF_PARTS_BCM4908)\t+= ofpart_bcm4908.o\n+ofpart-$(CONFIG_MTD_OF_PARTS_LINKSYS_NS)+= ofpart_linksys_ns.o\n obj-$(CONFIG_MTD_PARSER_IMAGETAG)\t+= parser_imagetag.o\n obj-$(CONFIG_MTD_AFS_PARTS)\t\t+= afs.o\n obj-$(CONFIG_MTD_PARSER_TRX)\t\t+= parser_trx.o\n--- a/drivers/mtd/parsers/ofpart_core.c\n+++ b/drivers/mtd/parsers/ofpart_core.c\n@@ -17,6 +17,7 @@\n #include <linux/mtd/partitions.h>\n \n #include \"ofpart_bcm4908.h\"\n+#include \"ofpart_linksys_ns.h\"\n \n struct fixed_partitions_quirks {\n \tint (*post_parse)(struct mtd_info *mtd, struct mtd_partition *parts, int nr_parts);\n@@ -26,6 +27,10 @@ static struct fixed_partitions_quirks bc\n \t.post_parse = bcm4908_partitions_post_parse,\n };\n \n+static struct fixed_partitions_quirks linksys_ns_partitions_quirks = {\n+\t.post_parse = linksys_ns_partitions_post_parse,\n+};\n+\n static const struct of_device_id parse_ofpart_match_table[];\n \n static bool node_has_compatible(struct device_node *pp)\n@@ -167,6 +172,7 @@ static const struct of_device_id parse_o\n \t{ .compatible = \"fixed-partitions\" },\n \t/* Customized */\n \t{ .compatible = \"brcm,bcm4908-partitions\", .data = &bcm4908_partitions_quirks, },\n+\t{ .compatible = \"linksys,ns-partitions\", .data = &linksys_ns_partitions_quirks, },\n \t{},\n };\n MODULE_DEVICE_TABLE(of, parse_ofpart_match_table);\n--- /dev/null\n+++ b/drivers/mtd/parsers/ofpart_linksys_ns.c\n@@ -0,0 +1,50 @@\n+// SPDX-License-Identifier: GPL-2.0\n+/*\n+ * Copyright (C) 2021 Rafał Miłecki <rafal@milecki.pl>\n+ */\n+\n+#include <linux/bcm47xx_nvram.h>\n+#include <linux/mtd/mtd.h>\n+#include <linux/mtd/partitions.h>\n+\n+#include \"ofpart_linksys_ns.h\"\n+\n+#define NVRAM_BOOT_PART\t\t\"bootpartition\"\n+\n+static int ofpart_linksys_ns_bootpartition(void)\n+{\n+\tchar buf[4];\n+\tint bootpartition;\n+\n+\t/* Check CFE environment variable */\n+\tif (bcm47xx_nvram_getenv(NVRAM_BOOT_PART, buf, sizeof(buf)) > 0) {\n+\t\tif (!kstrtoint(buf, 0, &bootpartition))\n+\t\t\treturn bootpartition;\n+\t\tpr_warn(\"Failed to parse %s value \\\"%s\\\"\\n\", NVRAM_BOOT_PART,\n+\t\t\tbuf);\n+\t} else {\n+\t\tpr_warn(\"Failed to get NVRAM \\\"%s\\\"\\n\", NVRAM_BOOT_PART);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+int linksys_ns_partitions_post_parse(struct mtd_info *mtd,\n+\t\t\t\t     struct mtd_partition *parts,\n+\t\t\t\t     int nr_parts)\n+{\n+\tint bootpartition = ofpart_linksys_ns_bootpartition();\n+\tint trx_idx = 0;\n+\tint i;\n+\n+\tfor (i = 0; i < nr_parts; i++) {\n+\t\tif (of_device_is_compatible(parts[i].of_node, \"linksys,ns-firmware\")) {\n+\t\t\tif (trx_idx++ == bootpartition)\n+\t\t\t\tparts[i].name = \"firmware\";\n+\t\t\telse\n+\t\t\t\tparts[i].name = \"backup\";\n+\t\t}\n+\t}\n+\n+\treturn 0;\n+}\n--- /dev/null\n+++ b/drivers/mtd/parsers/ofpart_linksys_ns.h\n@@ -0,0 +1,18 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+#ifndef __OFPART_LINKSYS_NS_H\n+#define __OFPART_LINKSYS_NS_H\n+\n+#ifdef CONFIG_MTD_OF_PARTS_LINKSYS_NS\n+int linksys_ns_partitions_post_parse(struct mtd_info *mtd,\n+\t\t\t\t     struct mtd_partition *parts,\n+\t\t\t\t     int nr_parts);\n+#else\n+static inline int linksys_ns_partitions_post_parse(struct mtd_info *mtd,\n+\t\t\t\t\t\t   struct mtd_partition *parts,\n+\t\t\t\t\t\t   int nr_parts)\n+{\n+\treturn -EOPNOTSUPP;\n+}\n+#endif\n+\n+#endif\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/408-v5.13-mtd-cfi_cmdset_0002-Disable-buffered-writes-for-AMD.patch",
    "content": "From 7e4404113686868858a34210c28ae122e967aa64 Mon Sep 17 00:00:00 2001\nFrom: Mauri Sandberg <sandberg@mailfence.com>\nDate: Tue, 9 Mar 2021 19:48:59 +0200\nSubject: [PATCH] mtd: cfi_cmdset_0002: Disable buffered writes for AMD chip\n 0x2201\n\nBuffer writes do not work with AMD chip 0x2201. The chip in question\nis a AMD/Spansion/Cypress Semiconductor S29GL256N and datasheet [1]\ntalks about writing buffers being possible. While waiting for a neater\nsolution resort to writing word-sized chunks only.\n\nWithout the patch kernel logs will be flooded with entries like below:\n\njffs2_scan_eraseblock(): End of filesystem marker found at 0x0\njffs2_build_filesystem(): unlocking the mtd device...\ndone.\njffs2_build_filesystem(): erasing all blocks after the end marker...\nMTD do_write_buffer_wait(): software timeout, address:0x01ec000a.\njffs2: Write clean marker to block at 0x01920000 failed: -5\nMTD do_write_buffer_wait(): software timeout, address:0x01e2000a.\njffs2: Write clean marker to block at 0x01880000 failed: -5\nMTD do_write_buffer_wait(): software timeout, address:0x01e0000a.\njffs2: Write clean marker to block at 0x01860000 failed: -5\nMTD do_write_buffer_wait(): software timeout, address:0x01dc000a.\njffs2: Write clean marker to block at 0x01820000 failed: -5\nMTD do_write_buffer_wait(): software timeout, address:0x01da000a.\njffs2: Write clean marker to block at 0x01800000 failed: -5\n...\n\nTested on a Buffalo wzr-hp-g300nh running kernel 5.10.16.\n\n[1] https://www.cypress.com/file/219941/download\nor  https://datasheetspdf.com/pdf-file/565708/SPANSION/S29GL256N/1\n\nSigned-off-by: Mauri Sandberg <sandberg@mailfence.com>\nSigned-off-by: Vignesh Raghavendra <vigneshr@ti.com>\nLink: https://lore.kernel.org/r/20210309174859.362060-1-sandberg@mailfence.com\n---\n drivers/mtd/chips/cfi_cmdset_0002.c | 4 ++++\n 1 file changed, 4 insertions(+)\n\n--- a/drivers/mtd/chips/cfi_cmdset_0002.c\n+++ b/drivers/mtd/chips/cfi_cmdset_0002.c\n@@ -272,6 +272,10 @@ static void fixup_use_write_buffers(stru\n {\n \tstruct map_info *map = mtd->priv;\n \tstruct cfi_private *cfi = map->fldrv_priv;\n+\n+\tif (cfi->mfr == CFI_MFR_AMD && cfi->id == 0x2201)\n+\t\treturn;\n+\n \tif (cfi->cfiq->BufWriteTimeoutTyp) {\n \t\tpr_debug(\"Using buffer write method\\n\");\n \t\tmtd->_write = cfi_amdstd_write_buffers;\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/409-v5.14-0001-dt-bindings-mtd-brcm-trx-Add-brcm-trx-magic.patch",
    "content": "From a4d82940ff85a7e307953dfa715f65d5ab487e10 Mon Sep 17 00:00:00 2001\nFrom: Hauke Mehrtens <hauke@hauke-m.de>\nDate: Sun, 18 Apr 2021 23:46:14 +0200\nSubject: dt-bindings: mtd: brcm,trx: Add brcm,trx-magic\n\nThis adds the description of an additional property which allows to\nspecify a custom partition parser magic to detect a trx partition.\nBuffalo has multiple device which are using the trx format, but with\ndifferent magic values.\n\nSigned-off-by: Hauke Mehrtens <hauke@hauke-m.de>\nAcked-by: Rob Herring <robh@kernel.org>\nSigned-off-by: Miquel Raynal <miquel.raynal@bootlin.com>\nLink: https://lore.kernel.org/linux-mtd/20210418214616.239574-2-hauke@hauke-m.de\n---\n .../devicetree/bindings/mtd/partitions/brcm,trx.txt          | 5 +++++\n 1 file changed, 5 insertions(+)\n\n--- a/Documentation/devicetree/bindings/mtd/partitions/brcm,trx.txt\n+++ b/Documentation/devicetree/bindings/mtd/partitions/brcm,trx.txt\n@@ -28,6 +28,11 @@ detected by a software parsing TRX heade\n Required properties:\n - compatible : (required) must be \"brcm,trx\"\n \n+Optional properties:\n+\n+- brcm,trx-magic: TRX magic, if it is different from the default magic\n+\t\t  0x30524448 as a u32.\n+\n Example:\n \n flash@0 {\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/409-v5.14-0002-mtd-parsers-trx-Allow-to-specify-brcm-trx-magic-in-D.patch",
    "content": "From d7f7e04f8b67571a4bf5a0dcd4f9da4214f5262c Mon Sep 17 00:00:00 2001\nFrom: Hauke Mehrtens <hauke@hauke-m.de>\nDate: Sun, 18 Apr 2021 23:46:15 +0200\nSubject: mtd: parsers: trx: Allow to specify brcm, trx-magic in DT\n\nBuffalo uses a different TRX magic for every device, to be able to use\nthis trx parser, make it possible to specify the TRX magic in device\ntree. If no TRX magic is specified in device tree, the standard value\nwill be used. This value should only be specified if a vendor chooses to\nuse a non standard TRX magic.\n\nSigned-off-by: Hauke Mehrtens <hauke@hauke-m.de>\nSigned-off-by: Miquel Raynal <miquel.raynal@bootlin.com>\nLink: https://lore.kernel.org/linux-mtd/20210418214616.239574-3-hauke@hauke-m.de\n---\n drivers/mtd/parsers/parser_trx.c | 9 ++++++++-\n 1 file changed, 8 insertions(+), 1 deletion(-)\n\n--- a/drivers/mtd/parsers/parser_trx.c\n+++ b/drivers/mtd/parsers/parser_trx.c\n@@ -51,13 +51,20 @@ static int parser_trx_parse(struct mtd_i\n \t\t\t    const struct mtd_partition **pparts,\n \t\t\t    struct mtd_part_parser_data *data)\n {\n+\tstruct device_node *np = mtd_get_of_node(mtd);\n \tstruct mtd_partition *parts;\n \tstruct mtd_partition *part;\n \tstruct trx_header trx;\n \tsize_t bytes_read;\n \tuint8_t curr_part = 0, i = 0;\n+\tuint32_t trx_magic = TRX_MAGIC;\n \tint err;\n \n+\t/* Get different magic from device tree if specified */\n+\terr = of_property_read_u32(np, \"brcm,trx-magic\", &trx_magic);\n+\tif (err != 0 && err != -EINVAL)\n+\t\tpr_err(\"failed to parse \\\"brcm,trx-magic\\\" DT attribute, using default: %d\\n\", err);\n+\n \tparts = kcalloc(TRX_PARSER_MAX_PARTS, sizeof(struct mtd_partition),\n \t\t\tGFP_KERNEL);\n \tif (!parts)\n@@ -70,7 +77,7 @@ static int parser_trx_parse(struct mtd_i\n \t\treturn err;\n \t}\n \n-\tif (trx.magic != TRX_MAGIC) {\n+\tif (trx.magic != trx_magic) {\n \t\tkfree(parts);\n \t\treturn -ENOENT;\n \t}\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/409-v5.14-0003-mtd-parsers-trx-Allow-to-use-TRX-parser-on-Mediatek-.patch",
    "content": "From 81bb218c829246962a6327c64eec18ddcc049936 Mon Sep 17 00:00:00 2001\nFrom: Hauke Mehrtens <hauke@hauke-m.de>\nDate: Sun, 18 Apr 2021 23:46:16 +0200\nSubject: mtd: parsers: trx: Allow to use TRX parser on Mediatek SoCs\n\nBuffalo uses the TRX partition format also on Mediatek MT7622 SoCs.\n\nSigned-off-by: Hauke Mehrtens <hauke@hauke-m.de>\nSigned-off-by: Miquel Raynal <miquel.raynal@bootlin.com>\nLink: https://lore.kernel.org/linux-mtd/20210418214616.239574-4-hauke@hauke-m.de\n---\n drivers/mtd/parsers/Kconfig | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/drivers/mtd/parsers/Kconfig\n+++ b/drivers/mtd/parsers/Kconfig\n@@ -115,7 +115,7 @@ config MTD_AFS_PARTS\n \n config MTD_PARSER_TRX\n \ttristate \"Parser for TRX format partitions\"\n-\tdepends on MTD && (BCM47XX || ARCH_BCM_5301X || COMPILE_TEST)\n+\tdepends on MTD && (BCM47XX || ARCH_BCM_5301X || ARCH_MEDIATEK || COMPILE_TEST)\n \thelp\n \t  TRX is a firmware format used by Broadcom on their devices. It\n \t  may contain up to 3/4 partitions (depending on the version).\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/410-mtd-next-mtd-parsers-trx-allow-to-use-on-MediaTek-MIPS-SoCs.patch",
    "content": "From 2365f91c861cbfeef7141c69842848c7b2d3c2db Mon Sep 17 00:00:00 2001\nFrom: INAGAKI Hiroshi <musashino.open@gmail.com>\nDate: Sun, 13 Feb 2022 15:40:44 +0900\nSubject: [PATCH] mtd: parsers: trx: allow to use on MediaTek MIPS SoCs\n\nBuffalo sells some router devices which have trx-formatted firmware,\nbased on MediaTek MIPS SoCs. To use parser_trx on those devices, add\n\"RALINK\" to dependency and allow to compile for MediaTek MIPS SoCs.\n\nexamples:\n\n- WCR-1166DS  (MT7628)\n- WSR-1166DHP (MT7621)\n- WSR-2533DHP (MT7621)\n\nSigned-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>\nSigned-off-by: Miquel Raynal <miquel.raynal@bootlin.com>\nLink: https://lore.kernel.org/linux-mtd/20220213064045.1781-1-musashino.open@gmail.com\n---\n drivers/mtd/parsers/Kconfig | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/drivers/mtd/parsers/Kconfig\n+++ b/drivers/mtd/parsers/Kconfig\n@@ -115,7 +115,7 @@ config MTD_AFS_PARTS\n \n config MTD_PARSER_TRX\n \ttristate \"Parser for TRX format partitions\"\n-\tdepends on MTD && (BCM47XX || ARCH_BCM_5301X || ARCH_MEDIATEK || COMPILE_TEST)\n+\tdepends on MTD && (BCM47XX || ARCH_BCM_5301X || ARCH_MEDIATEK || RALINK || COMPILE_TEST)\n \thelp\n \t  TRX is a firmware format used by Broadcom on their devices. It\n \t  may contain up to 3/4 partitions (depending on the version).\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/419-v5.14-mtd-spinand-gigadevice-Support-GD5F1GQ5UExxG.patch",
    "content": "From bd568cc04c675b7fa97214d278a54794c2ecc2ad Mon Sep 17 00:00:00 2001\nFrom: Reto Schneider <reto.schneider@husqvarnagroup.com>\nDate: Thu, 11 Feb 2021 12:36:19 +0100\nSubject: [PATCH] mtd: spinand: gigadevice: Support GD5F1GQ5UExxG\n\nThe relevant changes to the already existing GD5F1GQ4UExxG support has\nbeen determined by consulting the GigaDevice product change notice\nAN-0392-10, version 1.0 from November 30, 2020.\n\nAs the overlaps are huge, variable names have been generalized\naccordingly.\n\nApart from the lowered ECC strength (4 instead of 8 bits per 512 bytes),\nthe new device ID, and the extra quad IO dummy byte, no changes had to\nbe taken into account.\n\nNew hardware features are not supported, namely:\n - Power on reset\n - Unique ID\n - Double transfer rate (DTR)\n - Parameter page\n - Random data quad IO\n\nThe inverted semantic of the \"driver strength\" register bits, defaulting\nto 100% instead of 50% for the Q5 devices, got ignored as the driver has\nnever touched them anyway.\n\nThe no longer supported \"read from cache during block erase\"\nfunctionality is not reflected as the current SPI NAND core does not\nsupport it anyway.\n\nImplementation has been tested on MediaTek MT7688 based GARDENA smart\nGateways using both, GigaDevice GD5F1GQ5UEYIG and GD5F1GQ4UBYIG.\n\nSigned-off-by: Reto Schneider <reto.schneider@husqvarnagroup.com>\nReviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>\nReviewed-by: Stefan Roese <sr@denx.de>\nSigned-off-by: Miquel Raynal <miquel.raynal@bootlin.com>\nLink: https://lore.kernel.org/linux-mtd/20210211113619.3502-1-code@reto-schneider.ch\n(cherry picked from commit 469b992489852b500d39048aa0013639dfe9f2e6)\n---\n drivers/mtd/nand/spi/gigadevice.c | 69 +++++++++++++++++++++++++++----\n 1 file changed, 60 insertions(+), 9 deletions(-)\n\n--- a/drivers/mtd/nand/spi/gigadevice.c\n+++ b/drivers/mtd/nand/spi/gigadevice.c\n@@ -13,7 +13,10 @@\n #define GD5FXGQ4XA_STATUS_ECC_1_7_BITFLIPS\t(1 << 4)\n #define GD5FXGQ4XA_STATUS_ECC_8_BITFLIPS\t(3 << 4)\n \n-#define GD5FXGQ4UEXXG_REG_STATUS2\t\t0xf0\n+#define GD5FXGQ5XE_STATUS_ECC_1_4_BITFLIPS\t(1 << 4)\n+#define GD5FXGQ5XE_STATUS_ECC_4_BITFLIPS\t(3 << 4)\n+\n+#define GD5FXGQXXEXXG_REG_STATUS2\t\t0xf0\n \n #define GD5FXGQ4UXFXXG_STATUS_ECC_MASK\t\t(7 << 4)\n #define GD5FXGQ4UXFXXG_STATUS_ECC_NO_BITFLIPS\t(0 << 4)\n@@ -102,7 +105,7 @@ static int gd5fxgq4xa_ecc_get_status(str\n \treturn -EINVAL;\n }\n \n-static int gd5fxgq4_variant2_ooblayout_ecc(struct mtd_info *mtd, int section,\n+static int gd5fxgqx_variant2_ooblayout_ecc(struct mtd_info *mtd, int section,\n \t\t\t\t       struct mtd_oob_region *region)\n {\n \tif (section)\n@@ -114,7 +117,7 @@ static int gd5fxgq4_variant2_ooblayout_e\n \treturn 0;\n }\n \n-static int gd5fxgq4_variant2_ooblayout_free(struct mtd_info *mtd, int section,\n+static int gd5fxgqx_variant2_ooblayout_free(struct mtd_info *mtd, int section,\n \t\t\t\t\tstruct mtd_oob_region *region)\n {\n \tif (section)\n@@ -127,9 +130,10 @@ static int gd5fxgq4_variant2_ooblayout_f\n \treturn 0;\n }\n \n-static const struct mtd_ooblayout_ops gd5fxgq4_variant2_ooblayout = {\n-\t.ecc = gd5fxgq4_variant2_ooblayout_ecc,\n-\t.free = gd5fxgq4_variant2_ooblayout_free,\n+/* Valid for Q4/Q5 and Q6 (untested) devices */\n+static const struct mtd_ooblayout_ops gd5fxgqx_variant2_ooblayout = {\n+\t.ecc = gd5fxgqx_variant2_ooblayout_ecc,\n+\t.free = gd5fxgqx_variant2_ooblayout_free,\n };\n \n static int gd5fxgq4xc_ooblayout_256_ecc(struct mtd_info *mtd, int section,\n@@ -165,7 +169,7 @@ static int gd5fxgq4uexxg_ecc_get_status(\n \t\t\t\t\tu8 status)\n {\n \tu8 status2;\n-\tstruct spi_mem_op op = SPINAND_GET_FEATURE_OP(GD5FXGQ4UEXXG_REG_STATUS2,\n+\tstruct spi_mem_op op = SPINAND_GET_FEATURE_OP(GD5FXGQXXEXXG_REG_STATUS2,\n \t\t\t\t\t\t      &status2);\n \tint ret;\n \n@@ -203,6 +207,43 @@ static int gd5fxgq4uexxg_ecc_get_status(\n \treturn -EINVAL;\n }\n \n+static int gd5fxgq5xexxg_ecc_get_status(struct spinand_device *spinand,\n+\t\t\t\t\tu8 status)\n+{\n+\tu8 status2;\n+\tstruct spi_mem_op op = SPINAND_GET_FEATURE_OP(GD5FXGQXXEXXG_REG_STATUS2,\n+\t\t\t\t\t\t      &status2);\n+\tint ret;\n+\n+\tswitch (status & STATUS_ECC_MASK) {\n+\tcase STATUS_ECC_NO_BITFLIPS:\n+\t\treturn 0;\n+\n+\tcase GD5FXGQ5XE_STATUS_ECC_1_4_BITFLIPS:\n+\t\t/*\n+\t\t * Read status2 register to determine a more fine grained\n+\t\t * bit error status\n+\t\t */\n+\t\tret = spi_mem_exec_op(spinand->spimem, &op);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\n+\t\t/*\n+\t\t * 1 ... 4 bits are flipped (and corrected)\n+\t\t */\n+\t\t/* bits sorted this way (1...0): ECCSE1, ECCSE0 */\n+\t\treturn ((status2 & STATUS_ECC_MASK) >> 4) + 1;\n+\n+\tcase STATUS_ECC_UNCOR_ERROR:\n+\t\treturn -EBADMSG;\n+\n+\tdefault:\n+\t\tbreak;\n+\t}\n+\n+\treturn -EINVAL;\n+}\n+\n static int gd5fxgq4ufxxg_ecc_get_status(struct spinand_device *spinand,\n \t\t\t\t\tu8 status)\n {\n@@ -282,7 +323,7 @@ static const struct spinand_info gigadev\n \t\t\t\t\t      &write_cache_variants,\n \t\t\t\t\t      &update_cache_variants),\n \t\t     SPINAND_HAS_QE_BIT,\n-\t\t     SPINAND_ECCINFO(&gd5fxgq4_variant2_ooblayout,\n+\t\t     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,\n \t\t\t\t     gd5fxgq4uexxg_ecc_get_status)),\n \tSPINAND_INFO(\"GD5F1GQ4UFxxG\",\n \t\t     SPINAND_ID(SPINAND_READID_METHOD_OPCODE, 0xb1, 0x48),\n@@ -292,8 +333,18 @@ static const struct spinand_info gigadev\n \t\t\t\t\t      &write_cache_variants,\n \t\t\t\t\t      &update_cache_variants),\n \t\t     SPINAND_HAS_QE_BIT,\n-\t\t     SPINAND_ECCINFO(&gd5fxgq4_variant2_ooblayout,\n+\t\t     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,\n \t\t\t\t     gd5fxgq4ufxxg_ecc_get_status)),\n+\tSPINAND_INFO(\"GD5F1GQ5UExxG\",\n+\t\t     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x51),\n+\t\t     NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),\n+\t\t     NAND_ECCREQ(4, 512),\n+\t\t     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,\n+\t\t\t\t\t      &write_cache_variants,\n+\t\t\t\t\t      &update_cache_variants),\n+\t\t     SPINAND_HAS_QE_BIT,\n+\t\t     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,\n+\t\t\t\t     gd5fxgq5xexxg_ecc_get_status)),\n };\n \n static const struct spinand_manufacturer_ops gigadevice_spinand_manuf_ops = {\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/420-v5.19-01-mtd-spinand-gigadevice-fix-Quad-IO-for-GD5F1GQ5UExxG.patch",
    "content": "From a4f9dd55c5e1bb951db6f1dee20e62e0103f3438 Mon Sep 17 00:00:00 2001\nFrom: Chuanhong Guo <gch981213@gmail.com>\nDate: Sun, 20 Mar 2022 17:59:57 +0800\nSubject: [PATCH 1/5] mtd: spinand: gigadevice: fix Quad IO for GD5F1GQ5UExxG\n\nRead From Cache Quad IO (EBH) uses 2 dummy bytes on this chip according\nto page 23 of the datasheet[0].\n\n[0]: https://www.gigadevice.com/datasheet/gd5f1gq5xexxg/\n\nFixes: 469b99248985 (\"mtd: spinand: gigadevice: Support GD5F1GQ5UExxG\")\nSigned-off-by: Chuanhong Guo <gch981213@gmail.com>\nSigned-off-by: Miquel Raynal <miquel.raynal@bootlin.com>\nLink: https://lore.kernel.org/linux-mtd/20220320100001.247905-2-gch981213@gmail.com\n---\n drivers/mtd/nand/spi/gigadevice.c | 10 +++++++++-\n 1 file changed, 9 insertions(+), 1 deletion(-)\n\n--- a/drivers/mtd/nand/spi/gigadevice.c\n+++ b/drivers/mtd/nand/spi/gigadevice.c\n@@ -39,6 +39,14 @@ static SPINAND_OP_VARIANTS(read_cache_va\n \t\tSPINAND_PAGE_READ_FROM_CACHE_OP_3A(true, 0, 1, NULL, 0),\n \t\tSPINAND_PAGE_READ_FROM_CACHE_OP_3A(false, 0, 0, NULL, 0));\n \n+static SPINAND_OP_VARIANTS(read_cache_variants_1gq5,\n+\t\tSPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),\n+\t\tSPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),\n+\t\tSPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),\n+\t\tSPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),\n+\t\tSPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),\n+\t\tSPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));\n+\n static SPINAND_OP_VARIANTS(write_cache_variants,\n \t\tSPINAND_PROG_LOAD_X4(true, 0, NULL, 0),\n \t\tSPINAND_PROG_LOAD(true, 0, NULL, 0));\n@@ -339,7 +347,7 @@ static const struct spinand_info gigadev\n \t\t     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x51),\n \t\t     NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),\n \t\t     NAND_ECCREQ(4, 512),\n-\t\t     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,\n+\t\t     SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,\n \t\t\t\t\t      &write_cache_variants,\n \t\t\t\t\t      &update_cache_variants),\n \t\t     SPINAND_HAS_QE_BIT,\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/420-v5.19-02-mtd-spinand-gigadevice-add-support-for-GD5FxGQ4xExxG.patch",
    "content": "From 573eec222bc82fb5e724586267fbbb1aed9ffd03 Mon Sep 17 00:00:00 2001\nFrom: Chuanhong Guo <gch981213@gmail.com>\nDate: Sun, 20 Mar 2022 17:59:58 +0800\nSubject: [PATCH 2/5] mtd: spinand: gigadevice: add support for GD5FxGQ4xExxG\n\nAdd support for:\n GD5F1GQ4RExxG\n GD5F2GQ4{U,R}ExxG\n\nThese chips differ from GD5F1GQ4UExxG only in chip ID, voltage\nand capacity.\n\nSigned-off-by: Chuanhong Guo <gch981213@gmail.com>\nSigned-off-by: Miquel Raynal <miquel.raynal@bootlin.com>\nLink: https://lore.kernel.org/linux-mtd/20220320100001.247905-3-gch981213@gmail.com\n---\n drivers/mtd/nand/spi/gigadevice.c | 30 ++++++++++++++++++++++++++++++\n 1 file changed, 30 insertions(+)\n\n--- a/drivers/mtd/nand/spi/gigadevice.c\n+++ b/drivers/mtd/nand/spi/gigadevice.c\n@@ -333,6 +333,36 @@ static const struct spinand_info gigadev\n \t\t     SPINAND_HAS_QE_BIT,\n \t\t     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,\n \t\t\t\t     gd5fxgq4uexxg_ecc_get_status)),\n+\tSPINAND_INFO(\"GD5F1GQ4RExxG\",\n+\t\t     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xc1),\n+\t\t     NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),\n+\t\t     NAND_ECCREQ(8, 512),\n+\t\t     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,\n+\t\t\t\t\t      &write_cache_variants,\n+\t\t\t\t\t      &update_cache_variants),\n+\t\t     SPINAND_HAS_QE_BIT,\n+\t\t     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,\n+\t\t\t\t     gd5fxgq4uexxg_ecc_get_status)),\n+\tSPINAND_INFO(\"GD5F2GQ4UExxG\",\n+\t\t     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xd2),\n+\t\t     NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),\n+\t\t     NAND_ECCREQ(8, 512),\n+\t\t     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,\n+\t\t\t\t\t      &write_cache_variants,\n+\t\t\t\t\t      &update_cache_variants),\n+\t\t     SPINAND_HAS_QE_BIT,\n+\t\t     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,\n+\t\t\t\t     gd5fxgq4uexxg_ecc_get_status)),\n+\tSPINAND_INFO(\"GD5F2GQ4RExxG\",\n+\t\t     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xc2),\n+\t\t     NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),\n+\t\t     NAND_ECCREQ(8, 512),\n+\t\t     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,\n+\t\t\t\t\t      &write_cache_variants,\n+\t\t\t\t\t      &update_cache_variants),\n+\t\t     SPINAND_HAS_QE_BIT,\n+\t\t     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,\n+\t\t\t\t     gd5fxgq4uexxg_ecc_get_status)),\n \tSPINAND_INFO(\"GD5F1GQ4UFxxG\",\n \t\t     SPINAND_ID(SPINAND_READID_METHOD_OPCODE, 0xb1, 0x48),\n \t\t     NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/420-v5.19-03-mtd-spinand-gigadevice-add-support-for-GD5F1GQ5RExxG.patch",
    "content": "From 620a988813403318023296b61228ee8f3fcdb8e0 Mon Sep 17 00:00:00 2001\nFrom: Chuanhong Guo <gch981213@gmail.com>\nDate: Sun, 20 Mar 2022 17:59:59 +0800\nSubject: [PATCH 3/5] mtd: spinand: gigadevice: add support for GD5F1GQ5RExxG\n\nThis chip is the 1.8v version of GD5F1GQ5UExxG.\n\nSigned-off-by: Chuanhong Guo <gch981213@gmail.com>\nSigned-off-by: Miquel Raynal <miquel.raynal@bootlin.com>\nLink: https://lore.kernel.org/linux-mtd/20220320100001.247905-4-gch981213@gmail.com\n---\n drivers/mtd/nand/spi/gigadevice.c | 10 ++++++++++\n 1 file changed, 10 insertions(+)\n\n--- a/drivers/mtd/nand/spi/gigadevice.c\n+++ b/drivers/mtd/nand/spi/gigadevice.c\n@@ -383,6 +383,16 @@ static const struct spinand_info gigadev\n \t\t     SPINAND_HAS_QE_BIT,\n \t\t     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,\n \t\t\t\t     gd5fxgq5xexxg_ecc_get_status)),\n+\tSPINAND_INFO(\"GD5F1GQ5RExxG\",\n+\t\t     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x41),\n+\t\t     NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),\n+\t\t     NAND_ECCREQ(4, 512),\n+\t\t     SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,\n+\t\t\t\t\t      &write_cache_variants,\n+\t\t\t\t\t      &update_cache_variants),\n+\t\t     SPINAND_HAS_QE_BIT,\n+\t\t     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,\n+\t\t\t\t     gd5fxgq5xexxg_ecc_get_status)),\n };\n \n static const struct spinand_manufacturer_ops gigadevice_spinand_manuf_ops = {\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/420-v5.19-04-mtd-spinand-gigadevice-add-support-for-GD5F-2-4-GQ5x.patch",
    "content": "From 194ec04b3a9e7fa97d1fbef296410631bc3cf1c8 Mon Sep 17 00:00:00 2001\nFrom: Chuanhong Guo <gch981213@gmail.com>\nDate: Sun, 20 Mar 2022 18:00:00 +0800\nSubject: [PATCH 4/5] mtd: spinand: gigadevice: add support for GD5F{2,\n 4}GQ5xExxG\n\nAdd support for:\n GD5F2GQ5{U,R}ExxG\n GD5F4GQ6{U,R}ExxG\n\nThese chips uses 4 dummy bytes for quad io and 2 dummy bytes for dual io.\nBesides that and memory layout, they are identical to their 1G variant.\n\nSigned-off-by: Chuanhong Guo <gch981213@gmail.com>\nSigned-off-by: Miquel Raynal <miquel.raynal@bootlin.com>\nLink: https://lore.kernel.org/linux-mtd/20220320100001.247905-5-gch981213@gmail.com\n---\n drivers/mtd/nand/spi/gigadevice.c | 48 +++++++++++++++++++++++++++++++\n 1 file changed, 48 insertions(+)\n\n--- a/drivers/mtd/nand/spi/gigadevice.c\n+++ b/drivers/mtd/nand/spi/gigadevice.c\n@@ -47,6 +47,14 @@ static SPINAND_OP_VARIANTS(read_cache_va\n \t\tSPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),\n \t\tSPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));\n \n+static SPINAND_OP_VARIANTS(read_cache_variants_2gq5,\n+\t\tSPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 4, NULL, 0),\n+\t\tSPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),\n+\t\tSPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 2, NULL, 0),\n+\t\tSPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),\n+\t\tSPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),\n+\t\tSPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));\n+\n static SPINAND_OP_VARIANTS(write_cache_variants,\n \t\tSPINAND_PROG_LOAD_X4(true, 0, NULL, 0),\n \t\tSPINAND_PROG_LOAD(true, 0, NULL, 0));\n@@ -391,6 +399,46 @@ static const struct spinand_info gigadev\n \t\t\t\t\t      &write_cache_variants,\n \t\t\t\t\t      &update_cache_variants),\n \t\t     SPINAND_HAS_QE_BIT,\n+\t\t     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,\n+\t\t\t\t     gd5fxgq5xexxg_ecc_get_status)),\n+\tSPINAND_INFO(\"GD5F2GQ5UExxG\",\n+\t\t     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x52),\n+\t\t     NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),\n+\t\t     NAND_ECCREQ(4, 512),\n+\t\t     SPINAND_INFO_OP_VARIANTS(&read_cache_variants_2gq5,\n+\t\t\t\t\t      &write_cache_variants,\n+\t\t\t\t\t      &update_cache_variants),\n+\t\t     SPINAND_HAS_QE_BIT,\n+\t\t     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,\n+\t\t\t\t     gd5fxgq5xexxg_ecc_get_status)),\n+\tSPINAND_INFO(\"GD5F2GQ5RExxG\",\n+\t\t     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x42),\n+\t\t     NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),\n+\t\t     NAND_ECCREQ(4, 512),\n+\t\t     SPINAND_INFO_OP_VARIANTS(&read_cache_variants_2gq5,\n+\t\t\t\t\t      &write_cache_variants,\n+\t\t\t\t\t      &update_cache_variants),\n+\t\t     SPINAND_HAS_QE_BIT,\n+\t\t     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,\n+\t\t\t\t     gd5fxgq5xexxg_ecc_get_status)),\n+\tSPINAND_INFO(\"GD5F4GQ6UExxG\",\n+\t\t     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x55),\n+\t\t     NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 2, 1),\n+\t\t     NAND_ECCREQ(4, 512),\n+\t\t     SPINAND_INFO_OP_VARIANTS(&read_cache_variants_2gq5,\n+\t\t\t\t\t      &write_cache_variants,\n+\t\t\t\t\t      &update_cache_variants),\n+\t\t     SPINAND_HAS_QE_BIT,\n+\t\t     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,\n+\t\t\t\t     gd5fxgq5xexxg_ecc_get_status)),\n+\tSPINAND_INFO(\"GD5F4GQ6RExxG\",\n+\t\t     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x45),\n+\t\t     NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 2, 1),\n+\t\t     NAND_ECCREQ(4, 512),\n+\t\t     SPINAND_INFO_OP_VARIANTS(&read_cache_variants_2gq5,\n+\t\t\t\t\t      &write_cache_variants,\n+\t\t\t\t\t      &update_cache_variants),\n+\t\t     SPINAND_HAS_QE_BIT,\n \t\t     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,\n \t\t\t\t     gd5fxgq5xexxg_ecc_get_status)),\n };\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/420-v5.19-05-mtd-spinand-gigadevice-add-support-for-GD5FxGM7xExxG.patch",
    "content": "From 54647cd003c08b714474a5b599a147ec6a160486 Mon Sep 17 00:00:00 2001\nFrom: Chuanhong Guo <gch981213@gmail.com>\nDate: Sun, 20 Mar 2022 18:00:01 +0800\nSubject: [PATCH 5/5] mtd: spinand: gigadevice: add support for GD5FxGM7xExxG\n\nAdd support for:\n GD5F{1,2}GM7{U,R}ExxG\n GD5F4GM8{U,R}ExxG\n\nThese are new 27nm counterparts for the GD5FxGQ4 chips from GigaDevice\nwith 8b/512b on-die ECC capability.\nThese chips (and currently supported GD5FxGQ5 chips) have QIO DTR\ninstruction for reading page cache. It isn't added in this patch because\nI don't have a DTR spi controller for testing.\n\nSigned-off-by: Chuanhong Guo <gch981213@gmail.com>\nSigned-off-by: Miquel Raynal <miquel.raynal@bootlin.com>\nLink: https://lore.kernel.org/linux-mtd/20220320100001.247905-6-gch981213@gmail.com\n---\n drivers/mtd/nand/spi/gigadevice.c | 60 +++++++++++++++++++++++++++++++\n 1 file changed, 60 insertions(+)\n\n--- a/drivers/mtd/nand/spi/gigadevice.c\n+++ b/drivers/mtd/nand/spi/gigadevice.c\n@@ -441,6 +441,66 @@ static const struct spinand_info gigadev\n \t\t     SPINAND_HAS_QE_BIT,\n \t\t     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,\n \t\t\t\t     gd5fxgq5xexxg_ecc_get_status)),\n+\tSPINAND_INFO(\"GD5F1GM7UExxG\",\n+\t\t     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x91),\n+\t\t     NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),\n+\t\t     NAND_ECCREQ(8, 512),\n+\t\t     SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,\n+\t\t\t\t\t      &write_cache_variants,\n+\t\t\t\t\t      &update_cache_variants),\n+\t\t     SPINAND_HAS_QE_BIT,\n+\t\t     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,\n+\t\t\t\t     gd5fxgq4uexxg_ecc_get_status)),\n+\tSPINAND_INFO(\"GD5F1GM7RExxG\",\n+\t\t     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x81),\n+\t\t     NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),\n+\t\t     NAND_ECCREQ(8, 512),\n+\t\t     SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,\n+\t\t\t\t\t      &write_cache_variants,\n+\t\t\t\t\t      &update_cache_variants),\n+\t\t     SPINAND_HAS_QE_BIT,\n+\t\t     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,\n+\t\t\t\t     gd5fxgq4uexxg_ecc_get_status)),\n+\tSPINAND_INFO(\"GD5F2GM7UExxG\",\n+\t\t     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x92),\n+\t\t     NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),\n+\t\t     NAND_ECCREQ(8, 512),\n+\t\t     SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,\n+\t\t\t\t\t      &write_cache_variants,\n+\t\t\t\t\t      &update_cache_variants),\n+\t\t     SPINAND_HAS_QE_BIT,\n+\t\t     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,\n+\t\t\t\t     gd5fxgq4uexxg_ecc_get_status)),\n+\tSPINAND_INFO(\"GD5F2GM7RExxG\",\n+\t\t     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x82),\n+\t\t     NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),\n+\t\t     NAND_ECCREQ(8, 512),\n+\t\t     SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,\n+\t\t\t\t\t      &write_cache_variants,\n+\t\t\t\t\t      &update_cache_variants),\n+\t\t     SPINAND_HAS_QE_BIT,\n+\t\t     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,\n+\t\t\t\t     gd5fxgq4uexxg_ecc_get_status)),\n+\tSPINAND_INFO(\"GD5F4GM8UExxG\",\n+\t\t     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x95),\n+\t\t     NAND_MEMORG(1, 2048, 128, 64, 4096, 80, 1, 1, 1),\n+\t\t     NAND_ECCREQ(8, 512),\n+\t\t     SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,\n+\t\t\t\t\t      &write_cache_variants,\n+\t\t\t\t\t      &update_cache_variants),\n+\t\t     SPINAND_HAS_QE_BIT,\n+\t\t     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,\n+\t\t\t\t     gd5fxgq4uexxg_ecc_get_status)),\n+\tSPINAND_INFO(\"GD5F4GM8RExxG\",\n+\t\t     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x85),\n+\t\t     NAND_MEMORG(1, 2048, 128, 64, 4096, 80, 1, 1, 1),\n+\t\t     NAND_ECCREQ(8, 512),\n+\t\t     SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,\n+\t\t\t\t\t      &write_cache_variants,\n+\t\t\t\t\t      &update_cache_variants),\n+\t\t     SPINAND_HAS_QE_BIT,\n+\t\t     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,\n+\t\t\t\t     gd5fxgq4uexxg_ecc_get_status)),\n };\n \n static const struct spinand_manufacturer_ops gigadevice_spinand_manuf_ops = {\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/500-v5.13-ubifs-default-to-zstd-compression.patch",
    "content": "From dcdf415b740923530dc71d89fecc8361078473f5 Mon Sep 17 00:00:00 2001\nFrom: Rui Salvaterra <rsalvaterra@gmail.com>\nDate: Mon, 5 Apr 2021 16:11:55 +0100\nSubject: [PATCH] ubifs: default to zstd compression\n\nCompared to lzo and zlib, zstd is the best all-around performer, both in terms\nof speed and compression ratio. Set it as the default, if available.\n\nSigned-off-by: Rui Salvaterra <rsalvaterra@gmail.com>\n---\n fs/ubifs/sb.c | 3 +++\n 1 file changed, 3 insertions(+)\n\n--- a/fs/ubifs/sb.c\n+++ b/fs/ubifs/sb.c\n@@ -53,6 +53,9 @@\n \n static int get_default_compressor(struct ubifs_info *c)\n {\n+\tif (ubifs_compr_present(c, UBIFS_COMPR_ZSTD))\n+\t\treturn UBIFS_COMPR_ZSTD;\n+\n \tif (ubifs_compr_present(c, UBIFS_COMPR_LZO))\n \t\treturn UBIFS_COMPR_LZO;\n \n"
  },
  {
    "path": "target/linux/generic/backport-5.10/600-v5.12-net-extract-napi-poll-functionality-to-__napi_poll.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nDate: Mon, 8 Feb 2021 11:34:08 -0800\nSubject: [PATCH] net: extract napi poll functionality to __napi_poll()\n\nThis commit introduces a new function __napi_poll() which does the main\nlogic of the existing napi_poll() function, and will be called by other\nfunctions in later commits.\nThis idea and implementation is done by Felix Fietkau <nbd@nbd.name> and\nis proposed as part of the patch to move napi work to work_queue\ncontext.\nThis commit by itself is a code restructure.\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\nSigned-off-by: Wei Wang <weiwan@google.com>\nReviewed-by: Alexander Duyck <alexanderduyck@fb.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n\n--- a/net/core/dev.c\n+++ b/net/core/dev.c\n@@ -6805,15 +6805,10 @@ void __netif_napi_del(struct napi_struct\n }\n EXPORT_SYMBOL(__netif_napi_del);\n \n-static int napi_poll(struct napi_struct *n, struct list_head *repoll)\n+static int __napi_poll(struct napi_struct *n, bool *repoll)\n {\n-\tvoid *have;\n \tint work, weight;\n \n-\tlist_del_init(&n->poll_list);\n-\n-\thave = netpoll_poll_lock(n);\n-\n \tweight = n->weight;\n \n \t/* This NAPI_STATE_SCHED test is for avoiding a race\n@@ -6833,7 +6828,7 @@ static int napi_poll(struct napi_struct\n \t\t\t    n->poll, work, weight);\n \n \tif (likely(work < weight))\n-\t\tgoto out_unlock;\n+\t\treturn work;\n \n \t/* Drivers must not modify the NAPI state if they\n \t * consume the entire weight.  In such cases this code\n@@ -6842,7 +6837,7 @@ static int napi_poll(struct napi_struct\n \t */\n \tif (unlikely(napi_disable_pending(n))) {\n \t\tnapi_complete(n);\n-\t\tgoto out_unlock;\n+\t\treturn work;\n \t}\n \n \tif (n->gro_bitmask) {\n@@ -6860,12 +6855,29 @@ static int napi_poll(struct napi_struct\n \tif (unlikely(!list_empty(&n->poll_list))) {\n \t\tpr_warn_once(\"%s: Budget exhausted after napi rescheduled\\n\",\n \t\t\t     n->dev ? n->dev->name : \"backlog\");\n-\t\tgoto out_unlock;\n+\t\treturn work;\n \t}\n \n-\tlist_add_tail(&n->poll_list, repoll);\n+\t*repoll = true;\n+\n+\treturn work;\n+}\n+\n+static int napi_poll(struct napi_struct *n, struct list_head *repoll)\n+{\n+\tbool do_repoll = false;\n+\tvoid *have;\n+\tint work;\n+\n+\tlist_del_init(&n->poll_list);\n+\n+\thave = netpoll_poll_lock(n);\n+\n+\twork = __napi_poll(n, &do_repoll);\n+\n+\tif (do_repoll)\n+\t\tlist_add_tail(&n->poll_list, repoll);\n \n-out_unlock:\n \tnetpoll_poll_unlock(have);\n \n \treturn work;\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/601-v5.12-net-implement-threaded-able-napi-poll-loop-support.patch",
    "content": "From: Wei Wang <weiwan@google.com>\nDate: Mon, 8 Feb 2021 11:34:09 -0800\nSubject: [PATCH] net: implement threaded-able napi poll loop support\n\nThis patch allows running each napi poll loop inside its own\nkernel thread.\nThe kthread is created during netif_napi_add() if dev->threaded\nis set. And threaded mode is enabled in napi_enable(). We will\nprovide a way to set dev->threaded and enable threaded mode\nwithout a device up/down in the following patch.\n\nOnce that threaded mode is enabled and the kthread is\nstarted, napi_schedule() will wake-up such thread instead\nof scheduling the softirq.\n\nThe threaded poll loop behaves quite likely the net_rx_action,\nbut it does not have to manipulate local irqs and uses\nan explicit scheduling point based on netdev_budget.\n\nCo-developed-by: Paolo Abeni <pabeni@redhat.com>\nSigned-off-by: Paolo Abeni <pabeni@redhat.com>\nCo-developed-by: Hannes Frederic Sowa <hannes@stressinduktion.org>\nSigned-off-by: Hannes Frederic Sowa <hannes@stressinduktion.org>\nCo-developed-by: Jakub Kicinski <kuba@kernel.org>\nSigned-off-by: Jakub Kicinski <kuba@kernel.org>\nSigned-off-by: Wei Wang <weiwan@google.com>\nReviewed-by: Alexander Duyck <alexanderduyck@fb.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n\n--- a/include/linux/netdevice.h\n+++ b/include/linux/netdevice.h\n@@ -347,6 +347,7 @@ struct napi_struct {\n \tstruct list_head\tdev_list;\n \tstruct hlist_node\tnapi_hash_node;\n \tunsigned int\t\tnapi_id;\n+\tstruct task_struct\t*thread;\n };\n \n enum {\n@@ -357,6 +358,7 @@ enum {\n \tNAPI_STATE_LISTED,\t/* NAPI added to system lists */\n \tNAPI_STATE_NO_BUSY_POLL,/* Do not add in napi_hash, no busy polling */\n \tNAPI_STATE_IN_BUSY_POLL,/* sk_busy_loop() owns this NAPI */\n+\tNAPI_STATE_THREADED,\t\t/* The poll is performed inside its own thread*/\n };\n \n enum {\n@@ -367,6 +369,7 @@ enum {\n \tNAPIF_STATE_LISTED\t = BIT(NAPI_STATE_LISTED),\n \tNAPIF_STATE_NO_BUSY_POLL = BIT(NAPI_STATE_NO_BUSY_POLL),\n \tNAPIF_STATE_IN_BUSY_POLL = BIT(NAPI_STATE_IN_BUSY_POLL),\n+\tNAPIF_STATE_THREADED\t = BIT(NAPI_STATE_THREADED),\n };\n \n enum gro_result {\n@@ -497,20 +500,7 @@ static inline bool napi_complete(struct\n  */\n void napi_disable(struct napi_struct *n);\n \n-/**\n- *\tnapi_enable - enable NAPI scheduling\n- *\t@n: NAPI context\n- *\n- * Resume NAPI from being scheduled on this context.\n- * Must be paired with napi_disable.\n- */\n-static inline void napi_enable(struct napi_struct *n)\n-{\n-\tBUG_ON(!test_bit(NAPI_STATE_SCHED, &n->state));\n-\tsmp_mb__before_atomic();\n-\tclear_bit(NAPI_STATE_SCHED, &n->state);\n-\tclear_bit(NAPI_STATE_NPSVC, &n->state);\n-}\n+void napi_enable(struct napi_struct *n);\n \n /**\n  *\tnapi_synchronize - wait until NAPI is not running\n@@ -1842,6 +1832,8 @@ enum netdev_ml_priv_type {\n  *\n  *\t@wol_enabled:\tWake-on-LAN is enabled\n  *\n+ *\t@threaded:\tnapi threaded mode is enabled\n+ *\n  *\t@net_notifier_list:\tList of per-net netdev notifier block\n  *\t\t\t\tthat follow this device when it is moved\n  *\t\t\t\tto another network namespace.\n@@ -2161,6 +2153,7 @@ struct net_device {\n \tstruct lock_class_key\t*qdisc_running_key;\n \tbool\t\t\tproto_down;\n \tunsigned\t\twol_enabled:1;\n+\tunsigned\t\tthreaded:1;\n \n \tstruct list_head\tnet_notifier_list;\n \n--- a/net/core/dev.c\n+++ b/net/core/dev.c\n@@ -91,6 +91,7 @@\n #include <linux/etherdevice.h>\n #include <linux/ethtool.h>\n #include <linux/skbuff.h>\n+#include <linux/kthread.h>\n #include <linux/bpf.h>\n #include <linux/bpf_trace.h>\n #include <net/net_namespace.h>\n@@ -1500,6 +1501,27 @@ void netdev_notify_peers(struct net_devi\n }\n EXPORT_SYMBOL(netdev_notify_peers);\n \n+static int napi_threaded_poll(void *data);\n+\n+static int napi_kthread_create(struct napi_struct *n)\n+{\n+\tint err = 0;\n+\n+\t/* Create and wake up the kthread once to put it in\n+\t * TASK_INTERRUPTIBLE mode to avoid the blocked task\n+\t * warning and work with loadavg.\n+\t */\n+\tn->thread = kthread_run(napi_threaded_poll, n, \"napi/%s-%d\",\n+\t\t\t\tn->dev->name, n->napi_id);\n+\tif (IS_ERR(n->thread)) {\n+\t\terr = PTR_ERR(n->thread);\n+\t\tpr_err(\"kthread_run failed with err %d\\n\", err);\n+\t\tn->thread = NULL;\n+\t}\n+\n+\treturn err;\n+}\n+\n static int __dev_open(struct net_device *dev, struct netlink_ext_ack *extack)\n {\n \tconst struct net_device_ops *ops = dev->netdev_ops;\n@@ -4267,6 +4289,21 @@ int gro_normal_batch __read_mostly = 8;\n static inline void ____napi_schedule(struct softnet_data *sd,\n \t\t\t\t     struct napi_struct *napi)\n {\n+\tstruct task_struct *thread;\n+\n+\tif (test_bit(NAPI_STATE_THREADED, &napi->state)) {\n+\t\t/* Paired with smp_mb__before_atomic() in\n+\t\t * napi_enable(). Use READ_ONCE() to guarantee\n+\t\t * a complete read on napi->thread. Only call\n+\t\t * wake_up_process() when it's not NULL.\n+\t\t */\n+\t\tthread = READ_ONCE(napi->thread);\n+\t\tif (thread) {\n+\t\t\twake_up_process(thread);\n+\t\t\treturn;\n+\t\t}\n+\t}\n+\n \tlist_add_tail(&napi->poll_list, &sd->poll_list);\n \t__raise_softirq_irqoff(NET_RX_SOFTIRQ);\n }\n@@ -6758,6 +6795,12 @@ void netif_napi_add(struct net_device *d\n \tset_bit(NAPI_STATE_NPSVC, &napi->state);\n \tlist_add_rcu(&napi->dev_list, &dev->napi_list);\n \tnapi_hash_add(napi);\n+\t/* Create kthread for this napi if dev->threaded is set.\n+\t * Clear dev->threaded if kthread creation failed so that\n+\t * threaded mode will not be enabled in napi_enable().\n+\t */\n+\tif (dev->threaded && napi_kthread_create(napi))\n+\t\tdev->threaded = 0;\n }\n EXPORT_SYMBOL(netif_napi_add);\n \n@@ -6774,9 +6817,28 @@ void napi_disable(struct napi_struct *n)\n \thrtimer_cancel(&n->timer);\n \n \tclear_bit(NAPI_STATE_DISABLE, &n->state);\n+\tclear_bit(NAPI_STATE_THREADED, &n->state);\n }\n EXPORT_SYMBOL(napi_disable);\n \n+/**\n+ *\tnapi_enable - enable NAPI scheduling\n+ *\t@n: NAPI context\n+ *\n+ * Resume NAPI from being scheduled on this context.\n+ * Must be paired with napi_disable.\n+ */\n+void napi_enable(struct napi_struct *n)\n+{\n+\tBUG_ON(!test_bit(NAPI_STATE_SCHED, &n->state));\n+\tsmp_mb__before_atomic();\n+\tclear_bit(NAPI_STATE_SCHED, &n->state);\n+\tclear_bit(NAPI_STATE_NPSVC, &n->state);\n+\tif (n->dev->threaded && n->thread)\n+\t\tset_bit(NAPI_STATE_THREADED, &n->state);\n+}\n+EXPORT_SYMBOL(napi_enable);\n+\n static void flush_gro_hash(struct napi_struct *napi)\n {\n \tint i;\n@@ -6802,6 +6864,11 @@ void __netif_napi_del(struct napi_struct\n \n \tflush_gro_hash(napi);\n \tnapi->gro_bitmask = 0;\n+\n+\tif (napi->thread) {\n+\t\tkthread_stop(napi->thread);\n+\t\tnapi->thread = NULL;\n+\t}\n }\n EXPORT_SYMBOL(__netif_napi_del);\n \n@@ -6883,6 +6950,51 @@ static int napi_poll(struct napi_struct\n \treturn work;\n }\n \n+static int napi_thread_wait(struct napi_struct *napi)\n+{\n+\tset_current_state(TASK_INTERRUPTIBLE);\n+\n+\twhile (!kthread_should_stop() && !napi_disable_pending(napi)) {\n+\t\tif (test_bit(NAPI_STATE_SCHED, &napi->state)) {\n+\t\t\tWARN_ON(!list_empty(&napi->poll_list));\n+\t\t\t__set_current_state(TASK_RUNNING);\n+\t\t\treturn 0;\n+\t\t}\n+\n+\t\tschedule();\n+\t\tset_current_state(TASK_INTERRUPTIBLE);\n+\t}\n+\t__set_current_state(TASK_RUNNING);\n+\treturn -1;\n+}\n+\n+static int napi_threaded_poll(void *data)\n+{\n+\tstruct napi_struct *napi = data;\n+\tvoid *have;\n+\n+\twhile (!napi_thread_wait(napi)) {\n+\t\tfor (;;) {\n+\t\t\tbool repoll = false;\n+\n+\t\t\tlocal_bh_disable();\n+\n+\t\t\thave = netpoll_poll_lock(napi);\n+\t\t\t__napi_poll(napi, &repoll);\n+\t\t\tnetpoll_poll_unlock(have);\n+\n+\t\t\t__kfree_skb_flush();\n+\t\t\tlocal_bh_enable();\n+\n+\t\t\tif (!repoll)\n+\t\t\t\tbreak;\n+\n+\t\t\tcond_resched();\n+\t\t}\n+\t}\n+\treturn 0;\n+}\n+\n static __latent_entropy void net_rx_action(struct softirq_action *h)\n {\n \tstruct softnet_data *sd = this_cpu_ptr(&softnet_data);\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/602-v5.12-net-add-sysfs-attribute-to-control-napi-threaded-mod.patch",
    "content": "From: Wei Wang <weiwan@google.com>\nDate: Mon, 8 Feb 2021 11:34:10 -0800\nSubject: [PATCH] net: add sysfs attribute to control napi threaded mode\n\nThis patch adds a new sysfs attribute to the network device class.\nSaid attribute provides a per-device control to enable/disable the\nthreaded mode for all the napi instances of the given network device,\nwithout the need for a device up/down.\nUser sets it to 1 or 0 to enable or disable threaded mode.\nNote: when switching between threaded and the current softirq based mode\nfor a napi instance, it will not immediately take effect if the napi is\ncurrently being polled. The mode switch will happen for the next time\nnapi_schedule() is called.\n\nCo-developed-by: Paolo Abeni <pabeni@redhat.com>\nSigned-off-by: Paolo Abeni <pabeni@redhat.com>\nCo-developed-by: Hannes Frederic Sowa <hannes@stressinduktion.org>\nSigned-off-by: Hannes Frederic Sowa <hannes@stressinduktion.org>\nCo-developed-by: Felix Fietkau <nbd@nbd.name>\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\nSigned-off-by: Wei Wang <weiwan@google.com>\nReviewed-by: Alexander Duyck <alexanderduyck@fb.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n\n--- a/Documentation/ABI/testing/sysfs-class-net\n+++ b/Documentation/ABI/testing/sysfs-class-net\n@@ -337,3 +337,18 @@ Contact:\tnetdev@vger.kernel.org\n Description:\n \t\t32-bit unsigned integer counting the number of times the link has\n \t\tbeen down\n+\n+What:\t\t/sys/class/net/<iface>/threaded\n+Date:\t\tJan 2021\n+KernelVersion:\t5.12\n+Contact:\tnetdev@vger.kernel.org\n+Description:\n+\t\tBoolean value to control the threaded mode per device. User could\n+\t\tset this value to enable/disable threaded mode for all napi\n+\t\tbelonging to this device, without the need to do device up/down.\n+\n+\t\tPossible values:\n+\t\t== ==================================\n+\t\t0  threaded mode disabled for this dev\n+\t\t1  threaded mode enabled for this dev\n+\t\t== ==================================\n--- a/include/linux/netdevice.h\n+++ b/include/linux/netdevice.h\n@@ -491,6 +491,8 @@ static inline bool napi_complete(struct\n \treturn napi_complete_done(n, 0);\n }\n \n+int dev_set_threaded(struct net_device *dev, bool threaded);\n+\n /**\n  *\tnapi_disable - prevent NAPI from scheduling\n  *\t@n: NAPI context\n--- a/net/core/dev.c\n+++ b/net/core/dev.c\n@@ -4293,8 +4293,9 @@ static inline void ____napi_schedule(str\n \n \tif (test_bit(NAPI_STATE_THREADED, &napi->state)) {\n \t\t/* Paired with smp_mb__before_atomic() in\n-\t\t * napi_enable(). Use READ_ONCE() to guarantee\n-\t\t * a complete read on napi->thread. Only call\n+\t\t * napi_enable()/dev_set_threaded().\n+\t\t * Use READ_ONCE() to guarantee a complete\n+\t\t * read on napi->thread. Only call\n \t\t * wake_up_process() when it's not NULL.\n \t\t */\n \t\tthread = READ_ONCE(napi->thread);\n@@ -6768,6 +6769,49 @@ static void init_gro_hash(struct napi_st\n \tnapi->gro_bitmask = 0;\n }\n \n+int dev_set_threaded(struct net_device *dev, bool threaded)\n+{\n+\tstruct napi_struct *napi;\n+\tint err = 0;\n+\n+\tif (dev->threaded == threaded)\n+\t\treturn 0;\n+\n+\tif (threaded) {\n+\t\tlist_for_each_entry(napi, &dev->napi_list, dev_list) {\n+\t\t\tif (!napi->thread) {\n+\t\t\t\terr = napi_kthread_create(napi);\n+\t\t\t\tif (err) {\n+\t\t\t\t\tthreaded = false;\n+\t\t\t\t\tbreak;\n+\t\t\t\t}\n+\t\t\t}\n+\t\t}\n+\t}\n+\n+\tdev->threaded = threaded;\n+\n+\t/* Make sure kthread is created before THREADED bit\n+\t * is set.\n+\t */\n+\tsmp_mb__before_atomic();\n+\n+\t/* Setting/unsetting threaded mode on a napi might not immediately\n+\t * take effect, if the current napi instance is actively being\n+\t * polled. In this case, the switch between threaded mode and\n+\t * softirq mode will happen in the next round of napi_schedule().\n+\t * This should not cause hiccups/stalls to the live traffic.\n+\t */\n+\tlist_for_each_entry(napi, &dev->napi_list, dev_list) {\n+\t\tif (threaded)\n+\t\t\tset_bit(NAPI_STATE_THREADED, &napi->state);\n+\t\telse\n+\t\t\tclear_bit(NAPI_STATE_THREADED, &napi->state);\n+\t}\n+\n+\treturn err;\n+}\n+\n void netif_napi_add(struct net_device *dev, struct napi_struct *napi,\n \t\t    int (*poll)(struct napi_struct *, int), int weight)\n {\n--- a/net/core/net-sysfs.c\n+++ b/net/core/net-sysfs.c\n@@ -587,6 +587,45 @@ static ssize_t phys_switch_id_show(struc\n }\n static DEVICE_ATTR_RO(phys_switch_id);\n \n+static ssize_t threaded_show(struct device *dev,\n+\t\t\t     struct device_attribute *attr, char *buf)\n+{\n+\tstruct net_device *netdev = to_net_dev(dev);\n+\tssize_t ret = -EINVAL;\n+\n+\tif (!rtnl_trylock())\n+\t\treturn restart_syscall();\n+\n+\tif (dev_isalive(netdev))\n+\t\tret = sprintf(buf, fmt_dec, netdev->threaded);\n+\n+\trtnl_unlock();\n+\treturn ret;\n+}\n+\n+static int modify_napi_threaded(struct net_device *dev, unsigned long val)\n+{\n+\tint ret;\n+\n+\tif (list_empty(&dev->napi_list))\n+\t\treturn -EOPNOTSUPP;\n+\n+\tif (val != 0 && val != 1)\n+\t\treturn -EOPNOTSUPP;\n+\n+\tret = dev_set_threaded(dev, val);\n+\n+\treturn ret;\n+}\n+\n+static ssize_t threaded_store(struct device *dev,\n+\t\t\t      struct device_attribute *attr,\n+\t\t\t      const char *buf, size_t len)\n+{\n+\treturn netdev_store(dev, attr, buf, len, modify_napi_threaded);\n+}\n+static DEVICE_ATTR_RW(threaded);\n+\n static struct attribute *net_class_attrs[] __ro_after_init = {\n \t&dev_attr_netdev_group.attr,\n \t&dev_attr_type.attr,\n@@ -619,6 +658,7 @@ static struct attribute *net_class_attrs\n \t&dev_attr_proto_down.attr,\n \t&dev_attr_carrier_up_count.attr,\n \t&dev_attr_carrier_down_count.attr,\n+\t&dev_attr_threaded.attr,\n \tNULL,\n };\n ATTRIBUTE_GROUPS(net_class);\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/603-v5.12-net-fix-race-between-napi-kthread-mode-and-busy-poll.patch",
    "content": "From: Wei Wang <weiwan@google.com>\nDate: Mon, 1 Mar 2021 17:21:13 -0800\nSubject: [PATCH] net: fix race between napi kthread mode and busy poll\n\nCurrently, napi_thread_wait() checks for NAPI_STATE_SCHED bit to\ndetermine if the kthread owns this napi and could call napi->poll() on\nit. However, if socket busy poll is enabled, it is possible that the\nbusy poll thread grabs this SCHED bit (after the previous napi->poll()\ninvokes napi_complete_done() and clears SCHED bit) and tries to poll\non the same napi. napi_disable() could grab the SCHED bit as well.\nThis patch tries to fix this race by adding a new bit\nNAPI_STATE_SCHED_THREADED in napi->state. This bit gets set in\n____napi_schedule() if the threaded mode is enabled, and gets cleared\nin napi_complete_done(), and we only poll the napi in kthread if this\nbit is set. This helps distinguish the ownership of the napi between\nkthread and other scenarios and fixes the race issue.\n\nFixes: 29863d41bb6e (\"net: implement threaded-able napi poll loop support\")\nReported-by: Martin Zaharinov <micron10@gmail.com>\nSuggested-by: Jakub Kicinski <kuba@kernel.org>\nSigned-off-by: Wei Wang <weiwan@google.com>\nCc: Alexander Duyck <alexanderduyck@fb.com>\nCc: Eric Dumazet <edumazet@google.com>\nCc: Paolo Abeni <pabeni@redhat.com>\nCc: Hannes Frederic Sowa <hannes@stressinduktion.org>\n---\n\n--- a/include/linux/netdevice.h\n+++ b/include/linux/netdevice.h\n@@ -359,6 +359,7 @@ enum {\n \tNAPI_STATE_NO_BUSY_POLL,/* Do not add in napi_hash, no busy polling */\n \tNAPI_STATE_IN_BUSY_POLL,/* sk_busy_loop() owns this NAPI */\n \tNAPI_STATE_THREADED,\t\t/* The poll is performed inside its own thread*/\n+\tNAPI_STATE_SCHED_THREADED,\t/* Napi is currently scheduled in threaded mode */\n };\n \n enum {\n@@ -370,6 +371,7 @@ enum {\n \tNAPIF_STATE_NO_BUSY_POLL = BIT(NAPI_STATE_NO_BUSY_POLL),\n \tNAPIF_STATE_IN_BUSY_POLL = BIT(NAPI_STATE_IN_BUSY_POLL),\n \tNAPIF_STATE_THREADED\t = BIT(NAPI_STATE_THREADED),\n+\tNAPIF_STATE_SCHED_THREADED\t= BIT(NAPI_STATE_SCHED_THREADED),\n };\n \n enum gro_result {\n--- a/net/core/dev.c\n+++ b/net/core/dev.c\n@@ -4300,6 +4300,8 @@ static inline void ____napi_schedule(str\n \t\t */\n \t\tthread = READ_ONCE(napi->thread);\n \t\tif (thread) {\n+\t\t\tif (thread->state != TASK_INTERRUPTIBLE)\n+\t\t\t\tset_bit(NAPI_STATE_SCHED_THREADED, &napi->state);\n \t\t\twake_up_process(thread);\n \t\t\treturn;\n \t\t}\n@@ -6560,7 +6562,8 @@ bool napi_complete_done(struct napi_stru\n \n \t\tWARN_ON_ONCE(!(val & NAPIF_STATE_SCHED));\n \n-\t\tnew = val & ~(NAPIF_STATE_MISSED | NAPIF_STATE_SCHED);\n+\t\tnew = val & ~(NAPIF_STATE_MISSED | NAPIF_STATE_SCHED |\n+\t\t\t      NAPIF_STATE_SCHED_THREADED);\n \n \t\t/* If STATE_MISSED was set, leave STATE_SCHED set,\n \t\t * because we will call napi->poll() one more time.\n@@ -6996,16 +6999,25 @@ static int napi_poll(struct napi_struct\n \n static int napi_thread_wait(struct napi_struct *napi)\n {\n+\tbool woken = false;\n+\n \tset_current_state(TASK_INTERRUPTIBLE);\n \n \twhile (!kthread_should_stop() && !napi_disable_pending(napi)) {\n-\t\tif (test_bit(NAPI_STATE_SCHED, &napi->state)) {\n+\t\t/* Testing SCHED_THREADED bit here to make sure the current\n+\t\t * kthread owns this napi and could poll on this napi.\n+\t\t * Testing SCHED bit is not enough because SCHED bit might be\n+\t\t * set by some other busy poll thread or by napi_disable().\n+\t\t */\n+\t\tif (test_bit(NAPI_STATE_SCHED_THREADED, &napi->state) || woken) {\n \t\t\tWARN_ON(!list_empty(&napi->poll_list));\n \t\t\t__set_current_state(TASK_RUNNING);\n \t\t\treturn 0;\n \t\t}\n \n \t\tschedule();\n+\t\t/* woken being true indicates this thread owns this napi. */\n+\t\twoken = true;\n \t\tset_current_state(TASK_INTERRUPTIBLE);\n \t}\n \t__set_current_state(TASK_RUNNING);\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/604-v5.12-net-fix-hangup-on-napi_disable-for-threaded-napi.patch",
    "content": "From: Paolo Abeni <pabeni@redhat.com>\nDate: Fri, 9 Apr 2021 17:24:17 +0200\nSubject: [PATCH] net: fix hangup on napi_disable for threaded napi\n\nnapi_disable() is subject to an hangup, when the threaded\nmode is enabled and the napi is under heavy traffic.\n\nIf the relevant napi has been scheduled and the napi_disable()\nkicks in before the next napi_threaded_wait() completes - so\nthat the latter quits due to the napi_disable_pending() condition,\nthe existing code leaves the NAPI_STATE_SCHED bit set and the\nnapi_disable() loop waiting for such bit will hang.\n\nThis patch addresses the issue by dropping the NAPI_STATE_DISABLE\nbit test in napi_thread_wait(). The later napi_threaded_poll()\niteration will take care of clearing the NAPI_STATE_SCHED.\n\nThis also addresses a related problem reported by Jakub:\nbefore this patch a napi_disable()/napi_enable() pair killed\nthe napi thread, effectively disabling the threaded mode.\nOn the patched kernel napi_disable() simply stops scheduling\nthe relevant thread.\n\nv1 -> v2:\n  - let the main napi_thread_poll() loop clear the SCHED bit\n\nReported-by: Jakub Kicinski <kuba@kernel.org>\nFixes: 29863d41bb6e (\"net: implement threaded-able napi poll loop support\")\nSigned-off-by: Paolo Abeni <pabeni@redhat.com>\nReviewed-by: Eric Dumazet <edumazet@google.com>\nLink: https://lore.kernel.org/r/883923fa22745a9589e8610962b7dc59df09fb1f.1617981844.git.pabeni@redhat.com\nSigned-off-by: Jakub Kicinski <kuba@kernel.org>\n---\n\n--- a/net/core/dev.c\n+++ b/net/core/dev.c\n@@ -7003,7 +7003,7 @@ static int napi_thread_wait(struct napi_\n \n \tset_current_state(TASK_INTERRUPTIBLE);\n \n-\twhile (!kthread_should_stop() && !napi_disable_pending(napi)) {\n+\twhile (!kthread_should_stop()) {\n \t\t/* Testing SCHED_THREADED bit here to make sure the current\n \t\t * kthread owns this napi and could poll on this napi.\n \t\t * Testing SCHED bit is not enough because SCHED bit might be\n@@ -7021,6 +7021,7 @@ static int napi_thread_wait(struct napi_\n \t\tset_current_state(TASK_INTERRUPTIBLE);\n \t}\n \t__set_current_state(TASK_RUNNING);\n+\n \treturn -1;\n }\n \n"
  },
  {
    "path": "target/linux/generic/backport-5.10/610-v5.13-00-netfilter-flowtable-add-hash-offset-field-to-tuple.patch",
    "content": "From: Pablo Neira Ayuso <pablo@netfilter.org>\nDate: Fri, 20 Nov 2020 13:49:13 +0100\nSubject: [PATCH] netfilter: flowtable: add hash offset field to tuple\n\nAdd a placeholder field to calculate hash tuple offset. Similar to\n2c407aca6497 (\"netfilter: conntrack: avoid gcc-10 zero-length-bounds\nwarning\").\n\nSigned-off-by: Pablo Neira Ayuso <pablo@netfilter.org>\n---\n\n--- a/include/net/netfilter/nf_flow_table.h\n+++ b/include/net/netfilter/nf_flow_table.h\n@@ -107,6 +107,10 @@ struct flow_offload_tuple {\n \n \tu8\t\t\t\tl3proto;\n \tu8\t\t\t\tl4proto;\n+\n+\t/* All members above are keys for lookups, see flow_offload_hash(). */\n+\tstruct { }\t\t\t__hash;\n+\n \tu8\t\t\t\tdir;\n \n \tu16\t\t\t\tmtu;\n--- a/net/netfilter/nf_flow_table_core.c\n+++ b/net/netfilter/nf_flow_table_core.c\n@@ -191,14 +191,14 @@ static u32 flow_offload_hash(const void\n {\n \tconst struct flow_offload_tuple *tuple = data;\n \n-\treturn jhash(tuple, offsetof(struct flow_offload_tuple, dir), seed);\n+\treturn jhash(tuple, offsetof(struct flow_offload_tuple, __hash), seed);\n }\n \n static u32 flow_offload_hash_obj(const void *data, u32 len, u32 seed)\n {\n \tconst struct flow_offload_tuple_rhash *tuplehash = data;\n \n-\treturn jhash(&tuplehash->tuple, offsetof(struct flow_offload_tuple, dir), seed);\n+\treturn jhash(&tuplehash->tuple, offsetof(struct flow_offload_tuple, __hash), seed);\n }\n \n static int flow_offload_hash_cmp(struct rhashtable_compare_arg *arg,\n@@ -207,7 +207,7 @@ static int flow_offload_hash_cmp(struct\n \tconst struct flow_offload_tuple *tuple = arg->key;\n \tconst struct flow_offload_tuple_rhash *x = ptr;\n \n-\tif (memcmp(&x->tuple, tuple, offsetof(struct flow_offload_tuple, dir)))\n+\tif (memcmp(&x->tuple, tuple, offsetof(struct flow_offload_tuple, __hash)))\n \t\treturn 1;\n \n \treturn 0;\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/610-v5.13-01-netfilter-flowtable-separate-replace-destroy-and-sta.patch",
    "content": "From: Oz Shlomo <ozsh@nvidia.com>\nDate: Tue, 23 Mar 2021 00:56:19 +0100\nSubject: [PATCH] netfilter: flowtable: separate replace, destroy and\n stats to different workqueues\n\nCurrently the flow table offload replace, destroy and stats work items are\nexecuted on a single workqueue. As such, DESTROY and STATS commands may\nbe backloged after a burst of REPLACE work items. This scenario can bloat\nup memory and may cause active connections to age.\n\nInstatiate add, del and stats workqueues to avoid backlogs of non-dependent\nactions. Provide sysfs control over the workqueue attributes, allowing\nuserspace applications to control the workqueue cpumask.\n\nSigned-off-by: Oz Shlomo <ozsh@nvidia.com>\nReviewed-by: Paul Blakey <paulb@nvidia.com>\nSigned-off-by: Pablo Neira Ayuso <pablo@netfilter.org>\n---\n\n--- a/net/netfilter/nf_flow_table_offload.c\n+++ b/net/netfilter/nf_flow_table_offload.c\n@@ -13,7 +13,9 @@\n #include <net/netfilter/nf_conntrack_core.h>\n #include <net/netfilter/nf_conntrack_tuple.h>\n \n-static struct workqueue_struct *nf_flow_offload_wq;\n+static struct workqueue_struct *nf_flow_offload_add_wq;\n+static struct workqueue_struct *nf_flow_offload_del_wq;\n+static struct workqueue_struct *nf_flow_offload_stats_wq;\n \n struct flow_offload_work {\n \tstruct list_head\tlist;\n@@ -827,7 +829,12 @@ static void flow_offload_work_handler(st\n \n static void flow_offload_queue_work(struct flow_offload_work *offload)\n {\n-\tqueue_work(nf_flow_offload_wq, &offload->work);\n+\tif (offload->cmd == FLOW_CLS_REPLACE)\n+\t\tqueue_work(nf_flow_offload_add_wq, &offload->work);\n+\telse if (offload->cmd == FLOW_CLS_DESTROY)\n+\t\tqueue_work(nf_flow_offload_del_wq, &offload->work);\n+\telse\n+\t\tqueue_work(nf_flow_offload_stats_wq, &offload->work);\n }\n \n static struct flow_offload_work *\n@@ -899,8 +906,11 @@ void nf_flow_offload_stats(struct nf_flo\n \n void nf_flow_table_offload_flush(struct nf_flowtable *flowtable)\n {\n-\tif (nf_flowtable_hw_offload(flowtable))\n-\t\tflush_workqueue(nf_flow_offload_wq);\n+\tif (nf_flowtable_hw_offload(flowtable)) {\n+\t\tflush_workqueue(nf_flow_offload_add_wq);\n+\t\tflush_workqueue(nf_flow_offload_del_wq);\n+\t\tflush_workqueue(nf_flow_offload_stats_wq);\n+\t}\n }\n \n static int nf_flow_table_block_setup(struct nf_flowtable *flowtable,\n@@ -1013,15 +1023,33 @@ EXPORT_SYMBOL_GPL(nf_flow_table_offload_\n \n int nf_flow_table_offload_init(void)\n {\n-\tnf_flow_offload_wq  = alloc_workqueue(\"nf_flow_table_offload\",\n-\t\t\t\t\t      WQ_UNBOUND, 0);\n-\tif (!nf_flow_offload_wq)\n+\tnf_flow_offload_add_wq  = alloc_workqueue(\"nf_ft_offload_add\",\n+\t\t\t\t\t\t  WQ_UNBOUND | WQ_SYSFS, 0);\n+\tif (!nf_flow_offload_add_wq)\n \t\treturn -ENOMEM;\n \n+\tnf_flow_offload_del_wq  = alloc_workqueue(\"nf_ft_offload_del\",\n+\t\t\t\t\t\t  WQ_UNBOUND | WQ_SYSFS, 0);\n+\tif (!nf_flow_offload_del_wq)\n+\t\tgoto err_del_wq;\n+\n+\tnf_flow_offload_stats_wq  = alloc_workqueue(\"nf_ft_offload_stats\",\n+\t\t\t\t\t\t    WQ_UNBOUND | WQ_SYSFS, 0);\n+\tif (!nf_flow_offload_stats_wq)\n+\t\tgoto err_stats_wq;\n+\n \treturn 0;\n+\n+err_stats_wq:\n+\tdestroy_workqueue(nf_flow_offload_del_wq);\n+err_del_wq:\n+\tdestroy_workqueue(nf_flow_offload_add_wq);\n+\treturn -ENOMEM;\n }\n \n void nf_flow_table_offload_exit(void)\n {\n-\tdestroy_workqueue(nf_flow_offload_wq);\n+\tdestroy_workqueue(nf_flow_offload_add_wq);\n+\tdestroy_workqueue(nf_flow_offload_del_wq);\n+\tdestroy_workqueue(nf_flow_offload_stats_wq);\n }\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/610-v5.13-03-netfilter-conntrack-Remove-unused-variable-declarati.patch",
    "content": "From: YueHaibing <yuehaibing@huawei.com>\nDate: Tue, 23 Mar 2021 00:56:21 +0100\nSubject: [PATCH] netfilter: conntrack: Remove unused variable\n declaration\n\ncommit e97c3e278e95 (\"tproxy: split off ipv6 defragmentation to a separate\nmodule\") left behind this.\n\nSigned-off-by: YueHaibing <yuehaibing@huawei.com>\nSigned-off-by: Pablo Neira Ayuso <pablo@netfilter.org>\n---\n\n--- a/include/net/netfilter/ipv6/nf_conntrack_ipv6.h\n+++ b/include/net/netfilter/ipv6/nf_conntrack_ipv6.h\n@@ -4,7 +4,4 @@\n \n extern const struct nf_conntrack_l4proto nf_conntrack_l4proto_icmpv6;\n \n-#include <linux/sysctl.h>\n-extern struct ctl_table nf_ct_ipv6_sysctl_table[];\n-\n #endif /* _NF_CONNTRACK_IPV6_H*/\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/610-v5.13-04-netfilter-flowtable-consolidate-skb_try_make_writabl.patch",
    "content": "From: Pablo Neira Ayuso <pablo@netfilter.org>\nDate: Tue, 23 Mar 2021 00:56:22 +0100\nSubject: [PATCH] netfilter: flowtable: consolidate\n skb_try_make_writable() call\n\nFetch the layer 4 header size to be mangled by NAT when building the\ntuple, then use it to make writable the network and the transport\nheaders. After this update, the NAT routines now assumes that the skbuff\narea is writable. Do the pointer refetch only after the single\nskb_try_make_writable() call.\n\nSigned-off-by: Pablo Neira Ayuso <pablo@netfilter.org>\n---\n\n--- a/net/netfilter/nf_flow_table_core.c\n+++ b/net/netfilter/nf_flow_table_core.c\n@@ -394,9 +394,6 @@ static int nf_flow_nat_port_tcp(struct s\n {\n \tstruct tcphdr *tcph;\n \n-\tif (skb_try_make_writable(skb, thoff + sizeof(*tcph)))\n-\t\treturn -1;\n-\n \ttcph = (void *)(skb_network_header(skb) + thoff);\n \tinet_proto_csum_replace2(&tcph->check, skb, port, new_port, false);\n \n@@ -408,9 +405,6 @@ static int nf_flow_nat_port_udp(struct s\n {\n \tstruct udphdr *udph;\n \n-\tif (skb_try_make_writable(skb, thoff + sizeof(*udph)))\n-\t\treturn -1;\n-\n \tudph = (void *)(skb_network_header(skb) + thoff);\n \tif (udph->check || skb->ip_summed == CHECKSUM_PARTIAL) {\n \t\tinet_proto_csum_replace2(&udph->check, skb, port,\n@@ -446,9 +440,6 @@ int nf_flow_snat_port(const struct flow_\n \tstruct flow_ports *hdr;\n \t__be16 port, new_port;\n \n-\tif (skb_try_make_writable(skb, thoff + sizeof(*hdr)))\n-\t\treturn -1;\n-\n \thdr = (void *)(skb_network_header(skb) + thoff);\n \n \tswitch (dir) {\n@@ -477,9 +468,6 @@ int nf_flow_dnat_port(const struct flow_\n \tstruct flow_ports *hdr;\n \t__be16 port, new_port;\n \n-\tif (skb_try_make_writable(skb, thoff + sizeof(*hdr)))\n-\t\treturn -1;\n-\n \thdr = (void *)(skb_network_header(skb) + thoff);\n \n \tswitch (dir) {\n--- a/net/netfilter/nf_flow_table_ip.c\n+++ b/net/netfilter/nf_flow_table_ip.c\n@@ -39,9 +39,6 @@ static int nf_flow_nat_ip_tcp(struct sk_\n {\n \tstruct tcphdr *tcph;\n \n-\tif (skb_try_make_writable(skb, thoff + sizeof(*tcph)))\n-\t\treturn -1;\n-\n \ttcph = (void *)(skb_network_header(skb) + thoff);\n \tinet_proto_csum_replace4(&tcph->check, skb, addr, new_addr, true);\n \n@@ -53,9 +50,6 @@ static int nf_flow_nat_ip_udp(struct sk_\n {\n \tstruct udphdr *udph;\n \n-\tif (skb_try_make_writable(skb, thoff + sizeof(*udph)))\n-\t\treturn -1;\n-\n \tudph = (void *)(skb_network_header(skb) + thoff);\n \tif (udph->check || skb->ip_summed == CHECKSUM_PARTIAL) {\n \t\tinet_proto_csum_replace4(&udph->check, skb, addr,\n@@ -136,19 +130,17 @@ static int nf_flow_dnat_ip(const struct\n }\n \n static int nf_flow_nat_ip(const struct flow_offload *flow, struct sk_buff *skb,\n-\t\t\t  unsigned int thoff, enum flow_offload_tuple_dir dir)\n+\t\t\t  unsigned int thoff, enum flow_offload_tuple_dir dir,\n+\t\t\t  struct iphdr *iph)\n {\n-\tstruct iphdr *iph = ip_hdr(skb);\n-\n \tif (test_bit(NF_FLOW_SNAT, &flow->flags) &&\n \t    (nf_flow_snat_port(flow, skb, thoff, iph->protocol, dir) < 0 ||\n-\t     nf_flow_snat_ip(flow, skb, ip_hdr(skb), thoff, dir) < 0))\n+\t     nf_flow_snat_ip(flow, skb, iph, thoff, dir) < 0))\n \t\treturn -1;\n \n-\tiph = ip_hdr(skb);\n \tif (test_bit(NF_FLOW_DNAT, &flow->flags) &&\n \t    (nf_flow_dnat_port(flow, skb, thoff, iph->protocol, dir) < 0 ||\n-\t     nf_flow_dnat_ip(flow, skb, ip_hdr(skb), thoff, dir) < 0))\n+\t     nf_flow_dnat_ip(flow, skb, iph, thoff, dir) < 0))\n \t\treturn -1;\n \n \treturn 0;\n@@ -160,10 +152,10 @@ static bool ip_has_options(unsigned int\n }\n \n static int nf_flow_tuple_ip(struct sk_buff *skb, const struct net_device *dev,\n-\t\t\t    struct flow_offload_tuple *tuple)\n+\t\t\t    struct flow_offload_tuple *tuple, u32 *hdrsize)\n {\n-\tunsigned int thoff, hdrsize;\n \tstruct flow_ports *ports;\n+\tunsigned int thoff;\n \tstruct iphdr *iph;\n \n \tif (!pskb_may_pull(skb, sizeof(*iph)))\n@@ -178,10 +170,10 @@ static int nf_flow_tuple_ip(struct sk_bu\n \n \tswitch (iph->protocol) {\n \tcase IPPROTO_TCP:\n-\t\thdrsize = sizeof(struct tcphdr);\n+\t\t*hdrsize = sizeof(struct tcphdr);\n \t\tbreak;\n \tcase IPPROTO_UDP:\n-\t\thdrsize = sizeof(struct udphdr);\n+\t\t*hdrsize = sizeof(struct udphdr);\n \t\tbreak;\n \tdefault:\n \t\treturn -1;\n@@ -191,7 +183,7 @@ static int nf_flow_tuple_ip(struct sk_bu\n \t\treturn -1;\n \n \tthoff = iph->ihl * 4;\n-\tif (!pskb_may_pull(skb, thoff + hdrsize))\n+\tif (!pskb_may_pull(skb, thoff + *hdrsize))\n \t\treturn -1;\n \n \tiph = ip_hdr(skb);\n@@ -252,11 +244,12 @@ nf_flow_offload_ip_hook(void *priv, stru\n \tunsigned int thoff;\n \tstruct iphdr *iph;\n \t__be32 nexthop;\n+\tu32 hdrsize;\n \n \tif (skb->protocol != htons(ETH_P_IP))\n \t\treturn NF_ACCEPT;\n \n-\tif (nf_flow_tuple_ip(skb, state->in, &tuple) < 0)\n+\tif (nf_flow_tuple_ip(skb, state->in, &tuple, &hdrsize) < 0)\n \t\treturn NF_ACCEPT;\n \n \ttuplehash = flow_offload_lookup(flow_table, &tuple);\n@@ -271,11 +264,13 @@ nf_flow_offload_ip_hook(void *priv, stru\n \tif (unlikely(nf_flow_exceeds_mtu(skb, flow->tuplehash[dir].tuple.mtu)))\n \t\treturn NF_ACCEPT;\n \n-\tif (skb_try_make_writable(skb, sizeof(*iph)))\n+\tiph = ip_hdr(skb);\n+\tthoff = iph->ihl * 4;\n+\tif (skb_try_make_writable(skb, thoff + hdrsize))\n \t\treturn NF_DROP;\n \n-\tthoff = ip_hdr(skb)->ihl * 4;\n-\tif (nf_flow_state_check(flow, ip_hdr(skb)->protocol, skb, thoff))\n+\tiph = ip_hdr(skb);\n+\tif (nf_flow_state_check(flow, iph->protocol, skb, thoff))\n \t\treturn NF_ACCEPT;\n \n \tflow_offload_refresh(flow_table, flow);\n@@ -285,10 +280,9 @@ nf_flow_offload_ip_hook(void *priv, stru\n \t\treturn NF_ACCEPT;\n \t}\n \n-\tif (nf_flow_nat_ip(flow, skb, thoff, dir) < 0)\n+\tif (nf_flow_nat_ip(flow, skb, thoff, dir, iph) < 0)\n \t\treturn NF_DROP;\n \n-\tiph = ip_hdr(skb);\n \tip_decrease_ttl(iph);\n \tskb->tstamp = 0;\n \n@@ -317,9 +311,6 @@ static int nf_flow_nat_ipv6_tcp(struct s\n {\n \tstruct tcphdr *tcph;\n \n-\tif (skb_try_make_writable(skb, thoff + sizeof(*tcph)))\n-\t\treturn -1;\n-\n \ttcph = (void *)(skb_network_header(skb) + thoff);\n \tinet_proto_csum_replace16(&tcph->check, skb, addr->s6_addr32,\n \t\t\t\t  new_addr->s6_addr32, true);\n@@ -333,9 +324,6 @@ static int nf_flow_nat_ipv6_udp(struct s\n {\n \tstruct udphdr *udph;\n \n-\tif (skb_try_make_writable(skb, thoff + sizeof(*udph)))\n-\t\treturn -1;\n-\n \tudph = (void *)(skb_network_header(skb) + thoff);\n \tif (udph->check || skb->ip_summed == CHECKSUM_PARTIAL) {\n \t\tinet_proto_csum_replace16(&udph->check, skb, addr->s6_addr32,\n@@ -417,31 +405,30 @@ static int nf_flow_dnat_ipv6(const struc\n \n static int nf_flow_nat_ipv6(const struct flow_offload *flow,\n \t\t\t    struct sk_buff *skb,\n-\t\t\t    enum flow_offload_tuple_dir dir)\n+\t\t\t    enum flow_offload_tuple_dir dir,\n+\t\t\t    struct ipv6hdr *ip6h)\n {\n-\tstruct ipv6hdr *ip6h = ipv6_hdr(skb);\n \tunsigned int thoff = sizeof(*ip6h);\n \n \tif (test_bit(NF_FLOW_SNAT, &flow->flags) &&\n \t    (nf_flow_snat_port(flow, skb, thoff, ip6h->nexthdr, dir) < 0 ||\n-\t     nf_flow_snat_ipv6(flow, skb, ipv6_hdr(skb), thoff, dir) < 0))\n+\t     nf_flow_snat_ipv6(flow, skb, ip6h, thoff, dir) < 0))\n \t\treturn -1;\n \n-\tip6h = ipv6_hdr(skb);\n \tif (test_bit(NF_FLOW_DNAT, &flow->flags) &&\n \t    (nf_flow_dnat_port(flow, skb, thoff, ip6h->nexthdr, dir) < 0 ||\n-\t     nf_flow_dnat_ipv6(flow, skb, ipv6_hdr(skb), thoff, dir) < 0))\n+\t     nf_flow_dnat_ipv6(flow, skb, ip6h, thoff, dir) < 0))\n \t\treturn -1;\n \n \treturn 0;\n }\n \n static int nf_flow_tuple_ipv6(struct sk_buff *skb, const struct net_device *dev,\n-\t\t\t      struct flow_offload_tuple *tuple)\n+\t\t\t      struct flow_offload_tuple *tuple, u32 *hdrsize)\n {\n-\tunsigned int thoff, hdrsize;\n \tstruct flow_ports *ports;\n \tstruct ipv6hdr *ip6h;\n+\tunsigned int thoff;\n \n \tif (!pskb_may_pull(skb, sizeof(*ip6h)))\n \t\treturn -1;\n@@ -450,10 +437,10 @@ static int nf_flow_tuple_ipv6(struct sk_\n \n \tswitch (ip6h->nexthdr) {\n \tcase IPPROTO_TCP:\n-\t\thdrsize = sizeof(struct tcphdr);\n+\t\t*hdrsize = sizeof(struct tcphdr);\n \t\tbreak;\n \tcase IPPROTO_UDP:\n-\t\thdrsize = sizeof(struct udphdr);\n+\t\t*hdrsize = sizeof(struct udphdr);\n \t\tbreak;\n \tdefault:\n \t\treturn -1;\n@@ -463,7 +450,7 @@ static int nf_flow_tuple_ipv6(struct sk_\n \t\treturn -1;\n \n \tthoff = sizeof(*ip6h);\n-\tif (!pskb_may_pull(skb, thoff + hdrsize))\n+\tif (!pskb_may_pull(skb, thoff + *hdrsize))\n \t\treturn -1;\n \n \tip6h = ipv6_hdr(skb);\n@@ -493,11 +480,12 @@ nf_flow_offload_ipv6_hook(void *priv, st\n \tstruct net_device *outdev;\n \tstruct ipv6hdr *ip6h;\n \tstruct rt6_info *rt;\n+\tu32 hdrsize;\n \n \tif (skb->protocol != htons(ETH_P_IPV6))\n \t\treturn NF_ACCEPT;\n \n-\tif (nf_flow_tuple_ipv6(skb, state->in, &tuple) < 0)\n+\tif (nf_flow_tuple_ipv6(skb, state->in, &tuple, &hdrsize) < 0)\n \t\treturn NF_ACCEPT;\n \n \ttuplehash = flow_offload_lookup(flow_table, &tuple);\n@@ -523,13 +511,13 @@ nf_flow_offload_ipv6_hook(void *priv, st\n \t\treturn NF_ACCEPT;\n \t}\n \n-\tif (skb_try_make_writable(skb, sizeof(*ip6h)))\n+\tif (skb_try_make_writable(skb, sizeof(*ip6h) + hdrsize))\n \t\treturn NF_DROP;\n \n-\tif (nf_flow_nat_ipv6(flow, skb, dir) < 0)\n+\tip6h = ipv6_hdr(skb);\n+\tif (nf_flow_nat_ipv6(flow, skb, dir, ip6h) < 0)\n \t\treturn NF_DROP;\n \n-\tip6h = ipv6_hdr(skb);\n \tip6h->hop_limit--;\n \tskb->tstamp = 0;\n \n"
  },
  {
    "path": "target/linux/generic/backport-5.10/610-v5.13-05-netfilter-flowtable-move-skb_try_make_writable-befor.patch",
    "content": "From: Pablo Neira Ayuso <pablo@netfilter.org>\nDate: Tue, 23 Mar 2021 00:56:23 +0100\nSubject: [PATCH] netfilter: flowtable: move skb_try_make_writable()\n before NAT in IPv4\n\nFor consistency with the IPv6 flowtable datapath and to make sure the\nskbuff is writable right before the NAT header updates.\n\nSigned-off-by: Pablo Neira Ayuso <pablo@netfilter.org>\n---\n\n--- a/net/netfilter/nf_flow_table_ip.c\n+++ b/net/netfilter/nf_flow_table_ip.c\n@@ -266,10 +266,6 @@ nf_flow_offload_ip_hook(void *priv, stru\n \n \tiph = ip_hdr(skb);\n \tthoff = iph->ihl * 4;\n-\tif (skb_try_make_writable(skb, thoff + hdrsize))\n-\t\treturn NF_DROP;\n-\n-\tiph = ip_hdr(skb);\n \tif (nf_flow_state_check(flow, iph->protocol, skb, thoff))\n \t\treturn NF_ACCEPT;\n \n@@ -280,6 +276,10 @@ nf_flow_offload_ip_hook(void *priv, stru\n \t\treturn NF_ACCEPT;\n \t}\n \n+\tif (skb_try_make_writable(skb, thoff + hdrsize))\n+\t\treturn NF_DROP;\n+\n+\tiph = ip_hdr(skb);\n \tif (nf_flow_nat_ip(flow, skb, thoff, dir, iph) < 0)\n \t\treturn NF_DROP;\n \n"
  },
  {
    "path": "target/linux/generic/backport-5.10/610-v5.13-06-netfilter-flowtable-move-FLOW_OFFLOAD_DIR_MAX-away-f.patch",
    "content": "From: Pablo Neira Ayuso <pablo@netfilter.org>\nDate: Tue, 23 Mar 2021 00:56:24 +0100\nSubject: [PATCH] netfilter: flowtable: move FLOW_OFFLOAD_DIR_MAX away\n from enumeration\n\nThis allows to remove the default case which should not ever happen and\nthat was added to avoid gcc warnings on unhandled FLOW_OFFLOAD_DIR_MAX\nenumeration case.\n\nSigned-off-by: Pablo Neira Ayuso <pablo@netfilter.org>\n---\n\n--- a/include/net/netfilter/nf_flow_table.h\n+++ b/include/net/netfilter/nf_flow_table.h\n@@ -86,8 +86,8 @@ static inline bool nf_flowtable_hw_offlo\n enum flow_offload_tuple_dir {\n \tFLOW_OFFLOAD_DIR_ORIGINAL = IP_CT_DIR_ORIGINAL,\n \tFLOW_OFFLOAD_DIR_REPLY = IP_CT_DIR_REPLY,\n-\tFLOW_OFFLOAD_DIR_MAX = IP_CT_DIR_MAX\n };\n+#define FLOW_OFFLOAD_DIR_MAX\tIP_CT_DIR_MAX\n \n struct flow_offload_tuple {\n \tunion {\n--- a/net/netfilter/nf_flow_table_core.c\n+++ b/net/netfilter/nf_flow_table_core.c\n@@ -453,8 +453,6 @@ int nf_flow_snat_port(const struct flow_\n \t\tnew_port = flow->tuplehash[FLOW_OFFLOAD_DIR_ORIGINAL].tuple.src_port;\n \t\thdr->dest = new_port;\n \t\tbreak;\n-\tdefault:\n-\t\treturn -1;\n \t}\n \n \treturn nf_flow_nat_port(skb, thoff, protocol, port, new_port);\n@@ -481,8 +479,6 @@ int nf_flow_dnat_port(const struct flow_\n \t\tnew_port = flow->tuplehash[FLOW_OFFLOAD_DIR_ORIGINAL].tuple.dst_port;\n \t\thdr->source = new_port;\n \t\tbreak;\n-\tdefault:\n-\t\treturn -1;\n \t}\n \n \treturn nf_flow_nat_port(skb, thoff, protocol, port, new_port);\n--- a/net/netfilter/nf_flow_table_ip.c\n+++ b/net/netfilter/nf_flow_table_ip.c\n@@ -96,8 +96,6 @@ static int nf_flow_snat_ip(const struct\n \t\tnew_addr = flow->tuplehash[FLOW_OFFLOAD_DIR_ORIGINAL].tuple.src_v4.s_addr;\n \t\tiph->daddr = new_addr;\n \t\tbreak;\n-\tdefault:\n-\t\treturn -1;\n \t}\n \tcsum_replace4(&iph->check, addr, new_addr);\n \n@@ -121,8 +119,6 @@ static int nf_flow_dnat_ip(const struct\n \t\tnew_addr = flow->tuplehash[FLOW_OFFLOAD_DIR_ORIGINAL].tuple.dst_v4.s_addr;\n \t\tiph->saddr = new_addr;\n \t\tbreak;\n-\tdefault:\n-\t\treturn -1;\n \t}\n \tcsum_replace4(&iph->check, addr, new_addr);\n \n@@ -371,8 +367,6 @@ static int nf_flow_snat_ipv6(const struc\n \t\tnew_addr = flow->tuplehash[FLOW_OFFLOAD_DIR_ORIGINAL].tuple.src_v6;\n \t\tip6h->daddr = new_addr;\n \t\tbreak;\n-\tdefault:\n-\t\treturn -1;\n \t}\n \n \treturn nf_flow_nat_ipv6_l4proto(skb, ip6h, thoff, &addr, &new_addr);\n@@ -396,8 +390,6 @@ static int nf_flow_dnat_ipv6(const struc\n \t\tnew_addr = flow->tuplehash[FLOW_OFFLOAD_DIR_ORIGINAL].tuple.dst_v6;\n \t\tip6h->saddr = new_addr;\n \t\tbreak;\n-\tdefault:\n-\t\treturn -1;\n \t}\n \n \treturn nf_flow_nat_ipv6_l4proto(skb, ip6h, thoff, &addr, &new_addr);\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/610-v5.13-07-netfilter-flowtable-fast-NAT-functions-never-fail.patch",
    "content": "From: Pablo Neira Ayuso <pablo@netfilter.org>\nDate: Tue, 23 Mar 2021 00:56:25 +0100\nSubject: [PATCH] netfilter: flowtable: fast NAT functions never fail\n\nSimplify existing fast NAT routines by returning void. After the\nskb_try_make_writable() call consolidation, these routines cannot ever\nfail.\n\nSigned-off-by: Pablo Neira Ayuso <pablo@netfilter.org>\n---\n\n--- a/include/net/netfilter/nf_flow_table.h\n+++ b/include/net/netfilter/nf_flow_table.h\n@@ -228,12 +228,12 @@ void nf_flow_table_free(struct nf_flowta\n \n void flow_offload_teardown(struct flow_offload *flow);\n \n-int nf_flow_snat_port(const struct flow_offload *flow,\n-\t\t      struct sk_buff *skb, unsigned int thoff,\n-\t\t      u8 protocol, enum flow_offload_tuple_dir dir);\n-int nf_flow_dnat_port(const struct flow_offload *flow,\n-\t\t      struct sk_buff *skb, unsigned int thoff,\n-\t\t      u8 protocol, enum flow_offload_tuple_dir dir);\n+void nf_flow_snat_port(const struct flow_offload *flow,\n+\t\t       struct sk_buff *skb, unsigned int thoff,\n+\t\t       u8 protocol, enum flow_offload_tuple_dir dir);\n+void nf_flow_dnat_port(const struct flow_offload *flow,\n+\t\t       struct sk_buff *skb, unsigned int thoff,\n+\t\t       u8 protocol, enum flow_offload_tuple_dir dir);\n \n struct flow_ports {\n \t__be16 source, dest;\n--- a/net/netfilter/nf_flow_table_core.c\n+++ b/net/netfilter/nf_flow_table_core.c\n@@ -388,20 +388,17 @@ static void nf_flow_offload_work_gc(stru\n \tqueue_delayed_work(system_power_efficient_wq, &flow_table->gc_work, HZ);\n }\n \n-\n-static int nf_flow_nat_port_tcp(struct sk_buff *skb, unsigned int thoff,\n-\t\t\t\t__be16 port, __be16 new_port)\n+static void nf_flow_nat_port_tcp(struct sk_buff *skb, unsigned int thoff,\n+\t\t\t\t __be16 port, __be16 new_port)\n {\n \tstruct tcphdr *tcph;\n \n \ttcph = (void *)(skb_network_header(skb) + thoff);\n \tinet_proto_csum_replace2(&tcph->check, skb, port, new_port, false);\n-\n-\treturn 0;\n }\n \n-static int nf_flow_nat_port_udp(struct sk_buff *skb, unsigned int thoff,\n-\t\t\t\t__be16 port, __be16 new_port)\n+static void nf_flow_nat_port_udp(struct sk_buff *skb, unsigned int thoff,\n+\t\t\t\t __be16 port, __be16 new_port)\n {\n \tstruct udphdr *udph;\n \n@@ -412,30 +409,24 @@ static int nf_flow_nat_port_udp(struct s\n \t\tif (!udph->check)\n \t\t\tudph->check = CSUM_MANGLED_0;\n \t}\n-\n-\treturn 0;\n }\n \n-static int nf_flow_nat_port(struct sk_buff *skb, unsigned int thoff,\n-\t\t\t    u8 protocol, __be16 port, __be16 new_port)\n+static void nf_flow_nat_port(struct sk_buff *skb, unsigned int thoff,\n+\t\t\t     u8 protocol, __be16 port, __be16 new_port)\n {\n \tswitch (protocol) {\n \tcase IPPROTO_TCP:\n-\t\tif (nf_flow_nat_port_tcp(skb, thoff, port, new_port) < 0)\n-\t\t\treturn NF_DROP;\n+\t\tnf_flow_nat_port_tcp(skb, thoff, port, new_port);\n \t\tbreak;\n \tcase IPPROTO_UDP:\n-\t\tif (nf_flow_nat_port_udp(skb, thoff, port, new_port) < 0)\n-\t\t\treturn NF_DROP;\n+\t\tnf_flow_nat_port_udp(skb, thoff, port, new_port);\n \t\tbreak;\n \t}\n-\n-\treturn 0;\n }\n \n-int nf_flow_snat_port(const struct flow_offload *flow,\n-\t\t      struct sk_buff *skb, unsigned int thoff,\n-\t\t      u8 protocol, enum flow_offload_tuple_dir dir)\n+void nf_flow_snat_port(const struct flow_offload *flow,\n+\t\t       struct sk_buff *skb, unsigned int thoff,\n+\t\t       u8 protocol, enum flow_offload_tuple_dir dir)\n {\n \tstruct flow_ports *hdr;\n \t__be16 port, new_port;\n@@ -455,13 +446,13 @@ int nf_flow_snat_port(const struct flow_\n \t\tbreak;\n \t}\n \n-\treturn nf_flow_nat_port(skb, thoff, protocol, port, new_port);\n+\tnf_flow_nat_port(skb, thoff, protocol, port, new_port);\n }\n EXPORT_SYMBOL_GPL(nf_flow_snat_port);\n \n-int nf_flow_dnat_port(const struct flow_offload *flow,\n-\t\t      struct sk_buff *skb, unsigned int thoff,\n-\t\t      u8 protocol, enum flow_offload_tuple_dir dir)\n+void nf_flow_dnat_port(const struct flow_offload *flow, struct sk_buff *skb,\n+\t\t       unsigned int thoff, u8 protocol,\n+\t\t       enum flow_offload_tuple_dir dir)\n {\n \tstruct flow_ports *hdr;\n \t__be16 port, new_port;\n@@ -481,7 +472,7 @@ int nf_flow_dnat_port(const struct flow_\n \t\tbreak;\n \t}\n \n-\treturn nf_flow_nat_port(skb, thoff, protocol, port, new_port);\n+\tnf_flow_nat_port(skb, thoff, protocol, port, new_port);\n }\n EXPORT_SYMBOL_GPL(nf_flow_dnat_port);\n \n--- a/net/netfilter/nf_flow_table_ip.c\n+++ b/net/netfilter/nf_flow_table_ip.c\n@@ -34,19 +34,17 @@ static int nf_flow_state_check(struct fl\n \treturn 0;\n }\n \n-static int nf_flow_nat_ip_tcp(struct sk_buff *skb, unsigned int thoff,\n-\t\t\t      __be32 addr, __be32 new_addr)\n+static void nf_flow_nat_ip_tcp(struct sk_buff *skb, unsigned int thoff,\n+\t\t\t       __be32 addr, __be32 new_addr)\n {\n \tstruct tcphdr *tcph;\n \n \ttcph = (void *)(skb_network_header(skb) + thoff);\n \tinet_proto_csum_replace4(&tcph->check, skb, addr, new_addr, true);\n-\n-\treturn 0;\n }\n \n-static int nf_flow_nat_ip_udp(struct sk_buff *skb, unsigned int thoff,\n-\t\t\t      __be32 addr, __be32 new_addr)\n+static void nf_flow_nat_ip_udp(struct sk_buff *skb, unsigned int thoff,\n+\t\t\t       __be32 addr, __be32 new_addr)\n {\n \tstruct udphdr *udph;\n \n@@ -57,31 +55,25 @@ static int nf_flow_nat_ip_udp(struct sk_\n \t\tif (!udph->check)\n \t\t\tudph->check = CSUM_MANGLED_0;\n \t}\n-\n-\treturn 0;\n }\n \n-static int nf_flow_nat_ip_l4proto(struct sk_buff *skb, struct iphdr *iph,\n-\t\t\t\t  unsigned int thoff, __be32 addr,\n-\t\t\t\t  __be32 new_addr)\n+static void nf_flow_nat_ip_l4proto(struct sk_buff *skb, struct iphdr *iph,\n+\t\t\t\t   unsigned int thoff, __be32 addr,\n+\t\t\t\t   __be32 new_addr)\n {\n \tswitch (iph->protocol) {\n \tcase IPPROTO_TCP:\n-\t\tif (nf_flow_nat_ip_tcp(skb, thoff, addr, new_addr) < 0)\n-\t\t\treturn NF_DROP;\n+\t\tnf_flow_nat_ip_tcp(skb, thoff, addr, new_addr);\n \t\tbreak;\n \tcase IPPROTO_UDP:\n-\t\tif (nf_flow_nat_ip_udp(skb, thoff, addr, new_addr) < 0)\n-\t\t\treturn NF_DROP;\n+\t\tnf_flow_nat_ip_udp(skb, thoff, addr, new_addr);\n \t\tbreak;\n \t}\n-\n-\treturn 0;\n }\n \n-static int nf_flow_snat_ip(const struct flow_offload *flow, struct sk_buff *skb,\n-\t\t\t   struct iphdr *iph, unsigned int thoff,\n-\t\t\t   enum flow_offload_tuple_dir dir)\n+static void nf_flow_snat_ip(const struct flow_offload *flow,\n+\t\t\t    struct sk_buff *skb, struct iphdr *iph,\n+\t\t\t    unsigned int thoff, enum flow_offload_tuple_dir dir)\n {\n \t__be32 addr, new_addr;\n \n@@ -99,12 +91,12 @@ static int nf_flow_snat_ip(const struct\n \t}\n \tcsum_replace4(&iph->check, addr, new_addr);\n \n-\treturn nf_flow_nat_ip_l4proto(skb, iph, thoff, addr, new_addr);\n+\tnf_flow_nat_ip_l4proto(skb, iph, thoff, addr, new_addr);\n }\n \n-static int nf_flow_dnat_ip(const struct flow_offload *flow, struct sk_buff *skb,\n-\t\t\t   struct iphdr *iph, unsigned int thoff,\n-\t\t\t   enum flow_offload_tuple_dir dir)\n+static void nf_flow_dnat_ip(const struct flow_offload *flow,\n+\t\t\t    struct sk_buff *skb, struct iphdr *iph,\n+\t\t\t    unsigned int thoff, enum flow_offload_tuple_dir dir)\n {\n \t__be32 addr, new_addr;\n \n@@ -122,24 +114,21 @@ static int nf_flow_dnat_ip(const struct\n \t}\n \tcsum_replace4(&iph->check, addr, new_addr);\n \n-\treturn nf_flow_nat_ip_l4proto(skb, iph, thoff, addr, new_addr);\n+\tnf_flow_nat_ip_l4proto(skb, iph, thoff, addr, new_addr);\n }\n \n-static int nf_flow_nat_ip(const struct flow_offload *flow, struct sk_buff *skb,\n+static void nf_flow_nat_ip(const struct flow_offload *flow, struct sk_buff *skb,\n \t\t\t  unsigned int thoff, enum flow_offload_tuple_dir dir,\n \t\t\t  struct iphdr *iph)\n {\n-\tif (test_bit(NF_FLOW_SNAT, &flow->flags) &&\n-\t    (nf_flow_snat_port(flow, skb, thoff, iph->protocol, dir) < 0 ||\n-\t     nf_flow_snat_ip(flow, skb, iph, thoff, dir) < 0))\n-\t\treturn -1;\n-\n-\tif (test_bit(NF_FLOW_DNAT, &flow->flags) &&\n-\t    (nf_flow_dnat_port(flow, skb, thoff, iph->protocol, dir) < 0 ||\n-\t     nf_flow_dnat_ip(flow, skb, iph, thoff, dir) < 0))\n-\t\treturn -1;\n-\n-\treturn 0;\n+\tif (test_bit(NF_FLOW_SNAT, &flow->flags)) {\n+\t\tnf_flow_snat_port(flow, skb, thoff, iph->protocol, dir);\n+\t\tnf_flow_snat_ip(flow, skb, iph, thoff, dir);\n+\t}\n+\tif (test_bit(NF_FLOW_DNAT, &flow->flags)) {\n+\t\tnf_flow_dnat_port(flow, skb, thoff, iph->protocol, dir);\n+\t\tnf_flow_dnat_ip(flow, skb, iph, thoff, dir);\n+\t}\n }\n \n static bool ip_has_options(unsigned int thoff)\n@@ -276,8 +265,7 @@ nf_flow_offload_ip_hook(void *priv, stru\n \t\treturn NF_DROP;\n \n \tiph = ip_hdr(skb);\n-\tif (nf_flow_nat_ip(flow, skb, thoff, dir, iph) < 0)\n-\t\treturn NF_DROP;\n+\tnf_flow_nat_ip(flow, skb, thoff, dir, iph);\n \n \tip_decrease_ttl(iph);\n \tskb->tstamp = 0;\n@@ -301,22 +289,21 @@ nf_flow_offload_ip_hook(void *priv, stru\n }\n EXPORT_SYMBOL_GPL(nf_flow_offload_ip_hook);\n \n-static int nf_flow_nat_ipv6_tcp(struct sk_buff *skb, unsigned int thoff,\n-\t\t\t\tstruct in6_addr *addr,\n-\t\t\t\tstruct in6_addr *new_addr)\n+static void nf_flow_nat_ipv6_tcp(struct sk_buff *skb, unsigned int thoff,\n+\t\t\t\t struct in6_addr *addr,\n+\t\t\t\t struct in6_addr *new_addr,\n+\t\t\t\t struct ipv6hdr *ip6h)\n {\n \tstruct tcphdr *tcph;\n \n \ttcph = (void *)(skb_network_header(skb) + thoff);\n \tinet_proto_csum_replace16(&tcph->check, skb, addr->s6_addr32,\n \t\t\t\t  new_addr->s6_addr32, true);\n-\n-\treturn 0;\n }\n \n-static int nf_flow_nat_ipv6_udp(struct sk_buff *skb, unsigned int thoff,\n-\t\t\t\tstruct in6_addr *addr,\n-\t\t\t\tstruct in6_addr *new_addr)\n+static void nf_flow_nat_ipv6_udp(struct sk_buff *skb, unsigned int thoff,\n+\t\t\t\t struct in6_addr *addr,\n+\t\t\t\t struct in6_addr *new_addr)\n {\n \tstruct udphdr *udph;\n \n@@ -327,32 +314,26 @@ static int nf_flow_nat_ipv6_udp(struct s\n \t\tif (!udph->check)\n \t\t\tudph->check = CSUM_MANGLED_0;\n \t}\n-\n-\treturn 0;\n }\n \n-static int nf_flow_nat_ipv6_l4proto(struct sk_buff *skb, struct ipv6hdr *ip6h,\n-\t\t\t\t    unsigned int thoff, struct in6_addr *addr,\n-\t\t\t\t    struct in6_addr *new_addr)\n+static void nf_flow_nat_ipv6_l4proto(struct sk_buff *skb, struct ipv6hdr *ip6h,\n+\t\t\t\t     unsigned int thoff, struct in6_addr *addr,\n+\t\t\t\t     struct in6_addr *new_addr)\n {\n \tswitch (ip6h->nexthdr) {\n \tcase IPPROTO_TCP:\n-\t\tif (nf_flow_nat_ipv6_tcp(skb, thoff, addr, new_addr) < 0)\n-\t\t\treturn NF_DROP;\n+\t\tnf_flow_nat_ipv6_tcp(skb, thoff, addr, new_addr, ip6h);\n \t\tbreak;\n \tcase IPPROTO_UDP:\n-\t\tif (nf_flow_nat_ipv6_udp(skb, thoff, addr, new_addr) < 0)\n-\t\t\treturn NF_DROP;\n+\t\tnf_flow_nat_ipv6_udp(skb, thoff, addr, new_addr);\n \t\tbreak;\n \t}\n-\n-\treturn 0;\n }\n \n-static int nf_flow_snat_ipv6(const struct flow_offload *flow,\n-\t\t\t     struct sk_buff *skb, struct ipv6hdr *ip6h,\n-\t\t\t     unsigned int thoff,\n-\t\t\t     enum flow_offload_tuple_dir dir)\n+static void nf_flow_snat_ipv6(const struct flow_offload *flow,\n+\t\t\t      struct sk_buff *skb, struct ipv6hdr *ip6h,\n+\t\t\t      unsigned int thoff,\n+\t\t\t      enum flow_offload_tuple_dir dir)\n {\n \tstruct in6_addr addr, new_addr;\n \n@@ -369,13 +350,13 @@ static int nf_flow_snat_ipv6(const struc\n \t\tbreak;\n \t}\n \n-\treturn nf_flow_nat_ipv6_l4proto(skb, ip6h, thoff, &addr, &new_addr);\n+\tnf_flow_nat_ipv6_l4proto(skb, ip6h, thoff, &addr, &new_addr);\n }\n \n-static int nf_flow_dnat_ipv6(const struct flow_offload *flow,\n-\t\t\t     struct sk_buff *skb, struct ipv6hdr *ip6h,\n-\t\t\t     unsigned int thoff,\n-\t\t\t     enum flow_offload_tuple_dir dir)\n+static void nf_flow_dnat_ipv6(const struct flow_offload *flow,\n+\t\t\t      struct sk_buff *skb, struct ipv6hdr *ip6h,\n+\t\t\t      unsigned int thoff,\n+\t\t\t      enum flow_offload_tuple_dir dir)\n {\n \tstruct in6_addr addr, new_addr;\n \n@@ -392,27 +373,24 @@ static int nf_flow_dnat_ipv6(const struc\n \t\tbreak;\n \t}\n \n-\treturn nf_flow_nat_ipv6_l4proto(skb, ip6h, thoff, &addr, &new_addr);\n+\tnf_flow_nat_ipv6_l4proto(skb, ip6h, thoff, &addr, &new_addr);\n }\n \n-static int nf_flow_nat_ipv6(const struct flow_offload *flow,\n-\t\t\t    struct sk_buff *skb,\n-\t\t\t    enum flow_offload_tuple_dir dir,\n-\t\t\t    struct ipv6hdr *ip6h)\n+static void nf_flow_nat_ipv6(const struct flow_offload *flow,\n+\t\t\t     struct sk_buff *skb,\n+\t\t\t     enum flow_offload_tuple_dir dir,\n+\t\t\t     struct ipv6hdr *ip6h)\n {\n \tunsigned int thoff = sizeof(*ip6h);\n \n-\tif (test_bit(NF_FLOW_SNAT, &flow->flags) &&\n-\t    (nf_flow_snat_port(flow, skb, thoff, ip6h->nexthdr, dir) < 0 ||\n-\t     nf_flow_snat_ipv6(flow, skb, ip6h, thoff, dir) < 0))\n-\t\treturn -1;\n-\n-\tif (test_bit(NF_FLOW_DNAT, &flow->flags) &&\n-\t    (nf_flow_dnat_port(flow, skb, thoff, ip6h->nexthdr, dir) < 0 ||\n-\t     nf_flow_dnat_ipv6(flow, skb, ip6h, thoff, dir) < 0))\n-\t\treturn -1;\n-\n-\treturn 0;\n+\tif (test_bit(NF_FLOW_SNAT, &flow->flags)) {\n+\t\tnf_flow_snat_port(flow, skb, thoff, ip6h->nexthdr, dir);\n+\t\tnf_flow_snat_ipv6(flow, skb, ip6h, thoff, dir);\n+\t}\n+\tif (test_bit(NF_FLOW_DNAT, &flow->flags)) {\n+\t\tnf_flow_dnat_port(flow, skb, thoff, ip6h->nexthdr, dir);\n+\t\tnf_flow_dnat_ipv6(flow, skb, ip6h, thoff, dir);\n+\t}\n }\n \n static int nf_flow_tuple_ipv6(struct sk_buff *skb, const struct net_device *dev,\n@@ -507,8 +485,7 @@ nf_flow_offload_ipv6_hook(void *priv, st\n \t\treturn NF_DROP;\n \n \tip6h = ipv6_hdr(skb);\n-\tif (nf_flow_nat_ipv6(flow, skb, dir, ip6h) < 0)\n-\t\treturn NF_DROP;\n+\tnf_flow_nat_ipv6(flow, skb, dir, ip6h);\n \n \tip6h->hop_limit--;\n \tskb->tstamp = 0;\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/610-v5.13-08-netfilter-flowtable-call-dst_check-to-fall-back-to-c.patch",
    "content": "From: Pablo Neira Ayuso <pablo@netfilter.org>\nDate: Tue, 23 Mar 2021 00:56:26 +0100\nSubject: [PATCH] netfilter: flowtable: call dst_check() to fall back to\n classic forwarding\n\nIn case the route is stale, pass up the packet to the classic forwarding\npath for re-evaluation and schedule this flow entry for removal.\n\nSigned-off-by: Pablo Neira Ayuso <pablo@netfilter.org>\n---\n\n--- a/net/netfilter/nf_flow_table_ip.c\n+++ b/net/netfilter/nf_flow_table_ip.c\n@@ -197,14 +197,6 @@ static bool nf_flow_exceeds_mtu(const st\n \treturn true;\n }\n \n-static int nf_flow_offload_dst_check(struct dst_entry *dst)\n-{\n-\tif (unlikely(dst_xfrm(dst)))\n-\t\treturn dst_check(dst, 0) ? 0 : -1;\n-\n-\treturn 0;\n-}\n-\n static unsigned int nf_flow_xmit_xfrm(struct sk_buff *skb,\n \t\t\t\t      const struct nf_hook_state *state,\n \t\t\t\t      struct dst_entry *dst)\n@@ -256,7 +248,7 @@ nf_flow_offload_ip_hook(void *priv, stru\n \n \tflow_offload_refresh(flow_table, flow);\n \n-\tif (nf_flow_offload_dst_check(&rt->dst)) {\n+\tif (!dst_check(&rt->dst, 0)) {\n \t\tflow_offload_teardown(flow);\n \t\treturn NF_ACCEPT;\n \t}\n@@ -476,7 +468,7 @@ nf_flow_offload_ipv6_hook(void *priv, st\n \n \tflow_offload_refresh(flow_table, flow);\n \n-\tif (nf_flow_offload_dst_check(&rt->dst)) {\n+\tif (!dst_check(&rt->dst, 0)) {\n \t\tflow_offload_teardown(flow);\n \t\treturn NF_ACCEPT;\n \t}\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/610-v5.13-09-netfilter-flowtable-refresh-timeout-after-dst-and-wr.patch",
    "content": "From: Pablo Neira Ayuso <pablo@netfilter.org>\nDate: Tue, 23 Mar 2021 00:56:27 +0100\nSubject: [PATCH] netfilter: flowtable: refresh timeout after dst and\n writable checks\n\nRefresh the timeout (and retry hardware offload) once the skbuff dst\nis confirmed to be current and after the skbuff is made writable.\n\nSigned-off-by: Pablo Neira Ayuso <pablo@netfilter.org>\n---\n\n--- a/net/netfilter/nf_flow_table_ip.c\n+++ b/net/netfilter/nf_flow_table_ip.c\n@@ -246,8 +246,6 @@ nf_flow_offload_ip_hook(void *priv, stru\n \tif (nf_flow_state_check(flow, iph->protocol, skb, thoff))\n \t\treturn NF_ACCEPT;\n \n-\tflow_offload_refresh(flow_table, flow);\n-\n \tif (!dst_check(&rt->dst, 0)) {\n \t\tflow_offload_teardown(flow);\n \t\treturn NF_ACCEPT;\n@@ -256,6 +254,8 @@ nf_flow_offload_ip_hook(void *priv, stru\n \tif (skb_try_make_writable(skb, thoff + hdrsize))\n \t\treturn NF_DROP;\n \n+\tflow_offload_refresh(flow_table, flow);\n+\n \tiph = ip_hdr(skb);\n \tnf_flow_nat_ip(flow, skb, thoff, dir, iph);\n \n@@ -466,8 +466,6 @@ nf_flow_offload_ipv6_hook(void *priv, st\n \t\t\t\tsizeof(*ip6h)))\n \t\treturn NF_ACCEPT;\n \n-\tflow_offload_refresh(flow_table, flow);\n-\n \tif (!dst_check(&rt->dst, 0)) {\n \t\tflow_offload_teardown(flow);\n \t\treturn NF_ACCEPT;\n@@ -476,6 +474,8 @@ nf_flow_offload_ipv6_hook(void *priv, st\n \tif (skb_try_make_writable(skb, sizeof(*ip6h) + hdrsize))\n \t\treturn NF_DROP;\n \n+\tflow_offload_refresh(flow_table, flow);\n+\n \tip6h = ipv6_hdr(skb);\n \tnf_flow_nat_ipv6(flow, skb, dir, ip6h);\n \n"
  },
  {
    "path": "target/linux/generic/backport-5.10/610-v5.13-10-netfilter-nftables-update-table-flags-from-the-commi.patch",
    "content": "From: Pablo Neira Ayuso <pablo@netfilter.org>\nDate: Tue, 23 Mar 2021 00:56:28 +0100\nSubject: [PATCH] netfilter: nftables: update table flags from the commit\n phase\n\nDo not update table flags from the preparation phase. Store the flags\nupdate into the transaction, then update the flags from the commit\nphase.\n\nSigned-off-by: Pablo Neira Ayuso <pablo@netfilter.org>\n---\n\n--- a/include/net/netfilter/nf_tables.h\n+++ b/include/net/netfilter/nf_tables.h\n@@ -1470,13 +1470,16 @@ struct nft_trans_chain {\n \n struct nft_trans_table {\n \tbool\t\t\t\tupdate;\n-\tbool\t\t\t\tenable;\n+\tu8\t\t\t\tstate;\n+\tu32\t\t\t\tflags;\n };\n \n #define nft_trans_table_update(trans)\t\\\n \t(((struct nft_trans_table *)trans->data)->update)\n-#define nft_trans_table_enable(trans)\t\\\n-\t(((struct nft_trans_table *)trans->data)->enable)\n+#define nft_trans_table_state(trans)\t\\\n+\t(((struct nft_trans_table *)trans->data)->state)\n+#define nft_trans_table_flags(trans)\t\\\n+\t(((struct nft_trans_table *)trans->data)->flags)\n \n struct nft_trans_elem {\n \tstruct nft_set\t\t\t*set;\n--- a/net/netfilter/nf_tables_api.c\n+++ b/net/netfilter/nf_tables_api.c\n@@ -891,6 +891,12 @@ static void nf_tables_table_disable(stru\n \tnft_table_disable(net, table, 0);\n }\n \n+enum {\n+\tNFT_TABLE_STATE_UNCHANGED\t= 0,\n+\tNFT_TABLE_STATE_DORMANT,\n+\tNFT_TABLE_STATE_WAKEUP\n+};\n+\n static int nf_tables_updtable(struct nft_ctx *ctx)\n {\n \tstruct nft_trans *trans;\n@@ -914,19 +920,17 @@ static int nf_tables_updtable(struct nft\n \n \tif ((flags & NFT_TABLE_F_DORMANT) &&\n \t    !(ctx->table->flags & NFT_TABLE_F_DORMANT)) {\n-\t\tnft_trans_table_enable(trans) = false;\n+\t\tnft_trans_table_state(trans) = NFT_TABLE_STATE_DORMANT;\n \t} else if (!(flags & NFT_TABLE_F_DORMANT) &&\n \t\t   ctx->table->flags & NFT_TABLE_F_DORMANT) {\n-\t\tctx->table->flags &= ~NFT_TABLE_F_DORMANT;\n \t\tret = nf_tables_table_enable(ctx->net, ctx->table);\n \t\tif (ret >= 0)\n-\t\t\tnft_trans_table_enable(trans) = true;\n-\t\telse\n-\t\t\tctx->table->flags |= NFT_TABLE_F_DORMANT;\n+\t\t\tnft_trans_table_state(trans) = NFT_TABLE_STATE_WAKEUP;\n \t}\n \tif (ret < 0)\n \t\tgoto err;\n \n+\tnft_trans_table_flags(trans) = flags;\n \tnft_trans_table_update(trans) = true;\n \tlist_add_tail(&trans->list, &ctx->net->nft.commit_list);\n \treturn 0;\n@@ -7908,11 +7912,10 @@ static int nf_tables_commit(struct net *\n \t\tswitch (trans->msg_type) {\n \t\tcase NFT_MSG_NEWTABLE:\n \t\t\tif (nft_trans_table_update(trans)) {\n-\t\t\t\tif (!nft_trans_table_enable(trans)) {\n-\t\t\t\t\tnf_tables_table_disable(net,\n-\t\t\t\t\t\t\t\ttrans->ctx.table);\n-\t\t\t\t\ttrans->ctx.table->flags |= NFT_TABLE_F_DORMANT;\n-\t\t\t\t}\n+\t\t\t\tif (nft_trans_table_state(trans) == NFT_TABLE_STATE_DORMANT)\n+\t\t\t\t\tnf_tables_table_disable(net, trans->ctx.table);\n+\n+\t\t\t\ttrans->ctx.table->flags = nft_trans_table_flags(trans);\n \t\t\t} else {\n \t\t\t\tnft_clear(net, trans->ctx.table);\n \t\t\t}\n@@ -8125,11 +8128,9 @@ static int __nf_tables_abort(struct net\n \t\tswitch (trans->msg_type) {\n \t\tcase NFT_MSG_NEWTABLE:\n \t\t\tif (nft_trans_table_update(trans)) {\n-\t\t\t\tif (nft_trans_table_enable(trans)) {\n-\t\t\t\t\tnf_tables_table_disable(net,\n-\t\t\t\t\t\t\t\ttrans->ctx.table);\n-\t\t\t\t\ttrans->ctx.table->flags |= NFT_TABLE_F_DORMANT;\n-\t\t\t\t}\n+\t\t\t\tif (nft_trans_table_state(trans) == NFT_TABLE_STATE_WAKEUP)\n+\t\t\t\t\tnf_tables_table_disable(net, trans->ctx.table);\n+\n \t\t\t\tnft_trans_destroy(trans);\n \t\t\t} else {\n \t\t\t\tlist_del_rcu(&trans->ctx.table->list);\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/610-v5.13-11-net-resolve-forwarding-path-from-virtual-netdevice-a.patch",
    "content": "From: Pablo Neira Ayuso <pablo@netfilter.org>\nDate: Wed, 24 Mar 2021 02:30:32 +0100\nSubject: [PATCH] net: resolve forwarding path from virtual netdevice and\n HW destination address\n\nThis patch adds dev_fill_forward_path() which resolves the path to reach\nthe real netdevice from the IP forwarding side. This function takes as\ninput the netdevice and the destination hardware address and it walks\ndown the devices calling .ndo_fill_forward_path() for each device until\nthe real device is found.\n\nFor instance, assuming the following topology:\n\n               IP forwarding\n              /             \\\n           br0              eth0\n           / \\\n       eth1  eth2\n        .\n        .\n        .\n       ethX\n ab:cd:ef:ab:cd:ef\n\nwhere eth1 and eth2 are bridge ports and eth0 provides WAN connectivity.\nethX is the interface in another box which is connected to the eth1\nbridge port.\n\nFor packets going through IP forwarding to br0 whose destination MAC\naddress is ab:cd:ef:ab:cd:ef, dev_fill_forward_path() provides the\nfollowing path:\n\n\tbr0 -> eth1\n\n.ndo_fill_forward_path for br0 looks up at the FDB for the bridge port\nfrom the destination MAC address to get the bridge port eth1.\n\nThis information allows to create a fast path that bypasses the classic\nbridge and IP forwarding paths, so packets go directly from the bridge\nport eth1 to eth0 (wan interface) and vice versa.\n\n             fast path\n      .------------------------.\n     /                          \\\n    |           IP forwarding   |\n    |          /             \\  \\/\n    |       br0               eth0\n    .       / \\\n     -> eth1  eth2\n        .\n        .\n        .\n       ethX\n ab:cd:ef:ab:cd:ef\n\nSigned-off-by: Pablo Neira Ayuso <pablo@netfilter.org>\n---\n\n--- a/include/linux/netdevice.h\n+++ b/include/linux/netdevice.h\n@@ -827,6 +827,27 @@ typedef u16 (*select_queue_fallback_t)(s\n \t\t\t\t       struct sk_buff *skb,\n \t\t\t\t       struct net_device *sb_dev);\n \n+enum net_device_path_type {\n+\tDEV_PATH_ETHERNET = 0,\n+};\n+\n+struct net_device_path {\n+\tenum net_device_path_type\ttype;\n+\tconst struct net_device\t\t*dev;\n+};\n+\n+#define NET_DEVICE_PATH_STACK_MAX\t5\n+\n+struct net_device_path_stack {\n+\tint\t\t\tnum_paths;\n+\tstruct net_device_path\tpath[NET_DEVICE_PATH_STACK_MAX];\n+};\n+\n+struct net_device_path_ctx {\n+\tconst struct net_device *dev;\n+\tconst u8\t\t*daddr;\n+};\n+\n enum tc_setup_type {\n \tTC_SETUP_QDISC_MQPRIO,\n \tTC_SETUP_CLSU32,\n@@ -1273,6 +1294,8 @@ struct netdev_net_notifier {\n  * struct net_device *(*ndo_get_peer_dev)(struct net_device *dev);\n  *\tIf a device is paired with a peer device, return the peer instance.\n  *\tThe caller must be under RCU read context.\n+ * int (*ndo_fill_forward_path)(struct net_device_path_ctx *ctx, struct net_device_path *path);\n+ *     Get the forwarding path to reach the real device from the HW destination address\n  */\n struct net_device_ops {\n \tint\t\t\t(*ndo_init)(struct net_device *dev);\n@@ -1481,6 +1504,8 @@ struct net_device_ops {\n \tint\t\t\t(*ndo_tunnel_ctl)(struct net_device *dev,\n \t\t\t\t\t\t  struct ip_tunnel_parm *p, int cmd);\n \tstruct net_device *\t(*ndo_get_peer_dev)(struct net_device *dev);\n+\tint                     (*ndo_fill_forward_path)(struct net_device_path_ctx *ctx,\n+                                                         struct net_device_path *path);\n };\n \n /**\n@@ -2828,6 +2853,8 @@ void dev_remove_offload(struct packet_of\n \n int dev_get_iflink(const struct net_device *dev);\n int dev_fill_metadata_dst(struct net_device *dev, struct sk_buff *skb);\n+int dev_fill_forward_path(const struct net_device *dev, const u8 *daddr,\n+\t\t\t  struct net_device_path_stack *stack);\n struct net_device *__dev_get_by_flags(struct net *net, unsigned short flags,\n \t\t\t\t      unsigned short mask);\n struct net_device *dev_get_by_name(struct net *net, const char *name);\n--- a/net/core/dev.c\n+++ b/net/core/dev.c\n@@ -847,6 +847,52 @@ int dev_fill_metadata_dst(struct net_dev\n }\n EXPORT_SYMBOL_GPL(dev_fill_metadata_dst);\n \n+static struct net_device_path *dev_fwd_path(struct net_device_path_stack *stack)\n+{\n+\tint k = stack->num_paths++;\n+\n+\tif (WARN_ON_ONCE(k >= NET_DEVICE_PATH_STACK_MAX))\n+\t\treturn NULL;\n+\n+\treturn &stack->path[k];\n+}\n+\n+int dev_fill_forward_path(const struct net_device *dev, const u8 *daddr,\n+\t\t\t  struct net_device_path_stack *stack)\n+{\n+\tconst struct net_device *last_dev;\n+\tstruct net_device_path_ctx ctx = {\n+\t\t.dev\t= dev,\n+\t\t.daddr\t= daddr,\n+\t};\n+\tstruct net_device_path *path;\n+\tint ret = 0;\n+\n+\tstack->num_paths = 0;\n+\twhile (ctx.dev && ctx.dev->netdev_ops->ndo_fill_forward_path) {\n+\t\tlast_dev = ctx.dev;\n+\t\tpath = dev_fwd_path(stack);\n+\t\tif (!path)\n+\t\t\treturn -1;\n+\n+\t\tmemset(path, 0, sizeof(struct net_device_path));\n+\t\tret = ctx.dev->netdev_ops->ndo_fill_forward_path(&ctx, path);\n+\t\tif (ret < 0)\n+\t\t\treturn -1;\n+\n+\t\tif (WARN_ON_ONCE(last_dev == ctx.dev))\n+\t\t\treturn -1;\n+\t}\n+\tpath = dev_fwd_path(stack);\n+\tif (!path)\n+\t\treturn -1;\n+\tpath->type = DEV_PATH_ETHERNET;\n+\tpath->dev = ctx.dev;\n+\n+\treturn ret;\n+}\n+EXPORT_SYMBOL_GPL(dev_fill_forward_path);\n+\n /**\n  *\t__dev_get_by_name\t- find a device by its name\n  *\t@net: the applicable net namespace\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/610-v5.13-12-net-8021q-resolve-forwarding-path-for-vlan-devices.patch",
    "content": "From: Pablo Neira Ayuso <pablo@netfilter.org>\nDate: Wed, 24 Mar 2021 02:30:33 +0100\nSubject: [PATCH] net: 8021q: resolve forwarding path for vlan devices\n\nAdd .ndo_fill_forward_path for vlan devices.\n\nFor instance, assuming the following topology:\n\n                   IP forwarding\n                  /             \\\n            eth0.100             eth0\n            |\n            eth0\n            .\n            .\n            .\n           ethX\n     ab:cd:ef:ab:cd:ef\n\nFor packets going through IP forwarding to eth0.100 whose destination\nMAC address is ab:cd:ef:ab:cd:ef, dev_fill_forward_path() provides the\nfollowing path:\n\n        eth0.100 -> eth0\n\nSigned-off-by: Pablo Neira Ayuso <pablo@netfilter.org>\n---\n\n--- a/include/linux/netdevice.h\n+++ b/include/linux/netdevice.h\n@@ -829,11 +829,18 @@ typedef u16 (*select_queue_fallback_t)(s\n \n enum net_device_path_type {\n \tDEV_PATH_ETHERNET = 0,\n+\tDEV_PATH_VLAN,\n };\n \n struct net_device_path {\n \tenum net_device_path_type\ttype;\n \tconst struct net_device\t\t*dev;\n+\tunion {\n+\t\tstruct {\n+\t\t\tu16\t\tid;\n+\t\t\t__be16\t\tproto;\n+\t\t} encap;\n+\t};\n };\n \n #define NET_DEVICE_PATH_STACK_MAX\t5\n--- a/net/8021q/vlan_dev.c\n+++ b/net/8021q/vlan_dev.c\n@@ -770,6 +770,20 @@ static int vlan_dev_get_iflink(const str\n \treturn real_dev->ifindex;\n }\n \n+static int vlan_dev_fill_forward_path(struct net_device_path_ctx *ctx,\n+\t\t\t\t      struct net_device_path *path)\n+{\n+\tstruct vlan_dev_priv *vlan = vlan_dev_priv(ctx->dev);\n+\n+\tpath->type = DEV_PATH_VLAN;\n+\tpath->encap.id = vlan->vlan_id;\n+\tpath->encap.proto = vlan->vlan_proto;\n+\tpath->dev = ctx->dev;\n+\tctx->dev = vlan->real_dev;\n+\n+\treturn 0;\n+}\n+\n static const struct ethtool_ops vlan_ethtool_ops = {\n \t.get_link_ksettings\t= vlan_ethtool_get_link_ksettings,\n \t.get_drvinfo\t        = vlan_ethtool_get_drvinfo,\n@@ -808,6 +822,7 @@ static const struct net_device_ops vlan_\n #endif\n \t.ndo_fix_features\t= vlan_dev_fix_features,\n \t.ndo_get_iflink\t\t= vlan_dev_get_iflink,\n+\t.ndo_fill_forward_path\t= vlan_dev_fill_forward_path,\n };\n \n static void vlan_dev_free(struct net_device *dev)\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/610-v5.13-13-net-bridge-resolve-forwarding-path-for-bridge-device.patch",
    "content": "From: Pablo Neira Ayuso <pablo@netfilter.org>\nDate: Wed, 24 Mar 2021 02:30:34 +0100\nSubject: [PATCH] net: bridge: resolve forwarding path for bridge devices\n\nAdd .ndo_fill_forward_path for bridge devices.\n\nSigned-off-by: Pablo Neira Ayuso <pablo@netfilter.org>\n---\n\n--- a/include/linux/netdevice.h\n+++ b/include/linux/netdevice.h\n@@ -830,6 +830,7 @@ typedef u16 (*select_queue_fallback_t)(s\n enum net_device_path_type {\n \tDEV_PATH_ETHERNET = 0,\n \tDEV_PATH_VLAN,\n+\tDEV_PATH_BRIDGE,\n };\n \n struct net_device_path {\n--- a/net/bridge/br_device.c\n+++ b/net/bridge/br_device.c\n@@ -398,6 +398,32 @@ static int br_del_slave(struct net_devic\n \treturn br_del_if(br, slave_dev);\n }\n \n+static int br_fill_forward_path(struct net_device_path_ctx *ctx,\n+\t\t\t\tstruct net_device_path *path)\n+{\n+\tstruct net_bridge_fdb_entry *f;\n+\tstruct net_bridge_port *dst;\n+\tstruct net_bridge *br;\n+\n+\tif (netif_is_bridge_port(ctx->dev))\n+\t\treturn -1;\n+\n+\tbr = netdev_priv(ctx->dev);\n+\tf = br_fdb_find_rcu(br, ctx->daddr, 0);\n+\tif (!f || !f->dst)\n+\t\treturn -1;\n+\n+\tdst = READ_ONCE(f->dst);\n+\tif (!dst)\n+\t\treturn -1;\n+\n+\tpath->type = DEV_PATH_BRIDGE;\n+\tpath->dev = dst->br->dev;\n+\tctx->dev = dst->dev;\n+\n+\treturn 0;\n+}\n+\n static const struct ethtool_ops br_ethtool_ops = {\n \t.get_drvinfo\t\t = br_getinfo,\n \t.get_link\t\t = ethtool_op_get_link,\n@@ -432,6 +458,7 @@ static const struct net_device_ops br_ne\n \t.ndo_bridge_setlink\t = br_setlink,\n \t.ndo_bridge_dellink\t = br_dellink,\n \t.ndo_features_check\t = passthru_features_check,\n+\t.ndo_fill_forward_path\t = br_fill_forward_path,\n };\n \n static struct device_type br_type = {\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/610-v5.13-14-net-bridge-resolve-forwarding-path-for-VLAN-tag-acti.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nDate: Wed, 24 Mar 2021 02:30:35 +0100\nSubject: [PATCH] net: bridge: resolve forwarding path for VLAN tag\n actions in bridge devices\n\nDepending on the VLAN settings of the bridge and the port, the bridge can\neither add or remove a tag. When vlan filtering is enabled, the fdb lookup\nalso needs to know the VLAN tag/proto for the destination address\nTo provide this, keep track of the stack of VLAN tags for the path in the\nlookup context\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\nSigned-off-by: Pablo Neira Ayuso <pablo@netfilter.org>\n---\n\n--- a/include/linux/netdevice.h\n+++ b/include/linux/netdevice.h\n@@ -841,10 +841,20 @@ struct net_device_path {\n \t\t\tu16\t\tid;\n \t\t\t__be16\t\tproto;\n \t\t} encap;\n+\t\tstruct {\n+\t\t\tenum {\n+\t\t\t\tDEV_PATH_BR_VLAN_KEEP,\n+\t\t\t\tDEV_PATH_BR_VLAN_TAG,\n+\t\t\t\tDEV_PATH_BR_VLAN_UNTAG,\n+\t\t\t}\t\tvlan_mode;\n+\t\t\tu16\t\tvlan_id;\n+\t\t\t__be16\t\tvlan_proto;\n+\t\t} bridge;\n \t};\n };\n \n #define NET_DEVICE_PATH_STACK_MAX\t5\n+#define NET_DEVICE_PATH_VLAN_MAX\t2\n \n struct net_device_path_stack {\n \tint\t\t\tnum_paths;\n@@ -854,6 +864,12 @@ struct net_device_path_stack {\n struct net_device_path_ctx {\n \tconst struct net_device *dev;\n \tconst u8\t\t*daddr;\n+\n+\tint\t\t\tnum_vlans;\n+\tstruct {\n+\t\tu16\t\tid;\n+\t\t__be16\t\tproto;\n+\t} vlan[NET_DEVICE_PATH_VLAN_MAX];\n };\n \n enum tc_setup_type {\n--- a/net/8021q/vlan_dev.c\n+++ b/net/8021q/vlan_dev.c\n@@ -780,6 +780,12 @@ static int vlan_dev_fill_forward_path(st\n \tpath->encap.proto = vlan->vlan_proto;\n \tpath->dev = ctx->dev;\n \tctx->dev = vlan->real_dev;\n+\tif (ctx->num_vlans >= ARRAY_SIZE(ctx->vlan))\n+\t\treturn -ENOSPC;\n+\n+\tctx->vlan[ctx->num_vlans].id = vlan->vlan_id;\n+\tctx->vlan[ctx->num_vlans].proto = vlan->vlan_proto;\n+\tctx->num_vlans++;\n \n \treturn 0;\n }\n--- a/net/bridge/br_device.c\n+++ b/net/bridge/br_device.c\n@@ -409,7 +409,10 @@ static int br_fill_forward_path(struct n\n \t\treturn -1;\n \n \tbr = netdev_priv(ctx->dev);\n-\tf = br_fdb_find_rcu(br, ctx->daddr, 0);\n+\n+\tbr_vlan_fill_forward_path_pvid(br, ctx, path);\n+\n+\tf = br_fdb_find_rcu(br, ctx->daddr, path->bridge.vlan_id);\n \tif (!f || !f->dst)\n \t\treturn -1;\n \n@@ -417,10 +420,28 @@ static int br_fill_forward_path(struct n\n \tif (!dst)\n \t\treturn -1;\n \n+\tif (br_vlan_fill_forward_path_mode(br, dst, path))\n+\t\treturn -1;\n+\n \tpath->type = DEV_PATH_BRIDGE;\n \tpath->dev = dst->br->dev;\n \tctx->dev = dst->dev;\n \n+\tswitch (path->bridge.vlan_mode) {\n+\tcase DEV_PATH_BR_VLAN_TAG:\n+\t\tif (ctx->num_vlans >= ARRAY_SIZE(ctx->vlan))\n+\t\t\treturn -ENOSPC;\n+\t\tctx->vlan[ctx->num_vlans].id = path->bridge.vlan_id;\n+\t\tctx->vlan[ctx->num_vlans].proto = path->bridge.vlan_proto;\n+\t\tctx->num_vlans++;\n+\t\tbreak;\n+\tcase DEV_PATH_BR_VLAN_UNTAG:\n+\t\tctx->num_vlans--;\n+\t\tbreak;\n+\tcase DEV_PATH_BR_VLAN_KEEP:\n+\t\tbreak;\n+\t}\n+\n \treturn 0;\n }\n \n--- a/net/bridge/br_private.h\n+++ b/net/bridge/br_private.h\n@@ -1093,6 +1093,13 @@ void br_vlan_notify(const struct net_bri\n bool br_vlan_can_enter_range(const struct net_bridge_vlan *v_curr,\n \t\t\t     const struct net_bridge_vlan *range_end);\n \n+void br_vlan_fill_forward_path_pvid(struct net_bridge *br,\n+\t\t\t\t    struct net_device_path_ctx *ctx,\n+\t\t\t\t    struct net_device_path *path);\n+int br_vlan_fill_forward_path_mode(struct net_bridge *br,\n+\t\t\t\t   struct net_bridge_port *dst,\n+\t\t\t\t   struct net_device_path *path);\n+\n static inline struct net_bridge_vlan_group *br_vlan_group(\n \t\t\t\t\tconst struct net_bridge *br)\n {\n@@ -1250,6 +1257,19 @@ static inline int nbp_get_num_vlan_infos\n {\n \treturn 0;\n }\n+\n+static inline void br_vlan_fill_forward_path_pvid(struct net_bridge *br,\n+\t\t\t\t\t\t  struct net_device_path_ctx *ctx,\n+\t\t\t\t\t\t  struct net_device_path *path)\n+{\n+}\n+\n+static inline int br_vlan_fill_forward_path_mode(struct net_bridge *br,\n+\t\t\t\t\t\t struct net_bridge_port *dst,\n+\t\t\t\t\t\t struct net_device_path *path)\n+{\n+\treturn 0;\n+}\n \n static inline struct net_bridge_vlan_group *br_vlan_group(\n \t\t\t\t\tconst struct net_bridge *br)\n--- a/net/bridge/br_vlan.c\n+++ b/net/bridge/br_vlan.c\n@@ -1327,6 +1327,59 @@ int br_vlan_get_pvid_rcu(const struct ne\n }\n EXPORT_SYMBOL_GPL(br_vlan_get_pvid_rcu);\n \n+void br_vlan_fill_forward_path_pvid(struct net_bridge *br,\n+\t\t\t\t    struct net_device_path_ctx *ctx,\n+\t\t\t\t    struct net_device_path *path)\n+{\n+\tstruct net_bridge_vlan_group *vg;\n+\tint idx = ctx->num_vlans - 1;\n+\tu16 vid;\n+\n+\tpath->bridge.vlan_mode = DEV_PATH_BR_VLAN_KEEP;\n+\n+\tif (!br_opt_get(br, BROPT_VLAN_ENABLED))\n+\t\treturn;\n+\n+\tvg = br_vlan_group(br);\n+\n+\tif (idx >= 0 &&\n+\t    ctx->vlan[idx].proto == br->vlan_proto) {\n+\t\tvid = ctx->vlan[idx].id;\n+\t} else {\n+\t\tpath->bridge.vlan_mode = DEV_PATH_BR_VLAN_TAG;\n+\t\tvid = br_get_pvid(vg);\n+\t}\n+\n+\tpath->bridge.vlan_id = vid;\n+\tpath->bridge.vlan_proto = br->vlan_proto;\n+}\n+\n+int br_vlan_fill_forward_path_mode(struct net_bridge *br,\n+\t\t\t\t   struct net_bridge_port *dst,\n+\t\t\t\t   struct net_device_path *path)\n+{\n+\tstruct net_bridge_vlan_group *vg;\n+\tstruct net_bridge_vlan *v;\n+\n+\tif (!br_opt_get(br, BROPT_VLAN_ENABLED))\n+\t\treturn 0;\n+\n+\tvg = nbp_vlan_group_rcu(dst);\n+\tv = br_vlan_find(vg, path->bridge.vlan_id);\n+\tif (!v || !br_vlan_should_use(v))\n+\t\treturn -EINVAL;\n+\n+\tif (!(v->flags & BRIDGE_VLAN_INFO_UNTAGGED))\n+\t\treturn 0;\n+\n+\tif (path->bridge.vlan_mode == DEV_PATH_BR_VLAN_TAG)\n+\t\tpath->bridge.vlan_mode = DEV_PATH_BR_VLAN_KEEP;\n+\telse\n+\t\tpath->bridge.vlan_mode = DEV_PATH_BR_VLAN_UNTAG;\n+\n+\treturn 0;\n+}\n+\n int br_vlan_get_info(const struct net_device *dev, u16 vid,\n \t\t     struct bridge_vlan_info *p_vinfo)\n {\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/610-v5.13-15-net-ppp-resolve-forwarding-path-for-bridge-pppoe-dev.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nDate: Wed, 24 Mar 2021 02:30:36 +0100\nSubject: [PATCH] net: ppp: resolve forwarding path for bridge pppoe\n devices\n\nPass on the PPPoE session ID, destination hardware address and the real\ndevice.\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\nSigned-off-by: Pablo Neira Ayuso <pablo@netfilter.org>\n---\n\n--- a/drivers/net/ppp/ppp_generic.c\n+++ b/drivers/net/ppp/ppp_generic.c\n@@ -1466,12 +1466,34 @@ static void ppp_dev_priv_destructor(stru\n \t\tppp_destroy_interface(ppp);\n }\n \n+static int ppp_fill_forward_path(struct net_device_path_ctx *ctx,\n+\t\t\t\t struct net_device_path *path)\n+{\n+\tstruct ppp *ppp = netdev_priv(ctx->dev);\n+\tstruct ppp_channel *chan;\n+\tstruct channel *pch;\n+\n+\tif (ppp->flags & SC_MULTILINK)\n+\t\treturn -EOPNOTSUPP;\n+\n+\tif (list_empty(&ppp->channels))\n+\t\treturn -ENODEV;\n+\n+\tpch = list_first_entry(&ppp->channels, struct channel, clist);\n+\tchan = pch->chan;\n+\tif (!chan->ops->fill_forward_path)\n+\t\treturn -EOPNOTSUPP;\n+\n+\treturn chan->ops->fill_forward_path(ctx, path, chan);\n+}\n+\n static const struct net_device_ops ppp_netdev_ops = {\n \t.ndo_init\t = ppp_dev_init,\n \t.ndo_uninit      = ppp_dev_uninit,\n \t.ndo_start_xmit  = ppp_start_xmit,\n \t.ndo_do_ioctl    = ppp_net_ioctl,\n \t.ndo_get_stats64 = ppp_get_stats64,\n+\t.ndo_fill_forward_path = ppp_fill_forward_path,\n };\n \n static struct device_type ppp_type = {\n--- a/drivers/net/ppp/pppoe.c\n+++ b/drivers/net/ppp/pppoe.c\n@@ -972,8 +972,31 @@ static int pppoe_xmit(struct ppp_channel\n \treturn __pppoe_xmit(sk, skb);\n }\n \n+static int pppoe_fill_forward_path(struct net_device_path_ctx *ctx,\n+\t\t\t\t   struct net_device_path *path,\n+\t\t\t\t   const struct ppp_channel *chan)\n+{\n+\tstruct sock *sk = (struct sock *)chan->private;\n+\tstruct pppox_sock *po = pppox_sk(sk);\n+\tstruct net_device *dev = po->pppoe_dev;\n+\n+\tif (sock_flag(sk, SOCK_DEAD) ||\n+\t    !(sk->sk_state & PPPOX_CONNECTED) || !dev)\n+\t\treturn -1;\n+\n+\tpath->type = DEV_PATH_PPPOE;\n+\tpath->encap.proto = htons(ETH_P_PPP_SES);\n+\tpath->encap.id = be16_to_cpu(po->num);\n+\tmemcpy(path->encap.h_dest, po->pppoe_pa.remote, ETH_ALEN);\n+\tpath->dev = ctx->dev;\n+\tctx->dev = dev;\n+\n+\treturn 0;\n+}\n+\n static const struct ppp_channel_ops pppoe_chan_ops = {\n \t.start_xmit = pppoe_xmit,\n+\t.fill_forward_path = pppoe_fill_forward_path,\n };\n \n static int pppoe_recvmsg(struct socket *sock, struct msghdr *m,\n--- a/include/linux/netdevice.h\n+++ b/include/linux/netdevice.h\n@@ -831,6 +831,7 @@ enum net_device_path_type {\n \tDEV_PATH_ETHERNET = 0,\n \tDEV_PATH_VLAN,\n \tDEV_PATH_BRIDGE,\n+\tDEV_PATH_PPPOE,\n };\n \n struct net_device_path {\n@@ -840,6 +841,7 @@ struct net_device_path {\n \t\tstruct {\n \t\t\tu16\t\tid;\n \t\t\t__be16\t\tproto;\n+\t\t\tu8\t\th_dest[ETH_ALEN];\n \t\t} encap;\n \t\tstruct {\n \t\t\tenum {\n--- a/include/linux/ppp_channel.h\n+++ b/include/linux/ppp_channel.h\n@@ -28,6 +28,9 @@ struct ppp_channel_ops {\n \tint\t(*start_xmit)(struct ppp_channel *, struct sk_buff *);\n \t/* Handle an ioctl call that has come in via /dev/ppp. */\n \tint\t(*ioctl)(struct ppp_channel *, unsigned int, unsigned long);\n+\tint\t(*fill_forward_path)(struct net_device_path_ctx *,\n+\t\t\t\t     struct net_device_path *,\n+\t\t\t\t     const struct ppp_channel *);\n };\n \n struct ppp_channel {\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/610-v5.13-16-net-dsa-resolve-forwarding-path-for-dsa-slave-ports.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nDate: Wed, 24 Mar 2021 02:30:37 +0100\nSubject: [PATCH] net: dsa: resolve forwarding path for dsa slave ports\n\nAdd .ndo_fill_forward_path for dsa slave port devices\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\nSigned-off-by: Pablo Neira Ayuso <pablo@netfilter.org>\n---\n\n--- a/include/linux/netdevice.h\n+++ b/include/linux/netdevice.h\n@@ -832,6 +832,7 @@ enum net_device_path_type {\n \tDEV_PATH_VLAN,\n \tDEV_PATH_BRIDGE,\n \tDEV_PATH_PPPOE,\n+\tDEV_PATH_DSA,\n };\n \n struct net_device_path {\n@@ -852,6 +853,10 @@ struct net_device_path {\n \t\t\tu16\t\tvlan_id;\n \t\t\t__be16\t\tvlan_proto;\n \t\t} bridge;\n+\t\tstruct {\n+\t\t\tint port;\n+\t\t\tu16 proto;\n+\t\t} dsa;\n \t};\n };\n \n--- a/net/dsa/slave.c\n+++ b/net/dsa/slave.c\n@@ -1619,6 +1619,21 @@ static struct devlink_port *dsa_slave_ge\n \treturn dp->ds->devlink ? &dp->devlink_port : NULL;\n }\n \n+static int dsa_slave_fill_forward_path(struct net_device_path_ctx *ctx,\n+\t\t\t\t       struct net_device_path *path)\n+{\n+\tstruct dsa_port *dp = dsa_slave_to_port(ctx->dev);\n+\tstruct dsa_port *cpu_dp = dp->cpu_dp;\n+\n+\tpath->dev = ctx->dev;\n+\tpath->type = DEV_PATH_DSA;\n+\tpath->dsa.proto = cpu_dp->tag_ops->proto;\n+\tpath->dsa.port = dp->index;\n+\tctx->dev = cpu_dp->master;\n+\n+\treturn 0;\n+}\n+\n static const struct net_device_ops dsa_slave_netdev_ops = {\n \t.ndo_open\t \t= dsa_slave_open,\n \t.ndo_stop\t\t= dsa_slave_close,\n@@ -1644,6 +1659,7 @@ static const struct net_device_ops dsa_s\n \t.ndo_vlan_rx_kill_vid\t= dsa_slave_vlan_rx_kill_vid,\n \t.ndo_get_devlink_port\t= dsa_slave_get_devlink_port,\n \t.ndo_change_mtu\t\t= dsa_slave_change_mtu,\n+\t.ndo_fill_forward_path\t= dsa_slave_fill_forward_path,\n };\n \n static struct device_type dsa_type = {\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/610-v5.13-17-netfilter-flowtable-add-xmit-path-types.patch",
    "content": "From: Pablo Neira Ayuso <pablo@netfilter.org>\nDate: Wed, 24 Mar 2021 02:30:38 +0100\nSubject: [PATCH] netfilter: flowtable: add xmit path types\n\nAdd the xmit_type field that defines the two supported xmit paths in the\nflowtable data plane, which are the neighbour and the xfrm xmit paths.\nThis patch prepares for new flowtable xmit path types to come.\n\nSigned-off-by: Pablo Neira Ayuso <pablo@netfilter.org>\n---\n\n--- a/include/net/netfilter/nf_flow_table.h\n+++ b/include/net/netfilter/nf_flow_table.h\n@@ -89,6 +89,11 @@ enum flow_offload_tuple_dir {\n };\n #define FLOW_OFFLOAD_DIR_MAX\tIP_CT_DIR_MAX\n \n+enum flow_offload_xmit_type {\n+\tFLOW_OFFLOAD_XMIT_NEIGH\t\t= 0,\n+\tFLOW_OFFLOAD_XMIT_XFRM,\n+};\n+\n struct flow_offload_tuple {\n \tunion {\n \t\tstruct in_addr\t\tsrc_v4;\n@@ -111,7 +116,8 @@ struct flow_offload_tuple {\n \t/* All members above are keys for lookups, see flow_offload_hash(). */\n \tstruct { }\t\t\t__hash;\n \n-\tu8\t\t\t\tdir;\n+\tu8\t\t\t\tdir:6,\n+\t\t\t\t\txmit_type:2;\n \n \tu16\t\t\t\tmtu;\n \n@@ -157,7 +163,8 @@ static inline __s32 nf_flow_timeout_delt\n \n struct nf_flow_route {\n \tstruct {\n-\t\tstruct dst_entry\t*dst;\n+\t\tstruct dst_entry\t\t*dst;\n+\t\tenum flow_offload_xmit_type\txmit_type;\n \t} tuple[FLOW_OFFLOAD_DIR_MAX];\n };\n \n--- a/net/netfilter/nf_flow_table_core.c\n+++ b/net/netfilter/nf_flow_table_core.c\n@@ -95,6 +95,7 @@ static int flow_offload_fill_route(struc\n \t}\n \n \tflow_tuple->iifidx = other_dst->dev->ifindex;\n+\tflow_tuple->xmit_type = route->tuple[dir].xmit_type;\n \tflow_tuple->dst_cache = dst;\n \n \treturn 0;\n--- a/net/netfilter/nf_flow_table_ip.c\n+++ b/net/netfilter/nf_flow_table_ip.c\n@@ -235,8 +235,6 @@ nf_flow_offload_ip_hook(void *priv, stru\n \n \tdir = tuplehash->tuple.dir;\n \tflow = container_of(tuplehash, struct flow_offload, tuplehash[dir]);\n-\trt = (struct rtable *)flow->tuplehash[dir].tuple.dst_cache;\n-\toutdev = rt->dst.dev;\n \n \tif (unlikely(nf_flow_exceeds_mtu(skb, flow->tuplehash[dir].tuple.mtu)))\n \t\treturn NF_ACCEPT;\n@@ -265,13 +263,16 @@ nf_flow_offload_ip_hook(void *priv, stru\n \tif (flow_table->flags & NF_FLOWTABLE_COUNTER)\n \t\tnf_ct_acct_update(flow->ct, tuplehash->tuple.dir, skb->len);\n \n-\tif (unlikely(dst_xfrm(&rt->dst))) {\n+\trt = (struct rtable *)tuplehash->tuple.dst_cache;\n+\n+\tif (unlikely(tuplehash->tuple.xmit_type == FLOW_OFFLOAD_XMIT_XFRM)) {\n \t\tmemset(skb->cb, 0, sizeof(struct inet_skb_parm));\n \t\tIPCB(skb)->iif = skb->dev->ifindex;\n \t\tIPCB(skb)->flags = IPSKB_FORWARDED;\n \t\treturn nf_flow_xmit_xfrm(skb, state, &rt->dst);\n \t}\n \n+\toutdev = rt->dst.dev;\n \tskb->dev = outdev;\n \tnexthop = rt_nexthop(rt, flow->tuplehash[!dir].tuple.src_v4.s_addr);\n \tskb_dst_set_noref(skb, &rt->dst);\n@@ -456,8 +457,6 @@ nf_flow_offload_ipv6_hook(void *priv, st\n \n \tdir = tuplehash->tuple.dir;\n \tflow = container_of(tuplehash, struct flow_offload, tuplehash[dir]);\n-\trt = (struct rt6_info *)flow->tuplehash[dir].tuple.dst_cache;\n-\toutdev = rt->dst.dev;\n \n \tif (unlikely(nf_flow_exceeds_mtu(skb, flow->tuplehash[dir].tuple.mtu)))\n \t\treturn NF_ACCEPT;\n@@ -485,13 +484,16 @@ nf_flow_offload_ipv6_hook(void *priv, st\n \tif (flow_table->flags & NF_FLOWTABLE_COUNTER)\n \t\tnf_ct_acct_update(flow->ct, tuplehash->tuple.dir, skb->len);\n \n-\tif (unlikely(dst_xfrm(&rt->dst))) {\n+\trt = (struct rt6_info *)tuplehash->tuple.dst_cache;\n+\n+\tif (unlikely(tuplehash->tuple.xmit_type == FLOW_OFFLOAD_XMIT_XFRM)) {\n \t\tmemset(skb->cb, 0, sizeof(struct inet6_skb_parm));\n \t\tIP6CB(skb)->iif = skb->dev->ifindex;\n \t\tIP6CB(skb)->flags = IP6SKB_FORWARDED;\n \t\treturn nf_flow_xmit_xfrm(skb, state, &rt->dst);\n \t}\n \n+\toutdev = rt->dst.dev;\n \tskb->dev = outdev;\n \tnexthop = rt6_nexthop(rt, &flow->tuplehash[!dir].tuple.src_v6);\n \tskb_dst_set_noref(skb, &rt->dst);\n--- a/net/netfilter/nft_flow_offload.c\n+++ b/net/netfilter/nft_flow_offload.c\n@@ -19,6 +19,22 @@ struct nft_flow_offload {\n \tstruct nft_flowtable\t*flowtable;\n };\n \n+static enum flow_offload_xmit_type nft_xmit_type(struct dst_entry *dst)\n+{\n+\tif (dst_xfrm(dst))\n+\t\treturn FLOW_OFFLOAD_XMIT_XFRM;\n+\n+\treturn FLOW_OFFLOAD_XMIT_NEIGH;\n+}\n+\n+static void nft_default_forward_path(struct nf_flow_route *route,\n+\t\t\t\t     struct dst_entry *dst_cache,\n+\t\t\t\t     enum ip_conntrack_dir dir)\n+{\n+\troute->tuple[dir].dst\t\t= dst_cache;\n+\troute->tuple[dir].xmit_type\t= nft_xmit_type(dst_cache);\n+}\n+\n static int nft_flow_route(const struct nft_pktinfo *pkt,\n \t\t\t  const struct nf_conn *ct,\n \t\t\t  struct nf_flow_route *route,\n@@ -44,8 +60,8 @@ static int nft_flow_route(const struct n\n \tif (!other_dst)\n \t\treturn -ENOENT;\n \n-\troute->tuple[dir].dst\t\t= this_dst;\n-\troute->tuple[!dir].dst\t\t= other_dst;\n+\tnft_default_forward_path(route, this_dst, dir);\n+\tnft_default_forward_path(route, other_dst, !dir);\n \n \treturn 0;\n }\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/610-v5.13-18-netfilter-flowtable-use-dev_fill_forward_path-to-obt.patch",
    "content": "From: Pablo Neira Ayuso <pablo@netfilter.org>\nDate: Wed, 24 Mar 2021 02:30:39 +0100\nSubject: [PATCH] netfilter: flowtable: use dev_fill_forward_path() to\n obtain ingress device\n\nObtain the ingress device in the tuple from the route in the reply\ndirection. Use dev_fill_forward_path() instead to get the real ingress\ndevice for this flow.\n\nFall back to use the ingress device that the IP forwarding route\nprovides if:\n\n- dev_fill_forward_path() finds no real ingress device.\n- the ingress device that is obtained is not part of the flowtable\n  devices.\n- this route has a xfrm policy.\n\nSigned-off-by: Pablo Neira Ayuso <pablo@netfilter.org>\n---\n\n--- a/include/net/netfilter/nf_flow_table.h\n+++ b/include/net/netfilter/nf_flow_table.h\n@@ -164,6 +164,9 @@ static inline __s32 nf_flow_timeout_delt\n struct nf_flow_route {\n \tstruct {\n \t\tstruct dst_entry\t\t*dst;\n+\t\tstruct {\n+\t\t\tu32\t\t\tifindex;\n+\t\t} in;\n \t\tenum flow_offload_xmit_type\txmit_type;\n \t} tuple[FLOW_OFFLOAD_DIR_MAX];\n };\n--- a/net/netfilter/nf_flow_table_core.c\n+++ b/net/netfilter/nf_flow_table_core.c\n@@ -79,7 +79,6 @@ static int flow_offload_fill_route(struc\n \t\t\t\t   enum flow_offload_tuple_dir dir)\n {\n \tstruct flow_offload_tuple *flow_tuple = &flow->tuplehash[dir].tuple;\n-\tstruct dst_entry *other_dst = route->tuple[!dir].dst;\n \tstruct dst_entry *dst = route->tuple[dir].dst;\n \n \tif (!dst_hold_safe(route->tuple[dir].dst))\n@@ -94,7 +93,7 @@ static int flow_offload_fill_route(struc\n \t\tbreak;\n \t}\n \n-\tflow_tuple->iifidx = other_dst->dev->ifindex;\n+\tflow_tuple->iifidx = route->tuple[dir].in.ifindex;\n \tflow_tuple->xmit_type = route->tuple[dir].xmit_type;\n \tflow_tuple->dst_cache = dst;\n \n--- a/net/netfilter/nft_flow_offload.c\n+++ b/net/netfilter/nft_flow_offload.c\n@@ -31,14 +31,104 @@ static void nft_default_forward_path(str\n \t\t\t\t     struct dst_entry *dst_cache,\n \t\t\t\t     enum ip_conntrack_dir dir)\n {\n+\troute->tuple[!dir].in.ifindex\t= dst_cache->dev->ifindex;\n \troute->tuple[dir].dst\t\t= dst_cache;\n \troute->tuple[dir].xmit_type\t= nft_xmit_type(dst_cache);\n }\n \n+static int nft_dev_fill_forward_path(const struct nf_flow_route *route,\n+\t\t\t\t     const struct dst_entry *dst_cache,\n+\t\t\t\t     const struct nf_conn *ct,\n+\t\t\t\t     enum ip_conntrack_dir dir,\n+\t\t\t\t     struct net_device_path_stack *stack)\n+{\n+\tconst void *daddr = &ct->tuplehash[!dir].tuple.src.u3;\n+\tstruct net_device *dev = dst_cache->dev;\n+\tunsigned char ha[ETH_ALEN];\n+\tstruct neighbour *n;\n+\tu8 nud_state;\n+\n+\tn = dst_neigh_lookup(dst_cache, daddr);\n+\tif (!n)\n+\t\treturn -1;\n+\n+\tread_lock_bh(&n->lock);\n+\tnud_state = n->nud_state;\n+\tether_addr_copy(ha, n->ha);\n+\tread_unlock_bh(&n->lock);\n+\tneigh_release(n);\n+\n+\tif (!(nud_state & NUD_VALID))\n+\t\treturn -1;\n+\n+\treturn dev_fill_forward_path(dev, ha, stack);\n+}\n+\n+struct nft_forward_info {\n+\tconst struct net_device *indev;\n+};\n+\n+static void nft_dev_path_info(const struct net_device_path_stack *stack,\n+\t\t\t      struct nft_forward_info *info)\n+{\n+\tconst struct net_device_path *path;\n+\tint i;\n+\n+\tfor (i = 0; i < stack->num_paths; i++) {\n+\t\tpath = &stack->path[i];\n+\t\tswitch (path->type) {\n+\t\tcase DEV_PATH_ETHERNET:\n+\t\t\tinfo->indev = path->dev;\n+\t\t\tbreak;\n+\t\tcase DEV_PATH_VLAN:\n+\t\tcase DEV_PATH_BRIDGE:\n+\t\tdefault:\n+\t\t\tinfo->indev = NULL;\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+}\n+\n+static bool nft_flowtable_find_dev(const struct net_device *dev,\n+\t\t\t\t   struct nft_flowtable *ft)\n+{\n+\tstruct nft_hook *hook;\n+\tbool found = false;\n+\n+\tlist_for_each_entry_rcu(hook, &ft->hook_list, list) {\n+\t\tif (hook->ops.dev != dev)\n+\t\t\tcontinue;\n+\n+\t\tfound = true;\n+\t\tbreak;\n+\t}\n+\n+\treturn found;\n+}\n+\n+static void nft_dev_forward_path(struct nf_flow_route *route,\n+\t\t\t\t const struct nf_conn *ct,\n+\t\t\t\t enum ip_conntrack_dir dir,\n+\t\t\t\t struct nft_flowtable *ft)\n+{\n+\tconst struct dst_entry *dst = route->tuple[dir].dst;\n+\tstruct net_device_path_stack stack;\n+\tstruct nft_forward_info info = {};\n+\n+\tif (nft_dev_fill_forward_path(route, dst, ct, dir, &stack) >= 0)\n+\t\tnft_dev_path_info(&stack, &info);\n+\n+\tif (!info.indev || !nft_flowtable_find_dev(info.indev, ft))\n+\t\treturn;\n+\n+\troute->tuple[!dir].in.ifindex = info.indev->ifindex;\n+}\n+\n static int nft_flow_route(const struct nft_pktinfo *pkt,\n \t\t\t  const struct nf_conn *ct,\n \t\t\t  struct nf_flow_route *route,\n-\t\t\t  enum ip_conntrack_dir dir)\n+\t\t\t  enum ip_conntrack_dir dir,\n+\t\t\t  struct nft_flowtable *ft)\n {\n \tstruct dst_entry *this_dst = skb_dst(pkt->skb);\n \tstruct dst_entry *other_dst = NULL;\n@@ -63,6 +153,12 @@ static int nft_flow_route(const struct n\n \tnft_default_forward_path(route, this_dst, dir);\n \tnft_default_forward_path(route, other_dst, !dir);\n \n+\tif (route->tuple[dir].xmit_type\t== FLOW_OFFLOAD_XMIT_NEIGH &&\n+\t    route->tuple[!dir].xmit_type == FLOW_OFFLOAD_XMIT_NEIGH) {\n+\t\tnft_dev_forward_path(route, ct, dir, ft);\n+\t\tnft_dev_forward_path(route, ct, !dir, ft);\n+\t}\n+\n \treturn 0;\n }\n \n@@ -90,8 +186,8 @@ static void nft_flow_offload_eval(const\n \tstruct nft_flow_offload *priv = nft_expr_priv(expr);\n \tstruct nf_flowtable *flowtable = &priv->flowtable->data;\n \tstruct tcphdr _tcph, *tcph = NULL;\n+\tstruct nf_flow_route route = {};\n \tenum ip_conntrack_info ctinfo;\n-\tstruct nf_flow_route route;\n \tstruct flow_offload *flow;\n \tenum ip_conntrack_dir dir;\n \tstruct nf_conn *ct;\n@@ -128,7 +224,7 @@ static void nft_flow_offload_eval(const\n \t\tgoto out;\n \n \tdir = CTINFO2DIR(ctinfo);\n-\tif (nft_flow_route(pkt, ct, &route, dir) < 0)\n+\tif (nft_flow_route(pkt, ct, &route, dir, priv->flowtable) < 0)\n \t\tgoto err_flow_route;\n \n \tflow = flow_offload_alloc(ct);\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/610-v5.13-19-netfilter-flowtable-use-dev_fill_forward_path-to-obt.patch",
    "content": "From: Pablo Neira Ayuso <pablo@netfilter.org>\nDate: Wed, 24 Mar 2021 02:30:40 +0100\nSubject: [PATCH] netfilter: flowtable: use dev_fill_forward_path() to\n obtain egress device\n\nThe egress device in the tuple is obtained from route. Use\ndev_fill_forward_path() instead to provide the real egress device for\nthis flow whenever this is available.\n\nThe new FLOW_OFFLOAD_XMIT_DIRECT type uses dev_queue_xmit() to transmit\nethernet frames. Cache the source and destination hardware address to\nuse dev_queue_xmit() to transfer packets.\n\nThe FLOW_OFFLOAD_XMIT_DIRECT replaces FLOW_OFFLOAD_XMIT_NEIGH if\ndev_fill_forward_path() finds a direct transmit path.\n\nIn case of topology updates, if peer is moved to different bridge port,\nthe connection will time out, reconnect will result in a new entry with\nthe correct path. Snooping fdb updates would allow for cleaning up stale\nflowtable entries.\n\nSigned-off-by: Pablo Neira Ayuso <pablo@netfilter.org>\n---\n\n--- a/include/net/netfilter/nf_flow_table.h\n+++ b/include/net/netfilter/nf_flow_table.h\n@@ -92,6 +92,7 @@ enum flow_offload_tuple_dir {\n enum flow_offload_xmit_type {\n \tFLOW_OFFLOAD_XMIT_NEIGH\t\t= 0,\n \tFLOW_OFFLOAD_XMIT_XFRM,\n+\tFLOW_OFFLOAD_XMIT_DIRECT,\n };\n \n struct flow_offload_tuple {\n@@ -120,8 +121,14 @@ struct flow_offload_tuple {\n \t\t\t\t\txmit_type:2;\n \n \tu16\t\t\t\tmtu;\n-\n-\tstruct dst_entry\t\t*dst_cache;\n+\tunion {\n+\t\tstruct dst_entry\t*dst_cache;\n+\t\tstruct {\n+\t\t\tu32\t\tifidx;\n+\t\t\tu8\t\th_source[ETH_ALEN];\n+\t\t\tu8\t\th_dest[ETH_ALEN];\n+\t\t} out;\n+\t};\n };\n \n struct flow_offload_tuple_rhash {\n@@ -167,6 +174,11 @@ struct nf_flow_route {\n \t\tstruct {\n \t\t\tu32\t\t\tifindex;\n \t\t} in;\n+\t\tstruct {\n+\t\t\tu32\t\t\tifindex;\n+\t\t\tu8\t\t\th_source[ETH_ALEN];\n+\t\t\tu8\t\t\th_dest[ETH_ALEN];\n+\t\t} out;\n \t\tenum flow_offload_xmit_type\txmit_type;\n \t} tuple[FLOW_OFFLOAD_DIR_MAX];\n };\n--- a/net/netfilter/nf_flow_table_core.c\n+++ b/net/netfilter/nf_flow_table_core.c\n@@ -81,9 +81,6 @@ static int flow_offload_fill_route(struc\n \tstruct flow_offload_tuple *flow_tuple = &flow->tuplehash[dir].tuple;\n \tstruct dst_entry *dst = route->tuple[dir].dst;\n \n-\tif (!dst_hold_safe(route->tuple[dir].dst))\n-\t\treturn -1;\n-\n \tswitch (flow_tuple->l3proto) {\n \tcase NFPROTO_IPV4:\n \t\tflow_tuple->mtu = ip_dst_mtu_maybe_forward(dst, true);\n@@ -94,12 +91,36 @@ static int flow_offload_fill_route(struc\n \t}\n \n \tflow_tuple->iifidx = route->tuple[dir].in.ifindex;\n+\n+\tswitch (route->tuple[dir].xmit_type) {\n+\tcase FLOW_OFFLOAD_XMIT_DIRECT:\n+\t\tmemcpy(flow_tuple->out.h_dest, route->tuple[dir].out.h_dest,\n+\t\t       ETH_ALEN);\n+\t\tmemcpy(flow_tuple->out.h_source, route->tuple[dir].out.h_source,\n+\t\t       ETH_ALEN);\n+\t\tflow_tuple->out.ifidx = route->tuple[dir].out.ifindex;\n+\t\tbreak;\n+\tcase FLOW_OFFLOAD_XMIT_XFRM:\n+\tcase FLOW_OFFLOAD_XMIT_NEIGH:\n+\t\tif (!dst_hold_safe(route->tuple[dir].dst))\n+\t\t\treturn -1;\n+\n+\t\tflow_tuple->dst_cache = dst;\n+\t\tbreak;\n+\t}\n \tflow_tuple->xmit_type = route->tuple[dir].xmit_type;\n-\tflow_tuple->dst_cache = dst;\n \n \treturn 0;\n }\n \n+static void nft_flow_dst_release(struct flow_offload *flow,\n+\t\t\t\t enum flow_offload_tuple_dir dir)\n+{\n+\tif (flow->tuplehash[dir].tuple.xmit_type == FLOW_OFFLOAD_XMIT_NEIGH ||\n+\t    flow->tuplehash[dir].tuple.xmit_type == FLOW_OFFLOAD_XMIT_XFRM)\n+\t\tdst_release(flow->tuplehash[dir].tuple.dst_cache);\n+}\n+\n int flow_offload_route_init(struct flow_offload *flow,\n \t\t\t    const struct nf_flow_route *route)\n {\n@@ -118,7 +139,7 @@ int flow_offload_route_init(struct flow_\n \treturn 0;\n \n err_route_reply:\n-\tdst_release(route->tuple[FLOW_OFFLOAD_DIR_ORIGINAL].dst);\n+\tnft_flow_dst_release(flow, FLOW_OFFLOAD_DIR_ORIGINAL);\n \n \treturn err;\n }\n@@ -169,8 +190,8 @@ static void flow_offload_fixup_ct(struct\n \n static void flow_offload_route_release(struct flow_offload *flow)\n {\n-\tdst_release(flow->tuplehash[FLOW_OFFLOAD_DIR_ORIGINAL].tuple.dst_cache);\n-\tdst_release(flow->tuplehash[FLOW_OFFLOAD_DIR_REPLY].tuple.dst_cache);\n+\tnft_flow_dst_release(flow, FLOW_OFFLOAD_DIR_ORIGINAL);\n+\tnft_flow_dst_release(flow, FLOW_OFFLOAD_DIR_REPLY);\n }\n \n void flow_offload_free(struct flow_offload *flow)\n--- a/net/netfilter/nf_flow_table_ip.c\n+++ b/net/netfilter/nf_flow_table_ip.c\n@@ -207,6 +207,24 @@ static unsigned int nf_flow_xmit_xfrm(st\n \treturn NF_STOLEN;\n }\n \n+static unsigned int nf_flow_queue_xmit(struct net *net, struct sk_buff *skb,\n+\t\t\t\t       const struct flow_offload_tuple_rhash *tuplehash,\n+\t\t\t\t       unsigned short type)\n+{\n+\tstruct net_device *outdev;\n+\n+\toutdev = dev_get_by_index_rcu(net, tuplehash->tuple.out.ifidx);\n+\tif (!outdev)\n+\t\treturn NF_DROP;\n+\n+\tskb->dev = outdev;\n+\tdev_hard_header(skb, skb->dev, type, tuplehash->tuple.out.h_dest,\n+\t\t\ttuplehash->tuple.out.h_source, skb->len);\n+\tdev_queue_xmit(skb);\n+\n+\treturn NF_STOLEN;\n+}\n+\n unsigned int\n nf_flow_offload_ip_hook(void *priv, struct sk_buff *skb,\n \t\t\tconst struct nf_hook_state *state)\n@@ -222,6 +240,7 @@ nf_flow_offload_ip_hook(void *priv, stru\n \tstruct iphdr *iph;\n \t__be32 nexthop;\n \tu32 hdrsize;\n+\tint ret;\n \n \tif (skb->protocol != htons(ETH_P_IP))\n \t\treturn NF_ACCEPT;\n@@ -244,9 +263,13 @@ nf_flow_offload_ip_hook(void *priv, stru\n \tif (nf_flow_state_check(flow, iph->protocol, skb, thoff))\n \t\treturn NF_ACCEPT;\n \n-\tif (!dst_check(&rt->dst, 0)) {\n-\t\tflow_offload_teardown(flow);\n-\t\treturn NF_ACCEPT;\n+\tif (tuplehash->tuple.xmit_type == FLOW_OFFLOAD_XMIT_NEIGH ||\n+\t    tuplehash->tuple.xmit_type == FLOW_OFFLOAD_XMIT_XFRM) {\n+\t\trt = (struct rtable *)tuplehash->tuple.dst_cache;\n+\t\tif (!dst_check(&rt->dst, 0)) {\n+\t\t\tflow_offload_teardown(flow);\n+\t\t\treturn NF_ACCEPT;\n+\t\t}\n \t}\n \n \tif (skb_try_make_writable(skb, thoff + hdrsize))\n@@ -263,8 +286,6 @@ nf_flow_offload_ip_hook(void *priv, stru\n \tif (flow_table->flags & NF_FLOWTABLE_COUNTER)\n \t\tnf_ct_acct_update(flow->ct, tuplehash->tuple.dir, skb->len);\n \n-\trt = (struct rtable *)tuplehash->tuple.dst_cache;\n-\n \tif (unlikely(tuplehash->tuple.xmit_type == FLOW_OFFLOAD_XMIT_XFRM)) {\n \t\tmemset(skb->cb, 0, sizeof(struct inet_skb_parm));\n \t\tIPCB(skb)->iif = skb->dev->ifindex;\n@@ -272,13 +293,23 @@ nf_flow_offload_ip_hook(void *priv, stru\n \t\treturn nf_flow_xmit_xfrm(skb, state, &rt->dst);\n \t}\n \n-\toutdev = rt->dst.dev;\n-\tskb->dev = outdev;\n-\tnexthop = rt_nexthop(rt, flow->tuplehash[!dir].tuple.src_v4.s_addr);\n-\tskb_dst_set_noref(skb, &rt->dst);\n-\tneigh_xmit(NEIGH_ARP_TABLE, outdev, &nexthop, skb);\n+\tswitch (tuplehash->tuple.xmit_type) {\n+\tcase FLOW_OFFLOAD_XMIT_NEIGH:\n+\t\toutdev = rt->dst.dev;\n+\t\tskb->dev = outdev;\n+\t\tnexthop = rt_nexthop(rt, flow->tuplehash[!dir].tuple.src_v4.s_addr);\n+\t\tskb_dst_set_noref(skb, &rt->dst);\n+\t\tneigh_xmit(NEIGH_ARP_TABLE, outdev, &nexthop, skb);\n+\t\tret = NF_STOLEN;\n+\t\tbreak;\n+\tcase FLOW_OFFLOAD_XMIT_DIRECT:\n+\t\tret = nf_flow_queue_xmit(state->net, skb, tuplehash, ETH_P_IP);\n+\t\tif (ret == NF_DROP)\n+\t\t\tflow_offload_teardown(flow);\n+\t\tbreak;\n+\t}\n \n-\treturn NF_STOLEN;\n+\treturn ret;\n }\n EXPORT_SYMBOL_GPL(nf_flow_offload_ip_hook);\n \n@@ -444,6 +475,7 @@ nf_flow_offload_ipv6_hook(void *priv, st\n \tstruct ipv6hdr *ip6h;\n \tstruct rt6_info *rt;\n \tu32 hdrsize;\n+\tint ret;\n \n \tif (skb->protocol != htons(ETH_P_IPV6))\n \t\treturn NF_ACCEPT;\n@@ -465,9 +497,13 @@ nf_flow_offload_ipv6_hook(void *priv, st\n \t\t\t\tsizeof(*ip6h)))\n \t\treturn NF_ACCEPT;\n \n-\tif (!dst_check(&rt->dst, 0)) {\n-\t\tflow_offload_teardown(flow);\n-\t\treturn NF_ACCEPT;\n+\tif (tuplehash->tuple.xmit_type == FLOW_OFFLOAD_XMIT_NEIGH ||\n+\t    tuplehash->tuple.xmit_type == FLOW_OFFLOAD_XMIT_XFRM) {\n+\t\trt = (struct rt6_info *)tuplehash->tuple.dst_cache;\n+\t\tif (!dst_check(&rt->dst, 0)) {\n+\t\t\tflow_offload_teardown(flow);\n+\t\t\treturn NF_ACCEPT;\n+\t\t}\n \t}\n \n \tif (skb_try_make_writable(skb, sizeof(*ip6h) + hdrsize))\n@@ -484,8 +520,6 @@ nf_flow_offload_ipv6_hook(void *priv, st\n \tif (flow_table->flags & NF_FLOWTABLE_COUNTER)\n \t\tnf_ct_acct_update(flow->ct, tuplehash->tuple.dir, skb->len);\n \n-\trt = (struct rt6_info *)tuplehash->tuple.dst_cache;\n-\n \tif (unlikely(tuplehash->tuple.xmit_type == FLOW_OFFLOAD_XMIT_XFRM)) {\n \t\tmemset(skb->cb, 0, sizeof(struct inet6_skb_parm));\n \t\tIP6CB(skb)->iif = skb->dev->ifindex;\n@@ -493,12 +527,22 @@ nf_flow_offload_ipv6_hook(void *priv, st\n \t\treturn nf_flow_xmit_xfrm(skb, state, &rt->dst);\n \t}\n \n-\toutdev = rt->dst.dev;\n-\tskb->dev = outdev;\n-\tnexthop = rt6_nexthop(rt, &flow->tuplehash[!dir].tuple.src_v6);\n-\tskb_dst_set_noref(skb, &rt->dst);\n-\tneigh_xmit(NEIGH_ND_TABLE, outdev, nexthop, skb);\n+\tswitch (tuplehash->tuple.xmit_type) {\n+\tcase FLOW_OFFLOAD_XMIT_NEIGH:\n+\t\toutdev = rt->dst.dev;\n+\t\tskb->dev = outdev;\n+\t\tnexthop = rt6_nexthop(rt, &flow->tuplehash[!dir].tuple.src_v6);\n+\t\tskb_dst_set_noref(skb, &rt->dst);\n+\t\tneigh_xmit(NEIGH_ND_TABLE, outdev, nexthop, skb);\n+\t\tret = NF_STOLEN;\n+\t\tbreak;\n+\tcase FLOW_OFFLOAD_XMIT_DIRECT:\n+\t\tret = nf_flow_queue_xmit(state->net, skb, tuplehash, ETH_P_IPV6);\n+\t\tif (ret == NF_DROP)\n+\t\t\tflow_offload_teardown(flow);\n+\t\tbreak;\n+\t}\n \n-\treturn NF_STOLEN;\n+\treturn ret;\n }\n EXPORT_SYMBOL_GPL(nf_flow_offload_ipv6_hook);\n--- a/net/netfilter/nft_flow_offload.c\n+++ b/net/netfilter/nft_flow_offload.c\n@@ -39,12 +39,11 @@ static void nft_default_forward_path(str\n static int nft_dev_fill_forward_path(const struct nf_flow_route *route,\n \t\t\t\t     const struct dst_entry *dst_cache,\n \t\t\t\t     const struct nf_conn *ct,\n-\t\t\t\t     enum ip_conntrack_dir dir,\n+\t\t\t\t     enum ip_conntrack_dir dir, u8 *ha,\n \t\t\t\t     struct net_device_path_stack *stack)\n {\n \tconst void *daddr = &ct->tuplehash[!dir].tuple.src.u3;\n \tstruct net_device *dev = dst_cache->dev;\n-\tunsigned char ha[ETH_ALEN];\n \tstruct neighbour *n;\n \tu8 nud_state;\n \n@@ -66,27 +65,43 @@ static int nft_dev_fill_forward_path(con\n \n struct nft_forward_info {\n \tconst struct net_device *indev;\n+\tconst struct net_device *outdev;\n+\tu8 h_source[ETH_ALEN];\n+\tu8 h_dest[ETH_ALEN];\n+\tenum flow_offload_xmit_type xmit_type;\n };\n \n static void nft_dev_path_info(const struct net_device_path_stack *stack,\n-\t\t\t      struct nft_forward_info *info)\n+\t\t\t      struct nft_forward_info *info,\n+\t\t\t      unsigned char *ha)\n {\n \tconst struct net_device_path *path;\n \tint i;\n \n+\tmemcpy(info->h_dest, ha, ETH_ALEN);\n+\n \tfor (i = 0; i < stack->num_paths; i++) {\n \t\tpath = &stack->path[i];\n \t\tswitch (path->type) {\n \t\tcase DEV_PATH_ETHERNET:\n \t\t\tinfo->indev = path->dev;\n+\t\t\tif (is_zero_ether_addr(info->h_source))\n+\t\t\t\tmemcpy(info->h_source, path->dev->dev_addr, ETH_ALEN);\n \t\t\tbreak;\n-\t\tcase DEV_PATH_VLAN:\n \t\tcase DEV_PATH_BRIDGE:\n+\t\t\tif (is_zero_ether_addr(info->h_source))\n+\t\t\t\tmemcpy(info->h_source, path->dev->dev_addr, ETH_ALEN);\n+\n+\t\t\tinfo->xmit_type = FLOW_OFFLOAD_XMIT_DIRECT;\n+\t\t\tbreak;\n+\t\tcase DEV_PATH_VLAN:\n \t\tdefault:\n \t\t\tinfo->indev = NULL;\n \t\t\tbreak;\n \t\t}\n \t}\n+\tif (!info->outdev)\n+\t\tinfo->outdev = info->indev;\n }\n \n static bool nft_flowtable_find_dev(const struct net_device *dev,\n@@ -114,14 +129,22 @@ static void nft_dev_forward_path(struct\n \tconst struct dst_entry *dst = route->tuple[dir].dst;\n \tstruct net_device_path_stack stack;\n \tstruct nft_forward_info info = {};\n+\tunsigned char ha[ETH_ALEN];\n \n-\tif (nft_dev_fill_forward_path(route, dst, ct, dir, &stack) >= 0)\n-\t\tnft_dev_path_info(&stack, &info);\n+\tif (nft_dev_fill_forward_path(route, dst, ct, dir, ha, &stack) >= 0)\n+\t\tnft_dev_path_info(&stack, &info, ha);\n \n \tif (!info.indev || !nft_flowtable_find_dev(info.indev, ft))\n \t\treturn;\n \n \troute->tuple[!dir].in.ifindex = info.indev->ifindex;\n+\n+\tif (info.xmit_type == FLOW_OFFLOAD_XMIT_DIRECT) {\n+\t\tmemcpy(route->tuple[dir].out.h_source, info.h_source, ETH_ALEN);\n+\t\tmemcpy(route->tuple[dir].out.h_dest, info.h_dest, ETH_ALEN);\n+\t\troute->tuple[dir].out.ifindex = info.outdev->ifindex;\n+\t\troute->tuple[dir].xmit_type = info.xmit_type;\n+\t}\n }\n \n static int nft_flow_route(const struct nft_pktinfo *pkt,\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/610-v5.13-20-netfilter-flowtable-add-vlan-support.patch",
    "content": "From: Pablo Neira Ayuso <pablo@netfilter.org>\nDate: Wed, 24 Mar 2021 02:30:41 +0100\nSubject: [PATCH] netfilter: flowtable: add vlan support\n\nAdd the vlan id and protocol to the flow tuple to uniquely identify\nflows from the receive path. For the transmit path, dev_hard_header() on\nthe vlan device push the headers. This patch includes support for two\nvlan headers (QinQ) from the ingress path.\n\nAdd a generic encap field to the flowtable entry which stores the\nprotocol and the tag id. This allows to reuse these fields in the PPPoE\nsupport coming in a later patch.\n\nSigned-off-by: Pablo Neira Ayuso <pablo@netfilter.org>\n---\n\n--- a/include/net/netfilter/nf_flow_table.h\n+++ b/include/net/netfilter/nf_flow_table.h\n@@ -95,6 +95,8 @@ enum flow_offload_xmit_type {\n \tFLOW_OFFLOAD_XMIT_DIRECT,\n };\n \n+#define NF_FLOW_TABLE_ENCAP_MAX\t\t2\n+\n struct flow_offload_tuple {\n \tunion {\n \t\tstruct in_addr\t\tsrc_v4;\n@@ -113,13 +115,17 @@ struct flow_offload_tuple {\n \n \tu8\t\t\t\tl3proto;\n \tu8\t\t\t\tl4proto;\n+\tstruct {\n+\t\tu16\t\t\tid;\n+\t\t__be16\t\t\tproto;\n+\t} encap[NF_FLOW_TABLE_ENCAP_MAX];\n \n \t/* All members above are keys for lookups, see flow_offload_hash(). */\n \tstruct { }\t\t\t__hash;\n \n-\tu8\t\t\t\tdir:6,\n-\t\t\t\t\txmit_type:2;\n-\n+\tu8\t\t\t\tdir:4,\n+\t\t\t\t\txmit_type:2,\n+\t\t\t\t\tencap_num:2;\n \tu16\t\t\t\tmtu;\n \tunion {\n \t\tstruct dst_entry\t*dst_cache;\n@@ -173,6 +179,11 @@ struct nf_flow_route {\n \t\tstruct dst_entry\t\t*dst;\n \t\tstruct {\n \t\t\tu32\t\t\tifindex;\n+\t\t\tstruct {\n+\t\t\t\tu16\t\tid;\n+\t\t\t\t__be16\t\tproto;\n+\t\t\t} encap[NF_FLOW_TABLE_ENCAP_MAX];\n+\t\t\tu8\t\t\tnum_encaps;\n \t\t} in;\n \t\tstruct {\n \t\t\tu32\t\t\tifindex;\n--- a/net/netfilter/nf_flow_table_core.c\n+++ b/net/netfilter/nf_flow_table_core.c\n@@ -80,6 +80,7 @@ static int flow_offload_fill_route(struc\n {\n \tstruct flow_offload_tuple *flow_tuple = &flow->tuplehash[dir].tuple;\n \tstruct dst_entry *dst = route->tuple[dir].dst;\n+\tint i, j = 0;\n \n \tswitch (flow_tuple->l3proto) {\n \tcase NFPROTO_IPV4:\n@@ -91,6 +92,12 @@ static int flow_offload_fill_route(struc\n \t}\n \n \tflow_tuple->iifidx = route->tuple[dir].in.ifindex;\n+\tfor (i = route->tuple[dir].in.num_encaps - 1; i >= 0; i--) {\n+\t\tflow_tuple->encap[j].id = route->tuple[dir].in.encap[i].id;\n+\t\tflow_tuple->encap[j].proto = route->tuple[dir].in.encap[i].proto;\n+\t\tj++;\n+\t}\n+\tflow_tuple->encap_num = route->tuple[dir].in.num_encaps;\n \n \tswitch (route->tuple[dir].xmit_type) {\n \tcase FLOW_OFFLOAD_XMIT_DIRECT:\n--- a/net/netfilter/nf_flow_table_ip.c\n+++ b/net/netfilter/nf_flow_table_ip.c\n@@ -136,23 +136,44 @@ static bool ip_has_options(unsigned int\n \treturn thoff != sizeof(struct iphdr);\n }\n \n+static void nf_flow_tuple_encap(struct sk_buff *skb,\n+\t\t\t\tstruct flow_offload_tuple *tuple)\n+{\n+\tint i = 0;\n+\n+\tif (skb_vlan_tag_present(skb)) {\n+\t\ttuple->encap[i].id = skb_vlan_tag_get(skb);\n+\t\ttuple->encap[i].proto = skb->vlan_proto;\n+\t\ti++;\n+\t}\n+\tif (skb->protocol == htons(ETH_P_8021Q)) {\n+\t\tstruct vlan_ethhdr *veth = (struct vlan_ethhdr *)skb_mac_header(skb);\n+\n+\t\ttuple->encap[i].id = ntohs(veth->h_vlan_TCI);\n+\t\ttuple->encap[i].proto = skb->protocol;\n+\t}\n+}\n+\n static int nf_flow_tuple_ip(struct sk_buff *skb, const struct net_device *dev,\n-\t\t\t    struct flow_offload_tuple *tuple, u32 *hdrsize)\n+\t\t\t    struct flow_offload_tuple *tuple, u32 *hdrsize,\n+\t\t\t    u32 offset)\n {\n \tstruct flow_ports *ports;\n \tunsigned int thoff;\n \tstruct iphdr *iph;\n \n-\tif (!pskb_may_pull(skb, sizeof(*iph)))\n+\tif (!pskb_may_pull(skb, sizeof(*iph) + offset))\n \t\treturn -1;\n \n-\tiph = ip_hdr(skb);\n-\tthoff = iph->ihl * 4;\n+\tiph = (struct iphdr *)(skb_network_header(skb) + offset);\n+\tthoff = (iph->ihl * 4);\n \n \tif (ip_is_fragment(iph) ||\n \t    unlikely(ip_has_options(thoff)))\n \t\treturn -1;\n \n+\tthoff += offset;\n+\n \tswitch (iph->protocol) {\n \tcase IPPROTO_TCP:\n \t\t*hdrsize = sizeof(struct tcphdr);\n@@ -167,11 +188,10 @@ static int nf_flow_tuple_ip(struct sk_bu\n \tif (iph->ttl <= 1)\n \t\treturn -1;\n \n-\tthoff = iph->ihl * 4;\n \tif (!pskb_may_pull(skb, thoff + *hdrsize))\n \t\treturn -1;\n \n-\tiph = ip_hdr(skb);\n+\tiph = (struct iphdr *)(skb_network_header(skb) + offset);\n \tports = (struct flow_ports *)(skb_network_header(skb) + thoff);\n \n \ttuple->src_v4.s_addr\t= iph->saddr;\n@@ -181,6 +201,7 @@ static int nf_flow_tuple_ip(struct sk_bu\n \ttuple->l3proto\t\t= AF_INET;\n \ttuple->l4proto\t\t= iph->protocol;\n \ttuple->iifidx\t\t= dev->ifindex;\n+\tnf_flow_tuple_encap(skb, tuple);\n \n \treturn 0;\n }\n@@ -207,6 +228,43 @@ static unsigned int nf_flow_xmit_xfrm(st\n \treturn NF_STOLEN;\n }\n \n+static bool nf_flow_skb_encap_protocol(const struct sk_buff *skb, __be16 proto,\n+\t\t\t\t       u32 *offset)\n+{\n+\tif (skb->protocol == htons(ETH_P_8021Q)) {\n+\t\tstruct vlan_ethhdr *veth;\n+\n+\t\tveth = (struct vlan_ethhdr *)skb_mac_header(skb);\n+\t\tif (veth->h_vlan_encapsulated_proto == proto) {\n+\t\t\t*offset += VLAN_HLEN;\n+\t\t\treturn true;\n+\t\t}\n+\t}\n+\n+\treturn false;\n+}\n+\n+static void nf_flow_encap_pop(struct sk_buff *skb,\n+\t\t\t      struct flow_offload_tuple_rhash *tuplehash)\n+{\n+\tstruct vlan_hdr *vlan_hdr;\n+\tint i;\n+\n+\tfor (i = 0; i < tuplehash->tuple.encap_num; i++) {\n+\t\tif (skb_vlan_tag_present(skb)) {\n+\t\t\t__vlan_hwaccel_clear_tag(skb);\n+\t\t\tcontinue;\n+\t\t}\n+\t\tif (skb->protocol == htons(ETH_P_8021Q)) {\n+\t\t\tvlan_hdr = (struct vlan_hdr *)skb->data;\n+\t\t\t__skb_pull(skb, VLAN_HLEN);\n+\t\t\tvlan_set_encap_proto(skb, vlan_hdr);\n+\t\t\tskb_reset_network_header(skb);\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+}\n+\n static unsigned int nf_flow_queue_xmit(struct net *net, struct sk_buff *skb,\n \t\t\t\t       const struct flow_offload_tuple_rhash *tuplehash,\n \t\t\t\t       unsigned short type)\n@@ -235,17 +293,18 @@ nf_flow_offload_ip_hook(void *priv, stru\n \tenum flow_offload_tuple_dir dir;\n \tstruct flow_offload *flow;\n \tstruct net_device *outdev;\n+\tu32 hdrsize, offset = 0;\n+\tunsigned int thoff, mtu;\n \tstruct rtable *rt;\n-\tunsigned int thoff;\n \tstruct iphdr *iph;\n \t__be32 nexthop;\n-\tu32 hdrsize;\n \tint ret;\n \n-\tif (skb->protocol != htons(ETH_P_IP))\n+\tif (skb->protocol != htons(ETH_P_IP) &&\n+\t    !nf_flow_skb_encap_protocol(skb, htons(ETH_P_IP), &offset))\n \t\treturn NF_ACCEPT;\n \n-\tif (nf_flow_tuple_ip(skb, state->in, &tuple, &hdrsize) < 0)\n+\tif (nf_flow_tuple_ip(skb, state->in, &tuple, &hdrsize, offset) < 0)\n \t\treturn NF_ACCEPT;\n \n \ttuplehash = flow_offload_lookup(flow_table, &tuple);\n@@ -255,11 +314,12 @@ nf_flow_offload_ip_hook(void *priv, stru\n \tdir = tuplehash->tuple.dir;\n \tflow = container_of(tuplehash, struct flow_offload, tuplehash[dir]);\n \n-\tif (unlikely(nf_flow_exceeds_mtu(skb, flow->tuplehash[dir].tuple.mtu)))\n+\tmtu = flow->tuplehash[dir].tuple.mtu + offset;\n+\tif (unlikely(nf_flow_exceeds_mtu(skb, mtu)))\n \t\treturn NF_ACCEPT;\n \n-\tiph = ip_hdr(skb);\n-\tthoff = iph->ihl * 4;\n+\tiph = (struct iphdr *)(skb_network_header(skb) + offset);\n+\tthoff = (iph->ihl * 4) + offset;\n \tif (nf_flow_state_check(flow, iph->protocol, skb, thoff))\n \t\treturn NF_ACCEPT;\n \n@@ -277,6 +337,9 @@ nf_flow_offload_ip_hook(void *priv, stru\n \n \tflow_offload_refresh(flow_table, flow);\n \n+\tnf_flow_encap_pop(skb, tuplehash);\n+\tthoff -= offset;\n+\n \tiph = ip_hdr(skb);\n \tnf_flow_nat_ip(flow, skb, thoff, dir, iph);\n \n@@ -418,16 +481,18 @@ static void nf_flow_nat_ipv6(const struc\n }\n \n static int nf_flow_tuple_ipv6(struct sk_buff *skb, const struct net_device *dev,\n-\t\t\t      struct flow_offload_tuple *tuple, u32 *hdrsize)\n+\t\t\t      struct flow_offload_tuple *tuple, u32 *hdrsize,\n+\t\t\t      u32 offset)\n {\n \tstruct flow_ports *ports;\n \tstruct ipv6hdr *ip6h;\n \tunsigned int thoff;\n \n-\tif (!pskb_may_pull(skb, sizeof(*ip6h)))\n+\tthoff = sizeof(*ip6h) + offset;\n+\tif (!pskb_may_pull(skb, thoff))\n \t\treturn -1;\n \n-\tip6h = ipv6_hdr(skb);\n+\tip6h = (struct ipv6hdr *)(skb_network_header(skb) + offset);\n \n \tswitch (ip6h->nexthdr) {\n \tcase IPPROTO_TCP:\n@@ -443,11 +508,10 @@ static int nf_flow_tuple_ipv6(struct sk_\n \tif (ip6h->hop_limit <= 1)\n \t\treturn -1;\n \n-\tthoff = sizeof(*ip6h);\n \tif (!pskb_may_pull(skb, thoff + *hdrsize))\n \t\treturn -1;\n \n-\tip6h = ipv6_hdr(skb);\n+\tip6h = (struct ipv6hdr *)(skb_network_header(skb) + offset);\n \tports = (struct flow_ports *)(skb_network_header(skb) + thoff);\n \n \ttuple->src_v6\t\t= ip6h->saddr;\n@@ -457,6 +521,7 @@ static int nf_flow_tuple_ipv6(struct sk_\n \ttuple->l3proto\t\t= AF_INET6;\n \ttuple->l4proto\t\t= ip6h->nexthdr;\n \ttuple->iifidx\t\t= dev->ifindex;\n+\tnf_flow_tuple_encap(skb, tuple);\n \n \treturn 0;\n }\n@@ -472,15 +537,17 @@ nf_flow_offload_ipv6_hook(void *priv, st\n \tconst struct in6_addr *nexthop;\n \tstruct flow_offload *flow;\n \tstruct net_device *outdev;\n+\tunsigned int thoff, mtu;\n+\tu32 hdrsize, offset = 0;\n \tstruct ipv6hdr *ip6h;\n \tstruct rt6_info *rt;\n-\tu32 hdrsize;\n \tint ret;\n \n-\tif (skb->protocol != htons(ETH_P_IPV6))\n+\tif (skb->protocol != htons(ETH_P_IPV6) &&\n+\t    !nf_flow_skb_encap_protocol(skb, htons(ETH_P_IPV6), &offset))\n \t\treturn NF_ACCEPT;\n \n-\tif (nf_flow_tuple_ipv6(skb, state->in, &tuple, &hdrsize) < 0)\n+\tif (nf_flow_tuple_ipv6(skb, state->in, &tuple, &hdrsize, offset) < 0)\n \t\treturn NF_ACCEPT;\n \n \ttuplehash = flow_offload_lookup(flow_table, &tuple);\n@@ -490,11 +557,13 @@ nf_flow_offload_ipv6_hook(void *priv, st\n \tdir = tuplehash->tuple.dir;\n \tflow = container_of(tuplehash, struct flow_offload, tuplehash[dir]);\n \n-\tif (unlikely(nf_flow_exceeds_mtu(skb, flow->tuplehash[dir].tuple.mtu)))\n+\tmtu = flow->tuplehash[dir].tuple.mtu + offset;\n+\tif (unlikely(nf_flow_exceeds_mtu(skb, mtu)))\n \t\treturn NF_ACCEPT;\n \n-\tif (nf_flow_state_check(flow, ipv6_hdr(skb)->nexthdr, skb,\n-\t\t\t\tsizeof(*ip6h)))\n+\tip6h = (struct ipv6hdr *)(skb_network_header(skb) + offset);\n+\tthoff = sizeof(*ip6h) + offset;\n+\tif (nf_flow_state_check(flow, ip6h->nexthdr, skb, thoff))\n \t\treturn NF_ACCEPT;\n \n \tif (tuplehash->tuple.xmit_type == FLOW_OFFLOAD_XMIT_NEIGH ||\n@@ -506,11 +575,13 @@ nf_flow_offload_ipv6_hook(void *priv, st\n \t\t}\n \t}\n \n-\tif (skb_try_make_writable(skb, sizeof(*ip6h) + hdrsize))\n+\tif (skb_try_make_writable(skb, thoff + hdrsize))\n \t\treturn NF_DROP;\n \n \tflow_offload_refresh(flow_table, flow);\n \n+\tnf_flow_encap_pop(skb, tuplehash);\n+\n \tip6h = ipv6_hdr(skb);\n \tnf_flow_nat_ipv6(flow, skb, dir, ip6h);\n \n--- a/net/netfilter/nft_flow_offload.c\n+++ b/net/netfilter/nft_flow_offload.c\n@@ -66,6 +66,11 @@ static int nft_dev_fill_forward_path(con\n struct nft_forward_info {\n \tconst struct net_device *indev;\n \tconst struct net_device *outdev;\n+\tstruct id {\n+\t\t__u16\tid;\n+\t\t__be16\tproto;\n+\t} encap[NF_FLOW_TABLE_ENCAP_MAX];\n+\tu8 num_encaps;\n \tu8 h_source[ETH_ALEN];\n \tu8 h_dest[ETH_ALEN];\n \tenum flow_offload_xmit_type xmit_type;\n@@ -84,9 +89,23 @@ static void nft_dev_path_info(const stru\n \t\tpath = &stack->path[i];\n \t\tswitch (path->type) {\n \t\tcase DEV_PATH_ETHERNET:\n+\t\tcase DEV_PATH_VLAN:\n \t\t\tinfo->indev = path->dev;\n \t\t\tif (is_zero_ether_addr(info->h_source))\n \t\t\t\tmemcpy(info->h_source, path->dev->dev_addr, ETH_ALEN);\n+\n+\t\t\tif (path->type == DEV_PATH_ETHERNET)\n+\t\t\t\tbreak;\n+\n+\t\t\t/* DEV_PATH_VLAN */\n+\t\t\tif (info->num_encaps >= NF_FLOW_TABLE_ENCAP_MAX) {\n+\t\t\t\tinfo->indev = NULL;\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t\tinfo->outdev = path->dev;\n+\t\t\tinfo->encap[info->num_encaps].id = path->encap.id;\n+\t\t\tinfo->encap[info->num_encaps].proto = path->encap.proto;\n+\t\t\tinfo->num_encaps++;\n \t\t\tbreak;\n \t\tcase DEV_PATH_BRIDGE:\n \t\t\tif (is_zero_ether_addr(info->h_source))\n@@ -94,7 +113,6 @@ static void nft_dev_path_info(const stru\n \n \t\t\tinfo->xmit_type = FLOW_OFFLOAD_XMIT_DIRECT;\n \t\t\tbreak;\n-\t\tcase DEV_PATH_VLAN:\n \t\tdefault:\n \t\t\tinfo->indev = NULL;\n \t\t\tbreak;\n@@ -130,6 +148,7 @@ static void nft_dev_forward_path(struct\n \tstruct net_device_path_stack stack;\n \tstruct nft_forward_info info = {};\n \tunsigned char ha[ETH_ALEN];\n+\tint i;\n \n \tif (nft_dev_fill_forward_path(route, dst, ct, dir, ha, &stack) >= 0)\n \t\tnft_dev_path_info(&stack, &info, ha);\n@@ -138,6 +157,11 @@ static void nft_dev_forward_path(struct\n \t\treturn;\n \n \troute->tuple[!dir].in.ifindex = info.indev->ifindex;\n+\tfor (i = 0; i < info.num_encaps; i++) {\n+\t\troute->tuple[!dir].in.encap[i].id = info.encap[i].id;\n+\t\troute->tuple[!dir].in.encap[i].proto = info.encap[i].proto;\n+\t}\n+\troute->tuple[!dir].in.num_encaps = info.num_encaps;\n \n \tif (info.xmit_type == FLOW_OFFLOAD_XMIT_DIRECT) {\n \t\tmemcpy(route->tuple[dir].out.h_source, info.h_source, ETH_ALEN);\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/610-v5.13-21-netfilter-flowtable-add-bridge-vlan-filtering-suppor.patch",
    "content": "From: Pablo Neira Ayuso <pablo@netfilter.org>\nDate: Wed, 24 Mar 2021 02:30:42 +0100\nSubject: [PATCH] netfilter: flowtable: add bridge vlan filtering support\n\nAdd the vlan tag based when PVID is set on.\n\nSigned-off-by: Pablo Neira Ayuso <pablo@netfilter.org>\n---\n\n--- a/net/netfilter/nft_flow_offload.c\n+++ b/net/netfilter/nft_flow_offload.c\n@@ -111,6 +111,18 @@ static void nft_dev_path_info(const stru\n \t\t\tif (is_zero_ether_addr(info->h_source))\n \t\t\t\tmemcpy(info->h_source, path->dev->dev_addr, ETH_ALEN);\n \n+\t\t\tswitch (path->bridge.vlan_mode) {\n+\t\t\tcase DEV_PATH_BR_VLAN_TAG:\n+\t\t\t\tinfo->encap[info->num_encaps].id = path->bridge.vlan_id;\n+\t\t\t\tinfo->encap[info->num_encaps].proto = path->bridge.vlan_proto;\n+\t\t\t\tinfo->num_encaps++;\n+\t\t\t\tbreak;\n+\t\t\tcase DEV_PATH_BR_VLAN_UNTAG:\n+\t\t\t\tinfo->num_encaps--;\n+\t\t\t\tbreak;\n+\t\t\tcase DEV_PATH_BR_VLAN_KEEP:\n+\t\t\t\tbreak;\n+\t\t\t}\n \t\t\tinfo->xmit_type = FLOW_OFFLOAD_XMIT_DIRECT;\n \t\t\tbreak;\n \t\tdefault:\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/610-v5.13-22-netfilter-flowtable-add-pppoe-support.patch",
    "content": "From: Pablo Neira Ayuso <pablo@netfilter.org>\nDate: Wed, 24 Mar 2021 02:30:43 +0100\nSubject: [PATCH] netfilter: flowtable: add pppoe support\n\nAdd the PPPoE protocol and session id to the flow tuple using the encap\nfields to uniquely identify flows from the receive path. For the\ntransmit path, dev_hard_header() on the vlan device push the headers.\n\nSigned-off-by: Pablo Neira Ayuso <pablo@netfilter.org>\n---\n\n--- a/net/netfilter/nf_flow_table_ip.c\n+++ b/net/netfilter/nf_flow_table_ip.c\n@@ -7,6 +7,9 @@\n #include <linux/ip.h>\n #include <linux/ipv6.h>\n #include <linux/netdevice.h>\n+#include <linux/if_ether.h>\n+#include <linux/if_pppox.h>\n+#include <linux/ppp_defs.h>\n #include <net/ip.h>\n #include <net/ipv6.h>\n #include <net/ip6_route.h>\n@@ -139,6 +142,8 @@ static bool ip_has_options(unsigned int\n static void nf_flow_tuple_encap(struct sk_buff *skb,\n \t\t\t\tstruct flow_offload_tuple *tuple)\n {\n+\tstruct vlan_ethhdr *veth;\n+\tstruct pppoe_hdr *phdr;\n \tint i = 0;\n \n \tif (skb_vlan_tag_present(skb)) {\n@@ -146,11 +151,17 @@ static void nf_flow_tuple_encap(struct s\n \t\ttuple->encap[i].proto = skb->vlan_proto;\n \t\ti++;\n \t}\n-\tif (skb->protocol == htons(ETH_P_8021Q)) {\n-\t\tstruct vlan_ethhdr *veth = (struct vlan_ethhdr *)skb_mac_header(skb);\n-\n+\tswitch (skb->protocol) {\n+\tcase htons(ETH_P_8021Q):\n+\t\tveth = (struct vlan_ethhdr *)skb_mac_header(skb);\n \t\ttuple->encap[i].id = ntohs(veth->h_vlan_TCI);\n \t\ttuple->encap[i].proto = skb->protocol;\n+\t\tbreak;\n+\tcase htons(ETH_P_PPP_SES):\n+\t\tphdr = (struct pppoe_hdr *)skb_mac_header(skb);\n+\t\ttuple->encap[i].id = ntohs(phdr->sid);\n+\t\ttuple->encap[i].proto = skb->protocol;\n+\t\tbreak;\n \t}\n }\n \n@@ -228,17 +239,41 @@ static unsigned int nf_flow_xmit_xfrm(st\n \treturn NF_STOLEN;\n }\n \n+static inline __be16 nf_flow_pppoe_proto(const struct sk_buff *skb)\n+{\n+\t__be16 proto;\n+\n+\tproto = *((__be16 *)(skb_mac_header(skb) + ETH_HLEN +\n+\t\t\t     sizeof(struct pppoe_hdr)));\n+\tswitch (proto) {\n+\tcase htons(PPP_IP):\n+\t\treturn htons(ETH_P_IP);\n+\tcase htons(PPP_IPV6):\n+\t\treturn htons(ETH_P_IPV6);\n+\t}\n+\n+\treturn 0;\n+}\n+\n static bool nf_flow_skb_encap_protocol(const struct sk_buff *skb, __be16 proto,\n \t\t\t\t       u32 *offset)\n {\n-\tif (skb->protocol == htons(ETH_P_8021Q)) {\n-\t\tstruct vlan_ethhdr *veth;\n+\tstruct vlan_ethhdr *veth;\n \n+\tswitch (skb->protocol) {\n+\tcase htons(ETH_P_8021Q):\n \t\tveth = (struct vlan_ethhdr *)skb_mac_header(skb);\n \t\tif (veth->h_vlan_encapsulated_proto == proto) {\n \t\t\t*offset += VLAN_HLEN;\n \t\t\treturn true;\n \t\t}\n+\t\tbreak;\n+\tcase htons(ETH_P_PPP_SES):\n+\t\tif (nf_flow_pppoe_proto(skb) == proto) {\n+\t\t\t*offset += PPPOE_SES_HLEN;\n+\t\t\treturn true;\n+\t\t}\n+\t\tbreak;\n \t}\n \n \treturn false;\n@@ -255,12 +290,18 @@ static void nf_flow_encap_pop(struct sk_\n \t\t\t__vlan_hwaccel_clear_tag(skb);\n \t\t\tcontinue;\n \t\t}\n-\t\tif (skb->protocol == htons(ETH_P_8021Q)) {\n+\t\tswitch (skb->protocol) {\n+\t\tcase htons(ETH_P_8021Q):\n \t\t\tvlan_hdr = (struct vlan_hdr *)skb->data;\n \t\t\t__skb_pull(skb, VLAN_HLEN);\n \t\t\tvlan_set_encap_proto(skb, vlan_hdr);\n \t\t\tskb_reset_network_header(skb);\n \t\t\tbreak;\n+\t\tcase htons(ETH_P_PPP_SES):\n+\t\t\tskb->protocol = nf_flow_pppoe_proto(skb);\n+\t\t\tskb_pull(skb, PPPOE_SES_HLEN);\n+\t\t\tskb_reset_network_header(skb);\n+\t\t\tbreak;\n \t\t}\n \t}\n }\n--- a/net/netfilter/nft_flow_offload.c\n+++ b/net/netfilter/nft_flow_offload.c\n@@ -90,6 +90,7 @@ static void nft_dev_path_info(const stru\n \t\tswitch (path->type) {\n \t\tcase DEV_PATH_ETHERNET:\n \t\tcase DEV_PATH_VLAN:\n+\t\tcase DEV_PATH_PPPOE:\n \t\t\tinfo->indev = path->dev;\n \t\t\tif (is_zero_ether_addr(info->h_source))\n \t\t\t\tmemcpy(info->h_source, path->dev->dev_addr, ETH_ALEN);\n@@ -97,7 +98,7 @@ static void nft_dev_path_info(const stru\n \t\t\tif (path->type == DEV_PATH_ETHERNET)\n \t\t\t\tbreak;\n \n-\t\t\t/* DEV_PATH_VLAN */\n+\t\t\t/* DEV_PATH_VLAN and DEV_PATH_PPPOE */\n \t\t\tif (info->num_encaps >= NF_FLOW_TABLE_ENCAP_MAX) {\n \t\t\t\tinfo->indev = NULL;\n \t\t\t\tbreak;\n@@ -106,6 +107,8 @@ static void nft_dev_path_info(const stru\n \t\t\tinfo->encap[info->num_encaps].id = path->encap.id;\n \t\t\tinfo->encap[info->num_encaps].proto = path->encap.proto;\n \t\t\tinfo->num_encaps++;\n+\t\t\tif (path->type == DEV_PATH_PPPOE)\n+\t\t\t\tmemcpy(info->h_dest, path->encap.h_dest, ETH_ALEN);\n \t\t\tbreak;\n \t\tcase DEV_PATH_BRIDGE:\n \t\t\tif (is_zero_ether_addr(info->h_source))\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/610-v5.13-23-netfilter-flowtable-add-dsa-support.patch",
    "content": "From: Pablo Neira Ayuso <pablo@netfilter.org>\nDate: Wed, 24 Mar 2021 02:30:44 +0100\nSubject: [PATCH] netfilter: flowtable: add dsa support\n\nReplace the master ethernet device by the dsa slave port. Packets coming\nin from the software ingress path use the dsa slave port as input\ndevice.\n\nSigned-off-by: Pablo Neira Ayuso <pablo@netfilter.org>\n---\n\n--- a/net/netfilter/nft_flow_offload.c\n+++ b/net/netfilter/nft_flow_offload.c\n@@ -89,6 +89,7 @@ static void nft_dev_path_info(const stru\n \t\tpath = &stack->path[i];\n \t\tswitch (path->type) {\n \t\tcase DEV_PATH_ETHERNET:\n+\t\tcase DEV_PATH_DSA:\n \t\tcase DEV_PATH_VLAN:\n \t\tcase DEV_PATH_PPPOE:\n \t\t\tinfo->indev = path->dev;\n@@ -97,6 +98,10 @@ static void nft_dev_path_info(const stru\n \n \t\t\tif (path->type == DEV_PATH_ETHERNET)\n \t\t\t\tbreak;\n+\t\t\tif (path->type == DEV_PATH_DSA) {\n+\t\t\t\ti = stack->num_paths;\n+\t\t\t\tbreak;\n+\t\t\t}\n \n \t\t\t/* DEV_PATH_VLAN and DEV_PATH_PPPOE */\n \t\t\tif (info->num_encaps >= NF_FLOW_TABLE_ENCAP_MAX) {\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/610-v5.13-24-selftests-netfilter-flowtable-bridge-and-vlan-suppor.patch",
    "content": "From: Pablo Neira Ayuso <pablo@netfilter.org>\nDate: Wed, 24 Mar 2021 02:30:45 +0100\nSubject: [PATCH] selftests: netfilter: flowtable bridge and vlan support\n\nThis patch adds two new tests to cover bridge and vlan support:\n\n- Add a bridge device to the Router1 (nsr1) container and attach the\n  veth0 device to the bridge. Set the IP address to the bridge device\n  to exercise the bridge forwarding path.\n\n- Add vlan encapsulation between to the bridge device in the Router1 and\n  one of the sender containers (ns1).\n\nSigned-off-by: Pablo Neira Ayuso <pablo@netfilter.org>\n---\n\n--- a/tools/testing/selftests/netfilter/nft_flowtable.sh\n+++ b/tools/testing/selftests/netfilter/nft_flowtable.sh\n@@ -370,6 +370,88 @@ else\n \tip netns exec nsr1 nft list ruleset\n fi\n \n+# Another test:\n+# Add bridge interface br0 to Router1, with NAT enabled.\n+ip -net nsr1 link add name br0 type bridge\n+ip -net nsr1 addr flush dev veth0\n+ip -net nsr1 link set up dev veth0\n+ip -net nsr1 link set veth0 master br0\n+ip -net nsr1 addr add 10.0.1.1/24 dev br0\n+ip -net nsr1 addr add dead:1::1/64 dev br0\n+ip -net nsr1 link set up dev br0\n+\n+ip netns exec nsr1 sysctl net.ipv4.conf.br0.forwarding=1 > /dev/null\n+\n+# br0 with NAT enabled.\n+ip netns exec nsr1 nft -f - <<EOF\n+flush table ip nat\n+table ip nat {\n+   chain prerouting {\n+      type nat hook prerouting priority 0; policy accept;\n+      meta iif \"br0\" ip daddr 10.6.6.6 tcp dport 1666 counter dnat ip to 10.0.2.99:12345\n+   }\n+\n+   chain postrouting {\n+      type nat hook postrouting priority 0; policy accept;\n+      meta oifname \"veth1\" counter masquerade\n+   }\n+}\n+EOF\n+\n+if test_tcp_forwarding_nat ns1 ns2; then\n+\techo \"PASS: flow offloaded for ns1/ns2 with bridge NAT\"\n+else\n+\techo \"FAIL: flow offload for ns1/ns2 with bridge NAT\" 1>&2\n+\tip netns exec nsr1 nft list ruleset\n+\tret=1\n+fi\n+\n+# Another test:\n+# Add bridge interface br0 to Router1, with NAT and VLAN.\n+ip -net nsr1 link set veth0 nomaster\n+ip -net nsr1 link set down dev veth0\n+ip -net nsr1 link add link veth0 name veth0.10 type vlan id 10\n+ip -net nsr1 link set up dev veth0\n+ip -net nsr1 link set up dev veth0.10\n+ip -net nsr1 link set veth0.10 master br0\n+\n+ip -net ns1 addr flush dev eth0\n+ip -net ns1 link add link eth0 name eth0.10 type vlan id 10\n+ip -net ns1 link set eth0 up\n+ip -net ns1 link set eth0.10 up\n+ip -net ns1 addr add 10.0.1.99/24 dev eth0.10\n+ip -net ns1 route add default via 10.0.1.1\n+ip -net ns1 addr add dead:1::99/64 dev eth0.10\n+\n+if test_tcp_forwarding_nat ns1 ns2; then\n+\techo \"PASS: flow offloaded for ns1/ns2 with bridge NAT and VLAN\"\n+else\n+\techo \"FAIL: flow offload for ns1/ns2 with bridge NAT and VLAN\" 1>&2\n+\tip netns exec nsr1 nft list ruleset\n+\tret=1\n+fi\n+\n+# restore test topology (remove bridge and VLAN)\n+ip -net nsr1 link set veth0 nomaster\n+ip -net nsr1 link set veth0 down\n+ip -net nsr1 link set veth0.10 down\n+ip -net nsr1 link delete veth0.10 type vlan\n+ip -net nsr1 link delete br0 type bridge\n+ip -net ns1 addr flush dev eth0.10\n+ip -net ns1 link set eth0.10 down\n+ip -net ns1 link set eth0 down\n+ip -net ns1 link delete eth0.10 type vlan\n+\n+# restore address in ns1 and nsr1\n+ip -net ns1 link set eth0 up\n+ip -net ns1 addr add 10.0.1.99/24 dev eth0\n+ip -net ns1 route add default via 10.0.1.1\n+ip -net ns1 addr add dead:1::99/64 dev eth0\n+ip -net ns1 route add default via dead:1::1\n+ip -net nsr1 addr add 10.0.1.1/24 dev veth0\n+ip -net nsr1 addr add dead:1::1/64 dev veth0\n+ip -net nsr1 link set up dev veth0\n+\n KEY_SHA=\"0x\"$(ps -xaf | sha1sum | cut -d \" \" -f 1)\n KEY_AES=\"0x\"$(ps -xaf | md5sum | cut -d \" \" -f 1)\n SPI1=$RANDOM\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/610-v5.13-25-netfilter-flowtable-add-offload-support-for-xmit-pat.patch",
    "content": "From: Pablo Neira Ayuso <pablo@netfilter.org>\nDate: Wed, 24 Mar 2021 02:30:46 +0100\nSubject: [PATCH] netfilter: flowtable: add offload support for xmit path\n types\n\nWhen the flow tuple xmit_type is set to FLOW_OFFLOAD_XMIT_DIRECT, the\ndst_cache pointer is not valid, and the h_source/h_dest/ifidx out fields\nneed to be used.\n\nThis patch also adds the FLOW_ACTION_VLAN_PUSH action to pass the VLAN\ntag to the driver.\n\nSigned-off-by: Pablo Neira Ayuso <pablo@netfilter.org>\n---\n\n--- a/net/netfilter/nf_flow_table_offload.c\n+++ b/net/netfilter/nf_flow_table_offload.c\n@@ -177,28 +177,45 @@ static int flow_offload_eth_src(struct n\n \t\t\t\tenum flow_offload_tuple_dir dir,\n \t\t\t\tstruct nf_flow_rule *flow_rule)\n {\n-\tconst struct flow_offload_tuple *tuple = &flow->tuplehash[!dir].tuple;\n \tstruct flow_action_entry *entry0 = flow_action_entry_next(flow_rule);\n \tstruct flow_action_entry *entry1 = flow_action_entry_next(flow_rule);\n-\tstruct net_device *dev;\n+\tconst struct flow_offload_tuple *other_tuple, *this_tuple;\n+\tstruct net_device *dev = NULL;\n+\tconst unsigned char *addr;\n \tu32 mask, val;\n \tu16 val16;\n \n-\tdev = dev_get_by_index(net, tuple->iifidx);\n-\tif (!dev)\n-\t\treturn -ENOENT;\n+\tthis_tuple = &flow->tuplehash[dir].tuple;\n+\n+\tswitch (this_tuple->xmit_type) {\n+\tcase FLOW_OFFLOAD_XMIT_DIRECT:\n+\t\taddr = this_tuple->out.h_source;\n+\t\tbreak;\n+\tcase FLOW_OFFLOAD_XMIT_NEIGH:\n+\t\tother_tuple = &flow->tuplehash[!dir].tuple;\n+\t\tdev = dev_get_by_index(net, other_tuple->iifidx);\n+\t\tif (!dev)\n+\t\t\treturn -ENOENT;\n+\n+\t\taddr = dev->dev_addr;\n+\t\tbreak;\n+\tdefault:\n+\t\treturn -EOPNOTSUPP;\n+\t}\n \n \tmask = ~0xffff0000;\n-\tmemcpy(&val16, dev->dev_addr, 2);\n+\tmemcpy(&val16, addr, 2);\n \tval = val16 << 16;\n \tflow_offload_mangle(entry0, FLOW_ACT_MANGLE_HDR_TYPE_ETH, 4,\n \t\t\t    &val, &mask);\n \n \tmask = ~0xffffffff;\n-\tmemcpy(&val, dev->dev_addr + 2, 4);\n+\tmemcpy(&val, addr + 2, 4);\n \tflow_offload_mangle(entry1, FLOW_ACT_MANGLE_HDR_TYPE_ETH, 8,\n \t\t\t    &val, &mask);\n-\tdev_put(dev);\n+\n+\tif (dev)\n+\t\tdev_put(dev);\n \n \treturn 0;\n }\n@@ -210,27 +227,40 @@ static int flow_offload_eth_dst(struct n\n {\n \tstruct flow_action_entry *entry0 = flow_action_entry_next(flow_rule);\n \tstruct flow_action_entry *entry1 = flow_action_entry_next(flow_rule);\n-\tconst void *daddr = &flow->tuplehash[!dir].tuple.src_v4;\n+\tconst struct flow_offload_tuple *other_tuple, *this_tuple;\n \tconst struct dst_entry *dst_cache;\n \tunsigned char ha[ETH_ALEN];\n \tstruct neighbour *n;\n+\tconst void *daddr;\n \tu32 mask, val;\n \tu8 nud_state;\n \tu16 val16;\n \n-\tdst_cache = flow->tuplehash[dir].tuple.dst_cache;\n-\tn = dst_neigh_lookup(dst_cache, daddr);\n-\tif (!n)\n-\t\treturn -ENOENT;\n-\n-\tread_lock_bh(&n->lock);\n-\tnud_state = n->nud_state;\n-\tether_addr_copy(ha, n->ha);\n-\tread_unlock_bh(&n->lock);\n+\tthis_tuple = &flow->tuplehash[dir].tuple;\n \n-\tif (!(nud_state & NUD_VALID)) {\n+\tswitch (this_tuple->xmit_type) {\n+\tcase FLOW_OFFLOAD_XMIT_DIRECT:\n+\t\tether_addr_copy(ha, this_tuple->out.h_dest);\n+\t\tbreak;\n+\tcase FLOW_OFFLOAD_XMIT_NEIGH:\n+\t\tother_tuple = &flow->tuplehash[!dir].tuple;\n+\t\tdaddr = &other_tuple->src_v4;\n+\t\tdst_cache = this_tuple->dst_cache;\n+\t\tn = dst_neigh_lookup(dst_cache, daddr);\n+\t\tif (!n)\n+\t\t\treturn -ENOENT;\n+\n+\t\tread_lock_bh(&n->lock);\n+\t\tnud_state = n->nud_state;\n+\t\tether_addr_copy(ha, n->ha);\n+\t\tread_unlock_bh(&n->lock);\n \t\tneigh_release(n);\n-\t\treturn -ENOENT;\n+\n+\t\tif (!(nud_state & NUD_VALID))\n+\t\t\treturn -ENOENT;\n+\t\tbreak;\n+\tdefault:\n+\t\treturn -EOPNOTSUPP;\n \t}\n \n \tmask = ~0xffffffff;\n@@ -243,7 +273,6 @@ static int flow_offload_eth_dst(struct n\n \tval = val16;\n \tflow_offload_mangle(entry1, FLOW_ACT_MANGLE_HDR_TYPE_ETH, 4,\n \t\t\t    &val, &mask);\n-\tneigh_release(n);\n \n \treturn 0;\n }\n@@ -465,27 +494,52 @@ static void flow_offload_ipv4_checksum(s\n \t}\n }\n \n-static void flow_offload_redirect(const struct flow_offload *flow,\n+static void flow_offload_redirect(struct net *net,\n+\t\t\t\t  const struct flow_offload *flow,\n \t\t\t\t  enum flow_offload_tuple_dir dir,\n \t\t\t\t  struct nf_flow_rule *flow_rule)\n {\n-\tstruct flow_action_entry *entry = flow_action_entry_next(flow_rule);\n-\tstruct rtable *rt;\n+\tconst struct flow_offload_tuple *this_tuple, *other_tuple;\n+\tstruct flow_action_entry *entry;\n+\tstruct net_device *dev;\n+\tint ifindex;\n+\n+\tthis_tuple = &flow->tuplehash[dir].tuple;\n+\tswitch (this_tuple->xmit_type) {\n+\tcase FLOW_OFFLOAD_XMIT_DIRECT:\n+\t\tthis_tuple = &flow->tuplehash[dir].tuple;\n+\t\tifindex = this_tuple->out.ifidx;\n+\t\tbreak;\n+\tcase FLOW_OFFLOAD_XMIT_NEIGH:\n+\t\tother_tuple = &flow->tuplehash[!dir].tuple;\n+\t\tifindex = other_tuple->iifidx;\n+\t\tbreak;\n+\tdefault:\n+\t\treturn;\n+\t}\n \n-\trt = (struct rtable *)flow->tuplehash[dir].tuple.dst_cache;\n+\tdev = dev_get_by_index(net, ifindex);\n+\tif (!dev)\n+\t\treturn;\n+\n+\tentry = flow_action_entry_next(flow_rule);\n \tentry->id = FLOW_ACTION_REDIRECT;\n-\tentry->dev = rt->dst.dev;\n-\tdev_hold(rt->dst.dev);\n+\tentry->dev = dev;\n }\n \n static void flow_offload_encap_tunnel(const struct flow_offload *flow,\n \t\t\t\t      enum flow_offload_tuple_dir dir,\n \t\t\t\t      struct nf_flow_rule *flow_rule)\n {\n+\tconst struct flow_offload_tuple *this_tuple;\n \tstruct flow_action_entry *entry;\n \tstruct dst_entry *dst;\n \n-\tdst = flow->tuplehash[dir].tuple.dst_cache;\n+\tthis_tuple = &flow->tuplehash[dir].tuple;\n+\tif (this_tuple->xmit_type == FLOW_OFFLOAD_XMIT_DIRECT)\n+\t\treturn;\n+\n+\tdst = this_tuple->dst_cache;\n \tif (dst && dst->lwtstate) {\n \t\tstruct ip_tunnel_info *tun_info;\n \n@@ -502,10 +556,15 @@ static void flow_offload_decap_tunnel(co\n \t\t\t\t      enum flow_offload_tuple_dir dir,\n \t\t\t\t      struct nf_flow_rule *flow_rule)\n {\n+\tconst struct flow_offload_tuple *other_tuple;\n \tstruct flow_action_entry *entry;\n \tstruct dst_entry *dst;\n \n-\tdst = flow->tuplehash[!dir].tuple.dst_cache;\n+\tother_tuple = &flow->tuplehash[!dir].tuple;\n+\tif (other_tuple->xmit_type == FLOW_OFFLOAD_XMIT_DIRECT)\n+\t\treturn;\n+\n+\tdst = other_tuple->dst_cache;\n \tif (dst && dst->lwtstate) {\n \t\tstruct ip_tunnel_info *tun_info;\n \n@@ -517,10 +576,14 @@ static void flow_offload_decap_tunnel(co\n \t}\n }\n \n-int nf_flow_rule_route_ipv4(struct net *net, const struct flow_offload *flow,\n-\t\t\t    enum flow_offload_tuple_dir dir,\n-\t\t\t    struct nf_flow_rule *flow_rule)\n+static int\n+nf_flow_rule_route_common(struct net *net, const struct flow_offload *flow,\n+\t\t\t  enum flow_offload_tuple_dir dir,\n+\t\t\t  struct nf_flow_rule *flow_rule)\n {\n+\tconst struct flow_offload_tuple *other_tuple;\n+\tint i;\n+\n \tflow_offload_decap_tunnel(flow, dir, flow_rule);\n \tflow_offload_encap_tunnel(flow, dir, flow_rule);\n \n@@ -528,6 +591,26 @@ int nf_flow_rule_route_ipv4(struct net *\n \t    flow_offload_eth_dst(net, flow, dir, flow_rule) < 0)\n \t\treturn -1;\n \n+\tother_tuple = &flow->tuplehash[!dir].tuple;\n+\n+\tfor (i = 0; i < other_tuple->encap_num; i++) {\n+\t\tstruct flow_action_entry *entry = flow_action_entry_next(flow_rule);\n+\n+\t\tentry->id = FLOW_ACTION_VLAN_PUSH;\n+\t\tentry->vlan.vid = other_tuple->encap[i].id;\n+\t\tentry->vlan.proto = other_tuple->encap[i].proto;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+int nf_flow_rule_route_ipv4(struct net *net, const struct flow_offload *flow,\n+\t\t\t    enum flow_offload_tuple_dir dir,\n+\t\t\t    struct nf_flow_rule *flow_rule)\n+{\n+\tif (nf_flow_rule_route_common(net, flow, dir, flow_rule) < 0)\n+\t\treturn -1;\n+\n \tif (test_bit(NF_FLOW_SNAT, &flow->flags)) {\n \t\tflow_offload_ipv4_snat(net, flow, dir, flow_rule);\n \t\tflow_offload_port_snat(net, flow, dir, flow_rule);\n@@ -540,7 +623,7 @@ int nf_flow_rule_route_ipv4(struct net *\n \t    test_bit(NF_FLOW_DNAT, &flow->flags))\n \t\tflow_offload_ipv4_checksum(net, flow, flow_rule);\n \n-\tflow_offload_redirect(flow, dir, flow_rule);\n+\tflow_offload_redirect(net, flow, dir, flow_rule);\n \n \treturn 0;\n }\n@@ -550,11 +633,7 @@ int nf_flow_rule_route_ipv6(struct net *\n \t\t\t    enum flow_offload_tuple_dir dir,\n \t\t\t    struct nf_flow_rule *flow_rule)\n {\n-\tflow_offload_decap_tunnel(flow, dir, flow_rule);\n-\tflow_offload_encap_tunnel(flow, dir, flow_rule);\n-\n-\tif (flow_offload_eth_src(net, flow, dir, flow_rule) < 0 ||\n-\t    flow_offload_eth_dst(net, flow, dir, flow_rule) < 0)\n+\tif (nf_flow_rule_route_common(net, flow, dir, flow_rule) < 0)\n \t\treturn -1;\n \n \tif (test_bit(NF_FLOW_SNAT, &flow->flags)) {\n@@ -566,7 +645,7 @@ int nf_flow_rule_route_ipv6(struct net *\n \t\tflow_offload_port_dnat(net, flow, dir, flow_rule);\n \t}\n \n-\tflow_offload_redirect(flow, dir, flow_rule);\n+\tflow_offload_redirect(net, flow, dir, flow_rule);\n \n \treturn 0;\n }\n@@ -580,10 +659,10 @@ nf_flow_offload_rule_alloc(struct net *n\n \t\t\t   enum flow_offload_tuple_dir dir)\n {\n \tconst struct nf_flowtable *flowtable = offload->flowtable;\n+\tconst struct flow_offload_tuple *tuple, *other_tuple;\n \tconst struct flow_offload *flow = offload->flow;\n-\tconst struct flow_offload_tuple *tuple;\n+\tstruct dst_entry *other_dst = NULL;\n \tstruct nf_flow_rule *flow_rule;\n-\tstruct dst_entry *other_dst;\n \tint err = -ENOMEM;\n \n \tflow_rule = kzalloc(sizeof(*flow_rule), GFP_KERNEL);\n@@ -599,7 +678,10 @@ nf_flow_offload_rule_alloc(struct net *n\n \tflow_rule->rule->match.key = &flow_rule->match.key;\n \n \ttuple = &flow->tuplehash[dir].tuple;\n-\tother_dst = flow->tuplehash[!dir].tuple.dst_cache;\n+\tother_tuple = &flow->tuplehash[!dir].tuple;\n+\tif (other_tuple->xmit_type == FLOW_OFFLOAD_XMIT_NEIGH)\n+\t\tother_dst = other_tuple->dst_cache;\n+\n \terr = nf_flow_rule_match(&flow_rule->match, tuple, other_dst);\n \tif (err < 0)\n \t\tgoto err_flow_match;\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/610-v5.13-26-netfilter-nft_flow_offload-use-direct-xmit-if-hardwa.patch",
    "content": "From: Pablo Neira Ayuso <pablo@netfilter.org>\nDate: Wed, 24 Mar 2021 02:30:47 +0100\nSubject: [PATCH] netfilter: nft_flow_offload: use direct xmit if\n hardware offload is enabled\n\nIf there is a forward path to reach an ethernet device and hardware\noffload is enabled, then use the direct xmit path.\n\nMoreover, store the real device in the direct xmit path info since\nsoftware datapath uses dev_hard_header() to push the layer encapsulation\nheaders while hardware offload refers to the real device.\n\nSigned-off-by: Pablo Neira Ayuso <pablo@netfilter.org>\n---\n\n--- a/include/net/netfilter/nf_flow_table.h\n+++ b/include/net/netfilter/nf_flow_table.h\n@@ -131,6 +131,7 @@ struct flow_offload_tuple {\n \t\tstruct dst_entry\t*dst_cache;\n \t\tstruct {\n \t\t\tu32\t\tifidx;\n+\t\t\tu32\t\thw_ifidx;\n \t\t\tu8\t\th_source[ETH_ALEN];\n \t\t\tu8\t\th_dest[ETH_ALEN];\n \t\t} out;\n@@ -187,6 +188,7 @@ struct nf_flow_route {\n \t\t} in;\n \t\tstruct {\n \t\t\tu32\t\t\tifindex;\n+\t\t\tu32\t\t\thw_ifindex;\n \t\t\tu8\t\t\th_source[ETH_ALEN];\n \t\t\tu8\t\t\th_dest[ETH_ALEN];\n \t\t} out;\n--- a/net/netfilter/nf_flow_table_core.c\n+++ b/net/netfilter/nf_flow_table_core.c\n@@ -106,6 +106,7 @@ static int flow_offload_fill_route(struc\n \t\tmemcpy(flow_tuple->out.h_source, route->tuple[dir].out.h_source,\n \t\t       ETH_ALEN);\n \t\tflow_tuple->out.ifidx = route->tuple[dir].out.ifindex;\n+\t\tflow_tuple->out.hw_ifidx = route->tuple[dir].out.hw_ifindex;\n \t\tbreak;\n \tcase FLOW_OFFLOAD_XMIT_XFRM:\n \tcase FLOW_OFFLOAD_XMIT_NEIGH:\n--- a/net/netfilter/nf_flow_table_offload.c\n+++ b/net/netfilter/nf_flow_table_offload.c\n@@ -508,7 +508,7 @@ static void flow_offload_redirect(struct\n \tswitch (this_tuple->xmit_type) {\n \tcase FLOW_OFFLOAD_XMIT_DIRECT:\n \t\tthis_tuple = &flow->tuplehash[dir].tuple;\n-\t\tifindex = this_tuple->out.ifidx;\n+\t\tifindex = this_tuple->out.hw_ifidx;\n \t\tbreak;\n \tcase FLOW_OFFLOAD_XMIT_NEIGH:\n \t\tother_tuple = &flow->tuplehash[!dir].tuple;\n--- a/net/netfilter/nft_flow_offload.c\n+++ b/net/netfilter/nft_flow_offload.c\n@@ -66,6 +66,7 @@ static int nft_dev_fill_forward_path(con\n struct nft_forward_info {\n \tconst struct net_device *indev;\n \tconst struct net_device *outdev;\n+\tconst struct net_device *hw_outdev;\n \tstruct id {\n \t\t__u16\tid;\n \t\t__be16\tproto;\n@@ -76,9 +77,18 @@ struct nft_forward_info {\n \tenum flow_offload_xmit_type xmit_type;\n };\n \n+static bool nft_is_valid_ether_device(const struct net_device *dev)\n+{\n+\tif (!dev || (dev->flags & IFF_LOOPBACK) || dev->type != ARPHRD_ETHER ||\n+\t    dev->addr_len != ETH_ALEN || !is_valid_ether_addr(dev->dev_addr))\n+\t\treturn false;\n+\n+\treturn true;\n+}\n+\n static void nft_dev_path_info(const struct net_device_path_stack *stack,\n \t\t\t      struct nft_forward_info *info,\n-\t\t\t      unsigned char *ha)\n+\t\t\t      unsigned char *ha, struct nf_flowtable *flowtable)\n {\n \tconst struct net_device_path *path;\n \tint i;\n@@ -140,6 +150,12 @@ static void nft_dev_path_info(const stru\n \t}\n \tif (!info->outdev)\n \t\tinfo->outdev = info->indev;\n+\n+\tinfo->hw_outdev = info->indev;\n+\n+\tif (nf_flowtable_hw_offload(flowtable) &&\n+\t    nft_is_valid_ether_device(info->indev))\n+\t\tinfo->xmit_type = FLOW_OFFLOAD_XMIT_DIRECT;\n }\n \n static bool nft_flowtable_find_dev(const struct net_device *dev,\n@@ -171,7 +187,7 @@ static void nft_dev_forward_path(struct\n \tint i;\n \n \tif (nft_dev_fill_forward_path(route, dst, ct, dir, ha, &stack) >= 0)\n-\t\tnft_dev_path_info(&stack, &info, ha);\n+\t\tnft_dev_path_info(&stack, &info, ha, &ft->data);\n \n \tif (!info.indev || !nft_flowtable_find_dev(info.indev, ft))\n \t\treturn;\n@@ -187,6 +203,7 @@ static void nft_dev_forward_path(struct\n \t\tmemcpy(route->tuple[dir].out.h_source, info.h_source, ETH_ALEN);\n \t\tmemcpy(route->tuple[dir].out.h_dest, info.h_dest, ETH_ALEN);\n \t\troute->tuple[dir].out.ifindex = info.outdev->ifindex;\n+\t\troute->tuple[dir].out.hw_ifindex = info.hw_outdev->ifindex;\n \t\troute->tuple[dir].xmit_type = info.xmit_type;\n \t}\n }\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/610-v5.13-27-netfilter-flowtable-bridge-vlan-hardware-offload-and.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nDate: Wed, 24 Mar 2021 02:30:48 +0100\nSubject: [PATCH] netfilter: flowtable: bridge vlan hardware offload and\n switchdev\n\nThe switch might have already added the VLAN tag through PVID hardware\noffload. Keep this extra VLAN in the flowtable but skip it on egress.\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\nSigned-off-by: Pablo Neira Ayuso <pablo@netfilter.org>\n---\n\n--- a/include/linux/netdevice.h\n+++ b/include/linux/netdevice.h\n@@ -849,6 +849,7 @@ struct net_device_path {\n \t\t\t\tDEV_PATH_BR_VLAN_KEEP,\n \t\t\t\tDEV_PATH_BR_VLAN_TAG,\n \t\t\t\tDEV_PATH_BR_VLAN_UNTAG,\n+\t\t\t\tDEV_PATH_BR_VLAN_UNTAG_HW,\n \t\t\t}\t\tvlan_mode;\n \t\t\tu16\t\tvlan_id;\n \t\t\t__be16\t\tvlan_proto;\n--- a/include/net/netfilter/nf_flow_table.h\n+++ b/include/net/netfilter/nf_flow_table.h\n@@ -123,9 +123,10 @@ struct flow_offload_tuple {\n \t/* All members above are keys for lookups, see flow_offload_hash(). */\n \tstruct { }\t\t\t__hash;\n \n-\tu8\t\t\t\tdir:4,\n+\tu8\t\t\t\tdir:2,\n \t\t\t\t\txmit_type:2,\n-\t\t\t\t\tencap_num:2;\n+\t\t\t\t\tencap_num:2,\n+\t\t\t\t\tin_vlan_ingress:2;\n \tu16\t\t\t\tmtu;\n \tunion {\n \t\tstruct dst_entry\t*dst_cache;\n@@ -184,7 +185,8 @@ struct nf_flow_route {\n \t\t\t\tu16\t\tid;\n \t\t\t\t__be16\t\tproto;\n \t\t\t} encap[NF_FLOW_TABLE_ENCAP_MAX];\n-\t\t\tu8\t\t\tnum_encaps;\n+\t\t\tu8\t\t\tnum_encaps:2,\n+\t\t\t\t\t\tingress_vlans:2;\n \t\t} in;\n \t\tstruct {\n \t\t\tu32\t\t\tifindex;\n--- a/net/bridge/br_device.c\n+++ b/net/bridge/br_device.c\n@@ -435,6 +435,7 @@ static int br_fill_forward_path(struct n\n \t\tctx->vlan[ctx->num_vlans].proto = path->bridge.vlan_proto;\n \t\tctx->num_vlans++;\n \t\tbreak;\n+\tcase DEV_PATH_BR_VLAN_UNTAG_HW:\n \tcase DEV_PATH_BR_VLAN_UNTAG:\n \t\tctx->num_vlans--;\n \t\tbreak;\n--- a/net/bridge/br_vlan.c\n+++ b/net/bridge/br_vlan.c\n@@ -1374,6 +1374,8 @@ int br_vlan_fill_forward_path_mode(struc\n \n \tif (path->bridge.vlan_mode == DEV_PATH_BR_VLAN_TAG)\n \t\tpath->bridge.vlan_mode = DEV_PATH_BR_VLAN_KEEP;\n+\telse if (v->priv_flags & BR_VLFLAG_ADDED_BY_SWITCHDEV)\n+\t\tpath->bridge.vlan_mode = DEV_PATH_BR_VLAN_UNTAG_HW;\n \telse\n \t\tpath->bridge.vlan_mode = DEV_PATH_BR_VLAN_UNTAG;\n \n--- a/net/netfilter/nf_flow_table_core.c\n+++ b/net/netfilter/nf_flow_table_core.c\n@@ -95,6 +95,8 @@ static int flow_offload_fill_route(struc\n \tfor (i = route->tuple[dir].in.num_encaps - 1; i >= 0; i--) {\n \t\tflow_tuple->encap[j].id = route->tuple[dir].in.encap[i].id;\n \t\tflow_tuple->encap[j].proto = route->tuple[dir].in.encap[i].proto;\n+\t\tif (route->tuple[dir].in.ingress_vlans & BIT(i))\n+\t\t\tflow_tuple->in_vlan_ingress |= BIT(j);\n \t\tj++;\n \t}\n \tflow_tuple->encap_num = route->tuple[dir].in.num_encaps;\n--- a/net/netfilter/nf_flow_table_offload.c\n+++ b/net/netfilter/nf_flow_table_offload.c\n@@ -594,8 +594,12 @@ nf_flow_rule_route_common(struct net *ne\n \tother_tuple = &flow->tuplehash[!dir].tuple;\n \n \tfor (i = 0; i < other_tuple->encap_num; i++) {\n-\t\tstruct flow_action_entry *entry = flow_action_entry_next(flow_rule);\n+\t\tstruct flow_action_entry *entry;\n \n+\t\tif (other_tuple->in_vlan_ingress & BIT(i))\n+\t\t\tcontinue;\n+\n+\t\tentry = flow_action_entry_next(flow_rule);\n \t\tentry->id = FLOW_ACTION_VLAN_PUSH;\n \t\tentry->vlan.vid = other_tuple->encap[i].id;\n \t\tentry->vlan.proto = other_tuple->encap[i].proto;\n--- a/net/netfilter/nft_flow_offload.c\n+++ b/net/netfilter/nft_flow_offload.c\n@@ -72,6 +72,7 @@ struct nft_forward_info {\n \t\t__be16\tproto;\n \t} encap[NF_FLOW_TABLE_ENCAP_MAX];\n \tu8 num_encaps;\n+\tu8 ingress_vlans;\n \tu8 h_source[ETH_ALEN];\n \tu8 h_dest[ETH_ALEN];\n \tenum flow_offload_xmit_type xmit_type;\n@@ -130,6 +131,9 @@ static void nft_dev_path_info(const stru\n \t\t\t\tmemcpy(info->h_source, path->dev->dev_addr, ETH_ALEN);\n \n \t\t\tswitch (path->bridge.vlan_mode) {\n+\t\t\tcase DEV_PATH_BR_VLAN_UNTAG_HW:\n+\t\t\t\tinfo->ingress_vlans |= BIT(info->num_encaps - 1);\n+\t\t\t\tbreak;\n \t\t\tcase DEV_PATH_BR_VLAN_TAG:\n \t\t\t\tinfo->encap[info->num_encaps].id = path->bridge.vlan_id;\n \t\t\t\tinfo->encap[info->num_encaps].proto = path->bridge.vlan_proto;\n@@ -198,6 +202,7 @@ static void nft_dev_forward_path(struct\n \t\troute->tuple[!dir].in.encap[i].proto = info.encap[i].proto;\n \t}\n \troute->tuple[!dir].in.num_encaps = info.num_encaps;\n+\troute->tuple[!dir].in.ingress_vlans = info.ingress_vlans;\n \n \tif (info.xmit_type == FLOW_OFFLOAD_XMIT_DIRECT) {\n \t\tmemcpy(route->tuple[dir].out.h_source, info.h_source, ETH_ALEN);\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/610-v5.13-28-net-flow_offload-add-FLOW_ACTION_PPPOE_PUSH.patch",
    "content": "From: Pablo Neira Ayuso <pablo@netfilter.org>\nDate: Wed, 24 Mar 2021 02:30:49 +0100\nSubject: [PATCH] net: flow_offload: add FLOW_ACTION_PPPOE_PUSH\n\nAdd an action to represent the PPPoE hardware offload support that\nincludes the session ID.\n\nSigned-off-by: Pablo Neira Ayuso <pablo@netfilter.org>\n---\n\n--- a/include/net/flow_offload.h\n+++ b/include/net/flow_offload.h\n@@ -147,6 +147,7 @@ enum flow_action_id {\n \tFLOW_ACTION_MPLS_POP,\n \tFLOW_ACTION_MPLS_MANGLE,\n \tFLOW_ACTION_GATE,\n+\tFLOW_ACTION_PPPOE_PUSH,\n \tNUM_FLOW_ACTIONS,\n };\n \n@@ -271,6 +272,9 @@ struct flow_action_entry {\n \t\t\tu32\t\tnum_entries;\n \t\t\tstruct action_gate_entry *entries;\n \t\t} gate;\n+\t\tstruct {\t\t\t\t/* FLOW_ACTION_PPPOE_PUSH */\n+\t\t\tu16\t\tsid;\n+\t\t} pppoe;\n \t};\n \tstruct flow_action_cookie *cookie; /* user defined action cookie */\n };\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/610-v5.13-29-netfilter-flowtable-support-for-FLOW_ACTION_PPPOE_PU.patch",
    "content": "From: Pablo Neira Ayuso <pablo@netfilter.org>\nDate: Wed, 24 Mar 2021 02:30:50 +0100\nSubject: [PATCH] netfilter: flowtable: support for\n FLOW_ACTION_PPPOE_PUSH\n\nAdd a PPPoE push action if layer 2 protocol is ETH_P_PPP_SES to add\nPPPoE flowtable hardware offload support.\n\nSigned-off-by: Pablo Neira Ayuso <pablo@netfilter.org>\n---\n\n--- a/net/netfilter/nf_flow_table_offload.c\n+++ b/net/netfilter/nf_flow_table_offload.c\n@@ -600,9 +600,18 @@ nf_flow_rule_route_common(struct net *ne\n \t\t\tcontinue;\n \n \t\tentry = flow_action_entry_next(flow_rule);\n-\t\tentry->id = FLOW_ACTION_VLAN_PUSH;\n-\t\tentry->vlan.vid = other_tuple->encap[i].id;\n-\t\tentry->vlan.proto = other_tuple->encap[i].proto;\n+\n+\t\tswitch (other_tuple->encap[i].proto) {\n+\t\tcase htons(ETH_P_PPP_SES):\n+\t\t\tentry->id = FLOW_ACTION_PPPOE_PUSH;\n+\t\t\tentry->pppoe.sid = other_tuple->encap[i].id;\n+\t\t\tbreak;\n+\t\tcase htons(ETH_P_8021Q):\n+\t\t\tentry->id = FLOW_ACTION_VLAN_PUSH;\n+\t\t\tentry->vlan.vid = other_tuple->encap[i].id;\n+\t\t\tentry->vlan.proto = other_tuple->encap[i].proto;\n+\t\t\tbreak;\n+\t\t}\n \t}\n \n \treturn 0;\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/610-v5.13-30-dsa-slave-add-support-for-TC_SETUP_FT.patch",
    "content": "From: Pablo Neira Ayuso <pablo@netfilter.org>\nDate: Wed, 24 Mar 2021 02:30:51 +0100\nSubject: [PATCH] dsa: slave: add support for TC_SETUP_FT\n\nThe dsa infrastructure provides a well-defined hierarchy of devices,\npass up the call to set up the flow block to the master device. From the\nsoftware dataplane, the netfilter infrastructure uses the dsa slave\ndevices to refer to the input and output device for the given skbuff.\nSimilarly, the flowtable definition in the ruleset refers to the dsa\nslave port devices.\n\nThis patch adds the glue code to call ndo_setup_tc with TC_SETUP_FT\nwith the master device via the dsa slave devices.\n\nSigned-off-by: Pablo Neira Ayuso <pablo@netfilter.org>\n---\n\n--- a/net/dsa/slave.c\n+++ b/net/dsa/slave.c\n@@ -1239,14 +1239,32 @@ static int dsa_slave_setup_tc_block(stru\n \t}\n }\n \n+static int dsa_slave_setup_ft_block(struct dsa_switch *ds, int port,\n+\t\t\t\t    void *type_data)\n+{\n+\tstruct dsa_port *cpu_dp = dsa_to_port(ds, port)->cpu_dp;\n+\tstruct net_device *master = cpu_dp->master;\n+\n+\tif (!master->netdev_ops->ndo_setup_tc)\n+\t\treturn -EOPNOTSUPP;\n+\n+\treturn master->netdev_ops->ndo_setup_tc(master, TC_SETUP_FT, type_data);\n+}\n+\n static int dsa_slave_setup_tc(struct net_device *dev, enum tc_setup_type type,\n \t\t\t      void *type_data)\n {\n \tstruct dsa_port *dp = dsa_slave_to_port(dev);\n \tstruct dsa_switch *ds = dp->ds;\n \n-\tif (type == TC_SETUP_BLOCK)\n+\tswitch (type) {\n+\tcase TC_SETUP_BLOCK:\n \t\treturn dsa_slave_setup_tc_block(dev, type_data);\n+\tcase TC_SETUP_FT:\n+\t\treturn dsa_slave_setup_ft_block(ds, dp->index, type_data);\n+\tdefault:\n+\t\tbreak;\n+\t}\n \n \tif (!ds->ops->port_setup_tc)\n \t\treturn -EOPNOTSUPP;\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/610-v5.13-31-net-ethernet-mtk_eth_soc-fix-parsing-packets-in-GDM.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nDate: Wed, 24 Mar 2021 02:30:52 +0100\nSubject: [PATCH] net: ethernet: mtk_eth_soc: fix parsing packets in GDM\n\nWhen using DSA, set the special tag in GDM ingress control to allow the MAC\nto parse packets properly earlier. This affects rx DMA source port reporting.\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\nSigned-off-by: Pablo Neira Ayuso <pablo@netfilter.org>\n---\n\n--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c\n+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c\n@@ -19,6 +19,7 @@\n #include <linux/interrupt.h>\n #include <linux/pinctrl/devinfo.h>\n #include <linux/phylink.h>\n+#include <net/dsa.h>\n \n #include \"mtk_eth_soc.h\"\n \n@@ -1285,13 +1286,12 @@ static int mtk_poll_rx(struct napi_struc\n \t\t\tbreak;\n \n \t\t/* find out which mac the packet come from. values start at 1 */\n-\t\tif (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) {\n+\t\tif (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) ||\n+\t\t    (trxd.rxd4 & RX_DMA_SPECIAL_TAG))\n \t\t\tmac = 0;\n-\t\t} else {\n-\t\t\tmac = (trxd.rxd4 >> RX_DMA_FPORT_SHIFT) &\n-\t\t\t\tRX_DMA_FPORT_MASK;\n-\t\t\tmac--;\n-\t\t}\n+\t\telse\n+\t\t\tmac = ((trxd.rxd4 >> RX_DMA_FPORT_SHIFT) &\n+\t\t\t       RX_DMA_FPORT_MASK) - 1;\n \n \t\tif (unlikely(mac < 0 || mac >= MTK_MAC_COUNT ||\n \t\t\t     !eth->netdev[mac]))\n@@ -2254,6 +2254,9 @@ static void mtk_gdm_config(struct mtk_et\n \n \t\tval |= config;\n \n+\t\tif (!i && eth->netdev[0] && netdev_uses_dsa(eth->netdev[0]))\n+\t\t\tval |= MTK_GDMA_SPECIAL_TAG;\n+\n \t\tmtk_w32(eth, val, MTK_GDMA_FWD_CFG(i));\n \t}\n \t/* Reset and enable PSE */\n--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h\n+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h\n@@ -81,6 +81,7 @@\n \n /* GDM Exgress Control Register */\n #define MTK_GDMA_FWD_CFG(x)\t(0x500 + (x * 0x1000))\n+#define MTK_GDMA_SPECIAL_TAG\tBIT(24)\n #define MTK_GDMA_ICS_EN\t\tBIT(22)\n #define MTK_GDMA_TCS_EN\t\tBIT(21)\n #define MTK_GDMA_UCS_EN\t\tBIT(20)\n@@ -318,6 +319,7 @@\n #define RX_DMA_L4_VALID_PDMA\tBIT(30)\t\t/* when PDMA is used */\n #define RX_DMA_FPORT_SHIFT\t19\n #define RX_DMA_FPORT_MASK\t0x7\n+#define RX_DMA_SPECIAL_TAG\tBIT(22)\n \n /* PHY Indirect Access Control registers */\n #define MTK_PHY_IAC\t\t0x10004\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/610-v5.13-32-net-ethernet-mtk_eth_soc-add-support-for-initializin.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nDate: Wed, 24 Mar 2021 02:30:53 +0100\nSubject: [PATCH] net: ethernet: mtk_eth_soc: add support for\n initializing the PPE\n\nThe PPE (packet processing engine) is used to offload NAT/routed or even\nbridged flows. This patch brings up the PPE and uses it to get a packet\nhash. It also contains some functionality that will be used to bring up\nflow offloading.\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\nSigned-off-by: Pablo Neira Ayuso <pablo@netfilter.org>\n---\n create mode 100644 drivers/net/ethernet/mediatek/mtk_ppe.c\n create mode 100644 drivers/net/ethernet/mediatek/mtk_ppe.h\n create mode 100644 drivers/net/ethernet/mediatek/mtk_ppe_debugfs.c\n create mode 100644 drivers/net/ethernet/mediatek/mtk_ppe_regs.h\n\n--- a/drivers/net/ethernet/mediatek/Makefile\n+++ b/drivers/net/ethernet/mediatek/Makefile\n@@ -4,5 +4,5 @@\n #\n \n obj-$(CONFIG_NET_MEDIATEK_SOC) += mtk_eth.o\n-mtk_eth-y := mtk_eth_soc.o mtk_sgmii.o mtk_eth_path.o\n+mtk_eth-y := mtk_eth_soc.o mtk_sgmii.o mtk_eth_path.o mtk_ppe.o mtk_ppe_debugfs.o\n obj-$(CONFIG_NET_MEDIATEK_STAR_EMAC) += mtk_star_emac.o\n--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c\n+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c\n@@ -2279,12 +2279,17 @@ static int mtk_open(struct net_device *d\n \n \t/* we run 2 netdevs on the same dma ring so we only bring it up once */\n \tif (!refcount_read(&eth->dma_refcnt)) {\n-\t\tint err = mtk_start_dma(eth);\n+\t\tu32 gdm_config = MTK_GDMA_TO_PDMA;\n+\t\tint err;\n \n+\t\terr = mtk_start_dma(eth);\n \t\tif (err)\n \t\t\treturn err;\n \n-\t\tmtk_gdm_config(eth, MTK_GDMA_TO_PDMA);\n+\t\tif (eth->soc->offload_version && mtk_ppe_start(&eth->ppe) == 0)\n+\t\t\tgdm_config = MTK_GDMA_TO_PPE;\n+\n+\t\tmtk_gdm_config(eth, gdm_config);\n \n \t\tnapi_enable(&eth->tx_napi);\n \t\tnapi_enable(&eth->rx_napi);\n@@ -2351,6 +2356,9 @@ static int mtk_stop(struct net_device *d\n \n \tmtk_dma_free(eth);\n \n+\tif (eth->soc->offload_version)\n+\t\tmtk_ppe_stop(&eth->ppe);\n+\n \treturn 0;\n }\n \n@@ -3079,6 +3087,13 @@ static int mtk_probe(struct platform_dev\n \t\t\tgoto err_free_dev;\n \t}\n \n+\tif (eth->soc->offload_version) {\n+\t\terr = mtk_ppe_init(&eth->ppe, eth->dev,\n+\t\t\t\t   eth->base + MTK_ETH_PPE_BASE, 2);\n+\t\tif (err)\n+\t\t\tgoto err_free_dev;\n+\t}\n+\n \tfor (i = 0; i < MTK_MAX_DEVS; i++) {\n \t\tif (!eth->netdev[i])\n \t\t\tcontinue;\n@@ -3153,6 +3168,7 @@ static const struct mtk_soc_data mt7621_\n \t.hw_features = MTK_HW_FEATURES,\n \t.required_clks = MT7621_CLKS_BITMAP,\n \t.required_pctl = false,\n+\t.offload_version = 2,\n };\n \n static const struct mtk_soc_data mt7622_data = {\n@@ -3161,6 +3177,7 @@ static const struct mtk_soc_data mt7622_\n \t.hw_features = MTK_HW_FEATURES,\n \t.required_clks = MT7622_CLKS_BITMAP,\n \t.required_pctl = false,\n+\t.offload_version = 2,\n };\n \n static const struct mtk_soc_data mt7623_data = {\n--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h\n+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h\n@@ -15,6 +15,7 @@\n #include <linux/u64_stats_sync.h>\n #include <linux/refcount.h>\n #include <linux/phylink.h>\n+#include \"mtk_ppe.h\"\n \n #define MTK_QDMA_PAGE_SIZE\t2048\n #define\tMTK_MAX_RX_LENGTH\t1536\n@@ -86,6 +87,7 @@\n #define MTK_GDMA_TCS_EN\t\tBIT(21)\n #define MTK_GDMA_UCS_EN\t\tBIT(20)\n #define MTK_GDMA_TO_PDMA\t0x0\n+#define MTK_GDMA_TO_PPE\t\t0x4444\n #define MTK_GDMA_DROP_ALL       0x7777\n \n /* Unicast Filter MAC Address Register - Low */\n@@ -315,6 +317,12 @@\n #define RX_DMA_VID(_x)\t\t((_x) & 0xfff)\n \n /* QDMA descriptor rxd4 */\n+#define MTK_RXD4_FOE_ENTRY\tGENMASK(13, 0)\n+#define MTK_RXD4_PPE_CPU_REASON\tGENMASK(18, 14)\n+#define MTK_RXD4_SRC_PORT\tGENMASK(21, 19)\n+#define MTK_RXD4_ALG\t\tGENMASK(31, 22)\n+\n+/* QDMA descriptor rxd4 */\n #define RX_DMA_L4_VALID\t\tBIT(24)\n #define RX_DMA_L4_VALID_PDMA\tBIT(30)\t\t/* when PDMA is used */\n #define RX_DMA_FPORT_SHIFT\t19\n@@ -819,6 +827,7 @@ struct mtk_soc_data {\n \tu32\t\tcaps;\n \tu32\t\trequired_clks;\n \tbool\t\trequired_pctl;\n+\tu8\t\toffload_version;\n \tnetdev_features_t hw_features;\n };\n \n@@ -918,6 +927,8 @@ struct mtk_eth {\n \tu32\t\t\t\ttx_int_status_reg;\n \tu32\t\t\t\trx_dma_l4_valid;\n \tint\t\t\t\tip_align;\n+\n+\tstruct mtk_ppe\t\t\tppe;\n };\n \n /* struct mtk_mac -\tthe structure that holds the info about the MACs of the\n--- /dev/null\n+++ b/drivers/net/ethernet/mediatek/mtk_ppe.c\n@@ -0,0 +1,511 @@\n+// SPDX-License-Identifier: GPL-2.0-only\n+/* Copyright (C) 2020 Felix Fietkau <nbd@nbd.name> */\n+\n+#include <linux/kernel.h>\n+#include <linux/jiffies.h>\n+#include <linux/delay.h>\n+#include <linux/io.h>\n+#include <linux/etherdevice.h>\n+#include <linux/platform_device.h>\n+#include \"mtk_ppe.h\"\n+#include \"mtk_ppe_regs.h\"\n+\n+static void ppe_w32(struct mtk_ppe *ppe, u32 reg, u32 val)\n+{\n+\twritel(val, ppe->base + reg);\n+}\n+\n+static u32 ppe_r32(struct mtk_ppe *ppe, u32 reg)\n+{\n+\treturn readl(ppe->base + reg);\n+}\n+\n+static u32 ppe_m32(struct mtk_ppe *ppe, u32 reg, u32 mask, u32 set)\n+{\n+\tu32 val;\n+\n+\tval = ppe_r32(ppe, reg);\n+\tval &= ~mask;\n+\tval |= set;\n+\tppe_w32(ppe, reg, val);\n+\n+\treturn val;\n+}\n+\n+static u32 ppe_set(struct mtk_ppe *ppe, u32 reg, u32 val)\n+{\n+\treturn ppe_m32(ppe, reg, 0, val);\n+}\n+\n+static u32 ppe_clear(struct mtk_ppe *ppe, u32 reg, u32 val)\n+{\n+\treturn ppe_m32(ppe, reg, val, 0);\n+}\n+\n+static int mtk_ppe_wait_busy(struct mtk_ppe *ppe)\n+{\n+\tunsigned long timeout = jiffies + HZ;\n+\n+\twhile (time_is_before_jiffies(timeout)) {\n+\t\tif (!(ppe_r32(ppe, MTK_PPE_GLO_CFG) & MTK_PPE_GLO_CFG_BUSY))\n+\t\t\treturn 0;\n+\n+\t\tusleep_range(10, 20);\n+\t}\n+\n+\tdev_err(ppe->dev, \"PPE table busy\");\n+\n+\treturn -ETIMEDOUT;\n+}\n+\n+static void mtk_ppe_cache_clear(struct mtk_ppe *ppe)\n+{\n+\tppe_set(ppe, MTK_PPE_CACHE_CTL, MTK_PPE_CACHE_CTL_CLEAR);\n+\tppe_clear(ppe, MTK_PPE_CACHE_CTL, MTK_PPE_CACHE_CTL_CLEAR);\n+}\n+\n+static void mtk_ppe_cache_enable(struct mtk_ppe *ppe, bool enable)\n+{\n+\tmtk_ppe_cache_clear(ppe);\n+\n+\tppe_m32(ppe, MTK_PPE_CACHE_CTL, MTK_PPE_CACHE_CTL_EN,\n+\t\tenable * MTK_PPE_CACHE_CTL_EN);\n+}\n+\n+static u32 mtk_ppe_hash_entry(struct mtk_foe_entry *e)\n+{\n+\tu32 hv1, hv2, hv3;\n+\tu32 hash;\n+\n+\tswitch (FIELD_GET(MTK_FOE_IB1_PACKET_TYPE, e->ib1)) {\n+\t\tcase MTK_PPE_PKT_TYPE_BRIDGE:\n+\t\t\thv1 = e->bridge.src_mac_lo;\n+\t\t\thv1 ^= ((e->bridge.src_mac_hi & 0xffff) << 16);\n+\t\t\thv2 = e->bridge.src_mac_hi >> 16;\n+\t\t\thv2 ^= e->bridge.dest_mac_lo;\n+\t\t\thv3 = e->bridge.dest_mac_hi;\n+\t\t\tbreak;\n+\t\tcase MTK_PPE_PKT_TYPE_IPV4_ROUTE:\n+\t\tcase MTK_PPE_PKT_TYPE_IPV4_HNAPT:\n+\t\t\thv1 = e->ipv4.orig.ports;\n+\t\t\thv2 = e->ipv4.orig.dest_ip;\n+\t\t\thv3 = e->ipv4.orig.src_ip;\n+\t\t\tbreak;\n+\t\tcase MTK_PPE_PKT_TYPE_IPV6_ROUTE_3T:\n+\t\tcase MTK_PPE_PKT_TYPE_IPV6_ROUTE_5T:\n+\t\t\thv1 = e->ipv6.src_ip[3] ^ e->ipv6.dest_ip[3];\n+\t\t\thv1 ^= e->ipv6.ports;\n+\n+\t\t\thv2 = e->ipv6.src_ip[2] ^ e->ipv6.dest_ip[2];\n+\t\t\thv2 ^= e->ipv6.dest_ip[0];\n+\n+\t\t\thv3 = e->ipv6.src_ip[1] ^ e->ipv6.dest_ip[1];\n+\t\t\thv3 ^= e->ipv6.src_ip[0];\n+\t\t\tbreak;\n+\t\tcase MTK_PPE_PKT_TYPE_IPV4_DSLITE:\n+\t\tcase MTK_PPE_PKT_TYPE_IPV6_6RD:\n+\t\tdefault:\n+\t\t\tWARN_ON_ONCE(1);\n+\t\t\treturn MTK_PPE_HASH_MASK;\n+\t}\n+\n+\thash = (hv1 & hv2) | ((~hv1) & hv3);\n+\thash = (hash >> 24) | ((hash & 0xffffff) << 8);\n+\thash ^= hv1 ^ hv2 ^ hv3;\n+\thash ^= hash >> 16;\n+\thash <<= 1;\n+\thash &= MTK_PPE_ENTRIES - 1;\n+\n+\treturn hash;\n+}\n+\n+static inline struct mtk_foe_mac_info *\n+mtk_foe_entry_l2(struct mtk_foe_entry *entry)\n+{\n+\tint type = FIELD_GET(MTK_FOE_IB1_PACKET_TYPE, entry->ib1);\n+\n+\tif (type >= MTK_PPE_PKT_TYPE_IPV4_DSLITE)\n+\t\treturn &entry->ipv6.l2;\n+\n+\treturn &entry->ipv4.l2;\n+}\n+\n+static inline u32 *\n+mtk_foe_entry_ib2(struct mtk_foe_entry *entry)\n+{\n+\tint type = FIELD_GET(MTK_FOE_IB1_PACKET_TYPE, entry->ib1);\n+\n+\tif (type >= MTK_PPE_PKT_TYPE_IPV4_DSLITE)\n+\t\treturn &entry->ipv6.ib2;\n+\n+\treturn &entry->ipv4.ib2;\n+}\n+\n+int mtk_foe_entry_prepare(struct mtk_foe_entry *entry, int type, int l4proto,\n+\t\t\t  u8 pse_port, u8 *src_mac, u8 *dest_mac)\n+{\n+\tstruct mtk_foe_mac_info *l2;\n+\tu32 ports_pad, val;\n+\n+\tmemset(entry, 0, sizeof(*entry));\n+\n+\tval = FIELD_PREP(MTK_FOE_IB1_STATE, MTK_FOE_STATE_BIND) |\n+\t      FIELD_PREP(MTK_FOE_IB1_PACKET_TYPE, type) |\n+\t      FIELD_PREP(MTK_FOE_IB1_UDP, l4proto == IPPROTO_UDP) |\n+\t      MTK_FOE_IB1_BIND_TTL |\n+\t      MTK_FOE_IB1_BIND_CACHE;\n+\tentry->ib1 = val;\n+\n+\tval = FIELD_PREP(MTK_FOE_IB2_PORT_MG, 0x3f) |\n+\t      FIELD_PREP(MTK_FOE_IB2_PORT_AG, 0x1f) |\n+\t      FIELD_PREP(MTK_FOE_IB2_DEST_PORT, pse_port);\n+\n+\tif (is_multicast_ether_addr(dest_mac))\n+\t\tval |= MTK_FOE_IB2_MULTICAST;\n+\n+\tports_pad = 0xa5a5a500 | (l4proto & 0xff);\n+\tif (type == MTK_PPE_PKT_TYPE_IPV4_ROUTE)\n+\t\tentry->ipv4.orig.ports = ports_pad;\n+\tif (type == MTK_PPE_PKT_TYPE_IPV6_ROUTE_3T)\n+\t\tentry->ipv6.ports = ports_pad;\n+\n+\tif (type >= MTK_PPE_PKT_TYPE_IPV4_DSLITE) {\n+\t\tentry->ipv6.ib2 = val;\n+\t\tl2 = &entry->ipv6.l2;\n+\t} else {\n+\t\tentry->ipv4.ib2 = val;\n+\t\tl2 = &entry->ipv4.l2;\n+\t}\n+\n+\tl2->dest_mac_hi = get_unaligned_be32(dest_mac);\n+\tl2->dest_mac_lo = get_unaligned_be16(dest_mac + 4);\n+\tl2->src_mac_hi = get_unaligned_be32(src_mac);\n+\tl2->src_mac_lo = get_unaligned_be16(src_mac + 4);\n+\n+\tif (type >= MTK_PPE_PKT_TYPE_IPV6_ROUTE_3T)\n+\t\tl2->etype = ETH_P_IPV6;\n+\telse\n+\t\tl2->etype = ETH_P_IP;\n+\n+\treturn 0;\n+}\n+\n+int mtk_foe_entry_set_pse_port(struct mtk_foe_entry *entry, u8 port)\n+{\n+\tu32 *ib2 = mtk_foe_entry_ib2(entry);\n+\tu32 val;\n+\n+\tval = *ib2;\n+\tval &= ~MTK_FOE_IB2_DEST_PORT;\n+\tval |= FIELD_PREP(MTK_FOE_IB2_DEST_PORT, port);\n+\t*ib2 = val;\n+\n+\treturn 0;\n+}\n+\n+int mtk_foe_entry_set_ipv4_tuple(struct mtk_foe_entry *entry, bool egress,\n+\t\t\t\t __be32 src_addr, __be16 src_port,\n+\t\t\t\t __be32 dest_addr, __be16 dest_port)\n+{\n+\tint type = FIELD_GET(MTK_FOE_IB1_PACKET_TYPE, entry->ib1);\n+\tstruct mtk_ipv4_tuple *t;\n+\n+\tswitch (type) {\n+\tcase MTK_PPE_PKT_TYPE_IPV4_HNAPT:\n+\t\tif (egress) {\n+\t\t\tt = &entry->ipv4.new;\n+\t\t\tbreak;\n+\t\t}\n+\t\tfallthrough;\n+\tcase MTK_PPE_PKT_TYPE_IPV4_DSLITE:\n+\tcase MTK_PPE_PKT_TYPE_IPV4_ROUTE:\n+\t\tt = &entry->ipv4.orig;\n+\t\tbreak;\n+\tcase MTK_PPE_PKT_TYPE_IPV6_6RD:\n+\t\tentry->ipv6_6rd.tunnel_src_ip = be32_to_cpu(src_addr);\n+\t\tentry->ipv6_6rd.tunnel_dest_ip = be32_to_cpu(dest_addr);\n+\t\treturn 0;\n+\tdefault:\n+\t\tWARN_ON_ONCE(1);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tt->src_ip = be32_to_cpu(src_addr);\n+\tt->dest_ip = be32_to_cpu(dest_addr);\n+\n+\tif (type == MTK_PPE_PKT_TYPE_IPV4_ROUTE)\n+\t\treturn 0;\n+\n+\tt->src_port = be16_to_cpu(src_port);\n+\tt->dest_port = be16_to_cpu(dest_port);\n+\n+\treturn 0;\n+}\n+\n+int mtk_foe_entry_set_ipv6_tuple(struct mtk_foe_entry *entry,\n+\t\t\t\t __be32 *src_addr, __be16 src_port,\n+\t\t\t\t __be32 *dest_addr, __be16 dest_port)\n+{\n+\tint type = FIELD_GET(MTK_FOE_IB1_PACKET_TYPE, entry->ib1);\n+\tu32 *src, *dest;\n+\tint i;\n+\n+\tswitch (type) {\n+\tcase MTK_PPE_PKT_TYPE_IPV4_DSLITE:\n+\t\tsrc = entry->dslite.tunnel_src_ip;\n+\t\tdest = entry->dslite.tunnel_dest_ip;\n+\t\tbreak;\n+\tcase MTK_PPE_PKT_TYPE_IPV6_ROUTE_5T:\n+\tcase MTK_PPE_PKT_TYPE_IPV6_6RD:\n+\t\tentry->ipv6.src_port = be16_to_cpu(src_port);\n+\t\tentry->ipv6.dest_port = be16_to_cpu(dest_port);\n+\t\tfallthrough;\n+\tcase MTK_PPE_PKT_TYPE_IPV6_ROUTE_3T:\n+\t\tsrc = entry->ipv6.src_ip;\n+\t\tdest = entry->ipv6.dest_ip;\n+\t\tbreak;\n+\tdefault:\n+\t\tWARN_ON_ONCE(1);\n+\t\treturn -EINVAL;\n+\t};\n+\n+\tfor (i = 0; i < 4; i++)\n+\t\tsrc[i] = be32_to_cpu(src_addr[i]);\n+\tfor (i = 0; i < 4; i++)\n+\t\tdest[i] = be32_to_cpu(dest_addr[i]);\n+\n+\treturn 0;\n+}\n+\n+int mtk_foe_entry_set_dsa(struct mtk_foe_entry *entry, int port)\n+{\n+\tstruct mtk_foe_mac_info *l2 = mtk_foe_entry_l2(entry);\n+\n+\tl2->etype = BIT(port);\n+\n+\tif (!(entry->ib1 & MTK_FOE_IB1_BIND_VLAN_LAYER))\n+\t\tentry->ib1 |= FIELD_PREP(MTK_FOE_IB1_BIND_VLAN_LAYER, 1);\n+\telse\n+\t\tl2->etype |= BIT(8);\n+\n+\tentry->ib1 &= ~MTK_FOE_IB1_BIND_VLAN_TAG;\n+\n+\treturn 0;\n+}\n+\n+int mtk_foe_entry_set_vlan(struct mtk_foe_entry *entry, int vid)\n+{\n+\tstruct mtk_foe_mac_info *l2 = mtk_foe_entry_l2(entry);\n+\n+\tswitch (FIELD_GET(MTK_FOE_IB1_BIND_VLAN_LAYER, entry->ib1)) {\n+\tcase 0:\n+\t\tentry->ib1 |= MTK_FOE_IB1_BIND_VLAN_TAG |\n+\t\t\t      FIELD_PREP(MTK_FOE_IB1_BIND_VLAN_LAYER, 1);\n+\t\tl2->vlan1 = vid;\n+\t\treturn 0;\n+\tcase 1:\n+\t\tif (!(entry->ib1 & MTK_FOE_IB1_BIND_VLAN_TAG)) {\n+\t\t\tl2->vlan1 = vid;\n+\t\t\tl2->etype |= BIT(8);\n+\t\t} else {\n+\t\t\tl2->vlan2 = vid;\n+\t\t\tentry->ib1 += FIELD_PREP(MTK_FOE_IB1_BIND_VLAN_LAYER, 1);\n+\t\t}\n+\t\treturn 0;\n+\tdefault:\n+\t\treturn -ENOSPC;\n+\t}\n+}\n+\n+int mtk_foe_entry_set_pppoe(struct mtk_foe_entry *entry, int sid)\n+{\n+\tstruct mtk_foe_mac_info *l2 = mtk_foe_entry_l2(entry);\n+\n+\tif (!(entry->ib1 & MTK_FOE_IB1_BIND_VLAN_LAYER) ||\n+\t    (entry->ib1 & MTK_FOE_IB1_BIND_VLAN_TAG))\n+\t\tl2->etype = ETH_P_PPP_SES;\n+\n+\tentry->ib1 |= MTK_FOE_IB1_BIND_PPPOE;\n+\tl2->pppoe_id = sid;\n+\n+\treturn 0;\n+}\n+\n+static inline bool mtk_foe_entry_usable(struct mtk_foe_entry *entry)\n+{\n+\treturn !(entry->ib1 & MTK_FOE_IB1_STATIC) &&\n+\t       FIELD_GET(MTK_FOE_IB1_STATE, entry->ib1) != MTK_FOE_STATE_BIND;\n+}\n+\n+int mtk_foe_entry_commit(struct mtk_ppe *ppe, struct mtk_foe_entry *entry,\n+\t\t\t u16 timestamp)\n+{\n+\tstruct mtk_foe_entry *hwe;\n+\tu32 hash;\n+\n+\ttimestamp &= MTK_FOE_IB1_BIND_TIMESTAMP;\n+\tentry->ib1 &= ~MTK_FOE_IB1_BIND_TIMESTAMP;\n+\tentry->ib1 |= FIELD_PREP(MTK_FOE_IB1_BIND_TIMESTAMP, timestamp);\n+\n+\thash = mtk_ppe_hash_entry(entry);\n+\thwe = &ppe->foe_table[hash];\n+\tif (!mtk_foe_entry_usable(hwe)) {\n+\t\thwe++;\n+\t\thash++;\n+\n+\t\tif (!mtk_foe_entry_usable(hwe))\n+\t\t\treturn -ENOSPC;\n+\t}\n+\n+\tmemcpy(&hwe->data, &entry->data, sizeof(hwe->data));\n+\twmb();\n+\thwe->ib1 = entry->ib1;\n+\n+\tdma_wmb();\n+\n+\tmtk_ppe_cache_clear(ppe);\n+\n+\treturn hash;\n+}\n+\n+int mtk_ppe_init(struct mtk_ppe *ppe, struct device *dev, void __iomem *base,\n+\t\t int version)\n+{\n+\tstruct mtk_foe_entry *foe;\n+\n+\t/* need to allocate a separate device, since it PPE DMA access is\n+\t * not coherent.\n+\t */\n+\tppe->base = base;\n+\tppe->dev = dev;\n+\tppe->version = version;\n+\n+\tfoe = dmam_alloc_coherent(ppe->dev, MTK_PPE_ENTRIES * sizeof(*foe),\n+\t\t\t\t  &ppe->foe_phys, GFP_KERNEL);\n+\tif (!foe)\n+\t\treturn -ENOMEM;\n+\n+\tppe->foe_table = foe;\n+\n+\tmtk_ppe_debugfs_init(ppe);\n+\n+\treturn 0;\n+}\n+\n+static void mtk_ppe_init_foe_table(struct mtk_ppe *ppe)\n+{\n+\tstatic const u8 skip[] = { 12, 25, 38, 51, 76, 89, 102 };\n+\tint i, k;\n+\n+\tmemset(ppe->foe_table, 0, MTK_PPE_ENTRIES * sizeof(ppe->foe_table));\n+\n+\tif (!IS_ENABLED(CONFIG_SOC_MT7621))\n+\t\treturn;\n+\n+\t/* skip all entries that cross the 1024 byte boundary */\n+\tfor (i = 0; i < MTK_PPE_ENTRIES; i += 128)\n+\t\tfor (k = 0; k < ARRAY_SIZE(skip); k++)\n+\t\t\tppe->foe_table[i + skip[k]].ib1 |= MTK_FOE_IB1_STATIC;\n+}\n+\n+int mtk_ppe_start(struct mtk_ppe *ppe)\n+{\n+\tu32 val;\n+\n+\tmtk_ppe_init_foe_table(ppe);\n+\tppe_w32(ppe, MTK_PPE_TB_BASE, ppe->foe_phys);\n+\n+\tval = MTK_PPE_TB_CFG_ENTRY_80B |\n+\t      MTK_PPE_TB_CFG_AGE_NON_L4 |\n+\t      MTK_PPE_TB_CFG_AGE_UNBIND |\n+\t      MTK_PPE_TB_CFG_AGE_TCP |\n+\t      MTK_PPE_TB_CFG_AGE_UDP |\n+\t      MTK_PPE_TB_CFG_AGE_TCP_FIN |\n+\t      FIELD_PREP(MTK_PPE_TB_CFG_SEARCH_MISS,\n+\t\t\t MTK_PPE_SEARCH_MISS_ACTION_FORWARD_BUILD) |\n+\t      FIELD_PREP(MTK_PPE_TB_CFG_KEEPALIVE,\n+\t\t\t MTK_PPE_KEEPALIVE_DISABLE) |\n+\t      FIELD_PREP(MTK_PPE_TB_CFG_HASH_MODE, 1) |\n+\t      FIELD_PREP(MTK_PPE_TB_CFG_SCAN_MODE,\n+\t\t\t MTK_PPE_SCAN_MODE_KEEPALIVE_AGE) |\n+\t      FIELD_PREP(MTK_PPE_TB_CFG_ENTRY_NUM,\n+\t\t\t MTK_PPE_ENTRIES_SHIFT);\n+\tppe_w32(ppe, MTK_PPE_TB_CFG, val);\n+\n+\tppe_w32(ppe, MTK_PPE_IP_PROTO_CHK,\n+\t\tMTK_PPE_IP_PROTO_CHK_IPV4 | MTK_PPE_IP_PROTO_CHK_IPV6);\n+\n+\tmtk_ppe_cache_enable(ppe, true);\n+\n+\tval = MTK_PPE_FLOW_CFG_IP4_TCP_FRAG |\n+\t      MTK_PPE_FLOW_CFG_IP4_UDP_FRAG |\n+\t      MTK_PPE_FLOW_CFG_IP6_3T_ROUTE |\n+\t      MTK_PPE_FLOW_CFG_IP6_5T_ROUTE |\n+\t      MTK_PPE_FLOW_CFG_IP6_6RD |\n+\t      MTK_PPE_FLOW_CFG_IP4_NAT |\n+\t      MTK_PPE_FLOW_CFG_IP4_NAPT |\n+\t      MTK_PPE_FLOW_CFG_IP4_DSLITE |\n+\t      MTK_PPE_FLOW_CFG_L2_BRIDGE |\n+\t      MTK_PPE_FLOW_CFG_IP4_NAT_FRAG;\n+\tppe_w32(ppe, MTK_PPE_FLOW_CFG, val);\n+\n+\tval = FIELD_PREP(MTK_PPE_UNBIND_AGE_MIN_PACKETS, 1000) |\n+\t      FIELD_PREP(MTK_PPE_UNBIND_AGE_DELTA, 3);\n+\tppe_w32(ppe, MTK_PPE_UNBIND_AGE, val);\n+\n+\tval = FIELD_PREP(MTK_PPE_BIND_AGE0_DELTA_UDP, 12) |\n+\t      FIELD_PREP(MTK_PPE_BIND_AGE0_DELTA_NON_L4, 1);\n+\tppe_w32(ppe, MTK_PPE_BIND_AGE0, val);\n+\n+\tval = FIELD_PREP(MTK_PPE_BIND_AGE1_DELTA_TCP_FIN, 1) |\n+\t      FIELD_PREP(MTK_PPE_BIND_AGE1_DELTA_TCP, 7);\n+\tppe_w32(ppe, MTK_PPE_BIND_AGE1, val);\n+\n+\tval = MTK_PPE_BIND_LIMIT0_QUARTER | MTK_PPE_BIND_LIMIT0_HALF;\n+\tppe_w32(ppe, MTK_PPE_BIND_LIMIT0, val);\n+\n+\tval = MTK_PPE_BIND_LIMIT1_FULL |\n+\t      FIELD_PREP(MTK_PPE_BIND_LIMIT1_NON_L4, 1);\n+\tppe_w32(ppe, MTK_PPE_BIND_LIMIT1, val);\n+\n+\tval = FIELD_PREP(MTK_PPE_BIND_RATE_BIND, 30) |\n+\t      FIELD_PREP(MTK_PPE_BIND_RATE_PREBIND, 1);\n+\tppe_w32(ppe, MTK_PPE_BIND_RATE, val);\n+\n+\t/* enable PPE */\n+\tval = MTK_PPE_GLO_CFG_EN |\n+\t      MTK_PPE_GLO_CFG_IP4_L4_CS_DROP |\n+\t      MTK_PPE_GLO_CFG_IP4_CS_DROP |\n+\t      MTK_PPE_GLO_CFG_FLOW_DROP_UPDATE;\n+\tppe_w32(ppe, MTK_PPE_GLO_CFG, val);\n+\n+\tppe_w32(ppe, MTK_PPE_DEFAULT_CPU_PORT, 0);\n+\n+\treturn 0;\n+}\n+\n+int mtk_ppe_stop(struct mtk_ppe *ppe)\n+{\n+\tu32 val;\n+\tint i;\n+\n+\tfor (i = 0; i < MTK_PPE_ENTRIES; i++)\n+\t\tppe->foe_table[i].ib1 = FIELD_PREP(MTK_FOE_IB1_STATE,\n+\t\t\t\t\t\t   MTK_FOE_STATE_INVALID);\n+\n+\tmtk_ppe_cache_enable(ppe, false);\n+\n+\t/* disable offload engine */\n+\tppe_clear(ppe, MTK_PPE_GLO_CFG, MTK_PPE_GLO_CFG_EN);\n+\tppe_w32(ppe, MTK_PPE_FLOW_CFG, 0);\n+\n+\t/* disable aging */\n+\tval = MTK_PPE_TB_CFG_AGE_NON_L4 |\n+\t      MTK_PPE_TB_CFG_AGE_UNBIND |\n+\t      MTK_PPE_TB_CFG_AGE_TCP |\n+\t      MTK_PPE_TB_CFG_AGE_UDP |\n+\t      MTK_PPE_TB_CFG_AGE_TCP_FIN;\n+\tppe_clear(ppe, MTK_PPE_TB_CFG, val);\n+\n+\treturn mtk_ppe_wait_busy(ppe);\n+}\n--- /dev/null\n+++ b/drivers/net/ethernet/mediatek/mtk_ppe.h\n@@ -0,0 +1,287 @@\n+// SPDX-License-Identifier: GPL-2.0-only\n+/* Copyright (C) 2020 Felix Fietkau <nbd@nbd.name> */\n+\n+#ifndef __MTK_PPE_H\n+#define __MTK_PPE_H\n+\n+#include <linux/kernel.h>\n+#include <linux/bitfield.h>\n+\n+#define MTK_ETH_PPE_BASE\t\t0xc00\n+\n+#define MTK_PPE_ENTRIES_SHIFT\t\t3\n+#define MTK_PPE_ENTRIES\t\t\t(1024 << MTK_PPE_ENTRIES_SHIFT)\n+#define MTK_PPE_HASH_MASK\t\t(MTK_PPE_ENTRIES - 1)\n+\n+#define MTK_FOE_IB1_UNBIND_TIMESTAMP\tGENMASK(7, 0)\n+#define MTK_FOE_IB1_UNBIND_PACKETS\tGENMASK(23, 8)\n+#define MTK_FOE_IB1_UNBIND_PREBIND\tBIT(24)\n+\n+#define MTK_FOE_IB1_BIND_TIMESTAMP\tGENMASK(14, 0)\n+#define MTK_FOE_IB1_BIND_KEEPALIVE\tBIT(15)\n+#define MTK_FOE_IB1_BIND_VLAN_LAYER\tGENMASK(18, 16)\n+#define MTK_FOE_IB1_BIND_PPPOE\t\tBIT(19)\n+#define MTK_FOE_IB1_BIND_VLAN_TAG\tBIT(20)\n+#define MTK_FOE_IB1_BIND_PKT_SAMPLE\tBIT(21)\n+#define MTK_FOE_IB1_BIND_CACHE\t\tBIT(22)\n+#define MTK_FOE_IB1_BIND_TUNNEL_DECAP\tBIT(23)\n+#define MTK_FOE_IB1_BIND_TTL\t\tBIT(24)\n+\n+#define MTK_FOE_IB1_PACKET_TYPE\t\tGENMASK(27, 25)\n+#define MTK_FOE_IB1_STATE\t\tGENMASK(29, 28)\n+#define MTK_FOE_IB1_UDP\t\t\tBIT(30)\n+#define MTK_FOE_IB1_STATIC\t\tBIT(31)\n+\n+enum {\n+\tMTK_PPE_PKT_TYPE_IPV4_HNAPT = 0,\n+\tMTK_PPE_PKT_TYPE_IPV4_ROUTE = 1,\n+\tMTK_PPE_PKT_TYPE_BRIDGE = 2,\n+\tMTK_PPE_PKT_TYPE_IPV4_DSLITE = 3,\n+\tMTK_PPE_PKT_TYPE_IPV6_ROUTE_3T = 4,\n+\tMTK_PPE_PKT_TYPE_IPV6_ROUTE_5T = 5,\n+\tMTK_PPE_PKT_TYPE_IPV6_6RD = 7,\n+};\n+\n+#define MTK_FOE_IB2_QID\t\t\tGENMASK(3, 0)\n+#define MTK_FOE_IB2_PSE_QOS\t\tBIT(4)\n+#define MTK_FOE_IB2_DEST_PORT\t\tGENMASK(7, 5)\n+#define MTK_FOE_IB2_MULTICAST\t\tBIT(8)\n+\n+#define MTK_FOE_IB2_WHNAT_QID2\t\tGENMASK(13, 12)\n+#define MTK_FOE_IB2_WHNAT_DEVIDX\tBIT(16)\n+#define MTK_FOE_IB2_WHNAT_NAT\t\tBIT(17)\n+\n+#define MTK_FOE_IB2_PORT_MG\t\tGENMASK(17, 12)\n+\n+#define MTK_FOE_IB2_PORT_AG\t\tGENMASK(23, 18)\n+\n+#define MTK_FOE_IB2_DSCP\t\tGENMASK(31, 24)\n+\n+#define MTK_FOE_VLAN2_WHNAT_BSS\t\tGEMMASK(5, 0)\n+#define MTK_FOE_VLAN2_WHNAT_WCID\tGENMASK(13, 6)\n+#define MTK_FOE_VLAN2_WHNAT_RING\tGENMASK(15, 14)\n+\n+enum {\n+\tMTK_FOE_STATE_INVALID,\n+\tMTK_FOE_STATE_UNBIND,\n+\tMTK_FOE_STATE_BIND,\n+\tMTK_FOE_STATE_FIN\n+};\n+\n+struct mtk_foe_mac_info {\n+\tu16 vlan1;\n+\tu16 etype;\n+\n+\tu32 dest_mac_hi;\n+\n+\tu16 vlan2;\n+\tu16 dest_mac_lo;\n+\n+\tu32 src_mac_hi;\n+\n+\tu16 pppoe_id;\n+\tu16 src_mac_lo;\n+};\n+\n+struct mtk_foe_bridge {\n+\tu32 dest_mac_hi;\n+\n+\tu16 src_mac_lo;\n+\tu16 dest_mac_lo;\n+\n+\tu32 src_mac_hi;\n+\n+\tu32 ib2;\n+\n+\tu32 _rsv[5];\n+\n+\tu32 udf_tsid;\n+\tstruct mtk_foe_mac_info l2;\n+};\n+\n+struct mtk_ipv4_tuple {\n+\tu32 src_ip;\n+\tu32 dest_ip;\n+\tunion {\n+\t\tstruct {\n+\t\t\tu16 dest_port;\n+\t\t\tu16 src_port;\n+\t\t};\n+\t\tstruct {\n+\t\t\tu8 protocol;\n+\t\t\tu8 _pad[3]; /* fill with 0xa5a5a5 */\n+\t\t};\n+\t\tu32 ports;\n+\t};\n+};\n+\n+struct mtk_foe_ipv4 {\n+\tstruct mtk_ipv4_tuple orig;\n+\n+\tu32 ib2;\n+\n+\tstruct mtk_ipv4_tuple new;\n+\n+\tu16 timestamp;\n+\tu16 _rsv0[3];\n+\n+\tu32 udf_tsid;\n+\n+\tstruct mtk_foe_mac_info l2;\n+};\n+\n+struct mtk_foe_ipv4_dslite {\n+\tstruct mtk_ipv4_tuple ip4;\n+\n+\tu32 tunnel_src_ip[4];\n+\tu32 tunnel_dest_ip[4];\n+\n+\tu8 flow_label[3];\n+\tu8 priority;\n+\n+\tu32 udf_tsid;\n+\n+\tu32 ib2;\n+\n+\tstruct mtk_foe_mac_info l2;\n+};\n+\n+struct mtk_foe_ipv6 {\n+\tu32 src_ip[4];\n+\tu32 dest_ip[4];\n+\n+\tunion {\n+\t\tstruct {\n+\t\t\tu8 protocol;\n+\t\t\tu8 _pad[3]; /* fill with 0xa5a5a5 */\n+\t\t}; /* 3-tuple */\n+\t\tstruct {\n+\t\t\tu16 dest_port;\n+\t\t\tu16 src_port;\n+\t\t}; /* 5-tuple */\n+\t\tu32 ports;\n+\t};\n+\n+\tu32 _rsv[3];\n+\n+\tu32 udf;\n+\n+\tu32 ib2;\n+\tstruct mtk_foe_mac_info l2;\n+};\n+\n+struct mtk_foe_ipv6_6rd {\n+\tu32 src_ip[4];\n+\tu32 dest_ip[4];\n+\tu16 dest_port;\n+\tu16 src_port;\n+\n+\tu32 tunnel_src_ip;\n+\tu32 tunnel_dest_ip;\n+\n+\tu16 hdr_csum;\n+\tu8 dscp;\n+\tu8 ttl;\n+\n+\tu8 flag;\n+\tu8 pad;\n+\tu8 per_flow_6rd_id;\n+\tu8 pad2;\n+\n+\tu32 ib2;\n+\tstruct mtk_foe_mac_info l2;\n+};\n+\n+struct mtk_foe_entry {\n+\tu32 ib1;\n+\n+\tunion {\n+\t\tstruct mtk_foe_bridge bridge;\n+\t\tstruct mtk_foe_ipv4 ipv4;\n+\t\tstruct mtk_foe_ipv4_dslite dslite;\n+\t\tstruct mtk_foe_ipv6 ipv6;\n+\t\tstruct mtk_foe_ipv6_6rd ipv6_6rd;\n+\t\tu32 data[19];\n+\t};\n+};\n+\n+enum {\n+\tMTK_PPE_CPU_REASON_TTL_EXCEEDED\t\t\t= 0x02,\n+\tMTK_PPE_CPU_REASON_OPTION_HEADER\t\t= 0x03,\n+\tMTK_PPE_CPU_REASON_NO_FLOW\t\t\t= 0x07,\n+\tMTK_PPE_CPU_REASON_IPV4_FRAG\t\t\t= 0x08,\n+\tMTK_PPE_CPU_REASON_IPV4_DSLITE_FRAG\t\t= 0x09,\n+\tMTK_PPE_CPU_REASON_IPV4_DSLITE_NO_TCP_UDP\t= 0x0a,\n+\tMTK_PPE_CPU_REASON_IPV6_6RD_NO_TCP_UDP\t\t= 0x0b,\n+\tMTK_PPE_CPU_REASON_TCP_FIN_SYN_RST\t\t= 0x0c,\n+\tMTK_PPE_CPU_REASON_UN_HIT\t\t\t= 0x0d,\n+\tMTK_PPE_CPU_REASON_HIT_UNBIND\t\t\t= 0x0e,\n+\tMTK_PPE_CPU_REASON_HIT_UNBIND_RATE_REACHED\t= 0x0f,\n+\tMTK_PPE_CPU_REASON_HIT_BIND_TCP_FIN\t\t= 0x10,\n+\tMTK_PPE_CPU_REASON_HIT_TTL_1\t\t\t= 0x11,\n+\tMTK_PPE_CPU_REASON_HIT_BIND_VLAN_VIOLATION\t= 0x12,\n+\tMTK_PPE_CPU_REASON_KEEPALIVE_UC_OLD_HDR\t\t= 0x13,\n+\tMTK_PPE_CPU_REASON_KEEPALIVE_MC_NEW_HDR\t\t= 0x14,\n+\tMTK_PPE_CPU_REASON_KEEPALIVE_DUP_OLD_HDR\t= 0x15,\n+\tMTK_PPE_CPU_REASON_HIT_BIND_FORCE_CPU\t\t= 0x16,\n+\tMTK_PPE_CPU_REASON_TUNNEL_OPTION_HEADER\t\t= 0x17,\n+\tMTK_PPE_CPU_REASON_MULTICAST_TO_CPU\t\t= 0x18,\n+\tMTK_PPE_CPU_REASON_MULTICAST_TO_GMAC1_CPU\t= 0x19,\n+\tMTK_PPE_CPU_REASON_HIT_PRE_BIND\t\t\t= 0x1a,\n+\tMTK_PPE_CPU_REASON_PACKET_SAMPLING\t\t= 0x1b,\n+\tMTK_PPE_CPU_REASON_EXCEED_MTU\t\t\t= 0x1c,\n+\tMTK_PPE_CPU_REASON_PPE_BYPASS\t\t\t= 0x1e,\n+\tMTK_PPE_CPU_REASON_INVALID\t\t\t= 0x1f,\n+};\n+\n+struct mtk_ppe {\n+\tstruct device *dev;\n+\tvoid __iomem *base;\n+\tint version;\n+\n+\tstruct mtk_foe_entry *foe_table;\n+\tdma_addr_t foe_phys;\n+\n+\tvoid *acct_table;\n+};\n+\n+int mtk_ppe_init(struct mtk_ppe *ppe, struct device *dev, void __iomem *base,\n+\t\t int version);\n+int mtk_ppe_start(struct mtk_ppe *ppe);\n+int mtk_ppe_stop(struct mtk_ppe *ppe);\n+\n+static inline void\n+mtk_foe_entry_clear(struct mtk_ppe *ppe, u16 hash)\n+{\n+\tppe->foe_table[hash].ib1 = 0;\n+\tdma_wmb();\n+}\n+\n+static inline int\n+mtk_foe_entry_timestamp(struct mtk_ppe *ppe, u16 hash)\n+{\n+\tu32 ib1 = READ_ONCE(ppe->foe_table[hash].ib1);\n+\n+\tif (FIELD_GET(MTK_FOE_IB1_STATE, ib1) != MTK_FOE_STATE_BIND)\n+\t\treturn -1;\n+\n+\treturn FIELD_GET(MTK_FOE_IB1_BIND_TIMESTAMP, ib1);\n+}\n+\n+int mtk_foe_entry_prepare(struct mtk_foe_entry *entry, int type, int l4proto,\n+\t\t\t  u8 pse_port, u8 *src_mac, u8 *dest_mac);\n+int mtk_foe_entry_set_pse_port(struct mtk_foe_entry *entry, u8 port);\n+int mtk_foe_entry_set_ipv4_tuple(struct mtk_foe_entry *entry, bool orig,\n+\t\t\t\t __be32 src_addr, __be16 src_port,\n+\t\t\t\t __be32 dest_addr, __be16 dest_port);\n+int mtk_foe_entry_set_ipv6_tuple(struct mtk_foe_entry *entry,\n+\t\t\t\t __be32 *src_addr, __be16 src_port,\n+\t\t\t\t __be32 *dest_addr, __be16 dest_port);\n+int mtk_foe_entry_set_dsa(struct mtk_foe_entry *entry, int port);\n+int mtk_foe_entry_set_vlan(struct mtk_foe_entry *entry, int vid);\n+int mtk_foe_entry_set_pppoe(struct mtk_foe_entry *entry, int sid);\n+int mtk_foe_entry_commit(struct mtk_ppe *ppe, struct mtk_foe_entry *entry,\n+\t\t\t u16 timestamp);\n+int mtk_ppe_debugfs_init(struct mtk_ppe *ppe);\n+\n+#endif\n--- /dev/null\n+++ b/drivers/net/ethernet/mediatek/mtk_ppe_debugfs.c\n@@ -0,0 +1,217 @@\n+// SPDX-License-Identifier: GPL-2.0-only\n+/* Copyright (C) 2020 Felix Fietkau <nbd@nbd.name> */\n+\n+#include <linux/kernel.h>\n+#include <linux/debugfs.h>\n+#include \"mtk_eth_soc.h\"\n+\n+struct mtk_flow_addr_info\n+{\n+\tvoid *src, *dest;\n+\tu16 *src_port, *dest_port;\n+\tbool ipv6;\n+};\n+\n+static const char *mtk_foe_entry_state_str(int state)\n+{\n+\tstatic const char * const state_str[] = {\n+\t\t[MTK_FOE_STATE_INVALID] = \"INV\",\n+\t\t[MTK_FOE_STATE_UNBIND] = \"UNB\",\n+\t\t[MTK_FOE_STATE_BIND] = \"BND\",\n+\t\t[MTK_FOE_STATE_FIN] = \"FIN\",\n+\t};\n+\n+\tif (state >= ARRAY_SIZE(state_str) || !state_str[state])\n+\t\treturn \"UNK\";\n+\n+\treturn state_str[state];\n+}\n+\n+static const char *mtk_foe_pkt_type_str(int type)\n+{\n+\tstatic const char * const type_str[] = {\n+\t\t[MTK_PPE_PKT_TYPE_IPV4_HNAPT] = \"IPv4 5T\",\n+\t\t[MTK_PPE_PKT_TYPE_IPV4_ROUTE] = \"IPv4 3T\",\n+\t\t[MTK_PPE_PKT_TYPE_BRIDGE] = \"L2\",\n+\t\t[MTK_PPE_PKT_TYPE_IPV4_DSLITE] = \"DS-LITE\",\n+\t\t[MTK_PPE_PKT_TYPE_IPV6_ROUTE_3T] = \"IPv6 3T\",\n+\t\t[MTK_PPE_PKT_TYPE_IPV6_ROUTE_5T] = \"IPv6 5T\",\n+\t\t[MTK_PPE_PKT_TYPE_IPV6_6RD] = \"6RD\",\n+\t};\n+\n+\tif (type >= ARRAY_SIZE(type_str) || !type_str[type])\n+\t\treturn \"UNKNOWN\";\n+\n+\treturn type_str[type];\n+}\n+\n+static void\n+mtk_print_addr(struct seq_file *m, u32 *addr, bool ipv6)\n+{\n+\tu32 n_addr[4];\n+\tint i;\n+\n+\tif (!ipv6) {\n+\t\tseq_printf(m, \"%pI4h\", addr);\n+\t\treturn;\n+\t}\n+\n+\tfor (i = 0; i < ARRAY_SIZE(n_addr); i++)\n+\t\tn_addr[i] = htonl(addr[i]);\n+\tseq_printf(m, \"%pI6\", n_addr);\n+}\n+\n+static void\n+mtk_print_addr_info(struct seq_file *m, struct mtk_flow_addr_info *ai)\n+{\n+\tmtk_print_addr(m, ai->src, ai->ipv6);\n+\tif (ai->src_port)\n+\t\tseq_printf(m, \":%d\", *ai->src_port);\n+\tseq_printf(m, \"->\");\n+\tmtk_print_addr(m, ai->dest, ai->ipv6);\n+\tif (ai->dest_port)\n+\t\tseq_printf(m, \":%d\", *ai->dest_port);\n+}\n+\n+static int\n+mtk_ppe_debugfs_foe_show(struct seq_file *m, void *private, bool bind)\n+{\n+\tstruct mtk_ppe *ppe = m->private;\n+\tint i, count;\n+\n+\tfor (i = 0, count = 0; i < MTK_PPE_ENTRIES; i++) {\n+\t\tstruct mtk_foe_entry *entry = &ppe->foe_table[i];\n+\t\tstruct mtk_foe_mac_info *l2;\n+\t\tstruct mtk_flow_addr_info ai = {};\n+\t\tunsigned char h_source[ETH_ALEN];\n+\t\tunsigned char h_dest[ETH_ALEN];\n+\t\tint type, state;\n+\t\tu32 ib2;\n+\n+\n+\t\tstate = FIELD_GET(MTK_FOE_IB1_STATE, entry->ib1);\n+\t\tif (!state)\n+\t\t\tcontinue;\n+\n+\t\tif (bind && state != MTK_FOE_STATE_BIND)\n+\t\t\tcontinue;\n+\n+\t\ttype = FIELD_GET(MTK_FOE_IB1_PACKET_TYPE, entry->ib1);\n+\t\tseq_printf(m, \"%05x %s %7s\", i,\n+\t\t\t   mtk_foe_entry_state_str(state),\n+\t\t\t   mtk_foe_pkt_type_str(type));\n+\n+\t\tswitch (type) {\n+\t\tcase MTK_PPE_PKT_TYPE_IPV4_HNAPT:\n+\t\tcase MTK_PPE_PKT_TYPE_IPV4_DSLITE:\n+\t\t\tai.src_port = &entry->ipv4.orig.src_port;\n+\t\t\tai.dest_port = &entry->ipv4.orig.dest_port;\n+\t\t\tfallthrough;\n+\t\tcase MTK_PPE_PKT_TYPE_IPV4_ROUTE:\n+\t\t\tai.src = &entry->ipv4.orig.src_ip;\n+\t\t\tai.dest = &entry->ipv4.orig.dest_ip;\n+\t\t\tbreak;\n+\t\tcase MTK_PPE_PKT_TYPE_IPV6_ROUTE_5T:\n+\t\t\tai.src_port = &entry->ipv6.src_port;\n+\t\t\tai.dest_port = &entry->ipv6.dest_port;\n+\t\t\tfallthrough;\n+\t\tcase MTK_PPE_PKT_TYPE_IPV6_ROUTE_3T:\n+\t\tcase MTK_PPE_PKT_TYPE_IPV6_6RD:\n+\t\t\tai.src = &entry->ipv6.src_ip;\n+\t\t\tai.dest = &entry->ipv6.dest_ip;\n+\t\t\tai.ipv6 = true;\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\tseq_printf(m, \" orig=\");\n+\t\tmtk_print_addr_info(m, &ai);\n+\n+\t\tswitch (type) {\n+\t\tcase MTK_PPE_PKT_TYPE_IPV4_HNAPT:\n+\t\tcase MTK_PPE_PKT_TYPE_IPV4_DSLITE:\n+\t\t\tai.src_port = &entry->ipv4.new.src_port;\n+\t\t\tai.dest_port = &entry->ipv4.new.dest_port;\n+\t\t\tfallthrough;\n+\t\tcase MTK_PPE_PKT_TYPE_IPV4_ROUTE:\n+\t\t\tai.src = &entry->ipv4.new.src_ip;\n+\t\t\tai.dest = &entry->ipv4.new.dest_ip;\n+\t\t\tseq_printf(m, \" new=\");\n+\t\t\tmtk_print_addr_info(m, &ai);\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\tif (type >= MTK_PPE_PKT_TYPE_IPV4_DSLITE) {\n+\t\t\tl2 = &entry->ipv6.l2;\n+\t\t\tib2 = entry->ipv6.ib2;\n+\t\t} else {\n+\t\t\tl2 = &entry->ipv4.l2;\n+\t\t\tib2 = entry->ipv4.ib2;\n+\t\t}\n+\n+\t\t*((__be32 *)h_source) = htonl(l2->src_mac_hi);\n+\t\t*((__be16 *)&h_source[4]) = htons(l2->src_mac_lo);\n+\t\t*((__be32 *)h_dest) = htonl(l2->dest_mac_hi);\n+\t\t*((__be16 *)&h_dest[4]) = htons(l2->dest_mac_lo);\n+\n+\t\tseq_printf(m, \" eth=%pM->%pM etype=%04x\"\n+\t\t\t      \" vlan=%d,%d ib1=%08x ib2=%08x\\n\",\n+\t\t\t   h_source, h_dest, ntohs(l2->etype),\n+\t\t\t   l2->vlan1, l2->vlan2, entry->ib1, ib2);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int\n+mtk_ppe_debugfs_foe_show_all(struct seq_file *m, void *private)\n+{\n+\treturn mtk_ppe_debugfs_foe_show(m, private, false);\n+}\n+\n+static int\n+mtk_ppe_debugfs_foe_show_bind(struct seq_file *m, void *private)\n+{\n+\treturn mtk_ppe_debugfs_foe_show(m, private, true);\n+}\n+\n+static int\n+mtk_ppe_debugfs_foe_open_all(struct inode *inode, struct file *file)\n+{\n+\treturn single_open(file, mtk_ppe_debugfs_foe_show_all,\n+\t\t\t   inode->i_private);\n+}\n+\n+static int\n+mtk_ppe_debugfs_foe_open_bind(struct inode *inode, struct file *file)\n+{\n+\treturn single_open(file, mtk_ppe_debugfs_foe_show_bind,\n+\t\t\t   inode->i_private);\n+}\n+\n+int mtk_ppe_debugfs_init(struct mtk_ppe *ppe)\n+{\n+\tstatic const struct file_operations fops_all = {\n+\t\t.open = mtk_ppe_debugfs_foe_open_all,\n+\t\t.read = seq_read,\n+\t\t.llseek = seq_lseek,\n+\t\t.release = single_release,\n+\t};\n+\n+\tstatic const struct file_operations fops_bind = {\n+\t\t.open = mtk_ppe_debugfs_foe_open_bind,\n+\t\t.read = seq_read,\n+\t\t.llseek = seq_lseek,\n+\t\t.release = single_release,\n+\t};\n+\n+\tstruct dentry *root;\n+\n+\troot = debugfs_create_dir(\"mtk_ppe\", NULL);\n+\tif (!root)\n+\t\treturn -ENOMEM;\n+\n+\tdebugfs_create_file(\"entries\", S_IRUGO, root, ppe, &fops_all);\n+\tdebugfs_create_file(\"bind\", S_IRUGO, root, ppe, &fops_bind);\n+\n+\treturn 0;\n+}\n--- /dev/null\n+++ b/drivers/net/ethernet/mediatek/mtk_ppe_regs.h\n@@ -0,0 +1,144 @@\n+// SPDX-License-Identifier: GPL-2.0-only\n+/* Copyright (C) 2020 Felix Fietkau <nbd@nbd.name> */\n+\n+#ifndef __MTK_PPE_REGS_H\n+#define __MTK_PPE_REGS_H\n+\n+#define MTK_PPE_GLO_CFG\t\t\t\t0x200\n+#define MTK_PPE_GLO_CFG_EN\t\t\tBIT(0)\n+#define MTK_PPE_GLO_CFG_TSID_EN\t\t\tBIT(1)\n+#define MTK_PPE_GLO_CFG_IP4_L4_CS_DROP\t\tBIT(2)\n+#define MTK_PPE_GLO_CFG_IP4_CS_DROP\t\tBIT(3)\n+#define MTK_PPE_GLO_CFG_TTL0_DROP\t\tBIT(4)\n+#define MTK_PPE_GLO_CFG_PPE_BSWAP\t\tBIT(5)\n+#define MTK_PPE_GLO_CFG_PSE_HASH_OFS\t\tBIT(6)\n+#define MTK_PPE_GLO_CFG_MCAST_TB_EN\t\tBIT(7)\n+#define MTK_PPE_GLO_CFG_FLOW_DROP_KA\t\tBIT(8)\n+#define MTK_PPE_GLO_CFG_FLOW_DROP_UPDATE\tBIT(9)\n+#define MTK_PPE_GLO_CFG_UDP_LITE_EN\t\tBIT(10)\n+#define MTK_PPE_GLO_CFG_UDP_LEN_DROP\t\tBIT(11)\n+#define MTK_PPE_GLO_CFG_MCAST_ENTRIES\t\tGNEMASK(13, 12)\n+#define MTK_PPE_GLO_CFG_BUSY\t\t\tBIT(31)\n+\n+#define MTK_PPE_FLOW_CFG\t\t\t0x204\n+#define MTK_PPE_FLOW_CFG_IP4_TCP_FRAG\t\tBIT(6)\n+#define MTK_PPE_FLOW_CFG_IP4_UDP_FRAG\t\tBIT(7)\n+#define MTK_PPE_FLOW_CFG_IP6_3T_ROUTE\t\tBIT(8)\n+#define MTK_PPE_FLOW_CFG_IP6_5T_ROUTE\t\tBIT(9)\n+#define MTK_PPE_FLOW_CFG_IP6_6RD\t\tBIT(10)\n+#define MTK_PPE_FLOW_CFG_IP4_NAT\t\tBIT(12)\n+#define MTK_PPE_FLOW_CFG_IP4_NAPT\t\tBIT(13)\n+#define MTK_PPE_FLOW_CFG_IP4_DSLITE\t\tBIT(14)\n+#define MTK_PPE_FLOW_CFG_L2_BRIDGE\t\tBIT(15)\n+#define MTK_PPE_FLOW_CFG_IP_PROTO_BLACKLIST\tBIT(16)\n+#define MTK_PPE_FLOW_CFG_IP4_NAT_FRAG\t\tBIT(17)\n+#define MTK_PPE_FLOW_CFG_IP4_HASH_FLOW_LABEL\tBIT(18)\n+#define MTK_PPE_FLOW_CFG_IP4_HASH_GRE_KEY\tBIT(19)\n+#define MTK_PPE_FLOW_CFG_IP6_HASH_GRE_KEY\tBIT(20)\n+\n+#define MTK_PPE_IP_PROTO_CHK\t\t\t0x208\n+#define MTK_PPE_IP_PROTO_CHK_IPV4\t\tGENMASK(15, 0)\n+#define MTK_PPE_IP_PROTO_CHK_IPV6\t\tGENMASK(31, 16)\n+\n+#define MTK_PPE_TB_CFG\t\t\t\t0x21c\n+#define MTK_PPE_TB_CFG_ENTRY_NUM\t\tGENMASK(2, 0)\n+#define MTK_PPE_TB_CFG_ENTRY_80B\t\tBIT(3)\n+#define MTK_PPE_TB_CFG_SEARCH_MISS\t\tGENMASK(5, 4)\n+#define MTK_PPE_TB_CFG_AGE_PREBIND\t\tBIT(6)\n+#define MTK_PPE_TB_CFG_AGE_NON_L4\t\tBIT(7)\n+#define MTK_PPE_TB_CFG_AGE_UNBIND\t\tBIT(8)\n+#define MTK_PPE_TB_CFG_AGE_TCP\t\t\tBIT(9)\n+#define MTK_PPE_TB_CFG_AGE_UDP\t\t\tBIT(10)\n+#define MTK_PPE_TB_CFG_AGE_TCP_FIN\t\tBIT(11)\n+#define MTK_PPE_TB_CFG_KEEPALIVE\t\tGENMASK(13, 12)\n+#define MTK_PPE_TB_CFG_HASH_MODE\t\tGENMASK(15, 14)\n+#define MTK_PPE_TB_CFG_SCAN_MODE\t\tGENMASK(17, 16)\n+#define MTK_PPE_TB_CFG_HASH_DEBUG\t\tGENMASK(19, 18)\n+\n+enum {\n+\tMTK_PPE_SCAN_MODE_DISABLED,\n+\tMTK_PPE_SCAN_MODE_CHECK_AGE,\n+\tMTK_PPE_SCAN_MODE_KEEPALIVE_AGE,\n+};\n+\n+enum {\n+\tMTK_PPE_KEEPALIVE_DISABLE,\n+\tMTK_PPE_KEEPALIVE_UNICAST_CPU,\n+\tMTK_PPE_KEEPALIVE_DUP_CPU = 3,\n+};\n+\n+enum {\n+\tMTK_PPE_SEARCH_MISS_ACTION_DROP,\n+\tMTK_PPE_SEARCH_MISS_ACTION_FORWARD = 2,\n+\tMTK_PPE_SEARCH_MISS_ACTION_FORWARD_BUILD = 3,\n+};\n+\n+#define MTK_PPE_TB_BASE\t\t\t\t0x220\n+\n+#define MTK_PPE_TB_USED\t\t\t\t0x224\n+#define MTK_PPE_TB_USED_NUM\t\t\tGENMASK(13, 0)\n+\n+#define MTK_PPE_BIND_RATE\t\t\t0x228\n+#define MTK_PPE_BIND_RATE_BIND\t\t\tGENMASK(15, 0)\n+#define MTK_PPE_BIND_RATE_PREBIND\t\tGENMASK(31, 16)\n+\n+#define MTK_PPE_BIND_LIMIT0\t\t\t0x22c\n+#define MTK_PPE_BIND_LIMIT0_QUARTER\t\tGENMASK(13, 0)\n+#define MTK_PPE_BIND_LIMIT0_HALF\t\tGENMASK(29, 16)\n+\n+#define MTK_PPE_BIND_LIMIT1\t\t\t0x230\n+#define MTK_PPE_BIND_LIMIT1_FULL\t\tGENMASK(13, 0)\n+#define MTK_PPE_BIND_LIMIT1_NON_L4\t\tGENMASK(23, 16)\n+\n+#define MTK_PPE_KEEPALIVE\t\t\t0x234\n+#define MTK_PPE_KEEPALIVE_TIME\t\t\tGENMASK(15, 0)\n+#define MTK_PPE_KEEPALIVE_TIME_TCP\t\tGENMASK(23, 16)\n+#define MTK_PPE_KEEPALIVE_TIME_UDP\t\tGENMASK(31, 24)\n+\n+#define MTK_PPE_UNBIND_AGE\t\t\t0x238\n+#define MTK_PPE_UNBIND_AGE_MIN_PACKETS\t\tGENMASK(31, 16)\n+#define MTK_PPE_UNBIND_AGE_DELTA\t\tGENMASK(7, 0)\n+\n+#define MTK_PPE_BIND_AGE0\t\t\t0x23c\n+#define MTK_PPE_BIND_AGE0_DELTA_NON_L4\t\tGENMASK(30, 16)\n+#define MTK_PPE_BIND_AGE0_DELTA_UDP\t\tGENMASK(14, 0)\n+\n+#define MTK_PPE_BIND_AGE1\t\t\t0x240\n+#define MTK_PPE_BIND_AGE1_DELTA_TCP_FIN\t\tGENMASK(30, 16)\n+#define MTK_PPE_BIND_AGE1_DELTA_TCP\t\tGENMASK(14, 0)\n+\n+#define MTK_PPE_HASH_SEED\t\t\t0x244\n+\n+#define MTK_PPE_DEFAULT_CPU_PORT\t\t0x248\n+#define MTK_PPE_DEFAULT_CPU_PORT_MASK(_n)\t(GENMASK(2, 0) << ((_n) * 4))\n+\n+#define MTK_PPE_MTU_DROP\t\t\t0x308\n+\n+#define MTK_PPE_VLAN_MTU0\t\t\t0x30c\n+#define MTK_PPE_VLAN_MTU0_NONE\t\t\tGENMASK(13, 0)\n+#define MTK_PPE_VLAN_MTU0_1TAG\t\t\tGENMASK(29, 16)\n+\n+#define MTK_PPE_VLAN_MTU1\t\t\t0x310\n+#define MTK_PPE_VLAN_MTU1_2TAG\t\t\tGENMASK(13, 0)\n+#define MTK_PPE_VLAN_MTU1_3TAG\t\t\tGENMASK(29, 16)\n+\n+#define MTK_PPE_VPM_TPID\t\t\t0x318\n+\n+#define MTK_PPE_CACHE_CTL\t\t\t0x320\n+#define MTK_PPE_CACHE_CTL_EN\t\t\tBIT(0)\n+#define MTK_PPE_CACHE_CTL_LOCK_CLR\t\tBIT(4)\n+#define MTK_PPE_CACHE_CTL_REQ\t\t\tBIT(8)\n+#define MTK_PPE_CACHE_CTL_CLEAR\t\t\tBIT(9)\n+#define MTK_PPE_CACHE_CTL_CMD\t\t\tGENMASK(13, 12)\n+\n+#define MTK_PPE_MIB_CFG\t\t\t\t0x334\n+#define MTK_PPE_MIB_CFG_EN\t\t\tBIT(0)\n+#define MTK_PPE_MIB_CFG_RD_CLR\t\t\tBIT(1)\n+\n+#define MTK_PPE_MIB_TB_BASE\t\t\t0x338\n+\n+#define MTK_PPE_MIB_CACHE_CTL\t\t\t0x350\n+#define MTK_PPE_MIB_CACHE_CTL_EN\t\tBIT(0)\n+#define MTK_PPE_MIB_CACHE_CTL_FLUSH\t\tBIT(2)\n+\n+#endif\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/610-v5.13-33-net-ethernet-mtk_eth_soc-add-flow-offloading-support.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nDate: Wed, 24 Mar 2021 02:30:54 +0100\nSubject: [PATCH] net: ethernet: mtk_eth_soc: add flow offloading support\n\nThis adds support for offloading IPv4 routed flows, including SNAT/DNAT,\none VLAN, PPPoE and DSA.\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\nSigned-off-by: Pablo Neira Ayuso <pablo@netfilter.org>\n---\n create mode 100644 drivers/net/ethernet/mediatek/mtk_ppe_offload.c\n\n--- a/drivers/net/ethernet/mediatek/Makefile\n+++ b/drivers/net/ethernet/mediatek/Makefile\n@@ -4,5 +4,5 @@\n #\n \n obj-$(CONFIG_NET_MEDIATEK_SOC) += mtk_eth.o\n-mtk_eth-y := mtk_eth_soc.o mtk_sgmii.o mtk_eth_path.o mtk_ppe.o mtk_ppe_debugfs.o\n+mtk_eth-y := mtk_eth_soc.o mtk_sgmii.o mtk_eth_path.o mtk_ppe.o mtk_ppe_debugfs.o mtk_ppe_offload.o\n obj-$(CONFIG_NET_MEDIATEK_STAR_EMAC) += mtk_star_emac.o\n--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c\n+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c\n@@ -2834,6 +2834,7 @@ static const struct net_device_ops mtk_n\n #ifdef CONFIG_NET_POLL_CONTROLLER\n \t.ndo_poll_controller\t= mtk_poll_controller,\n #endif\n+\t.ndo_setup_tc\t\t= mtk_eth_setup_tc,\n };\n \n static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np)\n@@ -3092,6 +3093,10 @@ static int mtk_probe(struct platform_dev\n \t\t\t\t   eth->base + MTK_ETH_PPE_BASE, 2);\n \t\tif (err)\n \t\t\tgoto err_free_dev;\n+\n+\t\terr = mtk_eth_offload_init(eth);\n+\t\tif (err)\n+\t\t\tgoto err_free_dev;\n \t}\n \n \tfor (i = 0; i < MTK_MAX_DEVS; i++) {\n--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h\n+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h\n@@ -15,6 +15,7 @@\n #include <linux/u64_stats_sync.h>\n #include <linux/refcount.h>\n #include <linux/phylink.h>\n+#include <linux/rhashtable.h>\n #include \"mtk_ppe.h\"\n \n #define MTK_QDMA_PAGE_SIZE\t2048\n@@ -40,7 +41,8 @@\n \t\t\t\t NETIF_F_HW_VLAN_CTAG_RX | \\\n \t\t\t\t NETIF_F_SG | NETIF_F_TSO | \\\n \t\t\t\t NETIF_F_TSO6 | \\\n-\t\t\t\t NETIF_F_IPV6_CSUM)\n+\t\t\t\t NETIF_F_IPV6_CSUM |\\\n+\t\t\t\t NETIF_F_HW_TC)\n #define MTK_HW_FEATURES_MT7628\t(NETIF_F_SG | NETIF_F_RXCSUM)\n #define NEXT_DESP_IDX(X, Y)\t(((X) + 1) & ((Y) - 1))\n \n@@ -929,6 +931,7 @@ struct mtk_eth {\n \tint\t\t\t\tip_align;\n \n \tstruct mtk_ppe\t\t\tppe;\n+\tstruct rhashtable\t\tflow_table;\n };\n \n /* struct mtk_mac -\tthe structure that holds the info about the MACs of the\n@@ -973,4 +976,9 @@ int mtk_gmac_sgmii_path_setup(struct mtk\n int mtk_gmac_gephy_path_setup(struct mtk_eth *eth, int mac_id);\n int mtk_gmac_rgmii_path_setup(struct mtk_eth *eth, int mac_id);\n \n+int mtk_eth_offload_init(struct mtk_eth *eth);\n+int mtk_eth_setup_tc(struct net_device *dev, enum tc_setup_type type,\n+\t\t     void *type_data);\n+\n+\n #endif /* MTK_ETH_H */\n--- /dev/null\n+++ b/drivers/net/ethernet/mediatek/mtk_ppe_offload.c\n@@ -0,0 +1,485 @@\n+// SPDX-License-Identifier: GPL-2.0-only\n+/*\n+ *  Copyright (C) 2020 Felix Fietkau <nbd@nbd.name>\n+ */\n+\n+#include <linux/if_ether.h>\n+#include <linux/rhashtable.h>\n+#include <linux/if_ether.h>\n+#include <linux/ip.h>\n+#include <net/flow_offload.h>\n+#include <net/pkt_cls.h>\n+#include <net/dsa.h>\n+#include \"mtk_eth_soc.h\"\n+\n+struct mtk_flow_data {\n+\tstruct ethhdr eth;\n+\n+\tunion {\n+\t\tstruct {\n+\t\t\t__be32 src_addr;\n+\t\t\t__be32 dst_addr;\n+\t\t} v4;\n+\t};\n+\n+\t__be16 src_port;\n+\t__be16 dst_port;\n+\n+\tstruct {\n+\t\tu16 id;\n+\t\t__be16 proto;\n+\t\tu8 num;\n+\t} vlan;\n+\tstruct {\n+\t\tu16 sid;\n+\t\tu8 num;\n+\t} pppoe;\n+};\n+\n+struct mtk_flow_entry {\n+\tstruct rhash_head node;\n+\tunsigned long cookie;\n+\tu16 hash;\n+};\n+\n+static const struct rhashtable_params mtk_flow_ht_params = {\n+\t.head_offset = offsetof(struct mtk_flow_entry, node),\n+\t.head_offset = offsetof(struct mtk_flow_entry, cookie),\n+\t.key_len = sizeof(unsigned long),\n+\t.automatic_shrinking = true,\n+};\n+\n+static u32\n+mtk_eth_timestamp(struct mtk_eth *eth)\n+{\n+\treturn mtk_r32(eth, 0x0010) & MTK_FOE_IB1_BIND_TIMESTAMP;\n+}\n+\n+static int\n+mtk_flow_set_ipv4_addr(struct mtk_foe_entry *foe, struct mtk_flow_data *data,\n+\t\t       bool egress)\n+{\n+\treturn mtk_foe_entry_set_ipv4_tuple(foe, egress,\n+\t\t\t\t\t    data->v4.src_addr, data->src_port,\n+\t\t\t\t\t    data->v4.dst_addr, data->dst_port);\n+}\n+\n+static void\n+mtk_flow_offload_mangle_eth(const struct flow_action_entry *act, void *eth)\n+{\n+\tvoid *dest = eth + act->mangle.offset;\n+\tconst void *src = &act->mangle.val;\n+\n+\tif (act->mangle.offset > 8)\n+\t\treturn;\n+\n+\tif (act->mangle.mask == 0xffff) {\n+\t\tsrc += 2;\n+\t\tdest += 2;\n+\t}\n+\n+\tmemcpy(dest, src, act->mangle.mask ? 2 : 4);\n+}\n+\n+\n+static int\n+mtk_flow_mangle_ports(const struct flow_action_entry *act,\n+\t\t      struct mtk_flow_data *data)\n+{\n+\tu32 val = ntohl(act->mangle.val);\n+\n+\tswitch (act->mangle.offset) {\n+\tcase 0:\n+\t\tif (act->mangle.mask == ~htonl(0xffff))\n+\t\t\tdata->dst_port = cpu_to_be16(val);\n+\t\telse\n+\t\t\tdata->src_port = cpu_to_be16(val >> 16);\n+\t\tbreak;\n+\tcase 2:\n+\t\tdata->dst_port = cpu_to_be16(val);\n+\t\tbreak;\n+\tdefault:\n+\t\treturn -EINVAL;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int\n+mtk_flow_mangle_ipv4(const struct flow_action_entry *act,\n+\t\t     struct mtk_flow_data *data)\n+{\n+\t__be32 *dest;\n+\n+\tswitch (act->mangle.offset) {\n+\tcase offsetof(struct iphdr, saddr):\n+\t\tdest = &data->v4.src_addr;\n+\t\tbreak;\n+\tcase offsetof(struct iphdr, daddr):\n+\t\tdest = &data->v4.dst_addr;\n+\t\tbreak;\n+\tdefault:\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tmemcpy(dest, &act->mangle.val, sizeof(u32));\n+\n+\treturn 0;\n+}\n+\n+static int\n+mtk_flow_get_dsa_port(struct net_device **dev)\n+{\n+#if IS_ENABLED(CONFIG_NET_DSA)\n+\tstruct dsa_port *dp;\n+\n+\tdp = dsa_port_from_netdev(*dev);\n+\tif (IS_ERR(dp))\n+\t\treturn -ENODEV;\n+\n+\tif (dp->cpu_dp->tag_ops->proto != DSA_TAG_PROTO_MTK)\n+\t\treturn -ENODEV;\n+\n+\t*dev = dp->cpu_dp->master;\n+\n+\treturn dp->index;\n+#else\n+\treturn -ENODEV;\n+#endif\n+}\n+\n+static int\n+mtk_flow_set_output_device(struct mtk_eth *eth, struct mtk_foe_entry *foe,\n+\t\t\t   struct net_device *dev)\n+{\n+\tint pse_port, dsa_port;\n+\n+\tdsa_port = mtk_flow_get_dsa_port(&dev);\n+\tif (dsa_port >= 0)\n+\t\tmtk_foe_entry_set_dsa(foe, dsa_port);\n+\n+\tif (dev == eth->netdev[0])\n+\t\tpse_port = 1;\n+\telse if (dev == eth->netdev[1])\n+\t\tpse_port = 2;\n+\telse\n+\t\treturn -EOPNOTSUPP;\n+\n+\tmtk_foe_entry_set_pse_port(foe, pse_port);\n+\n+\treturn 0;\n+}\n+\n+static int\n+mtk_flow_offload_replace(struct mtk_eth *eth, struct flow_cls_offload *f)\n+{\n+\tstruct flow_rule *rule = flow_cls_offload_flow_rule(f);\n+\tstruct flow_action_entry *act;\n+\tstruct mtk_flow_data data = {};\n+\tstruct mtk_foe_entry foe;\n+\tstruct net_device *odev = NULL;\n+\tstruct mtk_flow_entry *entry;\n+\tint offload_type = 0;\n+\tu16 addr_type = 0;\n+\tu32 timestamp;\n+\tu8 l4proto = 0;\n+\tint err = 0;\n+\tint hash;\n+\tint i;\n+\n+\tif (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_META)) {\n+\t\tstruct flow_match_meta match;\n+\n+\t\tflow_rule_match_meta(rule, &match);\n+\t} else {\n+\t\treturn -EOPNOTSUPP;\n+\t}\n+\n+\tif (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_CONTROL)) {\n+\t\tstruct flow_match_control match;\n+\n+\t\tflow_rule_match_control(rule, &match);\n+\t\taddr_type = match.key->addr_type;\n+\t} else {\n+\t\treturn -EOPNOTSUPP;\n+\t}\n+\n+\tif (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) {\n+\t\tstruct flow_match_basic match;\n+\n+\t\tflow_rule_match_basic(rule, &match);\n+\t\tl4proto = match.key->ip_proto;\n+\t} else {\n+\t\treturn -EOPNOTSUPP;\n+\t}\n+\n+\tflow_action_for_each(i, act, &rule->action) {\n+\t\tswitch (act->id) {\n+\t\tcase FLOW_ACTION_MANGLE:\n+\t\t\tif (act->mangle.htype == FLOW_ACT_MANGLE_HDR_TYPE_ETH)\n+\t\t\t\tmtk_flow_offload_mangle_eth(act, &data.eth);\n+\t\t\tbreak;\n+\t\tcase FLOW_ACTION_REDIRECT:\n+\t\t\todev = act->dev;\n+\t\t\tbreak;\n+\t\tcase FLOW_ACTION_CSUM:\n+\t\t\tbreak;\n+\t\tcase FLOW_ACTION_VLAN_PUSH:\n+\t\t\tif (data.vlan.num == 1 ||\n+\t\t\t    act->vlan.proto != htons(ETH_P_8021Q))\n+\t\t\t\treturn -EOPNOTSUPP;\n+\n+\t\t\tdata.vlan.id = act->vlan.vid;\n+\t\t\tdata.vlan.proto = act->vlan.proto;\n+\t\t\tdata.vlan.num++;\n+\t\t\tbreak;\n+\t\tcase FLOW_ACTION_PPPOE_PUSH:\n+\t\t\tif (data.pppoe.num == 1)\n+\t\t\t\treturn -EOPNOTSUPP;\n+\n+\t\t\tdata.pppoe.sid = act->pppoe.sid;\n+\t\t\tdata.pppoe.num++;\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\treturn -EOPNOTSUPP;\n+\t\t}\n+\t}\n+\n+\tswitch (addr_type) {\n+\tcase FLOW_DISSECTOR_KEY_IPV4_ADDRS:\n+\t\toffload_type = MTK_PPE_PKT_TYPE_IPV4_HNAPT;\n+\t\tbreak;\n+\tdefault:\n+\t\treturn -EOPNOTSUPP;\n+\t}\n+\n+\tif (!is_valid_ether_addr(data.eth.h_source) ||\n+\t    !is_valid_ether_addr(data.eth.h_dest))\n+\t\treturn -EINVAL;\n+\n+\terr = mtk_foe_entry_prepare(&foe, offload_type, l4proto, 0,\n+\t\t\t\t    data.eth.h_source,\n+\t\t\t\t    data.eth.h_dest);\n+\tif (err)\n+\t\treturn err;\n+\n+\tif (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_PORTS)) {\n+\t\tstruct flow_match_ports ports;\n+\n+\t\tflow_rule_match_ports(rule, &ports);\n+\t\tdata.src_port = ports.key->src;\n+\t\tdata.dst_port = ports.key->dst;\n+\t} else {\n+\t\treturn -EOPNOTSUPP;\n+\t}\n+\n+\tif (addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) {\n+\t\tstruct flow_match_ipv4_addrs addrs;\n+\n+\t\tflow_rule_match_ipv4_addrs(rule, &addrs);\n+\n+\t\tdata.v4.src_addr = addrs.key->src;\n+\t\tdata.v4.dst_addr = addrs.key->dst;\n+\n+\t\tmtk_flow_set_ipv4_addr(&foe, &data, false);\n+\t}\n+\n+\tflow_action_for_each(i, act, &rule->action) {\n+\t\tif (act->id != FLOW_ACTION_MANGLE)\n+\t\t\tcontinue;\n+\n+\t\tswitch (act->mangle.htype) {\n+\t\tcase FLOW_ACT_MANGLE_HDR_TYPE_TCP:\n+\t\tcase FLOW_ACT_MANGLE_HDR_TYPE_UDP:\n+\t\t\terr = mtk_flow_mangle_ports(act, &data);\n+\t\t\tbreak;\n+\t\tcase FLOW_ACT_MANGLE_HDR_TYPE_IP4:\n+\t\t\terr = mtk_flow_mangle_ipv4(act, &data);\n+\t\t\tbreak;\n+\t\tcase FLOW_ACT_MANGLE_HDR_TYPE_ETH:\n+\t\t\t/* handled earlier */\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\treturn -EOPNOTSUPP;\n+\t\t}\n+\n+\t\tif (err)\n+\t\t\treturn err;\n+\t}\n+\n+\tif (addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) {\n+\t\terr = mtk_flow_set_ipv4_addr(&foe, &data, true);\n+\t\tif (err)\n+\t\t\treturn err;\n+\t}\n+\n+\tif (data.vlan.num == 1) {\n+\t\tif (data.vlan.proto != htons(ETH_P_8021Q))\n+\t\t\treturn -EOPNOTSUPP;\n+\n+\t\tmtk_foe_entry_set_vlan(&foe, data.vlan.id);\n+\t}\n+\tif (data.pppoe.num == 1)\n+\t\tmtk_foe_entry_set_pppoe(&foe, data.pppoe.sid);\n+\n+\terr = mtk_flow_set_output_device(eth, &foe, odev);\n+\tif (err)\n+\t\treturn err;\n+\n+\tentry = kzalloc(sizeof(*entry), GFP_KERNEL);\n+\tif (!entry)\n+\t\treturn -ENOMEM;\n+\n+\tentry->cookie = f->cookie;\n+\ttimestamp = mtk_eth_timestamp(eth);\n+\thash = mtk_foe_entry_commit(&eth->ppe, &foe, timestamp);\n+\tif (hash < 0) {\n+\t\terr = hash;\n+\t\tgoto free;\n+\t}\n+\n+\tentry->hash = hash;\n+\terr = rhashtable_insert_fast(&eth->flow_table, &entry->node,\n+\t\t\t\t     mtk_flow_ht_params);\n+\tif (err < 0)\n+\t\tgoto clear_flow;\n+\n+\treturn 0;\n+clear_flow:\n+\tmtk_foe_entry_clear(&eth->ppe, hash);\n+free:\n+\tkfree(entry);\n+\treturn err;\n+}\n+\n+static int\n+mtk_flow_offload_destroy(struct mtk_eth *eth, struct flow_cls_offload *f)\n+{\n+\tstruct mtk_flow_entry *entry;\n+\n+\tentry = rhashtable_lookup(&eth->flow_table, &f->cookie,\n+\t\t\t\t  mtk_flow_ht_params);\n+\tif (!entry)\n+\t\treturn -ENOENT;\n+\n+\tmtk_foe_entry_clear(&eth->ppe, entry->hash);\n+\trhashtable_remove_fast(&eth->flow_table, &entry->node,\n+\t\t\t       mtk_flow_ht_params);\n+\tkfree(entry);\n+\n+\treturn 0;\n+}\n+\n+static int\n+mtk_flow_offload_stats(struct mtk_eth *eth, struct flow_cls_offload *f)\n+{\n+\tstruct mtk_flow_entry *entry;\n+\tint timestamp;\n+\tu32 idle;\n+\n+\tentry = rhashtable_lookup(&eth->flow_table, &f->cookie,\n+\t\t\t\t  mtk_flow_ht_params);\n+\tif (!entry)\n+\t\treturn -ENOENT;\n+\n+\ttimestamp = mtk_foe_entry_timestamp(&eth->ppe, entry->hash);\n+\tif (timestamp < 0)\n+\t\treturn -ETIMEDOUT;\n+\n+\tidle = mtk_eth_timestamp(eth) - timestamp;\n+\tf->stats.lastused = jiffies - idle * HZ;\n+\n+\treturn 0;\n+}\n+\n+static int\n+mtk_eth_setup_tc_block_cb(enum tc_setup_type type, void *type_data, void *cb_priv)\n+{\n+\tstruct flow_cls_offload *cls = type_data;\n+\tstruct net_device *dev = cb_priv;\n+\tstruct mtk_mac *mac = netdev_priv(dev);\n+\tstruct mtk_eth *eth = mac->hw;\n+\n+\tif (!tc_can_offload(dev))\n+\t\treturn -EOPNOTSUPP;\n+\n+\tif (type != TC_SETUP_CLSFLOWER)\n+\t\treturn -EOPNOTSUPP;\n+\n+\tswitch (cls->command) {\n+\tcase FLOW_CLS_REPLACE:\n+\t\treturn mtk_flow_offload_replace(eth, cls);\n+\tcase FLOW_CLS_DESTROY:\n+\t\treturn mtk_flow_offload_destroy(eth, cls);\n+\tcase FLOW_CLS_STATS:\n+\t\treturn mtk_flow_offload_stats(eth, cls);\n+\tdefault:\n+\t\treturn -EOPNOTSUPP;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int\n+mtk_eth_setup_tc_block(struct net_device *dev, struct flow_block_offload *f)\n+{\n+\tstruct mtk_mac *mac = netdev_priv(dev);\n+\tstruct mtk_eth *eth = mac->hw;\n+\tstatic LIST_HEAD(block_cb_list);\n+\tstruct flow_block_cb *block_cb;\n+\tflow_setup_cb_t *cb;\n+\n+\tif (!eth->ppe.foe_table)\n+\t\treturn -EOPNOTSUPP;\n+\n+\tif (f->binder_type != FLOW_BLOCK_BINDER_TYPE_CLSACT_INGRESS)\n+\t\treturn -EOPNOTSUPP;\n+\n+\tcb = mtk_eth_setup_tc_block_cb;\n+\tf->driver_block_list = &block_cb_list;\n+\n+\tswitch (f->command) {\n+\tcase FLOW_BLOCK_BIND:\n+\t\tblock_cb = flow_block_cb_lookup(f->block, cb, dev);\n+\t\tif (block_cb) {\n+\t\t\tflow_block_cb_incref(block_cb);\n+\t\t\treturn 0;\n+\t\t}\n+\t\tblock_cb = flow_block_cb_alloc(cb, dev, dev, NULL);\n+\t\tif (IS_ERR(block_cb))\n+\t\t\treturn PTR_ERR(block_cb);\n+\n+\t\tflow_block_cb_add(block_cb, f);\n+\t\tlist_add_tail(&block_cb->driver_list, &block_cb_list);\n+\t\treturn 0;\n+\tcase FLOW_BLOCK_UNBIND:\n+\t\tblock_cb = flow_block_cb_lookup(f->block, cb, dev);\n+\t\tif (!block_cb)\n+\t\t\treturn -ENOENT;\n+\n+\t\tif (flow_block_cb_decref(block_cb)) {\n+\t\t\tflow_block_cb_remove(block_cb, f);\n+\t\t\tlist_del(&block_cb->driver_list);\n+\t\t}\n+\t\treturn 0;\n+\tdefault:\n+\t\treturn -EOPNOTSUPP;\n+\t}\n+}\n+\n+int mtk_eth_setup_tc(struct net_device *dev, enum tc_setup_type type,\n+\t\t     void *type_data)\n+{\n+\tif (type == TC_SETUP_FT)\n+\t\treturn mtk_eth_setup_tc_block(dev, type_data);\n+\n+\treturn -EOPNOTSUPP;\n+}\n+\n+int mtk_eth_offload_init(struct mtk_eth *eth)\n+{\n+\tif (!eth->ppe.foe_table)\n+\t\treturn 0;\n+\n+\treturn rhashtable_init(&eth->flow_table, &mtk_flow_ht_params);\n+}\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/610-v5.13-34-docs-nf_flowtable-update-documentation-with-enhancem.patch",
    "content": "From: Pablo Neira Ayuso <pablo@netfilter.org>\nDate: Wed, 24 Mar 2021 02:30:55 +0100\nSubject: [PATCH] docs: nf_flowtable: update documentation with\n enhancements\n\nThis patch updates the flowtable documentation to describe recent\nenhancements:\n\n- Offload action is available after the first packets go through the\n  classic forwarding path.\n- IPv4 and IPv6 are supported. Only TCP and UDP layer 4 are supported at\n  this stage.\n- Tuple has been augmented to track VLAN id and PPPoE session id.\n- Bridge and IP forwarding integration, including bridge VLAN filtering\n  support.\n- Hardware offload support.\n- Describe the [OFFLOAD] and [HW_OFFLOAD] tags in the conntrack table\n  listing.\n- Replace 'flow offload' by 'flow add' in example rulesets (preferred\n  syntax).\n- Describe existing cache limitations.\n\nSigned-off-by: Pablo Neira Ayuso <pablo@netfilter.org>\n---\n\n--- a/Documentation/networking/nf_flowtable.rst\n+++ b/Documentation/networking/nf_flowtable.rst\n@@ -4,35 +4,38 @@\n Netfilter's flowtable infrastructure\n ====================================\n \n-This documentation describes the software flowtable infrastructure available in\n-Netfilter since Linux kernel 4.16.\n+This documentation describes the Netfilter flowtable infrastructure which allows\n+you to define a fastpath through the flowtable datapath. This infrastructure\n+also provides hardware offload support. The flowtable supports for the layer 3\n+IPv4 and IPv6 and the layer 4 TCP and UDP protocols.\n \n Overview\n --------\n \n-Initial packets follow the classic forwarding path, once the flow enters the\n-established state according to the conntrack semantics (ie. we have seen traffic\n-in both directions), then you can decide to offload the flow to the flowtable\n-from the forward chain via the 'flow offload' action available in nftables.\n-\n-Packets that find an entry in the flowtable (ie. flowtable hit) are sent to the\n-output netdevice via neigh_xmit(), hence, they bypass the classic forwarding\n-path (the visible effect is that you do not see these packets from any of the\n-netfilter hooks coming after the ingress). In case of flowtable miss, the packet\n-follows the classic forward path.\n-\n-The flowtable uses a resizable hashtable, lookups are based on the following\n-7-tuple selectors: source, destination, layer 3 and layer 4 protocols, source\n-and destination ports and the input interface (useful in case there are several\n-conntrack zones in place).\n-\n-Flowtables are populated via the 'flow offload' nftables action, so the user can\n-selectively specify what flows are placed into the flow table. Hence, packets\n-follow the classic forwarding path unless the user explicitly instruct packets\n-to use this new alternative forwarding path via nftables policy.\n+Once the first packet of the flow successfully goes through the IP forwarding\n+path, from the second packet on, you might decide to offload the flow to the\n+flowtable through your ruleset. The flowtable infrastructure provides a rule\n+action that allows you to specify when to add a flow to the flowtable.\n+\n+A packet that finds a matching entry in the flowtable (ie. flowtable hit) is\n+transmitted to the output netdevice via neigh_xmit(), hence, packets bypass the\n+classic IP forwarding path (the visible effect is that you do not see these\n+packets from any of the Netfilter hooks coming after ingress). In case that\n+there is no matching entry in the flowtable (ie. flowtable miss), the packet\n+follows the classic IP forwarding path.\n+\n+The flowtable uses a resizable hashtable. Lookups are based on the following\n+n-tuple selectors: layer 2 protocol encapsulation (VLAN and PPPoE), layer 3\n+source and destination, layer 4 source and destination ports and the input\n+interface (useful in case there are several conntrack zones in place).\n+\n+The 'flow add' action allows you to populate the flowtable, the user selectively\n+specifies what flows are placed into the flowtable. Hence, packets follow the\n+classic IP forwarding path unless the user explicitly instruct flows to use this\n+new alternative forwarding path via policy.\n \n-This is represented in Fig.1, which describes the classic forwarding path\n-including the Netfilter hooks and the flowtable fastpath bypass.\n+The flowtable datapath is represented in Fig.1, which describes the classic IP\n+forwarding path including the Netfilter hooks and the flowtable fastpath bypass.\n \n ::\n \n@@ -67,11 +70,13 @@ including the Netfilter hooks and the fl\n \t       Fig.1 Netfilter hooks and flowtable interactions\n \n The flowtable entry also stores the NAT configuration, so all packets are\n-mangled according to the NAT policy that matches the initial packets that went\n-through the classic forwarding path. The TTL is decremented before calling\n-neigh_xmit(). Fragmented traffic is passed up to follow the classic forwarding\n-path given that the transport selectors are missing, therefore flowtable lookup\n-is not possible.\n+mangled according to the NAT policy that is specified from the classic IP\n+forwarding path. The TTL is decremented before calling neigh_xmit(). Fragmented\n+traffic is passed up to follow the classic IP forwarding path given that the\n+transport header is missing, in this case, flowtable lookups are not possible.\n+TCP RST and FIN packets are also passed up to the classic IP forwarding path to\n+release the flow gracefully. Packets that exceed the MTU are also passed up to\n+the classic forwarding path to report packet-too-big ICMP errors to the sender.\n \n Example configuration\n ---------------------\n@@ -85,7 +90,7 @@ flowtable and add one rule to your forwa\n \t\t}\n \t\tchain y {\n \t\t\ttype filter hook forward priority 0; policy accept;\n-\t\t\tip protocol tcp flow offload @f\n+\t\t\tip protocol tcp flow add @f\n \t\t\tcounter packets 0 bytes 0\n \t\t}\n \t}\n@@ -103,6 +108,117 @@ flow is offloaded, you will observe that\n does not get updated for the packets that are being forwarded through the\n forwarding bypass.\n \n+You can identify offloaded flows through the [OFFLOAD] tag when listing your\n+connection tracking table.\n+\n+::\n+\t# conntrack -L\n+\ttcp      6 src=10.141.10.2 dst=192.168.10.2 sport=52728 dport=5201 src=192.168.10.2 dst=192.168.10.1 sport=5201 dport=52728 [OFFLOAD] mark=0 use=2\n+\n+\n+Layer 2 encapsulation\n+---------------------\n+\n+Since Linux kernel 5.13, the flowtable infrastructure discovers the real\n+netdevice behind VLAN and PPPoE netdevices. The flowtable software datapath\n+parses the VLAN and PPPoE layer 2 headers to extract the ethertype and the\n+VLAN ID / PPPoE session ID which are used for the flowtable lookups. The\n+flowtable datapath also deals with layer 2 decapsulation.\n+\n+You do not need to add the PPPoE and the VLAN devices to your flowtable,\n+instead the real device is sufficient for the flowtable to track your flows.\n+\n+Bridge and IP forwarding\n+------------------------\n+\n+Since Linux kernel 5.13, you can add bridge ports to the flowtable. The\n+flowtable infrastructure discovers the topology behind the bridge device. This\n+allows the flowtable to define a fastpath bypass between the bridge ports\n+(represented as eth1 and eth2 in the example figure below) and the gateway\n+device (represented as eth0) in your switch/router.\n+\n+::\n+                      fastpath bypass\n+               .-------------------------.\n+              /                           \\\n+              |           IP forwarding   |\n+              |          /             \\ \\/\n+              |       br0               eth0 ..... eth0\n+              .       / \\                          *host B*\n+               -> eth1  eth2\n+                   .           *switch/router*\n+                   .\n+                   .\n+                 eth0\n+               *host A*\n+\n+The flowtable infrastructure also supports for bridge VLAN filtering actions\n+such as PVID and untagged. You can also stack a classic VLAN device on top of\n+your bridge port.\n+\n+If you would like that your flowtable defines a fastpath between your bridge\n+ports and your IP forwarding path, you have to add your bridge ports (as\n+represented by the real netdevice) to your flowtable definition.\n+\n+Counters\n+--------\n+\n+The flowtable can synchronize packet and byte counters with the existing\n+connection tracking entry by specifying the counter statement in your flowtable\n+definition, e.g.\n+\n+::\n+\ttable inet x {\n+\t\tflowtable f {\n+\t\t\thook ingress priority 0; devices = { eth0, eth1 };\n+\t\t\tcounter\n+\t\t}\n+\t\t...\n+\t}\n+\n+Counter support is available since Linux kernel 5.7.\n+\n+Hardware offload\n+----------------\n+\n+If your network device provides hardware offload support, you can turn it on by\n+means of the 'offload' flag in your flowtable definition, e.g.\n+\n+::\n+\ttable inet x {\n+\t\tflowtable f {\n+\t\t\thook ingress priority 0; devices = { eth0, eth1 };\n+\t\t\tflags offload;\n+\t\t}\n+\t\t...\n+\t}\n+\n+There is a workqueue that adds the flows to the hardware. Note that a few\n+packets might still run over the flowtable software path until the workqueue has\n+a chance to offload the flow to the network device.\n+\n+You can identify hardware offloaded flows through the [HW_OFFLOAD] tag when\n+listing your connection tracking table. Please, note that the [OFFLOAD] tag\n+refers to the software offload mode, so there is a distinction between [OFFLOAD]\n+which refers to the software flowtable fastpath and [HW_OFFLOAD] which refers\n+to the hardware offload datapath being used by the flow.\n+\n+The flowtable hardware offload infrastructure also supports for the DSA\n+(Distributed Switch Architecture).\n+\n+Limitations\n+-----------\n+\n+The flowtable behaves like a cache. The flowtable entries might get stale if\n+either the destination MAC address or the egress netdevice that is used for\n+transmission changes.\n+\n+This might be a problem if:\n+\n+- You run the flowtable in software mode and you combine bridge and IP\n+  forwarding in your setup.\n+- Hardware offload is enabled.\n+\n More reading\n ------------\n \n"
  },
  {
    "path": "target/linux/generic/backport-5.10/610-v5.13-35-net-ethernet-mediatek-ppe-fix-busy-wait-loop.patch",
    "content": "From c5d66587b8900201e1530b7c18d41e87bd5812f4 Mon Sep 17 00:00:00 2001\nFrom: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com>\nDate: Thu, 15 Apr 2021 17:37:48 -0700\nSubject: [PATCH] net: ethernet: mediatek: ppe: fix busy wait loop\n\nThe intention is for the loop to timeout if the body does not succeed.\nThe current logic calls time_is_before_jiffies(timeout) which is false\nuntil after the timeout, so the loop body never executes.\n\nFix by using readl_poll_timeout as a more standard and less error-prone\nsolution.\n\nFixes: ba37b7caf1ed (\"net: ethernet: mtk_eth_soc: add support for initializing the PPE\")\nSigned-off-by: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com>\nCc: Felix Fietkau <nbd@nbd.name>\nReviewed-by: Andrew Lunn <andrew@lunn.ch>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/ethernet/mediatek/mtk_ppe.c | 20 +++++++++-----------\n drivers/net/ethernet/mediatek/mtk_ppe.h |  1 +\n 2 files changed, 10 insertions(+), 11 deletions(-)\n\n--- a/drivers/net/ethernet/mediatek/mtk_ppe.c\n+++ b/drivers/net/ethernet/mediatek/mtk_ppe.c\n@@ -2,9 +2,8 @@\n /* Copyright (C) 2020 Felix Fietkau <nbd@nbd.name> */\n \n #include <linux/kernel.h>\n-#include <linux/jiffies.h>\n-#include <linux/delay.h>\n #include <linux/io.h>\n+#include <linux/iopoll.h>\n #include <linux/etherdevice.h>\n #include <linux/platform_device.h>\n #include \"mtk_ppe.h\"\n@@ -44,18 +43,17 @@ static u32 ppe_clear(struct mtk_ppe *ppe\n \n static int mtk_ppe_wait_busy(struct mtk_ppe *ppe)\n {\n-\tunsigned long timeout = jiffies + HZ;\n-\n-\twhile (time_is_before_jiffies(timeout)) {\n-\t\tif (!(ppe_r32(ppe, MTK_PPE_GLO_CFG) & MTK_PPE_GLO_CFG_BUSY))\n-\t\t\treturn 0;\n+\tint ret;\n+\tu32 val;\n \n-\t\tusleep_range(10, 20);\n-\t}\n+\tret = readl_poll_timeout(ppe->base + MTK_PPE_GLO_CFG, val,\n+\t\t\t\t !(val & MTK_PPE_GLO_CFG_BUSY),\n+\t\t\t\t 20, MTK_PPE_WAIT_TIMEOUT_US);\n \n-\tdev_err(ppe->dev, \"PPE table busy\");\n+\tif (ret)\n+\t\tdev_err(ppe->dev, \"PPE table busy\");\n \n-\treturn -ETIMEDOUT;\n+\treturn ret;\n }\n \n static void mtk_ppe_cache_clear(struct mtk_ppe *ppe)\n--- a/drivers/net/ethernet/mediatek/mtk_ppe.h\n+++ b/drivers/net/ethernet/mediatek/mtk_ppe.h\n@@ -12,6 +12,7 @@\n #define MTK_PPE_ENTRIES_SHIFT\t\t3\n #define MTK_PPE_ENTRIES\t\t\t(1024 << MTK_PPE_ENTRIES_SHIFT)\n #define MTK_PPE_HASH_MASK\t\t(MTK_PPE_ENTRIES - 1)\n+#define MTK_PPE_WAIT_TIMEOUT_US\t\t1000000\n \n #define MTK_FOE_IB1_UNBIND_TIMESTAMP\tGENMASK(7, 0)\n #define MTK_FOE_IB1_UNBIND_PACKETS\tGENMASK(23, 8)\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/610-v5.13-36-net-ethernet-mediatek-fix-a-typo-bug-in-flow-offload.patch",
    "content": "From 6ecaf81d4ac6365f9284f9d68d74f7c209e74f98 Mon Sep 17 00:00:00 2001\nFrom: DENG Qingfang <dqfext@gmail.com>\nDate: Sat, 17 Apr 2021 15:29:04 +0800\nSubject: [PATCH] net: ethernet: mediatek: fix a typo bug in flow offloading\n\nIssue was traffic problems after a while with increased ping times if\nflow offload is active. It turns out that key_offset with cookie is\nneeded in rhashtable_params but was re-assigned to head_offset.\nFix the assignment.\n\nFixes: 502e84e2382d (\"net: ethernet: mtk_eth_soc: add flow offloading support\")\nSigned-off-by: DENG Qingfang <dqfext@gmail.com>\nTested-by: Frank Wunderlich <frank-w@public-files.de>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/ethernet/mediatek/mtk_ppe_offload.c | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/drivers/net/ethernet/mediatek/mtk_ppe_offload.c\n+++ b/drivers/net/ethernet/mediatek/mtk_ppe_offload.c\n@@ -44,7 +44,7 @@ struct mtk_flow_entry {\n \n static const struct rhashtable_params mtk_flow_ht_params = {\n \t.head_offset = offsetof(struct mtk_flow_entry, node),\n-\t.head_offset = offsetof(struct mtk_flow_entry, cookie),\n+\t.key_offset = offsetof(struct mtk_flow_entry, cookie),\n \t.key_len = sizeof(unsigned long),\n \t.automatic_shrinking = true,\n };\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/610-v5.13-38-net-ethernet-mtk_eth_soc-unmap-RX-data-before-callin.patch",
    "content": "From 5196c417854942e218a59ec87bf7d414b3bd581e Mon Sep 17 00:00:00 2001\nFrom: Felix Fietkau <nbd@nbd.name>\nDate: Thu, 22 Apr 2021 22:20:55 -0700\nSubject: [PATCH] net: ethernet: mtk_eth_soc: unmap RX data before calling\n build_skb\n\nSince build_skb accesses the data area (for initializing shinfo), dma unmap\nneeds to happen before that call\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n[Ilya: split build_skb cleanup fix into a separate commit]\nSigned-off-by: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/ethernet/mediatek/mtk_eth_soc.c | 5 +++--\n 1 file changed, 3 insertions(+), 2 deletions(-)\n\n--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c\n+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c\n@@ -1319,6 +1319,9 @@ static int mtk_poll_rx(struct napi_struc\n \t\t\tgoto release_desc;\n \t\t}\n \n+\t\tdma_unmap_single(eth->dev, trxd.rxd1,\n+\t\t\t\t ring->buf_size, DMA_FROM_DEVICE);\n+\n \t\t/* receive data */\n \t\tskb = build_skb(data, ring->frag_size);\n \t\tif (unlikely(!skb)) {\n@@ -1328,8 +1331,6 @@ static int mtk_poll_rx(struct napi_struc\n \t\t}\n \t\tskb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN);\n \n-\t\tdma_unmap_single(eth->dev, trxd.rxd1,\n-\t\t\t\t ring->buf_size, DMA_FROM_DEVICE);\n \t\tpktlen = RX_DMA_GET_PLEN0(trxd.rxd2);\n \t\tskb->dev = netdev;\n \t\tskb_put(skb, pktlen);\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/610-v5.13-39-net-ethernet-mtk_eth_soc-fix-build_skb-cleanup.patch",
    "content": "From 787082ab9f7be4711e52f67c388535eda74a1269 Mon Sep 17 00:00:00 2001\nFrom: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com>\nDate: Thu, 22 Apr 2021 22:20:56 -0700\nSubject: [PATCH] net: ethernet: mtk_eth_soc: fix build_skb cleanup\n\nIn case build_skb fails, call skb_free_frag on the correct pointer. Also\nupdate the DMA structures with the new mapping before exiting, because\nthe mapping was successful\n\nSuggested-by: Felix Fietkau <nbd@nbd.name>\nSigned-off-by: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/ethernet/mediatek/mtk_eth_soc.c | 5 +++--\n 1 file changed, 3 insertions(+), 2 deletions(-)\n\n--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c\n+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c\n@@ -1325,9 +1325,9 @@ static int mtk_poll_rx(struct napi_struc\n \t\t/* receive data */\n \t\tskb = build_skb(data, ring->frag_size);\n \t\tif (unlikely(!skb)) {\n-\t\t\tskb_free_frag(new_data);\n+\t\t\tskb_free_frag(data);\n \t\t\tnetdev->stats.rx_dropped++;\n-\t\t\tgoto release_desc;\n+\t\t\tgoto skip_rx;\n \t\t}\n \t\tskb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN);\n \n@@ -1347,6 +1347,7 @@ static int mtk_poll_rx(struct napi_struc\n \t\tskb_record_rx_queue(skb, 0);\n \t\tnapi_gro_receive(napi, skb);\n \n+skip_rx:\n \t\tring->data[idx] = new_data;\n \t\trxd->rxd1 = (unsigned int)dma_addr;\n \n"
  },
  {
    "path": "target/linux/generic/backport-5.10/610-v5.13-40-net-ethernet-mtk_eth_soc-use-napi_consume_skb.patch",
    "content": "From c30c4a82739090a2de4a4e3f245355ea4fb3ec14 Mon Sep 17 00:00:00 2001\nFrom: Felix Fietkau <nbd@nbd.name>\nDate: Thu, 22 Apr 2021 22:20:57 -0700\nSubject: [PATCH] net: ethernet: mtk_eth_soc: use napi_consume_skb\n\nShould improve performance, since it can use bulk free\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\nSigned-off-by: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/ethernet/mediatek/mtk_eth_soc.c | 19 ++++++++++++-------\n 1 file changed, 12 insertions(+), 7 deletions(-)\n\n--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c\n+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c\n@@ -879,7 +879,8 @@ static int txd_to_idx(struct mtk_tx_ring\n \treturn ((void *)dma - (void *)ring->dma) / sizeof(*dma);\n }\n \n-static void mtk_tx_unmap(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf)\n+static void mtk_tx_unmap(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf,\n+\t\t\t bool napi)\n {\n \tif (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {\n \t\tif (tx_buf->flags & MTK_TX_FLAGS_SINGLE0) {\n@@ -911,8 +912,12 @@ static void mtk_tx_unmap(struct mtk_eth\n \n \ttx_buf->flags = 0;\n \tif (tx_buf->skb &&\n-\t    (tx_buf->skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC))\n-\t\tdev_kfree_skb_any(tx_buf->skb);\n+\t    (tx_buf->skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC)) {\n+\t\tif (napi)\n+\t\t\tnapi_consume_skb(tx_buf->skb, napi);\n+\t\telse\n+\t\t\tdev_kfree_skb_any(tx_buf->skb);\n+\t}\n \ttx_buf->skb = NULL;\n }\n \n@@ -1090,7 +1095,7 @@ err_dma:\n \t\ttx_buf = mtk_desc_to_tx_buf(ring, itxd);\n \n \t\t/* unmap dma */\n-\t\tmtk_tx_unmap(eth, tx_buf);\n+\t\tmtk_tx_unmap(eth, tx_buf, false);\n \n \t\titxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU;\n \t\tif (!MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA))\n@@ -1409,7 +1414,7 @@ static int mtk_poll_tx_qdma(struct mtk_e\n \t\t\tdone[mac]++;\n \t\t\tbudget--;\n \t\t}\n-\t\tmtk_tx_unmap(eth, tx_buf);\n+\t\tmtk_tx_unmap(eth, tx_buf, true);\n \n \t\tring->last_free = desc;\n \t\tatomic_inc(&ring->free_count);\n@@ -1446,7 +1451,7 @@ static int mtk_poll_tx_pdma(struct mtk_e\n \t\t\tbudget--;\n \t\t}\n \n-\t\tmtk_tx_unmap(eth, tx_buf);\n+\t\tmtk_tx_unmap(eth, tx_buf, true);\n \n \t\tdesc = &ring->dma[cpu];\n \t\tring->last_free = desc;\n@@ -1648,7 +1653,7 @@ static void mtk_tx_clean(struct mtk_eth\n \n \tif (ring->buf) {\n \t\tfor (i = 0; i < MTK_DMA_SIZE; i++)\n-\t\t\tmtk_tx_unmap(eth, &ring->buf[i]);\n+\t\t\tmtk_tx_unmap(eth, &ring->buf[i], false);\n \t\tkfree(ring->buf);\n \t\tring->buf = NULL;\n \t}\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/610-v5.13-41-net-ethernet-mtk_eth_soc-reduce-MDIO-bus-access-late.patch",
    "content": "From 3630d519d7c3eab92567658690e44ffe0517d109 Mon Sep 17 00:00:00 2001\nFrom: Felix Fietkau <nbd@nbd.name>\nDate: Thu, 22 Apr 2021 22:20:58 -0700\nSubject: [PATCH] net: ethernet: mtk_eth_soc: reduce MDIO bus access latency\n\nusleep_range often ends up sleeping much longer than the 10-20us provided\nas a range here. This causes significant latency in mdio bus acceses,\nwhich easily adds multiple seconds to the boot time on MT7621 when polling\nDSA slave ports.\nUse cond_resched instead of usleep_range, since the MDIO access does not\ntake much time\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\nSigned-off-by: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/ethernet/mediatek/mtk_eth_soc.c | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c\n+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c\n@@ -86,7 +86,7 @@ static int mtk_mdio_busy_wait(struct mtk\n \t\t\treturn 0;\n \t\tif (time_after(jiffies, t_start + PHY_IAC_TIMEOUT))\n \t\t\tbreak;\n-\t\tusleep_range(10, 20);\n+\t\tcond_resched();\n \t}\n \n \tdev_err(eth->dev, \"mdio: MDIO timeout\\n\");\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/610-v5.13-42-net-ethernet-mtk_eth_soc-remove-unnecessary-TX-queue.patch",
    "content": "From 16ef670789b252b221700adc413497ed2f941d8a Mon Sep 17 00:00:00 2001\nFrom: Felix Fietkau <nbd@nbd.name>\nDate: Thu, 22 Apr 2021 22:20:59 -0700\nSubject: [PATCH] net: ethernet: mtk_eth_soc: remove unnecessary TX queue stops\n\nWhen running short on descriptors, only stop the queue for the netdev that\ntx was attempted for. By the time something tries to send on the other\nnetdev, the ring might have some more room already.\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\nSigned-off-by: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/ethernet/mediatek/mtk_eth_soc.c | 15 ++-------------\n 1 file changed, 2 insertions(+), 13 deletions(-)\n\n--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c\n+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c\n@@ -1152,17 +1152,6 @@ static void mtk_wake_queue(struct mtk_et\n \t}\n }\n \n-static void mtk_stop_queue(struct mtk_eth *eth)\n-{\n-\tint i;\n-\n-\tfor (i = 0; i < MTK_MAC_COUNT; i++) {\n-\t\tif (!eth->netdev[i])\n-\t\t\tcontinue;\n-\t\tnetif_stop_queue(eth->netdev[i]);\n-\t}\n-}\n-\n static netdev_tx_t mtk_start_xmit(struct sk_buff *skb, struct net_device *dev)\n {\n \tstruct mtk_mac *mac = netdev_priv(dev);\n@@ -1183,7 +1172,7 @@ static netdev_tx_t mtk_start_xmit(struct\n \n \ttx_num = mtk_cal_txd_req(skb);\n \tif (unlikely(atomic_read(&ring->free_count) <= tx_num)) {\n-\t\tmtk_stop_queue(eth);\n+\t\tnetif_stop_queue(dev);\n \t\tnetif_err(eth, tx_queued, dev,\n \t\t\t  \"Tx Ring full when queue awake!\\n\");\n \t\tspin_unlock(&eth->page_lock);\n@@ -1209,7 +1198,7 @@ static netdev_tx_t mtk_start_xmit(struct\n \t\tgoto drop;\n \n \tif (unlikely(atomic_read(&ring->free_count) <= ring->thresh))\n-\t\tmtk_stop_queue(eth);\n+\t\tnetif_stop_queue(dev);\n \n \tspin_unlock(&eth->page_lock);\n \n"
  },
  {
    "path": "target/linux/generic/backport-5.10/610-v5.13-43-net-ethernet-mtk_eth_soc-use-larger-burst-size-for-Q.patch",
    "content": "From 59555a8d0dd39bf60b7ca1ba5e7393d293f7398d Mon Sep 17 00:00:00 2001\nFrom: Felix Fietkau <nbd@nbd.name>\nDate: Thu, 22 Apr 2021 22:21:00 -0700\nSubject: [PATCH] net: ethernet: mtk_eth_soc: use larger burst size for QDMA TX\n\nImproves tx performance\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\nSigned-off-by: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/ethernet/mediatek/mtk_eth_soc.c | 2 +-\n drivers/net/ethernet/mediatek/mtk_eth_soc.h | 2 +-\n 2 files changed, 2 insertions(+), 2 deletions(-)\n\n--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c\n+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c\n@@ -2214,7 +2214,7 @@ static int mtk_start_dma(struct mtk_eth\n \tif (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {\n \t\tmtk_w32(eth,\n \t\t\tMTK_TX_WB_DDONE | MTK_TX_DMA_EN |\n-\t\t\tMTK_DMA_SIZE_16DWORDS | MTK_NDP_CO_PRO |\n+\t\t\tMTK_TX_BT_32DWORDS | MTK_NDP_CO_PRO |\n \t\t\tMTK_RX_DMA_EN | MTK_RX_2B_OFFSET |\n \t\t\tMTK_RX_BT_32DWORDS,\n \t\t\tMTK_QDMA_GLO_CFG);\n--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h\n+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h\n@@ -202,7 +202,7 @@\n #define MTK_RX_BT_32DWORDS\t(3 << 11)\n #define MTK_NDP_CO_PRO\t\tBIT(10)\n #define MTK_TX_WB_DDONE\t\tBIT(6)\n-#define MTK_DMA_SIZE_16DWORDS\t(2 << 4)\n+#define MTK_TX_BT_32DWORDS\t(3 << 4)\n #define MTK_RX_DMA_BUSY\t\tBIT(3)\n #define MTK_TX_DMA_BUSY\t\tBIT(1)\n #define MTK_RX_DMA_EN\t\tBIT(2)\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/610-v5.13-44-net-ethernet-mtk_eth_soc-increase-DMA-ring-sizes.patch",
    "content": "From 6b4423b258b91032c50a5efca15d3d9bb194ea1d Mon Sep 17 00:00:00 2001\nFrom: Felix Fietkau <nbd@nbd.name>\nDate: Thu, 22 Apr 2021 22:21:01 -0700\nSubject: [PATCH] net: ethernet: mtk_eth_soc: increase DMA ring sizes\n\n256 descriptors is not enough for multi-gigabit traffic under load on\nMT7622. Bump it to 512 to improve performance.\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\nSigned-off-by: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/ethernet/mediatek/mtk_eth_soc.h | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h\n+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h\n@@ -21,7 +21,7 @@\n #define MTK_QDMA_PAGE_SIZE\t2048\n #define\tMTK_MAX_RX_LENGTH\t1536\n #define MTK_TX_DMA_BUF_LEN\t0x3fff\n-#define MTK_DMA_SIZE\t\t256\n+#define MTK_DMA_SIZE\t\t512\n #define MTK_NAPI_WEIGHT\t\t64\n #define MTK_MAC_COUNT\t\t2\n #define MTK_RX_ETH_HLEN\t\t(VLAN_ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN)\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/610-v5.13-45-net-ethernet-mtk_eth_soc-implement-dynamic-interrupt.patch",
    "content": "From e9229ffd550b2d8c4997c67a501dbc3919fd4e26 Mon Sep 17 00:00:00 2001\nFrom: Felix Fietkau <nbd@nbd.name>\nDate: Thu, 22 Apr 2021 22:21:02 -0700\nSubject: [PATCH] net: ethernet: mtk_eth_soc: implement dynamic interrupt\n moderation\n\nReduces the number of interrupts under load\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n[Ilya: add documentation for new struct fields]\nSigned-off-by: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/ethernet/mediatek/Kconfig       |  1 +\n drivers/net/ethernet/mediatek/mtk_eth_soc.c | 96 +++++++++++++++++++--\n drivers/net/ethernet/mediatek/mtk_eth_soc.h | 41 +++++++--\n 3 files changed, 124 insertions(+), 14 deletions(-)\n\n--- a/drivers/net/ethernet/mediatek/Kconfig\n+++ b/drivers/net/ethernet/mediatek/Kconfig\n@@ -10,6 +10,7 @@ if NET_VENDOR_MEDIATEK\n config NET_MEDIATEK_SOC\n \ttristate \"MediaTek SoC Gigabit Ethernet support\"\n \tselect PHYLINK\n+\tselect DIMLIB\n \thelp\n \t  This driver supports the gigabit ethernet MACs in the\n \t  MediaTek SoC family.\n--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c\n+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c\n@@ -1254,12 +1254,13 @@ static void mtk_update_rx_cpu_idx(struct\n static int mtk_poll_rx(struct napi_struct *napi, int budget,\n \t\t       struct mtk_eth *eth)\n {\n+\tstruct dim_sample dim_sample = {};\n \tstruct mtk_rx_ring *ring;\n \tint idx;\n \tstruct sk_buff *skb;\n \tu8 *data, *new_data;\n \tstruct mtk_rx_dma *rxd, trxd;\n-\tint done = 0;\n+\tint done = 0, bytes = 0;\n \n \twhile (done < budget) {\n \t\tstruct net_device *netdev;\n@@ -1333,6 +1334,7 @@ static int mtk_poll_rx(struct napi_struc\n \t\telse\n \t\t\tskb_checksum_none_assert(skb);\n \t\tskb->protocol = eth_type_trans(skb, netdev);\n+\t\tbytes += pktlen;\n \n \t\tif (netdev->features & NETIF_F_HW_VLAN_CTAG_RX &&\n \t\t    (trxd.rxd2 & RX_DMA_VTAG))\n@@ -1365,6 +1367,12 @@ rx_done:\n \t\tmtk_update_rx_cpu_idx(eth);\n \t}\n \n+\teth->rx_packets += done;\n+\teth->rx_bytes += bytes;\n+\tdim_update_sample(eth->rx_events, eth->rx_packets, eth->rx_bytes,\n+\t\t\t  &dim_sample);\n+\tnet_dim(&eth->rx_dim, dim_sample);\n+\n \treturn done;\n }\n \n@@ -1457,6 +1465,7 @@ static int mtk_poll_tx_pdma(struct mtk_e\n static int mtk_poll_tx(struct mtk_eth *eth, int budget)\n {\n \tstruct mtk_tx_ring *ring = &eth->tx_ring;\n+\tstruct dim_sample dim_sample = {};\n \tunsigned int done[MTK_MAX_DEVS];\n \tunsigned int bytes[MTK_MAX_DEVS];\n \tint total = 0, i;\n@@ -1474,8 +1483,14 @@ static int mtk_poll_tx(struct mtk_eth *e\n \t\t\tcontinue;\n \t\tnetdev_completed_queue(eth->netdev[i], done[i], bytes[i]);\n \t\ttotal += done[i];\n+\t\teth->tx_packets += done[i];\n+\t\teth->tx_bytes += bytes[i];\n \t}\n \n+\tdim_update_sample(eth->tx_events, eth->tx_packets, eth->tx_bytes,\n+\t\t\t  &dim_sample);\n+\tnet_dim(&eth->tx_dim, dim_sample);\n+\n \tif (mtk_queue_stopped(eth) &&\n \t    (atomic_read(&ring->free_count) > ring->thresh))\n \t\tmtk_wake_queue(eth);\n@@ -2150,6 +2165,7 @@ static irqreturn_t mtk_handle_irq_rx(int\n {\n \tstruct mtk_eth *eth = _eth;\n \n+\teth->rx_events++;\n \tif (likely(napi_schedule_prep(&eth->rx_napi))) {\n \t\t__napi_schedule(&eth->rx_napi);\n \t\tmtk_rx_irq_disable(eth, MTK_RX_DONE_INT);\n@@ -2162,6 +2178,7 @@ static irqreturn_t mtk_handle_irq_tx(int\n {\n \tstruct mtk_eth *eth = _eth;\n \n+\teth->tx_events++;\n \tif (likely(napi_schedule_prep(&eth->tx_napi))) {\n \t\t__napi_schedule(&eth->tx_napi);\n \t\tmtk_tx_irq_disable(eth, MTK_TX_DONE_INT);\n@@ -2346,6 +2363,9 @@ static int mtk_stop(struct net_device *d\n \tnapi_disable(&eth->tx_napi);\n \tnapi_disable(&eth->rx_napi);\n \n+\tcancel_work_sync(&eth->rx_dim.work);\n+\tcancel_work_sync(&eth->tx_dim.work);\n+\n \tif (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA))\n \t\tmtk_stop_dma(eth, MTK_QDMA_GLO_CFG);\n \tmtk_stop_dma(eth, MTK_PDMA_GLO_CFG);\n@@ -2398,6 +2418,64 @@ err_disable_clks:\n \treturn ret;\n }\n \n+static void mtk_dim_rx(struct work_struct *work)\n+{\n+\tstruct dim *dim = container_of(work, struct dim, work);\n+\tstruct mtk_eth *eth = container_of(dim, struct mtk_eth, rx_dim);\n+\tstruct dim_cq_moder cur_profile;\n+\tu32 val, cur;\n+\n+\tcur_profile = net_dim_get_rx_moderation(eth->rx_dim.mode,\n+\t\t\t\t\t\tdim->profile_ix);\n+\tspin_lock_bh(&eth->dim_lock);\n+\n+\tval = mtk_r32(eth, MTK_PDMA_DELAY_INT);\n+\tval &= MTK_PDMA_DELAY_TX_MASK;\n+\tval |= MTK_PDMA_DELAY_RX_EN;\n+\n+\tcur = min_t(u32, DIV_ROUND_UP(cur_profile.usec, 20), MTK_PDMA_DELAY_PTIME_MASK);\n+\tval |= cur << MTK_PDMA_DELAY_RX_PTIME_SHIFT;\n+\n+\tcur = min_t(u32, cur_profile.pkts, MTK_PDMA_DELAY_PINT_MASK);\n+\tval |= cur << MTK_PDMA_DELAY_RX_PINT_SHIFT;\n+\n+\tmtk_w32(eth, val, MTK_PDMA_DELAY_INT);\n+\tmtk_w32(eth, val, MTK_QDMA_DELAY_INT);\n+\n+\tspin_unlock_bh(&eth->dim_lock);\n+\n+\tdim->state = DIM_START_MEASURE;\n+}\n+\n+static void mtk_dim_tx(struct work_struct *work)\n+{\n+\tstruct dim *dim = container_of(work, struct dim, work);\n+\tstruct mtk_eth *eth = container_of(dim, struct mtk_eth, tx_dim);\n+\tstruct dim_cq_moder cur_profile;\n+\tu32 val, cur;\n+\n+\tcur_profile = net_dim_get_tx_moderation(eth->tx_dim.mode,\n+\t\t\t\t\t\tdim->profile_ix);\n+\tspin_lock_bh(&eth->dim_lock);\n+\n+\tval = mtk_r32(eth, MTK_PDMA_DELAY_INT);\n+\tval &= MTK_PDMA_DELAY_RX_MASK;\n+\tval |= MTK_PDMA_DELAY_TX_EN;\n+\n+\tcur = min_t(u32, DIV_ROUND_UP(cur_profile.usec, 20), MTK_PDMA_DELAY_PTIME_MASK);\n+\tval |= cur << MTK_PDMA_DELAY_TX_PTIME_SHIFT;\n+\n+\tcur = min_t(u32, cur_profile.pkts, MTK_PDMA_DELAY_PINT_MASK);\n+\tval |= cur << MTK_PDMA_DELAY_TX_PINT_SHIFT;\n+\n+\tmtk_w32(eth, val, MTK_PDMA_DELAY_INT);\n+\tmtk_w32(eth, val, MTK_QDMA_DELAY_INT);\n+\n+\tspin_unlock_bh(&eth->dim_lock);\n+\n+\tdim->state = DIM_START_MEASURE;\n+}\n+\n static int mtk_hw_init(struct mtk_eth *eth)\n {\n \tint i, val, ret;\n@@ -2419,9 +2497,6 @@ static int mtk_hw_init(struct mtk_eth *e\n \t\t\tgoto err_disable_pm;\n \t\t}\n \n-\t\t/* enable interrupt delay for RX */\n-\t\tmtk_w32(eth, MTK_PDMA_DELAY_RX_DELAY, MTK_PDMA_DELAY_INT);\n-\n \t\t/* disable delay and normal interrupt */\n \t\tmtk_tx_irq_disable(eth, ~0);\n \t\tmtk_rx_irq_disable(eth, ~0);\n@@ -2460,11 +2535,11 @@ static int mtk_hw_init(struct mtk_eth *e\n \t/* Enable RX VLan Offloading */\n \tmtk_w32(eth, 1, MTK_CDMP_EG_CTRL);\n \n-\t/* enable interrupt delay for RX */\n-\tmtk_w32(eth, MTK_PDMA_DELAY_RX_DELAY, MTK_PDMA_DELAY_INT);\n+\t/* set interrupt delays based on current Net DIM sample */\n+\tmtk_dim_rx(&eth->rx_dim.work);\n+\tmtk_dim_tx(&eth->tx_dim.work);\n \n \t/* disable delay and normal interrupt */\n-\tmtk_w32(eth, 0, MTK_QDMA_DELAY_INT);\n \tmtk_tx_irq_disable(eth, ~0);\n \tmtk_rx_irq_disable(eth, ~0);\n \n@@ -2969,6 +3044,13 @@ static int mtk_probe(struct platform_dev\n \tspin_lock_init(&eth->page_lock);\n \tspin_lock_init(&eth->tx_irq_lock);\n \tspin_lock_init(&eth->rx_irq_lock);\n+\tspin_lock_init(&eth->dim_lock);\n+\n+\teth->rx_dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;\n+\tINIT_WORK(&eth->rx_dim.work, mtk_dim_rx);\n+\n+\teth->tx_dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;\n+\tINIT_WORK(&eth->tx_dim.work, mtk_dim_tx);\n \n \tif (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) {\n \t\teth->ethsys = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,\n--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h\n+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h\n@@ -16,6 +16,7 @@\n #include <linux/refcount.h>\n #include <linux/phylink.h>\n #include <linux/rhashtable.h>\n+#include <linux/dim.h>\n #include \"mtk_ppe.h\"\n \n #define MTK_QDMA_PAGE_SIZE\t2048\n@@ -136,13 +137,18 @@\n \n /* PDMA Delay Interrupt Register */\n #define MTK_PDMA_DELAY_INT\t\t0xa0c\n+#define MTK_PDMA_DELAY_RX_MASK\t\tGENMASK(15, 0)\n #define MTK_PDMA_DELAY_RX_EN\t\tBIT(15)\n-#define MTK_PDMA_DELAY_RX_PINT\t\t4\n #define MTK_PDMA_DELAY_RX_PINT_SHIFT\t8\n-#define MTK_PDMA_DELAY_RX_PTIME\t\t4\n-#define MTK_PDMA_DELAY_RX_DELAY\t\t\\\n-\t(MTK_PDMA_DELAY_RX_EN | MTK_PDMA_DELAY_RX_PTIME | \\\n-\t(MTK_PDMA_DELAY_RX_PINT << MTK_PDMA_DELAY_RX_PINT_SHIFT))\n+#define MTK_PDMA_DELAY_RX_PTIME_SHIFT\t0\n+\n+#define MTK_PDMA_DELAY_TX_MASK\t\tGENMASK(31, 16)\n+#define MTK_PDMA_DELAY_TX_EN\t\tBIT(31)\n+#define MTK_PDMA_DELAY_TX_PINT_SHIFT\t24\n+#define MTK_PDMA_DELAY_TX_PTIME_SHIFT\t16\n+\n+#define MTK_PDMA_DELAY_PINT_MASK\t0x7f\n+#define MTK_PDMA_DELAY_PTIME_MASK\t0xff\n \n /* PDMA Interrupt Status Register */\n #define MTK_PDMA_INT_STATUS\t0xa20\n@@ -224,6 +230,7 @@\n /* QDMA Interrupt Status Register */\n #define MTK_QDMA_INT_STATUS\t0x1A18\n #define MTK_RX_DONE_DLY\t\tBIT(30)\n+#define MTK_TX_DONE_DLY\t\tBIT(28)\n #define MTK_RX_DONE_INT3\tBIT(19)\n #define MTK_RX_DONE_INT2\tBIT(18)\n #define MTK_RX_DONE_INT1\tBIT(17)\n@@ -233,8 +240,7 @@\n #define MTK_TX_DONE_INT1\tBIT(1)\n #define MTK_TX_DONE_INT0\tBIT(0)\n #define MTK_RX_DONE_INT\t\tMTK_RX_DONE_DLY\n-#define MTK_TX_DONE_INT\t\t(MTK_TX_DONE_INT0 | MTK_TX_DONE_INT1 | \\\n-\t\t\t\t MTK_TX_DONE_INT2 | MTK_TX_DONE_INT3)\n+#define MTK_TX_DONE_INT\t\tMTK_TX_DONE_DLY\n \n /* QDMA Interrupt grouping registers */\n #define MTK_QDMA_INT_GRP1\t0x1a20\n@@ -863,6 +869,7 @@ struct mtk_sgmii {\n  * @page_lock:\t\tMake sure that register operations are atomic\n  * @tx_irq__lock:\tMake sure that IRQ register operations are atomic\n  * @rx_irq__lock:\tMake sure that IRQ register operations are atomic\n+ * @dim_lock:\t\tMake sure that Net DIM operations are atomic\n  * @dummy_dev:\t\twe run 2 netdevs on 1 physical DMA ring and need a\n  *\t\t\tdummy for NAPI to work\n  * @netdev:\t\tThe netdev instances\n@@ -881,6 +888,14 @@ struct mtk_sgmii {\n  * @rx_ring_qdma:\tPointer to the memory holding info about the QDMA RX ring\n  * @tx_napi:\t\tThe TX NAPI struct\n  * @rx_napi:\t\tThe RX NAPI struct\n+ * @rx_events:\t\tNet DIM RX event counter\n+ * @rx_packets:\t\tNet DIM RX packet counter\n+ * @rx_bytes:\t\tNet DIM RX byte counter\n+ * @rx_dim:\t\tNet DIM RX context\n+ * @tx_events:\t\tNet DIM TX event counter\n+ * @tx_packets:\t\tNet DIM TX packet counter\n+ * @tx_bytes:\t\tNet DIM TX byte counter\n+ * @tx_dim:\t\tNet DIM TX context\n  * @scratch_ring:\tNewer SoCs need memory for a second HW managed TX ring\n  * @phy_scratch_ring:\tphysical address of scratch_ring\n  * @scratch_head:\tThe scratch memory that scratch_ring points to.\n@@ -925,6 +940,18 @@ struct mtk_eth {\n \n \tconst struct mtk_soc_data\t*soc;\n \n+\tspinlock_t\t\t\tdim_lock;\n+\n+\tu32\t\t\t\trx_events;\n+\tu32\t\t\t\trx_packets;\n+\tu32\t\t\t\trx_bytes;\n+\tstruct dim\t\t\trx_dim;\n+\n+\tu32\t\t\t\ttx_events;\n+\tu32\t\t\t\ttx_packets;\n+\tu32\t\t\t\ttx_bytes;\n+\tstruct dim\t\t\ttx_dim;\n+\n \tu32\t\t\t\ttx_int_mask_reg;\n \tu32\t\t\t\ttx_int_status_reg;\n \tu32\t\t\t\trx_dma_l4_valid;\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/610-v5.13-46-net-ethernet-mtk_eth_soc-cache-HW-pointer-of-last-fr.patch",
    "content": "From 4e6bf609569c59b6bd6acf4a607c096cbd820d79 Mon Sep 17 00:00:00 2001\nFrom: Felix Fietkau <nbd@nbd.name>\nDate: Thu, 22 Apr 2021 22:21:03 -0700\nSubject: [PATCH] net: ethernet: mtk_eth_soc: cache HW pointer of last freed TX\n descriptor\n\nThe value is only updated by the CPU, so it is cheaper to access from the\nring data structure than from a hardware register.\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\nSigned-off-by: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/ethernet/mediatek/mtk_eth_soc.c | 8 ++++----\n drivers/net/ethernet/mediatek/mtk_eth_soc.h | 2 ++\n 2 files changed, 6 insertions(+), 4 deletions(-)\n\n--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c\n+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c\n@@ -1385,7 +1385,7 @@ static int mtk_poll_tx_qdma(struct mtk_e\n \tstruct mtk_tx_buf *tx_buf;\n \tu32 cpu, dma;\n \n-\tcpu = mtk_r32(eth, MTK_QTX_CRX_PTR);\n+\tcpu = ring->last_free_ptr;\n \tdma = mtk_r32(eth, MTK_QTX_DRX_PTR);\n \n \tdesc = mtk_qdma_phys_to_virt(ring, cpu);\n@@ -1419,6 +1419,7 @@ static int mtk_poll_tx_qdma(struct mtk_e\n \t\tcpu = next_cpu;\n \t}\n \n+\tring->last_free_ptr = cpu;\n \tmtk_w32(eth, cpu, MTK_QTX_CRX_PTR);\n \n \treturn budget;\n@@ -1619,6 +1620,7 @@ static int mtk_tx_alloc(struct mtk_eth *\n \tatomic_set(&ring->free_count, MTK_DMA_SIZE - 2);\n \tring->next_free = &ring->dma[0];\n \tring->last_free = &ring->dma[MTK_DMA_SIZE - 1];\n+\tring->last_free_ptr = (u32)(ring->phys + ((MTK_DMA_SIZE - 1) * sz));\n \tring->thresh = MAX_SKB_FRAGS;\n \n \t/* make sure that all changes to the dma ring are flushed before we\n@@ -1632,9 +1634,7 @@ static int mtk_tx_alloc(struct mtk_eth *\n \t\tmtk_w32(eth,\n \t\t\tring->phys + ((MTK_DMA_SIZE - 1) * sz),\n \t\t\tMTK_QTX_CRX_PTR);\n-\t\tmtk_w32(eth,\n-\t\t\tring->phys + ((MTK_DMA_SIZE - 1) * sz),\n-\t\t\tMTK_QTX_DRX_PTR);\n+\t\tmtk_w32(eth, ring->last_free_ptr, MTK_QTX_DRX_PTR);\n \t\tmtk_w32(eth, (QDMA_RES_THRES << 8) | QDMA_RES_THRES,\n \t\t\tMTK_QTX_CFG(0));\n \t} else {\n--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h\n+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h\n@@ -656,6 +656,7 @@ struct mtk_tx_buf {\n  * @phys:\t\tThe physical addr of tx_buf\n  * @next_free:\t\tPointer to the next free descriptor\n  * @last_free:\t\tPointer to the last free descriptor\n+ * @last_free_ptr:\tHardware pointer value of the last free descriptor\n  * @thresh:\t\tThe threshold of minimum amount of free descriptors\n  * @free_count:\t\tQDMA uses a linked list. Track how many free descriptors\n  *\t\t\tare present\n@@ -666,6 +667,7 @@ struct mtk_tx_ring {\n \tdma_addr_t phys;\n \tstruct mtk_tx_dma *next_free;\n \tstruct mtk_tx_dma *last_free;\n+\tu32 last_free_ptr;\n \tu16 thresh;\n \tatomic_t free_count;\n \tint dma_size;\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/610-v5.13-47-net-ethernet-mtk_eth_soc-only-read-the-full-RX-descr.patch",
    "content": "From 816ac3e6e67bdd78d86226c6eb53619780750e92 Mon Sep 17 00:00:00 2001\nFrom: Felix Fietkau <nbd@nbd.name>\nDate: Thu, 22 Apr 2021 22:21:04 -0700\nSubject: [PATCH] net: ethernet: mtk_eth_soc: only read the full RX descriptor\n if DMA is done\n\nUncached memory access is expensive, and there is no need to access all\ndescriptor words if we can't process them anyway\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\nSigned-off-by: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/ethernet/mediatek/mtk_eth_soc.c | 12 ++++++++----\n 1 file changed, 8 insertions(+), 4 deletions(-)\n\n--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c\n+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c\n@@ -798,13 +798,18 @@ static inline int mtk_max_buf_size(int f\n \treturn buf_size;\n }\n \n-static inline void mtk_rx_get_desc(struct mtk_rx_dma *rxd,\n+static inline bool mtk_rx_get_desc(struct mtk_rx_dma *rxd,\n \t\t\t\t   struct mtk_rx_dma *dma_rxd)\n {\n-\trxd->rxd1 = READ_ONCE(dma_rxd->rxd1);\n \trxd->rxd2 = READ_ONCE(dma_rxd->rxd2);\n+\tif (!(rxd->rxd2 & RX_DMA_DONE))\n+\t\treturn false;\n+\n+\trxd->rxd1 = READ_ONCE(dma_rxd->rxd1);\n \trxd->rxd3 = READ_ONCE(dma_rxd->rxd3);\n \trxd->rxd4 = READ_ONCE(dma_rxd->rxd4);\n+\n+\treturn true;\n }\n \n /* the qdma core needs scratch memory to be setup */\n@@ -1276,8 +1281,7 @@ static int mtk_poll_rx(struct napi_struc\n \t\trxd = &ring->dma[idx];\n \t\tdata = ring->data[idx];\n \n-\t\tmtk_rx_get_desc(&trxd, rxd);\n-\t\tif (!(trxd.rxd2 & RX_DMA_DONE))\n+\t\tif (!mtk_rx_get_desc(&trxd, rxd))\n \t\t\tbreak;\n \n \t\t/* find out which mac the packet come from. values start at 1 */\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/610-v5.13-48-net-ethernet-mtk_eth_soc-reduce-unnecessary-interrup.patch",
    "content": "From 16769a8923fad5a5377253bcd76b0e0d64976c73 Mon Sep 17 00:00:00 2001\nFrom: Felix Fietkau <nbd@nbd.name>\nDate: Thu, 22 Apr 2021 22:21:05 -0700\nSubject: [PATCH] net: ethernet: mtk_eth_soc: reduce unnecessary interrupts\n\nAvoid rearming interrupt if napi_complete returns false\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\nSigned-off-by: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/ethernet/mediatek/mtk_eth_soc.c | 9 +++++----\n 1 file changed, 5 insertions(+), 4 deletions(-)\n\n--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c\n+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c\n@@ -1540,8 +1540,8 @@ static int mtk_napi_tx(struct napi_struc\n \tif (status & MTK_TX_DONE_INT)\n \t\treturn budget;\n \n-\tnapi_complete(napi);\n-\tmtk_tx_irq_enable(eth, MTK_TX_DONE_INT);\n+\tif (napi_complete(napi))\n+\t\tmtk_tx_irq_enable(eth, MTK_TX_DONE_INT);\n \n \treturn tx_done;\n }\n@@ -1574,8 +1574,9 @@ poll_again:\n \t\tremain_budget -= rx_done;\n \t\tgoto poll_again;\n \t}\n-\tnapi_complete(napi);\n-\tmtk_rx_irq_enable(eth, MTK_RX_DONE_INT);\n+\n+\tif (napi_complete(napi))\n+\t\tmtk_rx_irq_enable(eth, MTK_RX_DONE_INT);\n \n \treturn rx_done + budget - remain_budget;\n }\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/610-v5.13-49-net-ethernet-mtk_eth_soc-rework-NAPI-callbacks.patch",
    "content": "From db2c7b353db3b3f71b55f9ff4627d8a786446fbe Mon Sep 17 00:00:00 2001\nFrom: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com>\nDate: Thu, 22 Apr 2021 22:21:06 -0700\nSubject: [PATCH] net: ethernet: mtk_eth_soc: rework NAPI callbacks\n\nUse napi_complete_done to communicate total TX and RX work done to NAPI.\nCount total RX work up instead of remaining work down for clarity.\nRemove unneeded local variables for clarity. Use do {} while instead of\ngoto for clarity.\n\nSuggested-by: Jakub Kicinski <kuba@kernel.org>\nSigned-off-by: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/ethernet/mediatek/mtk_eth_soc.c | 54 +++++++++------------\n 1 file changed, 24 insertions(+), 30 deletions(-)\n\n--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c\n+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c\n@@ -1517,7 +1517,6 @@ static void mtk_handle_status_irq(struct\n static int mtk_napi_tx(struct napi_struct *napi, int budget)\n {\n \tstruct mtk_eth *eth = container_of(napi, struct mtk_eth, tx_napi);\n-\tu32 status, mask;\n \tint tx_done = 0;\n \n \tif (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA))\n@@ -1526,21 +1525,19 @@ static int mtk_napi_tx(struct napi_struc\n \ttx_done = mtk_poll_tx(eth, budget);\n \n \tif (unlikely(netif_msg_intr(eth))) {\n-\t\tstatus = mtk_r32(eth, eth->tx_int_status_reg);\n-\t\tmask = mtk_r32(eth, eth->tx_int_mask_reg);\n \t\tdev_info(eth->dev,\n-\t\t\t \"done tx %d, intr 0x%08x/0x%x\\n\",\n-\t\t\t tx_done, status, mask);\n+\t\t\t \"done tx %d, intr 0x%08x/0x%x\\n\", tx_done,\n+\t\t\t mtk_r32(eth, eth->tx_int_status_reg),\n+\t\t\t mtk_r32(eth, eth->tx_int_mask_reg));\n \t}\n \n \tif (tx_done == budget)\n \t\treturn budget;\n \n-\tstatus = mtk_r32(eth, eth->tx_int_status_reg);\n-\tif (status & MTK_TX_DONE_INT)\n+\tif (mtk_r32(eth, eth->tx_int_status_reg) & MTK_TX_DONE_INT)\n \t\treturn budget;\n \n-\tif (napi_complete(napi))\n+\tif (napi_complete_done(napi, tx_done))\n \t\tmtk_tx_irq_enable(eth, MTK_TX_DONE_INT);\n \n \treturn tx_done;\n@@ -1549,36 +1546,33 @@ static int mtk_napi_tx(struct napi_struc\n static int mtk_napi_rx(struct napi_struct *napi, int budget)\n {\n \tstruct mtk_eth *eth = container_of(napi, struct mtk_eth, rx_napi);\n-\tu32 status, mask;\n-\tint rx_done = 0;\n-\tint remain_budget = budget;\n+\tint rx_done_total = 0;\n \n \tmtk_handle_status_irq(eth);\n \n-poll_again:\n-\tmtk_w32(eth, MTK_RX_DONE_INT, MTK_PDMA_INT_STATUS);\n-\trx_done = mtk_poll_rx(napi, remain_budget, eth);\n+\tdo {\n+\t\tint rx_done;\n \n-\tif (unlikely(netif_msg_intr(eth))) {\n-\t\tstatus = mtk_r32(eth, MTK_PDMA_INT_STATUS);\n-\t\tmask = mtk_r32(eth, MTK_PDMA_INT_MASK);\n-\t\tdev_info(eth->dev,\n-\t\t\t \"done rx %d, intr 0x%08x/0x%x\\n\",\n-\t\t\t rx_done, status, mask);\n-\t}\n-\tif (rx_done == remain_budget)\n-\t\treturn budget;\n+\t\tmtk_w32(eth, MTK_RX_DONE_INT, MTK_PDMA_INT_STATUS);\n+\t\trx_done = mtk_poll_rx(napi, budget - rx_done_total, eth);\n+\t\trx_done_total += rx_done;\n+\n+\t\tif (unlikely(netif_msg_intr(eth))) {\n+\t\t\tdev_info(eth->dev,\n+\t\t\t\t \"done rx %d, intr 0x%08x/0x%x\\n\", rx_done,\n+\t\t\t\t mtk_r32(eth, MTK_PDMA_INT_STATUS),\n+\t\t\t\t mtk_r32(eth, MTK_PDMA_INT_MASK));\n+\t\t}\n \n-\tstatus = mtk_r32(eth, MTK_PDMA_INT_STATUS);\n-\tif (status & MTK_RX_DONE_INT) {\n-\t\tremain_budget -= rx_done;\n-\t\tgoto poll_again;\n-\t}\n+\t\tif (rx_done_total == budget)\n+\t\t\treturn budget;\n+\n+\t} while (mtk_r32(eth, MTK_PDMA_INT_STATUS) & MTK_RX_DONE_INT);\n \n-\tif (napi_complete(napi))\n+\tif (napi_complete_done(napi, rx_done_total))\n \t\tmtk_rx_irq_enable(eth, MTK_RX_DONE_INT);\n \n-\treturn rx_done + budget - remain_budget;\n+\treturn rx_done_total;\n }\n \n static int mtk_tx_alloc(struct mtk_eth *eth)\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/610-v5.13-50-net-ethernet-mtk_eth_soc-set-PPE-flow-hash-as-skb-ha.patch",
    "content": "From fa817272c37ef78e25dc14e4760ac78a7043a18a Mon Sep 17 00:00:00 2001\nFrom: Felix Fietkau <nbd@nbd.name>\nDate: Thu, 22 Apr 2021 22:21:07 -0700\nSubject: [PATCH] net: ethernet: mtk_eth_soc: set PPE flow hash as skb hash if\n present\n\nThis improves GRO performance\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n[Ilya: Use MTK_RXD4_FOE_ENTRY instead of GENMASK(13, 0)]\nSigned-off-by: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/ethernet/mediatek/mtk_eth_soc.c | 8 ++++++++\n 1 file changed, 8 insertions(+)\n\n--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c\n+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c\n@@ -19,6 +19,7 @@\n #include <linux/interrupt.h>\n #include <linux/pinctrl/devinfo.h>\n #include <linux/phylink.h>\n+#include <linux/jhash.h>\n #include <net/dsa.h>\n \n #include \"mtk_eth_soc.h\"\n@@ -1271,6 +1272,7 @@ static int mtk_poll_rx(struct napi_struc\n \t\tstruct net_device *netdev;\n \t\tunsigned int pktlen;\n \t\tdma_addr_t dma_addr;\n+\t\tu32 hash;\n \t\tint mac;\n \n \t\tring = mtk_get_rx_ring(eth);\n@@ -1340,6 +1342,12 @@ static int mtk_poll_rx(struct napi_struc\n \t\tskb->protocol = eth_type_trans(skb, netdev);\n \t\tbytes += pktlen;\n \n+\t\thash = trxd.rxd4 & MTK_RXD4_FOE_ENTRY;\n+\t\tif (hash != MTK_RXD4_FOE_ENTRY) {\n+\t\t\thash = jhash_1word(hash, 0);\n+\t\t\tskb_set_hash(skb, hash, PKT_HASH_TYPE_L4);\n+\t\t}\n+\n \t\tif (netdev->features & NETIF_F_HW_VLAN_CTAG_RX &&\n \t\t    (trxd.rxd2 & RX_DMA_VTAG))\n \t\t\t__vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/610-v5.13-51-net-ethernet-mtk_eth_soc-use-iopoll.h-macro-for-DMA-.patch",
    "content": "From 3bc8e0aff23be0526af0dbc7973a8866a08d73f1 Mon Sep 17 00:00:00 2001\nFrom: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com>\nDate: Thu, 22 Apr 2021 22:21:08 -0700\nSubject: [PATCH] net: ethernet: mtk_eth_soc: use iopoll.h macro for DMA init\n\nReplace a tight busy-wait loop without a pause with a standard\nreadx_poll_timeout_atomic routine with a 5 us poll period.\n\nTested by booting a MT7621 device to ensure the driver initializes\nproperly.\n\nSigned-off-by: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com>\nReviewed-by: Andrew Lunn <andrew@lunn.ch>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/ethernet/mediatek/mtk_eth_soc.c | 29 +++++++++------------\n drivers/net/ethernet/mediatek/mtk_eth_soc.h |  2 +-\n 2 files changed, 14 insertions(+), 17 deletions(-)\n\n--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c\n+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c\n@@ -2054,25 +2054,22 @@ static int mtk_set_features(struct net_d\n /* wait for DMA to finish whatever it is doing before we start using it again */\n static int mtk_dma_busy_wait(struct mtk_eth *eth)\n {\n-\tunsigned long t_start = jiffies;\n+\tunsigned int reg;\n+\tint ret;\n+\tu32 val;\n \n-\twhile (1) {\n-\t\tif (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {\n-\t\t\tif (!(mtk_r32(eth, MTK_QDMA_GLO_CFG) &\n-\t\t\t      (MTK_RX_DMA_BUSY | MTK_TX_DMA_BUSY)))\n-\t\t\t\treturn 0;\n-\t\t} else {\n-\t\t\tif (!(mtk_r32(eth, MTK_PDMA_GLO_CFG) &\n-\t\t\t      (MTK_RX_DMA_BUSY | MTK_TX_DMA_BUSY)))\n-\t\t\t\treturn 0;\n-\t\t}\n+\tif (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA))\n+\t\treg = MTK_QDMA_GLO_CFG;\n+\telse\n+\t\treg = MTK_PDMA_GLO_CFG;\n \n-\t\tif (time_after(jiffies, t_start + MTK_DMA_BUSY_TIMEOUT))\n-\t\t\tbreak;\n-\t}\n+\tret = readx_poll_timeout_atomic(__raw_readl, eth->base + reg, val,\n+\t\t\t\t\t!(val & (MTK_RX_DMA_BUSY | MTK_TX_DMA_BUSY)),\n+\t\t\t\t\t5, MTK_DMA_BUSY_TIMEOUT_US);\n+\tif (ret)\n+\t\tdev_err(eth->dev, \"DMA init timeout\\n\");\n \n-\tdev_err(eth->dev, \"DMA init timeout\\n\");\n-\treturn -1;\n+\treturn ret;\n }\n \n static int mtk_dma_init(struct mtk_eth *eth)\n--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h\n+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h\n@@ -213,7 +213,7 @@\n #define MTK_TX_DMA_BUSY\t\tBIT(1)\n #define MTK_RX_DMA_EN\t\tBIT(2)\n #define MTK_TX_DMA_EN\t\tBIT(0)\n-#define MTK_DMA_BUSY_TIMEOUT\tHZ\n+#define MTK_DMA_BUSY_TIMEOUT_US\t1000000\n \n /* QDMA Reset Index Register */\n #define MTK_QDMA_RST_IDX\t0x1A08\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/610-v5.13-52-net-ethernet-mtk_eth_soc-missing-mutex.patch",
    "content": "From: Pablo Neira Ayuso <pablo@netfilter.org>\nDate: Sun, 18 Apr 2021 23:11:44 +0200\nSubject: [PATCH] net: ethernet: mtk_eth_soc: missing mutex\n\nPatch 2ed37183abb7 (\"netfilter: flowtable: separate replace, destroy and\nstats to different workqueues\") splits the workqueue per event type. Add\na mutex to serialize updates.\n\nFixes: 502e84e2382d (\"net: ethernet: mtk_eth_soc: add flow offloading support\")\nReported-by: Frank Wunderlich <frank-w@public-files.de>\nSigned-off-by: Pablo Neira Ayuso <pablo@netfilter.org>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n\n--- a/drivers/net/ethernet/mediatek/mtk_ppe_offload.c\n+++ b/drivers/net/ethernet/mediatek/mtk_ppe_offload.c\n@@ -392,6 +392,8 @@ mtk_flow_offload_stats(struct mtk_eth *e\n \treturn 0;\n }\n \n+static DEFINE_MUTEX(mtk_flow_offload_mutex);\n+\n static int\n mtk_eth_setup_tc_block_cb(enum tc_setup_type type, void *type_data, void *cb_priv)\n {\n@@ -399,6 +401,7 @@ mtk_eth_setup_tc_block_cb(enum tc_setup_\n \tstruct net_device *dev = cb_priv;\n \tstruct mtk_mac *mac = netdev_priv(dev);\n \tstruct mtk_eth *eth = mac->hw;\n+\tint err;\n \n \tif (!tc_can_offload(dev))\n \t\treturn -EOPNOTSUPP;\n@@ -406,18 +409,24 @@ mtk_eth_setup_tc_block_cb(enum tc_setup_\n \tif (type != TC_SETUP_CLSFLOWER)\n \t\treturn -EOPNOTSUPP;\n \n+\tmutex_lock(&mtk_flow_offload_mutex);\n \tswitch (cls->command) {\n \tcase FLOW_CLS_REPLACE:\n-\t\treturn mtk_flow_offload_replace(eth, cls);\n+\t\terr = mtk_flow_offload_replace(eth, cls);\n+\t\tbreak;\n \tcase FLOW_CLS_DESTROY:\n-\t\treturn mtk_flow_offload_destroy(eth, cls);\n+\t\terr = mtk_flow_offload_destroy(eth, cls);\n+\t\tbreak;\n \tcase FLOW_CLS_STATS:\n-\t\treturn mtk_flow_offload_stats(eth, cls);\n+\t\terr = mtk_flow_offload_stats(eth, cls);\n+\t\tbreak;\n \tdefault:\n-\t\treturn -EOPNOTSUPP;\n+\t\terr = -EOPNOTSUPP;\n+\t\tbreak;\n \t}\n+\tmutex_unlock(&mtk_flow_offload_mutex);\n \n-\treturn 0;\n+\treturn err;\n }\n \n static int\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/610-v5.13-53-net-ethernet-mtk_eth_soc-handle-VLAN-pop-action.patch",
    "content": "From: Pablo Neira Ayuso <pablo@netfilter.org>\nDate: Sun, 18 Apr 2021 23:11:45 +0200\nSubject: [PATCH] net: ethernet: mtk_eth_soc: handle VLAN pop action\n\nDo not hit EOPNOTSUPP when flowtable offload provides a VLAN pop action.\n\nFixes: efce49dfe6a8 (\"netfilter: flowtable: add vlan pop action offload support\")\nSigned-off-by: Pablo Neira Ayuso <pablo@netfilter.org>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n\n--- a/drivers/net/ethernet/mediatek/mtk_ppe_offload.c\n+++ b/drivers/net/ethernet/mediatek/mtk_ppe_offload.c\n@@ -233,6 +233,8 @@ mtk_flow_offload_replace(struct mtk_eth\n \t\t\tdata.vlan.proto = act->vlan.proto;\n \t\t\tdata.vlan.num++;\n \t\t\tbreak;\n+\t\tcase FLOW_ACTION_VLAN_POP:\n+\t\t\tbreak;\n \t\tcase FLOW_ACTION_PPPOE_PUSH:\n \t\t\tif (data.pppoe.num == 1)\n \t\t\t\treturn -EOPNOTSUPP;\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/610-v5.13-54-netfilter-flowtable-dst_check-from-garbage-collector.patch",
    "content": "From: Pablo Neira Ayuso <pablo@netfilter.org>\nDate: Sun, 28 Mar 2021 23:08:55 +0200\nSubject: [PATCH] netfilter: flowtable: dst_check() from garbage collector path\n\nMove dst_check() to the garbage collector path. Stale routes trigger the\nflow entry teardown state which makes affected flows go back to the\nclassic forwarding path to re-evaluate flow offloading.\n\nIPv6 requires the dst cookie to work, store it in the flow_tuple,\notherwise dst_check() always fails.\n\nFixes: e5075c0badaa (\"netfilter: flowtable: call dst_check() to fall back to classic forwarding\")\nSigned-off-by: Pablo Neira Ayuso <pablo@netfilter.org>\n---\n\n--- a/include/net/netfilter/nf_flow_table.h\n+++ b/include/net/netfilter/nf_flow_table.h\n@@ -129,7 +129,10 @@ struct flow_offload_tuple {\n \t\t\t\t\tin_vlan_ingress:2;\n \tu16\t\t\t\tmtu;\n \tunion {\n-\t\tstruct dst_entry\t*dst_cache;\n+\t\tstruct {\n+\t\t\tstruct dst_entry *dst_cache;\n+\t\t\tu32\t\tdst_cookie;\n+\t\t};\n \t\tstruct {\n \t\t\tu32\t\tifidx;\n \t\t\tu32\t\thw_ifidx;\n--- a/net/netfilter/nf_flow_table_core.c\n+++ b/net/netfilter/nf_flow_table_core.c\n@@ -74,6 +74,18 @@ err_ct_refcnt:\n }\n EXPORT_SYMBOL_GPL(flow_offload_alloc);\n \n+static u32 flow_offload_dst_cookie(struct flow_offload_tuple *flow_tuple)\n+{\n+\tconst struct rt6_info *rt;\n+\n+\tif (flow_tuple->l3proto == NFPROTO_IPV6) {\n+\t\trt = (const struct rt6_info *)flow_tuple->dst_cache;\n+\t\treturn rt6_get_cookie(rt);\n+\t}\n+\n+\treturn 0;\n+}\n+\n static int flow_offload_fill_route(struct flow_offload *flow,\n \t\t\t\t   const struct nf_flow_route *route,\n \t\t\t\t   enum flow_offload_tuple_dir dir)\n@@ -116,6 +128,7 @@ static int flow_offload_fill_route(struc\n \t\t\treturn -1;\n \n \t\tflow_tuple->dst_cache = dst;\n+\t\tflow_tuple->dst_cookie = flow_offload_dst_cookie(flow_tuple);\n \t\tbreak;\n \t}\n \tflow_tuple->xmit_type = route->tuple[dir].xmit_type;\n@@ -389,11 +402,33 @@ nf_flow_table_iterate(struct nf_flowtabl\n \treturn err;\n }\n \n+static bool flow_offload_stale_dst(struct flow_offload_tuple *tuple)\n+{\n+\tstruct dst_entry *dst;\n+\n+\tif (tuple->xmit_type == FLOW_OFFLOAD_XMIT_NEIGH ||\n+\t    tuple->xmit_type == FLOW_OFFLOAD_XMIT_XFRM) {\n+\t\tdst = tuple->dst_cache;\n+\t\tif (!dst_check(dst, tuple->dst_cookie))\n+\t\t\treturn true;\n+\t}\n+\n+\treturn false;\n+}\n+\n+static bool nf_flow_has_stale_dst(struct flow_offload *flow)\n+{\n+\treturn flow_offload_stale_dst(&flow->tuplehash[FLOW_OFFLOAD_DIR_ORIGINAL].tuple) ||\n+\t       flow_offload_stale_dst(&flow->tuplehash[FLOW_OFFLOAD_DIR_REPLY].tuple);\n+}\n+\n static void nf_flow_offload_gc_step(struct flow_offload *flow, void *data)\n {\n \tstruct nf_flowtable *flow_table = data;\n \n-\tif (nf_flow_has_expired(flow) || nf_ct_is_dying(flow->ct))\n+\tif (nf_flow_has_expired(flow) ||\n+\t    nf_ct_is_dying(flow->ct) ||\n+\t    nf_flow_has_stale_dst(flow))\n \t\tset_bit(NF_FLOW_TEARDOWN, &flow->flags);\n \n \tif (test_bit(NF_FLOW_TEARDOWN, &flow->flags)) {\n--- a/net/netfilter/nf_flow_table_ip.c\n+++ b/net/netfilter/nf_flow_table_ip.c\n@@ -364,15 +364,6 @@ nf_flow_offload_ip_hook(void *priv, stru\n \tif (nf_flow_state_check(flow, iph->protocol, skb, thoff))\n \t\treturn NF_ACCEPT;\n \n-\tif (tuplehash->tuple.xmit_type == FLOW_OFFLOAD_XMIT_NEIGH ||\n-\t    tuplehash->tuple.xmit_type == FLOW_OFFLOAD_XMIT_XFRM) {\n-\t\trt = (struct rtable *)tuplehash->tuple.dst_cache;\n-\t\tif (!dst_check(&rt->dst, 0)) {\n-\t\t\tflow_offload_teardown(flow);\n-\t\t\treturn NF_ACCEPT;\n-\t\t}\n-\t}\n-\n \tif (skb_try_make_writable(skb, thoff + hdrsize))\n \t\treturn NF_DROP;\n \n@@ -391,6 +382,7 @@ nf_flow_offload_ip_hook(void *priv, stru\n \t\tnf_ct_acct_update(flow->ct, tuplehash->tuple.dir, skb->len);\n \n \tif (unlikely(tuplehash->tuple.xmit_type == FLOW_OFFLOAD_XMIT_XFRM)) {\n+\t\trt = (struct rtable *)tuplehash->tuple.dst_cache;\n \t\tmemset(skb->cb, 0, sizeof(struct inet_skb_parm));\n \t\tIPCB(skb)->iif = skb->dev->ifindex;\n \t\tIPCB(skb)->flags = IPSKB_FORWARDED;\n@@ -399,6 +391,7 @@ nf_flow_offload_ip_hook(void *priv, stru\n \n \tswitch (tuplehash->tuple.xmit_type) {\n \tcase FLOW_OFFLOAD_XMIT_NEIGH:\n+\t\trt = (struct rtable *)tuplehash->tuple.dst_cache;\n \t\toutdev = rt->dst.dev;\n \t\tskb->dev = outdev;\n \t\tnexthop = rt_nexthop(rt, flow->tuplehash[!dir].tuple.src_v4.s_addr);\n@@ -607,15 +600,6 @@ nf_flow_offload_ipv6_hook(void *priv, st\n \tif (nf_flow_state_check(flow, ip6h->nexthdr, skb, thoff))\n \t\treturn NF_ACCEPT;\n \n-\tif (tuplehash->tuple.xmit_type == FLOW_OFFLOAD_XMIT_NEIGH ||\n-\t    tuplehash->tuple.xmit_type == FLOW_OFFLOAD_XMIT_XFRM) {\n-\t\trt = (struct rt6_info *)tuplehash->tuple.dst_cache;\n-\t\tif (!dst_check(&rt->dst, 0)) {\n-\t\t\tflow_offload_teardown(flow);\n-\t\t\treturn NF_ACCEPT;\n-\t\t}\n-\t}\n-\n \tif (skb_try_make_writable(skb, thoff + hdrsize))\n \t\treturn NF_DROP;\n \n@@ -633,6 +617,7 @@ nf_flow_offload_ipv6_hook(void *priv, st\n \t\tnf_ct_acct_update(flow->ct, tuplehash->tuple.dir, skb->len);\n \n \tif (unlikely(tuplehash->tuple.xmit_type == FLOW_OFFLOAD_XMIT_XFRM)) {\n+\t\trt = (struct rt6_info *)tuplehash->tuple.dst_cache;\n \t\tmemset(skb->cb, 0, sizeof(struct inet6_skb_parm));\n \t\tIP6CB(skb)->iif = skb->dev->ifindex;\n \t\tIP6CB(skb)->flags = IP6SKB_FORWARDED;\n@@ -641,6 +626,7 @@ nf_flow_offload_ipv6_hook(void *priv, st\n \n \tswitch (tuplehash->tuple.xmit_type) {\n \tcase FLOW_OFFLOAD_XMIT_NEIGH:\n+\t\trt = (struct rt6_info *)tuplehash->tuple.dst_cache;\n \t\toutdev = rt->dst.dev;\n \t\tskb->dev = outdev;\n \t\tnexthop = rt6_nexthop(rt, &flow->tuplehash[!dir].tuple.src_v6);\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/610-v5.13-55-netfilter-conntrack-Introduce-tcp-offload-timeout-co.patch",
    "content": "From: Oz Shlomo <ozsh@nvidia.com>\nDate: Thu, 3 Jun 2021 15:12:33 +0300\nSubject: [PATCH] netfilter: conntrack: Introduce tcp offload timeout\n configuration\n\nTCP connections may be offloaded from nf conntrack to nf flow table.\nOffloaded connections are aged after 30 seconds of inactivity.\nOnce aged, ownership is returned to conntrack with a hard coded pickup\ntime of 120 seconds, after which the connection may be deleted.\neted. The current aging intervals may be too aggressive for some users.\n\nProvide users with the ability to control the nf flow table offload\naging and pickup time intervals via sysctl parameter as a pre-step for\nconfiguring the nf flow table GC timeout intervals.\n\nSigned-off-by: Oz Shlomo <ozsh@nvidia.com>\nReviewed-by: Paul Blakey <paulb@nvidia.com>\nSigned-off-by: Pablo Neira Ayuso <pablo@netfilter.org>\n---\n\n--- a/include/net/netns/conntrack.h\n+++ b/include/net/netns/conntrack.h\n@@ -27,6 +27,10 @@ struct nf_tcp_net {\n \tint tcp_loose;\n \tint tcp_be_liberal;\n \tint tcp_max_retrans;\n+#if IS_ENABLED(CONFIG_NF_FLOW_TABLE)\n+\tunsigned int offload_timeout;\n+\tunsigned int offload_pickup;\n+#endif\n };\n \n enum udp_conntrack {\n--- a/net/netfilter/nf_conntrack_proto_tcp.c\n+++ b/net/netfilter/nf_conntrack_proto_tcp.c\n@@ -1447,6 +1447,11 @@ void nf_conntrack_tcp_init_net(struct ne\n \ttn->tcp_loose = nf_ct_tcp_loose;\n \ttn->tcp_be_liberal = nf_ct_tcp_be_liberal;\n \ttn->tcp_max_retrans = nf_ct_tcp_max_retrans;\n+\n+#if IS_ENABLED(CONFIG_NF_FLOW_TABLE)\n+\ttn->offload_timeout = 30 * HZ;\n+\ttn->offload_pickup = 120 * HZ;\n+#endif\n }\n \n const struct nf_conntrack_l4proto nf_conntrack_l4proto_tcp =\n--- a/net/netfilter/nf_conntrack_standalone.c\n+++ b/net/netfilter/nf_conntrack_standalone.c\n@@ -567,6 +567,10 @@ enum nf_ct_sysctl_index {\n \tNF_SYSCTL_CT_PROTO_TIMEOUT_TCP_CLOSE,\n \tNF_SYSCTL_CT_PROTO_TIMEOUT_TCP_RETRANS,\n \tNF_SYSCTL_CT_PROTO_TIMEOUT_TCP_UNACK,\n+#if IS_ENABLED(CONFIG_NF_FLOW_TABLE)\n+\tNF_SYSCTL_CT_PROTO_TIMEOUT_TCP_OFFLOAD,\n+\tNF_SYSCTL_CT_PROTO_TIMEOUT_TCP_OFFLOAD_PICKUP,\n+#endif\n \tNF_SYSCTL_CT_PROTO_TCP_LOOSE,\n \tNF_SYSCTL_CT_PROTO_TCP_LIBERAL,\n \tNF_SYSCTL_CT_PROTO_TCP_MAX_RETRANS,\n@@ -758,6 +762,20 @@ static struct ctl_table nf_ct_sysctl_tab\n \t\t.mode\t\t= 0644,\n \t\t.proc_handler\t= proc_dointvec_jiffies,\n \t},\n+#if IS_ENABLED(CONFIG_NF_FLOW_TABLE)\n+\t[NF_SYSCTL_CT_PROTO_TIMEOUT_TCP_OFFLOAD] = {\n+\t\t.procname\t= \"nf_flowtable_tcp_timeout\",\n+\t\t.maxlen\t\t= sizeof(unsigned int),\n+\t\t.mode\t\t= 0644,\n+\t\t.proc_handler\t= proc_dointvec_jiffies,\n+\t},\n+\t[NF_SYSCTL_CT_PROTO_TIMEOUT_TCP_OFFLOAD_PICKUP] = {\n+\t\t.procname\t= \"nf_flowtable_tcp_pickup\",\n+\t\t.maxlen\t\t= sizeof(unsigned int),\n+\t\t.mode\t\t= 0644,\n+\t\t.proc_handler\t= proc_dointvec_jiffies,\n+\t},\n+#endif\n \t[NF_SYSCTL_CT_PROTO_TCP_LOOSE] = {\n \t\t.procname\t= \"nf_conntrack_tcp_loose\",\n \t\t.maxlen\t\t= sizeof(int),\n@@ -967,6 +985,12 @@ static void nf_conntrack_standalone_init\n \tXASSIGN(LIBERAL, &tn->tcp_be_liberal);\n \tXASSIGN(MAX_RETRANS, &tn->tcp_max_retrans);\n #undef XASSIGN\n+\n+#if IS_ENABLED(CONFIG_NF_FLOW_TABLE)\n+\ttable[NF_SYSCTL_CT_PROTO_TIMEOUT_TCP_OFFLOAD].data = &tn->offload_timeout;\n+\ttable[NF_SYSCTL_CT_PROTO_TIMEOUT_TCP_OFFLOAD_PICKUP].data = &tn->offload_pickup;\n+#endif\n+\n }\n \n static void nf_conntrack_standalone_init_sctp_sysctl(struct net *net,\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/610-v5.13-56-netfilter-conntrack-Introduce-udp-offload-timeout-co.patch",
    "content": "From: Oz Shlomo <ozsh@nvidia.com>\nDate: Thu, 3 Jun 2021 15:12:34 +0300\nSubject: [PATCH] netfilter: conntrack: Introduce udp offload timeout\n configuration\n\nUDP connections may be offloaded from nf conntrack to nf flow table.\nOffloaded connections are aged after 30 seconds of inactivity.\nOnce aged, ownership is returned to conntrack with a hard coded pickup\ntime of 30 seconds, after which the connection may be deleted.\neted. The current aging intervals may be too aggressive for some users.\n\nProvide users with the ability to control the nf flow table offload\naging and pickup time intervals via sysctl parameter as a pre-step for\nconfiguring the nf flow table GC timeout intervals.\n\nSigned-off-by: Oz Shlomo <ozsh@nvidia.com>\nReviewed-by: Paul Blakey <paulb@nvidia.com>\nSigned-off-by: Pablo Neira Ayuso <pablo@netfilter.org>\n---\n\n--- a/include/net/netns/conntrack.h\n+++ b/include/net/netns/conntrack.h\n@@ -41,6 +41,10 @@ enum udp_conntrack {\n \n struct nf_udp_net {\n \tunsigned int timeouts[UDP_CT_MAX];\n+#if IS_ENABLED(CONFIG_NF_FLOW_TABLE)\n+\tunsigned int offload_timeout;\n+\tunsigned int offload_pickup;\n+#endif\n };\n \n struct nf_icmp_net {\n--- a/net/netfilter/nf_conntrack_proto_udp.c\n+++ b/net/netfilter/nf_conntrack_proto_udp.c\n@@ -273,6 +273,11 @@ void nf_conntrack_udp_init_net(struct ne\n \n \tfor (i = 0; i < UDP_CT_MAX; i++)\n \t\tun->timeouts[i] = udp_timeouts[i];\n+\n+#if IS_ENABLED(CONFIG_NF_FLOW_TABLE)\n+\tun->offload_timeout = 30 * HZ;\n+\tun->offload_pickup = 30 * HZ;\n+#endif\n }\n \n const struct nf_conntrack_l4proto nf_conntrack_l4proto_udp =\n--- a/net/netfilter/nf_conntrack_standalone.c\n+++ b/net/netfilter/nf_conntrack_standalone.c\n@@ -576,6 +576,10 @@ enum nf_ct_sysctl_index {\n \tNF_SYSCTL_CT_PROTO_TCP_MAX_RETRANS,\n \tNF_SYSCTL_CT_PROTO_TIMEOUT_UDP,\n \tNF_SYSCTL_CT_PROTO_TIMEOUT_UDP_STREAM,\n+#if IS_ENABLED(CONFIG_NF_FLOW_TABLE)\n+\tNF_SYSCTL_CT_PROTO_TIMEOUT_UDP_OFFLOAD,\n+\tNF_SYSCTL_CT_PROTO_TIMEOUT_UDP_OFFLOAD_PICKUP,\n+#endif\n \tNF_SYSCTL_CT_PROTO_TIMEOUT_ICMP,\n \tNF_SYSCTL_CT_PROTO_TIMEOUT_ICMPV6,\n #ifdef CONFIG_NF_CT_PROTO_SCTP\n@@ -810,6 +814,20 @@ static struct ctl_table nf_ct_sysctl_tab\n \t\t.mode\t\t= 0644,\n \t\t.proc_handler\t= proc_dointvec_jiffies,\n \t},\n+#if IS_ENABLED(CONFIG_NFT_FLOW_OFFLOAD)\n+\t[NF_SYSCTL_CT_PROTO_TIMEOUT_UDP_OFFLOAD] = {\n+\t\t.procname\t= \"nf_flowtable_udp_timeout\",\n+\t\t.maxlen\t\t= sizeof(unsigned int),\n+\t\t.mode\t\t= 0644,\n+\t\t.proc_handler\t= proc_dointvec_jiffies,\n+\t},\n+\t[NF_SYSCTL_CT_PROTO_TIMEOUT_UDP_OFFLOAD_PICKUP] = {\n+\t\t.procname\t= \"nf_flowtable_udp_pickup\",\n+\t\t.maxlen\t\t= sizeof(unsigned int),\n+\t\t.mode\t\t= 0644,\n+\t\t.proc_handler\t= proc_dointvec_jiffies,\n+\t},\n+#endif\n \t[NF_SYSCTL_CT_PROTO_TIMEOUT_ICMP] = {\n \t\t.procname\t= \"nf_conntrack_icmp_timeout\",\n \t\t.maxlen\t\t= sizeof(unsigned int),\n@@ -1078,6 +1096,10 @@ static int nf_conntrack_standalone_init_\n \ttable[NF_SYSCTL_CT_PROTO_TIMEOUT_ICMPV6].data = &nf_icmpv6_pernet(net)->timeout;\n \ttable[NF_SYSCTL_CT_PROTO_TIMEOUT_UDP].data = &un->timeouts[UDP_CT_UNREPLIED];\n \ttable[NF_SYSCTL_CT_PROTO_TIMEOUT_UDP_STREAM].data = &un->timeouts[UDP_CT_REPLIED];\n+#if IS_ENABLED(CONFIG_NF_FLOW_TABLE)\n+\ttable[NF_SYSCTL_CT_PROTO_TIMEOUT_UDP_OFFLOAD].data = &un->offload_timeout;\n+\ttable[NF_SYSCTL_CT_PROTO_TIMEOUT_UDP_OFFLOAD_PICKUP].data = &un->offload_pickup;\n+#endif\n \n \tnf_conntrack_standalone_init_tcp_sysctl(net, table);\n \tnf_conntrack_standalone_init_sctp_sysctl(net, table);\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/610-v5.13-57-netfilter-flowtable-Set-offload-timeouts-according-t.patch",
    "content": "From: Oz Shlomo <ozsh@nvidia.com>\nDate: Thu, 3 Jun 2021 15:12:35 +0300\nSubject: [PATCH] netfilter: flowtable: Set offload timeouts according to proto\n values\n\nCurrently the aging period for tcp/udp connections is hard coded to\n30 seconds. Aged tcp/udp connections configure a hard coded 120/30\nseconds pickup timeout for conntrack.\nThis configuration may be too aggressive or permissive for some users.\n\nDynamically configure the nf flow table GC timeout intervals according\nto the user defined values.\n\nSigned-off-by: Oz Shlomo <ozsh@nvidia.com>\nReviewed-by: Paul Blakey <paulb@nvidia.com>\nSigned-off-by: Pablo Neira Ayuso <pablo@netfilter.org>\n---\n\n--- a/include/net/netfilter/nf_flow_table.h\n+++ b/include/net/netfilter/nf_flow_table.h\n@@ -174,6 +174,8 @@ struct flow_offload {\n #define NF_FLOW_TIMEOUT (30 * HZ)\n #define nf_flowtable_time_stamp\t(u32)jiffies\n \n+unsigned long flow_offload_get_timeout(struct flow_offload *flow);\n+\n static inline __s32 nf_flow_timeout_delta(unsigned int timeout)\n {\n \treturn (__s32)(timeout - nf_flowtable_time_stamp);\n--- a/net/netfilter/nf_flow_table_core.c\n+++ b/net/netfilter/nf_flow_table_core.c\n@@ -175,12 +175,10 @@ static void flow_offload_fixup_tcp(struc\n \ttcp->seen[1].td_maxwin = 0;\n }\n \n-#define NF_FLOWTABLE_TCP_PICKUP_TIMEOUT\t(120 * HZ)\n-#define NF_FLOWTABLE_UDP_PICKUP_TIMEOUT\t(30 * HZ)\n-\n static void flow_offload_fixup_ct_timeout(struct nf_conn *ct)\n {\n \tconst struct nf_conntrack_l4proto *l4proto;\n+\tstruct net *net = nf_ct_net(ct);\n \tint l4num = nf_ct_protonum(ct);\n \tunsigned int timeout;\n \n@@ -188,12 +186,17 @@ static void flow_offload_fixup_ct_timeou\n \tif (!l4proto)\n \t\treturn;\n \n-\tif (l4num == IPPROTO_TCP)\n-\t\ttimeout = NF_FLOWTABLE_TCP_PICKUP_TIMEOUT;\n-\telse if (l4num == IPPROTO_UDP)\n-\t\ttimeout = NF_FLOWTABLE_UDP_PICKUP_TIMEOUT;\n-\telse\n+\tif (l4num == IPPROTO_TCP) {\n+\t\tstruct nf_tcp_net *tn = nf_tcp_pernet(net);\n+\n+\t\ttimeout = tn->offload_pickup;\n+\t} else if (l4num == IPPROTO_UDP) {\n+\t\tstruct nf_udp_net *tn = nf_udp_pernet(net);\n+\n+\t\ttimeout = tn->offload_pickup;\n+\t} else {\n \t\treturn;\n+\t}\n \n \tif (nf_flow_timeout_delta(READ_ONCE(ct->timeout)) > (__s32)timeout)\n \t\tWRITE_ONCE(ct->timeout, nfct_time_stamp + timeout);\n@@ -265,11 +268,35 @@ static const struct rhashtable_params nf\n \t.automatic_shrinking\t= true,\n };\n \n+unsigned long flow_offload_get_timeout(struct flow_offload *flow)\n+{\n+\tconst struct nf_conntrack_l4proto *l4proto;\n+\tunsigned long timeout = NF_FLOW_TIMEOUT;\n+\tstruct net *net = nf_ct_net(flow->ct);\n+\tint l4num = nf_ct_protonum(flow->ct);\n+\n+\tl4proto = nf_ct_l4proto_find(l4num);\n+\tif (!l4proto)\n+\t\treturn timeout;\n+\n+\tif (l4num == IPPROTO_TCP) {\n+\t\tstruct nf_tcp_net *tn = nf_tcp_pernet(net);\n+\n+\t\ttimeout = tn->offload_timeout;\n+\t} else if (l4num == IPPROTO_UDP) {\n+\t\tstruct nf_udp_net *tn = nf_udp_pernet(net);\n+\n+\t\ttimeout = tn->offload_timeout;\n+\t}\n+\n+\treturn timeout;\n+}\n+\n int flow_offload_add(struct nf_flowtable *flow_table, struct flow_offload *flow)\n {\n \tint err;\n \n-\tflow->timeout = nf_flowtable_time_stamp + NF_FLOW_TIMEOUT;\n+\tflow->timeout = nf_flowtable_time_stamp + flow_offload_get_timeout(flow);\n \n \terr = rhashtable_insert_fast(&flow_table->rhashtable,\n \t\t\t\t     &flow->tuplehash[0].node,\n@@ -301,7 +328,7 @@ EXPORT_SYMBOL_GPL(flow_offload_add);\n void flow_offload_refresh(struct nf_flowtable *flow_table,\n \t\t\t  struct flow_offload *flow)\n {\n-\tflow->timeout = nf_flowtable_time_stamp + NF_FLOW_TIMEOUT;\n+\tflow->timeout = nf_flowtable_time_stamp + flow_offload_get_timeout(flow);\n \n \tif (likely(!nf_flowtable_hw_offload(flow_table)))\n \t\treturn;\n--- a/net/netfilter/nf_flow_table_offload.c\n+++ b/net/netfilter/nf_flow_table_offload.c\n@@ -885,7 +885,7 @@ static void flow_offload_work_stats(stru\n \n \tlastused = max_t(u64, stats[0].lastused, stats[1].lastused);\n \toffload->flow->timeout = max_t(u64, offload->flow->timeout,\n-\t\t\t\t       lastused + NF_FLOW_TIMEOUT);\n+\t\t\t\t       lastused + flow_offload_get_timeout(offload->flow));\n \n \tif (offload->flowtable->flags & NF_FLOWTABLE_COUNTER) {\n \t\tif (stats[0].pkts)\n@@ -989,7 +989,7 @@ void nf_flow_offload_stats(struct nf_flo\n \t__s32 delta;\n \n \tdelta = nf_flow_timeout_delta(flow->timeout);\n-\tif ((delta >= (9 * NF_FLOW_TIMEOUT) / 10))\n+\tif ((delta >= (9 * flow_offload_get_timeout(flow)) / 10))\n \t\treturn;\n \n \toffload = nf_flow_offload_work_alloc(flowtable, flow, FLOW_CLS_STATS);\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/610-v5.15-58-netfilter-flowtable-avoid-possible-false-sharing.patch",
    "content": "From: Pablo Neira Ayuso <pablo@netfilter.org>\nDate: Sat, 17 Jul 2021 10:10:29 +0200\nSubject: [PATCH] netfilter: flowtable: avoid possible false sharing\n\nThe flowtable follows the same timeout approach as conntrack, use the\nsame idiom as in cc16921351d8 (\"netfilter: conntrack: avoid same-timeout\nupdate\") but also include the fix provided by e37542ba111f (\"netfilter:\nconntrack: avoid possible false sharing\").\n\nSigned-off-by: Pablo Neira Ayuso <pablo@netfilter.org>\n---\n\n--- a/net/netfilter/nf_flow_table_core.c\n+++ b/net/netfilter/nf_flow_table_core.c\n@@ -328,7 +328,11 @@ EXPORT_SYMBOL_GPL(flow_offload_add);\n void flow_offload_refresh(struct nf_flowtable *flow_table,\n \t\t\t  struct flow_offload *flow)\n {\n-\tflow->timeout = nf_flowtable_time_stamp + flow_offload_get_timeout(flow);\n+\tu32 timeout;\n+\n+\ttimeout = nf_flowtable_time_stamp + flow_offload_get_timeout(flow);\n+\tif (READ_ONCE(flow->timeout) != timeout)\n+\t\tWRITE_ONCE(flow->timeout, timeout);\n \n \tif (likely(!nf_flowtable_hw_offload(flow_table)))\n \t\treturn;\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/611-v5.12-net-ethernet-mediatek-support-setting-MTU.patch",
    "content": "From 4fd59792097a6b2fb949d41264386a7ecade469e Mon Sep 17 00:00:00 2001\nFrom: DENG Qingfang <dqfext@gmail.com>\nDate: Mon, 25 Jan 2021 12:20:46 +0800\nSubject: [PATCH] net: ethernet: mediatek: support setting MTU\n\nMT762x HW, except for MT7628, supports frame length up to 2048\n(maximum length on GDM), so allow setting MTU up to 2030.\n\nAlso set the default frame length to the hardware default 1518.\n\nSigned-off-by: DENG Qingfang <dqfext@gmail.com>\nReviewed-by: Andrew Lunn <andrew@lunn.ch>\nLink: https://lore.kernel.org/r/20210125042046.5599-1-dqfext@gmail.com\nSigned-off-by: Jakub Kicinski <kuba@kernel.org>\n---\n drivers/net/ethernet/mediatek/mtk_eth_soc.c | 43 ++++++++++++++++++---\n drivers/net/ethernet/mediatek/mtk_eth_soc.h | 12 ++++--\n 2 files changed, 47 insertions(+), 8 deletions(-)\n\n--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c\n+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c\n@@ -355,7 +355,7 @@ static void mtk_mac_config(struct phylin\n \t/* Setup gmac */\n \tmcr_cur = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id));\n \tmcr_new = mcr_cur;\n-\tmcr_new |= MAC_MCR_MAX_RX_1536 | MAC_MCR_IPG_CFG | MAC_MCR_FORCE_MODE |\n+\tmcr_new |= MAC_MCR_IPG_CFG | MAC_MCR_FORCE_MODE |\n \t\t   MAC_MCR_BACKOFF_EN | MAC_MCR_BACKPR_EN | MAC_MCR_FORCE_LINK;\n \n \t/* Only update control register when needed! */\n@@ -782,8 +782,8 @@ static void mtk_get_stats64(struct net_d\n static inline int mtk_max_frag_size(int mtu)\n {\n \t/* make sure buf_size will be at least MTK_MAX_RX_LENGTH */\n-\tif (mtu + MTK_RX_ETH_HLEN < MTK_MAX_RX_LENGTH)\n-\t\tmtu = MTK_MAX_RX_LENGTH - MTK_RX_ETH_HLEN;\n+\tif (mtu + MTK_RX_ETH_HLEN < MTK_MAX_RX_LENGTH_2K)\n+\t\tmtu = MTK_MAX_RX_LENGTH_2K - MTK_RX_ETH_HLEN;\n \n \treturn SKB_DATA_ALIGN(MTK_RX_HLEN + mtu) +\n \t\tSKB_DATA_ALIGN(sizeof(struct skb_shared_info));\n@@ -794,7 +794,7 @@ static inline int mtk_max_buf_size(int f\n \tint buf_size = frag_size - NET_SKB_PAD - NET_IP_ALIGN -\n \t\t       SKB_DATA_ALIGN(sizeof(struct skb_shared_info));\n \n-\tWARN_ON(buf_size < MTK_MAX_RX_LENGTH);\n+\tWARN_ON(buf_size < MTK_MAX_RX_LENGTH_2K);\n \n \treturn buf_size;\n }\n@@ -2606,6 +2606,35 @@ static void mtk_uninit(struct net_device\n \tmtk_rx_irq_disable(eth, ~0);\n }\n \n+static int mtk_change_mtu(struct net_device *dev, int new_mtu)\n+{\n+\tint length = new_mtu + MTK_RX_ETH_HLEN;\n+\tstruct mtk_mac *mac = netdev_priv(dev);\n+\tstruct mtk_eth *eth = mac->hw;\n+\tu32 mcr_cur, mcr_new;\n+\n+\tif (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) {\n+\t\tmcr_cur = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id));\n+\t\tmcr_new = mcr_cur & ~MAC_MCR_MAX_RX_MASK;\n+\n+\t\tif (length <= 1518)\n+\t\t\tmcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_1518);\n+\t\telse if (length <= 1536)\n+\t\t\tmcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_1536);\n+\t\telse if (length <= 1552)\n+\t\t\tmcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_1552);\n+\t\telse\n+\t\t\tmcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_2048);\n+\n+\t\tif (mcr_new != mcr_cur)\n+\t\t\tmtk_w32(mac->hw, mcr_new, MTK_MAC_MCR(mac->id));\n+\t}\n+\n+\tdev->mtu = new_mtu;\n+\n+\treturn 0;\n+}\n+\n static int mtk_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)\n {\n \tstruct mtk_mac *mac = netdev_priv(dev);\n@@ -2902,6 +2931,7 @@ static const struct net_device_ops mtk_n\n \t.ndo_set_mac_address\t= mtk_set_mac_address,\n \t.ndo_validate_addr\t= eth_validate_addr,\n \t.ndo_do_ioctl\t\t= mtk_do_ioctl,\n+\t.ndo_change_mtu\t\t= mtk_change_mtu,\n \t.ndo_tx_timeout\t\t= mtk_tx_timeout,\n \t.ndo_get_stats64        = mtk_get_stats64,\n \t.ndo_fix_features\t= mtk_fix_features,\n@@ -3004,7 +3034,10 @@ static int mtk_add_mac(struct mtk_eth *e\n \teth->netdev[id]->irq = eth->irq[0];\n \teth->netdev[id]->dev.of_node = np;\n \n-\teth->netdev[id]->max_mtu = MTK_MAX_RX_LENGTH - MTK_RX_ETH_HLEN;\n+\tif (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628))\n+\t\teth->netdev[id]->max_mtu = MTK_MAX_RX_LENGTH - MTK_RX_ETH_HLEN;\n+\telse\n+\t\teth->netdev[id]->max_mtu = MTK_MAX_RX_LENGTH_2K - MTK_RX_ETH_HLEN;\n \n \treturn 0;\n \n--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h\n+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h\n@@ -20,12 +20,13 @@\n #include \"mtk_ppe.h\"\n \n #define MTK_QDMA_PAGE_SIZE\t2048\n-#define\tMTK_MAX_RX_LENGTH\t1536\n+#define MTK_MAX_RX_LENGTH\t1536\n+#define MTK_MAX_RX_LENGTH_2K\t2048\n #define MTK_TX_DMA_BUF_LEN\t0x3fff\n #define MTK_DMA_SIZE\t\t512\n #define MTK_NAPI_WEIGHT\t\t64\n #define MTK_MAC_COUNT\t\t2\n-#define MTK_RX_ETH_HLEN\t\t(VLAN_ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN)\n+#define MTK_RX_ETH_HLEN\t\t(ETH_HLEN + ETH_FCS_LEN)\n #define MTK_RX_HLEN\t\t(NET_SKB_PAD + MTK_RX_ETH_HLEN + NET_IP_ALIGN)\n #define MTK_DMA_DUMMY_DESC\t0xffffffff\n #define MTK_DEFAULT_MSG_ENABLE\t(NETIF_MSG_DRV | \\\n@@ -352,7 +353,12 @@\n \n /* Mac control registers */\n #define MTK_MAC_MCR(x)\t\t(0x10100 + (x * 0x100))\n-#define MAC_MCR_MAX_RX_1536\tBIT(24)\n+#define MAC_MCR_MAX_RX_MASK\tGENMASK(25, 24)\n+#define MAC_MCR_MAX_RX(_x)\t(MAC_MCR_MAX_RX_MASK & ((_x) << 24))\n+#define MAC_MCR_MAX_RX_1518\t0x0\n+#define MAC_MCR_MAX_RX_1536\t0x1\n+#define MAC_MCR_MAX_RX_1552\t0x2\n+#define MAC_MCR_MAX_RX_2048\t0x3\n #define MAC_MCR_IPG_CFG\t\t(BIT(18) | BIT(16))\n #define MAC_MCR_FORCE_MODE\tBIT(15)\n #define MAC_MCR_TX_EN\t\tBIT(14)\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/612-v5.15-netfilter-conntrack-sanitize-table-size-default-sett.patch",
    "content": "From d532bcd0b2699d84d71a0c71d37157ac6eb3be25 Mon Sep 17 00:00:00 2001\nMessage-Id: <d532bcd0b2699d84d71a0c71d37157ac6eb3be25.1645246598.git.plr.vincent@gmail.com>\nFrom: Florian Westphal <fw@strlen.de>\nDate: Thu, 26 Aug 2021 15:54:19 +0200\nSubject: [PATCH] netfilter: conntrack: sanitize table size default settings\n\nconntrack has two distinct table size settings:\nnf_conntrack_max and nf_conntrack_buckets.\n\nThe former limits how many conntrack objects are allowed to exist\nin each namespace.\n\nThe second sets the size of the hashtable.\n\nAs all entries are inserted twice (once for original direction, once for\nreply), there should be at least twice as many buckets in the table than\nthe maximum number of conntrack objects that can exist at the same time.\n\nChange the default multiplier to 1 and increase the chosen bucket sizes.\nThis results in the same nf_conntrack_max settings as before but reduces\nthe average bucket list length.\n\nSigned-off-by: Florian Westphal <fw@strlen.de>\nSigned-off-by: Pablo Neira Ayuso <pablo@netfilter.org>\n---\n .../networking/nf_conntrack-sysctl.rst        | 13 ++++----\n net/netfilter/nf_conntrack_core.c             | 30 +++++++++----------\n 2 files changed, 22 insertions(+), 21 deletions(-)\n\n--- a/Documentation/networking/nf_conntrack-sysctl.rst\n+++ b/Documentation/networking/nf_conntrack-sysctl.rst\n@@ -17,9 +17,8 @@ nf_conntrack_acct - BOOLEAN\n nf_conntrack_buckets - INTEGER\n \tSize of hash table. If not specified as parameter during module\n \tloading, the default size is calculated by dividing total memory\n-\tby 16384 to determine the number of buckets but the hash table will\n-\tnever have fewer than 32 and limited to 16384 buckets. For systems\n-\twith more than 4GB of memory it will be 65536 buckets.\n+\tby 16384 to determine the number of buckets. The hash table will\n+\tnever have fewer than 1024 and never more than 262144 buckets.\n \tThis sysctl is only writeable in the initial net namespace.\n \n nf_conntrack_checksum - BOOLEAN\n@@ -100,8 +99,12 @@ nf_conntrack_log_invalid - INTEGER\n \tLog invalid packets of a type specified by value.\n \n nf_conntrack_max - INTEGER\n-\tSize of connection tracking table.  Default value is\n-\tnf_conntrack_buckets value * 4.\n+        Maximum number of allowed connection tracking entries. This value is set\n+        to nf_conntrack_buckets by default.\n+        Note that connection tracking entries are added to the table twice -- once\n+        for the original direction and once for the reply direction (i.e., with\n+        the reversed address). This means that with default settings a maxed-out\n+        table will have a average hash chain length of 2, not 1.\n \n nf_conntrack_tcp_be_liberal - BOOLEAN\n \t- 0 - disabled (default)\n--- a/net/netfilter/nf_conntrack_core.c\n+++ b/net/netfilter/nf_conntrack_core.c\n@@ -2575,26 +2575,24 @@ int nf_conntrack_init_start(void)\n \t\tspin_lock_init(&nf_conntrack_locks[i]);\n \n \tif (!nf_conntrack_htable_size) {\n-\t\t/* Idea from tcp.c: use 1/16384 of memory.\n-\t\t * On i386: 32MB machine has 512 buckets.\n-\t\t * >= 1GB machines have 16384 buckets.\n-\t\t * >= 4GB machines have 65536 buckets.\n-\t\t */\n \t\tnf_conntrack_htable_size\n \t\t\t= (((nr_pages << PAGE_SHIFT) / 16384)\n \t\t\t   / sizeof(struct hlist_head));\n-\t\tif (nr_pages > (4 * (1024 * 1024 * 1024 / PAGE_SIZE)))\n-\t\t\tnf_conntrack_htable_size = 65536;\n+\t\tif (BITS_PER_LONG >= 64 &&\n+\t\t    nr_pages > (4 * (1024 * 1024 * 1024 / PAGE_SIZE)))\n+\t\t\tnf_conntrack_htable_size = 262144;\n \t\telse if (nr_pages > (1024 * 1024 * 1024 / PAGE_SIZE))\n-\t\t\tnf_conntrack_htable_size = 16384;\n-\t\tif (nf_conntrack_htable_size < 32)\n-\t\t\tnf_conntrack_htable_size = 32;\n+\t\t\tnf_conntrack_htable_size = 65536;\n \n-\t\t/* Use a max. factor of four by default to get the same max as\n-\t\t * with the old struct list_heads. When a table size is given\n-\t\t * we use the old value of 8 to avoid reducing the max.\n-\t\t * entries. */\n-\t\tmax_factor = 4;\n+\t\tif (nf_conntrack_htable_size < 1024)\n+\t\t\tnf_conntrack_htable_size = 1024;\n+\t\t/* Use a max. factor of one by default to keep the average\n+\t\t * hash chain length at 2 entries.  Each entry has to be added\n+\t\t * twice (once for original direction, once for reply).\n+\t\t * When a table size is given we use the old value of 8 to\n+\t\t * avoid implicit reduction of the max entries setting.\n+\t\t */\n+\t\tmax_factor = 1;\n \t}\n \n \tnf_conntrack_hash = nf_ct_alloc_hashtable(&nf_conntrack_htable_size, 1);\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/705-net-phy-at803x-select-correct-page-on-config-init.patch",
    "content": "From c329e5afb42ff0a88285eb4d8a391a18793e4777 Mon Sep 17 00:00:00 2001\nFrom: David Bauer <mail@david-bauer.net>\nDate: Thu, 15 Apr 2021 03:26:50 +0200\nSubject: [PATCH] net: phy: at803x: select correct page on config init\n\nThe Atheros AR8031 and AR8033 expose different registers for SGMII/Fiber\nas well as the copper side of the PHY depending on the BT_BX_REG_SEL bit\nin the chip configure register.\n\nThe driver assumes the copper side is selected on probe, but this might\nnot be the case depending which page was last selected by the\nbootloader. Notably, Ubiquiti UniFi bootloaders show this behavior.\n\nSelect the copper page when probing to circumvent this.\n\nSigned-off-by: David Bauer <mail@david-bauer.net>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/phy/at803x.c | 50 +++++++++++++++++++++++++++++++++++++++-\n 1 file changed, 49 insertions(+), 1 deletion(-)\n\n--- a/drivers/net/phy/at803x.c\n+++ b/drivers/net/phy/at803x.c\n@@ -139,6 +139,9 @@\n #define ATH8035_PHY_ID 0x004dd072\n #define AT8030_PHY_ID_MASK\t\t\t0xffffffef\n \n+#define AT803X_PAGE_FIBER\t\t0\n+#define AT803X_PAGE_COPPER\t\t1\n+\n MODULE_DESCRIPTION(\"Qualcomm Atheros AR803x PHY driver\");\n MODULE_AUTHOR(\"Matus Ujhelyi\");\n MODULE_LICENSE(\"GPL\");\n@@ -190,6 +193,35 @@ static int at803x_debug_reg_mask(struct\n \treturn phy_write(phydev, AT803X_DEBUG_DATA, val);\n }\n \n+static int at803x_write_page(struct phy_device *phydev, int page)\n+{\n+\tint mask;\n+\tint set;\n+\n+\tif (page == AT803X_PAGE_COPPER) {\n+\t\tset = AT803X_BT_BX_REG_SEL;\n+\t\tmask = 0;\n+\t} else {\n+\t\tset = 0;\n+\t\tmask = AT803X_BT_BX_REG_SEL;\n+\t}\n+\n+\treturn __phy_modify(phydev, AT803X_REG_CHIP_CONFIG, mask, set);\n+}\n+\n+static int at803x_read_page(struct phy_device *phydev)\n+{\n+\tint ccr = __phy_read(phydev, AT803X_REG_CHIP_CONFIG);\n+\n+\tif (ccr < 0)\n+\t\treturn ccr;\n+\n+\tif (ccr & AT803X_BT_BX_REG_SEL)\n+\t\treturn AT803X_PAGE_COPPER;\n+\n+\treturn AT803X_PAGE_FIBER;\n+}\n+\n static int at803x_enable_rx_delay(struct phy_device *phydev)\n {\n \treturn at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_0, 0,\n@@ -508,6 +540,7 @@ static int at803x_probe(struct phy_devic\n {\n \tstruct device *dev = &phydev->mdio.dev;\n \tstruct at803x_priv *priv;\n+\tint ret;\n \n \tpriv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);\n \tif (!priv)\n@@ -515,7 +548,20 @@ static int at803x_probe(struct phy_devic\n \n \tphydev->priv = priv;\n \n-\treturn at803x_parse_dt(phydev);\n+\tret = at803x_parse_dt(phydev);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\t/* Some bootloaders leave the fiber page selected.\n+\t * Switch to the copper page, as otherwise we read\n+\t * the PHY capabilities from the fiber side.\n+\t */\n+\tif (at803x_match_phy_id(phydev, ATH8031_PHY_ID)) {\n+\t\tret = phy_select_page(phydev, AT803X_PAGE_COPPER);\n+\t\tret = phy_restore_page(phydev, AT803X_PAGE_COPPER, ret);\n+\t}\n+\n+\treturn ret;\n }\n \n static void at803x_remove(struct phy_device *phydev)\n@@ -1097,6 +1143,8 @@ static struct phy_driver at803x_driver[]\n \t.get_wol\t\t= at803x_get_wol,\n \t.suspend\t\t= at803x_suspend,\n \t.resume\t\t\t= at803x_resume,\n+\t.read_page\t\t= at803x_read_page,\n+\t.write_page\t\t= at803x_write_page,\n \t/* PHY_GBIT_FEATURES */\n \t.read_status\t\t= at803x_read_status,\n \t.aneg_done\t\t= at803x_aneg_done,\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/706-net-phy-at803x-fix-probe-error-if-copper-page-is-sel.patch",
    "content": "From 8f7e876273e294b732b42af2e5e6bba91d798954 Mon Sep 17 00:00:00 2001\nFrom: Michael Walle <michael@walle.cc>\nDate: Tue, 20 Apr 2021 12:29:29 +0200\nSubject: [PATCH] net: phy: at803x: fix probe error if copper page is selected\n\nThe commit c329e5afb42f (\"net: phy: at803x: select correct page on\nconfig init\") selects the copper page during probe. This fails if the\ncopper page was already selected. In this case, the value of the copper\npage (which is 1) is propagated through phy_restore_page() and is\nfinally returned for at803x_probe(). Fix it, by just using the\nat803x_page_write() directly.\n\nAlso in case of an error, the regulator is not disabled and leads to a\nWARN_ON() when the probe fails. This couldn't happen before, because\nat803x_parse_dt() was the last call in at803x_probe(). It is hard to\nsee, that the parse_dt() actually enables the regulator. Thus move the\nregulator_enable() to the probe function and undo it in case of an\nerror.\n\nFixes: c329e5afb42f (\"net: phy: at803x: select correct page on config init\")\nSigned-off-by: Michael Walle <michael@walle.cc>\nReviewed-by: David Bauer <mail@david-bauer.net>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/phy/at803x.c | 23 +++++++++++++++++------\n 1 file changed, 17 insertions(+), 6 deletions(-)\n\n--- a/drivers/net/phy/at803x.c\n+++ b/drivers/net/phy/at803x.c\n@@ -527,10 +527,6 @@ static int at803x_parse_dt(struct phy_de\n \t\t\tphydev_err(phydev, \"failed to get VDDIO regulator\\n\");\n \t\t\treturn PTR_ERR(priv->vddio);\n \t\t}\n-\n-\t\tret = regulator_enable(priv->vddio);\n-\t\tif (ret < 0)\n-\t\t\treturn ret;\n \t}\n \n \treturn 0;\n@@ -552,15 +548,30 @@ static int at803x_probe(struct phy_devic\n \tif (ret)\n \t\treturn ret;\n \n+\tif (priv->vddio) {\n+\t\tret = regulator_enable(priv->vddio);\n+\t\tif (ret < 0)\n+\t\t\treturn ret;\n+\t}\n+\n \t/* Some bootloaders leave the fiber page selected.\n \t * Switch to the copper page, as otherwise we read\n \t * the PHY capabilities from the fiber side.\n \t */\n \tif (at803x_match_phy_id(phydev, ATH8031_PHY_ID)) {\n-\t\tret = phy_select_page(phydev, AT803X_PAGE_COPPER);\n-\t\tret = phy_restore_page(phydev, AT803X_PAGE_COPPER, ret);\n+\t\tphy_lock_mdio_bus(phydev);\n+\t\tret = at803x_write_page(phydev, AT803X_PAGE_COPPER);\n+\t\tphy_unlock_mdio_bus(phydev);\n+\t\tif (ret)\n+\t\t\tgoto err;\n \t}\n \n+\treturn 0;\n+\n+err:\n+\tif (priv->vddio)\n+\t\tregulator_disable(priv->vddio);\n+\n \treturn ret;\n }\n \n"
  },
  {
    "path": "target/linux/generic/backport-5.10/710-v5.12-net-phy-Add-100-base-x-mode.patch",
    "content": "From b1ae3587d16a8c8fc9453e147c8708d6f006ffbb Mon Sep 17 00:00:00 2001\nFrom: Bjarni Jonasson <bjarni.jonasson@microchip.com>\nDate: Wed, 13 Jan 2021 12:56:25 +0100\nSubject: [PATCH] net: phy: Add 100 base-x mode\n\nSparx-5 supports this mode and it is missing in the PHY core.\n\nSigned-off-by: Bjarni Jonasson <bjarni.jonasson@microchip.com>\nReviewed-by: Russell King <rmk+kernel@armlinux.org.uk>\nSigned-off-by: Jakub Kicinski <kuba@kernel.org>\n---\n Documentation/networking/phy.rst | 5 +++++\n include/linux/phy.h              | 4 ++++\n 2 files changed, 9 insertions(+)\n\n--- a/Documentation/networking/phy.rst\n+++ b/Documentation/networking/phy.rst\n@@ -286,6 +286,11 @@ Some of the interface modes are describe\n     Note: due to legacy usage, some 10GBASE-R usage incorrectly makes\n     use of this definition.\n \n+``PHY_INTERFACE_MODE_100BASEX``\n+    This defines IEEE 802.3 Clause 24.  The link operates at a fixed data\n+    rate of 125Mpbs using a 4B/5B encoding scheme, resulting in an underlying\n+    data rate of 100Mpbs.\n+\n Pause frames / flow control\n ===========================\n \n--- a/include/linux/phy.h\n+++ b/include/linux/phy.h\n@@ -104,6 +104,7 @@ extern const int phy_10gbit_features_arr\n  * @PHY_INTERFACE_MODE_MOCA: Multimedia over Coax\n  * @PHY_INTERFACE_MODE_QSGMII: Quad SGMII\n  * @PHY_INTERFACE_MODE_TRGMII: Turbo RGMII\n+ * @PHY_INTERFACE_MODE_100BASEX: 100 BaseX\n  * @PHY_INTERFACE_MODE_1000BASEX: 1000 BaseX\n  * @PHY_INTERFACE_MODE_2500BASEX: 2500 BaseX\n  * @PHY_INTERFACE_MODE_RXAUI: Reduced XAUI\n@@ -135,6 +136,7 @@ typedef enum {\n \tPHY_INTERFACE_MODE_MOCA,\n \tPHY_INTERFACE_MODE_QSGMII,\n \tPHY_INTERFACE_MODE_TRGMII,\n+\tPHY_INTERFACE_MODE_100BASEX,\n \tPHY_INTERFACE_MODE_1000BASEX,\n \tPHY_INTERFACE_MODE_2500BASEX,\n \tPHY_INTERFACE_MODE_RXAUI,\n@@ -217,6 +219,8 @@ static inline const char *phy_modes(phy_\n \t\treturn \"usxgmii\";\n \tcase PHY_INTERFACE_MODE_10GKR:\n \t\treturn \"10gbase-kr\";\n+\tcase PHY_INTERFACE_MODE_100BASEX:\n+\t\treturn \"100base-x\";\n \tdefault:\n \t\treturn \"unknown\";\n \t}\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/711-v5.12-sfp-add-support-for-100-base-x-SFPs.patch",
    "content": "From 6e12f35cef6b8a458d7ecf507ae330e0bffaad8c Mon Sep 17 00:00:00 2001\nFrom: Bjarni Jonasson <bjarni.jonasson@microchip.com>\nDate: Wed, 13 Jan 2021 12:56:26 +0100\nSubject: [PATCH] sfp: add support for 100 base-x SFPs\n\nAdd support for 100Base-FX, 100Base-LX, 100Base-PX and 100Base-BX10 modules\nThis is needed for Sparx-5 switch.\n\nSigned-off-by: Bjarni Jonasson <bjarni.jonasson@microchip.com>\nReviewed-by: Russell King <rmk+kernel@armlinux.org.uk>\nSigned-off-by: Jakub Kicinski <kuba@kernel.org>\n---\n drivers/net/phy/sfp-bus.c | 9 +++++++++\n 1 file changed, 9 insertions(+)\n\n--- a/drivers/net/phy/sfp-bus.c\n+++ b/drivers/net/phy/sfp-bus.c\n@@ -286,6 +286,12 @@ void sfp_parse_support(struct sfp_bus *b\n \t    br_min <= 1300 && br_max >= 1200)\n \t\tphylink_set(modes, 1000baseX_Full);\n \n+\t/* 100Base-FX, 100Base-LX, 100Base-PX, 100Base-BX10 */\n+\tif (id->base.e100_base_fx || id->base.e100_base_lx)\n+\t\tphylink_set(modes, 100baseFX_Full);\n+\tif ((id->base.e_base_px || id->base.e_base_bx10) && br_nom == 100)\n+\t\tphylink_set(modes, 100baseFX_Full);\n+\n \t/* For active or passive cables, select the link modes\n \t * based on the bit rates and the cable compliance bytes.\n \t */\n@@ -405,6 +411,9 @@ phy_interface_t sfp_select_interface(str\n \tif (phylink_test(link_modes, 1000baseX_Full))\n \t\treturn PHY_INTERFACE_MODE_1000BASEX;\n \n+\tif (phylink_test(link_modes, 100baseFX_Full))\n+\t\treturn PHY_INTERFACE_MODE_100BASEX;\n+\n \tdev_warn(bus->sfp_dev, \"Unable to ascertain link mode\\n\");\n \n \treturn PHY_INTERFACE_MODE_NA;\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/712-v5.13-net-phy-marvell-refactor-HWMON-OOP-style.patch",
    "content": "From 41d26bf4aba070dfd2ab48866cc27a48ee6228c7 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Marek=20Beh=C3=BAn?= <kabel@kernel.org>\nDate: Tue, 20 Apr 2021 09:53:59 +0200\nSubject: [PATCH] net: phy: marvell: refactor HWMON OOP style\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nUse a structure of Marvell PHY specific HWMON methods to reduce code\nduplication. Store a pointer to this structure into the PHY driver's\ndriver_data member.\n\nSigned-off-by: Marek Behún <kabel@kernel.org>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/phy/marvell.c | 369 +++++++++++++-------------------------\n 1 file changed, 125 insertions(+), 244 deletions(-)\n\n--- a/drivers/net/phy/marvell.c\n+++ b/drivers/net/phy/marvell.c\n@@ -2141,6 +2141,19 @@ static int marvell_vct7_cable_test_get_s\n }\n \n #ifdef CONFIG_HWMON\n+struct marvell_hwmon_ops {\n+\tint (*get_temp)(struct phy_device *phydev, long *temp);\n+\tint (*get_temp_critical)(struct phy_device *phydev, long *temp);\n+\tint (*set_temp_critical)(struct phy_device *phydev, long temp);\n+\tint (*get_temp_alarm)(struct phy_device *phydev, long *alarm);\n+};\n+\n+static const struct marvell_hwmon_ops *\n+to_marvell_hwmon_ops(const struct phy_device *phydev)\n+{\n+\treturn phydev->drv->driver_data;\n+}\n+\n static int m88e1121_get_temp(struct phy_device *phydev, long *temp)\n {\n \tint oldpage;\n@@ -2184,75 +2197,6 @@ error:\n \treturn phy_restore_page(phydev, oldpage, ret);\n }\n \n-static int m88e1121_hwmon_read(struct device *dev,\n-\t\t\t       enum hwmon_sensor_types type,\n-\t\t\t       u32 attr, int channel, long *temp)\n-{\n-\tstruct phy_device *phydev = dev_get_drvdata(dev);\n-\tint err;\n-\n-\tswitch (attr) {\n-\tcase hwmon_temp_input:\n-\t\terr = m88e1121_get_temp(phydev, temp);\n-\t\tbreak;\n-\tdefault:\n-\t\treturn -EOPNOTSUPP;\n-\t}\n-\n-\treturn err;\n-}\n-\n-static umode_t m88e1121_hwmon_is_visible(const void *data,\n-\t\t\t\t\t enum hwmon_sensor_types type,\n-\t\t\t\t\t u32 attr, int channel)\n-{\n-\tif (type != hwmon_temp)\n-\t\treturn 0;\n-\n-\tswitch (attr) {\n-\tcase hwmon_temp_input:\n-\t\treturn 0444;\n-\tdefault:\n-\t\treturn 0;\n-\t}\n-}\n-\n-static u32 m88e1121_hwmon_chip_config[] = {\n-\tHWMON_C_REGISTER_TZ,\n-\t0\n-};\n-\n-static const struct hwmon_channel_info m88e1121_hwmon_chip = {\n-\t.type = hwmon_chip,\n-\t.config = m88e1121_hwmon_chip_config,\n-};\n-\n-static u32 m88e1121_hwmon_temp_config[] = {\n-\tHWMON_T_INPUT,\n-\t0\n-};\n-\n-static const struct hwmon_channel_info m88e1121_hwmon_temp = {\n-\t.type = hwmon_temp,\n-\t.config = m88e1121_hwmon_temp_config,\n-};\n-\n-static const struct hwmon_channel_info *m88e1121_hwmon_info[] = {\n-\t&m88e1121_hwmon_chip,\n-\t&m88e1121_hwmon_temp,\n-\tNULL\n-};\n-\n-static const struct hwmon_ops m88e1121_hwmon_hwmon_ops = {\n-\t.is_visible = m88e1121_hwmon_is_visible,\n-\t.read = m88e1121_hwmon_read,\n-};\n-\n-static const struct hwmon_chip_info m88e1121_hwmon_chip_info = {\n-\t.ops = &m88e1121_hwmon_hwmon_ops,\n-\t.info = m88e1121_hwmon_info,\n-};\n-\n static int m88e1510_get_temp(struct phy_device *phydev, long *temp)\n {\n \tint ret;\n@@ -2315,92 +2259,6 @@ static int m88e1510_get_temp_alarm(struc\n \treturn 0;\n }\n \n-static int m88e1510_hwmon_read(struct device *dev,\n-\t\t\t       enum hwmon_sensor_types type,\n-\t\t\t       u32 attr, int channel, long *temp)\n-{\n-\tstruct phy_device *phydev = dev_get_drvdata(dev);\n-\tint err;\n-\n-\tswitch (attr) {\n-\tcase hwmon_temp_input:\n-\t\terr = m88e1510_get_temp(phydev, temp);\n-\t\tbreak;\n-\tcase hwmon_temp_crit:\n-\t\terr = m88e1510_get_temp_critical(phydev, temp);\n-\t\tbreak;\n-\tcase hwmon_temp_max_alarm:\n-\t\terr = m88e1510_get_temp_alarm(phydev, temp);\n-\t\tbreak;\n-\tdefault:\n-\t\treturn -EOPNOTSUPP;\n-\t}\n-\n-\treturn err;\n-}\n-\n-static int m88e1510_hwmon_write(struct device *dev,\n-\t\t\t\tenum hwmon_sensor_types type,\n-\t\t\t\tu32 attr, int channel, long temp)\n-{\n-\tstruct phy_device *phydev = dev_get_drvdata(dev);\n-\tint err;\n-\n-\tswitch (attr) {\n-\tcase hwmon_temp_crit:\n-\t\terr = m88e1510_set_temp_critical(phydev, temp);\n-\t\tbreak;\n-\tdefault:\n-\t\treturn -EOPNOTSUPP;\n-\t}\n-\treturn err;\n-}\n-\n-static umode_t m88e1510_hwmon_is_visible(const void *data,\n-\t\t\t\t\t enum hwmon_sensor_types type,\n-\t\t\t\t\t u32 attr, int channel)\n-{\n-\tif (type != hwmon_temp)\n-\t\treturn 0;\n-\n-\tswitch (attr) {\n-\tcase hwmon_temp_input:\n-\tcase hwmon_temp_max_alarm:\n-\t\treturn 0444;\n-\tcase hwmon_temp_crit:\n-\t\treturn 0644;\n-\tdefault:\n-\t\treturn 0;\n-\t}\n-}\n-\n-static u32 m88e1510_hwmon_temp_config[] = {\n-\tHWMON_T_INPUT | HWMON_T_CRIT | HWMON_T_MAX_ALARM,\n-\t0\n-};\n-\n-static const struct hwmon_channel_info m88e1510_hwmon_temp = {\n-\t.type = hwmon_temp,\n-\t.config = m88e1510_hwmon_temp_config,\n-};\n-\n-static const struct hwmon_channel_info *m88e1510_hwmon_info[] = {\n-\t&m88e1121_hwmon_chip,\n-\t&m88e1510_hwmon_temp,\n-\tNULL\n-};\n-\n-static const struct hwmon_ops m88e1510_hwmon_hwmon_ops = {\n-\t.is_visible = m88e1510_hwmon_is_visible,\n-\t.read = m88e1510_hwmon_read,\n-\t.write = m88e1510_hwmon_write,\n-};\n-\n-static const struct hwmon_chip_info m88e1510_hwmon_chip_info = {\n-\t.ops = &m88e1510_hwmon_hwmon_ops,\n-\t.info = m88e1510_hwmon_info,\n-};\n-\n static int m88e6390_get_temp(struct phy_device *phydev, long *temp)\n {\n \tint sum = 0;\n@@ -2459,63 +2317,112 @@ error:\n \treturn ret;\n }\n \n-static int m88e6390_hwmon_read(struct device *dev,\n-\t\t\t       enum hwmon_sensor_types type,\n-\t\t\t       u32 attr, int channel, long *temp)\n+static int marvell_hwmon_read(struct device *dev, enum hwmon_sensor_types type,\n+\t\t\t      u32 attr, int channel, long *temp)\n {\n \tstruct phy_device *phydev = dev_get_drvdata(dev);\n-\tint err;\n+\tconst struct marvell_hwmon_ops *ops = to_marvell_hwmon_ops(phydev);\n+\tint err = -EOPNOTSUPP;\n \n \tswitch (attr) {\n \tcase hwmon_temp_input:\n-\t\terr = m88e6390_get_temp(phydev, temp);\n+\t\tif (ops->get_temp)\n+\t\t\terr = ops->get_temp(phydev, temp);\n+\t\tbreak;\n+\tcase hwmon_temp_crit:\n+\t\tif (ops->get_temp_critical)\n+\t\t\terr = ops->get_temp_critical(phydev, temp);\n+\t\tbreak;\n+\tcase hwmon_temp_max_alarm:\n+\t\tif (ops->get_temp_alarm)\n+\t\t\terr = ops->get_temp_alarm(phydev, temp);\n+\t\tbreak;\n+\t}\n+\n+\treturn err;\n+}\n+\n+static int marvell_hwmon_write(struct device *dev, enum hwmon_sensor_types type,\n+\t\t\t       u32 attr, int channel, long temp)\n+{\n+\tstruct phy_device *phydev = dev_get_drvdata(dev);\n+\tconst struct marvell_hwmon_ops *ops = to_marvell_hwmon_ops(phydev);\n+\tint err = -EOPNOTSUPP;\n+\n+\tswitch (attr) {\n+\tcase hwmon_temp_crit:\n+\t\tif (ops->set_temp_critical)\n+\t\t\terr = ops->set_temp_critical(phydev, temp);\n \t\tbreak;\n \tdefault:\n-\t\treturn -EOPNOTSUPP;\n+\t\tfallthrough;\n \t}\n \n \treturn err;\n }\n \n-static umode_t m88e6390_hwmon_is_visible(const void *data,\n-\t\t\t\t\t enum hwmon_sensor_types type,\n-\t\t\t\t\t u32 attr, int channel)\n+static umode_t marvell_hwmon_is_visible(const void *data,\n+\t\t\t\t\tenum hwmon_sensor_types type,\n+\t\t\t\t\tu32 attr, int channel)\n {\n+\tconst struct phy_device *phydev = data;\n+\tconst struct marvell_hwmon_ops *ops = to_marvell_hwmon_ops(phydev);\n+\n \tif (type != hwmon_temp)\n \t\treturn 0;\n \n \tswitch (attr) {\n \tcase hwmon_temp_input:\n-\t\treturn 0444;\n+\t\treturn ops->get_temp ? 0444 : 0;\n+\tcase hwmon_temp_max_alarm:\n+\t\treturn ops->get_temp_alarm ? 0444 : 0;\n+\tcase hwmon_temp_crit:\n+\t\treturn (ops->get_temp_critical ? 0444 : 0) |\n+\t\t       (ops->set_temp_critical ? 0200 : 0);\n \tdefault:\n \t\treturn 0;\n \t}\n }\n \n-static u32 m88e6390_hwmon_temp_config[] = {\n-\tHWMON_T_INPUT,\n+static u32 marvell_hwmon_chip_config[] = {\n+\tHWMON_C_REGISTER_TZ,\n \t0\n };\n \n-static const struct hwmon_channel_info m88e6390_hwmon_temp = {\n+static const struct hwmon_channel_info marvell_hwmon_chip = {\n+\t.type = hwmon_chip,\n+\t.config = marvell_hwmon_chip_config,\n+};\n+\n+/* we can define HWMON_T_CRIT and HWMON_T_MAX_ALARM even though these are not\n+ * defined for all PHYs, because the hwmon code checks whether the attributes\n+ * exists via the .is_visible method\n+ */\n+static u32 marvell_hwmon_temp_config[] = {\n+\tHWMON_T_INPUT | HWMON_T_CRIT | HWMON_T_MAX_ALARM,\n+\t0\n+};\n+\n+static const struct hwmon_channel_info marvell_hwmon_temp = {\n \t.type = hwmon_temp,\n-\t.config = m88e6390_hwmon_temp_config,\n+\t.config = marvell_hwmon_temp_config,\n };\n \n-static const struct hwmon_channel_info *m88e6390_hwmon_info[] = {\n-\t&m88e1121_hwmon_chip,\n-\t&m88e6390_hwmon_temp,\n+static const struct hwmon_channel_info *marvell_hwmon_info[] = {\n+\t&marvell_hwmon_chip,\n+\t&marvell_hwmon_temp,\n \tNULL\n };\n \n-static const struct hwmon_ops m88e6390_hwmon_hwmon_ops = {\n-\t.is_visible = m88e6390_hwmon_is_visible,\n-\t.read = m88e6390_hwmon_read,\n+static const struct hwmon_ops marvell_hwmon_hwmon_ops = {\n+\t.is_visible = marvell_hwmon_is_visible,\n+\t.read = marvell_hwmon_read,\n+\t.write = marvell_hwmon_write,\n };\n \n-static const struct hwmon_chip_info m88e6390_hwmon_chip_info = {\n-\t.ops = &m88e6390_hwmon_hwmon_ops,\n-\t.info = m88e6390_hwmon_info,\n+static const struct hwmon_chip_info marvell_hwmon_chip_info = {\n+\t.ops = &marvell_hwmon_hwmon_ops,\n+\t.info = marvell_hwmon_info,\n };\n \n static int marvell_hwmon_name(struct phy_device *phydev)\n@@ -2538,49 +2445,48 @@ static int marvell_hwmon_name(struct phy\n \treturn 0;\n }\n \n-static int marvell_hwmon_probe(struct phy_device *phydev,\n-\t\t\t       const struct hwmon_chip_info *chip)\n+static int marvell_hwmon_probe(struct phy_device *phydev)\n {\n+\tconst struct marvell_hwmon_ops *ops = to_marvell_hwmon_ops(phydev);\n \tstruct marvell_priv *priv = phydev->priv;\n \tstruct device *dev = &phydev->mdio.dev;\n \tint err;\n \n+\tif (!ops)\n+\t\treturn 0;\n+\n \terr = marvell_hwmon_name(phydev);\n \tif (err)\n \t\treturn err;\n \n \tpriv->hwmon_dev = devm_hwmon_device_register_with_info(\n-\t\tdev, priv->hwmon_name, phydev, chip, NULL);\n+\t\tdev, priv->hwmon_name, phydev, &marvell_hwmon_chip_info, NULL);\n \n \treturn PTR_ERR_OR_ZERO(priv->hwmon_dev);\n }\n \n-static int m88e1121_hwmon_probe(struct phy_device *phydev)\n-{\n-\treturn marvell_hwmon_probe(phydev, &m88e1121_hwmon_chip_info);\n-}\n+static const struct marvell_hwmon_ops m88e1121_hwmon_ops = {\n+\t.get_temp = m88e1121_get_temp,\n+};\n \n-static int m88e1510_hwmon_probe(struct phy_device *phydev)\n-{\n-\treturn marvell_hwmon_probe(phydev, &m88e1510_hwmon_chip_info);\n-}\n+static const struct marvell_hwmon_ops m88e1510_hwmon_ops = {\n+\t.get_temp = m88e1510_get_temp,\n+\t.get_temp_critical = m88e1510_get_temp_critical,\n+\t.set_temp_critical = m88e1510_set_temp_critical,\n+\t.get_temp_alarm = m88e1510_get_temp_alarm,\n+};\n+\n+static const struct marvell_hwmon_ops m88e6390_hwmon_ops = {\n+\t.get_temp = m88e6390_get_temp,\n+};\n+\n+#define DEF_MARVELL_HWMON_OPS(s) (&(s))\n \n-static int m88e6390_hwmon_probe(struct phy_device *phydev)\n-{\n-\treturn marvell_hwmon_probe(phydev, &m88e6390_hwmon_chip_info);\n-}\n #else\n-static int m88e1121_hwmon_probe(struct phy_device *phydev)\n-{\n-\treturn 0;\n-}\n \n-static int m88e1510_hwmon_probe(struct phy_device *phydev)\n-{\n-\treturn 0;\n-}\n+#define DEF_MARVELL_HWMON_OPS(s) NULL\n \n-static int m88e6390_hwmon_probe(struct phy_device *phydev)\n+static int marvell_hwmon_probe(struct phy_device *phydev)\n {\n \treturn 0;\n }\n@@ -2596,40 +2502,7 @@ static int marvell_probe(struct phy_devi\n \n \tphydev->priv = priv;\n \n-\treturn 0;\n-}\n-\n-static int m88e1121_probe(struct phy_device *phydev)\n-{\n-\tint err;\n-\n-\terr = marvell_probe(phydev);\n-\tif (err)\n-\t\treturn err;\n-\n-\treturn m88e1121_hwmon_probe(phydev);\n-}\n-\n-static int m88e1510_probe(struct phy_device *phydev)\n-{\n-\tint err;\n-\n-\terr = marvell_probe(phydev);\n-\tif (err)\n-\t\treturn err;\n-\n-\treturn m88e1510_hwmon_probe(phydev);\n-}\n-\n-static int m88e6390_probe(struct phy_device *phydev)\n-{\n-\tint err;\n-\n-\terr = marvell_probe(phydev);\n-\tif (err)\n-\t\treturn err;\n-\n-\treturn m88e6390_hwmon_probe(phydev);\n+\treturn marvell_hwmon_probe(phydev);\n }\n \n static struct phy_driver marvell_drivers[] = {\n@@ -2714,8 +2587,9 @@ static struct phy_driver marvell_drivers\n \t\t.phy_id = MARVELL_PHY_ID_88E1121R,\n \t\t.phy_id_mask = MARVELL_PHY_ID_MASK,\n \t\t.name = \"Marvell 88E1121R\",\n+\t\t.driver_data = DEF_MARVELL_HWMON_OPS(m88e1121_hwmon_ops),\n \t\t/* PHY_GBIT_FEATURES */\n-\t\t.probe = m88e1121_probe,\n+\t\t.probe = marvell_probe,\n \t\t.config_init = marvell_config_init,\n \t\t.config_aneg = m88e1121_config_aneg,\n \t\t.read_status = marvell_read_status,\n@@ -2834,9 +2708,10 @@ static struct phy_driver marvell_drivers\n \t\t.phy_id = MARVELL_PHY_ID_88E1510,\n \t\t.phy_id_mask = MARVELL_PHY_ID_MASK,\n \t\t.name = \"Marvell 88E1510\",\n+\t\t.driver_data = DEF_MARVELL_HWMON_OPS(m88e1510_hwmon_ops),\n \t\t.features = PHY_GBIT_FIBRE_FEATURES,\n \t\t.flags = PHY_POLL_CABLE_TEST,\n-\t\t.probe = m88e1510_probe,\n+\t\t.probe = marvell_probe,\n \t\t.config_init = m88e1510_config_init,\n \t\t.config_aneg = m88e1510_config_aneg,\n \t\t.read_status = marvell_read_status,\n@@ -2863,9 +2738,10 @@ static struct phy_driver marvell_drivers\n \t\t.phy_id = MARVELL_PHY_ID_88E1540,\n \t\t.phy_id_mask = MARVELL_PHY_ID_MASK,\n \t\t.name = \"Marvell 88E1540\",\n+\t\t.driver_data = DEF_MARVELL_HWMON_OPS(m88e1510_hwmon_ops),\n \t\t/* PHY_GBIT_FEATURES */\n \t\t.flags = PHY_POLL_CABLE_TEST,\n-\t\t.probe = m88e1510_probe,\n+\t\t.probe = marvell_probe,\n \t\t.config_init = marvell_config_init,\n \t\t.config_aneg = m88e1510_config_aneg,\n \t\t.read_status = marvell_read_status,\n@@ -2889,7 +2765,8 @@ static struct phy_driver marvell_drivers\n \t\t.phy_id = MARVELL_PHY_ID_88E1545,\n \t\t.phy_id_mask = MARVELL_PHY_ID_MASK,\n \t\t.name = \"Marvell 88E1545\",\n-\t\t.probe = m88e1510_probe,\n+\t\t.driver_data = DEF_MARVELL_HWMON_OPS(m88e1510_hwmon_ops),\n+\t\t.probe = marvell_probe,\n \t\t/* PHY_GBIT_FEATURES */\n \t\t.flags = PHY_POLL_CABLE_TEST,\n \t\t.config_init = marvell_config_init,\n@@ -2935,9 +2812,10 @@ static struct phy_driver marvell_drivers\n \t\t.phy_id = MARVELL_PHY_ID_88E6341_FAMILY,\n \t\t.phy_id_mask = MARVELL_PHY_ID_MASK,\n \t\t.name = \"Marvell 88E6341 Family\",\n+\t\t.driver_data = DEF_MARVELL_HWMON_OPS(m88e1510_hwmon_ops),\n \t\t/* PHY_GBIT_FEATURES */\n \t\t.flags = PHY_POLL_CABLE_TEST,\n-\t\t.probe = m88e1510_probe,\n+\t\t.probe = marvell_probe,\n \t\t.config_init = marvell_config_init,\n \t\t.config_aneg = m88e6390_config_aneg,\n \t\t.read_status = marvell_read_status,\n@@ -2961,9 +2839,10 @@ static struct phy_driver marvell_drivers\n \t\t.phy_id = MARVELL_PHY_ID_88E6390_FAMILY,\n \t\t.phy_id_mask = MARVELL_PHY_ID_MASK,\n \t\t.name = \"Marvell 88E6390 Family\",\n+\t\t.driver_data = DEF_MARVELL_HWMON_OPS(m88e6390_hwmon_ops),\n \t\t/* PHY_GBIT_FEATURES */\n \t\t.flags = PHY_POLL_CABLE_TEST,\n-\t\t.probe = m88e6390_probe,\n+\t\t.probe = marvell_probe,\n \t\t.config_init = marvell_config_init,\n \t\t.config_aneg = m88e6390_config_aneg,\n \t\t.read_status = marvell_read_status,\n@@ -2987,7 +2866,8 @@ static struct phy_driver marvell_drivers\n \t\t.phy_id = MARVELL_PHY_ID_88E1340S,\n \t\t.phy_id_mask = MARVELL_PHY_ID_MASK,\n \t\t.name = \"Marvell 88E1340S\",\n-\t\t.probe = m88e1510_probe,\n+\t\t.driver_data = DEF_MARVELL_HWMON_OPS(m88e1510_hwmon_ops),\n+\t\t.probe = marvell_probe,\n \t\t/* PHY_GBIT_FEATURES */\n \t\t.config_init = marvell_config_init,\n \t\t.config_aneg = m88e1510_config_aneg,\n@@ -3009,7 +2889,8 @@ static struct phy_driver marvell_drivers\n \t\t.phy_id = MARVELL_PHY_ID_88E1548P,\n \t\t.phy_id_mask = MARVELL_PHY_ID_MASK,\n \t\t.name = \"Marvell 88E1548P\",\n-\t\t.probe = m88e1510_probe,\n+\t\t.driver_data = DEF_MARVELL_HWMON_OPS(m88e1510_hwmon_ops),\n+\t\t.probe = marvell_probe,\n \t\t.features = PHY_GBIT_FIBRE_FEATURES,\n \t\t.config_init = marvell_config_init,\n \t\t.config_aneg = m88e1510_config_aneg,\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/713-v5.15-net-phy-marvell-add-SFP-support-for-88E1510.patch",
    "content": "From b697d9d38a5a5ab405d7cc4743d39fe2c5d7517c Mon Sep 17 00:00:00 2001\nFrom: Ivan Bornyakov <i.bornyakov@metrotek.ru>\nDate: Thu, 12 Aug 2021 16:42:56 +0300\nSubject: [PATCH] net: phy: marvell: add SFP support for 88E1510\n\nAdd support for SFP cages connected to the Marvell 88E1512 transceiver.\n88E1512 supports for SGMII/1000Base-X/100Base-FX media type with RGMII\non system interface. Configure PHY to appropriate mode depending on the\ntype of SFP inserted. On SFP removal configure PHY to the RGMII-copper\nmode so RJ-45 port can still work.\n\nSigned-off-by: Ivan Bornyakov <i.bornyakov@metrotek.ru>\nLink: https://lore.kernel.org/r/20210812134256.2436-1-i.bornyakov@metrotek.ru\nSigned-off-by: Jakub Kicinski <kuba@kernel.org>\n---\n drivers/net/phy/marvell.c | 105 +++++++++++++++++++++++++++++++++++++-\n 1 file changed, 104 insertions(+), 1 deletion(-)\n\n--- a/drivers/net/phy/marvell.c\n+++ b/drivers/net/phy/marvell.c\n@@ -32,6 +32,7 @@\n #include <linux/marvell_phy.h>\n #include <linux/bitfield.h>\n #include <linux/of.h>\n+#include <linux/sfp.h>\n \n #include <linux/io.h>\n #include <asm/irq.h>\n@@ -46,6 +47,7 @@\n #define MII_MARVELL_MISC_TEST_PAGE\t0x06\n #define MII_MARVELL_VCT7_PAGE\t\t0x07\n #define MII_MARVELL_WOL_PAGE\t\t0x11\n+#define MII_MARVELL_MODE_PAGE\t\t0x12\n \n #define MII_M1011_IEVENT\t\t0x13\n #define MII_M1011_IEVENT_CLEAR\t\t0x0000\n@@ -162,7 +164,14 @@\n \n #define MII_88E1510_GEN_CTRL_REG_1\t\t0x14\n #define MII_88E1510_GEN_CTRL_REG_1_MODE_MASK\t0x7\n+#define MII_88E1510_GEN_CTRL_REG_1_MODE_RGMII\t0x0\t/* RGMII to copper */\n #define MII_88E1510_GEN_CTRL_REG_1_MODE_SGMII\t0x1\t/* SGMII to copper */\n+/* RGMII to 1000BASE-X */\n+#define MII_88E1510_GEN_CTRL_REG_1_MODE_RGMII_1000X\t0x2\n+/* RGMII to 100BASE-FX */\n+#define MII_88E1510_GEN_CTRL_REG_1_MODE_RGMII_100FX\t0x3\n+/* RGMII to SGMII */\n+#define MII_88E1510_GEN_CTRL_REG_1_MODE_RGMII_SGMII\t0x4\n #define MII_88E1510_GEN_CTRL_REG_1_RESET\t0x8000\t/* Soft reset */\n \n #define MII_VCT5_TX_RX_MDI0_COUPLING\t0x10\n@@ -2505,6 +2514,100 @@ static int marvell_probe(struct phy_devi\n \treturn marvell_hwmon_probe(phydev);\n }\n \n+static int m88e1510_sfp_insert(void *upstream, const struct sfp_eeprom_id *id)\n+{\n+\tstruct phy_device *phydev = upstream;\n+\tphy_interface_t interface;\n+\tstruct device *dev;\n+\tint oldpage;\n+\tint ret = 0;\n+\tu16 mode;\n+\n+\t__ETHTOOL_DECLARE_LINK_MODE_MASK(supported) = { 0, };\n+\n+\tdev = &phydev->mdio.dev;\n+\n+\tsfp_parse_support(phydev->sfp_bus, id, supported);\n+\tinterface = sfp_select_interface(phydev->sfp_bus, supported);\n+\n+\tdev_info(dev, \"%s SFP module inserted\\n\", phy_modes(interface));\n+\n+\tswitch (interface) {\n+\tcase PHY_INTERFACE_MODE_1000BASEX:\n+\t\tmode = MII_88E1510_GEN_CTRL_REG_1_MODE_RGMII_1000X;\n+\n+\t\tbreak;\n+\tcase PHY_INTERFACE_MODE_100BASEX:\n+\t\tmode = MII_88E1510_GEN_CTRL_REG_1_MODE_RGMII_100FX;\n+\n+\t\tbreak;\n+\tcase PHY_INTERFACE_MODE_SGMII:\n+\t\tmode = MII_88E1510_GEN_CTRL_REG_1_MODE_RGMII_SGMII;\n+\n+\t\tbreak;\n+\tdefault:\n+\t\tdev_err(dev, \"Incompatible SFP module inserted\\n\");\n+\n+\t\treturn -EINVAL;\n+\t}\n+\n+\toldpage = phy_select_page(phydev, MII_MARVELL_MODE_PAGE);\n+\tif (oldpage < 0)\n+\t\tgoto error;\n+\n+\tret = __phy_modify(phydev, MII_88E1510_GEN_CTRL_REG_1,\n+\t\t\t   MII_88E1510_GEN_CTRL_REG_1_MODE_MASK, mode);\n+\tif (ret < 0)\n+\t\tgoto error;\n+\n+\tret = __phy_set_bits(phydev, MII_88E1510_GEN_CTRL_REG_1,\n+\t\t\t     MII_88E1510_GEN_CTRL_REG_1_RESET);\n+\n+error:\n+\treturn phy_restore_page(phydev, oldpage, ret);\n+}\n+\n+static void m88e1510_sfp_remove(void *upstream)\n+{\n+\tstruct phy_device *phydev = upstream;\n+\tint oldpage;\n+\tint ret = 0;\n+\n+\toldpage = phy_select_page(phydev, MII_MARVELL_MODE_PAGE);\n+\tif (oldpage < 0)\n+\t\tgoto error;\n+\n+\tret = __phy_modify(phydev, MII_88E1510_GEN_CTRL_REG_1,\n+\t\t\t   MII_88E1510_GEN_CTRL_REG_1_MODE_MASK,\n+\t\t\t   MII_88E1510_GEN_CTRL_REG_1_MODE_RGMII);\n+\tif (ret < 0)\n+\t\tgoto error;\n+\n+\tret = __phy_set_bits(phydev, MII_88E1510_GEN_CTRL_REG_1,\n+\t\t\t     MII_88E1510_GEN_CTRL_REG_1_RESET);\n+\n+error:\n+\tphy_restore_page(phydev, oldpage, ret);\n+}\n+\n+static const struct sfp_upstream_ops m88e1510_sfp_ops = {\n+\t.module_insert = m88e1510_sfp_insert,\n+\t.module_remove = m88e1510_sfp_remove,\n+\t.attach = phy_sfp_attach,\n+\t.detach = phy_sfp_detach,\n+};\n+\n+static int m88e1510_probe(struct phy_device *phydev)\n+{\n+\tint err;\n+\n+\terr = marvell_probe(phydev);\n+\tif (err)\n+\t\treturn err;\n+\n+\treturn phy_sfp_probe(phydev, &m88e1510_sfp_ops);\n+}\n+\n static struct phy_driver marvell_drivers[] = {\n \t{\n \t\t.phy_id = MARVELL_PHY_ID_88E1101,\n@@ -2711,7 +2814,7 @@ static struct phy_driver marvell_drivers\n \t\t.driver_data = DEF_MARVELL_HWMON_OPS(m88e1510_hwmon_ops),\n \t\t.features = PHY_GBIT_FIBRE_FEATURES,\n \t\t.flags = PHY_POLL_CABLE_TEST,\n-\t\t.probe = marvell_probe,\n+\t\t.probe = m88e1510_probe,\n \t\t.config_init = m88e1510_config_init,\n \t\t.config_aneg = m88e1510_config_aneg,\n \t\t.read_status = marvell_read_status,\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/719-v5.12-net-dsa-automatically-bring-up-DSA-master-when-openi.patch",
    "content": "From 9d5ef190e5615a7b63af89f88c4106a5bc127974 Mon Sep 17 00:00:00 2001\nFrom: Vladimir Oltean <vladimir.oltean@nxp.com>\nDate: Fri, 5 Feb 2021 15:37:10 +0200\nSubject: [PATCH] net: dsa: automatically bring up DSA master when opening user\n port\n\nDSA wants the master interface to be open before the user port is due to\nhistorical reasons. The promiscuity of interfaces that are down used to\nhave issues, as referenced Lennert Buytenhek in commit df02c6ff2e39\n(\"dsa: fix master interface allmulti/promisc handling\").\n\nThe bugfix mentioned there, commit b6c40d68ff64 (\"net: only invoke\ndev->change_rx_flags when device is UP\"), was basically a \"don't do\nthat\" approach to working around the promiscuity while down issue.\n\nFurther work done by Vlad Yasevich in commit d2615bf45069 (\"net: core:\nAlways propagate flag changes to interfaces\") has resolved the\nunderlying issue, and it is strictly up to the DSA and 8021q drivers\nnow, it is no longer mandated by the networking core that the master\ninterface must be up when changing its promiscuity.\n\nFrom DSA's point of view, deciding to error out in dsa_slave_open\nbecause the master isn't up is\n(a) a bad user experience and\n(b) knocking at an open door.\nEven if there still was an issue with promiscuity while down, DSA could\nstill just open the master and avoid it.\n\nDoing it this way has the additional benefit that user space can now\nremove DSA-specific workarounds, like systemd-networkd with BindCarrier:\nhttps://github.com/systemd/systemd/issues/7478\n\nAnd we can finally remove one of the 2 bullets in the \"Common pitfalls\nusing DSA setups\" chapter.\n\nTested with two cascaded DSA switches:\n\n$ ip link set sw0p2 up\nfsl_enetc 0000:00:00.2 eno2: configuring for fixed/internal link mode\nfsl_enetc 0000:00:00.2 eno2: Link is Up - 1Gbps/Full - flow control rx/tx\nmscc_felix 0000:00:00.5 swp0: configuring for fixed/sgmii link mode\nmscc_felix 0000:00:00.5 swp0: Link is Up - 1Gbps/Full - flow control off\n8021q: adding VLAN 0 to HW filter on device swp0\nsja1105 spi2.0 sw0p2: configuring for phy/rgmii-id link mode\nIPv6: ADDRCONF(NETDEV_CHANGE): eno2: link becomes ready\nIPv6: ADDRCONF(NETDEV_CHANGE): swp0: link becomes ready\n\nSigned-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>\nReviewed-by: Andrew Lunn <andrew@lunn.ch>\nReviewed-by: Florian Fainelli <f.fainelli@gmail.com>\nSigned-off-by: Jakub Kicinski <kuba@kernel.org>\n---\n Documentation/networking/dsa/dsa.rst | 4 ----\n net/dsa/slave.c                      | 7 +++++--\n 2 files changed, 5 insertions(+), 6 deletions(-)\n\n--- a/Documentation/networking/dsa/dsa.rst\n+++ b/Documentation/networking/dsa/dsa.rst\n@@ -273,10 +273,6 @@ will not make us go through the switch t\n the Ethernet switch on the other end, expecting a tag will typically drop this\n frame.\n \n-Slave network devices check that the master network device is UP before allowing\n-you to administratively bring UP these slave network devices. A common\n-configuration mistake is forgetting to bring UP the master network device first.\n-\n Interactions with other subsystems\n ==================================\n \n--- a/net/dsa/slave.c\n+++ b/net/dsa/slave.c\n@@ -68,8 +68,11 @@ static int dsa_slave_open(struct net_dev\n \tstruct dsa_port *dp = dsa_slave_to_port(dev);\n \tint err;\n \n-\tif (!(master->flags & IFF_UP))\n-\t\treturn -ENETDOWN;\n+\terr = dev_open(master, NULL);\n+\tif (err < 0) {\n+\t\tnetdev_err(dev, \"failed to open master %s\\n\", master->name);\n+\t\tgoto out;\n+\t}\n \n \tif (!ether_addr_equal(dev->dev_addr, master->dev_addr)) {\n \t\terr = dev_uc_add(master, dev->dev_addr);\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/720-v5.12-net-bridge-notify-switchdev-of-disappearance-of-old-.patch",
    "content": "From 90dc8fd36078a536671adae884d0b929cce6480a Mon Sep 17 00:00:00 2001\nFrom: Vladimir Oltean <vladimir.oltean@nxp.com>\nDate: Wed, 6 Jan 2021 11:51:30 +0200\nSubject: [PATCH] net: bridge: notify switchdev of disappearance of old FDB\n entry upon migration\n\nCurrently the bridge emits atomic switchdev notifications for\ndynamically learnt FDB entries. Monitoring these notifications works\nwonders for switchdev drivers that want to keep their hardware FDB in\nsync with the bridge's FDB.\n\nFor example station A wants to talk to station B in the diagram below,\nand we are concerned with the behavior of the bridge on the DUT device:\n\n                   DUT\n +-------------------------------------+\n |                 br0                 |\n | +------+ +------+ +------+ +------+ |\n | |      | |      | |      | |      | |\n | | swp0 | | swp1 | | swp2 | | eth0 | |\n +-------------------------------------+\n      |        |                  |\n  Station A    |                  |\n               |                  |\n         +--+------+--+    +--+------+--+\n         |  |      |  |    |  |      |  |\n         |  | swp0 |  |    |  | swp0 |  |\n Another |  +------+  |    |  +------+  | Another\n  switch |     br0    |    |     br0    | switch\n         |  +------+  |    |  +------+  |\n         |  |      |  |    |  |      |  |\n         |  | swp1 |  |    |  | swp1 |  |\n         +--+------+--+    +--+------+--+\n                                  |\n                              Station B\n\nInterfaces swp0, swp1, swp2 are handled by a switchdev driver that has\nthe following property: frames injected from its control interface bypass\nthe internal address analyzer logic, and therefore, this hardware does\nnot learn from the source address of packets transmitted by the network\nstack through it. So, since bridging between eth0 (where Station B is\nattached) and swp0 (where Station A is attached) is done in software,\nthe switchdev hardware will never learn the source address of Station B.\nSo the traffic towards that destination will be treated as unknown, i.e.\nflooded.\n\nThis is where the bridge notifications come in handy. When br0 on the\nDUT sees frames with Station B's MAC address on eth0, the switchdev\ndriver gets these notifications and can install a rule to send frames\ntowards Station B's address that are incoming from swp0, swp1, swp2,\nonly towards the control interface. This is all switchdev driver private\nbusiness, which the notification makes possible.\n\nAll is fine until someone unplugs Station B's cable and moves it to the\nother switch:\n\n                   DUT\n +-------------------------------------+\n |                 br0                 |\n | +------+ +------+ +------+ +------+ |\n | |      | |      | |      | |      | |\n | | swp0 | | swp1 | | swp2 | | eth0 | |\n +-------------------------------------+\n      |        |                  |\n  Station A    |                  |\n               |                  |\n         +--+------+--+    +--+------+--+\n         |  |      |  |    |  |      |  |\n         |  | swp0 |  |    |  | swp0 |  |\n Another |  +------+  |    |  +------+  | Another\n  switch |     br0    |    |     br0    | switch\n         |  +------+  |    |  +------+  |\n         |  |      |  |    |  |      |  |\n         |  | swp1 |  |    |  | swp1 |  |\n         +--+------+--+    +--+------+--+\n               |\n           Station B\n\nLuckily for the use cases we care about, Station B is noisy enough that\nthe DUT hears it (on swp1 this time). swp1 receives the frames and\ndelivers them to the bridge, who enters the unlikely path in br_fdb_update\nof updating an existing entry. It moves the entry in the software bridge\nto swp1 and emits an addition notification towards that.\n\nAs far as the switchdev driver is concerned, all that it needs to ensure\nis that traffic between Station A and Station B is not forever broken.\nIf it does nothing, then the stale rule to send frames for Station B\ntowards the control interface remains in place. But Station B is no\nlonger reachable via the control interface, but via a port that can\noffload the bridge port learning attribute. It's just that the port is\nprevented from learning this address, since the rule overrides FDB\nupdates. So the rule needs to go. The question is via what mechanism.\n\nIt sure would be possible for this switchdev driver to keep track of all\naddresses which are sent to the control interface, and then also listen\nfor bridge notifier events on its own ports, searching for the ones that\nhave a MAC address which was previously sent to the control interface.\nBut this is cumbersome and inefficient. Instead, with one small change,\nthe bridge could notify of the address deletion from the old port, in a\nsymmetrical manner with how it did for the insertion. Then the switchdev\ndriver would not be required to monitor learn/forget events for its own\nports. It could just delete the rule towards the control interface upon\nbridge entry migration. This would make hardware address learning be\npossible again. Then it would take a few more packets until the hardware\nand software FDB would be in sync again.\n\nSigned-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>\nAcked-by: Nikolay Aleksandrov <nikolay@nvidia.com>\nReviewed-by: Ido Schimmel <idosch@nvidia.com>\nReviewed-by: Andrew Lunn <andrew@lunn.ch>\nReviewed-by: Florian Fainelli <f.fainelli@gmail.com>\nSigned-off-by: Jakub Kicinski <kuba@kernel.org>\n---\n net/bridge/br_fdb.c | 1 +\n 1 file changed, 1 insertion(+)\n\n--- a/net/bridge/br_fdb.c\n+++ b/net/bridge/br_fdb.c\n@@ -602,6 +602,7 @@ void br_fdb_update(struct net_bridge *br\n \t\t\t/* fastpath: update of existing entry */\n \t\t\tif (unlikely(source != fdb->dst &&\n \t\t\t\t     !test_bit(BR_FDB_STICKY, &fdb->flags))) {\n+\t\t\t\tbr_switchdev_fdb_notify(fdb, RTM_DELNEIGH);\n \t\t\t\tfdb->dst = source;\n \t\t\t\tfdb_modified = true;\n \t\t\t\t/* Take over HW learned entry */\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/721-v5.12-net-dsa-be-louder-when-a-non-legacy-FDB-operation-fa.patch",
    "content": "From 2fd186501b1cff155cc4a755c210793cfc0dffb5 Mon Sep 17 00:00:00 2001\nFrom: Vladimir Oltean <vladimir.oltean@nxp.com>\nDate: Wed, 6 Jan 2021 11:51:31 +0200\nSubject: [PATCH] net: dsa: be louder when a non-legacy FDB operation fails\n\nThe dev_close() call was added in commit c9eb3e0f8701 (\"net: dsa: Add\nsupport for learning FDB through notification\") \"to indicate inconsistent\nsituation\" when we could not delete an FDB entry from the port.\n\nbridge fdb del d8:58:d7:00:ca:6d dev swp0 self master\n\nIt is a bit drastic and at the same time not helpful if the above fails\nto only print with netdev_dbg log level, but on the other hand to bring\nthe interface down.\n\nSo increase the verbosity of the error message, and drop dev_close().\n\nSigned-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>\nReviewed-by: Andrew Lunn <andrew@lunn.ch>\nReviewed-by: Florian Fainelli <f.fainelli@gmail.com>\nSigned-off-by: Jakub Kicinski <kuba@kernel.org>\n---\n net/dsa/slave.c | 10 +++++++---\n 1 file changed, 7 insertions(+), 3 deletions(-)\n\n--- a/net/dsa/slave.c\n+++ b/net/dsa/slave.c\n@@ -2112,7 +2112,9 @@ static void dsa_slave_switchdev_event_wo\n \n \t\terr = dsa_port_fdb_add(dp, fdb_info->addr, fdb_info->vid);\n \t\tif (err) {\n-\t\t\tnetdev_dbg(dev, \"fdb add failed err=%d\\n\", err);\n+\t\t\tnetdev_err(dev,\n+\t\t\t\t   \"failed to add %pM vid %d to fdb: %d\\n\",\n+\t\t\t\t   fdb_info->addr, fdb_info->vid, err);\n \t\t\tbreak;\n \t\t}\n \t\tfdb_info->offloaded = true;\n@@ -2127,9 +2129,11 @@ static void dsa_slave_switchdev_event_wo\n \n \t\terr = dsa_port_fdb_del(dp, fdb_info->addr, fdb_info->vid);\n \t\tif (err) {\n-\t\t\tnetdev_dbg(dev, \"fdb del failed err=%d\\n\", err);\n-\t\t\tdev_close(dev);\n+\t\t\tnetdev_err(dev,\n+\t\t\t\t   \"failed to delete %pM vid %d from fdb: %d\\n\",\n+\t\t\t\t   fdb_info->addr, fdb_info->vid, err);\n \t\t}\n+\n \t\tbreak;\n \t}\n \trtnl_unlock();\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/722-v5.12-net-dsa-don-t-use-switchdev_notifier_fdb_info-in-dsa.patch",
    "content": "From c4bb76a9a0ef87c4cc1f636defed5f12deb9f5a7 Mon Sep 17 00:00:00 2001\nFrom: Vladimir Oltean <vladimir.oltean@nxp.com>\nDate: Wed, 6 Jan 2021 11:51:32 +0200\nSubject: [PATCH] net: dsa: don't use switchdev_notifier_fdb_info in\n dsa_switchdev_event_work\n\nCurrently DSA doesn't add FDB entries on the CPU port, because it only\ndoes so through switchdev, which is associated with a net_device, and\nthere are none of those for the CPU port.\n\nBut actually FDB addresses on the CPU port have some use cases of their\nown, if the switchdev operations are initiated from within the DSA\nlayer. There is just one problem with the existing code: it passes a\nstructure in dsa_switchdev_event_work which was retrieved directly from\nswitchdev, so it contains a net_device. We need to generalize the\ncontents to something that covers the CPU port as well: the \"ds, port\"\ntuple is fine for that.\n\nNote that the new procedure for notifying the successful FDB offload is\ninspired from the rocker model.\n\nAlso, nothing was being done if added_by_user was false. Let's check for\nthat a lot earlier, and don't actually bother to schedule the worker\nfor nothing.\n\nSigned-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>\nReviewed-by: Florian Fainelli <f.fainelli@gmail.com>\nSigned-off-by: Jakub Kicinski <kuba@kernel.org>\n---\n net/dsa/dsa_priv.h |  12 +++++\n net/dsa/slave.c    | 106 ++++++++++++++++++++++-----------------------\n 2 files changed, 65 insertions(+), 53 deletions(-)\n\n--- a/net/dsa/dsa_priv.h\n+++ b/net/dsa/dsa_priv.h\n@@ -73,6 +73,18 @@ struct dsa_notifier_mtu_info {\n \tint mtu;\n };\n \n+struct dsa_switchdev_event_work {\n+\tstruct dsa_switch *ds;\n+\tint port;\n+\tstruct work_struct work;\n+\tunsigned long event;\n+\t/* Specific for SWITCHDEV_FDB_ADD_TO_DEVICE and\n+\t * SWITCHDEV_FDB_DEL_TO_DEVICE\n+\t */\n+\tunsigned char addr[ETH_ALEN];\n+\tu16 vid;\n+};\n+\n struct dsa_slave_priv {\n \t/* Copy of CPU port xmit for faster access in slave transmit hot path */\n \tstruct sk_buff *\t(*xmit)(struct sk_buff *skb,\n--- a/net/dsa/slave.c\n+++ b/net/dsa/slave.c\n@@ -2087,76 +2087,66 @@ static int dsa_slave_netdevice_event(str\n \treturn NOTIFY_DONE;\n }\n \n-struct dsa_switchdev_event_work {\n-\tstruct work_struct work;\n-\tstruct switchdev_notifier_fdb_info fdb_info;\n-\tstruct net_device *dev;\n-\tunsigned long event;\n-};\n+static void\n+dsa_fdb_offload_notify(struct dsa_switchdev_event_work *switchdev_work)\n+{\n+\tstruct dsa_switch *ds = switchdev_work->ds;\n+\tstruct switchdev_notifier_fdb_info info;\n+\tstruct dsa_port *dp;\n+\n+\tif (!dsa_is_user_port(ds, switchdev_work->port))\n+\t\treturn;\n+\n+\tinfo.addr = switchdev_work->addr;\n+\tinfo.vid = switchdev_work->vid;\n+\tinfo.offloaded = true;\n+\tdp = dsa_to_port(ds, switchdev_work->port);\n+\tcall_switchdev_notifiers(SWITCHDEV_FDB_OFFLOADED,\n+\t\t\t\t dp->slave, &info.info, NULL);\n+}\n \n static void dsa_slave_switchdev_event_work(struct work_struct *work)\n {\n \tstruct dsa_switchdev_event_work *switchdev_work =\n \t\tcontainer_of(work, struct dsa_switchdev_event_work, work);\n-\tstruct net_device *dev = switchdev_work->dev;\n-\tstruct switchdev_notifier_fdb_info *fdb_info;\n-\tstruct dsa_port *dp = dsa_slave_to_port(dev);\n+\tstruct dsa_switch *ds = switchdev_work->ds;\n+\tstruct dsa_port *dp;\n \tint err;\n \n+\tdp = dsa_to_port(ds, switchdev_work->port);\n+\n \trtnl_lock();\n \tswitch (switchdev_work->event) {\n \tcase SWITCHDEV_FDB_ADD_TO_DEVICE:\n-\t\tfdb_info = &switchdev_work->fdb_info;\n-\t\tif (!fdb_info->added_by_user)\n-\t\t\tbreak;\n-\n-\t\terr = dsa_port_fdb_add(dp, fdb_info->addr, fdb_info->vid);\n+\t\terr = dsa_port_fdb_add(dp, switchdev_work->addr,\n+\t\t\t\t       switchdev_work->vid);\n \t\tif (err) {\n-\t\t\tnetdev_err(dev,\n-\t\t\t\t   \"failed to add %pM vid %d to fdb: %d\\n\",\n-\t\t\t\t   fdb_info->addr, fdb_info->vid, err);\n+\t\t\tdev_err(ds->dev,\n+\t\t\t\t\"port %d failed to add %pM vid %d to fdb: %d\\n\",\n+\t\t\t\tdp->index, switchdev_work->addr,\n+\t\t\t\tswitchdev_work->vid, err);\n \t\t\tbreak;\n \t\t}\n-\t\tfdb_info->offloaded = true;\n-\t\tcall_switchdev_notifiers(SWITCHDEV_FDB_OFFLOADED, dev,\n-\t\t\t\t\t &fdb_info->info, NULL);\n+\t\tdsa_fdb_offload_notify(switchdev_work);\n \t\tbreak;\n \n \tcase SWITCHDEV_FDB_DEL_TO_DEVICE:\n-\t\tfdb_info = &switchdev_work->fdb_info;\n-\t\tif (!fdb_info->added_by_user)\n-\t\t\tbreak;\n-\n-\t\terr = dsa_port_fdb_del(dp, fdb_info->addr, fdb_info->vid);\n+\t\terr = dsa_port_fdb_del(dp, switchdev_work->addr,\n+\t\t\t\t       switchdev_work->vid);\n \t\tif (err) {\n-\t\t\tnetdev_err(dev,\n-\t\t\t\t   \"failed to delete %pM vid %d from fdb: %d\\n\",\n-\t\t\t\t   fdb_info->addr, fdb_info->vid, err);\n+\t\t\tdev_err(ds->dev,\n+\t\t\t\t\"port %d failed to delete %pM vid %d from fdb: %d\\n\",\n+\t\t\t\tdp->index, switchdev_work->addr,\n+\t\t\t\tswitchdev_work->vid, err);\n \t\t}\n \n \t\tbreak;\n \t}\n \trtnl_unlock();\n \n-\tkfree(switchdev_work->fdb_info.addr);\n \tkfree(switchdev_work);\n-\tdev_put(dev);\n-}\n-\n-static int\n-dsa_slave_switchdev_fdb_work_init(struct dsa_switchdev_event_work *\n-\t\t\t\t  switchdev_work,\n-\t\t\t\t  const struct switchdev_notifier_fdb_info *\n-\t\t\t\t  fdb_info)\n-{\n-\tmemcpy(&switchdev_work->fdb_info, fdb_info,\n-\t       sizeof(switchdev_work->fdb_info));\n-\tswitchdev_work->fdb_info.addr = kzalloc(ETH_ALEN, GFP_ATOMIC);\n-\tif (!switchdev_work->fdb_info.addr)\n-\t\treturn -ENOMEM;\n-\tether_addr_copy((u8 *)switchdev_work->fdb_info.addr,\n-\t\t\tfdb_info->addr);\n-\treturn 0;\n+\tif (dsa_is_user_port(ds, dp->index))\n+\t\tdev_put(dp->slave);\n }\n \n /* Called under rcu_read_lock() */\n@@ -2164,7 +2154,9 @@ static int dsa_slave_switchdev_event(str\n \t\t\t\t     unsigned long event, void *ptr)\n {\n \tstruct net_device *dev = switchdev_notifier_info_to_dev(ptr);\n+\tconst struct switchdev_notifier_fdb_info *fdb_info;\n \tstruct dsa_switchdev_event_work *switchdev_work;\n+\tstruct dsa_port *dp;\n \tint err;\n \n \tif (event == SWITCHDEV_PORT_ATTR_SET) {\n@@ -2177,20 +2169,32 @@ static int dsa_slave_switchdev_event(str\n \tif (!dsa_slave_dev_check(dev))\n \t\treturn NOTIFY_DONE;\n \n+\tdp = dsa_slave_to_port(dev);\n+\n \tswitchdev_work = kzalloc(sizeof(*switchdev_work), GFP_ATOMIC);\n \tif (!switchdev_work)\n \t\treturn NOTIFY_BAD;\n \n \tINIT_WORK(&switchdev_work->work,\n \t\t  dsa_slave_switchdev_event_work);\n-\tswitchdev_work->dev = dev;\n+\tswitchdev_work->ds = dp->ds;\n+\tswitchdev_work->port = dp->index;\n \tswitchdev_work->event = event;\n \n \tswitch (event) {\n \tcase SWITCHDEV_FDB_ADD_TO_DEVICE:\n \tcase SWITCHDEV_FDB_DEL_TO_DEVICE:\n-\t\tif (dsa_slave_switchdev_fdb_work_init(switchdev_work, ptr))\n-\t\t\tgoto err_fdb_work_init;\n+\t\tfdb_info = ptr;\n+\n+\t\tif (!fdb_info->added_by_user) {\n+\t\t\tkfree(switchdev_work);\n+\t\t\treturn NOTIFY_OK;\n+\t\t}\n+\n+\t\tether_addr_copy(switchdev_work->addr,\n+\t\t\t\tfdb_info->addr);\n+\t\tswitchdev_work->vid = fdb_info->vid;\n+\n \t\tdev_hold(dev);\n \t\tbreak;\n \tdefault:\n@@ -2200,10 +2204,6 @@ static int dsa_slave_switchdev_event(str\n \n \tdsa_schedule_work(&switchdev_work->work);\n \treturn NOTIFY_OK;\n-\n-err_fdb_work_init:\n-\tkfree(switchdev_work);\n-\treturn NOTIFY_BAD;\n }\n \n static int dsa_slave_switchdev_blocking_event(struct notifier_block *unused,\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/723-v5.12-net-dsa-move-switchdev-event-implementation-under-th.patch",
    "content": "From 447d290a58bd335d68f665713842365d3d6447df Mon Sep 17 00:00:00 2001\nFrom: Vladimir Oltean <vladimir.oltean@nxp.com>\nDate: Wed, 6 Jan 2021 11:51:33 +0200\nSubject: [PATCH] net: dsa: move switchdev event implementation under the same\n switch/case statement\n\nWe'll need to start listening to SWITCHDEV_FDB_{ADD,DEL}_TO_DEVICE\nevents even for interfaces where dsa_slave_dev_check returns false, so\nwe need that check inside the switch-case statement for SWITCHDEV_FDB_*.\n\nThis movement also avoids a useless allocation / free of switchdev_work\non the untreated \"default event\" case.\n\nSigned-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>\nReviewed-by: Florian Fainelli <f.fainelli@gmail.com>\nSigned-off-by: Jakub Kicinski <kuba@kernel.org>\n---\n net/dsa/slave.c | 35 ++++++++++++++++-------------------\n 1 file changed, 16 insertions(+), 19 deletions(-)\n\n--- a/net/dsa/slave.c\n+++ b/net/dsa/slave.c\n@@ -2159,31 +2159,29 @@ static int dsa_slave_switchdev_event(str\n \tstruct dsa_port *dp;\n \tint err;\n \n-\tif (event == SWITCHDEV_PORT_ATTR_SET) {\n+\tswitch (event) {\n+\tcase SWITCHDEV_PORT_ATTR_SET:\n \t\terr = switchdev_handle_port_attr_set(dev, ptr,\n \t\t\t\t\t\t     dsa_slave_dev_check,\n \t\t\t\t\t\t     dsa_slave_port_attr_set);\n \t\treturn notifier_from_errno(err);\n-\t}\n-\n-\tif (!dsa_slave_dev_check(dev))\n-\t\treturn NOTIFY_DONE;\n+\tcase SWITCHDEV_FDB_ADD_TO_DEVICE:\n+\tcase SWITCHDEV_FDB_DEL_TO_DEVICE:\n+\t\tif (!dsa_slave_dev_check(dev))\n+\t\t\treturn NOTIFY_DONE;\n \n-\tdp = dsa_slave_to_port(dev);\n+\t\tdp = dsa_slave_to_port(dev);\n \n-\tswitchdev_work = kzalloc(sizeof(*switchdev_work), GFP_ATOMIC);\n-\tif (!switchdev_work)\n-\t\treturn NOTIFY_BAD;\n-\n-\tINIT_WORK(&switchdev_work->work,\n-\t\t  dsa_slave_switchdev_event_work);\n-\tswitchdev_work->ds = dp->ds;\n-\tswitchdev_work->port = dp->index;\n-\tswitchdev_work->event = event;\n+\t\tswitchdev_work = kzalloc(sizeof(*switchdev_work), GFP_ATOMIC);\n+\t\tif (!switchdev_work)\n+\t\t\treturn NOTIFY_BAD;\n+\n+\t\tINIT_WORK(&switchdev_work->work,\n+\t\t\t  dsa_slave_switchdev_event_work);\n+\t\tswitchdev_work->ds = dp->ds;\n+\t\tswitchdev_work->port = dp->index;\n+\t\tswitchdev_work->event = event;\n \n-\tswitch (event) {\n-\tcase SWITCHDEV_FDB_ADD_TO_DEVICE:\n-\tcase SWITCHDEV_FDB_DEL_TO_DEVICE:\n \t\tfdb_info = ptr;\n \n \t\tif (!fdb_info->added_by_user) {\n@@ -2196,13 +2194,12 @@ static int dsa_slave_switchdev_event(str\n \t\tswitchdev_work->vid = fdb_info->vid;\n \n \t\tdev_hold(dev);\n+\t\tdsa_schedule_work(&switchdev_work->work);\n \t\tbreak;\n \tdefault:\n-\t\tkfree(switchdev_work);\n \t\treturn NOTIFY_DONE;\n \t}\n \n-\tdsa_schedule_work(&switchdev_work->work);\n \treturn NOTIFY_OK;\n }\n \n"
  },
  {
    "path": "target/linux/generic/backport-5.10/724-v5.12-net-dsa-exit-early-in-dsa_slave_switchdev_event-if-w.patch",
    "content": "From 5fb4a451a87d8ed3363d28b63a3295399373d6c4 Mon Sep 17 00:00:00 2001\nFrom: Vladimir Oltean <vladimir.oltean@nxp.com>\nDate: Wed, 6 Jan 2021 11:51:34 +0200\nSubject: [PATCH] net: dsa: exit early in dsa_slave_switchdev_event if we can't\n program the FDB\n\nRight now, the following would happen for a switch driver that does not\nimplement .port_fdb_add or .port_fdb_del.\n\ndsa_slave_switchdev_event returns NOTIFY_OK and schedules:\n-> dsa_slave_switchdev_event_work\n   -> dsa_port_fdb_add\n      -> dsa_port_notify(DSA_NOTIFIER_FDB_ADD)\n         -> dsa_switch_fdb_add\n            -> if (!ds->ops->port_fdb_add) return -EOPNOTSUPP;\n   -> an error is printed with dev_dbg, and\n      dsa_fdb_offload_notify(switchdev_work) is not called.\n\nWe can avoid scheduling the worker for nothing and say NOTIFY_DONE.\nBecause we don't call dsa_fdb_offload_notify, the static FDB entry will\nremain just in the software bridge.\n\nSigned-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>\nReviewed-by: Florian Fainelli <f.fainelli@gmail.com>\nReviewed-by: Andrew Lunn <andrew@lunn.ch>\nSigned-off-by: Jakub Kicinski <kuba@kernel.org>\n---\n net/dsa/slave.c | 3 +++\n 1 file changed, 3 insertions(+)\n\n--- a/net/dsa/slave.c\n+++ b/net/dsa/slave.c\n@@ -2172,6 +2172,9 @@ static int dsa_slave_switchdev_event(str\n \n \t\tdp = dsa_slave_to_port(dev);\n \n+\t\tif (!dp->ds->ops->port_fdb_add || !dp->ds->ops->port_fdb_del)\n+\t\t\treturn NOTIFY_DONE;\n+\n \t\tswitchdev_work = kzalloc(sizeof(*switchdev_work), GFP_ATOMIC);\n \t\tif (!switchdev_work)\n \t\t\treturn NOTIFY_BAD;\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/725-v5.12-net-dsa-listen-for-SWITCHDEV_-FDB-DEL-_ADD_TO_DEVICE.patch",
    "content": "From d5f19486cee79d04c054427577ac96ed123706db Mon Sep 17 00:00:00 2001\nFrom: Vladimir Oltean <vladimir.oltean@nxp.com>\nDate: Wed, 6 Jan 2021 11:51:35 +0200\nSubject: [PATCH] net: dsa: listen for SWITCHDEV_{FDB,DEL}_ADD_TO_DEVICE on\n foreign bridge neighbors\n\nSome DSA switches (and not only) cannot learn source MAC addresses from\npackets injected from the CPU. They only perform hardware address\nlearning from inbound traffic.\n\nThis can be problematic when we have a bridge spanning some DSA switch\nports and some non-DSA ports (which we'll call \"foreign interfaces\" from\nDSA's perspective).\n\nThere are 2 classes of problems created by the lack of learning on\nCPU-injected traffic:\n- excessive flooding, due to the fact that DSA treats those addresses as\n  unknown\n- the risk of stale routes, which can lead to temporary packet loss\n\nTo illustrate the second class, consider the following situation, which\nis common in production equipment (wireless access points, where there\nis a WLAN interface and an Ethernet switch, and these form a single\nbridging domain).\n\n AP 1:\n +------------------------------------------------------------------------+\n |                                          br0                           |\n +------------------------------------------------------------------------+\n +------------+ +------------+ +------------+ +------------+ +------------+\n |    swp0    | |    swp1    | |    swp2    | |    swp3    | |    wlan0   |\n +------------+ +------------+ +------------+ +------------+ +------------+\n       |                                                       ^        ^\n       |                                                       |        |\n       |                                                       |        |\n       |                                                    Client A  Client B\n       |\n       |\n       |\n +------------+ +------------+ +------------+ +------------+ +------------+\n |    swp0    | |    swp1    | |    swp2    | |    swp3    | |    wlan0   |\n +------------+ +------------+ +------------+ +------------+ +------------+\n +------------------------------------------------------------------------+\n |                                          br0                           |\n +------------------------------------------------------------------------+\n AP 2\n\n- br0 of AP 1 will know that Clients A and B are reachable via wlan0\n- the hardware fdb of a DSA switch driver today is not kept in sync with\n  the software entries on other bridge ports, so it will not know that\n  clients A and B are reachable via the CPU port UNLESS the hardware\n  switch itself performs SA learning from traffic injected from the CPU.\n  Nonetheless, a substantial number of switches don't.\n- the hardware fdb of the DSA switch on AP 2 may autonomously learn that\n  Client A and B are reachable through swp0. Therefore, the software br0\n  of AP 2 also may or may not learn this. In the example we're\n  illustrating, some Ethernet traffic has been going on, and br0 from AP\n  2 has indeed learnt that it can reach Client B through swp0.\n\nOne of the wireless clients, say Client B, disconnects from AP 1 and\nroams to AP 2. The topology now looks like this:\n\n AP 1:\n +------------------------------------------------------------------------+\n |                                          br0                           |\n +------------------------------------------------------------------------+\n +------------+ +------------+ +------------+ +------------+ +------------+\n |    swp0    | |    swp1    | |    swp2    | |    swp3    | |    wlan0   |\n +------------+ +------------+ +------------+ +------------+ +------------+\n       |                                                            ^\n       |                                                            |\n       |                                                         Client A\n       |\n       |\n       |                                                         Client B\n       |                                                            |\n       |                                                            v\n +------------+ +------------+ +------------+ +------------+ +------------+\n |    swp0    | |    swp1    | |    swp2    | |    swp3    | |    wlan0   |\n +------------+ +------------+ +------------+ +------------+ +------------+\n +------------------------------------------------------------------------+\n |                                          br0                           |\n +------------------------------------------------------------------------+\n AP 2\n\n- br0 of AP 1 still knows that Client A is reachable via wlan0 (no change)\n- br0 of AP 1 will (possibly) know that Client B has left wlan0. There\n  are cases where it might never find out though. Either way, DSA today\n  does not process that notification in any way.\n- the hardware FDB of the DSA switch on AP 1 may learn autonomously that\n  Client B can be reached via swp0, if it receives any packet with\n  Client 1's source MAC address over Ethernet.\n- the hardware FDB of the DSA switch on AP 2 still thinks that Client B\n  can be reached via swp0. It does not know that it has roamed to wlan0,\n  because it doesn't perform SA learning from the CPU port.\n\nNow Client A contacts Client B.\nAP 1 routes the packet fine towards swp0 and delivers it on the Ethernet\nsegment.\nAP 2 sees a frame on swp0 and its fdb says that the destination is swp0.\nHairpinning is disabled => drop.\n\nThis problem comes from the fact that these switches have a 'blind spot'\nfor addresses coming from software bridging. The generic solution is not\nto assume that hardware learning can be enabled somehow, but to listen\nto more bridge learning events. It turns out that the bridge driver does\nlearn in software from all inbound frames, in __br_handle_local_finish.\nA proper SWITCHDEV_FDB_ADD_TO_DEVICE notification is emitted for the\naddresses serviced by the bridge on 'foreign' interfaces. The software\nbridge also does the right thing on migration, by notifying that the old\nentry is deleted, so that does not need to be special-cased in DSA. When\nit is deleted, we just need to delete our static FDB entry towards the\nCPU too, and wait.\n\nThe problem is that DSA currently only cares about SWITCHDEV_FDB_ADD_TO_DEVICE\nevents received on its own interfaces, such as static FDB entries.\n\nLuckily we can change that, and DSA can listen to all switchdev FDB\nadd/del events in the system and figure out if those events were emitted\nby a bridge that spans at least one of DSA's own ports. In case that is\ntrue, DSA will also offload that address towards its own CPU port, in\nthe eventuality that there might be bridge clients attached to the DSA\nswitch who want to talk to the station connected to the foreign\ninterface.\n\nIn terms of implementation, we need to keep the fdb_info->added_by_user\ncheck for the case where the switchdev event was targeted directly at a\nDSA switch port. But we don't need to look at that flag for snooped\nevents. So the check is currently too late, we need to move it earlier.\nThis also simplifies the code a bit, since we avoid uselessly allocating\nand freeing switchdev_work.\n\nWe could probably do some improvements in the future. For example,\nmulti-bridge support is rudimentary at the moment. If there are two\nbridges spanning a DSA switch's ports, and both of them need to service\nthe same MAC address, then what will happen is that the migration of one\nof those stations will trigger the deletion of the FDB entry from the\nCPU port while it is still used by other bridge. That could be improved\nwith reference counting but is left for another time.\n\nThis behavior needs to be enabled at driver level by setting\nds->assisted_learning_on_cpu_port = true. This is because we don't want\nto inflict a potential performance penalty (accesses through\nMDIO/I2C/SPI are expensive) to hardware that really doesn't need it\nbecause address learning on the CPU port works there.\n\nReported-by: DENG Qingfang <dqfext@gmail.com>\nSigned-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>\nReviewed-by: Florian Fainelli <f.fainelli@gmail.com>\nReviewed-by: Andrew Lunn <andrew@lunn.ch>\nSigned-off-by: Jakub Kicinski <kuba@kernel.org>\n---\n include/net/dsa.h |  5 +++++\n net/dsa/slave.c   | 66 +++++++++++++++++++++++++++++++++++++++++++++----------\n 2 files changed, 60 insertions(+), 11 deletions(-)\n\n--- a/include/net/dsa.h\n+++ b/include/net/dsa.h\n@@ -317,6 +317,11 @@ struct dsa_switch {\n \t */\n \tbool\t\t\tuntag_bridge_pvid;\n \n+\t/* Let DSA manage the FDB entries towards the CPU, based on the\n+\t * software bridge database.\n+\t */\n+\tbool\t\t\tassisted_learning_on_cpu_port;\n+\n \t/* In case vlan_filtering_is_global is set, the VLAN awareness state\n \t * should be retrieved from here and not from the per-port settings.\n \t */\n--- a/net/dsa/slave.c\n+++ b/net/dsa/slave.c\n@@ -2149,6 +2149,28 @@ static void dsa_slave_switchdev_event_wo\n \t\tdev_put(dp->slave);\n }\n \n+static int dsa_lower_dev_walk(struct net_device *lower_dev,\n+\t\t\t      struct netdev_nested_priv *priv)\n+{\n+\tif (dsa_slave_dev_check(lower_dev)) {\n+\t\tpriv->data = (void *)netdev_priv(lower_dev);\n+\t\treturn 1;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static struct dsa_slave_priv *dsa_slave_dev_lower_find(struct net_device *dev)\n+{\n+\tstruct netdev_nested_priv priv = {\n+\t\t.data = NULL,\n+\t};\n+\n+\tnetdev_walk_all_lower_dev_rcu(dev, dsa_lower_dev_walk, &priv);\n+\n+\treturn (struct dsa_slave_priv *)priv.data;\n+}\n+\n /* Called under rcu_read_lock() */\n static int dsa_slave_switchdev_event(struct notifier_block *unused,\n \t\t\t\t     unsigned long event, void *ptr)\n@@ -2167,10 +2189,37 @@ static int dsa_slave_switchdev_event(str\n \t\treturn notifier_from_errno(err);\n \tcase SWITCHDEV_FDB_ADD_TO_DEVICE:\n \tcase SWITCHDEV_FDB_DEL_TO_DEVICE:\n-\t\tif (!dsa_slave_dev_check(dev))\n-\t\t\treturn NOTIFY_DONE;\n+\t\tfdb_info = ptr;\n+\n+\t\tif (dsa_slave_dev_check(dev)) {\n+\t\t\tif (!fdb_info->added_by_user)\n+\t\t\t\treturn NOTIFY_OK;\n+\n+\t\t\tdp = dsa_slave_to_port(dev);\n+\t\t} else {\n+\t\t\t/* Snoop addresses learnt on foreign interfaces\n+\t\t\t * bridged with us, for switches that don't\n+\t\t\t * automatically learn SA from CPU-injected traffic\n+\t\t\t */\n+\t\t\tstruct net_device *br_dev;\n+\t\t\tstruct dsa_slave_priv *p;\n+\n+\t\t\tbr_dev = netdev_master_upper_dev_get_rcu(dev);\n+\t\t\tif (!br_dev)\n+\t\t\t\treturn NOTIFY_DONE;\n+\n+\t\t\tif (!netif_is_bridge_master(br_dev))\n+\t\t\t\treturn NOTIFY_DONE;\n+\n+\t\t\tp = dsa_slave_dev_lower_find(br_dev);\n+\t\t\tif (!p)\n+\t\t\t\treturn NOTIFY_DONE;\n \n-\t\tdp = dsa_slave_to_port(dev);\n+\t\t\tdp = p->dp->cpu_dp;\n+\n+\t\t\tif (!dp->ds->assisted_learning_on_cpu_port)\n+\t\t\t\treturn NOTIFY_DONE;\n+\t\t}\n \n \t\tif (!dp->ds->ops->port_fdb_add || !dp->ds->ops->port_fdb_del)\n \t\t\treturn NOTIFY_DONE;\n@@ -2185,18 +2234,13 @@ static int dsa_slave_switchdev_event(str\n \t\tswitchdev_work->port = dp->index;\n \t\tswitchdev_work->event = event;\n \n-\t\tfdb_info = ptr;\n-\n-\t\tif (!fdb_info->added_by_user) {\n-\t\t\tkfree(switchdev_work);\n-\t\t\treturn NOTIFY_OK;\n-\t\t}\n-\n \t\tether_addr_copy(switchdev_work->addr,\n \t\t\t\tfdb_info->addr);\n \t\tswitchdev_work->vid = fdb_info->vid;\n \n-\t\tdev_hold(dev);\n+\t\t/* Hold a reference on the slave for dsa_fdb_offload_notify */\n+\t\tif (dsa_is_user_port(dp->ds, dp->index))\n+\t\t\tdev_hold(dev);\n \t\tdsa_schedule_work(&switchdev_work->work);\n \t\tbreak;\n \tdefault:\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/730-net-dsa-mt7530-setup-core-clock-even-in-TRGMII-mode.patch",
    "content": "From c3b8e07909dbe67b0d580416c1a5257643a73be7 Mon Sep 17 00:00:00 2001\nFrom: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com>\nDate: Fri, 12 Mar 2021 00:07:03 -0800\nSubject: [PATCH] net: dsa: mt7530: setup core clock even in TRGMII mode\n\nA recent change to MIPS ralink reset logic made it so mt7530 actually\nresets the switch on platforms such as mt7621 (where bit 2 is the reset\nline for the switch). That exposed an issue where the switch would not\nfunction properly in TRGMII mode after a reset.\n\nReconfigure core clock in TRGMII mode to fix the issue.\n\nTested on Ubiquiti ER-X (MT7621) with TRGMII mode enabled.\n\nFixes: 3f9ef7785a9c (\"MIPS: ralink: manage low reset lines\")\nSigned-off-by: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/dsa/mt7530.c | 52 +++++++++++++++++++---------------------\n 1 file changed, 25 insertions(+), 27 deletions(-)\n\n--- a/drivers/net/dsa/mt7530.c\n+++ b/drivers/net/dsa/mt7530.c\n@@ -436,34 +436,32 @@ mt7530_pad_clk_setup(struct dsa_switch *\n \t\t\t     TD_DM_DRVP(8) | TD_DM_DRVN(8));\n \n \t/* Setup core clock for MT7530 */\n-\tif (!trgint) {\n-\t\t/* Disable MT7530 core clock */\n-\t\tcore_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);\n-\n-\t\t/* Disable PLL, since phy_device has not yet been created\n-\t\t * provided for phy_[read,write]_mmd_indirect is called, we\n-\t\t * provide our own core_write_mmd_indirect to complete this\n-\t\t * function.\n-\t\t */\n-\t\tcore_write_mmd_indirect(priv,\n-\t\t\t\t\tCORE_GSWPLL_GRP1,\n-\t\t\t\t\tMDIO_MMD_VEND2,\n-\t\t\t\t\t0);\n-\n-\t\t/* Set core clock into 500Mhz */\n-\t\tcore_write(priv, CORE_GSWPLL_GRP2,\n-\t\t\t   RG_GSWPLL_POSDIV_500M(1) |\n-\t\t\t   RG_GSWPLL_FBKDIV_500M(25));\n-\n-\t\t/* Enable PLL */\n-\t\tcore_write(priv, CORE_GSWPLL_GRP1,\n-\t\t\t   RG_GSWPLL_EN_PRE |\n-\t\t\t   RG_GSWPLL_POSDIV_200M(2) |\n-\t\t\t   RG_GSWPLL_FBKDIV_200M(32));\n-\n-\t\t/* Enable MT7530 core clock */\n-\t\tcore_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);\n-\t}\n+\t/* Disable MT7530 core clock */\n+\tcore_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);\n+\n+\t/* Disable PLL, since phy_device has not yet been created\n+\t * provided for phy_[read,write]_mmd_indirect is called, we\n+\t * provide our own core_write_mmd_indirect to complete this\n+\t * function.\n+\t */\n+\tcore_write_mmd_indirect(priv,\n+\t\t\t\tCORE_GSWPLL_GRP1,\n+\t\t\t\tMDIO_MMD_VEND2,\n+\t\t\t\t0);\n+\n+\t/* Set core clock into 500Mhz */\n+\tcore_write(priv, CORE_GSWPLL_GRP2,\n+\t\t   RG_GSWPLL_POSDIV_500M(1) |\n+\t\t   RG_GSWPLL_FBKDIV_500M(25));\n+\n+\t/* Enable PLL */\n+\tcore_write(priv, CORE_GSWPLL_GRP1,\n+\t\t   RG_GSWPLL_EN_PRE |\n+\t\t   RG_GSWPLL_POSDIV_200M(2) |\n+\t\t   RG_GSWPLL_FBKDIV_200M(32));\n+\n+\t/* Enable MT7530 core clock */\n+\tcore_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);\n \n \t/* Setup the MT7530 TRGMII Tx Clock */\n \tcore_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/731-v5.12-net-dsa-mt7530-MT7530-optional-GPIO-support.patch",
    "content": "From 429a0edeefd88cbfca5c417dfb8561047bb50769 Mon Sep 17 00:00:00 2001\nFrom: DENG Qingfang <dqfext@gmail.com>\nDate: Mon, 25 Jan 2021 12:43:22 +0800\nSubject: [PATCH] net: dsa: mt7530: MT7530 optional GPIO support\n\nMT7530's LED controller can drive up to 15 LED/GPIOs.\n\nAdd support for GPIO control and allow users to use its GPIOs by\nsetting gpio-controller property in device tree.\n\nSigned-off-by: DENG Qingfang <dqfext@gmail.com>\nReviewed-by: Linus Walleij <linus.walleij@linaro.org>\nReviewed-by: Andrew Lunn <andrew@lunn.ch>\nSigned-off-by: Jakub Kicinski <kuba@kernel.org>\n---\n drivers/net/dsa/mt7530.c | 110 +++++++++++++++++++++++++++++++++++++++\n drivers/net/dsa/mt7530.h |  20 +++++++\n 2 files changed, 130 insertions(+)\n\n--- a/drivers/net/dsa/mt7530.c\n+++ b/drivers/net/dsa/mt7530.c\n@@ -18,6 +18,7 @@\n #include <linux/regulator/consumer.h>\n #include <linux/reset.h>\n #include <linux/gpio/consumer.h>\n+#include <linux/gpio/driver.h>\n #include <net/dsa.h>\n \n #include \"mt7530.h\"\n@@ -1534,6 +1535,109 @@ mtk_get_tag_protocol(struct dsa_switch *\n \t}\n }\n \n+static inline u32\n+mt7530_gpio_to_bit(unsigned int offset)\n+{\n+\t/* Map GPIO offset to register bit\n+\t * [ 2: 0]  port 0 LED 0..2 as GPIO 0..2\n+\t * [ 6: 4]  port 1 LED 0..2 as GPIO 3..5\n+\t * [10: 8]  port 2 LED 0..2 as GPIO 6..8\n+\t * [14:12]  port 3 LED 0..2 as GPIO 9..11\n+\t * [18:16]  port 4 LED 0..2 as GPIO 12..14\n+\t */\n+\treturn BIT(offset + offset / 3);\n+}\n+\n+static int\n+mt7530_gpio_get(struct gpio_chip *gc, unsigned int offset)\n+{\n+\tstruct mt7530_priv *priv = gpiochip_get_data(gc);\n+\tu32 bit = mt7530_gpio_to_bit(offset);\n+\n+\treturn !!(mt7530_read(priv, MT7530_LED_GPIO_DATA) & bit);\n+}\n+\n+static void\n+mt7530_gpio_set(struct gpio_chip *gc, unsigned int offset, int value)\n+{\n+\tstruct mt7530_priv *priv = gpiochip_get_data(gc);\n+\tu32 bit = mt7530_gpio_to_bit(offset);\n+\n+\tif (value)\n+\t\tmt7530_set(priv, MT7530_LED_GPIO_DATA, bit);\n+\telse\n+\t\tmt7530_clear(priv, MT7530_LED_GPIO_DATA, bit);\n+}\n+\n+static int\n+mt7530_gpio_get_direction(struct gpio_chip *gc, unsigned int offset)\n+{\n+\tstruct mt7530_priv *priv = gpiochip_get_data(gc);\n+\tu32 bit = mt7530_gpio_to_bit(offset);\n+\n+\treturn (mt7530_read(priv, MT7530_LED_GPIO_DIR) & bit) ?\n+\t\tGPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN;\n+}\n+\n+static int\n+mt7530_gpio_direction_input(struct gpio_chip *gc, unsigned int offset)\n+{\n+\tstruct mt7530_priv *priv = gpiochip_get_data(gc);\n+\tu32 bit = mt7530_gpio_to_bit(offset);\n+\n+\tmt7530_clear(priv, MT7530_LED_GPIO_OE, bit);\n+\tmt7530_clear(priv, MT7530_LED_GPIO_DIR, bit);\n+\n+\treturn 0;\n+}\n+\n+static int\n+mt7530_gpio_direction_output(struct gpio_chip *gc, unsigned int offset, int value)\n+{\n+\tstruct mt7530_priv *priv = gpiochip_get_data(gc);\n+\tu32 bit = mt7530_gpio_to_bit(offset);\n+\n+\tmt7530_set(priv, MT7530_LED_GPIO_DIR, bit);\n+\n+\tif (value)\n+\t\tmt7530_set(priv, MT7530_LED_GPIO_DATA, bit);\n+\telse\n+\t\tmt7530_clear(priv, MT7530_LED_GPIO_DATA, bit);\n+\n+\tmt7530_set(priv, MT7530_LED_GPIO_OE, bit);\n+\n+\treturn 0;\n+}\n+\n+static int\n+mt7530_setup_gpio(struct mt7530_priv *priv)\n+{\n+\tstruct device *dev = priv->dev;\n+\tstruct gpio_chip *gc;\n+\n+\tgc = devm_kzalloc(dev, sizeof(*gc), GFP_KERNEL);\n+\tif (!gc)\n+\t\treturn -ENOMEM;\n+\n+\tmt7530_write(priv, MT7530_LED_GPIO_OE, 0);\n+\tmt7530_write(priv, MT7530_LED_GPIO_DIR, 0);\n+\tmt7530_write(priv, MT7530_LED_IO_MODE, 0);\n+\n+\tgc->label = \"mt7530\";\n+\tgc->parent = dev;\n+\tgc->owner = THIS_MODULE;\n+\tgc->get_direction = mt7530_gpio_get_direction;\n+\tgc->direction_input = mt7530_gpio_direction_input;\n+\tgc->direction_output = mt7530_gpio_direction_output;\n+\tgc->get = mt7530_gpio_get;\n+\tgc->set = mt7530_gpio_set;\n+\tgc->base = -1;\n+\tgc->ngpio = 15;\n+\tgc->can_sleep = true;\n+\n+\treturn devm_gpiochip_add_data(dev, gc, priv);\n+}\n+\n static int\n mt7530_setup(struct dsa_switch *ds)\n {\n@@ -1675,6 +1779,12 @@ mt7530_setup(struct dsa_switch *ds)\n \t\t}\n \t}\n \n+\tif (of_property_read_bool(priv->dev->of_node, \"gpio-controller\")) {\n+\t\tret = mt7530_setup_gpio(priv);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\t}\n+\n \tmt7530_setup_port5(ds, interface);\n \n \t/* Flush the FDB table */\n--- a/drivers/net/dsa/mt7530.h\n+++ b/drivers/net/dsa/mt7530.h\n@@ -529,6 +529,26 @@ enum mt7531_clk_skew {\n #define  MT7531_GPIO12_RG_RXD3_MASK\tGENMASK(19, 16)\n #define  MT7531_EXT_P_MDIO_12\t\t(2 << 16)\n \n+/* Registers for LED GPIO control (MT7530 only)\n+ * All registers follow this pattern:\n+ * [ 2: 0]  port 0\n+ * [ 6: 4]  port 1\n+ * [10: 8]  port 2\n+ * [14:12]  port 3\n+ * [18:16]  port 4\n+ */\n+\n+/* LED enable, 0: Disable, 1: Enable (Default) */\n+#define MT7530_LED_EN\t\t\t0x7d00\n+/* LED mode, 0: GPIO mode, 1: PHY mode (Default) */\n+#define MT7530_LED_IO_MODE\t\t0x7d04\n+/* GPIO direction, 0: Input, 1: Output */\n+#define MT7530_LED_GPIO_DIR\t\t0x7d10\n+/* GPIO output enable, 0: Disable, 1: Enable */\n+#define MT7530_LED_GPIO_OE\t\t0x7d14\n+/* GPIO value, 0: Low, 1: High */\n+#define MT7530_LED_GPIO_DATA\t\t0x7d18\n+\n #define MT7530_CREV\t\t\t0x7ffc\n #define  CHIP_NAME_SHIFT\t\t16\n #define  MT7530_ID\t\t\t0x7530\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/731-v5.13-net-dsa-mt7530-Add-support-for-EEE-features.patch",
    "content": "From 40b5d2f15c091fa9c854acde91ad2acb504027d7 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Ren=C3=A9=20van=20Dorst?= <opensource@vdorst.com>\nDate: Mon, 12 Apr 2021 08:50:31 +0200\nSubject: [PATCH] net: dsa: mt7530: Add support for EEE features\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nThis patch adds EEE support.\n\nSigned-off-by: René van Dorst <opensource@vdorst.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/dsa/mt7530.c | 43 ++++++++++++++++++++++++++++++++++++++++\n drivers/net/dsa/mt7530.h | 14 ++++++++++++-\n 2 files changed, 56 insertions(+), 1 deletion(-)\n\n--- a/drivers/net/dsa/mt7530.c\n+++ b/drivers/net/dsa/mt7530.c\n@@ -2371,6 +2371,17 @@ static void mt753x_phylink_mac_link_up(s\n \t\t\tmcr |= PMCR_RX_FC_EN;\n \t}\n \n+\tif (mode == MLO_AN_PHY && phydev && phy_init_eee(phydev, 0) >= 0) {\n+\t\tswitch (speed) {\n+\t\tcase SPEED_1000:\n+\t\t\tmcr |= PMCR_FORCE_EEE1G;\n+\t\t\tbreak;\n+\t\tcase SPEED_100:\n+\t\t\tmcr |= PMCR_FORCE_EEE100;\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\n \tmt7530_set(priv, MT7530_PMCR_P(port), mcr);\n }\n \n@@ -2601,6 +2612,36 @@ mt753x_phy_write(struct dsa_switch *ds,\n \treturn priv->info->phy_write(ds, port, regnum, val);\n }\n \n+static int mt753x_get_mac_eee(struct dsa_switch *ds, int port,\n+\t\t\t      struct ethtool_eee *e)\n+{\n+\tstruct mt7530_priv *priv = ds->priv;\n+\tu32 eeecr = mt7530_read(priv, MT7530_PMEEECR_P(port));\n+\n+\te->tx_lpi_enabled = !(eeecr & LPI_MODE_EN);\n+\te->tx_lpi_timer = GET_LPI_THRESH(eeecr);\n+\n+\treturn 0;\n+}\n+\n+static int mt753x_set_mac_eee(struct dsa_switch *ds, int port,\n+\t\t\t      struct ethtool_eee *e)\n+{\n+\tstruct mt7530_priv *priv = ds->priv;\n+\tu32 set, mask = LPI_THRESH_MASK | LPI_MODE_EN;\n+\n+\tif (e->tx_lpi_timer > 0xFFF)\n+\t\treturn -EINVAL;\n+\n+\tset = SET_LPI_THRESH(e->tx_lpi_timer);\n+\tif (!e->tx_lpi_enabled)\n+\t\t/* Force LPI Mode without a delay */\n+\t\tset |= LPI_MODE_EN;\n+\tmt7530_rmw(priv, MT7530_PMEEECR_P(port), mask, set);\n+\n+\treturn 0;\n+}\n+\n static const struct dsa_switch_ops mt7530_switch_ops = {\n \t.get_tag_protocol\t= mtk_get_tag_protocol,\n \t.setup\t\t\t= mt753x_setup,\n@@ -2629,6 +2670,8 @@ static const struct dsa_switch_ops mt753\n \t.phylink_mac_an_restart\t= mt753x_phylink_mac_an_restart,\n \t.phylink_mac_link_down\t= mt753x_phylink_mac_link_down,\n \t.phylink_mac_link_up\t= mt753x_phylink_mac_link_up,\n+\t.get_mac_eee\t\t= mt753x_get_mac_eee,\n+\t.set_mac_eee\t\t= mt753x_set_mac_eee,\n };\n \n static const struct mt753x_info mt753x_table[] = {\n--- a/drivers/net/dsa/mt7530.h\n+++ b/drivers/net/dsa/mt7530.h\n@@ -240,6 +240,8 @@ enum mt7530_vlan_port_attr {\n #define  PMCR_RX_EN\t\t\tBIT(13)\n #define  PMCR_BACKOFF_EN\t\tBIT(9)\n #define  PMCR_BACKPR_EN\t\t\tBIT(8)\n+#define  PMCR_FORCE_EEE1G\t\tBIT(7)\n+#define  PMCR_FORCE_EEE100\t\tBIT(6)\n #define  PMCR_TX_FC_EN\t\t\tBIT(5)\n #define  PMCR_RX_FC_EN\t\t\tBIT(4)\n #define  PMCR_FORCE_SPEED_1000\t\tBIT(3)\n@@ -264,7 +266,8 @@ enum mt7530_vlan_port_attr {\n #define  PMCR_LINK_SETTINGS_MASK\t(PMCR_TX_EN | PMCR_FORCE_SPEED_1000 | \\\n \t\t\t\t\t PMCR_RX_EN | PMCR_FORCE_SPEED_100 | \\\n \t\t\t\t\t PMCR_TX_FC_EN | PMCR_RX_FC_EN | \\\n-\t\t\t\t\t PMCR_FORCE_FDX | PMCR_FORCE_LNK)\n+\t\t\t\t\t PMCR_FORCE_FDX | PMCR_FORCE_LNK | \\\n+\t\t\t\t\t PMCR_FORCE_EEE1G | PMCR_FORCE_EEE100)\n #define  PMCR_CPU_PORT_SETTING(id)\t(PMCR_FORCE_MODE_ID((id)) | \\\n \t\t\t\t\t PMCR_IFG_XMIT(1) | PMCR_MAC_MODE | \\\n \t\t\t\t\t PMCR_BACKOFF_EN | PMCR_BACKPR_EN | \\\n@@ -273,6 +276,15 @@ enum mt7530_vlan_port_attr {\n \t\t\t\t\t PMCR_FORCE_SPEED_1000 | \\\n \t\t\t\t\t PMCR_FORCE_FDX | PMCR_FORCE_LNK)\n \n+#define MT7530_PMEEECR_P(x)\t\t(0x3004 + (x) * 0x100)\n+#define  WAKEUP_TIME_1000(x)\t\t(((x) & 0xFF) << 24)\n+#define  WAKEUP_TIME_100(x)\t\t(((x) & 0xFF) << 16)\n+#define  LPI_THRESH_MASK\t\tGENMASK(15, 4)\n+#define  LPI_THRESH_SHT\t\t\t4\n+#define  SET_LPI_THRESH(x)\t\t(((x) << LPI_THRESH_SHT) & LPI_THRESH_MASK)\n+#define  GET_LPI_THRESH(x)\t\t(((x) & LPI_THRESH_MASK) >> LPI_THRESH_SHT)\n+#define  LPI_MODE_EN\t\t\tBIT(0)\n+\n #define MT7530_PMSR_P(x)\t\t(0x3008 + (x) * 0x100)\n #define  PMSR_EEE1G\t\t\tBIT(7)\n #define  PMSR_EEE100M\t\t\tBIT(6)\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/732-net-next-1-of-net-pass-the-dst-buffer-to-of_get_mac_address.patch",
    "content": "From 83216e3988cd196183542937c9bd58b279f946af Mon Sep 17 00:00:00 2001\nFrom: Michael Walle <michael@walle.cc>\nDate: Mon, 12 Apr 2021 19:47:17 +0200\nSubject: of: net: pass the dst buffer to of_get_mac_address()\n\nof_get_mac_address() returns a \"const void*\" pointer to a MAC address.\nLately, support to fetch the MAC address by an NVMEM provider was added.\nBut this will only work with platform devices. It will not work with\nPCI devices (e.g. of an integrated root complex) and esp. not with DSA\nports.\n\nThere is an of_* variant of the nvmem binding which works without\ndevices. The returned data of a nvmem_cell_read() has to be freed after\nuse. On the other hand the return of_get_mac_address() points to some\nstatic data without a lifetime. The trick for now, was to allocate a\ndevice resource managed buffer which is then returned. This will only\nwork if we have an actual device.\n\nChange it, so that the caller of of_get_mac_address() has to supply a\nbuffer where the MAC address is written to. Unfortunately, this will\ntouch all drivers which use the of_get_mac_address().\n\nUsually the code looks like:\n\n  const char *addr;\n  addr = of_get_mac_address(np);\n  if (!IS_ERR(addr))\n    ether_addr_copy(ndev->dev_addr, addr);\n\nThis can then be simply rewritten as:\n\n  of_get_mac_address(np, ndev->dev_addr);\n\nSometimes is_valid_ether_addr() is used to test the MAC address.\nof_get_mac_address() already makes sure, it just returns a valid MAC\naddress. Thus we can just test its return code. But we have to be\ncareful if there are still other sources for the MAC address before the\nof_get_mac_address(). In this case we have to keep the\nis_valid_ether_addr() call.\n\nThe following coccinelle patch was used to convert common cases to the\nnew style. Afterwards, I've manually gone over the drivers and fixed the\nreturn code variable: either used a new one or if one was already\navailable use that. Mansour Moufid, thanks for that coccinelle patch!\n\n<spml>\n@a@\nidentifier x;\nexpression y, z;\n@@\n- x = of_get_mac_address(y);\n+ x = of_get_mac_address(y, z);\n  <...\n- ether_addr_copy(z, x);\n  ...>\n\n@@\nidentifier a.x;\n@@\n- if (<+... x ...+>) {}\n\n@@\nidentifier a.x;\n@@\n  if (<+... x ...+>) {\n      ...\n  }\n- else {}\n\n@@\nidentifier a.x;\nexpression e;\n@@\n- if (<+... x ...+>@e)\n-     {}\n- else\n+ if (!(e))\n      {...}\n\n@@\nexpression x, y, z;\n@@\n- x = of_get_mac_address(y, z);\n+ of_get_mac_address(y, z);\n  ... when != x\n</spml>\n\nAll drivers, except drivers/net/ethernet/aeroflex/greth.c, were\ncompile-time tested.\n\nSuggested-by: Andrew Lunn <andrew@lunn.ch>\nSigned-off-by: Michael Walle <michael@walle.cc>\nReviewed-by: Andrew Lunn <andrew@lunn.ch>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n arch/arm/mach-mvebu/kirkwood.c                     |  3 +-\n arch/powerpc/sysdev/tsi108_dev.c                   |  5 +-\n drivers/net/ethernet/aeroflex/greth.c              |  6 +--\n drivers/net/ethernet/allwinner/sun4i-emac.c        | 10 ++--\n drivers/net/ethernet/altera/altera_tse_main.c      |  7 +--\n drivers/net/ethernet/arc/emac_main.c               |  8 +--\n drivers/net/ethernet/atheros/ag71xx.c              |  7 +--\n drivers/net/ethernet/broadcom/bcm4908_enet.c       |  7 +--\n drivers/net/ethernet/broadcom/bcmsysport.c         |  7 +--\n drivers/net/ethernet/broadcom/bgmac-bcma.c         | 10 ++--\n drivers/net/ethernet/broadcom/bgmac-platform.c     | 11 ++--\n drivers/net/ethernet/cadence/macb_main.c           | 11 ++--\n drivers/net/ethernet/cavium/octeon/octeon_mgmt.c   |  8 +--\n drivers/net/ethernet/cavium/thunder/thunder_bgx.c  |  5 +-\n drivers/net/ethernet/davicom/dm9000.c              | 10 ++--\n drivers/net/ethernet/ethoc.c                       |  6 +--\n drivers/net/ethernet/ezchip/nps_enet.c             |  7 +--\n drivers/net/ethernet/freescale/fec_main.c          |  7 +--\n drivers/net/ethernet/freescale/fec_mpc52xx.c       |  7 +--\n drivers/net/ethernet/freescale/fman/mac.c          |  9 ++--\n .../net/ethernet/freescale/fs_enet/fs_enet-main.c  |  5 +-\n drivers/net/ethernet/freescale/gianfar.c           |  8 +--\n drivers/net/ethernet/freescale/ucc_geth.c          |  5 +-\n drivers/net/ethernet/hisilicon/hisi_femac.c        |  7 +--\n drivers/net/ethernet/hisilicon/hix5hd2_gmac.c      |  7 +--\n drivers/net/ethernet/lantiq_xrx200.c               |  7 +--\n drivers/net/ethernet/marvell/mv643xx_eth.c         |  5 +-\n drivers/net/ethernet/marvell/mvneta.c              |  6 +--\n .../net/ethernet/marvell/prestera/prestera_main.c  | 11 ++--\n drivers/net/ethernet/marvell/pxa168_eth.c          |  9 +---\n drivers/net/ethernet/marvell/sky2.c                |  8 ++-\n drivers/net/ethernet/mediatek/mtk_eth_soc.c        | 11 ++--\n drivers/net/ethernet/micrel/ks8851_common.c        |  7 ++-\n drivers/net/ethernet/microchip/lan743x_main.c      |  5 +-\n drivers/net/ethernet/nxp/lpc_eth.c                 |  4 +-\n drivers/net/ethernet/qualcomm/qca_spi.c            | 10 ++--\n drivers/net/ethernet/qualcomm/qca_uart.c           |  9 +---\n drivers/net/ethernet/renesas/ravb_main.c           | 12 +++--\n drivers/net/ethernet/renesas/sh_eth.c              |  5 +-\n .../net/ethernet/samsung/sxgbe/sxgbe_platform.c    | 13 ++---\n drivers/net/ethernet/socionext/sni_ave.c           | 10 ++--\n .../net/ethernet/stmicro/stmmac/dwmac-anarion.c    |  2 +-\n .../ethernet/stmicro/stmmac/dwmac-dwc-qos-eth.c    |  2 +-\n .../net/ethernet/stmicro/stmmac/dwmac-generic.c    |  2 +-\n drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c    |  2 +-\n .../net/ethernet/stmicro/stmmac/dwmac-intel-plat.c |  2 +-\n .../net/ethernet/stmicro/stmmac/dwmac-ipq806x.c    |  2 +-\n .../net/ethernet/stmicro/stmmac/dwmac-lpc18xx.c    |  2 +-\n .../net/ethernet/stmicro/stmmac/dwmac-mediatek.c   |  2 +-\n drivers/net/ethernet/stmicro/stmmac/dwmac-meson.c  |  2 +-\n .../net/ethernet/stmicro/stmmac/dwmac-meson8b.c    |  2 +-\n drivers/net/ethernet/stmicro/stmmac/dwmac-oxnas.c  |  2 +-\n .../ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c    |  2 +-\n drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c     |  2 +-\n .../net/ethernet/stmicro/stmmac/dwmac-socfpga.c    |  2 +-\n drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c    |  2 +-\n drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c  |  2 +-\n drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c  |  2 +-\n drivers/net/ethernet/stmicro/stmmac/dwmac-sunxi.c  |  2 +-\n .../net/ethernet/stmicro/stmmac/dwmac-visconti.c   |  2 +-\n drivers/net/ethernet/stmicro/stmmac/stmmac.h       |  2 +-\n drivers/net/ethernet/stmicro/stmmac/stmmac_main.c  |  2 +-\n .../net/ethernet/stmicro/stmmac/stmmac_platform.c  | 14 ++---\n .../net/ethernet/stmicro/stmmac/stmmac_platform.h  |  2 +-\n drivers/net/ethernet/ti/am65-cpsw-nuss.c           | 19 ++++---\n drivers/net/ethernet/ti/cpsw.c                     |  7 +--\n drivers/net/ethernet/ti/cpsw_new.c                 |  7 +--\n drivers/net/ethernet/ti/davinci_emac.c             |  8 +--\n drivers/net/ethernet/ti/netcp_core.c               |  7 +--\n drivers/net/ethernet/wiznet/w5100-spi.c            |  8 ++-\n drivers/net/ethernet/wiznet/w5100.c                |  2 +-\n drivers/net/ethernet/xilinx/ll_temac_main.c        |  8 +--\n drivers/net/ethernet/xilinx/xilinx_axienet_main.c  | 15 +++---\n drivers/net/ethernet/xilinx/xilinx_emaclite.c      |  8 +--\n drivers/net/wireless/ath/ath9k/init.c              |  5 +-\n drivers/net/wireless/mediatek/mt76/eeprom.c        |  9 +---\n drivers/net/wireless/ralink/rt2x00/rt2x00dev.c     |  6 +--\n drivers/of/of_net.c                                | 60 ++++++++++------------\n drivers/staging/octeon/ethernet.c                  | 10 ++--\n drivers/staging/wfx/main.c                         |  7 ++-\n include/linux/of_net.h                             |  6 +--\n include/net/dsa.h                                  |  2 +-\n net/dsa/dsa2.c                                     |  2 +-\n net/dsa/slave.c                                    |  2 +-\n net/ethernet/eth.c                                 | 11 ++--\n 85 files changed, 218 insertions(+), 364 deletions(-)\n\n--- a/arch/arm/mach-mvebu/kirkwood.c\n+++ b/arch/arm/mach-mvebu/kirkwood.c\n@@ -84,6 +84,7 @@ static void __init kirkwood_dt_eth_fixup\n \t\tstruct device_node *pnp = of_get_parent(np);\n \t\tstruct clk *clk;\n \t\tstruct property *pmac;\n+\t\tu8 tmpmac[ETH_ALEN];\n \t\tvoid __iomem *io;\n \t\tu8 *macaddr;\n \t\tu32 reg;\n@@ -93,7 +94,7 @@ static void __init kirkwood_dt_eth_fixup\n \n \t\t/* skip disabled nodes or nodes with valid MAC address*/\n \t\tif (!of_device_is_available(pnp) ||\n-\t\t    !IS_ERR(of_get_mac_address(np)))\n+\t\t    !of_get_mac_address(np, tmpmac))\n \t\t\tgoto eth_fixup_skip;\n \n \t\tclk = of_clk_get(pnp, 0);\n--- a/arch/powerpc/sysdev/tsi108_dev.c\n+++ b/arch/powerpc/sysdev/tsi108_dev.c\n@@ -73,7 +73,6 @@ static int __init tsi108_eth_of_init(voi\n \t\tstruct device_node *phy, *mdio;\n \t\thw_info tsi_eth_data;\n \t\tconst unsigned int *phy_id;\n-\t\tconst void *mac_addr;\n \t\tconst phandle *ph;\n \n \t\tmemset(r, 0, sizeof(r));\n@@ -101,9 +100,7 @@ static int __init tsi108_eth_of_init(voi\n \t\t\tgoto err;\n \t\t}\n \n-\t\tmac_addr = of_get_mac_address(np);\n-\t\tif (!IS_ERR(mac_addr))\n-\t\t\tether_addr_copy(tsi_eth_data.mac_addr, mac_addr);\n+\t\tof_get_mac_address(np, tsi_eth_data.mac_addr);\n \n \t\tph = of_get_property(np, \"mdio-handle\", NULL);\n \t\tmdio = of_find_node_by_phandle(*ph);\n--- a/drivers/net/ethernet/aeroflex/greth.c\n+++ b/drivers/net/ethernet/aeroflex/greth.c\n@@ -1449,10 +1449,10 @@ static int greth_of_probe(struct platfor\n \t\t\tbreak;\n \t}\n \tif (i == 6) {\n-\t\tconst u8 *addr;\n+\t\tu8 addr[ETH_ALEN];\n \n-\t\taddr = of_get_mac_address(ofdev->dev.of_node);\n-\t\tif (!IS_ERR(addr)) {\n+\t\terr = of_get_mac_address(ofdev->dev.of_node, addr);\n+\t\tif (!err) {\n \t\t\tfor (i = 0; i < 6; i++)\n \t\t\t\tmacaddr[i] = (unsigned int) addr[i];\n \t\t} else {\n--- a/drivers/net/ethernet/allwinner/sun4i-emac.c\n+++ b/drivers/net/ethernet/allwinner/sun4i-emac.c\n@@ -790,7 +790,6 @@ static int emac_probe(struct platform_de\n \tstruct emac_board_info *db;\n \tstruct net_device *ndev;\n \tint ret = 0;\n-\tconst char *mac_addr;\n \n \tndev = alloc_etherdev(sizeof(struct emac_board_info));\n \tif (!ndev) {\n@@ -853,12 +852,9 @@ static int emac_probe(struct platform_de\n \t}\n \n \t/* Read MAC-address from DT */\n-\tmac_addr = of_get_mac_address(np);\n-\tif (!IS_ERR(mac_addr))\n-\t\tether_addr_copy(ndev->dev_addr, mac_addr);\n-\n-\t/* Check if the MAC address is valid, if not get a random one */\n-\tif (!is_valid_ether_addr(ndev->dev_addr)) {\n+\tret = of_get_mac_address(np, ndev->dev_addr);\n+\tif (ret) {\n+\t\t/* if the MAC address is invalid get a random one */\n \t\teth_hw_addr_random(ndev);\n \t\tdev_warn(&pdev->dev, \"using random MAC address %pM\\n\",\n \t\t\t ndev->dev_addr);\n--- a/drivers/net/ethernet/altera/altera_tse_main.c\n+++ b/drivers/net/ethernet/altera/altera_tse_main.c\n@@ -1351,7 +1351,6 @@ static int altera_tse_probe(struct platf\n \tstruct resource *control_port;\n \tstruct resource *dma_res;\n \tstruct altera_tse_private *priv;\n-\tconst unsigned char *macaddr;\n \tvoid __iomem *descmap;\n \tconst struct of_device_id *of_id = NULL;\n \n@@ -1528,10 +1527,8 @@ static int altera_tse_probe(struct platf\n \tpriv->rx_dma_buf_sz = ALTERA_RXDMABUFFER_SIZE;\n \n \t/* get default MAC address from device tree */\n-\tmacaddr = of_get_mac_address(pdev->dev.of_node);\n-\tif (!IS_ERR(macaddr))\n-\t\tether_addr_copy(ndev->dev_addr, macaddr);\n-\telse\n+\tret = of_get_mac_address(pdev->dev.of_node, ndev->dev_addr);\n+\tif (ret)\n \t\teth_hw_addr_random(ndev);\n \n \t/* get phy addr and create mdio */\n--- a/drivers/net/ethernet/arc/emac_main.c\n+++ b/drivers/net/ethernet/arc/emac_main.c\n@@ -857,7 +857,6 @@ int arc_emac_probe(struct net_device *nd\n \tstruct device_node *phy_node;\n \tstruct phy_device *phydev = NULL;\n \tstruct arc_emac_priv *priv;\n-\tconst char *mac_addr;\n \tunsigned int id, clock_frequency, irq;\n \tint err;\n \n@@ -942,11 +941,8 @@ int arc_emac_probe(struct net_device *nd\n \t}\n \n \t/* Get MAC address from device tree */\n-\tmac_addr = of_get_mac_address(dev->of_node);\n-\n-\tif (!IS_ERR(mac_addr))\n-\t\tether_addr_copy(ndev->dev_addr, mac_addr);\n-\telse\n+\terr = of_get_mac_address(dev->of_node, ndev->dev_addr);\n+\tif (err)\n \t\teth_hw_addr_random(ndev);\n \n \tarc_emac_set_address_internal(ndev);\n--- a/drivers/net/ethernet/atheros/ag71xx.c\n+++ b/drivers/net/ethernet/atheros/ag71xx.c\n@@ -1856,7 +1856,6 @@ static int ag71xx_probe(struct platform_\n \tconst struct ag71xx_dcfg *dcfg;\n \tstruct net_device *ndev;\n \tstruct resource *res;\n-\tconst void *mac_addr;\n \tint tx_size, err, i;\n \tstruct ag71xx *ag;\n \n@@ -1952,10 +1951,8 @@ static int ag71xx_probe(struct platform_\n \tag->stop_desc->ctrl = 0;\n \tag->stop_desc->next = (u32)ag->stop_desc_dma;\n \n-\tmac_addr = of_get_mac_address(np);\n-\tif (!IS_ERR(mac_addr))\n-\t\tmemcpy(ndev->dev_addr, mac_addr, ETH_ALEN);\n-\tif (IS_ERR(mac_addr) || !is_valid_ether_addr(ndev->dev_addr)) {\n+\terr = of_get_mac_address(np, ndev->dev_addr);\n+\tif (err) {\n \t\tnetif_err(ag, probe, ndev, \"invalid MAC address, using random address\\n\");\n \t\teth_random_addr(ndev->dev_addr);\n \t}\n--- a/drivers/net/ethernet/broadcom/bcmsysport.c\n+++ b/drivers/net/ethernet/broadcom/bcmsysport.c\n@@ -2468,7 +2468,6 @@ static int bcm_sysport_probe(struct plat\n \tstruct bcm_sysport_priv *priv;\n \tstruct device_node *dn;\n \tstruct net_device *dev;\n-\tconst void *macaddr;\n \tu32 txq, rxq;\n \tint ret;\n \n@@ -2563,12 +2562,10 @@ static int bcm_sysport_probe(struct plat\n \t}\n \n \t/* Initialize netdevice members */\n-\tmacaddr = of_get_mac_address(dn);\n-\tif (IS_ERR(macaddr)) {\n+\tret = of_get_mac_address(dn, dev->dev_addr);\n+\tif (ret) {\n \t\tdev_warn(&pdev->dev, \"using random Ethernet MAC\\n\");\n \t\teth_hw_addr_random(dev);\n-\t} else {\n-\t\tether_addr_copy(dev->dev_addr, macaddr);\n \t}\n \n \tSET_NETDEV_DEV(dev, &pdev->dev);\n--- a/drivers/net/ethernet/broadcom/bgmac-bcma.c\n+++ b/drivers/net/ethernet/broadcom/bgmac-bcma.c\n@@ -115,7 +115,7 @@ static int bgmac_probe(struct bcma_devic\n \tstruct ssb_sprom *sprom = &core->bus->sprom;\n \tstruct mii_bus *mii_bus;\n \tstruct bgmac *bgmac;\n-\tconst u8 *mac = NULL;\n+\tconst u8 *mac;\n \tint err;\n \n \tbgmac = bgmac_alloc(&core->dev);\n@@ -128,11 +128,10 @@ static int bgmac_probe(struct bcma_devic\n \n \tbcma_set_drvdata(core, bgmac);\n \n-\tif (bgmac->dev->of_node)\n-\t\tmac = of_get_mac_address(bgmac->dev->of_node);\n+\terr = of_get_mac_address(bgmac->dev->of_node, bgmac->net_dev->dev_addr);\n \n \t/* If no MAC address assigned via device tree, check SPROM */\n-\tif (IS_ERR_OR_NULL(mac)) {\n+\tif (err) {\n \t\tswitch (core->core_unit) {\n \t\tcase 0:\n \t\t\tmac = sprom->et0mac;\n@@ -149,10 +148,9 @@ static int bgmac_probe(struct bcma_devic\n \t\t\terr = -ENOTSUPP;\n \t\t\tgoto err;\n \t\t}\n+\t\tether_addr_copy(bgmac->net_dev->dev_addr, mac);\n \t}\n \n-\tether_addr_copy(bgmac->net_dev->dev_addr, mac);\n-\n \t/* On BCM4706 we need common core to access PHY */\n \tif (core->id.id == BCMA_CORE_4706_MAC_GBIT &&\n \t    !core->bus->drv_gmac_cmn.core) {\n--- a/drivers/net/ethernet/broadcom/bgmac-platform.c\n+++ b/drivers/net/ethernet/broadcom/bgmac-platform.c\n@@ -173,7 +173,7 @@ static int bgmac_probe(struct platform_d\n \tstruct device_node *np = pdev->dev.of_node;\n \tstruct bgmac *bgmac;\n \tstruct resource *regs;\n-\tconst u8 *mac_addr;\n+\tint ret;\n \n \tbgmac = bgmac_alloc(&pdev->dev);\n \tif (!bgmac)\n@@ -192,11 +192,10 @@ static int bgmac_probe(struct platform_d\n \tbgmac->dev = &pdev->dev;\n \tbgmac->dma_dev = &pdev->dev;\n \n-\tmac_addr = of_get_mac_address(np);\n-\tif (!IS_ERR(mac_addr))\n-\t\tether_addr_copy(bgmac->net_dev->dev_addr, mac_addr);\n-\telse\n-\t\tdev_warn(&pdev->dev, \"MAC address not present in device tree\\n\");\n+\tret = of_get_mac_address(np, bgmac->net_dev->dev_addr);\n+\tif (ret)\n+\t\tdev_warn(&pdev->dev,\n+\t\t\t \"MAC address not present in device tree\\n\");\n \n \tbgmac->irq = platform_get_irq(pdev, 0);\n \tif (bgmac->irq < 0)\n--- a/drivers/net/ethernet/cadence/macb_main.c\n+++ b/drivers/net/ethernet/cadence/macb_main.c\n@@ -4487,7 +4487,6 @@ static int macb_probe(struct platform_de\n \tstruct net_device *dev;\n \tstruct resource *regs;\n \tvoid __iomem *mem;\n-\tconst char *mac;\n \tstruct macb *bp;\n \tint err, val;\n \n@@ -4600,15 +4599,11 @@ static int macb_probe(struct platform_de\n \tif (bp->caps & MACB_CAPS_NEEDS_RSTONUBR)\n \t\tbp->rx_intr_mask |= MACB_BIT(RXUBR);\n \n-\tmac = of_get_mac_address(np);\n-\tif (PTR_ERR(mac) == -EPROBE_DEFER) {\n-\t\terr = -EPROBE_DEFER;\n+\terr = of_get_mac_address(np, bp->dev->dev_addr);\n+\tif (err == -EPROBE_DEFER)\n \t\tgoto err_out_free_netdev;\n-\t} else if (!IS_ERR_OR_NULL(mac)) {\n-\t\tether_addr_copy(bp->dev->dev_addr, mac);\n-\t} else {\n+\telse if (err)\n \t\tmacb_get_hwaddr(bp);\n-\t}\n \n \terr = of_get_phy_mode(np, &interface);\n \tif (err)\n--- a/drivers/net/ethernet/cavium/octeon/octeon_mgmt.c\n+++ b/drivers/net/ethernet/cavium/octeon/octeon_mgmt.c\n@@ -1385,7 +1385,6 @@ static int octeon_mgmt_probe(struct plat\n \tstruct net_device *netdev;\n \tstruct octeon_mgmt *p;\n \tconst __be32 *data;\n-\tconst u8 *mac;\n \tstruct resource *res_mix;\n \tstruct resource *res_agl;\n \tstruct resource *res_agl_prt_ctl;\n@@ -1502,11 +1501,8 @@ static int octeon_mgmt_probe(struct plat\n \tnetdev->min_mtu = 64 - OCTEON_MGMT_RX_HEADROOM;\n \tnetdev->max_mtu = 16383 - OCTEON_MGMT_RX_HEADROOM - VLAN_HLEN;\n \n-\tmac = of_get_mac_address(pdev->dev.of_node);\n-\n-\tif (!IS_ERR(mac))\n-\t\tether_addr_copy(netdev->dev_addr, mac);\n-\telse\n+\tresult = of_get_mac_address(pdev->dev.of_node, netdev->dev_addr);\n+\tif (result)\n \t\teth_hw_addr_random(netdev);\n \n \tp->phy_np = of_parse_phandle(pdev->dev.of_node, \"phy-handle\", 0);\n--- a/drivers/net/ethernet/cavium/thunder/thunder_bgx.c\n+++ b/drivers/net/ethernet/cavium/thunder/thunder_bgx.c\n@@ -1474,7 +1474,6 @@ static int bgx_init_of_phy(struct bgx *b\n \tdevice_for_each_child_node(&bgx->pdev->dev, fwn) {\n \t\tstruct phy_device *pd;\n \t\tstruct device_node *phy_np;\n-\t\tconst char *mac;\n \n \t\t/* Should always be an OF node.  But if it is not, we\n \t\t * cannot handle it, so exit the loop.\n@@ -1483,9 +1482,7 @@ static int bgx_init_of_phy(struct bgx *b\n \t\tif (!node)\n \t\t\tbreak;\n \n-\t\tmac = of_get_mac_address(node);\n-\t\tif (!IS_ERR(mac))\n-\t\t\tether_addr_copy(bgx->lmac[lmac].mac, mac);\n+\t\tof_get_mac_address(node, bgx->lmac[lmac].mac);\n \n \t\tSET_NETDEV_DEV(&bgx->lmac[lmac].netdev, &bgx->pdev->dev);\n \t\tbgx->lmac[lmac].lmacid = lmac;\n--- a/drivers/net/ethernet/davicom/dm9000.c\n+++ b/drivers/net/ethernet/davicom/dm9000.c\n@@ -1388,7 +1388,7 @@ static struct dm9000_plat_data *dm9000_p\n {\n \tstruct dm9000_plat_data *pdata;\n \tstruct device_node *np = dev->of_node;\n-\tconst void *mac_addr;\n+\tint ret;\n \n \tif (!IS_ENABLED(CONFIG_OF) || !np)\n \t\treturn ERR_PTR(-ENXIO);\n@@ -1402,11 +1402,9 @@ static struct dm9000_plat_data *dm9000_p\n \tif (of_find_property(np, \"davicom,no-eeprom\", NULL))\n \t\tpdata->flags |= DM9000_PLATF_NO_EEPROM;\n \n-\tmac_addr = of_get_mac_address(np);\n-\tif (!IS_ERR(mac_addr))\n-\t\tether_addr_copy(pdata->dev_addr, mac_addr);\n-\telse if (PTR_ERR(mac_addr) == -EPROBE_DEFER)\n-\t\treturn ERR_CAST(mac_addr);\n+\tret = of_get_mac_address(np, pdata->dev_addr);\n+\tif (ret == -EPROBE_DEFER)\n+\t\treturn ERR_PTR(ret);\n \n \treturn pdata;\n }\n--- a/drivers/net/ethernet/ethoc.c\n+++ b/drivers/net/ethernet/ethoc.c\n@@ -1151,11 +1151,7 @@ static int ethoc_probe(struct platform_d\n \t\tether_addr_copy(netdev->dev_addr, pdata->hwaddr);\n \t\tpriv->phy_id = pdata->phy_id;\n \t} else {\n-\t\tconst void *mac;\n-\n-\t\tmac = of_get_mac_address(pdev->dev.of_node);\n-\t\tif (!IS_ERR(mac))\n-\t\t\tether_addr_copy(netdev->dev_addr, mac);\n+\t\tof_get_mac_address(pdev->dev.of_node, netdev->dev_addr);\n \t\tpriv->phy_id = -1;\n \t}\n \n--- a/drivers/net/ethernet/ezchip/nps_enet.c\n+++ b/drivers/net/ethernet/ezchip/nps_enet.c\n@@ -575,7 +575,6 @@ static s32 nps_enet_probe(struct platfor\n \tstruct net_device *ndev;\n \tstruct nps_enet_priv *priv;\n \ts32 err = 0;\n-\tconst char *mac_addr;\n \n \tif (!dev->of_node)\n \t\treturn -ENODEV;\n@@ -602,10 +601,8 @@ static s32 nps_enet_probe(struct platfor\n \tdev_dbg(dev, \"Registers base address is 0x%p\\n\", priv->regs_base);\n \n \t/* set kernel MAC address to dev */\n-\tmac_addr = of_get_mac_address(dev->of_node);\n-\tif (!IS_ERR(mac_addr))\n-\t\tether_addr_copy(ndev->dev_addr, mac_addr);\n-\telse\n+\terr = of_get_mac_address(dev->of_node, ndev->dev_addr);\n+\tif (err)\n \t\teth_hw_addr_random(ndev);\n \n \t/* Get IRQ number */\n--- a/drivers/net/ethernet/freescale/fec_main.c\n+++ b/drivers/net/ethernet/freescale/fec_main.c\n@@ -1666,6 +1666,7 @@ static void fec_get_mac(struct net_devic\n \tstruct fec_enet_private *fep = netdev_priv(ndev);\n \tstruct fec_platform_data *pdata = dev_get_platdata(&fep->pdev->dev);\n \tunsigned char *iap, tmpaddr[ETH_ALEN];\n+\tint ret;\n \n \t/*\n \t * try to get mac address in following order:\n@@ -1681,9 +1682,9 @@ static void fec_get_mac(struct net_devic\n \tif (!is_valid_ether_addr(iap)) {\n \t\tstruct device_node *np = fep->pdev->dev.of_node;\n \t\tif (np) {\n-\t\t\tconst char *mac = of_get_mac_address(np);\n-\t\t\tif (!IS_ERR(mac))\n-\t\t\t\tiap = (unsigned char *) mac;\n+\t\t\tret = of_get_mac_address(np, tmpaddr);\n+\t\t\tif (!ret)\n+\t\t\t\tiap = tmpaddr;\n \t\t}\n \t}\n \n--- a/drivers/net/ethernet/freescale/fec_mpc52xx.c\n+++ b/drivers/net/ethernet/freescale/fec_mpc52xx.c\n@@ -813,7 +813,6 @@ static int mpc52xx_fec_probe(struct plat\n \tconst u32 *prop;\n \tint prop_size;\n \tstruct device_node *np = op->dev.of_node;\n-\tconst char *mac_addr;\n \n \tphys_addr_t rx_fifo;\n \tphys_addr_t tx_fifo;\n@@ -891,10 +890,8 @@ static int mpc52xx_fec_probe(struct plat\n \t *\n \t * First try to read MAC address from DT\n \t */\n-\tmac_addr = of_get_mac_address(np);\n-\tif (!IS_ERR(mac_addr)) {\n-\t\tether_addr_copy(ndev->dev_addr, mac_addr);\n-\t} else {\n+\trv = of_get_mac_address(np, ndev->dev_addr);\n+\tif (rv) {\n \t\tstruct mpc52xx_fec __iomem *fec = priv->fec;\n \n \t\t/*\n--- a/drivers/net/ethernet/freescale/fman/mac.c\n+++ b/drivers/net/ethernet/freescale/fman/mac.c\n@@ -616,7 +616,6 @@ static int mac_probe(struct platform_dev\n \tstruct platform_device\t*of_dev;\n \tstruct resource\t\t res;\n \tstruct mac_priv_s\t*priv;\n-\tconst u8\t\t*mac_addr;\n \tu32\t\t\t val;\n \tu8\t\t\tfman_id;\n \tphy_interface_t          phy_if;\n@@ -734,11 +733,9 @@ static int mac_probe(struct platform_dev\n \tpriv->cell_index = (u8)val;\n \n \t/* Get the MAC address */\n-\tmac_addr = of_get_mac_address(mac_node);\n-\tif (IS_ERR(mac_addr))\n+\terr = of_get_mac_address(mac_node, mac_dev->addr);\n+\tif (err)\n \t\tdev_warn(dev, \"of_get_mac_address(%pOF) failed\\n\", mac_node);\n-\telse\n-\t\tether_addr_copy(mac_dev->addr, mac_addr);\n \n \t/* Get the port handles */\n \tnph = of_count_phandle_with_args(mac_node, \"fsl,fman-ports\", NULL);\n@@ -864,7 +861,7 @@ static int mac_probe(struct platform_dev\n \tif (err < 0)\n \t\tdev_err(dev, \"fman_set_mac_active_pause() = %d\\n\", err);\n \n-\tif (!IS_ERR(mac_addr))\n+\tif (!is_zero_ether_addr(mac_dev->addr))\n \t\tdev_info(dev, \"FMan MAC address: %pM\\n\", mac_dev->addr);\n \n \tpriv->eth_dev = dpaa_eth_add_device(fman_id, mac_dev);\n--- a/drivers/net/ethernet/freescale/fs_enet/fs_enet-main.c\n+++ b/drivers/net/ethernet/freescale/fs_enet/fs_enet-main.c\n@@ -918,7 +918,6 @@ static int fs_enet_probe(struct platform\n \tconst u32 *data;\n \tstruct clk *clk;\n \tint err;\n-\tconst u8 *mac_addr;\n \tconst char *phy_connection_type;\n \tint privsize, len, ret = -ENODEV;\n \n@@ -1006,9 +1005,7 @@ static int fs_enet_probe(struct platform\n \tspin_lock_init(&fep->lock);\n \tspin_lock_init(&fep->tx_lock);\n \n-\tmac_addr = of_get_mac_address(ofdev->dev.of_node);\n-\tif (!IS_ERR(mac_addr))\n-\t\tether_addr_copy(ndev->dev_addr, mac_addr);\n+\tof_get_mac_address(ofdev->dev.of_node, ndev->dev_addr);\n \n \tret = fep->ops->allocate_bd(ndev);\n \tif (ret)\n--- a/drivers/net/ethernet/freescale/gianfar.c\n+++ b/drivers/net/ethernet/freescale/gianfar.c\n@@ -641,7 +641,6 @@ static phy_interface_t gfar_get_interfac\n static int gfar_of_init(struct platform_device *ofdev, struct net_device **pdev)\n {\n \tconst char *model;\n-\tconst void *mac_addr;\n \tint err = 0, i;\n \tphy_interface_t interface;\n \tstruct net_device *dev = NULL;\n@@ -783,11 +782,8 @@ static int gfar_of_init(struct platform_\n \tif (stash_len || stash_idx)\n \t\tpriv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING;\n \n-\tmac_addr = of_get_mac_address(np);\n-\n-\tif (!IS_ERR(mac_addr)) {\n-\t\tether_addr_copy(dev->dev_addr, mac_addr);\n-\t} else {\n+\terr = of_get_mac_address(np, dev->dev_addr);\n+\tif (err) {\n \t\teth_hw_addr_random(dev);\n \t\tdev_info(&ofdev->dev, \"Using random MAC address: %pM\\n\", dev->dev_addr);\n \t}\n--- a/drivers/net/ethernet/freescale/ucc_geth.c\n+++ b/drivers/net/ethernet/freescale/ucc_geth.c\n@@ -3696,7 +3696,6 @@ static int ucc_geth_probe(struct platfor\n \tint err, ucc_num, max_speed = 0;\n \tconst unsigned int *prop;\n \tconst char *sprop;\n-\tconst void *mac_addr;\n \tphy_interface_t phy_interface;\n \tstatic const int enet_to_speed[] = {\n \t\tSPEED_10, SPEED_10, SPEED_10,\n@@ -3906,9 +3905,7 @@ static int ucc_geth_probe(struct platfor\n \t\tgoto err_free_netdev;\n \t}\n \n-\tmac_addr = of_get_mac_address(np);\n-\tif (!IS_ERR(mac_addr))\n-\t\tether_addr_copy(dev->dev_addr, mac_addr);\n+\tof_get_mac_address(np, dev->dev_addr);\n \n \tugeth->ug_info = ug_info;\n \tugeth->dev = device;\n--- a/drivers/net/ethernet/hisilicon/hisi_femac.c\n+++ b/drivers/net/ethernet/hisilicon/hisi_femac.c\n@@ -772,7 +772,6 @@ static int hisi_femac_drv_probe(struct p\n \tstruct net_device *ndev;\n \tstruct hisi_femac_priv *priv;\n \tstruct phy_device *phy;\n-\tconst char *mac_addr;\n \tint ret;\n \n \tndev = alloc_etherdev(sizeof(*priv));\n@@ -842,10 +841,8 @@ static int hisi_femac_drv_probe(struct p\n \t\t\t   (unsigned long)phy->phy_id,\n \t\t\t   phy_modes(phy->interface));\n \n-\tmac_addr = of_get_mac_address(node);\n-\tif (!IS_ERR(mac_addr))\n-\t\tether_addr_copy(ndev->dev_addr, mac_addr);\n-\tif (!is_valid_ether_addr(ndev->dev_addr)) {\n+\tret = of_get_mac_address(node, ndev->dev_addr);\n+\tif (ret) {\n \t\teth_hw_addr_random(ndev);\n \t\tdev_warn(dev, \"using random MAC address %pM\\n\",\n \t\t\t ndev->dev_addr);\n--- a/drivers/net/ethernet/hisilicon/hix5hd2_gmac.c\n+++ b/drivers/net/ethernet/hisilicon/hix5hd2_gmac.c\n@@ -1098,7 +1098,6 @@ static int hix5hd2_dev_probe(struct plat\n \tstruct net_device *ndev;\n \tstruct hix5hd2_priv *priv;\n \tstruct mii_bus *bus;\n-\tconst char *mac_addr;\n \tint ret;\n \n \tndev = alloc_etherdev(sizeof(struct hix5hd2_priv));\n@@ -1220,10 +1219,8 @@ static int hix5hd2_dev_probe(struct plat\n \t\tgoto out_phy_node;\n \t}\n \n-\tmac_addr = of_get_mac_address(node);\n-\tif (!IS_ERR(mac_addr))\n-\t\tether_addr_copy(ndev->dev_addr, mac_addr);\n-\tif (!is_valid_ether_addr(ndev->dev_addr)) {\n+\tret = of_get_mac_address(node, ndev->dev_addr);\n+\tif (ret) {\n \t\teth_hw_addr_random(ndev);\n \t\tnetdev_warn(ndev, \"using random MAC address %pM\\n\",\n \t\t\t    ndev->dev_addr);\n--- a/drivers/net/ethernet/lantiq_xrx200.c\n+++ b/drivers/net/ethernet/lantiq_xrx200.c\n@@ -440,7 +440,6 @@ static int xrx200_probe(struct platform_\n \tstruct resource *res;\n \tstruct xrx200_priv *priv;\n \tstruct net_device *net_dev;\n-\tconst u8 *mac;\n \tint err;\n \n \t/* alloc the network device */\n@@ -484,10 +483,8 @@ static int xrx200_probe(struct platform_\n \t\treturn PTR_ERR(priv->clk);\n \t}\n \n-\tmac = of_get_mac_address(np);\n-\tif (!IS_ERR(mac))\n-\t\tether_addr_copy(net_dev->dev_addr, mac);\n-\telse\n+\terr = of_get_mac_address(np, net_dev->dev_addr);\n+\tif (err)\n \t\teth_hw_addr_random(net_dev);\n \n \t/* bring up the dma engine and IP core */\n--- a/drivers/net/ethernet/marvell/mv643xx_eth.c\n+++ b/drivers/net/ethernet/marvell/mv643xx_eth.c\n@@ -2700,7 +2700,6 @@ static int mv643xx_eth_shared_of_add_por\n \tstruct platform_device *ppdev;\n \tstruct mv643xx_eth_platform_data ppd;\n \tstruct resource res;\n-\tconst char *mac_addr;\n \tint ret;\n \tint dev_num = 0;\n \n@@ -2731,9 +2730,7 @@ static int mv643xx_eth_shared_of_add_por\n \t\treturn -EINVAL;\n \t}\n \n-\tmac_addr = of_get_mac_address(pnp);\n-\tif (!IS_ERR(mac_addr))\n-\t\tether_addr_copy(ppd.mac_addr, mac_addr);\n+\tof_get_mac_address(pnp, ppd.mac_addr);\n \n \tmv643xx_eth_property(pnp, \"tx-queue-size\", ppd.tx_queue_size);\n \tmv643xx_eth_property(pnp, \"tx-sram-addr\", ppd.tx_sram_addr);\n--- a/drivers/net/ethernet/marvell/mvneta.c\n+++ b/drivers/net/ethernet/marvell/mvneta.c\n@@ -5062,7 +5062,6 @@ static int mvneta_probe(struct platform_\n \tstruct net_device *dev;\n \tstruct phylink *phylink;\n \tstruct phy *comphy;\n-\tconst char *dt_mac_addr;\n \tchar hw_mac_addr[ETH_ALEN];\n \tphy_interface_t phy_mode;\n \tconst char *mac_from;\n@@ -5158,10 +5157,9 @@ static int mvneta_probe(struct platform_\n \t\tgoto err_free_ports;\n \t}\n \n-\tdt_mac_addr = of_get_mac_address(dn);\n-\tif (!IS_ERR(dt_mac_addr)) {\n+\terr = of_get_mac_address(dn, dev->dev_addr);\n+\tif (!err) {\n \t\tmac_from = \"device tree\";\n-\t\tether_addr_copy(dev->dev_addr, dt_mac_addr);\n \t} else {\n \t\tmvneta_get_mac_addr(pp, hw_mac_addr);\n \t\tif (is_valid_ether_addr(hw_mac_addr)) {\n--- a/drivers/net/ethernet/marvell/prestera/prestera_main.c\n+++ b/drivers/net/ethernet/marvell/prestera/prestera_main.c\n@@ -466,20 +466,17 @@ static int prestera_switch_set_base_mac_\n {\n \tstruct device_node *base_mac_np;\n \tstruct device_node *np;\n-\tconst char *base_mac;\n+\tint ret;\n \n \tnp = of_find_compatible_node(NULL, NULL, \"marvell,prestera\");\n \tbase_mac_np = of_parse_phandle(np, \"base-mac-provider\", 0);\n \n-\tbase_mac = of_get_mac_address(base_mac_np);\n-\tof_node_put(base_mac_np);\n-\tif (!IS_ERR(base_mac))\n-\t\tether_addr_copy(sw->base_mac, base_mac);\n-\n-\tif (!is_valid_ether_addr(sw->base_mac)) {\n+\tret = of_get_mac_address(base_mac_np, sw->base_mac);\n+\tif (ret) {\n \t\teth_random_addr(sw->base_mac);\n \t\tdev_info(prestera_dev(sw), \"using random base mac address\\n\");\n \t}\n+\tof_node_put(base_mac_np);\n \n \treturn prestera_hw_switch_mac_set(sw, sw->base_mac);\n }\n--- a/drivers/net/ethernet/marvell/pxa168_eth.c\n+++ b/drivers/net/ethernet/marvell/pxa168_eth.c\n@@ -1392,7 +1392,6 @@ static int pxa168_eth_probe(struct platf\n \tstruct resource *res;\n \tstruct clk *clk;\n \tstruct device_node *np;\n-\tconst unsigned char *mac_addr = NULL;\n \tint err;\n \n \tprintk(KERN_NOTICE \"PXA168 10/100 Ethernet Driver\\n\");\n@@ -1435,12 +1434,8 @@ static int pxa168_eth_probe(struct platf\n \n \tINIT_WORK(&pep->tx_timeout_task, pxa168_eth_tx_timeout_task);\n \n-\tif (pdev->dev.of_node)\n-\t\tmac_addr = of_get_mac_address(pdev->dev.of_node);\n-\n-\tif (!IS_ERR_OR_NULL(mac_addr)) {\n-\t\tether_addr_copy(dev->dev_addr, mac_addr);\n-\t} else {\n+\terr = of_get_mac_address(pdev->dev.of_node, dev->dev_addr);\n+\tif (err) {\n \t\t/* try reading the mac address, if set by the bootloader */\n \t\tpxa168_eth_get_mac_address(dev, dev->dev_addr);\n \t\tif (!is_valid_ether_addr(dev->dev_addr)) {\n--- a/drivers/net/ethernet/marvell/sky2.c\n+++ b/drivers/net/ethernet/marvell/sky2.c\n@@ -4725,7 +4725,7 @@ static struct net_device *sky2_init_netd\n {\n \tstruct sky2_port *sky2;\n \tstruct net_device *dev = alloc_etherdev(sizeof(*sky2));\n-\tconst void *iap;\n+\tint ret;\n \n \tif (!dev)\n \t\treturn NULL;\n@@ -4795,10 +4795,8 @@ static struct net_device *sky2_init_netd\n \t * 1) from device tree data\n \t * 2) from internal registers set by bootloader\n \t */\n-\tiap = of_get_mac_address(hw->pdev->dev.of_node);\n-\tif (!IS_ERR(iap))\n-\t\tether_addr_copy(dev->dev_addr, iap);\n-\telse\n+\tret = of_get_mac_address(hw->pdev->dev.of_node, dev->dev_addr);\n+\tif (ret)\n \t\tmemcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8,\n \t\t\t      ETH_ALEN);\n \n--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c\n+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c\n@@ -2580,14 +2580,11 @@ static int __init mtk_init(struct net_de\n {\n \tstruct mtk_mac *mac = netdev_priv(dev);\n \tstruct mtk_eth *eth = mac->hw;\n-\tconst char *mac_addr;\n+\tint ret;\n \n-\tmac_addr = of_get_mac_address(mac->of_node);\n-\tif (!IS_ERR(mac_addr))\n-\t\tether_addr_copy(dev->dev_addr, mac_addr);\n-\n-\t/* If the mac address is invalid, use random mac address  */\n-\tif (!is_valid_ether_addr(dev->dev_addr)) {\n+\tret = of_get_mac_address(mac->of_node, dev->dev_addr);\n+\tif (ret) {\n+\t\t/* If the mac address is invalid, use random mac address */\n \t\teth_hw_addr_random(dev);\n \t\tdev_err(eth->dev, \"generated random MAC address %pM\\n\",\n \t\t\tdev->dev_addr);\n--- a/drivers/net/ethernet/micrel/ks8851_common.c\n+++ b/drivers/net/ethernet/micrel/ks8851_common.c\n@@ -194,11 +194,10 @@ static void ks8851_read_mac_addr(struct\n static void ks8851_init_mac(struct ks8851_net *ks, struct device_node *np)\n {\n \tstruct net_device *dev = ks->netdev;\n-\tconst u8 *mac_addr;\n+\tint ret;\n \n-\tmac_addr = of_get_mac_address(np);\n-\tif (!IS_ERR(mac_addr)) {\n-\t\tether_addr_copy(dev->dev_addr, mac_addr);\n+\tret = of_get_mac_address(np, dev->dev_addr);\n+\tif (!ret) {\n \t\tks8851_write_mac_addr(dev);\n \t\treturn;\n \t}\n--- a/drivers/net/ethernet/microchip/lan743x_main.c\n+++ b/drivers/net/ethernet/microchip/lan743x_main.c\n@@ -2831,7 +2831,6 @@ static int lan743x_pcidev_probe(struct p\n {\n \tstruct lan743x_adapter *adapter = NULL;\n \tstruct net_device *netdev = NULL;\n-\tconst void *mac_addr;\n \tint ret = -ENODEV;\n \n \tnetdev = devm_alloc_etherdev(&pdev->dev,\n@@ -2848,9 +2847,7 @@ static int lan743x_pcidev_probe(struct p\n \t\t\t      NETIF_MSG_IFDOWN | NETIF_MSG_TX_QUEUED;\n \tnetdev->max_mtu = LAN743X_MAX_FRAME_SIZE;\n \n-\tmac_addr = of_get_mac_address(pdev->dev.of_node);\n-\tif (!IS_ERR(mac_addr))\n-\t\tether_addr_copy(adapter->mac_address, mac_addr);\n+\tof_get_mac_address(pdev->dev.of_node, adapter->mac_address);\n \n \tret = lan743x_pci_init(adapter, pdev);\n \tif (ret)\n--- a/drivers/net/ethernet/nxp/lpc_eth.c\n+++ b/drivers/net/ethernet/nxp/lpc_eth.c\n@@ -1347,9 +1347,7 @@ static int lpc_eth_drv_probe(struct plat\n \t__lpc_get_mac(pldat, ndev->dev_addr);\n \n \tif (!is_valid_ether_addr(ndev->dev_addr)) {\n-\t\tconst char *macaddr = of_get_mac_address(np);\n-\t\tif (!IS_ERR(macaddr))\n-\t\t\tether_addr_copy(ndev->dev_addr, macaddr);\n+\t\tof_get_mac_address(np, ndev->dev_addr);\n \t}\n \tif (!is_valid_ether_addr(ndev->dev_addr))\n \t\teth_hw_addr_random(ndev);\n--- a/drivers/net/ethernet/qualcomm/qca_spi.c\n+++ b/drivers/net/ethernet/qualcomm/qca_spi.c\n@@ -885,7 +885,7 @@ qca_spi_probe(struct spi_device *spi)\n \tstruct net_device *qcaspi_devs = NULL;\n \tu8 legacy_mode = 0;\n \tu16 signature;\n-\tconst char *mac;\n+\tint ret;\n \n \tif (!spi->dev.of_node) {\n \t\tdev_err(&spi->dev, \"Missing device tree\\n\");\n@@ -962,12 +962,8 @@ qca_spi_probe(struct spi_device *spi)\n \n \tspi_set_drvdata(spi, qcaspi_devs);\n \n-\tmac = of_get_mac_address(spi->dev.of_node);\n-\n-\tif (!IS_ERR(mac))\n-\t\tether_addr_copy(qca->net_dev->dev_addr, mac);\n-\n-\tif (!is_valid_ether_addr(qca->net_dev->dev_addr)) {\n+\tret = of_get_mac_address(spi->dev.of_node, qca->net_dev->dev_addr);\n+\tif (ret) {\n \t\teth_hw_addr_random(qca->net_dev);\n \t\tdev_info(&spi->dev, \"Using random MAC address: %pM\\n\",\n \t\t\t qca->net_dev->dev_addr);\n--- a/drivers/net/ethernet/qualcomm/qca_uart.c\n+++ b/drivers/net/ethernet/qualcomm/qca_uart.c\n@@ -323,7 +323,6 @@ static int qca_uart_probe(struct serdev_\n {\n \tstruct net_device *qcauart_dev = alloc_etherdev(sizeof(struct qcauart));\n \tstruct qcauart *qca;\n-\tconst char *mac;\n \tu32 speed = 115200;\n \tint ret;\n \n@@ -348,12 +347,8 @@ static int qca_uart_probe(struct serdev_\n \n \tof_property_read_u32(serdev->dev.of_node, \"current-speed\", &speed);\n \n-\tmac = of_get_mac_address(serdev->dev.of_node);\n-\n-\tif (!IS_ERR(mac))\n-\t\tether_addr_copy(qca->net_dev->dev_addr, mac);\n-\n-\tif (!is_valid_ether_addr(qca->net_dev->dev_addr)) {\n+\tret = of_get_mac_address(serdev->dev.of_node, qca->net_dev->dev_addr);\n+\tif (ret) {\n \t\teth_hw_addr_random(qca->net_dev);\n \t\tdev_info(&serdev->dev, \"Using random MAC address: %pM\\n\",\n \t\t\t qca->net_dev->dev_addr);\n--- a/drivers/net/ethernet/renesas/ravb_main.c\n+++ b/drivers/net/ethernet/renesas/ravb_main.c\n@@ -109,11 +109,13 @@ static void ravb_set_buffer_align(struct\n  * Ethernet AVB device doesn't have ROM for MAC address.\n  * This function gets the MAC address that was used by a bootloader.\n  */\n-static void ravb_read_mac_address(struct net_device *ndev, const u8 *mac)\n+static void ravb_read_mac_address(struct device_node *np,\n+\t\t\t\t  struct net_device *ndev)\n {\n-\tif (!IS_ERR(mac)) {\n-\t\tether_addr_copy(ndev->dev_addr, mac);\n-\t} else {\n+\tint ret;\n+\n+\tret = of_get_mac_address(np, ndev->dev_addr);\n+\tif (ret) {\n \t\tu32 mahr = ravb_read(ndev, MAHR);\n \t\tu32 malr = ravb_read(ndev, MALR);\n \n@@ -2189,7 +2191,7 @@ static int ravb_probe(struct platform_de\n \tpriv->msg_enable = RAVB_DEF_MSG_ENABLE;\n \n \t/* Read and set MAC address */\n-\travb_read_mac_address(ndev, of_get_mac_address(np));\n+\travb_read_mac_address(np, ndev);\n \tif (!is_valid_ether_addr(ndev->dev_addr)) {\n \t\tdev_warn(&pdev->dev,\n \t\t\t \"no valid MAC address supplied, using a random one\\n\");\n--- a/drivers/net/ethernet/renesas/sh_eth.c\n+++ b/drivers/net/ethernet/renesas/sh_eth.c\n@@ -3145,7 +3145,6 @@ static struct sh_eth_plat_data *sh_eth_p\n \tstruct device_node *np = dev->of_node;\n \tstruct sh_eth_plat_data *pdata;\n \tphy_interface_t interface;\n-\tconst char *mac_addr;\n \tint ret;\n \n \tpdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);\n@@ -3157,9 +3156,7 @@ static struct sh_eth_plat_data *sh_eth_p\n \t\treturn NULL;\n \tpdata->phy_interface = interface;\n \n-\tmac_addr = of_get_mac_address(np);\n-\tif (!IS_ERR(mac_addr))\n-\t\tether_addr_copy(pdata->mac_addr, mac_addr);\n+\tof_get_mac_address(np, pdata->mac_addr);\n \n \tpdata->no_ether_link =\n \t\tof_property_read_bool(np, \"renesas,no-ether-link\");\n--- a/drivers/net/ethernet/samsung/sxgbe/sxgbe_platform.c\n+++ b/drivers/net/ethernet/samsung/sxgbe/sxgbe_platform.c\n@@ -25,8 +25,7 @@\n \n #ifdef CONFIG_OF\n static int sxgbe_probe_config_dt(struct platform_device *pdev,\n-\t\t\t\t struct sxgbe_plat_data *plat,\n-\t\t\t\t const char **mac)\n+\t\t\t\t struct sxgbe_plat_data *plat)\n {\n \tstruct device_node *np = pdev->dev.of_node;\n \tstruct sxgbe_dma_cfg *dma_cfg;\n@@ -35,7 +34,6 @@ static int sxgbe_probe_config_dt(struct\n \tif (!np)\n \t\treturn -ENODEV;\n \n-\t*mac = of_get_mac_address(np);\n \terr = of_get_phy_mode(np, &plat->interface);\n \tif (err && err != -ENODEV)\n \t\treturn err;\n@@ -63,8 +61,7 @@ static int sxgbe_probe_config_dt(struct\n }\n #else\n static int sxgbe_probe_config_dt(struct platform_device *pdev,\n-\t\t\t\t struct sxgbe_plat_data *plat,\n-\t\t\t\t const char **mac)\n+\t\t\t\t struct sxgbe_plat_data *plat)\n {\n \treturn -ENOSYS;\n }\n@@ -85,7 +82,6 @@ static int sxgbe_platform_probe(struct p\n \tvoid __iomem *addr;\n \tstruct sxgbe_priv_data *priv = NULL;\n \tstruct sxgbe_plat_data *plat_dat = NULL;\n-\tconst char *mac = NULL;\n \tstruct net_device *ndev = platform_get_drvdata(pdev);\n \tstruct device_node *node = dev->of_node;\n \n@@ -101,7 +97,7 @@ static int sxgbe_platform_probe(struct p\n \t\tif (!plat_dat)\n \t\t\treturn  -ENOMEM;\n \n-\t\tret = sxgbe_probe_config_dt(pdev, plat_dat, &mac);\n+\t\tret = sxgbe_probe_config_dt(pdev, plat_dat);\n \t\tif (ret) {\n \t\t\tpr_err(\"%s: main dt probe failed\\n\", __func__);\n \t\t\treturn ret;\n@@ -122,8 +118,7 @@ static int sxgbe_platform_probe(struct p\n \t}\n \n \t/* Get MAC address if available (DT) */\n-\tif (!IS_ERR_OR_NULL(mac))\n-\t\tether_addr_copy(priv->dev->dev_addr, mac);\n+\tof_get_mac_address(node, priv->dev->dev_addr);\n \n \t/* Get the TX/RX IRQ numbers */\n \tfor (i = 0, chan = 1; i < SXGBE_TX_QUEUES; i++) {\n--- a/drivers/net/ethernet/socionext/sni_ave.c\n+++ b/drivers/net/ethernet/socionext/sni_ave.c\n@@ -1559,7 +1559,6 @@ static int ave_probe(struct platform_dev\n \tstruct ave_private *priv;\n \tstruct net_device *ndev;\n \tstruct device_node *np;\n-\tconst void *mac_addr;\n \tvoid __iomem *base;\n \tconst char *name;\n \tint i, irq, ret;\n@@ -1600,12 +1599,9 @@ static int ave_probe(struct platform_dev\n \n \tndev->max_mtu = AVE_MAX_ETHFRAME - (ETH_HLEN + ETH_FCS_LEN);\n \n-\tmac_addr = of_get_mac_address(np);\n-\tif (!IS_ERR(mac_addr))\n-\t\tether_addr_copy(ndev->dev_addr, mac_addr);\n-\n-\t/* if the mac address is invalid, use random mac address */\n-\tif (!is_valid_ether_addr(ndev->dev_addr)) {\n+\tret = of_get_mac_address(np, ndev->dev_addr);\n+\tif (ret) {\n+\t\t/* if the mac address is invalid, use random mac address */\n \t\teth_hw_addr_random(ndev);\n \t\tdev_warn(dev, \"Using random MAC address: %pM\\n\",\n \t\t\t ndev->dev_addr);\n--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-anarion.c\n+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-anarion.c\n@@ -115,7 +115,7 @@ static int anarion_dwmac_probe(struct pl\n \tif (IS_ERR(gmac))\n \t\treturn PTR_ERR(gmac);\n \n-\tplat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac);\n+\tplat_dat = stmmac_probe_config_dt(pdev, stmmac_res.mac);\n \tif (IS_ERR(plat_dat))\n \t\treturn PTR_ERR(plat_dat);\n \n--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-dwc-qos-eth.c\n+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-dwc-qos-eth.c\n@@ -444,7 +444,7 @@ static int dwc_eth_dwmac_probe(struct pl\n \tif (IS_ERR(stmmac_res.addr))\n \t\treturn PTR_ERR(stmmac_res.addr);\n \n-\tplat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac);\n+\tplat_dat = stmmac_probe_config_dt(pdev, stmmac_res.mac);\n \tif (IS_ERR(plat_dat))\n \t\treturn PTR_ERR(plat_dat);\n \n--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-generic.c\n+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-generic.c\n@@ -27,7 +27,7 @@ static int dwmac_generic_probe(struct pl\n \t\treturn ret;\n \n \tif (pdev->dev.of_node) {\n-\t\tplat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac);\n+\t\tplat_dat = stmmac_probe_config_dt(pdev, stmmac_res.mac);\n \t\tif (IS_ERR(plat_dat)) {\n \t\t\tdev_err(&pdev->dev, \"dt configuration failed\\n\");\n \t\t\treturn PTR_ERR(plat_dat);\n--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c\n+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c\n@@ -226,7 +226,7 @@ static int imx_dwmac_probe(struct platfo\n \tif (!dwmac)\n \t\treturn -ENOMEM;\n \n-\tplat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac);\n+\tplat_dat = stmmac_probe_config_dt(pdev, stmmac_res.mac);\n \tif (IS_ERR(plat_dat))\n \t\treturn PTR_ERR(plat_dat);\n \n--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel-plat.c\n+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel-plat.c\n@@ -88,7 +88,7 @@ static int intel_eth_plat_probe(struct p\n \tif (ret)\n \t\treturn ret;\n \n-\tplat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac);\n+\tplat_dat = stmmac_probe_config_dt(pdev, stmmac_res.mac);\n \tif (IS_ERR(plat_dat)) {\n \t\tdev_err(&pdev->dev, \"dt configuration failed\\n\");\n \t\treturn PTR_ERR(plat_dat);\n--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c\n+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c\n@@ -255,7 +255,7 @@ static int ipq806x_gmac_probe(struct pla\n \tif (val)\n \t\treturn val;\n \n-\tplat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac);\n+\tplat_dat = stmmac_probe_config_dt(pdev, stmmac_res.mac);\n \tif (IS_ERR(plat_dat))\n \t\treturn PTR_ERR(plat_dat);\n \n--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-lpc18xx.c\n+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-lpc18xx.c\n@@ -37,7 +37,7 @@ static int lpc18xx_dwmac_probe(struct pl\n \tif (ret)\n \t\treturn ret;\n \n-\tplat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac);\n+\tplat_dat = stmmac_probe_config_dt(pdev, stmmac_res.mac);\n \tif (IS_ERR(plat_dat))\n \t\treturn PTR_ERR(plat_dat);\n \n--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c\n+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c\n@@ -407,7 +407,7 @@ static int mediatek_dwmac_probe(struct p\n \tif (ret)\n \t\treturn ret;\n \n-\tplat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac);\n+\tplat_dat = stmmac_probe_config_dt(pdev, stmmac_res.mac);\n \tif (IS_ERR(plat_dat))\n \t\treturn PTR_ERR(plat_dat);\n \n--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson.c\n+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson.c\n@@ -52,7 +52,7 @@ static int meson6_dwmac_probe(struct pla\n \tif (ret)\n \t\treturn ret;\n \n-\tplat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac);\n+\tplat_dat = stmmac_probe_config_dt(pdev, stmmac_res.mac);\n \tif (IS_ERR(plat_dat))\n \t\treturn PTR_ERR(plat_dat);\n \n--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c\n+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c\n@@ -372,7 +372,7 @@ static int meson8b_dwmac_probe(struct pl\n \tif (ret)\n \t\treturn ret;\n \n-\tplat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac);\n+\tplat_dat = stmmac_probe_config_dt(pdev, stmmac_res.mac);\n \tif (IS_ERR(plat_dat))\n \t\treturn PTR_ERR(plat_dat);\n \n--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-oxnas.c\n+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-oxnas.c\n@@ -118,7 +118,7 @@ static int oxnas_dwmac_probe(struct plat\n \tif (ret)\n \t\treturn ret;\n \n-\tplat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac);\n+\tplat_dat = stmmac_probe_config_dt(pdev, stmmac_res.mac);\n \tif (IS_ERR(plat_dat))\n \t\treturn PTR_ERR(plat_dat);\n \n--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c\n+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c\n@@ -461,7 +461,7 @@ static int qcom_ethqos_probe(struct plat\n \tif (ret)\n \t\treturn ret;\n \n-\tplat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac);\n+\tplat_dat = stmmac_probe_config_dt(pdev, stmmac_res.mac);\n \tif (IS_ERR(plat_dat)) {\n \t\tdev_err(&pdev->dev, \"dt configuration failed\\n\");\n \t\treturn PTR_ERR(plat_dat);\n--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c\n+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c\n@@ -1392,7 +1392,7 @@ static int rk_gmac_probe(struct platform\n \tif (ret)\n \t\treturn ret;\n \n-\tplat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac);\n+\tplat_dat = stmmac_probe_config_dt(pdev, stmmac_res.mac);\n \tif (IS_ERR(plat_dat))\n \t\treturn PTR_ERR(plat_dat);\n \n--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c\n+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c\n@@ -395,7 +395,7 @@ static int socfpga_dwmac_probe(struct pl\n \tif (ret)\n \t\treturn ret;\n \n-\tplat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac);\n+\tplat_dat = stmmac_probe_config_dt(pdev, stmmac_res.mac);\n \tif (IS_ERR(plat_dat))\n \t\treturn PTR_ERR(plat_dat);\n \n--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c\n+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c\n@@ -325,7 +325,7 @@ static int sti_dwmac_probe(struct platfo\n \tif (ret)\n \t\treturn ret;\n \n-\tplat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac);\n+\tplat_dat = stmmac_probe_config_dt(pdev, stmmac_res.mac);\n \tif (IS_ERR(plat_dat))\n \t\treturn PTR_ERR(plat_dat);\n \n--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c\n+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c\n@@ -371,7 +371,7 @@ static int stm32_dwmac_probe(struct plat\n \tif (ret)\n \t\treturn ret;\n \n-\tplat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac);\n+\tplat_dat = stmmac_probe_config_dt(pdev, stmmac_res.mac);\n \tif (IS_ERR(plat_dat))\n \t\treturn PTR_ERR(plat_dat);\n \n--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c\n+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c\n@@ -1202,7 +1202,7 @@ static int sun8i_dwmac_probe(struct plat\n \tif (ret)\n \t\treturn -EINVAL;\n \n-\tplat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac);\n+\tplat_dat = stmmac_probe_config_dt(pdev, stmmac_res.mac);\n \tif (IS_ERR(plat_dat))\n \t\treturn PTR_ERR(plat_dat);\n \n--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sunxi.c\n+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sunxi.c\n@@ -108,7 +108,7 @@ static int sun7i_gmac_probe(struct platf\n \tif (ret)\n \t\treturn ret;\n \n-\tplat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac);\n+\tplat_dat = stmmac_probe_config_dt(pdev, stmmac_res.mac);\n \tif (IS_ERR(plat_dat))\n \t\treturn PTR_ERR(plat_dat);\n \n--- a/drivers/net/ethernet/stmicro/stmmac/stmmac.h\n+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac.h\n@@ -25,7 +25,7 @@\n \n struct stmmac_resources {\n \tvoid __iomem *addr;\n-\tconst char *mac;\n+\tu8 mac[ETH_ALEN];\n \tint wol_irq;\n \tint lpi_irq;\n \tint irq;\n--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c\n+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c\n@@ -4988,7 +4988,7 @@ int stmmac_dvr_probe(struct device *devi\n \tpriv->wol_irq = res->wol_irq;\n \tpriv->lpi_irq = res->lpi_irq;\n \n-\tif (!IS_ERR_OR_NULL(res->mac))\n+\tif (!is_zero_ether_addr(res->mac))\n \t\tmemcpy(priv->dev->dev_addr, res->mac, ETH_ALEN);\n \n \tdev_set_drvdata(device, priv->dev);\n--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c\n+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c\n@@ -395,7 +395,7 @@ static int stmmac_of_get_mac_mode(struct\n  * set some private fields that will be used by the main at runtime.\n  */\n struct plat_stmmacenet_data *\n-stmmac_probe_config_dt(struct platform_device *pdev, const char **mac)\n+stmmac_probe_config_dt(struct platform_device *pdev, u8 *mac)\n {\n \tstruct device_node *np = pdev->dev.of_node;\n \tstruct plat_stmmacenet_data *plat;\n@@ -407,12 +407,12 @@ stmmac_probe_config_dt(struct platform_d\n \tif (!plat)\n \t\treturn ERR_PTR(-ENOMEM);\n \n-\t*mac = of_get_mac_address(np);\n-\tif (IS_ERR(*mac)) {\n-\t\tif (PTR_ERR(*mac) == -EPROBE_DEFER)\n-\t\t\treturn ERR_CAST(*mac);\n+\trc = of_get_mac_address(np, mac);\n+\tif (rc) {\n+\t\tif (rc == -EPROBE_DEFER)\n+\t\t\treturn ERR_PTR(rc);\n \n-\t\t*mac = NULL;\n+\t\teth_zero_addr(mac);\n \t}\n \n \tphy_mode = device_get_phy_mode(&pdev->dev);\n@@ -643,7 +643,7 @@ void stmmac_remove_config_dt(struct plat\n }\n #else\n struct plat_stmmacenet_data *\n-stmmac_probe_config_dt(struct platform_device *pdev, const char **mac)\n+stmmac_probe_config_dt(struct platform_device *pdev, u8 *mac)\n {\n \treturn ERR_PTR(-EINVAL);\n }\n--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.h\n+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.h\n@@ -12,7 +12,7 @@\n #include \"stmmac.h\"\n \n struct plat_stmmacenet_data *\n-stmmac_probe_config_dt(struct platform_device *pdev, const char **mac);\n+stmmac_probe_config_dt(struct platform_device *pdev, u8 *mac);\n void stmmac_remove_config_dt(struct platform_device *pdev,\n \t\t\t     struct plat_stmmacenet_data *plat);\n \n--- a/drivers/net/ethernet/ti/am65-cpsw-nuss.c\n+++ b/drivers/net/ethernet/ti/am65-cpsw-nuss.c\n@@ -1741,7 +1741,6 @@ static int am65_cpsw_nuss_init_slave_por\n \n \tfor_each_child_of_node(node, port_np) {\n \t\tstruct am65_cpsw_port *port;\n-\t\tconst void *mac_addr;\n \t\tu32 port_id;\n \n \t\t/* it is not a slave port node, continue */\n@@ -1820,15 +1819,15 @@ static int am65_cpsw_nuss_init_slave_por\n \t\t\treturn ret;\n \t\t}\n \n-\t\tmac_addr = of_get_mac_address(port_np);\n-\t\tif (!IS_ERR(mac_addr)) {\n-\t\t\tether_addr_copy(port->slave.mac_addr, mac_addr);\n-\t\t} else if (am65_cpsw_am654_get_efuse_macid(port_np,\n-\t\t\t\t\t\t\t   port->port_id,\n-\t\t\t\t\t\t\t   port->slave.mac_addr) ||\n-\t\t\t   !is_valid_ether_addr(port->slave.mac_addr)) {\n-\t\t\trandom_ether_addr(port->slave.mac_addr);\n-\t\t\tdev_err(dev, \"Use random MAC address\\n\");\n+\t\tret = of_get_mac_address(port_np, port->slave.mac_addr);\n+\t\tif (ret) {\n+\t\t\tam65_cpsw_am654_get_efuse_macid(port_np,\n+\t\t\t\t\t\t\tport->port_id,\n+\t\t\t\t\t\t\tport->slave.mac_addr);\n+\t\t\tif (!is_valid_ether_addr(port->slave.mac_addr)) {\n+\t\t\t\trandom_ether_addr(port->slave.mac_addr);\n+\t\t\t\tdev_err(dev, \"Use random MAC address\\n\");\n+\t\t\t}\n \t\t}\n \t}\n \tof_node_put(node);\n--- a/drivers/net/ethernet/ti/cpsw.c\n+++ b/drivers/net/ethernet/ti/cpsw.c\n@@ -1306,7 +1306,6 @@ static int cpsw_probe_dt(struct cpsw_pla\n \n \tfor_each_available_child_of_node(node, slave_node) {\n \t\tstruct cpsw_slave_data *slave_data = data->slave_data + i;\n-\t\tconst void *mac_addr = NULL;\n \t\tint lenp;\n \t\tconst __be32 *parp;\n \n@@ -1378,10 +1377,8 @@ static int cpsw_probe_dt(struct cpsw_pla\n \t\t}\n \n no_phy_slave:\n-\t\tmac_addr = of_get_mac_address(slave_node);\n-\t\tif (!IS_ERR(mac_addr)) {\n-\t\t\tether_addr_copy(slave_data->mac_addr, mac_addr);\n-\t\t} else {\n+\t\tret = of_get_mac_address(slave_node, slave_data->mac_addr);\n+\t\tif (ret) {\n \t\t\tret = ti_cm_get_macid(&pdev->dev, i,\n \t\t\t\t\t      slave_data->mac_addr);\n \t\t\tif (ret)\n--- a/drivers/net/ethernet/ti/cpsw_new.c\n+++ b/drivers/net/ethernet/ti/cpsw_new.c\n@@ -1267,7 +1267,6 @@ static int cpsw_probe_dt(struct cpsw_com\n \n \tfor_each_child_of_node(tmp_node, port_np) {\n \t\tstruct cpsw_slave_data *slave_data;\n-\t\tconst void *mac_addr;\n \t\tu32 port_id;\n \n \t\tret = of_property_read_u32(port_np, \"reg\", &port_id);\n@@ -1326,10 +1325,8 @@ static int cpsw_probe_dt(struct cpsw_com\n \t\t\tgoto err_node_put;\n \t\t}\n \n-\t\tmac_addr = of_get_mac_address(port_np);\n-\t\tif (!IS_ERR(mac_addr)) {\n-\t\t\tether_addr_copy(slave_data->mac_addr, mac_addr);\n-\t\t} else {\n+\t\tret = of_get_mac_address(port_np, slave_data->mac_addr);\n+\t\tif (ret) {\n \t\t\tret = ti_cm_get_macid(dev, port_id - 1,\n \t\t\t\t\t      slave_data->mac_addr);\n \t\t\tif (ret)\n--- a/drivers/net/ethernet/ti/davinci_emac.c\n+++ b/drivers/net/ethernet/ti/davinci_emac.c\n@@ -1699,7 +1699,6 @@ davinci_emac_of_get_pdata(struct platfor\n \tconst struct of_device_id *match;\n \tconst struct emac_platform_data *auxdata;\n \tstruct emac_platform_data *pdata = NULL;\n-\tconst u8 *mac_addr;\n \n \tif (!IS_ENABLED(CONFIG_OF) || !pdev->dev.of_node)\n \t\treturn dev_get_platdata(&pdev->dev);\n@@ -1711,11 +1710,8 @@ davinci_emac_of_get_pdata(struct platfor\n \tnp = pdev->dev.of_node;\n \tpdata->version = EMAC_VERSION_2;\n \n-\tif (!is_valid_ether_addr(pdata->mac_addr)) {\n-\t\tmac_addr = of_get_mac_address(np);\n-\t\tif (!IS_ERR(mac_addr))\n-\t\t\tether_addr_copy(pdata->mac_addr, mac_addr);\n-\t}\n+\tif (!is_valid_ether_addr(pdata->mac_addr))\n+\t\tof_get_mac_address(np, pdata->mac_addr);\n \n \tof_property_read_u32(np, \"ti,davinci-ctrl-reg-offset\",\n \t\t\t     &pdata->ctrl_reg_offset);\n--- a/drivers/net/ethernet/ti/netcp_core.c\n+++ b/drivers/net/ethernet/ti/netcp_core.c\n@@ -1966,7 +1966,6 @@ static int netcp_create_interface(struct\n \tstruct resource res;\n \tvoid __iomem *efuse = NULL;\n \tu32 efuse_mac = 0;\n-\tconst void *mac_addr;\n \tu8 efuse_mac_addr[6];\n \tu32 temp[2];\n \tint ret = 0;\n@@ -2036,10 +2035,8 @@ static int netcp_create_interface(struct\n \t\tdevm_iounmap(dev, efuse);\n \t\tdevm_release_mem_region(dev, res.start, size);\n \t} else {\n-\t\tmac_addr = of_get_mac_address(node_interface);\n-\t\tif (!IS_ERR(mac_addr))\n-\t\t\tether_addr_copy(ndev->dev_addr, mac_addr);\n-\t\telse\n+\t\tret = of_get_mac_address(node_interface, ndev->dev_addr);\n+\t\tif (ret)\n \t\t\teth_random_addr(ndev->dev_addr);\n \t}\n \n--- a/drivers/net/ethernet/wiznet/w5100-spi.c\n+++ b/drivers/net/ethernet/wiznet/w5100-spi.c\n@@ -423,8 +423,14 @@ static int w5100_spi_probe(struct spi_de\n \tconst struct of_device_id *of_id;\n \tconst struct w5100_ops *ops;\n \tkernel_ulong_t driver_data;\n+\tconst void *mac = NULL;\n+\tu8 tmpmac[ETH_ALEN];\n \tint priv_size;\n-\tconst void *mac = of_get_mac_address(spi->dev.of_node);\n+\tint ret;\n+\n+\tret = of_get_mac_address(spi->dev.of_node, tmpmac);\n+\tif (!ret)\n+\t\tmac = tmpmac;\n \n \tif (spi->dev.of_node) {\n \t\tof_id = of_match_device(w5100_of_match, &spi->dev);\n--- a/drivers/net/ethernet/wiznet/w5100.c\n+++ b/drivers/net/ethernet/wiznet/w5100.c\n@@ -1159,7 +1159,7 @@ int w5100_probe(struct device *dev, cons\n \tINIT_WORK(&priv->setrx_work, w5100_setrx_work);\n \tINIT_WORK(&priv->restart_work, w5100_restart_work);\n \n-\tif (!IS_ERR_OR_NULL(mac_addr))\n+\tif (mac_addr)\n \t\tmemcpy(ndev->dev_addr, mac_addr, ETH_ALEN);\n \telse\n \t\teth_hw_addr_random(ndev);\n--- a/drivers/net/ethernet/xilinx/ll_temac_main.c\n+++ b/drivers/net/ethernet/xilinx/ll_temac_main.c\n@@ -438,7 +438,7 @@ static void temac_do_set_mac_address(str\n \n static int temac_init_mac_address(struct net_device *ndev, const void *address)\n {\n-\tether_addr_copy(ndev->dev_addr, address);\n+\tmemcpy(ndev->dev_addr, address, ETH_ALEN);\n \tif (!is_valid_ether_addr(ndev->dev_addr))\n \t\teth_hw_addr_random(ndev);\n \ttemac_do_set_mac_address(ndev);\n@@ -1370,7 +1370,7 @@ static int temac_probe(struct platform_d\n \tstruct device_node *temac_np = dev_of_node(&pdev->dev), *dma_np;\n \tstruct temac_local *lp;\n \tstruct net_device *ndev;\n-\tconst void *addr;\n+\tu8 addr[ETH_ALEN];\n \t__be32 *p;\n \tbool little_endian;\n \tint rc = 0;\n@@ -1563,8 +1563,8 @@ static int temac_probe(struct platform_d\n \n \tif (temac_np) {\n \t\t/* Retrieve the MAC address */\n-\t\taddr = of_get_mac_address(temac_np);\n-\t\tif (IS_ERR(addr)) {\n+\t\trc = of_get_mac_address(temac_np, addr);\n+\t\tif (rc) {\n \t\t\tdev_err(&pdev->dev, \"could not find MAC address\\n\");\n \t\t\treturn -ENODEV;\n \t\t}\n--- a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c\n+++ b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c\n@@ -1843,8 +1843,8 @@ static int axienet_probe(struct platform\n \tstruct device_node *np;\n \tstruct axienet_local *lp;\n \tstruct net_device *ndev;\n-\tconst void *mac_addr;\n \tstruct resource *ethres;\n+\tu8 mac_addr[ETH_ALEN];\n \tint addr_width = 32;\n \tu32 value;\n \n@@ -2044,13 +2044,14 @@ static int axienet_probe(struct platform\n \t\tdev_info(&pdev->dev, \"Ethernet core IRQ not defined\\n\");\n \n \t/* Retrieve the MAC address */\n-\tmac_addr = of_get_mac_address(pdev->dev.of_node);\n-\tif (IS_ERR(mac_addr)) {\n-\t\tdev_warn(&pdev->dev, \"could not find MAC address property: %ld\\n\",\n-\t\t\t PTR_ERR(mac_addr));\n-\t\tmac_addr = NULL;\n+\tret = of_get_mac_address(pdev->dev.of_node, mac_addr);\n+\tif (!ret) {\n+\t\taxienet_set_mac_address(ndev, mac_addr);\n+\t} else {\n+\t\tdev_warn(&pdev->dev, \"could not find MAC address property: %d\\n\",\n+\t\t\t ret);\n+\t\taxienet_set_mac_address(ndev, NULL);\n \t}\n-\taxienet_set_mac_address(ndev, mac_addr);\n \n \tlp->coalesce_count_rx = XAXIDMA_DFT_RX_THRESHOLD;\n \tlp->coalesce_count_tx = XAXIDMA_DFT_TX_THRESHOLD;\n--- a/drivers/net/ethernet/xilinx/xilinx_emaclite.c\n+++ b/drivers/net/ethernet/xilinx/xilinx_emaclite.c\n@@ -1113,7 +1113,6 @@ static int xemaclite_of_probe(struct pla\n \tstruct net_device *ndev = NULL;\n \tstruct net_local *lp = NULL;\n \tstruct device *dev = &ofdev->dev;\n-\tconst void *mac_address;\n \n \tint rc = 0;\n \n@@ -1155,12 +1154,9 @@ static int xemaclite_of_probe(struct pla\n \tlp->next_rx_buf_to_use = 0x0;\n \tlp->tx_ping_pong = get_bool(ofdev, \"xlnx,tx-ping-pong\");\n \tlp->rx_ping_pong = get_bool(ofdev, \"xlnx,rx-ping-pong\");\n-\tmac_address = of_get_mac_address(ofdev->dev.of_node);\n \n-\tif (!IS_ERR(mac_address)) {\n-\t\t/* Set the MAC address. */\n-\t\tether_addr_copy(ndev->dev_addr, mac_address);\n-\t} else {\n+\trc = of_get_mac_address(ofdev->dev.of_node, ndev->dev_addr);\n+\tif (rc) {\n \t\tdev_warn(dev, \"No MAC address found, using random\\n\");\n \t\teth_hw_addr_random(ndev);\n \t}\n--- a/drivers/net/wireless/ath/ath9k/init.c\n+++ b/drivers/net/wireless/ath/ath9k/init.c\n@@ -618,7 +618,6 @@ static int ath9k_of_init(struct ath_soft\n \tstruct ath_hw *ah = sc->sc_ah;\n \tstruct ath_common *common = ath9k_hw_common(ah);\n \tenum ath_bus_type bus_type = common->bus_ops->ath_bus_type;\n-\tconst char *mac;\n \tchar eeprom_name[100];\n \tint ret;\n \n@@ -641,9 +640,7 @@ static int ath9k_of_init(struct ath_soft\n \t\tah->ah_flags |= AH_NO_EEP_SWAP;\n \t}\n \n-\tmac = of_get_mac_address(np);\n-\tif (!IS_ERR(mac))\n-\t\tether_addr_copy(common->macaddr, mac);\n+\tof_get_mac_address(np, common->macaddr);\n \n \treturn 0;\n }\n--- a/drivers/net/wireless/mediatek/mt76/eeprom.c\n+++ b/drivers/net/wireless/mediatek/mt76/eeprom.c\n@@ -90,15 +90,9 @@ out_put_node:\n void\n mt76_eeprom_override(struct mt76_dev *dev)\n {\n-#ifdef CONFIG_OF\n \tstruct device_node *np = dev->dev->of_node;\n-\tconst u8 *mac = NULL;\n \n-\tif (np)\n-\t\tmac = of_get_mac_address(np);\n-\tif (!IS_ERR_OR_NULL(mac))\n-\t\tether_addr_copy(dev->macaddr, mac);\n-#endif\n+\tof_get_mac_address(np, dev->macaddr);\n \n \tif (!is_valid_ether_addr(dev->macaddr)) {\n \t\teth_random_addr(dev->macaddr);\n--- a/drivers/net/wireless/ralink/rt2x00/rt2x00dev.c\n+++ b/drivers/net/wireless/ralink/rt2x00/rt2x00dev.c\n@@ -990,11 +990,7 @@ static void rt2x00lib_rate(struct ieee80\n \n void rt2x00lib_set_mac_address(struct rt2x00_dev *rt2x00dev, u8 *eeprom_mac_addr)\n {\n-\tconst char *mac_addr;\n-\n-\tmac_addr = of_get_mac_address(rt2x00dev->dev->of_node);\n-\tif (!IS_ERR(mac_addr))\n-\t\tether_addr_copy(eeprom_mac_addr, mac_addr);\n+\tof_get_mac_address(rt2x00dev->dev->of_node, eeprom_mac_addr);\n \n \tif (!is_valid_ether_addr(eeprom_mac_addr)) {\n \t\teth_random_addr(eeprom_mac_addr);\n--- a/drivers/of/of_net.c\n+++ b/drivers/of/of_net.c\n@@ -45,37 +45,29 @@ int of_get_phy_mode(struct device_node *\n }\n EXPORT_SYMBOL_GPL(of_get_phy_mode);\n \n-static const void *of_get_mac_addr(struct device_node *np, const char *name)\n+static int of_get_mac_addr(struct device_node *np, const char *name, u8 *addr)\n {\n \tstruct property *pp = of_find_property(np, name, NULL);\n \n-\tif (pp && pp->length == ETH_ALEN && is_valid_ether_addr(pp->value))\n-\t\treturn pp->value;\n-\treturn NULL;\n+\tif (pp && pp->length == ETH_ALEN && is_valid_ether_addr(pp->value)) {\n+\t\tmemcpy(addr, pp->value, ETH_ALEN);\n+\t\treturn 0;\n+\t}\n+\treturn -ENODEV;\n }\n \n-static const void *of_get_mac_addr_nvmem(struct device_node *np)\n+static int of_get_mac_addr_nvmem(struct device_node *np, u8 *addr)\n {\n-\tint ret;\n-\tconst void *mac;\n-\tu8 nvmem_mac[ETH_ALEN];\n \tstruct platform_device *pdev = of_find_device_by_node(np);\n+\tint ret;\n \n \tif (!pdev)\n-\t\treturn ERR_PTR(-ENODEV);\n+\t\treturn -ENODEV;\n \n-\tret = nvmem_get_mac_address(&pdev->dev, &nvmem_mac);\n-\tif (ret) {\n-\t\tput_device(&pdev->dev);\n-\t\treturn ERR_PTR(ret);\n-\t}\n-\n-\tmac = devm_kmemdup(&pdev->dev, nvmem_mac, ETH_ALEN, GFP_KERNEL);\n+\tret = nvmem_get_mac_address(&pdev->dev, addr);\n \tput_device(&pdev->dev);\n-\tif (!mac)\n-\t\treturn ERR_PTR(-ENOMEM);\n \n-\treturn mac;\n+\treturn ret;\n }\n \n /**\n@@ -98,24 +90,27 @@ static const void *of_get_mac_addr_nvmem\n  * this case, the real MAC is in 'local-mac-address', and 'mac-address' exists\n  * but is all zeros.\n  *\n- * Return: Will be a valid pointer on success and ERR_PTR in case of error.\n+ * Return: 0 on success and errno in case of error.\n */\n-const void *of_get_mac_address(struct device_node *np)\n+int of_get_mac_address(struct device_node *np, u8 *addr)\n {\n-\tconst void *addr;\n-\n-\taddr = of_get_mac_addr(np, \"mac-address\");\n-\tif (addr)\n-\t\treturn addr;\n+\tint ret;\n \n-\taddr = of_get_mac_addr(np, \"local-mac-address\");\n-\tif (addr)\n-\t\treturn addr;\n+\tif (!np)\n+\t\treturn -ENODEV;\n \n-\taddr = of_get_mac_addr(np, \"address\");\n-\tif (addr)\n-\t\treturn addr;\n+\tret = of_get_mac_addr(np, \"mac-address\", addr);\n+\tif (!ret)\n+\t\treturn 0;\n+\n+\tret = of_get_mac_addr(np, \"local-mac-address\", addr);\n+\tif (!ret)\n+\t\treturn 0;\n+\n+\tret = of_get_mac_addr(np, \"address\", addr);\n+\tif (!ret)\n+\t\treturn 0;\n \n-\treturn of_get_mac_addr_nvmem(np);\n+\treturn of_get_mac_addr_nvmem(np, addr);\n }\n EXPORT_SYMBOL(of_get_mac_address);\n--- a/drivers/staging/octeon/ethernet.c\n+++ b/drivers/staging/octeon/ethernet.c\n@@ -407,14 +407,10 @@ static int cvm_oct_common_set_mac_addres\n int cvm_oct_common_init(struct net_device *dev)\n {\n \tstruct octeon_ethernet *priv = netdev_priv(dev);\n-\tconst u8 *mac = NULL;\n+\tint ret;\n \n-\tif (priv->of_node)\n-\t\tmac = of_get_mac_address(priv->of_node);\n-\n-\tif (!IS_ERR_OR_NULL(mac))\n-\t\tether_addr_copy(dev->dev_addr, mac);\n-\telse\n+\tret = of_get_mac_address(priv->of_node, dev->dev_addr);\n+\tif (ret)\n \t\teth_hw_addr_random(dev);\n \n \t/*\n--- a/drivers/staging/wfx/main.c\n+++ b/drivers/staging/wfx/main.c\n@@ -339,7 +339,6 @@ int wfx_probe(struct wfx_dev *wdev)\n {\n \tint i;\n \tint err;\n-\tconst void *macaddr;\n \tstruct gpio_desc *gpio_saved;\n \n \t// During first part of boot, gpio_wakeup cannot yet been used. So\n@@ -428,9 +427,9 @@ int wfx_probe(struct wfx_dev *wdev)\n \n \tfor (i = 0; i < ARRAY_SIZE(wdev->addresses); i++) {\n \t\teth_zero_addr(wdev->addresses[i].addr);\n-\t\tmacaddr = of_get_mac_address(wdev->dev->of_node);\n-\t\tif (!IS_ERR_OR_NULL(macaddr)) {\n-\t\t\tether_addr_copy(wdev->addresses[i].addr, macaddr);\n+\t\terr = of_get_mac_address(wdev->dev->of_node,\n+\t\t\t\t\t wdev->addresses[i].addr);\n+\t\tif (!err) {\n \t\t\twdev->addresses[i].addr[ETH_ALEN - 1] += i;\n \t\t} else {\n \t\t\tether_addr_copy(wdev->addresses[i].addr,\n--- a/include/linux/of_net.h\n+++ b/include/linux/of_net.h\n@@ -13,7 +13,7 @@\n \n struct net_device;\n extern int of_get_phy_mode(struct device_node *np, phy_interface_t *interface);\n-extern const void *of_get_mac_address(struct device_node *np);\n+extern int of_get_mac_address(struct device_node *np, u8 *mac);\n extern struct net_device *of_find_net_device_by_node(struct device_node *np);\n #else\n static inline int of_get_phy_mode(struct device_node *np,\n@@ -22,9 +22,9 @@ static inline int of_get_phy_mode(struct\n \treturn -ENODEV;\n }\n \n-static inline const void *of_get_mac_address(struct device_node *np)\n+static inline int of_get_mac_address(struct device_node *np, u8 *mac)\n {\n-\treturn ERR_PTR(-ENODEV);\n+\treturn -ENODEV;\n }\n \n static inline struct net_device *of_find_net_device_by_node(struct device_node *np)\n--- a/include/net/dsa.h\n+++ b/include/net/dsa.h\n@@ -208,7 +208,7 @@ struct dsa_port {\n \tunsigned int\t\tindex;\n \tconst char\t\t*name;\n \tstruct dsa_port\t\t*cpu_dp;\n-\tconst char\t\t*mac;\n+\tu8\t\t\tmac[ETH_ALEN];\n \tstruct device_node\t*dn;\n \tunsigned int\t\tageing_time;\n \tbool\t\t\tvlan_filtering;\n--- a/net/dsa/dsa2.c\n+++ b/net/dsa/dsa2.c\n@@ -288,7 +288,7 @@ static int dsa_port_setup(struct dsa_por\n \n \t\tbreak;\n \tcase DSA_PORT_TYPE_USER:\n-\t\tdp->mac = of_get_mac_address(dp->dn);\n+\t\tof_get_mac_address(dp->dn, dp->mac);\n \t\terr = dsa_slave_create(dp);\n \t\tif (err)\n \t\t\tbreak;\n--- a/net/dsa/slave.c\n+++ b/net/dsa/slave.c\n@@ -1855,7 +1855,7 @@ int dsa_slave_create(struct dsa_port *po\n \tslave_dev->hw_features |= NETIF_F_HW_TC;\n \tslave_dev->features |= NETIF_F_LLTX;\n \tslave_dev->ethtool_ops = &dsa_slave_ethtool_ops;\n-\tif (!IS_ERR_OR_NULL(port->mac))\n+\tif (!is_zero_ether_addr(port->mac))\n \t\tether_addr_copy(slave_dev->dev_addr, port->mac);\n \telse\n \t\teth_hw_addr_inherit(slave_dev, master);\n--- a/net/ethernet/eth.c\n+++ b/net/ethernet/eth.c\n@@ -506,13 +506,14 @@ unsigned char * __weak arch_get_platform\n \n int eth_platform_get_mac_address(struct device *dev, u8 *mac_addr)\n {\n-\tconst unsigned char *addr = NULL;\n+\tunsigned char *addr;\n+\tint ret;\n \n-\tif (dev->of_node)\n-\t\taddr = of_get_mac_address(dev->of_node);\n-\tif (IS_ERR_OR_NULL(addr))\n-\t\taddr = arch_get_platform_mac_address();\n+\tret = of_get_mac_address(dev->of_node, mac_addr);\n+\tif (!ret)\n+\t\treturn 0;\n \n+\taddr = arch_get_platform_mac_address();\n \tif (!addr)\n \t\treturn -ENODEV;\n \n"
  },
  {
    "path": "target/linux/generic/backport-5.10/732-net-next-2-of-net-fix-of_get_mac_addr_nvmem-for-non-platform-devices.patch",
    "content": "From f10843e04a075202dbb39dfcee047e3a2fdf5a8d Mon Sep 17 00:00:00 2001\nFrom: Michael Walle <michael@walle.cc>\nDate: Mon, 12 Apr 2021 19:47:18 +0200\nSubject: of: net: fix of_get_mac_addr_nvmem() for non-platform devices\n\nof_get_mac_address() already supports fetching the MAC address by an\nnvmem provider. But until now, it was just working for platform devices.\nEsp. it was not working for DSA ports and PCI devices. It gets more\ncommon that PCI devices have a device tree binding since SoCs contain\nintegrated root complexes.\n\nUse the nvmem of_* binding to fetch the nvmem cells by a struct\ndevice_node. We still have to try to read the cell by device first\nbecause there might be a nvmem_cell_lookup associated with that device.\n\nSigned-off-by: Michael Walle <michael@walle.cc>\nReviewed-by: Andrew Lunn <andrew@lunn.ch>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/of/of_net.c | 35 ++++++++++++++++++++++++++++++-----\n 1 file changed, 30 insertions(+), 5 deletions(-)\n\n--- a/drivers/of/of_net.c\n+++ b/drivers/of/of_net.c\n@@ -11,6 +11,7 @@\n #include <linux/phy.h>\n #include <linux/export.h>\n #include <linux/device.h>\n+#include <linux/nvmem-consumer.h>\n \n /**\n  * of_get_phy_mode - Get phy mode for given device_node\n@@ -59,15 +60,39 @@ static int of_get_mac_addr(struct device\n static int of_get_mac_addr_nvmem(struct device_node *np, u8 *addr)\n {\n \tstruct platform_device *pdev = of_find_device_by_node(np);\n+\tstruct nvmem_cell *cell;\n+\tconst void *mac;\n+\tsize_t len;\n \tint ret;\n \n-\tif (!pdev)\n-\t\treturn -ENODEV;\n+\t/* Try lookup by device first, there might be a nvmem_cell_lookup\n+\t * associated with a given device.\n+\t */\n+\tif (pdev) {\n+\t\tret = nvmem_get_mac_address(&pdev->dev, addr);\n+\t\tput_device(&pdev->dev);\n+\t\treturn ret;\n+\t}\n+\n+\tcell = of_nvmem_cell_get(np, \"mac-address\");\n+\tif (IS_ERR(cell))\n+\t\treturn PTR_ERR(cell);\n+\n+\tmac = nvmem_cell_read(cell, &len);\n+\tnvmem_cell_put(cell);\n+\n+\tif (IS_ERR(mac))\n+\t\treturn PTR_ERR(mac);\n+\n+\tif (len != ETH_ALEN || !is_valid_ether_addr(mac)) {\n+\t\tkfree(mac);\n+\t\treturn -EINVAL;\n+\t}\n \n-\tret = nvmem_get_mac_address(&pdev->dev, addr);\n-\tput_device(&pdev->dev);\n+\tmemcpy(addr, mac, ETH_ALEN);\n+\tkfree(mac);\n \n-\treturn ret;\n+\treturn 0;\n }\n \n /**\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/733-v5.15-0001-net-bgmac-bcma-handle-deferred-probe-error-due-to-ma.patch",
    "content": "From 029497e66bdc762e001880e4c85a91f35a54b1e2 Mon Sep 17 00:00:00 2001\nFrom: Christian Lamparter <chunkeey@gmail.com>\nDate: Sun, 19 Sep 2021 13:57:25 +0200\nSubject: [PATCH] net: bgmac-bcma: handle deferred probe error due to\n mac-address\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nDue to the inclusion of nvmem handling into the mac-address getter\nfunction of_get_mac_address() by\ncommit d01f449c008a (\"of_net: add NVMEM support to of_get_mac_address\")\nit is now possible to get a -EPROBE_DEFER return code. Which did cause\nbgmac to assign a random ethernet address.\n\nThis exact issue happened on my Meraki MR32. The nvmem provider is\nan EEPROM (at24c64) which gets instantiated once the module\ndriver is loaded... This happens once the filesystem becomes available.\n\nWith this patch, bgmac_probe() will propagate the -EPROBE_DEFER error.\nThen the driver subsystem will reschedule the probe at a later time.\n\nCc: Petr Štetiar <ynezz@true.cz>\nCc: Michael Walle <michael@walle.cc>\nFixes: d01f449c008a (\"of_net: add NVMEM support to of_get_mac_address\")\nSigned-off-by: Christian Lamparter <chunkeey@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/ethernet/broadcom/bgmac-bcma.c | 2 ++\n 1 file changed, 2 insertions(+)\n\n--- a/drivers/net/ethernet/broadcom/bgmac-bcma.c\n+++ b/drivers/net/ethernet/broadcom/bgmac-bcma.c\n@@ -129,6 +129,8 @@ static int bgmac_probe(struct bcma_devic\n \tbcma_set_drvdata(core, bgmac);\n \n \terr = of_get_mac_address(bgmac->dev->of_node, bgmac->net_dev->dev_addr);\n+\tif (err == -EPROBE_DEFER)\n+\t\treturn err;\n \n \t/* If no MAC address assigned via device tree, check SPROM */\n \tif (err) {\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/733-v5.15-0002-net-bgmac-platform-handle-mac-address-deferral.patch",
    "content": "From 763716a55cb1f480ffe1a9702e6b5d9ea1a80a24 Mon Sep 17 00:00:00 2001\nFrom: Matthew Hagan <mnhagan88@gmail.com>\nDate: Sat, 25 Sep 2021 11:36:27 +0000\nSubject: [PATCH] net: bgmac-platform: handle mac-address deferral\n\nThis patch is a replication of Christian Lamparter's \"net: bgmac-bcma:\nhandle deferred probe error due to mac-address\" patch for the\nbgmac-platform driver [1].\n\nAs is the case with the bgmac-bcma driver, this change is to cover the\nscenario where the MAC address cannot yet be discovered due to reliance\non an nvmem provider which is yet to be instantiated, resulting in a\nrandom address being assigned that has to be manually overridden.\n\n[1] https://lore.kernel.org/netdev/20210919115725.29064-1-chunkeey@gmail.com\n\nSigned-off-by: Matthew Hagan <mnhagan88@gmail.com>\nReviewed-by: Andrew Lunn <andrew@lunn.ch>\nReviewed-by: Florian Fainelli <f.fainelli@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/ethernet/broadcom/bgmac-platform.c | 3 +++\n 1 file changed, 3 insertions(+)\n\n--- a/drivers/net/ethernet/broadcom/bgmac-platform.c\n+++ b/drivers/net/ethernet/broadcom/bgmac-platform.c\n@@ -193,6 +193,9 @@ static int bgmac_probe(struct platform_d\n \tbgmac->dma_dev = &pdev->dev;\n \n \tret = of_get_mac_address(np, bgmac->net_dev->dev_addr);\n+\tif (ret == -EPROBE_DEFER)\n+\t\treturn ret;\n+\n \tif (ret)\n \t\tdev_warn(&pdev->dev,\n \t\t\t \"MAC address not present in device tree\\n\");\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/734-v5.16-0001-net-bgmac-improve-handling-PHY.patch",
    "content": "From b5375509184dc23d2b7fa0c5ed8763899ccc9674 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Sat, 2 Oct 2021 19:58:11 +0200\nSubject: [PATCH] net: bgmac: improve handling PHY\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\n1. Use info from DT if available\n\nIt allows describing for example a fixed link. It's more accurate than\njust guessing there may be one (depending on a chipset).\n\n2. Verify PHY ID before trying to connect PHY\n\nPHY addr 0x1e (30) is special in Broadcom routers and means a switch\nconnected as MDIO devices instead of a real PHY. Don't try connecting to\nit.\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/ethernet/broadcom/bgmac-bcma.c | 33 ++++++++++++++--------\n 1 file changed, 21 insertions(+), 12 deletions(-)\n\n--- a/drivers/net/ethernet/broadcom/bgmac-bcma.c\n+++ b/drivers/net/ethernet/broadcom/bgmac-bcma.c\n@@ -11,6 +11,7 @@\n #include <linux/bcma/bcma.h>\n #include <linux/brcmphy.h>\n #include <linux/etherdevice.h>\n+#include <linux/of_mdio.h>\n #include <linux/of_net.h>\n #include \"bgmac.h\"\n \n@@ -86,17 +87,28 @@ static int bcma_phy_connect(struct bgmac\n \tstruct phy_device *phy_dev;\n \tchar bus_id[MII_BUS_ID_SIZE + 3];\n \n+\t/* DT info should be the most accurate */\n+\tphy_dev = of_phy_get_and_connect(bgmac->net_dev, bgmac->dev->of_node,\n+\t\t\t\t\t bgmac_adjust_link);\n+\tif (phy_dev)\n+\t\treturn 0;\n+\n \t/* Connect to the PHY */\n-\tsnprintf(bus_id, sizeof(bus_id), PHY_ID_FMT, bgmac->mii_bus->id,\n-\t\t bgmac->phyaddr);\n-\tphy_dev = phy_connect(bgmac->net_dev, bus_id, bgmac_adjust_link,\n-\t\t\t      PHY_INTERFACE_MODE_MII);\n-\tif (IS_ERR(phy_dev)) {\n-\t\tdev_err(bgmac->dev, \"PHY connection failed\\n\");\n-\t\treturn PTR_ERR(phy_dev);\n+\tif (bgmac->mii_bus && bgmac->phyaddr != BGMAC_PHY_NOREGS) {\n+\t\tsnprintf(bus_id, sizeof(bus_id), PHY_ID_FMT, bgmac->mii_bus->id,\n+\t\t\t bgmac->phyaddr);\n+\t\tphy_dev = phy_connect(bgmac->net_dev, bus_id, bgmac_adjust_link,\n+\t\t\t\t      PHY_INTERFACE_MODE_MII);\n+\t\tif (IS_ERR(phy_dev)) {\n+\t\t\tdev_err(bgmac->dev, \"PHY connection failed\\n\");\n+\t\t\treturn PTR_ERR(phy_dev);\n+\t\t}\n+\n+\t\treturn 0;\n \t}\n \n-\treturn 0;\n+\t/* Assume a fixed link to the switch port */\n+\treturn bgmac_phy_connect_direct(bgmac);\n }\n \n static const struct bcma_device_id bgmac_bcma_tbl[] = {\n@@ -297,10 +309,7 @@ static int bgmac_probe(struct bcma_devic\n \tbgmac->cco_ctl_maskset = bcma_bgmac_cco_ctl_maskset;\n \tbgmac->get_bus_clock = bcma_bgmac_get_bus_clock;\n \tbgmac->cmn_maskset32 = bcma_bgmac_cmn_maskset32;\n-\tif (bgmac->mii_bus)\n-\t\tbgmac->phy_connect = bcma_phy_connect;\n-\telse\n-\t\tbgmac->phy_connect = bgmac_phy_connect_direct;\n+\tbgmac->phy_connect = bcma_phy_connect;\n \n \terr = bgmac_enet_probe(bgmac);\n \tif (err)\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/734-v5.16-0002-net-bgmac-support-MDIO-described-in-DT.patch",
    "content": "From 45c9d966688e7fad7f24bfc450547d91e4304d0b Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Sat, 2 Oct 2021 19:58:12 +0200\nSubject: [PATCH] net: bgmac: support MDIO described in DT\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nCheck ethernet controller DT node for \"mdio\" subnode and use it with\nof_mdiobus_register() when present. That allows specifying MDIO and its\nPHY devices in a standard DT based way.\n\nThis is required for BCM53573 SoC support. That family is sometimes\ncalled Northstar (by marketing?) but is quite different from it. It uses\ndifferent CPU(s) and many different hw blocks.\n\nOne of shared blocks in BCM53573 is Ethernet controller. Switch however\nis not SRAB accessible (as it Northstar) but is MDIO attached.\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/ethernet/broadcom/bgmac-bcma-mdio.c | 6 +++++-\n 1 file changed, 5 insertions(+), 1 deletion(-)\n\n--- a/drivers/net/ethernet/broadcom/bgmac-bcma-mdio.c\n+++ b/drivers/net/ethernet/broadcom/bgmac-bcma-mdio.c\n@@ -10,6 +10,7 @@\n \n #include <linux/bcma/bcma.h>\n #include <linux/brcmphy.h>\n+#include <linux/of_mdio.h>\n #include \"bgmac.h\"\n \n static bool bcma_mdio_wait_value(struct bcma_device *core, u16 reg, u32 mask,\n@@ -211,6 +212,7 @@ struct mii_bus *bcma_mdio_mii_register(s\n {\n \tstruct bcma_device *core = bgmac->bcma.core;\n \tstruct mii_bus *mii_bus;\n+\tstruct device_node *np;\n \tint err;\n \n \tmii_bus = mdiobus_alloc();\n@@ -229,7 +231,9 @@ struct mii_bus *bcma_mdio_mii_register(s\n \tmii_bus->parent = &core->dev;\n \tmii_bus->phy_mask = ~(1 << bgmac->phyaddr);\n \n-\terr = mdiobus_register(mii_bus);\n+\tnp = of_get_child_by_name(core->dev.of_node, \"mdio\");\n+\n+\terr = of_mdiobus_register(mii_bus, np);\n \tif (err) {\n \t\tdev_err(&core->dev, \"Registration of mii bus failed\\n\");\n \t\tgoto err_free_bus;\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/735-v5.14-01-net-dsa-qca8k-change-simple-print-to-dev-variant.patch",
    "content": "From 5d9e068402dcf7354cc8ee66c2152845306d2ccb Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Fri, 14 May 2021 22:59:51 +0200\nSubject: [PATCH] net: dsa: qca8k: change simple print to dev variant\n\nChange pr_err and pr_warn to dev variant.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nReviewed-by: Florian Fainelli <f.fainelli@gmail.com>\nReviewed-by: Andrew Lunn <andrew@lunn.ch>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/dsa/qca8k.c | 4 ++--\n 1 file changed, 2 insertions(+), 2 deletions(-)\n\n--- a/drivers/net/dsa/qca8k.c\n+++ b/drivers/net/dsa/qca8k.c\n@@ -701,7 +701,7 @@ qca8k_setup(struct dsa_switch *ds)\n \n \t/* Make sure that port 0 is the cpu port */\n \tif (!dsa_is_cpu_port(ds, 0)) {\n-\t\tpr_err(\"port 0 is not the CPU port\\n\");\n+\t\tdev_err(priv->dev, \"port 0 is not the CPU port\");\n \t\treturn -EINVAL;\n \t}\n \n@@ -711,7 +711,7 @@ qca8k_setup(struct dsa_switch *ds)\n \tpriv->regmap = devm_regmap_init(ds->dev, NULL, priv,\n \t\t\t\t\t&qca8k_regmap_config);\n \tif (IS_ERR(priv->regmap))\n-\t\tpr_warn(\"regmap initialization failed\");\n+\t\tdev_warn(priv->dev, \"regmap initialization failed\");\n \n \tret = qca8k_setup_mdio_bus(priv);\n \tif (ret)\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/735-v5.14-02-net-dsa-qca8k-use-iopoll-macro-for-qca8k_busy_wait.patch",
    "content": "From 2ad255f2faaffb3af786031fba2e7955454b558a Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Fri, 14 May 2021 22:59:52 +0200\nSubject: [PATCH] net: dsa: qca8k: use iopoll macro for qca8k_busy_wait\n\nUse iopoll macro instead of while loop.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nReviewed-by: Andrew Lunn <andrew@lunn.ch>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/dsa/qca8k.c | 23 +++++++++++------------\n drivers/net/dsa/qca8k.h |  2 ++\n 2 files changed, 13 insertions(+), 12 deletions(-)\n\n--- a/drivers/net/dsa/qca8k.c\n+++ b/drivers/net/dsa/qca8k.c\n@@ -262,21 +262,20 @@ static struct regmap_config qca8k_regmap\n static int\n qca8k_busy_wait(struct qca8k_priv *priv, u32 reg, u32 mask)\n {\n-\tunsigned long timeout;\n+\tu32 val;\n+\tint ret;\n \n-\ttimeout = jiffies + msecs_to_jiffies(20);\n+\tret = read_poll_timeout(qca8k_read, val, !(val & mask),\n+\t\t\t\t0, QCA8K_BUSY_WAIT_TIMEOUT * USEC_PER_MSEC, false,\n+\t\t\t\tpriv, reg);\n \n-\t/* loop until the busy flag has cleared */\n-\tdo {\n-\t\tu32 val = qca8k_read(priv, reg);\n-\t\tint busy = val & mask;\n+\t/* Check if qca8k_read has failed for a different reason\n+\t * before returning -ETIMEDOUT\n+\t */\n+\tif (ret < 0 && val < 0)\n+\t\treturn val;\n \n-\t\tif (!busy)\n-\t\t\tbreak;\n-\t\tcond_resched();\n-\t} while (!time_after_eq(jiffies, timeout));\n-\n-\treturn time_after_eq(jiffies, timeout);\n+\treturn ret;\n }\n \n static void\n--- a/drivers/net/dsa/qca8k.h\n+++ b/drivers/net/dsa/qca8k.h\n@@ -18,6 +18,8 @@\n #define PHY_ID_QCA8337\t\t\t\t\t0x004dd036\n #define QCA8K_ID_QCA8337\t\t\t\t0x13\n \n+#define QCA8K_BUSY_WAIT_TIMEOUT\t\t\t\t20\n+\n #define QCA8K_NUM_FDB_RECORDS\t\t\t\t2048\n \n #define QCA8K_CPU_PORT\t\t\t\t\t0\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/735-v5.14-03-net-dsa-qca8k-improve-qca8k-read-write-rmw-bus-acces.patch",
    "content": "From 504bf65931824eda83494e5b5d75686e27ace03e Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Fri, 14 May 2021 22:59:53 +0200\nSubject: [PATCH] net: dsa: qca8k: improve qca8k read/write/rmw bus access\n\nPut bus in local variable to improve faster access to the mdio bus.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nReviewed-by: Andrew Lunn <andrew@lunn.ch>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/dsa/qca8k.c | 29 ++++++++++++++++-------------\n 1 file changed, 16 insertions(+), 13 deletions(-)\n\n--- a/drivers/net/dsa/qca8k.c\n+++ b/drivers/net/dsa/qca8k.c\n@@ -142,17 +142,18 @@ qca8k_set_page(struct mii_bus *bus, u16\n static u32\n qca8k_read(struct qca8k_priv *priv, u32 reg)\n {\n+\tstruct mii_bus *bus = priv->bus;\n \tu16 r1, r2, page;\n \tu32 val;\n \n \tqca8k_split_addr(reg, &r1, &r2, &page);\n \n-\tmutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED);\n+\tmutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);\n \n-\tqca8k_set_page(priv->bus, page);\n-\tval = qca8k_mii_read32(priv->bus, 0x10 | r2, r1);\n+\tqca8k_set_page(bus, page);\n+\tval = qca8k_mii_read32(bus, 0x10 | r2, r1);\n \n-\tmutex_unlock(&priv->bus->mdio_lock);\n+\tmutex_unlock(&bus->mdio_lock);\n \n \treturn val;\n }\n@@ -160,35 +161,37 @@ qca8k_read(struct qca8k_priv *priv, u32\n static void\n qca8k_write(struct qca8k_priv *priv, u32 reg, u32 val)\n {\n+\tstruct mii_bus *bus = priv->bus;\n \tu16 r1, r2, page;\n \n \tqca8k_split_addr(reg, &r1, &r2, &page);\n \n-\tmutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED);\n+\tmutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);\n \n-\tqca8k_set_page(priv->bus, page);\n-\tqca8k_mii_write32(priv->bus, 0x10 | r2, r1, val);\n+\tqca8k_set_page(bus, page);\n+\tqca8k_mii_write32(bus, 0x10 | r2, r1, val);\n \n-\tmutex_unlock(&priv->bus->mdio_lock);\n+\tmutex_unlock(&bus->mdio_lock);\n }\n \n static u32\n qca8k_rmw(struct qca8k_priv *priv, u32 reg, u32 mask, u32 val)\n {\n+\tstruct mii_bus *bus = priv->bus;\n \tu16 r1, r2, page;\n \tu32 ret;\n \n \tqca8k_split_addr(reg, &r1, &r2, &page);\n \n-\tmutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED);\n+\tmutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);\n \n-\tqca8k_set_page(priv->bus, page);\n-\tret = qca8k_mii_read32(priv->bus, 0x10 | r2, r1);\n+\tqca8k_set_page(bus, page);\n+\tret = qca8k_mii_read32(bus, 0x10 | r2, r1);\n \tret &= ~mask;\n \tret |= val;\n-\tqca8k_mii_write32(priv->bus, 0x10 | r2, r1, ret);\n+\tqca8k_mii_write32(bus, 0x10 | r2, r1, ret);\n \n-\tmutex_unlock(&priv->bus->mdio_lock);\n+\tmutex_unlock(&bus->mdio_lock);\n \n \treturn ret;\n }\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/735-v5.14-04-net-dsa-qca8k-handle-qca8k_set_page-errors.patch",
    "content": "From ba5707ec58cfb6853dff41c2aae72deb6a03d389 Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Fri, 14 May 2021 22:59:54 +0200\nSubject: [PATCH] net: dsa: qca8k: handle qca8k_set_page errors\n\nWith a remote possibility, the set_page function can fail. Since this is\na critical part of the write/read qca8k regs, propagate the error and\nterminate any read/write operation.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nReviewed-by: Andrew Lunn <andrew@lunn.ch>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/dsa/qca8k.c | 33 ++++++++++++++++++++++++++-------\n 1 file changed, 26 insertions(+), 7 deletions(-)\n\n--- a/drivers/net/dsa/qca8k.c\n+++ b/drivers/net/dsa/qca8k.c\n@@ -127,16 +127,23 @@ qca8k_mii_write32(struct mii_bus *bus, i\n \t\t\t\t    \"failed to write qca8k 32bit register\\n\");\n }\n \n-static void\n+static int\n qca8k_set_page(struct mii_bus *bus, u16 page)\n {\n+\tint ret;\n+\n \tif (page == qca8k_current_page)\n-\t\treturn;\n+\t\treturn 0;\n \n-\tif (bus->write(bus, 0x18, 0, page) < 0)\n+\tret = bus->write(bus, 0x18, 0, page);\n+\tif (ret < 0) {\n \t\tdev_err_ratelimited(&bus->dev,\n \t\t\t\t    \"failed to set qca8k page\\n\");\n+\t\treturn ret;\n+\t}\n+\n \tqca8k_current_page = page;\n+\treturn 0;\n }\n \n static u32\n@@ -150,11 +157,14 @@ qca8k_read(struct qca8k_priv *priv, u32\n \n \tmutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);\n \n-\tqca8k_set_page(bus, page);\n+\tval = qca8k_set_page(bus, page);\n+\tif (val < 0)\n+\t\tgoto exit;\n+\n \tval = qca8k_mii_read32(bus, 0x10 | r2, r1);\n \n+exit:\n \tmutex_unlock(&bus->mdio_lock);\n-\n \treturn val;\n }\n \n@@ -163,14 +173,19 @@ qca8k_write(struct qca8k_priv *priv, u32\n {\n \tstruct mii_bus *bus = priv->bus;\n \tu16 r1, r2, page;\n+\tint ret;\n \n \tqca8k_split_addr(reg, &r1, &r2, &page);\n \n \tmutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);\n \n-\tqca8k_set_page(bus, page);\n+\tret = qca8k_set_page(bus, page);\n+\tif (ret < 0)\n+\t\tgoto exit;\n+\n \tqca8k_mii_write32(bus, 0x10 | r2, r1, val);\n \n+exit:\n \tmutex_unlock(&bus->mdio_lock);\n }\n \n@@ -185,12 +200,16 @@ qca8k_rmw(struct qca8k_priv *priv, u32 r\n \n \tmutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);\n \n-\tqca8k_set_page(bus, page);\n+\tret = qca8k_set_page(bus, page);\n+\tif (ret < 0)\n+\t\tgoto exit;\n+\n \tret = qca8k_mii_read32(bus, 0x10 | r2, r1);\n \tret &= ~mask;\n \tret |= val;\n \tqca8k_mii_write32(bus, 0x10 | r2, r1, ret);\n \n+exit:\n \tmutex_unlock(&bus->mdio_lock);\n \n \treturn ret;\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/735-v5.14-05-net-dsa-qca8k-handle-error-with-qca8k_read-operation.patch",
    "content": "From 028f5f8ef44fcf87a456772cbb9f0d90a0a22884 Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Fri, 14 May 2021 22:59:55 +0200\nSubject: [PATCH] net: dsa: qca8k: handle error with qca8k_read operation\n\nqca8k_read can fail. Rework any user to handle error values and\ncorrectly return.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nReviewed-by: Andrew Lunn <andrew@lunn.ch>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/dsa/qca8k.c | 73 ++++++++++++++++++++++++++++++++---------\n 1 file changed, 58 insertions(+), 15 deletions(-)\n\n--- a/drivers/net/dsa/qca8k.c\n+++ b/drivers/net/dsa/qca8k.c\n@@ -231,8 +231,13 @@ static int\n qca8k_regmap_read(void *ctx, uint32_t reg, uint32_t *val)\n {\n \tstruct qca8k_priv *priv = (struct qca8k_priv *)ctx;\n+\tint ret;\n+\n+\tret = qca8k_read(priv, reg);\n+\tif (ret < 0)\n+\t\treturn ret;\n \n-\t*val = qca8k_read(priv, reg);\n+\t*val = ret;\n \n \treturn 0;\n }\n@@ -300,15 +305,20 @@ qca8k_busy_wait(struct qca8k_priv *priv,\n \treturn ret;\n }\n \n-static void\n+static int\n qca8k_fdb_read(struct qca8k_priv *priv, struct qca8k_fdb *fdb)\n {\n-\tu32 reg[4];\n+\tu32 reg[4], val;\n \tint i;\n \n \t/* load the ARL table into an array */\n-\tfor (i = 0; i < 4; i++)\n-\t\treg[i] = qca8k_read(priv, QCA8K_REG_ATU_DATA0 + (i * 4));\n+\tfor (i = 0; i < 4; i++) {\n+\t\tval = qca8k_read(priv, QCA8K_REG_ATU_DATA0 + (i * 4));\n+\t\tif (val < 0)\n+\t\t\treturn val;\n+\n+\t\treg[i] = val;\n+\t}\n \n \t/* vid - 83:72 */\n \tfdb->vid = (reg[2] >> QCA8K_ATU_VID_S) & QCA8K_ATU_VID_M;\n@@ -323,6 +333,8 @@ qca8k_fdb_read(struct qca8k_priv *priv,\n \tfdb->mac[3] = (reg[0] >> QCA8K_ATU_ADDR3_S) & 0xff;\n \tfdb->mac[4] = (reg[0] >> QCA8K_ATU_ADDR4_S) & 0xff;\n \tfdb->mac[5] = reg[0] & 0xff;\n+\n+\treturn 0;\n }\n \n static void\n@@ -374,6 +386,8 @@ qca8k_fdb_access(struct qca8k_priv *priv\n \t/* Check for table full violation when adding an entry */\n \tif (cmd == QCA8K_FDB_LOAD) {\n \t\treg = qca8k_read(priv, QCA8K_REG_ATU_FUNC);\n+\t\tif (reg < 0)\n+\t\t\treturn reg;\n \t\tif (reg & QCA8K_ATU_FUNC_FULL)\n \t\t\treturn -1;\n \t}\n@@ -388,10 +402,10 @@ qca8k_fdb_next(struct qca8k_priv *priv,\n \n \tqca8k_fdb_write(priv, fdb->vid, fdb->port_mask, fdb->mac, fdb->aging);\n \tret = qca8k_fdb_access(priv, QCA8K_FDB_NEXT, port);\n-\tif (ret >= 0)\n-\t\tqca8k_fdb_read(priv, fdb);\n+\tif (ret < 0)\n+\t\treturn ret;\n \n-\treturn ret;\n+\treturn qca8k_fdb_read(priv, fdb);\n }\n \n static int\n@@ -449,6 +463,8 @@ qca8k_vlan_access(struct qca8k_priv *pri\n \t/* Check for table full violation when adding an entry */\n \tif (cmd == QCA8K_VLAN_LOAD) {\n \t\treg = qca8k_read(priv, QCA8K_REG_VTU_FUNC1);\n+\t\tif (reg < 0)\n+\t\t\treturn reg;\n \t\tif (reg & QCA8K_VTU_FUNC1_FULL)\n \t\t\treturn -ENOMEM;\n \t}\n@@ -475,6 +491,8 @@ qca8k_vlan_add(struct qca8k_priv *priv,\n \t\tgoto out;\n \n \treg = qca8k_read(priv, QCA8K_REG_VTU_FUNC0);\n+\tif (reg < 0)\n+\t\treturn reg;\n \treg |= QCA8K_VTU_FUNC0_VALID | QCA8K_VTU_FUNC0_IVL_EN;\n \treg &= ~(QCA8K_VTU_FUNC0_EG_MODE_MASK << QCA8K_VTU_FUNC0_EG_MODE_S(port));\n \tif (untagged)\n@@ -506,6 +524,8 @@ qca8k_vlan_del(struct qca8k_priv *priv,\n \t\tgoto out;\n \n \treg = qca8k_read(priv, QCA8K_REG_VTU_FUNC0);\n+\tif (reg < 0)\n+\t\treturn reg;\n \treg &= ~(3 << QCA8K_VTU_FUNC0_EG_MODE_S(port));\n \treg |= QCA8K_VTU_FUNC0_EG_MODE_NOT <<\n \t\t\tQCA8K_VTU_FUNC0_EG_MODE_S(port);\n@@ -621,8 +641,11 @@ qca8k_mdio_read(struct qca8k_priv *priv,\n \t\t\t    QCA8K_MDIO_MASTER_BUSY))\n \t\treturn -ETIMEDOUT;\n \n-\tval = (qca8k_read(priv, QCA8K_MDIO_MASTER_CTRL) &\n-\t\tQCA8K_MDIO_MASTER_DATA_MASK);\n+\tval = qca8k_read(priv, QCA8K_MDIO_MASTER_CTRL);\n+\tif (val < 0)\n+\t\treturn val;\n+\n+\tval &= QCA8K_MDIO_MASTER_DATA_MASK;\n \n \treturn val;\n }\n@@ -978,6 +1001,8 @@ qca8k_phylink_mac_link_state(struct dsa_\n \tu32 reg;\n \n \treg = qca8k_read(priv, QCA8K_REG_PORT_STATUS(port));\n+\tif (reg < 0)\n+\t\treturn reg;\n \n \tstate->link = !!(reg & QCA8K_PORT_STATUS_LINK_UP);\n \tstate->an_complete = state->link;\n@@ -1078,18 +1103,26 @@ qca8k_get_ethtool_stats(struct dsa_switc\n {\n \tstruct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;\n \tconst struct qca8k_mib_desc *mib;\n-\tu32 reg, i;\n+\tu32 reg, i, val;\n \tu64 hi;\n \n \tfor (i = 0; i < ARRAY_SIZE(ar8327_mib); i++) {\n \t\tmib = &ar8327_mib[i];\n \t\treg = QCA8K_PORT_MIB_COUNTER(port) + mib->offset;\n \n-\t\tdata[i] = qca8k_read(priv, reg);\n+\t\tval = qca8k_read(priv, reg);\n+\t\tif (val < 0)\n+\t\t\tcontinue;\n+\n \t\tif (mib->size == 2) {\n \t\t\thi = qca8k_read(priv, reg + 4);\n-\t\t\tdata[i] |= hi << 32;\n+\t\t\tif (hi < 0)\n+\t\t\t\tcontinue;\n \t\t}\n+\n+\t\tdata[i] = val;\n+\t\tif (mib->size == 2)\n+\t\t\tdata[i] |= hi << 32;\n \t}\n }\n \n@@ -1107,18 +1140,25 @@ qca8k_set_mac_eee(struct dsa_switch *ds,\n {\n \tstruct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;\n \tu32 lpi_en = QCA8K_REG_EEE_CTRL_LPI_EN(port);\n+\tint ret = 0;\n \tu32 reg;\n \n \tmutex_lock(&priv->reg_mutex);\n \treg = qca8k_read(priv, QCA8K_REG_EEE_CTRL);\n+\tif (reg < 0) {\n+\t\tret = reg;\n+\t\tgoto exit;\n+\t}\n+\n \tif (eee->eee_enabled)\n \t\treg |= lpi_en;\n \telse\n \t\treg &= ~lpi_en;\n \tqca8k_write(priv, QCA8K_REG_EEE_CTRL, reg);\n-\tmutex_unlock(&priv->reg_mutex);\n \n-\treturn 0;\n+exit:\n+\tmutex_unlock(&priv->reg_mutex);\n+\treturn ret;\n }\n \n static int\n@@ -1456,6 +1496,9 @@ qca8k_sw_probe(struct mdio_device *mdiod\n \n \t/* read the switches ID register */\n \tid = qca8k_read(priv, QCA8K_REG_MASK_CTRL);\n+\tif (id < 0)\n+\t\treturn id;\n+\n \tid >>= QCA8K_MASK_CTRL_ID_S;\n \tid &= QCA8K_MASK_CTRL_ID_M;\n \tif (id != QCA8K_ID_QCA8337)\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/735-v5.14-06-net-dsa-qca8k-handle-error-with-qca8k_write-operatio.patch",
    "content": "From d7805757c75c76e9518fc1023a29f0c4eed5b581 Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Fri, 14 May 2021 22:59:56 +0200\nSubject: [PATCH] net: dsa: qca8k: handle error with qca8k_write operation\n\nqca8k_write can fail. Rework any user to handle error values and\ncorrectly return.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nReviewed-by: Andrew Lunn <andrew@lunn.ch>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/dsa/qca8k.c | 102 ++++++++++++++++++++++++++--------------\n 1 file changed, 67 insertions(+), 35 deletions(-)\n\n--- a/drivers/net/dsa/qca8k.c\n+++ b/drivers/net/dsa/qca8k.c\n@@ -168,7 +168,7 @@ exit:\n \treturn val;\n }\n \n-static void\n+static int\n qca8k_write(struct qca8k_priv *priv, u32 reg, u32 val)\n {\n \tstruct mii_bus *bus = priv->bus;\n@@ -187,6 +187,7 @@ qca8k_write(struct qca8k_priv *priv, u32\n \n exit:\n \tmutex_unlock(&bus->mdio_lock);\n+\treturn ret;\n }\n \n static u32\n@@ -247,9 +248,7 @@ qca8k_regmap_write(void *ctx, uint32_t r\n {\n \tstruct qca8k_priv *priv = (struct qca8k_priv *)ctx;\n \n-\tqca8k_write(priv, reg, val);\n-\n-\treturn 0;\n+\treturn qca8k_write(priv, reg, val);\n }\n \n static const struct regmap_range qca8k_readable_ranges[] = {\n@@ -367,6 +366,7 @@ static int\n qca8k_fdb_access(struct qca8k_priv *priv, enum qca8k_fdb_cmd cmd, int port)\n {\n \tu32 reg;\n+\tint ret;\n \n \t/* Set the command and FDB index */\n \treg = QCA8K_ATU_FUNC_BUSY;\n@@ -377,7 +377,9 @@ qca8k_fdb_access(struct qca8k_priv *priv\n \t}\n \n \t/* Write the function register triggering the table access */\n-\tqca8k_write(priv, QCA8K_REG_ATU_FUNC, reg);\n+\tret = qca8k_write(priv, QCA8K_REG_ATU_FUNC, reg);\n+\tif (ret)\n+\t\treturn ret;\n \n \t/* wait for completion */\n \tif (qca8k_busy_wait(priv, QCA8K_REG_ATU_FUNC, QCA8K_ATU_FUNC_BUSY))\n@@ -447,6 +449,7 @@ static int\n qca8k_vlan_access(struct qca8k_priv *priv, enum qca8k_vlan_cmd cmd, u16 vid)\n {\n \tu32 reg;\n+\tint ret;\n \n \t/* Set the command and VLAN index */\n \treg = QCA8K_VTU_FUNC1_BUSY;\n@@ -454,7 +457,9 @@ qca8k_vlan_access(struct qca8k_priv *pri\n \treg |= vid << QCA8K_VTU_FUNC1_VID_S;\n \n \t/* Write the function register triggering the table access */\n-\tqca8k_write(priv, QCA8K_REG_VTU_FUNC1, reg);\n+\tret = qca8k_write(priv, QCA8K_REG_VTU_FUNC1, reg);\n+\tif (ret)\n+\t\treturn ret;\n \n \t/* wait for completion */\n \tif (qca8k_busy_wait(priv, QCA8K_REG_VTU_FUNC1, QCA8K_VTU_FUNC1_BUSY))\n@@ -502,7 +507,9 @@ qca8k_vlan_add(struct qca8k_priv *priv,\n \t\treg |= QCA8K_VTU_FUNC0_EG_MODE_TAG <<\n \t\t\t\tQCA8K_VTU_FUNC0_EG_MODE_S(port);\n \n-\tqca8k_write(priv, QCA8K_REG_VTU_FUNC0, reg);\n+\tret = qca8k_write(priv, QCA8K_REG_VTU_FUNC0, reg);\n+\tif (ret)\n+\t\treturn ret;\n \tret = qca8k_vlan_access(priv, QCA8K_VLAN_LOAD, vid);\n \n out:\n@@ -545,7 +552,9 @@ qca8k_vlan_del(struct qca8k_priv *priv,\n \tif (del) {\n \t\tret = qca8k_vlan_access(priv, QCA8K_VLAN_PURGE, vid);\n \t} else {\n-\t\tqca8k_write(priv, QCA8K_REG_VTU_FUNC0, reg);\n+\t\tret = qca8k_write(priv, QCA8K_REG_VTU_FUNC0, reg);\n+\t\tif (ret)\n+\t\t\treturn ret;\n \t\tret = qca8k_vlan_access(priv, QCA8K_VLAN_LOAD, vid);\n \t}\n \n@@ -555,15 +564,20 @@ out:\n \treturn ret;\n }\n \n-static void\n+static int\n qca8k_mib_init(struct qca8k_priv *priv)\n {\n+\tint ret;\n+\n \tmutex_lock(&priv->reg_mutex);\n \tqca8k_reg_set(priv, QCA8K_REG_MIB, QCA8K_MIB_FLUSH | QCA8K_MIB_BUSY);\n \tqca8k_busy_wait(priv, QCA8K_REG_MIB, QCA8K_MIB_BUSY);\n \tqca8k_reg_set(priv, QCA8K_REG_MIB, QCA8K_MIB_CPU_KEEP);\n-\tqca8k_write(priv, QCA8K_REG_MODULE_EN, QCA8K_MODULE_EN_MIB);\n+\n+\tret = qca8k_write(priv, QCA8K_REG_MODULE_EN, QCA8K_MODULE_EN_MIB);\n+\n \tmutex_unlock(&priv->reg_mutex);\n+\treturn ret;\n }\n \n static void\n@@ -600,6 +614,7 @@ static int\n qca8k_mdio_write(struct qca8k_priv *priv, int port, u32 regnum, u16 data)\n {\n \tu32 phy, val;\n+\tint ret;\n \n \tif (regnum >= QCA8K_MDIO_MASTER_MAX_REG)\n \t\treturn -EINVAL;\n@@ -613,7 +628,9 @@ qca8k_mdio_write(struct qca8k_priv *priv\n \t      QCA8K_MDIO_MASTER_REG_ADDR(regnum) |\n \t      QCA8K_MDIO_MASTER_DATA(data);\n \n-\tqca8k_write(priv, QCA8K_MDIO_MASTER_CTRL, val);\n+\tret = qca8k_write(priv, QCA8K_MDIO_MASTER_CTRL, val);\n+\tif (ret)\n+\t\treturn ret;\n \n \treturn qca8k_busy_wait(priv, QCA8K_MDIO_MASTER_CTRL,\n \t\tQCA8K_MDIO_MASTER_BUSY);\n@@ -623,6 +640,7 @@ static int\n qca8k_mdio_read(struct qca8k_priv *priv, int port, u32 regnum)\n {\n \tu32 phy, val;\n+\tint ret;\n \n \tif (regnum >= QCA8K_MDIO_MASTER_MAX_REG)\n \t\treturn -EINVAL;\n@@ -635,7 +653,9 @@ qca8k_mdio_read(struct qca8k_priv *priv,\n \t      QCA8K_MDIO_MASTER_READ | QCA8K_MDIO_MASTER_PHY_ADDR(phy) |\n \t      QCA8K_MDIO_MASTER_REG_ADDR(regnum);\n \n-\tqca8k_write(priv, QCA8K_MDIO_MASTER_CTRL, val);\n+\tret = qca8k_write(priv, QCA8K_MDIO_MASTER_CTRL, val);\n+\tif (ret)\n+\t\treturn ret;\n \n \tif (qca8k_busy_wait(priv, QCA8K_MDIO_MASTER_CTRL,\n \t\t\t    QCA8K_MDIO_MASTER_BUSY))\n@@ -766,12 +786,18 @@ qca8k_setup(struct dsa_switch *ds)\n \t\t      QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN);\n \n \t/* Enable MIB counters */\n-\tqca8k_mib_init(priv);\n+\tret = qca8k_mib_init(priv);\n+\tif (ret)\n+\t\tdev_warn(priv->dev, \"mib init failed\");\n \n \t/* Enable QCA header mode on the cpu port */\n-\tqca8k_write(priv, QCA8K_REG_PORT_HDR_CTRL(QCA8K_CPU_PORT),\n-\t\t    QCA8K_PORT_HDR_CTRL_ALL << QCA8K_PORT_HDR_CTRL_TX_S |\n-\t\t    QCA8K_PORT_HDR_CTRL_ALL << QCA8K_PORT_HDR_CTRL_RX_S);\n+\tret = qca8k_write(priv, QCA8K_REG_PORT_HDR_CTRL(QCA8K_CPU_PORT),\n+\t\t\t  QCA8K_PORT_HDR_CTRL_ALL << QCA8K_PORT_HDR_CTRL_TX_S |\n+\t\t\t  QCA8K_PORT_HDR_CTRL_ALL << QCA8K_PORT_HDR_CTRL_RX_S);\n+\tif (ret) {\n+\t\tdev_err(priv->dev, \"failed enabling QCA header mode\");\n+\t\treturn ret;\n+\t}\n \n \t/* Disable forwarding by default on all ports */\n \tfor (i = 0; i < QCA8K_NUM_PORTS; i++)\n@@ -783,11 +809,13 @@ qca8k_setup(struct dsa_switch *ds)\n \t\tqca8k_port_set_status(priv, i, 0);\n \n \t/* Forward all unknown frames to CPU port for Linux processing */\n-\tqca8k_write(priv, QCA8K_REG_GLOBAL_FW_CTRL1,\n-\t\t    BIT(0) << QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_S |\n-\t\t    BIT(0) << QCA8K_GLOBAL_FW_CTRL1_BC_DP_S |\n-\t\t    BIT(0) << QCA8K_GLOBAL_FW_CTRL1_MC_DP_S |\n-\t\t    BIT(0) << QCA8K_GLOBAL_FW_CTRL1_UC_DP_S);\n+\tret = qca8k_write(priv, QCA8K_REG_GLOBAL_FW_CTRL1,\n+\t\t\t  BIT(0) << QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_S |\n+\t\t\t  BIT(0) << QCA8K_GLOBAL_FW_CTRL1_BC_DP_S |\n+\t\t\t  BIT(0) << QCA8K_GLOBAL_FW_CTRL1_MC_DP_S |\n+\t\t\t  BIT(0) << QCA8K_GLOBAL_FW_CTRL1_UC_DP_S);\n+\tif (ret)\n+\t\treturn ret;\n \n \t/* Setup connection between CPU port & user ports */\n \tfor (i = 0; i < QCA8K_NUM_PORTS; i++) {\n@@ -815,16 +843,20 @@ qca8k_setup(struct dsa_switch *ds)\n \t\t\tqca8k_rmw(priv, QCA8K_EGRESS_VLAN(i),\n \t\t\t\t  0xfff << shift,\n \t\t\t\t  QCA8K_PORT_VID_DEF << shift);\n-\t\t\tqca8k_write(priv, QCA8K_REG_PORT_VLAN_CTRL0(i),\n-\t\t\t\t    QCA8K_PORT_VLAN_CVID(QCA8K_PORT_VID_DEF) |\n-\t\t\t\t    QCA8K_PORT_VLAN_SVID(QCA8K_PORT_VID_DEF));\n+\t\t\tret = qca8k_write(priv, QCA8K_REG_PORT_VLAN_CTRL0(i),\n+\t\t\t\t\t  QCA8K_PORT_VLAN_CVID(QCA8K_PORT_VID_DEF) |\n+\t\t\t\t\t  QCA8K_PORT_VLAN_SVID(QCA8K_PORT_VID_DEF));\n+\t\t\tif (ret)\n+\t\t\t\treturn ret;\n \t\t}\n \t}\n \n \t/* Setup our port MTUs to match power on defaults */\n \tfor (i = 0; i < QCA8K_NUM_PORTS; i++)\n \t\tpriv->port_mtu[i] = ETH_FRAME_LEN + ETH_FCS_LEN;\n-\tqca8k_write(priv, QCA8K_MAX_FRAME_SIZE, ETH_FRAME_LEN + ETH_FCS_LEN);\n+\tret = qca8k_write(priv, QCA8K_MAX_FRAME_SIZE, ETH_FRAME_LEN + ETH_FCS_LEN);\n+\tif (ret)\n+\t\tdev_warn(priv->dev, \"failed setting MTU settings\");\n \n \t/* Flush the FDB table */\n \tqca8k_fdb_flush(priv);\n@@ -1140,8 +1172,8 @@ qca8k_set_mac_eee(struct dsa_switch *ds,\n {\n \tstruct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;\n \tu32 lpi_en = QCA8K_REG_EEE_CTRL_LPI_EN(port);\n-\tint ret = 0;\n \tu32 reg;\n+\tint ret;\n \n \tmutex_lock(&priv->reg_mutex);\n \treg = qca8k_read(priv, QCA8K_REG_EEE_CTRL);\n@@ -1154,7 +1186,7 @@ qca8k_set_mac_eee(struct dsa_switch *ds,\n \t\treg |= lpi_en;\n \telse\n \t\treg &= ~lpi_en;\n-\tqca8k_write(priv, QCA8K_REG_EEE_CTRL, reg);\n+\tret = qca8k_write(priv, QCA8K_REG_EEE_CTRL, reg);\n \n exit:\n \tmutex_unlock(&priv->reg_mutex);\n@@ -1284,9 +1316,7 @@ qca8k_port_change_mtu(struct dsa_switch\n \t\t\tmtu = priv->port_mtu[i];\n \n \t/* Include L2 header / FCS length */\n-\tqca8k_write(priv, QCA8K_MAX_FRAME_SIZE, mtu + ETH_HLEN + ETH_FCS_LEN);\n-\n-\treturn 0;\n+\treturn qca8k_write(priv, QCA8K_MAX_FRAME_SIZE, mtu + ETH_HLEN + ETH_FCS_LEN);\n }\n \n static int\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/735-v5.14-07-net-dsa-qca8k-handle-error-with-qca8k_rmw-operation.patch",
    "content": "From aaf421425cbdec4eb6fd75a29e65c2867b0b7bbd Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Fri, 14 May 2021 22:59:57 +0200\nSubject: [PATCH] net: dsa: qca8k: handle error with qca8k_rmw operation\n\nqca8k_rmw can fail. Rework any user to handle error values and\ncorrectly return. Change qca8k_rmw to return the error code or 0 instead\nof the reg value. The reg returned by qca8k_rmw wasn't used anywhere,\nso this doesn't cause any functional change.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nReviewed-by: Andrew Lunn <andrew@lunn.ch>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/dsa/qca8k.c | 133 +++++++++++++++++++++++++---------------\n 1 file changed, 83 insertions(+), 50 deletions(-)\n\n--- a/drivers/net/dsa/qca8k.c\n+++ b/drivers/net/dsa/qca8k.c\n@@ -190,12 +190,13 @@ exit:\n \treturn ret;\n }\n \n-static u32\n-qca8k_rmw(struct qca8k_priv *priv, u32 reg, u32 mask, u32 val)\n+static int\n+qca8k_rmw(struct qca8k_priv *priv, u32 reg, u32 mask, u32 write_val)\n {\n \tstruct mii_bus *bus = priv->bus;\n \tu16 r1, r2, page;\n-\tu32 ret;\n+\tu32 val;\n+\tint ret;\n \n \tqca8k_split_addr(reg, &r1, &r2, &page);\n \n@@ -205,10 +206,15 @@ qca8k_rmw(struct qca8k_priv *priv, u32 r\n \tif (ret < 0)\n \t\tgoto exit;\n \n-\tret = qca8k_mii_read32(bus, 0x10 | r2, r1);\n-\tret &= ~mask;\n-\tret |= val;\n-\tqca8k_mii_write32(bus, 0x10 | r2, r1, ret);\n+\tval = qca8k_mii_read32(bus, 0x10 | r2, r1);\n+\tif (val < 0) {\n+\t\tret = val;\n+\t\tgoto exit;\n+\t}\n+\n+\tval &= ~mask;\n+\tval |= write_val;\n+\tqca8k_mii_write32(bus, 0x10 | r2, r1, val);\n \n exit:\n \tmutex_unlock(&bus->mdio_lock);\n@@ -216,16 +222,16 @@ exit:\n \treturn ret;\n }\n \n-static void\n+static int\n qca8k_reg_set(struct qca8k_priv *priv, u32 reg, u32 val)\n {\n-\tqca8k_rmw(priv, reg, 0, val);\n+\treturn qca8k_rmw(priv, reg, 0, val);\n }\n \n-static void\n+static int\n qca8k_reg_clear(struct qca8k_priv *priv, u32 reg, u32 val)\n {\n-\tqca8k_rmw(priv, reg, val, 0);\n+\treturn qca8k_rmw(priv, reg, val, 0);\n }\n \n static int\n@@ -570,12 +576,19 @@ qca8k_mib_init(struct qca8k_priv *priv)\n \tint ret;\n \n \tmutex_lock(&priv->reg_mutex);\n-\tqca8k_reg_set(priv, QCA8K_REG_MIB, QCA8K_MIB_FLUSH | QCA8K_MIB_BUSY);\n+\tret = qca8k_reg_set(priv, QCA8K_REG_MIB, QCA8K_MIB_FLUSH | QCA8K_MIB_BUSY);\n+\tif (ret)\n+\t\tgoto exit;\n+\n \tqca8k_busy_wait(priv, QCA8K_REG_MIB, QCA8K_MIB_BUSY);\n-\tqca8k_reg_set(priv, QCA8K_REG_MIB, QCA8K_MIB_CPU_KEEP);\n+\n+\tret = qca8k_reg_set(priv, QCA8K_REG_MIB, QCA8K_MIB_CPU_KEEP);\n+\tif (ret)\n+\t\tgoto exit;\n \n \tret = qca8k_write(priv, QCA8K_REG_MODULE_EN, QCA8K_MODULE_EN_MIB);\n \n+exit:\n \tmutex_unlock(&priv->reg_mutex);\n \treturn ret;\n }\n@@ -747,9 +760,8 @@ qca8k_setup_mdio_bus(struct qca8k_priv *\n \t\t * a dt-overlay and driver reload changed the configuration\n \t\t */\n \n-\t\tqca8k_reg_clear(priv, QCA8K_MDIO_MASTER_CTRL,\n-\t\t\t\tQCA8K_MDIO_MASTER_EN);\n-\t\treturn 0;\n+\t\treturn qca8k_reg_clear(priv, QCA8K_MDIO_MASTER_CTRL,\n+\t\t\t\t       QCA8K_MDIO_MASTER_EN);\n \t}\n \n \tpriv->ops.phy_read = qca8k_phy_read;\n@@ -782,8 +794,12 @@ qca8k_setup(struct dsa_switch *ds)\n \t\treturn ret;\n \n \t/* Enable CPU Port */\n-\tqca8k_reg_set(priv, QCA8K_REG_GLOBAL_FW_CTRL0,\n-\t\t      QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN);\n+\tret = qca8k_reg_set(priv, QCA8K_REG_GLOBAL_FW_CTRL0,\n+\t\t\t    QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN);\n+\tif (ret) {\n+\t\tdev_err(priv->dev, \"failed enabling CPU port\");\n+\t\treturn ret;\n+\t}\n \n \t/* Enable MIB counters */\n \tret = qca8k_mib_init(priv);\n@@ -800,9 +816,12 @@ qca8k_setup(struct dsa_switch *ds)\n \t}\n \n \t/* Disable forwarding by default on all ports */\n-\tfor (i = 0; i < QCA8K_NUM_PORTS; i++)\n-\t\tqca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i),\n-\t\t\t  QCA8K_PORT_LOOKUP_MEMBER, 0);\n+\tfor (i = 0; i < QCA8K_NUM_PORTS; i++) {\n+\t\tret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i),\n+\t\t\t\tQCA8K_PORT_LOOKUP_MEMBER, 0);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\t}\n \n \t/* Disable MAC by default on all ports */\n \tfor (i = 1; i < QCA8K_NUM_PORTS; i++)\n@@ -821,28 +840,37 @@ qca8k_setup(struct dsa_switch *ds)\n \tfor (i = 0; i < QCA8K_NUM_PORTS; i++) {\n \t\t/* CPU port gets connected to all user ports of the switch */\n \t\tif (dsa_is_cpu_port(ds, i)) {\n-\t\t\tqca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(QCA8K_CPU_PORT),\n-\t\t\t\t  QCA8K_PORT_LOOKUP_MEMBER, dsa_user_ports(ds));\n+\t\t\tret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(QCA8K_CPU_PORT),\n+\t\t\t\t\tQCA8K_PORT_LOOKUP_MEMBER, dsa_user_ports(ds));\n+\t\t\tif (ret)\n+\t\t\t\treturn ret;\n \t\t}\n \n \t\t/* Individual user ports get connected to CPU port only */\n \t\tif (dsa_is_user_port(ds, i)) {\n \t\t\tint shift = 16 * (i % 2);\n \n-\t\t\tqca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i),\n-\t\t\t\t  QCA8K_PORT_LOOKUP_MEMBER,\n-\t\t\t\t  BIT(QCA8K_CPU_PORT));\n+\t\t\tret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i),\n+\t\t\t\t\tQCA8K_PORT_LOOKUP_MEMBER,\n+\t\t\t\t\tBIT(QCA8K_CPU_PORT));\n+\t\t\tif (ret)\n+\t\t\t\treturn ret;\n \n \t\t\t/* Enable ARP Auto-learning by default */\n-\t\t\tqca8k_reg_set(priv, QCA8K_PORT_LOOKUP_CTRL(i),\n-\t\t\t\t      QCA8K_PORT_LOOKUP_LEARN);\n+\t\t\tret = qca8k_reg_set(priv, QCA8K_PORT_LOOKUP_CTRL(i),\n+\t\t\t\t\t    QCA8K_PORT_LOOKUP_LEARN);\n+\t\t\tif (ret)\n+\t\t\t\treturn ret;\n \n \t\t\t/* For port based vlans to work we need to set the\n \t\t\t * default egress vid\n \t\t\t */\n-\t\t\tqca8k_rmw(priv, QCA8K_EGRESS_VLAN(i),\n-\t\t\t\t  0xfff << shift,\n-\t\t\t\t  QCA8K_PORT_VID_DEF << shift);\n+\t\t\tret = qca8k_rmw(priv, QCA8K_EGRESS_VLAN(i),\n+\t\t\t\t\t0xfff << shift,\n+\t\t\t\t\tQCA8K_PORT_VID_DEF << shift);\n+\t\t\tif (ret)\n+\t\t\t\treturn ret;\n+\n \t\t\tret = qca8k_write(priv, QCA8K_REG_PORT_VLAN_CTRL0(i),\n \t\t\t\t\t  QCA8K_PORT_VLAN_CVID(QCA8K_PORT_VID_DEF) |\n \t\t\t\t\t  QCA8K_PORT_VLAN_SVID(QCA8K_PORT_VID_DEF));\n@@ -1234,7 +1262,7 @@ qca8k_port_bridge_join(struct dsa_switch\n {\n \tstruct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;\n \tint port_mask = BIT(QCA8K_CPU_PORT);\n-\tint i;\n+\tint i, ret;\n \n \tfor (i = 1; i < QCA8K_NUM_PORTS; i++) {\n \t\tif (dsa_to_port(ds, i)->bridge_dev != br)\n@@ -1242,17 +1270,20 @@ qca8k_port_bridge_join(struct dsa_switch\n \t\t/* Add this port to the portvlan mask of the other ports\n \t\t * in the bridge\n \t\t */\n-\t\tqca8k_reg_set(priv,\n-\t\t\t      QCA8K_PORT_LOOKUP_CTRL(i),\n-\t\t\t      BIT(port));\n+\t\tret = qca8k_reg_set(priv,\n+\t\t\t\t    QCA8K_PORT_LOOKUP_CTRL(i),\n+\t\t\t\t    BIT(port));\n+\t\tif (ret)\n+\t\t\treturn ret;\n \t\tif (i != port)\n \t\t\tport_mask |= BIT(i);\n \t}\n+\n \t/* Add all other ports to this ports portvlan mask */\n-\tqca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),\n-\t\t  QCA8K_PORT_LOOKUP_MEMBER, port_mask);\n+\tret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),\n+\t\t\tQCA8K_PORT_LOOKUP_MEMBER, port_mask);\n \n-\treturn 0;\n+\treturn ret;\n }\n \n static void\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/735-v5.14-08-net-dsa-qca8k-handle-error-from-qca8k_busy_wait.patch",
    "content": "From b7c818d194927bdc60ed15db55bb8654496a36b7 Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Fri, 14 May 2021 22:59:58 +0200\nSubject: [PATCH] net: dsa: qca8k: handle error from qca8k_busy_wait\n\nPropagate errors from qca8k_busy_wait instead of hardcoding return\nvalue.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nReviewed-by: Andrew Lunn <andrew@lunn.ch>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/dsa/qca8k.c | 21 +++++++++++++--------\n 1 file changed, 13 insertions(+), 8 deletions(-)\n\n--- a/drivers/net/dsa/qca8k.c\n+++ b/drivers/net/dsa/qca8k.c\n@@ -388,8 +388,9 @@ qca8k_fdb_access(struct qca8k_priv *priv\n \t\treturn ret;\n \n \t/* wait for completion */\n-\tif (qca8k_busy_wait(priv, QCA8K_REG_ATU_FUNC, QCA8K_ATU_FUNC_BUSY))\n-\t\treturn -1;\n+\tret = qca8k_busy_wait(priv, QCA8K_REG_ATU_FUNC, QCA8K_ATU_FUNC_BUSY);\n+\tif (ret)\n+\t\treturn ret;\n \n \t/* Check for table full violation when adding an entry */\n \tif (cmd == QCA8K_FDB_LOAD) {\n@@ -468,8 +469,9 @@ qca8k_vlan_access(struct qca8k_priv *pri\n \t\treturn ret;\n \n \t/* wait for completion */\n-\tif (qca8k_busy_wait(priv, QCA8K_REG_VTU_FUNC1, QCA8K_VTU_FUNC1_BUSY))\n-\t\treturn -ETIMEDOUT;\n+\tret = qca8k_busy_wait(priv, QCA8K_REG_VTU_FUNC1, QCA8K_VTU_FUNC1_BUSY);\n+\tif (ret)\n+\t\treturn ret;\n \n \t/* Check for table full violation when adding an entry */\n \tif (cmd == QCA8K_VLAN_LOAD) {\n@@ -580,7 +582,9 @@ qca8k_mib_init(struct qca8k_priv *priv)\n \tif (ret)\n \t\tgoto exit;\n \n-\tqca8k_busy_wait(priv, QCA8K_REG_MIB, QCA8K_MIB_BUSY);\n+\tret = qca8k_busy_wait(priv, QCA8K_REG_MIB, QCA8K_MIB_BUSY);\n+\tif (ret)\n+\t\tgoto exit;\n \n \tret = qca8k_reg_set(priv, QCA8K_REG_MIB, QCA8K_MIB_CPU_KEEP);\n \tif (ret)\n@@ -670,9 +674,10 @@ qca8k_mdio_read(struct qca8k_priv *priv,\n \tif (ret)\n \t\treturn ret;\n \n-\tif (qca8k_busy_wait(priv, QCA8K_MDIO_MASTER_CTRL,\n-\t\t\t    QCA8K_MDIO_MASTER_BUSY))\n-\t\treturn -ETIMEDOUT;\n+\tret = qca8k_busy_wait(priv, QCA8K_MDIO_MASTER_CTRL,\n+\t\t\t      QCA8K_MDIO_MASTER_BUSY);\n+\tif (ret)\n+\t\treturn ret;\n \n \tval = qca8k_read(priv, QCA8K_MDIO_MASTER_CTRL);\n \tif (val < 0)\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/735-v5.14-09-net-dsa-qca8k-add-support-for-qca8327-switch.patch",
    "content": "From 6e82a457e06252b59102486767539cc9c2aba60b Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Fri, 14 May 2021 22:59:59 +0200\nSubject: [PATCH] net: dsa: qca8k: add support for qca8327 switch\n\nqca8327 switch is a low tier version of the more recent qca8337.\nIt does share the same regs used by the qca8k driver and can be\nsupported with minimal change.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nReviewed-by: Andrew Lunn <andrew@lunn.ch>\nReviewed-by: Vladimir Oltean <olteanv@gmail.com>\nReviewed-by: Florian Fainelli <f.fainelli@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/dsa/qca8k.c | 23 ++++++++++++++++++++---\n drivers/net/dsa/qca8k.h |  6 ++++++\n 2 files changed, 26 insertions(+), 3 deletions(-)\n\n--- a/drivers/net/dsa/qca8k.c\n+++ b/drivers/net/dsa/qca8k.c\n@@ -1533,6 +1533,7 @@ static const struct dsa_switch_ops qca8k\n static int\n qca8k_sw_probe(struct mdio_device *mdiodev)\n {\n+\tconst struct qca8k_match_data *data;\n \tstruct qca8k_priv *priv;\n \tu32 id;\n \n@@ -1560,6 +1561,11 @@ qca8k_sw_probe(struct mdio_device *mdiod\n \t\tgpiod_set_value_cansleep(priv->reset_gpio, 0);\n \t}\n \n+\t/* get the switches ID from the compatible */\n+\tdata = of_device_get_match_data(&mdiodev->dev);\n+\tif (!data)\n+\t\treturn -ENODEV;\n+\n \t/* read the switches ID register */\n \tid = qca8k_read(priv, QCA8K_REG_MASK_CTRL);\n \tif (id < 0)\n@@ -1567,8 +1573,10 @@ qca8k_sw_probe(struct mdio_device *mdiod\n \n \tid >>= QCA8K_MASK_CTRL_ID_S;\n \tid &= QCA8K_MASK_CTRL_ID_M;\n-\tif (id != QCA8K_ID_QCA8337)\n+\tif (id != data->id) {\n+\t\tdev_err(&mdiodev->dev, \"Switch id detected %x but expected %x\", id, data->id);\n \t\treturn -ENODEV;\n+\t}\n \n \tpriv->ds = devm_kzalloc(&mdiodev->dev, sizeof(*priv->ds), GFP_KERNEL);\n \tif (!priv->ds)\n@@ -1634,9 +1642,18 @@ static int qca8k_resume(struct device *d\n static SIMPLE_DEV_PM_OPS(qca8k_pm_ops,\n \t\t\t qca8k_suspend, qca8k_resume);\n \n+static const struct qca8k_match_data qca832x = {\n+\t.id = QCA8K_ID_QCA8327,\n+};\n+\n+static const struct qca8k_match_data qca833x = {\n+\t.id = QCA8K_ID_QCA8337,\n+};\n+\n static const struct of_device_id qca8k_of_match[] = {\n-\t{ .compatible = \"qca,qca8334\" },\n-\t{ .compatible = \"qca,qca8337\" },\n+\t{ .compatible = \"qca,qca8327\", .data = &qca832x },\n+\t{ .compatible = \"qca,qca8334\", .data = &qca833x },\n+\t{ .compatible = \"qca,qca8337\", .data = &qca833x },\n \t{ /* sentinel */ },\n };\n \n--- a/drivers/net/dsa/qca8k.h\n+++ b/drivers/net/dsa/qca8k.h\n@@ -15,6 +15,8 @@\n #define QCA8K_NUM_PORTS\t\t\t\t\t7\n #define QCA8K_MAX_MTU\t\t\t\t\t9000\n \n+#define PHY_ID_QCA8327\t\t\t\t\t0x004dd034\n+#define QCA8K_ID_QCA8327\t\t\t\t0x12\n #define PHY_ID_QCA8337\t\t\t\t\t0x004dd036\n #define QCA8K_ID_QCA8337\t\t\t\t0x13\n \n@@ -213,6 +215,10 @@ struct ar8xxx_port_status {\n \tint enabled;\n };\n \n+struct qca8k_match_data {\n+\tu8 id;\n+};\n+\n struct qca8k_priv {\n \tstruct regmap *regmap;\n \tstruct mii_bus *bus;\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/735-v5.14-10-devicetree-net-dsa-qca8k-Document-new-compatible-qca.patch",
    "content": "From 227a9ffc1bc77037339530607fe129af3824620e Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Fri, 14 May 2021 23:00:00 +0200\nSubject: [PATCH] devicetree: net: dsa: qca8k: Document new compatible qca8327\n\nAdd support for qca8327 in the compatible list.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nReviewed-by: Andrew Lunn <andrew@lunn.ch>\nAcked-by: Rob Herring <robh@kernel.org>\nReviewed-by: Florian Fainelli <f.fainelli@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n Documentation/devicetree/bindings/net/dsa/qca8k.txt | 1 +\n 1 file changed, 1 insertion(+)\n\n--- a/Documentation/devicetree/bindings/net/dsa/qca8k.txt\n+++ b/Documentation/devicetree/bindings/net/dsa/qca8k.txt\n@@ -3,6 +3,7 @@\n Required properties:\n \n - compatible: should be one of:\n+    \"qca,qca8327\"\n     \"qca,qca8334\"\n     \"qca,qca8337\"\n \n"
  },
  {
    "path": "target/linux/generic/backport-5.10/735-v5.14-11-net-dsa-qca8k-add-priority-tweak-to-qca8337-switch.patch",
    "content": "From 83a3ceb39b2495171aabe9446271b94c678354f3 Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Fri, 14 May 2021 23:00:01 +0200\nSubject: [PATCH] net: dsa: qca8k: add priority tweak to qca8337 switch\n\nThe port 5 of the qca8337 have some problem in flood condition. The\noriginal legacy driver had some specific buffer and priority settings\nfor the different port suggested by the QCA switch team. Add this\nmissing settings to improve switch stability under load condition.\nThe packet priority tweak is only needed for the qca8337 switch and\nother qca8k switch are not affected.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/dsa/qca8k.c | 47 +++++++++++++++++++++++++++++++++++++++++\n drivers/net/dsa/qca8k.h | 25 ++++++++++++++++++++++\n 2 files changed, 72 insertions(+)\n\n--- a/drivers/net/dsa/qca8k.c\n+++ b/drivers/net/dsa/qca8k.c\n@@ -779,6 +779,7 @@ qca8k_setup(struct dsa_switch *ds)\n {\n \tstruct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;\n \tint ret, i;\n+\tu32 mask;\n \n \t/* Make sure that port 0 is the cpu port */\n \tif (!dsa_is_cpu_port(ds, 0)) {\n@@ -884,6 +885,51 @@ qca8k_setup(struct dsa_switch *ds)\n \t\t}\n \t}\n \n+\t/* The port 5 of the qca8337 have some problem in flood condition. The\n+\t * original legacy driver had some specific buffer and priority settings\n+\t * for the different port suggested by the QCA switch team. Add this\n+\t * missing settings to improve switch stability under load condition.\n+\t * This problem is limited to qca8337 and other qca8k switch are not affected.\n+\t */\n+\tif (priv->switch_id == QCA8K_ID_QCA8337) {\n+\t\tfor (i = 0; i < QCA8K_NUM_PORTS; i++) {\n+\t\t\tswitch (i) {\n+\t\t\t/* The 2 CPU port and port 5 requires some different\n+\t\t\t * priority than any other ports.\n+\t\t\t */\n+\t\t\tcase 0:\n+\t\t\tcase 5:\n+\t\t\tcase 6:\n+\t\t\t\tmask = QCA8K_PORT_HOL_CTRL0_EG_PRI0(0x3) |\n+\t\t\t\t\tQCA8K_PORT_HOL_CTRL0_EG_PRI1(0x4) |\n+\t\t\t\t\tQCA8K_PORT_HOL_CTRL0_EG_PRI2(0x4) |\n+\t\t\t\t\tQCA8K_PORT_HOL_CTRL0_EG_PRI3(0x4) |\n+\t\t\t\t\tQCA8K_PORT_HOL_CTRL0_EG_PRI4(0x6) |\n+\t\t\t\t\tQCA8K_PORT_HOL_CTRL0_EG_PRI5(0x8) |\n+\t\t\t\t\tQCA8K_PORT_HOL_CTRL0_EG_PORT(0x1e);\n+\t\t\t\tbreak;\n+\t\t\tdefault:\n+\t\t\t\tmask = QCA8K_PORT_HOL_CTRL0_EG_PRI0(0x3) |\n+\t\t\t\t\tQCA8K_PORT_HOL_CTRL0_EG_PRI1(0x4) |\n+\t\t\t\t\tQCA8K_PORT_HOL_CTRL0_EG_PRI2(0x6) |\n+\t\t\t\t\tQCA8K_PORT_HOL_CTRL0_EG_PRI3(0x8) |\n+\t\t\t\t\tQCA8K_PORT_HOL_CTRL0_EG_PORT(0x19);\n+\t\t\t}\n+\t\t\tqca8k_write(priv, QCA8K_REG_PORT_HOL_CTRL0(i), mask);\n+\n+\t\t\tmask = QCA8K_PORT_HOL_CTRL1_ING(0x6) |\n+\t\t\tQCA8K_PORT_HOL_CTRL1_EG_PRI_BUF_EN |\n+\t\t\tQCA8K_PORT_HOL_CTRL1_EG_PORT_BUF_EN |\n+\t\t\tQCA8K_PORT_HOL_CTRL1_WRED_EN;\n+\t\t\tqca8k_rmw(priv, QCA8K_REG_PORT_HOL_CTRL1(i),\n+\t\t\t\t  QCA8K_PORT_HOL_CTRL1_ING_BUF |\n+\t\t\t\t  QCA8K_PORT_HOL_CTRL1_EG_PRI_BUF_EN |\n+\t\t\t\t  QCA8K_PORT_HOL_CTRL1_EG_PORT_BUF_EN |\n+\t\t\t\t  QCA8K_PORT_HOL_CTRL1_WRED_EN,\n+\t\t\t\t  mask);\n+\t\t}\n+\t}\n+\n \t/* Setup our port MTUs to match power on defaults */\n \tfor (i = 0; i < QCA8K_NUM_PORTS; i++)\n \t\tpriv->port_mtu[i] = ETH_FRAME_LEN + ETH_FCS_LEN;\n@@ -1578,6 +1624,7 @@ qca8k_sw_probe(struct mdio_device *mdiod\n \t\treturn -ENODEV;\n \t}\n \n+\tpriv->switch_id = id;\n \tpriv->ds = devm_kzalloc(&mdiodev->dev, sizeof(*priv->ds), GFP_KERNEL);\n \tif (!priv->ds)\n \t\treturn -ENOMEM;\n--- a/drivers/net/dsa/qca8k.h\n+++ b/drivers/net/dsa/qca8k.h\n@@ -168,6 +168,30 @@\n #define   QCA8K_PORT_LOOKUP_STATE\t\t\tGENMASK(18, 16)\n #define   QCA8K_PORT_LOOKUP_LEARN\t\t\tBIT(20)\n \n+#define QCA8K_REG_PORT_HOL_CTRL0(_i)\t\t\t(0x970 + (_i) * 0x8)\n+#define   QCA8K_PORT_HOL_CTRL0_EG_PRI0_BUF\t\tGENMASK(3, 0)\n+#define   QCA8K_PORT_HOL_CTRL0_EG_PRI0(x)\t\t((x) << 0)\n+#define   QCA8K_PORT_HOL_CTRL0_EG_PRI1_BUF\t\tGENMASK(7, 4)\n+#define   QCA8K_PORT_HOL_CTRL0_EG_PRI1(x)\t\t((x) << 4)\n+#define   QCA8K_PORT_HOL_CTRL0_EG_PRI2_BUF\t\tGENMASK(11, 8)\n+#define   QCA8K_PORT_HOL_CTRL0_EG_PRI2(x)\t\t((x) << 8)\n+#define   QCA8K_PORT_HOL_CTRL0_EG_PRI3_BUF\t\tGENMASK(15, 12)\n+#define   QCA8K_PORT_HOL_CTRL0_EG_PRI3(x)\t\t((x) << 12)\n+#define   QCA8K_PORT_HOL_CTRL0_EG_PRI4_BUF\t\tGENMASK(19, 16)\n+#define   QCA8K_PORT_HOL_CTRL0_EG_PRI4(x)\t\t((x) << 16)\n+#define   QCA8K_PORT_HOL_CTRL0_EG_PRI5_BUF\t\tGENMASK(23, 20)\n+#define   QCA8K_PORT_HOL_CTRL0_EG_PRI5(x)\t\t((x) << 20)\n+#define   QCA8K_PORT_HOL_CTRL0_EG_PORT_BUF\t\tGENMASK(29, 24)\n+#define   QCA8K_PORT_HOL_CTRL0_EG_PORT(x)\t\t((x) << 24)\n+\n+#define QCA8K_REG_PORT_HOL_CTRL1(_i)\t\t\t(0x974 + (_i) * 0x8)\n+#define   QCA8K_PORT_HOL_CTRL1_ING_BUF\t\t\tGENMASK(3, 0)\n+#define   QCA8K_PORT_HOL_CTRL1_ING(x)\t\t\t((x) << 0)\n+#define   QCA8K_PORT_HOL_CTRL1_EG_PRI_BUF_EN\t\tBIT(6)\n+#define   QCA8K_PORT_HOL_CTRL1_EG_PORT_BUF_EN\t\tBIT(7)\n+#define   QCA8K_PORT_HOL_CTRL1_WRED_EN\t\t\tBIT(8)\n+#define   QCA8K_PORT_HOL_CTRL1_EG_MIRROR_EN\t\tBIT(16)\n+\n /* Pkt edit registers */\n #define QCA8K_EGRESS_VLAN(x)\t\t\t\t(0x0c70 + (4 * (x / 2)))\n \n@@ -220,6 +244,7 @@ struct qca8k_match_data {\n };\n \n struct qca8k_priv {\n+\tu8 switch_id;\n \tstruct regmap *regmap;\n \tstruct mii_bus *bus;\n \tstruct ar8xxx_port_status port_sts[QCA8K_NUM_PORTS];\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/735-v5.14-12-net-dsa-qca8k-limit-port5-delay-to-qca8337.patch",
    "content": "From 5bf9ff3b9fb5ecb67a1a3517b26db3a00f2a2f11 Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Fri, 14 May 2021 23:00:02 +0200\nSubject: [PATCH] net: dsa: qca8k: limit port5 delay to qca8337\n\nLimit port5 rx delay to qca8337. This is taken from the legacy QSDK code\nthat limits the rx delay on port5 to only this particular switch version,\non other switch only the tx and rx delay for port0 are needed.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nReviewed-by: Andrew Lunn <andrew@lunn.ch>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/dsa/qca8k.c | 6 ++++--\n 1 file changed, 4 insertions(+), 2 deletions(-)\n\n--- a/drivers/net/dsa/qca8k.c\n+++ b/drivers/net/dsa/qca8k.c\n@@ -1003,8 +1003,10 @@ qca8k_phylink_mac_config(struct dsa_swit\n \t\t\t    QCA8K_PORT_PAD_RGMII_EN |\n \t\t\t    QCA8K_PORT_PAD_RGMII_TX_DELAY(QCA8K_MAX_DELAY) |\n \t\t\t    QCA8K_PORT_PAD_RGMII_RX_DELAY(QCA8K_MAX_DELAY));\n-\t\tqca8k_write(priv, QCA8K_REG_PORT5_PAD_CTRL,\n-\t\t\t    QCA8K_PORT_PAD_RGMII_RX_DELAY_EN);\n+\t\t/* QCA8337 requires to set rgmii rx delay */\n+\t\tif (priv->switch_id == QCA8K_ID_QCA8337)\n+\t\t\tqca8k_write(priv, QCA8K_REG_PORT5_PAD_CTRL,\n+\t\t\t\t    QCA8K_PORT_PAD_RGMII_RX_DELAY_EN);\n \t\tbreak;\n \tcase PHY_INTERFACE_MODE_SGMII:\n \tcase PHY_INTERFACE_MODE_1000BASEX:\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/735-v5.14-13-net-dsa-qca8k-add-GLOBAL_FC-settings-needed-for-qca8.patch",
    "content": "From 0fc57e4b5e39461fc0a54aae0afe4241363a7267 Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Fri, 14 May 2021 23:00:03 +0200\nSubject: [PATCH] net: dsa: qca8k: add GLOBAL_FC settings needed for qca8327\n\nSwitch qca8327 needs special settings for the GLOBAL_FC_THRES regs.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/dsa/qca8k.c | 10 ++++++++++\n drivers/net/dsa/qca8k.h |  6 ++++++\n 2 files changed, 16 insertions(+)\n\n--- a/drivers/net/dsa/qca8k.c\n+++ b/drivers/net/dsa/qca8k.c\n@@ -930,6 +930,16 @@ qca8k_setup(struct dsa_switch *ds)\n \t\t}\n \t}\n \n+\t/* Special GLOBAL_FC_THRESH value are needed for ar8327 switch */\n+\tif (priv->switch_id == QCA8K_ID_QCA8327) {\n+\t\tmask = QCA8K_GLOBAL_FC_GOL_XON_THRES(288) |\n+\t\t       QCA8K_GLOBAL_FC_GOL_XOFF_THRES(496);\n+\t\tqca8k_rmw(priv, QCA8K_REG_GLOBAL_FC_THRESH,\n+\t\t\t  QCA8K_GLOBAL_FC_GOL_XON_THRES_S |\n+\t\t\t  QCA8K_GLOBAL_FC_GOL_XOFF_THRES_S,\n+\t\t\t  mask);\n+\t}\n+\n \t/* Setup our port MTUs to match power on defaults */\n \tfor (i = 0; i < QCA8K_NUM_PORTS; i++)\n \t\tpriv->port_mtu[i] = ETH_FRAME_LEN + ETH_FCS_LEN;\n--- a/drivers/net/dsa/qca8k.h\n+++ b/drivers/net/dsa/qca8k.h\n@@ -168,6 +168,12 @@\n #define   QCA8K_PORT_LOOKUP_STATE\t\t\tGENMASK(18, 16)\n #define   QCA8K_PORT_LOOKUP_LEARN\t\t\tBIT(20)\n \n+#define QCA8K_REG_GLOBAL_FC_THRESH\t\t\t0x800\n+#define   QCA8K_GLOBAL_FC_GOL_XON_THRES(x)\t\t((x) << 16)\n+#define   QCA8K_GLOBAL_FC_GOL_XON_THRES_S\t\tGENMASK(24, 16)\n+#define   QCA8K_GLOBAL_FC_GOL_XOFF_THRES(x)\t\t((x) << 0)\n+#define   QCA8K_GLOBAL_FC_GOL_XOFF_THRES_S\t\tGENMASK(8, 0)\n+\n #define QCA8K_REG_PORT_HOL_CTRL0(_i)\t\t\t(0x970 + (_i) * 0x8)\n #define   QCA8K_PORT_HOL_CTRL0_EG_PRI0_BUF\t\tGENMASK(3, 0)\n #define   QCA8K_PORT_HOL_CTRL0_EG_PRI0(x)\t\t((x) << 0)\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/735-v5.14-14-net-dsa-qca8k-add-support-for-switch-rev.patch",
    "content": "From 95ffeaf18b3bb90eeef52cbf7d79ccc9d0345ff5 Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Fri, 14 May 2021 23:00:04 +0200\nSubject: [PATCH] net: dsa: qca8k: add support for switch rev\n\nqca8k internal phy driver require some special debug value to be set\nbased on the switch revision. Rework the switch id read function to\nalso read the chip revision.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nReviewed-by: Florian Fainelli <f.fainelli@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/dsa/qca8k.c | 53 ++++++++++++++++++++++++++---------------\n drivers/net/dsa/qca8k.h |  7 ++++--\n 2 files changed, 39 insertions(+), 21 deletions(-)\n\n--- a/drivers/net/dsa/qca8k.c\n+++ b/drivers/net/dsa/qca8k.c\n@@ -1588,12 +1588,40 @@ static const struct dsa_switch_ops qca8k\n \t.phylink_mac_link_up\t= qca8k_phylink_mac_link_up,\n };\n \n+static int qca8k_read_switch_id(struct qca8k_priv *priv)\n+{\n+\tconst struct qca8k_match_data *data;\n+\tu32 val;\n+\tu8 id;\n+\n+\t/* get the switches ID from the compatible */\n+\tdata = of_device_get_match_data(priv->dev);\n+\tif (!data)\n+\t\treturn -ENODEV;\n+\n+\tval = qca8k_read(priv, QCA8K_REG_MASK_CTRL);\n+\tif (val < 0)\n+\t\treturn -ENODEV;\n+\n+\tid = QCA8K_MASK_CTRL_DEVICE_ID(val & QCA8K_MASK_CTRL_DEVICE_ID_MASK);\n+\tif (id != data->id) {\n+\t\tdev_err(priv->dev, \"Switch id detected %x but expected %x\", id, data->id);\n+\t\treturn -ENODEV;\n+\t}\n+\n+\tpriv->switch_id = id;\n+\n+\t/* Save revision to communicate to the internal PHY driver */\n+\tpriv->switch_revision = (val & QCA8K_MASK_CTRL_REV_ID_MASK);\n+\n+\treturn 0;\n+}\n+\n static int\n qca8k_sw_probe(struct mdio_device *mdiodev)\n {\n-\tconst struct qca8k_match_data *data;\n \tstruct qca8k_priv *priv;\n-\tu32 id;\n+\tint ret;\n \n \t/* allocate the private data struct so that we can probe the switches\n \t * ID register\n@@ -1619,24 +1647,11 @@ qca8k_sw_probe(struct mdio_device *mdiod\n \t\tgpiod_set_value_cansleep(priv->reset_gpio, 0);\n \t}\n \n-\t/* get the switches ID from the compatible */\n-\tdata = of_device_get_match_data(&mdiodev->dev);\n-\tif (!data)\n-\t\treturn -ENODEV;\n+\t/* Check the detected switch id */\n+\tret = qca8k_read_switch_id(priv);\n+\tif (ret)\n+\t\treturn ret;\n \n-\t/* read the switches ID register */\n-\tid = qca8k_read(priv, QCA8K_REG_MASK_CTRL);\n-\tif (id < 0)\n-\t\treturn id;\n-\n-\tid >>= QCA8K_MASK_CTRL_ID_S;\n-\tid &= QCA8K_MASK_CTRL_ID_M;\n-\tif (id != data->id) {\n-\t\tdev_err(&mdiodev->dev, \"Switch id detected %x but expected %x\", id, data->id);\n-\t\treturn -ENODEV;\n-\t}\n-\n-\tpriv->switch_id = id;\n \tpriv->ds = devm_kzalloc(&mdiodev->dev, sizeof(*priv->ds), GFP_KERNEL);\n \tif (!priv->ds)\n \t\treturn -ENOMEM;\n--- a/drivers/net/dsa/qca8k.h\n+++ b/drivers/net/dsa/qca8k.h\n@@ -30,8 +30,10 @@\n \n /* Global control registers */\n #define QCA8K_REG_MASK_CTRL\t\t\t\t0x000\n-#define   QCA8K_MASK_CTRL_ID_M\t\t\t\t0xff\n-#define   QCA8K_MASK_CTRL_ID_S\t\t\t\t8\n+#define   QCA8K_MASK_CTRL_REV_ID_MASK\t\t\tGENMASK(7, 0)\n+#define   QCA8K_MASK_CTRL_REV_ID(x)\t\t\t((x) >> 0)\n+#define   QCA8K_MASK_CTRL_DEVICE_ID_MASK\t\tGENMASK(15, 8)\n+#define   QCA8K_MASK_CTRL_DEVICE_ID(x)\t\t\t((x) >> 8)\n #define QCA8K_REG_PORT0_PAD_CTRL\t\t\t0x004\n #define QCA8K_REG_PORT5_PAD_CTRL\t\t\t0x008\n #define QCA8K_REG_PORT6_PAD_CTRL\t\t\t0x00c\n@@ -251,6 +253,7 @@ struct qca8k_match_data {\n \n struct qca8k_priv {\n \tu8 switch_id;\n+\tu8 switch_revision;\n \tstruct regmap *regmap;\n \tstruct mii_bus *bus;\n \tstruct ar8xxx_port_status port_sts[QCA8K_NUM_PORTS];\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/735-v5.14-15-net-dsa-qca8k-add-ethernet-ports-fallback-to-setup_m.patch",
    "content": "From 1ee0591a1093c2448642c33433483e9260275f7b Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Fri, 14 May 2021 23:00:05 +0200\nSubject: [PATCH] net: dsa: qca8k: add ethernet-ports fallback to\n setup_mdio_bus\n\nDsa now also supports ethernet-ports. Add this new binding as a fallback\nif the ports node can't be found.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nReviewed-by: Andrew Lunn <andrew@lunn.ch>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/dsa/qca8k.c | 3 +++\n 1 file changed, 3 insertions(+)\n\n--- a/drivers/net/dsa/qca8k.c\n+++ b/drivers/net/dsa/qca8k.c\n@@ -719,6 +719,9 @@ qca8k_setup_mdio_bus(struct qca8k_priv *\n \n \tports = of_get_child_by_name(priv->dev->of_node, \"ports\");\n \tif (!ports)\n+\t\tports = of_get_child_by_name(priv->dev->of_node, \"ethernet-ports\");\n+\n+\tif (!ports)\n \t\treturn -EINVAL;\n \n \tfor_each_available_child_of_node(ports, port) {\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/735-v5.14-16-net-dsa-qca8k-make-rgmii-delay-configurable.patch",
    "content": "From e4b9977cee1583da38a6e9118078bb728aaccf7b Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Fri, 14 May 2021 23:00:06 +0200\nSubject: [PATCH] net: dsa: qca8k: make rgmii delay configurable\n\nThe legacy qsdk code used a different delay instead of the max value.\nQsdk use 1 ns for rx and 2 ns for tx. Make these values configurable\nusing the standard rx/tx-internal-delay-ps ethernet binding and apply\nqsdk values by default. The connected gmac doesn't add any delay so no\nadditional delay is added to tx/rx.\nOn this switch the delay is actually in ns so value should be in the\n1000 order. Any value converted from ps to ns by dividing it by 1000\nas the switch max value for delay is 3ns.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/dsa/qca8k.c | 82 ++++++++++++++++++++++++++++++++++++++++-\n drivers/net/dsa/qca8k.h | 11 +++---\n 2 files changed, 86 insertions(+), 7 deletions(-)\n\n--- a/drivers/net/dsa/qca8k.c\n+++ b/drivers/net/dsa/qca8k.c\n@@ -778,6 +778,68 @@ qca8k_setup_mdio_bus(struct qca8k_priv *\n }\n \n static int\n+qca8k_setup_of_rgmii_delay(struct qca8k_priv *priv)\n+{\n+\tstruct device_node *port_dn;\n+\tphy_interface_t mode;\n+\tstruct dsa_port *dp;\n+\tu32 val;\n+\n+\t/* CPU port is already checked */\n+\tdp = dsa_to_port(priv->ds, 0);\n+\n+\tport_dn = dp->dn;\n+\n+\t/* Check if port 0 is set to the correct type */\n+\tof_get_phy_mode(port_dn, &mode);\n+\tif (mode != PHY_INTERFACE_MODE_RGMII_ID &&\n+\t    mode != PHY_INTERFACE_MODE_RGMII_RXID &&\n+\t    mode != PHY_INTERFACE_MODE_RGMII_TXID) {\n+\t\treturn 0;\n+\t}\n+\n+\tswitch (mode) {\n+\tcase PHY_INTERFACE_MODE_RGMII_ID:\n+\tcase PHY_INTERFACE_MODE_RGMII_RXID:\n+\t\tif (of_property_read_u32(port_dn, \"rx-internal-delay-ps\", &val))\n+\t\t\tval = 2;\n+\t\telse\n+\t\t\t/* Switch regs accept value in ns, convert ps to ns */\n+\t\t\tval = val / 1000;\n+\n+\t\tif (val > QCA8K_MAX_DELAY) {\n+\t\t\tdev_err(priv->dev, \"rgmii rx delay is limited to a max value of 3ns, setting to the max value\");\n+\t\t\tval = 3;\n+\t\t}\n+\n+\t\tpriv->rgmii_rx_delay = val;\n+\t\t/* Stop here if we need to check only for rx delay */\n+\t\tif (mode != PHY_INTERFACE_MODE_RGMII_ID)\n+\t\t\tbreak;\n+\n+\t\tfallthrough;\n+\tcase PHY_INTERFACE_MODE_RGMII_TXID:\n+\t\tif (of_property_read_u32(port_dn, \"tx-internal-delay-ps\", &val))\n+\t\t\tval = 1;\n+\t\telse\n+\t\t\t/* Switch regs accept value in ns, convert ps to ns */\n+\t\t\tval = val / 1000;\n+\n+\t\tif (val > QCA8K_MAX_DELAY) {\n+\t\t\tdev_err(priv->dev, \"rgmii tx delay is limited to a max value of 3ns, setting to the max value\");\n+\t\t\tval = 3;\n+\t\t}\n+\n+\t\tpriv->rgmii_tx_delay = val;\n+\t\tbreak;\n+\tdefault:\n+\t\treturn 0;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int\n qca8k_setup(struct dsa_switch *ds)\n {\n \tstruct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;\n@@ -802,6 +864,10 @@ qca8k_setup(struct dsa_switch *ds)\n \tif (ret)\n \t\treturn ret;\n \n+\tret = qca8k_setup_of_rgmii_delay(priv);\n+\tif (ret)\n+\t\treturn ret;\n+\n \t/* Enable CPU Port */\n \tret = qca8k_reg_set(priv, QCA8K_REG_GLOBAL_FW_CTRL0,\n \t\t\t    QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN);\n@@ -970,6 +1036,8 @@ qca8k_phylink_mac_config(struct dsa_swit\n \tcase 0: /* 1st CPU port */\n \t\tif (state->interface != PHY_INTERFACE_MODE_RGMII &&\n \t\t    state->interface != PHY_INTERFACE_MODE_RGMII_ID &&\n+\t\t    state->interface != PHY_INTERFACE_MODE_RGMII_TXID &&\n+\t\t    state->interface != PHY_INTERFACE_MODE_RGMII_RXID &&\n \t\t    state->interface != PHY_INTERFACE_MODE_SGMII)\n \t\t\treturn;\n \n@@ -985,6 +1053,8 @@ qca8k_phylink_mac_config(struct dsa_swit\n \tcase 6: /* 2nd CPU port / external PHY */\n \t\tif (state->interface != PHY_INTERFACE_MODE_RGMII &&\n \t\t    state->interface != PHY_INTERFACE_MODE_RGMII_ID &&\n+\t\t    state->interface != PHY_INTERFACE_MODE_RGMII_TXID &&\n+\t\t    state->interface != PHY_INTERFACE_MODE_RGMII_RXID &&\n \t\t    state->interface != PHY_INTERFACE_MODE_SGMII &&\n \t\t    state->interface != PHY_INTERFACE_MODE_1000BASEX)\n \t\t\treturn;\n@@ -1008,14 +1078,18 @@ qca8k_phylink_mac_config(struct dsa_swit\n \t\tqca8k_write(priv, reg, QCA8K_PORT_PAD_RGMII_EN);\n \t\tbreak;\n \tcase PHY_INTERFACE_MODE_RGMII_ID:\n+\tcase PHY_INTERFACE_MODE_RGMII_TXID:\n+\tcase PHY_INTERFACE_MODE_RGMII_RXID:\n \t\t/* RGMII_ID needs internal delay. This is enabled through\n \t\t * PORT5_PAD_CTRL for all ports, rather than individual port\n \t\t * registers\n \t\t */\n \t\tqca8k_write(priv, reg,\n \t\t\t    QCA8K_PORT_PAD_RGMII_EN |\n-\t\t\t    QCA8K_PORT_PAD_RGMII_TX_DELAY(QCA8K_MAX_DELAY) |\n-\t\t\t    QCA8K_PORT_PAD_RGMII_RX_DELAY(QCA8K_MAX_DELAY));\n+\t\t\t    QCA8K_PORT_PAD_RGMII_TX_DELAY(priv->rgmii_tx_delay) |\n+\t\t\t    QCA8K_PORT_PAD_RGMII_RX_DELAY(priv->rgmii_rx_delay) |\n+\t\t\t    QCA8K_PORT_PAD_RGMII_TX_DELAY_EN |\n+\t\t\t    QCA8K_PORT_PAD_RGMII_RX_DELAY_EN);\n \t\t/* QCA8337 requires to set rgmii rx delay */\n \t\tif (priv->switch_id == QCA8K_ID_QCA8337)\n \t\t\tqca8k_write(priv, QCA8K_REG_PORT5_PAD_CTRL,\n@@ -1073,6 +1147,8 @@ qca8k_phylink_validate(struct dsa_switch\n \t\tif (state->interface != PHY_INTERFACE_MODE_NA &&\n \t\t    state->interface != PHY_INTERFACE_MODE_RGMII &&\n \t\t    state->interface != PHY_INTERFACE_MODE_RGMII_ID &&\n+\t\t    state->interface != PHY_INTERFACE_MODE_RGMII_TXID &&\n+\t\t    state->interface != PHY_INTERFACE_MODE_RGMII_RXID &&\n \t\t    state->interface != PHY_INTERFACE_MODE_SGMII)\n \t\t\tgoto unsupported;\n \t\tbreak;\n@@ -1090,6 +1166,8 @@ qca8k_phylink_validate(struct dsa_switch\n \t\tif (state->interface != PHY_INTERFACE_MODE_NA &&\n \t\t    state->interface != PHY_INTERFACE_MODE_RGMII &&\n \t\t    state->interface != PHY_INTERFACE_MODE_RGMII_ID &&\n+\t\t    state->interface != PHY_INTERFACE_MODE_RGMII_TXID &&\n+\t\t    state->interface != PHY_INTERFACE_MODE_RGMII_RXID &&\n \t\t    state->interface != PHY_INTERFACE_MODE_SGMII &&\n \t\t    state->interface != PHY_INTERFACE_MODE_1000BASEX)\n \t\t\tgoto unsupported;\n--- a/drivers/net/dsa/qca8k.h\n+++ b/drivers/net/dsa/qca8k.h\n@@ -38,12 +38,11 @@\n #define QCA8K_REG_PORT5_PAD_CTRL\t\t\t0x008\n #define QCA8K_REG_PORT6_PAD_CTRL\t\t\t0x00c\n #define   QCA8K_PORT_PAD_RGMII_EN\t\t\tBIT(26)\n-#define   QCA8K_PORT_PAD_RGMII_TX_DELAY(x)\t\t\\\n-\t\t\t\t\t\t((0x8 + (x & 0x3)) << 22)\n-#define   QCA8K_PORT_PAD_RGMII_RX_DELAY(x)\t\t\\\n-\t\t\t\t\t\t((0x10 + (x & 0x3)) << 20)\n-#define   QCA8K_MAX_DELAY\t\t\t\t3\n+#define   QCA8K_PORT_PAD_RGMII_TX_DELAY(x)\t\t((x) << 22)\n+#define   QCA8K_PORT_PAD_RGMII_RX_DELAY(x)\t\t((x) << 20)\n+#define\t  QCA8K_PORT_PAD_RGMII_TX_DELAY_EN\t\tBIT(25)\n #define   QCA8K_PORT_PAD_RGMII_RX_DELAY_EN\t\tBIT(24)\n+#define   QCA8K_MAX_DELAY\t\t\t\t3\n #define   QCA8K_PORT_PAD_SGMII_EN\t\t\tBIT(7)\n #define QCA8K_REG_PWS\t\t\t\t\t0x010\n #define   QCA8K_PWS_SERDES_AEN_DIS\t\t\tBIT(7)\n@@ -254,6 +253,8 @@ struct qca8k_match_data {\n struct qca8k_priv {\n \tu8 switch_id;\n \tu8 switch_revision;\n+\tu8 rgmii_tx_delay;\n+\tu8 rgmii_rx_delay;\n \tstruct regmap *regmap;\n \tstruct mii_bus *bus;\n \tstruct ar8xxx_port_status port_sts[QCA8K_NUM_PORTS];\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/735-v5.14-17-net-dsa-qca8k-clear-MASTER_EN-after-phy-read-write.patch",
    "content": "From 63c33bbfeb6842a956a0eb12901e28eb335bdb18 Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Fri, 14 May 2021 23:00:07 +0200\nSubject: [PATCH] net: dsa: qca8k: clear MASTER_EN after phy read/write\n\nClear MDIO_MASTER_EN bit from MDIO_MASTER_CTRL after read/write\noperation. The MDIO_MASTER_EN bit is not reset after read/write\noperation and the next operation can be wrongly interpreted by the\nswitch as a mdio operation. This cause a production of wrong/garbage\ndata from the switch and underfined bheavior. (random port drop,\nunplugged port flagged with link up, wrong port speed)\nAlso on driver remove the MASTER_CTRL can be left set and cause the\nmalfunction of any next driver using the mdio device.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/dsa/qca8k.c | 14 ++++++++++++--\n 1 file changed, 12 insertions(+), 2 deletions(-)\n\n--- a/drivers/net/dsa/qca8k.c\n+++ b/drivers/net/dsa/qca8k.c\n@@ -649,8 +649,14 @@ qca8k_mdio_write(struct qca8k_priv *priv\n \tif (ret)\n \t\treturn ret;\n \n-\treturn qca8k_busy_wait(priv, QCA8K_MDIO_MASTER_CTRL,\n-\t\tQCA8K_MDIO_MASTER_BUSY);\n+\tret = qca8k_busy_wait(priv, QCA8K_MDIO_MASTER_CTRL,\n+\t\t\t      QCA8K_MDIO_MASTER_BUSY);\n+\n+\t/* even if the busy_wait timeouts try to clear the MASTER_EN */\n+\tqca8k_reg_clear(priv, QCA8K_MDIO_MASTER_CTRL,\n+\t\t\tQCA8K_MDIO_MASTER_EN);\n+\n+\treturn ret;\n }\n \n static int\n@@ -685,6 +691,10 @@ qca8k_mdio_read(struct qca8k_priv *priv,\n \n \tval &= QCA8K_MDIO_MASTER_DATA_MASK;\n \n+\t/* even if the busy_wait timeouts try to clear the MASTER_EN */\n+\tqca8k_reg_clear(priv, QCA8K_MDIO_MASTER_CTRL,\n+\t\t\tQCA8K_MDIO_MASTER_EN);\n+\n \treturn val;\n }\n \n"
  },
  {
    "path": "target/linux/generic/backport-5.10/735-v5.14-18-net-dsa-qca8k-dsa-qca8k-protect-MASTER-busy_wait-wit.patch",
    "content": "From 60df02b6ea4581d72eb7a3ab7204504a54059b72 Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Fri, 14 May 2021 23:00:08 +0200\nSubject: [PATCH] net: dsa: qca8k: dsa: qca8k: protect MASTER busy_wait with\n mdio mutex\n\nMDIO_MASTER operation have a dedicated busy wait that is not protected\nby the mdio mutex. This can cause situation where the MASTER operation\nis done and a normal operation is executed between the MASTER read/write\nand the MASTER busy_wait. Rework the qca8k_mdio_read/write function to\naddress this issue by binding the lock for the whole MASTER operation\nand not only the mdio read/write common operation.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nReviewed-by: Andrew Lunn <andrew@lunn.ch>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/dsa/qca8k.c | 68 +++++++++++++++++++++++++++++++++--------\n 1 file changed, 55 insertions(+), 13 deletions(-)\n\n--- a/drivers/net/dsa/qca8k.c\n+++ b/drivers/net/dsa/qca8k.c\n@@ -628,8 +628,31 @@ qca8k_port_to_phy(int port)\n }\n \n static int\n+qca8k_mdio_busy_wait(struct qca8k_priv *priv, u32 reg, u32 mask)\n+{\n+\tu16 r1, r2, page;\n+\tu32 val;\n+\tint ret;\n+\n+\tqca8k_split_addr(reg, &r1, &r2, &page);\n+\n+\tret = read_poll_timeout(qca8k_mii_read32, val, !(val & mask), 0,\n+\t\t\t\tQCA8K_BUSY_WAIT_TIMEOUT * USEC_PER_MSEC, false,\n+\t\t\t\tpriv->bus, 0x10 | r2, r1);\n+\n+\t/* Check if qca8k_read has failed for a different reason\n+\t * before returnting -ETIMEDOUT\n+\t */\n+\tif (ret < 0 && val < 0)\n+\t\treturn val;\n+\n+\treturn ret;\n+}\n+\n+static int\n qca8k_mdio_write(struct qca8k_priv *priv, int port, u32 regnum, u16 data)\n {\n+\tu16 r1, r2, page;\n \tu32 phy, val;\n \tint ret;\n \n@@ -645,12 +668,21 @@ qca8k_mdio_write(struct qca8k_priv *priv\n \t      QCA8K_MDIO_MASTER_REG_ADDR(regnum) |\n \t      QCA8K_MDIO_MASTER_DATA(data);\n \n-\tret = qca8k_write(priv, QCA8K_MDIO_MASTER_CTRL, val);\n+\tqca8k_split_addr(QCA8K_MDIO_MASTER_CTRL, &r1, &r2, &page);\n+\n+\tmutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED);\n+\n+\tret = qca8k_set_page(priv->bus, page);\n \tif (ret)\n-\t\treturn ret;\n+\t\tgoto exit;\n+\n+\tqca8k_mii_write32(priv->bus, 0x10 | r2, r1, val);\n \n-\tret = qca8k_busy_wait(priv, QCA8K_MDIO_MASTER_CTRL,\n-\t\t\t      QCA8K_MDIO_MASTER_BUSY);\n+\tret = qca8k_mdio_busy_wait(priv, QCA8K_MDIO_MASTER_CTRL,\n+\t\t\t\t   QCA8K_MDIO_MASTER_BUSY);\n+\n+exit:\n+\tmutex_unlock(&priv->bus->mdio_lock);\n \n \t/* even if the busy_wait timeouts try to clear the MASTER_EN */\n \tqca8k_reg_clear(priv, QCA8K_MDIO_MASTER_CTRL,\n@@ -662,6 +694,7 @@ qca8k_mdio_write(struct qca8k_priv *priv\n static int\n qca8k_mdio_read(struct qca8k_priv *priv, int port, u32 regnum)\n {\n+\tu16 r1, r2, page;\n \tu32 phy, val;\n \tint ret;\n \n@@ -676,21 +709,30 @@ qca8k_mdio_read(struct qca8k_priv *priv,\n \t      QCA8K_MDIO_MASTER_READ | QCA8K_MDIO_MASTER_PHY_ADDR(phy) |\n \t      QCA8K_MDIO_MASTER_REG_ADDR(regnum);\n \n-\tret = qca8k_write(priv, QCA8K_MDIO_MASTER_CTRL, val);\n-\tif (ret)\n-\t\treturn ret;\n+\tqca8k_split_addr(QCA8K_MDIO_MASTER_CTRL, &r1, &r2, &page);\n+\n+\tmutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED);\n \n-\tret = qca8k_busy_wait(priv, QCA8K_MDIO_MASTER_CTRL,\n-\t\t\t      QCA8K_MDIO_MASTER_BUSY);\n+\tret = qca8k_set_page(priv->bus, page);\n \tif (ret)\n-\t\treturn ret;\n+\t\tgoto exit;\n \n-\tval = qca8k_read(priv, QCA8K_MDIO_MASTER_CTRL);\n-\tif (val < 0)\n-\t\treturn val;\n+\tqca8k_mii_write32(priv->bus, 0x10 | r2, r1, val);\n+\n+\tret = qca8k_mdio_busy_wait(priv, QCA8K_MDIO_MASTER_CTRL,\n+\t\t\t\t   QCA8K_MDIO_MASTER_BUSY);\n+\tif (ret)\n+\t\tgoto exit;\n \n+\tval = qca8k_mii_read32(priv->bus, 0x10 | r2, r1);\n \tval &= QCA8K_MDIO_MASTER_DATA_MASK;\n \n+exit:\n+\tmutex_unlock(&priv->bus->mdio_lock);\n+\n+\tif (val >= 0)\n+\t\tval &= QCA8K_MDIO_MASTER_DATA_MASK;\n+\n \t/* even if the busy_wait timeouts try to clear the MASTER_EN */\n \tqca8k_reg_clear(priv, QCA8K_MDIO_MASTER_CTRL,\n \t\t\tQCA8K_MDIO_MASTER_EN);\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/735-v5.14-19-net-dsa-qca8k-enlarge-mdio-delay-and-timeout.patch",
    "content": "From 617960d72e93de0f3fa52407e2d39e8c43e73b0a Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Fri, 14 May 2021 23:00:09 +0200\nSubject: [PATCH] net: dsa: qca8k: enlarge mdio delay and timeout\n\nThe witch require some extra delay after setting page or the next\nread/write can use still use the old page. Add a delay after the\nset_page function to address this as it's done in QSDK legacy driver.\nSome timeouts were notice with VLAN and phy function, enlarge the\nmdio busy wait timeout to fix these problems.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/dsa/qca8k.c | 1 +\n drivers/net/dsa/qca8k.h | 2 +-\n 2 files changed, 2 insertions(+), 1 deletion(-)\n\n--- a/drivers/net/dsa/qca8k.c\n+++ b/drivers/net/dsa/qca8k.c\n@@ -143,6 +143,7 @@ qca8k_set_page(struct mii_bus *bus, u16\n \t}\n \n \tqca8k_current_page = page;\n+\tusleep_range(1000, 2000);\n \treturn 0;\n }\n \n--- a/drivers/net/dsa/qca8k.h\n+++ b/drivers/net/dsa/qca8k.h\n@@ -20,7 +20,7 @@\n #define PHY_ID_QCA8337\t\t\t\t\t0x004dd036\n #define QCA8K_ID_QCA8337\t\t\t\t0x13\n \n-#define QCA8K_BUSY_WAIT_TIMEOUT\t\t\t\t20\n+#define QCA8K_BUSY_WAIT_TIMEOUT\t\t\t\t2000\n \n #define QCA8K_NUM_FDB_RECORDS\t\t\t\t2048\n \n"
  },
  {
    "path": "target/linux/generic/backport-5.10/735-v5.14-20-net-dsa-qca8k-add-support-for-internal-phy-and-inter.patch",
    "content": "From 759bafb8a3226326ca357613bc90acf738f80c32 Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Fri, 14 May 2021 23:00:10 +0200\nSubject: [PATCH] net: dsa: qca8k: add support for internal phy and internal\n mdio\n\nAdd support to setup_mdio_bus for internal phy declaration. Introduce a\nflag to use the legacy port phy mapping by default and use the direct\nmapping if a mdio node is detected in the switch node. Register a\ndedicated mdio internal mdio bus to address the different mapping\nbetween port and phy if the mdio node is detected.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/dsa/qca8k.c | 112 +++++++++++++++++++++++++++++-----------\n drivers/net/dsa/qca8k.h |   1 +\n 2 files changed, 83 insertions(+), 30 deletions(-)\n\n--- a/drivers/net/dsa/qca8k.c\n+++ b/drivers/net/dsa/qca8k.c\n@@ -11,6 +11,7 @@\n #include <linux/netdevice.h>\n #include <net/dsa.h>\n #include <linux/of_net.h>\n+#include <linux/of_mdio.h>\n #include <linux/of_platform.h>\n #include <linux/if_bridge.h>\n #include <linux/mdio.h>\n@@ -629,7 +630,7 @@ qca8k_port_to_phy(int port)\n }\n \n static int\n-qca8k_mdio_busy_wait(struct qca8k_priv *priv, u32 reg, u32 mask)\n+qca8k_mdio_busy_wait(struct mii_bus *bus, u32 reg, u32 mask)\n {\n \tu16 r1, r2, page;\n \tu32 val;\n@@ -639,7 +640,7 @@ qca8k_mdio_busy_wait(struct qca8k_priv *\n \n \tret = read_poll_timeout(qca8k_mii_read32, val, !(val & mask), 0,\n \t\t\t\tQCA8K_BUSY_WAIT_TIMEOUT * USEC_PER_MSEC, false,\n-\t\t\t\tpriv->bus, 0x10 | r2, r1);\n+\t\t\t\tbus, 0x10 | r2, r1);\n \n \t/* Check if qca8k_read has failed for a different reason\n \t * before returnting -ETIMEDOUT\n@@ -651,19 +652,16 @@ qca8k_mdio_busy_wait(struct qca8k_priv *\n }\n \n static int\n-qca8k_mdio_write(struct qca8k_priv *priv, int port, u32 regnum, u16 data)\n+qca8k_mdio_write(struct mii_bus *salve_bus, int phy, int regnum, u16 data)\n {\n+\tstruct qca8k_priv *priv = salve_bus->priv;\n \tu16 r1, r2, page;\n-\tu32 phy, val;\n+\tu32 val;\n \tint ret;\n \n \tif (regnum >= QCA8K_MDIO_MASTER_MAX_REG)\n \t\treturn -EINVAL;\n \n-\t/* callee is responsible for not passing bad ports,\n-\t * but we still would like to make spills impossible.\n-\t */\n-\tphy = qca8k_port_to_phy(port) % PHY_MAX_ADDR;\n \tval = QCA8K_MDIO_MASTER_BUSY | QCA8K_MDIO_MASTER_EN |\n \t      QCA8K_MDIO_MASTER_WRITE | QCA8K_MDIO_MASTER_PHY_ADDR(phy) |\n \t      QCA8K_MDIO_MASTER_REG_ADDR(regnum) |\n@@ -679,33 +677,29 @@ qca8k_mdio_write(struct qca8k_priv *priv\n \n \tqca8k_mii_write32(priv->bus, 0x10 | r2, r1, val);\n \n-\tret = qca8k_mdio_busy_wait(priv, QCA8K_MDIO_MASTER_CTRL,\n+\tret = qca8k_mdio_busy_wait(priv->bus, QCA8K_MDIO_MASTER_CTRL,\n \t\t\t\t   QCA8K_MDIO_MASTER_BUSY);\n \n exit:\n-\tmutex_unlock(&priv->bus->mdio_lock);\n-\n \t/* even if the busy_wait timeouts try to clear the MASTER_EN */\n-\tqca8k_reg_clear(priv, QCA8K_MDIO_MASTER_CTRL,\n-\t\t\tQCA8K_MDIO_MASTER_EN);\n+\tqca8k_mii_write32(priv->bus, 0x10 | r2, r1, 0);\n+\n+\tmutex_unlock(&priv->bus->mdio_lock);\n \n \treturn ret;\n }\n \n static int\n-qca8k_mdio_read(struct qca8k_priv *priv, int port, u32 regnum)\n+qca8k_mdio_read(struct mii_bus *salve_bus, int phy, int regnum)\n {\n+\tstruct qca8k_priv *priv = salve_bus->priv;\n \tu16 r1, r2, page;\n-\tu32 phy, val;\n+\tu32 val;\n \tint ret;\n \n \tif (regnum >= QCA8K_MDIO_MASTER_MAX_REG)\n \t\treturn -EINVAL;\n \n-\t/* callee is responsible for not passing bad ports,\n-\t * but we still would like to make spills impossible.\n-\t */\n-\tphy = qca8k_port_to_phy(port) % PHY_MAX_ADDR;\n \tval = QCA8K_MDIO_MASTER_BUSY | QCA8K_MDIO_MASTER_EN |\n \t      QCA8K_MDIO_MASTER_READ | QCA8K_MDIO_MASTER_PHY_ADDR(phy) |\n \t      QCA8K_MDIO_MASTER_REG_ADDR(regnum);\n@@ -720,24 +714,22 @@ qca8k_mdio_read(struct qca8k_priv *priv,\n \n \tqca8k_mii_write32(priv->bus, 0x10 | r2, r1, val);\n \n-\tret = qca8k_mdio_busy_wait(priv, QCA8K_MDIO_MASTER_CTRL,\n+\tret = qca8k_mdio_busy_wait(priv->bus, QCA8K_MDIO_MASTER_CTRL,\n \t\t\t\t   QCA8K_MDIO_MASTER_BUSY);\n \tif (ret)\n \t\tgoto exit;\n \n \tval = qca8k_mii_read32(priv->bus, 0x10 | r2, r1);\n-\tval &= QCA8K_MDIO_MASTER_DATA_MASK;\n \n exit:\n+\t/* even if the busy_wait timeouts try to clear the MASTER_EN */\n+\tqca8k_mii_write32(priv->bus, 0x10 | r2, r1, 0);\n+\n \tmutex_unlock(&priv->bus->mdio_lock);\n \n \tif (val >= 0)\n \t\tval &= QCA8K_MDIO_MASTER_DATA_MASK;\n \n-\t/* even if the busy_wait timeouts try to clear the MASTER_EN */\n-\tqca8k_reg_clear(priv, QCA8K_MDIO_MASTER_CTRL,\n-\t\t\tQCA8K_MDIO_MASTER_EN);\n-\n \treturn val;\n }\n \n@@ -746,7 +738,14 @@ qca8k_phy_write(struct dsa_switch *ds, i\n {\n \tstruct qca8k_priv *priv = ds->priv;\n \n-\treturn qca8k_mdio_write(priv, port, regnum, data);\n+\t/* Check if the legacy mapping should be used and the\n+\t * port is not correctly mapped to the right PHY in the\n+\t * devicetree\n+\t */\n+\tif (priv->legacy_phy_port_mapping)\n+\t\tport = qca8k_port_to_phy(port) % PHY_MAX_ADDR;\n+\n+\treturn qca8k_mdio_write(priv->bus, port, regnum, data);\n }\n \n static int\n@@ -755,7 +754,14 @@ qca8k_phy_read(struct dsa_switch *ds, in\n \tstruct qca8k_priv *priv = ds->priv;\n \tint ret;\n \n-\tret = qca8k_mdio_read(priv, port, regnum);\n+\t/* Check if the legacy mapping should be used and the\n+\t * port is not correctly mapped to the right PHY in the\n+\t * devicetree\n+\t */\n+\tif (priv->legacy_phy_port_mapping)\n+\t\tport = qca8k_port_to_phy(port) % PHY_MAX_ADDR;\n+\n+\tret = qca8k_mdio_read(priv->bus, port, regnum);\n \n \tif (ret < 0)\n \t\treturn 0xffff;\n@@ -764,10 +770,37 @@ qca8k_phy_read(struct dsa_switch *ds, in\n }\n \n static int\n+qca8k_mdio_register(struct qca8k_priv *priv, struct device_node *mdio)\n+{\n+\tstruct dsa_switch *ds = priv->ds;\n+\tstruct mii_bus *bus;\n+\n+\tbus = devm_mdiobus_alloc(ds->dev);\n+\n+\tif (!bus)\n+\t\treturn -ENOMEM;\n+\n+\tbus->priv = (void *)priv;\n+\tbus->name = \"qca8k slave mii\";\n+\tbus->read = qca8k_mdio_read;\n+\tbus->write = qca8k_mdio_write;\n+\tsnprintf(bus->id, MII_BUS_ID_SIZE, \"qca8k-%d\",\n+\t\t ds->index);\n+\n+\tbus->parent = ds->dev;\n+\tbus->phy_mask = ~ds->phys_mii_mask;\n+\n+\tds->slave_mii_bus = bus;\n+\n+\treturn devm_of_mdiobus_register(priv->dev, bus, mdio);\n+}\n+\n+static int\n qca8k_setup_mdio_bus(struct qca8k_priv *priv)\n {\n \tu32 internal_mdio_mask = 0, external_mdio_mask = 0, reg;\n-\tstruct device_node *ports, *port;\n+\tstruct device_node *ports, *port, *mdio;\n+\tphy_interface_t mode;\n \tint err;\n \n \tports = of_get_child_by_name(priv->dev->of_node, \"ports\");\n@@ -788,7 +821,10 @@ qca8k_setup_mdio_bus(struct qca8k_priv *\n \t\tif (!dsa_is_user_port(priv->ds, reg))\n \t\t\tcontinue;\n \n-\t\tif (of_property_read_bool(port, \"phy-handle\"))\n+\t\tof_get_phy_mode(port, &mode);\n+\n+\t\tif (of_property_read_bool(port, \"phy-handle\") &&\n+\t\t    mode != PHY_INTERFACE_MODE_INTERNAL)\n \t\t\texternal_mdio_mask |= BIT(reg);\n \t\telse\n \t\t\tinternal_mdio_mask |= BIT(reg);\n@@ -825,8 +861,23 @@ qca8k_setup_mdio_bus(struct qca8k_priv *\n \t\t\t\t       QCA8K_MDIO_MASTER_EN);\n \t}\n \n+\t/* Check if the devicetree declare the port:phy mapping */\n+\tmdio = of_get_child_by_name(priv->dev->of_node, \"mdio\");\n+\tif (of_device_is_available(mdio)) {\n+\t\terr = qca8k_mdio_register(priv, mdio);\n+\t\tif (err)\n+\t\t\tof_node_put(mdio);\n+\n+\t\treturn err;\n+\t}\n+\n+\t/* If a mapping can't be found the legacy mapping is used,\n+\t * using the qca8k_port_to_phy function\n+\t */\n+\tpriv->legacy_phy_port_mapping = true;\n \tpriv->ops.phy_read = qca8k_phy_read;\n \tpriv->ops.phy_write = qca8k_phy_write;\n+\n \treturn 0;\n }\n \n@@ -1212,7 +1263,8 @@ qca8k_phylink_validate(struct dsa_switch\n \tcase 5:\n \t\t/* Internal PHY */\n \t\tif (state->interface != PHY_INTERFACE_MODE_NA &&\n-\t\t    state->interface != PHY_INTERFACE_MODE_GMII)\n+\t\t    state->interface != PHY_INTERFACE_MODE_GMII &&\n+\t\t    state->interface != PHY_INTERFACE_MODE_INTERNAL)\n \t\t\tgoto unsupported;\n \t\tbreak;\n \tcase 6: /* 2nd CPU port / external PHY */\n--- a/drivers/net/dsa/qca8k.h\n+++ b/drivers/net/dsa/qca8k.h\n@@ -255,6 +255,7 @@ struct qca8k_priv {\n \tu8 switch_revision;\n \tu8 rgmii_tx_delay;\n \tu8 rgmii_rx_delay;\n+\tbool legacy_phy_port_mapping;\n \tstruct regmap *regmap;\n \tstruct mii_bus *bus;\n \tstruct ar8xxx_port_status port_sts[QCA8K_NUM_PORTS];\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/735-v5.14-21-devicetree-bindings-dsa-qca8k-Document-internal-mdio.patch",
    "content": "From 0c994a28e7518f098c84a3049cb2915780db873a Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Fri, 14 May 2021 23:00:11 +0200\nSubject: [PATCH] devicetree: bindings: dsa: qca8k: Document internal mdio\n definition\n\nDocument new way of declare mapping of internal PHY to port.\nThe new implementation directly declare the PHY connected to the port\nby adding a node in the switch node. The driver detect this and register\nan internal mdiobus using the mapping defined in the mdio node.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nReviewed-by: Rob Herring <robh@kernel.org>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n .../devicetree/bindings/net/dsa/qca8k.txt     | 39 +++++++++++++++++++\n 1 file changed, 39 insertions(+)\n\n--- a/Documentation/devicetree/bindings/net/dsa/qca8k.txt\n+++ b/Documentation/devicetree/bindings/net/dsa/qca8k.txt\n@@ -21,6 +21,10 @@ described in dsa/dsa.txt. If the QCA8K s\n mdio-bus each subnode describing a port needs to have a valid phandle\n referencing the internal PHY it is connected to. This is because there's no\n N:N mapping of port and PHY id.\n+To declare the internal mdio-bus configuration, declare a mdio node in the\n+switch node and declare the phandle for the port referencing the internal\n+PHY is connected to. In this config a internal mdio-bus is registered and\n+the mdio MASTER is used as communication.\n \n Don't use mixed external and internal mdio-bus configurations, as this is\n not supported by the hardware.\n@@ -150,26 +154,61 @@ for the internal master mdio-bus configu\n \t\t\t\tport@1 {\n \t\t\t\t\treg = <1>;\n \t\t\t\t\tlabel = \"lan1\";\n+\t\t\t\t\tphy-mode = \"internal\";\n+\t\t\t\t\tphy-handle = <&phy_port1>;\n \t\t\t\t};\n \n \t\t\t\tport@2 {\n \t\t\t\t\treg = <2>;\n \t\t\t\t\tlabel = \"lan2\";\n+\t\t\t\t\tphy-mode = \"internal\";\n+\t\t\t\t\tphy-handle = <&phy_port2>;\n \t\t\t\t};\n \n \t\t\t\tport@3 {\n \t\t\t\t\treg = <3>;\n \t\t\t\t\tlabel = \"lan3\";\n+\t\t\t\t\tphy-mode = \"internal\";\n+\t\t\t\t\tphy-handle = <&phy_port3>;\n \t\t\t\t};\n \n \t\t\t\tport@4 {\n \t\t\t\t\treg = <4>;\n \t\t\t\t\tlabel = \"lan4\";\n+\t\t\t\t\tphy-mode = \"internal\";\n+\t\t\t\t\tphy-handle = <&phy_port4>;\n \t\t\t\t};\n \n \t\t\t\tport@5 {\n \t\t\t\t\treg = <5>;\n \t\t\t\t\tlabel = \"wan\";\n+\t\t\t\t\tphy-mode = \"internal\";\n+\t\t\t\t\tphy-handle = <&phy_port5>;\n+\t\t\t\t};\n+\t\t\t};\n+\n+\t\t\tmdio {\n+\t\t\t\t#address-cells = <1>;\n+\t\t\t\t#size-cells = <0>;\n+\n+\t\t\t\tphy_port1: phy@0 {\n+\t\t\t\t\treg = <0>;\n+\t\t\t\t};\n+\n+\t\t\t\tphy_port2: phy@1 {\n+\t\t\t\t\treg = <1>;\n+\t\t\t\t};\n+\n+\t\t\t\tphy_port3: phy@2 {\n+\t\t\t\t\treg = <2>;\n+\t\t\t\t};\n+\n+\t\t\t\tphy_port4: phy@3 {\n+\t\t\t\t\treg = <3>;\n+\t\t\t\t};\n+\n+\t\t\t\tphy_port5: phy@4 {\n+\t\t\t\t\treg = <4>;\n \t\t\t\t};\n \t\t\t};\n \t\t};\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/735-v5.14-22-net-dsa-qca8k-improve-internal-mdio-read-write-bus-a.patch",
    "content": "From b7ebac354d54f1657bb89b7a7ca149db50203e6a Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Fri, 14 May 2021 23:00:12 +0200\nSubject: [PATCH] net: dsa: qca8k: improve internal mdio read/write bus access\n\nImprove the internal mdio read/write bus access by caching the value\nwithout accessing it for every read/write.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/dsa/qca8k.c | 28 +++++++++++++++-------------\n 1 file changed, 15 insertions(+), 13 deletions(-)\n\n--- a/drivers/net/dsa/qca8k.c\n+++ b/drivers/net/dsa/qca8k.c\n@@ -655,6 +655,7 @@ static int\n qca8k_mdio_write(struct mii_bus *salve_bus, int phy, int regnum, u16 data)\n {\n \tstruct qca8k_priv *priv = salve_bus->priv;\n+\tstruct mii_bus *bus = priv->bus;\n \tu16 r1, r2, page;\n \tu32 val;\n \tint ret;\n@@ -669,22 +670,22 @@ qca8k_mdio_write(struct mii_bus *salve_b\n \n \tqca8k_split_addr(QCA8K_MDIO_MASTER_CTRL, &r1, &r2, &page);\n \n-\tmutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED);\n+\tmutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);\n \n-\tret = qca8k_set_page(priv->bus, page);\n+\tret = qca8k_set_page(bus, page);\n \tif (ret)\n \t\tgoto exit;\n \n-\tqca8k_mii_write32(priv->bus, 0x10 | r2, r1, val);\n+\tqca8k_mii_write32(bus, 0x10 | r2, r1, val);\n \n-\tret = qca8k_mdio_busy_wait(priv->bus, QCA8K_MDIO_MASTER_CTRL,\n+\tret = qca8k_mdio_busy_wait(bus, QCA8K_MDIO_MASTER_CTRL,\n \t\t\t\t   QCA8K_MDIO_MASTER_BUSY);\n \n exit:\n \t/* even if the busy_wait timeouts try to clear the MASTER_EN */\n-\tqca8k_mii_write32(priv->bus, 0x10 | r2, r1, 0);\n+\tqca8k_mii_write32(bus, 0x10 | r2, r1, 0);\n \n-\tmutex_unlock(&priv->bus->mdio_lock);\n+\tmutex_unlock(&bus->mdio_lock);\n \n \treturn ret;\n }\n@@ -693,6 +694,7 @@ static int\n qca8k_mdio_read(struct mii_bus *salve_bus, int phy, int regnum)\n {\n \tstruct qca8k_priv *priv = salve_bus->priv;\n+\tstruct mii_bus *bus = priv->bus;\n \tu16 r1, r2, page;\n \tu32 val;\n \tint ret;\n@@ -706,26 +708,26 @@ qca8k_mdio_read(struct mii_bus *salve_bu\n \n \tqca8k_split_addr(QCA8K_MDIO_MASTER_CTRL, &r1, &r2, &page);\n \n-\tmutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED);\n+\tmutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);\n \n-\tret = qca8k_set_page(priv->bus, page);\n+\tret = qca8k_set_page(bus, page);\n \tif (ret)\n \t\tgoto exit;\n \n-\tqca8k_mii_write32(priv->bus, 0x10 | r2, r1, val);\n+\tqca8k_mii_write32(bus, 0x10 | r2, r1, val);\n \n-\tret = qca8k_mdio_busy_wait(priv->bus, QCA8K_MDIO_MASTER_CTRL,\n+\tret = qca8k_mdio_busy_wait(bus, QCA8K_MDIO_MASTER_CTRL,\n \t\t\t\t   QCA8K_MDIO_MASTER_BUSY);\n \tif (ret)\n \t\tgoto exit;\n \n-\tval = qca8k_mii_read32(priv->bus, 0x10 | r2, r1);\n+\tval = qca8k_mii_read32(bus, 0x10 | r2, r1);\n \n exit:\n \t/* even if the busy_wait timeouts try to clear the MASTER_EN */\n-\tqca8k_mii_write32(priv->bus, 0x10 | r2, r1, 0);\n+\tqca8k_mii_write32(bus, 0x10 | r2, r1, 0);\n \n-\tmutex_unlock(&priv->bus->mdio_lock);\n+\tmutex_unlock(&bus->mdio_lock);\n \n \tif (val >= 0)\n \t\tval &= QCA8K_MDIO_MASTER_DATA_MASK;\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/735-v5.14-23-net-dsa-qca8k-pass-switch_revision-info-to-phy-dev_f.patch",
    "content": "From a46aec02bc06ac2c33f326339e4ef88c735dc30d Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Fri, 14 May 2021 23:00:13 +0200\nSubject: [PATCH] net: dsa: qca8k: pass switch_revision info to phy dev_flags\n\nDefine get_phy_flags to pass switch_Revision needed to tweak the\ninternal PHY with debug values based on the revision.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nReviewed-by: Florian Fainelli <f.fainelli@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/dsa/qca8k.c | 17 +++++++++++++++++\n 1 file changed, 17 insertions(+)\n\n--- a/drivers/net/dsa/qca8k.c\n+++ b/drivers/net/dsa/qca8k.c\n@@ -1740,6 +1740,22 @@ qca8k_port_vlan_del(struct dsa_switch *d\n \treturn ret;\n }\n \n+static u32 qca8k_get_phy_flags(struct dsa_switch *ds, int port)\n+{\n+\tstruct qca8k_priv *priv = ds->priv;\n+\n+\t/* Communicate to the phy internal driver the switch revision.\n+\t * Based on the switch revision different values needs to be\n+\t * set to the dbg and mmd reg on the phy.\n+\t * The first 2 bit are used to communicate the switch revision\n+\t * to the phy driver.\n+\t */\n+\tif (port > 0 && port < 6)\n+\t\treturn priv->switch_revision;\n+\n+\treturn 0;\n+}\n+\n static enum dsa_tag_protocol\n qca8k_get_tag_protocol(struct dsa_switch *ds, int port,\n \t\t       enum dsa_tag_protocol mp)\n@@ -1774,6 +1790,7 @@ static const struct dsa_switch_ops qca8k\n \t.phylink_mac_config\t= qca8k_phylink_mac_config,\n \t.phylink_mac_link_down\t= qca8k_phylink_mac_link_down,\n \t.phylink_mac_link_up\t= qca8k_phylink_mac_link_up,\n+\t.get_phy_flags\t\t= qca8k_get_phy_flags,\n };\n \n static int qca8k_read_switch_id(struct qca8k_priv *priv)\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/735-v5.14-25-net-phy-add-support-for-qca8k-switch-internal-PHY-in.patch",
    "content": "From 272833b9b3b3969be7a91839121d86662c8c4253 Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Fri, 14 May 2021 23:00:15 +0200\nSubject: [PATCH] net: phy: add support for qca8k switch internal PHY in at803x\n\nSince the at803x share the same regs, it's assumed they are based on the\nsame implementation. Make it part of the at803x PHY driver to skip\nhaving redudant code.\nAdd initial support for qca8k internal PHYs. The internal PHYs requires\nspecial mmd and debug values to be set based on the switch revision\npasswd using the dev_flags. Supports output of idle, receive and eee_wake\nerrors stats.\nSome debug values sets can't be translated as the documentation lacks any\nreference about them.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/phy/Kconfig  |   5 +-\n drivers/net/phy/at803x.c | 132 ++++++++++++++++++++++++++++++++++++++-\n 2 files changed, 134 insertions(+), 3 deletions(-)\n\n--- a/drivers/net/phy/Kconfig\n+++ b/drivers/net/phy/Kconfig\n@@ -235,10 +235,11 @@ config NXP_TJA11XX_PHY\n \t  Currently supports the NXP TJA1100 and TJA1101 PHY.\n \n config AT803X_PHY\n-\ttristate \"Qualcomm Atheros AR803X PHYs\"\n+\ttristate \"Qualcomm Atheros AR803X PHYs and QCA833x PHYs\"\n \tdepends on REGULATOR\n \thelp\n-\t  Currently supports the AR8030, AR8031, AR8033 and AR8035 model\n+\t  Currently supports the AR8030, AR8031, AR8033, AR8035 and internal\n+\t  QCA8337(Internal qca8k PHY) model\n \n config QSEMI_PHY\n \ttristate \"Quality Semiconductor PHYs\"\n--- a/drivers/net/phy/at803x.c\n+++ b/drivers/net/phy/at803x.c\n@@ -92,10 +92,16 @@\n #define AT803X_DEBUG_REG_5\t\t\t0x05\n #define AT803X_DEBUG_TX_CLK_DLY_EN\t\tBIT(8)\n \n+#define AT803X_DEBUG_REG_3C\t\t\t0x3C\n+\n+#define AT803X_DEBUG_REG_3D\t\t\t0x3D\n+\n #define AT803X_DEBUG_REG_1F\t\t\t0x1F\n #define AT803X_DEBUG_PLL_ON\t\t\tBIT(2)\n #define AT803X_DEBUG_RGMII_1V8\t\t\tBIT(3)\n \n+#define MDIO_AZ_DEBUG\t\t\t\t0x800D\n+\n /* AT803x supports either the XTAL input pad, an internal PLL or the\n  * DSP as clock reference for the clock output pad. The XTAL reference\n  * is only used for 25 MHz output, all other frequencies need the PLL.\n@@ -142,10 +148,34 @@\n #define AT803X_PAGE_FIBER\t\t0\n #define AT803X_PAGE_COPPER\t\t1\n \n+#define QCA8327_PHY_ID\t\t\t\t0x004dd034\n+#define QCA8337_PHY_ID\t\t\t\t0x004dd036\n+#define QCA8K_PHY_ID_MASK\t\t\t0xffffffff\n+\n+#define QCA8K_DEVFLAGS_REVISION_MASK\t\tGENMASK(2, 0)\n+\n MODULE_DESCRIPTION(\"Qualcomm Atheros AR803x PHY driver\");\n MODULE_AUTHOR(\"Matus Ujhelyi\");\n MODULE_LICENSE(\"GPL\");\n \n+enum stat_access_type {\n+\tPHY,\n+\tMMD\n+};\n+\n+struct at803x_hw_stat {\n+\tconst char *string;\n+\tu8 reg;\n+\tu32 mask;\n+\tenum stat_access_type access_type;\n+};\n+\n+static struct at803x_hw_stat at803x_hw_stats[] = {\n+\t{ \"phy_idle_errors\", 0xa, GENMASK(7, 0), PHY},\n+\t{ \"phy_receive_errors\", 0x15, GENMASK(15, 0), PHY},\n+\t{ \"eee_wake_errors\", 0x16, GENMASK(15, 0), MMD},\n+};\n+\n struct at803x_priv {\n \tint flags;\n #define AT803X_KEEP_PLL_ENABLED\tBIT(0)\t/* don't turn off internal PLL */\n@@ -154,6 +184,7 @@ struct at803x_priv {\n \tstruct regulator_dev *vddio_rdev;\n \tstruct regulator_dev *vddh_rdev;\n \tstruct regulator *vddio;\n+\tu64 stats[ARRAY_SIZE(at803x_hw_stats)];\n };\n \n struct at803x_context {\n@@ -165,6 +196,17 @@ struct at803x_context {\n \tu16 led_control;\n };\n \n+static int at803x_debug_reg_write(struct phy_device *phydev, u16 reg, u16 data)\n+{\n+\tint ret;\n+\n+\tret = phy_write(phydev, AT803X_DEBUG_ADDR, reg);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\treturn phy_write(phydev, AT803X_DEBUG_DATA, data);\n+}\n+\n static int at803x_debug_reg_read(struct phy_device *phydev, u16 reg)\n {\n \tint ret;\n@@ -327,6 +369,53 @@ static void at803x_get_wol(struct phy_de\n \t\twol->wolopts |= WAKE_MAGIC;\n }\n \n+static int at803x_get_sset_count(struct phy_device *phydev)\n+{\n+\treturn ARRAY_SIZE(at803x_hw_stats);\n+}\n+\n+static void at803x_get_strings(struct phy_device *phydev, u8 *data)\n+{\n+\tint i;\n+\n+\tfor (i = 0; i < ARRAY_SIZE(at803x_hw_stats); i++) {\n+\t\tstrscpy(data + i * ETH_GSTRING_LEN,\n+\t\t\tat803x_hw_stats[i].string, ETH_GSTRING_LEN);\n+\t}\n+}\n+\n+static u64 at803x_get_stat(struct phy_device *phydev, int i)\n+{\n+\tstruct at803x_hw_stat stat = at803x_hw_stats[i];\n+\tstruct at803x_priv *priv = phydev->priv;\n+\tint val;\n+\tu64 ret;\n+\n+\tif (stat.access_type == MMD)\n+\t\tval = phy_read_mmd(phydev, MDIO_MMD_PCS, stat.reg);\n+\telse\n+\t\tval = phy_read(phydev, stat.reg);\n+\n+\tif (val < 0) {\n+\t\tret = U64_MAX;\n+\t} else {\n+\t\tval = val & stat.mask;\n+\t\tpriv->stats[i] += val;\n+\t\tret = priv->stats[i];\n+\t}\n+\n+\treturn ret;\n+}\n+\n+static void at803x_get_stats(struct phy_device *phydev,\n+\t\t\t     struct ethtool_stats *stats, u64 *data)\n+{\n+\tint i;\n+\n+\tfor (i = 0; i < ARRAY_SIZE(at803x_hw_stats); i++)\n+\t\tdata[i] = at803x_get_stat(phydev, i);\n+}\n+\n static int at803x_suspend(struct phy_device *phydev)\n {\n \tint value;\n@@ -1102,6 +1191,34 @@ static int at803x_cable_test_start(struc\n \treturn 0;\n }\n \n+static int qca83xx_config_init(struct phy_device *phydev)\n+{\n+\tu8 switch_revision;\n+\n+\tswitch_revision = phydev->dev_flags & QCA8K_DEVFLAGS_REVISION_MASK;\n+\n+\tswitch (switch_revision) {\n+\tcase 1:\n+\t\t/* For 100M waveform */\n+\t\tat803x_debug_reg_write(phydev, AT803X_DEBUG_REG_0, 0x02ea);\n+\t\t/* Turn on Gigabit clock */\n+\t\tat803x_debug_reg_write(phydev, AT803X_DEBUG_REG_3D, 0x68a0);\n+\t\tbreak;\n+\n+\tcase 2:\n+\t\tphy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0x0);\n+\t\tfallthrough;\n+\tcase 4:\n+\t\tphy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_AZ_DEBUG, 0x803f);\n+\t\tat803x_debug_reg_write(phydev, AT803X_DEBUG_REG_3D, 0x6860);\n+\t\tat803x_debug_reg_write(phydev, AT803X_DEBUG_REG_5, 0x2c46);\n+\t\tat803x_debug_reg_write(phydev, AT803X_DEBUG_REG_3C, 0x6000);\n+\t\tbreak;\n+\t}\n+\n+\treturn 0;\n+}\n+\n static struct phy_driver at803x_driver[] = {\n {\n \t/* Qualcomm Atheros AR8035 */\n@@ -1198,7 +1315,20 @@ static struct phy_driver at803x_driver[]\n \t.read_status\t\t= at803x_read_status,\n \t.soft_reset\t\t= genphy_soft_reset,\n \t.config_aneg\t\t= at803x_config_aneg,\n-} };\n+}, {\n+\t/* QCA8337 */\n+\t.phy_id = QCA8337_PHY_ID,\n+\t.phy_id_mask = QCA8K_PHY_ID_MASK,\n+\t.name = \"QCA PHY 8337\",\n+\t/* PHY_GBIT_FEATURES */\n+\t.probe = at803x_probe,\n+\t.flags = PHY_IS_INTERNAL,\n+\t.config_init = qca83xx_config_init,\n+\t.soft_reset = genphy_soft_reset,\n+\t.get_sset_count = at803x_get_sset_count,\n+\t.get_strings = at803x_get_strings,\n+\t.get_stats = at803x_get_stats,\n+}, };\n \n module_phy_driver(at803x_driver);\n \n"
  },
  {
    "path": "target/linux/generic/backport-5.10/736-v5.14-net-dsa-qca8k-fix-missing-unlock-on-error-in-qca8k-vlan.patch",
    "content": "From 0d56e5c191b197e1d30a0a4c92628836dafced0f Mon Sep 17 00:00:00 2001\nFrom: Wei Yongjun <weiyongjun1@huawei.com>\nDate: Tue, 18 May 2021 11:24:13 +0000\nSubject: [PATCH] net: dsa: qca8k: fix missing unlock on error in\n qca8k_vlan_(add|del)\n\nAdd the missing unlock before return from function qca8k_vlan_add()\nand qca8k_vlan_del() in the error handling case.\n\nFixes: 028f5f8ef44f (\"net: dsa: qca8k: handle error with qca8k_read operation\")\nReported-by: Hulk Robot <hulkci@huawei.com>\nSigned-off-by: Wei Yongjun <weiyongjun1@huawei.com>\nReviewed-by: Vladimir Oltean <olteanv@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/dsa/qca8k.c | 16 ++++++++++------\n 1 file changed, 10 insertions(+), 6 deletions(-)\n\n--- a/drivers/net/dsa/qca8k.c\n+++ b/drivers/net/dsa/qca8k.c\n@@ -506,8 +506,10 @@ qca8k_vlan_add(struct qca8k_priv *priv,\n \t\tgoto out;\n \n \treg = qca8k_read(priv, QCA8K_REG_VTU_FUNC0);\n-\tif (reg < 0)\n-\t\treturn reg;\n+\tif (reg < 0) {\n+\t\tret = reg;\n+\t\tgoto out;\n+\t}\n \treg |= QCA8K_VTU_FUNC0_VALID | QCA8K_VTU_FUNC0_IVL_EN;\n \treg &= ~(QCA8K_VTU_FUNC0_EG_MODE_MASK << QCA8K_VTU_FUNC0_EG_MODE_S(port));\n \tif (untagged)\n@@ -519,7 +521,7 @@ qca8k_vlan_add(struct qca8k_priv *priv,\n \n \tret = qca8k_write(priv, QCA8K_REG_VTU_FUNC0, reg);\n \tif (ret)\n-\t\treturn ret;\n+\t\tgoto out;\n \tret = qca8k_vlan_access(priv, QCA8K_VLAN_LOAD, vid);\n \n out:\n@@ -541,8 +543,10 @@ qca8k_vlan_del(struct qca8k_priv *priv,\n \t\tgoto out;\n \n \treg = qca8k_read(priv, QCA8K_REG_VTU_FUNC0);\n-\tif (reg < 0)\n-\t\treturn reg;\n+\tif (reg < 0) {\n+\t\tret = reg;\n+\t\tgoto out;\n+\t}\n \treg &= ~(3 << QCA8K_VTU_FUNC0_EG_MODE_S(port));\n \treg |= QCA8K_VTU_FUNC0_EG_MODE_NOT <<\n \t\t\tQCA8K_VTU_FUNC0_EG_MODE_S(port);\n@@ -564,7 +568,7 @@ qca8k_vlan_del(struct qca8k_priv *priv,\n \t} else {\n \t\tret = qca8k_write(priv, QCA8K_REG_VTU_FUNC0, reg);\n \t\tif (ret)\n-\t\t\treturn ret;\n+\t\t\tgoto out;\n \t\tret = qca8k_vlan_access(priv, QCA8K_VLAN_LOAD, vid);\n \t}\n \n"
  },
  {
    "path": "target/linux/generic/backport-5.10/737-v5.14-01-net-dsa-qca8k-check-return-value-of-read-functions-c.patch",
    "content": "From 7c9896e37807862e276064dd9331860f5d27affc Mon Sep 17 00:00:00 2001\nFrom: Yang Yingliang <yangyingliang@huawei.com>\nDate: Sat, 29 May 2021 11:04:38 +0800\nSubject: [PATCH] net: dsa: qca8k: check return value of read functions\n correctly\n\nCurrent return type of qca8k_mii_read32() and qca8k_read() are\nunsigned, it can't be negative, so the return value check is\nunuseful. For check the return value correctly, change return\ntype of the read functions and add a output parameter to store\nthe read value.\n\nSigned-off-by: Yang Yingliang <yangyingliang@huawei.com>\nSigned-off-by: Jakub Kicinski <kuba@kernel.org>\n---\n drivers/net/dsa/qca8k.c | 130 +++++++++++++++++++---------------------\n 1 file changed, 60 insertions(+), 70 deletions(-)\n\n--- a/drivers/net/dsa/qca8k.c\n+++ b/drivers/net/dsa/qca8k.c\n@@ -89,26 +89,26 @@ qca8k_split_addr(u32 regaddr, u16 *r1, u\n \t*page = regaddr & 0x3ff;\n }\n \n-static u32\n-qca8k_mii_read32(struct mii_bus *bus, int phy_id, u32 regnum)\n+static int\n+qca8k_mii_read32(struct mii_bus *bus, int phy_id, u32 regnum, u32 *val)\n {\n-\tu32 val;\n \tint ret;\n \n \tret = bus->read(bus, phy_id, regnum);\n \tif (ret >= 0) {\n-\t\tval = ret;\n+\t\t*val = ret;\n \t\tret = bus->read(bus, phy_id, regnum + 1);\n-\t\tval |= ret << 16;\n+\t\t*val |= ret << 16;\n \t}\n \n \tif (ret < 0) {\n \t\tdev_err_ratelimited(&bus->dev,\n \t\t\t\t    \"failed to read qca8k 32bit register\\n\");\n+\t\t*val = 0;\n \t\treturn ret;\n \t}\n \n-\treturn val;\n+\treturn 0;\n }\n \n static void\n@@ -148,26 +148,26 @@ qca8k_set_page(struct mii_bus *bus, u16\n \treturn 0;\n }\n \n-static u32\n-qca8k_read(struct qca8k_priv *priv, u32 reg)\n+static int\n+qca8k_read(struct qca8k_priv *priv, u32 reg, u32 *val)\n {\n \tstruct mii_bus *bus = priv->bus;\n \tu16 r1, r2, page;\n-\tu32 val;\n+\tint ret;\n \n \tqca8k_split_addr(reg, &r1, &r2, &page);\n \n \tmutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);\n \n-\tval = qca8k_set_page(bus, page);\n-\tif (val < 0)\n+\tret = qca8k_set_page(bus, page);\n+\tif (ret < 0)\n \t\tgoto exit;\n \n-\tval = qca8k_mii_read32(bus, 0x10 | r2, r1);\n+\tret = qca8k_mii_read32(bus, 0x10 | r2, r1, val);\n \n exit:\n \tmutex_unlock(&bus->mdio_lock);\n-\treturn val;\n+\treturn ret;\n }\n \n static int\n@@ -208,11 +208,9 @@ qca8k_rmw(struct qca8k_priv *priv, u32 r\n \tif (ret < 0)\n \t\tgoto exit;\n \n-\tval = qca8k_mii_read32(bus, 0x10 | r2, r1);\n-\tif (val < 0) {\n-\t\tret = val;\n+\tret = qca8k_mii_read32(bus, 0x10 | r2, r1, &val);\n+\tif (ret < 0)\n \t\tgoto exit;\n-\t}\n \n \tval &= ~mask;\n \tval |= write_val;\n@@ -240,15 +238,8 @@ static int\n qca8k_regmap_read(void *ctx, uint32_t reg, uint32_t *val)\n {\n \tstruct qca8k_priv *priv = (struct qca8k_priv *)ctx;\n-\tint ret;\n-\n-\tret = qca8k_read(priv, reg);\n-\tif (ret < 0)\n-\t\treturn ret;\n-\n-\t*val = ret;\n \n-\treturn 0;\n+\treturn qca8k_read(priv, reg, val);\n }\n \n static int\n@@ -296,18 +287,18 @@ static struct regmap_config qca8k_regmap\n static int\n qca8k_busy_wait(struct qca8k_priv *priv, u32 reg, u32 mask)\n {\n+\tint ret, ret1;\n \tu32 val;\n-\tint ret;\n \n-\tret = read_poll_timeout(qca8k_read, val, !(val & mask),\n+\tret = read_poll_timeout(qca8k_read, ret1, !(val & mask),\n \t\t\t\t0, QCA8K_BUSY_WAIT_TIMEOUT * USEC_PER_MSEC, false,\n-\t\t\t\tpriv, reg);\n+\t\t\t\tpriv, reg, &val);\n \n \t/* Check if qca8k_read has failed for a different reason\n \t * before returning -ETIMEDOUT\n \t */\n-\tif (ret < 0 && val < 0)\n-\t\treturn val;\n+\tif (ret < 0 && ret1 < 0)\n+\t\treturn ret1;\n \n \treturn ret;\n }\n@@ -316,13 +307,13 @@ static int\n qca8k_fdb_read(struct qca8k_priv *priv, struct qca8k_fdb *fdb)\n {\n \tu32 reg[4], val;\n-\tint i;\n+\tint i, ret;\n \n \t/* load the ARL table into an array */\n \tfor (i = 0; i < 4; i++) {\n-\t\tval = qca8k_read(priv, QCA8K_REG_ATU_DATA0 + (i * 4));\n-\t\tif (val < 0)\n-\t\t\treturn val;\n+\t\tret = qca8k_read(priv, QCA8K_REG_ATU_DATA0 + (i * 4), &val);\n+\t\tif (ret < 0)\n+\t\t\treturn ret;\n \n \t\treg[i] = val;\n \t}\n@@ -396,9 +387,9 @@ qca8k_fdb_access(struct qca8k_priv *priv\n \n \t/* Check for table full violation when adding an entry */\n \tif (cmd == QCA8K_FDB_LOAD) {\n-\t\treg = qca8k_read(priv, QCA8K_REG_ATU_FUNC);\n-\t\tif (reg < 0)\n-\t\t\treturn reg;\n+\t\tret = qca8k_read(priv, QCA8K_REG_ATU_FUNC, &reg);\n+\t\tif (ret < 0)\n+\t\t\treturn ret;\n \t\tif (reg & QCA8K_ATU_FUNC_FULL)\n \t\t\treturn -1;\n \t}\n@@ -477,9 +468,9 @@ qca8k_vlan_access(struct qca8k_priv *pri\n \n \t/* Check for table full violation when adding an entry */\n \tif (cmd == QCA8K_VLAN_LOAD) {\n-\t\treg = qca8k_read(priv, QCA8K_REG_VTU_FUNC1);\n-\t\tif (reg < 0)\n-\t\t\treturn reg;\n+\t\tret = qca8k_read(priv, QCA8K_REG_VTU_FUNC1, &reg);\n+\t\tif (ret < 0)\n+\t\t\treturn ret;\n \t\tif (reg & QCA8K_VTU_FUNC1_FULL)\n \t\t\treturn -ENOMEM;\n \t}\n@@ -505,11 +496,9 @@ qca8k_vlan_add(struct qca8k_priv *priv,\n \tif (ret < 0)\n \t\tgoto out;\n \n-\treg = qca8k_read(priv, QCA8K_REG_VTU_FUNC0);\n-\tif (reg < 0) {\n-\t\tret = reg;\n+\tret = qca8k_read(priv, QCA8K_REG_VTU_FUNC0, &reg);\n+\tif (ret < 0)\n \t\tgoto out;\n-\t}\n \treg |= QCA8K_VTU_FUNC0_VALID | QCA8K_VTU_FUNC0_IVL_EN;\n \treg &= ~(QCA8K_VTU_FUNC0_EG_MODE_MASK << QCA8K_VTU_FUNC0_EG_MODE_S(port));\n \tif (untagged)\n@@ -542,11 +531,9 @@ qca8k_vlan_del(struct qca8k_priv *priv,\n \tif (ret < 0)\n \t\tgoto out;\n \n-\treg = qca8k_read(priv, QCA8K_REG_VTU_FUNC0);\n-\tif (reg < 0) {\n-\t\tret = reg;\n+\tret = qca8k_read(priv, QCA8K_REG_VTU_FUNC0, &reg);\n+\tif (ret < 0)\n \t\tgoto out;\n-\t}\n \treg &= ~(3 << QCA8K_VTU_FUNC0_EG_MODE_S(port));\n \treg |= QCA8K_VTU_FUNC0_EG_MODE_NOT <<\n \t\t\tQCA8K_VTU_FUNC0_EG_MODE_S(port);\n@@ -638,19 +625,19 @@ qca8k_mdio_busy_wait(struct mii_bus *bus\n {\n \tu16 r1, r2, page;\n \tu32 val;\n-\tint ret;\n+\tint ret, ret1;\n \n \tqca8k_split_addr(reg, &r1, &r2, &page);\n \n-\tret = read_poll_timeout(qca8k_mii_read32, val, !(val & mask), 0,\n+\tret = read_poll_timeout(qca8k_mii_read32, ret1, !(val & mask), 0,\n \t\t\t\tQCA8K_BUSY_WAIT_TIMEOUT * USEC_PER_MSEC, false,\n-\t\t\t\tbus, 0x10 | r2, r1);\n+\t\t\t\tbus, 0x10 | r2, r1, &val);\n \n \t/* Check if qca8k_read has failed for a different reason\n \t * before returnting -ETIMEDOUT\n \t */\n-\tif (ret < 0 && val < 0)\n-\t\treturn val;\n+\tif (ret < 0 && ret1 < 0)\n+\t\treturn ret1;\n \n \treturn ret;\n }\n@@ -725,7 +712,7 @@ qca8k_mdio_read(struct mii_bus *salve_bu\n \tif (ret)\n \t\tgoto exit;\n \n-\tval = qca8k_mii_read32(bus, 0x10 | r2, r1);\n+\tret = qca8k_mii_read32(bus, 0x10 | r2, r1, &val);\n \n exit:\n \t/* even if the busy_wait timeouts try to clear the MASTER_EN */\n@@ -733,10 +720,10 @@ exit:\n \n \tmutex_unlock(&bus->mdio_lock);\n \n-\tif (val >= 0)\n-\t\tval &= QCA8K_MDIO_MASTER_DATA_MASK;\n+\tif (ret >= 0)\n+\t\tret = val & QCA8K_MDIO_MASTER_DATA_MASK;\n \n-\treturn val;\n+\treturn ret;\n }\n \n static int\n@@ -1211,7 +1198,7 @@ qca8k_phylink_mac_config(struct dsa_swit\n \t\tqca8k_write(priv, reg, QCA8K_PORT_PAD_SGMII_EN);\n \n \t\t/* Enable/disable SerDes auto-negotiation as necessary */\n-\t\tval = qca8k_read(priv, QCA8K_REG_PWS);\n+\t\tqca8k_read(priv, QCA8K_REG_PWS, &val);\n \t\tif (phylink_autoneg_inband(mode))\n \t\t\tval &= ~QCA8K_PWS_SERDES_AEN_DIS;\n \t\telse\n@@ -1219,7 +1206,7 @@ qca8k_phylink_mac_config(struct dsa_swit\n \t\tqca8k_write(priv, QCA8K_REG_PWS, val);\n \n \t\t/* Configure the SGMII parameters */\n-\t\tval = qca8k_read(priv, QCA8K_REG_SGMII_CTRL);\n+\t\tqca8k_read(priv, QCA8K_REG_SGMII_CTRL, &val);\n \n \t\tval |= QCA8K_SGMII_EN_PLL | QCA8K_SGMII_EN_RX |\n \t\t\tQCA8K_SGMII_EN_TX | QCA8K_SGMII_EN_SD;\n@@ -1314,10 +1301,11 @@ qca8k_phylink_mac_link_state(struct dsa_\n {\n \tstruct qca8k_priv *priv = ds->priv;\n \tu32 reg;\n+\tint ret;\n \n-\treg = qca8k_read(priv, QCA8K_REG_PORT_STATUS(port));\n-\tif (reg < 0)\n-\t\treturn reg;\n+\tret = qca8k_read(priv, QCA8K_REG_PORT_STATUS(port), &reg);\n+\tif (ret < 0)\n+\t\treturn ret;\n \n \tstate->link = !!(reg & QCA8K_PORT_STATUS_LINK_UP);\n \tstate->an_complete = state->link;\n@@ -1419,19 +1407,20 @@ qca8k_get_ethtool_stats(struct dsa_switc\n \tstruct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;\n \tconst struct qca8k_mib_desc *mib;\n \tu32 reg, i, val;\n-\tu64 hi;\n+\tu64 hi = 0;\n+\tint ret;\n \n \tfor (i = 0; i < ARRAY_SIZE(ar8327_mib); i++) {\n \t\tmib = &ar8327_mib[i];\n \t\treg = QCA8K_PORT_MIB_COUNTER(port) + mib->offset;\n \n-\t\tval = qca8k_read(priv, reg);\n-\t\tif (val < 0)\n+\t\tret = qca8k_read(priv, reg, &val);\n+\t\tif (ret < 0)\n \t\t\tcontinue;\n \n \t\tif (mib->size == 2) {\n-\t\t\thi = qca8k_read(priv, reg + 4);\n-\t\t\tif (hi < 0)\n+\t\t\tret = qca8k_read(priv, reg + 4, (u32 *)&hi);\n+\t\t\tif (ret < 0)\n \t\t\t\tcontinue;\n \t\t}\n \n@@ -1459,7 +1448,7 @@ qca8k_set_mac_eee(struct dsa_switch *ds,\n \tint ret;\n \n \tmutex_lock(&priv->reg_mutex);\n-\treg = qca8k_read(priv, QCA8K_REG_EEE_CTRL);\n+\tret = qca8k_read(priv, QCA8K_REG_EEE_CTRL, &reg);\n \tif (reg < 0) {\n \t\tret = reg;\n \t\tgoto exit;\n@@ -1802,14 +1791,15 @@ static int qca8k_read_switch_id(struct q\n \tconst struct qca8k_match_data *data;\n \tu32 val;\n \tu8 id;\n+\tint ret;\n \n \t/* get the switches ID from the compatible */\n \tdata = of_device_get_match_data(priv->dev);\n \tif (!data)\n \t\treturn -ENODEV;\n \n-\tval = qca8k_read(priv, QCA8K_REG_MASK_CTRL);\n-\tif (val < 0)\n+\tret = qca8k_read(priv, QCA8K_REG_MASK_CTRL, &val);\n+\tif (ret < 0)\n \t\treturn -ENODEV;\n \n \tid = QCA8K_MASK_CTRL_DEVICE_ID(val & QCA8K_MASK_CTRL_DEVICE_ID_MASK);\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/737-v5.14-02-net-dsa-qca8k-add-missing-check-return-value-in-qca8.patch",
    "content": "From 9fe99de01440d9ede74d447ac76e9c445d8daae9 Mon Sep 17 00:00:00 2001\nFrom: Yang Yingliang <yangyingliang@huawei.com>\nDate: Sat, 29 May 2021 11:04:39 +0800\nSubject: [PATCH] net: dsa: qca8k: add missing check return value in\n qca8k_phylink_mac_config()\n\nNow we can check qca8k_read() return value correctly, so if\nit fails, we need return directly.\n\nSigned-off-by: Yang Yingliang <yangyingliang@huawei.com>\nSigned-off-by: Jakub Kicinski <kuba@kernel.org>\n---\n drivers/net/dsa/qca8k.c | 9 +++++++--\n 1 file changed, 7 insertions(+), 2 deletions(-)\n\n--- a/drivers/net/dsa/qca8k.c\n+++ b/drivers/net/dsa/qca8k.c\n@@ -1128,6 +1128,7 @@ qca8k_phylink_mac_config(struct dsa_swit\n {\n \tstruct qca8k_priv *priv = ds->priv;\n \tu32 reg, val;\n+\tint ret;\n \n \tswitch (port) {\n \tcase 0: /* 1st CPU port */\n@@ -1198,7 +1199,9 @@ qca8k_phylink_mac_config(struct dsa_swit\n \t\tqca8k_write(priv, reg, QCA8K_PORT_PAD_SGMII_EN);\n \n \t\t/* Enable/disable SerDes auto-negotiation as necessary */\n-\t\tqca8k_read(priv, QCA8K_REG_PWS, &val);\n+\t\tret = qca8k_read(priv, QCA8K_REG_PWS, &val);\n+\t\tif (ret)\n+\t\t\treturn;\n \t\tif (phylink_autoneg_inband(mode))\n \t\t\tval &= ~QCA8K_PWS_SERDES_AEN_DIS;\n \t\telse\n@@ -1206,7 +1209,9 @@ qca8k_phylink_mac_config(struct dsa_swit\n \t\tqca8k_write(priv, QCA8K_REG_PWS, val);\n \n \t\t/* Configure the SGMII parameters */\n-\t\tqca8k_read(priv, QCA8K_REG_SGMII_CTRL, &val);\n+\t\tret = qca8k_read(priv, QCA8K_REG_SGMII_CTRL, &val);\n+\t\tif (ret)\n+\t\t\treturn;\n \n \t\tval |= QCA8K_SGMII_EN_PLL | QCA8K_SGMII_EN_RX |\n \t\t\tQCA8K_SGMII_EN_TX | QCA8K_SGMII_EN_SD;\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/738-v5.14-01-net-dsa-qca8k-fix-an-endian-bug-in-qca8k-get-ethtool.patch",
    "content": "From aa3d020b22cb844ab7bdbb9e5d861a64666e2b74 Mon Sep 17 00:00:00 2001\nFrom: Dan Carpenter <dan.carpenter@oracle.com>\nDate: Wed, 9 Jun 2021 12:52:12 +0300\nSubject: [PATCH] net: dsa: qca8k: fix an endian bug in\n qca8k_get_ethtool_stats()\n\nThe \"hi\" variable is a u64 but the qca8k_read() writes to the top 32\nbits of it.  That will work on little endian systems but it's a bit\nsubtle.  It's cleaner to make declare \"hi\" as a u32.  We will still need\nto cast it when we shift it later on in the function but that's fine.\n\nFixes: 7c9896e37807 (\"net: dsa: qca8k: check return value of read functions correctly\")\nSigned-off-by: Dan Carpenter <dan.carpenter@oracle.com>\nReviewed-by: Vladimir Oltean <olteanv@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/dsa/qca8k.c | 6 +++---\n 1 file changed, 3 insertions(+), 3 deletions(-)\n\n--- a/drivers/net/dsa/qca8k.c\n+++ b/drivers/net/dsa/qca8k.c\n@@ -1412,7 +1412,7 @@ qca8k_get_ethtool_stats(struct dsa_switc\n \tstruct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;\n \tconst struct qca8k_mib_desc *mib;\n \tu32 reg, i, val;\n-\tu64 hi = 0;\n+\tu32 hi = 0;\n \tint ret;\n \n \tfor (i = 0; i < ARRAY_SIZE(ar8327_mib); i++) {\n@@ -1424,14 +1424,14 @@ qca8k_get_ethtool_stats(struct dsa_switc\n \t\t\tcontinue;\n \n \t\tif (mib->size == 2) {\n-\t\t\tret = qca8k_read(priv, reg + 4, (u32 *)&hi);\n+\t\t\tret = qca8k_read(priv, reg + 4, &hi);\n \t\t\tif (ret < 0)\n \t\t\t\tcontinue;\n \t\t}\n \n \t\tdata[i] = val;\n \t\tif (mib->size == 2)\n-\t\t\tdata[i] |= hi << 32;\n+\t\t\tdata[i] |= (u64)hi << 32;\n \t}\n }\n \n"
  },
  {
    "path": "target/linux/generic/backport-5.10/738-v5.14-02-net-dsa-qca8k-check-the-correct-variable-in-qca8k-se.patch",
    "content": "From 3d0167f2a627528032821cdeb78b4eab0510460f Mon Sep 17 00:00:00 2001\nFrom: Dan Carpenter <dan.carpenter@oracle.com>\nDate: Wed, 9 Jun 2021 12:53:03 +0300\nSubject: [PATCH] net: dsa: qca8k: check the correct variable in\n qca8k_set_mac_eee()\n\nThis code check \"reg\" but \"ret\" was intended so the error handling will\nnever trigger.\n\nFixes: 7c9896e37807 (\"net: dsa: qca8k: check return value of read functions correctly\")\nSigned-off-by: Dan Carpenter <dan.carpenter@oracle.com>\nReviewed-by: Vladimir Oltean <olteanv@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/dsa/qca8k.c | 4 +---\n 1 file changed, 1 insertion(+), 3 deletions(-)\n\n--- a/drivers/net/dsa/qca8k.c\n+++ b/drivers/net/dsa/qca8k.c\n@@ -1454,10 +1454,8 @@ qca8k_set_mac_eee(struct dsa_switch *ds,\n \n \tmutex_lock(&priv->reg_mutex);\n \tret = qca8k_read(priv, QCA8K_REG_EEE_CTRL, &reg);\n-\tif (reg < 0) {\n-\t\tret = reg;\n+\tif (ret < 0)\n \t\tgoto exit;\n-\t}\n \n \tif (eee->eee_enabled)\n \t\treg |= lpi_en;\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/739-v5.15-net-dsa-qca8k-fix-kernel-panic-with-legacy-mdio-mapping.patch",
    "content": "From ce062a0adbfe933b1932235fdfd874c4c91d1bb0 Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Sat, 11 Sep 2021 17:50:09 +0200\nSubject: net: dsa: qca8k: fix kernel panic with legacy mdio mapping\n\nWhen the mdio legacy mapping is used the mii_bus priv registered by DSA\nrefer to the dsa switch struct instead of the qca8k_priv struct and\ncauses a kernel panic. Create dedicated function when the internal\ndedicated mdio driver is used to properly handle the 2 different\nimplementation.\n\nFixes: 759bafb8a322 (\"net: dsa: qca8k: add support for internal phy and internal mdio\")\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/dsa/qca8k.c | 30 ++++++++++++++++++++++--------\n 1 file changed, 22 insertions(+), 8 deletions(-)\n\n--- a/drivers/net/dsa/qca8k.c\n+++ b/drivers/net/dsa/qca8k.c\n@@ -643,10 +643,8 @@ qca8k_mdio_busy_wait(struct mii_bus *bus\n }\n \n static int\n-qca8k_mdio_write(struct mii_bus *salve_bus, int phy, int regnum, u16 data)\n+qca8k_mdio_write(struct mii_bus *bus, int phy, int regnum, u16 data)\n {\n-\tstruct qca8k_priv *priv = salve_bus->priv;\n-\tstruct mii_bus *bus = priv->bus;\n \tu16 r1, r2, page;\n \tu32 val;\n \tint ret;\n@@ -682,10 +680,8 @@ exit:\n }\n \n static int\n-qca8k_mdio_read(struct mii_bus *salve_bus, int phy, int regnum)\n+qca8k_mdio_read(struct mii_bus *bus, int phy, int regnum)\n {\n-\tstruct qca8k_priv *priv = salve_bus->priv;\n-\tstruct mii_bus *bus = priv->bus;\n \tu16 r1, r2, page;\n \tu32 val;\n \tint ret;\n@@ -727,6 +723,24 @@ exit:\n }\n \n static int\n+qca8k_internal_mdio_write(struct mii_bus *slave_bus, int phy, int regnum, u16 data)\n+{\n+\tstruct qca8k_priv *priv = slave_bus->priv;\n+\tstruct mii_bus *bus = priv->bus;\n+\n+\treturn qca8k_mdio_write(bus, phy, regnum, data);\n+}\n+\n+static int\n+qca8k_internal_mdio_read(struct mii_bus *slave_bus, int phy, int regnum)\n+{\n+\tstruct qca8k_priv *priv = slave_bus->priv;\n+\tstruct mii_bus *bus = priv->bus;\n+\n+\treturn qca8k_mdio_read(bus, phy, regnum);\n+}\n+\n+static int\n qca8k_phy_write(struct dsa_switch *ds, int port, int regnum, u16 data)\n {\n \tstruct qca8k_priv *priv = ds->priv;\n@@ -775,8 +789,8 @@ qca8k_mdio_register(struct qca8k_priv *p\n \n \tbus->priv = (void *)priv;\n \tbus->name = \"qca8k slave mii\";\n-\tbus->read = qca8k_mdio_read;\n-\tbus->write = qca8k_mdio_write;\n+\tbus->read = qca8k_internal_mdio_read;\n+\tbus->write = qca8k_internal_mdio_write;\n \tsnprintf(bus->id, MII_BUS_ID_SIZE, \"qca8k-%d\",\n \t\t ds->index);\n \n"
  },
  {
    "path": "target/linux/generic/backport-5.10/740-v5.13-0001-net-dsa-b53-Add-debug-prints-in-b53_vlan_enable.patch",
    "content": "From ee47ed08d75e8f16b3cf882061ee19c2ea19dd6c Mon Sep 17 00:00:00 2001\nFrom: Florian Fainelli <f.fainelli@gmail.com>\nDate: Wed, 10 Mar 2021 10:52:26 -0800\nSubject: [PATCH] net: dsa: b53: Add debug prints in b53_vlan_enable()\n\nHaving dynamic debug prints in b53_vlan_enable() has been helpful to\nuncover a recent but update the function to indicate the port being\nconfigured (or -1 for initial setup) and include the global VLAN enabled\nand VLAN filtering enable status.\n\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\nReviewed-by: Andrew Lunn <andrew@lunn.ch>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/dsa/b53/b53_common.c | 11 +++++++----\n 1 file changed, 7 insertions(+), 4 deletions(-)\n\n--- a/drivers/net/dsa/b53/b53_common.c\n+++ b/drivers/net/dsa/b53/b53_common.c\n@@ -349,7 +349,7 @@ static void b53_set_forwarding(struct b5\n \tb53_write8(dev, B53_CTRL_PAGE, B53_IP_MULTICAST_CTRL, mgmt);\n }\n \n-static void b53_enable_vlan(struct b53_device *dev, bool enable,\n+static void b53_enable_vlan(struct b53_device *dev, int port, bool enable,\n \t\t\t    bool enable_filtering)\n {\n \tu8 mgmt, vc0, vc1, vc4 = 0, vc5;\n@@ -431,6 +431,9 @@ static void b53_enable_vlan(struct b53_d\n \tb53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);\n \n \tdev->vlan_enabled = enable;\n+\n+\tdev_dbg(dev->dev, \"Port %d VLAN enabled: %d, filtering: %d\\n\",\n+\t\tport, enable, enable_filtering);\n }\n \n static int b53_set_jumbo(struct b53_device *dev, bool enable, bool allow_10_100)\n@@ -708,7 +711,7 @@ int b53_configure_vlan(struct dsa_switch\n \t\tb53_do_vlan_op(dev, VTA_CMD_CLEAR);\n \t}\n \n-\tb53_enable_vlan(dev, dev->vlan_enabled, ds->vlan_filtering);\n+\tb53_enable_vlan(dev, -1, dev->vlan_enabled, ds->vlan_filtering);\n \n \tb53_for_each_port(dev, i)\n \t\tb53_write16(dev, B53_VLAN_PAGE,\n@@ -1390,7 +1393,7 @@ int b53_vlan_filtering(struct dsa_switch\n \tif (switchdev_trans_ph_prepare(trans))\n \t\treturn 0;\n \n-\tb53_enable_vlan(dev, dev->vlan_enabled, vlan_filtering);\n+\tb53_enable_vlan(dev, port, dev->vlan_enabled, vlan_filtering);\n \n \treturn 0;\n }\n@@ -1415,7 +1418,7 @@ int b53_vlan_prepare(struct dsa_switch *\n \tif (vlan->vid_end >= dev->num_vlans)\n \t\treturn -ERANGE;\n \n-\tb53_enable_vlan(dev, true, ds->vlan_filtering);\n+\tb53_enable_vlan(dev, port, true, ds->vlan_filtering);\n \n \treturn 0;\n }\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/740-v5.13-0002-net-dsa-b53-spi-allow-device-tree-probing.patch",
    "content": "From 6d16eadab6db0c1d61e59fee7ed1ecc2d10269be Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com>\nDate: Mon, 15 Mar 2021 15:14:23 +0100\nSubject: [PATCH] net: dsa: b53: spi: allow device tree probing\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nAdd missing of_match_table to allow device tree probing.\n\nSigned-off-by: Álvaro Fernández Rojas <noltari@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/dsa/b53/b53_spi.c | 13 +++++++++++++\n 1 file changed, 13 insertions(+)\n\n--- a/drivers/net/dsa/b53/b53_spi.c\n+++ b/drivers/net/dsa/b53/b53_spi.c\n@@ -324,9 +324,22 @@ static int b53_spi_remove(struct spi_dev\n \treturn 0;\n }\n \n+static const struct of_device_id b53_spi_of_match[] = {\n+\t{ .compatible = \"brcm,bcm5325\" },\n+\t{ .compatible = \"brcm,bcm5365\" },\n+\t{ .compatible = \"brcm,bcm5395\" },\n+\t{ .compatible = \"brcm,bcm5397\" },\n+\t{ .compatible = \"brcm,bcm5398\" },\n+\t{ .compatible = \"brcm,bcm53115\" },\n+\t{ .compatible = \"brcm,bcm53125\" },\n+\t{ .compatible = \"brcm,bcm53128\" },\n+\t{ /* sentinel */ }\n+};\n+\n static struct spi_driver b53_spi_driver = {\n \t.driver = {\n \t\t.name\t= \"b53-switch\",\n+\t\t.of_match_table = b53_spi_of_match,\n \t},\n \t.probe\t= b53_spi_probe,\n \t.remove\t= b53_spi_remove,\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/740-v5.13-0003-net-dsa-b53-relax-is63xx-condition.patch",
    "content": "From ad426d7d966b525b73ed5a1842dd830312bbba71 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com>\nDate: Wed, 17 Mar 2021 09:42:01 +0100\nSubject: [PATCH] net: dsa: b53: relax is63xx() condition\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nBCM63xx switches are present on bcm63xx and bmips devices.\n\nSigned-off-by: Álvaro Fernández Rojas <noltari@gmail.com>\nAcked-by: Florian Fainelli <f.fainelli@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/dsa/b53/b53_priv.h | 4 ----\n 1 file changed, 4 deletions(-)\n\n--- a/drivers/net/dsa/b53/b53_priv.h\n+++ b/drivers/net/dsa/b53/b53_priv.h\n@@ -186,11 +186,7 @@ static inline int is531x5(struct b53_dev\n \n static inline int is63xx(struct b53_device *dev)\n {\n-#ifdef CONFIG_BCM63XX\n \treturn dev->chip_id == BCM63XX_DEVICE_ID;\n-#else\n-\treturn 0;\n-#endif\n }\n \n static inline int is5301x(struct b53_device *dev)\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/740-v5.13-0004-net-dsa-tag_brcm-add-support-for-legacy-tags.patch",
    "content": "From 964dbf186eaa84d409c359ddf09c827a3fbe8228 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com>\nDate: Wed, 17 Mar 2021 11:29:26 +0100\nSubject: [PATCH] net: dsa: tag_brcm: add support for legacy tags\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nAdd support for legacy Broadcom tags, which are similar to DSA_TAG_PROTO_BRCM.\nThese tags are used on BCM5325, BCM5365 and BCM63xx switches.\n\nSigned-off-by: Álvaro Fernández Rojas <noltari@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n include/net/dsa.h  |   2 +\n net/dsa/Kconfig    |   7 +++\n net/dsa/tag_brcm.c | 107 +++++++++++++++++++++++++++++++++++++++++++--\n 3 files changed, 113 insertions(+), 3 deletions(-)\n\n--- a/include/net/dsa.h\n+++ b/include/net/dsa.h\n@@ -45,10 +45,12 @@ struct phylink_link_state;\n #define DSA_TAG_PROTO_OCELOT_VALUE\t\t15\n #define DSA_TAG_PROTO_AR9331_VALUE\t\t16\n #define DSA_TAG_PROTO_RTL4_A_VALUE\t\t17\n+#define DSA_TAG_PROTO_BRCM_LEGACY_VALUE\t\t22\n \n enum dsa_tag_protocol {\n \tDSA_TAG_PROTO_NONE\t\t= DSA_TAG_PROTO_NONE_VALUE,\n \tDSA_TAG_PROTO_BRCM\t\t= DSA_TAG_PROTO_BRCM_VALUE,\n+\tDSA_TAG_PROTO_BRCM_LEGACY\t= DSA_TAG_PROTO_BRCM_LEGACY_VALUE,\n \tDSA_TAG_PROTO_BRCM_PREPEND\t= DSA_TAG_PROTO_BRCM_PREPEND_VALUE,\n \tDSA_TAG_PROTO_DSA\t\t= DSA_TAG_PROTO_DSA_VALUE,\n \tDSA_TAG_PROTO_EDSA\t\t= DSA_TAG_PROTO_EDSA_VALUE,\n--- a/net/dsa/Kconfig\n+++ b/net/dsa/Kconfig\n@@ -47,6 +47,13 @@ config NET_DSA_TAG_BRCM\n \t  Say Y if you want to enable support for tagging frames for the\n \t  Broadcom switches which place the tag after the MAC source address.\n \n+config NET_DSA_TAG_BRCM_LEGACY\n+\ttristate \"Tag driver for Broadcom legacy switches using in-frame headers\"\n+\tselect NET_DSA_TAG_BRCM_COMMON\n+\thelp\n+\t  Say Y if you want to enable support for tagging frames for the\n+\t  Broadcom legacy switches which place the tag after the MAC source\n+\t  address.\n \n config NET_DSA_TAG_BRCM_PREPEND\n \ttristate \"Tag driver for Broadcom switches using prepended headers\"\n--- a/net/dsa/tag_brcm.c\n+++ b/net/dsa/tag_brcm.c\n@@ -11,9 +11,26 @@\n \n #include \"dsa_priv.h\"\n \n-/* This tag length is 4 bytes, older ones were 6 bytes, we do not\n- * handle them\n- */\n+/* Legacy Broadcom tag (6 bytes) */\n+#define BRCM_LEG_TAG_LEN\t6\n+\n+/* Type fields */\n+/* 1st byte in the tag */\n+#define BRCM_LEG_TYPE_HI\t0x88\n+/* 2nd byte in the tag */\n+#define BRCM_LEG_TYPE_LO\t0x74\n+\n+/* Tag fields */\n+/* 3rd byte in the tag */\n+#define BRCM_LEG_UNICAST\t(0 << 5)\n+#define BRCM_LEG_MULTICAST\t(1 << 5)\n+#define BRCM_LEG_EGRESS\t\t(2 << 5)\n+#define BRCM_LEG_INGRESS\t(3 << 5)\n+\n+/* 6th byte in the tag */\n+#define BRCM_LEG_PORT_ID\t(0xf)\n+\n+/* Newer Broadcom tag (4 bytes) */\n #define BRCM_TAG_LEN\t4\n \n /* Tag is constructed and desconstructed using byte by byte access\n@@ -194,6 +211,87 @@ DSA_TAG_DRIVER(brcm_netdev_ops);\n MODULE_ALIAS_DSA_TAG_DRIVER(DSA_TAG_PROTO_BRCM);\n #endif\n \n+#if IS_ENABLED(CONFIG_NET_DSA_TAG_BRCM_LEGACY)\n+static struct sk_buff *brcm_leg_tag_xmit(struct sk_buff *skb,\n+\t\t\t\t\t struct net_device *dev)\n+{\n+\tstruct dsa_port *dp = dsa_slave_to_port(dev);\n+\tu8 *brcm_tag;\n+\n+\t/* The Ethernet switch we are interfaced with needs packets to be at\n+\t * least 64 bytes (including FCS) otherwise they will be discarded when\n+\t * they enter the switch port logic. When Broadcom tags are enabled, we\n+\t * need to make sure that packets are at least 70 bytes\n+\t * (including FCS and tag) because the length verification is done after\n+\t * the Broadcom tag is stripped off the ingress packet.\n+\t *\n+\t * Let dsa_slave_xmit() free the SKB\n+\t */\n+\tif (__skb_put_padto(skb, ETH_ZLEN + BRCM_LEG_TAG_LEN, false))\n+\t\treturn NULL;\n+\n+\tskb_push(skb, BRCM_LEG_TAG_LEN);\n+\n+\tmemmove(skb->data, skb->data + BRCM_LEG_TAG_LEN, 2 * ETH_ALEN);\n+\n+\tbrcm_tag = skb->data + 2 * ETH_ALEN;\n+\n+\t/* Broadcom tag type */\n+\tbrcm_tag[0] = BRCM_LEG_TYPE_HI;\n+\tbrcm_tag[1] = BRCM_LEG_TYPE_LO;\n+\n+\t/* Broadcom tag value */\n+\tbrcm_tag[2] = BRCM_LEG_EGRESS;\n+\tbrcm_tag[3] = 0;\n+\tbrcm_tag[4] = 0;\n+\tbrcm_tag[5] = dp->index & BRCM_LEG_PORT_ID;\n+\n+\treturn skb;\n+}\n+\n+static struct sk_buff *brcm_leg_tag_rcv(struct sk_buff *skb,\n+\t\t\t\t\tstruct net_device *dev,\n+\t\t\t\t\tstruct packet_type *pt)\n+{\n+\tint source_port;\n+\tu8 *brcm_tag;\n+\n+\tif (unlikely(!pskb_may_pull(skb, BRCM_LEG_PORT_ID)))\n+\t\treturn NULL;\n+\n+\tbrcm_tag = skb->data - 2;\n+\n+\tsource_port = brcm_tag[5] & BRCM_LEG_PORT_ID;\n+\n+\tskb->dev = dsa_master_find_slave(dev, 0, source_port);\n+\tif (!skb->dev)\n+\t\treturn NULL;\n+\n+\t/* Remove Broadcom tag and update checksum */\n+\tskb_pull_rcsum(skb, BRCM_LEG_TAG_LEN);\n+\n+\tskb->offload_fwd_mark = 1;\n+\n+\t/* Move the Ethernet DA and SA */\n+\tmemmove(skb->data - ETH_HLEN,\n+\t\tskb->data - ETH_HLEN - BRCM_LEG_TAG_LEN,\n+\t\t2 * ETH_ALEN);\n+\n+\treturn skb;\n+}\n+\n+static const struct dsa_device_ops brcm_legacy_netdev_ops = {\n+\t.name = \"brcm-legacy\",\n+\t.proto = DSA_TAG_PROTO_BRCM_LEGACY,\n+\t.xmit = brcm_leg_tag_xmit,\n+\t.rcv = brcm_leg_tag_rcv,\n+\t.overhead = BRCM_LEG_TAG_LEN,\n+};\n+\n+DSA_TAG_DRIVER(brcm_legacy_netdev_ops);\n+MODULE_ALIAS_DSA_TAG_DRIVER(DSA_TAG_PROTO_BRCM_LEGACY);\n+#endif /* CONFIG_NET_DSA_TAG_BRCM_LEGACY */\n+\n #if IS_ENABLED(CONFIG_NET_DSA_TAG_BRCM_PREPEND)\n static struct sk_buff *brcm_tag_xmit_prepend(struct sk_buff *skb,\n \t\t\t\t\t     struct net_device *dev)\n@@ -226,6 +324,9 @@ static struct dsa_tag_driver *dsa_tag_dr\n #if IS_ENABLED(CONFIG_NET_DSA_TAG_BRCM)\n \t&DSA_TAG_DRIVER_NAME(brcm_netdev_ops),\n #endif\n+#if IS_ENABLED(CONFIG_NET_DSA_TAG_BRCM_LEGACY)\n+\t&DSA_TAG_DRIVER_NAME(brcm_legacy_netdev_ops),\n+#endif\n #if IS_ENABLED(CONFIG_NET_DSA_TAG_BRCM_PREPEND)\n \t&DSA_TAG_DRIVER_NAME(brcm_prepend_netdev_ops),\n #endif\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/740-v5.13-0005-net-dsa-b53-support-legacy-tags.patch",
    "content": "From 46c5176c586c81306bf9e7024c13b95da775490f Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com>\nDate: Wed, 17 Mar 2021 11:29:27 +0100\nSubject: [PATCH] net: dsa: b53: support legacy tags\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nThese tags are used on BCM5325, BCM5365 and BCM63xx switches.\n\nSigned-off-by: Álvaro Fernández Rojas <noltari@gmail.com>\nAcked-by: Florian Fainelli <f.fainelli@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/dsa/b53/Kconfig      |  1 +\n drivers/net/dsa/b53/b53_common.c | 12 +++++++-----\n 2 files changed, 8 insertions(+), 5 deletions(-)\n\n--- a/drivers/net/dsa/b53/Kconfig\n+++ b/drivers/net/dsa/b53/Kconfig\n@@ -3,6 +3,7 @@ menuconfig B53\n \ttristate \"Broadcom BCM53xx managed switch support\"\n \tdepends on NET_DSA\n \tselect NET_DSA_TAG_BRCM\n+\tselect NET_DSA_TAG_BRCM_LEGACY\n \tselect NET_DSA_TAG_BRCM_PREPEND\n \thelp\n \t  This driver adds support for Broadcom managed switch chips. It supports\n--- a/drivers/net/dsa/b53/b53_common.c\n+++ b/drivers/net/dsa/b53/b53_common.c\n@@ -2024,15 +2024,17 @@ enum dsa_tag_protocol b53_get_tag_protoc\n {\n \tstruct b53_device *dev = ds->priv;\n \n-\t/* Older models (5325, 5365) support a different tag format that we do\n-\t * not support in net/dsa/tag_brcm.c yet.\n-\t */\n-\tif (is5325(dev) || is5365(dev) ||\n-\t    !b53_can_enable_brcm_tags(ds, port, mprot)) {\n+\tif (!b53_can_enable_brcm_tags(ds, port, mprot)) {\n \t\tdev->tag_protocol = DSA_TAG_PROTO_NONE;\n \t\tgoto out;\n \t}\n \n+\t/* Older models require a different 6 byte tag */\n+\tif (is5325(dev) || is5365(dev) || is63xx(dev)) {\n+\t\tdev->tag_protocol = DSA_TAG_PROTO_BRCM_LEGACY;\n+\t\tgoto out;\n+\t}\n+\n \t/* Broadcom BCM58xx chips have a flow accelerator on Port 8\n \t * which requires us to use the prepended Broadcom tag type\n \t */\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/740-v5.13-0006-net-dsa-b53-mmap-Add-device-tree-support.patch",
    "content": "From a5538a777b73b35750ed1ffff8c1ef539e861624 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com>\nDate: Wed, 17 Mar 2021 10:23:17 +0100\nSubject: [PATCH] net: dsa: b53: mmap: Add device tree support\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nAdd device tree support to b53_mmap.c while keeping platform devices support.\n\nSigned-off-by: Álvaro Fernández Rojas <noltari@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/dsa/b53/b53_mmap.c | 55 ++++++++++++++++++++++++++++++++++\n 1 file changed, 55 insertions(+)\n\n--- a/drivers/net/dsa/b53/b53_mmap.c\n+++ b/drivers/net/dsa/b53/b53_mmap.c\n@@ -16,6 +16,7 @@\n  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n  */\n \n+#include <linux/bits.h>\n #include <linux/kernel.h>\n #include <linux/module.h>\n #include <linux/io.h>\n@@ -228,11 +229,65 @@ static const struct b53_io_ops b53_mmap_\n \t.write64 = b53_mmap_write64,\n };\n \n+static int b53_mmap_probe_of(struct platform_device *pdev,\n+\t\t\t     struct b53_platform_data **ppdata)\n+{\n+\tstruct device_node *np = pdev->dev.of_node;\n+\tstruct device_node *of_ports, *of_port;\n+\tstruct device *dev = &pdev->dev;\n+\tstruct b53_platform_data *pdata;\n+\tvoid __iomem *mem;\n+\n+\tmem = devm_platform_ioremap_resource(pdev, 0);\n+\tif (IS_ERR(mem))\n+\t\treturn PTR_ERR(mem);\n+\n+\tpdata = devm_kzalloc(dev, sizeof(struct b53_platform_data),\n+\t\t\t     GFP_KERNEL);\n+\tif (!pdata)\n+\t\treturn -ENOMEM;\n+\n+\tpdata->regs = mem;\n+\tpdata->chip_id = BCM63XX_DEVICE_ID;\n+\tpdata->big_endian = of_property_read_bool(np, \"big-endian\");\n+\n+\tof_ports = of_get_child_by_name(np, \"ports\");\n+\tif (!of_ports) {\n+\t\tdev_err(dev, \"no ports child node found\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tfor_each_available_child_of_node(of_ports, of_port) {\n+\t\tu32 reg;\n+\n+\t\tif (of_property_read_u32(of_port, \"reg\", &reg))\n+\t\t\tcontinue;\n+\n+\t\tif (reg < B53_CPU_PORT)\n+\t\t\tpdata->enabled_ports |= BIT(reg);\n+\t}\n+\n+\tof_node_put(of_ports);\n+\t*ppdata = pdata;\n+\n+\treturn 0;\n+}\n+\n static int b53_mmap_probe(struct platform_device *pdev)\n {\n+\tstruct device_node *np = pdev->dev.of_node;\n \tstruct b53_platform_data *pdata = pdev->dev.platform_data;\n \tstruct b53_mmap_priv *priv;\n \tstruct b53_device *dev;\n+\tint ret;\n+\n+\tif (!pdata && np) {\n+\t\tret = b53_mmap_probe_of(pdev, &pdata);\n+\t\tif (ret) {\n+\t\t\tdev_err(&pdev->dev, \"OF probe error\\n\");\n+\t\t\treturn ret;\n+\t\t}\n+\t}\n \n \tif (!pdata)\n \t\treturn -EINVAL;\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/740-v5.13-0007-net-dsa-b53-spi-add-missing-MODULE_DEVICE_TABLE.patch",
    "content": "From 866f1577ba69bde2b9f36c300f603596c7d84a62 Mon Sep 17 00:00:00 2001\nFrom: Qinglang Miao <miaoqinglang@huawei.com>\nDate: Thu, 25 Mar 2021 17:19:54 +0800\nSubject: [PATCH] net: dsa: b53: spi: add missing MODULE_DEVICE_TABLE\n\nThis patch adds missing MODULE_DEVICE_TABLE definition which generates\ncorrect modalias for automatic loading of this driver when it is built\nas an external module.\n\nReported-by: Hulk Robot <hulkci@huawei.com>\nSigned-off-by: Qinglang Miao <miaoqinglang@huawei.com>\nAcked-by: Florian Fainelli <f.fainelli@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/dsa/b53/b53_spi.c | 1 +\n 1 file changed, 1 insertion(+)\n\n--- a/drivers/net/dsa/b53/b53_spi.c\n+++ b/drivers/net/dsa/b53/b53_spi.c\n@@ -335,6 +335,7 @@ static const struct of_device_id b53_spi\n \t{ .compatible = \"brcm,bcm53128\" },\n \t{ /* sentinel */ }\n };\n+MODULE_DEVICE_TABLE(of, b53_spi_of_match);\n \n static struct spi_driver b53_spi_driver = {\n \t.driver = {\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/741-v5.14-0001-net-dsa-b53-Do-not-force-CPU-to-be-always-tagged.patch",
    "content": "From 2c32a3d3c233b855943677609fe388f82b1f0975 Mon Sep 17 00:00:00 2001\nFrom: Florian Fainelli <f.fainelli@gmail.com>\nDate: Tue, 8 Jun 2021 14:22:04 -0700\nSubject: [PATCH] net: dsa: b53: Do not force CPU to be always tagged\n\nCommit ca8931948344 (\"net: dsa: b53: Keep CPU port as tagged in all\nVLANs\") forced the CPU port to be always tagged in any VLAN membership.\nThis was necessary back then because we did not support Broadcom tags\nfor all configurations so the only way to differentiate tagged and\nuntagged traffic while DSA_TAG_PROTO_NONE was used was to force the CPU\nport into being always tagged.\n\nWith most configurations enabling Broadcom tags, especially after\n8fab459e69ab (\"net: dsa: b53: Enable Broadcom tags for 531x5/539x\nfamilies\") we do not need to apply this unconditional force tagging of\nthe CPU port in all VLANs.\n\nA helper function is introduced to faciliate the encapsulation of the\nspecific condition requiring the CPU port to be tagged in all VLANs and\nthe dsa_switch_ops::untag_bridge_pvid boolean is moved to when\ndsa_switch_ops::setup is called when we have already determined the\ntagging protocol we will be using.\n\nReported-by: Matthew Hagan <mnhagan88@gmail.com>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\nReviewed-by: Vladimir Oltean <olteanv@gmail.com>\nTested-by: Matthew Hagan <mnhagan88@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/dsa/b53/b53_common.c | 17 ++++++++++++++---\n 1 file changed, 14 insertions(+), 3 deletions(-)\n\n--- a/drivers/net/dsa/b53/b53_common.c\n+++ b/drivers/net/dsa/b53/b53_common.c\n@@ -1049,6 +1049,11 @@ static int b53_setup(struct dsa_switch *\n \tunsigned int port;\n \tint ret;\n \n+\t/* Request bridge PVID untagged when DSA_TAG_PROTO_NONE is set\n+\t * which forces the CPU port to be tagged in all VLANs.\n+\t */\n+\tds->untag_bridge_pvid = dev->tag_protocol == DSA_TAG_PROTO_NONE;\n+\n \tret = b53_reset_switch(dev);\n \tif (ret) {\n \t\tdev_err(ds->dev, \"failed to reset switch\\n\");\n@@ -1423,6 +1428,13 @@ int b53_vlan_prepare(struct dsa_switch *\n \treturn 0;\n }\n EXPORT_SYMBOL(b53_vlan_prepare);\n+ \n+static bool b53_vlan_port_needs_forced_tagged(struct dsa_switch *ds, int port)\n+{\n+\tstruct b53_device *dev = ds->priv;\n+\n+\treturn dev->tag_protocol == DSA_TAG_PROTO_NONE && dsa_is_cpu_port(ds, port);\n+}\n \n void b53_vlan_add(struct dsa_switch *ds, int port,\n \t\t  const struct switchdev_obj_port_vlan *vlan)\n@@ -1442,7 +1454,7 @@ void b53_vlan_add(struct dsa_switch *ds,\n \t\t\tuntagged = true;\n \n \t\tvl->members |= BIT(port);\n-\t\tif (untagged && !dsa_is_cpu_port(ds, port))\n+\t\tif (untagged && !b53_vlan_port_needs_forced_tagged(ds, port))\n \t\t\tvl->untag |= BIT(port);\n \t\telse\n \t\t\tvl->untag &= ~BIT(port);\n@@ -1480,7 +1492,7 @@ int b53_vlan_del(struct dsa_switch *ds,\n \t\tif (pvid == vid)\n \t\t\tpvid = b53_default_pvid(dev);\n \n-\t\tif (untagged && !dsa_is_cpu_port(ds, port))\n+\t\tif (untagged && !b53_vlan_port_needs_forced_tagged(ds, port))\n \t\t\tvl->untag &= ~(BIT(port));\n \n \t\tb53_set_vlan_entry(dev, vid, vl);\n@@ -2644,7 +2656,6 @@ struct b53_device *b53_switch_alloc(stru\n \tdev->ops = ops;\n \tds->ops = &b53_switch_ops;\n \tds->configure_vlan_while_not_filtering = true;\n-\tds->untag_bridge_pvid = true;\n \tdev->vlan_enabled = ds->configure_vlan_while_not_filtering;\n \t/* Let DSA handle the case were multiple bridges span the same switch\n \t * device and different VLAN awareness settings are requested, which\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/741-v5.14-0002-net-dsa-b53-remove-redundant-null-check-on-dev.patch",
    "content": "From 11b57faf951cd3a570e3d9e463fc7c41023bc8c6 Mon Sep 17 00:00:00 2001\nFrom: Colin Ian King <colin.king@canonical.com>\nDate: Tue, 15 Jun 2021 10:05:16 +0100\nSubject: [PATCH] net: dsa: b53: remove redundant null check on dev\n\nThe pointer dev can never be null, the null check is redundant\nand can be removed. Cleans up a static analysis warning that\npointer priv is dereferencing dev before dev is being null\nchecked.\n\nAddresses-Coverity: (\"Dereference before null check\")\nSigned-off-by: Colin Ian King <colin.king@canonical.com>\nAcked-by: Florian Fainelli <f.fainelli@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/dsa/b53/b53_srab.c | 3 +--\n 1 file changed, 1 insertion(+), 2 deletions(-)\n\n--- a/drivers/net/dsa/b53/b53_srab.c\n+++ b/drivers/net/dsa/b53/b53_srab.c\n@@ -632,8 +632,7 @@ static int b53_srab_remove(struct platfo\n \tstruct b53_srab_priv *priv = dev->priv;\n \n \tb53_srab_intr_set(priv, false);\n-\tif (dev)\n-\t\tb53_switch_remove(dev);\n+\tb53_switch_remove(dev);\n \n \treturn 0;\n }\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/741-v5.14-0003-net-dsa-b53-Create-default-VLAN-entry-explicitly.patch",
    "content": "From 64a81b24487f0d2fba0f033029eec2abc7d82cee Mon Sep 17 00:00:00 2001\nFrom: Florian Fainelli <f.fainelli@gmail.com>\nDate: Mon, 21 Jun 2021 15:10:55 -0700\nSubject: [PATCH] net: dsa: b53: Create default VLAN entry explicitly\n\nIn case CONFIG_VLAN_8021Q is not set, there will be no call down to the\nb53 driver to ensure that the default PVID VLAN entry will be configured\nwith the appropriate untagged attribute towards the CPU port. We were\nimplicitly relying on dsa_slave_vlan_rx_add_vid() to do that for us,\ninstead make it explicit.\n\nReported-by: Vladimir Oltean <olteanv@gmail.com>\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\nReviewed-by: Vladimir Oltean <olteanv@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/dsa/b53/b53_common.c | 27 +++++++++++++++++++--------\n 1 file changed, 19 insertions(+), 8 deletions(-)\n\n--- a/drivers/net/dsa/b53/b53_common.c\n+++ b/drivers/net/dsa/b53/b53_common.c\n@@ -693,6 +693,13 @@ static u16 b53_default_pvid(struct b53_d\n \t\treturn 0;\n }\n \n+static bool b53_vlan_port_needs_forced_tagged(struct dsa_switch *ds, int port)\n+{\n+\tstruct b53_device *dev = ds->priv;\n+\n+\treturn dev->tag_protocol == DSA_TAG_PROTO_NONE && dsa_is_cpu_port(ds, port);\n+}\n+\n int b53_configure_vlan(struct dsa_switch *ds)\n {\n \tstruct b53_device *dev = ds->priv;\n@@ -713,9 +720,20 @@ int b53_configure_vlan(struct dsa_switch\n \n \tb53_enable_vlan(dev, -1, dev->vlan_enabled, ds->vlan_filtering);\n \n-\tb53_for_each_port(dev, i)\n+\t/* Create an untagged VLAN entry for the default PVID in case\n+\t * CONFIG_VLAN_8021Q is disabled and there are no calls to\n+\t * dsa_slave_vlan_rx_add_vid() to create the default VLAN\n+\t * entry. Do this only when the tagging protocol is not\n+\t * DSA_TAG_PROTO_NONE\n+\t */\n+\tb53_for_each_port(dev, i) {\n+\t\tv = &dev->vlans[def_vid];\n+\t\tv->members |= BIT(i);\n+\t\tif (!b53_vlan_port_needs_forced_tagged(ds, i))\n+\t\t\tv->untag = v->members;\n \t\tb53_write16(dev, B53_VLAN_PAGE,\n \t\t\t    B53_VLAN_PORT_DEF_TAG(i), def_vid);\n+\t}\n \n \t/* Upon initial call we have not set-up any VLANs, but upon\n \t * system resume, we need to restore all VLAN entries.\n@@ -1429,13 +1447,6 @@ int b53_vlan_prepare(struct dsa_switch *\n }\n EXPORT_SYMBOL(b53_vlan_prepare);\n  \n-static bool b53_vlan_port_needs_forced_tagged(struct dsa_switch *ds, int port)\n-{\n-\tstruct b53_device *dev = ds->priv;\n-\n-\treturn dev->tag_protocol == DSA_TAG_PROTO_NONE && dsa_is_cpu_port(ds, port);\n-}\n-\n void b53_vlan_add(struct dsa_switch *ds, int port,\n \t\t  const struct switchdev_obj_port_vlan *vlan)\n {\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/742-v5.16-net-phy-at803x-add-support-for-qca-8327-internal-phy.patch",
    "content": "From 0ccf8511182436183c031e8a2f740ae91a02c625 Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Tue, 14 Sep 2021 14:33:45 +0200\nSubject: net: phy: at803x: add support for qca 8327 internal phy\n\nAdd support for qca8327 internal phy needed for correct init of the\nswitch port. It does use the same qca8337 function and reg just with a\ndifferent id.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nTested-by: Rosen Penev <rosenp@gmail.com>\nTested-by: Andrew Lunn <andrew@lunn.ch>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/phy/at803x.c | 15 +++++++++++++++\n 1 file changed, 15 insertions(+)\n\n--- a/drivers/net/phy/at803x.c\n+++ b/drivers/net/phy/at803x.c\n@@ -1328,6 +1328,19 @@ static struct phy_driver at803x_driver[]\n \t.get_sset_count = at803x_get_sset_count,\n \t.get_strings = at803x_get_strings,\n \t.get_stats = at803x_get_stats,\n+}, {\n+\t/* QCA8327 */\n+\t.phy_id = QCA8327_PHY_ID,\n+\t.phy_id_mask = QCA8K_PHY_ID_MASK,\n+\t.name = \"QCA PHY 8327\",\n+\t/* PHY_GBIT_FEATURES */\n+\t.probe = at803x_probe,\n+\t.flags = PHY_IS_INTERNAL,\n+\t.config_init = qca83xx_config_init,\n+\t.soft_reset = genphy_soft_reset,\n+\t.get_sset_count = at803x_get_sset_count,\n+\t.get_strings = at803x_get_strings,\n+\t.get_stats = at803x_get_stats,\n }, };\n \n module_phy_driver(at803x_driver);\n@@ -1338,6 +1351,8 @@ static struct mdio_device_id __maybe_unu\n \t{ PHY_ID_MATCH_EXACT(ATH8032_PHY_ID) },\n \t{ PHY_ID_MATCH_EXACT(ATH8035_PHY_ID) },\n \t{ PHY_ID_MATCH_EXACT(ATH9331_PHY_ID) },\n+\t{ PHY_ID_MATCH_EXACT(QCA8337_PHY_ID) },\n+\t{ PHY_ID_MATCH_EXACT(QCA8327_PHY_ID) },\n \t{ }\n };\n \n"
  },
  {
    "path": "target/linux/generic/backport-5.10/743-v5.16-0001-net-dsa-b53-Include-all-ports-in-enabled_ports.patch",
    "content": "From 983d96a9116a328668601555d96736261d33170c Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Thu, 16 Sep 2021 14:03:51 +0200\nSubject: [PATCH] net: dsa: b53: Include all ports in \"enabled_ports\"\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nMake \"enabled_ports\" bitfield contain all available switch ports\nincluding a CPU port. This way there is no need for fixup during\ninitialization.\n\nFor BCM53010, BCM53018 and BCM53019 include also other available ports.\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nReviewed-by: Florian Fainelli <f.fainelli@gmail.com>\nTested-by: Florian Fainelli <f.fainelli@gmail.com>\nSigned-off-by: Jakub Kicinski <kuba@kernel.org>\n---\n drivers/net/dsa/b53/b53_common.c | 23 +++++++++++------------\n 1 file changed, 11 insertions(+), 12 deletions(-)\n\n--- a/drivers/net/dsa/b53/b53_common.c\n+++ b/drivers/net/dsa/b53/b53_common.c\n@@ -2288,7 +2288,7 @@ static const struct b53_chip_data b53_sw\n \t\t.chip_id = BCM5325_DEVICE_ID,\n \t\t.dev_name = \"BCM5325\",\n \t\t.vlans = 16,\n-\t\t.enabled_ports = 0x1f,\n+\t\t.enabled_ports = 0x3f,\n \t\t.arl_bins = 2,\n \t\t.arl_buckets = 1024,\n \t\t.imp_port = 5,\n@@ -2299,7 +2299,7 @@ static const struct b53_chip_data b53_sw\n \t\t.chip_id = BCM5365_DEVICE_ID,\n \t\t.dev_name = \"BCM5365\",\n \t\t.vlans = 256,\n-\t\t.enabled_ports = 0x1f,\n+\t\t.enabled_ports = 0x3f,\n \t\t.arl_bins = 2,\n \t\t.arl_buckets = 1024,\n \t\t.imp_port = 5,\n@@ -2310,7 +2310,7 @@ static const struct b53_chip_data b53_sw\n \t\t.chip_id = BCM5389_DEVICE_ID,\n \t\t.dev_name = \"BCM5389\",\n \t\t.vlans = 4096,\n-\t\t.enabled_ports = 0x1f,\n+\t\t.enabled_ports = 0x11f,\n \t\t.arl_bins = 4,\n \t\t.arl_buckets = 1024,\n \t\t.imp_port = 8,\n@@ -2324,7 +2324,7 @@ static const struct b53_chip_data b53_sw\n \t\t.chip_id = BCM5395_DEVICE_ID,\n \t\t.dev_name = \"BCM5395\",\n \t\t.vlans = 4096,\n-\t\t.enabled_ports = 0x1f,\n+\t\t.enabled_ports = 0x11f,\n \t\t.arl_bins = 4,\n \t\t.arl_buckets = 1024,\n \t\t.imp_port = 8,\n@@ -2338,7 +2338,7 @@ static const struct b53_chip_data b53_sw\n \t\t.chip_id = BCM5397_DEVICE_ID,\n \t\t.dev_name = \"BCM5397\",\n \t\t.vlans = 4096,\n-\t\t.enabled_ports = 0x1f,\n+\t\t.enabled_ports = 0x11f,\n \t\t.arl_bins = 4,\n \t\t.arl_buckets = 1024,\n \t\t.imp_port = 8,\n@@ -2352,7 +2352,7 @@ static const struct b53_chip_data b53_sw\n \t\t.chip_id = BCM5398_DEVICE_ID,\n \t\t.dev_name = \"BCM5398\",\n \t\t.vlans = 4096,\n-\t\t.enabled_ports = 0x7f,\n+\t\t.enabled_ports = 0x17f,\n \t\t.arl_bins = 4,\n \t\t.arl_buckets = 1024,\n \t\t.imp_port = 8,\n@@ -2366,7 +2366,7 @@ static const struct b53_chip_data b53_sw\n \t\t.chip_id = BCM53115_DEVICE_ID,\n \t\t.dev_name = \"BCM53115\",\n \t\t.vlans = 4096,\n-\t\t.enabled_ports = 0x1f,\n+\t\t.enabled_ports = 0x11f,\n \t\t.arl_bins = 4,\n \t\t.arl_buckets = 1024,\n \t\t.vta_regs = B53_VTA_REGS,\n@@ -2380,7 +2380,7 @@ static const struct b53_chip_data b53_sw\n \t\t.chip_id = BCM53125_DEVICE_ID,\n \t\t.dev_name = \"BCM53125\",\n \t\t.vlans = 4096,\n-\t\t.enabled_ports = 0xff,\n+\t\t.enabled_ports = 0x1ff,\n \t\t.arl_bins = 4,\n \t\t.arl_buckets = 1024,\n \t\t.imp_port = 8,\n@@ -2422,7 +2422,7 @@ static const struct b53_chip_data b53_sw\n \t\t.chip_id = BCM53010_DEVICE_ID,\n \t\t.dev_name = \"BCM53010\",\n \t\t.vlans = 4096,\n-\t\t.enabled_ports = 0x1f,\n+\t\t.enabled_ports = 0x1bf,\n \t\t.arl_bins = 4,\n \t\t.arl_buckets = 1024,\n \t\t.imp_port = 8,\n@@ -2464,7 +2464,7 @@ static const struct b53_chip_data b53_sw\n \t\t.chip_id = BCM53018_DEVICE_ID,\n \t\t.dev_name = \"BCM53018\",\n \t\t.vlans = 4096,\n-\t\t.enabled_ports = 0x1f,\n+\t\t.enabled_ports = 0x1bf,\n \t\t.arl_bins = 4,\n \t\t.arl_buckets = 1024,\n \t\t.imp_port = 8,\n@@ -2478,7 +2478,7 @@ static const struct b53_chip_data b53_sw\n \t\t.chip_id = BCM53019_DEVICE_ID,\n \t\t.dev_name = \"BCM53019\",\n \t\t.vlans = 4096,\n-\t\t.enabled_ports = 0x1f,\n+\t\t.enabled_ports = 0x1bf,\n \t\t.arl_bins = 4,\n \t\t.arl_buckets = 1024,\n \t\t.imp_port = 8,\n@@ -2605,7 +2605,6 @@ static int b53_switch_init(struct b53_de\n \t\t\tdev->cpu_port = 5;\n \t}\n \n-\tdev->enabled_ports |= BIT(dev->cpu_port);\n \tdev->num_ports = fls(dev->enabled_ports);\n \n \tdev->ds->num_ports = min_t(unsigned int, dev->num_ports, DSA_MAX_PORTS);\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/743-v5.16-0002-net-dsa-b53-Drop-BCM5301x-workaround-for-a-wrong-CPU.patch",
    "content": "From b290c6384afabbca5ae6e2af72fb1b2bc37922be Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Thu, 16 Sep 2021 14:03:52 +0200\nSubject: [PATCH] net: dsa: b53: Drop BCM5301x workaround for a wrong CPU/IMP\n port\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nOn BCM5301x port 8 requires a fixed link when used.\n\nYears ago when b53 was an OpenWrt downstream driver (with configuration\nbased on sometimes bugged NVRAM) there was a need for a fixup. In case\nof forcing fixed link for (incorrectly specified) port 5 the code had to\nactually setup port 8 link.\n\nFor upstream b53 driver with setup based on DT there is no need for that\nworkaround. In DT we have and require correct ports setup.\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nReviewed-by: Florian Fainelli <f.fainelli@gmail.com>\nTested-by: Florian Fainelli <f.fainelli@gmail.com>\nSigned-off-by: Jakub Kicinski <kuba@kernel.org>\n---\n drivers/net/dsa/b53/b53_common.c | 6 ------\n 1 file changed, 6 deletions(-)\n\n--- a/drivers/net/dsa/b53/b53_common.c\n+++ b/drivers/net/dsa/b53/b53_common.c\n@@ -1256,12 +1256,6 @@ static void b53_adjust_link(struct dsa_s\n \t\t\t\treturn;\n \t\t\t}\n \t\t}\n-\t} else if (is5301x(dev)) {\n-\t\tif (port != dev->cpu_port) {\n-\t\t\tb53_force_port_config(dev, dev->cpu_port, 2000,\n-\t\t\t\t\t      DUPLEX_FULL, true, true);\n-\t\t\tb53_force_link(dev, dev->cpu_port, 1);\n-\t\t}\n \t}\n \n \t/* Re-negotiate EEE if it was enabled already */\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/743-v5.16-0003-net-dsa-b53-Improve-flow-control-setup-on-BCM5301x.patch",
    "content": "From 3ff26b29230c54fea2353b63124c589b61953e14 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Thu, 16 Sep 2021 14:03:53 +0200\nSubject: [PATCH] net: dsa: b53: Improve flow control setup on BCM5301x\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nAccording to the Broadcom's reference driver flow control needs to be\nenabled for any CPU switch port (5, 7 or 8 - depending on which one is\nused). Current code makes it work only for the port 5. Use\ndsa_is_cpu_port() which solved that problem.\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nReviewed-by: Florian Fainelli <f.fainelli@gmail.com>\nTested-by: Florian Fainelli <f.fainelli@gmail.com>\nSigned-off-by: Jakub Kicinski <kuba@kernel.org>\n---\n drivers/net/dsa/b53/b53_common.c | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/drivers/net/dsa/b53/b53_common.c\n+++ b/drivers/net/dsa/b53/b53_common.c\n@@ -1187,7 +1187,7 @@ static void b53_adjust_link(struct dsa_s\n \t\treturn;\n \n \t/* Enable flow control on BCM5301x's CPU port */\n-\tif (is5301x(dev) && port == dev->cpu_port)\n+\tif (is5301x(dev) && dsa_is_cpu_port(ds, port))\n \t\ttx_pause = rx_pause = true;\n \n \tif (phydev->pause) {\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/743-v5.16-0004-net-dsa-b53-Drop-unused-cpu_port-field.patch",
    "content": "From 7d5af56418d7d01e43247a33b6fe6492ea871923 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Thu, 16 Sep 2021 14:03:54 +0200\nSubject: [PATCH] net: dsa: b53: Drop unused \"cpu_port\" field\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nIt's set but never used anymore.\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nReviewed-by: Florian Fainelli <f.fainelli@gmail.com>\nTested-by: Florian Fainelli <f.fainelli@gmail.com>\nSigned-off-by: Jakub Kicinski <kuba@kernel.org>\n---\n drivers/net/dsa/b53/b53_common.c | 28 ----------------------------\n drivers/net/dsa/b53/b53_priv.h   |  1 -\n 2 files changed, 29 deletions(-)\n\n--- a/drivers/net/dsa/b53/b53_common.c\n+++ b/drivers/net/dsa/b53/b53_common.c\n@@ -2286,7 +2286,6 @@ static const struct b53_chip_data b53_sw\n \t\t.arl_bins = 2,\n \t\t.arl_buckets = 1024,\n \t\t.imp_port = 5,\n-\t\t.cpu_port = B53_CPU_PORT_25,\n \t\t.duplex_reg = B53_DUPLEX_STAT_FE,\n \t},\n \t{\n@@ -2297,7 +2296,6 @@ static const struct b53_chip_data b53_sw\n \t\t.arl_bins = 2,\n \t\t.arl_buckets = 1024,\n \t\t.imp_port = 5,\n-\t\t.cpu_port = B53_CPU_PORT_25,\n \t\t.duplex_reg = B53_DUPLEX_STAT_FE,\n \t},\n \t{\n@@ -2308,7 +2306,6 @@ static const struct b53_chip_data b53_sw\n \t\t.arl_bins = 4,\n \t\t.arl_buckets = 1024,\n \t\t.imp_port = 8,\n-\t\t.cpu_port = B53_CPU_PORT,\n \t\t.vta_regs = B53_VTA_REGS,\n \t\t.duplex_reg = B53_DUPLEX_STAT_GE,\n \t\t.jumbo_pm_reg = B53_JUMBO_PORT_MASK,\n@@ -2322,7 +2319,6 @@ static const struct b53_chip_data b53_sw\n \t\t.arl_bins = 4,\n \t\t.arl_buckets = 1024,\n \t\t.imp_port = 8,\n-\t\t.cpu_port = B53_CPU_PORT,\n \t\t.vta_regs = B53_VTA_REGS,\n \t\t.duplex_reg = B53_DUPLEX_STAT_GE,\n \t\t.jumbo_pm_reg = B53_JUMBO_PORT_MASK,\n@@ -2336,7 +2332,6 @@ static const struct b53_chip_data b53_sw\n \t\t.arl_bins = 4,\n \t\t.arl_buckets = 1024,\n \t\t.imp_port = 8,\n-\t\t.cpu_port = B53_CPU_PORT,\n \t\t.vta_regs = B53_VTA_REGS_9798,\n \t\t.duplex_reg = B53_DUPLEX_STAT_GE,\n \t\t.jumbo_pm_reg = B53_JUMBO_PORT_MASK,\n@@ -2350,7 +2345,6 @@ static const struct b53_chip_data b53_sw\n \t\t.arl_bins = 4,\n \t\t.arl_buckets = 1024,\n \t\t.imp_port = 8,\n-\t\t.cpu_port = B53_CPU_PORT,\n \t\t.vta_regs = B53_VTA_REGS_9798,\n \t\t.duplex_reg = B53_DUPLEX_STAT_GE,\n \t\t.jumbo_pm_reg = B53_JUMBO_PORT_MASK,\n@@ -2365,7 +2359,6 @@ static const struct b53_chip_data b53_sw\n \t\t.arl_buckets = 1024,\n \t\t.vta_regs = B53_VTA_REGS,\n \t\t.imp_port = 8,\n-\t\t.cpu_port = B53_CPU_PORT,\n \t\t.duplex_reg = B53_DUPLEX_STAT_GE,\n \t\t.jumbo_pm_reg = B53_JUMBO_PORT_MASK,\n \t\t.jumbo_size_reg = B53_JUMBO_MAX_SIZE,\n@@ -2378,7 +2371,6 @@ static const struct b53_chip_data b53_sw\n \t\t.arl_bins = 4,\n \t\t.arl_buckets = 1024,\n \t\t.imp_port = 8,\n-\t\t.cpu_port = B53_CPU_PORT,\n \t\t.vta_regs = B53_VTA_REGS,\n \t\t.duplex_reg = B53_DUPLEX_STAT_GE,\n \t\t.jumbo_pm_reg = B53_JUMBO_PORT_MASK,\n@@ -2392,7 +2384,6 @@ static const struct b53_chip_data b53_sw\n \t\t.arl_bins = 4,\n \t\t.arl_buckets = 1024,\n \t\t.imp_port = 8,\n-\t\t.cpu_port = B53_CPU_PORT,\n \t\t.vta_regs = B53_VTA_REGS,\n \t\t.duplex_reg = B53_DUPLEX_STAT_GE,\n \t\t.jumbo_pm_reg = B53_JUMBO_PORT_MASK,\n@@ -2406,7 +2397,6 @@ static const struct b53_chip_data b53_sw\n \t\t.arl_bins = 4,\n \t\t.arl_buckets = 1024,\n \t\t.imp_port = 8,\n-\t\t.cpu_port = B53_CPU_PORT,\n \t\t.vta_regs = B53_VTA_REGS_63XX,\n \t\t.duplex_reg = B53_DUPLEX_STAT_63XX,\n \t\t.jumbo_pm_reg = B53_JUMBO_PORT_MASK_63XX,\n@@ -2420,7 +2410,6 @@ static const struct b53_chip_data b53_sw\n \t\t.arl_bins = 4,\n \t\t.arl_buckets = 1024,\n \t\t.imp_port = 8,\n-\t\t.cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */\n \t\t.vta_regs = B53_VTA_REGS,\n \t\t.duplex_reg = B53_DUPLEX_STAT_GE,\n \t\t.jumbo_pm_reg = B53_JUMBO_PORT_MASK,\n@@ -2434,7 +2423,6 @@ static const struct b53_chip_data b53_sw\n \t\t.arl_bins = 4,\n \t\t.arl_buckets = 1024,\n \t\t.imp_port = 8,\n-\t\t.cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */\n \t\t.vta_regs = B53_VTA_REGS,\n \t\t.duplex_reg = B53_DUPLEX_STAT_GE,\n \t\t.jumbo_pm_reg = B53_JUMBO_PORT_MASK,\n@@ -2448,7 +2436,6 @@ static const struct b53_chip_data b53_sw\n \t\t.arl_bins = 4,\n \t\t.arl_buckets = 1024,\n \t\t.imp_port = 8,\n-\t\t.cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */\n \t\t.vta_regs = B53_VTA_REGS,\n \t\t.duplex_reg = B53_DUPLEX_STAT_GE,\n \t\t.jumbo_pm_reg = B53_JUMBO_PORT_MASK,\n@@ -2462,7 +2449,6 @@ static const struct b53_chip_data b53_sw\n \t\t.arl_bins = 4,\n \t\t.arl_buckets = 1024,\n \t\t.imp_port = 8,\n-\t\t.cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */\n \t\t.vta_regs = B53_VTA_REGS,\n \t\t.duplex_reg = B53_DUPLEX_STAT_GE,\n \t\t.jumbo_pm_reg = B53_JUMBO_PORT_MASK,\n@@ -2476,7 +2462,6 @@ static const struct b53_chip_data b53_sw\n \t\t.arl_bins = 4,\n \t\t.arl_buckets = 1024,\n \t\t.imp_port = 8,\n-\t\t.cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */\n \t\t.vta_regs = B53_VTA_REGS,\n \t\t.duplex_reg = B53_DUPLEX_STAT_GE,\n \t\t.jumbo_pm_reg = B53_JUMBO_PORT_MASK,\n@@ -2490,7 +2475,6 @@ static const struct b53_chip_data b53_sw\n \t\t.arl_bins = 4,\n \t\t.arl_buckets = 1024,\n \t\t.imp_port = 8,\n-\t\t.cpu_port = B53_CPU_PORT,\n \t\t.vta_regs = B53_VTA_REGS,\n \t\t.duplex_reg = B53_DUPLEX_STAT_GE,\n \t\t.jumbo_pm_reg = B53_JUMBO_PORT_MASK,\n@@ -2504,7 +2488,6 @@ static const struct b53_chip_data b53_sw\n \t\t.arl_bins = 4,\n \t\t.arl_buckets = 1024,\n \t\t.imp_port = 8,\n-\t\t.cpu_port = B53_CPU_PORT,\n \t\t.vta_regs = B53_VTA_REGS,\n \t\t.duplex_reg = B53_DUPLEX_STAT_GE,\n \t\t.jumbo_pm_reg = B53_JUMBO_PORT_MASK,\n@@ -2518,7 +2501,6 @@ static const struct b53_chip_data b53_sw\n \t\t.arl_bins = 4,\n \t\t.arl_buckets = 1024,\n \t\t.imp_port = 8,\n-\t\t.cpu_port = B53_CPU_PORT,\n \t\t.vta_regs = B53_VTA_REGS,\n \t\t.duplex_reg = B53_DUPLEX_STAT_GE,\n \t\t.jumbo_pm_reg = B53_JUMBO_PORT_MASK,\n@@ -2532,7 +2514,6 @@ static const struct b53_chip_data b53_sw\n \t\t.arl_bins = 4,\n \t\t.arl_buckets = 256,\n \t\t.imp_port = 8,\n-\t\t.cpu_port = B53_CPU_PORT,\n \t\t.vta_regs = B53_VTA_REGS,\n \t\t.duplex_reg = B53_DUPLEX_STAT_GE,\n \t\t.jumbo_pm_reg = B53_JUMBO_PORT_MASK,\n@@ -2558,7 +2539,6 @@ static int b53_switch_init(struct b53_de\n \t\t\tdev->vta_regs[2] = chip->vta_regs[2];\n \t\t\tdev->jumbo_pm_reg = chip->jumbo_pm_reg;\n \t\t\tdev->imp_port = chip->imp_port;\n-\t\t\tdev->cpu_port = chip->cpu_port;\n \t\t\tdev->num_vlans = chip->vlans;\n \t\t\tdev->num_arl_bins = chip->arl_bins;\n \t\t\tdev->num_arl_buckets = chip->arl_buckets;\n@@ -2590,13 +2570,6 @@ static int b53_switch_init(struct b53_de\n \t\t\tbreak;\n #endif\n \t\t}\n-\t} else if (dev->chip_id == BCM53115_DEVICE_ID) {\n-\t\tu64 strap_value;\n-\n-\t\tb53_read48(dev, B53_STAT_PAGE, B53_STRAP_VALUE, &strap_value);\n-\t\t/* use second IMP port if GMII is enabled */\n-\t\tif (strap_value & SV_GMII_CTRL_115)\n-\t\t\tdev->cpu_port = 5;\n \t}\n \n \tdev->num_ports = fls(dev->enabled_ports);\n--- a/drivers/net/dsa/b53/b53_priv.h\n+++ b/drivers/net/dsa/b53/b53_priv.h\n@@ -123,7 +123,6 @@ struct b53_device {\n \t/* used ports mask */\n \tu16 enabled_ports;\n \tunsigned int imp_port;\n-\tunsigned int cpu_port;\n \n \t/* connect specific data */\n \tu8 current_page;\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/744-v5.15-net-dsa-don-t-set-skb-offload_fwd_mark-when-not-offl.patch",
    "content": "From bea7907837c57a0aaac009931eb14efb056dafab Mon Sep 17 00:00:00 2001\nFrom: Vladimir Oltean <vladimir.oltean@nxp.com>\nDate: Thu, 29 Jul 2021 17:56:00 +0300\nSubject: [PATCH] net: dsa: don't set skb->offload_fwd_mark when not offloading\n the bridge\n\nDSA has gained the recent ability to deal gracefully with upper\ninterfaces it cannot offload, such as the bridge, bonding or team\ndrivers. When such uppers exist, the ports are still in standalone mode\nas far as the hardware is concerned.\n\nBut when we deliver packets to the software bridge in order for that to\ndo the forwarding, there is an unpleasant surprise in that the bridge\nwill refuse to forward them. This is because we unconditionally set\nskb->offload_fwd_mark = true, meaning that the bridge thinks the frames\nwere already forwarded in hardware by us.\n\nSince dp->bridge_dev is populated only when there is hardware offload\nfor it, but not in the software fallback case, let's introduce a new\nhelper that can be called from the tagger data path which sets the\nskb->offload_fwd_mark accordingly to zero when there is no hardware\noffload for bridging. This lets the bridge forward packets back to other\ninterfaces of our switch, if needed.\n\nSigned-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>\nReviewed-by: Tobias Waldekranz <tobias@waldekranz.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n net/dsa/dsa_priv.h         | 14 ++++++++++++++\n net/dsa/tag_brcm.c         |  4 ++--\n net/dsa/tag_dsa.c          | 15 +++++++++++----\n net/dsa/tag_ksz.c          |  2 +-\n net/dsa/tag_lan9303.c      |  3 ++-\n net/dsa/tag_mtk.c          |  2 +-\n net/dsa/tag_ocelot.c       |  2 +-\n net/dsa/tag_rtl4_a.c       |  2 +-\n net/dsa/tag_sja1105.c      | 20 ++++++++++++++------\n 9 files changed, 47 insertions(+), 17 deletions(-)\n\n--- a/net/dsa/dsa_priv.h\n+++ b/net/dsa/dsa_priv.h\n@@ -266,6 +266,20 @@ static inline struct sk_buff *dsa_untag_\n \treturn skb;\n }\n \n+/* If the ingress port offloads the bridge, we mark the frame as autonomously\n+ * forwarded by hardware, so the software bridge doesn't forward in twice, back\n+ * to us, because we already did. However, if we're in fallback mode and we do\n+ * software bridging, we are not offloading it, therefore the dp->bridge_dev\n+ * pointer is not populated, and flooding needs to be done by software (we are\n+ * effectively operating in standalone ports mode).\n+ */\n+static inline void dsa_default_offload_fwd_mark(struct sk_buff *skb)\n+{\n+\tstruct dsa_port *dp = dsa_slave_to_port(skb->dev);\n+\n+\tskb->offload_fwd_mark = !!(dp->bridge_dev);\n+}\n+\n /* switch.c */\n int dsa_switch_register_notifier(struct dsa_switch *ds);\n void dsa_switch_unregister_notifier(struct dsa_switch *ds);\n--- a/net/dsa/tag_brcm.c\n+++ b/net/dsa/tag_brcm.c\n@@ -166,7 +166,7 @@ static struct sk_buff *brcm_tag_rcv_ll(s\n \t/* Remove Broadcom tag and update checksum */\n \tskb_pull_rcsum(skb, BRCM_TAG_LEN);\n \n-\tskb->offload_fwd_mark = 1;\n+\tdsa_default_offload_fwd_mark(skb);\n \n \treturn skb;\n }\n@@ -270,7 +270,7 @@ static struct sk_buff *brcm_leg_tag_rcv(\n \t/* Remove Broadcom tag and update checksum */\n \tskb_pull_rcsum(skb, BRCM_LEG_TAG_LEN);\n \n-\tskb->offload_fwd_mark = 1;\n+\tdsa_default_offload_fwd_mark(skb);\n \n \t/* Move the Ethernet DA and SA */\n \tmemmove(skb->data - ETH_HLEN,\n--- a/net/dsa/tag_ksz.c\n+++ b/net/dsa/tag_ksz.c\n@@ -24,7 +24,7 @@ static struct sk_buff *ksz_common_rcv(st\n \n \tpskb_trim_rcsum(skb, skb->len - len);\n \n-\tskb->offload_fwd_mark = true;\n+\tdsa_default_offload_fwd_mark(skb);\n \n \treturn skb;\n }\n--- a/net/dsa/tag_lan9303.c\n+++ b/net/dsa/tag_lan9303.c\n@@ -115,7 +115,8 @@ static struct sk_buff *lan9303_rcv(struc\n \tskb_pull_rcsum(skb, 2 + 2);\n \tmemmove(skb->data - ETH_HLEN, skb->data - (ETH_HLEN + LAN9303_TAG_LEN),\n \t\t2 * ETH_ALEN);\n-\tskb->offload_fwd_mark = !(lan9303_tag1 & LAN9303_TAG_RX_TRAPPED_TO_CPU);\n+\tif (!(lan9303_tag1 & LAN9303_TAG_RX_TRAPPED_TO_CPU))\n+\t\tdsa_default_offload_fwd_mark(skb);\n \n \treturn skb;\n }\n--- a/net/dsa/tag_mtk.c\n+++ b/net/dsa/tag_mtk.c\n@@ -104,7 +104,7 @@ static struct sk_buff *mtk_tag_rcv(struc\n \n \t/* Only unicast or broadcast frames are offloaded */\n \tif (likely(!is_multicast_skb))\n-\t\tskb->offload_fwd_mark = 1;\n+\t\tdsa_default_offload_fwd_mark(skb);\n \n \treturn skb;\n }\n--- a/net/dsa/tag_ocelot.c\n+++ b/net/dsa/tag_ocelot.c\n@@ -225,7 +225,7 @@ static struct sk_buff *ocelot_rcv(struct\n \t\t */\n \t\treturn NULL;\n \n-\tskb->offload_fwd_mark = 1;\n+\tdsa_default_offload_fwd_mark(skb);\n \tskb->priority = qos_class;\n \n \t/* Ocelot switches copy frames unmodified to the CPU. However, it is\n--- a/net/dsa/tag_rtl4_a.c\n+++ b/net/dsa/tag_rtl4_a.c\n@@ -115,7 +115,7 @@ static struct sk_buff *rtl4a_tag_rcv(str\n \t\tskb->data - ETH_HLEN - RTL4_A_HDR_LEN,\n \t\t2 * ETH_ALEN);\n \n-\tskb->offload_fwd_mark = 1;\n+\tdsa_default_offload_fwd_mark(skb);\n \n \treturn skb;\n }\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/745-v5.16-01-net-phy-at803x-add-support-for-qca-8327-A-variant.patch",
    "content": "From b4df02b562f4aa14ff6811f30e1b4d2159585c59 Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Sun, 19 Sep 2021 18:28:15 +0200\nSubject: net: phy: at803x: add support for qca 8327 A variant internal phy\n\nFor qca8327 internal phy there are 2 different switch variant with 2\ndifferent phy id. Add this missing variant so the internal phy can be\ncorrectly identified and fixed.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nReviewed-by: Andrew Lunn <andrew@lunn.ch>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/phy/at803x.c | 25 ++++++++++++++++++++-----\n 1 file changed, 20 insertions(+), 5 deletions(-)\n\n--- a/drivers/net/phy/at803x.c\n+++ b/drivers/net/phy/at803x.c\n@@ -148,7 +148,8 @@\n #define AT803X_PAGE_FIBER\t\t0\n #define AT803X_PAGE_COPPER\t\t1\n \n-#define QCA8327_PHY_ID\t\t\t\t0x004dd034\n+#define QCA8327_A_PHY_ID\t\t\t0x004dd033\n+#define QCA8327_B_PHY_ID\t\t\t0x004dd034\n #define QCA8337_PHY_ID\t\t\t\t0x004dd036\n #define QCA8K_PHY_ID_MASK\t\t\t0xffffffff\n \n@@ -1329,10 +1330,23 @@ static struct phy_driver at803x_driver[]\n \t.get_strings = at803x_get_strings,\n \t.get_stats = at803x_get_stats,\n }, {\n-\t/* QCA8327 */\n-\t.phy_id = QCA8327_PHY_ID,\n+\t/* QCA8327-A from switch QCA8327-AL1A */\n+\t.phy_id = QCA8327_A_PHY_ID,\n \t.phy_id_mask = QCA8K_PHY_ID_MASK,\n-\t.name = \"QCA PHY 8327\",\n+\t.name = \"QCA PHY 8327-A\",\n+\t/* PHY_GBIT_FEATURES */\n+\t.probe = at803x_probe,\n+\t.flags = PHY_IS_INTERNAL,\n+\t.config_init = qca83xx_config_init,\n+\t.soft_reset = genphy_soft_reset,\n+\t.get_sset_count = at803x_get_sset_count,\n+\t.get_strings = at803x_get_strings,\n+\t.get_stats = at803x_get_stats,\n+}, {\n+\t/* QCA8327-B from switch QCA8327-BL1A */\n+\t.phy_id = QCA8327_B_PHY_ID,\n+\t.phy_id_mask = QCA8K_PHY_ID_MASK,\n+\t.name = \"QCA PHY 8327-B\",\n \t/* PHY_GBIT_FEATURES */\n \t.probe = at803x_probe,\n \t.flags = PHY_IS_INTERNAL,\n@@ -1352,7 +1366,8 @@ static struct mdio_device_id __maybe_unu\n \t{ PHY_ID_MATCH_EXACT(ATH8035_PHY_ID) },\n \t{ PHY_ID_MATCH_EXACT(ATH9331_PHY_ID) },\n \t{ PHY_ID_MATCH_EXACT(QCA8337_PHY_ID) },\n-\t{ PHY_ID_MATCH_EXACT(QCA8327_PHY_ID) },\n+\t{ PHY_ID_MATCH_EXACT(QCA8327_A_PHY_ID) },\n+\t{ PHY_ID_MATCH_EXACT(QCA8327_B_PHY_ID) },\n \t{ }\n };\n \n"
  },
  {
    "path": "target/linux/generic/backport-5.10/745-v5.16-02-net-phy-at803x-add-resume-suspend-function-to-qca83x.patch",
    "content": "From 15b9df4ece17d084f14eb0ca1cf05f2ad497e425 Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Sun, 19 Sep 2021 18:28:16 +0200\nSubject: net: phy: at803x: add resume/suspend function to qca83xx phy\n\nAdd resume/suspend function to qca83xx internal phy.\nWe can't use the at803x generic function as the documentation lacks of\nany support for WoL regs.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nReviewed-by: Andrew Lunn <andrew@lunn.ch>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/phy/at803x.c | 6 ++++++\n 1 file changed, 6 insertions(+)\n\n--- a/drivers/net/phy/at803x.c\n+++ b/drivers/net/phy/at803x.c\n@@ -1329,6 +1329,8 @@ static struct phy_driver at803x_driver[]\n \t.get_sset_count = at803x_get_sset_count,\n \t.get_strings = at803x_get_strings,\n \t.get_stats = at803x_get_stats,\n+\t.suspend\t\t= genphy_suspend,\n+\t.resume\t\t\t= genphy_resume,\n }, {\n \t/* QCA8327-A from switch QCA8327-AL1A */\n \t.phy_id = QCA8327_A_PHY_ID,\n@@ -1342,6 +1344,8 @@ static struct phy_driver at803x_driver[]\n \t.get_sset_count = at803x_get_sset_count,\n \t.get_strings = at803x_get_strings,\n \t.get_stats = at803x_get_stats,\n+\t.suspend\t\t= genphy_suspend,\n+\t.resume\t\t\t= genphy_resume,\n }, {\n \t/* QCA8327-B from switch QCA8327-BL1A */\n \t.phy_id = QCA8327_B_PHY_ID,\n@@ -1355,6 +1359,8 @@ static struct phy_driver at803x_driver[]\n \t.get_sset_count = at803x_get_sset_count,\n \t.get_strings = at803x_get_strings,\n \t.get_stats = at803x_get_stats,\n+\t.suspend\t\t= genphy_suspend,\n+\t.resume\t\t\t= genphy_resume,\n }, };\n \n module_phy_driver(at803x_driver);\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/745-v5.16-03-net-phy-at803x-fix-spacing-and-improve-name-for-83xx.patch",
    "content": "From d44fd8604a4ab92119adb35f05fd87612af722b5 Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Sun, 19 Sep 2021 18:28:17 +0200\nSubject: net: phy: at803x: fix spacing and improve name for 83xx phy\n\nFix spacing and improve name for 83xx phy following other phy in the\nsame driver.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nReviewed-by: Andrew Lunn <andrew@lunn.ch>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/phy/at803x.c | 60 ++++++++++++++++++++++++------------------------\n 1 file changed, 30 insertions(+), 30 deletions(-)\n\n--- a/drivers/net/phy/at803x.c\n+++ b/drivers/net/phy/at803x.c\n@@ -1318,47 +1318,47 @@ static struct phy_driver at803x_driver[]\n \t.config_aneg\t\t= at803x_config_aneg,\n }, {\n \t/* QCA8337 */\n-\t.phy_id = QCA8337_PHY_ID,\n-\t.phy_id_mask = QCA8K_PHY_ID_MASK,\n-\t.name = \"QCA PHY 8337\",\n+\t.phy_id\t\t\t= QCA8337_PHY_ID,\n+\t.phy_id_mask\t\t= QCA8K_PHY_ID_MASK,\n+\t.name\t\t\t= \"Qualcomm Atheros 8337 internal PHY\",\n \t/* PHY_GBIT_FEATURES */\n-\t.probe = at803x_probe,\n-\t.flags = PHY_IS_INTERNAL,\n-\t.config_init = qca83xx_config_init,\n-\t.soft_reset = genphy_soft_reset,\n-\t.get_sset_count = at803x_get_sset_count,\n-\t.get_strings = at803x_get_strings,\n-\t.get_stats = at803x_get_stats,\n+\t.probe\t\t\t= at803x_probe,\n+\t.flags\t\t\t= PHY_IS_INTERNAL,\n+\t.config_init\t\t= qca83xx_config_init,\n+\t.soft_reset\t\t= genphy_soft_reset,\n+\t.get_sset_count\t\t= at803x_get_sset_count,\n+\t.get_strings\t\t= at803x_get_strings,\n+\t.get_stats\t\t= at803x_get_stats,\n \t.suspend\t\t= genphy_suspend,\n \t.resume\t\t\t= genphy_resume,\n }, {\n \t/* QCA8327-A from switch QCA8327-AL1A */\n-\t.phy_id = QCA8327_A_PHY_ID,\n-\t.phy_id_mask = QCA8K_PHY_ID_MASK,\n-\t.name = \"QCA PHY 8327-A\",\n+\t.phy_id\t\t\t= QCA8327_A_PHY_ID,\n+\t.phy_id_mask\t\t= QCA8K_PHY_ID_MASK,\n+\t.name\t\t\t= \"Qualcomm Atheros 8327-A internal PHY\",\n \t/* PHY_GBIT_FEATURES */\n-\t.probe = at803x_probe,\n-\t.flags = PHY_IS_INTERNAL,\n-\t.config_init = qca83xx_config_init,\n-\t.soft_reset = genphy_soft_reset,\n-\t.get_sset_count = at803x_get_sset_count,\n-\t.get_strings = at803x_get_strings,\n-\t.get_stats = at803x_get_stats,\n+\t.probe\t\t\t= at803x_probe,\n+\t.flags\t\t\t= PHY_IS_INTERNAL,\n+\t.config_init\t\t= qca83xx_config_init,\n+\t.soft_reset\t\t= genphy_soft_reset,\n+\t.get_sset_count\t\t= at803x_get_sset_count,\n+\t.get_strings\t\t= at803x_get_strings,\n+\t.get_stats\t\t= at803x_get_stats,\n \t.suspend\t\t= genphy_suspend,\n \t.resume\t\t\t= genphy_resume,\n }, {\n \t/* QCA8327-B from switch QCA8327-BL1A */\n-\t.phy_id = QCA8327_B_PHY_ID,\n-\t.phy_id_mask = QCA8K_PHY_ID_MASK,\n-\t.name = \"QCA PHY 8327-B\",\n+\t.phy_id\t\t\t= QCA8327_B_PHY_ID,\n+\t.phy_id_mask\t\t= QCA8K_PHY_ID_MASK,\n+\t.name\t\t\t= \"Qualcomm Atheros 8327-B internal PHY\",\n \t/* PHY_GBIT_FEATURES */\n-\t.probe = at803x_probe,\n-\t.flags = PHY_IS_INTERNAL,\n-\t.config_init = qca83xx_config_init,\n-\t.soft_reset = genphy_soft_reset,\n-\t.get_sset_count = at803x_get_sset_count,\n-\t.get_strings = at803x_get_strings,\n-\t.get_stats = at803x_get_stats,\n+\t.probe\t\t\t= at803x_probe,\n+\t.flags\t\t\t= PHY_IS_INTERNAL,\n+\t.config_init\t\t= qca83xx_config_init,\n+\t.soft_reset\t\t= genphy_soft_reset,\n+\t.get_sset_count\t\t= at803x_get_sset_count,\n+\t.get_strings\t\t= at803x_get_strings,\n+\t.get_stats\t\t= at803x_get_stats,\n \t.suspend\t\t= genphy_suspend,\n \t.resume\t\t\t= genphy_resume,\n }, };\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/746-v5.16-01-net-phy-at803x-fix-resume-for-QCA8327-phy.patch",
    "content": "From ba3c01ee02ed0d821c9f241f179bbc9457542b8f Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Sun, 10 Oct 2021 00:46:15 +0200\nSubject: net: phy: at803x: fix resume for QCA8327 phy\n\nFrom Documentation phy resume triggers phy reset and restart\nauto-negotiation. Add a dedicated function to wait reset to finish as\nit was notice a regression where port sometime are not reliable after a\nsuspend/resume session. The reset wait logic is copied from phy_poll_reset.\nAdd dedicated suspend function to use genphy_suspend only with QCA8337\nphy and set only additional debug settings for QCA8327. With more test\nit was reported that QCA8327 doesn't proprely support this mode and\nusing this cause the unreliability of the switch ports, especially the\nmalfunction of the port0.\n\nFixes: 15b9df4ece17 (\"net: phy: at803x: add resume/suspend function to qca83xx phy\")\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/phy/at803x.c | 69 +++++++++++++++++++++++++++++++++++++++++++-----\n 1 file changed, 63 insertions(+), 6 deletions(-)\n\n--- a/drivers/net/phy/at803x.c\n+++ b/drivers/net/phy/at803x.c\n@@ -92,9 +92,14 @@\n #define AT803X_DEBUG_REG_5\t\t\t0x05\n #define AT803X_DEBUG_TX_CLK_DLY_EN\t\tBIT(8)\n \n+#define AT803X_DEBUG_REG_HIB_CTRL\t\t0x0b\n+#define   AT803X_DEBUG_HIB_CTRL_SEL_RST_80U\tBIT(10)\n+#define   AT803X_DEBUG_HIB_CTRL_EN_ANY_CHANGE\tBIT(13)\n+\n #define AT803X_DEBUG_REG_3C\t\t\t0x3C\n \n #define AT803X_DEBUG_REG_3D\t\t\t0x3D\n+#define   AT803X_DEBUG_GATE_CLK_IN1000\t\tBIT(6)\n \n #define AT803X_DEBUG_REG_1F\t\t\t0x1F\n #define AT803X_DEBUG_PLL_ON\t\t\tBIT(2)\n@@ -1220,6 +1225,58 @@ static int qca83xx_config_init(struct ph\n \treturn 0;\n }\n \n+static int qca83xx_resume(struct phy_device *phydev)\n+{\n+\tint ret, val;\n+\n+\t/* Skip reset if not suspended */\n+\tif (!phydev->suspended)\n+\t\treturn 0;\n+\n+\t/* Reinit the port, reset values set by suspend */\n+\tqca83xx_config_init(phydev);\n+\n+\t/* Reset the port on port resume */\n+\tphy_set_bits(phydev, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);\n+\n+\t/* On resume from suspend the switch execute a reset and\n+\t * restart auto-negotiation. Wait for reset to complete.\n+\t */\n+\tret = phy_read_poll_timeout(phydev, MII_BMCR, val, !(val & BMCR_RESET),\n+\t\t\t\t    50000, 600000, true);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tmsleep(1);\n+\n+\treturn 0;\n+}\n+\n+static int qca83xx_suspend(struct phy_device *phydev)\n+{\n+\tu16 mask = 0;\n+\n+\t/* Only QCA8337 support actual suspend.\n+\t * QCA8327 cause port unreliability when phy suspend\n+\t * is set.\n+\t */\n+\tif (phydev->drv->phy_id == QCA8337_PHY_ID) {\n+\t\tgenphy_suspend(phydev);\n+\t} else {\n+\t\tmask |= ~(BMCR_SPEED1000 | BMCR_FULLDPLX);\n+\t\tphy_modify(phydev, MII_BMCR, mask, 0);\n+\t}\n+\n+\tat803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_3D,\n+\t\t\t      AT803X_DEBUG_GATE_CLK_IN1000, 0);\n+\n+\tat803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_HIB_CTRL,\n+\t\t\t      AT803X_DEBUG_HIB_CTRL_EN_ANY_CHANGE |\n+\t\t\t      AT803X_DEBUG_HIB_CTRL_SEL_RST_80U, 0);\n+\n+\treturn 0;\n+}\n+\n static struct phy_driver at803x_driver[] = {\n {\n \t/* Qualcomm Atheros AR8035 */\n@@ -1329,8 +1386,8 @@ static struct phy_driver at803x_driver[]\n \t.get_sset_count\t\t= at803x_get_sset_count,\n \t.get_strings\t\t= at803x_get_strings,\n \t.get_stats\t\t= at803x_get_stats,\n-\t.suspend\t\t= genphy_suspend,\n-\t.resume\t\t\t= genphy_resume,\n+\t.suspend\t\t= qca83xx_suspend,\n+\t.resume\t\t\t= qca83xx_resume,\n }, {\n \t/* QCA8327-A from switch QCA8327-AL1A */\n \t.phy_id\t\t\t= QCA8327_A_PHY_ID,\n@@ -1344,8 +1401,8 @@ static struct phy_driver at803x_driver[]\n \t.get_sset_count\t\t= at803x_get_sset_count,\n \t.get_strings\t\t= at803x_get_strings,\n \t.get_stats\t\t= at803x_get_stats,\n-\t.suspend\t\t= genphy_suspend,\n-\t.resume\t\t\t= genphy_resume,\n+\t.suspend\t\t= qca83xx_suspend,\n+\t.resume\t\t\t= qca83xx_resume,\n }, {\n \t/* QCA8327-B from switch QCA8327-BL1A */\n \t.phy_id\t\t\t= QCA8327_B_PHY_ID,\n@@ -1359,8 +1416,8 @@ static struct phy_driver at803x_driver[]\n \t.get_sset_count\t\t= at803x_get_sset_count,\n \t.get_strings\t\t= at803x_get_strings,\n \t.get_stats\t\t= at803x_get_stats,\n-\t.suspend\t\t= genphy_suspend,\n-\t.resume\t\t\t= genphy_resume,\n+\t.suspend\t\t= qca83xx_suspend,\n+\t.resume\t\t\t= qca83xx_resume,\n }, };\n \n module_phy_driver(at803x_driver);\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/746-v5.16-02-net-phy-at803x-add-DAC-amplitude-fix-for-8327-phy.patch",
    "content": "From 1ca8311949aec5c9447645731ef1c6bc5bd71350 Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Sun, 10 Oct 2021 00:46:16 +0200\nSubject: net: phy: at803x: add DAC amplitude fix for 8327 phy\n\nQCA8327 internal phy require DAC amplitude adjustement set to +6% with\n100m speed. Also add additional define to report a change of the same\nreg in QCA8337. (different scope it does set 1000m voltage)\nAdd link_change_notify function to set the proper amplitude adjustement\non PHY_RUNNING state and disable on any other state.\n\nFixes: b4df02b562f4 (\"net: phy: at803x: add support for qca 8327 A variant internal phy\")\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/phy/at803x.c | 33 +++++++++++++++++++++++++++++++++\n 1 file changed, 33 insertions(+)\n\n--- a/drivers/net/phy/at803x.c\n+++ b/drivers/net/phy/at803x.c\n@@ -87,6 +87,8 @@\n #define AT803X_PSSR_MR_AN_COMPLETE\t0x0200\n \n #define AT803X_DEBUG_REG_0\t\t\t0x00\n+#define QCA8327_DEBUG_MANU_CTRL_EN\t\tBIT(2)\n+#define QCA8337_DEBUG_MANU_CTRL_EN\t\tGENMASK(3, 2)\n #define AT803X_DEBUG_RX_CLK_DLY_EN\t\tBIT(15)\n \n #define AT803X_DEBUG_REG_5\t\t\t0x05\n@@ -1222,9 +1224,37 @@ static int qca83xx_config_init(struct ph\n \t\tbreak;\n \t}\n \n+\t/* QCA8327 require DAC amplitude adjustment for 100m set to +6%.\n+\t * Disable on init and enable only with 100m speed following\n+\t * qca original source code.\n+\t */\n+\tif (phydev->drv->phy_id == QCA8327_A_PHY_ID ||\n+\t    phydev->drv->phy_id == QCA8327_B_PHY_ID)\n+\t\tat803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_0,\n+\t\t\t\t      QCA8327_DEBUG_MANU_CTRL_EN, 0);\n+\n \treturn 0;\n }\n \n+static void qca83xx_link_change_notify(struct phy_device *phydev)\n+{\n+\t/* QCA8337 doesn't require DAC Amplitude adjustement */\n+\tif (phydev->drv->phy_id == QCA8337_PHY_ID)\n+\t\treturn;\n+\n+\t/* Set DAC Amplitude adjustment to +6% for 100m on link running */\n+\tif (phydev->state == PHY_RUNNING) {\n+\t\tif (phydev->speed == SPEED_100)\n+\t\t\tat803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_0,\n+\t\t\t\t\t      QCA8327_DEBUG_MANU_CTRL_EN,\n+\t\t\t\t\t      QCA8327_DEBUG_MANU_CTRL_EN);\n+\t} else {\n+\t\t/* Reset DAC Amplitude adjustment */\n+\t\tat803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_0,\n+\t\t\t\t      QCA8327_DEBUG_MANU_CTRL_EN, 0);\n+\t}\n+}\n+\n static int qca83xx_resume(struct phy_device *phydev)\n {\n \tint ret, val;\n@@ -1379,6 +1409,7 @@ static struct phy_driver at803x_driver[]\n \t.phy_id_mask\t\t= QCA8K_PHY_ID_MASK,\n \t.name\t\t\t= \"Qualcomm Atheros 8337 internal PHY\",\n \t/* PHY_GBIT_FEATURES */\n+\t.link_change_notify\t= qca83xx_link_change_notify,\n \t.probe\t\t\t= at803x_probe,\n \t.flags\t\t\t= PHY_IS_INTERNAL,\n \t.config_init\t\t= qca83xx_config_init,\n@@ -1394,6 +1425,7 @@ static struct phy_driver at803x_driver[]\n \t.phy_id_mask\t\t= QCA8K_PHY_ID_MASK,\n \t.name\t\t\t= \"Qualcomm Atheros 8327-A internal PHY\",\n \t/* PHY_GBIT_FEATURES */\n+\t.link_change_notify\t= qca83xx_link_change_notify,\n \t.probe\t\t\t= at803x_probe,\n \t.flags\t\t\t= PHY_IS_INTERNAL,\n \t.config_init\t\t= qca83xx_config_init,\n@@ -1409,6 +1441,7 @@ static struct phy_driver at803x_driver[]\n \t.phy_id_mask\t\t= QCA8K_PHY_ID_MASK,\n \t.name\t\t\t= \"Qualcomm Atheros 8327-B internal PHY\",\n \t/* PHY_GBIT_FEATURES */\n+\t.link_change_notify\t= qca83xx_link_change_notify,\n \t.probe\t\t\t= at803x_probe,\n \t.flags\t\t\t= PHY_IS_INTERNAL,\n \t.config_init\t\t= qca83xx_config_init,\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/746-v5.16-03-net-phy-at803x-enable-prefer-master-for-83xx-interna.patch",
    "content": "From 9d1c29b4028557a496be9c5eb2b4b86063700636 Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Sun, 10 Oct 2021 00:46:17 +0200\nSubject: net: phy: at803x: enable prefer master for 83xx internal phy\n\nFrom original QCA source code the port was set to prefer master as port\ntype in 1000BASE-T mode. Apply the same settings also here.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nReviewed-by: Andrew Lunn <andrew@lunn.ch>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/phy/at803x.c | 3 +++\n 1 file changed, 3 insertions(+)\n\n--- a/drivers/net/phy/at803x.c\n+++ b/drivers/net/phy/at803x.c\n@@ -1233,6 +1233,9 @@ static int qca83xx_config_init(struct ph\n \t\tat803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_0,\n \t\t\t\t      QCA8327_DEBUG_MANU_CTRL_EN, 0);\n \n+\t/* Following original QCA sourcecode set port to prefer master */\n+\tphy_set_bits(phydev, MII_CTRL1000, CTL1000_PREFER_MASTER);\n+\n \treturn 0;\n }\n \n"
  },
  {
    "path": "target/linux/generic/backport-5.10/746-v5.16-04-net-phy-at803x-better-describe-debug-regs.patch",
    "content": "From 67999555ff42e91de7654488d9a7735bd9e84555 Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Sun, 10 Oct 2021 00:46:18 +0200\nSubject: net: phy: at803x: better describe debug regs\n\nGive a name to known debug regs from Documentation instead of using\nunknown hex values.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nReviewed-by: Andrew Lunn <andrew@lunn.ch>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/phy/at803x.c | 30 +++++++++++++++---------------\n 1 file changed, 15 insertions(+), 15 deletions(-)\n\n--- a/drivers/net/phy/at803x.c\n+++ b/drivers/net/phy/at803x.c\n@@ -86,12 +86,12 @@\n #define AT803X_PSSR\t\t\t0x11\t/*PHY-Specific Status Register*/\n #define AT803X_PSSR_MR_AN_COMPLETE\t0x0200\n \n-#define AT803X_DEBUG_REG_0\t\t\t0x00\n+#define AT803X_DEBUG_ANALOG_TEST_CTRL\t\t0x00\n #define QCA8327_DEBUG_MANU_CTRL_EN\t\tBIT(2)\n #define QCA8337_DEBUG_MANU_CTRL_EN\t\tGENMASK(3, 2)\n #define AT803X_DEBUG_RX_CLK_DLY_EN\t\tBIT(15)\n \n-#define AT803X_DEBUG_REG_5\t\t\t0x05\n+#define AT803X_DEBUG_SYSTEM_CTRL_MODE\t\t0x05\n #define AT803X_DEBUG_TX_CLK_DLY_EN\t\tBIT(8)\n \n #define AT803X_DEBUG_REG_HIB_CTRL\t\t0x0b\n@@ -100,7 +100,7 @@\n \n #define AT803X_DEBUG_REG_3C\t\t\t0x3C\n \n-#define AT803X_DEBUG_REG_3D\t\t\t0x3D\n+#define AT803X_DEBUG_REG_GREEN\t\t\t0x3D\n #define   AT803X_DEBUG_GATE_CLK_IN1000\t\tBIT(6)\n \n #define AT803X_DEBUG_REG_1F\t\t\t0x1F\n@@ -274,25 +274,25 @@ static int at803x_read_page(struct phy_d\n \n static int at803x_enable_rx_delay(struct phy_device *phydev)\n {\n-\treturn at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_0, 0,\n+\treturn at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 0,\n \t\t\t\t     AT803X_DEBUG_RX_CLK_DLY_EN);\n }\n \n static int at803x_enable_tx_delay(struct phy_device *phydev)\n {\n-\treturn at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_5, 0,\n+\treturn at803x_debug_reg_mask(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE, 0,\n \t\t\t\t     AT803X_DEBUG_TX_CLK_DLY_EN);\n }\n \n static int at803x_disable_rx_delay(struct phy_device *phydev)\n {\n-\treturn at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_0,\n+\treturn at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL,\n \t\t\t\t     AT803X_DEBUG_RX_CLK_DLY_EN, 0);\n }\n \n static int at803x_disable_tx_delay(struct phy_device *phydev)\n {\n-\treturn at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_5,\n+\treturn at803x_debug_reg_mask(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE,\n \t\t\t\t     AT803X_DEBUG_TX_CLK_DLY_EN, 0);\n }\n \n@@ -1208,9 +1208,9 @@ static int qca83xx_config_init(struct ph\n \tswitch (switch_revision) {\n \tcase 1:\n \t\t/* For 100M waveform */\n-\t\tat803x_debug_reg_write(phydev, AT803X_DEBUG_REG_0, 0x02ea);\n+\t\tat803x_debug_reg_write(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 0x02ea);\n \t\t/* Turn on Gigabit clock */\n-\t\tat803x_debug_reg_write(phydev, AT803X_DEBUG_REG_3D, 0x68a0);\n+\t\tat803x_debug_reg_write(phydev, AT803X_DEBUG_REG_GREEN, 0x68a0);\n \t\tbreak;\n \n \tcase 2:\n@@ -1218,8 +1218,8 @@ static int qca83xx_config_init(struct ph\n \t\tfallthrough;\n \tcase 4:\n \t\tphy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_AZ_DEBUG, 0x803f);\n-\t\tat803x_debug_reg_write(phydev, AT803X_DEBUG_REG_3D, 0x6860);\n-\t\tat803x_debug_reg_write(phydev, AT803X_DEBUG_REG_5, 0x2c46);\n+\t\tat803x_debug_reg_write(phydev, AT803X_DEBUG_REG_GREEN, 0x6860);\n+\t\tat803x_debug_reg_write(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE, 0x2c46);\n \t\tat803x_debug_reg_write(phydev, AT803X_DEBUG_REG_3C, 0x6000);\n \t\tbreak;\n \t}\n@@ -1230,7 +1230,7 @@ static int qca83xx_config_init(struct ph\n \t */\n \tif (phydev->drv->phy_id == QCA8327_A_PHY_ID ||\n \t    phydev->drv->phy_id == QCA8327_B_PHY_ID)\n-\t\tat803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_0,\n+\t\tat803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL,\n \t\t\t\t      QCA8327_DEBUG_MANU_CTRL_EN, 0);\n \n \t/* Following original QCA sourcecode set port to prefer master */\n@@ -1248,12 +1248,12 @@ static void qca83xx_link_change_notify(s\n \t/* Set DAC Amplitude adjustment to +6% for 100m on link running */\n \tif (phydev->state == PHY_RUNNING) {\n \t\tif (phydev->speed == SPEED_100)\n-\t\t\tat803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_0,\n+\t\t\tat803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL,\n \t\t\t\t\t      QCA8327_DEBUG_MANU_CTRL_EN,\n \t\t\t\t\t      QCA8327_DEBUG_MANU_CTRL_EN);\n \t} else {\n \t\t/* Reset DAC Amplitude adjustment */\n-\t\tat803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_0,\n+\t\tat803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL,\n \t\t\t\t      QCA8327_DEBUG_MANU_CTRL_EN, 0);\n \t}\n }\n@@ -1300,7 +1300,7 @@ static int qca83xx_suspend(struct phy_de\n \t\tphy_modify(phydev, MII_BMCR, mask, 0);\n \t}\n \n-\tat803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_3D,\n+\tat803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_GREEN,\n \t\t\t      AT803X_DEBUG_GATE_CLK_IN1000, 0);\n \n \tat803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_HIB_CTRL,\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/747-v5.16-01-dsa-qca8k-add-mac-power-sel-support.patch",
    "content": "From d8b6f5bae6d3b648a67b6958cb98e4e97256d652 Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Thu, 14 Oct 2021 00:39:06 +0200\nSubject: dsa: qca8k: add mac_power_sel support\n\nAdd missing mac power sel support needed for ipq8064/5 SoC that require\n1.8v for the internal regulator port instead of the default 1.5v.\nIf other device needs this, consider adding a dedicated binding to\nsupport this.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nReviewed-by: Vladimir Oltean <olteanv@gmail.com>\nReviewed-by: Florian Fainelli <f.fainelli@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/dsa/qca8k.c | 31 +++++++++++++++++++++++++++++++\n drivers/net/dsa/qca8k.h |  5 +++++\n 2 files changed, 36 insertions(+)\n\n--- a/drivers/net/dsa/qca8k.c\n+++ b/drivers/net/dsa/qca8k.c\n@@ -951,6 +951,33 @@ qca8k_setup_of_rgmii_delay(struct qca8k_\n }\n \n static int\n+qca8k_setup_mac_pwr_sel(struct qca8k_priv *priv)\n+{\n+\tu32 mask = 0;\n+\tint ret = 0;\n+\n+\t/* SoC specific settings for ipq8064.\n+\t * If more device require this consider adding\n+\t * a dedicated binding.\n+\t */\n+\tif (of_machine_is_compatible(\"qcom,ipq8064\"))\n+\t\tmask |= QCA8K_MAC_PWR_RGMII0_1_8V;\n+\n+\t/* SoC specific settings for ipq8065 */\n+\tif (of_machine_is_compatible(\"qcom,ipq8065\"))\n+\t\tmask |= QCA8K_MAC_PWR_RGMII1_1_8V;\n+\n+\tif (mask) {\n+\t\tret = qca8k_rmw(priv, QCA8K_REG_MAC_PWR_SEL,\n+\t\t\t\tQCA8K_MAC_PWR_RGMII0_1_8V |\n+\t\t\t\tQCA8K_MAC_PWR_RGMII1_1_8V,\n+\t\t\t\tmask);\n+\t}\n+\n+\treturn ret;\n+}\n+\n+static int\n qca8k_setup(struct dsa_switch *ds)\n {\n \tstruct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;\n@@ -979,6 +1006,10 @@ qca8k_setup(struct dsa_switch *ds)\n \tif (ret)\n \t\treturn ret;\n \n+\tret = qca8k_setup_mac_pwr_sel(priv);\n+\tif (ret)\n+\t\treturn ret;\n+\n \t/* Enable CPU Port */\n \tret = qca8k_reg_set(priv, QCA8K_REG_GLOBAL_FW_CTRL0,\n \t\t\t    QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN);\n--- a/drivers/net/dsa/qca8k.h\n+++ b/drivers/net/dsa/qca8k.h\n@@ -100,6 +100,11 @@\n #define   QCA8K_SGMII_MODE_CTRL_PHY\t\t\t(1 << 22)\n #define   QCA8K_SGMII_MODE_CTRL_MAC\t\t\t(2 << 22)\n \n+/* MAC_PWR_SEL registers */\n+#define QCA8K_REG_MAC_PWR_SEL\t\t\t\t0x0e4\n+#define   QCA8K_MAC_PWR_RGMII1_1_8V\t\t\tBIT(18)\n+#define   QCA8K_MAC_PWR_RGMII0_1_8V\t\t\tBIT(19)\n+\n /* EEE control registers */\n #define QCA8K_REG_EEE_CTRL\t\t\t\t0x100\n #define  QCA8K_REG_EEE_CTRL_LPI_EN(_i)\t\t\t((_i + 1) * 2)\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/747-v5.16-02-dt-bindings-net-dsa-qca8k-Add-SGMII-clock-phase-prop.patch",
    "content": "From fdbf35df9c091db9c46e57e9938e3f7a4f603a7c Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Thu, 14 Oct 2021 00:39:07 +0200\nSubject: dt-bindings: net: dsa: qca8k: Add SGMII clock phase properties\n\nAdd names and descriptions of additional PORT0_PAD_CTRL properties.\nqca,sgmii-(rx|tx)clk-falling-edge are for setting the respective clock\nphase to failling edge.\n\nCo-developed-by: Matthew Hagan <mnhagan88@gmail.com>\nSigned-off-by: Matthew Hagan <mnhagan88@gmail.com>\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n Documentation/devicetree/bindings/net/dsa/qca8k.txt | 4 ++++\n 1 file changed, 4 insertions(+)\n\n--- a/Documentation/devicetree/bindings/net/dsa/qca8k.txt\n+++ b/Documentation/devicetree/bindings/net/dsa/qca8k.txt\n@@ -37,6 +37,10 @@ A CPU port node has the following option\n                           managed entity. See\n                           Documentation/devicetree/bindings/net/fixed-link.txt\n                           for details.\n+- qca,sgmii-rxclk-falling-edge: Set the receive clock phase to falling edge.\n+                                Mostly used in qca8327 with CPU port 0 set to\n+                                sgmii.\n+- qca,sgmii-txclk-falling-edge: Set the transmit clock phase to falling edge.\n \n For QCA8K the 'fixed-link' sub-node supports only the following properties:\n \n"
  },
  {
    "path": "target/linux/generic/backport-5.10/747-v5.16-03-net-dsa-qca8k-add-support-for-sgmii-falling-edge.patch",
    "content": "From 6c43809bf1bee76c434e365a26546a92a5fbec14 Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Thu, 14 Oct 2021 00:39:08 +0200\nSubject: net: dsa: qca8k: add support for sgmii falling edge\n\nAdd support for this in the qca8k driver. Also add support for SGMII\nrx/tx clock falling edge. This is only present for pad0, pad5 and\npad6 have these bit reserved from Documentation. Add a comment that this\nis hardcoded to PAD0 as qca8327/28/34/37 have an unique sgmii line and\nsetting falling in port0 applies to both configuration with sgmii used\nfor port0 or port6.\n\nCo-developed-by: Matthew Hagan <mnhagan88@gmail.com>\nSigned-off-by: Matthew Hagan <mnhagan88@gmail.com>\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/dsa/qca8k.c | 63 +++++++++++++++++++++++++++++++++++++++++++++++++\n drivers/net/dsa/qca8k.h |  4 ++++\n 2 files changed, 67 insertions(+)\n\n--- a/drivers/net/dsa/qca8k.c\n+++ b/drivers/net/dsa/qca8k.c\n@@ -978,6 +978,42 @@ qca8k_setup_mac_pwr_sel(struct qca8k_pri\n }\n \n static int\n+qca8k_parse_port_config(struct qca8k_priv *priv)\n+{\n+\tstruct device_node *port_dn;\n+\tphy_interface_t mode;\n+\tstruct dsa_port *dp;\n+\tint port, ret;\n+\n+\t/* We have 2 CPU port. Check them */\n+\tfor (port = 0; port < QCA8K_NUM_PORTS; port++) {\n+\t\t/* Skip every other port */\n+\t\tif (port != 0 && port != 6)\n+\t\t\tcontinue;\n+\n+\t\tdp = dsa_to_port(priv->ds, port);\n+\t\tport_dn = dp->dn;\n+\n+\t\tif (!of_device_is_available(port_dn))\n+\t\t\tcontinue;\n+\n+\t\tret = of_get_phy_mode(port_dn, &mode);\n+\t\tif (ret)\n+\t\t\tcontinue;\n+\n+\t\tif (mode == PHY_INTERFACE_MODE_SGMII) {\n+\t\t\tif (of_property_read_bool(port_dn, \"qca,sgmii-txclk-falling-edge\"))\n+\t\t\t\tpriv->sgmii_tx_clk_falling_edge = true;\n+\n+\t\t\tif (of_property_read_bool(port_dn, \"qca,sgmii-rxclk-falling-edge\"))\n+\t\t\t\tpriv->sgmii_rx_clk_falling_edge = true;\n+\t\t}\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int\n qca8k_setup(struct dsa_switch *ds)\n {\n \tstruct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;\n@@ -990,6 +1026,11 @@ qca8k_setup(struct dsa_switch *ds)\n \t\treturn -EINVAL;\n \t}\n \n+\t/* Parse CPU port config to be later used in phy_link mac_config */\n+\tret = qca8k_parse_port_config(priv);\n+\tif (ret)\n+\t\treturn ret;\n+\n \tmutex_init(&priv->reg_mutex);\n \n \t/* Start by setting up the register mapping */\n@@ -1274,6 +1315,28 @@ qca8k_phylink_mac_config(struct dsa_swit\n \t\t}\n \n \t\tqca8k_write(priv, QCA8K_REG_SGMII_CTRL, val);\n+\n+\t\t/* For qca8327/qca8328/qca8334/qca8338 sgmii is unique and\n+\t\t * falling edge is set writing in the PORT0 PAD reg\n+\t\t */\n+\t\tif (priv->switch_id == QCA8K_ID_QCA8327 ||\n+\t\t    priv->switch_id == QCA8K_ID_QCA8337)\n+\t\t\treg = QCA8K_REG_PORT0_PAD_CTRL;\n+\n+\t\tval = 0;\n+\n+\t\t/* SGMII Clock phase configuration */\n+\t\tif (priv->sgmii_rx_clk_falling_edge)\n+\t\t\tval |= QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE;\n+\n+\t\tif (priv->sgmii_tx_clk_falling_edge)\n+\t\t\tval |= QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE;\n+\n+\t\tif (val)\n+\t\t\tret = qca8k_rmw(priv, reg,\n+\t\t\t\t\tQCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE |\n+\t\t\t\t\tQCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE,\n+\t\t\t\t\tval);\n \t\tbreak;\n \tdefault:\n \t\tdev_err(ds->dev, \"xMII mode %s not supported for port %d\\n\",\n--- a/drivers/net/dsa/qca8k.h\n+++ b/drivers/net/dsa/qca8k.h\n@@ -35,6 +35,8 @@\n #define   QCA8K_MASK_CTRL_DEVICE_ID_MASK\t\tGENMASK(15, 8)\n #define   QCA8K_MASK_CTRL_DEVICE_ID(x)\t\t\t((x) >> 8)\n #define QCA8K_REG_PORT0_PAD_CTRL\t\t\t0x004\n+#define   QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE\tBIT(19)\n+#define   QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE\tBIT(18)\n #define QCA8K_REG_PORT5_PAD_CTRL\t\t\t0x008\n #define QCA8K_REG_PORT6_PAD_CTRL\t\t\t0x00c\n #define   QCA8K_PORT_PAD_RGMII_EN\t\t\tBIT(26)\n@@ -260,6 +262,8 @@ struct qca8k_priv {\n \tu8 switch_revision;\n \tu8 rgmii_tx_delay;\n \tu8 rgmii_rx_delay;\n+\tbool sgmii_rx_clk_falling_edge;\n+\tbool sgmii_tx_clk_falling_edge;\n \tbool legacy_phy_port_mapping;\n \tstruct regmap *regmap;\n \tstruct mii_bus *bus;\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/747-v5.16-04-dt-bindings-net-dsa-qca8k-Document-support-for-CPU-p.patch",
    "content": "From 731d613338ec6de482053ffa3f71be2325b0f8eb Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Thu, 14 Oct 2021 00:39:09 +0200\nSubject: dt-bindings: net: dsa: qca8k: Document support for CPU port 6\n\nThe switch now support CPU port to be set 6 instead of be hardcoded to\n0. Document support for it and describe logic selection.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n Documentation/devicetree/bindings/net/dsa/qca8k.txt | 6 +++++-\n 1 file changed, 5 insertions(+), 1 deletion(-)\n\n--- a/Documentation/devicetree/bindings/net/dsa/qca8k.txt\n+++ b/Documentation/devicetree/bindings/net/dsa/qca8k.txt\n@@ -29,7 +29,11 @@ the mdio MASTER is used as communication\n Don't use mixed external and internal mdio-bus configurations, as this is\n not supported by the hardware.\n \n-The CPU port of this switch is always port 0.\n+This switch support 2 CPU port. Normally and advised configuration is with\n+CPU port set to port 0. It is also possible to set the CPU port to port 6\n+if the device requires it. The driver will configure the switch to the defined\n+port. With both CPU port declared the first CPU port is selected as primary\n+and the secondary CPU ignored.\n \n A CPU port node has the following optional node:\n \n"
  },
  {
    "path": "target/linux/generic/backport-5.10/747-v5.16-05-net-dsa-qca8k-add-support-for-cpu-port-6.patch",
    "content": "From 3fcf734aa482487df83cf8f18608438fcf59127f Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Thu, 14 Oct 2021 00:39:10 +0200\nSubject: net: dsa: qca8k: add support for cpu port 6\n\nCurrently CPU port is always hardcoded to port 0. This switch have 2 CPU\nports. The original intention of this driver seems to be use the\nmac06_exchange bit to swap MAC0 with MAC6 in the strange configuration\nwhere device have connected only the CPU port 6. To skip the\nintroduction of a new binding, rework the driver to address the\nsecondary CPU port as primary and drop any reference of hardcoded port.\nWith configuration of mac06 exchange, just skip the definition of port0\nand define the CPU port as a secondary. The driver will autoconfigure\nthe switch to use that as the primary CPU port.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/dsa/qca8k.c | 51 ++++++++++++++++++++++++++++++++++---------------\n drivers/net/dsa/qca8k.h |  2 --\n 2 files changed, 36 insertions(+), 17 deletions(-)\n\n--- a/drivers/net/dsa/qca8k.c\n+++ b/drivers/net/dsa/qca8k.c\n@@ -977,6 +977,22 @@ qca8k_setup_mac_pwr_sel(struct qca8k_pri\n \treturn ret;\n }\n \n+static int qca8k_find_cpu_port(struct dsa_switch *ds)\n+{\n+\tstruct qca8k_priv *priv = ds->priv;\n+\n+\t/* Find the connected cpu port. Valid port are 0 or 6 */\n+\tif (dsa_is_cpu_port(ds, 0))\n+\t\treturn 0;\n+\n+\tdev_dbg(priv->dev, \"port 0 is not the CPU port. Checking port 6\");\n+\n+\tif (dsa_is_cpu_port(ds, 6))\n+\t\treturn 6;\n+\n+\treturn -EINVAL;\n+}\n+\n static int\n qca8k_parse_port_config(struct qca8k_priv *priv)\n {\n@@ -1017,13 +1033,13 @@ static int\n qca8k_setup(struct dsa_switch *ds)\n {\n \tstruct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;\n-\tint ret, i;\n+\tint cpu_port, ret, i;\n \tu32 mask;\n \n-\t/* Make sure that port 0 is the cpu port */\n-\tif (!dsa_is_cpu_port(ds, 0)) {\n-\t\tdev_err(priv->dev, \"port 0 is not the CPU port\");\n-\t\treturn -EINVAL;\n+\tcpu_port = qca8k_find_cpu_port(ds);\n+\tif (cpu_port < 0) {\n+\t\tdev_err(priv->dev, \"No cpu port configured in both cpu port0 and port6\");\n+\t\treturn cpu_port;\n \t}\n \n \t/* Parse CPU port config to be later used in phy_link mac_config */\n@@ -1065,7 +1081,7 @@ qca8k_setup(struct dsa_switch *ds)\n \t\tdev_warn(priv->dev, \"mib init failed\");\n \n \t/* Enable QCA header mode on the cpu port */\n-\tret = qca8k_write(priv, QCA8K_REG_PORT_HDR_CTRL(QCA8K_CPU_PORT),\n+\tret = qca8k_write(priv, QCA8K_REG_PORT_HDR_CTRL(cpu_port),\n \t\t\t  QCA8K_PORT_HDR_CTRL_ALL << QCA8K_PORT_HDR_CTRL_TX_S |\n \t\t\t  QCA8K_PORT_HDR_CTRL_ALL << QCA8K_PORT_HDR_CTRL_RX_S);\n \tif (ret) {\n@@ -1087,10 +1103,10 @@ qca8k_setup(struct dsa_switch *ds)\n \n \t/* Forward all unknown frames to CPU port for Linux processing */\n \tret = qca8k_write(priv, QCA8K_REG_GLOBAL_FW_CTRL1,\n-\t\t\t  BIT(0) << QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_S |\n-\t\t\t  BIT(0) << QCA8K_GLOBAL_FW_CTRL1_BC_DP_S |\n-\t\t\t  BIT(0) << QCA8K_GLOBAL_FW_CTRL1_MC_DP_S |\n-\t\t\t  BIT(0) << QCA8K_GLOBAL_FW_CTRL1_UC_DP_S);\n+\t\t\t  BIT(cpu_port) << QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_S |\n+\t\t\t  BIT(cpu_port) << QCA8K_GLOBAL_FW_CTRL1_BC_DP_S |\n+\t\t\t  BIT(cpu_port) << QCA8K_GLOBAL_FW_CTRL1_MC_DP_S |\n+\t\t\t  BIT(cpu_port) << QCA8K_GLOBAL_FW_CTRL1_UC_DP_S);\n \tif (ret)\n \t\treturn ret;\n \n@@ -1098,7 +1114,7 @@ qca8k_setup(struct dsa_switch *ds)\n \tfor (i = 0; i < QCA8K_NUM_PORTS; i++) {\n \t\t/* CPU port gets connected to all user ports of the switch */\n \t\tif (dsa_is_cpu_port(ds, i)) {\n-\t\t\tret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(QCA8K_CPU_PORT),\n+\t\t\tret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(cpu_port),\n \t\t\t\t\tQCA8K_PORT_LOOKUP_MEMBER, dsa_user_ports(ds));\n \t\t\tif (ret)\n \t\t\t\treturn ret;\n@@ -1110,7 +1126,7 @@ qca8k_setup(struct dsa_switch *ds)\n \n \t\t\tret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i),\n \t\t\t\t\tQCA8K_PORT_LOOKUP_MEMBER,\n-\t\t\t\t\tBIT(QCA8K_CPU_PORT));\n+\t\t\t\t\tBIT(cpu_port));\n \t\t\tif (ret)\n \t\t\t\treturn ret;\n \n@@ -1616,9 +1632,12 @@ static int\n qca8k_port_bridge_join(struct dsa_switch *ds, int port, struct net_device *br)\n {\n \tstruct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;\n-\tint port_mask = BIT(QCA8K_CPU_PORT);\n+\tint port_mask, cpu_port;\n \tint i, ret;\n \n+\tcpu_port = dsa_to_port(ds, port)->cpu_dp->index;\n+\tport_mask = BIT(cpu_port);\n+\n \tfor (i = 1; i < QCA8K_NUM_PORTS; i++) {\n \t\tif (dsa_to_port(ds, i)->bridge_dev != br)\n \t\t\tcontinue;\n@@ -1645,7 +1664,9 @@ static void\n qca8k_port_bridge_leave(struct dsa_switch *ds, int port, struct net_device *br)\n {\n \tstruct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;\n-\tint i;\n+\tint cpu_port, i;\n+\n+\tcpu_port = dsa_to_port(ds, port)->cpu_dp->index;\n \n \tfor (i = 1; i < QCA8K_NUM_PORTS; i++) {\n \t\tif (dsa_to_port(ds, i)->bridge_dev != br)\n@@ -1662,7 +1683,7 @@ qca8k_port_bridge_leave(struct dsa_switc\n \t * this port\n \t */\n \tqca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),\n-\t\t  QCA8K_PORT_LOOKUP_MEMBER, BIT(QCA8K_CPU_PORT));\n+\t\t  QCA8K_PORT_LOOKUP_MEMBER, BIT(cpu_port));\n }\n \n static int\n--- a/drivers/net/dsa/qca8k.h\n+++ b/drivers/net/dsa/qca8k.h\n@@ -24,8 +24,6 @@\n \n #define QCA8K_NUM_FDB_RECORDS\t\t\t\t2048\n \n-#define QCA8K_CPU_PORT\t\t\t\t\t0\n-\n #define QCA8K_PORT_VID_DEF\t\t\t\t1\n \n /* Global control registers */\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/747-v5.16-06-net-dsa-qca8k-rework-rgmii-delay-logic-and-scan-for-.patch",
    "content": "From 5654ec78dd7e64b1e04777b24007344329e6a63b Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Thu, 14 Oct 2021 00:39:11 +0200\nSubject: net: dsa: qca8k: rework rgmii delay logic and scan for cpu port 6\n\nFuture proof commit. This switch have 2 CPU ports and one valid\nconfiguration is first CPU port set to sgmii and second CPU port set to\nrgmii-id. The current implementation detects delay only for CPU port\nzero set to rgmii and doesn't count any delay set in a secondary CPU\nport. Drop the current delay scan function and move it to the sgmii\nparser function to generalize and implicitly add support for secondary\nCPU port set to rgmii-id. Introduce new logic where delay is enabled\nalso with internal delay binding declared and rgmii set as PHY mode.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/dsa/qca8k.c | 165 ++++++++++++++++++++++++------------------------\n drivers/net/dsa/qca8k.h |  10 ++-\n 2 files changed, 89 insertions(+), 86 deletions(-)\n\n--- a/drivers/net/dsa/qca8k.c\n+++ b/drivers/net/dsa/qca8k.c\n@@ -889,68 +889,6 @@ qca8k_setup_mdio_bus(struct qca8k_priv *\n }\n \n static int\n-qca8k_setup_of_rgmii_delay(struct qca8k_priv *priv)\n-{\n-\tstruct device_node *port_dn;\n-\tphy_interface_t mode;\n-\tstruct dsa_port *dp;\n-\tu32 val;\n-\n-\t/* CPU port is already checked */\n-\tdp = dsa_to_port(priv->ds, 0);\n-\n-\tport_dn = dp->dn;\n-\n-\t/* Check if port 0 is set to the correct type */\n-\tof_get_phy_mode(port_dn, &mode);\n-\tif (mode != PHY_INTERFACE_MODE_RGMII_ID &&\n-\t    mode != PHY_INTERFACE_MODE_RGMII_RXID &&\n-\t    mode != PHY_INTERFACE_MODE_RGMII_TXID) {\n-\t\treturn 0;\n-\t}\n-\n-\tswitch (mode) {\n-\tcase PHY_INTERFACE_MODE_RGMII_ID:\n-\tcase PHY_INTERFACE_MODE_RGMII_RXID:\n-\t\tif (of_property_read_u32(port_dn, \"rx-internal-delay-ps\", &val))\n-\t\t\tval = 2;\n-\t\telse\n-\t\t\t/* Switch regs accept value in ns, convert ps to ns */\n-\t\t\tval = val / 1000;\n-\n-\t\tif (val > QCA8K_MAX_DELAY) {\n-\t\t\tdev_err(priv->dev, \"rgmii rx delay is limited to a max value of 3ns, setting to the max value\");\n-\t\t\tval = 3;\n-\t\t}\n-\n-\t\tpriv->rgmii_rx_delay = val;\n-\t\t/* Stop here if we need to check only for rx delay */\n-\t\tif (mode != PHY_INTERFACE_MODE_RGMII_ID)\n-\t\t\tbreak;\n-\n-\t\tfallthrough;\n-\tcase PHY_INTERFACE_MODE_RGMII_TXID:\n-\t\tif (of_property_read_u32(port_dn, \"tx-internal-delay-ps\", &val))\n-\t\t\tval = 1;\n-\t\telse\n-\t\t\t/* Switch regs accept value in ns, convert ps to ns */\n-\t\t\tval = val / 1000;\n-\n-\t\tif (val > QCA8K_MAX_DELAY) {\n-\t\t\tdev_err(priv->dev, \"rgmii tx delay is limited to a max value of 3ns, setting to the max value\");\n-\t\t\tval = 3;\n-\t\t}\n-\n-\t\tpriv->rgmii_tx_delay = val;\n-\t\tbreak;\n-\tdefault:\n-\t\treturn 0;\n-\t}\n-\n-\treturn 0;\n-}\n-\n-static int\n qca8k_setup_mac_pwr_sel(struct qca8k_priv *priv)\n {\n \tu32 mask = 0;\n@@ -996,19 +934,21 @@ static int qca8k_find_cpu_port(struct ds\n static int\n qca8k_parse_port_config(struct qca8k_priv *priv)\n {\n+\tint port, cpu_port_index = 0, ret;\n \tstruct device_node *port_dn;\n \tphy_interface_t mode;\n \tstruct dsa_port *dp;\n-\tint port, ret;\n+\tu32 delay;\n \n \t/* We have 2 CPU port. Check them */\n-\tfor (port = 0; port < QCA8K_NUM_PORTS; port++) {\n+\tfor (port = 0; port < QCA8K_NUM_PORTS && cpu_port_index < QCA8K_NUM_CPU_PORTS; port++) {\n \t\t/* Skip every other port */\n \t\tif (port != 0 && port != 6)\n \t\t\tcontinue;\n \n \t\tdp = dsa_to_port(priv->ds, port);\n \t\tport_dn = dp->dn;\n+\t\tcpu_port_index++;\n \n \t\tif (!of_device_is_available(port_dn))\n \t\t\tcontinue;\n@@ -1017,12 +957,54 @@ qca8k_parse_port_config(struct qca8k_pri\n \t\tif (ret)\n \t\t\tcontinue;\n \n-\t\tif (mode == PHY_INTERFACE_MODE_SGMII) {\n+\t\tswitch (mode) {\n+\t\tcase PHY_INTERFACE_MODE_RGMII:\n+\t\tcase PHY_INTERFACE_MODE_RGMII_ID:\n+\t\tcase PHY_INTERFACE_MODE_RGMII_TXID:\n+\t\tcase PHY_INTERFACE_MODE_RGMII_RXID:\n+\t\t\tdelay = 0;\n+\n+\t\t\tif (!of_property_read_u32(port_dn, \"tx-internal-delay-ps\", &delay))\n+\t\t\t\t/* Switch regs accept value in ns, convert ps to ns */\n+\t\t\t\tdelay = delay / 1000;\n+\t\t\telse if (mode == PHY_INTERFACE_MODE_RGMII_ID ||\n+\t\t\t\t mode == PHY_INTERFACE_MODE_RGMII_TXID)\n+\t\t\t\tdelay = 1;\n+\n+\t\t\tif (delay > QCA8K_MAX_DELAY) {\n+\t\t\t\tdev_err(priv->dev, \"rgmii tx delay is limited to a max value of 3ns, setting to the max value\");\n+\t\t\t\tdelay = 3;\n+\t\t\t}\n+\n+\t\t\tpriv->rgmii_tx_delay[cpu_port_index] = delay;\n+\n+\t\t\tdelay = 0;\n+\n+\t\t\tif (!of_property_read_u32(port_dn, \"rx-internal-delay-ps\", &delay))\n+\t\t\t\t/* Switch regs accept value in ns, convert ps to ns */\n+\t\t\t\tdelay = delay / 1000;\n+\t\t\telse if (mode == PHY_INTERFACE_MODE_RGMII_ID ||\n+\t\t\t\t mode == PHY_INTERFACE_MODE_RGMII_RXID)\n+\t\t\t\tdelay = 2;\n+\n+\t\t\tif (delay > QCA8K_MAX_DELAY) {\n+\t\t\t\tdev_err(priv->dev, \"rgmii rx delay is limited to a max value of 3ns, setting to the max value\");\n+\t\t\t\tdelay = 3;\n+\t\t\t}\n+\n+\t\t\tpriv->rgmii_rx_delay[cpu_port_index] = delay;\n+\n+\t\t\tbreak;\n+\t\tcase PHY_INTERFACE_MODE_SGMII:\n \t\t\tif (of_property_read_bool(port_dn, \"qca,sgmii-txclk-falling-edge\"))\n \t\t\t\tpriv->sgmii_tx_clk_falling_edge = true;\n \n \t\t\tif (of_property_read_bool(port_dn, \"qca,sgmii-rxclk-falling-edge\"))\n \t\t\t\tpriv->sgmii_rx_clk_falling_edge = true;\n+\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tcontinue;\n \t\t}\n \t}\n \n@@ -1059,10 +1041,6 @@ qca8k_setup(struct dsa_switch *ds)\n \tif (ret)\n \t\treturn ret;\n \n-\tret = qca8k_setup_of_rgmii_delay(priv);\n-\tif (ret)\n-\t\treturn ret;\n-\n \tret = qca8k_setup_mac_pwr_sel(priv);\n \tif (ret)\n \t\treturn ret;\n@@ -1229,8 +1207,8 @@ qca8k_phylink_mac_config(struct dsa_swit\n \t\t\t const struct phylink_link_state *state)\n {\n \tstruct qca8k_priv *priv = ds->priv;\n-\tu32 reg, val;\n-\tint ret;\n+\tint cpu_port_index, ret;\n+\tu32 reg, val, delay;\n \n \tswitch (port) {\n \tcase 0: /* 1st CPU port */\n@@ -1242,6 +1220,7 @@ qca8k_phylink_mac_config(struct dsa_swit\n \t\t\treturn;\n \n \t\treg = QCA8K_REG_PORT0_PAD_CTRL;\n+\t\tcpu_port_index = QCA8K_CPU_PORT0;\n \t\tbreak;\n \tcase 1:\n \tcase 2:\n@@ -1260,6 +1239,7 @@ qca8k_phylink_mac_config(struct dsa_swit\n \t\t\treturn;\n \n \t\treg = QCA8K_REG_PORT6_PAD_CTRL;\n+\t\tcpu_port_index = QCA8K_CPU_PORT6;\n \t\tbreak;\n \tdefault:\n \t\tdev_err(ds->dev, \"%s: unsupported port: %i\\n\", __func__, port);\n@@ -1274,23 +1254,40 @@ qca8k_phylink_mac_config(struct dsa_swit\n \n \tswitch (state->interface) {\n \tcase PHY_INTERFACE_MODE_RGMII:\n-\t\t/* RGMII mode means no delay so don't enable the delay */\n-\t\tqca8k_write(priv, reg, QCA8K_PORT_PAD_RGMII_EN);\n-\t\tbreak;\n \tcase PHY_INTERFACE_MODE_RGMII_ID:\n \tcase PHY_INTERFACE_MODE_RGMII_TXID:\n \tcase PHY_INTERFACE_MODE_RGMII_RXID:\n-\t\t/* RGMII_ID needs internal delay. This is enabled through\n-\t\t * PORT5_PAD_CTRL for all ports, rather than individual port\n-\t\t * registers\n+\t\tval = QCA8K_PORT_PAD_RGMII_EN;\n+\n+\t\t/* Delay can be declared in 3 different way.\n+\t\t * Mode to rgmii and internal-delay standard binding defined\n+\t\t * rgmii-id or rgmii-tx/rx phy mode set.\n+\t\t * The parse logic set a delay different than 0 only when one\n+\t\t * of the 3 different way is used. In all other case delay is\n+\t\t * not enabled. With ID or TX/RXID delay is enabled and set\n+\t\t * to the default and recommended value.\n+\t\t */\n+\t\tif (priv->rgmii_tx_delay[cpu_port_index]) {\n+\t\t\tdelay = priv->rgmii_tx_delay[cpu_port_index];\n+\n+\t\t\tval |= QCA8K_PORT_PAD_RGMII_TX_DELAY(delay) |\n+\t\t\t       QCA8K_PORT_PAD_RGMII_TX_DELAY_EN;\n+\t\t}\n+\n+\t\tif (priv->rgmii_rx_delay[cpu_port_index]) {\n+\t\t\tdelay = priv->rgmii_rx_delay[cpu_port_index];\n+\n+\t\t\tval |= QCA8K_PORT_PAD_RGMII_RX_DELAY(delay) |\n+\t\t\t       QCA8K_PORT_PAD_RGMII_RX_DELAY_EN;\n+\t\t}\n+\n+\t\t/* Set RGMII delay based on the selected values */\n+\t\tqca8k_write(priv, reg, val);\n+\n+\t\t/* QCA8337 requires to set rgmii rx delay for all ports.\n+\t\t * This is enabled through PORT5_PAD_CTRL for all ports,\n+\t\t * rather than individual port registers.\n \t\t */\n-\t\tqca8k_write(priv, reg,\n-\t\t\t    QCA8K_PORT_PAD_RGMII_EN |\n-\t\t\t    QCA8K_PORT_PAD_RGMII_TX_DELAY(priv->rgmii_tx_delay) |\n-\t\t\t    QCA8K_PORT_PAD_RGMII_RX_DELAY(priv->rgmii_rx_delay) |\n-\t\t\t    QCA8K_PORT_PAD_RGMII_TX_DELAY_EN |\n-\t\t\t    QCA8K_PORT_PAD_RGMII_RX_DELAY_EN);\n-\t\t/* QCA8337 requires to set rgmii rx delay */\n \t\tif (priv->switch_id == QCA8K_ID_QCA8337)\n \t\t\tqca8k_write(priv, QCA8K_REG_PORT5_PAD_CTRL,\n \t\t\t\t    QCA8K_PORT_PAD_RGMII_RX_DELAY_EN);\n--- a/drivers/net/dsa/qca8k.h\n+++ b/drivers/net/dsa/qca8k.h\n@@ -13,6 +13,7 @@\n #include <linux/gpio.h>\n \n #define QCA8K_NUM_PORTS\t\t\t\t\t7\n+#define QCA8K_NUM_CPU_PORTS\t\t\t\t2\n #define QCA8K_MAX_MTU\t\t\t\t\t9000\n \n #define PHY_ID_QCA8327\t\t\t\t\t0x004dd034\n@@ -255,13 +256,18 @@ struct qca8k_match_data {\n \tu8 id;\n };\n \n+enum {\n+\tQCA8K_CPU_PORT0,\n+\tQCA8K_CPU_PORT6,\n+};\n+\n struct qca8k_priv {\n \tu8 switch_id;\n \tu8 switch_revision;\n-\tu8 rgmii_tx_delay;\n-\tu8 rgmii_rx_delay;\n \tbool sgmii_rx_clk_falling_edge;\n \tbool sgmii_tx_clk_falling_edge;\n+\tu8 rgmii_rx_delay[QCA8K_NUM_CPU_PORTS]; /* 0: CPU port0, 1: CPU port6 */\n+\tu8 rgmii_tx_delay[QCA8K_NUM_CPU_PORTS]; /* 0: CPU port0, 1: CPU port6 */\n \tbool legacy_phy_port_mapping;\n \tstruct regmap *regmap;\n \tstruct mii_bus *bus;\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/747-v5.16-07-dt-bindings-net-dsa-qca8k-Document-qca-sgmii-enable-.patch",
    "content": "From 13ad5ccc093ff448b99ac7e138e91e78796adb48 Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Thu, 14 Oct 2021 00:39:12 +0200\nSubject: dt-bindings: net: dsa: qca8k: Document qca,sgmii-enable-pll\n\nDocument qca,sgmii-enable-pll binding used in the CPU nodes to\nenable SGMII PLL on MAC config.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n Documentation/devicetree/bindings/net/dsa/qca8k.txt | 10 ++++++++++\n 1 file changed, 10 insertions(+)\n\n--- a/Documentation/devicetree/bindings/net/dsa/qca8k.txt\n+++ b/Documentation/devicetree/bindings/net/dsa/qca8k.txt\n@@ -45,6 +45,16 @@ A CPU port node has the following option\n                                 Mostly used in qca8327 with CPU port 0 set to\n                                 sgmii.\n - qca,sgmii-txclk-falling-edge: Set the transmit clock phase to falling edge.\n+- qca,sgmii-enable-pll  : For SGMII CPU port, explicitly enable PLL, TX and RX\n+                          chain along with Signal Detection.\n+                          This should NOT be enabled for qca8327. If enabled with\n+                          qca8327 the sgmii port won't correctly init and an err\n+                          is printed.\n+                          This can be required for qca8337 switch with revision 2.\n+                          A warning is displayed when used with revision greater\n+                          2.\n+                          With CPU port set to sgmii and qca8337 it is advised\n+                          to set this unless a communication problem is observed.\n \n For QCA8K the 'fixed-link' sub-node supports only the following properties:\n \n"
  },
  {
    "path": "target/linux/generic/backport-5.10/747-v5.16-08-net-dsa-qca8k-add-explicit-SGMII-PLL-enable.patch",
    "content": "From bbc4799e8bb6c397e3b3fec13de68e179f5db9ff Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Thu, 14 Oct 2021 00:39:13 +0200\nSubject: net: dsa: qca8k: add explicit SGMII PLL enable\n\nSupport enabling PLL on the SGMII CPU port. Some device require this\nspecial configuration or no traffic is transmitted and the switch\ndoesn't work at all. A dedicated binding is added to the CPU node\nport to apply the correct reg on mac config.\nFail to correctly configure sgmii with qca8327 switch and warn if pll is\nused on qca8337 with a revision greater than 1.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nReviewed-by: Florian Fainelli <f.fainelli@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/dsa/qca8k.c | 19 +++++++++++++++++--\n drivers/net/dsa/qca8k.h |  1 +\n 2 files changed, 18 insertions(+), 2 deletions(-)\n\n--- a/drivers/net/dsa/qca8k.c\n+++ b/drivers/net/dsa/qca8k.c\n@@ -1002,6 +1002,18 @@ qca8k_parse_port_config(struct qca8k_pri\n \t\t\tif (of_property_read_bool(port_dn, \"qca,sgmii-rxclk-falling-edge\"))\n \t\t\t\tpriv->sgmii_rx_clk_falling_edge = true;\n \n+\t\t\tif (of_property_read_bool(port_dn, \"qca,sgmii-enable-pll\")) {\n+\t\t\t\tpriv->sgmii_enable_pll = true;\n+\n+\t\t\t\tif (priv->switch_id == QCA8K_ID_QCA8327) {\n+\t\t\t\t\tdev_err(priv->dev, \"SGMII PLL should NOT be enabled for qca8327. Aborting enabling\");\n+\t\t\t\t\tpriv->sgmii_enable_pll = false;\n+\t\t\t\t}\n+\n+\t\t\t\tif (priv->switch_revision < 2)\n+\t\t\t\t\tdev_warn(priv->dev, \"SGMII PLL should NOT be enabled for qca8337 with revision 2 or more.\");\n+\t\t\t}\n+\n \t\t\tbreak;\n \t\tdefault:\n \t\t\tcontinue;\n@@ -1312,8 +1324,11 @@ qca8k_phylink_mac_config(struct dsa_swit\n \t\tif (ret)\n \t\t\treturn;\n \n-\t\tval |= QCA8K_SGMII_EN_PLL | QCA8K_SGMII_EN_RX |\n-\t\t\tQCA8K_SGMII_EN_TX | QCA8K_SGMII_EN_SD;\n+\t\tval |= QCA8K_SGMII_EN_SD;\n+\n+\t\tif (priv->sgmii_enable_pll)\n+\t\t\tval |= QCA8K_SGMII_EN_PLL | QCA8K_SGMII_EN_RX |\n+\t\t\t       QCA8K_SGMII_EN_TX;\n \n \t\tif (dsa_is_cpu_port(ds, port)) {\n \t\t\t/* CPU port, we're talking to the CPU MAC, be a PHY */\n--- a/drivers/net/dsa/qca8k.h\n+++ b/drivers/net/dsa/qca8k.h\n@@ -266,6 +266,7 @@ struct qca8k_priv {\n \tu8 switch_revision;\n \tbool sgmii_rx_clk_falling_edge;\n \tbool sgmii_tx_clk_falling_edge;\n+\tbool sgmii_enable_pll;\n \tu8 rgmii_rx_delay[QCA8K_NUM_CPU_PORTS]; /* 0: CPU port0, 1: CPU port6 */\n \tu8 rgmii_tx_delay[QCA8K_NUM_CPU_PORTS]; /* 0: CPU port0, 1: CPU port6 */\n \tbool legacy_phy_port_mapping;\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/747-v5.16-09-dt-bindings-net-dsa-qca8k-Document-qca-led-open-drai.patch",
    "content": "From 924087c5c3d41553700b0eb83ca2a53b91643dca Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Thu, 14 Oct 2021 00:39:14 +0200\nSubject: dt-bindings: net: dsa: qca8k: Document qca,led-open-drain binding\n\nDocument new binding qca,ignore-power-on-sel used to ignore\npower on strapping and use sw regs instead.\nDocument qca,led-open.drain to set led to open drain mode, the\nqca,ignore-power-on-sel is mandatory with this enabled or an error will\nbe reported.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n Documentation/devicetree/bindings/net/dsa/qca8k.txt | 11 +++++++++++\n 1 file changed, 11 insertions(+)\n\n--- a/Documentation/devicetree/bindings/net/dsa/qca8k.txt\n+++ b/Documentation/devicetree/bindings/net/dsa/qca8k.txt\n@@ -13,6 +13,17 @@ Required properties:\n Optional properties:\n \n - reset-gpios: GPIO to be used to reset the whole device\n+- qca,ignore-power-on-sel: Ignore power on pin strapping to configure led open\n+                           drain or eeprom presence. This is needed for broken\n+                           devices that have wrong configuration or when the oem\n+                           decided to not use pin strapping and fallback to sw\n+                           regs.\n+- qca,led-open-drain: Set leds to open-drain mode. This requires the\n+                      qca,ignore-power-on-sel to be set or the driver will fail\n+                      to probe. This is needed if the oem doesn't use pin\n+                      strapping to set this mode and prefers to set it using sw\n+                      regs. The pin strapping related to led open drain mode is\n+                      the pin B68 for QCA832x and B49 for QCA833x\n \n Subnodes:\n \n"
  },
  {
    "path": "target/linux/generic/backport-5.10/747-v5.16-10-net-dsa-qca8k-add-support-for-pws-config-reg.patch",
    "content": "From 362bb238d8bf1470424214a8a5968d9c6cce68fa Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Thu, 14 Oct 2021 00:39:15 +0200\nSubject: net: dsa: qca8k: add support for pws config reg\n\nSome qca8327 switch require to force the ignore of power on sel\nstrapping. Some switch require to set the led open drain mode in regs\ninstead of using strapping. While most of the device implements this\nusing the correct way using pin strapping, there are still some broken\ndevice that require to be set using sw regs.\nIntroduce a new binding and support these special configuration.\nAs led open drain require to ignore pin strapping to work, the probe\nfails with EINVAL error with incorrect configuration.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nReviewed-by: Florian Fainelli <f.fainelli@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/dsa/qca8k.c | 39 +++++++++++++++++++++++++++++++++++++++\n drivers/net/dsa/qca8k.h |  6 ++++++\n 2 files changed, 45 insertions(+)\n\n--- a/drivers/net/dsa/qca8k.c\n+++ b/drivers/net/dsa/qca8k.c\n@@ -932,6 +932,41 @@ static int qca8k_find_cpu_port(struct ds\n }\n \n static int\n+qca8k_setup_of_pws_reg(struct qca8k_priv *priv)\n+{\n+\tstruct device_node *node = priv->dev->of_node;\n+\tu32 val = 0;\n+\tint ret;\n+\n+\t/* QCA8327 require to set to the correct mode.\n+\t * His bigger brother QCA8328 have the 172 pin layout.\n+\t * Should be applied by default but we set this just to make sure.\n+\t */\n+\tif (priv->switch_id == QCA8K_ID_QCA8327) {\n+\t\tret = qca8k_rmw(priv, QCA8K_REG_PWS, QCA8327_PWS_PACKAGE148_EN,\n+\t\t\t\tQCA8327_PWS_PACKAGE148_EN);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\t}\n+\n+\tif (of_property_read_bool(node, \"qca,ignore-power-on-sel\"))\n+\t\tval |= QCA8K_PWS_POWER_ON_SEL;\n+\n+\tif (of_property_read_bool(node, \"qca,led-open-drain\")) {\n+\t\tif (!(val & QCA8K_PWS_POWER_ON_SEL)) {\n+\t\t\tdev_err(priv->dev, \"qca,led-open-drain require qca,ignore-power-on-sel to be set.\");\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\n+\t\tval |= QCA8K_PWS_LED_OPEN_EN_CSR;\n+\t}\n+\n+\treturn qca8k_rmw(priv, QCA8K_REG_PWS,\n+\t\t\tQCA8K_PWS_LED_OPEN_EN_CSR | QCA8K_PWS_POWER_ON_SEL,\n+\t\t\tval);\n+}\n+\n+static int\n qca8k_parse_port_config(struct qca8k_priv *priv)\n {\n \tint port, cpu_port_index = 0, ret;\n@@ -1053,6 +1088,10 @@ qca8k_setup(struct dsa_switch *ds)\n \tif (ret)\n \t\treturn ret;\n \n+\tret = qca8k_setup_of_pws_reg(priv);\n+\tif (ret)\n+\t\treturn ret;\n+\n \tret = qca8k_setup_mac_pwr_sel(priv);\n \tif (ret)\n \t\treturn ret;\n--- a/drivers/net/dsa/qca8k.h\n+++ b/drivers/net/dsa/qca8k.h\n@@ -46,6 +46,12 @@\n #define   QCA8K_MAX_DELAY\t\t\t\t3\n #define   QCA8K_PORT_PAD_SGMII_EN\t\t\tBIT(7)\n #define QCA8K_REG_PWS\t\t\t\t\t0x010\n+#define   QCA8K_PWS_POWER_ON_SEL\t\t\tBIT(31)\n+/* This reg is only valid for QCA832x and toggle the package\n+ * type from 176 pin (by default) to 148 pin used on QCA8327\n+ */\n+#define   QCA8327_PWS_PACKAGE148_EN\t\t\tBIT(30)\n+#define   QCA8K_PWS_LED_OPEN_EN_CSR\t\t\tBIT(24)\n #define   QCA8K_PWS_SERDES_AEN_DIS\t\t\tBIT(7)\n #define QCA8K_REG_MODULE_EN\t\t\t\t0x030\n #define   QCA8K_MODULE_EN_MIB\t\t\t\tBIT(0)\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/747-v5.16-11-dt-bindings-net-dsa-qca8k-document-support-for-qca83.patch",
    "content": "From ed7988d77fbfb79366b68f9e7fa60a6080da23d4 Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Thu, 14 Oct 2021 00:39:16 +0200\nSubject: dt-bindings: net: dsa: qca8k: document support for qca8328\n\nQCA8328 is the bigger brother of qca8327. Document the new compatible\nbinding and add some information to understand the various switch\ncompatible.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nReviewed-by: Florian Fainelli <f.fainelli@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n Documentation/devicetree/bindings/net/dsa/qca8k.txt | 7 ++++---\n 1 file changed, 4 insertions(+), 3 deletions(-)\n\n--- a/Documentation/devicetree/bindings/net/dsa/qca8k.txt\n+++ b/Documentation/devicetree/bindings/net/dsa/qca8k.txt\n@@ -3,9 +3,10 @@\n Required properties:\n \n - compatible: should be one of:\n-    \"qca,qca8327\"\n-    \"qca,qca8334\"\n-    \"qca,qca8337\"\n+    \"qca,qca8328\": referenced as AR8328(N)-AK1(A/B) QFN 176 pin package\n+    \"qca,qca8327\": referenced as AR8327(N)-AL1A DR-QFN 148 pin package\n+    \"qca,qca8334\": referenced as QCA8334-AL3C QFN 88 pin package\n+    \"qca,qca8337\": referenced as QCA8337N-AL3(B/C) DR-QFN 148 pin package\n \n - #size-cells: must be 0\n - #address-cells: must be 1\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/747-v5.16-12-net-dsa-qca8k-add-support-for-QCA8328.patch",
    "content": "From f477d1c8bdbef4f400718238e350f16f521d2a3e Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Thu, 14 Oct 2021 00:39:17 +0200\nSubject: net: dsa: qca8k: add support for QCA8328\n\nQCA8328 switch is the bigger brother of the qca8327. Same regs different\nchip. Change the function to set the correct pin layout and introduce a\nnew match_data to differentiate the 2 switch as they have the same ID\nand their internal PHY have the same ID.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nReviewed-by: Florian Fainelli <f.fainelli@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/dsa/qca8k.c | 19 ++++++++++++++++---\n drivers/net/dsa/qca8k.h |  1 +\n 2 files changed, 17 insertions(+), 3 deletions(-)\n\n--- a/drivers/net/dsa/qca8k.c\n+++ b/drivers/net/dsa/qca8k.c\n@@ -935,6 +935,7 @@ static int\n qca8k_setup_of_pws_reg(struct qca8k_priv *priv)\n {\n \tstruct device_node *node = priv->dev->of_node;\n+\tconst struct qca8k_match_data *data;\n \tu32 val = 0;\n \tint ret;\n \n@@ -943,8 +944,14 @@ qca8k_setup_of_pws_reg(struct qca8k_priv\n \t * Should be applied by default but we set this just to make sure.\n \t */\n \tif (priv->switch_id == QCA8K_ID_QCA8327) {\n+\t\tdata = of_device_get_match_data(priv->dev);\n+\n+\t\t/* Set the correct package of 148 pin for QCA8327 */\n+\t\tif (data->reduced_package)\n+\t\t\tval |= QCA8327_PWS_PACKAGE148_EN;\n+\n \t\tret = qca8k_rmw(priv, QCA8K_REG_PWS, QCA8327_PWS_PACKAGE148_EN,\n-\t\t\t\tQCA8327_PWS_PACKAGE148_EN);\n+\t\t\t\tval);\n \t\tif (ret)\n \t\t\treturn ret;\n \t}\n@@ -2098,7 +2105,12 @@ static int qca8k_resume(struct device *d\n static SIMPLE_DEV_PM_OPS(qca8k_pm_ops,\n \t\t\t qca8k_suspend, qca8k_resume);\n \n-static const struct qca8k_match_data qca832x = {\n+static const struct qca8k_match_data qca8327 = {\n+\t.id = QCA8K_ID_QCA8327,\n+\t.reduced_package = true,\n+};\n+\n+static const struct qca8k_match_data qca8328 = {\n \t.id = QCA8K_ID_QCA8327,\n };\n \n@@ -2107,7 +2119,8 @@ static const struct qca8k_match_data qca\n };\n \n static const struct of_device_id qca8k_of_match[] = {\n-\t{ .compatible = \"qca,qca8327\", .data = &qca832x },\n+\t{ .compatible = \"qca,qca8327\", .data = &qca8327 },\n+\t{ .compatible = \"qca,qca8328\", .data = &qca8328 },\n \t{ .compatible = \"qca,qca8334\", .data = &qca833x },\n \t{ .compatible = \"qca,qca8337\", .data = &qca833x },\n \t{ /* sentinel */ },\n--- a/drivers/net/dsa/qca8k.h\n+++ b/drivers/net/dsa/qca8k.h\n@@ -260,6 +260,7 @@ struct ar8xxx_port_status {\n \n struct qca8k_match_data {\n \tu8 id;\n+\tbool reduced_package;\n };\n \n enum {\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/747-v5.16-13-net-dsa-qca8k-set-internal-delay-also-for-sgmii.patch",
    "content": "From cef08115846e581f80ff99abf7bf218da1840616 Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Thu, 14 Oct 2021 00:39:18 +0200\nSubject: net: dsa: qca8k: set internal delay also for sgmii\n\nQCA original code report port instability and sa that SGMII also require\nto set internal delay. Generalize the rgmii delay function and apply the\nadvised value if they are not defined in DT.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/dsa/qca8k.c | 88 +++++++++++++++++++++++++++++++++----------------\n drivers/net/dsa/qca8k.h |  2 ++\n 2 files changed, 62 insertions(+), 28 deletions(-)\n\n--- a/drivers/net/dsa/qca8k.c\n+++ b/drivers/net/dsa/qca8k.c\n@@ -1004,6 +1004,7 @@ qca8k_parse_port_config(struct qca8k_pri\n \t\tcase PHY_INTERFACE_MODE_RGMII_ID:\n \t\tcase PHY_INTERFACE_MODE_RGMII_TXID:\n \t\tcase PHY_INTERFACE_MODE_RGMII_RXID:\n+\t\tcase PHY_INTERFACE_MODE_SGMII:\n \t\t\tdelay = 0;\n \n \t\t\tif (!of_property_read_u32(port_dn, \"tx-internal-delay-ps\", &delay))\n@@ -1036,8 +1037,13 @@ qca8k_parse_port_config(struct qca8k_pri\n \n \t\t\tpriv->rgmii_rx_delay[cpu_port_index] = delay;\n \n-\t\t\tbreak;\n-\t\tcase PHY_INTERFACE_MODE_SGMII:\n+\t\t\t/* Skip sgmii parsing for rgmii* mode */\n+\t\t\tif (mode == PHY_INTERFACE_MODE_RGMII ||\n+\t\t\t    mode == PHY_INTERFACE_MODE_RGMII_ID ||\n+\t\t\t    mode == PHY_INTERFACE_MODE_RGMII_TXID ||\n+\t\t\t    mode == PHY_INTERFACE_MODE_RGMII_RXID)\n+\t\t\t\tbreak;\n+\n \t\t\tif (of_property_read_bool(port_dn, \"qca,sgmii-txclk-falling-edge\"))\n \t\t\t\tpriv->sgmii_tx_clk_falling_edge = true;\n \n@@ -1261,12 +1267,53 @@ qca8k_setup(struct dsa_switch *ds)\n }\n \n static void\n+qca8k_mac_config_setup_internal_delay(struct qca8k_priv *priv, int cpu_port_index,\n+\t\t\t\t      u32 reg)\n+{\n+\tu32 delay, val = 0;\n+\tint ret;\n+\n+\t/* Delay can be declared in 3 different way.\n+\t * Mode to rgmii and internal-delay standard binding defined\n+\t * rgmii-id or rgmii-tx/rx phy mode set.\n+\t * The parse logic set a delay different than 0 only when one\n+\t * of the 3 different way is used. In all other case delay is\n+\t * not enabled. With ID or TX/RXID delay is enabled and set\n+\t * to the default and recommended value.\n+\t */\n+\tif (priv->rgmii_tx_delay[cpu_port_index]) {\n+\t\tdelay = priv->rgmii_tx_delay[cpu_port_index];\n+\n+\t\tval |= QCA8K_PORT_PAD_RGMII_TX_DELAY(delay) |\n+\t\t\tQCA8K_PORT_PAD_RGMII_TX_DELAY_EN;\n+\t}\n+\n+\tif (priv->rgmii_rx_delay[cpu_port_index]) {\n+\t\tdelay = priv->rgmii_rx_delay[cpu_port_index];\n+\n+\t\tval |= QCA8K_PORT_PAD_RGMII_RX_DELAY(delay) |\n+\t\t\tQCA8K_PORT_PAD_RGMII_RX_DELAY_EN;\n+\t}\n+\n+\t/* Set RGMII delay based on the selected values */\n+\tret = qca8k_rmw(priv, reg,\n+\t\t\tQCA8K_PORT_PAD_RGMII_TX_DELAY_MASK |\n+\t\t\tQCA8K_PORT_PAD_RGMII_RX_DELAY_MASK |\n+\t\t\tQCA8K_PORT_PAD_RGMII_TX_DELAY_EN |\n+\t\t\tQCA8K_PORT_PAD_RGMII_RX_DELAY_EN,\n+\t\t\tval);\n+\tif (ret)\n+\t\tdev_err(priv->dev, \"Failed to set internal delay for CPU port%d\",\n+\t\t\tcpu_port_index == QCA8K_CPU_PORT0 ? 0 : 6);\n+}\n+\n+static void\n qca8k_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode,\n \t\t\t const struct phylink_link_state *state)\n {\n \tstruct qca8k_priv *priv = ds->priv;\n \tint cpu_port_index, ret;\n-\tu32 reg, val, delay;\n+\tu32 reg, val;\n \n \tswitch (port) {\n \tcase 0: /* 1st CPU port */\n@@ -1315,32 +1362,10 @@ qca8k_phylink_mac_config(struct dsa_swit\n \tcase PHY_INTERFACE_MODE_RGMII_ID:\n \tcase PHY_INTERFACE_MODE_RGMII_TXID:\n \tcase PHY_INTERFACE_MODE_RGMII_RXID:\n-\t\tval = QCA8K_PORT_PAD_RGMII_EN;\n-\n-\t\t/* Delay can be declared in 3 different way.\n-\t\t * Mode to rgmii and internal-delay standard binding defined\n-\t\t * rgmii-id or rgmii-tx/rx phy mode set.\n-\t\t * The parse logic set a delay different than 0 only when one\n-\t\t * of the 3 different way is used. In all other case delay is\n-\t\t * not enabled. With ID or TX/RXID delay is enabled and set\n-\t\t * to the default and recommended value.\n-\t\t */\n-\t\tif (priv->rgmii_tx_delay[cpu_port_index]) {\n-\t\t\tdelay = priv->rgmii_tx_delay[cpu_port_index];\n-\n-\t\t\tval |= QCA8K_PORT_PAD_RGMII_TX_DELAY(delay) |\n-\t\t\t       QCA8K_PORT_PAD_RGMII_TX_DELAY_EN;\n-\t\t}\n-\n-\t\tif (priv->rgmii_rx_delay[cpu_port_index]) {\n-\t\t\tdelay = priv->rgmii_rx_delay[cpu_port_index];\n-\n-\t\t\tval |= QCA8K_PORT_PAD_RGMII_RX_DELAY(delay) |\n-\t\t\t       QCA8K_PORT_PAD_RGMII_RX_DELAY_EN;\n-\t\t}\n+\t\tqca8k_write(priv, reg, QCA8K_PORT_PAD_RGMII_EN);\n \n-\t\t/* Set RGMII delay based on the selected values */\n-\t\tqca8k_write(priv, reg, val);\n+\t\t/* Configure rgmii delay */\n+\t\tqca8k_mac_config_setup_internal_delay(priv, cpu_port_index, reg);\n \n \t\t/* QCA8337 requires to set rgmii rx delay for all ports.\n \t\t * This is enabled through PORT5_PAD_CTRL for all ports,\n@@ -1411,6 +1436,13 @@ qca8k_phylink_mac_config(struct dsa_swit\n \t\t\t\t\tQCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE |\n \t\t\t\t\tQCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE,\n \t\t\t\t\tval);\n+\n+\t\t/* From original code is reported port instability as SGMII also\n+\t\t * require delay set. Apply advised values here or take them from DT.\n+\t\t */\n+\t\tif (state->interface == PHY_INTERFACE_MODE_SGMII)\n+\t\t\tqca8k_mac_config_setup_internal_delay(priv, cpu_port_index, reg);\n+\n \t\tbreak;\n \tdefault:\n \t\tdev_err(ds->dev, \"xMII mode %s not supported for port %d\\n\",\n--- a/drivers/net/dsa/qca8k.h\n+++ b/drivers/net/dsa/qca8k.h\n@@ -39,7 +39,9 @@\n #define QCA8K_REG_PORT5_PAD_CTRL\t\t\t0x008\n #define QCA8K_REG_PORT6_PAD_CTRL\t\t\t0x00c\n #define   QCA8K_PORT_PAD_RGMII_EN\t\t\tBIT(26)\n+#define   QCA8K_PORT_PAD_RGMII_TX_DELAY_MASK\t\tGENMASK(23, 22)\n #define   QCA8K_PORT_PAD_RGMII_TX_DELAY(x)\t\t((x) << 22)\n+#define   QCA8K_PORT_PAD_RGMII_RX_DELAY_MASK\t\tGENMASK(21, 20)\n #define   QCA8K_PORT_PAD_RGMII_RX_DELAY(x)\t\t((x) << 20)\n #define\t  QCA8K_PORT_PAD_RGMII_TX_DELAY_EN\t\tBIT(25)\n #define   QCA8K_PORT_PAD_RGMII_RX_DELAY_EN\t\tBIT(24)\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/747-v5.16-14-net-dsa-qca8k-move-port-config-to-dedicated-struct.patch",
    "content": "From fd0bb28c547f7c8affb1691128cece38f5b626a1 Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Thu, 14 Oct 2021 00:39:19 +0200\nSubject: net: dsa: qca8k: move port config to dedicated struct\n\nMove ports related config to dedicated struct to keep things organized.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nReviewed-by: Florian Fainelli <f.fainelli@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/dsa/qca8k.c | 26 +++++++++++++-------------\n drivers/net/dsa/qca8k.h | 10 +++++++---\n 2 files changed, 20 insertions(+), 16 deletions(-)\n\n--- a/drivers/net/dsa/qca8k.c\n+++ b/drivers/net/dsa/qca8k.c\n@@ -1019,7 +1019,7 @@ qca8k_parse_port_config(struct qca8k_pri\n \t\t\t\tdelay = 3;\n \t\t\t}\n \n-\t\t\tpriv->rgmii_tx_delay[cpu_port_index] = delay;\n+\t\t\tpriv->ports_config.rgmii_tx_delay[cpu_port_index] = delay;\n \n \t\t\tdelay = 0;\n \n@@ -1035,7 +1035,7 @@ qca8k_parse_port_config(struct qca8k_pri\n \t\t\t\tdelay = 3;\n \t\t\t}\n \n-\t\t\tpriv->rgmii_rx_delay[cpu_port_index] = delay;\n+\t\t\tpriv->ports_config.rgmii_rx_delay[cpu_port_index] = delay;\n \n \t\t\t/* Skip sgmii parsing for rgmii* mode */\n \t\t\tif (mode == PHY_INTERFACE_MODE_RGMII ||\n@@ -1045,17 +1045,17 @@ qca8k_parse_port_config(struct qca8k_pri\n \t\t\t\tbreak;\n \n \t\t\tif (of_property_read_bool(port_dn, \"qca,sgmii-txclk-falling-edge\"))\n-\t\t\t\tpriv->sgmii_tx_clk_falling_edge = true;\n+\t\t\t\tpriv->ports_config.sgmii_tx_clk_falling_edge = true;\n \n \t\t\tif (of_property_read_bool(port_dn, \"qca,sgmii-rxclk-falling-edge\"))\n-\t\t\t\tpriv->sgmii_rx_clk_falling_edge = true;\n+\t\t\t\tpriv->ports_config.sgmii_rx_clk_falling_edge = true;\n \n \t\t\tif (of_property_read_bool(port_dn, \"qca,sgmii-enable-pll\")) {\n-\t\t\t\tpriv->sgmii_enable_pll = true;\n+\t\t\t\tpriv->ports_config.sgmii_enable_pll = true;\n \n \t\t\t\tif (priv->switch_id == QCA8K_ID_QCA8327) {\n \t\t\t\t\tdev_err(priv->dev, \"SGMII PLL should NOT be enabled for qca8327. Aborting enabling\");\n-\t\t\t\t\tpriv->sgmii_enable_pll = false;\n+\t\t\t\t\tpriv->ports_config.sgmii_enable_pll = false;\n \t\t\t\t}\n \n \t\t\t\tif (priv->switch_revision < 2)\n@@ -1281,15 +1281,15 @@ qca8k_mac_config_setup_internal_delay(st\n \t * not enabled. With ID or TX/RXID delay is enabled and set\n \t * to the default and recommended value.\n \t */\n-\tif (priv->rgmii_tx_delay[cpu_port_index]) {\n-\t\tdelay = priv->rgmii_tx_delay[cpu_port_index];\n+\tif (priv->ports_config.rgmii_tx_delay[cpu_port_index]) {\n+\t\tdelay = priv->ports_config.rgmii_tx_delay[cpu_port_index];\n \n \t\tval |= QCA8K_PORT_PAD_RGMII_TX_DELAY(delay) |\n \t\t\tQCA8K_PORT_PAD_RGMII_TX_DELAY_EN;\n \t}\n \n-\tif (priv->rgmii_rx_delay[cpu_port_index]) {\n-\t\tdelay = priv->rgmii_rx_delay[cpu_port_index];\n+\tif (priv->ports_config.rgmii_rx_delay[cpu_port_index]) {\n+\t\tdelay = priv->ports_config.rgmii_rx_delay[cpu_port_index];\n \n \t\tval |= QCA8K_PORT_PAD_RGMII_RX_DELAY(delay) |\n \t\t\tQCA8K_PORT_PAD_RGMII_RX_DELAY_EN;\n@@ -1397,7 +1397,7 @@ qca8k_phylink_mac_config(struct dsa_swit\n \n \t\tval |= QCA8K_SGMII_EN_SD;\n \n-\t\tif (priv->sgmii_enable_pll)\n+\t\tif (priv->ports_config.sgmii_enable_pll)\n \t\t\tval |= QCA8K_SGMII_EN_PLL | QCA8K_SGMII_EN_RX |\n \t\t\t       QCA8K_SGMII_EN_TX;\n \n@@ -1425,10 +1425,10 @@ qca8k_phylink_mac_config(struct dsa_swit\n \t\tval = 0;\n \n \t\t/* SGMII Clock phase configuration */\n-\t\tif (priv->sgmii_rx_clk_falling_edge)\n+\t\tif (priv->ports_config.sgmii_rx_clk_falling_edge)\n \t\t\tval |= QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE;\n \n-\t\tif (priv->sgmii_tx_clk_falling_edge)\n+\t\tif (priv->ports_config.sgmii_tx_clk_falling_edge)\n \t\t\tval |= QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE;\n \n \t\tif (val)\n--- a/drivers/net/dsa/qca8k.h\n+++ b/drivers/net/dsa/qca8k.h\n@@ -270,15 +270,19 @@ enum {\n \tQCA8K_CPU_PORT6,\n };\n \n-struct qca8k_priv {\n-\tu8 switch_id;\n-\tu8 switch_revision;\n+struct qca8k_ports_config {\n \tbool sgmii_rx_clk_falling_edge;\n \tbool sgmii_tx_clk_falling_edge;\n \tbool sgmii_enable_pll;\n \tu8 rgmii_rx_delay[QCA8K_NUM_CPU_PORTS]; /* 0: CPU port0, 1: CPU port6 */\n \tu8 rgmii_tx_delay[QCA8K_NUM_CPU_PORTS]; /* 0: CPU port0, 1: CPU port6 */\n+};\n+\n+struct qca8k_priv {\n+\tu8 switch_id;\n+\tu8 switch_revision;\n \tbool legacy_phy_port_mapping;\n+\tstruct qca8k_ports_config ports_config;\n \tstruct regmap *regmap;\n \tstruct mii_bus *bus;\n \tstruct ar8xxx_port_status port_sts[QCA8K_NUM_PORTS];\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/747-v5.16-15-dt-bindings-net-ipq8064-mdio-fix-warning-with-new-qc.patch",
    "content": "From e52073a8e3086046a098b8a7cbeb282ff0cdb424 Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Thu, 14 Oct 2021 00:39:20 +0200\nSubject: dt-bindings: net: ipq8064-mdio: fix warning with new qca8k switch\n\nFix warning now that we have qca8k switch Documentation using yaml.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n Documentation/devicetree/bindings/net/qcom,ipq8064-mdio.yaml | 5 ++++-\n 1 file changed, 4 insertions(+), 1 deletion(-)\n\n--- a/Documentation/devicetree/bindings/net/qcom,ipq8064-mdio.yaml\n+++ b/Documentation/devicetree/bindings/net/qcom,ipq8064-mdio.yaml\n@@ -51,6 +51,9 @@ examples:\n         switch@10 {\n             compatible = \"qca,qca8337\";\n             reg = <0x10>;\n-            /* ... */\n+\n+            ports {\n+              /* ... */\n+            };\n         };\n     };\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/747-v5.16-16-dt-bindings-net-dsa-qca8k-convert-to-YAML-schema.patch",
    "content": "From d291fbb8245d5ba04979fed85575860a5cea7196 Mon Sep 17 00:00:00 2001\nFrom: Matthew Hagan <mnhagan88@gmail.com>\nDate: Thu, 14 Oct 2021 00:39:21 +0200\nSubject: dt-bindings: net: dsa: qca8k: convert to YAML schema\n\nConvert the qca8k bindings to YAML format.\n\nSigned-off-by: Matthew Hagan <mnhagan88@gmail.com>\nCo-developed-by: Ansuel Smith <ansuelsmth@gmail.com>\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n .../devicetree/bindings/net/dsa/qca8k.txt          | 245 --------------\n .../devicetree/bindings/net/dsa/qca8k.yaml         | 362 +++++++++++++++++++++\n 2 files changed, 362 insertions(+), 245 deletions(-)\n delete mode 100644 Documentation/devicetree/bindings/net/dsa/qca8k.txt\n create mode 100644 Documentation/devicetree/bindings/net/dsa/qca8k.yaml\n\n--- a/Documentation/devicetree/bindings/net/dsa/qca8k.txt\n+++ /dev/null\n@@ -1,245 +0,0 @@\n-* Qualcomm Atheros QCA8xxx switch family\n-\n-Required properties:\n-\n-- compatible: should be one of:\n-    \"qca,qca8328\": referenced as AR8328(N)-AK1(A/B) QFN 176 pin package\n-    \"qca,qca8327\": referenced as AR8327(N)-AL1A DR-QFN 148 pin package\n-    \"qca,qca8334\": referenced as QCA8334-AL3C QFN 88 pin package\n-    \"qca,qca8337\": referenced as QCA8337N-AL3(B/C) DR-QFN 148 pin package\n-\n-- #size-cells: must be 0\n-- #address-cells: must be 1\n-\n-Optional properties:\n-\n-- reset-gpios: GPIO to be used to reset the whole device\n-- qca,ignore-power-on-sel: Ignore power on pin strapping to configure led open\n-                           drain or eeprom presence. This is needed for broken\n-                           devices that have wrong configuration or when the oem\n-                           decided to not use pin strapping and fallback to sw\n-                           regs.\n-- qca,led-open-drain: Set leds to open-drain mode. This requires the\n-                      qca,ignore-power-on-sel to be set or the driver will fail\n-                      to probe. This is needed if the oem doesn't use pin\n-                      strapping to set this mode and prefers to set it using sw\n-                      regs. The pin strapping related to led open drain mode is\n-                      the pin B68 for QCA832x and B49 for QCA833x\n-\n-Subnodes:\n-\n-The integrated switch subnode should be specified according to the binding\n-described in dsa/dsa.txt. If the QCA8K switch is connect to a SoC's external\n-mdio-bus each subnode describing a port needs to have a valid phandle\n-referencing the internal PHY it is connected to. This is because there's no\n-N:N mapping of port and PHY id.\n-To declare the internal mdio-bus configuration, declare a mdio node in the\n-switch node and declare the phandle for the port referencing the internal\n-PHY is connected to. In this config a internal mdio-bus is registered and\n-the mdio MASTER is used as communication.\n-\n-Don't use mixed external and internal mdio-bus configurations, as this is\n-not supported by the hardware.\n-\n-This switch support 2 CPU port. Normally and advised configuration is with\n-CPU port set to port 0. It is also possible to set the CPU port to port 6\n-if the device requires it. The driver will configure the switch to the defined\n-port. With both CPU port declared the first CPU port is selected as primary\n-and the secondary CPU ignored.\n-\n-A CPU port node has the following optional node:\n-\n-- fixed-link            : Fixed-link subnode describing a link to a non-MDIO\n-                          managed entity. See\n-                          Documentation/devicetree/bindings/net/fixed-link.txt\n-                          for details.\n-- qca,sgmii-rxclk-falling-edge: Set the receive clock phase to falling edge.\n-                                Mostly used in qca8327 with CPU port 0 set to\n-                                sgmii.\n-- qca,sgmii-txclk-falling-edge: Set the transmit clock phase to falling edge.\n-- qca,sgmii-enable-pll  : For SGMII CPU port, explicitly enable PLL, TX and RX\n-                          chain along with Signal Detection.\n-                          This should NOT be enabled for qca8327. If enabled with\n-                          qca8327 the sgmii port won't correctly init and an err\n-                          is printed.\n-                          This can be required for qca8337 switch with revision 2.\n-                          A warning is displayed when used with revision greater\n-                          2.\n-                          With CPU port set to sgmii and qca8337 it is advised\n-                          to set this unless a communication problem is observed.\n-\n-For QCA8K the 'fixed-link' sub-node supports only the following properties:\n-\n-- 'speed' (integer, mandatory), to indicate the link speed. Accepted\n-  values are 10, 100 and 1000\n-- 'full-duplex' (boolean, optional), to indicate that full duplex is\n-  used. When absent, half duplex is assumed.\n-\n-Examples:\n-\n-for the external mdio-bus configuration:\n-\n-\t&mdio0 {\n-\t\tphy_port1: phy@0 {\n-\t\t\treg = <0>;\n-\t\t};\n-\n-\t\tphy_port2: phy@1 {\n-\t\t\treg = <1>;\n-\t\t};\n-\n-\t\tphy_port3: phy@2 {\n-\t\t\treg = <2>;\n-\t\t};\n-\n-\t\tphy_port4: phy@3 {\n-\t\t\treg = <3>;\n-\t\t};\n-\n-\t\tphy_port5: phy@4 {\n-\t\t\treg = <4>;\n-\t\t};\n-\n-\t\tswitch@10 {\n-\t\t\tcompatible = \"qca,qca8337\";\n-\t\t\t#address-cells = <1>;\n-\t\t\t#size-cells = <0>;\n-\n-\t\t\treset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>;\n-\t\t\treg = <0x10>;\n-\n-\t\t\tports {\n-\t\t\t\t#address-cells = <1>;\n-\t\t\t\t#size-cells = <0>;\n-\t\t\t\tport@0 {\n-\t\t\t\t\treg = <0>;\n-\t\t\t\t\tlabel = \"cpu\";\n-\t\t\t\t\tethernet = <&gmac1>;\n-\t\t\t\t\tphy-mode = \"rgmii\";\n-\t\t\t\t\tfixed-link {\n-\t\t\t\t\t\tspeed = 1000;\n-\t\t\t\t\t\tfull-duplex;\n-\t\t\t\t\t};\n-\t\t\t\t};\n-\n-\t\t\t\tport@1 {\n-\t\t\t\t\treg = <1>;\n-\t\t\t\t\tlabel = \"lan1\";\n-\t\t\t\t\tphy-handle = <&phy_port1>;\n-\t\t\t\t};\n-\n-\t\t\t\tport@2 {\n-\t\t\t\t\treg = <2>;\n-\t\t\t\t\tlabel = \"lan2\";\n-\t\t\t\t\tphy-handle = <&phy_port2>;\n-\t\t\t\t};\n-\n-\t\t\t\tport@3 {\n-\t\t\t\t\treg = <3>;\n-\t\t\t\t\tlabel = \"lan3\";\n-\t\t\t\t\tphy-handle = <&phy_port3>;\n-\t\t\t\t};\n-\n-\t\t\t\tport@4 {\n-\t\t\t\t\treg = <4>;\n-\t\t\t\t\tlabel = \"lan4\";\n-\t\t\t\t\tphy-handle = <&phy_port4>;\n-\t\t\t\t};\n-\n-\t\t\t\tport@5 {\n-\t\t\t\t\treg = <5>;\n-\t\t\t\t\tlabel = \"wan\";\n-\t\t\t\t\tphy-handle = <&phy_port5>;\n-\t\t\t\t};\n-\t\t\t};\n-\t\t};\n-\t};\n-\n-for the internal master mdio-bus configuration:\n-\n-\t&mdio0 {\n-\t\tswitch@10 {\n-\t\t\tcompatible = \"qca,qca8337\";\n-\t\t\t#address-cells = <1>;\n-\t\t\t#size-cells = <0>;\n-\n-\t\t\treset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>;\n-\t\t\treg = <0x10>;\n-\n-\t\t\tports {\n-\t\t\t\t#address-cells = <1>;\n-\t\t\t\t#size-cells = <0>;\n-\n-\t\t\t\tport@0 {\n-\t\t\t\t\treg = <0>;\n-\t\t\t\t\tlabel = \"cpu\";\n-\t\t\t\t\tethernet = <&gmac1>;\n-\t\t\t\t\tphy-mode = \"rgmii\";\n-\t\t\t\t\tfixed-link {\n-\t\t\t\t\t\tspeed = 1000;\n-\t\t\t\t\t\tfull-duplex;\n-\t\t\t\t\t};\n-\t\t\t\t};\n-\n-\t\t\t\tport@1 {\n-\t\t\t\t\treg = <1>;\n-\t\t\t\t\tlabel = \"lan1\";\n-\t\t\t\t\tphy-mode = \"internal\";\n-\t\t\t\t\tphy-handle = <&phy_port1>;\n-\t\t\t\t};\n-\n-\t\t\t\tport@2 {\n-\t\t\t\t\treg = <2>;\n-\t\t\t\t\tlabel = \"lan2\";\n-\t\t\t\t\tphy-mode = \"internal\";\n-\t\t\t\t\tphy-handle = <&phy_port2>;\n-\t\t\t\t};\n-\n-\t\t\t\tport@3 {\n-\t\t\t\t\treg = <3>;\n-\t\t\t\t\tlabel = \"lan3\";\n-\t\t\t\t\tphy-mode = \"internal\";\n-\t\t\t\t\tphy-handle = <&phy_port3>;\n-\t\t\t\t};\n-\n-\t\t\t\tport@4 {\n-\t\t\t\t\treg = <4>;\n-\t\t\t\t\tlabel = \"lan4\";\n-\t\t\t\t\tphy-mode = \"internal\";\n-\t\t\t\t\tphy-handle = <&phy_port4>;\n-\t\t\t\t};\n-\n-\t\t\t\tport@5 {\n-\t\t\t\t\treg = <5>;\n-\t\t\t\t\tlabel = \"wan\";\n-\t\t\t\t\tphy-mode = \"internal\";\n-\t\t\t\t\tphy-handle = <&phy_port5>;\n-\t\t\t\t};\n-\t\t\t};\n-\n-\t\t\tmdio {\n-\t\t\t\t#address-cells = <1>;\n-\t\t\t\t#size-cells = <0>;\n-\n-\t\t\t\tphy_port1: phy@0 {\n-\t\t\t\t\treg = <0>;\n-\t\t\t\t};\n-\n-\t\t\t\tphy_port2: phy@1 {\n-\t\t\t\t\treg = <1>;\n-\t\t\t\t};\n-\n-\t\t\t\tphy_port3: phy@2 {\n-\t\t\t\t\treg = <2>;\n-\t\t\t\t};\n-\n-\t\t\t\tphy_port4: phy@3 {\n-\t\t\t\t\treg = <3>;\n-\t\t\t\t};\n-\n-\t\t\t\tphy_port5: phy@4 {\n-\t\t\t\t\treg = <4>;\n-\t\t\t\t};\n-\t\t\t};\n-\t\t};\n-\t};\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/net/dsa/qca8k.yaml\n@@ -0,0 +1,362 @@\n+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)\n+%YAML 1.2\n+---\n+$id: http://devicetree.org/schemas/net/dsa/qca8k.yaml#\n+$schema: http://devicetree.org/meta-schemas/core.yaml#\n+\n+title: Qualcomm Atheros QCA83xx switch family\n+\n+maintainers:\n+  - John Crispin <john@phrozen.org>\n+\n+description:\n+  If the QCA8K switch is connect to an SoC's external mdio-bus, each subnode\n+  describing a port needs to have a valid phandle referencing the internal PHY\n+  it is connected to. This is because there is no N:N mapping of port and PHY\n+  ID. To declare the internal mdio-bus configuration, declare an MDIO node in\n+  the switch node and declare the phandle for the port, referencing the internal\n+  PHY it is connected to. In this config, an internal mdio-bus is registered and\n+  the MDIO master is used for communication. Mixed external and internal\n+  mdio-bus configurations are not supported by the hardware.\n+\n+properties:\n+  compatible:\n+    oneOf:\n+      - enum:\n+          - qca,qca8327\n+          - qca,qca8328\n+          - qca,qca8334\n+          - qca,qca8337\n+    description: |\n+      qca,qca8328: referenced as AR8328(N)-AK1(A/B) QFN 176 pin package\n+      qca,qca8327: referenced as AR8327(N)-AL1A DR-QFN 148 pin package\n+      qca,qca8334: referenced as QCA8334-AL3C QFN 88 pin package\n+      qca,qca8337: referenced as QCA8337N-AL3(B/C) DR-QFN 148 pin package\n+\n+  reg:\n+    maxItems: 1\n+\n+  reset-gpios:\n+    description:\n+      GPIO to be used to reset the whole device\n+    maxItems: 1\n+\n+  qca,ignore-power-on-sel:\n+    $ref: /schemas/types.yaml#/definitions/flag\n+    description:\n+      Ignore power-on pin strapping to configure LED open-drain or EEPROM\n+      presence. This is needed for devices with incorrect configuration or when\n+      the OEM has decided not to use pin strapping and falls back to SW regs.\n+\n+  qca,led-open-drain:\n+    $ref: /schemas/types.yaml#/definitions/flag\n+    description:\n+      Set LEDs to open-drain mode. This requires the qca,ignore-power-on-sel to\n+      be set, otherwise the driver will fail at probe. This is required if the\n+      OEM does not use pin strapping to set this mode and prefers to set it\n+      using SW regs. The pin strappings related to LED open-drain mode are\n+      B68 on the QCA832x and B49 on the QCA833x.\n+\n+  mdio:\n+    type: object\n+    description: Qca8k switch have an internal mdio to access switch port.\n+                 If this is not present, the legacy mapping is used and the\n+                 internal mdio access is used.\n+                 With the legacy mapping the reg corresponding to the internal\n+                 mdio is the switch reg with an offset of -1.\n+\n+    properties:\n+      '#address-cells':\n+        const: 1\n+      '#size-cells':\n+        const: 0\n+\n+    patternProperties:\n+      \"^(ethernet-)?phy@[0-4]$\":\n+        type: object\n+\n+        allOf:\n+          - $ref: \"http://devicetree.org/schemas/net/mdio.yaml#\"\n+\n+        properties:\n+          reg:\n+            maxItems: 1\n+\n+        required:\n+          - reg\n+\n+patternProperties:\n+  \"^(ethernet-)?ports$\":\n+    type: object\n+    properties:\n+      '#address-cells':\n+        const: 1\n+      '#size-cells':\n+        const: 0\n+\n+    patternProperties:\n+      \"^(ethernet-)?port@[0-6]$\":\n+        type: object\n+        description: Ethernet switch ports\n+\n+        properties:\n+          reg:\n+            description: Port number\n+\n+          label:\n+            description:\n+              Describes the label associated with this port, which will become\n+              the netdev name\n+            $ref: /schemas/types.yaml#/definitions/string\n+\n+          link:\n+            description:\n+              Should be a list of phandles to other switch's DSA port. This\n+              port is used as the outgoing port towards the phandle ports. The\n+              full routing information must be given, not just the one hop\n+              routes to neighbouring switches\n+            $ref: /schemas/types.yaml#/definitions/phandle-array\n+\n+          ethernet:\n+            description:\n+              Should be a phandle to a valid Ethernet device node.  This host\n+              device is what the switch port is connected to\n+            $ref: /schemas/types.yaml#/definitions/phandle\n+\n+          phy-handle: true\n+\n+          phy-mode: true\n+\n+          fixed-link: true\n+\n+          mac-address: true\n+\n+          sfp: true\n+\n+          qca,sgmii-rxclk-falling-edge:\n+            $ref: /schemas/types.yaml#/definitions/flag\n+            description:\n+              Set the receive clock phase to falling edge. Mostly commonly used on\n+              the QCA8327 with CPU port 0 set to SGMII.\n+\n+          qca,sgmii-txclk-falling-edge:\n+            $ref: /schemas/types.yaml#/definitions/flag\n+            description:\n+              Set the transmit clock phase to falling edge.\n+\n+          qca,sgmii-enable-pll:\n+            $ref: /schemas/types.yaml#/definitions/flag\n+            description:\n+              For SGMII CPU port, explicitly enable PLL, TX and RX chain along with\n+              Signal Detection. On the QCA8327 this should not be enabled, otherwise\n+              the SGMII port will not initialize. When used on the QCA8337, revision 3\n+              or greater, a warning will be displayed. When the CPU port is set to\n+              SGMII on the QCA8337, it is advised to set this unless a communication\n+              issue is observed.\n+\n+        required:\n+          - reg\n+\n+        additionalProperties: false\n+\n+oneOf:\n+  - required:\n+      - ports\n+  - required:\n+      - ethernet-ports\n+\n+required:\n+  - compatible\n+  - reg\n+\n+additionalProperties: true\n+\n+examples:\n+  - |\n+    #include <dt-bindings/gpio/gpio.h>\n+\n+    mdio {\n+        #address-cells = <1>;\n+        #size-cells = <0>;\n+\n+        external_phy_port1: ethernet-phy@0 {\n+            reg = <0>;\n+        };\n+\n+        external_phy_port2: ethernet-phy@1 {\n+            reg = <1>;\n+        };\n+\n+        external_phy_port3: ethernet-phy@2 {\n+            reg = <2>;\n+        };\n+\n+        external_phy_port4: ethernet-phy@3 {\n+            reg = <3>;\n+        };\n+\n+        external_phy_port5: ethernet-phy@4 {\n+            reg = <4>;\n+        };\n+\n+        switch@10 {\n+            compatible = \"qca,qca8337\";\n+            #address-cells = <1>;\n+            #size-cells = <0>;\n+            reset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>;\n+            reg = <0x10>;\n+\n+            ports {\n+                #address-cells = <1>;\n+                #size-cells = <0>;\n+\n+                port@0 {\n+                    reg = <0>;\n+                    label = \"cpu\";\n+                    ethernet = <&gmac1>;\n+                    phy-mode = \"rgmii\";\n+\n+                    fixed-link {\n+                        speed = <1000>;\n+                        full-duplex;\n+                    };\n+                };\n+\n+                port@1 {\n+                    reg = <1>;\n+                    label = \"lan1\";\n+                    phy-handle = <&external_phy_port1>;\n+                };\n+\n+                port@2 {\n+                    reg = <2>;\n+                    label = \"lan2\";\n+                    phy-handle = <&external_phy_port2>;\n+                };\n+\n+                port@3 {\n+                    reg = <3>;\n+                    label = \"lan3\";\n+                    phy-handle = <&external_phy_port3>;\n+                };\n+\n+                port@4 {\n+                    reg = <4>;\n+                    label = \"lan4\";\n+                    phy-handle = <&external_phy_port4>;\n+                };\n+\n+                port@5 {\n+                    reg = <5>;\n+                    label = \"wan\";\n+                    phy-handle = <&external_phy_port5>;\n+                };\n+            };\n+        };\n+    };\n+  - |\n+    #include <dt-bindings/gpio/gpio.h>\n+\n+    mdio {\n+        #address-cells = <1>;\n+        #size-cells = <0>;\n+\n+        switch@10 {\n+            compatible = \"qca,qca8337\";\n+            #address-cells = <1>;\n+            #size-cells = <0>;\n+            reset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>;\n+            reg = <0x10>;\n+\n+            ports {\n+                #address-cells = <1>;\n+                #size-cells = <0>;\n+\n+                port@0 {\n+                    reg = <0>;\n+                    label = \"cpu\";\n+                    ethernet = <&gmac1>;\n+                    phy-mode = \"rgmii\";\n+\n+                    fixed-link {\n+                        speed = <1000>;\n+                        full-duplex;\n+                    };\n+                };\n+\n+                port@1 {\n+                    reg = <1>;\n+                    label = \"lan1\";\n+                    phy-mode = \"internal\";\n+                    phy-handle = <&internal_phy_port1>;\n+                };\n+\n+                port@2 {\n+                    reg = <2>;\n+                    label = \"lan2\";\n+                    phy-mode = \"internal\";\n+                    phy-handle = <&internal_phy_port2>;\n+                };\n+\n+                port@3 {\n+                    reg = <3>;\n+                    label = \"lan3\";\n+                    phy-mode = \"internal\";\n+                    phy-handle = <&internal_phy_port3>;\n+                };\n+\n+                port@4 {\n+                    reg = <4>;\n+                    label = \"lan4\";\n+                    phy-mode = \"internal\";\n+                    phy-handle = <&internal_phy_port4>;\n+                };\n+\n+                port@5 {\n+                    reg = <5>;\n+                    label = \"wan\";\n+                    phy-mode = \"internal\";\n+                    phy-handle = <&internal_phy_port5>;\n+                };\n+\n+                port@6 {\n+                    reg = <0>;\n+                    label = \"cpu\";\n+                    ethernet = <&gmac1>;\n+                    phy-mode = \"sgmii\";\n+\n+                    qca,sgmii-rxclk-falling-edge;\n+\n+                    fixed-link {\n+                        speed = <1000>;\n+                        full-duplex;\n+                    };\n+                };\n+            };\n+\n+            mdio {\n+                #address-cells = <1>;\n+                #size-cells = <0>;\n+\n+                internal_phy_port1: ethernet-phy@0 {\n+                    reg = <0>;\n+                };\n+\n+                internal_phy_port2: ethernet-phy@1 {\n+                    reg = <1>;\n+                };\n+\n+                internal_phy_port3: ethernet-phy@2 {\n+                    reg = <2>;\n+                };\n+\n+                internal_phy_port4: ethernet-phy@3 {\n+                    reg = <3>;\n+                };\n+\n+                internal_phy_port5: ethernet-phy@4 {\n+                    reg = <4>;\n+                };\n+            };\n+        };\n+    };\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/748-v5.16-net-dsa-qca8k-fix-delay-applied-to-wrong-cpu-in-parse-p.patch",
    "content": "From 06dd34a628ae5b6a839b757e746de165d6789ca8 Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Sun, 17 Oct 2021 16:56:46 +0200\nSubject: net: dsa: qca8k: fix delay applied to wrong cpu in parse_port_config\n\nFix delay settings applied to wrong cpu in parse_port_config. The delay\nvalues is set to the wrong index as the cpu_port_index is incremented\ntoo early. Start the cpu_port_index to -1 so the correct value is\napplied to address also the case with invalid phy mode and not available\nport.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/dsa/qca8k.c | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/drivers/net/dsa/qca8k.c\n+++ b/drivers/net/dsa/qca8k.c\n@@ -976,7 +976,7 @@ qca8k_setup_of_pws_reg(struct qca8k_priv\n static int\n qca8k_parse_port_config(struct qca8k_priv *priv)\n {\n-\tint port, cpu_port_index = 0, ret;\n+\tint port, cpu_port_index = -1, ret;\n \tstruct device_node *port_dn;\n \tphy_interface_t mode;\n \tstruct dsa_port *dp;\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/749-v5.16-net-dsa-qca8k-tidy-for-loop-in-setup-and-add-cpu-port-c.patch",
    "content": "From 040e926f5813a5f4cc18dbff7c942d1e52f368f2 Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Tue, 19 Oct 2021 02:08:50 +0200\nSubject: net: dsa: qca8k: tidy for loop in setup and add cpu port check\n\nTidy and organize qca8k setup function from multiple for loop.\nChange for loop in bridge leave/join to scan all port and skip cpu port.\nNo functional change intended.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/dsa/qca8k.c | 74 +++++++++++++++++++++++++++++--------------------\n 1 file changed, 44 insertions(+), 30 deletions(-)\n\n--- a/drivers/net/dsa/qca8k.c\n+++ b/drivers/net/dsa/qca8k.c\n@@ -1122,28 +1122,34 @@ qca8k_setup(struct dsa_switch *ds)\n \tif (ret)\n \t\tdev_warn(priv->dev, \"mib init failed\");\n \n-\t/* Enable QCA header mode on the cpu port */\n-\tret = qca8k_write(priv, QCA8K_REG_PORT_HDR_CTRL(cpu_port),\n-\t\t\t  QCA8K_PORT_HDR_CTRL_ALL << QCA8K_PORT_HDR_CTRL_TX_S |\n-\t\t\t  QCA8K_PORT_HDR_CTRL_ALL << QCA8K_PORT_HDR_CTRL_RX_S);\n-\tif (ret) {\n-\t\tdev_err(priv->dev, \"failed enabling QCA header mode\");\n-\t\treturn ret;\n-\t}\n-\n-\t/* Disable forwarding by default on all ports */\n+\t/* Initial setup of all ports */\n \tfor (i = 0; i < QCA8K_NUM_PORTS; i++) {\n+\t\t/* Disable forwarding by default on all ports */\n \t\tret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i),\n \t\t\t\tQCA8K_PORT_LOOKUP_MEMBER, 0);\n \t\tif (ret)\n \t\t\treturn ret;\n-\t}\n \n-\t/* Disable MAC by default on all ports */\n-\tfor (i = 1; i < QCA8K_NUM_PORTS; i++)\n-\t\tqca8k_port_set_status(priv, i, 0);\n+\t\t/* Enable QCA header mode on all cpu ports */\n+\t\tif (dsa_is_cpu_port(ds, i)) {\n+\t\t\tret = qca8k_write(priv, QCA8K_REG_PORT_HDR_CTRL(i),\n+\t\t\t\t\t  QCA8K_PORT_HDR_CTRL_ALL << QCA8K_PORT_HDR_CTRL_TX_S |\n+\t\t\t\t\t  QCA8K_PORT_HDR_CTRL_ALL << QCA8K_PORT_HDR_CTRL_RX_S);\n+\t\t\tif (ret) {\n+\t\t\t\tdev_err(priv->dev, \"failed enabling QCA header mode\");\n+\t\t\t\treturn ret;\n+\t\t\t}\n+\t\t}\n+\n+\t\t/* Disable MAC by default on all user ports */\n+\t\tif (dsa_is_user_port(ds, i))\n+\t\t\tqca8k_port_set_status(priv, i, 0);\n+\t}\n \n-\t/* Forward all unknown frames to CPU port for Linux processing */\n+\t/* Forward all unknown frames to CPU port for Linux processing\n+\t * Notice that in multi-cpu config only one port should be set\n+\t * for igmp, unknown, multicast and broadcast packet\n+\t */\n \tret = qca8k_write(priv, QCA8K_REG_GLOBAL_FW_CTRL1,\n \t\t\t  BIT(cpu_port) << QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_S |\n \t\t\t  BIT(cpu_port) << QCA8K_GLOBAL_FW_CTRL1_BC_DP_S |\n@@ -1152,11 +1158,13 @@ qca8k_setup(struct dsa_switch *ds)\n \tif (ret)\n \t\treturn ret;\n \n-\t/* Setup connection between CPU port & user ports */\n+\t/* Setup connection between CPU port & user ports\n+\t * Configure specific switch configuration for ports\n+\t */\n \tfor (i = 0; i < QCA8K_NUM_PORTS; i++) {\n \t\t/* CPU port gets connected to all user ports of the switch */\n \t\tif (dsa_is_cpu_port(ds, i)) {\n-\t\t\tret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(cpu_port),\n+\t\t\tret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i),\n \t\t\t\t\tQCA8K_PORT_LOOKUP_MEMBER, dsa_user_ports(ds));\n \t\t\tif (ret)\n \t\t\t\treturn ret;\n@@ -1193,16 +1201,14 @@ qca8k_setup(struct dsa_switch *ds)\n \t\t\tif (ret)\n \t\t\t\treturn ret;\n \t\t}\n-\t}\n \n-\t/* The port 5 of the qca8337 have some problem in flood condition. The\n-\t * original legacy driver had some specific buffer and priority settings\n-\t * for the different port suggested by the QCA switch team. Add this\n-\t * missing settings to improve switch stability under load condition.\n-\t * This problem is limited to qca8337 and other qca8k switch are not affected.\n-\t */\n-\tif (priv->switch_id == QCA8K_ID_QCA8337) {\n-\t\tfor (i = 0; i < QCA8K_NUM_PORTS; i++) {\n+\t\t/* The port 5 of the qca8337 have some problem in flood condition. The\n+\t\t * original legacy driver had some specific buffer and priority settings\n+\t\t * for the different port suggested by the QCA switch team. Add this\n+\t\t * missing settings to improve switch stability under load condition.\n+\t\t * This problem is limited to qca8337 and other qca8k switch are not affected.\n+\t\t */\n+\t\tif (priv->switch_id == QCA8K_ID_QCA8337) {\n \t\t\tswitch (i) {\n \t\t\t/* The 2 CPU port and port 5 requires some different\n \t\t\t * priority than any other ports.\n@@ -1238,6 +1244,12 @@ qca8k_setup(struct dsa_switch *ds)\n \t\t\t\t  QCA8K_PORT_HOL_CTRL1_WRED_EN,\n \t\t\t\t  mask);\n \t\t}\n+\n+\t\t/* Set initial MTU for every port.\n+\t\t * We have only have a general MTU setting. So track\n+\t\t * every port and set the max across all port.\n+\t\t */\n+\t\tpriv->port_mtu[i] = ETH_FRAME_LEN + ETH_FCS_LEN;\n \t}\n \n \t/* Special GLOBAL_FC_THRESH value are needed for ar8327 switch */\n@@ -1251,8 +1263,6 @@ qca8k_setup(struct dsa_switch *ds)\n \t}\n \n \t/* Setup our port MTUs to match power on defaults */\n-\tfor (i = 0; i < QCA8K_NUM_PORTS; i++)\n-\t\tpriv->port_mtu[i] = ETH_FRAME_LEN + ETH_FCS_LEN;\n \tret = qca8k_write(priv, QCA8K_MAX_FRAME_SIZE, ETH_FRAME_LEN + ETH_FCS_LEN);\n \tif (ret)\n \t\tdev_warn(priv->dev, \"failed setting MTU settings\");\n@@ -1728,7 +1738,9 @@ qca8k_port_bridge_join(struct dsa_switch\n \tcpu_port = dsa_to_port(ds, port)->cpu_dp->index;\n \tport_mask = BIT(cpu_port);\n \n-\tfor (i = 1; i < QCA8K_NUM_PORTS; i++) {\n+\tfor (i = 0; i < QCA8K_NUM_PORTS; i++) {\n+\t\tif (dsa_is_cpu_port(ds, i))\n+\t\t\tcontinue;\n \t\tif (dsa_to_port(ds, i)->bridge_dev != br)\n \t\t\tcontinue;\n \t\t/* Add this port to the portvlan mask of the other ports\n@@ -1758,7 +1770,9 @@ qca8k_port_bridge_leave(struct dsa_switc\n \n \tcpu_port = dsa_to_port(ds, port)->cpu_dp->index;\n \n-\tfor (i = 1; i < QCA8K_NUM_PORTS; i++) {\n+\tfor (i = 0; i < QCA8K_NUM_PORTS; i++) {\n+\t\tif (dsa_is_cpu_port(ds, i))\n+\t\t\tcontinue;\n \t\tif (dsa_to_port(ds, i)->bridge_dev != br)\n \t\t\tcontinue;\n \t\t/* Remove this port to the portvlan mask of the other ports\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/750-v5.16-net-dsa-qca8k-make-sure-pad0-mac06-exchange-is-disabled.patch",
    "content": "From 5f15d392dcb4aa250a63d6f2c5adfc26c0aedc78 Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Tue, 2 Nov 2021 19:30:41 +0100\nSubject: net: dsa: qca8k: make sure PAD0 MAC06 exchange is disabled\n\nSome device set MAC06 exchange in the bootloader. This cause some\nproblem as we don't support this strange mode and we just set the port6\nas the primary CPU port. With MAC06 exchange, PAD0 reg configure port6\ninstead of port0. Add an extra check and explicitly disable MAC06 exchange\nto correctly configure the port PAD config.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nFixes: 3fcf734aa482 (\"net: dsa: qca8k: add support for cpu port 6\")\nReviewed-by: Vladimir Oltean <olteanv@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/dsa/qca8k.c | 8 ++++++++\n drivers/net/dsa/qca8k.h | 1 +\n 2 files changed, 9 insertions(+)\n\n--- a/drivers/net/dsa/qca8k.c\n+++ b/drivers/net/dsa/qca8k.c\n@@ -1109,6 +1109,14 @@ qca8k_setup(struct dsa_switch *ds)\n \tif (ret)\n \t\treturn ret;\n \n+\t/* Make sure MAC06 is disabled */\n+\tret = qca8k_reg_clear(priv, QCA8K_REG_PORT0_PAD_CTRL,\n+\t\t\t      QCA8K_PORT0_PAD_MAC06_EXCHANGE_EN);\n+\tif (ret) {\n+\t\tdev_err(priv->dev, \"failed disabling MAC06 exchange\");\n+\t\treturn ret;\n+\t}\n+\n \t/* Enable CPU Port */\n \tret = qca8k_reg_set(priv, QCA8K_REG_GLOBAL_FW_CTRL0,\n \t\t\t    QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN);\n--- a/drivers/net/dsa/qca8k.h\n+++ b/drivers/net/dsa/qca8k.h\n@@ -34,6 +34,7 @@\n #define   QCA8K_MASK_CTRL_DEVICE_ID_MASK\t\tGENMASK(15, 8)\n #define   QCA8K_MASK_CTRL_DEVICE_ID(x)\t\t\t((x) >> 8)\n #define QCA8K_REG_PORT0_PAD_CTRL\t\t\t0x004\n+#define   QCA8K_PORT0_PAD_MAC06_EXCHANGE_EN\t\tBIT(31)\n #define   QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE\tBIT(19)\n #define   QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE\tBIT(18)\n #define QCA8K_REG_PORT5_PAD_CTRL\t\t\t0x008\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/751-v5.16-net-dsa-qca8k-fix-internal-delay-applied-to-the-wrong-PAD.patch",
    "content": "From 3b00a07c2443745d62babfe08dbb2ad8e649526e Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Fri, 19 Nov 2021 03:03:49 +0100\nSubject: [PATCH] net: dsa: qca8k: fix internal delay applied to the wrong PAD\n config\n\nWith SGMII phy the internal delay is always applied to the PAD0 config.\nThis is caused by the falling edge configuration that hardcode the reg\nto PAD0 (as the falling edge bits are present only in PAD0 reg)\nMove the delay configuration before the reg overwrite to correctly apply\nthe delay.\n\nFixes: cef08115846e (\"net: dsa: qca8k: set internal delay also for sgmii\")\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nReviewed-by: Vladimir Oltean <olteanv@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/dsa/qca8k.c | 12 ++++++------\n 1 file changed, 6 insertions(+), 6 deletions(-)\n\n--- a/drivers/net/dsa/qca8k.c\n+++ b/drivers/net/dsa/qca8k.c\n@@ -1433,6 +1433,12 @@ qca8k_phylink_mac_config(struct dsa_swit\n \n \t\tqca8k_write(priv, QCA8K_REG_SGMII_CTRL, val);\n \n+\t\t/* From original code is reported port instability as SGMII also\n+\t\t * require delay set. Apply advised values here or take them from DT.\n+\t\t */\n+\t\tif (state->interface == PHY_INTERFACE_MODE_SGMII)\n+\t\t\tqca8k_mac_config_setup_internal_delay(priv, cpu_port_index, reg);\n+\n \t\t/* For qca8327/qca8328/qca8334/qca8338 sgmii is unique and\n \t\t * falling edge is set writing in the PORT0 PAD reg\n \t\t */\n@@ -1455,12 +1461,6 @@ qca8k_phylink_mac_config(struct dsa_swit\n \t\t\t\t\tQCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE,\n \t\t\t\t\tval);\n \n-\t\t/* From original code is reported port instability as SGMII also\n-\t\t * require delay set. Apply advised values here or take them from DT.\n-\t\t */\n-\t\tif (state->interface == PHY_INTERFACE_MODE_SGMII)\n-\t\t\tqca8k_mac_config_setup_internal_delay(priv, cpu_port_index, reg);\n-\n \t\tbreak;\n \tdefault:\n \t\tdev_err(ds->dev, \"xMII mode %s not supported for port %d\\n\",\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/752-v5.16-net-dsa-qca8k-fix-MTU-calculation.patch",
    "content": "From 65258b9d8cde45689bdc86ca39b50f01f983733b Mon Sep 17 00:00:00 2001\nFrom: Robert Marko <robert.marko@sartura.hr>\nDate: Fri, 19 Nov 2021 03:03:50 +0100\nSubject: [PATCH] net: dsa: qca8k: fix MTU calculation\n\nqca8k has a global MTU, so its tracking the MTU per port to make sure\nthat the largest MTU gets applied.\nSince it uses the frame size instead of MTU the driver MTU change function\nwill then add the size of Ethernet header and checksum on top of MTU.\n\nThe driver currently populates the per port MTU size as Ethernet frame\nlength + checksum which equals 1518.\n\nThe issue is that then MTU change function will go through all of the\nports, find the largest MTU and apply the Ethernet header + checksum on\ntop of it again, so for a desired MTU of 1500 you will end up with 1536.\n\nThis is obviously incorrect, so to correct it populate the per port struct\nMTU with just the MTU and not include the Ethernet header + checksum size\nas those will be added by the MTU change function.\n\nFixes: f58d2598cf70 (\"net: dsa: qca8k: implement the port MTU callbacks\")\nSigned-off-by: Robert Marko <robert.marko@sartura.hr>\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nReviewed-by: Vladimir Oltean <olteanv@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/dsa/qca8k.c | 6 +++++-\n 1 file changed, 5 insertions(+), 1 deletion(-)\n\n--- a/drivers/net/dsa/qca8k.c\n+++ b/drivers/net/dsa/qca8k.c\n@@ -1256,8 +1256,12 @@ qca8k_setup(struct dsa_switch *ds)\n \t\t/* Set initial MTU for every port.\n \t\t * We have only have a general MTU setting. So track\n \t\t * every port and set the max across all port.\n+\t\t * Set per port MTU to 1500 as the MTU change function\n+\t\t * will add the overhead and if its set to 1518 then it\n+\t\t * will apply the overhead again and we will end up with\n+\t\t * MTU of 1536 instead of 1518\n \t\t */\n-\t\tpriv->port_mtu[i] = ETH_FRAME_LEN + ETH_FCS_LEN;\n+\t\tpriv->port_mtu[i] = ETH_DATA_LEN;\n \t}\n \n \t/* Special GLOBAL_FC_THRESH value are needed for ar8327 switch */\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/753-net-next-net-dsa-qca8k-remove-redundant-check-in-parse_port_config.patch",
    "content": "From b9133f3ef5a2659730cf47a74bd0a9259f1cf8ff Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Mon, 22 Nov 2021 16:23:40 +0100\nSubject: net: dsa: qca8k: remove redundant check in parse_port_config\n\nThe very next check for port 0 and 6 already makes sure we don't go out\nof bounds with the ports_config delay table.\nRemove the redundant check.\n\nReported-by: kernel test robot <lkp@intel.com>\nReported-by: Dan Carpenter <dan.carpenter@oracle.com>\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nReviewed-by: Vladimir Oltean <olteanv@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/dsa/qca8k.c | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/drivers/net/dsa/qca8k.c\n+++ b/drivers/net/dsa/qca8k.c\n@@ -983,7 +983,7 @@ qca8k_parse_port_config(struct qca8k_pri\n \tu32 delay;\n \n \t/* We have 2 CPU port. Check them */\n-\tfor (port = 0; port < QCA8K_NUM_PORTS && cpu_port_index < QCA8K_NUM_CPU_PORTS; port++) {\n+\tfor (port = 0; port < QCA8K_NUM_PORTS; port++) {\n \t\t/* Skip every other port */\n \t\tif (port != 0 && port != 6)\n \t\t\tcontinue;\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/754-net-next-net-dsa-qca8k-convert-to-GENMASK_FIELD_PREP_FIELD_GET.patch",
    "content": "From 90ae68bfc2ffcb54a4ba4f64edbeb84a80cbb57c Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Mon, 22 Nov 2021 16:23:41 +0100\nSubject: net: dsa: qca8k: convert to GENMASK/FIELD_PREP/FIELD_GET\n\nConvert and try to standardize bit fields using\nGENMASK/FIELD_PREP/FIELD_GET macros. Rework some logic to support the\nstandard macro and tidy things up. No functional change intended.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/dsa/qca8k.c |  98 +++++++++++++++----------------\n drivers/net/dsa/qca8k.h | 153 ++++++++++++++++++++++++++----------------------\n 2 files changed, 130 insertions(+), 121 deletions(-)\n\n--- a/drivers/net/dsa/qca8k.c\n+++ b/drivers/net/dsa/qca8k.c\n@@ -9,6 +9,7 @@\n #include <linux/module.h>\n #include <linux/phy.h>\n #include <linux/netdevice.h>\n+#include <linux/bitfield.h>\n #include <net/dsa.h>\n #include <linux/of_net.h>\n #include <linux/of_mdio.h>\n@@ -319,18 +320,18 @@ qca8k_fdb_read(struct qca8k_priv *priv,\n \t}\n \n \t/* vid - 83:72 */\n-\tfdb->vid = (reg[2] >> QCA8K_ATU_VID_S) & QCA8K_ATU_VID_M;\n+\tfdb->vid = FIELD_GET(QCA8K_ATU_VID_MASK, reg[2]);\n \t/* aging - 67:64 */\n-\tfdb->aging = reg[2] & QCA8K_ATU_STATUS_M;\n+\tfdb->aging = FIELD_GET(QCA8K_ATU_STATUS_MASK, reg[2]);\n \t/* portmask - 54:48 */\n-\tfdb->port_mask = (reg[1] >> QCA8K_ATU_PORT_S) & QCA8K_ATU_PORT_M;\n+\tfdb->port_mask = FIELD_GET(QCA8K_ATU_PORT_MASK, reg[1]);\n \t/* mac - 47:0 */\n-\tfdb->mac[0] = (reg[1] >> QCA8K_ATU_ADDR0_S) & 0xff;\n-\tfdb->mac[1] = reg[1] & 0xff;\n-\tfdb->mac[2] = (reg[0] >> QCA8K_ATU_ADDR2_S) & 0xff;\n-\tfdb->mac[3] = (reg[0] >> QCA8K_ATU_ADDR3_S) & 0xff;\n-\tfdb->mac[4] = (reg[0] >> QCA8K_ATU_ADDR4_S) & 0xff;\n-\tfdb->mac[5] = reg[0] & 0xff;\n+\tfdb->mac[0] = FIELD_GET(QCA8K_ATU_ADDR0_MASK, reg[1]);\n+\tfdb->mac[1] = FIELD_GET(QCA8K_ATU_ADDR1_MASK, reg[1]);\n+\tfdb->mac[2] = FIELD_GET(QCA8K_ATU_ADDR2_MASK, reg[0]);\n+\tfdb->mac[3] = FIELD_GET(QCA8K_ATU_ADDR3_MASK, reg[0]);\n+\tfdb->mac[4] = FIELD_GET(QCA8K_ATU_ADDR4_MASK, reg[0]);\n+\tfdb->mac[5] = FIELD_GET(QCA8K_ATU_ADDR5_MASK, reg[0]);\n \n \treturn 0;\n }\n@@ -343,18 +344,18 @@ qca8k_fdb_write(struct qca8k_priv *priv,\n \tint i;\n \n \t/* vid - 83:72 */\n-\treg[2] = (vid & QCA8K_ATU_VID_M) << QCA8K_ATU_VID_S;\n+\treg[2] = FIELD_PREP(QCA8K_ATU_VID_MASK, vid);\n \t/* aging - 67:64 */\n-\treg[2] |= aging & QCA8K_ATU_STATUS_M;\n+\treg[2] |= FIELD_PREP(QCA8K_ATU_STATUS_MASK, aging);\n \t/* portmask - 54:48 */\n-\treg[1] = (port_mask & QCA8K_ATU_PORT_M) << QCA8K_ATU_PORT_S;\n+\treg[1] = FIELD_PREP(QCA8K_ATU_PORT_MASK, port_mask);\n \t/* mac - 47:0 */\n-\treg[1] |= mac[0] << QCA8K_ATU_ADDR0_S;\n-\treg[1] |= mac[1];\n-\treg[0] |= mac[2] << QCA8K_ATU_ADDR2_S;\n-\treg[0] |= mac[3] << QCA8K_ATU_ADDR3_S;\n-\treg[0] |= mac[4] << QCA8K_ATU_ADDR4_S;\n-\treg[0] |= mac[5];\n+\treg[1] |= FIELD_PREP(QCA8K_ATU_ADDR0_MASK, mac[0]);\n+\treg[1] |= FIELD_PREP(QCA8K_ATU_ADDR1_MASK, mac[1]);\n+\treg[0] |= FIELD_PREP(QCA8K_ATU_ADDR2_MASK, mac[2]);\n+\treg[0] |= FIELD_PREP(QCA8K_ATU_ADDR3_MASK, mac[3]);\n+\treg[0] |= FIELD_PREP(QCA8K_ATU_ADDR4_MASK, mac[4]);\n+\treg[0] |= FIELD_PREP(QCA8K_ATU_ADDR5_MASK, mac[5]);\n \n \t/* load the array into the ARL table */\n \tfor (i = 0; i < 3; i++)\n@@ -372,7 +373,7 @@ qca8k_fdb_access(struct qca8k_priv *priv\n \treg |= cmd;\n \tif (port >= 0) {\n \t\treg |= QCA8K_ATU_FUNC_PORT_EN;\n-\t\treg |= (port & QCA8K_ATU_FUNC_PORT_M) << QCA8K_ATU_FUNC_PORT_S;\n+\t\treg |= FIELD_PREP(QCA8K_ATU_FUNC_PORT_MASK, port);\n \t}\n \n \t/* Write the function register triggering the table access */\n@@ -454,7 +455,7 @@ qca8k_vlan_access(struct qca8k_priv *pri\n \t/* Set the command and VLAN index */\n \treg = QCA8K_VTU_FUNC1_BUSY;\n \treg |= cmd;\n-\treg |= vid << QCA8K_VTU_FUNC1_VID_S;\n+\treg |= FIELD_PREP(QCA8K_VTU_FUNC1_VID_MASK, vid);\n \n \t/* Write the function register triggering the table access */\n \tret = qca8k_write(priv, QCA8K_REG_VTU_FUNC1, reg);\n@@ -500,13 +501,11 @@ qca8k_vlan_add(struct qca8k_priv *priv,\n \tif (ret < 0)\n \t\tgoto out;\n \treg |= QCA8K_VTU_FUNC0_VALID | QCA8K_VTU_FUNC0_IVL_EN;\n-\treg &= ~(QCA8K_VTU_FUNC0_EG_MODE_MASK << QCA8K_VTU_FUNC0_EG_MODE_S(port));\n+\treg &= ~QCA8K_VTU_FUNC0_EG_MODE_PORT_MASK(port);\n \tif (untagged)\n-\t\treg |= QCA8K_VTU_FUNC0_EG_MODE_UNTAG <<\n-\t\t\t\tQCA8K_VTU_FUNC0_EG_MODE_S(port);\n+\t\treg |= QCA8K_VTU_FUNC0_EG_MODE_PORT_UNTAG(port);\n \telse\n-\t\treg |= QCA8K_VTU_FUNC0_EG_MODE_TAG <<\n-\t\t\t\tQCA8K_VTU_FUNC0_EG_MODE_S(port);\n+\t\treg |= QCA8K_VTU_FUNC0_EG_MODE_PORT_TAG(port);\n \n \tret = qca8k_write(priv, QCA8K_REG_VTU_FUNC0, reg);\n \tif (ret)\n@@ -534,15 +533,13 @@ qca8k_vlan_del(struct qca8k_priv *priv,\n \tret = qca8k_read(priv, QCA8K_REG_VTU_FUNC0, &reg);\n \tif (ret < 0)\n \t\tgoto out;\n-\treg &= ~(3 << QCA8K_VTU_FUNC0_EG_MODE_S(port));\n-\treg |= QCA8K_VTU_FUNC0_EG_MODE_NOT <<\n-\t\t\tQCA8K_VTU_FUNC0_EG_MODE_S(port);\n+\treg &= ~QCA8K_VTU_FUNC0_EG_MODE_PORT_MASK(port);\n+\treg |= QCA8K_VTU_FUNC0_EG_MODE_PORT_NOT(port);\n \n \t/* Check if we're the last member to be removed */\n \tdel = true;\n \tfor (i = 0; i < QCA8K_NUM_PORTS; i++) {\n-\t\tmask = QCA8K_VTU_FUNC0_EG_MODE_NOT;\n-\t\tmask <<= QCA8K_VTU_FUNC0_EG_MODE_S(i);\n+\t\tmask = QCA8K_VTU_FUNC0_EG_MODE_PORT_NOT(i);\n \n \t\tif ((reg & mask) != mask) {\n \t\t\tdel = false;\n@@ -1014,7 +1011,7 @@ qca8k_parse_port_config(struct qca8k_pri\n \t\t\t\t mode == PHY_INTERFACE_MODE_RGMII_TXID)\n \t\t\t\tdelay = 1;\n \n-\t\t\tif (delay > QCA8K_MAX_DELAY) {\n+\t\t\tif (!FIELD_FIT(QCA8K_PORT_PAD_RGMII_TX_DELAY_MASK, delay)) {\n \t\t\t\tdev_err(priv->dev, \"rgmii tx delay is limited to a max value of 3ns, setting to the max value\");\n \t\t\t\tdelay = 3;\n \t\t\t}\n@@ -1030,7 +1027,7 @@ qca8k_parse_port_config(struct qca8k_pri\n \t\t\t\t mode == PHY_INTERFACE_MODE_RGMII_RXID)\n \t\t\t\tdelay = 2;\n \n-\t\t\tif (delay > QCA8K_MAX_DELAY) {\n+\t\t\tif (!FIELD_FIT(QCA8K_PORT_PAD_RGMII_RX_DELAY_MASK, delay)) {\n \t\t\t\tdev_err(priv->dev, \"rgmii rx delay is limited to a max value of 3ns, setting to the max value\");\n \t\t\t\tdelay = 3;\n \t\t\t}\n@@ -1141,8 +1138,8 @@ qca8k_setup(struct dsa_switch *ds)\n \t\t/* Enable QCA header mode on all cpu ports */\n \t\tif (dsa_is_cpu_port(ds, i)) {\n \t\t\tret = qca8k_write(priv, QCA8K_REG_PORT_HDR_CTRL(i),\n-\t\t\t\t\t  QCA8K_PORT_HDR_CTRL_ALL << QCA8K_PORT_HDR_CTRL_TX_S |\n-\t\t\t\t\t  QCA8K_PORT_HDR_CTRL_ALL << QCA8K_PORT_HDR_CTRL_RX_S);\n+\t\t\t\t\t  FIELD_PREP(QCA8K_PORT_HDR_CTRL_TX_MASK, QCA8K_PORT_HDR_CTRL_ALL) |\n+\t\t\t\t\t  FIELD_PREP(QCA8K_PORT_HDR_CTRL_RX_MASK, QCA8K_PORT_HDR_CTRL_ALL));\n \t\t\tif (ret) {\n \t\t\t\tdev_err(priv->dev, \"failed enabling QCA header mode\");\n \t\t\t\treturn ret;\n@@ -1159,10 +1156,10 @@ qca8k_setup(struct dsa_switch *ds)\n \t * for igmp, unknown, multicast and broadcast packet\n \t */\n \tret = qca8k_write(priv, QCA8K_REG_GLOBAL_FW_CTRL1,\n-\t\t\t  BIT(cpu_port) << QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_S |\n-\t\t\t  BIT(cpu_port) << QCA8K_GLOBAL_FW_CTRL1_BC_DP_S |\n-\t\t\t  BIT(cpu_port) << QCA8K_GLOBAL_FW_CTRL1_MC_DP_S |\n-\t\t\t  BIT(cpu_port) << QCA8K_GLOBAL_FW_CTRL1_UC_DP_S);\n+\t\t\t  FIELD_PREP(QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_MASK, BIT(cpu_port)) |\n+\t\t\t  FIELD_PREP(QCA8K_GLOBAL_FW_CTRL1_BC_DP_MASK, BIT(cpu_port)) |\n+\t\t\t  FIELD_PREP(QCA8K_GLOBAL_FW_CTRL1_MC_DP_MASK, BIT(cpu_port)) |\n+\t\t\t  FIELD_PREP(QCA8K_GLOBAL_FW_CTRL1_UC_DP_MASK, BIT(cpu_port)));\n \tif (ret)\n \t\treturn ret;\n \n@@ -1180,8 +1177,6 @@ qca8k_setup(struct dsa_switch *ds)\n \n \t\t/* Individual user ports get connected to CPU port only */\n \t\tif (dsa_is_user_port(ds, i)) {\n-\t\t\tint shift = 16 * (i % 2);\n-\n \t\t\tret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i),\n \t\t\t\t\tQCA8K_PORT_LOOKUP_MEMBER,\n \t\t\t\t\tBIT(cpu_port));\n@@ -1198,8 +1193,8 @@ qca8k_setup(struct dsa_switch *ds)\n \t\t\t * default egress vid\n \t\t\t */\n \t\t\tret = qca8k_rmw(priv, QCA8K_EGRESS_VLAN(i),\n-\t\t\t\t\t0xfff << shift,\n-\t\t\t\t\tQCA8K_PORT_VID_DEF << shift);\n+\t\t\t\t\tQCA8K_EGREES_VLAN_PORT_MASK(i),\n+\t\t\t\t\tQCA8K_EGREES_VLAN_PORT(i, QCA8K_PORT_VID_DEF));\n \t\t\tif (ret)\n \t\t\t\treturn ret;\n \n@@ -1246,7 +1241,7 @@ qca8k_setup(struct dsa_switch *ds)\n \t\t\tQCA8K_PORT_HOL_CTRL1_EG_PORT_BUF_EN |\n \t\t\tQCA8K_PORT_HOL_CTRL1_WRED_EN;\n \t\t\tqca8k_rmw(priv, QCA8K_REG_PORT_HOL_CTRL1(i),\n-\t\t\t\t  QCA8K_PORT_HOL_CTRL1_ING_BUF |\n+\t\t\t\t  QCA8K_PORT_HOL_CTRL1_ING_BUF_MASK |\n \t\t\t\t  QCA8K_PORT_HOL_CTRL1_EG_PRI_BUF_EN |\n \t\t\t\t  QCA8K_PORT_HOL_CTRL1_EG_PORT_BUF_EN |\n \t\t\t\t  QCA8K_PORT_HOL_CTRL1_WRED_EN,\n@@ -1269,8 +1264,8 @@ qca8k_setup(struct dsa_switch *ds)\n \t\tmask = QCA8K_GLOBAL_FC_GOL_XON_THRES(288) |\n \t\t       QCA8K_GLOBAL_FC_GOL_XOFF_THRES(496);\n \t\tqca8k_rmw(priv, QCA8K_REG_GLOBAL_FC_THRESH,\n-\t\t\t  QCA8K_GLOBAL_FC_GOL_XON_THRES_S |\n-\t\t\t  QCA8K_GLOBAL_FC_GOL_XOFF_THRES_S,\n+\t\t\t  QCA8K_GLOBAL_FC_GOL_XON_THRES_MASK |\n+\t\t\t  QCA8K_GLOBAL_FC_GOL_XOFF_THRES_MASK,\n \t\t\t  mask);\n \t}\n \n@@ -1918,11 +1913,11 @@ qca8k_port_vlan_filtering(struct dsa_swi\n \n \tif (vlan_filtering) {\n \t\tqca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),\n-\t\t\t  QCA8K_PORT_LOOKUP_VLAN_MODE,\n+\t\t\t  QCA8K_PORT_LOOKUP_VLAN_MODE_MASK,\n \t\t\t  QCA8K_PORT_LOOKUP_VLAN_MODE_SECURE);\n \t} else {\n \t\tqca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),\n-\t\t\t  QCA8K_PORT_LOOKUP_VLAN_MODE,\n+\t\t\t  QCA8K_PORT_LOOKUP_VLAN_MODE_MASK,\n \t\t\t  QCA8K_PORT_LOOKUP_VLAN_MODE_NONE);\n \t}\n \n@@ -1953,11 +1948,9 @@ qca8k_port_vlan_add(struct dsa_switch *d\n \t\tdev_err(priv->dev, \"Failed to add VLAN to port %d (%d)\", port, ret);\n \n \tif (pvid) {\n-\t\tint shift = 16 * (port % 2);\n-\n \t\tqca8k_rmw(priv, QCA8K_EGRESS_VLAN(port),\n-\t\t\t  0xfff << shift,\n-\t\t\t  vlan->vid_end << shift);\n+\t\t\t  QCA8K_EGREES_VLAN_PORT_MASK(port),\n+\t\t\t  QCA8K_EGREES_VLAN_PORT(port, vlan->vid_end));\n \t\tqca8k_write(priv, QCA8K_REG_PORT_VLAN_CTRL0(port),\n \t\t\t    QCA8K_PORT_VLAN_CVID(vlan->vid_end) |\n \t\t\t    QCA8K_PORT_VLAN_SVID(vlan->vid_end));\n@@ -2050,7 +2043,7 @@ static int qca8k_read_switch_id(struct q\n \tif (ret < 0)\n \t\treturn -ENODEV;\n \n-\tid = QCA8K_MASK_CTRL_DEVICE_ID(val & QCA8K_MASK_CTRL_DEVICE_ID_MASK);\n+\tid = QCA8K_MASK_CTRL_DEVICE_ID(val);\n \tif (id != data->id) {\n \t\tdev_err(priv->dev, \"Switch id detected %x but expected %x\", id, data->id);\n \t\treturn -ENODEV;\n@@ -2059,7 +2052,7 @@ static int qca8k_read_switch_id(struct q\n \tpriv->switch_id = id;\n \n \t/* Save revision to communicate to the internal PHY driver */\n-\tpriv->switch_revision = (val & QCA8K_MASK_CTRL_REV_ID_MASK);\n+\tpriv->switch_revision = QCA8K_MASK_CTRL_REV_ID(val);\n \n \treturn 0;\n }\n--- a/drivers/net/dsa/qca8k.h\n+++ b/drivers/net/dsa/qca8k.h\n@@ -30,9 +30,9 @@\n /* Global control registers */\n #define QCA8K_REG_MASK_CTRL\t\t\t\t0x000\n #define   QCA8K_MASK_CTRL_REV_ID_MASK\t\t\tGENMASK(7, 0)\n-#define   QCA8K_MASK_CTRL_REV_ID(x)\t\t\t((x) >> 0)\n+#define   QCA8K_MASK_CTRL_REV_ID(x)\t\t\tFIELD_GET(QCA8K_MASK_CTRL_REV_ID_MASK, x)\n #define   QCA8K_MASK_CTRL_DEVICE_ID_MASK\t\tGENMASK(15, 8)\n-#define   QCA8K_MASK_CTRL_DEVICE_ID(x)\t\t\t((x) >> 8)\n+#define   QCA8K_MASK_CTRL_DEVICE_ID(x)\t\t\tFIELD_GET(QCA8K_MASK_CTRL_DEVICE_ID_MASK, x)\n #define QCA8K_REG_PORT0_PAD_CTRL\t\t\t0x004\n #define   QCA8K_PORT0_PAD_MAC06_EXCHANGE_EN\t\tBIT(31)\n #define   QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE\tBIT(19)\n@@ -41,12 +41,11 @@\n #define QCA8K_REG_PORT6_PAD_CTRL\t\t\t0x00c\n #define   QCA8K_PORT_PAD_RGMII_EN\t\t\tBIT(26)\n #define   QCA8K_PORT_PAD_RGMII_TX_DELAY_MASK\t\tGENMASK(23, 22)\n-#define   QCA8K_PORT_PAD_RGMII_TX_DELAY(x)\t\t((x) << 22)\n+#define   QCA8K_PORT_PAD_RGMII_TX_DELAY(x)\t\tFIELD_PREP(QCA8K_PORT_PAD_RGMII_TX_DELAY_MASK, x)\n #define   QCA8K_PORT_PAD_RGMII_RX_DELAY_MASK\t\tGENMASK(21, 20)\n-#define   QCA8K_PORT_PAD_RGMII_RX_DELAY(x)\t\t((x) << 20)\n+#define   QCA8K_PORT_PAD_RGMII_RX_DELAY(x)\t\tFIELD_PREP(QCA8K_PORT_PAD_RGMII_RX_DELAY_MASK, x)\n #define\t  QCA8K_PORT_PAD_RGMII_TX_DELAY_EN\t\tBIT(25)\n #define   QCA8K_PORT_PAD_RGMII_RX_DELAY_EN\t\tBIT(24)\n-#define   QCA8K_MAX_DELAY\t\t\t\t3\n #define   QCA8K_PORT_PAD_SGMII_EN\t\t\tBIT(7)\n #define QCA8K_REG_PWS\t\t\t\t\t0x010\n #define   QCA8K_PWS_POWER_ON_SEL\t\t\tBIT(31)\n@@ -68,10 +67,12 @@\n #define   QCA8K_MDIO_MASTER_READ\t\t\tBIT(27)\n #define   QCA8K_MDIO_MASTER_WRITE\t\t\t0\n #define   QCA8K_MDIO_MASTER_SUP_PRE\t\t\tBIT(26)\n-#define   QCA8K_MDIO_MASTER_PHY_ADDR(x)\t\t\t((x) << 21)\n-#define   QCA8K_MDIO_MASTER_REG_ADDR(x)\t\t\t((x) << 16)\n-#define   QCA8K_MDIO_MASTER_DATA(x)\t\t\t(x)\n+#define   QCA8K_MDIO_MASTER_PHY_ADDR_MASK\t\tGENMASK(25, 21)\n+#define   QCA8K_MDIO_MASTER_PHY_ADDR(x)\t\t\tFIELD_PREP(QCA8K_MDIO_MASTER_PHY_ADDR_MASK, x)\n+#define   QCA8K_MDIO_MASTER_REG_ADDR_MASK\t\tGENMASK(20, 16)\n+#define   QCA8K_MDIO_MASTER_REG_ADDR(x)\t\t\tFIELD_PREP(QCA8K_MDIO_MASTER_REG_ADDR_MASK, x)\n #define   QCA8K_MDIO_MASTER_DATA_MASK\t\t\tGENMASK(15, 0)\n+#define   QCA8K_MDIO_MASTER_DATA(x)\t\t\tFIELD_PREP(QCA8K_MDIO_MASTER_DATA_MASK, x)\n #define   QCA8K_MDIO_MASTER_MAX_PORTS\t\t\t5\n #define   QCA8K_MDIO_MASTER_MAX_REG\t\t\t32\n #define QCA8K_GOL_MAC_ADDR0\t\t\t\t0x60\n@@ -93,9 +94,7 @@\n #define   QCA8K_PORT_STATUS_FLOW_AUTO\t\t\tBIT(12)\n #define QCA8K_REG_PORT_HDR_CTRL(_i)\t\t\t(0x9c + (_i * 4))\n #define   QCA8K_PORT_HDR_CTRL_RX_MASK\t\t\tGENMASK(3, 2)\n-#define   QCA8K_PORT_HDR_CTRL_RX_S\t\t\t2\n #define   QCA8K_PORT_HDR_CTRL_TX_MASK\t\t\tGENMASK(1, 0)\n-#define   QCA8K_PORT_HDR_CTRL_TX_S\t\t\t0\n #define   QCA8K_PORT_HDR_CTRL_ALL\t\t\t2\n #define   QCA8K_PORT_HDR_CTRL_MGMT\t\t\t1\n #define   QCA8K_PORT_HDR_CTRL_NONE\t\t\t0\n@@ -105,10 +104,11 @@\n #define   QCA8K_SGMII_EN_TX\t\t\t\tBIT(3)\n #define   QCA8K_SGMII_EN_SD\t\t\t\tBIT(4)\n #define   QCA8K_SGMII_CLK125M_DELAY\t\t\tBIT(7)\n-#define   QCA8K_SGMII_MODE_CTRL_MASK\t\t\t(BIT(22) | BIT(23))\n-#define   QCA8K_SGMII_MODE_CTRL_BASEX\t\t\t(0 << 22)\n-#define   QCA8K_SGMII_MODE_CTRL_PHY\t\t\t(1 << 22)\n-#define   QCA8K_SGMII_MODE_CTRL_MAC\t\t\t(2 << 22)\n+#define   QCA8K_SGMII_MODE_CTRL_MASK\t\t\tGENMASK(23, 22)\n+#define   QCA8K_SGMII_MODE_CTRL(x)\t\t\tFIELD_PREP(QCA8K_SGMII_MODE_CTRL_MASK, x)\n+#define   QCA8K_SGMII_MODE_CTRL_BASEX\t\t\tQCA8K_SGMII_MODE_CTRL(0x0)\n+#define   QCA8K_SGMII_MODE_CTRL_PHY\t\t\tQCA8K_SGMII_MODE_CTRL(0x1)\n+#define   QCA8K_SGMII_MODE_CTRL_MAC\t\t\tQCA8K_SGMII_MODE_CTRL(0x2)\n \n /* MAC_PWR_SEL registers */\n #define QCA8K_REG_MAC_PWR_SEL\t\t\t\t0x0e4\n@@ -121,100 +121,115 @@\n \n /* ACL registers */\n #define QCA8K_REG_PORT_VLAN_CTRL0(_i)\t\t\t(0x420 + (_i * 8))\n-#define   QCA8K_PORT_VLAN_CVID(x)\t\t\t(x << 16)\n-#define   QCA8K_PORT_VLAN_SVID(x)\t\t\tx\n+#define   QCA8K_PORT_VLAN_CVID_MASK\t\t\tGENMASK(27, 16)\n+#define   QCA8K_PORT_VLAN_CVID(x)\t\t\tFIELD_PREP(QCA8K_PORT_VLAN_CVID_MASK, x)\n+#define   QCA8K_PORT_VLAN_SVID_MASK\t\t\tGENMASK(11, 0)\n+#define   QCA8K_PORT_VLAN_SVID(x)\t\t\tFIELD_PREP(QCA8K_PORT_VLAN_SVID_MASK, x)\n #define QCA8K_REG_PORT_VLAN_CTRL1(_i)\t\t\t(0x424 + (_i * 8))\n #define QCA8K_REG_IPV4_PRI_BASE_ADDR\t\t\t0x470\n #define QCA8K_REG_IPV4_PRI_ADDR_MASK\t\t\t0x474\n \n /* Lookup registers */\n #define QCA8K_REG_ATU_DATA0\t\t\t\t0x600\n-#define   QCA8K_ATU_ADDR2_S\t\t\t\t24\n-#define   QCA8K_ATU_ADDR3_S\t\t\t\t16\n-#define   QCA8K_ATU_ADDR4_S\t\t\t\t8\n+#define   QCA8K_ATU_ADDR2_MASK\t\t\t\tGENMASK(31, 24)\n+#define   QCA8K_ATU_ADDR3_MASK\t\t\t\tGENMASK(23, 16)\n+#define   QCA8K_ATU_ADDR4_MASK\t\t\t\tGENMASK(15, 8)\n+#define   QCA8K_ATU_ADDR5_MASK\t\t\t\tGENMASK(7, 0)\n #define QCA8K_REG_ATU_DATA1\t\t\t\t0x604\n-#define   QCA8K_ATU_PORT_M\t\t\t\t0x7f\n-#define   QCA8K_ATU_PORT_S\t\t\t\t16\n-#define   QCA8K_ATU_ADDR0_S\t\t\t\t8\n+#define   QCA8K_ATU_PORT_MASK\t\t\t\tGENMASK(22, 16)\n+#define   QCA8K_ATU_ADDR0_MASK\t\t\t\tGENMASK(15, 8)\n+#define   QCA8K_ATU_ADDR1_MASK\t\t\t\tGENMASK(7, 0)\n #define QCA8K_REG_ATU_DATA2\t\t\t\t0x608\n-#define   QCA8K_ATU_VID_M\t\t\t\t0xfff\n-#define   QCA8K_ATU_VID_S\t\t\t\t8\n-#define   QCA8K_ATU_STATUS_M\t\t\t\t0xf\n+#define   QCA8K_ATU_VID_MASK\t\t\t\tGENMASK(19, 8)\n+#define   QCA8K_ATU_STATUS_MASK\t\t\t\tGENMASK(3, 0)\n #define   QCA8K_ATU_STATUS_STATIC\t\t\t0xf\n #define QCA8K_REG_ATU_FUNC\t\t\t\t0x60c\n #define   QCA8K_ATU_FUNC_BUSY\t\t\t\tBIT(31)\n #define   QCA8K_ATU_FUNC_PORT_EN\t\t\tBIT(14)\n #define   QCA8K_ATU_FUNC_MULTI_EN\t\t\tBIT(13)\n #define   QCA8K_ATU_FUNC_FULL\t\t\t\tBIT(12)\n-#define   QCA8K_ATU_FUNC_PORT_M\t\t\t\t0xf\n-#define   QCA8K_ATU_FUNC_PORT_S\t\t\t\t8\n+#define   QCA8K_ATU_FUNC_PORT_MASK\t\t\tGENMASK(11, 8)\n #define QCA8K_REG_VTU_FUNC0\t\t\t\t0x610\n #define   QCA8K_VTU_FUNC0_VALID\t\t\t\tBIT(20)\n #define   QCA8K_VTU_FUNC0_IVL_EN\t\t\tBIT(19)\n-#define   QCA8K_VTU_FUNC0_EG_MODE_S(_i)\t\t\t(4 + (_i) * 2)\n-#define   QCA8K_VTU_FUNC0_EG_MODE_MASK\t\t\t3\n-#define   QCA8K_VTU_FUNC0_EG_MODE_UNMOD\t\t\t0\n-#define   QCA8K_VTU_FUNC0_EG_MODE_UNTAG\t\t\t1\n-#define   QCA8K_VTU_FUNC0_EG_MODE_TAG\t\t\t2\n-#define   QCA8K_VTU_FUNC0_EG_MODE_NOT\t\t\t3\n+/*        QCA8K_VTU_FUNC0_EG_MODE_MASK\t\t\tGENMASK(17, 4)\n+ *          It does contain VLAN_MODE for each port [5:4] for port0,\n+ *          [7:6] for port1 ... [17:16] for port6. Use virtual port\n+ *          define to handle this.\n+ */\n+#define   QCA8K_VTU_FUNC0_EG_MODE_PORT_SHIFT(_i)\t(4 + (_i) * 2)\n+#define   QCA8K_VTU_FUNC0_EG_MODE_MASK\t\t\tGENMASK(1, 0)\n+#define   QCA8K_VTU_FUNC0_EG_MODE_PORT_MASK(_i)\t\t(GENMASK(1, 0) << QCA8K_VTU_FUNC0_EG_MODE_PORT_SHIFT(_i))\n+#define   QCA8K_VTU_FUNC0_EG_MODE_UNMOD\t\t\tFIELD_PREP(QCA8K_VTU_FUNC0_EG_MODE_MASK, 0x0)\n+#define   QCA8K_VTU_FUNC0_EG_MODE_PORT_UNMOD(_i)\t(QCA8K_VTU_FUNC0_EG_MODE_UNMOD << QCA8K_VTU_FUNC0_EG_MODE_PORT_SHIFT(_i))\n+#define   QCA8K_VTU_FUNC0_EG_MODE_UNTAG\t\t\tFIELD_PREP(QCA8K_VTU_FUNC0_EG_MODE_MASK, 0x1)\n+#define   QCA8K_VTU_FUNC0_EG_MODE_PORT_UNTAG(_i)\t(QCA8K_VTU_FUNC0_EG_MODE_UNTAG << QCA8K_VTU_FUNC0_EG_MODE_PORT_SHIFT(_i))\n+#define   QCA8K_VTU_FUNC0_EG_MODE_TAG\t\t\tFIELD_PREP(QCA8K_VTU_FUNC0_EG_MODE_MASK, 0x2)\n+#define   QCA8K_VTU_FUNC0_EG_MODE_PORT_TAG(_i)\t\t(QCA8K_VTU_FUNC0_EG_MODE_TAG << QCA8K_VTU_FUNC0_EG_MODE_PORT_SHIFT(_i))\n+#define   QCA8K_VTU_FUNC0_EG_MODE_NOT\t\t\tFIELD_PREP(QCA8K_VTU_FUNC0_EG_MODE_MASK, 0x3)\n+#define   QCA8K_VTU_FUNC0_EG_MODE_PORT_NOT(_i)\t\t(QCA8K_VTU_FUNC0_EG_MODE_NOT << QCA8K_VTU_FUNC0_EG_MODE_PORT_SHIFT(_i))\n #define QCA8K_REG_VTU_FUNC1\t\t\t\t0x614\n #define   QCA8K_VTU_FUNC1_BUSY\t\t\t\tBIT(31)\n-#define   QCA8K_VTU_FUNC1_VID_S\t\t\t\t16\n+#define   QCA8K_VTU_FUNC1_VID_MASK\t\t\tGENMASK(27, 16)\n #define   QCA8K_VTU_FUNC1_FULL\t\t\t\tBIT(4)\n #define QCA8K_REG_GLOBAL_FW_CTRL0\t\t\t0x620\n #define   QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN\t\tBIT(10)\n #define QCA8K_REG_GLOBAL_FW_CTRL1\t\t\t0x624\n-#define   QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_S\t\t24\n-#define   QCA8K_GLOBAL_FW_CTRL1_BC_DP_S\t\t\t16\n-#define   QCA8K_GLOBAL_FW_CTRL1_MC_DP_S\t\t\t8\n-#define   QCA8K_GLOBAL_FW_CTRL1_UC_DP_S\t\t\t0\n+#define   QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_MASK\t\tGENMASK(30, 24)\n+#define   QCA8K_GLOBAL_FW_CTRL1_BC_DP_MASK\t\tGENMASK(22, 16)\n+#define   QCA8K_GLOBAL_FW_CTRL1_MC_DP_MASK\t\tGENMASK(14, 8)\n+#define   QCA8K_GLOBAL_FW_CTRL1_UC_DP_MASK\t\tGENMASK(6, 0)\n #define QCA8K_PORT_LOOKUP_CTRL(_i)\t\t\t(0x660 + (_i) * 0xc)\n #define   QCA8K_PORT_LOOKUP_MEMBER\t\t\tGENMASK(6, 0)\n-#define   QCA8K_PORT_LOOKUP_VLAN_MODE\t\t\tGENMASK(9, 8)\n-#define   QCA8K_PORT_LOOKUP_VLAN_MODE_NONE\t\t(0 << 8)\n-#define   QCA8K_PORT_LOOKUP_VLAN_MODE_FALLBACK\t\t(1 << 8)\n-#define   QCA8K_PORT_LOOKUP_VLAN_MODE_CHECK\t\t(2 << 8)\n-#define   QCA8K_PORT_LOOKUP_VLAN_MODE_SECURE\t\t(3 << 8)\n+#define   QCA8K_PORT_LOOKUP_VLAN_MODE_MASK\t\tGENMASK(9, 8)\n+#define   QCA8K_PORT_LOOKUP_VLAN_MODE(x)\t\tFIELD_PREP(QCA8K_PORT_LOOKUP_VLAN_MODE_MASK, x)\n+#define   QCA8K_PORT_LOOKUP_VLAN_MODE_NONE\t\tQCA8K_PORT_LOOKUP_VLAN_MODE(0x0)\n+#define   QCA8K_PORT_LOOKUP_VLAN_MODE_FALLBACK\t\tQCA8K_PORT_LOOKUP_VLAN_MODE(0x1)\n+#define   QCA8K_PORT_LOOKUP_VLAN_MODE_CHECK\t\tQCA8K_PORT_LOOKUP_VLAN_MODE(0x2)\n+#define   QCA8K_PORT_LOOKUP_VLAN_MODE_SECURE\t\tQCA8K_PORT_LOOKUP_VLAN_MODE(0x3)\n #define   QCA8K_PORT_LOOKUP_STATE_MASK\t\t\tGENMASK(18, 16)\n-#define   QCA8K_PORT_LOOKUP_STATE_DISABLED\t\t(0 << 16)\n-#define   QCA8K_PORT_LOOKUP_STATE_BLOCKING\t\t(1 << 16)\n-#define   QCA8K_PORT_LOOKUP_STATE_LISTENING\t\t(2 << 16)\n-#define   QCA8K_PORT_LOOKUP_STATE_LEARNING\t\t(3 << 16)\n-#define   QCA8K_PORT_LOOKUP_STATE_FORWARD\t\t(4 << 16)\n-#define   QCA8K_PORT_LOOKUP_STATE\t\t\tGENMASK(18, 16)\n+#define   QCA8K_PORT_LOOKUP_STATE(x)\t\t\tFIELD_PREP(QCA8K_PORT_LOOKUP_STATE_MASK, x)\n+#define   QCA8K_PORT_LOOKUP_STATE_DISABLED\t\tQCA8K_PORT_LOOKUP_STATE(0x0)\n+#define   QCA8K_PORT_LOOKUP_STATE_BLOCKING\t\tQCA8K_PORT_LOOKUP_STATE(0x1)\n+#define   QCA8K_PORT_LOOKUP_STATE_LISTENING\t\tQCA8K_PORT_LOOKUP_STATE(0x2)\n+#define   QCA8K_PORT_LOOKUP_STATE_LEARNING\t\tQCA8K_PORT_LOOKUP_STATE(0x3)\n+#define   QCA8K_PORT_LOOKUP_STATE_FORWARD\t\tQCA8K_PORT_LOOKUP_STATE(0x4)\n #define   QCA8K_PORT_LOOKUP_LEARN\t\t\tBIT(20)\n \n #define QCA8K_REG_GLOBAL_FC_THRESH\t\t\t0x800\n-#define   QCA8K_GLOBAL_FC_GOL_XON_THRES(x)\t\t((x) << 16)\n-#define   QCA8K_GLOBAL_FC_GOL_XON_THRES_S\t\tGENMASK(24, 16)\n-#define   QCA8K_GLOBAL_FC_GOL_XOFF_THRES(x)\t\t((x) << 0)\n-#define   QCA8K_GLOBAL_FC_GOL_XOFF_THRES_S\t\tGENMASK(8, 0)\n+#define   QCA8K_GLOBAL_FC_GOL_XON_THRES_MASK\t\tGENMASK(24, 16)\n+#define   QCA8K_GLOBAL_FC_GOL_XON_THRES(x)\t\tFIELD_PREP(QCA8K_GLOBAL_FC_GOL_XON_THRES_MASK, x)\n+#define   QCA8K_GLOBAL_FC_GOL_XOFF_THRES_MASK\t\tGENMASK(8, 0)\n+#define   QCA8K_GLOBAL_FC_GOL_XOFF_THRES(x)\t\tFIELD_PREP(QCA8K_GLOBAL_FC_GOL_XOFF_THRES_MASK, x)\n \n #define QCA8K_REG_PORT_HOL_CTRL0(_i)\t\t\t(0x970 + (_i) * 0x8)\n-#define   QCA8K_PORT_HOL_CTRL0_EG_PRI0_BUF\t\tGENMASK(3, 0)\n-#define   QCA8K_PORT_HOL_CTRL0_EG_PRI0(x)\t\t((x) << 0)\n-#define   QCA8K_PORT_HOL_CTRL0_EG_PRI1_BUF\t\tGENMASK(7, 4)\n-#define   QCA8K_PORT_HOL_CTRL0_EG_PRI1(x)\t\t((x) << 4)\n-#define   QCA8K_PORT_HOL_CTRL0_EG_PRI2_BUF\t\tGENMASK(11, 8)\n-#define   QCA8K_PORT_HOL_CTRL0_EG_PRI2(x)\t\t((x) << 8)\n-#define   QCA8K_PORT_HOL_CTRL0_EG_PRI3_BUF\t\tGENMASK(15, 12)\n-#define   QCA8K_PORT_HOL_CTRL0_EG_PRI3(x)\t\t((x) << 12)\n-#define   QCA8K_PORT_HOL_CTRL0_EG_PRI4_BUF\t\tGENMASK(19, 16)\n-#define   QCA8K_PORT_HOL_CTRL0_EG_PRI4(x)\t\t((x) << 16)\n-#define   QCA8K_PORT_HOL_CTRL0_EG_PRI5_BUF\t\tGENMASK(23, 20)\n-#define   QCA8K_PORT_HOL_CTRL0_EG_PRI5(x)\t\t((x) << 20)\n-#define   QCA8K_PORT_HOL_CTRL0_EG_PORT_BUF\t\tGENMASK(29, 24)\n-#define   QCA8K_PORT_HOL_CTRL0_EG_PORT(x)\t\t((x) << 24)\n+#define   QCA8K_PORT_HOL_CTRL0_EG_PRI0_BUF_MASK\t\tGENMASK(3, 0)\n+#define   QCA8K_PORT_HOL_CTRL0_EG_PRI0(x)\t\tFIELD_PREP(QCA8K_PORT_HOL_CTRL0_EG_PRI0_BUF_MASK, x)\n+#define   QCA8K_PORT_HOL_CTRL0_EG_PRI1_BUF_MASK\t\tGENMASK(7, 4)\n+#define   QCA8K_PORT_HOL_CTRL0_EG_PRI1(x)\t\tFIELD_PREP(QCA8K_PORT_HOL_CTRL0_EG_PRI1_BUF_MASK, x)\n+#define   QCA8K_PORT_HOL_CTRL0_EG_PRI2_BUF_MASK\t\tGENMASK(11, 8)\n+#define   QCA8K_PORT_HOL_CTRL0_EG_PRI2(x)\t\tFIELD_PREP(QCA8K_PORT_HOL_CTRL0_EG_PRI2_BUF_MASK, x)\n+#define   QCA8K_PORT_HOL_CTRL0_EG_PRI3_BUF_MASK\t\tGENMASK(15, 12)\n+#define   QCA8K_PORT_HOL_CTRL0_EG_PRI3(x)\t\tFIELD_PREP(QCA8K_PORT_HOL_CTRL0_EG_PRI3_BUF_MASK, x)\n+#define   QCA8K_PORT_HOL_CTRL0_EG_PRI4_BUF_MASK\t\tGENMASK(19, 16)\n+#define   QCA8K_PORT_HOL_CTRL0_EG_PRI4(x)\t\tFIELD_PREP(QCA8K_PORT_HOL_CTRL0_EG_PRI4_BUF_MASK, x)\n+#define   QCA8K_PORT_HOL_CTRL0_EG_PRI5_BUF_MASK\t\tGENMASK(23, 20)\n+#define   QCA8K_PORT_HOL_CTRL0_EG_PRI5(x)\t\tFIELD_PREP(QCA8K_PORT_HOL_CTRL0_EG_PRI5_BUF_MASK, x)\n+#define   QCA8K_PORT_HOL_CTRL0_EG_PORT_BUF_MASK\t\tGENMASK(29, 24)\n+#define   QCA8K_PORT_HOL_CTRL0_EG_PORT(x)\t\tFIELD_PREP(QCA8K_PORT_HOL_CTRL0_EG_PORT_BUF_MASK, x)\n \n #define QCA8K_REG_PORT_HOL_CTRL1(_i)\t\t\t(0x974 + (_i) * 0x8)\n-#define   QCA8K_PORT_HOL_CTRL1_ING_BUF\t\t\tGENMASK(3, 0)\n-#define   QCA8K_PORT_HOL_CTRL1_ING(x)\t\t\t((x) << 0)\n+#define   QCA8K_PORT_HOL_CTRL1_ING_BUF_MASK\t\tGENMASK(3, 0)\n+#define   QCA8K_PORT_HOL_CTRL1_ING(x)\t\t\tFIELD_PREP(QCA8K_PORT_HOL_CTRL1_ING_BUF_MASK, x)\n #define   QCA8K_PORT_HOL_CTRL1_EG_PRI_BUF_EN\t\tBIT(6)\n #define   QCA8K_PORT_HOL_CTRL1_EG_PORT_BUF_EN\t\tBIT(7)\n #define   QCA8K_PORT_HOL_CTRL1_WRED_EN\t\t\tBIT(8)\n #define   QCA8K_PORT_HOL_CTRL1_EG_MIRROR_EN\t\tBIT(16)\n \n /* Pkt edit registers */\n+#define QCA8K_EGREES_VLAN_PORT_SHIFT(_i)\t\t(16 * ((_i) % 2))\n+#define QCA8K_EGREES_VLAN_PORT_MASK(_i)\t\t\t(GENMASK(11, 0) << QCA8K_EGREES_VLAN_PORT_SHIFT(_i))\n+#define QCA8K_EGREES_VLAN_PORT(_i, x)\t\t\t((x) << QCA8K_EGREES_VLAN_PORT_SHIFT(_i))\n #define QCA8K_EGRESS_VLAN(x)\t\t\t\t(0x0c70 + (4 * (x / 2)))\n \n /* L3 registers */\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/755-net-next-net-dsa-qca8k-remove-extra-mutex_init-in-qca8k_setup.patch",
    "content": "From 994c28b6f971fa5db8ae977daea37eee87d93d51 Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Mon, 22 Nov 2021 16:23:42 +0100\nSubject: net: dsa: qca8k: remove extra mutex_init in qca8k_setup\n\nMutex is already init in sw_probe. Remove the extra init in qca8k_setup.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nReviewed-by: Vladimir Oltean <olteanv@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/dsa/qca8k.c | 2 --\n 1 file changed, 2 deletions(-)\n\n--- a/drivers/net/dsa/qca8k.c\n+++ b/drivers/net/dsa/qca8k.c\n@@ -1086,8 +1086,6 @@ qca8k_setup(struct dsa_switch *ds)\n \tif (ret)\n \t\treturn ret;\n \n-\tmutex_init(&priv->reg_mutex);\n-\n \t/* Start by setting up the register mapping */\n \tpriv->regmap = devm_regmap_init(ds->dev, NULL, priv,\n \t\t\t\t\t&qca8k_regmap_config);\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/756-net-next-net-dsa-qca8k-move-regmap-init-in-probe-and-set-it.patch",
    "content": "From 36b8af12f424e7a7f60a935c60a0fd4aa0822378 Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Mon, 22 Nov 2021 16:23:43 +0100\nSubject: net: dsa: qca8k: move regmap init in probe and set it mandatory\n\nIn preparation for regmap conversion, move regmap init in the probe\nfunction and make it mandatory as any read/write/rmw operation will be\nconverted to regmap API.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nReviewed-by: Vladimir Oltean <olteanv@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/dsa/qca8k.c | 14 ++++++++------\n 1 file changed, 8 insertions(+), 6 deletions(-)\n\n--- a/drivers/net/dsa/qca8k.c\n+++ b/drivers/net/dsa/qca8k.c\n@@ -1086,12 +1086,6 @@ qca8k_setup(struct dsa_switch *ds)\n \tif (ret)\n \t\treturn ret;\n \n-\t/* Start by setting up the register mapping */\n-\tpriv->regmap = devm_regmap_init(ds->dev, NULL, priv,\n-\t\t\t\t\t&qca8k_regmap_config);\n-\tif (IS_ERR(priv->regmap))\n-\t\tdev_warn(priv->dev, \"regmap initialization failed\");\n-\n \tret = qca8k_setup_mdio_bus(priv);\n \tif (ret)\n \t\treturn ret;\n@@ -2085,6 +2079,14 @@ qca8k_sw_probe(struct mdio_device *mdiod\n \t\tgpiod_set_value_cansleep(priv->reset_gpio, 0);\n \t}\n \n+\t/* Start by setting up the register mapping */\n+\tpriv->regmap = devm_regmap_init(&mdiodev->dev, NULL, priv,\n+\t\t\t\t\t&qca8k_regmap_config);\n+\tif (IS_ERR(priv->regmap)) {\n+\t\tdev_err(priv->dev, \"regmap initialization failed\");\n+\t\treturn PTR_ERR(priv->regmap);\n+\t}\n+\n \t/* Check the detected switch id */\n \tret = qca8k_read_switch_id(priv);\n \tif (ret)\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/757-net-next-net-dsa-qca8k-initial-conversion-to-regmap-heper.patch",
    "content": "From 8b5f3f29a81a71934d004e21a1292c1148b05926 Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Mon, 22 Nov 2021 16:23:44 +0100\nSubject: net: dsa: qca8k: initial conversion to regmap helper\n\nConvert any qca8k set/clear/pool to regmap helper and add\nmissing config to regmap_config struct.\nRead/write/rmw operation are reworked to use the regmap helper\ninternally to keep the delta of this patch low. These additional\nfunction will then be dropped when the code split will be proposed.\n\nIpq40xx SoC have the internal switch based on the qca8k regmap but use\nmmio for read/write/rmw operation instead of mdio.\nIn preparation for the support of this internal switch, convert the\ndriver to regmap API to later split the driver to common and specific\ncode. The overhead introduced by the use of regamp API is marginal as the\ninternal mdio will bypass it by using its direct access and regmap will be\nused only by configuration functions or fdb access.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/dsa/qca8k.c | 107 +++++++++++++++++++++---------------------------\n 1 file changed, 47 insertions(+), 60 deletions(-)\n\n--- a/drivers/net/dsa/qca8k.c\n+++ b/drivers/net/dsa/qca8k.c\n@@ -10,6 +10,7 @@\n #include <linux/phy.h>\n #include <linux/netdevice.h>\n #include <linux/bitfield.h>\n+#include <linux/regmap.h>\n #include <net/dsa.h>\n #include <linux/of_net.h>\n #include <linux/of_mdio.h>\n@@ -152,6 +153,25 @@ qca8k_set_page(struct mii_bus *bus, u16\n static int\n qca8k_read(struct qca8k_priv *priv, u32 reg, u32 *val)\n {\n+\treturn regmap_read(priv->regmap, reg, val);\n+}\n+\n+static int\n+qca8k_write(struct qca8k_priv *priv, u32 reg, u32 val)\n+{\n+\treturn regmap_write(priv->regmap, reg, val);\n+}\n+\n+static int\n+qca8k_rmw(struct qca8k_priv *priv, u32 reg, u32 mask, u32 write_val)\n+{\n+\treturn regmap_update_bits(priv->regmap, reg, mask, write_val);\n+}\n+\n+static int\n+qca8k_regmap_read(void *ctx, uint32_t reg, uint32_t *val)\n+{\n+\tstruct qca8k_priv *priv = (struct qca8k_priv *)ctx;\n \tstruct mii_bus *bus = priv->bus;\n \tu16 r1, r2, page;\n \tint ret;\n@@ -172,8 +192,9 @@ exit:\n }\n \n static int\n-qca8k_write(struct qca8k_priv *priv, u32 reg, u32 val)\n+qca8k_regmap_write(void *ctx, uint32_t reg, uint32_t val)\n {\n+\tstruct qca8k_priv *priv = (struct qca8k_priv *)ctx;\n \tstruct mii_bus *bus = priv->bus;\n \tu16 r1, r2, page;\n \tint ret;\n@@ -194,8 +215,9 @@ exit:\n }\n \n static int\n-qca8k_rmw(struct qca8k_priv *priv, u32 reg, u32 mask, u32 write_val)\n+qca8k_regmap_update_bits(void *ctx, uint32_t reg, uint32_t mask, uint32_t write_val)\n {\n+\tstruct qca8k_priv *priv = (struct qca8k_priv *)ctx;\n \tstruct mii_bus *bus = priv->bus;\n \tu16 r1, r2, page;\n \tu32 val;\n@@ -223,34 +245,6 @@ exit:\n \treturn ret;\n }\n \n-static int\n-qca8k_reg_set(struct qca8k_priv *priv, u32 reg, u32 val)\n-{\n-\treturn qca8k_rmw(priv, reg, 0, val);\n-}\n-\n-static int\n-qca8k_reg_clear(struct qca8k_priv *priv, u32 reg, u32 val)\n-{\n-\treturn qca8k_rmw(priv, reg, val, 0);\n-}\n-\n-static int\n-qca8k_regmap_read(void *ctx, uint32_t reg, uint32_t *val)\n-{\n-\tstruct qca8k_priv *priv = (struct qca8k_priv *)ctx;\n-\n-\treturn qca8k_read(priv, reg, val);\n-}\n-\n-static int\n-qca8k_regmap_write(void *ctx, uint32_t reg, uint32_t val)\n-{\n-\tstruct qca8k_priv *priv = (struct qca8k_priv *)ctx;\n-\n-\treturn qca8k_write(priv, reg, val);\n-}\n-\n static const struct regmap_range qca8k_readable_ranges[] = {\n \tregmap_reg_range(0x0000, 0x00e4), /* Global control */\n \tregmap_reg_range(0x0100, 0x0168), /* EEE control */\n@@ -282,26 +276,19 @@ static struct regmap_config qca8k_regmap\n \t.max_register = 0x16ac, /* end MIB - Port6 range */\n \t.reg_read = qca8k_regmap_read,\n \t.reg_write = qca8k_regmap_write,\n+\t.reg_update_bits = qca8k_regmap_update_bits,\n \t.rd_table = &qca8k_readable_table,\n+\t.disable_locking = true, /* Locking is handled by qca8k read/write */\n+\t.cache_type = REGCACHE_NONE, /* Explicitly disable CACHE */\n };\n \n static int\n qca8k_busy_wait(struct qca8k_priv *priv, u32 reg, u32 mask)\n {\n-\tint ret, ret1;\n \tu32 val;\n \n-\tret = read_poll_timeout(qca8k_read, ret1, !(val & mask),\n-\t\t\t\t0, QCA8K_BUSY_WAIT_TIMEOUT * USEC_PER_MSEC, false,\n-\t\t\t\tpriv, reg, &val);\n-\n-\t/* Check if qca8k_read has failed for a different reason\n-\t * before returning -ETIMEDOUT\n-\t */\n-\tif (ret < 0 && ret1 < 0)\n-\t\treturn ret1;\n-\n-\treturn ret;\n+\treturn regmap_read_poll_timeout(priv->regmap, reg, val, !(val & mask), 0,\n+\t\t\t\t       QCA8K_BUSY_WAIT_TIMEOUT * USEC_PER_MSEC);\n }\n \n static int\n@@ -568,7 +555,7 @@ qca8k_mib_init(struct qca8k_priv *priv)\n \tint ret;\n \n \tmutex_lock(&priv->reg_mutex);\n-\tret = qca8k_reg_set(priv, QCA8K_REG_MIB, QCA8K_MIB_FLUSH | QCA8K_MIB_BUSY);\n+\tret = regmap_set_bits(priv->regmap, QCA8K_REG_MIB, QCA8K_MIB_FLUSH | QCA8K_MIB_BUSY);\n \tif (ret)\n \t\tgoto exit;\n \n@@ -576,7 +563,7 @@ qca8k_mib_init(struct qca8k_priv *priv)\n \tif (ret)\n \t\tgoto exit;\n \n-\tret = qca8k_reg_set(priv, QCA8K_REG_MIB, QCA8K_MIB_CPU_KEEP);\n+\tret = regmap_set_bits(priv->regmap, QCA8K_REG_MIB, QCA8K_MIB_CPU_KEEP);\n \tif (ret)\n \t\tgoto exit;\n \n@@ -597,9 +584,9 @@ qca8k_port_set_status(struct qca8k_priv\n \t\tmask |= QCA8K_PORT_STATUS_LINK_AUTO;\n \n \tif (enable)\n-\t\tqca8k_reg_set(priv, QCA8K_REG_PORT_STATUS(port), mask);\n+\t\tregmap_set_bits(priv->regmap, QCA8K_REG_PORT_STATUS(port), mask);\n \telse\n-\t\tqca8k_reg_clear(priv, QCA8K_REG_PORT_STATUS(port), mask);\n+\t\tregmap_clear_bits(priv->regmap, QCA8K_REG_PORT_STATUS(port), mask);\n }\n \n static u32\n@@ -861,8 +848,8 @@ qca8k_setup_mdio_bus(struct qca8k_priv *\n \t\t * a dt-overlay and driver reload changed the configuration\n \t\t */\n \n-\t\treturn qca8k_reg_clear(priv, QCA8K_MDIO_MASTER_CTRL,\n-\t\t\t\t       QCA8K_MDIO_MASTER_EN);\n+\t\treturn regmap_clear_bits(priv->regmap, QCA8K_MDIO_MASTER_CTRL,\n+\t\t\t\t\t QCA8K_MDIO_MASTER_EN);\n \t}\n \n \t/* Check if the devicetree declare the port:phy mapping */\n@@ -1099,16 +1086,16 @@ qca8k_setup(struct dsa_switch *ds)\n \t\treturn ret;\n \n \t/* Make sure MAC06 is disabled */\n-\tret = qca8k_reg_clear(priv, QCA8K_REG_PORT0_PAD_CTRL,\n-\t\t\t      QCA8K_PORT0_PAD_MAC06_EXCHANGE_EN);\n+\tret = regmap_clear_bits(priv->regmap, QCA8K_REG_PORT0_PAD_CTRL,\n+\t\t\t\tQCA8K_PORT0_PAD_MAC06_EXCHANGE_EN);\n \tif (ret) {\n \t\tdev_err(priv->dev, \"failed disabling MAC06 exchange\");\n \t\treturn ret;\n \t}\n \n \t/* Enable CPU Port */\n-\tret = qca8k_reg_set(priv, QCA8K_REG_GLOBAL_FW_CTRL0,\n-\t\t\t    QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN);\n+\tret = regmap_set_bits(priv->regmap, QCA8K_REG_GLOBAL_FW_CTRL0,\n+\t\t\t      QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN);\n \tif (ret) {\n \t\tdev_err(priv->dev, \"failed enabling CPU port\");\n \t\treturn ret;\n@@ -1176,8 +1163,8 @@ qca8k_setup(struct dsa_switch *ds)\n \t\t\t\treturn ret;\n \n \t\t\t/* Enable ARP Auto-learning by default */\n-\t\t\tret = qca8k_reg_set(priv, QCA8K_PORT_LOOKUP_CTRL(i),\n-\t\t\t\t\t    QCA8K_PORT_LOOKUP_LEARN);\n+\t\t\tret = regmap_set_bits(priv->regmap, QCA8K_PORT_LOOKUP_CTRL(i),\n+\t\t\t\t\t      QCA8K_PORT_LOOKUP_LEARN);\n \t\t\tif (ret)\n \t\t\t\treturn ret;\n \n@@ -1745,9 +1732,9 @@ qca8k_port_bridge_join(struct dsa_switch\n \t\t/* Add this port to the portvlan mask of the other ports\n \t\t * in the bridge\n \t\t */\n-\t\tret = qca8k_reg_set(priv,\n-\t\t\t\t    QCA8K_PORT_LOOKUP_CTRL(i),\n-\t\t\t\t    BIT(port));\n+\t\tret = regmap_set_bits(priv->regmap,\n+\t\t\t\t      QCA8K_PORT_LOOKUP_CTRL(i),\n+\t\t\t\t      BIT(port));\n \t\tif (ret)\n \t\t\treturn ret;\n \t\tif (i != port)\n@@ -1777,9 +1764,9 @@ qca8k_port_bridge_leave(struct dsa_switc\n \t\t/* Remove this port to the portvlan mask of the other ports\n \t\t * in the bridge\n \t\t */\n-\t\tqca8k_reg_clear(priv,\n-\t\t\t\tQCA8K_PORT_LOOKUP_CTRL(i),\n-\t\t\t\tBIT(port));\n+\t\tregmap_clear_bits(priv->regmap,\n+\t\t\t\t  QCA8K_PORT_LOOKUP_CTRL(i),\n+\t\t\t\t  BIT(port));\n \t}\n \n \t/* Set the cpu port to be the only one in the portvlan mask of\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/758-net-next-net-dsa-qca8k-add-additional-MIB-counter-and-.patch",
    "content": "From c126f118b330ccf0db0dda4a4bd6c729865a205f Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Mon, 22 Nov 2021 16:23:45 +0100\nSubject: net: dsa: qca8k: add additional MIB counter and make it dynamic\n\nWe are currently missing 2 additionals MIB counter present in QCA833x\nswitch.\nQC832x switch have 39 MIB counter and QCA833X have 41 MIB counter.\nAdd the additional MIB counter and rework the MIB function to print the\ncorrect supported counter from the match_data struct.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nReviewed-by: Vladimir Oltean <olteanv@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/dsa/qca8k.c | 23 ++++++++++++++++++++---\n drivers/net/dsa/qca8k.h |  4 ++++\n 2 files changed, 24 insertions(+), 3 deletions(-)\n\n--- a/drivers/net/dsa/qca8k.c\n+++ b/drivers/net/dsa/qca8k.c\n@@ -70,6 +70,8 @@ static const struct qca8k_mib_desc ar832\n \tMIB_DESC(1, 0x9c, \"TxExcDefer\"),\n \tMIB_DESC(1, 0xa0, \"TxDefer\"),\n \tMIB_DESC(1, 0xa4, \"TxLateCol\"),\n+\tMIB_DESC(1, 0xa8, \"RXUnicast\"),\n+\tMIB_DESC(1, 0xac, \"TXUnicast\"),\n };\n \n /* The 32bit switch registers are accessed indirectly. To achieve this we need\n@@ -1605,12 +1607,16 @@ qca8k_phylink_mac_link_up(struct dsa_swi\n static void\n qca8k_get_strings(struct dsa_switch *ds, int port, u32 stringset, uint8_t *data)\n {\n+\tconst struct qca8k_match_data *match_data;\n+\tstruct qca8k_priv *priv = ds->priv;\n \tint i;\n \n \tif (stringset != ETH_SS_STATS)\n \t\treturn;\n \n-\tfor (i = 0; i < ARRAY_SIZE(ar8327_mib); i++)\n+\tmatch_data = of_device_get_match_data(priv->dev);\n+\n+\tfor (i = 0; i < match_data->mib_count; i++)\n \t\tstrncpy(data + i * ETH_GSTRING_LEN, ar8327_mib[i].name,\n \t\t\tETH_GSTRING_LEN);\n }\n@@ -1620,12 +1626,15 @@ qca8k_get_ethtool_stats(struct dsa_switc\n \t\t\tuint64_t *data)\n {\n \tstruct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;\n+\tconst struct qca8k_match_data *match_data;\n \tconst struct qca8k_mib_desc *mib;\n \tu32 reg, i, val;\n \tu32 hi = 0;\n \tint ret;\n \n-\tfor (i = 0; i < ARRAY_SIZE(ar8327_mib); i++) {\n+\tmatch_data = of_device_get_match_data(priv->dev);\n+\n+\tfor (i = 0; i < match_data->mib_count; i++) {\n \t\tmib = &ar8327_mib[i];\n \t\treg = QCA8K_PORT_MIB_COUNTER(port) + mib->offset;\n \n@@ -1648,10 +1657,15 @@ qca8k_get_ethtool_stats(struct dsa_switc\n static int\n qca8k_get_sset_count(struct dsa_switch *ds, int port, int sset)\n {\n+\tconst struct qca8k_match_data *match_data;\n+\tstruct qca8k_priv *priv = ds->priv;\n+\n \tif (sset != ETH_SS_STATS)\n \t\treturn 0;\n \n-\treturn ARRAY_SIZE(ar8327_mib);\n+\tmatch_data = of_device_get_match_data(priv->dev);\n+\n+\treturn match_data->mib_count;\n }\n \n static int\n@@ -2146,14 +2160,17 @@ static SIMPLE_DEV_PM_OPS(qca8k_pm_ops,\n static const struct qca8k_match_data qca8327 = {\n \t.id = QCA8K_ID_QCA8327,\n \t.reduced_package = true,\n+\t.mib_count = QCA8K_QCA832X_MIB_COUNT,\n };\n \n static const struct qca8k_match_data qca8328 = {\n \t.id = QCA8K_ID_QCA8327,\n+\t.mib_count = QCA8K_QCA832X_MIB_COUNT,\n };\n \n static const struct qca8k_match_data qca833x = {\n \t.id = QCA8K_ID_QCA8337,\n+\t.mib_count = QCA8K_QCA833X_MIB_COUNT,\n };\n \n static const struct of_device_id qca8k_of_match[] = {\n--- a/drivers/net/dsa/qca8k.h\n+++ b/drivers/net/dsa/qca8k.h\n@@ -21,6 +21,9 @@\n #define PHY_ID_QCA8337\t\t\t\t\t0x004dd036\n #define QCA8K_ID_QCA8337\t\t\t\t0x13\n \n+#define QCA8K_QCA832X_MIB_COUNT\t\t\t\t39\n+#define QCA8K_QCA833X_MIB_COUNT\t\t\t\t41\n+\n #define QCA8K_BUSY_WAIT_TIMEOUT\t\t\t\t2000\n \n #define QCA8K_NUM_FDB_RECORDS\t\t\t\t2048\n@@ -279,6 +282,7 @@ struct ar8xxx_port_status {\n struct qca8k_match_data {\n \tu8 id;\n \tbool reduced_package;\n+\tu8 mib_count;\n };\n \n enum {\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/759-net-next-net-dsa-qca8k-add-support-for-port-fast-aging.patch",
    "content": "From 4592538bfb0d5d3c3c8a1d7071724d081412ac91 Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Mon, 22 Nov 2021 16:23:46 +0100\nSubject: net: dsa: qca8k: add support for port fast aging\n\nThe switch supports fast aging by flushing any rule in the ARL\ntable for a specific port.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nReviewed-by: Vladimir Oltean <olteanv@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/dsa/qca8k.c | 11 +++++++++++\n drivers/net/dsa/qca8k.h |  1 +\n 2 files changed, 12 insertions(+)\n\n--- a/drivers/net/dsa/qca8k.c\n+++ b/drivers/net/dsa/qca8k.c\n@@ -1790,6 +1790,16 @@ qca8k_port_bridge_leave(struct dsa_switc\n \t\t  QCA8K_PORT_LOOKUP_MEMBER, BIT(cpu_port));\n }\n \n+static void\n+qca8k_port_fast_age(struct dsa_switch *ds, int port)\n+{\n+\tstruct qca8k_priv *priv = ds->priv;\n+\n+\tmutex_lock(&priv->reg_mutex);\n+\tqca8k_fdb_access(priv, QCA8K_FDB_FLUSH_PORT, port);\n+\tmutex_unlock(&priv->reg_mutex);\n+}\n+\n static int\n qca8k_port_enable(struct dsa_switch *ds, int port,\n \t\t  struct phy_device *phy)\n@@ -2005,6 +2015,7 @@ static const struct dsa_switch_ops qca8k\n \t.port_stp_state_set\t= qca8k_port_stp_state_set,\n \t.port_bridge_join\t= qca8k_port_bridge_join,\n \t.port_bridge_leave\t= qca8k_port_bridge_leave,\n+\t.port_fast_age\t\t= qca8k_port_fast_age,\n \t.port_fdb_add\t\t= qca8k_port_fdb_add,\n \t.port_fdb_del\t\t= qca8k_port_fdb_del,\n \t.port_fdb_dump\t\t= qca8k_port_fdb_dump,\n--- a/drivers/net/dsa/qca8k.h\n+++ b/drivers/net/dsa/qca8k.h\n@@ -262,6 +262,7 @@ enum qca8k_fdb_cmd {\n \tQCA8K_FDB_FLUSH\t= 1,\n \tQCA8K_FDB_LOAD = 2,\n \tQCA8K_FDB_PURGE = 3,\n+\tQCA8K_FDB_FLUSH_PORT = 5,\n \tQCA8K_FDB_NEXT = 6,\n \tQCA8K_FDB_SEARCH = 7,\n };\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/760-net-next-net-dsa-qca8k-add-set_ageing_time-support.patch",
    "content": "From 6a3bdc5209f45d2af83aa92433ab6e5cf2297aa4 Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Mon, 22 Nov 2021 16:23:47 +0100\nSubject: net: dsa: qca8k: add set_ageing_time support\n\nqca8k support setting ageing time in step of 7s. Add support for it and\nset the max value accepted of 7645m.\nDocumentation talks about support for 10000m but that values doesn't\nmake sense as the value doesn't match the max value in the reg.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nReviewed-by: Vladimir Oltean <olteanv@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/dsa/qca8k.c | 25 +++++++++++++++++++++++++\n drivers/net/dsa/qca8k.h |  3 +++\n 2 files changed, 28 insertions(+)\n\n--- a/drivers/net/dsa/qca8k.c\n+++ b/drivers/net/dsa/qca8k.c\n@@ -1261,6 +1261,10 @@ qca8k_setup(struct dsa_switch *ds)\n \t/* We don't have interrupts for link changes, so we need to poll */\n \tds->pcs_poll = true;\n \n+\t/* Set min a max ageing value supported */\n+\tds->ageing_time_min = 7000;\n+\tds->ageing_time_max = 458745000;\n+\n \treturn 0;\n }\n \n@@ -1801,6 +1805,26 @@ qca8k_port_fast_age(struct dsa_switch *d\n }\n \n static int\n+qca8k_set_ageing_time(struct dsa_switch *ds, unsigned int msecs)\n+{\n+\tstruct qca8k_priv *priv = ds->priv;\n+\tunsigned int secs = msecs / 1000;\n+\tu32 val;\n+\n+\t/* AGE_TIME reg is set in 7s step */\n+\tval = secs / 7;\n+\n+\t/* Handle case with 0 as val to NOT disable\n+\t * learning\n+\t */\n+\tif (!val)\n+\t\tval = 1;\n+\n+\treturn regmap_update_bits(priv->regmap, QCA8K_REG_ATU_CTRL, QCA8K_ATU_AGE_TIME_MASK,\n+\t\t\t\t  QCA8K_ATU_AGE_TIME(val));\n+}\n+\n+static int\n qca8k_port_enable(struct dsa_switch *ds, int port,\n \t\t  struct phy_device *phy)\n {\n@@ -2006,6 +2030,7 @@ static const struct dsa_switch_ops qca8k\n \t.get_strings\t\t= qca8k_get_strings,\n \t.get_ethtool_stats\t= qca8k_get_ethtool_stats,\n \t.get_sset_count\t\t= qca8k_get_sset_count,\n+\t.set_ageing_time\t= qca8k_set_ageing_time,\n \t.get_mac_eee\t\t= qca8k_get_mac_eee,\n \t.set_mac_eee\t\t= qca8k_set_mac_eee,\n \t.port_enable\t\t= qca8k_port_enable,\n--- a/drivers/net/dsa/qca8k.h\n+++ b/drivers/net/dsa/qca8k.h\n@@ -175,6 +175,9 @@\n #define   QCA8K_VTU_FUNC1_BUSY\t\t\t\tBIT(31)\n #define   QCA8K_VTU_FUNC1_VID_MASK\t\t\tGENMASK(27, 16)\n #define   QCA8K_VTU_FUNC1_FULL\t\t\t\tBIT(4)\n+#define QCA8K_REG_ATU_CTRL\t\t\t\t0x618\n+#define   QCA8K_ATU_AGE_TIME_MASK\t\t\tGENMASK(15, 0)\n+#define   QCA8K_ATU_AGE_TIME(x)\t\t\t\tFIELD_PREP(QCA8K_ATU_AGE_TIME_MASK, (x))\n #define QCA8K_REG_GLOBAL_FW_CTRL0\t\t\t0x620\n #define   QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN\t\tBIT(10)\n #define QCA8K_REG_GLOBAL_FW_CTRL1\t\t\t0x624\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/761-net-next-net-dsa-qca8k-add-support-for-mdb_add-del.patch",
    "content": "From ba8f870dfa635113ce6e8095a5eb1835ecde2e9e Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Mon, 22 Nov 2021 16:23:48 +0100\nSubject: net: dsa: qca8k: add support for mdb_add/del\n\nAdd support for mdb add/del function. The ARL table is used to insert\nthe rule. The rule will be searched, deleted and reinserted with the\nport mask updated. The function will check if the rule has to be updated\nor insert directly with no deletion of the old rule.\nIf every port is removed from the port mask, the rule is removed.\nThe rule is set STATIC in the ARL table (aka it doesn't age) to not be\nflushed by fast age function.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nReviewed-by: Vladimir Oltean <olteanv@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/dsa/qca8k.c | 99 +++++++++++++++++++++++++++++++++++++++++++++++++\n 1 file changed, 99 insertions(+)\n\n--- a/drivers/net/dsa/qca8k.c\n+++ b/drivers/net/dsa/qca8k.c\n@@ -436,6 +436,81 @@ qca8k_fdb_flush(struct qca8k_priv *priv)\n }\n \n static int\n+qca8k_fdb_search_and_insert(struct qca8k_priv *priv, u8 port_mask,\n+\t\t\t    const u8 *mac, u16 vid)\n+{\n+\tstruct qca8k_fdb fdb = { 0 };\n+\tint ret;\n+\n+\tmutex_lock(&priv->reg_mutex);\n+\n+\tqca8k_fdb_write(priv, vid, 0, mac, 0);\n+\tret = qca8k_fdb_access(priv, QCA8K_FDB_SEARCH, -1);\n+\tif (ret < 0)\n+\t\tgoto exit;\n+\n+\tret = qca8k_fdb_read(priv, &fdb);\n+\tif (ret < 0)\n+\t\tgoto exit;\n+\n+\t/* Rule exist. Delete first */\n+\tif (!fdb.aging) {\n+\t\tret = qca8k_fdb_access(priv, QCA8K_FDB_PURGE, -1);\n+\t\tif (ret)\n+\t\t\tgoto exit;\n+\t}\n+\n+\t/* Add port to fdb portmask */\n+\tfdb.port_mask |= port_mask;\n+\n+\tqca8k_fdb_write(priv, vid, fdb.port_mask, mac, fdb.aging);\n+\tret = qca8k_fdb_access(priv, QCA8K_FDB_LOAD, -1);\n+\n+exit:\n+\tmutex_unlock(&priv->reg_mutex);\n+\treturn ret;\n+}\n+\n+static int\n+qca8k_fdb_search_and_del(struct qca8k_priv *priv, u8 port_mask,\n+\t\t\t const u8 *mac, u16 vid)\n+{\n+\tstruct qca8k_fdb fdb = { 0 };\n+\tint ret;\n+\n+\tmutex_lock(&priv->reg_mutex);\n+\n+\tqca8k_fdb_write(priv, vid, 0, mac, 0);\n+\tret = qca8k_fdb_access(priv, QCA8K_FDB_SEARCH, -1);\n+\tif (ret < 0)\n+\t\tgoto exit;\n+\n+\t/* Rule doesn't exist. Why delete? */\n+\tif (!fdb.aging) {\n+\t\tret = -EINVAL;\n+\t\tgoto exit;\n+\t}\n+\n+\tret = qca8k_fdb_access(priv, QCA8K_FDB_PURGE, -1);\n+\tif (ret)\n+\t\tgoto exit;\n+\n+\t/* Only port in the rule is this port. Don't re insert */\n+\tif (fdb.port_mask == port_mask)\n+\t\tgoto exit;\n+\n+\t/* Remove port from port mask */\n+\tfdb.port_mask &= ~port_mask;\n+\n+\tqca8k_fdb_write(priv, vid, fdb.port_mask, mac, fdb.aging);\n+\tret = qca8k_fdb_access(priv, QCA8K_FDB_LOAD, -1);\n+\n+exit:\n+\tmutex_unlock(&priv->reg_mutex);\n+\treturn ret;\n+}\n+\n+static int\n qca8k_vlan_access(struct qca8k_priv *priv, enum qca8k_vlan_cmd cmd, u16 vid)\n {\n \tu32 reg;\n@@ -1929,6 +2004,28 @@ qca8k_port_fdb_dump(struct dsa_switch *d\n \treturn 0;\n }\n \n+static void\n+qca8k_port_mdb_add(struct dsa_switch *ds, int port,\n+\t\t   const struct switchdev_obj_port_mdb *mdb)\n+{\n+\tstruct qca8k_priv *priv = ds->priv;\n+\tconst u8 *addr = mdb->addr;\n+\tu16 vid = mdb->vid;\n+\n+\tqca8k_fdb_search_and_insert(priv, BIT(port), addr, vid);\n+}\n+\n+static int\n+qca8k_port_mdb_del(struct dsa_switch *ds, int port,\n+\t\t   const struct switchdev_obj_port_mdb *mdb)\n+{\n+\tstruct qca8k_priv *priv = ds->priv;\n+\tconst u8 *addr = mdb->addr;\n+\tu16 vid = mdb->vid;\n+\n+\treturn qca8k_fdb_search_and_del(priv, BIT(port), addr, vid);\n+}\n+\n static int\n qca8k_port_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering,\n \t\t\t  struct switchdev_trans *trans)\n@@ -2044,6 +2141,8 @@ static const struct dsa_switch_ops qca8k\n \t.port_fdb_add\t\t= qca8k_port_fdb_add,\n \t.port_fdb_del\t\t= qca8k_port_fdb_del,\n \t.port_fdb_dump\t\t= qca8k_port_fdb_dump,\n+\t.port_mdb_add\t\t= qca8k_port_mdb_add,\n+\t.port_mdb_del\t\t= qca8k_port_mdb_del,\n \t.port_vlan_filtering\t= qca8k_port_vlan_filtering,\n \t.port_vlan_prepare\t= qca8k_port_vlan_prepare,\n \t.port_vlan_add\t\t= qca8k_port_vlan_add,\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/762-v5.11-net-dsa-mt7530-support-setting-MTU.patch",
    "content": "From 9470174e7581e75a8ebd78964997314dfc2e706c Mon Sep 17 00:00:00 2001\nFrom: DENG Qingfang <dqfext@gmail.com>\nDate: Tue, 3 Nov 2020 13:06:18 +0800\nSubject: [PATCH] net: dsa: mt7530: support setting MTU\n\nMT7530/7531 has a global RX packet length register, which can be used\nto set MTU.\n\nSupported packet length values are 1522 (1518 if untagged), 1536,\n1552, and multiple of 1024 (from 2048 to 15360).\n\nSigned-off-by: DENG Qingfang <dqfext@gmail.com>\nLink: https://lore.kernel.org/r/20201103050618.11419-1-dqfext@gmail.com\nSigned-off-by: Jakub Kicinski <kuba@kernel.org>\n---\n drivers/net/dsa/mt7530.c | 49 ++++++++++++++++++++++++++++++++++++++++\n drivers/net/dsa/mt7530.h | 12 ++++++++++\n 2 files changed, 61 insertions(+)\n\n--- a/drivers/net/dsa/mt7530.c\n+++ b/drivers/net/dsa/mt7530.c\n@@ -1015,6 +1015,53 @@ mt7530_port_disable(struct dsa_switch *d\n \tmutex_unlock(&priv->reg_mutex);\n }\n \n+static int\n+mt7530_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu)\n+{\n+\tstruct mt7530_priv *priv = ds->priv;\n+\tstruct mii_bus *bus = priv->bus;\n+\tint length;\n+\tu32 val;\n+\n+\t/* When a new MTU is set, DSA always set the CPU port's MTU to the\n+\t * largest MTU of the slave ports. Because the switch only has a global\n+\t * RX length register, only allowing CPU port here is enough.\n+\t */\n+\tif (!dsa_is_cpu_port(ds, port))\n+\t\treturn 0;\n+\n+\tmutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);\n+\n+\tval = mt7530_mii_read(priv, MT7530_GMACCR);\n+\tval &= ~MAX_RX_PKT_LEN_MASK;\n+\n+\t/* RX length also includes Ethernet header, MTK tag, and FCS length */\n+\tlength = new_mtu + ETH_HLEN + MTK_HDR_LEN + ETH_FCS_LEN;\n+\tif (length <= 1522) {\n+\t\tval |= MAX_RX_PKT_LEN_1522;\n+\t} else if (length <= 1536) {\n+\t\tval |= MAX_RX_PKT_LEN_1536;\n+\t} else if (length <= 1552) {\n+\t\tval |= MAX_RX_PKT_LEN_1552;\n+\t} else {\n+\t\tval &= ~MAX_RX_JUMBO_MASK;\n+\t\tval |= MAX_RX_JUMBO(DIV_ROUND_UP(length, 1024));\n+\t\tval |= MAX_RX_PKT_LEN_JUMBO;\n+\t}\n+\n+\tmt7530_mii_write(priv, MT7530_GMACCR, val);\n+\n+\tmutex_unlock(&bus->mdio_lock);\n+\n+\treturn 0;\n+}\n+\n+static int\n+mt7530_port_max_mtu(struct dsa_switch *ds, int port)\n+{\n+\treturn MT7530_MAX_MTU;\n+}\n+\n static void\n mt7530_stp_state_set(struct dsa_switch *ds, int port, u8 state)\n {\n@@ -2652,6 +2699,8 @@ static const struct dsa_switch_ops mt753\n \t.get_sset_count\t\t= mt7530_get_sset_count,\n \t.port_enable\t\t= mt7530_port_enable,\n \t.port_disable\t\t= mt7530_port_disable,\n+\t.port_change_mtu\t= mt7530_port_change_mtu,\n+\t.port_max_mtu\t\t= mt7530_port_max_mtu,\n \t.port_stp_state_set\t= mt7530_stp_state_set,\n \t.port_bridge_join\t= mt7530_port_bridge_join,\n \t.port_bridge_leave\t= mt7530_port_bridge_leave,\n--- a/drivers/net/dsa/mt7530.h\n+++ b/drivers/net/dsa/mt7530.h\n@@ -11,6 +11,9 @@\n #define MT7530_NUM_FDB_RECORDS\t\t2048\n #define MT7530_ALL_MEMBERS\t\t0xff\n \n+#define MTK_HDR_LEN\t4\n+#define MT7530_MAX_MTU\t(15 * 1024 - ETH_HLEN - ETH_FCS_LEN - MTK_HDR_LEN)\n+\n enum mt753x_id {\n \tID_MT7530 = 0,\n \tID_MT7621 = 1,\n@@ -301,6 +304,15 @@ enum mt7530_vlan_port_attr {\n #define MT7531_DBG_CNT(x)\t\t(0x3018 + (x) * 0x100)\n #define  MT7531_DIS_CLR\t\t\tBIT(31)\n \n+#define MT7530_GMACCR\t\t\t0x30e0\n+#define  MAX_RX_JUMBO(x)\t\t((x) << 2)\n+#define  MAX_RX_JUMBO_MASK\t\tGENMASK(5, 2)\n+#define  MAX_RX_PKT_LEN_MASK\t\tGENMASK(1, 0)\n+#define  MAX_RX_PKT_LEN_1522\t\t0x0\n+#define  MAX_RX_PKT_LEN_1536\t\t0x1\n+#define  MAX_RX_PKT_LEN_1552\t\t0x2\n+#define  MAX_RX_PKT_LEN_JUMBO\t\t0x3\n+\n /* Register for MIB */\n #define MT7530_PORT_MIB_COUNTER(x)\t(0x4000 + (x) * 0x100)\n #define MT7530_MIB_CCR\t\t\t0x4fe0\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/763-v5.11-net-dsa-mt7530-enable-MTU-normalization.patch",
    "content": "From 771c8901568dd8776a260aa93db41be88a60389e Mon Sep 17 00:00:00 2001\nFrom: DENG Qingfang <dqfext@gmail.com>\nDate: Fri, 11 Dec 2020 01:03:22 +0800\nSubject: [PATCH] net: dsa: mt7530: enable MTU normalization\n\nMT7530 has a global RX length register, so we are actually changing its\nMRU.\nEnable MTU normalization for this reason.\n\nSigned-off-by: DENG Qingfang <dqfext@gmail.com>\nAcked-by: Landen Chao <landen.chao@mediatek.com>\nReviewed-by: Vladimir Oltean <olteanv@gmail.com>\nLink: https://lore.kernel.org/r/20201210170322.3433-1-dqfext@gmail.com\nSigned-off-by: Jakub Kicinski <kuba@kernel.org>\n---\n drivers/net/dsa/mt7530.c | 2 ++\n 1 file changed, 2 insertions(+)\n\n--- a/drivers/net/dsa/mt7530.c\n+++ b/drivers/net/dsa/mt7530.c\n@@ -1703,6 +1703,7 @@ mt7530_setup(struct dsa_switch *ds)\n \t */\n \tdn = dsa_to_port(ds, MT7530_CPU_PORT)->master->dev.of_node->parent;\n \tds->configure_vlan_while_not_filtering = true;\n+\tds->mtu_enforcement_ingress = true;\n \n \tif (priv->id == ID_MT7530) {\n \t\tregulator_set_voltage(priv->core_pwr, 1000000, 1000000);\n@@ -1947,6 +1948,7 @@ mt7531_setup(struct dsa_switch *ds)\n \t}\n \n \tds->configure_vlan_while_not_filtering = true;\n+\tds->mtu_enforcement_ingress = true;\n \n \t/* Flush the FDB table */\n \tret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL);\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/764-v5.11-net-dsa-mt7530-support-setting-ageing-time.patch",
    "content": "From ea6d5c924e391872d402acac38461a5f8261e57f Mon Sep 17 00:00:00 2001\nFrom: DENG Qingfang <dqfext@gmail.com>\nDate: Tue, 8 Dec 2020 15:00:28 +0800\nSubject: [PATCH] net: dsa: mt7530: support setting ageing time\n\nMT7530 has a global address age control register, so use it to set\nageing time.\n\nThe applied timer is (AGE_CNT + 1) * (AGE_UNIT + 1) seconds\n\nSigned-off-by: DENG Qingfang <dqfext@gmail.com>\nReviewed-by: Andrew Lunn <andrew@lunn.ch>\nReviewed-by: Vladimir Oltean <olteanv@gmail.com>\nReviewed-by: Florian Fainelli <f.fainelli@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/dsa/mt7530.c | 41 ++++++++++++++++++++++++++++++++++++++++\n drivers/net/dsa/mt7530.h | 13 +++++++++++++\n 2 files changed, 54 insertions(+)\n\n--- a/drivers/net/dsa/mt7530.c\n+++ b/drivers/net/dsa/mt7530.c\n@@ -870,6 +870,46 @@ mt7530_get_sset_count(struct dsa_switch\n \treturn ARRAY_SIZE(mt7530_mib);\n }\n \n+static int\n+mt7530_set_ageing_time(struct dsa_switch *ds, unsigned int msecs)\n+{\n+\tstruct mt7530_priv *priv = ds->priv;\n+\tunsigned int secs = msecs / 1000;\n+\tunsigned int tmp_age_count;\n+\tunsigned int error = -1;\n+\tunsigned int age_count;\n+\tunsigned int age_unit;\n+\n+\t/* Applied timer is (AGE_CNT + 1) * (AGE_UNIT + 1) seconds */\n+\tif (secs < 1 || secs > (AGE_CNT_MAX + 1) * (AGE_UNIT_MAX + 1))\n+\t\treturn -ERANGE;\n+\n+\t/* iterate through all possible age_count to find the closest pair */\n+\tfor (tmp_age_count = 0; tmp_age_count <= AGE_CNT_MAX; ++tmp_age_count) {\n+\t\tunsigned int tmp_age_unit = secs / (tmp_age_count + 1) - 1;\n+\n+\t\tif (tmp_age_unit <= AGE_UNIT_MAX) {\n+\t\t\tunsigned int tmp_error = secs -\n+\t\t\t\t(tmp_age_count + 1) * (tmp_age_unit + 1);\n+\n+\t\t\t/* found a closer pair */\n+\t\t\tif (error > tmp_error) {\n+\t\t\t\terror = tmp_error;\n+\t\t\t\tage_count = tmp_age_count;\n+\t\t\t\tage_unit = tmp_age_unit;\n+\t\t\t}\n+\n+\t\t\t/* found the exact match, so break the loop */\n+\t\t\tif (!error)\n+\t\t\t\tbreak;\n+\t\t}\n+\t}\n+\n+\tmt7530_write(priv, MT7530_AAC, AGE_CNT(age_count) | AGE_UNIT(age_unit));\n+\n+\treturn 0;\n+}\n+\n static void mt7530_setup_port5(struct dsa_switch *ds, phy_interface_t interface)\n {\n \tstruct mt7530_priv *priv = ds->priv;\n@@ -2699,6 +2739,7 @@ static const struct dsa_switch_ops mt753\n \t.phy_write\t\t= mt753x_phy_write,\n \t.get_ethtool_stats\t= mt7530_get_ethtool_stats,\n \t.get_sset_count\t\t= mt7530_get_sset_count,\n+\t.set_ageing_time\t= mt7530_set_ageing_time,\n \t.port_enable\t\t= mt7530_port_enable,\n \t.port_disable\t\t= mt7530_port_disable,\n \t.port_change_mtu\t= mt7530_port_change_mtu,\n--- a/drivers/net/dsa/mt7530.h\n+++ b/drivers/net/dsa/mt7530.h\n@@ -161,6 +161,19 @@ enum mt7530_vlan_egress_attr {\n \tMT7530_VLAN_EGRESS_STACK = 3,\n };\n \n+/* Register for address age control */\n+#define MT7530_AAC\t\t\t0xa0\n+/* Disable ageing */\n+#define  AGE_DIS\t\t\tBIT(20)\n+/* Age count */\n+#define  AGE_CNT_MASK\t\t\tGENMASK(19, 12)\n+#define  AGE_CNT_MAX\t\t\t0xff\n+#define  AGE_CNT(x)\t\t\t(AGE_CNT_MASK & ((x) << 12))\n+/* Age unit */\n+#define  AGE_UNIT_MASK\t\t\tGENMASK(11, 0)\n+#define  AGE_UNIT_MAX\t\t\t0xfff\n+#define  AGE_UNIT(x)\t\t\t(AGE_UNIT_MASK & (x))\n+\n /* Register for port STP state control */\n #define MT7530_SSP_P(x)\t\t\t(0x2000 + ((x) * 0x100))\n #define  FID_PST(x)\t\t\t((x) & 0x3)\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/770-v5.15-net-dsa-mt7530-support-MDB-operations.patch",
    "content": "From 1f11a07a33bc26997c18b633d63f088bf75d11f2 Mon Sep 17 00:00:00 2001\nFrom: DENG Qingfang <dqfext@gmail.com>\nDate: Tue, 24 Aug 2021 11:37:50 +0800\nSubject: [PATCH] net: dsa: mt7530: support MDB operations\n\nThis is a partial backport of commit 5a30833b9a16f8d1aa15de06636f9317ca51f9df\n(\"net: dsa: mt7530: support MDB and bridge flag operations\") upstream.\n\nSigned-off-by: DENG Qingfang <dqfext@gmail.com>\n---\n drivers/net/dsa/mt7530.c | 78 ++++++++++++++++++++++++++++++++++++++--\n net/dsa/tag_mtk.c        | 14 +-------\n 2 files changed, 76 insertions(+), 16 deletions(-)\n\n--- a/drivers/net/dsa/mt7530.c\n+++ b/drivers/net/dsa/mt7530.c\n@@ -998,9 +998,6 @@ mt753x_cpu_port_enable(struct dsa_switch\n \tmt7530_write(priv, MT7530_PVC_P(port),\n \t\t     PORT_SPEC_TAG);\n \n-\t/* Unknown multicast frame forwarding to the cpu port */\n-\tmt7530_rmw(priv, MT7530_MFC, UNM_FFP_MASK, UNM_FFP(BIT(port)));\n-\n \t/* Set CPU port number */\n \tif (priv->id == ID_MT7621)\n \t\tmt7530_rmw(priv, MT7530_MFC, CPU_MASK, CPU_EN | CPU_PORT(port));\n@@ -1131,6 +1128,20 @@ mt7530_stp_state_set(struct dsa_switch *\n }\n \n static int\n+mt7530_port_egress_floods(struct dsa_switch *ds, int port,\n+\t\t\t  bool unicast, bool multicast)\n+{\n+\tstruct mt7530_priv *priv = ds->priv;\n+\n+\tmt7530_rmw(priv, MT7530_MFC,\n+\t\t   UNU_FFP(BIT(port)) | UNM_FFP(BIT(port)),\n+\t\t   (unicast ? UNU_FFP(BIT(port)) : 0) |\n+\t\t   (multicast ? UNM_FFP(BIT(port)) : 0));\n+\n+\treturn 0;\n+}\n+\n+static int\n mt7530_port_bridge_join(struct dsa_switch *ds, int port,\n \t\t\tstruct net_device *bridge)\n {\n@@ -1331,6 +1342,63 @@ err:\n }\n \n static int\n+mt7530_port_mdb_prepare(struct dsa_switch *ds, int port,\n+\t\t\tconst struct switchdev_obj_port_mdb *mdb)\n+{\n+\treturn 0;\n+}\n+\n+static void\n+mt7530_port_mdb_add(struct dsa_switch *ds, int port,\n+\t\t    const struct switchdev_obj_port_mdb *mdb)\n+{\n+\tstruct mt7530_priv *priv = ds->priv;\n+\tconst u8 *addr = mdb->addr;\n+\tu16 vid = mdb->vid;\n+\tu8 port_mask = 0;\n+\n+\tmutex_lock(&priv->reg_mutex);\n+\n+\tmt7530_fdb_write(priv, vid, 0, addr, 0, STATIC_EMP);\n+\tif (!mt7530_fdb_cmd(priv, MT7530_FDB_READ, NULL))\n+\t\tport_mask = (mt7530_read(priv, MT7530_ATRD) >> PORT_MAP)\n+\t\t\t    & PORT_MAP_MASK;\n+\n+\tport_mask |= BIT(port);\n+\tmt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT);\n+\tmt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL);\n+\n+\tmutex_unlock(&priv->reg_mutex);\n+}\n+\n+static int\n+mt7530_port_mdb_del(struct dsa_switch *ds, int port,\n+\t\t    const struct switchdev_obj_port_mdb *mdb)\n+{\n+\tstruct mt7530_priv *priv = ds->priv;\n+\tconst u8 *addr = mdb->addr;\n+\tu16 vid = mdb->vid;\n+\tu8 port_mask = 0;\n+\tint ret;\n+\n+\tmutex_lock(&priv->reg_mutex);\n+\n+\tmt7530_fdb_write(priv, vid, 0, addr, 0, STATIC_EMP);\n+\tif (!mt7530_fdb_cmd(priv, MT7530_FDB_READ, NULL))\n+\t\tport_mask = (mt7530_read(priv, MT7530_ATRD) >> PORT_MAP)\n+\t\t\t    & PORT_MAP_MASK;\n+\n+\tport_mask &= ~BIT(port);\n+\tmt7530_fdb_write(priv, vid, port_mask, addr, -1,\n+\t\t\t port_mask ? STATIC_ENT : STATIC_EMP);\n+\tret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL);\n+\n+\tmutex_unlock(&priv->reg_mutex);\n+\n+\treturn ret;\n+}\n+\n+static int\n mt7530_vlan_cmd(struct mt7530_priv *priv, enum mt7530_vlan_cmd cmd, u16 vid)\n {\n \tstruct mt7530_dummy_poll p;\n@@ -2745,11 +2813,15 @@ static const struct dsa_switch_ops mt753\n \t.port_change_mtu\t= mt7530_port_change_mtu,\n \t.port_max_mtu\t\t= mt7530_port_max_mtu,\n \t.port_stp_state_set\t= mt7530_stp_state_set,\n+\t.port_egress_floods\t= mt7530_port_egress_floods,\n \t.port_bridge_join\t= mt7530_port_bridge_join,\n \t.port_bridge_leave\t= mt7530_port_bridge_leave,\n \t.port_fdb_add\t\t= mt7530_port_fdb_add,\n \t.port_fdb_del\t\t= mt7530_port_fdb_del,\n \t.port_fdb_dump\t\t= mt7530_port_fdb_dump,\n+\t.port_mdb_prepare\t= mt7530_port_mdb_prepare,\n+\t.port_mdb_add\t\t= mt7530_port_mdb_add,\n+\t.port_mdb_del\t\t= mt7530_port_mdb_del,\n \t.port_vlan_filtering\t= mt7530_port_vlan_filtering,\n \t.port_vlan_prepare\t= mt7530_port_vlan_prepare,\n \t.port_vlan_add\t\t= mt7530_port_vlan_add,\n--- a/net/dsa/tag_mtk.c\n+++ b/net/dsa/tag_mtk.c\n@@ -24,9 +24,6 @@ static struct sk_buff *mtk_tag_xmit(stru\n \tstruct dsa_port *dp = dsa_slave_to_port(dev);\n \tu8 xmit_tpid;\n \tu8 *mtk_tag;\n-\tunsigned char *dest = eth_hdr(skb)->h_dest;\n-\tbool is_multicast_skb = is_multicast_ether_addr(dest) &&\n-\t\t\t\t!is_broadcast_ether_addr(dest);\n \n \t/* Build the special tag after the MAC Source Address. If VLAN header\n \t * is present, it's required that VLAN header and special tag is\n@@ -55,10 +52,6 @@ static struct sk_buff *mtk_tag_xmit(stru\n \tmtk_tag[0] = xmit_tpid;\n \tmtk_tag[1] = (1 << dp->index) & MTK_HDR_XMIT_DP_BIT_MASK;\n \n-\t/* Disable SA learning for multicast frames */\n-\tif (unlikely(is_multicast_skb))\n-\t\tmtk_tag[1] |= MTK_HDR_XMIT_SA_DIS;\n-\n \t/* Tag control information is kept for 802.1Q */\n \tif (xmit_tpid == MTK_HDR_XMIT_UNTAGGED) {\n \t\tmtk_tag[2] = 0;\n@@ -74,9 +67,6 @@ static struct sk_buff *mtk_tag_rcv(struc\n \tu16 hdr;\n \tint port;\n \t__be16 *phdr;\n-\tunsigned char *dest = eth_hdr(skb)->h_dest;\n-\tbool is_multicast_skb = is_multicast_ether_addr(dest) &&\n-\t\t\t\t!is_broadcast_ether_addr(dest);\n \n \tif (unlikely(!pskb_may_pull(skb, MTK_HDR_LEN)))\n \t\treturn NULL;\n@@ -102,9 +92,7 @@ static struct sk_buff *mtk_tag_rcv(struc\n \tif (!skb->dev)\n \t\treturn NULL;\n \n-\t/* Only unicast or broadcast frames are offloaded */\n-\tif (likely(!is_multicast_skb))\n-\t\tdsa_default_offload_fwd_mark(skb);\n+\tdsa_default_offload_fwd_mark(skb);\n \n \treturn skb;\n }\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/771-v5.14-net-phy-add-MediaTek-Gigabit-Ethernet-PHY-driver.patch",
    "content": "From e40d2cca01893c1941f5959b14bb0cd0d4f4d099 Mon Sep 17 00:00:00 2001\nFrom: DENG Qingfang <dqfext@gmail.com>\nDate: Wed, 19 May 2021 11:31:59 +0800\nSubject: [PATCH] net: phy: add MediaTek Gigabit Ethernet PHY driver\n\nAdd support for MediaTek Gigabit Ethernet PHYs found in MT7530 and\nMT7531 switches.\nThe initialization procedure is from the vendor driver, but due to lack\nof documentation, the function of some register values remains unknown.\n\nSigned-off-by: DENG Qingfang <dqfext@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/phy/Kconfig       |   5 ++\n drivers/net/phy/Makefile      |   1 +\n drivers/net/phy/mediatek-ge.c | 116 ++++++++++++++++++++++++++++++++++\n 3 files changed, 122 insertions(+)\n create mode 100644 drivers/net/phy/mediatek-ge.c\n\n--- a/drivers/net/phy/Kconfig\n+++ b/drivers/net/phy/Kconfig\n@@ -201,6 +201,11 @@ config MARVELL_10G_PHY\n \thelp\n \t  Support for the Marvell Alaska MV88X3310 and compatible PHYs.\n \n+config MEDIATEK_GE_PHY\n+\ttristate \"MediaTek PHYs\"\n+\thelp\n+\t  Supports the MediaTek switch integrated PHYs.\n+\n config MICREL_PHY\n \ttristate \"Micrel PHYs\"\n \thelp\n--- a/drivers/net/phy/Makefile\n+++ b/drivers/net/phy/Makefile\n@@ -63,6 +63,7 @@ obj-$(CONFIG_LSI_ET1011C_PHY)\t+= et1011c\n obj-$(CONFIG_LXT_PHY)\t\t+= lxt.o\n obj-$(CONFIG_MARVELL_10G_PHY)\t+= marvell10g.o\n obj-$(CONFIG_MARVELL_PHY)\t+= marvell.o\n+obj-$(CONFIG_MEDIATEK_GE_PHY)\t+= mediatek-ge.o\n obj-$(CONFIG_MESON_GXL_PHY)\t+= meson-gxl.o\n obj-$(CONFIG_MICREL_KS8995MA)\t+= spi_ks8995.o\n obj-$(CONFIG_MICREL_PHY)\t+= micrel.o\n--- /dev/null\n+++ b/drivers/net/phy/mediatek-ge.c\n@@ -0,0 +1,113 @@\n+// SPDX-License-Identifier: GPL-2.0+\n+#include <linux/bitfield.h>\n+#include <linux/module.h>\n+#include <linux/phy.h>\n+\n+#define MTK_T10_TEST_CONTROL\t\t0x145\n+#define MTK_PHY_TP_MASK\t\t\tGENMASK(4, 3)\n+#define MTK_PHY_TP_AUTO\t\t\t0\n+#define MTK_PHY_TP_MDI\t\t\t2\n+#define MTK_PHY_TP_MDIX\t\t\t3\n+\n+#define MTK_EXT_PAGE_ACCESS\t\t0x1f\n+#define MTK_PHY_PAGE_STANDARD\t\t0x0000\n+#define MTK_PHY_PAGE_EXTENDED\t\t0x0001\n+#define MTK_PHY_PAGE_EXTENDED_2\t\t0x0002\n+#define MTK_PHY_PAGE_EXTENDED_3\t\t0x0003\n+#define MTK_PHY_PAGE_EXTENDED_2A30\t0x2a30\n+#define MTK_PHY_PAGE_EXTENDED_52B5\t0x52b5\n+\n+static int mtk_gephy_read_page(struct phy_device *phydev)\n+{\n+\treturn __phy_read(phydev, MTK_EXT_PAGE_ACCESS);\n+}\n+\n+static int mtk_gephy_write_page(struct phy_device *phydev, int page)\n+{\n+\treturn __phy_write(phydev, MTK_EXT_PAGE_ACCESS, page);\n+}\n+\n+static void mtk_gephy_config_init(struct phy_device *phydev)\n+{\n+\t/* Disable EEE */\n+\tphy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0);\n+\n+\t/* Enable HW auto downshift */\n+\tphy_modify_paged(phydev, MTK_PHY_PAGE_EXTENDED, 0x14, 0, BIT(4));\n+\n+\t/* Increase SlvDPSready time */\n+\tphy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);\n+\t__phy_write(phydev, 0x10, 0xafae);\n+\t__phy_write(phydev, 0x12, 0x2f);\n+\t__phy_write(phydev, 0x10, 0x8fae);\n+\tphy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);\n+\n+\t/* Adjust 100_mse_threshold */\n+\tphy_write_mmd(phydev, MDIO_MMD_VEND1, 0x123, 0xffff);\n+\n+\t/* Disable mcc */\n+\tphy_write_mmd(phydev, MDIO_MMD_VEND1, 0xa6, 0x300);\n+}\n+\n+static int mt7530_phy_config_init(struct phy_device *phydev)\n+{\n+\tmtk_gephy_config_init(phydev);\n+\n+\t/* Increase post_update_timer */\n+\tphy_write_paged(phydev, MTK_PHY_PAGE_EXTENDED_3, 0x11, 0x4b);\n+\n+\treturn 0;\n+}\n+\n+static int mt7531_phy_config_init(struct phy_device *phydev)\n+{\n+\tmtk_gephy_config_init(phydev);\n+\n+\t/* PHY link down power saving enable */\n+\tphy_set_bits(phydev, 0x17, BIT(4));\n+\tphy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 0xc6, 0x300);\n+\n+\t/* Set TX Pair delay selection */\n+\tphy_write_mmd(phydev, MDIO_MMD_VEND1, 0x13, 0x404);\n+\tphy_write_mmd(phydev, MDIO_MMD_VEND1, 0x14, 0x404);\n+\n+\treturn 0;\n+}\n+\n+static struct phy_driver mtk_gephy_driver[] = {\n+\t{\n+\t\tPHY_ID_MATCH_EXACT(0x03a29412),\n+\t\t.name\t\t= \"MediaTek MT7530 PHY\",\n+\t\t.config_init\t= mt7530_phy_config_init,\n+\t\t/* Interrupts are handled by the switch, not the PHY\n+\t\t * itself.\n+\t\t */\n+\t\t.config_intr\t= genphy_no_config_intr,\n+\t\t.ack_interrupt  = genphy_no_ack_interrupt,\n+\t\t.suspend\t= genphy_suspend,\n+\t\t.resume\t\t= genphy_resume,\n+\t\t.read_page\t= mtk_gephy_read_page,\n+\t\t.write_page\t= mtk_gephy_write_page,\n+\t},\n+\t{\n+\t\tPHY_ID_MATCH_EXACT(0x03a29441),\n+\t\t.name\t\t= \"MediaTek MT7531 PHY\",\n+\t\t.config_init\t= mt7531_phy_config_init,\n+\t\t/* Interrupts are handled by the switch, not the PHY\n+\t\t * itself.\n+\t\t */\n+\t\t.config_intr\t= genphy_no_config_intr,\n+\t\t.ack_interrupt  = genphy_no_ack_interrupt,\n+\t\t.suspend\t= genphy_suspend,\n+\t\t.resume\t\t= genphy_resume,\n+\t\t.read_page\t= mtk_gephy_read_page,\n+\t\t.write_page\t= mtk_gephy_write_page,\n+\t},\n+};\n+\n+module_phy_driver(mtk_gephy_driver);\n+\n+static struct mdio_device_id __maybe_unused mtk_gephy_tbl[] = {\n+\t{ PHY_ID_MATCH_VENDOR(0x03a29400) },\n+\t{ }\n+};\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/772-v5.14-net-dsa-mt7530-add-interrupt-support.patch",
    "content": "From ba751e28d44255744a30190faad0ca09b455c44d Mon Sep 17 00:00:00 2001\nFrom: DENG Qingfang <dqfext@gmail.com>\nDate: Wed, 19 May 2021 11:32:00 +0800\nSubject: [PATCH] net: dsa: mt7530: add interrupt support\n\nAdd support for MT7530 interrupt controller to handle internal PHYs.\nIn order to assign an IRQ number to each PHY, the registration of MDIO bus\nis also done in this driver.\n\nSigned-off-by: DENG Qingfang <dqfext@gmail.com>\nReviewed-by: Andrew Lunn <andrew@lunn.ch>\nReviewed-by: Florian Fainelli <f.fainelli@gmail.com>\nReviewed-by: Vladimir Oltean <olteanv@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/dsa/mt7530.c | 264 +++++++++++++++++++++++++++++++++++----\n drivers/net/dsa/mt7530.h |  20 ++-\n 2 files changed, 256 insertions(+), 28 deletions(-)\n\n--- a/drivers/net/dsa/mt7530.c\n+++ b/drivers/net/dsa/mt7530.c\n@@ -10,6 +10,7 @@\n #include <linux/mfd/syscon.h>\n #include <linux/module.h>\n #include <linux/netdevice.h>\n+#include <linux/of_irq.h>\n #include <linux/of_mdio.h>\n #include <linux/of_net.h>\n #include <linux/of_platform.h>\n@@ -600,18 +601,14 @@ mt7530_mib_reset(struct dsa_switch *ds)\n \tmt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_ACTIVATE);\n }\n \n-static int mt7530_phy_read(struct dsa_switch *ds, int port, int regnum)\n+static int mt7530_phy_read(struct mt7530_priv *priv, int port, int regnum)\n {\n-\tstruct mt7530_priv *priv = ds->priv;\n-\n \treturn mdiobus_read_nested(priv->bus, port, regnum);\n }\n \n-static int mt7530_phy_write(struct dsa_switch *ds, int port, int regnum,\n+static int mt7530_phy_write(struct mt7530_priv *priv, int port, int regnum,\n \t\t\t    u16 val)\n {\n-\tstruct mt7530_priv *priv = ds->priv;\n-\n \treturn mdiobus_write_nested(priv->bus, port, regnum, val);\n }\n \n@@ -789,9 +786,8 @@ out:\n }\n \n static int\n-mt7531_ind_phy_read(struct dsa_switch *ds, int port, int regnum)\n+mt7531_ind_phy_read(struct mt7530_priv *priv, int port, int regnum)\n {\n-\tstruct mt7530_priv *priv = ds->priv;\n \tint devad;\n \tint ret;\n \n@@ -807,10 +803,9 @@ mt7531_ind_phy_read(struct dsa_switch *d\n }\n \n static int\n-mt7531_ind_phy_write(struct dsa_switch *ds, int port, int regnum,\n+mt7531_ind_phy_write(struct mt7530_priv *priv, int port, int regnum,\n \t\t     u16 data)\n {\n-\tstruct mt7530_priv *priv = ds->priv;\n \tint devad;\n \tint ret;\n \n@@ -826,6 +821,22 @@ mt7531_ind_phy_write(struct dsa_switch *\n \treturn ret;\n }\n \n+static int\n+mt753x_phy_read(struct mii_bus *bus, int port, int regnum)\n+{\n+\tstruct mt7530_priv *priv = bus->priv;\n+\n+\treturn priv->info->phy_read(priv, port, regnum);\n+}\n+\n+static int\n+mt753x_phy_write(struct mii_bus *bus, int port, int regnum, u16 val)\n+{\n+\tstruct mt7530_priv *priv = bus->priv;\n+\n+\treturn priv->info->phy_write(priv, port, regnum, val);\n+}\n+\n static void\n mt7530_get_strings(struct dsa_switch *ds, int port, u32 stringset,\n \t\t   uint8_t *data)\n@@ -1793,6 +1804,210 @@ mt7530_setup_gpio(struct mt7530_priv *pr\n \treturn devm_gpiochip_add_data(dev, gc, priv);\n }\n \n+static irqreturn_t\n+mt7530_irq_thread_fn(int irq, void *dev_id)\n+{\n+\tstruct mt7530_priv *priv = dev_id;\n+\tbool handled = false;\n+\tu32 val;\n+\tint p;\n+\n+\tmutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED);\n+\tval = mt7530_mii_read(priv, MT7530_SYS_INT_STS);\n+\tmt7530_mii_write(priv, MT7530_SYS_INT_STS, val);\n+\tmutex_unlock(&priv->bus->mdio_lock);\n+\n+\tfor (p = 0; p < MT7530_NUM_PHYS; p++) {\n+\t\tif (BIT(p) & val) {\n+\t\t\tunsigned int irq;\n+\n+\t\t\tirq = irq_find_mapping(priv->irq_domain, p);\n+\t\t\thandle_nested_irq(irq);\n+\t\t\thandled = true;\n+\t\t}\n+\t}\n+\n+\treturn IRQ_RETVAL(handled);\n+}\n+\n+static void\n+mt7530_irq_mask(struct irq_data *d)\n+{\n+\tstruct mt7530_priv *priv = irq_data_get_irq_chip_data(d);\n+\n+\tpriv->irq_enable &= ~BIT(d->hwirq);\n+}\n+\n+static void\n+mt7530_irq_unmask(struct irq_data *d)\n+{\n+\tstruct mt7530_priv *priv = irq_data_get_irq_chip_data(d);\n+\n+\tpriv->irq_enable |= BIT(d->hwirq);\n+}\n+\n+static void\n+mt7530_irq_bus_lock(struct irq_data *d)\n+{\n+\tstruct mt7530_priv *priv = irq_data_get_irq_chip_data(d);\n+\n+\tmutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED);\n+}\n+\n+static void\n+mt7530_irq_bus_sync_unlock(struct irq_data *d)\n+{\n+\tstruct mt7530_priv *priv = irq_data_get_irq_chip_data(d);\n+\n+\tmt7530_mii_write(priv, MT7530_SYS_INT_EN, priv->irq_enable);\n+\tmutex_unlock(&priv->bus->mdio_lock);\n+}\n+\n+static struct irq_chip mt7530_irq_chip = {\n+\t.name = KBUILD_MODNAME,\n+\t.irq_mask = mt7530_irq_mask,\n+\t.irq_unmask = mt7530_irq_unmask,\n+\t.irq_bus_lock = mt7530_irq_bus_lock,\n+\t.irq_bus_sync_unlock = mt7530_irq_bus_sync_unlock,\n+};\n+\n+static int\n+mt7530_irq_map(struct irq_domain *domain, unsigned int irq,\n+\t       irq_hw_number_t hwirq)\n+{\n+\tirq_set_chip_data(irq, domain->host_data);\n+\tirq_set_chip_and_handler(irq, &mt7530_irq_chip, handle_simple_irq);\n+\tirq_set_nested_thread(irq, true);\n+\tirq_set_noprobe(irq);\n+\n+\treturn 0;\n+}\n+\n+static const struct irq_domain_ops mt7530_irq_domain_ops = {\n+\t.map = mt7530_irq_map,\n+\t.xlate = irq_domain_xlate_onecell,\n+};\n+\n+static void\n+mt7530_setup_mdio_irq(struct mt7530_priv *priv)\n+{\n+\tstruct dsa_switch *ds = priv->ds;\n+\tint p;\n+\n+\tfor (p = 0; p < MT7530_NUM_PHYS; p++) {\n+\t\tif (BIT(p) & ds->phys_mii_mask) {\n+\t\t\tunsigned int irq;\n+\n+\t\t\tirq = irq_create_mapping(priv->irq_domain, p);\n+\t\t\tds->slave_mii_bus->irq[p] = irq;\n+\t\t}\n+\t}\n+}\n+\n+static int\n+mt7530_setup_irq(struct mt7530_priv *priv)\n+{\n+\tstruct device *dev = priv->dev;\n+\tstruct device_node *np = dev->of_node;\n+\tint ret;\n+\n+\tif (!of_property_read_bool(np, \"interrupt-controller\")) {\n+\t\tdev_info(dev, \"no interrupt support\\n\");\n+\t\treturn 0;\n+\t}\n+\n+\tpriv->irq = of_irq_get(np, 0);\n+\tif (priv->irq <= 0) {\n+\t\tdev_err(dev, \"failed to get parent IRQ: %d\\n\", priv->irq);\n+\t\treturn priv->irq ? : -EINVAL;\n+\t}\n+\n+\tpriv->irq_domain = irq_domain_add_linear(np, MT7530_NUM_PHYS,\n+\t\t\t\t\t\t &mt7530_irq_domain_ops, priv);\n+\tif (!priv->irq_domain) {\n+\t\tdev_err(dev, \"failed to create IRQ domain\\n\");\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\t/* This register must be set for MT7530 to properly fire interrupts */\n+\tif (priv->id != ID_MT7531)\n+\t\tmt7530_set(priv, MT7530_TOP_SIG_CTRL, TOP_SIG_CTRL_NORMAL);\n+\n+\tret = request_threaded_irq(priv->irq, NULL, mt7530_irq_thread_fn,\n+\t\t\t\t   IRQF_ONESHOT, KBUILD_MODNAME, priv);\n+\tif (ret) {\n+\t\tirq_domain_remove(priv->irq_domain);\n+\t\tdev_err(dev, \"failed to request IRQ: %d\\n\", ret);\n+\t\treturn ret;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static void\n+mt7530_free_mdio_irq(struct mt7530_priv *priv)\n+{\n+\tint p;\n+\n+\tfor (p = 0; p < MT7530_NUM_PHYS; p++) {\n+\t\tif (BIT(p) & priv->ds->phys_mii_mask) {\n+\t\t\tunsigned int irq;\n+\n+\t\t\tirq = irq_find_mapping(priv->irq_domain, p);\n+\t\t\tirq_dispose_mapping(irq);\n+\t\t}\n+\t}\n+}\n+\n+static void\n+mt7530_free_irq_common(struct mt7530_priv *priv)\n+{\n+\tfree_irq(priv->irq, priv);\n+\tirq_domain_remove(priv->irq_domain);\n+}\n+\n+static void\n+mt7530_free_irq(struct mt7530_priv *priv)\n+{\n+\tmt7530_free_mdio_irq(priv);\n+\tmt7530_free_irq_common(priv);\n+}\n+\n+static int\n+mt7530_setup_mdio(struct mt7530_priv *priv)\n+{\n+\tstruct dsa_switch *ds = priv->ds;\n+\tstruct device *dev = priv->dev;\n+\tstruct mii_bus *bus;\n+\tstatic int idx;\n+\tint ret;\n+\n+\tbus = devm_mdiobus_alloc(dev);\n+\tif (!bus)\n+\t\treturn -ENOMEM;\n+\n+\tds->slave_mii_bus = bus;\n+\tbus->priv = priv;\n+\tbus->name = KBUILD_MODNAME \"-mii\";\n+\tsnprintf(bus->id, MII_BUS_ID_SIZE, KBUILD_MODNAME \"-%d\", idx++);\n+\tbus->read = mt753x_phy_read;\n+\tbus->write = mt753x_phy_write;\n+\tbus->parent = dev;\n+\tbus->phy_mask = ~ds->phys_mii_mask;\n+\n+\tif (priv->irq)\n+\t\tmt7530_setup_mdio_irq(priv);\n+\n+\tret = devm_mdiobus_register(dev, bus);\n+\tif (ret) {\n+\t\tdev_err(dev, \"failed to register MDIO bus: %d\\n\", ret);\n+\t\tif (priv->irq)\n+\t\t\tmt7530_free_mdio_irq(priv);\n+\t}\n+\n+\treturn ret;\n+}\n+\n static int\n mt7530_setup(struct dsa_switch *ds)\n {\n@@ -2749,24 +2964,20 @@ static int\n mt753x_setup(struct dsa_switch *ds)\n {\n \tstruct mt7530_priv *priv = ds->priv;\n+\tint ret = priv->info->sw_setup(ds);\n \n-\treturn priv->info->sw_setup(ds);\n-}\n-\n-static int\n-mt753x_phy_read(struct dsa_switch *ds, int port, int regnum)\n-{\n-\tstruct mt7530_priv *priv = ds->priv;\n+\tif (ret)\n+\t\treturn ret;\n \n-\treturn priv->info->phy_read(ds, port, regnum);\n-}\n+\tret = mt7530_setup_irq(priv);\n+\tif (ret)\n+\t\treturn ret;\n \n-static int\n-mt753x_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val)\n-{\n-\tstruct mt7530_priv *priv = ds->priv;\n+\tret = mt7530_setup_mdio(priv);\n+\tif (ret && priv->irq)\n+\t\tmt7530_free_irq_common(priv);\n \n-\treturn priv->info->phy_write(ds, port, regnum, val);\n+\treturn ret;\n }\n \n static int mt753x_get_mac_eee(struct dsa_switch *ds, int port,\n@@ -2803,8 +3014,6 @@ static const struct dsa_switch_ops mt753\n \t.get_tag_protocol\t= mtk_get_tag_protocol,\n \t.setup\t\t\t= mt753x_setup,\n \t.get_strings\t\t= mt7530_get_strings,\n-\t.phy_read\t\t= mt753x_phy_read,\n-\t.phy_write\t\t= mt753x_phy_write,\n \t.get_ethtool_stats\t= mt7530_get_ethtool_stats,\n \t.get_sset_count\t\t= mt7530_get_sset_count,\n \t.set_ageing_time\t= mt7530_set_ageing_time,\n@@ -2987,6 +3196,9 @@ mt7530_remove(struct mdio_device *mdiode\n \t\tdev_err(priv->dev, \"Failed to disable io pwr: %d\\n\",\n \t\t\tret);\n \n+\tif (priv->irq)\n+\t\tmt7530_free_irq(priv);\n+\n \tdsa_unregister_switch(priv->ds);\n \tmutex_destroy(&priv->reg_mutex);\n }\n--- a/drivers/net/dsa/mt7530.h\n+++ b/drivers/net/dsa/mt7530.h\n@@ -7,6 +7,7 @@\n #define __MT7530_H\n \n #define MT7530_NUM_PORTS\t\t7\n+#define MT7530_NUM_PHYS\t\t\t5\n #define MT7530_CPU_PORT\t\t\t6\n #define MT7530_NUM_FDB_RECORDS\t\t2048\n #define MT7530_ALL_MEMBERS\t\t0xff\n@@ -392,6 +393,12 @@ enum mt7531_sgmii_force_duplex {\n #define  SYS_CTRL_SW_RST\t\tBIT(1)\n #define  SYS_CTRL_REG_RST\t\tBIT(0)\n \n+/* Register for system interrupt */\n+#define MT7530_SYS_INT_EN\t\t0x7008\n+\n+/* Register for system interrupt status */\n+#define MT7530_SYS_INT_STS\t\t0x700c\n+\n /* Register for PHY Indirect Access Control */\n #define MT7531_PHY_IAC\t\t\t0x701C\n #define  MT7531_PHY_ACS_ST\t\tBIT(31)\n@@ -713,6 +720,8 @@ static const char *p5_intf_modes(unsigne\n \t}\n }\n \n+struct mt7530_priv;\n+\n /* struct mt753x_info -\tThis is the main data structure for holding the specific\n  *\t\t\tpart for each supported device\n  * @sw_setup:\t\tHolding the handler to a device initialization\n@@ -737,8 +746,8 @@ struct mt753x_info {\n \tenum mt753x_id id;\n \n \tint (*sw_setup)(struct dsa_switch *ds);\n-\tint (*phy_read)(struct dsa_switch *ds, int port, int regnum);\n-\tint (*phy_write)(struct dsa_switch *ds, int port, int regnum, u16 val);\n+\tint (*phy_read)(struct mt7530_priv *priv, int port, int regnum);\n+\tint (*phy_write)(struct mt7530_priv *priv, int port, int regnum, u16 val);\n \tint (*pad_setup)(struct dsa_switch *ds, phy_interface_t interface);\n \tint (*cpu_port_config)(struct dsa_switch *ds, int port);\n \tbool (*phy_mode_supported)(struct dsa_switch *ds, int port,\n@@ -772,6 +781,10 @@ struct mt753x_info {\n  *\t\t\tregisters\n  * @p6_interface\tHolding the current port 6 interface\n  * @p5_intf_sel:\tHolding the current port 5 interface select\n+ *\n+ * @irq:\t\tIRQ number of the switch\n+ * @irq_domain:\t\tIRQ domain of the switch irq_chip\n+ * @irq_enable:\t\tIRQ enable bits, synced to SYS_INT_EN\n  */\n struct mt7530_priv {\n \tstruct device\t\t*dev;\n@@ -793,6 +806,9 @@ struct mt7530_priv {\n \tstruct mt7530_port\tports[MT7530_NUM_PORTS];\n \t/* protect among processes for registers access*/\n \tstruct mutex reg_mutex;\n+\tint irq;\n+\tstruct irq_domain *irq_domain;\n+\tu32 irq_enable;\n };\n \n struct mt7530_hw_vlan_entry {\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/773-v5.18-1-net-dsa-Move-VLAN-filtering-syncing-out-of-dsa_switc.patch",
    "content": "From 7164a8cde4b42f76474088ccaf53f1e463d4e2f6 Mon Sep 17 00:00:00 2001\nFrom: Tobias Waldekranz <tobias@waldekranz.com>\nDate: Mon, 24 Jan 2022 22:09:43 +0100\nSubject: [PATCH 5.10 1/2] net: dsa: Move VLAN filtering syncing out of\n dsa_switch_bridge_leave\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\ncommit 381a730182f1d174e1950cd4e63e885b1c302051 upstream.\n\nMost of dsa_switch_bridge_leave was, in fact, dealing with the syncing\nof VLAN filtering for switches on which that is a global\nsetting. Separate the two phases to prepare for the cross-chip related\nbugfix in the following commit.\n\nSigned-off-by: Tobias Waldekranz <tobias@waldekranz.com>\nReviewed-by: Vladimir Oltean <olteanv@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\nSigned-off-by: Marek Behún <kabel@kernel.org>\n---\n net/dsa/switch.c | 39 ++++++++++++++++++++++++++-------------\n 1 file changed, 26 insertions(+), 13 deletions(-)\n\n--- a/net/dsa/switch.c\n+++ b/net/dsa/switch.c\n@@ -104,23 +104,12 @@ static int dsa_switch_bridge_join(struct\n \treturn 0;\n }\n \n-static int dsa_switch_bridge_leave(struct dsa_switch *ds,\n-\t\t\t\t   struct dsa_notifier_bridge_info *info)\n+static int dsa_switch_sync_vlan_filtering(struct dsa_switch *ds,\n+\t\t\t\t\t  struct dsa_notifier_bridge_info *info)\n {\n \tbool unset_vlan_filtering = br_vlan_enabled(info->br);\n-\tstruct dsa_switch_tree *dst = ds->dst;\n \tint err, i;\n \n-\tif (dst->index == info->tree_index && ds->index == info->sw_index &&\n-\t    ds->ops->port_bridge_leave)\n-\t\tds->ops->port_bridge_leave(ds, info->port, info->br);\n-\n-\tif ((dst->index != info->tree_index || ds->index != info->sw_index) &&\n-\t    ds->ops->crosschip_bridge_leave)\n-\t\tds->ops->crosschip_bridge_leave(ds, info->tree_index,\n-\t\t\t\t\t\tinfo->sw_index, info->port,\n-\t\t\t\t\t\tinfo->br);\n-\n \t/* If the bridge was vlan_filtering, the bridge core doesn't trigger an\n \t * event for changing vlan_filtering setting upon slave ports leaving\n \t * it. That is a good thing, because that lets us handle it and also\n@@ -153,6 +142,30 @@ static int dsa_switch_bridge_leave(struc\n \t\tif (err && err != EOPNOTSUPP)\n \t\t\treturn err;\n \t}\n+\n+\treturn 0;\n+}\n+\n+static int dsa_switch_bridge_leave(struct dsa_switch *ds,\n+\t\t\t\t   struct dsa_notifier_bridge_info *info)\n+{\n+\tstruct dsa_switch_tree *dst = ds->dst;\n+\tint err;\n+\n+\tif (dst->index == info->tree_index && ds->index == info->sw_index &&\n+\t    ds->ops->port_bridge_leave)\n+\t\tds->ops->port_bridge_leave(ds, info->port, info->br);\n+\n+\tif ((dst->index != info->tree_index || ds->index != info->sw_index) &&\n+\t    ds->ops->crosschip_bridge_leave)\n+\t\tds->ops->crosschip_bridge_leave(ds, info->tree_index,\n+\t\t\t\t\t\tinfo->sw_index, info->port,\n+\t\t\t\t\t\tinfo->br);\n+\n+\terr = dsa_switch_sync_vlan_filtering(ds, info);\n+\tif (err)\n+\t\treturn err;\n+\n \treturn 0;\n }\n \n"
  },
  {
    "path": "target/linux/generic/backport-5.10/773-v5.18-2-net-dsa-Avoid-cross-chip-syncing-of-VLAN-filtering.patch",
    "content": "From 6948a6654ffc878fc0258b363da77e7fd775b2d9 Mon Sep 17 00:00:00 2001\nFrom: Tobias Waldekranz <tobias@waldekranz.com>\nDate: Mon, 24 Jan 2022 22:09:44 +0100\nSubject: [PATCH 5.10 2/2] net: dsa: Avoid cross-chip syncing of VLAN filtering\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\ncommit 108dc8741c203e9d6ce4e973367f1bac20c7192b upstream.\n\nChanges to VLAN filtering are not applicable to cross-chip\nnotifications.\n\nOn a system like this:\n\n.-----.   .-----.   .-----.\n| sw1 +---+ sw2 +---+ sw3 |\n'-1-2-'   '-1-2-'   '-1-2-'\n\nBefore this change, upon sw1p1 leaving a bridge, a call to\ndsa_port_vlan_filtering would also be made to sw2p1 and sw3p1.\n\nIn this scenario:\n\n.---------.   .-----.   .-----.\n|   sw1   +---+ sw2 +---+ sw3 |\n'-1-2-3-4-'   '-1-2-'   '-1-2-'\n\nWhen sw1p4 would leave a bridge, dsa_port_vlan_filtering would be\ncalled for sw2 and sw3 with a non-existing port - leading to array\nout-of-bounds accesses and crashes on mv88e6xxx.\n\nFixes: d371b7c92d19 (\"net: dsa: Unset vlan_filtering when ports leave the bridge\")\nSigned-off-by: Tobias Waldekranz <tobias@waldekranz.com>\nReviewed-by: Vladimir Oltean <olteanv@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\nSigned-off-by: Marek Behún <kabel@kernel.org>\n---\n net/dsa/switch.c | 8 +++++---\n 1 file changed, 5 insertions(+), 3 deletions(-)\n\n--- a/net/dsa/switch.c\n+++ b/net/dsa/switch.c\n@@ -162,9 +162,11 @@ static int dsa_switch_bridge_leave(struc\n \t\t\t\t\t\tinfo->sw_index, info->port,\n \t\t\t\t\t\tinfo->br);\n \n-\terr = dsa_switch_sync_vlan_filtering(ds, info);\n-\tif (err)\n-\t\treturn err;\n+\tif (dst->index == info->tree_index && ds->index == info->sw_index) {\n+\t\terr = dsa_switch_sync_vlan_filtering(ds, info);\n+\t\tif (err)\n+\t\t\treturn err;\n+\t}\n \n \treturn 0;\n }\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/774-v5.15-1-igc-remove-_I_PHY_ID-checking.patch",
    "content": "From 7c496de538eebd8212dc2a3c9a468386b264d0d4 Mon Sep 17 00:00:00 2001\nFrom: Sasha Neftin <sasha.neftin@intel.com>\nDate: Wed, 7 Jul 2021 08:14:40 +0300\nSubject: igc: Remove _I_PHY_ID checking\n\ni225 devices have only one PHY vendor. There is no point checking\n_I_PHY_ID during the link establishment and auto-negotiation process.\nThis patch comes to clean up these pointless checkings.\n\nSigned-off-by: Sasha Neftin <sasha.neftin@intel.com>\nTested-by: Dvora Fuxbrumer <dvorax.fuxbrumer@linux.intel.com>\nSigned-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>\n---\n drivers/net/ethernet/intel/igc/igc_base.c | 10 +---------\n drivers/net/ethernet/intel/igc/igc_main.c |  3 +--\n drivers/net/ethernet/intel/igc/igc_phy.c  |  6 ++----\n 3 files changed, 4 insertions(+), 15 deletions(-)\n\n(limited to 'drivers/net/ethernet/intel/igc')\n\n--- a/drivers/net/ethernet/intel/igc/igc_base.c\n+++ b/drivers/net/ethernet/intel/igc/igc_base.c\n@@ -187,15 +187,7 @@ static s32 igc_init_phy_params_base(stru\n \n \tigc_check_for_copper_link(hw);\n \n-\t/* Verify phy id and set remaining function pointers */\n-\tswitch (phy->id) {\n-\tcase I225_I_PHY_ID:\n-\t\tphy->type\t= igc_phy_i225;\n-\t\tbreak;\n-\tdefault:\n-\t\tret_val = -IGC_ERR_PHY;\n-\t\tgoto out;\n-\t}\n+\tphy->type = igc_phy_i225;\n \n out:\n \treturn ret_val;\n--- a/drivers/net/ethernet/intel/igc/igc_main.c\n+++ b/drivers/net/ethernet/intel/igc/igc_main.c\n@@ -4189,8 +4189,7 @@ bool igc_has_link(struct igc_adapter *ad\n \t\tbreak;\n \t}\n \n-\tif (hw->mac.type == igc_i225 &&\n-\t    hw->phy.id == I225_I_PHY_ID) {\n+\tif (hw->mac.type == igc_i225) {\n \t\tif (!netif_carrier_ok(adapter->netdev)) {\n \t\t\tadapter->flags &= ~IGC_FLAG_NEED_LINK_UPDATE;\n \t\t} else if (!(adapter->flags & IGC_FLAG_NEED_LINK_UPDATE)) {\n--- a/drivers/net/ethernet/intel/igc/igc_phy.c\n+++ b/drivers/net/ethernet/intel/igc/igc_phy.c\n@@ -249,8 +249,7 @@ static s32 igc_phy_setup_autoneg(struct\n \t\t\treturn ret_val;\n \t}\n \n-\tif ((phy->autoneg_mask & ADVERTISE_2500_FULL) &&\n-\t    hw->phy.id == I225_I_PHY_ID) {\n+\tif (phy->autoneg_mask & ADVERTISE_2500_FULL) {\n \t\t/* Read the MULTI GBT AN Control Register - reg 7.32 */\n \t\tret_val = phy->ops.read_reg(hw, (STANDARD_AN_REG_MASK <<\n \t\t\t\t\t    MMD_DEVADDR_SHIFT) |\n@@ -390,8 +389,7 @@ static s32 igc_phy_setup_autoneg(struct\n \t\tret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL,\n \t\t\t\t\t     mii_1000t_ctrl_reg);\n \n-\tif ((phy->autoneg_mask & ADVERTISE_2500_FULL) &&\n-\t    hw->phy.id == I225_I_PHY_ID)\n+\tif (phy->autoneg_mask & ADVERTISE_2500_FULL)\n \t\tret_val = phy->ops.write_reg(hw,\n \t\t\t\t\t     (STANDARD_AN_REG_MASK <<\n \t\t\t\t\t     MMD_DEVADDR_SHIFT) |\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/774-v5.15-2-igc-remove-phy-type-checking.patch",
    "content": "From 47bca7de6a4fb8dcb564c7ca14d885c91ed19e03 Mon Sep 17 00:00:00 2001\nFrom: Sasha Neftin <sasha.neftin@intel.com>\nDate: Sat, 10 Jul 2021 20:57:50 +0300\nSubject: igc: Remove phy->type checking\n\ni225 devices have only one phy->type: copper. There is no point checking\nphy->type during the igc_has_link method from the watchdog that\ninvoked every 2 seconds.\nThis patch comes to clean up these pointless checkings.\n\nSigned-off-by: Sasha Neftin <sasha.neftin@intel.com>\nTested-by: Dvora Fuxbrumer <dvorax.fuxbrumer@linux.intel.com>\nSigned-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>\n---\n drivers/net/ethernet/intel/igc/igc_main.c | 15 ++++-----------\n 1 file changed, 4 insertions(+), 11 deletions(-)\n\n(limited to 'drivers/net/ethernet/intel/igc')\n\n--- a/drivers/net/ethernet/intel/igc/igc_main.c\n+++ b/drivers/net/ethernet/intel/igc/igc_main.c\n@@ -4177,17 +4177,10 @@ bool igc_has_link(struct igc_adapter *ad\n \t * false until the igc_check_for_link establishes link\n \t * for copper adapters ONLY\n \t */\n-\tswitch (hw->phy.media_type) {\n-\tcase igc_media_type_copper:\n-\t\tif (!hw->mac.get_link_status)\n-\t\t\treturn true;\n-\t\thw->mac.ops.check_for_link(hw);\n-\t\tlink_active = !hw->mac.get_link_status;\n-\t\tbreak;\n-\tdefault:\n-\tcase igc_media_type_unknown:\n-\t\tbreak;\n-\t}\n+\tif (!hw->mac.get_link_status)\n+\t\treturn true;\n+\thw->mac.ops.check_for_link(hw);\n+\tlink_active = !hw->mac.get_link_status;\n \n \tif (hw->mac.type == igc_i225) {\n \t\tif (!netif_carrier_ok(adapter->netdev)) {\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/774-v5.15-net-dsa-mv88e6xxx-keep-the-pvid-at-0-when-VLAN-unawa.patch",
    "content": "From 675992be6f7b603b8cfda4678f173e1021fc1ab6 Mon Sep 17 00:00:00 2001\nFrom: Vladimir Oltean <vladimir.oltean@nxp.com>\nDate: Thu, 7 Oct 2021 19:47:10 +0300\nSubject: [PATCH] net: dsa: mv88e6xxx: keep the pvid at 0 when VLAN-unaware\n\nThe VLAN support in mv88e6xxx has a loaded history. Commit 2ea7a679ca2a\n(\"net: dsa: Don't add vlans when vlan filtering is disabled\") noticed\nsome issues with VLAN and decided the best way to deal with them was to\nmake the DSA core ignore VLANs added by the bridge while VLAN awareness\nis turned off. Those issues were never explained, just presented as\n\"at least one corner case\".\n\nThat approach had problems of its own, presented by\ncommit 54a0ed0df496 (\"net: dsa: provide an option for drivers to always\nreceive bridge VLANs\") for the DSA core, followed by\ncommit 1fb74191988f (\"net: dsa: mv88e6xxx: fix vlan setup\") which\napplied ds->configure_vlan_while_not_filtering = true for mv88e6xxx in\nparticular.\n\nWe still don't know what corner case Andrew saw when he wrote\ncommit 2ea7a679ca2a (\"net: dsa: Don't add vlans when vlan filtering is\ndisabled\"), but Tobias now reports that when we use TX forwarding\noffload, pinging an external station from the bridge device is broken if\nthe front-facing DSA user port has flooding turned off. The full\ndescription is in the link below, but for short, when a mv88e6xxx port\nis under a VLAN-unaware bridge, it inherits that bridge's pvid.\nSo packets ingressing a user port will be classified to e.g. VID 1\n(assuming that value for the bridge_default_pvid), whereas when\ntag_dsa.c xmits towards a user port, it always sends packets using a VID\nof 0 if that port is standalone or under a VLAN-unaware bridge - or at\nleast it did so prior to commit d82f8ab0d874 (\"net: dsa: tag_dsa:\noffload the bridge forwarding process\").\n\nIn any case, when there is a conversation between the CPU and a station\nconnected to a user port, the station's MAC address is learned in VID 1\nbut the CPU tries to transmit through VID 0. The packets reach the\nintended station, but via flooding and not by virtue of matching the\nexisting ATU entry.\n\nDSA has established (and enforced in other drivers: sja1105, felix,\nmt7530) that a VLAN-unaware port should use a private pvid, and not\ninherit the one from the bridge. The bridge's pvid should only be\ninherited when that bridge is VLAN-aware, so all state transitions need\nto be handled. On the other hand, all bridge VLANs should sit in the VTU\nstarting with the moment when the bridge offloads them via switchdev,\nthey are just not used.\n\nThis solves the problem that Tobias sees because packets ingressing on\nVLAN-unaware user ports now get classified to VID 0, which is also the\nVID used by tag_dsa.c on xmit.\n\nFixes: d82f8ab0d874 (\"net: dsa: tag_dsa: offload the bridge forwarding process\")\nLink: https://patchwork.kernel.org/project/netdevbpf/patch/20211003222312.284175-2-vladimir.oltean@nxp.com/#24491503\nReported-by: Tobias Waldekranz <tobias@waldekranz.com>\nSigned-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>\nSigned-off-by: Jakub Kicinski <kuba@kernel.org>\n---\n drivers/net/dsa/mv88e6xxx/chip.c | 56 +++++++++++++++++++++++++++++---\n drivers/net/dsa/mv88e6xxx/chip.h |  6 ++++\n drivers/net/dsa/mv88e6xxx/port.c | 21 ++++++++++++\n drivers/net/dsa/mv88e6xxx/port.h |  2 ++\n 4 files changed, 81 insertions(+), 4 deletions(-)\n\n--- a/drivers/net/dsa/mv88e6xxx/chip.c\n+++ b/drivers/net/dsa/mv88e6xxx/chip.c\n@@ -1586,6 +1586,26 @@ static int mv88e6xxx_port_check_hw_vlan(\n \treturn 0;\n }\n \n+static int mv88e6xxx_port_commit_pvid(struct mv88e6xxx_chip *chip, int port)\n+{\n+\tstruct dsa_port *dp = dsa_to_port(chip->ds, port);\n+\tstruct mv88e6xxx_port *p = &chip->ports[port];\n+\tbool drop_untagged = false;\n+\tu16 pvid = 0;\n+\tint err;\n+\n+\tif (dp->bridge_dev && br_vlan_enabled(dp->bridge_dev)) {\n+\t\tpvid = p->bridge_pvid.vid;\n+\t\tdrop_untagged = !p->bridge_pvid.valid;\n+\t}\n+\n+\terr = mv88e6xxx_port_set_pvid(chip, port, pvid);\n+\tif (err)\n+\t\treturn err;\n+\n+\treturn mv88e6xxx_port_drop_untagged(chip, port, drop_untagged);\n+}\n+\n static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,\n \t\t\t\t\t bool vlan_filtering,\n \t\t\t\t\t struct switchdev_trans *trans)\n@@ -1599,7 +1619,16 @@ static int mv88e6xxx_port_vlan_filtering\n \t\treturn chip->info->max_vid ? 0 : -EOPNOTSUPP;\n \n \tmv88e6xxx_reg_lock(chip);\n+\n \terr = mv88e6xxx_port_set_8021q_mode(chip, port, mode);\n+\tif (err)\n+\t\tgoto unlock;\n+\n+\terr = mv88e6xxx_port_commit_pvid(chip, port);\n+\tif (err)\n+\t\tgoto unlock;\n+\n+unlock:\n \tmv88e6xxx_reg_unlock(chip);\n \n \treturn err;\n@@ -1982,8 +2011,10 @@ static void mv88e6xxx_port_vlan_add(stru\n \tstruct mv88e6xxx_chip *chip = ds->priv;\n \tbool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;\n \tbool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;\n+\tstruct mv88e6xxx_port *p = &chip->ports[port];\n \tbool warn;\n \tu8 member;\n+\tint err;\n \tu16 vid;\n \n \tif (!chip->info->max_vid)\n@@ -2008,9 +2039,23 @@ static void mv88e6xxx_port_vlan_add(stru\n \t\t\tdev_err(ds->dev, \"p%d: failed to add VLAN %d%c\\n\", port,\n \t\t\t\tvid, untagged ? 'u' : 't');\n \n-\tif (pvid && mv88e6xxx_port_set_pvid(chip, port, vlan->vid_end))\n-\t\tdev_err(ds->dev, \"p%d: failed to set PVID %d\\n\", port,\n-\t\t\tvlan->vid_end);\n+\tif (pvid) {\n+\t\tp->bridge_pvid.vid = vlan->vid_end;\n+\t\tp->bridge_pvid.valid = true;\n+\n+\t\terr = mv88e6xxx_port_commit_pvid(chip, port);\n+\t\tif (err)\n+\t\t\tdev_err(ds->dev, \"p%d: failed to set PVID %d\", port,\n+\t\t\t\tvlan->vid_end);\n+\t} else if (vlan->vid_end && p->bridge_pvid.vid == vlan->vid_end) {\n+\t\t/* The old pvid was reinstalled as a non-pvid VLAN */\n+\t\tp->bridge_pvid.valid = false;\n+\n+\t\terr = mv88e6xxx_port_commit_pvid(chip, port);\n+\t\tif (err)\n+\t\t\tdev_err(ds->dev, \"p%d: failed to unset PVID %d\", port,\n+\t\t\t\tvlan->vid_end);\n+\t}\n \n \tmv88e6xxx_reg_unlock(chip);\n }\n@@ -2061,6 +2106,7 @@ static int mv88e6xxx_port_vlan_del(struc\n \t\t\t\t   const struct switchdev_obj_port_vlan *vlan)\n {\n \tstruct mv88e6xxx_chip *chip = ds->priv;\n+\tstruct mv88e6xxx_port *p = &chip->ports[port];\n \tu16 pvid, vid;\n \tint err = 0;\n \n@@ -2079,7 +2125,9 @@ static int mv88e6xxx_port_vlan_del(struc\n \t\t\tgoto unlock;\n \n \t\tif (vid == pvid) {\n-\t\t\terr = mv88e6xxx_port_set_pvid(chip, port, 0);\n+\t\t\tp->bridge_pvid.valid = false;\n+\n+\t\t\terr = mv88e6xxx_port_commit_pvid(chip, port);\n \t\t\tif (err)\n \t\t\t\tgoto unlock;\n \t\t}\n--- a/drivers/net/dsa/mv88e6xxx/chip.h\n+++ b/drivers/net/dsa/mv88e6xxx/chip.h\n@@ -224,9 +224,15 @@ struct mv88e6xxx_policy {\n \tu16 vid;\n };\n \n+struct mv88e6xxx_vlan {\n+\tu16\tvid;\n+\tbool\tvalid;\n+};\n+\n struct mv88e6xxx_port {\n \tstruct mv88e6xxx_chip *chip;\n \tint port;\n+\tstruct mv88e6xxx_vlan bridge_pvid;\n \tu64 serdes_stats[2];\n \tu64 atu_member_violation;\n \tu64 atu_miss_violation;\n--- a/drivers/net/dsa/mv88e6xxx/port.c\n+++ b/drivers/net/dsa/mv88e6xxx/port.c\n@@ -1062,6 +1062,27 @@ int mv88e6xxx_port_set_8021q_mode(struct\n \treturn 0;\n }\n \n+int mv88e6xxx_port_drop_untagged(struct mv88e6xxx_chip *chip, int port,\n+\t\t\t\t bool drop_untagged)\n+{\n+\tu16 old, new;\n+\tint err;\n+\n+\terr = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, &old);\n+\tif (err)\n+\t\treturn err;\n+\n+\tif (drop_untagged)\n+\t\tnew = old | MV88E6XXX_PORT_CTL2_DISCARD_UNTAGGED;\n+\telse\n+\t\tnew = old & ~MV88E6XXX_PORT_CTL2_DISCARD_UNTAGGED;\n+\n+\tif (new == old)\n+\t\treturn 0;\n+\n+\treturn mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, new);\n+}\n+\n int mv88e6xxx_port_set_map_da(struct mv88e6xxx_chip *chip, int port)\n {\n \tu16 reg;\n--- a/drivers/net/dsa/mv88e6xxx/port.h\n+++ b/drivers/net/dsa/mv88e6xxx/port.h\n@@ -364,6 +364,8 @@ int mv88e6390x_port_set_cmode(struct mv8\n \t\t\t      phy_interface_t mode);\n int mv88e6185_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode);\n int mv88e6352_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode);\n+int mv88e6xxx_port_drop_untagged(struct mv88e6xxx_chip *chip, int port,\n+\t\t\t\t bool drop_untagged);\n int mv88e6xxx_port_set_map_da(struct mv88e6xxx_chip *chip, int port);\n int mv88e6095_port_set_upstream_port(struct mv88e6xxx_chip *chip, int port,\n \t\t\t\t     int upstream_port);\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/780-v5.11-net-usb-r8152-Provide-missing-documentation-for-some.patch",
    "content": "From 586f04ce6a391419ca3cc9cef6b6f38570cede88 Mon Sep 17 00:00:00 2001\nFrom: Lee Jones <lee.jones@linaro.org>\nDate: Mon, 2 Nov 2020 11:45:04 +0000\nSubject: [PATCH] net: usb: r8152: Provide missing documentation for\n some struct members\n\ncommit 34e653efb602e0651867fb5ab14369b555a61dcd upstream.\n\nFixes the following W=1 kernel build warning(s):\n\n drivers/net/usb/r8152.c:934: warning: Function parameter or member 'blk_hdr' not described in 'fw_mac'\n drivers/net/usb/r8152.c:934: warning: Function parameter or member 'reserved' not described in 'fw_mac'\n drivers/net/usb/r8152.c:947: warning: Function parameter or member 'blk_hdr' not described in 'fw_phy_patch_key'\n drivers/net/usb/r8152.c:947: warning: Function parameter or member 'reserved' not described in 'fw_phy_patch_key'\n drivers/net/usb/r8152.c:986: warning: Function parameter or member 'blk_hdr' not described in 'fw_phy_nc'\n drivers/net/usb/r8152.c:986: warning: Function parameter or member 'mode_pre' not described in 'fw_phy_nc'\n drivers/net/usb/r8152.c:986: warning: Function parameter or member 'mode_post' not described in 'fw_phy_nc'\n drivers/net/usb/r8152.c:986: warning: Function parameter or member 'reserved' not described in 'fw_phy_nc'\n\nSigned-off-by: Lee Jones <lee.jones@linaro.org>\nAcked-by: Hayes Wang <hayeswang@realtek.com>\nLink: https://lore.kernel.org/r/20201102114512.1062724-23-lee.jones@linaro.org\nSigned-off-by: Jakub Kicinski <kuba@kernel.org>\n---\n drivers/net/usb/r8152.c | 6 ++++++\n 1 file changed, 6 insertions(+)\n\n--- a/drivers/net/usb/r8152.c\n+++ b/drivers/net/usb/r8152.c\n@@ -898,6 +898,7 @@ struct fw_header {\n  * struct fw_mac - a firmware block used by RTL_FW_PLA and RTL_FW_USB.\n  *\tThe layout of the firmware block is:\n  *\t<struct fw_mac> + <info> + <firmware data>.\n+ * @blk_hdr: firmware descriptor (type, length)\n  * @fw_offset: offset of the firmware binary data. The start address of\n  *\tthe data would be the address of struct fw_mac + @fw_offset.\n  * @fw_reg: the register to load the firmware. Depends on chip.\n@@ -911,6 +912,7 @@ struct fw_header {\n  * @bp_num: the break point number which needs to be set for this firmware.\n  *\tDepends on the firmware.\n  * @bp: break points. Depends on firmware.\n+ * @reserved: reserved space (unused)\n  * @fw_ver_reg: the register to store the fw version.\n  * @fw_ver_data: the firmware version of the current type.\n  * @info: additional information for debugging, and is followed by the\n@@ -936,8 +938,10 @@ struct fw_mac {\n /**\n  * struct fw_phy_patch_key - a firmware block used by RTL_FW_PHY_START.\n  *\tThis is used to set patch key when loading the firmware of PHY.\n+ * @blk_hdr: firmware descriptor (type, length)\n  * @key_reg: the register to write the patch key.\n  * @key_data: patch key.\n+ * @reserved: reserved space (unused)\n  */\n struct fw_phy_patch_key {\n \tstruct fw_block blk_hdr;\n@@ -950,6 +954,7 @@ struct fw_phy_patch_key {\n  * struct fw_phy_nc - a firmware block used by RTL_FW_PHY_NC.\n  *\tThe layout of the firmware block is:\n  *\t<struct fw_phy_nc> + <info> + <firmware data>.\n+ * @blk_hdr: firmware descriptor (type, length)\n  * @fw_offset: offset of the firmware binary data. The start address of\n  *\tthe data would be the address of struct fw_phy_nc + @fw_offset.\n  * @fw_reg: the register to load the firmware. Depends on chip.\n@@ -960,6 +965,7 @@ struct fw_phy_patch_key {\n  * @mode_reg: the regitster of switching the mode.\n  * @mod_pre: the mode needing to be set before loading the firmware.\n  * @mod_post: the mode to be set when finishing to load the firmware.\n+ * @reserved: reserved space (unused)\n  * @bp_start: the start register of break points. Depends on chip.\n  * @bp_num: the break point number which needs to be set for this firmware.\n  *\tDepends on the firmware.\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/781-v5.11-net-usb-r8152-Fix-a-couple-of-spelling-errors-in-fw_.patch",
    "content": "From 5fcfa846181de6676509696c4cd7b60a22e74077 Mon Sep 17 00:00:00 2001\nFrom: Lee Jones <lee.jones@linaro.org>\nDate: Mon, 2 Nov 2020 11:45:09 +0000\nSubject: [PATCH] net: usb: r8152: Fix a couple of spelling errors in\n fw_phy_nc's docs\n\ncommit 9f07814d01ad085b2d9f1d55b4ce532fb2c27110 upstream.\n\nFixes the following W=1 kernel build warning(s):\n\n drivers/net/usb/r8152.c:992: warning: Function parameter or member 'mode_pre' not described in 'fw_phy_nc'\n drivers/net/usb/r8152.c:992: warning: Function parameter or member 'mode_post' not described in 'fw_phy_nc'\n\nSigned-off-by: Lee Jones <lee.jones@linaro.org>\nAcked-by: Hayes Wang <hayeswang@realtek.com>\nLink: https://lore.kernel.org/r/20201102114512.1062724-28-lee.jones@linaro.org\nSigned-off-by: Jakub Kicinski <kuba@kernel.org>\n---\n drivers/net/usb/r8152.c | 4 ++--\n 1 file changed, 2 insertions(+), 2 deletions(-)\n\n--- a/drivers/net/usb/r8152.c\n+++ b/drivers/net/usb/r8152.c\n@@ -963,8 +963,8 @@ struct fw_phy_patch_key {\n  * @patch_en_addr: the register of enabling patch mode. Depends on chip.\n  * @patch_en_value: patch mode enabled mask. Depends on the firmware.\n  * @mode_reg: the regitster of switching the mode.\n- * @mod_pre: the mode needing to be set before loading the firmware.\n- * @mod_post: the mode to be set when finishing to load the firmware.\n+ * @mode_pre: the mode needing to be set before loading the firmware.\n+ * @mode_post: the mode to be set when finishing to load the firmware.\n  * @reserved: reserved space (unused)\n  * @bp_start: the start register of break points. Depends on chip.\n  * @bp_num: the break point number which needs to be set for this firmware.\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/782-v5.11-net-usb-r8153_ecm-support-ECM-mode-for-RTL8153.patch",
    "content": "From 0ef50460f7f053bd2a911ec53e01bfda646a5574 Mon Sep 17 00:00:00 2001\nFrom: Hayes Wang <hayeswang@realtek.com>\nDate: Wed, 4 Nov 2020 10:19:22 +0800\nSubject: [PATCH] net/usb/r8153_ecm: support ECM mode for RTL8153\n\ncommit c1aedf015ebdd0232757a66e2daccf1246bd609c upstream.\n\nSupport ECM mode based on cdc_ether with relative mii functions,\nwhen CONFIG_USB_RTL8152 is not set, or the device is not supported\nby r8152 driver.\n\nBoth r8152 and r8153_ecm would check the return value of\nrtl8152_get_version() in porbe(). If rtl8152_get_version()\nreturn none zero value, the r8152 is used for the device\nwith vendor mode. Otherwise, the r8153_ecm is used for the\ndevice with ECM mode.\n\nSigned-off-by: Hayes Wang <hayeswang@realtek.com>\nLink: https://lore.kernel.org/r/1394712342-15778-392-Taiwan-albertk@realtek.com\nSigned-off-by: Jakub Kicinski <kuba@kernel.org>\n---\n drivers/net/usb/Makefile    |   2 +-\n drivers/net/usb/r8152.c     |  30 +------\n drivers/net/usb/r8153_ecm.c | 162 ++++++++++++++++++++++++++++++++++++\n include/linux/usb/r8152.h   |  37 ++++++++\n 4 files changed, 204 insertions(+), 27 deletions(-)\n create mode 100644 drivers/net/usb/r8153_ecm.c\n create mode 100644 include/linux/usb/r8152.h\n\n--- a/drivers/net/usb/Makefile\n+++ b/drivers/net/usb/Makefile\n@@ -13,7 +13,7 @@ obj-$(CONFIG_USB_LAN78XX)\t+= lan78xx.o\n obj-$(CONFIG_USB_NET_AX8817X)\t+= asix.o\n asix-y := asix_devices.o asix_common.o ax88172a.o\n obj-$(CONFIG_USB_NET_AX88179_178A)      += ax88179_178a.o\n-obj-$(CONFIG_USB_NET_CDCETHER)\t+= cdc_ether.o\n+obj-$(CONFIG_USB_NET_CDCETHER)\t+= cdc_ether.o r8153_ecm.o\n obj-$(CONFIG_USB_NET_CDC_EEM)\t+= cdc_eem.o\n obj-$(CONFIG_USB_NET_DM9601)\t+= dm9601.o\n obj-$(CONFIG_USB_NET_SR9700)\t+= sr9700.o\n--- a/drivers/net/usb/r8152.c\n+++ b/drivers/net/usb/r8152.c\n@@ -26,6 +26,7 @@\n #include <linux/acpi.h>\n #include <linux/firmware.h>\n #include <crypto/hash.h>\n+#include <linux/usb/r8152.h>\n \n /* Information for net-next */\n #define NETNEXT_VERSION\t\t\"11\"\n@@ -653,18 +654,6 @@ enum rtl_register_content {\n \n #define INTR_LINK\t\t0x0004\n \n-#define RTL8152_REQT_READ\t0xc0\n-#define RTL8152_REQT_WRITE\t0x40\n-#define RTL8152_REQ_GET_REGS\t0x05\n-#define RTL8152_REQ_SET_REGS\t0x05\n-\n-#define BYTE_EN_DWORD\t\t0xff\n-#define BYTE_EN_WORD\t\t0x33\n-#define BYTE_EN_BYTE\t\t0x11\n-#define BYTE_EN_SIX_BYTES\t0x3f\n-#define BYTE_EN_START_MASK\t0x0f\n-#define BYTE_EN_END_MASK\t0xf0\n-\n #define RTL8153_MAX_PACKET\t9216 /* 9K */\n #define RTL8153_MAX_MTU\t\t(RTL8153_MAX_PACKET - VLAN_ETH_HLEN - \\\n \t\t\t\t ETH_FCS_LEN)\n@@ -689,21 +678,9 @@ enum rtl8152_flags {\n \tLENOVO_MACPASSTHRU,\n };\n \n-/* Define these values to match your device */\n-#define VENDOR_ID_REALTEK\t\t0x0bda\n-#define VENDOR_ID_MICROSOFT\t\t0x045e\n-#define VENDOR_ID_SAMSUNG\t\t0x04e8\n-#define VENDOR_ID_LENOVO\t\t0x17ef\n-#define VENDOR_ID_LINKSYS\t\t0x13b1\n-#define VENDOR_ID_NVIDIA\t\t0x0955\n-#define VENDOR_ID_TPLINK\t\t0x2357\n-\n #define DEVICE_ID_THINKPAD_THUNDERBOLT3_DOCK_GEN2\t0x3082\n #define DEVICE_ID_THINKPAD_USB_C_DOCK_GEN2\t\t0xa387\n \n-#define MCU_TYPE_PLA\t\t\t0x0100\n-#define MCU_TYPE_USB\t\t\t0x0000\n-\n struct tally_counter {\n \t__le64\ttx_packets;\n \t__le64\trx_packets;\n@@ -6602,7 +6579,7 @@ static int rtl_fw_init(struct r8152 *tp)\n \treturn 0;\n }\n \n-static u8 rtl_get_version(struct usb_interface *intf)\n+u8 rtl8152_get_version(struct usb_interface *intf)\n {\n \tstruct usb_device *udev = interface_to_usbdev(intf);\n \tu32 ocp_data = 0;\n@@ -6660,12 +6637,13 @@ static u8 rtl_get_version(struct usb_int\n \n \treturn version;\n }\n+EXPORT_SYMBOL_GPL(rtl8152_get_version);\n \n static int rtl8152_probe(struct usb_interface *intf,\n \t\t\t const struct usb_device_id *id)\n {\n \tstruct usb_device *udev = interface_to_usbdev(intf);\n-\tu8 version = rtl_get_version(intf);\n+\tu8 version = rtl8152_get_version(intf);\n \tstruct r8152 *tp;\n \tstruct net_device *netdev;\n \tint ret;\n--- /dev/null\n+++ b/drivers/net/usb/r8153_ecm.c\n@@ -0,0 +1,162 @@\n+// SPDX-License-Identifier: GPL-2.0-or-later\n+#include <linux/module.h>\n+#include <linux/netdevice.h>\n+#include <linux/mii.h>\n+#include <linux/usb.h>\n+#include <linux/usb/cdc.h>\n+#include <linux/usb/usbnet.h>\n+#include <linux/usb/r8152.h>\n+\n+#define OCP_BASE\t\t0xe86c\n+\n+static int pla_read_word(struct usbnet *dev, u16 index)\n+{\n+\tu16 byen = BYTE_EN_WORD;\n+\tu8 shift = index & 2;\n+\t__le32 tmp;\n+\tint ret;\n+\n+\tif (shift)\n+\t\tbyen <<= shift;\n+\n+\tindex &= ~3;\n+\n+\tret = usbnet_read_cmd(dev, RTL8152_REQ_GET_REGS, RTL8152_REQT_READ, index,\n+\t\t\t      MCU_TYPE_PLA | byen, &tmp, sizeof(tmp));\n+\tif (ret < 0)\n+\t\tgoto out;\n+\n+\tret = __le32_to_cpu(tmp);\n+\tret >>= (shift * 8);\n+\tret &= 0xffff;\n+\n+out:\n+\treturn ret;\n+}\n+\n+static int pla_write_word(struct usbnet *dev, u16 index, u32 data)\n+{\n+\tu32 mask = 0xffff;\n+\tu16 byen = BYTE_EN_WORD;\n+\tu8 shift = index & 2;\n+\t__le32 tmp;\n+\tint ret;\n+\n+\tdata &= mask;\n+\n+\tif (shift) {\n+\t\tbyen <<= shift;\n+\t\tmask <<= (shift * 8);\n+\t\tdata <<= (shift * 8);\n+\t}\n+\n+\tindex &= ~3;\n+\n+\tret = usbnet_read_cmd(dev, RTL8152_REQ_GET_REGS, RTL8152_REQT_READ, index,\n+\t\t\t      MCU_TYPE_PLA | byen, &tmp, sizeof(tmp));\n+\n+\tif (ret < 0)\n+\t\tgoto out;\n+\n+\tdata |= __le32_to_cpu(tmp) & ~mask;\n+\ttmp = __cpu_to_le32(data);\n+\n+\tret = usbnet_write_cmd(dev, RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE, index,\n+\t\t\t       MCU_TYPE_PLA | byen, &tmp, sizeof(tmp));\n+\n+out:\n+\treturn ret;\n+}\n+\n+static int r8153_ecm_mdio_read(struct net_device *netdev, int phy_id, int reg)\n+{\n+\tstruct usbnet *dev = netdev_priv(netdev);\n+\tint ret;\n+\n+\tret = pla_write_word(dev, OCP_BASE, 0xa000);\n+\tif (ret < 0)\n+\t\tgoto out;\n+\n+\tret = pla_read_word(dev, 0xb400 + reg * 2);\n+\n+out:\n+\treturn ret;\n+}\n+\n+static void r8153_ecm_mdio_write(struct net_device *netdev, int phy_id, int reg, int val)\n+{\n+\tstruct usbnet *dev = netdev_priv(netdev);\n+\tint ret;\n+\n+\tret = pla_write_word(dev, OCP_BASE, 0xa000);\n+\tif (ret < 0)\n+\t\treturn;\n+\n+\tret = pla_write_word(dev, 0xb400 + reg * 2, val);\n+}\n+\n+static int r8153_bind(struct usbnet *dev, struct usb_interface *intf)\n+{\n+\tint status;\n+\n+\tstatus = usbnet_cdc_bind(dev, intf);\n+\tif (status < 0)\n+\t\treturn status;\n+\n+\tdev->mii.dev = dev->net;\n+\tdev->mii.mdio_read = r8153_ecm_mdio_read;\n+\tdev->mii.mdio_write = r8153_ecm_mdio_write;\n+\tdev->mii.reg_num_mask = 0x1f;\n+\tdev->mii.supports_gmii = 1;\n+\n+\treturn status;\n+}\n+\n+static const struct driver_info r8153_info = {\n+\t.description =\t\"RTL8153 ECM Device\",\n+\t.flags =\tFLAG_ETHER,\n+\t.bind =\t\tr8153_bind,\n+\t.unbind =\tusbnet_cdc_unbind,\n+\t.status =\tusbnet_cdc_status,\n+\t.manage_power =\tusbnet_manage_power,\n+};\n+\n+static const struct usb_device_id products[] = {\n+{\n+\tUSB_DEVICE_AND_INTERFACE_INFO(VENDOR_ID_REALTEK, 0x8153, USB_CLASS_COMM,\n+\t\t\t\t      USB_CDC_SUBCLASS_ETHERNET, USB_CDC_PROTO_NONE),\n+\t.driver_info = (unsigned long)&r8153_info,\n+},\n+\n+\t{ },\t\t/* END */\n+};\n+MODULE_DEVICE_TABLE(usb, products);\n+\n+static int rtl8153_ecm_probe(struct usb_interface *intf,\n+\t\t\t     const struct usb_device_id *id)\n+{\n+#if IS_REACHABLE(CONFIG_USB_RTL8152)\n+\tif (rtl8152_get_version(intf))\n+\t\treturn -ENODEV;\n+#endif\n+\n+\treturn usbnet_probe(intf, id);\n+}\n+\n+static struct usb_driver r8153_ecm_driver = {\n+\t.name =\t\t\"r8153_ecm\",\n+\t.id_table =\tproducts,\n+\t.probe =\trtl8153_ecm_probe,\n+\t.disconnect =\tusbnet_disconnect,\n+\t.suspend =\tusbnet_suspend,\n+\t.resume =\tusbnet_resume,\n+\t.reset_resume =\tusbnet_resume,\n+\t.supports_autosuspend = 1,\n+\t.disable_hub_initiated_lpm = 1,\n+};\n+\n+module_usb_driver(r8153_ecm_driver);\n+\n+MODULE_AUTHOR(\"Hayes Wang\");\n+MODULE_DESCRIPTION(\"Realtek USB ECM device\");\n+MODULE_LICENSE(\"GPL\");\n--- /dev/null\n+++ b/include/linux/usb/r8152.h\n@@ -0,0 +1,37 @@\n+/* SPDX-License-Identifier: GPL-2.0-only */\n+/*\n+ *  Copyright (c) 2020 Realtek Semiconductor Corp. All rights reserved.\n+ */\n+\n+#ifndef\t__LINUX_R8152_H\n+#define __LINUX_R8152_H\n+\n+#define RTL8152_REQT_READ\t\t0xc0\n+#define RTL8152_REQT_WRITE\t\t0x40\n+#define RTL8152_REQ_GET_REGS\t\t0x05\n+#define RTL8152_REQ_SET_REGS\t\t0x05\n+\n+#define BYTE_EN_DWORD\t\t\t0xff\n+#define BYTE_EN_WORD\t\t\t0x33\n+#define BYTE_EN_BYTE\t\t\t0x11\n+#define BYTE_EN_SIX_BYTES\t\t0x3f\n+#define BYTE_EN_START_MASK\t\t0x0f\n+#define BYTE_EN_END_MASK\t\t0xf0\n+\n+#define MCU_TYPE_PLA\t\t\t0x0100\n+#define MCU_TYPE_USB\t\t\t0x0000\n+\n+/* Define these values to match your device */\n+#define VENDOR_ID_REALTEK\t\t0x0bda\n+#define VENDOR_ID_MICROSOFT\t\t0x045e\n+#define VENDOR_ID_SAMSUNG\t\t0x04e8\n+#define VENDOR_ID_LENOVO\t\t0x17ef\n+#define VENDOR_ID_LINKSYS\t\t0x13b1\n+#define VENDOR_ID_NVIDIA\t\t0x0955\n+#define VENDOR_ID_TPLINK\t\t0x2357\n+\n+#if IS_REACHABLE(CONFIG_USB_RTL8152)\n+extern u8 rtl8152_get_version(struct usb_interface *intf);\n+#endif\n+\n+#endif /* __LINUX_R8152_H */\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/783-v5.12-net-usb-r8152-use-new-tasklet-API.patch",
    "content": "From 90f1afc7f96c8f7cf19c82e5f4b39e61a63b053d Mon Sep 17 00:00:00 2001\nFrom: Emil Renner Berthing <kernel@esmil.dk>\nDate: Sun, 31 Jan 2021 00:47:29 +0100\nSubject: [PATCH] net: usb: r8152: use new tasklet API\n\ncommit f3163f1cb87141c7a41a15a5d4c98b353f807b04 upstream.\n\nThis converts the driver to use the new tasklet API introduced in\ncommit 12cc923f1ccc (\"tasklet: Introduce new initialization API\")\n\nSigned-off-by: Emil Renner Berthing <kernel@esmil.dk>\nSigned-off-by: Jakub Kicinski <kuba@kernel.org>\n---\n drivers/net/usb/r8152.c | 8 +++-----\n 1 file changed, 3 insertions(+), 5 deletions(-)\n\n--- a/drivers/net/usb/r8152.c\n+++ b/drivers/net/usb/r8152.c\n@@ -2393,11 +2393,9 @@ static void tx_bottom(struct r8152 *tp)\n \t} while (res == 0);\n }\n \n-static void bottom_half(unsigned long data)\n+static void bottom_half(struct tasklet_struct *t)\n {\n-\tstruct r8152 *tp;\n-\n-\ttp = (struct r8152 *)data;\n+\tstruct r8152 *tp = from_tasklet(tp, t, tx_tl);\n \n \tif (test_bit(RTL8152_UNPLUG, &tp->flags))\n \t\treturn;\n@@ -6695,7 +6693,7 @@ static int rtl8152_probe(struct usb_inte\n \tmutex_init(&tp->control);\n \tINIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t);\n \tINIT_DELAYED_WORK(&tp->hw_phy_work, rtl_hw_phy_work_func_t);\n-\ttasklet_init(&tp->tx_tl, bottom_half, (unsigned long)tp);\n+\ttasklet_setup(&tp->tx_tl, bottom_half);\n \ttasklet_disable(&tp->tx_tl);\n \n \tnetdev->netdev_ops = &rtl8152_netdev_ops;\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/784-v5.12-r8152-replace-several-functions-about-phy-patch-requ.patch",
    "content": "From 86b98abf4f8c691c260c5113d6a2d32f5377caca Mon Sep 17 00:00:00 2001\nFrom: Hayes Wang <hayeswang@realtek.com>\nDate: Wed, 3 Feb 2021 17:14:28 +0800\nSubject: [PATCH] r8152: replace several functions about phy patch\n request\n\ncommit a08c0d309d8c078d22717d815cf9853f6f2c07bd upstream.\n\nReplace r8153_patch_request() with rtl_phy_patch_request().\nReplace r8153_pre_ram_code() with rtl_pre_ram_code().\nReplace r8153_post_ram_code() with rtl_post_ram_code().\nAdd rtl_patch_key_set().\n\nThe new functions have an additional parameter. It is used to wait\nthe patch request command finished. When the PHY is resumed from\nthe state of power cut, the PHY is at a safe mode and the\nOCP_PHY_PATCH_STAT wouldn't be updated. For this situation, it is\nsafe to set patch request command without waiting OCP_PHY_PATCH_STAT.\n\nSigned-off-by: Hayes Wang <hayeswang@realtek.com>\nSigned-off-by: Jakub Kicinski <kuba@kernel.org>\n---\n drivers/net/usb/r8152.c | 84 ++++++++++++++++++++++++-----------------\n 1 file changed, 50 insertions(+), 34 deletions(-)\n\n--- a/drivers/net/usb/r8152.c\n+++ b/drivers/net/usb/r8152.c\n@@ -3443,59 +3443,76 @@ static void rtl_clear_bp(struct r8152 *t\n \tocp_write_word(tp, type, PLA_BP_BA, 0);\n }\n \n-static int r8153_patch_request(struct r8152 *tp, bool request)\n+static int rtl_phy_patch_request(struct r8152 *tp, bool request, bool wait)\n {\n-\tu16 data;\n+\tu16 data, check;\n \tint i;\n \n \tdata = ocp_reg_read(tp, OCP_PHY_PATCH_CMD);\n-\tif (request)\n+\tif (request) {\n \t\tdata |= PATCH_REQUEST;\n-\telse\n+\t\tcheck = 0;\n+\t} else {\n \t\tdata &= ~PATCH_REQUEST;\n+\t\tcheck = PATCH_READY;\n+\t}\n \tocp_reg_write(tp, OCP_PHY_PATCH_CMD, data);\n \n-\tfor (i = 0; request && i < 5000; i++) {\n+\tfor (i = 0; wait && i < 5000; i++) {\n+\t\tu32 ocp_data;\n+\n \t\tusleep_range(1000, 2000);\n-\t\tif (ocp_reg_read(tp, OCP_PHY_PATCH_STAT) & PATCH_READY)\n+\t\tocp_data = ocp_reg_read(tp, OCP_PHY_PATCH_STAT);\n+\t\tif ((ocp_data & PATCH_READY) ^ check)\n \t\t\tbreak;\n \t}\n \n-\tif (request && !(ocp_reg_read(tp, OCP_PHY_PATCH_STAT) & PATCH_READY)) {\n-\t\tnetif_err(tp, drv, tp->netdev, \"patch request fail\\n\");\n-\t\tr8153_patch_request(tp, false);\n+\tif (request && wait &&\n+\t    !(ocp_reg_read(tp, OCP_PHY_PATCH_STAT) & PATCH_READY)) {\n+\t\tdev_err(&tp->intf->dev, \"PHY patch request fail\\n\");\n+\t\trtl_phy_patch_request(tp, false, false);\n \t\treturn -ETIME;\n \t} else {\n \t\treturn 0;\n \t}\n }\n \n-static int r8153_pre_ram_code(struct r8152 *tp, u16 key_addr, u16 patch_key)\n+static void rtl_patch_key_set(struct r8152 *tp, u16 key_addr, u16 patch_key)\n {\n-\tif (r8153_patch_request(tp, true)) {\n-\t\tdev_err(&tp->intf->dev, \"patch request fail\\n\");\n-\t\treturn -ETIME;\n-\t}\n+\tif (patch_key && key_addr) {\n+\t\tsram_write(tp, key_addr, patch_key);\n+\t\tsram_write(tp, SRAM_PHY_LOCK, PHY_PATCH_LOCK);\n+\t} else if (key_addr) {\n+\t\tu16 data;\n \n-\tsram_write(tp, key_addr, patch_key);\n-\tsram_write(tp, SRAM_PHY_LOCK, PHY_PATCH_LOCK);\n+\t\tsram_write(tp, 0x0000, 0x0000);\n \n-\treturn 0;\n+\t\tdata = ocp_reg_read(tp, OCP_PHY_LOCK);\n+\t\tdata &= ~PATCH_LOCK;\n+\t\tocp_reg_write(tp, OCP_PHY_LOCK, data);\n+\n+\t\tsram_write(tp, key_addr, 0x0000);\n+\t} else {\n+\t\tWARN_ON_ONCE(1);\n+\t}\n }\n \n-static int r8153_post_ram_code(struct r8152 *tp, u16 key_addr)\n+static int\n+rtl_pre_ram_code(struct r8152 *tp, u16 key_addr, u16 patch_key, bool wait)\n {\n-\tu16 data;\n+\tif (rtl_phy_patch_request(tp, true, wait))\n+\t\treturn -ETIME;\n \n-\tsram_write(tp, 0x0000, 0x0000);\n+\trtl_patch_key_set(tp, key_addr, patch_key);\n \n-\tdata = ocp_reg_read(tp, OCP_PHY_LOCK);\n-\tdata &= ~PATCH_LOCK;\n-\tocp_reg_write(tp, OCP_PHY_LOCK, data);\n+\treturn 0;\n+}\n \n-\tsram_write(tp, key_addr, 0x0000);\n+static int rtl_post_ram_code(struct r8152 *tp, u16 key_addr, bool wait)\n+{\n+\trtl_patch_key_set(tp, key_addr, 0);\n \n-\tr8153_patch_request(tp, false);\n+\trtl_phy_patch_request(tp, false, wait);\n \n \tocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, tp->ocp_base);\n \n@@ -3980,7 +3997,7 @@ static void rtl8152_fw_mac_apply(struct\n \tdev_dbg(&tp->intf->dev, \"successfully applied %s\\n\", mac->info);\n }\n \n-static void rtl8152_apply_firmware(struct r8152 *tp)\n+static void rtl8152_apply_firmware(struct r8152 *tp, bool power_cut)\n {\n \tstruct rtl_fw *rtl_fw = &tp->rtl_fw;\n \tconst struct firmware *fw;\n@@ -4011,12 +4028,11 @@ static void rtl8152_apply_firmware(struc\n \t\tcase RTL_FW_PHY_START:\n \t\t\tkey = (struct fw_phy_patch_key *)block;\n \t\t\tkey_addr = __le16_to_cpu(key->key_reg);\n-\t\t\tr8153_pre_ram_code(tp, key_addr,\n-\t\t\t\t\t   __le16_to_cpu(key->key_data));\n+\t\t\trtl_pre_ram_code(tp, key_addr, __le16_to_cpu(key->key_data), !power_cut);\n \t\t\tbreak;\n \t\tcase RTL_FW_PHY_STOP:\n \t\t\tWARN_ON(!key_addr);\n-\t\t\tr8153_post_ram_code(tp, key_addr);\n+\t\t\trtl_post_ram_code(tp, key_addr, !power_cut);\n \t\t\tbreak;\n \t\tcase RTL_FW_PHY_NC:\n \t\t\trtl8152_fw_phy_nc_apply(tp, (struct fw_phy_nc *)block);\n@@ -4221,7 +4237,7 @@ static void rtl8152_disable(struct r8152\n \n static void r8152b_hw_phy_cfg(struct r8152 *tp)\n {\n-\trtl8152_apply_firmware(tp);\n+\trtl8152_apply_firmware(tp, false);\n \trtl_eee_enable(tp, tp->eee_en);\n \tr8152_aldps_en(tp, true);\n \tr8152b_enable_fc(tp);\n@@ -4503,7 +4519,7 @@ static void r8153_hw_phy_cfg(struct r815\n \t/* disable EEE before updating the PHY parameters */\n \trtl_eee_enable(tp, false);\n \n-\trtl8152_apply_firmware(tp);\n+\trtl8152_apply_firmware(tp, false);\n \n \tif (tp->version == RTL_VER_03) {\n \t\tdata = ocp_reg_read(tp, OCP_EEE_CFG);\n@@ -4577,7 +4593,7 @@ static void r8153b_hw_phy_cfg(struct r81\n \t/* disable EEE before updating the PHY parameters */\n \trtl_eee_enable(tp, false);\n \n-\trtl8152_apply_firmware(tp);\n+\trtl8152_apply_firmware(tp, false);\n \n \tr8153b_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags));\n \n@@ -4618,7 +4634,7 @@ static void r8153b_hw_phy_cfg(struct r81\n \tocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);\n \n \t/* Advnace EEE */\n-\tif (!r8153_patch_request(tp, true)) {\n+\tif (!rtl_phy_patch_request(tp, true, true)) {\n \t\tdata = ocp_reg_read(tp, OCP_POWER_CFG);\n \t\tdata |= EEE_CLKDIV_EN;\n \t\tocp_reg_write(tp, OCP_POWER_CFG, data);\n@@ -4635,7 +4651,7 @@ static void r8153b_hw_phy_cfg(struct r81\n \t\tocp_reg_write(tp, OCP_SYSCLK_CFG, clk_div_expo(5));\n \t\ttp->ups_info._250m_ckdiv = true;\n \n-\t\tr8153_patch_request(tp, false);\n+\t\trtl_phy_patch_request(tp, false, true);\n \t}\n \n \tif (tp->eee_en)\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/785-v5.12-r8152-adjust-the-flow-of-power-cut-for-RTL8153B.patch",
    "content": "From 29a61d8564ad3439d03c7ec135016a4e70072af1 Mon Sep 17 00:00:00 2001\nFrom: Hayes Wang <hayeswang@realtek.com>\nDate: Wed, 3 Feb 2021 17:14:29 +0800\nSubject: [PATCH] r8152: adjust the flow of power cut for RTL8153B\n\ncommit 80fd850b31f09263ad175b2f640d5c5c6f76ed41 upstream.\n\nFor runtime resuming, the RTL8153B may be resumed from the state\nof power cut, when enabling the feature of UPS. Then, the PHY\nwould be reset, so it is necessary to be initailized again.\n\nBesides, the USB_U1U2_TIMER also has to be set again, so I move\nit from r8153b_init() to r8153b_hw_phy_cfg().\n\nSigned-off-by: Hayes Wang <hayeswang@realtek.com>\nSigned-off-by: Jakub Kicinski <kuba@kernel.org>\n---\n drivers/net/usb/r8152.c | 68 ++++++++++++++++++++++++-----------------\n 1 file changed, 40 insertions(+), 28 deletions(-)\n\n--- a/drivers/net/usb/r8152.c\n+++ b/drivers/net/usb/r8152.c\n@@ -1371,6 +1371,10 @@ void write_mii_word(struct net_device *n\n static int\n r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags);\n \n+static int\n+rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u32 speed, u8 duplex,\n+\t\t  u32 advertising);\n+\n static int rtl8152_set_mac_address(struct net_device *netdev, void *p)\n {\n \tstruct r8152 *tp = netdev_priv(netdev);\n@@ -3182,8 +3186,6 @@ static void r8153b_ups_en(struct r8152 *\n \t\tocp_data |= BIT(0);\n \t\tocp_write_byte(tp, MCU_TYPE_USB, 0xcfff, ocp_data);\n \t} else {\n-\t\tu16 data;\n-\n \t\tocp_data &= ~(UPS_EN | USP_PREWAKE);\n \t\tocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);\n \n@@ -3191,31 +3193,20 @@ static void r8153b_ups_en(struct r8152 *\n \t\tocp_data &= ~BIT(0);\n \t\tocp_write_byte(tp, MCU_TYPE_USB, 0xcfff, ocp_data);\n \n-\t\tocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);\n-\t\tocp_data &= ~PCUT_STATUS;\n-\t\tocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);\n+\t\tif (ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0) & PCUT_STATUS) {\n+\t\t\tint i;\n \n-\t\tdata = r8153_phy_status(tp, 0);\n+\t\t\tfor (i = 0; i < 500; i++) {\n+\t\t\t\tif (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &\n+\t\t\t\t    AUTOLOAD_DONE)\n+\t\t\t\t\tbreak;\n+\t\t\t\tmsleep(20);\n+\t\t\t}\n \n-\t\tswitch (data) {\n-\t\tcase PHY_STAT_PWRDN:\n-\t\tcase PHY_STAT_EXT_INIT:\n-\t\t\tr8153b_green_en(tp,\n-\t\t\t\t\ttest_bit(GREEN_ETHERNET, &tp->flags));\n-\n-\t\t\tdata = r8152_mdio_read(tp, MII_BMCR);\n-\t\t\tdata &= ~BMCR_PDOWN;\n-\t\t\tdata |= BMCR_RESET;\n-\t\t\tr8152_mdio_write(tp, MII_BMCR, data);\n+\t\t\ttp->rtl_ops.hw_phy_cfg(tp);\n \n-\t\t\tdata = r8153_phy_status(tp, PHY_STAT_LAN_ON);\n-\t\t\tfallthrough;\n-\n-\t\tdefault:\n-\t\t\tif (data != PHY_STAT_LAN_ON)\n-\t\t\t\tnetif_warn(tp, link, tp->netdev,\n-\t\t\t\t\t   \"PHY not ready\");\n-\t\t\tbreak;\n+\t\t\trtl8152_set_speed(tp, tp->autoneg, tp->speed,\n+\t\t\t\t\t  tp->duplex, tp->advertising);\n \t\t}\n \t}\n }\n@@ -4587,13 +4578,37 @@ static void r8153b_hw_phy_cfg(struct r81\n \tu32 ocp_data;\n \tu16 data;\n \n+\tocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);\n+\tif (ocp_data & PCUT_STATUS) {\n+\t\tocp_data &= ~PCUT_STATUS;\n+\t\tocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);\n+\t}\n+\n \t/* disable ALDPS before updating the PHY parameters */\n \tr8153_aldps_en(tp, false);\n \n \t/* disable EEE before updating the PHY parameters */\n \trtl_eee_enable(tp, false);\n \n-\trtl8152_apply_firmware(tp, false);\n+\t/* U1/U2/L1 idle timer. 500 us */\n+\tocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500);\n+\n+\tdata = r8153_phy_status(tp, 0);\n+\n+\tswitch (data) {\n+\tcase PHY_STAT_PWRDN:\n+\tcase PHY_STAT_EXT_INIT:\n+\t\trtl8152_apply_firmware(tp, true);\n+\n+\t\tdata = r8152_mdio_read(tp, MII_BMCR);\n+\t\tdata &= ~BMCR_PDOWN;\n+\t\tr8152_mdio_write(tp, MII_BMCR, data);\n+\t\tbreak;\n+\tcase PHY_STAT_LAN_ON:\n+\tdefault:\n+\t\trtl8152_apply_firmware(tp, false);\n+\t\tbreak;\n+\t}\n \n \tr8153b_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags));\n \n@@ -5522,9 +5537,6 @@ static void r8153b_init(struct r8152 *tp\n \t/* MSC timer = 0xfff * 8ms = 32760 ms */\n \tocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff);\n \n-\t/* U1/U2/L1 idle timer. 500 us */\n-\tocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500);\n-\n \tr8153b_power_cut_en(tp, false);\n \tr8153b_ups_en(tp, false);\n \tr8153_queue_wake(tp, false);\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/786-v5.12-r8152-enable-U1-U2-for-USB_SPEED_SUPER.patch",
    "content": "From 69b4339c0b9f3edc6a8f681f05efaaf4add1bb0e Mon Sep 17 00:00:00 2001\nFrom: Hayes Wang <hayeswang@realtek.com>\nDate: Fri, 19 Feb 2021 17:04:40 +0800\nSubject: [PATCH] r8152: enable U1/U2 for USB_SPEED_SUPER\n\ncommit 7a0ae61acde2cebd69665837170405eced86a6c7 upstream.\n\nU1/U2 shoued be enabled for USB 3.0 or later. The USB 2.0 doesn't\nsupport it.\n\nSigned-off-by: Hayes Wang <hayeswang@realtek.com>\nSigned-off-by: Jakub Kicinski <kuba@kernel.org>\n---\n drivers/net/usb/r8152.c | 7 ++++---\n 1 file changed, 4 insertions(+), 3 deletions(-)\n\n--- a/drivers/net/usb/r8152.c\n+++ b/drivers/net/usb/r8152.c\n@@ -3335,7 +3335,7 @@ static void rtl8153b_runtime_enable(stru\n \t\tr8153b_ups_en(tp, false);\n \t\tr8153_queue_wake(tp, false);\n \t\trtl_runtime_suspend_enable(tp, false);\n-\t\tif (tp->udev->speed != USB_SPEED_HIGH)\n+\t\tif (tp->udev->speed >= USB_SPEED_SUPER)\n \t\t\tr8153b_u1u2en(tp, true);\n \t}\n }\n@@ -5028,7 +5028,7 @@ static void rtl8153b_up(struct r8152 *tp\n \n \tr8153_aldps_en(tp, true);\n \n-\tif (tp->udev->speed != USB_SPEED_HIGH)\n+\tif (tp->udev->speed >= USB_SPEED_SUPER)\n \t\tr8153b_u1u2en(tp, true);\n }\n \n@@ -5550,8 +5550,9 @@ static void r8153b_init(struct r8152 *tp\n \tocp_data |= POLL_LINK_CHG;\n \tocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);\n \n-\tif (tp->udev->speed != USB_SPEED_HIGH)\n+\tif (tp->udev->speed >= USB_SPEED_SUPER)\n \t\tr8153b_u1u2en(tp, true);\n+\n \tusb_enable_lpm(tp->udev);\n \n \t/* MAC clock speed down */\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/787-v5.12-r8152-check-if-the-pointer-of-the-function-exists.patch",
    "content": "From e78b75f5be204a0a235da995d01c778dc282bb42 Mon Sep 17 00:00:00 2001\nFrom: Hayes Wang <hayeswang@realtek.com>\nDate: Fri, 19 Feb 2021 17:04:41 +0800\nSubject: [PATCH] r8152: check if the pointer of the function exists\n\ncommit c79515e47935c747282c6ed2ee5b2ef039756eeb upstream.\n\nReturn error code if autosuspend_en, eee_get, or eee_set don't exist.\n\nSigned-off-by: Hayes Wang <hayeswang@realtek.com>\nSigned-off-by: Jakub Kicinski <kuba@kernel.org>\n---\n drivers/net/usb/r8152.c | 13 +++++++++++++\n 1 file changed, 13 insertions(+)\n\n--- a/drivers/net/usb/r8152.c\n+++ b/drivers/net/usb/r8152.c\n@@ -5735,6 +5735,9 @@ static int rtl8152_runtime_suspend(struc\n \tstruct net_device *netdev = tp->netdev;\n \tint ret = 0;\n \n+\tif (!tp->rtl_ops.autosuspend_en)\n+\t\treturn -EBUSY;\n+\n \tset_bit(SELECTIVE_SUSPEND, &tp->flags);\n \tsmp_mb__after_atomic();\n \n@@ -6134,6 +6137,11 @@ rtl_ethtool_get_eee(struct net_device *n\n \tstruct r8152 *tp = netdev_priv(net);\n \tint ret;\n \n+\tif (!tp->rtl_ops.eee_get) {\n+\t\tret = -EOPNOTSUPP;\n+\t\tgoto out;\n+\t}\n+\n \tret = usb_autopm_get_interface(tp->intf);\n \tif (ret < 0)\n \t\tgoto out;\n@@ -6156,6 +6164,11 @@ rtl_ethtool_set_eee(struct net_device *n\n \tstruct r8152 *tp = netdev_priv(net);\n \tint ret;\n \n+\tif (!tp->rtl_ops.eee_set) {\n+\t\tret = -EOPNOTSUPP;\n+\t\tgoto out;\n+\t}\n+\n \tret = usb_autopm_get_interface(tp->intf);\n \tif (ret < 0)\n \t\tgoto out;\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/788-v5.12-r8152-replace-netif_err-with-dev_err.patch",
    "content": "From 38e44c7926512cff0b2809dc329de2a8e769e523 Mon Sep 17 00:00:00 2001\nFrom: Hayes Wang <hayeswang@realtek.com>\nDate: Fri, 19 Feb 2021 17:04:42 +0800\nSubject: [PATCH] r8152: replace netif_err with dev_err\n\ncommit 156c3207611262266f0eea589ac3f00c5657320e upstream.\n\nSome messages are before calling register_netdev(), so replace\nnetif_err() with dev_err().\n\nSigned-off-by: Hayes Wang <hayeswang@realtek.com>\nSigned-off-by: Jakub Kicinski <kuba@kernel.org>\n---\n drivers/net/usb/r8152.c | 4 ++--\n 1 file changed, 2 insertions(+), 2 deletions(-)\n\n--- a/drivers/net/usb/r8152.c\n+++ b/drivers/net/usb/r8152.c\n@@ -6571,7 +6571,7 @@ static int rtl_ops_init(struct r8152 *tp\n \n \tdefault:\n \t\tret = -ENODEV;\n-\t\tnetif_err(tp, probe, tp->netdev, \"Unknown Device\\n\");\n+\t\tdev_err(&tp->intf->dev, \"Unknown Device\\n\");\n \t\tbreak;\n \t}\n \n@@ -6828,7 +6828,7 @@ static int rtl8152_probe(struct usb_inte\n \n \tret = register_netdev(netdev);\n \tif (ret != 0) {\n-\t\tnetif_err(tp, probe, netdev, \"couldn't register the device\\n\");\n+\t\tdev_err(&intf->dev, \"couldn't register the device\\n\");\n \t\tgoto out1;\n \t}\n \n"
  },
  {
    "path": "target/linux/generic/backport-5.10/789-v5.12-r8152-spilt-rtl_set_eee_plus-and-r8153b_green_en.patch",
    "content": "From 260814de2d6cb958767785ffcb2e76915d1be32b Mon Sep 17 00:00:00 2001\nFrom: Hayes Wang <hayeswang@realtek.com>\nDate: Fri, 19 Feb 2021 17:04:43 +0800\nSubject: [PATCH] r8152: spilt rtl_set_eee_plus and r8153b_green_en\n\ncommit 40fa7568ac230446d888b7ad402cff9e20fe3ad5 upstream.\n\nAdd rtl_eee_plus_en() and rtl_green_en().\n\nSigned-off-by: Hayes Wang <hayeswang@realtek.com>\nSigned-off-by: Jakub Kicinski <kuba@kernel.org>\n---\n drivers/net/usb/r8152.c | 43 ++++++++++++++++++++++++++---------------\n 1 file changed, 27 insertions(+), 16 deletions(-)\n\n--- a/drivers/net/usb/r8152.c\n+++ b/drivers/net/usb/r8152.c\n@@ -2632,21 +2632,24 @@ static inline u8 rtl8152_get_speed(struc\n \treturn ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);\n }\n \n-static void rtl_set_eee_plus(struct r8152 *tp)\n+static void rtl_eee_plus_en(struct r8152 *tp, bool enable)\n {\n \tu32 ocp_data;\n-\tu8 speed;\n \n-\tspeed = rtl8152_get_speed(tp);\n-\tif (speed & _10bps) {\n-\t\tocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);\n+\tocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);\n+\tif (enable)\n \t\tocp_data |= EEEP_CR_EEEP_TX;\n-\t\tocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);\n-\t} else {\n-\t\tocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);\n+\telse\n \t\tocp_data &= ~EEEP_CR_EEEP_TX;\n-\t\tocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);\n-\t}\n+\tocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);\n+}\n+\n+static void rtl_set_eee_plus(struct r8152 *tp)\n+{\n+\tif (rtl8152_get_speed(tp) & _10bps)\n+\t\trtl_eee_plus_en(tp, true);\n+\telse\n+\t\trtl_eee_plus_en(tp, false);\n }\n \n static void rxdy_gated_en(struct r8152 *tp, bool enable)\n@@ -3127,10 +3130,22 @@ static void r8153b_ups_flags(struct r815\n \tocp_write_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS, ups_flags);\n }\n \n-static void r8153b_green_en(struct r8152 *tp, bool enable)\n+static void rtl_green_en(struct r8152 *tp, bool enable)\n {\n \tu16 data;\n \n+\tdata = sram_read(tp, SRAM_GREEN_CFG);\n+\tif (enable)\n+\t\tdata |= GREEN_ETH_EN;\n+\telse\n+\t\tdata &= ~GREEN_ETH_EN;\n+\tsram_write(tp, SRAM_GREEN_CFG, data);\n+\n+\ttp->ups_info.green = enable;\n+}\n+\n+static void r8153b_green_en(struct r8152 *tp, bool enable)\n+{\n \tif (enable) {\n \t\tsram_write(tp, 0x8045, 0);\t/* 10M abiq&ldvbias */\n \t\tsram_write(tp, 0x804d, 0x1222);\t/* 100M short abiq&ldvbias */\n@@ -3141,11 +3156,7 @@ static void r8153b_green_en(struct r8152\n \t\tsram_write(tp, 0x805d, 0x2444);\t/* 1000M short abiq&ldvbias */\n \t}\n \n-\tdata = sram_read(tp, SRAM_GREEN_CFG);\n-\tdata |= GREEN_ETH_EN;\n-\tsram_write(tp, SRAM_GREEN_CFG, data);\n-\n-\ttp->ups_info.green = enable;\n+\trtl_green_en(tp, true);\n }\n \n static u16 r8153_phy_status(struct r8152 *tp, u16 desired)\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/790-v5.13-r8152-set-inter-fram-gap-time-depending-on-speed.patch",
    "content": "From f1bbbb260a8016373adf239c716d2da90e6ced0b Mon Sep 17 00:00:00 2001\nFrom: Hayes Wang <hayeswang@realtek.com>\nDate: Fri, 16 Apr 2021 16:04:32 +0800\nSubject: [PATCH] r8152: set inter fram gap time depending on speed\n\ncommit 5133bcc7481528e36fff0a3b056601efb704fb32 upstream.\n\nSet the maximum inter frame gap time (144ns) for speed 10M/half and\n100M/half. It improves the performance for those speeds. And, there\nis no effect for the other speeds.\n\nFor 10M/half and 100M/half, the fast inter frame gap time let the\ndevice couldn't use the feature of the aggregation effectively,\nbecause the transfer would be completed fastly. Therefore, use the\nmaximum value to improve the effect of the aggregation. However, you\nmay not feel the improvement for fast CPUs, because they compensate\nfor the effect of the aggregation.\n\nSigned-off-by: Hayes Wang <hayeswang@realtek.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/usb/r8152.c | 28 ++++++++++++++++++++++++++++\n 1 file changed, 28 insertions(+)\n\n--- a/drivers/net/usb/r8152.c\n+++ b/drivers/net/usb/r8152.c\n@@ -249,6 +249,9 @@\n \n /* PLA_TCR1 */\n #define VERSION_MASK\t\t0x7cf0\n+#define IFG_MASK\t\t(BIT(3) | BIT(9) | BIT(8))\n+#define IFG_144NS\t\tBIT(9)\n+#define IFG_96NS\t\t(BIT(9) | BIT(8))\n \n /* PLA_MTPS */\n #define MTPS_JUMBO\t\t(12 * 1024 / 64)\n@@ -2747,6 +2750,29 @@ static int rtl_stop_rx(struct r8152 *tp)\n \treturn 0;\n }\n \n+static void rtl_set_ifg(struct r8152 *tp, u16 speed)\n+{\n+\tu32 ocp_data;\n+\n+\tocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1);\n+\tocp_data &= ~IFG_MASK;\n+\tif ((speed & (_10bps | _100bps)) && !(speed & FULL_DUP)) {\n+\t\tocp_data |= IFG_144NS;\n+\t\tocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR1, ocp_data);\n+\n+\t\tocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);\n+\t\tocp_data &= ~TX10MIDLE_EN;\n+\t\tocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data);\n+\t} else {\n+\t\tocp_data |= IFG_96NS;\n+\t\tocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR1, ocp_data);\n+\n+\t\tocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);\n+\t\tocp_data |= TX10MIDLE_EN;\n+\t\tocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data);\n+\t}\n+}\n+\n static inline void r8153b_rx_agg_chg_indicate(struct r8152 *tp)\n {\n \tocp_write_byte(tp, MCU_TYPE_USB, USB_UPT_RXDMA_OWN,\n@@ -2850,6 +2876,8 @@ static int rtl8153_enable(struct r8152 *\n \tr8153_set_rx_early_timeout(tp);\n \tr8153_set_rx_early_size(tp);\n \n+\trtl_set_ifg(tp, rtl8152_get_speed(tp));\n+\n \tif (tp->version == RTL_VER_09) {\n \t\tu32 ocp_data;\n \n"
  },
  {
    "path": "target/linux/generic/backport-5.10/791-v5.13-r8152-adjust-rtl8152_check_firmware-function.patch",
    "content": "From f10c9edf47d3fa240d965e151a48c670f5035b73 Mon Sep 17 00:00:00 2001\nFrom: Hayes Wang <hayeswang@realtek.com>\nDate: Fri, 16 Apr 2021 16:04:33 +0800\nSubject: [PATCH] r8152: adjust rtl8152_check_firmware function\n\ncommit a8a7be178e81a3d4b6972cbeb0ccd091ca2f9f89 upstream.\n\nUse bits operations to record and check the firmware.\n\nSigned-off-by: Hayes Wang <hayeswang@realtek.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/usb/r8152.c | 51 +++++++++++++++++++++++------------------\n 1 file changed, 29 insertions(+), 22 deletions(-)\n\n--- a/drivers/net/usb/r8152.c\n+++ b/drivers/net/usb/r8152.c\n@@ -874,6 +874,14 @@ struct fw_header {\n \tstruct fw_block blocks[];\n } __packed;\n \n+enum rtl8152_fw_flags {\n+\tFW_FLAGS_USB = 0,\n+\tFW_FLAGS_PLA,\n+\tFW_FLAGS_START,\n+\tFW_FLAGS_STOP,\n+\tFW_FLAGS_NC,\n+};\n+\n /**\n  * struct fw_mac - a firmware block used by RTL_FW_PLA and RTL_FW_USB.\n  *\tThe layout of the firmware block is:\n@@ -3800,10 +3808,7 @@ static long rtl8152_check_firmware(struc\n {\n \tconst struct firmware *fw = rtl_fw->fw;\n \tstruct fw_header *fw_hdr = (struct fw_header *)fw->data;\n-\tstruct fw_mac *pla = NULL, *usb = NULL;\n-\tstruct fw_phy_patch_key *start = NULL;\n-\tstruct fw_phy_nc *phy_nc = NULL;\n-\tstruct fw_block *stop = NULL;\n+\tunsigned long fw_flags = 0;\n \tlong ret = -EFAULT;\n \tint i;\n \n@@ -3832,50 +3837,52 @@ static long rtl8152_check_firmware(struc\n \t\t\t\tgoto fail;\n \t\t\tgoto fw_end;\n \t\tcase RTL_FW_PLA:\n-\t\t\tif (pla) {\n+\t\t\tif (test_bit(FW_FLAGS_PLA, &fw_flags)) {\n \t\t\t\tdev_err(&tp->intf->dev,\n \t\t\t\t\t\"multiple PLA firmware encountered\");\n \t\t\t\tgoto fail;\n \t\t\t}\n \n-\t\t\tpla = (struct fw_mac *)block;\n-\t\t\tif (!rtl8152_is_fw_mac_ok(tp, pla)) {\n+\t\t\tif (!rtl8152_is_fw_mac_ok(tp, (struct fw_mac *)block)) {\n \t\t\t\tdev_err(&tp->intf->dev,\n \t\t\t\t\t\"check PLA firmware failed\\n\");\n \t\t\t\tgoto fail;\n \t\t\t}\n+\t\t\t__set_bit(FW_FLAGS_PLA, &fw_flags);\n \t\t\tbreak;\n \t\tcase RTL_FW_USB:\n-\t\t\tif (usb) {\n+\t\t\tif (test_bit(FW_FLAGS_USB, &fw_flags)) {\n \t\t\t\tdev_err(&tp->intf->dev,\n \t\t\t\t\t\"multiple USB firmware encountered\");\n \t\t\t\tgoto fail;\n \t\t\t}\n \n-\t\t\tusb = (struct fw_mac *)block;\n-\t\t\tif (!rtl8152_is_fw_mac_ok(tp, usb)) {\n+\t\t\tif (!rtl8152_is_fw_mac_ok(tp, (struct fw_mac *)block)) {\n \t\t\t\tdev_err(&tp->intf->dev,\n \t\t\t\t\t\"check USB firmware failed\\n\");\n \t\t\t\tgoto fail;\n \t\t\t}\n+\t\t\t__set_bit(FW_FLAGS_USB, &fw_flags);\n \t\t\tbreak;\n \t\tcase RTL_FW_PHY_START:\n-\t\t\tif (start || phy_nc || stop) {\n+\t\t\tif (test_bit(FW_FLAGS_START, &fw_flags) ||\n+\t\t\t    test_bit(FW_FLAGS_NC, &fw_flags) ||\n+\t\t\t    test_bit(FW_FLAGS_STOP, &fw_flags)) {\n \t\t\t\tdev_err(&tp->intf->dev,\n \t\t\t\t\t\"check PHY_START fail\\n\");\n \t\t\t\tgoto fail;\n \t\t\t}\n \n-\t\t\tif (__le32_to_cpu(block->length) != sizeof(*start)) {\n+\t\t\tif (__le32_to_cpu(block->length) != sizeof(struct fw_phy_patch_key)) {\n \t\t\t\tdev_err(&tp->intf->dev,\n \t\t\t\t\t\"Invalid length for PHY_START\\n\");\n \t\t\t\tgoto fail;\n \t\t\t}\n-\n-\t\t\tstart = (struct fw_phy_patch_key *)block;\n+\t\t\t__set_bit(FW_FLAGS_START, &fw_flags);\n \t\t\tbreak;\n \t\tcase RTL_FW_PHY_STOP:\n-\t\t\tif (stop || !start) {\n+\t\t\tif (test_bit(FW_FLAGS_STOP, &fw_flags) ||\n+\t\t\t    !test_bit(FW_FLAGS_START, &fw_flags)) {\n \t\t\t\tdev_err(&tp->intf->dev,\n \t\t\t\t\t\"Check PHY_STOP fail\\n\");\n \t\t\t\tgoto fail;\n@@ -3886,28 +3893,28 @@ static long rtl8152_check_firmware(struc\n \t\t\t\t\t\"Invalid length for PHY_STOP\\n\");\n \t\t\t\tgoto fail;\n \t\t\t}\n-\n-\t\t\tstop = block;\n+\t\t\t__set_bit(FW_FLAGS_STOP, &fw_flags);\n \t\t\tbreak;\n \t\tcase RTL_FW_PHY_NC:\n-\t\t\tif (!start || stop) {\n+\t\t\tif (!test_bit(FW_FLAGS_START, &fw_flags) ||\n+\t\t\t    test_bit(FW_FLAGS_STOP, &fw_flags)) {\n \t\t\t\tdev_err(&tp->intf->dev,\n \t\t\t\t\t\"check PHY_NC fail\\n\");\n \t\t\t\tgoto fail;\n \t\t\t}\n \n-\t\t\tif (phy_nc) {\n+\t\t\tif (test_bit(FW_FLAGS_NC, &fw_flags)) {\n \t\t\t\tdev_err(&tp->intf->dev,\n \t\t\t\t\t\"multiple PHY NC encountered\\n\");\n \t\t\t\tgoto fail;\n \t\t\t}\n \n-\t\t\tphy_nc = (struct fw_phy_nc *)block;\n-\t\t\tif (!rtl8152_is_fw_phy_nc_ok(tp, phy_nc)) {\n+\t\t\tif (!rtl8152_is_fw_phy_nc_ok(tp, (struct fw_phy_nc *)block)) {\n \t\t\t\tdev_err(&tp->intf->dev,\n \t\t\t\t\t\"check PHY NC firmware failed\\n\");\n \t\t\t\tgoto fail;\n \t\t\t}\n+\t\t\t__set_bit(FW_FLAGS_NC, &fw_flags);\n \n \t\t\tbreak;\n \t\tdefault:\n@@ -3921,7 +3928,7 @@ static long rtl8152_check_firmware(struc\n \t}\n \n fw_end:\n-\tif ((phy_nc || start) && !stop) {\n+\tif (test_bit(FW_FLAGS_START, &fw_flags) && !test_bit(FW_FLAGS_STOP, &fw_flags)) {\n \t\tdev_err(&tp->intf->dev, \"without PHY_STOP\\n\");\n \t\tgoto fail;\n \t}\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/792-v5.13-r8152-add-help-function-to-change-mtu.patch",
    "content": "From f010a7d51cbb42bdb956f0a28b8868b15d7a3816 Mon Sep 17 00:00:00 2001\nFrom: Hayes Wang <hayeswang@realtek.com>\nDate: Fri, 16 Apr 2021 16:04:34 +0800\nSubject: [PATCH] r8152: add help function to change mtu\n\ncommit 67ce1a806f164e59a074fea8809725d3411eaa20 upstream.\n\nThe different chips may have different requests when changing mtu.\nTherefore, add a new help function of rtl_ops to change mtu. Besides,\nreset the tx/rx after changing mtu.\n\nAdditionally, add mtu_to_size() and size_to_mtu() macros to simplify\nthe code.\n\nSigned-off-by: Hayes Wang <hayeswang@realtek.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/usb/r8152.c | 53 ++++++++++++++++++++++++-----------------\n 1 file changed, 31 insertions(+), 22 deletions(-)\n\n--- a/drivers/net/usb/r8152.c\n+++ b/drivers/net/usb/r8152.c\n@@ -657,15 +657,13 @@ enum rtl_register_content {\n \n #define INTR_LINK\t\t0x0004\n \n-#define RTL8153_MAX_PACKET\t9216 /* 9K */\n-#define RTL8153_MAX_MTU\t\t(RTL8153_MAX_PACKET - VLAN_ETH_HLEN - \\\n-\t\t\t\t ETH_FCS_LEN)\n #define RTL8152_RMS\t\t(VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)\n #define RTL8153_RMS\t\tRTL8153_MAX_PACKET\n #define RTL8152_TX_TIMEOUT\t(5 * HZ)\n #define RTL8152_NAPI_WEIGHT\t64\n-#define rx_reserved_size(x)\t((x) + VLAN_ETH_HLEN + ETH_FCS_LEN + \\\n-\t\t\t\t sizeof(struct rx_desc) + RX_ALIGN)\n+#define mtu_to_size(m)\t\t((m) + VLAN_ETH_HLEN + ETH_FCS_LEN)\n+#define size_to_mtu(s)\t\t((s) - VLAN_ETH_HLEN - ETH_FCS_LEN)\n+#define rx_reserved_size(x)\t(mtu_to_size(x) + sizeof(struct rx_desc) + RX_ALIGN)\n \n /* rtl8152 flags */\n enum rtl8152_flags {\n@@ -795,6 +793,7 @@ struct r8152 {\n \t\tbool (*in_nway)(struct r8152 *tp);\n \t\tvoid (*hw_phy_cfg)(struct r8152 *tp);\n \t\tvoid (*autosuspend_en)(struct r8152 *tp, bool enable);\n+\t\tvoid (*change_mtu)(struct r8152 *tp);\n \t} rtl_ops;\n \n \tstruct ups_info {\n@@ -1021,8 +1020,7 @@ enum tx_csum_stat {\n static const int multicast_filter_limit = 32;\n static unsigned int agg_buf_sz = 16384;\n \n-#define RTL_LIMITED_TSO_SIZE\t(agg_buf_sz - sizeof(struct tx_desc) - \\\n-\t\t\t\t VLAN_ETH_HLEN - ETH_FCS_LEN)\n+#define RTL_LIMITED_TSO_SIZE\t(size_to_mtu(agg_buf_sz) - sizeof(struct tx_desc))\n \n static\n int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)\n@@ -2632,10 +2630,7 @@ static void rtl8152_nic_reset(struct r81\n \n static void set_tx_qlen(struct r8152 *tp)\n {\n-\tstruct net_device *netdev = tp->netdev;\n-\n-\ttp->tx_qlen = agg_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN +\n-\t\t\t\t    sizeof(struct tx_desc));\n+\ttp->tx_qlen = agg_buf_sz / (mtu_to_size(tp->netdev->mtu) + sizeof(struct tx_desc));\n }\n \n static inline u8 rtl8152_get_speed(struct r8152 *tp)\n@@ -4724,6 +4719,12 @@ static void r8153b_hw_phy_cfg(struct r81\n \tset_bit(PHY_RESET, &tp->flags);\n }\n \n+static void rtl8153_change_mtu(struct r8152 *tp)\n+{\n+\tocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, mtu_to_size(tp->netdev->mtu));\n+\tocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);\n+}\n+\n static void r8153_first_init(struct r8152 *tp)\n {\n \tu32 ocp_data;\n@@ -4756,9 +4757,7 @@ static void r8153_first_init(struct r815\n \n \trtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);\n \n-\tocp_data = tp->netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;\n-\tocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data);\n-\tocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);\n+\trtl8153_change_mtu(tp);\n \n \tocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);\n \tocp_data |= TCR0_AUTO_FIFO;\n@@ -4793,8 +4792,7 @@ static void r8153_enter_oob(struct r8152\n \n \twait_oob_link_list_ready(tp);\n \n-\tocp_data = tp->netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;\n-\tocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data);\n+\tocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, mtu_to_size(tp->netdev->mtu));\n \n \tswitch (tp->version) {\n \tcase RTL_VER_03:\n@@ -6495,12 +6493,21 @@ static int rtl8152_change_mtu(struct net\n \tdev->mtu = new_mtu;\n \n \tif (netif_running(dev)) {\n-\t\tu32 rms = new_mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;\n-\n-\t\tocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, rms);\n+\t\tif (tp->rtl_ops.change_mtu)\n+\t\t\ttp->rtl_ops.change_mtu(tp);\n \n-\t\tif (netif_carrier_ok(dev))\n-\t\t\tr8153_set_rx_early_size(tp);\n+\t\tif (netif_carrier_ok(dev)) {\n+\t\t\tnetif_stop_queue(dev);\n+\t\t\tnapi_disable(&tp->napi);\n+\t\t\ttasklet_disable(&tp->tx_tl);\n+\t\t\ttp->rtl_ops.disable(tp);\n+\t\t\ttp->rtl_ops.enable(tp);\n+\t\t\trtl_start_rx(tp);\n+\t\t\ttasklet_enable(&tp->tx_tl);\n+\t\t\tnapi_enable(&tp->napi);\n+\t\t\trtl8152_set_rx_mode(dev);\n+\t\t\tnetif_wake_queue(dev);\n+\t\t}\n \t}\n \n \tmutex_unlock(&tp->control);\n@@ -6589,6 +6596,7 @@ static int rtl_ops_init(struct r8152 *tp\n \t\tops->in_nway\t\t= rtl8153_in_nway;\n \t\tops->hw_phy_cfg\t\t= r8153_hw_phy_cfg;\n \t\tops->autosuspend_en\t= rtl8153_runtime_enable;\n+\t\tops->change_mtu\t\t= rtl8153_change_mtu;\n \t\tif (tp->udev->speed < USB_SPEED_SUPER)\n \t\t\ttp->rx_buf_sz\t= 16 * 1024;\n \t\telse\n@@ -6610,6 +6618,7 @@ static int rtl_ops_init(struct r8152 *tp\n \t\tops->in_nway\t\t= rtl8153_in_nway;\n \t\tops->hw_phy_cfg\t\t= r8153b_hw_phy_cfg;\n \t\tops->autosuspend_en\t= rtl8153b_runtime_enable;\n+\t\tops->change_mtu\t\t= rtl8153_change_mtu;\n \t\ttp->rx_buf_sz\t\t= 32 * 1024;\n \t\ttp->eee_en\t\t= true;\n \t\ttp->eee_adv\t\t= MDIO_EEE_1000T | MDIO_EEE_100TX;\n@@ -6830,7 +6839,7 @@ static int rtl8152_probe(struct usb_inte\n \t\tnetdev->max_mtu = ETH_DATA_LEN;\n \t\tbreak;\n \tdefault:\n-\t\tnetdev->max_mtu = RTL8153_MAX_MTU;\n+\t\tnetdev->max_mtu = size_to_mtu(9 * 1024);\n \t\tbreak;\n \t}\n \n"
  },
  {
    "path": "target/linux/generic/backport-5.10/793-v5.13-r8152-support-new-chips.patch",
    "content": "From e7439e7fd384f55f55837f7e4866e74d8dca3827 Mon Sep 17 00:00:00 2001\nFrom: Hayes Wang <hayeswang@realtek.com>\nDate: Fri, 16 Apr 2021 16:04:35 +0800\nSubject: [PATCH] r8152: support new chips\n\ncommit 195aae321c829dd1945900d75561e6aa79cce208 upstream.\n\nSupport RTL8153C, RTL8153D, RTL8156A, and RTL8156B. The RTL8156A\nand RTL8156B are the 2.5G ethernet.\n\nSigned-off-by: Hayes Wang <hayeswang@realtek.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/usb/r8152.c | 2634 +++++++++++++++++++++++++++++++++++----\n 1 file changed, 2359 insertions(+), 275 deletions(-)\n\n--- a/drivers/net/usb/r8152.c\n+++ b/drivers/net/usb/r8152.c\n@@ -43,10 +43,14 @@\n \n #define PLA_IDR\t\t\t0xc000\n #define PLA_RCR\t\t\t0xc010\n+#define PLA_RCR1\t\t0xc012\n #define PLA_RMS\t\t\t0xc016\n #define PLA_RXFIFO_CTRL0\t0xc0a0\n+#define PLA_RXFIFO_FULL\t\t0xc0a2\n #define PLA_RXFIFO_CTRL1\t0xc0a4\n+#define PLA_RX_FIFO_FULL\t0xc0a6\n #define PLA_RXFIFO_CTRL2\t0xc0a8\n+#define PLA_RX_FIFO_EMPTY\t0xc0aa\n #define PLA_DMY_REG0\t\t0xc0b0\n #define PLA_FMC\t\t\t0xc0b4\n #define PLA_CFG_WOL\t\t0xc0b6\n@@ -63,6 +67,8 @@\n #define PLA_MACDBG_PRE\t\t0xd38c\t/* RTL_VER_04 only */\n #define PLA_MACDBG_POST\t\t0xd38e\t/* RTL_VER_04 only */\n #define PLA_EXTRA_STATUS\t0xd398\n+#define PLA_GPHY_CTRL\t\t0xd3ae\n+#define PLA_POL_GPIO_CTRL\t0xdc6a\n #define PLA_EFUSE_DATA\t\t0xdd00\n #define PLA_EFUSE_CMD\t\t0xdd02\n #define PLA_LEDSEL\t\t0xdd90\n@@ -72,6 +78,8 @@\n #define PLA_LWAKE_CTRL_REG\t0xe007\n #define PLA_GPHY_INTR_IMR\t0xe022\n #define PLA_EEE_CR\t\t0xe040\n+#define PLA_EEE_TXTWSYS\t\t0xe04c\n+#define PLA_EEE_TXTWSYS_2P5G\t0xe058\n #define PLA_EEEP_CR\t\t0xe080\n #define PLA_MAC_PWR_CTRL\t0xe0c0\n #define PLA_MAC_PWR_CTRL2\t0xe0ca\n@@ -82,6 +90,7 @@\n #define PLA_TCR1\t\t0xe612\n #define PLA_MTPS\t\t0xe615\n #define PLA_TXFIFO_CTRL\t\t0xe618\n+#define PLA_TXFIFO_FULL\t\t0xe61a\n #define PLA_RSTTALLY\t\t0xe800\n #define PLA_CR\t\t\t0xe813\n #define PLA_CRWECR\t\t0xe81c\n@@ -98,6 +107,7 @@\n #define PLA_SFF_STS_7\t\t0xe8de\n #define PLA_PHYSTATUS\t\t0xe908\n #define PLA_CONFIG6\t\t0xe90a /* CONFIG6 */\n+#define PLA_USB_CFG\t\t0xe952\n #define PLA_BP_BA\t\t0xfc26\n #define PLA_BP_0\t\t0xfc28\n #define PLA_BP_1\t\t0xfc2a\n@@ -112,6 +122,7 @@\n #define USB_USB2PHY\t\t0xb41e\n #define USB_SSPHYLINK1\t\t0xb426\n #define USB_SSPHYLINK2\t\t0xb428\n+#define USB_L1_CTRL\t\t0xb45e\n #define USB_U2P3_CTRL\t\t0xb460\n #define USB_CSR_DUMMY1\t\t0xb464\n #define USB_CSR_DUMMY2\t\t0xb466\n@@ -122,7 +133,12 @@\n #define USB_FW_FIX_EN0\t\t0xcfca\n #define USB_FW_FIX_EN1\t\t0xcfcc\n #define USB_LPM_CONFIG\t\t0xcfd8\n+#define USB_ECM_OPTION\t\t0xcfee\n #define USB_CSTMR\t\t0xcfef\t/* RTL8153A */\n+#define USB_MISC_2\t\t0xcfff\n+#define USB_ECM_OP\t\t0xd26b\n+#define USB_GPHY_CTRL\t\t0xd284\n+#define USB_SPEED_OPTION\t0xd32a\n #define USB_FW_CTRL\t\t0xd334\t/* RTL8153B */\n #define USB_FC_TIMER\t\t0xd340\n #define USB_USB_CTRL\t\t0xd406\n@@ -136,16 +152,20 @@\n #define USB_RX_EXTRA_AGGR_TMR\t0xd432\t/* RTL8153B */\n #define USB_TX_DMA\t\t0xd434\n #define USB_UPT_RXDMA_OWN\t0xd437\n+#define USB_UPHY3_MDCMDIO\t0xd480\n #define USB_TOLERANCE\t\t0xd490\n #define USB_LPM_CTRL\t\t0xd41a\n #define USB_BMU_RESET\t\t0xd4b0\n+#define USB_BMU_CONFIG\t\t0xd4b4\n #define USB_U1U2_TIMER\t\t0xd4da\n #define USB_FW_TASK\t\t0xd4e8\t/* RTL8153B */\n+#define USB_RX_AGGR_NUM\t\t0xd4ee\n #define USB_UPS_CTRL\t\t0xd800\n #define USB_POWER_CUT\t\t0xd80a\n #define USB_MISC_0\t\t0xd81a\n #define USB_MISC_1\t\t0xd81f\n #define USB_AFE_CTRL2\t\t0xd824\n+#define USB_UPHY_XTAL\t\t0xd826\n #define USB_UPS_CFG\t\t0xd842\n #define USB_UPS_FLAGS\t\t0xd848\n #define USB_WDT1_CTRL\t\t0xe404\n@@ -188,6 +208,9 @@\n #define OCP_EEE_ABLE\t\t0xa5c4\n #define OCP_EEE_ADV\t\t0xa5d0\n #define OCP_EEE_LPABLE\t\t0xa5d2\n+#define OCP_10GBT_CTRL\t\t0xa5d4\n+#define OCP_10GBT_STAT\t\t0xa5d6\n+#define OCP_EEE_ADV2\t\t0xa6d4\n #define OCP_PHY_STATE\t\t0xa708\t\t/* nway state for 8153 */\n #define OCP_PHY_PATCH_STAT\t0xb800\n #define OCP_PHY_PATCH_CMD\t0xb820\n@@ -199,6 +222,7 @@\n /* SRAM Register */\n #define SRAM_GREEN_CFG\t\t0x8011\n #define SRAM_LPF_CFG\t\t0x8012\n+#define SRAM_GPHY_FW_VER\t0x801e\n #define SRAM_10M_AMP1\t\t0x8080\n #define SRAM_10M_AMP2\t\t0x8082\n #define SRAM_IMPEDANCE\t\t0x8084\n@@ -210,11 +234,19 @@\n #define RCR_AM\t\t\t0x00000004\n #define RCR_AB\t\t\t0x00000008\n #define RCR_ACPT_ALL\t\t(RCR_AAP | RCR_APM | RCR_AM | RCR_AB)\n+#define SLOT_EN\t\t\tBIT(11)\n+\n+/* PLA_RCR1 */\n+#define OUTER_VLAN\t\tBIT(7)\n+#define INNER_VLAN\t\tBIT(6)\n \n /* PLA_RXFIFO_CTRL0 */\n #define RXFIFO_THR1_NORMAL\t0x00080002\n #define RXFIFO_THR1_OOB\t\t0x01800003\n \n+/* PLA_RXFIFO_FULL */\n+#define RXFIFO_FULL_MASK\t0xfff\n+\n /* PLA_RXFIFO_CTRL1 */\n #define RXFIFO_THR2_FULL\t0x00000060\n #define RXFIFO_THR2_HIGH\t0x00000038\n@@ -285,6 +317,7 @@\n #define MCU_BORW_EN\t\t0x4000\n \n /* PLA_CPCR */\n+#define FLOW_CTRL_EN\t\tBIT(0)\n #define CPCR_RX_VLAN\t\t0x0040\n \n /* PLA_CFG_WOL */\n@@ -310,6 +343,10 @@\n /* PLA_CONFIG6 */\n #define LANWAKE_CLR_EN\t\tBIT(0)\n \n+/* PLA_USB_CFG */\n+#define EN_XG_LIP\t\tBIT(1)\n+#define EN_G_LIP\t\tBIT(2)\n+\n /* PLA_CONFIG5 */\n #define BWF_EN\t\t\t0x0040\n #define MWF_EN\t\t\t0x0020\n@@ -333,6 +370,7 @@\n /* PLA_MAC_PWR_CTRL2 */\n #define EEE_SPDWN_RATIO\t\t0x8007\n #define MAC_CLK_SPDWN_EN\tBIT(15)\n+#define EEE_SPDWN_RATIO_MASK\t0xff\n \n /* PLA_MAC_PWR_CTRL3 */\n #define PLA_MCU_SPDWN_EN\tBIT(14)\n@@ -345,6 +383,7 @@\n #define PWRSAVE_SPDWN_EN\t0x1000\n #define RXDV_SPDWN_EN\t\t0x0800\n #define TX10MIDLE_EN\t\t0x0100\n+#define IDLE_SPDWN_EN\t\tBIT(6)\n #define TP100_SPDWN_EN\t\t0x0020\n #define TP500_SPDWN_EN\t\t0x0010\n #define TP1000_SPDWN_EN\t\t0x0008\n@@ -385,6 +424,13 @@\n #define LINK_CHANGE_FLAG\tBIT(8)\n #define POLL_LINK_CHG\t\tBIT(0)\n \n+/* PLA_GPHY_CTRL */\n+#define GPHY_FLASH\t\tBIT(1)\n+\n+/* PLA_POL_GPIO_CTRL */\n+#define DACK_DET_EN\t\tBIT(15)\n+#define POL_GPHY_PATCH\t\tBIT(4)\n+\n /* USB_USB2PHY */\n #define USB2PHY_SUSPEND\t\t0x0001\n #define USB2PHY_L1\t\t0x0002\n@@ -433,6 +479,9 @@\n #define BMU_RESET_EP_IN\t\t0x01\n #define BMU_RESET_EP_OUT\t0x02\n \n+/* USB_BMU_CONFIG */\n+#define ACT_ODMA\t\tBIT(1)\n+\n /* USB_UPT_RXDMA_OWN */\n #define OWN_UPDATE\t\tBIT(0)\n #define OWN_CLEAR\t\tBIT(1)\n@@ -440,27 +489,52 @@\n /* USB_FW_TASK */\n #define FC_PATCH_TASK\t\tBIT(1)\n \n+/* USB_RX_AGGR_NUM */\n+#define RX_AGGR_NUM_MASK\t0x1ff\n+\n /* USB_UPS_CTRL */\n #define POWER_CUT\t\t0x0100\n \n /* USB_PM_CTRL_STATUS */\n #define RESUME_INDICATE\t\t0x0001\n \n+/* USB_ECM_OPTION */\n+#define BYPASS_MAC_RESET\tBIT(5)\n+\n /* USB_CSTMR */\n #define FORCE_SUPER\t\tBIT(0)\n \n+/* USB_MISC_2 */\n+#define UPS_FORCE_PWR_DOWN\tBIT(0)\n+\n+/* USB_ECM_OP */\n+#define\tEN_ALL_SPEED\t\tBIT(0)\n+\n+/* USB_GPHY_CTRL */\n+#define GPHY_PATCH_DONE\t\tBIT(2)\n+#define BYPASS_FLASH\t\tBIT(5)\n+#define BACKUP_RESTRORE\t\tBIT(6)\n+\n+/* USB_SPEED_OPTION */\n+#define RG_PWRDN_EN\t\tBIT(8)\n+#define ALL_SPEED_OFF\t\tBIT(9)\n+\n /* USB_FW_CTRL */\n #define FLOW_CTRL_PATCH_OPT\tBIT(1)\n+#define AUTO_SPEEDUP\t\tBIT(3)\n+#define FLOW_CTRL_PATCH_2\tBIT(8)\n \n /* USB_FC_TIMER */\n #define CTRL_TIMER_EN\t\tBIT(15)\n \n /* USB_USB_CTRL */\n+#define CDC_ECM_EN\t\tBIT(3)\n #define RX_AGG_DISABLE\t\t0x0010\n #define RX_ZERO_EN\t\t0x0080\n \n /* USB_U2P3_CTRL */\n #define U2P3_ENABLE\t\t0x0001\n+#define RX_DETECT8\t\tBIT(3)\n \n /* USB_POWER_CUT */\n #define PWR_EN\t\t\t0x0001\n@@ -496,8 +570,12 @@\n #define SEN_VAL_NORMAL\t\t0xa000\n #define SEL_RXIDLE\t\t0x0100\n \n+/* USB_UPHY_XTAL */\n+#define OOBS_POLLING\t\tBIT(8)\n+\n /* USB_UPS_CFG */\n #define SAW_CNT_1MS_MASK\t0x0fff\n+#define MID_REVERSE\t\tBIT(5)\t/* RTL8156A */\n \n /* USB_UPS_FLAGS */\n #define UPS_FLAGS_R_TUNE\t\tBIT(0)\n@@ -505,6 +583,7 @@\n #define UPS_FLAGS_250M_CKDIV\t\tBIT(2)\n #define UPS_FLAGS_EN_ALDPS\t\tBIT(3)\n #define UPS_FLAGS_CTAP_SHORT_DIS\tBIT(4)\n+#define UPS_FLAGS_SPEED_MASK\t\t(0xf << 16)\n #define ups_flags_speed(x)\t\t((x) << 16)\n #define UPS_FLAGS_EN_EEE\t\tBIT(20)\n #define UPS_FLAGS_EN_500M_EEE\t\tBIT(21)\n@@ -525,6 +604,8 @@ enum spd_duplex {\n \tFORCE_10M_FULL,\n \tFORCE_100M_HALF,\n \tFORCE_100M_FULL,\n+\tFORCE_1000M_FULL,\n+\tNWAY_2500M_FULL,\n };\n \n /* OCP_ALDPS_CONFIG */\n@@ -589,6 +670,9 @@ enum spd_duplex {\n #define EN_10M_CLKDIV\t\tBIT(11)\n #define EN_10M_BGOFF\t\t0x0080\n \n+/* OCP_10GBT_CTRL */\n+#define RTL_ADV2_5G_F_R\t\tBIT(5)\t/* Advertise 2.5GBASE-T fast-retrain */\n+\n /* OCP_PHY_STATE */\n #define TXDIS_STATE\t\t0x01\n #define ABD_STATE\t\t0x02\n@@ -608,7 +692,8 @@ enum spd_duplex {\n #define EN_EMI_L\t\t0x0040\n \n /* OCP_SYSCLK_CFG */\n-#define clk_div_expo(x)\t\t(min(x, 5) << 8)\n+#define sysclk_div_expo(x)\t(min(x, 5) << 8)\n+#define clk_div_expo(x)\t\t(min(x, 5) << 4)\n \n /* SRAM_GREEN_CFG */\n #define GREEN_ETH_EN\t\tBIT(15)\n@@ -639,6 +724,11 @@ enum spd_duplex {\n #define BP4_SUPER_ONLY\t\t0x1578\t/* RTL_VER_04 only */\n \n enum rtl_register_content {\n+\t_2500bps\t= BIT(10),\n+\t_1250bps\t= BIT(9),\n+\t_500bps\t\t= BIT(8),\n+\t_tx_flow\t= BIT(6),\n+\t_rx_flow\t= BIT(5),\n \t_1000bps\t= 0x10,\n \t_100bps\t\t= 0x08,\n \t_10bps\t\t= 0x04,\n@@ -646,6 +736,9 @@ enum rtl_register_content {\n \tFULL_DUP\t= 0x01,\n };\n \n+#define is_speed_2500(_speed)\t(((_speed) & (_2500bps | LINK_STATUS)) == (_2500bps | LINK_STATUS))\n+#define is_flow_control(_speed)\t(((_speed) & (_tx_flow | _rx_flow)) == (_tx_flow | _rx_flow))\n+\n #define RTL8152_MAX_TX\t\t4\n #define RTL8152_MAX_RX\t\t10\n #define INTBUFSIZE\t\t2\n@@ -660,7 +753,6 @@ enum rtl_register_content {\n #define RTL8152_RMS\t\t(VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)\n #define RTL8153_RMS\t\tRTL8153_MAX_PACKET\n #define RTL8152_TX_TIMEOUT\t(5 * HZ)\n-#define RTL8152_NAPI_WEIGHT\t64\n #define mtu_to_size(m)\t\t((m) + VLAN_ETH_HLEN + ETH_FCS_LEN)\n #define size_to_mtu(s)\t\t((s) - VLAN_ETH_HLEN - ETH_FCS_LEN)\n #define rx_reserved_size(x)\t(mtu_to_size(x) + sizeof(struct rx_desc) + RX_ALIGN)\n@@ -797,6 +889,7 @@ struct r8152 {\n \t} rtl_ops;\n \n \tstruct ups_info {\n+\t\tu32 r_tune:1;\n \t\tu32 _10m_ckdiv:1;\n \t\tu32 _250m_ckdiv:1;\n \t\tu32 aldps:1;\n@@ -838,7 +931,9 @@ struct r8152 {\n \tu32 rx_buf_sz;\n \tu32 rx_copybreak;\n \tu32 rx_pending;\n+\tu32 fc_pause_on, fc_pause_off;\n \n+\tu32 support_2500full:1;\n \tu16 ocp_base;\n \tu16 speed;\n \tu16 eee_adv;\n@@ -998,6 +1093,15 @@ enum rtl_version {\n \tRTL_VER_07,\n \tRTL_VER_08,\n \tRTL_VER_09,\n+\n+\tRTL_TEST_01,\n+\tRTL_VER_10,\n+\tRTL_VER_11,\n+\tRTL_VER_12,\n+\tRTL_VER_13,\n+\tRTL_VER_14,\n+\tRTL_VER_15,\n+\n \tRTL_VER_MAX\n };\n \n@@ -1013,6 +1117,7 @@ enum tx_csum_stat {\n #define RTL_ADVERTISED_100_FULL\t\t\tBIT(3)\n #define RTL_ADVERTISED_1000_HALF\t\tBIT(4)\n #define RTL_ADVERTISED_1000_FULL\t\tBIT(5)\n+#define RTL_ADVERTISED_2500_FULL\t\tBIT(6)\n \n /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).\n  * The RTL chips use a 64 element hash table based on the Ethernet CRC.\n@@ -2606,7 +2711,7 @@ static netdev_tx_t rtl8152_start_xmit(st\n \n static void r8152b_reset_packet_filter(struct r8152 *tp)\n {\n-\tu32\tocp_data;\n+\tu32 ocp_data;\n \n \tocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);\n \tocp_data &= ~FMC_FCR_MCU_EN;\n@@ -2617,14 +2722,47 @@ static void r8152b_reset_packet_filter(s\n \n static void rtl8152_nic_reset(struct r8152 *tp)\n {\n-\tint\ti;\n+\tu32 ocp_data;\n+\tint i;\n \n-\tocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST);\n+\tswitch (tp->version) {\n+\tcase RTL_TEST_01:\n+\tcase RTL_VER_10:\n+\tcase RTL_VER_11:\n+\t\tocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);\n+\t\tocp_data &= ~CR_TE;\n+\t\tocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);\n+\n+\t\tocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_BMU_RESET);\n+\t\tocp_data &= ~BMU_RESET_EP_IN;\n+\t\tocp_write_word(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);\n+\n+\t\tocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);\n+\t\tocp_data |= CDC_ECM_EN;\n+\t\tocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);\n+\n+\t\tocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);\n+\t\tocp_data &= ~CR_RE;\n+\t\tocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);\n+\n+\t\tocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_BMU_RESET);\n+\t\tocp_data |= BMU_RESET_EP_IN;\n+\t\tocp_write_word(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);\n+\n+\t\tocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);\n+\t\tocp_data &= ~CDC_ECM_EN;\n+\t\tocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);\n+\t\tbreak;\n \n-\tfor (i = 0; i < 1000; i++) {\n-\t\tif (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST))\n-\t\t\tbreak;\n-\t\tusleep_range(100, 400);\n+\tdefault:\n+\t\tocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST);\n+\n+\t\tfor (i = 0; i < 1000; i++) {\n+\t\t\tif (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST))\n+\t\t\t\tbreak;\n+\t\t\tusleep_range(100, 400);\n+\t\t}\n+\t\tbreak;\n \t}\n }\n \n@@ -2633,9 +2771,9 @@ static void set_tx_qlen(struct r8152 *tp\n \ttp->tx_qlen = agg_buf_sz / (mtu_to_size(tp->netdev->mtu) + sizeof(struct tx_desc));\n }\n \n-static inline u8 rtl8152_get_speed(struct r8152 *tp)\n+static inline u16 rtl8152_get_speed(struct r8152 *tp)\n {\n-\treturn ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);\n+\treturn ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);\n }\n \n static void rtl_eee_plus_en(struct r8152 *tp, bool enable)\n@@ -2795,6 +2933,7 @@ static int rtl_enable(struct r8152 *tp)\n \tswitch (tp->version) {\n \tcase RTL_VER_08:\n \tcase RTL_VER_09:\n+\tcase RTL_VER_14:\n \t\tr8153b_rx_agg_chg_indicate(tp);\n \t\tbreak;\n \tdefault:\n@@ -2832,6 +2971,7 @@ static void r8153_set_rx_early_timeout(s\n \n \tcase RTL_VER_08:\n \tcase RTL_VER_09:\n+\tcase RTL_VER_14:\n \t\t/* The RTL8153B uses USB_RX_EXTRA_AGGR_TMR for rx timeout\n \t\t * primarily. For USB_RX_EARLY_TIMEOUT, we fix it to 128ns.\n \t\t */\n@@ -2841,6 +2981,18 @@ static void r8153_set_rx_early_timeout(s\n \t\t\t       ocp_data);\n \t\tbreak;\n \n+\tcase RTL_VER_10:\n+\tcase RTL_VER_11:\n+\tcase RTL_VER_12:\n+\tcase RTL_VER_13:\n+\tcase RTL_VER_15:\n+\t\tocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,\n+\t\t\t       640 / 8);\n+\t\tocp_write_word(tp, MCU_TYPE_USB, USB_RX_EXTRA_AGGR_TMR,\n+\t\t\t       ocp_data);\n+\t\tr8153b_rx_agg_chg_indicate(tp);\n+\t\tbreak;\n+\n \tdefault:\n \t\tbreak;\n \t}\n@@ -2860,8 +3012,19 @@ static void r8153_set_rx_early_size(stru\n \t\tbreak;\n \tcase RTL_VER_08:\n \tcase RTL_VER_09:\n+\tcase RTL_VER_14:\n+\t\tocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,\n+\t\t\t       ocp_data / 8);\n+\t\tbreak;\n+\tcase RTL_TEST_01:\n+\tcase RTL_VER_10:\n+\tcase RTL_VER_11:\n+\tcase RTL_VER_12:\n+\tcase RTL_VER_13:\n+\tcase RTL_VER_15:\n \t\tocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,\n \t\t\t       ocp_data / 8);\n+\t\tr8153b_rx_agg_chg_indicate(tp);\n \t\tbreak;\n \tdefault:\n \t\tWARN_ON_ONCE(1);\n@@ -2871,6 +3034,8 @@ static void r8153_set_rx_early_size(stru\n \n static int rtl8153_enable(struct r8152 *tp)\n {\n+\tu32 ocp_data;\n+\n \tif (test_bit(RTL8152_UNPLUG, &tp->flags))\n \t\treturn -ENODEV;\n \n@@ -2881,15 +3046,18 @@ static int rtl8153_enable(struct r8152 *\n \n \trtl_set_ifg(tp, rtl8152_get_speed(tp));\n \n-\tif (tp->version == RTL_VER_09) {\n-\t\tu32 ocp_data;\n-\n+\tswitch (tp->version) {\n+\tcase RTL_VER_09:\n+\tcase RTL_VER_14:\n \t\tocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);\n \t\tocp_data &= ~FC_PATCH_TASK;\n \t\tocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);\n \t\tusleep_range(1000, 2000);\n \t\tocp_data |= FC_PATCH_TASK;\n \t\tocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);\n+\t\tbreak;\n+\tdefault:\n+\t\tbreak;\n \t}\n \n \treturn rtl_enable(tp);\n@@ -2954,12 +3122,40 @@ static void rtl_rx_vlan_en(struct r8152\n {\n \tu32 ocp_data;\n \n-\tocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);\n-\tif (enable)\n-\t\tocp_data |= CPCR_RX_VLAN;\n-\telse\n-\t\tocp_data &= ~CPCR_RX_VLAN;\n-\tocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);\n+\tswitch (tp->version) {\n+\tcase RTL_VER_01:\n+\tcase RTL_VER_02:\n+\tcase RTL_VER_03:\n+\tcase RTL_VER_04:\n+\tcase RTL_VER_05:\n+\tcase RTL_VER_06:\n+\tcase RTL_VER_07:\n+\tcase RTL_VER_08:\n+\tcase RTL_VER_09:\n+\tcase RTL_VER_14:\n+\t\tocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);\n+\t\tif (enable)\n+\t\t\tocp_data |= CPCR_RX_VLAN;\n+\t\telse\n+\t\t\tocp_data &= ~CPCR_RX_VLAN;\n+\t\tocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);\n+\t\tbreak;\n+\n+\tcase RTL_TEST_01:\n+\tcase RTL_VER_10:\n+\tcase RTL_VER_11:\n+\tcase RTL_VER_12:\n+\tcase RTL_VER_13:\n+\tcase RTL_VER_15:\n+\tdefault:\n+\t\tocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RCR1);\n+\t\tif (enable)\n+\t\t\tocp_data |= OUTER_VLAN | INNER_VLAN;\n+\t\telse\n+\t\t\tocp_data &= ~(OUTER_VLAN | INNER_VLAN);\n+\t\tocp_write_word(tp, MCU_TYPE_PLA, PLA_RCR1, ocp_data);\n+\t\tbreak;\n+\t}\n }\n \n static int rtl8152_set_features(struct net_device *dev,\n@@ -3052,6 +3248,40 @@ static void __rtl_set_wol(struct r8152 *\n \t\tdevice_set_wakeup_enable(&tp->udev->dev, false);\n }\n \n+static void r8153_mac_clk_speed_down(struct r8152 *tp, bool enable)\n+{\n+\tu32 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2);\n+\n+\t/* MAC clock speed down */\n+\tif (enable)\n+\t\tocp_data |= MAC_CLK_SPDWN_EN;\n+\telse\n+\t\tocp_data &= ~MAC_CLK_SPDWN_EN;\n+\n+\tocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data);\n+}\n+\n+static void r8156_mac_clk_spd(struct r8152 *tp, bool enable)\n+{\n+\tu32 ocp_data;\n+\n+\t/* MAC clock speed down */\n+\tif (enable) {\n+\t\t/* aldps_spdwn_ratio, tp10_spdwn_ratio */\n+\t\tocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL,\n+\t\t\t       0x0403);\n+\n+\t\tocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2);\n+\t\tocp_data &= ~EEE_SPDWN_RATIO_MASK;\n+\t\tocp_data |= MAC_CLK_SPDWN_EN | 0x03; /* eee_spdwn_ratio */\n+\t\tocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data);\n+\t} else {\n+\t\tocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2);\n+\t\tocp_data &= ~MAC_CLK_SPDWN_EN;\n+\t\tocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data);\n+\t}\n+}\n+\n static void r8153_u1u2en(struct r8152 *tp, bool enable)\n {\n \tu8 u1u2[8];\n@@ -3111,6 +3341,9 @@ static void r8153b_ups_flags(struct r815\n \tif (tp->ups_info.eee_cmod_lv)\n \t\tups_flags |= UPS_FLAGS_EEE_CMOD_LV_EN;\n \n+\tif (tp->ups_info.r_tune)\n+\t\tups_flags |= UPS_FLAGS_R_TUNE;\n+\n \tif (tp->ups_info._10m_ckdiv)\n \t\tups_flags |= UPS_FLAGS_EN_10M_CKDIV;\n \n@@ -3161,6 +3394,88 @@ static void r8153b_ups_flags(struct r815\n \tocp_write_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS, ups_flags);\n }\n \n+static void r8156_ups_flags(struct r8152 *tp)\n+{\n+\tu32 ups_flags = 0;\n+\n+\tif (tp->ups_info.green)\n+\t\tups_flags |= UPS_FLAGS_EN_GREEN;\n+\n+\tif (tp->ups_info.aldps)\n+\t\tups_flags |= UPS_FLAGS_EN_ALDPS;\n+\n+\tif (tp->ups_info.eee)\n+\t\tups_flags |= UPS_FLAGS_EN_EEE;\n+\n+\tif (tp->ups_info.flow_control)\n+\t\tups_flags |= UPS_FLAGS_EN_FLOW_CTR;\n+\n+\tif (tp->ups_info.eee_ckdiv)\n+\t\tups_flags |= UPS_FLAGS_EN_EEE_CKDIV;\n+\n+\tif (tp->ups_info._10m_ckdiv)\n+\t\tups_flags |= UPS_FLAGS_EN_10M_CKDIV;\n+\n+\tif (tp->ups_info.eee_plloff_100)\n+\t\tups_flags |= UPS_FLAGS_EEE_PLLOFF_100;\n+\n+\tif (tp->ups_info.eee_plloff_giga)\n+\t\tups_flags |= UPS_FLAGS_EEE_PLLOFF_GIGA;\n+\n+\tif (tp->ups_info._250m_ckdiv)\n+\t\tups_flags |= UPS_FLAGS_250M_CKDIV;\n+\n+\tswitch (tp->ups_info.speed_duplex) {\n+\tcase FORCE_10M_HALF:\n+\t\tups_flags |= ups_flags_speed(0);\n+\t\tbreak;\n+\tcase FORCE_10M_FULL:\n+\t\tups_flags |= ups_flags_speed(1);\n+\t\tbreak;\n+\tcase FORCE_100M_HALF:\n+\t\tups_flags |= ups_flags_speed(2);\n+\t\tbreak;\n+\tcase FORCE_100M_FULL:\n+\t\tups_flags |= ups_flags_speed(3);\n+\t\tbreak;\n+\tcase NWAY_10M_HALF:\n+\t\tups_flags |= ups_flags_speed(4);\n+\t\tbreak;\n+\tcase NWAY_10M_FULL:\n+\t\tups_flags |= ups_flags_speed(5);\n+\t\tbreak;\n+\tcase NWAY_100M_HALF:\n+\t\tups_flags |= ups_flags_speed(6);\n+\t\tbreak;\n+\tcase NWAY_100M_FULL:\n+\t\tups_flags |= ups_flags_speed(7);\n+\t\tbreak;\n+\tcase NWAY_1000M_FULL:\n+\t\tups_flags |= ups_flags_speed(8);\n+\t\tbreak;\n+\tcase NWAY_2500M_FULL:\n+\t\tups_flags |= ups_flags_speed(9);\n+\t\tbreak;\n+\tdefault:\n+\t\tbreak;\n+\t}\n+\n+\tswitch (tp->ups_info.lite_mode) {\n+\tcase 1:\n+\t\tups_flags |= 0 << 5;\n+\t\tbreak;\n+\tcase 2:\n+\t\tups_flags |= 2 << 5;\n+\t\tbreak;\n+\tcase 0:\n+\tdefault:\n+\t\tups_flags |= 1 << 5;\n+\t\tbreak;\n+\t}\n+\n+\tocp_write_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS, ups_flags);\n+}\n+\n static void rtl_green_en(struct r8152 *tp, bool enable)\n {\n \tu16 data;\n@@ -3224,16 +3539,16 @@ static void r8153b_ups_en(struct r8152 *\n \t\tocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN;\n \t\tocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);\n \n-\t\tocp_data = ocp_read_byte(tp, MCU_TYPE_USB, 0xcfff);\n-\t\tocp_data |= BIT(0);\n-\t\tocp_write_byte(tp, MCU_TYPE_USB, 0xcfff, ocp_data);\n+\t\tocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);\n+\t\tocp_data |= UPS_FORCE_PWR_DOWN;\n+\t\tocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);\n \t} else {\n \t\tocp_data &= ~(UPS_EN | USP_PREWAKE);\n \t\tocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);\n \n-\t\tocp_data = ocp_read_byte(tp, MCU_TYPE_USB, 0xcfff);\n-\t\tocp_data &= ~BIT(0);\n-\t\tocp_write_byte(tp, MCU_TYPE_USB, 0xcfff, ocp_data);\n+\t\tocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);\n+\t\tocp_data &= ~UPS_FORCE_PWR_DOWN;\n+\t\tocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);\n \n \t\tif (ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0) & PCUT_STATUS) {\n \t\t\tint i;\n@@ -3253,6 +3568,95 @@ static void r8153b_ups_en(struct r8152 *\n \t}\n }\n \n+static void r8153c_ups_en(struct r8152 *tp, bool enable)\n+{\n+\tu32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT);\n+\n+\tif (enable) {\n+\t\tr8153b_ups_flags(tp);\n+\n+\t\tocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN;\n+\t\tocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);\n+\n+\t\tocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);\n+\t\tocp_data |= UPS_FORCE_PWR_DOWN;\n+\t\tocp_data &= ~BIT(7);\n+\t\tocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);\n+\t} else {\n+\t\tocp_data &= ~(UPS_EN | USP_PREWAKE);\n+\t\tocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);\n+\n+\t\tocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);\n+\t\tocp_data &= ~UPS_FORCE_PWR_DOWN;\n+\t\tocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);\n+\n+\t\tif (ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0) & PCUT_STATUS) {\n+\t\t\tint i;\n+\n+\t\t\tfor (i = 0; i < 500; i++) {\n+\t\t\t\tif (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &\n+\t\t\t\t    AUTOLOAD_DONE)\n+\t\t\t\t\tbreak;\n+\t\t\t\tmsleep(20);\n+\t\t\t}\n+\n+\t\t\ttp->rtl_ops.hw_phy_cfg(tp);\n+\n+\t\t\trtl8152_set_speed(tp, tp->autoneg, tp->speed,\n+\t\t\t\t\t  tp->duplex, tp->advertising);\n+\t\t}\n+\n+\t\tocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);\n+\n+\t\tocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);\n+\t\tocp_data |= BIT(8);\n+\t\tocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);\n+\n+\t\tocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);\n+\t}\n+}\n+\n+static void r8156_ups_en(struct r8152 *tp, bool enable)\n+{\n+\tu32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT);\n+\n+\tif (enable) {\n+\t\tr8156_ups_flags(tp);\n+\n+\t\tocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN;\n+\t\tocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);\n+\n+\t\tocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);\n+\t\tocp_data |= UPS_FORCE_PWR_DOWN;\n+\t\tocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);\n+\n+\t\tswitch (tp->version) {\n+\t\tcase RTL_VER_13:\n+\t\tcase RTL_VER_15:\n+\t\t\tocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPHY_XTAL);\n+\t\t\tocp_data &= ~OOBS_POLLING;\n+\t\t\tocp_write_byte(tp, MCU_TYPE_USB, USB_UPHY_XTAL, ocp_data);\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tbreak;\n+\t\t}\n+\t} else {\n+\t\tocp_data &= ~(UPS_EN | USP_PREWAKE);\n+\t\tocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);\n+\n+\t\tocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);\n+\t\tocp_data &= ~UPS_FORCE_PWR_DOWN;\n+\t\tocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);\n+\n+\t\tif (ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0) & PCUT_STATUS) {\n+\t\t\ttp->rtl_ops.hw_phy_cfg(tp);\n+\n+\t\t\trtl8152_set_speed(tp, tp->autoneg, tp->speed,\n+\t\t\t\t\t  tp->duplex, tp->advertising);\n+\t\t}\n+\t}\n+}\n+\n static void r8153_power_cut_en(struct r8152 *tp, bool enable)\n {\n \tu32 ocp_data;\n@@ -3382,6 +3786,38 @@ static void rtl8153b_runtime_enable(stru\n \t}\n }\n \n+static void rtl8153c_runtime_enable(struct r8152 *tp, bool enable)\n+{\n+\tif (enable) {\n+\t\tr8153_queue_wake(tp, true);\n+\t\tr8153b_u1u2en(tp, false);\n+\t\tr8153_u2p3en(tp, false);\n+\t\trtl_runtime_suspend_enable(tp, true);\n+\t\tr8153c_ups_en(tp, true);\n+\t} else {\n+\t\tr8153c_ups_en(tp, false);\n+\t\tr8153_queue_wake(tp, false);\n+\t\trtl_runtime_suspend_enable(tp, false);\n+\t\tr8153b_u1u2en(tp, true);\n+\t}\n+}\n+\n+static void rtl8156_runtime_enable(struct r8152 *tp, bool enable)\n+{\n+\tif (enable) {\n+\t\tr8153_queue_wake(tp, true);\n+\t\tr8153b_u1u2en(tp, false);\n+\t\tr8153_u2p3en(tp, false);\n+\t\trtl_runtime_suspend_enable(tp, true);\n+\t} else {\n+\t\tr8153_queue_wake(tp, false);\n+\t\trtl_runtime_suspend_enable(tp, false);\n+\t\tr8153_u2p3en(tp, true);\n+\t\tif (tp->udev->speed >= USB_SPEED_SUPER)\n+\t\t\tr8153b_u1u2en(tp, true);\n+\t}\n+}\n+\n static void r8153_teredo_off(struct r8152 *tp)\n {\n \tu32 ocp_data;\n@@ -3402,14 +3838,19 @@ static void r8153_teredo_off(struct r815\n \n \tcase RTL_VER_08:\n \tcase RTL_VER_09:\n+\tcase RTL_TEST_01:\n+\tcase RTL_VER_10:\n+\tcase RTL_VER_11:\n+\tcase RTL_VER_12:\n+\tcase RTL_VER_13:\n+\tcase RTL_VER_14:\n+\tcase RTL_VER_15:\n+\tdefault:\n \t\t/* The bit 0 ~ 7 are relative with teredo settings. They are\n \t\t * W1C (write 1 to clear), so set all 1 to disable it.\n \t\t */\n \t\tocp_write_byte(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, 0xff);\n \t\tbreak;\n-\n-\tdefault:\n-\t\tbreak;\n \t}\n \n \tocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE);\n@@ -3444,6 +3885,12 @@ static void rtl_clear_bp(struct r8152 *t\n \t\tbreak;\n \tcase RTL_VER_08:\n \tcase RTL_VER_09:\n+\tcase RTL_VER_10:\n+\tcase RTL_VER_11:\n+\tcase RTL_VER_12:\n+\tcase RTL_VER_13:\n+\tcase RTL_VER_14:\n+\tcase RTL_VER_15:\n \tdefault:\n \t\tif (type == MCU_TYPE_USB) {\n \t\t\tocp_write_word(tp, MCU_TYPE_USB, USB_BP2_EN, 0);\n@@ -3653,6 +4100,11 @@ static bool rtl8152_is_fw_mac_ok(struct\n \t\tcase RTL_VER_06:\n \t\tcase RTL_VER_08:\n \t\tcase RTL_VER_09:\n+\t\tcase RTL_VER_11:\n+\t\tcase RTL_VER_12:\n+\t\tcase RTL_VER_13:\n+\t\tcase RTL_VER_14:\n+\t\tcase RTL_VER_15:\n \t\t\tfw_reg = 0xf800;\n \t\t\tbp_ba_addr = PLA_BP_BA;\n \t\t\tbp_en_addr = PLA_BP_EN;\n@@ -3676,6 +4128,11 @@ static bool rtl8152_is_fw_mac_ok(struct\n \t\t\tbreak;\n \t\tcase RTL_VER_08:\n \t\tcase RTL_VER_09:\n+\t\tcase RTL_VER_11:\n+\t\tcase RTL_VER_12:\n+\t\tcase RTL_VER_13:\n+\t\tcase RTL_VER_14:\n+\t\tcase RTL_VER_15:\n \t\t\tfw_reg = 0xe600;\n \t\t\tbp_ba_addr = USB_BP_BA;\n \t\t\tbp_en_addr = USB_BP2_EN;\n@@ -4215,6 +4672,22 @@ static void r8153_eee_en(struct r8152 *t\n \ttp->ups_info.eee = enable;\n }\n \n+static void r8156_eee_en(struct r8152 *tp, bool enable)\n+{\n+\tu16 config;\n+\n+\tr8153_eee_en(tp, enable);\n+\n+\tconfig = ocp_reg_read(tp, OCP_EEE_ADV2);\n+\n+\tif (enable)\n+\t\tconfig |= MDIO_EEE_2_5GT;\n+\telse\n+\t\tconfig &= ~MDIO_EEE_2_5GT;\n+\n+\tocp_reg_write(tp, OCP_EEE_ADV2, config);\n+}\n+\n static void rtl_eee_enable(struct r8152 *tp, bool enable)\n {\n \tswitch (tp->version) {\n@@ -4236,6 +4709,7 @@ static void rtl_eee_enable(struct r8152\n \tcase RTL_VER_06:\n \tcase RTL_VER_08:\n \tcase RTL_VER_09:\n+\tcase RTL_VER_14:\n \t\tif (enable) {\n \t\t\tr8153_eee_en(tp, true);\n \t\t\tocp_reg_write(tp, OCP_EEE_ADV, tp->eee_adv);\n@@ -4244,6 +4718,19 @@ static void rtl_eee_enable(struct r8152\n \t\t\tocp_reg_write(tp, OCP_EEE_ADV, 0);\n \t\t}\n \t\tbreak;\n+\tcase RTL_VER_10:\n+\tcase RTL_VER_11:\n+\tcase RTL_VER_12:\n+\tcase RTL_VER_13:\n+\tcase RTL_VER_15:\n+\t\tif (enable) {\n+\t\t\tr8156_eee_en(tp, true);\n+\t\t\tocp_reg_write(tp, OCP_EEE_ADV, tp->eee_adv);\n+\t\t} else {\n+\t\t\tr8156_eee_en(tp, false);\n+\t\t\tocp_reg_write(tp, OCP_EEE_ADV, 0);\n+\t\t}\n+\t\tbreak;\n \tdefault:\n \t\tbreak;\n \t}\n@@ -4290,6 +4777,20 @@ static void wait_oob_link_list_ready(str\n \t}\n }\n \n+static void r8156b_wait_loading_flash(struct r8152 *tp)\n+{\n+\tif ((ocp_read_word(tp, MCU_TYPE_PLA, PLA_GPHY_CTRL) & GPHY_FLASH) &&\n+\t    !(ocp_read_word(tp, MCU_TYPE_USB, USB_GPHY_CTRL) & BYPASS_FLASH)) {\n+\t\tint i;\n+\n+\t\tfor (i = 0; i < 100; i++) {\n+\t\t\tif (ocp_read_word(tp, MCU_TYPE_USB, USB_GPHY_CTRL) & GPHY_PATCH_DONE)\n+\t\t\t\tbreak;\n+\t\t\tusleep_range(1000, 2000);\n+\t\t}\n+\t}\n+}\n+\n static void r8152b_exit_oob(struct r8152 *tp)\n {\n \tu32 ocp_data;\n@@ -4340,7 +4841,7 @@ static void r8152b_exit_oob(struct r8152\n \t}\n \n \t/* TX share fifo free credit full threshold */\n-\tocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL);\n+\tocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);\n \n \tocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);\n \tocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH);\n@@ -4517,6 +5018,21 @@ static int r8153b_post_firmware_1(struct\n \treturn 0;\n }\n \n+static int r8153c_post_firmware_1(struct r8152 *tp)\n+{\n+\tu32 ocp_data;\n+\n+\tocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_CTRL);\n+\tocp_data |= FLOW_CTRL_PATCH_2;\n+\tocp_write_word(tp, MCU_TYPE_USB, USB_FW_CTRL, ocp_data);\n+\n+\tocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);\n+\tocp_data |= FC_PATCH_TASK;\n+\tocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);\n+\n+\treturn 0;\n+}\n+\n static void r8153_aldps_en(struct r8152 *tp, bool enable)\n {\n \tu16 data;\n@@ -4719,6 +5235,13 @@ static void r8153b_hw_phy_cfg(struct r81\n \tset_bit(PHY_RESET, &tp->flags);\n }\n \n+static void r8153c_hw_phy_cfg(struct r8152 *tp)\n+{\n+\tr8153b_hw_phy_cfg(tp);\n+\n+\ttp->ups_info.r_tune = true;\n+}\n+\n static void rtl8153_change_mtu(struct r8152 *tp)\n {\n \tocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, mtu_to_size(tp->netdev->mtu));\n@@ -4806,6 +5329,7 @@ static void r8153_enter_oob(struct r8152\n \n \tcase RTL_VER_08:\n \tcase RTL_VER_09:\n+\tcase RTL_VER_14:\n \t\t/* Clear teredo wake event. bit[15:8] is the teredo wakeup\n \t\t * type. Set it to zero. bits[7:0] are the W1C bits about\n \t\t * the events. Set them to all 1 to clear them.\n@@ -4842,6 +5366,96 @@ static void rtl8153_disable(struct r8152\n \tr8153_aldps_en(tp, true);\n }\n \n+static int rtl8156_enable(struct r8152 *tp)\n+{\n+\tu32 ocp_data;\n+\tu16 speed;\n+\n+\tif (test_bit(RTL8152_UNPLUG, &tp->flags))\n+\t\treturn -ENODEV;\n+\n+\tset_tx_qlen(tp);\n+\trtl_set_eee_plus(tp);\n+\tr8153_set_rx_early_timeout(tp);\n+\tr8153_set_rx_early_size(tp);\n+\n+\tspeed = rtl8152_get_speed(tp);\n+\trtl_set_ifg(tp, speed);\n+\n+\tocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);\n+\tif (speed & _2500bps)\n+\t\tocp_data &= ~IDLE_SPDWN_EN;\n+\telse\n+\t\tocp_data |= IDLE_SPDWN_EN;\n+\tocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data);\n+\n+\tif (speed & _1000bps)\n+\t\tocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_TXTWSYS, 0x11);\n+\telse if (speed & _500bps)\n+\t\tocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_TXTWSYS, 0x3d);\n+\n+\tif (tp->udev->speed == USB_SPEED_HIGH) {\n+\t\t/* USB 0xb45e[3:0] l1_nyet_hird */\n+\t\tocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_L1_CTRL);\n+\t\tocp_data &= ~0xf;\n+\t\tif (is_flow_control(speed))\n+\t\t\tocp_data |= 0xf;\n+\t\telse\n+\t\t\tocp_data |= 0x1;\n+\t\tocp_write_word(tp, MCU_TYPE_USB, USB_L1_CTRL, ocp_data);\n+\t}\n+\n+\treturn rtl_enable(tp);\n+}\n+\n+static int rtl8156b_enable(struct r8152 *tp)\n+{\n+\tu32 ocp_data;\n+\tu16 speed;\n+\n+\tif (test_bit(RTL8152_UNPLUG, &tp->flags))\n+\t\treturn -ENODEV;\n+\n+\tset_tx_qlen(tp);\n+\trtl_set_eee_plus(tp);\n+\n+\tocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_RX_AGGR_NUM);\n+\tocp_data &= ~RX_AGGR_NUM_MASK;\n+\tocp_write_word(tp, MCU_TYPE_USB, USB_RX_AGGR_NUM, ocp_data);\n+\n+\tr8153_set_rx_early_timeout(tp);\n+\tr8153_set_rx_early_size(tp);\n+\n+\tspeed = rtl8152_get_speed(tp);\n+\trtl_set_ifg(tp, speed);\n+\n+\tocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);\n+\tif (speed & _2500bps)\n+\t\tocp_data &= ~IDLE_SPDWN_EN;\n+\telse\n+\t\tocp_data |= IDLE_SPDWN_EN;\n+\tocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data);\n+\n+\tif (tp->udev->speed == USB_SPEED_HIGH) {\n+\t\tocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_L1_CTRL);\n+\t\tocp_data &= ~0xf;\n+\t\tif (is_flow_control(speed))\n+\t\t\tocp_data |= 0xf;\n+\t\telse\n+\t\t\tocp_data |= 0x1;\n+\t\tocp_write_word(tp, MCU_TYPE_USB, USB_L1_CTRL, ocp_data);\n+\t}\n+\n+\tocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);\n+\tocp_data &= ~FC_PATCH_TASK;\n+\tocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);\n+\tusleep_range(1000, 2000);\n+\tocp_data |= FC_PATCH_TASK;\n+\tocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);\n+\n+\treturn rtl_enable(tp);\n+}\n+\n static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u32 speed, u8 duplex,\n \t\t\t     u32 advertising)\n {\n@@ -4890,58 +5504,73 @@ static int rtl8152_set_speed(struct r815\n \n \t\ttp->mii.force_media = 1;\n \t} else {\n-\t\tu16 anar, tmp1;\n+\t\tu16 orig, new1;\n \t\tu32 support;\n \n \t\tsupport = RTL_ADVERTISED_10_HALF | RTL_ADVERTISED_10_FULL |\n \t\t\t  RTL_ADVERTISED_100_HALF | RTL_ADVERTISED_100_FULL;\n \n-\t\tif (tp->mii.supports_gmii)\n+\t\tif (tp->mii.supports_gmii) {\n \t\t\tsupport |= RTL_ADVERTISED_1000_FULL;\n \n+\t\t\tif (tp->support_2500full)\n+\t\t\t\tsupport |= RTL_ADVERTISED_2500_FULL;\n+\t\t}\n+\n \t\tif (!(advertising & support))\n \t\t\treturn -EINVAL;\n \n-\t\tanar = r8152_mdio_read(tp, MII_ADVERTISE);\n-\t\ttmp1 = anar & ~(ADVERTISE_10HALF | ADVERTISE_10FULL |\n+\t\torig = r8152_mdio_read(tp, MII_ADVERTISE);\n+\t\tnew1 = orig & ~(ADVERTISE_10HALF | ADVERTISE_10FULL |\n \t\t\t\tADVERTISE_100HALF | ADVERTISE_100FULL);\n \t\tif (advertising & RTL_ADVERTISED_10_HALF) {\n-\t\t\ttmp1 |= ADVERTISE_10HALF;\n+\t\t\tnew1 |= ADVERTISE_10HALF;\n \t\t\ttp->ups_info.speed_duplex = NWAY_10M_HALF;\n \t\t}\n \t\tif (advertising & RTL_ADVERTISED_10_FULL) {\n-\t\t\ttmp1 |= ADVERTISE_10FULL;\n+\t\t\tnew1 |= ADVERTISE_10FULL;\n \t\t\ttp->ups_info.speed_duplex = NWAY_10M_FULL;\n \t\t}\n \n \t\tif (advertising & RTL_ADVERTISED_100_HALF) {\n-\t\t\ttmp1 |= ADVERTISE_100HALF;\n+\t\t\tnew1 |= ADVERTISE_100HALF;\n \t\t\ttp->ups_info.speed_duplex = NWAY_100M_HALF;\n \t\t}\n \t\tif (advertising & RTL_ADVERTISED_100_FULL) {\n-\t\t\ttmp1 |= ADVERTISE_100FULL;\n+\t\t\tnew1 |= ADVERTISE_100FULL;\n \t\t\ttp->ups_info.speed_duplex = NWAY_100M_FULL;\n \t\t}\n \n-\t\tif (anar != tmp1) {\n-\t\t\tr8152_mdio_write(tp, MII_ADVERTISE, tmp1);\n-\t\t\ttp->mii.advertising = tmp1;\n+\t\tif (orig != new1) {\n+\t\t\tr8152_mdio_write(tp, MII_ADVERTISE, new1);\n+\t\t\ttp->mii.advertising = new1;\n \t\t}\n \n \t\tif (tp->mii.supports_gmii) {\n-\t\t\tu16 gbcr;\n-\n-\t\t\tgbcr = r8152_mdio_read(tp, MII_CTRL1000);\n-\t\t\ttmp1 = gbcr & ~(ADVERTISE_1000FULL |\n+\t\t\torig = r8152_mdio_read(tp, MII_CTRL1000);\n+\t\t\tnew1 = orig & ~(ADVERTISE_1000FULL |\n \t\t\t\t\tADVERTISE_1000HALF);\n \n \t\t\tif (advertising & RTL_ADVERTISED_1000_FULL) {\n-\t\t\t\ttmp1 |= ADVERTISE_1000FULL;\n+\t\t\t\tnew1 |= ADVERTISE_1000FULL;\n \t\t\t\ttp->ups_info.speed_duplex = NWAY_1000M_FULL;\n \t\t\t}\n \n-\t\t\tif (gbcr != tmp1)\n-\t\t\t\tr8152_mdio_write(tp, MII_CTRL1000, tmp1);\n+\t\t\tif (orig != new1)\n+\t\t\t\tr8152_mdio_write(tp, MII_CTRL1000, new1);\n+\t\t}\n+\n+\t\tif (tp->support_2500full) {\n+\t\t\torig = ocp_reg_read(tp, OCP_10GBT_CTRL);\n+\t\t\tnew1 = orig & ~MDIO_AN_10GBT_CTRL_ADV2_5G;\n+\n+\t\t\tif (advertising & RTL_ADVERTISED_2500_FULL) {\n+\t\t\t\tnew1 |= MDIO_AN_10GBT_CTRL_ADV2_5G;\n+\t\t\t\ttp->ups_info.speed_duplex = NWAY_2500M_FULL;\n+\t\t\t}\n+\n+\t\t\tif (orig != new1)\n+\t\t\t\tocp_reg_write(tp, OCP_10GBT_CTRL, new1);\n \t\t}\n \n \t\tbmcr = BMCR_ANENABLE | BMCR_ANRESTART;\n@@ -5097,6 +5726,253 @@ static void rtl8153b_down(struct r8152 *\n \tr8153_aldps_en(tp, true);\n }\n \n+static void rtl8153c_change_mtu(struct r8152 *tp)\n+{\n+\tocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, mtu_to_size(tp->netdev->mtu));\n+\tocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, 10 * 1024 / 64);\n+\n+\tocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, 512 / 64);\n+\n+\t/* Adjust the tx fifo free credit full threshold, otherwise\n+\t * the fifo would be too small to send a jumbo frame packet.\n+\t */\n+\tif (tp->netdev->mtu < 8000)\n+\t\tocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_FULL, 2048 / 8);\n+\telse\n+\t\tocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_FULL, 900 / 8);\n+}\n+\n+static void rtl8153c_up(struct r8152 *tp)\n+{\n+\tu32 ocp_data;\n+\n+\tif (test_bit(RTL8152_UNPLUG, &tp->flags))\n+\t\treturn;\n+\n+\tr8153b_u1u2en(tp, false);\n+\tr8153_u2p3en(tp, false);\n+\tr8153_aldps_en(tp, false);\n+\n+\trxdy_gated_en(tp, true);\n+\tr8153_teredo_off(tp);\n+\n+\tocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);\n+\tocp_data &= ~RCR_ACPT_ALL;\n+\tocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);\n+\n+\trtl8152_nic_reset(tp);\n+\trtl_reset_bmu(tp);\n+\n+\tocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);\n+\tocp_data &= ~NOW_IS_OOB;\n+\tocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);\n+\n+\tocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);\n+\tocp_data &= ~MCU_BORW_EN;\n+\tocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);\n+\n+\twait_oob_link_list_ready(tp);\n+\n+\tocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);\n+\tocp_data |= RE_INIT_LL;\n+\tocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);\n+\n+\twait_oob_link_list_ready(tp);\n+\n+\trtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);\n+\n+\trtl8153c_change_mtu(tp);\n+\n+\trtl8152_nic_reset(tp);\n+\n+\t/* rx share fifo credit full threshold */\n+\tocp_write_byte(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, 0x02);\n+\tocp_write_byte(tp, MCU_TYPE_PLA, PLA_RXFIFO_FULL, 0x08);\n+\tocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);\n+\tocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);\n+\n+\tocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_B);\n+\n+\tocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);\n+\n+\tocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);\n+\tocp_data |= BIT(8);\n+\tocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);\n+\n+\tocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);\n+\n+\tocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);\n+\tocp_data &= ~PLA_MCU_SPDWN_EN;\n+\tocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);\n+\n+\tr8153_aldps_en(tp, true);\n+\tr8153b_u1u2en(tp, true);\n+}\n+\n+static inline u32 fc_pause_on_auto(struct r8152 *tp)\n+{\n+\treturn (ALIGN(mtu_to_size(tp->netdev->mtu), 1024) + 6 * 1024);\n+}\n+\n+static inline u32 fc_pause_off_auto(struct r8152 *tp)\n+{\n+\treturn (ALIGN(mtu_to_size(tp->netdev->mtu), 1024) + 14 * 1024);\n+}\n+\n+static void r8156_fc_parameter(struct r8152 *tp)\n+{\n+\tu32 pause_on = tp->fc_pause_on ? tp->fc_pause_on : fc_pause_on_auto(tp);\n+\tu32 pause_off = tp->fc_pause_off ? tp->fc_pause_off : fc_pause_off_auto(tp);\n+\n+\tswitch (tp->version) {\n+\tcase RTL_VER_10:\n+\tcase RTL_VER_11:\n+\t\tocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_FULL, pause_on / 8);\n+\t\tocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_EMPTY, pause_off / 8);\n+\t\tbreak;\n+\tcase RTL_VER_12:\n+\tcase RTL_VER_13:\n+\tcase RTL_VER_15:\n+\t\tocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_FULL, pause_on / 16);\n+\t\tocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_EMPTY, pause_off / 16);\n+\t\tbreak;\n+\tdefault:\n+\t\tbreak;\n+\t}\n+}\n+\n+static void rtl8156_change_mtu(struct r8152 *tp)\n+{\n+\tu32 rx_max_size = mtu_to_size(tp->netdev->mtu);\n+\n+\tocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, rx_max_size);\n+\tocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);\n+\tr8156_fc_parameter(tp);\n+\n+\t/* TX share fifo free credit full threshold */\n+\tocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, 512 / 64);\n+\tocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_FULL,\n+\t\t       ALIGN(rx_max_size + sizeof(struct tx_desc), 1024) / 16);\n+}\n+\n+static void rtl8156_up(struct r8152 *tp)\n+{\n+\tu32 ocp_data;\n+\n+\tif (test_bit(RTL8152_UNPLUG, &tp->flags))\n+\t\treturn;\n+\n+\tr8153b_u1u2en(tp, false);\n+\tr8153_u2p3en(tp, false);\n+\tr8153_aldps_en(tp, false);\n+\n+\trxdy_gated_en(tp, true);\n+\tr8153_teredo_off(tp);\n+\n+\tocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);\n+\tocp_data &= ~RCR_ACPT_ALL;\n+\tocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);\n+\n+\trtl8152_nic_reset(tp);\n+\trtl_reset_bmu(tp);\n+\n+\tocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);\n+\tocp_data &= ~NOW_IS_OOB;\n+\tocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);\n+\n+\tocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);\n+\tocp_data &= ~MCU_BORW_EN;\n+\tocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);\n+\n+\trtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);\n+\n+\trtl8156_change_mtu(tp);\n+\n+\tswitch (tp->version) {\n+\tcase RTL_TEST_01:\n+\tcase RTL_VER_10:\n+\tcase RTL_VER_11:\n+\t\tocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_BMU_CONFIG);\n+\t\tocp_data |= ACT_ODMA;\n+\t\tocp_write_word(tp, MCU_TYPE_USB, USB_BMU_CONFIG, ocp_data);\n+\t\tbreak;\n+\tdefault:\n+\t\tbreak;\n+\t}\n+\n+\t/* share FIFO settings */\n+\tocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_FULL);\n+\tocp_data &= ~RXFIFO_FULL_MASK;\n+\tocp_data |= 0x08;\n+\tocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_FULL, ocp_data);\n+\n+\tocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);\n+\tocp_data &= ~PLA_MCU_SPDWN_EN;\n+\tocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);\n+\n+\tocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION);\n+\tocp_data &= ~(RG_PWRDN_EN | ALL_SPEED_OFF);\n+\tocp_write_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION, ocp_data);\n+\n+\tocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, 0x00600400);\n+\n+\tif (tp->saved_wolopts != __rtl_get_wol(tp)) {\n+\t\tnetif_warn(tp, ifup, tp->netdev, \"wol setting is changed\\n\");\n+\t\t__rtl_set_wol(tp, tp->saved_wolopts);\n+\t}\n+\n+\tr8153_aldps_en(tp, true);\n+\tr8153_u2p3en(tp, true);\n+\n+\tif (tp->udev->speed >= USB_SPEED_SUPER)\n+\t\tr8153b_u1u2en(tp, true);\n+}\n+\n+static void rtl8156_down(struct r8152 *tp)\n+{\n+\tu32 ocp_data;\n+\n+\tif (test_bit(RTL8152_UNPLUG, &tp->flags)) {\n+\t\trtl_drop_queued_tx(tp);\n+\t\treturn;\n+\t}\n+\n+\tocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);\n+\tocp_data |= PLA_MCU_SPDWN_EN;\n+\tocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);\n+\n+\tr8153b_u1u2en(tp, false);\n+\tr8153_u2p3en(tp, false);\n+\tr8153b_power_cut_en(tp, false);\n+\tr8153_aldps_en(tp, false);\n+\n+\tocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);\n+\tocp_data &= ~NOW_IS_OOB;\n+\tocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);\n+\n+\trtl_disable(tp);\n+\trtl_reset_bmu(tp);\n+\n+\t/* Clear teredo wake event. bit[15:8] is the teredo wakeup\n+\t * type. Set it to zero. bits[7:0] are the W1C bits about\n+\t * the events. Set them to all 1 to clear them.\n+\t */\n+\tocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_WAKE_BASE, 0x00ff);\n+\n+\tocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);\n+\tocp_data |= NOW_IS_OOB;\n+\tocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);\n+\n+\trtl_rx_vlan_en(tp, true);\n+\trxdy_gated_en(tp, false);\n+\n+\tocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);\n+\tocp_data |= RCR_APM | RCR_AM | RCR_AB;\n+\tocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);\n+\n+\tr8153_aldps_en(tp, true);\n+}\n+\n static bool rtl8152_in_nway(struct r8152 *tp)\n {\n \tu16 nway_state;\n@@ -5127,7 +6003,7 @@ static void set_carrier(struct r8152 *tp\n {\n \tstruct net_device *netdev = tp->netdev;\n \tstruct napi_struct *napi = &tp->napi;\n-\tu8 speed;\n+\tu16 speed;\n \n \tspeed = rtl8152_get_speed(tp);\n \n@@ -5140,7 +6016,7 @@ static void set_carrier(struct r8152 *tp\n \t\t\trtl_start_rx(tp);\n \t\t\tclear_bit(RTL8152_SET_RX_MODE, &tp->flags);\n \t\t\t_rtl8152_set_rx_mode(netdev);\n-\t\t\tnapi_enable(&tp->napi);\n+\t\t\tnapi_enable(napi);\n \t\t\tnetif_wake_queue(netdev);\n \t\t\tnetif_info(tp, link, netdev, \"carrier on\\n\");\n \t\t} else if (netif_queue_stopped(netdev) &&\n@@ -5502,14 +6378,9 @@ static void r8153_init(struct r8152 *tp)\n \n \tocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001);\n \n-\t/* MAC clock speed down */\n-\tocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, 0);\n-\tocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, 0);\n-\tocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, 0);\n-\tocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, 0);\n-\n \tr8153_power_cut_en(tp, false);\n \trtl_runtime_suspend_enable(tp, false);\n+\tr8153_mac_clk_speed_down(tp, false);\n \tr8153_u1u2en(tp, true);\n \tusb_enable_lpm(tp->udev);\n \n@@ -5600,9 +6471,7 @@ static void r8153b_init(struct r8152 *tp\n \tusb_enable_lpm(tp->udev);\n \n \t/* MAC clock speed down */\n-\tocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2);\n-\tocp_data |= MAC_CLK_SPDWN_EN;\n-\tocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data);\n+\tr8153_mac_clk_speed_down(tp, true);\n \n \tocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);\n \tocp_data &= ~PLA_MCU_SPDWN_EN;\n@@ -5629,6 +6498,1069 @@ static void r8153b_init(struct r8152 *tp\n \ttp->coalesce = 15000;\t/* 15 us */\n }\n \n+static void r8153c_init(struct r8152 *tp)\n+{\n+\tu32 ocp_data;\n+\tu16 data;\n+\tint i;\n+\n+\tif (test_bit(RTL8152_UNPLUG, &tp->flags))\n+\t\treturn;\n+\n+\tr8153b_u1u2en(tp, false);\n+\n+\t/* Disable spi_en */\n+\tocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);\n+\tocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);\n+\tocp_data &= ~BIT(3);\n+\tocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data);\n+\tocp_data = ocp_read_word(tp, MCU_TYPE_USB, 0xcbf0);\n+\tocp_data |= BIT(1);\n+\tocp_write_word(tp, MCU_TYPE_USB, 0xcbf0, ocp_data);\n+\n+\tfor (i = 0; i < 500; i++) {\n+\t\tif (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &\n+\t\t    AUTOLOAD_DONE)\n+\t\t\tbreak;\n+\n+\t\tmsleep(20);\n+\t\tif (test_bit(RTL8152_UNPLUG, &tp->flags))\n+\t\t\treturn;\n+\t}\n+\n+\tdata = r8153_phy_status(tp, 0);\n+\n+\tdata = r8152_mdio_read(tp, MII_BMCR);\n+\tif (data & BMCR_PDOWN) {\n+\t\tdata &= ~BMCR_PDOWN;\n+\t\tr8152_mdio_write(tp, MII_BMCR, data);\n+\t}\n+\n+\tdata = r8153_phy_status(tp, PHY_STAT_LAN_ON);\n+\n+\tr8153_u2p3en(tp, false);\n+\n+\t/* MSC timer = 0xfff * 8ms = 32760 ms */\n+\tocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff);\n+\n+\tr8153b_power_cut_en(tp, false);\n+\tr8153c_ups_en(tp, false);\n+\tr8153_queue_wake(tp, false);\n+\trtl_runtime_suspend_enable(tp, false);\n+\n+\tocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);\n+\tif (rtl8152_get_speed(tp) & LINK_STATUS)\n+\t\tocp_data |= CUR_LINK_OK;\n+\telse\n+\t\tocp_data &= ~CUR_LINK_OK;\n+\n+\tocp_data |= POLL_LINK_CHG;\n+\tocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);\n+\n+\tr8153b_u1u2en(tp, true);\n+\n+\tusb_enable_lpm(tp->udev);\n+\n+\t/* MAC clock speed down */\n+\tr8153_mac_clk_speed_down(tp, true);\n+\n+\tocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);\n+\tocp_data &= ~BIT(7);\n+\tocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);\n+\n+\tset_bit(GREEN_ETHERNET, &tp->flags);\n+\n+\t/* rx aggregation */\n+\tocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);\n+\tocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);\n+\tocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);\n+\n+\trtl_tally_reset(tp);\n+\n+\ttp->coalesce = 15000;\t/* 15 us */\n+}\n+\n+static void r8156_hw_phy_cfg(struct r8152 *tp)\n+{\n+\tu32 ocp_data;\n+\tu16 data;\n+\n+\tocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);\n+\tif (ocp_data & PCUT_STATUS) {\n+\t\tocp_data &= ~PCUT_STATUS;\n+\t\tocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);\n+\t}\n+\n+\tdata = r8153_phy_status(tp, 0);\n+\tswitch (data) {\n+\tcase PHY_STAT_EXT_INIT:\n+\t\trtl8152_apply_firmware(tp, true);\n+\n+\t\tdata = ocp_reg_read(tp, 0xa468);\n+\t\tdata &= ~(BIT(3) | BIT(1));\n+\t\tocp_reg_write(tp, 0xa468, data);\n+\t\tbreak;\n+\tcase PHY_STAT_LAN_ON:\n+\tcase PHY_STAT_PWRDN:\n+\tdefault:\n+\t\trtl8152_apply_firmware(tp, false);\n+\t\tbreak;\n+\t}\n+\n+\t/* disable ALDPS before updating the PHY parameters */\n+\tr8153_aldps_en(tp, false);\n+\n+\t/* disable EEE before updating the PHY parameters */\n+\trtl_eee_enable(tp, false);\n+\n+\tdata = r8153_phy_status(tp, PHY_STAT_LAN_ON);\n+\tWARN_ON_ONCE(data != PHY_STAT_LAN_ON);\n+\n+\tocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);\n+\tocp_data |= PFM_PWM_SWITCH;\n+\tocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);\n+\n+\tswitch (tp->version) {\n+\tcase RTL_VER_10:\n+\t\tdata = ocp_reg_read(tp, 0xad40);\n+\t\tdata &= ~0x3ff;\n+\t\tdata |= BIT(7) | BIT(2);\n+\t\tocp_reg_write(tp, 0xad40, data);\n+\n+\t\tdata = ocp_reg_read(tp, 0xad4e);\n+\t\tdata |= BIT(4);\n+\t\tocp_reg_write(tp, 0xad4e, data);\n+\t\tdata = ocp_reg_read(tp, 0xad16);\n+\t\tdata &= ~0x3ff;\n+\t\tdata |= 0x6;\n+\t\tocp_reg_write(tp, 0xad16, data);\n+\t\tdata = ocp_reg_read(tp, 0xad32);\n+\t\tdata &= ~0x3f;\n+\t\tdata |= 6;\n+\t\tocp_reg_write(tp, 0xad32, data);\n+\t\tdata = ocp_reg_read(tp, 0xac08);\n+\t\tdata &= ~(BIT(12) | BIT(8));\n+\t\tocp_reg_write(tp, 0xac08, data);\n+\t\tdata = ocp_reg_read(tp, 0xac8a);\n+\t\tdata |= BIT(12) | BIT(13) | BIT(14);\n+\t\tdata &= ~BIT(15);\n+\t\tocp_reg_write(tp, 0xac8a, data);\n+\t\tdata = ocp_reg_read(tp, 0xad18);\n+\t\tdata |= BIT(10);\n+\t\tocp_reg_write(tp, 0xad18, data);\n+\t\tdata = ocp_reg_read(tp, 0xad1a);\n+\t\tdata |= 0x3ff;\n+\t\tocp_reg_write(tp, 0xad1a, data);\n+\t\tdata = ocp_reg_read(tp, 0xad1c);\n+\t\tdata |= 0x3ff;\n+\t\tocp_reg_write(tp, 0xad1c, data);\n+\n+\t\tdata = sram_read(tp, 0x80ea);\n+\t\tdata &= ~0xff00;\n+\t\tdata |= 0xc400;\n+\t\tsram_write(tp, 0x80ea, data);\n+\t\tdata = sram_read(tp, 0x80eb);\n+\t\tdata &= ~0x0700;\n+\t\tdata |= 0x0300;\n+\t\tsram_write(tp, 0x80eb, data);\n+\t\tdata = sram_read(tp, 0x80f8);\n+\t\tdata &= ~0xff00;\n+\t\tdata |= 0x1c00;\n+\t\tsram_write(tp, 0x80f8, data);\n+\t\tdata = sram_read(tp, 0x80f1);\n+\t\tdata &= ~0xff00;\n+\t\tdata |= 0x3000;\n+\t\tsram_write(tp, 0x80f1, data);\n+\n+\t\tdata = sram_read(tp, 0x80fe);\n+\t\tdata &= ~0xff00;\n+\t\tdata |= 0xa500;\n+\t\tsram_write(tp, 0x80fe, data);\n+\t\tdata = sram_read(tp, 0x8102);\n+\t\tdata &= ~0xff00;\n+\t\tdata |= 0x5000;\n+\t\tsram_write(tp, 0x8102, data);\n+\t\tdata = sram_read(tp, 0x8015);\n+\t\tdata &= ~0xff00;\n+\t\tdata |= 0x3300;\n+\t\tsram_write(tp, 0x8015, data);\n+\t\tdata = sram_read(tp, 0x8100);\n+\t\tdata &= ~0xff00;\n+\t\tdata |= 0x7000;\n+\t\tsram_write(tp, 0x8100, data);\n+\t\tdata = sram_read(tp, 0x8014);\n+\t\tdata &= ~0xff00;\n+\t\tdata |= 0xf000;\n+\t\tsram_write(tp, 0x8014, data);\n+\t\tdata = sram_read(tp, 0x8016);\n+\t\tdata &= ~0xff00;\n+\t\tdata |= 0x6500;\n+\t\tsram_write(tp, 0x8016, data);\n+\t\tdata = sram_read(tp, 0x80dc);\n+\t\tdata &= ~0xff00;\n+\t\tdata |= 0xed00;\n+\t\tsram_write(tp, 0x80dc, data);\n+\t\tdata = sram_read(tp, 0x80df);\n+\t\tdata |= BIT(8);\n+\t\tsram_write(tp, 0x80df, data);\n+\t\tdata = sram_read(tp, 0x80e1);\n+\t\tdata &= ~BIT(8);\n+\t\tsram_write(tp, 0x80e1, data);\n+\n+\t\tdata = ocp_reg_read(tp, 0xbf06);\n+\t\tdata &= ~0x003f;\n+\t\tdata |= 0x0038;\n+\t\tocp_reg_write(tp, 0xbf06, data);\n+\n+\t\tsram_write(tp, 0x819f, 0xddb6);\n+\n+\t\tocp_reg_write(tp, 0xbc34, 0x5555);\n+\t\tdata = ocp_reg_read(tp, 0xbf0a);\n+\t\tdata &= ~0x0e00;\n+\t\tdata |= 0x0a00;\n+\t\tocp_reg_write(tp, 0xbf0a, data);\n+\n+\t\tdata = ocp_reg_read(tp, 0xbd2c);\n+\t\tdata &= ~BIT(13);\n+\t\tocp_reg_write(tp, 0xbd2c, data);\n+\t\tbreak;\n+\tcase RTL_VER_11:\n+\t\tdata = ocp_reg_read(tp, 0xad16);\n+\t\tdata |= 0x3ff;\n+\t\tocp_reg_write(tp, 0xad16, data);\n+\t\tdata = ocp_reg_read(tp, 0xad32);\n+\t\tdata &= ~0x3f;\n+\t\tdata |= 6;\n+\t\tocp_reg_write(tp, 0xad32, data);\n+\t\tdata = ocp_reg_read(tp, 0xac08);\n+\t\tdata &= ~(BIT(12) | BIT(8));\n+\t\tocp_reg_write(tp, 0xac08, data);\n+\t\tdata = ocp_reg_read(tp, 0xacc0);\n+\t\tdata &= ~0x3;\n+\t\tdata |= BIT(1);\n+\t\tocp_reg_write(tp, 0xacc0, data);\n+\t\tdata = ocp_reg_read(tp, 0xad40);\n+\t\tdata &= ~0xe7;\n+\t\tdata |= BIT(6) | BIT(2);\n+\t\tocp_reg_write(tp, 0xad40, data);\n+\t\tdata = ocp_reg_read(tp, 0xac14);\n+\t\tdata &= ~BIT(7);\n+\t\tocp_reg_write(tp, 0xac14, data);\n+\t\tdata = ocp_reg_read(tp, 0xac80);\n+\t\tdata &= ~(BIT(8) | BIT(9));\n+\t\tocp_reg_write(tp, 0xac80, data);\n+\t\tdata = ocp_reg_read(tp, 0xac5e);\n+\t\tdata &= ~0x7;\n+\t\tdata |= BIT(1);\n+\t\tocp_reg_write(tp, 0xac5e, data);\n+\t\tocp_reg_write(tp, 0xad4c, 0x00a8);\n+\t\tocp_reg_write(tp, 0xac5c, 0x01ff);\n+\t\tdata = ocp_reg_read(tp, 0xac8a);\n+\t\tdata &= ~0xf0;\n+\t\tdata |= BIT(4) | BIT(5);\n+\t\tocp_reg_write(tp, 0xac8a, data);\n+\t\tocp_reg_write(tp, 0xb87c, 0x8157);\n+\t\tdata = ocp_reg_read(tp, 0xb87e);\n+\t\tdata &= ~0xff00;\n+\t\tdata |= 0x0500;\n+\t\tocp_reg_write(tp, 0xb87e, data);\n+\t\tocp_reg_write(tp, 0xb87c, 0x8159);\n+\t\tdata = ocp_reg_read(tp, 0xb87e);\n+\t\tdata &= ~0xff00;\n+\t\tdata |= 0x0700;\n+\t\tocp_reg_write(tp, 0xb87e, data);\n+\n+\t\t/* AAGC */\n+\t\tocp_reg_write(tp, 0xb87c, 0x80a2);\n+\t\tocp_reg_write(tp, 0xb87e, 0x0153);\n+\t\tocp_reg_write(tp, 0xb87c, 0x809c);\n+\t\tocp_reg_write(tp, 0xb87e, 0x0153);\n+\n+\t\t/* EEE parameter */\n+\t\tocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_TXTWSYS_2P5G, 0x0056);\n+\n+\t\tocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_USB_CFG);\n+\t\tocp_data |= EN_XG_LIP | EN_G_LIP;\n+\t\tocp_write_word(tp, MCU_TYPE_PLA, PLA_USB_CFG, ocp_data);\n+\n+\t\tsram_write(tp, 0x8257, 0x020f); /*  XG PLL */\n+\t\tsram_write(tp, 0x80ea, 0x7843); /* GIGA Master */\n+\n+\t\tif (rtl_phy_patch_request(tp, true, true))\n+\t\t\treturn;\n+\n+\t\t/* Advance EEE */\n+\t\tocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);\n+\t\tocp_data |= EEE_SPDWN_EN;\n+\t\tocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data);\n+\n+\t\tdata = ocp_reg_read(tp, OCP_DOWN_SPEED);\n+\t\tdata &= ~(EN_EEE_100 | EN_EEE_1000);\n+\t\tdata |= EN_10M_CLKDIV;\n+\t\tocp_reg_write(tp, OCP_DOWN_SPEED, data);\n+\t\ttp->ups_info._10m_ckdiv = true;\n+\t\ttp->ups_info.eee_plloff_100 = false;\n+\t\ttp->ups_info.eee_plloff_giga = false;\n+\n+\t\tdata = ocp_reg_read(tp, OCP_POWER_CFG);\n+\t\tdata &= ~EEE_CLKDIV_EN;\n+\t\tocp_reg_write(tp, OCP_POWER_CFG, data);\n+\t\ttp->ups_info.eee_ckdiv = false;\n+\n+\t\tocp_reg_write(tp, OCP_SYSCLK_CFG, 0);\n+\t\tocp_reg_write(tp, OCP_SYSCLK_CFG, sysclk_div_expo(5));\n+\t\ttp->ups_info._250m_ckdiv = false;\n+\n+\t\trtl_phy_patch_request(tp, false, true);\n+\n+\t\t/* enable ADC Ibias Cal */\n+\t\tdata = ocp_reg_read(tp, 0xd068);\n+\t\tdata |= BIT(13);\n+\t\tocp_reg_write(tp, 0xd068, data);\n+\n+\t\t/* enable Thermal Sensor */\n+\t\tdata = sram_read(tp, 0x81a2);\n+\t\tdata &= ~BIT(8);\n+\t\tsram_write(tp, 0x81a2, data);\n+\t\tdata = ocp_reg_read(tp, 0xb54c);\n+\t\tdata &= ~0xff00;\n+\t\tdata |= 0xdb00;\n+\t\tocp_reg_write(tp, 0xb54c, data);\n+\n+\t\t/* Nway 2.5G Lite */\n+\t\tdata = ocp_reg_read(tp, 0xa454);\n+\t\tdata &= ~BIT(0);\n+\t\tocp_reg_write(tp, 0xa454, data);\n+\n+\t\t/* CS DSP solution */\n+\t\tdata = ocp_reg_read(tp, OCP_10GBT_CTRL);\n+\t\tdata |= RTL_ADV2_5G_F_R;\n+\t\tocp_reg_write(tp, OCP_10GBT_CTRL, data);\n+\t\tdata = ocp_reg_read(tp, 0xad4e);\n+\t\tdata &= ~BIT(4);\n+\t\tocp_reg_write(tp, 0xad4e, data);\n+\t\tdata = ocp_reg_read(tp, 0xa86a);\n+\t\tdata &= ~BIT(0);\n+\t\tocp_reg_write(tp, 0xa86a, data);\n+\n+\t\t/* MDI SWAP */\n+\t\tif ((ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CFG) & MID_REVERSE) &&\n+\t\t    (ocp_reg_read(tp, 0xd068) & BIT(1))) {\n+\t\t\tu16 swap_a, swap_b;\n+\n+\t\t\tdata = ocp_reg_read(tp, 0xd068);\n+\t\t\tdata &= ~0x1f;\n+\t\t\tdata |= 0x1; /* p0 */\n+\t\t\tocp_reg_write(tp, 0xd068, data);\n+\t\t\tswap_a = ocp_reg_read(tp, 0xd06a);\n+\t\t\tdata &= ~0x18;\n+\t\t\tdata |= 0x18; /* p3 */\n+\t\t\tocp_reg_write(tp, 0xd068, data);\n+\t\t\tswap_b = ocp_reg_read(tp, 0xd06a);\n+\t\t\tdata &= ~0x18; /* p0 */\n+\t\t\tocp_reg_write(tp, 0xd068, data);\n+\t\t\tocp_reg_write(tp, 0xd06a,\n+\t\t\t\t      (swap_a & ~0x7ff) | (swap_b & 0x7ff));\n+\t\t\tdata |= 0x18; /* p3 */\n+\t\t\tocp_reg_write(tp, 0xd068, data);\n+\t\t\tocp_reg_write(tp, 0xd06a,\n+\t\t\t\t      (swap_b & ~0x7ff) | (swap_a & 0x7ff));\n+\t\t\tdata &= ~0x18;\n+\t\t\tdata |= 0x08; /* p1 */\n+\t\t\tocp_reg_write(tp, 0xd068, data);\n+\t\t\tswap_a = ocp_reg_read(tp, 0xd06a);\n+\t\t\tdata &= ~0x18;\n+\t\t\tdata |= 0x10; /* p2 */\n+\t\t\tocp_reg_write(tp, 0xd068, data);\n+\t\t\tswap_b = ocp_reg_read(tp, 0xd06a);\n+\t\t\tdata &= ~0x18;\n+\t\t\tdata |= 0x08; /* p1 */\n+\t\t\tocp_reg_write(tp, 0xd068, data);\n+\t\t\tocp_reg_write(tp, 0xd06a,\n+\t\t\t\t      (swap_a & ~0x7ff) | (swap_b & 0x7ff));\n+\t\t\tdata &= ~0x18;\n+\t\t\tdata |= 0x10; /* p2 */\n+\t\t\tocp_reg_write(tp, 0xd068, data);\n+\t\t\tocp_reg_write(tp, 0xd06a,\n+\t\t\t\t      (swap_b & ~0x7ff) | (swap_a & 0x7ff));\n+\t\t\tswap_a = ocp_reg_read(tp, 0xbd5a);\n+\t\t\tswap_b = ocp_reg_read(tp, 0xbd5c);\n+\t\t\tocp_reg_write(tp, 0xbd5a, (swap_a & ~0x1f1f) |\n+\t\t\t\t      ((swap_b & 0x1f) << 8) |\n+\t\t\t\t      ((swap_b >> 8) & 0x1f));\n+\t\t\tocp_reg_write(tp, 0xbd5c, (swap_b & ~0x1f1f) |\n+\t\t\t\t      ((swap_a & 0x1f) << 8) |\n+\t\t\t\t      ((swap_a >> 8) & 0x1f));\n+\t\t\tswap_a = ocp_reg_read(tp, 0xbc18);\n+\t\t\tswap_b = ocp_reg_read(tp, 0xbc1a);\n+\t\t\tocp_reg_write(tp, 0xbc18, (swap_a & ~0x1f1f) |\n+\t\t\t\t      ((swap_b & 0x1f) << 8) |\n+\t\t\t\t      ((swap_b >> 8) & 0x1f));\n+\t\t\tocp_reg_write(tp, 0xbc1a, (swap_b & ~0x1f1f) |\n+\t\t\t\t      ((swap_a & 0x1f) << 8) |\n+\t\t\t\t      ((swap_a >> 8) & 0x1f));\n+\t\t}\n+\t\tbreak;\n+\tdefault:\n+\t\tbreak;\n+\t}\n+\n+\trtl_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags));\n+\n+\tdata = ocp_reg_read(tp, 0xa428);\n+\tdata &= ~BIT(9);\n+\tocp_reg_write(tp, 0xa428, data);\n+\tdata = ocp_reg_read(tp, 0xa5ea);\n+\tdata &= ~BIT(0);\n+\tocp_reg_write(tp, 0xa5ea, data);\n+\ttp->ups_info.lite_mode = 0;\n+\n+\tif (tp->eee_en)\n+\t\trtl_eee_enable(tp, true);\n+\n+\tr8153_aldps_en(tp, true);\n+\tr8152b_enable_fc(tp);\n+\tr8153_u2p3en(tp, true);\n+\n+\tset_bit(PHY_RESET, &tp->flags);\n+}\n+\n+static void r8156b_hw_phy_cfg(struct r8152 *tp)\n+{\n+\tu32 ocp_data;\n+\tu16 data;\n+\n+\tswitch (tp->version) {\n+\tcase RTL_VER_12:\n+\t\tocp_reg_write(tp, 0xbf86, 0x9000);\n+\t\tdata = ocp_reg_read(tp, 0xc402);\n+\t\tdata |= BIT(10);\n+\t\tocp_reg_write(tp, 0xc402, data);\n+\t\tdata &= ~BIT(10);\n+\t\tocp_reg_write(tp, 0xc402, data);\n+\t\tocp_reg_write(tp, 0xbd86, 0x1010);\n+\t\tocp_reg_write(tp, 0xbd88, 0x1010);\n+\t\tdata = ocp_reg_read(tp, 0xbd4e);\n+\t\tdata &= ~(BIT(10) | BIT(11));\n+\t\tdata |= BIT(11);\n+\t\tocp_reg_write(tp, 0xbd4e, data);\n+\t\tdata = ocp_reg_read(tp, 0xbf46);\n+\t\tdata &= ~0xf00;\n+\t\tdata |= 0x700;\n+\t\tocp_reg_write(tp, 0xbf46, data);\n+\t\tbreak;\n+\tcase RTL_VER_13:\n+\tcase RTL_VER_15:\n+\t\tr8156b_wait_loading_flash(tp);\n+\t\tbreak;\n+\tdefault:\n+\t\tbreak;\n+\t}\n+\n+\tocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);\n+\tif (ocp_data & PCUT_STATUS) {\n+\t\tocp_data &= ~PCUT_STATUS;\n+\t\tocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);\n+\t}\n+\n+\tdata = r8153_phy_status(tp, 0);\n+\tswitch (data) {\n+\tcase PHY_STAT_EXT_INIT:\n+\t\trtl8152_apply_firmware(tp, true);\n+\n+\t\tdata = ocp_reg_read(tp, 0xa466);\n+\t\tdata &= ~BIT(0);\n+\t\tocp_reg_write(tp, 0xa466, data);\n+\n+\t\tdata = ocp_reg_read(tp, 0xa468);\n+\t\tdata &= ~(BIT(3) | BIT(1));\n+\t\tocp_reg_write(tp, 0xa468, data);\n+\t\tbreak;\n+\tcase PHY_STAT_LAN_ON:\n+\tcase PHY_STAT_PWRDN:\n+\tdefault:\n+\t\trtl8152_apply_firmware(tp, false);\n+\t\tbreak;\n+\t}\n+\n+\tdata = r8152_mdio_read(tp, MII_BMCR);\n+\tif (data & BMCR_PDOWN) {\n+\t\tdata &= ~BMCR_PDOWN;\n+\t\tr8152_mdio_write(tp, MII_BMCR, data);\n+\t}\n+\n+\t/* disable ALDPS before updating the PHY parameters */\n+\tr8153_aldps_en(tp, false);\n+\n+\t/* disable EEE before updating the PHY parameters */\n+\trtl_eee_enable(tp, false);\n+\n+\tdata = r8153_phy_status(tp, PHY_STAT_LAN_ON);\n+\tWARN_ON_ONCE(data != PHY_STAT_LAN_ON);\n+\n+\tocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);\n+\tocp_data |= PFM_PWM_SWITCH;\n+\tocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);\n+\n+\tswitch (tp->version) {\n+\tcase RTL_VER_12:\n+\t\tdata = ocp_reg_read(tp, 0xbc08);\n+\t\tdata |= BIT(3) | BIT(2);\n+\t\tocp_reg_write(tp, 0xbc08, data);\n+\n+\t\tdata = sram_read(tp, 0x8fff);\n+\t\tdata &= ~0xff00;\n+\t\tdata |= 0x0400;\n+\t\tsram_write(tp, 0x8fff, data);\n+\n+\t\tdata = ocp_reg_read(tp, 0xacda);\n+\t\tdata |= 0xff00;\n+\t\tocp_reg_write(tp, 0xacda, data);\n+\t\tdata = ocp_reg_read(tp, 0xacde);\n+\t\tdata |= 0xf000;\n+\t\tocp_reg_write(tp, 0xacde, data);\n+\t\tocp_reg_write(tp, 0xac8c, 0x0ffc);\n+\t\tocp_reg_write(tp, 0xac46, 0xb7b4);\n+\t\tocp_reg_write(tp, 0xac50, 0x0fbc);\n+\t\tocp_reg_write(tp, 0xac3c, 0x9240);\n+\t\tocp_reg_write(tp, 0xac4e, 0x0db4);\n+\t\tocp_reg_write(tp, 0xacc6, 0x0707);\n+\t\tocp_reg_write(tp, 0xacc8, 0xa0d3);\n+\t\tocp_reg_write(tp, 0xad08, 0x0007);\n+\n+\t\tocp_reg_write(tp, 0xb87c, 0x8560);\n+\t\tocp_reg_write(tp, 0xb87e, 0x19cc);\n+\t\tocp_reg_write(tp, 0xb87c, 0x8562);\n+\t\tocp_reg_write(tp, 0xb87e, 0x19cc);\n+\t\tocp_reg_write(tp, 0xb87c, 0x8564);\n+\t\tocp_reg_write(tp, 0xb87e, 0x19cc);\n+\t\tocp_reg_write(tp, 0xb87c, 0x8566);\n+\t\tocp_reg_write(tp, 0xb87e, 0x147d);\n+\t\tocp_reg_write(tp, 0xb87c, 0x8568);\n+\t\tocp_reg_write(tp, 0xb87e, 0x147d);\n+\t\tocp_reg_write(tp, 0xb87c, 0x856a);\n+\t\tocp_reg_write(tp, 0xb87e, 0x147d);\n+\t\tocp_reg_write(tp, 0xb87c, 0x8ffe);\n+\t\tocp_reg_write(tp, 0xb87e, 0x0907);\n+\t\tocp_reg_write(tp, 0xb87c, 0x80d6);\n+\t\tocp_reg_write(tp, 0xb87e, 0x2801);\n+\t\tocp_reg_write(tp, 0xb87c, 0x80f2);\n+\t\tocp_reg_write(tp, 0xb87e, 0x2801);\n+\t\tocp_reg_write(tp, 0xb87c, 0x80f4);\n+\t\tocp_reg_write(tp, 0xb87e, 0x6077);\n+\t\tocp_reg_write(tp, 0xb506, 0x01e7);\n+\n+\t\tocp_reg_write(tp, 0xb87c, 0x8013);\n+\t\tocp_reg_write(tp, 0xb87e, 0x0700);\n+\t\tocp_reg_write(tp, 0xb87c, 0x8fb9);\n+\t\tocp_reg_write(tp, 0xb87e, 0x2801);\n+\t\tocp_reg_write(tp, 0xb87c, 0x8fba);\n+\t\tocp_reg_write(tp, 0xb87e, 0x0100);\n+\t\tocp_reg_write(tp, 0xb87c, 0x8fbc);\n+\t\tocp_reg_write(tp, 0xb87e, 0x1900);\n+\t\tocp_reg_write(tp, 0xb87c, 0x8fbe);\n+\t\tocp_reg_write(tp, 0xb87e, 0xe100);\n+\t\tocp_reg_write(tp, 0xb87c, 0x8fc0);\n+\t\tocp_reg_write(tp, 0xb87e, 0x0800);\n+\t\tocp_reg_write(tp, 0xb87c, 0x8fc2);\n+\t\tocp_reg_write(tp, 0xb87e, 0xe500);\n+\t\tocp_reg_write(tp, 0xb87c, 0x8fc4);\n+\t\tocp_reg_write(tp, 0xb87e, 0x0f00);\n+\t\tocp_reg_write(tp, 0xb87c, 0x8fc6);\n+\t\tocp_reg_write(tp, 0xb87e, 0xf100);\n+\t\tocp_reg_write(tp, 0xb87c, 0x8fc8);\n+\t\tocp_reg_write(tp, 0xb87e, 0x0400);\n+\t\tocp_reg_write(tp, 0xb87c, 0x8fca);\n+\t\tocp_reg_write(tp, 0xb87e, 0xf300);\n+\t\tocp_reg_write(tp, 0xb87c, 0x8fcc);\n+\t\tocp_reg_write(tp, 0xb87e, 0xfd00);\n+\t\tocp_reg_write(tp, 0xb87c, 0x8fce);\n+\t\tocp_reg_write(tp, 0xb87e, 0xff00);\n+\t\tocp_reg_write(tp, 0xb87c, 0x8fd0);\n+\t\tocp_reg_write(tp, 0xb87e, 0xfb00);\n+\t\tocp_reg_write(tp, 0xb87c, 0x8fd2);\n+\t\tocp_reg_write(tp, 0xb87e, 0x0100);\n+\t\tocp_reg_write(tp, 0xb87c, 0x8fd4);\n+\t\tocp_reg_write(tp, 0xb87e, 0xf400);\n+\t\tocp_reg_write(tp, 0xb87c, 0x8fd6);\n+\t\tocp_reg_write(tp, 0xb87e, 0xff00);\n+\t\tocp_reg_write(tp, 0xb87c, 0x8fd8);\n+\t\tocp_reg_write(tp, 0xb87e, 0xf600);\n+\n+\t\tocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_USB_CFG);\n+\t\tocp_data |= EN_XG_LIP | EN_G_LIP;\n+\t\tocp_write_byte(tp, MCU_TYPE_PLA, PLA_USB_CFG, ocp_data);\n+\t\tocp_reg_write(tp, 0xb87c, 0x813d);\n+\t\tocp_reg_write(tp, 0xb87e, 0x390e);\n+\t\tocp_reg_write(tp, 0xb87c, 0x814f);\n+\t\tocp_reg_write(tp, 0xb87e, 0x790e);\n+\t\tocp_reg_write(tp, 0xb87c, 0x80b0);\n+\t\tocp_reg_write(tp, 0xb87e, 0x0f31);\n+\t\tdata = ocp_reg_read(tp, 0xbf4c);\n+\t\tdata |= BIT(1);\n+\t\tocp_reg_write(tp, 0xbf4c, data);\n+\t\tdata = ocp_reg_read(tp, 0xbcca);\n+\t\tdata |= BIT(9) | BIT(8);\n+\t\tocp_reg_write(tp, 0xbcca, data);\n+\t\tocp_reg_write(tp, 0xb87c, 0x8141);\n+\t\tocp_reg_write(tp, 0xb87e, 0x320e);\n+\t\tocp_reg_write(tp, 0xb87c, 0x8153);\n+\t\tocp_reg_write(tp, 0xb87e, 0x720e);\n+\t\tocp_reg_write(tp, 0xb87c, 0x8529);\n+\t\tocp_reg_write(tp, 0xb87e, 0x050e);\n+\t\tdata = ocp_reg_read(tp, OCP_EEE_CFG);\n+\t\tdata &= ~CTAP_SHORT_EN;\n+\t\tocp_reg_write(tp, OCP_EEE_CFG, data);\n+\n+\t\tsram_write(tp, 0x816c, 0xc4a0);\n+\t\tsram_write(tp, 0x8170, 0xc4a0);\n+\t\tsram_write(tp, 0x8174, 0x04a0);\n+\t\tsram_write(tp, 0x8178, 0x04a0);\n+\t\tsram_write(tp, 0x817c, 0x0719);\n+\t\tsram_write(tp, 0x8ff4, 0x0400);\n+\t\tsram_write(tp, 0x8ff1, 0x0404);\n+\n+\t\tocp_reg_write(tp, 0xbf4a, 0x001b);\n+\t\tocp_reg_write(tp, 0xb87c, 0x8033);\n+\t\tocp_reg_write(tp, 0xb87e, 0x7c13);\n+\t\tocp_reg_write(tp, 0xb87c, 0x8037);\n+\t\tocp_reg_write(tp, 0xb87e, 0x7c13);\n+\t\tocp_reg_write(tp, 0xb87c, 0x803b);\n+\t\tocp_reg_write(tp, 0xb87e, 0xfc32);\n+\t\tocp_reg_write(tp, 0xb87c, 0x803f);\n+\t\tocp_reg_write(tp, 0xb87e, 0x7c13);\n+\t\tocp_reg_write(tp, 0xb87c, 0x8043);\n+\t\tocp_reg_write(tp, 0xb87e, 0x7c13);\n+\t\tocp_reg_write(tp, 0xb87c, 0x8047);\n+\t\tocp_reg_write(tp, 0xb87e, 0x7c13);\n+\n+\t\tocp_reg_write(tp, 0xb87c, 0x8145);\n+\t\tocp_reg_write(tp, 0xb87e, 0x370e);\n+\t\tocp_reg_write(tp, 0xb87c, 0x8157);\n+\t\tocp_reg_write(tp, 0xb87e, 0x770e);\n+\t\tocp_reg_write(tp, 0xb87c, 0x8169);\n+\t\tocp_reg_write(tp, 0xb87e, 0x0d0a);\n+\t\tocp_reg_write(tp, 0xb87c, 0x817b);\n+\t\tocp_reg_write(tp, 0xb87e, 0x1d0a);\n+\n+\t\tdata = sram_read(tp, 0x8217);\n+\t\tdata &= ~0xff00;\n+\t\tdata |= 0x5000;\n+\t\tsram_write(tp, 0x8217, data);\n+\t\tdata = sram_read(tp, 0x821a);\n+\t\tdata &= ~0xff00;\n+\t\tdata |= 0x5000;\n+\t\tsram_write(tp, 0x821a, data);\n+\t\tsram_write(tp, 0x80da, 0x0403);\n+\t\tdata = sram_read(tp, 0x80dc);\n+\t\tdata &= ~0xff00;\n+\t\tdata |= 0x1000;\n+\t\tsram_write(tp, 0x80dc, data);\n+\t\tsram_write(tp, 0x80b3, 0x0384);\n+\t\tsram_write(tp, 0x80b7, 0x2007);\n+\t\tdata = sram_read(tp, 0x80ba);\n+\t\tdata &= ~0xff00;\n+\t\tdata |= 0x6c00;\n+\t\tsram_write(tp, 0x80ba, data);\n+\t\tsram_write(tp, 0x80b5, 0xf009);\n+\t\tdata = sram_read(tp, 0x80bd);\n+\t\tdata &= ~0xff00;\n+\t\tdata |= 0x9f00;\n+\t\tsram_write(tp, 0x80bd, data);\n+\t\tsram_write(tp, 0x80c7, 0xf083);\n+\t\tsram_write(tp, 0x80dd, 0x03f0);\n+\t\tdata = sram_read(tp, 0x80df);\n+\t\tdata &= ~0xff00;\n+\t\tdata |= 0x1000;\n+\t\tsram_write(tp, 0x80df, data);\n+\t\tsram_write(tp, 0x80cb, 0x2007);\n+\t\tdata = sram_read(tp, 0x80ce);\n+\t\tdata &= ~0xff00;\n+\t\tdata |= 0x6c00;\n+\t\tsram_write(tp, 0x80ce, data);\n+\t\tsram_write(tp, 0x80c9, 0x8009);\n+\t\tdata = sram_read(tp, 0x80d1);\n+\t\tdata &= ~0xff00;\n+\t\tdata |= 0x8000;\n+\t\tsram_write(tp, 0x80d1, data);\n+\t\tsram_write(tp, 0x80a3, 0x200a);\n+\t\tsram_write(tp, 0x80a5, 0xf0ad);\n+\t\tsram_write(tp, 0x809f, 0x6073);\n+\t\tsram_write(tp, 0x80a1, 0x000b);\n+\t\tdata = sram_read(tp, 0x80a9);\n+\t\tdata &= ~0xff00;\n+\t\tdata |= 0xc000;\n+\t\tsram_write(tp, 0x80a9, data);\n+\n+\t\tif (rtl_phy_patch_request(tp, true, true))\n+\t\t\treturn;\n+\n+\t\tdata = ocp_reg_read(tp, 0xb896);\n+\t\tdata &= ~BIT(0);\n+\t\tocp_reg_write(tp, 0xb896, data);\n+\t\tdata = ocp_reg_read(tp, 0xb892);\n+\t\tdata &= ~0xff00;\n+\t\tocp_reg_write(tp, 0xb892, data);\n+\t\tocp_reg_write(tp, 0xb88e, 0xc23e);\n+\t\tocp_reg_write(tp, 0xb890, 0x0000);\n+\t\tocp_reg_write(tp, 0xb88e, 0xc240);\n+\t\tocp_reg_write(tp, 0xb890, 0x0103);\n+\t\tocp_reg_write(tp, 0xb88e, 0xc242);\n+\t\tocp_reg_write(tp, 0xb890, 0x0507);\n+\t\tocp_reg_write(tp, 0xb88e, 0xc244);\n+\t\tocp_reg_write(tp, 0xb890, 0x090b);\n+\t\tocp_reg_write(tp, 0xb88e, 0xc246);\n+\t\tocp_reg_write(tp, 0xb890, 0x0c0e);\n+\t\tocp_reg_write(tp, 0xb88e, 0xc248);\n+\t\tocp_reg_write(tp, 0xb890, 0x1012);\n+\t\tocp_reg_write(tp, 0xb88e, 0xc24a);\n+\t\tocp_reg_write(tp, 0xb890, 0x1416);\n+\t\tdata = ocp_reg_read(tp, 0xb896);\n+\t\tdata |= BIT(0);\n+\t\tocp_reg_write(tp, 0xb896, data);\n+\n+\t\trtl_phy_patch_request(tp, false, true);\n+\n+\t\tdata = ocp_reg_read(tp, 0xa86a);\n+\t\tdata |= BIT(0);\n+\t\tocp_reg_write(tp, 0xa86a, data);\n+\t\tdata = ocp_reg_read(tp, 0xa6f0);\n+\t\tdata |= BIT(0);\n+\t\tocp_reg_write(tp, 0xa6f0, data);\n+\n+\t\tocp_reg_write(tp, 0xbfa0, 0xd70d);\n+\t\tocp_reg_write(tp, 0xbfa2, 0x4100);\n+\t\tocp_reg_write(tp, 0xbfa4, 0xe868);\n+\t\tocp_reg_write(tp, 0xbfa6, 0xdc59);\n+\t\tocp_reg_write(tp, 0xb54c, 0x3c18);\n+\t\tdata = ocp_reg_read(tp, 0xbfa4);\n+\t\tdata &= ~BIT(5);\n+\t\tocp_reg_write(tp, 0xbfa4, data);\n+\t\tdata = sram_read(tp, 0x817d);\n+\t\tdata |= BIT(12);\n+\t\tsram_write(tp, 0x817d, data);\n+\t\tbreak;\n+\tcase RTL_VER_13:\n+\t\t/* 2.5G INRX */\n+\t\tdata = ocp_reg_read(tp, 0xac46);\n+\t\tdata &= ~0x00f0;\n+\t\tdata |= 0x0090;\n+\t\tocp_reg_write(tp, 0xac46, data);\n+\t\tdata = ocp_reg_read(tp, 0xad30);\n+\t\tdata &= ~0x0003;\n+\t\tdata |= 0x0001;\n+\t\tocp_reg_write(tp, 0xad30, data);\n+\t\tfallthrough;\n+\tcase RTL_VER_15:\n+\t\t/* EEE parameter */\n+\t\tocp_reg_write(tp, 0xb87c, 0x80f5);\n+\t\tocp_reg_write(tp, 0xb87e, 0x760e);\n+\t\tocp_reg_write(tp, 0xb87c, 0x8107);\n+\t\tocp_reg_write(tp, 0xb87e, 0x360e);\n+\t\tocp_reg_write(tp, 0xb87c, 0x8551);\n+\t\tdata = ocp_reg_read(tp, 0xb87e);\n+\t\tdata &= ~0xff00;\n+\t\tdata |= 0x0800;\n+\t\tocp_reg_write(tp, 0xb87e, data);\n+\n+\t\t/* ADC_PGA parameter */\n+\t\tdata = ocp_reg_read(tp, 0xbf00);\n+\t\tdata &= ~0xe000;\n+\t\tdata |= 0xa000;\n+\t\tocp_reg_write(tp, 0xbf00, data);\n+\t\tdata = ocp_reg_read(tp, 0xbf46);\n+\t\tdata &= ~0x0f00;\n+\t\tdata |= 0x0300;\n+\t\tocp_reg_write(tp, 0xbf46, data);\n+\n+\t\t/* Green Table-PGA, 1G full viterbi */\n+\t\tsram_write(tp, 0x8044, 0x2417);\n+\t\tsram_write(tp, 0x804a, 0x2417);\n+\t\tsram_write(tp, 0x8050, 0x2417);\n+\t\tsram_write(tp, 0x8056, 0x2417);\n+\t\tsram_write(tp, 0x805c, 0x2417);\n+\t\tsram_write(tp, 0x8062, 0x2417);\n+\t\tsram_write(tp, 0x8068, 0x2417);\n+\t\tsram_write(tp, 0x806e, 0x2417);\n+\t\tsram_write(tp, 0x8074, 0x2417);\n+\t\tsram_write(tp, 0x807a, 0x2417);\n+\n+\t\t/* XG PLL */\n+\t\tdata = ocp_reg_read(tp, 0xbf84);\n+\t\tdata &= ~0xe000;\n+\t\tdata |= 0xa000;\n+\t\tocp_reg_write(tp, 0xbf84, data);\n+\t\tbreak;\n+\tdefault:\n+\t\tbreak;\n+\t}\n+\n+\tif (rtl_phy_patch_request(tp, true, true))\n+\t\treturn;\n+\n+\tocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);\n+\tocp_data |= EEE_SPDWN_EN;\n+\tocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data);\n+\n+\tdata = ocp_reg_read(tp, OCP_DOWN_SPEED);\n+\tdata &= ~(EN_EEE_100 | EN_EEE_1000);\n+\tdata |= EN_10M_CLKDIV;\n+\tocp_reg_write(tp, OCP_DOWN_SPEED, data);\n+\ttp->ups_info._10m_ckdiv = true;\n+\ttp->ups_info.eee_plloff_100 = false;\n+\ttp->ups_info.eee_plloff_giga = false;\n+\n+\tdata = ocp_reg_read(tp, OCP_POWER_CFG);\n+\tdata &= ~EEE_CLKDIV_EN;\n+\tocp_reg_write(tp, OCP_POWER_CFG, data);\n+\ttp->ups_info.eee_ckdiv = false;\n+\n+\trtl_phy_patch_request(tp, false, true);\n+\n+\trtl_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags));\n+\n+\tdata = ocp_reg_read(tp, 0xa428);\n+\tdata &= ~BIT(9);\n+\tocp_reg_write(tp, 0xa428, data);\n+\tdata = ocp_reg_read(tp, 0xa5ea);\n+\tdata &= ~BIT(0);\n+\tocp_reg_write(tp, 0xa5ea, data);\n+\ttp->ups_info.lite_mode = 0;\n+\n+\tif (tp->eee_en)\n+\t\trtl_eee_enable(tp, true);\n+\n+\tr8153_aldps_en(tp, true);\n+\tr8152b_enable_fc(tp);\n+\tr8153_u2p3en(tp, true);\n+\n+\tset_bit(PHY_RESET, &tp->flags);\n+}\n+\n+static void r8156_init(struct r8152 *tp)\n+{\n+\tu32 ocp_data;\n+\tu16 data;\n+\tint i;\n+\n+\tif (test_bit(RTL8152_UNPLUG, &tp->flags))\n+\t\treturn;\n+\n+\tocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_ECM_OP);\n+\tocp_data &= ~EN_ALL_SPEED;\n+\tocp_write_byte(tp, MCU_TYPE_USB, USB_ECM_OP, ocp_data);\n+\n+\tocp_write_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION, 0);\n+\n+\tocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_ECM_OPTION);\n+\tocp_data |= BYPASS_MAC_RESET;\n+\tocp_write_word(tp, MCU_TYPE_USB, USB_ECM_OPTION, ocp_data);\n+\n+\tr8153b_u1u2en(tp, false);\n+\n+\tfor (i = 0; i < 500; i++) {\n+\t\tif (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &\n+\t\t    AUTOLOAD_DONE)\n+\t\t\tbreak;\n+\n+\t\tmsleep(20);\n+\t\tif (test_bit(RTL8152_UNPLUG, &tp->flags))\n+\t\t\treturn;\n+\t}\n+\n+\tdata = r8153_phy_status(tp, 0);\n+\tif (data == PHY_STAT_EXT_INIT) {\n+\t\tdata = ocp_reg_read(tp, 0xa468);\n+\t\tdata &= ~(BIT(3) | BIT(1));\n+\t\tocp_reg_write(tp, 0xa468, data);\n+\t}\n+\n+\tdata = r8152_mdio_read(tp, MII_BMCR);\n+\tif (data & BMCR_PDOWN) {\n+\t\tdata &= ~BMCR_PDOWN;\n+\t\tr8152_mdio_write(tp, MII_BMCR, data);\n+\t}\n+\n+\tdata = r8153_phy_status(tp, PHY_STAT_LAN_ON);\n+\tWARN_ON_ONCE(data != PHY_STAT_LAN_ON);\n+\n+\tr8153_u2p3en(tp, false);\n+\n+\t/* MSC timer = 0xfff * 8ms = 32760 ms */\n+\tocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff);\n+\n+\t/* U1/U2/L1 idle timer. 500 us */\n+\tocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500);\n+\n+\tr8153b_power_cut_en(tp, false);\n+\tr8156_ups_en(tp, false);\n+\tr8153_queue_wake(tp, false);\n+\trtl_runtime_suspend_enable(tp, false);\n+\n+\tif (tp->udev->speed >= USB_SPEED_SUPER)\n+\t\tr8153b_u1u2en(tp, true);\n+\n+\tusb_enable_lpm(tp->udev);\n+\n+\tr8156_mac_clk_spd(tp, true);\n+\n+\tocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);\n+\tocp_data &= ~PLA_MCU_SPDWN_EN;\n+\tocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);\n+\n+\tocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);\n+\tif (rtl8152_get_speed(tp) & LINK_STATUS)\n+\t\tocp_data |= CUR_LINK_OK;\n+\telse\n+\t\tocp_data &= ~CUR_LINK_OK;\n+\tocp_data |= POLL_LINK_CHG;\n+\tocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);\n+\n+\tset_bit(GREEN_ETHERNET, &tp->flags);\n+\n+\t/* rx aggregation */\n+\tocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);\n+\tocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);\n+\tocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);\n+\n+\tocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_BMU_CONFIG);\n+\tocp_data |= ACT_ODMA;\n+\tocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_CONFIG, ocp_data);\n+\n+\trtl_tally_reset(tp);\n+\n+\ttp->coalesce = 15000;\t/* 15 us */\n+}\n+\n+static void r8156b_init(struct r8152 *tp)\n+{\n+\tu32 ocp_data;\n+\tu16 data;\n+\tint i;\n+\n+\tif (test_bit(RTL8152_UNPLUG, &tp->flags))\n+\t\treturn;\n+\n+\tocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_ECM_OP);\n+\tocp_data &= ~EN_ALL_SPEED;\n+\tocp_write_byte(tp, MCU_TYPE_USB, USB_ECM_OP, ocp_data);\n+\n+\tocp_write_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION, 0);\n+\n+\tocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_ECM_OPTION);\n+\tocp_data |= BYPASS_MAC_RESET;\n+\tocp_write_word(tp, MCU_TYPE_USB, USB_ECM_OPTION, ocp_data);\n+\n+\tocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);\n+\tocp_data |= RX_DETECT8;\n+\tocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);\n+\n+\tr8153b_u1u2en(tp, false);\n+\n+\tswitch (tp->version) {\n+\tcase RTL_VER_13:\n+\tcase RTL_VER_15:\n+\t\tr8156b_wait_loading_flash(tp);\n+\t\tbreak;\n+\tdefault:\n+\t\tbreak;\n+\t}\n+\n+\tfor (i = 0; i < 500; i++) {\n+\t\tif (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &\n+\t\t    AUTOLOAD_DONE)\n+\t\t\tbreak;\n+\n+\t\tmsleep(20);\n+\t\tif (test_bit(RTL8152_UNPLUG, &tp->flags))\n+\t\t\treturn;\n+\t}\n+\n+\tdata = r8153_phy_status(tp, 0);\n+\tif (data == PHY_STAT_EXT_INIT) {\n+\t\tdata = ocp_reg_read(tp, 0xa468);\n+\t\tdata &= ~(BIT(3) | BIT(1));\n+\t\tocp_reg_write(tp, 0xa468, data);\n+\n+\t\tdata = ocp_reg_read(tp, 0xa466);\n+\t\tdata &= ~BIT(0);\n+\t\tocp_reg_write(tp, 0xa466, data);\n+\t}\n+\n+\tdata = r8152_mdio_read(tp, MII_BMCR);\n+\tif (data & BMCR_PDOWN) {\n+\t\tdata &= ~BMCR_PDOWN;\n+\t\tr8152_mdio_write(tp, MII_BMCR, data);\n+\t}\n+\n+\tdata = r8153_phy_status(tp, PHY_STAT_LAN_ON);\n+\n+\tr8153_u2p3en(tp, false);\n+\n+\t/* MSC timer = 0xfff * 8ms = 32760 ms */\n+\tocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff);\n+\n+\t/* U1/U2/L1 idle timer. 500 us */\n+\tocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500);\n+\n+\tr8153b_power_cut_en(tp, false);\n+\tr8156_ups_en(tp, false);\n+\tr8153_queue_wake(tp, false);\n+\trtl_runtime_suspend_enable(tp, false);\n+\n+\tif (tp->udev->speed >= USB_SPEED_SUPER)\n+\t\tr8153b_u1u2en(tp, true);\n+\n+\tusb_enable_lpm(tp->udev);\n+\n+\tocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RCR);\n+\tocp_data &= ~SLOT_EN;\n+\tocp_write_word(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);\n+\n+\tocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);\n+\tocp_data |= FLOW_CTRL_EN;\n+\tocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);\n+\n+\t/* enable fc timer and set timer to 600 ms. */\n+\tocp_write_word(tp, MCU_TYPE_USB, USB_FC_TIMER,\n+\t\t       CTRL_TIMER_EN | (600 / 8));\n+\n+\tocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_CTRL);\n+\tif (!(ocp_read_word(tp, MCU_TYPE_PLA, PLA_POL_GPIO_CTRL) & DACK_DET_EN))\n+\t\tocp_data |= FLOW_CTRL_PATCH_2;\n+\tocp_data &= ~AUTO_SPEEDUP;\n+\tocp_write_word(tp, MCU_TYPE_USB, USB_FW_CTRL, ocp_data);\n+\n+\tocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);\n+\tocp_data |= FC_PATCH_TASK;\n+\tocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);\n+\n+\tr8156_mac_clk_spd(tp, true);\n+\n+\tocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);\n+\tocp_data &= ~PLA_MCU_SPDWN_EN;\n+\tocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);\n+\n+\tocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);\n+\tif (rtl8152_get_speed(tp) & LINK_STATUS)\n+\t\tocp_data |= CUR_LINK_OK;\n+\telse\n+\t\tocp_data &= ~CUR_LINK_OK;\n+\tocp_data |= POLL_LINK_CHG;\n+\tocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);\n+\n+\tset_bit(GREEN_ETHERNET, &tp->flags);\n+\n+\t/* rx aggregation */\n+\tocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);\n+\tocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);\n+\tocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);\n+\n+\trtl_tally_reset(tp);\n+\n+\ttp->coalesce = 15000;\t/* 15 us */\n+}\n+\n static int rtl8152_pre_reset(struct usb_interface *intf)\n {\n \tstruct r8152 *tp = usb_get_intfdata(intf);\n@@ -5992,6 +7924,22 @@ int rtl8152_get_link_ksettings(struct ne\n \n \tmii_ethtool_get_link_ksettings(&tp->mii, cmd);\n \n+\tlinkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,\n+\t\t\t cmd->link_modes.supported, tp->support_2500full);\n+\n+\tif (tp->support_2500full) {\n+\t\tlinkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,\n+\t\t\t\t cmd->link_modes.advertising,\n+\t\t\t\t ocp_reg_read(tp, OCP_10GBT_CTRL) & MDIO_AN_10GBT_CTRL_ADV2_5G);\n+\n+\t\tlinkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,\n+\t\t\t\t cmd->link_modes.lp_advertising,\n+\t\t\t\t ocp_reg_read(tp, OCP_10GBT_STAT) & MDIO_AN_10GBT_STAT_LP2_5G);\n+\n+\t\tif (is_speed_2500(rtl8152_get_speed(tp)))\n+\t\t\tcmd->base.speed = SPEED_2500;\n+\t}\n+\n \tmutex_unlock(&tp->control);\n \n \tusb_autopm_put_interface(tp->intf);\n@@ -6035,6 +7983,10 @@ static int rtl8152_set_link_ksettings(st\n \t\t     cmd->link_modes.advertising))\n \t\tadvertising |= RTL_ADVERTISED_1000_FULL;\n \n+\tif (test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,\n+\t\t     cmd->link_modes.advertising))\n+\t\tadvertising |= RTL_ADVERTISED_2500_FULL;\n+\n \tmutex_lock(&tp->control);\n \n \tret = rtl8152_set_speed(tp, cmd->base.autoneg, cmd->base.speed,\n@@ -6624,6 +8576,67 @@ static int rtl_ops_init(struct r8152 *tp\n \t\ttp->eee_adv\t\t= MDIO_EEE_1000T | MDIO_EEE_100TX;\n \t\tbreak;\n \n+\tcase RTL_VER_11:\n+\t\ttp->eee_en\t\t= true;\n+\t\ttp->eee_adv\t\t= MDIO_EEE_1000T | MDIO_EEE_100TX;\n+\t\tfallthrough;\n+\tcase RTL_VER_10:\n+\t\tops->init\t\t= r8156_init;\n+\t\tops->enable\t\t= rtl8156_enable;\n+\t\tops->disable\t\t= rtl8153_disable;\n+\t\tops->up\t\t\t= rtl8156_up;\n+\t\tops->down\t\t= rtl8156_down;\n+\t\tops->unload\t\t= rtl8153_unload;\n+\t\tops->eee_get\t\t= r8153_get_eee;\n+\t\tops->eee_set\t\t= r8152_set_eee;\n+\t\tops->in_nway\t\t= rtl8153_in_nway;\n+\t\tops->hw_phy_cfg\t\t= r8156_hw_phy_cfg;\n+\t\tops->autosuspend_en\t= rtl8156_runtime_enable;\n+\t\tops->change_mtu\t\t= rtl8156_change_mtu;\n+\t\ttp->rx_buf_sz\t\t= 48 * 1024;\n+\t\ttp->support_2500full\t= 1;\n+\t\tbreak;\n+\n+\tcase RTL_VER_12:\n+\tcase RTL_VER_13:\n+\t\ttp->support_2500full\t= 1;\n+\t\tfallthrough;\n+\tcase RTL_VER_15:\n+\t\ttp->eee_en\t\t= true;\n+\t\ttp->eee_adv\t\t= MDIO_EEE_1000T | MDIO_EEE_100TX;\n+\t\tops->init\t\t= r8156b_init;\n+\t\tops->enable\t\t= rtl8156b_enable;\n+\t\tops->disable\t\t= rtl8153_disable;\n+\t\tops->up\t\t\t= rtl8156_up;\n+\t\tops->down\t\t= rtl8156_down;\n+\t\tops->unload\t\t= rtl8153_unload;\n+\t\tops->eee_get\t\t= r8153_get_eee;\n+\t\tops->eee_set\t\t= r8152_set_eee;\n+\t\tops->in_nway\t\t= rtl8153_in_nway;\n+\t\tops->hw_phy_cfg\t\t= r8156b_hw_phy_cfg;\n+\t\tops->autosuspend_en\t= rtl8156_runtime_enable;\n+\t\tops->change_mtu\t\t= rtl8156_change_mtu;\n+\t\ttp->rx_buf_sz\t\t= 48 * 1024;\n+\t\tbreak;\n+\n+\tcase RTL_VER_14:\n+\t\tops->init\t\t= r8153c_init;\n+\t\tops->enable\t\t= rtl8153_enable;\n+\t\tops->disable\t\t= rtl8153_disable;\n+\t\tops->up\t\t\t= rtl8153c_up;\n+\t\tops->down\t\t= rtl8153b_down;\n+\t\tops->unload\t\t= rtl8153_unload;\n+\t\tops->eee_get\t\t= r8153_get_eee;\n+\t\tops->eee_set\t\t= r8152_set_eee;\n+\t\tops->in_nway\t\t= rtl8153_in_nway;\n+\t\tops->hw_phy_cfg\t\t= r8153c_hw_phy_cfg;\n+\t\tops->autosuspend_en\t= rtl8153c_runtime_enable;\n+\t\tops->change_mtu\t\t= rtl8153c_change_mtu;\n+\t\ttp->rx_buf_sz\t\t= 32 * 1024;\n+\t\ttp->eee_en\t\t= true;\n+\t\ttp->eee_adv\t\t= MDIO_EEE_1000T | MDIO_EEE_100TX;\n+\t\tbreak;\n+\n \tdefault:\n \t\tret = -ENODEV;\n \t\tdev_err(&tp->intf->dev, \"Unknown Device\\n\");\n@@ -6637,11 +8650,13 @@ static int rtl_ops_init(struct r8152 *tp\n #define FIRMWARE_8153A_3\t\"rtl_nic/rtl8153a-3.fw\"\n #define FIRMWARE_8153A_4\t\"rtl_nic/rtl8153a-4.fw\"\n #define FIRMWARE_8153B_2\t\"rtl_nic/rtl8153b-2.fw\"\n+#define FIRMWARE_8153C_1\t\"rtl_nic/rtl8153c-1.fw\"\n \n MODULE_FIRMWARE(FIRMWARE_8153A_2);\n MODULE_FIRMWARE(FIRMWARE_8153A_3);\n MODULE_FIRMWARE(FIRMWARE_8153A_4);\n MODULE_FIRMWARE(FIRMWARE_8153B_2);\n+MODULE_FIRMWARE(FIRMWARE_8153C_1);\n \n static int rtl_fw_init(struct r8152 *tp)\n {\n@@ -6667,6 +8682,11 @@ static int rtl_fw_init(struct r8152 *tp)\n \t\trtl_fw->pre_fw\t\t= r8153b_pre_firmware_1;\n \t\trtl_fw->post_fw\t\t= r8153b_post_firmware_1;\n \t\tbreak;\n+\tcase RTL_VER_14:\n+\t\trtl_fw->fw_name\t\t= FIRMWARE_8153C_1;\n+\t\trtl_fw->pre_fw\t\t= r8153b_pre_firmware_1;\n+\t\trtl_fw->post_fw\t\t= r8153c_post_firmware_1;\n+\t\tbreak;\n \tdefault:\n \t\tbreak;\n \t}\n@@ -6722,6 +8742,27 @@ u8 rtl8152_get_version(struct usb_interf\n \tcase 0x6010:\n \t\tversion = RTL_VER_09;\n \t\tbreak;\n+\tcase 0x7010:\n+\t\tversion = RTL_TEST_01;\n+\t\tbreak;\n+\tcase 0x7020:\n+\t\tversion = RTL_VER_10;\n+\t\tbreak;\n+\tcase 0x7030:\n+\t\tversion = RTL_VER_11;\n+\t\tbreak;\n+\tcase 0x7400:\n+\t\tversion = RTL_VER_12;\n+\t\tbreak;\n+\tcase 0x7410:\n+\t\tversion = RTL_VER_13;\n+\t\tbreak;\n+\tcase 0x6400:\n+\t\tversion = RTL_VER_14;\n+\t\tbreak;\n+\tcase 0x7420:\n+\t\tversion = RTL_VER_15;\n+\t\tbreak;\n \tdefault:\n \t\tversion = RTL_VER_UNKNOWN;\n \t\tdev_info(&intf->dev, \"Unknown version 0x%04x\\n\", ocp_data);\n@@ -6834,12 +8875,29 @@ static int rtl8152_probe(struct usb_inte\n \t/* MTU range: 68 - 1500 or 9194 */\n \tnetdev->min_mtu = ETH_MIN_MTU;\n \tswitch (tp->version) {\n+\tcase RTL_VER_03:\n+\tcase RTL_VER_04:\n+\tcase RTL_VER_05:\n+\tcase RTL_VER_06:\n+\tcase RTL_VER_08:\n+\tcase RTL_VER_09:\n+\tcase RTL_VER_14:\n+\t\tnetdev->max_mtu = size_to_mtu(9 * 1024);\n+\t\tbreak;\n+\tcase RTL_VER_10:\n+\tcase RTL_VER_11:\n+\t\tnetdev->max_mtu = size_to_mtu(15 * 1024);\n+\t\tbreak;\n+\tcase RTL_VER_12:\n+\tcase RTL_VER_13:\n+\tcase RTL_VER_15:\n+\t\tnetdev->max_mtu = size_to_mtu(16 * 1024);\n+\t\tbreak;\n \tcase RTL_VER_01:\n \tcase RTL_VER_02:\n-\t\tnetdev->max_mtu = ETH_DATA_LEN;\n-\t\tbreak;\n+\tcase RTL_VER_07:\n \tdefault:\n-\t\tnetdev->max_mtu = size_to_mtu(9 * 1024);\n+\t\tnetdev->max_mtu = ETH_DATA_LEN;\n \t\tbreak;\n \t}\n \n@@ -6855,7 +8913,13 @@ static int rtl8152_probe(struct usb_inte\n \ttp->advertising = RTL_ADVERTISED_10_HALF | RTL_ADVERTISED_10_FULL |\n \t\t\t  RTL_ADVERTISED_100_HALF | RTL_ADVERTISED_100_FULL;\n \tif (tp->mii.supports_gmii) {\n-\t\ttp->speed = SPEED_1000;\n+\t\tif (tp->support_2500full &&\n+\t\t    tp->udev->speed >= USB_SPEED_SUPER) {\n+\t\t\ttp->speed = SPEED_2500;\n+\t\t\ttp->advertising |= RTL_ADVERTISED_2500_FULL;\n+\t\t} else {\n+\t\t\ttp->speed = SPEED_1000;\n+\t\t}\n \t\ttp->advertising |= RTL_ADVERTISED_1000_FULL;\n \t}\n \ttp->duplex = DUPLEX_FULL;\n@@ -6879,7 +8943,11 @@ static int rtl8152_probe(struct usb_inte\n \tset_ethernet_addr(tp);\n \n \tusb_set_intfdata(intf, tp);\n-\tnetif_napi_add(netdev, &tp->napi, r8152_poll, RTL8152_NAPI_WEIGHT);\n+\n+\tif (tp->support_2500full)\n+\t\tnetif_napi_add(netdev, &tp->napi, r8152_poll, 256);\n+\telse\n+\t\tnetif_napi_add(netdev, &tp->napi, r8152_poll, 64);\n \n \tret = register_netdev(netdev);\n \tif (ret != 0) {\n@@ -6915,7 +8983,8 @@ static void rtl8152_disconnect(struct us\n \t\tunregister_netdev(tp->netdev);\n \t\ttasklet_kill(&tp->tx_tl);\n \t\tcancel_delayed_work_sync(&tp->hw_phy_work);\n-\t\ttp->rtl_ops.unload(tp);\n+\t\tif (tp->rtl_ops.unload)\n+\t\t\ttp->rtl_ops.unload(tp);\n \t\trtl8152_release_firmware(tp);\n \t\tfree_netdev(tp->netdev);\n \t}\n@@ -6935,13 +9004,28 @@ static void rtl8152_disconnect(struct us\n \t.idProduct = (prod), \\\n \t.bInterfaceClass = USB_CLASS_COMM, \\\n \t.bInterfaceSubClass = USB_CDC_SUBCLASS_ETHERNET, \\\n+\t.bInterfaceProtocol = USB_CDC_PROTO_NONE \\\n+}, \\\n+{ \\\n+\t.match_flags = USB_DEVICE_ID_MATCH_INT_INFO | \\\n+\t\t       USB_DEVICE_ID_MATCH_DEVICE, \\\n+\t.idVendor = (vend), \\\n+\t.idProduct = (prod), \\\n+\t.bInterfaceClass = USB_CLASS_COMM, \\\n+\t.bInterfaceSubClass = USB_CDC_SUBCLASS_NCM, \\\n \t.bInterfaceProtocol = USB_CDC_PROTO_NONE\n \n /* table of devices that work with this driver */\n static const struct usb_device_id rtl8152_table[] = {\n+\t/* Realtek */\n \t{REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8050)},\n+\t{REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8053)},\n \t{REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8152)},\n \t{REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8153)},\n+\t{REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8155)},\n+\t{REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8156)},\n+\n+\t/* Microsoft */\n \t{REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07ab)},\n \t{REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07c6)},\n \t{REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x0927)},\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/794-v5.13-r8152-support-PHY-firmware-for-RTL8156-series.patch",
    "content": "From ca09589a72a0aa17389754fb75a5cd1a5d46818f Mon Sep 17 00:00:00 2001\nFrom: Hayes Wang <hayeswang@realtek.com>\nDate: Fri, 16 Apr 2021 16:04:36 +0800\nSubject: [PATCH] r8152: support PHY firmware for RTL8156 series\n\ncommit 4a51b0e8a0143b0e83d51d9c58c6416c3818a9f2 upstream.\n\nSupport new firmware type and method for RTL8156 series.\n\nSigned-off-by: Hayes Wang <hayeswang@realtek.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/usb/r8152.c | 563 +++++++++++++++++++++++++++++++++++++++-\n 1 file changed, 561 insertions(+), 2 deletions(-)\n\n--- a/drivers/net/usb/r8152.c\n+++ b/drivers/net/usb/r8152.c\n@@ -974,8 +974,60 @@ enum rtl8152_fw_flags {\n \tFW_FLAGS_START,\n \tFW_FLAGS_STOP,\n \tFW_FLAGS_NC,\n+\tFW_FLAGS_NC1,\n+\tFW_FLAGS_NC2,\n+\tFW_FLAGS_UC2,\n+\tFW_FLAGS_UC,\n+\tFW_FLAGS_SPEED_UP,\n+\tFW_FLAGS_VER,\n };\n \n+enum rtl8152_fw_fixup_cmd {\n+\tFW_FIXUP_AND = 0,\n+\tFW_FIXUP_OR,\n+\tFW_FIXUP_NOT,\n+\tFW_FIXUP_XOR,\n+};\n+\n+struct fw_phy_set {\n+\t__le16 addr;\n+\t__le16 data;\n+} __packed;\n+\n+struct fw_phy_speed_up {\n+\tstruct fw_block blk_hdr;\n+\t__le16 fw_offset;\n+\t__le16 version;\n+\t__le16 fw_reg;\n+\t__le16 reserved;\n+\tchar info[];\n+} __packed;\n+\n+struct fw_phy_ver {\n+\tstruct fw_block blk_hdr;\n+\tstruct fw_phy_set ver;\n+\t__le32 reserved;\n+} __packed;\n+\n+struct fw_phy_fixup {\n+\tstruct fw_block blk_hdr;\n+\tstruct fw_phy_set setting;\n+\t__le16 bit_cmd;\n+\t__le16 reserved;\n+} __packed;\n+\n+struct fw_phy_union {\n+\tstruct fw_block blk_hdr;\n+\t__le16 fw_offset;\n+\t__le16 fw_reg;\n+\tstruct fw_phy_set pre_set[2];\n+\tstruct fw_phy_set bp[8];\n+\tstruct fw_phy_set bp_en;\n+\tu8 pre_num;\n+\tu8 bp_num;\n+\tchar info[];\n+} __packed;\n+\n /**\n  * struct fw_mac - a firmware block used by RTL_FW_PLA and RTL_FW_USB.\n  *\tThe layout of the firmware block is:\n@@ -1080,6 +1132,15 @@ enum rtl_fw_type {\n \tRTL_FW_PHY_START,\n \tRTL_FW_PHY_STOP,\n \tRTL_FW_PHY_NC,\n+\tRTL_FW_PHY_FIXUP,\n+\tRTL_FW_PHY_UNION_NC,\n+\tRTL_FW_PHY_UNION_NC1,\n+\tRTL_FW_PHY_UNION_NC2,\n+\tRTL_FW_PHY_UNION_UC2,\n+\tRTL_FW_PHY_UNION_UC,\n+\tRTL_FW_PHY_UNION_MISC,\n+\tRTL_FW_PHY_SPEED_UP,\n+\tRTL_FW_PHY_VER,\n };\n \n enum rtl_version {\n@@ -3999,6 +4060,162 @@ static int rtl_post_ram_code(struct r815\n \treturn 0;\n }\n \n+static bool rtl8152_is_fw_phy_speed_up_ok(struct r8152 *tp, struct fw_phy_speed_up *phy)\n+{\n+\tu16 fw_offset;\n+\tu32 length;\n+\tbool rc = false;\n+\n+\tswitch (tp->version) {\n+\tcase RTL_VER_01:\n+\tcase RTL_VER_02:\n+\tcase RTL_VER_03:\n+\tcase RTL_VER_04:\n+\tcase RTL_VER_05:\n+\tcase RTL_VER_06:\n+\tcase RTL_VER_07:\n+\tcase RTL_VER_08:\n+\tcase RTL_VER_09:\n+\tcase RTL_VER_10:\n+\tcase RTL_VER_11:\n+\tcase RTL_VER_12:\n+\tcase RTL_VER_14:\n+\t\tgoto out;\n+\tcase RTL_VER_13:\n+\tcase RTL_VER_15:\n+\tdefault:\n+\t\tbreak;\n+\t}\n+\n+\tfw_offset = __le16_to_cpu(phy->fw_offset);\n+\tlength = __le32_to_cpu(phy->blk_hdr.length);\n+\tif (fw_offset < sizeof(*phy) || length <= fw_offset) {\n+\t\tdev_err(&tp->intf->dev, \"invalid fw_offset\\n\");\n+\t\tgoto out;\n+\t}\n+\n+\tlength -= fw_offset;\n+\tif (length & 3) {\n+\t\tdev_err(&tp->intf->dev, \"invalid block length\\n\");\n+\t\tgoto out;\n+\t}\n+\n+\tif (__le16_to_cpu(phy->fw_reg) != 0x9A00) {\n+\t\tdev_err(&tp->intf->dev, \"invalid register to load firmware\\n\");\n+\t\tgoto out;\n+\t}\n+\n+\trc = true;\n+out:\n+\treturn rc;\n+}\n+\n+static bool rtl8152_is_fw_phy_ver_ok(struct r8152 *tp, struct fw_phy_ver *ver)\n+{\n+\tbool rc = false;\n+\n+\tswitch (tp->version) {\n+\tcase RTL_VER_10:\n+\tcase RTL_VER_11:\n+\tcase RTL_VER_12:\n+\tcase RTL_VER_13:\n+\tcase RTL_VER_15:\n+\t\tbreak;\n+\tdefault:\n+\t\tgoto out;\n+\t}\n+\n+\tif (__le32_to_cpu(ver->blk_hdr.length) != sizeof(*ver)) {\n+\t\tdev_err(&tp->intf->dev, \"invalid block length\\n\");\n+\t\tgoto out;\n+\t}\n+\n+\tif (__le16_to_cpu(ver->ver.addr) != SRAM_GPHY_FW_VER) {\n+\t\tdev_err(&tp->intf->dev, \"invalid phy ver addr\\n\");\n+\t\tgoto out;\n+\t}\n+\n+\trc = true;\n+out:\n+\treturn rc;\n+}\n+\n+static bool rtl8152_is_fw_phy_fixup_ok(struct r8152 *tp, struct fw_phy_fixup *fix)\n+{\n+\tbool rc = false;\n+\n+\tswitch (tp->version) {\n+\tcase RTL_VER_10:\n+\tcase RTL_VER_11:\n+\tcase RTL_VER_12:\n+\tcase RTL_VER_13:\n+\tcase RTL_VER_15:\n+\t\tbreak;\n+\tdefault:\n+\t\tgoto out;\n+\t}\n+\n+\tif (__le32_to_cpu(fix->blk_hdr.length) != sizeof(*fix)) {\n+\t\tdev_err(&tp->intf->dev, \"invalid block length\\n\");\n+\t\tgoto out;\n+\t}\n+\n+\tif (__le16_to_cpu(fix->setting.addr) != OCP_PHY_PATCH_CMD ||\n+\t    __le16_to_cpu(fix->setting.data) != BIT(7)) {\n+\t\tdev_err(&tp->intf->dev, \"invalid phy fixup\\n\");\n+\t\tgoto out;\n+\t}\n+\n+\trc = true;\n+out:\n+\treturn rc;\n+}\n+\n+static bool rtl8152_is_fw_phy_union_ok(struct r8152 *tp, struct fw_phy_union *phy)\n+{\n+\tu16 fw_offset;\n+\tu32 length;\n+\tbool rc = false;\n+\n+\tswitch (tp->version) {\n+\tcase RTL_VER_10:\n+\tcase RTL_VER_11:\n+\tcase RTL_VER_12:\n+\tcase RTL_VER_13:\n+\tcase RTL_VER_15:\n+\t\tbreak;\n+\tdefault:\n+\t\tgoto out;\n+\t}\n+\n+\tfw_offset = __le16_to_cpu(phy->fw_offset);\n+\tlength = __le32_to_cpu(phy->blk_hdr.length);\n+\tif (fw_offset < sizeof(*phy) || length <= fw_offset) {\n+\t\tdev_err(&tp->intf->dev, \"invalid fw_offset\\n\");\n+\t\tgoto out;\n+\t}\n+\n+\tlength -= fw_offset;\n+\tif (length & 1) {\n+\t\tdev_err(&tp->intf->dev, \"invalid block length\\n\");\n+\t\tgoto out;\n+\t}\n+\n+\tif (phy->pre_num > 2) {\n+\t\tdev_err(&tp->intf->dev, \"invalid pre_num %d\\n\", phy->pre_num);\n+\t\tgoto out;\n+\t}\n+\n+\tif (phy->bp_num > 8) {\n+\t\tdev_err(&tp->intf->dev, \"invalid bp_num %d\\n\", phy->bp_num);\n+\t\tgoto out;\n+\t}\n+\n+\trc = true;\n+out:\n+\treturn rc;\n+}\n+\n static bool rtl8152_is_fw_phy_nc_ok(struct r8152 *tp, struct fw_phy_nc *phy)\n {\n \tu32 length;\n@@ -4319,6 +4536,10 @@ static long rtl8152_check_firmware(struc\n \t\tcase RTL_FW_PHY_START:\n \t\t\tif (test_bit(FW_FLAGS_START, &fw_flags) ||\n \t\t\t    test_bit(FW_FLAGS_NC, &fw_flags) ||\n+\t\t\t    test_bit(FW_FLAGS_NC1, &fw_flags) ||\n+\t\t\t    test_bit(FW_FLAGS_NC2, &fw_flags) ||\n+\t\t\t    test_bit(FW_FLAGS_UC2, &fw_flags) ||\n+\t\t\t    test_bit(FW_FLAGS_UC, &fw_flags) ||\n \t\t\t    test_bit(FW_FLAGS_STOP, &fw_flags)) {\n \t\t\t\tdev_err(&tp->intf->dev,\n \t\t\t\t\t\"check PHY_START fail\\n\");\n@@ -4367,7 +4588,153 @@ static long rtl8152_check_firmware(struc\n \t\t\t\tgoto fail;\n \t\t\t}\n \t\t\t__set_bit(FW_FLAGS_NC, &fw_flags);\n+\t\t\tbreak;\n+\t\tcase RTL_FW_PHY_UNION_NC:\n+\t\t\tif (!test_bit(FW_FLAGS_START, &fw_flags) ||\n+\t\t\t    test_bit(FW_FLAGS_NC1, &fw_flags) ||\n+\t\t\t    test_bit(FW_FLAGS_NC2, &fw_flags) ||\n+\t\t\t    test_bit(FW_FLAGS_UC2, &fw_flags) ||\n+\t\t\t    test_bit(FW_FLAGS_UC, &fw_flags) ||\n+\t\t\t    test_bit(FW_FLAGS_STOP, &fw_flags)) {\n+\t\t\t\tdev_err(&tp->intf->dev, \"PHY_UNION_NC out of order\\n\");\n+\t\t\t\tgoto fail;\n+\t\t\t}\n+\n+\t\t\tif (test_bit(FW_FLAGS_NC, &fw_flags)) {\n+\t\t\t\tdev_err(&tp->intf->dev, \"multiple PHY_UNION_NC encountered\\n\");\n+\t\t\t\tgoto fail;\n+\t\t\t}\n \n+\t\t\tif (!rtl8152_is_fw_phy_union_ok(tp, (struct fw_phy_union *)block)) {\n+\t\t\t\tdev_err(&tp->intf->dev, \"check PHY_UNION_NC failed\\n\");\n+\t\t\t\tgoto fail;\n+\t\t\t}\n+\t\t\t__set_bit(FW_FLAGS_NC, &fw_flags);\n+\t\t\tbreak;\n+\t\tcase RTL_FW_PHY_UNION_NC1:\n+\t\t\tif (!test_bit(FW_FLAGS_START, &fw_flags) ||\n+\t\t\t    test_bit(FW_FLAGS_NC2, &fw_flags) ||\n+\t\t\t    test_bit(FW_FLAGS_UC2, &fw_flags) ||\n+\t\t\t    test_bit(FW_FLAGS_UC, &fw_flags) ||\n+\t\t\t    test_bit(FW_FLAGS_STOP, &fw_flags)) {\n+\t\t\t\tdev_err(&tp->intf->dev, \"PHY_UNION_NC1 out of order\\n\");\n+\t\t\t\tgoto fail;\n+\t\t\t}\n+\n+\t\t\tif (test_bit(FW_FLAGS_NC1, &fw_flags)) {\n+\t\t\t\tdev_err(&tp->intf->dev, \"multiple PHY NC1 encountered\\n\");\n+\t\t\t\tgoto fail;\n+\t\t\t}\n+\n+\t\t\tif (!rtl8152_is_fw_phy_union_ok(tp, (struct fw_phy_union *)block)) {\n+\t\t\t\tdev_err(&tp->intf->dev, \"check PHY_UNION_NC1 failed\\n\");\n+\t\t\t\tgoto fail;\n+\t\t\t}\n+\t\t\t__set_bit(FW_FLAGS_NC1, &fw_flags);\n+\t\t\tbreak;\n+\t\tcase RTL_FW_PHY_UNION_NC2:\n+\t\t\tif (!test_bit(FW_FLAGS_START, &fw_flags) ||\n+\t\t\t    test_bit(FW_FLAGS_UC2, &fw_flags) ||\n+\t\t\t    test_bit(FW_FLAGS_UC, &fw_flags) ||\n+\t\t\t    test_bit(FW_FLAGS_STOP, &fw_flags)) {\n+\t\t\t\tdev_err(&tp->intf->dev, \"PHY_UNION_NC2 out of order\\n\");\n+\t\t\t\tgoto fail;\n+\t\t\t}\n+\n+\t\t\tif (test_bit(FW_FLAGS_NC2, &fw_flags)) {\n+\t\t\t\tdev_err(&tp->intf->dev, \"multiple PHY NC2 encountered\\n\");\n+\t\t\t\tgoto fail;\n+\t\t\t}\n+\n+\t\t\tif (!rtl8152_is_fw_phy_union_ok(tp, (struct fw_phy_union *)block)) {\n+\t\t\t\tdev_err(&tp->intf->dev, \"check PHY_UNION_NC2 failed\\n\");\n+\t\t\t\tgoto fail;\n+\t\t\t}\n+\t\t\t__set_bit(FW_FLAGS_NC2, &fw_flags);\n+\t\t\tbreak;\n+\t\tcase RTL_FW_PHY_UNION_UC2:\n+\t\t\tif (!test_bit(FW_FLAGS_START, &fw_flags) ||\n+\t\t\t    test_bit(FW_FLAGS_UC, &fw_flags) ||\n+\t\t\t    test_bit(FW_FLAGS_STOP, &fw_flags)) {\n+\t\t\t\tdev_err(&tp->intf->dev, \"PHY_UNION_UC2 out of order\\n\");\n+\t\t\t\tgoto fail;\n+\t\t\t}\n+\n+\t\t\tif (test_bit(FW_FLAGS_UC2, &fw_flags)) {\n+\t\t\t\tdev_err(&tp->intf->dev, \"multiple PHY UC2 encountered\\n\");\n+\t\t\t\tgoto fail;\n+\t\t\t}\n+\n+\t\t\tif (!rtl8152_is_fw_phy_union_ok(tp, (struct fw_phy_union *)block)) {\n+\t\t\t\tdev_err(&tp->intf->dev, \"check PHY_UNION_UC2 failed\\n\");\n+\t\t\t\tgoto fail;\n+\t\t\t}\n+\t\t\t__set_bit(FW_FLAGS_UC2, &fw_flags);\n+\t\t\tbreak;\n+\t\tcase RTL_FW_PHY_UNION_UC:\n+\t\t\tif (!test_bit(FW_FLAGS_START, &fw_flags) ||\n+\t\t\t    test_bit(FW_FLAGS_STOP, &fw_flags)) {\n+\t\t\t\tdev_err(&tp->intf->dev, \"PHY_UNION_UC out of order\\n\");\n+\t\t\t\tgoto fail;\n+\t\t\t}\n+\n+\t\t\tif (test_bit(FW_FLAGS_UC, &fw_flags)) {\n+\t\t\t\tdev_err(&tp->intf->dev, \"multiple PHY UC encountered\\n\");\n+\t\t\t\tgoto fail;\n+\t\t\t}\n+\n+\t\t\tif (!rtl8152_is_fw_phy_union_ok(tp, (struct fw_phy_union *)block)) {\n+\t\t\t\tdev_err(&tp->intf->dev, \"check PHY_UNION_UC failed\\n\");\n+\t\t\t\tgoto fail;\n+\t\t\t}\n+\t\t\t__set_bit(FW_FLAGS_UC, &fw_flags);\n+\t\t\tbreak;\n+\t\tcase RTL_FW_PHY_UNION_MISC:\n+\t\t\tif (!rtl8152_is_fw_phy_union_ok(tp, (struct fw_phy_union *)block)) {\n+\t\t\t\tdev_err(&tp->intf->dev, \"check RTL_FW_PHY_UNION_MISC failed\\n\");\n+\t\t\t\tgoto fail;\n+\t\t\t}\n+\t\t\tbreak;\n+\t\tcase RTL_FW_PHY_FIXUP:\n+\t\t\tif (!rtl8152_is_fw_phy_fixup_ok(tp, (struct fw_phy_fixup *)block)) {\n+\t\t\t\tdev_err(&tp->intf->dev, \"check PHY fixup failed\\n\");\n+\t\t\t\tgoto fail;\n+\t\t\t}\n+\t\t\tbreak;\n+\t\tcase RTL_FW_PHY_SPEED_UP:\n+\t\t\tif (test_bit(FW_FLAGS_SPEED_UP, &fw_flags)) {\n+\t\t\t\tdev_err(&tp->intf->dev, \"multiple PHY firmware encountered\");\n+\t\t\t\tgoto fail;\n+\t\t\t}\n+\n+\t\t\tif (!rtl8152_is_fw_phy_speed_up_ok(tp, (struct fw_phy_speed_up *)block)) {\n+\t\t\t\tdev_err(&tp->intf->dev, \"check PHY speed up failed\\n\");\n+\t\t\t\tgoto fail;\n+\t\t\t}\n+\t\t\t__set_bit(FW_FLAGS_SPEED_UP, &fw_flags);\n+\t\t\tbreak;\n+\t\tcase RTL_FW_PHY_VER:\n+\t\t\tif (test_bit(FW_FLAGS_START, &fw_flags) ||\n+\t\t\t    test_bit(FW_FLAGS_NC, &fw_flags) ||\n+\t\t\t    test_bit(FW_FLAGS_NC1, &fw_flags) ||\n+\t\t\t    test_bit(FW_FLAGS_NC2, &fw_flags) ||\n+\t\t\t    test_bit(FW_FLAGS_UC2, &fw_flags) ||\n+\t\t\t    test_bit(FW_FLAGS_UC, &fw_flags) ||\n+\t\t\t    test_bit(FW_FLAGS_STOP, &fw_flags)) {\n+\t\t\t\tdev_err(&tp->intf->dev, \"Invalid order to set PHY version\\n\");\n+\t\t\t\tgoto fail;\n+\t\t\t}\n+\n+\t\t\tif (test_bit(FW_FLAGS_VER, &fw_flags)) {\n+\t\t\t\tdev_err(&tp->intf->dev, \"multiple PHY version encountered\");\n+\t\t\t\tgoto fail;\n+\t\t\t}\n+\n+\t\t\tif (!rtl8152_is_fw_phy_ver_ok(tp, (struct fw_phy_ver *)block)) {\n+\t\t\t\tdev_err(&tp->intf->dev, \"check PHY version failed\\n\");\n+\t\t\t\tgoto fail;\n+\t\t\t}\n+\t\t\t__set_bit(FW_FLAGS_VER, &fw_flags);\n \t\t\tbreak;\n \t\tdefault:\n \t\t\tdev_warn(&tp->intf->dev, \"Unknown type %u is found\\n\",\n@@ -4390,6 +4757,143 @@ fail:\n \treturn ret;\n }\n \n+static void rtl_ram_code_speed_up(struct r8152 *tp, struct fw_phy_speed_up *phy, bool wait)\n+{\n+\tu32 len;\n+\tu8 *data;\n+\n+\tif (sram_read(tp, SRAM_GPHY_FW_VER) >= __le16_to_cpu(phy->version)) {\n+\t\tdev_dbg(&tp->intf->dev, \"PHY firmware has been the newest\\n\");\n+\t\treturn;\n+\t}\n+\n+\tlen = __le32_to_cpu(phy->blk_hdr.length);\n+\tlen -= __le16_to_cpu(phy->fw_offset);\n+\tdata = (u8 *)phy + __le16_to_cpu(phy->fw_offset);\n+\n+\tif (rtl_phy_patch_request(tp, true, wait))\n+\t\treturn;\n+\n+\twhile (len) {\n+\t\tu32 ocp_data, size;\n+\t\tint i;\n+\n+\t\tif (len < 2048)\n+\t\t\tsize = len;\n+\t\telse\n+\t\t\tsize = 2048;\n+\n+\t\tocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_GPHY_CTRL);\n+\t\tocp_data |= GPHY_PATCH_DONE | BACKUP_RESTRORE;\n+\t\tocp_write_word(tp, MCU_TYPE_USB, USB_GPHY_CTRL, ocp_data);\n+\n+\t\tgeneric_ocp_write(tp, __le16_to_cpu(phy->fw_reg), 0xff, size, data, MCU_TYPE_USB);\n+\n+\t\tdata += size;\n+\t\tlen -= size;\n+\n+\t\tocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_POL_GPIO_CTRL);\n+\t\tocp_data |= POL_GPHY_PATCH;\n+\t\tocp_write_word(tp, MCU_TYPE_PLA, PLA_POL_GPIO_CTRL, ocp_data);\n+\n+\t\tfor (i = 0; i < 1000; i++) {\n+\t\t\tif (!(ocp_read_word(tp, MCU_TYPE_PLA, PLA_POL_GPIO_CTRL) & POL_GPHY_PATCH))\n+\t\t\t\tbreak;\n+\t\t}\n+\n+\t\tif (i == 1000) {\n+\t\t\tdev_err(&tp->intf->dev, \"ram code speedup mode timeout\\n\");\n+\t\t\treturn;\n+\t\t}\n+\t}\n+\n+\tocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, tp->ocp_base);\n+\trtl_phy_patch_request(tp, false, wait);\n+\n+\tif (sram_read(tp, SRAM_GPHY_FW_VER) == __le16_to_cpu(phy->version))\n+\t\tdev_dbg(&tp->intf->dev, \"successfully applied %s\\n\", phy->info);\n+\telse\n+\t\tdev_err(&tp->intf->dev, \"ram code speedup mode fail\\n\");\n+}\n+\n+static int rtl8152_fw_phy_ver(struct r8152 *tp, struct fw_phy_ver *phy_ver)\n+{\n+\tu16 ver_addr, ver;\n+\n+\tver_addr = __le16_to_cpu(phy_ver->ver.addr);\n+\tver = __le16_to_cpu(phy_ver->ver.data);\n+\n+\tif (sram_read(tp, ver_addr) >= ver) {\n+\t\tdev_dbg(&tp->intf->dev, \"PHY firmware has been the newest\\n\");\n+\t\treturn 0;\n+\t}\n+\n+\tsram_write(tp, ver_addr, ver);\n+\n+\tdev_dbg(&tp->intf->dev, \"PHY firmware version %x\\n\", ver);\n+\n+\treturn ver;\n+}\n+\n+static void rtl8152_fw_phy_fixup(struct r8152 *tp, struct fw_phy_fixup *fix)\n+{\n+\tu16 addr, data;\n+\n+\taddr = __le16_to_cpu(fix->setting.addr);\n+\tdata = ocp_reg_read(tp, addr);\n+\n+\tswitch (__le16_to_cpu(fix->bit_cmd)) {\n+\tcase FW_FIXUP_AND:\n+\t\tdata &= __le16_to_cpu(fix->setting.data);\n+\t\tbreak;\n+\tcase FW_FIXUP_OR:\n+\t\tdata |= __le16_to_cpu(fix->setting.data);\n+\t\tbreak;\n+\tcase FW_FIXUP_NOT:\n+\t\tdata &= ~__le16_to_cpu(fix->setting.data);\n+\t\tbreak;\n+\tcase FW_FIXUP_XOR:\n+\t\tdata ^= __le16_to_cpu(fix->setting.data);\n+\t\tbreak;\n+\tdefault:\n+\t\treturn;\n+\t}\n+\n+\tocp_reg_write(tp, addr, data);\n+\n+\tdev_dbg(&tp->intf->dev, \"applied ocp %x %x\\n\", addr, data);\n+}\n+\n+static void rtl8152_fw_phy_union_apply(struct r8152 *tp, struct fw_phy_union *phy)\n+{\n+\t__le16 *data;\n+\tu32 length;\n+\tint i, num;\n+\n+\tnum = phy->pre_num;\n+\tfor (i = 0; i < num; i++)\n+\t\tsram_write(tp, __le16_to_cpu(phy->pre_set[i].addr),\n+\t\t\t   __le16_to_cpu(phy->pre_set[i].data));\n+\n+\tlength = __le32_to_cpu(phy->blk_hdr.length);\n+\tlength -= __le16_to_cpu(phy->fw_offset);\n+\tnum = length / 2;\n+\tdata = (__le16 *)((u8 *)phy + __le16_to_cpu(phy->fw_offset));\n+\n+\tocp_reg_write(tp, OCP_SRAM_ADDR, __le16_to_cpu(phy->fw_reg));\n+\tfor (i = 0; i < num; i++)\n+\t\tocp_reg_write(tp, OCP_SRAM_DATA, __le16_to_cpu(data[i]));\n+\n+\tnum = phy->bp_num;\n+\tfor (i = 0; i < num; i++)\n+\t\tsram_write(tp, __le16_to_cpu(phy->bp[i].addr), __le16_to_cpu(phy->bp[i].data));\n+\n+\tif (phy->bp_num && phy->bp_en.addr)\n+\t\tsram_write(tp, __le16_to_cpu(phy->bp_en.addr), __le16_to_cpu(phy->bp_en.data));\n+\n+\tdev_dbg(&tp->intf->dev, \"successfully applied %s\\n\", phy->info);\n+}\n+\n static void rtl8152_fw_phy_nc_apply(struct r8152 *tp, struct fw_phy_nc *phy)\n {\n \tu16 mode_reg, bp_index;\n@@ -4443,6 +4947,12 @@ static void rtl8152_fw_mac_apply(struct\n \t\treturn;\n \t}\n \n+\tfw_ver_reg = __le16_to_cpu(mac->fw_ver_reg);\n+\tif (fw_ver_reg && ocp_read_byte(tp, MCU_TYPE_USB, fw_ver_reg) >= mac->fw_ver_data) {\n+\t\tdev_dbg(&tp->intf->dev, \"%s firmware has been the newest\\n\", type ? \"PLA\" : \"USB\");\n+\t\treturn;\n+\t}\n+\n \trtl_clear_bp(tp, type);\n \n \t/* Enable backup/restore of MACDBG. This is required after clearing PLA\n@@ -4478,7 +4988,6 @@ static void rtl8152_fw_mac_apply(struct\n \t\tocp_write_word(tp, type, bp_en_addr,\n \t\t\t       __le16_to_cpu(mac->bp_en_value));\n \n-\tfw_ver_reg = __le16_to_cpu(mac->fw_ver_reg);\n \tif (fw_ver_reg)\n \t\tocp_write_byte(tp, MCU_TYPE_USB, fw_ver_reg,\n \t\t\t       mac->fw_ver_data);\n@@ -4493,7 +5002,7 @@ static void rtl8152_apply_firmware(struc\n \tstruct fw_header *fw_hdr;\n \tstruct fw_phy_patch_key *key;\n \tu16 key_addr = 0;\n-\tint i;\n+\tint i, patch_phy = 1;\n \n \tif (IS_ERR_OR_NULL(rtl_fw->fw))\n \t\treturn;\n@@ -4515,17 +5024,40 @@ static void rtl8152_apply_firmware(struc\n \t\t\trtl8152_fw_mac_apply(tp, (struct fw_mac *)block);\n \t\t\tbreak;\n \t\tcase RTL_FW_PHY_START:\n+\t\t\tif (!patch_phy)\n+\t\t\t\tbreak;\n \t\t\tkey = (struct fw_phy_patch_key *)block;\n \t\t\tkey_addr = __le16_to_cpu(key->key_reg);\n \t\t\trtl_pre_ram_code(tp, key_addr, __le16_to_cpu(key->key_data), !power_cut);\n \t\t\tbreak;\n \t\tcase RTL_FW_PHY_STOP:\n+\t\t\tif (!patch_phy)\n+\t\t\t\tbreak;\n \t\t\tWARN_ON(!key_addr);\n \t\t\trtl_post_ram_code(tp, key_addr, !power_cut);\n \t\t\tbreak;\n \t\tcase RTL_FW_PHY_NC:\n \t\t\trtl8152_fw_phy_nc_apply(tp, (struct fw_phy_nc *)block);\n \t\t\tbreak;\n+\t\tcase RTL_FW_PHY_VER:\n+\t\t\tpatch_phy = rtl8152_fw_phy_ver(tp, (struct fw_phy_ver *)block);\n+\t\t\tbreak;\n+\t\tcase RTL_FW_PHY_UNION_NC:\n+\t\tcase RTL_FW_PHY_UNION_NC1:\n+\t\tcase RTL_FW_PHY_UNION_NC2:\n+\t\tcase RTL_FW_PHY_UNION_UC2:\n+\t\tcase RTL_FW_PHY_UNION_UC:\n+\t\tcase RTL_FW_PHY_UNION_MISC:\n+\t\t\tif (patch_phy)\n+\t\t\t\trtl8152_fw_phy_union_apply(tp, (struct fw_phy_union *)block);\n+\t\t\tbreak;\n+\t\tcase RTL_FW_PHY_FIXUP:\n+\t\t\tif (patch_phy)\n+\t\t\t\trtl8152_fw_phy_fixup(tp, (struct fw_phy_fixup *)block);\n+\t\t\tbreak;\n+\t\tcase RTL_FW_PHY_SPEED_UP:\n+\t\t\trtl_ram_code_speed_up(tp, (struct fw_phy_speed_up *)block, !power_cut);\n+\t\t\tbreak;\n \t\tdefault:\n \t\t\tbreak;\n \t\t}\n@@ -5033,6 +5565,21 @@ static int r8153c_post_firmware_1(struct\n \treturn 0;\n }\n \n+static int r8156a_post_firmware_1(struct r8152 *tp)\n+{\n+\tu32 ocp_data;\n+\n+\tocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1);\n+\tocp_data |= FW_IP_RESET_EN;\n+\tocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1, ocp_data);\n+\n+\t/* Modify U3PHY parameter for compatibility issue */\n+\tocp_write_dword(tp, MCU_TYPE_USB, USB_UPHY3_MDCMDIO, 0x4026840e);\n+\tocp_write_dword(tp, MCU_TYPE_USB, USB_UPHY3_MDCMDIO, 0x4001acc9);\n+\n+\treturn 0;\n+}\n+\n static void r8153_aldps_en(struct r8152 *tp, bool enable)\n {\n \tu16 data;\n@@ -8651,12 +9198,16 @@ static int rtl_ops_init(struct r8152 *tp\n #define FIRMWARE_8153A_4\t\"rtl_nic/rtl8153a-4.fw\"\n #define FIRMWARE_8153B_2\t\"rtl_nic/rtl8153b-2.fw\"\n #define FIRMWARE_8153C_1\t\"rtl_nic/rtl8153c-1.fw\"\n+#define FIRMWARE_8156A_2\t\"rtl_nic/rtl8156a-2.fw\"\n+#define FIRMWARE_8156B_2\t\"rtl_nic/rtl8156b-2.fw\"\n \n MODULE_FIRMWARE(FIRMWARE_8153A_2);\n MODULE_FIRMWARE(FIRMWARE_8153A_3);\n MODULE_FIRMWARE(FIRMWARE_8153A_4);\n MODULE_FIRMWARE(FIRMWARE_8153B_2);\n MODULE_FIRMWARE(FIRMWARE_8153C_1);\n+MODULE_FIRMWARE(FIRMWARE_8156A_2);\n+MODULE_FIRMWARE(FIRMWARE_8156B_2);\n \n static int rtl_fw_init(struct r8152 *tp)\n {\n@@ -8682,6 +9233,14 @@ static int rtl_fw_init(struct r8152 *tp)\n \t\trtl_fw->pre_fw\t\t= r8153b_pre_firmware_1;\n \t\trtl_fw->post_fw\t\t= r8153b_post_firmware_1;\n \t\tbreak;\n+\tcase RTL_VER_11:\n+\t\trtl_fw->fw_name\t\t= FIRMWARE_8156A_2;\n+\t\trtl_fw->post_fw\t\t= r8156a_post_firmware_1;\n+\t\tbreak;\n+\tcase RTL_VER_13:\n+\tcase RTL_VER_15:\n+\t\trtl_fw->fw_name\t\t= FIRMWARE_8156B_2;\n+\t\tbreak;\n \tcase RTL_VER_14:\n \t\trtl_fw->fw_name\t\t= FIRMWARE_8153C_1;\n \t\trtl_fw->pre_fw\t\t= r8153b_pre_firmware_1;\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/795-v5.13-r8152-search-the-configuration-of-vendor-mode.patch",
    "content": "From 579f58dd2819910354753bc5489fc1588fe9cfe2 Mon Sep 17 00:00:00 2001\nFrom: Hayes Wang <hayeswang@realtek.com>\nDate: Fri, 16 Apr 2021 16:04:37 +0800\nSubject: [PATCH] r8152: search the configuration of vendor mode\n\ncommit c2198943e33b100ed21dfb636c8fa6baef841e9d upstream.\n\nThe vendor mode is not always at config #1, so it is necessary to\nset the correct configuration number.\n\nSigned-off-by: Hayes Wang <hayeswang@realtek.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/usb/r8152.c | 39 +++++++++++++++++++++++++++++++++++----\n 1 file changed, 35 insertions(+), 4 deletions(-)\n\n--- a/drivers/net/usb/r8152.c\n+++ b/drivers/net/usb/r8152.c\n@@ -29,7 +29,7 @@\n #include <linux/usb/r8152.h>\n \n /* Information for net-next */\n-#define NETNEXT_VERSION\t\t\"11\"\n+#define NETNEXT_VERSION\t\t\"12\"\n \n /* Information for net */\n #define NET_VERSION\t\t\"11\"\n@@ -8108,6 +8108,39 @@ static void r8156b_init(struct r8152 *tp\n \ttp->coalesce = 15000;\t/* 15 us */\n }\n \n+static bool rtl_vendor_mode(struct usb_interface *intf)\n+{\n+\tstruct usb_host_interface *alt = intf->cur_altsetting;\n+\tstruct usb_device *udev;\n+\tstruct usb_host_config *c;\n+\tint i, num_configs;\n+\n+\tif (alt->desc.bInterfaceClass == USB_CLASS_VENDOR_SPEC)\n+\t\treturn true;\n+\n+\t/* The vendor mode is not always config #1, so to find it out. */\n+\tudev = interface_to_usbdev(intf);\n+\tc = udev->config;\n+\tnum_configs = udev->descriptor.bNumConfigurations;\n+\tfor (i = 0; i < num_configs; (i++, c++)) {\n+\t\tstruct usb_interface_descriptor\t*desc = NULL;\n+\n+\t\tif (c->desc.bNumInterfaces > 0)\n+\t\t\tdesc = &c->intf_cache[0]->altsetting->desc;\n+\t\telse\n+\t\t\tcontinue;\n+\n+\t\tif (desc->bInterfaceClass == USB_CLASS_VENDOR_SPEC) {\n+\t\t\tusb_driver_set_configuration(udev, c->desc.bConfigurationValue);\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\n+\tWARN_ON_ONCE(i == num_configs);\n+\n+\treturn false;\n+}\n+\n static int rtl8152_pre_reset(struct usb_interface *intf)\n {\n \tstruct r8152 *tp = usb_get_intfdata(intf);\n@@ -9346,10 +9379,8 @@ static int rtl8152_probe(struct usb_inte\n \tif (version == RTL_VER_UNKNOWN)\n \t\treturn -ENODEV;\n \n-\tif (udev->actconfig->desc.bConfigurationValue != 1) {\n-\t\tusb_driver_set_configuration(udev, 1);\n+\tif (!rtl_vendor_mode(intf))\n \t\treturn -ENODEV;\n-\t}\n \n \tif (intf->cur_altsetting->desc.bNumEndpoints < 3)\n \t\treturn -ENODEV;\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/800-v5.13-0001-firmware-bcm47xx_nvram-rename-finding-function-and-i.patch",
    "content": "From fb009cbdd0693bd633f11e99526617b3d392cfad Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Mon, 8 Mar 2021 10:03:16 +0100\nSubject: [PATCH] firmware: bcm47xx_nvram: rename finding function and its\n variables\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\n1. Use \"bcm47xx_\" function name prefix for consistency\n2. It takes flash start as argument so s/iobase/flash_start/\n3. \"off\" was used for finding flash end so just call it \"flash_size\"\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nSigned-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>\n---\n drivers/firmware/broadcom/bcm47xx_nvram.c | 24 ++++++++++++-----------\n 1 file changed, 13 insertions(+), 11 deletions(-)\n\n--- a/drivers/firmware/broadcom/bcm47xx_nvram.c\n+++ b/drivers/firmware/broadcom/bcm47xx_nvram.c\n@@ -48,11 +48,13 @@ static u32 find_nvram_size(void __iomem\n \treturn 0;\n }\n \n-/* Probe for NVRAM header */\n-static int nvram_find_and_copy(void __iomem *iobase, u32 lim)\n+/**\n+ * bcm47xx_nvram_find_and_copy - find NVRAM on flash mapping & copy it\n+ */\n+static int bcm47xx_nvram_find_and_copy(void __iomem *flash_start, size_t res_size)\n {\n \tstruct nvram_header __iomem *header;\n-\tu32 off;\n+\tsize_t flash_size;\n \tu32 size;\n \n \tif (nvram_len) {\n@@ -61,25 +63,25 @@ static int nvram_find_and_copy(void __io\n \t}\n \n \t/* TODO: when nvram is on nand flash check for bad blocks first. */\n-\toff = FLASH_MIN;\n-\twhile (off <= lim) {\n+\tflash_size = FLASH_MIN;\n+\twhile (flash_size <= res_size) {\n \t\t/* Windowed flash access */\n-\t\tsize = find_nvram_size(iobase + off);\n+\t\tsize = find_nvram_size(flash_start + flash_size);\n \t\tif (size) {\n-\t\t\theader = (struct nvram_header *)(iobase + off - size);\n+\t\t\theader = (struct nvram_header *)(flash_start + flash_size - size);\n \t\t\tgoto found;\n \t\t}\n-\t\toff <<= 1;\n+\t\tflash_size <<= 1;\n \t}\n \n \t/* Try embedded NVRAM at 4 KB and 1 KB as last resorts */\n-\theader = (struct nvram_header *)(iobase + 4096);\n+\theader = (struct nvram_header *)(flash_start + 4096);\n \tif (header->magic == NVRAM_MAGIC) {\n \t\tsize = NVRAM_SPACE;\n \t\tgoto found;\n \t}\n \n-\theader = (struct nvram_header *)(iobase + 1024);\n+\theader = (struct nvram_header *)(flash_start + 1024);\n \tif (header->magic == NVRAM_MAGIC) {\n \t\tsize = NVRAM_SPACE;\n \t\tgoto found;\n@@ -124,7 +126,7 @@ int bcm47xx_nvram_init_from_mem(u32 base\n \tif (!iobase)\n \t\treturn -ENOMEM;\n \n-\terr = nvram_find_and_copy(iobase, lim);\n+\terr = bcm47xx_nvram_find_and_copy(iobase, lim);\n \n \tiounmap(iobase);\n \n"
  },
  {
    "path": "target/linux/generic/backport-5.10/800-v5.13-0002-firmware-bcm47xx_nvram-add-helper-checking-for-NVRAM.patch",
    "content": "From 0a24b51a3264a3f942a75025ea5ff6133c8989b0 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Mon, 8 Mar 2021 10:03:17 +0100\nSubject: [PATCH] firmware: bcm47xx_nvram: add helper checking for NVRAM\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nThis avoids duplicating code doing casting and checking for NVRAM magic.\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nSigned-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>\n---\n drivers/firmware/broadcom/bcm47xx_nvram.c | 30 ++++++++++++++---------\n 1 file changed, 18 insertions(+), 12 deletions(-)\n\n--- a/drivers/firmware/broadcom/bcm47xx_nvram.c\n+++ b/drivers/firmware/broadcom/bcm47xx_nvram.c\n@@ -34,14 +34,20 @@ static char nvram_buf[NVRAM_SPACE];\n static size_t nvram_len;\n static const u32 nvram_sizes[] = {0x6000, 0x8000, 0xF000, 0x10000};\n \n+/**\n+ * bcm47xx_nvram_is_valid - check for a valid NVRAM at specified memory\n+ */\n+static bool bcm47xx_nvram_is_valid(void __iomem *nvram)\n+{\n+\treturn ((struct nvram_header *)nvram)->magic == NVRAM_MAGIC;\n+}\n+\n static u32 find_nvram_size(void __iomem *end)\n {\n-\tstruct nvram_header __iomem *header;\n \tint i;\n \n \tfor (i = 0; i < ARRAY_SIZE(nvram_sizes); i++) {\n-\t\theader = (struct nvram_header *)(end - nvram_sizes[i]);\n-\t\tif (header->magic == NVRAM_MAGIC)\n+\t\tif (bcm47xx_nvram_is_valid(end - nvram_sizes[i]))\n \t\t\treturn nvram_sizes[i];\n \t}\n \n@@ -55,6 +61,7 @@ static int bcm47xx_nvram_find_and_copy(v\n {\n \tstruct nvram_header __iomem *header;\n \tsize_t flash_size;\n+\tsize_t offset;\n \tu32 size;\n \n \tif (nvram_len) {\n@@ -68,31 +75,30 @@ static int bcm47xx_nvram_find_and_copy(v\n \t\t/* Windowed flash access */\n \t\tsize = find_nvram_size(flash_start + flash_size);\n \t\tif (size) {\n-\t\t\theader = (struct nvram_header *)(flash_start + flash_size - size);\n+\t\t\toffset = flash_size - size;\n \t\t\tgoto found;\n \t\t}\n \t\tflash_size <<= 1;\n \t}\n \n \t/* Try embedded NVRAM at 4 KB and 1 KB as last resorts */\n-\theader = (struct nvram_header *)(flash_start + 4096);\n-\tif (header->magic == NVRAM_MAGIC) {\n-\t\tsize = NVRAM_SPACE;\n+\n+\toffset = 4096;\n+\tif (bcm47xx_nvram_is_valid(flash_start + offset))\n \t\tgoto found;\n-\t}\n \n-\theader = (struct nvram_header *)(flash_start + 1024);\n-\tif (header->magic == NVRAM_MAGIC) {\n-\t\tsize = NVRAM_SPACE;\n+\toffset = 1024;\n+\tif (bcm47xx_nvram_is_valid(flash_start + offset))\n \t\tgoto found;\n-\t}\n \n \tpr_err(\"no nvram found\\n\");\n \treturn -ENXIO;\n \n found:\n+\theader = (struct nvram_header *)(flash_start + offset);\n \t__ioread32_copy(nvram_buf, header, sizeof(*header) / 4);\n \tnvram_len = ((struct nvram_header *)(nvram_buf))->len;\n+\tsize = res_size - offset;\n \tif (nvram_len > size) {\n \t\tpr_err(\"The nvram size according to the header seems to be bigger than the partition on flash\\n\");\n \t\tnvram_len = size;\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/800-v5.13-0003-firmware-bcm47xx_nvram-extract-code-copying-NVRAM.patch",
    "content": "From 298923cf999cecd2ef06df126f85a3d68da8c4d8 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Mon, 8 Mar 2021 10:03:18 +0100\nSubject: [PATCH] firmware: bcm47xx_nvram: extract code copying NVRAM\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nThis simplifies function finding NVRAM. It doesn't directly deal with\nNVRAM structure anymore and is a bit smaller.\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nSigned-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>\n---\n drivers/firmware/broadcom/bcm47xx_nvram.c | 43 +++++++++++++----------\n 1 file changed, 25 insertions(+), 18 deletions(-)\n\n--- a/drivers/firmware/broadcom/bcm47xx_nvram.c\n+++ b/drivers/firmware/broadcom/bcm47xx_nvram.c\n@@ -55,11 +55,34 @@ static u32 find_nvram_size(void __iomem\n }\n \n /**\n+ * bcm47xx_nvram_copy - copy NVRAM to internal buffer\n+ */\n+static void bcm47xx_nvram_copy(void __iomem *nvram_start, size_t res_size)\n+{\n+\tstruct nvram_header __iomem *header = nvram_start;\n+\tsize_t copy_size;\n+\n+\tcopy_size = header->len;\n+\tif (copy_size > res_size) {\n+\t\tpr_err(\"The nvram size according to the header seems to be bigger than the partition on flash\\n\");\n+\t\tcopy_size = res_size;\n+\t}\n+\tif (copy_size >= NVRAM_SPACE) {\n+\t\tpr_err(\"nvram on flash (%zu bytes) is bigger than the reserved space in memory, will just copy the first %i bytes\\n\",\n+\t\t       copy_size, NVRAM_SPACE - 1);\n+\t\tcopy_size = NVRAM_SPACE - 1;\n+\t}\n+\n+\t__ioread32_copy(nvram_buf, nvram_start, DIV_ROUND_UP(copy_size, 4));\n+\tnvram_buf[NVRAM_SPACE - 1] = '\\0';\n+\tnvram_len = copy_size;\n+}\n+\n+/**\n  * bcm47xx_nvram_find_and_copy - find NVRAM on flash mapping & copy it\n  */\n static int bcm47xx_nvram_find_and_copy(void __iomem *flash_start, size_t res_size)\n {\n-\tstruct nvram_header __iomem *header;\n \tsize_t flash_size;\n \tsize_t offset;\n \tu32 size;\n@@ -95,23 +118,7 @@ static int bcm47xx_nvram_find_and_copy(v\n \treturn -ENXIO;\n \n found:\n-\theader = (struct nvram_header *)(flash_start + offset);\n-\t__ioread32_copy(nvram_buf, header, sizeof(*header) / 4);\n-\tnvram_len = ((struct nvram_header *)(nvram_buf))->len;\n-\tsize = res_size - offset;\n-\tif (nvram_len > size) {\n-\t\tpr_err(\"The nvram size according to the header seems to be bigger than the partition on flash\\n\");\n-\t\tnvram_len = size;\n-\t}\n-\tif (nvram_len >= NVRAM_SPACE) {\n-\t\tpr_err(\"nvram on flash (%zu bytes) is bigger than the reserved space in memory, will just copy the first %i bytes\\n\",\n-\t\t       nvram_len, NVRAM_SPACE - 1);\n-\t\tnvram_len = NVRAM_SPACE - 1;\n-\t}\n-\t/* proceed reading data after header */\n-\t__ioread32_copy(nvram_buf + sizeof(*header), header + 1,\n-\t\t\tDIV_ROUND_UP(nvram_len, 4));\n-\tnvram_buf[NVRAM_SPACE - 1] = '\\0';\n+\tbcm47xx_nvram_copy(flash_start + offset, res_size - offset);\n \n \treturn 0;\n }\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/800-v5.13-0004-firmware-bcm47xx_nvram-look-for-NVRAM-with-for-inste.patch",
    "content": "From 98b68324f67236e8c9152976535dc1f27fb67ba8 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Mon, 8 Mar 2021 10:03:19 +0100\nSubject: [PATCH] firmware: bcm47xx_nvram: look for NVRAM with for instead of\n while\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nThis loop requires variable initialization, stop condition and post\niteration increment. It's pretty much a for loop definition.\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nSigned-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>\n---\n drivers/firmware/broadcom/bcm47xx_nvram.c | 4 +---\n 1 file changed, 1 insertion(+), 3 deletions(-)\n\n--- a/drivers/firmware/broadcom/bcm47xx_nvram.c\n+++ b/drivers/firmware/broadcom/bcm47xx_nvram.c\n@@ -93,15 +93,13 @@ static int bcm47xx_nvram_find_and_copy(v\n \t}\n \n \t/* TODO: when nvram is on nand flash check for bad blocks first. */\n-\tflash_size = FLASH_MIN;\n-\twhile (flash_size <= res_size) {\n+\tfor (flash_size = FLASH_MIN; flash_size <= res_size; flash_size <<= 1) {\n \t\t/* Windowed flash access */\n \t\tsize = find_nvram_size(flash_start + flash_size);\n \t\tif (size) {\n \t\t\toffset = flash_size - size;\n \t\t\tgoto found;\n \t\t}\n-\t\tflash_size <<= 1;\n \t}\n \n \t/* Try embedded NVRAM at 4 KB and 1 KB as last resorts */\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/800-v5.13-0005-firmware-bcm47xx_nvram-inline-code-checking-NVRAM-si.patch",
    "content": "From f52da4ccfec9192e17f5c16260dfdd6d3ea76f65 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Mon, 8 Mar 2021 10:03:20 +0100\nSubject: [PATCH] firmware: bcm47xx_nvram: inline code checking NVRAM size\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nSeparated function was not improving code quality much (or at all).\nMoreover it expected possible flash end address as argument and it was\nreturning NVRAM size.\n\nThe new code always operates on offsets which means less logic and less\ncalculations.\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nSigned-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>\n---\n drivers/firmware/broadcom/bcm47xx_nvram.c | 25 +++++++----------------\n 1 file changed, 7 insertions(+), 18 deletions(-)\n\n--- a/drivers/firmware/broadcom/bcm47xx_nvram.c\n+++ b/drivers/firmware/broadcom/bcm47xx_nvram.c\n@@ -42,18 +42,6 @@ static bool bcm47xx_nvram_is_valid(void\n \treturn ((struct nvram_header *)nvram)->magic == NVRAM_MAGIC;\n }\n \n-static u32 find_nvram_size(void __iomem *end)\n-{\n-\tint i;\n-\n-\tfor (i = 0; i < ARRAY_SIZE(nvram_sizes); i++) {\n-\t\tif (bcm47xx_nvram_is_valid(end - nvram_sizes[i]))\n-\t\t\treturn nvram_sizes[i];\n-\t}\n-\n-\treturn 0;\n-}\n-\n /**\n  * bcm47xx_nvram_copy - copy NVRAM to internal buffer\n  */\n@@ -85,7 +73,7 @@ static int bcm47xx_nvram_find_and_copy(v\n {\n \tsize_t flash_size;\n \tsize_t offset;\n-\tu32 size;\n+\tint i;\n \n \tif (nvram_len) {\n \t\tpr_warn(\"nvram already initialized\\n\");\n@@ -93,12 +81,13 @@ static int bcm47xx_nvram_find_and_copy(v\n \t}\n \n \t/* TODO: when nvram is on nand flash check for bad blocks first. */\n+\n+\t/* Try every possible flash size and check for NVRAM at its end */\n \tfor (flash_size = FLASH_MIN; flash_size <= res_size; flash_size <<= 1) {\n-\t\t/* Windowed flash access */\n-\t\tsize = find_nvram_size(flash_start + flash_size);\n-\t\tif (size) {\n-\t\t\toffset = flash_size - size;\n-\t\t\tgoto found;\n+\t\tfor (i = 0; i < ARRAY_SIZE(nvram_sizes); i++) {\n+\t\t\toffset = flash_size - nvram_sizes[i];\n+\t\t\tif (bcm47xx_nvram_is_valid(flash_start + offset))\n+\t\t\t\tgoto found;\n \t\t}\n \t}\n \n"
  },
  {
    "path": "target/linux/generic/backport-5.10/810-v5.13-usb-ehci-add-spurious-flag-to-disable-overcurrent-ch.patch",
    "content": "From 2d5ba37461013253d2ff0a3641b727fd32ea97a9 Mon Sep 17 00:00:00 2001\nFrom: Florian Fainelli <florian@openwrt.org>\nDate: Tue, 23 Feb 2021 18:44:53 +0100\nSubject: [PATCH 1/3] usb: ehci: add spurious flag to disable overcurrent\n checking\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nThis patch adds an ignore_oc flag which can be set by EHCI controller\nnot supporting or wanting to disable overcurrent checking. The EHCI\nplatform data in include/linux/usb/ehci_pdriver.h is also augmented to\ntake advantage of this new flag.\n\nSigned-off-by: Florian Fainelli <florian@openwrt.org>\nSigned-off-by: Álvaro Fernández Rojas <noltari@gmail.com>\nLink: https://lore.kernel.org/r/20210223174455.1378-2-noltari@gmail.com\nSigned-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>\n---\n drivers/usb/host/ehci-hcd.c      | 2 +-\n drivers/usb/host/ehci-hub.c      | 4 ++--\n drivers/usb/host/ehci-platform.c | 2 ++\n drivers/usb/host/ehci.h          | 1 +\n include/linux/usb/ehci_pdriver.h | 1 +\n 5 files changed, 7 insertions(+), 3 deletions(-)\n\n--- a/drivers/usb/host/ehci-hcd.c\n+++ b/drivers/usb/host/ehci-hcd.c\n@@ -660,7 +660,7 @@ static int ehci_run (struct usb_hcd *hcd\n \t\t\"USB %x.%x started, EHCI %x.%02x%s\\n\",\n \t\t((ehci->sbrn & 0xf0)>>4), (ehci->sbrn & 0x0f),\n \t\ttemp >> 8, temp & 0xff,\n-\t\tignore_oc ? \", overcurrent ignored\" : \"\");\n+\t\t(ignore_oc || ehci->spurious_oc) ? \", overcurrent ignored\" : \"\");\n \n \tehci_writel(ehci, INTR_MASK,\n \t\t    &ehci->regs->intr_enable); /* Turn On Interrupts */\n--- a/drivers/usb/host/ehci-hub.c\n+++ b/drivers/usb/host/ehci-hub.c\n@@ -643,7 +643,7 @@ ehci_hub_status_data (struct usb_hcd *hc\n \t * always set, seem to clear PORT_OCC and PORT_CSC when writing to\n \t * PORT_POWER; that's surprising, but maybe within-spec.\n \t */\n-\tif (!ignore_oc)\n+\tif (!ignore_oc && !ehci->spurious_oc)\n \t\tmask = PORT_CSC | PORT_PEC | PORT_OCC;\n \telse\n \t\tmask = PORT_CSC | PORT_PEC;\n@@ -1013,7 +1013,7 @@ int ehci_hub_control(\n \t\tif (temp & PORT_PEC)\n \t\t\tstatus |= USB_PORT_STAT_C_ENABLE << 16;\n \n-\t\tif ((temp & PORT_OCC) && !ignore_oc){\n+\t\tif ((temp & PORT_OCC) && (!ignore_oc && !ehci->spurious_oc)){\n \t\t\tstatus |= USB_PORT_STAT_C_OVERCURRENT << 16;\n \n \t\t\t/*\n--- a/drivers/usb/host/ehci-platform.c\n+++ b/drivers/usb/host/ehci-platform.c\n@@ -333,6 +333,8 @@ static int ehci_platform_probe(struct pl\n \t\thcd->has_tt = 1;\n \tif (pdata->reset_on_resume)\n \t\tpriv->reset_on_resume = true;\n+\tif (pdata->spurious_oc)\n+\t\tehci->spurious_oc = 1;\n \n #ifndef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO\n \tif (ehci->big_endian_mmio) {\n--- a/drivers/usb/host/ehci.h\n+++ b/drivers/usb/host/ehci.h\n@@ -219,6 +219,7 @@ struct ehci_hcd {\t\t\t/* one per controlle\n \tunsigned\t\tneed_oc_pp_cycle:1; /* MPC834X port power */\n \tunsigned\t\timx28_write_fix:1; /* For Freescale i.MX28 */\n \tunsigned\t\tis_aspeed:1;\n+\tunsigned\t\tspurious_oc:1;\n \n \t/* required for usb32 quirk */\n \t#define OHCI_CTRL_HCFS          (3 << 6)\n--- a/include/linux/usb/ehci_pdriver.h\n+++ b/include/linux/usb/ehci_pdriver.h\n@@ -50,6 +50,7 @@ struct usb_ehci_pdata {\n \tunsigned\tno_io_watchdog:1;\n \tunsigned\treset_on_resume:1;\n \tunsigned\tdma_mask_64:1;\n+\tunsigned\tspurious_oc:1;\n \n \t/* Turn on all power and clocks */\n \tint (*power_on)(struct platform_device *pdev);\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/811-v5.13-usb-host-ehci-platform-add-spurious_oc-DT-support.patch",
    "content": "From 4da57dbbffdfa7fe4e2b70b047fc5ff95ff25a3d Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com>\nDate: Tue, 23 Feb 2021 18:44:55 +0100\nSubject: [PATCH 3/3] usb: host: ehci-platform: add spurious_oc DT support\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nOver-current reporting isn't supported on some platforms such as bcm63xx.\nThese devices will incorrectly report over-current if this flag isn't properly\nactivated.\n\nSigned-off-by: Álvaro Fernández Rojas <noltari@gmail.com>\nLink: https://lore.kernel.org/r/20210223174455.1378-4-noltari@gmail.com\nSigned-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>\n---\n drivers/usb/host/ehci-platform.c | 3 +++\n 1 file changed, 3 insertions(+)\n\n--- a/drivers/usb/host/ehci-platform.c\n+++ b/drivers/usb/host/ehci-platform.c\n@@ -286,6 +286,9 @@ static int ehci_platform_probe(struct pl\n \t\tif (of_property_read_bool(dev->dev.of_node, \"big-endian\"))\n \t\t\tehci->big_endian_mmio = ehci->big_endian_desc = 1;\n \n+\t\tif (of_property_read_bool(dev->dev.of_node, \"spurious-oc\"))\n+\t\t\tehci->spurious_oc = 1;\n+\n \t\tif (of_property_read_bool(dev->dev.of_node,\n \t\t\t\t\t  \"needs-reset-on-resume\"))\n \t\t\tpriv->reset_on_resume = true;\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/820-v5.13-make-pci_host_common_probe-declare-its-reliance-on-msi-domains.patch",
    "content": "From 9ec37efb87832b578d7972fc80b04d94f5d2bbe3 Mon Sep 17 00:00:00 2001\nFrom: Marc Zyngier <maz@kernel.org>\nDate: Tue, 30 Mar 2021 16:11:42 +0100\nSubject: PCI/MSI: Make pci_host_common_probe() declare its reliance on MSI\n domains\n\nThe generic PCI host driver relies on MSI domains for MSIs to\nbe provided to its end-points. Make this dependency explicit.\n\nThis cures the warnings occuring on arm/arm64 VMs when booted\nwith PCI virtio devices and no MSI controller (no GICv3 ITS,\nfor example).\n\nIt is likely that other drivers will need to express the same\ndependency.\n\nLink: https://lore.kernel.org/r/20210330151145.997953-12-maz@kernel.org\nSigned-off-by: Marc Zyngier <maz@kernel.org>\nSigned-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>\nAcked-by: Bjorn Helgaas <bhelgaas@google.com>\n---\n drivers/pci/controller/pci-host-common.c | 1 +\n 1 file changed, 1 insertion(+)\n\n--- a/drivers/pci/controller/pci-host-common.c\n+++ b/drivers/pci/controller/pci-host-common.c\n@@ -77,6 +77,7 @@ int pci_host_common_probe(struct platfor\n \n \tbridge->sysdata = cfg;\n \tbridge->ops = (struct pci_ops *)&ops->pci_ops;\n+\tbridge->msi_domain = true;\n \n \tplatform_set_drvdata(pdev, bridge);\n \n"
  },
  {
    "path": "target/linux/generic/backport-5.10/821-v5.13-let-pci-host-bridges-declar-their-reliance-on-msi-domains.patch",
    "content": "From 94e89b145371b68fa0ea294855adebcd03e0522e Mon Sep 17 00:00:00 2001\nFrom: Marc Zyngier <maz@kernel.org>\nDate: Tue, 30 Mar 2021 16:11:41 +0100\nSubject: PCI/MSI: Let PCI host bridges declare their reliance on MSI domains\n\nThere is a whole class of host bridges that cannot know whether\nMSIs will be provided or not, as they rely on other blocks\nto provide the MSI functionnality, using MSI domains.  This is\nthe case for example on systems that use the ARM GIC architecture.\n\nIntroduce a new attribute ('msi_domain') indicating that implicit\ndependency, and use this property to set the NO_MSI flag when\nno MSI domain is found at probe time.\n\nLink: https://lore.kernel.org/r/20210330151145.997953-11-maz@kernel.org\nSigned-off-by: Marc Zyngier <maz@kernel.org>\nSigned-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>\nAcked-by: Bjorn Helgaas <bhelgaas@google.com>\n---\n drivers/pci/probe.c | 2 ++\n include/linux/pci.h | 1 +\n 2 files changed, 3 insertions(+)\n\n--- a/drivers/pci/probe.c\n+++ b/drivers/pci/probe.c\n@@ -925,6 +925,8 @@ static int pci_register_host_bridge(stru\n \tdevice_enable_async_suspend(bus->bridge);\n \tpci_set_bus_of_node(bus);\n \tpci_set_bus_msi_domain(bus);\n+\tif (bridge->msi_domain && !dev_get_msi_domain(&bus->dev))\n+\t\tbus->bus_flags |= PCI_BUS_FLAGS_NO_MSI;\n \n \tif (!parent)\n \t\tset_dev_node(bus->bridge, pcibus_to_node(bus));\n--- a/include/linux/pci.h\n+++ b/include/linux/pci.h\n@@ -547,6 +547,7 @@ struct pci_host_bridge {\n \tunsigned int\tnative_dpc:1;\t\t/* OS may use PCIe DPC */\n \tunsigned int\tpreserve_config:1;\t/* Preserve FW resource setup */\n \tunsigned int\tsize_windows:1;\t\t/* Enable root bus sizing */\n+\tunsigned int\tmsi_domain:1;\t\t/* Bridge wants MSI domain */\n \n \t/* Resource alignment requirements */\n \tresource_size_t (*align_resource)(struct pci_dev *dev,\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/822-v5.13-advertise-lack-of-built-in-msi-handling.patch",
    "content": "From 645e9c38383d7fcde2784ee537fa18ec9bed54d9 Mon Sep 17 00:00:00 2001\nFrom: Thomas Gleixner <tglx@linutronix.de>\nDate: Tue, 30 Mar 2021 16:11:43 +0100\nSubject: PCI: mediatek: Advertise lack of built-in MSI handling\n\nSome Mediatek host bridges cannot handle MSIs, which is sad.\nThis also results in an ugly warning at device probe time,\nas the core PCI code wasn't told that MSIs were not available.\n\nAdvertise this fact to the rest of the core PCI code by\nusing the 'msi_domain' attribute, which still opens the possibility\nfor another block to provide the MSI functionnality.\n\n[maz: commit message, switched over to msi_domain attribute]\n\nLink: https://lore.kernel.org/r/20210330151145.997953-13-maz@kernel.org\nReported-by: Frank Wunderlich <frank-w@public-files.de>\nSigned-off-by: Thomas Gleixner <tglx@linutronix.de>\nSigned-off-by: Marc Zyngier <maz@kernel.org>\nSigned-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>\nAcked-by: Bjorn Helgaas <bhelgaas@google.com>\n---\n drivers/pci/controller/pcie-mediatek.c | 4 ++++\n 1 file changed, 4 insertions(+)\n\n--- a/drivers/pci/controller/pcie-mediatek.c\n+++ b/drivers/pci/controller/pcie-mediatek.c\n@@ -143,6 +143,7 @@ struct mtk_pcie_port;\n  * struct mtk_pcie_soc - differentiate between host generations\n  * @need_fix_class_id: whether this host's class ID needed to be fixed or not\n  * @need_fix_device_id: whether this host's device ID needed to be fixed or not\n+ * @no_msi: Bridge has no MSI support, and relies on an external block\n  * @device_id: device ID which this host need to be fixed\n  * @ops: pointer to configuration access functions\n  * @startup: pointer to controller setting functions\n@@ -151,6 +152,7 @@ struct mtk_pcie_port;\n struct mtk_pcie_soc {\n \tbool need_fix_class_id;\n \tbool need_fix_device_id;\n+\tbool no_msi;\n \tunsigned int device_id;\n \tstruct pci_ops *ops;\n \tint (*startup)(struct mtk_pcie_port *port);\n@@ -1087,6 +1089,7 @@ static int mtk_pcie_probe(struct platfor\n \n \thost->ops = pcie->soc->ops;\n \thost->sysdata = pcie;\n+\thost->msi_domain = pcie->soc->no_msi;\n \n \terr = pci_host_probe(host);\n \tif (err)\n@@ -1176,6 +1179,7 @@ static const struct dev_pm_ops mtk_pcie_\n };\n \n static const struct mtk_pcie_soc mtk_pcie_soc_v1 = {\n+\t.no_msi = true,\n \t.ops = &mtk_pcie_ops,\n \t.startup = mtk_pcie_startup_port,\n };\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/830-v5.14-leds-lp55xx-Initialize-enable-GPIO-direction-to-outp.patch",
    "content": "From a5d3d1adc95f4ac5968b7a77ee95a3abbbb96f49 Mon Sep 17 00:00:00 2001\nFrom: Doug Zobel <dougdev334@gmail.com>\nDate: Mon, 10 May 2021 15:40:00 -0500\nSubject: [PATCH] leds: lp55xx: Initialize enable GPIO direction to output\n\nThe \"Convert to use GPIO descriptors\" commit changed the\ninitialization of the enable GPIO from GPIOF_DIR_OUT to\nGPIOD_ASIS.  This breaks systems where the GPIO does not\ndefault to output.  Changing the enable initialization\nto GPIOD_OUT_LOW.\n\nSigned-off-by: Doug Zobel <dougdev334@gmail.com>\nSigned-off-by: Pavel Machek <pavel@ucw.cz>\n---\n drivers/leds/leds-lp55xx-common.c | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/drivers/leds/leds-lp55xx-common.c\n+++ b/drivers/leds/leds-lp55xx-common.c\n@@ -694,7 +694,7 @@ struct lp55xx_platform_data *lp55xx_of_p\n \tof_property_read_u8(np, \"clock-mode\", &pdata->clock_mode);\n \n \tpdata->enable_gpiod = devm_gpiod_get_optional(dev, \"enable\",\n-\t\t\t\t\t\t      GPIOD_ASIS);\n+\t\t\t\t\t\t      GPIOD_OUT_LOW);\n \tif (IS_ERR(pdata->enable_gpiod))\n \t\treturn ERR_CAST(pdata->enable_gpiod);\n \n"
  },
  {
    "path": "target/linux/generic/backport-5.10/850-v5.17-0001-PCI-pci-bridge-emul-Add-description-for-class_revisi.patch",
    "content": "From 9319230ac147067652b58fe849ffe0ceec098665 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>\nDate: Tue, 30 Nov 2021 18:29:03 +0100\nSubject: [PATCH] PCI: pci-bridge-emul: Add description for class_revision\n field\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nThe current assignment to the class_revision member\n\n  class_revision |= cpu_to_le32(PCI_CLASS_BRIDGE_PCI << 16);\n\ncan make the reader think that class is at high 16 bits of the member and\nrevision at low 16 bits.\n\nIn reality, class is at high 24 bits, but the class for PCI Bridge Normal\nDecode is PCI_CLASS_BRIDGE_PCI << 8.\n\nChange the assignment and add a comment to make this clearer.\n\nLink: https://lore.kernel.org/r/20211130172913.9727-2-kabel@kernel.org\nSigned-off-by: Pali Rohár <pali@kernel.org>\nSigned-off-by: Marek Behún <kabel@kernel.org>\nSigned-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>\n---\n drivers/pci/pci-bridge-emul.c | 6 +++++-\n 1 file changed, 5 insertions(+), 1 deletion(-)\n\n--- a/drivers/pci/pci-bridge-emul.c\n+++ b/drivers/pci/pci-bridge-emul.c\n@@ -284,7 +284,11 @@ int pci_bridge_emul_init(struct pci_brid\n {\n \tBUILD_BUG_ON(sizeof(bridge->conf) != PCI_BRIDGE_CONF_END);\n \n-\tbridge->conf.class_revision |= cpu_to_le32(PCI_CLASS_BRIDGE_PCI << 16);\n+\t/*\n+\t * class_revision: Class is high 24 bits and revision is low 8 bit of this member,\n+\t * while class for PCI Bridge Normal Decode has the 24-bit value: PCI_CLASS_BRIDGE_PCI << 8\n+\t */\n+\tbridge->conf.class_revision |= cpu_to_le32((PCI_CLASS_BRIDGE_PCI << 8) << 8);\n \tbridge->conf.header_type = PCI_HEADER_TYPE_BRIDGE;\n \tbridge->conf.cache_line_size = 0x10;\n \tbridge->conf.status = cpu_to_le16(PCI_STATUS_CAP_LIST);\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/850-v5.17-0002-PCI-pci-bridge-emul-Add-definitions-for-missing-capa.patch",
    "content": "From 8ea673a8b30b4a32516b8adabb15e2a68ff02ec8 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>\nDate: Tue, 30 Nov 2021 18:29:04 +0100\nSubject: [PATCH] PCI: pci-bridge-emul: Add definitions for missing\n capabilities registers\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\npci-bridge-emul driver already allocates buffer for capabilities up to the\nPCI_EXP_SLTSTA2 register, but does not define bit access behavior for these\nregisters. Add these missing definitions.\n\nLink: https://lore.kernel.org/r/20211130172913.9727-3-kabel@kernel.org\nSigned-off-by: Pali Rohár <pali@kernel.org>\nSigned-off-by: Marek Behún <kabel@kernel.org>\nSigned-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>\n---\n drivers/pci/pci-bridge-emul.c | 43 +++++++++++++++++++++++++++++++++++\n 1 file changed, 43 insertions(+)\n\n--- a/drivers/pci/pci-bridge-emul.c\n+++ b/drivers/pci/pci-bridge-emul.c\n@@ -270,6 +270,49 @@ struct pci_bridge_reg_behavior pcie_cap_\n \t\t.ro = GENMASK(15, 0) | PCI_EXP_RTSTA_PENDING,\n \t\t.w1c = PCI_EXP_RTSTA_PME,\n \t},\n+\n+\t[PCI_EXP_DEVCAP2 / 4] = {\n+\t\t/*\n+\t\t * Device capabilities 2 register has reserved bits [30:27].\n+\t\t * Also bits [26:24] are reserved for non-upstream ports.\n+\t\t */\n+\t\t.ro = BIT(31) | GENMASK(23, 0),\n+\t},\n+\n+\t[PCI_EXP_DEVCTL2 / 4] = {\n+\t\t/*\n+\t\t * Device control 2 register is RW. Bit 11 is reserved for\n+\t\t * non-upstream ports.\n+\t\t *\n+\t\t * Device status 2 register is reserved.\n+\t\t */\n+\t\t.rw = GENMASK(15, 12) | GENMASK(10, 0),\n+\t},\n+\n+\t[PCI_EXP_LNKCAP2 / 4] = {\n+\t\t/* Link capabilities 2 register has reserved bits [30:25] and 0. */\n+\t\t.ro = BIT(31) | GENMASK(24, 1),\n+\t},\n+\n+\t[PCI_EXP_LNKCTL2 / 4] = {\n+\t\t/*\n+\t\t * Link control 2 register is RW.\n+\t\t *\n+\t\t * Link status 2 register has bits 5, 15 W1C;\n+\t\t * bits 10, 11 reserved and others are RO.\n+\t\t */\n+\t\t.rw = GENMASK(15, 0),\n+\t\t.w1c = (BIT(15) | BIT(5)) << 16,\n+\t\t.ro = (GENMASK(14, 12) | GENMASK(9, 6) | GENMASK(4, 0)) << 16,\n+\t},\n+\n+\t[PCI_EXP_SLTCAP2 / 4] = {\n+\t\t/* Slot capabilities 2 register is reserved. */\n+\t},\n+\n+\t[PCI_EXP_SLTCTL2 / 4] = {\n+\t\t/* Both Slot control 2 and Slot status 2 registers are reserved. */\n+\t},\n };\n \n /*\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/850-v5.17-0003-PCI-aardvark-Add-support-for-DEVCAP2-DEVCTL2-LNKCAP2.patch",
    "content": "From 1d3e170344dff2cef8827db6c09909b78cbc11d7 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>\nDate: Tue, 30 Nov 2021 18:29:05 +0100\nSubject: [PATCH] PCI: aardvark: Add support for DEVCAP2, DEVCTL2, LNKCAP2 and\n LNKCTL2 registers on emulated bridge\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nPCI aardvark hardware supports access to DEVCAP2, DEVCTL2, LNKCAP2 and\nLNKCTL2 configuration registers of PCIe core via PCIE_CORE_PCIEXP_CAP.\nExport them via emulated software root bridge.\n\nLink: https://lore.kernel.org/r/20211130172913.9727-4-kabel@kernel.org\nSigned-off-by: Pali Rohár <pali@kernel.org>\nSigned-off-by: Marek Behún <kabel@kernel.org>\nSigned-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>\n---\n drivers/pci/controller/pci-aardvark.c | 15 +++++++++++----\n 1 file changed, 11 insertions(+), 4 deletions(-)\n\n--- a/drivers/pci/controller/pci-aardvark.c\n+++ b/drivers/pci/controller/pci-aardvark.c\n@@ -883,8 +883,13 @@ advk_pci_bridge_emul_pcie_conf_read(stru\n \n \tcase PCI_EXP_DEVCAP:\n \tcase PCI_EXP_DEVCTL:\n+\tcase PCI_EXP_DEVCAP2:\n+\tcase PCI_EXP_DEVCTL2:\n+\tcase PCI_EXP_LNKCAP2:\n+\tcase PCI_EXP_LNKCTL2:\n \t\t*value = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + reg);\n \t\treturn PCI_BRIDGE_EMUL_HANDLED;\n+\n \tdefault:\n \t\treturn PCI_BRIDGE_EMUL_NOT_HANDLED;\n \t}\n@@ -898,10 +903,6 @@ advk_pci_bridge_emul_pcie_conf_write(str\n \tstruct advk_pcie *pcie = bridge->data;\n \n \tswitch (reg) {\n-\tcase PCI_EXP_DEVCTL:\n-\t\tadvk_writel(pcie, new, PCIE_CORE_PCIEXP_CAP + reg);\n-\t\tbreak;\n-\n \tcase PCI_EXP_LNKCTL:\n \t\tadvk_writel(pcie, new, PCIE_CORE_PCIEXP_CAP + reg);\n \t\tif (new & PCI_EXP_LNKCTL_RL)\n@@ -923,6 +924,12 @@ advk_pci_bridge_emul_pcie_conf_write(str\n \t\tadvk_writel(pcie, new, PCIE_ISR0_REG);\n \t\tbreak;\n \n+\tcase PCI_EXP_DEVCTL:\n+\tcase PCI_EXP_DEVCTL2:\n+\tcase PCI_EXP_LNKCTL2:\n+\t\tadvk_writel(pcie, new, PCIE_CORE_PCIEXP_CAP + reg);\n+\t\tbreak;\n+\n \tdefault:\n \t\tbreak;\n \t}\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/850-v5.17-0004-PCI-aardvark-Clear-all-MSIs-at-setup.patch",
    "content": "From 7d8dc1f7cd007a7ce94c5b4c20d63a8b8d6d7751 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>\nDate: Tue, 30 Nov 2021 18:29:06 +0100\nSubject: [PATCH] PCI: aardvark: Clear all MSIs at setup\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nWe already clear all the other interrupts (ISR0, ISR1, HOST_CTRL_INT).\n\nDefine a new macro PCIE_MSI_ALL_MASK and do the same clearing for MSIs,\nto ensure that we don't start receiving spurious interrupts.\n\nUse this new mask in advk_pcie_handle_msi();\n\nLink: https://lore.kernel.org/r/20211130172913.9727-5-kabel@kernel.org\nSigned-off-by: Pali Rohár <pali@kernel.org>\nSigned-off-by: Marek Behún <kabel@kernel.org>\nSigned-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>\n---\n drivers/pci/controller/pci-aardvark.c | 6 ++++--\n 1 file changed, 4 insertions(+), 2 deletions(-)\n\n--- a/drivers/pci/controller/pci-aardvark.c\n+++ b/drivers/pci/controller/pci-aardvark.c\n@@ -114,6 +114,7 @@\n #define PCIE_MSI_ADDR_HIGH_REG\t\t\t(CONTROL_BASE_ADDR + 0x54)\n #define PCIE_MSI_STATUS_REG\t\t\t(CONTROL_BASE_ADDR + 0x58)\n #define PCIE_MSI_MASK_REG\t\t\t(CONTROL_BASE_ADDR + 0x5C)\n+#define     PCIE_MSI_ALL_MASK\t\t\tGENMASK(31, 0)\n #define PCIE_MSI_PAYLOAD_REG\t\t\t(CONTROL_BASE_ADDR + 0x9C)\n #define     PCIE_MSI_DATA_MASK\t\t\tGENMASK(15, 0)\n \n@@ -577,6 +578,7 @@ static void advk_pcie_setup_hw(struct ad\n \tadvk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);\n \n \t/* Clear all interrupts */\n+\tadvk_writel(pcie, PCIE_MSI_ALL_MASK, PCIE_MSI_STATUS_REG);\n \tadvk_writel(pcie, PCIE_ISR0_ALL_MASK, PCIE_ISR0_REG);\n \tadvk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_REG);\n \tadvk_writel(pcie, PCIE_IRQ_ALL_MASK, HOST_CTRL_INT_STATUS_REG);\n@@ -589,7 +591,7 @@ static void advk_pcie_setup_hw(struct ad\n \tadvk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_MASK_REG);\n \n \t/* Unmask all MSIs */\n-\tadvk_writel(pcie, 0, PCIE_MSI_MASK_REG);\n+\tadvk_writel(pcie, ~(u32)PCIE_MSI_ALL_MASK, PCIE_MSI_MASK_REG);\n \n \t/* Enable summary interrupt for GIC SPI source */\n \treg = PCIE_IRQ_ALL_MASK & (~PCIE_IRQ_ENABLE_INTS_MASK);\n@@ -1397,7 +1399,7 @@ static void advk_pcie_handle_msi(struct\n \n \tmsi_mask = advk_readl(pcie, PCIE_MSI_MASK_REG);\n \tmsi_val = advk_readl(pcie, PCIE_MSI_STATUS_REG);\n-\tmsi_status = msi_val & ~msi_mask;\n+\tmsi_status = msi_val & ((~msi_mask) & PCIE_MSI_ALL_MASK);\n \n \tfor (msi_idx = 0; msi_idx < MSI_IRQ_NUM; msi_idx++) {\n \t\tif (!(BIT(msi_idx) & msi_status))\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/850-v5.17-0005-PCI-aardvark-Comment-actions-in-driver-remove-method.patch",
    "content": "From a4ca7948e1d47275f8f3e5023243440c40561916 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>\nDate: Tue, 30 Nov 2021 18:29:07 +0100\nSubject: [PATCH] PCI: aardvark: Comment actions in driver remove method\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nAdd two more comments into the advk_pcie_remove() method.\n\nLink: https://lore.kernel.org/r/20211130172913.9727-6-kabel@kernel.org\nSigned-off-by: Pali Rohár <pali@kernel.org>\nSigned-off-by: Marek Behún <kabel@kernel.org>\nSigned-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>\n---\n drivers/pci/controller/pci-aardvark.c | 2 ++\n 1 file changed, 2 insertions(+)\n\n--- a/drivers/pci/controller/pci-aardvark.c\n+++ b/drivers/pci/controller/pci-aardvark.c\n@@ -1696,11 +1696,13 @@ static int advk_pcie_remove(struct platf\n \tstruct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie);\n \tint i;\n \n+\t/* Remove PCI bus with all devices */\n \tpci_lock_rescan_remove();\n \tpci_stop_root_bus(bridge->bus);\n \tpci_remove_root_bus(bridge->bus);\n \tpci_unlock_rescan_remove();\n \n+\t/* Remove IRQ domains */\n \tadvk_pcie_remove_msi_irq_domain(pcie);\n \tadvk_pcie_remove_irq_domain(pcie);\n \n"
  },
  {
    "path": "target/linux/generic/backport-5.10/850-v5.17-0006-PCI-aardvark-Disable-bus-mastering-when-unbinding-dr.patch",
    "content": "From a46f2f6dd4093438d9615dfbf5c0fea2a9835dba Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>\nDate: Tue, 30 Nov 2021 18:29:08 +0100\nSubject: [PATCH] PCI: aardvark: Disable bus mastering when unbinding driver\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nEnsure that after driver unbind PCIe cards are not able to forward\nmemory and I/O requests in the upstream direction.\n\nLink: https://lore.kernel.org/r/20211130172913.9727-7-kabel@kernel.org\nSigned-off-by: Pali Rohár <pali@kernel.org>\nSigned-off-by: Marek Behún <kabel@kernel.org>\nSigned-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>\n---\n drivers/pci/controller/pci-aardvark.c | 6 ++++++\n 1 file changed, 6 insertions(+)\n\n--- a/drivers/pci/controller/pci-aardvark.c\n+++ b/drivers/pci/controller/pci-aardvark.c\n@@ -1694,6 +1694,7 @@ static int advk_pcie_remove(struct platf\n {\n \tstruct advk_pcie *pcie = platform_get_drvdata(pdev);\n \tstruct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie);\n+\tu32 val;\n \tint i;\n \n \t/* Remove PCI bus with all devices */\n@@ -1702,6 +1703,11 @@ static int advk_pcie_remove(struct platf\n \tpci_remove_root_bus(bridge->bus);\n \tpci_unlock_rescan_remove();\n \n+\t/* Disable Root Bridge I/O space, memory space and bus mastering */\n+\tval = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG);\n+\tval &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);\n+\tadvk_writel(pcie, val, PCIE_CORE_CMD_STATUS_REG);\n+\n \t/* Remove IRQ domains */\n \tadvk_pcie_remove_msi_irq_domain(pcie);\n \tadvk_pcie_remove_irq_domain(pcie);\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/850-v5.17-0007-PCI-aardvark-Mask-all-interrupts-when-unbinding-driv.patch",
    "content": "From 13bcdf07cb2ecff5d45d2c141df2539b15211448 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>\nDate: Tue, 30 Nov 2021 18:29:09 +0100\nSubject: [PATCH] PCI: aardvark: Mask all interrupts when unbinding driver\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nEnsure that no interrupt can be triggered after driver unbind.\n\nLink: https://lore.kernel.org/r/20211130172913.9727-8-kabel@kernel.org\nSigned-off-by: Pali Rohár <pali@kernel.org>\nSigned-off-by: Marek Behún <kabel@kernel.org>\nSigned-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>\n---\n drivers/pci/controller/pci-aardvark.c | 21 +++++++++++++++++++++\n 1 file changed, 21 insertions(+)\n\n--- a/drivers/pci/controller/pci-aardvark.c\n+++ b/drivers/pci/controller/pci-aardvark.c\n@@ -1708,6 +1708,27 @@ static int advk_pcie_remove(struct platf\n \tval &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);\n \tadvk_writel(pcie, val, PCIE_CORE_CMD_STATUS_REG);\n \n+\t/* Disable MSI */\n+\tval = advk_readl(pcie, PCIE_CORE_CTRL2_REG);\n+\tval &= ~PCIE_CORE_CTRL2_MSI_ENABLE;\n+\tadvk_writel(pcie, val, PCIE_CORE_CTRL2_REG);\n+\n+\t/* Clear MSI address */\n+\tadvk_writel(pcie, 0, PCIE_MSI_ADDR_LOW_REG);\n+\tadvk_writel(pcie, 0, PCIE_MSI_ADDR_HIGH_REG);\n+\n+\t/* Mask all interrupts */\n+\tadvk_writel(pcie, PCIE_MSI_ALL_MASK, PCIE_MSI_MASK_REG);\n+\tadvk_writel(pcie, PCIE_ISR0_ALL_MASK, PCIE_ISR0_MASK_REG);\n+\tadvk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_MASK_REG);\n+\tadvk_writel(pcie, PCIE_IRQ_ALL_MASK, HOST_CTRL_INT_MASK_REG);\n+\n+\t/* Clear all interrupts */\n+\tadvk_writel(pcie, PCIE_MSI_ALL_MASK, PCIE_MSI_STATUS_REG);\n+\tadvk_writel(pcie, PCIE_ISR0_ALL_MASK, PCIE_ISR0_REG);\n+\tadvk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_REG);\n+\tadvk_writel(pcie, PCIE_IRQ_ALL_MASK, HOST_CTRL_INT_STATUS_REG);\n+\n \t/* Remove IRQ domains */\n \tadvk_pcie_remove_msi_irq_domain(pcie);\n \tadvk_pcie_remove_irq_domain(pcie);\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/850-v5.17-0008-PCI-aardvark-Fix-memory-leak-in-driver-unbind.patch",
    "content": "From 2f040a17f5061457ae95035326d3159eddc1e5cc Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>\nDate: Tue, 30 Nov 2021 18:29:10 +0100\nSubject: [PATCH] PCI: aardvark: Fix memory leak in driver unbind\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nFree config space for emulated root bridge when unbinding driver to fix\nmemory leak. Do it after disabling and masking all interrupts, since\naardvark interrupt handler accesses config space of emulated root\nbridge.\n\nLink: https://lore.kernel.org/r/20211130172913.9727-9-kabel@kernel.org\nSigned-off-by: Pali Rohár <pali@kernel.org>\nSigned-off-by: Marek Behún <kabel@kernel.org>\nSigned-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>\n---\n drivers/pci/controller/pci-aardvark.c | 3 +++\n 1 file changed, 3 insertions(+)\n\n--- a/drivers/pci/controller/pci-aardvark.c\n+++ b/drivers/pci/controller/pci-aardvark.c\n@@ -1733,6 +1733,9 @@ static int advk_pcie_remove(struct platf\n \tadvk_pcie_remove_msi_irq_domain(pcie);\n \tadvk_pcie_remove_irq_domain(pcie);\n \n+\t/* Free config space for emulated root bridge */\n+\tpci_bridge_emul_cleanup(&pcie->bridge);\n+\n \t/* Disable outbound address windows mapping */\n \tfor (i = 0; i < OB_WIN_COUNT; i++)\n \t\tadvk_pcie_disable_ob_win(pcie, i);\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/850-v5.17-0009-PCI-aardvark-Assert-PERST-when-unbinding-driver.patch",
    "content": "From 1f54391be8ce0c981d312cb93acdc5608def576a Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>\nDate: Tue, 30 Nov 2021 18:29:11 +0100\nSubject: [PATCH] PCI: aardvark: Assert PERST# when unbinding driver\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nPut the PCIe card into reset by asserting PERST# signal when unbinding\ndriver. It doesn't make sense to leave the card working if it can't\ncommunicate with the host. This should also save some power.\n\nLink: https://lore.kernel.org/r/20211130172913.9727-10-kabel@kernel.org\nSigned-off-by: Pali Rohár <pali@kernel.org>\nSigned-off-by: Marek Behún <kabel@kernel.org>\nSigned-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>\n---\n drivers/pci/controller/pci-aardvark.c | 4 ++++\n 1 file changed, 4 insertions(+)\n\n--- a/drivers/pci/controller/pci-aardvark.c\n+++ b/drivers/pci/controller/pci-aardvark.c\n@@ -1736,6 +1736,10 @@ static int advk_pcie_remove(struct platf\n \t/* Free config space for emulated root bridge */\n \tpci_bridge_emul_cleanup(&pcie->bridge);\n \n+\t/* Assert PERST# signal which prepares PCIe card for power down */\n+\tif (pcie->reset_gpio)\n+\t\tgpiod_set_value_cansleep(pcie->reset_gpio, 1);\n+\n \t/* Disable outbound address windows mapping */\n \tfor (i = 0; i < OB_WIN_COUNT; i++)\n \t\tadvk_pcie_disable_ob_win(pcie, i);\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/850-v5.17-0010-PCI-aardvark-Disable-link-training-when-unbinding-dr.patch",
    "content": "From 759dec2e3dfdbd261c41d2279f04f2351c971a49 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>\nDate: Tue, 30 Nov 2021 18:29:12 +0100\nSubject: [PATCH] PCI: aardvark: Disable link training when unbinding driver\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nDisable link training circuit in driver unbind sequence. We want to\nleave link training in the same state as it was before the driver was\nprobed.\n\nLink: https://lore.kernel.org/r/20211130172913.9727-11-kabel@kernel.org\nSigned-off-by: Pali Rohár <pali@kernel.org>\nSigned-off-by: Marek Behún <kabel@kernel.org>\nSigned-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>\n---\n drivers/pci/controller/pci-aardvark.c | 5 +++++\n 1 file changed, 5 insertions(+)\n\n--- a/drivers/pci/controller/pci-aardvark.c\n+++ b/drivers/pci/controller/pci-aardvark.c\n@@ -1740,6 +1740,11 @@ static int advk_pcie_remove(struct platf\n \tif (pcie->reset_gpio)\n \t\tgpiod_set_value_cansleep(pcie->reset_gpio, 1);\n \n+\t/* Disable link training */\n+\tval = advk_readl(pcie, PCIE_CORE_CTRL0_REG);\n+\tval &= ~LINK_TRAINING_EN;\n+\tadvk_writel(pcie, val, PCIE_CORE_CTRL0_REG);\n+\n \t/* Disable outbound address windows mapping */\n \tfor (i = 0; i < OB_WIN_COUNT; i++)\n \t\tadvk_pcie_disable_ob_win(pcie, i);\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/850-v5.17-0011-PCI-aardvark-Disable-common-PHY-when-unbinding-drive.patch",
    "content": "From fdbbe242c15a8f2cd0e3ad8a56cd0a447b771d0d Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>\nDate: Tue, 30 Nov 2021 18:29:13 +0100\nSubject: [PATCH] PCI: aardvark: Disable common PHY when unbinding driver\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nDisable the PCIe PHY when unbinding driver. This should save some power.\n\nLink: https://lore.kernel.org/r/20211130172913.9727-12-kabel@kernel.org\nSigned-off-by: Pali Rohár <pali@kernel.org>\nSigned-off-by: Marek Behún <kabel@kernel.org>\nSigned-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>\n---\n drivers/pci/controller/pci-aardvark.c | 3 +++\n 1 file changed, 3 insertions(+)\n\n--- a/drivers/pci/controller/pci-aardvark.c\n+++ b/drivers/pci/controller/pci-aardvark.c\n@@ -1749,6 +1749,9 @@ static int advk_pcie_remove(struct platf\n \tfor (i = 0; i < OB_WIN_COUNT; i++)\n \t\tadvk_pcie_disable_ob_win(pcie, i);\n \n+\t/* Disable phy */\n+\tadvk_pcie_disable_phy(pcie);\n+\n \treturn 0;\n }\n \n"
  },
  {
    "path": "target/linux/generic/backport-5.10/851-v5.15-0001-phy-marvell-phy-mvebu-a3700-comphy-Rename-HS-SGMMI-t.patch",
    "content": "From 40da06da15c1718b02072687bbfb2d08f5eb9399 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>\nDate: Fri, 27 Aug 2021 11:27:52 +0200\nSubject: [PATCH] phy: marvell: phy-mvebu-a3700-comphy: Rename HS-SGMMI to\n 2500Base-X\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nComphy phy mode 0x3 is incorrectly named. It is not SGMII but rather\n2500Base-X mode which runs at 3.125 Gbps speed.\n\nRename macro names and comments to 2500Base-X.\n\nSigned-off-by: Pali Rohár <pali@kernel.org>\nFixes: 9695375a3f4a (\"phy: add A3700 COMPHY support\")\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/phy/marvell/phy-mvebu-a3700-comphy.c | 10 +++++-----\n 1 file changed, 5 insertions(+), 5 deletions(-)\n\n--- a/drivers/phy/marvell/phy-mvebu-a3700-comphy.c\n+++ b/drivers/phy/marvell/phy-mvebu-a3700-comphy.c\n@@ -29,7 +29,7 @@\n \n #define COMPHY_FW_MODE_SATA\t\t\t0x1\n #define COMPHY_FW_MODE_SGMII\t\t\t0x2\n-#define COMPHY_FW_MODE_HS_SGMII\t\t\t0x3\n+#define COMPHY_FW_MODE_2500BASEX\t\t0x3\n #define COMPHY_FW_MODE_USB3H\t\t\t0x4\n #define COMPHY_FW_MODE_USB3D\t\t\t0x5\n #define COMPHY_FW_MODE_PCIE\t\t\t0x6\n@@ -40,7 +40,7 @@\n \n #define COMPHY_FW_SPEED_1_25G\t\t\t0 /* SGMII 1G */\n #define COMPHY_FW_SPEED_2_5G\t\t\t1\n-#define COMPHY_FW_SPEED_3_125G\t\t\t2 /* SGMII 2.5G */\n+#define COMPHY_FW_SPEED_3_125G\t\t\t2 /* 2500BASE-X */\n #define COMPHY_FW_SPEED_5G\t\t\t3\n #define COMPHY_FW_SPEED_5_15625G\t\t4 /* XFI 5G */\n #define COMPHY_FW_SPEED_6G\t\t\t5\n@@ -84,14 +84,14 @@ static const struct mvebu_a3700_comphy_c\n \tMVEBU_A3700_COMPHY_CONF_ETH(0, PHY_INTERFACE_MODE_SGMII, 1,\n \t\t\t\t    COMPHY_FW_MODE_SGMII),\n \tMVEBU_A3700_COMPHY_CONF_ETH(0, PHY_INTERFACE_MODE_2500BASEX, 1,\n-\t\t\t\t    COMPHY_FW_MODE_HS_SGMII),\n+\t\t\t\t    COMPHY_FW_MODE_2500BASEX),\n \t/* lane 1 */\n \tMVEBU_A3700_COMPHY_CONF_GEN(1, PHY_MODE_PCIE, 0,\n \t\t\t\t    COMPHY_FW_MODE_PCIE),\n \tMVEBU_A3700_COMPHY_CONF_ETH(1, PHY_INTERFACE_MODE_SGMII, 0,\n \t\t\t\t    COMPHY_FW_MODE_SGMII),\n \tMVEBU_A3700_COMPHY_CONF_ETH(1, PHY_INTERFACE_MODE_2500BASEX, 0,\n-\t\t\t\t    COMPHY_FW_MODE_HS_SGMII),\n+\t\t\t\t    COMPHY_FW_MODE_2500BASEX),\n \t/* lane 2 */\n \tMVEBU_A3700_COMPHY_CONF_GEN(2, PHY_MODE_SATA, 0,\n \t\t\t\t    COMPHY_FW_MODE_SATA),\n@@ -205,7 +205,7 @@ static int mvebu_a3700_comphy_power_on(s\n \t\t\t\t\t\t COMPHY_FW_SPEED_1_25G);\n \t\t\tbreak;\n \t\tcase PHY_INTERFACE_MODE_2500BASEX:\n-\t\t\tdev_dbg(lane->dev, \"set lane %d to HS SGMII mode\\n\",\n+\t\t\tdev_dbg(lane->dev, \"set lane %d to 2500BASEX mode\\n\",\n \t\t\t\tlane->id);\n \t\t\tfw_param = COMPHY_FW_NET(fw_mode, lane->port,\n \t\t\t\t\t\t COMPHY_FW_SPEED_3_125G);\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/851-v5.15-0002-phy-marvell-phy-mvebu-a3700-comphy-Remove-unsupporte.patch",
    "content": "From e1dbe9ecf621b6f71f3d2df3e50731d583f3d27f Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>\nDate: Fri, 27 Aug 2021 11:27:53 +0200\nSubject: [PATCH] phy: marvell: phy-mvebu-a3700-comphy: Remove unsupported\n modes\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nArmada 3700 does not support RXAUI, XFI and neither SFI. Remove unused\nmacros for these unsupported modes.\n\nSigned-off-by: Pali Rohár <pali@kernel.org>\nFixes: 9695375a3f4a (\"phy: add A3700 COMPHY support\")\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/phy/marvell/phy-mvebu-a3700-comphy.c | 6 ------\n 1 file changed, 6 deletions(-)\n\n--- a/drivers/phy/marvell/phy-mvebu-a3700-comphy.c\n+++ b/drivers/phy/marvell/phy-mvebu-a3700-comphy.c\n@@ -33,18 +33,12 @@\n #define COMPHY_FW_MODE_USB3H\t\t\t0x4\n #define COMPHY_FW_MODE_USB3D\t\t\t0x5\n #define COMPHY_FW_MODE_PCIE\t\t\t0x6\n-#define COMPHY_FW_MODE_RXAUI\t\t\t0x7\n-#define COMPHY_FW_MODE_XFI\t\t\t0x8\n-#define COMPHY_FW_MODE_SFI\t\t\t0x9\n #define COMPHY_FW_MODE_USB3\t\t\t0xa\n \n #define COMPHY_FW_SPEED_1_25G\t\t\t0 /* SGMII 1G */\n #define COMPHY_FW_SPEED_2_5G\t\t\t1\n #define COMPHY_FW_SPEED_3_125G\t\t\t2 /* 2500BASE-X */\n #define COMPHY_FW_SPEED_5G\t\t\t3\n-#define COMPHY_FW_SPEED_5_15625G\t\t4 /* XFI 5G */\n-#define COMPHY_FW_SPEED_6G\t\t\t5\n-#define COMPHY_FW_SPEED_10_3125G\t\t6 /* XFI 10G */\n #define COMPHY_FW_SPEED_MAX\t\t\t0x3F\n \n #define COMPHY_FW_MODE(mode)\t\t\t((mode) << 12)\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/860-v5.17-MIPS-ath79-drop-_machine_restart-again.patch",
    "content": "From d3115128bdafb62628ab41861a4f06f6d02ac320 Mon Sep 17 00:00:00 2001\nFrom: Lech Perczak <lech.perczak@gmail.com>\nDate: Mon, 10 Jan 2022 23:48:44 +0100\nSubject: MIPS: ath79: drop _machine_restart again\n\nCommit 81424d0ad0d4 (\"MIPS: ath79: Use the reset controller to restart\nOF machines\") removed setup of _machine_restart on OF machines to use\nreset handler in reset controller driver.\nWhile removing remnants of non-OF machines in commit 3a77e0d75eed\n(\"MIPS: ath79: drop machfiles\"), this was introduced again, making it\nimpossible to use additional restart handlers registered through device\ntree. Drop setting _machine_restart altogether, and ath79_restart\nfunction, which is no longer used after this.\n\nFixes: 3a77e0d75eed (\"MIPS: ath79: drop machfiles\")\nCc: John Crispin <john@phrozen.org>\nCc: Florian Fainelli <f.fainelli@gmail.com>\nSigned-off-by: Lech Perczak <lech.perczak@gmail.com>\nSigned-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>\n---\n arch/mips/ath79/setup.c | 10 ----------\n 1 file changed, 10 deletions(-)\n\n--- a/arch/mips/ath79/setup.c\n+++ b/arch/mips/ath79/setup.c\n@@ -34,15 +34,6 @@\n \n static char ath79_sys_type[ATH79_SYS_TYPE_LEN];\n \n-static void ath79_restart(char *command)\n-{\n-\tlocal_irq_disable();\n-\tath79_device_reset_set(AR71XX_RESET_FULL_CHIP);\n-\tfor (;;)\n-\t\tif (cpu_wait)\n-\t\t\tcpu_wait();\n-}\n-\n static void ath79_halt(void)\n {\n \twhile (1)\n@@ -233,7 +224,6 @@ void __init plat_mem_setup(void)\n \n \tdetect_memory_region(0, ATH79_MEM_SIZE_MIN, ATH79_MEM_SIZE_MAX);\n \n-\t_machine_restart = ath79_restart;\n \t_machine_halt = ath79_halt;\n \tpm_power_off = ath79_halt;\n }\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/870-hwmon-next-hwmon-lm70-Add-ti-tmp125-support.patch",
    "content": "From 31d8f414e1596ba54a4315418e4c0086fda9e428 Mon Sep 17 00:00:00 2001\nFrom: Christian Lamparter <chunkeey@gmail.com>\nDate: Fri, 18 Feb 2022 10:06:43 +0100\nSubject: hwmon: (lm70) Add ti,tmp125 support\n\nThe TMP125 is a 2 degree Celsius accurate Digital\nTemperature Sensor with a SPI interface.\n\nThe temperature register is a 16-bit, read-only register.\nThe MSB (Bit 15) is a leading zero and never set. Bits 14\nto 5 are the 1+9 temperature data bits in a two's\ncomplement format. Bits 4 to 0 are useless copies of\nBit 5 value and therefore ignored.\n\nSigned-off-by: Christian Lamparter <chunkeey@gmail.com>\nLink: https://lore.kernel.org/r/43b19cbd4e7f51e9509e561b02b5d8d0e7079fac.1645175187.git.chunkeey@gmail.com\nSigned-off-by: Guenter Roeck <linux@roeck-us.net>\n---\n--- a/drivers/hwmon/lm70.c\n+++ b/drivers/hwmon/lm70.c\n@@ -34,6 +34,7 @@\n #define LM70_CHIP_LM71\t\t2\t/* NS LM71 */\n #define LM70_CHIP_LM74\t\t3\t/* NS LM74 */\n #define LM70_CHIP_TMP122\t4\t/* TI TMP122/TMP124 */\n+#define LM70_CHIP_TMP125\t5\t/* TI TMP125 */\n \n struct lm70 {\n \tstruct spi_device *spi;\n@@ -87,6 +88,12 @@ static ssize_t temp1_input_show(struct d\n \t * LM71:\n \t * 14 bits of 2's complement data, discard LSB 2 bits,\n \t * resolution 0.0312 degrees celsius.\n+\t *\n+\t * TMP125:\n+\t * MSB/D15 is a leading zero. D14 is the sign-bit. This is\n+\t * followed by 9 temperature bits (D13..D5) in 2's complement\n+\t * data format with a resolution of 0.25 degrees celsius per unit.\n+\t * LSB 5 bits (D4..D0) share the same value as D5 and get discarded.\n \t */\n \tswitch (p_lm70->chip) {\n \tcase LM70_CHIP_LM70:\n@@ -102,6 +109,10 @@ static ssize_t temp1_input_show(struct d\n \tcase LM70_CHIP_LM71:\n \t\tval = ((int)raw / 4) * 3125 / 100;\n \t\tbreak;\n+\n+\tcase LM70_CHIP_TMP125:\n+\t\tval = (sign_extend32(raw, 14) / 32) * 250;\n+\t\tbreak;\n \t}\n \n \tstatus = sprintf(buf, \"%d\\n\", val); /* millidegrees Celsius */\n@@ -136,6 +147,10 @@ static const struct of_device_id lm70_of\n \t\t.data = (void *) LM70_CHIP_TMP122,\n \t},\n \t{\n+\t\t.compatible = \"ti,tmp125\",\n+\t\t.data = (void *) LM70_CHIP_TMP125,\n+\t},\n+\t{\n \t\t.compatible = \"ti,lm71\",\n \t\t.data = (void *) LM70_CHIP_LM71,\n \t},\n@@ -184,6 +199,7 @@ static const struct spi_device_id lm70_i\n \t{ \"lm70\",   LM70_CHIP_LM70 },\n \t{ \"tmp121\", LM70_CHIP_TMP121 },\n \t{ \"tmp122\", LM70_CHIP_TMP122 },\n+\t{ \"tmp125\", LM70_CHIP_TMP125 },\n \t{ \"lm71\",   LM70_CHIP_LM71 },\n \t{ \"lm74\",   LM70_CHIP_LM74 },\n \t{ },\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/880-v5.19-cdc_ether-export-usbnet_cdc_zte_rx_fixup.patch",
    "content": "From d91a03b72c5f9c25e5b976f8f67bcf279601d644 Mon Sep 17 00:00:00 2001\nFrom: Lech Perczak <lech.perczak@gmail.com>\nDate: Fri, 1 Apr 2022 22:03:55 +0200\nSubject: [PATCH 1/3] cdc_ether: export usbnet_cdc_zte_rx_fixup\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nCommit bfe9b9d2df66 (\"cdc_ether: Improve ZTE MF823/831/910 handling\")\nintroduces a workaround for certain ZTE modems reporting invalid MAC\naddresses over CDC-ECM.\nThe same issue was present on their RNDIS interface,which was fixed in\ncommit a5a18bdf7453 (\"rndis_host: Set valid random MAC on buggy devices\").\n\nHowever, internal modem of ZTE MF286R router, on its RNDIS interface, also\nexhibits a second issue fixed already in CDC-ECM, of the device not\nrespecting configured random MAC address. In order to share the fixup for\nthis with rndis_host driver, export the workaround function, which will\nbe re-used in the following commit in rndis_host.\n\nCc: Kristian Evensen <kristian.evensen@gmail.com>\nCc: Bjørn Mork <bjorn@mork.no>\nCc: Oliver Neukum <oliver@neukum.org>\nSigned-off-by: Lech Perczak <lech.perczak@gmail.com>\n---\n drivers/net/usb/cdc_ether.c | 3 ++-\n include/linux/usb/usbnet.h  | 1 +\n 2 files changed, 3 insertions(+), 1 deletion(-)\n\n--- a/drivers/net/usb/cdc_ether.c\n+++ b/drivers/net/usb/cdc_ether.c\n@@ -466,7 +466,7 @@ static int usbnet_cdc_zte_bind(struct us\n  * device MAC address has been updated). Always set MAC address to that of the\n  * device.\n  */\n-static int usbnet_cdc_zte_rx_fixup(struct usbnet *dev, struct sk_buff *skb)\n+int usbnet_cdc_zte_rx_fixup(struct usbnet *dev, struct sk_buff *skb)\n {\n \tif (skb->len < ETH_HLEN || !(skb->data[0] & 0x02))\n \t\treturn 1;\n@@ -476,6 +476,7 @@ static int usbnet_cdc_zte_rx_fixup(struc\n \n \treturn 1;\n }\n+EXPORT_SYMBOL_GPL(usbnet_cdc_zte_rx_fixup);\n \n /* Ensure correct link state\n  *\n--- a/include/linux/usb/usbnet.h\n+++ b/include/linux/usb/usbnet.h\n@@ -215,6 +215,7 @@ extern int usbnet_ether_cdc_bind(struct\n extern int usbnet_cdc_bind(struct usbnet *, struct usb_interface *);\n extern void usbnet_cdc_unbind(struct usbnet *, struct usb_interface *);\n extern void usbnet_cdc_status(struct usbnet *, struct urb *);\n+extern int usbnet_cdc_zte_rx_fixup(struct usbnet *dev, struct sk_buff *skb);\n \n /* CDC and RNDIS support the same host-chosen packet filters for IN transfers */\n #define\tDEFAULT_FILTER\t(USB_CDC_PACKET_TYPE_BROADCAST \\\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/881-v5.19-rndis_host-enable-the-bogus-MAC-fixup-for-ZTE-device.patch",
    "content": "From 69a9efb689b43fedf5f19431f1889aa6b8d35d55 Mon Sep 17 00:00:00 2001\nFrom: Lech Perczak <lech.perczak@gmail.com>\nDate: Fri, 1 Apr 2022 22:04:01 +0200\nSubject: [PATCH 2/3] rndis_host: enable the bogus MAC fixup for ZTE devices\n from cdc_ether\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nCertain ZTE modems, namely: MF823. MF831, MF910, built-in modem from\nMF286R, expose both CDC-ECM and RNDIS network interfaces.\nThey have a trait of ignoring the locally-administered MAC address\nconfigured on the interface both in CDC-ECM and RNDIS part,\nand this leads to dropping of incoming traffic by the host.\nHowever, the workaround was only present in CDC-ECM, and MF286R\nexplicitly requires it in RNDIS mode.\n\nRe-use the workaround in rndis_host as well, to fix operation of MF286R\nmodule, some versions of which expose only the RNDIS interface. Do so by\nintroducing new flag, RNDIS_DRIVER_DATA_DST_MAC_FIXUP, and testing for it\nin rndis_rx_fixup. This is required, as RNDIS uses frame batching, and all\nof the packets inside the batch need the fixup. This might introduce a\nperformance penalty, because test is done for every returned Ethernet\nframe.\n\nApply the workaround to both \"flavors\" of RNDIS interfaces, as older ZTE\nmodems, like MF823 found in the wild, report the USB_CLASS_COMM class\ninterfaces, while MF286R reports USB_CLASS_WIRELESS_CONTROLLER.\n\nSuggested-by: Bjørn Mork <bjorn@mork.no>\nCc: Kristian Evensen <kristian.evensen@gmail.com>\nCc: Oliver Neukum <oliver@neukum.org>\nSigned-off-by: Lech Perczak <lech.perczak@gmail.com>\n---\n drivers/net/usb/rndis_host.c   | 32 ++++++++++++++++++++++++++++++++\n include/linux/usb/rndis_host.h |  1 +\n 2 files changed, 33 insertions(+)\n\n--- a/drivers/net/usb/rndis_host.c\n+++ b/drivers/net/usb/rndis_host.c\n@@ -485,10 +485,14 @@ EXPORT_SYMBOL_GPL(rndis_unbind);\n  */\n int rndis_rx_fixup(struct usbnet *dev, struct sk_buff *skb)\n {\n+\tbool dst_mac_fixup;\n+\n \t/* This check is no longer done by usbnet */\n \tif (skb->len < dev->net->hard_header_len)\n \t\treturn 0;\n \n+\tdst_mac_fixup = !!(dev->driver_info->data & RNDIS_DRIVER_DATA_DST_MAC_FIXUP);\n+\n \t/* peripheral may have batched packets to us... */\n \twhile (likely(skb->len)) {\n \t\tstruct rndis_data_hdr\t*hdr = (void *)skb->data;\n@@ -523,10 +527,17 @@ int rndis_rx_fixup(struct usbnet *dev, s\n \t\t\tbreak;\n \t\tskb_pull(skb, msg_len - sizeof *hdr);\n \t\tskb_trim(skb2, data_len);\n+\n+\t\tif (unlikely(dst_mac_fixup))\n+\t\t\tusbnet_cdc_zte_rx_fixup(dev, skb2);\n+\n \t\tusbnet_skb_return(dev, skb2);\n \t}\n \n \t/* caller will usbnet_skb_return the remaining packet */\n+\tif (unlikely(dst_mac_fixup))\n+\t\tusbnet_cdc_zte_rx_fixup(dev, skb);\n+\n \treturn 1;\n }\n EXPORT_SYMBOL_GPL(rndis_rx_fixup);\n@@ -600,6 +611,17 @@ static const struct driver_info\trndis_po\n \t.tx_fixup =\trndis_tx_fixup,\n };\n \n+static const struct driver_info\tzte_rndis_info = {\n+\t.description =\t\"ZTE RNDIS device\",\n+\t.flags =\tFLAG_ETHER | FLAG_POINTTOPOINT | FLAG_FRAMING_RN | FLAG_NO_SETINT,\n+\t.data =\t\tRNDIS_DRIVER_DATA_DST_MAC_FIXUP,\n+\t.bind =\t\trndis_bind,\n+\t.unbind =\trndis_unbind,\n+\t.status =\trndis_status,\n+\t.rx_fixup =\trndis_rx_fixup,\n+\t.tx_fixup =\trndis_tx_fixup,\n+};\n+\n /*-------------------------------------------------------------------------*/\n \n static const struct usb_device_id\tproducts [] = {\n@@ -609,6 +631,16 @@ static const struct usb_device_id\tproduc\n \t\t\t\t      USB_CLASS_COMM, 2 /* ACM */, 0x0ff),\n \t.driver_info = (unsigned long) &rndis_poll_status_info,\n }, {\n+\t/* ZTE WWAN modules */\n+\tUSB_VENDOR_AND_INTERFACE_INFO(0x19d2,\n+\t\t\t\t      USB_CLASS_WIRELESS_CONTROLLER, 1, 3),\n+\t.driver_info = (unsigned long)&zte_rndis_info,\n+}, {\n+\t/* ZTE WWAN modules, ACM flavour */\n+\tUSB_VENDOR_AND_INTERFACE_INFO(0x19d2,\n+\t\t\t\t      USB_CLASS_COMM, 2 /* ACM */, 0x0ff),\n+\t.driver_info = (unsigned long)&zte_rndis_info,\n+}, {\n \t/* Hytera Communications DMR radios' \"Radio to PC Network\" */\n \tUSB_VENDOR_AND_INTERFACE_INFO(0x238b,\n \t\t\t\t      USB_CLASS_COMM, 2 /* ACM */, 0x0ff),\n--- a/include/linux/usb/rndis_host.h\n+++ b/include/linux/usb/rndis_host.h\n@@ -197,6 +197,7 @@ struct rndis_keepalive_c {\t/* IN (option\n \n /* Flags for driver_info::data */\n #define RNDIS_DRIVER_DATA_POLL_STATUS\t1\t/* poll status before control */\n+#define RNDIS_DRIVER_DATA_DST_MAC_FIXUP\t2\t/* device ignores configured MAC address */\n \n extern void rndis_status(struct usbnet *dev, struct urb *urb);\n extern int\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/882-v5.19-rndis_host-limit-scope-of-bogus-MAC-address-detectio.patch",
    "content": "From 1bfbe1799b9ec5d00f7f032d6e7db1980e466aeb Mon Sep 17 00:00:00 2001\nFrom: Lech Perczak <lech.perczak@gmail.com>\nDate: Sat, 2 Apr 2022 02:19:57 +0200\nSubject: [PATCH 3/3] rndis_host: limit scope of bogus MAC address detection to\n ZTE devices\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nReporting of bogus MAC addresses and ignoring configuration of new\ndestination address wasn't observed outside of a range of ZTE devices,\namong which this seems to be the common bug. Align rndis_host driver\nwith implementation found in cdc_ether, which also limits this workaround\nto ZTE devices.\n\nSuggested-by: Bjørn Mork <bjorn@mork.no>\nCc: Kristian Evensen <kristian.evensen@gmail.com>\nCc: Oliver Neukum <oliver@neukum.org>\nSigned-off-by: Lech Perczak <lech.perczak@gmail.com>\n---\n drivers/net/usb/rndis_host.c | 17 ++++++++++++-----\n 1 file changed, 12 insertions(+), 5 deletions(-)\n\n--- a/drivers/net/usb/rndis_host.c\n+++ b/drivers/net/usb/rndis_host.c\n@@ -418,10 +418,7 @@ generic_rndis_bind(struct usbnet *dev, s\n \t\tgoto halt_fail_and_release;\n \t}\n \n-\tif (bp[0] & 0x02)\n-\t\teth_hw_addr_random(net);\n-\telse\n-\t\tether_addr_copy(net->dev_addr, bp);\n+\tether_addr_copy(net->dev_addr, bp);\n \n \t/* set a nonzero filter to enable data transfers */\n \tmemset(u.set, 0, sizeof *u.set);\n@@ -463,6 +460,16 @@ static int rndis_bind(struct usbnet *dev\n \treturn generic_rndis_bind(dev, intf, FLAG_RNDIS_PHYM_NOT_WIRELESS);\n }\n \n+static int zte_rndis_bind(struct usbnet *dev, struct usb_interface *intf)\n+{\n+\tint status = rndis_bind(dev, intf);\n+\n+\tif (!status && (dev->net->dev_addr[0] & 0x02))\n+\t\teth_hw_addr_random(dev->net);\n+\n+\treturn status;\n+}\n+\n void rndis_unbind(struct usbnet *dev, struct usb_interface *intf)\n {\n \tstruct rndis_halt\t*halt;\n@@ -615,7 +622,7 @@ static const struct driver_info\tzte_rndi\n \t.description =\t\"ZTE RNDIS device\",\n \t.flags =\tFLAG_ETHER | FLAG_POINTTOPOINT | FLAG_FRAMING_RN | FLAG_NO_SETINT,\n \t.data =\t\tRNDIS_DRIVER_DATA_DST_MAC_FIXUP,\n-\t.bind =\t\trndis_bind,\n+\t.bind =\t\tzte_rndis_bind,\n \t.unbind =\trndis_unbind,\n \t.status =\trndis_status,\n \t.rx_fixup =\trndis_rx_fixup,\n"
  },
  {
    "path": "target/linux/generic/backport-5.10/890-v5.19-net-sfp-Add-tx-fault-workaround-for-Huawei-MA5671A-SFP-ON.patch",
    "content": "From f81d97cb646ab8b90fb181d66fccaf9589990de6 Mon Sep 17 00:00:00 2001\nFrom: Matthew Hagan <mnhagan88@gmail.com>\nDate: Sat, 30 Apr 2022 11:00:49 +0100\nSubject: [PATCH v2] net: sfp: Add tx-fault workaround for Huawei MA5671A SFP\n ONT\n\nAs noted elsewhere, various GPON SFP modules exhibit non-standard\nTX-fault behaviour. In the tested case, the Huawei MA5671A, when used\nin combination with a Marvell mv88e6085 switch, was found to\npersistently assert TX-fault, resulting in the module being disabled.\n\nThis patch adds a quirk to ignore the SFP_F_TX_FAULT state, allowing the\nmodule to function.\n\nChange from v1: removal of erroneous return statment (Andrew Lunn)\n\nSigned-off-by: Matthew Hagan <mnhagan88@gmail.com>\nReviewed-by: Andrew Lunn <andrew@lunn.ch>\n---\n drivers/net/phy/sfp.c | 12 +++++++++++-\n 1 file changed, 11 insertions(+), 1 deletion(-)\n\n--- a/drivers/net/phy/sfp.c\n+++ b/drivers/net/phy/sfp.c\n@@ -249,6 +249,7 @@ struct sfp {\n \tstruct sfp_eeprom_id id;\n \tunsigned int module_power_mW;\n \tunsigned int module_t_start_up;\n+\tbool tx_fault_ignore;\n \n #if IS_ENABLED(CONFIG_HWMON)\n \tstruct sfp_diag diag;\n@@ -1893,6 +1894,12 @@ static int sfp_sm_mod_probe(struct sfp *\n \telse\n \t\tsfp->module_t_start_up = T_START_UP;\n \n+\tif (!memcmp(id.base.vendor_name, \"HUAWEI          \", 16) &&\n+\t    !memcmp(id.base.vendor_pn, \"MA5671A         \", 16))\n+\t\tsfp->tx_fault_ignore = true;\n+\telse\n+\t\tsfp->tx_fault_ignore = false;\n+\n \treturn 0;\n }\n \n@@ -2320,7 +2327,10 @@ static void sfp_check_state(struct sfp *\n \tmutex_lock(&sfp->st_mutex);\n \tstate = sfp_get_state(sfp);\n \tchanged = state ^ sfp->state;\n-\tchanged &= SFP_F_PRESENT | SFP_F_LOS | SFP_F_TX_FAULT;\n+\tif (sfp->tx_fault_ignore)\n+\t\tchanged &= SFP_F_PRESENT | SFP_F_LOS;\n+\telse\n+\t\tchanged &= SFP_F_PRESENT | SFP_F_LOS | SFP_F_TX_FAULT;\n \n \tfor (i = 0; i < GPIO_MAX; i++)\n \t\tif (changed & BIT(i))\n"
  },
  {
    "path": "target/linux/generic/backport-5.15/011-kbuild-export-SUBARCH.patch",
    "content": "From 173019b66dcc9d68ad9333aa744dad1e369b5aa8 Mon Sep 17 00:00:00 2001\nFrom: Felix Fietkau <nbd@nbd.name>\nDate: Sun, 9 Jul 2017 00:26:53 +0200\nSubject: [PATCH 34/34] kernel: add compile fix for linux 4.9 on x86\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n Makefile | 4 ++--\n 1 file changed, 2 insertions(+), 2 deletions(-)\n\n--- a/Makefile\n+++ b/Makefile\n@@ -523,7 +523,7 @@ KBUILD_LDFLAGS_MODULE :=\n KBUILD_LDFLAGS :=\n CLANG_FLAGS :=\n \n-export ARCH SRCARCH CONFIG_SHELL BASH HOSTCC KBUILD_HOSTCFLAGS CROSS_COMPILE LD CC\n+export ARCH SRCARCH SUBARCH CONFIG_SHELL BASH HOSTCC KBUILD_HOSTCFLAGS CROSS_COMPILE LD CC\n export CPP AR NM STRIP OBJCOPY OBJDUMP READELF PAHOLE RESOLVE_BTFIDS LEX YACC AWK INSTALLKERNEL\n export PERL PYTHON3 CHECK CHECKFLAGS MAKE UTS_MACHINE HOSTCXX\n export KGZIP KBZIP2 KLZOP LZMA LZ4 XZ ZSTD\n"
  },
  {
    "path": "target/linux/generic/backport-5.15/050-v5.16-00-MIPS-uasm-Enable-muhu-opcode-for-MIPS-R6.patch",
    "content": "From: Johan Almbladh <johan.almbladh@anyfinetworks.com>\nDate: Tue, 5 Oct 2021 18:54:02 +0200\nSubject: [PATCH] MIPS: uasm: Enable muhu opcode for MIPS R6\n\nEnable the 'muhu' instruction, complementing the existing 'mulu', needed\nto implement a MIPS32 BPF JIT.\n\nAlso fix a typo in the existing definition of 'dmulu'.\n\nSigned-off-by: Tony Ambardar <Tony.Ambardar@gmail.com>\n\nThis patch is a dependency for my 32-bit MIPS eBPF JIT.\n\nSigned-off-by: Johan Almbladh <johan.almbladh@anyfinetworks.com>\n---\n\n--- a/arch/mips/include/asm/uasm.h\n+++ b/arch/mips/include/asm/uasm.h\n@@ -145,6 +145,7 @@ Ip_u1(_mtlo);\n Ip_u3u1u2(_mul);\n Ip_u1u2(_multu);\n Ip_u3u1u2(_mulu);\n+Ip_u3u1u2(_muhu);\n Ip_u3u1u2(_nor);\n Ip_u3u1u2(_or);\n Ip_u2u1u3(_ori);\n--- a/arch/mips/mm/uasm-mips.c\n+++ b/arch/mips/mm/uasm-mips.c\n@@ -90,7 +90,7 @@ static const struct insn insn_table[insn\n \t\t\t\tRS | RT | RD},\n \t[insn_dmtc0]\t= {M(cop0_op, dmtc_op, 0, 0, 0, 0), RT | RD | SET},\n \t[insn_dmultu]\t= {M(spec_op, 0, 0, 0, 0, dmultu_op), RS | RT},\n-\t[insn_dmulu]\t= {M(spec_op, 0, 0, 0, dmult_dmul_op, dmultu_op),\n+\t[insn_dmulu]\t= {M(spec_op, 0, 0, 0, dmultu_dmulu_op, dmultu_op),\n \t\t\t\tRS | RT | RD},\n \t[insn_drotr]\t= {M(spec_op, 1, 0, 0, 0, dsrl_op), RT | RD | RE},\n \t[insn_drotr32]\t= {M(spec_op, 1, 0, 0, 0, dsrl32_op), RT | RD | RE},\n@@ -150,6 +150,8 @@ static const struct insn insn_table[insn\n \t[insn_mtlo]\t= {M(spec_op, 0, 0, 0, 0, mtlo_op), RS},\n \t[insn_mulu]\t= {M(spec_op, 0, 0, 0, multu_mulu_op, multu_op),\n \t\t\t\tRS | RT | RD},\n+\t[insn_muhu]\t= {M(spec_op, 0, 0, 0, multu_muhu_op, multu_op),\n+\t\t\t\tRS | RT | RD},\n #ifndef CONFIG_CPU_MIPSR6\n \t[insn_mul]\t= {M(spec2_op, 0, 0, 0, 0, mul_op), RS | RT | RD},\n #else\n--- a/arch/mips/mm/uasm.c\n+++ b/arch/mips/mm/uasm.c\n@@ -59,7 +59,7 @@ enum opcode {\n \tinsn_lddir, insn_ldpte, insn_ldx, insn_lh, insn_lhu, insn_ll, insn_lld,\n \tinsn_lui, insn_lw, insn_lwu, insn_lwx, insn_mfc0, insn_mfhc0, insn_mfhi,\n \tinsn_mflo, insn_modu, insn_movn, insn_movz, insn_mtc0, insn_mthc0,\n-\tinsn_mthi, insn_mtlo, insn_mul, insn_multu, insn_mulu, insn_nor,\n+\tinsn_mthi, insn_mtlo, insn_mul, insn_multu, insn_mulu, insn_muhu, insn_nor,\n \tinsn_or, insn_ori, insn_pref, insn_rfe, insn_rotr, insn_sb, insn_sc,\n \tinsn_scd, insn_seleqz, insn_selnez, insn_sd, insn_sh, insn_sll,\n \tinsn_sllv, insn_slt, insn_slti, insn_sltiu, insn_sltu, insn_sra,\n@@ -344,6 +344,7 @@ I_u1(_mtlo)\n I_u3u1u2(_mul)\n I_u1u2(_multu)\n I_u3u1u2(_mulu)\n+I_u3u1u2(_muhu)\n I_u3u1u2(_nor)\n I_u3u1u2(_or)\n I_u2u1u3(_ori)\n"
  },
  {
    "path": "target/linux/generic/backport-5.15/050-v5.16-01-mips-uasm-Add-workaround-for-Loongson-2F-nop-CPU-err.patch",
    "content": "From: Johan Almbladh <johan.almbladh@anyfinetworks.com>\nDate: Tue, 5 Oct 2021 18:54:03 +0200\nSubject: [PATCH] mips: uasm: Add workaround for Loongson-2F nop CPU errata\n\nThis patch implements a workaround for the Loongson-2F nop in generated,\ncode, if the existing option CONFIG_CPU_NOP_WORKAROUND is set. Before,\nthe binutils option -mfix-loongson2f-nop was enabled, but no workaround\nwas done when emitting MIPS code. Now, the nop pseudo instruction is\nemitted as \"or ax,ax,zero\" instead of the default \"sll zero,zero,0\". This\nis consistent with the workaround implemented by binutils.\n\nLink: https://sourceware.org/legacy-ml/binutils/2009-11/msg00387.html\n\nSigned-off-by: Johan Almbladh <johan.almbladh@anyfinetworks.com>\nReviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>\n---\n\n--- a/arch/mips/include/asm/uasm.h\n+++ b/arch/mips/include/asm/uasm.h\n@@ -249,7 +249,11 @@ static inline void uasm_l##lb(struct uas\n #define uasm_i_bnezl(buf, rs, off) uasm_i_bnel(buf, rs, 0, off)\n #define uasm_i_ehb(buf) uasm_i_sll(buf, 0, 0, 3)\n #define uasm_i_move(buf, a, b) UASM_i_ADDU(buf, a, 0, b)\n+#ifdef CONFIG_CPU_NOP_WORKAROUNDS\n+#define uasm_i_nop(buf) uasm_i_or(buf, 1, 1, 0)\n+#else\n #define uasm_i_nop(buf) uasm_i_sll(buf, 0, 0, 0)\n+#endif\n #define uasm_i_ssnop(buf) uasm_i_sll(buf, 0, 0, 1)\n \n static inline void uasm_i_drotr_safe(u32 **p, unsigned int a1,\n"
  },
  {
    "path": "target/linux/generic/backport-5.15/050-v5.16-02-mips-bpf-Add-eBPF-JIT-for-32-bit-MIPS.patch",
    "content": "From: Johan Almbladh <johan.almbladh@anyfinetworks.com>\nDate: Tue, 5 Oct 2021 18:54:04 +0200\nSubject: [PATCH] mips: bpf: Add eBPF JIT for 32-bit MIPS\n\nThis is an implementation of an eBPF JIT for 32-bit MIPS I-V and MIPS32.\nThe implementation supports all 32-bit and 64-bit ALU and JMP operations,\nincluding the recently-added atomics. 64-bit div/mod and 64-bit atomics\nare implemented using function calls to math64 and atomic64 functions,\nrespectively. All 32-bit operations are implemented natively by the JIT,\nexcept if the CPU lacks ll/sc instructions.\n\nRegister mapping\n================\nAll 64-bit eBPF registers are mapped to native 32-bit MIPS register pairs,\nand does not use any stack scratch space for register swapping. This means\nthat all eBPF register data is kept in CPU registers all the time, and\nthis simplifies the register management a lot. It also reduces the JIT's\npressure on temporary registers since we do not have to move data around.\n\nNative register pairs are ordered according to CPU endiannes, following\nthe O32 calling convention for passing 64-bit arguments and return values.\nThe eBPF return value, arguments and callee-saved registers are mapped to\ntheir native MIPS equivalents.\n\nSince the 32 highest bits in the eBPF FP (frame pointer) register are\nalways zero, only one general-purpose register is actually needed for the\nmapping. The MIPS fp register is used for this purpose. The high bits are\nmapped to MIPS register r0. This saves us one CPU register, which is much\nneeded for temporaries, while still allowing us to treat the R10 (FP)\nregister just like any other eBPF register in the JIT.\n\nThe MIPS gp (global pointer) and at (assembler temporary) registers are\nused as internal temporary registers for constant blinding. CPU registers\nt6-t9 are used internally by the JIT when constructing more complex 64-bit\noperations. This is precisely what is needed - two registers to store an\noperand value, and two more as scratch registers when performing the\noperation.\n\nThe register mapping is shown below.\n\n    R0 - $v1, $v0   return value\n    R1 - $a1, $a0   argument 1, passed in registers\n    R2 - $a3, $a2   argument 2, passed in registers\n    R3 - $t1, $t0   argument 3, passed on stack\n    R4 - $t3, $t2   argument 4, passed on stack\n    R5 - $t4, $t3   argument 5, passed on stack\n    R6 - $s1, $s0   callee-saved\n    R7 - $s3, $s2   callee-saved\n    R8 - $s5, $s4   callee-saved\n    R9 - $s7, $s6   callee-saved\n    FP - $r0, $fp   32-bit frame pointer\n    AX - $gp, $at   constant-blinding\n         $t6 - $t9  unallocated, JIT temporaries\n\nJump offsets\n============\nThe JIT tries to map all conditional JMP operations to MIPS conditional\nPC-relative branches. The MIPS branch offset field is 18 bits, in bytes,\nwhich is equivalent to the eBPF 16-bit instruction offset. However, since\nthe JIT may emit more than one CPU instruction per eBPF instruction, the\nfield width may overflow. If that happens, the JIT converts the long\nconditional jump to a short PC-relative branch with the condition\ninverted, jumping over a long unconditional absolute jmp (j).\n\nThis conversion will change the instruction offset mapping used for jumps,\nand may in turn result in more branch offset overflows. The JIT therefore\ndry-runs the translation until no more branches are converted and the\noffsets do not change anymore. There is an upper bound on this of course,\nand if the JIT hits that limit, the last two iterations are run with all\nbranches being converted.\n\nTail call count\n===============\nThe current tail call count is stored in the 16-byte area of the caller's\nstack frame that is reserved for the callee in the o32 ABI. The value is\ninitialized in the prologue, and propagated to the tail-callee by skipping\nthe initialization instructions when emitting the tail call.\n\nSigned-off-by: Johan Almbladh <johan.almbladh@anyfinetworks.com>\n---\n create mode 100644 arch/mips/net/bpf_jit_comp.c\n create mode 100644 arch/mips/net/bpf_jit_comp.h\n create mode 100644 arch/mips/net/bpf_jit_comp32.c\n\n--- a/arch/mips/net/Makefile\n+++ b/arch/mips/net/Makefile\n@@ -2,4 +2,9 @@\n # MIPS networking code\n \n obj-$(CONFIG_MIPS_CBPF_JIT) += bpf_jit.o bpf_jit_asm.o\n-obj-$(CONFIG_MIPS_EBPF_JIT) += ebpf_jit.o\n+\n+ifeq ($(CONFIG_32BIT),y)\n+        obj-$(CONFIG_MIPS_EBPF_JIT) += bpf_jit_comp.o bpf_jit_comp32.o\n+else\n+        obj-$(CONFIG_MIPS_EBPF_JIT) += ebpf_jit.o\n+endif\n--- /dev/null\n+++ b/arch/mips/net/bpf_jit_comp.c\n@@ -0,0 +1,1020 @@\n+// SPDX-License-Identifier: GPL-2.0-only\n+/*\n+ * Just-In-Time compiler for eBPF bytecode on MIPS.\n+ * Implementation of JIT functions common to 32-bit and 64-bit CPUs.\n+ *\n+ * Copyright (c) 2021 Anyfi Networks AB.\n+ * Author: Johan Almbladh <johan.almbladh@gmail.com>\n+ *\n+ * Based on code and ideas from\n+ * Copyright (c) 2017 Cavium, Inc.\n+ * Copyright (c) 2017 Shubham Bansal <illusionist.neo@gmail.com>\n+ * Copyright (c) 2011 Mircea Gherzan <mgherzan@gmail.com>\n+ */\n+\n+/*\n+ * Code overview\n+ * =============\n+ *\n+ * - bpf_jit_comp.h\n+ *   Common definitions and utilities.\n+ *\n+ * - bpf_jit_comp.c\n+ *   Implementation of JIT top-level logic and exported JIT API functions.\n+ *   Implementation of internal operations shared by 32-bit and 64-bit code.\n+ *   JMP and ALU JIT control code, register control code, shared ALU and\n+ *   JMP/JMP32 JIT operations.\n+ *\n+ * - bpf_jit_comp32.c\n+ *   Implementation of functions to JIT prologue, epilogue and a single eBPF\n+ *   instruction for 32-bit MIPS CPUs. The functions use shared operations\n+ *   where possible, and implement the rest for 32-bit MIPS such as ALU64\n+ *   operations.\n+ *\n+ * - bpf_jit_comp64.c\n+ *   Ditto, for 64-bit MIPS CPUs.\n+ *\n+ * Zero and sign extension\n+ * ========================\n+ * 32-bit MIPS instructions on 64-bit MIPS registers use sign extension,\n+ * but the eBPF instruction set mandates zero extension. We let the verifier\n+ * insert explicit zero-extensions after 32-bit ALU operations, both for\n+ * 32-bit and 64-bit MIPS JITs. Conditional JMP32 operations on 64-bit MIPs\n+ * are JITed with sign extensions inserted when so expected.\n+ *\n+ * ALU operations\n+ * ==============\n+ * ALU operations on 32/64-bit MIPS and ALU64 operations on 64-bit MIPS are\n+ * JITed in the following steps. ALU64 operations on 32-bit MIPS are more\n+ * complicated and therefore only processed by special implementations in\n+ * step (3).\n+ *\n+ * 1) valid_alu_i:\n+ *    Determine if an immediate operation can be emitted as such, or if\n+ *    we must fall back to the register version.\n+ *\n+ * 2) rewrite_alu_i:\n+ *    Convert BPF operation and immediate value to a canonical form for\n+ *    JITing. In some degenerate cases this form may be a no-op.\n+ *\n+ * 3) emit_alu_{i,i64,r,64}:\n+ *    Emit instructions for an ALU or ALU64 immediate or register operation.\n+ *\n+ * JMP operations\n+ * ==============\n+ * JMP and JMP32 operations require an JIT instruction offset table for\n+ * translating the jump offset. This table is computed by dry-running the\n+ * JIT without actually emitting anything. However, the computed PC-relative\n+ * offset may overflow the 18-bit offset field width of the native MIPS\n+ * branch instruction. In such cases, the long jump is converted into the\n+ * following sequence.\n+ *\n+ *    <branch> !<cond> +2    Inverted PC-relative branch\n+ *    nop                    Delay slot\n+ *    j <offset>             Unconditional absolute long jump\n+ *    nop                    Delay slot\n+ *\n+ * Since this converted sequence alters the offset table, all offsets must\n+ * be re-calculated. This may in turn trigger new branch conversions, so\n+ * the process is repeated until no further changes are made. Normally it\n+ * completes in 1-2 iterations. If JIT_MAX_ITERATIONS should reached, we\n+ * fall back to converting every remaining jump operation. The branch\n+ * conversion is independent of how the JMP or JMP32 condition is JITed.\n+ *\n+ * JMP32 and JMP operations are JITed as follows.\n+ *\n+ * 1) setup_jmp_{i,r}:\n+ *    Convert jump conditional and offset into a form that can be JITed.\n+ *    This form may be a no-op, a canonical form, or an inverted PC-relative\n+ *    jump if branch conversion is necessary.\n+ *\n+ * 2) valid_jmp_i:\n+ *    Determine if an immediate operations can be emitted as such, or if\n+ *    we must fall back to the register version. Applies to JMP32 for 32-bit\n+ *    MIPS, and both JMP and JMP32 for 64-bit MIPS.\n+ *\n+ * 3) emit_jmp_{i,i64,r,r64}:\n+ *    Emit instructions for an JMP or JMP32 immediate or register operation.\n+ *\n+ * 4) finish_jmp_{i,r}:\n+ *    Emit any instructions needed to finish the jump. This includes a nop\n+ *    for the delay slot if a branch was emitted, and a long absolute jump\n+ *    if the branch was converted.\n+ */\n+\n+#include <linux/limits.h>\n+#include <linux/bitops.h>\n+#include <linux/errno.h>\n+#include <linux/filter.h>\n+#include <linux/bpf.h>\n+#include <linux/slab.h>\n+#include <asm/bitops.h>\n+#include <asm/cacheflush.h>\n+#include <asm/cpu-features.h>\n+#include <asm/isa-rev.h>\n+#include <asm/uasm.h>\n+\n+#include \"bpf_jit_comp.h\"\n+\n+/* Convenience macros for descriptor access */\n+#define CONVERTED(desc)\t((desc) & JIT_DESC_CONVERT)\n+#define INDEX(desc)\t((desc) & ~JIT_DESC_CONVERT)\n+\n+/*\n+ * Push registers on the stack, starting at a given depth from the stack\n+ * pointer and increasing. The next depth to be written is returned.\n+ */\n+int push_regs(struct jit_context *ctx, u32 mask, u32 excl, int depth)\n+{\n+\tint reg;\n+\n+\tfor (reg = 0; reg < BITS_PER_BYTE * sizeof(mask); reg++)\n+\t\tif (mask & BIT(reg)) {\n+\t\t\tif ((excl & BIT(reg)) == 0) {\n+\t\t\t\tif (sizeof(long) == 4)\n+\t\t\t\t\temit(ctx, sw, reg, depth, MIPS_R_SP);\n+\t\t\t\telse /* sizeof(long) == 8 */\n+\t\t\t\t\temit(ctx, sd, reg, depth, MIPS_R_SP);\n+\t\t\t}\n+\t\t\tdepth += sizeof(long);\n+\t\t}\n+\n+\tctx->stack_used = max((int)ctx->stack_used, depth);\n+\treturn depth;\n+}\n+\n+/*\n+ * Pop registers from the stack, starting at a given depth from the stack\n+ * pointer and increasing. The next depth to be read is returned.\n+ */\n+int pop_regs(struct jit_context *ctx, u32 mask, u32 excl, int depth)\n+{\n+\tint reg;\n+\n+\tfor (reg = 0; reg < BITS_PER_BYTE * sizeof(mask); reg++)\n+\t\tif (mask & BIT(reg)) {\n+\t\t\tif ((excl & BIT(reg)) == 0) {\n+\t\t\t\tif (sizeof(long) == 4)\n+\t\t\t\t\temit(ctx, lw, reg, depth, MIPS_R_SP);\n+\t\t\t\telse /* sizeof(long) == 8 */\n+\t\t\t\t\temit(ctx, ld, reg, depth, MIPS_R_SP);\n+\t\t\t}\n+\t\t\tdepth += sizeof(long);\n+\t\t}\n+\n+\treturn depth;\n+}\n+\n+/* Compute the 28-bit jump target address from a BPF program location */\n+int get_target(struct jit_context *ctx, u32 loc)\n+{\n+\tu32 index = INDEX(ctx->descriptors[loc]);\n+\tunsigned long pc = (unsigned long)&ctx->target[ctx->jit_index];\n+\tunsigned long addr = (unsigned long)&ctx->target[index];\n+\n+\tif (!ctx->target)\n+\t\treturn 0;\n+\n+\tif ((addr ^ pc) & ~MIPS_JMP_MASK)\n+\t\treturn -1;\n+\n+\treturn addr & MIPS_JMP_MASK;\n+}\n+\n+/* Compute the PC-relative offset to relative BPF program offset */\n+int get_offset(const struct jit_context *ctx, int off)\n+{\n+\treturn (INDEX(ctx->descriptors[ctx->bpf_index + off]) -\n+\t\tctx->jit_index - 1) * sizeof(u32);\n+}\n+\n+/* dst = imm (register width) */\n+void emit_mov_i(struct jit_context *ctx, u8 dst, s32 imm)\n+{\n+\tif (imm >= -0x8000 && imm <= 0x7fff) {\n+\t\temit(ctx, addiu, dst, MIPS_R_ZERO, imm);\n+\t} else {\n+\t\temit(ctx, lui, dst, (s16)((u32)imm >> 16));\n+\t\temit(ctx, ori, dst, dst, (u16)(imm & 0xffff));\n+\t}\n+\tclobber_reg(ctx, dst);\n+}\n+\n+/* dst = src (register width) */\n+void emit_mov_r(struct jit_context *ctx, u8 dst, u8 src)\n+{\n+\temit(ctx, ori, dst, src, 0);\n+\tclobber_reg(ctx, dst);\n+}\n+\n+/* Validate ALU immediate range */\n+bool valid_alu_i(u8 op, s32 imm)\n+{\n+\tswitch (BPF_OP(op)) {\n+\tcase BPF_NEG:\n+\tcase BPF_LSH:\n+\tcase BPF_RSH:\n+\tcase BPF_ARSH:\n+\t\t/* All legal eBPF values are valid */\n+\t\treturn true;\n+\tcase BPF_ADD:\n+\t\t/* imm must be 16 bits */\n+\t\treturn imm >= -0x8000 && imm <= 0x7fff;\n+\tcase BPF_SUB:\n+\t\t/* -imm must be 16 bits */\n+\t\treturn imm >= -0x7fff && imm <= 0x8000;\n+\tcase BPF_AND:\n+\tcase BPF_OR:\n+\tcase BPF_XOR:\n+\t\t/* imm must be 16 bits unsigned */\n+\t\treturn imm >= 0 && imm <= 0xffff;\n+\tcase BPF_MUL:\n+\t\t/* imm must be zero or a positive power of two */\n+\t\treturn imm == 0 || (imm > 0 && is_power_of_2(imm));\n+\tcase BPF_DIV:\n+\tcase BPF_MOD:\n+\t\t/* imm must be an 17-bit power of two */\n+\t\treturn (u32)imm <= 0x10000 && is_power_of_2((u32)imm);\n+\t}\n+\treturn false;\n+}\n+\n+/* Rewrite ALU immediate operation */\n+bool rewrite_alu_i(u8 op, s32 imm, u8 *alu, s32 *val)\n+{\n+\tbool act = true;\n+\n+\tswitch (BPF_OP(op)) {\n+\tcase BPF_LSH:\n+\tcase BPF_RSH:\n+\tcase BPF_ARSH:\n+\tcase BPF_ADD:\n+\tcase BPF_SUB:\n+\tcase BPF_OR:\n+\tcase BPF_XOR:\n+\t\t/* imm == 0 is a no-op */\n+\t\tact = imm != 0;\n+\t\tbreak;\n+\tcase BPF_MUL:\n+\t\tif (imm == 1) {\n+\t\t\t/* dst * 1 is a no-op */\n+\t\t\tact = false;\n+\t\t} else if (imm == 0) {\n+\t\t\t/* dst * 0 is dst & 0 */\n+\t\t\top = BPF_AND;\n+\t\t} else {\n+\t\t\t/* dst * (1 << n) is dst << n */\n+\t\t\top = BPF_LSH;\n+\t\t\timm = ilog2(abs(imm));\n+\t\t}\n+\t\tbreak;\n+\tcase BPF_DIV:\n+\t\tif (imm == 1) {\n+\t\t\t/* dst / 1 is a no-op */\n+\t\t\tact = false;\n+\t\t} else {\n+\t\t\t/* dst / (1 << n) is dst >> n */\n+\t\t\top = BPF_RSH;\n+\t\t\timm = ilog2(imm);\n+\t\t}\n+\t\tbreak;\n+\tcase BPF_MOD:\n+\t\t/* dst % (1 << n) is dst & ((1 << n) - 1) */\n+\t\top = BPF_AND;\n+\t\timm--;\n+\t\tbreak;\n+\t}\n+\n+\t*alu = op;\n+\t*val = imm;\n+\treturn act;\n+}\n+\n+/* ALU immediate operation (32-bit) */\n+void emit_alu_i(struct jit_context *ctx, u8 dst, s32 imm, u8 op)\n+{\n+\tswitch (BPF_OP(op)) {\n+\t/* dst = -dst */\n+\tcase BPF_NEG:\n+\t\temit(ctx, subu, dst, MIPS_R_ZERO, dst);\n+\t\tbreak;\n+\t/* dst = dst & imm */\n+\tcase BPF_AND:\n+\t\temit(ctx, andi, dst, dst, (u16)imm);\n+\t\tbreak;\n+\t/* dst = dst | imm */\n+\tcase BPF_OR:\n+\t\temit(ctx, ori, dst, dst, (u16)imm);\n+\t\tbreak;\n+\t/* dst = dst ^ imm */\n+\tcase BPF_XOR:\n+\t\temit(ctx, xori, dst, dst, (u16)imm);\n+\t\tbreak;\n+\t/* dst = dst << imm */\n+\tcase BPF_LSH:\n+\t\temit(ctx, sll, dst, dst, imm);\n+\t\tbreak;\n+\t/* dst = dst >> imm */\n+\tcase BPF_RSH:\n+\t\temit(ctx, srl, dst, dst, imm);\n+\t\tbreak;\n+\t/* dst = dst >> imm (arithmetic) */\n+\tcase BPF_ARSH:\n+\t\temit(ctx, sra, dst, dst, imm);\n+\t\tbreak;\n+\t/* dst = dst + imm */\n+\tcase BPF_ADD:\n+\t\temit(ctx, addiu, dst, dst, imm);\n+\t\tbreak;\n+\t/* dst = dst - imm */\n+\tcase BPF_SUB:\n+\t\temit(ctx, addiu, dst, dst, -imm);\n+\t\tbreak;\n+\t}\n+\tclobber_reg(ctx, dst);\n+}\n+\n+/* ALU register operation (32-bit) */\n+void emit_alu_r(struct jit_context *ctx, u8 dst, u8 src, u8 op)\n+{\n+\tswitch (BPF_OP(op)) {\n+\t/* dst = dst & src */\n+\tcase BPF_AND:\n+\t\temit(ctx, and, dst, dst, src);\n+\t\tbreak;\n+\t/* dst = dst | src */\n+\tcase BPF_OR:\n+\t\temit(ctx, or, dst, dst, src);\n+\t\tbreak;\n+\t/* dst = dst ^ src */\n+\tcase BPF_XOR:\n+\t\temit(ctx, xor, dst, dst, src);\n+\t\tbreak;\n+\t/* dst = dst << src */\n+\tcase BPF_LSH:\n+\t\temit(ctx, sllv, dst, dst, src);\n+\t\tbreak;\n+\t/* dst = dst >> src */\n+\tcase BPF_RSH:\n+\t\temit(ctx, srlv, dst, dst, src);\n+\t\tbreak;\n+\t/* dst = dst >> src (arithmetic) */\n+\tcase BPF_ARSH:\n+\t\temit(ctx, srav, dst, dst, src);\n+\t\tbreak;\n+\t/* dst = dst + src */\n+\tcase BPF_ADD:\n+\t\temit(ctx, addu, dst, dst, src);\n+\t\tbreak;\n+\t/* dst = dst - src */\n+\tcase BPF_SUB:\n+\t\temit(ctx, subu, dst, dst, src);\n+\t\tbreak;\n+\t/* dst = dst * src */\n+\tcase BPF_MUL:\n+\t\tif (cpu_has_mips32r1 || cpu_has_mips32r6) {\n+\t\t\temit(ctx, mul, dst, dst, src);\n+\t\t} else {\n+\t\t\temit(ctx, multu, dst, src);\n+\t\t\temit(ctx, mflo, dst);\n+\t\t}\n+\t\tbreak;\n+\t/* dst = dst / src */\n+\tcase BPF_DIV:\n+\t\tif (cpu_has_mips32r6) {\n+\t\t\temit(ctx, divu_r6, dst, dst, src);\n+\t\t} else {\n+\t\t\temit(ctx, divu, dst, src);\n+\t\t\temit(ctx, mflo, dst);\n+\t\t}\n+\t\tbreak;\n+\t/* dst = dst % src */\n+\tcase BPF_MOD:\n+\t\tif (cpu_has_mips32r6) {\n+\t\t\temit(ctx, modu, dst, dst, src);\n+\t\t} else {\n+\t\t\temit(ctx, divu, dst, src);\n+\t\t\temit(ctx, mfhi, dst);\n+\t\t}\n+\t\tbreak;\n+\t}\n+\tclobber_reg(ctx, dst);\n+}\n+\n+/* Atomic read-modify-write (32-bit) */\n+void emit_atomic_r(struct jit_context *ctx, u8 dst, u8 src, s16 off, u8 code)\n+{\n+\temit(ctx, ll, MIPS_R_T9, off, dst);\n+\tswitch (code) {\n+\tcase BPF_ADD:\n+\t\temit(ctx, addu, MIPS_R_T8, MIPS_R_T9, src);\n+\t\tbreak;\n+\tcase BPF_AND:\n+\t\temit(ctx, and, MIPS_R_T8, MIPS_R_T9, src);\n+\t\tbreak;\n+\tcase BPF_OR:\n+\t\temit(ctx, or, MIPS_R_T8, MIPS_R_T9, src);\n+\t\tbreak;\n+\tcase BPF_XOR:\n+\t\temit(ctx, xor, MIPS_R_T8, MIPS_R_T9, src);\n+\t\tbreak;\n+\t}\n+\temit(ctx, sc, MIPS_R_T8, off, dst);\n+\temit(ctx, beqz, MIPS_R_T8, -16);\n+\temit(ctx, nop); /* Delay slot */\n+}\n+\n+/* Atomic compare-and-exchange (32-bit) */\n+void emit_cmpxchg_r(struct jit_context *ctx, u8 dst, u8 src, u8 res, s16 off)\n+{\n+\temit(ctx, ll, MIPS_R_T9, off, dst);\n+\temit(ctx, bne, MIPS_R_T9, res, 12);\n+\temit(ctx, move, MIPS_R_T8, src);     /* Delay slot */\n+\temit(ctx, sc, MIPS_R_T8, off, dst);\n+\temit(ctx, beqz, MIPS_R_T8, -20);\n+\temit(ctx, move, res, MIPS_R_T9);     /* Delay slot */\n+\tclobber_reg(ctx, res);\n+}\n+\n+/* Swap bytes and truncate a register word or half word */\n+void emit_bswap_r(struct jit_context *ctx, u8 dst, u32 width)\n+{\n+\tu8 tmp = MIPS_R_T8;\n+\tu8 msk = MIPS_R_T9;\n+\n+\tswitch (width) {\n+\t/* Swap bytes in a word */\n+\tcase 32:\n+\t\tif (cpu_has_mips32r2 || cpu_has_mips32r6) {\n+\t\t\temit(ctx, wsbh, dst, dst);\n+\t\t\temit(ctx, rotr, dst, dst, 16);\n+\t\t} else {\n+\t\t\temit(ctx, sll, tmp, dst, 16);    /* tmp  = dst << 16 */\n+\t\t\temit(ctx, srl, dst, dst, 16);    /* dst = dst >> 16  */\n+\t\t\temit(ctx, or, dst, dst, tmp);    /* dst = dst | tmp  */\n+\n+\t\t\temit(ctx, lui, msk, 0xff);       /* msk = 0x00ff0000 */\n+\t\t\temit(ctx, ori, msk, msk, 0xff);  /* msk = msk | 0xff */\n+\n+\t\t\temit(ctx, and, tmp, dst, msk);   /* tmp = dst & msk  */\n+\t\t\temit(ctx, sll, tmp, tmp, 8);     /* tmp = tmp << 8   */\n+\t\t\temit(ctx, srl, dst, dst, 8);     /* dst = dst >> 8   */\n+\t\t\temit(ctx, and, dst, dst, msk);   /* dst = dst & msk  */\n+\t\t\temit(ctx, or, dst, dst, tmp);    /* reg = dst | tmp  */\n+\t\t}\n+\t\tbreak;\n+\t/* Swap bytes in a half word */\n+\tcase 16:\n+\t\tif (cpu_has_mips32r2 || cpu_has_mips32r6) {\n+\t\t\temit(ctx, wsbh, dst, dst);\n+\t\t\temit(ctx, andi, dst, dst, 0xffff);\n+\t\t} else {\n+\t\t\temit(ctx, andi, tmp, dst, 0xff00); /* t = d & 0xff00 */\n+\t\t\temit(ctx, srl, tmp, tmp, 8);       /* t = t >> 8     */\n+\t\t\temit(ctx, andi, dst, dst, 0x00ff); /* d = d & 0x00ff */\n+\t\t\temit(ctx, sll, dst, dst, 8);       /* d = d << 8     */\n+\t\t\temit(ctx, or,  dst, dst, tmp);     /* d = d | t      */\n+\t\t}\n+\t\tbreak;\n+\t}\n+\tclobber_reg(ctx, dst);\n+}\n+\n+/* Validate jump immediate range */\n+bool valid_jmp_i(u8 op, s32 imm)\n+{\n+\tswitch (op) {\n+\tcase JIT_JNOP:\n+\t\t/* Immediate value not used */\n+\t\treturn true;\n+\tcase BPF_JEQ:\n+\tcase BPF_JNE:\n+\t\t/* No immediate operation */\n+\t\treturn false;\n+\tcase BPF_JSET:\n+\tcase JIT_JNSET:\n+\t\t/* imm must be 16 bits unsigned */\n+\t\treturn imm >= 0 && imm <= 0xffff;\n+\tcase BPF_JGE:\n+\tcase BPF_JLT:\n+\tcase BPF_JSGE:\n+\tcase BPF_JSLT:\n+\t\t/* imm must be 16 bits */\n+\t\treturn imm >= -0x8000 && imm <= 0x7fff;\n+\tcase BPF_JGT:\n+\tcase BPF_JLE:\n+\tcase BPF_JSGT:\n+\tcase BPF_JSLE:\n+\t\t/* imm + 1 must be 16 bits */\n+\t\treturn imm >= -0x8001 && imm <= 0x7ffe;\n+\t}\n+\treturn false;\n+}\n+\n+/* Invert a conditional jump operation */\n+static u8 invert_jmp(u8 op)\n+{\n+\tswitch (op) {\n+\tcase BPF_JA: return JIT_JNOP;\n+\tcase BPF_JEQ: return BPF_JNE;\n+\tcase BPF_JNE: return BPF_JEQ;\n+\tcase BPF_JSET: return JIT_JNSET;\n+\tcase BPF_JGT: return BPF_JLE;\n+\tcase BPF_JGE: return BPF_JLT;\n+\tcase BPF_JLT: return BPF_JGE;\n+\tcase BPF_JLE: return BPF_JGT;\n+\tcase BPF_JSGT: return BPF_JSLE;\n+\tcase BPF_JSGE: return BPF_JSLT;\n+\tcase BPF_JSLT: return BPF_JSGE;\n+\tcase BPF_JSLE: return BPF_JSGT;\n+\t}\n+\treturn 0;\n+}\n+\n+/* Prepare a PC-relative jump operation */\n+static void setup_jmp(struct jit_context *ctx, u8 bpf_op,\n+\t\t      s16 bpf_off, u8 *jit_op, s32 *jit_off)\n+{\n+\tu32 *descp = &ctx->descriptors[ctx->bpf_index];\n+\tint op = bpf_op;\n+\tint offset = 0;\n+\n+\t/* Do not compute offsets on the first pass */\n+\tif (INDEX(*descp) == 0)\n+\t\tgoto done;\n+\n+\t/* Skip jumps never taken */\n+\tif (bpf_op == JIT_JNOP)\n+\t\tgoto done;\n+\n+\t/* Convert jumps always taken */\n+\tif (bpf_op == BPF_JA)\n+\t\t*descp |= JIT_DESC_CONVERT;\n+\n+\t/*\n+\t * Current ctx->jit_index points to the start of the branch preamble.\n+\t * Since the preamble differs among different branch conditionals,\n+\t * the current index cannot be used to compute the branch offset.\n+\t * Instead, we use the offset table value for the next instruction,\n+\t * which gives the index immediately after the branch delay slot.\n+\t */\n+\tif (!CONVERTED(*descp)) {\n+\t\tint target = ctx->bpf_index + bpf_off + 1;\n+\t\tint origin = ctx->bpf_index + 1;\n+\n+\t\toffset = (INDEX(ctx->descriptors[target]) -\n+\t\t\t  INDEX(ctx->descriptors[origin]) + 1) * sizeof(u32);\n+\t}\n+\n+\t/*\n+\t * The PC-relative branch offset field on MIPS is 18 bits signed,\n+\t * so if the computed offset is larger than this we generate a an\n+\t * absolute jump that we skip with an inverted conditional branch.\n+\t */\n+\tif (CONVERTED(*descp) || offset < -0x20000 || offset > 0x1ffff) {\n+\t\toffset = 3 * sizeof(u32);\n+\t\top = invert_jmp(bpf_op);\n+\t\tctx->changes += !CONVERTED(*descp);\n+\t\t*descp |= JIT_DESC_CONVERT;\n+\t}\n+\n+done:\n+\t*jit_off = offset;\n+\t*jit_op = op;\n+}\n+\n+/* Prepare a PC-relative jump operation with immediate conditional */\n+void setup_jmp_i(struct jit_context *ctx, s32 imm, u8 width,\n+\t\t u8 bpf_op, s16 bpf_off, u8 *jit_op, s32 *jit_off)\n+{\n+\tbool always = false;\n+\tbool never = false;\n+\n+\tswitch (bpf_op) {\n+\tcase BPF_JEQ:\n+\tcase BPF_JNE:\n+\t\tbreak;\n+\tcase BPF_JSET:\n+\tcase BPF_JLT:\n+\t\tnever = imm == 0;\n+\t\tbreak;\n+\tcase BPF_JGE:\n+\t\talways = imm == 0;\n+\t\tbreak;\n+\tcase BPF_JGT:\n+\t\tnever = (u32)imm == U32_MAX;\n+\t\tbreak;\n+\tcase BPF_JLE:\n+\t\talways = (u32)imm == U32_MAX;\n+\t\tbreak;\n+\tcase BPF_JSGT:\n+\t\tnever = imm == S32_MAX && width == 32;\n+\t\tbreak;\n+\tcase BPF_JSGE:\n+\t\talways = imm == S32_MIN && width == 32;\n+\t\tbreak;\n+\tcase BPF_JSLT:\n+\t\tnever = imm == S32_MIN && width == 32;\n+\t\tbreak;\n+\tcase BPF_JSLE:\n+\t\talways = imm == S32_MAX && width == 32;\n+\t\tbreak;\n+\t}\n+\n+\tif (never)\n+\t\tbpf_op = JIT_JNOP;\n+\tif (always)\n+\t\tbpf_op = BPF_JA;\n+\tsetup_jmp(ctx, bpf_op, bpf_off, jit_op, jit_off);\n+}\n+\n+/* Prepare a PC-relative jump operation with register conditional */\n+void setup_jmp_r(struct jit_context *ctx, bool same_reg,\n+\t\t u8 bpf_op, s16 bpf_off, u8 *jit_op, s32 *jit_off)\n+{\n+\tswitch (bpf_op) {\n+\tcase BPF_JSET:\n+\t\tbreak;\n+\tcase BPF_JEQ:\n+\tcase BPF_JGE:\n+\tcase BPF_JLE:\n+\tcase BPF_JSGE:\n+\tcase BPF_JSLE:\n+\t\tif (same_reg)\n+\t\t\tbpf_op = BPF_JA;\n+\t\tbreak;\n+\tcase BPF_JNE:\n+\tcase BPF_JLT:\n+\tcase BPF_JGT:\n+\tcase BPF_JSGT:\n+\tcase BPF_JSLT:\n+\t\tif (same_reg)\n+\t\t\tbpf_op = JIT_JNOP;\n+\t\tbreak;\n+\t}\n+\tsetup_jmp(ctx, bpf_op, bpf_off, jit_op, jit_off);\n+}\n+\n+/* Finish a PC-relative jump operation */\n+int finish_jmp(struct jit_context *ctx, u8 jit_op, s16 bpf_off)\n+{\n+\t/* Emit conditional branch delay slot */\n+\tif (jit_op != JIT_JNOP)\n+\t\temit(ctx, nop);\n+\t/*\n+\t * Emit an absolute long jump with delay slot,\n+\t * if the PC-relative branch was converted.\n+\t */\n+\tif (CONVERTED(ctx->descriptors[ctx->bpf_index])) {\n+\t\tint target = get_target(ctx, ctx->bpf_index + bpf_off + 1);\n+\n+\t\tif (target < 0)\n+\t\t\treturn -1;\n+\t\temit(ctx, j, target);\n+\t\temit(ctx, nop);\n+\t}\n+\treturn 0;\n+}\n+\n+/* Jump immediate (32-bit) */\n+void emit_jmp_i(struct jit_context *ctx, u8 dst, s32 imm, s32 off, u8 op)\n+{\n+\tswitch (op) {\n+\t/* No-op, used internally for branch optimization */\n+\tcase JIT_JNOP:\n+\t\tbreak;\n+\t/* PC += off if dst & imm */\n+\tcase BPF_JSET:\n+\t\temit(ctx, andi, MIPS_R_T9, dst, (u16)imm);\n+\t\temit(ctx, bnez, MIPS_R_T9, off);\n+\t\tbreak;\n+\t/* PC += off if (dst & imm) == 0 (not in BPF, used for long jumps) */\n+\tcase JIT_JNSET:\n+\t\temit(ctx, andi, MIPS_R_T9, dst, (u16)imm);\n+\t\temit(ctx, beqz, MIPS_R_T9, off);\n+\t\tbreak;\n+\t/* PC += off if dst > imm */\n+\tcase BPF_JGT:\n+\t\temit(ctx, sltiu, MIPS_R_T9, dst, imm + 1);\n+\t\temit(ctx, beqz, MIPS_R_T9, off);\n+\t\tbreak;\n+\t/* PC += off if dst >= imm */\n+\tcase BPF_JGE:\n+\t\temit(ctx, sltiu, MIPS_R_T9, dst, imm);\n+\t\temit(ctx, beqz, MIPS_R_T9, off);\n+\t\tbreak;\n+\t/* PC += off if dst < imm */\n+\tcase BPF_JLT:\n+\t\temit(ctx, sltiu, MIPS_R_T9, dst, imm);\n+\t\temit(ctx, bnez, MIPS_R_T9, off);\n+\t\tbreak;\n+\t/* PC += off if dst <= imm */\n+\tcase BPF_JLE:\n+\t\temit(ctx, sltiu, MIPS_R_T9, dst, imm + 1);\n+\t\temit(ctx, bnez, MIPS_R_T9, off);\n+\t\tbreak;\n+\t/* PC += off if dst > imm (signed) */\n+\tcase BPF_JSGT:\n+\t\temit(ctx, slti, MIPS_R_T9, dst, imm + 1);\n+\t\temit(ctx, beqz, MIPS_R_T9, off);\n+\t\tbreak;\n+\t/* PC += off if dst >= imm (signed) */\n+\tcase BPF_JSGE:\n+\t\temit(ctx, slti, MIPS_R_T9, dst, imm);\n+\t\temit(ctx, beqz, MIPS_R_T9, off);\n+\t\tbreak;\n+\t/* PC += off if dst < imm (signed) */\n+\tcase BPF_JSLT:\n+\t\temit(ctx, slti, MIPS_R_T9, dst, imm);\n+\t\temit(ctx, bnez, MIPS_R_T9, off);\n+\t\tbreak;\n+\t/* PC += off if dst <= imm (signed) */\n+\tcase BPF_JSLE:\n+\t\temit(ctx, slti, MIPS_R_T9, dst, imm + 1);\n+\t\temit(ctx, bnez, MIPS_R_T9, off);\n+\t\tbreak;\n+\t}\n+}\n+\n+/* Jump register (32-bit) */\n+void emit_jmp_r(struct jit_context *ctx, u8 dst, u8 src, s32 off, u8 op)\n+{\n+\tswitch (op) {\n+\t/* No-op, used internally for branch optimization */\n+\tcase JIT_JNOP:\n+\t\tbreak;\n+\t/* PC += off if dst == src */\n+\tcase BPF_JEQ:\n+\t\temit(ctx, beq, dst, src, off);\n+\t\tbreak;\n+\t/* PC += off if dst != src */\n+\tcase BPF_JNE:\n+\t\temit(ctx, bne, dst, src, off);\n+\t\tbreak;\n+\t/* PC += off if dst & src */\n+\tcase BPF_JSET:\n+\t\temit(ctx, and, MIPS_R_T9, dst, src);\n+\t\temit(ctx, bnez, MIPS_R_T9, off);\n+\t\tbreak;\n+\t/* PC += off if (dst & imm) == 0 (not in BPF, used for long jumps) */\n+\tcase JIT_JNSET:\n+\t\temit(ctx, and, MIPS_R_T9, dst, src);\n+\t\temit(ctx, beqz, MIPS_R_T9, off);\n+\t\tbreak;\n+\t/* PC += off if dst > src */\n+\tcase BPF_JGT:\n+\t\temit(ctx, sltu, MIPS_R_T9, src, dst);\n+\t\temit(ctx, bnez, MIPS_R_T9, off);\n+\t\tbreak;\n+\t/* PC += off if dst >= src */\n+\tcase BPF_JGE:\n+\t\temit(ctx, sltu, MIPS_R_T9, dst, src);\n+\t\temit(ctx, beqz, MIPS_R_T9, off);\n+\t\tbreak;\n+\t/* PC += off if dst < src */\n+\tcase BPF_JLT:\n+\t\temit(ctx, sltu, MIPS_R_T9, dst, src);\n+\t\temit(ctx, bnez, MIPS_R_T9, off);\n+\t\tbreak;\n+\t/* PC += off if dst <= src */\n+\tcase BPF_JLE:\n+\t\temit(ctx, sltu, MIPS_R_T9, src, dst);\n+\t\temit(ctx, beqz, MIPS_R_T9, off);\n+\t\tbreak;\n+\t/* PC += off if dst > src (signed) */\n+\tcase BPF_JSGT:\n+\t\temit(ctx, slt, MIPS_R_T9, src, dst);\n+\t\temit(ctx, bnez, MIPS_R_T9, off);\n+\t\tbreak;\n+\t/* PC += off if dst >= src (signed) */\n+\tcase BPF_JSGE:\n+\t\temit(ctx, slt, MIPS_R_T9, dst, src);\n+\t\temit(ctx, beqz, MIPS_R_T9, off);\n+\t\tbreak;\n+\t/* PC += off if dst < src (signed) */\n+\tcase BPF_JSLT:\n+\t\temit(ctx, slt, MIPS_R_T9, dst, src);\n+\t\temit(ctx, bnez, MIPS_R_T9, off);\n+\t\tbreak;\n+\t/* PC += off if dst <= src (signed) */\n+\tcase BPF_JSLE:\n+\t\temit(ctx, slt, MIPS_R_T9, src, dst);\n+\t\temit(ctx, beqz, MIPS_R_T9, off);\n+\t\tbreak;\n+\t}\n+}\n+\n+/* Jump always */\n+int emit_ja(struct jit_context *ctx, s16 off)\n+{\n+\tint target = get_target(ctx, ctx->bpf_index + off + 1);\n+\n+\tif (target < 0)\n+\t\treturn -1;\n+\temit(ctx, j, target);\n+\temit(ctx, nop);\n+\treturn 0;\n+}\n+\n+/* Jump to epilogue */\n+int emit_exit(struct jit_context *ctx)\n+{\n+\tint target = get_target(ctx, ctx->program->len);\n+\n+\tif (target < 0)\n+\t\treturn -1;\n+\temit(ctx, j, target);\n+\temit(ctx, nop);\n+\treturn 0;\n+}\n+\n+/* Build the program body from eBPF bytecode */\n+static int build_body(struct jit_context *ctx)\n+{\n+\tconst struct bpf_prog *prog = ctx->program;\n+\tunsigned int i;\n+\n+\tctx->stack_used = 0;\n+\tfor (i = 0; i < prog->len; i++) {\n+\t\tconst struct bpf_insn *insn = &prog->insnsi[i];\n+\t\tu32 *descp = &ctx->descriptors[i];\n+\t\tint ret;\n+\n+\t\taccess_reg(ctx, insn->src_reg);\n+\t\taccess_reg(ctx, insn->dst_reg);\n+\n+\t\tctx->bpf_index = i;\n+\t\tif (ctx->target == NULL) {\n+\t\t\tctx->changes += INDEX(*descp) != ctx->jit_index;\n+\t\t\t*descp &= JIT_DESC_CONVERT;\n+\t\t\t*descp |= ctx->jit_index;\n+\t\t}\n+\n+\t\tret = build_insn(insn, ctx);\n+\t\tif (ret < 0)\n+\t\t\treturn ret;\n+\n+\t\tif (ret > 0) {\n+\t\t\ti++;\n+\t\t\tif (ctx->target == NULL)\n+\t\t\t\tdescp[1] = ctx->jit_index;\n+\t\t}\n+\t}\n+\n+\t/* Store the end offset, where the epilogue begins */\n+\tctx->descriptors[prog->len] = ctx->jit_index;\n+\treturn 0;\n+}\n+\n+/* Set the branch conversion flag on all instructions */\n+static void set_convert_flag(struct jit_context *ctx, bool enable)\n+{\n+\tconst struct bpf_prog *prog = ctx->program;\n+\tu32 flag = enable ? JIT_DESC_CONVERT : 0;\n+\tunsigned int i;\n+\n+\tfor (i = 0; i <= prog->len; i++)\n+\t\tctx->descriptors[i] = INDEX(ctx->descriptors[i]) | flag;\n+}\n+\n+static void jit_fill_hole(void *area, unsigned int size)\n+{\n+\tu32 *p;\n+\n+\t/* We are guaranteed to have aligned memory. */\n+\tfor (p = area; size >= sizeof(u32); size -= sizeof(u32))\n+\t\tuasm_i_break(&p, BRK_BUG); /* Increments p */\n+}\n+\n+bool bpf_jit_needs_zext(void)\n+{\n+\treturn true;\n+}\n+\n+struct bpf_prog *bpf_int_jit_compile(struct bpf_prog *prog)\n+{\n+\tstruct bpf_prog *tmp, *orig_prog = prog;\n+\tstruct bpf_binary_header *header = NULL;\n+\tstruct jit_context ctx;\n+\tbool tmp_blinded = false;\n+\tunsigned int tmp_idx;\n+\tunsigned int image_size;\n+\tu8 *image_ptr;\n+\tint tries;\n+\n+\t/*\n+\t * If BPF JIT was not enabled then we must fall back to\n+\t * the interpreter.\n+\t */\n+\tif (!prog->jit_requested)\n+\t\treturn orig_prog;\n+\t/*\n+\t * If constant blinding was enabled and we failed during blinding\n+\t * then we must fall back to the interpreter. Otherwise, we save\n+\t * the new JITed code.\n+\t */\n+\ttmp = bpf_jit_blind_constants(prog);\n+\tif (IS_ERR(tmp))\n+\t\treturn orig_prog;\n+\tif (tmp != prog) {\n+\t\ttmp_blinded = true;\n+\t\tprog = tmp;\n+\t}\n+\n+\tmemset(&ctx, 0, sizeof(ctx));\n+\tctx.program = prog;\n+\n+\t/*\n+\t * Not able to allocate memory for descriptors[], then\n+\t * we must fall back to the interpreter\n+\t */\n+\tctx.descriptors = kcalloc(prog->len + 1, sizeof(*ctx.descriptors),\n+\t\t\t\t  GFP_KERNEL);\n+\tif (ctx.descriptors == NULL)\n+\t\tgoto out_err;\n+\n+\t/* First pass discovers used resources */\n+\tif (build_body(&ctx) < 0)\n+\t\tgoto out_err;\n+\t/*\n+\t * Second pass computes instruction offsets.\n+\t * If any PC-relative branches are out of range, a sequence of\n+\t * a PC-relative branch + a jump is generated, and we have to\n+\t * try again from the beginning to generate the new offsets.\n+\t * This is done until no additional conversions are necessary.\n+\t * The last two iterations are done with all branches being\n+\t * converted, to guarantee offset table convergence within a\n+\t * fixed number of iterations.\n+\t */\n+\tctx.jit_index = 0;\n+\tbuild_prologue(&ctx);\n+\ttmp_idx = ctx.jit_index;\n+\n+\ttries = JIT_MAX_ITERATIONS;\n+\tdo {\n+\t\tctx.jit_index = tmp_idx;\n+\t\tctx.changes = 0;\n+\t\tif (tries == 2)\n+\t\t\tset_convert_flag(&ctx, true);\n+\t\tif (build_body(&ctx) < 0)\n+\t\t\tgoto out_err;\n+\t} while (ctx.changes > 0 && --tries > 0);\n+\n+\tif (WARN_ONCE(ctx.changes > 0, \"JIT offsets failed to converge\"))\n+\t\tgoto out_err;\n+\n+\tbuild_epilogue(&ctx, MIPS_R_RA);\n+\n+\t/* Now we know the size of the structure to make */\n+\timage_size = sizeof(u32) * ctx.jit_index;\n+\theader = bpf_jit_binary_alloc(image_size, &image_ptr,\n+\t\t\t\t      sizeof(u32), jit_fill_hole);\n+\t/*\n+\t * Not able to allocate memory for the structure then\n+\t * we must fall back to the interpretation\n+\t */\n+\tif (header == NULL)\n+\t\tgoto out_err;\n+\n+\t/* Actual pass to generate final JIT code */\n+\tctx.target = (u32 *)image_ptr;\n+\tctx.jit_index = 0;\n+\n+\t/*\n+\t * If building the JITed code fails somehow,\n+\t * we fall back to the interpretation.\n+\t */\n+\tbuild_prologue(&ctx);\n+\tif (build_body(&ctx) < 0)\n+\t\tgoto out_err;\n+\tbuild_epilogue(&ctx, MIPS_R_RA);\n+\n+\t/* Populate line info meta data */\n+\tset_convert_flag(&ctx, false);\n+\tbpf_prog_fill_jited_linfo(prog, &ctx.descriptors[1]);\n+\n+\t/* Set as read-only exec and flush instruction cache */\n+\tbpf_jit_binary_lock_ro(header);\n+\tflush_icache_range((unsigned long)header,\n+\t\t\t   (unsigned long)&ctx.target[ctx.jit_index]);\n+\n+\tif (bpf_jit_enable > 1)\n+\t\tbpf_jit_dump(prog->len, image_size, 2, ctx.target);\n+\n+\tprog->bpf_func = (void *)ctx.target;\n+\tprog->jited = 1;\n+\tprog->jited_len = image_size;\n+\n+out:\n+\tif (tmp_blinded)\n+\t\tbpf_jit_prog_release_other(prog, prog == orig_prog ?\n+\t\t\t\t\t   tmp : orig_prog);\n+\tkfree(ctx.descriptors);\n+\treturn prog;\n+\n+out_err:\n+\tprog = orig_prog;\n+\tif (header)\n+\t\tbpf_jit_binary_free(header);\n+\tgoto out;\n+}\n--- /dev/null\n+++ b/arch/mips/net/bpf_jit_comp.h\n@@ -0,0 +1,211 @@\n+/* SPDX-License-Identifier: GPL-2.0-only */\n+/*\n+ * Just-In-Time compiler for eBPF bytecode on 32-bit and 64-bit MIPS.\n+ *\n+ * Copyright (c) 2021 Anyfi Networks AB.\n+ * Author: Johan Almbladh <johan.almbladh@gmail.com>\n+ *\n+ * Based on code and ideas from\n+ * Copyright (c) 2017 Cavium, Inc.\n+ * Copyright (c) 2017 Shubham Bansal <illusionist.neo@gmail.com>\n+ * Copyright (c) 2011 Mircea Gherzan <mgherzan@gmail.com>\n+ */\n+\n+#ifndef _BPF_JIT_COMP_H\n+#define _BPF_JIT_COMP_H\n+\n+/* MIPS registers */\n+#define MIPS_R_ZERO\t0   /* Const zero */\n+#define MIPS_R_AT\t1   /* Asm temp   */\n+#define MIPS_R_V0\t2   /* Result     */\n+#define MIPS_R_V1\t3   /* Result     */\n+#define MIPS_R_A0\t4   /* Argument   */\n+#define MIPS_R_A1\t5   /* Argument   */\n+#define MIPS_R_A2\t6   /* Argument   */\n+#define MIPS_R_A3\t7   /* Argument   */\n+#define MIPS_R_A4\t8   /* Arg (n64)  */\n+#define MIPS_R_A5\t9   /* Arg (n64)  */\n+#define MIPS_R_A6\t10  /* Arg (n64)  */\n+#define MIPS_R_A7\t11  /* Arg (n64)  */\n+#define MIPS_R_T0\t8   /* Temp (o32) */\n+#define MIPS_R_T1\t9   /* Temp (o32) */\n+#define MIPS_R_T2\t10  /* Temp (o32) */\n+#define MIPS_R_T3\t11  /* Temp (o32) */\n+#define MIPS_R_T4\t12  /* Temporary  */\n+#define MIPS_R_T5\t13  /* Temporary  */\n+#define MIPS_R_T6\t14  /* Temporary  */\n+#define MIPS_R_T7\t15  /* Temporary  */\n+#define MIPS_R_S0\t16  /* Saved      */\n+#define MIPS_R_S1\t17  /* Saved      */\n+#define MIPS_R_S2\t18  /* Saved      */\n+#define MIPS_R_S3\t19  /* Saved      */\n+#define MIPS_R_S4\t20  /* Saved      */\n+#define MIPS_R_S5\t21  /* Saved      */\n+#define MIPS_R_S6\t22  /* Saved      */\n+#define MIPS_R_S7\t23  /* Saved      */\n+#define MIPS_R_T8\t24  /* Temporary  */\n+#define MIPS_R_T9\t25  /* Temporary  */\n+/*      MIPS_R_K0\t26     Reserved   */\n+/*      MIPS_R_K1\t27     Reserved   */\n+#define MIPS_R_GP\t28  /* Global ptr */\n+#define MIPS_R_SP\t29  /* Stack ptr  */\n+#define MIPS_R_FP\t30  /* Frame ptr  */\n+#define MIPS_R_RA\t31  /* Return     */\n+\n+/*\n+ * Jump address mask for immediate jumps. The four most significant bits\n+ * must be equal to PC.\n+ */\n+#define MIPS_JMP_MASK\t0x0fffffffUL\n+\n+/* Maximum number of iterations in offset table computation */\n+#define JIT_MAX_ITERATIONS\t8\n+\n+/*\n+ * Jump pseudo-instructions used internally\n+ * for branch conversion and branch optimization.\n+ */\n+#define JIT_JNSET\t0xe0\n+#define JIT_JNOP\t0xf0\n+\n+/* Descriptor flag for PC-relative branch conversion */\n+#define JIT_DESC_CONVERT\tBIT(31)\n+\n+/* JIT context for an eBPF program */\n+struct jit_context {\n+\tstruct bpf_prog *program;     /* The eBPF program being JITed        */\n+\tu32 *descriptors;             /* eBPF to JITed CPU insn descriptors  */\n+\tu32 *target;                  /* JITed code buffer                   */\n+\tu32 bpf_index;                /* Index of current BPF program insn   */\n+\tu32 jit_index;                /* Index of current JIT target insn    */\n+\tu32 changes;                  /* Number of PC-relative branch conv   */\n+\tu32 accessed;                 /* Bit mask of read eBPF registers     */\n+\tu32 clobbered;                /* Bit mask of modified CPU registers  */\n+\tu32 stack_size;               /* Total allocated stack size in bytes */\n+\tu32 saved_size;               /* Size of callee-saved registers      */\n+\tu32 stack_used;               /* Stack size used for function calls  */\n+};\n+\n+/* Emit the instruction if the JIT memory space has been allocated */\n+#define emit(ctx, func, ...)\t\t\t\t\t\\\n+do {\t\t\t\t\t\t\t\t\\\n+\tif ((ctx)->target != NULL) {\t\t\t\t\\\n+\t\tu32 *p = &(ctx)->target[ctx->jit_index];\t\\\n+\t\tuasm_i_##func(&p, ##__VA_ARGS__);\t\t\\\n+\t}\t\t\t\t\t\t\t\\\n+\t(ctx)->jit_index++;\t\t\t\t\t\\\n+} while (0)\n+\n+/*\n+ * Mark a BPF register as accessed, it needs to be\n+ * initialized by the program if expected, e.g. FP.\n+ */\n+static inline void access_reg(struct jit_context *ctx, u8 reg)\n+{\n+\tctx->accessed |= BIT(reg);\n+}\n+\n+/*\n+ * Mark a CPU register as clobbered, it needs to be\n+ * saved/restored by the program if callee-saved.\n+ */\n+static inline void clobber_reg(struct jit_context *ctx, u8 reg)\n+{\n+\tctx->clobbered |= BIT(reg);\n+}\n+\n+/*\n+ * Push registers on the stack, starting at a given depth from the stack\n+ * pointer and increasing. The next depth to be written is returned.\n+ */\n+int push_regs(struct jit_context *ctx, u32 mask, u32 excl, int depth);\n+\n+/*\n+ * Pop registers from the stack, starting at a given depth from the stack\n+ * pointer and increasing. The next depth to be read is returned.\n+ */\n+int pop_regs(struct jit_context *ctx, u32 mask, u32 excl, int depth);\n+\n+/* Compute the 28-bit jump target address from a BPF program location */\n+int get_target(struct jit_context *ctx, u32 loc);\n+\n+/* Compute the PC-relative offset to relative BPF program offset */\n+int get_offset(const struct jit_context *ctx, int off);\n+\n+/* dst = imm (32-bit) */\n+void emit_mov_i(struct jit_context *ctx, u8 dst, s32 imm);\n+\n+/* dst = src (32-bit) */\n+void emit_mov_r(struct jit_context *ctx, u8 dst, u8 src);\n+\n+/* Validate ALU/ALU64 immediate range */\n+bool valid_alu_i(u8 op, s32 imm);\n+\n+/* Rewrite ALU/ALU64 immediate operation */\n+bool rewrite_alu_i(u8 op, s32 imm, u8 *alu, s32 *val);\n+\n+/* ALU immediate operation (32-bit) */\n+void emit_alu_i(struct jit_context *ctx, u8 dst, s32 imm, u8 op);\n+\n+/* ALU register operation (32-bit) */\n+void emit_alu_r(struct jit_context *ctx, u8 dst, u8 src, u8 op);\n+\n+/* Atomic read-modify-write (32-bit) */\n+void emit_atomic_r(struct jit_context *ctx, u8 dst, u8 src, s16 off, u8 code);\n+\n+/* Atomic compare-and-exchange (32-bit) */\n+void emit_cmpxchg_r(struct jit_context *ctx, u8 dst, u8 src, u8 res, s16 off);\n+\n+/* Swap bytes and truncate a register word or half word */\n+void emit_bswap_r(struct jit_context *ctx, u8 dst, u32 width);\n+\n+/* Validate JMP/JMP32 immediate range */\n+bool valid_jmp_i(u8 op, s32 imm);\n+\n+/* Prepare a PC-relative jump operation with immediate conditional */\n+void setup_jmp_i(struct jit_context *ctx, s32 imm, u8 width,\n+\t\t u8 bpf_op, s16 bpf_off, u8 *jit_op, s32 *jit_off);\n+\n+/* Prepare a PC-relative jump operation with register conditional */\n+void setup_jmp_r(struct jit_context *ctx, bool same_reg,\n+\t\t u8 bpf_op, s16 bpf_off, u8 *jit_op, s32 *jit_off);\n+\n+/* Finish a PC-relative jump operation */\n+int finish_jmp(struct jit_context *ctx, u8 jit_op, s16 bpf_off);\n+\n+/* Conditional JMP/JMP32 immediate */\n+void emit_jmp_i(struct jit_context *ctx, u8 dst, s32 imm, s32 off, u8 op);\n+\n+/* Conditional JMP/JMP32 register */\n+void emit_jmp_r(struct jit_context *ctx, u8 dst, u8 src, s32 off, u8 op);\n+\n+/* Jump always */\n+int emit_ja(struct jit_context *ctx, s16 off);\n+\n+/* Jump to epilogue */\n+int emit_exit(struct jit_context *ctx);\n+\n+/*\n+ * Build program prologue to set up the stack and registers.\n+ * This function is implemented separately for 32-bit and 64-bit JITs.\n+ */\n+void build_prologue(struct jit_context *ctx);\n+\n+/*\n+ * Build the program epilogue to restore the stack and registers.\n+ * This function is implemented separately for 32-bit and 64-bit JITs.\n+ */\n+void build_epilogue(struct jit_context *ctx, int dest_reg);\n+\n+/*\n+ * Convert an eBPF instruction to native instruction, i.e\n+ * JITs an eBPF instruction.\n+ * Returns :\n+ *\t0  - Successfully JITed an 8-byte eBPF instruction\n+ *\t>0 - Successfully JITed a 16-byte eBPF instruction\n+ *\t<0 - Failed to JIT.\n+ * This function is implemented separately for 32-bit and 64-bit JITs.\n+ */\n+int build_insn(const struct bpf_insn *insn, struct jit_context *ctx);\n+\n+#endif /* _BPF_JIT_COMP_H */\n--- /dev/null\n+++ b/arch/mips/net/bpf_jit_comp32.c\n@@ -0,0 +1,1741 @@\n+// SPDX-License-Identifier: GPL-2.0-only\n+/*\n+ * Just-In-Time compiler for eBPF bytecode on MIPS.\n+ * Implementation of JIT functions for 32-bit CPUs.\n+ *\n+ * Copyright (c) 2021 Anyfi Networks AB.\n+ * Author: Johan Almbladh <johan.almbladh@gmail.com>\n+ *\n+ * Based on code and ideas from\n+ * Copyright (c) 2017 Cavium, Inc.\n+ * Copyright (c) 2017 Shubham Bansal <illusionist.neo@gmail.com>\n+ * Copyright (c) 2011 Mircea Gherzan <mgherzan@gmail.com>\n+ */\n+\n+#include <linux/math64.h>\n+#include <linux/errno.h>\n+#include <linux/filter.h>\n+#include <linux/bpf.h>\n+#include <asm/cpu-features.h>\n+#include <asm/isa-rev.h>\n+#include <asm/uasm.h>\n+\n+#include \"bpf_jit_comp.h\"\n+\n+/* MIPS a4-a7 are not available in the o32 ABI */\n+#undef MIPS_R_A4\n+#undef MIPS_R_A5\n+#undef MIPS_R_A6\n+#undef MIPS_R_A7\n+\n+/* Stack is 8-byte aligned in o32 ABI */\n+#define MIPS_STACK_ALIGNMENT 8\n+\n+/*\n+ * The top 16 bytes of a stack frame is reserved for the callee in O32 ABI.\n+ * This corresponds to stack space for register arguments a0-a3.\n+ */\n+#define JIT_RESERVED_STACK 16\n+\n+/* Temporary 64-bit register used by JIT */\n+#define JIT_REG_TMP MAX_BPF_JIT_REG\n+\n+/*\n+ * Number of prologue bytes to skip when doing a tail call.\n+ * Tail call count (TCC) initialization (8 bytes) always, plus\n+ * R0-to-v0 assignment (4 bytes) if big endian.\n+ */\n+#ifdef __BIG_ENDIAN\n+#define JIT_TCALL_SKIP 12\n+#else\n+#define JIT_TCALL_SKIP 8\n+#endif\n+\n+/* CPU registers holding the callee return value */\n+#define JIT_RETURN_REGS\t  \\\n+\t(BIT(MIPS_R_V0) | \\\n+\t BIT(MIPS_R_V1))\n+\n+/* CPU registers arguments passed to callee directly */\n+#define JIT_ARG_REGS      \\\n+\t(BIT(MIPS_R_A0) | \\\n+\t BIT(MIPS_R_A1) | \\\n+\t BIT(MIPS_R_A2) | \\\n+\t BIT(MIPS_R_A3))\n+\n+/* CPU register arguments passed to callee on stack */\n+#define JIT_STACK_REGS    \\\n+\t(BIT(MIPS_R_T0) | \\\n+\t BIT(MIPS_R_T1) | \\\n+\t BIT(MIPS_R_T2) | \\\n+\t BIT(MIPS_R_T3) | \\\n+\t BIT(MIPS_R_T4) | \\\n+\t BIT(MIPS_R_T5))\n+\n+/* Caller-saved CPU registers */\n+#define JIT_CALLER_REGS    \\\n+\t(JIT_RETURN_REGS | \\\n+\t JIT_ARG_REGS    | \\\n+\t JIT_STACK_REGS)\n+\n+/* Callee-saved CPU registers */\n+#define JIT_CALLEE_REGS   \\\n+\t(BIT(MIPS_R_S0) | \\\n+\t BIT(MIPS_R_S1) | \\\n+\t BIT(MIPS_R_S2) | \\\n+\t BIT(MIPS_R_S3) | \\\n+\t BIT(MIPS_R_S4) | \\\n+\t BIT(MIPS_R_S5) | \\\n+\t BIT(MIPS_R_S6) | \\\n+\t BIT(MIPS_R_S7) | \\\n+\t BIT(MIPS_R_GP) | \\\n+\t BIT(MIPS_R_FP) | \\\n+\t BIT(MIPS_R_RA))\n+\n+/*\n+ * Mapping of 64-bit eBPF registers to 32-bit native MIPS registers.\n+ *\n+ * 1) Native register pairs are ordered according to CPU endiannes, following\n+ *    the MIPS convention for passing 64-bit arguments and return values.\n+ * 2) The eBPF return value, arguments and callee-saved registers are mapped\n+ *    to their native MIPS equivalents.\n+ * 3) Since the 32 highest bits in the eBPF FP register are always zero,\n+ *    only one general-purpose register is actually needed for the mapping.\n+ *    We use the fp register for this purpose, and map the highest bits to\n+ *    the MIPS register r0 (zero).\n+ * 4) We use the MIPS gp and at registers as internal temporary registers\n+ *    for constant blinding. The gp register is callee-saved.\n+ * 5) One 64-bit temporary register is mapped for use when sign-extending\n+ *    immediate operands. MIPS registers t6-t9 are available to the JIT\n+ *    for as temporaries when implementing complex 64-bit operations.\n+ *\n+ * With this scheme all eBPF registers are being mapped to native MIPS\n+ * registers without having to use any stack scratch space. The direct\n+ * register mapping (2) simplifies the handling of function calls.\n+ */\n+static const u8 bpf2mips32[][2] = {\n+\t/* Return value from in-kernel function, and exit value from eBPF */\n+\t[BPF_REG_0] = {MIPS_R_V1, MIPS_R_V0},\n+\t/* Arguments from eBPF program to in-kernel function */\n+\t[BPF_REG_1] = {MIPS_R_A1, MIPS_R_A0},\n+\t[BPF_REG_2] = {MIPS_R_A3, MIPS_R_A2},\n+\t/* Remaining arguments, to be passed on the stack per O32 ABI */\n+\t[BPF_REG_3] = {MIPS_R_T1, MIPS_R_T0},\n+\t[BPF_REG_4] = {MIPS_R_T3, MIPS_R_T2},\n+\t[BPF_REG_5] = {MIPS_R_T5, MIPS_R_T4},\n+\t/* Callee-saved registers that in-kernel function will preserve */\n+\t[BPF_REG_6] = {MIPS_R_S1, MIPS_R_S0},\n+\t[BPF_REG_7] = {MIPS_R_S3, MIPS_R_S2},\n+\t[BPF_REG_8] = {MIPS_R_S5, MIPS_R_S4},\n+\t[BPF_REG_9] = {MIPS_R_S7, MIPS_R_S6},\n+\t/* Read-only frame pointer to access the eBPF stack */\n+#ifdef __BIG_ENDIAN\n+\t[BPF_REG_FP] = {MIPS_R_FP, MIPS_R_ZERO},\n+#else\n+\t[BPF_REG_FP] = {MIPS_R_ZERO, MIPS_R_FP},\n+#endif\n+\t/* Temporary register for blinding constants */\n+\t[BPF_REG_AX] = {MIPS_R_GP, MIPS_R_AT},\n+\t/* Temporary register for internal JIT use */\n+\t[JIT_REG_TMP] = {MIPS_R_T7, MIPS_R_T6},\n+};\n+\n+/* Get low CPU register for a 64-bit eBPF register mapping */\n+static inline u8 lo(const u8 reg[])\n+{\n+#ifdef __BIG_ENDIAN\n+\treturn reg[0];\n+#else\n+\treturn reg[1];\n+#endif\n+}\n+\n+/* Get high CPU register for a 64-bit eBPF register mapping */\n+static inline u8 hi(const u8 reg[])\n+{\n+#ifdef __BIG_ENDIAN\n+\treturn reg[1];\n+#else\n+\treturn reg[0];\n+#endif\n+}\n+\n+/*\n+ * Mark a 64-bit CPU register pair as clobbered, it needs to be\n+ * saved/restored by the program if callee-saved.\n+ */\n+static void clobber_reg64(struct jit_context *ctx, const u8 reg[])\n+{\n+\tclobber_reg(ctx, reg[0]);\n+\tclobber_reg(ctx, reg[1]);\n+}\n+\n+/* dst = imm (sign-extended) */\n+static void emit_mov_se_i64(struct jit_context *ctx, const u8 dst[], s32 imm)\n+{\n+\temit_mov_i(ctx, lo(dst), imm);\n+\tif (imm < 0)\n+\t\temit(ctx, addiu, hi(dst), MIPS_R_ZERO, -1);\n+\telse\n+\t\temit(ctx, move, hi(dst), MIPS_R_ZERO);\n+\tclobber_reg64(ctx, dst);\n+}\n+\n+/* Zero extension, if verifier does not do it for us  */\n+static void emit_zext_ver(struct jit_context *ctx, const u8 dst[])\n+{\n+\tif (!ctx->program->aux->verifier_zext) {\n+\t\temit(ctx, move, hi(dst), MIPS_R_ZERO);\n+\t\tclobber_reg(ctx, hi(dst));\n+\t}\n+}\n+\n+/* Load delay slot, if ISA mandates it */\n+static void emit_load_delay(struct jit_context *ctx)\n+{\n+\tif (!cpu_has_mips_2_3_4_5_r)\n+\t\temit(ctx, nop);\n+}\n+\n+/* ALU immediate operation (64-bit) */\n+static void emit_alu_i64(struct jit_context *ctx,\n+\t\t\t const u8 dst[], s32 imm, u8 op)\n+{\n+\tu8 src = MIPS_R_T6;\n+\n+\t/*\n+\t * ADD/SUB with all but the max negative imm can be handled by\n+\t * inverting the operation and the imm value, saving one insn.\n+\t */\n+\tif (imm > S32_MIN && imm < 0)\n+\t\tswitch (op) {\n+\t\tcase BPF_ADD:\n+\t\t\top = BPF_SUB;\n+\t\t\timm = -imm;\n+\t\t\tbreak;\n+\t\tcase BPF_SUB:\n+\t\t\top = BPF_ADD;\n+\t\t\timm = -imm;\n+\t\t\tbreak;\n+\t\t}\n+\n+\t/* Move immediate to temporary register */\n+\temit_mov_i(ctx, src, imm);\n+\n+\tswitch (op) {\n+\t/* dst = dst + imm */\n+\tcase BPF_ADD:\n+\t\temit(ctx, addu, lo(dst), lo(dst), src);\n+\t\temit(ctx, sltu, MIPS_R_T9, lo(dst), src);\n+\t\temit(ctx, addu, hi(dst), hi(dst), MIPS_R_T9);\n+\t\tif (imm < 0)\n+\t\t\temit(ctx, addiu, hi(dst), hi(dst), -1);\n+\t\tbreak;\n+\t/* dst = dst - imm */\n+\tcase BPF_SUB:\n+\t\temit(ctx, sltu, MIPS_R_T9, lo(dst), src);\n+\t\temit(ctx, subu, lo(dst), lo(dst), src);\n+\t\temit(ctx, subu, hi(dst), hi(dst), MIPS_R_T9);\n+\t\tif (imm < 0)\n+\t\t\temit(ctx, addiu, hi(dst), hi(dst), 1);\n+\t\tbreak;\n+\t/* dst = dst | imm */\n+\tcase BPF_OR:\n+\t\temit(ctx, or, lo(dst), lo(dst), src);\n+\t\tif (imm < 0)\n+\t\t\temit(ctx, addiu, hi(dst), MIPS_R_ZERO, -1);\n+\t\tbreak;\n+\t/* dst = dst & imm */\n+\tcase BPF_AND:\n+\t\temit(ctx, and, lo(dst), lo(dst), src);\n+\t\tif (imm >= 0)\n+\t\t\temit(ctx, move, hi(dst), MIPS_R_ZERO);\n+\t\tbreak;\n+\t/* dst = dst ^ imm */\n+\tcase BPF_XOR:\n+\t\temit(ctx, xor, lo(dst), lo(dst), src);\n+\t\tif (imm < 0) {\n+\t\t\temit(ctx, subu, hi(dst), MIPS_R_ZERO, hi(dst));\n+\t\t\temit(ctx, addiu, hi(dst), hi(dst), -1);\n+\t\t}\n+\t\tbreak;\n+\t}\n+\tclobber_reg64(ctx, dst);\n+}\n+\n+/* ALU register operation (64-bit) */\n+static void emit_alu_r64(struct jit_context *ctx,\n+\t\t\t const u8 dst[], const u8 src[], u8 op)\n+{\n+\tswitch (BPF_OP(op)) {\n+\t/* dst = dst + src */\n+\tcase BPF_ADD:\n+\t\tif (src == dst) {\n+\t\t\temit(ctx, srl, MIPS_R_T9, lo(dst), 31);\n+\t\t\temit(ctx, addu, lo(dst), lo(dst), lo(dst));\n+\t\t} else {\n+\t\t\temit(ctx, addu, lo(dst), lo(dst), lo(src));\n+\t\t\temit(ctx, sltu, MIPS_R_T9, lo(dst), lo(src));\n+\t\t}\n+\t\temit(ctx, addu, hi(dst), hi(dst), hi(src));\n+\t\temit(ctx, addu, hi(dst), hi(dst), MIPS_R_T9);\n+\t\tbreak;\n+\t/* dst = dst - src */\n+\tcase BPF_SUB:\n+\t\temit(ctx, sltu, MIPS_R_T9, lo(dst), lo(src));\n+\t\temit(ctx, subu, lo(dst), lo(dst), lo(src));\n+\t\temit(ctx, subu, hi(dst), hi(dst), hi(src));\n+\t\temit(ctx, subu, hi(dst), hi(dst), MIPS_R_T9);\n+\t\tbreak;\n+\t/* dst = dst | src */\n+\tcase BPF_OR:\n+\t\temit(ctx, or, lo(dst), lo(dst), lo(src));\n+\t\temit(ctx, or, hi(dst), hi(dst), hi(src));\n+\t\tbreak;\n+\t/* dst = dst & src */\n+\tcase BPF_AND:\n+\t\temit(ctx, and, lo(dst), lo(dst), lo(src));\n+\t\temit(ctx, and, hi(dst), hi(dst), hi(src));\n+\t\tbreak;\n+\t/* dst = dst ^ src */\n+\tcase BPF_XOR:\n+\t\temit(ctx, xor, lo(dst), lo(dst), lo(src));\n+\t\temit(ctx, xor, hi(dst), hi(dst), hi(src));\n+\t\tbreak;\n+\t}\n+\tclobber_reg64(ctx, dst);\n+}\n+\n+/* ALU invert (64-bit) */\n+static void emit_neg_i64(struct jit_context *ctx, const u8 dst[])\n+{\n+\temit(ctx, sltu, MIPS_R_T9, MIPS_R_ZERO, lo(dst));\n+\temit(ctx, subu, lo(dst), MIPS_R_ZERO, lo(dst));\n+\temit(ctx, subu, hi(dst), MIPS_R_ZERO, hi(dst));\n+\temit(ctx, subu, hi(dst), hi(dst), MIPS_R_T9);\n+\n+\tclobber_reg64(ctx, dst);\n+}\n+\n+/* ALU shift immediate (64-bit) */\n+static void emit_shift_i64(struct jit_context *ctx,\n+\t\t\t   const u8 dst[], u32 imm, u8 op)\n+{\n+\tswitch (BPF_OP(op)) {\n+\t/* dst = dst << imm */\n+\tcase BPF_LSH:\n+\t\tif (imm < 32) {\n+\t\t\temit(ctx, srl, MIPS_R_T9, lo(dst), 32 - imm);\n+\t\t\temit(ctx, sll, lo(dst), lo(dst), imm);\n+\t\t\temit(ctx, sll, hi(dst), hi(dst), imm);\n+\t\t\temit(ctx, or, hi(dst), hi(dst), MIPS_R_T9);\n+\t\t} else {\n+\t\t\temit(ctx, sll, hi(dst), lo(dst), imm - 32);\n+\t\t\temit(ctx, move, lo(dst), MIPS_R_ZERO);\n+\t\t}\n+\t\tbreak;\n+\t/* dst = dst >> imm */\n+\tcase BPF_RSH:\n+\t\tif (imm < 32) {\n+\t\t\temit(ctx, sll, MIPS_R_T9, hi(dst), 32 - imm);\n+\t\t\temit(ctx, srl, lo(dst), lo(dst), imm);\n+\t\t\temit(ctx, srl, hi(dst), hi(dst), imm);\n+\t\t\temit(ctx, or, lo(dst), lo(dst), MIPS_R_T9);\n+\t\t} else {\n+\t\t\temit(ctx, srl, lo(dst), hi(dst), imm - 32);\n+\t\t\temit(ctx, move, hi(dst), MIPS_R_ZERO);\n+\t\t}\n+\t\tbreak;\n+\t/* dst = dst >> imm (arithmetic) */\n+\tcase BPF_ARSH:\n+\t\tif (imm < 32) {\n+\t\t\temit(ctx, sll, MIPS_R_T9, hi(dst), 32 - imm);\n+\t\t\temit(ctx, srl, lo(dst), lo(dst), imm);\n+\t\t\temit(ctx, sra, hi(dst), hi(dst), imm);\n+\t\t\temit(ctx, or, lo(dst), lo(dst), MIPS_R_T9);\n+\t\t} else {\n+\t\t\temit(ctx, sra, lo(dst), hi(dst), imm - 32);\n+\t\t\temit(ctx, sra, hi(dst), hi(dst), 31);\n+\t\t}\n+\t\tbreak;\n+\t}\n+\tclobber_reg64(ctx, dst);\n+}\n+\n+/* ALU shift register (64-bit) */\n+static void emit_shift_r64(struct jit_context *ctx,\n+\t\t\t   const u8 dst[], u8 src, u8 op)\n+{\n+\tu8 t1 = MIPS_R_T8;\n+\tu8 t2 = MIPS_R_T9;\n+\n+\temit(ctx, andi, t1, src, 32);              /* t1 = src & 32          */\n+\temit(ctx, beqz, t1, 16);                   /* PC += 16 if t1 == 0    */\n+\temit(ctx, nor, t2, src, MIPS_R_ZERO);      /* t2 = ~src (delay slot) */\n+\n+\tswitch (BPF_OP(op)) {\n+\t/* dst = dst << src */\n+\tcase BPF_LSH:\n+\t\t/* Next: shift >= 32 */\n+\t\temit(ctx, sllv, hi(dst), lo(dst), src);    /* dh = dl << src */\n+\t\temit(ctx, move, lo(dst), MIPS_R_ZERO);     /* dl = 0         */\n+\t\temit(ctx, b, 20);                          /* PC += 20       */\n+\t\t/* +16: shift < 32 */\n+\t\temit(ctx, srl, t1, lo(dst), 1);            /* t1 = dl >> 1   */\n+\t\temit(ctx, srlv, t1, t1, t2);               /* t1 = t1 >> t2  */\n+\t\temit(ctx, sllv, lo(dst), lo(dst), src);    /* dl = dl << src */\n+\t\temit(ctx, sllv, hi(dst), hi(dst), src);    /* dh = dh << src */\n+\t\temit(ctx, or, hi(dst), hi(dst), t1);       /* dh = dh | t1   */\n+\t\tbreak;\n+\t/* dst = dst >> src */\n+\tcase BPF_RSH:\n+\t\t/* Next: shift >= 32 */\n+\t\temit(ctx, srlv, lo(dst), hi(dst), src);    /* dl = dh >> src */\n+\t\temit(ctx, move, hi(dst), MIPS_R_ZERO);     /* dh = 0         */\n+\t\temit(ctx, b, 20);                          /* PC += 20       */\n+\t\t/* +16: shift < 32 */\n+\t\temit(ctx, sll, t1, hi(dst), 1);            /* t1 = dl << 1   */\n+\t\temit(ctx, sllv, t1, t1, t2);               /* t1 = t1 << t2  */\n+\t\temit(ctx, srlv, lo(dst), lo(dst), src);    /* dl = dl >> src */\n+\t\temit(ctx, srlv, hi(dst), hi(dst), src);    /* dh = dh >> src */\n+\t\temit(ctx, or, lo(dst), lo(dst), t1);       /* dl = dl | t1   */\n+\t\tbreak;\n+\t/* dst = dst >> src (arithmetic) */\n+\tcase BPF_ARSH:\n+\t\t/* Next: shift >= 32 */\n+\t\temit(ctx, srav, lo(dst), hi(dst), src);   /* dl = dh >>a src */\n+\t\temit(ctx, sra, hi(dst), hi(dst), 31);     /* dh = dh >>a 31  */\n+\t\temit(ctx, b, 20);                         /* PC += 20        */\n+\t\t/* +16: shift < 32 */\n+\t\temit(ctx, sll, t1, hi(dst), 1);           /* t1 = dl << 1    */\n+\t\temit(ctx, sllv, t1, t1, t2);              /* t1 = t1 << t2   */\n+\t\temit(ctx, srlv, lo(dst), lo(dst), src);   /* dl = dl >>a src */\n+\t\temit(ctx, srav, hi(dst), hi(dst), src);   /* dh = dh >> src  */\n+\t\temit(ctx, or, lo(dst), lo(dst), t1);      /* dl = dl | t1    */\n+\t\tbreak;\n+\t}\n+\n+\t/* +20: Done */\n+\tclobber_reg64(ctx, dst);\n+}\n+\n+/* ALU mul immediate (64x32-bit) */\n+static void emit_mul_i64(struct jit_context *ctx, const u8 dst[], s32 imm)\n+{\n+\tu8 src = MIPS_R_T6;\n+\tu8 tmp = MIPS_R_T9;\n+\n+\tswitch (imm) {\n+\t/* dst = dst * 1 is a no-op */\n+\tcase 1:\n+\t\tbreak;\n+\t/* dst = dst * -1 */\n+\tcase -1:\n+\t\temit_neg_i64(ctx, dst);\n+\t\tbreak;\n+\tcase 0:\n+\t\temit_mov_r(ctx, lo(dst), MIPS_R_ZERO);\n+\t\temit_mov_r(ctx, hi(dst), MIPS_R_ZERO);\n+\t\tbreak;\n+\t/* Full 64x32 multiply */\n+\tdefault:\n+\t\t/* hi(dst) = hi(dst) * src(imm) */\n+\t\temit_mov_i(ctx, src, imm);\n+\t\tif (cpu_has_mips32r1 || cpu_has_mips32r6) {\n+\t\t\temit(ctx, mul, hi(dst), hi(dst), src);\n+\t\t} else {\n+\t\t\temit(ctx, multu, hi(dst), src);\n+\t\t\temit(ctx, mflo, hi(dst));\n+\t\t}\n+\n+\t\t/* hi(dst) = hi(dst) - lo(dst) */\n+\t\tif (imm < 0)\n+\t\t\temit(ctx, subu, hi(dst), hi(dst), lo(dst));\n+\n+\t\t/* tmp = lo(dst) * src(imm) >> 32 */\n+\t\t/* lo(dst) = lo(dst) * src(imm) */\n+\t\tif (cpu_has_mips32r6) {\n+\t\t\temit(ctx, muhu, tmp, lo(dst), src);\n+\t\t\temit(ctx, mulu, lo(dst), lo(dst), src);\n+\t\t} else {\n+\t\t\temit(ctx, multu, lo(dst), src);\n+\t\t\temit(ctx, mflo, lo(dst));\n+\t\t\temit(ctx, mfhi, tmp);\n+\t\t}\n+\n+\t\t/* hi(dst) += tmp */\n+\t\temit(ctx, addu, hi(dst), hi(dst), tmp);\n+\t\tclobber_reg64(ctx, dst);\n+\t\tbreak;\n+\t}\n+}\n+\n+/* ALU mul register (64x64-bit) */\n+static void emit_mul_r64(struct jit_context *ctx,\n+\t\t\t const u8 dst[], const u8 src[])\n+{\n+\tu8 acc = MIPS_R_T8;\n+\tu8 tmp = MIPS_R_T9;\n+\n+\t/* acc = hi(dst) * lo(src) */\n+\tif (cpu_has_mips32r1 || cpu_has_mips32r6) {\n+\t\temit(ctx, mul, acc, hi(dst), lo(src));\n+\t} else {\n+\t\temit(ctx, multu, hi(dst), lo(src));\n+\t\temit(ctx, mflo, acc);\n+\t}\n+\n+\t/* tmp = lo(dst) * hi(src) */\n+\tif (cpu_has_mips32r1 || cpu_has_mips32r6) {\n+\t\temit(ctx, mul, tmp, lo(dst), hi(src));\n+\t} else {\n+\t\temit(ctx, multu, lo(dst), hi(src));\n+\t\temit(ctx, mflo, tmp);\n+\t}\n+\n+\t/* acc += tmp */\n+\temit(ctx, addu, acc, acc, tmp);\n+\n+\t/* tmp = lo(dst) * lo(src) >> 32 */\n+\t/* lo(dst) = lo(dst) * lo(src) */\n+\tif (cpu_has_mips32r6) {\n+\t\temit(ctx, muhu, tmp, lo(dst), lo(src));\n+\t\temit(ctx, mulu, lo(dst), lo(dst), lo(src));\n+\t} else {\n+\t\temit(ctx, multu, lo(dst), lo(src));\n+\t\temit(ctx, mflo, lo(dst));\n+\t\temit(ctx, mfhi, tmp);\n+\t}\n+\n+\t/* hi(dst) = acc + tmp */\n+\temit(ctx, addu, hi(dst), acc, tmp);\n+\tclobber_reg64(ctx, dst);\n+}\n+\n+/* Helper function for 64-bit modulo */\n+static u64 jit_mod64(u64 a, u64 b)\n+{\n+\tu64 rem;\n+\n+\tdiv64_u64_rem(a, b, &rem);\n+\treturn rem;\n+}\n+\n+/* ALU div/mod register (64-bit) */\n+static void emit_divmod_r64(struct jit_context *ctx,\n+\t\t\t    const u8 dst[], const u8 src[], u8 op)\n+{\n+\tconst u8 *r0 = bpf2mips32[BPF_REG_0]; /* Mapped to v0-v1 */\n+\tconst u8 *r1 = bpf2mips32[BPF_REG_1]; /* Mapped to a0-a1 */\n+\tconst u8 *r2 = bpf2mips32[BPF_REG_2]; /* Mapped to a2-a3 */\n+\tint exclude, k;\n+\tu32 addr = 0;\n+\n+\t/* Push caller-saved registers on stack */\n+\tpush_regs(ctx, ctx->clobbered & JIT_CALLER_REGS,\n+\t\t  0, JIT_RESERVED_STACK);\n+\n+\t/* Put 64-bit arguments 1 and 2 in registers a0-a3 */\n+\tfor (k = 0; k < 2; k++) {\n+\t\temit(ctx, move, MIPS_R_T9, src[k]);\n+\t\temit(ctx, move, r1[k], dst[k]);\n+\t\temit(ctx, move, r2[k], MIPS_R_T9);\n+\t}\n+\n+\t/* Emit function call */\n+\tswitch (BPF_OP(op)) {\n+\t/* dst = dst / src */\n+\tcase BPF_DIV:\n+\t\taddr = (u32)&div64_u64;\n+\t\tbreak;\n+\t/* dst = dst % src */\n+\tcase BPF_MOD:\n+\t\taddr = (u32)&jit_mod64;\n+\t\tbreak;\n+\t}\n+\temit_mov_i(ctx, MIPS_R_T9, addr);\n+\temit(ctx, jalr, MIPS_R_RA, MIPS_R_T9);\n+\temit(ctx, nop); /* Delay slot */\n+\n+\t/* Store the 64-bit result in dst */\n+\temit(ctx, move, dst[0], r0[0]);\n+\temit(ctx, move, dst[1], r0[1]);\n+\n+\t/* Restore caller-saved registers, excluding the computed result */\n+\texclude = BIT(lo(dst)) | BIT(hi(dst));\n+\tpop_regs(ctx, ctx->clobbered & JIT_CALLER_REGS,\n+\t\t exclude, JIT_RESERVED_STACK);\n+\temit_load_delay(ctx);\n+\n+\tclobber_reg64(ctx, dst);\n+\tclobber_reg(ctx, MIPS_R_V0);\n+\tclobber_reg(ctx, MIPS_R_V1);\n+\tclobber_reg(ctx, MIPS_R_RA);\n+}\n+\n+/* Swap bytes in a register word */\n+static void emit_swap8_r(struct jit_context *ctx, u8 dst, u8 src, u8 mask)\n+{\n+\tu8 tmp = MIPS_R_T9;\n+\n+\temit(ctx, and, tmp, src, mask); /* tmp = src & 0x00ff00ff */\n+\temit(ctx, sll, tmp, tmp, 8);    /* tmp = tmp << 8         */\n+\temit(ctx, srl, dst, src, 8);    /* dst = src >> 8         */\n+\temit(ctx, and, dst, dst, mask); /* dst = dst & 0x00ff00ff */\n+\temit(ctx, or,  dst, dst, tmp);  /* dst = dst | tmp        */\n+}\n+\n+/* Swap half words in a register word */\n+static void emit_swap16_r(struct jit_context *ctx, u8 dst, u8 src)\n+{\n+\tu8 tmp = MIPS_R_T9;\n+\n+\temit(ctx, sll, tmp, src, 16);  /* tmp = src << 16 */\n+\temit(ctx, srl, dst, src, 16);  /* dst = src >> 16 */\n+\temit(ctx, or,  dst, dst, tmp); /* dst = dst | tmp */\n+}\n+\n+/* Swap bytes and truncate a register double word, word or half word */\n+static void emit_bswap_r64(struct jit_context *ctx, const u8 dst[], u32 width)\n+{\n+\tu8 tmp = MIPS_R_T8;\n+\n+\tswitch (width) {\n+\t/* Swap bytes in a double word */\n+\tcase 64:\n+\t\tif (cpu_has_mips32r2 || cpu_has_mips32r6) {\n+\t\t\temit(ctx, rotr, tmp, hi(dst), 16);\n+\t\t\temit(ctx, rotr, hi(dst), lo(dst), 16);\n+\t\t\temit(ctx, wsbh, lo(dst), tmp);\n+\t\t\temit(ctx, wsbh, hi(dst), hi(dst));\n+\t\t} else {\n+\t\t\temit_swap16_r(ctx, tmp, lo(dst));\n+\t\t\temit_swap16_r(ctx, lo(dst), hi(dst));\n+\t\t\temit(ctx, move, hi(dst), tmp);\n+\n+\t\t\temit(ctx, lui, tmp, 0xff);      /* tmp = 0x00ff0000 */\n+\t\t\temit(ctx, ori, tmp, tmp, 0xff); /* tmp = 0x00ff00ff */\n+\t\t\temit_swap8_r(ctx, lo(dst), lo(dst), tmp);\n+\t\t\temit_swap8_r(ctx, hi(dst), hi(dst), tmp);\n+\t\t}\n+\t\tbreak;\n+\t/* Swap bytes in a word */\n+\t/* Swap bytes in a half word */\n+\tcase 32:\n+\tcase 16:\n+\t\temit_bswap_r(ctx, lo(dst), width);\n+\t\temit(ctx, move, hi(dst), MIPS_R_ZERO);\n+\t\tbreak;\n+\t}\n+\tclobber_reg64(ctx, dst);\n+}\n+\n+/* Truncate a register double word, word or half word */\n+static void emit_trunc_r64(struct jit_context *ctx, const u8 dst[], u32 width)\n+{\n+\tswitch (width) {\n+\tcase 64:\n+\t\tbreak;\n+\t/* Zero-extend a word */\n+\tcase 32:\n+\t\temit(ctx, move, hi(dst), MIPS_R_ZERO);\n+\t\tclobber_reg(ctx, hi(dst));\n+\t\tbreak;\n+\t/* Zero-extend a half word */\n+\tcase 16:\n+\t\temit(ctx, move, hi(dst), MIPS_R_ZERO);\n+\t\temit(ctx, andi, lo(dst), lo(dst), 0xffff);\n+\t\tclobber_reg64(ctx, dst);\n+\t\tbreak;\n+\t}\n+}\n+\n+/* Load operation: dst = *(size*)(src + off) */\n+static void emit_ldx(struct jit_context *ctx,\n+\t\t     const u8 dst[], u8 src, s16 off, u8 size)\n+{\n+\tswitch (size) {\n+\t/* Load a byte */\n+\tcase BPF_B:\n+\t\temit(ctx, lbu, lo(dst), off, src);\n+\t\temit(ctx, move, hi(dst), MIPS_R_ZERO);\n+\t\tbreak;\n+\t/* Load a half word */\n+\tcase BPF_H:\n+\t\temit(ctx, lhu, lo(dst), off, src);\n+\t\temit(ctx, move, hi(dst), MIPS_R_ZERO);\n+\t\tbreak;\n+\t/* Load a word */\n+\tcase BPF_W:\n+\t\temit(ctx, lw, lo(dst), off, src);\n+\t\temit(ctx, move, hi(dst), MIPS_R_ZERO);\n+\t\tbreak;\n+\t/* Load a double word */\n+\tcase BPF_DW:\n+\t\tif (dst[1] == src) {\n+\t\t\temit(ctx, lw, dst[0], off + 4, src);\n+\t\t\temit(ctx, lw, dst[1], off, src);\n+\t\t} else {\n+\t\t\temit(ctx, lw, dst[1], off, src);\n+\t\t\temit(ctx, lw, dst[0], off + 4, src);\n+\t\t}\n+\t\temit_load_delay(ctx);\n+\t\tbreak;\n+\t}\n+\tclobber_reg64(ctx, dst);\n+}\n+\n+/* Store operation: *(size *)(dst + off) = src */\n+static void emit_stx(struct jit_context *ctx,\n+\t\t     const u8 dst, const u8 src[], s16 off, u8 size)\n+{\n+\tswitch (size) {\n+\t/* Store a byte */\n+\tcase BPF_B:\n+\t\temit(ctx, sb, lo(src), off, dst);\n+\t\tbreak;\n+\t/* Store a half word */\n+\tcase BPF_H:\n+\t\temit(ctx, sh, lo(src), off, dst);\n+\t\tbreak;\n+\t/* Store a word */\n+\tcase BPF_W:\n+\t\temit(ctx, sw, lo(src), off, dst);\n+\t\tbreak;\n+\t/* Store a double word */\n+\tcase BPF_DW:\n+\t\temit(ctx, sw, src[1], off, dst);\n+\t\temit(ctx, sw, src[0], off + 4, dst);\n+\t\tbreak;\n+\t}\n+}\n+\n+/* Atomic read-modify-write (32-bit, non-ll/sc fallback) */\n+static void emit_atomic_r32(struct jit_context *ctx,\n+\t\t\t    u8 dst, u8 src, s16 off, u8 code)\n+{\n+\tu32 exclude = 0;\n+\tu32 addr = 0;\n+\n+\t/* Push caller-saved registers on stack */\n+\tpush_regs(ctx, ctx->clobbered & JIT_CALLER_REGS,\n+\t\t  0, JIT_RESERVED_STACK);\n+\t/*\n+\t * Argument 1: dst+off if xchg, otherwise src, passed in register a0\n+\t * Argument 2: src if xchg, othersize dst+off, passed in register a1\n+\t */\n+\temit(ctx, move, MIPS_R_T9, dst);\n+\temit(ctx, move, MIPS_R_A0, src);\n+\temit(ctx, addiu, MIPS_R_A1, MIPS_R_T9, off);\n+\n+\t/* Emit function call */\n+\tswitch (code) {\n+\tcase BPF_ADD:\n+\t\taddr = (u32)&atomic_add;\n+\t\tbreak;\n+\tcase BPF_SUB:\n+\t\taddr = (u32)&atomic_sub;\n+\t\tbreak;\n+\tcase BPF_OR:\n+\t\taddr = (u32)&atomic_or;\n+\t\tbreak;\n+\tcase BPF_AND:\n+\t\taddr = (u32)&atomic_and;\n+\t\tbreak;\n+\tcase BPF_XOR:\n+\t\taddr = (u32)&atomic_xor;\n+\t\tbreak;\n+\t}\n+\temit_mov_i(ctx, MIPS_R_T9, addr);\n+\temit(ctx, jalr, MIPS_R_RA, MIPS_R_T9);\n+\temit(ctx, nop); /* Delay slot */\n+\n+\t/* Restore caller-saved registers, except any fetched value */\n+\tpop_regs(ctx, ctx->clobbered & JIT_CALLER_REGS,\n+\t\t exclude, JIT_RESERVED_STACK);\n+\temit_load_delay(ctx);\n+\tclobber_reg(ctx, MIPS_R_RA);\n+}\n+\n+/* Atomic read-modify-write (64-bit) */\n+static void emit_atomic_r64(struct jit_context *ctx,\n+\t\t\t    u8 dst, const u8 src[], s16 off, u8 code)\n+{\n+\tconst u8 *r1 = bpf2mips32[BPF_REG_1]; /* Mapped to a0-a1 */\n+\tu32 exclude = 0;\n+\tu32 addr = 0;\n+\n+\t/* Push caller-saved registers on stack */\n+\tpush_regs(ctx, ctx->clobbered & JIT_CALLER_REGS,\n+\t\t  0, JIT_RESERVED_STACK);\n+\t/*\n+\t * Argument 1: 64-bit src, passed in registers a0-a1\n+\t * Argument 2: 32-bit dst+off, passed in register a2\n+\t */\n+\temit(ctx, move, MIPS_R_T9, dst);\n+\temit(ctx, move, r1[0], src[0]);\n+\temit(ctx, move, r1[1], src[1]);\n+\temit(ctx, addiu, MIPS_R_A2, MIPS_R_T9, off);\n+\n+\t/* Emit function call */\n+\tswitch (code) {\n+\tcase BPF_ADD:\n+\t\taddr = (u32)&atomic64_add;\n+\t\tbreak;\n+\tcase BPF_SUB:\n+\t\taddr = (u32)&atomic64_sub;\n+\t\tbreak;\n+\tcase BPF_OR:\n+\t\taddr = (u32)&atomic64_or;\n+\t\tbreak;\n+\tcase BPF_AND:\n+\t\taddr = (u32)&atomic64_and;\n+\t\tbreak;\n+\tcase BPF_XOR:\n+\t\taddr = (u32)&atomic64_xor;\n+\t\tbreak;\n+\t}\n+\temit_mov_i(ctx, MIPS_R_T9, addr);\n+\temit(ctx, jalr, MIPS_R_RA, MIPS_R_T9);\n+\temit(ctx, nop); /* Delay slot */\n+\n+\t/* Restore caller-saved registers, except any fetched value */\n+\tpop_regs(ctx, ctx->clobbered & JIT_CALLER_REGS,\n+\t\t exclude, JIT_RESERVED_STACK);\n+\temit_load_delay(ctx);\n+\tclobber_reg(ctx, MIPS_R_RA);\n+}\n+\n+/*\n+ * Conditional movz or an emulated equivalent.\n+ * Note that the rs register may be modified.\n+ */\n+static void emit_movz_r(struct jit_context *ctx, u8 rd, u8 rs, u8 rt)\n+{\n+\tif (cpu_has_mips_2) {\n+\t\temit(ctx, movz, rd, rs, rt);           /* rd = rt ? rd : rs  */\n+\t} else if (cpu_has_mips32r6) {\n+\t\tif (rs != MIPS_R_ZERO)\n+\t\t\temit(ctx, seleqz, rs, rs, rt); /* rs = 0 if rt == 0  */\n+\t\temit(ctx, selnez, rd, rd, rt);         /* rd = 0 if rt != 0  */\n+\t\tif (rs != MIPS_R_ZERO)\n+\t\t\temit(ctx, or, rd, rd, rs);     /* rd = rd | rs       */\n+\t} else {\n+\t\temit(ctx, bnez, rt, 8);                /* PC += 8 if rd != 0 */\n+\t\temit(ctx, nop);                        /* +0: delay slot     */\n+\t\temit(ctx, or, rd, rs, MIPS_R_ZERO);    /* +4: rd = rs        */\n+\t}\n+\tclobber_reg(ctx, rd);\n+\tclobber_reg(ctx, rs);\n+}\n+\n+/*\n+ * Conditional movn or an emulated equivalent.\n+ * Note that the rs register may be modified.\n+ */\n+static void emit_movn_r(struct jit_context *ctx, u8 rd, u8 rs, u8 rt)\n+{\n+\tif (cpu_has_mips_2) {\n+\t\temit(ctx, movn, rd, rs, rt);           /* rd = rt ? rs : rd  */\n+\t} else if (cpu_has_mips32r6) {\n+\t\tif (rs != MIPS_R_ZERO)\n+\t\t\temit(ctx, selnez, rs, rs, rt); /* rs = 0 if rt == 0  */\n+\t\temit(ctx, seleqz, rd, rd, rt);         /* rd = 0 if rt != 0  */\n+\t\tif (rs != MIPS_R_ZERO)\n+\t\t\temit(ctx, or, rd, rd, rs);     /* rd = rd | rs       */\n+\t} else {\n+\t\temit(ctx, beqz, rt, 8);                /* PC += 8 if rd == 0 */\n+\t\temit(ctx, nop);                        /* +0: delay slot     */\n+\t\temit(ctx, or, rd, rs, MIPS_R_ZERO);    /* +4: rd = rs        */\n+\t}\n+\tclobber_reg(ctx, rd);\n+\tclobber_reg(ctx, rs);\n+}\n+\n+/* Emulation of 64-bit sltiu rd, rs, imm, where imm may be S32_MAX + 1 */\n+static void emit_sltiu_r64(struct jit_context *ctx, u8 rd,\n+\t\t\t   const u8 rs[], s64 imm)\n+{\n+\tu8 tmp = MIPS_R_T9;\n+\n+\tif (imm < 0) {\n+\t\temit_mov_i(ctx, rd, imm);                 /* rd = imm        */\n+\t\temit(ctx, sltu, rd, lo(rs), rd);          /* rd = rsl < rd   */\n+\t\temit(ctx, sltiu, tmp, hi(rs), -1);        /* tmp = rsh < ~0U */\n+\t\temit(ctx, or, rd, rd, tmp);               /* rd = rd | tmp   */\n+\t} else { /* imm >= 0 */\n+\t\tif (imm > 0x7fff) {\n+\t\t\temit_mov_i(ctx, rd, (s32)imm);     /* rd = imm       */\n+\t\t\temit(ctx, sltu, rd, lo(rs), rd);   /* rd = rsl < rd  */\n+\t\t} else {\n+\t\t\temit(ctx, sltiu, rd, lo(rs), imm); /* rd = rsl < imm */\n+\t\t}\n+\t\temit_movn_r(ctx, rd, MIPS_R_ZERO, hi(rs)); /* rd = 0 if rsh  */\n+\t}\n+}\n+\n+/* Emulation of 64-bit sltu rd, rs, rt */\n+static void emit_sltu_r64(struct jit_context *ctx, u8 rd,\n+\t\t\t  const u8 rs[], const u8 rt[])\n+{\n+\tu8 tmp = MIPS_R_T9;\n+\n+\temit(ctx, sltu, rd, lo(rs), lo(rt));           /* rd = rsl < rtl     */\n+\temit(ctx, subu, tmp, hi(rs), hi(rt));          /* tmp = rsh - rth    */\n+\temit_movn_r(ctx, rd, MIPS_R_ZERO, tmp);        /* rd = 0 if tmp != 0 */\n+\temit(ctx, sltu, tmp, hi(rs), hi(rt));          /* tmp = rsh < rth    */\n+\temit(ctx, or, rd, rd, tmp);                    /* rd = rd | tmp      */\n+}\n+\n+/* Emulation of 64-bit slti rd, rs, imm, where imm may be S32_MAX + 1 */\n+static void emit_slti_r64(struct jit_context *ctx, u8 rd,\n+\t\t\t  const u8 rs[], s64 imm)\n+{\n+\tu8 t1 = MIPS_R_T8;\n+\tu8 t2 = MIPS_R_T9;\n+\tu8 cmp;\n+\n+\t/*\n+\t * if ((rs < 0) ^ (imm < 0)) t1 = imm >u rsl\n+\t * else                      t1 = rsl <u imm\n+\t */\n+\temit_mov_i(ctx, rd, (s32)imm);\n+\temit(ctx, sltu, t1, lo(rs), rd);               /* t1 = rsl <u imm   */\n+\temit(ctx, sltu, t2, rd, lo(rs));               /* t2 = imm <u rsl   */\n+\temit(ctx, srl, rd, hi(rs), 31);                /* rd = rsh >> 31    */\n+\tif (imm < 0)\n+\t\temit_movz_r(ctx, t1, t2, rd);          /* t1 = rd ? t1 : t2 */\n+\telse\n+\t\temit_movn_r(ctx, t1, t2, rd);          /* t1 = rd ? t2 : t1 */\n+\t/*\n+\t * if ((imm < 0 && rsh != 0xffffffff) ||\n+\t *     (imm >= 0 && rsh != 0))\n+\t *      t1 = 0\n+\t */\n+\tif (imm < 0) {\n+\t\temit(ctx, addiu, rd, hi(rs), 1);       /* rd = rsh + 1 */\n+\t\tcmp = rd;\n+\t} else { /* imm >= 0 */\n+\t\tcmp = hi(rs);\n+\t}\n+\temit_movn_r(ctx, t1, MIPS_R_ZERO, cmp);        /* t1 = 0 if cmp != 0 */\n+\n+\t/*\n+\t * if (imm < 0) rd = rsh < -1\n+\t * else         rd = rsh != 0\n+\t * rd = rd | t1\n+\t */\n+\temit(ctx, slti, rd, hi(rs), imm < 0 ? -1 : 0); /* rd = rsh < hi(imm) */\n+\temit(ctx, or, rd, rd, t1);                     /* rd = rd | t1       */\n+}\n+\n+/* Emulation of 64-bit(slt rd, rs, rt) */\n+static void emit_slt_r64(struct jit_context *ctx, u8 rd,\n+\t\t\t const u8 rs[], const u8 rt[])\n+{\n+\tu8 t1 = MIPS_R_T7;\n+\tu8 t2 = MIPS_R_T8;\n+\tu8 t3 = MIPS_R_T9;\n+\n+\t/*\n+\t * if ((rs < 0) ^ (rt < 0)) t1 = rtl <u rsl\n+\t * else                     t1 = rsl <u rtl\n+\t * if (rsh == rth)          t1 = 0\n+\t */\n+\temit(ctx, sltu, t1, lo(rs), lo(rt));           /* t1 = rsl <u rtl   */\n+\temit(ctx, sltu, t2, lo(rt), lo(rs));           /* t2 = rtl <u rsl   */\n+\temit(ctx, xor, t3, hi(rs), hi(rt));            /* t3 = rlh ^ rth    */\n+\temit(ctx, srl, rd, t3, 31);                    /* rd = t3 >> 31     */\n+\temit_movn_r(ctx, t1, t2, rd);                  /* t1 = rd ? t2 : t1 */\n+\temit_movn_r(ctx, t1, MIPS_R_ZERO, t3);         /* t1 = 0 if t3 != 0 */\n+\n+\t/* rd = (rsh < rth) | t1 */\n+\temit(ctx, slt, rd, hi(rs), hi(rt));            /* rd = rsh <s rth   */\n+\temit(ctx, or, rd, rd, t1);                     /* rd = rd | t1      */\n+}\n+\n+/* Jump immediate (64-bit) */\n+static void emit_jmp_i64(struct jit_context *ctx,\n+\t\t\t const u8 dst[], s32 imm, s32 off, u8 op)\n+{\n+\tu8 tmp = MIPS_R_T6;\n+\n+\tswitch (op) {\n+\t/* No-op, used internally for branch optimization */\n+\tcase JIT_JNOP:\n+\t\tbreak;\n+\t/* PC += off if dst == imm */\n+\t/* PC += off if dst != imm */\n+\tcase BPF_JEQ:\n+\tcase BPF_JNE:\n+\t\tif (imm >= -0x7fff && imm <= 0x8000) {\n+\t\t\temit(ctx, addiu, tmp, lo(dst), -imm);\n+\t\t} else if ((u32)imm <= 0xffff) {\n+\t\t\temit(ctx, xori, tmp, lo(dst), imm);\n+\t\t} else {       /* Register fallback */\n+\t\t\temit_mov_i(ctx, tmp, imm);\n+\t\t\temit(ctx, xor, tmp, lo(dst), tmp);\n+\t\t}\n+\t\tif (imm < 0) { /* Compare sign extension */\n+\t\t\temit(ctx, addu, MIPS_R_T9, hi(dst), 1);\n+\t\t\temit(ctx, or, tmp, tmp, MIPS_R_T9);\n+\t\t} else {       /* Compare zero extension */\n+\t\t\temit(ctx, or, tmp, tmp, hi(dst));\n+\t\t}\n+\t\tif (op == BPF_JEQ)\n+\t\t\temit(ctx, beqz, tmp, off);\n+\t\telse   /* BPF_JNE */\n+\t\t\temit(ctx, bnez, tmp, off);\n+\t\tbreak;\n+\t/* PC += off if dst & imm */\n+\t/* PC += off if (dst & imm) == 0 (not in BPF, used for long jumps) */\n+\tcase BPF_JSET:\n+\tcase JIT_JNSET:\n+\t\tif ((u32)imm <= 0xffff) {\n+\t\t\temit(ctx, andi, tmp, lo(dst), imm);\n+\t\t} else {     /* Register fallback */\n+\t\t\temit_mov_i(ctx, tmp, imm);\n+\t\t\temit(ctx, and, tmp, lo(dst), tmp);\n+\t\t}\n+\t\tif (imm < 0) /* Sign-extension pulls in high word */\n+\t\t\temit(ctx, or, tmp, tmp, hi(dst));\n+\t\tif (op == BPF_JSET)\n+\t\t\temit(ctx, bnez, tmp, off);\n+\t\telse   /* JIT_JNSET */\n+\t\t\temit(ctx, beqz, tmp, off);\n+\t\tbreak;\n+\t/* PC += off if dst > imm */\n+\tcase BPF_JGT:\n+\t\temit_sltiu_r64(ctx, tmp, dst, (s64)imm + 1);\n+\t\temit(ctx, beqz, tmp, off);\n+\t\tbreak;\n+\t/* PC += off if dst >= imm */\n+\tcase BPF_JGE:\n+\t\temit_sltiu_r64(ctx, tmp, dst, imm);\n+\t\temit(ctx, beqz, tmp, off);\n+\t\tbreak;\n+\t/* PC += off if dst < imm */\n+\tcase BPF_JLT:\n+\t\temit_sltiu_r64(ctx, tmp, dst, imm);\n+\t\temit(ctx, bnez, tmp, off);\n+\t\tbreak;\n+\t/* PC += off if dst <= imm */\n+\tcase BPF_JLE:\n+\t\temit_sltiu_r64(ctx, tmp, dst, (s64)imm + 1);\n+\t\temit(ctx, bnez, tmp, off);\n+\t\tbreak;\n+\t/* PC += off if dst > imm (signed) */\n+\tcase BPF_JSGT:\n+\t\temit_slti_r64(ctx, tmp, dst, (s64)imm + 1);\n+\t\temit(ctx, beqz, tmp, off);\n+\t\tbreak;\n+\t/* PC += off if dst >= imm (signed) */\n+\tcase BPF_JSGE:\n+\t\temit_slti_r64(ctx, tmp, dst, imm);\n+\t\temit(ctx, beqz, tmp, off);\n+\t\tbreak;\n+\t/* PC += off if dst < imm (signed) */\n+\tcase BPF_JSLT:\n+\t\temit_slti_r64(ctx, tmp, dst, imm);\n+\t\temit(ctx, bnez, tmp, off);\n+\t\tbreak;\n+\t/* PC += off if dst <= imm (signed) */\n+\tcase BPF_JSLE:\n+\t\temit_slti_r64(ctx, tmp, dst, (s64)imm + 1);\n+\t\temit(ctx, bnez, tmp, off);\n+\t\tbreak;\n+\t}\n+}\n+\n+/* Jump register (64-bit) */\n+static void emit_jmp_r64(struct jit_context *ctx,\n+\t\t\t const u8 dst[], const u8 src[], s32 off, u8 op)\n+{\n+\tu8 t1 = MIPS_R_T6;\n+\tu8 t2 = MIPS_R_T7;\n+\n+\tswitch (op) {\n+\t/* No-op, used internally for branch optimization */\n+\tcase JIT_JNOP:\n+\t\tbreak;\n+\t/* PC += off if dst == src */\n+\t/* PC += off if dst != src */\n+\tcase BPF_JEQ:\n+\tcase BPF_JNE:\n+\t\temit(ctx, subu, t1, lo(dst), lo(src));\n+\t\temit(ctx, subu, t2, hi(dst), hi(src));\n+\t\temit(ctx, or, t1, t1, t2);\n+\t\tif (op == BPF_JEQ)\n+\t\t\temit(ctx, beqz, t1, off);\n+\t\telse   /* BPF_JNE */\n+\t\t\temit(ctx, bnez, t1, off);\n+\t\tbreak;\n+\t/* PC += off if dst & src */\n+\t/* PC += off if (dst & imm) == 0 (not in BPF, used for long jumps) */\n+\tcase BPF_JSET:\n+\tcase JIT_JNSET:\n+\t\temit(ctx, and, t1, lo(dst), lo(src));\n+\t\temit(ctx, and, t2, hi(dst), hi(src));\n+\t\temit(ctx, or, t1, t1, t2);\n+\t\tif (op == BPF_JSET)\n+\t\t\temit(ctx, bnez, t1, off);\n+\t\telse   /* JIT_JNSET */\n+\t\t\temit(ctx, beqz, t1, off);\n+\t\tbreak;\n+\t/* PC += off if dst > src */\n+\tcase BPF_JGT:\n+\t\temit_sltu_r64(ctx, t1, src, dst);\n+\t\temit(ctx, bnez, t1, off);\n+\t\tbreak;\n+\t/* PC += off if dst >= src */\n+\tcase BPF_JGE:\n+\t\temit_sltu_r64(ctx, t1, dst, src);\n+\t\temit(ctx, beqz, t1, off);\n+\t\tbreak;\n+\t/* PC += off if dst < src */\n+\tcase BPF_JLT:\n+\t\temit_sltu_r64(ctx, t1, dst, src);\n+\t\temit(ctx, bnez, t1, off);\n+\t\tbreak;\n+\t/* PC += off if dst <= src */\n+\tcase BPF_JLE:\n+\t\temit_sltu_r64(ctx, t1, src, dst);\n+\t\temit(ctx, beqz, t1, off);\n+\t\tbreak;\n+\t/* PC += off if dst > src (signed) */\n+\tcase BPF_JSGT:\n+\t\temit_slt_r64(ctx, t1, src, dst);\n+\t\temit(ctx, bnez, t1, off);\n+\t\tbreak;\n+\t/* PC += off if dst >= src (signed) */\n+\tcase BPF_JSGE:\n+\t\temit_slt_r64(ctx, t1, dst, src);\n+\t\temit(ctx, beqz, t1, off);\n+\t\tbreak;\n+\t/* PC += off if dst < src (signed) */\n+\tcase BPF_JSLT:\n+\t\temit_slt_r64(ctx, t1, dst, src);\n+\t\temit(ctx, bnez, t1, off);\n+\t\tbreak;\n+\t/* PC += off if dst <= src (signed) */\n+\tcase BPF_JSLE:\n+\t\temit_slt_r64(ctx, t1, src, dst);\n+\t\temit(ctx, beqz, t1, off);\n+\t\tbreak;\n+\t}\n+}\n+\n+/* Function call */\n+static int emit_call(struct jit_context *ctx, const struct bpf_insn *insn)\n+{\n+\tbool fixed;\n+\tu64 addr;\n+\n+\t/* Decode the call address */\n+\tif (bpf_jit_get_func_addr(ctx->program, insn, false,\n+\t\t\t\t  &addr, &fixed) < 0)\n+\t\treturn -1;\n+\tif (!fixed)\n+\t\treturn -1;\n+\n+\t/* Push stack arguments */\n+\tpush_regs(ctx, JIT_STACK_REGS, 0, JIT_RESERVED_STACK);\n+\n+\t/* Emit function call */\n+\temit_mov_i(ctx, MIPS_R_T9, addr);\n+\temit(ctx, jalr, MIPS_R_RA, MIPS_R_T9);\n+\temit(ctx, nop); /* Delay slot */\n+\n+\tclobber_reg(ctx, MIPS_R_RA);\n+\tclobber_reg(ctx, MIPS_R_V0);\n+\tclobber_reg(ctx, MIPS_R_V1);\n+\treturn 0;\n+}\n+\n+/* Function tail call */\n+static int emit_tail_call(struct jit_context *ctx)\n+{\n+\tu8 ary = lo(bpf2mips32[BPF_REG_2]);\n+\tu8 ind = lo(bpf2mips32[BPF_REG_3]);\n+\tu8 t1 = MIPS_R_T8;\n+\tu8 t2 = MIPS_R_T9;\n+\tint off;\n+\n+\t/*\n+\t * Tail call:\n+\t * eBPF R1   - function argument (context ptr), passed in a0-a1\n+\t * eBPF R2   - ptr to object with array of function entry points\n+\t * eBPF R3   - array index of function to be called\n+\t * stack[sz] - remaining tail call count, initialized in prologue\n+\t */\n+\n+\t/* if (ind >= ary->map.max_entries) goto out */\n+\toff = offsetof(struct bpf_array, map.max_entries);\n+\tif (off > 0x7fff)\n+\t\treturn -1;\n+\temit(ctx, lw, t1, off, ary);             /* t1 = ary->map.max_entries*/\n+\temit_load_delay(ctx);                    /* Load delay slot          */\n+\temit(ctx, sltu, t1, ind, t1);            /* t1 = ind < t1            */\n+\temit(ctx, beqz, t1, get_offset(ctx, 1)); /* PC += off(1) if t1 == 0  */\n+\t\t\t\t\t\t /* (next insn delay slot)   */\n+\t/* if (TCC-- <= 0) goto out */\n+\temit(ctx, lw, t2, ctx->stack_size, MIPS_R_SP);  /* t2 = *(SP + size) */\n+\temit_load_delay(ctx);                     /* Load delay slot         */\n+\temit(ctx, blez, t2, get_offset(ctx, 1));  /* PC += off(1) if t2 < 0  */\n+\temit(ctx, addiu, t2, t2, -1);             /* t2-- (delay slot)       */\n+\temit(ctx, sw, t2, ctx->stack_size, MIPS_R_SP);  /* *(SP + size) = t2 */\n+\n+\t/* prog = ary->ptrs[ind] */\n+\toff = offsetof(struct bpf_array, ptrs);\n+\tif (off > 0x7fff)\n+\t\treturn -1;\n+\temit(ctx, sll, t1, ind, 2);               /* t1 = ind << 2           */\n+\temit(ctx, addu, t1, t1, ary);             /* t1 += ary               */\n+\temit(ctx, lw, t2, off, t1);               /* t2 = *(t1 + off)        */\n+\temit_load_delay(ctx);                     /* Load delay slot         */\n+\n+\t/* if (prog == 0) goto out */\n+\temit(ctx, beqz, t2, get_offset(ctx, 1));  /* PC += off(1) if t2 == 0 */\n+\temit(ctx, nop);                           /* Delay slot              */\n+\n+\t/* func = prog->bpf_func + 8 (prologue skip offset) */\n+\toff = offsetof(struct bpf_prog, bpf_func);\n+\tif (off > 0x7fff)\n+\t\treturn -1;\n+\temit(ctx, lw, t1, off, t2);                /* t1 = *(t2 + off)       */\n+\temit_load_delay(ctx);                      /* Load delay slot        */\n+\temit(ctx, addiu, t1, t1, JIT_TCALL_SKIP);  /* t1 += skip (8 or 12)   */\n+\n+\t/* goto func */\n+\tbuild_epilogue(ctx, t1);\n+\treturn 0;\n+}\n+\n+/*\n+ * Stack frame layout for a JITed program (stack grows down).\n+ *\n+ * Higher address  : Caller's stack frame       :\n+ *                 :----------------------------:\n+ *                 : 64-bit eBPF args r3-r5     :\n+ *                 :----------------------------:\n+ *                 : Reserved / tail call count :\n+ *                 +============================+  <--- MIPS sp before call\n+ *                 | Callee-saved registers,    |\n+ *                 | including RA and FP        |\n+ *                 +----------------------------+  <--- eBPF FP (MIPS zero,fp)\n+ *                 | Local eBPF variables       |\n+ *                 | allocated by program       |\n+ *                 +----------------------------+\n+ *                 | Reserved for caller-saved  |\n+ *                 | registers                  |\n+ *                 +----------------------------+\n+ *                 | Reserved for 64-bit eBPF   |\n+ *                 | args r3-r5 & args passed   |\n+ *                 | on stack in kernel calls   |\n+ * Lower address   +============================+  <--- MIPS sp\n+ */\n+\n+/* Build program prologue to set up the stack and registers */\n+void build_prologue(struct jit_context *ctx)\n+{\n+\tconst u8 *r1 = bpf2mips32[BPF_REG_1];\n+\tconst u8 *fp = bpf2mips32[BPF_REG_FP];\n+\tint stack, saved, locals, reserved;\n+\n+\t/*\n+\t * The first two instructions initialize TCC in the reserved (for us)\n+\t * 16-byte area in the parent's stack frame. On a tail call, the\n+\t * calling function jumps into the prologue after these instructions.\n+\t */\n+\temit(ctx, ori, MIPS_R_T9, MIPS_R_ZERO,\n+\t     min(MAX_TAIL_CALL_CNT + 1, 0xffff));\n+\temit(ctx, sw, MIPS_R_T9, 0, MIPS_R_SP);\n+\n+\t/*\n+\t * Register eBPF R1 contains the 32-bit context pointer argument.\n+\t * A 32-bit argument is always passed in MIPS register a0, regardless\n+\t * of CPU endianness. Initialize R1 accordingly and zero-extend.\n+\t */\n+#ifdef __BIG_ENDIAN\n+\temit(ctx, move, lo(r1), MIPS_R_A0);\n+#endif\n+\n+\t/* === Entry-point for tail calls === */\n+\n+\t/* Zero-extend the 32-bit argument */\n+\temit(ctx, move, hi(r1), MIPS_R_ZERO);\n+\n+\t/* If the eBPF frame pointer was accessed it must be saved */\n+\tif (ctx->accessed & BIT(BPF_REG_FP))\n+\t\tclobber_reg64(ctx, fp);\n+\n+\t/* Compute the stack space needed for callee-saved registers */\n+\tsaved = hweight32(ctx->clobbered & JIT_CALLEE_REGS) * sizeof(u32);\n+\tsaved = ALIGN(saved, MIPS_STACK_ALIGNMENT);\n+\n+\t/* Stack space used by eBPF program local data */\n+\tlocals = ALIGN(ctx->program->aux->stack_depth, MIPS_STACK_ALIGNMENT);\n+\n+\t/*\n+\t * If we are emitting function calls, reserve extra stack space for\n+\t * caller-saved registers and function arguments passed on the stack.\n+\t * The required space is computed automatically during resource\n+\t * usage discovery (pass 1).\n+\t */\n+\treserved = ctx->stack_used;\n+\n+\t/* Allocate the stack frame */\n+\tstack = ALIGN(saved + locals + reserved, MIPS_STACK_ALIGNMENT);\n+\temit(ctx, addiu, MIPS_R_SP, MIPS_R_SP, -stack);\n+\n+\t/* Store callee-saved registers on stack */\n+\tpush_regs(ctx, ctx->clobbered & JIT_CALLEE_REGS, 0, stack - saved);\n+\n+\t/* Initialize the eBPF frame pointer if accessed */\n+\tif (ctx->accessed & BIT(BPF_REG_FP))\n+\t\temit(ctx, addiu, lo(fp), MIPS_R_SP, stack - saved);\n+\n+\tctx->saved_size = saved;\n+\tctx->stack_size = stack;\n+}\n+\n+/* Build the program epilogue to restore the stack and registers */\n+void build_epilogue(struct jit_context *ctx, int dest_reg)\n+{\n+\t/* Restore callee-saved registers from stack */\n+\tpop_regs(ctx, ctx->clobbered & JIT_CALLEE_REGS, 0,\n+\t\t ctx->stack_size - ctx->saved_size);\n+\t/*\n+\t * A 32-bit return value is always passed in MIPS register v0,\n+\t * but on big-endian targets the low part of R0 is mapped to v1.\n+\t */\n+#ifdef __BIG_ENDIAN\n+\temit(ctx, move, MIPS_R_V0, MIPS_R_V1);\n+#endif\n+\n+\t/* Jump to the return address and adjust the stack pointer */\n+\temit(ctx, jr, dest_reg);\n+\temit(ctx, addiu, MIPS_R_SP, MIPS_R_SP, ctx->stack_size);\n+}\n+\n+/* Build one eBPF instruction */\n+int build_insn(const struct bpf_insn *insn, struct jit_context *ctx)\n+{\n+\tconst u8 *dst = bpf2mips32[insn->dst_reg];\n+\tconst u8 *src = bpf2mips32[insn->src_reg];\n+\tconst u8 *tmp = bpf2mips32[JIT_REG_TMP];\n+\tu8 code = insn->code;\n+\ts16 off = insn->off;\n+\ts32 imm = insn->imm;\n+\ts32 val, rel;\n+\tu8 alu, jmp;\n+\n+\tswitch (code) {\n+\t/* ALU operations */\n+\t/* dst = imm */\n+\tcase BPF_ALU | BPF_MOV | BPF_K:\n+\t\temit_mov_i(ctx, lo(dst), imm);\n+\t\temit_zext_ver(ctx, dst);\n+\t\tbreak;\n+\t/* dst = src */\n+\tcase BPF_ALU | BPF_MOV | BPF_X:\n+\t\tif (imm == 1) {\n+\t\t\t/* Special mov32 for zext */\n+\t\t\temit_mov_i(ctx, hi(dst), 0);\n+\t\t} else {\n+\t\t\temit_mov_r(ctx, lo(dst), lo(src));\n+\t\t\temit_zext_ver(ctx, dst);\n+\t\t}\n+\t\tbreak;\n+\t/* dst = -dst */\n+\tcase BPF_ALU | BPF_NEG:\n+\t\temit_alu_i(ctx, lo(dst), 0, BPF_NEG);\n+\t\temit_zext_ver(ctx, dst);\n+\t\tbreak;\n+\t/* dst = dst & imm */\n+\t/* dst = dst | imm */\n+\t/* dst = dst ^ imm */\n+\t/* dst = dst << imm */\n+\t/* dst = dst >> imm */\n+\t/* dst = dst >> imm (arithmetic) */\n+\t/* dst = dst + imm */\n+\t/* dst = dst - imm */\n+\t/* dst = dst * imm */\n+\t/* dst = dst / imm */\n+\t/* dst = dst % imm */\n+\tcase BPF_ALU | BPF_OR | BPF_K:\n+\tcase BPF_ALU | BPF_AND | BPF_K:\n+\tcase BPF_ALU | BPF_XOR | BPF_K:\n+\tcase BPF_ALU | BPF_LSH | BPF_K:\n+\tcase BPF_ALU | BPF_RSH | BPF_K:\n+\tcase BPF_ALU | BPF_ARSH | BPF_K:\n+\tcase BPF_ALU | BPF_ADD | BPF_K:\n+\tcase BPF_ALU | BPF_SUB | BPF_K:\n+\tcase BPF_ALU | BPF_MUL | BPF_K:\n+\tcase BPF_ALU | BPF_DIV | BPF_K:\n+\tcase BPF_ALU | BPF_MOD | BPF_K:\n+\t\tif (!valid_alu_i(BPF_OP(code), imm)) {\n+\t\t\temit_mov_i(ctx, MIPS_R_T6, imm);\n+\t\t\temit_alu_r(ctx, lo(dst), MIPS_R_T6, BPF_OP(code));\n+\t\t} else if (rewrite_alu_i(BPF_OP(code), imm, &alu, &val)) {\n+\t\t\temit_alu_i(ctx, lo(dst), val, alu);\n+\t\t}\n+\t\temit_zext_ver(ctx, dst);\n+\t\tbreak;\n+\t/* dst = dst & src */\n+\t/* dst = dst | src */\n+\t/* dst = dst ^ src */\n+\t/* dst = dst << src */\n+\t/* dst = dst >> src */\n+\t/* dst = dst >> src (arithmetic) */\n+\t/* dst = dst + src */\n+\t/* dst = dst - src */\n+\t/* dst = dst * src */\n+\t/* dst = dst / src */\n+\t/* dst = dst % src */\n+\tcase BPF_ALU | BPF_AND | BPF_X:\n+\tcase BPF_ALU | BPF_OR | BPF_X:\n+\tcase BPF_ALU | BPF_XOR | BPF_X:\n+\tcase BPF_ALU | BPF_LSH | BPF_X:\n+\tcase BPF_ALU | BPF_RSH | BPF_X:\n+\tcase BPF_ALU | BPF_ARSH | BPF_X:\n+\tcase BPF_ALU | BPF_ADD | BPF_X:\n+\tcase BPF_ALU | BPF_SUB | BPF_X:\n+\tcase BPF_ALU | BPF_MUL | BPF_X:\n+\tcase BPF_ALU | BPF_DIV | BPF_X:\n+\tcase BPF_ALU | BPF_MOD | BPF_X:\n+\t\temit_alu_r(ctx, lo(dst), lo(src), BPF_OP(code));\n+\t\temit_zext_ver(ctx, dst);\n+\t\tbreak;\n+\t/* dst = imm (64-bit) */\n+\tcase BPF_ALU64 | BPF_MOV | BPF_K:\n+\t\temit_mov_se_i64(ctx, dst, imm);\n+\t\tbreak;\n+\t/* dst = src (64-bit) */\n+\tcase BPF_ALU64 | BPF_MOV | BPF_X:\n+\t\temit_mov_r(ctx, lo(dst), lo(src));\n+\t\temit_mov_r(ctx, hi(dst), hi(src));\n+\t\tbreak;\n+\t/* dst = -dst (64-bit) */\n+\tcase BPF_ALU64 | BPF_NEG:\n+\t\temit_neg_i64(ctx, dst);\n+\t\tbreak;\n+\t/* dst = dst & imm (64-bit) */\n+\tcase BPF_ALU64 | BPF_AND | BPF_K:\n+\t\temit_alu_i64(ctx, dst, imm, BPF_OP(code));\n+\t\tbreak;\n+\t/* dst = dst | imm (64-bit) */\n+\t/* dst = dst ^ imm (64-bit) */\n+\t/* dst = dst + imm (64-bit) */\n+\t/* dst = dst - imm (64-bit) */\n+\tcase BPF_ALU64 | BPF_OR | BPF_K:\n+\tcase BPF_ALU64 | BPF_XOR | BPF_K:\n+\tcase BPF_ALU64 | BPF_ADD | BPF_K:\n+\tcase BPF_ALU64 | BPF_SUB | BPF_K:\n+\t\tif (imm)\n+\t\t\temit_alu_i64(ctx, dst, imm, BPF_OP(code));\n+\t\tbreak;\n+\t/* dst = dst << imm (64-bit) */\n+\t/* dst = dst >> imm (64-bit) */\n+\t/* dst = dst >> imm (64-bit, arithmetic) */\n+\tcase BPF_ALU64 | BPF_LSH | BPF_K:\n+\tcase BPF_ALU64 | BPF_RSH | BPF_K:\n+\tcase BPF_ALU64 | BPF_ARSH | BPF_K:\n+\t\tif (imm)\n+\t\t\temit_shift_i64(ctx, dst, imm, BPF_OP(code));\n+\t\tbreak;\n+\t/* dst = dst * imm (64-bit) */\n+\tcase BPF_ALU64 | BPF_MUL | BPF_K:\n+\t\temit_mul_i64(ctx, dst, imm);\n+\t\tbreak;\n+\t/* dst = dst / imm (64-bit) */\n+\t/* dst = dst % imm (64-bit) */\n+\tcase BPF_ALU64 | BPF_DIV | BPF_K:\n+\tcase BPF_ALU64 | BPF_MOD | BPF_K:\n+\t\t/*\n+\t\t * Sign-extend the immediate value into a temporary register,\n+\t\t * and then do the operation on this register.\n+\t\t */\n+\t\temit_mov_se_i64(ctx, tmp, imm);\n+\t\temit_divmod_r64(ctx, dst, tmp, BPF_OP(code));\n+\t\tbreak;\n+\t/* dst = dst & src (64-bit) */\n+\t/* dst = dst | src (64-bit) */\n+\t/* dst = dst ^ src (64-bit) */\n+\t/* dst = dst + src (64-bit) */\n+\t/* dst = dst - src (64-bit) */\n+\tcase BPF_ALU64 | BPF_AND | BPF_X:\n+\tcase BPF_ALU64 | BPF_OR | BPF_X:\n+\tcase BPF_ALU64 | BPF_XOR | BPF_X:\n+\tcase BPF_ALU64 | BPF_ADD | BPF_X:\n+\tcase BPF_ALU64 | BPF_SUB | BPF_X:\n+\t\temit_alu_r64(ctx, dst, src, BPF_OP(code));\n+\t\tbreak;\n+\t/* dst = dst << src (64-bit) */\n+\t/* dst = dst >> src (64-bit) */\n+\t/* dst = dst >> src (64-bit, arithmetic) */\n+\tcase BPF_ALU64 | BPF_LSH | BPF_X:\n+\tcase BPF_ALU64 | BPF_RSH | BPF_X:\n+\tcase BPF_ALU64 | BPF_ARSH | BPF_X:\n+\t\temit_shift_r64(ctx, dst, lo(src), BPF_OP(code));\n+\t\tbreak;\n+\t/* dst = dst * src (64-bit) */\n+\tcase BPF_ALU64 | BPF_MUL | BPF_X:\n+\t\temit_mul_r64(ctx, dst, src);\n+\t\tbreak;\n+\t/* dst = dst / src (64-bit) */\n+\t/* dst = dst % src (64-bit) */\n+\tcase BPF_ALU64 | BPF_DIV | BPF_X:\n+\tcase BPF_ALU64 | BPF_MOD | BPF_X:\n+\t\temit_divmod_r64(ctx, dst, src, BPF_OP(code));\n+\t\tbreak;\n+\t/* dst = htole(dst) */\n+\t/* dst = htobe(dst) */\n+\tcase BPF_ALU | BPF_END | BPF_FROM_LE:\n+\tcase BPF_ALU | BPF_END | BPF_FROM_BE:\n+\t\tif (BPF_SRC(code) ==\n+#ifdef __BIG_ENDIAN\n+\t\t    BPF_FROM_LE\n+#else\n+\t\t    BPF_FROM_BE\n+#endif\n+\t\t    )\n+\t\t\temit_bswap_r64(ctx, dst, imm);\n+\t\telse\n+\t\t\temit_trunc_r64(ctx, dst, imm);\n+\t\tbreak;\n+\t/* dst = imm64 */\n+\tcase BPF_LD | BPF_IMM | BPF_DW:\n+\t\temit_mov_i(ctx, lo(dst), imm);\n+\t\temit_mov_i(ctx, hi(dst), insn[1].imm);\n+\t\treturn 1;\n+\t/* LDX: dst = *(size *)(src + off) */\n+\tcase BPF_LDX | BPF_MEM | BPF_W:\n+\tcase BPF_LDX | BPF_MEM | BPF_H:\n+\tcase BPF_LDX | BPF_MEM | BPF_B:\n+\tcase BPF_LDX | BPF_MEM | BPF_DW:\n+\t\temit_ldx(ctx, dst, lo(src), off, BPF_SIZE(code));\n+\t\tbreak;\n+\t/* ST: *(size *)(dst + off) = imm */\n+\tcase BPF_ST | BPF_MEM | BPF_W:\n+\tcase BPF_ST | BPF_MEM | BPF_H:\n+\tcase BPF_ST | BPF_MEM | BPF_B:\n+\tcase BPF_ST | BPF_MEM | BPF_DW:\n+\t\tswitch (BPF_SIZE(code)) {\n+\t\tcase BPF_DW:\n+\t\t\t/* Sign-extend immediate value into temporary reg */\n+\t\t\temit_mov_se_i64(ctx, tmp, imm);\n+\t\t\tbreak;\n+\t\tcase BPF_W:\n+\t\tcase BPF_H:\n+\t\tcase BPF_B:\n+\t\t\temit_mov_i(ctx, lo(tmp), imm);\n+\t\t\tbreak;\n+\t\t}\n+\t\temit_stx(ctx, lo(dst), tmp, off, BPF_SIZE(code));\n+\t\tbreak;\n+\t/* STX: *(size *)(dst + off) = src */\n+\tcase BPF_STX | BPF_MEM | BPF_W:\n+\tcase BPF_STX | BPF_MEM | BPF_H:\n+\tcase BPF_STX | BPF_MEM | BPF_B:\n+\tcase BPF_STX | BPF_MEM | BPF_DW:\n+\t\temit_stx(ctx, lo(dst), src, off, BPF_SIZE(code));\n+\t\tbreak;\n+\t/* Speculation barrier */\n+\tcase BPF_ST | BPF_NOSPEC:\n+\t\tbreak;\n+\t/* Atomics */\n+\tcase BPF_STX | BPF_XADD | BPF_W:\n+\t\tswitch (imm) {\n+\t\tcase BPF_ADD:\n+\t\tcase BPF_AND:\n+\t\tcase BPF_OR:\n+\t\tcase BPF_XOR:\n+\t\t\tif (cpu_has_llsc)\n+\t\t\t\temit_atomic_r(ctx, lo(dst), lo(src), off, imm);\n+\t\t\telse /* Non-ll/sc fallback */\n+\t\t\t\temit_atomic_r32(ctx, lo(dst), lo(src),\n+\t\t\t\t\t\toff, imm);\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tgoto notyet;\n+\t\t}\n+\t\tbreak;\n+\t/* Atomics (64-bit) */\n+\tcase BPF_STX | BPF_XADD | BPF_DW:\n+\t\tswitch (imm) {\n+\t\tcase BPF_ADD:\n+\t\tcase BPF_AND:\n+\t\tcase BPF_OR:\n+\t\tcase BPF_XOR:\n+\t\t\temit_atomic_r64(ctx, lo(dst), src, off, imm);\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tgoto notyet;\n+\t\t}\n+\t\tbreak;\n+\t/* PC += off if dst == src */\n+\t/* PC += off if dst != src */\n+\t/* PC += off if dst & src */\n+\t/* PC += off if dst > src */\n+\t/* PC += off if dst >= src */\n+\t/* PC += off if dst < src */\n+\t/* PC += off if dst <= src */\n+\t/* PC += off if dst > src (signed) */\n+\t/* PC += off if dst >= src (signed) */\n+\t/* PC += off if dst < src (signed) */\n+\t/* PC += off if dst <= src (signed) */\n+\tcase BPF_JMP32 | BPF_JEQ | BPF_X:\n+\tcase BPF_JMP32 | BPF_JNE | BPF_X:\n+\tcase BPF_JMP32 | BPF_JSET | BPF_X:\n+\tcase BPF_JMP32 | BPF_JGT | BPF_X:\n+\tcase BPF_JMP32 | BPF_JGE | BPF_X:\n+\tcase BPF_JMP32 | BPF_JLT | BPF_X:\n+\tcase BPF_JMP32 | BPF_JLE | BPF_X:\n+\tcase BPF_JMP32 | BPF_JSGT | BPF_X:\n+\tcase BPF_JMP32 | BPF_JSGE | BPF_X:\n+\tcase BPF_JMP32 | BPF_JSLT | BPF_X:\n+\tcase BPF_JMP32 | BPF_JSLE | BPF_X:\n+\t\tif (off == 0)\n+\t\t\tbreak;\n+\t\tsetup_jmp_r(ctx, dst == src, BPF_OP(code), off, &jmp, &rel);\n+\t\temit_jmp_r(ctx, lo(dst), lo(src), rel, jmp);\n+\t\tif (finish_jmp(ctx, jmp, off) < 0)\n+\t\t\tgoto toofar;\n+\t\tbreak;\n+\t/* PC += off if dst == imm */\n+\t/* PC += off if dst != imm */\n+\t/* PC += off if dst & imm */\n+\t/* PC += off if dst > imm */\n+\t/* PC += off if dst >= imm */\n+\t/* PC += off if dst < imm */\n+\t/* PC += off if dst <= imm */\n+\t/* PC += off if dst > imm (signed) */\n+\t/* PC += off if dst >= imm (signed) */\n+\t/* PC += off if dst < imm (signed) */\n+\t/* PC += off if dst <= imm (signed) */\n+\tcase BPF_JMP32 | BPF_JEQ | BPF_K:\n+\tcase BPF_JMP32 | BPF_JNE | BPF_K:\n+\tcase BPF_JMP32 | BPF_JSET | BPF_K:\n+\tcase BPF_JMP32 | BPF_JGT | BPF_K:\n+\tcase BPF_JMP32 | BPF_JGE | BPF_K:\n+\tcase BPF_JMP32 | BPF_JLT | BPF_K:\n+\tcase BPF_JMP32 | BPF_JLE | BPF_K:\n+\tcase BPF_JMP32 | BPF_JSGT | BPF_K:\n+\tcase BPF_JMP32 | BPF_JSGE | BPF_K:\n+\tcase BPF_JMP32 | BPF_JSLT | BPF_K:\n+\tcase BPF_JMP32 | BPF_JSLE | BPF_K:\n+\t\tif (off == 0)\n+\t\t\tbreak;\n+\t\tsetup_jmp_i(ctx, imm, 32, BPF_OP(code), off, &jmp, &rel);\n+\t\tif (valid_jmp_i(jmp, imm)) {\n+\t\t\temit_jmp_i(ctx, lo(dst), imm, rel, jmp);\n+\t\t} else {\n+\t\t\t/* Move large immediate to register */\n+\t\t\temit_mov_i(ctx, MIPS_R_T6, imm);\n+\t\t\temit_jmp_r(ctx, lo(dst), MIPS_R_T6, rel, jmp);\n+\t\t}\n+\t\tif (finish_jmp(ctx, jmp, off) < 0)\n+\t\t\tgoto toofar;\n+\t\tbreak;\n+\t/* PC += off if dst == src */\n+\t/* PC += off if dst != src */\n+\t/* PC += off if dst & src */\n+\t/* PC += off if dst > src */\n+\t/* PC += off if dst >= src */\n+\t/* PC += off if dst < src */\n+\t/* PC += off if dst <= src */\n+\t/* PC += off if dst > src (signed) */\n+\t/* PC += off if dst >= src (signed) */\n+\t/* PC += off if dst < src (signed) */\n+\t/* PC += off if dst <= src (signed) */\n+\tcase BPF_JMP | BPF_JEQ | BPF_X:\n+\tcase BPF_JMP | BPF_JNE | BPF_X:\n+\tcase BPF_JMP | BPF_JSET | BPF_X:\n+\tcase BPF_JMP | BPF_JGT | BPF_X:\n+\tcase BPF_JMP | BPF_JGE | BPF_X:\n+\tcase BPF_JMP | BPF_JLT | BPF_X:\n+\tcase BPF_JMP | BPF_JLE | BPF_X:\n+\tcase BPF_JMP | BPF_JSGT | BPF_X:\n+\tcase BPF_JMP | BPF_JSGE | BPF_X:\n+\tcase BPF_JMP | BPF_JSLT | BPF_X:\n+\tcase BPF_JMP | BPF_JSLE | BPF_X:\n+\t\tif (off == 0)\n+\t\t\tbreak;\n+\t\tsetup_jmp_r(ctx, dst == src, BPF_OP(code), off, &jmp, &rel);\n+\t\temit_jmp_r64(ctx, dst, src, rel, jmp);\n+\t\tif (finish_jmp(ctx, jmp, off) < 0)\n+\t\t\tgoto toofar;\n+\t\tbreak;\n+\t/* PC += off if dst == imm */\n+\t/* PC += off if dst != imm */\n+\t/* PC += off if dst & imm */\n+\t/* PC += off if dst > imm */\n+\t/* PC += off if dst >= imm */\n+\t/* PC += off if dst < imm */\n+\t/* PC += off if dst <= imm */\n+\t/* PC += off if dst > imm (signed) */\n+\t/* PC += off if dst >= imm (signed) */\n+\t/* PC += off if dst < imm (signed) */\n+\t/* PC += off if dst <= imm (signed) */\n+\tcase BPF_JMP | BPF_JEQ | BPF_K:\n+\tcase BPF_JMP | BPF_JNE | BPF_K:\n+\tcase BPF_JMP | BPF_JSET | BPF_K:\n+\tcase BPF_JMP | BPF_JGT | BPF_K:\n+\tcase BPF_JMP | BPF_JGE | BPF_K:\n+\tcase BPF_JMP | BPF_JLT | BPF_K:\n+\tcase BPF_JMP | BPF_JLE | BPF_K:\n+\tcase BPF_JMP | BPF_JSGT | BPF_K:\n+\tcase BPF_JMP | BPF_JSGE | BPF_K:\n+\tcase BPF_JMP | BPF_JSLT | BPF_K:\n+\tcase BPF_JMP | BPF_JSLE | BPF_K:\n+\t\tif (off == 0)\n+\t\t\tbreak;\n+\t\tsetup_jmp_i(ctx, imm, 64, BPF_OP(code), off, &jmp, &rel);\n+\t\temit_jmp_i64(ctx, dst, imm, rel, jmp);\n+\t\tif (finish_jmp(ctx, jmp, off) < 0)\n+\t\t\tgoto toofar;\n+\t\tbreak;\n+\t/* PC += off */\n+\tcase BPF_JMP | BPF_JA:\n+\t\tif (off == 0)\n+\t\t\tbreak;\n+\t\tif (emit_ja(ctx, off) < 0)\n+\t\t\tgoto toofar;\n+\t\tbreak;\n+\t/* Tail call */\n+\tcase BPF_JMP | BPF_TAIL_CALL:\n+\t\tif (emit_tail_call(ctx) < 0)\n+\t\t\tgoto invalid;\n+\t\tbreak;\n+\t/* Function call */\n+\tcase BPF_JMP | BPF_CALL:\n+\t\tif (emit_call(ctx, insn) < 0)\n+\t\t\tgoto invalid;\n+\t\tbreak;\n+\t/* Function return */\n+\tcase BPF_JMP | BPF_EXIT:\n+\t\t/*\n+\t\t * Optimization: when last instruction is EXIT\n+\t\t * simply continue to epilogue.\n+\t\t */\n+\t\tif (ctx->bpf_index == ctx->program->len - 1)\n+\t\t\tbreak;\n+\t\tif (emit_exit(ctx) < 0)\n+\t\t\tgoto toofar;\n+\t\tbreak;\n+\n+\tdefault:\n+invalid:\n+\t\tpr_err_once(\"unknown opcode %02x\\n\", code);\n+\t\treturn -EINVAL;\n+notyet:\n+\t\tpr_info_once(\"*** NOT YET: opcode %02x ***\\n\", code);\n+\t\treturn -EFAULT;\n+toofar:\n+\t\tpr_info_once(\"*** TOO FAR: jump at %u opcode %02x ***\\n\",\n+\t\t\t     ctx->bpf_index, code);\n+\t\treturn -E2BIG;\n+\t}\n+\treturn 0;\n+}\n"
  },
  {
    "path": "target/linux/generic/backport-5.15/050-v5.16-03-mips-bpf-Add-new-eBPF-JIT-for-64-bit-MIPS.patch",
    "content": "From: Johan Almbladh <johan.almbladh@anyfinetworks.com>\nDate: Tue, 5 Oct 2021 18:54:05 +0200\nSubject: [PATCH] mips: bpf: Add new eBPF JIT for 64-bit MIPS\n\nThis is an implementation on of an eBPF JIT for 64-bit MIPS III-V and\nMIPS64r1-r6. It uses the same framework introduced by the 32-bit JIT.\n\nSigned-off-by: Johan Almbladh <johan.almbladh@anyfinetworks.com>\n---\n create mode 100644 arch/mips/net/bpf_jit_comp64.c\n\n--- /dev/null\n+++ b/arch/mips/net/bpf_jit_comp64.c\n@@ -0,0 +1,991 @@\n+// SPDX-License-Identifier: GPL-2.0-only\n+/*\n+ * Just-In-Time compiler for eBPF bytecode on MIPS.\n+ * Implementation of JIT functions for 64-bit CPUs.\n+ *\n+ * Copyright (c) 2021 Anyfi Networks AB.\n+ * Author: Johan Almbladh <johan.almbladh@gmail.com>\n+ *\n+ * Based on code and ideas from\n+ * Copyright (c) 2017 Cavium, Inc.\n+ * Copyright (c) 2017 Shubham Bansal <illusionist.neo@gmail.com>\n+ * Copyright (c) 2011 Mircea Gherzan <mgherzan@gmail.com>\n+ */\n+\n+#include <linux/errno.h>\n+#include <linux/filter.h>\n+#include <linux/bpf.h>\n+#include <asm/cpu-features.h>\n+#include <asm/isa-rev.h>\n+#include <asm/uasm.h>\n+\n+#include \"bpf_jit_comp.h\"\n+\n+/* MIPS t0-t3 are not available in the n64 ABI */\n+#undef MIPS_R_T0\n+#undef MIPS_R_T1\n+#undef MIPS_R_T2\n+#undef MIPS_R_T3\n+\n+/* Stack is 16-byte aligned in n64 ABI */\n+#define MIPS_STACK_ALIGNMENT 16\n+\n+/* Extra 64-bit eBPF registers used by JIT */\n+#define JIT_REG_TC (MAX_BPF_JIT_REG + 0)\n+#define JIT_REG_ZX (MAX_BPF_JIT_REG + 1)\n+\n+/* Number of prologue bytes to skip when doing a tail call */\n+#define JIT_TCALL_SKIP 4\n+\n+/* Callee-saved CPU registers that the JIT must preserve */\n+#define JIT_CALLEE_REGS   \\\n+\t(BIT(MIPS_R_S0) | \\\n+\t BIT(MIPS_R_S1) | \\\n+\t BIT(MIPS_R_S2) | \\\n+\t BIT(MIPS_R_S3) | \\\n+\t BIT(MIPS_R_S4) | \\\n+\t BIT(MIPS_R_S5) | \\\n+\t BIT(MIPS_R_S6) | \\\n+\t BIT(MIPS_R_S7) | \\\n+\t BIT(MIPS_R_GP) | \\\n+\t BIT(MIPS_R_FP) | \\\n+\t BIT(MIPS_R_RA))\n+\n+/* Caller-saved CPU registers available for JIT use */\n+#define JIT_CALLER_REGS\t  \\\n+\t(BIT(MIPS_R_A5) | \\\n+\t BIT(MIPS_R_A6) | \\\n+\t BIT(MIPS_R_A7))\n+/*\n+ * Mapping of 64-bit eBPF registers to 64-bit native MIPS registers.\n+ * MIPS registers t4 - t7 may be used by the JIT as temporary registers.\n+ * MIPS registers t8 - t9 are reserved for single-register common functions.\n+ */\n+static const u8 bpf2mips64[] = {\n+\t/* Return value from in-kernel function, and exit value from eBPF */\n+\t[BPF_REG_0] = MIPS_R_V0,\n+\t/* Arguments from eBPF program to in-kernel function */\n+\t[BPF_REG_1] = MIPS_R_A0,\n+\t[BPF_REG_2] = MIPS_R_A1,\n+\t[BPF_REG_3] = MIPS_R_A2,\n+\t[BPF_REG_4] = MIPS_R_A3,\n+\t[BPF_REG_5] = MIPS_R_A4,\n+\t/* Callee-saved registers that in-kernel function will preserve */\n+\t[BPF_REG_6] = MIPS_R_S0,\n+\t[BPF_REG_7] = MIPS_R_S1,\n+\t[BPF_REG_8] = MIPS_R_S2,\n+\t[BPF_REG_9] = MIPS_R_S3,\n+\t/* Read-only frame pointer to access the eBPF stack */\n+\t[BPF_REG_FP] = MIPS_R_FP,\n+\t/* Temporary register for blinding constants */\n+\t[BPF_REG_AX] = MIPS_R_AT,\n+\t/* Tail call count register, caller-saved */\n+\t[JIT_REG_TC] = MIPS_R_A5,\n+\t/* Constant for register zero-extension */\n+\t[JIT_REG_ZX] = MIPS_R_V1,\n+};\n+\n+/*\n+ * MIPS 32-bit operations on 64-bit registers generate a sign-extended\n+ * result. However, the eBPF ISA mandates zero-extension, so we rely on the\n+ * verifier to add that for us (emit_zext_ver). In addition, ALU arithmetic\n+ * operations, right shift and byte swap require properly sign-extended\n+ * operands or the result is unpredictable. We emit explicit sign-extensions\n+ * in those cases.\n+ */\n+\n+/* Sign extension */\n+static void emit_sext(struct jit_context *ctx, u8 dst, u8 src)\n+{\n+\temit(ctx, sll, dst, src, 0);\n+\tclobber_reg(ctx, dst);\n+}\n+\n+/* Zero extension */\n+static void emit_zext(struct jit_context *ctx, u8 dst)\n+{\n+\tif (cpu_has_mips64r2 || cpu_has_mips64r6) {\n+\t\temit(ctx, dinsu, dst, MIPS_R_ZERO, 32, 32);\n+\t} else {\n+\t\temit(ctx, and, dst, dst, bpf2mips64[JIT_REG_ZX]);\n+\t\taccess_reg(ctx, JIT_REG_ZX); /* We need the ZX register */\n+\t}\n+\tclobber_reg(ctx, dst);\n+}\n+\n+/* Zero extension, if verifier does not do it for us  */\n+static void emit_zext_ver(struct jit_context *ctx, u8 dst)\n+{\n+\tif (!ctx->program->aux->verifier_zext)\n+\t\temit_zext(ctx, dst);\n+}\n+\n+/* dst = imm (64-bit) */\n+static void emit_mov_i64(struct jit_context *ctx, u8 dst, u64 imm64)\n+{\n+\tif (imm64 >= 0xffffffffffff8000ULL || imm64 < 0x8000ULL) {\n+\t\temit(ctx, daddiu, dst, MIPS_R_ZERO, (s16)imm64);\n+\t} else if (imm64 >= 0xffffffff80000000ULL ||\n+\t\t   (imm64 < 0x80000000 && imm64 > 0xffff)) {\n+\t\temit(ctx, lui, dst, (s16)(imm64 >> 16));\n+\t\temit(ctx, ori, dst, dst, (u16)imm64 & 0xffff);\n+\t} else {\n+\t\tu8 acc = MIPS_R_ZERO;\n+\t\tint k;\n+\n+\t\tfor (k = 0; k < 4; k++) {\n+\t\t\tu16 half = imm64 >> (48 - 16 * k);\n+\n+\t\t\tif (acc == dst)\n+\t\t\t\temit(ctx, dsll, dst, dst, 16);\n+\n+\t\t\tif (half) {\n+\t\t\t\temit(ctx, ori, dst, acc, half);\n+\t\t\t\tacc = dst;\n+\t\t\t}\n+\t\t}\n+\t}\n+\tclobber_reg(ctx, dst);\n+}\n+\n+/* ALU immediate operation (64-bit) */\n+static void emit_alu_i64(struct jit_context *ctx, u8 dst, s32 imm, u8 op)\n+{\n+\tswitch (BPF_OP(op)) {\n+\t/* dst = dst | imm */\n+\tcase BPF_OR:\n+\t\temit(ctx, ori, dst, dst, (u16)imm);\n+\t\tbreak;\n+\t/* dst = dst ^ imm */\n+\tcase BPF_XOR:\n+\t\temit(ctx, xori, dst, dst, (u16)imm);\n+\t\tbreak;\n+\t/* dst = -dst */\n+\tcase BPF_NEG:\n+\t\temit(ctx, dsubu, dst, MIPS_R_ZERO, dst);\n+\t\tbreak;\n+\t/* dst = dst << imm */\n+\tcase BPF_LSH:\n+\t\temit(ctx, dsll_safe, dst, dst, imm);\n+\t\tbreak;\n+\t/* dst = dst >> imm */\n+\tcase BPF_RSH:\n+\t\temit(ctx, dsrl_safe, dst, dst, imm);\n+\t\tbreak;\n+\t/* dst = dst >> imm (arithmetic) */\n+\tcase BPF_ARSH:\n+\t\temit(ctx, dsra_safe, dst, dst, imm);\n+\t\tbreak;\n+\t/* dst = dst + imm */\n+\tcase BPF_ADD:\n+\t\temit(ctx, daddiu, dst, dst, imm);\n+\t\tbreak;\n+\t/* dst = dst - imm */\n+\tcase BPF_SUB:\n+\t\temit(ctx, daddiu, dst, dst, -imm);\n+\t\tbreak;\n+\tdefault:\n+\t\t/* Width-generic operations */\n+\t\temit_alu_i(ctx, dst, imm, op);\n+\t}\n+\tclobber_reg(ctx, dst);\n+}\n+\n+/* ALU register operation (64-bit) */\n+static void emit_alu_r64(struct jit_context *ctx, u8 dst, u8 src, u8 op)\n+{\n+\tswitch (BPF_OP(op)) {\n+\t/* dst = dst << src */\n+\tcase BPF_LSH:\n+\t\temit(ctx, dsllv, dst, dst, src);\n+\t\tbreak;\n+\t/* dst = dst >> src */\n+\tcase BPF_RSH:\n+\t\temit(ctx, dsrlv, dst, dst, src);\n+\t\tbreak;\n+\t/* dst = dst >> src (arithmetic) */\n+\tcase BPF_ARSH:\n+\t\temit(ctx, dsrav, dst, dst, src);\n+\t\tbreak;\n+\t/* dst = dst + src */\n+\tcase BPF_ADD:\n+\t\temit(ctx, daddu, dst, dst, src);\n+\t\tbreak;\n+\t/* dst = dst - src */\n+\tcase BPF_SUB:\n+\t\temit(ctx, dsubu, dst, dst, src);\n+\t\tbreak;\n+\t/* dst = dst * src */\n+\tcase BPF_MUL:\n+\t\tif (cpu_has_mips64r6) {\n+\t\t\temit(ctx, dmulu, dst, dst, src);\n+\t\t} else {\n+\t\t\temit(ctx, dmultu, dst, src);\n+\t\t\temit(ctx, mflo, dst);\n+\t\t}\n+\t\tbreak;\n+\t/* dst = dst / src */\n+\tcase BPF_DIV:\n+\t\tif (cpu_has_mips64r6) {\n+\t\t\temit(ctx, ddivu_r6, dst, dst, src);\n+\t\t} else {\n+\t\t\temit(ctx, ddivu, dst, src);\n+\t\t\temit(ctx, mflo, dst);\n+\t\t}\n+\t\tbreak;\n+\t/* dst = dst % src */\n+\tcase BPF_MOD:\n+\t\tif (cpu_has_mips64r6) {\n+\t\t\temit(ctx, dmodu, dst, dst, src);\n+\t\t} else {\n+\t\t\temit(ctx, ddivu, dst, src);\n+\t\t\temit(ctx, mfhi, dst);\n+\t\t}\n+\t\tbreak;\n+\tdefault:\n+\t\t/* Width-generic operations */\n+\t\temit_alu_r(ctx, dst, src, op);\n+\t}\n+\tclobber_reg(ctx, dst);\n+}\n+\n+/* Swap sub words in a register double word */\n+static void emit_swap_r64(struct jit_context *ctx, u8 dst, u8 mask, u32 bits)\n+{\n+\tu8 tmp = MIPS_R_T9;\n+\n+\temit(ctx, and, tmp, dst, mask);  /* tmp = dst & mask  */\n+\temit(ctx, dsll, tmp, tmp, bits); /* tmp = tmp << bits */\n+\temit(ctx, dsrl, dst, dst, bits); /* dst = dst >> bits */\n+\temit(ctx, and, dst, dst, mask);  /* dst = dst & mask  */\n+\temit(ctx, or, dst, dst, tmp);    /* dst = dst | tmp   */\n+}\n+\n+/* Swap bytes and truncate a register double word, word or half word */\n+static void emit_bswap_r64(struct jit_context *ctx, u8 dst, u32 width)\n+{\n+\tswitch (width) {\n+\t/* Swap bytes in a double word */\n+\tcase 64:\n+\t\tif (cpu_has_mips64r2 || cpu_has_mips64r6) {\n+\t\t\temit(ctx, dsbh, dst, dst);\n+\t\t\temit(ctx, dshd, dst, dst);\n+\t\t} else {\n+\t\t\tu8 t1 = MIPS_R_T6;\n+\t\t\tu8 t2 = MIPS_R_T7;\n+\n+\t\t\temit(ctx, dsll32, t2, dst, 0);  /* t2 = dst << 32    */\n+\t\t\temit(ctx, dsrl32, dst, dst, 0); /* dst = dst >> 32   */\n+\t\t\temit(ctx, or, dst, dst, t2);    /* dst = dst | t2    */\n+\n+\t\t\temit(ctx, ori, t2, MIPS_R_ZERO, 0xffff);\n+\t\t\temit(ctx, dsll32, t1, t2, 0);   /* t1 = t2 << 32     */\n+\t\t\temit(ctx, or, t1, t1, t2);      /* t1 = t1 | t2      */\n+\t\t\temit_swap_r64(ctx, dst, t1, 16);/* dst = swap16(dst) */\n+\n+\t\t\temit(ctx, lui, t2, 0xff);       /* t2 = 0x00ff0000   */\n+\t\t\temit(ctx, ori, t2, t2, 0xff);   /* t2 = t2 | 0x00ff  */\n+\t\t\temit(ctx, dsll32, t1, t2, 0);   /* t1 = t2 << 32     */\n+\t\t\temit(ctx, or, t1, t1, t2);      /* t1 = t1 | t2      */\n+\t\t\temit_swap_r64(ctx, dst, t1, 8); /* dst = swap8(dst)  */\n+\t\t}\n+\t\tbreak;\n+\t/* Swap bytes in a half word */\n+\t/* Swap bytes in a word */\n+\tcase 32:\n+\tcase 16:\n+\t\temit_sext(ctx, dst, dst);\n+\t\temit_bswap_r(ctx, dst, width);\n+\t\tif (cpu_has_mips64r2 || cpu_has_mips64r6)\n+\t\t\temit_zext(ctx, dst);\n+\t\tbreak;\n+\t}\n+\tclobber_reg(ctx, dst);\n+}\n+\n+/* Truncate a register double word, word or half word */\n+static void emit_trunc_r64(struct jit_context *ctx, u8 dst, u32 width)\n+{\n+\tswitch (width) {\n+\tcase 64:\n+\t\tbreak;\n+\t/* Zero-extend a word */\n+\tcase 32:\n+\t\temit_zext(ctx, dst);\n+\t\tbreak;\n+\t/* Zero-extend a half word */\n+\tcase 16:\n+\t\temit(ctx, andi, dst, dst, 0xffff);\n+\t\tbreak;\n+\t}\n+\tclobber_reg(ctx, dst);\n+}\n+\n+/* Load operation: dst = *(size*)(src + off) */\n+static void emit_ldx(struct jit_context *ctx, u8 dst, u8 src, s16 off, u8 size)\n+{\n+\tswitch (size) {\n+\t/* Load a byte */\n+\tcase BPF_B:\n+\t\temit(ctx, lbu, dst, off, src);\n+\t\tbreak;\n+\t/* Load a half word */\n+\tcase BPF_H:\n+\t\temit(ctx, lhu, dst, off, src);\n+\t\tbreak;\n+\t/* Load a word */\n+\tcase BPF_W:\n+\t\temit(ctx, lwu, dst, off, src);\n+\t\tbreak;\n+\t/* Load a double word */\n+\tcase BPF_DW:\n+\t\temit(ctx, ld, dst, off, src);\n+\t\tbreak;\n+\t}\n+\tclobber_reg(ctx, dst);\n+}\n+\n+/* Store operation: *(size *)(dst + off) = src */\n+static void emit_stx(struct jit_context *ctx, u8 dst, u8 src, s16 off, u8 size)\n+{\n+\tswitch (size) {\n+\t/* Store a byte */\n+\tcase BPF_B:\n+\t\temit(ctx, sb, src, off, dst);\n+\t\tbreak;\n+\t/* Store a half word */\n+\tcase BPF_H:\n+\t\temit(ctx, sh, src, off, dst);\n+\t\tbreak;\n+\t/* Store a word */\n+\tcase BPF_W:\n+\t\temit(ctx, sw, src, off, dst);\n+\t\tbreak;\n+\t/* Store a double word */\n+\tcase BPF_DW:\n+\t\temit(ctx, sd, src, off, dst);\n+\t\tbreak;\n+\t}\n+}\n+\n+/* Atomic read-modify-write */\n+static void emit_atomic_r64(struct jit_context *ctx,\n+\t\t\t    u8 dst, u8 src, s16 off, u8 code)\n+{\n+\tu8 t1 = MIPS_R_T6;\n+\tu8 t2 = MIPS_R_T7;\n+\n+\temit(ctx, lld, t1, off, dst);\n+\tswitch (code) {\n+\tcase BPF_ADD:\n+\t\temit(ctx, daddu, t2, t1, src);\n+\t\tbreak;\n+\tcase BPF_AND:\n+\t\temit(ctx, and, t2, t1, src);\n+\t\tbreak;\n+\tcase BPF_OR:\n+\t\temit(ctx, or, t2, t1, src);\n+\t\tbreak;\n+\tcase BPF_XOR:\n+\t\temit(ctx, xor, t2, t1, src);\n+\t\tbreak;\n+\t}\n+\temit(ctx, scd, t2, off, dst);\n+\temit(ctx, beqz, t2, -16);\n+\temit(ctx, nop); /* Delay slot */\n+}\n+\n+/* Function call */\n+static int emit_call(struct jit_context *ctx, const struct bpf_insn *insn)\n+{\n+\tu8 zx = bpf2mips64[JIT_REG_ZX];\n+\tu8 tmp = MIPS_R_T6;\n+\tbool fixed;\n+\tu64 addr;\n+\n+\t/* Decode the call address */\n+\tif (bpf_jit_get_func_addr(ctx->program, insn, false,\n+\t\t\t\t  &addr, &fixed) < 0)\n+\t\treturn -1;\n+\tif (!fixed)\n+\t\treturn -1;\n+\n+\t/* Push caller-saved registers on stack */\n+\tpush_regs(ctx, ctx->clobbered & JIT_CALLER_REGS, 0, 0);\n+\n+\t/* Emit function call */\n+\temit_mov_i64(ctx, tmp, addr);\n+\temit(ctx, jalr, MIPS_R_RA, tmp);\n+\temit(ctx, nop); /* Delay slot */\n+\n+\t/* Restore caller-saved registers */\n+\tpop_regs(ctx, ctx->clobbered & JIT_CALLER_REGS, 0, 0);\n+\n+\t/* Re-initialize the JIT zero-extension register if accessed */\n+\tif (ctx->accessed & BIT(JIT_REG_ZX)) {\n+\t\temit(ctx, daddiu, zx, MIPS_R_ZERO, -1);\n+\t\temit(ctx, dsrl32, zx, zx, 0);\n+\t}\n+\n+\tclobber_reg(ctx, MIPS_R_RA);\n+\tclobber_reg(ctx, MIPS_R_V0);\n+\tclobber_reg(ctx, MIPS_R_V1);\n+\treturn 0;\n+}\n+\n+/* Function tail call */\n+static int emit_tail_call(struct jit_context *ctx)\n+{\n+\tu8 ary = bpf2mips64[BPF_REG_2];\n+\tu8 ind = bpf2mips64[BPF_REG_3];\n+\tu8 tcc = bpf2mips64[JIT_REG_TC];\n+\tu8 tmp = MIPS_R_T6;\n+\tint off;\n+\n+\t/*\n+\t * Tail call:\n+\t * eBPF R1 - function argument (context ptr), passed in a0-a1\n+\t * eBPF R2 - ptr to object with array of function entry points\n+\t * eBPF R3 - array index of function to be called\n+\t */\n+\n+\t/* if (ind >= ary->map.max_entries) goto out */\n+\toff = offsetof(struct bpf_array, map.max_entries);\n+\tif (off > 0x7fff)\n+\t\treturn -1;\n+\temit(ctx, lwu, tmp, off, ary);            /* tmp = ary->map.max_entrs*/\n+\temit(ctx, sltu, tmp, ind, tmp);           /* tmp = ind < t1          */\n+\temit(ctx, beqz, tmp, get_offset(ctx, 1)); /* PC += off(1) if tmp == 0*/\n+\n+\t/* if (--TCC < 0) goto out */\n+\temit(ctx, daddiu, tcc, tcc, -1);          /* tcc-- (delay slot)      */\n+\temit(ctx, bltz, tcc, get_offset(ctx, 1)); /* PC += off(1) if tcc < 0 */\n+\t\t\t\t\t\t  /* (next insn delay slot)  */\n+\t/* prog = ary->ptrs[ind] */\n+\toff = offsetof(struct bpf_array, ptrs);\n+\tif (off > 0x7fff)\n+\t\treturn -1;\n+\temit(ctx, dsll, tmp, ind, 3);             /* tmp = ind << 3          */\n+\temit(ctx, daddu, tmp, tmp, ary);          /* tmp += ary              */\n+\temit(ctx, ld, tmp, off, tmp);             /* tmp = *(tmp + off)      */\n+\n+\t/* if (prog == 0) goto out */\n+\temit(ctx, beqz, tmp, get_offset(ctx, 1)); /* PC += off(1) if tmp == 0*/\n+\temit(ctx, nop);                           /* Delay slot              */\n+\n+\t/* func = prog->bpf_func + 8 (prologue skip offset) */\n+\toff = offsetof(struct bpf_prog, bpf_func);\n+\tif (off > 0x7fff)\n+\t\treturn -1;\n+\temit(ctx, ld, tmp, off, tmp);                /* tmp = *(tmp + off)   */\n+\temit(ctx, daddiu, tmp, tmp, JIT_TCALL_SKIP); /* tmp += skip (4)      */\n+\n+\t/* goto func */\n+\tbuild_epilogue(ctx, tmp);\n+\taccess_reg(ctx, JIT_REG_TC);\n+\treturn 0;\n+}\n+\n+/*\n+ * Stack frame layout for a JITed program (stack grows down).\n+ *\n+ * Higher address  : Previous stack frame      :\n+ *                 +===========================+  <--- MIPS sp before call\n+ *                 | Callee-saved registers,   |\n+ *                 | including RA and FP       |\n+ *                 +---------------------------+  <--- eBPF FP (MIPS fp)\n+ *                 | Local eBPF variables      |\n+ *                 | allocated by program      |\n+ *                 +---------------------------+\n+ *                 | Reserved for caller-saved |\n+ *                 | registers                 |\n+ * Lower address   +===========================+  <--- MIPS sp\n+ */\n+\n+/* Build program prologue to set up the stack and registers */\n+void build_prologue(struct jit_context *ctx)\n+{\n+\tu8 fp = bpf2mips64[BPF_REG_FP];\n+\tu8 tc = bpf2mips64[JIT_REG_TC];\n+\tu8 zx = bpf2mips64[JIT_REG_ZX];\n+\tint stack, saved, locals, reserved;\n+\n+\t/*\n+\t * The first instruction initializes the tail call count register.\n+\t * On a tail call, the calling function jumps into the prologue\n+\t * after this instruction.\n+\t */\n+\temit(ctx, addiu, tc, MIPS_R_ZERO, min(MAX_TAIL_CALL_CNT + 1, 0xffff));\n+\n+\t/* === Entry-point for tail calls === */\n+\n+\t/*\n+\t * If the eBPF frame pointer and tail call count registers were\n+\t * accessed they must be preserved. Mark them as clobbered here\n+\t * to save and restore them on the stack as needed.\n+\t */\n+\tif (ctx->accessed & BIT(BPF_REG_FP))\n+\t\tclobber_reg(ctx, fp);\n+\tif (ctx->accessed & BIT(JIT_REG_TC))\n+\t\tclobber_reg(ctx, tc);\n+\tif (ctx->accessed & BIT(JIT_REG_ZX))\n+\t\tclobber_reg(ctx, zx);\n+\n+\t/* Compute the stack space needed for callee-saved registers */\n+\tsaved = hweight32(ctx->clobbered & JIT_CALLEE_REGS) * sizeof(u64);\n+\tsaved = ALIGN(saved, MIPS_STACK_ALIGNMENT);\n+\n+\t/* Stack space used by eBPF program local data */\n+\tlocals = ALIGN(ctx->program->aux->stack_depth, MIPS_STACK_ALIGNMENT);\n+\n+\t/*\n+\t * If we are emitting function calls, reserve extra stack space for\n+\t * caller-saved registers needed by the JIT. The required space is\n+\t * computed automatically during resource usage discovery (pass 1).\n+\t */\n+\treserved = ctx->stack_used;\n+\n+\t/* Allocate the stack frame */\n+\tstack = ALIGN(saved + locals + reserved, MIPS_STACK_ALIGNMENT);\n+\tif (stack)\n+\t\temit(ctx, daddiu, MIPS_R_SP, MIPS_R_SP, -stack);\n+\n+\t/* Store callee-saved registers on stack */\n+\tpush_regs(ctx, ctx->clobbered & JIT_CALLEE_REGS, 0, stack - saved);\n+\n+\t/* Initialize the eBPF frame pointer if accessed */\n+\tif (ctx->accessed & BIT(BPF_REG_FP))\n+\t\temit(ctx, daddiu, fp, MIPS_R_SP, stack - saved);\n+\n+\t/* Initialize the ePF JIT zero-extension register if accessed */\n+\tif (ctx->accessed & BIT(JIT_REG_ZX)) {\n+\t\temit(ctx, daddiu, zx, MIPS_R_ZERO, -1);\n+\t\temit(ctx, dsrl32, zx, zx, 0);\n+\t}\n+\n+\tctx->saved_size = saved;\n+\tctx->stack_size = stack;\n+}\n+\n+/* Build the program epilogue to restore the stack and registers */\n+void build_epilogue(struct jit_context *ctx, int dest_reg)\n+{\n+\t/* Restore callee-saved registers from stack */\n+\tpop_regs(ctx, ctx->clobbered & JIT_CALLEE_REGS, 0,\n+\t\t ctx->stack_size - ctx->saved_size);\n+\n+\t/* Release the stack frame */\n+\tif (ctx->stack_size)\n+\t\temit(ctx, daddiu, MIPS_R_SP, MIPS_R_SP, ctx->stack_size);\n+\n+\t/* Jump to return address and sign-extend the 32-bit return value */\n+\temit(ctx, jr, dest_reg);\n+\temit(ctx, sll, MIPS_R_V0, MIPS_R_V0, 0); /* Delay slot */\n+}\n+\n+/* Build one eBPF instruction */\n+int build_insn(const struct bpf_insn *insn, struct jit_context *ctx)\n+{\n+\tu8 dst = bpf2mips64[insn->dst_reg];\n+\tu8 src = bpf2mips64[insn->src_reg];\n+\tu8 code = insn->code;\n+\ts16 off = insn->off;\n+\ts32 imm = insn->imm;\n+\ts32 val, rel;\n+\tu8 alu, jmp;\n+\n+\tswitch (code) {\n+\t/* ALU operations */\n+\t/* dst = imm */\n+\tcase BPF_ALU | BPF_MOV | BPF_K:\n+\t\temit_mov_i(ctx, dst, imm);\n+\t\temit_zext_ver(ctx, dst);\n+\t\tbreak;\n+\t/* dst = src */\n+\tcase BPF_ALU | BPF_MOV | BPF_X:\n+\t\tif (imm == 1) {\n+\t\t\t/* Special mov32 for zext */\n+\t\t\temit_zext(ctx, dst);\n+\t\t} else {\n+\t\t\temit_mov_r(ctx, dst, src);\n+\t\t\temit_zext_ver(ctx, dst);\n+\t\t}\n+\t\tbreak;\n+\t/* dst = -dst */\n+\tcase BPF_ALU | BPF_NEG:\n+\t\temit_sext(ctx, dst, dst);\n+\t\temit_alu_i(ctx, dst, 0, BPF_NEG);\n+\t\temit_zext_ver(ctx, dst);\n+\t\tbreak;\n+\t/* dst = dst & imm */\n+\t/* dst = dst | imm */\n+\t/* dst = dst ^ imm */\n+\t/* dst = dst << imm */\n+\tcase BPF_ALU | BPF_OR | BPF_K:\n+\tcase BPF_ALU | BPF_AND | BPF_K:\n+\tcase BPF_ALU | BPF_XOR | BPF_K:\n+\tcase BPF_ALU | BPF_LSH | BPF_K:\n+\t\tif (!valid_alu_i(BPF_OP(code), imm)) {\n+\t\t\temit_mov_i(ctx, MIPS_R_T4, imm);\n+\t\t\temit_alu_r(ctx, dst, MIPS_R_T4, BPF_OP(code));\n+\t\t} else if (rewrite_alu_i(BPF_OP(code), imm, &alu, &val)) {\n+\t\t\temit_alu_i(ctx, dst, val, alu);\n+\t\t}\n+\t\temit_zext_ver(ctx, dst);\n+\t\tbreak;\n+\t/* dst = dst >> imm */\n+\t/* dst = dst >> imm (arithmetic) */\n+\t/* dst = dst + imm */\n+\t/* dst = dst - imm */\n+\t/* dst = dst * imm */\n+\t/* dst = dst / imm */\n+\t/* dst = dst % imm */\n+\tcase BPF_ALU | BPF_RSH | BPF_K:\n+\tcase BPF_ALU | BPF_ARSH | BPF_K:\n+\tcase BPF_ALU | BPF_ADD | BPF_K:\n+\tcase BPF_ALU | BPF_SUB | BPF_K:\n+\tcase BPF_ALU | BPF_MUL | BPF_K:\n+\tcase BPF_ALU | BPF_DIV | BPF_K:\n+\tcase BPF_ALU | BPF_MOD | BPF_K:\n+\t\tif (!valid_alu_i(BPF_OP(code), imm)) {\n+\t\t\temit_sext(ctx, dst, dst);\n+\t\t\temit_mov_i(ctx, MIPS_R_T4, imm);\n+\t\t\temit_alu_r(ctx, dst, MIPS_R_T4, BPF_OP(code));\n+\t\t} else if (rewrite_alu_i(BPF_OP(code), imm, &alu, &val)) {\n+\t\t\temit_sext(ctx, dst, dst);\n+\t\t\temit_alu_i(ctx, dst, val, alu);\n+\t\t}\n+\t\temit_zext_ver(ctx, dst);\n+\t\tbreak;\n+\t/* dst = dst & src */\n+\t/* dst = dst | src */\n+\t/* dst = dst ^ src */\n+\t/* dst = dst << src */\n+\tcase BPF_ALU | BPF_AND | BPF_X:\n+\tcase BPF_ALU | BPF_OR | BPF_X:\n+\tcase BPF_ALU | BPF_XOR | BPF_X:\n+\tcase BPF_ALU | BPF_LSH | BPF_X:\n+\t\temit_alu_r(ctx, dst, src, BPF_OP(code));\n+\t\temit_zext_ver(ctx, dst);\n+\t\tbreak;\n+\t/* dst = dst >> src */\n+\t/* dst = dst >> src (arithmetic) */\n+\t/* dst = dst + src */\n+\t/* dst = dst - src */\n+\t/* dst = dst * src */\n+\t/* dst = dst / src */\n+\t/* dst = dst % src */\n+\tcase BPF_ALU | BPF_RSH | BPF_X:\n+\tcase BPF_ALU | BPF_ARSH | BPF_X:\n+\tcase BPF_ALU | BPF_ADD | BPF_X:\n+\tcase BPF_ALU | BPF_SUB | BPF_X:\n+\tcase BPF_ALU | BPF_MUL | BPF_X:\n+\tcase BPF_ALU | BPF_DIV | BPF_X:\n+\tcase BPF_ALU | BPF_MOD | BPF_X:\n+\t\temit_sext(ctx, dst, dst);\n+\t\temit_sext(ctx, MIPS_R_T4, src);\n+\t\temit_alu_r(ctx, dst, MIPS_R_T4, BPF_OP(code));\n+\t\temit_zext_ver(ctx, dst);\n+\t\tbreak;\n+\t/* dst = imm (64-bit) */\n+\tcase BPF_ALU64 | BPF_MOV | BPF_K:\n+\t\temit_mov_i(ctx, dst, imm);\n+\t\tbreak;\n+\t/* dst = src (64-bit) */\n+\tcase BPF_ALU64 | BPF_MOV | BPF_X:\n+\t\temit_mov_r(ctx, dst, src);\n+\t\tbreak;\n+\t/* dst = -dst (64-bit) */\n+\tcase BPF_ALU64 | BPF_NEG:\n+\t\temit_alu_i64(ctx, dst, 0, BPF_NEG);\n+\t\tbreak;\n+\t/* dst = dst & imm (64-bit) */\n+\t/* dst = dst | imm (64-bit) */\n+\t/* dst = dst ^ imm (64-bit) */\n+\t/* dst = dst << imm (64-bit) */\n+\t/* dst = dst >> imm (64-bit) */\n+\t/* dst = dst >> imm ((64-bit, arithmetic) */\n+\t/* dst = dst + imm (64-bit) */\n+\t/* dst = dst - imm (64-bit) */\n+\t/* dst = dst * imm (64-bit) */\n+\t/* dst = dst / imm (64-bit) */\n+\t/* dst = dst % imm (64-bit) */\n+\tcase BPF_ALU64 | BPF_AND | BPF_K:\n+\tcase BPF_ALU64 | BPF_OR | BPF_K:\n+\tcase BPF_ALU64 | BPF_XOR | BPF_K:\n+\tcase BPF_ALU64 | BPF_LSH | BPF_K:\n+\tcase BPF_ALU64 | BPF_RSH | BPF_K:\n+\tcase BPF_ALU64 | BPF_ARSH | BPF_K:\n+\tcase BPF_ALU64 | BPF_ADD | BPF_K:\n+\tcase BPF_ALU64 | BPF_SUB | BPF_K:\n+\tcase BPF_ALU64 | BPF_MUL | BPF_K:\n+\tcase BPF_ALU64 | BPF_DIV | BPF_K:\n+\tcase BPF_ALU64 | BPF_MOD | BPF_K:\n+\t\tif (!valid_alu_i(BPF_OP(code), imm)) {\n+\t\t\temit_mov_i(ctx, MIPS_R_T4, imm);\n+\t\t\temit_alu_r64(ctx, dst, MIPS_R_T4, BPF_OP(code));\n+\t\t} else if (rewrite_alu_i(BPF_OP(code), imm, &alu, &val)) {\n+\t\t\temit_alu_i64(ctx, dst, val, alu);\n+\t\t}\n+\t\tbreak;\n+\t/* dst = dst & src (64-bit) */\n+\t/* dst = dst | src (64-bit) */\n+\t/* dst = dst ^ src (64-bit) */\n+\t/* dst = dst << src (64-bit) */\n+\t/* dst = dst >> src (64-bit) */\n+\t/* dst = dst >> src (64-bit, arithmetic) */\n+\t/* dst = dst + src (64-bit) */\n+\t/* dst = dst - src (64-bit) */\n+\t/* dst = dst * src (64-bit) */\n+\t/* dst = dst / src (64-bit) */\n+\t/* dst = dst % src (64-bit) */\n+\tcase BPF_ALU64 | BPF_AND | BPF_X:\n+\tcase BPF_ALU64 | BPF_OR | BPF_X:\n+\tcase BPF_ALU64 | BPF_XOR | BPF_X:\n+\tcase BPF_ALU64 | BPF_LSH | BPF_X:\n+\tcase BPF_ALU64 | BPF_RSH | BPF_X:\n+\tcase BPF_ALU64 | BPF_ARSH | BPF_X:\n+\tcase BPF_ALU64 | BPF_ADD | BPF_X:\n+\tcase BPF_ALU64 | BPF_SUB | BPF_X:\n+\tcase BPF_ALU64 | BPF_MUL | BPF_X:\n+\tcase BPF_ALU64 | BPF_DIV | BPF_X:\n+\tcase BPF_ALU64 | BPF_MOD | BPF_X:\n+\t\temit_alu_r64(ctx, dst, src, BPF_OP(code));\n+\t\tbreak;\n+\t/* dst = htole(dst) */\n+\t/* dst = htobe(dst) */\n+\tcase BPF_ALU | BPF_END | BPF_FROM_LE:\n+\tcase BPF_ALU | BPF_END | BPF_FROM_BE:\n+\t\tif (BPF_SRC(code) ==\n+#ifdef __BIG_ENDIAN\n+\t\t    BPF_FROM_LE\n+#else\n+\t\t    BPF_FROM_BE\n+#endif\n+\t\t    )\n+\t\t\temit_bswap_r64(ctx, dst, imm);\n+\t\telse\n+\t\t\temit_trunc_r64(ctx, dst, imm);\n+\t\tbreak;\n+\t/* dst = imm64 */\n+\tcase BPF_LD | BPF_IMM | BPF_DW:\n+\t\temit_mov_i64(ctx, dst, (u32)imm | ((u64)insn[1].imm << 32));\n+\t\treturn 1;\n+\t/* LDX: dst = *(size *)(src + off) */\n+\tcase BPF_LDX | BPF_MEM | BPF_W:\n+\tcase BPF_LDX | BPF_MEM | BPF_H:\n+\tcase BPF_LDX | BPF_MEM | BPF_B:\n+\tcase BPF_LDX | BPF_MEM | BPF_DW:\n+\t\temit_ldx(ctx, dst, src, off, BPF_SIZE(code));\n+\t\tbreak;\n+\t/* ST: *(size *)(dst + off) = imm */\n+\tcase BPF_ST | BPF_MEM | BPF_W:\n+\tcase BPF_ST | BPF_MEM | BPF_H:\n+\tcase BPF_ST | BPF_MEM | BPF_B:\n+\tcase BPF_ST | BPF_MEM | BPF_DW:\n+\t\temit_mov_i(ctx, MIPS_R_T4, imm);\n+\t\temit_stx(ctx, dst, MIPS_R_T4, off, BPF_SIZE(code));\n+\t\tbreak;\n+\t/* STX: *(size *)(dst + off) = src */\n+\tcase BPF_STX | BPF_MEM | BPF_W:\n+\tcase BPF_STX | BPF_MEM | BPF_H:\n+\tcase BPF_STX | BPF_MEM | BPF_B:\n+\tcase BPF_STX | BPF_MEM | BPF_DW:\n+\t\temit_stx(ctx, dst, src, off, BPF_SIZE(code));\n+\t\tbreak;\n+\t/* Speculation barrier */\n+\tcase BPF_ST | BPF_NOSPEC:\n+\t\tbreak;\n+\t/* Atomics */\n+\tcase BPF_STX | BPF_XADD | BPF_W:\n+\tcase BPF_STX | BPF_XADD | BPF_DW:\n+\t\tswitch (imm) {\n+\t\tcase BPF_ADD:\n+\t\tcase BPF_AND:\n+\t\tcase BPF_OR:\n+\t\tcase BPF_XOR:\n+\t\t\tif (BPF_SIZE(code) == BPF_DW) {\n+\t\t\t\temit_atomic_r64(ctx, dst, src, off, imm);\n+\t\t\t} else { /* 32-bit, no fetch */\n+\t\t\t\temit_sext(ctx, MIPS_R_T4, src);\n+\t\t\t\temit_atomic_r(ctx, dst, MIPS_R_T4, off, imm);\n+\t\t\t}\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tgoto notyet;\n+\t\t}\n+\t\tbreak;\n+\t/* PC += off if dst == src */\n+\t/* PC += off if dst != src */\n+\t/* PC += off if dst & src */\n+\t/* PC += off if dst > src */\n+\t/* PC += off if dst >= src */\n+\t/* PC += off if dst < src */\n+\t/* PC += off if dst <= src */\n+\t/* PC += off if dst > src (signed) */\n+\t/* PC += off if dst >= src (signed) */\n+\t/* PC += off if dst < src (signed) */\n+\t/* PC += off if dst <= src (signed) */\n+\tcase BPF_JMP32 | BPF_JEQ | BPF_X:\n+\tcase BPF_JMP32 | BPF_JNE | BPF_X:\n+\tcase BPF_JMP32 | BPF_JSET | BPF_X:\n+\tcase BPF_JMP32 | BPF_JGT | BPF_X:\n+\tcase BPF_JMP32 | BPF_JGE | BPF_X:\n+\tcase BPF_JMP32 | BPF_JLT | BPF_X:\n+\tcase BPF_JMP32 | BPF_JLE | BPF_X:\n+\tcase BPF_JMP32 | BPF_JSGT | BPF_X:\n+\tcase BPF_JMP32 | BPF_JSGE | BPF_X:\n+\tcase BPF_JMP32 | BPF_JSLT | BPF_X:\n+\tcase BPF_JMP32 | BPF_JSLE | BPF_X:\n+\t\tif (off == 0)\n+\t\t\tbreak;\n+\t\tsetup_jmp_r(ctx, dst == src, BPF_OP(code), off, &jmp, &rel);\n+\t\temit_sext(ctx, MIPS_R_T4, dst); /* Sign-extended dst */\n+\t\temit_sext(ctx, MIPS_R_T5, src); /* Sign-extended src */\n+\t\temit_jmp_r(ctx, MIPS_R_T4, MIPS_R_T5, rel, jmp);\n+\t\tif (finish_jmp(ctx, jmp, off) < 0)\n+\t\t\tgoto toofar;\n+\t\tbreak;\n+\t/* PC += off if dst == imm */\n+\t/* PC += off if dst != imm */\n+\t/* PC += off if dst & imm */\n+\t/* PC += off if dst > imm */\n+\t/* PC += off if dst >= imm */\n+\t/* PC += off if dst < imm */\n+\t/* PC += off if dst <= imm */\n+\t/* PC += off if dst > imm (signed) */\n+\t/* PC += off if dst >= imm (signed) */\n+\t/* PC += off if dst < imm (signed) */\n+\t/* PC += off if dst <= imm (signed) */\n+\tcase BPF_JMP32 | BPF_JEQ | BPF_K:\n+\tcase BPF_JMP32 | BPF_JNE | BPF_K:\n+\tcase BPF_JMP32 | BPF_JSET | BPF_K:\n+\tcase BPF_JMP32 | BPF_JGT | BPF_K:\n+\tcase BPF_JMP32 | BPF_JGE | BPF_K:\n+\tcase BPF_JMP32 | BPF_JLT | BPF_K:\n+\tcase BPF_JMP32 | BPF_JLE | BPF_K:\n+\tcase BPF_JMP32 | BPF_JSGT | BPF_K:\n+\tcase BPF_JMP32 | BPF_JSGE | BPF_K:\n+\tcase BPF_JMP32 | BPF_JSLT | BPF_K:\n+\tcase BPF_JMP32 | BPF_JSLE | BPF_K:\n+\t\tif (off == 0)\n+\t\t\tbreak;\n+\t\tsetup_jmp_i(ctx, imm, 32, BPF_OP(code), off, &jmp, &rel);\n+\t\temit_sext(ctx, MIPS_R_T4, dst); /* Sign-extended dst */\n+\t\tif (valid_jmp_i(jmp, imm)) {\n+\t\t\temit_jmp_i(ctx, MIPS_R_T4, imm, rel, jmp);\n+\t\t} else {\n+\t\t\t/* Move large immediate to register, sign-extended */\n+\t\t\temit_mov_i(ctx, MIPS_R_T5, imm);\n+\t\t\temit_jmp_r(ctx, MIPS_R_T4, MIPS_R_T5, rel, jmp);\n+\t\t}\n+\t\tif (finish_jmp(ctx, jmp, off) < 0)\n+\t\t\tgoto toofar;\n+\t\tbreak;\n+\t/* PC += off if dst == src */\n+\t/* PC += off if dst != src */\n+\t/* PC += off if dst & src */\n+\t/* PC += off if dst > src */\n+\t/* PC += off if dst >= src */\n+\t/* PC += off if dst < src */\n+\t/* PC += off if dst <= src */\n+\t/* PC += off if dst > src (signed) */\n+\t/* PC += off if dst >= src (signed) */\n+\t/* PC += off if dst < src (signed) */\n+\t/* PC += off if dst <= src (signed) */\n+\tcase BPF_JMP | BPF_JEQ | BPF_X:\n+\tcase BPF_JMP | BPF_JNE | BPF_X:\n+\tcase BPF_JMP | BPF_JSET | BPF_X:\n+\tcase BPF_JMP | BPF_JGT | BPF_X:\n+\tcase BPF_JMP | BPF_JGE | BPF_X:\n+\tcase BPF_JMP | BPF_JLT | BPF_X:\n+\tcase BPF_JMP | BPF_JLE | BPF_X:\n+\tcase BPF_JMP | BPF_JSGT | BPF_X:\n+\tcase BPF_JMP | BPF_JSGE | BPF_X:\n+\tcase BPF_JMP | BPF_JSLT | BPF_X:\n+\tcase BPF_JMP | BPF_JSLE | BPF_X:\n+\t\tif (off == 0)\n+\t\t\tbreak;\n+\t\tsetup_jmp_r(ctx, dst == src, BPF_OP(code), off, &jmp, &rel);\n+\t\temit_jmp_r(ctx, dst, src, rel, jmp);\n+\t\tif (finish_jmp(ctx, jmp, off) < 0)\n+\t\t\tgoto toofar;\n+\t\tbreak;\n+\t/* PC += off if dst == imm */\n+\t/* PC += off if dst != imm */\n+\t/* PC += off if dst & imm */\n+\t/* PC += off if dst > imm */\n+\t/* PC += off if dst >= imm */\n+\t/* PC += off if dst < imm */\n+\t/* PC += off if dst <= imm */\n+\t/* PC += off if dst > imm (signed) */\n+\t/* PC += off if dst >= imm (signed) */\n+\t/* PC += off if dst < imm (signed) */\n+\t/* PC += off if dst <= imm (signed) */\n+\tcase BPF_JMP | BPF_JEQ | BPF_K:\n+\tcase BPF_JMP | BPF_JNE | BPF_K:\n+\tcase BPF_JMP | BPF_JSET | BPF_K:\n+\tcase BPF_JMP | BPF_JGT | BPF_K:\n+\tcase BPF_JMP | BPF_JGE | BPF_K:\n+\tcase BPF_JMP | BPF_JLT | BPF_K:\n+\tcase BPF_JMP | BPF_JLE | BPF_K:\n+\tcase BPF_JMP | BPF_JSGT | BPF_K:\n+\tcase BPF_JMP | BPF_JSGE | BPF_K:\n+\tcase BPF_JMP | BPF_JSLT | BPF_K:\n+\tcase BPF_JMP | BPF_JSLE | BPF_K:\n+\t\tif (off == 0)\n+\t\t\tbreak;\n+\t\tsetup_jmp_i(ctx, imm, 64, BPF_OP(code), off, &jmp, &rel);\n+\t\tif (valid_jmp_i(jmp, imm)) {\n+\t\t\temit_jmp_i(ctx, dst, imm, rel, jmp);\n+\t\t} else {\n+\t\t\t/* Move large immediate to register */\n+\t\t\temit_mov_i(ctx, MIPS_R_T4, imm);\n+\t\t\temit_jmp_r(ctx, dst, MIPS_R_T4, rel, jmp);\n+\t\t}\n+\t\tif (finish_jmp(ctx, jmp, off) < 0)\n+\t\t\tgoto toofar;\n+\t\tbreak;\n+\t/* PC += off */\n+\tcase BPF_JMP | BPF_JA:\n+\t\tif (off == 0)\n+\t\t\tbreak;\n+\t\tif (emit_ja(ctx, off) < 0)\n+\t\t\tgoto toofar;\n+\t\tbreak;\n+\t/* Tail call */\n+\tcase BPF_JMP | BPF_TAIL_CALL:\n+\t\tif (emit_tail_call(ctx) < 0)\n+\t\t\tgoto invalid;\n+\t\tbreak;\n+\t/* Function call */\n+\tcase BPF_JMP | BPF_CALL:\n+\t\tif (emit_call(ctx, insn) < 0)\n+\t\t\tgoto invalid;\n+\t\tbreak;\n+\t/* Function return */\n+\tcase BPF_JMP | BPF_EXIT:\n+\t\t/*\n+\t\t * Optimization: when last instruction is EXIT\n+\t\t * simply continue to epilogue.\n+\t\t */\n+\t\tif (ctx->bpf_index == ctx->program->len - 1)\n+\t\t\tbreak;\n+\t\tif (emit_exit(ctx) < 0)\n+\t\t\tgoto toofar;\n+\t\tbreak;\n+\n+\tdefault:\n+invalid:\n+\t\tpr_err_once(\"unknown opcode %02x\\n\", code);\n+\t\treturn -EINVAL;\n+notyet:\n+\t\tpr_info_once(\"*** NOT YET: opcode %02x ***\\n\", code);\n+\t\treturn -EFAULT;\n+toofar:\n+\t\tpr_info_once(\"*** TOO FAR: jump at %u opcode %02x ***\\n\",\n+\t\t\t     ctx->bpf_index, code);\n+\t\treturn -E2BIG;\n+\t}\n+\treturn 0;\n+}\n"
  },
  {
    "path": "target/linux/generic/backport-5.15/050-v5.16-04-mips-bpf-Add-JIT-workarounds-for-CPU-errata.patch",
    "content": "From: Johan Almbladh <johan.almbladh@anyfinetworks.com>\nDate: Tue, 5 Oct 2021 18:54:06 +0200\nSubject: [PATCH] mips: bpf: Add JIT workarounds for CPU errata\n\nThis patch adds workarounds for the following CPU errata to the MIPS\neBPF JIT, if enabled in the kernel configuration.\n\n  - R10000 ll/sc weak ordering\n  - Loongson-3 ll/sc weak ordering\n  - Loongson-2F jump hang\n\nThe Loongson-2F nop errata is implemented in uasm, which the JIT uses,\nso no additional mitigations are needed for that.\n\nSigned-off-by: Johan Almbladh <johan.almbladh@anyfinetworks.com>\nReviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>\n---\n\n--- a/arch/mips/net/bpf_jit_comp.c\n+++ b/arch/mips/net/bpf_jit_comp.c\n@@ -404,6 +404,7 @@ void emit_alu_r(struct jit_context *ctx,\n /* Atomic read-modify-write (32-bit) */\n void emit_atomic_r(struct jit_context *ctx, u8 dst, u8 src, s16 off, u8 code)\n {\n+\tLLSC_sync(ctx);\n \temit(ctx, ll, MIPS_R_T9, off, dst);\n \tswitch (code) {\n \tcase BPF_ADD:\n@@ -420,18 +421,19 @@ void emit_atomic_r(struct jit_context *c\n \t\tbreak;\n \t}\n \temit(ctx, sc, MIPS_R_T8, off, dst);\n-\temit(ctx, beqz, MIPS_R_T8, -16);\n+\temit(ctx, LLSC_beqz, MIPS_R_T8, -16 - LLSC_offset);\n \temit(ctx, nop); /* Delay slot */\n }\n \n /* Atomic compare-and-exchange (32-bit) */\n void emit_cmpxchg_r(struct jit_context *ctx, u8 dst, u8 src, u8 res, s16 off)\n {\n+\tLLSC_sync(ctx);\n \temit(ctx, ll, MIPS_R_T9, off, dst);\n \temit(ctx, bne, MIPS_R_T9, res, 12);\n \temit(ctx, move, MIPS_R_T8, src);     /* Delay slot */\n \temit(ctx, sc, MIPS_R_T8, off, dst);\n-\temit(ctx, beqz, MIPS_R_T8, -20);\n+\temit(ctx, LLSC_beqz, MIPS_R_T8, -20 - LLSC_offset);\n \temit(ctx, move, res, MIPS_R_T9);     /* Delay slot */\n \tclobber_reg(ctx, res);\n }\n--- a/arch/mips/net/bpf_jit_comp.h\n+++ b/arch/mips/net/bpf_jit_comp.h\n@@ -87,7 +87,7 @@ struct jit_context {\n };\n \n /* Emit the instruction if the JIT memory space has been allocated */\n-#define emit(ctx, func, ...)\t\t\t\t\t\\\n+#define __emit(ctx, func, ...)\t\t\t\t\t\\\n do {\t\t\t\t\t\t\t\t\\\n \tif ((ctx)->target != NULL) {\t\t\t\t\\\n \t\tu32 *p = &(ctx)->target[ctx->jit_index];\t\\\n@@ -95,6 +95,30 @@ do {\t\t\t\t\t\t\t\t\\\n \t}\t\t\t\t\t\t\t\\\n \t(ctx)->jit_index++;\t\t\t\t\t\\\n } while (0)\n+#define emit(...) __emit(__VA_ARGS__)\n+\n+/* Workaround for R10000 ll/sc errata */\n+#ifdef CONFIG_WAR_R10000\n+#define LLSC_beqz\tbeqzl\n+#else\n+#define LLSC_beqz\tbeqz\n+#endif\n+\n+/* Workaround for Loongson-3 ll/sc errata */\n+#ifdef CONFIG_CPU_LOONGSON3_WORKAROUNDS\n+#define LLSC_sync(ctx)\temit(ctx, sync, 0)\n+#define LLSC_offset\t4\n+#else\n+#define LLSC_sync(ctx)\n+#define LLSC_offset\t0\n+#endif\n+\n+/* Workaround for Loongson-2F jump errata */\n+#ifdef CONFIG_CPU_JUMP_WORKAROUNDS\n+#define JALR_MASK\t0xffffffffcfffffffULL\n+#else\n+#define JALR_MASK\t(~0ULL)\n+#endif\n \n /*\n  * Mark a BPF register as accessed, it needs to be\n--- a/arch/mips/net/bpf_jit_comp64.c\n+++ b/arch/mips/net/bpf_jit_comp64.c\n@@ -375,6 +375,7 @@ static void emit_atomic_r64(struct jit_c\n \tu8 t1 = MIPS_R_T6;\n \tu8 t2 = MIPS_R_T7;\n \n+\tLLSC_sync(ctx);\n \temit(ctx, lld, t1, off, dst);\n \tswitch (code) {\n \tcase BPF_ADD:\n@@ -391,7 +392,7 @@ static void emit_atomic_r64(struct jit_c\n \t\tbreak;\n \t}\n \temit(ctx, scd, t2, off, dst);\n-\temit(ctx, beqz, t2, -16);\n+\temit(ctx, LLSC_beqz, t2, -16 - LLSC_offset);\n \temit(ctx, nop); /* Delay slot */\n }\n \n@@ -414,7 +415,7 @@ static int emit_call(struct jit_context\n \tpush_regs(ctx, ctx->clobbered & JIT_CALLER_REGS, 0, 0);\n \n \t/* Emit function call */\n-\temit_mov_i64(ctx, tmp, addr);\n+\temit_mov_i64(ctx, tmp, addr & JALR_MASK);\n \temit(ctx, jalr, MIPS_R_RA, tmp);\n \temit(ctx, nop); /* Delay slot */\n \n"
  },
  {
    "path": "target/linux/generic/backport-5.15/050-v5.16-05-mips-bpf-Enable-eBPF-JITs.patch",
    "content": "From: Johan Almbladh <johan.almbladh@anyfinetworks.com>\nDate: Tue, 5 Oct 2021 18:54:07 +0200\nSubject: [PATCH] mips: bpf: Enable eBPF JITs\n\nThis patch enables the new eBPF JITs for 32-bit and 64-bit MIPS. It also\ndisables the old cBPF JIT to so cBPF programs are converted to use the\nnew JIT.\n\nWorkarounds for R4000 CPU errata are not implemented by the JIT, so the\nJIT is disabled if any of those workarounds are configured.\n\nSigned-off-by: Johan Almbladh <johan.almbladh@anyfinetworks.com>\n---\n\n--- a/MAINTAINERS\n+++ b/MAINTAINERS\n@@ -3428,6 +3428,7 @@ S:\tSupported\n F:\tarch/arm64/net/\n \n BPF JIT for MIPS (32-BIT AND 64-BIT)\n+M:\tJohan Almbladh <johan.almbladh@anyfinetworks.com>\n M:\tPaul Burton <paulburton@kernel.org>\n L:\tnetdev@vger.kernel.org\n L:\tbpf@vger.kernel.org\n--- a/arch/mips/Kconfig\n+++ b/arch/mips/Kconfig\n@@ -57,7 +57,6 @@ config MIPS\n \tselect HAVE_ARCH_TRACEHOOK\n \tselect HAVE_ARCH_TRANSPARENT_HUGEPAGE if CPU_SUPPORTS_HUGEPAGES\n \tselect HAVE_ASM_MODVERSIONS\n-\tselect HAVE_CBPF_JIT if !64BIT && !CPU_MICROMIPS\n \tselect HAVE_CONTEXT_TRACKING\n \tselect HAVE_TIF_NOHZ\n \tselect HAVE_C_RECORDMCOUNT\n@@ -65,7 +64,10 @@ config MIPS\n \tselect HAVE_DEBUG_STACKOVERFLOW\n \tselect HAVE_DMA_CONTIGUOUS\n \tselect HAVE_DYNAMIC_FTRACE\n-\tselect HAVE_EBPF_JIT if 64BIT && !CPU_MICROMIPS && TARGET_ISA_REV >= 2\n+\tselect HAVE_EBPF_JIT if !CPU_MICROMIPS && \\\n+\t\t\t\t!CPU_DADDI_WORKAROUNDS && \\\n+\t\t\t\t!CPU_R4000_WORKAROUNDS && \\\n+\t\t\t\t!CPU_R4400_WORKAROUNDS\n \tselect HAVE_EXIT_THREAD\n \tselect HAVE_FAST_GUP\n \tselect HAVE_FTRACE_MCOUNT_RECORD\n--- a/arch/mips/net/Makefile\n+++ b/arch/mips/net/Makefile\n@@ -2,9 +2,10 @@\n # MIPS networking code\n \n obj-$(CONFIG_MIPS_CBPF_JIT) += bpf_jit.o bpf_jit_asm.o\n+obj-$(CONFIG_MIPS_EBPF_JIT) += bpf_jit_comp.o\n \n ifeq ($(CONFIG_32BIT),y)\n-        obj-$(CONFIG_MIPS_EBPF_JIT) += bpf_jit_comp.o bpf_jit_comp32.o\n+        obj-$(CONFIG_MIPS_EBPF_JIT) += bpf_jit_comp32.o\n else\n-        obj-$(CONFIG_MIPS_EBPF_JIT) += ebpf_jit.o\n+        obj-$(CONFIG_MIPS_EBPF_JIT) += bpf_jit_comp64.o\n endif\n"
  },
  {
    "path": "target/linux/generic/backport-5.15/050-v5.16-06-mips-bpf-Remove-old-BPF-JIT-implementations.patch",
    "content": "From: Johan Almbladh <johan.almbladh@anyfinetworks.com>\nDate: Tue, 5 Oct 2021 18:54:08 +0200\nSubject: [PATCH] mips: bpf: Remove old BPF JIT implementations\n\nThis patch removes the old 32-bit cBPF and 64-bit eBPF JIT implementations.\nThey are replaced by a new eBPF implementation that supports both 32-bit\nand 64-bit MIPS CPUs.\n\nSigned-off-by: Johan Almbladh <johan.almbladh@anyfinetworks.com>\n---\n delete mode 100644 arch/mips/net/bpf_jit.c\n delete mode 100644 arch/mips/net/bpf_jit.h\n delete mode 100644 arch/mips/net/bpf_jit_asm.S\n delete mode 100644 arch/mips/net/ebpf_jit.c\n\n--- a/arch/mips/net/bpf_jit.h\n+++ /dev/null\n@@ -1,81 +0,0 @@\n-/* SPDX-License-Identifier: GPL-2.0-only */\n-/*\n- * Just-In-Time compiler for BPF filters on MIPS\n- *\n- * Copyright (c) 2014 Imagination Technologies Ltd.\n- * Author: Markos Chandras <markos.chandras@imgtec.com>\n- */\n-\n-#ifndef BPF_JIT_MIPS_OP_H\n-#define BPF_JIT_MIPS_OP_H\n-\n-/* Registers used by JIT */\n-#define MIPS_R_ZERO\t0\n-#define MIPS_R_V0\t2\n-#define MIPS_R_A0\t4\n-#define MIPS_R_A1\t5\n-#define MIPS_R_T4\t12\n-#define MIPS_R_T5\t13\n-#define MIPS_R_T6\t14\n-#define MIPS_R_T7\t15\n-#define MIPS_R_S0\t16\n-#define MIPS_R_S1\t17\n-#define MIPS_R_S2\t18\n-#define MIPS_R_S3\t19\n-#define MIPS_R_S4\t20\n-#define MIPS_R_S5\t21\n-#define MIPS_R_S6\t22\n-#define MIPS_R_S7\t23\n-#define MIPS_R_SP\t29\n-#define MIPS_R_RA\t31\n-\n-/* Conditional codes */\n-#define MIPS_COND_EQ\t0x1\n-#define MIPS_COND_GE\t(0x1 << 1)\n-#define MIPS_COND_GT\t(0x1 << 2)\n-#define MIPS_COND_NE\t(0x1 << 3)\n-#define MIPS_COND_ALL\t(0x1 << 4)\n-/* Conditionals on X register or K immediate */\n-#define MIPS_COND_X\t(0x1 << 5)\n-#define MIPS_COND_K\t(0x1 << 6)\n-\n-#define r_ret\tMIPS_R_V0\n-\n-/*\n- * Use 2 scratch registers to avoid pipeline interlocks.\n- * There is no overhead during epilogue and prologue since\n- * any of the $s0-$s6 registers will only be preserved if\n- * they are going to actually be used.\n- */\n-#define r_skb_hl\tMIPS_R_S0 /* skb header length */\n-#define r_skb_data\tMIPS_R_S1 /* skb actual data */\n-#define r_off\t\tMIPS_R_S2\n-#define r_A\t\tMIPS_R_S3\n-#define r_X\t\tMIPS_R_S4\n-#define r_skb\t\tMIPS_R_S5\n-#define r_M\t\tMIPS_R_S6\n-#define r_skb_len\tMIPS_R_S7\n-#define r_s0\t\tMIPS_R_T4 /* scratch reg 1 */\n-#define r_s1\t\tMIPS_R_T5 /* scratch reg 2 */\n-#define r_tmp_imm\tMIPS_R_T6 /* No need to preserve this */\n-#define r_tmp\t\tMIPS_R_T7 /* No need to preserve this */\n-#define r_zero\t\tMIPS_R_ZERO\n-#define r_sp\t\tMIPS_R_SP\n-#define r_ra\t\tMIPS_R_RA\n-\n-#ifndef __ASSEMBLY__\n-\n-/* Declare ASM helpers */\n-\n-#define DECLARE_LOAD_FUNC(func) \\\n-\textern u8 func(unsigned long *skb, int offset); \\\n-\textern u8 func##_negative(unsigned long *skb, int offset); \\\n-\textern u8 func##_positive(unsigned long *skb, int offset)\n-\n-DECLARE_LOAD_FUNC(sk_load_word);\n-DECLARE_LOAD_FUNC(sk_load_half);\n-DECLARE_LOAD_FUNC(sk_load_byte);\n-\n-#endif\n-\n-#endif /* BPF_JIT_MIPS_OP_H */\n--- a/arch/mips/net/bpf_jit_asm.S\n+++ /dev/null\n@@ -1,285 +0,0 @@\n-/*\n- * bpf_jib_asm.S: Packet/header access helper functions for MIPS/MIPS64 BPF\n- * compiler.\n- *\n- * Copyright (C) 2015 Imagination Technologies Ltd.\n- * Author: Markos Chandras <markos.chandras@imgtec.com>\n- *\n- * This program is free software; you can redistribute it and/or modify it\n- * under the terms of the GNU General Public License as published by the\n- * Free Software Foundation; version 2 of the License.\n- */\n-\n-#include <asm/asm.h>\n-#include <asm/isa-rev.h>\n-#include <asm/regdef.h>\n-#include \"bpf_jit.h\"\n-\n-/* ABI\n- *\n- * r_skb_hl\tskb header length\n- * r_skb_data\tskb data\n- * r_off(a1)\toffset register\n- * r_A\t\tBPF register A\n- * r_X\t\tPF register X\n- * r_skb(a0)\t*skb\n- * r_M\t\t*scratch memory\n- * r_skb_le\tskb length\n- * r_s0\t\tScratch register 0\n- * r_s1\t\tScratch register 1\n- *\n- * On entry:\n- * a0: *skb\n- * a1: offset (imm or imm + X)\n- *\n- * All non-BPF-ABI registers are free for use. On return, we only\n- * care about r_ret. The BPF-ABI registers are assumed to remain\n- * unmodified during the entire filter operation.\n- */\n-\n-#define skb\ta0\n-#define offset\ta1\n-#define SKF_LL_OFF  (-0x200000) /* Can't include linux/filter.h in assembly */\n-\n-\t/* We know better :) so prevent assembler reordering etc */\n-\t.set \tnoreorder\n-\n-#define is_offset_negative(TYPE)\t\t\t\t\\\n-\t/* If offset is negative we have more work to do */\t\\\n-\tslti\tt0, offset, 0;\t\t\t\t\t\\\n-\tbgtz\tt0, bpf_slow_path_##TYPE##_neg;\t\t\t\\\n-\t/* Be careful what follows in DS. */\n-\n-#define is_offset_in_header(SIZE, TYPE)\t\t\t\t\\\n-\t/* Reading from header? */\t\t\t\t\\\n-\taddiu\t$r_s0, $r_skb_hl, -SIZE;\t\t\t\\\n-\tslt\tt0, $r_s0, offset;\t\t\t\t\\\n-\tbgtz\tt0, bpf_slow_path_##TYPE;\t\t\t\\\n-\n-LEAF(sk_load_word)\n-\tis_offset_negative(word)\n-FEXPORT(sk_load_word_positive)\n-\tis_offset_in_header(4, word)\n-\t/* Offset within header boundaries */\n-\tPTR_ADDU t1, $r_skb_data, offset\n-\t.set\treorder\n-\tlw\t$r_A, 0(t1)\n-\t.set\tnoreorder\n-#ifdef CONFIG_CPU_LITTLE_ENDIAN\n-# if MIPS_ISA_REV >= 2\n-\twsbh\tt0, $r_A\n-\trotr\t$r_A, t0, 16\n-# else\n-\tsll\tt0, $r_A, 24\n-\tsrl\tt1, $r_A, 24\n-\tsrl\tt2, $r_A, 8\n-\tor\tt0, t0, t1\n-\tandi\tt2, t2, 0xff00\n-\tandi\tt1, $r_A, 0xff00\n-\tor\tt0, t0, t2\n-\tsll\tt1, t1, 8\n-\tor\t$r_A, t0, t1\n-# endif\n-#endif\n-\tjr\t$r_ra\n-\t move\t$r_ret, zero\n-\tEND(sk_load_word)\n-\n-LEAF(sk_load_half)\n-\tis_offset_negative(half)\n-FEXPORT(sk_load_half_positive)\n-\tis_offset_in_header(2, half)\n-\t/* Offset within header boundaries */\n-\tPTR_ADDU t1, $r_skb_data, offset\n-\tlhu\t$r_A, 0(t1)\n-#ifdef CONFIG_CPU_LITTLE_ENDIAN\n-# if MIPS_ISA_REV >= 2\n-\twsbh\t$r_A, $r_A\n-# else\n-\tsll\tt0, $r_A, 8\n-\tsrl\tt1, $r_A, 8\n-\tandi\tt0, t0, 0xff00\n-\tor\t$r_A, t0, t1\n-# endif\n-#endif\n-\tjr\t$r_ra\n-\t move\t$r_ret, zero\n-\tEND(sk_load_half)\n-\n-LEAF(sk_load_byte)\n-\tis_offset_negative(byte)\n-FEXPORT(sk_load_byte_positive)\n-\tis_offset_in_header(1, byte)\n-\t/* Offset within header boundaries */\n-\tPTR_ADDU t1, $r_skb_data, offset\n-\tlbu\t$r_A, 0(t1)\n-\tjr\t$r_ra\n-\t move\t$r_ret, zero\n-\tEND(sk_load_byte)\n-\n-/*\n- * call skb_copy_bits:\n- * (prototype in linux/skbuff.h)\n- *\n- * int skb_copy_bits(sk_buff *skb, int offset, void *to, int len)\n- *\n- * o32 mandates we leave 4 spaces for argument registers in case\n- * the callee needs to use them. Even though we don't care about\n- * the argument registers ourselves, we need to allocate that space\n- * to remain ABI compliant since the callee may want to use that space.\n- * We also allocate 2 more spaces for $r_ra and our return register (*to).\n- *\n- * n64 is a bit different. The *caller* will allocate the space to preserve\n- * the arguments. So in 64-bit kernels, we allocate the 4-arg space for no\n- * good reason but it does not matter that much really.\n- *\n- * (void *to) is returned in r_s0\n- *\n- */\n-#ifdef CONFIG_CPU_LITTLE_ENDIAN\n-#define DS_OFFSET(SIZE) (4 * SZREG)\n-#else\n-#define DS_OFFSET(SIZE) ((4 * SZREG) + (4 - SIZE))\n-#endif\n-#define bpf_slow_path_common(SIZE)\t\t\t\t\\\n-\t/* Quick check. Are we within reasonable boundaries? */ \\\n-\tLONG_ADDIU\t$r_s1, $r_skb_len, -SIZE;\t\t\\\n-\tsltu\t\t$r_s0, offset, $r_s1;\t\t\t\\\n-\tbeqz\t\t$r_s0, fault;\t\t\t\t\\\n-\t/* Load 4th argument in DS */\t\t\t\t\\\n-\t LONG_ADDIU\ta3, zero, SIZE;\t\t\t\t\\\n-\tPTR_ADDIU\t$r_sp, $r_sp, -(6 * SZREG);\t\t\\\n-\tPTR_LA\t\tt0, skb_copy_bits;\t\t\t\\\n-\tPTR_S\t\t$r_ra, (5 * SZREG)($r_sp);\t\t\\\n-\t/* Assign low slot to a2 */\t\t\t\t\\\n-\tPTR_ADDIU\ta2, $r_sp, DS_OFFSET(SIZE);\t\t\\\n-\tjalr\t\tt0;\t\t\t\t\t\\\n-\t/* Reset our destination slot (DS but it's ok) */\t\\\n-\t INT_S\t\tzero, (4 * SZREG)($r_sp);\t\t\\\n-\t/*\t\t\t\t\t\t\t\\\n-\t * skb_copy_bits returns 0 on success and -EFAULT\t\\\n-\t * on error. Our data live in a2. Do not bother with\t\\\n-\t * our data if an error has been returned.\t\t\\\n-\t */\t\t\t\t\t\t\t\\\n-\t/* Restore our frame */\t\t\t\t\t\\\n-\tPTR_L\t\t$r_ra, (5 * SZREG)($r_sp);\t\t\\\n-\tINT_L\t\t$r_s0, (4 * SZREG)($r_sp);\t\t\\\n-\tbltz\t\tv0, fault;\t\t\t\t\\\n-\t PTR_ADDIU\t$r_sp, $r_sp, 6 * SZREG;\t\t\\\n-\tmove\t\t$r_ret, zero;\t\t\t\t\\\n-\n-NESTED(bpf_slow_path_word, (6 * SZREG), $r_sp)\n-\tbpf_slow_path_common(4)\n-#ifdef CONFIG_CPU_LITTLE_ENDIAN\n-# if MIPS_ISA_REV >= 2\n-\twsbh\tt0, $r_s0\n-\tjr\t$r_ra\n-\t rotr\t$r_A, t0, 16\n-# else\n-\tsll\tt0, $r_s0, 24\n-\tsrl\tt1, $r_s0, 24\n-\tsrl\tt2, $r_s0, 8\n-\tor\tt0, t0, t1\n-\tandi\tt2, t2, 0xff00\n-\tandi\tt1, $r_s0, 0xff00\n-\tor\tt0, t0, t2\n-\tsll\tt1, t1, 8\n-\tjr\t$r_ra\n-\t or\t$r_A, t0, t1\n-# endif\n-#else\n-\tjr\t$r_ra\n-\t move\t$r_A, $r_s0\n-#endif\n-\n-\tEND(bpf_slow_path_word)\n-\n-NESTED(bpf_slow_path_half, (6 * SZREG), $r_sp)\n-\tbpf_slow_path_common(2)\n-#ifdef CONFIG_CPU_LITTLE_ENDIAN\n-# if MIPS_ISA_REV >= 2\n-\tjr\t$r_ra\n-\t wsbh\t$r_A, $r_s0\n-# else\n-\tsll\tt0, $r_s0, 8\n-\tandi\tt1, $r_s0, 0xff00\n-\tandi\tt0, t0, 0xff00\n-\tsrl\tt1, t1, 8\n-\tjr\t$r_ra\n-\t or\t$r_A, t0, t1\n-# endif\n-#else\n-\tjr\t$r_ra\n-\t move\t$r_A, $r_s0\n-#endif\n-\n-\tEND(bpf_slow_path_half)\n-\n-NESTED(bpf_slow_path_byte, (6 * SZREG), $r_sp)\n-\tbpf_slow_path_common(1)\n-\tjr\t$r_ra\n-\t move\t$r_A, $r_s0\n-\n-\tEND(bpf_slow_path_byte)\n-\n-/*\n- * Negative entry points\n- */\n-\t.macro bpf_is_end_of_data\n-\tli\tt0, SKF_LL_OFF\n-\t/* Reading link layer data? */\n-\tslt\tt1, offset, t0\n-\tbgtz\tt1, fault\n-\t/* Be careful what follows in DS. */\n-\t.endm\n-/*\n- * call skb_copy_bits:\n- * (prototype in linux/filter.h)\n- *\n- * void *bpf_internal_load_pointer_neg_helper(const struct sk_buff *skb,\n- *                                            int k, unsigned int size)\n- *\n- * see above (bpf_slow_path_common) for ABI restrictions\n- */\n-#define bpf_negative_common(SIZE)\t\t\t\t\t\\\n-\tPTR_ADDIU\t$r_sp, $r_sp, -(6 * SZREG);\t\t\t\\\n-\tPTR_LA\t\tt0, bpf_internal_load_pointer_neg_helper;\t\\\n-\tPTR_S\t\t$r_ra, (5 * SZREG)($r_sp);\t\t\t\\\n-\tjalr\t\tt0;\t\t\t\t\t\t\\\n-\t li\t\ta2, SIZE;\t\t\t\t\t\\\n-\tPTR_L\t\t$r_ra, (5 * SZREG)($r_sp);\t\t\t\\\n-\t/* Check return pointer */\t\t\t\t\t\\\n-\tbeqz\t\tv0, fault;\t\t\t\t\t\\\n-\t PTR_ADDIU\t$r_sp, $r_sp, 6 * SZREG;\t\t\t\\\n-\t/* Preserve our pointer */\t\t\t\t\t\\\n-\tmove\t\t$r_s0, v0;\t\t\t\t\t\\\n-\t/* Set return value */\t\t\t\t\t\t\\\n-\tmove\t\t$r_ret, zero;\t\t\t\t\t\\\n-\n-bpf_slow_path_word_neg:\n-\tbpf_is_end_of_data\n-NESTED(sk_load_word_negative, (6 * SZREG), $r_sp)\n-\tbpf_negative_common(4)\n-\tjr\t$r_ra\n-\t lw\t$r_A, 0($r_s0)\n-\tEND(sk_load_word_negative)\n-\n-bpf_slow_path_half_neg:\n-\tbpf_is_end_of_data\n-NESTED(sk_load_half_negative, (6 * SZREG), $r_sp)\n-\tbpf_negative_common(2)\n-\tjr\t$r_ra\n-\t lhu\t$r_A, 0($r_s0)\n-\tEND(sk_load_half_negative)\n-\n-bpf_slow_path_byte_neg:\n-\tbpf_is_end_of_data\n-NESTED(sk_load_byte_negative, (6 * SZREG), $r_sp)\n-\tbpf_negative_common(1)\n-\tjr\t$r_ra\n-\t lbu\t$r_A, 0($r_s0)\n-\tEND(sk_load_byte_negative)\n-\n-fault:\n-\tjr\t$r_ra\n-\t addiu $r_ret, zero, 1\n"
  },
  {
    "path": "target/linux/generic/backport-5.15/081-net-next-regmap-allow-to-define-reg_update_bits-for-no-bus.patch",
    "content": "From 02d6fdecb9c38de19065f6bed8d5214556fd061d Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Thu, 4 Nov 2021 16:00:40 +0100\nSubject: regmap: allow to define reg_update_bits for no bus configuration\n\nSome device requires a special handling for reg_update_bits and can't use\nthe normal regmap read write logic. An example is when locking is\nhandled by the device and rmw operations requires to do atomic operations.\nAllow to declare a dedicated function in regmap_config for\nreg_update_bits in no bus configuration.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nLink: https://lore.kernel.org/r/20211104150040.1260-1-ansuelsmth@gmail.com\nSigned-off-by: Mark Brown <broonie@kernel.org>\n---\n drivers/base/regmap/regmap.c | 1 +\n include/linux/regmap.h       | 7 +++++++\n 2 files changed, 8 insertions(+)\n\n--- a/drivers/base/regmap/regmap.c\n+++ b/drivers/base/regmap/regmap.c\n@@ -877,6 +877,7 @@ struct regmap *__regmap_init(struct devi\n \tif (!bus) {\n \t\tmap->reg_read  = config->reg_read;\n \t\tmap->reg_write = config->reg_write;\n+\t\tmap->reg_update_bits = config->reg_update_bits;\n \n \t\tmap->defer_caching = false;\n \t\tgoto skip_format_initialization;\n--- a/include/linux/regmap.h\n+++ b/include/linux/regmap.h\n@@ -290,6 +290,11 @@ typedef void (*regmap_unlock)(void *);\n  *\t\t  read operation on a bus such as SPI, I2C, etc. Most of the\n  *\t\t  devices do not need this.\n  * @reg_write:\t  Same as above for writing.\n+ * @reg_update_bits: Optional callback that if filled will be used to perform\n+ *\t\t     all the update_bits(rmw) operation. Should only be provided\n+ *\t\t     if the function require special handling with lock and reg\n+ *\t\t     handling and the operation cannot be represented as a simple\n+ *\t\t     update_bits operation on a bus such as SPI, I2C, etc.\n  * @fast_io:\t  Register IO is fast. Use a spinlock instead of a mutex\n  *\t     \t  to perform locking. This field is ignored if custom lock/unlock\n  *\t     \t  functions are used (see fields lock/unlock of struct regmap_config).\n@@ -372,6 +377,8 @@ struct regmap_config {\n \n \tint (*reg_read)(void *context, unsigned int reg, unsigned int *val);\n \tint (*reg_write)(void *context, unsigned int reg, unsigned int val);\n+\tint (*reg_update_bits)(void *context, unsigned int reg,\n+\t\t\t       unsigned int mask, unsigned int val);\n \n \tbool fast_io;\n \n"
  },
  {
    "path": "target/linux/generic/backport-5.15/300-v5.18-pinctrl-qcom-Return--EINVAL-for-setting-affinity-if-no-IRQ-parent.patch",
    "content": "From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>\nTo: linus.walleij@linaro.org\nCc: bjorn.andersson@linaro.org, dianders@chromium.org,\n        linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org,\n        linux-kernel@vger.kernel.org,\n        Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>\nSubject: [PATCH] pinctrl: qcom: Return -EINVAL for setting affinity if no IRQ\n parent\nDate: Thu, 13 Jan 2022 21:56:17 +0530\nMessage-Id: <20220113162617.131697-1-manivannan.sadhasivam@linaro.org>\n\nThe MSM GPIO IRQ controller relies on the parent IRQ controller to set the\nCPU affinity for the IRQ. And this is only valid if there is any wakeup\nparent available and defined in DT.\n\nFor the case of no parent IRQ controller defined in DT,\nmsm_gpio_irq_set_affinity() and msm_gpio_irq_set_vcpu_affinity() should\nreturn -EINVAL instead of 0 as the affinity can't be set.\n\nOtherwise, below warning will be printed by genirq:\n\ngenirq: irq_chip msmgpio did not update eff. affinity mask of irq 70\n\nSigned-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>\n---\n drivers/pinctrl/qcom/pinctrl-msm.c | 4 ++--\n 1 file changed, 2 insertions(+), 2 deletions(-)\n\n--- a/drivers/pinctrl/qcom/pinctrl-msm.c\n+++ b/drivers/pinctrl/qcom/pinctrl-msm.c\n@@ -1157,7 +1157,7 @@ static int msm_gpio_irq_set_affinity(str\n \tif (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs))\n \t\treturn irq_chip_set_affinity_parent(d, dest, force);\n \n-\treturn 0;\n+\treturn -EINVAL;\n }\n \n static int msm_gpio_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu_info)\n@@ -1168,7 +1168,7 @@ static int msm_gpio_irq_set_vcpu_affinit\n \tif (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs))\n \t\treturn irq_chip_set_vcpu_affinity_parent(d, vcpu_info);\n \n-\treturn 0;\n+\treturn -EINVAL;\n }\n \n static void msm_gpio_irq_handler(struct irq_desc *desc)\n"
  },
  {
    "path": "target/linux/generic/backport-5.15/343-netfilter-nft_flow_offload-handle-netdevice-events-f.patch",
    "content": "From: Pablo Neira Ayuso <pablo@netfilter.org>\nDate: Thu, 25 Jan 2018 12:58:55 +0100\nSubject: [PATCH] netfilter: nft_flow_offload: handle netdevice events from\n nf_flow_table\n\nMove the code that deals with device events to the core.\n\nSigned-off-by: Pablo Neira Ayuso <pablo@netfilter.org>\n---\n\n--- a/net/netfilter/nf_flow_table_core.c\n+++ b/net/netfilter/nf_flow_table_core.c\n@@ -646,13 +646,41 @@ void nf_flow_table_free(struct nf_flowta\n }\n EXPORT_SYMBOL_GPL(nf_flow_table_free);\n \n+static int nf_flow_table_netdev_event(struct notifier_block *this,\n+\t\t\t\t      unsigned long event, void *ptr)\n+{\n+\tstruct net_device *dev = netdev_notifier_info_to_dev(ptr);\n+\n+\tif (event != NETDEV_DOWN)\n+\t\treturn NOTIFY_DONE;\n+\n+\tnf_flow_table_cleanup(dev);\n+\n+\treturn NOTIFY_DONE;\n+}\n+\n+static struct notifier_block flow_offload_netdev_notifier = {\n+\t.notifier_call\t= nf_flow_table_netdev_event,\n+};\n+\n static int __init nf_flow_table_module_init(void)\n {\n-\treturn nf_flow_table_offload_init();\n+\tint ret;\n+\n+\tret = nf_flow_table_offload_init();\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = register_netdevice_notifier(&flow_offload_netdev_notifier);\n+\tif (ret)\n+\t\tnf_flow_table_offload_exit();\n+\n+\treturn ret;\n }\n \n static void __exit nf_flow_table_module_exit(void)\n {\n+\tunregister_netdevice_notifier(&flow_offload_netdev_notifier);\n \tnf_flow_table_offload_exit();\n }\n \n--- a/net/netfilter/nft_flow_offload.c\n+++ b/net/netfilter/nft_flow_offload.c\n@@ -438,47 +438,14 @@ static struct nft_expr_type nft_flow_off\n \t.owner\t\t= THIS_MODULE,\n };\n \n-static int flow_offload_netdev_event(struct notifier_block *this,\n-\t\t\t\t     unsigned long event, void *ptr)\n-{\n-\tstruct net_device *dev = netdev_notifier_info_to_dev(ptr);\n-\n-\tif (event != NETDEV_DOWN)\n-\t\treturn NOTIFY_DONE;\n-\n-\tnf_flow_table_cleanup(dev);\n-\n-\treturn NOTIFY_DONE;\n-}\n-\n-static struct notifier_block flow_offload_netdev_notifier = {\n-\t.notifier_call\t= flow_offload_netdev_event,\n-};\n-\n static int __init nft_flow_offload_module_init(void)\n {\n-\tint err;\n-\n-\terr = register_netdevice_notifier(&flow_offload_netdev_notifier);\n-\tif (err)\n-\t\tgoto err;\n-\n-\terr = nft_register_expr(&nft_flow_offload_type);\n-\tif (err < 0)\n-\t\tgoto register_expr;\n-\n-\treturn 0;\n-\n-register_expr:\n-\tunregister_netdevice_notifier(&flow_offload_netdev_notifier);\n-err:\n-\treturn err;\n+\treturn nft_register_expr(&nft_flow_offload_type);\n }\n \n static void __exit nft_flow_offload_module_exit(void)\n {\n \tnft_unregister_expr(&nft_flow_offload_type);\n-\tunregister_netdevice_notifier(&flow_offload_netdev_notifier);\n }\n \n module_init(nft_flow_offload_module_init);\n"
  },
  {
    "path": "target/linux/generic/backport-5.15/400-mtdblock-warn-if-opened-on-NAND.patch",
    "content": "From 96a3295c351da82d7af99b2fc004a3cf9f4716a9 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Bj=C3=B8rn=20Mork?= <bjorn@mork.no>\nDate: Mon, 28 Mar 2022 18:11:08 +0200\nSubject: [PATCH] mtdblock: warn if opened on NAND\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nWarning on every translated mtd partition results in excessive log noise\nif this driver is loaded:\n\n  nand: device found, Manufacturer ID: 0xc2, Chip ID: 0xf1\n  nand: Macronix MX30LF1G18AC\n  nand: 128 MiB, SLC, erase size: 128 KiB, page size: 2048, OOB size: 64\n  mt7621-nand 1e003000.nand: ECC strength adjusted to 4 bits\n  read_bbt: found bbt at block 1023\n  10 fixed-partitions partitions found on MTD device mt7621-nand\n  Creating 10 MTD partitions on \"mt7621-nand\":\n  0x000000000000-0x000000080000 : \"Bootloader\"\n  mtdblock: MTD device 'Bootloader' is NAND, please consider using UBI block devices instead.\n  0x000000080000-0x000000100000 : \"Config\"\n  mtdblock: MTD device 'Config' is NAND, please consider using UBI block devices instead.\n  0x000000100000-0x000000140000 : \"Factory\"\n  mtdblock: MTD device 'Factory' is NAND, please consider using UBI block devices instead.\n  0x000000140000-0x000002000000 : \"Kernel\"\n  mtdblock: MTD device 'Kernel' is NAND, please consider using UBI block devices instead.\n  0x000000540000-0x000002000000 : \"ubi\"\n  mtdblock: MTD device 'ubi' is NAND, please consider using UBI block devices instead.\n  0x000002140000-0x000004000000 : \"Kernel2\"\n  mtdblock: MTD device 'Kernel2' is NAND, please consider using UBI block devices instead.\n  0x000004000000-0x000004100000 : \"wwan\"\n  mtdblock: MTD device 'wwan' is NAND, please consider using UBI block devices instead.\n  0x000004100000-0x000005100000 : \"data\"\n  mtdblock: MTD device 'data' is NAND, please consider using UBI block devices instead.\n  0x000005100000-0x000005200000 : \"rom-d\"\n  mtdblock: MTD device 'rom-d' is NAND, please consider using UBI block devices instead.\n  0x000005200000-0x000005280000 : \"reserve\"\n  mtdblock: MTD device 'reserve' is NAND, please consider using UBI block devices instead.\n  mtk_soc_eth 1e100000.ethernet eth0: mediatek frame engine at 0xbe100000, irq 21\n\nThis is more likely to annoy than to help users of embedded distros where\nthis driver is enabled by default.  Making the blockdevs available does\nnot imply that they are in use, and warning about bootloader partitions\nor other devices which obviously never will be mounted is more confusing\nthan helpful.\n\nMove the warning to open(), where it will be of more use - actually warning\nanyone who mounts a file system on NAND using mtdblock.\n\nFixes: e07403a8c6be (\"mtdblock: Warn if added for a NAND device\")\nSigned-off-by: Bjørn Mork <bjorn@mork.no>\nReviewed-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>\nSigned-off-by: Miquel Raynal <miquel.raynal@bootlin.com>\nLink: https://lore.kernel.org/linux-mtd/20220328161108.87757-1-bjorn@mork.no\n---\n drivers/mtd/mtdblock.c | 8 ++++----\n 1 file changed, 4 insertions(+), 4 deletions(-)\n\n--- a/drivers/mtd/mtdblock.c\n+++ b/drivers/mtd/mtdblock.c\n@@ -257,6 +257,10 @@ static int mtdblock_open(struct mtd_blkt\n \t\treturn 0;\n \t}\n \n+\tif (mtd_type_is_nand(mbd->mtd))\n+\t\tpr_warn(\"%s: MTD device '%s' is NAND, please consider using UBI block devices instead.\\n\",\n+\t\t\tmbd->tr->name, mbd->mtd->name);\n+\n \t/* OK, it's not open. Create cache info for it */\n \tmtdblk->count = 1;\n \tmutex_init(&mtdblk->cache_mutex);\n@@ -322,10 +326,6 @@ static void mtdblock_add_mtd(struct mtd_\n \tif (!(mtd->flags & MTD_WRITEABLE))\n \t\tdev->mbd.readonly = 1;\n \n-\tif (mtd_type_is_nand(mtd))\n-\t\tpr_warn(\"%s: MTD device '%s' is NAND, please consider using UBI block devices instead.\\n\",\n-\t\t\ttr->name, mtd->name);\n-\n \tif (add_mtd_blktrans_dev(&dev->mbd))\n \t\tkfree(dev);\n }\n"
  },
  {
    "path": "target/linux/generic/backport-5.15/410-mtd-next-mtd-parsers-trx-allow-to-use-on-MediaTek-MIPS-SoCs.patch",
    "content": "From 2365f91c861cbfeef7141c69842848c7b2d3c2db Mon Sep 17 00:00:00 2001\nFrom: INAGAKI Hiroshi <musashino.open@gmail.com>\nDate: Sun, 13 Feb 2022 15:40:44 +0900\nSubject: [PATCH] mtd: parsers: trx: allow to use on MediaTek MIPS SoCs\n\nBuffalo sells some router devices which have trx-formatted firmware,\nbased on MediaTek MIPS SoCs. To use parser_trx on those devices, add\n\"RALINK\" to dependency and allow to compile for MediaTek MIPS SoCs.\n\nexamples:\n\n- WCR-1166DS  (MT7628)\n- WSR-1166DHP (MT7621)\n- WSR-2533DHP (MT7621)\n\nSigned-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>\nSigned-off-by: Miquel Raynal <miquel.raynal@bootlin.com>\nLink: https://lore.kernel.org/linux-mtd/20220213064045.1781-1-musashino.open@gmail.com\n---\n drivers/mtd/parsers/Kconfig | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/drivers/mtd/parsers/Kconfig\n+++ b/drivers/mtd/parsers/Kconfig\n@@ -115,7 +115,7 @@ config MTD_AFS_PARTS\n \n config MTD_PARSER_TRX\n \ttristate \"Parser for TRX format partitions\"\n-\tdepends on MTD && (BCM47XX || ARCH_BCM_5301X || ARCH_MEDIATEK || COMPILE_TEST)\n+\tdepends on MTD && (BCM47XX || ARCH_BCM_5301X || ARCH_MEDIATEK || RALINK || COMPILE_TEST)\n \thelp\n \t  TRX is a firmware format used by Broadcom on their devices. It\n \t  may contain up to 3/4 partitions (depending on the version).\n"
  },
  {
    "path": "target/linux/generic/backport-5.15/420-v5.19-01-mtd-spinand-gigadevice-fix-Quad-IO-for-GD5F1GQ5UExxG.patch",
    "content": "From a4f9dd55c5e1bb951db6f1dee20e62e0103f3438 Mon Sep 17 00:00:00 2001\nFrom: Chuanhong Guo <gch981213@gmail.com>\nDate: Sun, 20 Mar 2022 17:59:57 +0800\nSubject: [PATCH 1/5] mtd: spinand: gigadevice: fix Quad IO for GD5F1GQ5UExxG\n\nRead From Cache Quad IO (EBH) uses 2 dummy bytes on this chip according\nto page 23 of the datasheet[0].\n\n[0]: https://www.gigadevice.com/datasheet/gd5f1gq5xexxg/\n\nFixes: 469b99248985 (\"mtd: spinand: gigadevice: Support GD5F1GQ5UExxG\")\nSigned-off-by: Chuanhong Guo <gch981213@gmail.com>\nSigned-off-by: Miquel Raynal <miquel.raynal@bootlin.com>\nLink: https://lore.kernel.org/linux-mtd/20220320100001.247905-2-gch981213@gmail.com\n---\n drivers/mtd/nand/spi/gigadevice.c | 10 +++++++++-\n 1 file changed, 9 insertions(+), 1 deletion(-)\n\n--- a/drivers/mtd/nand/spi/gigadevice.c\n+++ b/drivers/mtd/nand/spi/gigadevice.c\n@@ -39,6 +39,14 @@ static SPINAND_OP_VARIANTS(read_cache_va\n \t\tSPINAND_PAGE_READ_FROM_CACHE_OP_3A(true, 0, 1, NULL, 0),\n \t\tSPINAND_PAGE_READ_FROM_CACHE_OP_3A(false, 0, 0, NULL, 0));\n \n+static SPINAND_OP_VARIANTS(read_cache_variants_1gq5,\n+\t\tSPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),\n+\t\tSPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),\n+\t\tSPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),\n+\t\tSPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),\n+\t\tSPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),\n+\t\tSPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));\n+\n static SPINAND_OP_VARIANTS(write_cache_variants,\n \t\tSPINAND_PROG_LOAD_X4(true, 0, NULL, 0),\n \t\tSPINAND_PROG_LOAD(true, 0, NULL, 0));\n@@ -339,7 +347,7 @@ static const struct spinand_info gigadev\n \t\t     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x51),\n \t\t     NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),\n \t\t     NAND_ECCREQ(4, 512),\n-\t\t     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,\n+\t\t     SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,\n \t\t\t\t\t      &write_cache_variants,\n \t\t\t\t\t      &update_cache_variants),\n \t\t     SPINAND_HAS_QE_BIT,\n"
  },
  {
    "path": "target/linux/generic/backport-5.15/420-v5.19-02-mtd-spinand-gigadevice-add-support-for-GD5FxGQ4xExxG.patch",
    "content": "From 573eec222bc82fb5e724586267fbbb1aed9ffd03 Mon Sep 17 00:00:00 2001\nFrom: Chuanhong Guo <gch981213@gmail.com>\nDate: Sun, 20 Mar 2022 17:59:58 +0800\nSubject: [PATCH 2/5] mtd: spinand: gigadevice: add support for GD5FxGQ4xExxG\n\nAdd support for:\n GD5F1GQ4RExxG\n GD5F2GQ4{U,R}ExxG\n\nThese chips differ from GD5F1GQ4UExxG only in chip ID, voltage\nand capacity.\n\nSigned-off-by: Chuanhong Guo <gch981213@gmail.com>\nSigned-off-by: Miquel Raynal <miquel.raynal@bootlin.com>\nLink: https://lore.kernel.org/linux-mtd/20220320100001.247905-3-gch981213@gmail.com\n---\n drivers/mtd/nand/spi/gigadevice.c | 30 ++++++++++++++++++++++++++++++\n 1 file changed, 30 insertions(+)\n\n--- a/drivers/mtd/nand/spi/gigadevice.c\n+++ b/drivers/mtd/nand/spi/gigadevice.c\n@@ -333,6 +333,36 @@ static const struct spinand_info gigadev\n \t\t     SPINAND_HAS_QE_BIT,\n \t\t     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,\n \t\t\t\t     gd5fxgq4uexxg_ecc_get_status)),\n+\tSPINAND_INFO(\"GD5F1GQ4RExxG\",\n+\t\t     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xc1),\n+\t\t     NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),\n+\t\t     NAND_ECCREQ(8, 512),\n+\t\t     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,\n+\t\t\t\t\t      &write_cache_variants,\n+\t\t\t\t\t      &update_cache_variants),\n+\t\t     SPINAND_HAS_QE_BIT,\n+\t\t     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,\n+\t\t\t\t     gd5fxgq4uexxg_ecc_get_status)),\n+\tSPINAND_INFO(\"GD5F2GQ4UExxG\",\n+\t\t     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xd2),\n+\t\t     NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),\n+\t\t     NAND_ECCREQ(8, 512),\n+\t\t     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,\n+\t\t\t\t\t      &write_cache_variants,\n+\t\t\t\t\t      &update_cache_variants),\n+\t\t     SPINAND_HAS_QE_BIT,\n+\t\t     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,\n+\t\t\t\t     gd5fxgq4uexxg_ecc_get_status)),\n+\tSPINAND_INFO(\"GD5F2GQ4RExxG\",\n+\t\t     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xc2),\n+\t\t     NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),\n+\t\t     NAND_ECCREQ(8, 512),\n+\t\t     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,\n+\t\t\t\t\t      &write_cache_variants,\n+\t\t\t\t\t      &update_cache_variants),\n+\t\t     SPINAND_HAS_QE_BIT,\n+\t\t     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,\n+\t\t\t\t     gd5fxgq4uexxg_ecc_get_status)),\n \tSPINAND_INFO(\"GD5F1GQ4UFxxG\",\n \t\t     SPINAND_ID(SPINAND_READID_METHOD_OPCODE, 0xb1, 0x48),\n \t\t     NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),\n"
  },
  {
    "path": "target/linux/generic/backport-5.15/420-v5.19-03-mtd-spinand-gigadevice-add-support-for-GD5F1GQ5RExxG.patch",
    "content": "From 620a988813403318023296b61228ee8f3fcdb8e0 Mon Sep 17 00:00:00 2001\nFrom: Chuanhong Guo <gch981213@gmail.com>\nDate: Sun, 20 Mar 2022 17:59:59 +0800\nSubject: [PATCH 3/5] mtd: spinand: gigadevice: add support for GD5F1GQ5RExxG\n\nThis chip is the 1.8v version of GD5F1GQ5UExxG.\n\nSigned-off-by: Chuanhong Guo <gch981213@gmail.com>\nSigned-off-by: Miquel Raynal <miquel.raynal@bootlin.com>\nLink: https://lore.kernel.org/linux-mtd/20220320100001.247905-4-gch981213@gmail.com\n---\n drivers/mtd/nand/spi/gigadevice.c | 10 ++++++++++\n 1 file changed, 10 insertions(+)\n\n--- a/drivers/mtd/nand/spi/gigadevice.c\n+++ b/drivers/mtd/nand/spi/gigadevice.c\n@@ -383,6 +383,16 @@ static const struct spinand_info gigadev\n \t\t     SPINAND_HAS_QE_BIT,\n \t\t     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,\n \t\t\t\t     gd5fxgq5xexxg_ecc_get_status)),\n+\tSPINAND_INFO(\"GD5F1GQ5RExxG\",\n+\t\t     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x41),\n+\t\t     NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),\n+\t\t     NAND_ECCREQ(4, 512),\n+\t\t     SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,\n+\t\t\t\t\t      &write_cache_variants,\n+\t\t\t\t\t      &update_cache_variants),\n+\t\t     SPINAND_HAS_QE_BIT,\n+\t\t     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,\n+\t\t\t\t     gd5fxgq5xexxg_ecc_get_status)),\n };\n \n static const struct spinand_manufacturer_ops gigadevice_spinand_manuf_ops = {\n"
  },
  {
    "path": "target/linux/generic/backport-5.15/420-v5.19-04-mtd-spinand-gigadevice-add-support-for-GD5F-2-4-GQ5x.patch",
    "content": "From 194ec04b3a9e7fa97d1fbef296410631bc3cf1c8 Mon Sep 17 00:00:00 2001\nFrom: Chuanhong Guo <gch981213@gmail.com>\nDate: Sun, 20 Mar 2022 18:00:00 +0800\nSubject: [PATCH 4/5] mtd: spinand: gigadevice: add support for GD5F{2,\n 4}GQ5xExxG\n\nAdd support for:\n GD5F2GQ5{U,R}ExxG\n GD5F4GQ6{U,R}ExxG\n\nThese chips uses 4 dummy bytes for quad io and 2 dummy bytes for dual io.\nBesides that and memory layout, they are identical to their 1G variant.\n\nSigned-off-by: Chuanhong Guo <gch981213@gmail.com>\nSigned-off-by: Miquel Raynal <miquel.raynal@bootlin.com>\nLink: https://lore.kernel.org/linux-mtd/20220320100001.247905-5-gch981213@gmail.com\n---\n drivers/mtd/nand/spi/gigadevice.c | 48 +++++++++++++++++++++++++++++++\n 1 file changed, 48 insertions(+)\n\n--- a/drivers/mtd/nand/spi/gigadevice.c\n+++ b/drivers/mtd/nand/spi/gigadevice.c\n@@ -47,6 +47,14 @@ static SPINAND_OP_VARIANTS(read_cache_va\n \t\tSPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),\n \t\tSPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));\n \n+static SPINAND_OP_VARIANTS(read_cache_variants_2gq5,\n+\t\tSPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 4, NULL, 0),\n+\t\tSPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),\n+\t\tSPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 2, NULL, 0),\n+\t\tSPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),\n+\t\tSPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),\n+\t\tSPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));\n+\n static SPINAND_OP_VARIANTS(write_cache_variants,\n \t\tSPINAND_PROG_LOAD_X4(true, 0, NULL, 0),\n \t\tSPINAND_PROG_LOAD(true, 0, NULL, 0));\n@@ -391,6 +399,46 @@ static const struct spinand_info gigadev\n \t\t\t\t\t      &write_cache_variants,\n \t\t\t\t\t      &update_cache_variants),\n \t\t     SPINAND_HAS_QE_BIT,\n+\t\t     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,\n+\t\t\t\t     gd5fxgq5xexxg_ecc_get_status)),\n+\tSPINAND_INFO(\"GD5F2GQ5UExxG\",\n+\t\t     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x52),\n+\t\t     NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),\n+\t\t     NAND_ECCREQ(4, 512),\n+\t\t     SPINAND_INFO_OP_VARIANTS(&read_cache_variants_2gq5,\n+\t\t\t\t\t      &write_cache_variants,\n+\t\t\t\t\t      &update_cache_variants),\n+\t\t     SPINAND_HAS_QE_BIT,\n+\t\t     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,\n+\t\t\t\t     gd5fxgq5xexxg_ecc_get_status)),\n+\tSPINAND_INFO(\"GD5F2GQ5RExxG\",\n+\t\t     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x42),\n+\t\t     NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),\n+\t\t     NAND_ECCREQ(4, 512),\n+\t\t     SPINAND_INFO_OP_VARIANTS(&read_cache_variants_2gq5,\n+\t\t\t\t\t      &write_cache_variants,\n+\t\t\t\t\t      &update_cache_variants),\n+\t\t     SPINAND_HAS_QE_BIT,\n+\t\t     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,\n+\t\t\t\t     gd5fxgq5xexxg_ecc_get_status)),\n+\tSPINAND_INFO(\"GD5F4GQ6UExxG\",\n+\t\t     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x55),\n+\t\t     NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 2, 1),\n+\t\t     NAND_ECCREQ(4, 512),\n+\t\t     SPINAND_INFO_OP_VARIANTS(&read_cache_variants_2gq5,\n+\t\t\t\t\t      &write_cache_variants,\n+\t\t\t\t\t      &update_cache_variants),\n+\t\t     SPINAND_HAS_QE_BIT,\n+\t\t     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,\n+\t\t\t\t     gd5fxgq5xexxg_ecc_get_status)),\n+\tSPINAND_INFO(\"GD5F4GQ6RExxG\",\n+\t\t     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x45),\n+\t\t     NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 2, 1),\n+\t\t     NAND_ECCREQ(4, 512),\n+\t\t     SPINAND_INFO_OP_VARIANTS(&read_cache_variants_2gq5,\n+\t\t\t\t\t      &write_cache_variants,\n+\t\t\t\t\t      &update_cache_variants),\n+\t\t     SPINAND_HAS_QE_BIT,\n \t\t     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,\n \t\t\t\t     gd5fxgq5xexxg_ecc_get_status)),\n };\n"
  },
  {
    "path": "target/linux/generic/backport-5.15/420-v5.19-05-mtd-spinand-gigadevice-add-support-for-GD5FxGM7xExxG.patch",
    "content": "From 54647cd003c08b714474a5b599a147ec6a160486 Mon Sep 17 00:00:00 2001\nFrom: Chuanhong Guo <gch981213@gmail.com>\nDate: Sun, 20 Mar 2022 18:00:01 +0800\nSubject: [PATCH 5/5] mtd: spinand: gigadevice: add support for GD5FxGM7xExxG\n\nAdd support for:\n GD5F{1,2}GM7{U,R}ExxG\n GD5F4GM8{U,R}ExxG\n\nThese are new 27nm counterparts for the GD5FxGQ4 chips from GigaDevice\nwith 8b/512b on-die ECC capability.\nThese chips (and currently supported GD5FxGQ5 chips) have QIO DTR\ninstruction for reading page cache. It isn't added in this patch because\nI don't have a DTR spi controller for testing.\n\nSigned-off-by: Chuanhong Guo <gch981213@gmail.com>\nSigned-off-by: Miquel Raynal <miquel.raynal@bootlin.com>\nLink: https://lore.kernel.org/linux-mtd/20220320100001.247905-6-gch981213@gmail.com\n---\n drivers/mtd/nand/spi/gigadevice.c | 60 +++++++++++++++++++++++++++++++\n 1 file changed, 60 insertions(+)\n\n--- a/drivers/mtd/nand/spi/gigadevice.c\n+++ b/drivers/mtd/nand/spi/gigadevice.c\n@@ -441,6 +441,66 @@ static const struct spinand_info gigadev\n \t\t     SPINAND_HAS_QE_BIT,\n \t\t     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,\n \t\t\t\t     gd5fxgq5xexxg_ecc_get_status)),\n+\tSPINAND_INFO(\"GD5F1GM7UExxG\",\n+\t\t     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x91),\n+\t\t     NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),\n+\t\t     NAND_ECCREQ(8, 512),\n+\t\t     SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,\n+\t\t\t\t\t      &write_cache_variants,\n+\t\t\t\t\t      &update_cache_variants),\n+\t\t     SPINAND_HAS_QE_BIT,\n+\t\t     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,\n+\t\t\t\t     gd5fxgq4uexxg_ecc_get_status)),\n+\tSPINAND_INFO(\"GD5F1GM7RExxG\",\n+\t\t     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x81),\n+\t\t     NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),\n+\t\t     NAND_ECCREQ(8, 512),\n+\t\t     SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,\n+\t\t\t\t\t      &write_cache_variants,\n+\t\t\t\t\t      &update_cache_variants),\n+\t\t     SPINAND_HAS_QE_BIT,\n+\t\t     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,\n+\t\t\t\t     gd5fxgq4uexxg_ecc_get_status)),\n+\tSPINAND_INFO(\"GD5F2GM7UExxG\",\n+\t\t     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x92),\n+\t\t     NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),\n+\t\t     NAND_ECCREQ(8, 512),\n+\t\t     SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,\n+\t\t\t\t\t      &write_cache_variants,\n+\t\t\t\t\t      &update_cache_variants),\n+\t\t     SPINAND_HAS_QE_BIT,\n+\t\t     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,\n+\t\t\t\t     gd5fxgq4uexxg_ecc_get_status)),\n+\tSPINAND_INFO(\"GD5F2GM7RExxG\",\n+\t\t     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x82),\n+\t\t     NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),\n+\t\t     NAND_ECCREQ(8, 512),\n+\t\t     SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,\n+\t\t\t\t\t      &write_cache_variants,\n+\t\t\t\t\t      &update_cache_variants),\n+\t\t     SPINAND_HAS_QE_BIT,\n+\t\t     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,\n+\t\t\t\t     gd5fxgq4uexxg_ecc_get_status)),\n+\tSPINAND_INFO(\"GD5F4GM8UExxG\",\n+\t\t     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x95),\n+\t\t     NAND_MEMORG(1, 2048, 128, 64, 4096, 80, 1, 1, 1),\n+\t\t     NAND_ECCREQ(8, 512),\n+\t\t     SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,\n+\t\t\t\t\t      &write_cache_variants,\n+\t\t\t\t\t      &update_cache_variants),\n+\t\t     SPINAND_HAS_QE_BIT,\n+\t\t     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,\n+\t\t\t\t     gd5fxgq4uexxg_ecc_get_status)),\n+\tSPINAND_INFO(\"GD5F4GM8RExxG\",\n+\t\t     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x85),\n+\t\t     NAND_MEMORG(1, 2048, 128, 64, 4096, 80, 1, 1, 1),\n+\t\t     NAND_ECCREQ(8, 512),\n+\t\t     SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,\n+\t\t\t\t\t      &write_cache_variants,\n+\t\t\t\t\t      &update_cache_variants),\n+\t\t     SPINAND_HAS_QE_BIT,\n+\t\t     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,\n+\t\t\t\t     gd5fxgq4uexxg_ecc_get_status)),\n };\n \n static const struct spinand_manufacturer_ops gigadevice_spinand_manuf_ops = {\n"
  },
  {
    "path": "target/linux/generic/backport-5.15/700-net-next-net-dsa-introduce-tagger-owned-storage-for-private.patch",
    "content": "From dc452a471dbae8aca8257c565174212620880093 Mon Sep 17 00:00:00 2001\nFrom: Vladimir Oltean <vladimir.oltean@nxp.com>\nDate: Fri, 10 Dec 2021 01:34:37 +0200\nSubject: net: dsa: introduce tagger-owned storage for private and shared data\n\nAnsuel is working on register access over Ethernet for the qca8k switch\nfamily. This requires the qca8k tagging protocol driver to receive\nframes which aren't intended for the network stack, but instead for the\nqca8k switch driver itself.\n\nThe dp->priv is currently the prevailing method for passing data back\nand forth between the tagging protocol driver and the switch driver.\nHowever, this method is riddled with caveats.\n\nThe DSA design allows in principle for any switch driver to return any\nprotocol it desires in ->get_tag_protocol(). The dsa_loop driver can be\nmodified to do just that. But in the current design, the memory behind\ndp->priv has to be allocated by the switch driver, so if the tagging\nprotocol is paired to an unexpected switch driver, we may end up in NULL\npointer dereferences inside the kernel, or worse (a switch driver may\nallocate dp->priv according to the expectations of a different tagger).\n\nThe latter possibility is even more plausible considering that DSA\nswitches can dynamically change tagging protocols in certain cases\n(dsa <-> edsa, ocelot <-> ocelot-8021q), and the current design lends\nitself to mistakes that are all too easy to make.\n\nThis patch proposes that the tagging protocol driver should manage its\nown memory, instead of relying on the switch driver to do so.\nAfter analyzing the different in-tree needs, it can be observed that the\nrequired tagger storage is per switch, therefore a ds->tagger_data\npointer is introduced. In principle, per-port storage could also be\nintroduced, although there is no need for it at the moment. Future\nchanges will replace the current usage of dp->priv with ds->tagger_data.\n\nWe define a \"binding\" event between the DSA switch tree and the tagging\nprotocol. During this binding event, the tagging protocol's ->connect()\nmethod is called first, and this may allocate some memory for each\nswitch of the tree. Then a cross-chip notifier is emitted for the\nswitches within that tree, and they are given the opportunity to fix up\nthe tagger's memory (for example, they might set up some function\npointers that represent virtual methods for consuming packets).\nBecause the memory is owned by the tagger, there exists a ->disconnect()\nmethod for the tagger (which is the place to free the resources), but\nthere doesn't exist a ->disconnect() method for the switch driver.\nThis is part of the design. The switch driver should make minimal use of\nthe public part of the tagger data, and only after type-checking it\nusing the supplied \"proto\" argument.\n\nIn the code there are in fact two binding events, one is the initial\nevent in dsa_switch_setup_tag_protocol(). At this stage, the cross chip\nnotifier chains aren't initialized, so we call each switch's connect()\nmethod by hand. Then there is dsa_tree_bind_tag_proto() during\ndsa_tree_change_tag_proto(), and here we have an old protocol and a new\none. We first connect to the new one before disconnecting from the old\none, to simplify error handling a bit and to ensure we remain in a valid\nstate at all times.\n\nCo-developed-by: Ansuel Smith <ansuelsmth@gmail.com>\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nSigned-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n include/net/dsa.h  | 12 +++++++++\n net/dsa/dsa2.c     | 73 +++++++++++++++++++++++++++++++++++++++++++++++++++---\n net/dsa/dsa_priv.h |  1 +\n net/dsa/switch.c   | 14 +++++++++++\n 4 files changed, 96 insertions(+), 4 deletions(-)\n\n--- a/include/net/dsa.h\n+++ b/include/net/dsa.h\n@@ -80,12 +80,15 @@ enum dsa_tag_protocol {\n };\n \n struct dsa_switch;\n+struct dsa_switch_tree;\n \n struct dsa_device_ops {\n \tstruct sk_buff *(*xmit)(struct sk_buff *skb, struct net_device *dev);\n \tstruct sk_buff *(*rcv)(struct sk_buff *skb, struct net_device *dev);\n \tvoid (*flow_dissect)(const struct sk_buff *skb, __be16 *proto,\n \t\t\t     int *offset);\n+\tint (*connect)(struct dsa_switch_tree *dst);\n+\tvoid (*disconnect)(struct dsa_switch_tree *dst);\n \tunsigned int needed_headroom;\n \tunsigned int needed_tailroom;\n \tconst char *name;\n@@ -329,6 +332,8 @@ struct dsa_switch {\n \t */\n \tvoid *priv;\n \n+\tvoid *tagger_data;\n+\n \t/*\n \t * Configuration data for this switch.\n \t */\n@@ -584,6 +589,13 @@ struct dsa_switch_ops {\n \t\t\t\t\t\t  enum dsa_tag_protocol mprot);\n \tint\t(*change_tag_protocol)(struct dsa_switch *ds, int port,\n \t\t\t\t       enum dsa_tag_protocol proto);\n+\t/*\n+\t * Method for switch drivers to connect to the tagging protocol driver\n+\t * in current use. The switch driver can provide handlers for certain\n+\t * types of packets for switch management.\n+\t */\n+\tint\t(*connect_tag_protocol)(struct dsa_switch *ds,\n+\t\t\t\t\tenum dsa_tag_protocol proto);\n \n \t/* Optional switch-wide initialization and destruction methods */\n \tint\t(*setup)(struct dsa_switch *ds);\n--- a/net/dsa/dsa2.c\n+++ b/net/dsa/dsa2.c\n@@ -230,8 +230,12 @@ static struct dsa_switch_tree *dsa_tree_\n \n static void dsa_tree_free(struct dsa_switch_tree *dst)\n {\n-\tif (dst->tag_ops)\n+\tif (dst->tag_ops) {\n+\t\tif (dst->tag_ops->disconnect)\n+\t\t\tdst->tag_ops->disconnect(dst);\n+\n \t\tdsa_tag_driver_put(dst->tag_ops);\n+\t}\n \tlist_del(&dst->list);\n \tkfree(dst);\n }\n@@ -805,7 +809,7 @@ static int dsa_switch_setup_tag_protocol\n \tint port, err;\n \n \tif (tag_ops->proto == dst->default_proto)\n-\t\treturn 0;\n+\t\tgoto connect;\n \n \tfor (port = 0; port < ds->num_ports; port++) {\n \t\tif (!dsa_is_cpu_port(ds, port))\n@@ -821,6 +825,17 @@ static int dsa_switch_setup_tag_protocol\n \t\t}\n \t}\n \n+connect:\n+\tif (ds->ops->connect_tag_protocol) {\n+\t\terr = ds->ops->connect_tag_protocol(ds, tag_ops->proto);\n+\t\tif (err) {\n+\t\t\tdev_err(ds->dev,\n+\t\t\t\t\"Unable to connect to tag protocol \\\"%s\\\": %pe\\n\",\n+\t\t\t\ttag_ops->name, ERR_PTR(err));\n+\t\t\treturn err;\n+\t\t}\n+\t}\n+\n \treturn 0;\n }\n \n@@ -1132,6 +1147,46 @@ static void dsa_tree_teardown(struct dsa\n \tdst->setup = false;\n }\n \n+static int dsa_tree_bind_tag_proto(struct dsa_switch_tree *dst,\n+\t\t\t\t   const struct dsa_device_ops *tag_ops)\n+{\n+\tconst struct dsa_device_ops *old_tag_ops = dst->tag_ops;\n+\tstruct dsa_notifier_tag_proto_info info;\n+\tint err;\n+\n+\tdst->tag_ops = tag_ops;\n+\n+\t/* Notify the new tagger about the connection to this tree */\n+\tif (tag_ops->connect) {\n+\t\terr = tag_ops->connect(dst);\n+\t\tif (err)\n+\t\t\tgoto out_revert;\n+\t}\n+\n+\t/* Notify the switches from this tree about the connection\n+\t * to the new tagger\n+\t */\n+\tinfo.tag_ops = tag_ops;\n+\terr = dsa_tree_notify(dst, DSA_NOTIFIER_TAG_PROTO_CONNECT, &info);\n+\tif (err && err != -EOPNOTSUPP)\n+\t\tgoto out_disconnect;\n+\n+\t/* Notify the old tagger about the disconnection from this tree */\n+\tif (old_tag_ops->disconnect)\n+\t\told_tag_ops->disconnect(dst);\n+\n+\treturn 0;\n+\n+out_disconnect:\n+\t/* Revert the new tagger's connection to this tree */\n+\tif (tag_ops->disconnect)\n+\t\ttag_ops->disconnect(dst);\n+out_revert:\n+\tdst->tag_ops = old_tag_ops;\n+\n+\treturn err;\n+}\n+\n /* Since the dsa/tagging sysfs device attribute is per master, the assumption\n  * is that all DSA switches within a tree share the same tagger, otherwise\n  * they would have formed disjoint trees (different \"dsa,member\" values).\n@@ -1164,12 +1219,15 @@ int dsa_tree_change_tag_proto(struct dsa\n \t\t\tgoto out_unlock;\n \t}\n \n+\t/* Notify the tag protocol change */\n \tinfo.tag_ops = tag_ops;\n \terr = dsa_tree_notify(dst, DSA_NOTIFIER_TAG_PROTO, &info);\n \tif (err)\n-\t\tgoto out_unwind_tagger;\n+\t\treturn err;\n \n-\tdst->tag_ops = tag_ops;\n+\terr = dsa_tree_bind_tag_proto(dst, tag_ops);\n+\tif (err)\n+\t\tgoto out_unwind_tagger;\n \n \trtnl_unlock();\n \n@@ -1257,6 +1315,7 @@ static int dsa_port_parse_cpu(struct dsa\n \tstruct dsa_switch_tree *dst = ds->dst;\n \tconst struct dsa_device_ops *tag_ops;\n \tenum dsa_tag_protocol default_proto;\n+\tint err;\n \n \t/* Find out which protocol the switch would prefer. */\n \tdefault_proto = dsa_get_tag_protocol(dp, master);\n@@ -1304,6 +1363,12 @@ static int dsa_port_parse_cpu(struct dsa\n \t\t */\n \t\tdsa_tag_driver_put(tag_ops);\n \t} else {\n+\t\tif (tag_ops->connect) {\n+\t\t\terr = tag_ops->connect(dst);\n+\t\t\tif (err)\n+\t\t\t\treturn err;\n+\t\t}\n+\n \t\tdst->tag_ops = tag_ops;\n \t}\n \n--- a/net/dsa/dsa_priv.h\n+++ b/net/dsa/dsa_priv.h\n@@ -37,6 +37,7 @@ enum {\n \tDSA_NOTIFIER_VLAN_DEL,\n \tDSA_NOTIFIER_MTU,\n \tDSA_NOTIFIER_TAG_PROTO,\n+\tDSA_NOTIFIER_TAG_PROTO_CONNECT,\n \tDSA_NOTIFIER_MRP_ADD,\n \tDSA_NOTIFIER_MRP_DEL,\n \tDSA_NOTIFIER_MRP_ADD_RING_ROLE,\n--- a/net/dsa/switch.c\n+++ b/net/dsa/switch.c\n@@ -616,6 +616,17 @@ static int dsa_switch_change_tag_proto(s\n \treturn 0;\n }\n \n+static int dsa_switch_connect_tag_proto(struct dsa_switch *ds,\n+\t\t\t\t\tstruct dsa_notifier_tag_proto_info *info)\n+{\n+\tconst struct dsa_device_ops *tag_ops = info->tag_ops;\n+\n+\tif (!ds->ops->connect_tag_protocol)\n+\t\treturn -EOPNOTSUPP;\n+\n+\treturn ds->ops->connect_tag_protocol(ds, tag_ops->proto);\n+}\n+\n static int dsa_switch_mrp_add(struct dsa_switch *ds,\n \t\t\t      struct dsa_notifier_mrp_info *info)\n {\n@@ -735,6 +746,9 @@ static int dsa_switch_event(struct notif\n \tcase DSA_NOTIFIER_TAG_PROTO:\n \t\terr = dsa_switch_change_tag_proto(ds, info);\n \t\tbreak;\n+\tcase DSA_NOTIFIER_TAG_PROTO_CONNECT:\n+\t\terr = dsa_switch_connect_tag_proto(ds, info);\n+\t\tbreak;\n \tcase DSA_NOTIFIER_MRP_ADD:\n \t\terr = dsa_switch_mrp_add(ds, info);\n \t\tbreak;\n"
  },
  {
    "path": "target/linux/generic/backport-5.15/701-net-dsa-make-tagging-protocols-connect-to-individual-switches.patch",
    "content": "From 7f2973149c22e7a6fee4c0c9fa6b8e4108e9c208 Mon Sep 17 00:00:00 2001\nFrom: Vladimir Oltean <vladimir.oltean@nxp.com>\nDate: Tue, 14 Dec 2021 03:45:36 +0200\nSubject: net: dsa: make tagging protocols connect to individual switches from\n a tree\n\nOn the NXP Bluebox 3 board which uses a multi-switch setup with sja1105,\nthe mechanism through which the tagger connects to the switch tree is\nbroken, due to improper DSA code design. At the time when tag_ops->connect()\nis called in dsa_port_parse_cpu(), DSA hasn't finished \"touching\" all\nthe ports, so it doesn't know how large the tree is and how many ports\nit has. It has just seen the first CPU port by this time. As a result,\nthis function will call the tagger's ->connect method too early, and the\ntagger will connect only to the first switch from the tree.\n\nThis could be perhaps addressed a bit more simply by just moving the\ntag_ops->connect(dst) call a bit later (for example in dsa_tree_setup),\nbut there is already a design inconsistency at present: on the switch\nside, the notification is on a per-switch basis, but on the tagger side,\nit is on a per-tree basis. Furthermore, the persistent storage itself is\nper switch (ds->tagger_data). And the tagger connect and disconnect\nprocedures (at least the ones that exist currently) could see a fair bit\nof simplification if they didn't have to iterate through the switches of\na tree.\n\nTo fix the issue, this change transforms tag_ops->connect(dst) into\ntag_ops->connect(ds) and moves it somewhere where we already iterate\nover all switches of a tree. That is in dsa_switch_setup_tag_protocol(),\nwhich is a good placement because we already have there the connection\ncall to the switch side of things.\n\nAs for the dsa_tree_bind_tag_proto() method (called from the code path\nthat changes the tag protocol), things are a bit more complicated\nbecause we receive the tree as argument, yet when we unwind on errors,\nit would be nice to not call tag_ops->disconnect(ds) where we didn't\npreviously call tag_ops->connect(ds). We didn't have this problem before\nbecause the tag_ops connection operations passed the entire dst before,\nand this is more fine grained now. To solve the error rewind case using\nthe new API, we have to create yet one more cross-chip notifier for\ndisconnection, and stay connected with the old tag protocol to all the\nswitches in the tree until we've succeeded to connect with the new one\nas well. So if something fails half way, the whole tree is still\nconnected to the old tagger. But there may still be leaks if the tagger\nfails to connect to the 2nd out of 3 switches in a tree: somebody needs\nto tell the tagger to disconnect from the first switch. Nothing comes\nfor free, and this was previously handled privately by the tagging\nprotocol driver before, but now we need to emit a disconnect cross-chip\nnotifier for that, because DSA has to take care of the unwind path. We\nassume that the tagging protocol has connected to a switch if it has set\nds->tagger_data to something, otherwise we avoid calling its\ndisconnection method in the error rewind path.\n\nThe rest of the changes are in the tagging protocol drivers, and have to\ndo with the replacement of dst with ds. The iteration is removed and the\nerror unwind path is simplified, as mentioned above.\n\nSigned-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n include/net/dsa.h          |  5 ++--\n net/dsa/dsa2.c             | 44 +++++++++++++-----------------\n net/dsa/dsa_priv.h         |  1 +\n net/dsa/switch.c           | 52 ++++++++++++++++++++++++++++++++---\n net/dsa/tag_ocelot_8021q.c | 53 +++++++++++-------------------------\n net/dsa/tag_sja1105.c      | 67 ++++++++++++++++------------------------------\n 6 files changed, 109 insertions(+), 113 deletions(-)\n\n--- a/include/net/dsa.h\n+++ b/include/net/dsa.h\n@@ -80,15 +80,14 @@ enum dsa_tag_protocol {\n };\n \n struct dsa_switch;\n-struct dsa_switch_tree;\n \n struct dsa_device_ops {\n \tstruct sk_buff *(*xmit)(struct sk_buff *skb, struct net_device *dev);\n \tstruct sk_buff *(*rcv)(struct sk_buff *skb, struct net_device *dev);\n \tvoid (*flow_dissect)(const struct sk_buff *skb, __be16 *proto,\n \t\t\t     int *offset);\n-\tint (*connect)(struct dsa_switch_tree *dst);\n-\tvoid (*disconnect)(struct dsa_switch_tree *dst);\n+\tint (*connect)(struct dsa_switch *ds);\n+\tvoid (*disconnect)(struct dsa_switch *ds);\n \tunsigned int needed_headroom;\n \tunsigned int needed_tailroom;\n \tconst char *name;\n--- a/net/dsa/dsa2.c\n+++ b/net/dsa/dsa2.c\n@@ -230,12 +230,8 @@ static struct dsa_switch_tree *dsa_tree_\n \n static void dsa_tree_free(struct dsa_switch_tree *dst)\n {\n-\tif (dst->tag_ops) {\n-\t\tif (dst->tag_ops->disconnect)\n-\t\t\tdst->tag_ops->disconnect(dst);\n-\n+\tif (dst->tag_ops)\n \t\tdsa_tag_driver_put(dst->tag_ops);\n-\t}\n \tlist_del(&dst->list);\n \tkfree(dst);\n }\n@@ -826,17 +822,29 @@ static int dsa_switch_setup_tag_protocol\n \t}\n \n connect:\n+\tif (tag_ops->connect) {\n+\t\terr = tag_ops->connect(ds);\n+\t\tif (err)\n+\t\t\treturn err;\n+\t}\n+\n \tif (ds->ops->connect_tag_protocol) {\n \t\terr = ds->ops->connect_tag_protocol(ds, tag_ops->proto);\n \t\tif (err) {\n \t\t\tdev_err(ds->dev,\n \t\t\t\t\"Unable to connect to tag protocol \\\"%s\\\": %pe\\n\",\n \t\t\t\ttag_ops->name, ERR_PTR(err));\n-\t\t\treturn err;\n+\t\t\tgoto disconnect;\n \t\t}\n \t}\n \n \treturn 0;\n+\n+disconnect:\n+\tif (tag_ops->disconnect)\n+\t\ttag_ops->disconnect(ds);\n+\n+\treturn err;\n }\n \n static int dsa_switch_setup(struct dsa_switch *ds)\n@@ -1156,13 +1164,6 @@ static int dsa_tree_bind_tag_proto(struc\n \n \tdst->tag_ops = tag_ops;\n \n-\t/* Notify the new tagger about the connection to this tree */\n-\tif (tag_ops->connect) {\n-\t\terr = tag_ops->connect(dst);\n-\t\tif (err)\n-\t\t\tgoto out_revert;\n-\t}\n-\n \t/* Notify the switches from this tree about the connection\n \t * to the new tagger\n \t */\n@@ -1172,16 +1173,14 @@ static int dsa_tree_bind_tag_proto(struc\n \t\tgoto out_disconnect;\n \n \t/* Notify the old tagger about the disconnection from this tree */\n-\tif (old_tag_ops->disconnect)\n-\t\told_tag_ops->disconnect(dst);\n+\tinfo.tag_ops = old_tag_ops;\n+\tdsa_tree_notify(dst, DSA_NOTIFIER_TAG_PROTO_DISCONNECT, &info);\n \n \treturn 0;\n \n out_disconnect:\n-\t/* Revert the new tagger's connection to this tree */\n-\tif (tag_ops->disconnect)\n-\t\ttag_ops->disconnect(dst);\n-out_revert:\n+\tinfo.tag_ops = tag_ops;\n+\tdsa_tree_notify(dst, DSA_NOTIFIER_TAG_PROTO_DISCONNECT, &info);\n \tdst->tag_ops = old_tag_ops;\n \n \treturn err;\n@@ -1315,7 +1314,6 @@ static int dsa_port_parse_cpu(struct dsa\n \tstruct dsa_switch_tree *dst = ds->dst;\n \tconst struct dsa_device_ops *tag_ops;\n \tenum dsa_tag_protocol default_proto;\n-\tint err;\n \n \t/* Find out which protocol the switch would prefer. */\n \tdefault_proto = dsa_get_tag_protocol(dp, master);\n@@ -1363,12 +1361,6 @@ static int dsa_port_parse_cpu(struct dsa\n \t\t */\n \t\tdsa_tag_driver_put(tag_ops);\n \t} else {\n-\t\tif (tag_ops->connect) {\n-\t\t\terr = tag_ops->connect(dst);\n-\t\t\tif (err)\n-\t\t\t\treturn err;\n-\t\t}\n-\n \t\tdst->tag_ops = tag_ops;\n \t}\n \n--- a/net/dsa/dsa_priv.h\n+++ b/net/dsa/dsa_priv.h\n@@ -38,6 +38,7 @@ enum {\n \tDSA_NOTIFIER_MTU,\n \tDSA_NOTIFIER_TAG_PROTO,\n \tDSA_NOTIFIER_TAG_PROTO_CONNECT,\n+\tDSA_NOTIFIER_TAG_PROTO_DISCONNECT,\n \tDSA_NOTIFIER_MRP_ADD,\n \tDSA_NOTIFIER_MRP_DEL,\n \tDSA_NOTIFIER_MRP_ADD_RING_ROLE,\n--- a/net/dsa/switch.c\n+++ b/net/dsa/switch.c\n@@ -616,15 +616,58 @@ static int dsa_switch_change_tag_proto(s\n \treturn 0;\n }\n \n-static int dsa_switch_connect_tag_proto(struct dsa_switch *ds,\n-\t\t\t\t\tstruct dsa_notifier_tag_proto_info *info)\n+/* We use the same cross-chip notifiers to inform both the tagger side, as well\n+ * as the switch side, of connection and disconnection events.\n+ * Since ds->tagger_data is owned by the tagger, it isn't a hard error if the\n+ * switch side doesn't support connecting to this tagger, and therefore, the\n+ * fact that we don't disconnect the tagger side doesn't constitute a memory\n+ * leak: the tagger will still operate with persistent per-switch memory, just\n+ * with the switch side unconnected to it. What does constitute a hard error is\n+ * when the switch side supports connecting but fails.\n+ */\n+static int\n+dsa_switch_connect_tag_proto(struct dsa_switch *ds,\n+\t\t\t     struct dsa_notifier_tag_proto_info *info)\n {\n \tconst struct dsa_device_ops *tag_ops = info->tag_ops;\n+\tint err;\n+\n+\t/* Notify the new tagger about the connection to this switch */\n+\tif (tag_ops->connect) {\n+\t\terr = tag_ops->connect(ds);\n+\t\tif (err)\n+\t\t\treturn err;\n+\t}\n \n \tif (!ds->ops->connect_tag_protocol)\n \t\treturn -EOPNOTSUPP;\n \n-\treturn ds->ops->connect_tag_protocol(ds, tag_ops->proto);\n+\t/* Notify the switch about the connection to the new tagger */\n+\terr = ds->ops->connect_tag_protocol(ds, tag_ops->proto);\n+\tif (err) {\n+\t\t/* Revert the new tagger's connection to this tree */\n+\t\tif (tag_ops->disconnect)\n+\t\t\ttag_ops->disconnect(ds);\n+\t\treturn err;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int\n+dsa_switch_disconnect_tag_proto(struct dsa_switch *ds,\n+\t\t\t\tstruct dsa_notifier_tag_proto_info *info)\n+{\n+\tconst struct dsa_device_ops *tag_ops = info->tag_ops;\n+\n+\t/* Notify the tagger about the disconnection from this switch */\n+\tif (tag_ops->disconnect && ds->tagger_data)\n+\t\ttag_ops->disconnect(ds);\n+\n+\t/* No need to notify the switch, since it shouldn't have any\n+\t * resources to tear down\n+\t */\n+\treturn 0;\n }\n \n static int dsa_switch_mrp_add(struct dsa_switch *ds,\n@@ -749,6 +792,9 @@ static int dsa_switch_event(struct notif\n \tcase DSA_NOTIFIER_TAG_PROTO_CONNECT:\n \t\terr = dsa_switch_connect_tag_proto(ds, info);\n \t\tbreak;\n+\tcase DSA_NOTIFIER_TAG_PROTO_DISCONNECT:\n+\t\terr = dsa_switch_disconnect_tag_proto(ds, info);\n+\t\tbreak;\n \tcase DSA_NOTIFIER_MRP_ADD:\n \t\terr = dsa_switch_mrp_add(ds, info);\n \t\tbreak;\n"
  },
  {
    "path": "target/linux/generic/backport-5.15/734-v5.16-0001-net-bgmac-improve-handling-PHY.patch",
    "content": "From b5375509184dc23d2b7fa0c5ed8763899ccc9674 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Sat, 2 Oct 2021 19:58:11 +0200\nSubject: [PATCH] net: bgmac: improve handling PHY\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\n1. Use info from DT if available\n\nIt allows describing for example a fixed link. It's more accurate than\njust guessing there may be one (depending on a chipset).\n\n2. Verify PHY ID before trying to connect PHY\n\nPHY addr 0x1e (30) is special in Broadcom routers and means a switch\nconnected as MDIO devices instead of a real PHY. Don't try connecting to\nit.\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/ethernet/broadcom/bgmac-bcma.c | 33 ++++++++++++++--------\n 1 file changed, 21 insertions(+), 12 deletions(-)\n\n--- a/drivers/net/ethernet/broadcom/bgmac-bcma.c\n+++ b/drivers/net/ethernet/broadcom/bgmac-bcma.c\n@@ -11,6 +11,7 @@\n #include <linux/bcma/bcma.h>\n #include <linux/brcmphy.h>\n #include <linux/etherdevice.h>\n+#include <linux/of_mdio.h>\n #include <linux/of_net.h>\n #include \"bgmac.h\"\n \n@@ -86,17 +87,28 @@ static int bcma_phy_connect(struct bgmac\n \tstruct phy_device *phy_dev;\n \tchar bus_id[MII_BUS_ID_SIZE + 3];\n \n+\t/* DT info should be the most accurate */\n+\tphy_dev = of_phy_get_and_connect(bgmac->net_dev, bgmac->dev->of_node,\n+\t\t\t\t\t bgmac_adjust_link);\n+\tif (phy_dev)\n+\t\treturn 0;\n+\n \t/* Connect to the PHY */\n-\tsnprintf(bus_id, sizeof(bus_id), PHY_ID_FMT, bgmac->mii_bus->id,\n-\t\t bgmac->phyaddr);\n-\tphy_dev = phy_connect(bgmac->net_dev, bus_id, bgmac_adjust_link,\n-\t\t\t      PHY_INTERFACE_MODE_MII);\n-\tif (IS_ERR(phy_dev)) {\n-\t\tdev_err(bgmac->dev, \"PHY connection failed\\n\");\n-\t\treturn PTR_ERR(phy_dev);\n+\tif (bgmac->mii_bus && bgmac->phyaddr != BGMAC_PHY_NOREGS) {\n+\t\tsnprintf(bus_id, sizeof(bus_id), PHY_ID_FMT, bgmac->mii_bus->id,\n+\t\t\t bgmac->phyaddr);\n+\t\tphy_dev = phy_connect(bgmac->net_dev, bus_id, bgmac_adjust_link,\n+\t\t\t\t      PHY_INTERFACE_MODE_MII);\n+\t\tif (IS_ERR(phy_dev)) {\n+\t\t\tdev_err(bgmac->dev, \"PHY connection failed\\n\");\n+\t\t\treturn PTR_ERR(phy_dev);\n+\t\t}\n+\n+\t\treturn 0;\n \t}\n \n-\treturn 0;\n+\t/* Assume a fixed link to the switch port */\n+\treturn bgmac_phy_connect_direct(bgmac);\n }\n \n static const struct bcma_device_id bgmac_bcma_tbl[] = {\n@@ -297,10 +309,7 @@ static int bgmac_probe(struct bcma_devic\n \tbgmac->cco_ctl_maskset = bcma_bgmac_cco_ctl_maskset;\n \tbgmac->get_bus_clock = bcma_bgmac_get_bus_clock;\n \tbgmac->cmn_maskset32 = bcma_bgmac_cmn_maskset32;\n-\tif (bgmac->mii_bus)\n-\t\tbgmac->phy_connect = bcma_phy_connect;\n-\telse\n-\t\tbgmac->phy_connect = bgmac_phy_connect_direct;\n+\tbgmac->phy_connect = bcma_phy_connect;\n \n \terr = bgmac_enet_probe(bgmac);\n \tif (err)\n"
  },
  {
    "path": "target/linux/generic/backport-5.15/734-v5.16-0002-net-bgmac-support-MDIO-described-in-DT.patch",
    "content": "From 45c9d966688e7fad7f24bfc450547d91e4304d0b Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Sat, 2 Oct 2021 19:58:12 +0200\nSubject: [PATCH] net: bgmac: support MDIO described in DT\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nCheck ethernet controller DT node for \"mdio\" subnode and use it with\nof_mdiobus_register() when present. That allows specifying MDIO and its\nPHY devices in a standard DT based way.\n\nThis is required for BCM53573 SoC support. That family is sometimes\ncalled Northstar (by marketing?) but is quite different from it. It uses\ndifferent CPU(s) and many different hw blocks.\n\nOne of shared blocks in BCM53573 is Ethernet controller. Switch however\nis not SRAB accessible (as it Northstar) but is MDIO attached.\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/ethernet/broadcom/bgmac-bcma-mdio.c | 6 +++++-\n 1 file changed, 5 insertions(+), 1 deletion(-)\n\n--- a/drivers/net/ethernet/broadcom/bgmac-bcma-mdio.c\n+++ b/drivers/net/ethernet/broadcom/bgmac-bcma-mdio.c\n@@ -10,6 +10,7 @@\n \n #include <linux/bcma/bcma.h>\n #include <linux/brcmphy.h>\n+#include <linux/of_mdio.h>\n #include \"bgmac.h\"\n \n static bool bcma_mdio_wait_value(struct bcma_device *core, u16 reg, u32 mask,\n@@ -211,6 +212,7 @@ struct mii_bus *bcma_mdio_mii_register(s\n {\n \tstruct bcma_device *core = bgmac->bcma.core;\n \tstruct mii_bus *mii_bus;\n+\tstruct device_node *np;\n \tint err;\n \n \tmii_bus = mdiobus_alloc();\n@@ -229,7 +231,9 @@ struct mii_bus *bcma_mdio_mii_register(s\n \tmii_bus->parent = &core->dev;\n \tmii_bus->phy_mask = ~(1 << bgmac->phyaddr);\n \n-\terr = mdiobus_register(mii_bus);\n+\tnp = of_get_child_by_name(core->dev.of_node, \"mdio\");\n+\n+\terr = of_mdiobus_register(mii_bus, np);\n \tif (err) {\n \t\tdev_err(&core->dev, \"Registration of mii bus failed\\n\");\n \t\tgoto err_free_bus;\n"
  },
  {
    "path": "target/linux/generic/backport-5.15/742-v5.16-net-phy-at803x-add-support-for-qca-8327-internal-phy.patch",
    "content": "From 0ccf8511182436183c031e8a2f740ae91a02c625 Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Tue, 14 Sep 2021 14:33:45 +0200\nSubject: net: phy: at803x: add support for qca 8327 internal phy\n\nAdd support for qca8327 internal phy needed for correct init of the\nswitch port. It does use the same qca8337 function and reg just with a\ndifferent id.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nTested-by: Rosen Penev <rosenp@gmail.com>\nTested-by: Andrew Lunn <andrew@lunn.ch>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/phy/at803x.c | 15 +++++++++++++++\n 1 file changed, 15 insertions(+)\n\n--- a/drivers/net/phy/at803x.c\n+++ b/drivers/net/phy/at803x.c\n@@ -1412,6 +1412,19 @@ static struct phy_driver at803x_driver[]\n \t.get_sset_count = at803x_get_sset_count,\n \t.get_strings = at803x_get_strings,\n \t.get_stats = at803x_get_stats,\n+}, {\n+\t/* QCA8327 */\n+\t.phy_id = QCA8327_PHY_ID,\n+\t.phy_id_mask = QCA8K_PHY_ID_MASK,\n+\t.name = \"QCA PHY 8327\",\n+\t/* PHY_GBIT_FEATURES */\n+\t.probe = at803x_probe,\n+\t.flags = PHY_IS_INTERNAL,\n+\t.config_init = qca83xx_config_init,\n+\t.soft_reset = genphy_soft_reset,\n+\t.get_sset_count = at803x_get_sset_count,\n+\t.get_strings = at803x_get_strings,\n+\t.get_stats = at803x_get_stats,\n }, };\n \n module_phy_driver(at803x_driver);\n@@ -1422,6 +1435,8 @@ static struct mdio_device_id __maybe_unu\n \t{ PHY_ID_MATCH_EXACT(ATH8032_PHY_ID) },\n \t{ PHY_ID_MATCH_EXACT(ATH8035_PHY_ID) },\n \t{ PHY_ID_MATCH_EXACT(ATH9331_PHY_ID) },\n+\t{ PHY_ID_MATCH_EXACT(QCA8337_PHY_ID) },\n+\t{ PHY_ID_MATCH_EXACT(QCA8327_PHY_ID) },\n \t{ }\n };\n \n"
  },
  {
    "path": "target/linux/generic/backport-5.15/743-v5.16-0001-net-dsa-b53-Include-all-ports-in-enabled_ports.patch",
    "content": "From 983d96a9116a328668601555d96736261d33170c Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Thu, 16 Sep 2021 14:03:51 +0200\nSubject: [PATCH] net: dsa: b53: Include all ports in \"enabled_ports\"\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nMake \"enabled_ports\" bitfield contain all available switch ports\nincluding a CPU port. This way there is no need for fixup during\ninitialization.\n\nFor BCM53010, BCM53018 and BCM53019 include also other available ports.\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nReviewed-by: Florian Fainelli <f.fainelli@gmail.com>\nTested-by: Florian Fainelli <f.fainelli@gmail.com>\nSigned-off-by: Jakub Kicinski <kuba@kernel.org>\n---\n drivers/net/dsa/b53/b53_common.c | 23 +++++++++++------------\n 1 file changed, 11 insertions(+), 12 deletions(-)\n\n--- a/drivers/net/dsa/b53/b53_common.c\n+++ b/drivers/net/dsa/b53/b53_common.c\n@@ -2302,7 +2302,7 @@ static const struct b53_chip_data b53_sw\n \t\t.chip_id = BCM5325_DEVICE_ID,\n \t\t.dev_name = \"BCM5325\",\n \t\t.vlans = 16,\n-\t\t.enabled_ports = 0x1f,\n+\t\t.enabled_ports = 0x3f,\n \t\t.arl_bins = 2,\n \t\t.arl_buckets = 1024,\n \t\t.imp_port = 5,\n@@ -2313,7 +2313,7 @@ static const struct b53_chip_data b53_sw\n \t\t.chip_id = BCM5365_DEVICE_ID,\n \t\t.dev_name = \"BCM5365\",\n \t\t.vlans = 256,\n-\t\t.enabled_ports = 0x1f,\n+\t\t.enabled_ports = 0x3f,\n \t\t.arl_bins = 2,\n \t\t.arl_buckets = 1024,\n \t\t.imp_port = 5,\n@@ -2324,7 +2324,7 @@ static const struct b53_chip_data b53_sw\n \t\t.chip_id = BCM5389_DEVICE_ID,\n \t\t.dev_name = \"BCM5389\",\n \t\t.vlans = 4096,\n-\t\t.enabled_ports = 0x1f,\n+\t\t.enabled_ports = 0x11f,\n \t\t.arl_bins = 4,\n \t\t.arl_buckets = 1024,\n \t\t.imp_port = 8,\n@@ -2338,7 +2338,7 @@ static const struct b53_chip_data b53_sw\n \t\t.chip_id = BCM5395_DEVICE_ID,\n \t\t.dev_name = \"BCM5395\",\n \t\t.vlans = 4096,\n-\t\t.enabled_ports = 0x1f,\n+\t\t.enabled_ports = 0x11f,\n \t\t.arl_bins = 4,\n \t\t.arl_buckets = 1024,\n \t\t.imp_port = 8,\n@@ -2352,7 +2352,7 @@ static const struct b53_chip_data b53_sw\n \t\t.chip_id = BCM5397_DEVICE_ID,\n \t\t.dev_name = \"BCM5397\",\n \t\t.vlans = 4096,\n-\t\t.enabled_ports = 0x1f,\n+\t\t.enabled_ports = 0x11f,\n \t\t.arl_bins = 4,\n \t\t.arl_buckets = 1024,\n \t\t.imp_port = 8,\n@@ -2366,7 +2366,7 @@ static const struct b53_chip_data b53_sw\n \t\t.chip_id = BCM5398_DEVICE_ID,\n \t\t.dev_name = \"BCM5398\",\n \t\t.vlans = 4096,\n-\t\t.enabled_ports = 0x7f,\n+\t\t.enabled_ports = 0x17f,\n \t\t.arl_bins = 4,\n \t\t.arl_buckets = 1024,\n \t\t.imp_port = 8,\n@@ -2380,7 +2380,7 @@ static const struct b53_chip_data b53_sw\n \t\t.chip_id = BCM53115_DEVICE_ID,\n \t\t.dev_name = \"BCM53115\",\n \t\t.vlans = 4096,\n-\t\t.enabled_ports = 0x1f,\n+\t\t.enabled_ports = 0x11f,\n \t\t.arl_bins = 4,\n \t\t.arl_buckets = 1024,\n \t\t.vta_regs = B53_VTA_REGS,\n@@ -2394,7 +2394,7 @@ static const struct b53_chip_data b53_sw\n \t\t.chip_id = BCM53125_DEVICE_ID,\n \t\t.dev_name = \"BCM53125\",\n \t\t.vlans = 4096,\n-\t\t.enabled_ports = 0xff,\n+\t\t.enabled_ports = 0x1ff,\n \t\t.arl_bins = 4,\n \t\t.arl_buckets = 1024,\n \t\t.imp_port = 8,\n@@ -2436,7 +2436,7 @@ static const struct b53_chip_data b53_sw\n \t\t.chip_id = BCM53010_DEVICE_ID,\n \t\t.dev_name = \"BCM53010\",\n \t\t.vlans = 4096,\n-\t\t.enabled_ports = 0x1f,\n+\t\t.enabled_ports = 0x1bf,\n \t\t.arl_bins = 4,\n \t\t.arl_buckets = 1024,\n \t\t.imp_port = 8,\n@@ -2478,7 +2478,7 @@ static const struct b53_chip_data b53_sw\n \t\t.chip_id = BCM53018_DEVICE_ID,\n \t\t.dev_name = \"BCM53018\",\n \t\t.vlans = 4096,\n-\t\t.enabled_ports = 0x1f,\n+\t\t.enabled_ports = 0x1bf,\n \t\t.arl_bins = 4,\n \t\t.arl_buckets = 1024,\n \t\t.imp_port = 8,\n@@ -2492,7 +2492,7 @@ static const struct b53_chip_data b53_sw\n \t\t.chip_id = BCM53019_DEVICE_ID,\n \t\t.dev_name = \"BCM53019\",\n \t\t.vlans = 4096,\n-\t\t.enabled_ports = 0x1f,\n+\t\t.enabled_ports = 0x1bf,\n \t\t.arl_bins = 4,\n \t\t.arl_buckets = 1024,\n \t\t.imp_port = 8,\n@@ -2634,7 +2634,6 @@ static int b53_switch_init(struct b53_de\n \t\t\tdev->cpu_port = 5;\n \t}\n \n-\tdev->enabled_ports |= BIT(dev->cpu_port);\n \tdev->num_ports = fls(dev->enabled_ports);\n \n \tdev->ds->num_ports = min_t(unsigned int, dev->num_ports, DSA_MAX_PORTS);\n"
  },
  {
    "path": "target/linux/generic/backport-5.15/743-v5.16-0002-net-dsa-b53-Drop-BCM5301x-workaround-for-a-wrong-CPU.patch",
    "content": "From b290c6384afabbca5ae6e2af72fb1b2bc37922be Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Thu, 16 Sep 2021 14:03:52 +0200\nSubject: [PATCH] net: dsa: b53: Drop BCM5301x workaround for a wrong CPU/IMP\n port\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nOn BCM5301x port 8 requires a fixed link when used.\n\nYears ago when b53 was an OpenWrt downstream driver (with configuration\nbased on sometimes bugged NVRAM) there was a need for a fixup. In case\nof forcing fixed link for (incorrectly specified) port 5 the code had to\nactually setup port 8 link.\n\nFor upstream b53 driver with setup based on DT there is no need for that\nworkaround. In DT we have and require correct ports setup.\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nReviewed-by: Florian Fainelli <f.fainelli@gmail.com>\nTested-by: Florian Fainelli <f.fainelli@gmail.com>\nSigned-off-by: Jakub Kicinski <kuba@kernel.org>\n---\n drivers/net/dsa/b53/b53_common.c | 6 ------\n 1 file changed, 6 deletions(-)\n\n--- a/drivers/net/dsa/b53/b53_common.c\n+++ b/drivers/net/dsa/b53/b53_common.c\n@@ -1291,12 +1291,6 @@ static void b53_adjust_link(struct dsa_s\n \t\t\t\treturn;\n \t\t\t}\n \t\t}\n-\t} else if (is5301x(dev)) {\n-\t\tif (port != dev->cpu_port) {\n-\t\t\tb53_force_port_config(dev, dev->cpu_port, 2000,\n-\t\t\t\t\t      DUPLEX_FULL, true, true);\n-\t\t\tb53_force_link(dev, dev->cpu_port, 1);\n-\t\t}\n \t}\n \n \t/* Re-negotiate EEE if it was enabled already */\n"
  },
  {
    "path": "target/linux/generic/backport-5.15/743-v5.16-0003-net-dsa-b53-Improve-flow-control-setup-on-BCM5301x.patch",
    "content": "From 3ff26b29230c54fea2353b63124c589b61953e14 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Thu, 16 Sep 2021 14:03:53 +0200\nSubject: [PATCH] net: dsa: b53: Improve flow control setup on BCM5301x\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nAccording to the Broadcom's reference driver flow control needs to be\nenabled for any CPU switch port (5, 7 or 8 - depending on which one is\nused). Current code makes it work only for the port 5. Use\ndsa_is_cpu_port() which solved that problem.\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nReviewed-by: Florian Fainelli <f.fainelli@gmail.com>\nTested-by: Florian Fainelli <f.fainelli@gmail.com>\nSigned-off-by: Jakub Kicinski <kuba@kernel.org>\n---\n drivers/net/dsa/b53/b53_common.c | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/drivers/net/dsa/b53/b53_common.c\n+++ b/drivers/net/dsa/b53/b53_common.c\n@@ -1222,7 +1222,7 @@ static void b53_adjust_link(struct dsa_s\n \t\treturn;\n \n \t/* Enable flow control on BCM5301x's CPU port */\n-\tif (is5301x(dev) && port == dev->cpu_port)\n+\tif (is5301x(dev) && dsa_is_cpu_port(ds, port))\n \t\ttx_pause = rx_pause = true;\n \n \tif (phydev->pause) {\n"
  },
  {
    "path": "target/linux/generic/backport-5.15/743-v5.16-0004-net-dsa-b53-Drop-unused-cpu_port-field.patch",
    "content": "From 7d5af56418d7d01e43247a33b6fe6492ea871923 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Thu, 16 Sep 2021 14:03:54 +0200\nSubject: [PATCH] net: dsa: b53: Drop unused \"cpu_port\" field\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nIt's set but never used anymore.\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\nReviewed-by: Florian Fainelli <f.fainelli@gmail.com>\nTested-by: Florian Fainelli <f.fainelli@gmail.com>\nSigned-off-by: Jakub Kicinski <kuba@kernel.org>\n---\n drivers/net/dsa/b53/b53_common.c | 28 ----------------------------\n drivers/net/dsa/b53/b53_priv.h   |  1 -\n 2 files changed, 29 deletions(-)\n\n--- a/drivers/net/dsa/b53/b53_common.c\n+++ b/drivers/net/dsa/b53/b53_common.c\n@@ -2300,7 +2300,6 @@ static const struct b53_chip_data b53_sw\n \t\t.arl_bins = 2,\n \t\t.arl_buckets = 1024,\n \t\t.imp_port = 5,\n-\t\t.cpu_port = B53_CPU_PORT_25,\n \t\t.duplex_reg = B53_DUPLEX_STAT_FE,\n \t},\n \t{\n@@ -2311,7 +2310,6 @@ static const struct b53_chip_data b53_sw\n \t\t.arl_bins = 2,\n \t\t.arl_buckets = 1024,\n \t\t.imp_port = 5,\n-\t\t.cpu_port = B53_CPU_PORT_25,\n \t\t.duplex_reg = B53_DUPLEX_STAT_FE,\n \t},\n \t{\n@@ -2322,7 +2320,6 @@ static const struct b53_chip_data b53_sw\n \t\t.arl_bins = 4,\n \t\t.arl_buckets = 1024,\n \t\t.imp_port = 8,\n-\t\t.cpu_port = B53_CPU_PORT,\n \t\t.vta_regs = B53_VTA_REGS,\n \t\t.duplex_reg = B53_DUPLEX_STAT_GE,\n \t\t.jumbo_pm_reg = B53_JUMBO_PORT_MASK,\n@@ -2336,7 +2333,6 @@ static const struct b53_chip_data b53_sw\n \t\t.arl_bins = 4,\n \t\t.arl_buckets = 1024,\n \t\t.imp_port = 8,\n-\t\t.cpu_port = B53_CPU_PORT,\n \t\t.vta_regs = B53_VTA_REGS,\n \t\t.duplex_reg = B53_DUPLEX_STAT_GE,\n \t\t.jumbo_pm_reg = B53_JUMBO_PORT_MASK,\n@@ -2350,7 +2346,6 @@ static const struct b53_chip_data b53_sw\n \t\t.arl_bins = 4,\n \t\t.arl_buckets = 1024,\n \t\t.imp_port = 8,\n-\t\t.cpu_port = B53_CPU_PORT,\n \t\t.vta_regs = B53_VTA_REGS_9798,\n \t\t.duplex_reg = B53_DUPLEX_STAT_GE,\n \t\t.jumbo_pm_reg = B53_JUMBO_PORT_MASK,\n@@ -2364,7 +2359,6 @@ static const struct b53_chip_data b53_sw\n \t\t.arl_bins = 4,\n \t\t.arl_buckets = 1024,\n \t\t.imp_port = 8,\n-\t\t.cpu_port = B53_CPU_PORT,\n \t\t.vta_regs = B53_VTA_REGS_9798,\n \t\t.duplex_reg = B53_DUPLEX_STAT_GE,\n \t\t.jumbo_pm_reg = B53_JUMBO_PORT_MASK,\n@@ -2379,7 +2373,6 @@ static const struct b53_chip_data b53_sw\n \t\t.arl_buckets = 1024,\n \t\t.vta_regs = B53_VTA_REGS,\n \t\t.imp_port = 8,\n-\t\t.cpu_port = B53_CPU_PORT,\n \t\t.duplex_reg = B53_DUPLEX_STAT_GE,\n \t\t.jumbo_pm_reg = B53_JUMBO_PORT_MASK,\n \t\t.jumbo_size_reg = B53_JUMBO_MAX_SIZE,\n@@ -2392,7 +2385,6 @@ static const struct b53_chip_data b53_sw\n \t\t.arl_bins = 4,\n \t\t.arl_buckets = 1024,\n \t\t.imp_port = 8,\n-\t\t.cpu_port = B53_CPU_PORT,\n \t\t.vta_regs = B53_VTA_REGS,\n \t\t.duplex_reg = B53_DUPLEX_STAT_GE,\n \t\t.jumbo_pm_reg = B53_JUMBO_PORT_MASK,\n@@ -2406,7 +2398,6 @@ static const struct b53_chip_data b53_sw\n \t\t.arl_bins = 4,\n \t\t.arl_buckets = 1024,\n \t\t.imp_port = 8,\n-\t\t.cpu_port = B53_CPU_PORT,\n \t\t.vta_regs = B53_VTA_REGS,\n \t\t.duplex_reg = B53_DUPLEX_STAT_GE,\n \t\t.jumbo_pm_reg = B53_JUMBO_PORT_MASK,\n@@ -2420,7 +2411,6 @@ static const struct b53_chip_data b53_sw\n \t\t.arl_bins = 4,\n \t\t.arl_buckets = 1024,\n \t\t.imp_port = 8,\n-\t\t.cpu_port = B53_CPU_PORT,\n \t\t.vta_regs = B53_VTA_REGS_63XX,\n \t\t.duplex_reg = B53_DUPLEX_STAT_63XX,\n \t\t.jumbo_pm_reg = B53_JUMBO_PORT_MASK_63XX,\n@@ -2434,7 +2424,6 @@ static const struct b53_chip_data b53_sw\n \t\t.arl_bins = 4,\n \t\t.arl_buckets = 1024,\n \t\t.imp_port = 8,\n-\t\t.cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */\n \t\t.vta_regs = B53_VTA_REGS,\n \t\t.duplex_reg = B53_DUPLEX_STAT_GE,\n \t\t.jumbo_pm_reg = B53_JUMBO_PORT_MASK,\n@@ -2448,7 +2437,6 @@ static const struct b53_chip_data b53_sw\n \t\t.arl_bins = 4,\n \t\t.arl_buckets = 1024,\n \t\t.imp_port = 8,\n-\t\t.cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */\n \t\t.vta_regs = B53_VTA_REGS,\n \t\t.duplex_reg = B53_DUPLEX_STAT_GE,\n \t\t.jumbo_pm_reg = B53_JUMBO_PORT_MASK,\n@@ -2462,7 +2450,6 @@ static const struct b53_chip_data b53_sw\n \t\t.arl_bins = 4,\n \t\t.arl_buckets = 1024,\n \t\t.imp_port = 8,\n-\t\t.cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */\n \t\t.vta_regs = B53_VTA_REGS,\n \t\t.duplex_reg = B53_DUPLEX_STAT_GE,\n \t\t.jumbo_pm_reg = B53_JUMBO_PORT_MASK,\n@@ -2476,7 +2463,6 @@ static const struct b53_chip_data b53_sw\n \t\t.arl_bins = 4,\n \t\t.arl_buckets = 1024,\n \t\t.imp_port = 8,\n-\t\t.cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */\n \t\t.vta_regs = B53_VTA_REGS,\n \t\t.duplex_reg = B53_DUPLEX_STAT_GE,\n \t\t.jumbo_pm_reg = B53_JUMBO_PORT_MASK,\n@@ -2490,7 +2476,6 @@ static const struct b53_chip_data b53_sw\n \t\t.arl_bins = 4,\n \t\t.arl_buckets = 1024,\n \t\t.imp_port = 8,\n-\t\t.cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */\n \t\t.vta_regs = B53_VTA_REGS,\n \t\t.duplex_reg = B53_DUPLEX_STAT_GE,\n \t\t.jumbo_pm_reg = B53_JUMBO_PORT_MASK,\n@@ -2504,7 +2489,6 @@ static const struct b53_chip_data b53_sw\n \t\t.arl_bins = 4,\n \t\t.arl_buckets = 1024,\n \t\t.imp_port = 8,\n-\t\t.cpu_port = B53_CPU_PORT,\n \t\t.vta_regs = B53_VTA_REGS,\n \t\t.duplex_reg = B53_DUPLEX_STAT_GE,\n \t\t.jumbo_pm_reg = B53_JUMBO_PORT_MASK,\n@@ -2518,7 +2502,6 @@ static const struct b53_chip_data b53_sw\n \t\t.arl_bins = 4,\n \t\t.arl_buckets = 1024,\n \t\t.imp_port = 8,\n-\t\t.cpu_port = B53_CPU_PORT,\n \t\t.vta_regs = B53_VTA_REGS,\n \t\t.duplex_reg = B53_DUPLEX_STAT_GE,\n \t\t.jumbo_pm_reg = B53_JUMBO_PORT_MASK,\n@@ -2547,7 +2530,6 @@ static const struct b53_chip_data b53_sw\n \t\t.arl_bins = 4,\n \t\t.arl_buckets = 1024,\n \t\t.imp_port = 8,\n-\t\t.cpu_port = B53_CPU_PORT,\n \t\t.vta_regs = B53_VTA_REGS,\n \t\t.duplex_reg = B53_DUPLEX_STAT_GE,\n \t\t.jumbo_pm_reg = B53_JUMBO_PORT_MASK,\n@@ -2561,7 +2543,6 @@ static const struct b53_chip_data b53_sw\n \t\t.arl_bins = 4,\n \t\t.arl_buckets = 256,\n \t\t.imp_port = 8,\n-\t\t.cpu_port = B53_CPU_PORT,\n \t\t.vta_regs = B53_VTA_REGS,\n \t\t.duplex_reg = B53_DUPLEX_STAT_GE,\n \t\t.jumbo_pm_reg = B53_JUMBO_PORT_MASK,\n@@ -2587,7 +2568,6 @@ static int b53_switch_init(struct b53_de\n \t\t\tdev->vta_regs[2] = chip->vta_regs[2];\n \t\t\tdev->jumbo_pm_reg = chip->jumbo_pm_reg;\n \t\t\tdev->imp_port = chip->imp_port;\n-\t\t\tdev->cpu_port = chip->cpu_port;\n \t\t\tdev->num_vlans = chip->vlans;\n \t\t\tdev->num_arl_bins = chip->arl_bins;\n \t\t\tdev->num_arl_buckets = chip->arl_buckets;\n@@ -2619,13 +2599,6 @@ static int b53_switch_init(struct b53_de\n \t\t\tbreak;\n #endif\n \t\t}\n-\t} else if (dev->chip_id == BCM53115_DEVICE_ID) {\n-\t\tu64 strap_value;\n-\n-\t\tb53_read48(dev, B53_STAT_PAGE, B53_STRAP_VALUE, &strap_value);\n-\t\t/* use second IMP port if GMII is enabled */\n-\t\tif (strap_value & SV_GMII_CTRL_115)\n-\t\t\tdev->cpu_port = 5;\n \t}\n \n \tdev->num_ports = fls(dev->enabled_ports);\n--- a/drivers/net/dsa/b53/b53_priv.h\n+++ b/drivers/net/dsa/b53/b53_priv.h\n@@ -124,7 +124,6 @@ struct b53_device {\n \t/* used ports mask */\n \tu16 enabled_ports;\n \tunsigned int imp_port;\n-\tunsigned int cpu_port;\n \n \t/* connect specific data */\n \tu8 current_page;\n"
  },
  {
    "path": "target/linux/generic/backport-5.15/745-v5.16-01-net-phy-at803x-add-support-for-qca-8327-A-variant.patch",
    "content": "From b4df02b562f4aa14ff6811f30e1b4d2159585c59 Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Sun, 19 Sep 2021 18:28:15 +0200\nSubject: net: phy: at803x: add support for qca 8327 A variant internal phy\n\nFor qca8327 internal phy there are 2 different switch variant with 2\ndifferent phy id. Add this missing variant so the internal phy can be\ncorrectly identified and fixed.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nReviewed-by: Andrew Lunn <andrew@lunn.ch>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/phy/at803x.c | 25 ++++++++++++++++++++-----\n 1 file changed, 20 insertions(+), 5 deletions(-)\n\n--- a/drivers/net/phy/at803x.c\n+++ b/drivers/net/phy/at803x.c\n@@ -150,7 +150,8 @@\n #define ATH8035_PHY_ID\t\t\t\t0x004dd072\n #define AT8030_PHY_ID_MASK\t\t\t0xffffffef\n \n-#define QCA8327_PHY_ID\t\t\t\t0x004dd034\n+#define QCA8327_A_PHY_ID\t\t\t0x004dd033\n+#define QCA8327_B_PHY_ID\t\t\t0x004dd034\n #define QCA8337_PHY_ID\t\t\t\t0x004dd036\n #define QCA8K_PHY_ID_MASK\t\t\t0xffffffff\n \n@@ -1413,10 +1414,23 @@ static struct phy_driver at803x_driver[]\n \t.get_strings = at803x_get_strings,\n \t.get_stats = at803x_get_stats,\n }, {\n-\t/* QCA8327 */\n-\t.phy_id = QCA8327_PHY_ID,\n+\t/* QCA8327-A from switch QCA8327-AL1A */\n+\t.phy_id = QCA8327_A_PHY_ID,\n \t.phy_id_mask = QCA8K_PHY_ID_MASK,\n-\t.name = \"QCA PHY 8327\",\n+\t.name = \"QCA PHY 8327-A\",\n+\t/* PHY_GBIT_FEATURES */\n+\t.probe = at803x_probe,\n+\t.flags = PHY_IS_INTERNAL,\n+\t.config_init = qca83xx_config_init,\n+\t.soft_reset = genphy_soft_reset,\n+\t.get_sset_count = at803x_get_sset_count,\n+\t.get_strings = at803x_get_strings,\n+\t.get_stats = at803x_get_stats,\n+}, {\n+\t/* QCA8327-B from switch QCA8327-BL1A */\n+\t.phy_id = QCA8327_B_PHY_ID,\n+\t.phy_id_mask = QCA8K_PHY_ID_MASK,\n+\t.name = \"QCA PHY 8327-B\",\n \t/* PHY_GBIT_FEATURES */\n \t.probe = at803x_probe,\n \t.flags = PHY_IS_INTERNAL,\n@@ -1436,7 +1450,8 @@ static struct mdio_device_id __maybe_unu\n \t{ PHY_ID_MATCH_EXACT(ATH8035_PHY_ID) },\n \t{ PHY_ID_MATCH_EXACT(ATH9331_PHY_ID) },\n \t{ PHY_ID_MATCH_EXACT(QCA8337_PHY_ID) },\n-\t{ PHY_ID_MATCH_EXACT(QCA8327_PHY_ID) },\n+\t{ PHY_ID_MATCH_EXACT(QCA8327_A_PHY_ID) },\n+\t{ PHY_ID_MATCH_EXACT(QCA8327_B_PHY_ID) },\n \t{ }\n };\n \n"
  },
  {
    "path": "target/linux/generic/backport-5.15/745-v5.16-02-net-phy-at803x-add-resume-suspend-function-to-qca83x.patch",
    "content": "From 15b9df4ece17d084f14eb0ca1cf05f2ad497e425 Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Sun, 19 Sep 2021 18:28:16 +0200\nSubject: net: phy: at803x: add resume/suspend function to qca83xx phy\n\nAdd resume/suspend function to qca83xx internal phy.\nWe can't use the at803x generic function as the documentation lacks of\nany support for WoL regs.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nReviewed-by: Andrew Lunn <andrew@lunn.ch>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/phy/at803x.c | 6 ++++++\n 1 file changed, 6 insertions(+)\n\n--- a/drivers/net/phy/at803x.c\n+++ b/drivers/net/phy/at803x.c\n@@ -1413,6 +1413,8 @@ static struct phy_driver at803x_driver[]\n \t.get_sset_count = at803x_get_sset_count,\n \t.get_strings = at803x_get_strings,\n \t.get_stats = at803x_get_stats,\n+\t.suspend\t\t= genphy_suspend,\n+\t.resume\t\t\t= genphy_resume,\n }, {\n \t/* QCA8327-A from switch QCA8327-AL1A */\n \t.phy_id = QCA8327_A_PHY_ID,\n@@ -1426,6 +1428,8 @@ static struct phy_driver at803x_driver[]\n \t.get_sset_count = at803x_get_sset_count,\n \t.get_strings = at803x_get_strings,\n \t.get_stats = at803x_get_stats,\n+\t.suspend\t\t= genphy_suspend,\n+\t.resume\t\t\t= genphy_resume,\n }, {\n \t/* QCA8327-B from switch QCA8327-BL1A */\n \t.phy_id = QCA8327_B_PHY_ID,\n@@ -1439,6 +1443,8 @@ static struct phy_driver at803x_driver[]\n \t.get_sset_count = at803x_get_sset_count,\n \t.get_strings = at803x_get_strings,\n \t.get_stats = at803x_get_stats,\n+\t.suspend\t\t= genphy_suspend,\n+\t.resume\t\t\t= genphy_resume,\n }, };\n \n module_phy_driver(at803x_driver);\n"
  },
  {
    "path": "target/linux/generic/backport-5.15/745-v5.16-03-net-phy-at803x-fix-spacing-and-improve-name-for-83xx.patch",
    "content": "From d44fd8604a4ab92119adb35f05fd87612af722b5 Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Sun, 19 Sep 2021 18:28:17 +0200\nSubject: net: phy: at803x: fix spacing and improve name for 83xx phy\n\nFix spacing and improve name for 83xx phy following other phy in the\nsame driver.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nReviewed-by: Andrew Lunn <andrew@lunn.ch>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/phy/at803x.c | 60 ++++++++++++++++++++++++------------------------\n 1 file changed, 30 insertions(+), 30 deletions(-)\n\n--- a/drivers/net/phy/at803x.c\n+++ b/drivers/net/phy/at803x.c\n@@ -1402,47 +1402,47 @@ static struct phy_driver at803x_driver[]\n \t.config_aneg\t\t= at803x_config_aneg,\n }, {\n \t/* QCA8337 */\n-\t.phy_id = QCA8337_PHY_ID,\n-\t.phy_id_mask = QCA8K_PHY_ID_MASK,\n-\t.name = \"QCA PHY 8337\",\n+\t.phy_id\t\t\t= QCA8337_PHY_ID,\n+\t.phy_id_mask\t\t= QCA8K_PHY_ID_MASK,\n+\t.name\t\t\t= \"Qualcomm Atheros 8337 internal PHY\",\n \t/* PHY_GBIT_FEATURES */\n-\t.probe = at803x_probe,\n-\t.flags = PHY_IS_INTERNAL,\n-\t.config_init = qca83xx_config_init,\n-\t.soft_reset = genphy_soft_reset,\n-\t.get_sset_count = at803x_get_sset_count,\n-\t.get_strings = at803x_get_strings,\n-\t.get_stats = at803x_get_stats,\n+\t.probe\t\t\t= at803x_probe,\n+\t.flags\t\t\t= PHY_IS_INTERNAL,\n+\t.config_init\t\t= qca83xx_config_init,\n+\t.soft_reset\t\t= genphy_soft_reset,\n+\t.get_sset_count\t\t= at803x_get_sset_count,\n+\t.get_strings\t\t= at803x_get_strings,\n+\t.get_stats\t\t= at803x_get_stats,\n \t.suspend\t\t= genphy_suspend,\n \t.resume\t\t\t= genphy_resume,\n }, {\n \t/* QCA8327-A from switch QCA8327-AL1A */\n-\t.phy_id = QCA8327_A_PHY_ID,\n-\t.phy_id_mask = QCA8K_PHY_ID_MASK,\n-\t.name = \"QCA PHY 8327-A\",\n+\t.phy_id\t\t\t= QCA8327_A_PHY_ID,\n+\t.phy_id_mask\t\t= QCA8K_PHY_ID_MASK,\n+\t.name\t\t\t= \"Qualcomm Atheros 8327-A internal PHY\",\n \t/* PHY_GBIT_FEATURES */\n-\t.probe = at803x_probe,\n-\t.flags = PHY_IS_INTERNAL,\n-\t.config_init = qca83xx_config_init,\n-\t.soft_reset = genphy_soft_reset,\n-\t.get_sset_count = at803x_get_sset_count,\n-\t.get_strings = at803x_get_strings,\n-\t.get_stats = at803x_get_stats,\n+\t.probe\t\t\t= at803x_probe,\n+\t.flags\t\t\t= PHY_IS_INTERNAL,\n+\t.config_init\t\t= qca83xx_config_init,\n+\t.soft_reset\t\t= genphy_soft_reset,\n+\t.get_sset_count\t\t= at803x_get_sset_count,\n+\t.get_strings\t\t= at803x_get_strings,\n+\t.get_stats\t\t= at803x_get_stats,\n \t.suspend\t\t= genphy_suspend,\n \t.resume\t\t\t= genphy_resume,\n }, {\n \t/* QCA8327-B from switch QCA8327-BL1A */\n-\t.phy_id = QCA8327_B_PHY_ID,\n-\t.phy_id_mask = QCA8K_PHY_ID_MASK,\n-\t.name = \"QCA PHY 8327-B\",\n+\t.phy_id\t\t\t= QCA8327_B_PHY_ID,\n+\t.phy_id_mask\t\t= QCA8K_PHY_ID_MASK,\n+\t.name\t\t\t= \"Qualcomm Atheros 8327-B internal PHY\",\n \t/* PHY_GBIT_FEATURES */\n-\t.probe = at803x_probe,\n-\t.flags = PHY_IS_INTERNAL,\n-\t.config_init = qca83xx_config_init,\n-\t.soft_reset = genphy_soft_reset,\n-\t.get_sset_count = at803x_get_sset_count,\n-\t.get_strings = at803x_get_strings,\n-\t.get_stats = at803x_get_stats,\n+\t.probe\t\t\t= at803x_probe,\n+\t.flags\t\t\t= PHY_IS_INTERNAL,\n+\t.config_init\t\t= qca83xx_config_init,\n+\t.soft_reset\t\t= genphy_soft_reset,\n+\t.get_sset_count\t\t= at803x_get_sset_count,\n+\t.get_strings\t\t= at803x_get_strings,\n+\t.get_stats\t\t= at803x_get_stats,\n \t.suspend\t\t= genphy_suspend,\n \t.resume\t\t\t= genphy_resume,\n }, };\n"
  },
  {
    "path": "target/linux/generic/backport-5.15/746-v5.16-01-net-phy-at803x-fix-resume-for-QCA8327-phy.patch",
    "content": "From ba3c01ee02ed0d821c9f241f179bbc9457542b8f Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Sun, 10 Oct 2021 00:46:15 +0200\nSubject: net: phy: at803x: fix resume for QCA8327 phy\n\nFrom Documentation phy resume triggers phy reset and restart\nauto-negotiation. Add a dedicated function to wait reset to finish as\nit was notice a regression where port sometime are not reliable after a\nsuspend/resume session. The reset wait logic is copied from phy_poll_reset.\nAdd dedicated suspend function to use genphy_suspend only with QCA8337\nphy and set only additional debug settings for QCA8327. With more test\nit was reported that QCA8327 doesn't proprely support this mode and\nusing this cause the unreliability of the switch ports, especially the\nmalfunction of the port0.\n\nFixes: 15b9df4ece17 (\"net: phy: at803x: add resume/suspend function to qca83xx phy\")\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/phy/at803x.c | 69 +++++++++++++++++++++++++++++++++++++++++++-----\n 1 file changed, 63 insertions(+), 6 deletions(-)\n\n--- a/drivers/net/phy/at803x.c\n+++ b/drivers/net/phy/at803x.c\n@@ -92,9 +92,14 @@\n #define AT803X_DEBUG_REG_5\t\t\t0x05\n #define AT803X_DEBUG_TX_CLK_DLY_EN\t\tBIT(8)\n \n+#define AT803X_DEBUG_REG_HIB_CTRL\t\t0x0b\n+#define   AT803X_DEBUG_HIB_CTRL_SEL_RST_80U\tBIT(10)\n+#define   AT803X_DEBUG_HIB_CTRL_EN_ANY_CHANGE\tBIT(13)\n+\n #define AT803X_DEBUG_REG_3C\t\t\t0x3C\n \n #define AT803X_DEBUG_REG_3D\t\t\t0x3D\n+#define   AT803X_DEBUG_GATE_CLK_IN1000\t\tBIT(6)\n \n #define AT803X_DEBUG_REG_1F\t\t\t0x1F\n #define AT803X_DEBUG_PLL_ON\t\t\tBIT(2)\n@@ -1304,6 +1309,58 @@ static int qca83xx_config_init(struct ph\n \treturn 0;\n }\n \n+static int qca83xx_resume(struct phy_device *phydev)\n+{\n+\tint ret, val;\n+\n+\t/* Skip reset if not suspended */\n+\tif (!phydev->suspended)\n+\t\treturn 0;\n+\n+\t/* Reinit the port, reset values set by suspend */\n+\tqca83xx_config_init(phydev);\n+\n+\t/* Reset the port on port resume */\n+\tphy_set_bits(phydev, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);\n+\n+\t/* On resume from suspend the switch execute a reset and\n+\t * restart auto-negotiation. Wait for reset to complete.\n+\t */\n+\tret = phy_read_poll_timeout(phydev, MII_BMCR, val, !(val & BMCR_RESET),\n+\t\t\t\t    50000, 600000, true);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tmsleep(1);\n+\n+\treturn 0;\n+}\n+\n+static int qca83xx_suspend(struct phy_device *phydev)\n+{\n+\tu16 mask = 0;\n+\n+\t/* Only QCA8337 support actual suspend.\n+\t * QCA8327 cause port unreliability when phy suspend\n+\t * is set.\n+\t */\n+\tif (phydev->drv->phy_id == QCA8337_PHY_ID) {\n+\t\tgenphy_suspend(phydev);\n+\t} else {\n+\t\tmask |= ~(BMCR_SPEED1000 | BMCR_FULLDPLX);\n+\t\tphy_modify(phydev, MII_BMCR, mask, 0);\n+\t}\n+\n+\tat803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_3D,\n+\t\t\t      AT803X_DEBUG_GATE_CLK_IN1000, 0);\n+\n+\tat803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_HIB_CTRL,\n+\t\t\t      AT803X_DEBUG_HIB_CTRL_EN_ANY_CHANGE |\n+\t\t\t      AT803X_DEBUG_HIB_CTRL_SEL_RST_80U, 0);\n+\n+\treturn 0;\n+}\n+\n static struct phy_driver at803x_driver[] = {\n {\n \t/* Qualcomm Atheros AR8035 */\n@@ -1413,8 +1470,8 @@ static struct phy_driver at803x_driver[]\n \t.get_sset_count\t\t= at803x_get_sset_count,\n \t.get_strings\t\t= at803x_get_strings,\n \t.get_stats\t\t= at803x_get_stats,\n-\t.suspend\t\t= genphy_suspend,\n-\t.resume\t\t\t= genphy_resume,\n+\t.suspend\t\t= qca83xx_suspend,\n+\t.resume\t\t\t= qca83xx_resume,\n }, {\n \t/* QCA8327-A from switch QCA8327-AL1A */\n \t.phy_id\t\t\t= QCA8327_A_PHY_ID,\n@@ -1428,8 +1485,8 @@ static struct phy_driver at803x_driver[]\n \t.get_sset_count\t\t= at803x_get_sset_count,\n \t.get_strings\t\t= at803x_get_strings,\n \t.get_stats\t\t= at803x_get_stats,\n-\t.suspend\t\t= genphy_suspend,\n-\t.resume\t\t\t= genphy_resume,\n+\t.suspend\t\t= qca83xx_suspend,\n+\t.resume\t\t\t= qca83xx_resume,\n }, {\n \t/* QCA8327-B from switch QCA8327-BL1A */\n \t.phy_id\t\t\t= QCA8327_B_PHY_ID,\n@@ -1443,8 +1500,8 @@ static struct phy_driver at803x_driver[]\n \t.get_sset_count\t\t= at803x_get_sset_count,\n \t.get_strings\t\t= at803x_get_strings,\n \t.get_stats\t\t= at803x_get_stats,\n-\t.suspend\t\t= genphy_suspend,\n-\t.resume\t\t\t= genphy_resume,\n+\t.suspend\t\t= qca83xx_suspend,\n+\t.resume\t\t\t= qca83xx_resume,\n }, };\n \n module_phy_driver(at803x_driver);\n"
  },
  {
    "path": "target/linux/generic/backport-5.15/746-v5.16-02-net-phy-at803x-add-DAC-amplitude-fix-for-8327-phy.patch",
    "content": "From 1ca8311949aec5c9447645731ef1c6bc5bd71350 Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Sun, 10 Oct 2021 00:46:16 +0200\nSubject: net: phy: at803x: add DAC amplitude fix for 8327 phy\n\nQCA8327 internal phy require DAC amplitude adjustement set to +6% with\n100m speed. Also add additional define to report a change of the same\nreg in QCA8337. (different scope it does set 1000m voltage)\nAdd link_change_notify function to set the proper amplitude adjustement\non PHY_RUNNING state and disable on any other state.\n\nFixes: b4df02b562f4 (\"net: phy: at803x: add support for qca 8327 A variant internal phy\")\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/phy/at803x.c | 33 +++++++++++++++++++++++++++++++++\n 1 file changed, 33 insertions(+)\n\n--- a/drivers/net/phy/at803x.c\n+++ b/drivers/net/phy/at803x.c\n@@ -87,6 +87,8 @@\n #define AT803X_PSSR_MR_AN_COMPLETE\t\t0x0200\n \n #define AT803X_DEBUG_REG_0\t\t\t0x00\n+#define QCA8327_DEBUG_MANU_CTRL_EN\t\tBIT(2)\n+#define QCA8337_DEBUG_MANU_CTRL_EN\t\tGENMASK(3, 2)\n #define AT803X_DEBUG_RX_CLK_DLY_EN\t\tBIT(15)\n \n #define AT803X_DEBUG_REG_5\t\t\t0x05\n@@ -1306,9 +1308,37 @@ static int qca83xx_config_init(struct ph\n \t\tbreak;\n \t}\n \n+\t/* QCA8327 require DAC amplitude adjustment for 100m set to +6%.\n+\t * Disable on init and enable only with 100m speed following\n+\t * qca original source code.\n+\t */\n+\tif (phydev->drv->phy_id == QCA8327_A_PHY_ID ||\n+\t    phydev->drv->phy_id == QCA8327_B_PHY_ID)\n+\t\tat803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_0,\n+\t\t\t\t      QCA8327_DEBUG_MANU_CTRL_EN, 0);\n+\n \treturn 0;\n }\n \n+static void qca83xx_link_change_notify(struct phy_device *phydev)\n+{\n+\t/* QCA8337 doesn't require DAC Amplitude adjustement */\n+\tif (phydev->drv->phy_id == QCA8337_PHY_ID)\n+\t\treturn;\n+\n+\t/* Set DAC Amplitude adjustment to +6% for 100m on link running */\n+\tif (phydev->state == PHY_RUNNING) {\n+\t\tif (phydev->speed == SPEED_100)\n+\t\t\tat803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_0,\n+\t\t\t\t\t      QCA8327_DEBUG_MANU_CTRL_EN,\n+\t\t\t\t\t      QCA8327_DEBUG_MANU_CTRL_EN);\n+\t} else {\n+\t\t/* Reset DAC Amplitude adjustment */\n+\t\tat803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_0,\n+\t\t\t\t      QCA8327_DEBUG_MANU_CTRL_EN, 0);\n+\t}\n+}\n+\n static int qca83xx_resume(struct phy_device *phydev)\n {\n \tint ret, val;\n@@ -1463,6 +1493,7 @@ static struct phy_driver at803x_driver[]\n \t.phy_id_mask\t\t= QCA8K_PHY_ID_MASK,\n \t.name\t\t\t= \"Qualcomm Atheros 8337 internal PHY\",\n \t/* PHY_GBIT_FEATURES */\n+\t.link_change_notify\t= qca83xx_link_change_notify,\n \t.probe\t\t\t= at803x_probe,\n \t.flags\t\t\t= PHY_IS_INTERNAL,\n \t.config_init\t\t= qca83xx_config_init,\n@@ -1478,6 +1509,7 @@ static struct phy_driver at803x_driver[]\n \t.phy_id_mask\t\t= QCA8K_PHY_ID_MASK,\n \t.name\t\t\t= \"Qualcomm Atheros 8327-A internal PHY\",\n \t/* PHY_GBIT_FEATURES */\n+\t.link_change_notify\t= qca83xx_link_change_notify,\n \t.probe\t\t\t= at803x_probe,\n \t.flags\t\t\t= PHY_IS_INTERNAL,\n \t.config_init\t\t= qca83xx_config_init,\n@@ -1493,6 +1525,7 @@ static struct phy_driver at803x_driver[]\n \t.phy_id_mask\t\t= QCA8K_PHY_ID_MASK,\n \t.name\t\t\t= \"Qualcomm Atheros 8327-B internal PHY\",\n \t/* PHY_GBIT_FEATURES */\n+\t.link_change_notify\t= qca83xx_link_change_notify,\n \t.probe\t\t\t= at803x_probe,\n \t.flags\t\t\t= PHY_IS_INTERNAL,\n \t.config_init\t\t= qca83xx_config_init,\n"
  },
  {
    "path": "target/linux/generic/backport-5.15/746-v5.16-03-net-phy-at803x-enable-prefer-master-for-83xx-interna.patch",
    "content": "From 9d1c29b4028557a496be9c5eb2b4b86063700636 Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Sun, 10 Oct 2021 00:46:17 +0200\nSubject: net: phy: at803x: enable prefer master for 83xx internal phy\n\nFrom original QCA source code the port was set to prefer master as port\ntype in 1000BASE-T mode. Apply the same settings also here.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nReviewed-by: Andrew Lunn <andrew@lunn.ch>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/phy/at803x.c | 3 +++\n 1 file changed, 3 insertions(+)\n\n--- a/drivers/net/phy/at803x.c\n+++ b/drivers/net/phy/at803x.c\n@@ -1317,6 +1317,9 @@ static int qca83xx_config_init(struct ph\n \t\tat803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_0,\n \t\t\t\t      QCA8327_DEBUG_MANU_CTRL_EN, 0);\n \n+\t/* Following original QCA sourcecode set port to prefer master */\n+\tphy_set_bits(phydev, MII_CTRL1000, CTL1000_PREFER_MASTER);\n+\n \treturn 0;\n }\n \n"
  },
  {
    "path": "target/linux/generic/backport-5.15/746-v5.16-04-net-phy-at803x-better-describe-debug-regs.patch",
    "content": "From 67999555ff42e91de7654488d9a7735bd9e84555 Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Sun, 10 Oct 2021 00:46:18 +0200\nSubject: net: phy: at803x: better describe debug regs\n\nGive a name to known debug regs from Documentation instead of using\nunknown hex values.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nReviewed-by: Andrew Lunn <andrew@lunn.ch>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/phy/at803x.c | 30 +++++++++++++++---------------\n 1 file changed, 15 insertions(+), 15 deletions(-)\n\n--- a/drivers/net/phy/at803x.c\n+++ b/drivers/net/phy/at803x.c\n@@ -86,12 +86,12 @@\n #define AT803X_PSSR\t\t\t\t0x11\t/*PHY-Specific Status Register*/\n #define AT803X_PSSR_MR_AN_COMPLETE\t\t0x0200\n \n-#define AT803X_DEBUG_REG_0\t\t\t0x00\n+#define AT803X_DEBUG_ANALOG_TEST_CTRL\t\t0x00\n #define QCA8327_DEBUG_MANU_CTRL_EN\t\tBIT(2)\n #define QCA8337_DEBUG_MANU_CTRL_EN\t\tGENMASK(3, 2)\n #define AT803X_DEBUG_RX_CLK_DLY_EN\t\tBIT(15)\n \n-#define AT803X_DEBUG_REG_5\t\t\t0x05\n+#define AT803X_DEBUG_SYSTEM_CTRL_MODE\t\t0x05\n #define AT803X_DEBUG_TX_CLK_DLY_EN\t\tBIT(8)\n \n #define AT803X_DEBUG_REG_HIB_CTRL\t\t0x0b\n@@ -100,7 +100,7 @@\n \n #define AT803X_DEBUG_REG_3C\t\t\t0x3C\n \n-#define AT803X_DEBUG_REG_3D\t\t\t0x3D\n+#define AT803X_DEBUG_REG_GREEN\t\t\t0x3D\n #define   AT803X_DEBUG_GATE_CLK_IN1000\t\tBIT(6)\n \n #define AT803X_DEBUG_REG_1F\t\t\t0x1F\n@@ -284,25 +284,25 @@ static int at803x_read_page(struct phy_d\n \n static int at803x_enable_rx_delay(struct phy_device *phydev)\n {\n-\treturn at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_0, 0,\n+\treturn at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 0,\n \t\t\t\t     AT803X_DEBUG_RX_CLK_DLY_EN);\n }\n \n static int at803x_enable_tx_delay(struct phy_device *phydev)\n {\n-\treturn at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_5, 0,\n+\treturn at803x_debug_reg_mask(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE, 0,\n \t\t\t\t     AT803X_DEBUG_TX_CLK_DLY_EN);\n }\n \n static int at803x_disable_rx_delay(struct phy_device *phydev)\n {\n-\treturn at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_0,\n+\treturn at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL,\n \t\t\t\t     AT803X_DEBUG_RX_CLK_DLY_EN, 0);\n }\n \n static int at803x_disable_tx_delay(struct phy_device *phydev)\n {\n-\treturn at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_5,\n+\treturn at803x_debug_reg_mask(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE,\n \t\t\t\t     AT803X_DEBUG_TX_CLK_DLY_EN, 0);\n }\n \n@@ -1292,9 +1292,9 @@ static int qca83xx_config_init(struct ph\n \tswitch (switch_revision) {\n \tcase 1:\n \t\t/* For 100M waveform */\n-\t\tat803x_debug_reg_write(phydev, AT803X_DEBUG_REG_0, 0x02ea);\n+\t\tat803x_debug_reg_write(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 0x02ea);\n \t\t/* Turn on Gigabit clock */\n-\t\tat803x_debug_reg_write(phydev, AT803X_DEBUG_REG_3D, 0x68a0);\n+\t\tat803x_debug_reg_write(phydev, AT803X_DEBUG_REG_GREEN, 0x68a0);\n \t\tbreak;\n \n \tcase 2:\n@@ -1302,8 +1302,8 @@ static int qca83xx_config_init(struct ph\n \t\tfallthrough;\n \tcase 4:\n \t\tphy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_AZ_DEBUG, 0x803f);\n-\t\tat803x_debug_reg_write(phydev, AT803X_DEBUG_REG_3D, 0x6860);\n-\t\tat803x_debug_reg_write(phydev, AT803X_DEBUG_REG_5, 0x2c46);\n+\t\tat803x_debug_reg_write(phydev, AT803X_DEBUG_REG_GREEN, 0x6860);\n+\t\tat803x_debug_reg_write(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE, 0x2c46);\n \t\tat803x_debug_reg_write(phydev, AT803X_DEBUG_REG_3C, 0x6000);\n \t\tbreak;\n \t}\n@@ -1314,7 +1314,7 @@ static int qca83xx_config_init(struct ph\n \t */\n \tif (phydev->drv->phy_id == QCA8327_A_PHY_ID ||\n \t    phydev->drv->phy_id == QCA8327_B_PHY_ID)\n-\t\tat803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_0,\n+\t\tat803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL,\n \t\t\t\t      QCA8327_DEBUG_MANU_CTRL_EN, 0);\n \n \t/* Following original QCA sourcecode set port to prefer master */\n@@ -1332,12 +1332,12 @@ static void qca83xx_link_change_notify(s\n \t/* Set DAC Amplitude adjustment to +6% for 100m on link running */\n \tif (phydev->state == PHY_RUNNING) {\n \t\tif (phydev->speed == SPEED_100)\n-\t\t\tat803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_0,\n+\t\t\tat803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL,\n \t\t\t\t\t      QCA8327_DEBUG_MANU_CTRL_EN,\n \t\t\t\t\t      QCA8327_DEBUG_MANU_CTRL_EN);\n \t} else {\n \t\t/* Reset DAC Amplitude adjustment */\n-\t\tat803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_0,\n+\t\tat803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL,\n \t\t\t\t      QCA8327_DEBUG_MANU_CTRL_EN, 0);\n \t}\n }\n@@ -1384,7 +1384,7 @@ static int qca83xx_suspend(struct phy_de\n \t\tphy_modify(phydev, MII_BMCR, mask, 0);\n \t}\n \n-\tat803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_3D,\n+\tat803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_GREEN,\n \t\t\t      AT803X_DEBUG_GATE_CLK_IN1000, 0);\n \n \tat803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_HIB_CTRL,\n"
  },
  {
    "path": "target/linux/generic/backport-5.15/747-v5.16-01-dsa-qca8k-add-mac-power-sel-support.patch",
    "content": "From d8b6f5bae6d3b648a67b6958cb98e4e97256d652 Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Thu, 14 Oct 2021 00:39:06 +0200\nSubject: dsa: qca8k: add mac_power_sel support\n\nAdd missing mac power sel support needed for ipq8064/5 SoC that require\n1.8v for the internal regulator port instead of the default 1.5v.\nIf other device needs this, consider adding a dedicated binding to\nsupport this.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nReviewed-by: Vladimir Oltean <olteanv@gmail.com>\nReviewed-by: Florian Fainelli <f.fainelli@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/dsa/qca8k.c | 31 +++++++++++++++++++++++++++++++\n drivers/net/dsa/qca8k.h |  5 +++++\n 2 files changed, 36 insertions(+)\n\n--- a/drivers/net/dsa/qca8k.c\n+++ b/drivers/net/dsa/qca8k.c\n@@ -951,6 +951,33 @@ qca8k_setup_of_rgmii_delay(struct qca8k_\n }\n \n static int\n+qca8k_setup_mac_pwr_sel(struct qca8k_priv *priv)\n+{\n+\tu32 mask = 0;\n+\tint ret = 0;\n+\n+\t/* SoC specific settings for ipq8064.\n+\t * If more device require this consider adding\n+\t * a dedicated binding.\n+\t */\n+\tif (of_machine_is_compatible(\"qcom,ipq8064\"))\n+\t\tmask |= QCA8K_MAC_PWR_RGMII0_1_8V;\n+\n+\t/* SoC specific settings for ipq8065 */\n+\tif (of_machine_is_compatible(\"qcom,ipq8065\"))\n+\t\tmask |= QCA8K_MAC_PWR_RGMII1_1_8V;\n+\n+\tif (mask) {\n+\t\tret = qca8k_rmw(priv, QCA8K_REG_MAC_PWR_SEL,\n+\t\t\t\tQCA8K_MAC_PWR_RGMII0_1_8V |\n+\t\t\t\tQCA8K_MAC_PWR_RGMII1_1_8V,\n+\t\t\t\tmask);\n+\t}\n+\n+\treturn ret;\n+}\n+\n+static int\n qca8k_setup(struct dsa_switch *ds)\n {\n \tstruct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;\n@@ -979,6 +1006,10 @@ qca8k_setup(struct dsa_switch *ds)\n \tif (ret)\n \t\treturn ret;\n \n+\tret = qca8k_setup_mac_pwr_sel(priv);\n+\tif (ret)\n+\t\treturn ret;\n+\n \t/* Enable CPU Port */\n \tret = qca8k_reg_set(priv, QCA8K_REG_GLOBAL_FW_CTRL0,\n \t\t\t    QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN);\n--- a/drivers/net/dsa/qca8k.h\n+++ b/drivers/net/dsa/qca8k.h\n@@ -100,6 +100,11 @@\n #define   QCA8K_SGMII_MODE_CTRL_PHY\t\t\t(1 << 22)\n #define   QCA8K_SGMII_MODE_CTRL_MAC\t\t\t(2 << 22)\n \n+/* MAC_PWR_SEL registers */\n+#define QCA8K_REG_MAC_PWR_SEL\t\t\t\t0x0e4\n+#define   QCA8K_MAC_PWR_RGMII1_1_8V\t\t\tBIT(18)\n+#define   QCA8K_MAC_PWR_RGMII0_1_8V\t\t\tBIT(19)\n+\n /* EEE control registers */\n #define QCA8K_REG_EEE_CTRL\t\t\t\t0x100\n #define  QCA8K_REG_EEE_CTRL_LPI_EN(_i)\t\t\t((_i + 1) * 2)\n"
  },
  {
    "path": "target/linux/generic/backport-5.15/747-v5.16-02-dt-bindings-net-dsa-qca8k-Add-SGMII-clock-phase-prop.patch",
    "content": "From fdbf35df9c091db9c46e57e9938e3f7a4f603a7c Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Thu, 14 Oct 2021 00:39:07 +0200\nSubject: dt-bindings: net: dsa: qca8k: Add SGMII clock phase properties\n\nAdd names and descriptions of additional PORT0_PAD_CTRL properties.\nqca,sgmii-(rx|tx)clk-falling-edge are for setting the respective clock\nphase to failling edge.\n\nCo-developed-by: Matthew Hagan <mnhagan88@gmail.com>\nSigned-off-by: Matthew Hagan <mnhagan88@gmail.com>\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n Documentation/devicetree/bindings/net/dsa/qca8k.txt | 4 ++++\n 1 file changed, 4 insertions(+)\n\n--- a/Documentation/devicetree/bindings/net/dsa/qca8k.txt\n+++ b/Documentation/devicetree/bindings/net/dsa/qca8k.txt\n@@ -37,6 +37,10 @@ A CPU port node has the following option\n                           managed entity. See\n                           Documentation/devicetree/bindings/net/fixed-link.txt\n                           for details.\n+- qca,sgmii-rxclk-falling-edge: Set the receive clock phase to falling edge.\n+                                Mostly used in qca8327 with CPU port 0 set to\n+                                sgmii.\n+- qca,sgmii-txclk-falling-edge: Set the transmit clock phase to falling edge.\n \n For QCA8K the 'fixed-link' sub-node supports only the following properties:\n \n"
  },
  {
    "path": "target/linux/generic/backport-5.15/747-v5.16-03-net-dsa-qca8k-add-support-for-sgmii-falling-edge.patch",
    "content": "From 6c43809bf1bee76c434e365a26546a92a5fbec14 Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Thu, 14 Oct 2021 00:39:08 +0200\nSubject: net: dsa: qca8k: add support for sgmii falling edge\n\nAdd support for this in the qca8k driver. Also add support for SGMII\nrx/tx clock falling edge. This is only present for pad0, pad5 and\npad6 have these bit reserved from Documentation. Add a comment that this\nis hardcoded to PAD0 as qca8327/28/34/37 have an unique sgmii line and\nsetting falling in port0 applies to both configuration with sgmii used\nfor port0 or port6.\n\nCo-developed-by: Matthew Hagan <mnhagan88@gmail.com>\nSigned-off-by: Matthew Hagan <mnhagan88@gmail.com>\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/dsa/qca8k.c | 63 +++++++++++++++++++++++++++++++++++++++++++++++++\n drivers/net/dsa/qca8k.h |  4 ++++\n 2 files changed, 67 insertions(+)\n\n--- a/drivers/net/dsa/qca8k.c\n+++ b/drivers/net/dsa/qca8k.c\n@@ -978,6 +978,42 @@ qca8k_setup_mac_pwr_sel(struct qca8k_pri\n }\n \n static int\n+qca8k_parse_port_config(struct qca8k_priv *priv)\n+{\n+\tstruct device_node *port_dn;\n+\tphy_interface_t mode;\n+\tstruct dsa_port *dp;\n+\tint port, ret;\n+\n+\t/* We have 2 CPU port. Check them */\n+\tfor (port = 0; port < QCA8K_NUM_PORTS; port++) {\n+\t\t/* Skip every other port */\n+\t\tif (port != 0 && port != 6)\n+\t\t\tcontinue;\n+\n+\t\tdp = dsa_to_port(priv->ds, port);\n+\t\tport_dn = dp->dn;\n+\n+\t\tif (!of_device_is_available(port_dn))\n+\t\t\tcontinue;\n+\n+\t\tret = of_get_phy_mode(port_dn, &mode);\n+\t\tif (ret)\n+\t\t\tcontinue;\n+\n+\t\tif (mode == PHY_INTERFACE_MODE_SGMII) {\n+\t\t\tif (of_property_read_bool(port_dn, \"qca,sgmii-txclk-falling-edge\"))\n+\t\t\t\tpriv->sgmii_tx_clk_falling_edge = true;\n+\n+\t\t\tif (of_property_read_bool(port_dn, \"qca,sgmii-rxclk-falling-edge\"))\n+\t\t\t\tpriv->sgmii_rx_clk_falling_edge = true;\n+\t\t}\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int\n qca8k_setup(struct dsa_switch *ds)\n {\n \tstruct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;\n@@ -990,6 +1026,11 @@ qca8k_setup(struct dsa_switch *ds)\n \t\treturn -EINVAL;\n \t}\n \n+\t/* Parse CPU port config to be later used in phy_link mac_config */\n+\tret = qca8k_parse_port_config(priv);\n+\tif (ret)\n+\t\treturn ret;\n+\n \tmutex_init(&priv->reg_mutex);\n \n \t/* Start by setting up the register mapping */\n@@ -1274,6 +1315,28 @@ qca8k_phylink_mac_config(struct dsa_swit\n \t\t}\n \n \t\tqca8k_write(priv, QCA8K_REG_SGMII_CTRL, val);\n+\n+\t\t/* For qca8327/qca8328/qca8334/qca8338 sgmii is unique and\n+\t\t * falling edge is set writing in the PORT0 PAD reg\n+\t\t */\n+\t\tif (priv->switch_id == QCA8K_ID_QCA8327 ||\n+\t\t    priv->switch_id == QCA8K_ID_QCA8337)\n+\t\t\treg = QCA8K_REG_PORT0_PAD_CTRL;\n+\n+\t\tval = 0;\n+\n+\t\t/* SGMII Clock phase configuration */\n+\t\tif (priv->sgmii_rx_clk_falling_edge)\n+\t\t\tval |= QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE;\n+\n+\t\tif (priv->sgmii_tx_clk_falling_edge)\n+\t\t\tval |= QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE;\n+\n+\t\tif (val)\n+\t\t\tret = qca8k_rmw(priv, reg,\n+\t\t\t\t\tQCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE |\n+\t\t\t\t\tQCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE,\n+\t\t\t\t\tval);\n \t\tbreak;\n \tdefault:\n \t\tdev_err(ds->dev, \"xMII mode %s not supported for port %d\\n\",\n--- a/drivers/net/dsa/qca8k.h\n+++ b/drivers/net/dsa/qca8k.h\n@@ -35,6 +35,8 @@\n #define   QCA8K_MASK_CTRL_DEVICE_ID_MASK\t\tGENMASK(15, 8)\n #define   QCA8K_MASK_CTRL_DEVICE_ID(x)\t\t\t((x) >> 8)\n #define QCA8K_REG_PORT0_PAD_CTRL\t\t\t0x004\n+#define   QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE\tBIT(19)\n+#define   QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE\tBIT(18)\n #define QCA8K_REG_PORT5_PAD_CTRL\t\t\t0x008\n #define QCA8K_REG_PORT6_PAD_CTRL\t\t\t0x00c\n #define   QCA8K_PORT_PAD_RGMII_EN\t\t\tBIT(26)\n@@ -260,6 +262,8 @@ struct qca8k_priv {\n \tu8 switch_revision;\n \tu8 rgmii_tx_delay;\n \tu8 rgmii_rx_delay;\n+\tbool sgmii_rx_clk_falling_edge;\n+\tbool sgmii_tx_clk_falling_edge;\n \tbool legacy_phy_port_mapping;\n \tstruct regmap *regmap;\n \tstruct mii_bus *bus;\n"
  },
  {
    "path": "target/linux/generic/backport-5.15/747-v5.16-04-dt-bindings-net-dsa-qca8k-Document-support-for-CPU-p.patch",
    "content": "From 731d613338ec6de482053ffa3f71be2325b0f8eb Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Thu, 14 Oct 2021 00:39:09 +0200\nSubject: dt-bindings: net: dsa: qca8k: Document support for CPU port 6\n\nThe switch now support CPU port to be set 6 instead of be hardcoded to\n0. Document support for it and describe logic selection.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n Documentation/devicetree/bindings/net/dsa/qca8k.txt | 6 +++++-\n 1 file changed, 5 insertions(+), 1 deletion(-)\n\n--- a/Documentation/devicetree/bindings/net/dsa/qca8k.txt\n+++ b/Documentation/devicetree/bindings/net/dsa/qca8k.txt\n@@ -29,7 +29,11 @@ the mdio MASTER is used as communication\n Don't use mixed external and internal mdio-bus configurations, as this is\n not supported by the hardware.\n \n-The CPU port of this switch is always port 0.\n+This switch support 2 CPU port. Normally and advised configuration is with\n+CPU port set to port 0. It is also possible to set the CPU port to port 6\n+if the device requires it. The driver will configure the switch to the defined\n+port. With both CPU port declared the first CPU port is selected as primary\n+and the secondary CPU ignored.\n \n A CPU port node has the following optional node:\n \n"
  },
  {
    "path": "target/linux/generic/backport-5.15/747-v5.16-05-net-dsa-qca8k-add-support-for-cpu-port-6.patch",
    "content": "From 3fcf734aa482487df83cf8f18608438fcf59127f Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Thu, 14 Oct 2021 00:39:10 +0200\nSubject: net: dsa: qca8k: add support for cpu port 6\n\nCurrently CPU port is always hardcoded to port 0. This switch have 2 CPU\nports. The original intention of this driver seems to be use the\nmac06_exchange bit to swap MAC0 with MAC6 in the strange configuration\nwhere device have connected only the CPU port 6. To skip the\nintroduction of a new binding, rework the driver to address the\nsecondary CPU port as primary and drop any reference of hardcoded port.\nWith configuration of mac06 exchange, just skip the definition of port0\nand define the CPU port as a secondary. The driver will autoconfigure\nthe switch to use that as the primary CPU port.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/dsa/qca8k.c | 51 ++++++++++++++++++++++++++++++++++---------------\n drivers/net/dsa/qca8k.h |  2 --\n 2 files changed, 36 insertions(+), 17 deletions(-)\n\n--- a/drivers/net/dsa/qca8k.c\n+++ b/drivers/net/dsa/qca8k.c\n@@ -977,6 +977,22 @@ qca8k_setup_mac_pwr_sel(struct qca8k_pri\n \treturn ret;\n }\n \n+static int qca8k_find_cpu_port(struct dsa_switch *ds)\n+{\n+\tstruct qca8k_priv *priv = ds->priv;\n+\n+\t/* Find the connected cpu port. Valid port are 0 or 6 */\n+\tif (dsa_is_cpu_port(ds, 0))\n+\t\treturn 0;\n+\n+\tdev_dbg(priv->dev, \"port 0 is not the CPU port. Checking port 6\");\n+\n+\tif (dsa_is_cpu_port(ds, 6))\n+\t\treturn 6;\n+\n+\treturn -EINVAL;\n+}\n+\n static int\n qca8k_parse_port_config(struct qca8k_priv *priv)\n {\n@@ -1017,13 +1033,13 @@ static int\n qca8k_setup(struct dsa_switch *ds)\n {\n \tstruct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;\n-\tint ret, i;\n+\tint cpu_port, ret, i;\n \tu32 mask;\n \n-\t/* Make sure that port 0 is the cpu port */\n-\tif (!dsa_is_cpu_port(ds, 0)) {\n-\t\tdev_err(priv->dev, \"port 0 is not the CPU port\");\n-\t\treturn -EINVAL;\n+\tcpu_port = qca8k_find_cpu_port(ds);\n+\tif (cpu_port < 0) {\n+\t\tdev_err(priv->dev, \"No cpu port configured in both cpu port0 and port6\");\n+\t\treturn cpu_port;\n \t}\n \n \t/* Parse CPU port config to be later used in phy_link mac_config */\n@@ -1065,7 +1081,7 @@ qca8k_setup(struct dsa_switch *ds)\n \t\tdev_warn(priv->dev, \"mib init failed\");\n \n \t/* Enable QCA header mode on the cpu port */\n-\tret = qca8k_write(priv, QCA8K_REG_PORT_HDR_CTRL(QCA8K_CPU_PORT),\n+\tret = qca8k_write(priv, QCA8K_REG_PORT_HDR_CTRL(cpu_port),\n \t\t\t  QCA8K_PORT_HDR_CTRL_ALL << QCA8K_PORT_HDR_CTRL_TX_S |\n \t\t\t  QCA8K_PORT_HDR_CTRL_ALL << QCA8K_PORT_HDR_CTRL_RX_S);\n \tif (ret) {\n@@ -1087,10 +1103,10 @@ qca8k_setup(struct dsa_switch *ds)\n \n \t/* Forward all unknown frames to CPU port for Linux processing */\n \tret = qca8k_write(priv, QCA8K_REG_GLOBAL_FW_CTRL1,\n-\t\t\t  BIT(0) << QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_S |\n-\t\t\t  BIT(0) << QCA8K_GLOBAL_FW_CTRL1_BC_DP_S |\n-\t\t\t  BIT(0) << QCA8K_GLOBAL_FW_CTRL1_MC_DP_S |\n-\t\t\t  BIT(0) << QCA8K_GLOBAL_FW_CTRL1_UC_DP_S);\n+\t\t\t  BIT(cpu_port) << QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_S |\n+\t\t\t  BIT(cpu_port) << QCA8K_GLOBAL_FW_CTRL1_BC_DP_S |\n+\t\t\t  BIT(cpu_port) << QCA8K_GLOBAL_FW_CTRL1_MC_DP_S |\n+\t\t\t  BIT(cpu_port) << QCA8K_GLOBAL_FW_CTRL1_UC_DP_S);\n \tif (ret)\n \t\treturn ret;\n \n@@ -1098,7 +1114,7 @@ qca8k_setup(struct dsa_switch *ds)\n \tfor (i = 0; i < QCA8K_NUM_PORTS; i++) {\n \t\t/* CPU port gets connected to all user ports of the switch */\n \t\tif (dsa_is_cpu_port(ds, i)) {\n-\t\t\tret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(QCA8K_CPU_PORT),\n+\t\t\tret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(cpu_port),\n \t\t\t\t\tQCA8K_PORT_LOOKUP_MEMBER, dsa_user_ports(ds));\n \t\t\tif (ret)\n \t\t\t\treturn ret;\n@@ -1110,7 +1126,7 @@ qca8k_setup(struct dsa_switch *ds)\n \n \t\t\tret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i),\n \t\t\t\t\tQCA8K_PORT_LOOKUP_MEMBER,\n-\t\t\t\t\tBIT(QCA8K_CPU_PORT));\n+\t\t\t\t\tBIT(cpu_port));\n \t\t\tif (ret)\n \t\t\t\treturn ret;\n \n@@ -1616,9 +1632,12 @@ static int\n qca8k_port_bridge_join(struct dsa_switch *ds, int port, struct net_device *br)\n {\n \tstruct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;\n-\tint port_mask = BIT(QCA8K_CPU_PORT);\n+\tint port_mask, cpu_port;\n \tint i, ret;\n \n+\tcpu_port = dsa_to_port(ds, port)->cpu_dp->index;\n+\tport_mask = BIT(cpu_port);\n+\n \tfor (i = 1; i < QCA8K_NUM_PORTS; i++) {\n \t\tif (dsa_to_port(ds, i)->bridge_dev != br)\n \t\t\tcontinue;\n@@ -1645,7 +1664,9 @@ static void\n qca8k_port_bridge_leave(struct dsa_switch *ds, int port, struct net_device *br)\n {\n \tstruct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;\n-\tint i;\n+\tint cpu_port, i;\n+\n+\tcpu_port = dsa_to_port(ds, port)->cpu_dp->index;\n \n \tfor (i = 1; i < QCA8K_NUM_PORTS; i++) {\n \t\tif (dsa_to_port(ds, i)->bridge_dev != br)\n@@ -1662,7 +1683,7 @@ qca8k_port_bridge_leave(struct dsa_switc\n \t * this port\n \t */\n \tqca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),\n-\t\t  QCA8K_PORT_LOOKUP_MEMBER, BIT(QCA8K_CPU_PORT));\n+\t\t  QCA8K_PORT_LOOKUP_MEMBER, BIT(cpu_port));\n }\n \n static int\n--- a/drivers/net/dsa/qca8k.h\n+++ b/drivers/net/dsa/qca8k.h\n@@ -24,8 +24,6 @@\n \n #define QCA8K_NUM_FDB_RECORDS\t\t\t\t2048\n \n-#define QCA8K_CPU_PORT\t\t\t\t\t0\n-\n #define QCA8K_PORT_VID_DEF\t\t\t\t1\n \n /* Global control registers */\n"
  },
  {
    "path": "target/linux/generic/backport-5.15/747-v5.16-06-net-dsa-qca8k-rework-rgmii-delay-logic-and-scan-for-.patch",
    "content": "From 5654ec78dd7e64b1e04777b24007344329e6a63b Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Thu, 14 Oct 2021 00:39:11 +0200\nSubject: net: dsa: qca8k: rework rgmii delay logic and scan for cpu port 6\n\nFuture proof commit. This switch have 2 CPU ports and one valid\nconfiguration is first CPU port set to sgmii and second CPU port set to\nrgmii-id. The current implementation detects delay only for CPU port\nzero set to rgmii and doesn't count any delay set in a secondary CPU\nport. Drop the current delay scan function and move it to the sgmii\nparser function to generalize and implicitly add support for secondary\nCPU port set to rgmii-id. Introduce new logic where delay is enabled\nalso with internal delay binding declared and rgmii set as PHY mode.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/dsa/qca8k.c | 165 ++++++++++++++++++++++++------------------------\n drivers/net/dsa/qca8k.h |  10 ++-\n 2 files changed, 89 insertions(+), 86 deletions(-)\n\n--- a/drivers/net/dsa/qca8k.c\n+++ b/drivers/net/dsa/qca8k.c\n@@ -889,68 +889,6 @@ qca8k_setup_mdio_bus(struct qca8k_priv *\n }\n \n static int\n-qca8k_setup_of_rgmii_delay(struct qca8k_priv *priv)\n-{\n-\tstruct device_node *port_dn;\n-\tphy_interface_t mode;\n-\tstruct dsa_port *dp;\n-\tu32 val;\n-\n-\t/* CPU port is already checked */\n-\tdp = dsa_to_port(priv->ds, 0);\n-\n-\tport_dn = dp->dn;\n-\n-\t/* Check if port 0 is set to the correct type */\n-\tof_get_phy_mode(port_dn, &mode);\n-\tif (mode != PHY_INTERFACE_MODE_RGMII_ID &&\n-\t    mode != PHY_INTERFACE_MODE_RGMII_RXID &&\n-\t    mode != PHY_INTERFACE_MODE_RGMII_TXID) {\n-\t\treturn 0;\n-\t}\n-\n-\tswitch (mode) {\n-\tcase PHY_INTERFACE_MODE_RGMII_ID:\n-\tcase PHY_INTERFACE_MODE_RGMII_RXID:\n-\t\tif (of_property_read_u32(port_dn, \"rx-internal-delay-ps\", &val))\n-\t\t\tval = 2;\n-\t\telse\n-\t\t\t/* Switch regs accept value in ns, convert ps to ns */\n-\t\t\tval = val / 1000;\n-\n-\t\tif (val > QCA8K_MAX_DELAY) {\n-\t\t\tdev_err(priv->dev, \"rgmii rx delay is limited to a max value of 3ns, setting to the max value\");\n-\t\t\tval = 3;\n-\t\t}\n-\n-\t\tpriv->rgmii_rx_delay = val;\n-\t\t/* Stop here if we need to check only for rx delay */\n-\t\tif (mode != PHY_INTERFACE_MODE_RGMII_ID)\n-\t\t\tbreak;\n-\n-\t\tfallthrough;\n-\tcase PHY_INTERFACE_MODE_RGMII_TXID:\n-\t\tif (of_property_read_u32(port_dn, \"tx-internal-delay-ps\", &val))\n-\t\t\tval = 1;\n-\t\telse\n-\t\t\t/* Switch regs accept value in ns, convert ps to ns */\n-\t\t\tval = val / 1000;\n-\n-\t\tif (val > QCA8K_MAX_DELAY) {\n-\t\t\tdev_err(priv->dev, \"rgmii tx delay is limited to a max value of 3ns, setting to the max value\");\n-\t\t\tval = 3;\n-\t\t}\n-\n-\t\tpriv->rgmii_tx_delay = val;\n-\t\tbreak;\n-\tdefault:\n-\t\treturn 0;\n-\t}\n-\n-\treturn 0;\n-}\n-\n-static int\n qca8k_setup_mac_pwr_sel(struct qca8k_priv *priv)\n {\n \tu32 mask = 0;\n@@ -996,19 +934,21 @@ static int qca8k_find_cpu_port(struct ds\n static int\n qca8k_parse_port_config(struct qca8k_priv *priv)\n {\n+\tint port, cpu_port_index = 0, ret;\n \tstruct device_node *port_dn;\n \tphy_interface_t mode;\n \tstruct dsa_port *dp;\n-\tint port, ret;\n+\tu32 delay;\n \n \t/* We have 2 CPU port. Check them */\n-\tfor (port = 0; port < QCA8K_NUM_PORTS; port++) {\n+\tfor (port = 0; port < QCA8K_NUM_PORTS && cpu_port_index < QCA8K_NUM_CPU_PORTS; port++) {\n \t\t/* Skip every other port */\n \t\tif (port != 0 && port != 6)\n \t\t\tcontinue;\n \n \t\tdp = dsa_to_port(priv->ds, port);\n \t\tport_dn = dp->dn;\n+\t\tcpu_port_index++;\n \n \t\tif (!of_device_is_available(port_dn))\n \t\t\tcontinue;\n@@ -1017,12 +957,54 @@ qca8k_parse_port_config(struct qca8k_pri\n \t\tif (ret)\n \t\t\tcontinue;\n \n-\t\tif (mode == PHY_INTERFACE_MODE_SGMII) {\n+\t\tswitch (mode) {\n+\t\tcase PHY_INTERFACE_MODE_RGMII:\n+\t\tcase PHY_INTERFACE_MODE_RGMII_ID:\n+\t\tcase PHY_INTERFACE_MODE_RGMII_TXID:\n+\t\tcase PHY_INTERFACE_MODE_RGMII_RXID:\n+\t\t\tdelay = 0;\n+\n+\t\t\tif (!of_property_read_u32(port_dn, \"tx-internal-delay-ps\", &delay))\n+\t\t\t\t/* Switch regs accept value in ns, convert ps to ns */\n+\t\t\t\tdelay = delay / 1000;\n+\t\t\telse if (mode == PHY_INTERFACE_MODE_RGMII_ID ||\n+\t\t\t\t mode == PHY_INTERFACE_MODE_RGMII_TXID)\n+\t\t\t\tdelay = 1;\n+\n+\t\t\tif (delay > QCA8K_MAX_DELAY) {\n+\t\t\t\tdev_err(priv->dev, \"rgmii tx delay is limited to a max value of 3ns, setting to the max value\");\n+\t\t\t\tdelay = 3;\n+\t\t\t}\n+\n+\t\t\tpriv->rgmii_tx_delay[cpu_port_index] = delay;\n+\n+\t\t\tdelay = 0;\n+\n+\t\t\tif (!of_property_read_u32(port_dn, \"rx-internal-delay-ps\", &delay))\n+\t\t\t\t/* Switch regs accept value in ns, convert ps to ns */\n+\t\t\t\tdelay = delay / 1000;\n+\t\t\telse if (mode == PHY_INTERFACE_MODE_RGMII_ID ||\n+\t\t\t\t mode == PHY_INTERFACE_MODE_RGMII_RXID)\n+\t\t\t\tdelay = 2;\n+\n+\t\t\tif (delay > QCA8K_MAX_DELAY) {\n+\t\t\t\tdev_err(priv->dev, \"rgmii rx delay is limited to a max value of 3ns, setting to the max value\");\n+\t\t\t\tdelay = 3;\n+\t\t\t}\n+\n+\t\t\tpriv->rgmii_rx_delay[cpu_port_index] = delay;\n+\n+\t\t\tbreak;\n+\t\tcase PHY_INTERFACE_MODE_SGMII:\n \t\t\tif (of_property_read_bool(port_dn, \"qca,sgmii-txclk-falling-edge\"))\n \t\t\t\tpriv->sgmii_tx_clk_falling_edge = true;\n \n \t\t\tif (of_property_read_bool(port_dn, \"qca,sgmii-rxclk-falling-edge\"))\n \t\t\t\tpriv->sgmii_rx_clk_falling_edge = true;\n+\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tcontinue;\n \t\t}\n \t}\n \n@@ -1059,10 +1041,6 @@ qca8k_setup(struct dsa_switch *ds)\n \tif (ret)\n \t\treturn ret;\n \n-\tret = qca8k_setup_of_rgmii_delay(priv);\n-\tif (ret)\n-\t\treturn ret;\n-\n \tret = qca8k_setup_mac_pwr_sel(priv);\n \tif (ret)\n \t\treturn ret;\n@@ -1229,8 +1207,8 @@ qca8k_phylink_mac_config(struct dsa_swit\n \t\t\t const struct phylink_link_state *state)\n {\n \tstruct qca8k_priv *priv = ds->priv;\n-\tu32 reg, val;\n-\tint ret;\n+\tint cpu_port_index, ret;\n+\tu32 reg, val, delay;\n \n \tswitch (port) {\n \tcase 0: /* 1st CPU port */\n@@ -1242,6 +1220,7 @@ qca8k_phylink_mac_config(struct dsa_swit\n \t\t\treturn;\n \n \t\treg = QCA8K_REG_PORT0_PAD_CTRL;\n+\t\tcpu_port_index = QCA8K_CPU_PORT0;\n \t\tbreak;\n \tcase 1:\n \tcase 2:\n@@ -1260,6 +1239,7 @@ qca8k_phylink_mac_config(struct dsa_swit\n \t\t\treturn;\n \n \t\treg = QCA8K_REG_PORT6_PAD_CTRL;\n+\t\tcpu_port_index = QCA8K_CPU_PORT6;\n \t\tbreak;\n \tdefault:\n \t\tdev_err(ds->dev, \"%s: unsupported port: %i\\n\", __func__, port);\n@@ -1274,23 +1254,40 @@ qca8k_phylink_mac_config(struct dsa_swit\n \n \tswitch (state->interface) {\n \tcase PHY_INTERFACE_MODE_RGMII:\n-\t\t/* RGMII mode means no delay so don't enable the delay */\n-\t\tqca8k_write(priv, reg, QCA8K_PORT_PAD_RGMII_EN);\n-\t\tbreak;\n \tcase PHY_INTERFACE_MODE_RGMII_ID:\n \tcase PHY_INTERFACE_MODE_RGMII_TXID:\n \tcase PHY_INTERFACE_MODE_RGMII_RXID:\n-\t\t/* RGMII_ID needs internal delay. This is enabled through\n-\t\t * PORT5_PAD_CTRL for all ports, rather than individual port\n-\t\t * registers\n+\t\tval = QCA8K_PORT_PAD_RGMII_EN;\n+\n+\t\t/* Delay can be declared in 3 different way.\n+\t\t * Mode to rgmii and internal-delay standard binding defined\n+\t\t * rgmii-id or rgmii-tx/rx phy mode set.\n+\t\t * The parse logic set a delay different than 0 only when one\n+\t\t * of the 3 different way is used. In all other case delay is\n+\t\t * not enabled. With ID or TX/RXID delay is enabled and set\n+\t\t * to the default and recommended value.\n+\t\t */\n+\t\tif (priv->rgmii_tx_delay[cpu_port_index]) {\n+\t\t\tdelay = priv->rgmii_tx_delay[cpu_port_index];\n+\n+\t\t\tval |= QCA8K_PORT_PAD_RGMII_TX_DELAY(delay) |\n+\t\t\t       QCA8K_PORT_PAD_RGMII_TX_DELAY_EN;\n+\t\t}\n+\n+\t\tif (priv->rgmii_rx_delay[cpu_port_index]) {\n+\t\t\tdelay = priv->rgmii_rx_delay[cpu_port_index];\n+\n+\t\t\tval |= QCA8K_PORT_PAD_RGMII_RX_DELAY(delay) |\n+\t\t\t       QCA8K_PORT_PAD_RGMII_RX_DELAY_EN;\n+\t\t}\n+\n+\t\t/* Set RGMII delay based on the selected values */\n+\t\tqca8k_write(priv, reg, val);\n+\n+\t\t/* QCA8337 requires to set rgmii rx delay for all ports.\n+\t\t * This is enabled through PORT5_PAD_CTRL for all ports,\n+\t\t * rather than individual port registers.\n \t\t */\n-\t\tqca8k_write(priv, reg,\n-\t\t\t    QCA8K_PORT_PAD_RGMII_EN |\n-\t\t\t    QCA8K_PORT_PAD_RGMII_TX_DELAY(priv->rgmii_tx_delay) |\n-\t\t\t    QCA8K_PORT_PAD_RGMII_RX_DELAY(priv->rgmii_rx_delay) |\n-\t\t\t    QCA8K_PORT_PAD_RGMII_TX_DELAY_EN |\n-\t\t\t    QCA8K_PORT_PAD_RGMII_RX_DELAY_EN);\n-\t\t/* QCA8337 requires to set rgmii rx delay */\n \t\tif (priv->switch_id == QCA8K_ID_QCA8337)\n \t\t\tqca8k_write(priv, QCA8K_REG_PORT5_PAD_CTRL,\n \t\t\t\t    QCA8K_PORT_PAD_RGMII_RX_DELAY_EN);\n--- a/drivers/net/dsa/qca8k.h\n+++ b/drivers/net/dsa/qca8k.h\n@@ -13,6 +13,7 @@\n #include <linux/gpio.h>\n \n #define QCA8K_NUM_PORTS\t\t\t\t\t7\n+#define QCA8K_NUM_CPU_PORTS\t\t\t\t2\n #define QCA8K_MAX_MTU\t\t\t\t\t9000\n \n #define PHY_ID_QCA8327\t\t\t\t\t0x004dd034\n@@ -255,13 +256,18 @@ struct qca8k_match_data {\n \tu8 id;\n };\n \n+enum {\n+\tQCA8K_CPU_PORT0,\n+\tQCA8K_CPU_PORT6,\n+};\n+\n struct qca8k_priv {\n \tu8 switch_id;\n \tu8 switch_revision;\n-\tu8 rgmii_tx_delay;\n-\tu8 rgmii_rx_delay;\n \tbool sgmii_rx_clk_falling_edge;\n \tbool sgmii_tx_clk_falling_edge;\n+\tu8 rgmii_rx_delay[QCA8K_NUM_CPU_PORTS]; /* 0: CPU port0, 1: CPU port6 */\n+\tu8 rgmii_tx_delay[QCA8K_NUM_CPU_PORTS]; /* 0: CPU port0, 1: CPU port6 */\n \tbool legacy_phy_port_mapping;\n \tstruct regmap *regmap;\n \tstruct mii_bus *bus;\n"
  },
  {
    "path": "target/linux/generic/backport-5.15/747-v5.16-07-dt-bindings-net-dsa-qca8k-Document-qca-sgmii-enable-.patch",
    "content": "From 13ad5ccc093ff448b99ac7e138e91e78796adb48 Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Thu, 14 Oct 2021 00:39:12 +0200\nSubject: dt-bindings: net: dsa: qca8k: Document qca,sgmii-enable-pll\n\nDocument qca,sgmii-enable-pll binding used in the CPU nodes to\nenable SGMII PLL on MAC config.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n Documentation/devicetree/bindings/net/dsa/qca8k.txt | 10 ++++++++++\n 1 file changed, 10 insertions(+)\n\n--- a/Documentation/devicetree/bindings/net/dsa/qca8k.txt\n+++ b/Documentation/devicetree/bindings/net/dsa/qca8k.txt\n@@ -45,6 +45,16 @@ A CPU port node has the following option\n                                 Mostly used in qca8327 with CPU port 0 set to\n                                 sgmii.\n - qca,sgmii-txclk-falling-edge: Set the transmit clock phase to falling edge.\n+- qca,sgmii-enable-pll  : For SGMII CPU port, explicitly enable PLL, TX and RX\n+                          chain along with Signal Detection.\n+                          This should NOT be enabled for qca8327. If enabled with\n+                          qca8327 the sgmii port won't correctly init and an err\n+                          is printed.\n+                          This can be required for qca8337 switch with revision 2.\n+                          A warning is displayed when used with revision greater\n+                          2.\n+                          With CPU port set to sgmii and qca8337 it is advised\n+                          to set this unless a communication problem is observed.\n \n For QCA8K the 'fixed-link' sub-node supports only the following properties:\n \n"
  },
  {
    "path": "target/linux/generic/backport-5.15/747-v5.16-08-net-dsa-qca8k-add-explicit-SGMII-PLL-enable.patch",
    "content": "From bbc4799e8bb6c397e3b3fec13de68e179f5db9ff Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Thu, 14 Oct 2021 00:39:13 +0200\nSubject: net: dsa: qca8k: add explicit SGMII PLL enable\n\nSupport enabling PLL on the SGMII CPU port. Some device require this\nspecial configuration or no traffic is transmitted and the switch\ndoesn't work at all. A dedicated binding is added to the CPU node\nport to apply the correct reg on mac config.\nFail to correctly configure sgmii with qca8327 switch and warn if pll is\nused on qca8337 with a revision greater than 1.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nReviewed-by: Florian Fainelli <f.fainelli@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/dsa/qca8k.c | 19 +++++++++++++++++--\n drivers/net/dsa/qca8k.h |  1 +\n 2 files changed, 18 insertions(+), 2 deletions(-)\n\n--- a/drivers/net/dsa/qca8k.c\n+++ b/drivers/net/dsa/qca8k.c\n@@ -1002,6 +1002,18 @@ qca8k_parse_port_config(struct qca8k_pri\n \t\t\tif (of_property_read_bool(port_dn, \"qca,sgmii-rxclk-falling-edge\"))\n \t\t\t\tpriv->sgmii_rx_clk_falling_edge = true;\n \n+\t\t\tif (of_property_read_bool(port_dn, \"qca,sgmii-enable-pll\")) {\n+\t\t\t\tpriv->sgmii_enable_pll = true;\n+\n+\t\t\t\tif (priv->switch_id == QCA8K_ID_QCA8327) {\n+\t\t\t\t\tdev_err(priv->dev, \"SGMII PLL should NOT be enabled for qca8327. Aborting enabling\");\n+\t\t\t\t\tpriv->sgmii_enable_pll = false;\n+\t\t\t\t}\n+\n+\t\t\t\tif (priv->switch_revision < 2)\n+\t\t\t\t\tdev_warn(priv->dev, \"SGMII PLL should NOT be enabled for qca8337 with revision 2 or more.\");\n+\t\t\t}\n+\n \t\t\tbreak;\n \t\tdefault:\n \t\t\tcontinue;\n@@ -1312,8 +1324,11 @@ qca8k_phylink_mac_config(struct dsa_swit\n \t\tif (ret)\n \t\t\treturn;\n \n-\t\tval |= QCA8K_SGMII_EN_PLL | QCA8K_SGMII_EN_RX |\n-\t\t\tQCA8K_SGMII_EN_TX | QCA8K_SGMII_EN_SD;\n+\t\tval |= QCA8K_SGMII_EN_SD;\n+\n+\t\tif (priv->sgmii_enable_pll)\n+\t\t\tval |= QCA8K_SGMII_EN_PLL | QCA8K_SGMII_EN_RX |\n+\t\t\t       QCA8K_SGMII_EN_TX;\n \n \t\tif (dsa_is_cpu_port(ds, port)) {\n \t\t\t/* CPU port, we're talking to the CPU MAC, be a PHY */\n--- a/drivers/net/dsa/qca8k.h\n+++ b/drivers/net/dsa/qca8k.h\n@@ -266,6 +266,7 @@ struct qca8k_priv {\n \tu8 switch_revision;\n \tbool sgmii_rx_clk_falling_edge;\n \tbool sgmii_tx_clk_falling_edge;\n+\tbool sgmii_enable_pll;\n \tu8 rgmii_rx_delay[QCA8K_NUM_CPU_PORTS]; /* 0: CPU port0, 1: CPU port6 */\n \tu8 rgmii_tx_delay[QCA8K_NUM_CPU_PORTS]; /* 0: CPU port0, 1: CPU port6 */\n \tbool legacy_phy_port_mapping;\n"
  },
  {
    "path": "target/linux/generic/backport-5.15/747-v5.16-09-dt-bindings-net-dsa-qca8k-Document-qca-led-open-drai.patch",
    "content": "From 924087c5c3d41553700b0eb83ca2a53b91643dca Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Thu, 14 Oct 2021 00:39:14 +0200\nSubject: dt-bindings: net: dsa: qca8k: Document qca,led-open-drain binding\n\nDocument new binding qca,ignore-power-on-sel used to ignore\npower on strapping and use sw regs instead.\nDocument qca,led-open.drain to set led to open drain mode, the\nqca,ignore-power-on-sel is mandatory with this enabled or an error will\nbe reported.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n Documentation/devicetree/bindings/net/dsa/qca8k.txt | 11 +++++++++++\n 1 file changed, 11 insertions(+)\n\n--- a/Documentation/devicetree/bindings/net/dsa/qca8k.txt\n+++ b/Documentation/devicetree/bindings/net/dsa/qca8k.txt\n@@ -13,6 +13,17 @@ Required properties:\n Optional properties:\n \n - reset-gpios: GPIO to be used to reset the whole device\n+- qca,ignore-power-on-sel: Ignore power on pin strapping to configure led open\n+                           drain or eeprom presence. This is needed for broken\n+                           devices that have wrong configuration or when the oem\n+                           decided to not use pin strapping and fallback to sw\n+                           regs.\n+- qca,led-open-drain: Set leds to open-drain mode. This requires the\n+                      qca,ignore-power-on-sel to be set or the driver will fail\n+                      to probe. This is needed if the oem doesn't use pin\n+                      strapping to set this mode and prefers to set it using sw\n+                      regs. The pin strapping related to led open drain mode is\n+                      the pin B68 for QCA832x and B49 for QCA833x\n \n Subnodes:\n \n"
  },
  {
    "path": "target/linux/generic/backport-5.15/747-v5.16-10-net-dsa-qca8k-add-support-for-pws-config-reg.patch",
    "content": "From 362bb238d8bf1470424214a8a5968d9c6cce68fa Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Thu, 14 Oct 2021 00:39:15 +0200\nSubject: net: dsa: qca8k: add support for pws config reg\n\nSome qca8327 switch require to force the ignore of power on sel\nstrapping. Some switch require to set the led open drain mode in regs\ninstead of using strapping. While most of the device implements this\nusing the correct way using pin strapping, there are still some broken\ndevice that require to be set using sw regs.\nIntroduce a new binding and support these special configuration.\nAs led open drain require to ignore pin strapping to work, the probe\nfails with EINVAL error with incorrect configuration.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nReviewed-by: Florian Fainelli <f.fainelli@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/dsa/qca8k.c | 39 +++++++++++++++++++++++++++++++++++++++\n drivers/net/dsa/qca8k.h |  6 ++++++\n 2 files changed, 45 insertions(+)\n\n--- a/drivers/net/dsa/qca8k.c\n+++ b/drivers/net/dsa/qca8k.c\n@@ -932,6 +932,41 @@ static int qca8k_find_cpu_port(struct ds\n }\n \n static int\n+qca8k_setup_of_pws_reg(struct qca8k_priv *priv)\n+{\n+\tstruct device_node *node = priv->dev->of_node;\n+\tu32 val = 0;\n+\tint ret;\n+\n+\t/* QCA8327 require to set to the correct mode.\n+\t * His bigger brother QCA8328 have the 172 pin layout.\n+\t * Should be applied by default but we set this just to make sure.\n+\t */\n+\tif (priv->switch_id == QCA8K_ID_QCA8327) {\n+\t\tret = qca8k_rmw(priv, QCA8K_REG_PWS, QCA8327_PWS_PACKAGE148_EN,\n+\t\t\t\tQCA8327_PWS_PACKAGE148_EN);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\t}\n+\n+\tif (of_property_read_bool(node, \"qca,ignore-power-on-sel\"))\n+\t\tval |= QCA8K_PWS_POWER_ON_SEL;\n+\n+\tif (of_property_read_bool(node, \"qca,led-open-drain\")) {\n+\t\tif (!(val & QCA8K_PWS_POWER_ON_SEL)) {\n+\t\t\tdev_err(priv->dev, \"qca,led-open-drain require qca,ignore-power-on-sel to be set.\");\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\n+\t\tval |= QCA8K_PWS_LED_OPEN_EN_CSR;\n+\t}\n+\n+\treturn qca8k_rmw(priv, QCA8K_REG_PWS,\n+\t\t\tQCA8K_PWS_LED_OPEN_EN_CSR | QCA8K_PWS_POWER_ON_SEL,\n+\t\t\tval);\n+}\n+\n+static int\n qca8k_parse_port_config(struct qca8k_priv *priv)\n {\n \tint port, cpu_port_index = 0, ret;\n@@ -1053,6 +1088,10 @@ qca8k_setup(struct dsa_switch *ds)\n \tif (ret)\n \t\treturn ret;\n \n+\tret = qca8k_setup_of_pws_reg(priv);\n+\tif (ret)\n+\t\treturn ret;\n+\n \tret = qca8k_setup_mac_pwr_sel(priv);\n \tif (ret)\n \t\treturn ret;\n--- a/drivers/net/dsa/qca8k.h\n+++ b/drivers/net/dsa/qca8k.h\n@@ -46,6 +46,12 @@\n #define   QCA8K_MAX_DELAY\t\t\t\t3\n #define   QCA8K_PORT_PAD_SGMII_EN\t\t\tBIT(7)\n #define QCA8K_REG_PWS\t\t\t\t\t0x010\n+#define   QCA8K_PWS_POWER_ON_SEL\t\t\tBIT(31)\n+/* This reg is only valid for QCA832x and toggle the package\n+ * type from 176 pin (by default) to 148 pin used on QCA8327\n+ */\n+#define   QCA8327_PWS_PACKAGE148_EN\t\t\tBIT(30)\n+#define   QCA8K_PWS_LED_OPEN_EN_CSR\t\t\tBIT(24)\n #define   QCA8K_PWS_SERDES_AEN_DIS\t\t\tBIT(7)\n #define QCA8K_REG_MODULE_EN\t\t\t\t0x030\n #define   QCA8K_MODULE_EN_MIB\t\t\t\tBIT(0)\n"
  },
  {
    "path": "target/linux/generic/backport-5.15/747-v5.16-11-dt-bindings-net-dsa-qca8k-document-support-for-qca83.patch",
    "content": "From ed7988d77fbfb79366b68f9e7fa60a6080da23d4 Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Thu, 14 Oct 2021 00:39:16 +0200\nSubject: dt-bindings: net: dsa: qca8k: document support for qca8328\n\nQCA8328 is the bigger brother of qca8327. Document the new compatible\nbinding and add some information to understand the various switch\ncompatible.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nReviewed-by: Florian Fainelli <f.fainelli@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n Documentation/devicetree/bindings/net/dsa/qca8k.txt | 7 ++++---\n 1 file changed, 4 insertions(+), 3 deletions(-)\n\n--- a/Documentation/devicetree/bindings/net/dsa/qca8k.txt\n+++ b/Documentation/devicetree/bindings/net/dsa/qca8k.txt\n@@ -3,9 +3,10 @@\n Required properties:\n \n - compatible: should be one of:\n-    \"qca,qca8327\"\n-    \"qca,qca8334\"\n-    \"qca,qca8337\"\n+    \"qca,qca8328\": referenced as AR8328(N)-AK1(A/B) QFN 176 pin package\n+    \"qca,qca8327\": referenced as AR8327(N)-AL1A DR-QFN 148 pin package\n+    \"qca,qca8334\": referenced as QCA8334-AL3C QFN 88 pin package\n+    \"qca,qca8337\": referenced as QCA8337N-AL3(B/C) DR-QFN 148 pin package\n \n - #size-cells: must be 0\n - #address-cells: must be 1\n"
  },
  {
    "path": "target/linux/generic/backport-5.15/747-v5.16-12-net-dsa-qca8k-add-support-for-QCA8328.patch",
    "content": "From f477d1c8bdbef4f400718238e350f16f521d2a3e Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Thu, 14 Oct 2021 00:39:17 +0200\nSubject: net: dsa: qca8k: add support for QCA8328\n\nQCA8328 switch is the bigger brother of the qca8327. Same regs different\nchip. Change the function to set the correct pin layout and introduce a\nnew match_data to differentiate the 2 switch as they have the same ID\nand their internal PHY have the same ID.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nReviewed-by: Florian Fainelli <f.fainelli@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/dsa/qca8k.c | 19 ++++++++++++++++---\n drivers/net/dsa/qca8k.h |  1 +\n 2 files changed, 17 insertions(+), 3 deletions(-)\n\n--- a/drivers/net/dsa/qca8k.c\n+++ b/drivers/net/dsa/qca8k.c\n@@ -935,6 +935,7 @@ static int\n qca8k_setup_of_pws_reg(struct qca8k_priv *priv)\n {\n \tstruct device_node *node = priv->dev->of_node;\n+\tconst struct qca8k_match_data *data;\n \tu32 val = 0;\n \tint ret;\n \n@@ -943,8 +944,14 @@ qca8k_setup_of_pws_reg(struct qca8k_priv\n \t * Should be applied by default but we set this just to make sure.\n \t */\n \tif (priv->switch_id == QCA8K_ID_QCA8327) {\n+\t\tdata = of_device_get_match_data(priv->dev);\n+\n+\t\t/* Set the correct package of 148 pin for QCA8327 */\n+\t\tif (data->reduced_package)\n+\t\t\tval |= QCA8327_PWS_PACKAGE148_EN;\n+\n \t\tret = qca8k_rmw(priv, QCA8K_REG_PWS, QCA8327_PWS_PACKAGE148_EN,\n-\t\t\t\tQCA8327_PWS_PACKAGE148_EN);\n+\t\t\t\tval);\n \t\tif (ret)\n \t\t\treturn ret;\n \t}\n@@ -2105,7 +2112,12 @@ static int qca8k_resume(struct device *d\n static SIMPLE_DEV_PM_OPS(qca8k_pm_ops,\n \t\t\t qca8k_suspend, qca8k_resume);\n \n-static const struct qca8k_match_data qca832x = {\n+static const struct qca8k_match_data qca8327 = {\n+\t.id = QCA8K_ID_QCA8327,\n+\t.reduced_package = true,\n+};\n+\n+static const struct qca8k_match_data qca8328 = {\n \t.id = QCA8K_ID_QCA8327,\n };\n \n@@ -2114,7 +2126,8 @@ static const struct qca8k_match_data qca\n };\n \n static const struct of_device_id qca8k_of_match[] = {\n-\t{ .compatible = \"qca,qca8327\", .data = &qca832x },\n+\t{ .compatible = \"qca,qca8327\", .data = &qca8327 },\n+\t{ .compatible = \"qca,qca8328\", .data = &qca8328 },\n \t{ .compatible = \"qca,qca8334\", .data = &qca833x },\n \t{ .compatible = \"qca,qca8337\", .data = &qca833x },\n \t{ /* sentinel */ },\n--- a/drivers/net/dsa/qca8k.h\n+++ b/drivers/net/dsa/qca8k.h\n@@ -260,6 +260,7 @@ struct ar8xxx_port_status {\n \n struct qca8k_match_data {\n \tu8 id;\n+\tbool reduced_package;\n };\n \n enum {\n"
  },
  {
    "path": "target/linux/generic/backport-5.15/747-v5.16-13-net-dsa-qca8k-set-internal-delay-also-for-sgmii.patch",
    "content": "From cef08115846e581f80ff99abf7bf218da1840616 Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Thu, 14 Oct 2021 00:39:18 +0200\nSubject: net: dsa: qca8k: set internal delay also for sgmii\n\nQCA original code report port instability and sa that SGMII also require\nto set internal delay. Generalize the rgmii delay function and apply the\nadvised value if they are not defined in DT.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/dsa/qca8k.c | 88 +++++++++++++++++++++++++++++++++----------------\n drivers/net/dsa/qca8k.h |  2 ++\n 2 files changed, 62 insertions(+), 28 deletions(-)\n\n--- a/drivers/net/dsa/qca8k.c\n+++ b/drivers/net/dsa/qca8k.c\n@@ -1004,6 +1004,7 @@ qca8k_parse_port_config(struct qca8k_pri\n \t\tcase PHY_INTERFACE_MODE_RGMII_ID:\n \t\tcase PHY_INTERFACE_MODE_RGMII_TXID:\n \t\tcase PHY_INTERFACE_MODE_RGMII_RXID:\n+\t\tcase PHY_INTERFACE_MODE_SGMII:\n \t\t\tdelay = 0;\n \n \t\t\tif (!of_property_read_u32(port_dn, \"tx-internal-delay-ps\", &delay))\n@@ -1036,8 +1037,13 @@ qca8k_parse_port_config(struct qca8k_pri\n \n \t\t\tpriv->rgmii_rx_delay[cpu_port_index] = delay;\n \n-\t\t\tbreak;\n-\t\tcase PHY_INTERFACE_MODE_SGMII:\n+\t\t\t/* Skip sgmii parsing for rgmii* mode */\n+\t\t\tif (mode == PHY_INTERFACE_MODE_RGMII ||\n+\t\t\t    mode == PHY_INTERFACE_MODE_RGMII_ID ||\n+\t\t\t    mode == PHY_INTERFACE_MODE_RGMII_TXID ||\n+\t\t\t    mode == PHY_INTERFACE_MODE_RGMII_RXID)\n+\t\t\t\tbreak;\n+\n \t\t\tif (of_property_read_bool(port_dn, \"qca,sgmii-txclk-falling-edge\"))\n \t\t\t\tpriv->sgmii_tx_clk_falling_edge = true;\n \n@@ -1261,12 +1267,53 @@ qca8k_setup(struct dsa_switch *ds)\n }\n \n static void\n+qca8k_mac_config_setup_internal_delay(struct qca8k_priv *priv, int cpu_port_index,\n+\t\t\t\t      u32 reg)\n+{\n+\tu32 delay, val = 0;\n+\tint ret;\n+\n+\t/* Delay can be declared in 3 different way.\n+\t * Mode to rgmii and internal-delay standard binding defined\n+\t * rgmii-id or rgmii-tx/rx phy mode set.\n+\t * The parse logic set a delay different than 0 only when one\n+\t * of the 3 different way is used. In all other case delay is\n+\t * not enabled. With ID or TX/RXID delay is enabled and set\n+\t * to the default and recommended value.\n+\t */\n+\tif (priv->rgmii_tx_delay[cpu_port_index]) {\n+\t\tdelay = priv->rgmii_tx_delay[cpu_port_index];\n+\n+\t\tval |= QCA8K_PORT_PAD_RGMII_TX_DELAY(delay) |\n+\t\t\tQCA8K_PORT_PAD_RGMII_TX_DELAY_EN;\n+\t}\n+\n+\tif (priv->rgmii_rx_delay[cpu_port_index]) {\n+\t\tdelay = priv->rgmii_rx_delay[cpu_port_index];\n+\n+\t\tval |= QCA8K_PORT_PAD_RGMII_RX_DELAY(delay) |\n+\t\t\tQCA8K_PORT_PAD_RGMII_RX_DELAY_EN;\n+\t}\n+\n+\t/* Set RGMII delay based on the selected values */\n+\tret = qca8k_rmw(priv, reg,\n+\t\t\tQCA8K_PORT_PAD_RGMII_TX_DELAY_MASK |\n+\t\t\tQCA8K_PORT_PAD_RGMII_RX_DELAY_MASK |\n+\t\t\tQCA8K_PORT_PAD_RGMII_TX_DELAY_EN |\n+\t\t\tQCA8K_PORT_PAD_RGMII_RX_DELAY_EN,\n+\t\t\tval);\n+\tif (ret)\n+\t\tdev_err(priv->dev, \"Failed to set internal delay for CPU port%d\",\n+\t\t\tcpu_port_index == QCA8K_CPU_PORT0 ? 0 : 6);\n+}\n+\n+static void\n qca8k_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode,\n \t\t\t const struct phylink_link_state *state)\n {\n \tstruct qca8k_priv *priv = ds->priv;\n \tint cpu_port_index, ret;\n-\tu32 reg, val, delay;\n+\tu32 reg, val;\n \n \tswitch (port) {\n \tcase 0: /* 1st CPU port */\n@@ -1315,32 +1362,10 @@ qca8k_phylink_mac_config(struct dsa_swit\n \tcase PHY_INTERFACE_MODE_RGMII_ID:\n \tcase PHY_INTERFACE_MODE_RGMII_TXID:\n \tcase PHY_INTERFACE_MODE_RGMII_RXID:\n-\t\tval = QCA8K_PORT_PAD_RGMII_EN;\n-\n-\t\t/* Delay can be declared in 3 different way.\n-\t\t * Mode to rgmii and internal-delay standard binding defined\n-\t\t * rgmii-id or rgmii-tx/rx phy mode set.\n-\t\t * The parse logic set a delay different than 0 only when one\n-\t\t * of the 3 different way is used. In all other case delay is\n-\t\t * not enabled. With ID or TX/RXID delay is enabled and set\n-\t\t * to the default and recommended value.\n-\t\t */\n-\t\tif (priv->rgmii_tx_delay[cpu_port_index]) {\n-\t\t\tdelay = priv->rgmii_tx_delay[cpu_port_index];\n-\n-\t\t\tval |= QCA8K_PORT_PAD_RGMII_TX_DELAY(delay) |\n-\t\t\t       QCA8K_PORT_PAD_RGMII_TX_DELAY_EN;\n-\t\t}\n-\n-\t\tif (priv->rgmii_rx_delay[cpu_port_index]) {\n-\t\t\tdelay = priv->rgmii_rx_delay[cpu_port_index];\n-\n-\t\t\tval |= QCA8K_PORT_PAD_RGMII_RX_DELAY(delay) |\n-\t\t\t       QCA8K_PORT_PAD_RGMII_RX_DELAY_EN;\n-\t\t}\n+\t\tqca8k_write(priv, reg, QCA8K_PORT_PAD_RGMII_EN);\n \n-\t\t/* Set RGMII delay based on the selected values */\n-\t\tqca8k_write(priv, reg, val);\n+\t\t/* Configure rgmii delay */\n+\t\tqca8k_mac_config_setup_internal_delay(priv, cpu_port_index, reg);\n \n \t\t/* QCA8337 requires to set rgmii rx delay for all ports.\n \t\t * This is enabled through PORT5_PAD_CTRL for all ports,\n@@ -1411,6 +1436,13 @@ qca8k_phylink_mac_config(struct dsa_swit\n \t\t\t\t\tQCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE |\n \t\t\t\t\tQCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE,\n \t\t\t\t\tval);\n+\n+\t\t/* From original code is reported port instability as SGMII also\n+\t\t * require delay set. Apply advised values here or take them from DT.\n+\t\t */\n+\t\tif (state->interface == PHY_INTERFACE_MODE_SGMII)\n+\t\t\tqca8k_mac_config_setup_internal_delay(priv, cpu_port_index, reg);\n+\n \t\tbreak;\n \tdefault:\n \t\tdev_err(ds->dev, \"xMII mode %s not supported for port %d\\n\",\n--- a/drivers/net/dsa/qca8k.h\n+++ b/drivers/net/dsa/qca8k.h\n@@ -39,7 +39,9 @@\n #define QCA8K_REG_PORT5_PAD_CTRL\t\t\t0x008\n #define QCA8K_REG_PORT6_PAD_CTRL\t\t\t0x00c\n #define   QCA8K_PORT_PAD_RGMII_EN\t\t\tBIT(26)\n+#define   QCA8K_PORT_PAD_RGMII_TX_DELAY_MASK\t\tGENMASK(23, 22)\n #define   QCA8K_PORT_PAD_RGMII_TX_DELAY(x)\t\t((x) << 22)\n+#define   QCA8K_PORT_PAD_RGMII_RX_DELAY_MASK\t\tGENMASK(21, 20)\n #define   QCA8K_PORT_PAD_RGMII_RX_DELAY(x)\t\t((x) << 20)\n #define\t  QCA8K_PORT_PAD_RGMII_TX_DELAY_EN\t\tBIT(25)\n #define   QCA8K_PORT_PAD_RGMII_RX_DELAY_EN\t\tBIT(24)\n"
  },
  {
    "path": "target/linux/generic/backport-5.15/747-v5.16-14-net-dsa-qca8k-move-port-config-to-dedicated-struct.patch",
    "content": "From fd0bb28c547f7c8affb1691128cece38f5b626a1 Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Thu, 14 Oct 2021 00:39:19 +0200\nSubject: net: dsa: qca8k: move port config to dedicated struct\n\nMove ports related config to dedicated struct to keep things organized.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nReviewed-by: Florian Fainelli <f.fainelli@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/dsa/qca8k.c | 26 +++++++++++++-------------\n drivers/net/dsa/qca8k.h | 10 +++++++---\n 2 files changed, 20 insertions(+), 16 deletions(-)\n\n--- a/drivers/net/dsa/qca8k.c\n+++ b/drivers/net/dsa/qca8k.c\n@@ -1019,7 +1019,7 @@ qca8k_parse_port_config(struct qca8k_pri\n \t\t\t\tdelay = 3;\n \t\t\t}\n \n-\t\t\tpriv->rgmii_tx_delay[cpu_port_index] = delay;\n+\t\t\tpriv->ports_config.rgmii_tx_delay[cpu_port_index] = delay;\n \n \t\t\tdelay = 0;\n \n@@ -1035,7 +1035,7 @@ qca8k_parse_port_config(struct qca8k_pri\n \t\t\t\tdelay = 3;\n \t\t\t}\n \n-\t\t\tpriv->rgmii_rx_delay[cpu_port_index] = delay;\n+\t\t\tpriv->ports_config.rgmii_rx_delay[cpu_port_index] = delay;\n \n \t\t\t/* Skip sgmii parsing for rgmii* mode */\n \t\t\tif (mode == PHY_INTERFACE_MODE_RGMII ||\n@@ -1045,17 +1045,17 @@ qca8k_parse_port_config(struct qca8k_pri\n \t\t\t\tbreak;\n \n \t\t\tif (of_property_read_bool(port_dn, \"qca,sgmii-txclk-falling-edge\"))\n-\t\t\t\tpriv->sgmii_tx_clk_falling_edge = true;\n+\t\t\t\tpriv->ports_config.sgmii_tx_clk_falling_edge = true;\n \n \t\t\tif (of_property_read_bool(port_dn, \"qca,sgmii-rxclk-falling-edge\"))\n-\t\t\t\tpriv->sgmii_rx_clk_falling_edge = true;\n+\t\t\t\tpriv->ports_config.sgmii_rx_clk_falling_edge = true;\n \n \t\t\tif (of_property_read_bool(port_dn, \"qca,sgmii-enable-pll\")) {\n-\t\t\t\tpriv->sgmii_enable_pll = true;\n+\t\t\t\tpriv->ports_config.sgmii_enable_pll = true;\n \n \t\t\t\tif (priv->switch_id == QCA8K_ID_QCA8327) {\n \t\t\t\t\tdev_err(priv->dev, \"SGMII PLL should NOT be enabled for qca8327. Aborting enabling\");\n-\t\t\t\t\tpriv->sgmii_enable_pll = false;\n+\t\t\t\t\tpriv->ports_config.sgmii_enable_pll = false;\n \t\t\t\t}\n \n \t\t\t\tif (priv->switch_revision < 2)\n@@ -1281,15 +1281,15 @@ qca8k_mac_config_setup_internal_delay(st\n \t * not enabled. With ID or TX/RXID delay is enabled and set\n \t * to the default and recommended value.\n \t */\n-\tif (priv->rgmii_tx_delay[cpu_port_index]) {\n-\t\tdelay = priv->rgmii_tx_delay[cpu_port_index];\n+\tif (priv->ports_config.rgmii_tx_delay[cpu_port_index]) {\n+\t\tdelay = priv->ports_config.rgmii_tx_delay[cpu_port_index];\n \n \t\tval |= QCA8K_PORT_PAD_RGMII_TX_DELAY(delay) |\n \t\t\tQCA8K_PORT_PAD_RGMII_TX_DELAY_EN;\n \t}\n \n-\tif (priv->rgmii_rx_delay[cpu_port_index]) {\n-\t\tdelay = priv->rgmii_rx_delay[cpu_port_index];\n+\tif (priv->ports_config.rgmii_rx_delay[cpu_port_index]) {\n+\t\tdelay = priv->ports_config.rgmii_rx_delay[cpu_port_index];\n \n \t\tval |= QCA8K_PORT_PAD_RGMII_RX_DELAY(delay) |\n \t\t\tQCA8K_PORT_PAD_RGMII_RX_DELAY_EN;\n@@ -1397,7 +1397,7 @@ qca8k_phylink_mac_config(struct dsa_swit\n \n \t\tval |= QCA8K_SGMII_EN_SD;\n \n-\t\tif (priv->sgmii_enable_pll)\n+\t\tif (priv->ports_config.sgmii_enable_pll)\n \t\t\tval |= QCA8K_SGMII_EN_PLL | QCA8K_SGMII_EN_RX |\n \t\t\t       QCA8K_SGMII_EN_TX;\n \n@@ -1425,10 +1425,10 @@ qca8k_phylink_mac_config(struct dsa_swit\n \t\tval = 0;\n \n \t\t/* SGMII Clock phase configuration */\n-\t\tif (priv->sgmii_rx_clk_falling_edge)\n+\t\tif (priv->ports_config.sgmii_rx_clk_falling_edge)\n \t\t\tval |= QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE;\n \n-\t\tif (priv->sgmii_tx_clk_falling_edge)\n+\t\tif (priv->ports_config.sgmii_tx_clk_falling_edge)\n \t\t\tval |= QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE;\n \n \t\tif (val)\n--- a/drivers/net/dsa/qca8k.h\n+++ b/drivers/net/dsa/qca8k.h\n@@ -270,15 +270,19 @@ enum {\n \tQCA8K_CPU_PORT6,\n };\n \n-struct qca8k_priv {\n-\tu8 switch_id;\n-\tu8 switch_revision;\n+struct qca8k_ports_config {\n \tbool sgmii_rx_clk_falling_edge;\n \tbool sgmii_tx_clk_falling_edge;\n \tbool sgmii_enable_pll;\n \tu8 rgmii_rx_delay[QCA8K_NUM_CPU_PORTS]; /* 0: CPU port0, 1: CPU port6 */\n \tu8 rgmii_tx_delay[QCA8K_NUM_CPU_PORTS]; /* 0: CPU port0, 1: CPU port6 */\n+};\n+\n+struct qca8k_priv {\n+\tu8 switch_id;\n+\tu8 switch_revision;\n \tbool legacy_phy_port_mapping;\n+\tstruct qca8k_ports_config ports_config;\n \tstruct regmap *regmap;\n \tstruct mii_bus *bus;\n \tstruct ar8xxx_port_status port_sts[QCA8K_NUM_PORTS];\n"
  },
  {
    "path": "target/linux/generic/backport-5.15/747-v5.16-15-dt-bindings-net-ipq8064-mdio-fix-warning-with-new-qc.patch",
    "content": "From e52073a8e3086046a098b8a7cbeb282ff0cdb424 Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Thu, 14 Oct 2021 00:39:20 +0200\nSubject: dt-bindings: net: ipq8064-mdio: fix warning with new qca8k switch\n\nFix warning now that we have qca8k switch Documentation using yaml.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n Documentation/devicetree/bindings/net/qcom,ipq8064-mdio.yaml | 5 ++++-\n 1 file changed, 4 insertions(+), 1 deletion(-)\n\n--- a/Documentation/devicetree/bindings/net/qcom,ipq8064-mdio.yaml\n+++ b/Documentation/devicetree/bindings/net/qcom,ipq8064-mdio.yaml\n@@ -51,6 +51,9 @@ examples:\n         switch@10 {\n             compatible = \"qca,qca8337\";\n             reg = <0x10>;\n-            /* ... */\n+\n+            ports {\n+              /* ... */\n+            };\n         };\n     };\n"
  },
  {
    "path": "target/linux/generic/backport-5.15/747-v5.16-16-dt-bindings-net-dsa-qca8k-convert-to-YAML-schema.patch",
    "content": "From d291fbb8245d5ba04979fed85575860a5cea7196 Mon Sep 17 00:00:00 2001\nFrom: Matthew Hagan <mnhagan88@gmail.com>\nDate: Thu, 14 Oct 2021 00:39:21 +0200\nSubject: dt-bindings: net: dsa: qca8k: convert to YAML schema\n\nConvert the qca8k bindings to YAML format.\n\nSigned-off-by: Matthew Hagan <mnhagan88@gmail.com>\nCo-developed-by: Ansuel Smith <ansuelsmth@gmail.com>\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n .../devicetree/bindings/net/dsa/qca8k.txt          | 245 --------------\n .../devicetree/bindings/net/dsa/qca8k.yaml         | 362 +++++++++++++++++++++\n 2 files changed, 362 insertions(+), 245 deletions(-)\n delete mode 100644 Documentation/devicetree/bindings/net/dsa/qca8k.txt\n create mode 100644 Documentation/devicetree/bindings/net/dsa/qca8k.yaml\n\n--- a/Documentation/devicetree/bindings/net/dsa/qca8k.txt\n+++ /dev/null\n@@ -1,245 +0,0 @@\n-* Qualcomm Atheros QCA8xxx switch family\n-\n-Required properties:\n-\n-- compatible: should be one of:\n-    \"qca,qca8328\": referenced as AR8328(N)-AK1(A/B) QFN 176 pin package\n-    \"qca,qca8327\": referenced as AR8327(N)-AL1A DR-QFN 148 pin package\n-    \"qca,qca8334\": referenced as QCA8334-AL3C QFN 88 pin package\n-    \"qca,qca8337\": referenced as QCA8337N-AL3(B/C) DR-QFN 148 pin package\n-\n-- #size-cells: must be 0\n-- #address-cells: must be 1\n-\n-Optional properties:\n-\n-- reset-gpios: GPIO to be used to reset the whole device\n-- qca,ignore-power-on-sel: Ignore power on pin strapping to configure led open\n-                           drain or eeprom presence. This is needed for broken\n-                           devices that have wrong configuration or when the oem\n-                           decided to not use pin strapping and fallback to sw\n-                           regs.\n-- qca,led-open-drain: Set leds to open-drain mode. This requires the\n-                      qca,ignore-power-on-sel to be set or the driver will fail\n-                      to probe. This is needed if the oem doesn't use pin\n-                      strapping to set this mode and prefers to set it using sw\n-                      regs. The pin strapping related to led open drain mode is\n-                      the pin B68 for QCA832x and B49 for QCA833x\n-\n-Subnodes:\n-\n-The integrated switch subnode should be specified according to the binding\n-described in dsa/dsa.txt. If the QCA8K switch is connect to a SoC's external\n-mdio-bus each subnode describing a port needs to have a valid phandle\n-referencing the internal PHY it is connected to. This is because there's no\n-N:N mapping of port and PHY id.\n-To declare the internal mdio-bus configuration, declare a mdio node in the\n-switch node and declare the phandle for the port referencing the internal\n-PHY is connected to. In this config a internal mdio-bus is registered and\n-the mdio MASTER is used as communication.\n-\n-Don't use mixed external and internal mdio-bus configurations, as this is\n-not supported by the hardware.\n-\n-This switch support 2 CPU port. Normally and advised configuration is with\n-CPU port set to port 0. It is also possible to set the CPU port to port 6\n-if the device requires it. The driver will configure the switch to the defined\n-port. With both CPU port declared the first CPU port is selected as primary\n-and the secondary CPU ignored.\n-\n-A CPU port node has the following optional node:\n-\n-- fixed-link            : Fixed-link subnode describing a link to a non-MDIO\n-                          managed entity. See\n-                          Documentation/devicetree/bindings/net/fixed-link.txt\n-                          for details.\n-- qca,sgmii-rxclk-falling-edge: Set the receive clock phase to falling edge.\n-                                Mostly used in qca8327 with CPU port 0 set to\n-                                sgmii.\n-- qca,sgmii-txclk-falling-edge: Set the transmit clock phase to falling edge.\n-- qca,sgmii-enable-pll  : For SGMII CPU port, explicitly enable PLL, TX and RX\n-                          chain along with Signal Detection.\n-                          This should NOT be enabled for qca8327. If enabled with\n-                          qca8327 the sgmii port won't correctly init and an err\n-                          is printed.\n-                          This can be required for qca8337 switch with revision 2.\n-                          A warning is displayed when used with revision greater\n-                          2.\n-                          With CPU port set to sgmii and qca8337 it is advised\n-                          to set this unless a communication problem is observed.\n-\n-For QCA8K the 'fixed-link' sub-node supports only the following properties:\n-\n-- 'speed' (integer, mandatory), to indicate the link speed. Accepted\n-  values are 10, 100 and 1000\n-- 'full-duplex' (boolean, optional), to indicate that full duplex is\n-  used. When absent, half duplex is assumed.\n-\n-Examples:\n-\n-for the external mdio-bus configuration:\n-\n-\t&mdio0 {\n-\t\tphy_port1: phy@0 {\n-\t\t\treg = <0>;\n-\t\t};\n-\n-\t\tphy_port2: phy@1 {\n-\t\t\treg = <1>;\n-\t\t};\n-\n-\t\tphy_port3: phy@2 {\n-\t\t\treg = <2>;\n-\t\t};\n-\n-\t\tphy_port4: phy@3 {\n-\t\t\treg = <3>;\n-\t\t};\n-\n-\t\tphy_port5: phy@4 {\n-\t\t\treg = <4>;\n-\t\t};\n-\n-\t\tswitch@10 {\n-\t\t\tcompatible = \"qca,qca8337\";\n-\t\t\t#address-cells = <1>;\n-\t\t\t#size-cells = <0>;\n-\n-\t\t\treset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>;\n-\t\t\treg = <0x10>;\n-\n-\t\t\tports {\n-\t\t\t\t#address-cells = <1>;\n-\t\t\t\t#size-cells = <0>;\n-\t\t\t\tport@0 {\n-\t\t\t\t\treg = <0>;\n-\t\t\t\t\tlabel = \"cpu\";\n-\t\t\t\t\tethernet = <&gmac1>;\n-\t\t\t\t\tphy-mode = \"rgmii\";\n-\t\t\t\t\tfixed-link {\n-\t\t\t\t\t\tspeed = 1000;\n-\t\t\t\t\t\tfull-duplex;\n-\t\t\t\t\t};\n-\t\t\t\t};\n-\n-\t\t\t\tport@1 {\n-\t\t\t\t\treg = <1>;\n-\t\t\t\t\tlabel = \"lan1\";\n-\t\t\t\t\tphy-handle = <&phy_port1>;\n-\t\t\t\t};\n-\n-\t\t\t\tport@2 {\n-\t\t\t\t\treg = <2>;\n-\t\t\t\t\tlabel = \"lan2\";\n-\t\t\t\t\tphy-handle = <&phy_port2>;\n-\t\t\t\t};\n-\n-\t\t\t\tport@3 {\n-\t\t\t\t\treg = <3>;\n-\t\t\t\t\tlabel = \"lan3\";\n-\t\t\t\t\tphy-handle = <&phy_port3>;\n-\t\t\t\t};\n-\n-\t\t\t\tport@4 {\n-\t\t\t\t\treg = <4>;\n-\t\t\t\t\tlabel = \"lan4\";\n-\t\t\t\t\tphy-handle = <&phy_port4>;\n-\t\t\t\t};\n-\n-\t\t\t\tport@5 {\n-\t\t\t\t\treg = <5>;\n-\t\t\t\t\tlabel = \"wan\";\n-\t\t\t\t\tphy-handle = <&phy_port5>;\n-\t\t\t\t};\n-\t\t\t};\n-\t\t};\n-\t};\n-\n-for the internal master mdio-bus configuration:\n-\n-\t&mdio0 {\n-\t\tswitch@10 {\n-\t\t\tcompatible = \"qca,qca8337\";\n-\t\t\t#address-cells = <1>;\n-\t\t\t#size-cells = <0>;\n-\n-\t\t\treset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>;\n-\t\t\treg = <0x10>;\n-\n-\t\t\tports {\n-\t\t\t\t#address-cells = <1>;\n-\t\t\t\t#size-cells = <0>;\n-\n-\t\t\t\tport@0 {\n-\t\t\t\t\treg = <0>;\n-\t\t\t\t\tlabel = \"cpu\";\n-\t\t\t\t\tethernet = <&gmac1>;\n-\t\t\t\t\tphy-mode = \"rgmii\";\n-\t\t\t\t\tfixed-link {\n-\t\t\t\t\t\tspeed = 1000;\n-\t\t\t\t\t\tfull-duplex;\n-\t\t\t\t\t};\n-\t\t\t\t};\n-\n-\t\t\t\tport@1 {\n-\t\t\t\t\treg = <1>;\n-\t\t\t\t\tlabel = \"lan1\";\n-\t\t\t\t\tphy-mode = \"internal\";\n-\t\t\t\t\tphy-handle = <&phy_port1>;\n-\t\t\t\t};\n-\n-\t\t\t\tport@2 {\n-\t\t\t\t\treg = <2>;\n-\t\t\t\t\tlabel = \"lan2\";\n-\t\t\t\t\tphy-mode = \"internal\";\n-\t\t\t\t\tphy-handle = <&phy_port2>;\n-\t\t\t\t};\n-\n-\t\t\t\tport@3 {\n-\t\t\t\t\treg = <3>;\n-\t\t\t\t\tlabel = \"lan3\";\n-\t\t\t\t\tphy-mode = \"internal\";\n-\t\t\t\t\tphy-handle = <&phy_port3>;\n-\t\t\t\t};\n-\n-\t\t\t\tport@4 {\n-\t\t\t\t\treg = <4>;\n-\t\t\t\t\tlabel = \"lan4\";\n-\t\t\t\t\tphy-mode = \"internal\";\n-\t\t\t\t\tphy-handle = <&phy_port4>;\n-\t\t\t\t};\n-\n-\t\t\t\tport@5 {\n-\t\t\t\t\treg = <5>;\n-\t\t\t\t\tlabel = \"wan\";\n-\t\t\t\t\tphy-mode = \"internal\";\n-\t\t\t\t\tphy-handle = <&phy_port5>;\n-\t\t\t\t};\n-\t\t\t};\n-\n-\t\t\tmdio {\n-\t\t\t\t#address-cells = <1>;\n-\t\t\t\t#size-cells = <0>;\n-\n-\t\t\t\tphy_port1: phy@0 {\n-\t\t\t\t\treg = <0>;\n-\t\t\t\t};\n-\n-\t\t\t\tphy_port2: phy@1 {\n-\t\t\t\t\treg = <1>;\n-\t\t\t\t};\n-\n-\t\t\t\tphy_port3: phy@2 {\n-\t\t\t\t\treg = <2>;\n-\t\t\t\t};\n-\n-\t\t\t\tphy_port4: phy@3 {\n-\t\t\t\t\treg = <3>;\n-\t\t\t\t};\n-\n-\t\t\t\tphy_port5: phy@4 {\n-\t\t\t\t\treg = <4>;\n-\t\t\t\t};\n-\t\t\t};\n-\t\t};\n-\t};\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/net/dsa/qca8k.yaml\n@@ -0,0 +1,362 @@\n+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)\n+%YAML 1.2\n+---\n+$id: http://devicetree.org/schemas/net/dsa/qca8k.yaml#\n+$schema: http://devicetree.org/meta-schemas/core.yaml#\n+\n+title: Qualcomm Atheros QCA83xx switch family\n+\n+maintainers:\n+  - John Crispin <john@phrozen.org>\n+\n+description:\n+  If the QCA8K switch is connect to an SoC's external mdio-bus, each subnode\n+  describing a port needs to have a valid phandle referencing the internal PHY\n+  it is connected to. This is because there is no N:N mapping of port and PHY\n+  ID. To declare the internal mdio-bus configuration, declare an MDIO node in\n+  the switch node and declare the phandle for the port, referencing the internal\n+  PHY it is connected to. In this config, an internal mdio-bus is registered and\n+  the MDIO master is used for communication. Mixed external and internal\n+  mdio-bus configurations are not supported by the hardware.\n+\n+properties:\n+  compatible:\n+    oneOf:\n+      - enum:\n+          - qca,qca8327\n+          - qca,qca8328\n+          - qca,qca8334\n+          - qca,qca8337\n+    description: |\n+      qca,qca8328: referenced as AR8328(N)-AK1(A/B) QFN 176 pin package\n+      qca,qca8327: referenced as AR8327(N)-AL1A DR-QFN 148 pin package\n+      qca,qca8334: referenced as QCA8334-AL3C QFN 88 pin package\n+      qca,qca8337: referenced as QCA8337N-AL3(B/C) DR-QFN 148 pin package\n+\n+  reg:\n+    maxItems: 1\n+\n+  reset-gpios:\n+    description:\n+      GPIO to be used to reset the whole device\n+    maxItems: 1\n+\n+  qca,ignore-power-on-sel:\n+    $ref: /schemas/types.yaml#/definitions/flag\n+    description:\n+      Ignore power-on pin strapping to configure LED open-drain or EEPROM\n+      presence. This is needed for devices with incorrect configuration or when\n+      the OEM has decided not to use pin strapping and falls back to SW regs.\n+\n+  qca,led-open-drain:\n+    $ref: /schemas/types.yaml#/definitions/flag\n+    description:\n+      Set LEDs to open-drain mode. This requires the qca,ignore-power-on-sel to\n+      be set, otherwise the driver will fail at probe. This is required if the\n+      OEM does not use pin strapping to set this mode and prefers to set it\n+      using SW regs. The pin strappings related to LED open-drain mode are\n+      B68 on the QCA832x and B49 on the QCA833x.\n+\n+  mdio:\n+    type: object\n+    description: Qca8k switch have an internal mdio to access switch port.\n+                 If this is not present, the legacy mapping is used and the\n+                 internal mdio access is used.\n+                 With the legacy mapping the reg corresponding to the internal\n+                 mdio is the switch reg with an offset of -1.\n+\n+    properties:\n+      '#address-cells':\n+        const: 1\n+      '#size-cells':\n+        const: 0\n+\n+    patternProperties:\n+      \"^(ethernet-)?phy@[0-4]$\":\n+        type: object\n+\n+        allOf:\n+          - $ref: \"http://devicetree.org/schemas/net/mdio.yaml#\"\n+\n+        properties:\n+          reg:\n+            maxItems: 1\n+\n+        required:\n+          - reg\n+\n+patternProperties:\n+  \"^(ethernet-)?ports$\":\n+    type: object\n+    properties:\n+      '#address-cells':\n+        const: 1\n+      '#size-cells':\n+        const: 0\n+\n+    patternProperties:\n+      \"^(ethernet-)?port@[0-6]$\":\n+        type: object\n+        description: Ethernet switch ports\n+\n+        properties:\n+          reg:\n+            description: Port number\n+\n+          label:\n+            description:\n+              Describes the label associated with this port, which will become\n+              the netdev name\n+            $ref: /schemas/types.yaml#/definitions/string\n+\n+          link:\n+            description:\n+              Should be a list of phandles to other switch's DSA port. This\n+              port is used as the outgoing port towards the phandle ports. The\n+              full routing information must be given, not just the one hop\n+              routes to neighbouring switches\n+            $ref: /schemas/types.yaml#/definitions/phandle-array\n+\n+          ethernet:\n+            description:\n+              Should be a phandle to a valid Ethernet device node.  This host\n+              device is what the switch port is connected to\n+            $ref: /schemas/types.yaml#/definitions/phandle\n+\n+          phy-handle: true\n+\n+          phy-mode: true\n+\n+          fixed-link: true\n+\n+          mac-address: true\n+\n+          sfp: true\n+\n+          qca,sgmii-rxclk-falling-edge:\n+            $ref: /schemas/types.yaml#/definitions/flag\n+            description:\n+              Set the receive clock phase to falling edge. Mostly commonly used on\n+              the QCA8327 with CPU port 0 set to SGMII.\n+\n+          qca,sgmii-txclk-falling-edge:\n+            $ref: /schemas/types.yaml#/definitions/flag\n+            description:\n+              Set the transmit clock phase to falling edge.\n+\n+          qca,sgmii-enable-pll:\n+            $ref: /schemas/types.yaml#/definitions/flag\n+            description:\n+              For SGMII CPU port, explicitly enable PLL, TX and RX chain along with\n+              Signal Detection. On the QCA8327 this should not be enabled, otherwise\n+              the SGMII port will not initialize. When used on the QCA8337, revision 3\n+              or greater, a warning will be displayed. When the CPU port is set to\n+              SGMII on the QCA8337, it is advised to set this unless a communication\n+              issue is observed.\n+\n+        required:\n+          - reg\n+\n+        additionalProperties: false\n+\n+oneOf:\n+  - required:\n+      - ports\n+  - required:\n+      - ethernet-ports\n+\n+required:\n+  - compatible\n+  - reg\n+\n+additionalProperties: true\n+\n+examples:\n+  - |\n+    #include <dt-bindings/gpio/gpio.h>\n+\n+    mdio {\n+        #address-cells = <1>;\n+        #size-cells = <0>;\n+\n+        external_phy_port1: ethernet-phy@0 {\n+            reg = <0>;\n+        };\n+\n+        external_phy_port2: ethernet-phy@1 {\n+            reg = <1>;\n+        };\n+\n+        external_phy_port3: ethernet-phy@2 {\n+            reg = <2>;\n+        };\n+\n+        external_phy_port4: ethernet-phy@3 {\n+            reg = <3>;\n+        };\n+\n+        external_phy_port5: ethernet-phy@4 {\n+            reg = <4>;\n+        };\n+\n+        switch@10 {\n+            compatible = \"qca,qca8337\";\n+            #address-cells = <1>;\n+            #size-cells = <0>;\n+            reset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>;\n+            reg = <0x10>;\n+\n+            ports {\n+                #address-cells = <1>;\n+                #size-cells = <0>;\n+\n+                port@0 {\n+                    reg = <0>;\n+                    label = \"cpu\";\n+                    ethernet = <&gmac1>;\n+                    phy-mode = \"rgmii\";\n+\n+                    fixed-link {\n+                        speed = <1000>;\n+                        full-duplex;\n+                    };\n+                };\n+\n+                port@1 {\n+                    reg = <1>;\n+                    label = \"lan1\";\n+                    phy-handle = <&external_phy_port1>;\n+                };\n+\n+                port@2 {\n+                    reg = <2>;\n+                    label = \"lan2\";\n+                    phy-handle = <&external_phy_port2>;\n+                };\n+\n+                port@3 {\n+                    reg = <3>;\n+                    label = \"lan3\";\n+                    phy-handle = <&external_phy_port3>;\n+                };\n+\n+                port@4 {\n+                    reg = <4>;\n+                    label = \"lan4\";\n+                    phy-handle = <&external_phy_port4>;\n+                };\n+\n+                port@5 {\n+                    reg = <5>;\n+                    label = \"wan\";\n+                    phy-handle = <&external_phy_port5>;\n+                };\n+            };\n+        };\n+    };\n+  - |\n+    #include <dt-bindings/gpio/gpio.h>\n+\n+    mdio {\n+        #address-cells = <1>;\n+        #size-cells = <0>;\n+\n+        switch@10 {\n+            compatible = \"qca,qca8337\";\n+            #address-cells = <1>;\n+            #size-cells = <0>;\n+            reset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>;\n+            reg = <0x10>;\n+\n+            ports {\n+                #address-cells = <1>;\n+                #size-cells = <0>;\n+\n+                port@0 {\n+                    reg = <0>;\n+                    label = \"cpu\";\n+                    ethernet = <&gmac1>;\n+                    phy-mode = \"rgmii\";\n+\n+                    fixed-link {\n+                        speed = <1000>;\n+                        full-duplex;\n+                    };\n+                };\n+\n+                port@1 {\n+                    reg = <1>;\n+                    label = \"lan1\";\n+                    phy-mode = \"internal\";\n+                    phy-handle = <&internal_phy_port1>;\n+                };\n+\n+                port@2 {\n+                    reg = <2>;\n+                    label = \"lan2\";\n+                    phy-mode = \"internal\";\n+                    phy-handle = <&internal_phy_port2>;\n+                };\n+\n+                port@3 {\n+                    reg = <3>;\n+                    label = \"lan3\";\n+                    phy-mode = \"internal\";\n+                    phy-handle = <&internal_phy_port3>;\n+                };\n+\n+                port@4 {\n+                    reg = <4>;\n+                    label = \"lan4\";\n+                    phy-mode = \"internal\";\n+                    phy-handle = <&internal_phy_port4>;\n+                };\n+\n+                port@5 {\n+                    reg = <5>;\n+                    label = \"wan\";\n+                    phy-mode = \"internal\";\n+                    phy-handle = <&internal_phy_port5>;\n+                };\n+\n+                port@6 {\n+                    reg = <0>;\n+                    label = \"cpu\";\n+                    ethernet = <&gmac1>;\n+                    phy-mode = \"sgmii\";\n+\n+                    qca,sgmii-rxclk-falling-edge;\n+\n+                    fixed-link {\n+                        speed = <1000>;\n+                        full-duplex;\n+                    };\n+                };\n+            };\n+\n+            mdio {\n+                #address-cells = <1>;\n+                #size-cells = <0>;\n+\n+                internal_phy_port1: ethernet-phy@0 {\n+                    reg = <0>;\n+                };\n+\n+                internal_phy_port2: ethernet-phy@1 {\n+                    reg = <1>;\n+                };\n+\n+                internal_phy_port3: ethernet-phy@2 {\n+                    reg = <2>;\n+                };\n+\n+                internal_phy_port4: ethernet-phy@3 {\n+                    reg = <3>;\n+                };\n+\n+                internal_phy_port5: ethernet-phy@4 {\n+                    reg = <4>;\n+                };\n+            };\n+        };\n+    };\n"
  },
  {
    "path": "target/linux/generic/backport-5.15/748-v5.16-net-dsa-qca8k-fix-delay-applied-to-wrong-cpu-in-parse-p.patch",
    "content": "From 06dd34a628ae5b6a839b757e746de165d6789ca8 Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Sun, 17 Oct 2021 16:56:46 +0200\nSubject: net: dsa: qca8k: fix delay applied to wrong cpu in parse_port_config\n\nFix delay settings applied to wrong cpu in parse_port_config. The delay\nvalues is set to the wrong index as the cpu_port_index is incremented\ntoo early. Start the cpu_port_index to -1 so the correct value is\napplied to address also the case with invalid phy mode and not available\nport.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/dsa/qca8k.c | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/drivers/net/dsa/qca8k.c\n+++ b/drivers/net/dsa/qca8k.c\n@@ -976,7 +976,7 @@ qca8k_setup_of_pws_reg(struct qca8k_priv\n static int\n qca8k_parse_port_config(struct qca8k_priv *priv)\n {\n-\tint port, cpu_port_index = 0, ret;\n+\tint port, cpu_port_index = -1, ret;\n \tstruct device_node *port_dn;\n \tphy_interface_t mode;\n \tstruct dsa_port *dp;\n"
  },
  {
    "path": "target/linux/generic/backport-5.15/749-v5.16-net-dsa-qca8k-tidy-for-loop-in-setup-and-add-cpu-port-c.patch",
    "content": "From 040e926f5813a5f4cc18dbff7c942d1e52f368f2 Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Tue, 19 Oct 2021 02:08:50 +0200\nSubject: net: dsa: qca8k: tidy for loop in setup and add cpu port check\n\nTidy and organize qca8k setup function from multiple for loop.\nChange for loop in bridge leave/join to scan all port and skip cpu port.\nNo functional change intended.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/dsa/qca8k.c | 74 +++++++++++++++++++++++++++++--------------------\n 1 file changed, 44 insertions(+), 30 deletions(-)\n\n--- a/drivers/net/dsa/qca8k.c\n+++ b/drivers/net/dsa/qca8k.c\n@@ -1122,28 +1122,34 @@ qca8k_setup(struct dsa_switch *ds)\n \tif (ret)\n \t\tdev_warn(priv->dev, \"mib init failed\");\n \n-\t/* Enable QCA header mode on the cpu port */\n-\tret = qca8k_write(priv, QCA8K_REG_PORT_HDR_CTRL(cpu_port),\n-\t\t\t  QCA8K_PORT_HDR_CTRL_ALL << QCA8K_PORT_HDR_CTRL_TX_S |\n-\t\t\t  QCA8K_PORT_HDR_CTRL_ALL << QCA8K_PORT_HDR_CTRL_RX_S);\n-\tif (ret) {\n-\t\tdev_err(priv->dev, \"failed enabling QCA header mode\");\n-\t\treturn ret;\n-\t}\n-\n-\t/* Disable forwarding by default on all ports */\n+\t/* Initial setup of all ports */\n \tfor (i = 0; i < QCA8K_NUM_PORTS; i++) {\n+\t\t/* Disable forwarding by default on all ports */\n \t\tret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i),\n \t\t\t\tQCA8K_PORT_LOOKUP_MEMBER, 0);\n \t\tif (ret)\n \t\t\treturn ret;\n-\t}\n \n-\t/* Disable MAC by default on all ports */\n-\tfor (i = 1; i < QCA8K_NUM_PORTS; i++)\n-\t\tqca8k_port_set_status(priv, i, 0);\n+\t\t/* Enable QCA header mode on all cpu ports */\n+\t\tif (dsa_is_cpu_port(ds, i)) {\n+\t\t\tret = qca8k_write(priv, QCA8K_REG_PORT_HDR_CTRL(i),\n+\t\t\t\t\t  QCA8K_PORT_HDR_CTRL_ALL << QCA8K_PORT_HDR_CTRL_TX_S |\n+\t\t\t\t\t  QCA8K_PORT_HDR_CTRL_ALL << QCA8K_PORT_HDR_CTRL_RX_S);\n+\t\t\tif (ret) {\n+\t\t\t\tdev_err(priv->dev, \"failed enabling QCA header mode\");\n+\t\t\t\treturn ret;\n+\t\t\t}\n+\t\t}\n+\n+\t\t/* Disable MAC by default on all user ports */\n+\t\tif (dsa_is_user_port(ds, i))\n+\t\t\tqca8k_port_set_status(priv, i, 0);\n+\t}\n \n-\t/* Forward all unknown frames to CPU port for Linux processing */\n+\t/* Forward all unknown frames to CPU port for Linux processing\n+\t * Notice that in multi-cpu config only one port should be set\n+\t * for igmp, unknown, multicast and broadcast packet\n+\t */\n \tret = qca8k_write(priv, QCA8K_REG_GLOBAL_FW_CTRL1,\n \t\t\t  BIT(cpu_port) << QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_S |\n \t\t\t  BIT(cpu_port) << QCA8K_GLOBAL_FW_CTRL1_BC_DP_S |\n@@ -1152,11 +1158,13 @@ qca8k_setup(struct dsa_switch *ds)\n \tif (ret)\n \t\treturn ret;\n \n-\t/* Setup connection between CPU port & user ports */\n+\t/* Setup connection between CPU port & user ports\n+\t * Configure specific switch configuration for ports\n+\t */\n \tfor (i = 0; i < QCA8K_NUM_PORTS; i++) {\n \t\t/* CPU port gets connected to all user ports of the switch */\n \t\tif (dsa_is_cpu_port(ds, i)) {\n-\t\t\tret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(cpu_port),\n+\t\t\tret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i),\n \t\t\t\t\tQCA8K_PORT_LOOKUP_MEMBER, dsa_user_ports(ds));\n \t\t\tif (ret)\n \t\t\t\treturn ret;\n@@ -1193,16 +1201,14 @@ qca8k_setup(struct dsa_switch *ds)\n \t\t\tif (ret)\n \t\t\t\treturn ret;\n \t\t}\n-\t}\n \n-\t/* The port 5 of the qca8337 have some problem in flood condition. The\n-\t * original legacy driver had some specific buffer and priority settings\n-\t * for the different port suggested by the QCA switch team. Add this\n-\t * missing settings to improve switch stability under load condition.\n-\t * This problem is limited to qca8337 and other qca8k switch are not affected.\n-\t */\n-\tif (priv->switch_id == QCA8K_ID_QCA8337) {\n-\t\tfor (i = 0; i < QCA8K_NUM_PORTS; i++) {\n+\t\t/* The port 5 of the qca8337 have some problem in flood condition. The\n+\t\t * original legacy driver had some specific buffer and priority settings\n+\t\t * for the different port suggested by the QCA switch team. Add this\n+\t\t * missing settings to improve switch stability under load condition.\n+\t\t * This problem is limited to qca8337 and other qca8k switch are not affected.\n+\t\t */\n+\t\tif (priv->switch_id == QCA8K_ID_QCA8337) {\n \t\t\tswitch (i) {\n \t\t\t/* The 2 CPU port and port 5 requires some different\n \t\t\t * priority than any other ports.\n@@ -1238,6 +1244,12 @@ qca8k_setup(struct dsa_switch *ds)\n \t\t\t\t  QCA8K_PORT_HOL_CTRL1_WRED_EN,\n \t\t\t\t  mask);\n \t\t}\n+\n+\t\t/* Set initial MTU for every port.\n+\t\t * We have only have a general MTU setting. So track\n+\t\t * every port and set the max across all port.\n+\t\t */\n+\t\tpriv->port_mtu[i] = ETH_FRAME_LEN + ETH_FCS_LEN;\n \t}\n \n \t/* Special GLOBAL_FC_THRESH value are needed for ar8327 switch */\n@@ -1251,8 +1263,6 @@ qca8k_setup(struct dsa_switch *ds)\n \t}\n \n \t/* Setup our port MTUs to match power on defaults */\n-\tfor (i = 0; i < QCA8K_NUM_PORTS; i++)\n-\t\tpriv->port_mtu[i] = ETH_FRAME_LEN + ETH_FCS_LEN;\n \tret = qca8k_write(priv, QCA8K_MAX_FRAME_SIZE, ETH_FRAME_LEN + ETH_FCS_LEN);\n \tif (ret)\n \t\tdev_warn(priv->dev, \"failed setting MTU settings\");\n@@ -1728,7 +1738,9 @@ qca8k_port_bridge_join(struct dsa_switch\n \tcpu_port = dsa_to_port(ds, port)->cpu_dp->index;\n \tport_mask = BIT(cpu_port);\n \n-\tfor (i = 1; i < QCA8K_NUM_PORTS; i++) {\n+\tfor (i = 0; i < QCA8K_NUM_PORTS; i++) {\n+\t\tif (dsa_is_cpu_port(ds, i))\n+\t\t\tcontinue;\n \t\tif (dsa_to_port(ds, i)->bridge_dev != br)\n \t\t\tcontinue;\n \t\t/* Add this port to the portvlan mask of the other ports\n@@ -1758,7 +1770,9 @@ qca8k_port_bridge_leave(struct dsa_switc\n \n \tcpu_port = dsa_to_port(ds, port)->cpu_dp->index;\n \n-\tfor (i = 1; i < QCA8K_NUM_PORTS; i++) {\n+\tfor (i = 0; i < QCA8K_NUM_PORTS; i++) {\n+\t\tif (dsa_is_cpu_port(ds, i))\n+\t\t\tcontinue;\n \t\tif (dsa_to_port(ds, i)->bridge_dev != br)\n \t\t\tcontinue;\n \t\t/* Remove this port to the portvlan mask of the other ports\n"
  },
  {
    "path": "target/linux/generic/backport-5.15/750-v5.16-net-dsa-qca8k-make-sure-pad0-mac06-exchange-is-disabled.patch",
    "content": "From 5f15d392dcb4aa250a63d6f2c5adfc26c0aedc78 Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Tue, 2 Nov 2021 19:30:41 +0100\nSubject: net: dsa: qca8k: make sure PAD0 MAC06 exchange is disabled\n\nSome device set MAC06 exchange in the bootloader. This cause some\nproblem as we don't support this strange mode and we just set the port6\nas the primary CPU port. With MAC06 exchange, PAD0 reg configure port6\ninstead of port0. Add an extra check and explicitly disable MAC06 exchange\nto correctly configure the port PAD config.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nFixes: 3fcf734aa482 (\"net: dsa: qca8k: add support for cpu port 6\")\nReviewed-by: Vladimir Oltean <olteanv@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/dsa/qca8k.c | 8 ++++++++\n drivers/net/dsa/qca8k.h | 1 +\n 2 files changed, 9 insertions(+)\n\n--- a/drivers/net/dsa/qca8k.c\n+++ b/drivers/net/dsa/qca8k.c\n@@ -1109,6 +1109,14 @@ qca8k_setup(struct dsa_switch *ds)\n \tif (ret)\n \t\treturn ret;\n \n+\t/* Make sure MAC06 is disabled */\n+\tret = qca8k_reg_clear(priv, QCA8K_REG_PORT0_PAD_CTRL,\n+\t\t\t      QCA8K_PORT0_PAD_MAC06_EXCHANGE_EN);\n+\tif (ret) {\n+\t\tdev_err(priv->dev, \"failed disabling MAC06 exchange\");\n+\t\treturn ret;\n+\t}\n+\n \t/* Enable CPU Port */\n \tret = qca8k_reg_set(priv, QCA8K_REG_GLOBAL_FW_CTRL0,\n \t\t\t    QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN);\n--- a/drivers/net/dsa/qca8k.h\n+++ b/drivers/net/dsa/qca8k.h\n@@ -34,6 +34,7 @@\n #define   QCA8K_MASK_CTRL_DEVICE_ID_MASK\t\tGENMASK(15, 8)\n #define   QCA8K_MASK_CTRL_DEVICE_ID(x)\t\t\t((x) >> 8)\n #define QCA8K_REG_PORT0_PAD_CTRL\t\t\t0x004\n+#define   QCA8K_PORT0_PAD_MAC06_EXCHANGE_EN\t\tBIT(31)\n #define   QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE\tBIT(19)\n #define   QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE\tBIT(18)\n #define QCA8K_REG_PORT5_PAD_CTRL\t\t\t0x008\n"
  },
  {
    "path": "target/linux/generic/backport-5.15/751-v5.16-net-dsa-qca8k-fix-internal-delay-applied-to-the-wrong-PAD.patch",
    "content": "From 3b00a07c2443745d62babfe08dbb2ad8e649526e Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Fri, 19 Nov 2021 03:03:49 +0100\nSubject: [PATCH] net: dsa: qca8k: fix internal delay applied to the wrong PAD\n config\n\nWith SGMII phy the internal delay is always applied to the PAD0 config.\nThis is caused by the falling edge configuration that hardcode the reg\nto PAD0 (as the falling edge bits are present only in PAD0 reg)\nMove the delay configuration before the reg overwrite to correctly apply\nthe delay.\n\nFixes: cef08115846e (\"net: dsa: qca8k: set internal delay also for sgmii\")\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nReviewed-by: Vladimir Oltean <olteanv@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/dsa/qca8k.c | 12 ++++++------\n 1 file changed, 6 insertions(+), 6 deletions(-)\n\n--- a/drivers/net/dsa/qca8k.c\n+++ b/drivers/net/dsa/qca8k.c\n@@ -1433,6 +1433,12 @@ qca8k_phylink_mac_config(struct dsa_swit\n \n \t\tqca8k_write(priv, QCA8K_REG_SGMII_CTRL, val);\n \n+\t\t/* From original code is reported port instability as SGMII also\n+\t\t * require delay set. Apply advised values here or take them from DT.\n+\t\t */\n+\t\tif (state->interface == PHY_INTERFACE_MODE_SGMII)\n+\t\t\tqca8k_mac_config_setup_internal_delay(priv, cpu_port_index, reg);\n+\n \t\t/* For qca8327/qca8328/qca8334/qca8338 sgmii is unique and\n \t\t * falling edge is set writing in the PORT0 PAD reg\n \t\t */\n@@ -1455,12 +1461,6 @@ qca8k_phylink_mac_config(struct dsa_swit\n \t\t\t\t\tQCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE,\n \t\t\t\t\tval);\n \n-\t\t/* From original code is reported port instability as SGMII also\n-\t\t * require delay set. Apply advised values here or take them from DT.\n-\t\t */\n-\t\tif (state->interface == PHY_INTERFACE_MODE_SGMII)\n-\t\t\tqca8k_mac_config_setup_internal_delay(priv, cpu_port_index, reg);\n-\n \t\tbreak;\n \tdefault:\n \t\tdev_err(ds->dev, \"xMII mode %s not supported for port %d\\n\",\n"
  },
  {
    "path": "target/linux/generic/backport-5.15/752-v5.16-net-dsa-qca8k-fix-MTU-calculation.patch",
    "content": "From 65258b9d8cde45689bdc86ca39b50f01f983733b Mon Sep 17 00:00:00 2001\nFrom: Robert Marko <robert.marko@sartura.hr>\nDate: Fri, 19 Nov 2021 03:03:50 +0100\nSubject: [PATCH] net: dsa: qca8k: fix MTU calculation\n\nqca8k has a global MTU, so its tracking the MTU per port to make sure\nthat the largest MTU gets applied.\nSince it uses the frame size instead of MTU the driver MTU change function\nwill then add the size of Ethernet header and checksum on top of MTU.\n\nThe driver currently populates the per port MTU size as Ethernet frame\nlength + checksum which equals 1518.\n\nThe issue is that then MTU change function will go through all of the\nports, find the largest MTU and apply the Ethernet header + checksum on\ntop of it again, so for a desired MTU of 1500 you will end up with 1536.\n\nThis is obviously incorrect, so to correct it populate the per port struct\nMTU with just the MTU and not include the Ethernet header + checksum size\nas those will be added by the MTU change function.\n\nFixes: f58d2598cf70 (\"net: dsa: qca8k: implement the port MTU callbacks\")\nSigned-off-by: Robert Marko <robert.marko@sartura.hr>\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nReviewed-by: Vladimir Oltean <olteanv@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/dsa/qca8k.c | 6 +++++-\n 1 file changed, 5 insertions(+), 1 deletion(-)\n\n--- a/drivers/net/dsa/qca8k.c\n+++ b/drivers/net/dsa/qca8k.c\n@@ -1256,8 +1256,12 @@ qca8k_setup(struct dsa_switch *ds)\n \t\t/* Set initial MTU for every port.\n \t\t * We have only have a general MTU setting. So track\n \t\t * every port and set the max across all port.\n+\t\t * Set per port MTU to 1500 as the MTU change function\n+\t\t * will add the overhead and if its set to 1518 then it\n+\t\t * will apply the overhead again and we will end up with\n+\t\t * MTU of 1536 instead of 1518\n \t\t */\n-\t\tpriv->port_mtu[i] = ETH_FRAME_LEN + ETH_FCS_LEN;\n+\t\tpriv->port_mtu[i] = ETH_DATA_LEN;\n \t}\n \n \t/* Special GLOBAL_FC_THRESH value are needed for ar8327 switch */\n"
  },
  {
    "path": "target/linux/generic/backport-5.15/753-net-next-net-dsa-qca8k-remove-redundant-check-in-parse_port_config.patch",
    "content": "From b9133f3ef5a2659730cf47a74bd0a9259f1cf8ff Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Mon, 22 Nov 2021 16:23:40 +0100\nSubject: net: dsa: qca8k: remove redundant check in parse_port_config\n\nThe very next check for port 0 and 6 already makes sure we don't go out\nof bounds with the ports_config delay table.\nRemove the redundant check.\n\nReported-by: kernel test robot <lkp@intel.com>\nReported-by: Dan Carpenter <dan.carpenter@oracle.com>\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nReviewed-by: Vladimir Oltean <olteanv@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/dsa/qca8k.c | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/drivers/net/dsa/qca8k.c\n+++ b/drivers/net/dsa/qca8k.c\n@@ -983,7 +983,7 @@ qca8k_parse_port_config(struct qca8k_pri\n \tu32 delay;\n \n \t/* We have 2 CPU port. Check them */\n-\tfor (port = 0; port < QCA8K_NUM_PORTS && cpu_port_index < QCA8K_NUM_CPU_PORTS; port++) {\n+\tfor (port = 0; port < QCA8K_NUM_PORTS; port++) {\n \t\t/* Skip every other port */\n \t\tif (port != 0 && port != 6)\n \t\t\tcontinue;\n"
  },
  {
    "path": "target/linux/generic/backport-5.15/754-net-next-net-dsa-qca8k-convert-to-GENMASK_FIELD_PREP_FIELD_GET.patch",
    "content": "From 90ae68bfc2ffcb54a4ba4f64edbeb84a80cbb57c Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Mon, 22 Nov 2021 16:23:41 +0100\nSubject: net: dsa: qca8k: convert to GENMASK/FIELD_PREP/FIELD_GET\n\nConvert and try to standardize bit fields using\nGENMASK/FIELD_PREP/FIELD_GET macros. Rework some logic to support the\nstandard macro and tidy things up. No functional change intended.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/dsa/qca8k.c |  98 +++++++++++++++----------------\n drivers/net/dsa/qca8k.h | 153 ++++++++++++++++++++++++++----------------------\n 2 files changed, 130 insertions(+), 121 deletions(-)\n\n--- a/drivers/net/dsa/qca8k.c\n+++ b/drivers/net/dsa/qca8k.c\n@@ -9,6 +9,7 @@\n #include <linux/module.h>\n #include <linux/phy.h>\n #include <linux/netdevice.h>\n+#include <linux/bitfield.h>\n #include <net/dsa.h>\n #include <linux/of_net.h>\n #include <linux/of_mdio.h>\n@@ -319,18 +320,18 @@ qca8k_fdb_read(struct qca8k_priv *priv,\n \t}\n \n \t/* vid - 83:72 */\n-\tfdb->vid = (reg[2] >> QCA8K_ATU_VID_S) & QCA8K_ATU_VID_M;\n+\tfdb->vid = FIELD_GET(QCA8K_ATU_VID_MASK, reg[2]);\n \t/* aging - 67:64 */\n-\tfdb->aging = reg[2] & QCA8K_ATU_STATUS_M;\n+\tfdb->aging = FIELD_GET(QCA8K_ATU_STATUS_MASK, reg[2]);\n \t/* portmask - 54:48 */\n-\tfdb->port_mask = (reg[1] >> QCA8K_ATU_PORT_S) & QCA8K_ATU_PORT_M;\n+\tfdb->port_mask = FIELD_GET(QCA8K_ATU_PORT_MASK, reg[1]);\n \t/* mac - 47:0 */\n-\tfdb->mac[0] = (reg[1] >> QCA8K_ATU_ADDR0_S) & 0xff;\n-\tfdb->mac[1] = reg[1] & 0xff;\n-\tfdb->mac[2] = (reg[0] >> QCA8K_ATU_ADDR2_S) & 0xff;\n-\tfdb->mac[3] = (reg[0] >> QCA8K_ATU_ADDR3_S) & 0xff;\n-\tfdb->mac[4] = (reg[0] >> QCA8K_ATU_ADDR4_S) & 0xff;\n-\tfdb->mac[5] = reg[0] & 0xff;\n+\tfdb->mac[0] = FIELD_GET(QCA8K_ATU_ADDR0_MASK, reg[1]);\n+\tfdb->mac[1] = FIELD_GET(QCA8K_ATU_ADDR1_MASK, reg[1]);\n+\tfdb->mac[2] = FIELD_GET(QCA8K_ATU_ADDR2_MASK, reg[0]);\n+\tfdb->mac[3] = FIELD_GET(QCA8K_ATU_ADDR3_MASK, reg[0]);\n+\tfdb->mac[4] = FIELD_GET(QCA8K_ATU_ADDR4_MASK, reg[0]);\n+\tfdb->mac[5] = FIELD_GET(QCA8K_ATU_ADDR5_MASK, reg[0]);\n \n \treturn 0;\n }\n@@ -343,18 +344,18 @@ qca8k_fdb_write(struct qca8k_priv *priv,\n \tint i;\n \n \t/* vid - 83:72 */\n-\treg[2] = (vid & QCA8K_ATU_VID_M) << QCA8K_ATU_VID_S;\n+\treg[2] = FIELD_PREP(QCA8K_ATU_VID_MASK, vid);\n \t/* aging - 67:64 */\n-\treg[2] |= aging & QCA8K_ATU_STATUS_M;\n+\treg[2] |= FIELD_PREP(QCA8K_ATU_STATUS_MASK, aging);\n \t/* portmask - 54:48 */\n-\treg[1] = (port_mask & QCA8K_ATU_PORT_M) << QCA8K_ATU_PORT_S;\n+\treg[1] = FIELD_PREP(QCA8K_ATU_PORT_MASK, port_mask);\n \t/* mac - 47:0 */\n-\treg[1] |= mac[0] << QCA8K_ATU_ADDR0_S;\n-\treg[1] |= mac[1];\n-\treg[0] |= mac[2] << QCA8K_ATU_ADDR2_S;\n-\treg[0] |= mac[3] << QCA8K_ATU_ADDR3_S;\n-\treg[0] |= mac[4] << QCA8K_ATU_ADDR4_S;\n-\treg[0] |= mac[5];\n+\treg[1] |= FIELD_PREP(QCA8K_ATU_ADDR0_MASK, mac[0]);\n+\treg[1] |= FIELD_PREP(QCA8K_ATU_ADDR1_MASK, mac[1]);\n+\treg[0] |= FIELD_PREP(QCA8K_ATU_ADDR2_MASK, mac[2]);\n+\treg[0] |= FIELD_PREP(QCA8K_ATU_ADDR3_MASK, mac[3]);\n+\treg[0] |= FIELD_PREP(QCA8K_ATU_ADDR4_MASK, mac[4]);\n+\treg[0] |= FIELD_PREP(QCA8K_ATU_ADDR5_MASK, mac[5]);\n \n \t/* load the array into the ARL table */\n \tfor (i = 0; i < 3; i++)\n@@ -372,7 +373,7 @@ qca8k_fdb_access(struct qca8k_priv *priv\n \treg |= cmd;\n \tif (port >= 0) {\n \t\treg |= QCA8K_ATU_FUNC_PORT_EN;\n-\t\treg |= (port & QCA8K_ATU_FUNC_PORT_M) << QCA8K_ATU_FUNC_PORT_S;\n+\t\treg |= FIELD_PREP(QCA8K_ATU_FUNC_PORT_MASK, port);\n \t}\n \n \t/* Write the function register triggering the table access */\n@@ -454,7 +455,7 @@ qca8k_vlan_access(struct qca8k_priv *pri\n \t/* Set the command and VLAN index */\n \treg = QCA8K_VTU_FUNC1_BUSY;\n \treg |= cmd;\n-\treg |= vid << QCA8K_VTU_FUNC1_VID_S;\n+\treg |= FIELD_PREP(QCA8K_VTU_FUNC1_VID_MASK, vid);\n \n \t/* Write the function register triggering the table access */\n \tret = qca8k_write(priv, QCA8K_REG_VTU_FUNC1, reg);\n@@ -500,13 +501,11 @@ qca8k_vlan_add(struct qca8k_priv *priv,\n \tif (ret < 0)\n \t\tgoto out;\n \treg |= QCA8K_VTU_FUNC0_VALID | QCA8K_VTU_FUNC0_IVL_EN;\n-\treg &= ~(QCA8K_VTU_FUNC0_EG_MODE_MASK << QCA8K_VTU_FUNC0_EG_MODE_S(port));\n+\treg &= ~QCA8K_VTU_FUNC0_EG_MODE_PORT_MASK(port);\n \tif (untagged)\n-\t\treg |= QCA8K_VTU_FUNC0_EG_MODE_UNTAG <<\n-\t\t\t\tQCA8K_VTU_FUNC0_EG_MODE_S(port);\n+\t\treg |= QCA8K_VTU_FUNC0_EG_MODE_PORT_UNTAG(port);\n \telse\n-\t\treg |= QCA8K_VTU_FUNC0_EG_MODE_TAG <<\n-\t\t\t\tQCA8K_VTU_FUNC0_EG_MODE_S(port);\n+\t\treg |= QCA8K_VTU_FUNC0_EG_MODE_PORT_TAG(port);\n \n \tret = qca8k_write(priv, QCA8K_REG_VTU_FUNC0, reg);\n \tif (ret)\n@@ -534,15 +533,13 @@ qca8k_vlan_del(struct qca8k_priv *priv,\n \tret = qca8k_read(priv, QCA8K_REG_VTU_FUNC0, &reg);\n \tif (ret < 0)\n \t\tgoto out;\n-\treg &= ~(3 << QCA8K_VTU_FUNC0_EG_MODE_S(port));\n-\treg |= QCA8K_VTU_FUNC0_EG_MODE_NOT <<\n-\t\t\tQCA8K_VTU_FUNC0_EG_MODE_S(port);\n+\treg &= ~QCA8K_VTU_FUNC0_EG_MODE_PORT_MASK(port);\n+\treg |= QCA8K_VTU_FUNC0_EG_MODE_PORT_NOT(port);\n \n \t/* Check if we're the last member to be removed */\n \tdel = true;\n \tfor (i = 0; i < QCA8K_NUM_PORTS; i++) {\n-\t\tmask = QCA8K_VTU_FUNC0_EG_MODE_NOT;\n-\t\tmask <<= QCA8K_VTU_FUNC0_EG_MODE_S(i);\n+\t\tmask = QCA8K_VTU_FUNC0_EG_MODE_PORT_NOT(i);\n \n \t\tif ((reg & mask) != mask) {\n \t\t\tdel = false;\n@@ -1014,7 +1011,7 @@ qca8k_parse_port_config(struct qca8k_pri\n \t\t\t\t mode == PHY_INTERFACE_MODE_RGMII_TXID)\n \t\t\t\tdelay = 1;\n \n-\t\t\tif (delay > QCA8K_MAX_DELAY) {\n+\t\t\tif (!FIELD_FIT(QCA8K_PORT_PAD_RGMII_TX_DELAY_MASK, delay)) {\n \t\t\t\tdev_err(priv->dev, \"rgmii tx delay is limited to a max value of 3ns, setting to the max value\");\n \t\t\t\tdelay = 3;\n \t\t\t}\n@@ -1030,7 +1027,7 @@ qca8k_parse_port_config(struct qca8k_pri\n \t\t\t\t mode == PHY_INTERFACE_MODE_RGMII_RXID)\n \t\t\t\tdelay = 2;\n \n-\t\t\tif (delay > QCA8K_MAX_DELAY) {\n+\t\t\tif (!FIELD_FIT(QCA8K_PORT_PAD_RGMII_RX_DELAY_MASK, delay)) {\n \t\t\t\tdev_err(priv->dev, \"rgmii rx delay is limited to a max value of 3ns, setting to the max value\");\n \t\t\t\tdelay = 3;\n \t\t\t}\n@@ -1141,8 +1138,8 @@ qca8k_setup(struct dsa_switch *ds)\n \t\t/* Enable QCA header mode on all cpu ports */\n \t\tif (dsa_is_cpu_port(ds, i)) {\n \t\t\tret = qca8k_write(priv, QCA8K_REG_PORT_HDR_CTRL(i),\n-\t\t\t\t\t  QCA8K_PORT_HDR_CTRL_ALL << QCA8K_PORT_HDR_CTRL_TX_S |\n-\t\t\t\t\t  QCA8K_PORT_HDR_CTRL_ALL << QCA8K_PORT_HDR_CTRL_RX_S);\n+\t\t\t\t\t  FIELD_PREP(QCA8K_PORT_HDR_CTRL_TX_MASK, QCA8K_PORT_HDR_CTRL_ALL) |\n+\t\t\t\t\t  FIELD_PREP(QCA8K_PORT_HDR_CTRL_RX_MASK, QCA8K_PORT_HDR_CTRL_ALL));\n \t\t\tif (ret) {\n \t\t\t\tdev_err(priv->dev, \"failed enabling QCA header mode\");\n \t\t\t\treturn ret;\n@@ -1159,10 +1156,10 @@ qca8k_setup(struct dsa_switch *ds)\n \t * for igmp, unknown, multicast and broadcast packet\n \t */\n \tret = qca8k_write(priv, QCA8K_REG_GLOBAL_FW_CTRL1,\n-\t\t\t  BIT(cpu_port) << QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_S |\n-\t\t\t  BIT(cpu_port) << QCA8K_GLOBAL_FW_CTRL1_BC_DP_S |\n-\t\t\t  BIT(cpu_port) << QCA8K_GLOBAL_FW_CTRL1_MC_DP_S |\n-\t\t\t  BIT(cpu_port) << QCA8K_GLOBAL_FW_CTRL1_UC_DP_S);\n+\t\t\t  FIELD_PREP(QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_MASK, BIT(cpu_port)) |\n+\t\t\t  FIELD_PREP(QCA8K_GLOBAL_FW_CTRL1_BC_DP_MASK, BIT(cpu_port)) |\n+\t\t\t  FIELD_PREP(QCA8K_GLOBAL_FW_CTRL1_MC_DP_MASK, BIT(cpu_port)) |\n+\t\t\t  FIELD_PREP(QCA8K_GLOBAL_FW_CTRL1_UC_DP_MASK, BIT(cpu_port)));\n \tif (ret)\n \t\treturn ret;\n \n@@ -1180,8 +1177,6 @@ qca8k_setup(struct dsa_switch *ds)\n \n \t\t/* Individual user ports get connected to CPU port only */\n \t\tif (dsa_is_user_port(ds, i)) {\n-\t\t\tint shift = 16 * (i % 2);\n-\n \t\t\tret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i),\n \t\t\t\t\tQCA8K_PORT_LOOKUP_MEMBER,\n \t\t\t\t\tBIT(cpu_port));\n@@ -1198,8 +1193,8 @@ qca8k_setup(struct dsa_switch *ds)\n \t\t\t * default egress vid\n \t\t\t */\n \t\t\tret = qca8k_rmw(priv, QCA8K_EGRESS_VLAN(i),\n-\t\t\t\t\t0xfff << shift,\n-\t\t\t\t\tQCA8K_PORT_VID_DEF << shift);\n+\t\t\t\t\tQCA8K_EGREES_VLAN_PORT_MASK(i),\n+\t\t\t\t\tQCA8K_EGREES_VLAN_PORT(i, QCA8K_PORT_VID_DEF));\n \t\t\tif (ret)\n \t\t\t\treturn ret;\n \n@@ -1246,7 +1241,7 @@ qca8k_setup(struct dsa_switch *ds)\n \t\t\tQCA8K_PORT_HOL_CTRL1_EG_PORT_BUF_EN |\n \t\t\tQCA8K_PORT_HOL_CTRL1_WRED_EN;\n \t\t\tqca8k_rmw(priv, QCA8K_REG_PORT_HOL_CTRL1(i),\n-\t\t\t\t  QCA8K_PORT_HOL_CTRL1_ING_BUF |\n+\t\t\t\t  QCA8K_PORT_HOL_CTRL1_ING_BUF_MASK |\n \t\t\t\t  QCA8K_PORT_HOL_CTRL1_EG_PRI_BUF_EN |\n \t\t\t\t  QCA8K_PORT_HOL_CTRL1_EG_PORT_BUF_EN |\n \t\t\t\t  QCA8K_PORT_HOL_CTRL1_WRED_EN,\n@@ -1269,8 +1264,8 @@ qca8k_setup(struct dsa_switch *ds)\n \t\tmask = QCA8K_GLOBAL_FC_GOL_XON_THRES(288) |\n \t\t       QCA8K_GLOBAL_FC_GOL_XOFF_THRES(496);\n \t\tqca8k_rmw(priv, QCA8K_REG_GLOBAL_FC_THRESH,\n-\t\t\t  QCA8K_GLOBAL_FC_GOL_XON_THRES_S |\n-\t\t\t  QCA8K_GLOBAL_FC_GOL_XOFF_THRES_S,\n+\t\t\t  QCA8K_GLOBAL_FC_GOL_XON_THRES_MASK |\n+\t\t\t  QCA8K_GLOBAL_FC_GOL_XOFF_THRES_MASK,\n \t\t\t  mask);\n \t}\n \n@@ -1916,11 +1911,11 @@ qca8k_port_vlan_filtering(struct dsa_swi\n \n \tif (vlan_filtering) {\n \t\tret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),\n-\t\t\t\tQCA8K_PORT_LOOKUP_VLAN_MODE,\n+\t\t\t\tQCA8K_PORT_LOOKUP_VLAN_MODE_MASK,\n \t\t\t\tQCA8K_PORT_LOOKUP_VLAN_MODE_SECURE);\n \t} else {\n \t\tret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),\n-\t\t\t\tQCA8K_PORT_LOOKUP_VLAN_MODE,\n+\t\t\t\tQCA8K_PORT_LOOKUP_VLAN_MODE_MASK,\n \t\t\t\tQCA8K_PORT_LOOKUP_VLAN_MODE_NONE);\n \t}\n \n@@ -1944,10 +1939,9 @@ qca8k_port_vlan_add(struct dsa_switch *d\n \t}\n \n \tif (pvid) {\n-\t\tint shift = 16 * (port % 2);\n-\n \t\tret = qca8k_rmw(priv, QCA8K_EGRESS_VLAN(port),\n-\t\t\t\t0xfff << shift, vlan->vid << shift);\n+\t\t\t\tQCA8K_EGREES_VLAN_PORT_MASK(port),\n+\t\t\t\tQCA8K_EGREES_VLAN_PORT(port, vlan->vid));\n \t\tif (ret)\n \t\t\treturn ret;\n \n@@ -2041,7 +2035,7 @@ static int qca8k_read_switch_id(struct q\n \tif (ret < 0)\n \t\treturn -ENODEV;\n \n-\tid = QCA8K_MASK_CTRL_DEVICE_ID(val & QCA8K_MASK_CTRL_DEVICE_ID_MASK);\n+\tid = QCA8K_MASK_CTRL_DEVICE_ID(val);\n \tif (id != data->id) {\n \t\tdev_err(priv->dev, \"Switch id detected %x but expected %x\", id, data->id);\n \t\treturn -ENODEV;\n@@ -2050,7 +2044,7 @@ static int qca8k_read_switch_id(struct q\n \tpriv->switch_id = id;\n \n \t/* Save revision to communicate to the internal PHY driver */\n-\tpriv->switch_revision = (val & QCA8K_MASK_CTRL_REV_ID_MASK);\n+\tpriv->switch_revision = QCA8K_MASK_CTRL_REV_ID(val);\n \n \treturn 0;\n }\n--- a/drivers/net/dsa/qca8k.h\n+++ b/drivers/net/dsa/qca8k.h\n@@ -30,9 +30,9 @@\n /* Global control registers */\n #define QCA8K_REG_MASK_CTRL\t\t\t\t0x000\n #define   QCA8K_MASK_CTRL_REV_ID_MASK\t\t\tGENMASK(7, 0)\n-#define   QCA8K_MASK_CTRL_REV_ID(x)\t\t\t((x) >> 0)\n+#define   QCA8K_MASK_CTRL_REV_ID(x)\t\t\tFIELD_GET(QCA8K_MASK_CTRL_REV_ID_MASK, x)\n #define   QCA8K_MASK_CTRL_DEVICE_ID_MASK\t\tGENMASK(15, 8)\n-#define   QCA8K_MASK_CTRL_DEVICE_ID(x)\t\t\t((x) >> 8)\n+#define   QCA8K_MASK_CTRL_DEVICE_ID(x)\t\t\tFIELD_GET(QCA8K_MASK_CTRL_DEVICE_ID_MASK, x)\n #define QCA8K_REG_PORT0_PAD_CTRL\t\t\t0x004\n #define   QCA8K_PORT0_PAD_MAC06_EXCHANGE_EN\t\tBIT(31)\n #define   QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE\tBIT(19)\n@@ -41,12 +41,11 @@\n #define QCA8K_REG_PORT6_PAD_CTRL\t\t\t0x00c\n #define   QCA8K_PORT_PAD_RGMII_EN\t\t\tBIT(26)\n #define   QCA8K_PORT_PAD_RGMII_TX_DELAY_MASK\t\tGENMASK(23, 22)\n-#define   QCA8K_PORT_PAD_RGMII_TX_DELAY(x)\t\t((x) << 22)\n+#define   QCA8K_PORT_PAD_RGMII_TX_DELAY(x)\t\tFIELD_PREP(QCA8K_PORT_PAD_RGMII_TX_DELAY_MASK, x)\n #define   QCA8K_PORT_PAD_RGMII_RX_DELAY_MASK\t\tGENMASK(21, 20)\n-#define   QCA8K_PORT_PAD_RGMII_RX_DELAY(x)\t\t((x) << 20)\n+#define   QCA8K_PORT_PAD_RGMII_RX_DELAY(x)\t\tFIELD_PREP(QCA8K_PORT_PAD_RGMII_RX_DELAY_MASK, x)\n #define\t  QCA8K_PORT_PAD_RGMII_TX_DELAY_EN\t\tBIT(25)\n #define   QCA8K_PORT_PAD_RGMII_RX_DELAY_EN\t\tBIT(24)\n-#define   QCA8K_MAX_DELAY\t\t\t\t3\n #define   QCA8K_PORT_PAD_SGMII_EN\t\t\tBIT(7)\n #define QCA8K_REG_PWS\t\t\t\t\t0x010\n #define   QCA8K_PWS_POWER_ON_SEL\t\t\tBIT(31)\n@@ -68,10 +67,12 @@\n #define   QCA8K_MDIO_MASTER_READ\t\t\tBIT(27)\n #define   QCA8K_MDIO_MASTER_WRITE\t\t\t0\n #define   QCA8K_MDIO_MASTER_SUP_PRE\t\t\tBIT(26)\n-#define   QCA8K_MDIO_MASTER_PHY_ADDR(x)\t\t\t((x) << 21)\n-#define   QCA8K_MDIO_MASTER_REG_ADDR(x)\t\t\t((x) << 16)\n-#define   QCA8K_MDIO_MASTER_DATA(x)\t\t\t(x)\n+#define   QCA8K_MDIO_MASTER_PHY_ADDR_MASK\t\tGENMASK(25, 21)\n+#define   QCA8K_MDIO_MASTER_PHY_ADDR(x)\t\t\tFIELD_PREP(QCA8K_MDIO_MASTER_PHY_ADDR_MASK, x)\n+#define   QCA8K_MDIO_MASTER_REG_ADDR_MASK\t\tGENMASK(20, 16)\n+#define   QCA8K_MDIO_MASTER_REG_ADDR(x)\t\t\tFIELD_PREP(QCA8K_MDIO_MASTER_REG_ADDR_MASK, x)\n #define   QCA8K_MDIO_MASTER_DATA_MASK\t\t\tGENMASK(15, 0)\n+#define   QCA8K_MDIO_MASTER_DATA(x)\t\t\tFIELD_PREP(QCA8K_MDIO_MASTER_DATA_MASK, x)\n #define   QCA8K_MDIO_MASTER_MAX_PORTS\t\t\t5\n #define   QCA8K_MDIO_MASTER_MAX_REG\t\t\t32\n #define QCA8K_GOL_MAC_ADDR0\t\t\t\t0x60\n@@ -93,9 +94,7 @@\n #define   QCA8K_PORT_STATUS_FLOW_AUTO\t\t\tBIT(12)\n #define QCA8K_REG_PORT_HDR_CTRL(_i)\t\t\t(0x9c + (_i * 4))\n #define   QCA8K_PORT_HDR_CTRL_RX_MASK\t\t\tGENMASK(3, 2)\n-#define   QCA8K_PORT_HDR_CTRL_RX_S\t\t\t2\n #define   QCA8K_PORT_HDR_CTRL_TX_MASK\t\t\tGENMASK(1, 0)\n-#define   QCA8K_PORT_HDR_CTRL_TX_S\t\t\t0\n #define   QCA8K_PORT_HDR_CTRL_ALL\t\t\t2\n #define   QCA8K_PORT_HDR_CTRL_MGMT\t\t\t1\n #define   QCA8K_PORT_HDR_CTRL_NONE\t\t\t0\n@@ -105,10 +104,11 @@\n #define   QCA8K_SGMII_EN_TX\t\t\t\tBIT(3)\n #define   QCA8K_SGMII_EN_SD\t\t\t\tBIT(4)\n #define   QCA8K_SGMII_CLK125M_DELAY\t\t\tBIT(7)\n-#define   QCA8K_SGMII_MODE_CTRL_MASK\t\t\t(BIT(22) | BIT(23))\n-#define   QCA8K_SGMII_MODE_CTRL_BASEX\t\t\t(0 << 22)\n-#define   QCA8K_SGMII_MODE_CTRL_PHY\t\t\t(1 << 22)\n-#define   QCA8K_SGMII_MODE_CTRL_MAC\t\t\t(2 << 22)\n+#define   QCA8K_SGMII_MODE_CTRL_MASK\t\t\tGENMASK(23, 22)\n+#define   QCA8K_SGMII_MODE_CTRL(x)\t\t\tFIELD_PREP(QCA8K_SGMII_MODE_CTRL_MASK, x)\n+#define   QCA8K_SGMII_MODE_CTRL_BASEX\t\t\tQCA8K_SGMII_MODE_CTRL(0x0)\n+#define   QCA8K_SGMII_MODE_CTRL_PHY\t\t\tQCA8K_SGMII_MODE_CTRL(0x1)\n+#define   QCA8K_SGMII_MODE_CTRL_MAC\t\t\tQCA8K_SGMII_MODE_CTRL(0x2)\n \n /* MAC_PWR_SEL registers */\n #define QCA8K_REG_MAC_PWR_SEL\t\t\t\t0x0e4\n@@ -121,100 +121,115 @@\n \n /* ACL registers */\n #define QCA8K_REG_PORT_VLAN_CTRL0(_i)\t\t\t(0x420 + (_i * 8))\n-#define   QCA8K_PORT_VLAN_CVID(x)\t\t\t(x << 16)\n-#define   QCA8K_PORT_VLAN_SVID(x)\t\t\tx\n+#define   QCA8K_PORT_VLAN_CVID_MASK\t\t\tGENMASK(27, 16)\n+#define   QCA8K_PORT_VLAN_CVID(x)\t\t\tFIELD_PREP(QCA8K_PORT_VLAN_CVID_MASK, x)\n+#define   QCA8K_PORT_VLAN_SVID_MASK\t\t\tGENMASK(11, 0)\n+#define   QCA8K_PORT_VLAN_SVID(x)\t\t\tFIELD_PREP(QCA8K_PORT_VLAN_SVID_MASK, x)\n #define QCA8K_REG_PORT_VLAN_CTRL1(_i)\t\t\t(0x424 + (_i * 8))\n #define QCA8K_REG_IPV4_PRI_BASE_ADDR\t\t\t0x470\n #define QCA8K_REG_IPV4_PRI_ADDR_MASK\t\t\t0x474\n \n /* Lookup registers */\n #define QCA8K_REG_ATU_DATA0\t\t\t\t0x600\n-#define   QCA8K_ATU_ADDR2_S\t\t\t\t24\n-#define   QCA8K_ATU_ADDR3_S\t\t\t\t16\n-#define   QCA8K_ATU_ADDR4_S\t\t\t\t8\n+#define   QCA8K_ATU_ADDR2_MASK\t\t\t\tGENMASK(31, 24)\n+#define   QCA8K_ATU_ADDR3_MASK\t\t\t\tGENMASK(23, 16)\n+#define   QCA8K_ATU_ADDR4_MASK\t\t\t\tGENMASK(15, 8)\n+#define   QCA8K_ATU_ADDR5_MASK\t\t\t\tGENMASK(7, 0)\n #define QCA8K_REG_ATU_DATA1\t\t\t\t0x604\n-#define   QCA8K_ATU_PORT_M\t\t\t\t0x7f\n-#define   QCA8K_ATU_PORT_S\t\t\t\t16\n-#define   QCA8K_ATU_ADDR0_S\t\t\t\t8\n+#define   QCA8K_ATU_PORT_MASK\t\t\t\tGENMASK(22, 16)\n+#define   QCA8K_ATU_ADDR0_MASK\t\t\t\tGENMASK(15, 8)\n+#define   QCA8K_ATU_ADDR1_MASK\t\t\t\tGENMASK(7, 0)\n #define QCA8K_REG_ATU_DATA2\t\t\t\t0x608\n-#define   QCA8K_ATU_VID_M\t\t\t\t0xfff\n-#define   QCA8K_ATU_VID_S\t\t\t\t8\n-#define   QCA8K_ATU_STATUS_M\t\t\t\t0xf\n+#define   QCA8K_ATU_VID_MASK\t\t\t\tGENMASK(19, 8)\n+#define   QCA8K_ATU_STATUS_MASK\t\t\t\tGENMASK(3, 0)\n #define   QCA8K_ATU_STATUS_STATIC\t\t\t0xf\n #define QCA8K_REG_ATU_FUNC\t\t\t\t0x60c\n #define   QCA8K_ATU_FUNC_BUSY\t\t\t\tBIT(31)\n #define   QCA8K_ATU_FUNC_PORT_EN\t\t\tBIT(14)\n #define   QCA8K_ATU_FUNC_MULTI_EN\t\t\tBIT(13)\n #define   QCA8K_ATU_FUNC_FULL\t\t\t\tBIT(12)\n-#define   QCA8K_ATU_FUNC_PORT_M\t\t\t\t0xf\n-#define   QCA8K_ATU_FUNC_PORT_S\t\t\t\t8\n+#define   QCA8K_ATU_FUNC_PORT_MASK\t\t\tGENMASK(11, 8)\n #define QCA8K_REG_VTU_FUNC0\t\t\t\t0x610\n #define   QCA8K_VTU_FUNC0_VALID\t\t\t\tBIT(20)\n #define   QCA8K_VTU_FUNC0_IVL_EN\t\t\tBIT(19)\n-#define   QCA8K_VTU_FUNC0_EG_MODE_S(_i)\t\t\t(4 + (_i) * 2)\n-#define   QCA8K_VTU_FUNC0_EG_MODE_MASK\t\t\t3\n-#define   QCA8K_VTU_FUNC0_EG_MODE_UNMOD\t\t\t0\n-#define   QCA8K_VTU_FUNC0_EG_MODE_UNTAG\t\t\t1\n-#define   QCA8K_VTU_FUNC0_EG_MODE_TAG\t\t\t2\n-#define   QCA8K_VTU_FUNC0_EG_MODE_NOT\t\t\t3\n+/*        QCA8K_VTU_FUNC0_EG_MODE_MASK\t\t\tGENMASK(17, 4)\n+ *          It does contain VLAN_MODE for each port [5:4] for port0,\n+ *          [7:6] for port1 ... [17:16] for port6. Use virtual port\n+ *          define to handle this.\n+ */\n+#define   QCA8K_VTU_FUNC0_EG_MODE_PORT_SHIFT(_i)\t(4 + (_i) * 2)\n+#define   QCA8K_VTU_FUNC0_EG_MODE_MASK\t\t\tGENMASK(1, 0)\n+#define   QCA8K_VTU_FUNC0_EG_MODE_PORT_MASK(_i)\t\t(GENMASK(1, 0) << QCA8K_VTU_FUNC0_EG_MODE_PORT_SHIFT(_i))\n+#define   QCA8K_VTU_FUNC0_EG_MODE_UNMOD\t\t\tFIELD_PREP(QCA8K_VTU_FUNC0_EG_MODE_MASK, 0x0)\n+#define   QCA8K_VTU_FUNC0_EG_MODE_PORT_UNMOD(_i)\t(QCA8K_VTU_FUNC0_EG_MODE_UNMOD << QCA8K_VTU_FUNC0_EG_MODE_PORT_SHIFT(_i))\n+#define   QCA8K_VTU_FUNC0_EG_MODE_UNTAG\t\t\tFIELD_PREP(QCA8K_VTU_FUNC0_EG_MODE_MASK, 0x1)\n+#define   QCA8K_VTU_FUNC0_EG_MODE_PORT_UNTAG(_i)\t(QCA8K_VTU_FUNC0_EG_MODE_UNTAG << QCA8K_VTU_FUNC0_EG_MODE_PORT_SHIFT(_i))\n+#define   QCA8K_VTU_FUNC0_EG_MODE_TAG\t\t\tFIELD_PREP(QCA8K_VTU_FUNC0_EG_MODE_MASK, 0x2)\n+#define   QCA8K_VTU_FUNC0_EG_MODE_PORT_TAG(_i)\t\t(QCA8K_VTU_FUNC0_EG_MODE_TAG << QCA8K_VTU_FUNC0_EG_MODE_PORT_SHIFT(_i))\n+#define   QCA8K_VTU_FUNC0_EG_MODE_NOT\t\t\tFIELD_PREP(QCA8K_VTU_FUNC0_EG_MODE_MASK, 0x3)\n+#define   QCA8K_VTU_FUNC0_EG_MODE_PORT_NOT(_i)\t\t(QCA8K_VTU_FUNC0_EG_MODE_NOT << QCA8K_VTU_FUNC0_EG_MODE_PORT_SHIFT(_i))\n #define QCA8K_REG_VTU_FUNC1\t\t\t\t0x614\n #define   QCA8K_VTU_FUNC1_BUSY\t\t\t\tBIT(31)\n-#define   QCA8K_VTU_FUNC1_VID_S\t\t\t\t16\n+#define   QCA8K_VTU_FUNC1_VID_MASK\t\t\tGENMASK(27, 16)\n #define   QCA8K_VTU_FUNC1_FULL\t\t\t\tBIT(4)\n #define QCA8K_REG_GLOBAL_FW_CTRL0\t\t\t0x620\n #define   QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN\t\tBIT(10)\n #define QCA8K_REG_GLOBAL_FW_CTRL1\t\t\t0x624\n-#define   QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_S\t\t24\n-#define   QCA8K_GLOBAL_FW_CTRL1_BC_DP_S\t\t\t16\n-#define   QCA8K_GLOBAL_FW_CTRL1_MC_DP_S\t\t\t8\n-#define   QCA8K_GLOBAL_FW_CTRL1_UC_DP_S\t\t\t0\n+#define   QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_MASK\t\tGENMASK(30, 24)\n+#define   QCA8K_GLOBAL_FW_CTRL1_BC_DP_MASK\t\tGENMASK(22, 16)\n+#define   QCA8K_GLOBAL_FW_CTRL1_MC_DP_MASK\t\tGENMASK(14, 8)\n+#define   QCA8K_GLOBAL_FW_CTRL1_UC_DP_MASK\t\tGENMASK(6, 0)\n #define QCA8K_PORT_LOOKUP_CTRL(_i)\t\t\t(0x660 + (_i) * 0xc)\n #define   QCA8K_PORT_LOOKUP_MEMBER\t\t\tGENMASK(6, 0)\n-#define   QCA8K_PORT_LOOKUP_VLAN_MODE\t\t\tGENMASK(9, 8)\n-#define   QCA8K_PORT_LOOKUP_VLAN_MODE_NONE\t\t(0 << 8)\n-#define   QCA8K_PORT_LOOKUP_VLAN_MODE_FALLBACK\t\t(1 << 8)\n-#define   QCA8K_PORT_LOOKUP_VLAN_MODE_CHECK\t\t(2 << 8)\n-#define   QCA8K_PORT_LOOKUP_VLAN_MODE_SECURE\t\t(3 << 8)\n+#define   QCA8K_PORT_LOOKUP_VLAN_MODE_MASK\t\tGENMASK(9, 8)\n+#define   QCA8K_PORT_LOOKUP_VLAN_MODE(x)\t\tFIELD_PREP(QCA8K_PORT_LOOKUP_VLAN_MODE_MASK, x)\n+#define   QCA8K_PORT_LOOKUP_VLAN_MODE_NONE\t\tQCA8K_PORT_LOOKUP_VLAN_MODE(0x0)\n+#define   QCA8K_PORT_LOOKUP_VLAN_MODE_FALLBACK\t\tQCA8K_PORT_LOOKUP_VLAN_MODE(0x1)\n+#define   QCA8K_PORT_LOOKUP_VLAN_MODE_CHECK\t\tQCA8K_PORT_LOOKUP_VLAN_MODE(0x2)\n+#define   QCA8K_PORT_LOOKUP_VLAN_MODE_SECURE\t\tQCA8K_PORT_LOOKUP_VLAN_MODE(0x3)\n #define   QCA8K_PORT_LOOKUP_STATE_MASK\t\t\tGENMASK(18, 16)\n-#define   QCA8K_PORT_LOOKUP_STATE_DISABLED\t\t(0 << 16)\n-#define   QCA8K_PORT_LOOKUP_STATE_BLOCKING\t\t(1 << 16)\n-#define   QCA8K_PORT_LOOKUP_STATE_LISTENING\t\t(2 << 16)\n-#define   QCA8K_PORT_LOOKUP_STATE_LEARNING\t\t(3 << 16)\n-#define   QCA8K_PORT_LOOKUP_STATE_FORWARD\t\t(4 << 16)\n-#define   QCA8K_PORT_LOOKUP_STATE\t\t\tGENMASK(18, 16)\n+#define   QCA8K_PORT_LOOKUP_STATE(x)\t\t\tFIELD_PREP(QCA8K_PORT_LOOKUP_STATE_MASK, x)\n+#define   QCA8K_PORT_LOOKUP_STATE_DISABLED\t\tQCA8K_PORT_LOOKUP_STATE(0x0)\n+#define   QCA8K_PORT_LOOKUP_STATE_BLOCKING\t\tQCA8K_PORT_LOOKUP_STATE(0x1)\n+#define   QCA8K_PORT_LOOKUP_STATE_LISTENING\t\tQCA8K_PORT_LOOKUP_STATE(0x2)\n+#define   QCA8K_PORT_LOOKUP_STATE_LEARNING\t\tQCA8K_PORT_LOOKUP_STATE(0x3)\n+#define   QCA8K_PORT_LOOKUP_STATE_FORWARD\t\tQCA8K_PORT_LOOKUP_STATE(0x4)\n #define   QCA8K_PORT_LOOKUP_LEARN\t\t\tBIT(20)\n \n #define QCA8K_REG_GLOBAL_FC_THRESH\t\t\t0x800\n-#define   QCA8K_GLOBAL_FC_GOL_XON_THRES(x)\t\t((x) << 16)\n-#define   QCA8K_GLOBAL_FC_GOL_XON_THRES_S\t\tGENMASK(24, 16)\n-#define   QCA8K_GLOBAL_FC_GOL_XOFF_THRES(x)\t\t((x) << 0)\n-#define   QCA8K_GLOBAL_FC_GOL_XOFF_THRES_S\t\tGENMASK(8, 0)\n+#define   QCA8K_GLOBAL_FC_GOL_XON_THRES_MASK\t\tGENMASK(24, 16)\n+#define   QCA8K_GLOBAL_FC_GOL_XON_THRES(x)\t\tFIELD_PREP(QCA8K_GLOBAL_FC_GOL_XON_THRES_MASK, x)\n+#define   QCA8K_GLOBAL_FC_GOL_XOFF_THRES_MASK\t\tGENMASK(8, 0)\n+#define   QCA8K_GLOBAL_FC_GOL_XOFF_THRES(x)\t\tFIELD_PREP(QCA8K_GLOBAL_FC_GOL_XOFF_THRES_MASK, x)\n \n #define QCA8K_REG_PORT_HOL_CTRL0(_i)\t\t\t(0x970 + (_i) * 0x8)\n-#define   QCA8K_PORT_HOL_CTRL0_EG_PRI0_BUF\t\tGENMASK(3, 0)\n-#define   QCA8K_PORT_HOL_CTRL0_EG_PRI0(x)\t\t((x) << 0)\n-#define   QCA8K_PORT_HOL_CTRL0_EG_PRI1_BUF\t\tGENMASK(7, 4)\n-#define   QCA8K_PORT_HOL_CTRL0_EG_PRI1(x)\t\t((x) << 4)\n-#define   QCA8K_PORT_HOL_CTRL0_EG_PRI2_BUF\t\tGENMASK(11, 8)\n-#define   QCA8K_PORT_HOL_CTRL0_EG_PRI2(x)\t\t((x) << 8)\n-#define   QCA8K_PORT_HOL_CTRL0_EG_PRI3_BUF\t\tGENMASK(15, 12)\n-#define   QCA8K_PORT_HOL_CTRL0_EG_PRI3(x)\t\t((x) << 12)\n-#define   QCA8K_PORT_HOL_CTRL0_EG_PRI4_BUF\t\tGENMASK(19, 16)\n-#define   QCA8K_PORT_HOL_CTRL0_EG_PRI4(x)\t\t((x) << 16)\n-#define   QCA8K_PORT_HOL_CTRL0_EG_PRI5_BUF\t\tGENMASK(23, 20)\n-#define   QCA8K_PORT_HOL_CTRL0_EG_PRI5(x)\t\t((x) << 20)\n-#define   QCA8K_PORT_HOL_CTRL0_EG_PORT_BUF\t\tGENMASK(29, 24)\n-#define   QCA8K_PORT_HOL_CTRL0_EG_PORT(x)\t\t((x) << 24)\n+#define   QCA8K_PORT_HOL_CTRL0_EG_PRI0_BUF_MASK\t\tGENMASK(3, 0)\n+#define   QCA8K_PORT_HOL_CTRL0_EG_PRI0(x)\t\tFIELD_PREP(QCA8K_PORT_HOL_CTRL0_EG_PRI0_BUF_MASK, x)\n+#define   QCA8K_PORT_HOL_CTRL0_EG_PRI1_BUF_MASK\t\tGENMASK(7, 4)\n+#define   QCA8K_PORT_HOL_CTRL0_EG_PRI1(x)\t\tFIELD_PREP(QCA8K_PORT_HOL_CTRL0_EG_PRI1_BUF_MASK, x)\n+#define   QCA8K_PORT_HOL_CTRL0_EG_PRI2_BUF_MASK\t\tGENMASK(11, 8)\n+#define   QCA8K_PORT_HOL_CTRL0_EG_PRI2(x)\t\tFIELD_PREP(QCA8K_PORT_HOL_CTRL0_EG_PRI2_BUF_MASK, x)\n+#define   QCA8K_PORT_HOL_CTRL0_EG_PRI3_BUF_MASK\t\tGENMASK(15, 12)\n+#define   QCA8K_PORT_HOL_CTRL0_EG_PRI3(x)\t\tFIELD_PREP(QCA8K_PORT_HOL_CTRL0_EG_PRI3_BUF_MASK, x)\n+#define   QCA8K_PORT_HOL_CTRL0_EG_PRI4_BUF_MASK\t\tGENMASK(19, 16)\n+#define   QCA8K_PORT_HOL_CTRL0_EG_PRI4(x)\t\tFIELD_PREP(QCA8K_PORT_HOL_CTRL0_EG_PRI4_BUF_MASK, x)\n+#define   QCA8K_PORT_HOL_CTRL0_EG_PRI5_BUF_MASK\t\tGENMASK(23, 20)\n+#define   QCA8K_PORT_HOL_CTRL0_EG_PRI5(x)\t\tFIELD_PREP(QCA8K_PORT_HOL_CTRL0_EG_PRI5_BUF_MASK, x)\n+#define   QCA8K_PORT_HOL_CTRL0_EG_PORT_BUF_MASK\t\tGENMASK(29, 24)\n+#define   QCA8K_PORT_HOL_CTRL0_EG_PORT(x)\t\tFIELD_PREP(QCA8K_PORT_HOL_CTRL0_EG_PORT_BUF_MASK, x)\n \n #define QCA8K_REG_PORT_HOL_CTRL1(_i)\t\t\t(0x974 + (_i) * 0x8)\n-#define   QCA8K_PORT_HOL_CTRL1_ING_BUF\t\t\tGENMASK(3, 0)\n-#define   QCA8K_PORT_HOL_CTRL1_ING(x)\t\t\t((x) << 0)\n+#define   QCA8K_PORT_HOL_CTRL1_ING_BUF_MASK\t\tGENMASK(3, 0)\n+#define   QCA8K_PORT_HOL_CTRL1_ING(x)\t\t\tFIELD_PREP(QCA8K_PORT_HOL_CTRL1_ING_BUF_MASK, x)\n #define   QCA8K_PORT_HOL_CTRL1_EG_PRI_BUF_EN\t\tBIT(6)\n #define   QCA8K_PORT_HOL_CTRL1_EG_PORT_BUF_EN\t\tBIT(7)\n #define   QCA8K_PORT_HOL_CTRL1_WRED_EN\t\t\tBIT(8)\n #define   QCA8K_PORT_HOL_CTRL1_EG_MIRROR_EN\t\tBIT(16)\n \n /* Pkt edit registers */\n+#define QCA8K_EGREES_VLAN_PORT_SHIFT(_i)\t\t(16 * ((_i) % 2))\n+#define QCA8K_EGREES_VLAN_PORT_MASK(_i)\t\t\t(GENMASK(11, 0) << QCA8K_EGREES_VLAN_PORT_SHIFT(_i))\n+#define QCA8K_EGREES_VLAN_PORT(_i, x)\t\t\t((x) << QCA8K_EGREES_VLAN_PORT_SHIFT(_i))\n #define QCA8K_EGRESS_VLAN(x)\t\t\t\t(0x0c70 + (4 * (x / 2)))\n \n /* L3 registers */\n"
  },
  {
    "path": "target/linux/generic/backport-5.15/755-net-next-net-dsa-qca8k-remove-extra-mutex_init-in-qca8k_setup.patch",
    "content": "From 994c28b6f971fa5db8ae977daea37eee87d93d51 Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Mon, 22 Nov 2021 16:23:42 +0100\nSubject: net: dsa: qca8k: remove extra mutex_init in qca8k_setup\n\nMutex is already init in sw_probe. Remove the extra init in qca8k_setup.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nReviewed-by: Vladimir Oltean <olteanv@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/dsa/qca8k.c | 2 --\n 1 file changed, 2 deletions(-)\n\n--- a/drivers/net/dsa/qca8k.c\n+++ b/drivers/net/dsa/qca8k.c\n@@ -1086,8 +1086,6 @@ qca8k_setup(struct dsa_switch *ds)\n \tif (ret)\n \t\treturn ret;\n \n-\tmutex_init(&priv->reg_mutex);\n-\n \t/* Start by setting up the register mapping */\n \tpriv->regmap = devm_regmap_init(ds->dev, NULL, priv,\n \t\t\t\t\t&qca8k_regmap_config);\n"
  },
  {
    "path": "target/linux/generic/backport-5.15/756-net-next-net-dsa-qca8k-move-regmap-init-in-probe-and-set-it.patch",
    "content": "From 36b8af12f424e7a7f60a935c60a0fd4aa0822378 Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Mon, 22 Nov 2021 16:23:43 +0100\nSubject: net: dsa: qca8k: move regmap init in probe and set it mandatory\n\nIn preparation for regmap conversion, move regmap init in the probe\nfunction and make it mandatory as any read/write/rmw operation will be\nconverted to regmap API.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nReviewed-by: Vladimir Oltean <olteanv@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/dsa/qca8k.c | 14 ++++++++------\n 1 file changed, 8 insertions(+), 6 deletions(-)\n\n--- a/drivers/net/dsa/qca8k.c\n+++ b/drivers/net/dsa/qca8k.c\n@@ -1086,12 +1086,6 @@ qca8k_setup(struct dsa_switch *ds)\n \tif (ret)\n \t\treturn ret;\n \n-\t/* Start by setting up the register mapping */\n-\tpriv->regmap = devm_regmap_init(ds->dev, NULL, priv,\n-\t\t\t\t\t&qca8k_regmap_config);\n-\tif (IS_ERR(priv->regmap))\n-\t\tdev_warn(priv->dev, \"regmap initialization failed\");\n-\n \tret = qca8k_setup_mdio_bus(priv);\n \tif (ret)\n \t\treturn ret;\n@@ -2077,6 +2071,14 @@ qca8k_sw_probe(struct mdio_device *mdiod\n \t\tgpiod_set_value_cansleep(priv->reset_gpio, 0);\n \t}\n \n+\t/* Start by setting up the register mapping */\n+\tpriv->regmap = devm_regmap_init(&mdiodev->dev, NULL, priv,\n+\t\t\t\t\t&qca8k_regmap_config);\n+\tif (IS_ERR(priv->regmap)) {\n+\t\tdev_err(priv->dev, \"regmap initialization failed\");\n+\t\treturn PTR_ERR(priv->regmap);\n+\t}\n+\n \t/* Check the detected switch id */\n \tret = qca8k_read_switch_id(priv);\n \tif (ret)\n"
  },
  {
    "path": "target/linux/generic/backport-5.15/757-net-next-net-dsa-qca8k-initial-conversion-to-regmap-heper.patch",
    "content": "From 8b5f3f29a81a71934d004e21a1292c1148b05926 Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Mon, 22 Nov 2021 16:23:44 +0100\nSubject: net: dsa: qca8k: initial conversion to regmap helper\n\nConvert any qca8k set/clear/pool to regmap helper and add\nmissing config to regmap_config struct.\nRead/write/rmw operation are reworked to use the regmap helper\ninternally to keep the delta of this patch low. These additional\nfunction will then be dropped when the code split will be proposed.\n\nIpq40xx SoC have the internal switch based on the qca8k regmap but use\nmmio for read/write/rmw operation instead of mdio.\nIn preparation for the support of this internal switch, convert the\ndriver to regmap API to later split the driver to common and specific\ncode. The overhead introduced by the use of regamp API is marginal as the\ninternal mdio will bypass it by using its direct access and regmap will be\nused only by configuration functions or fdb access.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/dsa/qca8k.c | 107 +++++++++++++++++++++---------------------------\n 1 file changed, 47 insertions(+), 60 deletions(-)\n\n--- a/drivers/net/dsa/qca8k.c\n+++ b/drivers/net/dsa/qca8k.c\n@@ -10,6 +10,7 @@\n #include <linux/phy.h>\n #include <linux/netdevice.h>\n #include <linux/bitfield.h>\n+#include <linux/regmap.h>\n #include <net/dsa.h>\n #include <linux/of_net.h>\n #include <linux/of_mdio.h>\n@@ -152,6 +153,25 @@ qca8k_set_page(struct mii_bus *bus, u16\n static int\n qca8k_read(struct qca8k_priv *priv, u32 reg, u32 *val)\n {\n+\treturn regmap_read(priv->regmap, reg, val);\n+}\n+\n+static int\n+qca8k_write(struct qca8k_priv *priv, u32 reg, u32 val)\n+{\n+\treturn regmap_write(priv->regmap, reg, val);\n+}\n+\n+static int\n+qca8k_rmw(struct qca8k_priv *priv, u32 reg, u32 mask, u32 write_val)\n+{\n+\treturn regmap_update_bits(priv->regmap, reg, mask, write_val);\n+}\n+\n+static int\n+qca8k_regmap_read(void *ctx, uint32_t reg, uint32_t *val)\n+{\n+\tstruct qca8k_priv *priv = (struct qca8k_priv *)ctx;\n \tstruct mii_bus *bus = priv->bus;\n \tu16 r1, r2, page;\n \tint ret;\n@@ -172,8 +192,9 @@ exit:\n }\n \n static int\n-qca8k_write(struct qca8k_priv *priv, u32 reg, u32 val)\n+qca8k_regmap_write(void *ctx, uint32_t reg, uint32_t val)\n {\n+\tstruct qca8k_priv *priv = (struct qca8k_priv *)ctx;\n \tstruct mii_bus *bus = priv->bus;\n \tu16 r1, r2, page;\n \tint ret;\n@@ -194,8 +215,9 @@ exit:\n }\n \n static int\n-qca8k_rmw(struct qca8k_priv *priv, u32 reg, u32 mask, u32 write_val)\n+qca8k_regmap_update_bits(void *ctx, uint32_t reg, uint32_t mask, uint32_t write_val)\n {\n+\tstruct qca8k_priv *priv = (struct qca8k_priv *)ctx;\n \tstruct mii_bus *bus = priv->bus;\n \tu16 r1, r2, page;\n \tu32 val;\n@@ -223,34 +245,6 @@ exit:\n \treturn ret;\n }\n \n-static int\n-qca8k_reg_set(struct qca8k_priv *priv, u32 reg, u32 val)\n-{\n-\treturn qca8k_rmw(priv, reg, 0, val);\n-}\n-\n-static int\n-qca8k_reg_clear(struct qca8k_priv *priv, u32 reg, u32 val)\n-{\n-\treturn qca8k_rmw(priv, reg, val, 0);\n-}\n-\n-static int\n-qca8k_regmap_read(void *ctx, uint32_t reg, uint32_t *val)\n-{\n-\tstruct qca8k_priv *priv = (struct qca8k_priv *)ctx;\n-\n-\treturn qca8k_read(priv, reg, val);\n-}\n-\n-static int\n-qca8k_regmap_write(void *ctx, uint32_t reg, uint32_t val)\n-{\n-\tstruct qca8k_priv *priv = (struct qca8k_priv *)ctx;\n-\n-\treturn qca8k_write(priv, reg, val);\n-}\n-\n static const struct regmap_range qca8k_readable_ranges[] = {\n \tregmap_reg_range(0x0000, 0x00e4), /* Global control */\n \tregmap_reg_range(0x0100, 0x0168), /* EEE control */\n@@ -282,26 +276,19 @@ static struct regmap_config qca8k_regmap\n \t.max_register = 0x16ac, /* end MIB - Port6 range */\n \t.reg_read = qca8k_regmap_read,\n \t.reg_write = qca8k_regmap_write,\n+\t.reg_update_bits = qca8k_regmap_update_bits,\n \t.rd_table = &qca8k_readable_table,\n+\t.disable_locking = true, /* Locking is handled by qca8k read/write */\n+\t.cache_type = REGCACHE_NONE, /* Explicitly disable CACHE */\n };\n \n static int\n qca8k_busy_wait(struct qca8k_priv *priv, u32 reg, u32 mask)\n {\n-\tint ret, ret1;\n \tu32 val;\n \n-\tret = read_poll_timeout(qca8k_read, ret1, !(val & mask),\n-\t\t\t\t0, QCA8K_BUSY_WAIT_TIMEOUT * USEC_PER_MSEC, false,\n-\t\t\t\tpriv, reg, &val);\n-\n-\t/* Check if qca8k_read has failed for a different reason\n-\t * before returning -ETIMEDOUT\n-\t */\n-\tif (ret < 0 && ret1 < 0)\n-\t\treturn ret1;\n-\n-\treturn ret;\n+\treturn regmap_read_poll_timeout(priv->regmap, reg, val, !(val & mask), 0,\n+\t\t\t\t       QCA8K_BUSY_WAIT_TIMEOUT * USEC_PER_MSEC);\n }\n \n static int\n@@ -568,7 +555,7 @@ qca8k_mib_init(struct qca8k_priv *priv)\n \tint ret;\n \n \tmutex_lock(&priv->reg_mutex);\n-\tret = qca8k_reg_set(priv, QCA8K_REG_MIB, QCA8K_MIB_FLUSH | QCA8K_MIB_BUSY);\n+\tret = regmap_set_bits(priv->regmap, QCA8K_REG_MIB, QCA8K_MIB_FLUSH | QCA8K_MIB_BUSY);\n \tif (ret)\n \t\tgoto exit;\n \n@@ -576,7 +563,7 @@ qca8k_mib_init(struct qca8k_priv *priv)\n \tif (ret)\n \t\tgoto exit;\n \n-\tret = qca8k_reg_set(priv, QCA8K_REG_MIB, QCA8K_MIB_CPU_KEEP);\n+\tret = regmap_set_bits(priv->regmap, QCA8K_REG_MIB, QCA8K_MIB_CPU_KEEP);\n \tif (ret)\n \t\tgoto exit;\n \n@@ -597,9 +584,9 @@ qca8k_port_set_status(struct qca8k_priv\n \t\tmask |= QCA8K_PORT_STATUS_LINK_AUTO;\n \n \tif (enable)\n-\t\tqca8k_reg_set(priv, QCA8K_REG_PORT_STATUS(port), mask);\n+\t\tregmap_set_bits(priv->regmap, QCA8K_REG_PORT_STATUS(port), mask);\n \telse\n-\t\tqca8k_reg_clear(priv, QCA8K_REG_PORT_STATUS(port), mask);\n+\t\tregmap_clear_bits(priv->regmap, QCA8K_REG_PORT_STATUS(port), mask);\n }\n \n static u32\n@@ -861,8 +848,8 @@ qca8k_setup_mdio_bus(struct qca8k_priv *\n \t\t * a dt-overlay and driver reload changed the configuration\n \t\t */\n \n-\t\treturn qca8k_reg_clear(priv, QCA8K_MDIO_MASTER_CTRL,\n-\t\t\t\t       QCA8K_MDIO_MASTER_EN);\n+\t\treturn regmap_clear_bits(priv->regmap, QCA8K_MDIO_MASTER_CTRL,\n+\t\t\t\t\t QCA8K_MDIO_MASTER_EN);\n \t}\n \n \t/* Check if the devicetree declare the port:phy mapping */\n@@ -1099,16 +1086,16 @@ qca8k_setup(struct dsa_switch *ds)\n \t\treturn ret;\n \n \t/* Make sure MAC06 is disabled */\n-\tret = qca8k_reg_clear(priv, QCA8K_REG_PORT0_PAD_CTRL,\n-\t\t\t      QCA8K_PORT0_PAD_MAC06_EXCHANGE_EN);\n+\tret = regmap_clear_bits(priv->regmap, QCA8K_REG_PORT0_PAD_CTRL,\n+\t\t\t\tQCA8K_PORT0_PAD_MAC06_EXCHANGE_EN);\n \tif (ret) {\n \t\tdev_err(priv->dev, \"failed disabling MAC06 exchange\");\n \t\treturn ret;\n \t}\n \n \t/* Enable CPU Port */\n-\tret = qca8k_reg_set(priv, QCA8K_REG_GLOBAL_FW_CTRL0,\n-\t\t\t    QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN);\n+\tret = regmap_set_bits(priv->regmap, QCA8K_REG_GLOBAL_FW_CTRL0,\n+\t\t\t      QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN);\n \tif (ret) {\n \t\tdev_err(priv->dev, \"failed enabling CPU port\");\n \t\treturn ret;\n@@ -1176,8 +1163,8 @@ qca8k_setup(struct dsa_switch *ds)\n \t\t\t\treturn ret;\n \n \t\t\t/* Enable ARP Auto-learning by default */\n-\t\t\tret = qca8k_reg_set(priv, QCA8K_PORT_LOOKUP_CTRL(i),\n-\t\t\t\t\t    QCA8K_PORT_LOOKUP_LEARN);\n+\t\t\tret = regmap_set_bits(priv->regmap, QCA8K_PORT_LOOKUP_CTRL(i),\n+\t\t\t\t\t      QCA8K_PORT_LOOKUP_LEARN);\n \t\t\tif (ret)\n \t\t\t\treturn ret;\n \n@@ -1745,9 +1732,9 @@ qca8k_port_bridge_join(struct dsa_switch\n \t\t/* Add this port to the portvlan mask of the other ports\n \t\t * in the bridge\n \t\t */\n-\t\tret = qca8k_reg_set(priv,\n-\t\t\t\t    QCA8K_PORT_LOOKUP_CTRL(i),\n-\t\t\t\t    BIT(port));\n+\t\tret = regmap_set_bits(priv->regmap,\n+\t\t\t\t      QCA8K_PORT_LOOKUP_CTRL(i),\n+\t\t\t\t      BIT(port));\n \t\tif (ret)\n \t\t\treturn ret;\n \t\tif (i != port)\n@@ -1777,9 +1764,9 @@ qca8k_port_bridge_leave(struct dsa_switc\n \t\t/* Remove this port to the portvlan mask of the other ports\n \t\t * in the bridge\n \t\t */\n-\t\tqca8k_reg_clear(priv,\n-\t\t\t\tQCA8K_PORT_LOOKUP_CTRL(i),\n-\t\t\t\tBIT(port));\n+\t\tregmap_clear_bits(priv->regmap,\n+\t\t\t\t  QCA8K_PORT_LOOKUP_CTRL(i),\n+\t\t\t\t  BIT(port));\n \t}\n \n \t/* Set the cpu port to be the only one in the portvlan mask of\n"
  },
  {
    "path": "target/linux/generic/backport-5.15/758-net-next-net-dsa-qca8k-add-additional-MIB-counter-and-.patch",
    "content": "From c126f118b330ccf0db0dda4a4bd6c729865a205f Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Mon, 22 Nov 2021 16:23:45 +0100\nSubject: net: dsa: qca8k: add additional MIB counter and make it dynamic\n\nWe are currently missing 2 additionals MIB counter present in QCA833x\nswitch.\nQC832x switch have 39 MIB counter and QCA833X have 41 MIB counter.\nAdd the additional MIB counter and rework the MIB function to print the\ncorrect supported counter from the match_data struct.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nReviewed-by: Vladimir Oltean <olteanv@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/dsa/qca8k.c | 23 ++++++++++++++++++++---\n drivers/net/dsa/qca8k.h |  4 ++++\n 2 files changed, 24 insertions(+), 3 deletions(-)\n\n--- a/drivers/net/dsa/qca8k.c\n+++ b/drivers/net/dsa/qca8k.c\n@@ -70,6 +70,8 @@ static const struct qca8k_mib_desc ar832\n \tMIB_DESC(1, 0x9c, \"TxExcDefer\"),\n \tMIB_DESC(1, 0xa0, \"TxDefer\"),\n \tMIB_DESC(1, 0xa4, \"TxLateCol\"),\n+\tMIB_DESC(1, 0xa8, \"RXUnicast\"),\n+\tMIB_DESC(1, 0xac, \"TXUnicast\"),\n };\n \n /* The 32bit switch registers are accessed indirectly. To achieve this we need\n@@ -1605,12 +1607,16 @@ qca8k_phylink_mac_link_up(struct dsa_swi\n static void\n qca8k_get_strings(struct dsa_switch *ds, int port, u32 stringset, uint8_t *data)\n {\n+\tconst struct qca8k_match_data *match_data;\n+\tstruct qca8k_priv *priv = ds->priv;\n \tint i;\n \n \tif (stringset != ETH_SS_STATS)\n \t\treturn;\n \n-\tfor (i = 0; i < ARRAY_SIZE(ar8327_mib); i++)\n+\tmatch_data = of_device_get_match_data(priv->dev);\n+\n+\tfor (i = 0; i < match_data->mib_count; i++)\n \t\tstrncpy(data + i * ETH_GSTRING_LEN, ar8327_mib[i].name,\n \t\t\tETH_GSTRING_LEN);\n }\n@@ -1620,12 +1626,15 @@ qca8k_get_ethtool_stats(struct dsa_switc\n \t\t\tuint64_t *data)\n {\n \tstruct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;\n+\tconst struct qca8k_match_data *match_data;\n \tconst struct qca8k_mib_desc *mib;\n \tu32 reg, i, val;\n \tu32 hi = 0;\n \tint ret;\n \n-\tfor (i = 0; i < ARRAY_SIZE(ar8327_mib); i++) {\n+\tmatch_data = of_device_get_match_data(priv->dev);\n+\n+\tfor (i = 0; i < match_data->mib_count; i++) {\n \t\tmib = &ar8327_mib[i];\n \t\treg = QCA8K_PORT_MIB_COUNTER(port) + mib->offset;\n \n@@ -1648,10 +1657,15 @@ qca8k_get_ethtool_stats(struct dsa_switc\n static int\n qca8k_get_sset_count(struct dsa_switch *ds, int port, int sset)\n {\n+\tconst struct qca8k_match_data *match_data;\n+\tstruct qca8k_priv *priv = ds->priv;\n+\n \tif (sset != ETH_SS_STATS)\n \t\treturn 0;\n \n-\treturn ARRAY_SIZE(ar8327_mib);\n+\tmatch_data = of_device_get_match_data(priv->dev);\n+\n+\treturn match_data->mib_count;\n }\n \n static int\n@@ -2154,14 +2168,17 @@ static SIMPLE_DEV_PM_OPS(qca8k_pm_ops,\n static const struct qca8k_match_data qca8327 = {\n \t.id = QCA8K_ID_QCA8327,\n \t.reduced_package = true,\n+\t.mib_count = QCA8K_QCA832X_MIB_COUNT,\n };\n \n static const struct qca8k_match_data qca8328 = {\n \t.id = QCA8K_ID_QCA8327,\n+\t.mib_count = QCA8K_QCA832X_MIB_COUNT,\n };\n \n static const struct qca8k_match_data qca833x = {\n \t.id = QCA8K_ID_QCA8337,\n+\t.mib_count = QCA8K_QCA833X_MIB_COUNT,\n };\n \n static const struct of_device_id qca8k_of_match[] = {\n--- a/drivers/net/dsa/qca8k.h\n+++ b/drivers/net/dsa/qca8k.h\n@@ -21,6 +21,9 @@\n #define PHY_ID_QCA8337\t\t\t\t\t0x004dd036\n #define QCA8K_ID_QCA8337\t\t\t\t0x13\n \n+#define QCA8K_QCA832X_MIB_COUNT\t\t\t\t39\n+#define QCA8K_QCA833X_MIB_COUNT\t\t\t\t41\n+\n #define QCA8K_BUSY_WAIT_TIMEOUT\t\t\t\t2000\n \n #define QCA8K_NUM_FDB_RECORDS\t\t\t\t2048\n@@ -279,6 +282,7 @@ struct ar8xxx_port_status {\n struct qca8k_match_data {\n \tu8 id;\n \tbool reduced_package;\n+\tu8 mib_count;\n };\n \n enum {\n"
  },
  {
    "path": "target/linux/generic/backport-5.15/759-net-next-net-dsa-qca8k-add-support-for-port-fast-aging.patch",
    "content": "From 4592538bfb0d5d3c3c8a1d7071724d081412ac91 Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Mon, 22 Nov 2021 16:23:46 +0100\nSubject: net: dsa: qca8k: add support for port fast aging\n\nThe switch supports fast aging by flushing any rule in the ARL\ntable for a specific port.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nReviewed-by: Vladimir Oltean <olteanv@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/dsa/qca8k.c | 11 +++++++++++\n drivers/net/dsa/qca8k.h |  1 +\n 2 files changed, 12 insertions(+)\n\n--- a/drivers/net/dsa/qca8k.c\n+++ b/drivers/net/dsa/qca8k.c\n@@ -1790,6 +1790,16 @@ qca8k_port_bridge_leave(struct dsa_switc\n \t\t  QCA8K_PORT_LOOKUP_MEMBER, BIT(cpu_port));\n }\n \n+static void\n+qca8k_port_fast_age(struct dsa_switch *ds, int port)\n+{\n+\tstruct qca8k_priv *priv = ds->priv;\n+\n+\tmutex_lock(&priv->reg_mutex);\n+\tqca8k_fdb_access(priv, QCA8K_FDB_FLUSH_PORT, port);\n+\tmutex_unlock(&priv->reg_mutex);\n+}\n+\n static int\n qca8k_port_enable(struct dsa_switch *ds, int port,\n \t\t  struct phy_device *phy)\n@@ -1998,6 +2008,7 @@ static const struct dsa_switch_ops qca8k\n \t.port_stp_state_set\t= qca8k_port_stp_state_set,\n \t.port_bridge_join\t= qca8k_port_bridge_join,\n \t.port_bridge_leave\t= qca8k_port_bridge_leave,\n+\t.port_fast_age\t\t= qca8k_port_fast_age,\n \t.port_fdb_add\t\t= qca8k_port_fdb_add,\n \t.port_fdb_del\t\t= qca8k_port_fdb_del,\n \t.port_fdb_dump\t\t= qca8k_port_fdb_dump,\n--- a/drivers/net/dsa/qca8k.h\n+++ b/drivers/net/dsa/qca8k.h\n@@ -262,6 +262,7 @@ enum qca8k_fdb_cmd {\n \tQCA8K_FDB_FLUSH\t= 1,\n \tQCA8K_FDB_LOAD = 2,\n \tQCA8K_FDB_PURGE = 3,\n+\tQCA8K_FDB_FLUSH_PORT = 5,\n \tQCA8K_FDB_NEXT = 6,\n \tQCA8K_FDB_SEARCH = 7,\n };\n"
  },
  {
    "path": "target/linux/generic/backport-5.15/760-net-next-net-dsa-qca8k-add-set_ageing_time-support.patch",
    "content": "From 6a3bdc5209f45d2af83aa92433ab6e5cf2297aa4 Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Mon, 22 Nov 2021 16:23:47 +0100\nSubject: net: dsa: qca8k: add set_ageing_time support\n\nqca8k support setting ageing time in step of 7s. Add support for it and\nset the max value accepted of 7645m.\nDocumentation talks about support for 10000m but that values doesn't\nmake sense as the value doesn't match the max value in the reg.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nReviewed-by: Vladimir Oltean <olteanv@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/dsa/qca8k.c | 25 +++++++++++++++++++++++++\n drivers/net/dsa/qca8k.h |  3 +++\n 2 files changed, 28 insertions(+)\n\n--- a/drivers/net/dsa/qca8k.c\n+++ b/drivers/net/dsa/qca8k.c\n@@ -1261,6 +1261,10 @@ qca8k_setup(struct dsa_switch *ds)\n \t/* We don't have interrupts for link changes, so we need to poll */\n \tds->pcs_poll = true;\n \n+\t/* Set min a max ageing value supported */\n+\tds->ageing_time_min = 7000;\n+\tds->ageing_time_max = 458745000;\n+\n \treturn 0;\n }\n \n@@ -1801,6 +1805,26 @@ qca8k_port_fast_age(struct dsa_switch *d\n }\n \n static int\n+qca8k_set_ageing_time(struct dsa_switch *ds, unsigned int msecs)\n+{\n+\tstruct qca8k_priv *priv = ds->priv;\n+\tunsigned int secs = msecs / 1000;\n+\tu32 val;\n+\n+\t/* AGE_TIME reg is set in 7s step */\n+\tval = secs / 7;\n+\n+\t/* Handle case with 0 as val to NOT disable\n+\t * learning\n+\t */\n+\tif (!val)\n+\t\tval = 1;\n+\n+\treturn regmap_update_bits(priv->regmap, QCA8K_REG_ATU_CTRL, QCA8K_ATU_AGE_TIME_MASK,\n+\t\t\t\t  QCA8K_ATU_AGE_TIME(val));\n+}\n+\n+static int\n qca8k_port_enable(struct dsa_switch *ds, int port,\n \t\t  struct phy_device *phy)\n {\n@@ -1999,6 +2023,7 @@ static const struct dsa_switch_ops qca8k\n \t.get_strings\t\t= qca8k_get_strings,\n \t.get_ethtool_stats\t= qca8k_get_ethtool_stats,\n \t.get_sset_count\t\t= qca8k_get_sset_count,\n+\t.set_ageing_time\t= qca8k_set_ageing_time,\n \t.get_mac_eee\t\t= qca8k_get_mac_eee,\n \t.set_mac_eee\t\t= qca8k_set_mac_eee,\n \t.port_enable\t\t= qca8k_port_enable,\n--- a/drivers/net/dsa/qca8k.h\n+++ b/drivers/net/dsa/qca8k.h\n@@ -175,6 +175,9 @@\n #define   QCA8K_VTU_FUNC1_BUSY\t\t\t\tBIT(31)\n #define   QCA8K_VTU_FUNC1_VID_MASK\t\t\tGENMASK(27, 16)\n #define   QCA8K_VTU_FUNC1_FULL\t\t\t\tBIT(4)\n+#define QCA8K_REG_ATU_CTRL\t\t\t\t0x618\n+#define   QCA8K_ATU_AGE_TIME_MASK\t\t\tGENMASK(15, 0)\n+#define   QCA8K_ATU_AGE_TIME(x)\t\t\t\tFIELD_PREP(QCA8K_ATU_AGE_TIME_MASK, (x))\n #define QCA8K_REG_GLOBAL_FW_CTRL0\t\t\t0x620\n #define   QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN\t\tBIT(10)\n #define QCA8K_REG_GLOBAL_FW_CTRL1\t\t\t0x624\n"
  },
  {
    "path": "target/linux/generic/backport-5.15/761-net-next-net-dsa-qca8k-add-support-for-mdb_add-del.patch",
    "content": "From ba8f870dfa635113ce6e8095a5eb1835ecde2e9e Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Mon, 22 Nov 2021 16:23:48 +0100\nSubject: net: dsa: qca8k: add support for mdb_add/del\n\nAdd support for mdb add/del function. The ARL table is used to insert\nthe rule. The rule will be searched, deleted and reinserted with the\nport mask updated. The function will check if the rule has to be updated\nor insert directly with no deletion of the old rule.\nIf every port is removed from the port mask, the rule is removed.\nThe rule is set STATIC in the ARL table (aka it doesn't age) to not be\nflushed by fast age function.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nReviewed-by: Vladimir Oltean <olteanv@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/dsa/qca8k.c | 99 +++++++++++++++++++++++++++++++++++++++++++++++++\n 1 file changed, 99 insertions(+)\n\n--- a/drivers/net/dsa/qca8k.c\n+++ b/drivers/net/dsa/qca8k.c\n@@ -436,6 +436,81 @@ qca8k_fdb_flush(struct qca8k_priv *priv)\n }\n \n static int\n+qca8k_fdb_search_and_insert(struct qca8k_priv *priv, u8 port_mask,\n+\t\t\t    const u8 *mac, u16 vid)\n+{\n+\tstruct qca8k_fdb fdb = { 0 };\n+\tint ret;\n+\n+\tmutex_lock(&priv->reg_mutex);\n+\n+\tqca8k_fdb_write(priv, vid, 0, mac, 0);\n+\tret = qca8k_fdb_access(priv, QCA8K_FDB_SEARCH, -1);\n+\tif (ret < 0)\n+\t\tgoto exit;\n+\n+\tret = qca8k_fdb_read(priv, &fdb);\n+\tif (ret < 0)\n+\t\tgoto exit;\n+\n+\t/* Rule exist. Delete first */\n+\tif (!fdb.aging) {\n+\t\tret = qca8k_fdb_access(priv, QCA8K_FDB_PURGE, -1);\n+\t\tif (ret)\n+\t\t\tgoto exit;\n+\t}\n+\n+\t/* Add port to fdb portmask */\n+\tfdb.port_mask |= port_mask;\n+\n+\tqca8k_fdb_write(priv, vid, fdb.port_mask, mac, fdb.aging);\n+\tret = qca8k_fdb_access(priv, QCA8K_FDB_LOAD, -1);\n+\n+exit:\n+\tmutex_unlock(&priv->reg_mutex);\n+\treturn ret;\n+}\n+\n+static int\n+qca8k_fdb_search_and_del(struct qca8k_priv *priv, u8 port_mask,\n+\t\t\t const u8 *mac, u16 vid)\n+{\n+\tstruct qca8k_fdb fdb = { 0 };\n+\tint ret;\n+\n+\tmutex_lock(&priv->reg_mutex);\n+\n+\tqca8k_fdb_write(priv, vid, 0, mac, 0);\n+\tret = qca8k_fdb_access(priv, QCA8K_FDB_SEARCH, -1);\n+\tif (ret < 0)\n+\t\tgoto exit;\n+\n+\t/* Rule doesn't exist. Why delete? */\n+\tif (!fdb.aging) {\n+\t\tret = -EINVAL;\n+\t\tgoto exit;\n+\t}\n+\n+\tret = qca8k_fdb_access(priv, QCA8K_FDB_PURGE, -1);\n+\tif (ret)\n+\t\tgoto exit;\n+\n+\t/* Only port in the rule is this port. Don't re insert */\n+\tif (fdb.port_mask == port_mask)\n+\t\tgoto exit;\n+\n+\t/* Remove port from port mask */\n+\tfdb.port_mask &= ~port_mask;\n+\n+\tqca8k_fdb_write(priv, vid, fdb.port_mask, mac, fdb.aging);\n+\tret = qca8k_fdb_access(priv, QCA8K_FDB_LOAD, -1);\n+\n+exit:\n+\tmutex_unlock(&priv->reg_mutex);\n+\treturn ret;\n+}\n+\n+static int\n qca8k_vlan_access(struct qca8k_priv *priv, enum qca8k_vlan_cmd cmd, u16 vid)\n {\n \tu32 reg;\n@@ -1930,6 +2005,28 @@ qca8k_port_fdb_dump(struct dsa_switch *d\n }\n \n static int\n+qca8k_port_mdb_add(struct dsa_switch *ds, int port,\n+\t\t   const struct switchdev_obj_port_mdb *mdb)\n+{\n+\tstruct qca8k_priv *priv = ds->priv;\n+\tconst u8 *addr = mdb->addr;\n+\tu16 vid = mdb->vid;\n+\n+\treturn qca8k_fdb_search_and_insert(priv, BIT(port), addr, vid);\n+}\n+\n+static int\n+qca8k_port_mdb_del(struct dsa_switch *ds, int port,\n+\t\t   const struct switchdev_obj_port_mdb *mdb)\n+{\n+\tstruct qca8k_priv *priv = ds->priv;\n+\tconst u8 *addr = mdb->addr;\n+\tu16 vid = mdb->vid;\n+\n+\treturn qca8k_fdb_search_and_del(priv, BIT(port), addr, vid);\n+}\n+\n+static int\n qca8k_port_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering,\n \t\t\t  struct netlink_ext_ack *extack)\n {\n@@ -2037,6 +2134,8 @@ static const struct dsa_switch_ops qca8k\n \t.port_fdb_add\t\t= qca8k_port_fdb_add,\n \t.port_fdb_del\t\t= qca8k_port_fdb_del,\n \t.port_fdb_dump\t\t= qca8k_port_fdb_dump,\n+\t.port_mdb_add\t\t= qca8k_port_mdb_add,\n+\t.port_mdb_del\t\t= qca8k_port_mdb_del,\n \t.port_vlan_filtering\t= qca8k_port_vlan_filtering,\n \t.port_vlan_add\t\t= qca8k_port_vlan_add,\n \t.port_vlan_del\t\t= qca8k_port_vlan_del,\n"
  },
  {
    "path": "target/linux/generic/backport-5.15/762-net-next-net-dsa-qca8k-add-support-for-mirror-mode.patch",
    "content": "From 2c1bdbc7e7560d7de754cad277d968d56bb1899e Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Tue, 23 Nov 2021 03:59:10 +0100\nSubject: net: dsa: qca8k: add support for mirror mode\n\nThe switch supports mirror mode. Only one port can set as mirror port and\nevery other port can set to both ingress and egress mode. The mirror\nport is disabled and reverted to normal operation once every port is\nremoved from sending packet to it.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/dsa/qca8k.c | 95 +++++++++++++++++++++++++++++++++++++++++++++++++\n drivers/net/dsa/qca8k.h |  4 +++\n 2 files changed, 99 insertions(+)\n\n--- a/drivers/net/dsa/qca8k.c\n+++ b/drivers/net/dsa/qca8k.c\n@@ -2027,6 +2027,99 @@ qca8k_port_mdb_del(struct dsa_switch *ds\n }\n \n static int\n+qca8k_port_mirror_add(struct dsa_switch *ds, int port,\n+\t\t      struct dsa_mall_mirror_tc_entry *mirror,\n+\t\t      bool ingress)\n+{\n+\tstruct qca8k_priv *priv = ds->priv;\n+\tint monitor_port, ret;\n+\tu32 reg, val;\n+\n+\t/* Check for existent entry */\n+\tif ((ingress ? priv->mirror_rx : priv->mirror_tx) & BIT(port))\n+\t\treturn -EEXIST;\n+\n+\tret = regmap_read(priv->regmap, QCA8K_REG_GLOBAL_FW_CTRL0, &val);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\t/* QCA83xx can have only one port set to mirror mode.\n+\t * Check that the correct port is requested and return error otherwise.\n+\t * When no mirror port is set, the values is set to 0xF\n+\t */\n+\tmonitor_port = FIELD_GET(QCA8K_GLOBAL_FW_CTRL0_MIRROR_PORT_NUM, val);\n+\tif (monitor_port != 0xF && monitor_port != mirror->to_local_port)\n+\t\treturn -EEXIST;\n+\n+\t/* Set the monitor port */\n+\tval = FIELD_PREP(QCA8K_GLOBAL_FW_CTRL0_MIRROR_PORT_NUM,\n+\t\t\t mirror->to_local_port);\n+\tret = regmap_update_bits(priv->regmap, QCA8K_REG_GLOBAL_FW_CTRL0,\n+\t\t\t\t QCA8K_GLOBAL_FW_CTRL0_MIRROR_PORT_NUM, val);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tif (ingress) {\n+\t\treg = QCA8K_PORT_LOOKUP_CTRL(port);\n+\t\tval = QCA8K_PORT_LOOKUP_ING_MIRROR_EN;\n+\t} else {\n+\t\treg = QCA8K_REG_PORT_HOL_CTRL1(port);\n+\t\tval = QCA8K_PORT_HOL_CTRL1_EG_MIRROR_EN;\n+\t}\n+\n+\tret = regmap_update_bits(priv->regmap, reg, val, val);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\t/* Track mirror port for tx and rx to decide when the\n+\t * mirror port has to be disabled.\n+\t */\n+\tif (ingress)\n+\t\tpriv->mirror_rx |= BIT(port);\n+\telse\n+\t\tpriv->mirror_tx |= BIT(port);\n+\n+\treturn 0;\n+}\n+\n+static void\n+qca8k_port_mirror_del(struct dsa_switch *ds, int port,\n+\t\t      struct dsa_mall_mirror_tc_entry *mirror)\n+{\n+\tstruct qca8k_priv *priv = ds->priv;\n+\tu32 reg, val;\n+\tint ret;\n+\n+\tif (mirror->ingress) {\n+\t\treg = QCA8K_PORT_LOOKUP_CTRL(port);\n+\t\tval = QCA8K_PORT_LOOKUP_ING_MIRROR_EN;\n+\t} else {\n+\t\treg = QCA8K_REG_PORT_HOL_CTRL1(port);\n+\t\tval = QCA8K_PORT_HOL_CTRL1_EG_MIRROR_EN;\n+\t}\n+\n+\tret = regmap_clear_bits(priv->regmap, reg, val);\n+\tif (ret)\n+\t\tgoto err;\n+\n+\tif (mirror->ingress)\n+\t\tpriv->mirror_rx &= ~BIT(port);\n+\telse\n+\t\tpriv->mirror_tx &= ~BIT(port);\n+\n+\t/* No port set to send packet to mirror port. Disable mirror port */\n+\tif (!priv->mirror_rx && !priv->mirror_tx) {\n+\t\tval = FIELD_PREP(QCA8K_GLOBAL_FW_CTRL0_MIRROR_PORT_NUM, 0xF);\n+\t\tret = regmap_update_bits(priv->regmap, QCA8K_REG_GLOBAL_FW_CTRL0,\n+\t\t\t\t\t QCA8K_GLOBAL_FW_CTRL0_MIRROR_PORT_NUM, val);\n+\t\tif (ret)\n+\t\t\tgoto err;\n+\t}\n+err:\n+\tdev_err(priv->dev, \"Failed to del mirror port from %d\", port);\n+}\n+\n+static int\n qca8k_port_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering,\n \t\t\t  struct netlink_ext_ack *extack)\n {\n@@ -2136,6 +2229,8 @@ static const struct dsa_switch_ops qca8k\n \t.port_fdb_dump\t\t= qca8k_port_fdb_dump,\n \t.port_mdb_add\t\t= qca8k_port_mdb_add,\n \t.port_mdb_del\t\t= qca8k_port_mdb_del,\n+\t.port_mirror_add\t= qca8k_port_mirror_add,\n+\t.port_mirror_del\t= qca8k_port_mirror_del,\n \t.port_vlan_filtering\t= qca8k_port_vlan_filtering,\n \t.port_vlan_add\t\t= qca8k_port_vlan_add,\n \t.port_vlan_del\t\t= qca8k_port_vlan_del,\n--- a/drivers/net/dsa/qca8k.h\n+++ b/drivers/net/dsa/qca8k.h\n@@ -180,6 +180,7 @@\n #define   QCA8K_ATU_AGE_TIME(x)\t\t\t\tFIELD_PREP(QCA8K_ATU_AGE_TIME_MASK, (x))\n #define QCA8K_REG_GLOBAL_FW_CTRL0\t\t\t0x620\n #define   QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN\t\tBIT(10)\n+#define   QCA8K_GLOBAL_FW_CTRL0_MIRROR_PORT_NUM\t\tGENMASK(7, 4)\n #define QCA8K_REG_GLOBAL_FW_CTRL1\t\t\t0x624\n #define   QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_MASK\t\tGENMASK(30, 24)\n #define   QCA8K_GLOBAL_FW_CTRL1_BC_DP_MASK\t\tGENMASK(22, 16)\n@@ -201,6 +202,7 @@\n #define   QCA8K_PORT_LOOKUP_STATE_LEARNING\t\tQCA8K_PORT_LOOKUP_STATE(0x3)\n #define   QCA8K_PORT_LOOKUP_STATE_FORWARD\t\tQCA8K_PORT_LOOKUP_STATE(0x4)\n #define   QCA8K_PORT_LOOKUP_LEARN\t\t\tBIT(20)\n+#define   QCA8K_PORT_LOOKUP_ING_MIRROR_EN\t\tBIT(25)\n \n #define QCA8K_REG_GLOBAL_FC_THRESH\t\t\t0x800\n #define   QCA8K_GLOBAL_FC_GOL_XON_THRES_MASK\t\tGENMASK(24, 16)\n@@ -305,6 +307,8 @@ struct qca8k_ports_config {\n struct qca8k_priv {\n \tu8 switch_id;\n \tu8 switch_revision;\n+\tu8 mirror_rx;\n+\tu8 mirror_tx;\n \tbool legacy_phy_port_mapping;\n \tstruct qca8k_ports_config ports_config;\n \tstruct regmap *regmap;\n"
  },
  {
    "path": "target/linux/generic/backport-5.15/763-net-next-net-dsa-qca8k-add-LAG-support.patch",
    "content": "From def975307c01191b6f0170048c3724b0ed3348af Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Tue, 23 Nov 2021 03:59:11 +0100\nSubject: net: dsa: qca8k: add LAG support\n\nAdd LAG support to this switch. In Documentation this is described as\ntrunk mode. A max of 4 LAGs are supported and each can support up to 4\nport. The current tx mode supported is Hash mode with both L2 and L2+3\nmode.\nWhen no port are present in the trunk, the trunk is disabled in the\nswitch.\nWhen a port is disconnected, the traffic is redirected to the other\navailable port.\nThe hash mode is global and each LAG require to have the same hash mode\nset. To change the hash mode when multiple LAG are configured, it's\nrequired to remove each LAG and set the desired hash mode to the last.\nAn error is printed when it's asked to set a not supported hadh mode.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/dsa/qca8k.c | 177 ++++++++++++++++++++++++++++++++++++++++++++++++\n drivers/net/dsa/qca8k.h |  33 +++++++++\n 2 files changed, 210 insertions(+)\n\n--- a/drivers/net/dsa/qca8k.c\n+++ b/drivers/net/dsa/qca8k.c\n@@ -1340,6 +1340,9 @@ qca8k_setup(struct dsa_switch *ds)\n \tds->ageing_time_min = 7000;\n \tds->ageing_time_max = 458745000;\n \n+\t/* Set max number of LAGs supported */\n+\tds->num_lag_ids = QCA8K_NUM_LAGS;\n+\n \treturn 0;\n }\n \n@@ -2207,6 +2210,178 @@ qca8k_get_tag_protocol(struct dsa_switch\n \treturn DSA_TAG_PROTO_QCA;\n }\n \n+static bool\n+qca8k_lag_can_offload(struct dsa_switch *ds,\n+\t\t      struct net_device *lag,\n+\t\t      struct netdev_lag_upper_info *info)\n+{\n+\tstruct dsa_port *dp;\n+\tint id, members = 0;\n+\n+\tid = dsa_lag_id(ds->dst, lag);\n+\tif (id < 0 || id >= ds->num_lag_ids)\n+\t\treturn false;\n+\n+\tdsa_lag_foreach_port(dp, ds->dst, lag)\n+\t\t/* Includes the port joining the LAG */\n+\t\tmembers++;\n+\n+\tif (members > QCA8K_NUM_PORTS_FOR_LAG)\n+\t\treturn false;\n+\n+\tif (info->tx_type != NETDEV_LAG_TX_TYPE_HASH)\n+\t\treturn false;\n+\n+\tif (info->hash_type != NETDEV_LAG_HASH_L2 ||\n+\t    info->hash_type != NETDEV_LAG_HASH_L23)\n+\t\treturn false;\n+\n+\treturn true;\n+}\n+\n+static int\n+qca8k_lag_setup_hash(struct dsa_switch *ds,\n+\t\t     struct net_device *lag,\n+\t\t     struct netdev_lag_upper_info *info)\n+{\n+\tstruct qca8k_priv *priv = ds->priv;\n+\tbool unique_lag = true;\n+\tint i, id;\n+\tu32 hash;\n+\n+\tid = dsa_lag_id(ds->dst, lag);\n+\n+\tswitch (info->hash_type) {\n+\tcase NETDEV_LAG_HASH_L23:\n+\t\thash |= QCA8K_TRUNK_HASH_SIP_EN;\n+\t\thash |= QCA8K_TRUNK_HASH_DIP_EN;\n+\t\tfallthrough;\n+\tcase NETDEV_LAG_HASH_L2:\n+\t\thash |= QCA8K_TRUNK_HASH_SA_EN;\n+\t\thash |= QCA8K_TRUNK_HASH_DA_EN;\n+\t\tbreak;\n+\tdefault: /* We should NEVER reach this */\n+\t\treturn -EOPNOTSUPP;\n+\t}\n+\n+\t/* Check if we are the unique configured LAG */\n+\tdsa_lags_foreach_id(i, ds->dst)\n+\t\tif (i != id && dsa_lag_dev(ds->dst, i)) {\n+\t\t\tunique_lag = false;\n+\t\t\tbreak;\n+\t\t}\n+\n+\t/* Hash Mode is global. Make sure the same Hash Mode\n+\t * is set to all the 4 possible lag.\n+\t * If we are the unique LAG we can set whatever hash\n+\t * mode we want.\n+\t * To change hash mode it's needed to remove all LAG\n+\t * and change the mode with the latest.\n+\t */\n+\tif (unique_lag) {\n+\t\tpriv->lag_hash_mode = hash;\n+\t} else if (priv->lag_hash_mode != hash) {\n+\t\tnetdev_err(lag, \"Error: Mismateched Hash Mode across different lag is not supported\\n\");\n+\t\treturn -EOPNOTSUPP;\n+\t}\n+\n+\treturn regmap_update_bits(priv->regmap, QCA8K_TRUNK_HASH_EN_CTRL,\n+\t\t\t\t  QCA8K_TRUNK_HASH_MASK, hash);\n+}\n+\n+static int\n+qca8k_lag_refresh_portmap(struct dsa_switch *ds, int port,\n+\t\t\t  struct net_device *lag, bool delete)\n+{\n+\tstruct qca8k_priv *priv = ds->priv;\n+\tint ret, id, i;\n+\tu32 val;\n+\n+\tid = dsa_lag_id(ds->dst, lag);\n+\n+\t/* Read current port member */\n+\tret = regmap_read(priv->regmap, QCA8K_REG_GOL_TRUNK_CTRL0, &val);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\t/* Shift val to the correct trunk */\n+\tval >>= QCA8K_REG_GOL_TRUNK_SHIFT(id);\n+\tval &= QCA8K_REG_GOL_TRUNK_MEMBER_MASK;\n+\tif (delete)\n+\t\tval &= ~BIT(port);\n+\telse\n+\t\tval |= BIT(port);\n+\n+\t/* Update port member. With empty portmap disable trunk */\n+\tret = regmap_update_bits(priv->regmap, QCA8K_REG_GOL_TRUNK_CTRL0,\n+\t\t\t\t QCA8K_REG_GOL_TRUNK_MEMBER(id) |\n+\t\t\t\t QCA8K_REG_GOL_TRUNK_EN(id),\n+\t\t\t\t !val << QCA8K_REG_GOL_TRUNK_SHIFT(id) |\n+\t\t\t\t val << QCA8K_REG_GOL_TRUNK_SHIFT(id));\n+\n+\t/* Search empty member if adding or port on deleting */\n+\tfor (i = 0; i < QCA8K_NUM_PORTS_FOR_LAG; i++) {\n+\t\tret = regmap_read(priv->regmap, QCA8K_REG_GOL_TRUNK_CTRL(id), &val);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\n+\t\tval >>= QCA8K_REG_GOL_TRUNK_ID_MEM_ID_SHIFT(id, i);\n+\t\tval &= QCA8K_REG_GOL_TRUNK_ID_MEM_ID_MASK;\n+\n+\t\tif (delete) {\n+\t\t\t/* If port flagged to be disabled assume this member is\n+\t\t\t * empty\n+\t\t\t */\n+\t\t\tif (val != QCA8K_REG_GOL_TRUNK_ID_MEM_ID_EN_MASK)\n+\t\t\t\tcontinue;\n+\n+\t\t\tval &= QCA8K_REG_GOL_TRUNK_ID_MEM_ID_PORT_MASK;\n+\t\t\tif (val != port)\n+\t\t\t\tcontinue;\n+\t\t} else {\n+\t\t\t/* If port flagged to be enabled assume this member is\n+\t\t\t * already set\n+\t\t\t */\n+\t\t\tif (val == QCA8K_REG_GOL_TRUNK_ID_MEM_ID_EN_MASK)\n+\t\t\t\tcontinue;\n+\t\t}\n+\n+\t\t/* We have found the member to add/remove */\n+\t\tbreak;\n+\t}\n+\n+\t/* Set port in the correct port mask or disable port if in delete mode */\n+\treturn regmap_update_bits(priv->regmap, QCA8K_REG_GOL_TRUNK_CTRL(id),\n+\t\t\t\t  QCA8K_REG_GOL_TRUNK_ID_MEM_ID_EN(id, i) |\n+\t\t\t\t  QCA8K_REG_GOL_TRUNK_ID_MEM_ID_PORT(id, i),\n+\t\t\t\t  !delete << QCA8K_REG_GOL_TRUNK_ID_MEM_ID_SHIFT(id, i) |\n+\t\t\t\t  port << QCA8K_REG_GOL_TRUNK_ID_MEM_ID_SHIFT(id, i));\n+}\n+\n+static int\n+qca8k_port_lag_join(struct dsa_switch *ds, int port,\n+\t\t    struct net_device *lag,\n+\t\t    struct netdev_lag_upper_info *info)\n+{\n+\tint ret;\n+\n+\tif (!qca8k_lag_can_offload(ds, lag, info))\n+\t\treturn -EOPNOTSUPP;\n+\n+\tret = qca8k_lag_setup_hash(ds, lag, info);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\treturn qca8k_lag_refresh_portmap(ds, port, lag, false);\n+}\n+\n+static int\n+qca8k_port_lag_leave(struct dsa_switch *ds, int port,\n+\t\t     struct net_device *lag)\n+{\n+\treturn qca8k_lag_refresh_portmap(ds, port, lag, true);\n+}\n+\n static const struct dsa_switch_ops qca8k_switch_ops = {\n \t.get_tag_protocol\t= qca8k_get_tag_protocol,\n \t.setup\t\t\t= qca8k_setup,\n@@ -2240,6 +2415,8 @@ static const struct dsa_switch_ops qca8k\n \t.phylink_mac_link_down\t= qca8k_phylink_mac_link_down,\n \t.phylink_mac_link_up\t= qca8k_phylink_mac_link_up,\n \t.get_phy_flags\t\t= qca8k_get_phy_flags,\n+\t.port_lag_join\t\t= qca8k_port_lag_join,\n+\t.port_lag_leave\t\t= qca8k_port_lag_leave,\n };\n \n static int qca8k_read_switch_id(struct qca8k_priv *priv)\n--- a/drivers/net/dsa/qca8k.h\n+++ b/drivers/net/dsa/qca8k.h\n@@ -15,6 +15,8 @@\n #define QCA8K_NUM_PORTS\t\t\t\t\t7\n #define QCA8K_NUM_CPU_PORTS\t\t\t\t2\n #define QCA8K_MAX_MTU\t\t\t\t\t9000\n+#define QCA8K_NUM_LAGS\t\t\t\t\t4\n+#define QCA8K_NUM_PORTS_FOR_LAG\t\t\t\t4\n \n #define PHY_ID_QCA8327\t\t\t\t\t0x004dd034\n #define QCA8K_ID_QCA8327\t\t\t\t0x12\n@@ -122,6 +124,14 @@\n #define QCA8K_REG_EEE_CTRL\t\t\t\t0x100\n #define  QCA8K_REG_EEE_CTRL_LPI_EN(_i)\t\t\t((_i + 1) * 2)\n \n+/* TRUNK_HASH_EN registers */\n+#define QCA8K_TRUNK_HASH_EN_CTRL\t\t\t0x270\n+#define   QCA8K_TRUNK_HASH_SIP_EN\t\t\tBIT(3)\n+#define   QCA8K_TRUNK_HASH_DIP_EN\t\t\tBIT(2)\n+#define   QCA8K_TRUNK_HASH_SA_EN\t\t\tBIT(1)\n+#define   QCA8K_TRUNK_HASH_DA_EN\t\t\tBIT(0)\n+#define   QCA8K_TRUNK_HASH_MASK\t\t\t\tGENMASK(3, 0)\n+\n /* ACL registers */\n #define QCA8K_REG_PORT_VLAN_CTRL0(_i)\t\t\t(0x420 + (_i * 8))\n #define   QCA8K_PORT_VLAN_CVID_MASK\t\t\tGENMASK(27, 16)\n@@ -204,6 +214,28 @@\n #define   QCA8K_PORT_LOOKUP_LEARN\t\t\tBIT(20)\n #define   QCA8K_PORT_LOOKUP_ING_MIRROR_EN\t\tBIT(25)\n \n+#define QCA8K_REG_GOL_TRUNK_CTRL0\t\t\t0x700\n+/* 4 max trunk first\n+ * first 6 bit for member bitmap\n+ * 7th bit is to enable trunk port\n+ */\n+#define QCA8K_REG_GOL_TRUNK_SHIFT(_i)\t\t\t((_i) * 8)\n+#define QCA8K_REG_GOL_TRUNK_EN_MASK\t\t\tBIT(7)\n+#define QCA8K_REG_GOL_TRUNK_EN(_i)\t\t\t(QCA8K_REG_GOL_TRUNK_EN_MASK << QCA8K_REG_GOL_TRUNK_SHIFT(_i))\n+#define QCA8K_REG_GOL_TRUNK_MEMBER_MASK\t\t\tGENMASK(6, 0)\n+#define QCA8K_REG_GOL_TRUNK_MEMBER(_i)\t\t\t(QCA8K_REG_GOL_TRUNK_MEMBER_MASK << QCA8K_REG_GOL_TRUNK_SHIFT(_i))\n+/* 0x704 for TRUNK 0-1 --- 0x708 for TRUNK 2-3 */\n+#define QCA8K_REG_GOL_TRUNK_CTRL(_i)\t\t\t(0x704 + (((_i) / 2) * 4))\n+#define QCA8K_REG_GOL_TRUNK_ID_MEM_ID_MASK\t\tGENMASK(3, 0)\n+#define QCA8K_REG_GOL_TRUNK_ID_MEM_ID_EN_MASK\t\tBIT(3)\n+#define QCA8K_REG_GOL_TRUNK_ID_MEM_ID_PORT_MASK\t\tGENMASK(2, 0)\n+#define QCA8K_REG_GOL_TRUNK_ID_SHIFT(_i)\t\t(((_i) / 2) * 16)\n+#define QCA8K_REG_GOL_MEM_ID_SHIFT(_i)\t\t\t((_i) * 4)\n+/* Complex shift: FIRST shift for port THEN shift for trunk */\n+#define QCA8K_REG_GOL_TRUNK_ID_MEM_ID_SHIFT(_i, _j)\t(QCA8K_REG_GOL_MEM_ID_SHIFT(_j) + QCA8K_REG_GOL_TRUNK_ID_SHIFT(_i))\n+#define QCA8K_REG_GOL_TRUNK_ID_MEM_ID_EN(_i, _j)\t(QCA8K_REG_GOL_TRUNK_ID_MEM_ID_EN_MASK << QCA8K_REG_GOL_TRUNK_ID_MEM_ID_SHIFT(_i, _j))\n+#define QCA8K_REG_GOL_TRUNK_ID_MEM_ID_PORT(_i, _j)\t(QCA8K_REG_GOL_TRUNK_ID_MEM_ID_PORT_MASK << QCA8K_REG_GOL_TRUNK_ID_MEM_ID_SHIFT(_i, _j))\n+\n #define QCA8K_REG_GLOBAL_FC_THRESH\t\t\t0x800\n #define   QCA8K_GLOBAL_FC_GOL_XON_THRES_MASK\t\tGENMASK(24, 16)\n #define   QCA8K_GLOBAL_FC_GOL_XON_THRES(x)\t\tFIELD_PREP(QCA8K_GLOBAL_FC_GOL_XON_THRES_MASK, x)\n@@ -309,6 +341,7 @@ struct qca8k_priv {\n \tu8 switch_revision;\n \tu8 mirror_rx;\n \tu8 mirror_tx;\n+\tu8 lag_hash_mode;\n \tbool legacy_phy_port_mapping;\n \tstruct qca8k_ports_config ports_config;\n \tstruct regmap *regmap;\n"
  },
  {
    "path": "target/linux/generic/backport-5.15/764-net-next-net-dsa-qca8k-fix-warning-in-LAG-feature.patch",
    "content": "From 0898ca67b86e14207d4feb3f3fea8b87cec5aab1 Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Tue, 23 Nov 2021 16:44:46 +0100\nSubject: net: dsa: qca8k: fix warning in LAG feature\n\nFix warning reported by bot.\nMake sure hash is init to 0 and fix wrong logic for hash_type in\nqca8k_lag_can_offload.\n\nReported-by: kernel test robot <lkp@intel.com>\nFixes: def975307c01 (\"net: dsa: qca8k: add LAG support\")\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nReviewed-by: Florian Fainelli <f.fainelli@gmail.com>\nLink: https://lore.kernel.org/r/20211123154446.31019-1-ansuelsmth@gmail.com\nSigned-off-by: Jakub Kicinski <kuba@kernel.org>\n---\n drivers/net/dsa/qca8k.c | 4 ++--\n 1 file changed, 2 insertions(+), 2 deletions(-)\n\n--- a/drivers/net/dsa/qca8k.c\n+++ b/drivers/net/dsa/qca8k.c\n@@ -2232,7 +2232,7 @@ qca8k_lag_can_offload(struct dsa_switch\n \tif (info->tx_type != NETDEV_LAG_TX_TYPE_HASH)\n \t\treturn false;\n \n-\tif (info->hash_type != NETDEV_LAG_HASH_L2 ||\n+\tif (info->hash_type != NETDEV_LAG_HASH_L2 &&\n \t    info->hash_type != NETDEV_LAG_HASH_L23)\n \t\treturn false;\n \n@@ -2246,8 +2246,8 @@ qca8k_lag_setup_hash(struct dsa_switch *\n {\n \tstruct qca8k_priv *priv = ds->priv;\n \tbool unique_lag = true;\n+\tu32 hash = 0;\n \tint i, id;\n-\tu32 hash;\n \n \tid = dsa_lag_id(ds->dst, lag);\n \n"
  },
  {
    "path": "target/linux/generic/backport-5.15/765-1-net-next-net-dsa-reorder-PHY-initialization-with-MTU-setup-in.patch",
    "content": "From 904e112ad431492b34f235f59738e8312802bbf9 Mon Sep 17 00:00:00 2001\nFrom: Vladimir Oltean <vladimir.oltean@nxp.com>\nDate: Thu, 6 Jan 2022 01:11:12 +0200\nSubject: [PATCH 1/6] net: dsa: reorder PHY initialization with MTU setup in\n slave.c\n\nIn dsa_slave_create() there are 2 sections that take rtnl_lock():\nMTU change and netdev registration. They are separated by PHY\ninitialization.\n\nThere isn't any strict ordering requirement except for the fact that\nnetdev registration should be last. Therefore, we can perform the MTU\nchange a bit later, after the PHY setup. A future change will then be\nable to merge the two rtnl_lock sections into one.\n\nSigned-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>\nReviewed-by: Florian Fainelli <f.fainelli@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n net/dsa/slave.c | 14 +++++++-------\n 1 file changed, 7 insertions(+), 7 deletions(-)\n\n--- a/net/dsa/slave.c\n+++ b/net/dsa/slave.c\n@@ -1986,13 +1986,6 @@ int dsa_slave_create(struct dsa_port *po\n \tport->slave = slave_dev;\n \tdsa_slave_setup_tagger(slave_dev);\n \n-\trtnl_lock();\n-\tret = dsa_slave_change_mtu(slave_dev, ETH_DATA_LEN);\n-\trtnl_unlock();\n-\tif (ret && ret != -EOPNOTSUPP)\n-\t\tdev_warn(ds->dev, \"nonfatal error %d setting MTU to %d on port %d\\n\",\n-\t\t\t ret, ETH_DATA_LEN, port->index);\n-\n \tnetif_carrier_off(slave_dev);\n \n \tret = dsa_slave_phy_setup(slave_dev);\n@@ -2004,6 +1997,13 @@ int dsa_slave_create(struct dsa_port *po\n \t}\n \n \trtnl_lock();\n+\tret = dsa_slave_change_mtu(slave_dev, ETH_DATA_LEN);\n+\trtnl_unlock();\n+\tif (ret && ret != -EOPNOTSUPP)\n+\t\tdev_warn(ds->dev, \"nonfatal error %d setting MTU to %d on port %d\\n\",\n+\t\t\t ret, ETH_DATA_LEN, port->index);\n+\n+\trtnl_lock();\n \n \tret = register_netdevice(slave_dev);\n \tif (ret) {\n"
  },
  {
    "path": "target/linux/generic/backport-5.15/765-2-net-next-net-dsa-merge-rtnl_lock-sections-in-dsa_slave_create.patch",
    "content": "From e31dbd3b6aba585231cd84a87adeb22e7c6a8c19 Mon Sep 17 00:00:00 2001\nFrom: Vladimir Oltean <vladimir.oltean@nxp.com>\nDate: Thu, 6 Jan 2022 01:11:13 +0200\nSubject: [PATCH 2/6] net: dsa: merge rtnl_lock sections in dsa_slave_create\n\nCurrently dsa_slave_create() has two sequences of rtnl_lock/rtnl_unlock\nin a row. Remove the rtnl_unlock() and rtnl_lock() in between, such that\nthe operation can execute slighly faster.\n\nSigned-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>\nReviewed-by: Florian Fainelli <f.fainelli@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n net/dsa/slave.c | 4 +---\n 1 file changed, 1 insertion(+), 3 deletions(-)\n\n--- a/net/dsa/slave.c\n+++ b/net/dsa/slave.c\n@@ -1997,14 +1997,12 @@ int dsa_slave_create(struct dsa_port *po\n \t}\n \n \trtnl_lock();\n+\n \tret = dsa_slave_change_mtu(slave_dev, ETH_DATA_LEN);\n-\trtnl_unlock();\n \tif (ret && ret != -EOPNOTSUPP)\n \t\tdev_warn(ds->dev, \"nonfatal error %d setting MTU to %d on port %d\\n\",\n \t\t\t ret, ETH_DATA_LEN, port->index);\n \n-\trtnl_lock();\n-\n \tret = register_netdevice(slave_dev);\n \tif (ret) {\n \t\tnetdev_err(master, \"error %d registering interface %s\\n\",\n"
  },
  {
    "path": "target/linux/generic/backport-5.15/765-3-net-next-net-dsa-stop-updating-master-MTU-from-master.c.patch",
    "content": "From a1ff94c2973c43bc1e2677ac63ebb15b1d1ff846 Mon Sep 17 00:00:00 2001\nFrom: Vladimir Oltean <vladimir.oltean@nxp.com>\nDate: Thu, 6 Jan 2022 01:11:14 +0200\nSubject: [PATCH 3/6] net: dsa: stop updating master MTU from master.c\n\nAt present there are two paths for changing the MTU of the DSA master.\n\nThe first is:\n\ndsa_tree_setup\n-> dsa_tree_setup_ports\n   -> dsa_port_setup\n      -> dsa_slave_create\n         -> dsa_slave_change_mtu\n            -> dev_set_mtu(master)\n\nThe second is:\n\ndsa_tree_setup\n-> dsa_tree_setup_master\n   -> dsa_master_setup\n      -> dev_set_mtu(dev)\n\nSo the dev_set_mtu() call from dsa_master_setup() has been effectively\nsuperseded by the dsa_slave_change_mtu(slave_dev, ETH_DATA_LEN) that is\ndone from dsa_slave_create() for each user port. The later function also\nupdates the master MTU according to the largest user port MTU from the\ntree. Therefore, updating the master MTU through a separate code path\nisn't needed.\n\nSigned-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>\nReviewed-by: Florian Fainelli <f.fainelli@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n net/dsa/master.c | 25 +------------------------\n 1 file changed, 1 insertion(+), 24 deletions(-)\n\n--- a/net/dsa/master.c\n+++ b/net/dsa/master.c\n@@ -330,28 +330,13 @@ static const struct attribute_group dsa_\n \t.attrs\t= dsa_slave_attrs,\n };\n \n-static void dsa_master_reset_mtu(struct net_device *dev)\n-{\n-\tint err;\n-\n-\trtnl_lock();\n-\terr = dev_set_mtu(dev, ETH_DATA_LEN);\n-\tif (err)\n-\t\tnetdev_dbg(dev,\n-\t\t\t   \"Unable to reset MTU to exclude DSA overheads\\n\");\n-\trtnl_unlock();\n-}\n-\n static struct lock_class_key dsa_master_addr_list_lock_key;\n \n int dsa_master_setup(struct net_device *dev, struct dsa_port *cpu_dp)\n {\n-\tconst struct dsa_device_ops *tag_ops = cpu_dp->tag_ops;\n \tstruct dsa_switch *ds = cpu_dp->ds;\n \tstruct device_link *consumer_link;\n-\tint mtu, ret;\n-\n-\tmtu = ETH_DATA_LEN + dsa_tag_protocol_overhead(tag_ops);\n+\tint ret;\n \n \t/* The DSA master must use SET_NETDEV_DEV for this to work. */\n \tconsumer_link = device_link_add(ds->dev, dev->dev.parent,\n@@ -361,13 +346,6 @@ int dsa_master_setup(struct net_device *\n \t\t\t   \"Failed to create a device link to DSA switch %s\\n\",\n \t\t\t   dev_name(ds->dev));\n \n-\trtnl_lock();\n-\tret = dev_set_mtu(dev, mtu);\n-\trtnl_unlock();\n-\tif (ret)\n-\t\tnetdev_warn(dev, \"error %d setting MTU to %d to include DSA overhead\\n\",\n-\t\t\t    ret, mtu);\n-\n \t/* If we use a tagging format that doesn't have an ethertype\n \t * field, make sure that all packets from this point on get\n \t * sent to the tag format's receive function.\n@@ -405,7 +383,6 @@ void dsa_master_teardown(struct net_devi\n \tsysfs_remove_group(&dev->dev.kobj, &dsa_group);\n \tdsa_netdev_ops_set(dev, NULL);\n \tdsa_master_ethtool_teardown(dev);\n-\tdsa_master_reset_mtu(dev);\n \tdsa_master_set_promiscuity(dev, -1);\n \n \tdev->dsa_ptr = NULL;\n"
  },
  {
    "path": "target/linux/generic/backport-5.15/765-4-net-next-net-dsa-hold-rtnl_mutex-when-calling-dsa_master_-set.patch",
    "content": "From c146f9bc195a9dc3ad7fd000a14540e7c9df952d Mon Sep 17 00:00:00 2001\nFrom: Vladimir Oltean <vladimir.oltean@nxp.com>\nDate: Thu, 6 Jan 2022 01:11:15 +0200\nSubject: [PATCH 4/6] net: dsa: hold rtnl_mutex when calling\n dsa_master_{setup,teardown}\n\nDSA needs to simulate master tracking events when a binding is first\nwith a DSA master established and torn down, in order to give drivers\nthe simplifying guarantee that ->master_state_change calls are made\nonly when the master's readiness state to pass traffic changes.\nmaster_state_change() provide a operational bool that DSA driver can use\nto understand if DSA master is operational or not.\nTo avoid races, we need to block the reception of\nNETDEV_UP/NETDEV_CHANGE/NETDEV_GOING_DOWN events in the netdev notifier\nchain while we are changing the master's dev->dsa_ptr (this changes what\nnetdev_uses_dsa(dev) reports).\n\nThe dsa_master_setup() and dsa_master_teardown() functions optionally\nrequire the rtnl_mutex to be held, if the tagger needs the master to be\npromiscuous, these functions call dev_set_promiscuity(). Move the\nrtnl_lock() from that function and make it top-level.\n\nSigned-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>\nReviewed-by: Florian Fainelli <f.fainelli@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n net/dsa/dsa2.c   | 8 ++++++++\n net/dsa/master.c | 4 ++--\n 2 files changed, 10 insertions(+), 2 deletions(-)\n\n--- a/net/dsa/dsa2.c\n+++ b/net/dsa/dsa2.c\n@@ -1034,6 +1034,8 @@ static int dsa_tree_setup_master(struct\n \tstruct dsa_port *dp;\n \tint err;\n \n+\trtnl_lock();\n+\n \tlist_for_each_entry(dp, &dst->ports, list) {\n \t\tif (dsa_port_is_cpu(dp)) {\n \t\t\terr = dsa_master_setup(dp->master, dp);\n@@ -1042,6 +1044,8 @@ static int dsa_tree_setup_master(struct\n \t\t}\n \t}\n \n+\trtnl_unlock();\n+\n \treturn 0;\n }\n \n@@ -1049,9 +1053,13 @@ static void dsa_tree_teardown_master(str\n {\n \tstruct dsa_port *dp;\n \n+\trtnl_lock();\n+\n \tlist_for_each_entry(dp, &dst->ports, list)\n \t\tif (dsa_port_is_cpu(dp))\n \t\t\tdsa_master_teardown(dp->master);\n+\n+\trtnl_unlock();\n }\n \n static int dsa_tree_setup_lags(struct dsa_switch_tree *dst)\n--- a/net/dsa/master.c\n+++ b/net/dsa/master.c\n@@ -267,9 +267,9 @@ static void dsa_master_set_promiscuity(s\n \tif (!ops->promisc_on_master)\n \t\treturn;\n \n-\trtnl_lock();\n+\tASSERT_RTNL();\n+\n \tdev_set_promiscuity(dev, inc);\n-\trtnl_unlock();\n }\n \n static ssize_t tagging_show(struct device *d, struct device_attribute *attr,\n"
  },
  {
    "path": "target/linux/generic/backport-5.15/765-5-net-next-net-dsa-first-set-up-shared-ports-then-non-shared-po.patch",
    "content": "From 1e3f407f3cacc5dcfe27166c412ed9bc263d82bf Mon Sep 17 00:00:00 2001\nFrom: Vladimir Oltean <vladimir.oltean@nxp.com>\nDate: Thu, 6 Jan 2022 01:11:16 +0200\nSubject: [PATCH 5/6] net: dsa: first set up shared ports, then non-shared\n ports\n\nAfter commit a57d8c217aad (\"net: dsa: flush switchdev workqueue before\ntearing down CPU/DSA ports\"), the port setup and teardown procedure\nbecame asymmetric.\n\nThe fact of the matter is that user ports need the shared ports to be up\nbefore they can be used for CPU-initiated termination. And since we\nregister net devices for the user ports, those won't be functional until\nwe also call the setup for the shared (CPU, DSA) ports. But we may do\nthat later, depending on the port numbering scheme of the hardware we\nare dealing with.\n\nIt just makes sense that all shared ports are brought up before any user\nport is. I can't pinpoint any issue due to the current behavior, but\nlet's change it nonetheless, for consistency's sake.\n\nSigned-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n net/dsa/dsa2.c | 50 +++++++++++++++++++++++++++++++++++++-------------\n 1 file changed, 37 insertions(+), 13 deletions(-)\n\n--- a/net/dsa/dsa2.c\n+++ b/net/dsa/dsa2.c\n@@ -999,23 +999,28 @@ static void dsa_tree_teardown_switches(s\n \t\tdsa_switch_teardown(dp->ds);\n }\n \n-static int dsa_tree_setup_switches(struct dsa_switch_tree *dst)\n+/* Bring shared ports up first, then non-shared ports */\n+static int dsa_tree_setup_ports(struct dsa_switch_tree *dst)\n {\n \tstruct dsa_port *dp;\n-\tint err;\n+\tint err = 0;\n \n \tlist_for_each_entry(dp, &dst->ports, list) {\n-\t\terr = dsa_switch_setup(dp->ds);\n-\t\tif (err)\n-\t\t\tgoto teardown;\n+\t\tif (dsa_port_is_dsa(dp) || dsa_port_is_cpu(dp)) {\n+\t\t\terr = dsa_port_setup(dp);\n+\t\t\tif (err)\n+\t\t\t\tgoto teardown;\n+\t\t}\n \t}\n \n \tlist_for_each_entry(dp, &dst->ports, list) {\n-\t\terr = dsa_port_setup(dp);\n-\t\tif (err) {\n-\t\t\terr = dsa_port_reinit_as_unused(dp);\n-\t\t\tif (err)\n-\t\t\t\tgoto teardown;\n+\t\tif (dsa_port_is_user(dp) || dsa_port_is_unused(dp)) {\n+\t\t\terr = dsa_port_setup(dp);\n+\t\t\tif (err) {\n+\t\t\t\terr = dsa_port_reinit_as_unused(dp);\n+\t\t\t\tif (err)\n+\t\t\t\t\tgoto teardown;\n+\t\t\t}\n \t\t}\n \t}\n \n@@ -1024,7 +1029,21 @@ static int dsa_tree_setup_switches(struc\n teardown:\n \tdsa_tree_teardown_ports(dst);\n \n-\tdsa_tree_teardown_switches(dst);\n+\treturn err;\n+}\n+\n+static int dsa_tree_setup_switches(struct dsa_switch_tree *dst)\n+{\n+\tstruct dsa_port *dp;\n+\tint err = 0;\n+\n+\tlist_for_each_entry(dp, &dst->ports, list) {\n+\t\terr = dsa_switch_setup(dp->ds);\n+\t\tif (err) {\n+\t\t\tdsa_tree_teardown_switches(dst);\n+\t\t\tbreak;\n+\t\t}\n+\t}\n \n \treturn err;\n }\n@@ -1111,10 +1130,14 @@ static int dsa_tree_setup(struct dsa_swi\n \tif (err)\n \t\tgoto teardown_cpu_ports;\n \n-\terr = dsa_tree_setup_master(dst);\n+\terr = dsa_tree_setup_ports(dst);\n \tif (err)\n \t\tgoto teardown_switches;\n \n+\terr = dsa_tree_setup_master(dst);\n+\tif (err)\n+\t\tgoto teardown_ports;\n+\n \terr = dsa_tree_setup_lags(dst);\n \tif (err)\n \t\tgoto teardown_master;\n@@ -1127,8 +1150,9 @@ static int dsa_tree_setup(struct dsa_swi\n \n teardown_master:\n \tdsa_tree_teardown_master(dst);\n-teardown_switches:\n+teardown_ports:\n \tdsa_tree_teardown_ports(dst);\n+teardown_switches:\n \tdsa_tree_teardown_switches(dst);\n teardown_cpu_ports:\n \tdsa_tree_teardown_cpu_ports(dst);\n"
  },
  {
    "path": "target/linux/generic/backport-5.15/765-6-net-next-net-dsa-setup-master-before-ports.patch",
    "content": "From 11fd667dac315ea3f2469961f6d2869271a46cae Mon Sep 17 00:00:00 2001\nFrom: Vladimir Oltean <vladimir.oltean@nxp.com>\nDate: Thu, 6 Jan 2022 01:11:17 +0200\nSubject: [PATCH 6/6] net: dsa: setup master before ports\n\nIt is said that as soon as a network interface is registered, all its\nresources should have already been prepared, so that it is available for\nsending and receiving traffic. One of the resources needed by a DSA\nslave interface is the master.\n\ndsa_tree_setup\n-> dsa_tree_setup_ports\n   -> dsa_port_setup\n      -> dsa_slave_create\n         -> register_netdevice\n-> dsa_tree_setup_master\n   -> dsa_master_setup\n      -> sets up master->dsa_ptr, which enables reception\n\nTherefore, there is a short period of time after register_netdevice()\nduring which the master isn't prepared to pass traffic to the DSA layer\n(master->dsa_ptr is checked by eth_type_trans). Same thing during\nunregistration, there is a time frame in which packets might be missed.\n\nNote that this change opens us to another race: dsa_master_find_slave()\nwill get invoked potentially earlier than the slave creation, and later\nthan the slave deletion. Since dp->slave starts off as a NULL pointer,\nthe earlier calls aren't a problem, but the later calls are. To avoid\nuse-after-free, we should zeroize dp->slave before calling\ndsa_slave_destroy().\n\nIn practice I cannot really test real life improvements brought by this\nchange, since in my systems, netdevice creation races with PHY autoneg\nwhich takes a few seconds to complete, and that masks quite a few races.\nEffects might be noticeable in a setup with fixed links all the way to\nan external system.\n\nSigned-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n net/dsa/dsa2.c | 23 +++++++++++++----------\n 1 file changed, 13 insertions(+), 10 deletions(-)\n\n--- a/net/dsa/dsa2.c\n+++ b/net/dsa/dsa2.c\n@@ -545,6 +545,7 @@ static void dsa_port_teardown(struct dsa\n \tstruct devlink_port *dlp = &dp->devlink_port;\n \tstruct dsa_switch *ds = dp->ds;\n \tstruct dsa_mac_addr *a, *tmp;\n+\tstruct net_device *slave;\n \n \tif (!dp->setup)\n \t\treturn;\n@@ -566,9 +567,11 @@ static void dsa_port_teardown(struct dsa\n \t\tdsa_port_link_unregister_of(dp);\n \t\tbreak;\n \tcase DSA_PORT_TYPE_USER:\n-\t\tif (dp->slave) {\n-\t\t\tdsa_slave_destroy(dp->slave);\n+\t\tslave = dp->slave;\n+\n+\t\tif (slave) {\n \t\t\tdp->slave = NULL;\n+\t\t\tdsa_slave_destroy(slave);\n \t\t}\n \t\tbreak;\n \t}\n@@ -1130,17 +1133,17 @@ static int dsa_tree_setup(struct dsa_swi\n \tif (err)\n \t\tgoto teardown_cpu_ports;\n \n-\terr = dsa_tree_setup_ports(dst);\n+\terr = dsa_tree_setup_master(dst);\n \tif (err)\n \t\tgoto teardown_switches;\n \n-\terr = dsa_tree_setup_master(dst);\n+\terr = dsa_tree_setup_ports(dst);\n \tif (err)\n-\t\tgoto teardown_ports;\n+\t\tgoto teardown_master;\n \n \terr = dsa_tree_setup_lags(dst);\n \tif (err)\n-\t\tgoto teardown_master;\n+\t\tgoto teardown_ports;\n \n \tdst->setup = true;\n \n@@ -1148,10 +1151,10 @@ static int dsa_tree_setup(struct dsa_swi\n \n \treturn 0;\n \n-teardown_master:\n-\tdsa_tree_teardown_master(dst);\n teardown_ports:\n \tdsa_tree_teardown_ports(dst);\n+teardown_master:\n+\tdsa_tree_teardown_master(dst);\n teardown_switches:\n \tdsa_tree_teardown_switches(dst);\n teardown_cpu_ports:\n@@ -1169,10 +1172,10 @@ static void dsa_tree_teardown(struct dsa\n \n \tdsa_tree_teardown_lags(dst);\n \n-\tdsa_tree_teardown_master(dst);\n-\n \tdsa_tree_teardown_ports(dst);\n \n+\tdsa_tree_teardown_master(dst);\n+\n \tdsa_tree_teardown_switches(dst);\n \n \tdsa_tree_teardown_cpu_ports(dst);\n"
  },
  {
    "path": "target/linux/generic/backport-5.15/766-01-net-dsa-provide-switch-operations-for-tracking-the-m.patch",
    "content": "From 295ab96f478d0fa56393e85406f19a867e26ce22 Mon Sep 17 00:00:00 2001\nFrom: Vladimir Oltean <vladimir.oltean@nxp.com>\nDate: Wed, 2 Feb 2022 01:03:20 +0100\nSubject: [PATCH 01/16] net: dsa: provide switch operations for tracking the\n master state\n\nCertain drivers may need to send management traffic to the switch for\nthings like register access, FDB dump, etc, to accelerate what their\nslow bus (SPI, I2C, MDIO) can already do.\n\nEthernet is faster (especially in bulk transactions) but is also more\nunreliable, since the user may decide to bring the DSA master down (or\nnot bring it up), therefore severing the link between the host and the\nattached switch.\n\nDrivers needing Ethernet-based register access already should have\nfallback logic to the slow bus if the Ethernet method fails, but that\nfallback may be based on a timeout, and the I/O to the switch may slow\ndown to a halt if the master is down, because every Ethernet packet will\nhave to time out. The driver also doesn't have the option to turn off\nEthernet-based I/O momentarily, because it wouldn't know when to turn it\nback on.\n\nWhich is where this change comes in. By tracking NETDEV_CHANGE,\nNETDEV_UP and NETDEV_GOING_DOWN events on the DSA master, we should know\nthe exact interval of time during which this interface is reliably\navailable for traffic. Provide this information to switches so they can\nuse it as they wish.\n\nAn helper is added dsa_port_master_is_operational() to check if a master\nport is operational.\n\nSigned-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nReviewed-by: Florian Fainelli <f.fainelli@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n include/net/dsa.h  | 17 +++++++++++++++++\n net/dsa/dsa2.c     | 46 ++++++++++++++++++++++++++++++++++++++++++++++\n net/dsa/dsa_priv.h | 13 +++++++++++++\n net/dsa/slave.c    | 32 ++++++++++++++++++++++++++++++++\n net/dsa/switch.c   | 15 +++++++++++++++\n 5 files changed, 123 insertions(+)\n\n--- a/include/net/dsa.h\n+++ b/include/net/dsa.h\n@@ -291,6 +291,10 @@ struct dsa_port {\n \tstruct list_head\tmdbs;\n \n \tbool setup;\n+\t/* Master state bits, valid only on CPU ports */\n+\tu8\t\t\tmaster_admin_up:1;\n+\tu8\t\t\tmaster_oper_up:1;\n+\n };\n \n /* TODO: ideally DSA ports would have a single dp->link_dp member,\n@@ -456,6 +460,12 @@ static inline bool dsa_port_is_unused(st\n \treturn dp->type == DSA_PORT_TYPE_UNUSED;\n }\n \n+static inline bool dsa_port_master_is_operational(struct dsa_port *dp)\n+{\n+\treturn dsa_port_is_cpu(dp) && dp->master_admin_up &&\n+\t       dp->master_oper_up;\n+}\n+\n static inline bool dsa_is_unused_port(struct dsa_switch *ds, int p)\n {\n \treturn dsa_to_port(ds, p)->type == DSA_PORT_TYPE_UNUSED;\n@@ -916,6 +926,13 @@ struct dsa_switch_ops {\n \tint\t(*tag_8021q_vlan_add)(struct dsa_switch *ds, int port, u16 vid,\n \t\t\t\t      u16 flags);\n \tint\t(*tag_8021q_vlan_del)(struct dsa_switch *ds, int port, u16 vid);\n+\n+\t/*\n+\t * DSA master tracking operations\n+\t */\n+\tvoid\t(*master_state_change)(struct dsa_switch *ds,\n+\t\t\t\t       const struct net_device *master,\n+\t\t\t\t       bool operational);\n };\n \n #define DSA_DEVLINK_PARAM_DRIVER(_id, _name, _type, _cmodes)\t\t\\\n--- a/net/dsa/dsa2.c\n+++ b/net/dsa/dsa2.c\n@@ -1275,6 +1275,52 @@ out_unlock:\n \treturn err;\n }\n \n+static void dsa_tree_master_state_change(struct dsa_switch_tree *dst,\n+\t\t\t\t\t struct net_device *master)\n+{\n+\tstruct dsa_notifier_master_state_info info;\n+\tstruct dsa_port *cpu_dp = master->dsa_ptr;\n+\n+\tinfo.master = master;\n+\tinfo.operational = dsa_port_master_is_operational(cpu_dp);\n+\n+\tdsa_tree_notify(dst, DSA_NOTIFIER_MASTER_STATE_CHANGE, &info);\n+}\n+\n+void dsa_tree_master_admin_state_change(struct dsa_switch_tree *dst,\n+\t\t\t\t\tstruct net_device *master,\n+\t\t\t\t\tbool up)\n+{\n+\tstruct dsa_port *cpu_dp = master->dsa_ptr;\n+\tbool notify = false;\n+\n+\tif ((dsa_port_master_is_operational(cpu_dp)) !=\n+\t    (up && cpu_dp->master_oper_up))\n+\t\tnotify = true;\n+\n+\tcpu_dp->master_admin_up = up;\n+\n+\tif (notify)\n+\t\tdsa_tree_master_state_change(dst, master);\n+}\n+\n+void dsa_tree_master_oper_state_change(struct dsa_switch_tree *dst,\n+\t\t\t\t       struct net_device *master,\n+\t\t\t\t       bool up)\n+{\n+\tstruct dsa_port *cpu_dp = master->dsa_ptr;\n+\tbool notify = false;\n+\n+\tif ((dsa_port_master_is_operational(cpu_dp)) !=\n+\t    (cpu_dp->master_admin_up && up))\n+\t\tnotify = true;\n+\n+\tcpu_dp->master_oper_up = up;\n+\n+\tif (notify)\n+\t\tdsa_tree_master_state_change(dst, master);\n+}\n+\n static struct dsa_port *dsa_port_touch(struct dsa_switch *ds, int index)\n {\n \tstruct dsa_switch_tree *dst = ds->dst;\n--- a/net/dsa/dsa_priv.h\n+++ b/net/dsa/dsa_priv.h\n@@ -45,6 +45,7 @@ enum {\n \tDSA_NOTIFIER_MRP_DEL_RING_ROLE,\n \tDSA_NOTIFIER_TAG_8021Q_VLAN_ADD,\n \tDSA_NOTIFIER_TAG_8021Q_VLAN_DEL,\n+\tDSA_NOTIFIER_MASTER_STATE_CHANGE,\n };\n \n /* DSA_NOTIFIER_AGEING_TIME */\n@@ -127,6 +128,12 @@ struct dsa_notifier_tag_8021q_vlan_info\n \tu16 vid;\n };\n \n+/* DSA_NOTIFIER_MASTER_STATE_CHANGE */\n+struct dsa_notifier_master_state_info {\n+\tconst struct net_device *master;\n+\tbool operational;\n+};\n+\n struct dsa_switchdev_event_work {\n \tstruct dsa_switch *ds;\n \tint port;\n@@ -548,6 +555,12 @@ int dsa_tree_change_tag_proto(struct dsa\n \t\t\t      struct net_device *master,\n \t\t\t      const struct dsa_device_ops *tag_ops,\n \t\t\t      const struct dsa_device_ops *old_tag_ops);\n+void dsa_tree_master_admin_state_change(struct dsa_switch_tree *dst,\n+\t\t\t\t\tstruct net_device *master,\n+\t\t\t\t\tbool up);\n+void dsa_tree_master_oper_state_change(struct dsa_switch_tree *dst,\n+\t\t\t\t       struct net_device *master,\n+\t\t\t\t       bool up);\n int dsa_bridge_num_get(const struct net_device *bridge_dev, int max);\n void dsa_bridge_num_put(const struct net_device *bridge_dev, int bridge_num);\n \n--- a/net/dsa/slave.c\n+++ b/net/dsa/slave.c\n@@ -2320,6 +2320,36 @@ static int dsa_slave_netdevice_event(str\n \t\terr = dsa_port_lag_change(dp, info->lower_state_info);\n \t\treturn notifier_from_errno(err);\n \t}\n+\tcase NETDEV_CHANGE:\n+\tcase NETDEV_UP: {\n+\t\t/* Track state of master port.\n+\t\t * DSA driver may require the master port (and indirectly\n+\t\t * the tagger) to be available for some special operation.\n+\t\t */\n+\t\tif (netdev_uses_dsa(dev)) {\n+\t\t\tstruct dsa_port *cpu_dp = dev->dsa_ptr;\n+\t\t\tstruct dsa_switch_tree *dst = cpu_dp->ds->dst;\n+\n+\t\t\t/* Track when the master port is UP */\n+\t\t\tdsa_tree_master_oper_state_change(dst, dev,\n+\t\t\t\t\t\t\t  netif_oper_up(dev));\n+\n+\t\t\t/* Track when the master port is ready and can accept\n+\t\t\t * packet.\n+\t\t\t * NETDEV_UP event is not enough to flag a port as ready.\n+\t\t\t * We also have to wait for linkwatch_do_dev to dev_activate\n+\t\t\t * and emit a NETDEV_CHANGE event.\n+\t\t\t * We check if a master port is ready by checking if the dev\n+\t\t\t * have a qdisc assigned and is not noop.\n+\t\t\t */\n+\t\t\tdsa_tree_master_admin_state_change(dst, dev,\n+\t\t\t\t\t\t\t   !qdisc_tx_is_noop(dev));\n+\n+\t\t\treturn NOTIFY_OK;\n+\t\t}\n+\n+\t\treturn NOTIFY_DONE;\n+\t}\n \tcase NETDEV_GOING_DOWN: {\n \t\tstruct dsa_port *dp, *cpu_dp;\n \t\tstruct dsa_switch_tree *dst;\n@@ -2331,6 +2361,8 @@ static int dsa_slave_netdevice_event(str\n \t\tcpu_dp = dev->dsa_ptr;\n \t\tdst = cpu_dp->ds->dst;\n \n+\t\tdsa_tree_master_admin_state_change(dst, dev, false);\n+\n \t\tlist_for_each_entry(dp, &dst->ports, list) {\n \t\t\tif (!dsa_is_user_port(dp->ds, dp->index))\n \t\t\t\tcontinue;\n--- a/net/dsa/switch.c\n+++ b/net/dsa/switch.c\n@@ -722,6 +722,18 @@ dsa_switch_mrp_del_ring_role(struct dsa_\n \treturn 0;\n }\n \n+static int\n+dsa_switch_master_state_change(struct dsa_switch *ds,\n+\t\t\t       struct dsa_notifier_master_state_info *info)\n+{\n+\tif (!ds->ops->master_state_change)\n+\t\treturn 0;\n+\n+\tds->ops->master_state_change(ds, info->master, info->operational);\n+\n+\treturn 0;\n+}\n+\n static int dsa_switch_event(struct notifier_block *nb,\n \t\t\t    unsigned long event, void *info)\n {\n@@ -813,6 +825,9 @@ static int dsa_switch_event(struct notif\n \tcase DSA_NOTIFIER_TAG_8021Q_VLAN_DEL:\n \t\terr = dsa_switch_tag_8021q_vlan_del(ds, info);\n \t\tbreak;\n+\tcase DSA_NOTIFIER_MASTER_STATE_CHANGE:\n+\t\terr = dsa_switch_master_state_change(ds, info);\n+\t\tbreak;\n \tdefault:\n \t\terr = -EOPNOTSUPP;\n \t\tbreak;\n"
  },
  {
    "path": "target/linux/generic/backport-5.15/766-02-net-dsa-replay-master-state-events-in-dsa_tree_-setu.patch",
    "content": "From e83d56537859849f2223b90749e554831b1f3c27 Mon Sep 17 00:00:00 2001\nFrom: Vladimir Oltean <vladimir.oltean@nxp.com>\nDate: Wed, 2 Feb 2022 01:03:21 +0100\nSubject: [PATCH 02/16] net: dsa: replay master state events in\n dsa_tree_{setup,teardown}_master\n\nIn order for switch driver to be able to make simple and reliable use of\nthe master tracking operations, they must also be notified of the\ninitial state of the DSA master, not just of the changes. This is\nbecause they might enable certain features only during the time when\nthey know that the DSA master is up and running.\n\nTherefore, this change explicitly checks the state of the DSA master\nunder the same rtnl_mutex as we were holding during the\ndsa_master_setup() and dsa_master_teardown() call. The idea being that\nif the DSA master became operational in between the moment in which it\nbecame a DSA master (dsa_master_setup set dev->dsa_ptr) and the moment\nwhen we checked for the master being up, there is a chance that we\nwould emit a ->master_state_change() call with no actual state change.\nWe need to avoid that by serializing the concurrent netdevice event with\nus. If the netdevice event started before, we force it to finish before\nwe begin, because we take rtnl_lock before making netdev_uses_dsa()\nreturn true. So we also handle that early event and do nothing on it.\nSimilarly, if the dev_open() attempt is concurrent with us, it will\nattempt to take the rtnl_mutex, but we're holding it. We'll see that\nthe master flag IFF_UP isn't set, then when we release the rtnl_mutex\nwe'll process the NETDEV_UP notifier.\n\nSigned-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nReviewed-by: Florian Fainelli <f.fainelli@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n net/dsa/dsa2.c | 28 ++++++++++++++++++++++++----\n 1 file changed, 24 insertions(+), 4 deletions(-)\n\n--- a/net/dsa/dsa2.c\n+++ b/net/dsa/dsa2.c\n@@ -15,6 +15,7 @@\n #include <linux/of.h>\n #include <linux/of_net.h>\n #include <net/devlink.h>\n+#include <net/sch_generic.h>\n \n #include \"dsa_priv.h\"\n \n@@ -1060,9 +1061,18 @@ static int dsa_tree_setup_master(struct\n \n \tlist_for_each_entry(dp, &dst->ports, list) {\n \t\tif (dsa_port_is_cpu(dp)) {\n-\t\t\terr = dsa_master_setup(dp->master, dp);\n+\t\t\tstruct net_device *master = dp->master;\n+\t\t\tbool admin_up = (master->flags & IFF_UP) &&\n+\t\t\t\t\t!qdisc_tx_is_noop(master);\n+\n+\t\t\terr = dsa_master_setup(master, dp);\n \t\t\tif (err)\n \t\t\t\treturn err;\n+\n+\t\t\t/* Replay master state event */\n+\t\t\tdsa_tree_master_admin_state_change(dst, master, admin_up);\n+\t\t\tdsa_tree_master_oper_state_change(dst, master,\n+\t\t\t\t\t\t\t  netif_oper_up(master));\n \t\t}\n \t}\n \n@@ -1077,9 +1087,19 @@ static void dsa_tree_teardown_master(str\n \n \trtnl_lock();\n \n-\tlist_for_each_entry(dp, &dst->ports, list)\n-\t\tif (dsa_port_is_cpu(dp))\n-\t\t\tdsa_master_teardown(dp->master);\n+\tlist_for_each_entry(dp, &dst->ports, list) {\n+\t\tif (dsa_port_is_cpu(dp)) {\n+\t\t\tstruct net_device *master = dp->master;\n+\n+\t\t\t/* Synthesizing an \"admin down\" state is sufficient for\n+\t\t\t * the switches to get a notification if the master is\n+\t\t\t * currently up and running.\n+\t\t\t */\n+\t\t\tdsa_tree_master_admin_state_change(dst, master, false);\n+\n+\t\t\tdsa_master_teardown(master);\n+\t\t}\n+\t}\n \n \trtnl_unlock();\n }\n"
  },
  {
    "path": "target/linux/generic/backport-5.15/766-03-net-dsa-tag_qca-convert-to-FIELD-macro.patch",
    "content": "From 6b0458299297ca4ab6fb295800e29a4e501d50c1 Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Wed, 2 Feb 2022 01:03:22 +0100\nSubject: [PATCH 03/16] net: dsa: tag_qca: convert to FIELD macro\n\nConvert driver to FIELD macro to drop redundant define.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nReviewed-by: Vladimir Oltean <olteanv@gmail.com>\nReviewed-by: Florian Fainelli <f.fainelli@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n net/dsa/tag_qca.c | 34 +++++++++++++++-------------------\n 1 file changed, 15 insertions(+), 19 deletions(-)\n\n--- a/net/dsa/tag_qca.c\n+++ b/net/dsa/tag_qca.c\n@@ -4,29 +4,24 @@\n  */\n \n #include <linux/etherdevice.h>\n+#include <linux/bitfield.h>\n \n #include \"dsa_priv.h\"\n \n #define QCA_HDR_LEN\t2\n #define QCA_HDR_VERSION\t0x2\n \n-#define QCA_HDR_RECV_VERSION_MASK\tGENMASK(15, 14)\n-#define QCA_HDR_RECV_VERSION_S\t\t14\n-#define QCA_HDR_RECV_PRIORITY_MASK\tGENMASK(13, 11)\n-#define QCA_HDR_RECV_PRIORITY_S\t\t11\n-#define QCA_HDR_RECV_TYPE_MASK\t\tGENMASK(10, 6)\n-#define QCA_HDR_RECV_TYPE_S\t\t6\n+#define QCA_HDR_RECV_VERSION\t\tGENMASK(15, 14)\n+#define QCA_HDR_RECV_PRIORITY\t\tGENMASK(13, 11)\n+#define QCA_HDR_RECV_TYPE\t\tGENMASK(10, 6)\n #define QCA_HDR_RECV_FRAME_IS_TAGGED\tBIT(3)\n-#define QCA_HDR_RECV_SOURCE_PORT_MASK\tGENMASK(2, 0)\n+#define QCA_HDR_RECV_SOURCE_PORT\tGENMASK(2, 0)\n \n-#define QCA_HDR_XMIT_VERSION_MASK\tGENMASK(15, 14)\n-#define QCA_HDR_XMIT_VERSION_S\t\t14\n-#define QCA_HDR_XMIT_PRIORITY_MASK\tGENMASK(13, 11)\n-#define QCA_HDR_XMIT_PRIORITY_S\t\t11\n-#define QCA_HDR_XMIT_CONTROL_MASK\tGENMASK(10, 8)\n-#define QCA_HDR_XMIT_CONTROL_S\t\t8\n+#define QCA_HDR_XMIT_VERSION\t\tGENMASK(15, 14)\n+#define QCA_HDR_XMIT_PRIORITY\t\tGENMASK(13, 11)\n+#define QCA_HDR_XMIT_CONTROL\t\tGENMASK(10, 8)\n #define QCA_HDR_XMIT_FROM_CPU\t\tBIT(7)\n-#define QCA_HDR_XMIT_DP_BIT_MASK\tGENMASK(6, 0)\n+#define QCA_HDR_XMIT_DP_BIT\t\tGENMASK(6, 0)\n \n static struct sk_buff *qca_tag_xmit(struct sk_buff *skb, struct net_device *dev)\n {\n@@ -40,8 +35,9 @@ static struct sk_buff *qca_tag_xmit(stru\n \tphdr = dsa_etype_header_pos_tx(skb);\n \n \t/* Set the version field, and set destination port information */\n-\thdr = QCA_HDR_VERSION << QCA_HDR_XMIT_VERSION_S |\n-\t\tQCA_HDR_XMIT_FROM_CPU | BIT(dp->index);\n+\thdr = FIELD_PREP(QCA_HDR_XMIT_VERSION, QCA_HDR_VERSION);\n+\thdr |= QCA_HDR_XMIT_FROM_CPU;\n+\thdr |= FIELD_PREP(QCA_HDR_XMIT_DP_BIT, BIT(dp->index));\n \n \t*phdr = htons(hdr);\n \n@@ -62,7 +58,7 @@ static struct sk_buff *qca_tag_rcv(struc\n \thdr = ntohs(*phdr);\n \n \t/* Make sure the version is correct */\n-\tver = (hdr & QCA_HDR_RECV_VERSION_MASK) >> QCA_HDR_RECV_VERSION_S;\n+\tver = FIELD_GET(QCA_HDR_RECV_VERSION, hdr);\n \tif (unlikely(ver != QCA_HDR_VERSION))\n \t\treturn NULL;\n \n@@ -71,7 +67,7 @@ static struct sk_buff *qca_tag_rcv(struc\n \tdsa_strip_etype_header(skb, QCA_HDR_LEN);\n \n \t/* Get source port information */\n-\tport = (hdr & QCA_HDR_RECV_SOURCE_PORT_MASK);\n+\tport = FIELD_GET(QCA_HDR_RECV_SOURCE_PORT, hdr);\n \n \tskb->dev = dsa_master_find_slave(dev, 0, port);\n \tif (!skb->dev)\n"
  },
  {
    "path": "target/linux/generic/backport-5.15/766-04-net-dsa-tag_qca-move-define-to-include-linux-dsa.patch",
    "content": "From 3ec762fb13c7e7273800b94c80db1c2cc37590d1 Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Wed, 2 Feb 2022 01:03:23 +0100\nSubject: [PATCH 04/16] net: dsa: tag_qca: move define to include linux/dsa\n\nMove tag_qca define to include dir linux/dsa as the qca8k require access\nto the tagger define to support in-band mdio read/write using ethernet\npacket.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nReviewed-by: Vladimir Oltean <olteanv@gmail.com>\nReviewed-by: Florian Fainelli <f.fainelli@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n include/linux/dsa/tag_qca.h | 21 +++++++++++++++++++++\n net/dsa/tag_qca.c           | 16 +---------------\n 2 files changed, 22 insertions(+), 15 deletions(-)\n create mode 100644 include/linux/dsa/tag_qca.h\n\n--- /dev/null\n+++ b/include/linux/dsa/tag_qca.h\n@@ -0,0 +1,21 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+\n+#ifndef __TAG_QCA_H\n+#define __TAG_QCA_H\n+\n+#define QCA_HDR_LEN\t2\n+#define QCA_HDR_VERSION\t0x2\n+\n+#define QCA_HDR_RECV_VERSION\t\tGENMASK(15, 14)\n+#define QCA_HDR_RECV_PRIORITY\t\tGENMASK(13, 11)\n+#define QCA_HDR_RECV_TYPE\t\tGENMASK(10, 6)\n+#define QCA_HDR_RECV_FRAME_IS_TAGGED\tBIT(3)\n+#define QCA_HDR_RECV_SOURCE_PORT\tGENMASK(2, 0)\n+\n+#define QCA_HDR_XMIT_VERSION\t\tGENMASK(15, 14)\n+#define QCA_HDR_XMIT_PRIORITY\t\tGENMASK(13, 11)\n+#define QCA_HDR_XMIT_CONTROL\t\tGENMASK(10, 8)\n+#define QCA_HDR_XMIT_FROM_CPU\t\tBIT(7)\n+#define QCA_HDR_XMIT_DP_BIT\t\tGENMASK(6, 0)\n+\n+#endif /* __TAG_QCA_H */\n--- a/net/dsa/tag_qca.c\n+++ b/net/dsa/tag_qca.c\n@@ -5,24 +5,10 @@\n \n #include <linux/etherdevice.h>\n #include <linux/bitfield.h>\n+#include <linux/dsa/tag_qca.h>\n \n #include \"dsa_priv.h\"\n \n-#define QCA_HDR_LEN\t2\n-#define QCA_HDR_VERSION\t0x2\n-\n-#define QCA_HDR_RECV_VERSION\t\tGENMASK(15, 14)\n-#define QCA_HDR_RECV_PRIORITY\t\tGENMASK(13, 11)\n-#define QCA_HDR_RECV_TYPE\t\tGENMASK(10, 6)\n-#define QCA_HDR_RECV_FRAME_IS_TAGGED\tBIT(3)\n-#define QCA_HDR_RECV_SOURCE_PORT\tGENMASK(2, 0)\n-\n-#define QCA_HDR_XMIT_VERSION\t\tGENMASK(15, 14)\n-#define QCA_HDR_XMIT_PRIORITY\t\tGENMASK(13, 11)\n-#define QCA_HDR_XMIT_CONTROL\t\tGENMASK(10, 8)\n-#define QCA_HDR_XMIT_FROM_CPU\t\tBIT(7)\n-#define QCA_HDR_XMIT_DP_BIT\t\tGENMASK(6, 0)\n-\n static struct sk_buff *qca_tag_xmit(struct sk_buff *skb, struct net_device *dev)\n {\n \tstruct dsa_port *dp = dsa_slave_to_port(dev);\n"
  },
  {
    "path": "target/linux/generic/backport-5.15/766-05-net-dsa-tag_qca-enable-promisc_on_master-flag.patch",
    "content": "From 101c04c3463b87061e6a3d4f72c1bc57670685a6 Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Wed, 2 Feb 2022 01:03:24 +0100\nSubject: [PATCH 05/16] net: dsa: tag_qca: enable promisc_on_master flag\n\nEthernet MDIO packets are non-standard and DSA master expects the first\n6 octets to be the MAC DA. To address these kind of packet, enable\npromisc_on_master flag for the tagger.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nReviewed-by: Vladimir Oltean <olteanv@gmail.com>\nReviewed-by: Florian Fainelli <f.fainelli@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n net/dsa/tag_qca.c | 1 +\n 1 file changed, 1 insertion(+)\n\n--- a/net/dsa/tag_qca.c\n+++ b/net/dsa/tag_qca.c\n@@ -68,6 +68,7 @@ static const struct dsa_device_ops qca_n\n \t.xmit\t= qca_tag_xmit,\n \t.rcv\t= qca_tag_rcv,\n \t.needed_headroom = QCA_HDR_LEN,\n+\t.promisc_on_master = true,\n };\n \n MODULE_LICENSE(\"GPL\");\n"
  },
  {
    "path": "target/linux/generic/backport-5.15/766-06-net-dsa-tag_qca-add-define-for-handling-mgmt-Etherne.patch",
    "content": "From c2ee8181fddb293d296477f60b3eb4fa3ce4e1a6 Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Wed, 2 Feb 2022 01:03:25 +0100\nSubject: [PATCH 06/16] net: dsa: tag_qca: add define for handling mgmt\n Ethernet packet\n\nAdd all the required define to prepare support for mgmt read/write in\nEthernet packet. Any packet of this type has to be dropped as the only\nuse of these special packet is receive ack for an mgmt write request or\nreceive data for an mgmt read request.\nA struct is used that emulates the Ethernet header but is used for a\ndifferent purpose.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nReviewed-by: Florian Fainelli <f.fainelli@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n include/linux/dsa/tag_qca.h | 44 +++++++++++++++++++++++++++++++++++++\n net/dsa/tag_qca.c           | 15 ++++++++++---\n 2 files changed, 56 insertions(+), 3 deletions(-)\n\n--- a/include/linux/dsa/tag_qca.h\n+++ b/include/linux/dsa/tag_qca.h\n@@ -12,10 +12,54 @@\n #define QCA_HDR_RECV_FRAME_IS_TAGGED\tBIT(3)\n #define QCA_HDR_RECV_SOURCE_PORT\tGENMASK(2, 0)\n \n+/* Packet type for recv */\n+#define QCA_HDR_RECV_TYPE_NORMAL\t0x0\n+#define QCA_HDR_RECV_TYPE_MIB\t\t0x1\n+#define QCA_HDR_RECV_TYPE_RW_REG_ACK\t0x2\n+\n #define QCA_HDR_XMIT_VERSION\t\tGENMASK(15, 14)\n #define QCA_HDR_XMIT_PRIORITY\t\tGENMASK(13, 11)\n #define QCA_HDR_XMIT_CONTROL\t\tGENMASK(10, 8)\n #define QCA_HDR_XMIT_FROM_CPU\t\tBIT(7)\n #define QCA_HDR_XMIT_DP_BIT\t\tGENMASK(6, 0)\n \n+/* Packet type for xmit */\n+#define QCA_HDR_XMIT_TYPE_NORMAL\t0x0\n+#define QCA_HDR_XMIT_TYPE_RW_REG\t0x1\n+\n+/* Check code for a valid mgmt packet. Switch will ignore the packet\n+ * with this wrong.\n+ */\n+#define QCA_HDR_MGMT_CHECK_CODE_VAL\t0x5\n+\n+/* Specific define for in-band MDIO read/write with Ethernet packet */\n+#define QCA_HDR_MGMT_SEQ_LEN\t\t4 /* 4 byte for the seq */\n+#define QCA_HDR_MGMT_COMMAND_LEN\t4 /* 4 byte for the command */\n+#define QCA_HDR_MGMT_DATA1_LEN\t\t4 /* First 4 byte for the mdio data */\n+#define QCA_HDR_MGMT_HEADER_LEN\t\t(QCA_HDR_MGMT_SEQ_LEN + \\\n+\t\t\t\t\tQCA_HDR_MGMT_COMMAND_LEN + \\\n+\t\t\t\t\tQCA_HDR_MGMT_DATA1_LEN)\n+\n+#define QCA_HDR_MGMT_DATA2_LEN\t\t12 /* Other 12 byte for the mdio data */\n+#define QCA_HDR_MGMT_PADDING_LEN\t34 /* Padding to reach the min Ethernet packet */\n+\n+#define QCA_HDR_MGMT_PKT_LEN\t\t(QCA_HDR_MGMT_HEADER_LEN + \\\n+\t\t\t\t\tQCA_HDR_LEN + \\\n+\t\t\t\t\tQCA_HDR_MGMT_DATA2_LEN + \\\n+\t\t\t\t\tQCA_HDR_MGMT_PADDING_LEN)\n+\n+#define QCA_HDR_MGMT_SEQ_NUM\t\tGENMASK(31, 0)  /* 63, 32 */\n+#define QCA_HDR_MGMT_CHECK_CODE\t\tGENMASK(31, 29) /* 31, 29 */\n+#define QCA_HDR_MGMT_CMD\t\tBIT(28)\t\t/* 28 */\n+#define QCA_HDR_MGMT_LENGTH\t\tGENMASK(23, 20) /* 23, 20 */\n+#define QCA_HDR_MGMT_ADDR\t\tGENMASK(18, 0)  /* 18, 0 */\n+\n+/* Special struct emulating a Ethernet header */\n+struct qca_mgmt_ethhdr {\n+\tu32 command;\t\t/* command bit 31:0 */\n+\tu32 seq;\t\t/* seq 63:32 */\n+\tu32 mdio_data;\t\t/* first 4byte mdio */\n+\t__be16 hdr;\t\t/* qca hdr */\n+} __packed;\n+\n #endif /* __TAG_QCA_H */\n--- a/net/dsa/tag_qca.c\n+++ b/net/dsa/tag_qca.c\n@@ -32,10 +32,12 @@ static struct sk_buff *qca_tag_xmit(stru\n \n static struct sk_buff *qca_tag_rcv(struct sk_buff *skb, struct net_device *dev)\n {\n-\tu8 ver;\n-\tu16  hdr;\n-\tint port;\n+\tu8 ver, pk_type;\n \t__be16 *phdr;\n+\tint port;\n+\tu16 hdr;\n+\n+\tBUILD_BUG_ON(sizeof(struct qca_mgmt_ethhdr) != QCA_HDR_MGMT_HEADER_LEN + QCA_HDR_LEN);\n \n \tif (unlikely(!pskb_may_pull(skb, QCA_HDR_LEN)))\n \t\treturn NULL;\n@@ -48,6 +50,13 @@ static struct sk_buff *qca_tag_rcv(struc\n \tif (unlikely(ver != QCA_HDR_VERSION))\n \t\treturn NULL;\n \n+\t/* Get pk type */\n+\tpk_type = FIELD_GET(QCA_HDR_RECV_TYPE, hdr);\n+\n+\t/* Ethernet MDIO read/write packet */\n+\tif (pk_type == QCA_HDR_RECV_TYPE_RW_REG_ACK)\n+\t\treturn NULL;\n+\n \t/* Remove QCA tag and recalculate checksum */\n \tskb_pull_rcsum(skb, QCA_HDR_LEN);\n \tdsa_strip_etype_header(skb, QCA_HDR_LEN);\n"
  },
  {
    "path": "target/linux/generic/backport-5.15/766-07-net-dsa-tag_qca-add-define-for-handling-MIB-packet.patch",
    "content": "From 18be654a4345f7d937b4bfbad74bea8093e3a93c Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Wed, 2 Feb 2022 01:03:26 +0100\nSubject: [PATCH 07/16] net: dsa: tag_qca: add define for handling MIB packet\n\nAdd struct to correctly parse a mib Ethernet packet.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nReviewed-by: Florian Fainelli <f.fainelli@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n include/linux/dsa/tag_qca.h | 10 ++++++++++\n net/dsa/tag_qca.c           |  4 ++++\n 2 files changed, 14 insertions(+)\n\n--- a/include/linux/dsa/tag_qca.h\n+++ b/include/linux/dsa/tag_qca.h\n@@ -62,4 +62,14 @@ struct qca_mgmt_ethhdr {\n \t__be16 hdr;\t\t/* qca hdr */\n } __packed;\n \n+enum mdio_cmd {\n+\tMDIO_WRITE = 0x0,\n+\tMDIO_READ\n+};\n+\n+struct mib_ethhdr {\n+\tu32 data[3];\t\t/* first 3 mib counter */\n+\t__be16 hdr;\t\t/* qca hdr */\n+} __packed;\n+\n #endif /* __TAG_QCA_H */\n--- a/net/dsa/tag_qca.c\n+++ b/net/dsa/tag_qca.c\n@@ -57,6 +57,10 @@ static struct sk_buff *qca_tag_rcv(struc\n \tif (pk_type == QCA_HDR_RECV_TYPE_RW_REG_ACK)\n \t\treturn NULL;\n \n+\t/* Ethernet MIB counter packet */\n+\tif (pk_type == QCA_HDR_RECV_TYPE_MIB)\n+\t\treturn NULL;\n+\n \t/* Remove QCA tag and recalculate checksum */\n \tskb_pull_rcsum(skb, QCA_HDR_LEN);\n \tdsa_strip_etype_header(skb, QCA_HDR_LEN);\n"
  },
  {
    "path": "target/linux/generic/backport-5.15/766-08-net-dsa-tag_qca-add-support-for-handling-mgmt-and-MI.patch",
    "content": "From 31eb6b4386ad91930417e3f5c8157a4b5e31cbd5 Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Wed, 2 Feb 2022 01:03:27 +0100\nSubject: [PATCH 08/16] net: dsa: tag_qca: add support for handling mgmt and\n MIB Ethernet packet\n\nAdd connect/disconnect helper to assign private struct to the DSA switch.\nAdd support for Ethernet mgmt and MIB if the DSA driver provide an handler\nto correctly parse and elaborate the data.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nReviewed-by: Vladimir Oltean <olteanv@gmail.com>\nReviewed-by: Florian Fainelli <f.fainelli@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n include/linux/dsa/tag_qca.h |  7 +++++++\n net/dsa/tag_qca.c           | 39 ++++++++++++++++++++++++++++++++++---\n 2 files changed, 43 insertions(+), 3 deletions(-)\n\n--- a/include/linux/dsa/tag_qca.h\n+++ b/include/linux/dsa/tag_qca.h\n@@ -72,4 +72,11 @@ struct mib_ethhdr {\n \t__be16 hdr;\t\t/* qca hdr */\n } __packed;\n \n+struct qca_tagger_data {\n+\tvoid (*rw_reg_ack_handler)(struct dsa_switch *ds,\n+\t\t\t\t   struct sk_buff *skb);\n+\tvoid (*mib_autocast_handler)(struct dsa_switch *ds,\n+\t\t\t\t     struct sk_buff *skb);\n+};\n+\n #endif /* __TAG_QCA_H */\n--- a/net/dsa/tag_qca.c\n+++ b/net/dsa/tag_qca.c\n@@ -5,6 +5,7 @@\n \n #include <linux/etherdevice.h>\n #include <linux/bitfield.h>\n+#include <net/dsa.h>\n #include <linux/dsa/tag_qca.h>\n \n #include \"dsa_priv.h\"\n@@ -32,6 +33,9 @@ static struct sk_buff *qca_tag_xmit(stru\n \n static struct sk_buff *qca_tag_rcv(struct sk_buff *skb, struct net_device *dev)\n {\n+\tstruct qca_tagger_data *tagger_data;\n+\tstruct dsa_port *dp = dev->dsa_ptr;\n+\tstruct dsa_switch *ds = dp->ds;\n \tu8 ver, pk_type;\n \t__be16 *phdr;\n \tint port;\n@@ -39,6 +43,8 @@ static struct sk_buff *qca_tag_rcv(struc\n \n \tBUILD_BUG_ON(sizeof(struct qca_mgmt_ethhdr) != QCA_HDR_MGMT_HEADER_LEN + QCA_HDR_LEN);\n \n+\ttagger_data = ds->tagger_data;\n+\n \tif (unlikely(!pskb_may_pull(skb, QCA_HDR_LEN)))\n \t\treturn NULL;\n \n@@ -53,13 +59,19 @@ static struct sk_buff *qca_tag_rcv(struc\n \t/* Get pk type */\n \tpk_type = FIELD_GET(QCA_HDR_RECV_TYPE, hdr);\n \n-\t/* Ethernet MDIO read/write packet */\n-\tif (pk_type == QCA_HDR_RECV_TYPE_RW_REG_ACK)\n+\t/* Ethernet mgmt read/write packet */\n+\tif (pk_type == QCA_HDR_RECV_TYPE_RW_REG_ACK) {\n+\t\tif (likely(tagger_data->rw_reg_ack_handler))\n+\t\t\ttagger_data->rw_reg_ack_handler(ds, skb);\n \t\treturn NULL;\n+\t}\n \n \t/* Ethernet MIB counter packet */\n-\tif (pk_type == QCA_HDR_RECV_TYPE_MIB)\n+\tif (pk_type == QCA_HDR_RECV_TYPE_MIB) {\n+\t\tif (likely(tagger_data->mib_autocast_handler))\n+\t\t\ttagger_data->mib_autocast_handler(ds, skb);\n \t\treturn NULL;\n+\t}\n \n \t/* Remove QCA tag and recalculate checksum */\n \tskb_pull_rcsum(skb, QCA_HDR_LEN);\n@@ -75,9 +87,30 @@ static struct sk_buff *qca_tag_rcv(struc\n \treturn skb;\n }\n \n+static int qca_tag_connect(struct dsa_switch *ds)\n+{\n+\tstruct qca_tagger_data *tagger_data;\n+\n+\ttagger_data = kzalloc(sizeof(*tagger_data), GFP_KERNEL);\n+\tif (!tagger_data)\n+\t\treturn -ENOMEM;\n+\n+\tds->tagger_data = tagger_data;\n+\n+\treturn 0;\n+}\n+\n+static void qca_tag_disconnect(struct dsa_switch *ds)\n+{\n+\tkfree(ds->tagger_data);\n+\tds->tagger_data = NULL;\n+}\n+\n static const struct dsa_device_ops qca_netdev_ops = {\n \t.name\t= \"qca\",\n \t.proto\t= DSA_TAG_PROTO_QCA,\n+\t.connect = qca_tag_connect,\n+\t.disconnect = qca_tag_disconnect,\n \t.xmit\t= qca_tag_xmit,\n \t.rcv\t= qca_tag_rcv,\n \t.needed_headroom = QCA_HDR_LEN,\n"
  },
  {
    "path": "target/linux/generic/backport-5.15/766-09-net-dsa-qca8k-add-tracking-state-of-master-port.patch",
    "content": "From cddbec19466a1dfb4d45ddd507d9f09f991d54ae Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Wed, 2 Feb 2022 01:03:28 +0100\nSubject: [PATCH 09/16] net: dsa: qca8k: add tracking state of master port\n\nMDIO/MIB Ethernet require the master port and the tagger availabale to\ncorrectly work. Use the new api master_state_change to track when master\nis operational or not and set a bool in qca8k_priv.\nWe cache the first cached master available and we check if other cpu\nport are operational when the cached one goes down.\nThis cached master will later be used by mdio read/write and mib request to\ncorrectly use the working function.\n\nqca8k implementation for MDIO/MIB Ethernet is bad. CPU port0 is the only\none that answers with the ack packet or sends MIB Ethernet packets. For\nthis reason the master_state_change ignore CPU port6 and only checks\nCPU port0 if it's operational and enables this mode.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nReviewed-by: Florian Fainelli <f.fainelli@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/dsa/qca8k.c | 15 +++++++++++++++\n drivers/net/dsa/qca8k.h |  1 +\n 2 files changed, 16 insertions(+)\n\n--- a/drivers/net/dsa/qca8k.c\n+++ b/drivers/net/dsa/qca8k.c\n@@ -2382,6 +2382,20 @@ qca8k_port_lag_leave(struct dsa_switch *\n \treturn qca8k_lag_refresh_portmap(ds, port, lag, true);\n }\n \n+static void\n+qca8k_master_change(struct dsa_switch *ds, const struct net_device *master,\n+\t\t    bool operational)\n+{\n+\tstruct dsa_port *dp = master->dsa_ptr;\n+\tstruct qca8k_priv *priv = ds->priv;\n+\n+\t/* Ethernet MIB/MDIO is only supported for CPU port 0 */\n+\tif (dp->index != 0)\n+\t\treturn;\n+\n+\tpriv->mgmt_master = operational ? (struct net_device *)master : NULL;\n+}\n+\n static const struct dsa_switch_ops qca8k_switch_ops = {\n \t.get_tag_protocol\t= qca8k_get_tag_protocol,\n \t.setup\t\t\t= qca8k_setup,\n@@ -2417,6 +2431,7 @@ static const struct dsa_switch_ops qca8k\n \t.get_phy_flags\t\t= qca8k_get_phy_flags,\n \t.port_lag_join\t\t= qca8k_port_lag_join,\n \t.port_lag_leave\t\t= qca8k_port_lag_leave,\n+\t.master_state_change\t= qca8k_master_change,\n };\n \n static int qca8k_read_switch_id(struct qca8k_priv *priv)\n--- a/drivers/net/dsa/qca8k.h\n+++ b/drivers/net/dsa/qca8k.h\n@@ -353,6 +353,7 @@ struct qca8k_priv {\n \tstruct dsa_switch_ops ops;\n \tstruct gpio_desc *reset_gpio;\n \tunsigned int port_mtu[QCA8K_NUM_PORTS];\n+\tstruct net_device *mgmt_master; /* Track if mdio/mib Ethernet is available */\n };\n \n struct qca8k_mib_desc {\n"
  },
  {
    "path": "target/linux/generic/backport-5.15/766-10-net-dsa-qca8k-add-support-for-mgmt-read-write-in-Eth.patch",
    "content": "From 5950c7c0a68c915b336c70f79388626e2d576ab7 Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Wed, 2 Feb 2022 01:03:29 +0100\nSubject: [PATCH 10/16] net: dsa: qca8k: add support for mgmt read/write in\n Ethernet packet\n\nAdd qca8k side support for mgmt read/write in Ethernet packet.\nqca8k supports some specially crafted Ethernet packet that can be used\nfor mgmt read/write instead of the legacy method uart/internal mdio.\nThis add support for the qca8k side to craft the packet and enqueue it.\nEach port and the qca8k_priv have a special struct to put data in it.\nThe completion API is used to wait for the packet to be received back\nwith the requested data.\n\nThe various steps are:\n1. Craft the special packet with the qca hdr set to mgmt read/write\n   mode.\n2. Set the lock in the dedicated mgmt struct.\n3. Increment the seq number and set it in the mgmt pkt\n4. Reinit the completion.\n5. Enqueue the packet.\n6. Wait the packet to be received.\n7. Use the data set by the tagger to complete the mdio operation.\n\nIf the completion timeouts or the ack value is not true, the legacy\nmdio way is used.\n\nIt has to be considered that in the initial setup mdio is still used and\nmdio is still used until DSA is ready to accept and tag packet.\n\ntag_proto_connect() is used to fill the required handler for the tagger\nto correctly parse and elaborate the special Ethernet mdio packet.\n\nLocking is added to qca8k_master_change() to make sure no mgmt Ethernet\nare in progress.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/dsa/qca8k.c | 225 ++++++++++++++++++++++++++++++++++++++++\n drivers/net/dsa/qca8k.h |  13 +++\n 2 files changed, 238 insertions(+)\n\n--- a/drivers/net/dsa/qca8k.c\n+++ b/drivers/net/dsa/qca8k.c\n@@ -20,6 +20,7 @@\n #include <linux/phylink.h>\n #include <linux/gpio/consumer.h>\n #include <linux/etherdevice.h>\n+#include <linux/dsa/tag_qca.h>\n \n #include \"qca8k.h\"\n \n@@ -170,6 +171,194 @@ qca8k_rmw(struct qca8k_priv *priv, u32 r\n \treturn regmap_update_bits(priv->regmap, reg, mask, write_val);\n }\n \n+static void qca8k_rw_reg_ack_handler(struct dsa_switch *ds, struct sk_buff *skb)\n+{\n+\tstruct qca8k_mgmt_eth_data *mgmt_eth_data;\n+\tstruct qca8k_priv *priv = ds->priv;\n+\tstruct qca_mgmt_ethhdr *mgmt_ethhdr;\n+\tu8 len, cmd;\n+\n+\tmgmt_ethhdr = (struct qca_mgmt_ethhdr *)skb_mac_header(skb);\n+\tmgmt_eth_data = &priv->mgmt_eth_data;\n+\n+\tcmd = FIELD_GET(QCA_HDR_MGMT_CMD, mgmt_ethhdr->command);\n+\tlen = FIELD_GET(QCA_HDR_MGMT_LENGTH, mgmt_ethhdr->command);\n+\n+\t/* Make sure the seq match the requested packet */\n+\tif (mgmt_ethhdr->seq == mgmt_eth_data->seq)\n+\t\tmgmt_eth_data->ack = true;\n+\n+\tif (cmd == MDIO_READ) {\n+\t\tmgmt_eth_data->data[0] = mgmt_ethhdr->mdio_data;\n+\n+\t\t/* Get the rest of the 12 byte of data */\n+\t\tif (len > QCA_HDR_MGMT_DATA1_LEN)\n+\t\t\tmemcpy(mgmt_eth_data->data + 1, skb->data,\n+\t\t\t       QCA_HDR_MGMT_DATA2_LEN);\n+\t}\n+\n+\tcomplete(&mgmt_eth_data->rw_done);\n+}\n+\n+static struct sk_buff *qca8k_alloc_mdio_header(enum mdio_cmd cmd, u32 reg, u32 *val,\n+\t\t\t\t\t       int priority)\n+{\n+\tstruct qca_mgmt_ethhdr *mgmt_ethhdr;\n+\tstruct sk_buff *skb;\n+\tu16 hdr;\n+\n+\tskb = dev_alloc_skb(QCA_HDR_MGMT_PKT_LEN);\n+\tif (!skb)\n+\t\treturn NULL;\n+\n+\tskb_reset_mac_header(skb);\n+\tskb_set_network_header(skb, skb->len);\n+\n+\tmgmt_ethhdr = skb_push(skb, QCA_HDR_MGMT_HEADER_LEN + QCA_HDR_LEN);\n+\n+\thdr = FIELD_PREP(QCA_HDR_XMIT_VERSION, QCA_HDR_VERSION);\n+\thdr |= FIELD_PREP(QCA_HDR_XMIT_PRIORITY, priority);\n+\thdr |= QCA_HDR_XMIT_FROM_CPU;\n+\thdr |= FIELD_PREP(QCA_HDR_XMIT_DP_BIT, BIT(0));\n+\thdr |= FIELD_PREP(QCA_HDR_XMIT_CONTROL, QCA_HDR_XMIT_TYPE_RW_REG);\n+\n+\tmgmt_ethhdr->command = FIELD_PREP(QCA_HDR_MGMT_ADDR, reg);\n+\tmgmt_ethhdr->command |= FIELD_PREP(QCA_HDR_MGMT_LENGTH, 4);\n+\tmgmt_ethhdr->command |= FIELD_PREP(QCA_HDR_MGMT_CMD, cmd);\n+\tmgmt_ethhdr->command |= FIELD_PREP(QCA_HDR_MGMT_CHECK_CODE,\n+\t\t\t\t\t   QCA_HDR_MGMT_CHECK_CODE_VAL);\n+\n+\tif (cmd == MDIO_WRITE)\n+\t\tmgmt_ethhdr->mdio_data = *val;\n+\n+\tmgmt_ethhdr->hdr = htons(hdr);\n+\n+\tskb_put_zero(skb, QCA_HDR_MGMT_DATA2_LEN + QCA_HDR_MGMT_PADDING_LEN);\n+\n+\treturn skb;\n+}\n+\n+static void qca8k_mdio_header_fill_seq_num(struct sk_buff *skb, u32 seq_num)\n+{\n+\tstruct qca_mgmt_ethhdr *mgmt_ethhdr;\n+\n+\tmgmt_ethhdr = (struct qca_mgmt_ethhdr *)skb->data;\n+\tmgmt_ethhdr->seq = FIELD_PREP(QCA_HDR_MGMT_SEQ_NUM, seq_num);\n+}\n+\n+static int qca8k_read_eth(struct qca8k_priv *priv, u32 reg, u32 *val)\n+{\n+\tstruct qca8k_mgmt_eth_data *mgmt_eth_data = &priv->mgmt_eth_data;\n+\tstruct sk_buff *skb;\n+\tbool ack;\n+\tint ret;\n+\n+\tskb = qca8k_alloc_mdio_header(MDIO_READ, reg, NULL,\n+\t\t\t\t      QCA8K_ETHERNET_MDIO_PRIORITY);\n+\tif (!skb)\n+\t\treturn -ENOMEM;\n+\n+\tmutex_lock(&mgmt_eth_data->mutex);\n+\n+\t/* Check mgmt_master if is operational */\n+\tif (!priv->mgmt_master) {\n+\t\tkfree_skb(skb);\n+\t\tmutex_unlock(&mgmt_eth_data->mutex);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tskb->dev = priv->mgmt_master;\n+\n+\treinit_completion(&mgmt_eth_data->rw_done);\n+\n+\t/* Increment seq_num and set it in the mdio pkt */\n+\tmgmt_eth_data->seq++;\n+\tqca8k_mdio_header_fill_seq_num(skb, mgmt_eth_data->seq);\n+\tmgmt_eth_data->ack = false;\n+\n+\tdev_queue_xmit(skb);\n+\n+\tret = wait_for_completion_timeout(&mgmt_eth_data->rw_done,\n+\t\t\t\t\t  msecs_to_jiffies(QCA8K_ETHERNET_TIMEOUT));\n+\n+\t*val = mgmt_eth_data->data[0];\n+\tack = mgmt_eth_data->ack;\n+\n+\tmutex_unlock(&mgmt_eth_data->mutex);\n+\n+\tif (ret <= 0)\n+\t\treturn -ETIMEDOUT;\n+\n+\tif (!ack)\n+\t\treturn -EINVAL;\n+\n+\treturn 0;\n+}\n+\n+static int qca8k_write_eth(struct qca8k_priv *priv, u32 reg, u32 val)\n+{\n+\tstruct qca8k_mgmt_eth_data *mgmt_eth_data = &priv->mgmt_eth_data;\n+\tstruct sk_buff *skb;\n+\tbool ack;\n+\tint ret;\n+\n+\tskb = qca8k_alloc_mdio_header(MDIO_WRITE, reg, &val,\n+\t\t\t\t      QCA8K_ETHERNET_MDIO_PRIORITY);\n+\tif (!skb)\n+\t\treturn -ENOMEM;\n+\n+\tmutex_lock(&mgmt_eth_data->mutex);\n+\n+\t/* Check mgmt_master if is operational */\n+\tif (!priv->mgmt_master) {\n+\t\tkfree_skb(skb);\n+\t\tmutex_unlock(&mgmt_eth_data->mutex);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tskb->dev = priv->mgmt_master;\n+\n+\treinit_completion(&mgmt_eth_data->rw_done);\n+\n+\t/* Increment seq_num and set it in the mdio pkt */\n+\tmgmt_eth_data->seq++;\n+\tqca8k_mdio_header_fill_seq_num(skb, mgmt_eth_data->seq);\n+\tmgmt_eth_data->ack = false;\n+\n+\tdev_queue_xmit(skb);\n+\n+\tret = wait_for_completion_timeout(&mgmt_eth_data->rw_done,\n+\t\t\t\t\t  msecs_to_jiffies(QCA8K_ETHERNET_TIMEOUT));\n+\n+\tack = mgmt_eth_data->ack;\n+\n+\tmutex_unlock(&mgmt_eth_data->mutex);\n+\n+\tif (ret <= 0)\n+\t\treturn -ETIMEDOUT;\n+\n+\tif (!ack)\n+\t\treturn -EINVAL;\n+\n+\treturn 0;\n+}\n+\n+static int\n+qca8k_regmap_update_bits_eth(struct qca8k_priv *priv, u32 reg, u32 mask, u32 write_val)\n+{\n+\tu32 val = 0;\n+\tint ret;\n+\n+\tret = qca8k_read_eth(priv, reg, &val);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tval &= ~mask;\n+\tval |= write_val;\n+\n+\treturn qca8k_write_eth(priv, reg, val);\n+}\n+\n static int\n qca8k_regmap_read(void *ctx, uint32_t reg, uint32_t *val)\n {\n@@ -178,6 +367,9 @@ qca8k_regmap_read(void *ctx, uint32_t re\n \tu16 r1, r2, page;\n \tint ret;\n \n+\tif (!qca8k_read_eth(priv, reg, val))\n+\t\treturn 0;\n+\n \tqca8k_split_addr(reg, &r1, &r2, &page);\n \n \tmutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);\n@@ -201,6 +393,9 @@ qca8k_regmap_write(void *ctx, uint32_t r\n \tu16 r1, r2, page;\n \tint ret;\n \n+\tif (!qca8k_write_eth(priv, reg, val))\n+\t\treturn 0;\n+\n \tqca8k_split_addr(reg, &r1, &r2, &page);\n \n \tmutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);\n@@ -225,6 +420,9 @@ qca8k_regmap_update_bits(void *ctx, uint\n \tu32 val;\n \tint ret;\n \n+\tif (!qca8k_regmap_update_bits_eth(priv, reg, mask, write_val))\n+\t\treturn 0;\n+\n \tqca8k_split_addr(reg, &r1, &r2, &page);\n \n \tmutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);\n@@ -2393,7 +2591,30 @@ qca8k_master_change(struct dsa_switch *d\n \tif (dp->index != 0)\n \t\treturn;\n \n+\tmutex_lock(&priv->mgmt_eth_data.mutex);\n+\n \tpriv->mgmt_master = operational ? (struct net_device *)master : NULL;\n+\n+\tmutex_unlock(&priv->mgmt_eth_data.mutex);\n+}\n+\n+static int qca8k_connect_tag_protocol(struct dsa_switch *ds,\n+\t\t\t\t      enum dsa_tag_protocol proto)\n+{\n+\tstruct qca_tagger_data *tagger_data;\n+\n+\tswitch (proto) {\n+\tcase DSA_TAG_PROTO_QCA:\n+\t\ttagger_data = ds->tagger_data;\n+\n+\t\ttagger_data->rw_reg_ack_handler = qca8k_rw_reg_ack_handler;\n+\n+\t\tbreak;\n+\tdefault:\n+\t\treturn -EOPNOTSUPP;\n+\t}\n+\n+\treturn 0;\n }\n \n static const struct dsa_switch_ops qca8k_switch_ops = {\n@@ -2432,6 +2653,7 @@ static const struct dsa_switch_ops qca8k\n \t.port_lag_join\t\t= qca8k_port_lag_join,\n \t.port_lag_leave\t\t= qca8k_port_lag_leave,\n \t.master_state_change\t= qca8k_master_change,\n+\t.connect_tag_protocol\t= qca8k_connect_tag_protocol,\n };\n \n static int qca8k_read_switch_id(struct qca8k_priv *priv)\n@@ -2511,6 +2733,9 @@ qca8k_sw_probe(struct mdio_device *mdiod\n \tif (!priv->ds)\n \t\treturn -ENOMEM;\n \n+\tmutex_init(&priv->mgmt_eth_data.mutex);\n+\tinit_completion(&priv->mgmt_eth_data.rw_done);\n+\n \tpriv->ds->dev = &mdiodev->dev;\n \tpriv->ds->num_ports = QCA8K_NUM_PORTS;\n \tpriv->ds->priv = priv;\n--- a/drivers/net/dsa/qca8k.h\n+++ b/drivers/net/dsa/qca8k.h\n@@ -11,6 +11,10 @@\n #include <linux/delay.h>\n #include <linux/regmap.h>\n #include <linux/gpio.h>\n+#include <linux/dsa/tag_qca.h>\n+\n+#define QCA8K_ETHERNET_MDIO_PRIORITY\t\t\t7\n+#define QCA8K_ETHERNET_TIMEOUT\t\t\t\t100\n \n #define QCA8K_NUM_PORTS\t\t\t\t\t7\n #define QCA8K_NUM_CPU_PORTS\t\t\t\t2\n@@ -328,6 +332,14 @@ enum {\n \tQCA8K_CPU_PORT6,\n };\n \n+struct qca8k_mgmt_eth_data {\n+\tstruct completion rw_done;\n+\tstruct mutex mutex; /* Enforce one mdio read/write at time */\n+\tbool ack;\n+\tu32 seq;\n+\tu32 data[4];\n+};\n+\n struct qca8k_ports_config {\n \tbool sgmii_rx_clk_falling_edge;\n \tbool sgmii_tx_clk_falling_edge;\n@@ -354,6 +366,7 @@ struct qca8k_priv {\n \tstruct gpio_desc *reset_gpio;\n \tunsigned int port_mtu[QCA8K_NUM_PORTS];\n \tstruct net_device *mgmt_master; /* Track if mdio/mib Ethernet is available */\n+\tstruct qca8k_mgmt_eth_data mgmt_eth_data;\n };\n \n struct qca8k_mib_desc {\n"
  },
  {
    "path": "target/linux/generic/backport-5.15/766-11-net-dsa-qca8k-add-support-for-mib-autocast-in-Ethern.patch",
    "content": "From 5c957c7ca78cce5e4b96866722b0115bd758d945 Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Wed, 2 Feb 2022 01:03:30 +0100\nSubject: [PATCH 11/16] net: dsa: qca8k: add support for mib autocast in\n Ethernet packet\n\nThe switch can autocast MIB counter using Ethernet packet.\nAdd support for this and provide a handler for the tagger.\nThe switch will send packet with MIB counter for each port, the switch\nwill use completion API to wait for the correct packet to be received\nand will complete the task only when each packet is received.\nAlthough the handler will drop all the other packet, we still have to\nconsume each MIB packet to complete the request. This is done to prevent\nmixed data with concurrent ethtool request.\n\nconnect_tag_protocol() is used to add the handler to the tag_qca tagger,\nmaster_state_change() use the MIB lock to make sure no MIB Ethernet is\nin progress.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/dsa/qca8k.c | 106 +++++++++++++++++++++++++++++++++++++++-\n drivers/net/dsa/qca8k.h |  17 ++++++-\n 2 files changed, 121 insertions(+), 2 deletions(-)\n\n--- a/drivers/net/dsa/qca8k.c\n+++ b/drivers/net/dsa/qca8k.c\n@@ -830,7 +830,10 @@ qca8k_mib_init(struct qca8k_priv *priv)\n \tint ret;\n \n \tmutex_lock(&priv->reg_mutex);\n-\tret = regmap_set_bits(priv->regmap, QCA8K_REG_MIB, QCA8K_MIB_FLUSH | QCA8K_MIB_BUSY);\n+\tret = regmap_update_bits(priv->regmap, QCA8K_REG_MIB,\n+\t\t\t\t QCA8K_MIB_FUNC | QCA8K_MIB_BUSY,\n+\t\t\t\t FIELD_PREP(QCA8K_MIB_FUNC, QCA8K_MIB_FLUSH) |\n+\t\t\t\t QCA8K_MIB_BUSY);\n \tif (ret)\n \t\tgoto exit;\n \n@@ -1901,6 +1904,97 @@ qca8k_get_strings(struct dsa_switch *ds,\n \t\t\tETH_GSTRING_LEN);\n }\n \n+static void qca8k_mib_autocast_handler(struct dsa_switch *ds, struct sk_buff *skb)\n+{\n+\tconst struct qca8k_match_data *match_data;\n+\tstruct qca8k_mib_eth_data *mib_eth_data;\n+\tstruct qca8k_priv *priv = ds->priv;\n+\tconst struct qca8k_mib_desc *mib;\n+\tstruct mib_ethhdr *mib_ethhdr;\n+\tint i, mib_len, offset = 0;\n+\tu64 *data;\n+\tu8 port;\n+\n+\tmib_ethhdr = (struct mib_ethhdr *)skb_mac_header(skb);\n+\tmib_eth_data = &priv->mib_eth_data;\n+\n+\t/* The switch autocast every port. Ignore other packet and\n+\t * parse only the requested one.\n+\t */\n+\tport = FIELD_GET(QCA_HDR_RECV_SOURCE_PORT, ntohs(mib_ethhdr->hdr));\n+\tif (port != mib_eth_data->req_port)\n+\t\tgoto exit;\n+\n+\tmatch_data = device_get_match_data(priv->dev);\n+\tdata = mib_eth_data->data;\n+\n+\tfor (i = 0; i < match_data->mib_count; i++) {\n+\t\tmib = &ar8327_mib[i];\n+\n+\t\t/* First 3 mib are present in the skb head */\n+\t\tif (i < 3) {\n+\t\t\tdata[i] = mib_ethhdr->data[i];\n+\t\t\tcontinue;\n+\t\t}\n+\n+\t\tmib_len = sizeof(uint32_t);\n+\n+\t\t/* Some mib are 64 bit wide */\n+\t\tif (mib->size == 2)\n+\t\t\tmib_len = sizeof(uint64_t);\n+\n+\t\t/* Copy the mib value from packet to the */\n+\t\tmemcpy(data + i, skb->data + offset, mib_len);\n+\n+\t\t/* Set the offset for the next mib */\n+\t\toffset += mib_len;\n+\t}\n+\n+exit:\n+\t/* Complete on receiving all the mib packet */\n+\tif (refcount_dec_and_test(&mib_eth_data->port_parsed))\n+\t\tcomplete(&mib_eth_data->rw_done);\n+}\n+\n+static int\n+qca8k_get_ethtool_stats_eth(struct dsa_switch *ds, int port, u64 *data)\n+{\n+\tstruct dsa_port *dp = dsa_to_port(ds, port);\n+\tstruct qca8k_mib_eth_data *mib_eth_data;\n+\tstruct qca8k_priv *priv = ds->priv;\n+\tint ret;\n+\n+\tmib_eth_data = &priv->mib_eth_data;\n+\n+\tmutex_lock(&mib_eth_data->mutex);\n+\n+\treinit_completion(&mib_eth_data->rw_done);\n+\n+\tmib_eth_data->req_port = dp->index;\n+\tmib_eth_data->data = data;\n+\trefcount_set(&mib_eth_data->port_parsed, QCA8K_NUM_PORTS);\n+\n+\tmutex_lock(&priv->reg_mutex);\n+\n+\t/* Send mib autocast request */\n+\tret = regmap_update_bits(priv->regmap, QCA8K_REG_MIB,\n+\t\t\t\t QCA8K_MIB_FUNC | QCA8K_MIB_BUSY,\n+\t\t\t\t FIELD_PREP(QCA8K_MIB_FUNC, QCA8K_MIB_CAST) |\n+\t\t\t\t QCA8K_MIB_BUSY);\n+\n+\tmutex_unlock(&priv->reg_mutex);\n+\n+\tif (ret)\n+\t\tgoto exit;\n+\n+\tret = wait_for_completion_timeout(&mib_eth_data->rw_done, QCA8K_ETHERNET_TIMEOUT);\n+\n+exit:\n+\tmutex_unlock(&mib_eth_data->mutex);\n+\n+\treturn ret;\n+}\n+\n static void\n qca8k_get_ethtool_stats(struct dsa_switch *ds, int port,\n \t\t\tuint64_t *data)\n@@ -1912,6 +2006,10 @@ qca8k_get_ethtool_stats(struct dsa_switc\n \tu32 hi = 0;\n \tint ret;\n \n+\tif (priv->mgmt_master &&\n+\t    qca8k_get_ethtool_stats_eth(ds, port, data) > 0)\n+\t\treturn;\n+\n \tmatch_data = of_device_get_match_data(priv->dev);\n \n \tfor (i = 0; i < match_data->mib_count; i++) {\n@@ -2592,9 +2690,11 @@ qca8k_master_change(struct dsa_switch *d\n \t\treturn;\n \n \tmutex_lock(&priv->mgmt_eth_data.mutex);\n+\tmutex_lock(&priv->mib_eth_data.mutex);\n \n \tpriv->mgmt_master = operational ? (struct net_device *)master : NULL;\n \n+\tmutex_unlock(&priv->mib_eth_data.mutex);\n \tmutex_unlock(&priv->mgmt_eth_data.mutex);\n }\n \n@@ -2608,6 +2708,7 @@ static int qca8k_connect_tag_protocol(st\n \t\ttagger_data = ds->tagger_data;\n \n \t\ttagger_data->rw_reg_ack_handler = qca8k_rw_reg_ack_handler;\n+\t\ttagger_data->mib_autocast_handler = qca8k_mib_autocast_handler;\n \n \t\tbreak;\n \tdefault:\n@@ -2736,6 +2837,9 @@ qca8k_sw_probe(struct mdio_device *mdiod\n \tmutex_init(&priv->mgmt_eth_data.mutex);\n \tinit_completion(&priv->mgmt_eth_data.rw_done);\n \n+\tmutex_init(&priv->mib_eth_data.mutex);\n+\tinit_completion(&priv->mib_eth_data.rw_done);\n+\n \tpriv->ds->dev = &mdiodev->dev;\n \tpriv->ds->num_ports = QCA8K_NUM_PORTS;\n \tpriv->ds->priv = priv;\n--- a/drivers/net/dsa/qca8k.h\n+++ b/drivers/net/dsa/qca8k.h\n@@ -67,7 +67,7 @@\n #define QCA8K_REG_MODULE_EN\t\t\t\t0x030\n #define   QCA8K_MODULE_EN_MIB\t\t\t\tBIT(0)\n #define QCA8K_REG_MIB\t\t\t\t\t0x034\n-#define   QCA8K_MIB_FLUSH\t\t\t\tBIT(24)\n+#define   QCA8K_MIB_FUNC\t\t\t\tGENMASK(26, 24)\n #define   QCA8K_MIB_CPU_KEEP\t\t\t\tBIT(20)\n #define   QCA8K_MIB_BUSY\t\t\t\tBIT(17)\n #define QCA8K_MDIO_MASTER_CTRL\t\t\t\t0x3c\n@@ -317,6 +317,12 @@ enum qca8k_vlan_cmd {\n \tQCA8K_VLAN_READ = 6,\n };\n \n+enum qca8k_mid_cmd {\n+\tQCA8K_MIB_FLUSH = 1,\n+\tQCA8K_MIB_FLUSH_PORT = 2,\n+\tQCA8K_MIB_CAST = 3,\n+};\n+\n struct ar8xxx_port_status {\n \tint enabled;\n };\n@@ -340,6 +346,14 @@ struct qca8k_mgmt_eth_data {\n \tu32 data[4];\n };\n \n+struct qca8k_mib_eth_data {\n+\tstruct completion rw_done;\n+\tstruct mutex mutex; /* Process one command at time */\n+\trefcount_t port_parsed; /* Counter to track parsed port */\n+\tu8 req_port;\n+\tu64 *data; /* pointer to ethtool data */\n+};\n+\n struct qca8k_ports_config {\n \tbool sgmii_rx_clk_falling_edge;\n \tbool sgmii_tx_clk_falling_edge;\n@@ -367,6 +381,7 @@ struct qca8k_priv {\n \tunsigned int port_mtu[QCA8K_NUM_PORTS];\n \tstruct net_device *mgmt_master; /* Track if mdio/mib Ethernet is available */\n \tstruct qca8k_mgmt_eth_data mgmt_eth_data;\n+\tstruct qca8k_mib_eth_data mib_eth_data;\n };\n \n struct qca8k_mib_desc {\n"
  },
  {
    "path": "target/linux/generic/backport-5.15/766-12-net-dsa-qca8k-add-support-for-phy-read-write-with-mg.patch",
    "content": "From 2cd5485663847d468dc207b3ff85fb1fab44d97f Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Wed, 2 Feb 2022 01:03:31 +0100\nSubject: [PATCH 12/16] net: dsa: qca8k: add support for phy read/write with\n mgmt Ethernet\n\nUse mgmt Ethernet also for phy read/write if availabale. Use a different\nseq number to make sure we receive the correct packet.\nOn any error, we fallback to the legacy mdio read/write.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/dsa/qca8k.c | 216 ++++++++++++++++++++++++++++++++++++++++\n drivers/net/dsa/qca8k.h |   1 +\n 2 files changed, 217 insertions(+)\n\n--- a/drivers/net/dsa/qca8k.c\n+++ b/drivers/net/dsa/qca8k.c\n@@ -867,6 +867,199 @@ qca8k_port_set_status(struct qca8k_priv\n \t\tregmap_clear_bits(priv->regmap, QCA8K_REG_PORT_STATUS(port), mask);\n }\n \n+static int\n+qca8k_phy_eth_busy_wait(struct qca8k_mgmt_eth_data *mgmt_eth_data,\n+\t\t\tstruct sk_buff *read_skb, u32 *val)\n+{\n+\tstruct sk_buff *skb = skb_copy(read_skb, GFP_KERNEL);\n+\tbool ack;\n+\tint ret;\n+\n+\treinit_completion(&mgmt_eth_data->rw_done);\n+\n+\t/* Increment seq_num and set it in the copy pkt */\n+\tmgmt_eth_data->seq++;\n+\tqca8k_mdio_header_fill_seq_num(skb, mgmt_eth_data->seq);\n+\tmgmt_eth_data->ack = false;\n+\n+\tdev_queue_xmit(skb);\n+\n+\tret = wait_for_completion_timeout(&mgmt_eth_data->rw_done,\n+\t\t\t\t\t  QCA8K_ETHERNET_TIMEOUT);\n+\n+\tack = mgmt_eth_data->ack;\n+\n+\tif (ret <= 0)\n+\t\treturn -ETIMEDOUT;\n+\n+\tif (!ack)\n+\t\treturn -EINVAL;\n+\n+\t*val = mgmt_eth_data->data[0];\n+\n+\treturn 0;\n+}\n+\n+static int\n+qca8k_phy_eth_command(struct qca8k_priv *priv, bool read, int phy,\n+\t\t      int regnum, u16 data)\n+{\n+\tstruct sk_buff *write_skb, *clear_skb, *read_skb;\n+\tstruct qca8k_mgmt_eth_data *mgmt_eth_data;\n+\tu32 write_val, clear_val = 0, val;\n+\tstruct net_device *mgmt_master;\n+\tint ret, ret1;\n+\tbool ack;\n+\n+\tif (regnum >= QCA8K_MDIO_MASTER_MAX_REG)\n+\t\treturn -EINVAL;\n+\n+\tmgmt_eth_data = &priv->mgmt_eth_data;\n+\n+\twrite_val = QCA8K_MDIO_MASTER_BUSY | QCA8K_MDIO_MASTER_EN |\n+\t\t    QCA8K_MDIO_MASTER_PHY_ADDR(phy) |\n+\t\t    QCA8K_MDIO_MASTER_REG_ADDR(regnum);\n+\n+\tif (read) {\n+\t\twrite_val |= QCA8K_MDIO_MASTER_READ;\n+\t} else {\n+\t\twrite_val |= QCA8K_MDIO_MASTER_WRITE;\n+\t\twrite_val |= QCA8K_MDIO_MASTER_DATA(data);\n+\t}\n+\n+\t/* Prealloc all the needed skb before the lock */\n+\twrite_skb = qca8k_alloc_mdio_header(MDIO_WRITE, QCA8K_MDIO_MASTER_CTRL,\n+\t\t\t\t\t    &write_val, QCA8K_ETHERNET_PHY_PRIORITY);\n+\tif (!write_skb)\n+\t\treturn -ENOMEM;\n+\n+\tclear_skb = qca8k_alloc_mdio_header(MDIO_WRITE, QCA8K_MDIO_MASTER_CTRL,\n+\t\t\t\t\t    &clear_val, QCA8K_ETHERNET_PHY_PRIORITY);\n+\tif (!write_skb) {\n+\t\tret = -ENOMEM;\n+\t\tgoto err_clear_skb;\n+\t}\n+\n+\tread_skb = qca8k_alloc_mdio_header(MDIO_READ, QCA8K_MDIO_MASTER_CTRL,\n+\t\t\t\t\t   &clear_val, QCA8K_ETHERNET_PHY_PRIORITY);\n+\tif (!write_skb) {\n+\t\tret = -ENOMEM;\n+\t\tgoto err_read_skb;\n+\t}\n+\n+\t/* Actually start the request:\n+\t * 1. Send mdio master packet\n+\t * 2. Busy Wait for mdio master command\n+\t * 3. Get the data if we are reading\n+\t * 4. Reset the mdio master (even with error)\n+\t */\n+\tmutex_lock(&mgmt_eth_data->mutex);\n+\n+\t/* Check if mgmt_master is operational */\n+\tmgmt_master = priv->mgmt_master;\n+\tif (!mgmt_master) {\n+\t\tmutex_unlock(&mgmt_eth_data->mutex);\n+\t\tret = -EINVAL;\n+\t\tgoto err_mgmt_master;\n+\t}\n+\n+\tread_skb->dev = mgmt_master;\n+\tclear_skb->dev = mgmt_master;\n+\twrite_skb->dev = mgmt_master;\n+\n+\treinit_completion(&mgmt_eth_data->rw_done);\n+\n+\t/* Increment seq_num and set it in the write pkt */\n+\tmgmt_eth_data->seq++;\n+\tqca8k_mdio_header_fill_seq_num(write_skb, mgmt_eth_data->seq);\n+\tmgmt_eth_data->ack = false;\n+\n+\tdev_queue_xmit(write_skb);\n+\n+\tret = wait_for_completion_timeout(&mgmt_eth_data->rw_done,\n+\t\t\t\t\t  QCA8K_ETHERNET_TIMEOUT);\n+\n+\tack = mgmt_eth_data->ack;\n+\n+\tif (ret <= 0) {\n+\t\tret = -ETIMEDOUT;\n+\t\tkfree_skb(read_skb);\n+\t\tgoto exit;\n+\t}\n+\n+\tif (!ack) {\n+\t\tret = -EINVAL;\n+\t\tkfree_skb(read_skb);\n+\t\tgoto exit;\n+\t}\n+\n+\tret = read_poll_timeout(qca8k_phy_eth_busy_wait, ret1,\n+\t\t\t\t!(val & QCA8K_MDIO_MASTER_BUSY), 0,\n+\t\t\t\tQCA8K_BUSY_WAIT_TIMEOUT * USEC_PER_MSEC, false,\n+\t\t\t\tmgmt_eth_data, read_skb, &val);\n+\n+\tif (ret < 0 && ret1 < 0) {\n+\t\tret = ret1;\n+\t\tgoto exit;\n+\t}\n+\n+\tif (read) {\n+\t\treinit_completion(&mgmt_eth_data->rw_done);\n+\n+\t\t/* Increment seq_num and set it in the read pkt */\n+\t\tmgmt_eth_data->seq++;\n+\t\tqca8k_mdio_header_fill_seq_num(read_skb, mgmt_eth_data->seq);\n+\t\tmgmt_eth_data->ack = false;\n+\n+\t\tdev_queue_xmit(read_skb);\n+\n+\t\tret = wait_for_completion_timeout(&mgmt_eth_data->rw_done,\n+\t\t\t\t\t\t  QCA8K_ETHERNET_TIMEOUT);\n+\n+\t\tack = mgmt_eth_data->ack;\n+\n+\t\tif (ret <= 0) {\n+\t\t\tret = -ETIMEDOUT;\n+\t\t\tgoto exit;\n+\t\t}\n+\n+\t\tif (!ack) {\n+\t\t\tret = -EINVAL;\n+\t\t\tgoto exit;\n+\t\t}\n+\n+\t\tret = mgmt_eth_data->data[0] & QCA8K_MDIO_MASTER_DATA_MASK;\n+\t} else {\n+\t\tkfree_skb(read_skb);\n+\t}\n+exit:\n+\treinit_completion(&mgmt_eth_data->rw_done);\n+\n+\t/* Increment seq_num and set it in the clear pkt */\n+\tmgmt_eth_data->seq++;\n+\tqca8k_mdio_header_fill_seq_num(clear_skb, mgmt_eth_data->seq);\n+\tmgmt_eth_data->ack = false;\n+\n+\tdev_queue_xmit(clear_skb);\n+\n+\twait_for_completion_timeout(&mgmt_eth_data->rw_done,\n+\t\t\t\t    QCA8K_ETHERNET_TIMEOUT);\n+\n+\tmutex_unlock(&mgmt_eth_data->mutex);\n+\n+\treturn ret;\n+\n+\t/* Error handling before lock */\n+err_mgmt_master:\n+\tkfree_skb(read_skb);\n+err_read_skb:\n+\tkfree_skb(clear_skb);\n+err_clear_skb:\n+\tkfree_skb(write_skb);\n+\n+\treturn ret;\n+}\n+\n static u32\n qca8k_port_to_phy(int port)\n {\n@@ -989,6 +1182,12 @@ qca8k_internal_mdio_write(struct mii_bus\n {\n \tstruct qca8k_priv *priv = slave_bus->priv;\n \tstruct mii_bus *bus = priv->bus;\n+\tint ret;\n+\n+\t/* Use mdio Ethernet when available, fallback to legacy one on error */\n+\tret = qca8k_phy_eth_command(priv, false, phy, regnum, data);\n+\tif (!ret)\n+\t\treturn 0;\n \n \treturn qca8k_mdio_write(bus, phy, regnum, data);\n }\n@@ -998,6 +1197,12 @@ qca8k_internal_mdio_read(struct mii_bus\n {\n \tstruct qca8k_priv *priv = slave_bus->priv;\n \tstruct mii_bus *bus = priv->bus;\n+\tint ret;\n+\n+\t/* Use mdio Ethernet when available, fallback to legacy one on error */\n+\tret = qca8k_phy_eth_command(priv, true, phy, regnum, 0);\n+\tif (ret >= 0)\n+\t\treturn ret;\n \n \treturn qca8k_mdio_read(bus, phy, regnum);\n }\n@@ -1006,6 +1211,7 @@ static int\n qca8k_phy_write(struct dsa_switch *ds, int port, int regnum, u16 data)\n {\n \tstruct qca8k_priv *priv = ds->priv;\n+\tint ret;\n \n \t/* Check if the legacy mapping should be used and the\n \t * port is not correctly mapped to the right PHY in the\n@@ -1014,6 +1220,11 @@ qca8k_phy_write(struct dsa_switch *ds, i\n \tif (priv->legacy_phy_port_mapping)\n \t\tport = qca8k_port_to_phy(port) % PHY_MAX_ADDR;\n \n+\t/* Use mdio Ethernet when available, fallback to legacy one on error */\n+\tret = qca8k_phy_eth_command(priv, false, port, regnum, 0);\n+\tif (!ret)\n+\t\treturn ret;\n+\n \treturn qca8k_mdio_write(priv->bus, port, regnum, data);\n }\n \n@@ -1030,6 +1241,11 @@ qca8k_phy_read(struct dsa_switch *ds, in\n \tif (priv->legacy_phy_port_mapping)\n \t\tport = qca8k_port_to_phy(port) % PHY_MAX_ADDR;\n \n+\t/* Use mdio Ethernet when available, fallback to legacy one on error */\n+\tret = qca8k_phy_eth_command(priv, true, port, regnum, 0);\n+\tif (ret >= 0)\n+\t\treturn ret;\n+\n \tret = qca8k_mdio_read(priv->bus, port, regnum);\n \n \tif (ret < 0)\n--- a/drivers/net/dsa/qca8k.h\n+++ b/drivers/net/dsa/qca8k.h\n@@ -14,6 +14,7 @@\n #include <linux/dsa/tag_qca.h>\n \n #define QCA8K_ETHERNET_MDIO_PRIORITY\t\t\t7\n+#define QCA8K_ETHERNET_PHY_PRIORITY\t\t\t6\n #define QCA8K_ETHERNET_TIMEOUT\t\t\t\t100\n \n #define QCA8K_NUM_PORTS\t\t\t\t\t7\n"
  },
  {
    "path": "target/linux/generic/backport-5.15/766-13-net-dsa-qca8k-move-page-cache-to-driver-priv.patch",
    "content": "From 4264350acb75430d5021a1d7de56a33faf69a097 Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Wed, 2 Feb 2022 01:03:32 +0100\nSubject: [PATCH 13/16] net: dsa: qca8k: move page cache to driver priv\n\nThere can be multiple qca8k switch on the same system. Move the static\nqca8k_current_page to qca8k_priv and make it specific for each switch.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nReviewed-by: Florian Fainelli <f.fainelli@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/dsa/qca8k.c | 42 ++++++++++++++++++++---------------------\n drivers/net/dsa/qca8k.h |  9 +++++++++\n 2 files changed, 29 insertions(+), 22 deletions(-)\n\n--- a/drivers/net/dsa/qca8k.c\n+++ b/drivers/net/dsa/qca8k.c\n@@ -75,12 +75,6 @@ static const struct qca8k_mib_desc ar832\n \tMIB_DESC(1, 0xac, \"TXUnicast\"),\n };\n \n-/* The 32bit switch registers are accessed indirectly. To achieve this we need\n- * to set the page of the register. Track the last page that was set to reduce\n- * mdio writes\n- */\n-static u16 qca8k_current_page = 0xffff;\n-\n static void\n qca8k_split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page)\n {\n@@ -134,11 +128,13 @@ qca8k_mii_write32(struct mii_bus *bus, i\n }\n \n static int\n-qca8k_set_page(struct mii_bus *bus, u16 page)\n+qca8k_set_page(struct qca8k_priv *priv, u16 page)\n {\n+\tu16 *cached_page = &priv->mdio_cache.page;\n+\tstruct mii_bus *bus = priv->bus;\n \tint ret;\n \n-\tif (page == qca8k_current_page)\n+\tif (page == *cached_page)\n \t\treturn 0;\n \n \tret = bus->write(bus, 0x18, 0, page);\n@@ -148,7 +144,7 @@ qca8k_set_page(struct mii_bus *bus, u16\n \t\treturn ret;\n \t}\n \n-\tqca8k_current_page = page;\n+\t*cached_page = page;\n \tusleep_range(1000, 2000);\n \treturn 0;\n }\n@@ -374,7 +370,7 @@ qca8k_regmap_read(void *ctx, uint32_t re\n \n \tmutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);\n \n-\tret = qca8k_set_page(bus, page);\n+\tret = qca8k_set_page(priv, page);\n \tif (ret < 0)\n \t\tgoto exit;\n \n@@ -400,7 +396,7 @@ qca8k_regmap_write(void *ctx, uint32_t r\n \n \tmutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);\n \n-\tret = qca8k_set_page(bus, page);\n+\tret = qca8k_set_page(priv, page);\n \tif (ret < 0)\n \t\tgoto exit;\n \n@@ -427,7 +423,7 @@ qca8k_regmap_update_bits(void *ctx, uint\n \n \tmutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);\n \n-\tret = qca8k_set_page(bus, page);\n+\tret = qca8k_set_page(priv, page);\n \tif (ret < 0)\n \t\tgoto exit;\n \n@@ -1098,8 +1094,9 @@ qca8k_mdio_busy_wait(struct mii_bus *bus\n }\n \n static int\n-qca8k_mdio_write(struct mii_bus *bus, int phy, int regnum, u16 data)\n+qca8k_mdio_write(struct qca8k_priv *priv, int phy, int regnum, u16 data)\n {\n+\tstruct mii_bus *bus = priv->bus;\n \tu16 r1, r2, page;\n \tu32 val;\n \tint ret;\n@@ -1116,7 +1113,7 @@ qca8k_mdio_write(struct mii_bus *bus, in\n \n \tmutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);\n \n-\tret = qca8k_set_page(bus, page);\n+\tret = qca8k_set_page(priv, page);\n \tif (ret)\n \t\tgoto exit;\n \n@@ -1135,8 +1132,9 @@ exit:\n }\n \n static int\n-qca8k_mdio_read(struct mii_bus *bus, int phy, int regnum)\n+qca8k_mdio_read(struct qca8k_priv *priv, int phy, int regnum)\n {\n+\tstruct mii_bus *bus = priv->bus;\n \tu16 r1, r2, page;\n \tu32 val;\n \tint ret;\n@@ -1152,7 +1150,7 @@ qca8k_mdio_read(struct mii_bus *bus, int\n \n \tmutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);\n \n-\tret = qca8k_set_page(bus, page);\n+\tret = qca8k_set_page(priv, page);\n \tif (ret)\n \t\tgoto exit;\n \n@@ -1181,7 +1179,6 @@ static int\n qca8k_internal_mdio_write(struct mii_bus *slave_bus, int phy, int regnum, u16 data)\n {\n \tstruct qca8k_priv *priv = slave_bus->priv;\n-\tstruct mii_bus *bus = priv->bus;\n \tint ret;\n \n \t/* Use mdio Ethernet when available, fallback to legacy one on error */\n@@ -1189,14 +1186,13 @@ qca8k_internal_mdio_write(struct mii_bus\n \tif (!ret)\n \t\treturn 0;\n \n-\treturn qca8k_mdio_write(bus, phy, regnum, data);\n+\treturn qca8k_mdio_write(priv, phy, regnum, data);\n }\n \n static int\n qca8k_internal_mdio_read(struct mii_bus *slave_bus, int phy, int regnum)\n {\n \tstruct qca8k_priv *priv = slave_bus->priv;\n-\tstruct mii_bus *bus = priv->bus;\n \tint ret;\n \n \t/* Use mdio Ethernet when available, fallback to legacy one on error */\n@@ -1204,7 +1200,7 @@ qca8k_internal_mdio_read(struct mii_bus\n \tif (ret >= 0)\n \t\treturn ret;\n \n-\treturn qca8k_mdio_read(bus, phy, regnum);\n+\treturn qca8k_mdio_read(priv, phy, regnum);\n }\n \n static int\n@@ -1225,7 +1221,7 @@ qca8k_phy_write(struct dsa_switch *ds, i\n \tif (!ret)\n \t\treturn ret;\n \n-\treturn qca8k_mdio_write(priv->bus, port, regnum, data);\n+\treturn qca8k_mdio_write(priv, port, regnum, data);\n }\n \n static int\n@@ -1246,7 +1242,7 @@ qca8k_phy_read(struct dsa_switch *ds, in\n \tif (ret >= 0)\n \t\treturn ret;\n \n-\tret = qca8k_mdio_read(priv->bus, port, regnum);\n+\tret = qca8k_mdio_read(priv, port, regnum);\n \n \tif (ret < 0)\n \t\treturn 0xffff;\n@@ -3041,6 +3037,8 @@ qca8k_sw_probe(struct mdio_device *mdiod\n \t\treturn PTR_ERR(priv->regmap);\n \t}\n \n+\tpriv->mdio_cache.page = 0xffff;\n+\n \t/* Check the detected switch id */\n \tret = qca8k_read_switch_id(priv);\n \tif (ret)\n--- a/drivers/net/dsa/qca8k.h\n+++ b/drivers/net/dsa/qca8k.h\n@@ -363,6 +363,14 @@ struct qca8k_ports_config {\n \tu8 rgmii_tx_delay[QCA8K_NUM_CPU_PORTS]; /* 0: CPU port0, 1: CPU port6 */\n };\n \n+struct qca8k_mdio_cache {\n+/* The 32bit switch registers are accessed indirectly. To achieve this we need\n+ * to set the page of the register. Track the last page that was set to reduce\n+ * mdio writes\n+ */\n+\tu16 page;\n+};\n+\n struct qca8k_priv {\n \tu8 switch_id;\n \tu8 switch_revision;\n@@ -383,6 +391,7 @@ struct qca8k_priv {\n \tstruct net_device *mgmt_master; /* Track if mdio/mib Ethernet is available */\n \tstruct qca8k_mgmt_eth_data mgmt_eth_data;\n \tstruct qca8k_mib_eth_data mib_eth_data;\n+\tstruct qca8k_mdio_cache mdio_cache;\n };\n \n struct qca8k_mib_desc {\n"
  },
  {
    "path": "target/linux/generic/backport-5.15/766-14-net-dsa-qca8k-cache-lo-and-hi-for-mdio-write.patch",
    "content": "From 2481d206fae7884cd07014fd1318e63af35e99eb Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Wed, 2 Feb 2022 01:03:33 +0100\nSubject: [PATCH 14/16] net: dsa: qca8k: cache lo and hi for mdio write\n\nFrom Documentation, we can cache lo and hi the same way we do with the\npage. This massively reduce the mdio write as 3/4 of the time as we only\nrequire to write the lo or hi part for a mdio write.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nReviewed-by: Florian Fainelli <f.fainelli@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/dsa/qca8k.c | 61 +++++++++++++++++++++++++++++++++--------\n drivers/net/dsa/qca8k.h |  5 ++++\n 2 files changed, 54 insertions(+), 12 deletions(-)\n\n--- a/drivers/net/dsa/qca8k.c\n+++ b/drivers/net/dsa/qca8k.c\n@@ -89,6 +89,44 @@ qca8k_split_addr(u32 regaddr, u16 *r1, u\n }\n \n static int\n+qca8k_set_lo(struct qca8k_priv *priv, int phy_id, u32 regnum, u16 lo)\n+{\n+\tu16 *cached_lo = &priv->mdio_cache.lo;\n+\tstruct mii_bus *bus = priv->bus;\n+\tint ret;\n+\n+\tif (lo == *cached_lo)\n+\t\treturn 0;\n+\n+\tret = bus->write(bus, phy_id, regnum, lo);\n+\tif (ret < 0)\n+\t\tdev_err_ratelimited(&bus->dev,\n+\t\t\t\t    \"failed to write qca8k 32bit lo register\\n\");\n+\n+\t*cached_lo = lo;\n+\treturn 0;\n+}\n+\n+static int\n+qca8k_set_hi(struct qca8k_priv *priv, int phy_id, u32 regnum, u16 hi)\n+{\n+\tu16 *cached_hi = &priv->mdio_cache.hi;\n+\tstruct mii_bus *bus = priv->bus;\n+\tint ret;\n+\n+\tif (hi == *cached_hi)\n+\t\treturn 0;\n+\n+\tret = bus->write(bus, phy_id, regnum, hi);\n+\tif (ret < 0)\n+\t\tdev_err_ratelimited(&bus->dev,\n+\t\t\t\t    \"failed to write qca8k 32bit hi register\\n\");\n+\n+\t*cached_hi = hi;\n+\treturn 0;\n+}\n+\n+static int\n qca8k_mii_read32(struct mii_bus *bus, int phy_id, u32 regnum, u32 *val)\n {\n \tint ret;\n@@ -111,7 +149,7 @@ qca8k_mii_read32(struct mii_bus *bus, in\n }\n \n static void\n-qca8k_mii_write32(struct mii_bus *bus, int phy_id, u32 regnum, u32 val)\n+qca8k_mii_write32(struct qca8k_priv *priv, int phy_id, u32 regnum, u32 val)\n {\n \tu16 lo, hi;\n \tint ret;\n@@ -119,12 +157,9 @@ qca8k_mii_write32(struct mii_bus *bus, i\n \tlo = val & 0xffff;\n \thi = (u16)(val >> 16);\n \n-\tret = bus->write(bus, phy_id, regnum, lo);\n+\tret = qca8k_set_lo(priv, phy_id, regnum, lo);\n \tif (ret >= 0)\n-\t\tret = bus->write(bus, phy_id, regnum + 1, hi);\n-\tif (ret < 0)\n-\t\tdev_err_ratelimited(&bus->dev,\n-\t\t\t\t    \"failed to write qca8k 32bit register\\n\");\n+\t\tret = qca8k_set_hi(priv, phy_id, regnum + 1, hi);\n }\n \n static int\n@@ -400,7 +435,7 @@ qca8k_regmap_write(void *ctx, uint32_t r\n \tif (ret < 0)\n \t\tgoto exit;\n \n-\tqca8k_mii_write32(bus, 0x10 | r2, r1, val);\n+\tqca8k_mii_write32(priv, 0x10 | r2, r1, val);\n \n exit:\n \tmutex_unlock(&bus->mdio_lock);\n@@ -433,7 +468,7 @@ qca8k_regmap_update_bits(void *ctx, uint\n \n \tval &= ~mask;\n \tval |= write_val;\n-\tqca8k_mii_write32(bus, 0x10 | r2, r1, val);\n+\tqca8k_mii_write32(priv, 0x10 | r2, r1, val);\n \n exit:\n \tmutex_unlock(&bus->mdio_lock);\n@@ -1117,14 +1152,14 @@ qca8k_mdio_write(struct qca8k_priv *priv\n \tif (ret)\n \t\tgoto exit;\n \n-\tqca8k_mii_write32(bus, 0x10 | r2, r1, val);\n+\tqca8k_mii_write32(priv, 0x10 | r2, r1, val);\n \n \tret = qca8k_mdio_busy_wait(bus, QCA8K_MDIO_MASTER_CTRL,\n \t\t\t\t   QCA8K_MDIO_MASTER_BUSY);\n \n exit:\n \t/* even if the busy_wait timeouts try to clear the MASTER_EN */\n-\tqca8k_mii_write32(bus, 0x10 | r2, r1, 0);\n+\tqca8k_mii_write32(priv, 0x10 | r2, r1, 0);\n \n \tmutex_unlock(&bus->mdio_lock);\n \n@@ -1154,7 +1189,7 @@ qca8k_mdio_read(struct qca8k_priv *priv,\n \tif (ret)\n \t\tgoto exit;\n \n-\tqca8k_mii_write32(bus, 0x10 | r2, r1, val);\n+\tqca8k_mii_write32(priv, 0x10 | r2, r1, val);\n \n \tret = qca8k_mdio_busy_wait(bus, QCA8K_MDIO_MASTER_CTRL,\n \t\t\t\t   QCA8K_MDIO_MASTER_BUSY);\n@@ -1165,7 +1200,7 @@ qca8k_mdio_read(struct qca8k_priv *priv,\n \n exit:\n \t/* even if the busy_wait timeouts try to clear the MASTER_EN */\n-\tqca8k_mii_write32(bus, 0x10 | r2, r1, 0);\n+\tqca8k_mii_write32(priv, 0x10 | r2, r1, 0);\n \n \tmutex_unlock(&bus->mdio_lock);\n \n@@ -3038,6 +3073,8 @@ qca8k_sw_probe(struct mdio_device *mdiod\n \t}\n \n \tpriv->mdio_cache.page = 0xffff;\n+\tpriv->mdio_cache.lo = 0xffff;\n+\tpriv->mdio_cache.hi = 0xffff;\n \n \t/* Check the detected switch id */\n \tret = qca8k_read_switch_id(priv);\n--- a/drivers/net/dsa/qca8k.h\n+++ b/drivers/net/dsa/qca8k.h\n@@ -369,6 +369,11 @@ struct qca8k_mdio_cache {\n  * mdio writes\n  */\n \tu16 page;\n+/* lo and hi can also be cached and from Documentation we can skip one\n+ * extra mdio write if lo or hi is didn't change.\n+ */\n+\tu16 lo;\n+\tu16 hi;\n };\n \n struct qca8k_priv {\n"
  },
  {
    "path": "target/linux/generic/backport-5.15/766-15-net-dsa-qca8k-add-support-for-larger-read-write-size.patch",
    "content": "From 90386223f44e2a751d7e9e9ac8f78ea33358a891 Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Wed, 2 Feb 2022 01:03:34 +0100\nSubject: [PATCH 15/16] net: dsa: qca8k: add support for larger read/write size\n with mgmt Ethernet\n\nmgmt Ethernet packet can read/write up to 16byte at times. The len reg\nis limited to 15 (0xf). The switch actually sends and accepts data in 4\ndifferent steps of len values.\nLen steps:\n- 0: nothing\n- 1-4: first 4 byte\n- 5-6: first 12 byte\n- 7-15: all 16 byte\n\nIn the alloc skb function we check if the len is 16 and we fix it to a\nlen of 15. It the read/write function interest to extract the real asked\ndata. The tagger handler will always copy the fully 16byte with a READ\ncommand. This is useful for some big regs like the fdb reg that are\nmore than 4byte of data. This permits to introduce a bulk function that\nwill send and request the entire entry in one go.\nWrite function is changed and it does now require to pass the pointer to\nval to also handle array val.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/dsa/qca8k.c | 61 +++++++++++++++++++++++++++--------------\n 1 file changed, 41 insertions(+), 20 deletions(-)\n\n--- a/drivers/net/dsa/qca8k.c\n+++ b/drivers/net/dsa/qca8k.c\n@@ -222,7 +222,9 @@ static void qca8k_rw_reg_ack_handler(str\n \tif (cmd == MDIO_READ) {\n \t\tmgmt_eth_data->data[0] = mgmt_ethhdr->mdio_data;\n \n-\t\t/* Get the rest of the 12 byte of data */\n+\t\t/* Get the rest of the 12 byte of data.\n+\t\t * The read/write function will extract the requested data.\n+\t\t */\n \t\tif (len > QCA_HDR_MGMT_DATA1_LEN)\n \t\t\tmemcpy(mgmt_eth_data->data + 1, skb->data,\n \t\t\t       QCA_HDR_MGMT_DATA2_LEN);\n@@ -232,16 +234,30 @@ static void qca8k_rw_reg_ack_handler(str\n }\n \n static struct sk_buff *qca8k_alloc_mdio_header(enum mdio_cmd cmd, u32 reg, u32 *val,\n-\t\t\t\t\t       int priority)\n+\t\t\t\t\t       int priority, unsigned int len)\n {\n \tstruct qca_mgmt_ethhdr *mgmt_ethhdr;\n+\tunsigned int real_len;\n \tstruct sk_buff *skb;\n+\tu32 *data2;\n \tu16 hdr;\n \n \tskb = dev_alloc_skb(QCA_HDR_MGMT_PKT_LEN);\n \tif (!skb)\n \t\treturn NULL;\n \n+\t/* Max value for len reg is 15 (0xf) but the switch actually return 16 byte\n+\t * Actually for some reason the steps are:\n+\t * 0: nothing\n+\t * 1-4: first 4 byte\n+\t * 5-6: first 12 byte\n+\t * 7-15: all 16 byte\n+\t */\n+\tif (len == 16)\n+\t\treal_len = 15;\n+\telse\n+\t\treal_len = len;\n+\n \tskb_reset_mac_header(skb);\n \tskb_set_network_header(skb, skb->len);\n \n@@ -254,7 +270,7 @@ static struct sk_buff *qca8k_alloc_mdio_\n \thdr |= FIELD_PREP(QCA_HDR_XMIT_CONTROL, QCA_HDR_XMIT_TYPE_RW_REG);\n \n \tmgmt_ethhdr->command = FIELD_PREP(QCA_HDR_MGMT_ADDR, reg);\n-\tmgmt_ethhdr->command |= FIELD_PREP(QCA_HDR_MGMT_LENGTH, 4);\n+\tmgmt_ethhdr->command |= FIELD_PREP(QCA_HDR_MGMT_LENGTH, real_len);\n \tmgmt_ethhdr->command |= FIELD_PREP(QCA_HDR_MGMT_CMD, cmd);\n \tmgmt_ethhdr->command |= FIELD_PREP(QCA_HDR_MGMT_CHECK_CODE,\n \t\t\t\t\t   QCA_HDR_MGMT_CHECK_CODE_VAL);\n@@ -264,7 +280,9 @@ static struct sk_buff *qca8k_alloc_mdio_\n \n \tmgmt_ethhdr->hdr = htons(hdr);\n \n-\tskb_put_zero(skb, QCA_HDR_MGMT_DATA2_LEN + QCA_HDR_MGMT_PADDING_LEN);\n+\tdata2 = skb_put_zero(skb, QCA_HDR_MGMT_DATA2_LEN + QCA_HDR_MGMT_PADDING_LEN);\n+\tif (cmd == MDIO_WRITE && len > QCA_HDR_MGMT_DATA1_LEN)\n+\t\tmemcpy(data2, val + 1, len - QCA_HDR_MGMT_DATA1_LEN);\n \n \treturn skb;\n }\n@@ -277,7 +295,7 @@ static void qca8k_mdio_header_fill_seq_n\n \tmgmt_ethhdr->seq = FIELD_PREP(QCA_HDR_MGMT_SEQ_NUM, seq_num);\n }\n \n-static int qca8k_read_eth(struct qca8k_priv *priv, u32 reg, u32 *val)\n+static int qca8k_read_eth(struct qca8k_priv *priv, u32 reg, u32 *val, int len)\n {\n \tstruct qca8k_mgmt_eth_data *mgmt_eth_data = &priv->mgmt_eth_data;\n \tstruct sk_buff *skb;\n@@ -285,7 +303,7 @@ static int qca8k_read_eth(struct qca8k_p\n \tint ret;\n \n \tskb = qca8k_alloc_mdio_header(MDIO_READ, reg, NULL,\n-\t\t\t\t      QCA8K_ETHERNET_MDIO_PRIORITY);\n+\t\t\t\t      QCA8K_ETHERNET_MDIO_PRIORITY, len);\n \tif (!skb)\n \t\treturn -ENOMEM;\n \n@@ -313,6 +331,9 @@ static int qca8k_read_eth(struct qca8k_p\n \t\t\t\t\t  msecs_to_jiffies(QCA8K_ETHERNET_TIMEOUT));\n \n \t*val = mgmt_eth_data->data[0];\n+\tif (len > QCA_HDR_MGMT_DATA1_LEN)\n+\t\tmemcpy(val + 1, mgmt_eth_data->data + 1, len - QCA_HDR_MGMT_DATA1_LEN);\n+\n \tack = mgmt_eth_data->ack;\n \n \tmutex_unlock(&mgmt_eth_data->mutex);\n@@ -326,15 +347,15 @@ static int qca8k_read_eth(struct qca8k_p\n \treturn 0;\n }\n \n-static int qca8k_write_eth(struct qca8k_priv *priv, u32 reg, u32 val)\n+static int qca8k_write_eth(struct qca8k_priv *priv, u32 reg, u32 *val, int len)\n {\n \tstruct qca8k_mgmt_eth_data *mgmt_eth_data = &priv->mgmt_eth_data;\n \tstruct sk_buff *skb;\n \tbool ack;\n \tint ret;\n \n-\tskb = qca8k_alloc_mdio_header(MDIO_WRITE, reg, &val,\n-\t\t\t\t      QCA8K_ETHERNET_MDIO_PRIORITY);\n+\tskb = qca8k_alloc_mdio_header(MDIO_WRITE, reg, val,\n+\t\t\t\t      QCA8K_ETHERNET_MDIO_PRIORITY, len);\n \tif (!skb)\n \t\treturn -ENOMEM;\n \n@@ -380,14 +401,14 @@ qca8k_regmap_update_bits_eth(struct qca8\n \tu32 val = 0;\n \tint ret;\n \n-\tret = qca8k_read_eth(priv, reg, &val);\n+\tret = qca8k_read_eth(priv, reg, &val, sizeof(val));\n \tif (ret)\n \t\treturn ret;\n \n \tval &= ~mask;\n \tval |= write_val;\n \n-\treturn qca8k_write_eth(priv, reg, val);\n+\treturn qca8k_write_eth(priv, reg, &val, sizeof(val));\n }\n \n static int\n@@ -398,7 +419,7 @@ qca8k_regmap_read(void *ctx, uint32_t re\n \tu16 r1, r2, page;\n \tint ret;\n \n-\tif (!qca8k_read_eth(priv, reg, val))\n+\tif (!qca8k_read_eth(priv, reg, val, sizeof(val)))\n \t\treturn 0;\n \n \tqca8k_split_addr(reg, &r1, &r2, &page);\n@@ -424,7 +445,7 @@ qca8k_regmap_write(void *ctx, uint32_t r\n \tu16 r1, r2, page;\n \tint ret;\n \n-\tif (!qca8k_write_eth(priv, reg, val))\n+\tif (!qca8k_write_eth(priv, reg, &val, sizeof(val)))\n \t\treturn 0;\n \n \tqca8k_split_addr(reg, &r1, &r2, &page);\n@@ -959,21 +980,21 @@ qca8k_phy_eth_command(struct qca8k_priv\n \t}\n \n \t/* Prealloc all the needed skb before the lock */\n-\twrite_skb = qca8k_alloc_mdio_header(MDIO_WRITE, QCA8K_MDIO_MASTER_CTRL,\n-\t\t\t\t\t    &write_val, QCA8K_ETHERNET_PHY_PRIORITY);\n+\twrite_skb = qca8k_alloc_mdio_header(MDIO_WRITE, QCA8K_MDIO_MASTER_CTRL, &write_val,\n+\t\t\t\t\t    QCA8K_ETHERNET_PHY_PRIORITY, sizeof(write_val));\n \tif (!write_skb)\n \t\treturn -ENOMEM;\n \n-\tclear_skb = qca8k_alloc_mdio_header(MDIO_WRITE, QCA8K_MDIO_MASTER_CTRL,\n-\t\t\t\t\t    &clear_val, QCA8K_ETHERNET_PHY_PRIORITY);\n+\tclear_skb = qca8k_alloc_mdio_header(MDIO_WRITE, QCA8K_MDIO_MASTER_CTRL, &clear_val,\n+\t\t\t\t\t    QCA8K_ETHERNET_PHY_PRIORITY, sizeof(clear_val));\n \tif (!write_skb) {\n \t\tret = -ENOMEM;\n \t\tgoto err_clear_skb;\n \t}\n \n-\tread_skb = qca8k_alloc_mdio_header(MDIO_READ, QCA8K_MDIO_MASTER_CTRL,\n-\t\t\t\t\t   &clear_val, QCA8K_ETHERNET_PHY_PRIORITY);\n-\tif (!write_skb) {\n+\tread_skb = qca8k_alloc_mdio_header(MDIO_READ, QCA8K_MDIO_MASTER_CTRL, &clear_val,\n+\t\t\t\t\t   QCA8K_ETHERNET_PHY_PRIORITY, sizeof(clear_val));\n+\tif (!read_skb) {\n \t\tret = -ENOMEM;\n \t\tgoto err_read_skb;\n \t}\n"
  },
  {
    "path": "target/linux/generic/backport-5.15/766-16-net-dsa-qca8k-introduce-qca8k_bulk_read-write-functi.patch",
    "content": "From 4f3701fc599820568ba4395070d34e4248800fc0 Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Wed, 2 Feb 2022 01:03:35 +0100\nSubject: [PATCH 16/16] net: dsa: qca8k: introduce qca8k_bulk_read/write\n function\n\nIntroduce qca8k_bulk_read/write() function to use mgmt Ethernet way to\nread/write packet in bulk. Make use of this new function in the fdb\nfunction and while at it reduce the reg for fdb_read from 4 to 3 as the\nmax bit for the ARL(fdb) table is 83 bits.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/dsa/qca8k.c | 55 ++++++++++++++++++++++++++++++++---------\n 1 file changed, 43 insertions(+), 12 deletions(-)\n\n--- a/drivers/net/dsa/qca8k.c\n+++ b/drivers/net/dsa/qca8k.c\n@@ -412,6 +412,43 @@ qca8k_regmap_update_bits_eth(struct qca8\n }\n \n static int\n+qca8k_bulk_read(struct qca8k_priv *priv, u32 reg, u32 *val, int len)\n+{\n+\tint i, count = len / sizeof(u32), ret;\n+\n+\tif (priv->mgmt_master && !qca8k_read_eth(priv, reg, val, len))\n+\t\treturn 0;\n+\n+\tfor (i = 0; i < count; i++) {\n+\t\tret = regmap_read(priv->regmap, reg + (i * 4), val + i);\n+\t\tif (ret < 0)\n+\t\t\treturn ret;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int\n+qca8k_bulk_write(struct qca8k_priv *priv, u32 reg, u32 *val, int len)\n+{\n+\tint i, count = len / sizeof(u32), ret;\n+\tu32 tmp;\n+\n+\tif (priv->mgmt_master && !qca8k_write_eth(priv, reg, val, len))\n+\t\treturn 0;\n+\n+\tfor (i = 0; i < count; i++) {\n+\t\ttmp = val[i];\n+\n+\t\tret = regmap_write(priv->regmap, reg + (i * 4), tmp);\n+\t\tif (ret < 0)\n+\t\t\treturn ret;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int\n qca8k_regmap_read(void *ctx, uint32_t reg, uint32_t *val)\n {\n \tstruct qca8k_priv *priv = (struct qca8k_priv *)ctx;\n@@ -546,17 +583,13 @@ qca8k_busy_wait(struct qca8k_priv *priv,\n static int\n qca8k_fdb_read(struct qca8k_priv *priv, struct qca8k_fdb *fdb)\n {\n-\tu32 reg[4], val;\n-\tint i, ret;\n+\tu32 reg[3];\n+\tint ret;\n \n \t/* load the ARL table into an array */\n-\tfor (i = 0; i < 4; i++) {\n-\t\tret = qca8k_read(priv, QCA8K_REG_ATU_DATA0 + (i * 4), &val);\n-\t\tif (ret < 0)\n-\t\t\treturn ret;\n-\n-\t\treg[i] = val;\n-\t}\n+\tret = qca8k_bulk_read(priv, QCA8K_REG_ATU_DATA0, reg, sizeof(reg));\n+\tif (ret)\n+\t\treturn ret;\n \n \t/* vid - 83:72 */\n \tfdb->vid = FIELD_GET(QCA8K_ATU_VID_MASK, reg[2]);\n@@ -580,7 +613,6 @@ qca8k_fdb_write(struct qca8k_priv *priv,\n \t\tu8 aging)\n {\n \tu32 reg[3] = { 0 };\n-\tint i;\n \n \t/* vid - 83:72 */\n \treg[2] = FIELD_PREP(QCA8K_ATU_VID_MASK, vid);\n@@ -597,8 +629,7 @@ qca8k_fdb_write(struct qca8k_priv *priv,\n \treg[0] |= FIELD_PREP(QCA8K_ATU_ADDR5_MASK, mac[5]);\n \n \t/* load the array into the ARL table */\n-\tfor (i = 0; i < 3; i++)\n-\t\tqca8k_write(priv, QCA8K_REG_ATU_DATA0 + (i * 4), reg[i]);\n+\tqca8k_bulk_write(priv, QCA8K_REG_ATU_DATA0, reg, sizeof(reg));\n }\n \n static int\n"
  },
  {
    "path": "target/linux/generic/backport-5.15/773-v5.18-1-net-dsa-Move-VLAN-filtering-syncing-out-of-dsa_switc.patch",
    "content": "From 381a730182f1d174e1950cd4e63e885b1c302051 Mon Sep 17 00:00:00 2001\nFrom: Tobias Waldekranz <tobias@waldekranz.com>\nDate: Mon, 24 Jan 2022 22:09:43 +0100\nSubject: net: dsa: Move VLAN filtering syncing out of dsa_switch_bridge_leave\n\nMost of dsa_switch_bridge_leave was, in fact, dealing with the syncing\nof VLAN filtering for switches on which that is a global\nsetting. Separate the two phases to prepare for the cross-chip related\nbugfix in the following commit.\n\nSigned-off-by: Tobias Waldekranz <tobias@waldekranz.com>\nReviewed-by: Vladimir Oltean <olteanv@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n net/dsa/switch.c | 38 +++++++++++++++++++++++++-------------\n 1 file changed, 25 insertions(+), 13 deletions(-)\n\n--- a/net/dsa/switch.c\n+++ b/net/dsa/switch.c\n@@ -113,25 +113,14 @@ static int dsa_switch_bridge_join(struct\n \treturn dsa_tag_8021q_bridge_join(ds, info);\n }\n \n-static int dsa_switch_bridge_leave(struct dsa_switch *ds,\n-\t\t\t\t   struct dsa_notifier_bridge_info *info)\n+static int dsa_switch_sync_vlan_filtering(struct dsa_switch *ds,\n+\t\t\t\t\t  struct dsa_notifier_bridge_info *info)\n {\n-\tstruct dsa_switch_tree *dst = ds->dst;\n \tstruct netlink_ext_ack extack = {0};\n \tbool change_vlan_filtering = false;\n \tbool vlan_filtering;\n \tint err, port;\n \n-\tif (dst->index == info->tree_index && ds->index == info->sw_index &&\n-\t    ds->ops->port_bridge_leave)\n-\t\tds->ops->port_bridge_leave(ds, info->port, info->br);\n-\n-\tif ((dst->index != info->tree_index || ds->index != info->sw_index) &&\n-\t    ds->ops->crosschip_bridge_leave)\n-\t\tds->ops->crosschip_bridge_leave(ds, info->tree_index,\n-\t\t\t\t\t\tinfo->sw_index, info->port,\n-\t\t\t\t\t\tinfo->br);\n-\n \tif (ds->needs_standalone_vlan_filtering && !br_vlan_enabled(info->br)) {\n \t\tchange_vlan_filtering = true;\n \t\tvlan_filtering = true;\n@@ -172,6 +161,29 @@ static int dsa_switch_bridge_leave(struc\n \t\t\treturn err;\n \t}\n \n+\treturn 0;\n+}\n+\n+static int dsa_switch_bridge_leave(struct dsa_switch *ds,\n+\t\t\t\t   struct dsa_notifier_bridge_info *info)\n+{\n+\tstruct dsa_switch_tree *dst = ds->dst;\n+\tint err;\n+\n+\tif (dst->index == info->tree_index && ds->index == info->sw_index &&\n+\t    ds->ops->port_bridge_leave)\n+\t\tds->ops->port_bridge_leave(ds, info->port, info->br);\n+\n+\tif ((dst->index != info->tree_index || ds->index != info->sw_index) &&\n+\t    ds->ops->crosschip_bridge_leave)\n+\t\tds->ops->crosschip_bridge_leave(ds, info->tree_index,\n+\t\t\t\t\t\tinfo->sw_index, info->port,\n+\t\t\t\t\t\tinfo->br);\n+\n+\terr = dsa_switch_sync_vlan_filtering(ds, info);\n+\tif (err)\n+\t\treturn err;\n+\n \treturn dsa_tag_8021q_bridge_leave(ds, info);\n }\n \n"
  },
  {
    "path": "target/linux/generic/backport-5.15/773-v5.18-2-net-dsa-Avoid-cross-chip-syncing-of-VLAN-filtering.patch",
    "content": "From 108dc8741c203e9d6ce4e973367f1bac20c7192b Mon Sep 17 00:00:00 2001\nFrom: Tobias Waldekranz <tobias@waldekranz.com>\nDate: Mon, 24 Jan 2022 22:09:44 +0100\nSubject: net: dsa: Avoid cross-chip syncing of VLAN filtering\n\nChanges to VLAN filtering are not applicable to cross-chip\nnotifications.\n\nOn a system like this:\n\n.-----.   .-----.   .-----.\n| sw1 +---+ sw2 +---+ sw3 |\n'-1-2-'   '-1-2-'   '-1-2-'\n\nBefore this change, upon sw1p1 leaving a bridge, a call to\ndsa_port_vlan_filtering would also be made to sw2p1 and sw3p1.\n\nIn this scenario:\n\n.---------.   .-----.   .-----.\n|   sw1   +---+ sw2 +---+ sw3 |\n'-1-2-3-4-'   '-1-2-'   '-1-2-'\n\nWhen sw1p4 would leave a bridge, dsa_port_vlan_filtering would be\ncalled for sw2 and sw3 with a non-existing port - leading to array\nout-of-bounds accesses and crashes on mv88e6xxx.\n\nFixes: d371b7c92d19 (\"net: dsa: Unset vlan_filtering when ports leave the bridge\")\nSigned-off-by: Tobias Waldekranz <tobias@waldekranz.com>\nReviewed-by: Vladimir Oltean <olteanv@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n net/dsa/switch.c | 8 +++++---\n 1 file changed, 5 insertions(+), 3 deletions(-)\n\n--- a/net/dsa/switch.c\n+++ b/net/dsa/switch.c\n@@ -180,9 +180,11 @@ static int dsa_switch_bridge_leave(struc\n \t\t\t\t\t\tinfo->sw_index, info->port,\n \t\t\t\t\t\tinfo->br);\n \n-\terr = dsa_switch_sync_vlan_filtering(ds, info);\n-\tif (err)\n-\t\treturn err;\n+\tif (ds->dst->index == info->tree_index && ds->index == info->sw_index) {\n+\t\terr = dsa_switch_sync_vlan_filtering(ds, info);\n+\t\tif (err)\n+\t\t\treturn err;\n+\t}\n \n \treturn dsa_tag_8021q_bridge_leave(ds, info);\n }\n"
  },
  {
    "path": "target/linux/generic/backport-5.15/774-v5.16-01-net-dsa-rtl8366rb-Support-bridge-offloading.patch",
    "content": "From c9111895fd38dadf125e07be627778a9950d8d77 Mon Sep 17 00:00:00 2001\nFrom: DENG Qingfang <dqfext@gmail.com>\nDate: Sun, 26 Sep 2021 00:59:24 +0200\nSubject: [PATCH 01/11] net: dsa: rtl8366rb: Support bridge offloading\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nUse port isolation registers to configure bridge offloading.\n\nTested on the D-Link DIR-685, switching between ports and\nsniffing ports to make sure no packets leak.\n\nCc: Vladimir Oltean <olteanv@gmail.com>\nCc: Mauri Sandberg <sandberg@mailfence.com>\nReviewed-by: Vladimir Oltean <olteanv@gmail.com>\nReviewed-by: Alvin Šipraga <alsi@bang-olufsen.dk>\nReviewed-by: Florian Fainelli <f.fainelli@gmail.com>\nSigned-off-by: DENG Qingfang <dqfext@gmail.com>\nSigned-off-by: Linus Walleij <linus.walleij@linaro.org>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/dsa/rtl8366rb.c | 86 +++++++++++++++++++++++++++++++++++++\n 1 file changed, 86 insertions(+)\n\n--- a/drivers/net/dsa/rtl8366rb.c\n+++ b/drivers/net/dsa/rtl8366rb.c\n@@ -300,6 +300,13 @@\n #define RTL8366RB_INTERRUPT_STATUS_REG\t0x0442\n #define RTL8366RB_NUM_INTERRUPT\t\t14 /* 0..13 */\n \n+/* Port isolation registers */\n+#define RTL8366RB_PORT_ISO_BASE\t\t0x0F08\n+#define RTL8366RB_PORT_ISO(pnum)\t(RTL8366RB_PORT_ISO_BASE + (pnum))\n+#define RTL8366RB_PORT_ISO_EN\t\tBIT(0)\n+#define RTL8366RB_PORT_ISO_PORTS_MASK\tGENMASK(7, 1)\n+#define RTL8366RB_PORT_ISO_PORTS(pmask)\t((pmask) << 1)\n+\n /* bits 0..5 enable force when cleared */\n #define RTL8366RB_MAC_FORCE_CTRL_REG\t0x0F11\n \n@@ -835,6 +842,21 @@ static int rtl8366rb_setup(struct dsa_sw\n \tif (ret)\n \t\treturn ret;\n \n+\t/* Isolate all user ports so they can only send packets to itself and the CPU port */\n+\tfor (i = 0; i < RTL8366RB_PORT_NUM_CPU; i++) {\n+\t\tret = regmap_write(smi->map, RTL8366RB_PORT_ISO(i),\n+\t\t\t\t   RTL8366RB_PORT_ISO_PORTS(BIT(RTL8366RB_PORT_NUM_CPU)) |\n+\t\t\t\t   RTL8366RB_PORT_ISO_EN);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\t}\n+\t/* CPU port can send packets to all ports */\n+\tret = regmap_write(smi->map, RTL8366RB_PORT_ISO(RTL8366RB_PORT_NUM_CPU),\n+\t\t\t   RTL8366RB_PORT_ISO_PORTS(dsa_user_ports(ds)) |\n+\t\t\t   RTL8366RB_PORT_ISO_EN);\n+\tif (ret)\n+\t\treturn ret;\n+\n \t/* Set up the \"green ethernet\" feature */\n \tret = rtl8366rb_jam_table(rtl8366rb_green_jam,\n \t\t\t\t  ARRAY_SIZE(rtl8366rb_green_jam), smi, false);\n@@ -1127,6 +1149,68 @@ rtl8366rb_port_disable(struct dsa_switch\n \trb8366rb_set_port_led(smi, port, false);\n }\n \n+static int\n+rtl8366rb_port_bridge_join(struct dsa_switch *ds, int port,\n+\t\t\t   struct net_device *bridge)\n+{\n+\tstruct realtek_smi *smi = ds->priv;\n+\tunsigned int port_bitmap = 0;\n+\tint ret, i;\n+\n+\t/* Loop over all other ports than the current one */\n+\tfor (i = 0; i < RTL8366RB_PORT_NUM_CPU; i++) {\n+\t\t/* Current port handled last */\n+\t\tif (i == port)\n+\t\t\tcontinue;\n+\t\t/* Not on this bridge */\n+\t\tif (dsa_to_port(ds, i)->bridge_dev != bridge)\n+\t\t\tcontinue;\n+\t\t/* Join this port to each other port on the bridge */\n+\t\tret = regmap_update_bits(smi->map, RTL8366RB_PORT_ISO(i),\n+\t\t\t\t\t RTL8366RB_PORT_ISO_PORTS(BIT(port)),\n+\t\t\t\t\t RTL8366RB_PORT_ISO_PORTS(BIT(port)));\n+\t\tif (ret)\n+\t\t\tdev_err(smi->dev, \"failed to join port %d\\n\", port);\n+\n+\t\tport_bitmap |= BIT(i);\n+\t}\n+\n+\t/* Set the bits for the ports we can access */\n+\treturn regmap_update_bits(smi->map, RTL8366RB_PORT_ISO(port),\n+\t\t\t\t  RTL8366RB_PORT_ISO_PORTS(port_bitmap),\n+\t\t\t\t  RTL8366RB_PORT_ISO_PORTS(port_bitmap));\n+}\n+\n+static void\n+rtl8366rb_port_bridge_leave(struct dsa_switch *ds, int port,\n+\t\t\t    struct net_device *bridge)\n+{\n+\tstruct realtek_smi *smi = ds->priv;\n+\tunsigned int port_bitmap = 0;\n+\tint ret, i;\n+\n+\t/* Loop over all other ports than this one */\n+\tfor (i = 0; i < RTL8366RB_PORT_NUM_CPU; i++) {\n+\t\t/* Current port handled last */\n+\t\tif (i == port)\n+\t\t\tcontinue;\n+\t\t/* Not on this bridge */\n+\t\tif (dsa_to_port(ds, i)->bridge_dev != bridge)\n+\t\t\tcontinue;\n+\t\t/* Remove this port from any other port on the bridge */\n+\t\tret = regmap_update_bits(smi->map, RTL8366RB_PORT_ISO(i),\n+\t\t\t\t\t RTL8366RB_PORT_ISO_PORTS(BIT(port)), 0);\n+\t\tif (ret)\n+\t\t\tdev_err(smi->dev, \"failed to leave port %d\\n\", port);\n+\n+\t\tport_bitmap |= BIT(i);\n+\t}\n+\n+\t/* Clear the bits for the ports we can not access, leave ourselves */\n+\tregmap_update_bits(smi->map, RTL8366RB_PORT_ISO(port),\n+\t\t\t   RTL8366RB_PORT_ISO_PORTS(port_bitmap), 0);\n+}\n+\n static int rtl8366rb_change_mtu(struct dsa_switch *ds, int port, int new_mtu)\n {\n \tstruct realtek_smi *smi = ds->priv;\n@@ -1510,6 +1594,8 @@ static const struct dsa_switch_ops rtl83\n \t.get_strings = rtl8366_get_strings,\n \t.get_ethtool_stats = rtl8366_get_ethtool_stats,\n \t.get_sset_count = rtl8366_get_sset_count,\n+\t.port_bridge_join = rtl8366rb_port_bridge_join,\n+\t.port_bridge_leave = rtl8366rb_port_bridge_leave,\n \t.port_vlan_filtering = rtl8366_vlan_filtering,\n \t.port_vlan_add = rtl8366_vlan_add,\n \t.port_vlan_del = rtl8366_vlan_del,\n"
  },
  {
    "path": "target/linux/generic/backport-5.15/774-v5.16-02-net-dsa-rtl8366-Drop-custom-VLAN-set-up.patch",
    "content": "From 96cf10a8e7297065459473c081a6fb6432a22312 Mon Sep 17 00:00:00 2001\nFrom: Linus Walleij <linus.walleij@linaro.org>\nDate: Sun, 26 Sep 2021 00:59:25 +0200\nSubject: [PATCH 02/11] net: dsa: rtl8366: Drop custom VLAN set-up\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nThis hacky default VLAN setup was done in order to direct\npackets to the right ports and provide port isolation, both\nwhich we now support properly using custom tags and proper\nbridge port isolation.\n\nWe can drop the custom VLAN code and leave all VLAN handling\nalone, as users expect things to be. We can also drop\nds->configure_vlan_while_not_filtering = false; and let\nthe core deal with any VLANs it wants.\n\nCc: Mauri Sandberg <sandberg@mailfence.com>\nCc: DENG Qingfang <dqfext@gmail.com>\nReviewed-by: Vladimir Oltean <olteanv@gmail.com>\nReviewed-by: Alvin Šipraga <alsi@bang-olufsen.dk>\nReviewed-by: Florian Fainelli <f.fainelli@gmail.com>\nSigned-off-by: Linus Walleij <linus.walleij@linaro.org>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/dsa/realtek-smi-core.h |  1 -\n drivers/net/dsa/rtl8366.c          | 48 ------------------------------\n drivers/net/dsa/rtl8366rb.c        |  4 +--\n 3 files changed, 1 insertion(+), 52 deletions(-)\n\n--- a/drivers/net/dsa/realtek-smi-core.h\n+++ b/drivers/net/dsa/realtek-smi-core.h\n@@ -129,7 +129,6 @@ int rtl8366_set_pvid(struct realtek_smi\n int rtl8366_enable_vlan4k(struct realtek_smi *smi, bool enable);\n int rtl8366_enable_vlan(struct realtek_smi *smi, bool enable);\n int rtl8366_reset_vlan(struct realtek_smi *smi);\n-int rtl8366_init_vlan(struct realtek_smi *smi);\n int rtl8366_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering,\n \t\t\t   struct netlink_ext_ack *extack);\n int rtl8366_vlan_add(struct dsa_switch *ds, int port,\n--- a/drivers/net/dsa/rtl8366.c\n+++ b/drivers/net/dsa/rtl8366.c\n@@ -292,54 +292,6 @@ int rtl8366_reset_vlan(struct realtek_sm\n }\n EXPORT_SYMBOL_GPL(rtl8366_reset_vlan);\n \n-int rtl8366_init_vlan(struct realtek_smi *smi)\n-{\n-\tint port;\n-\tint ret;\n-\n-\tret = rtl8366_reset_vlan(smi);\n-\tif (ret)\n-\t\treturn ret;\n-\n-\t/* Loop over the available ports, for each port, associate\n-\t * it with the VLAN (port+1)\n-\t */\n-\tfor (port = 0; port < smi->num_ports; port++) {\n-\t\tu32 mask;\n-\n-\t\tif (port == smi->cpu_port)\n-\t\t\t/* For the CPU port, make all ports members of this\n-\t\t\t * VLAN.\n-\t\t\t */\n-\t\t\tmask = GENMASK((int)smi->num_ports - 1, 0);\n-\t\telse\n-\t\t\t/* For all other ports, enable itself plus the\n-\t\t\t * CPU port.\n-\t\t\t */\n-\t\t\tmask = BIT(port) | BIT(smi->cpu_port);\n-\n-\t\t/* For each port, set the port as member of VLAN (port+1)\n-\t\t * and untagged, except for the CPU port: the CPU port (5) is\n-\t\t * member of VLAN 6 and so are ALL the other ports as well.\n-\t\t * Use filter 0 (no filter).\n-\t\t */\n-\t\tdev_info(smi->dev, \"VLAN%d port mask for port %d, %08x\\n\",\n-\t\t\t (port + 1), port, mask);\n-\t\tret = rtl8366_set_vlan(smi, (port + 1), mask, mask, 0);\n-\t\tif (ret)\n-\t\t\treturn ret;\n-\n-\t\tdev_info(smi->dev, \"VLAN%d port %d, PVID set to %d\\n\",\n-\t\t\t (port + 1), port, (port + 1));\n-\t\tret = rtl8366_set_pvid(smi, port, (port + 1));\n-\t\tif (ret)\n-\t\t\treturn ret;\n-\t}\n-\n-\treturn rtl8366_enable_vlan(smi, true);\n-}\n-EXPORT_SYMBOL_GPL(rtl8366_init_vlan);\n-\n int rtl8366_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering,\n \t\t\t   struct netlink_ext_ack *extack)\n {\n--- a/drivers/net/dsa/rtl8366rb.c\n+++ b/drivers/net/dsa/rtl8366rb.c\n@@ -985,7 +985,7 @@ static int rtl8366rb_setup(struct dsa_sw\n \t\t\treturn ret;\n \t}\n \n-\tret = rtl8366_init_vlan(smi);\n+\tret = rtl8366_reset_vlan(smi);\n \tif (ret)\n \t\treturn ret;\n \n@@ -999,8 +999,6 @@ static int rtl8366rb_setup(struct dsa_sw\n \t\treturn -ENODEV;\n \t}\n \n-\tds->configure_vlan_while_not_filtering = false;\n-\n \treturn 0;\n }\n \n"
  },
  {
    "path": "target/linux/generic/backport-5.15/774-v5.16-03-net-dsa-rtl8366rb-Rewrite-weird-VLAN-filering-enable.patch",
    "content": "From 7028f54b620f8df344b18e46e4a78e266091ab45 Mon Sep 17 00:00:00 2001\nFrom: Linus Walleij <linus.walleij@linaro.org>\nDate: Sun, 26 Sep 2021 00:59:26 +0200\nSubject: [PATCH 03/11] net: dsa: rtl8366rb: Rewrite weird VLAN filering\n enablement\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nWhile we were defining one VLAN per port for isolating the ports\nthe port_vlan_filtering() callback was implemented to enable a\nVLAN on the port + 1. This function makes no sense, not only is\nit incomplete as it only enables the VLAN, it doesn't do what\nthe callback is supposed to do, which is to selectively enable\nand disable filtering on a certain port.\n\nImplement the correct callback: we have two registers dealing\nwith filtering on the RTL9366RB, so we implement an ASIC-specific\ncallback and implement filering using the register bit that makes\nthe switch drop frames if the port is not in the VLAN member set.\n\nThe DSA documentation Documentation/networking/switchdev.rst states:\n\n  When the bridge has VLAN filtering enabled and a PVID is not\n  configured on the ingress port, untagged and 802.1p tagged\n  packets must be dropped. When the bridge has VLAN filtering\n  enabled and a PVID exists on the ingress port, untagged and\n  priority-tagged packets must be accepted and forwarded according\n  to the bridge's port membership of the PVID VLAN. When the\n  bridge has VLAN filtering disabled, the presence/lack of a\n  PVID should not influence the packet forwarding decision.\n\nTo comply with this, we add two arrays of bool in the RTL8366RB\nstate that keeps track of if filtering and PVID is enabled or\nnot for each port. We then add code such that whenever filtering\nor PVID changes, we update the filter according to the\nspecification.\n\nCc: Vladimir Oltean <olteanv@gmail.com>\nCc: Mauri Sandberg <sandberg@mailfence.com>\nCc: Alvin Šipraga <alsi@bang-olufsen.dk>\nCc: Florian Fainelli <f.fainelli@gmail.com>\nCc: DENG Qingfang <dqfext@gmail.com>\nSigned-off-by: Linus Walleij <linus.walleij@linaro.org>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/dsa/realtek-smi-core.h |   2 -\n drivers/net/dsa/rtl8366.c          |  35 ----------\n drivers/net/dsa/rtl8366rb.c        | 102 +++++++++++++++++++++++++++--\n 3 files changed, 95 insertions(+), 44 deletions(-)\n\n--- a/drivers/net/dsa/realtek-smi-core.h\n+++ b/drivers/net/dsa/realtek-smi-core.h\n@@ -129,8 +129,6 @@ int rtl8366_set_pvid(struct realtek_smi\n int rtl8366_enable_vlan4k(struct realtek_smi *smi, bool enable);\n int rtl8366_enable_vlan(struct realtek_smi *smi, bool enable);\n int rtl8366_reset_vlan(struct realtek_smi *smi);\n-int rtl8366_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering,\n-\t\t\t   struct netlink_ext_ack *extack);\n int rtl8366_vlan_add(struct dsa_switch *ds, int port,\n \t\t     const struct switchdev_obj_port_vlan *vlan,\n \t\t     struct netlink_ext_ack *extack);\n--- a/drivers/net/dsa/rtl8366.c\n+++ b/drivers/net/dsa/rtl8366.c\n@@ -292,41 +292,6 @@ int rtl8366_reset_vlan(struct realtek_sm\n }\n EXPORT_SYMBOL_GPL(rtl8366_reset_vlan);\n \n-int rtl8366_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering,\n-\t\t\t   struct netlink_ext_ack *extack)\n-{\n-\tstruct realtek_smi *smi = ds->priv;\n-\tstruct rtl8366_vlan_4k vlan4k;\n-\tint ret;\n-\n-\t/* Use VLAN nr port + 1 since VLAN0 is not valid */\n-\tif (!smi->ops->is_vlan_valid(smi, port + 1))\n-\t\treturn -EINVAL;\n-\n-\tdev_info(smi->dev, \"%s filtering on port %d\\n\",\n-\t\t vlan_filtering ? \"enable\" : \"disable\",\n-\t\t port);\n-\n-\t/* TODO:\n-\t * The hardware support filter ID (FID) 0..7, I have no clue how to\n-\t * support this in the driver when the callback only says on/off.\n-\t */\n-\tret = smi->ops->get_vlan_4k(smi, port + 1, &vlan4k);\n-\tif (ret)\n-\t\treturn ret;\n-\n-\t/* Just set the filter to FID 1 for now then */\n-\tret = rtl8366_set_vlan(smi, port + 1,\n-\t\t\t       vlan4k.member,\n-\t\t\t       vlan4k.untag,\n-\t\t\t       1);\n-\tif (ret)\n-\t\treturn ret;\n-\n-\treturn 0;\n-}\n-EXPORT_SYMBOL_GPL(rtl8366_vlan_filtering);\n-\n int rtl8366_vlan_add(struct dsa_switch *ds, int port,\n \t\t     const struct switchdev_obj_port_vlan *vlan,\n \t\t     struct netlink_ext_ack *extack)\n--- a/drivers/net/dsa/rtl8366rb.c\n+++ b/drivers/net/dsa/rtl8366rb.c\n@@ -143,6 +143,21 @@\n #define RTL8366RB_PHY_NO_OFFSET\t\t\t9\n #define RTL8366RB_PHY_NO_MASK\t\t\t(0x1f << 9)\n \n+/* VLAN Ingress Control Register 1, one bit per port.\n+ * bit 0 .. 5 will make the switch drop ingress frames without\n+ * VID such as untagged or priority-tagged frames for respective\n+ * port.\n+ * bit 6 .. 11 will make the switch drop ingress frames carrying\n+ * a C-tag with VID != 0 for respective port.\n+ */\n+#define RTL8366RB_VLAN_INGRESS_CTRL1_REG\t0x037E\n+#define RTL8366RB_VLAN_INGRESS_CTRL1_DROP(port)\t(BIT((port)) | BIT((port) + 6))\n+\n+/* VLAN Ingress Control Register 2, one bit per port.\n+ * bit0 .. bit5 will make the switch drop all ingress frames with\n+ * a VLAN classification that does not include the port is in its\n+ * member set.\n+ */\n #define RTL8366RB_VLAN_INGRESS_CTRL2_REG\t0x037f\n \n /* LED control registers */\n@@ -321,9 +336,13 @@\n /**\n  * struct rtl8366rb - RTL8366RB-specific data\n  * @max_mtu: per-port max MTU setting\n+ * @pvid_enabled: if PVID is set for respective port\n+ * @vlan_filtering: if VLAN filtering is enabled for respective port\n  */\n struct rtl8366rb {\n \tunsigned int max_mtu[RTL8366RB_NUM_PORTS];\n+\tbool pvid_enabled[RTL8366RB_NUM_PORTS];\n+\tbool vlan_filtering[RTL8366RB_NUM_PORTS];\n };\n \n static struct rtl8366_mib_counter rtl8366rb_mib_counters[] = {\n@@ -933,11 +952,13 @@ static int rtl8366rb_setup(struct dsa_sw\n \tif (ret)\n \t\treturn ret;\n \n-\t/* Discard VLAN tagged packets if the port is not a member of\n-\t * the VLAN with which the packets is associated.\n-\t */\n+\t/* Accept all packets by default, we enable filtering on-demand */\n+\tret = regmap_write(smi->map, RTL8366RB_VLAN_INGRESS_CTRL1_REG,\n+\t\t\t   0);\n+\tif (ret)\n+\t\treturn ret;\n \tret = regmap_write(smi->map, RTL8366RB_VLAN_INGRESS_CTRL2_REG,\n-\t\t\t   RTL8366RB_PORT_ALL);\n+\t\t\t   0);\n \tif (ret)\n \t\treturn ret;\n \n@@ -1209,6 +1230,53 @@ rtl8366rb_port_bridge_leave(struct dsa_s\n \t\t\t   RTL8366RB_PORT_ISO_PORTS(port_bitmap), 0);\n }\n \n+/**\n+ * rtl8366rb_drop_untagged() - make the switch drop untagged and C-tagged frames\n+ * @smi: SMI state container\n+ * @port: the port to drop untagged and C-tagged frames on\n+ * @drop: whether to drop or pass untagged and C-tagged frames\n+ */\n+static int rtl8366rb_drop_untagged(struct realtek_smi *smi, int port, bool drop)\n+{\n+\treturn regmap_update_bits(smi->map, RTL8366RB_VLAN_INGRESS_CTRL1_REG,\n+\t\t\t\t  RTL8366RB_VLAN_INGRESS_CTRL1_DROP(port),\n+\t\t\t\t  drop ? RTL8366RB_VLAN_INGRESS_CTRL1_DROP(port) : 0);\n+}\n+\n+static int rtl8366rb_vlan_filtering(struct dsa_switch *ds, int port,\n+\t\t\t\t    bool vlan_filtering,\n+\t\t\t\t    struct netlink_ext_ack *extack)\n+{\n+\tstruct realtek_smi *smi = ds->priv;\n+\tstruct rtl8366rb *rb;\n+\tint ret;\n+\n+\trb = smi->chip_data;\n+\n+\tdev_dbg(smi->dev, \"port %d: %s VLAN filtering\\n\", port,\n+\t\tvlan_filtering ? \"enable\" : \"disable\");\n+\n+\t/* If the port is not in the member set, the frame will be dropped */\n+\tret = regmap_update_bits(smi->map, RTL8366RB_VLAN_INGRESS_CTRL2_REG,\n+\t\t\t\t BIT(port), vlan_filtering ? BIT(port) : 0);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\t/* Keep track if filtering is enabled on each port */\n+\trb->vlan_filtering[port] = vlan_filtering;\n+\n+\t/* If VLAN filtering is enabled and PVID is also enabled, we must\n+\t * not drop any untagged or C-tagged frames. If we turn off VLAN\n+\t * filtering on a port, we need ti accept any frames.\n+\t */\n+\tif (vlan_filtering)\n+\t\tret = rtl8366rb_drop_untagged(smi, port, !rb->pvid_enabled[port]);\n+\telse\n+\t\tret = rtl8366rb_drop_untagged(smi, port, false);\n+\n+\treturn ret;\n+}\n+\n static int rtl8366rb_change_mtu(struct dsa_switch *ds, int port, int new_mtu)\n {\n \tstruct realtek_smi *smi = ds->priv;\n@@ -1420,14 +1488,34 @@ static int rtl8366rb_get_mc_index(struct\n \n static int rtl8366rb_set_mc_index(struct realtek_smi *smi, int port, int index)\n {\n+\tstruct rtl8366rb *rb;\n+\tbool pvid_enabled;\n+\tint ret;\n+\n+\trb = smi->chip_data;\n+\tpvid_enabled = !!index;\n+\n \tif (port >= smi->num_ports || index >= RTL8366RB_NUM_VLANS)\n \t\treturn -EINVAL;\n \n-\treturn regmap_update_bits(smi->map, RTL8366RB_PORT_VLAN_CTRL_REG(port),\n+\tret = regmap_update_bits(smi->map, RTL8366RB_PORT_VLAN_CTRL_REG(port),\n \t\t\t\tRTL8366RB_PORT_VLAN_CTRL_MASK <<\n \t\t\t\t\tRTL8366RB_PORT_VLAN_CTRL_SHIFT(port),\n \t\t\t\t(index & RTL8366RB_PORT_VLAN_CTRL_MASK) <<\n \t\t\t\t\tRTL8366RB_PORT_VLAN_CTRL_SHIFT(port));\n+\tif (ret)\n+\t\treturn ret;\n+\n+\trb->pvid_enabled[port] = pvid_enabled;\n+\n+\t/* If VLAN filtering is enabled and PVID is also enabled, we must\n+\t * not drop any untagged or C-tagged frames. Make sure to update the\n+\t * filtering setting.\n+\t */\n+\tif (rb->vlan_filtering[port])\n+\t\tret = rtl8366rb_drop_untagged(smi, port, !pvid_enabled);\n+\n+\treturn ret;\n }\n \n static bool rtl8366rb_is_vlan_valid(struct realtek_smi *smi, unsigned int vlan)\n@@ -1437,7 +1525,7 @@ static bool rtl8366rb_is_vlan_valid(stru\n \tif (smi->vlan4k_enabled)\n \t\tmax = RTL8366RB_NUM_VIDS - 1;\n \n-\tif (vlan == 0 || vlan > max)\n+\tif (vlan > max)\n \t\treturn false;\n \n \treturn true;\n@@ -1594,7 +1682,7 @@ static const struct dsa_switch_ops rtl83\n \t.get_sset_count = rtl8366_get_sset_count,\n \t.port_bridge_join = rtl8366rb_port_bridge_join,\n \t.port_bridge_leave = rtl8366rb_port_bridge_leave,\n-\t.port_vlan_filtering = rtl8366_vlan_filtering,\n+\t.port_vlan_filtering = rtl8366rb_vlan_filtering,\n \t.port_vlan_add = rtl8366_vlan_add,\n \t.port_vlan_del = rtl8366_vlan_del,\n \t.port_enable = rtl8366rb_port_enable,\n"
  },
  {
    "path": "target/linux/generic/backport-5.15/774-v5.16-06-net-dsa-rtl8366-Drop-and-depromote-pointless-prints.patch",
    "content": "From ddb59a5dc42714999c335dab4bf256125ba3120c Mon Sep 17 00:00:00 2001\nFrom: Linus Walleij <linus.walleij@linaro.org>\nDate: Sun, 26 Sep 2021 00:59:29 +0200\nSubject: [PATCH 06/11] net: dsa: rtl8366: Drop and depromote pointless prints\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nWe don't need a message for every VLAN association, dbg\nis fine. The message about adding the DSA or CPU\nport to a VLAN is directly misleading, this is perfectly\nfine.\n\nCc: Vladimir Oltean <olteanv@gmail.com>\nCc: Mauri Sandberg <sandberg@mailfence.com>\nCc: DENG Qingfang <dqfext@gmail.com>\nReviewed-by: Alvin Šipraga <alsi@bang-olufsen.dk>\nReviewed-by: Florian Fainelli <f.fainelli@gmail.com>\nSigned-off-by: Linus Walleij <linus.walleij@linaro.org>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/dsa/rtl8366.c | 11 ++++-------\n 1 file changed, 4 insertions(+), 7 deletions(-)\n\n--- a/drivers/net/dsa/rtl8366.c\n+++ b/drivers/net/dsa/rtl8366.c\n@@ -318,12 +318,9 @@ int rtl8366_vlan_add(struct dsa_switch *\n \t\treturn ret;\n \t}\n \n-\tdev_info(smi->dev, \"add VLAN %d on port %d, %s, %s\\n\",\n-\t\t vlan->vid, port, untagged ? \"untagged\" : \"tagged\",\n-\t\t pvid ? \" PVID\" : \"no PVID\");\n-\n-\tif (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))\n-\t\tdev_err(smi->dev, \"port is DSA or CPU port\\n\");\n+\tdev_dbg(smi->dev, \"add VLAN %d on port %d, %s, %s\\n\",\n+\t\tvlan->vid, port, untagged ? \"untagged\" : \"tagged\",\n+\t\tpvid ? \"PVID\" : \"no PVID\");\n \n \tmember |= BIT(port);\n \n@@ -356,7 +353,7 @@ int rtl8366_vlan_del(struct dsa_switch *\n \tstruct realtek_smi *smi = ds->priv;\n \tint ret, i;\n \n-\tdev_info(smi->dev, \"del VLAN %04x on port %d\\n\", vlan->vid, port);\n+\tdev_dbg(smi->dev, \"del VLAN %d on port %d\\n\", vlan->vid, port);\n \n \tfor (i = 0; i < smi->num_vlan_mc; i++) {\n \t\tstruct rtl8366_vlan_mc vlanmc;\n"
  },
  {
    "path": "target/linux/generic/backport-5.15/774-v5.16-07-net-dsa-rtl8366rb-Use-core-filtering-tracking.patch",
    "content": "From 5c9b66f3c8a3f72fa2a58e89a57c6d7afd550bf0 Mon Sep 17 00:00:00 2001\nFrom: Linus Walleij <linus.walleij@linaro.org>\nDate: Wed, 29 Sep 2021 13:23:22 +0200\nSubject: [PATCH 07/11] net: dsa: rtl8366rb: Use core filtering tracking\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nWe added a state variable to track whether a certain port\nwas VLAN filtering or not, but we can just inquire the DSA\ncore about this.\n\nCc: Vladimir Oltean <olteanv@gmail.com>\nCc: Mauri Sandberg <sandberg@mailfence.com>\nCc: DENG Qingfang <dqfext@gmail.com>\nCc: Alvin Šipraga <alsi@bang-olufsen.dk>\nCc: Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>\nSigned-off-by: Linus Walleij <linus.walleij@linaro.org>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/dsa/rtl8366rb.c | 9 ++-------\n 1 file changed, 2 insertions(+), 7 deletions(-)\n\n--- a/drivers/net/dsa/rtl8366rb.c\n+++ b/drivers/net/dsa/rtl8366rb.c\n@@ -337,12 +337,10 @@\n  * struct rtl8366rb - RTL8366RB-specific data\n  * @max_mtu: per-port max MTU setting\n  * @pvid_enabled: if PVID is set for respective port\n- * @vlan_filtering: if VLAN filtering is enabled for respective port\n  */\n struct rtl8366rb {\n \tunsigned int max_mtu[RTL8366RB_NUM_PORTS];\n \tbool pvid_enabled[RTL8366RB_NUM_PORTS];\n-\tbool vlan_filtering[RTL8366RB_NUM_PORTS];\n };\n \n static struct rtl8366_mib_counter rtl8366rb_mib_counters[] = {\n@@ -1262,12 +1260,9 @@ static int rtl8366rb_vlan_filtering(stru\n \tif (ret)\n \t\treturn ret;\n \n-\t/* Keep track if filtering is enabled on each port */\n-\trb->vlan_filtering[port] = vlan_filtering;\n-\n \t/* If VLAN filtering is enabled and PVID is also enabled, we must\n \t * not drop any untagged or C-tagged frames. If we turn off VLAN\n-\t * filtering on a port, we need ti accept any frames.\n+\t * filtering on a port, we need to accept any frames.\n \t */\n \tif (vlan_filtering)\n \t\tret = rtl8366rb_drop_untagged(smi, port, !rb->pvid_enabled[port]);\n@@ -1512,7 +1507,7 @@ static int rtl8366rb_set_mc_index(struct\n \t * not drop any untagged or C-tagged frames. Make sure to update the\n \t * filtering setting.\n \t */\n-\tif (rb->vlan_filtering[port])\n+\tif (dsa_port_is_vlan_filtering(dsa_to_port(smi->ds, port)))\n \t\tret = rtl8366rb_drop_untagged(smi, port, !pvid_enabled);\n \n \treturn ret;\n"
  },
  {
    "path": "target/linux/generic/backport-5.15/774-v5.16-08-net-dsa-rtl8366rb-Support-disabling-learning.patch",
    "content": "From 831a3d26bea0d14f8563eecf96def660a74a3000 Mon Sep 17 00:00:00 2001\nFrom: Linus Walleij <linus.walleij@linaro.org>\nDate: Tue, 5 Oct 2021 21:47:02 +0200\nSubject: [PATCH 08/11] net: dsa: rtl8366rb: Support disabling learning\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nThe RTL8366RB hardware supports disabling learning per-port\nso let's make use of this feature. Rename some unfortunately\nnamed registers in the process.\n\nSuggested-by: Vladimir Oltean <olteanv@gmail.com>\nCc: Alvin Šipraga <alsi@bang-olufsen.dk>\nCc: Mauri Sandberg <sandberg@mailfence.com>\nCc: Florian Fainelli <f.fainelli@gmail.com>\nCc: DENG Qingfang <dqfext@gmail.com>\nReviewed-by: Vladimir Oltean <olteanv@gmail.com>\nSigned-off-by: Linus Walleij <linus.walleij@linaro.org>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/dsa/rtl8366rb.c | 50 ++++++++++++++++++++++++++++++++-----\n 1 file changed, 44 insertions(+), 6 deletions(-)\n\n--- a/drivers/net/dsa/rtl8366rb.c\n+++ b/drivers/net/dsa/rtl8366rb.c\n@@ -14,6 +14,7 @@\n \n #include <linux/bitops.h>\n #include <linux/etherdevice.h>\n+#include <linux/if_bridge.h>\n #include <linux/interrupt.h>\n #include <linux/irqdomain.h>\n #include <linux/irqchip/chained_irq.h>\n@@ -42,9 +43,12 @@\n /* Port Enable Control register */\n #define RTL8366RB_PECR\t\t\t\t0x0001\n \n-/* Switch Security Control registers */\n-#define RTL8366RB_SSCR0\t\t\t\t0x0002\n-#define RTL8366RB_SSCR1\t\t\t\t0x0003\n+/* Switch per-port learning disablement register */\n+#define RTL8366RB_PORT_LEARNDIS_CTRL\t\t0x0002\n+\n+/* Security control, actually aging register */\n+#define RTL8366RB_SECURITY_CTRL\t\t\t0x0003\n+\n #define RTL8366RB_SSCR2\t\t\t\t0x0004\n #define RTL8366RB_SSCR2_DROP_UNKNOWN_DA\t\tBIT(0)\n \n@@ -927,13 +931,14 @@ static int rtl8366rb_setup(struct dsa_sw\n \t\t/* layer 2 size, see rtl8366rb_change_mtu() */\n \t\trb->max_mtu[i] = 1532;\n \n-\t/* Enable learning for all ports */\n-\tret = regmap_write(smi->map, RTL8366RB_SSCR0, 0);\n+\t/* Disable learning for all ports */\n+\tret = regmap_write(smi->map, RTL8366RB_PORT_LEARNDIS_CTRL,\n+\t\t\t   RTL8366RB_PORT_ALL);\n \tif (ret)\n \t\treturn ret;\n \n \t/* Enable auto ageing for all ports */\n-\tret = regmap_write(smi->map, RTL8366RB_SSCR1, 0);\n+\tret = regmap_write(smi->map, RTL8366RB_SECURITY_CTRL, 0);\n \tif (ret)\n \t\treturn ret;\n \n@@ -1272,6 +1277,37 @@ static int rtl8366rb_vlan_filtering(stru\n \treturn ret;\n }\n \n+static int\n+rtl8366rb_port_pre_bridge_flags(struct dsa_switch *ds, int port,\n+\t\t\t\tstruct switchdev_brport_flags flags,\n+\t\t\t\tstruct netlink_ext_ack *extack)\n+{\n+\t/* We support enabling/disabling learning */\n+\tif (flags.mask & ~(BR_LEARNING))\n+\t\treturn -EINVAL;\n+\n+\treturn 0;\n+}\n+\n+static int\n+rtl8366rb_port_bridge_flags(struct dsa_switch *ds, int port,\n+\t\t\t    struct switchdev_brport_flags flags,\n+\t\t\t    struct netlink_ext_ack *extack)\n+{\n+\tstruct realtek_smi *smi = ds->priv;\n+\tint ret;\n+\n+\tif (flags.mask & BR_LEARNING) {\n+\t\tret = regmap_update_bits(smi->map, RTL8366RB_PORT_LEARNDIS_CTRL,\n+\t\t\t\t\t BIT(port),\n+\t\t\t\t\t (flags.val & BR_LEARNING) ? 0 : BIT(port));\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\t}\n+\n+\treturn 0;\n+}\n+\n static int rtl8366rb_change_mtu(struct dsa_switch *ds, int port, int new_mtu)\n {\n \tstruct realtek_smi *smi = ds->priv;\n@@ -1682,6 +1718,8 @@ static const struct dsa_switch_ops rtl83\n \t.port_vlan_del = rtl8366_vlan_del,\n \t.port_enable = rtl8366rb_port_enable,\n \t.port_disable = rtl8366rb_port_disable,\n+\t.port_pre_bridge_flags = rtl8366rb_port_pre_bridge_flags,\n+\t.port_bridge_flags = rtl8366rb_port_bridge_flags,\n \t.port_change_mtu = rtl8366rb_change_mtu,\n \t.port_max_mtu = rtl8366rb_max_mtu,\n };\n"
  },
  {
    "path": "target/linux/generic/backport-5.15/774-v5.16-09-net-dsa-rtl8366rb-Support-fast-aging.patch",
    "content": "From 8eb13420eb9ab4a4e2ebd612bf5dc9dba0039236 Mon Sep 17 00:00:00 2001\nFrom: Linus Walleij <linus.walleij@linaro.org>\nDate: Tue, 5 Oct 2021 21:47:03 +0200\nSubject: [PATCH 09/11] net: dsa: rtl8366rb: Support fast aging\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nThis implements fast aging per-port using the special \"security\"\nregister, which will flush any learned L2 LUT entries on a port.\n\nThe vendor API just enabled setting and clearing this bit, so\nwe set it to age out any entries on the port and then we clear\nit again.\n\nSuggested-by: Vladimir Oltean <olteanv@gmail.com>\nCc: Mauri Sandberg <sandberg@mailfence.com>\nCc: DENG Qingfang <dqfext@gmail.com>\nCc: Florian Fainelli <f.fainelli@gmail.com>\nReviewed-by: Alvin Šipraga <alsi@bang-olufsen.dk>\nSigned-off-by: Linus Walleij <linus.walleij@linaro.org>\nReviewed-by: Vladimir Oltean <olteanv@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/dsa/rtl8366rb.c | 14 ++++++++++++++\n 1 file changed, 14 insertions(+)\n\n--- a/drivers/net/dsa/rtl8366rb.c\n+++ b/drivers/net/dsa/rtl8366rb.c\n@@ -1308,6 +1308,19 @@ rtl8366rb_port_bridge_flags(struct dsa_s\n \treturn 0;\n }\n \n+static void\n+rtl8366rb_port_fast_age(struct dsa_switch *ds, int port)\n+{\n+\tstruct realtek_smi *smi = ds->priv;\n+\n+\t/* This will age out any learned L2 entries */\n+\tregmap_update_bits(smi->map, RTL8366RB_SECURITY_CTRL,\n+\t\t\t   BIT(port), BIT(port));\n+\t/* Restore the normal state of things */\n+\tregmap_update_bits(smi->map, RTL8366RB_SECURITY_CTRL,\n+\t\t\t   BIT(port), 0);\n+}\n+\n static int rtl8366rb_change_mtu(struct dsa_switch *ds, int port, int new_mtu)\n {\n \tstruct realtek_smi *smi = ds->priv;\n@@ -1720,6 +1733,7 @@ static const struct dsa_switch_ops rtl83\n \t.port_disable = rtl8366rb_port_disable,\n \t.port_pre_bridge_flags = rtl8366rb_port_pre_bridge_flags,\n \t.port_bridge_flags = rtl8366rb_port_bridge_flags,\n+\t.port_fast_age = rtl8366rb_port_fast_age,\n \t.port_change_mtu = rtl8366rb_change_mtu,\n \t.port_max_mtu = rtl8366rb_max_mtu,\n };\n"
  },
  {
    "path": "target/linux/generic/backport-5.15/774-v5.16-10-net-dsa-rtl8366rb-Support-setting-STP-state.patch",
    "content": "From 90c855471a89d3e05ecf5b6464bd04abf2c83b70 Mon Sep 17 00:00:00 2001\nFrom: Linus Walleij <linus.walleij@linaro.org>\nDate: Tue, 5 Oct 2021 21:47:04 +0200\nSubject: [PATCH 10/11] net: dsa: rtl8366rb: Support setting STP state\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nThis adds support for setting the STP state to the RTL8366RB\nDSA switch. This rids the following message from the kernel on\ne.g. OpenWrt:\n\nDSA: failed to set STP state 3 (-95)\n\nSince the RTL8366RB has one STP state register per FID with\ntwo bit per port in each, we simply loop over all the FIDs\nand set the state on all of them.\n\nCc: Vladimir Oltean <olteanv@gmail.com>\nCc: Alvin Šipraga <alsi@bang-olufsen.dk>\nCc: Mauri Sandberg <sandberg@mailfence.com>\nCc: DENG Qingfang <dqfext@gmail.com>\nSigned-off-by: Linus Walleij <linus.walleij@linaro.org>\nReviewed-by: Vladimir Oltean <olteanv@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/dsa/rtl8366rb.c | 48 +++++++++++++++++++++++++++++++++++++\n 1 file changed, 48 insertions(+)\n\n--- a/drivers/net/dsa/rtl8366rb.c\n+++ b/drivers/net/dsa/rtl8366rb.c\n@@ -110,6 +110,18 @@\n \n #define RTL8366RB_POWER_SAVING_REG\t0x0021\n \n+/* Spanning tree status (STP) control, two bits per port per FID */\n+#define RTL8366RB_STP_STATE_BASE\t0x0050 /* 0x0050..0x0057 */\n+#define RTL8366RB_STP_STATE_DISABLED\t0x0\n+#define RTL8366RB_STP_STATE_BLOCKING\t0x1\n+#define RTL8366RB_STP_STATE_LEARNING\t0x2\n+#define RTL8366RB_STP_STATE_FORWARDING\t0x3\n+#define RTL8366RB_STP_MASK\t\tGENMASK(1, 0)\n+#define RTL8366RB_STP_STATE(port, state) \\\n+\t((state) << ((port) * 2))\n+#define RTL8366RB_STP_STATE_MASK(port) \\\n+\tRTL8366RB_STP_STATE((port), RTL8366RB_STP_MASK)\n+\n /* CPU port control reg */\n #define RTL8368RB_CPU_CTRL_REG\t\t0x0061\n #define RTL8368RB_CPU_PORTS_MSK\t\t0x00FF\n@@ -234,6 +246,7 @@\n #define RTL8366RB_NUM_LEDGROUPS\t\t4\n #define RTL8366RB_NUM_VIDS\t\t4096\n #define RTL8366RB_PRIORITYMAX\t\t7\n+#define RTL8366RB_NUM_FIDS\t\t8\n #define RTL8366RB_FIDMAX\t\t7\n \n #define RTL8366RB_PORT_1\t\tBIT(0) /* In userspace port 0 */\n@@ -1309,6 +1322,40 @@ rtl8366rb_port_bridge_flags(struct dsa_s\n }\n \n static void\n+rtl8366rb_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)\n+{\n+\tstruct realtek_smi *smi = ds->priv;\n+\tu32 val;\n+\tint i;\n+\n+\tswitch (state) {\n+\tcase BR_STATE_DISABLED:\n+\t\tval = RTL8366RB_STP_STATE_DISABLED;\n+\t\tbreak;\n+\tcase BR_STATE_BLOCKING:\n+\tcase BR_STATE_LISTENING:\n+\t\tval = RTL8366RB_STP_STATE_BLOCKING;\n+\t\tbreak;\n+\tcase BR_STATE_LEARNING:\n+\t\tval = RTL8366RB_STP_STATE_LEARNING;\n+\t\tbreak;\n+\tcase BR_STATE_FORWARDING:\n+\t\tval = RTL8366RB_STP_STATE_FORWARDING;\n+\t\tbreak;\n+\tdefault:\n+\t\tdev_err(smi->dev, \"unknown bridge state requested\\n\");\n+\t\treturn;\n+\t};\n+\n+\t/* Set the same status for the port on all the FIDs */\n+\tfor (i = 0; i < RTL8366RB_NUM_FIDS; i++) {\n+\t\tregmap_update_bits(smi->map, RTL8366RB_STP_STATE_BASE + i,\n+\t\t\t\t   RTL8366RB_STP_STATE_MASK(port),\n+\t\t\t\t   RTL8366RB_STP_STATE(port, val));\n+\t}\n+}\n+\n+static void\n rtl8366rb_port_fast_age(struct dsa_switch *ds, int port)\n {\n \tstruct realtek_smi *smi = ds->priv;\n@@ -1733,6 +1780,7 @@ static const struct dsa_switch_ops rtl83\n \t.port_disable = rtl8366rb_port_disable,\n \t.port_pre_bridge_flags = rtl8366rb_port_pre_bridge_flags,\n \t.port_bridge_flags = rtl8366rb_port_bridge_flags,\n+\t.port_stp_state_set = rtl8366rb_port_stp_state_set,\n \t.port_fast_age = rtl8366rb_port_fast_age,\n \t.port_change_mtu = rtl8366rb_change_mtu,\n \t.port_max_mtu = rtl8366rb_max_mtu,\n"
  },
  {
    "path": "target/linux/generic/backport-5.15/850-v5.17-0001-PCI-pci-bridge-emul-Add-description-for-class_revisi.patch",
    "content": "From 9319230ac147067652b58fe849ffe0ceec098665 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>\nDate: Tue, 30 Nov 2021 18:29:03 +0100\nSubject: [PATCH] PCI: pci-bridge-emul: Add description for class_revision\n field\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nThe current assignment to the class_revision member\n\n  class_revision |= cpu_to_le32(PCI_CLASS_BRIDGE_PCI << 16);\n\ncan make the reader think that class is at high 16 bits of the member and\nrevision at low 16 bits.\n\nIn reality, class is at high 24 bits, but the class for PCI Bridge Normal\nDecode is PCI_CLASS_BRIDGE_PCI << 8.\n\nChange the assignment and add a comment to make this clearer.\n\nLink: https://lore.kernel.org/r/20211130172913.9727-2-kabel@kernel.org\nSigned-off-by: Pali Rohár <pali@kernel.org>\nSigned-off-by: Marek Behún <kabel@kernel.org>\nSigned-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>\n---\n drivers/pci/pci-bridge-emul.c | 6 +++++-\n 1 file changed, 5 insertions(+), 1 deletion(-)\n\n--- a/drivers/pci/pci-bridge-emul.c\n+++ b/drivers/pci/pci-bridge-emul.c\n@@ -284,7 +284,11 @@ int pci_bridge_emul_init(struct pci_brid\n {\n \tBUILD_BUG_ON(sizeof(bridge->conf) != PCI_BRIDGE_CONF_END);\n \n-\tbridge->conf.class_revision |= cpu_to_le32(PCI_CLASS_BRIDGE_PCI << 16);\n+\t/*\n+\t * class_revision: Class is high 24 bits and revision is low 8 bit of this member,\n+\t * while class for PCI Bridge Normal Decode has the 24-bit value: PCI_CLASS_BRIDGE_PCI << 8\n+\t */\n+\tbridge->conf.class_revision |= cpu_to_le32((PCI_CLASS_BRIDGE_PCI << 8) << 8);\n \tbridge->conf.header_type = PCI_HEADER_TYPE_BRIDGE;\n \tbridge->conf.cache_line_size = 0x10;\n \tbridge->conf.status = cpu_to_le16(PCI_STATUS_CAP_LIST);\n"
  },
  {
    "path": "target/linux/generic/backport-5.15/850-v5.17-0002-PCI-pci-bridge-emul-Add-definitions-for-missing-capa.patch",
    "content": "From 8ea673a8b30b4a32516b8adabb15e2a68ff02ec8 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>\nDate: Tue, 30 Nov 2021 18:29:04 +0100\nSubject: [PATCH] PCI: pci-bridge-emul: Add definitions for missing\n capabilities registers\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\npci-bridge-emul driver already allocates buffer for capabilities up to the\nPCI_EXP_SLTSTA2 register, but does not define bit access behavior for these\nregisters. Add these missing definitions.\n\nLink: https://lore.kernel.org/r/20211130172913.9727-3-kabel@kernel.org\nSigned-off-by: Pali Rohár <pali@kernel.org>\nSigned-off-by: Marek Behún <kabel@kernel.org>\nSigned-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>\n---\n drivers/pci/pci-bridge-emul.c | 43 +++++++++++++++++++++++++++++++++++\n 1 file changed, 43 insertions(+)\n\n--- a/drivers/pci/pci-bridge-emul.c\n+++ b/drivers/pci/pci-bridge-emul.c\n@@ -270,6 +270,49 @@ struct pci_bridge_reg_behavior pcie_cap_\n \t\t.ro = GENMASK(15, 0) | PCI_EXP_RTSTA_PENDING,\n \t\t.w1c = PCI_EXP_RTSTA_PME,\n \t},\n+\n+\t[PCI_EXP_DEVCAP2 / 4] = {\n+\t\t/*\n+\t\t * Device capabilities 2 register has reserved bits [30:27].\n+\t\t * Also bits [26:24] are reserved for non-upstream ports.\n+\t\t */\n+\t\t.ro = BIT(31) | GENMASK(23, 0),\n+\t},\n+\n+\t[PCI_EXP_DEVCTL2 / 4] = {\n+\t\t/*\n+\t\t * Device control 2 register is RW. Bit 11 is reserved for\n+\t\t * non-upstream ports.\n+\t\t *\n+\t\t * Device status 2 register is reserved.\n+\t\t */\n+\t\t.rw = GENMASK(15, 12) | GENMASK(10, 0),\n+\t},\n+\n+\t[PCI_EXP_LNKCAP2 / 4] = {\n+\t\t/* Link capabilities 2 register has reserved bits [30:25] and 0. */\n+\t\t.ro = BIT(31) | GENMASK(24, 1),\n+\t},\n+\n+\t[PCI_EXP_LNKCTL2 / 4] = {\n+\t\t/*\n+\t\t * Link control 2 register is RW.\n+\t\t *\n+\t\t * Link status 2 register has bits 5, 15 W1C;\n+\t\t * bits 10, 11 reserved and others are RO.\n+\t\t */\n+\t\t.rw = GENMASK(15, 0),\n+\t\t.w1c = (BIT(15) | BIT(5)) << 16,\n+\t\t.ro = (GENMASK(14, 12) | GENMASK(9, 6) | GENMASK(4, 0)) << 16,\n+\t},\n+\n+\t[PCI_EXP_SLTCAP2 / 4] = {\n+\t\t/* Slot capabilities 2 register is reserved. */\n+\t},\n+\n+\t[PCI_EXP_SLTCTL2 / 4] = {\n+\t\t/* Both Slot control 2 and Slot status 2 registers are reserved. */\n+\t},\n };\n \n /*\n"
  },
  {
    "path": "target/linux/generic/backport-5.15/850-v5.17-0003-PCI-aardvark-Add-support-for-DEVCAP2-DEVCTL2-LNKCAP2.patch",
    "content": "From 1d3e170344dff2cef8827db6c09909b78cbc11d7 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>\nDate: Tue, 30 Nov 2021 18:29:05 +0100\nSubject: [PATCH] PCI: aardvark: Add support for DEVCAP2, DEVCTL2, LNKCAP2 and\n LNKCTL2 registers on emulated bridge\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nPCI aardvark hardware supports access to DEVCAP2, DEVCTL2, LNKCAP2 and\nLNKCTL2 configuration registers of PCIe core via PCIE_CORE_PCIEXP_CAP.\nExport them via emulated software root bridge.\n\nLink: https://lore.kernel.org/r/20211130172913.9727-4-kabel@kernel.org\nSigned-off-by: Pali Rohár <pali@kernel.org>\nSigned-off-by: Marek Behún <kabel@kernel.org>\nSigned-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>\n---\n drivers/pci/controller/pci-aardvark.c | 15 +++++++++++----\n 1 file changed, 11 insertions(+), 4 deletions(-)\n\n--- a/drivers/pci/controller/pci-aardvark.c\n+++ b/drivers/pci/controller/pci-aardvark.c\n@@ -876,8 +876,13 @@ advk_pci_bridge_emul_pcie_conf_read(stru\n \n \tcase PCI_EXP_DEVCAP:\n \tcase PCI_EXP_DEVCTL:\n+\tcase PCI_EXP_DEVCAP2:\n+\tcase PCI_EXP_DEVCTL2:\n+\tcase PCI_EXP_LNKCAP2:\n+\tcase PCI_EXP_LNKCTL2:\n \t\t*value = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + reg);\n \t\treturn PCI_BRIDGE_EMUL_HANDLED;\n+\n \tdefault:\n \t\treturn PCI_BRIDGE_EMUL_NOT_HANDLED;\n \t}\n@@ -891,10 +896,6 @@ advk_pci_bridge_emul_pcie_conf_write(str\n \tstruct advk_pcie *pcie = bridge->data;\n \n \tswitch (reg) {\n-\tcase PCI_EXP_DEVCTL:\n-\t\tadvk_writel(pcie, new, PCIE_CORE_PCIEXP_CAP + reg);\n-\t\tbreak;\n-\n \tcase PCI_EXP_LNKCTL:\n \t\tadvk_writel(pcie, new, PCIE_CORE_PCIEXP_CAP + reg);\n \t\tif (new & PCI_EXP_LNKCTL_RL)\n@@ -916,6 +917,12 @@ advk_pci_bridge_emul_pcie_conf_write(str\n \t\tadvk_writel(pcie, new, PCIE_ISR0_REG);\n \t\tbreak;\n \n+\tcase PCI_EXP_DEVCTL:\n+\tcase PCI_EXP_DEVCTL2:\n+\tcase PCI_EXP_LNKCTL2:\n+\t\tadvk_writel(pcie, new, PCIE_CORE_PCIEXP_CAP + reg);\n+\t\tbreak;\n+\n \tdefault:\n \t\tbreak;\n \t}\n"
  },
  {
    "path": "target/linux/generic/backport-5.15/850-v5.17-0004-PCI-aardvark-Clear-all-MSIs-at-setup.patch",
    "content": "From 7d8dc1f7cd007a7ce94c5b4c20d63a8b8d6d7751 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>\nDate: Tue, 30 Nov 2021 18:29:06 +0100\nSubject: [PATCH] PCI: aardvark: Clear all MSIs at setup\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nWe already clear all the other interrupts (ISR0, ISR1, HOST_CTRL_INT).\n\nDefine a new macro PCIE_MSI_ALL_MASK and do the same clearing for MSIs,\nto ensure that we don't start receiving spurious interrupts.\n\nUse this new mask in advk_pcie_handle_msi();\n\nLink: https://lore.kernel.org/r/20211130172913.9727-5-kabel@kernel.org\nSigned-off-by: Pali Rohár <pali@kernel.org>\nSigned-off-by: Marek Behún <kabel@kernel.org>\nSigned-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>\n---\n drivers/pci/controller/pci-aardvark.c | 6 ++++--\n 1 file changed, 4 insertions(+), 2 deletions(-)\n\n--- a/drivers/pci/controller/pci-aardvark.c\n+++ b/drivers/pci/controller/pci-aardvark.c\n@@ -115,6 +115,7 @@\n #define PCIE_MSI_ADDR_HIGH_REG\t\t\t(CONTROL_BASE_ADDR + 0x54)\n #define PCIE_MSI_STATUS_REG\t\t\t(CONTROL_BASE_ADDR + 0x58)\n #define PCIE_MSI_MASK_REG\t\t\t(CONTROL_BASE_ADDR + 0x5C)\n+#define     PCIE_MSI_ALL_MASK\t\t\tGENMASK(31, 0)\n #define PCIE_MSI_PAYLOAD_REG\t\t\t(CONTROL_BASE_ADDR + 0x9C)\n #define     PCIE_MSI_DATA_MASK\t\t\tGENMASK(15, 0)\n \n@@ -570,6 +571,7 @@ static void advk_pcie_setup_hw(struct ad\n \tadvk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);\n \n \t/* Clear all interrupts */\n+\tadvk_writel(pcie, PCIE_MSI_ALL_MASK, PCIE_MSI_STATUS_REG);\n \tadvk_writel(pcie, PCIE_ISR0_ALL_MASK, PCIE_ISR0_REG);\n \tadvk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_REG);\n \tadvk_writel(pcie, PCIE_IRQ_ALL_MASK, HOST_CTRL_INT_STATUS_REG);\n@@ -582,7 +584,7 @@ static void advk_pcie_setup_hw(struct ad\n \tadvk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_MASK_REG);\n \n \t/* Unmask all MSIs */\n-\tadvk_writel(pcie, 0, PCIE_MSI_MASK_REG);\n+\tadvk_writel(pcie, ~(u32)PCIE_MSI_ALL_MASK, PCIE_MSI_MASK_REG);\n \n \t/* Enable summary interrupt for GIC SPI source */\n \treg = PCIE_IRQ_ALL_MASK & (~PCIE_IRQ_ENABLE_INTS_MASK);\n@@ -1389,7 +1391,7 @@ static void advk_pcie_handle_msi(struct\n \n \tmsi_mask = advk_readl(pcie, PCIE_MSI_MASK_REG);\n \tmsi_val = advk_readl(pcie, PCIE_MSI_STATUS_REG);\n-\tmsi_status = msi_val & ~msi_mask;\n+\tmsi_status = msi_val & ((~msi_mask) & PCIE_MSI_ALL_MASK);\n \n \tfor (msi_idx = 0; msi_idx < MSI_IRQ_NUM; msi_idx++) {\n \t\tif (!(BIT(msi_idx) & msi_status))\n"
  },
  {
    "path": "target/linux/generic/backport-5.15/850-v5.17-0005-PCI-aardvark-Comment-actions-in-driver-remove-method.patch",
    "content": "From a4ca7948e1d47275f8f3e5023243440c40561916 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>\nDate: Tue, 30 Nov 2021 18:29:07 +0100\nSubject: [PATCH] PCI: aardvark: Comment actions in driver remove method\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nAdd two more comments into the advk_pcie_remove() method.\n\nLink: https://lore.kernel.org/r/20211130172913.9727-6-kabel@kernel.org\nSigned-off-by: Pali Rohár <pali@kernel.org>\nSigned-off-by: Marek Behún <kabel@kernel.org>\nSigned-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>\n---\n drivers/pci/controller/pci-aardvark.c | 2 ++\n 1 file changed, 2 insertions(+)\n\n--- a/drivers/pci/controller/pci-aardvark.c\n+++ b/drivers/pci/controller/pci-aardvark.c\n@@ -1681,11 +1681,13 @@ static int advk_pcie_remove(struct platf\n \tstruct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie);\n \tint i;\n \n+\t/* Remove PCI bus with all devices */\n \tpci_lock_rescan_remove();\n \tpci_stop_root_bus(bridge->bus);\n \tpci_remove_root_bus(bridge->bus);\n \tpci_unlock_rescan_remove();\n \n+\t/* Remove IRQ domains */\n \tadvk_pcie_remove_msi_irq_domain(pcie);\n \tadvk_pcie_remove_irq_domain(pcie);\n \n"
  },
  {
    "path": "target/linux/generic/backport-5.15/850-v5.17-0006-PCI-aardvark-Disable-bus-mastering-when-unbinding-dr.patch",
    "content": "From a46f2f6dd4093438d9615dfbf5c0fea2a9835dba Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>\nDate: Tue, 30 Nov 2021 18:29:08 +0100\nSubject: [PATCH] PCI: aardvark: Disable bus mastering when unbinding driver\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nEnsure that after driver unbind PCIe cards are not able to forward\nmemory and I/O requests in the upstream direction.\n\nLink: https://lore.kernel.org/r/20211130172913.9727-7-kabel@kernel.org\nSigned-off-by: Pali Rohár <pali@kernel.org>\nSigned-off-by: Marek Behún <kabel@kernel.org>\nSigned-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>\n---\n drivers/pci/controller/pci-aardvark.c | 6 ++++++\n 1 file changed, 6 insertions(+)\n\n--- a/drivers/pci/controller/pci-aardvark.c\n+++ b/drivers/pci/controller/pci-aardvark.c\n@@ -1679,6 +1679,7 @@ static int advk_pcie_remove(struct platf\n {\n \tstruct advk_pcie *pcie = platform_get_drvdata(pdev);\n \tstruct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie);\n+\tu32 val;\n \tint i;\n \n \t/* Remove PCI bus with all devices */\n@@ -1687,6 +1688,11 @@ static int advk_pcie_remove(struct platf\n \tpci_remove_root_bus(bridge->bus);\n \tpci_unlock_rescan_remove();\n \n+\t/* Disable Root Bridge I/O space, memory space and bus mastering */\n+\tval = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG);\n+\tval &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);\n+\tadvk_writel(pcie, val, PCIE_CORE_CMD_STATUS_REG);\n+\n \t/* Remove IRQ domains */\n \tadvk_pcie_remove_msi_irq_domain(pcie);\n \tadvk_pcie_remove_irq_domain(pcie);\n"
  },
  {
    "path": "target/linux/generic/backport-5.15/850-v5.17-0007-PCI-aardvark-Mask-all-interrupts-when-unbinding-driv.patch",
    "content": "From 13bcdf07cb2ecff5d45d2c141df2539b15211448 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>\nDate: Tue, 30 Nov 2021 18:29:09 +0100\nSubject: [PATCH] PCI: aardvark: Mask all interrupts when unbinding driver\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nEnsure that no interrupt can be triggered after driver unbind.\n\nLink: https://lore.kernel.org/r/20211130172913.9727-8-kabel@kernel.org\nSigned-off-by: Pali Rohár <pali@kernel.org>\nSigned-off-by: Marek Behún <kabel@kernel.org>\nSigned-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>\n---\n drivers/pci/controller/pci-aardvark.c | 21 +++++++++++++++++++++\n 1 file changed, 21 insertions(+)\n\n--- a/drivers/pci/controller/pci-aardvark.c\n+++ b/drivers/pci/controller/pci-aardvark.c\n@@ -1693,6 +1693,27 @@ static int advk_pcie_remove(struct platf\n \tval &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);\n \tadvk_writel(pcie, val, PCIE_CORE_CMD_STATUS_REG);\n \n+\t/* Disable MSI */\n+\tval = advk_readl(pcie, PCIE_CORE_CTRL2_REG);\n+\tval &= ~PCIE_CORE_CTRL2_MSI_ENABLE;\n+\tadvk_writel(pcie, val, PCIE_CORE_CTRL2_REG);\n+\n+\t/* Clear MSI address */\n+\tadvk_writel(pcie, 0, PCIE_MSI_ADDR_LOW_REG);\n+\tadvk_writel(pcie, 0, PCIE_MSI_ADDR_HIGH_REG);\n+\n+\t/* Mask all interrupts */\n+\tadvk_writel(pcie, PCIE_MSI_ALL_MASK, PCIE_MSI_MASK_REG);\n+\tadvk_writel(pcie, PCIE_ISR0_ALL_MASK, PCIE_ISR0_MASK_REG);\n+\tadvk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_MASK_REG);\n+\tadvk_writel(pcie, PCIE_IRQ_ALL_MASK, HOST_CTRL_INT_MASK_REG);\n+\n+\t/* Clear all interrupts */\n+\tadvk_writel(pcie, PCIE_MSI_ALL_MASK, PCIE_MSI_STATUS_REG);\n+\tadvk_writel(pcie, PCIE_ISR0_ALL_MASK, PCIE_ISR0_REG);\n+\tadvk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_REG);\n+\tadvk_writel(pcie, PCIE_IRQ_ALL_MASK, HOST_CTRL_INT_STATUS_REG);\n+\n \t/* Remove IRQ domains */\n \tadvk_pcie_remove_msi_irq_domain(pcie);\n \tadvk_pcie_remove_irq_domain(pcie);\n"
  },
  {
    "path": "target/linux/generic/backport-5.15/850-v5.17-0008-PCI-aardvark-Fix-memory-leak-in-driver-unbind.patch",
    "content": "From 2f040a17f5061457ae95035326d3159eddc1e5cc Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>\nDate: Tue, 30 Nov 2021 18:29:10 +0100\nSubject: [PATCH] PCI: aardvark: Fix memory leak in driver unbind\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nFree config space for emulated root bridge when unbinding driver to fix\nmemory leak. Do it after disabling and masking all interrupts, since\naardvark interrupt handler accesses config space of emulated root\nbridge.\n\nLink: https://lore.kernel.org/r/20211130172913.9727-9-kabel@kernel.org\nSigned-off-by: Pali Rohár <pali@kernel.org>\nSigned-off-by: Marek Behún <kabel@kernel.org>\nSigned-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>\n---\n drivers/pci/controller/pci-aardvark.c | 3 +++\n 1 file changed, 3 insertions(+)\n\n--- a/drivers/pci/controller/pci-aardvark.c\n+++ b/drivers/pci/controller/pci-aardvark.c\n@@ -1718,6 +1718,9 @@ static int advk_pcie_remove(struct platf\n \tadvk_pcie_remove_msi_irq_domain(pcie);\n \tadvk_pcie_remove_irq_domain(pcie);\n \n+\t/* Free config space for emulated root bridge */\n+\tpci_bridge_emul_cleanup(&pcie->bridge);\n+\n \t/* Disable outbound address windows mapping */\n \tfor (i = 0; i < OB_WIN_COUNT; i++)\n \t\tadvk_pcie_disable_ob_win(pcie, i);\n"
  },
  {
    "path": "target/linux/generic/backport-5.15/850-v5.17-0009-PCI-aardvark-Assert-PERST-when-unbinding-driver.patch",
    "content": "From 1f54391be8ce0c981d312cb93acdc5608def576a Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>\nDate: Tue, 30 Nov 2021 18:29:11 +0100\nSubject: [PATCH] PCI: aardvark: Assert PERST# when unbinding driver\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nPut the PCIe card into reset by asserting PERST# signal when unbinding\ndriver. It doesn't make sense to leave the card working if it can't\ncommunicate with the host. This should also save some power.\n\nLink: https://lore.kernel.org/r/20211130172913.9727-10-kabel@kernel.org\nSigned-off-by: Pali Rohár <pali@kernel.org>\nSigned-off-by: Marek Behún <kabel@kernel.org>\nSigned-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>\n---\n drivers/pci/controller/pci-aardvark.c | 4 ++++\n 1 file changed, 4 insertions(+)\n\n--- a/drivers/pci/controller/pci-aardvark.c\n+++ b/drivers/pci/controller/pci-aardvark.c\n@@ -1721,6 +1721,10 @@ static int advk_pcie_remove(struct platf\n \t/* Free config space for emulated root bridge */\n \tpci_bridge_emul_cleanup(&pcie->bridge);\n \n+\t/* Assert PERST# signal which prepares PCIe card for power down */\n+\tif (pcie->reset_gpio)\n+\t\tgpiod_set_value_cansleep(pcie->reset_gpio, 1);\n+\n \t/* Disable outbound address windows mapping */\n \tfor (i = 0; i < OB_WIN_COUNT; i++)\n \t\tadvk_pcie_disable_ob_win(pcie, i);\n"
  },
  {
    "path": "target/linux/generic/backport-5.15/850-v5.17-0010-PCI-aardvark-Disable-link-training-when-unbinding-dr.patch",
    "content": "From 759dec2e3dfdbd261c41d2279f04f2351c971a49 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>\nDate: Tue, 30 Nov 2021 18:29:12 +0100\nSubject: [PATCH] PCI: aardvark: Disable link training when unbinding driver\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nDisable link training circuit in driver unbind sequence. We want to\nleave link training in the same state as it was before the driver was\nprobed.\n\nLink: https://lore.kernel.org/r/20211130172913.9727-11-kabel@kernel.org\nSigned-off-by: Pali Rohár <pali@kernel.org>\nSigned-off-by: Marek Behún <kabel@kernel.org>\nSigned-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>\n---\n drivers/pci/controller/pci-aardvark.c | 5 +++++\n 1 file changed, 5 insertions(+)\n\n--- a/drivers/pci/controller/pci-aardvark.c\n+++ b/drivers/pci/controller/pci-aardvark.c\n@@ -1725,6 +1725,11 @@ static int advk_pcie_remove(struct platf\n \tif (pcie->reset_gpio)\n \t\tgpiod_set_value_cansleep(pcie->reset_gpio, 1);\n \n+\t/* Disable link training */\n+\tval = advk_readl(pcie, PCIE_CORE_CTRL0_REG);\n+\tval &= ~LINK_TRAINING_EN;\n+\tadvk_writel(pcie, val, PCIE_CORE_CTRL0_REG);\n+\n \t/* Disable outbound address windows mapping */\n \tfor (i = 0; i < OB_WIN_COUNT; i++)\n \t\tadvk_pcie_disable_ob_win(pcie, i);\n"
  },
  {
    "path": "target/linux/generic/backport-5.15/850-v5.17-0011-PCI-aardvark-Disable-common-PHY-when-unbinding-drive.patch",
    "content": "From fdbbe242c15a8f2cd0e3ad8a56cd0a447b771d0d Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>\nDate: Tue, 30 Nov 2021 18:29:13 +0100\nSubject: [PATCH] PCI: aardvark: Disable common PHY when unbinding driver\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nDisable the PCIe PHY when unbinding driver. This should save some power.\n\nLink: https://lore.kernel.org/r/20211130172913.9727-12-kabel@kernel.org\nSigned-off-by: Pali Rohár <pali@kernel.org>\nSigned-off-by: Marek Behún <kabel@kernel.org>\nSigned-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>\n---\n drivers/pci/controller/pci-aardvark.c | 3 +++\n 1 file changed, 3 insertions(+)\n\n--- a/drivers/pci/controller/pci-aardvark.c\n+++ b/drivers/pci/controller/pci-aardvark.c\n@@ -1734,6 +1734,9 @@ static int advk_pcie_remove(struct platf\n \tfor (i = 0; i < OB_WIN_COUNT; i++)\n \t\tadvk_pcie_disable_ob_win(pcie, i);\n \n+\t/* Disable phy */\n+\tadvk_pcie_disable_phy(pcie);\n+\n \treturn 0;\n }\n \n"
  },
  {
    "path": "target/linux/generic/backport-5.15/860-v5.17-MIPS-ath79-drop-_machine_restart-again.patch",
    "content": "From d3115128bdafb62628ab41861a4f06f6d02ac320 Mon Sep 17 00:00:00 2001\nFrom: Lech Perczak <lech.perczak@gmail.com>\nDate: Mon, 10 Jan 2022 23:48:44 +0100\nSubject: MIPS: ath79: drop _machine_restart again\n\nCommit 81424d0ad0d4 (\"MIPS: ath79: Use the reset controller to restart\nOF machines\") removed setup of _machine_restart on OF machines to use\nreset handler in reset controller driver.\nWhile removing remnants of non-OF machines in commit 3a77e0d75eed\n(\"MIPS: ath79: drop machfiles\"), this was introduced again, making it\nimpossible to use additional restart handlers registered through device\ntree. Drop setting _machine_restart altogether, and ath79_restart\nfunction, which is no longer used after this.\n\nFixes: 3a77e0d75eed (\"MIPS: ath79: drop machfiles\")\nCc: John Crispin <john@phrozen.org>\nCc: Florian Fainelli <f.fainelli@gmail.com>\nSigned-off-by: Lech Perczak <lech.perczak@gmail.com>\nSigned-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>\n---\n arch/mips/ath79/setup.c | 10 ----------\n 1 file changed, 10 deletions(-)\n\n--- a/arch/mips/ath79/setup.c\n+++ b/arch/mips/ath79/setup.c\n@@ -34,15 +34,6 @@\n \n static char ath79_sys_type[ATH79_SYS_TYPE_LEN];\n \n-static void ath79_restart(char *command)\n-{\n-\tlocal_irq_disable();\n-\tath79_device_reset_set(AR71XX_RESET_FULL_CHIP);\n-\tfor (;;)\n-\t\tif (cpu_wait)\n-\t\t\tcpu_wait();\n-}\n-\n static void ath79_halt(void)\n {\n \twhile (1)\n@@ -234,7 +225,6 @@ void __init plat_mem_setup(void)\n \n \tdetect_memory_region(0, ATH79_MEM_SIZE_MIN, ATH79_MEM_SIZE_MAX);\n \n-\t_machine_restart = ath79_restart;\n \t_machine_halt = ath79_halt;\n \tpm_power_off = ath79_halt;\n }\n"
  },
  {
    "path": "target/linux/generic/backport-5.15/870-hwmon-next-hwmon-lm70-Add-ti-tmp125-support.patch",
    "content": "From 31d8f414e1596ba54a4315418e4c0086fda9e428 Mon Sep 17 00:00:00 2001\nFrom: Christian Lamparter <chunkeey@gmail.com>\nDate: Fri, 18 Feb 2022 10:06:43 +0100\nSubject: hwmon: (lm70) Add ti,tmp125 support\n\nThe TMP125 is a 2 degree Celsius accurate Digital\nTemperature Sensor with a SPI interface.\n\nThe temperature register is a 16-bit, read-only register.\nThe MSB (Bit 15) is a leading zero and never set. Bits 14\nto 5 are the 1+9 temperature data bits in a two's\ncomplement format. Bits 4 to 0 are useless copies of\nBit 5 value and therefore ignored.\n\nSigned-off-by: Christian Lamparter <chunkeey@gmail.com>\nLink: https://lore.kernel.org/r/43b19cbd4e7f51e9509e561b02b5d8d0e7079fac.1645175187.git.chunkeey@gmail.com\nSigned-off-by: Guenter Roeck <linux@roeck-us.net>\n---\n--- a/drivers/hwmon/lm70.c\n+++ b/drivers/hwmon/lm70.c\n@@ -34,6 +34,7 @@\n #define LM70_CHIP_LM71\t\t2\t/* NS LM71 */\n #define LM70_CHIP_LM74\t\t3\t/* NS LM74 */\n #define LM70_CHIP_TMP122\t4\t/* TI TMP122/TMP124 */\n+#define LM70_CHIP_TMP125\t5\t/* TI TMP125 */\n \n struct lm70 {\n \tstruct spi_device *spi;\n@@ -87,6 +88,12 @@ static ssize_t temp1_input_show(struct d\n \t * LM71:\n \t * 14 bits of 2's complement data, discard LSB 2 bits,\n \t * resolution 0.0312 degrees celsius.\n+\t *\n+\t * TMP125:\n+\t * MSB/D15 is a leading zero. D14 is the sign-bit. This is\n+\t * followed by 9 temperature bits (D13..D5) in 2's complement\n+\t * data format with a resolution of 0.25 degrees celsius per unit.\n+\t * LSB 5 bits (D4..D0) share the same value as D5 and get discarded.\n \t */\n \tswitch (p_lm70->chip) {\n \tcase LM70_CHIP_LM70:\n@@ -102,6 +109,10 @@ static ssize_t temp1_input_show(struct d\n \tcase LM70_CHIP_LM71:\n \t\tval = ((int)raw / 4) * 3125 / 100;\n \t\tbreak;\n+\n+\tcase LM70_CHIP_TMP125:\n+\t\tval = (sign_extend32(raw, 14) / 32) * 250;\n+\t\tbreak;\n \t}\n \n \tstatus = sprintf(buf, \"%d\\n\", val); /* millidegrees Celsius */\n@@ -136,6 +147,10 @@ static const struct of_device_id lm70_of\n \t\t.data = (void *) LM70_CHIP_TMP122,\n \t},\n \t{\n+\t\t.compatible = \"ti,tmp125\",\n+\t\t.data = (void *) LM70_CHIP_TMP125,\n+\t},\n+\t{\n \t\t.compatible = \"ti,lm71\",\n \t\t.data = (void *) LM70_CHIP_LM71,\n \t},\n@@ -184,6 +199,7 @@ static const struct spi_device_id lm70_i\n \t{ \"lm70\",   LM70_CHIP_LM70 },\n \t{ \"tmp121\", LM70_CHIP_TMP121 },\n \t{ \"tmp122\", LM70_CHIP_TMP122 },\n+\t{ \"tmp125\", LM70_CHIP_TMP125 },\n \t{ \"lm71\",   LM70_CHIP_LM71 },\n \t{ \"lm74\",   LM70_CHIP_LM74 },\n \t{ },\n"
  },
  {
    "path": "target/linux/generic/backport-5.15/880-v5.19-cdc_ether-export-usbnet_cdc_zte_rx_fixup.patch",
    "content": "From a79a5613e1907e1bf09bb6ba6fd5ff43b66c1afe Mon Sep 17 00:00:00 2001\nFrom: Lech Perczak <lech.perczak@gmail.com>\nDate: Fri, 1 Apr 2022 22:03:55 +0200\nSubject: [PATCH 1/3] cdc_ether: export usbnet_cdc_zte_rx_fixup\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nCommit bfe9b9d2df66 (\"cdc_ether: Improve ZTE MF823/831/910 handling\")\nintroduces a workaround for certain ZTE modems reporting invalid MAC\naddresses over CDC-ECM.\nThe same issue was present on their RNDIS interface,which was fixed in\ncommit a5a18bdf7453 (\"rndis_host: Set valid random MAC on buggy devices\").\n\nHowever, internal modem of ZTE MF286R router, on its RNDIS interface, also\nexhibits a second issue fixed already in CDC-ECM, of the device not\nrespecting configured random MAC address. In order to share the fixup for\nthis with rndis_host driver, export the workaround function, which will\nbe re-used in the following commit in rndis_host.\n\nCc: Kristian Evensen <kristian.evensen@gmail.com>\nCc: Bjørn Mork <bjorn@mork.no>\nCc: Oliver Neukum <oliver@neukum.org>\nSigned-off-by: Lech Perczak <lech.perczak@gmail.com>\n---\n drivers/net/usb/cdc_ether.c | 3 ++-\n include/linux/usb/usbnet.h  | 1 +\n 2 files changed, 3 insertions(+), 1 deletion(-)\n\n--- a/drivers/net/usb/cdc_ether.c\n+++ b/drivers/net/usb/cdc_ether.c\n@@ -479,7 +479,7 @@ static int usbnet_cdc_zte_bind(struct us\n  * device MAC address has been updated). Always set MAC address to that of the\n  * device.\n  */\n-static int usbnet_cdc_zte_rx_fixup(struct usbnet *dev, struct sk_buff *skb)\n+int usbnet_cdc_zte_rx_fixup(struct usbnet *dev, struct sk_buff *skb)\n {\n \tif (skb->len < ETH_HLEN || !(skb->data[0] & 0x02))\n \t\treturn 1;\n@@ -489,6 +489,7 @@ static int usbnet_cdc_zte_rx_fixup(struc\n \n \treturn 1;\n }\n+EXPORT_SYMBOL_GPL(usbnet_cdc_zte_rx_fixup);\n \n /* Ensure correct link state\n  *\n--- a/include/linux/usb/usbnet.h\n+++ b/include/linux/usb/usbnet.h\n@@ -214,6 +214,7 @@ extern int usbnet_ether_cdc_bind(struct\n extern int usbnet_cdc_bind(struct usbnet *, struct usb_interface *);\n extern void usbnet_cdc_unbind(struct usbnet *, struct usb_interface *);\n extern void usbnet_cdc_status(struct usbnet *, struct urb *);\n+extern int usbnet_cdc_zte_rx_fixup(struct usbnet *dev, struct sk_buff *skb);\n \n /* CDC and RNDIS support the same host-chosen packet filters for IN transfers */\n #define\tDEFAULT_FILTER\t(USB_CDC_PACKET_TYPE_BROADCAST \\\n"
  },
  {
    "path": "target/linux/generic/backport-5.15/881-v5.19-rndis_host-enable-the-bogus-MAC-fixup-for-ZTE-device.patch",
    "content": "From aa8aff10e969aca0cb64f5e54ff7489355582667 Mon Sep 17 00:00:00 2001\nFrom: Lech Perczak <lech.perczak@gmail.com>\nDate: Fri, 1 Apr 2022 22:04:01 +0200\nSubject: [PATCH 2/3] rndis_host: enable the bogus MAC fixup for ZTE devices\n from cdc_ether\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nCertain ZTE modems, namely: MF823. MF831, MF910, built-in modem from\nMF286R, expose both CDC-ECM and RNDIS network interfaces.\nThey have a trait of ignoring the locally-administered MAC address\nconfigured on the interface both in CDC-ECM and RNDIS part,\nand this leads to dropping of incoming traffic by the host.\nHowever, the workaround was only present in CDC-ECM, and MF286R\nexplicitly requires it in RNDIS mode.\n\nRe-use the workaround in rndis_host as well, to fix operation of MF286R\nmodule, some versions of which expose only the RNDIS interface. Do so by\nintroducing new flag, RNDIS_DRIVER_DATA_DST_MAC_FIXUP, and testing for it\nin rndis_rx_fixup. This is required, as RNDIS uses frame batching, and all\nof the packets inside the batch need the fixup. This might introduce a\nperformance penalty, because test is done for every returned Ethernet\nframe.\n\nApply the workaround to both \"flavors\" of RNDIS interfaces, as older ZTE\nmodems, like MF823 found in the wild, report the USB_CLASS_COMM class\ninterfaces, while MF286R reports USB_CLASS_WIRELESS_CONTROLLER.\n\nSuggested-by: Bjørn Mork <bjorn@mork.no>\nCc: Kristian Evensen <kristian.evensen@gmail.com>\nCc: Oliver Neukum <oliver@neukum.org>\nSigned-off-by: Lech Perczak <lech.perczak@gmail.com>\n---\n drivers/net/usb/rndis_host.c   | 32 ++++++++++++++++++++++++++++++++\n include/linux/usb/rndis_host.h |  1 +\n 2 files changed, 33 insertions(+)\n\n--- a/drivers/net/usb/rndis_host.c\n+++ b/drivers/net/usb/rndis_host.c\n@@ -485,10 +485,14 @@ EXPORT_SYMBOL_GPL(rndis_unbind);\n  */\n int rndis_rx_fixup(struct usbnet *dev, struct sk_buff *skb)\n {\n+\tbool dst_mac_fixup;\n+\n \t/* This check is no longer done by usbnet */\n \tif (skb->len < dev->net->hard_header_len)\n \t\treturn 0;\n \n+\tdst_mac_fixup = !!(dev->driver_info->data & RNDIS_DRIVER_DATA_DST_MAC_FIXUP);\n+\n \t/* peripheral may have batched packets to us... */\n \twhile (likely(skb->len)) {\n \t\tstruct rndis_data_hdr\t*hdr = (void *)skb->data;\n@@ -523,10 +527,17 @@ int rndis_rx_fixup(struct usbnet *dev, s\n \t\t\tbreak;\n \t\tskb_pull(skb, msg_len - sizeof *hdr);\n \t\tskb_trim(skb2, data_len);\n+\n+\t\tif (unlikely(dst_mac_fixup))\n+\t\t\tusbnet_cdc_zte_rx_fixup(dev, skb2);\n+\n \t\tusbnet_skb_return(dev, skb2);\n \t}\n \n \t/* caller will usbnet_skb_return the remaining packet */\n+\tif (unlikely(dst_mac_fixup))\n+\t\tusbnet_cdc_zte_rx_fixup(dev, skb);\n+\n \treturn 1;\n }\n EXPORT_SYMBOL_GPL(rndis_rx_fixup);\n@@ -600,6 +611,17 @@ static const struct driver_info\trndis_po\n \t.tx_fixup =\trndis_tx_fixup,\n };\n \n+static const struct driver_info\tzte_rndis_info = {\n+\t.description =\t\"ZTE RNDIS device\",\n+\t.flags =\tFLAG_ETHER | FLAG_POINTTOPOINT | FLAG_FRAMING_RN | FLAG_NO_SETINT,\n+\t.data =\t\tRNDIS_DRIVER_DATA_DST_MAC_FIXUP,\n+\t.bind =\t\trndis_bind,\n+\t.unbind =\trndis_unbind,\n+\t.status =\trndis_status,\n+\t.rx_fixup =\trndis_rx_fixup,\n+\t.tx_fixup =\trndis_tx_fixup,\n+};\n+\n /*-------------------------------------------------------------------------*/\n \n static const struct usb_device_id\tproducts [] = {\n@@ -614,6 +636,16 @@ static const struct usb_device_id\tproduc\n \t\t\t\t      USB_CLASS_COMM, 2 /* ACM */, 0x0ff),\n \t.driver_info = (unsigned long)&rndis_info,\n }, {\n+\t/* ZTE WWAN modules */\n+\tUSB_VENDOR_AND_INTERFACE_INFO(0x19d2,\n+\t\t\t\t      USB_CLASS_WIRELESS_CONTROLLER, 1, 3),\n+\t.driver_info = (unsigned long)&zte_rndis_info,\n+}, {\n+\t/* ZTE WWAN modules, ACM flavour */\n+\tUSB_VENDOR_AND_INTERFACE_INFO(0x19d2,\n+\t\t\t\t      USB_CLASS_COMM, 2 /* ACM */, 0x0ff),\n+\t.driver_info = (unsigned long)&zte_rndis_info,\n+}, {\n \t/* RNDIS is MSFT's un-official variant of CDC ACM */\n \tUSB_INTERFACE_INFO(USB_CLASS_COMM, 2 /* ACM */, 0x0ff),\n \t.driver_info = (unsigned long) &rndis_info,\n--- a/include/linux/usb/rndis_host.h\n+++ b/include/linux/usb/rndis_host.h\n@@ -197,6 +197,7 @@ struct rndis_keepalive_c {\t/* IN (option\n \n /* Flags for driver_info::data */\n #define RNDIS_DRIVER_DATA_POLL_STATUS\t1\t/* poll status before control */\n+#define RNDIS_DRIVER_DATA_DST_MAC_FIXUP\t2\t/* device ignores configured MAC address */\n \n extern void rndis_status(struct usbnet *dev, struct urb *urb);\n extern int\n"
  },
  {
    "path": "target/linux/generic/backport-5.15/882-v5.19-rndis_host-limit-scope-of-bogus-MAC-address-detectio.patch",
    "content": "From 9bfb4bcda7ba32d73ea322ea56a8ebe32e9247f6 Mon Sep 17 00:00:00 2001\nFrom: Lech Perczak <lech.perczak@gmail.com>\nDate: Sat, 2 Apr 2022 02:19:57 +0200\nSubject: [PATCH 3/3] rndis_host: limit scope of bogus MAC address detection to\n ZTE devices\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nReporting of bogus MAC addresses and ignoring configuration of new\ndestination address wasn't observed outside of a range of ZTE devices,\namong which this seems to be the common bug. Align rndis_host driver\nwith implementation found in cdc_ether, which also limits this workaround\nto ZTE devices.\n\nSuggested-by: Bjørn Mork <bjorn@mork.no>\nCc: Kristian Evensen <kristian.evensen@gmail.com>\nCc: Oliver Neukum <oliver@neukum.org>\nSigned-off-by: Lech Perczak <lech.perczak@gmail.com>\n---\n drivers/net/usb/rndis_host.c | 17 ++++++++++++-----\n 1 file changed, 12 insertions(+), 5 deletions(-)\n\n--- a/drivers/net/usb/rndis_host.c\n+++ b/drivers/net/usb/rndis_host.c\n@@ -418,10 +418,7 @@ generic_rndis_bind(struct usbnet *dev, s\n \t\tgoto halt_fail_and_release;\n \t}\n \n-\tif (bp[0] & 0x02)\n-\t\teth_hw_addr_random(net);\n-\telse\n-\t\tether_addr_copy(net->dev_addr, bp);\n+\tether_addr_copy(net->dev_addr, bp);\n \n \t/* set a nonzero filter to enable data transfers */\n \tmemset(u.set, 0, sizeof *u.set);\n@@ -463,6 +460,16 @@ static int rndis_bind(struct usbnet *dev\n \treturn generic_rndis_bind(dev, intf, FLAG_RNDIS_PHYM_NOT_WIRELESS);\n }\n \n+static int zte_rndis_bind(struct usbnet *dev, struct usb_interface *intf)\n+{\n+\tint status = rndis_bind(dev, intf);\n+\n+\tif (!status && (dev->net->dev_addr[0] & 0x02))\n+\t\teth_hw_addr_random(dev->net);\n+\n+\treturn status;\n+}\n+\n void rndis_unbind(struct usbnet *dev, struct usb_interface *intf)\n {\n \tstruct rndis_halt\t*halt;\n@@ -615,7 +622,7 @@ static const struct driver_info\tzte_rndi\n \t.description =\t\"ZTE RNDIS device\",\n \t.flags =\tFLAG_ETHER | FLAG_POINTTOPOINT | FLAG_FRAMING_RN | FLAG_NO_SETINT,\n \t.data =\t\tRNDIS_DRIVER_DATA_DST_MAC_FIXUP,\n-\t.bind =\t\trndis_bind,\n+\t.bind =\t\tzte_rndis_bind,\n \t.unbind =\trndis_unbind,\n \t.status =\trndis_status,\n \t.rx_fixup =\trndis_rx_fixup,\n"
  },
  {
    "path": "target/linux/generic/backport-5.15/890-v5.19-net-sfp-Add-tx-fault-workaround-for-Huawei-MA5671A-SFP-ON.patch",
    "content": "From f81d97cb646ab8b90fb181d66fccaf9589990de6 Mon Sep 17 00:00:00 2001\nFrom: Matthew Hagan <mnhagan88@gmail.com>\nDate: Sat, 30 Apr 2022 11:00:49 +0100\nSubject: [PATCH v2] net: sfp: Add tx-fault workaround for Huawei MA5671A SFP\n ONT\n\nAs noted elsewhere, various GPON SFP modules exhibit non-standard\nTX-fault behaviour. In the tested case, the Huawei MA5671A, when used\nin combination with a Marvell mv88e6085 switch, was found to\npersistently assert TX-fault, resulting in the module being disabled.\n\nThis patch adds a quirk to ignore the SFP_F_TX_FAULT state, allowing the\nmodule to function.\n\nChange from v1: removal of erroneous return statment (Andrew Lunn)\n\nSigned-off-by: Matthew Hagan <mnhagan88@gmail.com>\nReviewed-by: Andrew Lunn <andrew@lunn.ch>\n---\n drivers/net/phy/sfp.c | 12 +++++++++++-\n 1 file changed, 11 insertions(+), 1 deletion(-)\n\n--- a/drivers/net/phy/sfp.c\n+++ b/drivers/net/phy/sfp.c\n@@ -250,6 +250,7 @@ struct sfp {\n \tstruct sfp_eeprom_id id;\n \tunsigned int module_power_mW;\n \tunsigned int module_t_start_up;\n+\tbool tx_fault_ignore;\n \n #if IS_ENABLED(CONFIG_HWMON)\n \tstruct sfp_diag diag;\n@@ -1945,6 +1946,12 @@ static int sfp_sm_mod_probe(struct sfp *\n \telse\n \t\tsfp->module_t_start_up = T_START_UP;\n \n+\tif (!memcmp(id.base.vendor_name, \"HUAWEI          \", 16) &&\n+\t    !memcmp(id.base.vendor_pn, \"MA5671A         \", 16))\n+\t\tsfp->tx_fault_ignore = true;\n+\telse\n+\t\tsfp->tx_fault_ignore = false;\n+\n \treturn 0;\n }\n \n@@ -2397,7 +2404,10 @@ static void sfp_check_state(struct sfp *\n \tmutex_lock(&sfp->st_mutex);\n \tstate = sfp_get_state(sfp);\n \tchanged = state ^ sfp->state;\n-\tchanged &= SFP_F_PRESENT | SFP_F_LOS | SFP_F_TX_FAULT;\n+\tif (sfp->tx_fault_ignore)\n+\t\tchanged &= SFP_F_PRESENT | SFP_F_LOS;\n+\telse\n+\t\tchanged &= SFP_F_PRESENT | SFP_F_LOS | SFP_F_TX_FAULT;\n \n \tfor (i = 0; i < GPIO_MAX; i++)\n \t\tif (changed & BIT(i))\n"
  },
  {
    "path": "target/linux/generic/config-5.10",
    "content": "# CONFIG_104_QUAD_8 is not set\nCONFIG_32BIT=y\nCONFIG_64BIT_TIME=y\n# CONFIG_6LOWPAN is not set\n# CONFIG_6LOWPAN_DEBUGFS is not set\n# CONFIG_6PACK is not set\n# CONFIG_8139CP is not set\n# CONFIG_8139TOO is not set\n# CONFIG_9P_FS is not set\n# CONFIG_AB3100_CORE is not set\n# CONFIG_AB8500_CORE is not set\n# CONFIG_ABP060MG is not set\n# CONFIG_ABX500_CORE is not set\n# CONFIG_ACCESSIBILITY is not set\n# CONFIG_ACENIC is not set\n# CONFIG_ACERHDF is not set\n# CONFIG_ACER_WIRELESS is not set\n# CONFIG_ACORN_PARTITION is not set\n# CONFIG_ACPI_ALS is not set\n# CONFIG_ACPI_APEI is not set\n# CONFIG_ACPI_BUTTON is not set\n# CONFIG_ACPI_CONFIGFS is not set\n# CONFIG_ACPI_CUSTOM_METHOD is not set\n# CONFIG_ACPI_EXTLOG is not set\n# CONFIG_ACPI_HED is not set\n# CONFIG_ACPI_NFIT is not set\n# CONFIG_ACPI_REDUCED_HARDWARE_ONLY is not set\n# CONFIG_ACPI_TABLE_UPGRADE is not set\n# CONFIG_ACPI_VIDEO is not set\n# CONFIG_AD2S1200 is not set\n# CONFIG_AD2S1210 is not set\n# CONFIG_AD2S90 is not set\n# CONFIG_AD5064 is not set\n# CONFIG_AD525X_DPOT is not set\n# CONFIG_AD5272 is not set\n# CONFIG_AD5360 is not set\n# CONFIG_AD5380 is not set\n# CONFIG_AD5421 is not set\n# CONFIG_AD5446 is not set\n# CONFIG_AD5449 is not set\n# CONFIG_AD5504 is not set\n# CONFIG_AD5592R is not set\n# CONFIG_AD5593R is not set\n# CONFIG_AD5624R_SPI is not set\n# CONFIG_AD5686 is not set\n# CONFIG_AD5686_SPI is not set\n# CONFIG_AD5696_I2C is not set\n# CONFIG_AD5755 is not set\n# CONFIG_AD5758 is not set\n# CONFIG_AD5761 is not set\n# CONFIG_AD5764 is not set\n# CONFIG_AD5770R is not set\n# CONFIG_AD5791 is not set\n# CONFIG_AD5933 is not set\n# CONFIG_AD7091R5 is not set\n# CONFIG_AD7124 is not set\n# CONFIG_AD7150 is not set\n# CONFIG_AD7152 is not set\n# CONFIG_AD7192 is not set\n# CONFIG_AD7266 is not set\n# CONFIG_AD7280 is not set\n# CONFIG_AD7291 is not set\n# CONFIG_AD7292 is not set\n# CONFIG_AD7298 is not set\n# CONFIG_AD7303 is not set\n# CONFIG_AD7476 is not set\n# CONFIG_AD7606 is not set\n# CONFIG_AD7606_IFACE_PARALLEL is not set\n# CONFIG_AD7606_IFACE_SPI is not set\n# CONFIG_AD7746 is not set\n# CONFIG_AD7766 is not set\n# CONFIG_AD7768_1 is not set\n# CONFIG_AD7780 is not set\n# CONFIG_AD7791 is not set\n# CONFIG_AD7793 is not set\n# CONFIG_AD7816 is not set\n# CONFIG_AD7887 is not set\n# CONFIG_AD7923 is not set\n# CONFIG_AD7949 is not set\n# CONFIG_AD799X is not set\n# CONFIG_AD8366 is not set\n# CONFIG_AD8801 is not set\n# CONFIG_AD9467 is not set\n# CONFIG_AD9523 is not set\n# CONFIG_AD9832 is not set\n# CONFIG_AD9834 is not set\n# CONFIG_ADAPTEC_STARFIRE is not set\n# CONFIG_ADE7854 is not set\n# CONFIG_ADF4350 is not set\n# CONFIG_ADF4371 is not set\n# CONFIG_ADFS_FS is not set\n# CONFIG_ADIN_PHY is not set\n# CONFIG_ADIS16080 is not set\n# CONFIG_ADIS16130 is not set\n# CONFIG_ADIS16136 is not set\n# CONFIG_ADIS16201 is not set\n# CONFIG_ADIS16203 is not set\n# CONFIG_ADIS16209 is not set\n# CONFIG_ADIS16240 is not set\n# CONFIG_ADIS16260 is not set\n# CONFIG_ADIS16400 is not set\n# CONFIG_ADIS16460 is not set\n# CONFIG_ADIS16475 is not set\n# CONFIG_ADIS16480 is not set\n# CONFIG_ADI_AXI_ADC is not set\n# CONFIG_ADJD_S311 is not set\n# CONFIG_ADM6996_PHY is not set\n# CONFIG_ADM8211 is not set\n# CONFIG_ADT7316 is not set\n# CONFIG_ADUX1020 is not set\nCONFIG_ADVISE_SYSCALLS=y\n# CONFIG_ADXL345_I2C is not set\n# CONFIG_ADXL345_SPI is not set\n# CONFIG_ADXL372_I2C is not set\n# CONFIG_ADXL372_SPI is not set\n# CONFIG_ADXRS290 is not set\n# CONFIG_ADXRS450 is not set\nCONFIG_AEABI=y\n# CONFIG_AFE4403 is not set\n# CONFIG_AFE4404 is not set\n# CONFIG_AFFS_FS is not set\n# CONFIG_AFS_DEBUG_CURSOR is not set\n# CONFIG_AFS_FS is not set\n# CONFIG_AF_KCM is not set\n# CONFIG_AF_RXRPC is not set\n# CONFIG_AF_RXRPC_INJECT_LOSS is not set\n# CONFIG_AF_RXRPC_IPV6 is not set\n# CONFIG_AGP is not set\n# CONFIG_AHCI_CEVA is not set\n# CONFIG_AHCI_IMX is not set\n# CONFIG_AHCI_MVEBU is not set\n# CONFIG_AHCI_QORIQ is not set\n# CONFIG_AHCI_XGENE is not set\nCONFIG_AIO=y\n# CONFIG_AIRO is not set\n# CONFIG_AIRO_CS is not set\n# CONFIG_AIX_PARTITION is not set\n# CONFIG_AK09911 is not set\n# CONFIG_AK8974 is not set\n# CONFIG_AK8975 is not set\n# CONFIG_AL3010 is not set\n# CONFIG_AL3320A is not set\n# CONFIG_ALIM7101_WDT is not set\nCONFIG_ALLOW_DEV_COREDUMP=y\n# CONFIG_ALTERA_MBOX is not set\n# CONFIG_ALTERA_MSGDMA is not set\n# CONFIG_ALTERA_STAPL is not set\n# CONFIG_ALTERA_TSE is not set\n# CONFIG_ALX is not set\n# CONFIG_AL_FIC is not set\n# CONFIG_AM2315 is not set\n# CONFIG_AM335X_PHY_USB is not set\n# CONFIG_AMBA_PL08X is not set\n# CONFIG_AMD8111_ETH is not set\n# CONFIG_AMD_MEM_ENCRYPT is not set\n# CONFIG_AMD_PHY is not set\n# CONFIG_AMD_XGBE is not set\n# CONFIG_AMD_XGBE_HAVE_ECC is not set\n# CONFIG_AMIGA_PARTITION is not set\n# CONFIG_AMILO_RFKILL is not set\n# CONFIG_ANDROID is not set\nCONFIG_ANON_INODES=y\n# CONFIG_APDS9300 is not set\n# CONFIG_APDS9802ALS is not set\n# CONFIG_APDS9960 is not set\n# CONFIG_APM8018X is not set\n# CONFIG_APM_EMULATION is not set\n# CONFIG_APPLE_GMUX is not set\n# CONFIG_APPLE_MFI_FASTCHARGE is not set\n# CONFIG_APPLE_PROPERTIES is not set\n# CONFIG_APPLICOM is not set\n# CONFIG_AQTION is not set\n# CONFIG_AQUANTIA_PHY is not set\n# CONFIG_AR5523 is not set\n# CONFIG_AR7 is not set\n# CONFIG_AR8216_PHY is not set\n# CONFIG_AR8216_PHY_LEDS is not set\n# CONFIG_ARCH_ACTIONS is not set\n# CONFIG_ARCH_AGILEX is not set\n# CONFIG_ARCH_ALPINE is not set\n# CONFIG_ARCH_ARTPEC is not set\n# CONFIG_ARCH_ASPEED is not set\n# CONFIG_ARCH_AT91 is not set\n# CONFIG_ARCH_AXXIA is not set\n# CONFIG_ARCH_BCM is not set\n# CONFIG_ARCH_BCM2835 is not set\n# CONFIG_ARCH_BCM_21664 is not set\n# CONFIG_ARCH_BCM_23550 is not set\n# CONFIG_ARCH_BCM_281XX is not set\n# CONFIG_ARCH_BCM_5301X is not set\n# CONFIG_ARCH_BCM_53573 is not set\n# CONFIG_ARCH_BCM_63XX is not set\n# CONFIG_ARCH_BCM_CYGNUS is not set\n# CONFIG_ARCH_BCM_IPROC is not set\n# CONFIG_ARCH_BCM_NSP is not set\n# CONFIG_ARCH_BERLIN is not set\nCONFIG_ARCH_BINFMT_ELF_STATE=y\n# CONFIG_ARCH_BITMAIN is not set\n# CONFIG_ARCH_BRCMSTB is not set\n# CONFIG_ARCH_CLPS711X is not set\n# CONFIG_ARCH_CNS3XXX is not set\n# CONFIG_ARCH_DAVINCI is not set\n# CONFIG_ARCH_DIGICOLOR is not set\n# CONFIG_ARCH_DMA_ADDR_T_64BIT is not set\n# CONFIG_ARCH_DOVE is not set\n# CONFIG_ARCH_EBSA110 is not set\n# CONFIG_ARCH_EP93XX is not set\n# CONFIG_ARCH_EXYNOS is not set\nCONFIG_ARCH_FLATMEM_ENABLE=y\n# CONFIG_ARCH_FOOTBRIDGE is not set\n# CONFIG_ARCH_GEMINI is not set\n# CONFIG_ARCH_HI3xxx is not set\n# CONFIG_ARCH_HIGHBANK is not set\n# CONFIG_ARCH_HISI is not set\n# CONFIG_ARCH_INTEGRATOR is not set\n# CONFIG_ARCH_IOP13XX is not set\n# CONFIG_ARCH_IOP32X is not set\n# CONFIG_ARCH_IOP33X is not set\n# CONFIG_ARCH_IXP4XX is not set\n# CONFIG_ARCH_K3 is not set\n# CONFIG_ARCH_KEEMBAY is not set\n# CONFIG_ARCH_KEYSTONE is not set\n# CONFIG_ARCH_KS8695 is not set\n# CONFIG_ARCH_LAYERSCAPE is not set\n# CONFIG_ARCH_LG1K is not set\n# CONFIG_ARCH_LPC32XX is not set\n# CONFIG_ARCH_MEDIATEK is not set\n# CONFIG_ARCH_MESON is not set\n# CONFIG_ARCH_MILBEAUT is not set\nCONFIG_ARCH_MMAP_RND_BITS=8\nCONFIG_ARCH_MMAP_RND_BITS_MAX=16\nCONFIG_ARCH_MMAP_RND_BITS_MIN=8\nCONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=16\nCONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=8\n# CONFIG_ARCH_MMP is not set\n# CONFIG_ARCH_MSTARV7 is not set\n# CONFIG_ARCH_MULTIPLATFORM is not set\n# CONFIG_ARCH_MULTI_V6 is not set\n# CONFIG_ARCH_MULTI_V7 is not set\n# CONFIG_ARCH_MV78XX0 is not set\n# CONFIG_ARCH_MVEBU is not set\n# CONFIG_ARCH_MXC is not set\n# CONFIG_ARCH_MXS is not set\n# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set\n# CONFIG_ARCH_NETX is not set\n# CONFIG_ARCH_NOMADIK is not set\n# CONFIG_ARCH_NPCM is not set\n# CONFIG_ARCH_NSPIRE is not set\n# CONFIG_ARCH_OMAP is not set\n# CONFIG_ARCH_OMAP1 is not set\n# CONFIG_ARCH_OMAP2 is not set\n# CONFIG_ARCH_OMAP2PLUS is not set\n# CONFIG_ARCH_OMAP3 is not set\n# CONFIG_ARCH_OMAP4 is not set\n# CONFIG_ARCH_ORION5X is not set\n# CONFIG_ARCH_OXNAS is not set\n# CONFIG_ARCH_PICOXCELL is not set\n# CONFIG_ARCH_PRIMA2 is not set\n# CONFIG_ARCH_PXA is not set\n# CONFIG_ARCH_QCOM is not set\n# CONFIG_ARCH_RANDOM is not set\n# CONFIG_ARCH_RDA is not set\n# CONFIG_ARCH_REALTEK is not set\n# CONFIG_ARCH_REALVIEW is not set\n# CONFIG_ARCH_RENESAS is not set\n# CONFIG_ARCH_ROCKCHIP is not set\n# CONFIG_ARCH_RPC is not set\n# CONFIG_ARCH_S32 is not set\n# CONFIG_ARCH_S3C24XX is not set\n# CONFIG_ARCH_S3C64XX is not set\n# CONFIG_ARCH_S5PV210 is not set\n# CONFIG_ARCH_SA1100 is not set\n# CONFIG_ARCH_SEATTLE is not set\n# CONFIG_ARCH_SHMOBILE is not set\n# CONFIG_ARCH_SIRF is not set\n# CONFIG_ARCH_SOCFPGA is not set\n# CONFIG_ARCH_SPARX5 is not set\n# CONFIG_ARCH_SPRD is not set\n# CONFIG_ARCH_STI is not set\n# CONFIG_ARCH_STM32 is not set\n# CONFIG_ARCH_STRATIX10 is not set\n# CONFIG_ARCH_SUNXI is not set\n# CONFIG_ARCH_SYNQUACER is not set\n# CONFIG_ARCH_TANGO is not set\n# CONFIG_ARCH_TEGRA is not set\n# CONFIG_ARCH_THUNDER is not set\n# CONFIG_ARCH_THUNDER2 is not set\n# CONFIG_ARCH_U300 is not set\n# CONFIG_ARCH_U8500 is not set\n# CONFIG_ARCH_UNIPHIER is not set\n# CONFIG_ARCH_VERSATILE is not set\n# CONFIG_ARCH_VEXPRESS is not set\n# CONFIG_ARCH_VIRT is not set\n# CONFIG_ARCH_VISCONTI is not set\n# CONFIG_ARCH_VT8500 is not set\n# CONFIG_ARCH_VULCAN is not set\n# CONFIG_ARCH_W90X900 is not set\n# CONFIG_ARCH_WANTS_THP_SWAP is not set\n# CONFIG_ARCH_WM8505 is not set\n# CONFIG_ARCH_WM8750 is not set\n# CONFIG_ARCH_WM8850 is not set\n# CONFIG_ARCH_XGENE is not set\n# CONFIG_ARCH_ZX is not set\n# CONFIG_ARCH_ZYNQ is not set\n# CONFIG_ARCH_ZYNQMP is not set\n# CONFIG_ARCNET is not set\n# CONFIG_ARC_EMAC is not set\n# CONFIG_ARC_IRQ_NO_AUTOSAVE is not set\n# CONFIG_ARM64_16K_PAGES is not set\n# CONFIG_ARM64_64K_PAGES is not set\n# CONFIG_ARM64_AMU_EXTN is not set\n# CONFIG_ARM64_BTI is not set\n# CONFIG_ARM64_CRYPTO is not set\n# CONFIG_ARM64_E0PD is not set\n# CONFIG_ARM64_ERRATUM_1024718 is not set\n# CONFIG_ARM64_ERRATUM_1165522 is not set\n# CONFIG_ARM64_ERRATUM_1286807 is not set\n# CONFIG_ARM64_ERRATUM_1319367 is not set\n# CONFIG_ARM64_ERRATUM_1418040 is not set\n# CONFIG_ARM64_ERRATUM_1463225 is not set\n# CONFIG_ARM64_ERRATUM_1508412 is not set\n# CONFIG_ARM64_ERRATUM_1530923 is not set\n# CONFIG_ARM64_ERRATUM_1542419 is not set\n# CONFIG_ARM64_ERRATUM_819472 is not set\n# CONFIG_ARM64_ERRATUM_824069 is not set\n# CONFIG_ARM64_ERRATUM_826319 is not set\n# CONFIG_ARM64_ERRATUM_827319 is not set\n# CONFIG_ARM64_ERRATUM_832075 is not set\n# CONFIG_ARM64_ERRATUM_834220 is not set\n# CONFIG_ARM64_ERRATUM_843419 is not set\n# CONFIG_ARM64_ERRATUM_845719 is not set\n# CONFIG_ARM64_ERRATUM_858921 is not set\n# CONFIG_ARM64_HW_AFDBM is not set\n# CONFIG_ARM64_LSE_ATOMICS is not set\n# CONFIG_ARM64_MODULE_PLTS is not set\n# CONFIG_ARM64_MTE is not set\n# CONFIG_ARM64_PAN is not set\n# CONFIG_ARM64_PMEM is not set\n# CONFIG_ARM64_PSEUDO_NMI is not set\n# CONFIG_ARM64_PTDUMP_DEBUGFS is not set\n# CONFIG_ARM64_RANDOMIZE_TEXT_OFFSET is not set\n# CONFIG_ARM64_RAS_EXTN is not set\n# CONFIG_ARM64_RELOC_TEST is not set\nCONFIG_ARM64_SW_TTBR0_PAN=y\n# CONFIG_ARM64_TLB_RANGE is not set\n# CONFIG_ARM64_UAO is not set\n# CONFIG_ARM64_USE_LSE_ATOMICS is not set\n# CONFIG_ARM64_VA_BITS_48 is not set\n# CONFIG_ARM64_VHE is not set\n# CONFIG_ARM_APPENDED_DTB is not set\n# CONFIG_ARM_ARCH_TIMER is not set\n# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set\n# CONFIG_ARM_BIG_LITTLE_CPUFREQ is not set\n# CONFIG_ARM_CCI is not set\n# CONFIG_ARM_CCI400_PMU is not set\n# CONFIG_ARM_CCI5xx_PMU is not set\n# CONFIG_ARM_CCI_PMU is not set\n# CONFIG_ARM_CCN is not set\n# CONFIG_ARM_CMN is not set\n# CONFIG_ARM_CPUIDLE is not set\nCONFIG_ARM_CPU_TOPOLOGY=y\n# CONFIG_ARM_CRYPTO is not set\nCONFIG_ARM_DMA_MEM_BUFFERABLE=y\n# CONFIG_ARM_DSU_PMU is not set\n# CONFIG_ARM_ERRATA_326103 is not set\n# CONFIG_ARM_ERRATA_364296 is not set\n# CONFIG_ARM_ERRATA_411920 is not set\n# CONFIG_ARM_ERRATA_430973 is not set\n# CONFIG_ARM_ERRATA_458693 is not set\n# CONFIG_ARM_ERRATA_460075 is not set\n# CONFIG_ARM_ERRATA_643719 is not set\n# CONFIG_ARM_ERRATA_720789 is not set\n# CONFIG_ARM_ERRATA_742230 is not set\n# CONFIG_ARM_ERRATA_742231 is not set\n# CONFIG_ARM_ERRATA_743622 is not set\n# CONFIG_ARM_ERRATA_751472 is not set\n# CONFIG_ARM_ERRATA_754322 is not set\n# CONFIG_ARM_ERRATA_754327 is not set\n# CONFIG_ARM_ERRATA_764369 is not set\n# CONFIG_ARM_ERRATA_773022 is not set\n# CONFIG_ARM_ERRATA_775420 is not set\n# CONFIG_ARM_ERRATA_798181 is not set\n# CONFIG_ARM_ERRATA_814220 is not set\n# CONFIG_ARM_ERRATA_818325_852422 is not set\n# CONFIG_ARM_ERRATA_821420 is not set\n# CONFIG_ARM_ERRATA_825619 is not set\n# CONFIG_ARM_ERRATA_852421 is not set\n# CONFIG_ARM_ERRATA_852423 is not set\n# CONFIG_ARM_ERRATA_857271 is not set\n# CONFIG_ARM_ERRATA_857272 is not set\nCONFIG_ARM_GIC_MAX_NR=1\n# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set\n# CONFIG_ARM_KPROBES_TEST is not set\n# CONFIG_ARM_LPAE is not set\n# CONFIG_ARM_MHU is not set\n# CONFIG_ARM_MODULE_PLTS is not set\n# CONFIG_ARM_PATCH_PHYS_VIRT is not set\n# CONFIG_ARM_PSCI is not set\n# CONFIG_ARM_PSCI_CHECKER is not set\n# CONFIG_ARM_PSCI_CPUIDLE is not set\n# CONFIG_ARM_PTDUMP_DEBUGFS is not set\n# CONFIG_ARM_SBSA_WATCHDOG is not set\n# CONFIG_ARM_SCMI_PROTOCOL is not set\n# CONFIG_ARM_SCPI_PROTOCOL is not set\n# CONFIG_ARM_SDE_INTERFACE is not set\n# CONFIG_ARM_SMCCC_SOC_ID is not set\n# CONFIG_ARM_SMC_WATCHDOG is not set\n# CONFIG_ARM_SP805_WATCHDOG is not set\n# CONFIG_ARM_SPE_PMU is not set\n# CONFIG_ARM_THUMBEE is not set\n# CONFIG_ARM_TIMER_SP804 is not set\n# CONFIG_ARM_UNWIND is not set\n# CONFIG_ARM_VIRT_EXT is not set\n# CONFIG_AS3935 is not set\n# CONFIG_AS73211 is not set\n# CONFIG_ASM9260_TIMER is not set\n# CONFIG_ASN1 is not set\n# CONFIG_ASUS_LAPTOP is not set\n# CONFIG_ASUS_WIRELESS is not set\n# CONFIG_ASYMMETRIC_KEY_TYPE is not set\n# CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE is not set\n# CONFIG_ASYMMETRIC_TPM_KEY_SUBTYPE is not set\n# CONFIG_ASYNC_RAID6_TEST is not set\n# CONFIG_ASYNC_TX_DMA is not set\n# CONFIG_AT76C50X_USB is not set\n# CONFIG_AT803X_PHY is not set\n# CONFIG_AT91_SAMA5D2_ADC is not set\n# CONFIG_ATA is not set\n# CONFIG_ATAGS is not set\nCONFIG_ATAGS_PROC=y\n# CONFIG_ATALK is not set\n# CONFIG_ATARI_PARTITION is not set\n# CONFIG_ATA_ACPI is not set\nCONFIG_ATA_BMDMA=y\n# CONFIG_ATA_FORCE is not set\n# CONFIG_ATA_GENERIC is not set\n# CONFIG_ATA_LEDS is not set\n# CONFIG_ATA_NONSTANDARD is not set\n# CONFIG_ATA_OVER_ETH is not set\n# CONFIG_ATA_PIIX is not set\nCONFIG_ATA_SFF=y\n# CONFIG_ATA_VERBOSE_ERROR is not set\n# CONFIG_ATH10K is not set\n# CONFIG_ATH25 is not set\n# CONFIG_ATH5K is not set\n# CONFIG_ATH6KL is not set\n# CONFIG_ATH79 is not set\n# CONFIG_ATH9K is not set\n# CONFIG_ATH9K_HTC is not set\n# CONFIG_ATH_DEBUG is not set\n# CONFIG_ATL1 is not set\n# CONFIG_ATL1C is not set\n# CONFIG_ATL1E is not set\n# CONFIG_ATL2 is not set\n# CONFIG_ATLAS_EZO_SENSOR is not set\n# CONFIG_ATLAS_PH_SENSOR is not set\n# CONFIG_ATM is not set\n# CONFIG_ATMEL is not set\n# CONFIG_ATMEL_PIT is not set\n# CONFIG_ATMEL_SSC is not set\n# CONFIG_ATM_AMBASSADOR is not set\n# CONFIG_ATM_BR2684 is not set\nCONFIG_ATM_BR2684_IPFILTER=y\n# CONFIG_ATM_CLIP is not set\nCONFIG_ATM_CLIP_NO_ICMP=y\n# CONFIG_ATM_DRIVERS is not set\n# CONFIG_ATM_DUMMY is not set\n# CONFIG_ATM_ENI is not set\n# CONFIG_ATM_FIRESTREAM is not set\n# CONFIG_ATM_FORE200E is not set\n# CONFIG_ATM_HE is not set\n# CONFIG_ATM_HORIZON is not set\n# CONFIG_ATM_IA is not set\n# CONFIG_ATM_IDT77252 is not set\n# CONFIG_ATM_LANAI is not set\n# CONFIG_ATM_LANE is not set\n# CONFIG_ATM_MPOA is not set\n# CONFIG_ATM_NICSTAR is not set\n# CONFIG_ATM_SOLOS is not set\n# CONFIG_ATM_TCP is not set\n# CONFIG_ATM_ZATM is not set\n# CONFIG_ATOMIC64_SELFTEST is not set\n# CONFIG_ATP is not set\n# CONFIG_AUDIT is not set\n# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set\n# CONFIG_AURORA_NB8800 is not set\n# CONFIG_AUTOFS4_FS is not set\n# CONFIG_AUTOFS_FS is not set\n# CONFIG_AUTO_ZRELADDR is not set\n# CONFIG_AUXDISPLAY is not set\n# CONFIG_AX25 is not set\n# CONFIG_AX25_DAMA_SLAVE is not set\n# CONFIG_AX88796 is not set\n# CONFIG_AX88796B_PHY is not set\n# CONFIG_AXP20X_ADC is not set\n# CONFIG_AXP20X_POWER is not set\n# CONFIG_AXP288_ADC is not set\n# CONFIG_AXP288_FUEL_GAUGE is not set\n# CONFIG_B43 is not set\n# CONFIG_B43LEGACY is not set\n# CONFIG_B44 is not set\n# CONFIG_B53 is not set\n# CONFIG_B53_MDIO_DRIVER is not set\n# CONFIG_B53_MMAP_DRIVER is not set\n# CONFIG_B53_SERDES is not set\n# CONFIG_B53_SPI_DRIVER is not set\n# CONFIG_B53_SRAB_DRIVER is not set\n# CONFIG_BACKLIGHT_ADP8860 is not set\n# CONFIG_BACKLIGHT_ADP8870 is not set\n# CONFIG_BACKLIGHT_APPLE is not set\n# CONFIG_BACKLIGHT_ARCXCNN is not set\n# CONFIG_BACKLIGHT_BD6107 is not set\n# CONFIG_BACKLIGHT_CLASS_DEVICE is not set\n# CONFIG_BACKLIGHT_GENERIC is not set\n# CONFIG_BACKLIGHT_GPIO is not set\n# CONFIG_BACKLIGHT_KTD253 is not set\n# CONFIG_BACKLIGHT_LCD_SUPPORT is not set\n# CONFIG_BACKLIGHT_LED is not set\n# CONFIG_BACKLIGHT_LM3630A is not set\n# CONFIG_BACKLIGHT_LM3639 is not set\n# CONFIG_BACKLIGHT_LP855X is not set\n# CONFIG_BACKLIGHT_LV5207LP is not set\n# CONFIG_BACKLIGHT_PANDORA is not set\n# CONFIG_BACKLIGHT_PM8941_WLED is not set\n# CONFIG_BACKLIGHT_PWM is not set\n# CONFIG_BACKLIGHT_QCOM_WLED is not set\n# CONFIG_BACKLIGHT_RPI is not set\n# CONFIG_BACKLIGHT_SAHARA is not set\n# CONFIG_BACKTRACE_SELF_TEST is not set\n# CONFIG_BAREUDP is not set\nCONFIG_BASE_FULL=y\nCONFIG_BASE_SMALL=0\n# CONFIG_BATMAN_ADV is not set\n# CONFIG_BATTERY_BQ27XXX is not set\n# CONFIG_BATTERY_BQ27XXX_HDQ is not set\n# CONFIG_BATTERY_CW2015 is not set\n# CONFIG_BATTERY_DS2760 is not set\n# CONFIG_BATTERY_DS2780 is not set\n# CONFIG_BATTERY_DS2781 is not set\n# CONFIG_BATTERY_DS2782 is not set\n# CONFIG_BATTERY_GAUGE_LTC2941 is not set\n# CONFIG_BATTERY_GOLDFISH is not set\n# CONFIG_BATTERY_LEGO_EV3 is not set\n# CONFIG_BATTERY_MAX17040 is not set\n# CONFIG_BATTERY_MAX17042 is not set\n# CONFIG_BATTERY_MAX1721X is not set\n# CONFIG_BATTERY_RT5033 is not set\n# CONFIG_BATTERY_SBS is not set\n# CONFIG_BAYCOM_EPP is not set\n# CONFIG_BAYCOM_PAR is not set\n# CONFIG_BAYCOM_SER_FDX is not set\n# CONFIG_BAYCOM_SER_HDX is not set\n# CONFIG_BCACHE is not set\n# CONFIG_BCM47XX is not set\n# CONFIG_BCM54140_PHY is not set\n# CONFIG_BCM63XX is not set\n# CONFIG_BCM63XX_PHY is not set\n# CONFIG_BCM7038_WDT is not set\n# CONFIG_BCM7XXX_PHY is not set\n# CONFIG_BCM84881_PHY is not set\n# CONFIG_BCM87XX_PHY is not set\n# CONFIG_BCMA is not set\n# CONFIG_BCMA_DRIVER_GPIO is not set\nCONFIG_BCMA_POSSIBLE=y\n# CONFIG_BCMGENET is not set\n# CONFIG_BCM_IPROC_ADC is not set\n# CONFIG_BCM_KONA_USB2_PHY is not set\n# CONFIG_BCM_SBA_RAID is not set\n# CONFIG_BDI_SWITCH is not set\n# CONFIG_BE2ISCSI is not set\n# CONFIG_BE2NET is not set\n# CONFIG_BEFS_FS is not set\n# CONFIG_BFS_FS is not set\n# CONFIG_BGMAC is not set\n# CONFIG_BH1750 is not set\n# CONFIG_BH1780 is not set\n# CONFIG_BIG_KEYS is not set\n# CONFIG_BIG_LITTLE is not set\n# CONFIG_BINARY_PRINTF is not set\n# CONFIG_BINFMT_AOUT is not set\nCONFIG_BINFMT_ELF=y\n# CONFIG_BINFMT_ELF_FDPIC is not set\n# CONFIG_BINFMT_FLAT is not set\n# CONFIG_BINFMT_MISC is not set\nCONFIG_BINFMT_SCRIPT=y\nCONFIG_BITREVERSE=y\n# CONFIG_BLK_CGROUP_IOCOST is not set\n# CONFIG_BLK_CGROUP_IOLATENCY is not set\n# CONFIG_BLK_CMDLINE_PARSER is not set\n# CONFIG_BLK_DEBUG_FS is not set\nCONFIG_BLK_DEV=y\n# CONFIG_BLK_DEV_3W_XXXX_RAID is not set\n# CONFIG_BLK_DEV_4DRIVES is not set\n# CONFIG_BLK_DEV_AEC62XX is not set\n# CONFIG_BLK_DEV_ALI14XX is not set\n# CONFIG_BLK_DEV_ALI15X3 is not set\n# CONFIG_BLK_DEV_AMD74XX is not set\n# CONFIG_BLK_DEV_ATIIXP is not set\n# CONFIG_BLK_DEV_BSG is not set\n# CONFIG_BLK_DEV_BSGLIB is not set\n# CONFIG_BLK_DEV_CMD640 is not set\n# CONFIG_BLK_DEV_CMD64X is not set\n# CONFIG_BLK_DEV_COW_COMMON is not set\n# CONFIG_BLK_DEV_CRYPTOLOOP is not set\n# CONFIG_BLK_DEV_CS5520 is not set\n# CONFIG_BLK_DEV_CS5530 is not set\n# CONFIG_BLK_DEV_CS5535 is not set\n# CONFIG_BLK_DEV_CS5536 is not set\n# CONFIG_BLK_DEV_CY82C693 is not set\n# CONFIG_BLK_DEV_DAC960 is not set\n# CONFIG_BLK_DEV_DELKIN is not set\n# CONFIG_BLK_DEV_DRBD is not set\n# CONFIG_BLK_DEV_DTC2278 is not set\n# CONFIG_BLK_DEV_FD is not set\n# CONFIG_BLK_DEV_GENERIC is not set\n# CONFIG_BLK_DEV_HPT366 is not set\n# CONFIG_BLK_DEV_HT6560B is not set\n# CONFIG_BLK_DEV_IDEACPI is not set\n# CONFIG_BLK_DEV_IDECD is not set\n# CONFIG_BLK_DEV_IDECS is not set\n# CONFIG_BLK_DEV_IDEPCI is not set\n# CONFIG_BLK_DEV_IDEPNP is not set\n# CONFIG_BLK_DEV_IDETAPE is not set\n# CONFIG_BLK_DEV_IDE_AU1XXX is not set\n# CONFIG_BLK_DEV_IDE_SATA is not set\nCONFIG_BLK_DEV_INITRD=y\n# CONFIG_BLK_DEV_INTEGRITY is not set\n# CONFIG_BLK_DEV_IO_TRACE is not set\n# CONFIG_BLK_DEV_IT8172 is not set\n# CONFIG_BLK_DEV_IT8213 is not set\n# CONFIG_BLK_DEV_IT821X is not set\n# CONFIG_BLK_DEV_JMICRON is not set\n# CONFIG_BLK_DEV_LOOP is not set\nCONFIG_BLK_DEV_LOOP_MIN_COUNT=8\n# CONFIG_BLK_DEV_NBD is not set\n# CONFIG_BLK_DEV_NS87415 is not set\n# CONFIG_BLK_DEV_NULL_BLK is not set\n# CONFIG_BLK_DEV_NVME is not set\n# CONFIG_BLK_DEV_OFFBOARD is not set\n# CONFIG_BLK_DEV_OPTI621 is not set\n# CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set\n# CONFIG_BLK_DEV_PDC202XX_NEW is not set\n# CONFIG_BLK_DEV_PDC202XX_OLD is not set\n# CONFIG_BLK_DEV_PIIX is not set\n# CONFIG_BLK_DEV_PLATFORM is not set\n# CONFIG_BLK_DEV_PMEM is not set\n# CONFIG_BLK_DEV_QD65XX is not set\n# CONFIG_BLK_DEV_RAM is not set\n# CONFIG_BLK_DEV_RBD is not set\n# CONFIG_BLK_DEV_RSXX is not set\n# CONFIG_BLK_DEV_RZ1000 is not set\n# CONFIG_BLK_DEV_SC1200 is not set\n# CONFIG_BLK_DEV_SD is not set\n# CONFIG_BLK_DEV_SIIMAGE is not set\n# CONFIG_BLK_DEV_SIS5513 is not set\n# CONFIG_BLK_DEV_SKD is not set\n# CONFIG_BLK_DEV_SL82C105 is not set\n# CONFIG_BLK_DEV_SLC90E66 is not set\n# CONFIG_BLK_DEV_SR is not set\n# CONFIG_BLK_DEV_SVWKS is not set\n# CONFIG_BLK_DEV_SX8 is not set\n# CONFIG_BLK_DEV_TC86C001 is not set\n# CONFIG_BLK_DEV_THROTTLING is not set\n# CONFIG_BLK_DEV_TRIFLEX is not set\n# CONFIG_BLK_DEV_TRM290 is not set\n# CONFIG_BLK_DEV_UMC8672 is not set\n# CONFIG_BLK_DEV_UMEM is not set\n# CONFIG_BLK_DEV_VIA82CXXX is not set\n# CONFIG_BLK_DEV_ZONED is not set\n# CONFIG_BLK_INLINE_ENCRYPTION is not set\n# CONFIG_BLK_SED_OPAL is not set\n# CONFIG_BLK_WBT is not set\nCONFIG_BLOCK=y\n# CONFIG_BMA180 is not set\n# CONFIG_BMA220 is not set\n# CONFIG_BMA400 is not set\n# CONFIG_BMC150_ACCEL is not set\n# CONFIG_BMC150_MAGN is not set\n# CONFIG_BMC150_MAGN_I2C is not set\n# CONFIG_BMC150_MAGN_SPI is not set\n# CONFIG_BME680 is not set\n# CONFIG_BMG160 is not set\n# CONFIG_BMI160_I2C is not set\n# CONFIG_BMI160_SPI is not set\n# CONFIG_BMIPS_GENERIC is not set\n# CONFIG_BMP280 is not set\n# CONFIG_BNA is not set\n# CONFIG_BNX2 is not set\n# CONFIG_BNX2X is not set\n# CONFIG_BNX2X_SRIOV is not set\n# CONFIG_BNXT is not set\n# CONFIG_BONDING is not set\n# CONFIG_BOOKE_WDT is not set\nCONFIG_BOOKE_WDT_DEFAULT_TIMEOUT=3\n# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set\n# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set\n# CONFIG_BOOTTIME_TRACING is not set\n# CONFIG_BOOT_CONFIG is not set\n# CONFIG_BOOT_PRINTK_DELAY is not set\nCONFIG_BOOT_RAW=y\n# CONFIG_BOUNCE is not set\nCONFIG_BPF=y\n# CONFIG_BPFILTER is not set\nCONFIG_BPF_JIT=y\n# CONFIG_BPF_JIT_ALWAYS_ON is not set\nCONFIG_BPF_JIT_DEFAULT_ON=y\n# CONFIG_BPF_PRELOAD is not set\n# CONFIG_BPF_STREAM_PARSER is not set\nCONFIG_BPF_SYSCALL=y\nCONFIG_BPF_UNPRIV_DEFAULT_OFF=y\n# CONFIG_BPQETHER is not set\nCONFIG_BQL=y\nCONFIG_BRANCH_PROFILE_NONE=y\n# CONFIG_BRCMFMAC is not set\n# CONFIG_BRCMSMAC is not set\n# CONFIG_BRCMSTB_GISB_ARB is not set\nCONFIG_BRIDGE=y\n# CONFIG_BRIDGE_EBT_802_3 is not set\n# CONFIG_BRIDGE_EBT_AMONG is not set\n# CONFIG_BRIDGE_EBT_ARP is not set\n# CONFIG_BRIDGE_EBT_ARPREPLY is not set\n# CONFIG_BRIDGE_EBT_BROUTE is not set\n# CONFIG_BRIDGE_EBT_DNAT is not set\n# CONFIG_BRIDGE_EBT_IP is not set\n# CONFIG_BRIDGE_EBT_IP6 is not set\n# CONFIG_BRIDGE_EBT_LIMIT is not set\n# CONFIG_BRIDGE_EBT_LOG is not set\n# CONFIG_BRIDGE_EBT_MARK is not set\n# CONFIG_BRIDGE_EBT_MARK_T is not set\n# CONFIG_BRIDGE_EBT_NFLOG is not set\n# CONFIG_BRIDGE_EBT_PKTTYPE is not set\n# CONFIG_BRIDGE_EBT_REDIRECT is not set\n# CONFIG_BRIDGE_EBT_SNAT is not set\n# CONFIG_BRIDGE_EBT_STP is not set\n# CONFIG_BRIDGE_EBT_T_FILTER is not set\n# CONFIG_BRIDGE_EBT_T_NAT is not set\n# CONFIG_BRIDGE_EBT_VLAN is not set\nCONFIG_BRIDGE_IGMP_SNOOPING=y\n# CONFIG_BRIDGE_MRP is not set\n# CONFIG_BRIDGE_NETFILTER is not set\n# CONFIG_BRIDGE_NF_EBTABLES is not set\nCONFIG_BRIDGE_VLAN_FILTERING=y\n# CONFIG_BROADCOM_PHY is not set\nCONFIG_BROKEN_ON_SMP=y\n# CONFIG_BSD_DISKLABEL is not set\n# CONFIG_BSD_PROCESS_ACCT is not set\n# CONFIG_BSD_PROCESS_ACCT_V3 is not set\n# CONFIG_BT is not set\n# CONFIG_BTRFS_ASSERT is not set\n# CONFIG_BTRFS_DEBUG is not set\n# CONFIG_BTRFS_FS is not set\n# CONFIG_BTRFS_FS_POSIX_ACL is not set\n# CONFIG_BTRFS_FS_REF_VERIFY is not set\n# CONFIG_BTRFS_FS_RUN_SANITY_TESTS is not set\n# CONFIG_BT_ATH3K is not set\n# CONFIG_BT_BNEP is not set\nCONFIG_BT_BNEP_MC_FILTER=y\nCONFIG_BT_BNEP_PROTO_FILTER=y\n# CONFIG_BT_BREDR is not set\n# CONFIG_BT_CMTP is not set\n# CONFIG_BT_FEATURE_DEBUG is not set\n# CONFIG_BT_HCIBCM203X is not set\n# CONFIG_BT_HCIBFUSB is not set\n# CONFIG_BT_HCIBLUECARD is not set\n# CONFIG_BT_HCIBPA10X is not set\n# CONFIG_BT_HCIBT3C is not set\n# CONFIG_BT_HCIBTSDIO is not set\n# CONFIG_BT_HCIBTUSB is not set\n# CONFIG_BT_HCIBTUSB_AUTOSUSPEND is not set\n# CONFIG_BT_HCIBTUSB_MTK is not set\n# CONFIG_BT_HCIBTUSB_RTL is not set\n# CONFIG_BT_HCIDTL1 is not set\n# CONFIG_BT_HCIUART is not set\n# CONFIG_BT_HCIUART_3WIRE is not set\n# CONFIG_BT_HCIUART_AG6XX is not set\n# CONFIG_BT_HCIUART_ATH3K is not set\nCONFIG_BT_HCIUART_BCSP=y\nCONFIG_BT_HCIUART_H4=y\n# CONFIG_BT_HCIUART_LL is not set\n# CONFIG_BT_HCIUART_MRVL is not set\n# CONFIG_BT_HCIUART_QCA is not set\n# CONFIG_BT_HCIUART_RTL is not set\n# CONFIG_BT_HCIVHCI is not set\n# CONFIG_BT_HIDP is not set\n# CONFIG_BT_HS is not set\n# CONFIG_BT_LE is not set\n# CONFIG_BT_LEDS is not set\n# CONFIG_BT_MRVL is not set\n# CONFIG_BT_MSFTEXT is not set\n# CONFIG_BT_MTKSDIO is not set\n# CONFIG_BT_MTKUART is not set\n# CONFIG_BT_RFCOMM is not set\nCONFIG_BT_RFCOMM_TTY=y\n# CONFIG_BT_SELFTEST is not set\nCONFIG_BUG=y\n# CONFIG_BUG_ON_DATA_CORRUPTION is not set\nCONFIG_BUILDTIME_EXTABLE_SORT=y\nCONFIG_BUILDTIME_TABLE_SORT=y\n# CONFIG_BUILD_BIN2C is not set\nCONFIG_BUILD_SALT=\"\"\n# CONFIG_C2PORT is not set\nCONFIG_CACHE_L2X0_PMU=y\n# CONFIG_CADENCE_WATCHDOG is not set\n# CONFIG_CAIF is not set\n# CONFIG_CAN is not set\n# CONFIG_CAN_BCM is not set\n# CONFIG_CAN_DEBUG_DEVICES is not set\n# CONFIG_CAN_DEV is not set\n# CONFIG_CAN_GS_USB is not set\n# CONFIG_CAN_GW is not set\n# CONFIG_CAN_HI311X is not set\n# CONFIG_CAN_IFI_CANFD is not set\n# CONFIG_CAN_ISOTP is not set\n# CONFIG_CAN_J1939 is not set\n# CONFIG_CAN_KVASER_PCIEFD is not set\n# CONFIG_CAN_MCBA_USB is not set\n# CONFIG_CAN_MCP251XFD is not set\n# CONFIG_CAN_M_CAN is not set\n# CONFIG_CAN_PEAK_PCIEFD is not set\n# CONFIG_CAN_RAW is not set\n# CONFIG_CAN_RCAR is not set\n# CONFIG_CAN_RCAR_CANFD is not set\n# CONFIG_CAN_SLCAN is not set\n# CONFIG_CAN_SUN4I is not set\n# CONFIG_CAN_UCAN is not set\n# CONFIG_CAN_VCAN is not set\n# CONFIG_CAN_VXCAN is not set\n# CONFIG_CAPI_AVM is not set\n# CONFIG_CAPI_EICON is not set\n# CONFIG_CAPI_TRACE is not set\nCONFIG_CARDBUS=y\n# CONFIG_CARDMAN_4000 is not set\n# CONFIG_CARDMAN_4040 is not set\n# CONFIG_CARL9170 is not set\n# CONFIG_CASSINI is not set\n# CONFIG_CAVIUM_CPT is not set\n# CONFIG_CAVIUM_ERRATUM_22375 is not set\n# CONFIG_CAVIUM_ERRATUM_23144 is not set\n# CONFIG_CAVIUM_ERRATUM_23154 is not set\n# CONFIG_CAVIUM_ERRATUM_27456 is not set\n# CONFIG_CAVIUM_ERRATUM_30115 is not set\n# CONFIG_CAVIUM_OCTEON_SOC is not set\n# CONFIG_CAVIUM_PTP is not set\n# CONFIG_CAVIUM_TX2_ERRATUM_219 is not set\n# CONFIG_CB710_CORE is not set\n# CONFIG_CC10001_ADC is not set\n# CONFIG_CCS811 is not set\nCONFIG_CC_CAN_LINK=y\nCONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y\n# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set\n# CONFIG_CDROM_PKTCDVD is not set\n# CONFIG_CEPH_FS is not set\n# CONFIG_CEPH_LIB is not set\n# CONFIG_CFG80211 is not set\n# CONFIG_CFG80211_CERTIFICATION_ONUS is not set\n# CONFIG_CGROUPS is not set\n# CONFIG_CHARGER_ADP5061 is not set\n# CONFIG_CHARGER_BD99954 is not set\n# CONFIG_CHARGER_BQ2415X is not set\n# CONFIG_CHARGER_BQ24190 is not set\n# CONFIG_CHARGER_BQ24257 is not set\n# CONFIG_CHARGER_BQ24735 is not set\n# CONFIG_CHARGER_BQ2515X is not set\n# CONFIG_CHARGER_BQ25890 is not set\n# CONFIG_CHARGER_BQ25980 is not set\n# CONFIG_CHARGER_DETECTOR_MAX14656 is not set\n# CONFIG_CHARGER_GPIO is not set\n# CONFIG_CHARGER_ISP1704 is not set\n# CONFIG_CHARGER_LP8727 is not set\n# CONFIG_CHARGER_LT3651 is not set\n# CONFIG_CHARGER_LTC3651 is not set\n# CONFIG_CHARGER_MANAGER is not set\n# CONFIG_CHARGER_MAX8903 is not set\n# CONFIG_CHARGER_RT9455 is not set\n# CONFIG_CHARGER_SBS is not set\n# CONFIG_CHARGER_SMB347 is not set\n# CONFIG_CHARGER_TWL4030 is not set\n# CONFIG_CHARGER_UCS1002 is not set\n# CONFIG_CHASH_SELFTEST is not set\n# CONFIG_CHASH_STATS is not set\n# CONFIG_CHECKPOINT_RESTORE is not set\n# CONFIG_CHELSIO_T1 is not set\n# CONFIG_CHELSIO_T3 is not set\n# CONFIG_CHELSIO_T4 is not set\n# CONFIG_CHELSIO_T4VF is not set\n# CONFIG_CHROME_PLATFORMS is not set\n# CONFIG_CHR_DEV_OSST is not set\n# CONFIG_CHR_DEV_SCH is not set\n# CONFIG_CHR_DEV_SG is not set\n# CONFIG_CHR_DEV_ST is not set\n# CONFIG_CICADA_PHY is not set\n# CONFIG_CIFS is not set\n# CONFIG_CIFS_ACL is not set\nCONFIG_CIFS_ALLOW_INSECURE_LEGACY=y\n# CONFIG_CIFS_DEBUG is not set\n# CONFIG_CIFS_DEBUG2 is not set\n# CONFIG_CIFS_FSCACHE is not set\n# CONFIG_CIFS_NFSD_EXPORT is not set\nCONFIG_CIFS_POSIX=y\n# CONFIG_CIFS_SMB2 is not set\n# CONFIG_CIFS_STATS is not set\n# CONFIG_CIFS_STATS2 is not set\n# CONFIG_CIFS_WEAK_PW_HASH is not set\nCONFIG_CIFS_XATTR=y\n# CONFIG_CIO_DAC is not set\n# CONFIG_CLEANCACHE is not set\n# CONFIG_CLKSRC_VERSATILE is not set\n# CONFIG_CLK_HSDK is not set\n# CONFIG_CLK_QORIQ is not set\n# CONFIG_CLOCK_THERMAL is not set\nCONFIG_CLS_U32_MARK=y\n# CONFIG_CLS_U32_PERF is not set\n# CONFIG_CM32181 is not set\n# CONFIG_CM3232 is not set\n# CONFIG_CM3323 is not set\n# CONFIG_CM3605 is not set\n# CONFIG_CM36651 is not set\n# CONFIG_CMA is not set\nCONFIG_CMDLINE=\"\"\n# CONFIG_CMDLINE_BOOL is not set\n# CONFIG_CMDLINE_EXTEND is not set\n# CONFIG_CMDLINE_FORCE is not set\n# CONFIG_CMDLINE_FROM_BOOTLOADER is not set\n# CONFIG_CMDLINE_PARTITION is not set\n# CONFIG_CNIC is not set\n# CONFIG_CODA_FS is not set\n# CONFIG_CODE_PATCHING_SELFTEST is not set\n# CONFIG_COMEDI is not set\n# CONFIG_COMMON_CLK_CDCE706 is not set\n# CONFIG_COMMON_CLK_CDCE925 is not set\n# CONFIG_COMMON_CLK_CS2000_CP is not set\n# CONFIG_COMMON_CLK_FIXED_MMIO is not set\n# CONFIG_COMMON_CLK_IPROC is not set\n# CONFIG_COMMON_CLK_MAX9485 is not set\n# CONFIG_COMMON_CLK_MT6765 is not set\n# CONFIG_COMMON_CLK_MT8167 is not set\n# CONFIG_COMMON_CLK_MT8167_AUDSYS is not set\n# CONFIG_COMMON_CLK_MT8167_IMGSYS is not set\n# CONFIG_COMMON_CLK_MT8167_MFGCFG is not set\n# CONFIG_COMMON_CLK_MT8167_MMSYS is not set\n# CONFIG_COMMON_CLK_MT8167_VDECSYS is not set\n# CONFIG_COMMON_CLK_NXP is not set\n# CONFIG_COMMON_CLK_PIC32 is not set\n# CONFIG_COMMON_CLK_PWM is not set\n# CONFIG_COMMON_CLK_PXA is not set\n# CONFIG_COMMON_CLK_QCOM is not set\n# CONFIG_COMMON_CLK_SI514 is not set\n# CONFIG_COMMON_CLK_SI5341 is not set\n# CONFIG_COMMON_CLK_SI5351 is not set\n# CONFIG_COMMON_CLK_SI544 is not set\n# CONFIG_COMMON_CLK_SI570 is not set\n# CONFIG_COMMON_CLK_VC5 is not set\n# CONFIG_COMMON_CLK_XGENE is not set\n# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set\nCONFIG_COMPACTION=y\n# CONFIG_COMPAL_LAPTOP is not set\n# CONFIG_COMPAT is not set\n# CONFIG_COMPAT_BRK is not set\n# CONFIG_COMPILE_TEST is not set\n# CONFIG_CONFIGFS_FS is not set\n# CONFIG_CONNECTOR is not set\nCONFIG_CONSOLE_LOGLEVEL_DEFAULT=7\nCONFIG_CONSOLE_LOGLEVEL_QUIET=4\nCONFIG_CONSTRUCTORS=y\n# CONFIG_CONTEXT_SWITCH_TRACER is not set\n# CONFIG_COPS is not set\n# CONFIG_CORDIC is not set\n# CONFIG_COREDUMP is not set\n# CONFIG_CORESIGHT is not set\n# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set\n# CONFIG_CORTINA_PHY is not set\n# CONFIG_COUNTER is not set\n# CONFIG_CPA_DEBUG is not set\n# CONFIG_CPU_BIG_ENDIAN is not set\n# CONFIG_CPU_BPREDICT_DISABLE is not set\n# CONFIG_CPU_DCACHE_DISABLE is not set\n# CONFIG_CPU_FREQ is not set\n# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set\n# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set\n# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set\n# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set\n# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set\n# CONFIG_CPU_FREQ_GOV_SCHEDUTIL is not set\n# CONFIG_CPU_FREQ_STAT_DETAILS is not set\n# CONFIG_CPU_FREQ_THERMAL is not set\n# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set\n# CONFIG_CPU_ICACHE_DISABLE is not set\n# CONFIG_CPU_ICACHE_MISMATCH_WORKAROUND is not set\n# CONFIG_CPU_IDLE is not set\n# CONFIG_CPU_IDLE_GOV_LADDER is not set\n# CONFIG_CPU_IDLE_GOV_MENU is not set\n# CONFIG_CPU_IDLE_GOV_TEO is not set\n# CONFIG_CPU_IDLE_MULTIPLE_DRIVERS is not set\n# CONFIG_CPU_ISOLATION is not set\nCONFIG_CPU_LITTLE_ENDIAN=y\n# CONFIG_CPU_NO_EFFICIENT_FFS is not set\nCONFIG_CPU_SW_DOMAIN_PAN=y\n# CONFIG_CPU_THERMAL is not set\n# CONFIG_CRAMFS is not set\nCONFIG_CRAMFS_BLOCKDEV=y\n# CONFIG_CRAMFS_MTD is not set\n# CONFIG_CRASH_DUMP is not set\n# CONFIG_CRC16 is not set\nCONFIG_CRC32=y\n# CONFIG_CRC32_BIT is not set\nCONFIG_CRC32_SARWATE=y\n# CONFIG_CRC32_SELFTEST is not set\n# CONFIG_CRC32_SLICEBY4 is not set\n# CONFIG_CRC32_SLICEBY8 is not set\n# CONFIG_CRC4 is not set\n# CONFIG_CRC64 is not set\n# CONFIG_CRC7 is not set\n# CONFIG_CRC8 is not set\n# CONFIG_CRC_CCITT is not set\n# CONFIG_CRC_ITU_T is not set\n# CONFIG_CRC_T10DIF is not set\nCONFIG_CROSS_COMPILE=\"\"\n# CONFIG_CROSS_MEMORY_ATTACH is not set\nCONFIG_CRYPTO=y\n# CONFIG_CRYPTO_842 is not set\nCONFIG_CRYPTO_ACOMP2=y\n# CONFIG_CRYPTO_ADIANTUM is not set\nCONFIG_CRYPTO_AEAD=y\nCONFIG_CRYPTO_AEAD2=y\n# CONFIG_CRYPTO_AEGIS128 is not set\n# CONFIG_CRYPTO_AEGIS128L is not set\n# CONFIG_CRYPTO_AEGIS128L_AESNI_SSE2 is not set\n# CONFIG_CRYPTO_AEGIS128_AESNI_SSE2 is not set\n# CONFIG_CRYPTO_AEGIS256 is not set\n# CONFIG_CRYPTO_AEGIS256_AESNI_SSE2 is not set\nCONFIG_CRYPTO_AES=y\n# CONFIG_CRYPTO_AES_586 is not set\n# CONFIG_CRYPTO_AES_ARM is not set\n# CONFIG_CRYPTO_AES_ARM64 is not set\n# CONFIG_CRYPTO_AES_ARM64_BS is not set\n# CONFIG_CRYPTO_AES_ARM64_CE is not set\n# CONFIG_CRYPTO_AES_ARM64_CE_BLK is not set\n# CONFIG_CRYPTO_AES_ARM64_CE_CCM is not set\n# CONFIG_CRYPTO_AES_ARM64_NEON_BLK is not set\n# CONFIG_CRYPTO_AES_ARM_BS is not set\n# CONFIG_CRYPTO_AES_ARM_CE is not set\n# CONFIG_CRYPTO_AES_NI_INTEL is not set\n# CONFIG_CRYPTO_AES_TI is not set\nCONFIG_CRYPTO_AKCIPHER=y\nCONFIG_CRYPTO_AKCIPHER2=y\nCONFIG_CRYPTO_ALGAPI=y\nCONFIG_CRYPTO_ALGAPI2=y\n# CONFIG_CRYPTO_ANSI_CPRNG is not set\n# CONFIG_CRYPTO_ANUBIS is not set\n# CONFIG_CRYPTO_ARC4 is not set\n# CONFIG_CRYPTO_AUTHENC is not set\n# CONFIG_CRYPTO_BLAKE2B is not set\n# CONFIG_CRYPTO_BLAKE2S is not set\n# CONFIG_CRYPTO_BLAKE2S_X86 is not set\n# CONFIG_CRYPTO_BLOWFISH is not set\n# CONFIG_CRYPTO_CAMELLIA is not set\n# CONFIG_CRYPTO_CAST5 is not set\n# CONFIG_CRYPTO_CAST6 is not set\n# CONFIG_CRYPTO_CBC is not set\nCONFIG_CRYPTO_CCM=y\n# CONFIG_CRYPTO_CFB is not set\n# CONFIG_CRYPTO_CHACHA20 is not set\n# CONFIG_CRYPTO_CHACHA20POLY1305 is not set\n# CONFIG_CRYPTO_CHACHA20_NEON is not set\n# CONFIG_CRYPTO_CHACHA20_X86_64 is not set\n# CONFIG_CRYPTO_CHACHA_MIPS is not set\n# CONFIG_CRYPTO_CMAC is not set\n# CONFIG_CRYPTO_CRC32 is not set\n# CONFIG_CRYPTO_CRC32C is not set\n# CONFIG_CRYPTO_CRC32C_INTEL is not set\n# CONFIG_CRYPTO_CRC32_ARM_CE is not set\n# CONFIG_CRYPTO_CRCT10DIF is not set\n# CONFIG_CRYPTO_CRCT10DIF_ARM64_CE is not set\n# CONFIG_CRYPTO_CRCT10DIF_ARM_CE is not set\n# CONFIG_CRYPTO_CRYPTD is not set\nCONFIG_CRYPTO_CTR=y\n# CONFIG_CRYPTO_CTS is not set\n# CONFIG_CRYPTO_CURVE25519 is not set\n# CONFIG_CRYPTO_CURVE25519_NEON is not set\n# CONFIG_CRYPTO_CURVE25519_X86 is not set\n# CONFIG_CRYPTO_DEFLATE is not set\n# CONFIG_CRYPTO_DES is not set\n# CONFIG_CRYPTO_DEV_AMLOGIC_GXL is not set\n# CONFIG_CRYPTO_DEV_ATMEL_AES is not set\n# CONFIG_CRYPTO_DEV_ATMEL_AUTHENC is not set\n# CONFIG_CRYPTO_DEV_ATMEL_ECC is not set\n# CONFIG_CRYPTO_DEV_ATMEL_SHA is not set\n# CONFIG_CRYPTO_DEV_ATMEL_SHA204A is not set\n# CONFIG_CRYPTO_DEV_ATMEL_TDES is not set\n# CONFIG_CRYPTO_DEV_CAVIUM_ZIP is not set\n# CONFIG_CRYPTO_DEV_CCP is not set\n# CONFIG_CRYPTO_DEV_CCP_DEBUGFS is not set\n# CONFIG_CRYPTO_DEV_CCREE is not set\n# CONFIG_CRYPTO_DEV_FSL_CAAM is not set\n# CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API_DESC is not set\n# CONFIG_CRYPTO_DEV_HIFN_795X is not set\n# CONFIG_CRYPTO_DEV_HISI_SEC is not set\n# CONFIG_CRYPTO_DEV_HISI_ZIP is not set\n# CONFIG_CRYPTO_DEV_IMGTEC_HASH is not set\n# CONFIG_CRYPTO_DEV_MARVELL_CESA is not set\n# CONFIG_CRYPTO_DEV_MV_CESA is not set\n# CONFIG_CRYPTO_DEV_MXC_SCC is not set\n# CONFIG_CRYPTO_DEV_MXS_DCP is not set\n# CONFIG_CRYPTO_DEV_NITROX_CNN55XX is not set\n# CONFIG_CRYPTO_DEV_OCTEONTX_CPT is not set\n# CONFIG_CRYPTO_DEV_QAT_C3XXX is not set\n# CONFIG_CRYPTO_DEV_QAT_C3XXXVF is not set\n# CONFIG_CRYPTO_DEV_QAT_C62X is not set\n# CONFIG_CRYPTO_DEV_QAT_C62XVF is not set\n# CONFIG_CRYPTO_DEV_QAT_DH895xCC is not set\n# CONFIG_CRYPTO_DEV_QAT_DH895xCCVF is not set\n# CONFIG_CRYPTO_DEV_QCE is not set\n# CONFIG_CRYPTO_DEV_S5P is not set\n# CONFIG_CRYPTO_DEV_SAFEXCEL is not set\n# CONFIG_CRYPTO_DEV_SAHARA is not set\n# CONFIG_CRYPTO_DEV_SP_PSP is not set\n# CONFIG_CRYPTO_DEV_TALITOS is not set\n# CONFIG_CRYPTO_DEV_VIRTIO is not set\n# CONFIG_CRYPTO_DH is not set\n# CONFIG_CRYPTO_DRBG_CTR is not set\n# CONFIG_CRYPTO_DRBG_HASH is not set\n# CONFIG_CRYPTO_DRBG_MENU is not set\n# CONFIG_CRYPTO_ECB is not set\n# CONFIG_CRYPTO_ECDH is not set\n# CONFIG_CRYPTO_ECHAINIV is not set\n# CONFIG_CRYPTO_ECRDSA is not set\n# CONFIG_CRYPTO_ESSIV is not set\n# CONFIG_CRYPTO_FCRYPT is not set\n# CONFIG_CRYPTO_FIPS is not set\nCONFIG_CRYPTO_GCM=y\nCONFIG_CRYPTO_GF128MUL=y\nCONFIG_CRYPTO_GHASH=y\n# CONFIG_CRYPTO_GHASH_ARM64_CE is not set\n# CONFIG_CRYPTO_GHASH_ARM_CE is not set\n# CONFIG_CRYPTO_GHASH_CLMUL_NI_INTEL is not set\nCONFIG_CRYPTO_HASH=y\nCONFIG_CRYPTO_HASH2=y\n# CONFIG_CRYPTO_HMAC is not set\n# CONFIG_CRYPTO_HW is not set\n# CONFIG_CRYPTO_JITTERENTROPY is not set\n# CONFIG_CRYPTO_KEYWRAP is not set\n# CONFIG_CRYPTO_KHAZAD is not set\nCONFIG_CRYPTO_KPP=y\nCONFIG_CRYPTO_KPP2=y\nCONFIG_CRYPTO_LIB_AES=y\nCONFIG_CRYPTO_LIB_ARC4=y\n# CONFIG_CRYPTO_LIB_BLAKE2S is not set\n# CONFIG_CRYPTO_LIB_CHACHA is not set\n# CONFIG_CRYPTO_LIB_CHACHA20POLY1305 is not set\n# CONFIG_CRYPTO_LIB_CURVE25519 is not set\n# CONFIG_CRYPTO_LIB_POLY1305 is not set\nCONFIG_CRYPTO_LIB_POLY1305_RSIZE=9\n# CONFIG_CRYPTO_LRW is not set\n# CONFIG_CRYPTO_LZ4 is not set\n# CONFIG_CRYPTO_LZ4HC is not set\n# CONFIG_CRYPTO_LZO is not set\nCONFIG_CRYPTO_MANAGER=y\nCONFIG_CRYPTO_MANAGER2=y\nCONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y\n# CONFIG_CRYPTO_MCRYPTD is not set\n# CONFIG_CRYPTO_MD4 is not set\n# CONFIG_CRYPTO_MD5 is not set\n# CONFIG_CRYPTO_MICHAEL_MIC is not set\n# CONFIG_CRYPTO_MORUS1280 is not set\n# CONFIG_CRYPTO_MORUS1280_AVX2 is not set\n# CONFIG_CRYPTO_MORUS1280_SSE2 is not set\n# CONFIG_CRYPTO_MORUS640 is not set\n# CONFIG_CRYPTO_MORUS640_SSE2 is not set\n# CONFIG_CRYPTO_NHPOLY1305_NEON is not set\nCONFIG_CRYPTO_NULL=y\nCONFIG_CRYPTO_NULL2=y\n# CONFIG_CRYPTO_OFB is not set\n# CONFIG_CRYPTO_PCBC is not set\n# CONFIG_CRYPTO_PCOMP is not set\n# CONFIG_CRYPTO_PCOMP2 is not set\nCONFIG_CRYPTO_PCRYPT=y\n# CONFIG_CRYPTO_POLY1305 is not set\n# CONFIG_CRYPTO_POLY1305_ARM is not set\n# CONFIG_CRYPTO_POLY1305_MIPS is not set\n# CONFIG_CRYPTO_POLY1305_NEON is not set\n# CONFIG_CRYPTO_POLY1305_X86_64 is not set\n# CONFIG_CRYPTO_RMD128 is not set\n# CONFIG_CRYPTO_RMD160 is not set\n# CONFIG_CRYPTO_RMD256 is not set\n# CONFIG_CRYPTO_RMD320 is not set\n# CONFIG_CRYPTO_RNG is not set\n# CONFIG_CRYPTO_RSA is not set\n# CONFIG_CRYPTO_SALSA20 is not set\n# CONFIG_CRYPTO_SALSA20_586 is not set\n# CONFIG_CRYPTO_SEED is not set\n# CONFIG_CRYPTO_SEQIV is not set\n# CONFIG_CRYPTO_SERPENT is not set\n# CONFIG_CRYPTO_SHA1 is not set\n# CONFIG_CRYPTO_SHA1_ARM is not set\n# CONFIG_CRYPTO_SHA1_ARM64_CE is not set\n# CONFIG_CRYPTO_SHA1_ARM_CE is not set\n# CONFIG_CRYPTO_SHA1_ARM_NEON is not set\n# CONFIG_CRYPTO_SHA256 is not set\n# CONFIG_CRYPTO_SHA256_ARM is not set\n# CONFIG_CRYPTO_SHA256_ARM64 is not set\n# CONFIG_CRYPTO_SHA2_ARM64_CE is not set\n# CONFIG_CRYPTO_SHA2_ARM_CE is not set\n# CONFIG_CRYPTO_SHA3 is not set\n# CONFIG_CRYPTO_SHA3_ARM64 is not set\n# CONFIG_CRYPTO_SHA512 is not set\n# CONFIG_CRYPTO_SHA512_ARM is not set\n# CONFIG_CRYPTO_SHA512_ARM64 is not set\n# CONFIG_CRYPTO_SHA512_ARM64_CE is not set\n# CONFIG_CRYPTO_SIMD is not set\nCONFIG_CRYPTO_SKCIPHER=y\nCONFIG_CRYPTO_SKCIPHER2=y\n# CONFIG_CRYPTO_SM2 is not set\n# CONFIG_CRYPTO_SM3 is not set\n# CONFIG_CRYPTO_SM3_ARM64_CE is not set\n# CONFIG_CRYPTO_SM4 is not set\n# CONFIG_CRYPTO_SM4_ARM64_CE is not set\n# CONFIG_CRYPTO_SPECK is not set\n# CONFIG_CRYPTO_STATS is not set\n# CONFIG_CRYPTO_STREEBOG is not set\n# CONFIG_CRYPTO_TEA is not set\n# CONFIG_CRYPTO_TEST is not set\n# CONFIG_CRYPTO_TGR192 is not set\n# CONFIG_CRYPTO_TWOFISH is not set\n# CONFIG_CRYPTO_TWOFISH_586 is not set\n# CONFIG_CRYPTO_TWOFISH_COMMON is not set\n# CONFIG_CRYPTO_USER is not set\n# CONFIG_CRYPTO_USER_API_AEAD is not set\n# CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE is not set\n# CONFIG_CRYPTO_USER_API_HASH is not set\n# CONFIG_CRYPTO_USER_API_RNG is not set\n# CONFIG_CRYPTO_USER_API_RNG_CAVP is not set\n# CONFIG_CRYPTO_USER_API_SKCIPHER is not set\n# CONFIG_CRYPTO_VMAC is not set\n# CONFIG_CRYPTO_WP512 is not set\n# CONFIG_CRYPTO_XCBC is not set\n# CONFIG_CRYPTO_XTS is not set\n# CONFIG_CRYPTO_XXHASH is not set\n# CONFIG_CRYPTO_ZLIB is not set\n# CONFIG_CRYPTO_ZSTD is not set\n# CONFIG_CS5535_MFGPT is not set\n# CONFIG_CS89x0 is not set\n# CONFIG_CSD_LOCK_WAIT_DEBUG is not set\n# CONFIG_CUSE is not set\n# CONFIG_CW1200 is not set\n# CONFIG_CXD2880_SPI_DRV is not set\n# CONFIG_CXL_AFU_DRIVER_OPS is not set\n# CONFIG_CXL_BASE is not set\n# CONFIG_CXL_EEH is not set\n# CONFIG_CXL_KERNEL_API is not set\n# CONFIG_CXL_LIB is not set\n# CONFIG_CYPRESS_FIRMWARE is not set\n# CONFIG_DA280 is not set\n# CONFIG_DA311 is not set\n# CONFIG_DAVICOM_PHY is not set\n# CONFIG_DAX is not set\n# CONFIG_DCB is not set\n# CONFIG_DDR is not set\n# CONFIG_DEBUG_ALIGN_RODATA is not set\n# CONFIG_DEBUG_ATOMIC_SLEEP is not set\n# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set\n# CONFIG_DEBUG_BUGVERBOSE is not set\n# CONFIG_DEBUG_CREDENTIALS is not set\n# CONFIG_DEBUG_DEVRES is not set\n# CONFIG_DEBUG_DRIVER is not set\n# CONFIG_DEBUG_EFI is not set\n# CONFIG_DEBUG_FORCE_FUNCTION_ALIGN_32B is not set\n# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set\nCONFIG_DEBUG_FS=y\nCONFIG_DEBUG_FS_ALLOW_ALL=y\n# CONFIG_DEBUG_FS_ALLOW_NONE is not set\n# CONFIG_DEBUG_FS_DISALLOW_MOUNT is not set\n# CONFIG_DEBUG_GPIO is not set\n# CONFIG_DEBUG_HIGHMEM is not set\n# CONFIG_DEBUG_ICEDCC is not set\n# CONFIG_DEBUG_INFO is not set\n# CONFIG_DEBUG_INFO_BTF is not set\n# CONFIG_DEBUG_INFO_COMPRESSED is not set\n# CONFIG_DEBUG_INFO_DWARF4 is not set\nCONFIG_DEBUG_INFO_REDUCED=y\n# CONFIG_DEBUG_INFO_SPLIT is not set\nCONFIG_DEBUG_KERNEL=y\n# CONFIG_DEBUG_KMEMLEAK is not set\n# CONFIG_DEBUG_KOBJECT is not set\n# CONFIG_DEBUG_KOBJECT_RELEASE is not set\n# CONFIG_DEBUG_LIST is not set\n# CONFIG_DEBUG_LL is not set\n# CONFIG_DEBUG_LL_UART_8250 is not set\n# CONFIG_DEBUG_LL_UART_PL01X is not set\n# CONFIG_DEBUG_LOCKDEP is not set\n# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set\n# CONFIG_DEBUG_LOCK_ALLOC is not set\n# CONFIG_DEBUG_MEMORY_INIT is not set\n# CONFIG_DEBUG_MISC is not set\n# CONFIG_DEBUG_MUTEXES is not set\n# CONFIG_DEBUG_NOTIFIERS is not set\n# CONFIG_DEBUG_NX_TEST is not set\n# CONFIG_DEBUG_OBJECTS is not set\n# CONFIG_DEBUG_PAGEALLOC is not set\n# CONFIG_DEBUG_PAGE_REF is not set\n# CONFIG_DEBUG_PERF_USE_VMALLOC is not set\n# CONFIG_DEBUG_PER_CPU_MAPS is not set\n# CONFIG_DEBUG_PINCTRL is not set\n# CONFIG_DEBUG_PI_LIST is not set\n# CONFIG_DEBUG_PLIST is not set\n# CONFIG_DEBUG_PREEMPT is not set\n# CONFIG_DEBUG_RODATA_TEST is not set\n# CONFIG_DEBUG_RSEQ is not set\n# CONFIG_DEBUG_RT_MUTEXES is not set\n# CONFIG_DEBUG_RWSEMS is not set\n# CONFIG_DEBUG_SECTION_MISMATCH is not set\n# CONFIG_DEBUG_SEMIHOSTING is not set\n# CONFIG_DEBUG_SG is not set\n# CONFIG_DEBUG_SHIRQ is not set\n# CONFIG_DEBUG_SLAB is not set\n# CONFIG_DEBUG_SPINLOCK is not set\n# CONFIG_DEBUG_STACKOVERFLOW is not set\n# CONFIG_DEBUG_STACK_USAGE is not set\n# CONFIG_DEBUG_STRICT_USER_COPY_CHECKS is not set\n# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set\n# CONFIG_DEBUG_TIMEKEEPING is not set\n# CONFIG_DEBUG_UART_8250_PALMCHIP is not set\n# CONFIG_DEBUG_UART_8250_WORD is not set\n# CONFIG_DEBUG_UART_BCM63XX is not set\n# CONFIG_DEBUG_UART_FLOW_CONTROL is not set\n# CONFIG_DEBUG_USER is not set\n# CONFIG_DEBUG_VIRTUAL is not set\n# CONFIG_DEBUG_VM is not set\n# CONFIG_DEBUG_VM_PGTABLE is not set\n# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set\n# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set\n# CONFIG_DEBUG_WX is not set\n# CONFIG_DEBUG_ZBOOT is not set\n# CONFIG_DECNET is not set\n# CONFIG_DEFAULT_CODEL is not set\nCONFIG_DEFAULT_CUBIC=y\nCONFIG_DEFAULT_DEADLINE=y\n# CONFIG_DEFAULT_FQ is not set\nCONFIG_DEFAULT_FQ_CODEL=y\nCONFIG_DEFAULT_HOSTNAME=\"(none)\"\nCONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120\nCONFIG_DEFAULT_INIT=\"\"\nCONFIG_DEFAULT_MMAP_MIN_ADDR=4096\nCONFIG_DEFAULT_NET_SCH=\"fq_codel\"\n# CONFIG_DEFAULT_NOOP is not set\n# CONFIG_DEFAULT_PFIFO_FAST is not set\n# CONFIG_DEFAULT_RENO is not set\nCONFIG_DEFAULT_SECURITY=\"\"\nCONFIG_DEFAULT_SECURITY_DAC=y\n# CONFIG_DEFAULT_SECURITY_SELINUX is not set\n# CONFIG_DEFAULT_SFQ is not set\nCONFIG_DEFAULT_TCP_CONG=\"cubic\"\nCONFIG_DEFCONFIG_LIST=\"/lib/modules/$UNAME_RELEASE/.config\"\n# CONFIG_DEFERRED_STRUCT_PAGE_INIT is not set\n# CONFIG_DELL_LAPTOP is not set\n# CONFIG_DELL_RBTN is not set\n# CONFIG_DELL_SMBIOS is not set\n# CONFIG_DELL_SMO8800 is not set\n# CONFIG_DEPRECATED_PARAM_STRUCT is not set\n# CONFIG_DETECT_HUNG_TASK is not set\n# CONFIG_DEVKMEM is not set\n# CONFIG_DEVMEM is not set\nCONFIG_DEVPORT=y\n# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set\n# CONFIG_DEVTMPFS is not set\n# CONFIG_DEVTMPFS_MOUNT is not set\n# CONFIG_DEV_DAX is not set\n# CONFIG_DGAP is not set\n# CONFIG_DGNC is not set\n# CONFIG_DHT11 is not set\n# CONFIG_DISCONTIGMEM_MANUAL is not set\n# CONFIG_DISPLAY_CONNECTOR_ANALOG_TV is not set\n# CONFIG_DISPLAY_CONNECTOR_DVI is not set\n# CONFIG_DISPLAY_CONNECTOR_HDMI is not set\n# CONFIG_DISPLAY_ENCODER_TFP410 is not set\n# CONFIG_DISPLAY_ENCODER_TPD12S015 is not set\n# CONFIG_DISPLAY_PANEL_DPI is not set\n# CONFIG_DISPLAY_PANEL_LGPHILIPS_LB035Q02 is not set\n# CONFIG_DISPLAY_PANEL_TPO_TD028TTEC1 is not set\n# CONFIG_DISPLAY_PANEL_TPO_TD043MTEA1 is not set\n# CONFIG_DL2K is not set\n# CONFIG_DLHL60D is not set\n# CONFIG_DLM is not set\n# CONFIG_DM9000 is not set\n# CONFIG_DMABUF_HEAPS is not set\n# CONFIG_DMABUF_MOVE_NOTIFY is not set\n# CONFIG_DMABUF_SELFTESTS is not set\n# CONFIG_DMADEVICES is not set\n# CONFIG_DMADEVICES_DEBUG is not set\n# CONFIG_DMARD06 is not set\n# CONFIG_DMARD09 is not set\n# CONFIG_DMARD10 is not set\n# CONFIG_DMASCC is not set\n# CONFIG_DMATEST is not set\n# CONFIG_DMA_API_DEBUG is not set\nCONFIG_DMA_COHERENT_POOL=y\nCONFIG_DMA_DECLARE_COHERENT=y\n# CONFIG_DMA_ENGINE is not set\n# CONFIG_DMA_FENCE_TRACE is not set\n# CONFIG_DMA_JZ4780 is not set\nCONFIG_DMA_NONCOHERENT_MMAP=y\n# CONFIG_DMA_NOOP_OPS is not set\n# CONFIG_DMA_PERNUMA_CMA is not set\n# CONFIG_DMA_SHARED_BUFFER is not set\n# CONFIG_DMA_VIRT_OPS is not set\n# CONFIG_DM_CACHE is not set\n# CONFIG_DM_CLONE is not set\n# CONFIG_DM_DEBUG is not set\n# CONFIG_DM_DELAY is not set\n# CONFIG_DM_DUST is not set\n# CONFIG_DM_EBS is not set\n# CONFIG_DM_ERA is not set\n# CONFIG_DM_FLAKEY is not set\n# CONFIG_DM_INTEGRITY is not set\n# CONFIG_DM_LOG_USERSPACE is not set\n# CONFIG_DM_LOG_WRITES is not set\n# CONFIG_DM_MQ_DEFAULT is not set\n# CONFIG_DM_MULTIPATH is not set\n# CONFIG_DM_RAID is not set\n# CONFIG_DM_SWITCH is not set\n# CONFIG_DM_THIN_PROVISIONING is not set\n# CONFIG_DM_UEVENT is not set\n# CONFIG_DM_UNSTRIPED is not set\n# CONFIG_DM_VERITY is not set\n# CONFIG_DM_WRITECACHE is not set\n# CONFIG_DM_ZERO is not set\n# CONFIG_DNET is not set\n# CONFIG_DNOTIFY is not set\n# CONFIG_DNS_RESOLVER is not set\nCONFIG_DOUBLEFAULT=y\n# CONFIG_DP83822_PHY is not set\n# CONFIG_DP83848_PHY is not set\n# CONFIG_DP83867_PHY is not set\n# CONFIG_DP83869_PHY is not set\n# CONFIG_DP83TC811_PHY is not set\n# CONFIG_DPOT_DAC is not set\n# CONFIG_DPS310 is not set\nCONFIG_DQL=y\n# CONFIG_DRAGONRISE_FF is not set\n# CONFIG_DRM is not set\n# CONFIG_DRM_AMDGPU is not set\n# CONFIG_DRM_AMDGPU_CIK is not set\n# CONFIG_DRM_AMDGPU_GART_DEBUGFS is not set\n# CONFIG_DRM_AMDGPU_SI is not set\n# CONFIG_DRM_AMDGPU_USERPTR is not set\n# CONFIG_DRM_AMD_ACP is not set\n# CONFIG_DRM_AMD_DC_DCN2_0 is not set\n# CONFIG_DRM_AMD_DC_DCN3_0 is not set\n# CONFIG_DRM_AMD_DC_HDCP is not set\n# CONFIG_DRM_AMD_DC_SI is not set\n# CONFIG_DRM_ANALOGIX_ANX6345 is not set\n# CONFIG_DRM_ANALOGIX_ANX78XX is not set\n# CONFIG_DRM_ARCPGU is not set\n# CONFIG_DRM_ARMADA is not set\n# CONFIG_DRM_AST is not set\n# CONFIG_DRM_BOCHS is not set\n# CONFIG_DRM_CDNS_DSI is not set\n# CONFIG_DRM_CDNS_MHDP8546 is not set\n# CONFIG_DRM_CHRONTEL_CH7033 is not set\n# CONFIG_DRM_CIRRUS_QEMU is not set\n# CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS is not set\n# CONFIG_DRM_DEBUG_MM is not set\n# CONFIG_DRM_DEBUG_SELFTEST is not set\n# CONFIG_DRM_DISPLAY_CONNECTOR is not set\n# CONFIG_DRM_DP_AUX_CHARDEV is not set\n# CONFIG_DRM_DP_CEC is not set\n# CONFIG_DRM_DUMB_VGA_DAC is not set\n# CONFIG_DRM_DW_HDMI_CEC is not set\n# CONFIG_DRM_ETNAVIV is not set\n# CONFIG_DRM_EXYNOS is not set\n# CONFIG_DRM_FBDEV_EMULATION is not set\n# CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM is not set\n# CONFIG_DRM_FSL_DCU is not set\n# CONFIG_DRM_GM12U320 is not set\n# CONFIG_DRM_GMA500 is not set\n# CONFIG_DRM_HDLCD is not set\n# CONFIG_DRM_HISI_HIBMC is not set\n# CONFIG_DRM_HISI_KIRIN is not set\n# CONFIG_DRM_I2C_ADV7511 is not set\n# CONFIG_DRM_I2C_CH7006 is not set\n# CONFIG_DRM_I2C_NXP_TDA9950 is not set\n# CONFIG_DRM_I2C_NXP_TDA998X is not set\n# CONFIG_DRM_I2C_SIL164 is not set\n# CONFIG_DRM_I915 is not set\n# CONFIG_DRM_KOMEDA is not set\n# CONFIG_DRM_LEGACY is not set\n# CONFIG_DRM_LIB_RANDOM is not set\n# CONFIG_DRM_LIMA is not set\n# CONFIG_DRM_LOAD_EDID_FIRMWARE is not set\n# CONFIG_DRM_LONTIUM_LT9611 is not set\n# CONFIG_DRM_LVDS_CODEC is not set\n# CONFIG_DRM_LVDS_ENCODER is not set\n# CONFIG_DRM_MALI_DISPLAY is not set\n# CONFIG_DRM_MCDE is not set\n# CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW is not set\n# CONFIG_DRM_MGAG200 is not set\n# CONFIG_DRM_MXSFB is not set\n# CONFIG_DRM_NOUVEAU is not set\n# CONFIG_DRM_NWL_MIPI_DSI is not set\n# CONFIG_DRM_NXP_PTN3460 is not set\n# CONFIG_DRM_OMAP is not set\n# CONFIG_DRM_PANEL_ARM_VERSATILE is not set\n# CONFIG_DRM_PANEL_ASUS_Z00T_TM5P5_NT35596 is not set\n# CONFIG_DRM_PANEL_BOE_HIMAX8279D is not set\n# CONFIG_DRM_PANEL_BOE_TV101WUM_NL6 is not set\n# CONFIG_DRM_PANEL_ELIDA_KD35T133 is not set\n# CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02 is not set\n# CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D is not set\n# CONFIG_DRM_PANEL_ILITEK_IL9322 is not set\n# CONFIG_DRM_PANEL_ILITEK_ILI9881C is not set\n# CONFIG_DRM_PANEL_INNOLUX_P079ZCA is not set\n# CONFIG_DRM_PANEL_JDI_LT070ME05000 is not set\n# CONFIG_DRM_PANEL_KINGDISPLAY_KD097D04 is not set\n# CONFIG_DRM_PANEL_LEADTEK_LTK050H3146W is not set\n# CONFIG_DRM_PANEL_LEADTEK_LTK500HD1829 is not set\n# CONFIG_DRM_PANEL_LG_LB035Q02 is not set\n# CONFIG_DRM_PANEL_LG_LG4573 is not set\n# CONFIG_DRM_PANEL_LVDS is not set\n# CONFIG_DRM_PANEL_MANTIX_MLAF057WE51 is not set\n# CONFIG_DRM_PANEL_NEC_NL8048HL11 is not set\n# CONFIG_DRM_PANEL_NOVATEK_NT35510 is not set\n# CONFIG_DRM_PANEL_NOVATEK_NT39016 is not set\n# CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO is not set\n# CONFIG_DRM_PANEL_ORISETECH_OTM8009A is not set\n# CONFIG_DRM_PANEL_OSD_OSD101T2587_53TS is not set\n# CONFIG_DRM_PANEL_PANASONIC_VVX10F034N00 is not set\n# CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN is not set\n# CONFIG_DRM_PANEL_RAYDIUM_RM67191 is not set\n# CONFIG_DRM_PANEL_RAYDIUM_RM68200 is not set\n# CONFIG_DRM_PANEL_ROCKTECH_JH057N00900 is not set\n# CONFIG_DRM_PANEL_RONBO_RB070D30 is not set\n# CONFIG_DRM_PANEL_SAMSUNG_LD9040 is not set\n# CONFIG_DRM_PANEL_SAMSUNG_S6D16D0 is not set\n# CONFIG_DRM_PANEL_SAMSUNG_S6E3HA2 is not set\n# CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03 is not set\n# CONFIG_DRM_PANEL_SAMSUNG_S6E63M0 is not set\n# CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01 is not set\n# CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0 is not set\n# CONFIG_DRM_PANEL_SEIKO_43WVF1G is not set\n# CONFIG_DRM_PANEL_SHARP_LQ101R1SX01 is not set\n# CONFIG_DRM_PANEL_SHARP_LS037V7DW01 is not set\n# CONFIG_DRM_PANEL_SHARP_LS043T1LE01 is not set\n# CONFIG_DRM_PANEL_SIMPLE is not set\n# CONFIG_DRM_PANEL_SITRONIX_ST7701 is not set\n# CONFIG_DRM_PANEL_SITRONIX_ST7703 is not set\n# CONFIG_DRM_PANEL_SITRONIX_ST7789V is not set\n# CONFIG_DRM_PANEL_SONY_ACX424AKP is not set\n# CONFIG_DRM_PANEL_SONY_ACX565AKM is not set\n# CONFIG_DRM_PANEL_TPO_TD028TTEC1 is not set\n# CONFIG_DRM_PANEL_TPO_TD043MTEA1 is not set\n# CONFIG_DRM_PANEL_TPO_TPG110 is not set\n# CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA is not set\n# CONFIG_DRM_PANEL_VISIONOX_RM69299 is not set\n# CONFIG_DRM_PANEL_XINPENG_XPP055C272 is not set\n# CONFIG_DRM_PANFROST is not set\n# CONFIG_DRM_PARADE_PS8622 is not set\n# CONFIG_DRM_PARADE_PS8640 is not set\n# CONFIG_DRM_PL111 is not set\n# CONFIG_DRM_QXL is not set\n# CONFIG_DRM_RADEON is not set\n# CONFIG_DRM_RADEON_USERPTR is not set\n# CONFIG_DRM_RCAR_DW_HDMI is not set\n# CONFIG_DRM_RCAR_LVDS is not set\n# CONFIG_DRM_SII902X is not set\n# CONFIG_DRM_SII9234 is not set\n# CONFIG_DRM_SIL_SII8620 is not set\n# CONFIG_DRM_SIMPLE_BRIDGE is not set\n# CONFIG_DRM_STI is not set\n# CONFIG_DRM_STM is not set\n# CONFIG_DRM_SUN4I is not set\n# CONFIG_DRM_THINE_THC63LVD1024 is not set\n# CONFIG_DRM_TIDSS is not set\n# CONFIG_DRM_TILCDC is not set\n# CONFIG_DRM_TINYDRM is not set\n# CONFIG_DRM_TI_SN65DSI86 is not set\n# CONFIG_DRM_TI_TFP410 is not set\n# CONFIG_DRM_TI_TPD12S015 is not set\n# CONFIG_DRM_TOSHIBA_TC358762 is not set\n# CONFIG_DRM_TOSHIBA_TC358764 is not set\n# CONFIG_DRM_TOSHIBA_TC358767 is not set\n# CONFIG_DRM_TOSHIBA_TC358768 is not set\n# CONFIG_DRM_TOSHIBA_TC358775 is not set\n# CONFIG_DRM_TVE200 is not set\n# CONFIG_DRM_UDL is not set\n# CONFIG_DRM_VBOXVIDEO is not set\n# CONFIG_DRM_VC4_HDMI_CEC is not set\n# CONFIG_DRM_VGEM is not set\n# CONFIG_DRM_VIRTIO_GPU is not set\n# CONFIG_DRM_VKMS is not set\n# CONFIG_DRM_VMWGFX is not set\n# CONFIG_DRM_XEN is not set\n# CONFIG_DS1682 is not set\n# CONFIG_DS1803 is not set\n# CONFIG_DS4424 is not set\n# CONFIG_DST_CACHE is not set\n# CONFIG_DTLK is not set\n# CONFIG_DUMMY is not set\nCONFIG_DUMMY_CONSOLE_COLUMNS=80\nCONFIG_DUMMY_CONSOLE_ROWS=25\n# CONFIG_DUMMY_IRQ is not set\n# CONFIG_DVB_A8293 is not set\n# CONFIG_DVB_AF9013 is not set\n# CONFIG_DVB_AF9033 is not set\n# CONFIG_DVB_AS102 is not set\n# CONFIG_DVB_ASCOT2E is not set\n# CONFIG_DVB_ATBM8830 is not set\n# CONFIG_DVB_AU8522_DTV is not set\n# CONFIG_DVB_AU8522_V4L is not set\n# CONFIG_DVB_B2C2_FLEXCOP_USB is not set\n# CONFIG_DVB_BCM3510 is not set\n# CONFIG_DVB_CORE is not set\n# CONFIG_DVB_CX22700 is not set\n# CONFIG_DVB_CX22702 is not set\n# CONFIG_DVB_CX24110 is not set\n# CONFIG_DVB_CX24116 is not set\n# CONFIG_DVB_CX24117 is not set\n# CONFIG_DVB_CX24120 is not set\n# CONFIG_DVB_CX24123 is not set\n# CONFIG_DVB_CXD2099 is not set\n# CONFIG_DVB_CXD2820R is not set\n# CONFIG_DVB_CXD2841ER is not set\n# CONFIG_DVB_CXD2880 is not set\n# CONFIG_DVB_DEMUX_SECTION_LOSS_LOG is not set\n# CONFIG_DVB_DIB3000MB is not set\n# CONFIG_DVB_DIB3000MC is not set\n# CONFIG_DVB_DIB7000M is not set\n# CONFIG_DVB_DIB7000P is not set\n# CONFIG_DVB_DIB8000 is not set\n# CONFIG_DVB_DIB9000 is not set\n# CONFIG_DVB_DRX39XYJ is not set\n# CONFIG_DVB_DRXD is not set\n# CONFIG_DVB_DRXK is not set\n# CONFIG_DVB_DS3000 is not set\n# CONFIG_DVB_DUMMY_FE is not set\n# CONFIG_DVB_DYNAMIC_MINORS is not set\n# CONFIG_DVB_EC100 is not set\n# CONFIG_DVB_FIREDTV is not set\n# CONFIG_DVB_HELENE is not set\n# CONFIG_DVB_HORUS3A is not set\n# CONFIG_DVB_ISL6405 is not set\n# CONFIG_DVB_ISL6421 is not set\n# CONFIG_DVB_ISL6423 is not set\n# CONFIG_DVB_IX2505V is not set\n# CONFIG_DVB_L64781 is not set\n# CONFIG_DVB_LG2160 is not set\n# CONFIG_DVB_LGDT3305 is not set\n# CONFIG_DVB_LGDT3306A is not set\n# CONFIG_DVB_LGDT330X is not set\n# CONFIG_DVB_LGS8GL5 is not set\n# CONFIG_DVB_LGS8GXX is not set\n# CONFIG_DVB_LNBH25 is not set\n# CONFIG_DVB_LNBH29 is not set\n# CONFIG_DVB_LNBP21 is not set\n# CONFIG_DVB_LNBP22 is not set\n# CONFIG_DVB_M88DS3103 is not set\n# CONFIG_DVB_M88RS2000 is not set\nCONFIG_DVB_MAX_ADAPTERS=16\n# CONFIG_DVB_MB86A16 is not set\n# CONFIG_DVB_MB86A20S is not set\n# CONFIG_DVB_MMAP is not set\n# CONFIG_DVB_MN88443X is not set\n# CONFIG_DVB_MN88472 is not set\n# CONFIG_DVB_MN88473 is not set\n# CONFIG_DVB_MT312 is not set\n# CONFIG_DVB_MT352 is not set\n# CONFIG_DVB_MXL5XX is not set\n# CONFIG_DVB_NET is not set\n# CONFIG_DVB_NXT200X is not set\n# CONFIG_DVB_NXT6000 is not set\n# CONFIG_DVB_OR51132 is not set\n# CONFIG_DVB_OR51211 is not set\n# CONFIG_DVB_PLATFORM_DRIVERS is not set\n# CONFIG_DVB_PLL is not set\n# CONFIG_DVB_RTL2830 is not set\n# CONFIG_DVB_RTL2832 is not set\n# CONFIG_DVB_RTL2832_SDR is not set\n# CONFIG_DVB_S5H1409 is not set\n# CONFIG_DVB_S5H1411 is not set\n# CONFIG_DVB_S5H1420 is not set\n# CONFIG_DVB_S5H1432 is not set\n# CONFIG_DVB_S921 is not set\n# CONFIG_DVB_SI2165 is not set\n# CONFIG_DVB_SI2168 is not set\n# CONFIG_DVB_SI21XX is not set\n# CONFIG_DVB_SP2 is not set\n# CONFIG_DVB_SP8870 is not set\n# CONFIG_DVB_SP887X is not set\n# CONFIG_DVB_STB0899 is not set\n# CONFIG_DVB_STB6000 is not set\n# CONFIG_DVB_STB6100 is not set\n# CONFIG_DVB_STV0288 is not set\n# CONFIG_DVB_STV0297 is not set\n# CONFIG_DVB_STV0299 is not set\n# CONFIG_DVB_STV0367 is not set\n# CONFIG_DVB_STV0900 is not set\n# CONFIG_DVB_STV090x is not set\n# CONFIG_DVB_STV0910 is not set\n# CONFIG_DVB_STV6110 is not set\n# CONFIG_DVB_STV6110x is not set\n# CONFIG_DVB_STV6111 is not set\n# CONFIG_DVB_TC90522 is not set\n# CONFIG_DVB_TDA10021 is not set\n# CONFIG_DVB_TDA10023 is not set\n# CONFIG_DVB_TDA10048 is not set\n# CONFIG_DVB_TDA1004X is not set\n# CONFIG_DVB_TDA10071 is not set\n# CONFIG_DVB_TDA10086 is not set\n# CONFIG_DVB_TDA18271C2DD is not set\n# CONFIG_DVB_TDA665x is not set\n# CONFIG_DVB_TDA8083 is not set\n# CONFIG_DVB_TDA8261 is not set\n# CONFIG_DVB_TDA826X is not set\n# CONFIG_DVB_TEST_DRIVERS is not set\n# CONFIG_DVB_TS2020 is not set\n# CONFIG_DVB_TTUSB_BUDGET is not set\n# CONFIG_DVB_TTUSB_DEC is not set\n# CONFIG_DVB_TUA6100 is not set\n# CONFIG_DVB_TUNER_CX24113 is not set\n# CONFIG_DVB_TUNER_DIB0070 is not set\n# CONFIG_DVB_TUNER_DIB0090 is not set\n# CONFIG_DVB_TUNER_ITD1000 is not set\n# CONFIG_DVB_ULE_DEBUG is not set\n# CONFIG_DVB_USB_V2 is not set\n# CONFIG_DVB_VES1820 is not set\n# CONFIG_DVB_VES1X93 is not set\n# CONFIG_DVB_ZD1301_DEMOD is not set\n# CONFIG_DVB_ZL10036 is not set\n# CONFIG_DVB_ZL10039 is not set\n# CONFIG_DVB_ZL10353 is not set\n# CONFIG_DWC_XLGMAC is not set\n# CONFIG_DWMAC_DWC_QOS_ETH is not set\n# CONFIG_DWMAC_INTEL_PLAT is not set\n# CONFIG_DWMAC_IPQ806X is not set\n# CONFIG_DWMAC_LPC18XX is not set\n# CONFIG_DWMAC_MESON is not set\n# CONFIG_DWMAC_ROCKCHIP is not set\n# CONFIG_DWMAC_SOCFPGA is not set\n# CONFIG_DWMAC_STI is not set\n# CONFIG_DW_AXI_DMAC is not set\n# CONFIG_DW_DMAC is not set\n# CONFIG_DW_DMAC_PCI is not set\n# CONFIG_DW_EDMA is not set\n# CONFIG_DW_EDMA_PCIE is not set\n# CONFIG_DW_WATCHDOG is not set\n# CONFIG_DYNAMIC_DEBUG is not set\nCONFIG_DYNAMIC_DEBUG_CORE=y\n# CONFIG_E100 is not set\n# CONFIG_E1000 is not set\n# CONFIG_E1000E is not set\n# CONFIG_E1000E_HWTS is not set\n# CONFIG_EARLY_PRINTK_8250 is not set\n# CONFIG_EARLY_PRINTK_USB_XDBC is not set\n# CONFIG_EBC_C384_WDT is not set\n# CONFIG_ECHO is not set\n# CONFIG_ECRYPT_FS is not set\n# CONFIG_EDAC is not set\n# CONFIG_EEEPC_LAPTOP is not set\n# CONFIG_EEPROM_93CX6 is not set\n# CONFIG_EEPROM_93XX46 is not set\n# CONFIG_EEPROM_AT24 is not set\n# CONFIG_EEPROM_AT25 is not set\n# CONFIG_EEPROM_DIGSY_MTC_CFG is not set\n# CONFIG_EEPROM_EE1004 is not set\n# CONFIG_EEPROM_IDT_89HPESX is not set\n# CONFIG_EEPROM_LEGACY is not set\n# CONFIG_EEPROM_MAX6875 is not set\n# CONFIG_EFI is not set\nCONFIG_EFI_PARTITION=y\n# CONFIG_EFI_VARS_PSTORE is not set\n# CONFIG_EFS_FS is not set\nCONFIG_ELFCORE=y\n# CONFIG_ELF_CORE is not set\n# CONFIG_EMAC_ROCKCHIP is not set\nCONFIG_EMBEDDED=y\n# CONFIG_EM_TIMER_STI is not set\n# CONFIG_ENABLE_MUST_CHECK is not set\nCONFIG_ENABLE_WARN_DEPRECATED=y\n# CONFIG_ENA_ETHERNET is not set\n# CONFIG_ENC28J60 is not set\n# CONFIG_ENCLOSURE_SERVICES is not set\n# CONFIG_ENCRYPTED_KEYS is not set\n# CONFIG_ENCX24J600 is not set\n# CONFIG_ENERGY_MODEL is not set\n# CONFIG_ENIC is not set\n# CONFIG_ENVELOPE_DETECTOR is not set\n# CONFIG_EPAPR_PARAVIRT is not set\n# CONFIG_EPIC100 is not set\nCONFIG_EPOLL=y\n# CONFIG_EQUALIZER is not set\n# CONFIG_EROFS_FS is not set\n# CONFIG_ET131X is not set\nCONFIG_ETHERNET=y\n# CONFIG_ETHOC is not set\nCONFIG_ETHTOOL_NETLINK=y\nCONFIG_EVENTFD=y\n# CONFIG_EVM is not set\n# CONFIG_EXFAT_FS is not set\nCONFIG_EXPERT=y\nCONFIG_EXPORTFS=y\n# CONFIG_EXPORTFS_BLOCK_OPS is not set\n# CONFIG_EXT2_FS is not set\nCONFIG_EXT2_FS_XATTR=y\n# CONFIG_EXT3_FS is not set\n# CONFIG_EXT4_DEBUG is not set\n# CONFIG_EXT4_ENCRYPTION is not set\n# CONFIG_EXT4_FS is not set\n# CONFIG_EXT4_FS_POSIX_ACL is not set\n# CONFIG_EXT4_FS_SECURITY is not set\nCONFIG_EXT4_USE_FOR_EXT2=y\n# CONFIG_EXTCON is not set\n# CONFIG_EXTCON_ADC_JACK is not set\n# CONFIG_EXTCON_ARIZONA is not set\n# CONFIG_EXTCON_AXP288 is not set\n# CONFIG_EXTCON_FSA9480 is not set\n# CONFIG_EXTCON_GPIO is not set\n# CONFIG_EXTCON_INTEL_INT3496 is not set\n# CONFIG_EXTCON_MAX3355 is not set\n# CONFIG_EXTCON_PTN5150 is not set\n# CONFIG_EXTCON_QCOM_SPMI_MISC is not set\n# CONFIG_EXTCON_RT8973A is not set\n# CONFIG_EXTCON_SM5502 is not set\n# CONFIG_EXTCON_USB_GPIO is not set\nCONFIG_EXTRA_FIRMWARE=\"\"\nCONFIG_EXTRA_TARGETS=\"\"\n# CONFIG_EXYNOS_ADC is not set\n# CONFIG_EXYNOS_VIDEO is not set\n# CONFIG_EZCHIP_NPS_MANAGEMENT_ENET is not set\n# CONFIG_EZX_PCAP is not set\n# CONFIG_F2FS_CHECK_FS is not set\n# CONFIG_F2FS_FAULT_INJECTION is not set\n# CONFIG_F2FS_FS is not set\n# CONFIG_F2FS_FS_COMPRESSION is not set\n# CONFIG_F2FS_FS_ENCRYPTION is not set\n# CONFIG_F2FS_FS_POSIX_ACL is not set\n# CONFIG_F2FS_FS_SECURITY is not set\nCONFIG_F2FS_FS_XATTR=y\n# CONFIG_F2FS_IO_TRACE is not set\nCONFIG_F2FS_STAT_FS=y\n# CONFIG_FAILOVER is not set\n# CONFIG_FAIR_GROUP_SCHED is not set\n# CONFIG_FANOTIFY is not set\n# CONFIG_FANOTIFY_ACCESS_PERMISSIONS is not set\nCONFIG_FAT_DEFAULT_CODEPAGE=437\nCONFIG_FAT_DEFAULT_IOCHARSET=\"iso8859-1\"\n# CONFIG_FAT_DEFAULT_UTF8 is not set\n# CONFIG_FAT_FS is not set\n# CONFIG_FAULT_INJECTION is not set\n# CONFIG_FB is not set\n# CONFIG_FB_3DFX is not set\n# CONFIG_FB_ARC is not set\n# CONFIG_FB_ARK is not set\n# CONFIG_FB_ARMCLCD is not set\n# CONFIG_FB_ASILIANT is not set\n# CONFIG_FB_ATY is not set\n# CONFIG_FB_ATY128 is not set\n# CONFIG_FB_AUO_K190X is not set\n# CONFIG_FB_BACKLIGHT is not set\n# CONFIG_FB_BIG_ENDIAN is not set\n# CONFIG_FB_BOOT_VESA_SUPPORT is not set\n# CONFIG_FB_BOTH_ENDIAN is not set\n# CONFIG_FB_BROADSHEET is not set\n# CONFIG_FB_CARMINE is not set\n# CONFIG_FB_CFB_COPYAREA is not set\n# CONFIG_FB_CFB_FILLRECT is not set\n# CONFIG_FB_CFB_IMAGEBLIT is not set\n# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set\n# CONFIG_FB_CIRRUS is not set\n# CONFIG_FB_CYBER2000 is not set\n# CONFIG_FB_DA8XX is not set\n# CONFIG_FB_DDC is not set\n# CONFIG_FB_FLEX is not set\n# CONFIG_FB_FOREIGN_ENDIAN is not set\n# CONFIG_FB_FSL_DIU is not set\n# CONFIG_FB_GEODE is not set\n# CONFIG_FB_GOLDFISH is not set\n# CONFIG_FB_HGA is not set\n# CONFIG_FB_I740 is not set\n# CONFIG_FB_IBM_GXT4500 is not set\n# CONFIG_FB_IMSTT is not set\n# CONFIG_FB_IMX is not set\n# CONFIG_FB_KYRO is not set\n# CONFIG_FB_LE80578 is not set\n# CONFIG_FB_LITTLE_ENDIAN is not set\n# CONFIG_FB_MACMODES is not set\n# CONFIG_FB_MATROX is not set\n# CONFIG_FB_MB862XX is not set\n# CONFIG_FB_METRONOME is not set\n# CONFIG_FB_MODE_HELPERS is not set\n# CONFIG_FB_MXS is not set\n# CONFIG_FB_N411 is not set\n# CONFIG_FB_NEOMAGIC is not set\nCONFIG_FB_NOTIFY=y\n# CONFIG_FB_NVIDIA is not set\n# CONFIG_FB_OF is not set\n# CONFIG_FB_OMAP2 is not set\n# CONFIG_FB_OPENCORES is not set\n# CONFIG_FB_PM2 is not set\n# CONFIG_FB_PM3 is not set\n# CONFIG_FB_PS3 is not set\n# CONFIG_FB_PXA is not set\n# CONFIG_FB_RADEON is not set\n# CONFIG_FB_RIVA is not set\n# CONFIG_FB_S1D13XXX is not set\n# CONFIG_FB_S3 is not set\n# CONFIG_FB_SAVAGE is not set\n# CONFIG_FB_SIMPLE is not set\n# CONFIG_FB_SIS is not set\n# CONFIG_FB_SM712 is not set\n# CONFIG_FB_SM750 is not set\n# CONFIG_FB_SMSCUFX is not set\n# CONFIG_FB_SSD1307 is not set\n# CONFIG_FB_SVGALIB is not set\n# CONFIG_FB_SYS_COPYAREA is not set\n# CONFIG_FB_SYS_FILLRECT is not set\n# CONFIG_FB_SYS_FOPS is not set\n# CONFIG_FB_SYS_IMAGEBLIT is not set\n# CONFIG_FB_TFT is not set\n# CONFIG_FB_TFT_AGM1264K_FL is not set\n# CONFIG_FB_TFT_BD663474 is not set\n# CONFIG_FB_TFT_FBTFT_DEVICE is not set\n# CONFIG_FB_TFT_HX8340BN is not set\n# CONFIG_FB_TFT_HX8347D is not set\n# CONFIG_FB_TFT_HX8353D is not set\n# CONFIG_FB_TFT_HX8357D is not set\n# CONFIG_FB_TFT_ILI9163 is not set\n# CONFIG_FB_TFT_ILI9320 is not set\n# CONFIG_FB_TFT_ILI9325 is not set\n# CONFIG_FB_TFT_ILI9340 is not set\n# CONFIG_FB_TFT_ILI9341 is not set\n# CONFIG_FB_TFT_ILI9481 is not set\n# CONFIG_FB_TFT_ILI9486 is not set\n# CONFIG_FB_TFT_PCD8544 is not set\n# CONFIG_FB_TFT_RA8875 is not set\n# CONFIG_FB_TFT_S6D02A1 is not set\n# CONFIG_FB_TFT_S6D1121 is not set\n# CONFIG_FB_TFT_SEPS525 is not set\n# CONFIG_FB_TFT_SH1106 is not set\n# CONFIG_FB_TFT_SSD1289 is not set\n# CONFIG_FB_TFT_SSD1305 is not set\n# CONFIG_FB_TFT_SSD1306 is not set\n# CONFIG_FB_TFT_SSD1325 is not set\n# CONFIG_FB_TFT_SSD1331 is not set\n# CONFIG_FB_TFT_SSD1351 is not set\n# CONFIG_FB_TFT_ST7735R is not set\n# CONFIG_FB_TFT_ST7789V is not set\n# CONFIG_FB_TFT_TINYLCD is not set\n# CONFIG_FB_TFT_TLS8204 is not set\n# CONFIG_FB_TFT_UC1611 is not set\n# CONFIG_FB_TFT_UC1701 is not set\n# CONFIG_FB_TFT_UPD161704 is not set\n# CONFIG_FB_TFT_WATTEROTT is not set\n# CONFIG_FB_TILEBLITTING is not set\n# CONFIG_FB_TMIO is not set\n# CONFIG_FB_TRIDENT is not set\n# CONFIG_FB_UDL is not set\n# CONFIG_FB_UVESA is not set\n# CONFIG_FB_VGA16 is not set\n# CONFIG_FB_VIA is not set\n# CONFIG_FB_VIRTUAL is not set\n# CONFIG_FB_VOODOO1 is not set\n# CONFIG_FB_VT8623 is not set\n# CONFIG_FB_XGI is not set\n# CONFIG_FCOE is not set\n# CONFIG_FCOE_FNIC is not set\n# CONFIG_FDDI is not set\n# CONFIG_FEALNX is not set\n# CONFIG_FENCE_TRACE is not set\n# CONFIG_FHANDLE is not set\nCONFIG_FIB_RULES=y\n# CONFIG_FIELDBUS_DEV is not set\nCONFIG_FILE_LOCKING=y\n# CONFIG_FIND_BIT_BENCHMARK is not set\n# CONFIG_FIREWIRE is not set\n# CONFIG_FIREWIRE_NOSY is not set\n# CONFIG_FIREWIRE_SERIAL is not set\n# CONFIG_FIRMWARE_EDID is not set\n# CONFIG_FIRMWARE_IN_KERNEL is not set\n# CONFIG_FIRMWARE_MEMMAP is not set\n# CONFIG_FIT_PARTITION is not set\n# CONFIG_FIXED_PHY is not set\nCONFIG_FLATMEM=y\nCONFIG_FLATMEM_MANUAL=y\nCONFIG_FLAT_NODE_MEM_MAP=y\n# CONFIG_FM10K is not set\n# CONFIG_FMC is not set\n# CONFIG_FONTS is not set\n# CONFIG_FONT_6x8 is not set\n# CONFIG_FONT_TER16x32 is not set\n# CONFIG_FORCEDETH is not set\nCONFIG_FORCE_MAX_ZONEORDER=11\nCONFIG_FORTIFY_SOURCE=y\n# CONFIG_FPGA is not set\n# CONFIG_FRAMEBUFFER_CONSOLE is not set\n# CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER is not set\n# CONFIG_FRAMEBUFFER_CONSOLE_LEGACY_ACCELERATION is not set\n# CONFIG_FRAME_POINTER is not set\nCONFIG_FRAME_WARN=1024\n# CONFIG_FREEZER is not set\n# CONFIG_FRONTSWAP is not set\n# CONFIG_FSCACHE is not set\n# CONFIG_FSI is not set\n# CONFIG_FSL_EDMA is not set\n# CONFIG_FSL_ENETC is not set\n# CONFIG_FSL_ENETC_MDIO is not set\n# CONFIG_FSL_ENETC_VF is not set\n# CONFIG_FSL_ERRATUM_A008585 is not set\n# CONFIG_FSL_MC_BUS is not set\n# CONFIG_FSL_PQ_MDIO is not set\n# CONFIG_FSL_QDMA is not set\n# CONFIG_FSL_RCPM is not set\n# CONFIG_FSL_XGMAC_MDIO is not set\nCONFIG_FSNOTIFY=y\n# CONFIG_FS_DAX is not set\n# CONFIG_FS_ENCRYPTION is not set\n# CONFIG_FS_POSIX_ACL is not set\n# CONFIG_FS_VERITY is not set\n# CONFIG_FTGMAC100 is not set\n# CONFIG_FTL is not set\n# CONFIG_FTMAC100 is not set\n# CONFIG_FTRACE is not set\n# CONFIG_FTRACE_STARTUP_TEST is not set\n# CONFIG_FTR_FIXUP_SELFTEST is not set\n# CONFIG_FTWDT010_WATCHDOG is not set\n# CONFIG_FUJITSU_ERRATUM_010001 is not set\n# CONFIG_FUJITSU_ES is not set\n# CONFIG_FUJITSU_LAPTOP is not set\n# CONFIG_FUJITSU_TABLET is not set\n# CONFIG_FUNCTION_TRACER is not set\n# CONFIG_FUSE_FS is not set\n# CONFIG_FUSION is not set\n# CONFIG_FUSION_FC is not set\n# CONFIG_FUSION_SAS is not set\n# CONFIG_FUSION_SPI is not set\nCONFIG_FUTEX=y\nCONFIG_FUTEX_PI=y\n# CONFIG_FW_CFG_SYSFS is not set\nCONFIG_FW_LOADER=y\n# CONFIG_FW_LOADER_COMPRESS is not set\nCONFIG_FW_LOADER_USER_HELPER=y\nCONFIG_FW_LOADER_USER_HELPER_FALLBACK=y\n# CONFIG_FXAS21002C is not set\n# CONFIG_FXOS8700_I2C is not set\n# CONFIG_FXOS8700_SPI is not set\nCONFIG_GACT_PROB=y\n# CONFIG_GADGET_UAC1 is not set\n# CONFIG_GAMEPORT is not set\n# CONFIG_GATEWORKS_GW16083 is not set\n# CONFIG_GCC_PLUGINS is not set\n# CONFIG_GCOV is not set\n# CONFIG_GCOV_KERNEL is not set\n# CONFIG_GDB_SCRIPTS is not set\n# CONFIG_GEMINI_ETHERNET is not set\n# CONFIG_GENERIC_ADC_BATTERY is not set\n# CONFIG_GENERIC_ADC_THERMAL is not set\nCONFIG_GENERIC_CALIBRATE_DELAY=y\n# CONFIG_GENERIC_CPU_DEVICES is not set\nCONFIG_GENERIC_HWEIGHT=y\n# CONFIG_GENERIC_IRQ_DEBUGFS is not set\nCONFIG_GENERIC_IRQ_IPI=y\nCONFIG_GENERIC_IRQ_PROBE=y\nCONFIG_GENERIC_NET_UTILS=y\n# CONFIG_GENERIC_PHY is not set\nCONFIG_GENERIC_PTDUMP=y\nCONFIG_GENERIC_VDSO_TIME_NS=y\n# CONFIG_GENEVE is not set\n# CONFIG_GENWQE is not set\n# CONFIG_GFS2_FS is not set\n# CONFIG_GIGASET_CAPI is not set\n# CONFIG_GIGASET_DEBUG is not set\n# CONFIG_GIGASET_DUMMYLL is not set\n# CONFIG_GLOB_SELFTEST is not set\n# CONFIG_GNSS is not set\n# CONFIG_GOLDFISH is not set\n# CONFIG_GOOGLE_COREBOOT_TABLE is not set\n# CONFIG_GOOGLE_FIRMWARE is not set\n# CONFIG_GOOGLE_FRAMEBUFFER_COREBOOT is not set\n# CONFIG_GOOGLE_MEMCONSOLE_COREBOOT is not set\n# CONFIG_GOOGLE_MEMCONSOLE_X86_LEGACY is not set\n# CONFIG_GOOGLE_SMI is not set\n# CONFIG_GOOGLE_VPD is not set\n# CONFIG_GP2AP002 is not set\n# CONFIG_GP2AP020A00F is not set\n# CONFIG_GPD_POCKET_FAN is not set\n# CONFIG_GPIOLIB is not set\nCONFIG_GPIOLIB_FASTPATH_LIMIT=512\n# CONFIG_GPIO_104_DIO_48E is not set\n# CONFIG_GPIO_104_IDIO_16 is not set\n# CONFIG_GPIO_104_IDI_48 is not set\n# CONFIG_GPIO_74X164 is not set\n# CONFIG_GPIO_74XX_MMIO is not set\n# CONFIG_GPIO_ADNP is not set\n# CONFIG_GPIO_ADP5588 is not set\n# CONFIG_GPIO_AGGREGATOR is not set\n# CONFIG_GPIO_ALTERA is not set\n# CONFIG_GPIO_AMD8111 is not set\n# CONFIG_GPIO_AMDPT is not set\n# CONFIG_GPIO_AMD_FCH is not set\n# CONFIG_GPIO_BCM_KONA is not set\n# CONFIG_GPIO_BT8XX is not set\n# CONFIG_GPIO_CADENCE is not set\n# CONFIG_GPIO_CASCADE is not set\n# CONFIG_GPIO_CDEV is not set\n# CONFIG_GPIO_CDEV_V1 is not set\n# CONFIG_GPIO_CS5535 is not set\n# CONFIG_GPIO_DWAPB is not set\n# CONFIG_GPIO_EM is not set\n# CONFIG_GPIO_EXAR is not set\n# CONFIG_GPIO_F7188X is not set\n# CONFIG_GPIO_FTGPIO010 is not set\n# CONFIG_GPIO_GENERIC_PLATFORM is not set\n# CONFIG_GPIO_GPIO_MM is not set\n# CONFIG_GPIO_GRGPIO is not set\n# CONFIG_GPIO_GW_PLD is not set\n# CONFIG_GPIO_HLWD is not set\n# CONFIG_GPIO_ICH is not set\n# CONFIG_GPIO_IT87 is not set\n# CONFIG_GPIO_LOGICVC is not set\n# CONFIG_GPIO_LYNXPOINT is not set\n# CONFIG_GPIO_MAX3191X is not set\n# CONFIG_GPIO_MAX7300 is not set\n# CONFIG_GPIO_MAX7301 is not set\n# CONFIG_GPIO_MAX732X is not set\n# CONFIG_GPIO_MB86S7X is not set\n# CONFIG_GPIO_MC33880 is not set\n# CONFIG_GPIO_MCP23S08 is not set\n# CONFIG_GPIO_ML_IOH is not set\n# CONFIG_GPIO_MOCKUP is not set\n# CONFIG_GPIO_MPC8XXX is not set\n# CONFIG_GPIO_PCA953X is not set\n# CONFIG_GPIO_PCA953X_IRQ is not set\n# CONFIG_GPIO_PCA9570 is not set\n# CONFIG_GPIO_PCF857X is not set\n# CONFIG_GPIO_PCH is not set\n# CONFIG_GPIO_PCIE_IDIO_24 is not set\n# CONFIG_GPIO_PCI_IDIO_16 is not set\n# CONFIG_GPIO_PISOSR is not set\n# CONFIG_GPIO_PL061 is not set\n# CONFIG_GPIO_RCAR is not set\n# CONFIG_GPIO_RDC321X is not set\n# CONFIG_GPIO_SAMA5D2_PIOBU is not set\n# CONFIG_GPIO_SCH is not set\n# CONFIG_GPIO_SCH311X is not set\n# CONFIG_GPIO_SIFIVE is not set\n# CONFIG_GPIO_SX150X is not set\n# CONFIG_GPIO_SYSCON is not set\nCONFIG_GPIO_SYSFS=y\n# CONFIG_GPIO_TPIC2810 is not set\n# CONFIG_GPIO_TS4900 is not set\n# CONFIG_GPIO_TS5500 is not set\n# CONFIG_GPIO_VX855 is not set\n# CONFIG_GPIO_WATCHDOG is not set\n# CONFIG_GPIO_WINBOND is not set\n# CONFIG_GPIO_WS16C48 is not set\n# CONFIG_GPIO_XGENE is not set\n# CONFIG_GPIO_XILINX is not set\n# CONFIG_GPIO_XRA1403 is not set\n# CONFIG_GPIO_ZEVIO is not set\n# CONFIG_GPIO_ZX is not set\n# CONFIG_GREENASIA_FF is not set\n# CONFIG_GREYBUS is not set\n# CONFIG_GS_FPGABOOT is not set\n# CONFIG_GTP is not set\n# CONFIG_GUP_BENCHMARK is not set\n# CONFIG_GVE is not set\n# CONFIG_HABANA_AI is not set\n# CONFIG_HAMACHI is not set\n# CONFIG_HAMRADIO is not set\n# CONFIG_HAPPYMEAL is not set\nCONFIG_HARDENED_USERCOPY=y\n# CONFIG_HARDENED_USERCOPY_FALLBACK is not set\n# CONFIG_HARDENED_USERCOPY_PAGESPAN is not set\nCONFIG_HARDEN_BRANCH_HISTORY=y\nCONFIG_HARDEN_EL2_VECTORS=y\n# CONFIG_HARDLOCKUP_DETECTOR is not set\n# CONFIG_HAVE_ARM_ARCH_TIMER is not set\n# CONFIG_HCALL_STATS is not set\n# CONFIG_HDC100X is not set\n# CONFIG_HDC2010 is not set\n# CONFIG_HDLC is not set\n# CONFIG_HDLC_CISCO is not set\n# CONFIG_HDLC_FR is not set\n# CONFIG_HDLC_PPP is not set\n# CONFIG_HDLC_RAW is not set\n# CONFIG_HDLC_RAW_ETH is not set\n# CONFIG_HDMI_LPE_AUDIO is not set\n# CONFIG_HDQ_MASTER_OMAP is not set\n# CONFIG_HEADERS_CHECK is not set\n# CONFIG_HEADERS_INSTALL is not set\n# CONFIG_HEADER_TEST is not set\n# CONFIG_HERMES is not set\n# CONFIG_HFSPLUS_FS is not set\n# CONFIG_HFSPLUS_FS_POSIX_ACL is not set\n# CONFIG_HFS_FS is not set\n# CONFIG_HFS_FS_POSIX_ACL is not set\n# CONFIG_HI8435 is not set\n# CONFIG_HIBERNATION is not set\n# CONFIG_HID is not set\n# CONFIG_HIDRAW is not set\n# CONFIG_HID_A4TECH is not set\n# CONFIG_HID_ACCUTOUCH is not set\n# CONFIG_HID_ACRUX is not set\n# CONFIG_HID_ACRUX_FF is not set\n# CONFIG_HID_ALPS is not set\n# CONFIG_HID_APPLE is not set\n# CONFIG_HID_APPLEIR is not set\n# CONFIG_HID_ASUS is not set\n# CONFIG_HID_AUREAL is not set\n# CONFIG_HID_BATTERY_STRENGTH is not set\n# CONFIG_HID_BELKIN is not set\n# CONFIG_HID_BETOP_FF is not set\n# CONFIG_HID_BIGBEN_FF is not set\n# CONFIG_HID_CHERRY is not set\n# CONFIG_HID_CHICONY is not set\n# CONFIG_HID_CMEDIA is not set\n# CONFIG_HID_CORSAIR is not set\n# CONFIG_HID_COUGAR is not set\n# CONFIG_HID_CP2112 is not set\n# CONFIG_HID_CREATIVE_SB0540 is not set\n# CONFIG_HID_CYPRESS is not set\n# CONFIG_HID_DRAGONRISE is not set\n# CONFIG_HID_ELAN is not set\n# CONFIG_HID_ELECOM is not set\n# CONFIG_HID_ELO is not set\n# CONFIG_HID_EMS_FF is not set\n# CONFIG_HID_EZKEY is not set\n# CONFIG_HID_GEMBIRD is not set\n# CONFIG_HID_GENERIC is not set\n# CONFIG_HID_GFRM is not set\n# CONFIG_HID_GLORIOUS is not set\n# CONFIG_HID_GOOGLE_HAMMER is not set\n# CONFIG_HID_GREENASIA is not set\n# CONFIG_HID_GT683R is not set\n# CONFIG_HID_GYRATION is not set\n# CONFIG_HID_HOLTEK is not set\n# CONFIG_HID_ICADE is not set\n# CONFIG_HID_ITE is not set\n# CONFIG_HID_JABRA is not set\n# CONFIG_HID_KENSINGTON is not set\n# CONFIG_HID_KEYTOUCH is not set\n# CONFIG_HID_KYE is not set\n# CONFIG_HID_LCPOWER is not set\n# CONFIG_HID_LED is not set\n# CONFIG_HID_LENOVO is not set\n# CONFIG_HID_LOGITECH is not set\n# CONFIG_HID_LOGITECH_DJ is not set\n# CONFIG_HID_LOGITECH_HIDPP is not set\n# CONFIG_HID_MACALLY is not set\n# CONFIG_HID_MAGICMOUSE is not set\n# CONFIG_HID_MALTRON is not set\n# CONFIG_HID_MAYFLASH is not set\n# CONFIG_HID_MCP2221 is not set\n# CONFIG_HID_MICROSOFT is not set\n# CONFIG_HID_MONTEREY is not set\n# CONFIG_HID_MULTITOUCH is not set\n# CONFIG_HID_NTI is not set\n# CONFIG_HID_NTRIG is not set\n# CONFIG_HID_ORTEK is not set\n# CONFIG_HID_PANTHERLORD is not set\n# CONFIG_HID_PENMOUNT is not set\n# CONFIG_HID_PETALYNX is not set\n# CONFIG_HID_PICOLCD is not set\n# CONFIG_HID_PID is not set\n# CONFIG_HID_PLANTRONICS is not set\n# CONFIG_HID_PRIMAX is not set\n# CONFIG_HID_PRODIKEYS is not set\n# CONFIG_HID_REDRAGON is not set\n# CONFIG_HID_RETRODE is not set\n# CONFIG_HID_RMI is not set\n# CONFIG_HID_ROCCAT is not set\n# CONFIG_HID_SAITEK is not set\n# CONFIG_HID_SAMSUNG is not set\n# CONFIG_HID_SENSOR_HUB is not set\n# CONFIG_HID_SMARTJOYPLUS is not set\n# CONFIG_HID_SONY is not set\n# CONFIG_HID_SPEEDLINK is not set\n# CONFIG_HID_STEAM is not set\n# CONFIG_HID_STEELSERIES is not set\n# CONFIG_HID_SUNPLUS is not set\n# CONFIG_HID_THINGM is not set\n# CONFIG_HID_THRUSTMASTER is not set\n# CONFIG_HID_TIVO is not set\n# CONFIG_HID_TOPSEED is not set\n# CONFIG_HID_TWINHAN is not set\n# CONFIG_HID_U2FZERO is not set\n# CONFIG_HID_UCLOGIC is not set\n# CONFIG_HID_UDRAW_PS3 is not set\n# CONFIG_HID_VIEWSONIC is not set\n# CONFIG_HID_VIVALDI is not set\n# CONFIG_HID_WACOM is not set\n# CONFIG_HID_WALTOP is not set\n# CONFIG_HID_WIIMOTE is not set\n# CONFIG_HID_XINMO is not set\n# CONFIG_HID_ZEROPLUS is not set\n# CONFIG_HID_ZYDACRON is not set\n# CONFIG_HIGHMEM is not set\nCONFIG_HIGH_RES_TIMERS=y\n# CONFIG_HINIC is not set\n# CONFIG_HIP04_ETH is not set\n# CONFIG_HIPPI is not set\n# CONFIG_HISILICON_ERRATUM_161010101 is not set\n# CONFIG_HISILICON_ERRATUM_161600802 is not set\n# CONFIG_HISI_DMA is not set\n# CONFIG_HISI_FEMAC is not set\n# CONFIG_HISI_HIKEY_USB is not set\n# CONFIG_HIX5HD2_GMAC is not set\n# CONFIG_HMC425 is not set\n# CONFIG_HMC6352 is not set\n# CONFIG_HNS is not set\n# CONFIG_HNS3 is not set\n# CONFIG_HNS_DSAF is not set\n# CONFIG_HNS_ENET is not set\n# CONFIG_HOSTAP is not set\n# CONFIG_HOSTAP_CS is not set\n# CONFIG_HOSTAP_PCI is not set\n# CONFIG_HOSTAP_PLX is not set\n# CONFIG_HOTPLUG_CPU is not set\n# CONFIG_HOTPLUG_PCI is not set\n# CONFIG_HP03 is not set\n# CONFIG_HP100 is not set\n# CONFIG_HP206C is not set\nCONFIG_HPET_MMAP_DEFAULT=y\n# CONFIG_HPFS_FS is not set\n# CONFIG_HP_ILO is not set\n# CONFIG_HP_WIRELESS is not set\n# CONFIG_HSA_AMD is not set\n# CONFIG_HSI is not set\n# CONFIG_HSR is not set\n# CONFIG_HTC_EGPIO is not set\n# CONFIG_HTC_I2CPLD is not set\n# CONFIG_HTC_PASIC3 is not set\n# CONFIG_HTS221 is not set\n# CONFIG_HTU21 is not set\n# CONFIG_HUGETLBFS is not set\n# CONFIG_HUGETLB_PAGE is not set\n# CONFIG_HVC_DCC is not set\n# CONFIG_HVC_UDBG is not set\n# CONFIG_HWLAT_TRACER is not set\n# CONFIG_HWMON is not set\n# CONFIG_HWMON_DEBUG_CHIP is not set\n# CONFIG_HWMON_VID is not set\n# CONFIG_HWSPINLOCK is not set\n# CONFIG_HWSPINLOCK_OMAP is not set\nCONFIG_HW_PERF_EVENTS=y\n# CONFIG_HW_RANDOM is not set\n# CONFIG_HW_RANDOM_AMD is not set\n# CONFIG_HW_RANDOM_ATMEL is not set\n# CONFIG_HW_RANDOM_BA431 is not set\n# CONFIG_HW_RANDOM_CAVIUM is not set\n# CONFIG_HW_RANDOM_CCTRNG is not set\n# CONFIG_HW_RANDOM_EXYNOS is not set\n# CONFIG_HW_RANDOM_GEODE is not set\n# CONFIG_HW_RANDOM_INTEL is not set\n# CONFIG_HW_RANDOM_IPROC_RNG200 is not set\n# CONFIG_HW_RANDOM_MTK is not set\n# CONFIG_HW_RANDOM_OMAP is not set\n# CONFIG_HW_RANDOM_OMAP3_ROM is not set\n# CONFIG_HW_RANDOM_PPC4XX is not set\n# CONFIG_HW_RANDOM_TIMERIOMEM is not set\nCONFIG_HW_RANDOM_TPM=y\n# CONFIG_HW_RANDOM_VIA is not set\n# CONFIG_HW_RANDOM_VIRTIO is not set\n# CONFIG_HW_RANDOM_XIPHERA is not set\n# CONFIG_HX711 is not set\n# CONFIG_HYPERV is not set\n# CONFIG_HYPERV_TSCPAGE is not set\n# CONFIG_HYSDN is not set\nCONFIG_HZ=100\nCONFIG_HZ_100=y\n# CONFIG_HZ_1000 is not set\n# CONFIG_HZ_1024 is not set\n# CONFIG_HZ_128 is not set\n# CONFIG_HZ_200 is not set\n# CONFIG_HZ_24 is not set\n# CONFIG_HZ_250 is not set\n# CONFIG_HZ_256 is not set\n# CONFIG_HZ_300 is not set\n# CONFIG_HZ_48 is not set\n# CONFIG_HZ_500 is not set\n# CONFIG_HZ_PERIODIC is not set\n# CONFIG_I2C is not set\n# CONFIG_I2C_ALGOBIT is not set\n# CONFIG_I2C_ALGOPCA is not set\n# CONFIG_I2C_ALGOPCF is not set\n# CONFIG_I2C_ALI1535 is not set\n# CONFIG_I2C_ALI1563 is not set\n# CONFIG_I2C_ALI15X3 is not set\n# CONFIG_I2C_AMD756 is not set\n# CONFIG_I2C_AMD8111 is not set\n# CONFIG_I2C_ARB_GPIO_CHALLENGE is not set\n# CONFIG_I2C_AU1550 is not set\n# CONFIG_I2C_BCM2835 is not set\n# CONFIG_I2C_BCM_IPROC is not set\n# CONFIG_I2C_CADENCE is not set\n# CONFIG_I2C_CBUS_GPIO is not set\n# CONFIG_I2C_CHARDEV is not set\n# CONFIG_I2C_COMPAT is not set\n# CONFIG_I2C_DEBUG_ALGO is not set\n# CONFIG_I2C_DEBUG_BUS is not set\n# CONFIG_I2C_DEBUG_CORE is not set\n# CONFIG_I2C_DEMUX_PINCTRL is not set\n# CONFIG_I2C_DESIGNWARE_PCI is not set\n# CONFIG_I2C_DESIGNWARE_PLATFORM is not set\n# CONFIG_I2C_DESIGNWARE_SLAVE is not set\n# CONFIG_I2C_DIOLAN_U2C is not set\n# CONFIG_I2C_EG20T is not set\n# CONFIG_I2C_ELEKTOR is not set\n# CONFIG_I2C_EMEV2 is not set\n# CONFIG_I2C_GPIO is not set\n# CONFIG_I2C_GPIO_FAULT_INJECTOR is not set\n# CONFIG_I2C_HELPER_AUTO is not set\n# CONFIG_I2C_HID is not set\n# CONFIG_I2C_I801 is not set\n# CONFIG_I2C_IBM_IIC is not set\n# CONFIG_I2C_IMG is not set\n# CONFIG_I2C_ISCH is not set\n# CONFIG_I2C_ISMT is not set\n# CONFIG_I2C_JZ4780 is not set\n# CONFIG_I2C_MLXCPLD is not set\n# CONFIG_I2C_MPC is not set\n# CONFIG_I2C_MT65XX is not set\n# CONFIG_I2C_MUX is not set\n# CONFIG_I2C_MUX_GPIO is not set\n# CONFIG_I2C_MUX_GPMUX is not set\n# CONFIG_I2C_MUX_LTC4306 is not set\n# CONFIG_I2C_MUX_MLXCPLD is not set\n# CONFIG_I2C_MUX_PCA9541 is not set\n# CONFIG_I2C_MUX_PCA954x is not set\n# CONFIG_I2C_MUX_PINCTRL is not set\n# CONFIG_I2C_MUX_REG is not set\n# CONFIG_I2C_MV64XXX is not set\n# CONFIG_I2C_NFORCE2 is not set\n# CONFIG_I2C_NOMADIK is not set\n# CONFIG_I2C_NVIDIA_GPU is not set\n# CONFIG_I2C_OCORES is not set\n# CONFIG_I2C_OCTEON is not set\n# CONFIG_I2C_PARPORT is not set\n# CONFIG_I2C_PARPORT_LIGHT is not set\n# CONFIG_I2C_PCA_ISA is not set\n# CONFIG_I2C_PCA_PLATFORM is not set\n# CONFIG_I2C_PIIX4 is not set\n# CONFIG_I2C_PXA_PCI is not set\n# CONFIG_I2C_PXA_SLAVE is not set\n# CONFIG_I2C_RCAR is not set\n# CONFIG_I2C_RK3X is not set\n# CONFIG_I2C_ROBOTFUZZ_OSIF is not set\n# CONFIG_I2C_S3C2410 is not set\n# CONFIG_I2C_SCMI is not set\n# CONFIG_I2C_SH_MOBILE is not set\n# CONFIG_I2C_SIMTEC is not set\n# CONFIG_I2C_SIS5595 is not set\n# CONFIG_I2C_SIS630 is not set\n# CONFIG_I2C_SIS96X is not set\n# CONFIG_I2C_SLAVE is not set\n# CONFIG_I2C_SLAVE_EEPROM is not set\n# CONFIG_I2C_SMBUS is not set\n# CONFIG_I2C_STUB is not set\n# CONFIG_I2C_TAOS_EVM is not set\n# CONFIG_I2C_THUNDERX is not set\n# CONFIG_I2C_TINY_USB is not set\n# CONFIG_I2C_VERSATILE is not set\n# CONFIG_I2C_VIA is not set\n# CONFIG_I2C_VIAPRO is not set\n# CONFIG_I2C_XILINX is not set\n# CONFIG_I3C is not set\n# CONFIG_I40E is not set\n# CONFIG_I40EVF is not set\n# CONFIG_I6300ESB_WDT is not set\n# CONFIG_I82092 is not set\n# CONFIG_I82365 is not set\n# CONFIG_IAQCORE is not set\n# CONFIG_IBM_ASM is not set\n# CONFIG_IBM_EMAC_DEBUG is not set\n# CONFIG_IBM_EMAC_EMAC4 is not set\n# CONFIG_IBM_EMAC_MAL_CLR_ICINTSTAT is not set\n# CONFIG_IBM_EMAC_MAL_COMMON_ERR is not set\n# CONFIG_IBM_EMAC_NO_FLOW_CTRL is not set\n# CONFIG_IBM_EMAC_RGMII is not set\n# CONFIG_IBM_EMAC_TAH is not set\n# CONFIG_IBM_EMAC_ZMII is not set\n# CONFIG_ICE is not set\n# CONFIG_ICP10100 is not set\n# CONFIG_ICPLUS_PHY is not set\n# CONFIG_ICS932S401 is not set\n# CONFIG_IDE is not set\n# CONFIG_IDEAPAD_LAPTOP is not set\n# CONFIG_IDE_GD is not set\n# CONFIG_IDE_PROC_FS is not set\n# CONFIG_IDE_TASK_IOCTL is not set\n# CONFIG_IDLE_PAGE_TRACKING is not set\n# CONFIG_IEEE802154 is not set\n# CONFIG_IEEE802154_ADF7242 is not set\n# CONFIG_IEEE802154_ATUSB is not set\n# CONFIG_IEEE802154_CA8210 is not set\n# CONFIG_IEEE802154_HWSIM is not set\n# CONFIG_IEEE802154_MCR20A is not set\n# CONFIG_IFB is not set\n# CONFIG_IGB is not set\n# CONFIG_IGBVF is not set\n# CONFIG_IGC is not set\n# CONFIG_IIO is not set\n# CONFIG_IIO_BUFFER is not set\n# CONFIG_IIO_BUFFER_CB is not set\n# CONFIG_IIO_BUFFER_DMA is not set\n# CONFIG_IIO_BUFFER_DMAENGINE is not set\n# CONFIG_IIO_BUFFER_HDC2010 is not set\n# CONFIG_IIO_BUFFER_HW_CONSUMER is not set\n# CONFIG_IIO_CONFIGFS is not set\nCONFIG_IIO_CONSUMERS_PER_TRIGGER=2\n# CONFIG_IIO_CROS_EC_ACCEL_LEGACY is not set\n# CONFIG_IIO_INTERRUPT_TRIGGER is not set\n# CONFIG_IIO_MUX is not set\n# CONFIG_IIO_PERIODIC_RTC_TRIGGER is not set\n# CONFIG_IIO_RESCALE is not set\n# CONFIG_IIO_SIMPLE_DUMMY is not set\n# CONFIG_IIO_SSP_SENSORHUB is not set\n# CONFIG_IIO_ST_ACCEL_3AXIS is not set\n# CONFIG_IIO_ST_GYRO_3AXIS is not set\n# CONFIG_IIO_ST_LSM6DSX is not set\n# CONFIG_IIO_ST_MAGN_3AXIS is not set\n# CONFIG_IIO_ST_PRESS is not set\n# CONFIG_IIO_SW_DEVICE is not set\n# CONFIG_IIO_SW_TRIGGER is not set\n# CONFIG_IIO_SYSFS_TRIGGER is not set\n# CONFIG_IIO_TRIGGER is not set\n# CONFIG_IIO_TRIGGERED_EVENT is not set\n# CONFIG_IKCONFIG is not set\n# CONFIG_IKCONFIG_PROC is not set\n# CONFIG_IKHEADERS is not set\n# CONFIG_IMA is not set\n# CONFIG_IMAGE_CMDLINE_HACK is not set\n# CONFIG_IMGPDC_WDT is not set\n# CONFIG_IMG_MDC_DMA is not set\n# CONFIG_IMX7D_ADC is not set\n# CONFIG_IMX_IPUV3_CORE is not set\n# CONFIG_IMX_THERMAL is not set\n# CONFIG_INA2XX_ADC is not set\n# CONFIG_INDIRECT_PIO is not set\nCONFIG_INET=y\n# CONFIG_INET6_AH is not set\n# CONFIG_INET6_ESP is not set\n# CONFIG_INET6_ESPINTCP is not set\n# CONFIG_INET6_IPCOMP is not set\n# CONFIG_INET6_TUNNEL is not set\n# CONFIG_INET6_XFRM_MODE_BEET is not set\n# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set\n# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set\n# CONFIG_INET6_XFRM_MODE_TUNNEL is not set\n# CONFIG_INET6_XFRM_TUNNEL is not set\n# CONFIG_INET_AH is not set\n# CONFIG_INET_DIAG is not set\n# CONFIG_INET_ESP is not set\n# CONFIG_INET_ESPINTCP is not set\n# CONFIG_INET_IPCOMP is not set\n# CONFIG_INET_LRO is not set\n# CONFIG_INET_TCP_DIAG is not set\n# CONFIG_INET_TUNNEL is not set\n# CONFIG_INET_UDP_DIAG is not set\n# CONFIG_INET_XFRM_MODE_BEET is not set\n# CONFIG_INET_XFRM_MODE_TRANSPORT is not set\n# CONFIG_INET_XFRM_MODE_TUNNEL is not set\n# CONFIG_INET_XFRM_TUNNEL is not set\n# CONFIG_INFINIBAND is not set\n# CONFIG_INFTL is not set\n# CONFIG_INGENIC_ADC is not set\n# CONFIG_INGENIC_CGU_JZ4725B is not set\n# CONFIG_INGENIC_CGU_JZ4740 is not set\n# CONFIG_INGENIC_CGU_JZ4770 is not set\n# CONFIG_INGENIC_CGU_JZ4780 is not set\n# CONFIG_INGENIC_CGU_X1000 is not set\n# CONFIG_INGENIC_CGU_X1830 is not set\n# CONFIG_INGENIC_OST is not set\n# CONFIG_INGENIC_SYSOST is not set\n# CONFIG_INGENIC_TCU_CLK is not set\n# CONFIG_INGENIC_TCU_IRQ is not set\n# CONFIG_INGENIC_TIMER is not set\nCONFIG_INIT_ENV_ARG_LIMIT=32\n# CONFIG_INIT_ON_ALLOC_DEFAULT_ON is not set\n# CONFIG_INIT_ON_FREE_DEFAULT_ON is not set\nCONFIG_INIT_STACK_NONE=y\nCONFIG_INOTIFY_USER=y\n# CONFIG_INPUT is not set\n# CONFIG_INPUT_AD714X is not set\n# CONFIG_INPUT_ADXL34X is not set\n# CONFIG_INPUT_APANEL is not set\n# CONFIG_INPUT_ATI_REMOTE2 is not set\n# CONFIG_INPUT_ATLAS_BTNS is not set\n# CONFIG_INPUT_ATMEL_CAPTOUCH is not set\n# CONFIG_INPUT_AXP20X_PEK is not set\n# CONFIG_INPUT_BMA150 is not set\n# CONFIG_INPUT_CM109 is not set\n# CONFIG_INPUT_CMA3000 is not set\n# CONFIG_INPUT_DRV260X_HAPTICS is not set\n# CONFIG_INPUT_DRV2665_HAPTICS is not set\n# CONFIG_INPUT_DRV2667_HAPTICS is not set\n# CONFIG_INPUT_E3X0_BUTTON is not set\n# CONFIG_INPUT_EVBUG is not set\n# CONFIG_INPUT_EVDEV is not set\n# CONFIG_INPUT_FF_MEMLESS is not set\n# CONFIG_INPUT_GP2A is not set\n# CONFIG_INPUT_GPIO_BEEPER is not set\n# CONFIG_INPUT_GPIO_DECODER is not set\n# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set\n# CONFIG_INPUT_GPIO_TILT_POLLED is not set\n# CONFIG_INPUT_GPIO_VIBRA is not set\n# CONFIG_INPUT_IDEAPAD_SLIDEBAR is not set\n# CONFIG_INPUT_IMS_PCU is not set\n# CONFIG_INPUT_IQS269A is not set\n# CONFIG_INPUT_JOYDEV is not set\n# CONFIG_INPUT_JOYSTICK is not set\n# CONFIG_INPUT_KEYBOARD is not set\n# CONFIG_INPUT_KEYSPAN_REMOTE is not set\n# CONFIG_INPUT_KXTJ9 is not set\n# CONFIG_INPUT_LEDS is not set\n# CONFIG_INPUT_MATRIXKMAP is not set\n# CONFIG_INPUT_MAX8997_HAPTIC is not set\nCONFIG_INPUT_MISC=y\n# CONFIG_INPUT_MMA8450 is not set\n# CONFIG_INPUT_MOUSE is not set\n# CONFIG_INPUT_MOUSEDEV is not set\n# CONFIG_INPUT_MPU3050 is not set\n# CONFIG_INPUT_MSM_VIBRATOR is not set\n# CONFIG_INPUT_PALMAS_PWRBUTTON is not set\n# CONFIG_INPUT_PCF8574 is not set\n# CONFIG_INPUT_PCSPKR is not set\n# CONFIG_INPUT_POLLDEV is not set\n# CONFIG_INPUT_POWERMATE is not set\n# CONFIG_INPUT_PWM_BEEPER is not set\n# CONFIG_INPUT_PWM_VIBRA is not set\n# CONFIG_INPUT_REGULATOR_HAPTIC is not set\n# CONFIG_INPUT_SOC_BUTTON_ARRAY is not set\n# CONFIG_INPUT_SPARSEKMAP is not set\n# CONFIG_INPUT_TABLET is not set\n# CONFIG_INPUT_TOUCHSCREEN is not set\n# CONFIG_INPUT_TPS65218_PWRBUTTON is not set\n# CONFIG_INPUT_TWL4030_PWRBUTTON is not set\n# CONFIG_INPUT_TWL4030_VIBRA is not set\n# CONFIG_INPUT_TWL6040_VIBRA is not set\n# CONFIG_INPUT_UINPUT is not set\n# CONFIG_INPUT_WISTRON_BTNS is not set\n# CONFIG_INPUT_YEALINK is not set\n# CONFIG_INT340X_THERMAL is not set\n# CONFIG_INTEGRITY is not set\n# CONFIG_INTEGRITY_AUDIT is not set\n# CONFIG_INTEGRITY_SIGNATURE is not set\n# CONFIG_INTEL_ATOMISP2_LED is not set\n# CONFIG_INTEL_ATOMISP2_PM is not set\n# CONFIG_INTEL_CHT_INT33FE is not set\n# CONFIG_INTEL_HID_EVENT is not set\n# CONFIG_INTEL_IDLE is not set\n# CONFIG_INTEL_IDMA64 is not set\n# CONFIG_INTEL_INT0002_VGPIO is not set\n# CONFIG_INTEL_IOATDMA is not set\n# CONFIG_INTEL_ISH_HID is not set\n# CONFIG_INTEL_MEI is not set\n# CONFIG_INTEL_MEI_ME is not set\n# CONFIG_INTEL_MEI_TXE is not set\n# CONFIG_INTEL_MIC_CARD is not set\n# CONFIG_INTEL_MIC_HOST is not set\n# CONFIG_INTEL_MID_PTI is not set\n# CONFIG_INTEL_OAKTRAIL is not set\n# CONFIG_INTEL_PMC_CORE is not set\n# CONFIG_INTEL_PUNIT_IPC is not set\n# CONFIG_INTEL_RST is not set\n# CONFIG_INTEL_SMARTCONNECT is not set\n# CONFIG_INTEL_SOC_PMIC is not set\n# CONFIG_INTEL_SOC_PMIC_CHTDC_TI is not set\n# CONFIG_INTEL_SOC_PMIC_CHTWC is not set\n# CONFIG_INTEL_TH is not set\n# CONFIG_INTEL_VBTN is not set\n# CONFIG_INTEL_XWAY_PHY is not set\n# CONFIG_INTERCONNECT is not set\n# CONFIG_INTERVAL_TREE_TEST is not set\n# CONFIG_INV_ICM42600_I2C is not set\n# CONFIG_INV_ICM42600_SPI is not set\n# CONFIG_INV_MPU6050_I2C is not set\n# CONFIG_INV_MPU6050_IIO is not set\n# CONFIG_INV_MPU6050_SPI is not set\n# CONFIG_IOMMU_SUPPORT is not set\n# CONFIG_IONIC is not set\n# CONFIG_IOSCHED_BFQ is not set\nCONFIG_IO_STRICT_DEVMEM=y\n# CONFIG_IO_URING is not set\nCONFIG_IO_WQ=y\n# CONFIG_IP17XX_PHY is not set\n# CONFIG_IP6_NF_FILTER is not set\n# CONFIG_IP6_NF_IPTABLES is not set\n# CONFIG_IP6_NF_MANGLE is not set\n# CONFIG_IP6_NF_MATCH_AH is not set\n# CONFIG_IP6_NF_MATCH_EUI64 is not set\n# CONFIG_IP6_NF_MATCH_FRAG is not set\n# CONFIG_IP6_NF_MATCH_HL is not set\n# CONFIG_IP6_NF_MATCH_IPV6HEADER is not set\n# CONFIG_IP6_NF_MATCH_MH is not set\n# CONFIG_IP6_NF_MATCH_OPTS is not set\n# CONFIG_IP6_NF_MATCH_RPFILTER is not set\n# CONFIG_IP6_NF_MATCH_RT is not set\n# CONFIG_IP6_NF_MATCH_SRH is not set\n# CONFIG_IP6_NF_NAT is not set\n# CONFIG_IP6_NF_RAW is not set\n# CONFIG_IP6_NF_SECURITY is not set\n# CONFIG_IP6_NF_TARGET_HL is not set\n# CONFIG_IP6_NF_TARGET_MASQUERADE is not set\n# CONFIG_IP6_NF_TARGET_REJECT is not set\n# CONFIG_IP6_NF_TARGET_SYNPROXY is not set\n# CONFIG_IPACK_BUS is not set\n# CONFIG_IPC_NS is not set\n# CONFIG_IPMB_DEVICE_INTERFACE is not set\n# CONFIG_IPMI_HANDLER is not set\n# CONFIG_IPV6 is not set\n# CONFIG_IPV6_FOU is not set\n# CONFIG_IPV6_FOU_TUNNEL is not set\n# CONFIG_IPV6_ILA is not set\n# CONFIG_IPV6_MIP6 is not set\n# CONFIG_IPV6_MROUTE is not set\n# CONFIG_IPV6_MROUTE_MULTIPLE_TABLES is not set\n# CONFIG_IPV6_MULTIPLE_TABLES is not set\nCONFIG_IPV6_NDISC_NODETYPE=y\n# CONFIG_IPV6_OPTIMISTIC_DAD is not set\n# CONFIG_IPV6_ROUTER_PREF is not set\n# CONFIG_IPV6_ROUTE_INFO is not set\n# CONFIG_IPV6_RPL_LWTUNNEL is not set\n# CONFIG_IPV6_SEG6_HMAC is not set\n# CONFIG_IPV6_SEG6_LWTUNNEL is not set\n# CONFIG_IPV6_SIT is not set\n# CONFIG_IPV6_SIT_6RD is not set\n# CONFIG_IPV6_TUNNEL is not set\n# CONFIG_IPV6_VTI is not set\n# CONFIG_IPVLAN is not set\n# CONFIG_IPVTAP is not set\n# CONFIG_IPW2100 is not set\n# CONFIG_IPW2100_DEBUG is not set\nCONFIG_IPW2100_MONITOR=y\n# CONFIG_IPW2200 is not set\n# CONFIG_IPW2200_DEBUG is not set\nCONFIG_IPW2200_MONITOR=y\n# CONFIG_IPW2200_PROMISCUOUS is not set\n# CONFIG_IPW2200_QOS is not set\n# CONFIG_IPW2200_RADIOTAP is not set\n# CONFIG_IPWIRELESS is not set\n# CONFIG_IPX is not set\nCONFIG_IP_ADVANCED_ROUTER=y\n# CONFIG_IP_DCCP is not set\n# CONFIG_IP_FIB_TRIE_STATS is not set\n# CONFIG_IP_MROUTE is not set\nCONFIG_IP_MROUTE_MULTIPLE_TABLES=y\nCONFIG_IP_MULTICAST=y\nCONFIG_IP_MULTIPLE_TABLES=y\n# CONFIG_IP_NF_ARPFILTER is not set\n# CONFIG_IP_NF_ARPTABLES is not set\n# CONFIG_IP_NF_ARP_MANGLE is not set\n# CONFIG_IP_NF_FILTER is not set\n# CONFIG_IP_NF_IPTABLES is not set\n# CONFIG_IP_NF_MANGLE is not set\n# CONFIG_IP_NF_MATCH_AH is not set\n# CONFIG_IP_NF_MATCH_ECN is not set\n# CONFIG_IP_NF_MATCH_RPFILTER is not set\n# CONFIG_IP_NF_MATCH_TTL is not set\n# CONFIG_IP_NF_RAW is not set\n# CONFIG_IP_NF_SECURITY is not set\n# CONFIG_IP_NF_TARGET_CLUSTERIP is not set\n# CONFIG_IP_NF_TARGET_ECN is not set\n# CONFIG_IP_NF_TARGET_MASQUERADE is not set\n# CONFIG_IP_NF_TARGET_NETMAP is not set\n# CONFIG_IP_NF_TARGET_REDIRECT is not set\n# CONFIG_IP_NF_TARGET_REJECT is not set\n# CONFIG_IP_NF_TARGET_SYNPROXY is not set\n# CONFIG_IP_NF_TARGET_TTL is not set\n# CONFIG_IP_PIMSM_V1 is not set\n# CONFIG_IP_PIMSM_V2 is not set\n# CONFIG_IP_PNP is not set\nCONFIG_IP_ROUTE_MULTIPATH=y\nCONFIG_IP_ROUTE_VERBOSE=y\n# CONFIG_IP_SCTP is not set\n# CONFIG_IP_SET is not set\n# CONFIG_IP_SET_HASH_IPMAC is not set\n# CONFIG_IP_VS is not set\n# CONFIG_IP_VS_MH is not set\nCONFIG_IP_VS_MH_TAB_INDEX=10\n# CONFIG_IRDA is not set\n# CONFIG_IRQSOFF_TRACER is not set\n# CONFIG_IRQ_ALL_CPUS is not set\n# CONFIG_IRQ_DOMAIN_DEBUG is not set\n# CONFIG_IRQ_POLL is not set\n# CONFIG_IRQ_TIME_ACCOUNTING is not set\n# CONFIG_IR_GPIO_CIR is not set\n# CONFIG_IR_HIX5HD2 is not set\n# CONFIG_IR_IGORPLUGUSB is not set\n# CONFIG_IR_IGUANA is not set\n# CONFIG_IR_IMG is not set\n# CONFIG_IR_IMON is not set\n# CONFIG_IR_IMON_RAW is not set\n# CONFIG_IR_JVC_DECODER is not set\n# CONFIG_IR_LIRC_CODEC is not set\n# CONFIG_IR_MCEUSB is not set\n# CONFIG_IR_NEC_DECODER is not set\n# CONFIG_IR_RC5_DECODER is not set\n# CONFIG_IR_RC6_DECODER is not set\n# CONFIG_IR_REDRAT3 is not set\n# CONFIG_IR_SONY_DECODER is not set\n# CONFIG_IR_STREAMZAP is not set\n# CONFIG_IR_TTUSBIR is not set\n# CONFIG_ISA_BUS is not set\n# CONFIG_ISA_BUS_API is not set\n# CONFIG_ISCSI_BOOT_SYSFS is not set\n# CONFIG_ISCSI_TCP is not set\nCONFIG_ISDN=y\n# CONFIG_ISDN_AUDIO is not set\n# CONFIG_ISDN_CAPI is not set\n# CONFIG_ISDN_CAPI_CAPIDRV is not set\n# CONFIG_ISDN_DIVERSION is not set\n# CONFIG_ISDN_DRV_ACT2000 is not set\n# CONFIG_ISDN_DRV_GIGASET is not set\n# CONFIG_ISDN_DRV_HISAX is not set\n# CONFIG_ISDN_DRV_ICN is not set\n# CONFIG_ISDN_DRV_LOOP is not set\n# CONFIG_ISDN_DRV_PCBIT is not set\n# CONFIG_ISDN_DRV_SC is not set\n# CONFIG_ISDN_I4L is not set\n# CONFIG_ISL29003 is not set\n# CONFIG_ISL29020 is not set\n# CONFIG_ISL29125 is not set\n# CONFIG_ISL29501 is not set\n# CONFIG_ISO9660_FS is not set\n# CONFIG_ISS4xx is not set\n# CONFIG_ITG3200 is not set\n# CONFIG_IWL3945 is not set\n# CONFIG_IWLWIFI is not set\n# CONFIG_IXGB is not set\n# CONFIG_IXGBE is not set\n# CONFIG_IXGBEVF is not set\n# CONFIG_JAILHOUSE_GUEST is not set\n# CONFIG_JBD2_DEBUG is not set\n# CONFIG_JFFS2_CMODE_FAVOURLZO is not set\n# CONFIG_JFFS2_CMODE_NONE is not set\nCONFIG_JFFS2_CMODE_PRIORITY=y\n# CONFIG_JFFS2_CMODE_SIZE is not set\nCONFIG_JFFS2_COMPRESSION_OPTIONS=y\nCONFIG_JFFS2_FS=y\nCONFIG_JFFS2_FS_DEBUG=0\n# CONFIG_JFFS2_FS_POSIX_ACL is not set\n# CONFIG_JFFS2_FS_SECURITY is not set\n# CONFIG_JFFS2_FS_WBUF_VERIFY is not set\nCONFIG_JFFS2_FS_WRITEBUFFER=y\nCONFIG_JFFS2_FS_XATTR=y\nCONFIG_JFFS2_LZMA=y\n# CONFIG_JFFS2_LZO is not set\nCONFIG_JFFS2_RTIME=y\n# CONFIG_JFFS2_RUBIN is not set\nCONFIG_JFFS2_SUMMARY=y\n# CONFIG_JFFS2_ZLIB is not set\n# CONFIG_JFS_DEBUG is not set\n# CONFIG_JFS_FS is not set\n# CONFIG_JFS_POSIX_ACL is not set\n# CONFIG_JFS_SECURITY is not set\n# CONFIG_JFS_STATISTICS is not set\n# CONFIG_JME is not set\nCONFIG_JOLIET=y\n# CONFIG_JSA1212 is not set\n# CONFIG_JUMP_LABEL is not set\n# CONFIG_JZ4740_WDT is not set\n# CONFIG_JZ4770_PHY is not set\n# CONFIG_KALLSYMS is not set\n# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set\n# CONFIG_KALLSYMS_ALL is not set\nCONFIG_KALLSYMS_BASE_RELATIVE=y\n# CONFIG_KALLSYMS_UNCOMPRESSED is not set\n# CONFIG_KARMA_PARTITION is not set\n# CONFIG_KASAN is not set\nCONFIG_KASAN_STACK=1\n# CONFIG_KCMP is not set\n# CONFIG_KCOV is not set\n# CONFIG_KCSAN is not set\n# CONFIG_KERNEL_BZIP2 is not set\n# CONFIG_KERNEL_CAT is not set\n# CONFIG_KERNEL_GZIP is not set\n# CONFIG_KERNEL_LZ4 is not set\n# CONFIG_KERNEL_LZMA is not set\n# CONFIG_KERNEL_LZO is not set\nCONFIG_KERNEL_MODE_NEON=y\nCONFIG_KERNEL_XZ=y\n# CONFIG_KERNEL_ZSTD is not set\nCONFIG_KERNFS=y\n# CONFIG_KEXEC is not set\n# CONFIG_KEXEC_FILE is not set\n# CONFIG_KEXEC_SIG is not set\n# CONFIG_KEYBOARD_ADC is not set\n# CONFIG_KEYBOARD_ADP5588 is not set\n# CONFIG_KEYBOARD_ADP5589 is not set\n# CONFIG_KEYBOARD_APPLESPI is not set\n# CONFIG_KEYBOARD_ATKBD is not set\n# CONFIG_KEYBOARD_BCM is not set\n# CONFIG_KEYBOARD_CAP11XX is not set\n# CONFIG_KEYBOARD_DLINK_DIR685 is not set\n# CONFIG_KEYBOARD_GPIO is not set\n# CONFIG_KEYBOARD_GPIO_POLLED is not set\n# CONFIG_KEYBOARD_LKKBD is not set\n# CONFIG_KEYBOARD_LM8323 is not set\n# CONFIG_KEYBOARD_LM8333 is not set\n# CONFIG_KEYBOARD_MATRIX is not set\n# CONFIG_KEYBOARD_MAX7359 is not set\n# CONFIG_KEYBOARD_MCS is not set\n# CONFIG_KEYBOARD_MPR121 is not set\n# CONFIG_KEYBOARD_NEWTON is not set\n# CONFIG_KEYBOARD_OMAP4 is not set\n# CONFIG_KEYBOARD_OPENCORES is not set\n# CONFIG_KEYBOARD_PXA27x is not set\n# CONFIG_KEYBOARD_QT1050 is not set\n# CONFIG_KEYBOARD_QT1070 is not set\n# CONFIG_KEYBOARD_QT2160 is not set\n# CONFIG_KEYBOARD_SAMSUNG is not set\n# CONFIG_KEYBOARD_SH_KEYSC is not set\n# CONFIG_KEYBOARD_SNVS_PWRKEY is not set\n# CONFIG_KEYBOARD_STMPE is not set\n# CONFIG_KEYBOARD_STOWAWAY is not set\n# CONFIG_KEYBOARD_SUNKBD is not set\n# CONFIG_KEYBOARD_TCA6416 is not set\n# CONFIG_KEYBOARD_TCA8418 is not set\n# CONFIG_KEYBOARD_TEGRA is not set\n# CONFIG_KEYBOARD_TM2_TOUCHKEY is not set\n# CONFIG_KEYBOARD_TWL4030 is not set\n# CONFIG_KEYBOARD_XTKBD is not set\n# CONFIG_KEYS is not set\n# CONFIG_KEYS_REQUEST_CACHE is not set\n# CONFIG_KEY_DH_OPERATIONS is not set\n# CONFIG_KGDB is not set\n# CONFIG_KMEMCHECK is not set\n# CONFIG_KMX61 is not set\n# CONFIG_KPC2000 is not set\n# CONFIG_KPROBES is not set\n# CONFIG_KPROBES_SANITY_TEST is not set\n# CONFIG_KPROBE_EVENTS_ON_NOTRACE is not set\n# CONFIG_KPROBE_EVENT_GEN_TEST is not set\n# CONFIG_KS7010 is not set\n# CONFIG_KS8842 is not set\n# CONFIG_KS8851 is not set\n# CONFIG_KS8851_MLL is not set\n# CONFIG_KSM is not set\n# CONFIG_KSZ884X_PCI is not set\n# CONFIG_KUNIT is not set\nCONFIG_KUSER_HELPERS=y\n# CONFIG_KVM_AMD is not set\n# CONFIG_KVM_AMD_SEV is not set\n# CONFIG_KVM_GUEST is not set\n# CONFIG_KVM_INTEL is not set\n# CONFIG_KVM_WERROR is not set\n# CONFIG_KXCJK1013 is not set\n# CONFIG_KXSD9 is not set\n# CONFIG_L2TP is not set\n# CONFIG_L2TP_ETH is not set\n# CONFIG_L2TP_IP is not set\n# CONFIG_L2TP_V3 is not set\n# CONFIG_LAN743X is not set\n# CONFIG_LANMEDIA is not set\n# CONFIG_LANTIQ is not set\n# CONFIG_LAPB is not set\n# CONFIG_LASAT is not set\n# CONFIG_LATENCYTOP is not set\n# CONFIG_LATTICE_ECP3_CONFIG is not set\nCONFIG_LBDAF=y\n# CONFIG_LCD_AMS369FG06 is not set\n# CONFIG_LCD_CLASS_DEVICE is not set\n# CONFIG_LCD_HX8357 is not set\n# CONFIG_LCD_ILI922X is not set\n# CONFIG_LCD_ILI9320 is not set\n# CONFIG_LCD_L4F00242T03 is not set\n# CONFIG_LCD_LD9040 is not set\n# CONFIG_LCD_LMS283GF05 is not set\n# CONFIG_LCD_LMS501KF03 is not set\n# CONFIG_LCD_LTV350QV is not set\n# CONFIG_LCD_OTM3225A is not set\n# CONFIG_LCD_S6E63M0 is not set\n# CONFIG_LCD_TDO24M is not set\n# CONFIG_LCD_VGG2432A4 is not set\nCONFIG_LDISC_AUTOLOAD=y\n# CONFIG_LDM_PARTITION is not set\nCONFIG_LD_DEAD_CODE_DATA_ELIMINATION=y\n# CONFIG_LEDS_AN30259A is not set\n# CONFIG_LEDS_APU is not set\n# CONFIG_LEDS_AW2013 is not set\n# CONFIG_LEDS_BCM6328 is not set\n# CONFIG_LEDS_BCM6358 is not set\n# CONFIG_LEDS_BD2802 is not set\n# CONFIG_LEDS_BLINKM is not set\nCONFIG_LEDS_BRIGHTNESS_HW_CHANGED=y\nCONFIG_LEDS_CLASS=y\n# CONFIG_LEDS_CLASS_FLASH is not set\nCONFIG_LEDS_CLASS_MULTICOLOR=y\n# CONFIG_LEDS_CR0014114 is not set\n# CONFIG_LEDS_DAC124S085 is not set\n# CONFIG_LEDS_EL15203000 is not set\n# CONFIG_LEDS_GPIO is not set\n# CONFIG_LEDS_INTEL_SS4200 is not set\n# CONFIG_LEDS_IS31FL319X is not set\n# CONFIG_LEDS_IS31FL32XX is not set\n# CONFIG_LEDS_LM3530 is not set\n# CONFIG_LEDS_LM3532 is not set\n# CONFIG_LEDS_LM355x is not set\n# CONFIG_LEDS_LM3642 is not set\n# CONFIG_LEDS_LM3692X is not set\n# CONFIG_LEDS_LP3944 is not set\n# CONFIG_LEDS_LP3952 is not set\n# CONFIG_LEDS_LP50XX is not set\n# CONFIG_LEDS_LP5521 is not set\n# CONFIG_LEDS_LP5523 is not set\n# CONFIG_LEDS_LP5562 is not set\n# CONFIG_LEDS_LP55XX_COMMON is not set\n# CONFIG_LEDS_LP8501 is not set\n# CONFIG_LEDS_LP8860 is not set\n# CONFIG_LEDS_LT3593 is not set\n# CONFIG_LEDS_MLXCPLD is not set\n# CONFIG_LEDS_MLXREG is not set\n# CONFIG_LEDS_NIC78BX is not set\n# CONFIG_LEDS_NS2 is not set\n# CONFIG_LEDS_OT200 is not set\n# CONFIG_LEDS_PCA9532 is not set\n# CONFIG_LEDS_PCA955X is not set\n# CONFIG_LEDS_PCA963X is not set\n# CONFIG_LEDS_PWM is not set\n# CONFIG_LEDS_REGULATOR is not set\n# CONFIG_LEDS_SPI_BYTE is not set\n# CONFIG_LEDS_SYSCON is not set\n# CONFIG_LEDS_TCA6507 is not set\n# CONFIG_LEDS_TI_LMU_COMMON is not set\n# CONFIG_LEDS_TLC591XX is not set\nCONFIG_LEDS_TRIGGERS=y\n# CONFIG_LEDS_TRIGGER_ACTIVITY is not set\n# CONFIG_LEDS_TRIGGER_AUDIO is not set\n# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set\n# CONFIG_LEDS_TRIGGER_CAMERA is not set\n# CONFIG_LEDS_TRIGGER_CPU is not set\nCONFIG_LEDS_TRIGGER_DEFAULT_ON=y\n# CONFIG_LEDS_TRIGGER_DISK is not set\n# CONFIG_LEDS_TRIGGER_GPIO is not set\nCONFIG_LEDS_TRIGGER_HEARTBEAT=y\n# CONFIG_LEDS_TRIGGER_MTD is not set\nCONFIG_LEDS_TRIGGER_NETDEV=y\n# CONFIG_LEDS_TRIGGER_ONESHOT is not set\n# CONFIG_LEDS_TRIGGER_PANIC is not set\n# CONFIG_LEDS_TRIGGER_PATTERN is not set\nCONFIG_LEDS_TRIGGER_TIMER=y\n# CONFIG_LEDS_TRIGGER_TRANSIENT is not set\n# CONFIG_LEDS_TURRIS_OMNIA is not set\n# CONFIG_LEDS_USER is not set\n# CONFIG_LED_TRIGGER_PHY is not set\n# CONFIG_LEGACY_PTYS is not set\n# CONFIG_LGUEST is not set\n# CONFIG_LIB80211 is not set\n# CONFIG_LIB80211_CRYPT_CCMP is not set\n# CONFIG_LIB80211_CRYPT_TKIP is not set\n# CONFIG_LIB80211_CRYPT_WEP is not set\n# CONFIG_LIB80211_DEBUG is not set\n# CONFIG_LIBCRC32C is not set\n# CONFIG_LIBERTAS is not set\n# CONFIG_LIBERTAS_THINFIRM is not set\n# CONFIG_LIBERTAS_USB is not set\n# CONFIG_LIBFC is not set\n# CONFIG_LIBFCOE is not set\n# CONFIG_LIBIPW_DEBUG is not set\n# CONFIG_LIBNVDIMM is not set\n# CONFIG_LIDAR_LITE_V2 is not set\nCONFIG_LINEAR_RANGES=y\n# CONFIG_LIQUIDIO is not set\n# CONFIG_LIQUIDIO_VF is not set\n# CONFIG_LIS3L02DQ is not set\n# CONFIG_LKDTM is not set\nCONFIG_LLC=y\n# CONFIG_LLC2 is not set\n# CONFIG_LMP91000 is not set\n# CONFIG_LNET is not set\nCONFIG_LOCALVERSION=\"\"\n# CONFIG_LOCALVERSION_AUTO is not set\n# CONFIG_LOCKD is not set\nCONFIG_LOCKDEP_SUPPORT=y\nCONFIG_LOCKD_V4=y\n# CONFIG_LOCKUP_DETECTOR is not set\n# CONFIG_LOCK_EVENT_COUNTS is not set\n# CONFIG_LOCK_STAT is not set\n# CONFIG_LOCK_TORTURE_TEST is not set\n# CONFIG_LOGFS is not set\n# CONFIG_LOGIG940_FF is not set\n# CONFIG_LOGIRUMBLEPAD2_FF is not set\n# CONFIG_LOGITECH_FF is not set\n# CONFIG_LOGIWHEELS_FF is not set\n# CONFIG_LOGO is not set\nCONFIG_LOG_BUF_SHIFT=17\nCONFIG_LOG_CPU_MAX_BUF_SHIFT=12\n# CONFIG_LOONGSON_MC146818 is not set\n# CONFIG_LPC_ICH is not set\n# CONFIG_LPC_SCH is not set\n# CONFIG_LP_CONSOLE is not set\n# CONFIG_LSI_ET1011C_PHY is not set\nCONFIG_LSM=\"lockdown,yama,loadpin,safesetid,integrity\"\nCONFIG_LSM_MMAP_MIN_ADDR=65536\n# CONFIG_LTC1660 is not set\n# CONFIG_LTC2471 is not set\n# CONFIG_LTC2485 is not set\n# CONFIG_LTC2496 is not set\n# CONFIG_LTC2497 is not set\n# CONFIG_LTC2632 is not set\n# CONFIG_LTC2983 is not set\n# CONFIG_LTE_GDM724X is not set\n# CONFIG_LTPC is not set\n# CONFIG_LTR501 is not set\n# CONFIG_LUSTRE_FS is not set\n# CONFIG_LV0104CS is not set\n# CONFIG_LWTUNNEL is not set\n# CONFIG_LXT_PHY is not set\n# CONFIG_LZ4HC_COMPRESS is not set\n# CONFIG_LZ4_COMPRESS is not set\n# CONFIG_LZ4_DECOMPRESS is not set\nCONFIG_LZMA_COMPRESS=y\nCONFIG_LZMA_DECOMPRESS=y\n# CONFIG_LZO_COMPRESS is not set\n# CONFIG_LZO_DECOMPRESS is not set\n# CONFIG_M62332 is not set\n# CONFIG_MAC80211 is not set\n# CONFIG_MAC80211_MESSAGE_TRACING is not set\nCONFIG_MAC80211_STA_HASH_MAX_SIZE=0\n# CONFIG_MACB is not set\n# CONFIG_MACB_USE_HWSTAMP is not set\n# CONFIG_MACH_ASM9260 is not set\n# CONFIG_MACH_DECSTATION is not set\n# CONFIG_MACH_INGENIC is not set\n# CONFIG_MACH_INGENIC_SOC is not set\n# CONFIG_MACH_JAZZ is not set\n# CONFIG_MACH_JZ4740 is not set\n# CONFIG_MACH_LOONGSON2EF is not set\n# CONFIG_MACH_LOONGSON32 is not set\n# CONFIG_MACH_LOONGSON64 is not set\n# CONFIG_MACH_PIC32 is not set\n# CONFIG_MACH_PISTACHIO is not set\n# CONFIG_MACH_TX39XX is not set\n# CONFIG_MACH_TX49XX is not set\n# CONFIG_MACH_VR41XX is not set\n# CONFIG_MACH_XILFPGA is not set\n# CONFIG_MACINTOSH_DRIVERS is not set\n# CONFIG_MACSEC is not set\n# CONFIG_MACVLAN is not set\n# CONFIG_MACVTAP is not set\n# CONFIG_MAC_EMUMOUSEBTN is not set\n# CONFIG_MAC_PARTITION is not set\n# CONFIG_MAG3110 is not set\n# CONFIG_MAGIC_SYSRQ is not set\nCONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1\n# CONFIG_MAGIC_SYSRQ_SERIAL is not set\nCONFIG_MAGIC_SYSRQ_SERIAL_SEQUENCE=\"\"\n# CONFIG_MAILBOX is not set\n# CONFIG_MANAGER_SBS is not set\n# CONFIG_MANDATORY_FILE_LOCKING is not set\n# CONFIG_MANGLE_BOOTARGS is not set\n# CONFIG_MARVELL_10G_PHY is not set\n# CONFIG_MARVELL_PHY is not set\n# CONFIG_MAX1027 is not set\n# CONFIG_MAX11100 is not set\n# CONFIG_MAX1118 is not set\n# CONFIG_MAX1241 is not set\n# CONFIG_MAX1363 is not set\n# CONFIG_MAX30100 is not set\n# CONFIG_MAX30102 is not set\n# CONFIG_MAX31856 is not set\n# CONFIG_MAX44000 is not set\n# CONFIG_MAX44009 is not set\n# CONFIG_MAX517 is not set\n# CONFIG_MAX5432 is not set\n# CONFIG_MAX5481 is not set\n# CONFIG_MAX5487 is not set\n# CONFIG_MAX5821 is not set\n# CONFIG_MAX63XX_WATCHDOG is not set\n# CONFIG_MAX9611 is not set\n# CONFIG_MAXIM_THERMOCOUPLE is not set\nCONFIG_MAY_USE_DEVLINK=y\n# CONFIG_MB1232 is not set\n# CONFIG_MC3230 is not set\n# CONFIG_MCB is not set\n# CONFIG_MCP320X is not set\n# CONFIG_MCP3422 is not set\n# CONFIG_MCP3911 is not set\n# CONFIG_MCP4018 is not set\n# CONFIG_MCP41010 is not set\n# CONFIG_MCP4131 is not set\n# CONFIG_MCP4531 is not set\n# CONFIG_MCP4725 is not set\n# CONFIG_MCP4922 is not set\n# CONFIG_MCPM is not set\n# CONFIG_MD is not set\n# CONFIG_MDIO_BCM_UNIMAC is not set\n# CONFIG_MDIO_BITBANG is not set\n# CONFIG_MDIO_BUS_MUX_GPIO is not set\n# CONFIG_MDIO_BUS_MUX_MMIOREG is not set\n# CONFIG_MDIO_BUS_MUX_MULTIPLEXER is not set\n# CONFIG_MDIO_DEVICE is not set\n# CONFIG_MDIO_DEVRES is not set\n# CONFIG_MDIO_HISI_FEMAC is not set\n# CONFIG_MDIO_IPQ4019 is not set\n# CONFIG_MDIO_IPQ8064 is not set\n# CONFIG_MDIO_MSCC_MIIM is not set\n# CONFIG_MDIO_MVUSB is not set\n# CONFIG_MDIO_OCTEON is not set\n# CONFIG_MDIO_THUNDER is not set\n# CONFIG_MDIO_XPCS is not set\n# CONFIG_MD_FAULTY is not set\n# CONFIG_MEDIATEK_GE_PHY is not set\n# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set\n# CONFIG_MEDIA_ATTACH is not set\n# CONFIG_MEDIA_CAMERA_SUPPORT is not set\n# CONFIG_MEDIA_CEC_SUPPORT is not set\n# CONFIG_MEDIA_CONTROLLER is not set\n# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set\n# CONFIG_MEDIA_PCI_SUPPORT is not set\n# CONFIG_MEDIA_PLATFORM_SUPPORT is not set\n# CONFIG_MEDIA_RADIO_SUPPORT is not set\n# CONFIG_MEDIA_RC_SUPPORT is not set\n# CONFIG_MEDIA_SDR_SUPPORT is not set\n# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set\n# CONFIG_MEDIA_SUPPORT is not set\n# CONFIG_MEDIA_SUPPORT_FILTER is not set\n# CONFIG_MEDIA_TEST_SUPPORT is not set\n# CONFIG_MEDIA_TUNER_E4000 is not set\n# CONFIG_MEDIA_TUNER_FC0011 is not set\n# CONFIG_MEDIA_TUNER_FC0012 is not set\n# CONFIG_MEDIA_TUNER_FC0013 is not set\n# CONFIG_MEDIA_TUNER_FC2580 is not set\n# CONFIG_MEDIA_TUNER_IT913X is not set\n# CONFIG_MEDIA_TUNER_M88RS6000T is not set\n# CONFIG_MEDIA_TUNER_MAX2165 is not set\n# CONFIG_MEDIA_TUNER_MC44S803 is not set\n# CONFIG_MEDIA_TUNER_MSI001 is not set\n# CONFIG_MEDIA_TUNER_MT2060 is not set\n# CONFIG_MEDIA_TUNER_MT2063 is not set\n# CONFIG_MEDIA_TUNER_MT20XX is not set\n# CONFIG_MEDIA_TUNER_MT2131 is not set\n# CONFIG_MEDIA_TUNER_MT2266 is not set\n# CONFIG_MEDIA_TUNER_MXL301RF is not set\n# CONFIG_MEDIA_TUNER_MXL5005S is not set\n# CONFIG_MEDIA_TUNER_MXL5007T is not set\n# CONFIG_MEDIA_TUNER_QM1D1B0004 is not set\n# CONFIG_MEDIA_TUNER_QM1D1C0042 is not set\n# CONFIG_MEDIA_TUNER_QT1010 is not set\n# CONFIG_MEDIA_TUNER_R820T is not set\n# CONFIG_MEDIA_TUNER_SI2157 is not set\n# CONFIG_MEDIA_TUNER_SIMPLE is not set\n# CONFIG_MEDIA_TUNER_TDA18212 is not set\n# CONFIG_MEDIA_TUNER_TDA18218 is not set\n# CONFIG_MEDIA_TUNER_TDA18250 is not set\n# CONFIG_MEDIA_TUNER_TDA18271 is not set\n# CONFIG_MEDIA_TUNER_TDA827X is not set\n# CONFIG_MEDIA_TUNER_TDA8290 is not set\n# CONFIG_MEDIA_TUNER_TDA9887 is not set\n# CONFIG_MEDIA_TUNER_TEA5761 is not set\n# CONFIG_MEDIA_TUNER_TEA5767 is not set\n# CONFIG_MEDIA_TUNER_TUA9001 is not set\n# CONFIG_MEDIA_TUNER_XC2028 is not set\n# CONFIG_MEDIA_TUNER_XC4000 is not set\n# CONFIG_MEDIA_TUNER_XC5000 is not set\n# CONFIG_MEDIA_USB_SUPPORT is not set\n# CONFIG_MEGARAID_LEGACY is not set\n# CONFIG_MEGARAID_NEWGEN is not set\n# CONFIG_MEGARAID_SAS is not set\n# CONFIG_MELLANOX_PLATFORM is not set\nCONFIG_MEMBARRIER=y\n# CONFIG_MEMORY is not set\n# CONFIG_MEMORY_FAILURE is not set\n# CONFIG_MEMORY_HOTPLUG is not set\n# CONFIG_MEMSTICK is not set\n# CONFIG_MEMTEST is not set\n# CONFIG_MEN_A21_WDT is not set\n# CONFIG_MESON_SM is not set\nCONFIG_MESSAGE_LOGLEVEL_DEFAULT=4\n# CONFIG_MFD_88PM800 is not set\n# CONFIG_MFD_88PM805 is not set\n# CONFIG_MFD_88PM860X is not set\n# CONFIG_MFD_AAT2870_CORE is not set\n# CONFIG_MFD_AC100 is not set\n# CONFIG_MFD_ACT8945A is not set\n# CONFIG_MFD_ARIZONA_I2C is not set\n# CONFIG_MFD_ARIZONA_SPI is not set\n# CONFIG_MFD_AS3711 is not set\n# CONFIG_MFD_AS3722 is not set\n# CONFIG_MFD_ASIC3 is not set\n# CONFIG_MFD_ATMEL_FLEXCOM is not set\n# CONFIG_MFD_ATMEL_HLCDC is not set\n# CONFIG_MFD_AXP20X is not set\n# CONFIG_MFD_AXP20X_I2C is not set\n# CONFIG_MFD_BCM590XX is not set\n# CONFIG_MFD_BD9571MWV is not set\n# CONFIG_MFD_CORE is not set\n# CONFIG_MFD_CPCAP is not set\n# CONFIG_MFD_CROS_EC is not set\n# CONFIG_MFD_CS5535 is not set\n# CONFIG_MFD_DA9052_I2C is not set\n# CONFIG_MFD_DA9052_SPI is not set\n# CONFIG_MFD_DA9055 is not set\n# CONFIG_MFD_DA9062 is not set\n# CONFIG_MFD_DA9063 is not set\n# CONFIG_MFD_DA9150 is not set\n# CONFIG_MFD_DLN2 is not set\n# CONFIG_MFD_EXYNOS_LPASS is not set\n# CONFIG_MFD_GATEWORKS_GSC is not set\n# CONFIG_MFD_HI6421_PMIC is not set\n# CONFIG_MFD_INTEL_M10_BMC is not set\n# CONFIG_MFD_INTEL_QUARK_I2C_GPIO is not set\n# CONFIG_MFD_IQS62X is not set\n# CONFIG_MFD_JANZ_CMODIO is not set\n# CONFIG_MFD_KEMPLD is not set\n# CONFIG_MFD_LM3533 is not set\n# CONFIG_MFD_LOCHNAGAR is not set\n# CONFIG_MFD_LP3943 is not set\n# CONFIG_MFD_LP8788 is not set\n# CONFIG_MFD_MADERA is not set\n# CONFIG_MFD_MAX14577 is not set\n# CONFIG_MFD_MAX77620 is not set\n# CONFIG_MFD_MAX77650 is not set\n# CONFIG_MFD_MAX77686 is not set\n# CONFIG_MFD_MAX77693 is not set\n# CONFIG_MFD_MAX77843 is not set\n# CONFIG_MFD_MAX8907 is not set\n# CONFIG_MFD_MAX8925 is not set\n# CONFIG_MFD_MAX8997 is not set\n# CONFIG_MFD_MAX8998 is not set\n# CONFIG_MFD_MC13XXX is not set\n# CONFIG_MFD_MC13XXX_I2C is not set\n# CONFIG_MFD_MC13XXX_SPI is not set\n# CONFIG_MFD_MENF21BMC is not set\n# CONFIG_MFD_MP2629 is not set\n# CONFIG_MFD_MT6360 is not set\n# CONFIG_MFD_MT6397 is not set\n# CONFIG_MFD_OMAP_USB_HOST is not set\n# CONFIG_MFD_PALMAS is not set\n# CONFIG_MFD_PCF50633 is not set\n# CONFIG_MFD_PM8921_CORE is not set\n# CONFIG_MFD_PM8XXX is not set\n# CONFIG_MFD_RC5T583 is not set\n# CONFIG_MFD_RDC321X is not set\n# CONFIG_MFD_RETU is not set\n# CONFIG_MFD_RK808 is not set\n# CONFIG_MFD_RN5T618 is not set\n# CONFIG_MFD_ROHM_BD70528 is not set\n# CONFIG_MFD_ROHM_BD71828 is not set\n# CONFIG_MFD_ROHM_BD718XX is not set\n# CONFIG_MFD_RT5033 is not set\n# CONFIG_MFD_RTSX_PCI is not set\n# CONFIG_MFD_RTSX_USB is not set\n# CONFIG_MFD_SEC_CORE is not set\n# CONFIG_MFD_SI476X_CORE is not set\n# CONFIG_MFD_SKY81452 is not set\n# CONFIG_MFD_SL28CPLD is not set\n# CONFIG_MFD_SM501 is not set\n# CONFIG_MFD_SMSC is not set\n# CONFIG_MFD_STMFX is not set\n# CONFIG_MFD_STMPE is not set\n# CONFIG_MFD_STPMIC1 is not set\n# CONFIG_MFD_SYSCON is not set\n# CONFIG_MFD_T7L66XB is not set\n# CONFIG_MFD_TC3589X is not set\n# CONFIG_MFD_TC6387XB is not set\n# CONFIG_MFD_TC6393XB is not set\n# CONFIG_MFD_TIMBERDALE is not set\n# CONFIG_MFD_TI_AM335X_TSCADC is not set\n# CONFIG_MFD_TI_LMU is not set\n# CONFIG_MFD_TI_LP873X is not set\n# CONFIG_MFD_TI_LP87565 is not set\n# CONFIG_MFD_TMIO is not set\n# CONFIG_MFD_TPS65086 is not set\n# CONFIG_MFD_TPS65090 is not set\n# CONFIG_MFD_TPS65217 is not set\n# CONFIG_MFD_TPS65218 is not set\n# CONFIG_MFD_TPS6586X is not set\n# CONFIG_MFD_TPS65910 is not set\n# CONFIG_MFD_TPS65912 is not set\n# CONFIG_MFD_TPS65912_I2C is not set\n# CONFIG_MFD_TPS65912_SPI is not set\n# CONFIG_MFD_TPS68470 is not set\n# CONFIG_MFD_TPS80031 is not set\n# CONFIG_MFD_TQMX86 is not set\n# CONFIG_MFD_VIPERBOARD is not set\n# CONFIG_MFD_VX855 is not set\n# CONFIG_MFD_WL1273_CORE is not set\n# CONFIG_MFD_WM831X is not set\n# CONFIG_MFD_WM831X_I2C is not set\n# CONFIG_MFD_WM831X_SPI is not set\n# CONFIG_MFD_WM8350_I2C is not set\n# CONFIG_MFD_WM8400 is not set\n# CONFIG_MFD_WM8994 is not set\n# CONFIG_MG_DISK is not set\n# CONFIG_MHI_BUS is not set\n# CONFIG_MICREL_KS8995MA is not set\n# CONFIG_MICREL_PHY is not set\n# CONFIG_MICROCHIP_KSZ is not set\n# CONFIG_MICROCHIP_PHY is not set\n# CONFIG_MICROCHIP_PIT64B is not set\n# CONFIG_MICROCHIP_T1_PHY is not set\n# CONFIG_MICROSEMI_PHY is not set\n# CONFIG_MIGRATION is not set\nCONFIG_MII=y\n# CONFIG_MIKROTIK is not set\n# CONFIG_MIKROTIK_RB532 is not set\n# CONFIG_MINIX_FS is not set\n# CONFIG_MINIX_FS_NATIVE_ENDIAN is not set\n# CONFIG_MINIX_SUBPARTITION is not set\n# CONFIG_MIPS_ALCHEMY is not set\n# CONFIG_MIPS_CDMM is not set\n# CONFIG_MIPS_COBALT is not set\n# CONFIG_MIPS_FPU_EMULATOR is not set\n# CONFIG_MIPS_FP_SUPPORT is not set\n# CONFIG_MIPS_GENERIC is not set\n# CONFIG_MIPS_GENERIC_KERNEL is not set\n# CONFIG_MIPS_MALTA is not set\n# CONFIG_MIPS_O32_FP64_SUPPORT is not set\n# CONFIG_MIPS_PARAVIRT is not set\n# CONFIG_MIPS_PLATFORM_DEVICES is not set\n# CONFIG_MIPS_SEAD3 is not set\n# CONFIG_MISC_ALCOR_PCI is not set\nCONFIG_MISC_FILESYSTEMS=y\n# CONFIG_MISC_RTSX_PCI is not set\n# CONFIG_MISC_RTSX_USB is not set\n# CONFIG_MISDN is not set\n# CONFIG_MISDN_AVMFRITZ is not set\n# CONFIG_MISDN_HFCPCI is not set\n# CONFIG_MISDN_HFCUSB is not set\n# CONFIG_MISDN_INFINEON is not set\n# CONFIG_MISDN_NETJET is not set\n# CONFIG_MISDN_SPEEDFAX is not set\n# CONFIG_MISDN_W6692 is not set\nCONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY=y\n# CONFIG_MKISS is not set\n# CONFIG_MLX4_CORE is not set\n# CONFIG_MLX4_EN is not set\n# CONFIG_MLX5_CORE is not set\n# CONFIG_MLX90614 is not set\n# CONFIG_MLX90632 is not set\n# CONFIG_MLXFW is not set\n# CONFIG_MLXSW_CORE is not set\n# CONFIG_MLX_CPLD_PLATFORM is not set\n# CONFIG_MLX_PLATFORM is not set\n# CONFIG_MMA7455_I2C is not set\n# CONFIG_MMA7455_SPI is not set\n# CONFIG_MMA7660 is not set\n# CONFIG_MMA8452 is not set\n# CONFIG_MMA9551 is not set\n# CONFIG_MMA9553 is not set\n# CONFIG_MMC is not set\n# CONFIG_MMC35240 is not set\n# CONFIG_MMC_ARMMMCI is not set\n# CONFIG_MMC_AU1X is not set\n# CONFIG_MMC_BLOCK is not set\nCONFIG_MMC_BLOCK_BOUNCE=y\nCONFIG_MMC_BLOCK_MINORS=8\n# CONFIG_MMC_CAVIUM_THUNDERX is not set\n# CONFIG_MMC_CB710 is not set\n# CONFIG_MMC_CQHCI is not set\n# CONFIG_MMC_DEBUG is not set\n# CONFIG_MMC_DW is not set\n# CONFIG_MMC_HSQ is not set\n# CONFIG_MMC_JZ4740 is not set\n# CONFIG_MMC_MTK is not set\n# CONFIG_MMC_MVSDIO is not set\n# CONFIG_MMC_S3C is not set\n# CONFIG_MMC_SDHCI is not set\n# CONFIG_MMC_SDHCI_ACPI is not set\n# CONFIG_MMC_SDHCI_AM654 is not set\n# CONFIG_MMC_SDHCI_BCM_KONA is not set\n# CONFIG_MMC_SDHCI_CADENCE is not set\n# CONFIG_MMC_SDHCI_F_SDH30 is not set\n# CONFIG_MMC_SDHCI_IPROC is not set\n# CONFIG_MMC_SDHCI_MILBEAUT is not set\n# CONFIG_MMC_SDHCI_MSM is not set\n# CONFIG_MMC_SDHCI_OF_ARASAN is not set\n# CONFIG_MMC_SDHCI_OF_ASPEED is not set\n# CONFIG_MMC_SDHCI_OF_AT91 is not set\n# CONFIG_MMC_SDHCI_OF_DWCMSHC is not set\n# CONFIG_MMC_SDHCI_OF_ESDHC is not set\n# CONFIG_MMC_SDHCI_OF_HLWD is not set\n# CONFIG_MMC_SDHCI_OMAP is not set\n# CONFIG_MMC_SDHCI_PXAV2 is not set\n# CONFIG_MMC_SDHCI_PXAV3 is not set\n# CONFIG_MMC_SDHCI_S3C is not set\n# CONFIG_MMC_SDHCI_XENON is not set\n# CONFIG_MMC_SDRICOH_CS is not set\n# CONFIG_MMC_SPI is not set\n# CONFIG_MMC_STM32_SDMMC is not set\n# CONFIG_MMC_TEST is not set\n# CONFIG_MMC_TIFM_SD is not set\n# CONFIG_MMC_TOSHIBA_PCI is not set\n# CONFIG_MMC_USDHI6ROL0 is not set\n# CONFIG_MMC_USHC is not set\n# CONFIG_MMC_VIA_SDMMC is not set\n# CONFIG_MMC_VUB300 is not set\n# CONFIG_MMIOTRACE is not set\nCONFIG_MMU=y\nCONFIG_MMU_GATHER_RCU_TABLE_FREE=y\nCONFIG_MMU_GATHER_TABLE_FREE=y\nCONFIG_MODULES=y\n# CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set\n# CONFIG_MODULE_COMPRESS is not set\n# CONFIG_MODULE_FORCE_LOAD is not set\n# CONFIG_MODULE_FORCE_UNLOAD is not set\n# CONFIG_MODULE_SIG is not set\n# CONFIG_MODULE_SRCVERSION_ALL is not set\nCONFIG_MODULE_STRIPPED=y\nCONFIG_MODULE_UNLOAD=y\n# CONFIG_MODVERSIONS is not set\n# CONFIG_MOST is not set\n# CONFIG_MOUSE_APPLETOUCH is not set\n# CONFIG_MOUSE_ELAN_I2C is not set\n# CONFIG_MOUSE_GPIO is not set\n# CONFIG_MOUSE_INPORT is not set\n# CONFIG_MOUSE_LOGIBM is not set\n# CONFIG_MOUSE_PC110PAD is not set\n# CONFIG_MOUSE_PS2_FOCALTECH is not set\n# CONFIG_MOUSE_PS2_SENTELIC is not set\n# CONFIG_MOUSE_SYNAPTICS_I2C is not set\n# CONFIG_MOUSE_SYNAPTICS_USB is not set\n# CONFIG_MOXTET is not set\n# CONFIG_MPL115 is not set\n# CONFIG_MPL115_I2C is not set\n# CONFIG_MPL115_SPI is not set\n# CONFIG_MPL3115 is not set\n# CONFIG_MPLS is not set\n# CONFIG_MPLS_IPTUNNEL is not set\n# CONFIG_MPLS_ROUTING is not set\n# CONFIG_MPTCP is not set\n# CONFIG_MPU3050_I2C is not set\n# CONFIG_MQ_IOSCHED_DEADLINE is not set\n# CONFIG_MQ_IOSCHED_KYBER is not set\n# CONFIG_MS5611 is not set\n# CONFIG_MS5637 is not set\n# CONFIG_MSCC_OCELOT_SWITCH is not set\n# CONFIG_MSDOS_FS is not set\nCONFIG_MSDOS_PARTITION=y\n# CONFIG_MSI_BITMAP_SELFTEST is not set\n# CONFIG_MSI_LAPTOP is not set\n# CONFIG_MST_IRQ is not set\nCONFIG_MTD=y\n# CONFIG_MTD_ABSENT is not set\n# CONFIG_MTD_AFS_PARTS is not set\n# CONFIG_MTD_AR7_PARTS is not set\nCONFIG_MTD_BLKDEVS=y\nCONFIG_MTD_BLOCK=y\n# CONFIG_MTD_BLOCK2MTD is not set\nCONFIG_MTD_CFI=y\n# CONFIG_MTD_CFI_ADV_OPTIONS is not set\nCONFIG_MTD_CFI_AMDSTD=y\n# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set\nCONFIG_MTD_CFI_I1=y\nCONFIG_MTD_CFI_I2=y\n# CONFIG_MTD_CFI_I4 is not set\n# CONFIG_MTD_CFI_I8 is not set\nCONFIG_MTD_CFI_INTELEXT=y\n# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set\nCONFIG_MTD_CFI_NOSWAP=y\n# CONFIG_MTD_CFI_STAA is not set\nCONFIG_MTD_CFI_UTIL=y\n# CONFIG_MTD_CMDLINE_PARTS is not set\nCONFIG_MTD_COMPLEX_MAPPINGS=y\n# CONFIG_MTD_DATAFLASH is not set\n# CONFIG_MTD_DOCG3 is not set\nCONFIG_MTD_GEN_PROBE=y\n# CONFIG_MTD_GPIO_ADDR is not set\n# CONFIG_MTD_HYPERBUS is not set\n# CONFIG_MTD_IMPA7 is not set\n# CONFIG_MTD_INTEL_VR_NOR is not set\n# CONFIG_MTD_JEDECPROBE is not set\n# CONFIG_MTD_LATCH_ADDR is not set\n# CONFIG_MTD_LPDDR is not set\n# CONFIG_MTD_LPDDR2_NVM is not set\n# CONFIG_MTD_M25P80 is not set\nCONFIG_MTD_MAP_BANK_WIDTH_1=y\n# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set\nCONFIG_MTD_MAP_BANK_WIDTH_2=y\n# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set\nCONFIG_MTD_MAP_BANK_WIDTH_4=y\n# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set\n# CONFIG_MTD_MCHP23K256 is not set\n# CONFIG_MTD_MT81xx_NOR is not set\n# CONFIG_MTD_MTDRAM is not set\n# CONFIG_MTD_MYLOADER_PARTS is not set\n# CONFIG_MTD_NAND is not set\n# CONFIG_MTD_NAND_AMS_DELTA is not set\n# CONFIG_MTD_NAND_AR934X is not set\n# CONFIG_MTD_NAND_AR934X_HW_ECC is not set\n# CONFIG_MTD_NAND_ARASAN is not set\n# CONFIG_MTD_NAND_ATMEL is not set\n# CONFIG_MTD_NAND_AU1550 is not set\n# CONFIG_MTD_NAND_BCH is not set\n# CONFIG_MTD_NAND_BF5XX is not set\n# CONFIG_MTD_NAND_BRCMNAND is not set\n# CONFIG_MTD_NAND_CADENCE is not set\n# CONFIG_MTD_NAND_CAFE is not set\n# CONFIG_MTD_NAND_CM_X270 is not set\n# CONFIG_MTD_NAND_CS553X is not set\n# CONFIG_MTD_NAND_DAVINCI is not set\n# CONFIG_MTD_NAND_DENALI is not set\n# CONFIG_MTD_NAND_DENALI_DT is not set\n# CONFIG_MTD_NAND_DENALI_PCI is not set\nCONFIG_MTD_NAND_DENALI_SCRATCH_REG_ADDR=0xff108018\n# CONFIG_MTD_NAND_DISKONCHIP is not set\n# CONFIG_MTD_NAND_DOCG4 is not set\n# CONFIG_MTD_NAND_ECC is not set\n# CONFIG_MTD_NAND_ECC_BCH is not set\n# CONFIG_MTD_NAND_ECC_SMC is not set\n# CONFIG_MTD_NAND_ECC_SW_BCH is not set\n# CONFIG_MTD_NAND_ECC_SW_HAMMING_SMC is not set\n# CONFIG_MTD_NAND_FSL_ELBC is not set\n# CONFIG_MTD_NAND_FSL_IFC is not set\n# CONFIG_MTD_NAND_FSL_UPM is not set\n# CONFIG_MTD_NAND_FSMC is not set\n# CONFIG_MTD_NAND_GPIO is not set\n# CONFIG_MTD_NAND_GPMI_NAND is not set\n# CONFIG_MTD_NAND_HISI504 is not set\nCONFIG_MTD_NAND_IDS=y\n# CONFIG_MTD_NAND_JZ4740 is not set\n# CONFIG_MTD_NAND_MPC5121_NFC is not set\n# CONFIG_MTD_NAND_MTK is not set\n# CONFIG_MTD_NAND_MTK_BMT is not set\n# CONFIG_MTD_NAND_MXC is not set\n# CONFIG_MTD_NAND_MXIC is not set\n# CONFIG_MTD_NAND_NANDSIM is not set\n# CONFIG_MTD_NAND_NDFC is not set\n# CONFIG_MTD_NAND_NUC900 is not set\n# CONFIG_MTD_NAND_OMAP2 is not set\n# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set\n# CONFIG_MTD_NAND_ORION is not set\n# CONFIG_MTD_NAND_PASEMI is not set\n# CONFIG_MTD_NAND_PLATFORM is not set\n# CONFIG_MTD_NAND_PXA3xx is not set\n# CONFIG_MTD_NAND_RB4XX is not set\n# CONFIG_MTD_NAND_RB750 is not set\n# CONFIG_MTD_NAND_RB91X is not set\n# CONFIG_MTD_NAND_RICOH is not set\n# CONFIG_MTD_NAND_S3C2410 is not set\n# CONFIG_MTD_NAND_SHARPSL is not set\n# CONFIG_MTD_NAND_SH_FLCTL is not set\n# CONFIG_MTD_NAND_SOCRATES is not set\n# CONFIG_MTD_NAND_TMIO is not set\n# CONFIG_MTD_NAND_TXX9NDFMC is not set\nCONFIG_MTD_OF_PARTS=y\n# CONFIG_MTD_ONENAND is not set\n# CONFIG_MTD_OOPS is not set\n# CONFIG_MTD_OTP is not set\n# CONFIG_MTD_PARSER_TRX is not set\n# CONFIG_MTD_PARTITIONED_MASTER is not set\n# CONFIG_MTD_PCI is not set\n# CONFIG_MTD_PCMCIA is not set\n# CONFIG_MTD_PHRAM is not set\n# CONFIG_MTD_PHYSMAP is not set\n# CONFIG_MTD_PHYSMAP_COMPAT is not set\n# CONFIG_MTD_PHYSMAP_GEMINI is not set\n# CONFIG_MTD_PHYSMAP_GPIO_ADDR is not set\n# CONFIG_MTD_PHYSMAP_IXP4XX is not set\nCONFIG_MTD_PHYSMAP_OF=y\n# CONFIG_MTD_PHYSMAP_OF_GEMINI is not set\n# CONFIG_MTD_PHYSMAP_OF_VERSATILE is not set\n# CONFIG_MTD_PHYSMAP_VERSATILE is not set\n# CONFIG_MTD_PLATRAM is not set\n# CONFIG_MTD_PMC551 is not set\n# CONFIG_MTD_RAM is not set\n# CONFIG_MTD_RAW_NAND is not set\nCONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1\n# CONFIG_MTD_REDBOOT_PARTS is not set\n# CONFIG_MTD_REDBOOT_PARTS_READONLY is not set\n# CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED is not set\n# CONFIG_MTD_ROM is not set\nCONFIG_MTD_ROOTFS_ROOT_DEV=y\n# CONFIG_MTD_ROUTERBOOT_PARTS is not set\n# CONFIG_MTD_SLRAM is not set\n# CONFIG_MTD_SM_COMMON is not set\n# CONFIG_MTD_SPINAND_MT29F is not set\n# CONFIG_MTD_SPI_NAND is not set\n# CONFIG_MTD_SPI_NOR is not set\n# CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set\nCONFIG_MTD_SPI_NOR_USE_4K_SECTORS_LIMIT=4096\n# CONFIG_MTD_SPI_NOR_USE_VARIABLE_ERASE is not set\nCONFIG_MTD_SPLIT=y\n# CONFIG_MTD_SPLIT_BCM63XX_FW is not set\n# CONFIG_MTD_SPLIT_BCM_WFI_FW is not set\n# CONFIG_MTD_SPLIT_BRNIMAGE_FW is not set\n# CONFIG_MTD_SPLIT_ELF_FW is not set\n# CONFIG_MTD_SPLIT_EVA_FW is not set\n# CONFIG_MTD_SPLIT_FIRMWARE is not set\nCONFIG_MTD_SPLIT_FIRMWARE_NAME=\"firmware\"\n# CONFIG_MTD_SPLIT_FIT_FW is not set\n# CONFIG_MTD_SPLIT_JIMAGE_FW is not set\n# CONFIG_MTD_SPLIT_LZMA_FW is not set\n# CONFIG_MTD_SPLIT_MINOR_FW is not set\n# CONFIG_MTD_SPLIT_SEAMA_FW is not set\nCONFIG_MTD_SPLIT_SQUASHFS_ROOT=y\nCONFIG_MTD_SPLIT_SUPPORT=y\n# CONFIG_MTD_SPLIT_TPLINK_FW is not set\n# CONFIG_MTD_SPLIT_TRX_FW is not set\n# CONFIG_MTD_SPLIT_UIMAGE_FW is not set\n# CONFIG_MTD_SPLIT_WRGG_FW is not set\n# CONFIG_MTD_SST25L is not set\n# CONFIG_MTD_SWAP is not set\n# CONFIG_MTD_TESTS is not set\n# CONFIG_MTD_UBI is not set\n# CONFIG_MTD_UBI_FASTMAP is not set\n# CONFIG_MTD_UBI_GLUEBI is not set\n# CONFIG_MTD_UIMAGE_SPLIT is not set\n# CONFIG_MTD_VIRT_CONCAT is not set\n# CONFIG_MTK_MMC is not set\n# CONFIG_MTK_MMSYS is not set\n# CONFIG_MULTIPLEXER is not set\nCONFIG_MULTIUSER=y\n# CONFIG_MUTEX_SPIN_ON_OWNER is not set\n# CONFIG_MUX_ADG792A is not set\n# CONFIG_MUX_ADGS1408 is not set\n# CONFIG_MUX_GPIO is not set\n# CONFIG_MUX_MMIO is not set\n# CONFIG_MV643XX_ETH is not set\n# CONFIG_MVMDIO is not set\n# CONFIG_MVNETA_BM is not set\n# CONFIG_MVSW61XX_PHY is not set\n# CONFIG_MV_XOR_V2 is not set\n# CONFIG_MWAVE is not set\n# CONFIG_MWL8K is not set\n# CONFIG_MXC4005 is not set\n# CONFIG_MXC6255 is not set\n# CONFIG_MYRI10GE is not set\n# CONFIG_NAMESPACES is not set\n# CONFIG_NATIONAL_PHY is not set\n# CONFIG_NATSEMI is not set\n# CONFIG_NAU7802 is not set\n# CONFIG_NBPFAXI_DMA is not set\n# CONFIG_NCP_FS is not set\n# CONFIG_NE2000 is not set\n# CONFIG_NE2K_PCI is not set\n# CONFIG_NEC_MARKEINS is not set\nCONFIG_NET=y\n# CONFIG_NETCONSOLE is not set\nCONFIG_NETDEVICES=y\n# CONFIG_NETDEVSIM is not set\n# CONFIG_NETFILTER is not set\n# CONFIG_NETFILTER_ADVANCED is not set\n# CONFIG_NETFILTER_DEBUG is not set\n# CONFIG_NETFILTER_INGRESS is not set\n# CONFIG_NETFILTER_NETLINK is not set\n# CONFIG_NETFILTER_NETLINK_ACCT is not set\n# CONFIG_NETFILTER_NETLINK_GLUE_CT is not set\n# CONFIG_NETFILTER_NETLINK_LOG is not set\n# CONFIG_NETFILTER_NETLINK_OSF is not set\n# CONFIG_NETFILTER_NETLINK_QUEUE is not set\n# CONFIG_NETFILTER_XTABLES is not set\n# CONFIG_NETFILTER_XT_CONNMARK is not set\n# CONFIG_NETFILTER_XT_MARK is not set\n# CONFIG_NETFILTER_XT_MATCH_ADDRTYPE is not set\n# CONFIG_NETFILTER_XT_MATCH_BPF is not set\n# CONFIG_NETFILTER_XT_MATCH_CGROUP is not set\n# CONFIG_NETFILTER_XT_MATCH_CLUSTER is not set\n# CONFIG_NETFILTER_XT_MATCH_COMMENT is not set\n# CONFIG_NETFILTER_XT_MATCH_CONNBYTES is not set\n# CONFIG_NETFILTER_XT_MATCH_CONNLABEL is not set\n# CONFIG_NETFILTER_XT_MATCH_CONNLIMIT is not set\n# CONFIG_NETFILTER_XT_MATCH_CONNMARK is not set\n# CONFIG_NETFILTER_XT_MATCH_CONNTRACK is not set\n# CONFIG_NETFILTER_XT_MATCH_CPU is not set\n# CONFIG_NETFILTER_XT_MATCH_DCCP is not set\n# CONFIG_NETFILTER_XT_MATCH_DEVGROUP is not set\n# CONFIG_NETFILTER_XT_MATCH_DSCP is not set\n# CONFIG_NETFILTER_XT_MATCH_ECN is not set\n# CONFIG_NETFILTER_XT_MATCH_ESP is not set\n# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set\n# CONFIG_NETFILTER_XT_MATCH_HELPER is not set\n# CONFIG_NETFILTER_XT_MATCH_HL is not set\n# CONFIG_NETFILTER_XT_MATCH_IPCOMP is not set\n# CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set\n# CONFIG_NETFILTER_XT_MATCH_L2TP is not set\n# CONFIG_NETFILTER_XT_MATCH_LENGTH is not set\n# CONFIG_NETFILTER_XT_MATCH_LIMIT is not set\n# CONFIG_NETFILTER_XT_MATCH_MAC is not set\n# CONFIG_NETFILTER_XT_MATCH_MARK is not set\n# CONFIG_NETFILTER_XT_MATCH_MULTIPORT is not set\n# CONFIG_NETFILTER_XT_MATCH_NFACCT is not set\n# CONFIG_NETFILTER_XT_MATCH_OSF is not set\n# CONFIG_NETFILTER_XT_MATCH_OWNER is not set\n# CONFIG_NETFILTER_XT_MATCH_PHYSDEV is not set\n# CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set\n# CONFIG_NETFILTER_XT_MATCH_POLICY is not set\n# CONFIG_NETFILTER_XT_MATCH_QUOTA is not set\n# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set\n# CONFIG_NETFILTER_XT_MATCH_REALM is not set\n# CONFIG_NETFILTER_XT_MATCH_RECENT is not set\n# CONFIG_NETFILTER_XT_MATCH_SCTP is not set\n# CONFIG_NETFILTER_XT_MATCH_SOCKET is not set\n# CONFIG_NETFILTER_XT_MATCH_STATE is not set\n# CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set\n# CONFIG_NETFILTER_XT_MATCH_STRING is not set\n# CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set\n# CONFIG_NETFILTER_XT_MATCH_TIME is not set\n# CONFIG_NETFILTER_XT_MATCH_U32 is not set\n# CONFIG_NETFILTER_XT_TARGET_AUDIT is not set\n# CONFIG_NETFILTER_XT_TARGET_CHECKSUM is not set\n# CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set\n# CONFIG_NETFILTER_XT_TARGET_CONNMARK is not set\n# CONFIG_NETFILTER_XT_TARGET_CT is not set\n# CONFIG_NETFILTER_XT_TARGET_DSCP is not set\n# CONFIG_NETFILTER_XT_TARGET_HL is not set\n# CONFIG_NETFILTER_XT_TARGET_HMARK is not set\n# CONFIG_NETFILTER_XT_TARGET_IDLETIMER is not set\n# CONFIG_NETFILTER_XT_TARGET_LED is not set\n# CONFIG_NETFILTER_XT_TARGET_LOG is not set\n# CONFIG_NETFILTER_XT_TARGET_MARK is not set\n# CONFIG_NETFILTER_XT_TARGET_NETMAP is not set\n# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set\n# CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set\n# CONFIG_NETFILTER_XT_TARGET_NOTRACK is not set\n# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set\n# CONFIG_NETFILTER_XT_TARGET_REDIRECT is not set\n# CONFIG_NETFILTER_XT_TARGET_SECMARK is not set\n# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set\n# CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP is not set\n# CONFIG_NETFILTER_XT_TARGET_TEE is not set\n# CONFIG_NETFILTER_XT_TARGET_TPROXY is not set\n# CONFIG_NETFILTER_XT_TARGET_TRACE is not set\n# CONFIG_NETLABEL is not set\n# CONFIG_NETLINK_DIAG is not set\n# CONFIG_NETLINK_MMAP is not set\n# CONFIG_NETPOLL is not set\n# CONFIG_NETROM is not set\nCONFIG_NETWORK_FILESYSTEMS=y\n# CONFIG_NETWORK_PHY_TIMESTAMPING is not set\n# CONFIG_NETWORK_SECMARK is not set\n# CONFIG_NETXEN_NIC is not set\n# CONFIG_NET_9P is not set\n# CONFIG_NET_ACT_BPF is not set\n# CONFIG_NET_ACT_CSUM is not set\n# CONFIG_NET_ACT_CT is not set\n# CONFIG_NET_ACT_GACT is not set\n# CONFIG_NET_ACT_GATE is not set\n# CONFIG_NET_ACT_IFE is not set\n# CONFIG_NET_ACT_IPT is not set\n# CONFIG_NET_ACT_MIRRED is not set\n# CONFIG_NET_ACT_MPLS is not set\n# CONFIG_NET_ACT_NAT is not set\n# CONFIG_NET_ACT_PEDIT is not set\n# CONFIG_NET_ACT_POLICE is not set\n# CONFIG_NET_ACT_SAMPLE is not set\n# CONFIG_NET_ACT_SIMP is not set\n# CONFIG_NET_ACT_SKBEDIT is not set\n# CONFIG_NET_ACT_SKBMOD is not set\n# CONFIG_NET_ACT_TUNNEL_KEY is not set\n# CONFIG_NET_ACT_VLAN is not set\nCONFIG_NET_CADENCE=y\n# CONFIG_NET_CALXEDA_XGMAC is not set\nCONFIG_NET_CLS=y\n# CONFIG_NET_CLS_ACT is not set\n# CONFIG_NET_CLS_BASIC is not set\n# CONFIG_NET_CLS_BPF is not set\n# CONFIG_NET_CLS_FLOW is not set\n# CONFIG_NET_CLS_FLOWER is not set\n# CONFIG_NET_CLS_FW is not set\nCONFIG_NET_CLS_IND=y\n# CONFIG_NET_CLS_MATCHALL is not set\n# CONFIG_NET_CLS_ROUTE4 is not set\n# CONFIG_NET_CLS_RSVP is not set\n# CONFIG_NET_CLS_RSVP6 is not set\n# CONFIG_NET_CLS_TCINDEX is not set\n# CONFIG_NET_CLS_U32 is not set\nCONFIG_NET_CORE=y\n# CONFIG_NET_DEVLINK is not set\n# CONFIG_NET_DROP_MONITOR is not set\n# CONFIG_NET_DSA is not set\n# CONFIG_NET_DSA_AR9331 is not set\n# CONFIG_NET_DSA_BCM_SF2 is not set\n# CONFIG_NET_DSA_LANTIQ_GSWIP is not set\n# CONFIG_NET_DSA_LEGACY is not set\n# CONFIG_NET_DSA_LOOP is not set\n# CONFIG_NET_DSA_MICROCHIP_KSZ8795 is not set\n# CONFIG_NET_DSA_MICROCHIP_KSZ9477 is not set\n# CONFIG_NET_DSA_MSCC_FELIX is not set\n# CONFIG_NET_DSA_MSCC_SEVILLE is not set\n# CONFIG_NET_DSA_MT7530 is not set\n# CONFIG_NET_DSA_MV88E6060 is not set\n# CONFIG_NET_DSA_MV88E6123_61_65 is not set\n# CONFIG_NET_DSA_MV88E6131 is not set\n# CONFIG_NET_DSA_MV88E6171 is not set\n# CONFIG_NET_DSA_MV88E6352 is not set\n# CONFIG_NET_DSA_MV88E6XXX is not set\n# CONFIG_NET_DSA_MV88E6XXX_NEED_PPU is not set\n# CONFIG_NET_DSA_MV88E6XXX_PTP is not set\n# CONFIG_NET_DSA_QCA8K is not set\n# CONFIG_NET_DSA_REALTEK_SMI is not set\n# CONFIG_NET_DSA_SJA1105 is not set\n# CONFIG_NET_DSA_SMSC_LAN9303_I2C is not set\n# CONFIG_NET_DSA_SMSC_LAN9303_MDIO is not set\n# CONFIG_NET_DSA_TAG_8021Q is not set\n# CONFIG_NET_DSA_TAG_AR9331 is not set\n# CONFIG_NET_DSA_TAG_BRCM is not set\n# CONFIG_NET_DSA_TAG_BRCM_LEGACY is not set\n# CONFIG_NET_DSA_TAG_BRCM_PREPEND is not set\n# CONFIG_NET_DSA_TAG_DSA is not set\n# CONFIG_NET_DSA_TAG_EDSA is not set\n# CONFIG_NET_DSA_TAG_GSWIP is not set\n# CONFIG_NET_DSA_TAG_KSZ is not set\n# CONFIG_NET_DSA_TAG_LAN9303 is not set\n# CONFIG_NET_DSA_TAG_MTK is not set\n# CONFIG_NET_DSA_TAG_OCELOT is not set\n# CONFIG_NET_DSA_TAG_QCA is not set\n# CONFIG_NET_DSA_TAG_RTL4_A is not set\n# CONFIG_NET_DSA_TAG_SJA1105 is not set\n# CONFIG_NET_DSA_TAG_TRAILER is not set\n# CONFIG_NET_DSA_VITESSE_VSC73XX is not set\n# CONFIG_NET_DSA_VITESSE_VSC73XX_PLATFORM is not set\n# CONFIG_NET_DSA_VITESSE_VSC73XX_SPI is not set\n# CONFIG_NET_EMATCH is not set\n# CONFIG_NET_EMATCH_CANID is not set\n# CONFIG_NET_EMATCH_CMP is not set\n# CONFIG_NET_EMATCH_IPT is not set\n# CONFIG_NET_EMATCH_META is not set\n# CONFIG_NET_EMATCH_NBYTE is not set\nCONFIG_NET_EMATCH_STACK=32\n# CONFIG_NET_EMATCH_TEXT is not set\n# CONFIG_NET_EMATCH_U32 is not set\n# CONFIG_NET_FAILOVER is not set\n# CONFIG_NET_FC is not set\n# CONFIG_NET_FOU is not set\n# CONFIG_NET_FOU_IP_TUNNELS is not set\n# CONFIG_NET_IFE is not set\n# CONFIG_NET_IPGRE is not set\nCONFIG_NET_IPGRE_BROADCAST=y\n# CONFIG_NET_IPGRE_DEMUX is not set\n# CONFIG_NET_IPIP is not set\n# CONFIG_NET_IPVTI is not set\n# CONFIG_NET_IP_TUNNEL is not set\n# CONFIG_NET_KEY is not set\n# CONFIG_NET_KEY_MIGRATE is not set\n# CONFIG_NET_L3_MASTER_DEV is not set\n# CONFIG_NET_MEDIATEK_STAR_EMAC is not set\n# CONFIG_NET_MPLS_GSO is not set\n# CONFIG_NET_NCSI is not set\n# CONFIG_NET_NSH is not set\n# CONFIG_NET_PACKET_ENGINE is not set\n# CONFIG_NET_PKTGEN is not set\n# CONFIG_NET_POLL_CONTROLLER is not set\n# CONFIG_NET_PTP_CLASSIFY is not set\nCONFIG_NET_RX_BUSY_POLL=y\n# CONFIG_NET_SB1000 is not set\nCONFIG_NET_SCHED=y\n# CONFIG_NET_SCH_ATM is not set\n# CONFIG_NET_SCH_CAKE is not set\n# CONFIG_NET_SCH_CBQ is not set\n# CONFIG_NET_SCH_CBS is not set\n# CONFIG_NET_SCH_CHOKE is not set\n# CONFIG_NET_SCH_CODEL is not set\nCONFIG_NET_SCH_DEFAULT=y\n# CONFIG_NET_SCH_DRR is not set\n# CONFIG_NET_SCH_DSMARK is not set\n# CONFIG_NET_SCH_ETF is not set\n# CONFIG_NET_SCH_ETS is not set\nCONFIG_NET_SCH_FIFO=y\n# CONFIG_NET_SCH_FQ is not set\nCONFIG_NET_SCH_FQ_CODEL=y\n# CONFIG_NET_SCH_FQ_PIE is not set\n# CONFIG_NET_SCH_GRED is not set\n# CONFIG_NET_SCH_HFSC is not set\n# CONFIG_NET_SCH_HHF is not set\n# CONFIG_NET_SCH_HTB is not set\n# CONFIG_NET_SCH_INGRESS is not set\n# CONFIG_NET_SCH_MQPRIO is not set\n# CONFIG_NET_SCH_MULTIQ is not set\n# CONFIG_NET_SCH_NETEM is not set\n# CONFIG_NET_SCH_PIE is not set\n# CONFIG_NET_SCH_PLUG is not set\n# CONFIG_NET_SCH_PRIO is not set\n# CONFIG_NET_SCH_QFQ is not set\n# CONFIG_NET_SCH_RED is not set\n# CONFIG_NET_SCH_SFB is not set\n# CONFIG_NET_SCH_SFQ is not set\n# CONFIG_NET_SCH_SKBPRIO is not set\n# CONFIG_NET_SCH_TAPRIO is not set\n# CONFIG_NET_SCH_TBF is not set\n# CONFIG_NET_SCH_TEQL is not set\n# CONFIG_NET_SCTPPROBE is not set\n# CONFIG_NET_SWITCHDEV is not set\n# CONFIG_NET_TCPPROBE is not set\n# CONFIG_NET_TC_SKB_EXT is not set\n# CONFIG_NET_TEAM is not set\n# CONFIG_NET_TULIP is not set\n# CONFIG_NET_UDP_TUNNEL is not set\nCONFIG_NET_VENDOR_3COM=y\nCONFIG_NET_VENDOR_8390=y\nCONFIG_NET_VENDOR_ADAPTEC=y\nCONFIG_NET_VENDOR_AGERE=y\nCONFIG_NET_VENDOR_ALACRITECH=y\nCONFIG_NET_VENDOR_ALTEON=y\nCONFIG_NET_VENDOR_AMAZON=y\nCONFIG_NET_VENDOR_AMD=y\nCONFIG_NET_VENDOR_AQUANTIA=y\nCONFIG_NET_VENDOR_ARC=y\nCONFIG_NET_VENDOR_ATHEROS=y\nCONFIG_NET_VENDOR_AURORA=y\nCONFIG_NET_VENDOR_BROADCOM=y\nCONFIG_NET_VENDOR_BROCADE=y\nCONFIG_NET_VENDOR_CADENCE=y\nCONFIG_NET_VENDOR_CAVIUM=y\nCONFIG_NET_VENDOR_CHELSIO=y\nCONFIG_NET_VENDOR_CIRRUS=y\nCONFIG_NET_VENDOR_CISCO=y\nCONFIG_NET_VENDOR_CORTINA=y\nCONFIG_NET_VENDOR_DEC=y\nCONFIG_NET_VENDOR_DLINK=y\nCONFIG_NET_VENDOR_EMULEX=y\nCONFIG_NET_VENDOR_EXAR=y\nCONFIG_NET_VENDOR_EZCHIP=y\nCONFIG_NET_VENDOR_FARADAY=y\nCONFIG_NET_VENDOR_FREESCALE=y\nCONFIG_NET_VENDOR_FUJITSU=y\nCONFIG_NET_VENDOR_GOOGLE=y\nCONFIG_NET_VENDOR_HISILICON=y\nCONFIG_NET_VENDOR_HP=y\nCONFIG_NET_VENDOR_HUAWEI=y\nCONFIG_NET_VENDOR_I825XX=y\nCONFIG_NET_VENDOR_IBM=y\nCONFIG_NET_VENDOR_INTEL=y\nCONFIG_NET_VENDOR_MARVELL=y\nCONFIG_NET_VENDOR_MELLANOX=y\nCONFIG_NET_VENDOR_MICREL=y\nCONFIG_NET_VENDOR_MICROCHIP=y\nCONFIG_NET_VENDOR_MICROSEMI=y\nCONFIG_NET_VENDOR_MYRI=y\nCONFIG_NET_VENDOR_NATSEMI=y\nCONFIG_NET_VENDOR_NETERION=y\nCONFIG_NET_VENDOR_NETRONOME=y\nCONFIG_NET_VENDOR_NI=y\nCONFIG_NET_VENDOR_NVIDIA=y\nCONFIG_NET_VENDOR_OKI=y\nCONFIG_NET_VENDOR_PACKET_ENGINES=y\nCONFIG_NET_VENDOR_PENSANDO=y\nCONFIG_NET_VENDOR_QLOGIC=y\nCONFIG_NET_VENDOR_QUALCOMM=y\nCONFIG_NET_VENDOR_RDC=y\nCONFIG_NET_VENDOR_REALTEK=y\nCONFIG_NET_VENDOR_RENESAS=y\nCONFIG_NET_VENDOR_ROCKER=y\nCONFIG_NET_VENDOR_SAMSUNG=y\nCONFIG_NET_VENDOR_SEEQ=y\nCONFIG_NET_VENDOR_SILAN=y\nCONFIG_NET_VENDOR_SIS=y\nCONFIG_NET_VENDOR_SMSC=y\nCONFIG_NET_VENDOR_SOCIONEXT=y\nCONFIG_NET_VENDOR_SOLARFLARE=y\nCONFIG_NET_VENDOR_STMICRO=y\nCONFIG_NET_VENDOR_SUN=y\nCONFIG_NET_VENDOR_SYNOPSYS=y\nCONFIG_NET_VENDOR_TEHUTI=y\nCONFIG_NET_VENDOR_TI=y\nCONFIG_NET_VENDOR_TOSHIBA=y\nCONFIG_NET_VENDOR_VIA=y\nCONFIG_NET_VENDOR_WIZNET=y\nCONFIG_NET_VENDOR_XILINX=y\nCONFIG_NET_VENDOR_XIRCOM=y\n# CONFIG_NET_VRF is not set\n# CONFIG_NET_XGENE is not set\nCONFIG_NEW_LEDS=y\n# CONFIG_NFC is not set\n# CONFIG_NFP is not set\n# CONFIG_NFSD is not set\n# CONFIG_NFSD_V2_ACL is not set\nCONFIG_NFSD_V3=y\n# CONFIG_NFSD_V3_ACL is not set\n# CONFIG_NFSD_V4 is not set\n# CONFIG_NFS_ACL_SUPPORT is not set\nCONFIG_NFS_COMMON=y\n# CONFIG_NFS_DISABLE_UDP_SUPPORT is not set\n# CONFIG_NFS_FS is not set\n# CONFIG_NFS_FSCACHE is not set\n# CONFIG_NFS_SWAP is not set\n# CONFIG_NFS_V2 is not set\nCONFIG_NFS_V3=y\n# CONFIG_NFS_V3_ACL is not set\n# CONFIG_NFS_V4 is not set\n# CONFIG_NFS_V4_1 is not set\n# CONFIG_NFTL is not set\n# CONFIG_NFT_BRIDGE_META is not set\n# CONFIG_NFT_BRIDGE_REJECT is not set\n# CONFIG_NFT_CONNLIMIT is not set\n# CONFIG_NFT_DUP_IPV4 is not set\n# CONFIG_NFT_DUP_IPV6 is not set\n# CONFIG_NFT_FIB_IPV4 is not set\n# CONFIG_NFT_FIB_IPV6 is not set\n# CONFIG_NFT_FIB_NETDEV is not set\n# CONFIG_NFT_FLOW_OFFLOAD is not set\n# CONFIG_NFT_OBJREF is not set\n# CONFIG_NFT_OSF is not set\n# CONFIG_NFT_RT is not set\n# CONFIG_NFT_SET_BITMAP is not set\n# CONFIG_NFT_SOCKET is not set\n# CONFIG_NFT_SYNPROXY is not set\n# CONFIG_NFT_TPROXY is not set\n# CONFIG_NFT_TUNNEL is not set\n# CONFIG_NFT_XFRM is not set\n# CONFIG_NF_CONNTRACK is not set\n# CONFIG_NF_CONNTRACK_AMANDA is not set\n# CONFIG_NF_CONNTRACK_BRIDGE is not set\n# CONFIG_NF_CONNTRACK_EVENTS is not set\n# CONFIG_NF_CONNTRACK_FTP is not set\n# CONFIG_NF_CONNTRACK_H323 is not set\n# CONFIG_NF_CONNTRACK_IRC is not set\n# CONFIG_NF_CONNTRACK_LABELS is not set\n# CONFIG_NF_CONNTRACK_MARK is not set\n# CONFIG_NF_CONNTRACK_NETBIOS_NS is not set\n# CONFIG_NF_CONNTRACK_PPTP is not set\nCONFIG_NF_CONNTRACK_PROCFS=y\n# CONFIG_NF_CONNTRACK_PROC_COMPAT is not set\n# CONFIG_NF_CONNTRACK_SANE is not set\n# CONFIG_NF_CONNTRACK_SECMARK is not set\n# CONFIG_NF_CONNTRACK_SIP is not set\n# CONFIG_NF_CONNTRACK_SNMP is not set\n# CONFIG_NF_CONNTRACK_TFTP is not set\n# CONFIG_NF_CONNTRACK_TIMEOUT is not set\n# CONFIG_NF_CONNTRACK_TIMESTAMP is not set\n# CONFIG_NF_CONNTRACK_ZONES is not set\n# CONFIG_NF_CT_NETLINK is not set\n# CONFIG_NF_CT_NETLINK_HELPER is not set\n# CONFIG_NF_CT_NETLINK_TIMEOUT is not set\n# CONFIG_NF_CT_PROTO_DCCP is not set\n# CONFIG_NF_CT_PROTO_GRE is not set\n# CONFIG_NF_CT_PROTO_SCTP is not set\n# CONFIG_NF_CT_PROTO_UDPLITE is not set\n# CONFIG_NF_DEFRAG_IPV4 is not set\n# CONFIG_NF_DUP_IPV4 is not set\n# CONFIG_NF_DUP_IPV6 is not set\n# CONFIG_NF_FLOW_TABLE is not set\n# CONFIG_NF_LOG_ARP is not set\n# CONFIG_NF_LOG_BRIDGE is not set\n# CONFIG_NF_LOG_IPV4 is not set\n# CONFIG_NF_LOG_NETDEV is not set\n# CONFIG_NF_NAT is not set\n# CONFIG_NF_NAT_AMANDA is not set\n# CONFIG_NF_NAT_FTP is not set\n# CONFIG_NF_NAT_H323 is not set\n# CONFIG_NF_NAT_IPV6 is not set\n# CONFIG_NF_NAT_IRC is not set\nCONFIG_NF_NAT_MASQUERADE_IPV4=y\nCONFIG_NF_NAT_MASQUERADE_IPV6=y\n# CONFIG_NF_NAT_NEEDED is not set\n# CONFIG_NF_NAT_PPTP is not set\n# CONFIG_NF_NAT_PROTO_GRE is not set\n# CONFIG_NF_NAT_SIP is not set\n# CONFIG_NF_NAT_SNMP_BASIC is not set\n# CONFIG_NF_NAT_TFTP is not set\n# CONFIG_NF_REJECT_IPV4 is not set\n# CONFIG_NF_REJECT_IPV6 is not set\n# CONFIG_NF_SOCKET_IPV4 is not set\n# CONFIG_NF_SOCKET_IPV6 is not set\n# CONFIG_NF_TABLES is not set\nCONFIG_NF_TABLES_ARP=y\nCONFIG_NF_TABLES_BRIDGE=y\nCONFIG_NF_TABLES_INET=y\nCONFIG_NF_TABLES_IPV4=y\nCONFIG_NF_TABLES_IPV6=y\nCONFIG_NF_TABLES_NETDEV=y\n# CONFIG_NF_TABLES_SET is not set\n# CONFIG_NF_TPROXY_IPV4 is not set\n# CONFIG_NF_TPROXY_IPV6 is not set\n# CONFIG_NI65 is not set\n# CONFIG_NI903X_WDT is not set\n# CONFIG_NIC7018_WDT is not set\n# CONFIG_NILFS2_FS is not set\n# CONFIG_NIU is not set\n# CONFIG_NI_XGE_MANAGEMENT_ENET is not set\nCONFIG_NLATTR=y\n# CONFIG_NLMON is not set\n# CONFIG_NLM_XLP_BOARD is not set\n# CONFIG_NLM_XLR_BOARD is not set\n# CONFIG_NLS is not set\n# CONFIG_NLS_ASCII is not set\n# CONFIG_NLS_CODEPAGE_1250 is not set\n# CONFIG_NLS_CODEPAGE_1251 is not set\n# CONFIG_NLS_CODEPAGE_437 is not set\n# CONFIG_NLS_CODEPAGE_737 is not set\n# CONFIG_NLS_CODEPAGE_775 is not set\n# CONFIG_NLS_CODEPAGE_850 is not set\n# CONFIG_NLS_CODEPAGE_852 is not set\n# CONFIG_NLS_CODEPAGE_855 is not set\n# CONFIG_NLS_CODEPAGE_857 is not set\n# CONFIG_NLS_CODEPAGE_860 is not set\n# CONFIG_NLS_CODEPAGE_861 is not set\n# CONFIG_NLS_CODEPAGE_862 is not set\n# CONFIG_NLS_CODEPAGE_863 is not set\n# CONFIG_NLS_CODEPAGE_864 is not set\n# CONFIG_NLS_CODEPAGE_865 is not set\n# CONFIG_NLS_CODEPAGE_866 is not set\n# CONFIG_NLS_CODEPAGE_869 is not set\n# CONFIG_NLS_CODEPAGE_874 is not set\n# CONFIG_NLS_CODEPAGE_932 is not set\n# CONFIG_NLS_CODEPAGE_936 is not set\n# CONFIG_NLS_CODEPAGE_949 is not set\n# CONFIG_NLS_CODEPAGE_950 is not set\nCONFIG_NLS_DEFAULT=\"iso8859-1\"\n# CONFIG_NLS_ISO8859_1 is not set\n# CONFIG_NLS_ISO8859_13 is not set\n# CONFIG_NLS_ISO8859_14 is not set\n# CONFIG_NLS_ISO8859_15 is not set\n# CONFIG_NLS_ISO8859_2 is not set\n# CONFIG_NLS_ISO8859_3 is not set\n# CONFIG_NLS_ISO8859_4 is not set\n# CONFIG_NLS_ISO8859_5 is not set\n# CONFIG_NLS_ISO8859_6 is not set\n# CONFIG_NLS_ISO8859_7 is not set\n# CONFIG_NLS_ISO8859_8 is not set\n# CONFIG_NLS_ISO8859_9 is not set\n# CONFIG_NLS_KOI8_R is not set\n# CONFIG_NLS_KOI8_U is not set\n# CONFIG_NLS_MAC_CELTIC is not set\n# CONFIG_NLS_MAC_CENTEURO is not set\n# CONFIG_NLS_MAC_CROATIAN is not set\n# CONFIG_NLS_MAC_CYRILLIC is not set\n# CONFIG_NLS_MAC_GAELIC is not set\n# CONFIG_NLS_MAC_GREEK is not set\n# CONFIG_NLS_MAC_ICELAND is not set\n# CONFIG_NLS_MAC_INUIT is not set\n# CONFIG_NLS_MAC_ROMAN is not set\n# CONFIG_NLS_MAC_ROMANIAN is not set\n# CONFIG_NLS_MAC_TURKISH is not set\n# CONFIG_NLS_UTF8 is not set\nCONFIG_NMI_LOG_BUF_SHIFT=13\n# CONFIG_NOA1305 is not set\n# CONFIG_NOP_USB_XCEIV is not set\n# CONFIG_NORTEL_HERMES is not set\n# CONFIG_NOTIFIER_ERROR_INJECTION is not set\n# CONFIG_NOUVEAU_LEGACY_CTX_SUPPORT is not set\n# CONFIG_NOZOMI is not set\n# CONFIG_NO_BOOTMEM is not set\n# CONFIG_NO_HZ is not set\n# CONFIG_NO_HZ_FULL is not set\n# CONFIG_NO_HZ_IDLE is not set\n# CONFIG_NS83820 is not set\n# CONFIG_NTB is not set\n# CONFIG_NTFS_DEBUG is not set\n# CONFIG_NTFS_FS is not set\n# CONFIG_NTFS_RW is not set\n# CONFIG_NTP_PPS is not set\n# CONFIG_NULL_TTY is not set\n# CONFIG_NUMA is not set\n# CONFIG_NVM is not set\n# CONFIG_NVMEM is not set\n# CONFIG_NVMEM_BCM_OCOTP is not set\n# CONFIG_NVMEM_IMX_OCOTP is not set\n# CONFIG_NVMEM_REBOOT_MODE is not set\n# CONFIG_NVMEM_SYSFS is not set\n# CONFIG_NVME_FC is not set\n# CONFIG_NVME_TARGET is not set\n# CONFIG_NVME_TCP is not set\n# CONFIG_NVRAM is not set\n# CONFIG_NV_TCO is not set\n# CONFIG_NXP_STB220 is not set\n# CONFIG_NXP_STB225 is not set\n# CONFIG_NXP_TJA11XX_PHY is not set\n# CONFIG_N_GSM is not set\n# CONFIG_OABI_COMPAT is not set\n# CONFIG_OBS600 is not set\n# CONFIG_OCFS2_FS is not set\n# CONFIG_OCTEONTX2_AF is not set\n# CONFIG_OCTEONTX2_PF is not set\n# CONFIG_OF_OVERLAY is not set\nCONFIG_OF_RESERVED_MEM=y\n# CONFIG_OF_UNITTEST is not set\n# CONFIG_OID_REGISTRY is not set\n# CONFIG_OMAP2_DSS_DEBUG is not set\n# CONFIG_OMAP2_DSS_DEBUGFS is not set\n# CONFIG_OMAP2_DSS_SDI is not set\n# CONFIG_OMAP_OCP2SCP is not set\n# CONFIG_OMAP_USB2 is not set\n# CONFIG_OMFS_FS is not set\n# CONFIG_OPENVSWITCH is not set\n# CONFIG_OPROFILE is not set\n# CONFIG_OPROFILE_EVENT_MULTIPLEX is not set\n# CONFIG_OPT3001 is not set\nCONFIG_OPTIMIZE_INLINING=y\n# CONFIG_ORANGEFS_FS is not set\n# CONFIG_ORION_WATCHDOG is not set\n# CONFIG_OSF_PARTITION is not set\nCONFIG_OVERLAY_FS=y\n# CONFIG_OVERLAY_FS_INDEX is not set\n# CONFIG_OVERLAY_FS_METACOPY is not set\nCONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y\n# CONFIG_OVERLAY_FS_REDIRECT_DIR is not set\nCONFIG_OVERLAY_FS_XINO_AUTO=y\n# CONFIG_OWL_LOADER is not set\n# CONFIG_P54_COMMON is not set\n# CONFIG_PA12203001 is not set\nCONFIG_PACKET=y\n# CONFIG_PACKET_DIAG is not set\n# CONFIG_PACKING is not set\n# CONFIG_PAGE_EXTENSION is not set\n# CONFIG_PAGE_OWNER is not set\n# CONFIG_PAGE_POISONING is not set\n# CONFIG_PAGE_REPORTING is not set\n# CONFIG_PAGE_SIZE_16KB is not set\n# CONFIG_PAGE_SIZE_32KB is not set\nCONFIG_PAGE_SIZE_4KB=y\n# CONFIG_PAGE_SIZE_64KB is not set\n# CONFIG_PAGE_SIZE_8KB is not set\n# CONFIG_PALMAS_GPADC is not set\n# CONFIG_PANASONIC_LAPTOP is not set\n# CONFIG_PANEL is not set\nCONFIG_PANIC_ON_OOPS=y\nCONFIG_PANIC_ON_OOPS_VALUE=1\nCONFIG_PANIC_TIMEOUT=1\n# CONFIG_PANTHERLORD_FF is not set\n# CONFIG_PARAVIRT is not set\n# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set\n# CONFIG_PARPORT is not set\n# CONFIG_PARPORT_1284 is not set\n# CONFIG_PARPORT_AX88796 is not set\n# CONFIG_PARPORT_GSC is not set\n# CONFIG_PARPORT_PC is not set\nCONFIG_PARTITION_ADVANCED=y\n# CONFIG_PATA_ALI is not set\n# CONFIG_PATA_AMD is not set\n# CONFIG_PATA_ARASAN_CF is not set\n# CONFIG_PATA_ARTOP is not set\n# CONFIG_PATA_ATIIXP is not set\n# CONFIG_PATA_ATP867X is not set\n# CONFIG_PATA_CMD640_PCI is not set\n# CONFIG_PATA_CMD64X is not set\n# CONFIG_PATA_CS5520 is not set\n# CONFIG_PATA_CS5530 is not set\n# CONFIG_PATA_CS5535 is not set\n# CONFIG_PATA_CS5536 is not set\n# CONFIG_PATA_CYPRESS is not set\n# CONFIG_PATA_EFAR is not set\n# CONFIG_PATA_HPT366 is not set\n# CONFIG_PATA_HPT37X is not set\n# CONFIG_PATA_HPT3X2N is not set\n# CONFIG_PATA_HPT3X3 is not set\n# CONFIG_PATA_IMX is not set\n# CONFIG_PATA_ISAPNP is not set\n# CONFIG_PATA_IT8213 is not set\n# CONFIG_PATA_IT821X is not set\n# CONFIG_PATA_JMICRON is not set\n# CONFIG_PATA_LEGACY is not set\n# CONFIG_PATA_MARVELL is not set\n# CONFIG_PATA_MPIIX is not set\n# CONFIG_PATA_NETCELL is not set\n# CONFIG_PATA_NINJA32 is not set\n# CONFIG_PATA_NS87410 is not set\n# CONFIG_PATA_NS87415 is not set\n# CONFIG_PATA_OCTEON_CF is not set\n# CONFIG_PATA_OF_PLATFORM is not set\n# CONFIG_PATA_OLDPIIX is not set\n# CONFIG_PATA_OPTI is not set\n# CONFIG_PATA_OPTIDMA is not set\n# CONFIG_PATA_PCMCIA is not set\n# CONFIG_PATA_PDC2027X is not set\n# CONFIG_PATA_PDC_OLD is not set\n# CONFIG_PATA_PLATFORM is not set\n# CONFIG_PATA_QDI is not set\n# CONFIG_PATA_RADISYS is not set\n# CONFIG_PATA_RDC is not set\n# CONFIG_PATA_RZ1000 is not set\n# CONFIG_PATA_SC1200 is not set\n# CONFIG_PATA_SCH is not set\n# CONFIG_PATA_SERVERWORKS is not set\n# CONFIG_PATA_SIL680 is not set\n# CONFIG_PATA_SIS is not set\n# CONFIG_PATA_TOSHIBA is not set\n# CONFIG_PATA_TRIFLEX is not set\n# CONFIG_PATA_VIA is not set\n# CONFIG_PATA_WINBOND is not set\n# CONFIG_PATA_WINBOND_VLB is not set\n# CONFIG_PC104 is not set\n# CONFIG_PC300TOO is not set\n# CONFIG_PCCARD is not set\n# CONFIG_PCH_DMA is not set\n# CONFIG_PCH_GBE is not set\n# CONFIG_PCH_PHUB is not set\n# CONFIG_PCI is not set\n# CONFIG_PCI200SYN is not set\n# CONFIG_PCIEAER is not set\n# CONFIG_PCIEAER_INJECT is not set\n# CONFIG_PCIEASPM is not set\n# CONFIG_PCIEPORTBUS is not set\n# CONFIG_PCIE_AL is not set\n# CONFIG_PCIE_ALTERA is not set\n# CONFIG_PCIE_ARMADA_8K is not set\nCONFIG_PCIE_BUS_DEFAULT=y\n# CONFIG_PCIE_BUS_PEER2PEER is not set\n# CONFIG_PCIE_BUS_PERFORMANCE is not set\n# CONFIG_PCIE_BUS_SAFE is not set\n# CONFIG_PCIE_BUS_TUNE_OFF is not set\n# CONFIG_PCIE_BW is not set\n# CONFIG_PCIE_CADENCE_HOST is not set\n# CONFIG_PCIE_CADENCE_PLAT_HOST is not set\n# CONFIG_PCIE_DPC is not set\n# CONFIG_PCIE_DW_PLAT is not set\n# CONFIG_PCIE_DW_PLAT_HOST is not set\n# CONFIG_PCIE_ECRC is not set\n# CONFIG_PCIE_IPROC is not set\n# CONFIG_PCIE_KIRIN is not set\n# CONFIG_PCIE_LAYERSCAPE_GEN4 is not set\n# CONFIG_PCIE_PTM is not set\n# CONFIG_PCIE_XILINX is not set\n# CONFIG_PCIPCWATCHDOG is not set\n# CONFIG_PCI_ATMEL is not set\n# CONFIG_PCI_CNB20LE_QUIRK is not set\n# CONFIG_PCI_DEBUG is not set\n# CONFIG_PCI_DISABLE_COMMON_QUIRKS is not set\n# CONFIG_PCI_ENDPOINT is not set\n# CONFIG_PCI_ENDPOINT_TEST is not set\n# CONFIG_PCI_FTPCI100 is not set\n# CONFIG_PCI_HERMES is not set\n# CONFIG_PCI_HISI is not set\n# CONFIG_PCI_HOST_GENERIC is not set\n# CONFIG_PCI_HOST_THUNDER_ECAM is not set\n# CONFIG_PCI_HOST_THUNDER_PEM is not set\n# CONFIG_PCI_IOV is not set\n# CONFIG_PCI_J721E_HOST is not set\n# CONFIG_PCI_LAYERSCAPE is not set\n# CONFIG_PCI_MESON is not set\n# CONFIG_PCI_MSI is not set\n# CONFIG_PCI_PASID is not set\n# CONFIG_PCI_PF_STUB is not set\n# CONFIG_PCI_PRI is not set\nCONFIG_PCI_QUIRKS=y\n# CONFIG_PCI_REALLOC_ENABLE_AUTO is not set\n# CONFIG_PCI_STUB is not set\n# CONFIG_PCI_SW_SWITCHTEC is not set\nCONFIG_PCI_SYSCALL=y\n# CONFIG_PCI_V3_SEMI is not set\n# CONFIG_PCI_XGENE is not set\n# CONFIG_PCMCIA is not set\n# CONFIG_PCMCIA_3C574 is not set\n# CONFIG_PCMCIA_3C589 is not set\n# CONFIG_PCMCIA_AHA152X is not set\n# CONFIG_PCMCIA_ATMEL is not set\n# CONFIG_PCMCIA_AXNET is not set\n# CONFIG_PCMCIA_DEBUG is not set\n# CONFIG_PCMCIA_FDOMAIN is not set\n# CONFIG_PCMCIA_FMVJ18X is not set\n# CONFIG_PCMCIA_HERMES is not set\n# CONFIG_PCMCIA_LOAD_CIS is not set\n# CONFIG_PCMCIA_NINJA_SCSI is not set\n# CONFIG_PCMCIA_NMCLAN is not set\n# CONFIG_PCMCIA_PCNET is not set\n# CONFIG_PCMCIA_QLOGIC is not set\n# CONFIG_PCMCIA_RAYCS is not set\n# CONFIG_PCMCIA_SMC91C92 is not set\n# CONFIG_PCMCIA_SPECTRUM is not set\n# CONFIG_PCMCIA_SYM53C500 is not set\n# CONFIG_PCMCIA_WL3501 is not set\n# CONFIG_PCMCIA_XIRC2PS is not set\n# CONFIG_PCMCIA_XIRCOM is not set\n# CONFIG_PCNET32 is not set\n# CONFIG_PCSPKR_PLATFORM is not set\n# CONFIG_PCS_XPCS is not set\n# CONFIG_PD6729 is not set\n# CONFIG_PDA_POWER is not set\n# CONFIG_PDC_ADMA is not set\n# CONFIG_PERCPU_STATS is not set\n# CONFIG_PERCPU_TEST is not set\n# CONFIG_PERF_EVENTS is not set\n# CONFIG_PERF_EVENTS_AMD_POWER is not set\n# CONFIG_PERSISTENT_KEYRINGS is not set\n# CONFIG_PHANTOM is not set\n# CONFIG_PHONET is not set\n# CONFIG_PHYLIB is not set\n# CONFIG_PHYS_ADDR_T_64BIT is not set\n# CONFIG_PHY_CADENCE_DP is not set\n# CONFIG_PHY_CADENCE_DPHY is not set\n# CONFIG_PHY_CADENCE_SALVO is not set\n# CONFIG_PHY_CADENCE_SIERRA is not set\n# CONFIG_PHY_CADENCE_TORRENT is not set\n# CONFIG_PHY_CPCAP_USB is not set\n# CONFIG_PHY_EXYNOS_DP_VIDEO is not set\n# CONFIG_PHY_EXYNOS_MIPI_VIDEO is not set\n# CONFIG_PHY_FSL_IMX8MQ_USB is not set\n# CONFIG_PHY_INTEL_KEEMBAY_EMMC is not set\n# CONFIG_PHY_MAPPHONE_MDM6600 is not set\n# CONFIG_PHY_MIXEL_MIPI_DPHY is not set\n# CONFIG_PHY_MTK_HDMI is not set\n# CONFIG_PHY_OCELOT_SERDES is not set\n# CONFIG_PHY_PXA_28NM_HSIC is not set\n# CONFIG_PHY_PXA_28NM_USB2 is not set\n# CONFIG_PHY_QCOM_DWC3 is not set\n# CONFIG_PHY_QCOM_USB_HS is not set\n# CONFIG_PHY_QCOM_USB_HSIC is not set\n# CONFIG_PHY_SAMSUNG_USB2 is not set\n# CONFIG_PHY_TUSB1210 is not set\n# CONFIG_PHY_XGENE is not set\n# CONFIG_PI433 is not set\n# CONFIG_PID_IN_CONTEXTIDR is not set\n# CONFIG_PID_NS is not set\nCONFIG_PINCONF=y\n# CONFIG_PINCTRL is not set\n# CONFIG_PINCTRL_AMD is not set\n# CONFIG_PINCTRL_AXP209 is not set\n# CONFIG_PINCTRL_CEDARFORK is not set\n# CONFIG_PINCTRL_EXYNOS is not set\n# CONFIG_PINCTRL_EXYNOS5440 is not set\n# CONFIG_PINCTRL_ICELAKE is not set\n# CONFIG_PINCTRL_INGENIC is not set\n# CONFIG_PINCTRL_MCP23S08 is not set\n# CONFIG_PINCTRL_MSM8X74 is not set\n# CONFIG_PINCTRL_MT6779 is not set\n# CONFIG_PINCTRL_MT8167 is not set\n# CONFIG_PINCTRL_MT8192 is not set\n# CONFIG_PINCTRL_MTK_V2 is not set\n# CONFIG_PINCTRL_OCELOT is not set\nCONFIG_PINCTRL_SINGLE=y\n# CONFIG_PINCTRL_STMFX is not set\n# CONFIG_PINCTRL_SX150X is not set\n# CONFIG_PING is not set\nCONFIG_PINMUX=y\n# CONFIG_PKCS7_MESSAGE_PARSER is not set\n# CONFIG_PL310_ERRATA_588369 is not set\n# CONFIG_PL310_ERRATA_727915 is not set\n# CONFIG_PL310_ERRATA_753970 is not set\n# CONFIG_PL310_ERRATA_769419 is not set\n# CONFIG_PL320_MBOX is not set\n# CONFIG_PL330_DMA is not set\n# CONFIG_PLATFORM_MHU is not set\n# CONFIG_PLAT_SPEAR is not set\n# CONFIG_PLIP is not set\n# CONFIG_PLX_DMA is not set\n# CONFIG_PLX_HERMES is not set\n# CONFIG_PM is not set\n# CONFIG_PMBUS is not set\n# CONFIG_PMC_MSP is not set\n# CONFIG_PMIC_ADP5520 is not set\n# CONFIG_PMIC_DA903X is not set\n# CONFIG_PMS7003 is not set\n# CONFIG_PM_AUTOSLEEP is not set\n# CONFIG_PM_DEBUG is not set\n# CONFIG_PM_DEVFREQ is not set\n# CONFIG_PM_WAKELOCKS is not set\n# CONFIG_POSIX_MQUEUE is not set\nCONFIG_POSIX_TIMERS=y\n# CONFIG_POWERCAP is not set\n# CONFIG_POWER_AVS is not set\n# CONFIG_POWER_RESET is not set\n# CONFIG_POWER_RESET_BRCMKONA is not set\n# CONFIG_POWER_RESET_BRCMSTB is not set\n# CONFIG_POWER_RESET_GPIO is not set\n# CONFIG_POWER_RESET_GPIO_RESTART is not set\n# CONFIG_POWER_RESET_LINKSTATION is not set\n# CONFIG_POWER_RESET_LTC2952 is not set\n# CONFIG_POWER_RESET_PIIX4_POWEROFF is not set\n# CONFIG_POWER_RESET_QNAP is not set\n# CONFIG_POWER_RESET_RESTART is not set\n# CONFIG_POWER_RESET_SYSCON is not set\n# CONFIG_POWER_RESET_SYSCON_POWEROFF is not set\n# CONFIG_POWER_RESET_VERSATILE is not set\n# CONFIG_POWER_RESET_XGENE is not set\n# CONFIG_POWER_SUPPLY is not set\n# CONFIG_POWER_SUPPLY_DEBUG is not set\n# CONFIG_POWER_SUPPLY_HWMON is not set\n# CONFIG_PPC4xx_GPIO is not set\n# CONFIG_PPC_16K_PAGES is not set\n# CONFIG_PPC_256K_PAGES is not set\nCONFIG_PPC_4K_PAGES=y\n# CONFIG_PPC_64K_PAGES is not set\n# CONFIG_PPC_DISABLE_WERROR is not set\n# CONFIG_PPC_EMULATED_STATS is not set\n# CONFIG_PPC_EPAPR_HV_BYTECHAN is not set\n# CONFIG_PPC_QUEUED_SPINLOCKS is not set\n# CONFIG_PPP is not set\n# CONFIG_PPPOATM is not set\n# CONFIG_PPPOE is not set\n# CONFIG_PPPOL2TP is not set\n# CONFIG_PPP_ASYNC is not set\n# CONFIG_PPP_BSDCOMP is not set\n# CONFIG_PPP_DEFLATE is not set\nCONFIG_PPP_FILTER=y\n# CONFIG_PPP_MPPE is not set\nCONFIG_PPP_MULTILINK=y\n# CONFIG_PPP_SYNC_TTY is not set\n# CONFIG_PPS is not set\n# CONFIG_PPS_CLIENT_GPIO is not set\n# CONFIG_PPS_CLIENT_KTIMER is not set\n# CONFIG_PPS_CLIENT_LDISC is not set\n# CONFIG_PPS_CLIENT_PARPORT is not set\n# CONFIG_PPS_DEBUG is not set\n# CONFIG_PPTP is not set\n# CONFIG_PREEMPT is not set\n# CONFIG_PREEMPTIRQ_DELAY_TEST is not set\n# CONFIG_PREEMPTIRQ_EVENTS is not set\nCONFIG_PREEMPT_NONE=y\n# CONFIG_PREEMPT_TRACER is not set\n# CONFIG_PREEMPT_VOLUNTARY is not set\n# CONFIG_PRESTERA is not set\nCONFIG_PREVENT_FIRMWARE_BUILD=y\n# CONFIG_PRIME_NUMBERS is not set\nCONFIG_PRINTK=y\n# CONFIG_PRINTK_CALLER is not set\nCONFIG_PRINTK_NMI=y\nCONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13\n# CONFIG_PRINTK_TIME is not set\nCONFIG_PRINT_STACK_DEPTH=64\n# CONFIG_PRISM2_USB is not set\n# CONFIG_PRISM54 is not set\n# CONFIG_PROC_CHILDREN is not set\nCONFIG_PROC_FS=y\n# CONFIG_PROC_KCORE is not set\n# CONFIG_PROC_PAGE_MONITOR is not set\n# CONFIG_PROC_STRIPPED is not set\nCONFIG_PROC_SYSCTL=y\n# CONFIG_PROC_VMCORE_DEVICE_DUMP is not set\n# CONFIG_PROFILE_ALL_BRANCHES is not set\n# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set\n# CONFIG_PROFILING is not set\n# CONFIG_PROVE_LOCKING is not set\n# CONFIG_PROVE_RAW_LOCK_NESTING is not set\n# CONFIG_PROVE_RCU is not set\n# CONFIG_PROVE_RCU_LIST is not set\n# CONFIG_PROVE_RCU_REPEATEDLY is not set\n# CONFIG_PSAMPLE is not set\n# CONFIG_PSB6970_PHY is not set\n# CONFIG_PSI is not set\n# CONFIG_PSTORE is not set\n# CONFIG_PSTORE_842_COMPRESS is not set\n# CONFIG_PSTORE_COMPRESS is not set\n# CONFIG_PSTORE_COMPRESS_DEFAULT is not set\n# CONFIG_PSTORE_CONSOLE is not set\n# CONFIG_PSTORE_DEFLATE_COMPRESS is not set\n# CONFIG_PSTORE_DEFLATE_COMPRESS_DEFAULT is not set\n# CONFIG_PSTORE_LZ4HC_COMPRESS is not set\n# CONFIG_PSTORE_LZ4_COMPRESS is not set\n# CONFIG_PSTORE_LZO_COMPRESS is not set\n# CONFIG_PSTORE_PMSG is not set\n# CONFIG_PSTORE_RAM is not set\n# CONFIG_PSTORE_ZSTD_COMPRESS is not set\n# CONFIG_PTDUMP_DEBUGFS is not set\n# CONFIG_PTP_1588_CLOCK is not set\n# CONFIG_PTP_1588_CLOCK_IDT82P33 is not set\n# CONFIG_PTP_1588_CLOCK_IDTCM is not set\n# CONFIG_PTP_1588_CLOCK_IXP46X is not set\n# CONFIG_PTP_1588_CLOCK_KVM is not set\n# CONFIG_PTP_1588_CLOCK_PCH is not set\n# CONFIG_PTP_1588_CLOCK_VMW is not set\n# CONFIG_PUBLIC_KEY_ALGO_RSA is not set\n# CONFIG_PVPANIC is not set\n# CONFIG_PWM is not set\n# CONFIG_PWM_DEBUG is not set\n# CONFIG_PWM_FSL_FTM is not set\n# CONFIG_PWM_JZ4740 is not set\n# CONFIG_PWM_PCA9685 is not set\nCONFIG_PWRSEQ_EMMC=y\n# CONFIG_PWRSEQ_SD8787 is not set\nCONFIG_PWRSEQ_SIMPLE=y\n# CONFIG_QCA7000 is not set\n# CONFIG_QCA7000_SPI is not set\n# CONFIG_QCA7000_UART is not set\n# CONFIG_QCOM_EMAC is not set\n# CONFIG_QCOM_FALKOR_ERRATUM_1003 is not set\n# CONFIG_QCOM_FALKOR_ERRATUM_1009 is not set\n# CONFIG_QCOM_FALKOR_ERRATUM_E1041 is not set\n# CONFIG_QCOM_HIDMA is not set\n# CONFIG_QCOM_HIDMA_MGMT is not set\n# CONFIG_QCOM_QDF2400_ERRATUM_0065 is not set\n# CONFIG_QCOM_SPMI_ADC5 is not set\n# CONFIG_QCOM_SPMI_IADC is not set\n# CONFIG_QCOM_SPMI_TEMP_ALARM is not set\n# CONFIG_QCOM_SPMI_VADC is not set\n# CONFIG_QED is not set\n# CONFIG_QLA3XXX is not set\n# CONFIG_QLCNIC is not set\n# CONFIG_QLGE is not set\n# CONFIG_QNX4FS_FS is not set\n# CONFIG_QNX6FS_FS is not set\n# CONFIG_QORIQ_CPUFREQ is not set\n# CONFIG_QORIQ_THERMAL is not set\n# CONFIG_QRTR is not set\n# CONFIG_QSEMI_PHY is not set\n# CONFIG_QUEUED_LOCK_STAT is not set\n# CONFIG_QUICC_ENGINE is not set\n# CONFIG_QUOTA is not set\n# CONFIG_QUOTACTL is not set\n# CONFIG_QUOTA_DEBUG is not set\n# CONFIG_R3964 is not set\n# CONFIG_R6040 is not set\n# CONFIG_R8169 is not set\n# CONFIG_R8188EU is not set\n# CONFIG_R8712U is not set\n# CONFIG_R8723AU is not set\n# CONFIG_RADIO_ADAPTERS is not set\n# CONFIG_RADIO_AZTECH is not set\n# CONFIG_RADIO_CADET is not set\n# CONFIG_RADIO_GEMTEK is not set\n# CONFIG_RADIO_MAXIRADIO is not set\n# CONFIG_RADIO_RTRACK is not set\n# CONFIG_RADIO_RTRACK2 is not set\n# CONFIG_RADIO_SF16FMI is not set\n# CONFIG_RADIO_SF16FMR2 is not set\n# CONFIG_RADIO_TERRATEC is not set\n# CONFIG_RADIO_TRUST is not set\n# CONFIG_RADIO_TYPHOON is not set\n# CONFIG_RADIO_ZOLTRIX is not set\n# CONFIG_RAID6_PQ_BENCHMARK is not set\n# CONFIG_RAID_ATTRS is not set\n# CONFIG_RALINK is not set\n# CONFIG_RANDOM32_SELFTEST is not set\n# CONFIG_RANDOMIZE_BASE is not set\n# CONFIG_RANDOM_TRUST_BOOTLOADER is not set\n# CONFIG_RANDOM_TRUST_CPU is not set\n# CONFIG_RAPIDIO is not set\n# CONFIG_RAS is not set\n# CONFIG_RAW_DRIVER is not set\n# CONFIG_RBTREE_TEST is not set\n# CONFIG_RCU_BOOST is not set\nCONFIG_RCU_CPU_STALL_TIMEOUT=21\n# CONFIG_RCU_EQS_DEBUG is not set\n# CONFIG_RCU_EXPEDITE_BOOT is not set\n# CONFIG_RCU_EXPERT is not set\nCONFIG_RCU_KTHREAD_PRIO=0\nCONFIG_RCU_NEED_SEGCBLIST=y\n# CONFIG_RCU_PERF_TEST is not set\n# CONFIG_RCU_REF_SCALE_TEST is not set\n# CONFIG_RCU_SCALE_TEST is not set\nCONFIG_RCU_STALL_COMMON=y\n# CONFIG_RCU_STRICT_GRACE_PERIOD is not set\n# CONFIG_RCU_TORTURE_TEST is not set\nCONFIG_RCU_TORTURE_TEST_SLOW_INIT_DELAY=3\n# CONFIG_RCU_TRACE is not set\n# CONFIG_RC_ATI_REMOTE is not set\n# CONFIG_RC_CORE is not set\n# CONFIG_RC_DECODERS is not set\n# CONFIG_RC_LOOPBACK is not set\n# CONFIG_RC_MAP is not set\n# CONFIG_RDS is not set\n# CONFIG_RD_BZIP2 is not set\n# CONFIG_RD_GZIP is not set\n# CONFIG_RD_LZ4 is not set\n# CONFIG_RD_LZMA is not set\n# CONFIG_RD_LZO is not set\n# CONFIG_RD_XZ is not set\n# CONFIG_RD_ZSTD is not set\n# CONFIG_READABLE_ASM is not set\n# CONFIG_READ_ONLY_THP_FOR_FS is not set\n# CONFIG_REALTEK_PHY is not set\n# CONFIG_REDWOOD is not set\n# CONFIG_REED_SOLOMON is not set\n# CONFIG_REED_SOLOMON_DEC8 is not set\n# CONFIG_REED_SOLOMON_ENC8 is not set\n# CONFIG_REED_SOLOMON_TEST is not set\n# CONFIG_REGMAP is not set\n# CONFIG_REGMAP_I2C is not set\n# CONFIG_REGMAP_MMIO is not set\n# CONFIG_REGMAP_SPI is not set\n# CONFIG_REGULATOR is not set\n# CONFIG_REGULATOR_88PG86X is not set\n# CONFIG_REGULATOR_ACT8865 is not set\n# CONFIG_REGULATOR_AD5398 is not set\n# CONFIG_REGULATOR_ANATOP is not set\n# CONFIG_REGULATOR_DA9210 is not set\n# CONFIG_REGULATOR_DA9211 is not set\n# CONFIG_REGULATOR_DEBUG is not set\n# CONFIG_REGULATOR_FAN53555 is not set\n# CONFIG_REGULATOR_FAN53880 is not set\n# CONFIG_REGULATOR_FIXED_VOLTAGE is not set\n# CONFIG_REGULATOR_GPIO is not set\n# CONFIG_REGULATOR_ISL6271A is not set\n# CONFIG_REGULATOR_ISL9305 is not set\n# CONFIG_REGULATOR_LP3971 is not set\n# CONFIG_REGULATOR_LP3972 is not set\n# CONFIG_REGULATOR_LP872X is not set\n# CONFIG_REGULATOR_LP8755 is not set\n# CONFIG_REGULATOR_LTC3589 is not set\n# CONFIG_REGULATOR_LTC3676 is not set\n# CONFIG_REGULATOR_MAX1586 is not set\n# CONFIG_REGULATOR_MAX77620 is not set\n# CONFIG_REGULATOR_MAX77826 is not set\n# CONFIG_REGULATOR_MAX8649 is not set\n# CONFIG_REGULATOR_MAX8660 is not set\n# CONFIG_REGULATOR_MAX8952 is not set\n# CONFIG_REGULATOR_MAX8973 is not set\n# CONFIG_REGULATOR_MCP16502 is not set\n# CONFIG_REGULATOR_MP5416 is not set\n# CONFIG_REGULATOR_MP8859 is not set\n# CONFIG_REGULATOR_MP886X is not set\n# CONFIG_REGULATOR_MPQ7920 is not set\n# CONFIG_REGULATOR_MT6311 is not set\n# CONFIG_REGULATOR_PCA9450 is not set\n# CONFIG_REGULATOR_PFUZE100 is not set\n# CONFIG_REGULATOR_PV88060 is not set\n# CONFIG_REGULATOR_PV88080 is not set\n# CONFIG_REGULATOR_PV88090 is not set\n# CONFIG_REGULATOR_PWM is not set\n# CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY is not set\n# CONFIG_REGULATOR_RT4801 is not set\n# CONFIG_REGULATOR_RTMV20 is not set\n# CONFIG_REGULATOR_SLG51000 is not set\n# CONFIG_REGULATOR_SY8106A is not set\n# CONFIG_REGULATOR_SY8824X is not set\n# CONFIG_REGULATOR_SY8827N is not set\n# CONFIG_REGULATOR_TI_ABB is not set\n# CONFIG_REGULATOR_TPS51632 is not set\n# CONFIG_REGULATOR_TPS62360 is not set\n# CONFIG_REGULATOR_TPS65023 is not set\n# CONFIG_REGULATOR_TPS6507X is not set\n# CONFIG_REGULATOR_TPS65132 is not set\n# CONFIG_REGULATOR_TPS6524X is not set\n# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set\n# CONFIG_REGULATOR_VCTRL is not set\n# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set\n# CONFIG_REISERFS_CHECK is not set\n# CONFIG_REISERFS_FS is not set\n# CONFIG_REISERFS_FS_POSIX_ACL is not set\n# CONFIG_REISERFS_FS_SECURITY is not set\nCONFIG_REISERFS_FS_XATTR=y\n# CONFIG_REISERFS_PROC_INFO is not set\n# CONFIG_RELAY is not set\n# CONFIG_RELOCATABLE is not set\n# CONFIG_REMOTEPROC is not set\n# CONFIG_RENESAS_PHY is not set\n# CONFIG_RESET_ATH79 is not set\n# CONFIG_RESET_BERLIN is not set\n# CONFIG_RESET_BRCMSTB_RESCAL is not set\n# CONFIG_RESET_CONTROLLER is not set\n# CONFIG_RESET_IMX7 is not set\n# CONFIG_RESET_INTEL_GW is not set\n# CONFIG_RESET_LANTIQ is not set\n# CONFIG_RESET_LPC18XX is not set\n# CONFIG_RESET_MESON is not set\n# CONFIG_RESET_PISTACHIO is not set\n# CONFIG_RESET_SOCFPGA is not set\n# CONFIG_RESET_STM32 is not set\n# CONFIG_RESET_SUNXI is not set\n# CONFIG_RESET_TEGRA_BPMP is not set\n# CONFIG_RESET_TI_SYSCON is not set\n# CONFIG_RESET_ZYNQ is not set\n# CONFIG_RFD77402 is not set\n# CONFIG_RFD_FTL is not set\nCONFIG_RFKILL=y\n# CONFIG_RFKILL_FULL is not set\n# CONFIG_RFKILL_GPIO is not set\n# CONFIG_RFKILL_INPUT is not set\n# CONFIG_RFKILL_LEDS is not set\n# CONFIG_RFKILL_REGULATOR is not set\n# CONFIG_RING_BUFFER_BENCHMARK is not set\n# CONFIG_RING_BUFFER_STARTUP_TEST is not set\n# CONFIG_RMI4_CORE is not set\n# CONFIG_RMNET is not set\n# CONFIG_ROCKCHIP_PHY is not set\n# CONFIG_ROCKER is not set\n# CONFIG_ROMFS_FS is not set\n# CONFIG_ROSE is not set\n# CONFIG_RPCSEC_GSS_KRB5 is not set\n# CONFIG_RPMSG_QCOM_GLINK_RPM is not set\n# CONFIG_RPMSG_VIRTIO is not set\n# CONFIG_RPR0521 is not set\n# CONFIG_RSEQ is not set\n# CONFIG_RT2X00 is not set\n# CONFIG_RTC_CLASS is not set\n# CONFIG_RTC_DEBUG is not set\n# CONFIG_RTC_DRV_ABB5ZES3 is not set\n# CONFIG_RTC_DRV_ABEOZ9 is not set\n# CONFIG_RTC_DRV_ABX80X is not set\n# CONFIG_RTC_DRV_ARMADA38X is not set\n# CONFIG_RTC_DRV_AU1XXX is not set\n# CONFIG_RTC_DRV_BQ32K is not set\n# CONFIG_RTC_DRV_BQ4802 is not set\n# CONFIG_RTC_DRV_CADENCE is not set\nCONFIG_RTC_DRV_CMOS=y\n# CONFIG_RTC_DRV_DS1286 is not set\n# CONFIG_RTC_DRV_DS1302 is not set\n# CONFIG_RTC_DRV_DS1305 is not set\n# CONFIG_RTC_DRV_DS1307 is not set\n# CONFIG_RTC_DRV_DS1307_CENTURY is not set\n# CONFIG_RTC_DRV_DS1307_HWMON is not set\n# CONFIG_RTC_DRV_DS1343 is not set\n# CONFIG_RTC_DRV_DS1347 is not set\n# CONFIG_RTC_DRV_DS1374 is not set\n# CONFIG_RTC_DRV_DS1390 is not set\n# CONFIG_RTC_DRV_DS1511 is not set\n# CONFIG_RTC_DRV_DS1553 is not set\n# CONFIG_RTC_DRV_DS1672 is not set\n# CONFIG_RTC_DRV_DS1685_FAMILY is not set\n# CONFIG_RTC_DRV_DS1742 is not set\n# CONFIG_RTC_DRV_DS2404 is not set\n# CONFIG_RTC_DRV_DS3232 is not set\n# CONFIG_RTC_DRV_DS3234 is not set\n# CONFIG_RTC_DRV_EM3027 is not set\n# CONFIG_RTC_DRV_EP93XX is not set\n# CONFIG_RTC_DRV_FM3130 is not set\n# CONFIG_RTC_DRV_FTRTC010 is not set\n# CONFIG_RTC_DRV_GENERIC is not set\n# CONFIG_RTC_DRV_HID_SENSOR_TIME is not set\n# CONFIG_RTC_DRV_HYM8563 is not set\n# CONFIG_RTC_DRV_ISL12022 is not set\n# CONFIG_RTC_DRV_ISL12026 is not set\n# CONFIG_RTC_DRV_ISL12057 is not set\n# CONFIG_RTC_DRV_ISL1208 is not set\n# CONFIG_RTC_DRV_JZ4740 is not set\n# CONFIG_RTC_DRV_M41T80 is not set\n# CONFIG_RTC_DRV_M41T93 is not set\n# CONFIG_RTC_DRV_M41T94 is not set\n# CONFIG_RTC_DRV_M48T35 is not set\n# CONFIG_RTC_DRV_M48T59 is not set\n# CONFIG_RTC_DRV_M48T86 is not set\n# CONFIG_RTC_DRV_MAX6900 is not set\n# CONFIG_RTC_DRV_MAX6902 is not set\n# CONFIG_RTC_DRV_MAX6916 is not set\n# CONFIG_RTC_DRV_MCP795 is not set\n# CONFIG_RTC_DRV_MOXART is not set\n# CONFIG_RTC_DRV_MPC5121 is not set\n# CONFIG_RTC_DRV_MSM6242 is not set\n# CONFIG_RTC_DRV_MT2712 is not set\n# CONFIG_RTC_DRV_OMAP is not set\n# CONFIG_RTC_DRV_PCF2123 is not set\n# CONFIG_RTC_DRV_PCF2127 is not set\n# CONFIG_RTC_DRV_PCF85063 is not set\n# CONFIG_RTC_DRV_PCF8523 is not set\n# CONFIG_RTC_DRV_PCF85363 is not set\n# CONFIG_RTC_DRV_PCF8563 is not set\n# CONFIG_RTC_DRV_PCF8583 is not set\n# CONFIG_RTC_DRV_PL030 is not set\n# CONFIG_RTC_DRV_PL031 is not set\n# CONFIG_RTC_DRV_PS3 is not set\n# CONFIG_RTC_DRV_PT7C4338 is not set\n# CONFIG_RTC_DRV_R7301 is not set\n# CONFIG_RTC_DRV_R9701 is not set\n# CONFIG_RTC_DRV_RP5C01 is not set\n# CONFIG_RTC_DRV_RS5C348 is not set\n# CONFIG_RTC_DRV_RS5C372 is not set\n# CONFIG_RTC_DRV_RTC7301 is not set\n# CONFIG_RTC_DRV_RV3028 is not set\n# CONFIG_RTC_DRV_RV3029C2 is not set\n# CONFIG_RTC_DRV_RV3032 is not set\n# CONFIG_RTC_DRV_RV8803 is not set\n# CONFIG_RTC_DRV_RX4581 is not set\n# CONFIG_RTC_DRV_RX6110 is not set\n# CONFIG_RTC_DRV_RX8010 is not set\n# CONFIG_RTC_DRV_RX8025 is not set\n# CONFIG_RTC_DRV_RX8581 is not set\n# CONFIG_RTC_DRV_S35390A is not set\n# CONFIG_RTC_DRV_SD3078 is not set\n# CONFIG_RTC_DRV_SNVS is not set\n# CONFIG_RTC_DRV_STK17TA8 is not set\n# CONFIG_RTC_DRV_SUN6I is not set\n# CONFIG_RTC_DRV_TEST is not set\n# CONFIG_RTC_DRV_V3020 is not set\n# CONFIG_RTC_DRV_X1205 is not set\n# CONFIG_RTC_DRV_XGENE is not set\n# CONFIG_RTC_DRV_ZYNQMP is not set\nCONFIG_RTC_HCTOSYS=y\nCONFIG_RTC_HCTOSYS_DEVICE=\"rtc0\"\nCONFIG_RTC_INTF_DEV=y\n# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set\nCONFIG_RTC_INTF_PROC=y\nCONFIG_RTC_INTF_SYSFS=y\nCONFIG_RTC_LIB=y\n# CONFIG_RTC_NVMEM is not set\nCONFIG_RTC_SYSTOHC=y\nCONFIG_RTC_SYSTOHC_DEVICE=\"rtc0\"\n# CONFIG_RTL8180 is not set\n# CONFIG_RTL8187 is not set\n# CONFIG_RTL8192E is not set\n# CONFIG_RTL8192U is not set\n# CONFIG_RTL8306_PHY is not set\n# CONFIG_RTL8366RB_PHY is not set\n# CONFIG_RTL8366S_PHY is not set\n# CONFIG_RTL8366_SMI is not set\n# CONFIG_RTL8366_SMI_DEBUG_FS is not set\n# CONFIG_RTL8367B_PHY is not set\n# CONFIG_RTL8367_PHY is not set\n# CONFIG_RTLLIB is not set\n# CONFIG_RTL_CARDS is not set\n# CONFIG_RTS5208 is not set\nCONFIG_RT_MUTEXES=y\n# CONFIG_RUNTIME_DEBUG is not set\nCONFIG_RUNTIME_TESTING_MENU=y\nCONFIG_RWSEM_GENERIC_SPINLOCK=y\nCONFIG_RXKAD=y\n# CONFIG_S2IO is not set\n# CONFIG_SAMPLES is not set\n# CONFIG_SAMSUNG_LAPTOP is not set\n# CONFIG_SATA_ACARD_AHCI is not set\n# CONFIG_SATA_AHCI is not set\n# CONFIG_SATA_AHCI_PLATFORM is not set\n# CONFIG_SATA_DWC is not set\n# CONFIG_SATA_FSL is not set\n# CONFIG_SATA_HIGHBANK is not set\n# CONFIG_SATA_HOST is not set\n# CONFIG_SATA_INIC162X is not set\nCONFIG_SATA_MOBILE_LPM_POLICY=0\n# CONFIG_SATA_MV is not set\n# CONFIG_SATA_NV is not set\n# CONFIG_SATA_PMP is not set\n# CONFIG_SATA_PROMISE is not set\n# CONFIG_SATA_QSTOR is not set\n# CONFIG_SATA_RCAR is not set\n# CONFIG_SATA_SIL is not set\n# CONFIG_SATA_SIL24 is not set\n# CONFIG_SATA_SIS is not set\n# CONFIG_SATA_SVW is not set\n# CONFIG_SATA_SX4 is not set\n# CONFIG_SATA_ULI is not set\n# CONFIG_SATA_VIA is not set\n# CONFIG_SATA_VITESSE is not set\n# CONFIG_SBC_FITPC2_WATCHDOG is not set\nCONFIG_SBITMAP=y\n# CONFIG_SC92031 is not set\n# CONFIG_SCA3000 is not set\n# CONFIG_SCACHE_DEBUGFS is not set\n# CONFIG_SCC is not set\n# CONFIG_SCD30_CORE is not set\n# CONFIG_SCF_TORTURE_TEST is not set\n# CONFIG_SCHEDSTATS is not set\n# CONFIG_SCHED_AUTOGROUP is not set\n# CONFIG_SCHED_DEBUG is not set\nCONFIG_SCHED_HRTICK=y\n# CONFIG_SCHED_MC is not set\nCONFIG_SCHED_OMIT_FRAME_POINTER=y\n# CONFIG_SCHED_SMT is not set\n# CONFIG_SCHED_STACK_END_CHECK is not set\n# CONFIG_SCHED_TRACER is not set\n# CONFIG_SCR24X is not set\n# CONFIG_SCSI is not set\n# CONFIG_SCSI_3W_9XXX is not set\n# CONFIG_SCSI_3W_SAS is not set\n# CONFIG_SCSI_7000FASST is not set\n# CONFIG_SCSI_AACRAID is not set\n# CONFIG_SCSI_ACARD is not set\n# CONFIG_SCSI_ADVANSYS is not set\n# CONFIG_SCSI_AHA152X is not set\n# CONFIG_SCSI_AHA1542 is not set\n# CONFIG_SCSI_AIC79XX is not set\n# CONFIG_SCSI_AIC7XXX is not set\n# CONFIG_SCSI_AIC94XX is not set\n# CONFIG_SCSI_AM53C974 is not set\n# CONFIG_SCSI_ARCMSR is not set\n# CONFIG_SCSI_BFA_FC is not set\n# CONFIG_SCSI_BNX2X_FCOE is not set\n# CONFIG_SCSI_BNX2_ISCSI is not set\n# CONFIG_SCSI_BUSLOGIC is not set\n# CONFIG_SCSI_CHELSIO_FCOE is not set\n# CONFIG_SCSI_CONSTANTS is not set\n# CONFIG_SCSI_CXGB3_ISCSI is not set\n# CONFIG_SCSI_CXGB4_ISCSI is not set\n# CONFIG_SCSI_DC395x is not set\n# CONFIG_SCSI_DEBUG is not set\n# CONFIG_SCSI_DH is not set\nCONFIG_SCSI_DMA=y\n# CONFIG_SCSI_DMX3191D is not set\n# CONFIG_SCSI_DPT_I2O is not set\n# CONFIG_SCSI_DTC3280 is not set\n# CONFIG_SCSI_EATA is not set\n# CONFIG_SCSI_ESAS2R is not set\n# CONFIG_SCSI_FC_ATTRS is not set\n# CONFIG_SCSI_FDOMAIN_PCI is not set\n# CONFIG_SCSI_FUTURE_DOMAIN is not set\n# CONFIG_SCSI_GDTH is not set\n# CONFIG_SCSI_GENERIC_NCR5380 is not set\n# CONFIG_SCSI_GENERIC_NCR5380_MMIO is not set\n# CONFIG_SCSI_HISI_SAS is not set\n# CONFIG_SCSI_HPSA is not set\n# CONFIG_SCSI_HPTIOP is not set\n# CONFIG_SCSI_IN2000 is not set\n# CONFIG_SCSI_INIA100 is not set\n# CONFIG_SCSI_INITIO is not set\n# CONFIG_SCSI_IPR is not set\n# CONFIG_SCSI_IPS is not set\n# CONFIG_SCSI_ISCI is not set\n# CONFIG_SCSI_ISCSI_ATTRS is not set\n# CONFIG_SCSI_LOGGING is not set\nCONFIG_SCSI_LOWLEVEL=y\n# CONFIG_SCSI_LOWLEVEL_PCMCIA is not set\n# CONFIG_SCSI_LPFC is not set\nCONFIG_SCSI_MOD=y\n# CONFIG_SCSI_MPT2SAS is not set\n# CONFIG_SCSI_MPT3SAS is not set\n# CONFIG_SCSI_MQ_DEFAULT is not set\n# CONFIG_SCSI_MVSAS is not set\n# CONFIG_SCSI_MVSAS_DEBUG is not set\n# CONFIG_SCSI_MVUMI is not set\n# CONFIG_SCSI_MYRB is not set\n# CONFIG_SCSI_MYRS is not set\n# CONFIG_SCSI_NCR53C406A is not set\n# CONFIG_SCSI_NETLINK is not set\n# CONFIG_SCSI_NSP32 is not set\n# CONFIG_SCSI_OSD_INITIATOR is not set\n# CONFIG_SCSI_PAS16 is not set\n# CONFIG_SCSI_PM8001 is not set\n# CONFIG_SCSI_PMCRAID is not set\nCONFIG_SCSI_PROC_FS=y\n# CONFIG_SCSI_QLA_FC is not set\n# CONFIG_SCSI_QLA_ISCSI is not set\n# CONFIG_SCSI_QLOGIC_1280 is not set\n# CONFIG_SCSI_QLOGIC_FAS is not set\n# CONFIG_SCSI_SAS_ATTRS is not set\n# CONFIG_SCSI_SAS_LIBSAS is not set\n# CONFIG_SCSI_SCAN_ASYNC is not set\n# CONFIG_SCSI_SMARTPQI is not set\n# CONFIG_SCSI_SNIC is not set\n# CONFIG_SCSI_SPI_ATTRS is not set\n# CONFIG_SCSI_SRP_ATTRS is not set\n# CONFIG_SCSI_STEX is not set\n# CONFIG_SCSI_SYM53C416 is not set\n# CONFIG_SCSI_SYM53C8XX_2 is not set\n# CONFIG_SCSI_T128 is not set\n# CONFIG_SCSI_U14_34F is not set\n# CONFIG_SCSI_UFSHCD is not set\n# CONFIG_SCSI_ULTRASTOR is not set\n# CONFIG_SCSI_VIRTIO is not set\n# CONFIG_SCSI_WD719X is not set\n# CONFIG_SCx200_ACB is not set\n# CONFIG_SDIO_UART is not set\n# CONFIG_SDR_MAX2175 is not set\n# CONFIG_SDR_PLATFORM_DRIVERS is not set\n# CONFIG_SD_ADC_MODULATOR is not set\n# CONFIG_SECCOMP is not set\nCONFIG_SECTION_MISMATCH_WARN_ONLY=y\n# CONFIG_SECURITY is not set\n# CONFIG_SECURITYFS is not set\n# CONFIG_SECURITY_APPARMOR is not set\nCONFIG_SECURITY_DMESG_RESTRICT=y\n# CONFIG_SECURITY_LOADPIN is not set\n# CONFIG_SECURITY_LOCKDOWN_LSM is not set\n# CONFIG_SECURITY_NETWORK_XFRM is not set\n# CONFIG_SECURITY_PATH is not set\n# CONFIG_SECURITY_SAFESETID is not set\n# CONFIG_SECURITY_SELINUX_AVC_STATS is not set\n# CONFIG_SECURITY_SELINUX_BOOTPARAM is not set\nCONFIG_SECURITY_SELINUX_CHECKREQPROT_VALUE=0\n# CONFIG_SECURITY_SELINUX_DEVELOP is not set\n# CONFIG_SECURITY_SELINUX_DISABLE is not set\n# CONFIG_SECURITY_SMACK is not set\n# CONFIG_SECURITY_TOMOYO is not set\n# CONFIG_SECURITY_YAMA is not set\nCONFIG_SELECT_MEMORY_MODEL=y\n# CONFIG_SENSIRION_SGP30 is not set\n# CONFIG_SENSORS_ABITUGURU is not set\n# CONFIG_SENSORS_ABITUGURU3 is not set\n# CONFIG_SENSORS_ACPI_POWER is not set\n# CONFIG_SENSORS_AD7314 is not set\n# CONFIG_SENSORS_AD7414 is not set\n# CONFIG_SENSORS_AD7418 is not set\n# CONFIG_SENSORS_ADC128D818 is not set\n# CONFIG_SENSORS_ADCXX is not set\n# CONFIG_SENSORS_ADM1021 is not set\n# CONFIG_SENSORS_ADM1025 is not set\n# CONFIG_SENSORS_ADM1026 is not set\n# CONFIG_SENSORS_ADM1029 is not set\n# CONFIG_SENSORS_ADM1031 is not set\n# CONFIG_SENSORS_ADM1177 is not set\n# CONFIG_SENSORS_ADM1266 is not set\n# CONFIG_SENSORS_ADM1275 is not set\n# CONFIG_SENSORS_ADM9240 is not set\n# CONFIG_SENSORS_ADS1015 is not set\n# CONFIG_SENSORS_ADS7828 is not set\n# CONFIG_SENSORS_ADS7871 is not set\n# CONFIG_SENSORS_ADT7310 is not set\n# CONFIG_SENSORS_ADT7410 is not set\n# CONFIG_SENSORS_ADT7411 is not set\n# CONFIG_SENSORS_ADT7462 is not set\n# CONFIG_SENSORS_ADT7470 is not set\n# CONFIG_SENSORS_ADT7475 is not set\n# CONFIG_SENSORS_AMC6821 is not set\n# CONFIG_SENSORS_APDS990X is not set\n# CONFIG_SENSORS_APPLESMC is not set\n# CONFIG_SENSORS_AS370 is not set\n# CONFIG_SENSORS_ASB100 is not set\n# CONFIG_SENSORS_ASC7621 is not set\n# CONFIG_SENSORS_ASPEED is not set\n# CONFIG_SENSORS_ATK0110 is not set\n# CONFIG_SENSORS_ATXP1 is not set\n# CONFIG_SENSORS_AXI_FAN_CONTROL is not set\n# CONFIG_SENSORS_BEL_PFE is not set\n# CONFIG_SENSORS_BH1770 is not set\n# CONFIG_SENSORS_BH1780 is not set\n# CONFIG_SENSORS_CORETEMP is not set\n# CONFIG_SENSORS_CORSAIR_CPRO is not set\n# CONFIG_SENSORS_DELL_SMM is not set\n# CONFIG_SENSORS_DME1737 is not set\n# CONFIG_SENSORS_DRIVETEMP is not set\n# CONFIG_SENSORS_DS1621 is not set\n# CONFIG_SENSORS_DS620 is not set\n# CONFIG_SENSORS_EMC1403 is not set\n# CONFIG_SENSORS_EMC2103 is not set\n# CONFIG_SENSORS_EMC6W201 is not set\n# CONFIG_SENSORS_F71805F is not set\n# CONFIG_SENSORS_F71882FG is not set\n# CONFIG_SENSORS_F75375S is not set\n# CONFIG_SENSORS_FAM15H_POWER is not set\n# CONFIG_SENSORS_FSCHMD is not set\n# CONFIG_SENSORS_FTSTEUTATES is not set\n# CONFIG_SENSORS_G760A is not set\n# CONFIG_SENSORS_G762 is not set\n# CONFIG_SENSORS_GL518SM is not set\n# CONFIG_SENSORS_GL520SM is not set\n# CONFIG_SENSORS_GPIO_FAN is not set\n# CONFIG_SENSORS_GSC is not set\n# CONFIG_SENSORS_HDAPS is not set\n# CONFIG_SENSORS_HIH6130 is not set\n# CONFIG_SENSORS_HMC5843 is not set\n# CONFIG_SENSORS_HMC5843_I2C is not set\n# CONFIG_SENSORS_HMC5843_SPI is not set\n# CONFIG_SENSORS_HTU21 is not set\n# CONFIG_SENSORS_I5500 is not set\n# CONFIG_SENSORS_I5K_AMB is not set\n# CONFIG_SENSORS_IBM_CFFPS is not set\n# CONFIG_SENSORS_IIO_HWMON is not set\n# CONFIG_SENSORS_INA209 is not set\n# CONFIG_SENSORS_INA2XX is not set\n# CONFIG_SENSORS_INA3221 is not set\n# CONFIG_SENSORS_INSPUR_IPSPS is not set\n# CONFIG_SENSORS_IR35221 is not set\n# CONFIG_SENSORS_IR38064 is not set\n# CONFIG_SENSORS_IRPS5401 is not set\n# CONFIG_SENSORS_ISL29018 is not set\n# CONFIG_SENSORS_ISL29028 is not set\n# CONFIG_SENSORS_ISL68137 is not set\n# CONFIG_SENSORS_IT87 is not set\n# CONFIG_SENSORS_JC42 is not set\n# CONFIG_SENSORS_K10TEMP is not set\n# CONFIG_SENSORS_K8TEMP is not set\n# CONFIG_SENSORS_LINEAGE is not set\n# CONFIG_SENSORS_LIS3LV02D is not set\n# CONFIG_SENSORS_LIS3_I2C is not set\n# CONFIG_SENSORS_LIS3_SPI is not set\n# CONFIG_SENSORS_LM25066 is not set\n# CONFIG_SENSORS_LM63 is not set\n# CONFIG_SENSORS_LM70 is not set\n# CONFIG_SENSORS_LM73 is not set\n# CONFIG_SENSORS_LM75 is not set\n# CONFIG_SENSORS_LM77 is not set\n# CONFIG_SENSORS_LM78 is not set\n# CONFIG_SENSORS_LM80 is not set\n# CONFIG_SENSORS_LM83 is not set\n# CONFIG_SENSORS_LM85 is not set\n# CONFIG_SENSORS_LM87 is not set\n# CONFIG_SENSORS_LM90 is not set\n# CONFIG_SENSORS_LM92 is not set\n# CONFIG_SENSORS_LM93 is not set\n# CONFIG_SENSORS_LM95234 is not set\n# CONFIG_SENSORS_LM95241 is not set\n# CONFIG_SENSORS_LM95245 is not set\n# CONFIG_SENSORS_LTC2945 is not set\n# CONFIG_SENSORS_LTC2947_I2C is not set\n# CONFIG_SENSORS_LTC2947_SPI is not set\n# CONFIG_SENSORS_LTC2978 is not set\n# CONFIG_SENSORS_LTC2990 is not set\n# CONFIG_SENSORS_LTC3815 is not set\n# CONFIG_SENSORS_LTC4151 is not set\n# CONFIG_SENSORS_LTC4215 is not set\n# CONFIG_SENSORS_LTC4222 is not set\n# CONFIG_SENSORS_LTC4245 is not set\n# CONFIG_SENSORS_LTC4260 is not set\n# CONFIG_SENSORS_LTC4261 is not set\n# CONFIG_SENSORS_LTQ_CPUTEMP is not set\n# CONFIG_SENSORS_MAX1111 is not set\n# CONFIG_SENSORS_MAX16064 is not set\n# CONFIG_SENSORS_MAX16065 is not set\n# CONFIG_SENSORS_MAX1619 is not set\n# CONFIG_SENSORS_MAX16601 is not set\n# CONFIG_SENSORS_MAX1668 is not set\n# CONFIG_SENSORS_MAX197 is not set\n# CONFIG_SENSORS_MAX20730 is not set\n# CONFIG_SENSORS_MAX20751 is not set\n# CONFIG_SENSORS_MAX31722 is not set\n# CONFIG_SENSORS_MAX31730 is not set\n# CONFIG_SENSORS_MAX31785 is not set\n# CONFIG_SENSORS_MAX31790 is not set\n# CONFIG_SENSORS_MAX34440 is not set\n# CONFIG_SENSORS_MAX6621 is not set\n# CONFIG_SENSORS_MAX6639 is not set\n# CONFIG_SENSORS_MAX6642 is not set\n# CONFIG_SENSORS_MAX6650 is not set\n# CONFIG_SENSORS_MAX6697 is not set\n# CONFIG_SENSORS_MAX8688 is not set\n# CONFIG_SENSORS_MCP3021 is not set\n# CONFIG_SENSORS_MP2975 is not set\n# CONFIG_SENSORS_MR75203 is not set\n# CONFIG_SENSORS_NCT6683 is not set\n# CONFIG_SENSORS_NCT6775 is not set\n# CONFIG_SENSORS_NCT7802 is not set\n# CONFIG_SENSORS_NCT7904 is not set\n# CONFIG_SENSORS_NPCM7XX is not set\n# CONFIG_SENSORS_NSA320 is not set\n# CONFIG_SENSORS_NTC_THERMISTOR is not set\n# CONFIG_SENSORS_OCC_P8_I2C is not set\n# CONFIG_SENSORS_PC87360 is not set\n# CONFIG_SENSORS_PC87427 is not set\n# CONFIG_SENSORS_PCF8591 is not set\n# CONFIG_SENSORS_PMBUS is not set\n# CONFIG_SENSORS_POWR1220 is not set\n# CONFIG_SENSORS_PWM_FAN is not set\n# CONFIG_SENSORS_PXE1610 is not set\n# CONFIG_SENSORS_RM3100_I2C is not set\n# CONFIG_SENSORS_RM3100_SPI is not set\n# CONFIG_SENSORS_SCH5627 is not set\n# CONFIG_SENSORS_SCH5636 is not set\n# CONFIG_SENSORS_SCH56XX_COMMON is not set\n# CONFIG_SENSORS_SHT15 is not set\n# CONFIG_SENSORS_SHT21 is not set\n# CONFIG_SENSORS_SHT3x is not set\n# CONFIG_SENSORS_SHTC1 is not set\n# CONFIG_SENSORS_SIS5595 is not set\n# CONFIG_SENSORS_SMM665 is not set\n# CONFIG_SENSORS_SMSC47B397 is not set\n# CONFIG_SENSORS_SMSC47M1 is not set\n# CONFIG_SENSORS_SMSC47M192 is not set\n# CONFIG_SENSORS_STTS751 is not set\n# CONFIG_SENSORS_TC654 is not set\n# CONFIG_SENSORS_TC74 is not set\n# CONFIG_SENSORS_THMC50 is not set\n# CONFIG_SENSORS_TMP102 is not set\n# CONFIG_SENSORS_TMP103 is not set\n# CONFIG_SENSORS_TMP108 is not set\n# CONFIG_SENSORS_TMP401 is not set\n# CONFIG_SENSORS_TMP421 is not set\n# CONFIG_SENSORS_TMP513 is not set\n# CONFIG_SENSORS_TPS40422 is not set\n# CONFIG_SENSORS_TPS53679 is not set\n# CONFIG_SENSORS_TSL2550 is not set\n# CONFIG_SENSORS_TSL2563 is not set\n# CONFIG_SENSORS_UCD9000 is not set\n# CONFIG_SENSORS_UCD9200 is not set\n# CONFIG_SENSORS_VEXPRESS is not set\n# CONFIG_SENSORS_VIA686A is not set\n# CONFIG_SENSORS_VIA_CPUTEMP is not set\n# CONFIG_SENSORS_VT1211 is not set\n# CONFIG_SENSORS_VT8231 is not set\n# CONFIG_SENSORS_W83627EHF is not set\n# CONFIG_SENSORS_W83627HF is not set\n# CONFIG_SENSORS_W83773G is not set\n# CONFIG_SENSORS_W83781D is not set\n# CONFIG_SENSORS_W83791D is not set\n# CONFIG_SENSORS_W83792D is not set\n# CONFIG_SENSORS_W83793 is not set\n# CONFIG_SENSORS_W83795 is not set\n# CONFIG_SENSORS_W83L785TS is not set\n# CONFIG_SENSORS_W83L786NG is not set\n# CONFIG_SENSORS_XDPE122 is not set\n# CONFIG_SENSORS_XGENE is not set\n# CONFIG_SENSORS_ZL6100 is not set\nCONFIG_SERIAL_8250=y\nCONFIG_SERIAL_8250_16550A_VARIANTS=y\n# CONFIG_SERIAL_8250_ACCENT is not set\n# CONFIG_SERIAL_8250_ASPEED_VUART is not set\n# CONFIG_SERIAL_8250_BOCA is not set\nCONFIG_SERIAL_8250_CONSOLE=y\n# CONFIG_SERIAL_8250_CS is not set\n# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set\n# CONFIG_SERIAL_8250_DETECT_IRQ is not set\nCONFIG_SERIAL_8250_DMA=y\n# CONFIG_SERIAL_8250_DW is not set\n# CONFIG_SERIAL_8250_EM is not set\n# CONFIG_SERIAL_8250_EXAR is not set\n# CONFIG_SERIAL_8250_EXAR_ST16C554 is not set\n# CONFIG_SERIAL_8250_EXTENDED is not set\n# CONFIG_SERIAL_8250_FINTEK is not set\n# CONFIG_SERIAL_8250_FOURPORT is not set\n# CONFIG_SERIAL_8250_HUB6 is not set\n# CONFIG_SERIAL_8250_INGENIC is not set\n# CONFIG_SERIAL_8250_LPSS is not set\n# CONFIG_SERIAL_8250_MANY_PORTS is not set\n# CONFIG_SERIAL_8250_MID is not set\n# CONFIG_SERIAL_8250_MOXA is not set\nCONFIG_SERIAL_8250_NR_UARTS=2\n# CONFIG_SERIAL_8250_PCI is not set\n# CONFIG_SERIAL_8250_RSA is not set\n# CONFIG_SERIAL_8250_RT288X is not set\nCONFIG_SERIAL_8250_RUNTIME_UARTS=2\n# CONFIG_SERIAL_ALTERA_JTAGUART is not set\n# CONFIG_SERIAL_ALTERA_UART is not set\n# CONFIG_SERIAL_AMBA_PL010 is not set\n# CONFIG_SERIAL_AMBA_PL011 is not set\n# CONFIG_SERIAL_ARC is not set\n# CONFIG_SERIAL_BCM63XX is not set\n# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set\nCONFIG_SERIAL_CORE=y\nCONFIG_SERIAL_CORE_CONSOLE=y\n# CONFIG_SERIAL_DEV_BUS is not set\nCONFIG_SERIAL_EARLYCON=y\n# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set\n# CONFIG_SERIAL_FSL_LINFLEXUART is not set\n# CONFIG_SERIAL_FSL_LPUART is not set\n# CONFIG_SERIAL_GRLIB_GAISLER_APBUART is not set\n# CONFIG_SERIAL_IFX6X60 is not set\n# CONFIG_SERIAL_JSM is not set\n# CONFIG_SERIAL_MAX3100 is not set\n# CONFIG_SERIAL_MAX310X is not set\n# CONFIG_SERIAL_NONSTANDARD is not set\n# CONFIG_SERIAL_OF_PLATFORM is not set\n# CONFIG_SERIAL_OF_PLATFORM_NWPSERIAL is not set\n# CONFIG_SERIAL_PCH_UART is not set\n# CONFIG_SERIAL_RP2 is not set\n# CONFIG_SERIAL_SC16IS7XX is not set\n# CONFIG_SERIAL_SCCNXP is not set\n# CONFIG_SERIAL_SH_SCI is not set\n# CONFIG_SERIAL_SIFIVE is not set\n# CONFIG_SERIAL_SPRD is not set\n# CONFIG_SERIAL_STM32 is not set\n# CONFIG_SERIAL_ST_ASC is not set\n# CONFIG_SERIAL_TIMBERDALE is not set\n# CONFIG_SERIAL_UARTLITE is not set\n# CONFIG_SERIAL_XILINX_PS_UART is not set\n# CONFIG_SERIO is not set\n# CONFIG_SERIO_ALTERA_PS2 is not set\n# CONFIG_SERIO_AMBAKMI is not set\n# CONFIG_SERIO_APBPS2 is not set\n# CONFIG_SERIO_ARC_PS2 is not set\n# CONFIG_SERIO_CT82C710 is not set\n# CONFIG_SERIO_GPIO_PS2 is not set\n# CONFIG_SERIO_I8042 is not set\n# CONFIG_SERIO_LIBPS2 is not set\n# CONFIG_SERIO_PARKBD is not set\n# CONFIG_SERIO_PCIPS2 is not set\n# CONFIG_SERIO_PS2MULT is not set\n# CONFIG_SERIO_RAW is not set\n# CONFIG_SERIO_SERPORT is not set\n# CONFIG_SERIO_SUN4I_PS2 is not set\n# CONFIG_SFC is not set\n# CONFIG_SFC_FALCON is not set\n# CONFIG_SFI is not set\n# CONFIG_SFP is not set\n# CONFIG_SF_PDMA is not set\n# CONFIG_SGETMASK_SYSCALL is not set\n# CONFIG_SGI_IOC4 is not set\n# CONFIG_SGI_IP22 is not set\n# CONFIG_SGI_IP27 is not set\n# CONFIG_SGI_IP28 is not set\n# CONFIG_SGI_IP30 is not set\n# CONFIG_SGI_IP32 is not set\n# CONFIG_SGI_MFD_IOC3 is not set\n# CONFIG_SGI_PARTITION is not set\n# CONFIG_SG_POOL is not set\n# CONFIG_SG_SPLIT is not set\nCONFIG_SHMEM=y\n# CONFIG_SHUFFLE_PAGE_ALLOCATOR is not set\n# CONFIG_SH_ETH is not set\n# CONFIG_SH_TIMER_CMT is not set\n# CONFIG_SH_TIMER_MTU2 is not set\n# CONFIG_SH_TIMER_TMU is not set\n# CONFIG_SI1133 is not set\n# CONFIG_SI1145 is not set\n# CONFIG_SI7005 is not set\n# CONFIG_SI7020 is not set\n# CONFIG_SIBYTE_BIGSUR is not set\n# CONFIG_SIBYTE_CARMEL is not set\n# CONFIG_SIBYTE_CRHINE is not set\n# CONFIG_SIBYTE_CRHONE is not set\n# CONFIG_SIBYTE_LITTLESUR is not set\n# CONFIG_SIBYTE_RHONE is not set\n# CONFIG_SIBYTE_SENTOSA is not set\n# CONFIG_SIBYTE_SWARM is not set\nCONFIG_SIGNALFD=y\n# CONFIG_SIGNED_PE_FILE_VERIFICATION is not set\n# CONFIG_SIMPLE_GPIO is not set\n# CONFIG_SIMPLE_PM_BUS is not set\n# CONFIG_SIOX is not set\n# CONFIG_SIS190 is not set\n# CONFIG_SIS900 is not set\n# CONFIG_SKGE is not set\n# CONFIG_SKY2 is not set\n# CONFIG_SKY2_DEBUG is not set\n# CONFIG_SLAB is not set\nCONFIG_SLABINFO=y\n# CONFIG_SLAB_FREELIST_HARDENED is not set\n# CONFIG_SLAB_FREELIST_RANDOM is not set\nCONFIG_SLAB_MERGE_DEFAULT=y\n# CONFIG_SLHC is not set\n# CONFIG_SLICOSS is not set\n# CONFIG_SLIMBUS is not set\n# CONFIG_SLIP is not set\n# CONFIG_SLOB is not set\nCONFIG_SLUB=y\nCONFIG_SLUB_CPU_PARTIAL=y\n# CONFIG_SLUB_DEBUG is not set\n# CONFIG_SLUB_DEBUG_ON is not set\n# CONFIG_SLUB_MEMCG_SYSFS_ON is not set\n# CONFIG_SLUB_STATS is not set\n# CONFIG_SMARTJOYPLUS_FF is not set\n# CONFIG_SMC911X is not set\n# CONFIG_SMC9194 is not set\n# CONFIG_SMC91X is not set\n# CONFIG_SMP is not set\n# CONFIG_SMSC911X is not set\n# CONFIG_SMSC9420 is not set\n# CONFIG_SMSC_PHY is not set\n# CONFIG_SMS_SDIO_DRV is not set\n# CONFIG_SMS_USB_DRV is not set\n# CONFIG_SM_FTL is not set\n# CONFIG_SND is not set\n# CONFIG_SND_AC97_POWER_SAVE is not set\n# CONFIG_SND_AD1816A is not set\n# CONFIG_SND_AD1848 is not set\n# CONFIG_SND_AD1889 is not set\n# CONFIG_SND_ADLIB is not set\n# CONFIG_SND_ALI5451 is not set\n# CONFIG_SND_ALOOP is not set\n# CONFIG_SND_ALS100 is not set\n# CONFIG_SND_ALS300 is not set\n# CONFIG_SND_ALS4000 is not set\n# CONFIG_SND_ARM is not set\n# CONFIG_SND_ASIHPI is not set\n# CONFIG_SND_ATIIXP is not set\n# CONFIG_SND_ATIIXP_MODEM is not set\n# CONFIG_SND_ATMEL_AC97C is not set\n# CONFIG_SND_ATMEL_SOC is not set\n# CONFIG_SND_AU8810 is not set\n# CONFIG_SND_AU8820 is not set\n# CONFIG_SND_AU8830 is not set\n# CONFIG_SND_AUDIO_GRAPH_CARD is not set\n# CONFIG_SND_AUDIO_GRAPH_SCU_CARD is not set\n# CONFIG_SND_AW2 is not set\n# CONFIG_SND_AZT2320 is not set\n# CONFIG_SND_AZT3328 is not set\n# CONFIG_SND_BCD2000 is not set\n# CONFIG_SND_BCM63XX_I2S_WHISTLER is not set\n# CONFIG_SND_BT87X is not set\n# CONFIG_SND_CA0106 is not set\n# CONFIG_SND_CMI8330 is not set\n# CONFIG_SND_CMIPCI is not set\n# CONFIG_SND_CS4231 is not set\n# CONFIG_SND_CS4236 is not set\n# CONFIG_SND_CS4281 is not set\n# CONFIG_SND_CS46XX is not set\n# CONFIG_SND_CS5530 is not set\n# CONFIG_SND_CS5535AUDIO is not set\n# CONFIG_SND_CTXFI is not set\n# CONFIG_SND_DARLA20 is not set\n# CONFIG_SND_DARLA24 is not set\n# CONFIG_SND_DEBUG is not set\n# CONFIG_SND_DESIGNWARE_I2S is not set\nCONFIG_SND_DRIVERS=y\n# CONFIG_SND_DUMMY is not set\n# CONFIG_SND_DYNAMIC_MINORS is not set\n# CONFIG_SND_ECHO3G is not set\n# CONFIG_SND_EDMA_SOC is not set\n# CONFIG_SND_EMU10K1 is not set\n# CONFIG_SND_EMU10K1X is not set\n# CONFIG_SND_EMU10K1_SEQ is not set\n# CONFIG_SND_ENS1370 is not set\n# CONFIG_SND_ENS1371 is not set\n# CONFIG_SND_ES1688 is not set\n# CONFIG_SND_ES18XX is not set\n# CONFIG_SND_ES1938 is not set\n# CONFIG_SND_ES1968 is not set\n# CONFIG_SND_FIREWIRE is not set\n# CONFIG_SND_FM801 is not set\n# CONFIG_SND_GINA20 is not set\n# CONFIG_SND_GINA24 is not set\n# CONFIG_SND_GUSCLASSIC is not set\n# CONFIG_SND_GUSEXTREME is not set\n# CONFIG_SND_GUSMAX is not set\n# CONFIG_SND_HDA_INTEL is not set\n# CONFIG_SND_HDA_INTEL_DETECT_DMIC is not set\n# CONFIG_SND_HDA_INTEL_HDMI_SILENT_STREAM is not set\nCONFIG_SND_HDA_POWER_SAVE_DEFAULT=0\nCONFIG_SND_HDA_PREALLOC_SIZE=64\n# CONFIG_SND_HDSP is not set\n# CONFIG_SND_HDSPM is not set\n# CONFIG_SND_HRTIMER is not set\n# CONFIG_SND_HWDEP is not set\n# CONFIG_SND_I2S_HI6210_I2S is not set\n# CONFIG_SND_ICE1712 is not set\n# CONFIG_SND_ICE1724 is not set\n# CONFIG_SND_INDIGO is not set\n# CONFIG_SND_INDIGODJ is not set\n# CONFIG_SND_INDIGODJX is not set\n# CONFIG_SND_INDIGOIO is not set\n# CONFIG_SND_INDIGOIOX is not set\n# CONFIG_SND_INTEL8X0 is not set\n# CONFIG_SND_INTEL8X0M is not set\n# CONFIG_SND_INTERWAVE is not set\n# CONFIG_SND_INTERWAVE_STB is not set\n# CONFIG_SND_ISA is not set\n# CONFIG_SND_JZ4740_SOC_I2S is not set\n# CONFIG_SND_KIRKWOOD_SOC is not set\n# CONFIG_SND_KORG1212 is not set\n# CONFIG_SND_LAYLA20 is not set\n# CONFIG_SND_LAYLA24 is not set\n# CONFIG_SND_LOLA is not set\n# CONFIG_SND_LX6464ES is not set\n# CONFIG_SND_MAESTRO3 is not set\nCONFIG_SND_MAX_CARDS=16\n# CONFIG_SND_MIA is not set\n# CONFIG_SND_MIPS is not set\n# CONFIG_SND_MIRO is not set\n# CONFIG_SND_MIXART is not set\n# CONFIG_SND_MIXER_OSS is not set\n# CONFIG_SND_MONA is not set\n# CONFIG_SND_MPC52xx_SOC_EFIKA is not set\n# CONFIG_SND_MPU401 is not set\n# CONFIG_SND_MTPAV is not set\n# CONFIG_SND_MTS64 is not set\n# CONFIG_SND_MXS_SOC is not set\n# CONFIG_SND_NM256 is not set\n# CONFIG_SND_OPL3SA2 is not set\n# CONFIG_SND_OPL3_LIB_SEQ is not set\n# CONFIG_SND_OPL4_LIB_SEQ is not set\n# CONFIG_SND_OPTI92X_AD1848 is not set\n# CONFIG_SND_OPTI92X_CS4231 is not set\n# CONFIG_SND_OPTI93X is not set\nCONFIG_SND_OSSEMUL=y\n# CONFIG_SND_OXYGEN is not set\nCONFIG_SND_PCI=y\n# CONFIG_SND_PCM is not set\n# CONFIG_SND_PCMCIA is not set\n# CONFIG_SND_PCM_OSS is not set\nCONFIG_SND_PCM_OSS_PLUGINS=y\n# CONFIG_SND_PCM_TIMER is not set\n# CONFIG_SND_PCM_XRUN_DEBUG is not set\n# CONFIG_SND_PCXHR is not set\n# CONFIG_SND_PDAUDIOCF is not set\n# CONFIG_SND_PORTMAN2X4 is not set\n# CONFIG_SND_POWERPC_SOC is not set\n# CONFIG_SND_PPC is not set\nCONFIG_SND_PROC_FS=y\n# CONFIG_SND_RAWMIDI is not set\n# CONFIG_SND_RAWMIDI_SEQ is not set\n# CONFIG_SND_RIPTIDE is not set\n# CONFIG_SND_RME32 is not set\n# CONFIG_SND_RME96 is not set\n# CONFIG_SND_RME9652 is not set\n# CONFIG_SND_RTCTIMER is not set\n# CONFIG_SND_SB16 is not set\n# CONFIG_SND_SB8 is not set\n# CONFIG_SND_SBAWE is not set\n# CONFIG_SND_SBAWE_SEQ is not set\n# CONFIG_SND_SE6X is not set\n# CONFIG_SND_SEQUENCER is not set\n# CONFIG_SND_SERIAL_U16550 is not set\n# CONFIG_SND_SIMPLE_CARD is not set\n# CONFIG_SND_SIMPLE_SCU_CARD is not set\n# CONFIG_SND_SIS7019 is not set\n# CONFIG_SND_SOC is not set\n# CONFIG_SND_SOC_AC97_CODEC is not set\n# CONFIG_SND_SOC_ADAU1701 is not set\n# CONFIG_SND_SOC_ADAU1761_I2C is not set\n# CONFIG_SND_SOC_ADAU1761_SPI is not set\n# CONFIG_SND_SOC_ADAU7002 is not set\n# CONFIG_SND_SOC_ADAU7118_HW is not set\n# CONFIG_SND_SOC_ADAU7118_I2C is not set\n# CONFIG_SND_SOC_AK4104 is not set\n# CONFIG_SND_SOC_AK4118 is not set\n# CONFIG_SND_SOC_AK4458 is not set\n# CONFIG_SND_SOC_AK4554 is not set\n# CONFIG_SND_SOC_AK4613 is not set\n# CONFIG_SND_SOC_AK4642 is not set\n# CONFIG_SND_SOC_AK5386 is not set\n# CONFIG_SND_SOC_AK5558 is not set\n# CONFIG_SND_SOC_ALC5623 is not set\n# CONFIG_SND_SOC_AMD_ACP is not set\n# CONFIG_SND_SOC_AMD_ACP3x is not set\n# CONFIG_SND_SOC_AMD_RENOIR is not set\n# CONFIG_SND_SOC_AU1XAUDIO is not set\n# CONFIG_SND_SOC_AU1XPSC is not set\n# CONFIG_SND_SOC_BD28623 is not set\n# CONFIG_SND_SOC_BT_SCO is not set\n# CONFIG_SND_SOC_CS35L32 is not set\n# CONFIG_SND_SOC_CS35L33 is not set\n# CONFIG_SND_SOC_CS35L34 is not set\n# CONFIG_SND_SOC_CS35L35 is not set\n# CONFIG_SND_SOC_CS35L36 is not set\n# CONFIG_SND_SOC_CS4234 is not set\n# CONFIG_SND_SOC_CS4265 is not set\n# CONFIG_SND_SOC_CS4270 is not set\n# CONFIG_SND_SOC_CS4271 is not set\n# CONFIG_SND_SOC_CS4271_I2C is not set\n# CONFIG_SND_SOC_CS4271_SPI is not set\n# CONFIG_SND_SOC_CS42L42 is not set\n# CONFIG_SND_SOC_CS42L51_I2C is not set\n# CONFIG_SND_SOC_CS42L52 is not set\n# CONFIG_SND_SOC_CS42L56 is not set\n# CONFIG_SND_SOC_CS42L73 is not set\n# CONFIG_SND_SOC_CS42XX8_I2C is not set\n# CONFIG_SND_SOC_CS43130 is not set\n# CONFIG_SND_SOC_CS4341 is not set\n# CONFIG_SND_SOC_CS4349 is not set\n# CONFIG_SND_SOC_CS53L30 is not set\n# CONFIG_SND_SOC_CX2072X is not set\n# CONFIG_SND_SOC_DA7213 is not set\n# CONFIG_SND_SOC_DIO2125 is not set\n# CONFIG_SND_SOC_DMIC is not set\n# CONFIG_SND_SOC_ES7134 is not set\n# CONFIG_SND_SOC_ES7241 is not set\n# CONFIG_SND_SOC_ES8316 is not set\n# CONFIG_SND_SOC_ES8328 is not set\n# CONFIG_SND_SOC_ES8328_I2C is not set\n# CONFIG_SND_SOC_ES8328_SPI is not set\n# CONFIG_SND_SOC_EUKREA_TLV320 is not set\n# CONFIG_SND_SOC_FSL_ASOC_CARD is not set\n# CONFIG_SND_SOC_FSL_ASRC is not set\n# CONFIG_SND_SOC_FSL_AUDMIX is not set\n# CONFIG_SND_SOC_FSL_ESAI is not set\n# CONFIG_SND_SOC_FSL_MICFIL is not set\n# CONFIG_SND_SOC_FSL_SAI is not set\n# CONFIG_SND_SOC_FSL_SPDIF is not set\n# CONFIG_SND_SOC_FSL_SSI is not set\n# CONFIG_SND_SOC_GTM601 is not set\n# CONFIG_SND_SOC_ICS43432 is not set\n# CONFIG_SND_SOC_IMG is not set\n# CONFIG_SND_SOC_IMX_AUDMIX is not set\n# CONFIG_SND_SOC_IMX_AUDMUX is not set\n# CONFIG_SND_SOC_IMX_ES8328 is not set\n# CONFIG_SND_SOC_IMX_SPDIF is not set\n# CONFIG_SND_SOC_IMX_WM8962 is not set\n# CONFIG_SND_SOC_INNO_RK3036 is not set\n# CONFIG_SND_SOC_INTEL_APL is not set\n# CONFIG_SND_SOC_INTEL_BAYTRAIL is not set\n# CONFIG_SND_SOC_INTEL_BDW_RT5677_MACH is not set\n# CONFIG_SND_SOC_INTEL_BXT_DA7219_MAX98357A_MACH is not set\n# CONFIG_SND_SOC_INTEL_BXT_RT298_MACH is not set\n# CONFIG_SND_SOC_INTEL_BYTCR_RT5640_MACH is not set\n# CONFIG_SND_SOC_INTEL_BYTCR_RT5651_MACH is not set\n# CONFIG_SND_SOC_INTEL_BYT_CHT_DA7213_MACH is not set\n# CONFIG_SND_SOC_INTEL_BYT_CHT_ES8316_MACH is not set\n# CONFIG_SND_SOC_INTEL_BYT_CHT_NOCODEC_MACH is not set\n# CONFIG_SND_SOC_INTEL_BYT_MAX98090_MACH is not set\n# CONFIG_SND_SOC_INTEL_BYT_RT5640_MACH is not set\n# CONFIG_SND_SOC_INTEL_CATPT is not set\n# CONFIG_SND_SOC_INTEL_CFL is not set\n# CONFIG_SND_SOC_INTEL_CHT_BSW_MAX98090_TI_MACH is not set\n# CONFIG_SND_SOC_INTEL_CHT_BSW_NAU8824_MACH is not set\n# CONFIG_SND_SOC_INTEL_CHT_BSW_RT5645_MACH is not set\n# CONFIG_SND_SOC_INTEL_CHT_BSW_RT5672_MACH is not set\n# CONFIG_SND_SOC_INTEL_CML_H is not set\n# CONFIG_SND_SOC_INTEL_CML_LP is not set\n# CONFIG_SND_SOC_INTEL_CNL is not set\n# CONFIG_SND_SOC_INTEL_GLK is not set\n# CONFIG_SND_SOC_INTEL_HASWELL is not set\n# CONFIG_SND_SOC_INTEL_KBL is not set\n# CONFIG_SND_SOC_INTEL_KBL_RT5663_MAX98927_MACH is not set\n# CONFIG_SND_SOC_INTEL_KBL_RT5663_RT5514_MAX98927_MACH is not set\n# CONFIG_SND_SOC_INTEL_KEEMBAY is not set\n# CONFIG_SND_SOC_INTEL_SKL is not set\n# CONFIG_SND_SOC_INTEL_SKL_NAU88L25_MAX98357A_MACH is not set\n# CONFIG_SND_SOC_INTEL_SKL_NAU88L25_SSM4567_MACH is not set\n# CONFIG_SND_SOC_INTEL_SKL_RT286_MACH is not set\n# CONFIG_SND_SOC_INTEL_SKYLAKE is not set\n# CONFIG_SND_SOC_INTEL_SST is not set\nCONFIG_SND_SOC_INTEL_SST_TOPLEVEL=y\n# CONFIG_SND_SOC_INTEL_USER_FRIENDLY_LONG_NAMES is not set\n# CONFIG_SND_SOC_JZ4725B_CODEC is not set\n# CONFIG_SND_SOC_JZ4740_CODEC is not set\n# CONFIG_SND_SOC_JZ4770_CODEC is not set\n# CONFIG_SND_SOC_MA120X0P is not set\n# CONFIG_SND_SOC_MAX9759 is not set\n# CONFIG_SND_SOC_MAX98088 is not set\n# CONFIG_SND_SOC_MAX98357A is not set\n# CONFIG_SND_SOC_MAX98373 is not set\n# CONFIG_SND_SOC_MAX98373_I2C is not set\n# CONFIG_SND_SOC_MAX98390 is not set\n# CONFIG_SND_SOC_MAX98504 is not set\n# CONFIG_SND_SOC_MAX9860 is not set\n# CONFIG_SND_SOC_MAX9867 is not set\n# CONFIG_SND_SOC_MAX98927 is not set\n# CONFIG_SND_SOC_MEDIATEK is not set\n# CONFIG_SND_SOC_MPC5200_AC97 is not set\n# CONFIG_SND_SOC_MPC5200_I2S is not set\n# CONFIG_SND_SOC_MSM8916_WCD_ANALOG is not set\n# CONFIG_SND_SOC_MSM8916_WCD_DIGITAL is not set\n# CONFIG_SND_SOC_MT2701 is not set\n# CONFIG_SND_SOC_MT6351 is not set\n# CONFIG_SND_SOC_MT6358 is not set\n# CONFIG_SND_SOC_MT6660 is not set\n# CONFIG_SND_SOC_MT6797 is not set\n# CONFIG_SND_SOC_MT8173 is not set\n# CONFIG_SND_SOC_MT8183 is not set\n# CONFIG_SND_SOC_MTK_BTCVSD is not set\n# CONFIG_SND_SOC_NAU8540 is not set\n# CONFIG_SND_SOC_NAU8810 is not set\n# CONFIG_SND_SOC_NAU8822 is not set\n# CONFIG_SND_SOC_NAU8824 is not set\n# CONFIG_SND_SOC_PCM1681 is not set\n# CONFIG_SND_SOC_PCM1789_I2C is not set\n# CONFIG_SND_SOC_PCM1792A is not set\n# CONFIG_SND_SOC_PCM179X_I2C is not set\n# CONFIG_SND_SOC_PCM179X_SPI is not set\n# CONFIG_SND_SOC_PCM186X_I2C is not set\n# CONFIG_SND_SOC_PCM186X_SPI is not set\n# CONFIG_SND_SOC_PCM3060_I2C is not set\n# CONFIG_SND_SOC_PCM3060_SPI is not set\n# CONFIG_SND_SOC_PCM3168A_I2C is not set\n# CONFIG_SND_SOC_PCM3168A_SPI is not set\n# CONFIG_SND_SOC_PCM512x_I2C is not set\n# CONFIG_SND_SOC_PCM512x_SPI is not set\n# CONFIG_SND_SOC_QCOM is not set\n# CONFIG_SND_SOC_RK3328 is not set\n# CONFIG_SND_SOC_RT5616 is not set\n# CONFIG_SND_SOC_RT5631 is not set\n# CONFIG_SND_SOC_RT5677_SPI is not set\n# CONFIG_SND_SOC_SGTL5000 is not set\n# CONFIG_SND_SOC_SIMPLE_AMPLIFIER is not set\n# CONFIG_SND_SOC_SIRF_AUDIO_CODEC is not set\n# CONFIG_SND_SOC_SOF_TOPLEVEL is not set\n# CONFIG_SND_SOC_SPDIF is not set\n# CONFIG_SND_SOC_SSM2305 is not set\n# CONFIG_SND_SOC_SSM2602_I2C is not set\n# CONFIG_SND_SOC_SSM2602_SPI is not set\n# CONFIG_SND_SOC_SSM4567 is not set\n# CONFIG_SND_SOC_STA32X is not set\n# CONFIG_SND_SOC_STA350 is not set\n# CONFIG_SND_SOC_STI_SAS is not set\n# CONFIG_SND_SOC_TAS2552 is not set\n# CONFIG_SND_SOC_TAS2562 is not set\n# CONFIG_SND_SOC_TAS2764 is not set\n# CONFIG_SND_SOC_TAS2770 is not set\n# CONFIG_SND_SOC_TAS5086 is not set\n# CONFIG_SND_SOC_TAS571X is not set\n# CONFIG_SND_SOC_TAS5720 is not set\n# CONFIG_SND_SOC_TAS6424 is not set\n# CONFIG_SND_SOC_TDA7419 is not set\n# CONFIG_SND_SOC_TFA9879 is not set\n# CONFIG_SND_SOC_TLV320ADCX140 is not set\n# CONFIG_SND_SOC_TLV320AIC23_I2C is not set\n# CONFIG_SND_SOC_TLV320AIC23_SPI is not set\n# CONFIG_SND_SOC_TLV320AIC31XX is not set\n# CONFIG_SND_SOC_TLV320AIC32X4_I2C is not set\n# CONFIG_SND_SOC_TLV320AIC32X4_SPI is not set\n# CONFIG_SND_SOC_TLV320AIC3X is not set\n# CONFIG_SND_SOC_TPA6130A2 is not set\n# CONFIG_SND_SOC_TS3A227E is not set\n# CONFIG_SND_SOC_TSCS42XX is not set\n# CONFIG_SND_SOC_TSCS454 is not set\n# CONFIG_SND_SOC_UDA1334 is not set\n# CONFIG_SND_SOC_WM8510 is not set\n# CONFIG_SND_SOC_WM8523 is not set\n# CONFIG_SND_SOC_WM8524 is not set\n# CONFIG_SND_SOC_WM8580 is not set\n# CONFIG_SND_SOC_WM8711 is not set\n# CONFIG_SND_SOC_WM8728 is not set\n# CONFIG_SND_SOC_WM8731 is not set\n# CONFIG_SND_SOC_WM8737 is not set\n# CONFIG_SND_SOC_WM8741 is not set\n# CONFIG_SND_SOC_WM8750 is not set\n# CONFIG_SND_SOC_WM8753 is not set\n# CONFIG_SND_SOC_WM8770 is not set\n# CONFIG_SND_SOC_WM8776 is not set\n# CONFIG_SND_SOC_WM8782 is not set\n# CONFIG_SND_SOC_WM8804_I2C is not set\n# CONFIG_SND_SOC_WM8804_SPI is not set\n# CONFIG_SND_SOC_WM8903 is not set\n# CONFIG_SND_SOC_WM8904 is not set\n# CONFIG_SND_SOC_WM8960 is not set\n# CONFIG_SND_SOC_WM8962 is not set\n# CONFIG_SND_SOC_WM8974 is not set\n# CONFIG_SND_SOC_WM8978 is not set\n# CONFIG_SND_SOC_WM8985 is not set\n# CONFIG_SND_SOC_XILINX_AUDIO_FORMATTER is not set\n# CONFIG_SND_SOC_XILINX_I2S is not set\n# CONFIG_SND_SOC_XILINX_SPDIF is not set\n# CONFIG_SND_SOC_XTFPGA_I2S is not set\n# CONFIG_SND_SOC_ZL38060 is not set\n# CONFIG_SND_SOC_ZX_AUD96P22 is not set\n# CONFIG_SND_SONICVIBES is not set\n# CONFIG_SND_SPI is not set\n# CONFIG_SND_SSCAPE is not set\n# CONFIG_SND_SST_ATOM_HIFI2_PLATFORM_ACPI is not set\n# CONFIG_SND_SST_ATOM_HIFI2_PLATFORM_PCI is not set\n# CONFIG_SND_SUN4I_CODEC is not set\n# CONFIG_SND_SUPPORT_OLD_API is not set\n# CONFIG_SND_TIMER is not set\n# CONFIG_SND_TRIDENT is not set\nCONFIG_SND_USB=y\n# CONFIG_SND_USB_6FIRE is not set\n# CONFIG_SND_USB_AUDIO is not set\n# CONFIG_SND_USB_CAIAQ is not set\n# CONFIG_SND_USB_HIFACE is not set\n# CONFIG_SND_USB_POD is not set\n# CONFIG_SND_USB_PODHD is not set\n# CONFIG_SND_USB_TONEPORT is not set\n# CONFIG_SND_USB_UA101 is not set\n# CONFIG_SND_USB_US122L is not set\n# CONFIG_SND_USB_USX2Y is not set\n# CONFIG_SND_USB_VARIAX is not set\n# CONFIG_SND_VERBOSE_PRINTK is not set\nCONFIG_SND_VERBOSE_PROCFS=y\n# CONFIG_SND_VIA82XX is not set\n# CONFIG_SND_VIA82XX_MODEM is not set\n# CONFIG_SND_VIRTUOSO is not set\n# CONFIG_SND_VX222 is not set\n# CONFIG_SND_VXPOCKET is not set\n# CONFIG_SND_WAVEFRONT is not set\nCONFIG_SND_X86=y\n# CONFIG_SND_XEN_FRONTEND is not set\n# CONFIG_SND_YMFPCI is not set\n# CONFIG_SNI_RM is not set\n# CONFIG_SOCIONEXT_SYNQUACER_PREITS is not set\n# CONFIG_SOCK_CGROUP_DATA is not set\n# CONFIG_SOC_AM33XX is not set\n# CONFIG_SOC_AM43XX is not set\n# CONFIG_SOC_BRCMSTB is not set\n# CONFIG_SOC_CAMERA is not set\n# CONFIG_SOC_DRA7XX is not set\n# CONFIG_SOC_HAS_OMAP2_SDRC is not set\n# CONFIG_SOC_OMAP5 is not set\n# CONFIG_SOC_TI is not set\n# CONFIG_SOFTLOCKUP_DETECTOR is not set\n# CONFIG_SOFT_WATCHDOG is not set\n# CONFIG_SOLARIS_X86_PARTITION is not set\n# CONFIG_SONYPI is not set\n# CONFIG_SONY_LAPTOP is not set\n# CONFIG_SOUND is not set\n# CONFIG_SOUNDWIRE is not set\n# CONFIG_SOUND_OSS_CORE is not set\n# CONFIG_SOUND_OSS_CORE_PRECLAIM is not set\n# CONFIG_SOUND_PRIME is not set\n# CONFIG_SP5100_TCO is not set\n# CONFIG_SPARSEMEM_MANUAL is not set\n# CONFIG_SPARSEMEM_STATIC is not set\n# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set\n# CONFIG_SPARSE_IRQ is not set\n# CONFIG_SPARSE_RCU_POINTER is not set\n# CONFIG_SPEAKUP is not set\n# CONFIG_SPI is not set\n# CONFIG_SPINLOCK_TEST is not set\n# CONFIG_SPI_ALTERA is not set\n# CONFIG_SPI_AMD is not set\n# CONFIG_SPI_AU1550 is not set\n# CONFIG_SPI_AXI_SPI_ENGINE is not set\n# CONFIG_SPI_BCM2835 is not set\n# CONFIG_SPI_BCM_QSPI is not set\n# CONFIG_SPI_BITBANG is not set\n# CONFIG_SPI_BUTTERFLY is not set\n# CONFIG_SPI_CADENCE is not set\n# CONFIG_SPI_CADENCE_QUADSPI is not set\n# CONFIG_SPI_DEBUG is not set\n# CONFIG_SPI_DESIGNWARE is not set\n# CONFIG_SPI_FSL_DSPI is not set\n# CONFIG_SPI_FSL_ESPI is not set\n# CONFIG_SPI_FSL_SPI is not set\n# CONFIG_SPI_GPIO is not set\n# CONFIG_SPI_GPIO_OLD is not set\n# CONFIG_SPI_IMG_SPFI is not set\n# CONFIG_SPI_LANTIQ_SSC is not set\n# CONFIG_SPI_LM70_LLP is not set\n# CONFIG_SPI_LOOPBACK_TEST is not set\n# CONFIG_SPI_MASTER is not set\n# CONFIG_SPI_MEM is not set\n# CONFIG_SPI_MPC52xx is not set\n# CONFIG_SPI_MPC52xx_PSC is not set\n# CONFIG_SPI_MTK_QUADSPI is not set\n# CONFIG_SPI_MUX is not set\n# CONFIG_SPI_MXIC is not set\n# CONFIG_SPI_NXP_FLEXSPI is not set\n# CONFIG_SPI_OCTEON is not set\n# CONFIG_SPI_OC_TINY is not set\n# CONFIG_SPI_ORION is not set\n# CONFIG_SPI_PL022 is not set\n# CONFIG_SPI_PPC4xx is not set\n# CONFIG_SPI_PXA2XX is not set\n# CONFIG_SPI_PXA2XX_PCI is not set\n# CONFIG_SPI_QCOM_QSPI is not set\n# CONFIG_SPI_ROCKCHIP is not set\n# CONFIG_SPI_S3C64XX is not set\n# CONFIG_SPI_SC18IS602 is not set\n# CONFIG_SPI_SIFIVE is not set\n# CONFIG_SPI_SLAVE is not set\n# CONFIG_SPI_SPIDEV is not set\n# CONFIG_SPI_THUNDERX is not set\n# CONFIG_SPI_TI_QSPI is not set\n# CONFIG_SPI_TLE62X0 is not set\n# CONFIG_SPI_TOPCLIFF_PCH is not set\n# CONFIG_SPI_XCOMM is not set\n# CONFIG_SPI_XILINX is not set\n# CONFIG_SPI_XWAY is not set\n# CONFIG_SPI_ZYNQMP_GQSPI is not set\nCONFIG_SPLIT_PTLOCK_CPUS=4\n# CONFIG_SPMI is not set\n# CONFIG_SPS30 is not set\nCONFIG_SQUASHFS=y\n# CONFIG_SQUASHFS_4K_DEVBLK_SIZE is not set\n# CONFIG_SQUASHFS_DECOMP_MULTI is not set\nCONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y\n# CONFIG_SQUASHFS_DECOMP_SINGLE is not set\nCONFIG_SQUASHFS_EMBEDDED=y\n# CONFIG_SQUASHFS_FILE_CACHE is not set\nCONFIG_SQUASHFS_FILE_DIRECT=y\nCONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3\n# CONFIG_SQUASHFS_LZ4 is not set\n# CONFIG_SQUASHFS_LZO is not set\n# CONFIG_SQUASHFS_XATTR is not set\nCONFIG_SQUASHFS_XZ=y\n# CONFIG_SQUASHFS_ZLIB is not set\n# CONFIG_SQUASHFS_ZSTD is not set\n# CONFIG_SRAM is not set\n# CONFIG_SRF04 is not set\n# CONFIG_SRF08 is not set\n# CONFIG_SSB is not set\n# CONFIG_SSB_DEBUG is not set\n# CONFIG_SSB_DRIVER_GPIO is not set\n# CONFIG_SSB_HOST_SOC is not set\n# CONFIG_SSB_PCMCIAHOST is not set\nCONFIG_SSB_POSSIBLE=y\n# CONFIG_SSB_SDIOHOST is not set\n# CONFIG_SSB_SILENT is not set\n# CONFIG_SSFDC is not set\n# CONFIG_STACKPROTECTOR is not set\n# CONFIG_STACKPROTECTOR_STRONG is not set\n# CONFIG_STACKTRACE is not set\nCONFIG_STACKTRACE_SUPPORT=y\n# CONFIG_STACK_TRACER is not set\n# CONFIG_STACK_VALIDATION is not set\nCONFIG_STAGING=y\n# CONFIG_STAGING_BOARD is not set\n# CONFIG_STAGING_GASKET_FRAMEWORK is not set\n# CONFIG_STAGING_MEDIA is not set\nCONFIG_STANDALONE=y\n# CONFIG_STATIC_KEYS_SELFTEST is not set\n# CONFIG_STATIC_USERMODEHELPER is not set\nCONFIG_STDBINUTILS=y\n# CONFIG_STE10XP is not set\n# CONFIG_STE_MODEM_RPROC is not set\n# CONFIG_STK3310 is not set\n# CONFIG_STK8312 is not set\n# CONFIG_STK8BA50 is not set\n# CONFIG_STM is not set\n# CONFIG_STMMAC_ETH is not set\n# CONFIG_STMMAC_PCI is not set\n# CONFIG_STMMAC_PLATFORM is not set\n# CONFIG_STM_DUMMY is not set\n# CONFIG_STM_SOURCE_CONSOLE is not set\nCONFIG_STP=y\n# CONFIG_STREAM_PARSER is not set\n# CONFIG_STRICT_DEVMEM is not set\nCONFIG_STRICT_KERNEL_RWX=y\nCONFIG_STRICT_MODULE_RWX=y\n# CONFIG_STRING_SELFTEST is not set\nCONFIG_STRIP_ASM_SYMS=y\n# CONFIG_STX104 is not set\n# CONFIG_ST_UVIS25 is not set\n# CONFIG_SUN4I_GPADC is not set\n# CONFIG_SUN50I_DE2_BUS is not set\n# CONFIG_SUN50I_ERRATUM_UNKNOWN1 is not set\n# CONFIG_SUNDANCE is not set\n# CONFIG_SUNGEM is not set\n# CONFIG_SUNRPC is not set\n# CONFIG_SUNRPC_DEBUG is not set\nCONFIG_SUNRPC_DISABLE_INSECURE_ENCTYPES=y\n# CONFIG_SUNRPC_GSS is not set\n# CONFIG_SUNXI_SRAM is not set\n# CONFIG_SUN_PARTITION is not set\n# CONFIG_SURFACE_3_BUTTON is not set\n# CONFIG_SUSPEND is not set\n# CONFIG_SUSPEND_SKIP_SYNC is not set\nCONFIG_SWAP=y\n# CONFIG_SWCONFIG is not set\n# CONFIG_SWCONFIG_B53 is not set\n# CONFIG_SWCONFIG_B53_MDIO_DRIVER is not set\n# CONFIG_SWCONFIG_B53_MMAP_DRIVER is not set\n# CONFIG_SWCONFIG_B53_SPI_DRIVER is not set\n# CONFIG_SWCONFIG_B53_SRAB_DRIVER is not set\n# CONFIG_SWCONFIG_LEDS is not set\n# CONFIG_SW_SYNC is not set\n# CONFIG_SX9310 is not set\n# CONFIG_SX9500 is not set\n# CONFIG_SXGBE_ETH is not set\nCONFIG_SYMBOLIC_ERRNAME=y\n# CONFIG_SYNCLINK_CS is not set\n# CONFIG_SYNC_FILE is not set\n# CONFIG_SYNOPSYS_DWC_ETH_QOS is not set\n# CONFIG_SYNTH_EVENTS is not set\nCONFIG_SYN_COOKIES=y\n# CONFIG_SYSCON_REBOOT_MODE is not set\nCONFIG_SYSCTL=y\n# CONFIG_SYSCTL_SYSCALL is not set\nCONFIG_SYSFS=y\n# CONFIG_SYSFS_DEPRECATED is not set\n# CONFIG_SYSFS_DEPRECATED_V2 is not set\n# CONFIG_SYSFS_SYSCALL is not set\n# CONFIG_SYSTEMPORT is not set\n# CONFIG_SYSTEM_BLACKLIST_KEYRING is not set\n# CONFIG_SYSTEM_DATA_VERIFICATION is not set\n# CONFIG_SYSTEM_TRUSTED_KEYRING is not set\nCONFIG_SYSTEM_TRUSTED_KEYS=\"\"\n# CONFIG_SYSV68_PARTITION is not set\nCONFIG_SYSVIPC=y\nCONFIG_SYSVIPC_SYSCTL=y\n# CONFIG_SYSV_FS is not set\n# CONFIG_SYS_HYPERVISOR is not set\n# CONFIG_T5403 is not set\n# CONFIG_TARGET_CORE is not set\n# CONFIG_TASKSTATS is not set\n# CONFIG_TASKS_RCU is not set\n# CONFIG_TASK_XACCT is not set\n# CONFIG_TC35815 is not set\n# CONFIG_TCG_ATMEL is not set\n# CONFIG_TCG_CRB is not set\n# CONFIG_TCG_FTPM_TEE is not set\n# CONFIG_TCG_INFINEON is not set\n# CONFIG_TCG_NSC is not set\n# CONFIG_TCG_ST33_I2C is not set\n# CONFIG_TCG_TIS is not set\n# CONFIG_TCG_TIS_I2C_ATMEL is not set\n# CONFIG_TCG_TIS_I2C_INFINEON is not set\n# CONFIG_TCG_TIS_I2C_NUVOTON is not set\n# CONFIG_TCG_TIS_SPI is not set\n# CONFIG_TCG_TIS_ST33ZP24_I2C is not set\n# CONFIG_TCG_TIS_ST33ZP24_SPI is not set\n# CONFIG_TCG_TPM is not set\n# CONFIG_TCG_VTPM_PROXY is not set\n# CONFIG_TCG_XEN is not set\n# CONFIG_TCIC is not set\nCONFIG_TCP_CONG_ADVANCED=y\n# CONFIG_TCP_CONG_BBR is not set\n# CONFIG_TCP_CONG_BIC is not set\n# CONFIG_TCP_CONG_CDG is not set\nCONFIG_TCP_CONG_CUBIC=y\n# CONFIG_TCP_CONG_DCTCP is not set\n# CONFIG_TCP_CONG_HSTCP is not set\n# CONFIG_TCP_CONG_HTCP is not set\n# CONFIG_TCP_CONG_HYBLA is not set\n# CONFIG_TCP_CONG_ILLINOIS is not set\n# CONFIG_TCP_CONG_LP is not set\n# CONFIG_TCP_CONG_NV is not set\n# CONFIG_TCP_CONG_SCALABLE is not set\n# CONFIG_TCP_CONG_VEGAS is not set\n# CONFIG_TCP_CONG_VENO is not set\n# CONFIG_TCP_CONG_WESTWOOD is not set\n# CONFIG_TCP_CONG_YEAH is not set\n# CONFIG_TCP_MD5SIG is not set\n# CONFIG_TCS3414 is not set\n# CONFIG_TCS3472 is not set\n# CONFIG_TEE is not set\n# CONFIG_TEGRA_AHB is not set\n# CONFIG_TEGRA_HOST1X is not set\n# CONFIG_TEHUTI is not set\n# CONFIG_TERANETICS_PHY is not set\n# CONFIG_TEST_ASYNC_DRIVER_PROBE is not set\n# CONFIG_TEST_BITFIELD is not set\n# CONFIG_TEST_BITMAP is not set\n# CONFIG_TEST_BITOPS is not set\n# CONFIG_TEST_BLACKHOLE_DEV is not set\n# CONFIG_TEST_BPF is not set\n# CONFIG_TEST_FIRMWARE is not set\n# CONFIG_TEST_FREE_PAGES is not set\n# CONFIG_TEST_HASH is not set\n# CONFIG_TEST_HEXDUMP is not set\n# CONFIG_TEST_IDA is not set\n# CONFIG_TEST_KASAN_MODULE is not set\n# CONFIG_TEST_KMOD is not set\n# CONFIG_TEST_KSTRTOX is not set\n# CONFIG_TEST_LIST_SORT is not set\n# CONFIG_TEST_LKM is not set\n# CONFIG_TEST_LOCKUP is not set\n# CONFIG_TEST_MEMCAT_P is not set\n# CONFIG_TEST_MEMINIT is not set\n# CONFIG_TEST_MIN_HEAP is not set\n# CONFIG_TEST_OVERFLOW is not set\n# CONFIG_TEST_POWER is not set\n# CONFIG_TEST_PRINTF is not set\n# CONFIG_TEST_RHASHTABLE is not set\n# CONFIG_TEST_SORT is not set\n# CONFIG_TEST_STACKINIT is not set\n# CONFIG_TEST_STATIC_KEYS is not set\n# CONFIG_TEST_STRING_HELPERS is not set\n# CONFIG_TEST_STRSCPY is not set\n# CONFIG_TEST_SYSCTL is not set\n# CONFIG_TEST_UBSAN is not set\n# CONFIG_TEST_UDELAY is not set\n# CONFIG_TEST_USER_COPY is not set\n# CONFIG_TEST_UUID is not set\n# CONFIG_TEST_VMALLOC is not set\n# CONFIG_TEST_XARRAY is not set\nCONFIG_TEXTSEARCH=y\n# CONFIG_TEXTSEARCH_BM is not set\n# CONFIG_TEXTSEARCH_FSM is not set\n# CONFIG_TEXTSEARCH_KMP is not set\n# CONFIG_THERMAL is not set\n# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set\n# CONFIG_THERMAL_DEFAULT_GOV_POWER_ALLOCATOR is not set\n# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set\n# CONFIG_THERMAL_EMULATION is not set\n# CONFIG_THERMAL_GOV_BANG_BANG is not set\n# CONFIG_THERMAL_GOV_FAIR_SHARE is not set\n# CONFIG_THERMAL_GOV_POWER_ALLOCATOR is not set\n# CONFIG_THERMAL_GOV_USER_SPACE is not set\n# CONFIG_THERMAL_HWMON is not set\n# CONFIG_THERMAL_MMIO is not set\n# CONFIG_THERMAL_NETLINK is not set\n# CONFIG_THERMAL_STATISTICS is not set\n# CONFIG_THERMAL_WRITABLE_TRIPS is not set\n# CONFIG_THINKPAD_ACPI is not set\nCONFIG_THIN_ARCHIVES=y\n# CONFIG_THRUSTMASTER_FF is not set\n# CONFIG_THUMB2_KERNEL is not set\n# CONFIG_THUNDERBOLT is not set\n# CONFIG_THUNDER_NIC_BGX is not set\n# CONFIG_THUNDER_NIC_PF is not set\n# CONFIG_THUNDER_NIC_RGX is not set\n# CONFIG_THUNDER_NIC_VF is not set\n# CONFIG_TICK_CPU_ACCOUNTING is not set\nCONFIG_TICK_ONESHOT=y\n# CONFIG_TIFM_CORE is not set\n# CONFIG_TIGON3 is not set\n# CONFIG_TIMB_DMA is not set\nCONFIG_TIMERFD=y\n# CONFIG_TIMER_STATS is not set\n# CONFIG_TIME_NS is not set\n# CONFIG_TINYDRM_HX8357D is not set\n# CONFIG_TINYDRM_ILI9225 is not set\n# CONFIG_TINYDRM_ILI9341 is not set\n# CONFIG_TINYDRM_ILI9486 is not set\n# CONFIG_TINYDRM_MI0283QT is not set\n# CONFIG_TINYDRM_REPAPER is not set\n# CONFIG_TINYDRM_ST7586 is not set\n# CONFIG_TINYDRM_ST7735R is not set\nCONFIG_TINY_RCU=y\n# CONFIG_TIPC is not set\n# CONFIG_TI_ADC081C is not set\n# CONFIG_TI_ADC0832 is not set\n# CONFIG_TI_ADC084S021 is not set\n# CONFIG_TI_ADC108S102 is not set\n# CONFIG_TI_ADC12138 is not set\n# CONFIG_TI_ADC128S052 is not set\n# CONFIG_TI_ADC161S626 is not set\n# CONFIG_TI_ADS1015 is not set\n# CONFIG_TI_ADS124S08 is not set\n# CONFIG_TI_ADS7950 is not set\n# CONFIG_TI_ADS8344 is not set\n# CONFIG_TI_ADS8688 is not set\n# CONFIG_TI_AM335X_ADC is not set\n# CONFIG_TI_CPSW is not set\n# CONFIG_TI_CPSW_ALE is not set\n# CONFIG_TI_CPSW_PHY_SEL is not set\n# CONFIG_TI_CPTS is not set\n# CONFIG_TI_DAC082S085 is not set\n# CONFIG_TI_DAC5571 is not set\n# CONFIG_TI_DAC7311 is not set\n# CONFIG_TI_DAC7512 is not set\n# CONFIG_TI_DAC7612 is not set\n# CONFIG_TI_DAVINCI_CPDMA is not set\n# CONFIG_TI_DAVINCI_MDIO is not set\n# CONFIG_TI_ST is not set\n# CONFIG_TI_SYSCON_RESET is not set\n# CONFIG_TI_TLC4541 is not set\n# CONFIG_TLAN is not set\n# CONFIG_TLS is not set\n# CONFIG_TMD_HERMES is not set\n# CONFIG_TMP006 is not set\n# CONFIG_TMP007 is not set\nCONFIG_TMPFS=y\n# CONFIG_TMPFS_INODE64 is not set\n# CONFIG_TMPFS_POSIX_ACL is not set\nCONFIG_TMPFS_XATTR=y\n# CONFIG_TOPSTAR_LAPTOP is not set\n# CONFIG_TORTURE_TEST is not set\n# CONFIG_TOSHIBA_HAPS is not set\n# CONFIG_TOUCHSCREEN_88PM860X is not set\n# CONFIG_TOUCHSCREEN_AD7877 is not set\n# CONFIG_TOUCHSCREEN_AD7879 is not set\n# CONFIG_TOUCHSCREEN_AD7879_I2C is not set\n# CONFIG_TOUCHSCREEN_AD7879_SPI is not set\n# CONFIG_TOUCHSCREEN_ADC is not set\n# CONFIG_TOUCHSCREEN_ADS7846 is not set\n# CONFIG_TOUCHSCREEN_AR1021_I2C is not set\n# CONFIG_TOUCHSCREEN_ATMEL_MXT is not set\n# CONFIG_TOUCHSCREEN_ATMEL_MXT_T37 is not set\n# CONFIG_TOUCHSCREEN_AUO_PIXCIR is not set\n# CONFIG_TOUCHSCREEN_BU21013 is not set\n# CONFIG_TOUCHSCREEN_BU21029 is not set\n# CONFIG_TOUCHSCREEN_CHIPONE_ICN8318 is not set\n# CONFIG_TOUCHSCREEN_CHIPONE_ICN8505 is not set\n# CONFIG_TOUCHSCREEN_COLIBRI_VF50 is not set\n# CONFIG_TOUCHSCREEN_CY8CTMA140 is not set\n# CONFIG_TOUCHSCREEN_CY8CTMG110 is not set\n# CONFIG_TOUCHSCREEN_CYTTSP4_CORE is not set\n# CONFIG_TOUCHSCREEN_CYTTSP4_I2C is not set\n# CONFIG_TOUCHSCREEN_CYTTSP4_SPI is not set\n# CONFIG_TOUCHSCREEN_CYTTSP_CORE is not set\n# CONFIG_TOUCHSCREEN_CYTTSP_I2C is not set\n# CONFIG_TOUCHSCREEN_CYTTSP_SPI is not set\n# CONFIG_TOUCHSCREEN_DA9034 is not set\n# CONFIG_TOUCHSCREEN_DA9052 is not set\n# CONFIG_TOUCHSCREEN_DYNAPRO is not set\n# CONFIG_TOUCHSCREEN_EDT_FT5X06 is not set\n# CONFIG_TOUCHSCREEN_EETI is not set\n# CONFIG_TOUCHSCREEN_EGALAX is not set\n# CONFIG_TOUCHSCREEN_EGALAX_SERIAL is not set\n# CONFIG_TOUCHSCREEN_EKTF2127 is not set\n# CONFIG_TOUCHSCREEN_ELAN is not set\n# CONFIG_TOUCHSCREEN_ELO is not set\n# CONFIG_TOUCHSCREEN_EXC3000 is not set\n# CONFIG_TOUCHSCREEN_FUJITSU is not set\n# CONFIG_TOUCHSCREEN_GOODIX is not set\n# CONFIG_TOUCHSCREEN_GUNZE is not set\n# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set\n# CONFIG_TOUCHSCREEN_HIDEEP is not set\n# CONFIG_TOUCHSCREEN_HP600 is not set\n# CONFIG_TOUCHSCREEN_HP7XX is not set\n# CONFIG_TOUCHSCREEN_HTCPEN is not set\n# CONFIG_TOUCHSCREEN_ILI210X is not set\n# CONFIG_TOUCHSCREEN_IMX6UL_TSC is not set\n# CONFIG_TOUCHSCREEN_INEXIO is not set\n# CONFIG_TOUCHSCREEN_IPAQ_MICRO is not set\n# CONFIG_TOUCHSCREEN_IPROC is not set\n# CONFIG_TOUCHSCREEN_IQS5XX is not set\n# CONFIG_TOUCHSCREEN_LPC32XX is not set\n# CONFIG_TOUCHSCREEN_MAX11801 is not set\n# CONFIG_TOUCHSCREEN_MC13783 is not set\n# CONFIG_TOUCHSCREEN_MCS5000 is not set\n# CONFIG_TOUCHSCREEN_MELFAS_MIP4 is not set\n# CONFIG_TOUCHSCREEN_MIGOR is not set\n# CONFIG_TOUCHSCREEN_MK712 is not set\n# CONFIG_TOUCHSCREEN_MMS114 is not set\n# CONFIG_TOUCHSCREEN_MTOUCH is not set\n# CONFIG_TOUCHSCREEN_MX25 is not set\n# CONFIG_TOUCHSCREEN_MXS_LRADC is not set\n# CONFIG_TOUCHSCREEN_PCAP is not set\n# CONFIG_TOUCHSCREEN_PENMOUNT is not set\n# CONFIG_TOUCHSCREEN_PIXCIR is not set\n# CONFIG_TOUCHSCREEN_PROPERTIES is not set\n# CONFIG_TOUCHSCREEN_RASPBERRYPI_FW is not set\n# CONFIG_TOUCHSCREEN_RM_TS is not set\n# CONFIG_TOUCHSCREEN_ROHM_BU21023 is not set\n# CONFIG_TOUCHSCREEN_RPI_FT5406 is not set\n# CONFIG_TOUCHSCREEN_S3C2410 is not set\n# CONFIG_TOUCHSCREEN_S6SY761 is not set\n# CONFIG_TOUCHSCREEN_SILEAD is not set\n# CONFIG_TOUCHSCREEN_SIS_I2C is not set\n# CONFIG_TOUCHSCREEN_ST1232 is not set\n# CONFIG_TOUCHSCREEN_STMFTS is not set\n# CONFIG_TOUCHSCREEN_STMPE is not set\n# CONFIG_TOUCHSCREEN_SUN4I is not set\n# CONFIG_TOUCHSCREEN_SUR40 is not set\n# CONFIG_TOUCHSCREEN_SURFACE3_SPI is not set\n# CONFIG_TOUCHSCREEN_SX8654 is not set\n# CONFIG_TOUCHSCREEN_TI_AM335X_TSC is not set\n# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set\n# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set\n# CONFIG_TOUCHSCREEN_TOUCHWIN is not set\n# CONFIG_TOUCHSCREEN_TPS6507X is not set\n# CONFIG_TOUCHSCREEN_TS4800 is not set\n# CONFIG_TOUCHSCREEN_TSC2004 is not set\n# CONFIG_TOUCHSCREEN_TSC2005 is not set\n# CONFIG_TOUCHSCREEN_TSC2007 is not set\n# CONFIG_TOUCHSCREEN_TSC2007_IIO is not set\n# CONFIG_TOUCHSCREEN_TSC200X_CORE is not set\n# CONFIG_TOUCHSCREEN_TSC_SERIO is not set\n# CONFIG_TOUCHSCREEN_UCB1400 is not set\n# CONFIG_TOUCHSCREEN_USB_3M is not set\n# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set\n# CONFIG_TOUCHSCREEN_USB_DMC_TSC10 is not set\n# CONFIG_TOUCHSCREEN_USB_E2I is not set\n# CONFIG_TOUCHSCREEN_USB_EASYTOUCH is not set\n# CONFIG_TOUCHSCREEN_USB_EGALAX is not set\n# CONFIG_TOUCHSCREEN_USB_ELO is not set\n# CONFIG_TOUCHSCREEN_USB_ETT_TC45USB is not set\n# CONFIG_TOUCHSCREEN_USB_ETURBO is not set\n# CONFIG_TOUCHSCREEN_USB_GENERAL_TOUCH is not set\n# CONFIG_TOUCHSCREEN_USB_GOTOP is not set\n# CONFIG_TOUCHSCREEN_USB_GUNZE is not set\n# CONFIG_TOUCHSCREEN_USB_IDEALTEK is not set\n# CONFIG_TOUCHSCREEN_USB_IRTOUCH is not set\n# CONFIG_TOUCHSCREEN_USB_ITM is not set\n# CONFIG_TOUCHSCREEN_USB_JASTEC is not set\n# CONFIG_TOUCHSCREEN_USB_NEXIO is not set\n# CONFIG_TOUCHSCREEN_USB_PANJIT is not set\n# CONFIG_TOUCHSCREEN_USB_ZYTRONIC is not set\n# CONFIG_TOUCHSCREEN_W90X900 is not set\n# CONFIG_TOUCHSCREEN_WACOM_I2C is not set\n# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set\n# CONFIG_TOUCHSCREEN_WDT87XX_I2C is not set\n# CONFIG_TOUCHSCREEN_WM831X is not set\n# CONFIG_TOUCHSCREEN_WM9705 is not set\n# CONFIG_TOUCHSCREEN_WM9712 is not set\n# CONFIG_TOUCHSCREEN_WM9713 is not set\n# CONFIG_TOUCHSCREEN_WM97XX is not set\n# CONFIG_TOUCHSCREEN_WM97XX_MAINSTONE is not set\n# CONFIG_TOUCHSCREEN_WM97XX_ZYLONITE is not set\n# CONFIG_TOUCHSCREEN_ZET6223 is not set\n# CONFIG_TOUCHSCREEN_ZFORCE is not set\n# CONFIG_TOUCHSCREEN_ZINITIX is not set\n# CONFIG_TPL0102 is not set\n# CONFIG_TPS6105X is not set\n# CONFIG_TPS65010 is not set\n# CONFIG_TPS6507X is not set\n# CONFIG_TRACEPOINT_BENCHMARK is not set\n# CONFIG_TRACER_SNAPSHOT is not set\n# CONFIG_TRACER_SNAPSHOT_PER_CPU_SWAP is not set\n# CONFIG_TRACE_BRANCH_PROFILING is not set\n# CONFIG_TRACE_EVAL_MAP_FILE is not set\n# CONFIG_TRACE_EVENT_INJECT is not set\nCONFIG_TRACE_IRQFLAGS_SUPPORT=y\n# CONFIG_TRACE_SINK is not set\n# CONFIG_TRACING_EVENTS_GPIO is not set\nCONFIG_TRACING_SUPPORT=y\nCONFIG_TRAD_SIGNALS=y\n# CONFIG_TRANSPARENT_HUGEPAGE is not set\n# CONFIG_TREE_RCU is not set\n# CONFIG_TREE_RCU_TRACE is not set\n# CONFIG_TRIM_UNUSED_KSYMS is not set\n# CONFIG_TRUSTED_FOUNDATIONS is not set\n# CONFIG_TRUSTED_KEYS is not set\n# CONFIG_TSL2583 is not set\n# CONFIG_TSL2772 is not set\n# CONFIG_TSL2x7x is not set\n# CONFIG_TSL4531 is not set\n# CONFIG_TSYS01 is not set\n# CONFIG_TSYS02D is not set\n# CONFIG_TTPCI_EEPROM is not set\nCONFIG_TTY=y\n# CONFIG_TTY_PRINTK is not set\n# CONFIG_TUN is not set\n# CONFIG_TUN_VNET_CROSS_LE is not set\n# CONFIG_TWL4030_CORE is not set\n# CONFIG_TWL4030_MADC is not set\n# CONFIG_TWL6030_GPADC is not set\n# CONFIG_TWL6040_CORE is not set\n# CONFIG_TYPEC is not set\n# CONFIG_TYPEC_TCPM is not set\n# CONFIG_TYPEC_UCSI is not set\n# CONFIG_TYPHOON is not set\n# CONFIG_UACCESS_WITH_MEMCPY is not set\n# CONFIG_UBIFS_ATIME_SUPPORT is not set\n# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set\n# CONFIG_UBIFS_FS_AUTHENTICATION is not set\n# CONFIG_UBIFS_FS_ENCRYPTION is not set\nCONFIG_UBIFS_FS_LZO=y\n# CONFIG_UBIFS_FS_SECURITY is not set\nCONFIG_UBIFS_FS_XATTR=y\nCONFIG_UBIFS_FS_ZLIB=y\nCONFIG_UBIFS_FS_ZSTD=y\n# CONFIG_UBSAN is not set\nCONFIG_UBSAN_ALIGNMENT=y\n# CONFIG_UBSAN_MISC is not set\n# CONFIG_UCB1400_CORE is not set\n# CONFIG_UCSI is not set\n# CONFIG_UDF_FS is not set\n# CONFIG_UDMABUF is not set\nCONFIG_UEVENT_HELPER=y\nCONFIG_UEVENT_HELPER_PATH=\"/sbin/hotplug\"\n# CONFIG_UFS_FS is not set\n# CONFIG_UHID is not set\nCONFIG_UID16=y\n# CONFIG_UIO is not set\n# CONFIG_ULTRA is not set\n# CONFIG_ULTRIX_PARTITION is not set\n# CONFIG_UNICODE is not set\n# CONFIG_UNISYSSPAR is not set\n# CONFIG_UNISYS_VISORBUS is not set\nCONFIG_UNIX=y\nCONFIG_UNIX98_PTYS=y\n# CONFIG_UNIXWARE_DISKLABEL is not set\n# CONFIG_UNIX_DIAG is not set\nCONFIG_UNIX_SCM=y\n# CONFIG_UNUSED_SYMBOLS is not set\n# CONFIG_UNWINDER_FRAME_POINTER is not set\n# CONFIG_UPROBES is not set\n# CONFIG_UPROBE_EVENTS is not set\n# CONFIG_US5182D is not set\n# CONFIG_USB is not set\n# CONFIG_USB4 is not set\n# CONFIG_USBIP_CORE is not set\nCONFIG_USBIP_VHCI_HC_PORTS=8\nCONFIG_USBIP_VHCI_NR_HCS=1\n# CONFIG_USBIP_VUDC is not set\n# CONFIG_USBPCWATCHDOG is not set\n# CONFIG_USB_ACM is not set\n# CONFIG_USB_ADUTUX is not set\n# CONFIG_USB_AIRSPY is not set\nCONFIG_USB_ALI_M5632=y\n# CONFIG_USB_AMD5536UDC is not set\nCONFIG_USB_AN2720=y\n# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set\n# CONFIG_USB_APPLEDISPLAY is not set\nCONFIG_USB_ARCH_HAS_HCD=y\nCONFIG_USB_ARMLINUX=y\n# CONFIG_USB_ATM is not set\nCONFIG_USB_AUTOSUSPEND_DELAY=2\n# CONFIG_USB_BDC_UDC is not set\nCONFIG_USB_BELKIN=y\n# CONFIG_USB_C67X00_HCD is not set\n# CONFIG_USB_CATC is not set\n# CONFIG_USB_CDC_COMPOSITE is not set\n# CONFIG_USB_CDNS3 is not set\n# CONFIG_USB_CHAOSKEY is not set\n# CONFIG_USB_CHIPIDEA is not set\n# CONFIG_USB_CHIPIDEA_GENERIC is not set\n# CONFIG_USB_CHIPIDEA_IMX is not set\n# CONFIG_USB_CHIPIDEA_MSM is not set\n# CONFIG_USB_CHIPIDEA_PCI is not set\n# CONFIG_USB_CHIPIDEA_TEGRA is not set\n# CONFIG_USB_CONFIGFS is not set\n# CONFIG_USB_CONN_GPIO is not set\n# CONFIG_USB_CXACRU is not set\n# CONFIG_USB_CYPRESS_CY7C63 is not set\n# CONFIG_USB_CYTHERM is not set\nCONFIG_USB_DEFAULT_PERSIST=y\n# CONFIG_USB_DSBR is not set\n# CONFIG_USB_DUMMY_HCD is not set\n# CONFIG_USB_DWC2 is not set\n# CONFIG_USB_DWC2_DEBUG is not set\n# CONFIG_USB_DWC2_DUAL_ROLE is not set\n# CONFIG_USB_DWC2_HOST is not set\n# CONFIG_USB_DWC2_PERIPHERAL is not set\n# CONFIG_USB_DWC2_TRACK_MISSED_SOFS is not set\n# CONFIG_USB_DWC3 is not set\n# CONFIG_USB_DWC3_EXYNOS is not set\n# CONFIG_USB_DWC3_HAPS is not set\n# CONFIG_USB_DWC3_KEYSTONE is not set\n# CONFIG_USB_DWC3_OF_SIMPLE is not set\n# CONFIG_USB_DWC3_PCI is not set\n# CONFIG_USB_DWC3_QCOM is not set\n# CONFIG_USB_DWC3_ULPI is not set\n# CONFIG_USB_DYNAMIC_MINORS is not set\n# CONFIG_USB_EG20T is not set\n# CONFIG_USB_EHCI_ATH79 is not set\n# CONFIG_USB_EHCI_FSL is not set\n# CONFIG_USB_EHCI_HCD is not set\n# CONFIG_USB_EHCI_HCD_AT91 is not set\n# CONFIG_USB_EHCI_HCD_OMAP is not set\n# CONFIG_USB_EHCI_HCD_PPC_OF is not set\n# CONFIG_USB_EHCI_MSM is not set\n# CONFIG_USB_EHCI_MV is not set\nCONFIG_USB_EHCI_ROOT_HUB_TT=y\nCONFIG_USB_EHCI_TT_NEWSCHED=y\n# CONFIG_USB_EHSET_TEST_FIXTURE is not set\n# CONFIG_USB_EMI26 is not set\n# CONFIG_USB_EMI62 is not set\n# CONFIG_USB_EPSON2888 is not set\n# CONFIG_USB_ETH is not set\n# CONFIG_USB_EZUSB_FX2 is not set\n# CONFIG_USB_FEW_INIT_RETRIES is not set\n# CONFIG_USB_FOTG210_HCD is not set\n# CONFIG_USB_FOTG210_UDC is not set\n# CONFIG_USB_FSL_USB2 is not set\n# CONFIG_USB_FTDI_ELAN is not set\n# CONFIG_USB_FUNCTIONFS is not set\n# CONFIG_USB_FUSB300 is not set\n# CONFIG_USB_GADGET is not set\n# CONFIG_USB_GADGETFS is not set\n# CONFIG_USB_GADGET_DEBUG is not set\n# CONFIG_USB_GADGET_DEBUG_FILES is not set\n# CONFIG_USB_GADGET_DEBUG_FS is not set\nCONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2\nCONFIG_USB_GADGET_VBUS_DRAW=2\n# CONFIG_USB_GADGET_XILINX is not set\n# CONFIG_USB_GL860 is not set\n# CONFIG_USB_GOKU is not set\n# CONFIG_USB_GPIO_VBUS is not set\n# CONFIG_USB_GR_UDC is not set\n# CONFIG_USB_GSPCA is not set\n# CONFIG_USB_GSPCA_BENQ is not set\n# CONFIG_USB_GSPCA_CONEX is not set\n# CONFIG_USB_GSPCA_CPIA1 is not set\n# CONFIG_USB_GSPCA_DTCS033 is not set\n# CONFIG_USB_GSPCA_ETOMS is not set\n# CONFIG_USB_GSPCA_FINEPIX is not set\n# CONFIG_USB_GSPCA_JEILINJ is not set\n# CONFIG_USB_GSPCA_JL2005BCD is not set\n# CONFIG_USB_GSPCA_KINECT is not set\n# CONFIG_USB_GSPCA_KONICA is not set\n# CONFIG_USB_GSPCA_MARS is not set\n# CONFIG_USB_GSPCA_MR97310A is not set\n# CONFIG_USB_GSPCA_NW80X is not set\n# CONFIG_USB_GSPCA_OV519 is not set\n# CONFIG_USB_GSPCA_OV534 is not set\n# CONFIG_USB_GSPCA_OV534_9 is not set\n# CONFIG_USB_GSPCA_PAC207 is not set\n# CONFIG_USB_GSPCA_PAC7302 is not set\n# CONFIG_USB_GSPCA_PAC7311 is not set\n# CONFIG_USB_GSPCA_SE401 is not set\n# CONFIG_USB_GSPCA_SN9C2028 is not set\n# CONFIG_USB_GSPCA_SN9C20X is not set\n# CONFIG_USB_GSPCA_SONIXB is not set\n# CONFIG_USB_GSPCA_SONIXJ is not set\n# CONFIG_USB_GSPCA_SPCA1528 is not set\n# CONFIG_USB_GSPCA_SPCA500 is not set\n# CONFIG_USB_GSPCA_SPCA501 is not set\n# CONFIG_USB_GSPCA_SPCA505 is not set\n# CONFIG_USB_GSPCA_SPCA506 is not set\n# CONFIG_USB_GSPCA_SPCA508 is not set\n# CONFIG_USB_GSPCA_SPCA561 is not set\n# CONFIG_USB_GSPCA_SQ905 is not set\n# CONFIG_USB_GSPCA_SQ905C is not set\n# CONFIG_USB_GSPCA_SQ930X is not set\n# CONFIG_USB_GSPCA_STK014 is not set\n# CONFIG_USB_GSPCA_STK1135 is not set\n# CONFIG_USB_GSPCA_STV0680 is not set\n# CONFIG_USB_GSPCA_SUNPLUS is not set\n# CONFIG_USB_GSPCA_T613 is not set\n# CONFIG_USB_GSPCA_TOPRO is not set\n# CONFIG_USB_GSPCA_TOUPTEK is not set\n# CONFIG_USB_GSPCA_TV8532 is not set\n# CONFIG_USB_GSPCA_VC032X is not set\n# CONFIG_USB_GSPCA_VICAM is not set\n# CONFIG_USB_GSPCA_XIRLINK_CIT is not set\n# CONFIG_USB_GSPCA_ZC3XX is not set\n# CONFIG_USB_G_ACM_MS is not set\n# CONFIG_USB_G_DBGP is not set\n# CONFIG_USB_G_HID is not set\n# CONFIG_USB_G_MULTI is not set\n# CONFIG_USB_G_NCM is not set\n# CONFIG_USB_G_NOKIA is not set\n# CONFIG_USB_G_PRINTER is not set\n# CONFIG_USB_G_SERIAL is not set\n# CONFIG_USB_G_WEBCAM is not set\n# CONFIG_USB_HACKRF is not set\n# CONFIG_USB_HCD_TEST_MODE is not set\n# CONFIG_USB_HID is not set\n# CONFIG_USB_HIDDEV is not set\n# CONFIG_USB_HSIC_USB3503 is not set\n# CONFIG_USB_HSIC_USB4604 is not set\n# CONFIG_USB_HSO is not set\n# CONFIG_USB_HUB_USB251XB is not set\n# CONFIG_USB_HWA_HCD is not set\n# CONFIG_USB_IDMOUSE is not set\n# CONFIG_USB_IMX21_HCD is not set\n# CONFIG_USB_IOWARRIOR is not set\n# CONFIG_USB_IPHETH is not set\n# CONFIG_USB_ISIGHTFW is not set\n# CONFIG_USB_ISP116X_HCD is not set\n# CONFIG_USB_ISP1301 is not set\n# CONFIG_USB_ISP1362_HCD is not set\n# CONFIG_USB_ISP1760 is not set\n# CONFIG_USB_ISP1760_HCD is not set\n# CONFIG_USB_KAWETH is not set\n# CONFIG_USB_KBD is not set\n# CONFIG_USB_KC2190 is not set\n# CONFIG_USB_LAN78XX is not set\n# CONFIG_USB_LCD is not set\n# CONFIG_USB_LD is not set\n# CONFIG_USB_LED is not set\n# CONFIG_USB_LEDS_TRIGGER_USBPORT is not set\n# CONFIG_USB_LED_TRIG is not set\n# CONFIG_USB_LEGOTOWER is not set\n# CONFIG_USB_LGM_PHY is not set\n# CONFIG_USB_LINK_LAYER_TEST is not set\n# CONFIG_USB_M5602 is not set\n# CONFIG_USB_M66592 is not set\n# CONFIG_USB_MASS_STORAGE is not set\n# CONFIG_USB_MAX3420_UDC is not set\n# CONFIG_USB_MAX3421_HCD is not set\n# CONFIG_USB_MDC800 is not set\n# CONFIG_USB_MICROTEK is not set\n# CONFIG_USB_MIDI_GADGET is not set\n# CONFIG_USB_MON is not set\n# CONFIG_USB_MOUSE is not set\n# CONFIG_USB_MSI2500 is not set\n# CONFIG_USB_MSM_OTG is not set\n# CONFIG_USB_MTU3 is not set\n# CONFIG_USB_MUSB_HDRC is not set\n# CONFIG_USB_MV_U3D is not set\n# CONFIG_USB_MV_UDC is not set\n# CONFIG_USB_MXS_PHY is not set\n# CONFIG_USB_NET2272 is not set\n# CONFIG_USB_NET2280 is not set\n# CONFIG_USB_NET_AQC111 is not set\n# CONFIG_USB_NET_AX88179_178A is not set\n# CONFIG_USB_NET_AX8817X is not set\n# CONFIG_USB_NET_CDCETHER is not set\n# CONFIG_USB_NET_CDC_EEM is not set\n# CONFIG_USB_NET_CDC_MBIM is not set\n# CONFIG_USB_NET_CDC_NCM is not set\n# CONFIG_USB_NET_CDC_SUBSET is not set\n# CONFIG_USB_NET_CH9200 is not set\n# CONFIG_USB_NET_CX82310_ETH is not set\n# CONFIG_USB_NET_DM9601 is not set\n# CONFIG_USB_NET_DRIVERS is not set\n# CONFIG_USB_NET_GL620A is not set\n# CONFIG_USB_NET_HUAWEI_CDC_NCM is not set\n# CONFIG_USB_NET_INT51X1 is not set\n# CONFIG_USB_NET_KALMIA is not set\n# CONFIG_USB_NET_MCS7830 is not set\n# CONFIG_USB_NET_NET1080 is not set\n# CONFIG_USB_NET_PLUSB is not set\n# CONFIG_USB_NET_QMI_WWAN is not set\n# CONFIG_USB_NET_RNDIS_HOST is not set\n# CONFIG_USB_NET_RNDIS_WLAN is not set\n# CONFIG_USB_NET_SMSC75XX is not set\n# CONFIG_USB_NET_SMSC95XX is not set\n# CONFIG_USB_NET_SR9700 is not set\n# CONFIG_USB_NET_SR9800 is not set\n# CONFIG_USB_NET_ZAURUS is not set\n# CONFIG_USB_OHCI_HCD is not set\n# CONFIG_USB_OHCI_HCD_PCI is not set\n# CONFIG_USB_OHCI_HCD_PPC_OF is not set\n# CONFIG_USB_OHCI_HCD_PPC_OF_BE is not set\n# CONFIG_USB_OHCI_HCD_PPC_OF_LE is not set\n# CONFIG_USB_OHCI_HCD_SSB is not set\nCONFIG_USB_OHCI_LITTLE_ENDIAN=y\n# CONFIG_USB_OTG is not set\n# CONFIG_USB_OTG_BLACKLIST_HUB is not set\n# CONFIG_USB_OTG_DISABLE_EXTERNAL_HUB is not set\n# CONFIG_USB_OTG_FSM is not set\n# CONFIG_USB_OTG_PRODUCTLIST is not set\n# CONFIG_USB_OTG_WHITELIST is not set\n# CONFIG_USB_OXU210HP_HCD is not set\n# CONFIG_USB_PCI is not set\n# CONFIG_USB_PEGASUS is not set\n# CONFIG_USB_PHY is not set\n# CONFIG_USB_PRINTER is not set\n# CONFIG_USB_PWC_INPUT_EVDEV is not set\n# CONFIG_USB_PXA27X is not set\n# CONFIG_USB_R8A66597 is not set\n# CONFIG_USB_R8A66597_HCD is not set\n# CONFIG_USB_RAW_GADGET is not set\n# CONFIG_USB_RCAR_PHY is not set\n# CONFIG_USB_RENESAS_USBHS is not set\n# CONFIG_USB_RIO500 is not set\n# CONFIG_USB_ROLES_INTEL_XHCI is not set\n# CONFIG_USB_ROLE_SWITCH is not set\n# CONFIG_USB_RTL8150 is not set\n# CONFIG_USB_RTL8152 is not set\n# CONFIG_USB_S2255 is not set\n# CONFIG_USB_SERIAL is not set\n# CONFIG_USB_SERIAL_AIRCABLE is not set\n# CONFIG_USB_SERIAL_ARK3116 is not set\n# CONFIG_USB_SERIAL_BELKIN is not set\n# CONFIG_USB_SERIAL_CH341 is not set\n# CONFIG_USB_SERIAL_CP210X is not set\n# CONFIG_USB_SERIAL_CYBERJACK is not set\n# CONFIG_USB_SERIAL_CYPRESS_M8 is not set\n# CONFIG_USB_SERIAL_DEBUG is not set\n# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set\n# CONFIG_USB_SERIAL_EDGEPORT is not set\n# CONFIG_USB_SERIAL_EDGEPORT_TI is not set\n# CONFIG_USB_SERIAL_EMPEG is not set\n# CONFIG_USB_SERIAL_F81232 is not set\n# CONFIG_USB_SERIAL_F8153X is not set\n# CONFIG_USB_SERIAL_FTDI_SIO is not set\n# CONFIG_USB_SERIAL_GARMIN is not set\nCONFIG_USB_SERIAL_GENERIC=y\n# CONFIG_USB_SERIAL_IPAQ is not set\n# CONFIG_USB_SERIAL_IPW is not set\n# CONFIG_USB_SERIAL_IR is not set\n# CONFIG_USB_SERIAL_IUU is not set\n# CONFIG_USB_SERIAL_KEYSPAN is not set\nCONFIG_USB_SERIAL_KEYSPAN_MPR=y\n# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set\nCONFIG_USB_SERIAL_KEYSPAN_USA18X=y\nCONFIG_USB_SERIAL_KEYSPAN_USA19=y\nCONFIG_USB_SERIAL_KEYSPAN_USA19QI=y\nCONFIG_USB_SERIAL_KEYSPAN_USA19QW=y\nCONFIG_USB_SERIAL_KEYSPAN_USA19W=y\nCONFIG_USB_SERIAL_KEYSPAN_USA28=y\nCONFIG_USB_SERIAL_KEYSPAN_USA28X=y\nCONFIG_USB_SERIAL_KEYSPAN_USA28XA=y\nCONFIG_USB_SERIAL_KEYSPAN_USA28XB=y\nCONFIG_USB_SERIAL_KEYSPAN_USA49W=y\nCONFIG_USB_SERIAL_KEYSPAN_USA49WLC=y\n# CONFIG_USB_SERIAL_KLSI is not set\n# CONFIG_USB_SERIAL_KOBIL_SCT is not set\n# CONFIG_USB_SERIAL_MCT_U232 is not set\n# CONFIG_USB_SERIAL_METRO is not set\n# CONFIG_USB_SERIAL_MOS7715_PARPORT is not set\n# CONFIG_USB_SERIAL_MOS7720 is not set\n# CONFIG_USB_SERIAL_MOS7840 is not set\n# CONFIG_USB_SERIAL_MXUPORT is not set\n# CONFIG_USB_SERIAL_NAVMAN is not set\n# CONFIG_USB_SERIAL_OMNINET is not set\n# CONFIG_USB_SERIAL_OPTICON is not set\n# CONFIG_USB_SERIAL_OPTION is not set\n# CONFIG_USB_SERIAL_OTI6858 is not set\n# CONFIG_USB_SERIAL_PL2303 is not set\n# CONFIG_USB_SERIAL_QCAUX is not set\n# CONFIG_USB_SERIAL_QT2 is not set\n# CONFIG_USB_SERIAL_QUALCOMM is not set\n# CONFIG_USB_SERIAL_SAFE is not set\nCONFIG_USB_SERIAL_SAFE_PADDED=y\n# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set\n# CONFIG_USB_SERIAL_SIMPLE is not set\n# CONFIG_USB_SERIAL_SPCP8X5 is not set\n# CONFIG_USB_SERIAL_SSU100 is not set\n# CONFIG_USB_SERIAL_SYMBOL is not set\n# CONFIG_USB_SERIAL_TI is not set\n# CONFIG_USB_SERIAL_UPD78F0730 is not set\n# CONFIG_USB_SERIAL_VISOR is not set\n# CONFIG_USB_SERIAL_WHITEHEAT is not set\n# CONFIG_USB_SERIAL_WISHBONE is not set\n# CONFIG_USB_SERIAL_XIRCOM is not set\n# CONFIG_USB_SERIAL_XSENS_MT is not set\n# CONFIG_USB_SEVSEG is not set\n# CONFIG_USB_SIERRA_NET is not set\n# CONFIG_USB_SISUSBVGA is not set\n# CONFIG_USB_SL811_HCD is not set\n# CONFIG_USB_SNP_UDC_PLAT is not set\n# CONFIG_USB_SPEEDTOUCH is not set\n# CONFIG_USB_STKWEBCAM is not set\n# CONFIG_USB_STORAGE is not set\n# CONFIG_USB_STORAGE_ALAUDA is not set\n# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set\n# CONFIG_USB_STORAGE_DATAFAB is not set\n# CONFIG_USB_STORAGE_DEBUG is not set\n# CONFIG_USB_STORAGE_ENE_UB6250 is not set\n# CONFIG_USB_STORAGE_FREECOM is not set\n# CONFIG_USB_STORAGE_ISD200 is not set\n# CONFIG_USB_STORAGE_JUMPSHOT is not set\n# CONFIG_USB_STORAGE_KARMA is not set\n# CONFIG_USB_STORAGE_ONETOUCH is not set\n# CONFIG_USB_STORAGE_REALTEK is not set\n# CONFIG_USB_STORAGE_SDDR09 is not set\n# CONFIG_USB_STORAGE_SDDR55 is not set\n# CONFIG_USB_STORAGE_USBAT is not set\n# CONFIG_USB_STV06XX is not set\n# CONFIG_USB_SUPPORT is not set\n# CONFIG_USB_SWITCH_FSA9480 is not set\n# CONFIG_USB_TEST is not set\n# CONFIG_USB_TMC is not set\n# CONFIG_USB_TRANCEVIBRATOR is not set\n# CONFIG_USB_UAS is not set\n# CONFIG_USB_UEAGLEATM is not set\n# CONFIG_USB_ULPI is not set\n# CONFIG_USB_ULPI_BUS is not set\n# CONFIG_USB_USBNET is not set\n# CONFIG_USB_USS720 is not set\n# CONFIG_USB_VIDEO_CLASS is not set\nCONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y\n# CONFIG_USB_VL600 is not set\n# CONFIG_USB_WDM is not set\n# CONFIG_USB_WHCI_HCD is not set\n# CONFIG_USB_WUSB is not set\n# CONFIG_USB_WUSB_CBAF is not set\n# CONFIG_USB_XHCI_DBGCAP is not set\n# CONFIG_USB_XHCI_HCD is not set\n# CONFIG_USB_XHCI_MVEBU is not set\n# CONFIG_USB_XHCI_PCI_RENESAS is not set\n# CONFIG_USB_XUSBATM is not set\n# CONFIG_USB_YUREX is not set\n# CONFIG_USB_ZD1201 is not set\n# CONFIG_USB_ZERO is not set\n# CONFIG_USB_ZR364XX is not set\n# CONFIG_USELIB is not set\n# CONFIG_USERFAULTFD is not set\n# CONFIG_USERIO is not set\n# CONFIG_USE_OF is not set\n# CONFIG_UTS_NS is not set\n# CONFIG_UWB is not set\n# CONFIG_U_SERIAL_CONSOLE is not set\n# CONFIG_V4L_MEM2MEM_DRIVERS is not set\n# CONFIG_V4L_PLATFORM_DRIVERS is not set\n# CONFIG_V4L_TEST_DRIVERS is not set\n# CONFIG_VALIDATE_FS_PARSER is not set\n# CONFIG_VBOXGUEST is not set\n# CONFIG_VCNL3020 is not set\n# CONFIG_VCNL4000 is not set\n# CONFIG_VCNL4035 is not set\n# CONFIG_VDPA is not set\nCONFIG_VDSO=y\n# CONFIG_VEML6030 is not set\n# CONFIG_VEML6070 is not set\n# CONFIG_VETH is not set\n# CONFIG_VEXPRESS_CONFIG is not set\n# CONFIG_VF610_ADC is not set\n# CONFIG_VF610_DAC is not set\n# CONFIG_VFAT_FS is not set\n# CONFIG_VFIO is not set\n# CONFIG_VGASTATE is not set\n# CONFIG_VGA_ARB is not set\n# CONFIG_VGA_SWITCHEROO is not set\n# CONFIG_VHOST_CROSS_ENDIAN_LEGACY is not set\nCONFIG_VHOST_MENU=y\n# CONFIG_VHOST_NET is not set\n# CONFIG_VHOST_VSOCK is not set\n# CONFIG_VIA_RHINE is not set\n# CONFIG_VIA_VELOCITY is not set\n# CONFIG_VIDEO_AD5820 is not set\n# CONFIG_VIDEO_AD9389B is not set\n# CONFIG_VIDEO_ADP1653 is not set\n# CONFIG_VIDEO_ADV7170 is not set\n# CONFIG_VIDEO_ADV7175 is not set\n# CONFIG_VIDEO_ADV7180 is not set\n# CONFIG_VIDEO_ADV7183 is not set\n# CONFIG_VIDEO_ADV7343 is not set\n# CONFIG_VIDEO_ADV7393 is not set\n# CONFIG_VIDEO_ADV748X is not set\n# CONFIG_VIDEO_ADV7511 is not set\n# CONFIG_VIDEO_ADV7604 is not set\n# CONFIG_VIDEO_ADV7842 is not set\n# CONFIG_VIDEO_ADV_DEBUG is not set\n# CONFIG_VIDEO_AK7375 is not set\n# CONFIG_VIDEO_AK881X is not set\n# CONFIG_VIDEO_AM437X_VPFE is not set\n# CONFIG_VIDEO_ASPEED is not set\n# CONFIG_VIDEO_ATMEL_ISC is not set\n# CONFIG_VIDEO_ATMEL_ISI is not set\n# CONFIG_VIDEO_AU0828 is not set\n# CONFIG_VIDEO_BT819 is not set\n# CONFIG_VIDEO_BT848 is not set\n# CONFIG_VIDEO_BT856 is not set\n# CONFIG_VIDEO_BT866 is not set\n# CONFIG_VIDEO_CADENCE is not set\n# CONFIG_VIDEO_CAFE_CCIC is not set\n# CONFIG_VIDEO_CS3308 is not set\n# CONFIG_VIDEO_CS5345 is not set\n# CONFIG_VIDEO_CS53L32A is not set\n# CONFIG_VIDEO_CX231XX is not set\n# CONFIG_VIDEO_CX2341X is not set\n# CONFIG_VIDEO_CX25840 is not set\n# CONFIG_VIDEO_CX88 is not set\n# CONFIG_VIDEO_DEV is not set\n# CONFIG_VIDEO_DM6446_CCDC is not set\n# CONFIG_VIDEO_DT3155 is not set\n# CONFIG_VIDEO_DW9714 is not set\n# CONFIG_VIDEO_DW9768 is not set\n# CONFIG_VIDEO_DW9807_VCM is not set\n# CONFIG_VIDEO_EM28XX is not set\n# CONFIG_VIDEO_ET8EK8 is not set\n# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set\n# CONFIG_VIDEO_GO7007 is not set\n# CONFIG_VIDEO_GS1662 is not set\n# CONFIG_VIDEO_HDPVR is not set\n# CONFIG_VIDEO_HEXIUM_GEMINI is not set\n# CONFIG_VIDEO_HEXIUM_ORION is not set\n# CONFIG_VIDEO_HI556 is not set\n# CONFIG_VIDEO_I2C is not set\n# CONFIG_VIDEO_IMX214 is not set\n# CONFIG_VIDEO_IMX219 is not set\n# CONFIG_VIDEO_IMX258 is not set\n# CONFIG_VIDEO_IMX274 is not set\n# CONFIG_VIDEO_IMX290 is not set\n# CONFIG_VIDEO_IMX319 is not set\n# CONFIG_VIDEO_IMX355 is not set\n# CONFIG_VIDEO_IMX477 is not set\n# CONFIG_VIDEO_IRS1125 is not set\n# CONFIG_VIDEO_IR_I2C is not set\n# CONFIG_VIDEO_IVTV is not set\n# CONFIG_VIDEO_KS0127 is not set\n# CONFIG_VIDEO_LM3560 is not set\n# CONFIG_VIDEO_LM3646 is not set\n# CONFIG_VIDEO_M52790 is not set\n# CONFIG_VIDEO_M5MOLS is not set\n# CONFIG_VIDEO_MAX9286 is not set\n# CONFIG_VIDEO_ML86V7667 is not set\n# CONFIG_VIDEO_MSP3400 is not set\n# CONFIG_VIDEO_MT9M001 is not set\n# CONFIG_VIDEO_MT9M032 is not set\n# CONFIG_VIDEO_MT9M111 is not set\n# CONFIG_VIDEO_MT9P031 is not set\n# CONFIG_VIDEO_MT9T001 is not set\n# CONFIG_VIDEO_MT9T112 is not set\n# CONFIG_VIDEO_MT9V011 is not set\n# CONFIG_VIDEO_MT9V032 is not set\n# CONFIG_VIDEO_MT9V111 is not set\n# CONFIG_VIDEO_MUX is not set\n# CONFIG_VIDEO_MXB is not set\n# CONFIG_VIDEO_NOON010PC30 is not set\n# CONFIG_VIDEO_OMAP2_VOUT is not set\n# CONFIG_VIDEO_OV13858 is not set\n# CONFIG_VIDEO_OV2640 is not set\n# CONFIG_VIDEO_OV2659 is not set\n# CONFIG_VIDEO_OV2680 is not set\n# CONFIG_VIDEO_OV2685 is not set\n# CONFIG_VIDEO_OV2740 is not set\n# CONFIG_VIDEO_OV5640 is not set\n# CONFIG_VIDEO_OV5645 is not set\n# CONFIG_VIDEO_OV5647 is not set\n# CONFIG_VIDEO_OV5670 is not set\n# CONFIG_VIDEO_OV5675 is not set\n# CONFIG_VIDEO_OV5695 is not set\n# CONFIG_VIDEO_OV6650 is not set\n# CONFIG_VIDEO_OV7251 is not set\n# CONFIG_VIDEO_OV7640 is not set\n# CONFIG_VIDEO_OV7670 is not set\n# CONFIG_VIDEO_OV772X is not set\n# CONFIG_VIDEO_OV7740 is not set\n# CONFIG_VIDEO_OV8856 is not set\n# CONFIG_VIDEO_OV9281 is not set\n# CONFIG_VIDEO_OV9640 is not set\n# CONFIG_VIDEO_OV9650 is not set\n# CONFIG_VIDEO_PVRUSB2 is not set\n# CONFIG_VIDEO_RDACM20 is not set\n# CONFIG_VIDEO_RJ54N1 is not set\n# CONFIG_VIDEO_S5C73M3 is not set\n# CONFIG_VIDEO_S5K4ECGX is not set\n# CONFIG_VIDEO_S5K5BAF is not set\n# CONFIG_VIDEO_S5K6A3 is not set\n# CONFIG_VIDEO_S5K6AA is not set\n# CONFIG_VIDEO_SAA6588 is not set\n# CONFIG_VIDEO_SAA6752HS is not set\n# CONFIG_VIDEO_SAA7110 is not set\n# CONFIG_VIDEO_SAA711X is not set\n# CONFIG_VIDEO_SAA7127 is not set\n# CONFIG_VIDEO_SAA7134 is not set\n# CONFIG_VIDEO_SAA717X is not set\n# CONFIG_VIDEO_SAA7185 is not set\n# CONFIG_VIDEO_SH_MOBILE_CEU is not set\n# CONFIG_VIDEO_SMIAPP is not set\n# CONFIG_VIDEO_SONY_BTF_MPX is not set\n# CONFIG_VIDEO_SR030PC30 is not set\n# CONFIG_VIDEO_STK1160_COMMON is not set\n# CONFIG_VIDEO_ST_MIPID02 is not set\n# CONFIG_VIDEO_TC358743 is not set\n# CONFIG_VIDEO_TDA1997X is not set\n# CONFIG_VIDEO_TDA7432 is not set\n# CONFIG_VIDEO_TDA9840 is not set\n# CONFIG_VIDEO_TEA6415C is not set\n# CONFIG_VIDEO_TEA6420 is not set\n# CONFIG_VIDEO_THS7303 is not set\n# CONFIG_VIDEO_THS8200 is not set\n# CONFIG_VIDEO_TIMBERDALE is not set\n# CONFIG_VIDEO_TLV320AIC23B is not set\n# CONFIG_VIDEO_TM6000 is not set\n# CONFIG_VIDEO_TVAUDIO is not set\n# CONFIG_VIDEO_TVP514X is not set\n# CONFIG_VIDEO_TVP5150 is not set\n# CONFIG_VIDEO_TVP7002 is not set\n# CONFIG_VIDEO_TW2804 is not set\n# CONFIG_VIDEO_TW9903 is not set\n# CONFIG_VIDEO_TW9906 is not set\n# CONFIG_VIDEO_TW9910 is not set\n# CONFIG_VIDEO_UDA1342 is not set\n# CONFIG_VIDEO_UPD64031A is not set\n# CONFIG_VIDEO_UPD64083 is not set\n# CONFIG_VIDEO_USBTV is not set\n# CONFIG_VIDEO_USBVISION is not set\n# CONFIG_VIDEO_V4L2 is not set\n# CONFIG_VIDEO_VP27SMPX is not set\n# CONFIG_VIDEO_VPX3220 is not set\n# CONFIG_VIDEO_VS6624 is not set\n# CONFIG_VIDEO_WM8739 is not set\n# CONFIG_VIDEO_WM8775 is not set\n# CONFIG_VIDEO_XILINX is not set\n# CONFIG_VIDEO_ZORAN is not set\n# CONFIG_VIRTIO_BALLOON is not set\n# CONFIG_VIRTIO_BLK_SCSI is not set\n# CONFIG_VIRTIO_CONSOLE is not set\n# CONFIG_VIRTIO_FS is not set\n# CONFIG_VIRTIO_INPUT is not set\nCONFIG_VIRTIO_MENU=y\n# CONFIG_VIRTIO_MMIO is not set\n# CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES is not set\n# CONFIG_VIRTIO_PCI is not set\n# CONFIG_VIRTUALIZATION is not set\n# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set\n# CONFIG_VIRT_DRIVERS is not set\nCONFIG_VIRT_TO_BUS=y\n# CONFIG_VITESSE_PHY is not set\n# CONFIG_VL53L0X_I2C is not set\n# CONFIG_VL6180 is not set\nCONFIG_VLAN_8021Q=y\n# CONFIG_VLAN_8021Q_GVRP is not set\n# CONFIG_VLAN_8021Q_MVRP is not set\n# CONFIG_VME_BUS is not set\n# CONFIG_VMSPLIT_1G is not set\n# CONFIG_VMSPLIT_2G is not set\n# CONFIG_VMSPLIT_2G_OPT is not set\nCONFIG_VMSPLIT_3G=y\n# CONFIG_VMSPLIT_3G_OPT is not set\n# CONFIG_VMWARE_PVSCSI is not set\n# CONFIG_VMXNET3 is not set\n# CONFIG_VM_EVENT_COUNTERS is not set\n# CONFIG_VOP_BUS is not set\n# CONFIG_VORTEX is not set\n# CONFIG_VSOCKETS is not set\n# CONFIG_VSOCKETS_DIAG is not set\n# CONFIG_VT is not set\n# CONFIG_VT6655 is not set\n# CONFIG_VT6656 is not set\n# CONFIG_VXFS_FS is not set\n# CONFIG_VXGE is not set\n# CONFIG_VXLAN is not set\n# CONFIG_VZ89X is not set\n# CONFIG_W1 is not set\n# CONFIG_W1_CON is not set\n# CONFIG_W1_MASTER_DS1WM is not set\n# CONFIG_W1_MASTER_DS2482 is not set\n# CONFIG_W1_MASTER_DS2490 is not set\n# CONFIG_W1_MASTER_GPIO is not set\n# CONFIG_W1_MASTER_MATROX is not set\n# CONFIG_W1_MASTER_SGI is not set\n# CONFIG_W1_SLAVE_DS2405 is not set\n# CONFIG_W1_SLAVE_DS2406 is not set\n# CONFIG_W1_SLAVE_DS2408 is not set\n# CONFIG_W1_SLAVE_DS2413 is not set\n# CONFIG_W1_SLAVE_DS2423 is not set\n# CONFIG_W1_SLAVE_DS2430 is not set\n# CONFIG_W1_SLAVE_DS2431 is not set\n# CONFIG_W1_SLAVE_DS2433 is not set\n# CONFIG_W1_SLAVE_DS2438 is not set\n# CONFIG_W1_SLAVE_DS250X is not set\n# CONFIG_W1_SLAVE_DS2780 is not set\n# CONFIG_W1_SLAVE_DS2781 is not set\n# CONFIG_W1_SLAVE_DS2805 is not set\n# CONFIG_W1_SLAVE_DS28E04 is not set\n# CONFIG_W1_SLAVE_DS28E17 is not set\n# CONFIG_W1_SLAVE_SMEM is not set\n# CONFIG_W1_SLAVE_THERM is not set\n# CONFIG_W83627HF_WDT is not set\n# CONFIG_W83877F_WDT is not set\n# CONFIG_W83977F_WDT is not set\n# CONFIG_WAN is not set\n# CONFIG_WANXL is not set\n# CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set\nCONFIG_WATCHDOG=y\n# CONFIG_WATCHDOG_CORE is not set\nCONFIG_WATCHDOG_HANDLE_BOOT_ENABLED=y\n# CONFIG_WATCHDOG_NOWAYOUT is not set\nCONFIG_WATCHDOG_OPEN_TIMEOUT=0\n# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set\n# CONFIG_WATCHDOG_SYSFS is not set\n# CONFIG_WATCH_QUEUE is not set\n# CONFIG_WD80x3 is not set\n# CONFIG_WDAT_WDT is not set\n# CONFIG_WDTPCI is not set\nCONFIG_WEXT_CORE=y\nCONFIG_WEXT_PRIV=y\nCONFIG_WEXT_PROC=y\nCONFIG_WEXT_SPY=y\nCONFIG_WILINK_PLATFORM_DATA=y\n# CONFIG_WIMAX is not set\n# CONFIG_WIREGUARD is not set\nCONFIG_WIRELESS=y\nCONFIG_WIRELESS_EXT=y\n# CONFIG_WIRELESS_WDS is not set\n# CONFIG_WIZNET_W5100 is not set\n# CONFIG_WIZNET_W5300 is not set\n# CONFIG_WL1251 is not set\n# CONFIG_WL12XX is not set\n# CONFIG_WL18XX is not set\nCONFIG_WLAN=y\n# CONFIG_WLAN_VENDOR_ADMTEK is not set\n# CONFIG_WLAN_VENDOR_ATH is not set\n# CONFIG_WLAN_VENDOR_ATMEL is not set\n# CONFIG_WLAN_VENDOR_BROADCOM is not set\n# CONFIG_WLAN_VENDOR_CISCO is not set\n# CONFIG_WLAN_VENDOR_INTEL is not set\n# CONFIG_WLAN_VENDOR_INTERSIL is not set\n# CONFIG_WLAN_VENDOR_MARVELL is not set\n# CONFIG_WLAN_VENDOR_MEDIATEK is not set\n# CONFIG_WLAN_VENDOR_MICROCHIP is not set\n# CONFIG_WLAN_VENDOR_QUANTENNA is not set\n# CONFIG_WLAN_VENDOR_RALINK is not set\n# CONFIG_WLAN_VENDOR_REALTEK is not set\n# CONFIG_WLAN_VENDOR_RSI is not set\n# CONFIG_WLAN_VENDOR_ST is not set\n# CONFIG_WLAN_VENDOR_TI is not set\n# CONFIG_WLAN_VENDOR_ZYDAS is not set\n# CONFIG_WLCORE is not set\nCONFIG_WQ_POWER_EFFICIENT_DEFAULT=y\n# CONFIG_WQ_WATCHDOG is not set\n# CONFIG_WW_MUTEX_SELFTEST is not set\n# CONFIG_X25 is not set\n# CONFIG_X509_CERTIFICATE_PARSER is not set\n# CONFIG_X86_PKG_TEMP_THERMAL is not set\nCONFIG_X86_SYSFB=y\n# CONFIG_XDP_SOCKETS is not set\n# CONFIG_XEN is not set\n# CONFIG_XEN_GRANT_DMA_ALLOC is not set\n# CONFIG_XEN_PVCALLS_FRONTEND is not set\nCONFIG_XEN_SCRUB_PAGES_DEFAULT=y\nCONFIG_XFRM=y\n# CONFIG_XFRM_INTERFACE is not set\n# CONFIG_XFRM_IPCOMP is not set\n# CONFIG_XFRM_MIGRATE is not set\n# CONFIG_XFRM_STATISTICS is not set\n# CONFIG_XFRM_SUB_POLICY is not set\n# CONFIG_XFRM_USER is not set\n# CONFIG_XFS_DEBUG is not set\n# CONFIG_XFS_FS is not set\n# CONFIG_XFS_ONLINE_SCRUB is not set\n# CONFIG_XFS_POSIX_ACL is not set\n# CONFIG_XFS_QUOTA is not set\n# CONFIG_XFS_RT is not set\n# CONFIG_XFS_SUPPORT_V4 is not set\n# CONFIG_XFS_WARN is not set\n# CONFIG_XILINX_AXI_EMAC is not set\n# CONFIG_XILINX_DMA is not set\n# CONFIG_XILINX_EMACLITE is not set\n# CONFIG_XILINX_GMII2RGMII is not set\n# CONFIG_XILINX_LL_TEMAC is not set\n# CONFIG_XILINX_SDFEC is not set\n# CONFIG_XILINX_VCU is not set\n# CONFIG_XILINX_WATCHDOG is not set\n# CONFIG_XILINX_XADC is not set\n# CONFIG_XILINX_ZYNQMP_DMA is not set\n# CONFIG_XILINX_ZYNQMP_DPDMA is not set\n# CONFIG_XILLYBUS is not set\n# CONFIG_XIL_AXIS_FIFO is not set\n# CONFIG_XIP_KERNEL is not set\n# CONFIG_XMON is not set\nCONFIG_XZ_DEC=y\n# CONFIG_XZ_DEC_ARM is not set\n# CONFIG_XZ_DEC_ARMTHUMB is not set\n# CONFIG_XZ_DEC_BCJ is not set\n# CONFIG_XZ_DEC_IA64 is not set\n# CONFIG_XZ_DEC_POWERPC is not set\n# CONFIG_XZ_DEC_SPARC is not set\n# CONFIG_XZ_DEC_TEST is not set\n# CONFIG_XZ_DEC_X86 is not set\n# CONFIG_YAM is not set\n# CONFIG_YELLOWFIN is not set\n# CONFIG_YENTA is not set\n# CONFIG_YENTA_O2 is not set\n# CONFIG_YENTA_RICOH is not set\n# CONFIG_YENTA_TI is not set\n# CONFIG_YENTA_TOSHIBA is not set\n# CONFIG_ZBUD is not set\n# CONFIG_ZD1211RW is not set\n# CONFIG_ZD1211RW_DEBUG is not set\n# CONFIG_ZEROPLUS_FF is not set\n# CONFIG_ZIIRAVE_WATCHDOG is not set\n# CONFIG_ZISOFS is not set\n# CONFIG_ZLIB_DEFLATE is not set\n# CONFIG_ZLIB_INFLATE is not set\nCONFIG_ZONE_DMA=y\n# CONFIG_ZOPT2201 is not set\n# CONFIG_ZPA2326 is not set\n# CONFIG_ZPOOL is not set\n# CONFIG_ZRAM is not set\n# CONFIG_ZRAM_MEMORY_TRACKING is not set\n# CONFIG_ZSMALLOC is not set\n# CONFIG_ZX_TDM is not set\n"
  },
  {
    "path": "target/linux/generic/config-5.15",
    "content": "# CONFIG_104_QUAD_8 is not set\nCONFIG_32BIT=y\nCONFIG_64BIT_TIME=y\n# CONFIG_6LOWPAN is not set\n# CONFIG_6LOWPAN_DEBUGFS is not set\n# CONFIG_6PACK is not set\n# CONFIG_8139CP is not set\n# CONFIG_8139TOO is not set\n# CONFIG_9P_FS is not set\n# CONFIG_AB3100_CORE is not set\n# CONFIG_AB8500_CORE is not set\n# CONFIG_ABP060MG is not set\n# CONFIG_ABX500_CORE is not set\n# CONFIG_ACCESSIBILITY is not set\n# CONFIG_ACENIC is not set\n# CONFIG_ACERHDF is not set\n# CONFIG_ACER_WIRELESS is not set\n# CONFIG_ACORN_PARTITION is not set\n# CONFIG_ACPI_ALS is not set\n# CONFIG_ACPI_APEI is not set\n# CONFIG_ACPI_BUTTON is not set\n# CONFIG_ACPI_CONFIGFS is not set\n# CONFIG_ACPI_CUSTOM_METHOD is not set\n# CONFIG_ACPI_EXTLOG is not set\n# CONFIG_ACPI_HED is not set\n# CONFIG_ACPI_NFIT is not set\n# CONFIG_ACPI_REDUCED_HARDWARE_ONLY is not set\n# CONFIG_ACPI_TABLE_UPGRADE is not set\n# CONFIG_ACPI_VIDEO is not set\n# CONFIG_AD2S1200 is not set\n# CONFIG_AD2S1210 is not set\n# CONFIG_AD2S90 is not set\n# CONFIG_AD5064 is not set\n# CONFIG_AD5110 is not set\n# CONFIG_AD525X_DPOT is not set\n# CONFIG_AD5272 is not set\n# CONFIG_AD5360 is not set\n# CONFIG_AD5380 is not set\n# CONFIG_AD5421 is not set\n# CONFIG_AD5446 is not set\n# CONFIG_AD5449 is not set\n# CONFIG_AD5504 is not set\n# CONFIG_AD5592R is not set\n# CONFIG_AD5593R is not set\n# CONFIG_AD5624R_SPI is not set\n# CONFIG_AD5686 is not set\n# CONFIG_AD5686_SPI is not set\n# CONFIG_AD5696_I2C is not set\n# CONFIG_AD5755 is not set\n# CONFIG_AD5758 is not set\n# CONFIG_AD5761 is not set\n# CONFIG_AD5764 is not set\n# CONFIG_AD5766 is not set\n# CONFIG_AD5770R is not set\n# CONFIG_AD5791 is not set\n# CONFIG_AD5933 is not set\n# CONFIG_AD7091R5 is not set\n# CONFIG_AD7124 is not set\n# CONFIG_AD7150 is not set\n# CONFIG_AD7152 is not set\n# CONFIG_AD7192 is not set\n# CONFIG_AD7266 is not set\n# CONFIG_AD7280 is not set\n# CONFIG_AD7291 is not set\n# CONFIG_AD7292 is not set\n# CONFIG_AD7298 is not set\n# CONFIG_AD7303 is not set\n# CONFIG_AD7476 is not set\n# CONFIG_AD7606 is not set\n# CONFIG_AD7606_IFACE_PARALLEL is not set\n# CONFIG_AD7606_IFACE_SPI is not set\n# CONFIG_AD7746 is not set\n# CONFIG_AD7766 is not set\n# CONFIG_AD7768_1 is not set\n# CONFIG_AD7780 is not set\n# CONFIG_AD7791 is not set\n# CONFIG_AD7793 is not set\n# CONFIG_AD7816 is not set\n# CONFIG_AD7887 is not set\n# CONFIG_AD7923 is not set\n# CONFIG_AD7949 is not set\n# CONFIG_AD799X is not set\n# CONFIG_AD8366 is not set\n# CONFIG_AD8801 is not set\n# CONFIG_AD9467 is not set\n# CONFIG_AD9523 is not set\n# CONFIG_AD9832 is not set\n# CONFIG_AD9834 is not set\n# CONFIG_ADAPTEC_STARFIRE is not set\n# CONFIG_ADE7854 is not set\n# CONFIG_ADF4350 is not set\n# CONFIG_ADF4371 is not set\n# CONFIG_ADFS_FS is not set\n# CONFIG_ADIN_PHY is not set\n# CONFIG_ADIS16080 is not set\n# CONFIG_ADIS16130 is not set\n# CONFIG_ADIS16136 is not set\n# CONFIG_ADIS16201 is not set\n# CONFIG_ADIS16203 is not set\n# CONFIG_ADIS16209 is not set\n# CONFIG_ADIS16240 is not set\n# CONFIG_ADIS16260 is not set\n# CONFIG_ADIS16400 is not set\n# CONFIG_ADIS16460 is not set\n# CONFIG_ADIS16475 is not set\n# CONFIG_ADIS16480 is not set\n# CONFIG_ADI_AXI_ADC is not set\n# CONFIG_ADJD_S311 is not set\n# CONFIG_ADM6996_PHY is not set\n# CONFIG_ADM8211 is not set\n# CONFIG_ADT7316 is not set\n# CONFIG_ADUX1020 is not set\nCONFIG_ADVISE_SYSCALLS=y\n# CONFIG_ADXL345_I2C is not set\n# CONFIG_ADXL345_SPI is not set\n# CONFIG_ADXL372_I2C is not set\n# CONFIG_ADXL372_SPI is not set\n# CONFIG_ADXRS290 is not set\n# CONFIG_ADXRS450 is not set\nCONFIG_AEABI=y\n# CONFIG_AFE4403 is not set\n# CONFIG_AFE4404 is not set\n# CONFIG_AFFS_FS is not set\n# CONFIG_AFS_DEBUG_CURSOR is not set\n# CONFIG_AFS_FS is not set\n# CONFIG_AF_KCM is not set\n# CONFIG_AF_RXRPC is not set\n# CONFIG_AF_RXRPC_INJECT_LOSS is not set\n# CONFIG_AF_RXRPC_IPV6 is not set\nCONFIG_AF_UNIX_OOB=y\n# CONFIG_AGP is not set\n# CONFIG_AHCI_CEVA is not set\n# CONFIG_AHCI_IMX is not set\n# CONFIG_AHCI_MVEBU is not set\n# CONFIG_AHCI_QORIQ is not set\n# CONFIG_AHCI_XGENE is not set\nCONFIG_AIO=y\n# CONFIG_AIRO is not set\n# CONFIG_AIRO_CS is not set\n# CONFIG_AIX_PARTITION is not set\n# CONFIG_AK09911 is not set\n# CONFIG_AK8974 is not set\n# CONFIG_AK8975 is not set\n# CONFIG_AL3010 is not set\n# CONFIG_AL3320A is not set\n# CONFIG_ALIM7101_WDT is not set\nCONFIG_ALLOW_DEV_COREDUMP=y\n# CONFIG_ALTERA_MBOX is not set\n# CONFIG_ALTERA_MSGDMA is not set\n# CONFIG_ALTERA_STAPL is not set\n# CONFIG_ALTERA_TSE is not set\n# CONFIG_ALX is not set\n# CONFIG_AL_FIC is not set\n# CONFIG_AM2315 is not set\n# CONFIG_AM335X_PHY_USB is not set\n# CONFIG_AMBA_PL08X is not set\n# CONFIG_AMD8111_ETH is not set\n# CONFIG_AMD_MEM_ENCRYPT is not set\n# CONFIG_AMD_PHY is not set\n# CONFIG_AMD_XGBE is not set\n# CONFIG_AMD_XGBE_HAVE_ECC is not set\n# CONFIG_AMIGA_PARTITION is not set\n# CONFIG_AMILO_RFKILL is not set\n# CONFIG_ANDROID is not set\nCONFIG_ANON_INODES=y\n# CONFIG_APDS9300 is not set\n# CONFIG_APDS9802ALS is not set\n# CONFIG_APDS9960 is not set\n# CONFIG_APM8018X is not set\n# CONFIG_APM_EMULATION is not set\n# CONFIG_APPLE_GMUX is not set\n# CONFIG_APPLE_MFI_FASTCHARGE is not set\n# CONFIG_APPLE_PROPERTIES is not set\n# CONFIG_APPLICOM is not set\n# CONFIG_AQTION is not set\n# CONFIG_AQUANTIA_PHY is not set\n# CONFIG_AR5523 is not set\n# CONFIG_AR7 is not set\n# CONFIG_AR8216_PHY is not set\n# CONFIG_AR8216_PHY_LEDS is not set\n# CONFIG_ARCH_ACTIONS is not set\n# CONFIG_ARCH_AGILEX is not set\n# CONFIG_ARCH_ALPINE is not set\n# CONFIG_ARCH_APPLE is not set\n# CONFIG_ARCH_ARTPEC is not set\n# CONFIG_ARCH_ASPEED is not set\n# CONFIG_ARCH_AT91 is not set\n# CONFIG_ARCH_AXXIA is not set\n# CONFIG_ARCH_BCM is not set\n# CONFIG_ARCH_BCM2835 is not set\n# CONFIG_ARCH_BCM4908 is not set\n# CONFIG_ARCH_BCM_21664 is not set\n# CONFIG_ARCH_BCM_23550 is not set\n# CONFIG_ARCH_BCM_281XX is not set\n# CONFIG_ARCH_BCM_5301X is not set\n# CONFIG_ARCH_BCM_53573 is not set\n# CONFIG_ARCH_BCM_63XX is not set\n# CONFIG_ARCH_BCM_CYGNUS is not set\n# CONFIG_ARCH_BCM_IPROC is not set\n# CONFIG_ARCH_BCM_NSP is not set\n# CONFIG_ARCH_BERLIN is not set\nCONFIG_ARCH_BINFMT_ELF_STATE=y\n# CONFIG_ARCH_BITMAIN is not set\n# CONFIG_ARCH_BRCMSTB is not set\n# CONFIG_ARCH_CLPS711X is not set\n# CONFIG_ARCH_CNS3XXX is not set\n# CONFIG_ARCH_DAVINCI is not set\n# CONFIG_ARCH_DIGICOLOR is not set\n# CONFIG_ARCH_DMA_ADDR_T_64BIT is not set\n# CONFIG_ARCH_DOVE is not set\n# CONFIG_ARCH_EBSA110 is not set\n# CONFIG_ARCH_EP93XX is not set\n# CONFIG_ARCH_EXYNOS is not set\nCONFIG_ARCH_FLATMEM_ENABLE=y\n# CONFIG_ARCH_FOOTBRIDGE is not set\n# CONFIG_ARCH_GEMINI is not set\n# CONFIG_ARCH_HI3xxx is not set\n# CONFIG_ARCH_HIGHBANK is not set\n# CONFIG_ARCH_HISI is not set\n# CONFIG_ARCH_INTEGRATOR is not set\n# CONFIG_ARCH_INTEL_SOCFPGA is not set\n# CONFIG_ARCH_IOP13XX is not set\n# CONFIG_ARCH_IOP32X is not set\n# CONFIG_ARCH_IOP33X is not set\n# CONFIG_ARCH_IXP4XX is not set\n# CONFIG_ARCH_K3 is not set\n# CONFIG_ARCH_KEEMBAY is not set\n# CONFIG_ARCH_KEYSTONE is not set\n# CONFIG_ARCH_KS8695 is not set\n# CONFIG_ARCH_LAYERSCAPE is not set\n# CONFIG_ARCH_LG1K is not set\n# CONFIG_ARCH_LPC32XX is not set\n# CONFIG_ARCH_MEDIATEK is not set\n# CONFIG_ARCH_MESON is not set\n# CONFIG_ARCH_MILBEAUT is not set\nCONFIG_ARCH_MMAP_RND_BITS=8\nCONFIG_ARCH_MMAP_RND_BITS_MAX=16\nCONFIG_ARCH_MMAP_RND_BITS_MIN=8\nCONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=16\nCONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=8\n# CONFIG_ARCH_MMP is not set\n# CONFIG_ARCH_MSTARV7 is not set\n# CONFIG_ARCH_MULTIPLATFORM is not set\n# CONFIG_ARCH_MULTI_V6 is not set\n# CONFIG_ARCH_MULTI_V7 is not set\n# CONFIG_ARCH_MV78XX0 is not set\n# CONFIG_ARCH_MVEBU is not set\n# CONFIG_ARCH_MXC is not set\n# CONFIG_ARCH_MXS is not set\n# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set\n# CONFIG_ARCH_NETX is not set\n# CONFIG_ARCH_NOMADIK is not set\n# CONFIG_ARCH_NPCM is not set\n# CONFIG_ARCH_NSPIRE is not set\n# CONFIG_ARCH_OMAP is not set\n# CONFIG_ARCH_OMAP1 is not set\n# CONFIG_ARCH_OMAP2 is not set\n# CONFIG_ARCH_OMAP2PLUS is not set\n# CONFIG_ARCH_OMAP3 is not set\n# CONFIG_ARCH_OMAP4 is not set\n# CONFIG_ARCH_ORION5X is not set\n# CONFIG_ARCH_OXNAS is not set\n# CONFIG_ARCH_PICOXCELL is not set\n# CONFIG_ARCH_PRIMA2 is not set\n# CONFIG_ARCH_PXA is not set\n# CONFIG_ARCH_QCOM is not set\n# CONFIG_ARCH_RANDOM is not set\n# CONFIG_ARCH_RDA is not set\n# CONFIG_ARCH_REALTEK is not set\n# CONFIG_ARCH_REALVIEW is not set\n# CONFIG_ARCH_RENESAS is not set\n# CONFIG_ARCH_ROCKCHIP is not set\n# CONFIG_ARCH_RPC is not set\n# CONFIG_ARCH_S32 is not set\n# CONFIG_ARCH_S3C24XX is not set\n# CONFIG_ARCH_S3C64XX is not set\n# CONFIG_ARCH_S5PV210 is not set\n# CONFIG_ARCH_SA1100 is not set\n# CONFIG_ARCH_SEATTLE is not set\n# CONFIG_ARCH_SHMOBILE is not set\n# CONFIG_ARCH_SIRF is not set\n# CONFIG_ARCH_SOCFPGA is not set\n# CONFIG_ARCH_SPARX5 is not set\n# CONFIG_ARCH_SPRD is not set\n# CONFIG_ARCH_STI is not set\n# CONFIG_ARCH_STM32 is not set\n# CONFIG_ARCH_STRATIX10 is not set\n# CONFIG_ARCH_SUNXI is not set\n# CONFIG_ARCH_SYNQUACER is not set\n# CONFIG_ARCH_TANGO is not set\n# CONFIG_ARCH_TEGRA is not set\n# CONFIG_ARCH_THUNDER is not set\n# CONFIG_ARCH_THUNDER2 is not set\n# CONFIG_ARCH_U300 is not set\n# CONFIG_ARCH_U8500 is not set\n# CONFIG_ARCH_UNIPHIER is not set\n# CONFIG_ARCH_VERSATILE is not set\n# CONFIG_ARCH_VEXPRESS is not set\n# CONFIG_ARCH_VIRT is not set\n# CONFIG_ARCH_VISCONTI is not set\n# CONFIG_ARCH_VT8500 is not set\n# CONFIG_ARCH_VULCAN is not set\n# CONFIG_ARCH_W90X900 is not set\n# CONFIG_ARCH_WANTS_THP_SWAP is not set\n# CONFIG_ARCH_WM8505 is not set\n# CONFIG_ARCH_WM8750 is not set\n# CONFIG_ARCH_WM8850 is not set\n# CONFIG_ARCH_XGENE is not set\n# CONFIG_ARCH_ZX is not set\n# CONFIG_ARCH_ZYNQ is not set\n# CONFIG_ARCH_ZYNQMP is not set\n# CONFIG_ARCNET is not set\n# CONFIG_ARC_EMAC is not set\n# CONFIG_ARC_IRQ_NO_AUTOSAVE is not set\n# CONFIG_ARM64_16K_PAGES is not set\n# CONFIG_ARM64_64K_PAGES is not set\n# CONFIG_ARM64_AMU_EXTN is not set\n# CONFIG_ARM64_BTI is not set\n# CONFIG_ARM64_CRYPTO is not set\n# CONFIG_ARM64_E0PD is not set\n# CONFIG_ARM64_ERRATUM_1024718 is not set\n# CONFIG_ARM64_ERRATUM_1165522 is not set\n# CONFIG_ARM64_ERRATUM_1286807 is not set\n# CONFIG_ARM64_ERRATUM_1319367 is not set\n# CONFIG_ARM64_ERRATUM_1418040 is not set\n# CONFIG_ARM64_ERRATUM_1463225 is not set\n# CONFIG_ARM64_ERRATUM_1508412 is not set\n# CONFIG_ARM64_ERRATUM_1530923 is not set\n# CONFIG_ARM64_ERRATUM_1542419 is not set\n# CONFIG_ARM64_ERRATUM_819472 is not set\n# CONFIG_ARM64_ERRATUM_824069 is not set\n# CONFIG_ARM64_ERRATUM_826319 is not set\n# CONFIG_ARM64_ERRATUM_827319 is not set\n# CONFIG_ARM64_ERRATUM_832075 is not set\n# CONFIG_ARM64_ERRATUM_834220 is not set\n# CONFIG_ARM64_ERRATUM_843419 is not set\n# CONFIG_ARM64_ERRATUM_845719 is not set\n# CONFIG_ARM64_ERRATUM_858921 is not set\n# CONFIG_ARM64_HW_AFDBM is not set\n# CONFIG_ARM64_LSE_ATOMICS is not set\n# CONFIG_ARM64_MODULE_PLTS is not set\n# CONFIG_ARM64_MTE is not set\n# CONFIG_ARM64_PAN is not set\n# CONFIG_ARM64_PMEM is not set\n# CONFIG_ARM64_PSEUDO_NMI is not set\n# CONFIG_ARM64_PTDUMP_DEBUGFS is not set\n# CONFIG_ARM64_PTR_AUTH is not set\n# CONFIG_ARM64_RANDOMIZE_TEXT_OFFSET is not set\n# CONFIG_ARM64_RAS_EXTN is not set\n# CONFIG_ARM64_RELOC_TEST is not set\n# CONFIG_ARM64_SVE is not set\nCONFIG_ARM64_SW_TTBR0_PAN=y\n# CONFIG_ARM64_TLB_RANGE is not set\n# CONFIG_ARM64_UAO is not set\n# CONFIG_ARM64_USE_LSE_ATOMICS is not set\n# CONFIG_ARM64_VA_BITS_48 is not set\n# CONFIG_ARM64_VHE is not set\n# CONFIG_ARM_APPENDED_DTB is not set\n# CONFIG_ARM_ARCH_TIMER is not set\n# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set\n# CONFIG_ARM_BIG_LITTLE_CPUFREQ is not set\n# CONFIG_ARM_CCI is not set\n# CONFIG_ARM_CCI400_PMU is not set\n# CONFIG_ARM_CCI5xx_PMU is not set\n# CONFIG_ARM_CCI_PMU is not set\n# CONFIG_ARM_CCN is not set\n# CONFIG_ARM_CMN is not set\n# CONFIG_ARM_CPUIDLE is not set\nCONFIG_ARM_CPU_TOPOLOGY=y\n# CONFIG_ARM_CRYPTO is not set\nCONFIG_ARM_DMA_MEM_BUFFERABLE=y\n# CONFIG_ARM_DSU_PMU is not set\n# CONFIG_ARM_ERRATA_326103 is not set\n# CONFIG_ARM_ERRATA_364296 is not set\n# CONFIG_ARM_ERRATA_411920 is not set\n# CONFIG_ARM_ERRATA_430973 is not set\n# CONFIG_ARM_ERRATA_458693 is not set\n# CONFIG_ARM_ERRATA_460075 is not set\n# CONFIG_ARM_ERRATA_643719 is not set\n# CONFIG_ARM_ERRATA_720789 is not set\n# CONFIG_ARM_ERRATA_742230 is not set\n# CONFIG_ARM_ERRATA_742231 is not set\n# CONFIG_ARM_ERRATA_743622 is not set\n# CONFIG_ARM_ERRATA_751472 is not set\n# CONFIG_ARM_ERRATA_754322 is not set\n# CONFIG_ARM_ERRATA_754327 is not set\n# CONFIG_ARM_ERRATA_764369 is not set\n# CONFIG_ARM_ERRATA_773022 is not set\n# CONFIG_ARM_ERRATA_775420 is not set\n# CONFIG_ARM_ERRATA_798181 is not set\n# CONFIG_ARM_ERRATA_814220 is not set\n# CONFIG_ARM_ERRATA_818325_852422 is not set\n# CONFIG_ARM_ERRATA_821420 is not set\n# CONFIG_ARM_ERRATA_825619 is not set\n# CONFIG_ARM_ERRATA_852421 is not set\n# CONFIG_ARM_ERRATA_852423 is not set\n# CONFIG_ARM_ERRATA_857271 is not set\n# CONFIG_ARM_ERRATA_857272 is not set\n# CONFIG_ARM_FFA_TRANSPORT is not set\nCONFIG_ARM_GIC_MAX_NR=1\n# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set\n# CONFIG_ARM_KPROBES_TEST is not set\n# CONFIG_ARM_LPAE is not set\n# CONFIG_ARM_MEDIATEK_CPUFREQ_HW is not set\n# CONFIG_ARM_MHU is not set\n# CONFIG_ARM_MODULE_PLTS is not set\n# CONFIG_ARM_PATCH_PHYS_VIRT is not set\n# CONFIG_ARM_PSCI is not set\n# CONFIG_ARM_PSCI_CHECKER is not set\n# CONFIG_ARM_PSCI_CPUIDLE is not set\n# CONFIG_ARM_PTDUMP_DEBUGFS is not set\n# CONFIG_ARM_SBSA_WATCHDOG is not set\n# CONFIG_ARM_SCMI_PROTOCOL is not set\n# CONFIG_ARM_SCPI_PROTOCOL is not set\n# CONFIG_ARM_SDE_INTERFACE is not set\n# CONFIG_ARM_SMCCC_SOC_ID is not set\n# CONFIG_ARM_SMC_WATCHDOG is not set\n# CONFIG_ARM_SP805_WATCHDOG is not set\n# CONFIG_ARM_SPE_PMU is not set\n# CONFIG_ARM_THUMBEE is not set\n# CONFIG_ARM_TIMER_SP804 is not set\n# CONFIG_ARM_UNWIND is not set\n# CONFIG_ARM_VIRT_EXT is not set\n# CONFIG_AS3935 is not set\n# CONFIG_AS73211 is not set\n# CONFIG_ASM9260_TIMER is not set\n# CONFIG_ASN1 is not set\n# CONFIG_ASUS_LAPTOP is not set\n# CONFIG_ASUS_WIRELESS is not set\n# CONFIG_ASYMMETRIC_KEY_TYPE is not set\n# CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE is not set\n# CONFIG_ASYNC_RAID6_TEST is not set\n# CONFIG_ASYNC_TX_DMA is not set\n# CONFIG_AT76C50X_USB is not set\n# CONFIG_AT803X_PHY is not set\n# CONFIG_AT91_SAMA5D2_ADC is not set\n# CONFIG_ATA is not set\n# CONFIG_ATAGS is not set\nCONFIG_ATAGS_PROC=y\n# CONFIG_ATALK is not set\n# CONFIG_ATARI_PARTITION is not set\n# CONFIG_ATA_ACPI is not set\nCONFIG_ATA_BMDMA=y\n# CONFIG_ATA_FORCE is not set\n# CONFIG_ATA_GENERIC is not set\n# CONFIG_ATA_LEDS is not set\n# CONFIG_ATA_NONSTANDARD is not set\n# CONFIG_ATA_OVER_ETH is not set\n# CONFIG_ATA_PIIX is not set\nCONFIG_ATA_SFF=y\n# CONFIG_ATA_VERBOSE_ERROR is not set\n# CONFIG_ATH10K is not set\n# CONFIG_ATH25 is not set\n# CONFIG_ATH5K is not set\n# CONFIG_ATH6KL is not set\n# CONFIG_ATH79 is not set\n# CONFIG_ATH9K is not set\n# CONFIG_ATH9K_HTC is not set\n# CONFIG_ATH_DEBUG is not set\n# CONFIG_ATL1 is not set\n# CONFIG_ATL1C is not set\n# CONFIG_ATL1E is not set\n# CONFIG_ATL2 is not set\n# CONFIG_ATLAS_EZO_SENSOR is not set\n# CONFIG_ATLAS_PH_SENSOR is not set\n# CONFIG_ATM is not set\n# CONFIG_ATMEL is not set\n# CONFIG_ATMEL_PIT is not set\n# CONFIG_ATMEL_SSC is not set\n# CONFIG_ATM_AMBASSADOR is not set\n# CONFIG_ATM_BR2684 is not set\nCONFIG_ATM_BR2684_IPFILTER=y\n# CONFIG_ATM_CLIP is not set\nCONFIG_ATM_CLIP_NO_ICMP=y\n# CONFIG_ATM_DRIVERS is not set\n# CONFIG_ATM_DUMMY is not set\n# CONFIG_ATM_ENI is not set\n# CONFIG_ATM_FIRESTREAM is not set\n# CONFIG_ATM_FORE200E is not set\n# CONFIG_ATM_HE is not set\n# CONFIG_ATM_HORIZON is not set\n# CONFIG_ATM_IA is not set\n# CONFIG_ATM_IDT77252 is not set\n# CONFIG_ATM_LANAI is not set\n# CONFIG_ATM_LANE is not set\n# CONFIG_ATM_MPOA is not set\n# CONFIG_ATM_NICSTAR is not set\n# CONFIG_ATM_SOLOS is not set\n# CONFIG_ATM_TCP is not set\n# CONFIG_ATM_ZATM is not set\n# CONFIG_ATOMIC64_SELFTEST is not set\n# CONFIG_ATP is not set\n# CONFIG_AUDIT is not set\n# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set\n# CONFIG_AURORA_NB8800 is not set\n# CONFIG_AUTOFS4_FS is not set\n# CONFIG_AUTOFS_FS is not set\n# CONFIG_AUTO_ZRELADDR is not set\n# CONFIG_AUXDISPLAY is not set\n# CONFIG_AX25 is not set\n# CONFIG_AX25_DAMA_SLAVE is not set\n# CONFIG_AX88796 is not set\n# CONFIG_AX88796B_PHY is not set\n# CONFIG_AXP20X_ADC is not set\n# CONFIG_AXP20X_POWER is not set\n# CONFIG_AXP288_ADC is not set\n# CONFIG_AXP288_FUEL_GAUGE is not set\n# CONFIG_B43 is not set\n# CONFIG_B43LEGACY is not set\n# CONFIG_B44 is not set\n# CONFIG_B53 is not set\n# CONFIG_B53_MDIO_DRIVER is not set\n# CONFIG_B53_MMAP_DRIVER is not set\n# CONFIG_B53_SERDES is not set\n# CONFIG_B53_SPI_DRIVER is not set\n# CONFIG_B53_SRAB_DRIVER is not set\n# CONFIG_BACKLIGHT_ADP8860 is not set\n# CONFIG_BACKLIGHT_ADP8870 is not set\n# CONFIG_BACKLIGHT_APPLE is not set\n# CONFIG_BACKLIGHT_ARCXCNN is not set\n# CONFIG_BACKLIGHT_BD6107 is not set\n# CONFIG_BACKLIGHT_CLASS_DEVICE is not set\n# CONFIG_BACKLIGHT_GENERIC is not set\n# CONFIG_BACKLIGHT_GPIO is not set\n# CONFIG_BACKLIGHT_KTD253 is not set\n# CONFIG_BACKLIGHT_LCD_SUPPORT is not set\n# CONFIG_BACKLIGHT_LED is not set\n# CONFIG_BACKLIGHT_LM3630A is not set\n# CONFIG_BACKLIGHT_LM3639 is not set\n# CONFIG_BACKLIGHT_LP855X is not set\n# CONFIG_BACKLIGHT_LV5207LP is not set\n# CONFIG_BACKLIGHT_PANDORA is not set\n# CONFIG_BACKLIGHT_PM8941_WLED is not set\n# CONFIG_BACKLIGHT_PWM is not set\n# CONFIG_BACKLIGHT_QCOM_WLED is not set\n# CONFIG_BACKLIGHT_RPI is not set\n# CONFIG_BACKLIGHT_SAHARA is not set\n# CONFIG_BACKTRACE_SELF_TEST is not set\n# CONFIG_BAREUDP is not set\nCONFIG_BASE_FULL=y\nCONFIG_BASE_SMALL=0\n# CONFIG_BATMAN_ADV is not set\n# CONFIG_BATTERY_BQ27XXX is not set\n# CONFIG_BATTERY_BQ27XXX_HDQ is not set\n# CONFIG_BATTERY_CW2015 is not set\n# CONFIG_BATTERY_DS2760 is not set\n# CONFIG_BATTERY_DS2780 is not set\n# CONFIG_BATTERY_DS2781 is not set\n# CONFIG_BATTERY_DS2782 is not set\n# CONFIG_BATTERY_GAUGE_LTC2941 is not set\n# CONFIG_BATTERY_GOLDFISH is not set\n# CONFIG_BATTERY_LEGO_EV3 is not set\n# CONFIG_BATTERY_MAX17040 is not set\n# CONFIG_BATTERY_MAX17042 is not set\n# CONFIG_BATTERY_MAX1721X is not set\n# CONFIG_BATTERY_RT5033 is not set\n# CONFIG_BATTERY_SBS is not set\n# CONFIG_BAYCOM_EPP is not set\n# CONFIG_BAYCOM_PAR is not set\n# CONFIG_BAYCOM_SER_FDX is not set\n# CONFIG_BAYCOM_SER_HDX is not set\n# CONFIG_BCACHE is not set\n# CONFIG_BCM47XX is not set\n# CONFIG_BCM54140_PHY is not set\n# CONFIG_BCM63XX is not set\n# CONFIG_BCM63XX_PHY is not set\n# CONFIG_BCM7038_WDT is not set\n# CONFIG_BCM7XXX_PHY is not set\n# CONFIG_BCM84881_PHY is not set\n# CONFIG_BCM87XX_PHY is not set\n# CONFIG_BCMA is not set\n# CONFIG_BCMA_DRIVER_GPIO is not set\nCONFIG_BCMA_POSSIBLE=y\n# CONFIG_BCMGENET is not set\n# CONFIG_BCM_IPROC_ADC is not set\n# CONFIG_BCM_KONA_USB2_PHY is not set\n# CONFIG_BCM_SBA_RAID is not set\n# CONFIG_BCM_VK is not set\n# CONFIG_BDI_SWITCH is not set\n# CONFIG_BE2ISCSI is not set\n# CONFIG_BE2NET is not set\n# CONFIG_BEFS_FS is not set\n# CONFIG_BFS_FS is not set\n# CONFIG_BGMAC is not set\n# CONFIG_BH1750 is not set\n# CONFIG_BH1780 is not set\n# CONFIG_BIG_KEYS is not set\n# CONFIG_BIG_LITTLE is not set\nCONFIG_BINARY_PRINTF=y\n# CONFIG_BINFMT_AOUT is not set\nCONFIG_BINFMT_ELF=y\n# CONFIG_BINFMT_ELF_FDPIC is not set\n# CONFIG_BINFMT_FLAT is not set\n# CONFIG_BINFMT_MISC is not set\nCONFIG_BINFMT_SCRIPT=y\nCONFIG_BITREVERSE=y\n# CONFIG_BLK_CGROUP_IOCOST is not set\n# CONFIG_BLK_CGROUP_IOLATENCY is not set\n# CONFIG_BLK_CGROUP_IOPRIO is not set\n# CONFIG_BLK_CMDLINE_PARSER is not set\n# CONFIG_BLK_DEBUG_FS is not set\nCONFIG_BLK_DEV=y\n# CONFIG_BLK_DEV_3W_XXXX_RAID is not set\n# CONFIG_BLK_DEV_4DRIVES is not set\n# CONFIG_BLK_DEV_AEC62XX is not set\n# CONFIG_BLK_DEV_ALI14XX is not set\n# CONFIG_BLK_DEV_ALI15X3 is not set\n# CONFIG_BLK_DEV_AMD74XX is not set\n# CONFIG_BLK_DEV_ATIIXP is not set\n# CONFIG_BLK_DEV_BSG is not set\n# CONFIG_BLK_DEV_BSGLIB is not set\n# CONFIG_BLK_DEV_CMD640 is not set\n# CONFIG_BLK_DEV_CMD64X is not set\n# CONFIG_BLK_DEV_COW_COMMON is not set\n# CONFIG_BLK_DEV_CRYPTOLOOP is not set\n# CONFIG_BLK_DEV_CS5520 is not set\n# CONFIG_BLK_DEV_CS5530 is not set\n# CONFIG_BLK_DEV_CS5535 is not set\n# CONFIG_BLK_DEV_CS5536 is not set\n# CONFIG_BLK_DEV_CY82C693 is not set\n# CONFIG_BLK_DEV_DAC960 is not set\n# CONFIG_BLK_DEV_DELKIN is not set\n# CONFIG_BLK_DEV_DM is not set\n# CONFIG_BLK_DEV_DRBD is not set\n# CONFIG_BLK_DEV_DTC2278 is not set\n# CONFIG_BLK_DEV_FD is not set\n# CONFIG_BLK_DEV_GENERIC is not set\n# CONFIG_BLK_DEV_HPT366 is not set\n# CONFIG_BLK_DEV_HT6560B is not set\n# CONFIG_BLK_DEV_IDEACPI is not set\n# CONFIG_BLK_DEV_IDECD is not set\n# CONFIG_BLK_DEV_IDECS is not set\n# CONFIG_BLK_DEV_IDEPCI is not set\n# CONFIG_BLK_DEV_IDEPNP is not set\n# CONFIG_BLK_DEV_IDETAPE is not set\n# CONFIG_BLK_DEV_IDE_AU1XXX is not set\n# CONFIG_BLK_DEV_IDE_SATA is not set\nCONFIG_BLK_DEV_INITRD=y\n# CONFIG_BLK_DEV_INTEGRITY is not set\n# CONFIG_BLK_DEV_IO_TRACE is not set\n# CONFIG_BLK_DEV_IT8172 is not set\n# CONFIG_BLK_DEV_IT8213 is not set\n# CONFIG_BLK_DEV_IT821X is not set\n# CONFIG_BLK_DEV_JMICRON is not set\n# CONFIG_BLK_DEV_LOOP is not set\nCONFIG_BLK_DEV_LOOP_MIN_COUNT=8\n# CONFIG_BLK_DEV_MD is not set\n# CONFIG_BLK_DEV_NBD is not set\n# CONFIG_BLK_DEV_NS87415 is not set\n# CONFIG_BLK_DEV_NULL_BLK is not set\n# CONFIG_BLK_DEV_NVME is not set\n# CONFIG_BLK_DEV_OFFBOARD is not set\n# CONFIG_BLK_DEV_OPTI621 is not set\n# CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set\n# CONFIG_BLK_DEV_PDC202XX_NEW is not set\n# CONFIG_BLK_DEV_PDC202XX_OLD is not set\n# CONFIG_BLK_DEV_PIIX is not set\n# CONFIG_BLK_DEV_PLATFORM is not set\n# CONFIG_BLK_DEV_PMEM is not set\n# CONFIG_BLK_DEV_QD65XX is not set\n# CONFIG_BLK_DEV_RAM is not set\n# CONFIG_BLK_DEV_RBD is not set\n# CONFIG_BLK_DEV_RSXX is not set\n# CONFIG_BLK_DEV_RZ1000 is not set\n# CONFIG_BLK_DEV_SC1200 is not set\n# CONFIG_BLK_DEV_SD is not set\n# CONFIG_BLK_DEV_SIIMAGE is not set\n# CONFIG_BLK_DEV_SIS5513 is not set\n# CONFIG_BLK_DEV_SKD is not set\n# CONFIG_BLK_DEV_SL82C105 is not set\n# CONFIG_BLK_DEV_SLC90E66 is not set\n# CONFIG_BLK_DEV_SR is not set\n# CONFIG_BLK_DEV_SVWKS is not set\n# CONFIG_BLK_DEV_SX8 is not set\n# CONFIG_BLK_DEV_TC86C001 is not set\n# CONFIG_BLK_DEV_THROTTLING is not set\n# CONFIG_BLK_DEV_TRIFLEX is not set\n# CONFIG_BLK_DEV_TRM290 is not set\n# CONFIG_BLK_DEV_UMC8672 is not set\n# CONFIG_BLK_DEV_UMEM is not set\n# CONFIG_BLK_DEV_VIA82CXXX is not set\n# CONFIG_BLK_DEV_ZONED is not set\n# CONFIG_BLK_INLINE_ENCRYPTION is not set\n# CONFIG_BLK_SED_OPAL is not set\n# CONFIG_BLK_WBT is not set\nCONFIG_BLOCK=y\n# CONFIG_BMA180 is not set\n# CONFIG_BMA220 is not set\n# CONFIG_BMA400 is not set\n# CONFIG_BMC150_ACCEL is not set\n# CONFIG_BMC150_MAGN is not set\n# CONFIG_BMC150_MAGN_I2C is not set\n# CONFIG_BMC150_MAGN_SPI is not set\n# CONFIG_BME680 is not set\n# CONFIG_BMG160 is not set\n# CONFIG_BMI088_ACCEL is not set\n# CONFIG_BMI160_I2C is not set\n# CONFIG_BMI160_SPI is not set\n# CONFIG_BMIPS_GENERIC is not set\n# CONFIG_BMP280 is not set\n# CONFIG_BNA is not set\n# CONFIG_BNX2 is not set\n# CONFIG_BNX2X is not set\n# CONFIG_BNX2X_SRIOV is not set\n# CONFIG_BNXT is not set\n# CONFIG_BONDING is not set\n# CONFIG_BOOKE_WDT is not set\nCONFIG_BOOKE_WDT_DEFAULT_TIMEOUT=3\n# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set\n# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set\n# CONFIG_BOOTTIME_TRACING is not set\n# CONFIG_BOOT_CONFIG is not set\n# CONFIG_BOOT_PRINTK_DELAY is not set\nCONFIG_BOOT_RAW=y\n# CONFIG_BOUNCE is not set\nCONFIG_BPF=y\n# CONFIG_BPFILTER is not set\nCONFIG_BPF_JIT=y\n# CONFIG_BPF_JIT_ALWAYS_ON is not set\nCONFIG_BPF_JIT_DEFAULT_ON=y\n# CONFIG_BPF_PRELOAD is not set\n# CONFIG_BPF_STREAM_PARSER is not set\nCONFIG_BPF_SYSCALL=y\nCONFIG_BPF_UNPRIV_DEFAULT_OFF=y\n# CONFIG_BPQETHER is not set\nCONFIG_BQL=y\nCONFIG_BRANCH_PROFILE_NONE=y\n# CONFIG_BRCMFMAC is not set\n# CONFIG_BRCMSMAC is not set\n# CONFIG_BRCMSTB_GISB_ARB is not set\nCONFIG_BRIDGE=y\n# CONFIG_BRIDGE_CFM is not set\n# CONFIG_BRIDGE_EBT_802_3 is not set\n# CONFIG_BRIDGE_EBT_AMONG is not set\n# CONFIG_BRIDGE_EBT_ARP is not set\n# CONFIG_BRIDGE_EBT_ARPREPLY is not set\n# CONFIG_BRIDGE_EBT_BROUTE is not set\n# CONFIG_BRIDGE_EBT_DNAT is not set\n# CONFIG_BRIDGE_EBT_IP is not set\n# CONFIG_BRIDGE_EBT_IP6 is not set\n# CONFIG_BRIDGE_EBT_LIMIT is not set\n# CONFIG_BRIDGE_EBT_LOG is not set\n# CONFIG_BRIDGE_EBT_MARK is not set\n# CONFIG_BRIDGE_EBT_MARK_T is not set\n# CONFIG_BRIDGE_EBT_NFLOG is not set\n# CONFIG_BRIDGE_EBT_PKTTYPE is not set\n# CONFIG_BRIDGE_EBT_REDIRECT is not set\n# CONFIG_BRIDGE_EBT_SNAT is not set\n# CONFIG_BRIDGE_EBT_STP is not set\n# CONFIG_BRIDGE_EBT_T_FILTER is not set\n# CONFIG_BRIDGE_EBT_T_NAT is not set\n# CONFIG_BRIDGE_EBT_VLAN is not set\nCONFIG_BRIDGE_IGMP_SNOOPING=y\n# CONFIG_BRIDGE_MRP is not set\n# CONFIG_BRIDGE_NETFILTER is not set\n# CONFIG_BRIDGE_NF_EBTABLES is not set\nCONFIG_BRIDGE_VLAN_FILTERING=y\n# CONFIG_BROADCOM_PHY is not set\nCONFIG_BROKEN_ON_SMP=y\n# CONFIG_BSD_DISKLABEL is not set\n# CONFIG_BSD_PROCESS_ACCT is not set\n# CONFIG_BSD_PROCESS_ACCT_V3 is not set\n# CONFIG_BT is not set\n# CONFIG_BTRFS_ASSERT is not set\n# CONFIG_BTRFS_DEBUG is not set\n# CONFIG_BTRFS_FS is not set\n# CONFIG_BTRFS_FS_POSIX_ACL is not set\n# CONFIG_BTRFS_FS_REF_VERIFY is not set\n# CONFIG_BTRFS_FS_RUN_SANITY_TESTS is not set\n# CONFIG_BT_AOSPEXT is not set\n# CONFIG_BT_ATH3K is not set\n# CONFIG_BT_BNEP is not set\nCONFIG_BT_BNEP_MC_FILTER=y\nCONFIG_BT_BNEP_PROTO_FILTER=y\n# CONFIG_BT_BREDR is not set\n# CONFIG_BT_CMTP is not set\n# CONFIG_BT_FEATURE_DEBUG is not set\n# CONFIG_BT_HCIBCM203X is not set\n# CONFIG_BT_HCIBFUSB is not set\n# CONFIG_BT_HCIBLUECARD is not set\n# CONFIG_BT_HCIBPA10X is not set\n# CONFIG_BT_HCIBT3C is not set\n# CONFIG_BT_HCIBTSDIO is not set\n# CONFIG_BT_HCIBTUSB is not set\n# CONFIG_BT_HCIBTUSB_AUTOSUSPEND is not set\n# CONFIG_BT_HCIBTUSB_MTK is not set\n# CONFIG_BT_HCIBTUSB_RTL is not set\n# CONFIG_BT_HCIDTL1 is not set\n# CONFIG_BT_HCIUART is not set\n# CONFIG_BT_HCIUART_3WIRE is not set\n# CONFIG_BT_HCIUART_AG6XX is not set\n# CONFIG_BT_HCIUART_ATH3K is not set\nCONFIG_BT_HCIUART_BCSP=y\nCONFIG_BT_HCIUART_H4=y\n# CONFIG_BT_HCIUART_LL is not set\n# CONFIG_BT_HCIUART_MRVL is not set\n# CONFIG_BT_HCIUART_QCA is not set\n# CONFIG_BT_HCIUART_RTL is not set\n# CONFIG_BT_HCIVHCI is not set\n# CONFIG_BT_HIDP is not set\n# CONFIG_BT_HS is not set\n# CONFIG_BT_LE is not set\n# CONFIG_BT_LEDS is not set\n# CONFIG_BT_MRVL is not set\n# CONFIG_BT_MSFTEXT is not set\n# CONFIG_BT_MTKSDIO is not set\n# CONFIG_BT_MTKUART is not set\n# CONFIG_BT_RFCOMM is not set\nCONFIG_BT_RFCOMM_TTY=y\n# CONFIG_BT_SELFTEST is not set\n# CONFIG_BT_VIRTIO is not set\nCONFIG_BUG=y\n# CONFIG_BUG_ON_DATA_CORRUPTION is not set\nCONFIG_BUILDTIME_EXTABLE_SORT=y\nCONFIG_BUILDTIME_TABLE_SORT=y\n# CONFIG_BUILD_BIN2C is not set\nCONFIG_BUILD_SALT=\"\"\n# CONFIG_C2PORT is not set\nCONFIG_CACHE_L2X0_PMU=y\n# CONFIG_CADENCE_WATCHDOG is not set\n# CONFIG_CAIF is not set\n# CONFIG_CAN is not set\n# CONFIG_CAN_BCM is not set\n# CONFIG_CAN_DEBUG_DEVICES is not set\n# CONFIG_CAN_DEV is not set\n# CONFIG_CAN_ETAS_ES58X is not set\n# CONFIG_CAN_GS_USB is not set\n# CONFIG_CAN_GW is not set\n# CONFIG_CAN_HI311X is not set\n# CONFIG_CAN_IFI_CANFD is not set\n# CONFIG_CAN_ISOTP is not set\n# CONFIG_CAN_J1939 is not set\n# CONFIG_CAN_KVASER_PCIEFD is not set\n# CONFIG_CAN_MCBA_USB is not set\n# CONFIG_CAN_MCP251XFD is not set\n# CONFIG_CAN_M_CAN is not set\n# CONFIG_CAN_PEAK_PCIEFD is not set\n# CONFIG_CAN_RAW is not set\n# CONFIG_CAN_RCAR is not set\n# CONFIG_CAN_RCAR_CANFD is not set\n# CONFIG_CAN_SLCAN is not set\n# CONFIG_CAN_SUN4I is not set\n# CONFIG_CAN_UCAN is not set\n# CONFIG_CAN_VCAN is not set\n# CONFIG_CAN_VXCAN is not set\n# CONFIG_CAPI_AVM is not set\n# CONFIG_CAPI_EICON is not set\n# CONFIG_CAPI_TRACE is not set\nCONFIG_CARDBUS=y\n# CONFIG_CARDMAN_4000 is not set\n# CONFIG_CARDMAN_4040 is not set\n# CONFIG_CARL9170 is not set\n# CONFIG_CASSINI is not set\n# CONFIG_CAVIUM_CPT is not set\n# CONFIG_CAVIUM_ERRATUM_22375 is not set\n# CONFIG_CAVIUM_ERRATUM_23144 is not set\n# CONFIG_CAVIUM_ERRATUM_23154 is not set\n# CONFIG_CAVIUM_ERRATUM_27456 is not set\n# CONFIG_CAVIUM_ERRATUM_30115 is not set\n# CONFIG_CAVIUM_OCTEON_SOC is not set\n# CONFIG_CAVIUM_PTP is not set\n# CONFIG_CAVIUM_TX2_ERRATUM_219 is not set\n# CONFIG_CB710_CORE is not set\n# CONFIG_CC10001_ADC is not set\n# CONFIG_CCS811 is not set\nCONFIG_CC_CAN_LINK=y\nCONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y\n# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set\n# CONFIG_CDROM_PKTCDVD is not set\n# CONFIG_CEPH_FS is not set\n# CONFIG_CEPH_LIB is not set\n# CONFIG_CFG80211 is not set\n# CONFIG_CFG80211_CERTIFICATION_ONUS is not set\n# CONFIG_CGROUPS is not set\n# CONFIG_CGROUP_MISC is not set\n# CONFIG_CHARGER_ADP5061 is not set\n# CONFIG_CHARGER_BD99954 is not set\n# CONFIG_CHARGER_BQ2415X is not set\n# CONFIG_CHARGER_BQ24190 is not set\n# CONFIG_CHARGER_BQ24257 is not set\n# CONFIG_CHARGER_BQ24735 is not set\n# CONFIG_CHARGER_BQ2515X is not set\n# CONFIG_CHARGER_BQ256XX is not set\n# CONFIG_CHARGER_BQ25890 is not set\n# CONFIG_CHARGER_BQ25980 is not set\n# CONFIG_CHARGER_DETECTOR_MAX14656 is not set\n# CONFIG_CHARGER_GPIO is not set\n# CONFIG_CHARGER_ISP1704 is not set\n# CONFIG_CHARGER_LP8727 is not set\n# CONFIG_CHARGER_LT3651 is not set\n# CONFIG_CHARGER_LTC3651 is not set\n# CONFIG_CHARGER_LTC4162L is not set\n# CONFIG_CHARGER_MANAGER is not set\n# CONFIG_CHARGER_MAX8903 is not set\n# CONFIG_CHARGER_RT9455 is not set\n# CONFIG_CHARGER_SBS is not set\n# CONFIG_CHARGER_SMB347 is not set\n# CONFIG_CHARGER_TWL4030 is not set\n# CONFIG_CHARGER_UCS1002 is not set\n# CONFIG_CHASH_SELFTEST is not set\n# CONFIG_CHASH_STATS is not set\n# CONFIG_CHECKPOINT_RESTORE is not set\n# CONFIG_CHELSIO_T1 is not set\n# CONFIG_CHELSIO_T3 is not set\n# CONFIG_CHELSIO_T4 is not set\n# CONFIG_CHELSIO_T4VF is not set\n# CONFIG_CHROME_PLATFORMS is not set\n# CONFIG_CHR_DEV_OSST is not set\n# CONFIG_CHR_DEV_SCH is not set\n# CONFIG_CHR_DEV_SG is not set\n# CONFIG_CHR_DEV_ST is not set\n# CONFIG_CICADA_PHY is not set\n# CONFIG_CIFS is not set\n# CONFIG_CIFS_ACL is not set\nCONFIG_CIFS_ALLOW_INSECURE_LEGACY=y\n# CONFIG_CIFS_DEBUG is not set\n# CONFIG_CIFS_DEBUG2 is not set\n# CONFIG_CIFS_FSCACHE is not set\n# CONFIG_CIFS_NFSD_EXPORT is not set\nCONFIG_CIFS_POSIX=y\n# CONFIG_CIFS_SMB2 is not set\n# CONFIG_CIFS_STATS is not set\n# CONFIG_CIFS_STATS2 is not set\n# CONFIG_CIFS_SWN_UPCALL is not set\n# CONFIG_CIFS_WEAK_PW_HASH is not set\nCONFIG_CIFS_XATTR=y\n# CONFIG_CIO_DAC is not set\n# CONFIG_CLEANCACHE is not set\n# CONFIG_CLKSRC_PISTACHIO is not set\n# CONFIG_CLKSRC_VERSATILE is not set\n# CONFIG_CLK_GFM_LPASS_SM8250 is not set\n# CONFIG_CLK_HSDK is not set\n# CONFIG_CLK_QORIQ is not set\n# CONFIG_CLK_SP810 is not set\n# CONFIG_CLOCK_THERMAL is not set\nCONFIG_CLS_U32_MARK=y\n# CONFIG_CLS_U32_PERF is not set\n# CONFIG_CM32181 is not set\n# CONFIG_CM3232 is not set\n# CONFIG_CM3323 is not set\n# CONFIG_CM3605 is not set\n# CONFIG_CM36651 is not set\n# CONFIG_CMA is not set\nCONFIG_CMDLINE=\"\"\n# CONFIG_CMDLINE_BOOL is not set\n# CONFIG_CMDLINE_EXTEND is not set\n# CONFIG_CMDLINE_FORCE is not set\n# CONFIG_CMDLINE_FROM_BOOTLOADER is not set\n# CONFIG_CMDLINE_PARTITION is not set\n# CONFIG_CNIC is not set\n# CONFIG_CODA_FS is not set\n# CONFIG_CODE_PATCHING_SELFTEST is not set\n# CONFIG_COMEDI is not set\n# CONFIG_COMMON_CLK_AXI_CLKGEN is not set\n# CONFIG_COMMON_CLK_BOSTON is not set\n# CONFIG_COMMON_CLK_CDCE706 is not set\n# CONFIG_COMMON_CLK_CDCE925 is not set\n# CONFIG_COMMON_CLK_CS2000_CP is not set\n# CONFIG_COMMON_CLK_FIXED_MMIO is not set\n# CONFIG_COMMON_CLK_IPROC is not set\n# CONFIG_COMMON_CLK_MAX9485 is not set\n# CONFIG_COMMON_CLK_MT6765 is not set\n# CONFIG_COMMON_CLK_MT8167 is not set\n# CONFIG_COMMON_CLK_MT8167_AUDSYS is not set\n# CONFIG_COMMON_CLK_MT8167_IMGSYS is not set\n# CONFIG_COMMON_CLK_MT8167_MFGCFG is not set\n# CONFIG_COMMON_CLK_MT8167_MMSYS is not set\n# CONFIG_COMMON_CLK_MT8167_VDECSYS is not set\n# CONFIG_COMMON_CLK_MT8192 is not set\n# CONFIG_COMMON_CLK_NXP is not set\n# CONFIG_COMMON_CLK_PIC32 is not set\n# CONFIG_COMMON_CLK_PISTACHIO is not set\n# CONFIG_COMMON_CLK_PWM is not set\n# CONFIG_COMMON_CLK_PXA is not set\n# CONFIG_COMMON_CLK_QCOM is not set\n# CONFIG_COMMON_CLK_SI514 is not set\n# CONFIG_COMMON_CLK_SI5341 is not set\n# CONFIG_COMMON_CLK_SI5351 is not set\n# CONFIG_COMMON_CLK_SI544 is not set\n# CONFIG_COMMON_CLK_SI570 is not set\n# CONFIG_COMMON_CLK_VC5 is not set\n# CONFIG_COMMON_CLK_XGENE is not set\n# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set\nCONFIG_COMPACTION=y\n# CONFIG_COMPAL_LAPTOP is not set\n# CONFIG_COMPAT is not set\n# CONFIG_COMPAT_BRK is not set\n# CONFIG_COMPILE_TEST is not set\n# CONFIG_CONFIGFS_FS is not set\n# CONFIG_CONNECTOR is not set\nCONFIG_CONSOLE_LOGLEVEL_DEFAULT=7\nCONFIG_CONSOLE_LOGLEVEL_QUIET=4\nCONFIG_CONSTRUCTORS=y\n# CONFIG_CONTEXT_SWITCH_TRACER is not set\n# CONFIG_COPS is not set\n# CONFIG_CORDIC is not set\n# CONFIG_COREDUMP is not set\n# CONFIG_CORESIGHT is not set\n# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set\n# CONFIG_CORTINA_PHY is not set\n# CONFIG_COUNTER is not set\n# CONFIG_CPA_DEBUG is not set\n# CONFIG_CPU_BIG_ENDIAN is not set\n# CONFIG_CPU_BPREDICT_DISABLE is not set\n# CONFIG_CPU_DCACHE_DISABLE is not set\n# CONFIG_CPU_FREQ is not set\n# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set\n# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set\n# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set\n# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set\n# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set\n# CONFIG_CPU_FREQ_GOV_SCHEDUTIL is not set\n# CONFIG_CPU_FREQ_STAT_DETAILS is not set\n# CONFIG_CPU_FREQ_THERMAL is not set\n# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set\n# CONFIG_CPU_ICACHE_DISABLE is not set\n# CONFIG_CPU_ICACHE_MISMATCH_WORKAROUND is not set\n# CONFIG_CPU_IDLE is not set\n# CONFIG_CPU_IDLE_GOV_LADDER is not set\n# CONFIG_CPU_IDLE_GOV_MENU is not set\n# CONFIG_CPU_IDLE_GOV_TEO is not set\n# CONFIG_CPU_IDLE_MULTIPLE_DRIVERS is not set\n# CONFIG_CPU_ISOLATION is not set\nCONFIG_CPU_LITTLE_ENDIAN=y\n# CONFIG_CPU_NO_EFFICIENT_FFS is not set\nCONFIG_CPU_SW_DOMAIN_PAN=y\n# CONFIG_CPU_THERMAL is not set\n# CONFIG_CRAMFS is not set\nCONFIG_CRAMFS_BLOCKDEV=y\n# CONFIG_CRAMFS_MTD is not set\n# CONFIG_CRASH_DUMP is not set\n# CONFIG_CRC16 is not set\nCONFIG_CRC32=y\n# CONFIG_CRC32_BIT is not set\nCONFIG_CRC32_SARWATE=y\n# CONFIG_CRC32_SELFTEST is not set\n# CONFIG_CRC32_SLICEBY4 is not set\n# CONFIG_CRC32_SLICEBY8 is not set\n# CONFIG_CRC4 is not set\n# CONFIG_CRC64 is not set\n# CONFIG_CRC7 is not set\n# CONFIG_CRC8 is not set\n# CONFIG_CRC_CCITT is not set\n# CONFIG_CRC_ITU_T is not set\n# CONFIG_CRC_T10DIF is not set\nCONFIG_CROSS_COMPILE=\"\"\n# CONFIG_CROSS_MEMORY_ATTACH is not set\nCONFIG_CRYPTO=y\n# CONFIG_CRYPTO_842 is not set\nCONFIG_CRYPTO_ACOMP2=y\n# CONFIG_CRYPTO_ADIANTUM is not set\nCONFIG_CRYPTO_AEAD=y\nCONFIG_CRYPTO_AEAD2=y\n# CONFIG_CRYPTO_AEGIS128 is not set\n# CONFIG_CRYPTO_AEGIS128L is not set\n# CONFIG_CRYPTO_AEGIS128L_AESNI_SSE2 is not set\n# CONFIG_CRYPTO_AEGIS128_AESNI_SSE2 is not set\n# CONFIG_CRYPTO_AEGIS256 is not set\n# CONFIG_CRYPTO_AEGIS256_AESNI_SSE2 is not set\nCONFIG_CRYPTO_AES=y\n# CONFIG_CRYPTO_AES_586 is not set\n# CONFIG_CRYPTO_AES_ARM is not set\n# CONFIG_CRYPTO_AES_ARM64 is not set\n# CONFIG_CRYPTO_AES_ARM64_BS is not set\n# CONFIG_CRYPTO_AES_ARM64_CE is not set\n# CONFIG_CRYPTO_AES_ARM64_CE_BLK is not set\n# CONFIG_CRYPTO_AES_ARM64_CE_CCM is not set\n# CONFIG_CRYPTO_AES_ARM64_NEON_BLK is not set\n# CONFIG_CRYPTO_AES_ARM_BS is not set\n# CONFIG_CRYPTO_AES_ARM_CE is not set\n# CONFIG_CRYPTO_AES_NI_INTEL is not set\n# CONFIG_CRYPTO_AES_TI is not set\nCONFIG_CRYPTO_AKCIPHER=y\nCONFIG_CRYPTO_AKCIPHER2=y\nCONFIG_CRYPTO_ALGAPI=y\nCONFIG_CRYPTO_ALGAPI2=y\n# CONFIG_CRYPTO_ANSI_CPRNG is not set\n# CONFIG_CRYPTO_ANUBIS is not set\n# CONFIG_CRYPTO_ARC4 is not set\n# CONFIG_CRYPTO_AUTHENC is not set\n# CONFIG_CRYPTO_BLAKE2B is not set\n# CONFIG_CRYPTO_BLAKE2B_NEON is not set\n# CONFIG_CRYPTO_BLAKE2S is not set\n# CONFIG_CRYPTO_BLAKE2S_ARM is not set\n# CONFIG_CRYPTO_BLAKE2S_X86 is not set\n# CONFIG_CRYPTO_BLOWFISH is not set\n# CONFIG_CRYPTO_CAMELLIA is not set\n# CONFIG_CRYPTO_CAST5 is not set\n# CONFIG_CRYPTO_CAST6 is not set\n# CONFIG_CRYPTO_CBC is not set\nCONFIG_CRYPTO_CCM=y\n# CONFIG_CRYPTO_CFB is not set\n# CONFIG_CRYPTO_CHACHA20 is not set\n# CONFIG_CRYPTO_CHACHA20POLY1305 is not set\n# CONFIG_CRYPTO_CHACHA20_NEON is not set\n# CONFIG_CRYPTO_CHACHA20_X86_64 is not set\n# CONFIG_CRYPTO_CHACHA_MIPS is not set\n# CONFIG_CRYPTO_CMAC is not set\n# CONFIG_CRYPTO_CRC32 is not set\n# CONFIG_CRYPTO_CRC32C is not set\n# CONFIG_CRYPTO_CRC32C_INTEL is not set\n# CONFIG_CRYPTO_CRC32_ARM_CE is not set\n# CONFIG_CRYPTO_CRCT10DIF is not set\n# CONFIG_CRYPTO_CRCT10DIF_ARM64_CE is not set\n# CONFIG_CRYPTO_CRCT10DIF_ARM_CE is not set\n# CONFIG_CRYPTO_CRYPTD is not set\nCONFIG_CRYPTO_CTR=y\n# CONFIG_CRYPTO_CTS is not set\n# CONFIG_CRYPTO_CURVE25519 is not set\n# CONFIG_CRYPTO_CURVE25519_NEON is not set\n# CONFIG_CRYPTO_CURVE25519_X86 is not set\n# CONFIG_CRYPTO_DEFLATE is not set\n# CONFIG_CRYPTO_DES is not set\n# CONFIG_CRYPTO_DEV_AMLOGIC_GXL is not set\n# CONFIG_CRYPTO_DEV_ATMEL_AES is not set\n# CONFIG_CRYPTO_DEV_ATMEL_AUTHENC is not set\n# CONFIG_CRYPTO_DEV_ATMEL_ECC is not set\n# CONFIG_CRYPTO_DEV_ATMEL_SHA is not set\n# CONFIG_CRYPTO_DEV_ATMEL_SHA204A is not set\n# CONFIG_CRYPTO_DEV_ATMEL_TDES is not set\n# CONFIG_CRYPTO_DEV_CAVIUM_ZIP is not set\n# CONFIG_CRYPTO_DEV_CCP is not set\n# CONFIG_CRYPTO_DEV_CCP_DEBUGFS is not set\n# CONFIG_CRYPTO_DEV_CCREE is not set\n# CONFIG_CRYPTO_DEV_FSL_CAAM is not set\n# CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API_DESC is not set\n# CONFIG_CRYPTO_DEV_HIFN_795X is not set\n# CONFIG_CRYPTO_DEV_HISI_SEC is not set\n# CONFIG_CRYPTO_DEV_HISI_ZIP is not set\n# CONFIG_CRYPTO_DEV_IMGTEC_HASH is not set\n# CONFIG_CRYPTO_DEV_MARVELL_CESA is not set\n# CONFIG_CRYPTO_DEV_MV_CESA is not set\n# CONFIG_CRYPTO_DEV_MXC_SCC is not set\n# CONFIG_CRYPTO_DEV_MXS_DCP is not set\n# CONFIG_CRYPTO_DEV_NITROX_CNN55XX is not set\n# CONFIG_CRYPTO_DEV_OCTEONTX_CPT is not set\n# CONFIG_CRYPTO_DEV_QAT_4XXX is not set\n# CONFIG_CRYPTO_DEV_QAT_C3XXX is not set\n# CONFIG_CRYPTO_DEV_QAT_C3XXXVF is not set\n# CONFIG_CRYPTO_DEV_QAT_C62X is not set\n# CONFIG_CRYPTO_DEV_QAT_C62XVF is not set\n# CONFIG_CRYPTO_DEV_QAT_DH895xCC is not set\n# CONFIG_CRYPTO_DEV_QAT_DH895xCCVF is not set\n# CONFIG_CRYPTO_DEV_QCE is not set\n# CONFIG_CRYPTO_DEV_S5P is not set\n# CONFIG_CRYPTO_DEV_SAFEXCEL is not set\n# CONFIG_CRYPTO_DEV_SAHARA is not set\n# CONFIG_CRYPTO_DEV_SP_PSP is not set\n# CONFIG_CRYPTO_DEV_TALITOS is not set\n# CONFIG_CRYPTO_DEV_VIRTIO is not set\n# CONFIG_CRYPTO_DH is not set\n# CONFIG_CRYPTO_DRBG_CTR is not set\n# CONFIG_CRYPTO_DRBG_HASH is not set\n# CONFIG_CRYPTO_DRBG_MENU is not set\n# CONFIG_CRYPTO_ECB is not set\n# CONFIG_CRYPTO_ECDH is not set\n# CONFIG_CRYPTO_ECDSA is not set\n# CONFIG_CRYPTO_ECHAINIV is not set\n# CONFIG_CRYPTO_ECRDSA is not set\n# CONFIG_CRYPTO_ESSIV is not set\n# CONFIG_CRYPTO_FCRYPT is not set\n# CONFIG_CRYPTO_FIPS is not set\nCONFIG_CRYPTO_GCM=y\nCONFIG_CRYPTO_GF128MUL=y\nCONFIG_CRYPTO_GHASH=y\n# CONFIG_CRYPTO_GHASH_ARM64_CE is not set\n# CONFIG_CRYPTO_GHASH_ARM_CE is not set\n# CONFIG_CRYPTO_GHASH_CLMUL_NI_INTEL is not set\nCONFIG_CRYPTO_HASH=y\nCONFIG_CRYPTO_HASH2=y\n# CONFIG_CRYPTO_HMAC is not set\n# CONFIG_CRYPTO_HW is not set\n# CONFIG_CRYPTO_JITTERENTROPY is not set\n# CONFIG_CRYPTO_KEYWRAP is not set\n# CONFIG_CRYPTO_KHAZAD is not set\nCONFIG_CRYPTO_KPP=y\nCONFIG_CRYPTO_KPP2=y\nCONFIG_CRYPTO_LIB_AES=y\nCONFIG_CRYPTO_LIB_ARC4=y\n# CONFIG_CRYPTO_LIB_BLAKE2S is not set\n# CONFIG_CRYPTO_LIB_CHACHA is not set\n# CONFIG_CRYPTO_LIB_CHACHA20POLY1305 is not set\n# CONFIG_CRYPTO_LIB_CURVE25519 is not set\n# CONFIG_CRYPTO_LIB_POLY1305 is not set\nCONFIG_CRYPTO_LIB_POLY1305_RSIZE=9\n# CONFIG_CRYPTO_LRW is not set\n# CONFIG_CRYPTO_LZ4 is not set\n# CONFIG_CRYPTO_LZ4HC is not set\n# CONFIG_CRYPTO_LZO is not set\nCONFIG_CRYPTO_MANAGER=y\nCONFIG_CRYPTO_MANAGER2=y\nCONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y\n# CONFIG_CRYPTO_MCRYPTD is not set\n# CONFIG_CRYPTO_MD4 is not set\n# CONFIG_CRYPTO_MD5 is not set\n# CONFIG_CRYPTO_MICHAEL_MIC is not set\n# CONFIG_CRYPTO_MORUS1280 is not set\n# CONFIG_CRYPTO_MORUS1280_AVX2 is not set\n# CONFIG_CRYPTO_MORUS1280_SSE2 is not set\n# CONFIG_CRYPTO_MORUS640 is not set\n# CONFIG_CRYPTO_MORUS640_SSE2 is not set\n# CONFIG_CRYPTO_NHPOLY1305_NEON is not set\nCONFIG_CRYPTO_NULL=y\nCONFIG_CRYPTO_NULL2=y\n# CONFIG_CRYPTO_OFB is not set\n# CONFIG_CRYPTO_PCBC is not set\n# CONFIG_CRYPTO_PCOMP is not set\n# CONFIG_CRYPTO_PCOMP2 is not set\nCONFIG_CRYPTO_PCRYPT=y\n# CONFIG_CRYPTO_POLY1305 is not set\n# CONFIG_CRYPTO_POLY1305_ARM is not set\n# CONFIG_CRYPTO_POLY1305_MIPS is not set\n# CONFIG_CRYPTO_POLY1305_NEON is not set\n# CONFIG_CRYPTO_POLY1305_X86_64 is not set\n# CONFIG_CRYPTO_RMD128 is not set\n# CONFIG_CRYPTO_RMD160 is not set\n# CONFIG_CRYPTO_RMD256 is not set\n# CONFIG_CRYPTO_RMD320 is not set\n# CONFIG_CRYPTO_RNG is not set\n# CONFIG_CRYPTO_RSA is not set\n# CONFIG_CRYPTO_SALSA20 is not set\n# CONFIG_CRYPTO_SALSA20_586 is not set\n# CONFIG_CRYPTO_SEED is not set\n# CONFIG_CRYPTO_SEQIV is not set\n# CONFIG_CRYPTO_SERPENT is not set\n# CONFIG_CRYPTO_SHA1 is not set\n# CONFIG_CRYPTO_SHA1_ARM is not set\n# CONFIG_CRYPTO_SHA1_ARM64_CE is not set\n# CONFIG_CRYPTO_SHA1_ARM_CE is not set\n# CONFIG_CRYPTO_SHA1_ARM_NEON is not set\n# CONFIG_CRYPTO_SHA256 is not set\n# CONFIG_CRYPTO_SHA256_ARM is not set\n# CONFIG_CRYPTO_SHA256_ARM64 is not set\n# CONFIG_CRYPTO_SHA2_ARM64_CE is not set\n# CONFIG_CRYPTO_SHA2_ARM_CE is not set\n# CONFIG_CRYPTO_SHA3 is not set\n# CONFIG_CRYPTO_SHA3_ARM64 is not set\n# CONFIG_CRYPTO_SHA512 is not set\n# CONFIG_CRYPTO_SHA512_ARM is not set\n# CONFIG_CRYPTO_SHA512_ARM64 is not set\n# CONFIG_CRYPTO_SHA512_ARM64_CE is not set\n# CONFIG_CRYPTO_SIMD is not set\nCONFIG_CRYPTO_SKCIPHER=y\nCONFIG_CRYPTO_SKCIPHER2=y\n# CONFIG_CRYPTO_SM2 is not set\n# CONFIG_CRYPTO_SM3 is not set\n# CONFIG_CRYPTO_SM3_ARM64_CE is not set\n# CONFIG_CRYPTO_SM4 is not set\n# CONFIG_CRYPTO_SM4_ARM64_CE is not set\n# CONFIG_CRYPTO_SPECK is not set\n# CONFIG_CRYPTO_STATS is not set\n# CONFIG_CRYPTO_STREEBOG is not set\n# CONFIG_CRYPTO_TEA is not set\n# CONFIG_CRYPTO_TEST is not set\n# CONFIG_CRYPTO_TGR192 is not set\n# CONFIG_CRYPTO_TWOFISH is not set\n# CONFIG_CRYPTO_TWOFISH_586 is not set\n# CONFIG_CRYPTO_TWOFISH_COMMON is not set\n# CONFIG_CRYPTO_USER is not set\n# CONFIG_CRYPTO_USER_API_AEAD is not set\n# CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE is not set\n# CONFIG_CRYPTO_USER_API_HASH is not set\n# CONFIG_CRYPTO_USER_API_RNG is not set\n# CONFIG_CRYPTO_USER_API_RNG_CAVP is not set\n# CONFIG_CRYPTO_USER_API_SKCIPHER is not set\n# CONFIG_CRYPTO_VMAC is not set\n# CONFIG_CRYPTO_WP512 is not set\n# CONFIG_CRYPTO_XCBC is not set\n# CONFIG_CRYPTO_XTS is not set\n# CONFIG_CRYPTO_XXHASH is not set\n# CONFIG_CRYPTO_ZLIB is not set\n# CONFIG_CRYPTO_ZSTD is not set\n# CONFIG_CS5535_MFGPT is not set\n# CONFIG_CS89x0 is not set\n# CONFIG_CS89x0_PLATFORM is not set\n# CONFIG_CSD_LOCK_WAIT_DEBUG is not set\n# CONFIG_CUSE is not set\n# CONFIG_CW1200 is not set\n# CONFIG_CXD2880_SPI_DRV is not set\n# CONFIG_CXL_AFU_DRIVER_OPS is not set\n# CONFIG_CXL_BASE is not set\n# CONFIG_CXL_BUS is not set\n# CONFIG_CXL_EEH is not set\n# CONFIG_CXL_KERNEL_API is not set\n# CONFIG_CXL_LIB is not set\n# CONFIG_CYPRESS_FIRMWARE is not set\n# CONFIG_DA280 is not set\n# CONFIG_DA311 is not set\n# CONFIG_DAMON is not set\n# CONFIG_DAVICOM_PHY is not set\n# CONFIG_DAX is not set\n# CONFIG_DCB is not set\n# CONFIG_DDR is not set\n# CONFIG_DEBUG_ALIGN_RODATA is not set\n# CONFIG_DEBUG_ATOMIC_SLEEP is not set\n# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set\n# CONFIG_DEBUG_BUGVERBOSE is not set\n# CONFIG_DEBUG_CREDENTIALS is not set\n# CONFIG_DEBUG_DEVRES is not set\n# CONFIG_DEBUG_DRIVER is not set\n# CONFIG_DEBUG_EFI is not set\n# CONFIG_DEBUG_FORCE_FUNCTION_ALIGN_32B is not set\n# CONFIG_DEBUG_FORCE_FUNCTION_ALIGN_64B is not set\n# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set\nCONFIG_DEBUG_FS=y\nCONFIG_DEBUG_FS_ALLOW_ALL=y\n# CONFIG_DEBUG_FS_ALLOW_NONE is not set\n# CONFIG_DEBUG_FS_DISALLOW_MOUNT is not set\n# CONFIG_DEBUG_GPIO is not set\n# CONFIG_DEBUG_HIGHMEM is not set\n# CONFIG_DEBUG_ICEDCC is not set\n# CONFIG_DEBUG_INFO is not set\n# CONFIG_DEBUG_INFO_BTF is not set\n# CONFIG_DEBUG_INFO_COMPRESSED is not set\n# CONFIG_DEBUG_INFO_DWARF4 is not set\n# CONFIG_DEBUG_INFO_DWARF5 is not set\nCONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y\nCONFIG_DEBUG_INFO_REDUCED=y\n# CONFIG_DEBUG_INFO_SPLIT is not set\n# CONFIG_DEBUG_IRQFLAGS is not set\nCONFIG_DEBUG_KERNEL=y\n# CONFIG_DEBUG_KMAP_LOCAL is not set\n# CONFIG_DEBUG_KMEMLEAK is not set\n# CONFIG_DEBUG_KOBJECT is not set\n# CONFIG_DEBUG_KOBJECT_RELEASE is not set\n# CONFIG_DEBUG_LIST is not set\n# CONFIG_DEBUG_LL is not set\n# CONFIG_DEBUG_LL_UART_8250 is not set\n# CONFIG_DEBUG_LL_UART_PL01X is not set\n# CONFIG_DEBUG_LOCKDEP is not set\n# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set\n# CONFIG_DEBUG_LOCK_ALLOC is not set\n# CONFIG_DEBUG_MEMORY_INIT is not set\n# CONFIG_DEBUG_MISC is not set\n# CONFIG_DEBUG_MUTEXES is not set\n# CONFIG_DEBUG_NOTIFIERS is not set\n# CONFIG_DEBUG_NX_TEST is not set\n# CONFIG_DEBUG_OBJECTS is not set\n# CONFIG_DEBUG_PAGEALLOC is not set\n# CONFIG_DEBUG_PAGE_REF is not set\n# CONFIG_DEBUG_PERF_USE_VMALLOC is not set\n# CONFIG_DEBUG_PER_CPU_MAPS is not set\n# CONFIG_DEBUG_PINCTRL is not set\n# CONFIG_DEBUG_PI_LIST is not set\n# CONFIG_DEBUG_PLIST is not set\n# CONFIG_DEBUG_PREEMPT is not set\n# CONFIG_DEBUG_RODATA_TEST is not set\n# CONFIG_DEBUG_RSEQ is not set\n# CONFIG_DEBUG_RT_MUTEXES is not set\n# CONFIG_DEBUG_RWSEMS is not set\n# CONFIG_DEBUG_SECTION_MISMATCH is not set\n# CONFIG_DEBUG_SEMIHOSTING is not set\n# CONFIG_DEBUG_SG is not set\n# CONFIG_DEBUG_SHIRQ is not set\n# CONFIG_DEBUG_SLAB is not set\n# CONFIG_DEBUG_SPINLOCK is not set\n# CONFIG_DEBUG_STACKOVERFLOW is not set\n# CONFIG_DEBUG_STACK_USAGE is not set\n# CONFIG_DEBUG_STRICT_USER_COPY_CHECKS is not set\n# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set\n# CONFIG_DEBUG_TIMEKEEPING is not set\n# CONFIG_DEBUG_UART_8250_PALMCHIP is not set\n# CONFIG_DEBUG_UART_8250_WORD is not set\n# CONFIG_DEBUG_UART_BCM63XX is not set\n# CONFIG_DEBUG_UART_FLOW_CONTROL is not set\n# CONFIG_DEBUG_USER is not set\n# CONFIG_DEBUG_VIRTUAL is not set\n# CONFIG_DEBUG_VM is not set\n# CONFIG_DEBUG_VM_PGTABLE is not set\n# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set\n# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set\n# CONFIG_DEBUG_WX is not set\n# CONFIG_DEBUG_ZBOOT is not set\n# CONFIG_DECNET is not set\n# CONFIG_DEFAULT_CODEL is not set\nCONFIG_DEFAULT_CUBIC=y\nCONFIG_DEFAULT_DEADLINE=y\n# CONFIG_DEFAULT_FQ is not set\nCONFIG_DEFAULT_FQ_CODEL=y\nCONFIG_DEFAULT_HOSTNAME=\"(none)\"\nCONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120\nCONFIG_DEFAULT_INIT=\"\"\nCONFIG_DEFAULT_MMAP_MIN_ADDR=4096\nCONFIG_DEFAULT_NET_SCH=\"fq_codel\"\n# CONFIG_DEFAULT_NOOP is not set\n# CONFIG_DEFAULT_PFIFO_FAST is not set\n# CONFIG_DEFAULT_RENO is not set\nCONFIG_DEFAULT_SECURITY=\"\"\nCONFIG_DEFAULT_SECURITY_DAC=y\n# CONFIG_DEFAULT_SECURITY_SELINUX is not set\n# CONFIG_DEFAULT_SFQ is not set\nCONFIG_DEFAULT_TCP_CONG=\"cubic\"\nCONFIG_DEFCONFIG_LIST=\"/lib/modules/$UNAME_RELEASE/.config\"\n# CONFIG_DEFERRED_STRUCT_PAGE_INIT is not set\n# CONFIG_DELL_LAPTOP is not set\n# CONFIG_DELL_RBTN is not set\n# CONFIG_DELL_SMBIOS is not set\n# CONFIG_DELL_SMO8800 is not set\n# CONFIG_DEPRECATED_PARAM_STRUCT is not set\n# CONFIG_DETECT_HUNG_TASK is not set\n# CONFIG_DEVKMEM is not set\n# CONFIG_DEVMEM is not set\nCONFIG_DEVPORT=y\n# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set\n# CONFIG_DEVTMPFS is not set\n# CONFIG_DEVTMPFS_MOUNT is not set\n# CONFIG_DEV_DAX is not set\n# CONFIG_DGAP is not set\n# CONFIG_DGNC is not set\n# CONFIG_DHT11 is not set\n# CONFIG_DISCONTIGMEM_MANUAL is not set\n# CONFIG_DISPLAY_CONNECTOR_ANALOG_TV is not set\n# CONFIG_DISPLAY_CONNECTOR_DVI is not set\n# CONFIG_DISPLAY_CONNECTOR_HDMI is not set\n# CONFIG_DISPLAY_ENCODER_TFP410 is not set\n# CONFIG_DISPLAY_ENCODER_TPD12S015 is not set\n# CONFIG_DISPLAY_PANEL_DPI is not set\n# CONFIG_DISPLAY_PANEL_LGPHILIPS_LB035Q02 is not set\n# CONFIG_DISPLAY_PANEL_TPO_TD028TTEC1 is not set\n# CONFIG_DISPLAY_PANEL_TPO_TD043MTEA1 is not set\n# CONFIG_DL2K is not set\n# CONFIG_DLHL60D is not set\n# CONFIG_DLM is not set\n# CONFIG_DM9000 is not set\n# CONFIG_DMABUF_DEBUG is not set\n# CONFIG_DMABUF_HEAPS is not set\n# CONFIG_DMABUF_MOVE_NOTIFY is not set\n# CONFIG_DMABUF_SELFTESTS is not set\n# CONFIG_DMABUF_SYSFS_STATS is not set\n# CONFIG_DMADEVICES is not set\n# CONFIG_DMADEVICES_DEBUG is not set\n# CONFIG_DMARD06 is not set\n# CONFIG_DMARD09 is not set\n# CONFIG_DMARD10 is not set\n# CONFIG_DMASCC is not set\n# CONFIG_DMATEST is not set\n# CONFIG_DMA_API_DEBUG is not set\nCONFIG_DMA_COHERENT_POOL=y\nCONFIG_DMA_DECLARE_COHERENT=y\n# CONFIG_DMA_ENGINE is not set\n# CONFIG_DMA_FENCE_TRACE is not set\n# CONFIG_DMA_JZ4780 is not set\n# CONFIG_DMA_MAP_BENCHMARK is not set\nCONFIG_DMA_NONCOHERENT_MMAP=y\n# CONFIG_DMA_NOOP_OPS is not set\n# CONFIG_DMA_PERNUMA_CMA is not set\n# CONFIG_DMA_RESTRICTED_POOL is not set\n# CONFIG_DMA_SHARED_BUFFER is not set\n# CONFIG_DMA_VIRT_OPS is not set\n# CONFIG_DM_CACHE is not set\n# CONFIG_DM_CLONE is not set\n# CONFIG_DM_DEBUG is not set\n# CONFIG_DM_DELAY is not set\n# CONFIG_DM_DUST is not set\n# CONFIG_DM_EBS is not set\n# CONFIG_DM_ERA is not set\n# CONFIG_DM_FLAKEY is not set\n# CONFIG_DM_INTEGRITY is not set\n# CONFIG_DM_LOG_USERSPACE is not set\n# CONFIG_DM_LOG_WRITES is not set\n# CONFIG_DM_MQ_DEFAULT is not set\n# CONFIG_DM_MULTIPATH is not set\n# CONFIG_DM_RAID is not set\n# CONFIG_DM_SWITCH is not set\n# CONFIG_DM_THIN_PROVISIONING is not set\n# CONFIG_DM_UEVENT is not set\n# CONFIG_DM_UNSTRIPED is not set\n# CONFIG_DM_VERITY is not set\n# CONFIG_DM_WRITECACHE is not set\n# CONFIG_DM_ZERO is not set\n# CONFIG_DNET is not set\n# CONFIG_DNOTIFY is not set\n# CONFIG_DNS_RESOLVER is not set\nCONFIG_DOUBLEFAULT=y\n# CONFIG_DP83640_PHY is not set\n# CONFIG_DP83822_PHY is not set\n# CONFIG_DP83848_PHY is not set\n# CONFIG_DP83867_PHY is not set\n# CONFIG_DP83869_PHY is not set\n# CONFIG_DP83TC811_PHY is not set\n# CONFIG_DPOT_DAC is not set\n# CONFIG_DPS310 is not set\nCONFIG_DQL=y\n# CONFIG_DRAGONRISE_FF is not set\n# CONFIG_DRM is not set\n# CONFIG_DRM_AMDGPU is not set\n# CONFIG_DRM_AMDGPU_CIK is not set\n# CONFIG_DRM_AMDGPU_GART_DEBUGFS is not set\n# CONFIG_DRM_AMDGPU_SI is not set\n# CONFIG_DRM_AMDGPU_USERPTR is not set\n# CONFIG_DRM_AMD_ACP is not set\n# CONFIG_DRM_AMD_DC_DCN2_0 is not set\n# CONFIG_DRM_AMD_DC_DCN3_0 is not set\n# CONFIG_DRM_AMD_DC_HDCP is not set\n# CONFIG_DRM_AMD_DC_SI is not set\n# CONFIG_DRM_AMD_SECURE_DISPLAY is not set\n# CONFIG_DRM_ANALOGIX_ANX6345 is not set\n# CONFIG_DRM_ANALOGIX_ANX7625 is not set\n# CONFIG_DRM_ANALOGIX_ANX78XX is not set\n# CONFIG_DRM_ARCPGU is not set\n# CONFIG_DRM_ARMADA is not set\n# CONFIG_DRM_AST is not set\n# CONFIG_DRM_BOCHS is not set\n# CONFIG_DRM_CDNS_DSI is not set\n# CONFIG_DRM_CDNS_MHDP8546 is not set\n# CONFIG_DRM_CHIPONE_ICN6211 is not set\n# CONFIG_DRM_CHRONTEL_CH7033 is not set\n# CONFIG_DRM_CIRRUS_QEMU is not set\n# CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS is not set\n# CONFIG_DRM_DEBUG_MM is not set\n# CONFIG_DRM_DEBUG_SELFTEST is not set\n# CONFIG_DRM_DISPLAY_CONNECTOR is not set\n# CONFIG_DRM_DP_AUX_CHARDEV is not set\n# CONFIG_DRM_DP_CEC is not set\n# CONFIG_DRM_DUMB_VGA_DAC is not set\n# CONFIG_DRM_DW_HDMI_CEC is not set\n# CONFIG_DRM_ETNAVIV is not set\n# CONFIG_DRM_EXYNOS is not set\n# CONFIG_DRM_FBDEV_EMULATION is not set\n# CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM is not set\n# CONFIG_DRM_FSL_DCU is not set\n# CONFIG_DRM_GM12U320 is not set\n# CONFIG_DRM_GMA500 is not set\n# CONFIG_DRM_GUD is not set\n# CONFIG_DRM_HDLCD is not set\n# CONFIG_DRM_HISI_HIBMC is not set\n# CONFIG_DRM_HISI_KIRIN is not set\n# CONFIG_DRM_I2C_ADV7511 is not set\n# CONFIG_DRM_I2C_CH7006 is not set\n# CONFIG_DRM_I2C_NXP_TDA9950 is not set\n# CONFIG_DRM_I2C_NXP_TDA998X is not set\n# CONFIG_DRM_I2C_SIL164 is not set\n# CONFIG_DRM_I915 is not set\n# CONFIG_DRM_ITE_IT66121 is not set\n# CONFIG_DRM_KOMEDA is not set\n# CONFIG_DRM_LEGACY is not set\n# CONFIG_DRM_LIB_RANDOM is not set\n# CONFIG_DRM_LIMA is not set\n# CONFIG_DRM_LOAD_EDID_FIRMWARE is not set\n# CONFIG_DRM_LONTIUM_LT8912B is not set\n# CONFIG_DRM_LONTIUM_LT9611 is not set\n# CONFIG_DRM_LONTIUM_LT9611UXC is not set\n# CONFIG_DRM_LVDS_CODEC is not set\n# CONFIG_DRM_LVDS_ENCODER is not set\n# CONFIG_DRM_MALI_DISPLAY is not set\n# CONFIG_DRM_MCDE is not set\n# CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW is not set\n# CONFIG_DRM_MGAG200 is not set\n# CONFIG_DRM_MXSFB is not set\n# CONFIG_DRM_NOUVEAU is not set\n# CONFIG_DRM_NWL_MIPI_DSI is not set\n# CONFIG_DRM_NXP_PTN3460 is not set\n# CONFIG_DRM_OMAP is not set\n# CONFIG_DRM_PANEL_ABT_Y030XX067A is not set\n# CONFIG_DRM_PANEL_ARM_VERSATILE is not set\n# CONFIG_DRM_PANEL_ASUS_Z00T_TM5P5_NT35596 is not set\n# CONFIG_DRM_PANEL_BOE_HIMAX8279D is not set\n# CONFIG_DRM_PANEL_BOE_TV101WUM_NL6 is not set\n# CONFIG_DRM_PANEL_DSI_CM is not set\n# CONFIG_DRM_PANEL_ELIDA_KD35T133 is not set\n# CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02 is not set\n# CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D is not set\n# CONFIG_DRM_PANEL_ILITEK_IL9322 is not set\n# CONFIG_DRM_PANEL_ILITEK_ILI9341 is not set\n# CONFIG_DRM_PANEL_ILITEK_ILI9881C is not set\n# CONFIG_DRM_PANEL_INNOLUX_EJ030NA is not set\n# CONFIG_DRM_PANEL_INNOLUX_P079ZCA is not set\n# CONFIG_DRM_PANEL_JDI_LT070ME05000 is not set\n# CONFIG_DRM_PANEL_KHADAS_TS050 is not set\n# CONFIG_DRM_PANEL_KINGDISPLAY_KD097D04 is not set\n# CONFIG_DRM_PANEL_LEADTEK_LTK050H3146W is not set\n# CONFIG_DRM_PANEL_LEADTEK_LTK500HD1829 is not set\n# CONFIG_DRM_PANEL_LG_LB035Q02 is not set\n# CONFIG_DRM_PANEL_LG_LG4573 is not set\n# CONFIG_DRM_PANEL_LVDS is not set\n# CONFIG_DRM_PANEL_MANTIX_MLAF057WE51 is not set\n# CONFIG_DRM_PANEL_NEC_NL8048HL11 is not set\n# CONFIG_DRM_PANEL_NOVATEK_NT35510 is not set\n# CONFIG_DRM_PANEL_NOVATEK_NT36672A is not set\n# CONFIG_DRM_PANEL_NOVATEK_NT39016 is not set\n# CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO is not set\n# CONFIG_DRM_PANEL_ORISETECH_OTM8009A is not set\n# CONFIG_DRM_PANEL_OSD_OSD101T2587_53TS is not set\n# CONFIG_DRM_PANEL_PANASONIC_VVX10F034N00 is not set\n# CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN is not set\n# CONFIG_DRM_PANEL_RAYDIUM_RM67191 is not set\n# CONFIG_DRM_PANEL_RAYDIUM_RM68200 is not set\n# CONFIG_DRM_PANEL_ROCKTECH_JH057N00900 is not set\n# CONFIG_DRM_PANEL_RONBO_RB070D30 is not set\n# CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20 is not set\n# CONFIG_DRM_PANEL_SAMSUNG_DB7430 is not set\n# CONFIG_DRM_PANEL_SAMSUNG_LD9040 is not set\n# CONFIG_DRM_PANEL_SAMSUNG_S6D16D0 is not set\n# CONFIG_DRM_PANEL_SAMSUNG_S6E3HA2 is not set\n# CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03 is not set\n# CONFIG_DRM_PANEL_SAMSUNG_S6E63M0 is not set\n# CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01 is not set\n# CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0 is not set\n# CONFIG_DRM_PANEL_SAMSUNG_SOFEF00 is not set\n# CONFIG_DRM_PANEL_SEIKO_43WVF1G is not set\n# CONFIG_DRM_PANEL_SHARP_LQ101R1SX01 is not set\n# CONFIG_DRM_PANEL_SHARP_LS037V7DW01 is not set\n# CONFIG_DRM_PANEL_SHARP_LS043T1LE01 is not set\n# CONFIG_DRM_PANEL_SIMPLE is not set\n# CONFIG_DRM_PANEL_SITRONIX_ST7701 is not set\n# CONFIG_DRM_PANEL_SITRONIX_ST7703 is not set\n# CONFIG_DRM_PANEL_SITRONIX_ST7789V is not set\n# CONFIG_DRM_PANEL_SONY_ACX424AKP is not set\n# CONFIG_DRM_PANEL_SONY_ACX565AKM is not set\n# CONFIG_DRM_PANEL_TDO_TL070WSH30 is not set\n# CONFIG_DRM_PANEL_TPO_TD028TTEC1 is not set\n# CONFIG_DRM_PANEL_TPO_TD043MTEA1 is not set\n# CONFIG_DRM_PANEL_TPO_TPG110 is not set\n# CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA is not set\n# CONFIG_DRM_PANEL_VISIONOX_RM69299 is not set\n# CONFIG_DRM_PANEL_WIDECHIPS_WS2401 is not set\n# CONFIG_DRM_PANEL_XINPENG_XPP055C272 is not set\n# CONFIG_DRM_PANFROST is not set\n# CONFIG_DRM_PARADE_PS8622 is not set\n# CONFIG_DRM_PARADE_PS8640 is not set\n# CONFIG_DRM_PL111 is not set\n# CONFIG_DRM_QXL is not set\n# CONFIG_DRM_RADEON is not set\n# CONFIG_DRM_RADEON_USERPTR is not set\n# CONFIG_DRM_RCAR_DW_HDMI is not set\n# CONFIG_DRM_RCAR_LVDS is not set\n# CONFIG_DRM_SII902X is not set\n# CONFIG_DRM_SII9234 is not set\n# CONFIG_DRM_SIL_SII8620 is not set\n# CONFIG_DRM_SIMPLEDRM is not set\n# CONFIG_DRM_SIMPLE_BRIDGE is not set\n# CONFIG_DRM_STI is not set\n# CONFIG_DRM_STM is not set\n# CONFIG_DRM_SUN4I is not set\n# CONFIG_DRM_THINE_THC63LVD1024 is not set\n# CONFIG_DRM_TIDSS is not set\n# CONFIG_DRM_TILCDC is not set\n# CONFIG_DRM_TINYDRM is not set\n# CONFIG_DRM_TI_SN65DSI83 is not set\n# CONFIG_DRM_TI_SN65DSI86 is not set\n# CONFIG_DRM_TI_TFP410 is not set\n# CONFIG_DRM_TI_TPD12S015 is not set\n# CONFIG_DRM_TOSHIBA_TC358762 is not set\n# CONFIG_DRM_TOSHIBA_TC358764 is not set\n# CONFIG_DRM_TOSHIBA_TC358767 is not set\n# CONFIG_DRM_TOSHIBA_TC358768 is not set\n# CONFIG_DRM_TOSHIBA_TC358775 is not set\n# CONFIG_DRM_TVE200 is not set\n# CONFIG_DRM_UDL is not set\n# CONFIG_DRM_VBOXVIDEO is not set\n# CONFIG_DRM_VC4_HDMI_CEC is not set\n# CONFIG_DRM_VGEM is not set\n# CONFIG_DRM_VIRTIO_GPU is not set\n# CONFIG_DRM_VKMS is not set\n# CONFIG_DRM_VMWGFX is not set\n# CONFIG_DRM_XEN is not set\n# CONFIG_DS1682 is not set\n# CONFIG_DS1803 is not set\n# CONFIG_DS4424 is not set\n# CONFIG_DST_CACHE is not set\n# CONFIG_DTLK is not set\n# CONFIG_DUMMY is not set\nCONFIG_DUMMY_CONSOLE_COLUMNS=80\nCONFIG_DUMMY_CONSOLE_ROWS=25\n# CONFIG_DUMMY_IRQ is not set\n# CONFIG_DVB_A8293 is not set\n# CONFIG_DVB_AF9013 is not set\n# CONFIG_DVB_AF9033 is not set\n# CONFIG_DVB_AS102 is not set\n# CONFIG_DVB_ASCOT2E is not set\n# CONFIG_DVB_ATBM8830 is not set\n# CONFIG_DVB_AU8522_DTV is not set\n# CONFIG_DVB_AU8522_V4L is not set\n# CONFIG_DVB_B2C2_FLEXCOP_USB is not set\n# CONFIG_DVB_BCM3510 is not set\n# CONFIG_DVB_CORE is not set\n# CONFIG_DVB_CX22700 is not set\n# CONFIG_DVB_CX22702 is not set\n# CONFIG_DVB_CX24110 is not set\n# CONFIG_DVB_CX24116 is not set\n# CONFIG_DVB_CX24117 is not set\n# CONFIG_DVB_CX24120 is not set\n# CONFIG_DVB_CX24123 is not set\n# CONFIG_DVB_CXD2099 is not set\n# CONFIG_DVB_CXD2820R is not set\n# CONFIG_DVB_CXD2841ER is not set\n# CONFIG_DVB_CXD2880 is not set\n# CONFIG_DVB_DEMUX_SECTION_LOSS_LOG is not set\n# CONFIG_DVB_DIB3000MB is not set\n# CONFIG_DVB_DIB3000MC is not set\n# CONFIG_DVB_DIB7000M is not set\n# CONFIG_DVB_DIB7000P is not set\n# CONFIG_DVB_DIB8000 is not set\n# CONFIG_DVB_DIB9000 is not set\n# CONFIG_DVB_DRX39XYJ is not set\n# CONFIG_DVB_DRXD is not set\n# CONFIG_DVB_DRXK is not set\n# CONFIG_DVB_DS3000 is not set\n# CONFIG_DVB_DUMMY_FE is not set\n# CONFIG_DVB_DYNAMIC_MINORS is not set\n# CONFIG_DVB_EC100 is not set\n# CONFIG_DVB_FIREDTV is not set\n# CONFIG_DVB_HELENE is not set\n# CONFIG_DVB_HORUS3A is not set\n# CONFIG_DVB_ISL6405 is not set\n# CONFIG_DVB_ISL6421 is not set\n# CONFIG_DVB_ISL6423 is not set\n# CONFIG_DVB_IX2505V is not set\n# CONFIG_DVB_L64781 is not set\n# CONFIG_DVB_LG2160 is not set\n# CONFIG_DVB_LGDT3305 is not set\n# CONFIG_DVB_LGDT3306A is not set\n# CONFIG_DVB_LGDT330X is not set\n# CONFIG_DVB_LGS8GL5 is not set\n# CONFIG_DVB_LGS8GXX is not set\n# CONFIG_DVB_LNBH25 is not set\n# CONFIG_DVB_LNBH29 is not set\n# CONFIG_DVB_LNBP21 is not set\n# CONFIG_DVB_LNBP22 is not set\n# CONFIG_DVB_M88DS3103 is not set\n# CONFIG_DVB_M88RS2000 is not set\nCONFIG_DVB_MAX_ADAPTERS=16\n# CONFIG_DVB_MB86A16 is not set\n# CONFIG_DVB_MB86A20S is not set\n# CONFIG_DVB_MMAP is not set\n# CONFIG_DVB_MN88443X is not set\n# CONFIG_DVB_MN88472 is not set\n# CONFIG_DVB_MN88473 is not set\n# CONFIG_DVB_MT312 is not set\n# CONFIG_DVB_MT352 is not set\n# CONFIG_DVB_MXL5XX is not set\n# CONFIG_DVB_MXL692 is not set\n# CONFIG_DVB_NET is not set\n# CONFIG_DVB_NXT200X is not set\n# CONFIG_DVB_NXT6000 is not set\n# CONFIG_DVB_OR51132 is not set\n# CONFIG_DVB_OR51211 is not set\n# CONFIG_DVB_PLATFORM_DRIVERS is not set\n# CONFIG_DVB_PLL is not set\n# CONFIG_DVB_RTL2830 is not set\n# CONFIG_DVB_RTL2832 is not set\n# CONFIG_DVB_RTL2832_SDR is not set\n# CONFIG_DVB_S5H1409 is not set\n# CONFIG_DVB_S5H1411 is not set\n# CONFIG_DVB_S5H1420 is not set\n# CONFIG_DVB_S5H1432 is not set\n# CONFIG_DVB_S921 is not set\n# CONFIG_DVB_SI2165 is not set\n# CONFIG_DVB_SI2168 is not set\n# CONFIG_DVB_SI21XX is not set\n# CONFIG_DVB_SP2 is not set\n# CONFIG_DVB_SP8870 is not set\n# CONFIG_DVB_SP887X is not set\n# CONFIG_DVB_STB0899 is not set\n# CONFIG_DVB_STB6000 is not set\n# CONFIG_DVB_STB6100 is not set\n# CONFIG_DVB_STV0288 is not set\n# CONFIG_DVB_STV0297 is not set\n# CONFIG_DVB_STV0299 is not set\n# CONFIG_DVB_STV0367 is not set\n# CONFIG_DVB_STV0900 is not set\n# CONFIG_DVB_STV090x is not set\n# CONFIG_DVB_STV0910 is not set\n# CONFIG_DVB_STV6110 is not set\n# CONFIG_DVB_STV6110x is not set\n# CONFIG_DVB_STV6111 is not set\n# CONFIG_DVB_TC90522 is not set\n# CONFIG_DVB_TDA10021 is not set\n# CONFIG_DVB_TDA10023 is not set\n# CONFIG_DVB_TDA10048 is not set\n# CONFIG_DVB_TDA1004X is not set\n# CONFIG_DVB_TDA10071 is not set\n# CONFIG_DVB_TDA10086 is not set\n# CONFIG_DVB_TDA18271C2DD is not set\n# CONFIG_DVB_TDA665x is not set\n# CONFIG_DVB_TDA8083 is not set\n# CONFIG_DVB_TDA8261 is not set\n# CONFIG_DVB_TDA826X is not set\n# CONFIG_DVB_TEST_DRIVERS is not set\n# CONFIG_DVB_TS2020 is not set\n# CONFIG_DVB_TTUSB_BUDGET is not set\n# CONFIG_DVB_TTUSB_DEC is not set\n# CONFIG_DVB_TUA6100 is not set\n# CONFIG_DVB_TUNER_CX24113 is not set\n# CONFIG_DVB_TUNER_DIB0070 is not set\n# CONFIG_DVB_TUNER_DIB0090 is not set\n# CONFIG_DVB_TUNER_ITD1000 is not set\n# CONFIG_DVB_ULE_DEBUG is not set\n# CONFIG_DVB_USB_V2 is not set\n# CONFIG_DVB_VES1820 is not set\n# CONFIG_DVB_VES1X93 is not set\n# CONFIG_DVB_ZD1301_DEMOD is not set\n# CONFIG_DVB_ZL10036 is not set\n# CONFIG_DVB_ZL10039 is not set\n# CONFIG_DVB_ZL10353 is not set\n# CONFIG_DWC_XLGMAC is not set\n# CONFIG_DWMAC_DWC_QOS_ETH is not set\n# CONFIG_DWMAC_INTEL_PLAT is not set\n# CONFIG_DWMAC_IPQ806X is not set\n# CONFIG_DWMAC_LOONGSON is not set\n# CONFIG_DWMAC_LPC18XX is not set\n# CONFIG_DWMAC_MESON is not set\n# CONFIG_DWMAC_ROCKCHIP is not set\n# CONFIG_DWMAC_SOCFPGA is not set\n# CONFIG_DWMAC_STI is not set\n# CONFIG_DW_AXI_DMAC is not set\n# CONFIG_DW_DMAC is not set\n# CONFIG_DW_DMAC_PCI is not set\n# CONFIG_DW_EDMA is not set\n# CONFIG_DW_EDMA_PCIE is not set\n# CONFIG_DW_WATCHDOG is not set\n# CONFIG_DW_XDATA_PCIE is not set\n# CONFIG_DYNAMIC_DEBUG is not set\nCONFIG_DYNAMIC_DEBUG_CORE=y\n# CONFIG_E100 is not set\n# CONFIG_E1000 is not set\n# CONFIG_E1000E is not set\n# CONFIG_E1000E_HWTS is not set\n# CONFIG_EARLY_PRINTK_8250 is not set\n# CONFIG_EARLY_PRINTK_USB_XDBC is not set\n# CONFIG_EBC_C384_WDT is not set\n# CONFIG_ECHO is not set\n# CONFIG_ECRYPT_FS is not set\n# CONFIG_EDAC is not set\n# CONFIG_EEEPC_LAPTOP is not set\n# CONFIG_EEPROM_93CX6 is not set\n# CONFIG_EEPROM_93XX46 is not set\n# CONFIG_EEPROM_AT24 is not set\n# CONFIG_EEPROM_AT25 is not set\n# CONFIG_EEPROM_DIGSY_MTC_CFG is not set\n# CONFIG_EEPROM_EE1004 is not set\n# CONFIG_EEPROM_IDT_89HPESX is not set\n# CONFIG_EEPROM_LEGACY is not set\n# CONFIG_EEPROM_MAX6875 is not set\n# CONFIG_EFI is not set\nCONFIG_EFI_PARTITION=y\n# CONFIG_EFI_VARS_PSTORE is not set\n# CONFIG_EFS_FS is not set\nCONFIG_ELFCORE=y\n# CONFIG_ELF_CORE is not set\n# CONFIG_EMAC_ROCKCHIP is not set\nCONFIG_EMBEDDED=y\n# CONFIG_EM_TIMER_STI is not set\n# CONFIG_ENABLE_MUST_CHECK is not set\nCONFIG_ENABLE_WARN_DEPRECATED=y\n# CONFIG_ENA_ETHERNET is not set\n# CONFIG_ENC28J60 is not set\n# CONFIG_ENCLOSURE_SERVICES is not set\n# CONFIG_ENCRYPTED_KEYS is not set\n# CONFIG_ENCX24J600 is not set\n# CONFIG_ENERGY_MODEL is not set\n# CONFIG_ENIC is not set\n# CONFIG_ENVELOPE_DETECTOR is not set\n# CONFIG_EPAPR_PARAVIRT is not set\n# CONFIG_EPIC100 is not set\nCONFIG_EPOLL=y\n# CONFIG_EQUALIZER is not set\n# CONFIG_EROFS_FS is not set\n# CONFIG_ET131X is not set\nCONFIG_ETHERNET=y\n# CONFIG_ETHOC is not set\nCONFIG_ETHTOOL_NETLINK=y\nCONFIG_EVENTFD=y\n# CONFIG_EVM is not set\n# CONFIG_EXFAT_FS is not set\nCONFIG_EXPERT=y\nCONFIG_EXPORTFS=y\n# CONFIG_EXPORTFS_BLOCK_OPS is not set\n# CONFIG_EXT2_FS is not set\nCONFIG_EXT2_FS_XATTR=y\n# CONFIG_EXT3_FS is not set\n# CONFIG_EXT4_DEBUG is not set\n# CONFIG_EXT4_ENCRYPTION is not set\n# CONFIG_EXT4_FS is not set\n# CONFIG_EXT4_FS_POSIX_ACL is not set\n# CONFIG_EXT4_FS_SECURITY is not set\nCONFIG_EXT4_USE_FOR_EXT2=y\n# CONFIG_EXTCON is not set\n# CONFIG_EXTCON_ADC_JACK is not set\n# CONFIG_EXTCON_ARIZONA is not set\n# CONFIG_EXTCON_AXP288 is not set\n# CONFIG_EXTCON_FSA9480 is not set\n# CONFIG_EXTCON_GPIO is not set\n# CONFIG_EXTCON_INTEL_INT3496 is not set\n# CONFIG_EXTCON_MAX3355 is not set\n# CONFIG_EXTCON_PTN5150 is not set\n# CONFIG_EXTCON_QCOM_SPMI_MISC is not set\n# CONFIG_EXTCON_RT8973A is not set\n# CONFIG_EXTCON_SM5502 is not set\n# CONFIG_EXTCON_USBC_TUSB320 is not set\n# CONFIG_EXTCON_USB_GPIO is not set\nCONFIG_EXTRA_FIRMWARE=\"\"\nCONFIG_EXTRA_TARGETS=\"\"\n# CONFIG_EXYNOS_ADC is not set\n# CONFIG_EXYNOS_VIDEO is not set\n# CONFIG_EZCHIP_NPS_MANAGEMENT_ENET is not set\n# CONFIG_EZX_PCAP is not set\n# CONFIG_F2FS_CHECK_FS is not set\n# CONFIG_F2FS_FAULT_INJECTION is not set\n# CONFIG_F2FS_FS is not set\n# CONFIG_F2FS_FS_COMPRESSION is not set\n# CONFIG_F2FS_FS_ENCRYPTION is not set\n# CONFIG_F2FS_FS_POSIX_ACL is not set\n# CONFIG_F2FS_FS_SECURITY is not set\nCONFIG_F2FS_FS_XATTR=y\n# CONFIG_F2FS_IOSTAT is not set\n# CONFIG_F2FS_IO_TRACE is not set\nCONFIG_F2FS_STAT_FS=y\n# CONFIG_FAILOVER is not set\n# CONFIG_FAIR_GROUP_SCHED is not set\n# CONFIG_FANOTIFY is not set\n# CONFIG_FANOTIFY_ACCESS_PERMISSIONS is not set\nCONFIG_FAT_DEFAULT_CODEPAGE=437\nCONFIG_FAT_DEFAULT_IOCHARSET=\"iso8859-1\"\n# CONFIG_FAT_DEFAULT_UTF8 is not set\n# CONFIG_FAT_FS is not set\n# CONFIG_FAULT_INJECTION is not set\n# CONFIG_FB is not set\n# CONFIG_FB_3DFX is not set\n# CONFIG_FB_ARC is not set\n# CONFIG_FB_ARK is not set\n# CONFIG_FB_ARMCLCD is not set\n# CONFIG_FB_ASILIANT is not set\n# CONFIG_FB_ATY is not set\n# CONFIG_FB_ATY128 is not set\n# CONFIG_FB_AUO_K190X is not set\n# CONFIG_FB_BACKLIGHT is not set\n# CONFIG_FB_BIG_ENDIAN is not set\n# CONFIG_FB_BOOT_VESA_SUPPORT is not set\n# CONFIG_FB_BOTH_ENDIAN is not set\n# CONFIG_FB_BROADSHEET is not set\n# CONFIG_FB_CARMINE is not set\n# CONFIG_FB_CFB_COPYAREA is not set\n# CONFIG_FB_CFB_FILLRECT is not set\n# CONFIG_FB_CFB_IMAGEBLIT is not set\n# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set\n# CONFIG_FB_CIRRUS is not set\n# CONFIG_FB_CYBER2000 is not set\n# CONFIG_FB_DA8XX is not set\n# CONFIG_FB_DDC is not set\n# CONFIG_FB_FLEX is not set\n# CONFIG_FB_FOREIGN_ENDIAN is not set\n# CONFIG_FB_FSL_DIU is not set\n# CONFIG_FB_GEODE is not set\n# CONFIG_FB_GOLDFISH is not set\n# CONFIG_FB_HGA is not set\n# CONFIG_FB_I740 is not set\n# CONFIG_FB_IBM_GXT4500 is not set\n# CONFIG_FB_IMSTT is not set\n# CONFIG_FB_IMX is not set\n# CONFIG_FB_KYRO is not set\n# CONFIG_FB_LE80578 is not set\n# CONFIG_FB_LITTLE_ENDIAN is not set\n# CONFIG_FB_MACMODES is not set\n# CONFIG_FB_MATROX is not set\n# CONFIG_FB_MB862XX is not set\n# CONFIG_FB_METRONOME is not set\n# CONFIG_FB_MODE_HELPERS is not set\n# CONFIG_FB_MXS is not set\n# CONFIG_FB_N411 is not set\n# CONFIG_FB_NEOMAGIC is not set\nCONFIG_FB_NOTIFY=y\n# CONFIG_FB_NVIDIA is not set\n# CONFIG_FB_OF is not set\n# CONFIG_FB_OMAP2 is not set\n# CONFIG_FB_OPENCORES is not set\n# CONFIG_FB_PM2 is not set\n# CONFIG_FB_PM3 is not set\n# CONFIG_FB_PS3 is not set\n# CONFIG_FB_PXA is not set\n# CONFIG_FB_RADEON is not set\n# CONFIG_FB_RIVA is not set\n# CONFIG_FB_S1D13XXX is not set\n# CONFIG_FB_S3 is not set\n# CONFIG_FB_SAVAGE is not set\n# CONFIG_FB_SIMPLE is not set\n# CONFIG_FB_SIS is not set\n# CONFIG_FB_SM712 is not set\n# CONFIG_FB_SM750 is not set\n# CONFIG_FB_SMSCUFX is not set\n# CONFIG_FB_SSD1307 is not set\n# CONFIG_FB_SVGALIB is not set\n# CONFIG_FB_SYS_COPYAREA is not set\n# CONFIG_FB_SYS_FILLRECT is not set\n# CONFIG_FB_SYS_FOPS is not set\n# CONFIG_FB_SYS_IMAGEBLIT is not set\n# CONFIG_FB_TFT is not set\n# CONFIG_FB_TFT_AGM1264K_FL is not set\n# CONFIG_FB_TFT_BD663474 is not set\n# CONFIG_FB_TFT_FBTFT_DEVICE is not set\n# CONFIG_FB_TFT_HX8340BN is not set\n# CONFIG_FB_TFT_HX8347D is not set\n# CONFIG_FB_TFT_HX8353D is not set\n# CONFIG_FB_TFT_HX8357D is not set\n# CONFIG_FB_TFT_ILI9163 is not set\n# CONFIG_FB_TFT_ILI9320 is not set\n# CONFIG_FB_TFT_ILI9325 is not set\n# CONFIG_FB_TFT_ILI9340 is not set\n# CONFIG_FB_TFT_ILI9341 is not set\n# CONFIG_FB_TFT_ILI9481 is not set\n# CONFIG_FB_TFT_ILI9486 is not set\n# CONFIG_FB_TFT_PCD8544 is not set\n# CONFIG_FB_TFT_RA8875 is not set\n# CONFIG_FB_TFT_S6D02A1 is not set\n# CONFIG_FB_TFT_S6D1121 is not set\n# CONFIG_FB_TFT_SEPS525 is not set\n# CONFIG_FB_TFT_SH1106 is not set\n# CONFIG_FB_TFT_SSD1289 is not set\n# CONFIG_FB_TFT_SSD1305 is not set\n# CONFIG_FB_TFT_SSD1306 is not set\n# CONFIG_FB_TFT_SSD1325 is not set\n# CONFIG_FB_TFT_SSD1331 is not set\n# CONFIG_FB_TFT_SSD1351 is not set\n# CONFIG_FB_TFT_ST7735R is not set\n# CONFIG_FB_TFT_ST7789V is not set\n# CONFIG_FB_TFT_TINYLCD is not set\n# CONFIG_FB_TFT_TLS8204 is not set\n# CONFIG_FB_TFT_UC1611 is not set\n# CONFIG_FB_TFT_UC1701 is not set\n# CONFIG_FB_TFT_UPD161704 is not set\n# CONFIG_FB_TFT_WATTEROTT is not set\n# CONFIG_FB_TILEBLITTING is not set\n# CONFIG_FB_TMIO is not set\n# CONFIG_FB_TRIDENT is not set\n# CONFIG_FB_UDL is not set\n# CONFIG_FB_UVESA is not set\n# CONFIG_FB_VGA16 is not set\n# CONFIG_FB_VIA is not set\n# CONFIG_FB_VIRTUAL is not set\n# CONFIG_FB_VOODOO1 is not set\n# CONFIG_FB_VT8623 is not set\n# CONFIG_FB_XGI is not set\n# CONFIG_FCOE is not set\n# CONFIG_FCOE_FNIC is not set\n# CONFIG_FDDI is not set\n# CONFIG_FEALNX is not set\n# CONFIG_FENCE_TRACE is not set\n# CONFIG_FHANDLE is not set\nCONFIG_FIB_RULES=y\n# CONFIG_FIELDBUS_DEV is not set\nCONFIG_FILE_LOCKING=y\n# CONFIG_FIND_BIT_BENCHMARK is not set\n# CONFIG_FIREWIRE is not set\n# CONFIG_FIREWIRE_NOSY is not set\n# CONFIG_FIREWIRE_SERIAL is not set\n# CONFIG_FIRMWARE_EDID is not set\n# CONFIG_FIRMWARE_IN_KERNEL is not set\n# CONFIG_FIRMWARE_MEMMAP is not set\n# CONFIG_FIT_PARTITION is not set\n# CONFIG_FIXED_PHY is not set\nCONFIG_FLATMEM=y\nCONFIG_FLATMEM_MANUAL=y\nCONFIG_FLAT_NODE_MEM_MAP=y\n# CONFIG_FM10K is not set\n# CONFIG_FMC is not set\n# CONFIG_FONTS is not set\n# CONFIG_FONT_6x8 is not set\n# CONFIG_FONT_TER16x32 is not set\n# CONFIG_FORCEDETH is not set\nCONFIG_FORCE_MAX_ZONEORDER=11\nCONFIG_FORTIFY_SOURCE=y\n# CONFIG_FPGA is not set\n# CONFIG_FRAMEBUFFER_CONSOLE is not set\n# CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER is not set\n# CONFIG_FRAMEBUFFER_CONSOLE_LEGACY_ACCELERATION is not set\n# CONFIG_FRAME_POINTER is not set\nCONFIG_FRAME_WARN=1024\n# CONFIG_FREEZER is not set\n# CONFIG_FRONTSWAP is not set\n# CONFIG_FSCACHE is not set\n# CONFIG_FSI is not set\n# CONFIG_FSL_EDMA is not set\n# CONFIG_FSL_ENETC is not set\n# CONFIG_FSL_ENETC_IERB is not set\n# CONFIG_FSL_ENETC_MDIO is not set\n# CONFIG_FSL_ENETC_VF is not set\n# CONFIG_FSL_ERRATUM_A008585 is not set\n# CONFIG_FSL_MC_BUS is not set\n# CONFIG_FSL_PQ_MDIO is not set\n# CONFIG_FSL_QDMA is not set\n# CONFIG_FSL_RCPM is not set\n# CONFIG_FSL_XGMAC_MDIO is not set\nCONFIG_FSNOTIFY=y\n# CONFIG_FS_DAX is not set\n# CONFIG_FS_ENCRYPTION is not set\n# CONFIG_FS_POSIX_ACL is not set\n# CONFIG_FS_VERITY is not set\n# CONFIG_FTGMAC100 is not set\n# CONFIG_FTL is not set\n# CONFIG_FTMAC100 is not set\n# CONFIG_FTRACE is not set\n# CONFIG_FTRACE_RECORD_RECURSION is not set\n# CONFIG_FTRACE_STARTUP_TEST is not set\n# CONFIG_FTR_FIXUP_SELFTEST is not set\n# CONFIG_FTWDT010_WATCHDOG is not set\n# CONFIG_FUJITSU_ERRATUM_010001 is not set\n# CONFIG_FUJITSU_ES is not set\n# CONFIG_FUJITSU_LAPTOP is not set\n# CONFIG_FUJITSU_TABLET is not set\n# CONFIG_FUNCTION_TRACER is not set\n# CONFIG_FUSE_FS is not set\n# CONFIG_FUSION is not set\n# CONFIG_FUSION_FC is not set\n# CONFIG_FUSION_SAS is not set\n# CONFIG_FUSION_SPI is not set\nCONFIG_FUTEX=y\nCONFIG_FUTEX_PI=y\n# CONFIG_FW_CFG_SYSFS is not set\nCONFIG_FW_LOADER=y\n# CONFIG_FW_LOADER_COMPRESS is not set\nCONFIG_FW_LOADER_USER_HELPER=y\nCONFIG_FW_LOADER_USER_HELPER_FALLBACK=y\n# CONFIG_FXAS21002C is not set\n# CONFIG_FXLS8962AF_I2C is not set\n# CONFIG_FXLS8962AF_SPI is not set\n# CONFIG_FXOS8700_I2C is not set\n# CONFIG_FXOS8700_SPI is not set\nCONFIG_GACT_PROB=y\n# CONFIG_GADGET_UAC1 is not set\n# CONFIG_GAMEPORT is not set\n# CONFIG_GATEWORKS_GW16083 is not set\n# CONFIG_GCC_PLUGINS is not set\n# CONFIG_GCOV is not set\n# CONFIG_GCOV_KERNEL is not set\n# CONFIG_GDB_SCRIPTS is not set\n# CONFIG_GEMINI_ETHERNET is not set\n# CONFIG_GENERIC_ADC_BATTERY is not set\n# CONFIG_GENERIC_ADC_THERMAL is not set\nCONFIG_GENERIC_CALIBRATE_DELAY=y\n# CONFIG_GENERIC_CPU_DEVICES is not set\nCONFIG_GENERIC_HWEIGHT=y\n# CONFIG_GENERIC_IRQ_DEBUGFS is not set\nCONFIG_GENERIC_IRQ_IPI=y\nCONFIG_GENERIC_IRQ_PROBE=y\nCONFIG_GENERIC_NET_UTILS=y\n# CONFIG_GENERIC_PHY is not set\nCONFIG_GENERIC_PTDUMP=y\nCONFIG_GENERIC_VDSO_TIME_NS=y\n# CONFIG_GENEVE is not set\n# CONFIG_GENWQE is not set\n# CONFIG_GFS2_FS is not set\n# CONFIG_GIGASET_CAPI is not set\n# CONFIG_GIGASET_DEBUG is not set\n# CONFIG_GIGASET_DUMMYLL is not set\n# CONFIG_GLOB_SELFTEST is not set\n# CONFIG_GNSS is not set\n# CONFIG_GOLDFISH is not set\n# CONFIG_GOOGLE_FIRMWARE is not set\n# CONFIG_GOOGLE_FRAMEBUFFER_COREBOOT is not set\n# CONFIG_GOOGLE_MEMCONSOLE_X86_LEGACY is not set\n# CONFIG_GOOGLE_SMI is not set\n# CONFIG_GP2AP002 is not set\n# CONFIG_GP2AP020A00F is not set\n# CONFIG_GPD_POCKET_FAN is not set\n# CONFIG_GPIOLIB is not set\nCONFIG_GPIOLIB_FASTPATH_LIMIT=512\n# CONFIG_GPIO_104_DIO_48E is not set\n# CONFIG_GPIO_104_IDIO_16 is not set\n# CONFIG_GPIO_104_IDI_48 is not set\n# CONFIG_GPIO_74X164 is not set\n# CONFIG_GPIO_74XX_MMIO is not set\n# CONFIG_GPIO_ADNP is not set\n# CONFIG_GPIO_ADP5588 is not set\n# CONFIG_GPIO_AGGREGATOR is not set\n# CONFIG_GPIO_ALTERA is not set\n# CONFIG_GPIO_AMD8111 is not set\n# CONFIG_GPIO_AMDPT is not set\n# CONFIG_GPIO_AMD_FCH is not set\n# CONFIG_GPIO_BCM_KONA is not set\n# CONFIG_GPIO_BT8XX is not set\n# CONFIG_GPIO_CADENCE is not set\n# CONFIG_GPIO_CASCADE is not set\n# CONFIG_GPIO_CDEV is not set\n# CONFIG_GPIO_CDEV_V1 is not set\n# CONFIG_GPIO_CS5535 is not set\n# CONFIG_GPIO_DWAPB is not set\n# CONFIG_GPIO_EM is not set\n# CONFIG_GPIO_EXAR is not set\n# CONFIG_GPIO_F7188X is not set\n# CONFIG_GPIO_FTGPIO010 is not set\n# CONFIG_GPIO_GENERIC_PLATFORM is not set\n# CONFIG_GPIO_GPIO_MM is not set\n# CONFIG_GPIO_GRGPIO is not set\n# CONFIG_GPIO_GW_PLD is not set\n# CONFIG_GPIO_HLWD is not set\n# CONFIG_GPIO_ICH is not set\n# CONFIG_GPIO_IT87 is not set\n# CONFIG_GPIO_LOGICVC is not set\n# CONFIG_GPIO_LYNXPOINT is not set\n# CONFIG_GPIO_MAX3191X is not set\n# CONFIG_GPIO_MAX7300 is not set\n# CONFIG_GPIO_MAX7301 is not set\n# CONFIG_GPIO_MAX732X is not set\n# CONFIG_GPIO_MB86S7X is not set\n# CONFIG_GPIO_MC33880 is not set\n# CONFIG_GPIO_MCP23S08 is not set\n# CONFIG_GPIO_ML_IOH is not set\n# CONFIG_GPIO_MOCKUP is not set\n# CONFIG_GPIO_MPC8XXX is not set\n# CONFIG_GPIO_PCA953X is not set\n# CONFIG_GPIO_PCA953X_IRQ is not set\n# CONFIG_GPIO_PCA9570 is not set\n# CONFIG_GPIO_PCF857X is not set\n# CONFIG_GPIO_PCH is not set\n# CONFIG_GPIO_PCIE_IDIO_24 is not set\n# CONFIG_GPIO_PCI_IDIO_16 is not set\n# CONFIG_GPIO_PISOSR is not set\n# CONFIG_GPIO_PL061 is not set\n# CONFIG_GPIO_RCAR is not set\n# CONFIG_GPIO_RDC321X is not set\n# CONFIG_GPIO_SAMA5D2_PIOBU is not set\n# CONFIG_GPIO_SCH is not set\n# CONFIG_GPIO_SCH311X is not set\n# CONFIG_GPIO_SIFIVE is not set\n# CONFIG_GPIO_SX150X is not set\n# CONFIG_GPIO_SYSCON is not set\nCONFIG_GPIO_SYSFS=y\n# CONFIG_GPIO_TPIC2810 is not set\n# CONFIG_GPIO_TS4900 is not set\n# CONFIG_GPIO_TS5500 is not set\n# CONFIG_GPIO_VIRTIO is not set\n# CONFIG_GPIO_VX855 is not set\n# CONFIG_GPIO_WATCHDOG is not set\n# CONFIG_GPIO_WINBOND is not set\n# CONFIG_GPIO_WS16C48 is not set\n# CONFIG_GPIO_XGENE is not set\n# CONFIG_GPIO_XILINX is not set\n# CONFIG_GPIO_XRA1403 is not set\n# CONFIG_GPIO_ZEVIO is not set\n# CONFIG_GPIO_ZX is not set\n# CONFIG_GREENASIA_FF is not set\n# CONFIG_GREYBUS is not set\n# CONFIG_GS_FPGABOOT is not set\n# CONFIG_GTP is not set\n# CONFIG_GUP_BENCHMARK is not set\n# CONFIG_GUP_TEST is not set\n# CONFIG_GVE is not set\n# CONFIG_HABANA_AI is not set\n# CONFIG_HAMACHI is not set\n# CONFIG_HAMRADIO is not set\n# CONFIG_HAPPYMEAL is not set\nCONFIG_HARDENED_USERCOPY=y\n# CONFIG_HARDENED_USERCOPY_FALLBACK is not set\n# CONFIG_HARDENED_USERCOPY_PAGESPAN is not set\nCONFIG_HARDEN_BRANCH_HISTORY=y\nCONFIG_HARDEN_EL2_VECTORS=y\n# CONFIG_HARDLOCKUP_DETECTOR is not set\n# CONFIG_HAVE_ARM_ARCH_TIMER is not set\n# CONFIG_HCALL_STATS is not set\n# CONFIG_HDC100X is not set\n# CONFIG_HDC2010 is not set\n# CONFIG_HDLC is not set\n# CONFIG_HDLC_CISCO is not set\n# CONFIG_HDLC_FR is not set\n# CONFIG_HDLC_PPP is not set\n# CONFIG_HDLC_RAW is not set\n# CONFIG_HDLC_RAW_ETH is not set\n# CONFIG_HDMI_LPE_AUDIO is not set\n# CONFIG_HDQ_MASTER_OMAP is not set\n# CONFIG_HEADERS_CHECK is not set\n# CONFIG_HEADERS_INSTALL is not set\n# CONFIG_HEADER_TEST is not set\n# CONFIG_HERMES is not set\n# CONFIG_HFSPLUS_FS is not set\n# CONFIG_HFSPLUS_FS_POSIX_ACL is not set\n# CONFIG_HFS_FS is not set\n# CONFIG_HFS_FS_POSIX_ACL is not set\n# CONFIG_HI6421V600_IRQ is not set\n# CONFIG_HI8435 is not set\n# CONFIG_HIBERNATION is not set\n# CONFIG_HID is not set\n# CONFIG_HIDRAW is not set\n# CONFIG_HID_A4TECH is not set\n# CONFIG_HID_ACCUTOUCH is not set\n# CONFIG_HID_ACRUX is not set\n# CONFIG_HID_ACRUX_FF is not set\n# CONFIG_HID_ALPS is not set\n# CONFIG_HID_APPLE is not set\n# CONFIG_HID_APPLEIR is not set\n# CONFIG_HID_ASUS is not set\n# CONFIG_HID_AUREAL is not set\n# CONFIG_HID_BATTERY_STRENGTH is not set\n# CONFIG_HID_BELKIN is not set\n# CONFIG_HID_BETOP_FF is not set\n# CONFIG_HID_BIGBEN_FF is not set\n# CONFIG_HID_CHERRY is not set\n# CONFIG_HID_CHICONY is not set\n# CONFIG_HID_CMEDIA is not set\n# CONFIG_HID_CORSAIR is not set\n# CONFIG_HID_COUGAR is not set\n# CONFIG_HID_CP2112 is not set\n# CONFIG_HID_CREATIVE_SB0540 is not set\n# CONFIG_HID_CYPRESS is not set\n# CONFIG_HID_DRAGONRISE is not set\n# CONFIG_HID_ELAN is not set\n# CONFIG_HID_ELECOM is not set\n# CONFIG_HID_ELO is not set\n# CONFIG_HID_EMS_FF is not set\n# CONFIG_HID_EZKEY is not set\n# CONFIG_HID_FT260 is not set\n# CONFIG_HID_GEMBIRD is not set\n# CONFIG_HID_GENERIC is not set\n# CONFIG_HID_GFRM is not set\n# CONFIG_HID_GLORIOUS is not set\n# CONFIG_HID_GOOGLE_HAMMER is not set\n# CONFIG_HID_GREENASIA is not set\n# CONFIG_HID_GT683R is not set\n# CONFIG_HID_GYRATION is not set\n# CONFIG_HID_HOLTEK is not set\n# CONFIG_HID_ICADE is not set\n# CONFIG_HID_ITE is not set\n# CONFIG_HID_JABRA is not set\n# CONFIG_HID_KENSINGTON is not set\n# CONFIG_HID_KEYTOUCH is not set\n# CONFIG_HID_KYE is not set\n# CONFIG_HID_LCPOWER is not set\n# CONFIG_HID_LED is not set\n# CONFIG_HID_LENOVO is not set\n# CONFIG_HID_LOGITECH is not set\n# CONFIG_HID_LOGITECH_DJ is not set\n# CONFIG_HID_LOGITECH_HIDPP is not set\n# CONFIG_HID_MACALLY is not set\n# CONFIG_HID_MAGICMOUSE is not set\n# CONFIG_HID_MALTRON is not set\n# CONFIG_HID_MAYFLASH is not set\n# CONFIG_HID_MCP2221 is not set\n# CONFIG_HID_MICROSOFT is not set\n# CONFIG_HID_MONTEREY is not set\n# CONFIG_HID_MULTITOUCH is not set\n# CONFIG_HID_NTI is not set\n# CONFIG_HID_NTRIG is not set\n# CONFIG_HID_ORTEK is not set\n# CONFIG_HID_PANTHERLORD is not set\n# CONFIG_HID_PENMOUNT is not set\n# CONFIG_HID_PETALYNX is not set\n# CONFIG_HID_PICOLCD is not set\n# CONFIG_HID_PID is not set\n# CONFIG_HID_PLANTRONICS is not set\n# CONFIG_HID_PLAYSTATION is not set\n# CONFIG_HID_PRIMAX is not set\n# CONFIG_HID_PRODIKEYS is not set\n# CONFIG_HID_REDRAGON is not set\n# CONFIG_HID_RETRODE is not set\n# CONFIG_HID_RMI is not set\n# CONFIG_HID_ROCCAT is not set\n# CONFIG_HID_SAITEK is not set\n# CONFIG_HID_SAMSUNG is not set\n# CONFIG_HID_SEMITEK is not set\n# CONFIG_HID_SENSOR_HUB is not set\n# CONFIG_HID_SMARTJOYPLUS is not set\n# CONFIG_HID_SONY is not set\n# CONFIG_HID_SPEEDLINK is not set\n# CONFIG_HID_STEAM is not set\n# CONFIG_HID_STEELSERIES is not set\n# CONFIG_HID_SUNPLUS is not set\n# CONFIG_HID_THINGM is not set\n# CONFIG_HID_THRUSTMASTER is not set\n# CONFIG_HID_TIVO is not set\n# CONFIG_HID_TOPSEED is not set\n# CONFIG_HID_TWINHAN is not set\n# CONFIG_HID_U2FZERO is not set\n# CONFIG_HID_UCLOGIC is not set\n# CONFIG_HID_UDRAW_PS3 is not set\n# CONFIG_HID_VIEWSONIC is not set\n# CONFIG_HID_VIVALDI is not set\n# CONFIG_HID_WACOM is not set\n# CONFIG_HID_WALTOP is not set\n# CONFIG_HID_WIIMOTE is not set\n# CONFIG_HID_XINMO is not set\n# CONFIG_HID_ZEROPLUS is not set\n# CONFIG_HID_ZYDACRON is not set\n# CONFIG_HIGHMEM is not set\nCONFIG_HIGH_RES_TIMERS=y\n# CONFIG_HINIC is not set\n# CONFIG_HIP04_ETH is not set\n# CONFIG_HIPPI is not set\n# CONFIG_HISILICON_ERRATUM_161010101 is not set\n# CONFIG_HISILICON_ERRATUM_161600802 is not set\n# CONFIG_HISI_DMA is not set\n# CONFIG_HISI_FEMAC is not set\n# CONFIG_HISI_HIKEY_USB is not set\n# CONFIG_HIX5HD2_GMAC is not set\n# CONFIG_HMC425 is not set\n# CONFIG_HMC6352 is not set\n# CONFIG_HNS is not set\n# CONFIG_HNS3 is not set\n# CONFIG_HNS_DSAF is not set\n# CONFIG_HNS_ENET is not set\n# CONFIG_HOSTAP is not set\n# CONFIG_HOSTAP_CS is not set\n# CONFIG_HOSTAP_PCI is not set\n# CONFIG_HOSTAP_PLX is not set\n# CONFIG_HOTPLUG_CPU is not set\n# CONFIG_HOTPLUG_PCI is not set\n# CONFIG_HP03 is not set\n# CONFIG_HP100 is not set\n# CONFIG_HP206C is not set\nCONFIG_HPET_MMAP_DEFAULT=y\n# CONFIG_HPFS_FS is not set\n# CONFIG_HP_ILO is not set\n# CONFIG_HP_WIRELESS is not set\n# CONFIG_HSA_AMD is not set\n# CONFIG_HSI is not set\n# CONFIG_HSR is not set\n# CONFIG_HTC_EGPIO is not set\n# CONFIG_HTC_I2CPLD is not set\n# CONFIG_HTC_PASIC3 is not set\n# CONFIG_HTS221 is not set\n# CONFIG_HTU21 is not set\n# CONFIG_HUGETLBFS is not set\n# CONFIG_HUGETLB_PAGE is not set\n# CONFIG_HVC_DCC is not set\n# CONFIG_HVC_UDBG is not set\n# CONFIG_HWLAT_TRACER is not set\n# CONFIG_HWMON is not set\n# CONFIG_HWMON_DEBUG_CHIP is not set\n# CONFIG_HWMON_VID is not set\n# CONFIG_HWSPINLOCK is not set\n# CONFIG_HWSPINLOCK_OMAP is not set\nCONFIG_HW_PERF_EVENTS=y\n# CONFIG_HW_RANDOM is not set\n# CONFIG_HW_RANDOM_AMD is not set\n# CONFIG_HW_RANDOM_ARM_SMCCC_TRNG is not set\n# CONFIG_HW_RANDOM_ATMEL is not set\n# CONFIG_HW_RANDOM_BA431 is not set\n# CONFIG_HW_RANDOM_CAVIUM is not set\n# CONFIG_HW_RANDOM_CCTRNG is not set\n# CONFIG_HW_RANDOM_EXYNOS is not set\n# CONFIG_HW_RANDOM_GEODE is not set\n# CONFIG_HW_RANDOM_INTEL is not set\n# CONFIG_HW_RANDOM_IPROC_RNG200 is not set\n# CONFIG_HW_RANDOM_MTK is not set\n# CONFIG_HW_RANDOM_OMAP is not set\n# CONFIG_HW_RANDOM_OMAP3_ROM is not set\n# CONFIG_HW_RANDOM_PPC4XX is not set\n# CONFIG_HW_RANDOM_TIMERIOMEM is not set\nCONFIG_HW_RANDOM_TPM=y\n# CONFIG_HW_RANDOM_VIA is not set\n# CONFIG_HW_RANDOM_VIRTIO is not set\n# CONFIG_HW_RANDOM_XIPHERA is not set\n# CONFIG_HX711 is not set\n# CONFIG_HYPERV is not set\n# CONFIG_HYPERV_TSCPAGE is not set\n# CONFIG_HYSDN is not set\nCONFIG_HZ=100\nCONFIG_HZ_100=y\n# CONFIG_HZ_1000 is not set\n# CONFIG_HZ_1024 is not set\n# CONFIG_HZ_128 is not set\n# CONFIG_HZ_200 is not set\n# CONFIG_HZ_24 is not set\n# CONFIG_HZ_250 is not set\n# CONFIG_HZ_256 is not set\n# CONFIG_HZ_300 is not set\n# CONFIG_HZ_48 is not set\n# CONFIG_HZ_500 is not set\n# CONFIG_HZ_PERIODIC is not set\n# CONFIG_I2C is not set\n# CONFIG_I2C_ALGOBIT is not set\n# CONFIG_I2C_ALGOPCA is not set\n# CONFIG_I2C_ALGOPCF is not set\n# CONFIG_I2C_ALI1535 is not set\n# CONFIG_I2C_ALI1563 is not set\n# CONFIG_I2C_ALI15X3 is not set\n# CONFIG_I2C_AMD756 is not set\n# CONFIG_I2C_AMD8111 is not set\n# CONFIG_I2C_ARB_GPIO_CHALLENGE is not set\n# CONFIG_I2C_AU1550 is not set\n# CONFIG_I2C_BCM2835 is not set\n# CONFIG_I2C_BCM_IPROC is not set\n# CONFIG_I2C_CADENCE is not set\n# CONFIG_I2C_CBUS_GPIO is not set\n# CONFIG_I2C_CHARDEV is not set\n# CONFIG_I2C_COMPAT is not set\n# CONFIG_I2C_CP2615 is not set\n# CONFIG_I2C_DEBUG_ALGO is not set\n# CONFIG_I2C_DEBUG_BUS is not set\n# CONFIG_I2C_DEBUG_CORE is not set\n# CONFIG_I2C_DEMUX_PINCTRL is not set\n# CONFIG_I2C_DESIGNWARE_PCI is not set\n# CONFIG_I2C_DESIGNWARE_PLATFORM is not set\n# CONFIG_I2C_DESIGNWARE_SLAVE is not set\n# CONFIG_I2C_DIOLAN_U2C is not set\n# CONFIG_I2C_EG20T is not set\n# CONFIG_I2C_ELEKTOR is not set\n# CONFIG_I2C_EMEV2 is not set\n# CONFIG_I2C_GPIO is not set\n# CONFIG_I2C_GPIO_FAULT_INJECTOR is not set\n# CONFIG_I2C_HELPER_AUTO is not set\n# CONFIG_I2C_HID is not set\n# CONFIG_I2C_HID_OF is not set\n# CONFIG_I2C_HID_OF_GOODIX is not set\n# CONFIG_I2C_I801 is not set\n# CONFIG_I2C_IBM_IIC is not set\n# CONFIG_I2C_IMG is not set\n# CONFIG_I2C_ISCH is not set\n# CONFIG_I2C_ISMT is not set\n# CONFIG_I2C_JZ4780 is not set\n# CONFIG_I2C_MLXCPLD is not set\n# CONFIG_I2C_MPC is not set\n# CONFIG_I2C_MT65XX is not set\n# CONFIG_I2C_MUX is not set\n# CONFIG_I2C_MUX_GPIO is not set\n# CONFIG_I2C_MUX_GPMUX is not set\n# CONFIG_I2C_MUX_LTC4306 is not set\n# CONFIG_I2C_MUX_MLXCPLD is not set\n# CONFIG_I2C_MUX_PCA9541 is not set\n# CONFIG_I2C_MUX_PCA954x is not set\n# CONFIG_I2C_MUX_PINCTRL is not set\n# CONFIG_I2C_MUX_REG is not set\n# CONFIG_I2C_MV64XXX is not set\n# CONFIG_I2C_NFORCE2 is not set\n# CONFIG_I2C_NOMADIK is not set\n# CONFIG_I2C_NVIDIA_GPU is not set\n# CONFIG_I2C_OCORES is not set\n# CONFIG_I2C_OCTEON is not set\n# CONFIG_I2C_PARPORT is not set\n# CONFIG_I2C_PARPORT_LIGHT is not set\n# CONFIG_I2C_PCA_ISA is not set\n# CONFIG_I2C_PCA_PLATFORM is not set\n# CONFIG_I2C_PIIX4 is not set\n# CONFIG_I2C_PXA_PCI is not set\n# CONFIG_I2C_PXA_SLAVE is not set\n# CONFIG_I2C_RCAR is not set\n# CONFIG_I2C_RK3X is not set\n# CONFIG_I2C_ROBOTFUZZ_OSIF is not set\n# CONFIG_I2C_S3C2410 is not set\n# CONFIG_I2C_SCMI is not set\n# CONFIG_I2C_SH_MOBILE is not set\n# CONFIG_I2C_SIMTEC is not set\n# CONFIG_I2C_SIS5595 is not set\n# CONFIG_I2C_SIS630 is not set\n# CONFIG_I2C_SIS96X is not set\n# CONFIG_I2C_SLAVE is not set\n# CONFIG_I2C_SLAVE_EEPROM is not set\n# CONFIG_I2C_SMBUS is not set\n# CONFIG_I2C_STUB is not set\n# CONFIG_I2C_TAOS_EVM is not set\n# CONFIG_I2C_THUNDERX is not set\n# CONFIG_I2C_TINY_USB is not set\n# CONFIG_I2C_VERSATILE is not set\n# CONFIG_I2C_VIA is not set\n# CONFIG_I2C_VIAPRO is not set\n# CONFIG_I2C_VIRTIO is not set\n# CONFIG_I2C_XILINX is not set\n# CONFIG_I3C is not set\n# CONFIG_I40E is not set\n# CONFIG_I40EVF is not set\n# CONFIG_I6300ESB_WDT is not set\n# CONFIG_I82092 is not set\n# CONFIG_I82365 is not set\n# CONFIG_IAQCORE is not set\n# CONFIG_IBM_ASM is not set\n# CONFIG_IBM_EMAC_DEBUG is not set\n# CONFIG_IBM_EMAC_EMAC4 is not set\n# CONFIG_IBM_EMAC_MAL_CLR_ICINTSTAT is not set\n# CONFIG_IBM_EMAC_MAL_COMMON_ERR is not set\n# CONFIG_IBM_EMAC_NO_FLOW_CTRL is not set\n# CONFIG_IBM_EMAC_RGMII is not set\n# CONFIG_IBM_EMAC_TAH is not set\n# CONFIG_IBM_EMAC_ZMII is not set\n# CONFIG_ICE is not set\n# CONFIG_ICP10100 is not set\n# CONFIG_ICPLUS_PHY is not set\n# CONFIG_ICS932S401 is not set\n# CONFIG_ICST is not set\n# CONFIG_IDE is not set\n# CONFIG_IDEAPAD_LAPTOP is not set\n# CONFIG_IDE_GD is not set\n# CONFIG_IDE_PROC_FS is not set\n# CONFIG_IDE_TASK_IOCTL is not set\n# CONFIG_IDLE_PAGE_TRACKING is not set\n# CONFIG_IEEE802154 is not set\n# CONFIG_IEEE802154_ADF7242 is not set\n# CONFIG_IEEE802154_ATUSB is not set\n# CONFIG_IEEE802154_CA8210 is not set\n# CONFIG_IEEE802154_HWSIM is not set\n# CONFIG_IEEE802154_MCR20A is not set\n# CONFIG_IFB is not set\n# CONFIG_IGB is not set\n# CONFIG_IGBVF is not set\n# CONFIG_IGC is not set\n# CONFIG_IIO is not set\n# CONFIG_IIO_BUFFER is not set\n# CONFIG_IIO_BUFFER_CB is not set\n# CONFIG_IIO_BUFFER_DMA is not set\n# CONFIG_IIO_BUFFER_DMAENGINE is not set\n# CONFIG_IIO_BUFFER_HDC2010 is not set\n# CONFIG_IIO_BUFFER_HW_CONSUMER is not set\n# CONFIG_IIO_CONFIGFS is not set\nCONFIG_IIO_CONSUMERS_PER_TRIGGER=2\n# CONFIG_IIO_CROS_EC_ACCEL_LEGACY is not set\n# CONFIG_IIO_INTERRUPT_TRIGGER is not set\n# CONFIG_IIO_MUX is not set\n# CONFIG_IIO_PERIODIC_RTC_TRIGGER is not set\n# CONFIG_IIO_RESCALE is not set\n# CONFIG_IIO_SIMPLE_DUMMY is not set\n# CONFIG_IIO_SSP_SENSORHUB is not set\n# CONFIG_IIO_ST_ACCEL_3AXIS is not set\n# CONFIG_IIO_ST_GYRO_3AXIS is not set\n# CONFIG_IIO_ST_LSM6DSX is not set\n# CONFIG_IIO_ST_LSM9DS0 is not set\n# CONFIG_IIO_ST_MAGN_3AXIS is not set\n# CONFIG_IIO_ST_PRESS is not set\n# CONFIG_IIO_SW_DEVICE is not set\n# CONFIG_IIO_SW_TRIGGER is not set\n# CONFIG_IIO_SYSFS_TRIGGER is not set\n# CONFIG_IIO_TRIGGER is not set\n# CONFIG_IIO_TRIGGERED_EVENT is not set\n# CONFIG_IKCONFIG is not set\n# CONFIG_IKCONFIG_PROC is not set\n# CONFIG_IKHEADERS is not set\n# CONFIG_IMA is not set\n# CONFIG_IMAGE_CMDLINE_HACK is not set\n# CONFIG_IMGPDC_WDT is not set\n# CONFIG_IMG_MDC_DMA is not set\n# CONFIG_IMX7D_ADC is not set\n# CONFIG_IMX_IPUV3_CORE is not set\n# CONFIG_IMX_THERMAL is not set\n# CONFIG_INA2XX_ADC is not set\n# CONFIG_INDIRECT_PIO is not set\nCONFIG_INET=y\n# CONFIG_INET6_AH is not set\n# CONFIG_INET6_ESP is not set\n# CONFIG_INET6_ESPINTCP is not set\n# CONFIG_INET6_IPCOMP is not set\n# CONFIG_INET6_TUNNEL is not set\n# CONFIG_INET6_XFRM_MODE_BEET is not set\n# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set\n# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set\n# CONFIG_INET6_XFRM_MODE_TUNNEL is not set\n# CONFIG_INET6_XFRM_TUNNEL is not set\n# CONFIG_INET_AH is not set\n# CONFIG_INET_DIAG is not set\n# CONFIG_INET_ESP is not set\n# CONFIG_INET_ESPINTCP is not set\n# CONFIG_INET_IPCOMP is not set\n# CONFIG_INET_LRO is not set\n# CONFIG_INET_TCP_DIAG is not set\n# CONFIG_INET_TUNNEL is not set\n# CONFIG_INET_UDP_DIAG is not set\n# CONFIG_INET_XFRM_MODE_BEET is not set\n# CONFIG_INET_XFRM_MODE_TRANSPORT is not set\n# CONFIG_INET_XFRM_MODE_TUNNEL is not set\n# CONFIG_INET_XFRM_TUNNEL is not set\n# CONFIG_INFINIBAND is not set\n# CONFIG_INFTL is not set\n# CONFIG_INGENIC_ADC is not set\n# CONFIG_INGENIC_CGU_JZ4725B is not set\n# CONFIG_INGENIC_CGU_JZ4740 is not set\n# CONFIG_INGENIC_CGU_JZ4760 is not set\n# CONFIG_INGENIC_CGU_JZ4770 is not set\n# CONFIG_INGENIC_CGU_JZ4780 is not set\n# CONFIG_INGENIC_CGU_X1000 is not set\n# CONFIG_INGENIC_CGU_X1830 is not set\n# CONFIG_INGENIC_OST is not set\n# CONFIG_INGENIC_SYSOST is not set\n# CONFIG_INGENIC_TCU_CLK is not set\n# CONFIG_INGENIC_TCU_IRQ is not set\n# CONFIG_INGENIC_TIMER is not set\nCONFIG_INIT_ENV_ARG_LIMIT=32\n# CONFIG_INIT_ON_ALLOC_DEFAULT_ON is not set\n# CONFIG_INIT_ON_FREE_DEFAULT_ON is not set\nCONFIG_INIT_STACK_NONE=y\nCONFIG_INOTIFY_USER=y\n# CONFIG_INPUT is not set\n# CONFIG_INPUT_AD714X is not set\n# CONFIG_INPUT_ADXL34X is not set\n# CONFIG_INPUT_APANEL is not set\n# CONFIG_INPUT_ATI_REMOTE2 is not set\n# CONFIG_INPUT_ATLAS_BTNS is not set\n# CONFIG_INPUT_ATMEL_CAPTOUCH is not set\n# CONFIG_INPUT_AXP20X_PEK is not set\n# CONFIG_INPUT_BMA150 is not set\n# CONFIG_INPUT_CM109 is not set\n# CONFIG_INPUT_CMA3000 is not set\n# CONFIG_INPUT_DA7280_HAPTICS is not set\n# CONFIG_INPUT_DRV260X_HAPTICS is not set\n# CONFIG_INPUT_DRV2665_HAPTICS is not set\n# CONFIG_INPUT_DRV2667_HAPTICS is not set\n# CONFIG_INPUT_E3X0_BUTTON is not set\n# CONFIG_INPUT_EVBUG is not set\n# CONFIG_INPUT_EVDEV is not set\n# CONFIG_INPUT_FF_MEMLESS is not set\n# CONFIG_INPUT_GP2A is not set\n# CONFIG_INPUT_GPIO_BEEPER is not set\n# CONFIG_INPUT_GPIO_DECODER is not set\n# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set\n# CONFIG_INPUT_GPIO_TILT_POLLED is not set\n# CONFIG_INPUT_GPIO_VIBRA is not set\n# CONFIG_INPUT_IDEAPAD_SLIDEBAR is not set\n# CONFIG_INPUT_IMS_PCU is not set\n# CONFIG_INPUT_IQS269A is not set\n# CONFIG_INPUT_IQS626A is not set\n# CONFIG_INPUT_JOYDEV is not set\n# CONFIG_INPUT_JOYSTICK is not set\n# CONFIG_INPUT_KEYBOARD is not set\n# CONFIG_INPUT_KEYSPAN_REMOTE is not set\n# CONFIG_INPUT_KXTJ9 is not set\n# CONFIG_INPUT_LEDS is not set\n# CONFIG_INPUT_MATRIXKMAP is not set\n# CONFIG_INPUT_MAX8997_HAPTIC is not set\nCONFIG_INPUT_MISC=y\n# CONFIG_INPUT_MMA8450 is not set\n# CONFIG_INPUT_MOUSE is not set\n# CONFIG_INPUT_MOUSEDEV is not set\n# CONFIG_INPUT_MPU3050 is not set\n# CONFIG_INPUT_MSM_VIBRATOR is not set\n# CONFIG_INPUT_PALMAS_PWRBUTTON is not set\n# CONFIG_INPUT_PCF8574 is not set\n# CONFIG_INPUT_PCSPKR is not set\n# CONFIG_INPUT_POLLDEV is not set\n# CONFIG_INPUT_POWERMATE is not set\n# CONFIG_INPUT_PWM_BEEPER is not set\n# CONFIG_INPUT_PWM_VIBRA is not set\n# CONFIG_INPUT_REGULATOR_HAPTIC is not set\n# CONFIG_INPUT_SOC_BUTTON_ARRAY is not set\n# CONFIG_INPUT_SPARSEKMAP is not set\n# CONFIG_INPUT_TABLET is not set\n# CONFIG_INPUT_TOUCHSCREEN is not set\n# CONFIG_INPUT_TPS65218_PWRBUTTON is not set\n# CONFIG_INPUT_TWL4030_PWRBUTTON is not set\n# CONFIG_INPUT_TWL4030_VIBRA is not set\n# CONFIG_INPUT_TWL6040_VIBRA is not set\n# CONFIG_INPUT_UINPUT is not set\n# CONFIG_INPUT_WISTRON_BTNS is not set\n# CONFIG_INPUT_YEALINK is not set\n# CONFIG_INT340X_THERMAL is not set\n# CONFIG_INTEGRITY is not set\n# CONFIG_INTEGRITY_AUDIT is not set\n# CONFIG_INTEGRITY_SIGNATURE is not set\n# CONFIG_INTEL_ATOMISP2_LED is not set\n# CONFIG_INTEL_ATOMISP2_PM is not set\n# CONFIG_INTEL_CHT_INT33FE is not set\n# CONFIG_INTEL_HID_EVENT is not set\n# CONFIG_INTEL_IDLE is not set\n# CONFIG_INTEL_IDMA64 is not set\n# CONFIG_INTEL_INT0002_VGPIO is not set\n# CONFIG_INTEL_IOATDMA is not set\n# CONFIG_INTEL_ISH_HID is not set\n# CONFIG_INTEL_MEI is not set\n# CONFIG_INTEL_MEI_ME is not set\n# CONFIG_INTEL_MEI_TXE is not set\n# CONFIG_INTEL_MIC_CARD is not set\n# CONFIG_INTEL_MIC_HOST is not set\n# CONFIG_INTEL_MID_PTI is not set\n# CONFIG_INTEL_OAKTRAIL is not set\n# CONFIG_INTEL_PMC_CORE is not set\n# CONFIG_INTEL_PUNIT_IPC is not set\n# CONFIG_INTEL_RST is not set\n# CONFIG_INTEL_SMARTCONNECT is not set\n# CONFIG_INTEL_SOC_PMIC is not set\n# CONFIG_INTEL_SOC_PMIC_CHTDC_TI is not set\n# CONFIG_INTEL_SOC_PMIC_CHTWC is not set\n# CONFIG_INTEL_TH is not set\n# CONFIG_INTEL_VBTN is not set\n# CONFIG_INTEL_XWAY_PHY is not set\n# CONFIG_INTERCONNECT is not set\n# CONFIG_INTERVAL_TREE_TEST is not set\n# CONFIG_INV_ICM42600_I2C is not set\n# CONFIG_INV_ICM42600_SPI is not set\n# CONFIG_INV_MPU6050_I2C is not set\n# CONFIG_INV_MPU6050_IIO is not set\n# CONFIG_INV_MPU6050_SPI is not set\n# CONFIG_IOMMU_SUPPORT is not set\n# CONFIG_IONIC is not set\n# CONFIG_IOSCHED_BFQ is not set\nCONFIG_IO_STRICT_DEVMEM=y\n# CONFIG_IO_URING is not set\nCONFIG_IO_WQ=y\n# CONFIG_IP17XX_PHY is not set\n# CONFIG_IP6_NF_FILTER is not set\n# CONFIG_IP6_NF_IPTABLES is not set\n# CONFIG_IP6_NF_MANGLE is not set\n# CONFIG_IP6_NF_MATCH_AH is not set\n# CONFIG_IP6_NF_MATCH_EUI64 is not set\n# CONFIG_IP6_NF_MATCH_FRAG is not set\n# CONFIG_IP6_NF_MATCH_HL is not set\n# CONFIG_IP6_NF_MATCH_IPV6HEADER is not set\n# CONFIG_IP6_NF_MATCH_MH is not set\n# CONFIG_IP6_NF_MATCH_OPTS is not set\n# CONFIG_IP6_NF_MATCH_RPFILTER is not set\n# CONFIG_IP6_NF_MATCH_RT is not set\n# CONFIG_IP6_NF_MATCH_SRH is not set\n# CONFIG_IP6_NF_NAT is not set\n# CONFIG_IP6_NF_RAW is not set\n# CONFIG_IP6_NF_SECURITY is not set\n# CONFIG_IP6_NF_TARGET_HL is not set\n# CONFIG_IP6_NF_TARGET_MASQUERADE is not set\n# CONFIG_IP6_NF_TARGET_REJECT is not set\n# CONFIG_IP6_NF_TARGET_SYNPROXY is not set\n# CONFIG_IPACK_BUS is not set\n# CONFIG_IPC_NS is not set\n# CONFIG_IPMB_DEVICE_INTERFACE is not set\n# CONFIG_IPMI_HANDLER is not set\n# CONFIG_IPV6 is not set\n# CONFIG_IPV6_FOU is not set\n# CONFIG_IPV6_FOU_TUNNEL is not set\n# CONFIG_IPV6_ILA is not set\n# CONFIG_IPV6_IOAM6_LWTUNNEL is not set\n# CONFIG_IPV6_MIP6 is not set\n# CONFIG_IPV6_MROUTE is not set\n# CONFIG_IPV6_MROUTE_MULTIPLE_TABLES is not set\n# CONFIG_IPV6_MULTIPLE_TABLES is not set\nCONFIG_IPV6_NDISC_NODETYPE=y\n# CONFIG_IPV6_OPTIMISTIC_DAD is not set\n# CONFIG_IPV6_ROUTER_PREF is not set\n# CONFIG_IPV6_ROUTE_INFO is not set\n# CONFIG_IPV6_RPL_LWTUNNEL is not set\n# CONFIG_IPV6_SEG6_HMAC is not set\n# CONFIG_IPV6_SEG6_LWTUNNEL is not set\n# CONFIG_IPV6_SIT is not set\n# CONFIG_IPV6_SIT_6RD is not set\n# CONFIG_IPV6_TUNNEL is not set\n# CONFIG_IPV6_VTI is not set\n# CONFIG_IPVLAN is not set\n# CONFIG_IPVTAP is not set\n# CONFIG_IPW2100 is not set\n# CONFIG_IPW2100_DEBUG is not set\nCONFIG_IPW2100_MONITOR=y\n# CONFIG_IPW2200 is not set\n# CONFIG_IPW2200_DEBUG is not set\nCONFIG_IPW2200_MONITOR=y\n# CONFIG_IPW2200_PROMISCUOUS is not set\n# CONFIG_IPW2200_QOS is not set\n# CONFIG_IPW2200_RADIOTAP is not set\n# CONFIG_IPWIRELESS is not set\n# CONFIG_IPX is not set\nCONFIG_IP_ADVANCED_ROUTER=y\n# CONFIG_IP_DCCP is not set\n# CONFIG_IP_FIB_TRIE_STATS is not set\n# CONFIG_IP_MROUTE is not set\nCONFIG_IP_MROUTE_MULTIPLE_TABLES=y\nCONFIG_IP_MULTICAST=y\nCONFIG_IP_MULTIPLE_TABLES=y\n# CONFIG_IP_NF_ARPFILTER is not set\n# CONFIG_IP_NF_ARPTABLES is not set\n# CONFIG_IP_NF_ARP_MANGLE is not set\n# CONFIG_IP_NF_FILTER is not set\n# CONFIG_IP_NF_IPTABLES is not set\n# CONFIG_IP_NF_MANGLE is not set\n# CONFIG_IP_NF_MATCH_AH is not set\n# CONFIG_IP_NF_MATCH_ECN is not set\n# CONFIG_IP_NF_MATCH_RPFILTER is not set\n# CONFIG_IP_NF_MATCH_TTL is not set\n# CONFIG_IP_NF_RAW is not set\n# CONFIG_IP_NF_SECURITY is not set\n# CONFIG_IP_NF_TARGET_CLUSTERIP is not set\n# CONFIG_IP_NF_TARGET_ECN is not set\n# CONFIG_IP_NF_TARGET_MASQUERADE is not set\n# CONFIG_IP_NF_TARGET_NETMAP is not set\n# CONFIG_IP_NF_TARGET_REDIRECT is not set\n# CONFIG_IP_NF_TARGET_REJECT is not set\n# CONFIG_IP_NF_TARGET_SYNPROXY is not set\n# CONFIG_IP_NF_TARGET_TTL is not set\n# CONFIG_IP_PIMSM_V1 is not set\n# CONFIG_IP_PIMSM_V2 is not set\n# CONFIG_IP_PNP is not set\nCONFIG_IP_ROUTE_MULTIPATH=y\nCONFIG_IP_ROUTE_VERBOSE=y\n# CONFIG_IP_SCTP is not set\n# CONFIG_IP_SET is not set\n# CONFIG_IP_SET_HASH_IPMAC is not set\n# CONFIG_IP_VS is not set\n# CONFIG_IP_VS_MH is not set\nCONFIG_IP_VS_MH_TAB_INDEX=10\n# CONFIG_IP_VS_TWOS is not set\n# CONFIG_IRDA is not set\n# CONFIG_IRQSOFF_TRACER is not set\n# CONFIG_IRQ_ALL_CPUS is not set\n# CONFIG_IRQ_DOMAIN_DEBUG is not set\n# CONFIG_IRQ_POLL is not set\n# CONFIG_IRQ_TIME_ACCOUNTING is not set\n# CONFIG_IR_GPIO_CIR is not set\n# CONFIG_IR_HIX5HD2 is not set\n# CONFIG_IR_IGORPLUGUSB is not set\n# CONFIG_IR_IGUANA is not set\n# CONFIG_IR_IMG is not set\n# CONFIG_IR_IMON is not set\n# CONFIG_IR_IMON_RAW is not set\n# CONFIG_IR_JVC_DECODER is not set\n# CONFIG_IR_LIRC_CODEC is not set\n# CONFIG_IR_MCEUSB is not set\n# CONFIG_IR_NEC_DECODER is not set\n# CONFIG_IR_RC5_DECODER is not set\n# CONFIG_IR_RC6_DECODER is not set\n# CONFIG_IR_REDRAT3 is not set\n# CONFIG_IR_SONY_DECODER is not set\n# CONFIG_IR_STREAMZAP is not set\n# CONFIG_IR_TTUSBIR is not set\n# CONFIG_ISA_BUS is not set\n# CONFIG_ISA_BUS_API is not set\n# CONFIG_ISCSI_BOOT_SYSFS is not set\n# CONFIG_ISCSI_TCP is not set\nCONFIG_ISDN=y\n# CONFIG_ISDN_AUDIO is not set\n# CONFIG_ISDN_CAPI is not set\n# CONFIG_ISDN_CAPI_CAPIDRV is not set\n# CONFIG_ISDN_DIVERSION is not set\n# CONFIG_ISDN_DRV_ACT2000 is not set\n# CONFIG_ISDN_DRV_GIGASET is not set\n# CONFIG_ISDN_DRV_HISAX is not set\n# CONFIG_ISDN_DRV_ICN is not set\n# CONFIG_ISDN_DRV_LOOP is not set\n# CONFIG_ISDN_DRV_PCBIT is not set\n# CONFIG_ISDN_DRV_SC is not set\n# CONFIG_ISDN_I4L is not set\n# CONFIG_ISL29003 is not set\n# CONFIG_ISL29020 is not set\n# CONFIG_ISL29125 is not set\n# CONFIG_ISL29501 is not set\n# CONFIG_ISO9660_FS is not set\n# CONFIG_ISS4xx is not set\n# CONFIG_ITG3200 is not set\n# CONFIG_IWL3945 is not set\n# CONFIG_IWLWIFI is not set\n# CONFIG_IXGB is not set\n# CONFIG_IXGBE is not set\n# CONFIG_IXGBEVF is not set\n# CONFIG_JAILHOUSE_GUEST is not set\n# CONFIG_JBD2_DEBUG is not set\n# CONFIG_JFFS2_CMODE_FAVOURLZO is not set\n# CONFIG_JFFS2_CMODE_NONE is not set\nCONFIG_JFFS2_CMODE_PRIORITY=y\n# CONFIG_JFFS2_CMODE_SIZE is not set\nCONFIG_JFFS2_COMPRESSION_OPTIONS=y\nCONFIG_JFFS2_FS=y\nCONFIG_JFFS2_FS_DEBUG=0\n# CONFIG_JFFS2_FS_POSIX_ACL is not set\n# CONFIG_JFFS2_FS_SECURITY is not set\n# CONFIG_JFFS2_FS_WBUF_VERIFY is not set\nCONFIG_JFFS2_FS_WRITEBUFFER=y\nCONFIG_JFFS2_FS_XATTR=y\nCONFIG_JFFS2_LZMA=y\n# CONFIG_JFFS2_LZO is not set\nCONFIG_JFFS2_RTIME=y\n# CONFIG_JFFS2_RUBIN is not set\nCONFIG_JFFS2_SUMMARY=y\n# CONFIG_JFFS2_ZLIB is not set\n# CONFIG_JFS_DEBUG is not set\n# CONFIG_JFS_FS is not set\n# CONFIG_JFS_POSIX_ACL is not set\n# CONFIG_JFS_SECURITY is not set\n# CONFIG_JFS_STATISTICS is not set\n# CONFIG_JME is not set\nCONFIG_JOLIET=y\n# CONFIG_JSA1212 is not set\n# CONFIG_JUMP_LABEL is not set\n# CONFIG_JZ4740_WDT is not set\n# CONFIG_JZ4770_PHY is not set\n# CONFIG_KALLSYMS is not set\n# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set\n# CONFIG_KALLSYMS_ALL is not set\nCONFIG_KALLSYMS_BASE_RELATIVE=y\n# CONFIG_KALLSYMS_UNCOMPRESSED is not set\n# CONFIG_KARMA_PARTITION is not set\n# CONFIG_KASAN is not set\nCONFIG_KASAN_STACK=y\n# CONFIG_KCMP is not set\n# CONFIG_KCOV is not set\n# CONFIG_KCSAN is not set\n# CONFIG_KERNEL_BZIP2 is not set\n# CONFIG_KERNEL_CAT is not set\n# CONFIG_KERNEL_GZIP is not set\n# CONFIG_KERNEL_LZ4 is not set\n# CONFIG_KERNEL_LZMA is not set\n# CONFIG_KERNEL_LZO is not set\nCONFIG_KERNEL_MODE_NEON=y\nCONFIG_KERNEL_XZ=y\n# CONFIG_KERNEL_ZSTD is not set\nCONFIG_KERNFS=y\n# CONFIG_KEXEC is not set\n# CONFIG_KEXEC_FILE is not set\n# CONFIG_KEXEC_SIG is not set\n# CONFIG_KEYBOARD_ADC is not set\n# CONFIG_KEYBOARD_ADP5588 is not set\n# CONFIG_KEYBOARD_ADP5589 is not set\n# CONFIG_KEYBOARD_APPLESPI is not set\n# CONFIG_KEYBOARD_ATKBD is not set\n# CONFIG_KEYBOARD_BCM is not set\n# CONFIG_KEYBOARD_CAP11XX is not set\n# CONFIG_KEYBOARD_DLINK_DIR685 is not set\n# CONFIG_KEYBOARD_GPIO is not set\n# CONFIG_KEYBOARD_GPIO_POLLED is not set\n# CONFIG_KEYBOARD_LKKBD is not set\n# CONFIG_KEYBOARD_LM8323 is not set\n# CONFIG_KEYBOARD_LM8333 is not set\n# CONFIG_KEYBOARD_MATRIX is not set\n# CONFIG_KEYBOARD_MAX7359 is not set\n# CONFIG_KEYBOARD_MCS is not set\n# CONFIG_KEYBOARD_MPR121 is not set\n# CONFIG_KEYBOARD_NEWTON is not set\n# CONFIG_KEYBOARD_OMAP4 is not set\n# CONFIG_KEYBOARD_OPENCORES is not set\n# CONFIG_KEYBOARD_PXA27x is not set\n# CONFIG_KEYBOARD_QT1050 is not set\n# CONFIG_KEYBOARD_QT1070 is not set\n# CONFIG_KEYBOARD_QT2160 is not set\n# CONFIG_KEYBOARD_SAMSUNG is not set\n# CONFIG_KEYBOARD_SH_KEYSC is not set\n# CONFIG_KEYBOARD_SNVS_PWRKEY is not set\n# CONFIG_KEYBOARD_STMPE is not set\n# CONFIG_KEYBOARD_STOWAWAY is not set\n# CONFIG_KEYBOARD_SUNKBD is not set\n# CONFIG_KEYBOARD_TCA6416 is not set\n# CONFIG_KEYBOARD_TCA8418 is not set\n# CONFIG_KEYBOARD_TEGRA is not set\n# CONFIG_KEYBOARD_TM2_TOUCHKEY is not set\n# CONFIG_KEYBOARD_TWL4030 is not set\n# CONFIG_KEYBOARD_XTKBD is not set\n# CONFIG_KEYS is not set\n# CONFIG_KEYS_REQUEST_CACHE is not set\n# CONFIG_KEY_DH_OPERATIONS is not set\n# CONFIG_KFENCE is not set\n# CONFIG_KGDB is not set\n# CONFIG_KMEMCHECK is not set\n# CONFIG_KMX61 is not set\n# CONFIG_KPC2000 is not set\n# CONFIG_KPROBES is not set\n# CONFIG_KPROBES_SANITY_TEST is not set\n# CONFIG_KPROBE_EVENTS_ON_NOTRACE is not set\n# CONFIG_KPROBE_EVENT_GEN_TEST is not set\n# CONFIG_KS7010 is not set\n# CONFIG_KS8842 is not set\n# CONFIG_KS8851 is not set\n# CONFIG_KS8851_MLL is not set\n# CONFIG_KSM is not set\n# CONFIG_KSZ884X_PCI is not set\n# CONFIG_KUNIT is not set\nCONFIG_KUSER_HELPERS=y\n# CONFIG_KVM_AMD is not set\n# CONFIG_KVM_AMD_SEV is not set\n# CONFIG_KVM_GUEST is not set\n# CONFIG_KVM_INTEL is not set\n# CONFIG_KVM_WERROR is not set\n# CONFIG_KVM_XEN is not set\n# CONFIG_KXCJK1013 is not set\n# CONFIG_KXSD9 is not set\n# CONFIG_L2TP is not set\n# CONFIG_L2TP_ETH is not set\n# CONFIG_L2TP_IP is not set\n# CONFIG_L2TP_V3 is not set\n# CONFIG_LAN743X is not set\n# CONFIG_LANMEDIA is not set\n# CONFIG_LANTIQ is not set\n# CONFIG_LAPB is not set\n# CONFIG_LASAT is not set\n# CONFIG_LATENCYTOP is not set\n# CONFIG_LATTICE_ECP3_CONFIG is not set\nCONFIG_LBDAF=y\n# CONFIG_LCD_AMS369FG06 is not set\n# CONFIG_LCD_CLASS_DEVICE is not set\n# CONFIG_LCD_HX8357 is not set\n# CONFIG_LCD_ILI922X is not set\n# CONFIG_LCD_ILI9320 is not set\n# CONFIG_LCD_L4F00242T03 is not set\n# CONFIG_LCD_LD9040 is not set\n# CONFIG_LCD_LMS283GF05 is not set\n# CONFIG_LCD_LMS501KF03 is not set\n# CONFIG_LCD_LTV350QV is not set\n# CONFIG_LCD_OTM3225A is not set\n# CONFIG_LCD_S6E63M0 is not set\n# CONFIG_LCD_TDO24M is not set\n# CONFIG_LCD_VGG2432A4 is not set\nCONFIG_LDISC_AUTOLOAD=y\n# CONFIG_LDM_PARTITION is not set\nCONFIG_LD_DEAD_CODE_DATA_ELIMINATION=y\n# CONFIG_LEDS_AN30259A is not set\n# CONFIG_LEDS_APU is not set\n# CONFIG_LEDS_AW2013 is not set\n# CONFIG_LEDS_BCM6328 is not set\n# CONFIG_LEDS_BCM6358 is not set\n# CONFIG_LEDS_BD2802 is not set\n# CONFIG_LEDS_BLINKM is not set\nCONFIG_LEDS_BRIGHTNESS_HW_CHANGED=y\nCONFIG_LEDS_CLASS=y\n# CONFIG_LEDS_CLASS_FLASH is not set\nCONFIG_LEDS_CLASS_MULTICOLOR=y\n# CONFIG_LEDS_CR0014114 is not set\n# CONFIG_LEDS_DAC124S085 is not set\n# CONFIG_LEDS_EL15203000 is not set\n# CONFIG_LEDS_GPIO is not set\n# CONFIG_LEDS_INTEL_SS4200 is not set\n# CONFIG_LEDS_IS31FL319X is not set\n# CONFIG_LEDS_IS31FL32XX is not set\n# CONFIG_LEDS_LM3530 is not set\n# CONFIG_LEDS_LM3532 is not set\n# CONFIG_LEDS_LM355x is not set\n# CONFIG_LEDS_LM3642 is not set\n# CONFIG_LEDS_LM3692X is not set\n# CONFIG_LEDS_LP3944 is not set\n# CONFIG_LEDS_LP3952 is not set\n# CONFIG_LEDS_LP50XX is not set\n# CONFIG_LEDS_LP5521 is not set\n# CONFIG_LEDS_LP5523 is not set\n# CONFIG_LEDS_LP5562 is not set\n# CONFIG_LEDS_LP55XX_COMMON is not set\n# CONFIG_LEDS_LP8501 is not set\n# CONFIG_LEDS_LP8860 is not set\n# CONFIG_LEDS_LT3593 is not set\n# CONFIG_LEDS_MLXCPLD is not set\n# CONFIG_LEDS_MLXREG is not set\n# CONFIG_LEDS_NIC78BX is not set\n# CONFIG_LEDS_NS2 is not set\n# CONFIG_LEDS_OT200 is not set\n# CONFIG_LEDS_PCA9532 is not set\n# CONFIG_LEDS_PCA955X is not set\n# CONFIG_LEDS_PCA963X is not set\n# CONFIG_LEDS_PWM is not set\n# CONFIG_LEDS_REGULATOR is not set\n# CONFIG_LEDS_SPI_BYTE is not set\n# CONFIG_LEDS_SYSCON is not set\n# CONFIG_LEDS_TCA6507 is not set\n# CONFIG_LEDS_TI_LMU_COMMON is not set\n# CONFIG_LEDS_TLC591XX is not set\nCONFIG_LEDS_TRIGGERS=y\n# CONFIG_LEDS_TRIGGER_ACTIVITY is not set\n# CONFIG_LEDS_TRIGGER_AUDIO is not set\n# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set\n# CONFIG_LEDS_TRIGGER_CAMERA is not set\n# CONFIG_LEDS_TRIGGER_CPU is not set\nCONFIG_LEDS_TRIGGER_DEFAULT_ON=y\n# CONFIG_LEDS_TRIGGER_DISK is not set\n# CONFIG_LEDS_TRIGGER_GPIO is not set\nCONFIG_LEDS_TRIGGER_HEARTBEAT=y\n# CONFIG_LEDS_TRIGGER_MTD is not set\nCONFIG_LEDS_TRIGGER_NETDEV=y\n# CONFIG_LEDS_TRIGGER_ONESHOT is not set\n# CONFIG_LEDS_TRIGGER_PANIC is not set\n# CONFIG_LEDS_TRIGGER_PATTERN is not set\nCONFIG_LEDS_TRIGGER_TIMER=y\n# CONFIG_LEDS_TRIGGER_TRANSIENT is not set\n# CONFIG_LEDS_TRIGGER_TTY is not set\n# CONFIG_LEDS_TURRIS_OMNIA is not set\n# CONFIG_LEDS_USER is not set\n# CONFIG_LED_TRIGGER_PHY is not set\n# CONFIG_LEGACY_PTYS is not set\n# CONFIG_LGUEST is not set\n# CONFIG_LIB80211 is not set\n# CONFIG_LIB80211_CRYPT_CCMP is not set\n# CONFIG_LIB80211_CRYPT_TKIP is not set\n# CONFIG_LIB80211_CRYPT_WEP is not set\n# CONFIG_LIB80211_DEBUG is not set\n# CONFIG_LIBCRC32C is not set\n# CONFIG_LIBERTAS is not set\n# CONFIG_LIBERTAS_THINFIRM is not set\n# CONFIG_LIBERTAS_USB is not set\n# CONFIG_LIBFC is not set\n# CONFIG_LIBFCOE is not set\n# CONFIG_LIBIPW_DEBUG is not set\n# CONFIG_LIBNVDIMM is not set\n# CONFIG_LIDAR_LITE_V2 is not set\nCONFIG_LINEAR_RANGES=y\n# CONFIG_LIQUIDIO is not set\n# CONFIG_LIQUIDIO_VF is not set\n# CONFIG_LIS3L02DQ is not set\n# CONFIG_LITEX_LITEETH is not set\n# CONFIG_LITEX_SOC_CONTROLLER is not set\n# CONFIG_LKDTM is not set\nCONFIG_LLC=y\n# CONFIG_LLC2 is not set\n# CONFIG_LMK04832 is not set\n# CONFIG_LMP91000 is not set\n# CONFIG_LNET is not set\nCONFIG_LOCALVERSION=\"\"\n# CONFIG_LOCALVERSION_AUTO is not set\n# CONFIG_LOCKD is not set\nCONFIG_LOCKDEP_SUPPORT=y\nCONFIG_LOCKD_V4=y\n# CONFIG_LOCKUP_DETECTOR is not set\n# CONFIG_LOCK_EVENT_COUNTS is not set\n# CONFIG_LOCK_STAT is not set\n# CONFIG_LOCK_TORTURE_TEST is not set\n# CONFIG_LOGFS is not set\n# CONFIG_LOGIG940_FF is not set\n# CONFIG_LOGIRUMBLEPAD2_FF is not set\n# CONFIG_LOGITECH_FF is not set\n# CONFIG_LOGIWHEELS_FF is not set\n# CONFIG_LOGO is not set\nCONFIG_LOG_BUF_SHIFT=17\nCONFIG_LOG_CPU_MAX_BUF_SHIFT=12\n# CONFIG_LOONGSON_MC146818 is not set\n# CONFIG_LPC_ICH is not set\n# CONFIG_LPC_SCH is not set\n# CONFIG_LP_CONSOLE is not set\n# CONFIG_LSI_ET1011C_PHY is not set\nCONFIG_LSM=\"lockdown,yama,loadpin,safesetid,integrity\"\nCONFIG_LSM_MMAP_MIN_ADDR=65536\n# CONFIG_LTC1660 is not set\n# CONFIG_LTC2471 is not set\n# CONFIG_LTC2485 is not set\n# CONFIG_LTC2496 is not set\n# CONFIG_LTC2497 is not set\n# CONFIG_LTC2632 is not set\n# CONFIG_LTC2983 is not set\n# CONFIG_LTE_GDM724X is not set\nCONFIG_LTO_NONE=y\n# CONFIG_LTPC is not set\n# CONFIG_LTR501 is not set\n# CONFIG_LUSTRE_FS is not set\n# CONFIG_LV0104CS is not set\n# CONFIG_LWTUNNEL is not set\n# CONFIG_LXT_PHY is not set\n# CONFIG_LZ4HC_COMPRESS is not set\n# CONFIG_LZ4_COMPRESS is not set\n# CONFIG_LZ4_DECOMPRESS is not set\nCONFIG_LZMA_COMPRESS=y\nCONFIG_LZMA_DECOMPRESS=y\n# CONFIG_LZO_COMPRESS is not set\n# CONFIG_LZO_DECOMPRESS is not set\n# CONFIG_M62332 is not set\n# CONFIG_MAC80211 is not set\n# CONFIG_MAC80211_MESSAGE_TRACING is not set\nCONFIG_MAC80211_STA_HASH_MAX_SIZE=0\n# CONFIG_MACB is not set\n# CONFIG_MACH_ASM9260 is not set\n# CONFIG_MACH_DECSTATION is not set\n# CONFIG_MACH_INGENIC is not set\n# CONFIG_MACH_INGENIC_SOC is not set\n# CONFIG_MACH_JAZZ is not set\n# CONFIG_MACH_JZ4740 is not set\n# CONFIG_MACH_LOONGSON2EF is not set\n# CONFIG_MACH_LOONGSON32 is not set\n# CONFIG_MACH_LOONGSON64 is not set\n# CONFIG_MACH_NINTENDO64 is not set\n# CONFIG_MACH_PIC32 is not set\n# CONFIG_MACH_PISTACHIO is not set\n# CONFIG_MACH_REALTEK_RTL is not set\n# CONFIG_MACH_TX39XX is not set\n# CONFIG_MACH_TX49XX is not set\n# CONFIG_MACH_VR41XX is not set\n# CONFIG_MACH_XILFPGA is not set\n# CONFIG_MACINTOSH_DRIVERS is not set\n# CONFIG_MACSEC is not set\n# CONFIG_MACVLAN is not set\n# CONFIG_MACVTAP is not set\n# CONFIG_MAC_EMUMOUSEBTN is not set\n# CONFIG_MAC_PARTITION is not set\n# CONFIG_MAG3110 is not set\n# CONFIG_MAGIC_SYSRQ is not set\nCONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1\n# CONFIG_MAGIC_SYSRQ_SERIAL is not set\nCONFIG_MAGIC_SYSRQ_SERIAL_SEQUENCE=\"\"\n# CONFIG_MAILBOX is not set\n# CONFIG_MANAGER_SBS is not set\n# CONFIG_MANDATORY_FILE_LOCKING is not set\n# CONFIG_MANGLE_BOOTARGS is not set\n# CONFIG_MARVELL_10G_PHY is not set\n# CONFIG_MARVELL_88X2222_PHY is not set\n# CONFIG_MARVELL_PHY is not set\n# CONFIG_MAX1027 is not set\n# CONFIG_MAX11100 is not set\n# CONFIG_MAX1118 is not set\n# CONFIG_MAX1241 is not set\n# CONFIG_MAX1363 is not set\n# CONFIG_MAX30100 is not set\n# CONFIG_MAX30102 is not set\n# CONFIG_MAX31856 is not set\n# CONFIG_MAX44000 is not set\n# CONFIG_MAX44009 is not set\n# CONFIG_MAX517 is not set\n# CONFIG_MAX5432 is not set\n# CONFIG_MAX5481 is not set\n# CONFIG_MAX5487 is not set\n# CONFIG_MAX5821 is not set\n# CONFIG_MAX63XX_WATCHDOG is not set\n# CONFIG_MAX9611 is not set\n# CONFIG_MAXIM_THERMOCOUPLE is not set\n# CONFIG_MAXLINEAR_GPHY is not set\nCONFIG_MAY_USE_DEVLINK=y\n# CONFIG_MB1232 is not set\n# CONFIG_MC3230 is not set\n# CONFIG_MCB is not set\n# CONFIG_MCP320X is not set\n# CONFIG_MCP3422 is not set\n# CONFIG_MCP3911 is not set\n# CONFIG_MCP4018 is not set\n# CONFIG_MCP41010 is not set\n# CONFIG_MCP4131 is not set\n# CONFIG_MCP4531 is not set\n# CONFIG_MCP4725 is not set\n# CONFIG_MCP4922 is not set\n# CONFIG_MCPM is not set\n# CONFIG_MCTP is not set\n# CONFIG_MD is not set\n# CONFIG_MDIO_BCM_UNIMAC is not set\n# CONFIG_MDIO_BITBANG is not set\n# CONFIG_MDIO_BUS_MUX_GPIO is not set\n# CONFIG_MDIO_BUS_MUX_MMIOREG is not set\n# CONFIG_MDIO_BUS_MUX_MULTIPLEXER is not set\n# CONFIG_MDIO_DEVICE is not set\n# CONFIG_MDIO_DEVRES is not set\n# CONFIG_MDIO_HISI_FEMAC is not set\n# CONFIG_MDIO_IPQ4019 is not set\n# CONFIG_MDIO_IPQ8064 is not set\n# CONFIG_MDIO_MSCC_MIIM is not set\n# CONFIG_MDIO_MVUSB is not set\n# CONFIG_MDIO_OCTEON is not set\n# CONFIG_MDIO_THUNDER is not set\n# CONFIG_MDIO_XPCS is not set\n# CONFIG_MDM_GCC_9607 is not set\n# CONFIG_MD_FAULTY is not set\n# CONFIG_MEDIATEK_GE_PHY is not set\n# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set\n# CONFIG_MEDIA_ATTACH is not set\n# CONFIG_MEDIA_CAMERA_SUPPORT is not set\n# CONFIG_MEDIA_CEC_SUPPORT is not set\n# CONFIG_MEDIA_CONTROLLER is not set\n# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set\n# CONFIG_MEDIA_PCI_SUPPORT is not set\n# CONFIG_MEDIA_PLATFORM_SUPPORT is not set\n# CONFIG_MEDIA_RADIO_SUPPORT is not set\n# CONFIG_MEDIA_RC_SUPPORT is not set\n# CONFIG_MEDIA_SDR_SUPPORT is not set\n# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set\n# CONFIG_MEDIA_SUPPORT is not set\n# CONFIG_MEDIA_SUPPORT_FILTER is not set\n# CONFIG_MEDIA_TEST_SUPPORT is not set\n# CONFIG_MEDIA_TUNER_E4000 is not set\n# CONFIG_MEDIA_TUNER_FC0011 is not set\n# CONFIG_MEDIA_TUNER_FC0012 is not set\n# CONFIG_MEDIA_TUNER_FC0013 is not set\n# CONFIG_MEDIA_TUNER_FC2580 is not set\n# CONFIG_MEDIA_TUNER_IT913X is not set\n# CONFIG_MEDIA_TUNER_M88RS6000T is not set\n# CONFIG_MEDIA_TUNER_MAX2165 is not set\n# CONFIG_MEDIA_TUNER_MC44S803 is not set\n# CONFIG_MEDIA_TUNER_MSI001 is not set\n# CONFIG_MEDIA_TUNER_MT2060 is not set\n# CONFIG_MEDIA_TUNER_MT2063 is not set\n# CONFIG_MEDIA_TUNER_MT20XX is not set\n# CONFIG_MEDIA_TUNER_MT2131 is not set\n# CONFIG_MEDIA_TUNER_MT2266 is not set\n# CONFIG_MEDIA_TUNER_MXL301RF is not set\n# CONFIG_MEDIA_TUNER_MXL5005S is not set\n# CONFIG_MEDIA_TUNER_MXL5007T is not set\n# CONFIG_MEDIA_TUNER_QM1D1B0004 is not set\n# CONFIG_MEDIA_TUNER_QM1D1C0042 is not set\n# CONFIG_MEDIA_TUNER_QT1010 is not set\n# CONFIG_MEDIA_TUNER_R820T is not set\n# CONFIG_MEDIA_TUNER_SI2157 is not set\n# CONFIG_MEDIA_TUNER_SIMPLE is not set\n# CONFIG_MEDIA_TUNER_TDA18212 is not set\n# CONFIG_MEDIA_TUNER_TDA18218 is not set\n# CONFIG_MEDIA_TUNER_TDA18250 is not set\n# CONFIG_MEDIA_TUNER_TDA18271 is not set\n# CONFIG_MEDIA_TUNER_TDA827X is not set\n# CONFIG_MEDIA_TUNER_TDA8290 is not set\n# CONFIG_MEDIA_TUNER_TDA9887 is not set\n# CONFIG_MEDIA_TUNER_TEA5761 is not set\n# CONFIG_MEDIA_TUNER_TEA5767 is not set\n# CONFIG_MEDIA_TUNER_TUA9001 is not set\n# CONFIG_MEDIA_TUNER_XC2028 is not set\n# CONFIG_MEDIA_TUNER_XC4000 is not set\n# CONFIG_MEDIA_TUNER_XC5000 is not set\n# CONFIG_MEDIA_USB_SUPPORT is not set\n# CONFIG_MEGARAID_LEGACY is not set\n# CONFIG_MEGARAID_NEWGEN is not set\n# CONFIG_MEGARAID_SAS is not set\n# CONFIG_MELLANOX_PLATFORM is not set\nCONFIG_MEMBARRIER=y\n# CONFIG_MEMORY is not set\n# CONFIG_MEMORY_FAILURE is not set\n# CONFIG_MEMORY_HOTPLUG is not set\n# CONFIG_MEMSTICK is not set\n# CONFIG_MEMTEST is not set\n# CONFIG_MEN_A21_WDT is not set\n# CONFIG_MESON_SM is not set\nCONFIG_MESSAGE_LOGLEVEL_DEFAULT=4\n# CONFIG_MFD_88PM800 is not set\n# CONFIG_MFD_88PM805 is not set\n# CONFIG_MFD_88PM860X is not set\n# CONFIG_MFD_AAT2870_CORE is not set\n# CONFIG_MFD_AC100 is not set\n# CONFIG_MFD_ACT8945A is not set\n# CONFIG_MFD_ARIZONA_I2C is not set\n# CONFIG_MFD_ARIZONA_SPI is not set\n# CONFIG_MFD_AS3711 is not set\n# CONFIG_MFD_AS3722 is not set\n# CONFIG_MFD_ASIC3 is not set\n# CONFIG_MFD_ATC260X_I2C is not set\n# CONFIG_MFD_ATMEL_FLEXCOM is not set\n# CONFIG_MFD_ATMEL_HLCDC is not set\n# CONFIG_MFD_AXP20X is not set\n# CONFIG_MFD_AXP20X_I2C is not set\n# CONFIG_MFD_BCM590XX is not set\n# CONFIG_MFD_BD9571MWV is not set\n# CONFIG_MFD_CORE is not set\n# CONFIG_MFD_CPCAP is not set\n# CONFIG_MFD_CROS_EC is not set\n# CONFIG_MFD_CS5535 is not set\n# CONFIG_MFD_DA9052_I2C is not set\n# CONFIG_MFD_DA9052_SPI is not set\n# CONFIG_MFD_DA9055 is not set\n# CONFIG_MFD_DA9062 is not set\n# CONFIG_MFD_DA9063 is not set\n# CONFIG_MFD_DA9150 is not set\n# CONFIG_MFD_DLN2 is not set\n# CONFIG_MFD_EXYNOS_LPASS is not set\n# CONFIG_MFD_GATEWORKS_GSC is not set\n# CONFIG_MFD_HI6421_PMIC is not set\n# CONFIG_MFD_INTEL_M10_BMC is not set\n# CONFIG_MFD_INTEL_PMT is not set\n# CONFIG_MFD_INTEL_QUARK_I2C_GPIO is not set\n# CONFIG_MFD_IQS62X is not set\n# CONFIG_MFD_JANZ_CMODIO is not set\n# CONFIG_MFD_KEMPLD is not set\n# CONFIG_MFD_LM3533 is not set\n# CONFIG_MFD_LOCHNAGAR is not set\n# CONFIG_MFD_LP3943 is not set\n# CONFIG_MFD_LP8788 is not set\n# CONFIG_MFD_MADERA is not set\n# CONFIG_MFD_MAX14577 is not set\n# CONFIG_MFD_MAX77620 is not set\n# CONFIG_MFD_MAX77650 is not set\n# CONFIG_MFD_MAX77686 is not set\n# CONFIG_MFD_MAX77693 is not set\n# CONFIG_MFD_MAX77843 is not set\n# CONFIG_MFD_MAX8907 is not set\n# CONFIG_MFD_MAX8925 is not set\n# CONFIG_MFD_MAX8997 is not set\n# CONFIG_MFD_MAX8998 is not set\n# CONFIG_MFD_MC13XXX is not set\n# CONFIG_MFD_MC13XXX_I2C is not set\n# CONFIG_MFD_MC13XXX_SPI is not set\n# CONFIG_MFD_MENF21BMC is not set\n# CONFIG_MFD_MP2629 is not set\n# CONFIG_MFD_MT6360 is not set\n# CONFIG_MFD_MT6397 is not set\n# CONFIG_MFD_NTXEC is not set\n# CONFIG_MFD_OMAP_USB_HOST is not set\n# CONFIG_MFD_PALMAS is not set\n# CONFIG_MFD_PCF50633 is not set\n# CONFIG_MFD_PM8921_CORE is not set\n# CONFIG_MFD_PM8XXX is not set\n# CONFIG_MFD_QCOM_PM8008 is not set\n# CONFIG_MFD_RC5T583 is not set\n# CONFIG_MFD_RDC321X is not set\n# CONFIG_MFD_RETU is not set\n# CONFIG_MFD_RK808 is not set\n# CONFIG_MFD_RN5T618 is not set\n# CONFIG_MFD_ROHM_BD70528 is not set\n# CONFIG_MFD_ROHM_BD71828 is not set\n# CONFIG_MFD_ROHM_BD718XX is not set\n# CONFIG_MFD_ROHM_BD957XMUF is not set\n# CONFIG_MFD_RSMU_I2C is not set\n# CONFIG_MFD_RSMU_SPI is not set\n# CONFIG_MFD_RT4831 is not set\n# CONFIG_MFD_RT5033 is not set\n# CONFIG_MFD_RTSX_PCI is not set\n# CONFIG_MFD_RTSX_USB is not set\n# CONFIG_MFD_SEC_CORE is not set\n# CONFIG_MFD_SI476X_CORE is not set\n# CONFIG_MFD_SKY81452 is not set\n# CONFIG_MFD_SL28CPLD is not set\n# CONFIG_MFD_SM501 is not set\n# CONFIG_MFD_SMSC is not set\n# CONFIG_MFD_STMFX is not set\n# CONFIG_MFD_STMPE is not set\n# CONFIG_MFD_STPMIC1 is not set\n# CONFIG_MFD_SYSCON is not set\n# CONFIG_MFD_T7L66XB is not set\n# CONFIG_MFD_TC3589X is not set\n# CONFIG_MFD_TC6387XB is not set\n# CONFIG_MFD_TC6393XB is not set\n# CONFIG_MFD_TIMBERDALE is not set\n# CONFIG_MFD_TI_AM335X_TSCADC is not set\n# CONFIG_MFD_TI_LMU is not set\n# CONFIG_MFD_TI_LP873X is not set\n# CONFIG_MFD_TI_LP87565 is not set\n# CONFIG_MFD_TMIO is not set\n# CONFIG_MFD_TPS65086 is not set\n# CONFIG_MFD_TPS65090 is not set\n# CONFIG_MFD_TPS65217 is not set\n# CONFIG_MFD_TPS65218 is not set\n# CONFIG_MFD_TPS6586X is not set\n# CONFIG_MFD_TPS65910 is not set\n# CONFIG_MFD_TPS65912 is not set\n# CONFIG_MFD_TPS65912_I2C is not set\n# CONFIG_MFD_TPS65912_SPI is not set\n# CONFIG_MFD_TPS68470 is not set\n# CONFIG_MFD_TPS80031 is not set\n# CONFIG_MFD_TQMX86 is not set\n# CONFIG_MFD_VIPERBOARD is not set\n# CONFIG_MFD_VX855 is not set\n# CONFIG_MFD_WL1273_CORE is not set\n# CONFIG_MFD_WM831X is not set\n# CONFIG_MFD_WM831X_I2C is not set\n# CONFIG_MFD_WM831X_SPI is not set\n# CONFIG_MFD_WM8350_I2C is not set\n# CONFIG_MFD_WM8400 is not set\n# CONFIG_MFD_WM8994 is not set\n# CONFIG_MG_DISK is not set\n# CONFIG_MHI_BUS is not set\n# CONFIG_MHI_BUS_DEBUG is not set\n# CONFIG_MHI_BUS_PCI_GENERIC is not set\n# CONFIG_MHI_NET is not set\n# CONFIG_MHI_WWAN_CTRL is not set\n# CONFIG_MHI_WWAN_MBIM is not set\n# CONFIG_MICREL_KS8995MA is not set\n# CONFIG_MICREL_PHY is not set\n# CONFIG_MICROCHIP_KSZ is not set\n# CONFIG_MICROCHIP_PHY is not set\n# CONFIG_MICROCHIP_PIT64B is not set\n# CONFIG_MICROCHIP_T1_PHY is not set\n# CONFIG_MICROSEMI_PHY is not set\n# CONFIG_MIGRATION is not set\nCONFIG_MII=y\n# CONFIG_MIKROTIK is not set\n# CONFIG_MIKROTIK_RB532 is not set\n# CONFIG_MINIX_FS is not set\n# CONFIG_MINIX_FS_NATIVE_ENDIAN is not set\n# CONFIG_MINIX_SUBPARTITION is not set\n# CONFIG_MIPS32_N32 is not set\n# CONFIG_MIPS32_O32 is not set\n# CONFIG_MIPS_ALCHEMY is not set\n# CONFIG_MIPS_CDMM is not set\n# CONFIG_MIPS_CMDLINE_DTB_EXTEND is not set\n# CONFIG_MIPS_CMDLINE_FROM_DTB is not set\n# CONFIG_MIPS_CMP is not set\n# CONFIG_MIPS_COBALT is not set\n# CONFIG_MIPS_CPS is not set\n# CONFIG_MIPS_ELF_APPENDED_DTB is not set\n# CONFIG_MIPS_FPU_EMULATOR is not set\n# CONFIG_MIPS_FP_SUPPORT is not set\n# CONFIG_MIPS_GENERIC is not set\n# CONFIG_MIPS_GENERIC_KERNEL is not set\n# CONFIG_MIPS_MALTA is not set\n# CONFIG_MIPS_O32_FP64_SUPPORT is not set\n# CONFIG_MIPS_PARAVIRT is not set\n# CONFIG_MIPS_PLATFORM_DEVICES is not set\n# CONFIG_MIPS_RAW_APPENDED_DTB is not set\n# CONFIG_MIPS_SEAD3 is not set\n# CONFIG_MIPS_VA_BITS_48 is not set\n# CONFIG_MIPS_VPE_LOADER is not set\n# CONFIG_MISC_ALCOR_PCI is not set\nCONFIG_MISC_FILESYSTEMS=y\n# CONFIG_MISC_RTSX_PCI is not set\n# CONFIG_MISC_RTSX_USB is not set\n# CONFIG_MISDN is not set\n# CONFIG_MISDN_AVMFRITZ is not set\n# CONFIG_MISDN_HFCPCI is not set\n# CONFIG_MISDN_HFCUSB is not set\n# CONFIG_MISDN_INFINEON is not set\n# CONFIG_MISDN_NETJET is not set\n# CONFIG_MISDN_SPEEDFAX is not set\n# CONFIG_MISDN_W6692 is not set\nCONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY=y\n# CONFIG_MKISS is not set\n# CONFIG_MLX4_CORE is not set\n# CONFIG_MLX4_EN is not set\n# CONFIG_MLX5_CORE is not set\n# CONFIG_MLX5_SF is not set\n# CONFIG_MLX90614 is not set\n# CONFIG_MLX90632 is not set\n# CONFIG_MLXFW is not set\n# CONFIG_MLXSW_CORE is not set\n# CONFIG_MLX_CPLD_PLATFORM is not set\n# CONFIG_MLX_PLATFORM is not set\n# CONFIG_MMA7455_I2C is not set\n# CONFIG_MMA7455_SPI is not set\n# CONFIG_MMA7660 is not set\n# CONFIG_MMA8452 is not set\n# CONFIG_MMA9551 is not set\n# CONFIG_MMA9553 is not set\n# CONFIG_MMC is not set\n# CONFIG_MMC35240 is not set\n# CONFIG_MMC_ARMMMCI is not set\n# CONFIG_MMC_AU1X is not set\n# CONFIG_MMC_BLOCK is not set\nCONFIG_MMC_BLOCK_BOUNCE=y\nCONFIG_MMC_BLOCK_MINORS=8\n# CONFIG_MMC_CAVIUM_THUNDERX is not set\n# CONFIG_MMC_CB710 is not set\n# CONFIG_MMC_CQHCI is not set\n# CONFIG_MMC_DEBUG is not set\n# CONFIG_MMC_DW is not set\n# CONFIG_MMC_HSQ is not set\n# CONFIG_MMC_JZ4740 is not set\n# CONFIG_MMC_MTK is not set\n# CONFIG_MMC_MVSDIO is not set\n# CONFIG_MMC_S3C is not set\n# CONFIG_MMC_SDHCI is not set\n# CONFIG_MMC_SDHCI_ACPI is not set\n# CONFIG_MMC_SDHCI_AM654 is not set\n# CONFIG_MMC_SDHCI_BCM_KONA is not set\n# CONFIG_MMC_SDHCI_CADENCE is not set\n# CONFIG_MMC_SDHCI_F_SDH30 is not set\n# CONFIG_MMC_SDHCI_IPROC is not set\n# CONFIG_MMC_SDHCI_MILBEAUT is not set\n# CONFIG_MMC_SDHCI_MSM is not set\n# CONFIG_MMC_SDHCI_OF_ARASAN is not set\n# CONFIG_MMC_SDHCI_OF_ASPEED is not set\n# CONFIG_MMC_SDHCI_OF_AT91 is not set\n# CONFIG_MMC_SDHCI_OF_DWCMSHC is not set\n# CONFIG_MMC_SDHCI_OF_ESDHC is not set\n# CONFIG_MMC_SDHCI_OF_HLWD is not set\n# CONFIG_MMC_SDHCI_OMAP is not set\n# CONFIG_MMC_SDHCI_PXAV2 is not set\n# CONFIG_MMC_SDHCI_PXAV3 is not set\n# CONFIG_MMC_SDHCI_S3C is not set\n# CONFIG_MMC_SDHCI_XENON is not set\n# CONFIG_MMC_SDRICOH_CS is not set\n# CONFIG_MMC_SPI is not set\n# CONFIG_MMC_STM32_SDMMC is not set\n# CONFIG_MMC_TEST is not set\n# CONFIG_MMC_TIFM_SD is not set\n# CONFIG_MMC_TOSHIBA_PCI is not set\n# CONFIG_MMC_USDHI6ROL0 is not set\n# CONFIG_MMC_USHC is not set\n# CONFIG_MMC_VIA_SDMMC is not set\n# CONFIG_MMC_VUB300 is not set\n# CONFIG_MMIOTRACE is not set\nCONFIG_MMU=y\nCONFIG_MMU_GATHER_RCU_TABLE_FREE=y\nCONFIG_MMU_GATHER_TABLE_FREE=y\nCONFIG_MODPROBE_PATH=\"/sbin/modprobe\"\nCONFIG_MODULES=y\n# CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set\n# CONFIG_MODULE_COMPRESS is not set\n# CONFIG_MODULE_COMPRESS_GZIP is not set\nCONFIG_MODULE_COMPRESS_NONE=y\n# CONFIG_MODULE_COMPRESS_XZ is not set\n# CONFIG_MODULE_COMPRESS_ZSTD is not set\n# CONFIG_MODULE_FORCE_LOAD is not set\n# CONFIG_MODULE_FORCE_UNLOAD is not set\n# CONFIG_MODULE_SIG is not set\n# CONFIG_MODULE_SRCVERSION_ALL is not set\nCONFIG_MODULE_STRIPPED=y\nCONFIG_MODULE_UNLOAD=y\n# CONFIG_MODVERSIONS is not set\n# CONFIG_MOST is not set\n# CONFIG_MOTORCOMM_PHY is not set\n# CONFIG_MOUSE_APPLETOUCH is not set\n# CONFIG_MOUSE_ELAN_I2C is not set\n# CONFIG_MOUSE_GPIO is not set\n# CONFIG_MOUSE_INPORT is not set\n# CONFIG_MOUSE_LOGIBM is not set\n# CONFIG_MOUSE_PC110PAD is not set\n# CONFIG_MOUSE_PS2_FOCALTECH is not set\n# CONFIG_MOUSE_PS2_SENTELIC is not set\n# CONFIG_MOUSE_SYNAPTICS_I2C is not set\n# CONFIG_MOUSE_SYNAPTICS_USB is not set\n# CONFIG_MOXTET is not set\n# CONFIG_MPL115 is not set\n# CONFIG_MPL115_I2C is not set\n# CONFIG_MPL115_SPI is not set\n# CONFIG_MPL3115 is not set\n# CONFIG_MPLS is not set\n# CONFIG_MPLS_IPTUNNEL is not set\n# CONFIG_MPLS_ROUTING is not set\n# CONFIG_MPTCP is not set\n# CONFIG_MPU3050_I2C is not set\n# CONFIG_MQ_IOSCHED_DEADLINE is not set\n# CONFIG_MQ_IOSCHED_KYBER is not set\n# CONFIG_MS5611 is not set\n# CONFIG_MS5637 is not set\n# CONFIG_MSCC_OCELOT_SWITCH is not set\n# CONFIG_MSDOS_FS is not set\nCONFIG_MSDOS_PARTITION=y\n# CONFIG_MSI_BITMAP_SELFTEST is not set\n# CONFIG_MSI_LAPTOP is not set\n# CONFIG_MSM_GCC_8953 is not set\n# CONFIG_MSM_MMCC_8994 is not set\n# CONFIG_MST_IRQ is not set\nCONFIG_MTD=y\n# CONFIG_MTD_ABSENT is not set\n# CONFIG_MTD_AFS_PARTS is not set\n# CONFIG_MTD_AR7_PARTS is not set\nCONFIG_MTD_BLKDEVS=y\nCONFIG_MTD_BLOCK=y\n# CONFIG_MTD_BLOCK2MTD is not set\nCONFIG_MTD_CFI=y\n# CONFIG_MTD_CFI_ADV_OPTIONS is not set\nCONFIG_MTD_CFI_AMDSTD=y\n# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set\nCONFIG_MTD_CFI_I1=y\nCONFIG_MTD_CFI_I2=y\n# CONFIG_MTD_CFI_I4 is not set\n# CONFIG_MTD_CFI_I8 is not set\nCONFIG_MTD_CFI_INTELEXT=y\n# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set\nCONFIG_MTD_CFI_NOSWAP=y\n# CONFIG_MTD_CFI_STAA is not set\nCONFIG_MTD_CFI_UTIL=y\n# CONFIG_MTD_CMDLINE_PARTS is not set\nCONFIG_MTD_COMPLEX_MAPPINGS=y\n# CONFIG_MTD_DATAFLASH is not set\n# CONFIG_MTD_DOCG3 is not set\nCONFIG_MTD_GEN_PROBE=y\n# CONFIG_MTD_GPIO_ADDR is not set\n# CONFIG_MTD_HYPERBUS is not set\n# CONFIG_MTD_IMPA7 is not set\n# CONFIG_MTD_INTEL_VR_NOR is not set\n# CONFIG_MTD_JEDECPROBE is not set\n# CONFIG_MTD_LATCH_ADDR is not set\n# CONFIG_MTD_LPDDR is not set\n# CONFIG_MTD_LPDDR2_NVM is not set\n# CONFIG_MTD_M25P80 is not set\nCONFIG_MTD_MAP_BANK_WIDTH_1=y\n# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set\nCONFIG_MTD_MAP_BANK_WIDTH_2=y\n# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set\nCONFIG_MTD_MAP_BANK_WIDTH_4=y\n# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set\n# CONFIG_MTD_MCHP23K256 is not set\n# CONFIG_MTD_MCHP48L640 is not set\n# CONFIG_MTD_MT81xx_NOR is not set\n# CONFIG_MTD_MTDRAM is not set\n# CONFIG_MTD_MYLOADER_PARTS is not set\n# CONFIG_MTD_NAND is not set\n# CONFIG_MTD_NAND_AMS_DELTA is not set\n# CONFIG_MTD_NAND_AR934X is not set\n# CONFIG_MTD_NAND_AR934X_HW_ECC is not set\n# CONFIG_MTD_NAND_ARASAN is not set\n# CONFIG_MTD_NAND_ATMEL is not set\n# CONFIG_MTD_NAND_AU1550 is not set\n# CONFIG_MTD_NAND_BCH is not set\n# CONFIG_MTD_NAND_BF5XX is not set\n# CONFIG_MTD_NAND_BRCMNAND is not set\n# CONFIG_MTD_NAND_CADENCE is not set\n# CONFIG_MTD_NAND_CAFE is not set\n# CONFIG_MTD_NAND_CM_X270 is not set\n# CONFIG_MTD_NAND_CS553X is not set\n# CONFIG_MTD_NAND_DAVINCI is not set\n# CONFIG_MTD_NAND_DENALI is not set\n# CONFIG_MTD_NAND_DENALI_DT is not set\n# CONFIG_MTD_NAND_DENALI_PCI is not set\nCONFIG_MTD_NAND_DENALI_SCRATCH_REG_ADDR=0xff108018\n# CONFIG_MTD_NAND_DISKONCHIP is not set\n# CONFIG_MTD_NAND_DOCG4 is not set\n# CONFIG_MTD_NAND_ECC is not set\n# CONFIG_MTD_NAND_ECC_BCH is not set\n# CONFIG_MTD_NAND_ECC_SMC is not set\n# CONFIG_MTD_NAND_ECC_SW_BCH is not set\n# CONFIG_MTD_NAND_ECC_SW_HAMMING is not set\n# CONFIG_MTD_NAND_ECC_SW_HAMMING_SMC is not set\n# CONFIG_MTD_NAND_FSL_ELBC is not set\n# CONFIG_MTD_NAND_FSL_IFC is not set\n# CONFIG_MTD_NAND_FSL_UPM is not set\n# CONFIG_MTD_NAND_FSMC is not set\n# CONFIG_MTD_NAND_GPIO is not set\n# CONFIG_MTD_NAND_GPMI_NAND is not set\n# CONFIG_MTD_NAND_HISI504 is not set\nCONFIG_MTD_NAND_IDS=y\n# CONFIG_MTD_NAND_INTEL_LGM is not set\n# CONFIG_MTD_NAND_JZ4740 is not set\n# CONFIG_MTD_NAND_MPC5121_NFC is not set\n# CONFIG_MTD_NAND_MTK is not set\n# CONFIG_MTD_NAND_MTK_BMT is not set\n# CONFIG_MTD_NAND_MXC is not set\n# CONFIG_MTD_NAND_MXIC is not set\n# CONFIG_MTD_NAND_NANDSIM is not set\n# CONFIG_MTD_NAND_NDFC is not set\n# CONFIG_MTD_NAND_NUC900 is not set\n# CONFIG_MTD_NAND_OMAP2 is not set\n# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set\n# CONFIG_MTD_NAND_ORION is not set\n# CONFIG_MTD_NAND_PASEMI is not set\n# CONFIG_MTD_NAND_PLATFORM is not set\n# CONFIG_MTD_NAND_PXA3xx is not set\n# CONFIG_MTD_NAND_RB4XX is not set\n# CONFIG_MTD_NAND_RB750 is not set\n# CONFIG_MTD_NAND_RB91X is not set\n# CONFIG_MTD_NAND_RICOH is not set\n# CONFIG_MTD_NAND_S3C2410 is not set\n# CONFIG_MTD_NAND_SHARPSL is not set\n# CONFIG_MTD_NAND_SH_FLCTL is not set\n# CONFIG_MTD_NAND_SOCRATES is not set\n# CONFIG_MTD_NAND_TMIO is not set\n# CONFIG_MTD_NAND_TXX9NDFMC is not set\nCONFIG_MTD_OF_PARTS=y\n# CONFIG_MTD_ONENAND is not set\n# CONFIG_MTD_OOPS is not set\n# CONFIG_MTD_OTP is not set\n# CONFIG_MTD_PARSER_TRX is not set\n# CONFIG_MTD_PARTITIONED_MASTER is not set\n# CONFIG_MTD_PCI is not set\n# CONFIG_MTD_PCMCIA is not set\n# CONFIG_MTD_PHRAM is not set\n# CONFIG_MTD_PHYSMAP is not set\n# CONFIG_MTD_PHYSMAP_COMPAT is not set\n# CONFIG_MTD_PHYSMAP_GEMINI is not set\n# CONFIG_MTD_PHYSMAP_GPIO_ADDR is not set\n# CONFIG_MTD_PHYSMAP_IXP4XX is not set\nCONFIG_MTD_PHYSMAP_OF=y\n# CONFIG_MTD_PHYSMAP_OF_GEMINI is not set\n# CONFIG_MTD_PHYSMAP_OF_VERSATILE is not set\n# CONFIG_MTD_PHYSMAP_VERSATILE is not set\n# CONFIG_MTD_PLATRAM is not set\n# CONFIG_MTD_PMC551 is not set\n# CONFIG_MTD_RAM is not set\n# CONFIG_MTD_RAW_NAND is not set\nCONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1\n# CONFIG_MTD_REDBOOT_PARTS is not set\n# CONFIG_MTD_REDBOOT_PARTS_READONLY is not set\n# CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED is not set\n# CONFIG_MTD_ROM is not set\nCONFIG_MTD_ROOTFS_ROOT_DEV=y\n# CONFIG_MTD_ROUTERBOOT_PARTS is not set\n# CONFIG_MTD_SLRAM is not set\n# CONFIG_MTD_SM_COMMON is not set\n# CONFIG_MTD_SPINAND_MT29F is not set\n# CONFIG_MTD_SPI_NAND is not set\n# CONFIG_MTD_SPI_NOR is not set\n# CONFIG_MTD_SPI_NOR_SWP_DISABLE is not set\nCONFIG_MTD_SPI_NOR_SWP_DISABLE_ON_VOLATILE=y\n# CONFIG_MTD_SPI_NOR_SWP_KEEP is not set\n# CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set\nCONFIG_MTD_SPI_NOR_USE_4K_SECTORS_LIMIT=4096\n# CONFIG_MTD_SPI_NOR_USE_VARIABLE_ERASE is not set\nCONFIG_MTD_SPLIT=y\n# CONFIG_MTD_SPLIT_BCM63XX_FW is not set\n# CONFIG_MTD_SPLIT_BCM_WFI_FW is not set\n# CONFIG_MTD_SPLIT_BRNIMAGE_FW is not set\n# CONFIG_MTD_SPLIT_ELF_FW is not set\n# CONFIG_MTD_SPLIT_EVA_FW is not set\n# CONFIG_MTD_SPLIT_FIRMWARE is not set\nCONFIG_MTD_SPLIT_FIRMWARE_NAME=\"firmware\"\n# CONFIG_MTD_SPLIT_FIT_FW is not set\n# CONFIG_MTD_SPLIT_JIMAGE_FW is not set\n# CONFIG_MTD_SPLIT_LZMA_FW is not set\n# CONFIG_MTD_SPLIT_MINOR_FW is not set\n# CONFIG_MTD_SPLIT_SEAMA_FW is not set\nCONFIG_MTD_SPLIT_SQUASHFS_ROOT=y\nCONFIG_MTD_SPLIT_SUPPORT=y\n# CONFIG_MTD_SPLIT_TPLINK_FW is not set\n# CONFIG_MTD_SPLIT_TRX_FW is not set\n# CONFIG_MTD_SPLIT_UIMAGE_FW is not set\n# CONFIG_MTD_SPLIT_WRGG_FW is not set\n# CONFIG_MTD_SST25L is not set\n# CONFIG_MTD_SWAP is not set\n# CONFIG_MTD_TESTS is not set\n# CONFIG_MTD_UBI is not set\n# CONFIG_MTD_UBI_FASTMAP is not set\n# CONFIG_MTD_UBI_GLUEBI is not set\n# CONFIG_MTD_UIMAGE_SPLIT is not set\n# CONFIG_MTD_VIRT_CONCAT is not set\n# CONFIG_MTK_DEVAPC is not set\n# CONFIG_MTK_MMC is not set\n# CONFIG_MTK_MMSYS is not set\n# CONFIG_MULTIPLEXER is not set\nCONFIG_MULTIUSER=y\n# CONFIG_MUTEX_SPIN_ON_OWNER is not set\n# CONFIG_MUX_ADG792A is not set\n# CONFIG_MUX_ADGS1408 is not set\n# CONFIG_MUX_GPIO is not set\n# CONFIG_MUX_MMIO is not set\n# CONFIG_MV643XX_ETH is not set\n# CONFIG_MVMDIO is not set\n# CONFIG_MVNETA_BM is not set\n# CONFIG_MVSW61XX_PHY is not set\n# CONFIG_MV_XOR_V2 is not set\n# CONFIG_MWAVE is not set\n# CONFIG_MWL8K is not set\n# CONFIG_MXC4005 is not set\n# CONFIG_MXC6255 is not set\n# CONFIG_MYRI10GE is not set\n# CONFIG_NAMESPACES is not set\n# CONFIG_NATIONAL_PHY is not set\n# CONFIG_NATSEMI is not set\n# CONFIG_NAU7802 is not set\n# CONFIG_NBPFAXI_DMA is not set\n# CONFIG_NCP_FS is not set\n# CONFIG_NE2000 is not set\n# CONFIG_NE2K_PCI is not set\n# CONFIG_NEC_MARKEINS is not set\nCONFIG_NET=y\n# CONFIG_NETCONSOLE is not set\nCONFIG_NETDEVICES=y\n# CONFIG_NETDEVSIM is not set\n# CONFIG_NETFILTER is not set\n# CONFIG_NETFILTER_ADVANCED is not set\n# CONFIG_NETFILTER_DEBUG is not set\n# CONFIG_NETFILTER_INGRESS is not set\n# CONFIG_NETFILTER_NETLINK is not set\n# CONFIG_NETFILTER_NETLINK_ACCT is not set\n# CONFIG_NETFILTER_NETLINK_GLUE_CT is not set\n# CONFIG_NETFILTER_NETLINK_HOOK is not set\n# CONFIG_NETFILTER_NETLINK_LOG is not set\n# CONFIG_NETFILTER_NETLINK_OSF is not set\n# CONFIG_NETFILTER_NETLINK_QUEUE is not set\n# CONFIG_NETFILTER_XTABLES is not set\n# CONFIG_NETFILTER_XTABLES_COMPAT is not set\n# CONFIG_NETFILTER_XT_CONNMARK is not set\n# CONFIG_NETFILTER_XT_MARK is not set\n# CONFIG_NETFILTER_XT_MATCH_ADDRTYPE is not set\n# CONFIG_NETFILTER_XT_MATCH_BPF is not set\n# CONFIG_NETFILTER_XT_MATCH_CGROUP is not set\n# CONFIG_NETFILTER_XT_MATCH_CLUSTER is not set\n# CONFIG_NETFILTER_XT_MATCH_COMMENT is not set\n# CONFIG_NETFILTER_XT_MATCH_CONNBYTES is not set\n# CONFIG_NETFILTER_XT_MATCH_CONNLABEL is not set\n# CONFIG_NETFILTER_XT_MATCH_CONNLIMIT is not set\n# CONFIG_NETFILTER_XT_MATCH_CONNMARK is not set\n# CONFIG_NETFILTER_XT_MATCH_CONNTRACK is not set\n# CONFIG_NETFILTER_XT_MATCH_CPU is not set\n# CONFIG_NETFILTER_XT_MATCH_DCCP is not set\n# CONFIG_NETFILTER_XT_MATCH_DEVGROUP is not set\n# CONFIG_NETFILTER_XT_MATCH_DSCP is not set\n# CONFIG_NETFILTER_XT_MATCH_ECN is not set\n# CONFIG_NETFILTER_XT_MATCH_ESP is not set\n# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set\n# CONFIG_NETFILTER_XT_MATCH_HELPER is not set\n# CONFIG_NETFILTER_XT_MATCH_HL is not set\n# CONFIG_NETFILTER_XT_MATCH_IPCOMP is not set\n# CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set\n# CONFIG_NETFILTER_XT_MATCH_L2TP is not set\n# CONFIG_NETFILTER_XT_MATCH_LENGTH is not set\n# CONFIG_NETFILTER_XT_MATCH_LIMIT is not set\n# CONFIG_NETFILTER_XT_MATCH_MAC is not set\n# CONFIG_NETFILTER_XT_MATCH_MARK is not set\n# CONFIG_NETFILTER_XT_MATCH_MULTIPORT is not set\n# CONFIG_NETFILTER_XT_MATCH_NFACCT is not set\n# CONFIG_NETFILTER_XT_MATCH_OSF is not set\n# CONFIG_NETFILTER_XT_MATCH_OWNER is not set\n# CONFIG_NETFILTER_XT_MATCH_PHYSDEV is not set\n# CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set\n# CONFIG_NETFILTER_XT_MATCH_POLICY is not set\n# CONFIG_NETFILTER_XT_MATCH_QUOTA is not set\n# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set\n# CONFIG_NETFILTER_XT_MATCH_REALM is not set\n# CONFIG_NETFILTER_XT_MATCH_RECENT is not set\n# CONFIG_NETFILTER_XT_MATCH_SCTP is not set\n# CONFIG_NETFILTER_XT_MATCH_SOCKET is not set\n# CONFIG_NETFILTER_XT_MATCH_STATE is not set\n# CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set\n# CONFIG_NETFILTER_XT_MATCH_STRING is not set\n# CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set\n# CONFIG_NETFILTER_XT_MATCH_TIME is not set\n# CONFIG_NETFILTER_XT_MATCH_U32 is not set\n# CONFIG_NETFILTER_XT_TARGET_AUDIT is not set\n# CONFIG_NETFILTER_XT_TARGET_CHECKSUM is not set\n# CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set\n# CONFIG_NETFILTER_XT_TARGET_CONNMARK is not set\n# CONFIG_NETFILTER_XT_TARGET_CT is not set\n# CONFIG_NETFILTER_XT_TARGET_DSCP is not set\n# CONFIG_NETFILTER_XT_TARGET_HL is not set\n# CONFIG_NETFILTER_XT_TARGET_HMARK is not set\n# CONFIG_NETFILTER_XT_TARGET_IDLETIMER is not set\n# CONFIG_NETFILTER_XT_TARGET_LED is not set\n# CONFIG_NETFILTER_XT_TARGET_LOG is not set\n# CONFIG_NETFILTER_XT_TARGET_MARK is not set\n# CONFIG_NETFILTER_XT_TARGET_NETMAP is not set\n# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set\n# CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set\n# CONFIG_NETFILTER_XT_TARGET_NOTRACK is not set\n# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set\n# CONFIG_NETFILTER_XT_TARGET_REDIRECT is not set\n# CONFIG_NETFILTER_XT_TARGET_SECMARK is not set\n# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set\n# CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP is not set\n# CONFIG_NETFILTER_XT_TARGET_TEE is not set\n# CONFIG_NETFILTER_XT_TARGET_TPROXY is not set\n# CONFIG_NETFILTER_XT_TARGET_TRACE is not set\n# CONFIG_NETLABEL is not set\n# CONFIG_NETLINK_DIAG is not set\n# CONFIG_NETLINK_MMAP is not set\n# CONFIG_NETPOLL is not set\n# CONFIG_NETROM is not set\nCONFIG_NETWORK_FILESYSTEMS=y\n# CONFIG_NETWORK_PHY_TIMESTAMPING is not set\n# CONFIG_NETWORK_SECMARK is not set\n# CONFIG_NETXEN_NIC is not set\n# CONFIG_NET_9P is not set\n# CONFIG_NET_ACT_BPF is not set\n# CONFIG_NET_ACT_CSUM is not set\n# CONFIG_NET_ACT_CT is not set\n# CONFIG_NET_ACT_GACT is not set\n# CONFIG_NET_ACT_GATE is not set\n# CONFIG_NET_ACT_IFE is not set\n# CONFIG_NET_ACT_IPT is not set\n# CONFIG_NET_ACT_MIRRED is not set\n# CONFIG_NET_ACT_MPLS is not set\n# CONFIG_NET_ACT_NAT is not set\n# CONFIG_NET_ACT_PEDIT is not set\n# CONFIG_NET_ACT_POLICE is not set\n# CONFIG_NET_ACT_SAMPLE is not set\n# CONFIG_NET_ACT_SIMP is not set\n# CONFIG_NET_ACT_SKBEDIT is not set\n# CONFIG_NET_ACT_SKBMOD is not set\n# CONFIG_NET_ACT_TUNNEL_KEY is not set\n# CONFIG_NET_ACT_VLAN is not set\nCONFIG_NET_CADENCE=y\n# CONFIG_NET_CALXEDA_XGMAC is not set\nCONFIG_NET_CLS=y\n# CONFIG_NET_CLS_ACT is not set\n# CONFIG_NET_CLS_BASIC is not set\n# CONFIG_NET_CLS_BPF is not set\n# CONFIG_NET_CLS_FLOW is not set\n# CONFIG_NET_CLS_FLOWER is not set\n# CONFIG_NET_CLS_FW is not set\nCONFIG_NET_CLS_IND=y\n# CONFIG_NET_CLS_MATCHALL is not set\n# CONFIG_NET_CLS_ROUTE4 is not set\n# CONFIG_NET_CLS_RSVP is not set\n# CONFIG_NET_CLS_RSVP6 is not set\n# CONFIG_NET_CLS_TCINDEX is not set\n# CONFIG_NET_CLS_U32 is not set\nCONFIG_NET_CORE=y\n# CONFIG_NET_DEVLINK is not set\n# CONFIG_NET_DROP_MONITOR is not set\n# CONFIG_NET_DSA is not set\n# CONFIG_NET_DSA_AR9331 is not set\n# CONFIG_NET_DSA_BCM_SF2 is not set\n# CONFIG_NET_DSA_LANTIQ_GSWIP is not set\n# CONFIG_NET_DSA_LEGACY is not set\n# CONFIG_NET_DSA_LOOP is not set\n# CONFIG_NET_DSA_MICROCHIP_KSZ8795 is not set\n# CONFIG_NET_DSA_MICROCHIP_KSZ9477 is not set\n# CONFIG_NET_DSA_MSCC_FELIX is not set\n# CONFIG_NET_DSA_MSCC_SEVILLE is not set\n# CONFIG_NET_DSA_MT7530 is not set\n# CONFIG_NET_DSA_MV88E6060 is not set\n# CONFIG_NET_DSA_MV88E6123_61_65 is not set\n# CONFIG_NET_DSA_MV88E6131 is not set\n# CONFIG_NET_DSA_MV88E6171 is not set\n# CONFIG_NET_DSA_MV88E6352 is not set\n# CONFIG_NET_DSA_MV88E6XXX is not set\n# CONFIG_NET_DSA_MV88E6XXX_NEED_PPU is not set\n# CONFIG_NET_DSA_MV88E6XXX_PTP is not set\n# CONFIG_NET_DSA_QCA8K is not set\n# CONFIG_NET_DSA_REALTEK_SMI is not set\n# CONFIG_NET_DSA_SJA1105 is not set\n# CONFIG_NET_DSA_SMSC_LAN9303_I2C is not set\n# CONFIG_NET_DSA_SMSC_LAN9303_MDIO is not set\n# CONFIG_NET_DSA_TAG_8021Q is not set\n# CONFIG_NET_DSA_TAG_AR9331 is not set\n# CONFIG_NET_DSA_TAG_BRCM is not set\n# CONFIG_NET_DSA_TAG_BRCM_LEGACY is not set\n# CONFIG_NET_DSA_TAG_BRCM_PREPEND is not set\n# CONFIG_NET_DSA_TAG_DSA is not set\n# CONFIG_NET_DSA_TAG_EDSA is not set\n# CONFIG_NET_DSA_TAG_GSWIP is not set\n# CONFIG_NET_DSA_TAG_HELLCREEK is not set\n# CONFIG_NET_DSA_TAG_KSZ is not set\n# CONFIG_NET_DSA_TAG_LAN9303 is not set\n# CONFIG_NET_DSA_TAG_MTK is not set\n# CONFIG_NET_DSA_TAG_OCELOT is not set\n# CONFIG_NET_DSA_TAG_OCELOT_8021Q is not set\n# CONFIG_NET_DSA_TAG_QCA is not set\n# CONFIG_NET_DSA_TAG_RTL4_A is not set\n# CONFIG_NET_DSA_TAG_SJA1105 is not set\n# CONFIG_NET_DSA_TAG_TRAILER is not set\n# CONFIG_NET_DSA_TAG_XRS700X is not set\n# CONFIG_NET_DSA_VITESSE_VSC73XX is not set\n# CONFIG_NET_DSA_VITESSE_VSC73XX_PLATFORM is not set\n# CONFIG_NET_DSA_VITESSE_VSC73XX_SPI is not set\n# CONFIG_NET_DSA_XRS700X_I2C is not set\n# CONFIG_NET_DSA_XRS700X_MDIO is not set\n# CONFIG_NET_EMATCH is not set\n# CONFIG_NET_EMATCH_CANID is not set\n# CONFIG_NET_EMATCH_CMP is not set\n# CONFIG_NET_EMATCH_IPT is not set\n# CONFIG_NET_EMATCH_META is not set\n# CONFIG_NET_EMATCH_NBYTE is not set\nCONFIG_NET_EMATCH_STACK=32\n# CONFIG_NET_EMATCH_TEXT is not set\n# CONFIG_NET_EMATCH_U32 is not set\n# CONFIG_NET_FAILOVER is not set\n# CONFIG_NET_FC is not set\n# CONFIG_NET_FOU is not set\n# CONFIG_NET_FOU_IP_TUNNELS is not set\n# CONFIG_NET_IFE is not set\n# CONFIG_NET_IPGRE is not set\nCONFIG_NET_IPGRE_BROADCAST=y\n# CONFIG_NET_IPGRE_DEMUX is not set\n# CONFIG_NET_IPIP is not set\n# CONFIG_NET_IPVTI is not set\n# CONFIG_NET_IP_TUNNEL is not set\n# CONFIG_NET_KEY is not set\n# CONFIG_NET_KEY_MIGRATE is not set\n# CONFIG_NET_L3_MASTER_DEV is not set\n# CONFIG_NET_MEDIATEK_STAR_EMAC is not set\n# CONFIG_NET_MPLS_GSO is not set\n# CONFIG_NET_NCSI is not set\n# CONFIG_NET_NSH is not set\n# CONFIG_NET_PACKET_ENGINE is not set\n# CONFIG_NET_PKTGEN is not set\n# CONFIG_NET_POLL_CONTROLLER is not set\n# CONFIG_NET_PTP_CLASSIFY is not set\nCONFIG_NET_RX_BUSY_POLL=y\n# CONFIG_NET_SB1000 is not set\nCONFIG_NET_SCHED=y\n# CONFIG_NET_SCH_ATM is not set\n# CONFIG_NET_SCH_CAKE is not set\n# CONFIG_NET_SCH_CBQ is not set\n# CONFIG_NET_SCH_CBS is not set\n# CONFIG_NET_SCH_CHOKE is not set\n# CONFIG_NET_SCH_CODEL is not set\nCONFIG_NET_SCH_DEFAULT=y\n# CONFIG_NET_SCH_DRR is not set\n# CONFIG_NET_SCH_DSMARK is not set\n# CONFIG_NET_SCH_ETF is not set\n# CONFIG_NET_SCH_ETS is not set\nCONFIG_NET_SCH_FIFO=y\n# CONFIG_NET_SCH_FQ is not set\nCONFIG_NET_SCH_FQ_CODEL=y\n# CONFIG_NET_SCH_FQ_PIE is not set\n# CONFIG_NET_SCH_GRED is not set\n# CONFIG_NET_SCH_HFSC is not set\n# CONFIG_NET_SCH_HHF is not set\n# CONFIG_NET_SCH_HTB is not set\n# CONFIG_NET_SCH_INGRESS is not set\n# CONFIG_NET_SCH_MQPRIO is not set\n# CONFIG_NET_SCH_MULTIQ is not set\n# CONFIG_NET_SCH_NETEM is not set\n# CONFIG_NET_SCH_PIE is not set\n# CONFIG_NET_SCH_PLUG is not set\n# CONFIG_NET_SCH_PRIO is not set\n# CONFIG_NET_SCH_QFQ is not set\n# CONFIG_NET_SCH_RED is not set\n# CONFIG_NET_SCH_SFB is not set\n# CONFIG_NET_SCH_SFQ is not set\n# CONFIG_NET_SCH_SKBPRIO is not set\n# CONFIG_NET_SCH_TAPRIO is not set\n# CONFIG_NET_SCH_TBF is not set\n# CONFIG_NET_SCH_TEQL is not set\n# CONFIG_NET_SCTPPROBE is not set\n# CONFIG_NET_SELFTESTS is not set\nCONFIG_NET_SOCK_MSG=y\n# CONFIG_NET_SWITCHDEV is not set\n# CONFIG_NET_TCPPROBE is not set\n# CONFIG_NET_TC_SKB_EXT is not set\n# CONFIG_NET_TEAM is not set\n# CONFIG_NET_TULIP is not set\n# CONFIG_NET_UDP_TUNNEL is not set\nCONFIG_NET_VENDOR_3COM=y\nCONFIG_NET_VENDOR_8390=y\nCONFIG_NET_VENDOR_ADAPTEC=y\nCONFIG_NET_VENDOR_AGERE=y\nCONFIG_NET_VENDOR_ALACRITECH=y\nCONFIG_NET_VENDOR_ALTEON=y\nCONFIG_NET_VENDOR_AMAZON=y\nCONFIG_NET_VENDOR_AMD=y\nCONFIG_NET_VENDOR_AQUANTIA=y\nCONFIG_NET_VENDOR_ARC=y\nCONFIG_NET_VENDOR_ATHEROS=y\nCONFIG_NET_VENDOR_AURORA=y\nCONFIG_NET_VENDOR_BROADCOM=y\nCONFIG_NET_VENDOR_BROCADE=y\nCONFIG_NET_VENDOR_CADENCE=y\nCONFIG_NET_VENDOR_CAVIUM=y\nCONFIG_NET_VENDOR_CHELSIO=y\nCONFIG_NET_VENDOR_CIRRUS=y\nCONFIG_NET_VENDOR_CISCO=y\nCONFIG_NET_VENDOR_CORTINA=y\nCONFIG_NET_VENDOR_DEC=y\nCONFIG_NET_VENDOR_DLINK=y\nCONFIG_NET_VENDOR_EMULEX=y\nCONFIG_NET_VENDOR_EXAR=y\nCONFIG_NET_VENDOR_EZCHIP=y\nCONFIG_NET_VENDOR_FARADAY=y\nCONFIG_NET_VENDOR_FREESCALE=y\nCONFIG_NET_VENDOR_FUJITSU=y\nCONFIG_NET_VENDOR_GOOGLE=y\nCONFIG_NET_VENDOR_HISILICON=y\nCONFIG_NET_VENDOR_HP=y\nCONFIG_NET_VENDOR_HUAWEI=y\nCONFIG_NET_VENDOR_I825XX=y\nCONFIG_NET_VENDOR_IBM=y\nCONFIG_NET_VENDOR_INTEL=y\n# CONFIG_NET_VENDOR_LITEX is not set\nCONFIG_NET_VENDOR_MARVELL=y\nCONFIG_NET_VENDOR_MELLANOX=y\nCONFIG_NET_VENDOR_MICREL=y\nCONFIG_NET_VENDOR_MICROCHIP=y\nCONFIG_NET_VENDOR_MICROSEMI=y\n# CONFIG_NET_VENDOR_MICROSOFT is not set\nCONFIG_NET_VENDOR_MYRI=y\nCONFIG_NET_VENDOR_NATSEMI=y\nCONFIG_NET_VENDOR_NETERION=y\nCONFIG_NET_VENDOR_NETRONOME=y\nCONFIG_NET_VENDOR_NI=y\nCONFIG_NET_VENDOR_NVIDIA=y\nCONFIG_NET_VENDOR_OKI=y\nCONFIG_NET_VENDOR_PACKET_ENGINES=y\nCONFIG_NET_VENDOR_PENSANDO=y\nCONFIG_NET_VENDOR_QLOGIC=y\nCONFIG_NET_VENDOR_QUALCOMM=y\nCONFIG_NET_VENDOR_RDC=y\nCONFIG_NET_VENDOR_REALTEK=y\nCONFIG_NET_VENDOR_RENESAS=y\nCONFIG_NET_VENDOR_ROCKER=y\nCONFIG_NET_VENDOR_SAMSUNG=y\nCONFIG_NET_VENDOR_SEEQ=y\nCONFIG_NET_VENDOR_SILAN=y\nCONFIG_NET_VENDOR_SIS=y\nCONFIG_NET_VENDOR_SMSC=y\nCONFIG_NET_VENDOR_SOCIONEXT=y\nCONFIG_NET_VENDOR_SOLARFLARE=y\nCONFIG_NET_VENDOR_STMICRO=y\nCONFIG_NET_VENDOR_SUN=y\nCONFIG_NET_VENDOR_SYNOPSYS=y\nCONFIG_NET_VENDOR_TEHUTI=y\nCONFIG_NET_VENDOR_TI=y\nCONFIG_NET_VENDOR_TOSHIBA=y\nCONFIG_NET_VENDOR_VIA=y\nCONFIG_NET_VENDOR_WIZNET=y\nCONFIG_NET_VENDOR_XILINX=y\nCONFIG_NET_VENDOR_XIRCOM=y\n# CONFIG_NET_VRF is not set\n# CONFIG_NET_XGENE is not set\nCONFIG_NEW_LEDS=y\n# CONFIG_NFC is not set\n# CONFIG_NFP is not set\n# CONFIG_NFSD is not set\n# CONFIG_NFSD_V2_ACL is not set\nCONFIG_NFSD_V3=y\n# CONFIG_NFSD_V3_ACL is not set\n# CONFIG_NFSD_V4 is not set\n# CONFIG_NFS_ACL_SUPPORT is not set\nCONFIG_NFS_COMMON=y\n# CONFIG_NFS_DISABLE_UDP_SUPPORT is not set\n# CONFIG_NFS_FS is not set\n# CONFIG_NFS_FSCACHE is not set\n# CONFIG_NFS_SWAP is not set\n# CONFIG_NFS_V2 is not set\nCONFIG_NFS_V3=y\n# CONFIG_NFS_V3_ACL is not set\n# CONFIG_NFS_V4 is not set\n# CONFIG_NFS_V4_1 is not set\n# CONFIG_NFTL is not set\n# CONFIG_NFT_BRIDGE_META is not set\n# CONFIG_NFT_BRIDGE_REJECT is not set\n# CONFIG_NFT_CONNLIMIT is not set\n# CONFIG_NFT_DUP_IPV4 is not set\n# CONFIG_NFT_DUP_IPV6 is not set\n# CONFIG_NFT_FIB_IPV4 is not set\n# CONFIG_NFT_FIB_IPV6 is not set\n# CONFIG_NFT_FIB_NETDEV is not set\n# CONFIG_NFT_FLOW_OFFLOAD is not set\n# CONFIG_NFT_OBJREF is not set\n# CONFIG_NFT_OSF is not set\n# CONFIG_NFT_REJECT_NETDEV is not set\n# CONFIG_NFT_RT is not set\n# CONFIG_NFT_SET_BITMAP is not set\n# CONFIG_NFT_SOCKET is not set\n# CONFIG_NFT_SYNPROXY is not set\n# CONFIG_NFT_TPROXY is not set\n# CONFIG_NFT_TUNNEL is not set\n# CONFIG_NFT_XFRM is not set\n# CONFIG_NF_CONNTRACK is not set\n# CONFIG_NF_CONNTRACK_AMANDA is not set\n# CONFIG_NF_CONNTRACK_BRIDGE is not set\n# CONFIG_NF_CONNTRACK_EVENTS is not set\n# CONFIG_NF_CONNTRACK_FTP is not set\n# CONFIG_NF_CONNTRACK_H323 is not set\n# CONFIG_NF_CONNTRACK_IRC is not set\n# CONFIG_NF_CONNTRACK_LABELS is not set\n# CONFIG_NF_CONNTRACK_MARK is not set\n# CONFIG_NF_CONNTRACK_NETBIOS_NS is not set\n# CONFIG_NF_CONNTRACK_PPTP is not set\nCONFIG_NF_CONNTRACK_PROCFS=y\n# CONFIG_NF_CONNTRACK_PROC_COMPAT is not set\n# CONFIG_NF_CONNTRACK_SANE is not set\n# CONFIG_NF_CONNTRACK_SECMARK is not set\n# CONFIG_NF_CONNTRACK_SIP is not set\n# CONFIG_NF_CONNTRACK_SNMP is not set\n# CONFIG_NF_CONNTRACK_TFTP is not set\n# CONFIG_NF_CONNTRACK_TIMEOUT is not set\n# CONFIG_NF_CONNTRACK_TIMESTAMP is not set\n# CONFIG_NF_CONNTRACK_ZONES is not set\n# CONFIG_NF_CT_NETLINK is not set\n# CONFIG_NF_CT_NETLINK_HELPER is not set\n# CONFIG_NF_CT_NETLINK_TIMEOUT is not set\n# CONFIG_NF_CT_PROTO_DCCP is not set\n# CONFIG_NF_CT_PROTO_GRE is not set\n# CONFIG_NF_CT_PROTO_SCTP is not set\n# CONFIG_NF_CT_PROTO_UDPLITE is not set\n# CONFIG_NF_DEFRAG_IPV4 is not set\n# CONFIG_NF_DUP_IPV4 is not set\n# CONFIG_NF_DUP_IPV6 is not set\n# CONFIG_NF_FLOW_TABLE is not set\n# CONFIG_NF_LOG_ARP is not set\n# CONFIG_NF_LOG_BRIDGE is not set\n# CONFIG_NF_LOG_IPV4 is not set\n# CONFIG_NF_LOG_NETDEV is not set\n# CONFIG_NF_LOG_SYSLOG is not set\n# CONFIG_NF_NAT is not set\n# CONFIG_NF_NAT_AMANDA is not set\n# CONFIG_NF_NAT_FTP is not set\n# CONFIG_NF_NAT_H323 is not set\n# CONFIG_NF_NAT_IPV6 is not set\n# CONFIG_NF_NAT_IRC is not set\nCONFIG_NF_NAT_MASQUERADE_IPV4=y\nCONFIG_NF_NAT_MASQUERADE_IPV6=y\n# CONFIG_NF_NAT_NEEDED is not set\n# CONFIG_NF_NAT_PPTP is not set\n# CONFIG_NF_NAT_PROTO_GRE is not set\n# CONFIG_NF_NAT_SIP is not set\n# CONFIG_NF_NAT_SNMP_BASIC is not set\n# CONFIG_NF_NAT_TFTP is not set\n# CONFIG_NF_REJECT_IPV4 is not set\n# CONFIG_NF_REJECT_IPV6 is not set\n# CONFIG_NF_SOCKET_IPV4 is not set\n# CONFIG_NF_SOCKET_IPV6 is not set\n# CONFIG_NF_TABLES is not set\nCONFIG_NF_TABLES_ARP=y\nCONFIG_NF_TABLES_BRIDGE=y\nCONFIG_NF_TABLES_INET=y\nCONFIG_NF_TABLES_IPV4=y\nCONFIG_NF_TABLES_IPV6=y\nCONFIG_NF_TABLES_NETDEV=y\n# CONFIG_NF_TABLES_SET is not set\n# CONFIG_NF_TPROXY_IPV4 is not set\n# CONFIG_NF_TPROXY_IPV6 is not set\n# CONFIG_NI65 is not set\n# CONFIG_NI903X_WDT is not set\n# CONFIG_NIC7018_WDT is not set\n# CONFIG_NILFS2_FS is not set\n# CONFIG_NIU is not set\n# CONFIG_NI_XGE_MANAGEMENT_ENET is not set\nCONFIG_NLATTR=y\n# CONFIG_NLMON is not set\n# CONFIG_NLM_XLP_BOARD is not set\n# CONFIG_NLM_XLR_BOARD is not set\n# CONFIG_NLS is not set\n# CONFIG_NLS_ASCII is not set\n# CONFIG_NLS_CODEPAGE_1250 is not set\n# CONFIG_NLS_CODEPAGE_1251 is not set\n# CONFIG_NLS_CODEPAGE_437 is not set\n# CONFIG_NLS_CODEPAGE_737 is not set\n# CONFIG_NLS_CODEPAGE_775 is not set\n# CONFIG_NLS_CODEPAGE_850 is not set\n# CONFIG_NLS_CODEPAGE_852 is not set\n# CONFIG_NLS_CODEPAGE_855 is not set\n# CONFIG_NLS_CODEPAGE_857 is not set\n# CONFIG_NLS_CODEPAGE_860 is not set\n# CONFIG_NLS_CODEPAGE_861 is not set\n# CONFIG_NLS_CODEPAGE_862 is not set\n# CONFIG_NLS_CODEPAGE_863 is not set\n# CONFIG_NLS_CODEPAGE_864 is not set\n# CONFIG_NLS_CODEPAGE_865 is not set\n# CONFIG_NLS_CODEPAGE_866 is not set\n# CONFIG_NLS_CODEPAGE_869 is not set\n# CONFIG_NLS_CODEPAGE_874 is not set\n# CONFIG_NLS_CODEPAGE_932 is not set\n# CONFIG_NLS_CODEPAGE_936 is not set\n# CONFIG_NLS_CODEPAGE_949 is not set\n# CONFIG_NLS_CODEPAGE_950 is not set\nCONFIG_NLS_DEFAULT=\"iso8859-1\"\n# CONFIG_NLS_ISO8859_1 is not set\n# CONFIG_NLS_ISO8859_13 is not set\n# CONFIG_NLS_ISO8859_14 is not set\n# CONFIG_NLS_ISO8859_15 is not set\n# CONFIG_NLS_ISO8859_2 is not set\n# CONFIG_NLS_ISO8859_3 is not set\n# CONFIG_NLS_ISO8859_4 is not set\n# CONFIG_NLS_ISO8859_5 is not set\n# CONFIG_NLS_ISO8859_6 is not set\n# CONFIG_NLS_ISO8859_7 is not set\n# CONFIG_NLS_ISO8859_8 is not set\n# CONFIG_NLS_ISO8859_9 is not set\n# CONFIG_NLS_KOI8_R is not set\n# CONFIG_NLS_KOI8_U is not set\n# CONFIG_NLS_MAC_CELTIC is not set\n# CONFIG_NLS_MAC_CENTEURO is not set\n# CONFIG_NLS_MAC_CROATIAN is not set\n# CONFIG_NLS_MAC_CYRILLIC is not set\n# CONFIG_NLS_MAC_GAELIC is not set\n# CONFIG_NLS_MAC_GREEK is not set\n# CONFIG_NLS_MAC_ICELAND is not set\n# CONFIG_NLS_MAC_INUIT is not set\n# CONFIG_NLS_MAC_ROMAN is not set\n# CONFIG_NLS_MAC_ROMANIAN is not set\n# CONFIG_NLS_MAC_TURKISH is not set\n# CONFIG_NLS_UTF8 is not set\nCONFIG_NMI_LOG_BUF_SHIFT=13\n# CONFIG_NOA1305 is not set\n# CONFIG_NOP_USB_XCEIV is not set\n# CONFIG_NORTEL_HERMES is not set\n# CONFIG_NOTIFIER_ERROR_INJECTION is not set\n# CONFIG_NOUVEAU_LEGACY_CTX_SUPPORT is not set\n# CONFIG_NOZOMI is not set\n# CONFIG_NO_BOOTMEM is not set\n# CONFIG_NO_HZ is not set\n# CONFIG_NO_HZ_FULL is not set\n# CONFIG_NO_HZ_IDLE is not set\n# CONFIG_NS83820 is not set\n# CONFIG_NTB is not set\n# CONFIG_NTFS3_64BIT_CLUSTER is not set\n# CONFIG_NTFS3_FS is not set\n# CONFIG_NTFS3_FS_POSIX_ACL is not set\n# CONFIG_NTFS3_LZX_XPRESS is not set\n# CONFIG_NTFS_DEBUG is not set\n# CONFIG_NTFS_FS is not set\n# CONFIG_NTFS_RW is not set\n# CONFIG_NTP_PPS is not set\n# CONFIG_NULL_TTY is not set\n# CONFIG_NUMA is not set\n# CONFIG_NVIDIA_CARMEL_CNP_ERRATUM is not set\n# CONFIG_NVM is not set\n# CONFIG_NVMEM is not set\n# CONFIG_NVMEM_BCM_OCOTP is not set\n# CONFIG_NVMEM_IMX_OCOTP is not set\n# CONFIG_NVMEM_REBOOT_MODE is not set\n# CONFIG_NVMEM_RMEM is not set\n# CONFIG_NVMEM_SYSFS is not set\n# CONFIG_NVME_FC is not set\n# CONFIG_NVME_TARGET is not set\n# CONFIG_NVME_TCP is not set\n# CONFIG_NVRAM is not set\n# CONFIG_NV_TCO is not set\n# CONFIG_NXP_C45_TJA11XX_PHY is not set\n# CONFIG_NXP_STB220 is not set\n# CONFIG_NXP_STB225 is not set\n# CONFIG_NXP_TJA11XX_PHY is not set\n# CONFIG_N_GSM is not set\n# CONFIG_OABI_COMPAT is not set\n# CONFIG_OBS600 is not set\n# CONFIG_OCFS2_FS is not set\n# CONFIG_OCTEONTX2_AF is not set\n# CONFIG_OCTEONTX2_PF is not set\n# CONFIG_OF_OVERLAY is not set\nCONFIG_OF_RESERVED_MEM=y\n# CONFIG_OF_UNITTEST is not set\n# CONFIG_OID_REGISTRY is not set\n# CONFIG_OMAP2_DSS_DEBUG is not set\n# CONFIG_OMAP2_DSS_DEBUGFS is not set\n# CONFIG_OMAP2_DSS_SDI is not set\n# CONFIG_OMAP_OCP2SCP is not set\n# CONFIG_OMAP_USB2 is not set\n# CONFIG_OMFS_FS is not set\n# CONFIG_OPENVSWITCH is not set\n# CONFIG_OPROFILE is not set\n# CONFIG_OPROFILE_EVENT_MULTIPLEX is not set\n# CONFIG_OPT3001 is not set\nCONFIG_OPTIMIZE_INLINING=y\n# CONFIG_ORANGEFS_FS is not set\n# CONFIG_ORION_WATCHDOG is not set\n# CONFIG_OSF_PARTITION is not set\n# CONFIG_OSNOISE_TRACER is not set\nCONFIG_OVERLAY_FS=y\n# CONFIG_OVERLAY_FS_INDEX is not set\n# CONFIG_OVERLAY_FS_METACOPY is not set\nCONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y\n# CONFIG_OVERLAY_FS_REDIRECT_DIR is not set\nCONFIG_OVERLAY_FS_XINO_AUTO=y\n# CONFIG_OWL_LOADER is not set\n# CONFIG_P54_COMMON is not set\n# CONFIG_PA12203001 is not set\nCONFIG_PACKET=y\n# CONFIG_PACKET_DIAG is not set\n# CONFIG_PACKING is not set\n# CONFIG_PAGE_EXTENSION is not set\n# CONFIG_PAGE_OWNER is not set\n# CONFIG_PAGE_POISONING is not set\n# CONFIG_PAGE_REPORTING is not set\n# CONFIG_PAGE_SIZE_16KB is not set\n# CONFIG_PAGE_SIZE_32KB is not set\nCONFIG_PAGE_SIZE_4KB=y\n# CONFIG_PAGE_SIZE_64KB is not set\n# CONFIG_PAGE_SIZE_8KB is not set\n# CONFIG_PALMAS_GPADC is not set\n# CONFIG_PANASONIC_LAPTOP is not set\n# CONFIG_PANEL is not set\nCONFIG_PANIC_ON_OOPS=y\nCONFIG_PANIC_ON_OOPS_VALUE=1\nCONFIG_PANIC_TIMEOUT=1\n# CONFIG_PANTHERLORD_FF is not set\n# CONFIG_PARAVIRT is not set\n# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set\n# CONFIG_PARPORT is not set\n# CONFIG_PARPORT_1284 is not set\n# CONFIG_PARPORT_AX88796 is not set\n# CONFIG_PARPORT_GSC is not set\n# CONFIG_PARPORT_PC is not set\nCONFIG_PARTITION_ADVANCED=y\n# CONFIG_PATA_ALI is not set\n# CONFIG_PATA_AMD is not set\n# CONFIG_PATA_ARASAN_CF is not set\n# CONFIG_PATA_ARTOP is not set\n# CONFIG_PATA_ATIIXP is not set\n# CONFIG_PATA_ATP867X is not set\n# CONFIG_PATA_CMD640_PCI is not set\n# CONFIG_PATA_CMD64X is not set\n# CONFIG_PATA_CS5520 is not set\n# CONFIG_PATA_CS5530 is not set\n# CONFIG_PATA_CS5535 is not set\n# CONFIG_PATA_CS5536 is not set\n# CONFIG_PATA_CYPRESS is not set\n# CONFIG_PATA_EFAR is not set\n# CONFIG_PATA_HPT366 is not set\n# CONFIG_PATA_HPT37X is not set\n# CONFIG_PATA_HPT3X2N is not set\n# CONFIG_PATA_HPT3X3 is not set\n# CONFIG_PATA_IMX is not set\n# CONFIG_PATA_ISAPNP is not set\n# CONFIG_PATA_IT8213 is not set\n# CONFIG_PATA_IT821X is not set\n# CONFIG_PATA_JMICRON is not set\n# CONFIG_PATA_LEGACY is not set\n# CONFIG_PATA_MARVELL is not set\n# CONFIG_PATA_MPIIX is not set\n# CONFIG_PATA_NETCELL is not set\n# CONFIG_PATA_NINJA32 is not set\n# CONFIG_PATA_NS87410 is not set\n# CONFIG_PATA_NS87415 is not set\n# CONFIG_PATA_OCTEON_CF is not set\n# CONFIG_PATA_OF_PLATFORM is not set\n# CONFIG_PATA_OLDPIIX is not set\n# CONFIG_PATA_OPTI is not set\n# CONFIG_PATA_OPTIDMA is not set\n# CONFIG_PATA_PCMCIA is not set\n# CONFIG_PATA_PDC2027X is not set\n# CONFIG_PATA_PDC_OLD is not set\n# CONFIG_PATA_PLATFORM is not set\n# CONFIG_PATA_QDI is not set\n# CONFIG_PATA_RADISYS is not set\n# CONFIG_PATA_RDC is not set\n# CONFIG_PATA_RZ1000 is not set\n# CONFIG_PATA_SC1200 is not set\n# CONFIG_PATA_SCH is not set\n# CONFIG_PATA_SERVERWORKS is not set\n# CONFIG_PATA_SIL680 is not set\n# CONFIG_PATA_SIS is not set\n# CONFIG_PATA_TOSHIBA is not set\n# CONFIG_PATA_TRIFLEX is not set\n# CONFIG_PATA_VIA is not set\n# CONFIG_PATA_WINBOND is not set\n# CONFIG_PATA_WINBOND_VLB is not set\n# CONFIG_PC104 is not set\n# CONFIG_PC300TOO is not set\n# CONFIG_PCCARD is not set\n# CONFIG_PCH_DMA is not set\n# CONFIG_PCH_GBE is not set\n# CONFIG_PCH_PHUB is not set\n# CONFIG_PCI is not set\n# CONFIG_PCI200SYN is not set\n# CONFIG_PCIEAER is not set\n# CONFIG_PCIEAER_INJECT is not set\n# CONFIG_PCIEASPM is not set\n# CONFIG_PCIEPORTBUS is not set\n# CONFIG_PCIE_AL is not set\n# CONFIG_PCIE_ALTERA is not set\n# CONFIG_PCIE_ARMADA_8K is not set\nCONFIG_PCIE_BUS_DEFAULT=y\n# CONFIG_PCIE_BUS_PEER2PEER is not set\n# CONFIG_PCIE_BUS_PERFORMANCE is not set\n# CONFIG_PCIE_BUS_SAFE is not set\n# CONFIG_PCIE_BUS_TUNE_OFF is not set\n# CONFIG_PCIE_BW is not set\n# CONFIG_PCIE_CADENCE_HOST is not set\n# CONFIG_PCIE_CADENCE_PLAT_HOST is not set\n# CONFIG_PCIE_DPC is not set\n# CONFIG_PCIE_DW_PLAT is not set\n# CONFIG_PCIE_DW_PLAT_HOST is not set\n# CONFIG_PCIE_ECRC is not set\n# CONFIG_PCIE_IPROC is not set\n# CONFIG_PCIE_KIRIN is not set\n# CONFIG_PCIE_LAYERSCAPE_GEN4 is not set\n# CONFIG_PCIE_MEDIATEK_GEN3 is not set\n# CONFIG_PCIE_MICROCHIP_HOST is not set\n# CONFIG_PCIE_PTM is not set\n# CONFIG_PCIE_XILINX is not set\n# CONFIG_PCIPCWATCHDOG is not set\n# CONFIG_PCI_ATMEL is not set\n# CONFIG_PCI_CNB20LE_QUIRK is not set\n# CONFIG_PCI_DEBUG is not set\n# CONFIG_PCI_DISABLE_COMMON_QUIRKS is not set\n# CONFIG_PCI_ENDPOINT is not set\n# CONFIG_PCI_ENDPOINT_TEST is not set\n# CONFIG_PCI_FTPCI100 is not set\n# CONFIG_PCI_HERMES is not set\n# CONFIG_PCI_HISI is not set\n# CONFIG_PCI_HOST_GENERIC is not set\n# CONFIG_PCI_HOST_THUNDER_ECAM is not set\n# CONFIG_PCI_HOST_THUNDER_PEM is not set\n# CONFIG_PCI_IOV is not set\n# CONFIG_PCI_J721E_HOST is not set\n# CONFIG_PCI_LAYERSCAPE is not set\n# CONFIG_PCI_MESON is not set\n# CONFIG_PCI_MSI is not set\n# CONFIG_PCI_PASID is not set\n# CONFIG_PCI_PF_STUB is not set\n# CONFIG_PCI_PRI is not set\nCONFIG_PCI_QUIRKS=y\n# CONFIG_PCI_REALLOC_ENABLE_AUTO is not set\n# CONFIG_PCI_STUB is not set\n# CONFIG_PCI_SW_SWITCHTEC is not set\nCONFIG_PCI_SYSCALL=y\n# CONFIG_PCI_V3_SEMI is not set\n# CONFIG_PCI_XGENE is not set\n# CONFIG_PCMCIA is not set\n# CONFIG_PCMCIA_3C574 is not set\n# CONFIG_PCMCIA_3C589 is not set\n# CONFIG_PCMCIA_AHA152X is not set\n# CONFIG_PCMCIA_ATMEL is not set\n# CONFIG_PCMCIA_AXNET is not set\n# CONFIG_PCMCIA_DEBUG is not set\n# CONFIG_PCMCIA_FDOMAIN is not set\n# CONFIG_PCMCIA_FMVJ18X is not set\n# CONFIG_PCMCIA_HERMES is not set\n# CONFIG_PCMCIA_LOAD_CIS is not set\n# CONFIG_PCMCIA_NINJA_SCSI is not set\n# CONFIG_PCMCIA_NMCLAN is not set\n# CONFIG_PCMCIA_PCNET is not set\n# CONFIG_PCMCIA_QLOGIC is not set\n# CONFIG_PCMCIA_RAYCS is not set\n# CONFIG_PCMCIA_SMC91C92 is not set\n# CONFIG_PCMCIA_SPECTRUM is not set\n# CONFIG_PCMCIA_SYM53C500 is not set\n# CONFIG_PCMCIA_WL3501 is not set\n# CONFIG_PCMCIA_XIRC2PS is not set\n# CONFIG_PCMCIA_XIRCOM is not set\n# CONFIG_PCNET32 is not set\n# CONFIG_PCPU_DEV_REFCNT is not set\n# CONFIG_PCSPKR_PLATFORM is not set\n# CONFIG_PCS_XPCS is not set\n# CONFIG_PD6729 is not set\n# CONFIG_PDA_POWER is not set\n# CONFIG_PDC_ADMA is not set\n# CONFIG_PERCPU_STATS is not set\n# CONFIG_PERCPU_TEST is not set\n# CONFIG_PERF_EVENTS is not set\n# CONFIG_PERF_EVENTS_AMD_POWER is not set\n# CONFIG_PERSISTENT_KEYRINGS is not set\n# CONFIG_PHANTOM is not set\n# CONFIG_PHONET is not set\n# CONFIG_PHYLIB is not set\n# CONFIG_PHYS_ADDR_T_64BIT is not set\n# CONFIG_PHY_CADENCE_DP is not set\n# CONFIG_PHY_CADENCE_DPHY is not set\n# CONFIG_PHY_CADENCE_SALVO is not set\n# CONFIG_PHY_CADENCE_SIERRA is not set\n# CONFIG_PHY_CADENCE_TORRENT is not set\n# CONFIG_PHY_CAN_TRANSCEIVER is not set\n# CONFIG_PHY_CPCAP_USB is not set\n# CONFIG_PHY_EXYNOS_DP_VIDEO is not set\n# CONFIG_PHY_EXYNOS_MIPI_VIDEO is not set\n# CONFIG_PHY_FSL_IMX8MQ_USB is not set\n# CONFIG_PHY_INGENIC_USB is not set\n# CONFIG_PHY_INTEL_KEEMBAY_EMMC is not set\n# CONFIG_PHY_MAPPHONE_MDM6600 is not set\n# CONFIG_PHY_MIXEL_MIPI_DPHY is not set\n# CONFIG_PHY_MTK_HDMI is not set\n# CONFIG_PHY_MTK_MIPI_DSI is not set\n# CONFIG_PHY_MVEBU_CP110_UTMI is not set\n# CONFIG_PHY_OCELOT_SERDES is not set\n# CONFIG_PHY_PISTACHIO_USB is not set\n# CONFIG_PHY_PXA_28NM_HSIC is not set\n# CONFIG_PHY_PXA_28NM_USB2 is not set\n# CONFIG_PHY_QCOM_DWC3 is not set\n# CONFIG_PHY_QCOM_USB_HS is not set\n# CONFIG_PHY_QCOM_USB_HSIC is not set\n# CONFIG_PHY_SAMSUNG_USB2 is not set\n# CONFIG_PHY_TUSB1210 is not set\n# CONFIG_PHY_XGENE is not set\n# CONFIG_PI433 is not set\n# CONFIG_PID_IN_CONTEXTIDR is not set\n# CONFIG_PID_NS is not set\nCONFIG_PINCONF=y\n# CONFIG_PINCTRL is not set\n# CONFIG_PINCTRL_AMD is not set\n# CONFIG_PINCTRL_AXP209 is not set\n# CONFIG_PINCTRL_CEDARFORK is not set\n# CONFIG_PINCTRL_EXYNOS is not set\n# CONFIG_PINCTRL_EXYNOS5440 is not set\n# CONFIG_PINCTRL_ICELAKE is not set\n# CONFIG_PINCTRL_INGENIC is not set\n# CONFIG_PINCTRL_LPASS_LPI is not set\n# CONFIG_PINCTRL_MCP23S08 is not set\n# CONFIG_PINCTRL_MDM9607 is not set\n# CONFIG_PINCTRL_MICROCHIP_SGPIO is not set\n# CONFIG_PINCTRL_MSM8953 is not set\n# CONFIG_PINCTRL_MSM8X74 is not set\n# CONFIG_PINCTRL_MT6779 is not set\n# CONFIG_PINCTRL_MT8167 is not set\n# CONFIG_PINCTRL_MT8192 is not set\n# CONFIG_PINCTRL_MT8195 is not set\n# CONFIG_PINCTRL_MT8365 is not set\n# CONFIG_PINCTRL_MTK_V2 is not set\n# CONFIG_PINCTRL_OCELOT is not set\n# CONFIG_PINCTRL_SC7280 is not set\n# CONFIG_PINCTRL_SC8180X is not set\n# CONFIG_PINCTRL_SDX55 is not set\nCONFIG_PINCTRL_SINGLE=y\n# CONFIG_PINCTRL_SM6115 is not set\n# CONFIG_PINCTRL_SM6125 is not set\n# CONFIG_PINCTRL_SM8350 is not set\n# CONFIG_PINCTRL_STMFX is not set\n# CONFIG_PINCTRL_SX150X is not set\n# CONFIG_PING is not set\nCONFIG_PINMUX=y\n# CONFIG_PKCS7_MESSAGE_PARSER is not set\n# CONFIG_PL310_ERRATA_588369 is not set\n# CONFIG_PL310_ERRATA_727915 is not set\n# CONFIG_PL310_ERRATA_753970 is not set\n# CONFIG_PL310_ERRATA_769419 is not set\n# CONFIG_PL320_MBOX is not set\n# CONFIG_PL330_DMA is not set\n# CONFIG_PLATFORM_MHU is not set\n# CONFIG_PLAT_SPEAR is not set\n# CONFIG_PLIP is not set\n# CONFIG_PLX_DMA is not set\n# CONFIG_PLX_HERMES is not set\n# CONFIG_PM is not set\n# CONFIG_PMBUS is not set\n# CONFIG_PMC_MSP is not set\n# CONFIG_PMIC_ADP5520 is not set\n# CONFIG_PMIC_DA903X is not set\n# CONFIG_PMS7003 is not set\n# CONFIG_PM_AUTOSLEEP is not set\n# CONFIG_PM_DEBUG is not set\n# CONFIG_PM_DEVFREQ is not set\n# CONFIG_PM_WAKELOCKS is not set\n# CONFIG_POSIX_MQUEUE is not set\nCONFIG_POSIX_TIMERS=y\n# CONFIG_POWERCAP is not set\n# CONFIG_POWER_AVS is not set\n# CONFIG_POWER_RESET is not set\n# CONFIG_POWER_RESET_BRCMKONA is not set\n# CONFIG_POWER_RESET_BRCMSTB is not set\n# CONFIG_POWER_RESET_GPIO is not set\n# CONFIG_POWER_RESET_GPIO_RESTART is not set\n# CONFIG_POWER_RESET_LINKSTATION is not set\n# CONFIG_POWER_RESET_LTC2952 is not set\n# CONFIG_POWER_RESET_PIIX4_POWEROFF is not set\n# CONFIG_POWER_RESET_QNAP is not set\n# CONFIG_POWER_RESET_REGULATOR is not set\n# CONFIG_POWER_RESET_RESTART is not set\n# CONFIG_POWER_RESET_SYSCON is not set\n# CONFIG_POWER_RESET_SYSCON_POWEROFF is not set\n# CONFIG_POWER_RESET_VERSATILE is not set\n# CONFIG_POWER_RESET_XGENE is not set\n# CONFIG_POWER_SUPPLY is not set\n# CONFIG_POWER_SUPPLY_DEBUG is not set\n# CONFIG_POWER_SUPPLY_HWMON is not set\n# CONFIG_PPC4xx_GPIO is not set\n# CONFIG_PPC_16K_PAGES is not set\n# CONFIG_PPC_256K_PAGES is not set\nCONFIG_PPC_4K_PAGES=y\n# CONFIG_PPC_64K_PAGES is not set\n# CONFIG_PPC_DISABLE_WERROR is not set\n# CONFIG_PPC_EMULATED_STATS is not set\n# CONFIG_PPC_EPAPR_HV_BYTECHAN is not set\n# CONFIG_PPP is not set\n# CONFIG_PPPOATM is not set\n# CONFIG_PPPOE is not set\n# CONFIG_PPPOL2TP is not set\n# CONFIG_PPP_ASYNC is not set\n# CONFIG_PPP_BSDCOMP is not set\n# CONFIG_PPP_DEFLATE is not set\nCONFIG_PPP_FILTER=y\n# CONFIG_PPP_MPPE is not set\nCONFIG_PPP_MULTILINK=y\n# CONFIG_PPP_SYNC_TTY is not set\n# CONFIG_PPS is not set\n# CONFIG_PPS_CLIENT_GPIO is not set\n# CONFIG_PPS_CLIENT_KTIMER is not set\n# CONFIG_PPS_CLIENT_LDISC is not set\n# CONFIG_PPS_CLIENT_PARPORT is not set\n# CONFIG_PPS_DEBUG is not set\n# CONFIG_PPTP is not set\n# CONFIG_PREEMPT is not set\n# CONFIG_PREEMPTIRQ_DELAY_TEST is not set\n# CONFIG_PREEMPTIRQ_EVENTS is not set\nCONFIG_PREEMPT_NONE=y\n# CONFIG_PREEMPT_TRACER is not set\n# CONFIG_PREEMPT_VOLUNTARY is not set\n# CONFIG_PRESTERA is not set\nCONFIG_PREVENT_FIRMWARE_BUILD=y\n# CONFIG_PRIME_NUMBERS is not set\nCONFIG_PRINTK=y\n# CONFIG_PRINTK_CALLER is not set\n# CONFIG_PRINTK_INDEX is not set\nCONFIG_PRINTK_NMI=y\nCONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13\n# CONFIG_PRINTK_TIME is not set\nCONFIG_PRINT_STACK_DEPTH=64\n# CONFIG_PRISM2_USB is not set\n# CONFIG_PRISM54 is not set\n# CONFIG_PROC_CHILDREN is not set\nCONFIG_PROC_FS=y\n# CONFIG_PROC_KCORE is not set\n# CONFIG_PROC_PAGE_MONITOR is not set\n# CONFIG_PROC_STRIPPED is not set\nCONFIG_PROC_SYSCTL=y\n# CONFIG_PROC_VMCORE_DEVICE_DUMP is not set\n# CONFIG_PROFILE_ALL_BRANCHES is not set\n# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set\n# CONFIG_PROFILING is not set\n# CONFIG_PROVE_LOCKING is not set\n# CONFIG_PROVE_RAW_LOCK_NESTING is not set\n# CONFIG_PROVE_RCU is not set\n# CONFIG_PROVE_RCU_LIST is not set\n# CONFIG_PROVE_RCU_REPEATEDLY is not set\n# CONFIG_PSAMPLE is not set\n# CONFIG_PSB6970_PHY is not set\n# CONFIG_PSI is not set\n# CONFIG_PSTORE is not set\n# CONFIG_PSTORE_842_COMPRESS is not set\n# CONFIG_PSTORE_BLK is not set\n# CONFIG_PSTORE_COMPRESS is not set\n# CONFIG_PSTORE_CONSOLE is not set\nCONFIG_PSTORE_DEFAULT_KMSG_BYTES=10240\n# CONFIG_PSTORE_DEFLATE_COMPRESS is not set\n# CONFIG_PSTORE_DEFLATE_COMPRESS_DEFAULT is not set\n# CONFIG_PSTORE_FTRACE is not set\n# CONFIG_PSTORE_LZ4HC_COMPRESS is not set\n# CONFIG_PSTORE_LZ4_COMPRESS is not set\n# CONFIG_PSTORE_LZO_COMPRESS is not set\n# CONFIG_PSTORE_PMSG is not set\n# CONFIG_PSTORE_RAM is not set\n# CONFIG_PSTORE_ZSTD_COMPRESS is not set\n# CONFIG_PTDUMP_DEBUGFS is not set\n# CONFIG_PTP_1588_CLOCK is not set\n# CONFIG_PTP_1588_CLOCK_IDT82P33 is not set\n# CONFIG_PTP_1588_CLOCK_IDTCM is not set\n# CONFIG_PTP_1588_CLOCK_IXP46X is not set\n# CONFIG_PTP_1588_CLOCK_KVM is not set\n# CONFIG_PTP_1588_CLOCK_OCP is not set\n# CONFIG_PTP_1588_CLOCK_PCH is not set\n# CONFIG_PTP_1588_CLOCK_VMW is not set\n# CONFIG_PUBLIC_KEY_ALGO_RSA is not set\n# CONFIG_PVPANIC is not set\n# CONFIG_PWM is not set\n# CONFIG_PWM_ATMEL_TCB is not set\n# CONFIG_PWM_DEBUG is not set\n# CONFIG_PWM_DWC is not set\n# CONFIG_PWM_FSL_FTM is not set\n# CONFIG_PWM_JZ4740 is not set\n# CONFIG_PWM_PCA9685 is not set\nCONFIG_PWRSEQ_EMMC=y\n# CONFIG_PWRSEQ_SD8787 is not set\nCONFIG_PWRSEQ_SIMPLE=y\n# CONFIG_QCA7000 is not set\n# CONFIG_QCA7000_SPI is not set\n# CONFIG_QCA7000_UART is not set\n# CONFIG_QCOM_A7PLL is not set\n# CONFIG_QCOM_EMAC is not set\n# CONFIG_QCOM_FALKOR_ERRATUM_1003 is not set\n# CONFIG_QCOM_FALKOR_ERRATUM_1009 is not set\n# CONFIG_QCOM_FALKOR_ERRATUM_E1041 is not set\n# CONFIG_QCOM_GPI_DMA is not set\n# CONFIG_QCOM_HIDMA is not set\n# CONFIG_QCOM_HIDMA_MGMT is not set\n# CONFIG_QCOM_LMH is not set\n# CONFIG_QCOM_QDF2400_ERRATUM_0065 is not set\n# CONFIG_QCOM_SPMI_ADC5 is not set\n# CONFIG_QCOM_SPMI_ADC_TM5 is not set\n# CONFIG_QCOM_SPMI_IADC is not set\n# CONFIG_QCOM_SPMI_TEMP_ALARM is not set\n# CONFIG_QCOM_SPMI_VADC is not set\n# CONFIG_QED is not set\n# CONFIG_QFMT_V1 is not set\n# CONFIG_QLA3XXX is not set\n# CONFIG_QLCNIC is not set\n# CONFIG_QLGE is not set\n# CONFIG_QNX4FS_FS is not set\n# CONFIG_QNX6FS_FS is not set\n# CONFIG_QORIQ_CPUFREQ is not set\n# CONFIG_QORIQ_THERMAL is not set\n# CONFIG_QRTR is not set\n# CONFIG_QRTR_MHI is not set\n# CONFIG_QRTR_TUN is not set\n# CONFIG_QSEMI_PHY is not set\n# CONFIG_QUEUED_LOCK_STAT is not set\n# CONFIG_QUICC_ENGINE is not set\n# CONFIG_QUOTA is not set\n# CONFIG_QUOTACTL is not set\n# CONFIG_QUOTA_DEBUG is not set\n# CONFIG_QUOTA_NETLINK_INTERFACE is not set\n# CONFIG_R3964 is not set\n# CONFIG_R6040 is not set\n# CONFIG_R8169 is not set\n# CONFIG_R8188EU is not set\n# CONFIG_R8712U is not set\n# CONFIG_R8723AU is not set\n# CONFIG_RADIO_ADAPTERS is not set\n# CONFIG_RADIO_AZTECH is not set\n# CONFIG_RADIO_CADET is not set\n# CONFIG_RADIO_GEMTEK is not set\n# CONFIG_RADIO_MAXIRADIO is not set\n# CONFIG_RADIO_RTRACK is not set\n# CONFIG_RADIO_RTRACK2 is not set\n# CONFIG_RADIO_SF16FMI is not set\n# CONFIG_RADIO_SF16FMR2 is not set\n# CONFIG_RADIO_TERRATEC is not set\n# CONFIG_RADIO_TRUST is not set\n# CONFIG_RADIO_TYPHOON is not set\n# CONFIG_RADIO_ZOLTRIX is not set\n# CONFIG_RAID6_PQ_BENCHMARK is not set\n# CONFIG_RAID_ATTRS is not set\n# CONFIG_RALINK is not set\n# CONFIG_RANDOM32_SELFTEST is not set\n# CONFIG_RANDOMIZE_BASE is not set\n# CONFIG_RANDOMIZE_KSTACK_OFFSET_DEFAULT is not set\n# CONFIG_RANDOM_TRUST_BOOTLOADER is not set\n# CONFIG_RANDOM_TRUST_CPU is not set\n# CONFIG_RAPIDIO is not set\n# CONFIG_RAS is not set\n# CONFIG_RAW_DRIVER is not set\n# CONFIG_RBTREE_TEST is not set\n# CONFIG_RCU_BOOST is not set\nCONFIG_RCU_CPU_STALL_TIMEOUT=60\n# CONFIG_RCU_EQS_DEBUG is not set\n# CONFIG_RCU_EXPEDITE_BOOT is not set\n# CONFIG_RCU_EXPERT is not set\nCONFIG_RCU_KTHREAD_PRIO=0\nCONFIG_RCU_NEED_SEGCBLIST=y\n# CONFIG_RCU_PERF_TEST is not set\n# CONFIG_RCU_REF_SCALE_TEST is not set\n# CONFIG_RCU_SCALE_TEST is not set\nCONFIG_RCU_STALL_COMMON=y\n# CONFIG_RCU_STRICT_GRACE_PERIOD is not set\n# CONFIG_RCU_TORTURE_TEST is not set\nCONFIG_RCU_TORTURE_TEST_SLOW_INIT_DELAY=3\n# CONFIG_RCU_TRACE is not set\n# CONFIG_RC_ATI_REMOTE is not set\n# CONFIG_RC_CORE is not set\n# CONFIG_RC_DECODERS is not set\n# CONFIG_RC_LOOPBACK is not set\n# CONFIG_RC_MAP is not set\n# CONFIG_RDS is not set\n# CONFIG_RD_BZIP2 is not set\n# CONFIG_RD_GZIP is not set\n# CONFIG_RD_LZ4 is not set\n# CONFIG_RD_LZMA is not set\n# CONFIG_RD_LZO is not set\n# CONFIG_RD_XZ is not set\n# CONFIG_RD_ZSTD is not set\n# CONFIG_READABLE_ASM is not set\n# CONFIG_READ_ONLY_THP_FOR_FS is not set\n# CONFIG_REALTEK_PHY is not set\n# CONFIG_REDWOOD is not set\n# CONFIG_REED_SOLOMON is not set\n# CONFIG_REED_SOLOMON_DEC8 is not set\n# CONFIG_REED_SOLOMON_ENC8 is not set\n# CONFIG_REED_SOLOMON_TEST is not set\n# CONFIG_REGMAP is not set\n# CONFIG_REGMAP_I2C is not set\n# CONFIG_REGMAP_MMIO is not set\n# CONFIG_REGMAP_SPI is not set\n# CONFIG_REGULATOR is not set\n# CONFIG_REGULATOR_88PG86X is not set\n# CONFIG_REGULATOR_ACT8865 is not set\n# CONFIG_REGULATOR_AD5398 is not set\n# CONFIG_REGULATOR_ANATOP is not set\n# CONFIG_REGULATOR_DA9121 is not set\n# CONFIG_REGULATOR_DA9210 is not set\n# CONFIG_REGULATOR_DA9211 is not set\n# CONFIG_REGULATOR_DEBUG is not set\n# CONFIG_REGULATOR_FAN53555 is not set\n# CONFIG_REGULATOR_FAN53880 is not set\n# CONFIG_REGULATOR_FIXED_VOLTAGE is not set\n# CONFIG_REGULATOR_GPIO is not set\n# CONFIG_REGULATOR_ISL6271A is not set\n# CONFIG_REGULATOR_ISL9305 is not set\n# CONFIG_REGULATOR_LP3971 is not set\n# CONFIG_REGULATOR_LP3972 is not set\n# CONFIG_REGULATOR_LP872X is not set\n# CONFIG_REGULATOR_LP8755 is not set\n# CONFIG_REGULATOR_LTC3589 is not set\n# CONFIG_REGULATOR_LTC3676 is not set\n# CONFIG_REGULATOR_MAX1586 is not set\n# CONFIG_REGULATOR_MAX77620 is not set\n# CONFIG_REGULATOR_MAX77826 is not set\n# CONFIG_REGULATOR_MAX8649 is not set\n# CONFIG_REGULATOR_MAX8660 is not set\n# CONFIG_REGULATOR_MAX8893 is not set\n# CONFIG_REGULATOR_MAX8952 is not set\n# CONFIG_REGULATOR_MAX8973 is not set\n# CONFIG_REGULATOR_MCP16502 is not set\n# CONFIG_REGULATOR_MP5416 is not set\n# CONFIG_REGULATOR_MP8859 is not set\n# CONFIG_REGULATOR_MP886X is not set\n# CONFIG_REGULATOR_MPQ7920 is not set\n# CONFIG_REGULATOR_MT6311 is not set\n# CONFIG_REGULATOR_MT6315 is not set\n# CONFIG_REGULATOR_MT6359 is not set\n# CONFIG_REGULATOR_PCA9450 is not set\n# CONFIG_REGULATOR_PF8X00 is not set\n# CONFIG_REGULATOR_PFUZE100 is not set\n# CONFIG_REGULATOR_PV88060 is not set\n# CONFIG_REGULATOR_PV88080 is not set\n# CONFIG_REGULATOR_PV88090 is not set\n# CONFIG_REGULATOR_PWM is not set\n# CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY is not set\n# CONFIG_REGULATOR_RT4801 is not set\n# CONFIG_REGULATOR_RT6160 is not set\n# CONFIG_REGULATOR_RT6245 is not set\n# CONFIG_REGULATOR_RTMV20 is not set\n# CONFIG_REGULATOR_RTQ2134 is not set\n# CONFIG_REGULATOR_RTQ6752 is not set\n# CONFIG_REGULATOR_SLG51000 is not set\n# CONFIG_REGULATOR_SY8106A is not set\n# CONFIG_REGULATOR_SY8824X is not set\n# CONFIG_REGULATOR_SY8827N is not set\n# CONFIG_REGULATOR_TI_ABB is not set\n# CONFIG_REGULATOR_TPS51632 is not set\n# CONFIG_REGULATOR_TPS62360 is not set\n# CONFIG_REGULATOR_TPS65023 is not set\n# CONFIG_REGULATOR_TPS6507X is not set\n# CONFIG_REGULATOR_TPS65132 is not set\n# CONFIG_REGULATOR_TPS6524X is not set\n# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set\n# CONFIG_REGULATOR_VCTRL is not set\n# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set\n# CONFIG_REISERFS_CHECK is not set\n# CONFIG_REISERFS_FS is not set\n# CONFIG_REISERFS_FS_POSIX_ACL is not set\n# CONFIG_REISERFS_FS_SECURITY is not set\nCONFIG_REISERFS_FS_XATTR=y\n# CONFIG_REISERFS_PROC_INFO is not set\n# CONFIG_RELAY is not set\n# CONFIG_RELOCATABLE is not set\n# CONFIG_REMOTEPROC is not set\n# CONFIG_RENESAS_PHY is not set\n# CONFIG_RESET_ATH79 is not set\n# CONFIG_RESET_BERLIN is not set\n# CONFIG_RESET_BRCMSTB_RESCAL is not set\n# CONFIG_RESET_CONTROLLER is not set\n# CONFIG_RESET_IMX7 is not set\n# CONFIG_RESET_INTEL_GW is not set\n# CONFIG_RESET_LANTIQ is not set\n# CONFIG_RESET_LPC18XX is not set\n# CONFIG_RESET_MESON is not set\n# CONFIG_RESET_PISTACHIO is not set\n# CONFIG_RESET_SOCFPGA is not set\n# CONFIG_RESET_STM32 is not set\n# CONFIG_RESET_SUNXI is not set\n# CONFIG_RESET_TEGRA_BPMP is not set\n# CONFIG_RESET_TI_SYSCON is not set\n# CONFIG_RESET_ZYNQ is not set\n# CONFIG_RFD77402 is not set\n# CONFIG_RFD_FTL is not set\nCONFIG_RFKILL=y\n# CONFIG_RFKILL_FULL is not set\n# CONFIG_RFKILL_GPIO is not set\n# CONFIG_RFKILL_INPUT is not set\n# CONFIG_RFKILL_LEDS is not set\n# CONFIG_RFKILL_REGULATOR is not set\n# CONFIG_RING_BUFFER_BENCHMARK is not set\n# CONFIG_RING_BUFFER_STARTUP_TEST is not set\n# CONFIG_RING_BUFFER_VALIDATE_TIME_DELTAS is not set\n# CONFIG_RMI4_CORE is not set\n# CONFIG_RMNET is not set\n# CONFIG_ROCKCHIP_PHY is not set\n# CONFIG_ROCKER is not set\n# CONFIG_ROMFS_FS is not set\n# CONFIG_ROSE is not set\n# CONFIG_RPCSEC_GSS_KRB5 is not set\n# CONFIG_RPMSG_QCOM_GLINK_RPM is not set\n# CONFIG_RPMSG_VIRTIO is not set\n# CONFIG_RPR0521 is not set\n# CONFIG_RSEQ is not set\n# CONFIG_RT2X00 is not set\n# CONFIG_RTC_CLASS is not set\n# CONFIG_RTC_DEBUG is not set\n# CONFIG_RTC_DRV_ABB5ZES3 is not set\n# CONFIG_RTC_DRV_ABEOZ9 is not set\n# CONFIG_RTC_DRV_ABX80X is not set\n# CONFIG_RTC_DRV_ARMADA38X is not set\n# CONFIG_RTC_DRV_AU1XXX is not set\n# CONFIG_RTC_DRV_BQ32K is not set\n# CONFIG_RTC_DRV_BQ4802 is not set\n# CONFIG_RTC_DRV_CADENCE is not set\nCONFIG_RTC_DRV_CMOS=y\n# CONFIG_RTC_DRV_DS1286 is not set\n# CONFIG_RTC_DRV_DS1302 is not set\n# CONFIG_RTC_DRV_DS1305 is not set\n# CONFIG_RTC_DRV_DS1307 is not set\n# CONFIG_RTC_DRV_DS1307_CENTURY is not set\n# CONFIG_RTC_DRV_DS1307_HWMON is not set\n# CONFIG_RTC_DRV_DS1343 is not set\n# CONFIG_RTC_DRV_DS1347 is not set\n# CONFIG_RTC_DRV_DS1374 is not set\n# CONFIG_RTC_DRV_DS1390 is not set\n# CONFIG_RTC_DRV_DS1511 is not set\n# CONFIG_RTC_DRV_DS1553 is not set\n# CONFIG_RTC_DRV_DS1672 is not set\n# CONFIG_RTC_DRV_DS1685_FAMILY is not set\n# CONFIG_RTC_DRV_DS1742 is not set\n# CONFIG_RTC_DRV_DS2404 is not set\n# CONFIG_RTC_DRV_DS3232 is not set\n# CONFIG_RTC_DRV_DS3234 is not set\n# CONFIG_RTC_DRV_EM3027 is not set\n# CONFIG_RTC_DRV_EP93XX is not set\n# CONFIG_RTC_DRV_FM3130 is not set\n# CONFIG_RTC_DRV_FTRTC010 is not set\n# CONFIG_RTC_DRV_GENERIC is not set\n# CONFIG_RTC_DRV_GOLDFISH is not set\n# CONFIG_RTC_DRV_HID_SENSOR_TIME is not set\n# CONFIG_RTC_DRV_HYM8563 is not set\n# CONFIG_RTC_DRV_ISL12022 is not set\n# CONFIG_RTC_DRV_ISL12026 is not set\n# CONFIG_RTC_DRV_ISL12057 is not set\n# CONFIG_RTC_DRV_ISL1208 is not set\n# CONFIG_RTC_DRV_JZ4740 is not set\n# CONFIG_RTC_DRV_M41T80 is not set\n# CONFIG_RTC_DRV_M41T93 is not set\n# CONFIG_RTC_DRV_M41T94 is not set\n# CONFIG_RTC_DRV_M48T35 is not set\n# CONFIG_RTC_DRV_M48T59 is not set\n# CONFIG_RTC_DRV_M48T86 is not set\n# CONFIG_RTC_DRV_MAX6900 is not set\n# CONFIG_RTC_DRV_MAX6902 is not set\n# CONFIG_RTC_DRV_MAX6916 is not set\n# CONFIG_RTC_DRV_MCP795 is not set\n# CONFIG_RTC_DRV_MOXART is not set\n# CONFIG_RTC_DRV_MPC5121 is not set\n# CONFIG_RTC_DRV_MSM6242 is not set\n# CONFIG_RTC_DRV_MT2712 is not set\n# CONFIG_RTC_DRV_OMAP is not set\n# CONFIG_RTC_DRV_PCF2123 is not set\n# CONFIG_RTC_DRV_PCF2127 is not set\n# CONFIG_RTC_DRV_PCF85063 is not set\n# CONFIG_RTC_DRV_PCF8523 is not set\n# CONFIG_RTC_DRV_PCF85363 is not set\n# CONFIG_RTC_DRV_PCF8563 is not set\n# CONFIG_RTC_DRV_PCF8583 is not set\n# CONFIG_RTC_DRV_PL030 is not set\n# CONFIG_RTC_DRV_PL031 is not set\n# CONFIG_RTC_DRV_PS3 is not set\n# CONFIG_RTC_DRV_PT7C4338 is not set\n# CONFIG_RTC_DRV_R7301 is not set\n# CONFIG_RTC_DRV_R9701 is not set\n# CONFIG_RTC_DRV_RP5C01 is not set\n# CONFIG_RTC_DRV_RS5C348 is not set\n# CONFIG_RTC_DRV_RS5C372 is not set\n# CONFIG_RTC_DRV_RTC7301 is not set\n# CONFIG_RTC_DRV_RV3028 is not set\n# CONFIG_RTC_DRV_RV3029C2 is not set\n# CONFIG_RTC_DRV_RV3032 is not set\n# CONFIG_RTC_DRV_RV8803 is not set\n# CONFIG_RTC_DRV_RX4581 is not set\n# CONFIG_RTC_DRV_RX6110 is not set\n# CONFIG_RTC_DRV_RX8010 is not set\n# CONFIG_RTC_DRV_RX8025 is not set\n# CONFIG_RTC_DRV_RX8581 is not set\n# CONFIG_RTC_DRV_S35390A is not set\n# CONFIG_RTC_DRV_SD3078 is not set\n# CONFIG_RTC_DRV_SNVS is not set\n# CONFIG_RTC_DRV_STK17TA8 is not set\n# CONFIG_RTC_DRV_SUN6I is not set\n# CONFIG_RTC_DRV_TEST is not set\n# CONFIG_RTC_DRV_V3020 is not set\n# CONFIG_RTC_DRV_X1205 is not set\n# CONFIG_RTC_DRV_XGENE is not set\n# CONFIG_RTC_DRV_ZYNQMP is not set\nCONFIG_RTC_HCTOSYS=y\nCONFIG_RTC_HCTOSYS_DEVICE=\"rtc0\"\nCONFIG_RTC_INTF_DEV=y\n# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set\nCONFIG_RTC_INTF_PROC=y\nCONFIG_RTC_INTF_SYSFS=y\nCONFIG_RTC_LIB=y\n# CONFIG_RTC_NVMEM is not set\nCONFIG_RTC_SYSTOHC=y\nCONFIG_RTC_SYSTOHC_DEVICE=\"rtc0\"\n# CONFIG_RTL8180 is not set\n# CONFIG_RTL8187 is not set\n# CONFIG_RTL8192E is not set\n# CONFIG_RTL8192U is not set\n# CONFIG_RTL8306_PHY is not set\n# CONFIG_RTL8366RB_PHY is not set\n# CONFIG_RTL8366S_PHY is not set\n# CONFIG_RTL8366_SMI is not set\n# CONFIG_RTL8366_SMI_DEBUG_FS is not set\n# CONFIG_RTL8367B_PHY is not set\n# CONFIG_RTL8367_PHY is not set\n# CONFIG_RTLLIB is not set\n# CONFIG_RTL_CARDS is not set\n# CONFIG_RTS5208 is not set\nCONFIG_RT_MUTEXES=y\n# CONFIG_RUNTIME_DEBUG is not set\nCONFIG_RUNTIME_TESTING_MENU=y\nCONFIG_RWSEM_GENERIC_SPINLOCK=y\nCONFIG_RXKAD=y\n# CONFIG_S2IO is not set\n# CONFIG_SAMPLES is not set\n# CONFIG_SAMSUNG_LAPTOP is not set\n# CONFIG_SATA_ACARD_AHCI is not set\n# CONFIG_SATA_AHCI is not set\n# CONFIG_SATA_AHCI_PLATFORM is not set\n# CONFIG_SATA_DWC is not set\n# CONFIG_SATA_FSL is not set\n# CONFIG_SATA_HIGHBANK is not set\n# CONFIG_SATA_HOST is not set\n# CONFIG_SATA_INIC162X is not set\nCONFIG_SATA_MOBILE_LPM_POLICY=0\n# CONFIG_SATA_MV is not set\n# CONFIG_SATA_NV is not set\n# CONFIG_SATA_PMP is not set\n# CONFIG_SATA_PROMISE is not set\n# CONFIG_SATA_QSTOR is not set\n# CONFIG_SATA_RCAR is not set\n# CONFIG_SATA_SIL is not set\n# CONFIG_SATA_SIL24 is not set\n# CONFIG_SATA_SIS is not set\n# CONFIG_SATA_SVW is not set\n# CONFIG_SATA_SX4 is not set\n# CONFIG_SATA_ULI is not set\n# CONFIG_SATA_VIA is not set\n# CONFIG_SATA_VITESSE is not set\n# CONFIG_SBC_FITPC2_WATCHDOG is not set\nCONFIG_SBITMAP=y\n# CONFIG_SC92031 is not set\n# CONFIG_SCA3000 is not set\n# CONFIG_SCA3300 is not set\n# CONFIG_SCACHE_DEBUGFS is not set\n# CONFIG_SCC is not set\n# CONFIG_SCD30_CORE is not set\n# CONFIG_SCF_TORTURE_TEST is not set\n# CONFIG_SCHEDSTATS is not set\n# CONFIG_SCHED_AUTOGROUP is not set\n# CONFIG_SCHED_DEBUG is not set\nCONFIG_SCHED_HRTICK=y\n# CONFIG_SCHED_MC is not set\nCONFIG_SCHED_OMIT_FRAME_POINTER=y\n# CONFIG_SCHED_SMT is not set\n# CONFIG_SCHED_STACK_END_CHECK is not set\n# CONFIG_SCHED_TRACER is not set\n# CONFIG_SCR24X is not set\n# CONFIG_SCSI is not set\n# CONFIG_SCSI_3W_9XXX is not set\n# CONFIG_SCSI_3W_SAS is not set\n# CONFIG_SCSI_7000FASST is not set\n# CONFIG_SCSI_AACRAID is not set\n# CONFIG_SCSI_ACARD is not set\n# CONFIG_SCSI_ADVANSYS is not set\n# CONFIG_SCSI_AHA152X is not set\n# CONFIG_SCSI_AHA1542 is not set\n# CONFIG_SCSI_AIC79XX is not set\n# CONFIG_SCSI_AIC7XXX is not set\n# CONFIG_SCSI_AIC94XX is not set\n# CONFIG_SCSI_AM53C974 is not set\n# CONFIG_SCSI_ARCMSR is not set\n# CONFIG_SCSI_BFA_FC is not set\n# CONFIG_SCSI_BNX2X_FCOE is not set\n# CONFIG_SCSI_BNX2_ISCSI is not set\n# CONFIG_SCSI_BUSLOGIC is not set\n# CONFIG_SCSI_CHELSIO_FCOE is not set\n# CONFIG_SCSI_CONSTANTS is not set\n# CONFIG_SCSI_CXGB3_ISCSI is not set\n# CONFIG_SCSI_CXGB4_ISCSI is not set\n# CONFIG_SCSI_DC395x is not set\n# CONFIG_SCSI_DEBUG is not set\n# CONFIG_SCSI_DH is not set\nCONFIG_SCSI_DMA=y\n# CONFIG_SCSI_DMX3191D is not set\n# CONFIG_SCSI_DPT_I2O is not set\n# CONFIG_SCSI_DTC3280 is not set\n# CONFIG_SCSI_EATA is not set\n# CONFIG_SCSI_ESAS2R is not set\n# CONFIG_SCSI_FC_ATTRS is not set\n# CONFIG_SCSI_FDOMAIN_PCI is not set\n# CONFIG_SCSI_FUTURE_DOMAIN is not set\n# CONFIG_SCSI_GDTH is not set\n# CONFIG_SCSI_GENERIC_NCR5380 is not set\n# CONFIG_SCSI_GENERIC_NCR5380_MMIO is not set\n# CONFIG_SCSI_HISI_SAS is not set\n# CONFIG_SCSI_HPSA is not set\n# CONFIG_SCSI_HPTIOP is not set\n# CONFIG_SCSI_IN2000 is not set\n# CONFIG_SCSI_INIA100 is not set\n# CONFIG_SCSI_INITIO is not set\n# CONFIG_SCSI_IPR is not set\n# CONFIG_SCSI_IPS is not set\n# CONFIG_SCSI_ISCI is not set\n# CONFIG_SCSI_ISCSI_ATTRS is not set\n# CONFIG_SCSI_LOGGING is not set\nCONFIG_SCSI_LOWLEVEL=y\n# CONFIG_SCSI_LOWLEVEL_PCMCIA is not set\n# CONFIG_SCSI_LPFC is not set\nCONFIG_SCSI_MOD=y\n# CONFIG_SCSI_MPI3MR is not set\n# CONFIG_SCSI_MPT2SAS is not set\n# CONFIG_SCSI_MPT3SAS is not set\n# CONFIG_SCSI_MQ_DEFAULT is not set\n# CONFIG_SCSI_MVSAS is not set\n# CONFIG_SCSI_MVSAS_DEBUG is not set\n# CONFIG_SCSI_MVUMI is not set\n# CONFIG_SCSI_MYRB is not set\n# CONFIG_SCSI_MYRS is not set\n# CONFIG_SCSI_NCR53C406A is not set\n# CONFIG_SCSI_NETLINK is not set\n# CONFIG_SCSI_NSP32 is not set\n# CONFIG_SCSI_OSD_INITIATOR is not set\n# CONFIG_SCSI_PAS16 is not set\n# CONFIG_SCSI_PM8001 is not set\n# CONFIG_SCSI_PMCRAID is not set\nCONFIG_SCSI_PROC_FS=y\n# CONFIG_SCSI_QLA_FC is not set\n# CONFIG_SCSI_QLA_ISCSI is not set\n# CONFIG_SCSI_QLOGIC_1280 is not set\n# CONFIG_SCSI_QLOGIC_FAS is not set\n# CONFIG_SCSI_SAS_ATTRS is not set\n# CONFIG_SCSI_SAS_LIBSAS is not set\n# CONFIG_SCSI_SCAN_ASYNC is not set\n# CONFIG_SCSI_SMARTPQI is not set\n# CONFIG_SCSI_SNIC is not set\n# CONFIG_SCSI_SPI_ATTRS is not set\n# CONFIG_SCSI_SRP_ATTRS is not set\n# CONFIG_SCSI_STEX is not set\n# CONFIG_SCSI_SYM53C416 is not set\n# CONFIG_SCSI_SYM53C8XX_2 is not set\n# CONFIG_SCSI_T128 is not set\n# CONFIG_SCSI_U14_34F is not set\n# CONFIG_SCSI_UFSHCD is not set\n# CONFIG_SCSI_ULTRASTOR is not set\n# CONFIG_SCSI_VIRTIO is not set\n# CONFIG_SCSI_WD719X is not set\n# CONFIG_SC_CAMCC_7180 is not set\n# CONFIG_SC_DISPCC_7280 is not set\n# CONFIG_SC_GCC_7280 is not set\n# CONFIG_SC_GCC_8180X is not set\n# CONFIG_SC_GPUCC_7280 is not set\n# CONFIG_SC_VIDEOCC_7280 is not set\n# CONFIG_SCx200_ACB is not set\n# CONFIG_SDIO_UART is not set\n# CONFIG_SDM_GPUCC_660 is not set\n# CONFIG_SDM_MMCC_660 is not set\n# CONFIG_SDR_MAX2175 is not set\n# CONFIG_SDR_PLATFORM_DRIVERS is not set\n# CONFIG_SDX_GCC_55 is not set\n# CONFIG_SD_ADC_MODULATOR is not set\n# CONFIG_SECCOMP is not set\n# CONFIG_SECCOMP_CACHE_DEBUG is not set\nCONFIG_SECTION_MISMATCH_WARN_ONLY=y\n# CONFIG_SECURITY is not set\n# CONFIG_SECURITYFS is not set\n# CONFIG_SECURITY_APPARMOR is not set\nCONFIG_SECURITY_DMESG_RESTRICT=y\n# CONFIG_SECURITY_LANDLOCK is not set\n# CONFIG_SECURITY_LOADPIN is not set\n# CONFIG_SECURITY_LOCKDOWN_LSM is not set\n# CONFIG_SECURITY_NETWORK_XFRM is not set\n# CONFIG_SECURITY_PATH is not set\n# CONFIG_SECURITY_SAFESETID is not set\n# CONFIG_SECURITY_SELINUX_AVC_STATS is not set\n# CONFIG_SECURITY_SELINUX_BOOTPARAM is not set\nCONFIG_SECURITY_SELINUX_CHECKREQPROT_VALUE=0\n# CONFIG_SECURITY_SELINUX_DEVELOP is not set\n# CONFIG_SECURITY_SELINUX_DISABLE is not set\n# CONFIG_SECURITY_SMACK is not set\n# CONFIG_SECURITY_TOMOYO is not set\n# CONFIG_SECURITY_YAMA is not set\nCONFIG_SELECT_MEMORY_MODEL=y\n# CONFIG_SENSIRION_SGP30 is not set\n# CONFIG_SENSIRION_SGP40 is not set\n# CONFIG_SENSORS_ABITUGURU is not set\n# CONFIG_SENSORS_ABITUGURU3 is not set\n# CONFIG_SENSORS_ACPI_POWER is not set\n# CONFIG_SENSORS_AD7314 is not set\n# CONFIG_SENSORS_AD7414 is not set\n# CONFIG_SENSORS_AD7418 is not set\n# CONFIG_SENSORS_ADC128D818 is not set\n# CONFIG_SENSORS_ADCXX is not set\n# CONFIG_SENSORS_ADM1021 is not set\n# CONFIG_SENSORS_ADM1025 is not set\n# CONFIG_SENSORS_ADM1026 is not set\n# CONFIG_SENSORS_ADM1029 is not set\n# CONFIG_SENSORS_ADM1031 is not set\n# CONFIG_SENSORS_ADM1177 is not set\n# CONFIG_SENSORS_ADM1266 is not set\n# CONFIG_SENSORS_ADM1275 is not set\n# CONFIG_SENSORS_ADM9240 is not set\n# CONFIG_SENSORS_ADS1015 is not set\n# CONFIG_SENSORS_ADS7828 is not set\n# CONFIG_SENSORS_ADS7871 is not set\n# CONFIG_SENSORS_ADT7310 is not set\n# CONFIG_SENSORS_ADT7410 is not set\n# CONFIG_SENSORS_ADT7411 is not set\n# CONFIG_SENSORS_ADT7462 is not set\n# CONFIG_SENSORS_ADT7470 is not set\n# CONFIG_SENSORS_ADT7475 is not set\n# CONFIG_SENSORS_AHT10 is not set\n# CONFIG_SENSORS_AMC6821 is not set\n# CONFIG_SENSORS_APDS990X is not set\n# CONFIG_SENSORS_APPLESMC is not set\n# CONFIG_SENSORS_AQUACOMPUTER_D5NEXT is not set\n# CONFIG_SENSORS_AS370 is not set\n# CONFIG_SENSORS_ASB100 is not set\n# CONFIG_SENSORS_ASC7621 is not set\n# CONFIG_SENSORS_ASPEED is not set\n# CONFIG_SENSORS_ATK0110 is not set\n# CONFIG_SENSORS_ATXP1 is not set\n# CONFIG_SENSORS_AXI_FAN_CONTROL is not set\n# CONFIG_SENSORS_BEL_PFE is not set\n# CONFIG_SENSORS_BH1770 is not set\n# CONFIG_SENSORS_BH1780 is not set\n# CONFIG_SENSORS_BPA_RS600 is not set\n# CONFIG_SENSORS_CORETEMP is not set\n# CONFIG_SENSORS_CORSAIR_CPRO is not set\n# CONFIG_SENSORS_CORSAIR_PSU is not set\n# CONFIG_SENSORS_DELL_SMM is not set\n# CONFIG_SENSORS_DME1737 is not set\n# CONFIG_SENSORS_DPS920AB is not set\n# CONFIG_SENSORS_DRIVETEMP is not set\n# CONFIG_SENSORS_DS1621 is not set\n# CONFIG_SENSORS_DS620 is not set\n# CONFIG_SENSORS_EMC1403 is not set\n# CONFIG_SENSORS_EMC2103 is not set\n# CONFIG_SENSORS_EMC6W201 is not set\n# CONFIG_SENSORS_F71805F is not set\n# CONFIG_SENSORS_F71882FG is not set\n# CONFIG_SENSORS_F75375S is not set\n# CONFIG_SENSORS_FAM15H_POWER is not set\n# CONFIG_SENSORS_FSCHMD is not set\n# CONFIG_SENSORS_FSP_3Y is not set\n# CONFIG_SENSORS_FTSTEUTATES is not set\n# CONFIG_SENSORS_G760A is not set\n# CONFIG_SENSORS_G762 is not set\n# CONFIG_SENSORS_GL518SM is not set\n# CONFIG_SENSORS_GL520SM is not set\n# CONFIG_SENSORS_GPIO_FAN is not set\n# CONFIG_SENSORS_GSC is not set\n# CONFIG_SENSORS_HDAPS is not set\n# CONFIG_SENSORS_HIH6130 is not set\n# CONFIG_SENSORS_HMC5843 is not set\n# CONFIG_SENSORS_HMC5843_I2C is not set\n# CONFIG_SENSORS_HMC5843_SPI is not set\n# CONFIG_SENSORS_HTU21 is not set\n# CONFIG_SENSORS_I5500 is not set\n# CONFIG_SENSORS_I5K_AMB is not set\n# CONFIG_SENSORS_IBM_CFFPS is not set\n# CONFIG_SENSORS_IIO_HWMON is not set\n# CONFIG_SENSORS_INA209 is not set\n# CONFIG_SENSORS_INA2XX is not set\n# CONFIG_SENSORS_INA3221 is not set\n# CONFIG_SENSORS_INSPUR_IPSPS is not set\n# CONFIG_SENSORS_IR35221 is not set\n# CONFIG_SENSORS_IR36021 is not set\n# CONFIG_SENSORS_IR38064 is not set\n# CONFIG_SENSORS_IRPS5401 is not set\n# CONFIG_SENSORS_ISL29018 is not set\n# CONFIG_SENSORS_ISL29028 is not set\n# CONFIG_SENSORS_ISL68137 is not set\n# CONFIG_SENSORS_IT87 is not set\n# CONFIG_SENSORS_JC42 is not set\n# CONFIG_SENSORS_K10TEMP is not set\n# CONFIG_SENSORS_K8TEMP is not set\n# CONFIG_SENSORS_LINEAGE is not set\n# CONFIG_SENSORS_LIS3LV02D is not set\n# CONFIG_SENSORS_LIS3_I2C is not set\n# CONFIG_SENSORS_LIS3_SPI is not set\n# CONFIG_SENSORS_LM25066 is not set\n# CONFIG_SENSORS_LM63 is not set\n# CONFIG_SENSORS_LM70 is not set\n# CONFIG_SENSORS_LM73 is not set\n# CONFIG_SENSORS_LM75 is not set\n# CONFIG_SENSORS_LM77 is not set\n# CONFIG_SENSORS_LM78 is not set\n# CONFIG_SENSORS_LM80 is not set\n# CONFIG_SENSORS_LM83 is not set\n# CONFIG_SENSORS_LM85 is not set\n# CONFIG_SENSORS_LM87 is not set\n# CONFIG_SENSORS_LM90 is not set\n# CONFIG_SENSORS_LM92 is not set\n# CONFIG_SENSORS_LM93 is not set\n# CONFIG_SENSORS_LM95234 is not set\n# CONFIG_SENSORS_LM95241 is not set\n# CONFIG_SENSORS_LM95245 is not set\n# CONFIG_SENSORS_LTC2945 is not set\n# CONFIG_SENSORS_LTC2947_I2C is not set\n# CONFIG_SENSORS_LTC2947_SPI is not set\n# CONFIG_SENSORS_LTC2978 is not set\n# CONFIG_SENSORS_LTC2990 is not set\n# CONFIG_SENSORS_LTC2992 is not set\n# CONFIG_SENSORS_LTC3815 is not set\n# CONFIG_SENSORS_LTC4151 is not set\n# CONFIG_SENSORS_LTC4215 is not set\n# CONFIG_SENSORS_LTC4222 is not set\n# CONFIG_SENSORS_LTC4245 is not set\n# CONFIG_SENSORS_LTC4260 is not set\n# CONFIG_SENSORS_LTC4261 is not set\n# CONFIG_SENSORS_LTQ_CPUTEMP is not set\n# CONFIG_SENSORS_MAX1111 is not set\n# CONFIG_SENSORS_MAX127 is not set\n# CONFIG_SENSORS_MAX15301 is not set\n# CONFIG_SENSORS_MAX16064 is not set\n# CONFIG_SENSORS_MAX16065 is not set\n# CONFIG_SENSORS_MAX1619 is not set\n# CONFIG_SENSORS_MAX16601 is not set\n# CONFIG_SENSORS_MAX1668 is not set\n# CONFIG_SENSORS_MAX197 is not set\n# CONFIG_SENSORS_MAX20730 is not set\n# CONFIG_SENSORS_MAX20751 is not set\n# CONFIG_SENSORS_MAX31722 is not set\n# CONFIG_SENSORS_MAX31730 is not set\n# CONFIG_SENSORS_MAX31785 is not set\n# CONFIG_SENSORS_MAX31790 is not set\n# CONFIG_SENSORS_MAX34440 is not set\n# CONFIG_SENSORS_MAX6621 is not set\n# CONFIG_SENSORS_MAX6639 is not set\n# CONFIG_SENSORS_MAX6642 is not set\n# CONFIG_SENSORS_MAX6650 is not set\n# CONFIG_SENSORS_MAX6697 is not set\n# CONFIG_SENSORS_MAX8688 is not set\n# CONFIG_SENSORS_MCP3021 is not set\n# CONFIG_SENSORS_MP2888 is not set\n# CONFIG_SENSORS_MP2975 is not set\n# CONFIG_SENSORS_MR75203 is not set\n# CONFIG_SENSORS_NCT6683 is not set\n# CONFIG_SENSORS_NCT6775 is not set\n# CONFIG_SENSORS_NCT7802 is not set\n# CONFIG_SENSORS_NCT7904 is not set\n# CONFIG_SENSORS_NPCM7XX is not set\n# CONFIG_SENSORS_NSA320 is not set\n# CONFIG_SENSORS_NTC_THERMISTOR is not set\n# CONFIG_SENSORS_NZXT_KRAKEN2 is not set\n# CONFIG_SENSORS_OCC_P8_I2C is not set\n# CONFIG_SENSORS_PC87360 is not set\n# CONFIG_SENSORS_PC87427 is not set\n# CONFIG_SENSORS_PCF8591 is not set\n# CONFIG_SENSORS_PIM4328 is not set\n# CONFIG_SENSORS_PM6764TR is not set\n# CONFIG_SENSORS_PMBUS is not set\n# CONFIG_SENSORS_POWR1220 is not set\n# CONFIG_SENSORS_PWM_FAN is not set\n# CONFIG_SENSORS_PXE1610 is not set\n# CONFIG_SENSORS_Q54SJ108A2 is not set\n# CONFIG_SENSORS_RM3100_I2C is not set\n# CONFIG_SENSORS_RM3100_SPI is not set\n# CONFIG_SENSORS_SBRMI is not set\n# CONFIG_SENSORS_SBTSI is not set\n# CONFIG_SENSORS_SCH5627 is not set\n# CONFIG_SENSORS_SCH5636 is not set\n# CONFIG_SENSORS_SCH56XX_COMMON is not set\n# CONFIG_SENSORS_SHT15 is not set\n# CONFIG_SENSORS_SHT21 is not set\n# CONFIG_SENSORS_SHT3x is not set\n# CONFIG_SENSORS_SHT4x is not set\n# CONFIG_SENSORS_SHTC1 is not set\n# CONFIG_SENSORS_SIS5595 is not set\n# CONFIG_SENSORS_SMM665 is not set\n# CONFIG_SENSORS_SMSC47B397 is not set\n# CONFIG_SENSORS_SMSC47M1 is not set\n# CONFIG_SENSORS_SMSC47M192 is not set\n# CONFIG_SENSORS_STPDDC60 is not set\n# CONFIG_SENSORS_STTS751 is not set\n# CONFIG_SENSORS_TC654 is not set\n# CONFIG_SENSORS_TC74 is not set\n# CONFIG_SENSORS_THMC50 is not set\n# CONFIG_SENSORS_TMP102 is not set\n# CONFIG_SENSORS_TMP103 is not set\n# CONFIG_SENSORS_TMP108 is not set\n# CONFIG_SENSORS_TMP401 is not set\n# CONFIG_SENSORS_TMP421 is not set\n# CONFIG_SENSORS_TMP513 is not set\n# CONFIG_SENSORS_TPS23861 is not set\n# CONFIG_SENSORS_TPS40422 is not set\n# CONFIG_SENSORS_TPS53679 is not set\n# CONFIG_SENSORS_TSL2550 is not set\n# CONFIG_SENSORS_TSL2563 is not set\n# CONFIG_SENSORS_UCD9000 is not set\n# CONFIG_SENSORS_UCD9200 is not set\n# CONFIG_SENSORS_VEXPRESS is not set\n# CONFIG_SENSORS_VIA686A is not set\n# CONFIG_SENSORS_VIA_CPUTEMP is not set\n# CONFIG_SENSORS_VT1211 is not set\n# CONFIG_SENSORS_VT8231 is not set\n# CONFIG_SENSORS_W83627EHF is not set\n# CONFIG_SENSORS_W83627HF is not set\n# CONFIG_SENSORS_W83773G is not set\n# CONFIG_SENSORS_W83781D is not set\n# CONFIG_SENSORS_W83791D is not set\n# CONFIG_SENSORS_W83792D is not set\n# CONFIG_SENSORS_W83793 is not set\n# CONFIG_SENSORS_W83795 is not set\n# CONFIG_SENSORS_W83L785TS is not set\n# CONFIG_SENSORS_W83L786NG is not set\n# CONFIG_SENSORS_XDPE122 is not set\n# CONFIG_SENSORS_XGENE is not set\n# CONFIG_SENSORS_ZL6100 is not set\nCONFIG_SERIAL_8250=y\nCONFIG_SERIAL_8250_16550A_VARIANTS=y\n# CONFIG_SERIAL_8250_ACCENT is not set\n# CONFIG_SERIAL_8250_ASPEED_VUART is not set\n# CONFIG_SERIAL_8250_BOCA is not set\nCONFIG_SERIAL_8250_CONSOLE=y\n# CONFIG_SERIAL_8250_CS is not set\n# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set\n# CONFIG_SERIAL_8250_DETECT_IRQ is not set\nCONFIG_SERIAL_8250_DMA=y\n# CONFIG_SERIAL_8250_DW is not set\n# CONFIG_SERIAL_8250_EM is not set\n# CONFIG_SERIAL_8250_EXAR is not set\n# CONFIG_SERIAL_8250_EXAR_ST16C554 is not set\n# CONFIG_SERIAL_8250_EXTENDED is not set\n# CONFIG_SERIAL_8250_FINTEK is not set\n# CONFIG_SERIAL_8250_FOURPORT is not set\n# CONFIG_SERIAL_8250_HUB6 is not set\n# CONFIG_SERIAL_8250_INGENIC is not set\n# CONFIG_SERIAL_8250_LPSS is not set\n# CONFIG_SERIAL_8250_MANY_PORTS is not set\n# CONFIG_SERIAL_8250_MID is not set\n# CONFIG_SERIAL_8250_MOXA is not set\nCONFIG_SERIAL_8250_NR_UARTS=2\n# CONFIG_SERIAL_8250_PCI is not set\n# CONFIG_SERIAL_8250_RSA is not set\n# CONFIG_SERIAL_8250_RT288X is not set\nCONFIG_SERIAL_8250_RUNTIME_UARTS=2\n# CONFIG_SERIAL_ALTERA_JTAGUART is not set\n# CONFIG_SERIAL_ALTERA_UART is not set\n# CONFIG_SERIAL_AMBA_PL010 is not set\n# CONFIG_SERIAL_AMBA_PL011 is not set\n# CONFIG_SERIAL_ARC is not set\n# CONFIG_SERIAL_BCM63XX is not set\n# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set\nCONFIG_SERIAL_CORE=y\nCONFIG_SERIAL_CORE_CONSOLE=y\n# CONFIG_SERIAL_DEV_BUS is not set\nCONFIG_SERIAL_EARLYCON=y\n# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set\n# CONFIG_SERIAL_FSL_LINFLEXUART is not set\n# CONFIG_SERIAL_FSL_LPUART is not set\n# CONFIG_SERIAL_GRLIB_GAISLER_APBUART is not set\n# CONFIG_SERIAL_IFX6X60 is not set\n# CONFIG_SERIAL_JSM is not set\n# CONFIG_SERIAL_MAX3100 is not set\n# CONFIG_SERIAL_MAX310X is not set\n# CONFIG_SERIAL_NONSTANDARD is not set\n# CONFIG_SERIAL_OF_PLATFORM is not set\n# CONFIG_SERIAL_OF_PLATFORM_NWPSERIAL is not set\n# CONFIG_SERIAL_PCH_UART is not set\n# CONFIG_SERIAL_RP2 is not set\n# CONFIG_SERIAL_SC16IS7XX is not set\n# CONFIG_SERIAL_SCCNXP is not set\n# CONFIG_SERIAL_SH_SCI is not set\n# CONFIG_SERIAL_SIFIVE is not set\n# CONFIG_SERIAL_SPRD is not set\n# CONFIG_SERIAL_STM32 is not set\n# CONFIG_SERIAL_ST_ASC is not set\n# CONFIG_SERIAL_TIMBERDALE is not set\n# CONFIG_SERIAL_UARTLITE is not set\n# CONFIG_SERIAL_XILINX_PS_UART is not set\n# CONFIG_SERIO is not set\n# CONFIG_SERIO_ALTERA_PS2 is not set\n# CONFIG_SERIO_AMBAKMI is not set\n# CONFIG_SERIO_APBPS2 is not set\n# CONFIG_SERIO_ARC_PS2 is not set\n# CONFIG_SERIO_CT82C710 is not set\n# CONFIG_SERIO_GPIO_PS2 is not set\n# CONFIG_SERIO_I8042 is not set\n# CONFIG_SERIO_LIBPS2 is not set\n# CONFIG_SERIO_PARKBD is not set\n# CONFIG_SERIO_PCIPS2 is not set\n# CONFIG_SERIO_PS2MULT is not set\n# CONFIG_SERIO_RAW is not set\n# CONFIG_SERIO_SERPORT is not set\n# CONFIG_SERIO_SUN4I_PS2 is not set\n# CONFIG_SFC is not set\n# CONFIG_SFC_FALCON is not set\n# CONFIG_SFI is not set\n# CONFIG_SFP is not set\n# CONFIG_SF_PDMA is not set\n# CONFIG_SGETMASK_SYSCALL is not set\n# CONFIG_SGI_IOC4 is not set\n# CONFIG_SGI_IP22 is not set\n# CONFIG_SGI_IP27 is not set\n# CONFIG_SGI_IP28 is not set\n# CONFIG_SGI_IP30 is not set\n# CONFIG_SGI_IP32 is not set\n# CONFIG_SGI_MFD_IOC3 is not set\n# CONFIG_SGI_PARTITION is not set\n# CONFIG_SG_POOL is not set\n# CONFIG_SG_SPLIT is not set\nCONFIG_SHMEM=y\n# CONFIG_SHUFFLE_PAGE_ALLOCATOR is not set\n# CONFIG_SH_ETH is not set\n# CONFIG_SH_TIMER_CMT is not set\n# CONFIG_SH_TIMER_MTU2 is not set\n# CONFIG_SH_TIMER_TMU is not set\n# CONFIG_SI1133 is not set\n# CONFIG_SI1145 is not set\n# CONFIG_SI7005 is not set\n# CONFIG_SI7020 is not set\n# CONFIG_SIBYTE_BIGSUR is not set\n# CONFIG_SIBYTE_CARMEL is not set\n# CONFIG_SIBYTE_CRHINE is not set\n# CONFIG_SIBYTE_CRHONE is not set\n# CONFIG_SIBYTE_LITTLESUR is not set\n# CONFIG_SIBYTE_RHONE is not set\n# CONFIG_SIBYTE_SENTOSA is not set\n# CONFIG_SIBYTE_SWARM is not set\nCONFIG_SIGNALFD=y\n# CONFIG_SIGNED_PE_FILE_VERIFICATION is not set\n# CONFIG_SIMPLE_GPIO is not set\n# CONFIG_SIMPLE_PM_BUS is not set\n# CONFIG_SIOX is not set\n# CONFIG_SIS190 is not set\n# CONFIG_SIS900 is not set\n# CONFIG_SKGE is not set\n# CONFIG_SKY2 is not set\n# CONFIG_SKY2_DEBUG is not set\n# CONFIG_SLAB is not set\nCONFIG_SLABINFO=y\n# CONFIG_SLAB_FREELIST_HARDENED is not set\n# CONFIG_SLAB_FREELIST_RANDOM is not set\nCONFIG_SLAB_MERGE_DEFAULT=y\n# CONFIG_SLHC is not set\n# CONFIG_SLICOSS is not set\n# CONFIG_SLIMBUS is not set\n# CONFIG_SLIP is not set\n# CONFIG_SLOB is not set\nCONFIG_SLUB=y\nCONFIG_SLUB_CPU_PARTIAL=y\n# CONFIG_SLUB_DEBUG is not set\n# CONFIG_SLUB_DEBUG_ON is not set\n# CONFIG_SLUB_MEMCG_SYSFS_ON is not set\n# CONFIG_SLUB_STATS is not set\n# CONFIG_SMARTJOYPLUS_FF is not set\n# CONFIG_SMB_SERVER is not set\n# CONFIG_SMC911X is not set\n# CONFIG_SMC9194 is not set\n# CONFIG_SMC91X is not set\n# CONFIG_SMP is not set\n# CONFIG_SMSC911X is not set\n# CONFIG_SMSC9420 is not set\n# CONFIG_SMSC_PHY is not set\n# CONFIG_SMS_SDIO_DRV is not set\n# CONFIG_SMS_USB_DRV is not set\n# CONFIG_SM_CAMCC_8250 is not set\n# CONFIG_SM_FTL is not set\n# CONFIG_SM_GCC_6115 is not set\n# CONFIG_SM_GCC_6125 is not set\n# CONFIG_SM_GCC_6350 is not set\n# CONFIG_SM_GCC_8350 is not set\n# CONFIG_SND is not set\n# CONFIG_SND_AC97_POWER_SAVE is not set\n# CONFIG_SND_AD1816A is not set\n# CONFIG_SND_AD1848 is not set\n# CONFIG_SND_AD1889 is not set\n# CONFIG_SND_ADLIB is not set\n# CONFIG_SND_ALI5451 is not set\n# CONFIG_SND_ALOOP is not set\n# CONFIG_SND_ALS100 is not set\n# CONFIG_SND_ALS300 is not set\n# CONFIG_SND_ALS4000 is not set\n# CONFIG_SND_ARM is not set\n# CONFIG_SND_ASIHPI is not set\n# CONFIG_SND_ATIIXP is not set\n# CONFIG_SND_ATIIXP_MODEM is not set\n# CONFIG_SND_ATMEL_AC97C is not set\n# CONFIG_SND_ATMEL_SOC is not set\n# CONFIG_SND_AU8810 is not set\n# CONFIG_SND_AU8820 is not set\n# CONFIG_SND_AU8830 is not set\n# CONFIG_SND_AUDIO_GRAPH_CARD is not set\n# CONFIG_SND_AUDIO_GRAPH_SCU_CARD is not set\n# CONFIG_SND_AW2 is not set\n# CONFIG_SND_AZT2320 is not set\n# CONFIG_SND_AZT3328 is not set\n# CONFIG_SND_BCD2000 is not set\n# CONFIG_SND_BCM63XX_I2S_WHISTLER is not set\n# CONFIG_SND_BT87X is not set\n# CONFIG_SND_CA0106 is not set\n# CONFIG_SND_CMI8330 is not set\n# CONFIG_SND_CMIPCI is not set\n# CONFIG_SND_CS4231 is not set\n# CONFIG_SND_CS4236 is not set\n# CONFIG_SND_CS4281 is not set\n# CONFIG_SND_CS46XX is not set\n# CONFIG_SND_CS5530 is not set\n# CONFIG_SND_CS5535AUDIO is not set\n# CONFIG_SND_CTXFI is not set\n# CONFIG_SND_DARLA20 is not set\n# CONFIG_SND_DARLA24 is not set\n# CONFIG_SND_DEBUG is not set\n# CONFIG_SND_DESIGNWARE_I2S is not set\nCONFIG_SND_DRIVERS=y\n# CONFIG_SND_DUMMY is not set\n# CONFIG_SND_DYNAMIC_MINORS is not set\n# CONFIG_SND_ECHO3G is not set\n# CONFIG_SND_EDMA_SOC is not set\n# CONFIG_SND_EMU10K1 is not set\n# CONFIG_SND_EMU10K1X is not set\n# CONFIG_SND_EMU10K1_SEQ is not set\n# CONFIG_SND_ENS1370 is not set\n# CONFIG_SND_ENS1371 is not set\n# CONFIG_SND_ES1688 is not set\n# CONFIG_SND_ES18XX is not set\n# CONFIG_SND_ES1938 is not set\n# CONFIG_SND_ES1968 is not set\n# CONFIG_SND_FIREWIRE is not set\n# CONFIG_SND_FM801 is not set\n# CONFIG_SND_GINA20 is not set\n# CONFIG_SND_GINA24 is not set\n# CONFIG_SND_GUSCLASSIC is not set\n# CONFIG_SND_GUSEXTREME is not set\n# CONFIG_SND_GUSMAX is not set\n# CONFIG_SND_HDA_CODEC_CS8409 is not set\n# CONFIG_SND_HDA_INTEL is not set\n# CONFIG_SND_HDA_INTEL_DETECT_DMIC is not set\n# CONFIG_SND_HDA_INTEL_HDMI_SILENT_STREAM is not set\nCONFIG_SND_HDA_POWER_SAVE_DEFAULT=0\nCONFIG_SND_HDA_PREALLOC_SIZE=64\n# CONFIG_SND_HDSP is not set\n# CONFIG_SND_HDSPM is not set\n# CONFIG_SND_HRTIMER is not set\n# CONFIG_SND_HWDEP is not set\n# CONFIG_SND_I2S_HI6210_I2S is not set\n# CONFIG_SND_ICE1712 is not set\n# CONFIG_SND_ICE1724 is not set\n# CONFIG_SND_INDIGO is not set\n# CONFIG_SND_INDIGODJ is not set\n# CONFIG_SND_INDIGODJX is not set\n# CONFIG_SND_INDIGOIO is not set\n# CONFIG_SND_INDIGOIOX is not set\n# CONFIG_SND_INTEL8X0 is not set\n# CONFIG_SND_INTEL8X0M is not set\n# CONFIG_SND_INTERWAVE is not set\n# CONFIG_SND_INTERWAVE_STB is not set\n# CONFIG_SND_ISA is not set\n# CONFIG_SND_JZ4740_SOC_I2S is not set\n# CONFIG_SND_KIRKWOOD_SOC is not set\n# CONFIG_SND_KORG1212 is not set\n# CONFIG_SND_LAYLA20 is not set\n# CONFIG_SND_LAYLA24 is not set\n# CONFIG_SND_LOLA is not set\n# CONFIG_SND_LX6464ES is not set\n# CONFIG_SND_MAESTRO3 is not set\nCONFIG_SND_MAX_CARDS=16\n# CONFIG_SND_MIA is not set\n# CONFIG_SND_MIPS is not set\n# CONFIG_SND_MIRO is not set\n# CONFIG_SND_MIXART is not set\n# CONFIG_SND_MIXER_OSS is not set\n# CONFIG_SND_MONA is not set\n# CONFIG_SND_MPC52xx_SOC_EFIKA is not set\n# CONFIG_SND_MPU401 is not set\n# CONFIG_SND_MTPAV is not set\n# CONFIG_SND_MTS64 is not set\n# CONFIG_SND_MXS_SOC is not set\n# CONFIG_SND_NM256 is not set\n# CONFIG_SND_OPL3SA2 is not set\n# CONFIG_SND_OPL3_LIB_SEQ is not set\n# CONFIG_SND_OPL4_LIB_SEQ is not set\n# CONFIG_SND_OPTI92X_AD1848 is not set\n# CONFIG_SND_OPTI92X_CS4231 is not set\n# CONFIG_SND_OPTI93X is not set\nCONFIG_SND_OSSEMUL=y\n# CONFIG_SND_OXYGEN is not set\nCONFIG_SND_PCI=y\n# CONFIG_SND_PCM is not set\n# CONFIG_SND_PCMCIA is not set\n# CONFIG_SND_PCM_OSS is not set\nCONFIG_SND_PCM_OSS_PLUGINS=y\n# CONFIG_SND_PCM_TIMER is not set\n# CONFIG_SND_PCM_XRUN_DEBUG is not set\n# CONFIG_SND_PCXHR is not set\n# CONFIG_SND_PDAUDIOCF is not set\n# CONFIG_SND_PORTMAN2X4 is not set\n# CONFIG_SND_POWERPC_SOC is not set\n# CONFIG_SND_PPC is not set\nCONFIG_SND_PROC_FS=y\n# CONFIG_SND_RAWMIDI is not set\n# CONFIG_SND_RAWMIDI_SEQ is not set\n# CONFIG_SND_RIPTIDE is not set\n# CONFIG_SND_RME32 is not set\n# CONFIG_SND_RME96 is not set\n# CONFIG_SND_RME9652 is not set\n# CONFIG_SND_RTCTIMER is not set\n# CONFIG_SND_SB16 is not set\n# CONFIG_SND_SB8 is not set\n# CONFIG_SND_SBAWE is not set\n# CONFIG_SND_SBAWE_SEQ is not set\n# CONFIG_SND_SE6X is not set\n# CONFIG_SND_SEQUENCER is not set\n# CONFIG_SND_SERIAL_U16550 is not set\n# CONFIG_SND_SIMPLE_CARD is not set\n# CONFIG_SND_SIMPLE_SCU_CARD is not set\n# CONFIG_SND_SIS7019 is not set\n# CONFIG_SND_SOC is not set\n# CONFIG_SND_SOC_AC97_CODEC is not set\n# CONFIG_SND_SOC_ADAU1372_I2C is not set\n# CONFIG_SND_SOC_ADAU1372_SPI is not set\n# CONFIG_SND_SOC_ADAU1701 is not set\n# CONFIG_SND_SOC_ADAU1761_I2C is not set\n# CONFIG_SND_SOC_ADAU1761_SPI is not set\n# CONFIG_SND_SOC_ADAU7002 is not set\n# CONFIG_SND_SOC_ADAU7118_HW is not set\n# CONFIG_SND_SOC_ADAU7118_I2C is not set\n# CONFIG_SND_SOC_ADI is not set\n# CONFIG_SND_SOC_AK4104 is not set\n# CONFIG_SND_SOC_AK4118 is not set\n# CONFIG_SND_SOC_AK4458 is not set\n# CONFIG_SND_SOC_AK4554 is not set\n# CONFIG_SND_SOC_AK4613 is not set\n# CONFIG_SND_SOC_AK4642 is not set\n# CONFIG_SND_SOC_AK5386 is not set\n# CONFIG_SND_SOC_AK5558 is not set\n# CONFIG_SND_SOC_ALC5623 is not set\n# CONFIG_SND_SOC_AMD_ACP is not set\n# CONFIG_SND_SOC_AMD_ACP3x is not set\n# CONFIG_SND_SOC_AMD_ACP5x is not set\n# CONFIG_SND_SOC_AMD_RENOIR is not set\n# CONFIG_SND_SOC_AU1XAUDIO is not set\n# CONFIG_SND_SOC_AU1XPSC is not set\n# CONFIG_SND_SOC_BD28623 is not set\n# CONFIG_SND_SOC_BT_SCO is not set\n# CONFIG_SND_SOC_CS35L32 is not set\n# CONFIG_SND_SOC_CS35L33 is not set\n# CONFIG_SND_SOC_CS35L34 is not set\n# CONFIG_SND_SOC_CS35L35 is not set\n# CONFIG_SND_SOC_CS35L36 is not set\n# CONFIG_SND_SOC_CS4234 is not set\n# CONFIG_SND_SOC_CS4265 is not set\n# CONFIG_SND_SOC_CS4270 is not set\n# CONFIG_SND_SOC_CS4271 is not set\n# CONFIG_SND_SOC_CS4271_I2C is not set\n# CONFIG_SND_SOC_CS4271_SPI is not set\n# CONFIG_SND_SOC_CS42L42 is not set\n# CONFIG_SND_SOC_CS42L51_I2C is not set\n# CONFIG_SND_SOC_CS42L52 is not set\n# CONFIG_SND_SOC_CS42L56 is not set\n# CONFIG_SND_SOC_CS42L73 is not set\n# CONFIG_SND_SOC_CS42XX8_I2C is not set\n# CONFIG_SND_SOC_CS43130 is not set\n# CONFIG_SND_SOC_CS4341 is not set\n# CONFIG_SND_SOC_CS4349 is not set\n# CONFIG_SND_SOC_CS53L30 is not set\n# CONFIG_SND_SOC_CX2072X is not set\n# CONFIG_SND_SOC_DA7213 is not set\n# CONFIG_SND_SOC_DIO2125 is not set\n# CONFIG_SND_SOC_DMIC is not set\n# CONFIG_SND_SOC_ES7134 is not set\n# CONFIG_SND_SOC_ES7241 is not set\n# CONFIG_SND_SOC_ES8316 is not set\n# CONFIG_SND_SOC_ES8328 is not set\n# CONFIG_SND_SOC_ES8328_I2C is not set\n# CONFIG_SND_SOC_ES8328_SPI is not set\n# CONFIG_SND_SOC_EUKREA_TLV320 is not set\n# CONFIG_SND_SOC_FSL_ASOC_CARD is not set\n# CONFIG_SND_SOC_FSL_ASRC is not set\n# CONFIG_SND_SOC_FSL_AUD2HTX is not set\n# CONFIG_SND_SOC_FSL_AUDMIX is not set\n# CONFIG_SND_SOC_FSL_ESAI is not set\n# CONFIG_SND_SOC_FSL_MICFIL is not set\n# CONFIG_SND_SOC_FSL_SAI is not set\n# CONFIG_SND_SOC_FSL_SPDIF is not set\n# CONFIG_SND_SOC_FSL_SSI is not set\n# CONFIG_SND_SOC_FSL_XCVR is not set\n# CONFIG_SND_SOC_GTM601 is not set\n# CONFIG_SND_SOC_ICS43432 is not set\n# CONFIG_SND_SOC_IMG is not set\n# CONFIG_SND_SOC_IMX_AUDMIX is not set\n# CONFIG_SND_SOC_IMX_AUDMUX is not set\n# CONFIG_SND_SOC_IMX_ES8328 is not set\n# CONFIG_SND_SOC_IMX_SPDIF is not set\n# CONFIG_SND_SOC_IMX_WM8962 is not set\n# CONFIG_SND_SOC_INNO_RK3036 is not set\n# CONFIG_SND_SOC_INTEL_APL is not set\n# CONFIG_SND_SOC_INTEL_BAYTRAIL is not set\n# CONFIG_SND_SOC_INTEL_BDW_RT5677_MACH is not set\n# CONFIG_SND_SOC_INTEL_BXT_DA7219_MAX98357A_MACH is not set\n# CONFIG_SND_SOC_INTEL_BXT_RT298_MACH is not set\n# CONFIG_SND_SOC_INTEL_BYTCR_RT5640_MACH is not set\n# CONFIG_SND_SOC_INTEL_BYTCR_RT5651_MACH is not set\n# CONFIG_SND_SOC_INTEL_BYT_CHT_DA7213_MACH is not set\n# CONFIG_SND_SOC_INTEL_BYT_CHT_ES8316_MACH is not set\n# CONFIG_SND_SOC_INTEL_BYT_CHT_NOCODEC_MACH is not set\n# CONFIG_SND_SOC_INTEL_BYT_MAX98090_MACH is not set\n# CONFIG_SND_SOC_INTEL_BYT_RT5640_MACH is not set\n# CONFIG_SND_SOC_INTEL_CATPT is not set\n# CONFIG_SND_SOC_INTEL_CFL is not set\n# CONFIG_SND_SOC_INTEL_CHT_BSW_MAX98090_TI_MACH is not set\n# CONFIG_SND_SOC_INTEL_CHT_BSW_NAU8824_MACH is not set\n# CONFIG_SND_SOC_INTEL_CHT_BSW_RT5645_MACH is not set\n# CONFIG_SND_SOC_INTEL_CHT_BSW_RT5672_MACH is not set\n# CONFIG_SND_SOC_INTEL_CML_H is not set\n# CONFIG_SND_SOC_INTEL_CML_LP is not set\n# CONFIG_SND_SOC_INTEL_CNL is not set\n# CONFIG_SND_SOC_INTEL_GLK is not set\n# CONFIG_SND_SOC_INTEL_HASWELL is not set\n# CONFIG_SND_SOC_INTEL_KBL is not set\n# CONFIG_SND_SOC_INTEL_KBL_RT5663_MAX98927_MACH is not set\n# CONFIG_SND_SOC_INTEL_KBL_RT5663_RT5514_MAX98927_MACH is not set\n# CONFIG_SND_SOC_INTEL_KEEMBAY is not set\n# CONFIG_SND_SOC_INTEL_SKL is not set\n# CONFIG_SND_SOC_INTEL_SKL_NAU88L25_MAX98357A_MACH is not set\n# CONFIG_SND_SOC_INTEL_SKL_NAU88L25_SSM4567_MACH is not set\n# CONFIG_SND_SOC_INTEL_SKL_RT286_MACH is not set\n# CONFIG_SND_SOC_INTEL_SKYLAKE is not set\n# CONFIG_SND_SOC_INTEL_SST is not set\nCONFIG_SND_SOC_INTEL_SST_TOPLEVEL=y\n# CONFIG_SND_SOC_INTEL_USER_FRIENDLY_LONG_NAMES is not set\n# CONFIG_SND_SOC_JZ4725B_CODEC is not set\n# CONFIG_SND_SOC_JZ4740_CODEC is not set\n# CONFIG_SND_SOC_JZ4770_CODEC is not set\n# CONFIG_SND_SOC_LPASS_RX_MACRO is not set\n# CONFIG_SND_SOC_LPASS_TX_MACRO is not set\n# CONFIG_SND_SOC_LPASS_VA_MACRO is not set\n# CONFIG_SND_SOC_LPASS_WSA_MACRO is not set\n# CONFIG_SND_SOC_MA120X0P is not set\n# CONFIG_SND_SOC_MAX9759 is not set\n# CONFIG_SND_SOC_MAX98088 is not set\n# CONFIG_SND_SOC_MAX98357A is not set\n# CONFIG_SND_SOC_MAX98373 is not set\n# CONFIG_SND_SOC_MAX98373_I2C is not set\n# CONFIG_SND_SOC_MAX98390 is not set\n# CONFIG_SND_SOC_MAX98504 is not set\n# CONFIG_SND_SOC_MAX9860 is not set\n# CONFIG_SND_SOC_MAX9867 is not set\n# CONFIG_SND_SOC_MAX98927 is not set\n# CONFIG_SND_SOC_MEDIATEK is not set\n# CONFIG_SND_SOC_MPC5200_AC97 is not set\n# CONFIG_SND_SOC_MPC5200_I2S is not set\n# CONFIG_SND_SOC_MSM8916_WCD_ANALOG is not set\n# CONFIG_SND_SOC_MSM8916_WCD_DIGITAL is not set\n# CONFIG_SND_SOC_MT2701 is not set\n# CONFIG_SND_SOC_MT6351 is not set\n# CONFIG_SND_SOC_MT6358 is not set\n# CONFIG_SND_SOC_MT6359 is not set\n# CONFIG_SND_SOC_MT6359_ACCDET is not set\n# CONFIG_SND_SOC_MT6660 is not set\n# CONFIG_SND_SOC_MT6797 is not set\n# CONFIG_SND_SOC_MT8173 is not set\n# CONFIG_SND_SOC_MT8183 is not set\n# CONFIG_SND_SOC_MT8192 is not set\n# CONFIG_SND_SOC_MT8195 is not set\n# CONFIG_SND_SOC_MTK_BTCVSD is not set\n# CONFIG_SND_SOC_NAU8315 is not set\n# CONFIG_SND_SOC_NAU8540 is not set\n# CONFIG_SND_SOC_NAU8810 is not set\n# CONFIG_SND_SOC_NAU8822 is not set\n# CONFIG_SND_SOC_NAU8824 is not set\n# CONFIG_SND_SOC_PCM1681 is not set\n# CONFIG_SND_SOC_PCM1789_I2C is not set\n# CONFIG_SND_SOC_PCM1792A is not set\n# CONFIG_SND_SOC_PCM179X_I2C is not set\n# CONFIG_SND_SOC_PCM179X_SPI is not set\n# CONFIG_SND_SOC_PCM186X_I2C is not set\n# CONFIG_SND_SOC_PCM186X_SPI is not set\n# CONFIG_SND_SOC_PCM3060_I2C is not set\n# CONFIG_SND_SOC_PCM3060_SPI is not set\n# CONFIG_SND_SOC_PCM3168A_I2C is not set\n# CONFIG_SND_SOC_PCM3168A_SPI is not set\n# CONFIG_SND_SOC_PCM5102A is not set\n# CONFIG_SND_SOC_PCM512x_I2C is not set\n# CONFIG_SND_SOC_PCM512x_SPI is not set\n# CONFIG_SND_SOC_QCOM is not set\n# CONFIG_SND_SOC_RK3328 is not set\n# CONFIG_SND_SOC_RT5616 is not set\n# CONFIG_SND_SOC_RT5631 is not set\n# CONFIG_SND_SOC_RT5640 is not set\n# CONFIG_SND_SOC_RT5659 is not set\n# CONFIG_SND_SOC_RT5677_SPI is not set\n# CONFIG_SND_SOC_SGTL5000 is not set\n# CONFIG_SND_SOC_SIMPLE_AMPLIFIER is not set\n# CONFIG_SND_SOC_SIMPLE_MUX is not set\n# CONFIG_SND_SOC_SIRF_AUDIO_CODEC is not set\n# CONFIG_SND_SOC_SOF_TOPLEVEL is not set\n# CONFIG_SND_SOC_SPDIF is not set\n# CONFIG_SND_SOC_SSM2305 is not set\n# CONFIG_SND_SOC_SSM2518 is not set\n# CONFIG_SND_SOC_SSM2602_I2C is not set\n# CONFIG_SND_SOC_SSM2602_SPI is not set\n# CONFIG_SND_SOC_SSM4567 is not set\n# CONFIG_SND_SOC_STA32X is not set\n# CONFIG_SND_SOC_STA350 is not set\n# CONFIG_SND_SOC_STI_SAS is not set\n# CONFIG_SND_SOC_TAS2552 is not set\n# CONFIG_SND_SOC_TAS2562 is not set\n# CONFIG_SND_SOC_TAS2764 is not set\n# CONFIG_SND_SOC_TAS2770 is not set\n# CONFIG_SND_SOC_TAS5086 is not set\n# CONFIG_SND_SOC_TAS571X is not set\n# CONFIG_SND_SOC_TAS5720 is not set\n# CONFIG_SND_SOC_TAS6424 is not set\n# CONFIG_SND_SOC_TDA7419 is not set\n# CONFIG_SND_SOC_TFA9879 is not set\n# CONFIG_SND_SOC_TFA989X is not set\n# CONFIG_SND_SOC_TLV320ADCX140 is not set\n# CONFIG_SND_SOC_TLV320AIC23_I2C is not set\n# CONFIG_SND_SOC_TLV320AIC23_SPI is not set\n# CONFIG_SND_SOC_TLV320AIC31XX is not set\n# CONFIG_SND_SOC_TLV320AIC32X4_I2C is not set\n# CONFIG_SND_SOC_TLV320AIC32X4_SPI is not set\n# CONFIG_SND_SOC_TLV320AIC3X is not set\n# CONFIG_SND_SOC_TLV320AIC3X_I2C is not set\n# CONFIG_SND_SOC_TLV320AIC3X_SPI is not set\n# CONFIG_SND_SOC_TPA6130A2 is not set\n# CONFIG_SND_SOC_TS3A227E is not set\n# CONFIG_SND_SOC_TSCS42XX is not set\n# CONFIG_SND_SOC_TSCS454 is not set\n# CONFIG_SND_SOC_UDA1334 is not set\n# CONFIG_SND_SOC_WM8510 is not set\n# CONFIG_SND_SOC_WM8523 is not set\n# CONFIG_SND_SOC_WM8524 is not set\n# CONFIG_SND_SOC_WM8580 is not set\n# CONFIG_SND_SOC_WM8711 is not set\n# CONFIG_SND_SOC_WM8728 is not set\n# CONFIG_SND_SOC_WM8731 is not set\n# CONFIG_SND_SOC_WM8737 is not set\n# CONFIG_SND_SOC_WM8741 is not set\n# CONFIG_SND_SOC_WM8750 is not set\n# CONFIG_SND_SOC_WM8753 is not set\n# CONFIG_SND_SOC_WM8770 is not set\n# CONFIG_SND_SOC_WM8776 is not set\n# CONFIG_SND_SOC_WM8782 is not set\n# CONFIG_SND_SOC_WM8804_I2C is not set\n# CONFIG_SND_SOC_WM8804_SPI is not set\n# CONFIG_SND_SOC_WM8903 is not set\n# CONFIG_SND_SOC_WM8904 is not set\n# CONFIG_SND_SOC_WM8960 is not set\n# CONFIG_SND_SOC_WM8962 is not set\n# CONFIG_SND_SOC_WM8974 is not set\n# CONFIG_SND_SOC_WM8978 is not set\n# CONFIG_SND_SOC_WM8985 is not set\n# CONFIG_SND_SOC_XILINX_AUDIO_FORMATTER is not set\n# CONFIG_SND_SOC_XILINX_I2S is not set\n# CONFIG_SND_SOC_XILINX_SPDIF is not set\n# CONFIG_SND_SOC_XTFPGA_I2S is not set\n# CONFIG_SND_SOC_ZL38060 is not set\n# CONFIG_SND_SOC_ZX_AUD96P22 is not set\n# CONFIG_SND_SONICVIBES is not set\n# CONFIG_SND_SPI is not set\n# CONFIG_SND_SSCAPE is not set\n# CONFIG_SND_SST_ATOM_HIFI2_PLATFORM_ACPI is not set\n# CONFIG_SND_SST_ATOM_HIFI2_PLATFORM_PCI is not set\n# CONFIG_SND_SUN4I_CODEC is not set\n# CONFIG_SND_SUPPORT_OLD_API is not set\n# CONFIG_SND_TIMER is not set\n# CONFIG_SND_TRIDENT is not set\nCONFIG_SND_USB=y\n# CONFIG_SND_USB_6FIRE is not set\n# CONFIG_SND_USB_AUDIO is not set\n# CONFIG_SND_USB_CAIAQ is not set\n# CONFIG_SND_USB_HIFACE is not set\n# CONFIG_SND_USB_POD is not set\n# CONFIG_SND_USB_PODHD is not set\n# CONFIG_SND_USB_TONEPORT is not set\n# CONFIG_SND_USB_UA101 is not set\n# CONFIG_SND_USB_US122L is not set\n# CONFIG_SND_USB_USX2Y is not set\n# CONFIG_SND_USB_VARIAX is not set\n# CONFIG_SND_VERBOSE_PRINTK is not set\nCONFIG_SND_VERBOSE_PROCFS=y\n# CONFIG_SND_VIA82XX is not set\n# CONFIG_SND_VIA82XX_MODEM is not set\n# CONFIG_SND_VIRTIO is not set\n# CONFIG_SND_VIRTUOSO is not set\n# CONFIG_SND_VX222 is not set\n# CONFIG_SND_VXPOCKET is not set\n# CONFIG_SND_WAVEFRONT is not set\nCONFIG_SND_X86=y\n# CONFIG_SND_XEN_FRONTEND is not set\n# CONFIG_SND_YMFPCI is not set\n# CONFIG_SNI_RM is not set\n# CONFIG_SOCIONEXT_SYNQUACER_PREITS is not set\n# CONFIG_SOCK_CGROUP_DATA is not set\n# CONFIG_SOC_AM33XX is not set\n# CONFIG_SOC_AM43XX is not set\n# CONFIG_SOC_BRCMSTB is not set\n# CONFIG_SOC_CAMERA is not set\n# CONFIG_SOC_DRA7XX is not set\n# CONFIG_SOC_HAS_OMAP2_SDRC is not set\n# CONFIG_SOC_OMAP5 is not set\n# CONFIG_SOC_TI is not set\n# CONFIG_SOFTLOCKUP_DETECTOR is not set\n# CONFIG_SOFT_WATCHDOG is not set\n# CONFIG_SOLARIS_X86_PARTITION is not set\n# CONFIG_SONYPI is not set\n# CONFIG_SONY_LAPTOP is not set\n# CONFIG_SOUND is not set\n# CONFIG_SOUNDWIRE is not set\n# CONFIG_SOUND_OSS_CORE is not set\n# CONFIG_SOUND_OSS_CORE_PRECLAIM is not set\n# CONFIG_SOUND_PRIME is not set\n# CONFIG_SP5100_TCO is not set\n# CONFIG_SPARSEMEM_MANUAL is not set\n# CONFIG_SPARSEMEM_STATIC is not set\n# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set\n# CONFIG_SPARSE_IRQ is not set\n# CONFIG_SPARSE_RCU_POINTER is not set\n# CONFIG_SPEAKUP is not set\n# CONFIG_SPI is not set\n# CONFIG_SPINLOCK_TEST is not set\n# CONFIG_SPI_ALTERA is not set\n# CONFIG_SPI_AMD is not set\n# CONFIG_SPI_AU1550 is not set\n# CONFIG_SPI_AXI_SPI_ENGINE is not set\n# CONFIG_SPI_BCM2835 is not set\n# CONFIG_SPI_BCM_QSPI is not set\n# CONFIG_SPI_BITBANG is not set\n# CONFIG_SPI_BUTTERFLY is not set\n# CONFIG_SPI_CADENCE is not set\n# CONFIG_SPI_CADENCE_QUADSPI is not set\n# CONFIG_SPI_DEBUG is not set\n# CONFIG_SPI_DESIGNWARE is not set\n# CONFIG_SPI_FSL_DSPI is not set\n# CONFIG_SPI_FSL_ESPI is not set\n# CONFIG_SPI_FSL_SPI is not set\n# CONFIG_SPI_GPIO is not set\n# CONFIG_SPI_GPIO_OLD is not set\n# CONFIG_SPI_IMG_SPFI is not set\n# CONFIG_SPI_LANTIQ_SSC is not set\n# CONFIG_SPI_LM70_LLP is not set\n# CONFIG_SPI_LOOPBACK_TEST is not set\n# CONFIG_SPI_MASTER is not set\n# CONFIG_SPI_MEM is not set\n# CONFIG_SPI_MPC52xx is not set\n# CONFIG_SPI_MPC52xx_PSC is not set\n# CONFIG_SPI_MTK_QUADSPI is not set\n# CONFIG_SPI_MUX is not set\n# CONFIG_SPI_MXIC is not set\n# CONFIG_SPI_NXP_FLEXSPI is not set\n# CONFIG_SPI_OCTEON is not set\n# CONFIG_SPI_OC_TINY is not set\n# CONFIG_SPI_ORION is not set\n# CONFIG_SPI_PL022 is not set\n# CONFIG_SPI_PPC4xx is not set\n# CONFIG_SPI_PXA2XX is not set\n# CONFIG_SPI_PXA2XX_PCI is not set\n# CONFIG_SPI_QCOM_QSPI is not set\n# CONFIG_SPI_ROCKCHIP is not set\n# CONFIG_SPI_S3C64XX is not set\n# CONFIG_SPI_SC18IS602 is not set\n# CONFIG_SPI_SIFIVE is not set\n# CONFIG_SPI_SLAVE is not set\n# CONFIG_SPI_SPIDEV is not set\n# CONFIG_SPI_THUNDERX is not set\n# CONFIG_SPI_TI_QSPI is not set\n# CONFIG_SPI_TLE62X0 is not set\n# CONFIG_SPI_TOPCLIFF_PCH is not set\n# CONFIG_SPI_XCOMM is not set\n# CONFIG_SPI_XILINX is not set\n# CONFIG_SPI_XWAY is not set\n# CONFIG_SPI_ZYNQMP_GQSPI is not set\nCONFIG_SPLIT_PTLOCK_CPUS=4\n# CONFIG_SPMI is not set\n# CONFIG_SPS30 is not set\n# CONFIG_SPS30_I2C is not set\n# CONFIG_SPS30_SERIAL is not set\nCONFIG_SQUASHFS=y\n# CONFIG_SQUASHFS_4K_DEVBLK_SIZE is not set\n# CONFIG_SQUASHFS_DECOMP_MULTI is not set\nCONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y\n# CONFIG_SQUASHFS_DECOMP_SINGLE is not set\nCONFIG_SQUASHFS_EMBEDDED=y\n# CONFIG_SQUASHFS_FILE_CACHE is not set\nCONFIG_SQUASHFS_FILE_DIRECT=y\nCONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3\n# CONFIG_SQUASHFS_LZ4 is not set\n# CONFIG_SQUASHFS_LZO is not set\n# CONFIG_SQUASHFS_XATTR is not set\nCONFIG_SQUASHFS_XZ=y\n# CONFIG_SQUASHFS_ZLIB is not set\n# CONFIG_SQUASHFS_ZSTD is not set\n# CONFIG_SRAM is not set\n# CONFIG_SRF04 is not set\n# CONFIG_SRF08 is not set\n# CONFIG_SSB is not set\n# CONFIG_SSB_DEBUG is not set\n# CONFIG_SSB_DRIVER_GPIO is not set\n# CONFIG_SSB_HOST_SOC is not set\n# CONFIG_SSB_PCMCIAHOST is not set\nCONFIG_SSB_POSSIBLE=y\n# CONFIG_SSB_SDIOHOST is not set\n# CONFIG_SSB_SILENT is not set\n# CONFIG_SSFDC is not set\n# CONFIG_STACKPROTECTOR is not set\n# CONFIG_STACKPROTECTOR_STRONG is not set\n# CONFIG_STACKTRACE is not set\n# CONFIG_STACKTRACE_BUILD_ID is not set\nCONFIG_STACKTRACE_SUPPORT=y\n# CONFIG_STACK_TRACER is not set\n# CONFIG_STACK_VALIDATION is not set\nCONFIG_STAGING=y\n# CONFIG_STAGING_BOARD is not set\n# CONFIG_STAGING_GASKET_FRAMEWORK is not set\n# CONFIG_STAGING_MEDIA is not set\nCONFIG_STANDALONE=y\n# CONFIG_STATIC_KEYS_SELFTEST is not set\n# CONFIG_STATIC_USERMODEHELPER is not set\nCONFIG_STDBINUTILS=y\n# CONFIG_STE10XP is not set\n# CONFIG_STE_MODEM_RPROC is not set\n# CONFIG_STK3310 is not set\n# CONFIG_STK8312 is not set\n# CONFIG_STK8BA50 is not set\n# CONFIG_STM is not set\n# CONFIG_STMMAC_ETH is not set\n# CONFIG_STMMAC_PCI is not set\n# CONFIG_STMMAC_PLATFORM is not set\n# CONFIG_STMMAC_SELFTESTS is not set\n# CONFIG_STM_DUMMY is not set\n# CONFIG_STM_SOURCE_CONSOLE is not set\nCONFIG_STP=y\n# CONFIG_STREAM_PARSER is not set\n# CONFIG_STRICT_DEVMEM is not set\nCONFIG_STRICT_KERNEL_RWX=y\nCONFIG_STRICT_MODULE_RWX=y\n# CONFIG_STRING_SELFTEST is not set\nCONFIG_STRIP_ASM_SYMS=y\n# CONFIG_STX104 is not set\n# CONFIG_ST_UVIS25 is not set\n# CONFIG_SUN4I_GPADC is not set\n# CONFIG_SUN50I_DE2_BUS is not set\n# CONFIG_SUN50I_ERRATUM_UNKNOWN1 is not set\n# CONFIG_SUNDANCE is not set\n# CONFIG_SUNGEM is not set\n# CONFIG_SUNRPC is not set\n# CONFIG_SUNRPC_DEBUG is not set\nCONFIG_SUNRPC_DISABLE_INSECURE_ENCTYPES=y\n# CONFIG_SUNRPC_GSS is not set\n# CONFIG_SUNXI_SRAM is not set\n# CONFIG_SUN_PARTITION is not set\n# CONFIG_SURFACE_3_BUTTON is not set\n# CONFIG_SUSPEND is not set\n# CONFIG_SUSPEND_SKIP_SYNC is not set\nCONFIG_SWAP=y\n# CONFIG_SWCONFIG is not set\n# CONFIG_SWCONFIG_B53 is not set\n# CONFIG_SWCONFIG_B53_MDIO_DRIVER is not set\n# CONFIG_SWCONFIG_B53_MMAP_DRIVER is not set\n# CONFIG_SWCONFIG_B53_SPI_DRIVER is not set\n# CONFIG_SWCONFIG_B53_SRAB_DRIVER is not set\n# CONFIG_SWCONFIG_LEDS is not set\n# CONFIG_SW_SYNC is not set\n# CONFIG_SX9310 is not set\n# CONFIG_SX9500 is not set\n# CONFIG_SXGBE_ETH is not set\nCONFIG_SYMBOLIC_ERRNAME=y\n# CONFIG_SYNCLINK_CS is not set\n# CONFIG_SYNC_FILE is not set\n# CONFIG_SYNOPSYS_DWC_ETH_QOS is not set\n# CONFIG_SYNTH_EVENTS is not set\nCONFIG_SYN_COOKIES=y\n# CONFIG_SYSCON_REBOOT_MODE is not set\nCONFIG_SYSCTL=y\n# CONFIG_SYSCTL_SYSCALL is not set\nCONFIG_SYSFS=y\n# CONFIG_SYSFS_DEPRECATED is not set\n# CONFIG_SYSFS_DEPRECATED_V2 is not set\n# CONFIG_SYSFS_SYSCALL is not set\n# CONFIG_SYSTEMPORT is not set\n# CONFIG_SYSTEM_BLACKLIST_KEYRING is not set\n# CONFIG_SYSTEM_DATA_VERIFICATION is not set\n# CONFIG_SYSTEM_TRUSTED_KEYRING is not set\nCONFIG_SYSTEM_TRUSTED_KEYS=\"\"\n# CONFIG_SYSV68_PARTITION is not set\nCONFIG_SYSVIPC=y\nCONFIG_SYSVIPC_SYSCTL=y\n# CONFIG_SYSV_FS is not set\n# CONFIG_SYS_HYPERVISOR is not set\n# CONFIG_T5403 is not set\n# CONFIG_TARGET_CORE is not set\n# CONFIG_TASKSTATS is not set\n# CONFIG_TASKS_RCU is not set\n# CONFIG_TASK_XACCT is not set\n# CONFIG_TC35815 is not set\n# CONFIG_TCG_ATMEL is not set\n# CONFIG_TCG_CRB is not set\n# CONFIG_TCG_FTPM_TEE is not set\n# CONFIG_TCG_INFINEON is not set\n# CONFIG_TCG_NSC is not set\n# CONFIG_TCG_ST33_I2C is not set\n# CONFIG_TCG_TIS is not set\n# CONFIG_TCG_TIS_I2C_ATMEL is not set\n# CONFIG_TCG_TIS_I2C_CR50 is not set\n# CONFIG_TCG_TIS_I2C_INFINEON is not set\n# CONFIG_TCG_TIS_I2C_NUVOTON is not set\n# CONFIG_TCG_TIS_SPI is not set\n# CONFIG_TCG_TIS_ST33ZP24_I2C is not set\n# CONFIG_TCG_TIS_ST33ZP24_SPI is not set\n# CONFIG_TCG_TPM is not set\n# CONFIG_TCG_VTPM_PROXY is not set\n# CONFIG_TCG_XEN is not set\n# CONFIG_TCIC is not set\nCONFIG_TCP_CONG_ADVANCED=y\n# CONFIG_TCP_CONG_BBR is not set\n# CONFIG_TCP_CONG_BIC is not set\n# CONFIG_TCP_CONG_CDG is not set\nCONFIG_TCP_CONG_CUBIC=y\n# CONFIG_TCP_CONG_DCTCP is not set\n# CONFIG_TCP_CONG_HSTCP is not set\n# CONFIG_TCP_CONG_HTCP is not set\n# CONFIG_TCP_CONG_HYBLA is not set\n# CONFIG_TCP_CONG_ILLINOIS is not set\n# CONFIG_TCP_CONG_LP is not set\n# CONFIG_TCP_CONG_NV is not set\n# CONFIG_TCP_CONG_SCALABLE is not set\n# CONFIG_TCP_CONG_VEGAS is not set\n# CONFIG_TCP_CONG_VENO is not set\n# CONFIG_TCP_CONG_WESTWOOD is not set\n# CONFIG_TCP_CONG_YEAH is not set\n# CONFIG_TCP_MD5SIG is not set\n# CONFIG_TCS3414 is not set\n# CONFIG_TCS3472 is not set\n# CONFIG_TEE is not set\n# CONFIG_TEGRA_AHB is not set\n# CONFIG_TEGRA_HOST1X is not set\n# CONFIG_TEHUTI is not set\n# CONFIG_TERANETICS_PHY is not set\n# CONFIG_TEST_ASYNC_DRIVER_PROBE is not set\n# CONFIG_TEST_BITFIELD is not set\n# CONFIG_TEST_BITMAP is not set\n# CONFIG_TEST_BITOPS is not set\n# CONFIG_TEST_BLACKHOLE_DEV is not set\n# CONFIG_TEST_BPF is not set\n# CONFIG_TEST_CLOCKSOURCE_WATCHDOG is not set\n# CONFIG_TEST_DIV64 is not set\n# CONFIG_TEST_FIRMWARE is not set\n# CONFIG_TEST_FREE_PAGES is not set\n# CONFIG_TEST_HASH is not set\n# CONFIG_TEST_HEXDUMP is not set\n# CONFIG_TEST_IDA is not set\n# CONFIG_TEST_KASAN_MODULE is not set\n# CONFIG_TEST_KMOD is not set\n# CONFIG_TEST_KSTRTOX is not set\n# CONFIG_TEST_LIST_SORT is not set\n# CONFIG_TEST_LKM is not set\n# CONFIG_TEST_LOCKUP is not set\n# CONFIG_TEST_MEMCAT_P is not set\n# CONFIG_TEST_MEMINIT is not set\n# CONFIG_TEST_MIN_HEAP is not set\n# CONFIG_TEST_OVERFLOW is not set\n# CONFIG_TEST_POWER is not set\n# CONFIG_TEST_PRINTF is not set\n# CONFIG_TEST_RHASHTABLE is not set\n# CONFIG_TEST_SCANF is not set\n# CONFIG_TEST_SORT is not set\n# CONFIG_TEST_STACKINIT is not set\n# CONFIG_TEST_STATIC_KEYS is not set\n# CONFIG_TEST_STRING_HELPERS is not set\n# CONFIG_TEST_STRSCPY is not set\n# CONFIG_TEST_SYSCTL is not set\n# CONFIG_TEST_UBSAN is not set\n# CONFIG_TEST_UDELAY is not set\n# CONFIG_TEST_USER_COPY is not set\n# CONFIG_TEST_UUID is not set\n# CONFIG_TEST_VMALLOC is not set\n# CONFIG_TEST_XARRAY is not set\nCONFIG_TEXTSEARCH=y\n# CONFIG_TEXTSEARCH_BM is not set\n# CONFIG_TEXTSEARCH_FSM is not set\n# CONFIG_TEXTSEARCH_KMP is not set\n# CONFIG_THERMAL is not set\n# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set\n# CONFIG_THERMAL_DEFAULT_GOV_POWER_ALLOCATOR is not set\n# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set\n# CONFIG_THERMAL_EMULATION is not set\n# CONFIG_THERMAL_GOV_BANG_BANG is not set\n# CONFIG_THERMAL_GOV_FAIR_SHARE is not set\n# CONFIG_THERMAL_GOV_POWER_ALLOCATOR is not set\n# CONFIG_THERMAL_GOV_USER_SPACE is not set\n# CONFIG_THERMAL_HWMON is not set\n# CONFIG_THERMAL_MMIO is not set\n# CONFIG_THERMAL_NETLINK is not set\n# CONFIG_THERMAL_STATISTICS is not set\n# CONFIG_THERMAL_WRITABLE_TRIPS is not set\n# CONFIG_THINKPAD_ACPI is not set\nCONFIG_THIN_ARCHIVES=y\n# CONFIG_THRUSTMASTER_FF is not set\n# CONFIG_THUMB2_KERNEL is not set\n# CONFIG_THUNDERBOLT is not set\n# CONFIG_THUNDER_NIC_BGX is not set\n# CONFIG_THUNDER_NIC_PF is not set\n# CONFIG_THUNDER_NIC_RGX is not set\n# CONFIG_THUNDER_NIC_VF is not set\n# CONFIG_TICK_CPU_ACCOUNTING is not set\nCONFIG_TICK_ONESHOT=y\n# CONFIG_TIFM_CORE is not set\n# CONFIG_TIGON3 is not set\n# CONFIG_TIMB_DMA is not set\nCONFIG_TIMERFD=y\n# CONFIG_TIMERLAT_TRACER is not set\n# CONFIG_TIMER_STATS is not set\n# CONFIG_TIME_NS is not set\n# CONFIG_TINYDRM_HX8357D is not set\n# CONFIG_TINYDRM_ILI9225 is not set\n# CONFIG_TINYDRM_ILI9341 is not set\n# CONFIG_TINYDRM_ILI9486 is not set\n# CONFIG_TINYDRM_MI0283QT is not set\n# CONFIG_TINYDRM_REPAPER is not set\n# CONFIG_TINYDRM_ST7586 is not set\n# CONFIG_TINYDRM_ST7735R is not set\nCONFIG_TINY_RCU=y\n# CONFIG_TIPC is not set\n# CONFIG_TI_ADC081C is not set\n# CONFIG_TI_ADC0832 is not set\n# CONFIG_TI_ADC084S021 is not set\n# CONFIG_TI_ADC108S102 is not set\n# CONFIG_TI_ADC12138 is not set\n# CONFIG_TI_ADC128S052 is not set\n# CONFIG_TI_ADC161S626 is not set\n# CONFIG_TI_ADS1015 is not set\n# CONFIG_TI_ADS124S08 is not set\n# CONFIG_TI_ADS131E08 is not set\n# CONFIG_TI_ADS7950 is not set\n# CONFIG_TI_ADS8344 is not set\n# CONFIG_TI_ADS8688 is not set\n# CONFIG_TI_AM335X_ADC is not set\n# CONFIG_TI_CPSW is not set\n# CONFIG_TI_CPSW_ALE is not set\n# CONFIG_TI_CPSW_PHY_SEL is not set\n# CONFIG_TI_CPTS is not set\n# CONFIG_TI_DAC082S085 is not set\n# CONFIG_TI_DAC5571 is not set\n# CONFIG_TI_DAC7311 is not set\n# CONFIG_TI_DAC7512 is not set\n# CONFIG_TI_DAC7612 is not set\n# CONFIG_TI_DAVINCI_CPDMA is not set\n# CONFIG_TI_DAVINCI_MDIO is not set\n# CONFIG_TI_ST is not set\n# CONFIG_TI_SYSCON_RESET is not set\n# CONFIG_TI_TLC4541 is not set\n# CONFIG_TI_TSC2046 is not set\n# CONFIG_TLAN is not set\n# CONFIG_TLS is not set\n# CONFIG_TMD_HERMES is not set\n# CONFIG_TMP006 is not set\n# CONFIG_TMP007 is not set\n# CONFIG_TMP117 is not set\nCONFIG_TMPFS=y\n# CONFIG_TMPFS_INODE64 is not set\n# CONFIG_TMPFS_POSIX_ACL is not set\nCONFIG_TMPFS_XATTR=y\n# CONFIG_TOPSTAR_LAPTOP is not set\n# CONFIG_TORTURE_TEST is not set\n# CONFIG_TOSHIBA_HAPS is not set\n# CONFIG_TOUCHSCREEN_88PM860X is not set\n# CONFIG_TOUCHSCREEN_AD7877 is not set\n# CONFIG_TOUCHSCREEN_AD7879 is not set\n# CONFIG_TOUCHSCREEN_AD7879_I2C is not set\n# CONFIG_TOUCHSCREEN_AD7879_SPI is not set\n# CONFIG_TOUCHSCREEN_ADC is not set\n# CONFIG_TOUCHSCREEN_ADS7846 is not set\n# CONFIG_TOUCHSCREEN_AR1021_I2C is not set\n# CONFIG_TOUCHSCREEN_ATMEL_MXT is not set\n# CONFIG_TOUCHSCREEN_ATMEL_MXT_T37 is not set\n# CONFIG_TOUCHSCREEN_AUO_PIXCIR is not set\n# CONFIG_TOUCHSCREEN_BU21013 is not set\n# CONFIG_TOUCHSCREEN_BU21029 is not set\n# CONFIG_TOUCHSCREEN_CHIPONE_ICN8318 is not set\n# CONFIG_TOUCHSCREEN_CHIPONE_ICN8505 is not set\n# CONFIG_TOUCHSCREEN_COLIBRI_VF50 is not set\n# CONFIG_TOUCHSCREEN_CY8CTMA140 is not set\n# CONFIG_TOUCHSCREEN_CY8CTMG110 is not set\n# CONFIG_TOUCHSCREEN_CYTTSP4_CORE is not set\n# CONFIG_TOUCHSCREEN_CYTTSP4_I2C is not set\n# CONFIG_TOUCHSCREEN_CYTTSP4_SPI is not set\n# CONFIG_TOUCHSCREEN_CYTTSP_CORE is not set\n# CONFIG_TOUCHSCREEN_CYTTSP_I2C is not set\n# CONFIG_TOUCHSCREEN_CYTTSP_SPI is not set\n# CONFIG_TOUCHSCREEN_DA9034 is not set\n# CONFIG_TOUCHSCREEN_DA9052 is not set\n# CONFIG_TOUCHSCREEN_DYNAPRO is not set\n# CONFIG_TOUCHSCREEN_EDT_FT5X06 is not set\n# CONFIG_TOUCHSCREEN_EETI is not set\n# CONFIG_TOUCHSCREEN_EGALAX is not set\n# CONFIG_TOUCHSCREEN_EGALAX_SERIAL is not set\n# CONFIG_TOUCHSCREEN_EKTF2127 is not set\n# CONFIG_TOUCHSCREEN_ELAN is not set\n# CONFIG_TOUCHSCREEN_ELO is not set\n# CONFIG_TOUCHSCREEN_EXC3000 is not set\n# CONFIG_TOUCHSCREEN_FUJITSU is not set\n# CONFIG_TOUCHSCREEN_GOODIX is not set\n# CONFIG_TOUCHSCREEN_GUNZE is not set\n# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set\n# CONFIG_TOUCHSCREEN_HIDEEP is not set\n# CONFIG_TOUCHSCREEN_HP600 is not set\n# CONFIG_TOUCHSCREEN_HP7XX is not set\n# CONFIG_TOUCHSCREEN_HTCPEN is not set\n# CONFIG_TOUCHSCREEN_HYCON_HY46XX is not set\n# CONFIG_TOUCHSCREEN_ILI210X is not set\n# CONFIG_TOUCHSCREEN_ILITEK is not set\n# CONFIG_TOUCHSCREEN_IMX6UL_TSC is not set\n# CONFIG_TOUCHSCREEN_INEXIO is not set\n# CONFIG_TOUCHSCREEN_IPAQ_MICRO is not set\n# CONFIG_TOUCHSCREEN_IPROC is not set\n# CONFIG_TOUCHSCREEN_IQS5XX is not set\n# CONFIG_TOUCHSCREEN_LPC32XX is not set\n# CONFIG_TOUCHSCREEN_MAX11801 is not set\n# CONFIG_TOUCHSCREEN_MC13783 is not set\n# CONFIG_TOUCHSCREEN_MCS5000 is not set\n# CONFIG_TOUCHSCREEN_MELFAS_MIP4 is not set\n# CONFIG_TOUCHSCREEN_MIGOR is not set\n# CONFIG_TOUCHSCREEN_MK712 is not set\n# CONFIG_TOUCHSCREEN_MMS114 is not set\n# CONFIG_TOUCHSCREEN_MSG2638 is not set\n# CONFIG_TOUCHSCREEN_MTOUCH is not set\n# CONFIG_TOUCHSCREEN_MX25 is not set\n# CONFIG_TOUCHSCREEN_MXS_LRADC is not set\n# CONFIG_TOUCHSCREEN_PCAP is not set\n# CONFIG_TOUCHSCREEN_PENMOUNT is not set\n# CONFIG_TOUCHSCREEN_PIXCIR is not set\n# CONFIG_TOUCHSCREEN_PROPERTIES is not set\n# CONFIG_TOUCHSCREEN_RASPBERRYPI_FW is not set\n# CONFIG_TOUCHSCREEN_RM_TS is not set\n# CONFIG_TOUCHSCREEN_ROHM_BU21023 is not set\n# CONFIG_TOUCHSCREEN_RPI_FT5406 is not set\n# CONFIG_TOUCHSCREEN_S3C2410 is not set\n# CONFIG_TOUCHSCREEN_S6SY761 is not set\n# CONFIG_TOUCHSCREEN_SILEAD is not set\n# CONFIG_TOUCHSCREEN_SIS_I2C is not set\n# CONFIG_TOUCHSCREEN_ST1232 is not set\n# CONFIG_TOUCHSCREEN_STMFTS is not set\n# CONFIG_TOUCHSCREEN_STMPE is not set\n# CONFIG_TOUCHSCREEN_SUN4I is not set\n# CONFIG_TOUCHSCREEN_SUR40 is not set\n# CONFIG_TOUCHSCREEN_SURFACE3_SPI is not set\n# CONFIG_TOUCHSCREEN_SX8654 is not set\n# CONFIG_TOUCHSCREEN_TI_AM335X_TSC is not set\n# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set\n# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set\n# CONFIG_TOUCHSCREEN_TOUCHWIN is not set\n# CONFIG_TOUCHSCREEN_TPS6507X is not set\n# CONFIG_TOUCHSCREEN_TS4800 is not set\n# CONFIG_TOUCHSCREEN_TSC2004 is not set\n# CONFIG_TOUCHSCREEN_TSC2005 is not set\n# CONFIG_TOUCHSCREEN_TSC2007 is not set\n# CONFIG_TOUCHSCREEN_TSC2007_IIO is not set\n# CONFIG_TOUCHSCREEN_TSC200X_CORE is not set\n# CONFIG_TOUCHSCREEN_TSC_SERIO is not set\n# CONFIG_TOUCHSCREEN_UCB1400 is not set\n# CONFIG_TOUCHSCREEN_USB_3M is not set\n# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set\n# CONFIG_TOUCHSCREEN_USB_DMC_TSC10 is not set\n# CONFIG_TOUCHSCREEN_USB_E2I is not set\n# CONFIG_TOUCHSCREEN_USB_EASYTOUCH is not set\n# CONFIG_TOUCHSCREEN_USB_EGALAX is not set\n# CONFIG_TOUCHSCREEN_USB_ELO is not set\n# CONFIG_TOUCHSCREEN_USB_ETT_TC45USB is not set\n# CONFIG_TOUCHSCREEN_USB_ETURBO is not set\n# CONFIG_TOUCHSCREEN_USB_GENERAL_TOUCH is not set\n# CONFIG_TOUCHSCREEN_USB_GOTOP is not set\n# CONFIG_TOUCHSCREEN_USB_GUNZE is not set\n# CONFIG_TOUCHSCREEN_USB_IDEALTEK is not set\n# CONFIG_TOUCHSCREEN_USB_IRTOUCH is not set\n# CONFIG_TOUCHSCREEN_USB_ITM is not set\n# CONFIG_TOUCHSCREEN_USB_JASTEC is not set\n# CONFIG_TOUCHSCREEN_USB_NEXIO is not set\n# CONFIG_TOUCHSCREEN_USB_PANJIT is not set\n# CONFIG_TOUCHSCREEN_USB_ZYTRONIC is not set\n# CONFIG_TOUCHSCREEN_W90X900 is not set\n# CONFIG_TOUCHSCREEN_WACOM_I2C is not set\n# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set\n# CONFIG_TOUCHSCREEN_WDT87XX_I2C is not set\n# CONFIG_TOUCHSCREEN_WM831X is not set\n# CONFIG_TOUCHSCREEN_WM9705 is not set\n# CONFIG_TOUCHSCREEN_WM9712 is not set\n# CONFIG_TOUCHSCREEN_WM9713 is not set\n# CONFIG_TOUCHSCREEN_WM97XX is not set\n# CONFIG_TOUCHSCREEN_WM97XX_MAINSTONE is not set\n# CONFIG_TOUCHSCREEN_WM97XX_ZYLONITE is not set\n# CONFIG_TOUCHSCREEN_ZET6223 is not set\n# CONFIG_TOUCHSCREEN_ZFORCE is not set\n# CONFIG_TOUCHSCREEN_ZINITIX is not set\n# CONFIG_TPL0102 is not set\n# CONFIG_TPS6105X is not set\n# CONFIG_TPS65010 is not set\n# CONFIG_TPS6507X is not set\n# CONFIG_TRACEPOINT_BENCHMARK is not set\n# CONFIG_TRACER_SNAPSHOT is not set\n# CONFIG_TRACER_SNAPSHOT_PER_CPU_SWAP is not set\n# CONFIG_TRACE_BRANCH_PROFILING is not set\n# CONFIG_TRACE_EVAL_MAP_FILE is not set\n# CONFIG_TRACE_EVENT_INJECT is not set\nCONFIG_TRACE_IRQFLAGS_SUPPORT=y\n# CONFIG_TRACE_SINK is not set\n# CONFIG_TRACING_EVENTS_GPIO is not set\nCONFIG_TRACING_SUPPORT=y\nCONFIG_TRAD_SIGNALS=y\n# CONFIG_TRANSPARENT_HUGEPAGE is not set\n# CONFIG_TREE_RCU is not set\n# CONFIG_TREE_RCU_TRACE is not set\n# CONFIG_TRIM_UNUSED_KSYMS is not set\n# CONFIG_TRUSTED_FOUNDATIONS is not set\n# CONFIG_TRUSTED_KEYS is not set\n# CONFIG_TSL2583 is not set\n# CONFIG_TSL2591 is not set\n# CONFIG_TSL2772 is not set\n# CONFIG_TSL2x7x is not set\n# CONFIG_TSL4531 is not set\n# CONFIG_TSYS01 is not set\n# CONFIG_TSYS02D is not set\n# CONFIG_TTPCI_EEPROM is not set\nCONFIG_TTY=y\n# CONFIG_TTY_PRINTK is not set\n# CONFIG_TUN is not set\n# CONFIG_TUN_VNET_CROSS_LE is not set\n# CONFIG_TWL4030_CORE is not set\n# CONFIG_TWL4030_MADC is not set\n# CONFIG_TWL6030_GPADC is not set\n# CONFIG_TWL6040_CORE is not set\n# CONFIG_TYPEC is not set\n# CONFIG_TYPEC_TCPM is not set\n# CONFIG_TYPEC_UCSI is not set\n# CONFIG_TYPHOON is not set\n# CONFIG_UACCESS_WITH_MEMCPY is not set\n# CONFIG_UBIFS_ATIME_SUPPORT is not set\n# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set\n# CONFIG_UBIFS_FS_AUTHENTICATION is not set\n# CONFIG_UBIFS_FS_ENCRYPTION is not set\nCONFIG_UBIFS_FS_LZO=y\n# CONFIG_UBIFS_FS_SECURITY is not set\nCONFIG_UBIFS_FS_XATTR=y\nCONFIG_UBIFS_FS_ZLIB=y\nCONFIG_UBIFS_FS_ZSTD=y\n# CONFIG_UBSAN is not set\nCONFIG_UBSAN_ALIGNMENT=y\n# CONFIG_UBSAN_MISC is not set\n# CONFIG_UCB1400_CORE is not set\n# CONFIG_UCSI is not set\n# CONFIG_UDF_FS is not set\n# CONFIG_UDMABUF is not set\nCONFIG_UEVENT_HELPER=y\nCONFIG_UEVENT_HELPER_PATH=\"/sbin/hotplug\"\n# CONFIG_UFS_FS is not set\n# CONFIG_UHID is not set\nCONFIG_UID16=y\n# CONFIG_UIO is not set\n# CONFIG_ULTRA is not set\n# CONFIG_ULTRIX_PARTITION is not set\n# CONFIG_UNICODE is not set\n# CONFIG_UNISYSSPAR is not set\n# CONFIG_UNISYS_VISORBUS is not set\nCONFIG_UNIX=y\nCONFIG_UNIX98_PTYS=y\n# CONFIG_UNIXWARE_DISKLABEL is not set\n# CONFIG_UNIX_DIAG is not set\nCONFIG_UNIX_SCM=y\n# CONFIG_UNUSED_SYMBOLS is not set\n# CONFIG_UNWINDER_FRAME_POINTER is not set\n# CONFIG_UPROBES is not set\n# CONFIG_UPROBE_EVENTS is not set\n# CONFIG_US5182D is not set\n# CONFIG_USB is not set\n# CONFIG_USB4 is not set\n# CONFIG_USBIP_CORE is not set\nCONFIG_USBIP_VHCI_HC_PORTS=8\nCONFIG_USBIP_VHCI_NR_HCS=1\n# CONFIG_USBIP_VUDC is not set\n# CONFIG_USBPCWATCHDOG is not set\n# CONFIG_USB_ACM is not set\n# CONFIG_USB_ADUTUX is not set\n# CONFIG_USB_AIRSPY is not set\nCONFIG_USB_ALI_M5632=y\n# CONFIG_USB_AMD5536UDC is not set\nCONFIG_USB_AN2720=y\n# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set\n# CONFIG_USB_APPLEDISPLAY is not set\nCONFIG_USB_ARCH_HAS_HCD=y\nCONFIG_USB_ARMLINUX=y\n# CONFIG_USB_ATM is not set\n# CONFIG_USB_AUDIO is not set\nCONFIG_USB_AUTOSUSPEND_DELAY=2\n# CONFIG_USB_BDC_UDC is not set\nCONFIG_USB_BELKIN=y\n# CONFIG_USB_C67X00_HCD is not set\n# CONFIG_USB_CATC is not set\n# CONFIG_USB_CDC_COMPOSITE is not set\n# CONFIG_USB_CDNS3 is not set\n# CONFIG_USB_CDNS_SUPPORT is not set\n# CONFIG_USB_CHAOSKEY is not set\n# CONFIG_USB_CHIPIDEA is not set\n# CONFIG_USB_CHIPIDEA_GENERIC is not set\n# CONFIG_USB_CHIPIDEA_IMX is not set\n# CONFIG_USB_CHIPIDEA_MSM is not set\n# CONFIG_USB_CHIPIDEA_PCI is not set\n# CONFIG_USB_CHIPIDEA_TEGRA is not set\n# CONFIG_USB_CONFIGFS is not set\n# CONFIG_USB_CONN_GPIO is not set\n# CONFIG_USB_CXACRU is not set\n# CONFIG_USB_CYPRESS_CY7C63 is not set\n# CONFIG_USB_CYTHERM is not set\nCONFIG_USB_DEFAULT_PERSIST=y\n# CONFIG_USB_DSBR is not set\n# CONFIG_USB_DUMMY_HCD is not set\n# CONFIG_USB_DWC2 is not set\n# CONFIG_USB_DWC2_DEBUG is not set\n# CONFIG_USB_DWC2_DUAL_ROLE is not set\n# CONFIG_USB_DWC2_HOST is not set\n# CONFIG_USB_DWC2_PERIPHERAL is not set\n# CONFIG_USB_DWC2_TRACK_MISSED_SOFS is not set\n# CONFIG_USB_DWC3 is not set\n# CONFIG_USB_DWC3_EXYNOS is not set\n# CONFIG_USB_DWC3_HAPS is not set\n# CONFIG_USB_DWC3_KEYSTONE is not set\n# CONFIG_USB_DWC3_OF_SIMPLE is not set\n# CONFIG_USB_DWC3_PCI is not set\n# CONFIG_USB_DWC3_QCOM is not set\n# CONFIG_USB_DWC3_ULPI is not set\n# CONFIG_USB_DYNAMIC_MINORS is not set\n# CONFIG_USB_EG20T is not set\n# CONFIG_USB_EHCI_ATH79 is not set\n# CONFIG_USB_EHCI_FSL is not set\n# CONFIG_USB_EHCI_HCD is not set\n# CONFIG_USB_EHCI_HCD_AT91 is not set\n# CONFIG_USB_EHCI_HCD_OMAP is not set\n# CONFIG_USB_EHCI_HCD_PPC_OF is not set\n# CONFIG_USB_EHCI_MSM is not set\n# CONFIG_USB_EHCI_MV is not set\nCONFIG_USB_EHCI_ROOT_HUB_TT=y\nCONFIG_USB_EHCI_TT_NEWSCHED=y\n# CONFIG_USB_EHSET_TEST_FIXTURE is not set\n# CONFIG_USB_EMI26 is not set\n# CONFIG_USB_EMI62 is not set\n# CONFIG_USB_EPSON2888 is not set\n# CONFIG_USB_ETH is not set\n# CONFIG_USB_EZUSB_FX2 is not set\n# CONFIG_USB_FEW_INIT_RETRIES is not set\n# CONFIG_USB_FOTG210_HCD is not set\n# CONFIG_USB_FOTG210_UDC is not set\n# CONFIG_USB_FSL_USB2 is not set\n# CONFIG_USB_FTDI_ELAN is not set\n# CONFIG_USB_FUNCTIONFS is not set\n# CONFIG_USB_FUSB300 is not set\n# CONFIG_USB_GADGET is not set\n# CONFIG_USB_GADGETFS is not set\n# CONFIG_USB_GADGET_DEBUG is not set\n# CONFIG_USB_GADGET_DEBUG_FILES is not set\n# CONFIG_USB_GADGET_DEBUG_FS is not set\nCONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2\nCONFIG_USB_GADGET_VBUS_DRAW=2\n# CONFIG_USB_GADGET_XILINX is not set\n# CONFIG_USB_GL860 is not set\n# CONFIG_USB_GOKU is not set\n# CONFIG_USB_GPIO_VBUS is not set\n# CONFIG_USB_GR_UDC is not set\n# CONFIG_USB_GSPCA is not set\n# CONFIG_USB_GSPCA_BENQ is not set\n# CONFIG_USB_GSPCA_CONEX is not set\n# CONFIG_USB_GSPCA_CPIA1 is not set\n# CONFIG_USB_GSPCA_DTCS033 is not set\n# CONFIG_USB_GSPCA_ETOMS is not set\n# CONFIG_USB_GSPCA_FINEPIX is not set\n# CONFIG_USB_GSPCA_JEILINJ is not set\n# CONFIG_USB_GSPCA_JL2005BCD is not set\n# CONFIG_USB_GSPCA_KINECT is not set\n# CONFIG_USB_GSPCA_KONICA is not set\n# CONFIG_USB_GSPCA_MARS is not set\n# CONFIG_USB_GSPCA_MR97310A is not set\n# CONFIG_USB_GSPCA_NW80X is not set\n# CONFIG_USB_GSPCA_OV519 is not set\n# CONFIG_USB_GSPCA_OV534 is not set\n# CONFIG_USB_GSPCA_OV534_9 is not set\n# CONFIG_USB_GSPCA_PAC207 is not set\n# CONFIG_USB_GSPCA_PAC7302 is not set\n# CONFIG_USB_GSPCA_PAC7311 is not set\n# CONFIG_USB_GSPCA_SE401 is not set\n# CONFIG_USB_GSPCA_SN9C2028 is not set\n# CONFIG_USB_GSPCA_SN9C20X is not set\n# CONFIG_USB_GSPCA_SONIXB is not set\n# CONFIG_USB_GSPCA_SONIXJ is not set\n# CONFIG_USB_GSPCA_SPCA1528 is not set\n# CONFIG_USB_GSPCA_SPCA500 is not set\n# CONFIG_USB_GSPCA_SPCA501 is not set\n# CONFIG_USB_GSPCA_SPCA505 is not set\n# CONFIG_USB_GSPCA_SPCA506 is not set\n# CONFIG_USB_GSPCA_SPCA508 is not set\n# CONFIG_USB_GSPCA_SPCA561 is not set\n# CONFIG_USB_GSPCA_SQ905 is not set\n# CONFIG_USB_GSPCA_SQ905C is not set\n# CONFIG_USB_GSPCA_SQ930X is not set\n# CONFIG_USB_GSPCA_STK014 is not set\n# CONFIG_USB_GSPCA_STK1135 is not set\n# CONFIG_USB_GSPCA_STV0680 is not set\n# CONFIG_USB_GSPCA_SUNPLUS is not set\n# CONFIG_USB_GSPCA_T613 is not set\n# CONFIG_USB_GSPCA_TOPRO is not set\n# CONFIG_USB_GSPCA_TOUPTEK is not set\n# CONFIG_USB_GSPCA_TV8532 is not set\n# CONFIG_USB_GSPCA_VC032X is not set\n# CONFIG_USB_GSPCA_VICAM is not set\n# CONFIG_USB_GSPCA_XIRLINK_CIT is not set\n# CONFIG_USB_GSPCA_ZC3XX is not set\n# CONFIG_USB_G_ACM_MS is not set\n# CONFIG_USB_G_DBGP is not set\n# CONFIG_USB_G_HID is not set\n# CONFIG_USB_G_MULTI is not set\n# CONFIG_USB_G_NCM is not set\n# CONFIG_USB_G_NOKIA is not set\n# CONFIG_USB_G_PRINTER is not set\n# CONFIG_USB_G_SERIAL is not set\n# CONFIG_USB_G_WEBCAM is not set\n# CONFIG_USB_HACKRF is not set\n# CONFIG_USB_HCD_TEST_MODE is not set\n# CONFIG_USB_HID is not set\n# CONFIG_USB_HIDDEV is not set\n# CONFIG_USB_HSIC_USB3503 is not set\n# CONFIG_USB_HSIC_USB4604 is not set\n# CONFIG_USB_HSO is not set\n# CONFIG_USB_HUB_USB251XB is not set\n# CONFIG_USB_HWA_HCD is not set\n# CONFIG_USB_IDMOUSE is not set\n# CONFIG_USB_IMX21_HCD is not set\n# CONFIG_USB_IOWARRIOR is not set\n# CONFIG_USB_IPHETH is not set\n# CONFIG_USB_ISIGHTFW is not set\n# CONFIG_USB_ISP116X_HCD is not set\n# CONFIG_USB_ISP1301 is not set\n# CONFIG_USB_ISP1362_HCD is not set\n# CONFIG_USB_ISP1760 is not set\n# CONFIG_USB_ISP1760_HCD is not set\n# CONFIG_USB_KAWETH is not set\n# CONFIG_USB_KBD is not set\n# CONFIG_USB_KC2190 is not set\n# CONFIG_USB_LAN78XX is not set\n# CONFIG_USB_LCD is not set\n# CONFIG_USB_LD is not set\n# CONFIG_USB_LED is not set\n# CONFIG_USB_LEDS_TRIGGER_USBPORT is not set\n# CONFIG_USB_LED_TRIG is not set\n# CONFIG_USB_LEGOTOWER is not set\n# CONFIG_USB_LGM_PHY is not set\n# CONFIG_USB_LINK_LAYER_TEST is not set\n# CONFIG_USB_M5602 is not set\n# CONFIG_USB_M66592 is not set\n# CONFIG_USB_MASS_STORAGE is not set\n# CONFIG_USB_MAX3420_UDC is not set\n# CONFIG_USB_MAX3421_HCD is not set\n# CONFIG_USB_MDC800 is not set\n# CONFIG_USB_MICROTEK is not set\n# CONFIG_USB_MIDI_GADGET is not set\n# CONFIG_USB_MON is not set\n# CONFIG_USB_MOUSE is not set\n# CONFIG_USB_MSI2500 is not set\n# CONFIG_USB_MSM_OTG is not set\n# CONFIG_USB_MTU3 is not set\n# CONFIG_USB_MUSB_GADGET is not set\n# CONFIG_USB_MUSB_HDRC is not set\n# CONFIG_USB_MUSB_HOST is not set\n# CONFIG_USB_MV_U3D is not set\n# CONFIG_USB_MV_UDC is not set\n# CONFIG_USB_MXS_PHY is not set\n# CONFIG_USB_NET2272 is not set\n# CONFIG_USB_NET2280 is not set\n# CONFIG_USB_NET_AQC111 is not set\n# CONFIG_USB_NET_AX88179_178A is not set\n# CONFIG_USB_NET_AX8817X is not set\n# CONFIG_USB_NET_CDCETHER is not set\n# CONFIG_USB_NET_CDC_EEM is not set\n# CONFIG_USB_NET_CDC_MBIM is not set\n# CONFIG_USB_NET_CDC_NCM is not set\n# CONFIG_USB_NET_CDC_SUBSET is not set\n# CONFIG_USB_NET_CH9200 is not set\n# CONFIG_USB_NET_CX82310_ETH is not set\n# CONFIG_USB_NET_DM9601 is not set\n# CONFIG_USB_NET_DRIVERS is not set\n# CONFIG_USB_NET_GL620A is not set\n# CONFIG_USB_NET_HUAWEI_CDC_NCM is not set\n# CONFIG_USB_NET_INT51X1 is not set\n# CONFIG_USB_NET_KALMIA is not set\n# CONFIG_USB_NET_MCS7830 is not set\n# CONFIG_USB_NET_NET1080 is not set\n# CONFIG_USB_NET_PLUSB is not set\n# CONFIG_USB_NET_QMI_WWAN is not set\n# CONFIG_USB_NET_RNDIS_HOST is not set\n# CONFIG_USB_NET_RNDIS_WLAN is not set\n# CONFIG_USB_NET_SMSC75XX is not set\n# CONFIG_USB_NET_SMSC95XX is not set\n# CONFIG_USB_NET_SR9700 is not set\n# CONFIG_USB_NET_SR9800 is not set\n# CONFIG_USB_NET_ZAURUS is not set\n# CONFIG_USB_OHCI_HCD is not set\n# CONFIG_USB_OHCI_HCD_PCI is not set\n# CONFIG_USB_OHCI_HCD_PPC_OF is not set\n# CONFIG_USB_OHCI_HCD_PPC_OF_BE is not set\n# CONFIG_USB_OHCI_HCD_PPC_OF_LE is not set\n# CONFIG_USB_OHCI_HCD_SSB is not set\nCONFIG_USB_OHCI_LITTLE_ENDIAN=y\n# CONFIG_USB_OTG is not set\n# CONFIG_USB_OTG_BLACKLIST_HUB is not set\n# CONFIG_USB_OTG_DISABLE_EXTERNAL_HUB is not set\n# CONFIG_USB_OTG_FSM is not set\n# CONFIG_USB_OTG_PRODUCTLIST is not set\n# CONFIG_USB_OTG_WHITELIST is not set\n# CONFIG_USB_OXU210HP_HCD is not set\n# CONFIG_USB_PCI is not set\n# CONFIG_USB_PEGASUS is not set\n# CONFIG_USB_PHY is not set\n# CONFIG_USB_PRINTER is not set\n# CONFIG_USB_PWC_INPUT_EVDEV is not set\n# CONFIG_USB_PXA27X is not set\n# CONFIG_USB_R8A66597 is not set\n# CONFIG_USB_R8A66597_HCD is not set\n# CONFIG_USB_RAW_GADGET is not set\n# CONFIG_USB_RCAR_PHY is not set\n# CONFIG_USB_RENESAS_USBHS is not set\n# CONFIG_USB_RIO500 is not set\n# CONFIG_USB_ROLES_INTEL_XHCI is not set\n# CONFIG_USB_ROLE_SWITCH is not set\n# CONFIG_USB_RTL8150 is not set\n# CONFIG_USB_RTL8152 is not set\n# CONFIG_USB_RTL8153_ECM is not set\n# CONFIG_USB_S2255 is not set\n# CONFIG_USB_SERIAL is not set\n# CONFIG_USB_SERIAL_AIRCABLE is not set\n# CONFIG_USB_SERIAL_ARK3116 is not set\n# CONFIG_USB_SERIAL_BELKIN is not set\n# CONFIG_USB_SERIAL_CH341 is not set\n# CONFIG_USB_SERIAL_CP210X is not set\n# CONFIG_USB_SERIAL_CYBERJACK is not set\n# CONFIG_USB_SERIAL_CYPRESS_M8 is not set\n# CONFIG_USB_SERIAL_DEBUG is not set\n# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set\n# CONFIG_USB_SERIAL_EDGEPORT is not set\n# CONFIG_USB_SERIAL_EDGEPORT_TI is not set\n# CONFIG_USB_SERIAL_EMPEG is not set\n# CONFIG_USB_SERIAL_F81232 is not set\n# CONFIG_USB_SERIAL_F8153X is not set\n# CONFIG_USB_SERIAL_FTDI_SIO is not set\n# CONFIG_USB_SERIAL_GARMIN is not set\nCONFIG_USB_SERIAL_GENERIC=y\n# CONFIG_USB_SERIAL_IPAQ is not set\n# CONFIG_USB_SERIAL_IPW is not set\n# CONFIG_USB_SERIAL_IR is not set\n# CONFIG_USB_SERIAL_IUU is not set\n# CONFIG_USB_SERIAL_KEYSPAN is not set\nCONFIG_USB_SERIAL_KEYSPAN_MPR=y\n# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set\nCONFIG_USB_SERIAL_KEYSPAN_USA18X=y\nCONFIG_USB_SERIAL_KEYSPAN_USA19=y\nCONFIG_USB_SERIAL_KEYSPAN_USA19QI=y\nCONFIG_USB_SERIAL_KEYSPAN_USA19QW=y\nCONFIG_USB_SERIAL_KEYSPAN_USA19W=y\nCONFIG_USB_SERIAL_KEYSPAN_USA28=y\nCONFIG_USB_SERIAL_KEYSPAN_USA28X=y\nCONFIG_USB_SERIAL_KEYSPAN_USA28XA=y\nCONFIG_USB_SERIAL_KEYSPAN_USA28XB=y\nCONFIG_USB_SERIAL_KEYSPAN_USA49W=y\nCONFIG_USB_SERIAL_KEYSPAN_USA49WLC=y\n# CONFIG_USB_SERIAL_KLSI is not set\n# CONFIG_USB_SERIAL_KOBIL_SCT is not set\n# CONFIG_USB_SERIAL_MCT_U232 is not set\n# CONFIG_USB_SERIAL_METRO is not set\n# CONFIG_USB_SERIAL_MOS7715_PARPORT is not set\n# CONFIG_USB_SERIAL_MOS7720 is not set\n# CONFIG_USB_SERIAL_MOS7840 is not set\n# CONFIG_USB_SERIAL_MXUPORT is not set\n# CONFIG_USB_SERIAL_NAVMAN is not set\n# CONFIG_USB_SERIAL_OMNINET is not set\n# CONFIG_USB_SERIAL_OPTICON is not set\n# CONFIG_USB_SERIAL_OPTION is not set\n# CONFIG_USB_SERIAL_OTI6858 is not set\n# CONFIG_USB_SERIAL_PL2303 is not set\n# CONFIG_USB_SERIAL_QCAUX is not set\n# CONFIG_USB_SERIAL_QT2 is not set\n# CONFIG_USB_SERIAL_QUALCOMM is not set\n# CONFIG_USB_SERIAL_SAFE is not set\nCONFIG_USB_SERIAL_SAFE_PADDED=y\n# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set\n# CONFIG_USB_SERIAL_SIMPLE is not set\n# CONFIG_USB_SERIAL_SPCP8X5 is not set\n# CONFIG_USB_SERIAL_SSU100 is not set\n# CONFIG_USB_SERIAL_SYMBOL is not set\n# CONFIG_USB_SERIAL_TI is not set\n# CONFIG_USB_SERIAL_UPD78F0730 is not set\n# CONFIG_USB_SERIAL_VISOR is not set\n# CONFIG_USB_SERIAL_WHITEHEAT is not set\n# CONFIG_USB_SERIAL_WISHBONE is not set\n# CONFIG_USB_SERIAL_XIRCOM is not set\n# CONFIG_USB_SERIAL_XR is not set\n# CONFIG_USB_SERIAL_XSENS_MT is not set\n# CONFIG_USB_SEVSEG is not set\n# CONFIG_USB_SIERRA_NET is not set\n# CONFIG_USB_SISUSBVGA is not set\n# CONFIG_USB_SL811_HCD is not set\n# CONFIG_USB_SNP_UDC_PLAT is not set\n# CONFIG_USB_SPEEDTOUCH is not set\n# CONFIG_USB_STKWEBCAM is not set\n# CONFIG_USB_STORAGE is not set\n# CONFIG_USB_STORAGE_ALAUDA is not set\n# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set\n# CONFIG_USB_STORAGE_DATAFAB is not set\n# CONFIG_USB_STORAGE_DEBUG is not set\n# CONFIG_USB_STORAGE_ENE_UB6250 is not set\n# CONFIG_USB_STORAGE_FREECOM is not set\n# CONFIG_USB_STORAGE_ISD200 is not set\n# CONFIG_USB_STORAGE_JUMPSHOT is not set\n# CONFIG_USB_STORAGE_KARMA is not set\n# CONFIG_USB_STORAGE_ONETOUCH is not set\n# CONFIG_USB_STORAGE_REALTEK is not set\n# CONFIG_USB_STORAGE_SDDR09 is not set\n# CONFIG_USB_STORAGE_SDDR55 is not set\n# CONFIG_USB_STORAGE_USBAT is not set\n# CONFIG_USB_STV06XX is not set\n# CONFIG_USB_SUPPORT is not set\n# CONFIG_USB_SWITCH_FSA9480 is not set\n# CONFIG_USB_TEST is not set\n# CONFIG_USB_TMC is not set\n# CONFIG_USB_TRANCEVIBRATOR is not set\n# CONFIG_USB_UAS is not set\n# CONFIG_USB_UEAGLEATM is not set\n# CONFIG_USB_ULPI is not set\n# CONFIG_USB_ULPI_BUS is not set\n# CONFIG_USB_USBNET is not set\n# CONFIG_USB_USS720 is not set\n# CONFIG_USB_VIDEO_CLASS is not set\nCONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y\n# CONFIG_USB_VL600 is not set\n# CONFIG_USB_WDM is not set\n# CONFIG_USB_WHCI_HCD is not set\n# CONFIG_USB_WUSB is not set\n# CONFIG_USB_WUSB_CBAF is not set\n# CONFIG_USB_XHCI_DBGCAP is not set\n# CONFIG_USB_XHCI_HCD is not set\n# CONFIG_USB_XHCI_MVEBU is not set\n# CONFIG_USB_XHCI_PCI_RENESAS is not set\n# CONFIG_USB_XUSBATM is not set\n# CONFIG_USB_YUREX is not set\n# CONFIG_USB_ZD1201 is not set\n# CONFIG_USB_ZERO is not set\n# CONFIG_USB_ZR364XX is not set\n# CONFIG_USELIB is not set\n# CONFIG_USERFAULTFD is not set\n# CONFIG_USERIO is not set\n# CONFIG_USE_OF is not set\n# CONFIG_UTS_NS is not set\n# CONFIG_UWB is not set\n# CONFIG_U_SERIAL_CONSOLE is not set\n# CONFIG_V4L_MEM2MEM_DRIVERS is not set\n# CONFIG_V4L_PLATFORM_DRIVERS is not set\n# CONFIG_V4L_TEST_DRIVERS is not set\n# CONFIG_VALIDATE_FS_PARSER is not set\n# CONFIG_VBOXGUEST is not set\n# CONFIG_VCNL3020 is not set\n# CONFIG_VCNL4000 is not set\n# CONFIG_VCNL4035 is not set\n# CONFIG_VDPA is not set\nCONFIG_VDSO=y\n# CONFIG_VEML6030 is not set\n# CONFIG_VEML6070 is not set\n# CONFIG_VETH is not set\n# CONFIG_VEXPRESS_CONFIG is not set\n# CONFIG_VF610_ADC is not set\n# CONFIG_VF610_DAC is not set\n# CONFIG_VFAT_FS is not set\n# CONFIG_VFIO is not set\n# CONFIG_VGASTATE is not set\n# CONFIG_VGA_ARB is not set\n# CONFIG_VGA_CONSOLE is not set\n# CONFIG_VGA_SWITCHEROO is not set\n# CONFIG_VHOST_CROSS_ENDIAN_LEGACY is not set\nCONFIG_VHOST_MENU=y\n# CONFIG_VHOST_NET is not set\n# CONFIG_VHOST_VSOCK is not set\n# CONFIG_VIA_RHINE is not set\n# CONFIG_VIA_VELOCITY is not set\n# CONFIG_VIDEO_AD5820 is not set\n# CONFIG_VIDEO_AD9389B is not set\n# CONFIG_VIDEO_ADP1653 is not set\n# CONFIG_VIDEO_ADV7170 is not set\n# CONFIG_VIDEO_ADV7175 is not set\n# CONFIG_VIDEO_ADV7180 is not set\n# CONFIG_VIDEO_ADV7183 is not set\n# CONFIG_VIDEO_ADV7343 is not set\n# CONFIG_VIDEO_ADV7393 is not set\n# CONFIG_VIDEO_ADV748X is not set\n# CONFIG_VIDEO_ADV7511 is not set\n# CONFIG_VIDEO_ADV7604 is not set\n# CONFIG_VIDEO_ADV7842 is not set\n# CONFIG_VIDEO_ADV_DEBUG is not set\n# CONFIG_VIDEO_AK7375 is not set\n# CONFIG_VIDEO_AK881X is not set\n# CONFIG_VIDEO_AM437X_VPFE is not set\n# CONFIG_VIDEO_ASPEED is not set\n# CONFIG_VIDEO_ATMEL_ISC is not set\n# CONFIG_VIDEO_ATMEL_ISI is not set\n# CONFIG_VIDEO_AU0828 is not set\n# CONFIG_VIDEO_BT819 is not set\n# CONFIG_VIDEO_BT848 is not set\n# CONFIG_VIDEO_BT856 is not set\n# CONFIG_VIDEO_BT866 is not set\n# CONFIG_VIDEO_CADENCE is not set\n# CONFIG_VIDEO_CAFE_CCIC is not set\n# CONFIG_VIDEO_CCS is not set\n# CONFIG_VIDEO_CS3308 is not set\n# CONFIG_VIDEO_CS5345 is not set\n# CONFIG_VIDEO_CS53L32A is not set\n# CONFIG_VIDEO_CX231XX is not set\n# CONFIG_VIDEO_CX2341X is not set\n# CONFIG_VIDEO_CX25840 is not set\n# CONFIG_VIDEO_CX88 is not set\n# CONFIG_VIDEO_DEV is not set\n# CONFIG_VIDEO_DM6446_CCDC is not set\n# CONFIG_VIDEO_DT3155 is not set\n# CONFIG_VIDEO_DW9714 is not set\n# CONFIG_VIDEO_DW9768 is not set\n# CONFIG_VIDEO_DW9807_VCM is not set\n# CONFIG_VIDEO_EM28XX is not set\n# CONFIG_VIDEO_ET8EK8 is not set\n# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set\n# CONFIG_VIDEO_GO7007 is not set\n# CONFIG_VIDEO_GS1662 is not set\n# CONFIG_VIDEO_HDPVR is not set\n# CONFIG_VIDEO_HEXIUM_GEMINI is not set\n# CONFIG_VIDEO_HEXIUM_ORION is not set\n# CONFIG_VIDEO_HI556 is not set\n# CONFIG_VIDEO_I2C is not set\n# CONFIG_VIDEO_IMX214 is not set\n# CONFIG_VIDEO_IMX219 is not set\n# CONFIG_VIDEO_IMX258 is not set\n# CONFIG_VIDEO_IMX274 is not set\n# CONFIG_VIDEO_IMX290 is not set\n# CONFIG_VIDEO_IMX319 is not set\n# CONFIG_VIDEO_IMX334 is not set\n# CONFIG_VIDEO_IMX335 is not set\n# CONFIG_VIDEO_IMX355 is not set\n# CONFIG_VIDEO_IMX412 is not set\n# CONFIG_VIDEO_IMX477 is not set\n# CONFIG_VIDEO_IRS1125 is not set\n# CONFIG_VIDEO_IR_I2C is not set\n# CONFIG_VIDEO_IVTV is not set\n# CONFIG_VIDEO_KS0127 is not set\n# CONFIG_VIDEO_LM3560 is not set\n# CONFIG_VIDEO_LM3646 is not set\n# CONFIG_VIDEO_M52790 is not set\n# CONFIG_VIDEO_M5MOLS is not set\n# CONFIG_VIDEO_MAX9286 is not set\n# CONFIG_VIDEO_ML86V7667 is not set\n# CONFIG_VIDEO_MSP3400 is not set\n# CONFIG_VIDEO_MT9M001 is not set\n# CONFIG_VIDEO_MT9M032 is not set\n# CONFIG_VIDEO_MT9M111 is not set\n# CONFIG_VIDEO_MT9P031 is not set\n# CONFIG_VIDEO_MT9T001 is not set\n# CONFIG_VIDEO_MT9T112 is not set\n# CONFIG_VIDEO_MT9V011 is not set\n# CONFIG_VIDEO_MT9V032 is not set\n# CONFIG_VIDEO_MT9V111 is not set\n# CONFIG_VIDEO_MUX is not set\n# CONFIG_VIDEO_MXB is not set\n# CONFIG_VIDEO_NOON010PC30 is not set\n# CONFIG_VIDEO_OMAP2_VOUT is not set\n# CONFIG_VIDEO_OV02A10 is not set\n# CONFIG_VIDEO_OV13858 is not set\n# CONFIG_VIDEO_OV2640 is not set\n# CONFIG_VIDEO_OV2659 is not set\n# CONFIG_VIDEO_OV2680 is not set\n# CONFIG_VIDEO_OV2685 is not set\n# CONFIG_VIDEO_OV2740 is not set\n# CONFIG_VIDEO_OV5640 is not set\n# CONFIG_VIDEO_OV5645 is not set\n# CONFIG_VIDEO_OV5647 is not set\n# CONFIG_VIDEO_OV5648 is not set\n# CONFIG_VIDEO_OV5670 is not set\n# CONFIG_VIDEO_OV5675 is not set\n# CONFIG_VIDEO_OV5695 is not set\n# CONFIG_VIDEO_OV6650 is not set\n# CONFIG_VIDEO_OV7251 is not set\n# CONFIG_VIDEO_OV7640 is not set\n# CONFIG_VIDEO_OV7670 is not set\n# CONFIG_VIDEO_OV772X is not set\n# CONFIG_VIDEO_OV7740 is not set\n# CONFIG_VIDEO_OV8856 is not set\n# CONFIG_VIDEO_OV8865 is not set\n# CONFIG_VIDEO_OV9281 is not set\n# CONFIG_VIDEO_OV9282 is not set\n# CONFIG_VIDEO_OV9640 is not set\n# CONFIG_VIDEO_OV9650 is not set\n# CONFIG_VIDEO_OV9734 is not set\n# CONFIG_VIDEO_PVRUSB2 is not set\n# CONFIG_VIDEO_RDACM20 is not set\n# CONFIG_VIDEO_RDACM21 is not set\n# CONFIG_VIDEO_RJ54N1 is not set\n# CONFIG_VIDEO_S5C73M3 is not set\n# CONFIG_VIDEO_S5K4ECGX is not set\n# CONFIG_VIDEO_S5K5BAF is not set\n# CONFIG_VIDEO_S5K6A3 is not set\n# CONFIG_VIDEO_S5K6AA is not set\n# CONFIG_VIDEO_SAA6588 is not set\n# CONFIG_VIDEO_SAA6752HS is not set\n# CONFIG_VIDEO_SAA7110 is not set\n# CONFIG_VIDEO_SAA711X is not set\n# CONFIG_VIDEO_SAA7127 is not set\n# CONFIG_VIDEO_SAA7134 is not set\n# CONFIG_VIDEO_SAA717X is not set\n# CONFIG_VIDEO_SAA7185 is not set\n# CONFIG_VIDEO_SH_MOBILE_CEU is not set\n# CONFIG_VIDEO_SMIAPP is not set\n# CONFIG_VIDEO_SONY_BTF_MPX is not set\n# CONFIG_VIDEO_SR030PC30 is not set\n# CONFIG_VIDEO_STK1160_COMMON is not set\n# CONFIG_VIDEO_ST_MIPID02 is not set\n# CONFIG_VIDEO_TC358743 is not set\n# CONFIG_VIDEO_TDA1997X is not set\n# CONFIG_VIDEO_TDA7432 is not set\n# CONFIG_VIDEO_TDA9840 is not set\n# CONFIG_VIDEO_TEA6415C is not set\n# CONFIG_VIDEO_TEA6420 is not set\n# CONFIG_VIDEO_THS7303 is not set\n# CONFIG_VIDEO_THS8200 is not set\n# CONFIG_VIDEO_TIMBERDALE is not set\n# CONFIG_VIDEO_TLV320AIC23B is not set\n# CONFIG_VIDEO_TM6000 is not set\n# CONFIG_VIDEO_TVAUDIO is not set\n# CONFIG_VIDEO_TVP514X is not set\n# CONFIG_VIDEO_TVP5150 is not set\n# CONFIG_VIDEO_TVP7002 is not set\n# CONFIG_VIDEO_TW2804 is not set\n# CONFIG_VIDEO_TW9903 is not set\n# CONFIG_VIDEO_TW9906 is not set\n# CONFIG_VIDEO_TW9910 is not set\n# CONFIG_VIDEO_UDA1342 is not set\n# CONFIG_VIDEO_UPD64031A is not set\n# CONFIG_VIDEO_UPD64083 is not set\n# CONFIG_VIDEO_USBTV is not set\n# CONFIG_VIDEO_USBVISION is not set\n# CONFIG_VIDEO_V4L2 is not set\n# CONFIG_VIDEO_VP27SMPX is not set\n# CONFIG_VIDEO_VPX3220 is not set\n# CONFIG_VIDEO_VS6624 is not set\n# CONFIG_VIDEO_WM8739 is not set\n# CONFIG_VIDEO_WM8775 is not set\n# CONFIG_VIDEO_XILINX is not set\n# CONFIG_VIDEO_ZORAN is not set\n# CONFIG_VIRTIO_BALLOON is not set\n# CONFIG_VIRTIO_BLK_SCSI is not set\n# CONFIG_VIRTIO_CONSOLE is not set\n# CONFIG_VIRTIO_FS is not set\n# CONFIG_VIRTIO_INPUT is not set\nCONFIG_VIRTIO_MENU=y\n# CONFIG_VIRTIO_MMIO is not set\n# CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES is not set\n# CONFIG_VIRTIO_PCI is not set\n# CONFIG_VIRTUALIZATION is not set\n# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set\n# CONFIG_VIRT_DRIVERS is not set\nCONFIG_VIRT_TO_BUS=y\n# CONFIG_VITESSE_PHY is not set\n# CONFIG_VL53L0X_I2C is not set\n# CONFIG_VL6180 is not set\nCONFIG_VLAN_8021Q=y\n# CONFIG_VLAN_8021Q_GVRP is not set\n# CONFIG_VLAN_8021Q_MVRP is not set\n# CONFIG_VME_BUS is not set\n# CONFIG_VMLINUX_MAP is not set\n# CONFIG_VMSPLIT_1G is not set\n# CONFIG_VMSPLIT_2G is not set\n# CONFIG_VMSPLIT_2G_OPT is not set\nCONFIG_VMSPLIT_3G=y\n# CONFIG_VMSPLIT_3G_OPT is not set\n# CONFIG_VMWARE_PVSCSI is not set\n# CONFIG_VMXNET3 is not set\n# CONFIG_VM_EVENT_COUNTERS is not set\n# CONFIG_VOP_BUS is not set\n# CONFIG_VORTEX is not set\n# CONFIG_VSOCKETS is not set\n# CONFIG_VSOCKETS_DIAG is not set\n# CONFIG_VT is not set\n# CONFIG_VT6655 is not set\n# CONFIG_VT6656 is not set\n# CONFIG_VXFS_FS is not set\n# CONFIG_VXGE is not set\n# CONFIG_VXLAN is not set\n# CONFIG_VZ89X is not set\n# CONFIG_W1 is not set\n# CONFIG_W1_CON is not set\n# CONFIG_W1_MASTER_DS1WM is not set\n# CONFIG_W1_MASTER_DS2482 is not set\n# CONFIG_W1_MASTER_DS2490 is not set\n# CONFIG_W1_MASTER_GPIO is not set\n# CONFIG_W1_MASTER_MATROX is not set\n# CONFIG_W1_MASTER_SGI is not set\n# CONFIG_W1_SLAVE_DS2405 is not set\n# CONFIG_W1_SLAVE_DS2406 is not set\n# CONFIG_W1_SLAVE_DS2408 is not set\n# CONFIG_W1_SLAVE_DS2413 is not set\n# CONFIG_W1_SLAVE_DS2423 is not set\n# CONFIG_W1_SLAVE_DS2430 is not set\n# CONFIG_W1_SLAVE_DS2431 is not set\n# CONFIG_W1_SLAVE_DS2433 is not set\n# CONFIG_W1_SLAVE_DS2438 is not set\n# CONFIG_W1_SLAVE_DS250X is not set\n# CONFIG_W1_SLAVE_DS2780 is not set\n# CONFIG_W1_SLAVE_DS2781 is not set\n# CONFIG_W1_SLAVE_DS2805 is not set\n# CONFIG_W1_SLAVE_DS28E04 is not set\n# CONFIG_W1_SLAVE_DS28E17 is not set\n# CONFIG_W1_SLAVE_SMEM is not set\n# CONFIG_W1_SLAVE_THERM is not set\n# CONFIG_W83627HF_WDT is not set\n# CONFIG_W83877F_WDT is not set\n# CONFIG_W83977F_WDT is not set\n# CONFIG_WAN is not set\n# CONFIG_WANXL is not set\n# CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set\nCONFIG_WATCHDOG=y\n# CONFIG_WATCHDOG_CORE is not set\nCONFIG_WATCHDOG_HANDLE_BOOT_ENABLED=y\n# CONFIG_WATCHDOG_HRTIMER_PRETIMEOUT is not set\n# CONFIG_WATCHDOG_NOWAYOUT is not set\nCONFIG_WATCHDOG_OPEN_TIMEOUT=0\n# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set\n# CONFIG_WATCHDOG_SYSFS is not set\n# CONFIG_WATCH_QUEUE is not set\n# CONFIG_WD80x3 is not set\n# CONFIG_WDAT_WDT is not set\n# CONFIG_WDTPCI is not set\n# CONFIG_WERROR is not set\nCONFIG_WEXT_CORE=y\nCONFIG_WEXT_PRIV=y\nCONFIG_WEXT_PROC=y\nCONFIG_WEXT_SPY=y\nCONFIG_WILINK_PLATFORM_DATA=y\n# CONFIG_WIMAX is not set\n# CONFIG_WIREGUARD is not set\nCONFIG_WIRELESS=y\nCONFIG_WIRELESS_EXT=y\n# CONFIG_WIRELESS_WDS is not set\n# CONFIG_WIZNET_W5100 is not set\n# CONFIG_WIZNET_W5300 is not set\n# CONFIG_WL1251 is not set\n# CONFIG_WL12XX is not set\n# CONFIG_WL18XX is not set\nCONFIG_WLAN=y\n# CONFIG_WLAN_VENDOR_ADMTEK is not set\n# CONFIG_WLAN_VENDOR_ATH is not set\n# CONFIG_WLAN_VENDOR_ATMEL is not set\n# CONFIG_WLAN_VENDOR_BROADCOM is not set\n# CONFIG_WLAN_VENDOR_CISCO is not set\n# CONFIG_WLAN_VENDOR_INTEL is not set\n# CONFIG_WLAN_VENDOR_INTERSIL is not set\n# CONFIG_WLAN_VENDOR_MARVELL is not set\n# CONFIG_WLAN_VENDOR_MEDIATEK is not set\n# CONFIG_WLAN_VENDOR_MICROCHIP is not set\n# CONFIG_WLAN_VENDOR_QUANTENNA is not set\n# CONFIG_WLAN_VENDOR_RALINK is not set\n# CONFIG_WLAN_VENDOR_REALTEK is not set\n# CONFIG_WLAN_VENDOR_RSI is not set\n# CONFIG_WLAN_VENDOR_ST is not set\n# CONFIG_WLAN_VENDOR_TI is not set\n# CONFIG_WLAN_VENDOR_ZYDAS is not set\n# CONFIG_WLCORE is not set\nCONFIG_WQ_POWER_EFFICIENT_DEFAULT=y\n# CONFIG_WQ_WATCHDOG is not set\n# CONFIG_WWAN is not set\n# CONFIG_WW_MUTEX_SELFTEST is not set\n# CONFIG_X25 is not set\n# CONFIG_X509_CERTIFICATE_PARSER is not set\n# CONFIG_X86_PKG_TEMP_THERMAL is not set\nCONFIG_X86_SYSFB=y\n# CONFIG_XDP_SOCKETS is not set\n# CONFIG_XEN is not set\n# CONFIG_XEN_GRANT_DMA_ALLOC is not set\n# CONFIG_XEN_PVCALLS_FRONTEND is not set\nCONFIG_XEN_SCRUB_PAGES_DEFAULT=y\nCONFIG_XFRM=y\n# CONFIG_XFRM_INTERFACE is not set\n# CONFIG_XFRM_IPCOMP is not set\n# CONFIG_XFRM_MIGRATE is not set\n# CONFIG_XFRM_STATISTICS is not set\n# CONFIG_XFRM_SUB_POLICY is not set\n# CONFIG_XFRM_USER is not set\n# CONFIG_XFS_DEBUG is not set\n# CONFIG_XFS_FS is not set\n# CONFIG_XFS_ONLINE_SCRUB is not set\n# CONFIG_XFS_POSIX_ACL is not set\n# CONFIG_XFS_QUOTA is not set\n# CONFIG_XFS_RT is not set\n# CONFIG_XFS_SUPPORT_V4 is not set\n# CONFIG_XFS_WARN is not set\n# CONFIG_XILINX_AXI_EMAC is not set\n# CONFIG_XILINX_DMA is not set\n# CONFIG_XILINX_EMACLITE is not set\n# CONFIG_XILINX_GMII2RGMII is not set\n# CONFIG_XILINX_LL_TEMAC is not set\n# CONFIG_XILINX_SDFEC is not set\n# CONFIG_XILINX_VCU is not set\n# CONFIG_XILINX_WATCHDOG is not set\n# CONFIG_XILINX_XADC is not set\n# CONFIG_XILINX_ZYNQMP_DMA is not set\n# CONFIG_XILINX_ZYNQMP_DPDMA is not set\n# CONFIG_XILLYBUS is not set\n# CONFIG_XILLYUSB is not set\n# CONFIG_XIL_AXIS_FIFO is not set\n# CONFIG_XIP_KERNEL is not set\n# CONFIG_XMON is not set\nCONFIG_XZ_DEC=y\n# CONFIG_XZ_DEC_ARM is not set\n# CONFIG_XZ_DEC_ARMTHUMB is not set\n# CONFIG_XZ_DEC_BCJ is not set\n# CONFIG_XZ_DEC_IA64 is not set\n# CONFIG_XZ_DEC_POWERPC is not set\n# CONFIG_XZ_DEC_SPARC is not set\n# CONFIG_XZ_DEC_TEST is not set\n# CONFIG_XZ_DEC_X86 is not set\n# CONFIG_YAM is not set\n# CONFIG_YAMAHA_YAS530 is not set\n# CONFIG_YELLOWFIN is not set\n# CONFIG_YENTA is not set\n# CONFIG_YENTA_O2 is not set\n# CONFIG_YENTA_RICOH is not set\n# CONFIG_YENTA_TI is not set\n# CONFIG_YENTA_TOSHIBA is not set\n# CONFIG_ZBUD is not set\n# CONFIG_ZD1211RW is not set\n# CONFIG_ZD1211RW_DEBUG is not set\n# CONFIG_ZEROPLUS_FF is not set\n# CONFIG_ZERO_CALL_USED_REGS is not set\n# CONFIG_ZIIRAVE_WATCHDOG is not set\n# CONFIG_ZISOFS is not set\n# CONFIG_ZLIB_DEFLATE is not set\n# CONFIG_ZLIB_INFLATE is not set\nCONFIG_ZONE_DMA=y\n# CONFIG_ZOPT2201 is not set\n# CONFIG_ZPA2326 is not set\n# CONFIG_ZPOOL is not set\n# CONFIG_ZRAM is not set\n# CONFIG_ZRAM_DEF_COMP_LZ4 is not set\n# CONFIG_ZRAM_DEF_COMP_LZO is not set\n# CONFIG_ZRAM_DEF_COMP_LZORLE is not set\n# CONFIG_ZRAM_DEF_COMP_ZSTD is not set\n# CONFIG_ZRAM_MEMORY_TRACKING is not set\n# CONFIG_ZSMALLOC is not set\n# CONFIG_ZX_TDM is not set\n"
  },
  {
    "path": "target/linux/generic/config-filter",
    "content": "# CONFIG_ARM64_AS_.* is not set\n# CONFIG_ARM64_CONT_.*_SHIFT is not set\n# CONFIG_ARCH_(ENABLE|HAS|HAVE|INLINE|SUPPORTS|USE|WANT|STACKWALK)_.* is not set\n# CONFIG_AS_.* is not set\n# CONFIG_CC_(CAN|HAS|IS|VERSION)_.* is not set\nCONFIG_CLANG_VERSION=.*\n# CONFIG_GCC_VERSION is not set\n# CONFIG_HAVE_(?!(ARCH_TIMER|TCM|SMP)).* is not set\n# CONFIG_INLINE_.* is not set\n# CONFIG_LD_.* is not set\nCONFIG_LLD_VERSION=.*\nCONFIG_PLUGIN_HOSTCC=\".*\"\n# CONFIG_SET_FS is not set\n# CONFIG_TASKS_.* is not set\n"
  },
  {
    "path": "target/linux/generic/files/Documentation/devicetree/bindings/mtd/partitions/openwrt,uimage.yaml",
    "content": "# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause\n%YAML 1.2\n---\n$id: http://devicetree.org/schemas/mtd/partitions/openwrt,uimage.yaml#\n$schema: http://devicetree.org/meta-schemas/core.yaml#\n\ntitle: OpenWrt variations of U-Boot Image partitions\n\nmaintainers:\n  - Bjørn Mork <bjorn@mork.no>\n\ndescription: |\n  The image format defined by the boot loader \"Das U-Boot\" is often\n  modified or extended by device vendors. This defines a few optional\n  properties which can be used to describe such modifications.\n\n# partition.txt defines common properties, but has not yet been\n# converted to YAML\n#allOf:\n#  - $ref: ../partition.yaml#\n\nproperties:\n  compatible:\n    items:\n      - enum:\n          - openwrt,uimage\n      - const: denx,uimage\n\n  openwrt,padding:\n    description: Number of padding bytes between header and data\n    $ref: /schemas/types.yaml#/definitions/uint32\n    default: 0\n\n  openwrt,ih-magic:\n    description: U-Boot Image Header magic number.\n    $ref: /schemas/types.yaml#/definitions/uint32\n    default: 0x27051956 # IH_MAGIC\n\n  openwrt,ih-type:\n    description: U-Boot Image type\n    $ref: /schemas/types.yaml#/definitions/uint32\n    default: 2 # IH_TYPE_KERNEL\n\n  openwrt,offset:\n    description:\n      Offset between partition start and U-Boot Image in bytes\n    $ref: /schemas/types.yaml#/definitions/uint32\n    default: 0\n\n  openwrt,partition-magic:\n    description:\n      Magic number found at the start of the partition. Will only be\n      validated if both this property and openwrt,offset is non-zero\n    $ref: /schemas/types.yaml#/definitions/uint32\n    default: 0\n\nrequired:\n  - compatible\n  - reg\n\n#unevaluatedProperties: false\nadditionalProperties: false\n\nexamples:\n  - |\n    // device with non-default magic\n    partition@300000 {\n          compatible = \"openwrt,uimage\", \"denx,uimage\";\n          reg = <0x00300000 0xe80000>;\n          label = \"firmware\";\n          openwrt,ih-magic = <0x4e474520>;\n    };\n  - |\n    // device with U-Boot Image at an offset, with a partition magic value\n    partition@70000 {\n          compatible = \"openwrt,uimage\", \"denx,uimage\";\n          reg = <0x00070000 0x00790000>;\n          label = \"firmware\";\n          openwrt,offset = <20>;\n          openwrt,partition-magic = <0x43535953>;\n    };\n  - |\n    // device using a non-default image type\n    #include \"dt-bindings/mtd/partitions/uimage.h\"\n    partition@6c0000 {\n          compatible = \"openwrt,uimage\", \"denx,uimage\";\n          reg = <0x6c0000 0x1900000>;\n          label = \"firmware\";\n          openwrt,ih-magic = <0x33373033>;\n          openwrt,ih-type = <IH_TYPE_FILESYSTEM>;\n    };\n"
  },
  {
    "path": "target/linux/generic/files/Documentation/networking/adm6996.txt",
    "content": "------- \n\nADM6996FC / ADM6996M switch chip driver\n\n\n1. General information\n\n  This driver supports the FC and M models only. The ADM6996F and L are\n  completely different chips.\n  \n  Support for the FC model is extremely limited at the moment. There is no VLAN\n  support as of yet. The driver will not offer an swconfig interface for the FC\n  chip.\n \n1.1 VLAN IDs\n\n  It is possible to define 16 different VLANs. Every VLAN has an identifier, its\n  VLAN ID. It is easiest if you use at most VLAN IDs 0-15. In that case, the\n  swconfig based configuration is very straightforward. To define two VLANs with\n  IDs 4 and 5, you can invoke, for example:\n  \n      # swconfig dev ethX vlan 4 set ports '0 1t 2 5t' \n      # swconfig dev ethX vlan 5 set ports '0t 1t 5t'\n  \n  The swconfig framework will automatically invoke 'port Y set pvid Z' for every\n  port that is an untagged member of VLAN Y, setting its Primary VLAN ID. In\n  this example, ports 0 and 2 would get \"pvid 4\". The Primary VLAN ID of a port\n  is the VLAN ID associated with untagged packets coming in on that port.\n  \n  But if you wish to use VLAN IDs outside the range 0-15, this automatic\n  behaviour of the swconfig framework becomes a problem. The 16 VLANs that\n  swconfig can configure on the ADM6996 also have a \"vid\" setting. By default,\n  this is the same as the number of the VLAN entry, to make the simple behaviour\n  above possible. To still support a VLAN with a VLAN ID higher than 15\n  (presumably because you are in a network where such VLAN IDs are already in\n  use), you can change the \"vid\" setting of the VLAN to anything in the range\n  0-1023. But suppose you did the following:\n  \n      # swconfig dev ethX vlan 0 set vid 998 \n      # swconfig dev ethX vlan 0 set ports '0 2 5t'\n \n  Now the swconfig framework will issue 'port 0 set pvid 0' and 'port 2 set pvid\n  0'. But the \"pvid\" should be set to 998, so you are responsible for manually\n  fixing this!\n\n1.2 VLAN filtering\n\n  The switch is configured to apply source port filtering. This means that\n  packets are only accepted when the port the packets came in on is a member of\n  the VLAN the packet should go to.\n\n  Only membership of a VLAN is tested, it does not matter whether it is a tagged\n  or untagged membership.\n\n  For untagged packets, the destination VLAN is the Primary VLAN ID of the\n  incoming port. So if the PVID of a port is 0, but that port is not a member of\n  the VLAN with ID 0, this means that untagged packets on that port are dropped.\n  This can be used as a roundabout way of dropping untagged packets from a port,\n  a mode often referred to as \"Admit only tagged packets\".\n\n1.3 Reset\n\n  The two supported chip models do not have a sofware-initiated reset. When the\n  driver is initialised, as well as when the 'reset' swconfig option is invoked,\n  the driver will set those registers it knows about and supports to the correct\n  default value. But there are a lot of registers in the chip that the driver\n  does not support. If something changed those registers, invoking 'reset' or\n  performing a warm reboot might still leave the chip in a \"broken\" state. Only\n  a hardware reset will bring it back in the default state.\n\n2. Technical details on PHYs and the ADM6996\n\n  From the viewpoint of the Linux kernel, it is common that an Ethernet adapter\n  can be seen as a separate MAC entity and a separate PHY entity. The PHY entity\n  can be queried and set through registers accessible via an MDIO bus. A PHY\n  normally has a single address on that bus, in the range 0 through 31.\n\n  The ADM6996 has special-purpose registers in the range of PHYs 0 through 10.\n  Even though all these registers control a single ADM6996 chip, the Linux\n  kernel treats this as 11 separate PHYs.  The driver will bind to these\n  addresses to prevent a different PHY driver from binding and corrupting these\n  registers.\n\n  What Linux sees as the PHY on address 0 is meant for the Ethernet MAC\n  connected to the CPU port of the ADM6996 switch chip (port 5). This is the\n  Ethernet MAC you will use to send and receive data through the switch.\n\n  The PHYs at addresses 16 through 20 map to the PHYs on ports 0 through 4 of\n  the switch chip. These can be accessed with the Generic PHY driver, as the\n  registers have the common layout.\n\n  If a second Ethernet MAC on your board is wired to the port 4 PHY, that MAC\n  needs to bind to PHY address 20 for the port to work correctly.\n\n  The ADM6996 switch driver will reset the ports 0 through 3 on startup and when\n  'reset' is invoked. This could clash with a different PHY driver if the kernel\n  binds a PHY driver to address 16 through 19.\n\n  If Linux binds a PHY on addresses 1 through 10 to an Ethernet MAC, the ADM6996\n  driver will simply always report a connected 100 Mbit/s full-duplex link for\n  that PHY, and provide no other functionality. This is most likely not what you\n  want. So if you see a message in your log\n\n  \tethX: PHY overlaps ADM6996, providing fixed PHY yy.\n\n  This is most likely an indication that ethX will not work properly, and your\n  kernel needs to be configured to attach a different PHY to that Ethernet MAC.\n\n  Controlling the mapping between MACs and PHYs is usually done in platform- or\n  board-specific fixup code. The ADM6996 driver has no influence over this.\n"
  },
  {
    "path": "target/linux/generic/files/arch/mips/fw/myloader/Makefile",
    "content": "#\n# Makefile for the Compex's MyLoader support on MIPS architecture\n#\n\nlib-y += myloader.o\n"
  },
  {
    "path": "target/linux/generic/files/arch/mips/fw/myloader/myloader.c",
    "content": "/*\n *  Compex's MyLoader specific prom routines\n *\n *  Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>\n *\n *  This program is free software; you can redistribute it and/or modify it\n *  under the terms of the GNU General Public License version 2 as published\n *  by the Free Software Foundation.\n *\n */\n\n#include <linux/kernel.h>\n#include <linux/init.h>\n#include <linux/types.h>\n#include <linux/string.h>\n\n#include <asm/addrspace.h>\n#include <asm/fw/myloader/myloader.h>\n\n#define SYS_PARAMS_ADDR\t\tKSEG1ADDR(0x80000800)\n#define BOARD_PARAMS_ADDR\tKSEG1ADDR(0x80000A00)\n#define PART_TABLE_ADDR\t\tKSEG1ADDR(0x80000C00)\n#define BOOT_PARAMS_ADDR\tKSEG1ADDR(0x80000E00)\n\nstatic struct myloader_info myloader_info __initdata;\nstatic int myloader_found __initdata;\n\nstruct myloader_info * __init myloader_get_info(void)\n{\n\tstruct mylo_system_params *sysp;\n\tstruct mylo_board_params *boardp;\n\tstruct mylo_partition_table *parts;\n\n\tif (myloader_found)\n\t\treturn &myloader_info;\n\n\tsysp = (struct mylo_system_params *)(SYS_PARAMS_ADDR);\n\tboardp = (struct mylo_board_params *)(BOARD_PARAMS_ADDR);\n\tparts = (struct mylo_partition_table *)(PART_TABLE_ADDR);\n\n\tprintk(KERN_DEBUG \"MyLoader: sysp=%08x, boardp=%08x, parts=%08x\\n\",\n\t\tsysp->magic, boardp->magic, parts->magic);\n\n\t/* Check for some magic numbers */\n\tif (sysp->magic != MYLO_MAGIC_SYS_PARAMS ||\n\t    boardp->magic != MYLO_MAGIC_BOARD_PARAMS ||\n\t    le32_to_cpu(parts->magic) != MYLO_MAGIC_PARTITIONS)\n\t\treturn NULL;\n\n\tprintk(KERN_DEBUG \"MyLoader: id=%04x:%04x, sub_id=%04x:%04x\\n\",\n\t\tsysp->vid, sysp->did, sysp->svid, sysp->sdid);\n\n\tmyloader_info.vid = sysp->vid;\n\tmyloader_info.did = sysp->did;\n\tmyloader_info.svid = sysp->svid;\n\tmyloader_info.sdid = sysp->sdid;\n\n\tmemcpy(myloader_info.macs, boardp->addr, sizeof(myloader_info.macs));\n\n\tmyloader_found = 1;\n\n\treturn &myloader_info;\n}\n"
  },
  {
    "path": "target/linux/generic/files/block/partitions/fit.c",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later\n/*\n *  fs/partitions/fit.c\n *  Copyright (C) 2021  Daniel Golle\n *\n *  headers extracted from U-Boot mkimage sources\n *  (C) Copyright 2008 Semihalf\n *  (C) Copyright 2000-2005\n *  Wolfgang Denk, DENX Software Engineering, wd@denx.de.\n *\n *  based on existing partition parsers\n *  Copyright (C) 1991-1998  Linus Torvalds\n *  Re-organised Feb 1998 Russell King\n */\n\n#define pr_fmt(fmt) fmt\n\n#include <linux/types.h>\n#include <linux/of.h>\n#include <linux/of_device.h>\n#include <linux/of_fdt.h>\n#include <linux/libfdt.h>\n#include <linux/version.h>\n\n#include \"check.h\"\n\n#define FIT_IMAGES_PATH\t\t\"/images\"\n#define FIT_CONFS_PATH\t\t\"/configurations\"\n\n/* hash/signature/key node */\n#define FIT_HASH_NODENAME\t\"hash\"\n#define FIT_ALGO_PROP\t\t\"algo\"\n#define FIT_VALUE_PROP\t\t\"value\"\n#define FIT_IGNORE_PROP\t\t\"uboot-ignore\"\n#define FIT_SIG_NODENAME\t\"signature\"\n#define FIT_KEY_REQUIRED\t\"required\"\n#define FIT_KEY_HINT\t\t\"key-name-hint\"\n\n/* cipher node */\n#define FIT_CIPHER_NODENAME\t\"cipher\"\n#define FIT_ALGO_PROP\t\t\"algo\"\n\n/* image node */\n#define FIT_DATA_PROP\t\t\"data\"\n#define FIT_DATA_POSITION_PROP\t\"data-position\"\n#define FIT_DATA_OFFSET_PROP\t\"data-offset\"\n#define FIT_DATA_SIZE_PROP\t\"data-size\"\n#define FIT_TIMESTAMP_PROP\t\"timestamp\"\n#define FIT_DESC_PROP\t\t\"description\"\n#define FIT_ARCH_PROP\t\t\"arch\"\n#define FIT_TYPE_PROP\t\t\"type\"\n#define FIT_OS_PROP\t\t\"os\"\n#define FIT_COMP_PROP\t\t\"compression\"\n#define FIT_ENTRY_PROP\t\t\"entry\"\n#define FIT_LOAD_PROP\t\t\"load\"\n\n/* configuration node */\n#define FIT_KERNEL_PROP\t\t\"kernel\"\n#define FIT_FILESYSTEM_PROP\t\"filesystem\"\n#define FIT_RAMDISK_PROP\t\"ramdisk\"\n#define FIT_FDT_PROP\t\t\"fdt\"\n#define FIT_LOADABLE_PROP\t\"loadables\"\n#define FIT_DEFAULT_PROP\t\"default\"\n#define FIT_SETUP_PROP\t\t\"setup\"\n#define FIT_FPGA_PROP\t\t\"fpga\"\n#define FIT_FIRMWARE_PROP\t\"firmware\"\n#define FIT_STANDALONE_PROP\t\"standalone\"\n\n#define FIT_MAX_HASH_LEN\tHASH_MAX_DIGEST_SIZE\n\n#define MIN_FREE_SECT\t\t16\n#define REMAIN_VOLNAME\t\t\"rootfs_data\"\n\nint parse_fit_partitions(struct parsed_partitions *state, u64 fit_start_sector, u64 sectors, int *slot, int add_remain)\n{\n#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 11, 0)\n\tstruct block_device *bdev = state->disk->part0;\n#else\n\tstruct block_device *bdev = state->bdev;\n#endif\n\tstruct address_space *mapping = bdev->bd_inode->i_mapping;\n\tstruct page *page;\n\tvoid *fit, *init_fit;\n\tstruct partition_meta_info *info;\n\tchar tmp[sizeof(info->volname)];\n\tu64 dsize, dsectors, imgmaxsect = 0;\n\tu32 size, image_pos, image_len;\n\tconst u32 *image_offset_be, *image_len_be, *image_pos_be;\n\tint ret = 1, node, images, config;\n\tconst char *image_name, *image_type, *image_description, *config_default,\n\t\t*config_description, *config_loadables;\n\tint image_name_len, image_type_len, image_description_len, config_default_len,\n\t\tconfig_description_len, config_loadables_len;\n\tsector_t start_sect, nr_sects;\n\tsize_t label_min;\n\tstruct device_node *np = NULL;\n\tconst char *bootconf;\n\tconst char *loadable;\n\tconst char *select_rootfs = NULL;\n\tbool found;\n\tint loadables_rem_len, loadable_len;\n\n\tif (fit_start_sector % (1<<(PAGE_SHIFT - SECTOR_SHIFT)))\n\t\treturn -ERANGE;\n\n\tpage = read_mapping_page(mapping, fit_start_sector >> (PAGE_SHIFT - SECTOR_SHIFT), NULL);\n\tif (IS_ERR(page))\n\t\treturn -EFAULT;\n\n\tif (PageError(page))\n\t\treturn -EFAULT;\n\n\tinit_fit = page_address(page);\n\n\tif (!init_fit) {\n\t\tput_page(page);\n\t\treturn -EFAULT;\n\t}\n\n\tif (fdt_check_header(init_fit)) {\n\t\tput_page(page);\n\t\treturn 0;\n\t}\n\n\tdsectors = get_capacity(bdev->bd_disk);\n\tif (sectors)\n\t\tdsectors = (dsectors>sectors)?sectors:dsectors;\n\n\tdsize = dsectors << SECTOR_SHIFT;\n\tsize = fdt_totalsize(init_fit);\n\n\t/* silently skip non-external-data legacy FIT images */\n\tif (size > PAGE_SIZE) {\n\t\tput_page(page);\n\t\treturn 0;\n\t}\n\n\tif (size >= dsize) {\n\t\tstate->access_beyond_eod = 1;\n\t\tput_page(page);\n\t\treturn -EFBIG;\n\t}\n\n\tfit = kmemdup(init_fit, size, GFP_KERNEL);\n\tput_page(page);\n\tif (!fit)\n\t\treturn -ENOMEM;\n\n\tnp = of_find_node_by_path(\"/chosen\");\n\tif (np)\n\t\tbootconf = of_get_property(np, \"u-boot,bootconf\", NULL);\n\telse\n\t\tbootconf = NULL;\n\n\tconfig = fdt_path_offset(fit, FIT_CONFS_PATH);\n\tif (config < 0) {\n\t\tprintk(KERN_ERR \"FIT: Cannot find %s node: %d\\n\", FIT_CONFS_PATH, images);\n\t\tret = -ENOENT;\n\t\tgoto ret_out;\n\t}\n\n\tconfig_default = fdt_getprop(fit, config, FIT_DEFAULT_PROP, &config_default_len);\n\n\tif (!config_default && !bootconf) {\n\t\tprintk(KERN_ERR \"FIT: Cannot find default configuration\\n\");\n\t\tret = -ENOENT;\n\t\tgoto ret_out;\n\t}\n\n\tnode = fdt_subnode_offset(fit, config, bootconf?:config_default);\n\tif (node < 0) {\n\t\tprintk(KERN_ERR \"FIT: Cannot find %s node: %d\\n\", bootconf?:config_default, node);\n\t\tret = -ENOENT;\n\t\tgoto ret_out;\n\t}\n\n\tconfig_description = fdt_getprop(fit, node, FIT_DESC_PROP, &config_description_len);\n\tconfig_loadables = fdt_getprop(fit, node, FIT_LOADABLE_PROP, &config_loadables_len);\n\n\tprintk(KERN_DEBUG \"FIT: %s configuration: \\\"%s\\\"%s%s%s\\n\",\n\t\tbootconf?\"Selected\":\"Default\", bootconf?:config_default,\n\t\tconfig_description?\" (\":\"\", config_description?:\"\", config_description?\")\":\"\");\n\n\tif (!config_loadables || !config_loadables_len) {\n\t\tprintk(KERN_ERR \"FIT: No loadables configured in \\\"%s\\\"\\n\", bootconf?:config_default);\n\t\tret = -ENOENT;\n\t\tgoto ret_out;\n\t}\n\n\timages = fdt_path_offset(fit, FIT_IMAGES_PATH);\n\tif (images < 0) {\n\t\tprintk(KERN_ERR \"FIT: Cannot find %s node: %d\\n\", FIT_IMAGES_PATH, images);\n\t\tret = -EINVAL;\n\t\tgoto ret_out;\n\t}\n\n\tfdt_for_each_subnode(node, fit, images) {\n\t\timage_name = fdt_get_name(fit, node, &image_name_len);\n\t\timage_type = fdt_getprop(fit, node, FIT_TYPE_PROP, &image_type_len);\n\t\timage_offset_be = fdt_getprop(fit, node, FIT_DATA_OFFSET_PROP, NULL);\n\t\timage_pos_be = fdt_getprop(fit, node, FIT_DATA_POSITION_PROP, NULL);\n\t\timage_len_be = fdt_getprop(fit, node, FIT_DATA_SIZE_PROP, NULL);\n\t\tif (!image_name || !image_type || !image_len_be)\n\t\t\tcontinue;\n\n\t\timage_len = be32_to_cpu(*image_len_be);\n\t\tif (!image_len)\n\t\t\tcontinue;\n\n\t\tif (image_offset_be)\n\t\t\timage_pos = be32_to_cpu(*image_offset_be) + size;\n\t\telse if (image_pos_be)\n\t\t\timage_pos = be32_to_cpu(*image_pos_be);\n\t\telse\n\t\t\tcontinue;\n\n\t\timage_description = fdt_getprop(fit, node, FIT_DESC_PROP, &image_description_len);\n\n\t\tprintk(KERN_DEBUG \"FIT: %16s sub-image 0x%08x..0x%08x \\\"%s\\\" %s%s%s\\n\",\n\t\t\timage_type, image_pos, image_pos + image_len - 1, image_name,\n\t\t\timage_description?\"(\":\"\", image_description?:\"\", image_description?\") \":\"\");\n\n\t\tif (strcmp(image_type, FIT_FILESYSTEM_PROP))\n\t\t\tcontinue;\n\n\t\t/* check if sub-image is part of configured loadables */\n\t\tfound = false;\n\t\tloadable = config_loadables;\n\t\tloadables_rem_len = config_loadables_len;\n\t\twhile (loadables_rem_len > 1) {\n\t\t\tloadable_len = strnlen(loadable, loadables_rem_len - 1) + 1;\n\t\t\tloadables_rem_len -= loadable_len;\n\t\t\tif (!strncmp(image_name, loadable, loadable_len)) {\n\t\t\t\tfound = true;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\tloadable += loadable_len;\n\t\t}\n\t\tif (!found)\n\t\t\tcontinue;\n\n\t\tif (image_pos & ((1 << PAGE_SHIFT)-1)) {\n\t\t\tprintk(KERN_ERR \"FIT: image %s start not aligned to page boundaries, skipping\\n\", image_name);\n\t\t\tcontinue;\n\t\t}\n\n\t\tif (image_len & ((1 << PAGE_SHIFT)-1)) {\n\t\t\tprintk(KERN_ERR \"FIT: sub-image %s end not aligned to page boundaries, skipping\\n\", image_name);\n\t\t\tcontinue;\n\t\t}\n\n\t\tstart_sect = image_pos >> SECTOR_SHIFT;\n\t\tnr_sects = image_len >> SECTOR_SHIFT;\n\t\timgmaxsect = (imgmaxsect < (start_sect + nr_sects))?(start_sect + nr_sects):imgmaxsect;\n\n\t\tif (start_sect + nr_sects > dsectors) {\n\t\t\tstate->access_beyond_eod = 1;\n\t\t\tcontinue;\n\t\t}\n\n\t\tput_partition(state, ++(*slot), fit_start_sector + start_sect, nr_sects);\n\t\tstate->parts[*slot].flags = ADDPART_FLAG_READONLY;\n\t\tstate->parts[*slot].has_info = true;\n\t\tinfo = &state->parts[*slot].info;\n\n\t\tlabel_min = min_t(int, sizeof(info->volname) - 1, image_name_len);\n\t\tstrncpy(info->volname, image_name, label_min);\n\t\tinfo->volname[label_min] = '\\0';\n\n\t\tsnprintf(tmp, sizeof(tmp), \"(%s)\", info->volname);\n\t\tstrlcat(state->pp_buf, tmp, PAGE_SIZE);\n\n\t\t/* Mark first loadable listed to be mounted as rootfs */\n\t\tif (!strcmp(image_name, config_loadables)) {\n\t\t\tselect_rootfs = image_name;\n\t\t\tstate->parts[*slot].flags |= ADDPART_FLAG_ROOTDEV;\n\t\t}\n\t}\n\n\tif (select_rootfs)\n\t\tprintk(KERN_DEBUG \"FIT: selecting configured loadable \\\"%s\\\" to be root filesystem\\n\", select_rootfs);\n\n\tif (add_remain && (imgmaxsect + MIN_FREE_SECT) < dsectors) {\n\t\tput_partition(state, ++(*slot), fit_start_sector + imgmaxsect, dsectors - imgmaxsect);\n\t\tstate->parts[*slot].flags = 0;\n\t\tinfo = &state->parts[*slot].info;\n\t\tstrcpy(info->volname, REMAIN_VOLNAME);\n\t\tsnprintf(tmp, sizeof(tmp), \"(%s)\", REMAIN_VOLNAME);\n\t\tstrlcat(state->pp_buf, tmp, PAGE_SIZE);\n\t}\nret_out:\n\tkfree(fit);\n\treturn ret;\n}\n\nint fit_partition(struct parsed_partitions *state) {\n\tint slot = 0;\n\treturn parse_fit_partitions(state, 0, 0, &slot, 0);\n}\n"
  },
  {
    "path": "target/linux/generic/files/drivers/mtd/mtdsplit/Kconfig",
    "content": "config MTD_SPLIT\n\tdef_bool n\n\thelp\n\t  Generic MTD split support.\n\nconfig MTD_SPLIT_SUPPORT\n\tdef_bool MTD = y\n\ncomment \"Rootfs partition parsers\"\n\nconfig MTD_SPLIT_SQUASHFS_ROOT\n\tbool \"Squashfs based root partition parser\"\n\tdepends on MTD_SPLIT_SUPPORT\n\tselect MTD_SPLIT\n\tdefault n\n\thelp\n\t  This provides a parsing function which allows to detect the\n\t  offset and size of the unused portion of a rootfs partition\n\t  containing a squashfs.\n\ncomment \"Firmware partition parsers\"\n\nconfig MTD_SPLIT_BCM63XX_FW\n\tbool \"BCM63xx firmware parser\"\n\tdepends on MTD_SPLIT_SUPPORT\n\tselect MTD_SPLIT\n\nconfig MTD_SPLIT_BCM_WFI_FW\n\tbool \"Broadcom Whole Flash Image parser\"\n\tdepends on MTD_SPLIT_SUPPORT\n\tselect MTD_SPLIT\n\nconfig MTD_SPLIT_CFE_BOOTFS\n\tbool \"Parser finding rootfs appended to the CFE bootfs\"\n\tdepends on MTD_SPLIT_SUPPORT && ARCH_BCM4908\n\tselect MTD_SPLIT\n\thelp\n\t  cferom on BCM4908 (and bcm63xx) uses JFFS2 bootfs partition\n\t  for storing kernel, cferam and some device specific files.\n\t  There isn't any straight way of storing rootfs so it gets\n\t  appended to the JFFS2 bootfs partition. Kernel needs to find\n\t  it and run init from it. This parser is responsible for\n\t  finding appended rootfs.\n\nconfig MTD_SPLIT_SEAMA_FW\n\tbool \"Seama firmware parser\"\n\tdepends on MTD_SPLIT_SUPPORT\n\tselect MTD_SPLIT\n\nconfig MTD_SPLIT_WRGG_FW\n\tbool \"WRGG firmware parser\"\n\tdepends on MTD_SPLIT_SUPPORT\n\tselect MTD_SPLIT\n\nconfig MTD_SPLIT_UIMAGE_FW\n\tbool \"uImage based firmware partition parser\"\n\tdepends on MTD_SPLIT_SUPPORT\n\tselect MTD_SPLIT\n\nconfig MTD_SPLIT_FIT_FW\n\tbool \"FIT based firmware partition parser\"\n\tdepends on MTD_SPLIT_SUPPORT\n\tselect MTD_SPLIT\n\nconfig MTD_SPLIT_LZMA_FW\n\tbool \"LZMA compressed kernel based firmware partition parser\"\n\tdepends on MTD_SPLIT_SUPPORT\n\tselect MTD_SPLIT\n\nconfig MTD_SPLIT_TPLINK_FW\n\tbool \"TP-Link firmware parser\"\n\tdepends on MTD_SPLIT_SUPPORT\n\tselect MTD_SPLIT\n\nconfig MTD_SPLIT_TRX_FW\n\tbool \"TRX image based firmware partition parser\"\n\tdepends on MTD_SPLIT_SUPPORT\n\tselect MTD_SPLIT\n\nconfig MTD_SPLIT_BRNIMAGE_FW\n\tbool \"brnImage (brnboot image) firmware parser\"\n\tdepends on MTD_SPLIT_SUPPORT\n\tselect MTD_SPLIT\n\nconfig MTD_SPLIT_EVA_FW\n\tbool \"EVA image based firmware partition parser\"\n\tdepends on MTD_SPLIT_SUPPORT\n\tselect MTD_SPLIT\n\nconfig MTD_SPLIT_MINOR_FW\n\tbool \"Mikrotik NOR image based firmware partition parser\"\n\tdepends on MTD_SPLIT_SUPPORT\n\tselect MTD_SPLIT\n\nconfig MTD_SPLIT_JIMAGE_FW\n\tbool \"JBOOT Image based firmware partition parser\"\n\tdepends on MTD_SPLIT_SUPPORT\n\tselect MTD_SPLIT\n\nconfig MTD_SPLIT_ELF_FW\n\tbool \"ELF loader firmware partition parser\"\n\tdepends on MTD_SPLIT_SUPPORT\n\tselect MTD_SPLIT\n"
  },
  {
    "path": "target/linux/generic/files/drivers/mtd/mtdsplit/Makefile",
    "content": "obj-$(CONFIG_MTD_SPLIT)\t\t+= mtdsplit.o\nobj-$(CONFIG_MTD_SPLIT_BCM63XX_FW) += mtdsplit_bcm63xx.o\nobj-$(CONFIG_MTD_SPLIT_BCM_WFI_FW) += mtdsplit_bcm_wfi.o\nobj-$(CONFIG_MTD_SPLIT_CFE_BOOTFS) += mtdsplit_cfe_bootfs.o\nobj-$(CONFIG_MTD_SPLIT_SEAMA_FW) += mtdsplit_seama.o\nobj-$(CONFIG_MTD_SPLIT_SQUASHFS_ROOT) += mtdsplit_squashfs.o\nobj-$(CONFIG_MTD_SPLIT_UIMAGE_FW) += mtdsplit_uimage.o\nobj-$(CONFIG_MTD_SPLIT_FIT_FW) += mtdsplit_fit.o\nobj-$(CONFIG_MTD_SPLIT_LZMA_FW) += mtdsplit_lzma.o\nobj-$(CONFIG_MTD_SPLIT_TPLINK_FW) += mtdsplit_tplink.o\nobj-$(CONFIG_MTD_SPLIT_TRX_FW) += mtdsplit_trx.o\nobj-$(CONFIG_MTD_SPLIT_BRNIMAGE_FW) += mtdsplit_brnimage.o\nobj-$(CONFIG_MTD_SPLIT_EVA_FW) += mtdsplit_eva.o\nobj-$(CONFIG_MTD_SPLIT_WRGG_FW) += mtdsplit_wrgg.o\nobj-$(CONFIG_MTD_SPLIT_MINOR_FW) += mtdsplit_minor.o\nobj-$(CONFIG_MTD_SPLIT_JIMAGE_FW) += mtdsplit_jimage.o\nobj-$(CONFIG_MTD_SPLIT_ELF_FW) += mtdsplit_elf.o\n"
  },
  {
    "path": "target/linux/generic/files/drivers/mtd/mtdsplit/mtdsplit.c",
    "content": "/*\n * Copyright (C) 2009-2013 Felix Fietkau <nbd@nbd.name>\n * Copyright (C) 2009-2013 Gabor Juhos <juhosg@openwrt.org>\n * Copyright (C) 2012 Jonas Gorski <jogo@openwrt.org>\n * Copyright (C) 2013 Hauke Mehrtens <hauke@hauke-m.de>\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of the GNU General Public License version 2 as published\n * by the Free Software Foundation.\n *\n */\n\n#define pr_fmt(fmt)\t\"mtdsplit: \" fmt\n\n#include <linux/export.h>\n#include <linux/init.h>\n#include <linux/kernel.h>\n#include <linux/magic.h>\n#include <linux/mtd/mtd.h>\n#include <linux/mtd/partitions.h>\n#include <linux/byteorder/generic.h>\n\n#include \"mtdsplit.h\"\n\n#define UBI_EC_MAGIC\t\t\t0x55424923\t/* UBI# */\n\nstruct squashfs_super_block {\n\t__le32 s_magic;\n\t__le32 pad0[9];\n\t__le64 bytes_used;\n};\n\nint mtd_get_squashfs_len(struct mtd_info *master,\n\t\t\t size_t offset,\n\t\t\t size_t *squashfs_len)\n{\n\tstruct squashfs_super_block sb;\n\tsize_t retlen;\n\tint err;\n\n\terr = mtd_read(master, offset, sizeof(sb), &retlen, (void *)&sb);\n\tif (err || (retlen != sizeof(sb))) {\n\t\tpr_alert(\"error occured while reading from \\\"%s\\\"\\n\",\n\t\t\t master->name);\n\t\treturn -EIO;\n\t}\n\n\tif (le32_to_cpu(sb.s_magic) != SQUASHFS_MAGIC) {\n\t\tpr_alert(\"no squashfs found in \\\"%s\\\"\\n\", master->name);\n\t\treturn -EINVAL;\n\t}\n\n\tretlen = le64_to_cpu(sb.bytes_used);\n\tif (retlen <= 0) {\n\t\tpr_alert(\"squashfs is empty in \\\"%s\\\"\\n\", master->name);\n\t\treturn -ENODEV;\n\t}\n\n\tif (offset + retlen > master->size) {\n\t\tpr_alert(\"squashfs has invalid size in \\\"%s\\\"\\n\",\n\t\t\t master->name);\n\t\treturn -EINVAL;\n\t}\n\n\t*squashfs_len = retlen;\n\treturn 0;\n}\nEXPORT_SYMBOL_GPL(mtd_get_squashfs_len);\n\nstatic ssize_t mtd_next_eb(struct mtd_info *mtd, size_t offset)\n{\n\treturn mtd_rounddown_to_eb(offset, mtd) + mtd->erasesize;\n}\n\nint mtd_check_rootfs_magic(struct mtd_info *mtd, size_t offset,\n\t\t\t   enum mtdsplit_part_type *type)\n{\n\tu32 magic;\n\tsize_t retlen;\n\tint ret;\n\n\tret = mtd_read(mtd, offset, sizeof(magic), &retlen,\n\t\t       (unsigned char *) &magic);\n\tif (ret)\n\t\treturn ret;\n\n\tif (retlen != sizeof(magic))\n\t\treturn -EIO;\n\n\tif (le32_to_cpu(magic) == SQUASHFS_MAGIC) {\n\t\tif (type)\n\t\t\t*type = MTDSPLIT_PART_TYPE_SQUASHFS;\n\t\treturn 0;\n\t} else if (magic == 0x19852003) {\n\t\tif (type)\n\t\t\t*type = MTDSPLIT_PART_TYPE_JFFS2;\n\t\treturn 0;\n\t} else if (be32_to_cpu(magic) == UBI_EC_MAGIC) {\n\t\tif (type)\n\t\t\t*type = MTDSPLIT_PART_TYPE_UBI;\n\t\treturn 0;\n\t}\n\n\treturn -EINVAL;\n}\nEXPORT_SYMBOL_GPL(mtd_check_rootfs_magic);\n\nint mtd_find_rootfs_from(struct mtd_info *mtd,\n\t\t\t size_t from,\n\t\t\t size_t limit,\n\t\t\t size_t *ret_offset,\n\t\t\t enum mtdsplit_part_type *type)\n{\n\tsize_t offset;\n\tint err;\n\n\tfor (offset = from; offset < limit;\n\t     offset = mtd_next_eb(mtd, offset)) {\n\t\terr = mtd_check_rootfs_magic(mtd, offset, type);\n\t\tif (err)\n\t\t\tcontinue;\n\n\t\t*ret_offset = offset;\n\t\treturn 0;\n\t}\n\n\treturn -ENODEV;\n}\nEXPORT_SYMBOL_GPL(mtd_find_rootfs_from);\n\n"
  },
  {
    "path": "target/linux/generic/files/drivers/mtd/mtdsplit/mtdsplit.h",
    "content": "/*\n * Copyright (C) 2009-2013 Felix Fietkau <nbd@nbd.name>\n * Copyright (C) 2009-2013 Gabor Juhos <juhosg@openwrt.org>\n * Copyright (C) 2012 Jonas Gorski <jogo@openwrt.org>\n * Copyright (C) 2013 Hauke Mehrtens <hauke@hauke-m.de>\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of the GNU General Public License version 2 as published\n * by the Free Software Foundation.\n *\n */\n\n#ifndef _MTDSPLIT_H\n#define _MTDSPLIT_H\n\n#define KERNEL_PART_NAME\t\"kernel\"\n#define ROOTFS_PART_NAME\t\"rootfs\"\n#define UBI_PART_NAME\t\t\"ubi\"\n\n#define ROOTFS_SPLIT_NAME\t\"rootfs_data\"\n\nenum mtdsplit_part_type {\n\tMTDSPLIT_PART_TYPE_UNK = 0,\n\tMTDSPLIT_PART_TYPE_SQUASHFS,\n\tMTDSPLIT_PART_TYPE_JFFS2,\n\tMTDSPLIT_PART_TYPE_UBI,\n};\n\n#ifdef CONFIG_MTD_SPLIT\nint mtd_get_squashfs_len(struct mtd_info *master,\n\t\t\t size_t offset,\n\t\t\t size_t *squashfs_len);\n\nint mtd_check_rootfs_magic(struct mtd_info *mtd, size_t offset,\n\t\t\t   enum mtdsplit_part_type *type);\n\nint mtd_find_rootfs_from(struct mtd_info *mtd,\n\t\t\t size_t from,\n\t\t\t size_t limit,\n\t\t\t size_t *ret_offset,\n\t\t\t enum mtdsplit_part_type *type);\n\n#else\nstatic inline int mtd_get_squashfs_len(struct mtd_info *master,\n\t\t\t\t       size_t offset,\n\t\t\t\t       size_t *squashfs_len)\n{\n\treturn -ENODEV;\n}\n\nstatic inline int mtd_check_rootfs_magic(struct mtd_info *mtd, size_t offset,\n\t\t\t\t\t enum mtdsplit_part_type *type)\n{\n\treturn -EINVAL;\n}\n\nstatic inline int mtd_find_rootfs_from(struct mtd_info *mtd,\n\t\t\t\t       size_t from,\n\t\t\t\t       size_t limit,\n\t\t\t\t       size_t *ret_offset,\n\t\t\t\t       enum mtdsplit_part_type *type)\n{\n\treturn -ENODEV;\n}\n#endif /* CONFIG_MTD_SPLIT */\n\n#endif /* _MTDSPLIT_H */\n"
  },
  {
    "path": "target/linux/generic/files/drivers/mtd/mtdsplit/mtdsplit_bcm63xx.c",
    "content": "/*\n * Firmware MTD split for BCM63XX, based on bcm63xxpart.c\n *\n * Copyright (C) 2006-2008 Florian Fainelli <florian@openwrt.org>\n * Copyright (C) 2006-2008 Mike Albon <malbon@openwrt.org>\n * Copyright (C) 2009-2010 Daniel Dickinson <openwrt@cshore.neomailbox.net>\n * Copyright (C) 2011-2013 Jonas Gorski <jonas.gorski@gmail.com>\n * Copyright (C) 2015 Simon Arlott <simon@fire.lp0.eu>\n * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of the GNU General Public License version 2 as published\n * by the Free Software Foundation.\n *\n */\n\n#define pr_fmt(fmt) KBUILD_MODNAME \": \" fmt\n\n#include <linux/bcm963xx_tag.h>\n#include <linux/crc32.h>\n#include <linux/init.h>\n#include <linux/kernel.h>\n#include <linux/module.h>\n#include <linux/slab.h>\n#include <linux/byteorder/generic.h>\n#include <linux/mtd/mtd.h>\n#include <linux/mtd/partitions.h>\n\n#include \"mtdsplit.h\"\n\n/* Ensure strings read from flash structs are null terminated */\n#define STR_NULL_TERMINATE(x) \\\n\tdo { char *_str = (x); _str[sizeof(x) - 1] = 0; } while (0)\n\n#define BCM63XX_NR_PARTS 2\n\nstatic int bcm63xx_read_image_tag(struct mtd_info *master, loff_t offset,\n\t\t\t\t  struct bcm_tag *hdr)\n{\n\tint ret;\n\tsize_t retlen;\n\tu32 computed_crc;\n\n\tret = mtd_read(master, offset, sizeof(*hdr), &retlen, (void *) hdr);\n\tif (ret)\n\t\treturn ret;\n\n\tif (retlen != sizeof(*hdr))\n\t\treturn -EIO;\n\n\tcomputed_crc = crc32_le(IMAGETAG_CRC_START, (u8 *)hdr,\n\t\t\t\toffsetof(struct bcm_tag, header_crc));\n\tif (computed_crc == hdr->header_crc) {\n\t    STR_NULL_TERMINATE(hdr->board_id);\n\t    STR_NULL_TERMINATE(hdr->tag_version);\n\n\t\tpr_info(\"CFE image tag found at 0x%llx with version %s, \"\n\t\t\t\"board type %s\\n\", offset, hdr->tag_version,\n\t\t\thdr->board_id);\n\n\t\treturn 0;\n\t} else {\n\t\tpr_err(\"CFE image tag at 0x%llx CRC invalid \"\n\t\t       \"(expected %08x, actual %08x)\\n\",\n\t\t       offset, hdr->header_crc, computed_crc);\n\n\t\treturn 1;\n\t}\n}\n\nstatic int bcm63xx_parse_partitions(struct mtd_info *master,\n\t\t\t\t    const struct mtd_partition **pparts,\n\t\t\t\t    struct bcm_tag *hdr)\n{\n\tstruct mtd_partition *parts;\n\tunsigned int flash_image_start;\n\tunsigned int kernel_address;\n\tunsigned int kernel_length;\n\tsize_t kernel_offset = 0, kernel_size = 0;\n\tsize_t rootfs_offset = 0, rootfs_size = 0;\n\tint kernel_part, rootfs_part;\n\n\tSTR_NULL_TERMINATE(hdr->flash_image_start);\n\tif (kstrtouint(hdr->flash_image_start, 10, &flash_image_start) ||\n\t    flash_image_start < BCM963XX_EXTENDED_SIZE) {\n\t\tpr_err(\"invalid rootfs address: %*ph\\n\",\n\t\t       (int) sizeof(hdr->flash_image_start),\n\t\t       hdr->flash_image_start);\n\t\treturn -EINVAL;\n\t}\n\n\tSTR_NULL_TERMINATE(hdr->kernel_address);\n\tif (kstrtouint(hdr->kernel_address, 10, &kernel_address) ||\n\t    kernel_address < BCM963XX_EXTENDED_SIZE) {\n\t\tpr_err(\"invalid kernel address: %*ph\\n\",\n\t\t       (int) sizeof(hdr->kernel_address), hdr->kernel_address);\n\t\treturn -EINVAL;\n\t}\n\n\tSTR_NULL_TERMINATE(hdr->kernel_length);\n\tif (kstrtouint(hdr->kernel_length, 10, &kernel_length) ||\n\t    !kernel_length) {\n\t\tpr_err(\"invalid kernel length: %*ph\\n\",\n\t\t       (int) sizeof(hdr->kernel_length), hdr->kernel_length);\n\t\treturn -EINVAL;\n\t}\n\n\tkernel_offset = kernel_address - BCM963XX_EXTENDED_SIZE -\n\t\t\tmtdpart_get_offset(master);\n\tkernel_size = kernel_length;\n\n\tif (flash_image_start < kernel_address) {\n\t\t/* rootfs first */\n\t\trootfs_part = 0;\n\t\tkernel_part = 1;\n\t\trootfs_offset = flash_image_start - BCM963XX_EXTENDED_SIZE -\n\t\t\t\tmtdpart_get_offset(master);\n\t\trootfs_size = kernel_offset - rootfs_offset;\n\t} else {\n\t\t/* kernel first */\n\t\tkernel_part = 0;\n\t\trootfs_part = 1;\n\t\trootfs_offset = kernel_offset + kernel_size;\n\t\trootfs_size = master->size - rootfs_offset;\n\t}\n\n\tif (mtd_check_rootfs_magic(master, rootfs_offset, NULL))\n\t\tpr_warn(\"rootfs magic not found\\n\");\n\n\tparts = kzalloc(BCM63XX_NR_PARTS * sizeof(*parts), GFP_KERNEL);\n\tif (!parts)\n\t\treturn -ENOMEM;\n\n\tparts[kernel_part].name = KERNEL_PART_NAME;\n\tparts[kernel_part].offset = kernel_offset;\n\tparts[kernel_part].size = kernel_size;\n\n\tparts[rootfs_part].name = ROOTFS_PART_NAME;\n\tparts[rootfs_part].offset = rootfs_offset;\n\tparts[rootfs_part].size = rootfs_size;\n\n\t*pparts = parts;\n\treturn BCM63XX_NR_PARTS;\n}\n\nstatic int mtdsplit_parse_bcm63xx(struct mtd_info *master,\n\t\t\t\t  const struct mtd_partition **pparts,\n\t\t\t\t  struct mtd_part_parser_data *data)\n{\n\tstruct bcm_tag hdr;\n\tloff_t offset;\n\n\tif (mtd_type_is_nand(master))\n\t\treturn -EINVAL;\n\n\t/* find bcm63xx_cfe image on erase block boundaries */\n\tfor (offset = 0; offset < master->size; offset += master->erasesize) {\n\t\tif (!bcm63xx_read_image_tag(master, offset, (void *) &hdr))\n\t\t\treturn bcm63xx_parse_partitions(master, pparts,\n\t\t\t\t\t\t\t(void *) &hdr);\n\t}\n\n\treturn -EINVAL;\n}\n\nstatic const struct of_device_id mtdsplit_fit_of_match_table[] = {\n\t{ .compatible = \"brcm,bcm963xx-imagetag\" },\n\t{ },\n};\n\nstatic struct mtd_part_parser mtdsplit_bcm63xx_parser = {\n\t.owner = THIS_MODULE,\n\t.name = \"bcm63xx-fw\",\n\t.of_match_table = mtdsplit_fit_of_match_table,\n\t.parse_fn = mtdsplit_parse_bcm63xx,\n\t.type = MTD_PARSER_TYPE_FIRMWARE,\n};\n\nstatic int __init mtdsplit_bcm63xx_init(void)\n{\n\tregister_mtd_parser(&mtdsplit_bcm63xx_parser);\n\n\treturn 0;\n}\n\nmodule_init(mtdsplit_bcm63xx_init);\n"
  },
  {
    "path": "target/linux/generic/files/drivers/mtd/mtdsplit/mtdsplit_bcm_wfi.c",
    "content": "/*\n * MTD split for Broadcom Whole Flash Image\n *\n * Copyright (C) 2020 Álvaro Fernández Rojas <noltari@gmail.com>\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of the GNU General Public License version 2 as published\n * by the Free Software Foundation.\n *\n */\n\n#define je16_to_cpu(x) ((x).v16)\n#define je32_to_cpu(x) ((x).v32)\n\n#include <linux/crc32.h>\n#include <linux/init.h>\n#include <linux/jffs2.h>\n#include <linux/kernel.h>\n#include <linux/module.h>\n#include <linux/slab.h>\n#include <linux/byteorder/generic.h>\n#include <linux/mtd/mtd.h>\n#include <linux/mtd/partitions.h>\n\n#include \"mtdsplit.h\"\n\n#define char_to_num(c)\t\t((c >= '0' && c <= '9') ? (c - '0') : (0))\n\n#define BCM_WFI_PARTS\t\t3\n#define BCM_WFI_SPLIT_PARTS\t2\n\n#define CFERAM_NAME\t\t\"cferam\"\n#define CFERAM_NAME_LEN\t\t(sizeof(CFERAM_NAME) - 1)\n#define KERNEL_NAME\t\t\"vmlinux.lz\"\n#define KERNEL_NAME_LEN\t\t(sizeof(KERNEL_NAME) - 1)\n#define OPENWRT_NAME\t\t\"1-openwrt\"\n#define OPENWRT_NAME_LEN\t(sizeof(OPENWRT_NAME) - 1)\n\n#define UBI_MAGIC\t\t0x55424923\n\n#define CFE_MAGIC_PFX\t\t\"cferam.\"\n#define CFE_MAGIC_PFX_LEN\t(sizeof(CFE_MAGIC_PFX) - 1)\n#define CFE_MAGIC\t\t\"cferam.000\"\n#define CFE_MAGIC_LEN\t\t(sizeof(CFE_MAGIC) - 1)\n#define SERCOMM_MAGIC_PFX\t\"eRcOmM.\"\n#define SERCOMM_MAGIC_PFX_LEN\t(sizeof(SERCOMM_MAGIC_PFX) - 1)\n#define SERCOMM_MAGIC\t\t\"eRcOmM.000\"\n#define SERCOMM_MAGIC_LEN\t(sizeof(SERCOMM_MAGIC) - 1)\n\n#define PART_CFERAM\t\t\"cferam\"\n#define PART_FIRMWARE\t\t\"firmware\"\n#define PART_IMAGE_1\t\t\"img1\"\n#define PART_IMAGE_2\t\t\"img2\"\n\nstatic u32 jffs2_dirent_crc(struct jffs2_raw_dirent *node)\n{\n\treturn crc32(0, node, sizeof(struct jffs2_raw_dirent) - 8);\n}\n\nstatic bool jffs2_dirent_valid(struct jffs2_raw_dirent *node)\n{\n\treturn ((je16_to_cpu(node->magic) == JFFS2_MAGIC_BITMASK) &&\n\t\t(je16_to_cpu(node->nodetype) == JFFS2_NODETYPE_DIRENT) &&\n\t\tje32_to_cpu(node->ino) &&\n\t\tje32_to_cpu(node->node_crc) == jffs2_dirent_crc(node));\n}\n\nstatic int jffs2_find_file(struct mtd_info *mtd, uint8_t *buf,\n\t\t\t   const char *name, size_t name_len,\n\t\t\t   loff_t *offs, loff_t size,\n\t\t\t   char **out_name, size_t *out_name_len)\n{\n\tconst loff_t end = *offs + size;\n\tstruct jffs2_raw_dirent *node;\n\tbool valid = false;\n\tsize_t retlen;\n\tuint16_t magic;\n\tint rc;\n\n\tfor (; *offs < end; *offs += mtd->erasesize) {\n\t\tunsigned int block_offs = 0;\n\n\t\t/* Skip CFE erased blocks */\n\t\trc = mtd_read(mtd, *offs, sizeof(magic), &retlen,\n\t\t\t      (void *) &magic);\n\t\tif (rc || retlen != sizeof(magic)) {\n\t\t\tcontinue;\n\t\t}\n\n\t\t/* Skip blocks not starting with JFFS2 magic */\n\t\tif (magic != JFFS2_MAGIC_BITMASK)\n\t\t\tcontinue;\n\n\t\t/* Read full block */\n\t\trc = mtd_read(mtd, *offs, mtd->erasesize, &retlen,\n\t\t\t      (void *) buf);\n\t\tif (rc)\n\t\t\treturn rc;\n\t\tif (retlen != mtd->erasesize)\n\t\t\treturn -EINVAL;\n\n\t\twhile (block_offs < mtd->erasesize) {\n\t\t\tnode = (struct jffs2_raw_dirent *) &buf[block_offs];\n\n\t\t\tif (!jffs2_dirent_valid(node)) {\n\t\t\t\tblock_offs += 4;\n\t\t\t\tcontinue;\n\t\t\t}\n\n\t\t\tif (!memcmp(node->name, OPENWRT_NAME,\n\t\t\t\t    OPENWRT_NAME_LEN)) {\n\t\t\t\tvalid = true;\n\t\t\t} else if (!memcmp(node->name, name, name_len)) {\n\t\t\t\tif (!valid)\n\t\t\t\t\treturn -EINVAL;\n\n\t\t\t\tif (out_name)\n\t\t\t\t\t*out_name = kstrndup(node->name,\n\t\t\t\t\t\t\t     node->nsize,\n\t\t\t\t\t\t\t     GFP_KERNEL);\n\n\t\t\t\tif (out_name_len)\n\t\t\t\t\t*out_name_len = node->nsize;\n\n\t\t\t\treturn 0;\n\t\t\t}\n\n\t\t\tblock_offs += je32_to_cpu(node->totlen);\n\t\t\tblock_offs = (block_offs + 0x3) & ~0x3;\n\t\t}\n\t}\n\n\treturn -ENOENT;\n}\n\nstatic int ubifs_find(struct mtd_info *mtd, loff_t *offs, loff_t size)\n{\n\tconst loff_t end = *offs + size;\n\tuint32_t magic;\n\tsize_t retlen;\n\tint rc;\n\n\tfor (; *offs < end; *offs += mtd->erasesize) {\n\t\trc = mtd_read(mtd, *offs, sizeof(magic), &retlen,\n\t\t\t      (unsigned char *) &magic);\n\t\tif (rc || retlen != sizeof(magic))\n\t\t\tcontinue;\n\n\t\tif (be32_to_cpu(magic) == UBI_MAGIC)\n\t\t\treturn 0;\n\t}\n\n\treturn -ENOENT;\n}\n\nstatic int parse_bcm_wfi(struct mtd_info *master,\n\t\t\t const struct mtd_partition **pparts,\n\t\t\t uint8_t *buf, loff_t off, loff_t size, bool cfe_part)\n{\n\tstruct mtd_partition *parts;\n\tloff_t cfe_off, kernel_off, rootfs_off;\n\tunsigned int num_parts = BCM_WFI_PARTS, cur_part = 0;\n\tint ret;\n\n\tif (cfe_part) {\n\t\tnum_parts++;\n\t\tcfe_off = off;\n\n\t\tret = jffs2_find_file(master, buf, CFERAM_NAME,\n\t\t\t\t      CFERAM_NAME_LEN, &cfe_off,\n\t\t\t\t      size - (cfe_off - off), NULL, NULL);\n\t\tif (ret)\n\t\t\treturn ret;\n\n\t\tkernel_off = cfe_off + master->erasesize;\n\t} else {\n\t\tkernel_off = off;\n\t}\n\n\tret = jffs2_find_file(master, buf, KERNEL_NAME, KERNEL_NAME_LEN,\n\t\t\t      &kernel_off, size - (kernel_off - off),\n\t\t\t      NULL, NULL);\n\tif (ret)\n\t\treturn ret;\n\n\trootfs_off = kernel_off + master->erasesize;\n\tret = ubifs_find(master, &rootfs_off, size - (rootfs_off - off));\n\tif (ret)\n\t\treturn ret;\n\n\tparts = kzalloc(num_parts * sizeof(*parts), GFP_KERNEL);\n\tif (!parts)\n\t\treturn -ENOMEM;\n\n\tif (cfe_part) {\n\t\tparts[cur_part].name = PART_CFERAM;\n\t\tparts[cur_part].mask_flags = MTD_WRITEABLE;\n\t\tparts[cur_part].offset = cfe_off;\n\t\tparts[cur_part].size = kernel_off - cfe_off;\n\t\tcur_part++;\n\t}\n\n\tparts[cur_part].name = PART_FIRMWARE;\n\tparts[cur_part].offset = kernel_off;\n\tparts[cur_part].size = size - (kernel_off - off);\n\tcur_part++;\n\n\tparts[cur_part].name = KERNEL_PART_NAME;\n\tparts[cur_part].offset = kernel_off;\n\tparts[cur_part].size = rootfs_off - kernel_off;\n\tcur_part++;\n\n\tparts[cur_part].name = UBI_PART_NAME;\n\tparts[cur_part].offset = rootfs_off;\n\tparts[cur_part].size = size - (rootfs_off - off);\n\tcur_part++;\n\n\t*pparts = parts;\n\n\treturn num_parts;\n}\n\nstatic int mtdsplit_parse_bcm_wfi(struct mtd_info *master,\n\t\t\t\t  const struct mtd_partition **pparts,\n\t\t\t\t  struct mtd_part_parser_data *data)\n{\n\tstruct device_node *mtd_node;\n\tbool cfe_part = true;\n\tuint8_t *buf;\n\tint ret;\n\n\tmtd_node = mtd_get_of_node(master);\n\tif (!mtd_node)\n\t\treturn -EINVAL;\n\n\tbuf = kzalloc(master->erasesize, GFP_KERNEL);\n\tif (!buf)\n\t\treturn -ENOMEM;\n\n\tif (of_property_read_bool(mtd_node, \"brcm,no-cferam\"))\n\t\tcfe_part = false;\n\n\tret = parse_bcm_wfi(master, pparts, buf, 0, master->size, cfe_part);\n\n\tkfree(buf);\n\n\treturn ret;\n}\n\nstatic const struct of_device_id mtdsplit_bcm_wfi_of_match[] = {\n\t{ .compatible = \"brcm,wfi\" },\n\t{ },\n};\n\nstatic struct mtd_part_parser mtdsplit_bcm_wfi_parser = {\n\t.owner = THIS_MODULE,\n\t.name = \"bcm-wfi-fw\",\n\t.of_match_table = mtdsplit_bcm_wfi_of_match,\n\t.parse_fn = mtdsplit_parse_bcm_wfi,\n\t.type = MTD_PARSER_TYPE_FIRMWARE,\n};\n\nstatic int cferam_bootflag_value(const char *name, size_t name_len)\n{\n\tint rc = -ENOENT;\n\n\tif (name &&\n\t    (name_len >= CFE_MAGIC_LEN) &&\n\t    !memcmp(name, CFE_MAGIC_PFX, CFE_MAGIC_PFX_LEN)) {\n\t\trc = char_to_num(name[CFE_MAGIC_PFX_LEN + 0]) * 100;\n\t\trc += char_to_num(name[CFE_MAGIC_PFX_LEN + 1]) * 10;\n\t\trc += char_to_num(name[CFE_MAGIC_PFX_LEN + 2]) * 1;\n\t}\n\n\treturn rc;\n}\n\nstatic int mtdsplit_parse_bcm_wfi_split(struct mtd_info *master,\n\t\t\t\t\tconst struct mtd_partition **pparts,\n\t\t\t\t\tstruct mtd_part_parser_data *data)\n{\n\tstruct mtd_partition *parts;\n\tloff_t cfe_off;\n\tloff_t img1_off = 0;\n\tloff_t img2_off = master->size / 2;\n\tloff_t img1_size = (img2_off - img1_off);\n\tloff_t img2_size = (master->size - img2_off);\n\tloff_t active_off, inactive_off;\n\tloff_t active_size, inactive_size;\n\tconst char *inactive_name;\n\tuint8_t *buf;\n\tchar *cfe1_name = NULL, *cfe2_name = NULL;\n\tsize_t cfe1_size = 0, cfe2_size = 0;\n\tint ret;\n\tint bf1, bf2;\n\n\tbuf = kzalloc(master->erasesize, GFP_KERNEL);\n\tif (!buf)\n\t\treturn -ENOMEM;\n\n\tcfe_off = img1_off;\n\tret = jffs2_find_file(master, buf, CFERAM_NAME, CFERAM_NAME_LEN,\n\t\t\t      &cfe_off, img1_size, &cfe1_name, &cfe1_size);\n\n\tcfe_off = img2_off;\n\tret = jffs2_find_file(master, buf, CFERAM_NAME, CFERAM_NAME_LEN,\n\t\t\t      &cfe_off, img2_size, &cfe2_name, &cfe2_size);\n\n\tbf1 = cferam_bootflag_value(cfe1_name, cfe1_size);\n\tif (bf1 >= 0)\n\t\tprintk(\"cferam: bootflag1=%d\\n\", bf1);\n\n\tbf2 = cferam_bootflag_value(cfe2_name, cfe2_size);\n\tif (bf2 >= 0)\n\t\tprintk(\"cferam: bootflag2=%d\\n\", bf2);\n\n\tkfree(cfe1_name);\n\tkfree(cfe2_name);\n\n\tif (bf1 >= bf2) {\n\t\tactive_off = img1_off;\n\t\tactive_size = img1_size;\n\t\tinactive_off = img2_off;\n\t\tinactive_size = img2_size;\n\t\tinactive_name = PART_IMAGE_2;\n\t} else {\n\t\tactive_off = img2_off;\n\t\tactive_size = img2_size;\n\t\tinactive_off = img1_off;\n\t\tinactive_size = img1_size;\n\t\tinactive_name = PART_IMAGE_1;\n\t}\n\n\tret = parse_bcm_wfi(master, pparts, buf, active_off, active_size, true);\n\n\tkfree(buf);\n\n\tif (ret > 0) {\n\t\tparts = kzalloc((ret + 1) * sizeof(*parts), GFP_KERNEL);\n\t\tif (!parts)\n\t\t\treturn -ENOMEM;\n\n\t\tmemcpy(parts, *pparts, ret * sizeof(*parts));\n\t\tkfree(*pparts);\n\n\t\tparts[ret].name = inactive_name;\n\t\tparts[ret].offset = inactive_off;\n\t\tparts[ret].size = inactive_size;\n\t\tret++;\n\n\t\t*pparts = parts;\n\t} else {\n\t\tparts = kzalloc(BCM_WFI_SPLIT_PARTS * sizeof(*parts), GFP_KERNEL);\n\n\t\tparts[0].name = PART_IMAGE_1;\n\t\tparts[0].offset = img1_off;\n\t\tparts[0].size = img1_size;\n\n\t\tparts[1].name = PART_IMAGE_2;\n\t\tparts[1].offset = img2_off;\n\t\tparts[1].size = img2_size;\n\n\t\t*pparts = parts;\n\t}\n\n\treturn ret;\n}\n\nstatic const struct of_device_id mtdsplit_bcm_wfi_split_of_match[] = {\n\t{ .compatible = \"brcm,wfi-split\" },\n\t{ },\n};\n\nstatic struct mtd_part_parser mtdsplit_bcm_wfi_split_parser = {\n\t.owner = THIS_MODULE,\n\t.name = \"bcm-wfi-split-fw\",\n\t.of_match_table = mtdsplit_bcm_wfi_split_of_match,\n\t.parse_fn = mtdsplit_parse_bcm_wfi_split,\n\t.type = MTD_PARSER_TYPE_FIRMWARE,\n};\n\nstatic int sercomm_bootflag_value(struct mtd_info *mtd, uint8_t *buf)\n{\n\tsize_t retlen;\n\tloff_t offs;\n\tint rc;\n\n\tfor (offs = 0; offs < mtd->size; offs += mtd->erasesize) {\n\t\trc = mtd_read(mtd, offs, SERCOMM_MAGIC_LEN, &retlen, buf);\n\t\tif (rc || retlen != SERCOMM_MAGIC_LEN)\n\t\t\tcontinue;\n\n\t\tif (memcmp(buf, SERCOMM_MAGIC_PFX, SERCOMM_MAGIC_PFX_LEN))\n\t\t\tcontinue;\n\n\t\trc = char_to_num(buf[SERCOMM_MAGIC_PFX_LEN + 0]) * 100;\n\t\trc += char_to_num(buf[SERCOMM_MAGIC_PFX_LEN + 1]) * 10;\n\t\trc += char_to_num(buf[SERCOMM_MAGIC_PFX_LEN + 2]) * 1;\n\n\t\treturn rc;\n\t}\n\n\treturn -ENOENT;\n}\n\nstatic int mtdsplit_parse_ser_wfi(struct mtd_info *master,\n\t\t\t\t  const struct mtd_partition **pparts,\n\t\t\t\t  struct mtd_part_parser_data *data)\n{\n\tstruct mtd_partition *parts;\n\tstruct mtd_info *mtd_bf1, *mtd_bf2;\n\tloff_t img1_off = 0;\n\tloff_t img2_off = master->size / 2;\n\tloff_t img1_size = (img2_off - img1_off);\n\tloff_t img2_size = (master->size - img2_off);\n\tloff_t active_off, inactive_off;\n\tloff_t active_size, inactive_size;\n\tconst char *inactive_name;\n\tuint8_t *buf;\n\tint bf1, bf2;\n\tint ret;\n\n\tmtd_bf1 = get_mtd_device_nm(\"bootflag1\");\n\tif (IS_ERR(mtd_bf1))\n\t\treturn -ENOENT;\n\n\tmtd_bf2 = get_mtd_device_nm(\"bootflag2\");\n\tif (IS_ERR(mtd_bf2))\n\t\treturn -ENOENT;\n\n\tbuf = kzalloc(master->erasesize, GFP_KERNEL);\n\tif (!buf)\n\t\treturn -ENOMEM;\n\n\tbf1 = sercomm_bootflag_value(mtd_bf1, buf);\n\tif (bf1 >= 0)\n\t\tprintk(\"sercomm: bootflag1=%d\\n\", bf1);\n\n\tbf2 = sercomm_bootflag_value(mtd_bf2, buf);\n\tif (bf2 >= 0)\n\t\tprintk(\"sercomm: bootflag2=%d\\n\", bf2);\n\n\tif (bf1 == bf2 && bf2 >= 0) {\n\t\tstruct erase_info bf_erase;\n\n\t\tbf2 = -ENOENT;\n\t\tbf_erase.addr = 0;\n\t\tbf_erase.len = mtd_bf2->size;\n\t\tmtd_erase(mtd_bf2, &bf_erase);\n\t}\n\n\tif (bf1 >= bf2) {\n\t\tactive_off = img1_off;\n\t\tactive_size = img1_size;\n\t\tinactive_off = img2_off;\n\t\tinactive_size = img2_size;\n\t\tinactive_name = PART_IMAGE_2;\n\t} else {\n\t\tactive_off = img2_off;\n\t\tactive_size = img2_size;\n\t\tinactive_off = img1_off;\n\t\tinactive_size = img1_size;\n\t\tinactive_name = PART_IMAGE_1;\n\t}\n\n\tret = parse_bcm_wfi(master, pparts, buf, active_off, active_size, false);\n\n\tkfree(buf);\n\n\tif (ret > 0) {\n\t\tparts = kzalloc((ret + 1) * sizeof(*parts), GFP_KERNEL);\n\t\tif (!parts)\n\t\t\treturn -ENOMEM;\n\n\t\tmemcpy(parts, *pparts, ret * sizeof(*parts));\n\t\tkfree(*pparts);\n\n\t\tparts[ret].name = inactive_name;\n\t\tparts[ret].offset = inactive_off;\n\t\tparts[ret].size = inactive_size;\n\t\tret++;\n\n\t\t*pparts = parts;\n\t} else {\n\t\tparts = kzalloc(BCM_WFI_SPLIT_PARTS * sizeof(*parts), GFP_KERNEL);\n\n\t\tparts[0].name = PART_IMAGE_1;\n\t\tparts[0].offset = img1_off;\n\t\tparts[0].size = img1_size;\n\n\t\tparts[1].name = PART_IMAGE_2;\n\t\tparts[1].offset = img2_off;\n\t\tparts[1].size = img2_size;\n\n\t\t*pparts = parts;\n\t}\n\n\treturn ret;\n}\n\nstatic const struct of_device_id mtdsplit_ser_wfi_of_match[] = {\n\t{ .compatible = \"sercomm,wfi\" },\n\t{ },\n};\n\nstatic struct mtd_part_parser mtdsplit_ser_wfi_parser = {\n\t.owner = THIS_MODULE,\n\t.name = \"ser-wfi-fw\",\n\t.of_match_table = mtdsplit_ser_wfi_of_match,\n\t.parse_fn = mtdsplit_parse_ser_wfi,\n\t.type = MTD_PARSER_TYPE_FIRMWARE,\n};\n\nstatic int __init mtdsplit_bcm_wfi_init(void)\n{\n\tregister_mtd_parser(&mtdsplit_bcm_wfi_parser);\n\tregister_mtd_parser(&mtdsplit_bcm_wfi_split_parser);\n\tregister_mtd_parser(&mtdsplit_ser_wfi_parser);\n\n\treturn 0;\n}\n\nmodule_init(mtdsplit_bcm_wfi_init);\n"
  },
  {
    "path": "target/linux/generic/files/drivers/mtd/mtdsplit/mtdsplit_brnimage.c",
    "content": "/*\n *  Copyright (C) 2012 John Crispin <blogic@openwrt.org>\n *  Copyright (C) 2015 Martin Blumenstingl <martin.blumenstingl@googlemail.com>\n *\n *  This program is free software; you can redistribute it and/or modify it\n *  under the terms of the GNU General Public License version 2 as published\n *  by the Free Software Foundation.\n *\n */\n\n#include <linux/module.h>\n#include <linux/init.h>\n#include <linux/kernel.h>\n#include <linux/slab.h>\n#include <linux/mtd/mtd.h>\n#include <linux/mtd/partitions.h>\n#include <linux/byteorder/generic.h>\n\n#include \"mtdsplit.h\"\n\n#define BRNIMAGE_NR_PARTS\t2\n\n#define BRNIMAGE_ALIGN_BYTES\t0x400\n#define BRNIMAGE_FOOTER_SIZE\t12\n\n#define BRNIMAGE_MIN_OVERHEAD\t(BRNIMAGE_FOOTER_SIZE)\n#define BRNIMAGE_MAX_OVERHEAD\t(BRNIMAGE_ALIGN_BYTES + BRNIMAGE_FOOTER_SIZE)\n\nstatic int mtdsplit_parse_brnimage(struct mtd_info *master,\n\t\t\t\tconst struct mtd_partition **pparts,\n\t\t\t\tstruct mtd_part_parser_data *data)\n{\n\tstruct mtd_partition *parts;\n\tuint32_t buf;\n\tunsigned long rootfs_offset, rootfs_size, kernel_size;\n\tsize_t len;\n\tint ret = 0;\n\n\tfor (rootfs_offset = 0; rootfs_offset < master->size;\n\t     rootfs_offset += BRNIMAGE_ALIGN_BYTES) {\n\t\tret = mtd_check_rootfs_magic(master, rootfs_offset, NULL);\n\t\tif (!ret)\n\t\t\tbreak;\n\t}\n\n\tif (ret)\n\t\treturn ret;\n\n\tif (rootfs_offset >= master->size)\n\t\treturn -EINVAL;\n\n\tret = mtd_read(master, rootfs_offset - BRNIMAGE_FOOTER_SIZE, 4, &len,\n\t\t\t(void *)&buf);\n\tif (ret)\n\t\treturn ret;\n\n\tif (len != 4)\n\t\treturn -EIO;\n\n\tkernel_size = le32_to_cpu(buf);\n\n\tif (kernel_size > (rootfs_offset - BRNIMAGE_MIN_OVERHEAD))\n\t\treturn -EINVAL;\n\n\tif (kernel_size < (rootfs_offset - BRNIMAGE_MAX_OVERHEAD))\n\t\treturn -EINVAL;\n\n\t/*\n\t * The footer must be untouched as it contains the checksum of the\n\t * original brnImage (kernel + squashfs)!\n\t */\n\trootfs_size = master->size - rootfs_offset - BRNIMAGE_FOOTER_SIZE;\n\n\tparts = kzalloc(BRNIMAGE_NR_PARTS * sizeof(*parts), GFP_KERNEL);\n\tif (!parts)\n\t\treturn -ENOMEM;\n\n\tparts[0].name = KERNEL_PART_NAME;\n\tparts[0].offset = 0;\n\tparts[0].size = kernel_size;\n\n\tparts[1].name = ROOTFS_PART_NAME;\n\tparts[1].offset = rootfs_offset;\n\tparts[1].size = rootfs_size;\n\n\t*pparts = parts;\n\treturn BRNIMAGE_NR_PARTS;\n}\n\nstatic struct mtd_part_parser mtdsplit_brnimage_parser = {\n\t.owner = THIS_MODULE,\n\t.name = \"brnimage-fw\",\n\t.parse_fn = mtdsplit_parse_brnimage,\n\t.type = MTD_PARSER_TYPE_FIRMWARE,\n};\n\nstatic int __init mtdsplit_brnimage_init(void)\n{\n\tregister_mtd_parser(&mtdsplit_brnimage_parser);\n\n\treturn 0;\n}\n\nsubsys_initcall(mtdsplit_brnimage_init);\n"
  },
  {
    "path": "target/linux/generic/files/drivers/mtd/mtdsplit/mtdsplit_cfe_bootfs.c",
    "content": "// SPDX-License-Identifier: GPL-2.0-only\n/*\n * Copyright (C) 2021 Rafał Miłecki <rafal@milecki.pl>\n */\n\n#include <linux/init.h>\n#include <linux/jffs2.h>\n#include <linux/kernel.h>\n#include <linux/module.h>\n#include <linux/mtd/mtd.h>\n#include <linux/mtd/partitions.h>\n#include <linux/of.h>\n#include <linux/slab.h>\n\n#include \"mtdsplit.h\"\n\n#define je16_to_cpu(x) ((x).v16)\n#define je32_to_cpu(x) ((x).v32)\n\n#define NR_PARTS\t\t2\n\nstatic int mtdsplit_cfe_bootfs_parse(struct mtd_info *mtd,\n\t\t\t\t     const struct mtd_partition **pparts,\n\t\t\t\t     struct mtd_part_parser_data *data)\n{\n\tstruct jffs2_raw_dirent node;\n\tenum mtdsplit_part_type type;\n\tstruct mtd_partition *parts;\n\tsize_t rootfs_offset;\n\tsize_t retlen;\n\tsize_t offset;\n\tint err;\n\n\t/* Don't parse backup partitions */\n\tif (strcmp(mtd->name, \"firmware\"))\n\t\treturn -EINVAL;\n\n\t/* Find the end of JFFS2 bootfs partition */\n\toffset = 0;\n\tdo {\n\t\terr = mtd_read(mtd, offset, sizeof(node), &retlen, (void *)&node);\n\t\tif (err || retlen != sizeof(node))\n\t\t\tbreak;\n\n\t\tif (je16_to_cpu(node.magic) != JFFS2_MAGIC_BITMASK)\n\t\t\tbreak;\n\n\t\toffset += je32_to_cpu(node.totlen);\n\t\toffset = (offset + 0x3) & ~0x3;\n\t} while (offset < mtd->size);\n\n\t/* Find rootfs partition that follows the bootfs */\n\terr = mtd_find_rootfs_from(mtd, mtd->erasesize, mtd->size, &rootfs_offset, &type);\n\tif (err)\n\t\treturn err;\n\n\tparts = kzalloc(NR_PARTS * sizeof(*parts), GFP_KERNEL);\n\tif (!parts)\n\t\treturn -ENOMEM;\n\n\tparts[0].name = \"bootfs\";\n\tparts[0].offset = 0;\n\tparts[0].size = rootfs_offset;\n\n\tif (type == MTDSPLIT_PART_TYPE_UBI)\n\t\tparts[1].name = UBI_PART_NAME;\n\telse\n\t\tparts[1].name = ROOTFS_PART_NAME;\n\tparts[1].offset = rootfs_offset;\n\tparts[1].size = mtd->size - rootfs_offset;\n\n\t*pparts = parts;\n\n\treturn NR_PARTS;\n}\n\nstatic const struct of_device_id mtdsplit_cfe_bootfs_of_match_table[] = {\n\t{ .compatible = \"brcm,bcm4908-firmware\" },\n\t{},\n};\nMODULE_DEVICE_TABLE(of, mtdsplit_cfe_bootfs_of_match_table);\n\nstatic struct mtd_part_parser mtdsplit_cfe_bootfs_parser = {\n\t.owner = THIS_MODULE,\n\t.name = \"cfe-bootfs\",\n\t.of_match_table = mtdsplit_cfe_bootfs_of_match_table,\n\t.parse_fn = mtdsplit_cfe_bootfs_parse,\n};\n\nmodule_mtd_part_parser(mtdsplit_cfe_bootfs_parser);\n"
  },
  {
    "path": "target/linux/generic/files/drivers/mtd/mtdsplit/mtdsplit_elf.c",
    "content": "/* SPDX-License-Identifier: GPL-2.0-only */\n/*\n *  MTD splitter for ELF loader firmware partitions\n *\n *  Copyright (C) 2020 Sander Vanheule <sander@svanheule.net>\n *\n *  This program is free software; you can redistribute it and/or modify it\n *  under the terms of the GNU General Public License as published by the Free\n *  Software Foundation; version 2.\n *\n *  To parse the ELF kernel loader, a small ELF parser is used that can\n *  handle both ELF32 or ELF64 class loaders. The splitter assumes that the\n *  kernel is always located before the rootfs, whether it is embedded in the\n *  loader or not.\n *\n *  The kernel image is preferably embedded inside the ELF loader, so the end\n *  of the loader equals the end of the kernel partition. This is due to the\n *  way mtd_find_rootfs_from searches for the the rootfs:\n *  - if the kernel image is embedded in the loader, the appended rootfs may\n *    follow the loader immediately, within the same erase block.\n *  - if the kernel image is not embedded in the loader, but placed at some\n *    offset behind the loader (OKLI-style loader), the rootfs must be\n *    aligned to an erase-block after the loader and kernel image.\n */\n\n#include <linux/module.h>\n#include <linux/init.h>\n#include <linux/kernel.h>\n#include <linux/slab.h>\n#include <linux/mtd/mtd.h>\n#include <linux/mtd/partitions.h>\n#include <linux/of.h>\n#include <linux/byteorder/generic.h>\n\n#include \"mtdsplit.h\"\n\n#define ELF_NR_PARTS\t2\n\n#define ELF_MAGIC\t0x7f454c46 /* 0x7f E L F */\n#define ELF_CLASS_32\t1\n#define ELF_CLASS_64\t2\n\nstruct elf_header_ident {\n\tuint32_t magic;\n\tuint8_t class;\n\tuint8_t data;\n\tuint8_t version;\n\tuint8_t osabi;\n\tuint8_t abiversion;\n\tuint8_t pad[7];\n};\n\nstruct elf_header_32 {\n\tuint16_t type;\n\tuint16_t machine;\n\tuint32_t version;\n\tuint32_t entry;\n\tuint32_t phoff;\n\tuint32_t shoff;\n\tuint32_t flags;\n\tuint16_t ehsize;\n\tuint16_t phentsize;\n\tuint16_t phnum;\n\tuint16_t shentsize;\n\tuint16_t shnum;\n\tuint16_t shstrndx;\n};\n\nstruct elf_header_64 {\n\tuint16_t type;\n\tuint16_t machine;\n\tuint32_t version;\n\tuint64_t entry;\n\tuint64_t phoff;\n\tuint64_t shoff;\n\tuint32_t flags;\n\tuint16_t ehsize;\n\tuint16_t phentsize;\n\tuint16_t phnum;\n\tuint16_t shentsize;\n\tuint16_t shnum;\n\tuint16_t shstrndx;\n};\n\nstruct elf_header {\n\tstruct elf_header_ident ident;\n\tunion {\n\t\tstruct elf_header_32 elf32;\n\t\tstruct elf_header_64 elf64;\n\t};\n};\n\nstruct elf_program_header_32 {\n\tuint32_t type;\n\tuint32_t offset;\n\tuint32_t vaddr;\n\tuint32_t paddr;\n\tuint32_t filesize;\n\tuint32_t memsize;\n\tuint32_t flags;\n};\n\nstruct elf_program_header_64 {\n\tuint32_t type;\n\tuint32_t flags;\n\tuint64_t offset;\n\tuint64_t vaddr;\n\tuint64_t paddr;\n\tuint64_t filesize;\n\tuint64_t memsize;\n};\n\n\nstatic int mtdsplit_elf_read_mtd(struct mtd_info *mtd, size_t offset,\n\t\t\t\t uint8_t *dst, size_t len)\n{\n\tsize_t retlen;\n\tint ret;\n\n\tret = mtd_read(mtd, offset, len, &retlen, dst);\n\tif (ret) {\n\t\tpr_debug(\"read error in \\\"%s\\\"\\n\", mtd->name);\n\t\treturn ret;\n\t}\n\n\tif (retlen != len) {\n\t\tpr_debug(\"short read in \\\"%s\\\"\\n\", mtd->name);\n\t\treturn -EIO;\n\t}\n\n\treturn 0;\n}\n\nstatic int elf32_determine_size(struct mtd_info *mtd, struct elf_header *hdr,\n\t\t\t\tsize_t *size)\n{\n\tstruct elf_header_32 *hdr32 = &(hdr->elf32);\n\tint err;\n\tsize_t section_end, ph_table_end, ph_entry;\n\tstruct elf_program_header_32 ph;\n\n\t*size = 0;\n\n\tif (hdr32->shoff > 0) {\n\t\t*size = hdr32->shoff + hdr32->shentsize * hdr32->shnum;\n\t\treturn 0;\n\t}\n\n\tph_entry = hdr32->phoff;\n\tph_table_end = hdr32->phoff + hdr32->phentsize * hdr32->phnum;\n\n\twhile (ph_entry < ph_table_end) {\n\t\terr = mtdsplit_elf_read_mtd(mtd, ph_entry, (uint8_t *)(&ph),\n\t\t\t\t\t    sizeof(ph));\n\t\tif (err)\n\t\t\treturn err;\n\n\t\tsection_end = ph.offset + ph.filesize;\n\t\tif (section_end > *size)\n\t\t\t*size = section_end;\n\n\t\tph_entry += hdr32->phentsize;\n\t}\n\n\treturn 0;\n}\n\nstatic int elf64_determine_size(struct mtd_info *mtd, struct elf_header *hdr,\n\t\t\t\tsize_t *size)\n{\n\tstruct elf_header_64 *hdr64 = &(hdr->elf64);\n\tint err;\n\tsize_t section_end, ph_table_end, ph_entry;\n\tstruct elf_program_header_64 ph;\n\n\t*size = 0;\n\n\tif (hdr64->shoff > 0) {\n\t\t*size = hdr64->shoff + hdr64->shentsize * hdr64->shnum;\n\t\treturn 0;\n\t}\n\n\tph_entry = hdr64->phoff;\n\tph_table_end = hdr64->phoff + hdr64->phentsize * hdr64->phnum;\n\n\twhile (ph_entry < ph_table_end) {\n\t\terr = mtdsplit_elf_read_mtd(mtd, ph_entry, (uint8_t *)(&ph),\n\t\t\t\t\t    sizeof(ph));\n\t\tif (err)\n\t\t\treturn err;\n\n\t\tsection_end = ph.offset + ph.filesize;\n\t\tif (section_end > *size)\n\t\t\t*size = section_end;\n\n\t\tph_entry += hdr64->phentsize;\n\t}\n\n\treturn 0;\n}\n\nstatic int mtdsplit_parse_elf(struct mtd_info *mtd,\n\t\t\t      const struct mtd_partition **pparts,\n\t\t\t      struct mtd_part_parser_data *data)\n{\n\tstruct elf_header hdr;\n\tsize_t loader_size, rootfs_offset;\n\tenum mtdsplit_part_type type;\n\tstruct mtd_partition *parts;\n\tint err;\n\n\terr = mtdsplit_elf_read_mtd(mtd, 0, (uint8_t *)&hdr, sizeof(hdr));\n\tif (err)\n\t\treturn err;\n\n\tif (be32_to_cpu(hdr.ident.magic) != ELF_MAGIC) {\n\t\tpr_debug(\"invalid ELF magic %08x\\n\",\n\t\t\t be32_to_cpu(hdr.ident.magic));\n\t\treturn -EINVAL;\n\t}\n\n\tswitch (hdr.ident.class) {\n\tcase ELF_CLASS_32:\n\t\terr = elf32_determine_size(mtd, &hdr, &loader_size);\n\t\tbreak;\n\tcase ELF_CLASS_64:\n\t\terr = elf64_determine_size(mtd, &hdr, &loader_size);\n\t\tbreak;\n\tdefault:\n\t\tpr_debug(\"invalid ELF class %i\\n\", hdr.ident.class);\n\t\terr = -EINVAL;\n\t}\n\n\tif (err)\n\t\treturn err;\n\n\terr = mtd_find_rootfs_from(mtd, loader_size, mtd->size,\n\t\t\t\t   &rootfs_offset, &type);\n\tif (err)\n\t\treturn err;\n\n\tif (rootfs_offset == mtd->size) {\n\t\tpr_debug(\"no rootfs found in \\\"%s\\\"\\n\", mtd->name);\n\t\treturn -ENODEV;\n\t}\n\n\tparts = kzalloc(ELF_NR_PARTS * sizeof(*parts), GFP_KERNEL);\n\tif (!parts)\n\t\treturn -ENOMEM;\n\n\tparts[0].name = KERNEL_PART_NAME;\n\tparts[0].offset = 0;\n\tparts[0].size = rootfs_offset;\n\n\tif (type == MTDSPLIT_PART_TYPE_UBI)\n\t\tparts[1].name = UBI_PART_NAME;\n\telse\n\t\tparts[1].name = ROOTFS_PART_NAME;\n\tparts[1].offset = rootfs_offset;\n\tparts[1].size = mtd->size - rootfs_offset;\n\n\t*pparts = parts;\n\treturn ELF_NR_PARTS;\n}\n\nstatic const struct of_device_id mtdsplit_elf_of_match_table[] = {\n\t{ .compatible = \"openwrt,elf\" },\n\t{},\n};\nMODULE_DEVICE_TABLE(of, mtdsplit_elf_of_match_table);\n\nstatic struct mtd_part_parser mtdsplit_elf_parser = {\n\t.owner = THIS_MODULE,\n\t.name = \"elf-loader-fw\",\n\t.of_match_table = mtdsplit_elf_of_match_table,\n\t.parse_fn = mtdsplit_parse_elf,\n\t.type = MTD_PARSER_TYPE_FIRMWARE,\n};\n\nstatic int __init mtdsplit_elf_init(void)\n{\n\tregister_mtd_parser(&mtdsplit_elf_parser);\n\n\treturn 0;\n}\n\nsubsys_initcall(mtdsplit_elf_init);\n"
  },
  {
    "path": "target/linux/generic/files/drivers/mtd/mtdsplit/mtdsplit_eva.c",
    "content": "/*\n *  Copyright (C) 2012 John Crispin <blogic@openwrt.org>\n *  Copyright (C) 2015 Martin Blumenstingl <martin.blumenstingl@googlemail.com>\n *\n *  This program is free software; you can redistribute it and/or modify it\n *  under the terms of the GNU General Public License version 2 as published\n *  by the Free Software Foundation.\n *\n */\n\n#include <linux/module.h>\n#include <linux/init.h>\n#include <linux/kernel.h>\n#include <linux/slab.h>\n#include <linux/mtd/mtd.h>\n#include <linux/mtd/partitions.h>\n#include <linux/byteorder/generic.h>\n#include <linux/of.h>\n\n#include \"mtdsplit.h\"\n\n#define EVA_NR_PARTS\t\t2\n#define EVA_MAGIC\t\t0xfeed1281\n#define EVA_FOOTER_SIZE\t\t0x18\n#define EVA_DUMMY_SQUASHFS_SIZE\t0x100\n\nstruct eva_image_header {\n\tuint32_t\tmagic;\n\tuint32_t\tsize;\n};\n\nstatic int mtdsplit_parse_eva(struct mtd_info *master,\n\t\t\t\tconst struct mtd_partition **pparts,\n\t\t\t\tstruct mtd_part_parser_data *data)\n{\n\tstruct mtd_partition *parts;\n\tstruct eva_image_header hdr;\n\tsize_t retlen;\n\tunsigned long kernel_size, rootfs_offset;\n\tint err;\n\n\terr = mtd_read(master, 0, sizeof(hdr), &retlen, (void *) &hdr);\n\tif (err)\n\t\treturn err;\n\n\tif (retlen != sizeof(hdr))\n\t\treturn -EIO;\n\n\tif (le32_to_cpu(hdr.magic) != EVA_MAGIC)\n\t\treturn -EINVAL;\n\n\tkernel_size = le32_to_cpu(hdr.size) + EVA_FOOTER_SIZE;\n\n\t/* rootfs starts at the next 0x10000 boundary: */\n\trootfs_offset = round_up(kernel_size, 0x10000);\n\n\t/* skip the dummy EVA squashfs partition (with wrong endianness): */\n\trootfs_offset += EVA_DUMMY_SQUASHFS_SIZE;\n\n\tif (rootfs_offset >= master->size)\n\t\treturn -EINVAL;\n\n\terr = mtd_check_rootfs_magic(master, rootfs_offset, NULL);\n\tif (err)\n\t\treturn err;\n\n\tparts = kzalloc(EVA_NR_PARTS * sizeof(*parts), GFP_KERNEL);\n\tif (!parts)\n\t\treturn -ENOMEM;\n\n\tparts[0].name = KERNEL_PART_NAME;\n\tparts[0].offset = 0;\n\tparts[0].size = kernel_size;\n\n\tparts[1].name = ROOTFS_PART_NAME;\n\tparts[1].offset = rootfs_offset;\n\tparts[1].size = master->size - rootfs_offset;\n\n\t*pparts = parts;\n\treturn EVA_NR_PARTS;\n}\n\nstatic const struct of_device_id mtdsplit_eva_of_match_table[] = {\n\t{ .compatible = \"avm,eva-firmware\" },\n\t{},\n};\n\nstatic struct mtd_part_parser mtdsplit_eva_parser = {\n\t.owner = THIS_MODULE,\n\t.name = \"eva-fw\",\n\t.of_match_table = mtdsplit_eva_of_match_table,\n\t.parse_fn = mtdsplit_parse_eva,\n\t.type = MTD_PARSER_TYPE_FIRMWARE,\n};\n\nstatic int __init mtdsplit_eva_init(void)\n{\n\tregister_mtd_parser(&mtdsplit_eva_parser);\n\n\treturn 0;\n}\n\nsubsys_initcall(mtdsplit_eva_init);\n"
  },
  {
    "path": "target/linux/generic/files/drivers/mtd/mtdsplit/mtdsplit_fit.c",
    "content": "/*\n * Copyright (c) 2015 The Linux Foundation\n * Copyright (C) 2014 Gabor Juhos <juhosg@openwrt.org>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n */\n\n#include <linux/module.h>\n#include <linux/mtd/mtd.h>\n#include <linux/mtd/partitions.h>\n#include <linux/types.h>\n#include <linux/byteorder/generic.h>\n#include <linux/slab.h>\n#include <linux/libfdt.h>\n#include <linux/of_fdt.h>\n\n#include \"mtdsplit.h\"\n\n// string macros from git://git.denx.de/u-boot.git/include/image.h\n\n#define FIT_IMAGES_PATH         \"/images\"\n#define FIT_DATA_PROP           \"data\"\n#define FIT_DATA_POSITION_PROP  \"data-position\"\n#define FIT_DATA_OFFSET_PROP    \"data-offset\"\n#define FIT_DATA_SIZE_PROP      \"data-size\"\n\n// functions from git://git.denx.de/u-boot.git/common/image-fit.c\n\n/**\n * fit_image_get_data - get data property and its size for a given component image node\n * @fit: pointer to the FIT format image header\n * @noffset: component image node offset\n * @data: double pointer to void, will hold data property's data address\n * @size: pointer to size_t, will hold data property's data size\n *\n * fit_image_get_data() finds data property in a given component image node.\n * If the property is found its data start address and size are returned to\n * the caller.\n *\n * returns:\n *     0, on success\n *     -1, on failure\n */\nstatic int fit_image_get_data(const void *fit, int noffset,\n\t\tconst void **data, size_t *size)\n{\n\tint len;\n\n\t*data = fdt_getprop(fit, noffset, FIT_DATA_PROP, &len);\n\tif (*data == NULL) {\n\t\t*size = 0;\n\t\treturn -1;\n\t}\n\n\t*size = len;\n\treturn 0;\n}\n\n\n/**\n * Get 'data-offset' property from a given image node.\n *\n * @fit: pointer to the FIT image header\n * @noffset: component image node offset\n * @data_offset: holds the data-offset property\n *\n * returns:\n *     0, on success\n *     -ENOENT if the property could not be found\n */\nstatic int fit_image_get_data_offset(const void *fit, int noffset, int *data_offset)\n{\n\tconst fdt32_t *val;\n\n\tval = fdt_getprop(fit, noffset, FIT_DATA_OFFSET_PROP, NULL);\n\tif (!val)\n\t\treturn -ENOENT;\n\n\t*data_offset = fdt32_to_cpu(*val);\n\n\treturn 0;\n}\n\n/**\n * Get 'data-position' property from a given image node.\n *\n * @fit: pointer to the FIT image header\n * @noffset: component image node offset\n * @data_position: holds the data-position property\n *\n * returns:\n *     0, on success\n *     -ENOENT if the property could not be found\n */\nstatic int fit_image_get_data_position(const void *fit, int noffset,\n\t\t\t\tint *data_position)\n{\n\tconst fdt32_t *val;\n\n\tval = fdt_getprop(fit, noffset, FIT_DATA_POSITION_PROP, NULL);\n\tif (!val)\n\t\treturn -ENOENT;\n\n\t*data_position = fdt32_to_cpu(*val);\n\n\treturn 0;\n}\n\n/**\n * Get 'data-size' property from a given image node.\n *\n * @fit: pointer to the FIT image header\n * @noffset: component image node offset\n * @data_size: holds the data-size property\n *\n * returns:\n *     0, on success\n *     -ENOENT if the property could not be found\n */\nstatic int fit_image_get_data_size(const void *fit, int noffset, int *data_size)\n{\n\tconst fdt32_t *val;\n\n\tval = fdt_getprop(fit, noffset, FIT_DATA_SIZE_PROP, NULL);\n\tif (!val)\n\t\treturn -ENOENT;\n\n\t*data_size = fdt32_to_cpu(*val);\n\n\treturn 0;\n}\n\n/**\n * fit_image_get_data_and_size - get data and its size including\n *\t\t\t\t both embedded and external data\n * @fit: pointer to the FIT format image header\n * @noffset: component image node offset\n * @data: double pointer to void, will hold data property's data address\n * @size: pointer to size_t, will hold data property's data size\n *\n * fit_image_get_data_and_size() finds data and its size including\n * both embedded and external data. If the property is found\n * its data start address and size are returned to the caller.\n *\n * returns:\n *     0, on success\n *     otherwise, on failure\n */\nstatic int fit_image_get_data_and_size(const void *fit, int noffset,\n\t\t\t\tconst void **data, size_t *size)\n{\n\tbool external_data = false;\n\tint offset;\n\tint len;\n\tint ret;\n\n\tif (!fit_image_get_data_position(fit, noffset, &offset)) {\n\t\texternal_data = true;\n\t} else if (!fit_image_get_data_offset(fit, noffset, &offset)) {\n\t\texternal_data = true;\n\t\t/*\n\t\t * For FIT with external data, figure out where\n\t\t * the external images start. This is the base\n\t\t * for the data-offset properties in each image.\n\t\t */\n\t\toffset += ((fdt_totalsize(fit) + 3) & ~3);\n\t}\n\n\tif (external_data) {\n\t\tret = fit_image_get_data_size(fit, noffset, &len);\n\t\tif (!ret) {\n\t\t\t*data = fit + offset;\n\t\t\t*size = len;\n\t\t}\n\t} else {\n\t\tret = fit_image_get_data(fit, noffset, data, size);\n\t}\n\n\treturn ret;\n}\n\nstatic int\nmtdsplit_fit_parse(struct mtd_info *mtd,\n\t\t   const struct mtd_partition **pparts,\n\t           struct mtd_part_parser_data *data)\n{\n\tstruct device_node *np = mtd_get_of_node(mtd);\n\tconst char *cmdline_match = NULL;\n\tstruct fdt_header hdr;\n\tsize_t hdr_len, retlen;\n\tsize_t offset;\n\tsize_t fit_offset, fit_size;\n\tsize_t rootfs_offset, rootfs_size;\n\tsize_t data_size, img_total, max_size = 0;\n\tstruct mtd_partition *parts;\n\tint ret, ndepth, noffset, images_noffset;\n\tconst void *img_data;\n\tvoid *fit;\n\n\tof_property_read_string(np, \"openwrt,cmdline-match\", &cmdline_match);\n\tif (cmdline_match && !strstr(saved_command_line, cmdline_match))\n\t\treturn -ENODEV;\n\n\thdr_len = sizeof(struct fdt_header);\n\n\t/* Parse the MTD device & search for the FIT image location */\n\tfor(offset = 0; offset + hdr_len <= mtd->size; offset += mtd->erasesize) {\n\t\tret = mtd_read(mtd, offset, hdr_len, &retlen, (void*) &hdr);\n\t\tif (ret) {\n\t\t\tpr_err(\"read error in \\\"%s\\\" at offset 0x%llx\\n\",\n\t\t\t       mtd->name, (unsigned long long) offset);\n\t\t\treturn ret;\n\t\t}\n\n\t\tif (retlen != hdr_len) {\n\t\t\tpr_err(\"short read in \\\"%s\\\"\\n\", mtd->name);\n\t\t\treturn -EIO;\n\t\t}\n\n\t\t/* Check the magic - see if this is a FIT image */\n\t\tif (be32_to_cpu(hdr.magic) != OF_DT_HEADER) {\n\t\t\tpr_debug(\"no valid FIT image found in \\\"%s\\\" at offset %llx\\n\",\n\t\t\t\t mtd->name, (unsigned long long) offset);\n\t\t\tcontinue;\n\t\t}\n\n\t\t/* We found a FIT image. Let's keep going */\n\t\tbreak;\n\t}\n\n\tfit_offset = offset;\n\tfit_size = be32_to_cpu(hdr.totalsize);\n\n\tif (fit_size == 0) {\n\t\tpr_err(\"FIT image in \\\"%s\\\" at offset %llx has null size\\n\",\n\t\t       mtd->name, (unsigned long long) fit_offset);\n\t\treturn -ENODEV;\n\t}\n\n\t/*\n\t * Classic uImage.FIT has all data embedded into the FDT\n\t * data structure. Hence the total size of the image equals\n\t * the total size of the FDT structure.\n\t * Modern uImage.FIT may have only references to data in FDT,\n\t * hence we need to parse FDT structure to find the end of the\n\t * last external data refernced.\n\t */\n\tif (fit_size > 0x1000) {\n\t\tenum mtdsplit_part_type type;\n\n\t\t/* Search for the rootfs partition after the FIT image */\n\t\tret = mtd_find_rootfs_from(mtd, fit_offset + fit_size, mtd->size,\n\t\t\t\t\t   &rootfs_offset, &type);\n\t\tif (ret) {\n\t\t\tpr_info(\"no rootfs found after FIT image in \\\"%s\\\"\\n\",\n\t\t\t\tmtd->name);\n\t\t\treturn ret;\n\t\t}\n\n\t\trootfs_size = mtd->size - rootfs_offset;\n\n\t\tparts = kzalloc(2 * sizeof(*parts), GFP_KERNEL);\n\t\tif (!parts)\n\t\t\treturn -ENOMEM;\n\n\t\tparts[0].name = KERNEL_PART_NAME;\n\t\tparts[0].offset = fit_offset;\n\t\tparts[0].size = mtd_rounddown_to_eb(fit_size, mtd) + mtd->erasesize;\n\n\t\tif (type == MTDSPLIT_PART_TYPE_UBI)\n\t\t\tparts[1].name = UBI_PART_NAME;\n\t\telse\n\t\t\tparts[1].name = ROOTFS_PART_NAME;\n\t\tparts[1].offset = rootfs_offset;\n\t\tparts[1].size = rootfs_size;\n\n\t\t*pparts = parts;\n\n\t\treturn 2;\n\t} else {\n\t\t/* Search for rootfs_data after FIT external data */\n\t\tfit = kzalloc(fit_size, GFP_KERNEL);\n\t\tret = mtd_read(mtd, offset, fit_size, &retlen, fit);\n\t\tif (ret) {\n\t\t\tpr_err(\"read error in \\\"%s\\\" at offset 0x%llx\\n\",\n\t\t\t       mtd->name, (unsigned long long) offset);\n\t\t\treturn ret;\n\t\t}\n\n\t\timages_noffset = fdt_path_offset(fit, FIT_IMAGES_PATH);\n\t\tif (images_noffset < 0) {\n\t\t\tpr_err(\"Can't find images parent node '%s' (%s)\\n\",\n\t\t\tFIT_IMAGES_PATH, fdt_strerror(images_noffset));\n\t\t\treturn -ENODEV;\n\t\t}\n\n\t\tfor (ndepth = 0,\n\t\t     noffset = fdt_next_node(fit, images_noffset, &ndepth);\n\t\t     (noffset >= 0) && (ndepth > 0);\n\t\t     noffset = fdt_next_node(fit, noffset, &ndepth)) {\n\t\t\tif (ndepth == 1) {\n\t\t\t\tret = fit_image_get_data_and_size(fit, noffset, &img_data, &data_size);\n\t\t\t\tif (ret)\n\t\t\t\t\treturn 0;\n\n\t\t\t\timg_total = data_size + (img_data - fit);\n\n\t\t\t\tmax_size = (max_size > img_total) ? max_size : img_total;\n\t\t\t}\n\t\t}\n\n\t\tparts = kzalloc(sizeof(*parts), GFP_KERNEL);\n\t\tif (!parts)\n\t\t\treturn -ENOMEM;\n\n\t\tparts[0].name = ROOTFS_SPLIT_NAME;\n\t\tparts[0].offset = fit_offset + mtd_rounddown_to_eb(max_size, mtd) + mtd->erasesize;\n\t\tparts[0].size = mtd->size - parts[0].offset;\n\n\t\t*pparts = parts;\n\n\t\tkfree(fit);\n\n\t\treturn 1;\n\t}\n}\n\nstatic const struct of_device_id mtdsplit_fit_of_match_table[] = {\n\t{ .compatible = \"denx,fit\" },\n\t{},\n};\n\nstatic struct mtd_part_parser uimage_parser = {\n\t.owner = THIS_MODULE,\n\t.name = \"fit-fw\",\n\t.of_match_table = mtdsplit_fit_of_match_table,\n\t.parse_fn = mtdsplit_fit_parse,\n\t.type = MTD_PARSER_TYPE_FIRMWARE,\n};\n\n/**************************************************\n * Init\n **************************************************/\n\nstatic int __init mtdsplit_fit_init(void)\n{\n\tregister_mtd_parser(&uimage_parser);\n\n\treturn 0;\n}\n\nmodule_init(mtdsplit_fit_init);\n"
  },
  {
    "path": "target/linux/generic/files/drivers/mtd/mtdsplit/mtdsplit_jimage.c",
    "content": "/*\n *  Copyright (C) 2018 Paweł Dembicki <paweldembicki@gmail.com> \n *\n *  Based on: mtdsplit_uimage.c\n *  Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>\n *\n *  This program is free software; you can redistribute it and/or modify it\n *  under the terms of the GNU General Public License version 2 as published\n *  by the Free Software Foundation.\n *\n */\n\n#define pr_fmt(fmt)\tKBUILD_MODNAME \": \" fmt\n\n#include <linux/module.h>\n#include <linux/init.h>\n#include <linux/kernel.h>\n#include <linux/slab.h>\n#include <linux/vmalloc.h>\n#include <linux/mtd/mtd.h>\n#include <linux/mtd/partitions.h>\n#include <linux/byteorder/generic.h>\n#include <linux/of.h>\n\n#include \"mtdsplit.h\"\n\n#define MAX_HEADER_LEN ( STAG_SIZE + SCH2_SIZE )\n\n#define STAG_SIZE 16\n#define STAG_ID 0x04\n#define STAG_MAGIC 0x2B24\n\n#define SCH2_SIZE 40\n#define SCH2_MAGIC 0x2124\n#define SCH2_VER 0x02\n\n/*\n * Jboot image header,\n * all data in little endian.\n */\n\nstruct jimage_header\t\t//stag + sch2 jboot joined headers\n{\n\tuint8_t stag_cmark;\t\t// in factory 0xFF , in sysupgrade must be the same as stag_id\n\tuint8_t stag_id;\t\t// 0x04\n\tuint16_t stag_magic;\t\t//magic 0x2B24\n\tuint32_t stag_time_stamp;\t// timestamp calculated in jboot way\n\tuint32_t stag_image_length;\t// lentgh of kernel + sch2 header\n\tuint16_t stag_image_checksum;\t// negated jboot_checksum of sch2 + kernel\n\tuint16_t stag_tag_checksum;\t// negated jboot_checksum of stag header data\n\tuint16_t sch2_magic;\t\t// magic 0x2124\n\tuint8_t sch2_cp_type;\t// 0x00 for flat, 0x01 for jz, 0x02 for gzip, 0x03 for lzma\n\tuint8_t sch2_version;\t// 0x02 for sch2\n\tuint32_t sch2_ram_addr;\t// ram entry address\n\tuint32_t sch2_image_len;\t// kernel image length\n\tuint32_t sch2_image_crc32;\t// kernel image crc\n\tuint32_t sch2_start_addr;\t// ram start address\n\tuint32_t sch2_rootfs_addr;\t// rootfs flash address\n\tuint32_t sch2_rootfs_len;\t// rootfls length\n\tuint32_t sch2_rootfs_crc32;\t// rootfs crc32\n\tuint32_t sch2_header_crc32;\t// sch2 header crc32, durring calculation this area is replaced by zero\n\tuint16_t sch2_header_length;\t// sch2 header length: 0x28\n\tuint16_t sch2_cmd_line_length;\t// cmd line length, known zeros\n};\n\nstatic int\nread_jimage_header(struct mtd_info *mtd, size_t offset, u_char *buf,\n\t\t   size_t header_len)\n{\n\tsize_t retlen;\n\tint ret;\n\n\tret = mtd_read(mtd, offset, header_len, &retlen, buf);\n\tif (ret) {\n\t\tpr_debug(\"read error in \\\"%s\\\"\\n\", mtd->name);\n\t\treturn ret;\n\t}\n\n\tif (retlen != header_len) {\n\t\tpr_debug(\"short read in \\\"%s\\\"\\n\", mtd->name);\n\t\treturn -EIO;\n\t}\n\n\treturn 0;\n}\n\n/**\n * __mtdsplit_parse_jimage - scan partition and create kernel + rootfs parts\n *\n * @find_header: function to call for a block of data that will return offset\n *      of a valid jImage header if found\n */\nstatic int __mtdsplit_parse_jimage(struct mtd_info *master,\n\t\t\t\t   const struct mtd_partition **pparts,\n\t\t\t\t   struct mtd_part_parser_data *data,\n\t\t\t\t   ssize_t (*find_header)(u_char *buf, size_t len))\n{\n\tstruct mtd_partition *parts;\n\tu_char *buf;\n\tint nr_parts;\n\tsize_t offset;\n\tsize_t jimage_offset;\n\tsize_t jimage_size = 0;\n\tsize_t rootfs_offset;\n\tsize_t rootfs_size = 0;\n\tint jimage_part, rf_part;\n\tint ret;\n\tenum mtdsplit_part_type type;\n\n\tnr_parts = 2;\n\tparts = kzalloc(nr_parts * sizeof(*parts), GFP_KERNEL);\n\tif (!parts)\n\t\treturn -ENOMEM;\n\n\tbuf = vmalloc(MAX_HEADER_LEN);\n\tif (!buf) {\n\t\tret = -ENOMEM;\n\t\tgoto err_free_parts;\n\t}\n\n\t/* find jImage on erase block boundaries */\n\tfor (offset = 0; offset < master->size; offset += master->erasesize) {\n\t\tstruct jimage_header *header;\n\n\t\tjimage_size = 0;\n\n\t\tret = read_jimage_header(master, offset, buf, MAX_HEADER_LEN);\n\t\tif (ret)\n\t\t\tcontinue;\n\n\t\tret = find_header(buf, MAX_HEADER_LEN);\n\t\tif (ret < 0) {\n\t\t\tpr_debug(\"no valid jImage found in \\\"%s\\\" at offset %llx\\n\",\n\t\t\t\t master->name, (unsigned long long) offset);\n\t\t\tcontinue;\n\t\t}\n\t\theader = (struct jimage_header *)(buf + ret);\n\n\t\tjimage_size = sizeof(*header) + header->sch2_image_len + ret;\n\t\tif ((offset + jimage_size) > master->size) {\n\t\t\tpr_debug(\"jImage exceeds MTD device \\\"%s\\\"\\n\",\n\t\t\t\t master->name);\n\t\t\tcontinue;\n\t\t}\n\t\tbreak;\n\t}\n\n\tif (jimage_size == 0) {\n\t\tpr_debug(\"no jImage found in \\\"%s\\\"\\n\", master->name);\n\t\tret = -ENODEV;\n\t\tgoto err_free_buf;\n\t}\n\n\tjimage_offset = offset;\n\n\tif (jimage_offset == 0) {\n\t\tjimage_part = 0;\n\t\trf_part = 1;\n\n\t\t/* find the roots after the jImage */\n\t\tret = mtd_find_rootfs_from(master, jimage_offset + jimage_size,\n\t\t\t\t\t   master->size, &rootfs_offset, &type);\n\t\tif (ret) {\n\t\t\tpr_debug(\"no rootfs after jImage in \\\"%s\\\"\\n\",\n\t\t\t\t master->name);\n\t\t\tgoto err_free_buf;\n\t\t}\n\n\t\trootfs_size = master->size - rootfs_offset;\n\t\tjimage_size = rootfs_offset - jimage_offset;\n\t} else {\n\t\trf_part = 0;\n\t\tjimage_part = 1;\n\n\t\t/* check rootfs presence at offset 0 */\n\t\tret = mtd_check_rootfs_magic(master, 0, &type);\n\t\tif (ret) {\n\t\t\tpr_debug(\"no rootfs before jImage in \\\"%s\\\"\\n\",\n\t\t\t\t master->name);\n\t\t\tgoto err_free_buf;\n\t\t}\n\n\t\trootfs_offset = 0;\n\t\trootfs_size = jimage_offset;\n\t}\n\n\tif (rootfs_size == 0) {\n\t\tpr_debug(\"no rootfs found in \\\"%s\\\"\\n\", master->name);\n\t\tret = -ENODEV;\n\t\tgoto err_free_buf;\n\t}\n\n\tparts[jimage_part].name = KERNEL_PART_NAME;\n\tparts[jimage_part].offset = jimage_offset;\n\tparts[jimage_part].size = jimage_size;\n\n\tif (type == MTDSPLIT_PART_TYPE_UBI)\n\t\tparts[rf_part].name = UBI_PART_NAME;\n\telse\n\t\tparts[rf_part].name = ROOTFS_PART_NAME;\n\tparts[rf_part].offset = rootfs_offset;\n\tparts[rf_part].size = rootfs_size;\n\n\tvfree(buf);\n\n\t*pparts = parts;\n\treturn nr_parts;\n\nerr_free_buf:\n\tvfree(buf);\n\nerr_free_parts:\n\tkfree(parts);\n\treturn ret;\n}\n\nstatic ssize_t jimage_verify_default(u_char *buf, size_t len)\n{\n\tstruct jimage_header *header = (struct jimage_header *)buf;\n\n\t/* default sanity checks */\n\tif (header->stag_magic != STAG_MAGIC) {\n\t\tpr_debug(\"invalid jImage stag header magic: %04x\\n\",\n\t\t\t header->stag_magic);\n\t\treturn -EINVAL;\n\t}\n\tif (header->sch2_magic != SCH2_MAGIC) {\n\t\tpr_debug(\"invalid jImage sch2 header magic: %04x\\n\",\n\t\t\t header->stag_magic);\n\t\treturn -EINVAL;\n\t}\n\tif (header->stag_cmark != header->stag_id) {\n\t\tpr_debug(\"invalid jImage stag header cmark: %02x\\n\",\n\t\t\t header->stag_magic);\n\t\treturn -EINVAL;\n\t}\n\tif (header->stag_id != STAG_ID) {\n\t\tpr_debug(\"invalid jImage stag header id: %02x\\n\",\n\t\t\t header->stag_magic);\n\t\treturn -EINVAL;\n\t}\n\tif (header->sch2_version != SCH2_VER) {\n\t\tpr_debug(\"invalid jImage sch2 header version: %02x\\n\",\n\t\t\t header->stag_magic);\n\t\treturn -EINVAL;\n\t}\n\n\treturn 0;\n}\n\nstatic int\nmtdsplit_jimage_parse_generic(struct mtd_info *master,\n\t\t\t      const struct mtd_partition **pparts,\n\t\t\t      struct mtd_part_parser_data *data)\n{\n\treturn __mtdsplit_parse_jimage(master, pparts, data,\n\t\t\t\t      jimage_verify_default);\n}\n\nstatic const struct of_device_id mtdsplit_jimage_of_match_table[] = {\n\t{ .compatible = \"amit,jimage\" },\n\t{},\n};\n\nstatic struct mtd_part_parser jimage_generic_parser = {\n\t.owner = THIS_MODULE,\n\t.name = \"jimage-fw\",\n\t.of_match_table = mtdsplit_jimage_of_match_table,\n\t.parse_fn = mtdsplit_jimage_parse_generic,\n\t.type = MTD_PARSER_TYPE_FIRMWARE,\n};\n\n/**************************************************\n * Init\n **************************************************/\n\nstatic int __init mtdsplit_jimage_init(void)\n{\n\tregister_mtd_parser(&jimage_generic_parser);\n\n\treturn 0;\n}\n\nmodule_init(mtdsplit_jimage_init);\n"
  },
  {
    "path": "target/linux/generic/files/drivers/mtd/mtdsplit/mtdsplit_lzma.c",
    "content": "/*\n *  Copyright (C) 2014 Gabor Juhos <juhosg@openwrt.org>\n *\n *  This program is free software; you can redistribute it and/or modify it\n *  under the terms of the GNU General Public License version 2 as published\n *  by the Free Software Foundation.\n *\n */\n\n#include <linux/module.h>\n#include <linux/init.h>\n#include <linux/kernel.h>\n#include <linux/slab.h>\n#include <linux/mtd/mtd.h>\n#include <linux/mtd/partitions.h>\n#include <linux/of.h>\n\n#include <asm/unaligned.h>\n\n#include \"mtdsplit.h\"\n\n#define LZMA_NR_PARTS\t\t2\n#define LZMA_PROPERTIES_SIZE\t5\n\nstruct lzma_header {\n\tu8 props[LZMA_PROPERTIES_SIZE];\n\tu8 size_low[4];\n\tu8 size_high[4];\n};\n\nstatic int mtdsplit_parse_lzma(struct mtd_info *master,\n\t\t\t       const struct mtd_partition **pparts,\n\t\t\t       struct mtd_part_parser_data *data)\n{\n\tstruct lzma_header hdr;\n\tsize_t hdr_len, retlen;\n\tsize_t rootfs_offset;\n\tu32 t;\n\tstruct mtd_partition *parts;\n\tint err;\n\n\thdr_len = sizeof(hdr);\n\terr = mtd_read(master, 0, hdr_len, &retlen, (void *) &hdr);\n\tif (err)\n\t\treturn err;\n\n\tif (retlen != hdr_len)\n\t\treturn -EIO;\n\n\t/* verify LZMA properties */\n\tif (hdr.props[0] >= (9 * 5 * 5))\n\t\treturn -EINVAL;\n\n\tt = get_unaligned_le32(&hdr.props[1]);\n\tif (!is_power_of_2(t))\n\t\treturn -EINVAL;\n\n\tt = get_unaligned_le32(&hdr.size_high);\n\tif (t)\n\t\treturn -EINVAL;\n\n\terr = mtd_find_rootfs_from(master, master->erasesize, master->size,\n\t\t\t\t   &rootfs_offset, NULL);\n\tif (err)\n\t\treturn err;\n\n\tparts = kzalloc(LZMA_NR_PARTS * sizeof(*parts), GFP_KERNEL);\n\tif (!parts)\n\t\treturn -ENOMEM;\n\n\tparts[0].name = KERNEL_PART_NAME;\n\tparts[0].offset = 0;\n\tparts[0].size = rootfs_offset;\n\n\tparts[1].name = ROOTFS_PART_NAME;\n\tparts[1].offset = rootfs_offset;\n\tparts[1].size = master->size - rootfs_offset;\n\n\t*pparts = parts;\n\treturn LZMA_NR_PARTS;\n}\n\nstatic const struct of_device_id mtdsplit_lzma_of_match_table[] = {\n\t{ .compatible = \"lzma\" },\n\t{},\n};\nMODULE_DEVICE_TABLE(of, mtdsplit_lzma_of_match_table);\n\nstatic struct mtd_part_parser mtdsplit_lzma_parser = {\n\t.owner = THIS_MODULE,\n\t.name = \"lzma-fw\",\n\t.of_match_table = mtdsplit_lzma_of_match_table,\n\t.parse_fn = mtdsplit_parse_lzma,\n\t.type = MTD_PARSER_TYPE_FIRMWARE,\n};\n\nstatic int __init mtdsplit_lzma_init(void)\n{\n\tregister_mtd_parser(&mtdsplit_lzma_parser);\n\n\treturn 0;\n}\n\nsubsys_initcall(mtdsplit_lzma_init);\n"
  },
  {
    "path": "target/linux/generic/files/drivers/mtd/mtdsplit/mtdsplit_minor.c",
    "content": "/*\n *  MTD splitter for MikroTik NOR devices\n *\n *  Copyright (C) 2017 Thibaut VARENE <varenet@parisc-linux.org>\n *\n *  This program is free software; you can redistribute it and/or modify it\n *  under the terms of the GNU General Public License version 2 as published\n *  by the Free Software Foundation.\n *\n *  The rootfs is expected at erase-block boundary due to the use of\n *  mtd_find_rootfs_from(). We use a trimmed down version of the yaffs header\n *  for two main reasons:\n *  - the original header uses weakly defined types (int, enum...) which can\n *    vary in length depending on build host (and the struct is not packed),\n *    and the name field can have a different total length depending on\n *    whether or not the yaffs code was _built_ with unicode support.\n *  - the only field that could be of real use here (file_size_low) contains\n *    invalid data in the header generated by kernel2minor, so we cannot use\n *    it to infer the exact position of the rootfs and do away with\n *    mtd_find_rootfs_from() (and thus have non-EB-aligned rootfs).\n */\n\n#include <linux/module.h>\n#include <linux/init.h>\n#include <linux/kernel.h>\n#include <linux/slab.h>\n#include <linux/mtd/mtd.h>\n#include <linux/mtd/partitions.h>\n#include <linux/string.h>\n#include <linux/of.h>\n\n#include \"mtdsplit.h\"\n\n#define YAFFS_OBJECT_TYPE_FILE\t0x1\n#define YAFFS_OBJECTID_ROOT\t0x1\n#define YAFFS_SUM_UNUSED\t0xFFFF\n#define YAFFS_NAME\t\t\"kernel\"\n\n#define MINOR_NR_PARTS\t\t2\n\n/*\n * This structure is based on yaffs_obj_hdr from yaffs_guts.h\n * The weak types match upstream. The fields have cpu-endianness\n */\nstruct minor_header {\n\tint yaffs_type;\n\tint yaffs_obj_id;\n\tu16 yaffs_sum_unused;\n\tchar yaffs_name[sizeof(YAFFS_NAME)];\n};\n\nstatic int mtdsplit_parse_minor(struct mtd_info *master,\n\t\t\t\tconst struct mtd_partition **pparts,\n\t\t\t\tstruct mtd_part_parser_data *data)\n{\n\tstruct minor_header hdr;\n\tsize_t hdr_len, retlen;\n\tsize_t rootfs_offset;\n\tstruct mtd_partition *parts;\n\tint err;\n\n\thdr_len = sizeof(hdr);\n\terr = mtd_read(master, 0, hdr_len, &retlen, (void *) &hdr);\n\tif (err)\n\t\treturn err;\n\n\tif (retlen != hdr_len)\n\t\treturn -EIO;\n\n\t/* match header */\n\tif (hdr.yaffs_type != YAFFS_OBJECT_TYPE_FILE)\n\t\treturn -EINVAL;\n\n\tif (hdr.yaffs_obj_id != YAFFS_OBJECTID_ROOT)\n\t\treturn -EINVAL;\n\n\tif (hdr.yaffs_sum_unused != YAFFS_SUM_UNUSED)\n\t\treturn -EINVAL;\n\n\tif (memcmp(hdr.yaffs_name, YAFFS_NAME, sizeof(YAFFS_NAME)))\n\t\treturn -EINVAL;\n\n\terr = mtd_find_rootfs_from(master, master->erasesize, master->size,\n\t\t\t\t   &rootfs_offset, NULL);\n\tif (err)\n\t\treturn err;\n\n\tparts = kzalloc(MINOR_NR_PARTS * sizeof(*parts), GFP_KERNEL);\n\tif (!parts)\n\t\treturn -ENOMEM;\n\n\tparts[0].name = KERNEL_PART_NAME;\n\tparts[0].offset = 0;\n\tparts[0].size = rootfs_offset;\n\n\tparts[1].name = ROOTFS_PART_NAME;\n\tparts[1].offset = rootfs_offset;\n\tparts[1].size = master->size - rootfs_offset;\n\n\t*pparts = parts;\n\treturn MINOR_NR_PARTS;\n}\n\nstatic const struct of_device_id mtdsplit_minor_of_match_table[] = {\n\t{ .compatible = \"mikrotik,minor\" },\n\t{},\n};\nMODULE_DEVICE_TABLE(of, mtdsplit_minor_of_match_table);\n\nstatic struct mtd_part_parser mtdsplit_minor_parser = {\n\t.owner = THIS_MODULE,\n\t.name = \"minor-fw\",\n\t.of_match_table = mtdsplit_minor_of_match_table,\n\t.parse_fn = mtdsplit_parse_minor,\n\t.type = MTD_PARSER_TYPE_FIRMWARE,\n};\n\nstatic int __init mtdsplit_minor_init(void)\n{\n\tregister_mtd_parser(&mtdsplit_minor_parser);\n\n\treturn 0;\n}\n\nsubsys_initcall(mtdsplit_minor_init);\n"
  },
  {
    "path": "target/linux/generic/files/drivers/mtd/mtdsplit/mtdsplit_seama.c",
    "content": "/*\n *  Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>\n *\n *  This program is free software; you can redistribute it and/or modify it\n *  under the terms of the GNU General Public License version 2 as published\n *  by the Free Software Foundation.\n *\n */\n\n#include <linux/module.h>\n#include <linux/init.h>\n#include <linux/kernel.h>\n#include <linux/slab.h>\n#include <linux/mtd/mtd.h>\n#include <linux/mtd/partitions.h>\n#include <linux/byteorder/generic.h>\n#include <linux/of.h>\n\n#include \"mtdsplit.h\"\n\n#define SEAMA_MAGIC\t\t0x5EA3A417\n#define SEAMA_NR_PARTS\t\t2\n#define SEAMA_MIN_ROOTFS_OFFS\t0x80000\t/* 512KiB */\n\nstruct seama_header {\n\t__be32\tmagic;\t\t/* should always be SEAMA_MAGIC. */\n\t__be16\treserved;\t/* reserved for  */\n\t__be16\tmetasize;\t/* size of the META data */\n\t__be32\tsize;\t\t/* size of the image */\n\tu8\tmd5[16];\t/* digest */\n};\n\nstatic int mtdsplit_parse_seama(struct mtd_info *master,\n\t\t\t\tconst struct mtd_partition **pparts,\n\t\t\t\tstruct mtd_part_parser_data *data)\n{\n\tstruct seama_header hdr;\n\tsize_t hdr_len, retlen, kernel_ent_size;\n\tsize_t rootfs_offset;\n\tstruct mtd_partition *parts;\n\tenum mtdsplit_part_type type;\n\tint err;\n\n\thdr_len = sizeof(hdr);\n\terr = mtd_read(master, 0, hdr_len, &retlen, (void *) &hdr);\n\tif (err)\n\t\treturn err;\n\n\tif (retlen != hdr_len)\n\t\treturn -EIO;\n\n\t/* sanity checks */\n\tif (be32_to_cpu(hdr.magic) != SEAMA_MAGIC)\n\t\treturn -EINVAL;\n\n\tkernel_ent_size = hdr_len + be32_to_cpu(hdr.size) +\n\t\t\t  be16_to_cpu(hdr.metasize);\n\tif (kernel_ent_size > master->size)\n\t\treturn -EINVAL;\n\n\t/* Check for the rootfs right after Seama entity with a kernel. */\n\terr = mtd_check_rootfs_magic(master, kernel_ent_size, &type);\n\tif (!err) {\n\t\trootfs_offset = kernel_ent_size;\n\t} else {\n\t\t/*\n\t\t * On some devices firmware entity might contain both: kernel\n\t\t * and rootfs. We can't determine kernel size so we just have to\n\t\t * look for rootfs magic.\n\t\t * Start the search from an arbitrary offset.\n\t\t */\n\t\terr = mtd_find_rootfs_from(master, SEAMA_MIN_ROOTFS_OFFS,\n\t\t\t\t\t   master->size, &rootfs_offset, &type);\n\t\tif (err)\n\t\t\treturn err;\n\t}\n\n\tparts = kzalloc(SEAMA_NR_PARTS * sizeof(*parts), GFP_KERNEL);\n\tif (!parts)\n\t\treturn -ENOMEM;\n\n\tparts[0].name = KERNEL_PART_NAME;\n\tparts[0].offset = sizeof hdr + be16_to_cpu(hdr.metasize);\n\tparts[0].size = rootfs_offset - parts[0].offset;\n\n\tif (type == MTDSPLIT_PART_TYPE_UBI)\n\t\tparts[1].name = UBI_PART_NAME;\n\telse\n\t\tparts[1].name = ROOTFS_PART_NAME;\n\tparts[1].offset = rootfs_offset;\n\tparts[1].size = master->size - rootfs_offset;\n\n\t*pparts = parts;\n\treturn SEAMA_NR_PARTS;\n}\n\nstatic const struct of_device_id mtdsplit_seama_of_match_table[] = {\n\t{ .compatible = \"seama\" },\n\t{},\n};\nMODULE_DEVICE_TABLE(of, mtdsplit_seama_of_match_table);\n\nstatic struct mtd_part_parser mtdsplit_seama_parser = {\n\t.owner = THIS_MODULE,\n\t.name = \"seama-fw\",\n\t.of_match_table = mtdsplit_seama_of_match_table,\n\t.parse_fn = mtdsplit_parse_seama,\n\t.type = MTD_PARSER_TYPE_FIRMWARE,\n};\n\nstatic int __init mtdsplit_seama_init(void)\n{\n\tregister_mtd_parser(&mtdsplit_seama_parser);\n\n\treturn 0;\n}\n\nsubsys_initcall(mtdsplit_seama_init);\n"
  },
  {
    "path": "target/linux/generic/files/drivers/mtd/mtdsplit/mtdsplit_squashfs.c",
    "content": "/*\n *  Copyright (C) 2013 Felix Fietkau <nbd@nbd.name>\n *  Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>\n *\n *  This program is free software; you can redistribute it and/or modify it\n *  under the terms of the GNU General Public License version 2 as published\n *  by the Free Software Foundation.\n *\n */\n\n#define pr_fmt(fmt)\tKBUILD_MODNAME \": \" fmt\n\n#include <linux/module.h>\n#include <linux/init.h>\n#include <linux/kernel.h>\n#include <linux/slab.h>\n#include <linux/magic.h>\n#include <linux/mtd/mtd.h>\n#include <linux/mtd/partitions.h>\n#include <linux/byteorder/generic.h>\n\n#include \"mtdsplit.h\"\n\nstatic int\nmtdsplit_parse_squashfs(struct mtd_info *master,\n\t\t\tconst struct mtd_partition **pparts,\n\t\t\tstruct mtd_part_parser_data *data)\n{\n\tstruct mtd_partition *part;\n\tstruct mtd_info *parent_mtd;\n\tsize_t part_offset;\n\tsize_t squashfs_len;\n\tint err;\n\n\terr = mtd_get_squashfs_len(master, 0, &squashfs_len);\n\tif (err)\n\t\treturn err;\n\n\tparent_mtd = mtd_get_master(master);\n\tpart_offset = mtdpart_get_offset(master);\n\n\tpart = kzalloc(sizeof(*part), GFP_KERNEL);\n\tif (!part) {\n\t\tpr_alert(\"unable to allocate memory for \\\"%s\\\" partition\\n\",\n\t\t\t ROOTFS_SPLIT_NAME);\n\t\treturn -ENOMEM;\n\t}\n\n\tpart->name = ROOTFS_SPLIT_NAME;\n\tpart->offset = mtd_roundup_to_eb(part_offset + squashfs_len,\n\t\t\t\t\t parent_mtd) - part_offset;\n\tpart->size = mtd_rounddown_to_eb(master->size - part->offset, master);\n\n\t*pparts = part;\n\treturn 1;\n}\n\nstatic struct mtd_part_parser mtdsplit_squashfs_parser = {\n\t.owner = THIS_MODULE,\n\t.name = \"squashfs-split\",\n\t.parse_fn = mtdsplit_parse_squashfs,\n\t.type = MTD_PARSER_TYPE_ROOTFS,\n};\n\nstatic int __init mtdsplit_squashfs_init(void)\n{\n\tregister_mtd_parser(&mtdsplit_squashfs_parser);\n\n\treturn 0;\n}\n\nsubsys_initcall(mtdsplit_squashfs_init);\n"
  },
  {
    "path": "target/linux/generic/files/drivers/mtd/mtdsplit/mtdsplit_tplink.c",
    "content": "/*\n *  Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>\n *  Copyright (C) 2014 Felix Fietkau <nbd@nbd.name>\n *\n *  This program is free software; you can redistribute it and/or modify it\n *  under the terms of the GNU General Public License version 2 as published\n *  by the Free Software Foundation.\n *\n */\n\n#include <linux/module.h>\n#include <linux/init.h>\n#include <linux/kernel.h>\n#include <linux/slab.h>\n#include <linux/mtd/mtd.h>\n#include <linux/mtd/partitions.h>\n#include <linux/byteorder/generic.h>\n#include <linux/of.h>\n\n#include \"mtdsplit.h\"\n\n#define TPLINK_NR_PARTS\t\t2\n#define TPLINK_MIN_ROOTFS_OFFS\t0x80000\t/* 512KiB */\n\n#define MD5SUM_LEN  16\n\nstruct fw_v1 {\n\tchar\t\tvendor_name[24];\n\tchar\t\tfw_version[36];\n\tuint32_t\thw_id;\t\t/* hardware id */\n\tuint32_t\thw_rev;\t\t/* hardware revision */\n\tuint32_t\tunk1;\n\tuint8_t\t\tmd5sum1[MD5SUM_LEN];\n\tuint32_t\tunk2;\n\tuint8_t\t\tmd5sum2[MD5SUM_LEN];\n\tuint32_t\tunk3;\n\tuint32_t\tkernel_la;\t/* kernel load address */\n\tuint32_t\tkernel_ep;\t/* kernel entry point */\n\tuint32_t\tfw_length;\t/* total length of the firmware */\n\tuint32_t\tkernel_ofs;\t/* kernel data offset */\n\tuint32_t\tkernel_len;\t/* kernel data length */\n\tuint32_t\trootfs_ofs;\t/* rootfs data offset */\n\tuint32_t\trootfs_len;\t/* rootfs data length */\n\tuint32_t\tboot_ofs;\t/* bootloader data offset */\n\tuint32_t\tboot_len;\t/* bootloader data length */\n\tuint8_t\t\tpad[360];\n} __attribute__ ((packed));\n\nstruct fw_v2 {\n\tchar\t\tfw_version[48]; /* 0x04: fw version string */\n\tuint32_t\thw_id;\t\t/* 0x34: hardware id */\n\tuint32_t\thw_rev;\t\t/* 0x38: FIXME: hardware revision? */\n\tuint32_t\tunk1;\t        /* 0x3c: 0x00000000 */\n\tuint8_t\t\tmd5sum1[MD5SUM_LEN]; /* 0x40 */\n\tuint32_t\tunk2;\t\t/* 0x50: 0x00000000 */\n\tuint8_t\t\tmd5sum2[MD5SUM_LEN]; /* 0x54 */\n\tuint32_t\tunk3;\t\t/* 0x64: 0xffffffff */\n\n\tuint32_t\tkernel_la;\t/* 0x68: kernel load address */\n\tuint32_t\tkernel_ep;\t/* 0x6c: kernel entry point */\n\tuint32_t\tfw_length;\t/* 0x70: total length of the image */\n\tuint32_t\tkernel_ofs;\t/* 0x74: kernel data offset */\n\tuint32_t\tkernel_len;\t/* 0x78: kernel data length */\n\tuint32_t\trootfs_ofs;\t/* 0x7c: rootfs data offset */\n\tuint32_t\trootfs_len;\t/* 0x80: rootfs data length */\n\tuint32_t\tboot_ofs;\t/* 0x84: FIXME: seems to be unused */\n\tuint32_t\tboot_len;\t/* 0x88: FIXME: seems to be unused */\n\tuint16_t\tunk4;\t\t/* 0x8c: 0x55aa */\n\tuint8_t\t\tsver_hi;\t/* 0x8e */\n\tuint8_t\t\tsver_lo;\t/* 0x8f */\n\tuint8_t\t\tunk5;\t\t/* 0x90: magic: 0xa5 */\n\tuint8_t\t\tver_hi;         /* 0x91 */\n\tuint8_t\t\tver_mid;        /* 0x92 */\n\tuint8_t\t\tver_lo;         /* 0x93 */\n\tuint8_t\t\tpad[364];\n} __attribute__ ((packed));\n\nstruct tplink_fw_header {\n\tuint32_t version;\n\tunion {\n\t\tstruct fw_v1 v1;\n\t\tstruct fw_v2 v2;\n\t};\n};\n\nstatic int mtdsplit_parse_tplink(struct mtd_info *master,\n\t\t\t\t const struct mtd_partition **pparts,\n\t\t\t\t struct mtd_part_parser_data *data)\n{\n\tstruct tplink_fw_header hdr;\n\tsize_t hdr_len, retlen, kernel_size;\n\tsize_t rootfs_offset;\n\tstruct mtd_partition *parts;\n\tint err;\n\n\thdr_len = sizeof(hdr);\n\terr = mtd_read(master, 0, hdr_len, &retlen, (void *) &hdr);\n\tif (err)\n\t\treturn err;\n\n\tif (retlen != hdr_len)\n\t\treturn -EIO;\n\n\tswitch (le32_to_cpu(hdr.version)) {\n\tcase 1:\n\t\tif (be32_to_cpu(hdr.v1.kernel_ofs) != sizeof(hdr))\n\t\t\treturn -EINVAL;\n\n\t\tkernel_size = sizeof(hdr) + be32_to_cpu(hdr.v1.kernel_len);\n\t\trootfs_offset = be32_to_cpu(hdr.v1.rootfs_ofs);\n\t\tbreak;\n\tcase 2:\n\tcase 3:\n\t\tif (be32_to_cpu(hdr.v2.kernel_ofs) != sizeof(hdr))\n\t\t\treturn -EINVAL;\n\n\t\tkernel_size = sizeof(hdr) + be32_to_cpu(hdr.v2.kernel_len);\n\t\trootfs_offset = be32_to_cpu(hdr.v2.rootfs_ofs);\n\t\tbreak;\n\tdefault:\n\t\treturn -EINVAL;\n\t}\n\n\tif (kernel_size > master->size)\n\t\treturn -EINVAL;\n\n\t/* Find the rootfs */\n\terr = mtd_check_rootfs_magic(master, rootfs_offset, NULL);\n\tif (err) {\n\t\t/*\n\t\t * The size in the header might cover the rootfs as well.\n\t\t * Start the search from an arbitrary offset.\n\t\t */\n\t\terr = mtd_find_rootfs_from(master, TPLINK_MIN_ROOTFS_OFFS,\n\t\t\t\t\t   master->size, &rootfs_offset, NULL);\n\t\tif (err)\n\t\t\treturn err;\n\t}\n\n\tparts = kzalloc(TPLINK_NR_PARTS * sizeof(*parts), GFP_KERNEL);\n\tif (!parts)\n\t\treturn -ENOMEM;\n\n\tparts[0].name = KERNEL_PART_NAME;\n\tparts[0].offset = 0;\n\tparts[0].size = kernel_size;\n\n\tparts[1].name = ROOTFS_PART_NAME;\n\tparts[1].offset = rootfs_offset;\n\tparts[1].size = master->size - rootfs_offset;\n\n\t*pparts = parts;\n\treturn TPLINK_NR_PARTS;\n}\n\nstatic const struct of_device_id mtdsplit_tplink_of_match_table[] = {\n\t{ .compatible = \"tplink,firmware\" },\n\t{},\n};\n\nstatic struct mtd_part_parser mtdsplit_tplink_parser = {\n\t.owner = THIS_MODULE,\n\t.name = \"tplink-fw\",\n\t.of_match_table = mtdsplit_tplink_of_match_table,\n\t.parse_fn = mtdsplit_parse_tplink,\n\t.type = MTD_PARSER_TYPE_FIRMWARE,\n};\n\nstatic int __init mtdsplit_tplink_init(void)\n{\n\tregister_mtd_parser(&mtdsplit_tplink_parser);\n\n\treturn 0;\n}\n\nsubsys_initcall(mtdsplit_tplink_init);\n"
  },
  {
    "path": "target/linux/generic/files/drivers/mtd/mtdsplit/mtdsplit_trx.c",
    "content": "/*\n *  Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>\n *  Copyright (C) 2014 Felix Fietkau <nbd@nbd.name>\n *\n *  This program is free software; you can redistribute it and/or modify it\n *  under the terms of the GNU General Public License version 2 as published\n *  by the Free Software Foundation.\n *\n */\n\n#define pr_fmt(fmt)\tKBUILD_MODNAME \": \" fmt\n\n#include <linux/module.h>\n#include <linux/init.h>\n#include <linux/kernel.h>\n#include <linux/slab.h>\n#include <linux/mtd/mtd.h>\n#include <linux/mtd/partitions.h>\n#include <linux/byteorder/generic.h>\n#include <linux/of.h>\n\n#include \"mtdsplit.h\"\n\n#define TRX_MAGIC   0x30524448  /* \"HDR0\" */\n\nstruct trx_header {\n\t__le32 magic;\n\t__le32 len;\n\t__le32 crc32;\n\t__le32 flag_version;\n\t__le32 offset[4];\n};\n\nstatic int\nread_trx_header(struct mtd_info *mtd, size_t offset,\n\t\t   struct trx_header *header)\n{\n\tsize_t header_len;\n\tsize_t retlen;\n\tint ret;\n\n\theader_len = sizeof(*header);\n\tret = mtd_read(mtd, offset, header_len, &retlen,\n\t\t       (unsigned char *) header);\n\tif (ret) {\n\t\tpr_debug(\"read error in \\\"%s\\\"\\n\", mtd->name);\n\t\treturn ret;\n\t}\n\n\tif (retlen != header_len) {\n\t\tpr_debug(\"short read in \\\"%s\\\"\\n\", mtd->name);\n\t\treturn -EIO;\n\t}\n\n\treturn 0;\n}\n\nstatic int\nmtdsplit_parse_trx(struct mtd_info *master,\n\t\t   const struct mtd_partition **pparts,\n\t\t   struct mtd_part_parser_data *data)\n{\n\tstruct mtd_partition *parts;\n\tstruct trx_header hdr;\n\tint nr_parts;\n\tsize_t offset;\n\tsize_t trx_offset;\n\tsize_t trx_size = 0;\n\tsize_t rootfs_offset;\n\tsize_t rootfs_size = 0;\n\tint ret;\n\n\tnr_parts = 2;\n\tparts = kzalloc(nr_parts * sizeof(*parts), GFP_KERNEL);\n\tif (!parts)\n\t\treturn -ENOMEM;\n\n\t/* find trx image on erase block boundaries */\n\tfor (offset = 0; offset < master->size; offset += master->erasesize) {\n\t\ttrx_size = 0;\n\n\t\tret = read_trx_header(master, offset, &hdr);\n\t\tif (ret)\n\t\t\tcontinue;\n\n\t\tif (hdr.magic != cpu_to_le32(TRX_MAGIC)) {\n\t\t\tpr_debug(\"no valid trx header found in \\\"%s\\\" at offset %llx\\n\",\n\t\t\t\t master->name, (unsigned long long) offset);\n\t\t\tcontinue;\n\t\t}\n\n\t\ttrx_size = le32_to_cpu(hdr.len);\n\t\tif ((offset + trx_size) > master->size) {\n\t\t\tpr_debug(\"trx image exceeds MTD device \\\"%s\\\"\\n\",\n\t\t\t\t master->name);\n\t\t\tcontinue;\n\t\t}\n\t\tbreak;\n\t}\n\n\tif (trx_size == 0) {\n\t\tpr_debug(\"no trx header found in \\\"%s\\\"\\n\", master->name);\n\t\tret = -ENODEV;\n\t\tgoto err;\n\t}\n\n\ttrx_offset = offset + hdr.offset[0];\n\trootfs_offset = offset + hdr.offset[1];\n\trootfs_size = master->size - rootfs_offset;\n\ttrx_size = rootfs_offset - trx_offset;\n\n\tif (rootfs_size == 0) {\n\t\tpr_debug(\"no rootfs found in \\\"%s\\\"\\n\", master->name);\n\t\tret = -ENODEV;\n\t\tgoto err;\n\t}\n\n\tparts[0].name = KERNEL_PART_NAME;\n\tparts[0].offset = trx_offset;\n\tparts[0].size = trx_size;\n\n\tparts[1].name = ROOTFS_PART_NAME;\n\tparts[1].offset = rootfs_offset;\n\tparts[1].size = rootfs_size;\n\n\t*pparts = parts;\n\treturn nr_parts;\n\nerr:\n\tkfree(parts);\n\treturn ret;\n}\n\nstatic const struct of_device_id trx_parser_of_match_table[] = {\n\t{ .compatible = \"openwrt,trx\" },\n\t{},\n};\nMODULE_DEVICE_TABLE(of, trx_parser_of_match_table);\n\nstatic struct mtd_part_parser trx_parser = {\n\t.owner = THIS_MODULE,\n\t.name = \"trx-fw\",\n\t.of_match_table = trx_parser_of_match_table,\n\t.parse_fn = mtdsplit_parse_trx,\n\t.type = MTD_PARSER_TYPE_FIRMWARE,\n};\n\nstatic int __init mtdsplit_trx_init(void)\n{\n\tregister_mtd_parser(&trx_parser);\n\n\treturn 0;\n}\n\nmodule_init(mtdsplit_trx_init);\n"
  },
  {
    "path": "target/linux/generic/files/drivers/mtd/mtdsplit/mtdsplit_uimage.c",
    "content": "/*\n *  Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>\n *\n *  This program is free software; you can redistribute it and/or modify it\n *  under the terms of the GNU General Public License version 2 as published\n *  by the Free Software Foundation.\n *\n */\n\n#define pr_fmt(fmt)\tKBUILD_MODNAME \": \" fmt\n\n#include <linux/module.h>\n#include <linux/init.h>\n#include <linux/kernel.h>\n#include <linux/slab.h>\n#include <linux/vmalloc.h>\n#include <linux/mtd/mtd.h>\n#include <linux/mtd/partitions.h>\n#include <linux/version.h>\n#include <linux/byteorder/generic.h>\n#include <linux/of.h>\n#include <dt-bindings/mtd/partitions/uimage.h>\n\n#include \"mtdsplit.h\"\n\n/*\n * Legacy format image header,\n * all data in network byte order (aka natural aka bigendian).\n */\nstruct uimage_header {\n\tuint32_t\tih_magic;\t/* Image Header Magic Number\t*/\n\tuint32_t\tih_hcrc;\t/* Image Header CRC Checksum\t*/\n\tuint32_t\tih_time;\t/* Image Creation Timestamp\t*/\n\tuint32_t\tih_size;\t/* Image Data Size\t\t*/\n\tuint32_t\tih_load;\t/* Data\t Load  Address\t\t*/\n\tuint32_t\tih_ep;\t\t/* Entry Point Address\t\t*/\n\tuint32_t\tih_dcrc;\t/* Image Data CRC Checksum\t*/\n\tuint8_t\t\tih_os;\t\t/* Operating System\t\t*/\n\tuint8_t\t\tih_arch;\t/* CPU architecture\t\t*/\n\tuint8_t\t\tih_type;\t/* Image Type\t\t\t*/\n\tuint8_t\t\tih_comp;\t/* Compression Type\t\t*/\n\tuint8_t\t\tih_name[IH_NMLEN];\t/* Image Name\t\t*/\n};\n\nstatic int\nread_uimage_header(struct mtd_info *mtd, size_t offset, u_char *buf,\n\t\t   size_t header_len)\n{\n\tsize_t retlen;\n\tint ret;\n\n\tret = mtd_read(mtd, offset, header_len, &retlen, buf);\n\tif (ret) {\n\t\tpr_debug(\"read error in \\\"%s\\\"\\n\", mtd->name);\n\t\treturn ret;\n\t}\n\n\tif (retlen != header_len) {\n\t\tpr_debug(\"short read in \\\"%s\\\"\\n\", mtd->name);\n\t\treturn -EIO;\n\t}\n\n\treturn 0;\n}\n\nstatic void uimage_parse_dt(struct mtd_info *master, int *extralen,\n\t\t\t    u32 *ih_magic, u32 *ih_type,\n\t\t\t    u32 *header_offset, u32 *part_magic)\n{\n\tstruct device_node *np = mtd_get_of_node(master);\n\n\tif (!np || !of_device_is_compatible(np, \"openwrt,uimage\"))\n\t\treturn;\n\n\tif (!of_property_read_u32(np, \"openwrt,padding\", extralen))\n\t\tpr_debug(\"got openwrt,padding=%d from device-tree\\n\", *extralen);\n\tif (!of_property_read_u32(np, \"openwrt,ih-magic\", ih_magic))\n\t\tpr_debug(\"got openwrt,ih-magic=%08x from device-tree\\n\", *ih_magic);\n\tif (!of_property_read_u32(np, \"openwrt,ih-type\", ih_type))\n\t\tpr_debug(\"got openwrt,ih-type=%08x from device-tree\\n\", *ih_type);\n\tif (!of_property_read_u32(np, \"openwrt,offset\", header_offset))\n\t\tpr_debug(\"got ih-start=%u from device-tree\\n\", *header_offset);\n\tif (!of_property_read_u32(np, \"openwrt,partition-magic\", part_magic))\n\t\tpr_debug(\"got openwrt,partition-magic=%08x from device-tree\\n\", *part_magic);\n}\n\nstatic ssize_t uimage_verify_default(u_char *buf, u32 ih_magic, u32 ih_type)\n{\n\tstruct uimage_header *header = (struct uimage_header *)buf;\n\n\t/* default sanity checks */\n\tif (be32_to_cpu(header->ih_magic) != ih_magic) {\n\t\tpr_debug(\"invalid uImage magic: %08x != %08x\\n\",\n\t\t\t be32_to_cpu(header->ih_magic), ih_magic);\n\t\treturn -EINVAL;\n\t}\n\n\tif (header->ih_os != IH_OS_LINUX) {\n\t\tpr_debug(\"invalid uImage OS: %08x != %08x\\n\",\n\t\t\t be32_to_cpu(header->ih_os), IH_OS_LINUX);\n\t\treturn -EINVAL;\n\t}\n\n\tif (header->ih_type != ih_type) {\n\t\tpr_debug(\"invalid uImage type: %08x != %08x\\n\",\n\t\t\t be32_to_cpu(header->ih_type), ih_type);\n\t\treturn -EINVAL;\n\t}\n\n\treturn 0;\n}\n\n/**\n * __mtdsplit_parse_uimage - scan partition and create kernel + rootfs parts\n *\n * @find_header: function to call for a block of data that will return offset\n *      and tail padding length of a valid uImage header if found\n */\nstatic int __mtdsplit_parse_uimage(struct mtd_info *master,\n\t\t\t\t   const struct mtd_partition **pparts,\n\t\t\t\t   struct mtd_part_parser_data *data)\n{\n\tstruct mtd_partition *parts;\n\tu_char *buf;\n\tint nr_parts;\n\tsize_t offset;\n\tsize_t uimage_offset;\n\tsize_t uimage_size = 0;\n\tsize_t rootfs_offset;\n\tsize_t rootfs_size = 0;\n\tsize_t buflen;\n\tint uimage_part, rf_part;\n\tint ret;\n\tint extralen = 0;\n\tu32 ih_magic = IH_MAGIC;\n\tu32 ih_type = IH_TYPE_KERNEL;\n\tu32 header_offset = 0;\n\tu32 part_magic = 0;\n\tenum mtdsplit_part_type type;\n\n\tnr_parts = 2;\n\tparts = kzalloc(nr_parts * sizeof(*parts), GFP_KERNEL);\n\tif (!parts)\n\t\treturn -ENOMEM;\n\n\tuimage_parse_dt(master, &extralen, &ih_magic, &ih_type, &header_offset, &part_magic);\n\tbuflen = sizeof(struct uimage_header) + header_offset;\n\tbuf = vmalloc(buflen);\n\tif (!buf) {\n\t\tret = -ENOMEM;\n\t\tgoto err_free_parts;\n\t}\n\n\t/* find uImage on erase block boundaries */\n\tfor (offset = 0; offset < master->size; offset += master->erasesize) {\n\t\tstruct uimage_header *header;\n\n\t\tuimage_size = 0;\n\n\t\tret = read_uimage_header(master, offset, buf, buflen);\n\t\tif (ret)\n\t\t\tcontinue;\n\n\t\t/* verify optional partition magic before uimage header */\n\t\tif (header_offset && part_magic && (be32_to_cpu(*(u32 *)buf) != part_magic))\n\t\t\tcontinue;\n\n\t\tret = uimage_verify_default(buf + header_offset, ih_magic, ih_type);\n\t\tif (ret < 0) {\n\t\t\tpr_debug(\"no valid uImage found in \\\"%s\\\" at offset %llx\\n\",\n\t\t\t\t master->name, (unsigned long long) offset);\n\t\t\tcontinue;\n\t\t}\n\n\t\theader = (struct uimage_header *)(buf + header_offset);\n\n\t\tuimage_size = sizeof(*header) +\n\t\t\t\tbe32_to_cpu(header->ih_size) + header_offset + extralen;\n\n\t\tif ((offset + uimage_size) > master->size) {\n\t\t\tpr_debug(\"uImage exceeds MTD device \\\"%s\\\"\\n\",\n\t\t\t\t master->name);\n\t\t\tcontinue;\n\t\t}\n\t\tbreak;\n\t}\n\n\tif (uimage_size == 0) {\n\t\tpr_debug(\"no uImage found in \\\"%s\\\"\\n\", master->name);\n\t\tret = -ENODEV;\n\t\tgoto err_free_buf;\n\t}\n\n\tuimage_offset = offset;\n\n\tif (uimage_offset == 0) {\n\t\tuimage_part = 0;\n\t\trf_part = 1;\n\n\t\t/* find the roots after the uImage */\n\t\tret = mtd_find_rootfs_from(master, uimage_offset + uimage_size,\n\t\t\t\t\t   master->size, &rootfs_offset, &type);\n\t\tif (ret) {\n\t\t\tpr_debug(\"no rootfs after uImage in \\\"%s\\\"\\n\",\n\t\t\t\t master->name);\n\t\t\tgoto err_free_buf;\n\t\t}\n\n\t\trootfs_size = master->size - rootfs_offset;\n\t\tuimage_size = rootfs_offset - uimage_offset;\n\t} else {\n\t\trf_part = 0;\n\t\tuimage_part = 1;\n\n\t\t/* check rootfs presence at offset 0 */\n\t\tret = mtd_check_rootfs_magic(master, 0, &type);\n\t\tif (ret) {\n\t\t\tpr_debug(\"no rootfs before uImage in \\\"%s\\\"\\n\",\n\t\t\t\t master->name);\n\t\t\tgoto err_free_buf;\n\t\t}\n\n\t\trootfs_offset = 0;\n\t\trootfs_size = uimage_offset;\n\t}\n\n\tif (rootfs_size == 0) {\n\t\tpr_debug(\"no rootfs found in \\\"%s\\\"\\n\", master->name);\n\t\tret = -ENODEV;\n\t\tgoto err_free_buf;\n\t}\n\n\tparts[uimage_part].name = KERNEL_PART_NAME;\n\tparts[uimage_part].offset = uimage_offset;\n\tparts[uimage_part].size = uimage_size;\n\n\tif (type == MTDSPLIT_PART_TYPE_UBI)\n\t\tparts[rf_part].name = UBI_PART_NAME;\n\telse\n\t\tparts[rf_part].name = ROOTFS_PART_NAME;\n\tparts[rf_part].offset = rootfs_offset;\n\tparts[rf_part].size = rootfs_size;\n\n\tvfree(buf);\n\n\t*pparts = parts;\n\treturn nr_parts;\n\nerr_free_buf:\n\tvfree(buf);\n\nerr_free_parts:\n\tkfree(parts);\n\treturn ret;\n}\n\nstatic const struct of_device_id mtdsplit_uimage_of_match_table[] = {\n\t{ .compatible = \"denx,uimage\" },\n\t{ .compatible = \"openwrt,uimage\" },\n\t{},\n};\n\nstatic struct mtd_part_parser uimage_generic_parser = {\n\t.owner = THIS_MODULE,\n\t.name = \"uimage-fw\",\n\t.of_match_table = mtdsplit_uimage_of_match_table,\n\t.parse_fn = __mtdsplit_parse_uimage,\n\t.type = MTD_PARSER_TYPE_FIRMWARE,\n};\n\n/**************************************************\n * Init\n **************************************************/\n\nstatic int __init mtdsplit_uimage_init(void)\n{\n\tregister_mtd_parser(&uimage_generic_parser);\n\n\treturn 0;\n}\n\nmodule_init(mtdsplit_uimage_init);\n"
  },
  {
    "path": "target/linux/generic/files/drivers/mtd/mtdsplit/mtdsplit_wrgg.c",
    "content": "/*\n *  Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>\n *  Copyright (C) 2014 Felix Fietkau <nbd@nbd.name>\n *  Copyright (C) 2016 Stijn Tintel <stijn@linux-ipv6.be>\n *\n *  This program is free software; you can redistribute it and/or modify it\n *  under the terms of the GNU General Public License version 2 as published\n *  by the Free Software Foundation.\n *\n */\n\n#include <linux/module.h>\n#include <linux/init.h>\n#include <linux/kernel.h>\n#include <linux/slab.h>\n#include <linux/mtd/mtd.h>\n#include <linux/mtd/partitions.h>\n#include <linux/byteorder/generic.h>\n#include <linux/of.h>\n\n#include \"mtdsplit.h\"\n\n#define WRGG_NR_PARTS\t\t2\n#define WRGG_MIN_ROOTFS_OFFS\t0x80000\t/* 512KiB */\n#define WRGG03_MAGIC\t\t0x20080321\n#define WRG_MAGIC\t\t0x20040220\n\nstruct wrgg03_header {\n\tchar\t\tsignature[32];\n\tuint32_t\tmagic1;\n\tuint32_t\tmagic2;\n\tchar\t\tversion[16];\n\tchar\t\tmodel[16];\n\tuint32_t\tflag[2];\n\tuint32_t\treserve[2];\n\tchar\t\tbuildno[16];\n\tuint32_t\tsize;\n\tuint32_t\toffset;\n\tchar\t\tdevname[32];\n\tchar\t\tdigest[16];\n} __attribute__ ((packed));\n\nstruct wrg_header {\n\tchar\t\tsignature[32];\n\tuint32_t\tmagic1;\n\tuint32_t\tmagic2;\n\tuint32_t\tsize;\n\tuint32_t\toffset;\n\tchar\t\tdevname[32];\n\tchar\t\tdigest[16];\n} __attribute__ ((packed));\n\n\nstatic int mtdsplit_parse_wrgg(struct mtd_info *master,\n\t\t\t       const struct mtd_partition **pparts,\n\t\t\t       struct mtd_part_parser_data *data)\n{\n\tstruct wrgg03_header hdr;\n\tsize_t hdr_len, retlen, kernel_ent_size;\n\tsize_t rootfs_offset;\n\tstruct mtd_partition *parts;\n\tenum mtdsplit_part_type type;\n\tint err;\n\n\thdr_len = sizeof(hdr);\n\terr = mtd_read(master, 0, hdr_len, &retlen, (void *) &hdr);\n\tif (err)\n\t\treturn err;\n\n\tif (retlen != hdr_len)\n\t\treturn -EIO;\n\n\t/* sanity checks */\n\tif (le32_to_cpu(hdr.magic1) == WRGG03_MAGIC) {\n\t\tkernel_ent_size = hdr_len + be32_to_cpu(hdr.size);\n\t\t/*\n\t\t * If this becomes silly big it's probably because the\n\t\t * WRGG image is little-endian.\n\t\t */\n\t\tif (kernel_ent_size > master->size)\n\t\t\tkernel_ent_size = hdr_len + le32_to_cpu(hdr.size);\n\n\t\t/* Now what ?! It's neither */\n\t\tif (kernel_ent_size > master->size)\n\t\t\treturn -EINVAL;\n\t} else if (le32_to_cpu(hdr.magic1) == WRG_MAGIC) {\n\t\tkernel_ent_size = sizeof(struct wrg_header) + le32_to_cpu(\n\t\t                  ((struct wrg_header*)&hdr)->size);\n\t} else {\n\t\treturn -EINVAL;\n\t}\n\n\tif (kernel_ent_size > master->size)\n\t\treturn -EINVAL;\n\n\t/*\n\t * The size in the header covers the rootfs as well.\n\t * Start the search from an arbitrary offset.\n\t */\n\terr = mtd_find_rootfs_from(master, WRGG_MIN_ROOTFS_OFFS,\n\t\t\t\t   master->size, &rootfs_offset, &type);\n\tif (err)\n\t\treturn err;\n\n\tparts = kzalloc(WRGG_NR_PARTS * sizeof(*parts), GFP_KERNEL);\n\tif (!parts)\n\t\treturn -ENOMEM;\n\n\tparts[0].name = KERNEL_PART_NAME;\n\tparts[0].offset = 0;\n\tparts[0].size = rootfs_offset;\n\n\tparts[1].name = ROOTFS_PART_NAME;\n\tparts[1].offset = rootfs_offset;\n\tparts[1].size = master->size - rootfs_offset;\n\n\t*pparts = parts;\n\treturn WRGG_NR_PARTS;\n}\n\nstatic const struct of_device_id mtdsplit_wrgg_of_match_table[] = {\n\t{ .compatible = \"wrg\" },\n\t{},\n};\nMODULE_DEVICE_TABLE(of, mtdsplit_wrgg_of_match_table);\n\nstatic struct mtd_part_parser mtdsplit_wrgg_parser = {\n\t.owner = THIS_MODULE,\n\t.name = \"wrgg-fw\",\n\t.of_match_table = mtdsplit_wrgg_of_match_table,\n\t.parse_fn = mtdsplit_parse_wrgg,\n\t.type = MTD_PARSER_TYPE_FIRMWARE,\n};\n\nstatic int __init mtdsplit_wrgg_init(void)\n{\n\tregister_mtd_parser(&mtdsplit_wrgg_parser);\n\n\treturn 0;\n}\n\nsubsys_initcall(mtdsplit_wrgg_init);\n"
  },
  {
    "path": "target/linux/generic/files/drivers/mtd/nand/mtk_bmt.c",
    "content": "/*\n * Copyright (c) 2017 MediaTek Inc.\n * Author: Xiangsheng Hou <xiangsheng.hou@mediatek.com>\n * Copyright (c) 2020-2022 Felix Fietkau <nbd@nbd.name>\n *\n * This program is free software; you can redistribute it and/or modify\n * it under the terms of the GNU General Public License version 2 as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n * GNU General Public License for more details.\n */\n\n#include <linux/module.h>\n#include <linux/gfp.h>\n#include <linux/slab.h>\n#include <linux/bits.h>\n#include \"mtk_bmt.h\"\n\nstruct bmt_desc bmtd = {};\n\n/* -------- Nand operations wrapper -------- */\nint bbt_nand_copy(u16 dest_blk, u16 src_blk, loff_t max_offset)\n{\n\tint pages = bmtd.blk_size >> bmtd.pg_shift;\n\tloff_t src = (loff_t)src_blk << bmtd.blk_shift;\n\tloff_t dest = (loff_t)dest_blk << bmtd.blk_shift;\n\tloff_t offset = 0;\n\tuint8_t oob[64];\n\tint i, ret;\n\n\tfor (i = 0; i < pages; i++) {\n\t\tstruct mtd_oob_ops rd_ops = {\n\t\t\t.mode = MTD_OPS_PLACE_OOB,\n\t\t\t.oobbuf = oob,\n\t\t\t.ooblen = min_t(int, bmtd.mtd->oobsize / pages, sizeof(oob)),\n\t\t\t.datbuf = bmtd.data_buf,\n\t\t\t.len = bmtd.pg_size,\n\t\t};\n\t\tstruct mtd_oob_ops wr_ops = {\n\t\t\t.mode = MTD_OPS_PLACE_OOB,\n\t\t\t.oobbuf = oob,\n\t\t\t.datbuf = bmtd.data_buf,\n\t\t\t.len = bmtd.pg_size,\n\t\t};\n\n\t\tif (offset >= max_offset)\n\t\t\tbreak;\n\n\t\tret = bmtd._read_oob(bmtd.mtd, src + offset, &rd_ops);\n\t\tif (ret < 0 && !mtd_is_bitflip(ret))\n\t\t\treturn ret;\n\n\t\tif (!rd_ops.retlen)\n\t\t\tbreak;\n\n\t\tret = bmtd._write_oob(bmtd.mtd, dest + offset, &wr_ops);\n\t\tif (ret < 0)\n\t\t\treturn ret;\n\n\t\twr_ops.ooblen = rd_ops.oobretlen;\n\t\toffset += rd_ops.retlen;\n\t}\n\n\treturn 0;\n}\n\n/* -------- Bad Blocks Management -------- */\nbool mapping_block_in_range(int block, int *start, int *end)\n{\n\tconst __be32 *cur = bmtd.remap_range;\n\tu32 addr = block << bmtd.blk_shift;\n\tint i;\n\n\tif (!cur || !bmtd.remap_range_len) {\n\t\t*start = 0;\n\t\t*end = bmtd.total_blks;\n\t\treturn true;\n\t}\n\n\tfor (i = 0; i < bmtd.remap_range_len; i++, cur += 2) {\n\t\tif (addr < be32_to_cpu(cur[0]) || addr >= be32_to_cpu(cur[1]))\n\t\t\tcontinue;\n\n\t\t*start = be32_to_cpu(cur[0]);\n\t\t*end = be32_to_cpu(cur[1]);\n\t\treturn true;\n\t}\n\n\treturn false;\n}\n\nstatic bool\nmtk_bmt_remap_block(u32 block, u32 mapped_block, int copy_len)\n{\n\tint start, end;\n\n\tif (!mapping_block_in_range(block, &start, &end))\n\t\treturn false;\n\n\treturn bmtd.ops->remap_block(block, mapped_block, copy_len);\n}\n\nstatic int\nmtk_bmt_read(struct mtd_info *mtd, loff_t from,\n\t     struct mtd_oob_ops *ops)\n{\n\tstruct mtd_oob_ops cur_ops = *ops;\n\tint retry_count = 0;\n\tloff_t cur_from;\n\tint ret = 0;\n\tint max_bitflips = 0;\n\n\tops->retlen = 0;\n\tops->oobretlen = 0;\n\n\twhile (ops->retlen < ops->len || ops->oobretlen < ops->ooblen) {\n\t\tint cur_ret;\n\n\t\tu32 offset = from & (bmtd.blk_size - 1);\n\t\tu32 block = from >> bmtd.blk_shift;\n\t\tint cur_block;\n\n\t\tcur_block = bmtd.ops->get_mapping_block(block);\n\t\tif (cur_block < 0)\n\t\t\treturn -EIO;\n\n\t\tcur_from = ((loff_t)cur_block << bmtd.blk_shift) + offset;\n\n\t\tcur_ops.oobretlen = 0;\n\t\tcur_ops.retlen = 0;\n\t\tcur_ops.len = min_t(u32, mtd->erasesize - offset,\n\t\t\t\t\t ops->len - ops->retlen);\n\t\tcur_ret = bmtd._read_oob(mtd, cur_from, &cur_ops);\n\t\tif (cur_ret < 0)\n\t\t\tret = cur_ret;\n\t\telse\n\t\t\tmax_bitflips = max_t(int, max_bitflips, cur_ret);\n\t\tif (cur_ret < 0 && !mtd_is_bitflip(cur_ret)) {\n\t\t\tif (mtk_bmt_remap_block(block, cur_block, mtd->erasesize) &&\n\t\t\t\tretry_count++ < 10)\n\t\t\t\tcontinue;\n\n\t\t\tgoto out;\n\t\t}\n\n\t\tif (mtd->bitflip_threshold && cur_ret >= mtd->bitflip_threshold)\n\t\t\tmtk_bmt_remap_block(block, cur_block, mtd->erasesize);\n\n\t\tops->retlen += cur_ops.retlen;\n\t\tops->oobretlen += cur_ops.oobretlen;\n\n\t\tcur_ops.ooboffs = 0;\n\t\tcur_ops.datbuf += cur_ops.retlen;\n\t\tcur_ops.oobbuf += cur_ops.oobretlen;\n\t\tcur_ops.ooblen -= cur_ops.oobretlen;\n\n\t\tif (!cur_ops.len)\n\t\t\tcur_ops.len = mtd->erasesize - offset;\n\n\t\tfrom += cur_ops.len;\n\t\tretry_count = 0;\n\t}\n\nout:\n\tif (ret < 0)\n\t\treturn ret;\n\n\treturn max_bitflips;\n}\n\nstatic int\nmtk_bmt_write(struct mtd_info *mtd, loff_t to,\n\t      struct mtd_oob_ops *ops)\n{\n\tstruct mtd_oob_ops cur_ops = *ops;\n\tint retry_count = 0;\n\tloff_t cur_to;\n\tint ret;\n\n\tops->retlen = 0;\n\tops->oobretlen = 0;\n\n\twhile (ops->retlen < ops->len || ops->oobretlen < ops->ooblen) {\n\t\tu32 offset = to & (bmtd.blk_size - 1);\n\t\tu32 block = to >> bmtd.blk_shift;\n\t\tint cur_block;\n\n\t\tcur_block = bmtd.ops->get_mapping_block(block);\n\t\tif (cur_block < 0)\n\t\t\treturn -EIO;\n\n\t\tcur_to = ((loff_t)cur_block << bmtd.blk_shift) + offset;\n\n\t\tcur_ops.oobretlen = 0;\n\t\tcur_ops.retlen = 0;\n\t\tcur_ops.len = min_t(u32, bmtd.blk_size - offset,\n\t\t\t\t\t ops->len - ops->retlen);\n\t\tret = bmtd._write_oob(mtd, cur_to, &cur_ops);\n\t\tif (ret < 0) {\n\t\t\tif (mtk_bmt_remap_block(block, cur_block, offset) &&\n\t\t\t    retry_count++ < 10)\n\t\t\t\tcontinue;\n\n\t\t\treturn ret;\n\t\t}\n\n\t\tops->retlen += cur_ops.retlen;\n\t\tops->oobretlen += cur_ops.oobretlen;\n\n\t\tcur_ops.ooboffs = 0;\n\t\tcur_ops.datbuf += cur_ops.retlen;\n\t\tcur_ops.oobbuf += cur_ops.oobretlen;\n\t\tcur_ops.ooblen -= cur_ops.oobretlen;\n\n\t\tif (!cur_ops.len)\n\t\t\tcur_ops.len = mtd->erasesize - offset;\n\n\t\tto += cur_ops.len;\n\t\tretry_count = 0;\n\t}\n\n\treturn 0;\n}\n\nstatic int\nmtk_bmt_mtd_erase(struct mtd_info *mtd, struct erase_info *instr)\n{\n\tstruct erase_info mapped_instr = {\n\t\t.len = bmtd.blk_size,\n\t};\n\tint retry_count = 0;\n\tu64 start_addr, end_addr;\n\tint ret;\n\tu16 orig_block;\n\tint block;\n\n\tstart_addr = instr->addr & (~mtd->erasesize_mask);\n\tend_addr = instr->addr + instr->len;\n\n\twhile (start_addr < end_addr) {\n\t\torig_block = start_addr >> bmtd.blk_shift;\n\t\tblock = bmtd.ops->get_mapping_block(orig_block);\n\t\tif (block < 0)\n\t\t\treturn -EIO;\n\t\tmapped_instr.addr = (loff_t)block << bmtd.blk_shift;\n\t\tret = bmtd._erase(mtd, &mapped_instr);\n\t\tif (ret) {\n\t\t\tif (mtk_bmt_remap_block(orig_block, block, 0) &&\n\t\t\t    retry_count++ < 10)\n\t\t\t\tcontinue;\n\t\t\tinstr->fail_addr = start_addr;\n\t\t\tbreak;\n\t\t}\n\t\tstart_addr += mtd->erasesize;\n\t\tretry_count = 0;\n\t}\n\n\treturn ret;\n}\nstatic int\nmtk_bmt_block_isbad(struct mtd_info *mtd, loff_t ofs)\n{\n\tint retry_count = 0;\n\tu16 orig_block = ofs >> bmtd.blk_shift;\n\tu16 block;\n\tint ret;\n\nretry:\n\tblock = bmtd.ops->get_mapping_block(orig_block);\n\tret = bmtd._block_isbad(mtd, (loff_t)block << bmtd.blk_shift);\n\tif (ret) {\n\t\tif (mtk_bmt_remap_block(orig_block, block, bmtd.blk_size) &&\n\t\t    retry_count++ < 10)\n\t\t\tgoto retry;\n\t}\n\treturn ret;\n}\n\nstatic int\nmtk_bmt_block_markbad(struct mtd_info *mtd, loff_t ofs)\n{\n\tu16 orig_block = ofs >> bmtd.blk_shift;\n\tint block;\n\n\tblock = bmtd.ops->get_mapping_block(orig_block);\n\tif (block < 0)\n\t\treturn -EIO;\n\n\tmtk_bmt_remap_block(orig_block, block, bmtd.blk_size);\n\n\treturn bmtd._block_markbad(mtd, (loff_t)block << bmtd.blk_shift);\n}\n\nstatic void\nmtk_bmt_replace_ops(struct mtd_info *mtd)\n{\n\tbmtd._read_oob = mtd->_read_oob;\n\tbmtd._write_oob = mtd->_write_oob;\n\tbmtd._erase = mtd->_erase;\n\tbmtd._block_isbad = mtd->_block_isbad;\n\tbmtd._block_markbad = mtd->_block_markbad;\n\n\tmtd->_read_oob = mtk_bmt_read;\n\tmtd->_write_oob = mtk_bmt_write;\n\tmtd->_erase = mtk_bmt_mtd_erase;\n\tmtd->_block_isbad = mtk_bmt_block_isbad;\n\tmtd->_block_markbad = mtk_bmt_block_markbad;\n}\n\nstatic int mtk_bmt_debug_repair(void *data, u64 val)\n{\n\tint block = val >> bmtd.blk_shift;\n\tint prev_block, new_block;\n\n\tprev_block = bmtd.ops->get_mapping_block(block);\n\tif (prev_block < 0)\n\t\treturn -EIO;\n\n\tbmtd.ops->unmap_block(block);\n\tnew_block = bmtd.ops->get_mapping_block(block);\n\tif (new_block < 0)\n\t\treturn -EIO;\n\n\tif (prev_block == new_block)\n\t\treturn 0;\n\n\tbbt_nand_erase(new_block);\n\tbbt_nand_copy(new_block, prev_block, bmtd.blk_size);\n\n\treturn 0;\n}\n\nstatic int mtk_bmt_debug_mark_good(void *data, u64 val)\n{\n\tbmtd.ops->unmap_block(val >> bmtd.blk_shift);\n\n\treturn 0;\n}\n\nstatic int mtk_bmt_debug_mark_bad(void *data, u64 val)\n{\n\tu32 block = val >> bmtd.blk_shift;\n\tint cur_block;\n\n\tcur_block = bmtd.ops->get_mapping_block(block);\n\tif (cur_block < 0)\n\t\treturn -EIO;\n\n\tmtk_bmt_remap_block(block, cur_block, bmtd.blk_size);\n\n\treturn 0;\n}\n\nstatic int mtk_bmt_debug(void *data, u64 val)\n{\n\treturn bmtd.ops->debug(data, val);\n}\n\n\nDEFINE_DEBUGFS_ATTRIBUTE(fops_repair, NULL, mtk_bmt_debug_repair, \"%llu\\n\");\nDEFINE_DEBUGFS_ATTRIBUTE(fops_mark_good, NULL, mtk_bmt_debug_mark_good, \"%llu\\n\");\nDEFINE_DEBUGFS_ATTRIBUTE(fops_mark_bad, NULL, mtk_bmt_debug_mark_bad, \"%llu\\n\");\nDEFINE_DEBUGFS_ATTRIBUTE(fops_debug, NULL, mtk_bmt_debug, \"%llu\\n\");\n\nstatic void\nmtk_bmt_add_debugfs(void)\n{\n\tstruct dentry *dir;\n\n\tdir = bmtd.debugfs_dir = debugfs_create_dir(\"mtk-bmt\", NULL);\n\tif (!dir)\n\t\treturn;\n\n\tdebugfs_create_file_unsafe(\"repair\", S_IWUSR, dir, NULL, &fops_repair);\n\tdebugfs_create_file_unsafe(\"mark_good\", S_IWUSR, dir, NULL, &fops_mark_good);\n\tdebugfs_create_file_unsafe(\"mark_bad\", S_IWUSR, dir, NULL, &fops_mark_bad);\n\tdebugfs_create_file_unsafe(\"debug\", S_IWUSR, dir, NULL, &fops_debug);\n}\n\nvoid mtk_bmt_detach(struct mtd_info *mtd)\n{\n\tif (bmtd.mtd != mtd)\n\t\treturn;\n\n\tif (bmtd.debugfs_dir)\n\t\tdebugfs_remove_recursive(bmtd.debugfs_dir);\n\tbmtd.debugfs_dir = NULL;\n\n\tkfree(bmtd.bbt_buf);\n\tkfree(bmtd.data_buf);\n\n\tmtd->_read_oob = bmtd._read_oob;\n\tmtd->_write_oob = bmtd._write_oob;\n\tmtd->_erase = bmtd._erase;\n\tmtd->_block_isbad = bmtd._block_isbad;\n\tmtd->_block_markbad = bmtd._block_markbad;\n\tmtd->size = bmtd.total_blks << bmtd.blk_shift;\n\n\tmemset(&bmtd, 0, sizeof(bmtd));\n}\n\n\nint mtk_bmt_attach(struct mtd_info *mtd)\n{\n\tstruct device_node *np;\n\tint ret = 0;\n\n\tif (bmtd.mtd)\n\t\treturn -ENOSPC;\n\n\tnp = mtd_get_of_node(mtd);\n\tif (!np)\n\t\treturn 0;\n\n\tif (of_property_read_bool(np, \"mediatek,bmt-v2\"))\n\t\tbmtd.ops = &mtk_bmt_v2_ops;\n\telse if (of_property_read_bool(np, \"mediatek,nmbm\"))\n\t\tbmtd.ops = &mtk_bmt_nmbm_ops;\n\telse if (of_property_read_bool(np, \"mediatek,bbt\"))\n\t\tbmtd.ops = &mtk_bmt_bbt_ops;\n\telse\n\t\treturn 0;\n\n\tbmtd.remap_range = of_get_property(np, \"mediatek,bmt-remap-range\",\n\t\t\t\t\t   &bmtd.remap_range_len);\n\tbmtd.remap_range_len /= 8;\n\n\tbmtd.mtd = mtd;\n\tmtk_bmt_replace_ops(mtd);\n\n\tbmtd.blk_size = mtd->erasesize;\n\tbmtd.blk_shift = ffs(bmtd.blk_size) - 1;\n\tbmtd.pg_size = mtd->writesize;\n\tbmtd.pg_shift = ffs(bmtd.pg_size) - 1;\n\tbmtd.total_blks = mtd->size >> bmtd.blk_shift;\n\n\tbmtd.data_buf = kzalloc(bmtd.pg_size + bmtd.mtd->oobsize, GFP_KERNEL);\n\tif (!bmtd.data_buf) {\n\t\tpr_info(\"nand: FATAL ERR: allocate buffer failed!\\n\");\n\t\tret = -1;\n\t\tgoto error;\n\t}\n\n\tmemset(bmtd.data_buf, 0xff, bmtd.pg_size + bmtd.mtd->oobsize);\n\n\tret = bmtd.ops->init(np);\n\tif (ret)\n\t\tgoto error;\n\n\tmtk_bmt_add_debugfs();\n\treturn 0;\n\nerror:\n\tmtk_bmt_detach(mtd);\n\treturn ret;\n}\n\n\nMODULE_LICENSE(\"GPL\");\nMODULE_AUTHOR(\"Xiangsheng Hou <xiangsheng.hou@mediatek.com>, Felix Fietkau <nbd@nbd.name>\");\nMODULE_DESCRIPTION(\"Bad Block mapping management v2 for MediaTek NAND Flash Driver\");\n\n"
  },
  {
    "path": "target/linux/generic/files/drivers/mtd/nand/mtk_bmt.h",
    "content": "#ifndef __MTK_BMT_PRIV_H\n#define __MTK_BMT_PRIV_H\n\n#include <linux/kernel.h>\n#include <linux/of.h>\n#include <linux/mtd/mtd.h>\n#include <linux/mtd/partitions.h>\n#include <linux/mtd/mtk_bmt.h>\n#include <linux/debugfs.h>\n\n#define MAIN_SIGNATURE_OFFSET   0\n#define OOB_SIGNATURE_OFFSET    1\n\n#define BBT_LOG(fmt, ...) pr_debug(\"[BBT][%s|%d] \"fmt\"\\n\", __func__, __LINE__, ##__VA_ARGS__)\n\nstruct mtk_bmt_ops {\n\tchar *sig;\n\tunsigned int sig_len;\n\tint (*init)(struct device_node *np);\n\tbool (*remap_block)(u16 block, u16 mapped_block, int copy_len);\n\tvoid (*unmap_block)(u16 block);\n\tint (*get_mapping_block)(int block);\n\tint (*debug)(void *data, u64 val);\n};\n\nstruct bbbt;\nstruct nmbm_instance;\n\nstruct bmt_desc {\n\tstruct mtd_info *mtd;\n\tunsigned char *bbt_buf;\n\tunsigned char *data_buf;\n\n\tint (*_read_oob) (struct mtd_info *mtd, loff_t from,\n\t\t\t  struct mtd_oob_ops *ops);\n\tint (*_write_oob) (struct mtd_info *mtd, loff_t to,\n\t\t\t   struct mtd_oob_ops *ops);\n\tint (*_erase) (struct mtd_info *mtd, struct erase_info *instr);\n\tint (*_block_isbad) (struct mtd_info *mtd, loff_t ofs);\n\tint (*_block_markbad) (struct mtd_info *mtd, loff_t ofs);\n\n\tconst struct mtk_bmt_ops *ops;\n\n\tunion {\n\t\tstruct bbbt *bbt;\n\t\tstruct nmbm_instance *ni;\n\t};\n\n\tstruct dentry *debugfs_dir;\n\n\tu32 table_size;\n\tu32 pg_size;\n\tu32 blk_size;\n\tu16 pg_shift;\n\tu16 blk_shift;\n\t/* bbt logical address */\n\tu16 pool_lba;\n\t/* bbt physical address */\n\tu16 pool_pba;\n\t/* Maximum count of bad blocks that the vendor guaranteed */\n\tu16 bb_max;\n\t/* Total blocks of the Nand Chip */\n\tu16 total_blks;\n\t/* The block(n) BMT is located at (bmt_tbl[n]) */\n\tu16 bmt_blk_idx;\n\t/* How many pages needs to store 'struct bbbt' */\n\tu32 bmt_pgs;\n\n\tconst __be32 *remap_range;\n\tint remap_range_len;\n\n\t/* to compensate for driver level remapping */\n\tu8 oob_offset;\n};\n\nextern struct bmt_desc bmtd;\nextern const struct mtk_bmt_ops mtk_bmt_v2_ops;\nextern const struct mtk_bmt_ops mtk_bmt_bbt_ops;\nextern const struct mtk_bmt_ops mtk_bmt_nmbm_ops;\n\nstatic inline u32 blk_pg(u16 block)\n{\n\treturn (u32)(block << (bmtd.blk_shift - bmtd.pg_shift));\n}\n\nstatic inline int\nbbt_nand_read(u32 page, unsigned char *dat, int dat_len,\n\t      unsigned char *fdm, int fdm_len)\n{\n\tstruct mtd_oob_ops ops = {\n\t\t.mode = MTD_OPS_PLACE_OOB,\n\t\t.ooboffs = bmtd.oob_offset,\n\t\t.oobbuf = fdm,\n\t\t.ooblen = fdm_len,\n\t\t.datbuf = dat,\n\t\t.len = dat_len,\n\t};\n\n\treturn bmtd._read_oob(bmtd.mtd, page << bmtd.pg_shift, &ops);\n}\n\nstatic inline int bbt_nand_erase(u16 block)\n{\n\tstruct mtd_info *mtd = bmtd.mtd;\n\tstruct erase_info instr = {\n\t\t.addr = (loff_t)block << bmtd.blk_shift,\n\t\t.len = bmtd.blk_size,\n\t};\n\n\treturn bmtd._erase(mtd, &instr);\n}\n\nstatic inline int write_bmt(u16 block, unsigned char *dat)\n{\n\tstruct mtd_oob_ops ops = {\n\t\t.mode = MTD_OPS_PLACE_OOB,\n\t\t.ooboffs = OOB_SIGNATURE_OFFSET + bmtd.oob_offset,\n\t\t.oobbuf = bmtd.ops->sig,\n\t\t.ooblen = bmtd.ops->sig_len,\n\t\t.datbuf = dat,\n\t\t.len = bmtd.bmt_pgs << bmtd.pg_shift,\n\t};\n\tloff_t addr = (loff_t)block << bmtd.blk_shift;\n\n\treturn bmtd._write_oob(bmtd.mtd, addr, &ops);\n}\n\nint bbt_nand_copy(u16 dest_blk, u16 src_blk, loff_t max_offset);\nbool mapping_block_in_range(int block, int *start, int *end);\n\n#endif\n"
  },
  {
    "path": "target/linux/generic/files/drivers/mtd/nand/mtk_bmt_bbt.c",
    "content": "/*\n * Copyright (c) 2017 MediaTek Inc.\n * Author: Xiangsheng Hou <xiangsheng.hou@mediatek.com>\n * Copyright (c) 2020-2022 Felix Fietkau <nbd@nbd.name>\n *\n * This program is free software; you can redistribute it and/or modify\n * it under the terms of the GNU General Public License version 2 as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n * GNU General Public License for more details.\n */\n\n#include <linux/kernel.h>\n#include <linux/slab.h>\n#include \"mtk_bmt.h\"\n\nstatic bool\nbbt_block_is_bad(u16 block)\n{\n\tu8 cur = bmtd.bbt_buf[block / 4];\n\n\treturn cur & (3 << ((block % 4) * 2));\n}\n\nstatic void\nbbt_set_block_state(u16 block, bool bad)\n{\n\tu8 mask = (3 << ((block % 4) * 2));\n\n\tif (bad)\n\t\tbmtd.bbt_buf[block / 4] |= mask;\n\telse\n\t\tbmtd.bbt_buf[block / 4] &= ~mask;\n\n\tbbt_nand_erase(bmtd.bmt_blk_idx);\n\twrite_bmt(bmtd.bmt_blk_idx, bmtd.bbt_buf);\n}\n\nstatic int\nget_mapping_block_index_bbt(int block)\n{\n\tint start, end, ofs;\n\tint bad_blocks = 0;\n\tint i;\n\n\tif (!mapping_block_in_range(block, &start, &end))\n\t\treturn block;\n\n\tstart >>= bmtd.blk_shift;\n\tend >>= bmtd.blk_shift;\n\t/* skip bad blocks within the mapping range */\n\tofs = block - start;\n\tfor (i = start; i < end; i++) {\n\t\tif (bbt_block_is_bad(i))\n\t\t\tbad_blocks++;\n\t\telse if (ofs)\n\t\t\tofs--;\n\t\telse\n\t\t\tbreak;\n\t}\n\n\tif (i < end)\n\t\treturn i;\n\n\t/* when overflowing, remap remaining blocks to bad ones */\n\tfor (i = end - 1; bad_blocks > 0; i--) {\n\t\tif (!bbt_block_is_bad(i))\n\t\t\tcontinue;\n\n\t\tbad_blocks--;\n\t\tif (bad_blocks <= ofs)\n\t\t\treturn i;\n\t}\n\n\treturn block;\n}\n\nstatic bool remap_block_bbt(u16 block, u16 mapped_blk, int copy_len)\n{\n\tint start, end;\n\tu16 new_blk;\n\n\tif (!mapping_block_in_range(block, &start, &end))\n\t\treturn false;\n\n\tbbt_set_block_state(mapped_blk, true);\n\n\tnew_blk = get_mapping_block_index_bbt(block);\n\tbbt_nand_erase(new_blk);\n\tif (copy_len > 0)\n\t\tbbt_nand_copy(new_blk, mapped_blk, copy_len);\n\n\treturn true;\n}\n\nstatic void\nunmap_block_bbt(u16 block)\n{\n\tbbt_set_block_state(block, false);\n}\n\nstatic int\nmtk_bmt_read_bbt(void)\n{\n\tu8 oob_buf[8];\n\tint i;\n\n\tfor (i = bmtd.total_blks - 1; i >= bmtd.total_blks - 5; i--) {\n\t\tu32 page = i << (bmtd.blk_shift - bmtd.pg_shift);\n\n\t\tif (bbt_nand_read(page, bmtd.bbt_buf, bmtd.pg_size,\n\t\t\t\t  oob_buf, sizeof(oob_buf))) {\n\t\t\tpr_info(\"read_bbt: could not read block %d\\n\", i);\n\t\t\tcontinue;\n\t\t}\n\n\t\tif (oob_buf[0] != 0xff) {\n\t\t\tpr_info(\"read_bbt: bad block at %d\\n\", i);\n\t\t\tcontinue;\n\t\t}\n\n\t\tif (memcmp(&oob_buf[1], \"mtknand\", 7) != 0) {\n\t\t\tpr_info(\"read_bbt: signature mismatch in block %d\\n\", i);\n\t\t\tprint_hex_dump(KERN_INFO, \"\", DUMP_PREFIX_OFFSET, 16, 1, oob_buf, 8, 1);\n\t\t\tcontinue;\n\t\t}\n\n\t\tpr_info(\"read_bbt: found bbt at block %d\\n\", i);\n\t\tbmtd.bmt_blk_idx = i;\n\t\treturn 0;\n\t}\n\n\treturn -EIO;\n}\n\n\nstatic int\nmtk_bmt_init_bbt(struct device_node *np)\n{\n\tint buf_size = round_up(bmtd.total_blks >> 2, bmtd.blk_size);\n\tint ret;\n\n\tbmtd.bbt_buf = kmalloc(buf_size, GFP_KERNEL);\n\tif (!bmtd.bbt_buf)\n\t\treturn -ENOMEM;\n\n\tmemset(bmtd.bbt_buf, 0xff, buf_size);\n\tbmtd.mtd->size -= 4 * bmtd.mtd->erasesize;\n\n\tret = mtk_bmt_read_bbt();\n\tif (ret)\n\t\treturn ret;\n\n\tbmtd.bmt_pgs = buf_size / bmtd.pg_size;\n\n\treturn 0;\n}\n\nstatic int mtk_bmt_debug_bbt(void *data, u64 val)\n{\n\tchar buf[5];\n\tint i, k;\n\n\tswitch (val) {\n\tcase 0:\n\t\tfor (i = 0; i < bmtd.total_blks; i += 4) {\n\t\t\tu8 cur = bmtd.bbt_buf[i / 4];\n\n\t\t\tfor (k = 0; k < 4; k++, cur >>= 2)\n\t\t\t\tbuf[k] = (cur & 3) ? 'B' : '.';\n\n\t\t\tbuf[4] = 0;\n\t\t\tprintk(\"[%06x] %s\\n\", i * bmtd.blk_size, buf);\n\t\t}\n\t\tbreak;\n\tcase 100:\n#if 0\n\t\tfor (i = bmtd.bmt_blk_idx; i < bmtd.total_blks - 1; i++)\n\t\t\tbbt_nand_erase(bmtd.bmt_blk_idx);\n#endif\n\n\t\tbmtd.bmt_blk_idx = bmtd.total_blks - 1;\n\t\tbbt_nand_erase(bmtd.bmt_blk_idx);\n\t\twrite_bmt(bmtd.bmt_blk_idx, bmtd.bbt_buf);\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\treturn 0;\n}\n\nconst struct mtk_bmt_ops mtk_bmt_bbt_ops = {\n\t.sig = \"mtknand\",\n\t.sig_len = 7,\n\t.init = mtk_bmt_init_bbt,\n\t.remap_block = remap_block_bbt,\n\t.unmap_block = unmap_block_bbt,\n\t.get_mapping_block = get_mapping_block_index_bbt,\n\t.debug = mtk_bmt_debug_bbt,\n};\n"
  },
  {
    "path": "target/linux/generic/files/drivers/mtd/nand/mtk_bmt_nmbm.c",
    "content": "#include <linux/crc32.h>\n#include <linux/slab.h>\n#include \"mtk_bmt.h\"\n\n#define nlog_err(ni, ...) printk(KERN_ERR __VA_ARGS__)\n#define nlog_info(ni, ...) printk(KERN_INFO __VA_ARGS__)\n#define nlog_debug(ni, ...) printk(KERN_INFO __VA_ARGS__)\n#define nlog_warn(ni, ...) printk(KERN_WARNING __VA_ARGS__)\n\n#define NMBM_MAGIC_SIGNATURE\t\t\t0x304d4d4e\t/* NMM0 */\n#define NMBM_MAGIC_INFO_TABLE\t\t\t0x314d4d4e\t/* NMM1 */\n\n#define NMBM_VERSION_MAJOR_S\t\t\t0\n#define NMBM_VERSION_MAJOR_M\t\t\t0xffff\n#define NMBM_VERSION_MINOR_S\t\t\t16\n#define NMBM_VERSION_MINOR_M\t\t\t0xffff\n#define NMBM_VERSION_MAKE(major, minor)\t\t(((major) & NMBM_VERSION_MAJOR_M) | \\\n\t\t\t\t\t\t(((minor) & NMBM_VERSION_MINOR_M) << \\\n\t\t\t\t\t\tNMBM_VERSION_MINOR_S))\n#define NMBM_VERSION_MAJOR_GET(ver)\t\t(((ver) >> NMBM_VERSION_MAJOR_S) & \\\n\t\t\t\t\t\tNMBM_VERSION_MAJOR_M)\n#define NMBM_VERSION_MINOR_GET(ver)\t\t(((ver) >> NMBM_VERSION_MINOR_S) & \\\n\t\t\t\t\t\tNMBM_VERSION_MINOR_M)\n\n#define NMBM_BITMAP_UNIT_SIZE\t\t\t(sizeof(u32))\n#define NMBM_BITMAP_BITS_PER_BLOCK\t\t2\n#define NMBM_BITMAP_BITS_PER_UNIT\t\t(8 * sizeof(u32))\n#define NMBM_BITMAP_BLOCKS_PER_UNIT\t\t(NMBM_BITMAP_BITS_PER_UNIT / \\\n\t\t\t\t\t\t NMBM_BITMAP_BITS_PER_BLOCK)\n\n#define NMBM_SPARE_BLOCK_MULTI\t\t\t1\n#define NMBM_SPARE_BLOCK_DIV\t\t\t2\n#define NMBM_SPARE_BLOCK_MIN\t\t\t2\n\n#define NMBM_MGMT_DIV\t\t\t\t16\n#define NMBM_MGMT_BLOCKS_MIN\t\t\t32\n\n#define NMBM_TRY_COUNT\t\t\t\t3\n\n#define BLOCK_ST_BAD\t\t\t\t0\n#define BLOCK_ST_NEED_REMAP\t\t\t2\n#define BLOCK_ST_GOOD\t\t\t\t3\n#define BLOCK_ST_MASK\t\t\t\t3\n\n#define NMBM_VER_MAJOR\t\t\t1\n#define NMBM_VER_MINOR\t\t\t0\n#define NMBM_VER\t\t\tNMBM_VERSION_MAKE(NMBM_VER_MAJOR, \\\n\t\t\t\t\t\t\t  NMBM_VER_MINOR)\n\nstruct nmbm_header {\n\tu32 magic;\n\tu32 version;\n\tu32 size;\n\tu32 checksum;\n};\n\nstruct nmbm_signature {\n\tstruct nmbm_header header;\n\tuint64_t nand_size;\n\tu32 block_size;\n\tu32 page_size;\n\tu32 spare_size;\n\tu32 mgmt_start_pb;\n\tu8 max_try_count;\n\tu8 padding[3];\n};\n\nstruct nmbm_info_table_header {\n\tstruct nmbm_header header;\n\tu32 write_count;\n\tu32 state_table_off;\n\tu32 mapping_table_off;\n\tu32 padding;\n};\n\nstruct nmbm_instance {\n\tu32 rawpage_size;\n\tu32 rawblock_size;\n\tu32 rawchip_size;\n\n\tstruct nmbm_signature signature;\n\n\tu8 *info_table_cache;\n\tu32 info_table_size;\n\tu32 info_table_spare_blocks;\n\tstruct nmbm_info_table_header info_table;\n\n\tu32 *block_state;\n\tu32 block_state_changed;\n\tu32 state_table_size;\n\n\tint32_t *block_mapping;\n\tu32 block_mapping_changed;\n\tu32 mapping_table_size;\n\n\tu8 *page_cache;\n\n\tint protected;\n\n\tu32 block_count;\n\tu32 data_block_count;\n\n\tu32 mgmt_start_ba;\n\tu32 main_table_ba;\n\tu32 backup_table_ba;\n\tu32 mapping_blocks_ba;\n\tu32 mapping_blocks_top_ba;\n\tu32 signature_ba;\n\n\tu32 max_ratio;\n\tu32 max_reserved_blocks;\n\tbool empty_page_ecc_ok;\n\tbool force_create;\n};\n\nstatic inline u32 nmbm_crc32(u32 crcval, const void *buf, size_t size)\n{\n\tunsigned int chksz;\n\tconst unsigned char *p = buf;\n\n\twhile (size) {\n\t\tif (size > UINT_MAX)\n\t\t\tchksz = UINT_MAX;\n\t\telse\n\t\t\tchksz = (uint)size;\n\n\t\tcrcval = crc32_le(crcval, p, chksz);\n\t\tsize -= chksz;\n\t\tp += chksz;\n\t}\n\n\treturn crcval;\n}\n/*\n * nlog_table_creation - Print log of table creation event\n * @ni: NMBM instance structure\n * @main_table: whether the table is main info table\n * @start_ba: start block address of the table\n * @end_ba: block address after the end of the table\n */\nstatic void nlog_table_creation(struct nmbm_instance *ni, bool main_table,\n\t\t\t       uint32_t start_ba, uint32_t end_ba)\n{\n\tif (start_ba == end_ba - 1)\n\t\tnlog_info(ni, \"%s info table has been written to block %u\\n\",\n\t\t\t main_table ? \"Main\" : \"Backup\", start_ba);\n\telse\n\t\tnlog_info(ni, \"%s info table has been written to block %u-%u\\n\",\n\t\t\t main_table ? \"Main\" : \"Backup\", start_ba, end_ba - 1);\n}\n\n/*\n * nlog_table_update - Print log of table update event\n * @ni: NMBM instance structure\n * @main_table: whether the table is main info table\n * @start_ba: start block address of the table\n * @end_ba: block address after the end of the table\n */\nstatic void nlog_table_update(struct nmbm_instance *ni, bool main_table,\n\t\t\t     uint32_t start_ba, uint32_t end_ba)\n{\n\tif (start_ba == end_ba - 1)\n\t\tnlog_debug(ni, \"%s info table has been updated in block %u\\n\",\n\t\t\t  main_table ? \"Main\" : \"Backup\", start_ba);\n\telse\n\t\tnlog_debug(ni, \"%s info table has been updated in block %u-%u\\n\",\n\t\t\t  main_table ? \"Main\" : \"Backup\", start_ba, end_ba - 1);\n}\n\n/*\n * nlog_table_found - Print log of table found event\n * @ni: NMBM instance structure\n * @first_table: whether the table is first found info table\n * @write_count: write count of the info table\n * @start_ba: start block address of the table\n * @end_ba: block address after the end of the table\n */\nstatic void nlog_table_found(struct nmbm_instance *ni, bool first_table,\n\t\t\t    uint32_t write_count, uint32_t start_ba,\n\t\t\t    uint32_t end_ba)\n{\n\tif (start_ba == end_ba - 1)\n\t\tnlog_info(ni, \"%s info table with writecount %u found in block %u\\n\",\n\t\t\t first_table ? \"First\" : \"Second\", write_count,\n\t\t\t start_ba);\n\telse\n\t\tnlog_info(ni, \"%s info table with writecount %u found in block %u-%u\\n\",\n\t\t\t first_table ? \"First\" : \"Second\", write_count,\n\t\t\t start_ba, end_ba - 1);\n}\n\n/*****************************************************************************/\n/* Address conversion functions */\n/*****************************************************************************/\n\n/*\n * ba2addr - Convert a block address to linear address\n * @ni: NMBM instance structure\n * @ba: Block address\n */\nstatic uint64_t ba2addr(struct nmbm_instance *ni, uint32_t ba)\n{\n\treturn (uint64_t)ba << bmtd.blk_shift;\n}\n/*\n * size2blk - Get minimum required blocks for storing specific size of data\n * @ni: NMBM instance structure\n * @size: size for storing\n */\nstatic uint32_t size2blk(struct nmbm_instance *ni, uint64_t size)\n{\n\treturn (size + bmtd.blk_size - 1) >> bmtd.blk_shift;\n}\n\n/*****************************************************************************/\n/* High level NAND chip APIs */\n/*****************************************************************************/\n\n/*\n * nmbm_read_phys_page - Read page with retry\n * @ni: NMBM instance structure\n * @addr: linear address where the data will be read from\n * @data: the main data to be read\n * @oob: the oob data to be read\n *\n * Read a page for at most NMBM_TRY_COUNT times.\n *\n * Return 0 for success, positive value for corrected bitflip count,\n * -EBADMSG for ecc error, other negative values for other errors\n */\nstatic int nmbm_read_phys_page(struct nmbm_instance *ni, uint64_t addr,\n\t\t\t       void *data, void *oob)\n{\n\tint tries, ret;\n\n\tfor (tries = 0; tries < NMBM_TRY_COUNT; tries++) {\n\t\tstruct mtd_oob_ops ops = {\n\t\t\t.mode = MTD_OPS_PLACE_OOB,\n\t\t\t.oobbuf = oob,\n\t\t\t.datbuf = data,\n\t\t};\n\n\t\tif (data)\n\t\t\tops.len = bmtd.pg_size;\n\t\tif (oob)\n\t\t\tops.ooblen = mtd_oobavail(bmtd.mtd, &ops);\n\n\t\tret = bmtd._read_oob(bmtd.mtd, addr, &ops);\n\t\tif (ret == -EUCLEAN)\n\t\t\treturn min_t(u32, bmtd.mtd->bitflip_threshold + 1,\n\t\t\t\t     bmtd.mtd->ecc_strength);\n\t\tif (ret >= 0)\n\t\t\treturn 0;\n\t}\n\n\tif (ret != -EBADMSG)\n\t\tnlog_err(ni, \"Page read failed at address 0x%08llx\\n\", addr);\n\n\treturn ret;\n}\n\n/*\n * nmbm_write_phys_page - Write page with retry\n * @ni: NMBM instance structure\n * @addr: linear address where the data will be written to\n * @data: the main data to be written\n * @oob: the oob data to be written\n *\n * Write a page for at most NMBM_TRY_COUNT times.\n */\nstatic bool nmbm_write_phys_page(struct nmbm_instance *ni, uint64_t addr,\n\t\t\t\t const void *data, const void *oob)\n{\n\tint tries, ret;\n\n\tfor (tries = 0; tries < NMBM_TRY_COUNT; tries++) {\n\t\tstruct mtd_oob_ops ops = {\n\t\t\t.mode = MTD_OPS_PLACE_OOB,\n\t\t\t.oobbuf = (void *)oob,\n\t\t\t.datbuf = (void *)data,\n\t\t};\n\n\t\tif (data)\n\t\t\tops.len = bmtd.pg_size;\n\t\tif (oob)\n\t\t\tops.ooblen = mtd_oobavail(bmtd.mtd, &ops);\n\n\t\tret = bmtd._write_oob(bmtd.mtd, addr, &ops);\n\t\tif (!ret)\n\t\t\treturn true;\n\t}\n\n\tnlog_err(ni, \"Page write failed at address 0x%08llx\\n\", addr);\n\n\treturn false;\n}\n\n/*\n * nmbm_erase_phys_block - Erase a block with retry\n * @ni: NMBM instance structure\n * @addr: Linear address\n *\n * Erase a block for at most NMBM_TRY_COUNT times.\n */\nstatic bool nmbm_erase_phys_block(struct nmbm_instance *ni, uint64_t addr)\n{\n\tint tries, ret;\n\n\tfor (tries = 0; tries < NMBM_TRY_COUNT; tries++) {\n\t\tstruct erase_info ei = {\n\t\t\t.addr = addr,\n\t\t\t.len = bmtd.mtd->erasesize,\n\t\t};\n\n\t\tret = bmtd._erase(bmtd.mtd, &ei);\n\t\tif (!ret)\n\t\t\treturn true;\n\t}\n\n\tnlog_err(ni, \"Block erasure failed at address 0x%08llx\\n\", addr);\n\n\treturn false;\n}\n\n/*\n * nmbm_check_bad_phys_block - Check whether a block is marked bad in OOB\n * @ni: NMBM instance structure\n * @ba: block address\n */\nstatic bool nmbm_check_bad_phys_block(struct nmbm_instance *ni, uint32_t ba)\n{\n\tuint64_t addr = ba2addr(ni, ba);\n\n\treturn bmtd._block_isbad(bmtd.mtd, addr);\n}\n\n/*\n * nmbm_mark_phys_bad_block - Mark a block bad\n * @ni: NMBM instance structure\n * @addr: Linear address\n */\nstatic int nmbm_mark_phys_bad_block(struct nmbm_instance *ni, uint32_t ba)\n{\n\tuint64_t addr = ba2addr(ni, ba);\n\n\tnlog_info(ni, \"Block %u [0x%08llx] will be marked bad\\n\", ba, addr);\n\n\treturn bmtd._block_markbad(bmtd.mtd, addr);\n}\n\n/*****************************************************************************/\n/* NMBM related functions */\n/*****************************************************************************/\n\n/*\n * nmbm_check_header - Check whether a NMBM structure is valid\n * @data: pointer to a NMBM structure with a NMBM header at beginning\n * @size: Size of the buffer pointed by @header\n *\n * The size of the NMBM structure may be larger than NMBM header,\n * e.g. block mapping table and block state table.\n */\nstatic bool nmbm_check_header(const void *data, uint32_t size)\n{\n\tconst struct nmbm_header *header = data;\n\tstruct nmbm_header nhdr;\n\tuint32_t new_checksum;\n\n\t/*\n\t * Make sure expected structure size is equal or smaller than\n\t * buffer size.\n\t */\n\tif (header->size > size)\n\t\treturn false;\n\n\tmemcpy(&nhdr, data, sizeof(nhdr));\n\n\tnhdr.checksum = 0;\n\tnew_checksum = nmbm_crc32(0, &nhdr, sizeof(nhdr));\n\tif (header->size > sizeof(nhdr))\n\t\tnew_checksum = nmbm_crc32(new_checksum,\n\t\t\t(const uint8_t *)data + sizeof(nhdr),\n\t\t\theader->size - sizeof(nhdr));\n\n\tif (header->checksum != new_checksum)\n\t\treturn false;\n\n\treturn true;\n}\n\n/*\n * nmbm_update_checksum - Update checksum of a NMBM structure\n * @header: pointer to a NMBM structure with a NMBM header at beginning\n *\n * The size of the NMBM structure must be specified by @header->size\n */\nstatic void nmbm_update_checksum(struct nmbm_header *header)\n{\n\theader->checksum = 0;\n\theader->checksum = nmbm_crc32(0, header, header->size);\n}\n\n/*\n * nmbm_get_spare_block_count - Calculate number of blocks should be reserved\n * @block_count: number of blocks of data\n *\n * Calculate number of blocks should be reserved for data\n */\nstatic uint32_t nmbm_get_spare_block_count(uint32_t block_count)\n{\n\tuint32_t val;\n\n\tval = (block_count + NMBM_SPARE_BLOCK_DIV / 2) / NMBM_SPARE_BLOCK_DIV;\n\tval *= NMBM_SPARE_BLOCK_MULTI;\n\n\tif (val < NMBM_SPARE_BLOCK_MIN)\n\t\tval = NMBM_SPARE_BLOCK_MIN;\n\n\treturn val;\n}\n\n/*\n * nmbm_get_block_state_raw - Get state of a block from raw block state table\n * @block_state: pointer to raw block state table (bitmap)\n * @ba: block address\n */\nstatic uint32_t nmbm_get_block_state_raw(u32 *block_state,\n\t\t\t\t\t uint32_t ba)\n{\n\tuint32_t unit, shift;\n\n\tunit = ba / NMBM_BITMAP_BLOCKS_PER_UNIT;\n\tshift = (ba % NMBM_BITMAP_BLOCKS_PER_UNIT) * NMBM_BITMAP_BITS_PER_BLOCK;\n\n\treturn (block_state[unit] >> shift) & BLOCK_ST_MASK;\n}\n\n/*\n * nmbm_get_block_state - Get state of a block from block state table\n * @ni: NMBM instance structure\n * @ba: block address\n */\nstatic uint32_t nmbm_get_block_state(struct nmbm_instance *ni, uint32_t ba)\n{\n\treturn nmbm_get_block_state_raw(ni->block_state, ba);\n}\n\n/*\n * nmbm_set_block_state - Set state of a block to block state table\n * @ni: NMBM instance structure\n * @ba: block address\n * @state: block state\n *\n * Set state of a block. If the block state changed, ni->block_state_changed\n * will be increased.\n */\nstatic bool nmbm_set_block_state(struct nmbm_instance *ni, uint32_t ba,\n\t\t\t\t uint32_t state)\n{\n\tuint32_t unit, shift, orig;\n\tu32 uv;\n\n\tunit = ba / NMBM_BITMAP_BLOCKS_PER_UNIT;\n\tshift = (ba % NMBM_BITMAP_BLOCKS_PER_UNIT) * NMBM_BITMAP_BITS_PER_BLOCK;\n\n\torig = (ni->block_state[unit] >> shift) & BLOCK_ST_MASK;\n\tstate &= BLOCK_ST_MASK;\n\n\tuv = ni->block_state[unit] & (~(BLOCK_ST_MASK << shift));\n\tuv |= state << shift;\n\tni->block_state[unit] = uv;\n\n\tif (orig != state) {\n\t\tni->block_state_changed++;\n\t\treturn true;\n\t}\n\n\treturn false;\n}\n\n/*\n * nmbm_block_walk_asc - Skip specified number of good blocks, ascending addr.\n * @ni: NMBM instance structure\n * @ba: start physical block address\n * @nba: return physical block address after walk\n * @count: number of good blocks to be skipped\n * @limit: highest block address allowed for walking\n *\n * Start from @ba, skipping any bad blocks, counting @count good blocks, and\n * return the next good block address.\n *\n * If no enough good blocks counted while @limit reached, false will be returned.\n *\n * If @count == 0, nearest good block address will be returned.\n * @limit is not counted in walking.\n */\nstatic bool nmbm_block_walk_asc(struct nmbm_instance *ni, uint32_t ba,\n\t\t\t\tuint32_t *nba, uint32_t count,\n\t\t\t\tuint32_t limit)\n{\n\tint32_t nblock = count;\n\n\tif (limit >= ni->block_count)\n\t\tlimit = ni->block_count - 1;\n\n\twhile (ba < limit) {\n\t\tif (nmbm_get_block_state(ni, ba) == BLOCK_ST_GOOD)\n\t\t\tnblock--;\n\n\t\tif (nblock < 0) {\n\t\t\t*nba = ba;\n\t\t\treturn true;\n\t\t}\n\n\t\tba++;\n\t}\n\n\treturn false;\n}\n\n/*\n * nmbm_block_walk_desc - Skip specified number of good blocks, descending addr\n * @ni: NMBM instance structure\n * @ba: start physical block address\n * @nba: return physical block address after walk\n * @count: number of good blocks to be skipped\n * @limit: lowest block address allowed for walking\n *\n * Start from @ba, skipping any bad blocks, counting @count good blocks, and\n * return the next good block address.\n *\n * If no enough good blocks counted while @limit reached, false will be returned.\n *\n * If @count == 0, nearest good block address will be returned.\n * @limit is not counted in walking.\n */\nstatic bool nmbm_block_walk_desc(struct nmbm_instance *ni, uint32_t ba,\n\t\t\t\t uint32_t *nba, uint32_t count, uint32_t limit)\n{\n\tint32_t nblock = count;\n\n\tif (limit >= ni->block_count)\n\t\tlimit = ni->block_count - 1;\n\n\twhile (ba > limit) {\n\t\tif (nmbm_get_block_state(ni, ba) == BLOCK_ST_GOOD)\n\t\t\tnblock--;\n\n\t\tif (nblock < 0) {\n\t\t\t*nba = ba;\n\t\t\treturn true;\n\t\t}\n\n\t\tba--;\n\t}\n\n\treturn false;\n}\n\n/*\n * nmbm_block_walk - Skip specified number of good blocks from curr. block addr\n * @ni: NMBM instance structure\n * @ascending: whether to walk ascending\n * @ba: start physical block address\n * @nba: return physical block address after walk\n * @count: number of good blocks to be skipped\n * @limit: highest/lowest block address allowed for walking\n *\n * Start from @ba, skipping any bad blocks, counting @count good blocks, and\n * return the next good block address.\n *\n * If no enough good blocks counted while @limit reached, false will be returned.\n *\n * If @count == 0, nearest good block address will be returned.\n * @limit can be set to negative if no limit required.\n * @limit is not counted in walking.\n */\nstatic bool nmbm_block_walk(struct nmbm_instance *ni, bool ascending,\n\t\t\t    uint32_t ba, uint32_t *nba, int32_t count,\n\t\t\t    int32_t limit)\n{\n\tif (ascending)\n\t\treturn nmbm_block_walk_asc(ni, ba, nba, count, limit);\n\n\treturn nmbm_block_walk_desc(ni, ba, nba, count, limit);\n}\n\n/*\n * nmbm_scan_badblocks - Scan and record all bad blocks\n * @ni: NMBM instance structure\n *\n * Scan the entire lower NAND chip and record all bad blocks in to block state\n * table.\n */\nstatic void nmbm_scan_badblocks(struct nmbm_instance *ni)\n{\n\tuint32_t ba;\n\n\tfor (ba = 0; ba < ni->block_count; ba++) {\n\t\tif (nmbm_check_bad_phys_block(ni, ba)) {\n\t\t\tnmbm_set_block_state(ni, ba, BLOCK_ST_BAD);\n\t\t\tnlog_info(ni, \"Bad block %u [0x%08llx]\\n\", ba,\n\t\t\t\t ba2addr(ni, ba));\n\t\t}\n\t}\n}\n\n/*\n * nmbm_build_mapping_table - Build initial block mapping table\n * @ni: NMBM instance structure\n *\n * The initial mapping table will be compatible with the stratage of\n * factory production.\n */\nstatic void nmbm_build_mapping_table(struct nmbm_instance *ni)\n{\n\tuint32_t pb, lb;\n\n\tfor (pb = 0, lb = 0; pb < ni->mgmt_start_ba; pb++) {\n\t\tif (nmbm_get_block_state(ni, pb) == BLOCK_ST_BAD)\n\t\t\tcontinue;\n\n\t\t/* Always map to the next good block */\n\t\tni->block_mapping[lb++] = pb;\n\t}\n\n\tni->data_block_count = lb;\n\n\t/* Unusable/Management blocks */\n\tfor (pb = lb; pb < ni->block_count; pb++)\n\t\tni->block_mapping[pb] = -1;\n}\n\n/*\n * nmbm_erase_block_and_check - Erase a block and check its usability\n * @ni: NMBM instance structure\n * @ba: block address to be erased\n *\n * Erase a block anc check its usability\n *\n * Return true if the block is usable, false if erasure failure or the block\n * has too many bitflips.\n */\nstatic bool nmbm_erase_block_and_check(struct nmbm_instance *ni, uint32_t ba)\n{\n\tuint64_t addr, off;\n\tbool success;\n\tint ret;\n\n\tsuccess = nmbm_erase_phys_block(ni, ba2addr(ni, ba));\n\tif (!success)\n\t\treturn false;\n\n\tif (!ni->empty_page_ecc_ok)\n\t\treturn true;\n\n\t/* Check every page to make sure there aren't too many bitflips */\n\n\taddr = ba2addr(ni, ba);\n\n\tfor (off = 0; off < bmtd.blk_size; off += bmtd.pg_size) {\n\t\tret = nmbm_read_phys_page(ni, addr + off, ni->page_cache, NULL);\n\t\tif (ret == -EBADMSG) {\n\t\t\t/*\n\t\t\t * empty_page_ecc_ok means the empty page is\n\t\t\t * still protected by ECC. So reading pages with ECC\n\t\t\t * enabled and -EBADMSG means there are too many\n\t\t\t * bitflips that can't be recovered, and the block\n\t\t\t * containing the page should be marked bad.\n\t\t\t */\n\t\t\tnlog_err(ni,\n\t\t\t\t \"Too many bitflips in empty page at 0x%llx\\n\",\n\t\t\t\t addr + off);\n\t\t\treturn false;\n\t\t}\n\t}\n\n\treturn true;\n}\n\n/*\n * nmbm_erase_range - Erase a range of blocks\n * @ni: NMBM instance structure\n * @ba: block address where the erasure will start\n * @limit: top block address allowed for erasure\n *\n * Erase blocks within the specific range. Newly-found bad blocks will be\n * marked.\n *\n * @limit is not counted into the allowed erasure address.\n */\nstatic void nmbm_erase_range(struct nmbm_instance *ni, uint32_t ba,\n\t\t\t     uint32_t limit)\n{\n\tbool success;\n\n\twhile (ba < limit) {\n\t\tif (nmbm_get_block_state(ni, ba) != BLOCK_ST_GOOD)\n\t\t\tgoto next_block;\n\n\t\t/* Insurance to detect unexpected bad block marked by user */\n\t\tif (nmbm_check_bad_phys_block(ni, ba)) {\n\t\t\tnmbm_set_block_state(ni, ba, BLOCK_ST_BAD);\n\t\t\tgoto next_block;\n\t\t}\n\n\t\tsuccess = nmbm_erase_block_and_check(ni, ba);\n\t\tif (success)\n\t\t\tgoto next_block;\n\n\t\tnmbm_mark_phys_bad_block(ni, ba);\n\t\tnmbm_set_block_state(ni, ba, BLOCK_ST_BAD);\n\n\tnext_block:\n\t\tba++;\n\t}\n}\n\n/*\n * nmbm_write_repeated_data - Write critical data to a block with retry\n * @ni: NMBM instance structure\n * @ba: block address where the data will be written to\n * @data: the data to be written\n * @size: size of the data\n *\n * Write data to every page of the block. Success only if all pages within\n * this block have been successfully written.\n *\n * Make sure data size is not bigger than one page.\n *\n * This function will write and verify every page for at most\n * NMBM_TRY_COUNT times.\n */\nstatic bool nmbm_write_repeated_data(struct nmbm_instance *ni, uint32_t ba,\n\t\t\t\t     const void *data, uint32_t size)\n{\n\tuint64_t addr, off;\n\tbool success;\n\tint ret;\n\n\tif (size > bmtd.pg_size)\n\t\treturn false;\n\n\taddr = ba2addr(ni, ba);\n\n\tfor (off = 0; off < bmtd.blk_size; off += bmtd.pg_size) {\n\t\t/* Prepare page data. fill 0xff to unused region */\n\t\tmemcpy(ni->page_cache, data, size);\n\t\tmemset(ni->page_cache + size, 0xff, ni->rawpage_size - size);\n\n\t\tsuccess = nmbm_write_phys_page(ni, addr + off, ni->page_cache, NULL);\n\t\tif (!success)\n\t\t\treturn false;\n\n\t\t/* Verify the data just written. ECC error indicates failure */\n\t\tret = nmbm_read_phys_page(ni, addr + off, ni->page_cache, NULL);\n\t\tif (ret < 0)\n\t\t\treturn false;\n\n\t\tif (memcmp(ni->page_cache, data, size))\n\t\t\treturn false;\n\t}\n\n\treturn true;\n}\n\n/*\n * nmbm_write_signature - Write signature to NAND chip\n * @ni: NMBM instance structure\n * @limit: top block address allowed for writing\n * @signature: the signature to be written\n * @signature_ba: the actual block address where signature is written to\n *\n * Write signature within a specific range, from chip bottom to limit.\n * At most one block will be written.\n *\n * @limit is not counted into the allowed write address.\n */\nstatic bool nmbm_write_signature(struct nmbm_instance *ni, uint32_t limit,\n\t\t\t\t const struct nmbm_signature *signature,\n\t\t\t\t uint32_t *signature_ba)\n{\n\tuint32_t ba = ni->block_count - 1;\n\tbool success;\n\n\twhile (ba > limit) {\n\t\tif (nmbm_get_block_state(ni, ba) != BLOCK_ST_GOOD)\n\t\t\tgoto next_block;\n\n\t\t/* Insurance to detect unexpected bad block marked by user */\n\t\tif (nmbm_check_bad_phys_block(ni, ba)) {\n\t\t\tnmbm_set_block_state(ni, ba, BLOCK_ST_BAD);\n\t\t\tgoto next_block;\n\t\t}\n\n\t\tsuccess = nmbm_erase_block_and_check(ni, ba);\n\t\tif (!success)\n\t\t\tgoto skip_bad_block;\n\n\t\tsuccess = nmbm_write_repeated_data(ni, ba, signature,\n\t\t\t\t\t\t   sizeof(*signature));\n\t\tif (success) {\n\t\t\t*signature_ba = ba;\n\t\t\treturn true;\n\t\t}\n\n\tskip_bad_block:\n\t\tnmbm_mark_phys_bad_block(ni, ba);\n\t\tnmbm_set_block_state(ni, ba, BLOCK_ST_BAD);\n\n\tnext_block:\n\t\tba--;\n\t};\n\n\treturn false;\n}\n\n/*\n * nmbn_read_data - Read data\n * @ni: NMBM instance structure\n * @addr: linear address where the data will be read from\n * @data: the data to be read\n * @size: the size of data\n *\n * Read data range.\n * Every page will be tried for at most NMBM_TRY_COUNT times.\n *\n * Return 0 for success, positive value for corrected bitflip count,\n * -EBADMSG for ecc error, other negative values for other errors\n */\nstatic int nmbn_read_data(struct nmbm_instance *ni, uint64_t addr, void *data,\n\t\t\t  uint32_t size)\n{\n\tuint64_t off = addr;\n\tuint8_t *ptr = data;\n\tuint32_t sizeremain = size, chunksize, leading;\n\tint ret;\n\n\twhile (sizeremain) {\n\t\tleading = off & (bmtd.pg_size - 1);\n\t\tchunksize = bmtd.pg_size - leading;\n\t\tif (chunksize > sizeremain)\n\t\t\tchunksize = sizeremain;\n\n\t\tif (chunksize == bmtd.pg_size) {\n\t\t\tret = nmbm_read_phys_page(ni, off - leading, ptr, NULL);\n\t\t\tif (ret < 0)\n\t\t\t\treturn ret;\n\t\t} else {\n\t\t\tret = nmbm_read_phys_page(ni, off - leading,\n\t\t\t\t\t\t  ni->page_cache, NULL);\n\t\t\tif (ret < 0)\n\t\t\t\treturn ret;\n\n\t\t\tmemcpy(ptr, ni->page_cache + leading, chunksize);\n\t\t}\n\n\t\toff += chunksize;\n\t\tptr += chunksize;\n\t\tsizeremain -= chunksize;\n\t}\n\n\treturn 0;\n}\n\n/*\n * nmbn_write_verify_data - Write data with validation\n * @ni: NMBM instance structure\n * @addr: linear address where the data will be written to\n * @data: the data to be written\n * @size: the size of data\n *\n * Write data and verify.\n * Every page will be tried for at most NMBM_TRY_COUNT times.\n */\nstatic bool nmbn_write_verify_data(struct nmbm_instance *ni, uint64_t addr,\n\t\t\t\t   const void *data, uint32_t size)\n{\n\tuint64_t off = addr;\n\tconst uint8_t *ptr = data;\n\tuint32_t sizeremain = size, chunksize, leading;\n\tbool success;\n\tint ret;\n\n\twhile (sizeremain) {\n\t\tleading = off & (bmtd.pg_size - 1);\n\t\tchunksize = bmtd.pg_size - leading;\n\t\tif (chunksize > sizeremain)\n\t\t\tchunksize = sizeremain;\n\n\t\t/* Prepare page data. fill 0xff to unused region */\n\t\tmemset(ni->page_cache, 0xff, ni->rawpage_size);\n\t\tmemcpy(ni->page_cache + leading, ptr, chunksize);\n\n\t\tsuccess = nmbm_write_phys_page(ni, off - leading,\n\t\t\t\t\t       ni->page_cache, NULL);\n\t\tif (!success)\n\t\t\treturn false;\n\n\t\t/* Verify the data just written. ECC error indicates failure */\n\t\tret = nmbm_read_phys_page(ni, off - leading, ni->page_cache, NULL);\n\t\tif (ret < 0)\n\t\t\treturn false;\n\n\t\tif (memcmp(ni->page_cache + leading, ptr, chunksize))\n\t\t\treturn false;\n\n\t\toff += chunksize;\n\t\tptr += chunksize;\n\t\tsizeremain -= chunksize;\n\t}\n\n\treturn true;\n}\n\n/*\n * nmbm_write_mgmt_range - Write management data into NAND within a range\n * @ni: NMBM instance structure\n * @addr: preferred start block address for writing\n * @limit: highest block address allowed for writing\n * @data: the data to be written\n * @size: the size of data\n * @actual_start_ba: actual start block address of data\n * @actual_end_ba: block address after the end of data\n *\n * @limit is not counted into the allowed write address.\n */\nstatic bool nmbm_write_mgmt_range(struct nmbm_instance *ni, uint32_t ba,\n\t\t\t\t  uint32_t limit, const void *data,\n\t\t\t\t  uint32_t size, uint32_t *actual_start_ba,\n\t\t\t\t  uint32_t *actual_end_ba)\n{\n\tconst uint8_t *ptr = data;\n\tuint32_t sizeremain = size, chunksize;\n\tbool success;\n\n\twhile (sizeremain && ba < limit) {\n\t\tchunksize = sizeremain;\n\t\tif (chunksize > bmtd.blk_size)\n\t\t\tchunksize = bmtd.blk_size;\n\n\t\tif (nmbm_get_block_state(ni, ba) != BLOCK_ST_GOOD)\n\t\t\tgoto next_block;\n\n\t\t/* Insurance to detect unexpected bad block marked by user */\n\t\tif (nmbm_check_bad_phys_block(ni, ba)) {\n\t\t\tnmbm_set_block_state(ni, ba, BLOCK_ST_BAD);\n\t\t\tgoto next_block;\n\t\t}\n\n\t\tsuccess = nmbm_erase_block_and_check(ni, ba);\n\t\tif (!success)\n\t\t\tgoto skip_bad_block;\n\n\t\tsuccess = nmbn_write_verify_data(ni, ba2addr(ni, ba), ptr,\n\t\t\t\t\t\t chunksize);\n\t\tif (!success)\n\t\t\tgoto skip_bad_block;\n\n\t\tif (sizeremain == size)\n\t\t\t*actual_start_ba = ba;\n\n\t\tptr += chunksize;\n\t\tsizeremain -= chunksize;\n\n\t\tgoto next_block;\n\n\tskip_bad_block:\n\t\tnmbm_mark_phys_bad_block(ni, ba);\n\t\tnmbm_set_block_state(ni, ba, BLOCK_ST_BAD);\n\n\tnext_block:\n\t\tba++;\n\t}\n\n\tif (sizeremain)\n\t\treturn false;\n\n\t*actual_end_ba = ba;\n\n\treturn true;\n}\n\n/*\n * nmbm_generate_info_table_cache - Generate info table cache data\n * @ni: NMBM instance structure\n *\n * Generate info table cache data to be written into flash.\n */\nstatic bool nmbm_generate_info_table_cache(struct nmbm_instance *ni)\n{\n\tbool changed = false;\n\n\tmemset(ni->info_table_cache, 0xff, ni->info_table_size);\n\n\tmemcpy(ni->info_table_cache + ni->info_table.state_table_off,\n\t       ni->block_state, ni->state_table_size);\n\n\tmemcpy(ni->info_table_cache + ni->info_table.mapping_table_off,\n\t\tni->block_mapping, ni->mapping_table_size);\n\n\tni->info_table.header.magic = NMBM_MAGIC_INFO_TABLE;\n\tni->info_table.header.version = NMBM_VER;\n\tni->info_table.header.size = ni->info_table_size;\n\n\tif (ni->block_state_changed || ni->block_mapping_changed) {\n\t\tni->info_table.write_count++;\n\t\tchanged = true;\n\t}\n\n\tmemcpy(ni->info_table_cache, &ni->info_table, sizeof(ni->info_table));\n\n\tnmbm_update_checksum((struct nmbm_header *)ni->info_table_cache);\n\n\treturn changed;\n}\n\n/*\n * nmbm_write_info_table - Write info table into NAND within a range\n * @ni: NMBM instance structure\n * @ba: preferred start block address for writing\n * @limit: highest block address allowed for writing\n * @actual_start_ba: actual start block address of info table\n * @actual_end_ba: block address after the end of info table\n *\n * @limit is counted into the allowed write address.\n */\nstatic bool nmbm_write_info_table(struct nmbm_instance *ni, uint32_t ba,\n\t\t\t\t  uint32_t limit, uint32_t *actual_start_ba,\n\t\t\t\t  uint32_t *actual_end_ba)\n{\n\treturn nmbm_write_mgmt_range(ni, ba, limit, ni->info_table_cache,\n\t\t\t\t     ni->info_table_size, actual_start_ba,\n\t\t\t\t     actual_end_ba);\n}\n\n/*\n * nmbm_mark_tables_clean - Mark info table `clean'\n * @ni: NMBM instance structure\n */\nstatic void nmbm_mark_tables_clean(struct nmbm_instance *ni)\n{\n\tni->block_state_changed = 0;\n\tni->block_mapping_changed = 0;\n}\n\n/*\n * nmbm_try_reserve_blocks - Reserve blocks with compromisation\n * @ni: NMBM instance structure\n * @ba: start physical block address\n * @nba: return physical block address after reservation\n * @count: number of good blocks to be skipped\n * @min_count: minimum number of good blocks to be skipped\n * @limit: highest/lowest block address allowed for walking\n *\n * Reserve specific blocks. If failed, try to reserve as many as possible.\n */\nstatic bool nmbm_try_reserve_blocks(struct nmbm_instance *ni, uint32_t ba,\n\t\t\t\t    uint32_t *nba, uint32_t count,\n\t\t\t\t    int32_t min_count, int32_t limit)\n{\n\tint32_t nblocks = count;\n\tbool success;\n\n\twhile (nblocks >= min_count) {\n\t\tsuccess = nmbm_block_walk(ni, true, ba, nba, nblocks, limit);\n\t\tif (success)\n\t\t\treturn true;\n\n\t\tnblocks--;\n\t}\n\n\treturn false;\n}\n\n/*\n * nmbm_rebuild_info_table - Build main & backup info table from scratch\n * @ni: NMBM instance structure\n * @allow_no_gap: allow no spare blocks between two tables\n */\nstatic bool nmbm_rebuild_info_table(struct nmbm_instance *ni)\n{\n\tuint32_t table_start_ba, table_end_ba, next_start_ba;\n\tuint32_t main_table_end_ba;\n\tbool success;\n\n\t/* Set initial value */\n\tni->main_table_ba = 0;\n\tni->backup_table_ba = 0;\n\tni->mapping_blocks_ba = ni->mapping_blocks_top_ba;\n\n\t/* Write main table */\n\tsuccess = nmbm_write_info_table(ni, ni->mgmt_start_ba,\n\t\t\t\t\tni->mapping_blocks_top_ba,\n\t\t\t\t\t&table_start_ba, &table_end_ba);\n\tif (!success) {\n\t\t/* Failed to write main table, data will be lost */\n\t\tnlog_err(ni, \"Unable to write at least one info table!\\n\");\n\t\tnlog_err(ni, \"Please save your data before power off!\\n\");\n\t\tni->protected = 1;\n\t\treturn false;\n\t}\n\n\t/* Main info table is successfully written, record its offset */\n\tni->main_table_ba = table_start_ba;\n\tmain_table_end_ba = table_end_ba;\n\n\t/* Adjust mapping_blocks_ba */\n\tni->mapping_blocks_ba = table_end_ba;\n\n\tnmbm_mark_tables_clean(ni);\n\n\tnlog_table_creation(ni, true, table_start_ba, table_end_ba);\n\n\t/* Reserve spare blocks for main info table. */\n\tsuccess = nmbm_try_reserve_blocks(ni, table_end_ba,\n\t\t\t\t\t  &next_start_ba,\n\t\t\t\t\t  ni->info_table_spare_blocks, 0,\n\t\t\t\t\t  ni->mapping_blocks_top_ba -\n\t\t\t\t\t  size2blk(ni, ni->info_table_size));\n\tif (!success) {\n\t\t/* There is no spare block. */\n\t\tnlog_debug(ni, \"No room for backup info table\\n\");\n\t\treturn true;\n\t}\n\n\t/* Write backup info table. */\n\tsuccess = nmbm_write_info_table(ni, next_start_ba,\n\t\t\t\t\tni->mapping_blocks_top_ba,\n\t\t\t\t\t&table_start_ba, &table_end_ba);\n\tif (!success) {\n\t\t/* There is no enough blocks for backup table. */\n\t\tnlog_debug(ni, \"No room for backup info table\\n\");\n\t\treturn true;\n\t}\n\n\t/* Backup table is successfully written, record its offset */\n\tni->backup_table_ba = table_start_ba;\n\n\t/* Adjust mapping_blocks_off */\n\tni->mapping_blocks_ba = table_end_ba;\n\n\t/* Erase spare blocks of main table to clean possible interference data */\n\tnmbm_erase_range(ni, main_table_end_ba, ni->backup_table_ba);\n\n\tnlog_table_creation(ni, false, table_start_ba, table_end_ba);\n\n\treturn true;\n}\n\n/*\n * nmbm_rescue_single_info_table - Rescue when there is only one info table\n * @ni: NMBM instance structure\n *\n * This function is called when there is only one info table exists.\n * This function may fail if we can't write new info table\n */\nstatic bool nmbm_rescue_single_info_table(struct nmbm_instance *ni)\n{\n\tuint32_t table_start_ba, table_end_ba, write_ba;\n\tbool success;\n\n\t/* Try to write new info table in front of existing table */\n\tsuccess = nmbm_write_info_table(ni, ni->mgmt_start_ba,\n\t\t\t\t\tni->main_table_ba,\n\t\t\t\t\t&table_start_ba,\n\t\t\t\t\t&table_end_ba);\n\tif (success) {\n\t\t/*\n\t\t * New table becomes the main table, existing table becomes\n\t\t * the backup table.\n\t\t */\n\t\tni->backup_table_ba = ni->main_table_ba;\n\t\tni->main_table_ba = table_start_ba;\n\n\t\tnmbm_mark_tables_clean(ni);\n\n\t\t/* Erase spare blocks of main table to clean possible interference data */\n\t\tnmbm_erase_range(ni, table_end_ba, ni->backup_table_ba);\n\n\t\tnlog_table_creation(ni, true, table_start_ba, table_end_ba);\n\n\t\treturn true;\n\t}\n\n\t/* Try to reserve spare blocks for existing table */\n\tsuccess = nmbm_try_reserve_blocks(ni, ni->mapping_blocks_ba, &write_ba,\n\t\t\t\t\t  ni->info_table_spare_blocks, 0,\n\t\t\t\t\t  ni->mapping_blocks_top_ba -\n\t\t\t\t\t  size2blk(ni, ni->info_table_size));\n\tif (!success) {\n\t\tnlog_warn(ni, \"Failed to rescue single info table\\n\");\n\t\treturn false;\n\t}\n\n\t/* Try to write new info table next to the existing table */\n\twhile (write_ba >= ni->mapping_blocks_ba) {\n\t\tsuccess = nmbm_write_info_table(ni, write_ba,\n\t\t\t\t\t\tni->mapping_blocks_top_ba,\n\t\t\t\t\t\t&table_start_ba,\n\t\t\t\t\t\t&table_end_ba);\n\t\tif (success)\n\t\t\tbreak;\n\n\t\twrite_ba--;\n\t}\n\n\tif (success) {\n\t\t/* Erase spare blocks of main table to clean possible interference data */\n\t\tnmbm_erase_range(ni, ni->mapping_blocks_ba, table_start_ba);\n\n\t\t/* New table becomes the backup table */\n\t\tni->backup_table_ba = table_start_ba;\n\t\tni->mapping_blocks_ba = table_end_ba;\n\n\t\tnmbm_mark_tables_clean(ni);\n\n\t\tnlog_table_creation(ni, false, table_start_ba, table_end_ba);\n\n\t\treturn true;\n\t}\n\n\tnlog_warn(ni, \"Failed to rescue single info table\\n\");\n\treturn false;\n}\n\n/*\n * nmbm_update_single_info_table - Update specific one info table\n * @ni: NMBM instance structure\n */\nstatic bool nmbm_update_single_info_table(struct nmbm_instance *ni,\n\t\t\t\t\t  bool update_main_table)\n{\n\tuint32_t write_start_ba, write_limit, table_start_ba, table_end_ba;\n\tbool success;\n\n\t/* Determine the write range */\n\tif (update_main_table) {\n\t\twrite_start_ba = ni->main_table_ba;\n\t\twrite_limit = ni->backup_table_ba;\n\t} else {\n\t\twrite_start_ba = ni->backup_table_ba;\n\t\twrite_limit = ni->mapping_blocks_top_ba;\n\t}\n\n\tsuccess = nmbm_write_info_table(ni, write_start_ba, write_limit,\n\t\t\t\t\t&table_start_ba, &table_end_ba);\n\tif (success) {\n\t\tif (update_main_table) {\n\t\t\tni->main_table_ba = table_start_ba;\n\t\t} else {\n\t\t\tni->backup_table_ba = table_start_ba;\n\t\t\tni->mapping_blocks_ba = table_end_ba;\n\t\t}\n\n\t\tnmbm_mark_tables_clean(ni);\n\n\t\tnlog_table_update(ni, update_main_table, table_start_ba,\n\t\t\t\t table_end_ba);\n\n\t\treturn true;\n\t}\n\n\tif (update_main_table) {\n\t\t/*\n\t\t * If failed to update main table, make backup table the new\n\t\t * main table, and call nmbm_rescue_single_info_table()\n\t\t */\n\t\tnlog_warn(ni, \"Unable to update %s info table\\n\",\n\t\t\t update_main_table ? \"Main\" : \"Backup\");\n\n\t\tni->main_table_ba = ni->backup_table_ba;\n\t\tni->backup_table_ba = 0;\n\t\treturn nmbm_rescue_single_info_table(ni);\n\t}\n\n\t/* Only one table left */\n\tni->mapping_blocks_ba = ni->backup_table_ba;\n\tni->backup_table_ba = 0;\n\n\treturn false;\n}\n\n/*\n * nmbm_rescue_main_info_table - Rescue when failed to write main info table\n * @ni: NMBM instance structure\n *\n * This function is called when main info table failed to be written, and\n *    backup info table exists.\n */\nstatic bool nmbm_rescue_main_info_table(struct nmbm_instance *ni)\n{\n\tuint32_t tmp_table_start_ba, tmp_table_end_ba, main_table_start_ba;\n\tuint32_t main_table_end_ba, write_ba;\n\tuint32_t info_table_erasesize = size2blk(ni, ni->info_table_size);\n\tbool success;\n\n\t/* Try to reserve spare blocks for existing backup info table */\n\tsuccess = nmbm_try_reserve_blocks(ni, ni->mapping_blocks_ba, &write_ba,\n\t\t\t\t\t  ni->info_table_spare_blocks, 0,\n\t\t\t\t\t  ni->mapping_blocks_top_ba -\n\t\t\t\t\t  info_table_erasesize);\n\tif (!success) {\n\t\t/* There is no spare block. Backup info table becomes the main table. */\n\t\tnlog_err(ni, \"No room for temporary info table\\n\");\n\t\tni->main_table_ba = ni->backup_table_ba;\n\t\tni->backup_table_ba = 0;\n\t\treturn true;\n\t}\n\n\t/* Try to write temporary info table into spare unmapped blocks */\n\twhile (write_ba >= ni->mapping_blocks_ba) {\n\t\tsuccess = nmbm_write_info_table(ni, write_ba,\n\t\t\t\t\t\tni->mapping_blocks_top_ba,\n\t\t\t\t\t\t&tmp_table_start_ba,\n\t\t\t\t\t\t&tmp_table_end_ba);\n\t\tif (success)\n\t\t\tbreak;\n\n\t\twrite_ba--;\n\t}\n\n\tif (!success) {\n\t\t/* Backup info table becomes the main table */\n\t\tnlog_err(ni, \"Failed to update main info table\\n\");\n\t\tni->main_table_ba = ni->backup_table_ba;\n\t\tni->backup_table_ba = 0;\n\t\treturn true;\n\t}\n\n\t/* Adjust mapping_blocks_off */\n\tni->mapping_blocks_ba = tmp_table_end_ba;\n\n\t/*\n\t * Now write main info table at the beginning of management area.\n\t * This operation will generally destroy the original backup info\n\t * table.\n\t */\n\tsuccess = nmbm_write_info_table(ni, ni->mgmt_start_ba,\n\t\t\t\t\ttmp_table_start_ba,\n\t\t\t\t\t&main_table_start_ba,\n\t\t\t\t\t&main_table_end_ba);\n\tif (!success) {\n\t\t/* Temporary info table becomes the main table */\n\t\tni->main_table_ba = tmp_table_start_ba;\n\t\tni->backup_table_ba = 0;\n\n\t\tnmbm_mark_tables_clean(ni);\n\n\t\tnlog_err(ni, \"Failed to update main info table\\n\");\n\n\t\treturn true;\n\t}\n\n\t/* Main info table has been successfully written, record its offset */\n\tni->main_table_ba = main_table_start_ba;\n\n\tnmbm_mark_tables_clean(ni);\n\n\tnlog_table_creation(ni, true, main_table_start_ba, main_table_end_ba);\n\n\t/*\n\t * Temporary info table becomes the new backup info table if it's\n\t * not overwritten.\n\t */\n\tif (main_table_end_ba <= tmp_table_start_ba) {\n\t\tni->backup_table_ba = tmp_table_start_ba;\n\n\t\tnlog_table_creation(ni, false, tmp_table_start_ba,\n\t\t\t\t   tmp_table_end_ba);\n\n\t\treturn true;\n\t}\n\n\t/* Adjust mapping_blocks_off */\n\tni->mapping_blocks_ba = main_table_end_ba;\n\n\t/* Try to reserve spare blocks for new main info table */\n\tsuccess = nmbm_try_reserve_blocks(ni, main_table_end_ba, &write_ba,\n\t\t\t\t\t  ni->info_table_spare_blocks, 0,\n\t\t\t\t\t  ni->mapping_blocks_top_ba -\n\t\t\t\t\t  info_table_erasesize);\n\tif (!success) {\n\t\t/* There is no spare block. Only main table exists. */\n\t\tnlog_err(ni, \"No room for backup info table\\n\");\n\t\tni->backup_table_ba = 0;\n\t\treturn true;\n\t}\n\n\t/* Write new backup info table. */\n\twhile (write_ba >= main_table_end_ba) {\n\t\tsuccess = nmbm_write_info_table(ni, write_ba,\n\t\t\t\t\t\tni->mapping_blocks_top_ba,\n\t\t\t\t\t\t&tmp_table_start_ba,\n\t\t\t\t\t\t&tmp_table_end_ba);\n\t\tif (success)\n\t\t\tbreak;\n\n\t\twrite_ba--;\n\t}\n\n\tif (!success) {\n\t\tnlog_err(ni, \"No room for backup info table\\n\");\n\t\tni->backup_table_ba = 0;\n\t\treturn true;\n\t}\n\n\t/* Backup info table has been successfully written, record its offset */\n\tni->backup_table_ba = tmp_table_start_ba;\n\n\t/* Adjust mapping_blocks_off */\n\tni->mapping_blocks_ba = tmp_table_end_ba;\n\n\t/* Erase spare blocks of main table to clean possible interference data */\n\tnmbm_erase_range(ni, main_table_end_ba, ni->backup_table_ba);\n\n\tnlog_table_creation(ni, false, tmp_table_start_ba, tmp_table_end_ba);\n\n\treturn true;\n}\n\n/*\n * nmbm_update_info_table_once - Update info table once\n * @ni: NMBM instance structure\n * @force: force update\n *\n * Update both main and backup info table. Return true if at least one info\n * table has been successfully written.\n * This function only try to update info table once regard less of the result.\n */\nstatic bool nmbm_update_info_table_once(struct nmbm_instance *ni, bool force)\n{\n\tuint32_t table_start_ba, table_end_ba;\n\tuint32_t main_table_limit;\n\tbool success;\n\n\t/* Do nothing if there is no change */\n\tif (!nmbm_generate_info_table_cache(ni) && !force)\n\t\treturn true;\n\n\t/* Check whether both two tables exist */\n\tif (!ni->backup_table_ba) {\n\t\tmain_table_limit = ni->mapping_blocks_top_ba;\n\t\tgoto write_main_table;\n\t}\n\n\t/*\n\t * Write backup info table in its current range.\n\t * Note that limit is set to mapping_blocks_top_off to provide as many\n\t * spare blocks as possible for the backup table. If at last\n\t * unmapped blocks are used by backup table, mapping_blocks_off will\n\t * be adjusted.\n\t */\n\tsuccess = nmbm_write_info_table(ni, ni->backup_table_ba,\n\t\t\t\t\tni->mapping_blocks_top_ba,\n\t\t\t\t\t&table_start_ba, &table_end_ba);\n\tif (!success) {\n\t\t/*\n\t\t * There is nothing to do if failed to write backup table.\n\t\t * Write the main table now.\n\t\t */\n\t\tnlog_err(ni, \"No room for backup table\\n\");\n\t\tni->mapping_blocks_ba = ni->backup_table_ba;\n\t\tni->backup_table_ba = 0;\n\t\tmain_table_limit = ni->mapping_blocks_top_ba;\n\t\tgoto write_main_table;\n\t}\n\n\t/* Backup table is successfully written, record its offset */\n\tni->backup_table_ba = table_start_ba;\n\n\t/* Adjust mapping_blocks_off */\n\tni->mapping_blocks_ba = table_end_ba;\n\n\tnmbm_mark_tables_clean(ni);\n\n\t/* The normal limit of main table */\n\tmain_table_limit = ni->backup_table_ba;\n\n\tnlog_table_update(ni, false, table_start_ba, table_end_ba);\n\nwrite_main_table:\n\tif (!ni->main_table_ba)\n\t\tgoto rebuild_tables;\n\n\t/* Write main info table in its current range */\n\tsuccess = nmbm_write_info_table(ni, ni->main_table_ba,\n\t\t\t\t\tmain_table_limit, &table_start_ba,\n\t\t\t\t\t&table_end_ba);\n\tif (!success) {\n\t\t/* If failed to write main table, go rescue procedure */\n\t\tif (!ni->backup_table_ba)\n\t\t\tgoto rebuild_tables;\n\n\t\treturn nmbm_rescue_main_info_table(ni);\n\t}\n\n\t/* Main info table is successfully written, record its offset */\n\tni->main_table_ba = table_start_ba;\n\n\t/* Adjust mapping_blocks_off */\n\tif (!ni->backup_table_ba)\n\t\tni->mapping_blocks_ba = table_end_ba;\n\n\tnmbm_mark_tables_clean(ni);\n\n\tnlog_table_update(ni, true, table_start_ba, table_end_ba);\n\n\treturn true;\n\nrebuild_tables:\n\treturn nmbm_rebuild_info_table(ni);\n}\n\n/*\n * nmbm_update_info_table - Update info table\n * @ni: NMBM instance structure\n *\n * Update both main and backup info table. Return true if at least one table\n * has been successfully written.\n * This function will try to update info table repeatedly until no new bad\n * block found during updating.\n */\nstatic bool nmbm_update_info_table(struct nmbm_instance *ni)\n{\n\tbool success;\n\n\tif (ni->protected)\n\t\treturn true;\n\n\twhile (ni->block_state_changed || ni->block_mapping_changed) {\n\t\tsuccess = nmbm_update_info_table_once(ni, false);\n\t\tif (!success) {\n\t\t\tnlog_err(ni, \"Failed to update info table\\n\");\n\t\t\treturn false;\n\t\t}\n\t}\n\n\treturn true;\n}\n\n/*\n * nmbm_map_block - Map a bad block to a unused spare block\n * @ni: NMBM instance structure\n * @lb: logic block addr to map\n */\nstatic bool nmbm_map_block(struct nmbm_instance *ni, uint32_t lb)\n{\n\tuint32_t pb;\n\tbool success;\n\n\tif (ni->mapping_blocks_ba == ni->mapping_blocks_top_ba) {\n\t\tnlog_warn(ni, \"No spare unmapped blocks.\\n\");\n\t\treturn false;\n\t}\n\n\tsuccess = nmbm_block_walk(ni, false, ni->mapping_blocks_top_ba, &pb, 0,\n\t\t\t\t  ni->mapping_blocks_ba);\n\tif (!success) {\n\t\tnlog_warn(ni, \"No spare unmapped blocks.\\n\");\n\t\tnmbm_update_info_table(ni);\n\t\tni->mapping_blocks_top_ba = ni->mapping_blocks_ba;\n\t\treturn false;\n\t}\n\n\tni->block_mapping[lb] = pb;\n\tni->mapping_blocks_top_ba--;\n\tni->block_mapping_changed++;\n\n\tnlog_info(ni, \"Logic block %u mapped to physical block %u\\n\", lb, pb);\n\n\treturn true;\n}\n\n/*\n * nmbm_create_info_table - Create info table(s)\n * @ni: NMBM instance structure\n *\n * This function assumes that the chip has no existing info table(s)\n */\nstatic bool nmbm_create_info_table(struct nmbm_instance *ni)\n{\n\tuint32_t lb;\n\tbool success;\n\n\t/* Set initial mapping_blocks_top_off  */\n\tsuccess = nmbm_block_walk(ni, false, ni->signature_ba,\n\t\t\t\t  &ni->mapping_blocks_top_ba, 1,\n\t\t\t\t  ni->mgmt_start_ba);\n\tif (!success) {\n\t\tnlog_err(ni, \"No room for spare blocks\\n\");\n\t\treturn false;\n\t}\n\n\t/* Generate info table cache */\n\tnmbm_generate_info_table_cache(ni);\n\n\t/* Write info table */\n\tsuccess = nmbm_rebuild_info_table(ni);\n\tif (!success) {\n\t\tnlog_err(ni, \"Failed to build info tables\\n\");\n\t\treturn false;\n\t}\n\n\t/* Remap bad block(s) at end of data area */\n\tfor (lb = ni->data_block_count; lb < ni->mgmt_start_ba; lb++) {\n\t\tsuccess = nmbm_map_block(ni, lb);\n\t\tif (!success)\n\t\t\tbreak;\n\n\t\tni->data_block_count++;\n\t}\n\n\t/* If state table and/or mapping table changed, update info table. */\n\tsuccess = nmbm_update_info_table(ni);\n\tif (!success)\n\t\treturn false;\n\n\treturn true;\n}\n\n/*\n * nmbm_create_new - Create NMBM on a new chip\n * @ni: NMBM instance structure\n */\nstatic bool nmbm_create_new(struct nmbm_instance *ni)\n{\n\tbool success;\n\n\t/* Determine the boundary of management blocks */\n\tni->mgmt_start_ba = ni->block_count * (NMBM_MGMT_DIV - ni->max_ratio) / NMBM_MGMT_DIV;\n\n\tif (ni->max_reserved_blocks && ni->block_count - ni->mgmt_start_ba > ni->max_reserved_blocks)\n\t\tni->mgmt_start_ba = ni->block_count - ni->max_reserved_blocks;\n\n\tnlog_info(ni, \"NMBM management region starts at block %u [0x%08llx]\\n\",\n\t\t  ni->mgmt_start_ba, ba2addr(ni, ni->mgmt_start_ba));\n\n\t/* Fill block state table & mapping table */\n\tnmbm_scan_badblocks(ni);\n\tnmbm_build_mapping_table(ni);\n\n\t/* Write signature */\n\tni->signature.header.magic = NMBM_MAGIC_SIGNATURE;\n\tni->signature.header.version = NMBM_VER;\n\tni->signature.header.size = sizeof(ni->signature);\n\tni->signature.nand_size = bmtd.total_blks << bmtd.blk_shift;\n\tni->signature.block_size = bmtd.blk_size;\n\tni->signature.page_size = bmtd.pg_size;\n\tni->signature.spare_size = bmtd.mtd->oobsize;\n\tni->signature.mgmt_start_pb = ni->mgmt_start_ba;\n\tni->signature.max_try_count = NMBM_TRY_COUNT;\n\tnmbm_update_checksum(&ni->signature.header);\n\n\tsuccess = nmbm_write_signature(ni, ni->mgmt_start_ba,\n\t\t\t\t       &ni->signature, &ni->signature_ba);\n\tif (!success) {\n\t\tnlog_err(ni, \"Failed to write signature to a proper offset\\n\");\n\t\treturn false;\n\t}\n\n\tnlog_info(ni, \"Signature has been written to block %u [0x%08llx]\\n\",\n\t\t ni->signature_ba, ba2addr(ni, ni->signature_ba));\n\n\t/* Write info table(s) */\n\tsuccess = nmbm_create_info_table(ni);\n\tif (success) {\n\t\tnlog_info(ni, \"NMBM has been successfully created\\n\");\n\t\treturn true;\n\t}\n\n\treturn false;\n}\n\n/*\n * nmbm_check_info_table_header - Check if a info table header is valid\n * @ni: NMBM instance structure\n * @data: pointer to the info table header\n */\nstatic bool nmbm_check_info_table_header(struct nmbm_instance *ni, void *data)\n{\n\tstruct nmbm_info_table_header *ifthdr = data;\n\n\tif (ifthdr->header.magic != NMBM_MAGIC_INFO_TABLE)\n\t\treturn false;\n\n\tif (ifthdr->header.size != ni->info_table_size)\n\t\treturn false;\n\n\tif (ifthdr->mapping_table_off - ifthdr->state_table_off < ni->state_table_size)\n\t\treturn false;\n\n\tif (ni->info_table_size - ifthdr->mapping_table_off < ni->mapping_table_size)\n\t\treturn false;\n\n\treturn true;\n}\n\n/*\n * nmbm_check_info_table - Check if a whole info table is valid\n * @ni: NMBM instance structure\n * @start_ba: start block address of this table\n * @end_ba: end block address of this table\n * @data: pointer to the info table header\n * @mapping_blocks_top_ba: return the block address of top remapped block\n */\nstatic bool nmbm_check_info_table(struct nmbm_instance *ni, uint32_t start_ba,\n\t\t\t\t  uint32_t end_ba, void *data,\n\t\t\t\t  uint32_t *mapping_blocks_top_ba)\n{\n\tstruct nmbm_info_table_header *ifthdr = data;\n\tint32_t *block_mapping = (int32_t *)((uintptr_t)data + ifthdr->mapping_table_off);\n\tu32 *block_state = (u32 *)((uintptr_t)data + ifthdr->state_table_off);\n\tuint32_t minimum_mapping_pb = ni->signature_ba;\n\tuint32_t ba;\n\n\tfor (ba = 0; ba < ni->data_block_count; ba++) {\n\t\tif ((block_mapping[ba] >= ni->data_block_count && block_mapping[ba] < end_ba) ||\n\t\t    block_mapping[ba] == ni->signature_ba)\n\t\t\treturn false;\n\n\t\tif (block_mapping[ba] >= end_ba && block_mapping[ba] < minimum_mapping_pb)\n\t\t\tminimum_mapping_pb = block_mapping[ba];\n\t}\n\n\tfor (ba = start_ba; ba < end_ba; ba++) {\n\t\tif (nmbm_get_block_state(ni, ba) != BLOCK_ST_GOOD)\n\t\t\tcontinue;\n\n\t\tif (nmbm_get_block_state_raw(block_state, ba) != BLOCK_ST_GOOD)\n\t\t\treturn false;\n\t}\n\n\t*mapping_blocks_top_ba = minimum_mapping_pb - 1;\n\n\treturn true;\n}\n\n/*\n * nmbm_try_load_info_table - Try to load info table from a address\n * @ni: NMBM instance structure\n * @ba: start block address of the info table\n * @eba: return the block address after end of the table\n * @write_count: return the write count of this table\n * @mapping_blocks_top_ba: return the block address of top remapped block\n * @table_loaded: used to record whether ni->info_table has valid data\n */\nstatic bool nmbm_try_load_info_table(struct nmbm_instance *ni, uint32_t ba,\n\t\t\t\t     uint32_t *eba, uint32_t *write_count,\n\t\t\t\t     uint32_t *mapping_blocks_top_ba,\n\t\t\t\t     bool table_loaded)\n{\n\tstruct nmbm_info_table_header *ifthdr = (void *)ni->info_table_cache;\n\tuint8_t *off = ni->info_table_cache;\n\tuint32_t limit = ba + size2blk(ni, ni->info_table_size);\n\tuint32_t start_ba = 0, chunksize, sizeremain = ni->info_table_size;\n\tbool success, checkhdr = true;\n\tint ret;\n\n\twhile (sizeremain && ba < limit) {\n\t\tif (nmbm_get_block_state(ni, ba) != BLOCK_ST_GOOD)\n\t\t\tgoto next_block;\n\n\t\tif (nmbm_check_bad_phys_block(ni, ba)) {\n\t\t\tnmbm_set_block_state(ni, ba, BLOCK_ST_BAD);\n\t\t\tgoto next_block;\n\t\t}\n\n\t\tchunksize = sizeremain;\n\t\tif (chunksize > bmtd.blk_size)\n\t\t\tchunksize = bmtd.blk_size;\n\n\t\t/* Assume block with ECC error has no info table data */\n\t\tret = nmbn_read_data(ni, ba2addr(ni, ba), off, chunksize);\n\t\tif (ret < 0)\n\t\t\tgoto skip_bad_block;\n\t\telse if (ret > 0)\n\t\t\treturn false;\n\n\t\tif (checkhdr) {\n\t\t\tsuccess = nmbm_check_info_table_header(ni, off);\n\t\t\tif (!success)\n\t\t\t\treturn false;\n\n\t\t\tstart_ba = ba;\n\t\t\tcheckhdr = false;\n\t\t}\n\n\t\toff += chunksize;\n\t\tsizeremain -= chunksize;\n\n\t\tgoto next_block;\n\n\tskip_bad_block:\n\t\t/* Only mark bad in memory */\n\t\tnmbm_set_block_state(ni, ba, BLOCK_ST_BAD);\n\n\tnext_block:\n\t\tba++;\n\t}\n\n\tif (sizeremain)\n\t\treturn false;\n\n\tsuccess = nmbm_check_header(ni->info_table_cache, ni->info_table_size);\n\tif (!success)\n\t\treturn false;\n\n\t*eba = ba;\n\t*write_count = ifthdr->write_count;\n\n\tsuccess = nmbm_check_info_table(ni, start_ba, ba, ni->info_table_cache,\n\t\t\t\t\tmapping_blocks_top_ba);\n\tif (!success)\n\t\treturn false;\n\n\tif (!table_loaded || ifthdr->write_count > ni->info_table.write_count) {\n\t\tmemcpy(&ni->info_table, ifthdr, sizeof(ni->info_table));\n\t\tmemcpy(ni->block_state,\n\t\t       (uint8_t *)ifthdr + ifthdr->state_table_off,\n\t\t       ni->state_table_size);\n\t\tmemcpy(ni->block_mapping,\n\t\t       (uint8_t *)ifthdr + ifthdr->mapping_table_off,\n\t\t       ni->mapping_table_size);\n\t\tni->info_table.write_count = ifthdr->write_count;\n\t}\n\n\treturn true;\n}\n\n/*\n * nmbm_search_info_table - Search info table from specific address\n * @ni: NMBM instance structure\n * @ba: start block address to search\n * @limit: highest block address allowed for searching\n * @table_start_ba: return the start block address of this table\n * @table_end_ba: return the block address after end of this table\n * @write_count: return the write count of this table\n * @mapping_blocks_top_ba: return the block address of top remapped block\n * @table_loaded: used to record whether ni->info_table has valid data\n */\nstatic bool nmbm_search_info_table(struct nmbm_instance *ni, uint32_t ba,\n\t\t\t\t   uint32_t limit, uint32_t *table_start_ba,\n\t\t\t\t   uint32_t *table_end_ba,\n\t\t\t\t   uint32_t *write_count,\n\t\t\t\t   uint32_t *mapping_blocks_top_ba,\n\t\t\t\t   bool table_loaded)\n{\n\tbool success;\n\n\twhile (ba < limit - size2blk(ni, ni->info_table_size)) {\n\t\tsuccess = nmbm_try_load_info_table(ni, ba, table_end_ba,\n\t\t\t\t\t\t   write_count,\n\t\t\t\t\t\t   mapping_blocks_top_ba,\n\t\t\t\t\t\t   table_loaded);\n\t\tif (success) {\n\t\t\t*table_start_ba = ba;\n\t\t\treturn true;\n\t\t}\n\n\t\tba++;\n\t}\n\n\treturn false;\n}\n\n/*\n * nmbm_load_info_table - Load info table(s) from a chip\n * @ni: NMBM instance structure\n * @ba: start block address to search info table\n * @limit: highest block address allowed for searching\n */\nstatic bool nmbm_load_info_table(struct nmbm_instance *ni, uint32_t ba,\n\t\t\t\t uint32_t limit)\n{\n\tuint32_t main_table_end_ba, backup_table_end_ba, table_end_ba;\n\tuint32_t main_mapping_blocks_top_ba, backup_mapping_blocks_top_ba;\n\tuint32_t main_table_write_count, backup_table_write_count;\n\tuint32_t i;\n\tbool success;\n\n\t/* Set initial value */\n\tni->main_table_ba = 0;\n\tni->backup_table_ba = 0;\n\tni->info_table.write_count = 0;\n\tni->mapping_blocks_top_ba = ni->signature_ba - 1;\n\tni->data_block_count = ni->signature.mgmt_start_pb;\n\n\t/* Find first info table */\n\tsuccess = nmbm_search_info_table(ni, ba, limit, &ni->main_table_ba,\n\t\t&main_table_end_ba, &main_table_write_count,\n\t\t&main_mapping_blocks_top_ba, false);\n\tif (!success) {\n\t\tnlog_warn(ni, \"No valid info table found\\n\");\n\t\treturn false;\n\t}\n\n\ttable_end_ba = main_table_end_ba;\n\n\tnlog_table_found(ni, true, main_table_write_count, ni->main_table_ba,\n\t\t\tmain_table_end_ba);\n\n\t/* Find second info table */\n\tsuccess = nmbm_search_info_table(ni, main_table_end_ba, limit,\n\t\t&ni->backup_table_ba, &backup_table_end_ba,\n\t\t&backup_table_write_count, &backup_mapping_blocks_top_ba, true);\n\tif (!success) {\n\t\tnlog_warn(ni, \"Second info table not found\\n\");\n\t} else {\n\t\ttable_end_ba = backup_table_end_ba;\n\n\t\tnlog_table_found(ni, false, backup_table_write_count,\n\t\t\t\tni->backup_table_ba, backup_table_end_ba);\n\t}\n\n\t/* Pick mapping_blocks_top_ba */\n\tif (!ni->backup_table_ba) {\n\t\tni->mapping_blocks_top_ba= main_mapping_blocks_top_ba;\n\t} else {\n\t\tif (main_table_write_count >= backup_table_write_count)\n\t\t\tni->mapping_blocks_top_ba = main_mapping_blocks_top_ba;\n\t\telse\n\t\t\tni->mapping_blocks_top_ba = backup_mapping_blocks_top_ba;\n\t}\n\n\t/* Set final mapping_blocks_ba */\n\tni->mapping_blocks_ba = table_end_ba;\n\n\t/* Set final data_block_count */\n\tfor (i = ni->signature.mgmt_start_pb; i > 0; i--) {\n\t\tif (ni->block_mapping[i - 1] >= 0) {\n\t\t\tni->data_block_count = i;\n\t\t\tbreak;\n\t\t}\n\t}\n\n\t/* Regenerate the info table cache from the final selected info table */\n\tnmbm_generate_info_table_cache(ni);\n\n\t/*\n\t * If only one table exists, try to write another table.\n\t * If two tables have different write count, try to update info table\n\t */\n\tif (!ni->backup_table_ba) {\n\t\tsuccess = nmbm_rescue_single_info_table(ni);\n\t} else if (main_table_write_count != backup_table_write_count) {\n\t\t/* Mark state & mapping tables changed */\n\t\tni->block_state_changed = 1;\n\t\tni->block_mapping_changed = 1;\n\n\t\tsuccess = nmbm_update_single_info_table(ni,\n\t\t\tmain_table_write_count < backup_table_write_count);\n\t} else {\n\t\tsuccess = true;\n\t}\n\n\t/*\n\t * If there is no spare unmapped blocks, or still only one table\n\t * exists, set the chip to read-only\n\t */\n\tif (ni->mapping_blocks_ba == ni->mapping_blocks_top_ba) {\n\t\tnlog_warn(ni, \"No spare unmapped blocks. Device is now read-only\\n\");\n\t\tni->protected = 1;\n\t} else if (!success) {\n\t\tnlog_warn(ni, \"Only one info table found. Device is now read-only\\n\");\n\t\tni->protected = 1;\n\t}\n\n\treturn true;\n}\n\n/*\n * nmbm_load_existing - Load NMBM from a new chip\n * @ni: NMBM instance structure\n */\nstatic bool nmbm_load_existing(struct nmbm_instance *ni)\n{\n\tbool success;\n\n\t/* Calculate the boundary of management blocks */\n\tni->mgmt_start_ba = ni->signature.mgmt_start_pb;\n\n\tnlog_debug(ni, \"NMBM management region starts at block %u [0x%08llx]\\n\",\n\t\t  ni->mgmt_start_ba, ba2addr(ni, ni->mgmt_start_ba));\n\n\t/* Look for info table(s) */\n\tsuccess = nmbm_load_info_table(ni, ni->mgmt_start_ba,\n\t\tni->signature_ba);\n\tif (success) {\n\t\tnlog_info(ni, \"NMBM has been successfully attached\\n\");\n\t\treturn true;\n\t}\n\n\tif (!ni->force_create) {\n\t\tprintk(\"not creating NMBM table\\n\");\n\t\treturn false;\n\t}\n\n\t/* Fill block state table & mapping table */\n\tnmbm_scan_badblocks(ni);\n\tnmbm_build_mapping_table(ni);\n\n\t/* Write info table(s) */\n\tsuccess = nmbm_create_info_table(ni);\n\tif (success) {\n\t\tnlog_info(ni, \"NMBM has been successfully created\\n\");\n\t\treturn true;\n\t}\n\n\treturn false;\n}\n\n/*\n * nmbm_find_signature - Find signature in the lower NAND chip\n * @ni: NMBM instance structure\n * @signature_ba: used for storing block address of the signature\n * @signature_ba: return the actual block address of signature block\n *\n * Find a valid signature from a specific range in the lower NAND chip,\n * from bottom (highest address) to top (lowest address)\n *\n * Return true if found.\n */\nstatic bool nmbm_find_signature(struct nmbm_instance *ni,\n\t\t\t\tstruct nmbm_signature *signature,\n\t\t\t\tuint32_t *signature_ba)\n{\n\tstruct nmbm_signature sig;\n\tuint64_t off, addr;\n\tuint32_t block_count, ba, limit;\n\tbool success;\n\tint ret;\n\n\t/* Calculate top and bottom block address */\n\tblock_count = bmtd.total_blks;\n\tba = block_count;\n\tlimit = (block_count / NMBM_MGMT_DIV) * (NMBM_MGMT_DIV - ni->max_ratio);\n\tif (ni->max_reserved_blocks && block_count - limit > ni->max_reserved_blocks)\n\t\tlimit = block_count - ni->max_reserved_blocks;\n\n\twhile (ba >= limit) {\n\t\tba--;\n\t\taddr = ba2addr(ni, ba);\n\n\t\tif (nmbm_check_bad_phys_block(ni, ba))\n\t\t\tcontinue;\n\n\t\t/* Check every page.\n\t\t * As long as at leaset one page contains valid signature,\n\t\t * the block is treated as a valid signature block.\n\t\t */\n\t\tfor (off = 0; off < bmtd.blk_size;\n\t\t     off += bmtd.pg_size) {\n\t\t\tret = nmbn_read_data(ni, addr + off, &sig,\n\t\t\t\t\t     sizeof(sig));\n\t\t\tif (ret)\n\t\t\t\tcontinue;\n\n\t\t\t/* Check for header size and checksum */\n\t\t\tsuccess = nmbm_check_header(&sig, sizeof(sig));\n\t\t\tif (!success)\n\t\t\t\tcontinue;\n\n\t\t\t/* Check for header magic */\n\t\t\tif (sig.header.magic == NMBM_MAGIC_SIGNATURE) {\n\t\t\t\t/* Found it */\n\t\t\t\tmemcpy(signature, &sig, sizeof(sig));\n\t\t\t\t*signature_ba = ba;\n\t\t\t\treturn true;\n\t\t\t}\n\t\t}\n\t};\n\n\treturn false;\n}\n\n/*\n * nmbm_calc_structure_size - Calculate the instance structure size\n * @nld: NMBM lower device structure\n */\nstatic size_t nmbm_calc_structure_size(void)\n{\n\tuint32_t state_table_size, mapping_table_size, info_table_size;\n\tuint32_t block_count;\n\n\tblock_count = bmtd.total_blks;\n\n\t/* Calculate info table size */\n\tstate_table_size = ((block_count + NMBM_BITMAP_BLOCKS_PER_UNIT - 1) /\n\t\tNMBM_BITMAP_BLOCKS_PER_UNIT) * NMBM_BITMAP_UNIT_SIZE;\n\tmapping_table_size = block_count * sizeof(int32_t);\n\n\tinfo_table_size = ALIGN(sizeof(struct nmbm_info_table_header),\n\t\t\t\t     bmtd.pg_size);\n\tinfo_table_size += ALIGN(state_table_size, bmtd.pg_size);\n\tinfo_table_size += ALIGN(mapping_table_size, bmtd.pg_size);\n\n\treturn info_table_size + state_table_size + mapping_table_size +\n\t\tsizeof(struct nmbm_instance);\n}\n\n/*\n * nmbm_init_structure - Initialize members of instance structure\n * @ni: NMBM instance structure\n */\nstatic void nmbm_init_structure(struct nmbm_instance *ni)\n{\n\tuint32_t pages_per_block, blocks_per_chip;\n\tuintptr_t ptr;\n\n\tpages_per_block = bmtd.blk_size / bmtd.pg_size;\n\tblocks_per_chip = bmtd.total_blks;\n\n\tni->rawpage_size = bmtd.pg_size + bmtd.mtd->oobsize;\n\tni->rawblock_size = pages_per_block * ni->rawpage_size;\n\tni->rawchip_size = blocks_per_chip * ni->rawblock_size;\n\n\t/* Calculate number of block this chip */\n\tni->block_count = blocks_per_chip;\n\n\t/* Calculate info table size */\n\tni->state_table_size = ((ni->block_count + NMBM_BITMAP_BLOCKS_PER_UNIT - 1) /\n\t\tNMBM_BITMAP_BLOCKS_PER_UNIT) * NMBM_BITMAP_UNIT_SIZE;\n\tni->mapping_table_size = ni->block_count * sizeof(*ni->block_mapping);\n\n\tni->info_table_size = ALIGN(sizeof(ni->info_table),\n\t\t\t\t\t bmtd.pg_size);\n\tni->info_table.state_table_off = ni->info_table_size;\n\n\tni->info_table_size += ALIGN(ni->state_table_size,\n\t\t\t\t\t  bmtd.pg_size);\n\tni->info_table.mapping_table_off = ni->info_table_size;\n\n\tni->info_table_size += ALIGN(ni->mapping_table_size,\n\t\t\t\t\t  bmtd.pg_size);\n\n\tni->info_table_spare_blocks = nmbm_get_spare_block_count(\n\t\tsize2blk(ni, ni->info_table_size));\n\n\t/* Assign memory to members */\n\tptr = (uintptr_t)ni + sizeof(*ni);\n\n\tni->info_table_cache = (void *)ptr;\n\tptr += ni->info_table_size;\n\n\tni->block_state = (void *)ptr;\n\tptr += ni->state_table_size;\n\n\tni->block_mapping = (void *)ptr;\n\tptr += ni->mapping_table_size;\n\n\tni->page_cache = bmtd.data_buf;\n\n\t/* Initialize block state table */\n\tni->block_state_changed = 0;\n\tmemset(ni->block_state, 0xff, ni->state_table_size);\n\n\t/* Initialize block mapping table */\n\tni->block_mapping_changed = 0;\n}\n\n/*\n * nmbm_attach - Attach to a lower device\n * @ni: NMBM instance structure\n */\nstatic int nmbm_attach(struct nmbm_instance *ni)\n{\n\tbool success;\n\n\tif (!ni)\n\t\treturn -EINVAL;\n\n\t/* Initialize NMBM instance */\n\tnmbm_init_structure(ni);\n\n\tsuccess = nmbm_find_signature(ni, &ni->signature, &ni->signature_ba);\n\tif (!success) {\n\t\tif (!ni->force_create) {\n\t\t\tnlog_err(ni, \"Signature not found\\n\");\n\t\t\treturn -ENODEV;\n\t\t}\n\n\t\tsuccess = nmbm_create_new(ni);\n\t\tif (!success)\n\t\t\treturn -ENODEV;\n\n\t\treturn 0;\n\t}\n\n\tnlog_info(ni, \"Signature found at block %u [0x%08llx]\\n\",\n\t\t ni->signature_ba, ba2addr(ni, ni->signature_ba));\n\n\tif (ni->signature.header.version != NMBM_VER) {\n\t\tnlog_err(ni, \"NMBM version %u.%u is not supported\\n\",\n\t\t\tNMBM_VERSION_MAJOR_GET(ni->signature.header.version),\n\t\t\tNMBM_VERSION_MINOR_GET(ni->signature.header.version));\n\t\treturn -EINVAL;\n\t}\n\n\tif (ni->signature.nand_size != bmtd.total_blks << bmtd.blk_shift ||\n\t    ni->signature.block_size != bmtd.blk_size ||\n\t    ni->signature.page_size != bmtd.pg_size ||\n\t    ni->signature.spare_size != bmtd.mtd->oobsize) {\n\t\tnlog_err(ni, \"NMBM configuration mismatch\\n\");\n\t\treturn -EINVAL;\n\t}\n\n\tsuccess = nmbm_load_existing(ni);\n\tif (!success)\n\t\treturn -ENODEV;\n\n\treturn 0;\n}\n\nstatic bool remap_block_nmbm(u16 block, u16 mapped_block, int copy_len)\n{\n\tstruct nmbm_instance *ni = bmtd.ni;\n\tint new_block;\n\n\tif (block >= ni->data_block_count)\n\t\treturn false;\n\n\tnmbm_set_block_state(ni, mapped_block, BLOCK_ST_BAD);\n\tif (!nmbm_map_block(ni, block))\n\t\treturn false;\n\n\tnew_block = ni->block_mapping[block];\n\tbbt_nand_erase(new_block);\n    if (copy_len > 0)\n\t\tbbt_nand_copy(new_block, mapped_block, copy_len);\n\tnmbm_update_info_table(ni);\n\n\treturn true;\n}\n\nstatic int get_mapping_block_index_nmbm(int block)\n{\n\tstruct nmbm_instance *ni = bmtd.ni;\n\n\tif (block >= ni->data_block_count)\n\t\treturn -1;\n\n\treturn ni->block_mapping[block];\n}\n\nstatic int mtk_bmt_init_nmbm(struct device_node *np)\n{\n\tstruct nmbm_instance *ni;\n\tint ret;\n\n\tni = kzalloc(nmbm_calc_structure_size(), GFP_KERNEL);\n\tif (!ni)\n\t\treturn -ENOMEM;\n\n\tbmtd.ni = ni;\n\n\tif (of_property_read_u32(np, \"mediatek,bmt-max-ratio\", &ni->max_ratio))\n\t\tni->max_ratio = 1;\n\tif (of_property_read_u32(np, \"mediatek,bmt-max-reserved-blocks\",\n\t\t\t\t &ni->max_reserved_blocks))\n\t\tni->max_reserved_blocks = 256;\n\tif (of_property_read_bool(np, \"mediatek,empty-page-ecc-protected\"))\n\t\tni->empty_page_ecc_ok = true;\n\tif (of_property_read_bool(np, \"mediatek,bmt-force-create\"))\n\t\tni->force_create = true;\n\n\tret = nmbm_attach(ni);\n\tif (ret)\n\t\tgoto out;\n\n\tbmtd.mtd->size = ni->data_block_count << bmtd.blk_shift;\n\n\treturn 0;\n\nout:\n\tkfree(ni);\n\tbmtd.ni = NULL;\n\n\treturn ret;\n}\n\nstatic int mtk_bmt_debug_nmbm(void *data, u64 val)\n{\n\tstruct nmbm_instance *ni = bmtd.ni;\n\tint i;\n\n\tswitch (val) {\n\tcase 0:\n\t\tfor (i = 1; i < ni->data_block_count; i++) {\n\t\t\tif (ni->block_mapping[i] < ni->mapping_blocks_ba)\n\t\t\t\tcontinue;\n\n\t\t\tprintk(\"remap [%x->%x]\\n\", i, ni->block_mapping[i]);\n\t\t}\n\t}\n\n\treturn 0;\n}\n\nstatic void unmap_block_nmbm(u16 block)\n{\n\tstruct nmbm_instance *ni = bmtd.ni;\n\tint start, offset;\n\tint new_block;\n\n\tif (block >= ni->data_block_count)\n\t\treturn;\n\n\tstart = block;\n\toffset = 0;\n\twhile (ni->block_mapping[start] >= ni->mapping_blocks_ba) {\n\t\tstart--;\n\t\toffset++;\n\t\tif (start < 0)\n\t\t\treturn;\n\t}\n\n\tif (!offset)\n\t\treturn;\n\n\tnew_block = ni->block_mapping[start] + offset;\n\tnmbm_set_block_state(ni, new_block, BLOCK_ST_GOOD);\n\tni->block_mapping[block] = new_block;\n\tni->block_mapping_changed++;\n\n\tnew_block = ni->signature_ba - 1;\n\tfor (block = 0; block < ni->data_block_count; block++) {\n\t\tint cur = ni->block_mapping[block];\n\n\t\tif (cur < ni->mapping_blocks_ba)\n\t\t\tcontinue;\n\n\t\tif (cur <= new_block)\n\t\t\tnew_block = cur - 1;\n\t}\n\n\tni->mapping_blocks_top_ba = new_block;\n\n\tnmbm_update_info_table(ni);\n}\n\nconst struct mtk_bmt_ops mtk_bmt_nmbm_ops = {\n\t.init = mtk_bmt_init_nmbm,\n\t.remap_block = remap_block_nmbm,\n\t.unmap_block = unmap_block_nmbm,\n\t.get_mapping_block = get_mapping_block_index_nmbm,\n\t.debug = mtk_bmt_debug_nmbm,\n};\n"
  },
  {
    "path": "target/linux/generic/files/drivers/mtd/nand/mtk_bmt_v2.c",
    "content": "/*\n * Copyright (c) 2017 MediaTek Inc.\n * Author: Xiangsheng Hou <xiangsheng.hou@mediatek.com>\n * Copyright (c) 2020-2022 Felix Fietkau <nbd@nbd.name>\n *\n * This program is free software; you can redistribute it and/or modify\n * it under the terms of the GNU General Public License version 2 as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n * GNU General Public License for more details.\n */\n\n#include <linux/kernel.h>\n#include <linux/slab.h>\n#include \"mtk_bmt.h\"\n\nstruct bbbt {\n\tchar signature[3];\n\t/* This version is used to distinguish the legacy and new algorithm */\n#define BBMT_VERSION\t\t2\n\tunsigned char version;\n\t/* Below 2 tables will be written in SLC */\n\tu16 bb_tbl[];\n};\n\nstruct bbmt {\n\tu16 block;\n#define NO_MAPPED\t\t0\n#define NORMAL_MAPPED\t1\n#define BMT_MAPPED\t\t2\n\tu16 mapped;\n};\n\n/* Maximum 8k blocks */\n#define BBPOOL_RATIO\t\t2\n#define BB_TABLE_MAX\tbmtd.table_size\n#define BMT_TABLE_MAX\t(BB_TABLE_MAX * BBPOOL_RATIO / 100)\n#define BMT_TBL_DEF_VAL\t0x0\n\nstatic inline struct bbmt *bmt_tbl(struct bbbt *bbbt)\n{\n\treturn (struct bbmt *)&bbbt->bb_tbl[bmtd.table_size];\n}\n\nstatic u16 find_valid_block(u16 block)\n{\n\tu8 fdm[4];\n\tint ret;\n\tint loop = 0;\n\nretry:\n\tif (block >= bmtd.total_blks)\n\t\treturn 0;\n\n\tret = bbt_nand_read(blk_pg(block), bmtd.data_buf, bmtd.pg_size,\n\t\t\t    fdm, sizeof(fdm));\n\t/* Read the 1st byte of FDM to judge whether it's a bad\n\t * or not\n\t */\n\tif (ret || fdm[0] != 0xff) {\n\t\tpr_info(\"nand: found bad block 0x%x\\n\", block);\n\t\tif (loop >= bmtd.bb_max) {\n\t\t\tpr_info(\"nand: FATAL ERR: too many bad blocks!!\\n\");\n\t\t\treturn 0;\n\t\t}\n\n\t\tloop++;\n\t\tblock++;\n\t\tgoto retry;\n\t}\n\n\treturn block;\n}\n\n/* Find out all bad blocks, and fill in the mapping table */\nstatic int scan_bad_blocks(struct bbbt *bbt)\n{\n\tint i;\n\tu16 block = 0;\n\n\t/* First time download, the block0 MUST NOT be a bad block,\n\t * this is guaranteed by vendor\n\t */\n\tbbt->bb_tbl[0] = 0;\n\n\t/*\n\t * Construct the mapping table of Normal data area(non-PMT/BMTPOOL)\n\t * G - Good block; B - Bad block\n\t *\t\t\t---------------------------\n\t * physical |G|G|B|G|B|B|G|G|G|G|B|G|B|\n\t *\t\t\t---------------------------\n\t * What bb_tbl[i] looks like:\n\t *   physical block(i):\n\t *\t\t\t 0 1 2 3 4 5 6 7 8 9 a b c\n\t *   mapped block(bb_tbl[i]):\n\t *\t\t\t 0 1 3 6 7 8 9 b ......\n\t * ATTENTION:\n\t *\t\tIf new bad block ocurred(n), search bmt_tbl to find\n\t *\t\ta available block(x), and fill in the bb_tbl[n] = x;\n\t */\n\tfor (i = 1; i < bmtd.pool_lba; i++) {\n\t\tbbt->bb_tbl[i] = find_valid_block(bbt->bb_tbl[i - 1] + 1);\n\t\tBBT_LOG(\"bb_tbl[0x%x] = 0x%x\", i, bbt->bb_tbl[i]);\n\t\tif (bbt->bb_tbl[i] == 0)\n\t\t\treturn -1;\n\t}\n\n\t/* Physical Block start Address of BMT pool */\n\tbmtd.pool_pba = bbt->bb_tbl[i - 1] + 1;\n\tif (bmtd.pool_pba >= bmtd.total_blks - 2) {\n\t\tpr_info(\"nand: FATAL ERR: Too many bad blocks!!\\n\");\n\t\treturn -1;\n\t}\n\n\tBBT_LOG(\"pool_pba=0x%x\", bmtd.pool_pba);\n\ti = 0;\n\tblock = bmtd.pool_pba;\n\t/*\n\t * The bmt table is used for runtime bad block mapping\n\t * G - Good block; B - Bad block\n\t *\t\t\t---------------------------\n\t * physical |G|G|B|G|B|B|G|G|G|G|B|G|B|\n\t *\t\t\t---------------------------\n\t *   block:\t 0 1 2 3 4 5 6 7 8 9 a b c\n\t * What bmt_tbl[i] looks like in initial state:\n\t *   i:\n\t *\t\t\t 0 1 2 3 4 5 6 7\n\t *   bmt_tbl[i].block:\n\t *\t\t\t 0 1 3 6 7 8 9 b\n\t *   bmt_tbl[i].mapped:\n\t *\t\t\t N N N N N N N B\n\t *\t\tN - Not mapped(Available)\n\t *\t\tM - Mapped\n\t *\t\tB - BMT\n\t * ATTENTION:\n\t *\t\tBMT always in the last valid block in pool\n\t */\n\twhile ((block = find_valid_block(block)) != 0) {\n\t\tbmt_tbl(bbt)[i].block = block;\n\t\tbmt_tbl(bbt)[i].mapped = NO_MAPPED;\n\t\tBBT_LOG(\"bmt_tbl[%d].block = 0x%x\", i, block);\n\t\tblock++;\n\t\ti++;\n\t}\n\n\t/* i - How many available blocks in pool, which is the length of bmt_tbl[]\n\t * bmtd.bmt_blk_idx - bmt_tbl[bmtd.bmt_blk_idx].block => the BMT block\n\t */\n\tbmtd.bmt_blk_idx = i - 1;\n\tbmt_tbl(bbt)[bmtd.bmt_blk_idx].mapped = BMT_MAPPED;\n\n\tif (i < 1) {\n\t\tpr_info(\"nand: FATAL ERR: no space to store BMT!!\\n\");\n\t\treturn -1;\n\t}\n\n\tpr_info(\"[BBT] %d available blocks in BMT pool\\n\", i);\n\n\treturn 0;\n}\n\nstatic bool is_valid_bmt(unsigned char *buf, unsigned char *fdm)\n{\n\tstruct bbbt *bbt = (struct bbbt *)buf;\n\tu8 *sig = (u8*)bbt->signature + MAIN_SIGNATURE_OFFSET;\n\n\n\tif (memcmp(bbt->signature + MAIN_SIGNATURE_OFFSET, \"BMT\", 3) == 0 &&\n\t\tmemcmp(fdm + OOB_SIGNATURE_OFFSET, \"bmt\", 3) == 0) {\n\t\tif (bbt->version == BBMT_VERSION)\n\t\t\treturn true;\n\t}\n\tBBT_LOG(\"[BBT] BMT Version not match,upgrage preloader and uboot please! sig=%02x%02x%02x, fdm=%02x%02x%02x\",\n\t\tsig[0], sig[1], sig[2],\n\t\tfdm[1], fdm[2], fdm[3]);\n\treturn false;\n}\n\nstatic u16 get_bmt_index(struct bbmt *bmt)\n{\n\tint i = 0;\n\n\twhile (bmt[i].block != BMT_TBL_DEF_VAL) {\n\t\tif (bmt[i].mapped == BMT_MAPPED)\n\t\t\treturn i;\n\t\ti++;\n\t}\n\treturn 0;\n}\n\nstatic int\nread_bmt(u16 block, unsigned char *dat, unsigned char *fdm, int fdm_len)\n{\n\tu32 len = bmtd.bmt_pgs << bmtd.pg_shift;\n\n\treturn bbt_nand_read(blk_pg(block), dat, len, fdm, fdm_len);\n}\n\nstatic struct bbbt *scan_bmt(u16 block)\n{\n\tu8 fdm[4];\n\n\tif (block < bmtd.pool_lba)\n\t\treturn NULL;\n\n\tif (read_bmt(block, bmtd.bbt_buf, fdm, sizeof(fdm)))\n\t\treturn scan_bmt(block - 1);\n\n\tif (is_valid_bmt(bmtd.bbt_buf, fdm)) {\n\t\tbmtd.bmt_blk_idx = get_bmt_index(bmt_tbl((struct bbbt *)bmtd.bbt_buf));\n\t\tif (bmtd.bmt_blk_idx == 0) {\n\t\t\tpr_info(\"[BBT] FATAL ERR: bmt block index is wrong!\\n\");\n\t\t\treturn NULL;\n\t\t}\n\t\tpr_info(\"[BBT] BMT.v2 is found at 0x%x\\n\", block);\n\t\treturn (struct bbbt *)bmtd.bbt_buf;\n\t} else\n\t\treturn scan_bmt(block - 1);\n}\n\n/* Write the Burner Bad Block Table to Nand Flash\n * n - write BMT to bmt_tbl[n]\n */\nstatic u16 upload_bmt(struct bbbt *bbt, int n)\n{\n\tu16 block;\n\nretry:\n\tif (n < 0 || bmt_tbl(bbt)[n].mapped == NORMAL_MAPPED) {\n\t\tpr_info(\"nand: FATAL ERR: no space to store BMT!\\n\");\n\t\treturn (u16)-1;\n\t}\n\n\tblock = bmt_tbl(bbt)[n].block;\n\tBBT_LOG(\"n = 0x%x, block = 0x%x\", n, block);\n\tif (bbt_nand_erase(block)) {\n\t\tbmt_tbl(bbt)[n].block = 0;\n\t\t/* erase failed, try the previous block: bmt_tbl[n - 1].block */\n\t\tn--;\n\t\tgoto retry;\n\t}\n\n\t/* The signature offset is fixed set to 0,\n\t * oob signature offset is fixed set to 1\n\t */\n\tmemcpy(bbt->signature + MAIN_SIGNATURE_OFFSET, \"BMT\", 3);\n\tbbt->version = BBMT_VERSION;\n\n\tif (write_bmt(block, (unsigned char *)bbt)) {\n\t\tbmt_tbl(bbt)[n].block = 0;\n\n\t\t/* write failed, try the previous block in bmt_tbl[n - 1] */\n\t\tn--;\n\t\tgoto retry;\n\t}\n\n\t/* Return the current index(n) of BMT pool (bmt_tbl[n]) */\n\treturn n;\n}\n\nstatic u16 find_valid_block_in_pool(struct bbbt *bbt)\n{\n\tint i;\n\n\tif (bmtd.bmt_blk_idx == 0)\n\t\tgoto error;\n\n\tfor (i = 0; i < bmtd.bmt_blk_idx; i++) {\n\t\tif (bmt_tbl(bbt)[i].block != 0 && bmt_tbl(bbt)[i].mapped == NO_MAPPED) {\n\t\t\tbmt_tbl(bbt)[i].mapped = NORMAL_MAPPED;\n\t\t\treturn bmt_tbl(bbt)[i].block;\n\t\t}\n\t}\n\nerror:\n\tpr_info(\"nand: FATAL ERR: BMT pool is run out!\\n\");\n\treturn 0;\n}\n\n/* We met a bad block, mark it as bad and map it to a valid block in pool,\n * if it's a write failure, we need to write the data to mapped block\n */\nstatic bool remap_block_v2(u16 block, u16 mapped_block, int copy_len)\n{\n\tu16 new_block;\n\tstruct bbbt *bbt;\n\n\tbbt = bmtd.bbt;\n\tnew_block = find_valid_block_in_pool(bbt);\n\tif (new_block == 0)\n\t\treturn false;\n\n\t/* Map new bad block to available block in pool */\n\tbbt->bb_tbl[block] = new_block;\n\n\t/* Erase new block */\n\tbbt_nand_erase(new_block);\n\tif (copy_len > 0)\n\t\tbbt_nand_copy(new_block, mapped_block, copy_len);\n\n\tbmtd.bmt_blk_idx = upload_bmt(bbt, bmtd.bmt_blk_idx);\n\n\treturn true;\n}\n\nstatic int get_mapping_block_index_v2(int block)\n{\n\tint start, end;\n\n\tif (block >= bmtd.pool_lba)\n\t\treturn block;\n\n\tif (!mapping_block_in_range(block, &start, &end))\n\t\treturn block;\n\n\treturn bmtd.bbt->bb_tbl[block];\n}\n\nstatic void\nunmap_block_v2(u16 block)\n{\n\tbmtd.bbt->bb_tbl[block] = block;\n\tbmtd.bmt_blk_idx = upload_bmt(bmtd.bbt, bmtd.bmt_blk_idx);\n}\n\nstatic unsigned long *\nmtk_bmt_get_mapping_mask(void)\n{\n\tstruct bbmt *bbmt = bmt_tbl(bmtd.bbt);\n\tint main_blocks = bmtd.mtd->size >> bmtd.blk_shift;\n\tunsigned long *used;\n\tint i, k;\n\n\tused = kcalloc(sizeof(unsigned long), BIT_WORD(bmtd.bmt_blk_idx) + 1, GFP_KERNEL);\n\tif (!used)\n\t\treturn NULL;\n\n\tfor (i = 1; i < main_blocks; i++) {\n\t\tif (bmtd.bbt->bb_tbl[i] == i)\n\t\t\tcontinue;\n\n\t\tfor (k = 0; k < bmtd.bmt_blk_idx; k++) {\n\t\t\tif (bmtd.bbt->bb_tbl[i] != bbmt[k].block)\n\t\t\t\tcontinue;\n\n\t\t\tset_bit(k, used);\n\t\t\tbreak;\n\t\t}\n\t}\n\n\treturn used;\n}\n\nstatic int mtk_bmt_debug_v2(void *data, u64 val)\n{\n\tstruct bbmt *bbmt = bmt_tbl(bmtd.bbt);\n\tstruct mtd_info *mtd = bmtd.mtd;\n\tunsigned long *used;\n\tint main_blocks = mtd->size >> bmtd.blk_shift;\n\tint n_remap = 0;\n\tint i;\n\n\tused = mtk_bmt_get_mapping_mask();\n\tif (!used)\n\t\treturn -ENOMEM;\n\n\tswitch (val) {\n\tcase 0:\n\t\tfor (i = 1; i < main_blocks; i++) {\n\t\t\tif (bmtd.bbt->bb_tbl[i] == i)\n\t\t\t\tcontinue;\n\n\t\t\tprintk(\"remap [%x->%x]\\n\", i, bmtd.bbt->bb_tbl[i]);\n\t\t\tn_remap++;\n\t\t}\n\t\tfor (i = 0; i <= bmtd.bmt_blk_idx; i++) {\n\t\t\tchar c;\n\n\t\t\tswitch (bbmt[i].mapped) {\n\t\t\tcase NO_MAPPED:\n\t\t\t\tcontinue;\n\t\t\tcase NORMAL_MAPPED:\n\t\t\t\tc = 'm';\n\t\t\t\tif (test_bit(i, used))\n\t\t\t\t\tc = 'M';\n\t\t\t\tbreak;\n\t\t\tcase BMT_MAPPED:\n\t\t\t\tc = 'B';\n\t\t\t\tbreak;\n\t\t\tdefault:\n\t\t\t\tc = 'X';\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\tprintk(\"[%x:%c] = 0x%x\\n\", i, c, bbmt[i].block);\n\t\t}\n\t\tbreak;\n\tcase 100:\n\t\tfor (i = 0; i <= bmtd.bmt_blk_idx; i++) {\n\t\t\tif (bbmt[i].mapped != NORMAL_MAPPED)\n\t\t\t\tcontinue;\n\n\t\t\tif (test_bit(i, used))\n\t\t\t\tcontinue;\n\n\t\t\tn_remap++;\n\t\t\tbbmt[i].mapped = NO_MAPPED;\n\t\t\tprintk(\"free block [%d:%x]\\n\", i, bbmt[i].block);\n\t\t}\n\t\tif (n_remap)\n\t\t\tbmtd.bmt_blk_idx = upload_bmt(bmtd.bbt, bmtd.bmt_blk_idx);\n\t\tbreak;\n\t}\n\n\tkfree(used);\n\n\treturn 0;\n}\n\nstatic int mtk_bmt_init_v2(struct device_node *np)\n{\n\tu32 bmt_pool_size, bmt_table_size;\n\tu32 bufsz, block;\n\tu16 pmt_block;\n\n\tif (of_property_read_u32(np, \"mediatek,bmt-pool-size\",\n\t\t\t\t &bmt_pool_size) != 0)\n\t\tbmt_pool_size = 80;\n\n\tif (of_property_read_u8(np, \"mediatek,bmt-oob-offset\",\n\t\t\t\t &bmtd.oob_offset) != 0)\n\t\tbmtd.oob_offset = 0;\n\n\tif (of_property_read_u32(np, \"mediatek,bmt-table-size\",\n\t\t\t\t &bmt_table_size) != 0)\n\t\tbmt_table_size = 0x2000U;\n\n\tbmtd.table_size = bmt_table_size;\n\n\tpmt_block = bmtd.total_blks - bmt_pool_size - 2;\n\n\tbmtd.mtd->size = pmt_block << bmtd.blk_shift;\n\n\t/*\n\t *  ---------------------------------------\n\t * | PMT(2blks) | BMT POOL(totalblks * 2%) |\n\t *  ---------------------------------------\n\t * ^            ^\n\t * |            |\n\t * pmt_block\tpmt_block + 2blocks(pool_lba)\n\t *\n\t * ATTETION!!!!!!\n\t *     The blocks ahead of the boundary block are stored in bb_tbl\n\t *     and blocks behind are stored in bmt_tbl\n\t */\n\n\tbmtd.pool_lba = (u16)(pmt_block + 2);\n\tbmtd.bb_max = bmtd.total_blks * BBPOOL_RATIO / 100;\n\n\tbufsz = round_up(sizeof(struct bbbt) +\n\t\t\t bmt_table_size * sizeof(struct bbmt), bmtd.pg_size);\n\tbmtd.bmt_pgs = bufsz >> bmtd.pg_shift;\n\n\tbmtd.bbt_buf = kzalloc(bufsz, GFP_KERNEL);\n\tif (!bmtd.bbt_buf)\n\t\treturn -ENOMEM;\n\n\tmemset(bmtd.bbt_buf, 0xff, bufsz);\n\n\t/* Scanning start from the first page of the last block\n\t * of whole flash\n\t */\n\tbmtd.bbt = scan_bmt(bmtd.total_blks - 1);\n\tif (!bmtd.bbt) {\n\t\t/* BMT not found */\n\t\tif (bmtd.total_blks > BB_TABLE_MAX + BMT_TABLE_MAX) {\n\t\t\tpr_info(\"nand: FATAL: Too many blocks, can not support!\\n\");\n\t\t\treturn -1;\n\t\t}\n\n\t\tbmtd.bbt = (struct bbbt *)bmtd.bbt_buf;\n\t\tmemset(bmt_tbl(bmtd.bbt), BMT_TBL_DEF_VAL,\n\t\t       bmtd.table_size * sizeof(struct bbmt));\n\n\t\tif (scan_bad_blocks(bmtd.bbt))\n\t\t\treturn -1;\n\n\t\t/* BMT always in the last valid block in pool */\n\t\tbmtd.bmt_blk_idx = upload_bmt(bmtd.bbt, bmtd.bmt_blk_idx);\n\t\tblock = bmt_tbl(bmtd.bbt)[bmtd.bmt_blk_idx].block;\n\t\tpr_notice(\"[BBT] BMT.v2 is written into PBA:0x%x\\n\", block);\n\n\t\tif (bmtd.bmt_blk_idx == 0)\n\t\t\tpr_info(\"nand: Warning: no available block in BMT pool!\\n\");\n\t\telse if (bmtd.bmt_blk_idx == (u16)-1)\n\t\t\treturn -1;\n\t}\n\n\treturn 0;\n}\n\n\nconst struct mtk_bmt_ops mtk_bmt_v2_ops = {\n\t.sig = \"bmt\",\n\t.sig_len = 3,\n\t.init = mtk_bmt_init_v2,\n\t.remap_block = remap_block_v2,\n\t.unmap_block = unmap_block_v2,\n\t.get_mapping_block = get_mapping_block_index_v2,\n\t.debug = mtk_bmt_debug_v2,\n};\n"
  },
  {
    "path": "target/linux/generic/files/drivers/mtd/parsers/routerbootpart.c",
    "content": "// SPDX-License-Identifier: GPL-2.0-only\n/*\n * Parser for MikroTik RouterBoot partitions.\n *\n * Copyright (C) 2020 Thibaut VARÈNE <hacks+kernel@slashdirt.org>\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of the GNU General Public License version 2 as published\n * by the Free Software Foundation.\n *\n * This parser builds from the \"fixed-partitions\" one (see ofpart.c), but it can\n * handle dynamic partitions as found on routerboot devices.\n *\n * DTS nodes are defined as follows:\n * For fixed partitions:\n *\tnode-name@unit-address {\n *\t\treg = <prop-encoded-array>;\n *\t\tlabel = <string>;\n *\t\tread-only;\n *\t\tlock;\n *\t};\n *\n * reg property is mandatory; other properties are optional.\n * reg format is <address length>. length can be 0 if the next partition is\n * another fixed partition or a \"well-known\" partition as defined below: in that\n * case the partition will extend up to the next one.\n *\n * For dynamic partitions:\n *\tnode-name {\n *\t\tsize = <prop-encoded-array>;\n *\t\tlabel = <string>;\n *\t\tread-only;\n *\t\tlock;\n *\t};\n *\n * size property is normally mandatory. It can only be omitted (or set to 0) if:\n *\t- the partition is a \"well-known\" one (as defined below), in which case\n *\t  the partition size will be automatically adjusted; or\n *\t- the next partition is a fixed one or a \"well-known\" one, in which case\n *\t  the current partition will extend up to the next one.\n * Other properties are optional.\n * size format is <length>.\n * By default dynamic partitions are appended after the preceding one, except\n * for \"well-known\" ones which are automatically located on flash.\n *\n * Well-known partitions (matched via label or node-name):\n * - \"hard_config\"\n * - \"soft_config\"\n * - \"dtb_config\"\n *\n * Note: this parser will happily register 0-sized partitions if misused.\n *\n * This parser requires the DTS to list partitions in ascending order as\n * expected on the MTD device.\n *\n * Since only the \"hard_config\" and \"soft_config\" partitions are used in OpenWRT,\n * a minimal working DTS could define only these two partitions dynamically (in\n * the right order, usually hard_config then soft_config).\n *\n * Note: some mips RB devices encode the hard_config offset and length in two\n * consecutive u32 located at offset 0x14 (for ramips) or 0x24 (for ath79) on\n * the SPI NOR flash. Unfortunately this seems inconsistent across machines and\n * does not apply to e.g. ipq-based ones, so we ignore that information.\n *\n * Note: To find well-known partitions, this parser will go through the entire\n * top mtd partition parsed, _before_ the DTS nodes are processed. This works\n * well in the current state of affairs, and is a simpler implementation than\n * searching for known partitions in the \"holes\" left between fixed-partition,\n * _after_ processing DTS nodes.\n */\n\n#include <linux/module.h>\n#include <linux/slab.h>\n#include <linux/mtd/mtd.h>\n#include <linux/mtd/partitions.h>\n#include <linux/of.h>\n#include <linux/of_fdt.h>\n#include <linux/libfdt_env.h>\n#include <linux/string.h>\n\n#define RB_MAGIC_HARD\t(('H') | ('a' << 8) | ('r' << 16) | ('d' << 24))\n#define RB_MAGIC_SOFT\t(('S') | ('o' << 8) | ('f' << 16) | ('t' << 24))\n#define RB_BLOCK_SIZE\t0x1000\n\nstruct routerboot_dynpart {\n\tconst char * const name;\n\tconst u32 magic;\n\tint (* const size_fixup)(struct mtd_info *, struct routerboot_dynpart *);\n\tsize_t offset;\n\tsize_t size;\n\tbool found;\n};\n\nstatic int routerboot_dtbsfixup(struct mtd_info *, struct routerboot_dynpart *);\n\nstatic struct routerboot_dynpart rb_dynparts[] = {\n\t{\n\t\t.name = \"hard_config\",\n\t\t.magic = RB_MAGIC_HARD,\t// stored in CPU-endianness on flash\n\t\t.size_fixup = NULL,\n\t\t.offset = 0x0,\n\t\t.size = RB_BLOCK_SIZE,\n\t\t.found = false,\n\t}, {\n\t\t.name = \"soft_config\",\n\t\t.magic = RB_MAGIC_SOFT,\t// stored in CPU-endianness on flash\n\t\t.size_fixup = NULL,\n\t\t.offset = 0x0,\n\t\t.size = RB_BLOCK_SIZE,\n\t\t.found = false,\n\t}, {\n\t\t.name = \"dtb_config\",\n\t\t.magic = fdt32_to_cpu(OF_DT_HEADER),\t// stored BE on flash\n\t\t.size_fixup = routerboot_dtbsfixup,\n\t\t.offset = 0x0,\n\t\t.size = 0x0,\n\t\t.found = false,\n\t}\n};\n\nstatic int routerboot_dtbsfixup(struct mtd_info *master, struct routerboot_dynpart *rbdpart)\n{\n\tint err;\n\tsize_t bytes_read, psize;\n\tstruct {\n\t\tfdt32_t magic;\n\t\tfdt32_t totalsize;\n\t\tfdt32_t off_dt_struct;\n\t\tfdt32_t off_dt_strings;\n\t\tfdt32_t off_mem_rsvmap;\n\t\tfdt32_t version;\n\t\tfdt32_t last_comp_version;\n\t\tfdt32_t boot_cpuid_phys;\n\t\tfdt32_t size_dt_strings;\n\t\tfdt32_t size_dt_struct;\n\t} fdt_header;\n\n\terr = mtd_read(master, rbdpart->offset, sizeof(fdt_header),\n\t\t       &bytes_read, (u8 *)&fdt_header);\n\tif (err)\n\t\treturn err;\n\n\tif (bytes_read != sizeof(fdt_header))\n\t\treturn -EIO;\n\n\tpsize = fdt32_to_cpu(fdt_header.totalsize);\n\tif (!psize)\n\t\treturn -EINVAL;\n\n\trbdpart->size = psize;\n\treturn 0;\n}\n\nstatic void routerboot_find_dynparts(struct mtd_info *master)\n{\n\tsize_t bytes_read, offset;\n\tbool allfound;\n\tint err, i;\n\tu32 buf;\n\n\t/*\n\t * Dynamic RouterBoot partitions offsets are aligned to RB_BLOCK_SIZE:\n\t * read the whole partition at RB_BLOCK_SIZE intervals to find sigs.\n\t * Skip partition content when possible.\n\t */\n\toffset = 0;\n\twhile (offset < master->size) {\n\t\terr = mtd_read(master, offset, sizeof(buf), &bytes_read, (u8 *)&buf);\n\t\tif (err) {\n\t\t\tpr_err(\"%s: mtd_read error while parsing (offset: 0x%X): %d\\n\",\n\t\t\t       master->name, offset, err);\n\t\t\tcontinue;\n\t\t}\n\n\t\tallfound = true;\n\n\t\tfor (i = 0; i < ARRAY_SIZE(rb_dynparts); i++) {\n\t\t\tif (rb_dynparts[i].found)\n\t\t\t\tcontinue;\n\n\t\t\tallfound = false;\n\n\t\t\tif (rb_dynparts[i].magic == buf) {\n\t\t\t\trb_dynparts[i].offset = offset;\n\n\t\t\t\tif (rb_dynparts[i].size_fixup) {\n\t\t\t\t\terr = rb_dynparts[i].size_fixup(master, &rb_dynparts[i]);\n\t\t\t\t\tif (err) {\n\t\t\t\t\t\tpr_err(\"%s: size fixup error while parsing \\\"%s\\\": %d\\n\",\n\t\t\t\t\t\t       master->name, rb_dynparts[i].name, err);\n\t\t\t\t\t\tcontinue;\n\t\t\t\t\t}\n\t\t\t\t}\n\n\t\t\t\trb_dynparts[i].found = true;\n\n\t\t\t\t/*\n\t\t\t\t * move offset to skip the whole partition on\n\t\t\t\t * next iteration if size > RB_BLOCK_SIZE.\n\t\t\t\t */\n\t\t\t\tif (rb_dynparts[i].size > RB_BLOCK_SIZE)\n\t\t\t\t\toffset += ALIGN_DOWN((rb_dynparts[i].size - RB_BLOCK_SIZE), RB_BLOCK_SIZE);\n\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\n\t\toffset += RB_BLOCK_SIZE;\n\n\t\tif (allfound)\n\t\t\tbreak;\n\t}\n}\n\nstatic int routerboot_partitions_parse(struct mtd_info *master,\n\t\t\t\t       const struct mtd_partition **pparts,\n\t\t\t\t       struct mtd_part_parser_data *data)\n{\n\tstruct device_node *rbpart_node, *pp;\n\tstruct mtd_partition *parts;\n\tconst char *partname;\n\tsize_t master_ofs;\n\tint np;\n\n\t/* Pull of_node from the master device node */\n\trbpart_node = mtd_get_of_node(master);\n\tif (!rbpart_node)\n\t\treturn 0;\n\n\t/* First count the subnodes */\n\tnp = 0;\n\tfor_each_child_of_node(rbpart_node,  pp)\n\t\tnp++;\n\n\tif (!np)\n\t\treturn 0;\n\n\tparts = kcalloc(np, sizeof(*parts), GFP_KERNEL);\n\tif (!parts)\n\t\treturn -ENOMEM;\n\n\t/* Preemptively look for known parts in flash */\n\trouterboot_find_dynparts(master);\n\n\tnp = 0;\n\tmaster_ofs = 0;\n\tfor_each_child_of_node(rbpart_node, pp) {\n\t\tconst __be32 *reg, *sz;\n\t\tsize_t offset, size;\n\t\tint i, len, a_cells, s_cells;\n\n\t\tpartname = of_get_property(pp, \"label\", &len);\n\t\t/* Allow deprecated use of \"name\" instead of \"label\" */\n\t\tif (!partname)\n\t\t\tpartname = of_get_property(pp, \"name\", &len);\n\t\t/* Fallback to node name per spec if all else fails: partname is always set */\n\t\tif (!partname)\n\t\t\tpartname = pp->name;\n\t\tparts[np].name = partname;\n\n\t\treg = of_get_property(pp, \"reg\", &len);\n\t\tif (reg) {\n\t\t\t/* Fixed partition */\n\t\t\ta_cells = of_n_addr_cells(pp);\n\t\t\ts_cells = of_n_size_cells(pp);\n\n\t\t\tif ((len / 4) != (a_cells + s_cells)) {\n\t\t\t\tpr_debug(\"%s: routerboot partition %pOF (%pOF) error parsing reg property.\\n\",\n\t\t\t\t\t master->name, pp, rbpart_node);\n\t\t\t\tgoto rbpart_fail;\n\t\t\t}\n\n\t\t\toffset = of_read_number(reg, a_cells);\n\t\t\tsize = of_read_number(reg + a_cells, s_cells);\n\t\t} else {\n\t\t\t/* Dynamic partition */\n\t\t\t/* Default: part starts at current offset, 0 size */\n\t\t\toffset = master_ofs;\n\t\t\tsize = 0;\n\n\t\t\t/* Check if well-known partition */\n\t\t\tfor (i = 0; i < ARRAY_SIZE(rb_dynparts); i++) {\n\t\t\t\tif (!strcmp(partname, rb_dynparts[i].name) && rb_dynparts[i].found) {\n\t\t\t\t\toffset = rb_dynparts[i].offset;\n\t\t\t\t\tsize = rb_dynparts[i].size;\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t}\n\n\t\t\t/* Standalone 'size' property? Override size */\n\t\t\tsz = of_get_property(pp, \"size\", &len);\n\t\t\tif (sz) {\n\t\t\t\ts_cells = of_n_size_cells(pp);\n\t\t\t\tif ((len / 4) != s_cells) {\n\t\t\t\t\tpr_debug(\"%s: routerboot partition %pOF (%pOF) error parsing size property.\\n\",\n\t\t\t\t\t\t master->name, pp, rbpart_node);\n\t\t\t\t\tgoto rbpart_fail;\n\t\t\t\t}\n\n\t\t\t\tsize = of_read_number(sz, s_cells);\n\t\t\t}\n\t\t}\n\n\t\tif (np > 0) {\n\t\t\t/* Minor sanity check for overlaps */\n\t\t\tif (offset < (parts[np-1].offset + parts[np-1].size)) {\n\t\t\t\tpr_err(\"%s: routerboot partition %pOF (%pOF) \\\"%s\\\" overlaps with previous partition \\\"%s\\\".\\n\",\n\t\t\t\t       master->name, pp, rbpart_node,\n\t\t\t\t       partname, parts[np-1].name);\n\t\t\t\tgoto rbpart_fail;\n\t\t\t}\n\n\t\t\t/* Fixup end of previous partition if necessary */\n\t\t\tif (!parts[np-1].size)\n\t\t\t\tparts[np-1].size = (offset - parts[np-1].offset);\n\t\t}\n\n\t\tif ((offset + size) > master->size) {\n\t\t\tpr_err(\"%s: routerboot partition %pOF (%pOF) \\\"%s\\\" extends past end of segment.\\n\",\n\t\t\t       master->name, pp, rbpart_node, partname);\n\t\t\tgoto rbpart_fail;\n\t\t}\n\n\t\tparts[np].offset = offset;\n\t\tparts[np].size = size;\n\t\tparts[np].of_node = pp;\n\n\t\tif (of_get_property(pp, \"read-only\", &len))\n\t\t\tparts[np].mask_flags |= MTD_WRITEABLE;\n\n\t\tif (of_get_property(pp, \"lock\", &len))\n\t\t\tparts[np].mask_flags |= MTD_POWERUP_LOCK;\n\n\t\t/* Keep master offset aligned to RB_BLOCK_SIZE */\n\t\tmaster_ofs = ALIGN(offset + size, RB_BLOCK_SIZE);\n\t\tnp++;\n\t}\n\n\t*pparts = parts;\n\treturn np;\n\nrbpart_fail:\n\tpr_err(\"%s: error parsing routerboot partition %pOF (%pOF)\\n\",\n\t       master->name, pp, rbpart_node);\n\tof_node_put(pp);\n\tkfree(parts);\n\treturn -EINVAL;\n}\n\nstatic const struct of_device_id parse_routerbootpart_match_table[] = {\n\t{ .compatible = \"mikrotik,routerboot-partitions\" },\n\t{},\n};\nMODULE_DEVICE_TABLE(of, parse_routerbootpart_match_table);\n\nstatic struct mtd_part_parser routerbootpart_parser = {\n\t.parse_fn = routerboot_partitions_parse,\n\t.name = \"routerbootpart\",\n\t.of_match_table = parse_routerbootpart_match_table,\n};\nmodule_mtd_part_parser(routerbootpart_parser);\n\nMODULE_LICENSE(\"GPL v2\");\nMODULE_DESCRIPTION(\"MTD partitioning for RouterBoot\");\nMODULE_AUTHOR(\"Thibaut VARENE\");\n"
  },
  {
    "path": "target/linux/generic/files/drivers/net/phy/adm6996.c",
    "content": "/*\n * ADM6996 switch driver\n *\n * swconfig interface based on ar8216.c\n *\n * Copyright (c) 2008 Felix Fietkau <nbd@nbd.name>\n * VLAN support Copyright (c) 2010, 2011 Peter Lebbing <peter@digitalbrains.com>\n * Copyright (c) 2013 Hauke Mehrtens <hauke@hauke-m.de>\n * Copyright (c) 2014 Matti Laakso <malaakso@elisanet.fi>\n *\n * This program is free software; you can redistribute  it and/or modify it\n * under  the terms of the GNU General Public License v2 as published by the\n * Free Software Foundation\n */\n\n#define pr_fmt(fmt) KBUILD_MODNAME \": \" fmt\n\n/*#define DEBUG 1*/\n#include <linux/kernel.h>\n#include <linux/string.h>\n#include <linux/errno.h>\n#include <linux/unistd.h>\n#include <linux/slab.h>\n#include <linux/interrupt.h>\n#include <linux/init.h>\n#include <linux/delay.h>\n#include <linux/gpio.h>\n#include <linux/netdevice.h>\n#include <linux/etherdevice.h>\n#include <linux/skbuff.h>\n#include <linux/spinlock.h>\n#include <linux/mm.h>\n#include <linux/module.h>\n#include <linux/mii.h>\n#include <linux/platform_device.h>\n#include <linux/platform_data/adm6996-gpio.h>\n#include <linux/ethtool.h>\n#include <linux/phy.h>\n#include <linux/switch.h>\n#include <linux/version.h>\n\n#include <asm/io.h>\n#include <asm/irq.h>\n#include <asm/uaccess.h>\n#include \"adm6996.h\"\n\nMODULE_DESCRIPTION(\"Infineon ADM6996 Switch\");\nMODULE_AUTHOR(\"Felix Fietkau, Peter Lebbing <peter@digitalbrains.com>\");\nMODULE_LICENSE(\"GPL\");\n\nstatic const char * const adm6996_model_name[] =\n{\n\tNULL,\n\t\"ADM6996FC\",\n\t\"ADM6996M\",\n\t\"ADM6996L\"\n};\n\nstruct adm6996_mib_desc {\n\tunsigned int offset;\n\tconst char *name;\n};\n\nstruct adm6996_priv {\n\tstruct switch_dev dev;\n\tvoid *priv;\n\n\tu8 eecs;\n\tu8 eesk;\n\tu8 eedi;\n\n\tenum adm6996_model model;\n\n\tbool enable_vlan;\n\tbool vlan_enabled;\t/* Current hardware state */\n\n#ifdef DEBUG\n\tu16 addr;\t\t/* Debugging: register address to operate on */\n#endif\n\n\tu16 pvid[ADM_NUM_PORTS];\t/* Primary VLAN ID */\n\tu8 tagged_ports;\n\n\tu16 vlan_id[ADM_NUM_VLANS];\n\tu8 vlan_table[ADM_NUM_VLANS];\t/* bitmap, 1 = port is member */\n\tu8 vlan_tagged[ADM_NUM_VLANS];\t/* bitmap, 1 = tagged member */\n\t\n\tstruct mutex mib_lock;\n\tchar buf[2048];\n\n\tstruct mutex reg_mutex;\n\n\t/* use abstraction for regops, we want to add gpio support in the future */\n\tu16 (*read)(struct adm6996_priv *priv, enum admreg reg);\n\tvoid (*write)(struct adm6996_priv *priv, enum admreg reg, u16 val);\n};\n\n#define to_adm(_dev) container_of(_dev, struct adm6996_priv, dev)\n#define phy_to_adm(_phy) ((struct adm6996_priv *) (_phy)->priv)\n\n#define MIB_DESC(_o, _n)\t\\\n\t{\t\t\t\\\n\t\t.offset = (_o),\t\\\n\t\t.name = (_n),\t\\\n\t}\n\nstatic const struct adm6996_mib_desc adm6996_mibs[] = {\n\tMIB_DESC(ADM_CL0, \"RxPacket\"),\n\tMIB_DESC(ADM_CL6, \"RxByte\"),\n\tMIB_DESC(ADM_CL12, \"TxPacket\"),\n\tMIB_DESC(ADM_CL18, \"TxByte\"),\n\tMIB_DESC(ADM_CL24, \"Collision\"),\n\tMIB_DESC(ADM_CL30, \"Error\"),\n};\n\n#define ADM6996_MIB_RXB_ID\t1\n#define ADM6996_MIB_TXB_ID\t3\n\nstatic inline u16\nr16(struct adm6996_priv *priv, enum admreg reg)\n{\n\treturn priv->read(priv, reg);\n}\n\nstatic inline void\nw16(struct adm6996_priv *priv, enum admreg reg, u16 val)\n{\n\tpriv->write(priv, reg, val);\n}\n\n/* Minimum timing constants */\n#define EECK_EDGE_TIME  3   /* 3us - max(adm 2.5us, 93c 1us) */\n#define EEDI_SETUP_TIME 1   /* 1us - max(adm 10ns, 93c 400ns) */\n#define EECS_SETUP_TIME 1   /* 1us - max(adm no, 93c 200ns) */\n\nstatic void adm6996_gpio_write(struct adm6996_priv *priv, int cs, char *buf, unsigned int bits)\n{\n\tint i, len = (bits + 7) / 8;\n\tu8 mask;\n\n\tgpio_set_value(priv->eecs, cs);\n\tudelay(EECK_EDGE_TIME);\n\n\t/* Byte assemble from MSB to LSB */\n\tfor (i = 0; i < len; i++) {\n\t\t/* Bit bang from MSB to LSB */\n\t\tfor (mask = 0x80; mask && bits > 0; mask >>= 1, bits --) {\n\t\t\t/* Clock low */\n\t\t\tgpio_set_value(priv->eesk, 0);\n\t\t\tudelay(EECK_EDGE_TIME);\n\n\t\t\t/* Output on rising edge */\n\t\t\tgpio_set_value(priv->eedi, (mask & buf[i]));\n\t\t\tudelay(EEDI_SETUP_TIME);\n\n\t\t\t/* Clock high */\n\t\t\tgpio_set_value(priv->eesk, 1);\n\t\t\tudelay(EECK_EDGE_TIME);\n\t\t}\n\t}\n\n\t/* Clock low */\n\tgpio_set_value(priv->eesk, 0);\n\tudelay(EECK_EDGE_TIME);\n\n\tif (cs)\n\t\tgpio_set_value(priv->eecs, 0);\n}\n\nstatic void adm6996_gpio_read(struct adm6996_priv *priv, int cs, char *buf, unsigned int bits)\n{\n\tint i, len = (bits + 7) / 8;\n\tu8 mask;\n\n\tgpio_set_value(priv->eecs, cs);\n\tudelay(EECK_EDGE_TIME);\n\n\t/* Byte assemble from MSB to LSB */\n\tfor (i = 0; i < len; i++) {\n\t\tu8 byte;\n\n\t\t/* Bit bang from MSB to LSB */\n\t\tfor (mask = 0x80, byte = 0; mask && bits > 0; mask >>= 1, bits --) {\n\t\t\tu8 gp;\n\n\t\t\t/* Clock low */\n\t\t\tgpio_set_value(priv->eesk, 0);\n\t\t\tudelay(EECK_EDGE_TIME);\n\n\t\t\t/* Input on rising edge */\n\t\t\tgp = gpio_get_value(priv->eedi);\n\t\t\tif (gp)\n\t\t\t\tbyte |= mask;\n\n\t\t\t/* Clock high */\n\t\t\tgpio_set_value(priv->eesk, 1);\n\t\t\tudelay(EECK_EDGE_TIME);\n\t\t}\n\n\t\t*buf++ = byte;\n\t}\n\n\t/* Clock low */\n\tgpio_set_value(priv->eesk, 0);\n\tudelay(EECK_EDGE_TIME);\n\n\tif (cs)\n\t\tgpio_set_value(priv->eecs, 0);\n}\n\n/* Advance clock(s) */\nstatic void adm6996_gpio_adclk(struct adm6996_priv *priv, int clocks)\n{\n\tint i;\n\tfor (i = 0; i < clocks; i++) {\n\t\t/* Clock high */\n\t\tgpio_set_value(priv->eesk, 1);\n\t\tudelay(EECK_EDGE_TIME);\n\n\t\t/* Clock low */\n\t\tgpio_set_value(priv->eesk, 0);\n\t\tudelay(EECK_EDGE_TIME);\n\t}\n}\n\nstatic u16\nadm6996_read_gpio_reg(struct adm6996_priv *priv, enum admreg reg)\n{\n\t/* cmd: 01 10 T DD R RRRRRR */\n\tu8 bits[6] = {\n\t\t0xFF, 0xFF, 0xFF, 0xFF,\n\t\t(0x06 << 4) | ((0 & 0x01) << 3 | (reg&64)>>6),\n\t\t((reg&63)<<2)\n\t};\n\n\tu8 rbits[4];\n\n\t/* Enable GPIO outputs with all pins to 0 */\n\tgpio_direction_output(priv->eecs, 0);\n\tgpio_direction_output(priv->eesk, 0);\n\tgpio_direction_output(priv->eedi, 0);\n\n\tadm6996_gpio_write(priv, 0, bits, 46);\n\tgpio_direction_input(priv->eedi);\n\tadm6996_gpio_adclk(priv, 2);\n\tadm6996_gpio_read(priv, 0, rbits, 32);\n\n\t/* Extra clock(s) required per datasheet */\n\tadm6996_gpio_adclk(priv, 2);\n\n\t/* Disable GPIO outputs */\n\tgpio_direction_input(priv->eecs);\n\tgpio_direction_input(priv->eesk);\n\n\t /* EEPROM has 16-bit registers, but pumps out two registers in one request */\n\treturn (reg & 0x01 ?  (rbits[0]<<8) | rbits[1] : (rbits[2]<<8) | (rbits[3]));\n}\n\n/* Write chip configuration register */\n/* Follow 93c66 timing and chip's min EEPROM timing requirement */\nstatic void\nadm6996_write_gpio_reg(struct adm6996_priv *priv, enum admreg reg, u16 val)\n{\n\t/* cmd(27bits): sb(1) + opc(01) + addr(bbbbbbbb) + data(bbbbbbbbbbbbbbbb) */\n\tu8 bits[4] = {\n\t\t(0x05 << 5) | (reg >> 3),\n\t\t(reg << 5) | (u8)(val >> 11),\n\t\t(u8)(val >> 3),\n\t\t(u8)(val << 5)\n\t};\n\n\t/* Enable GPIO outputs with all pins to 0 */\n\tgpio_direction_output(priv->eecs, 0);\n\tgpio_direction_output(priv->eesk, 0);\n\tgpio_direction_output(priv->eedi, 0);\n\n\t/* Write cmd. Total 27 bits */\n\tadm6996_gpio_write(priv, 1, bits, 27);\n\n\t/* Extra clock(s) required per datasheet */\n\tadm6996_gpio_adclk(priv, 2);\n\n\t/* Disable GPIO outputs */\n\tgpio_direction_input(priv->eecs);\n\tgpio_direction_input(priv->eesk);\n\tgpio_direction_input(priv->eedi);\n}\n\nstatic u16\nadm6996_read_mii_reg(struct adm6996_priv *priv, enum admreg reg)\n{\n\tstruct phy_device *phydev = priv->priv;\n\tstruct mii_bus *bus = phydev->mdio.bus;\n\n\treturn bus->read(bus, PHYADDR(reg));\n}\n\nstatic void\nadm6996_write_mii_reg(struct adm6996_priv *priv, enum admreg reg, u16 val)\n{\n\tstruct phy_device *phydev = priv->priv;\n\tstruct mii_bus *bus = phydev->mdio.bus;\n\n\tbus->write(bus, PHYADDR(reg), val);\n}\n\nstatic int\nadm6996_set_enable_vlan(struct switch_dev *dev, const struct switch_attr *attr,\n\t\t\tstruct switch_val *val)\n{\n\tstruct adm6996_priv *priv = to_adm(dev);\n\n\tif (val->value.i > 1)\n\t\treturn -EINVAL;\n\n\tpriv->enable_vlan = val->value.i;\n\n\treturn 0;\n};\n\nstatic int\nadm6996_get_enable_vlan(struct switch_dev *dev, const struct switch_attr *attr,\n\t\t\tstruct switch_val *val)\n{\n\tstruct adm6996_priv *priv = to_adm(dev);\n\n\tval->value.i = priv->enable_vlan;\n\n\treturn 0;\n};\n\n#ifdef DEBUG\n\nstatic int\nadm6996_set_addr(struct switch_dev *dev, const struct switch_attr *attr,\n\t\t struct switch_val *val)\n{\n\tstruct adm6996_priv *priv = to_adm(dev);\n\n\tif (val->value.i > 1023)\n\t\treturn -EINVAL;\n\n\tpriv->addr = val->value.i;\n\n\treturn 0;\n};\n\nstatic int\nadm6996_get_addr(struct switch_dev *dev, const struct switch_attr *attr,\n\t\t struct switch_val *val)\n{\n\tstruct adm6996_priv *priv = to_adm(dev);\n\n\tval->value.i = priv->addr;\n\n\treturn 0;\n};\n\nstatic int\nadm6996_set_data(struct switch_dev *dev, const struct switch_attr *attr,\n\t\t struct switch_val *val)\n{\n\tstruct adm6996_priv *priv = to_adm(dev);\n\n\tif (val->value.i > 65535)\n\t\treturn -EINVAL;\n\n\tw16(priv, priv->addr, val->value.i);\n\n\treturn 0;\n};\n\nstatic int\nadm6996_get_data(struct switch_dev *dev, const struct switch_attr *attr,\n\t\t struct switch_val *val)\n{\n\tstruct adm6996_priv *priv = to_adm(dev);\n\n\tval->value.i = r16(priv, priv->addr);\n\n\treturn 0;\n};\n\n#endif /* def DEBUG */\n\nstatic int\nadm6996_set_pvid(struct switch_dev *dev, int port, int vlan)\n{\n\tstruct adm6996_priv *priv = to_adm(dev);\n\n\tpr_devel(\"set_pvid port %d vlan %d\\n\", port, vlan);\n\n\tif (vlan > ADM_VLAN_MAX_ID)\n\t\treturn -EINVAL;\n\n\tpriv->pvid[port] = vlan;\n\n\treturn 0;\n}\n\nstatic int\nadm6996_get_pvid(struct switch_dev *dev, int port, int *vlan)\n{\n\tstruct adm6996_priv *priv = to_adm(dev);\n\n\tpr_devel(\"get_pvid port %d\\n\", port);\n\t*vlan = priv->pvid[port];\n\n\treturn 0;\n}\n\nstatic int\nadm6996_set_vid(struct switch_dev *dev, const struct switch_attr *attr,\n\t\tstruct switch_val *val)\n{\n\tstruct adm6996_priv *priv = to_adm(dev);\n\n\tpr_devel(\"set_vid port %d vid %d\\n\", val->port_vlan, val->value.i);\n\n\tif (val->value.i > ADM_VLAN_MAX_ID)\n\t\treturn -EINVAL;\n\n\tpriv->vlan_id[val->port_vlan] = val->value.i;\n\n\treturn 0;\n};\n\nstatic int\nadm6996_get_vid(struct switch_dev *dev, const struct switch_attr *attr,\n\t\tstruct switch_val *val)\n{\n\tstruct adm6996_priv *priv = to_adm(dev);\n\n\tpr_devel(\"get_vid port %d\\n\", val->port_vlan);\n\n\tval->value.i = priv->vlan_id[val->port_vlan];\n\n\treturn 0;\n};\n\nstatic int\nadm6996_get_ports(struct switch_dev *dev, struct switch_val *val)\n{\n\tstruct adm6996_priv *priv = to_adm(dev);\n\tu8 ports = priv->vlan_table[val->port_vlan];\n\tu8 tagged = priv->vlan_tagged[val->port_vlan];\n\tint i;\n\n\tpr_devel(\"get_ports port_vlan %d\\n\", val->port_vlan);\n\n\tval->len = 0;\n\n\tfor (i = 0; i < ADM_NUM_PORTS; i++) {\n\t\tstruct switch_port *p;\n\n\t\tif (!(ports & (1 << i)))\n\t\t\tcontinue;\n\n\t\tp = &val->value.ports[val->len++];\n\t\tp->id = i;\n\t\tif (tagged & (1 << i))\n\t\t\tp->flags = (1 << SWITCH_PORT_FLAG_TAGGED);\n\t\telse\n\t\t\tp->flags = 0;\n\t}\n\n\treturn 0;\n};\n\nstatic int\nadm6996_set_ports(struct switch_dev *dev, struct switch_val *val)\n{\n\tstruct adm6996_priv *priv = to_adm(dev);\n\tu8 *ports = &priv->vlan_table[val->port_vlan];\n\tu8 *tagged = &priv->vlan_tagged[val->port_vlan];\n\tint i;\n\n\tpr_devel(\"set_ports port_vlan %d ports\", val->port_vlan);\n\n\t*ports = 0;\n\t*tagged = 0;\n\n\tfor (i = 0; i < val->len; i++) {\n\t\tstruct switch_port *p = &val->value.ports[i];\n\n#ifdef DEBUG\n\t\tpr_cont(\" %d%s\", p->id,\n\t\t       ((p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) ? \"T\" :\n\t\t\t\"\"));\n#endif\n\n\t\tif (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) {\n\t\t\t*tagged |= (1 << p->id);\n\t\t\tpriv->tagged_ports |= (1 << p->id);\n\t\t}\n\n\t\t*ports |= (1 << p->id);\n\t}\n\n#ifdef DEBUG\n\tpr_cont(\"\\n\");\n#endif\n\n\treturn 0;\n};\n\n/*\n * Precondition: reg_mutex must be held\n */\nstatic void\nadm6996_enable_vlan(struct adm6996_priv *priv)\n{\n\tu16 reg;\n\n\treg = r16(priv, ADM_OTBE_P2_PVID);\n\treg &= ~(ADM_OTBE_MASK);\n\tw16(priv, ADM_OTBE_P2_PVID, reg);\n\treg = r16(priv, ADM_IFNTE);\n\treg &= ~(ADM_IFNTE_MASK);\n\tw16(priv, ADM_IFNTE, reg);\n\treg = r16(priv, ADM_VID_CHECK);\n\treg |= ADM_VID_CHECK_MASK;\n\tw16(priv, ADM_VID_CHECK, reg);\n\treg = r16(priv, ADM_SYSC0);\n\treg |= ADM_NTTE;\n\treg &= ~(ADM_RVID1);\n\tw16(priv, ADM_SYSC0, reg);\n\treg = r16(priv, ADM_SYSC3);\n\treg |= ADM_TBV;\n\tw16(priv, ADM_SYSC3, reg);\n}\n\nstatic void\nadm6996_enable_vlan_6996l(struct adm6996_priv *priv)\n{\n\tu16 reg;\n\n\treg = r16(priv, ADM_SYSC3);\n\treg |= ADM_TBV;\n\treg |= ADM_MAC_CLONE;\n\tw16(priv, ADM_SYSC3, reg);\n}\n\n/*\n * Disable VLANs\n *\n * Sets VLAN mapping for port-based VLAN with all ports connected to\n * eachother (this is also the power-on default).\n *\n * Precondition: reg_mutex must be held\n */\nstatic void\nadm6996_disable_vlan(struct adm6996_priv *priv)\n{\n\tu16 reg;\n\tint i;\n\n\tfor (i = 0; i < ADM_NUM_VLANS; i++) {\n\t\treg = ADM_VLAN_FILT_MEMBER_MASK;\n\t\tw16(priv, ADM_VLAN_FILT_L(i), reg);\n\t\treg = ADM_VLAN_FILT_VALID | ADM_VLAN_FILT_VID(1);\n\t\tw16(priv, ADM_VLAN_FILT_H(i), reg);\n\t}\n\n\treg = r16(priv, ADM_OTBE_P2_PVID);\n\treg |= ADM_OTBE_MASK;\n\tw16(priv, ADM_OTBE_P2_PVID, reg);\n\treg = r16(priv, ADM_IFNTE);\n\treg |= ADM_IFNTE_MASK;\n\tw16(priv, ADM_IFNTE, reg);\n\treg = r16(priv, ADM_VID_CHECK);\n\treg &= ~(ADM_VID_CHECK_MASK);\n\tw16(priv, ADM_VID_CHECK, reg);\n\treg = r16(priv, ADM_SYSC0);\n\treg &= ~(ADM_NTTE);\n\treg |= ADM_RVID1;\n\tw16(priv, ADM_SYSC0, reg);\n\treg = r16(priv, ADM_SYSC3);\n\treg &= ~(ADM_TBV);\n\tw16(priv, ADM_SYSC3, reg);\n}\n\n/*\n * Disable VLANs\n *\n * Sets VLAN mapping for port-based VLAN with all ports connected to\n * eachother (this is also the power-on default).\n *\n * Precondition: reg_mutex must be held\n */\nstatic void\nadm6996_disable_vlan_6996l(struct adm6996_priv *priv)\n{\n\tu16 reg;\n\tint i;\n\n\tfor (i = 0; i < ADM_NUM_VLANS; i++) {\n\t\tw16(priv, ADM_VLAN_MAP(i), 0);\n\t}\n\n\treg = r16(priv, ADM_SYSC3);\n\treg &= ~(ADM_TBV);\n\treg &= ~(ADM_MAC_CLONE);\n\tw16(priv, ADM_SYSC3, reg);\n}\n\n/*\n * Precondition: reg_mutex must be held\n */\nstatic void\nadm6996_apply_port_pvids(struct adm6996_priv *priv)\n{\n\tu16 reg;\n\tint i;\n\n\tfor (i = 0; i < ADM_NUM_PORTS; i++) {\n\t\treg = r16(priv, adm_portcfg[i]);\n\t\treg &= ~(ADM_PORTCFG_PVID_MASK);\n\t\treg |= ADM_PORTCFG_PVID(priv->pvid[i]);\n\t\tif (priv->model == ADM6996L) {\n\t\t\tif (priv->tagged_ports & (1 << i))\n\t\t\t\treg |= (1 << 4);\n\t\t\telse\n\t\t\t\treg &= ~(1 << 4);\n\t\t}\n\t\tw16(priv, adm_portcfg[i], reg);\n\t}\n\n\tw16(priv, ADM_P0_PVID, ADM_P0_PVID_VAL(priv->pvid[0]));\n\tw16(priv, ADM_P1_PVID, ADM_P1_PVID_VAL(priv->pvid[1]));\n\treg = r16(priv, ADM_OTBE_P2_PVID);\n\treg &= ~(ADM_P2_PVID_MASK);\n\treg |= ADM_P2_PVID_VAL(priv->pvid[2]);\n\tw16(priv, ADM_OTBE_P2_PVID, reg);\n\treg = ADM_P3_PVID_VAL(priv->pvid[3]);\n\treg |= ADM_P4_PVID_VAL(priv->pvid[4]);\n\tw16(priv, ADM_P3_P4_PVID, reg);\n\treg = r16(priv, ADM_P5_PVID);\n\treg &= ~(ADM_P2_PVID_MASK);\n\treg |= ADM_P5_PVID_VAL(priv->pvid[5]);\n\tw16(priv, ADM_P5_PVID, reg);\n}\n\n/*\n * Precondition: reg_mutex must be held\n */\nstatic void\nadm6996_apply_vlan_filters(struct adm6996_priv *priv)\n{\n\tu8 ports, tagged;\n\tu16 vid, reg;\n\tint i;\n\n\tfor (i = 0; i < ADM_NUM_VLANS; i++) {\n\t\tvid = priv->vlan_id[i];\n\t\tports = priv->vlan_table[i];\n\t\ttagged = priv->vlan_tagged[i];\n\n\t\tif (ports == 0) {\n\t\t\t/* Disable VLAN entry */\n\t\t\tw16(priv, ADM_VLAN_FILT_H(i), 0);\n\t\t\tw16(priv, ADM_VLAN_FILT_L(i), 0);\n\t\t\tcontinue;\n\t\t}\n\n\t\treg = ADM_VLAN_FILT_MEMBER(ports);\n\t\treg |= ADM_VLAN_FILT_TAGGED(tagged);\n\t\tw16(priv, ADM_VLAN_FILT_L(i), reg);\n\t\treg = ADM_VLAN_FILT_VALID | ADM_VLAN_FILT_VID(vid);\n\t\tw16(priv, ADM_VLAN_FILT_H(i), reg);\n\t}\n}\n\nstatic void\nadm6996_apply_vlan_filters_6996l(struct adm6996_priv *priv)\n{\n\tu8 ports;\n\tu16 reg;\n\tint i;\n\n\tfor (i = 0; i < ADM_NUM_VLANS; i++) {\n\t\tports = priv->vlan_table[i];\n\n\t\tif (ports == 0) {\n\t\t\t/* Disable VLAN entry */\n\t\t\tw16(priv, ADM_VLAN_MAP(i), 0);\n\t\t\tcontinue;\n\t\t} else {\n\t\t\treg = ADM_VLAN_FILT(ports);\n\t\t\tw16(priv, ADM_VLAN_MAP(i), reg);\n\t\t}\n\t}\n}\n\nstatic int\nadm6996_hw_apply(struct switch_dev *dev)\n{\n\tstruct adm6996_priv *priv = to_adm(dev);\n\n\tpr_devel(\"hw_apply\\n\");\n\n\tmutex_lock(&priv->reg_mutex);\n\n\tif (!priv->enable_vlan) {\n\t\tif (priv->vlan_enabled) {\n\t\t\tif (priv->model == ADM6996L)\n\t\t\t\tadm6996_disable_vlan_6996l(priv);\n\t\t\telse\n\t\t\t\tadm6996_disable_vlan(priv);\n\t\t\tpriv->vlan_enabled = 0;\n\t\t}\n\t\tgoto out;\n\t}\n\n\tif (!priv->vlan_enabled) {\n\t\tif (priv->model == ADM6996L)\n\t\t\tadm6996_enable_vlan_6996l(priv);\n\t\telse\n\t\t\tadm6996_enable_vlan(priv);\n\t\tpriv->vlan_enabled = 1;\n\t}\n\n\tadm6996_apply_port_pvids(priv);\n\tif (priv->model == ADM6996L)\n\t\tadm6996_apply_vlan_filters_6996l(priv);\n\telse\n\t\tadm6996_apply_vlan_filters(priv);\n\nout:\n\tmutex_unlock(&priv->reg_mutex);\n\n\treturn 0;\n}\n\n/*\n * Reset the switch\n *\n * The ADM6996 can't do a software-initiated reset, so we just initialise the\n * registers we support in this driver.\n *\n * Precondition: reg_mutex must be held\n */\nstatic void\nadm6996_perform_reset (struct adm6996_priv *priv)\n{\n\tint i;\n\n\t/* initialize port and vlan settings */\n\tfor (i = 0; i < ADM_NUM_PORTS - 1; i++) {\n\t\tw16(priv, adm_portcfg[i], ADM_PORTCFG_INIT |\n\t\t\tADM_PORTCFG_PVID(0));\n\t}\n\tw16(priv, adm_portcfg[5], ADM_PORTCFG_CPU);\n\n\tif (priv->model == ADM6996M || priv->model == ADM6996FC) {\n\t\t/* reset all PHY ports */\n\t\tfor (i = 0; i < ADM_PHY_PORTS; i++) {\n\t\t\tw16(priv, ADM_PHY_PORT(i), ADM_PHYCFG_INIT);\n\t\t}\n\t}\n\n\tpriv->enable_vlan = 0;\n\tpriv->vlan_enabled = 0;\n\n\tfor (i = 0; i < ADM_NUM_PORTS; i++) {\n\t\tpriv->pvid[i] = 0;\n\t}\n\n\tfor (i = 0; i < ADM_NUM_VLANS; i++) {\n\t\tpriv->vlan_id[i] = i;\n\t\tpriv->vlan_table[i] = 0;\n\t\tpriv->vlan_tagged[i] = 0;\n\t}\n\n\tif (priv->model == ADM6996M) {\n\t\t/* Clear VLAN priority map so prio's are unused */\n\t\tw16 (priv, ADM_VLAN_PRIOMAP, 0);\n\n\t\tadm6996_disable_vlan(priv);\n\t\tadm6996_apply_port_pvids(priv);\n\t} else if (priv->model == ADM6996L) {\n\t\t/* Clear VLAN priority map so prio's are unused */\n\t\tw16 (priv, ADM_VLAN_PRIOMAP, 0);\n\n\t\tadm6996_disable_vlan_6996l(priv);\n\t\tadm6996_apply_port_pvids(priv);\n\t}\n}\n\nstatic int\nadm6996_reset_switch(struct switch_dev *dev)\n{\n\tstruct adm6996_priv *priv = to_adm(dev);\n\n\tpr_devel(\"reset\\n\");\n\n\tmutex_lock(&priv->reg_mutex);\n\tadm6996_perform_reset (priv);\n\tmutex_unlock(&priv->reg_mutex);\n\treturn 0;\n}\n\nstatic int\nadm6996_get_port_link(struct switch_dev *dev, int port,\n\t\tstruct switch_port_link *link)\n{\n\tstruct adm6996_priv *priv = to_adm(dev);\n\t\n\tu16 reg = 0;\n\t\n\tif (port >= ADM_NUM_PORTS)\n\t\treturn -EINVAL;\n\t\n\tswitch (port) {\n\tcase 0:\n\t\treg = r16(priv, ADM_PS0);\n\t\tbreak;\n\tcase 1:\n\t\treg = r16(priv, ADM_PS0);\n\t\treg = reg >> 8;\n\t\tbreak;\n\tcase 2:\n\t\treg = r16(priv, ADM_PS1);\n\t\tbreak;\n\tcase 3:\n\t\treg = r16(priv, ADM_PS1);\n\t\treg = reg >> 8;\n\t\tbreak;\n\tcase 4:\n\t\treg = r16(priv, ADM_PS1);\n\t\treg = reg >> 12;\n\t\tbreak;\n\tcase 5:\n\t\treg = r16(priv, ADM_PS2);\n\t\t/* Bits 0, 1, 3 and 4. */\n\t\treg = (reg & 3) | ((reg & 24) >> 1);\n\t\tbreak;\n\tdefault:\n\t\treturn -EINVAL;\n\t}\n\t\n\tlink->link = reg & ADM_PS_LS;\n\tif (!link->link)\n\t\treturn 0;\n\tlink->aneg = true;\n\tlink->duplex = reg & ADM_PS_DS;\n\tlink->tx_flow = reg & ADM_PS_FCS;\n\tlink->rx_flow = reg & ADM_PS_FCS;\n\tif (reg & ADM_PS_SS)\n\t\tlink->speed = SWITCH_PORT_SPEED_100;\n\telse\n\t\tlink->speed = SWITCH_PORT_SPEED_10;\n\n\treturn 0;\n}\n\nstatic int\nadm6996_sw_get_port_mib(struct switch_dev *dev,\n\t\t       const struct switch_attr *attr,\n\t\t       struct switch_val *val)\n{\n\tstruct adm6996_priv *priv = to_adm(dev);\n\tint port;\n\tchar *buf = priv->buf;\n\tint i, len = 0;\n\tu32 reg = 0;\n\n\tport = val->port_vlan;\n\tif (port >= ADM_NUM_PORTS)\n\t\treturn -EINVAL;\n\n\tmutex_lock(&priv->mib_lock);\n\n\tlen += snprintf(buf + len, sizeof(priv->buf) - len,\n\t\t\t\"Port %d MIB counters\\n\",\n\t\t\tport);\n\n\tfor (i = 0; i < ARRAY_SIZE(adm6996_mibs); i++) {\n\t\treg = r16(priv, adm6996_mibs[i].offset + ADM_OFFSET_PORT(port));\n\t\treg += r16(priv, adm6996_mibs[i].offset + ADM_OFFSET_PORT(port) + 1) << 16;\n\t\tlen += snprintf(buf + len, sizeof(priv->buf) - len,\n\t\t\t\t\"%-12s: %u\\n\",\n\t\t\t\tadm6996_mibs[i].name,\n\t\t\t\treg);\n\t}\n\n\tmutex_unlock(&priv->mib_lock);\n\n\tval->value.s = buf;\n\tval->len = len;\n\n\treturn 0;\n}\n\nstatic int\nadm6996_get_port_stats(struct switch_dev *dev, int port,\n\t\t\tstruct switch_port_stats *stats)\n{\n\tstruct adm6996_priv *priv = to_adm(dev);\n\tint id;\n\tu32 reg = 0;\n\n\tif (port >= ADM_NUM_PORTS)\n\t\treturn -EINVAL;\n\n\tmutex_lock(&priv->mib_lock);\n\n\tid = ADM6996_MIB_TXB_ID;\n\treg = r16(priv, adm6996_mibs[id].offset + ADM_OFFSET_PORT(port));\n\treg += r16(priv, adm6996_mibs[id].offset + ADM_OFFSET_PORT(port) + 1) << 16;\n\tstats->tx_bytes = reg;\n\n\tid = ADM6996_MIB_RXB_ID;\n\treg = r16(priv, adm6996_mibs[id].offset + ADM_OFFSET_PORT(port));\n\treg += r16(priv, adm6996_mibs[id].offset + ADM_OFFSET_PORT(port) + 1) << 16;\n\tstats->rx_bytes = reg;\n\n\tmutex_unlock(&priv->mib_lock);\n\n\treturn 0;\n}\n\nstatic struct switch_attr adm6996_globals[] = {\n\t{\n\t .type = SWITCH_TYPE_INT,\n\t .name = \"enable_vlan\",\n\t .description = \"Enable VLANs\",\n\t .set = adm6996_set_enable_vlan,\n\t .get = adm6996_get_enable_vlan,\n\t},\n#ifdef DEBUG\n\t{\n\t .type = SWITCH_TYPE_INT,\n\t .name = \"addr\",\n\t .description =\n\t \"Direct register access: set register address (0 - 1023)\",\n\t .set = adm6996_set_addr,\n\t .get = adm6996_get_addr,\n\t },\n\t{\n\t .type = SWITCH_TYPE_INT,\n\t .name = \"data\",\n\t .description =\n\t \"Direct register access: read/write to register (0 - 65535)\",\n\t .set = adm6996_set_data,\n\t .get = adm6996_get_data,\n\t },\n#endif /* def DEBUG */\n};\n\nstatic struct switch_attr adm6996_port[] = {\n\t{\n\t .type = SWITCH_TYPE_STRING,\n\t .name = \"mib\",\n\t .description = \"Get port's MIB counters\",\n\t .set = NULL,\n\t .get = adm6996_sw_get_port_mib,\n\t},\n};\n\nstatic struct switch_attr adm6996_vlan[] = {\n\t{\n\t .type = SWITCH_TYPE_INT,\n\t .name = \"vid\",\n\t .description = \"VLAN ID\",\n\t .set = adm6996_set_vid,\n\t .get = adm6996_get_vid,\n\t },\n};\n\nstatic struct switch_dev_ops adm6996_ops = {\n\t.attr_global = {\n\t\t\t.attr = adm6996_globals,\n\t\t\t.n_attr = ARRAY_SIZE(adm6996_globals),\n\t\t\t},\n\t.attr_port = {\n\t\t      .attr = adm6996_port,\n\t\t      .n_attr = ARRAY_SIZE(adm6996_port),\n\t\t      },\n\t.attr_vlan = {\n\t\t      .attr = adm6996_vlan,\n\t\t      .n_attr = ARRAY_SIZE(adm6996_vlan),\n\t\t      },\n\t.get_port_pvid = adm6996_get_pvid,\n\t.set_port_pvid = adm6996_set_pvid,\n\t.get_vlan_ports = adm6996_get_ports,\n\t.set_vlan_ports = adm6996_set_ports,\n\t.apply_config = adm6996_hw_apply,\n\t.reset_switch = adm6996_reset_switch,\n\t.get_port_link = adm6996_get_port_link,\n\t.get_port_stats = adm6996_get_port_stats,\n};\n\nstatic int adm6996_switch_init(struct adm6996_priv *priv, const char *alias, struct net_device *netdev)\n{\n\tstruct switch_dev *swdev;\n\tu16 test, old;\n\n\tif (!priv->model) {\n\t\t/* Detect type of chip */\n\t\told = r16(priv, ADM_VID_CHECK);\n\t\ttest = old ^ (1 << 12);\n\t\tw16(priv, ADM_VID_CHECK, test);\n\t\ttest ^= r16(priv, ADM_VID_CHECK);\n\t\tif (test & (1 << 12)) {\n\t\t\t/* \n\t\t\t * Bit 12 of this register is read-only. \n\t\t\t * This is the FC model. \n\t\t\t */\n\t\t\tpriv->model = ADM6996FC;\n\t\t} else {\n\t\t\t/* Bit 12 is read-write. This is the M model. */\n\t\t\tpriv->model = ADM6996M;\n\t\t\tw16(priv, ADM_VID_CHECK, old);\n\t\t}\n\t}\n\n\tswdev = &priv->dev;\n\tswdev->name = (adm6996_model_name[priv->model]);\n\tswdev->cpu_port = ADM_CPU_PORT;\n\tswdev->ports = ADM_NUM_PORTS;\n\tswdev->vlans = ADM_NUM_VLANS;\n\tswdev->ops = &adm6996_ops;\n\tswdev->alias = alias;\n\n\t/* The ADM6996L connected through GPIOs does not support any switch\n\t   status calls */\n\tif (priv->model == ADM6996L) {\n\t\tadm6996_ops.attr_port.n_attr = 0;\n\t\tadm6996_ops.get_port_link = NULL;\n\t}\n\n\tpr_info (\"%s: %s model PHY found.\\n\", alias, swdev->name);\n\n\tmutex_lock(&priv->reg_mutex);\n\tadm6996_perform_reset (priv);\n\tmutex_unlock(&priv->reg_mutex);\n\n\tif (priv->model == ADM6996M || priv->model == ADM6996L) {\n\t\treturn register_switch(swdev, netdev);\n\t}\n\n\treturn -ENODEV;\n}\n\nstatic int adm6996_config_init(struct phy_device *pdev)\n{\n\tstruct adm6996_priv *priv;\n\tint ret;\n\n\tlinkmode_zero(pdev->supported);\n\tlinkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, pdev->supported);\n\tlinkmode_copy(pdev->advertising, pdev->supported);\n\n\tif (pdev->mdio.addr != 0) {\n\t\tpr_info (\"%s: PHY overlaps ADM6996, providing fixed PHY 0x%x.\\n\"\n\t\t\t\t, pdev->attached_dev->name, pdev->mdio.addr);\n\t\treturn 0;\n\t}\n\n\tpriv = devm_kzalloc(&pdev->mdio.dev, sizeof(struct adm6996_priv), GFP_KERNEL);\n\tif (!priv)\n\t\treturn -ENOMEM;\n\n\tmutex_init(&priv->reg_mutex);\n\tmutex_init(&priv->mib_lock);\n\tpriv->priv = pdev;\n\tpriv->read = adm6996_read_mii_reg;\n\tpriv->write = adm6996_write_mii_reg;\n\n\tret = adm6996_switch_init(priv, pdev->attached_dev->name, pdev->attached_dev);\n\tif (ret < 0)\n\t\treturn ret;\n\n\tpdev->priv = priv;\n\n\treturn 0;\n}\n\n/*\n * Warning: phydev->priv is NULL if phydev->mdio.addr != 0\n */\nstatic int adm6996_read_status(struct phy_device *phydev)\n{\n\tphydev->speed = SPEED_100;\n\tphydev->duplex = DUPLEX_FULL;\n\tphydev->link = 1;\n\n\tphydev->state = PHY_RUNNING;\n\tnetif_carrier_on(phydev->attached_dev);\n\tphydev->adjust_link(phydev->attached_dev);\n\n\treturn 0;\n}\n\n/*\n * Warning: phydev->priv is NULL if phydev->mdio.addr != 0\n */\nstatic int adm6996_config_aneg(struct phy_device *phydev)\n{\n\treturn 0;\n}\n\nstatic int adm6996_fixup(struct phy_device *dev)\n{\n\tstruct mii_bus *bus = dev->mdio.bus;\n\tu16 reg;\n\n\t/* Our custom registers are at PHY addresses 0-10. Claim those. */\n\tif (dev->mdio.addr > 10)\n\t\treturn 0;\n\n\t/* look for the switch on the bus */\n\treg = bus->read(bus, PHYADDR(ADM_SIG0)) & ADM_SIG0_MASK;\n\tif (reg != ADM_SIG0_VAL)\n\t\treturn 0;\n\n\treg = bus->read(bus, PHYADDR(ADM_SIG1)) & ADM_SIG1_MASK;\n\tif (reg != ADM_SIG1_VAL)\n\t\treturn 0;\n\n\tdev->phy_id = (ADM_SIG0_VAL << 16) | ADM_SIG1_VAL;\n\n\treturn 0;\n}\n\nstatic int adm6996_probe(struct phy_device *pdev)\n{\n\treturn 0;\n}\n\nstatic void adm6996_remove(struct phy_device *pdev)\n{\n\tstruct adm6996_priv *priv = phy_to_adm(pdev);\n\n\tif (priv && (priv->model == ADM6996M || priv->model == ADM6996L))\n\t\tunregister_switch(&priv->dev);\n}\n\nstatic int adm6996_soft_reset(struct phy_device *phydev)\n{\n\t/* we don't need an extra reset */\n\treturn 0;\n}\n\nstatic struct phy_driver adm6996_phy_driver = {\n\t.name\t\t= \"Infineon ADM6996\",\n\t.phy_id\t\t= (ADM_SIG0_VAL << 16) | ADM_SIG1_VAL,\n\t.phy_id_mask\t= 0xffffffff,\n\t.features\t= PHY_BASIC_FEATURES,\n\t.probe\t\t= adm6996_probe,\n\t.remove\t\t= adm6996_remove,\n\t.config_init\t= &adm6996_config_init,\n\t.config_aneg\t= &adm6996_config_aneg,\n\t.read_status\t= &adm6996_read_status,\n\t.soft_reset\t= adm6996_soft_reset,\n};\n\nstatic int adm6996_gpio_probe(struct platform_device *pdev)\n{\n\tstruct adm6996_gpio_platform_data *pdata = pdev->dev.platform_data;\n\tstruct adm6996_priv *priv;\n\tint ret;\n\n\tif (!pdata)\n\t\treturn -EINVAL;\n\n\tpriv = devm_kzalloc(&pdev->dev, sizeof(struct adm6996_priv), GFP_KERNEL);\n\tif (!priv)\n\t\treturn -ENOMEM;\n\n\tmutex_init(&priv->reg_mutex);\n\tmutex_init(&priv->mib_lock);\n\n\tpriv->eecs = pdata->eecs;\n\tpriv->eedi = pdata->eedi;\n\tpriv->eesk = pdata->eesk;\n\n\tpriv->model = pdata->model;\n\tpriv->read = adm6996_read_gpio_reg;\n\tpriv->write = adm6996_write_gpio_reg;\n\n\tret = devm_gpio_request(&pdev->dev, priv->eecs, \"adm_eecs\");\n\tif (ret)\n\t\treturn ret;\n\tret = devm_gpio_request(&pdev->dev, priv->eedi, \"adm_eedi\");\n\tif (ret)\n\t\treturn ret;\n\tret = devm_gpio_request(&pdev->dev, priv->eesk, \"adm_eesk\");\n\tif (ret)\n\t\treturn ret;\n\n\tret = adm6996_switch_init(priv, dev_name(&pdev->dev), NULL);\n\tif (ret < 0)\n\t\treturn ret;\n\n\tplatform_set_drvdata(pdev, priv);\n\n\treturn 0;\n}\n\nstatic int adm6996_gpio_remove(struct platform_device *pdev)\n{\n\tstruct adm6996_priv *priv = platform_get_drvdata(pdev);\n\n\tif (priv && (priv->model == ADM6996M || priv->model == ADM6996L))\n\t\tunregister_switch(&priv->dev);\n\n\treturn 0;\n}\n\nstatic struct platform_driver adm6996_gpio_driver = {\n\t.probe = adm6996_gpio_probe,\n\t.remove = adm6996_gpio_remove,\n\t.driver = {\n\t\t.name = \"adm6996_gpio\",\n\t},\n};\n\nstatic int __init adm6996_init(void)\n{\n\tint err;\n\n\tphy_register_fixup_for_id(PHY_ANY_ID, adm6996_fixup);\n\terr = phy_driver_register(&adm6996_phy_driver, THIS_MODULE);\n\tif (err)\n\t\treturn err;\n\n\terr = platform_driver_register(&adm6996_gpio_driver);\n\tif (err)\n\t\tphy_driver_unregister(&adm6996_phy_driver);\n\n\treturn err;\n}\n\nstatic void __exit adm6996_exit(void)\n{\n\tplatform_driver_unregister(&adm6996_gpio_driver);\n\tphy_driver_unregister(&adm6996_phy_driver);\n}\n\nmodule_init(adm6996_init);\nmodule_exit(adm6996_exit);\n"
  },
  {
    "path": "target/linux/generic/files/drivers/net/phy/adm6996.h",
    "content": "/*\n * ADM6996 switch driver\n *\n * Copyright (c) 2008 Felix Fietkau <nbd@nbd.name>\n * Copyright (c) 2010,2011 Peter Lebbing <peter@digitalbrains.com>\n *\n * This program is free software; you can redistribute  it and/or modify it\n * under  the terms of the GNU General Public License v2 as published by the\n * Free Software Foundation\n */\n#ifndef __ADM6996_H\n#define __ADM6996_H\n\n/*\n * ADM_PHY_PORTS: Number of ports with a PHY.\n * We only control ports 0 to 3, because if 4 is connected, it is most likely\n * not connected to the switch but to a separate MII and MAC for the WAN port.\n */\n#define ADM_PHY_PORTS\t4\n#define ADM_NUM_PORTS\t6\n#define ADM_CPU_PORT\t5\n\n#define ADM_NUM_VLANS 16\n#define ADM_VLAN_MAX_ID 4094\n\nenum admreg {\n\tADM_EEPROM_BASE\t\t= 0x0,\n\t\tADM_P0_CFG\t\t= ADM_EEPROM_BASE + 1,\n\t\tADM_P1_CFG\t\t= ADM_EEPROM_BASE + 3,\n\t\tADM_P2_CFG\t\t= ADM_EEPROM_BASE + 5,\n\t\tADM_P3_CFG\t\t= ADM_EEPROM_BASE + 7,\n\t\tADM_P4_CFG\t\t= ADM_EEPROM_BASE + 8,\n\t\tADM_P5_CFG\t\t= ADM_EEPROM_BASE + 9,\n\t\tADM_SYSC0\t\t= ADM_EEPROM_BASE + 0xa,\n\t\tADM_VLAN_PRIOMAP\t= ADM_EEPROM_BASE + 0xe,\n\t\tADM_SYSC3\t\t= ADM_EEPROM_BASE + 0x11,\n\t\t/* Input Force No Tag Enable */\n\t\tADM_IFNTE\t\t= ADM_EEPROM_BASE + 0x20,\n\t\tADM_VID_CHECK\t\t= ADM_EEPROM_BASE + 0x26,\n\t\tADM_P0_PVID\t\t= ADM_EEPROM_BASE + 0x28,\n\t\tADM_P1_PVID\t\t= ADM_EEPROM_BASE + 0x29,\n\t\t/* Output Tag Bypass Enable and P2 PVID */\n\t\tADM_OTBE_P2_PVID\t= ADM_EEPROM_BASE + 0x2a,\n\t\tADM_P3_P4_PVID\t\t= ADM_EEPROM_BASE + 0x2b,\n\t\tADM_P5_PVID\t\t= ADM_EEPROM_BASE + 0x2c,\n\tADM_EEPROM_EXT_BASE\t= 0x40,\n#define ADM_VLAN_FILT_L(n) (ADM_EEPROM_EXT_BASE + 2 * (n))\n#define ADM_VLAN_FILT_H(n) (ADM_EEPROM_EXT_BASE + 1 + 2 * (n))\n#define ADM_VLAN_MAP(n) (ADM_EEPROM_BASE + 0x13 + n)\n\tADM_COUNTER_BASE\t= 0xa0,\n\t\tADM_SIG0\t\t= ADM_COUNTER_BASE + 0,\n\t\tADM_SIG1\t\t= ADM_COUNTER_BASE + 1,\n\t\tADM_PS0\t\t= ADM_COUNTER_BASE + 2,\n\t\tADM_PS1\t\t= ADM_COUNTER_BASE + 3,\n\t\tADM_PS2\t\t= ADM_COUNTER_BASE + 4,\n\t\tADM_CL0\t\t= ADM_COUNTER_BASE + 8, /* RxPacket */\n\t\tADM_CL6\t\t= ADM_COUNTER_BASE + 0x1a, /* RxByte */\n\t\tADM_CL12\t\t= ADM_COUNTER_BASE + 0x2c, /* TxPacket */\n\t\tADM_CL18\t\t= ADM_COUNTER_BASE + 0x3e, /* TxByte */\n\t\tADM_CL24\t\t= ADM_COUNTER_BASE + 0x50, /* Coll */\n\t\tADM_CL30\t\t= ADM_COUNTER_BASE + 0x62, /* Err */\n#define ADM_OFFSET_PORT(n) ((n * 4) - (n / 4) * 2 - (n / 5) * 2)\n\tADM_PHY_BASE\t\t= 0x200,\n#define ADM_PHY_PORT(n) (ADM_PHY_BASE + (0x20 * n))\n};\n\n/* Chip identification patterns */\n#define\tADM_SIG0_MASK\t0xffff\n#define ADM_SIG0_VAL\t0x1023\n#define ADM_SIG1_MASK\t0xffff\n#define ADM_SIG1_VAL\t0x0007\n\nenum {\n\tADM_PHYCFG_COLTST     = (1 << 7),\t/* Enable collision test */\n\tADM_PHYCFG_DPLX       = (1 << 8),\t/* Enable full duplex */\n\tADM_PHYCFG_ANEN_RST   = (1 << 9),\t/* Restart auto negotiation (self clear) */\n\tADM_PHYCFG_ISO        = (1 << 10),\t/* Isolate PHY */\n\tADM_PHYCFG_PDN        = (1 << 11),\t/* Power down PHY */\n\tADM_PHYCFG_ANEN       = (1 << 12),\t/* Enable auto negotiation */\n\tADM_PHYCFG_SPEED_100  = (1 << 13),\t/* Enable 100 Mbit/s */\n\tADM_PHYCFG_LPBK       = (1 << 14),\t/* Enable loopback operation */\n\tADM_PHYCFG_RST        = (1 << 15),\t/* Reset the port (self clear) */\n\tADM_PHYCFG_INIT = (\n\t\tADM_PHYCFG_RST |\n\t\tADM_PHYCFG_SPEED_100 |\n\t\tADM_PHYCFG_ANEN |\n\t\tADM_PHYCFG_ANEN_RST\n\t)\n};\n\nenum {\n\tADM_PORTCFG_FC        = (1 << 0),\t/* Enable 802.x flow control */\n\tADM_PORTCFG_AN        = (1 << 1),\t/* Enable auto-negotiation */\n\tADM_PORTCFG_SPEED_100 = (1 << 2),\t/* Enable 100 Mbit/s */\n\tADM_PORTCFG_DPLX      = (1 << 3),\t/* Enable full duplex */\n\tADM_PORTCFG_OT        = (1 << 4),\t/* Output tagged packets */\n\tADM_PORTCFG_PD        = (1 << 5),\t/* Port disable */\n\tADM_PORTCFG_TV_PRIO   = (1 << 6),\t/* 0 = VLAN based priority\n\t                                 \t * 1 = TOS based priority */\n\tADM_PORTCFG_PPE       = (1 << 7),\t/* Port based priority enable */\n\tADM_PORTCFG_PP_S      = (1 << 8),\t/* Port based priority, 2 bits */\n\tADM_PORTCFG_PVID_BASE = (1 << 10),\t/* Primary VLAN id, 4 bits */\n\tADM_PORTCFG_FSE\t      = (1 << 14),\t/* Fx select enable */\n\tADM_PORTCFG_CAM       = (1 << 15),\t/* Crossover Auto MDIX */\n\n\tADM_PORTCFG_INIT = (\n\t\tADM_PORTCFG_FC |\n\t\tADM_PORTCFG_AN |\n\t\tADM_PORTCFG_SPEED_100 |\n\t\tADM_PORTCFG_DPLX |\n\t\tADM_PORTCFG_CAM\n\t),\n\tADM_PORTCFG_CPU = (\n\t\tADM_PORTCFG_FC |\n\t\tADM_PORTCFG_SPEED_100 |\n\t\tADM_PORTCFG_OT |\n\t\tADM_PORTCFG_DPLX\n\t),\n};\n\n#define ADM_PORTCFG_PPID(n) ((n & 0x3) << 8)\n#define ADM_PORTCFG_PVID(n) ((n & 0xf) << 10)\n#define ADM_PORTCFG_PVID_MASK (0xf << 10)\n\n#define ADM_IFNTE_MASK (0x3f << 9)\n#define ADM_VID_CHECK_MASK (0x3f << 6)\n\n#define ADM_P0_PVID_VAL(n) ((((n) & 0xff0) >> 4) << 0)\n#define ADM_P1_PVID_VAL(n) ((((n) & 0xff0) >> 4) << 0)\n#define ADM_P2_PVID_VAL(n) ((((n) & 0xff0) >> 4) << 0)\n#define ADM_P3_PVID_VAL(n) ((((n) & 0xff0) >> 4) << 0)\n#define ADM_P4_PVID_VAL(n) ((((n) & 0xff0) >> 4) << 8)\n#define ADM_P5_PVID_VAL(n) ((((n) & 0xff0) >> 4) << 0)\n#define ADM_P2_PVID_MASK 0xff\n\n#define ADM_OTBE(n) (((n) & 0x3f) << 8)\n#define ADM_OTBE_MASK (0x3f << 8)\n\n/* ADM_SYSC0 */\nenum {\n\tADM_NTTE\t= (1 << 2),\t/* New Tag Transmit Enable */\n\tADM_RVID1\t= (1 << 8)\t/* Replace VLAN ID 1 */\n};\n\n/* Tag Based VLAN in ADM_SYSC3 */\n#define ADM_MAC_CLONE\tBIT(4)\n#define ADM_TBV\t\tBIT(5)\n\nstatic const u8 adm_portcfg[] = {\n\t[0] = ADM_P0_CFG,\n\t[1] = ADM_P1_CFG,\n\t[2] = ADM_P2_CFG,\n\t[3] = ADM_P3_CFG,\n\t[4] = ADM_P4_CFG,\n\t[5] = ADM_P5_CFG,\n};\n\n/* Fields in ADM_VLAN_FILT_L(x) */\n#define ADM_VLAN_FILT_FID(n) (((n) & 0xf) << 12)\n#define ADM_VLAN_FILT_TAGGED(n) (((n) & 0x3f) << 6)\n#define ADM_VLAN_FILT_MEMBER(n) (((n) & 0x3f) << 0)\n#define ADM_VLAN_FILT_MEMBER_MASK 0x3f\n/* Fields in ADM_VLAN_FILT_H(x) */\n#define ADM_VLAN_FILT_VALID (1 << 15)\n#define ADM_VLAN_FILT_VID(n) (((n) & 0xfff) << 0)\n\n/* Convert ports to a form for ADM6996L VLAN map */\n#define ADM_VLAN_FILT(ports) ((ports & 0x01) | ((ports & 0x02) << 1) | \\\n\t\t\t((ports & 0x04) << 2) | ((ports & 0x08) << 3) | \\\n\t\t\t((ports & 0x10) << 3) | ((ports & 0x20) << 3))\n\n/* Port status register */\nenum {\n\tADM_PS_LS = (1 << 0),\t/* Link status */\n\tADM_PS_SS = (1 << 1),\t/* Speed status */\n\tADM_PS_DS = (1 << 2),\t/* Duplex status */\n\tADM_PS_FCS = (1 << 3)\t/* Flow control status */\n};\n\n/*\n * Split the register address in phy id and register\n * it will get combined again by the mdio bus op\n */\n#define PHYADDR(_reg)\t((_reg >> 5) & 0xff), (_reg & 0x1f)\n\n#endif\n"
  },
  {
    "path": "target/linux/generic/files/drivers/net/phy/ar8216.c",
    "content": "/*\n * ar8216.c: AR8216 switch driver\n *\n * Copyright (C) 2009 Felix Fietkau <nbd@nbd.name>\n * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>\n *\n * This program is free software; you can redistribute it and/or\n * modify it under the terms of the GNU General Public License\n * as published by the Free Software Foundation; either version 2\n * of the License, or (at your option) any later version.\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n * GNU General Public License for more details.\n */\n\n#include <linux/if.h>\n#include <linux/module.h>\n#include <linux/init.h>\n#include <linux/list.h>\n#include <linux/if_ether.h>\n#include <linux/skbuff.h>\n#include <linux/netdevice.h>\n#include <linux/netlink.h>\n#include <linux/of_device.h>\n#include <linux/of_mdio.h>\n#include <linux/of_net.h>\n#include <linux/bitops.h>\n#include <net/genetlink.h>\n#include <linux/switch.h>\n#include <linux/delay.h>\n#include <linux/phy.h>\n#include <linux/etherdevice.h>\n#include <linux/lockdep.h>\n#include <linux/ar8216_platform.h>\n#include <linux/workqueue.h>\n#include <linux/version.h>\n\n#include \"ar8216.h\"\n\nextern const struct ar8xxx_chip ar8327_chip;\nextern const struct ar8xxx_chip ar8337_chip;\n\n#define MIB_DESC_BASIC(_s , _o, _n)\t\t\\\n\t{\t\t\t\t\t\\\n\t\t.size = (_s),\t\t\t\\\n\t\t.offset = (_o),\t\t\t\\\n\t\t.name = (_n),\t\t\t\\\n\t\t.type = AR8XXX_MIB_BASIC,\t\\\n\t}\n\n#define MIB_DESC_EXT(_s , _o, _n)\t\t\\\n\t{\t\t\t\t\t\\\n\t\t.size = (_s),\t\t\t\\\n\t\t.offset = (_o),\t\t\t\\\n\t\t.name = (_n),\t\t\t\\\n\t\t.type = AR8XXX_MIB_EXTENDED,\t\\\n\t}\n\nstatic const struct ar8xxx_mib_desc ar8216_mibs[] = {\n\tMIB_DESC_EXT(1, AR8216_STATS_RXBROAD, \"RxBroad\"),\n\tMIB_DESC_EXT(1, AR8216_STATS_RXPAUSE, \"RxPause\"),\n\tMIB_DESC_EXT(1, AR8216_STATS_RXMULTI, \"RxMulti\"),\n\tMIB_DESC_EXT(1, AR8216_STATS_RXFCSERR, \"RxFcsErr\"),\n\tMIB_DESC_EXT(1, AR8216_STATS_RXALIGNERR, \"RxAlignErr\"),\n\tMIB_DESC_EXT(1, AR8216_STATS_RXRUNT, \"RxRunt\"),\n\tMIB_DESC_EXT(1, AR8216_STATS_RXFRAGMENT, \"RxFragment\"),\n\tMIB_DESC_EXT(1, AR8216_STATS_RX64BYTE, \"Rx64Byte\"),\n\tMIB_DESC_EXT(1, AR8216_STATS_RX128BYTE, \"Rx128Byte\"),\n\tMIB_DESC_EXT(1, AR8216_STATS_RX256BYTE, \"Rx256Byte\"),\n\tMIB_DESC_EXT(1, AR8216_STATS_RX512BYTE, \"Rx512Byte\"),\n\tMIB_DESC_EXT(1, AR8216_STATS_RX1024BYTE, \"Rx1024Byte\"),\n\tMIB_DESC_EXT(1, AR8216_STATS_RXMAXBYTE, \"RxMaxByte\"),\n\tMIB_DESC_EXT(1, AR8216_STATS_RXTOOLONG, \"RxTooLong\"),\n\tMIB_DESC_BASIC(2, AR8216_STATS_RXGOODBYTE, \"RxGoodByte\"),\n\tMIB_DESC_EXT(2, AR8216_STATS_RXBADBYTE, \"RxBadByte\"),\n\tMIB_DESC_EXT(1, AR8216_STATS_RXOVERFLOW, \"RxOverFlow\"),\n\tMIB_DESC_EXT(1, AR8216_STATS_FILTERED, \"Filtered\"),\n\tMIB_DESC_EXT(1, AR8216_STATS_TXBROAD, \"TxBroad\"),\n\tMIB_DESC_EXT(1, AR8216_STATS_TXPAUSE, \"TxPause\"),\n\tMIB_DESC_EXT(1, AR8216_STATS_TXMULTI, \"TxMulti\"),\n\tMIB_DESC_EXT(1, AR8216_STATS_TXUNDERRUN, \"TxUnderRun\"),\n\tMIB_DESC_EXT(1, AR8216_STATS_TX64BYTE, \"Tx64Byte\"),\n\tMIB_DESC_EXT(1, AR8216_STATS_TX128BYTE, \"Tx128Byte\"),\n\tMIB_DESC_EXT(1, AR8216_STATS_TX256BYTE, \"Tx256Byte\"),\n\tMIB_DESC_EXT(1, AR8216_STATS_TX512BYTE, \"Tx512Byte\"),\n\tMIB_DESC_EXT(1, AR8216_STATS_TX1024BYTE, \"Tx1024Byte\"),\n\tMIB_DESC_EXT(1, AR8216_STATS_TXMAXBYTE, \"TxMaxByte\"),\n\tMIB_DESC_EXT(1, AR8216_STATS_TXOVERSIZE, \"TxOverSize\"),\n\tMIB_DESC_BASIC(2, AR8216_STATS_TXBYTE, \"TxByte\"),\n\tMIB_DESC_EXT(1, AR8216_STATS_TXCOLLISION, \"TxCollision\"),\n\tMIB_DESC_EXT(1, AR8216_STATS_TXABORTCOL, \"TxAbortCol\"),\n\tMIB_DESC_EXT(1, AR8216_STATS_TXMULTICOL, \"TxMultiCol\"),\n\tMIB_DESC_EXT(1, AR8216_STATS_TXSINGLECOL, \"TxSingleCol\"),\n\tMIB_DESC_EXT(1, AR8216_STATS_TXEXCDEFER, \"TxExcDefer\"),\n\tMIB_DESC_EXT(1, AR8216_STATS_TXDEFER, \"TxDefer\"),\n\tMIB_DESC_EXT(1, AR8216_STATS_TXLATECOL, \"TxLateCol\"),\n};\n\nconst struct ar8xxx_mib_desc ar8236_mibs[39] = {\n\tMIB_DESC_EXT(1, AR8236_STATS_RXBROAD, \"RxBroad\"),\n\tMIB_DESC_EXT(1, AR8236_STATS_RXPAUSE, \"RxPause\"),\n\tMIB_DESC_EXT(1, AR8236_STATS_RXMULTI, \"RxMulti\"),\n\tMIB_DESC_EXT(1, AR8236_STATS_RXFCSERR, \"RxFcsErr\"),\n\tMIB_DESC_EXT(1, AR8236_STATS_RXALIGNERR, \"RxAlignErr\"),\n\tMIB_DESC_EXT(1, AR8236_STATS_RXRUNT, \"RxRunt\"),\n\tMIB_DESC_EXT(1, AR8236_STATS_RXFRAGMENT, \"RxFragment\"),\n\tMIB_DESC_EXT(1, AR8236_STATS_RX64BYTE, \"Rx64Byte\"),\n\tMIB_DESC_EXT(1, AR8236_STATS_RX128BYTE, \"Rx128Byte\"),\n\tMIB_DESC_EXT(1, AR8236_STATS_RX256BYTE, \"Rx256Byte\"),\n\tMIB_DESC_EXT(1, AR8236_STATS_RX512BYTE, \"Rx512Byte\"),\n\tMIB_DESC_EXT(1, AR8236_STATS_RX1024BYTE, \"Rx1024Byte\"),\n\tMIB_DESC_EXT(1, AR8236_STATS_RX1518BYTE, \"Rx1518Byte\"),\n\tMIB_DESC_EXT(1, AR8236_STATS_RXMAXBYTE, \"RxMaxByte\"),\n\tMIB_DESC_EXT(1, AR8236_STATS_RXTOOLONG, \"RxTooLong\"),\n\tMIB_DESC_BASIC(2, AR8236_STATS_RXGOODBYTE, \"RxGoodByte\"),\n\tMIB_DESC_EXT(2, AR8236_STATS_RXBADBYTE, \"RxBadByte\"),\n\tMIB_DESC_EXT(1, AR8236_STATS_RXOVERFLOW, \"RxOverFlow\"),\n\tMIB_DESC_EXT(1, AR8236_STATS_FILTERED, \"Filtered\"),\n\tMIB_DESC_EXT(1, AR8236_STATS_TXBROAD, \"TxBroad\"),\n\tMIB_DESC_EXT(1, AR8236_STATS_TXPAUSE, \"TxPause\"),\n\tMIB_DESC_EXT(1, AR8236_STATS_TXMULTI, \"TxMulti\"),\n\tMIB_DESC_EXT(1, AR8236_STATS_TXUNDERRUN, \"TxUnderRun\"),\n\tMIB_DESC_EXT(1, AR8236_STATS_TX64BYTE, \"Tx64Byte\"),\n\tMIB_DESC_EXT(1, AR8236_STATS_TX128BYTE, \"Tx128Byte\"),\n\tMIB_DESC_EXT(1, AR8236_STATS_TX256BYTE, \"Tx256Byte\"),\n\tMIB_DESC_EXT(1, AR8236_STATS_TX512BYTE, \"Tx512Byte\"),\n\tMIB_DESC_EXT(1, AR8236_STATS_TX1024BYTE, \"Tx1024Byte\"),\n\tMIB_DESC_EXT(1, AR8236_STATS_TX1518BYTE, \"Tx1518Byte\"),\n\tMIB_DESC_EXT(1, AR8236_STATS_TXMAXBYTE, \"TxMaxByte\"),\n\tMIB_DESC_EXT(1, AR8236_STATS_TXOVERSIZE, \"TxOverSize\"),\n\tMIB_DESC_BASIC(2, AR8236_STATS_TXBYTE, \"TxByte\"),\n\tMIB_DESC_EXT(1, AR8236_STATS_TXCOLLISION, \"TxCollision\"),\n\tMIB_DESC_EXT(1, AR8236_STATS_TXABORTCOL, \"TxAbortCol\"),\n\tMIB_DESC_EXT(1, AR8236_STATS_TXMULTICOL, \"TxMultiCol\"),\n\tMIB_DESC_EXT(1, AR8236_STATS_TXSINGLECOL, \"TxSingleCol\"),\n\tMIB_DESC_EXT(1, AR8236_STATS_TXEXCDEFER, \"TxExcDefer\"),\n\tMIB_DESC_EXT(1, AR8236_STATS_TXDEFER, \"TxDefer\"),\n\tMIB_DESC_EXT(1, AR8236_STATS_TXLATECOL, \"TxLateCol\"),\n};\n\nstatic DEFINE_MUTEX(ar8xxx_dev_list_lock);\nstatic LIST_HEAD(ar8xxx_dev_list);\n\nstatic void\nar8xxx_mib_start(struct ar8xxx_priv *priv);\nstatic void\nar8xxx_mib_stop(struct ar8xxx_priv *priv);\n\n/* inspired by phy_poll_reset in drivers/net/phy/phy_device.c */\nstatic int\nar8xxx_phy_poll_reset(struct mii_bus *bus)\n{\n        unsigned int sleep_msecs = 20;\n        int ret, elapsed, i;\n\n        for (elapsed = sleep_msecs; elapsed <= 600;\n\t     elapsed += sleep_msecs) {\n                msleep(sleep_msecs);\n                for (i = 0; i < AR8XXX_NUM_PHYS; i++) {\n                        ret = mdiobus_read(bus, i, MII_BMCR);\n                        if (ret < 0)\n\t\t\t\treturn ret;\n                        if (ret & BMCR_RESET)\n\t\t\t\tbreak;\n                        if (i == AR8XXX_NUM_PHYS - 1) {\n                                usleep_range(1000, 2000);\n                                return 0;\n                        }\n                }\n        }\n        return -ETIMEDOUT;\n}\n\nstatic int\nar8xxx_phy_check_aneg(struct phy_device *phydev)\n{\n\tint ret;\n\n\tif (phydev->autoneg != AUTONEG_ENABLE)\n\t\treturn 0;\n\t/*\n\t * BMCR_ANENABLE might have been cleared\n\t * by phy_init_hw in certain kernel versions\n\t * therefore check for it\n\t */\n\tret = phy_read(phydev, MII_BMCR);\n\tif (ret < 0)\n\t\treturn ret;\n\tif (ret & BMCR_ANENABLE)\n\t\treturn 0;\n\n\tdev_info(&phydev->mdio.dev, \"ANEG disabled, re-enabling ...\\n\");\n\tret |= BMCR_ANENABLE | BMCR_ANRESTART;\n\treturn phy_write(phydev, MII_BMCR, ret);\n}\n\nvoid\nar8xxx_phy_init(struct ar8xxx_priv *priv)\n{\n\tint i;\n\tstruct mii_bus *bus;\n\n\tbus = priv->sw_mii_bus ?: priv->mii_bus;\n\tfor (i = 0; i < AR8XXX_NUM_PHYS; i++) {\n\t\tif (priv->chip->phy_fixup)\n\t\t\tpriv->chip->phy_fixup(priv, i);\n\n\t\t/* initialize the port itself */\n\t\tmdiobus_write(bus, i, MII_ADVERTISE,\n\t\t\tADVERTISE_ALL | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);\n\t\tif (ar8xxx_has_gige(priv))\n\t\t\tmdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);\n\t\tmdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);\n\t}\n\n\tar8xxx_phy_poll_reset(bus);\n}\n\nu32\nar8xxx_mii_read32(struct ar8xxx_priv *priv, int phy_id, int regnum)\n{\n\tstruct mii_bus *bus = priv->mii_bus;\n\tu16 lo, hi;\n\n\tlo = bus->read(bus, phy_id, regnum);\n\thi = bus->read(bus, phy_id, regnum + 1);\n\n\treturn (hi << 16) | lo;\n}\n\nvoid\nar8xxx_mii_write32(struct ar8xxx_priv *priv, int phy_id, int regnum, u32 val)\n{\n\tstruct mii_bus *bus = priv->mii_bus;\n\tu16 lo, hi;\n\n\tlo = val & 0xffff;\n\thi = (u16) (val >> 16);\n\n\tif (priv->chip->mii_lo_first)\n\t{\n\t\tbus->write(bus, phy_id, regnum, lo);\n\t\tbus->write(bus, phy_id, regnum + 1, hi);\n\t} else {\n\t\tbus->write(bus, phy_id, regnum + 1, hi);\n\t\tbus->write(bus, phy_id, regnum, lo);\n\t}\n}\n\nu32\nar8xxx_read(struct ar8xxx_priv *priv, int reg)\n{\n\tstruct mii_bus *bus = priv->mii_bus;\n\tu16 r1, r2, page;\n\tu32 val;\n\n\tsplit_addr((u32) reg, &r1, &r2, &page);\n\n\tmutex_lock(&bus->mdio_lock);\n\n\tbus->write(bus, 0x18, 0, page);\n\twait_for_page_switch();\n\tval = ar8xxx_mii_read32(priv, 0x10 | r2, r1);\n\n\tmutex_unlock(&bus->mdio_lock);\n\n\treturn val;\n}\n\nvoid\nar8xxx_write(struct ar8xxx_priv *priv, int reg, u32 val)\n{\n\tstruct mii_bus *bus = priv->mii_bus;\n\tu16 r1, r2, page;\n\n\tsplit_addr((u32) reg, &r1, &r2, &page);\n\n\tmutex_lock(&bus->mdio_lock);\n\n\tbus->write(bus, 0x18, 0, page);\n\twait_for_page_switch();\n\tar8xxx_mii_write32(priv, 0x10 | r2, r1, val);\n\n\tmutex_unlock(&bus->mdio_lock);\n}\n\nu32\nar8xxx_rmw(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)\n{\n\tstruct mii_bus *bus = priv->mii_bus;\n\tu16 r1, r2, page;\n\tu32 ret;\n\n\tsplit_addr((u32) reg, &r1, &r2, &page);\n\n\tmutex_lock(&bus->mdio_lock);\n\n\tbus->write(bus, 0x18, 0, page);\n\twait_for_page_switch();\n\n\tret = ar8xxx_mii_read32(priv, 0x10 | r2, r1);\n\tret &= ~mask;\n\tret |= val;\n\tar8xxx_mii_write32(priv, 0x10 | r2, r1, ret);\n\n\tmutex_unlock(&bus->mdio_lock);\n\n\treturn ret;\n}\nvoid\nar8xxx_phy_dbg_read(struct ar8xxx_priv *priv, int phy_addr,\n           u16 dbg_addr, u16 *dbg_data)\n{\n       struct mii_bus *bus = priv->mii_bus;\n\n       mutex_lock(&bus->mdio_lock);\n       bus->write(bus, phy_addr, MII_ATH_DBG_ADDR, dbg_addr);\n       *dbg_data = bus->read(bus, phy_addr, MII_ATH_DBG_DATA);\n       mutex_unlock(&bus->mdio_lock);\n}\n\nvoid\nar8xxx_phy_dbg_write(struct ar8xxx_priv *priv, int phy_addr,\n\t\t     u16 dbg_addr, u16 dbg_data)\n{\n\tstruct mii_bus *bus = priv->mii_bus;\n\n\tmutex_lock(&bus->mdio_lock);\n\tbus->write(bus, phy_addr, MII_ATH_DBG_ADDR, dbg_addr);\n\tbus->write(bus, phy_addr, MII_ATH_DBG_DATA, dbg_data);\n\tmutex_unlock(&bus->mdio_lock);\n}\n\nstatic inline void\nar8xxx_phy_mmd_prep(struct mii_bus *bus, int phy_addr, u16 addr, u16 reg)\n{\n\tbus->write(bus, phy_addr, MII_ATH_MMD_ADDR, addr);\n\tbus->write(bus, phy_addr, MII_ATH_MMD_DATA, reg);\n\tbus->write(bus, phy_addr, MII_ATH_MMD_ADDR, addr | 0x4000);\n}\n\nvoid\nar8xxx_phy_mmd_write(struct ar8xxx_priv *priv, int phy_addr, u16 addr, u16 reg, u16 data)\n{\n\tstruct mii_bus *bus = priv->mii_bus;\n\n\tmutex_lock(&bus->mdio_lock);\n\tar8xxx_phy_mmd_prep(bus, phy_addr, addr, reg);\n\tbus->write(bus, phy_addr, MII_ATH_MMD_DATA, data);\n\tmutex_unlock(&bus->mdio_lock);\n}\n\nu16\nar8xxx_phy_mmd_read(struct ar8xxx_priv *priv, int phy_addr, u16 addr, u16 reg)\n{\n\tstruct mii_bus *bus = priv->mii_bus;\n\tu16 data;\n\n\tmutex_lock(&bus->mdio_lock);\n\tar8xxx_phy_mmd_prep(bus, phy_addr, addr, reg);\n\tdata = bus->read(bus, phy_addr, MII_ATH_MMD_DATA);\n\tmutex_unlock(&bus->mdio_lock);\n\n\treturn data;\n}\n\nstatic int\nar8xxx_reg_wait(struct ar8xxx_priv *priv, u32 reg, u32 mask, u32 val,\n\t\tunsigned timeout)\n{\n\tint i;\n\n\tfor (i = 0; i < timeout; i++) {\n\t\tu32 t;\n\n\t\tt = ar8xxx_read(priv, reg);\n\t\tif ((t & mask) == val)\n\t\t\treturn 0;\n\n\t\tusleep_range(1000, 2000);\n\t\tcond_resched();\n\t}\n\n\treturn -ETIMEDOUT;\n}\n\nstatic int\nar8xxx_mib_op(struct ar8xxx_priv *priv, u32 op)\n{\n\tunsigned mib_func = priv->chip->mib_func;\n\tint ret;\n\n\tlockdep_assert_held(&priv->mib_lock);\n\n\t/* Capture the hardware statistics for all ports */\n\tar8xxx_rmw(priv, mib_func, AR8216_MIB_FUNC, (op << AR8216_MIB_FUNC_S));\n\n\t/* Wait for the capturing to complete. */\n\tret = ar8xxx_reg_wait(priv, mib_func, AR8216_MIB_BUSY, 0, 10);\n\tif (ret)\n\t\tgoto out;\n\n\tret = 0;\n\nout:\n\treturn ret;\n}\n\nstatic int\nar8xxx_mib_capture(struct ar8xxx_priv *priv)\n{\n\treturn ar8xxx_mib_op(priv, AR8216_MIB_FUNC_CAPTURE);\n}\n\nstatic int\nar8xxx_mib_flush(struct ar8xxx_priv *priv)\n{\n\treturn ar8xxx_mib_op(priv, AR8216_MIB_FUNC_FLUSH);\n}\n\nstatic void\nar8xxx_mib_fetch_port_stat(struct ar8xxx_priv *priv, int port, bool flush)\n{\n\tunsigned int base;\n\tu64 *mib_stats;\n\tint i;\n\n\tWARN_ON(port >= priv->dev.ports);\n\n\tlockdep_assert_held(&priv->mib_lock);\n\n\tbase = priv->chip->reg_port_stats_start +\n\t       priv->chip->reg_port_stats_length * port;\n\n\tmib_stats = &priv->mib_stats[port * priv->chip->num_mibs];\n\tfor (i = 0; i < priv->chip->num_mibs; i++) {\n\t\tconst struct ar8xxx_mib_desc *mib;\n\t\tu64 t;\n\n\t\tmib = &priv->chip->mib_decs[i];\n\t\tif (mib->type > priv->mib_type)\n\t\t\tcontinue;\n\t\tt = ar8xxx_read(priv, base + mib->offset);\n\t\tif (mib->size == 2) {\n\t\t\tu64 hi;\n\n\t\t\thi = ar8xxx_read(priv, base + mib->offset + 4);\n\t\t\tt |= hi << 32;\n\t\t}\n\n\t\tif (flush)\n\t\t\tmib_stats[i] = 0;\n\t\telse\n\t\t\tmib_stats[i] += t;\n\t\tcond_resched();\n\t}\n}\n\nstatic void\nar8216_read_port_link(struct ar8xxx_priv *priv, int port,\n\t\t      struct switch_port_link *link)\n{\n\tu32 status;\n\tu32 speed;\n\n\tmemset(link, '\\0', sizeof(*link));\n\n\tstatus = priv->chip->read_port_status(priv, port);\n\n\tlink->aneg = !!(status & AR8216_PORT_STATUS_LINK_AUTO);\n\tif (link->aneg) {\n\t\tlink->link = !!(status & AR8216_PORT_STATUS_LINK_UP);\n\t} else {\n\t\tlink->link = true;\n\n\t\tif (priv->get_port_link) {\n\t\t\tint err;\n\n\t\t\terr = priv->get_port_link(port);\n\t\t\tif (err >= 0)\n\t\t\t\tlink->link = !!err;\n\t\t}\n\t}\n\n\tif (!link->link)\n\t\treturn;\n\n\tlink->duplex = !!(status & AR8216_PORT_STATUS_DUPLEX);\n\tlink->tx_flow = !!(status & AR8216_PORT_STATUS_TXFLOW);\n\tlink->rx_flow = !!(status & AR8216_PORT_STATUS_RXFLOW);\n\n\tif (link->aneg && link->duplex && priv->chip->read_port_eee_status)\n\t\tlink->eee = priv->chip->read_port_eee_status(priv, port);\n\n\tspeed = (status & AR8216_PORT_STATUS_SPEED) >>\n\t\t AR8216_PORT_STATUS_SPEED_S;\n\n\tswitch (speed) {\n\tcase AR8216_PORT_SPEED_10M:\n\t\tlink->speed = SWITCH_PORT_SPEED_10;\n\t\tbreak;\n\tcase AR8216_PORT_SPEED_100M:\n\t\tlink->speed = SWITCH_PORT_SPEED_100;\n\t\tbreak;\n\tcase AR8216_PORT_SPEED_1000M:\n\t\tlink->speed = SWITCH_PORT_SPEED_1000;\n\t\tbreak;\n\tdefault:\n\t\tlink->speed = SWITCH_PORT_SPEED_UNKNOWN;\n\t\tbreak;\n\t}\n}\n\n#ifdef CONFIG_ETHERNET_PACKET_MANGLE\n\nstatic struct sk_buff *\nar8216_mangle_tx(struct net_device *dev, struct sk_buff *skb)\n{\n\tstruct ar8xxx_priv *priv = dev->phy_ptr;\n\tunsigned char *buf;\n\n\tif (unlikely(!priv))\n\t\tgoto error;\n\n\tif (!priv->vlan)\n\t\tgoto send;\n\n\tif (unlikely(skb_headroom(skb) < 2)) {\n\t\tif (pskb_expand_head(skb, 2, 0, GFP_ATOMIC) < 0)\n\t\t\tgoto error;\n\t}\n\n\tbuf = skb_push(skb, 2);\n\tbuf[0] = 0x10;\n\tbuf[1] = 0x80;\n\nsend:\n\treturn skb;\n\nerror:\n\tdev_kfree_skb_any(skb);\n\treturn NULL;\n}\n\nstatic void\nar8216_mangle_rx(struct net_device *dev, struct sk_buff *skb)\n{\n\tstruct ar8xxx_priv *priv;\n\tunsigned char *buf;\n\tint port, vlan;\n\n\tpriv = dev->phy_ptr;\n\tif (!priv)\n\t\treturn;\n\n\t/* don't strip the header if vlan mode is disabled */\n\tif (!priv->vlan)\n\t\treturn;\n\n\t/* strip header, get vlan id */\n\tbuf = skb->data;\n\tskb_pull(skb, 2);\n\n\t/* check for vlan header presence */\n\tif ((buf[12 + 2] != 0x81) || (buf[13 + 2] != 0x00))\n\t\treturn;\n\n\tport = buf[0] & 0x7;\n\n\t/* no need to fix up packets coming from a tagged source */\n\tif (priv->vlan_tagged & (1 << port))\n\t\treturn;\n\n\t/* lookup port vid from local table, the switch passes an invalid vlan id */\n\tvlan = priv->vlan_id[priv->pvid[port]];\n\n\tbuf[14 + 2] &= 0xf0;\n\tbuf[14 + 2] |= vlan >> 8;\n\tbuf[15 + 2] = vlan & 0xff;\n}\n\n#endif\n\nint\nar8216_wait_bit(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)\n{\n\tint timeout = 20;\n\tu32 t = 0;\n\n\twhile (1) {\n\t\tt = ar8xxx_read(priv, reg);\n\t\tif ((t & mask) == val)\n\t\t\treturn 0;\n\n\t\tif (timeout-- <= 0)\n\t\t\tbreak;\n\n\t\tudelay(10);\n\t\tcond_resched();\n\t}\n\n\tpr_err(\"ar8216: timeout on reg %08x: %08x & %08x != %08x\\n\",\n\t       (unsigned int) reg, t, mask, val);\n\treturn -ETIMEDOUT;\n}\n\nstatic void\nar8216_vtu_op(struct ar8xxx_priv *priv, u32 op, u32 val)\n{\n\tif (ar8216_wait_bit(priv, AR8216_REG_VTU, AR8216_VTU_ACTIVE, 0))\n\t\treturn;\n\tif ((op & AR8216_VTU_OP) == AR8216_VTU_OP_LOAD) {\n\t\tval &= AR8216_VTUDATA_MEMBER;\n\t\tval |= AR8216_VTUDATA_VALID;\n\t\tar8xxx_write(priv, AR8216_REG_VTU_DATA, val);\n\t}\n\top |= AR8216_VTU_ACTIVE;\n\tar8xxx_write(priv, AR8216_REG_VTU, op);\n}\n\nstatic void\nar8216_vtu_flush(struct ar8xxx_priv *priv)\n{\n\tar8216_vtu_op(priv, AR8216_VTU_OP_FLUSH, 0);\n}\n\nstatic void\nar8216_vtu_load_vlan(struct ar8xxx_priv *priv, u32 vid, u32 port_mask)\n{\n\tu32 op;\n\n\top = AR8216_VTU_OP_LOAD | (vid << AR8216_VTU_VID_S);\n\tar8216_vtu_op(priv, op, port_mask);\n}\n\nstatic int\nar8216_atu_flush(struct ar8xxx_priv *priv)\n{\n\tint ret;\n\n\tret = ar8216_wait_bit(priv, AR8216_REG_ATU_FUNC0, AR8216_ATU_ACTIVE, 0);\n\tif (!ret)\n\t\tar8xxx_write(priv, AR8216_REG_ATU_FUNC0, AR8216_ATU_OP_FLUSH |\n\t\t\t\t\t\t\t AR8216_ATU_ACTIVE);\n\n\treturn ret;\n}\n\nstatic int\nar8216_atu_flush_port(struct ar8xxx_priv *priv, int port)\n{\n\tu32 t;\n\tint ret;\n\n\tret = ar8216_wait_bit(priv, AR8216_REG_ATU_FUNC0, AR8216_ATU_ACTIVE, 0);\n\tif (!ret) {\n\t\tt = (port << AR8216_ATU_PORT_NUM_S) | AR8216_ATU_OP_FLUSH_PORT;\n\t\tt |= AR8216_ATU_ACTIVE;\n\t\tar8xxx_write(priv, AR8216_REG_ATU_FUNC0, t);\n\t}\n\n\treturn ret;\n}\n\nstatic u32\nar8216_read_port_status(struct ar8xxx_priv *priv, int port)\n{\n\treturn ar8xxx_read(priv, AR8216_REG_PORT_STATUS(port));\n}\n\nstatic void\n__ar8216_setup_port(struct ar8xxx_priv *priv, int port, u32 members,\n\t\t    bool ath_hdr_en)\n{\n\tu32 header;\n\tu32 egress, ingress;\n\tu32 pvid;\n\n\tif (priv->vlan) {\n\t\tpvid = priv->vlan_id[priv->pvid[port]];\n\t\tif (priv->vlan_tagged & (1 << port))\n\t\t\tegress = AR8216_OUT_ADD_VLAN;\n\t\telse\n\t\t\tegress = AR8216_OUT_STRIP_VLAN;\n\t\tingress = AR8216_IN_SECURE;\n\t} else {\n\t\tpvid = port;\n\t\tegress = AR8216_OUT_KEEP;\n\t\tingress = AR8216_IN_PORT_ONLY;\n\t}\n\n\theader = ath_hdr_en ? AR8216_PORT_CTRL_HEADER : 0;\n\n\tar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),\n\t\t   AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |\n\t\t   AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |\n\t\t   AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,\n\t\t   AR8216_PORT_CTRL_LEARN | header |\n\t\t   (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |\n\t\t   (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));\n\n\tar8xxx_rmw(priv, AR8216_REG_PORT_VLAN(port),\n\t\t   AR8216_PORT_VLAN_DEST_PORTS | AR8216_PORT_VLAN_MODE |\n\t\t   AR8216_PORT_VLAN_DEFAULT_ID,\n\t\t   (members << AR8216_PORT_VLAN_DEST_PORTS_S) |\n\t\t   (ingress << AR8216_PORT_VLAN_MODE_S) |\n\t\t   (pvid << AR8216_PORT_VLAN_DEFAULT_ID_S));\n}\n\nstatic void\nar8216_setup_port(struct ar8xxx_priv *priv, int port, u32 members)\n{\n\treturn __ar8216_setup_port(priv, port, members,\n\t\t\t\t   chip_is_ar8216(priv) && priv->vlan &&\n\t\t\t\t   port == AR8216_PORT_CPU);\n}\n\nstatic int\nar8216_hw_init(struct ar8xxx_priv *priv)\n{\n\tif (priv->initialized)\n\t\treturn 0;\n\n\tar8xxx_write(priv, AR8216_REG_CTRL, AR8216_CTRL_RESET);\n\tar8xxx_reg_wait(priv, AR8216_REG_CTRL, AR8216_CTRL_RESET, 0, 1000);\n\n\tar8xxx_phy_init(priv);\n\n\tpriv->initialized = true;\n\treturn 0;\n}\n\nstatic void\nar8216_init_globals(struct ar8xxx_priv *priv)\n{\n\t/* standard atheros magic */\n\tar8xxx_write(priv, 0x38, 0xc000050e);\n\n\tar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,\n\t\t   AR8216_GCTRL_MTU, 1518 + 8 + 2);\n}\n\nstatic void\n__ar8216_init_port(struct ar8xxx_priv *priv, int port,\n\t\t   bool cpu_ge, bool flow_en)\n{\n\t/* Enable port learning and tx */\n\tar8xxx_write(priv, AR8216_REG_PORT_CTRL(port),\n\t\tAR8216_PORT_CTRL_LEARN |\n\t\t(4 << AR8216_PORT_CTRL_STATE_S));\n\n\tar8xxx_write(priv, AR8216_REG_PORT_VLAN(port), 0);\n\n\tif (port == AR8216_PORT_CPU) {\n\t\tar8xxx_write(priv, AR8216_REG_PORT_STATUS(port),\n\t\t\tAR8216_PORT_STATUS_LINK_UP |\n\t\t\t(cpu_ge ? AR8216_PORT_SPEED_1000M : AR8216_PORT_SPEED_100M) |\n\t\t\tAR8216_PORT_STATUS_TXMAC |\n\t\t\tAR8216_PORT_STATUS_RXMAC |\n\t\t\t(flow_en ? AR8216_PORT_STATUS_RXFLOW : 0) |\n\t\t\t(flow_en ? AR8216_PORT_STATUS_TXFLOW : 0) |\n\t\t\tAR8216_PORT_STATUS_DUPLEX);\n\t} else {\n\t\tar8xxx_write(priv, AR8216_REG_PORT_STATUS(port),\n\t\t\tAR8216_PORT_STATUS_LINK_AUTO);\n\t}\n}\n\nstatic void\nar8216_init_port(struct ar8xxx_priv *priv, int port)\n{\n\t__ar8216_init_port(priv, port, ar8xxx_has_gige(priv),\n\t\t\t   chip_is_ar8316(priv));\n}\n\nstatic void\nar8216_wait_atu_ready(struct ar8xxx_priv *priv, u16 r2, u16 r1)\n{\n\tint timeout = 20;\n\n\twhile (ar8xxx_mii_read32(priv, r2, r1) & AR8216_ATU_ACTIVE && --timeout) {\n\t\tudelay(10);\n\t\tcond_resched();\n\t}\n\n\tif (!timeout)\n\t\tpr_err(\"ar8216: timeout waiting for atu to become ready\\n\");\n}\n\nstatic void ar8216_get_arl_entry(struct ar8xxx_priv *priv,\n\t\t\t\t struct arl_entry *a, u32 *status, enum arl_op op)\n{\n\tstruct mii_bus *bus = priv->mii_bus;\n\tu16 r2, page;\n\tu16 r1_func0, r1_func1, r1_func2;\n\tu32 t, val0, val1, val2;\n\n\tsplit_addr(AR8216_REG_ATU_FUNC0, &r1_func0, &r2, &page);\n\tr2 |= 0x10;\n\n\tr1_func1 = (AR8216_REG_ATU_FUNC1 >> 1) & 0x1e;\n\tr1_func2 = (AR8216_REG_ATU_FUNC2 >> 1) & 0x1e;\n\n\tswitch (op) {\n\tcase AR8XXX_ARL_INITIALIZE:\n\t\t/* all ATU registers are on the same page\n\t\t* therefore set page only once\n\t\t*/\n\t\tbus->write(bus, 0x18, 0, page);\n\t\twait_for_page_switch();\n\n\t\tar8216_wait_atu_ready(priv, r2, r1_func0);\n\n\t\tar8xxx_mii_write32(priv, r2, r1_func0, AR8216_ATU_OP_GET_NEXT);\n\t\tar8xxx_mii_write32(priv, r2, r1_func1, 0);\n\t\tar8xxx_mii_write32(priv, r2, r1_func2, 0);\n\t\tbreak;\n\tcase AR8XXX_ARL_GET_NEXT:\n\t\tt = ar8xxx_mii_read32(priv, r2, r1_func0);\n\t\tt |= AR8216_ATU_ACTIVE;\n\t\tar8xxx_mii_write32(priv, r2, r1_func0, t);\n\t\tar8216_wait_atu_ready(priv, r2, r1_func0);\n\n\t\tval0 = ar8xxx_mii_read32(priv, r2, r1_func0);\n\t\tval1 = ar8xxx_mii_read32(priv, r2, r1_func1);\n\t\tval2 = ar8xxx_mii_read32(priv, r2, r1_func2);\n\n\t\t*status = (val2 & AR8216_ATU_STATUS) >> AR8216_ATU_STATUS_S;\n\t\tif (!*status)\n\t\t\tbreak;\n\n\t\ta->portmap = (val2 & AR8216_ATU_PORTS) >> AR8216_ATU_PORTS_S;\n\t\ta->mac[0] = (val0 & AR8216_ATU_ADDR5) >> AR8216_ATU_ADDR5_S;\n\t\ta->mac[1] = (val0 & AR8216_ATU_ADDR4) >> AR8216_ATU_ADDR4_S;\n\t\ta->mac[2] = (val1 & AR8216_ATU_ADDR3) >> AR8216_ATU_ADDR3_S;\n\t\ta->mac[3] = (val1 & AR8216_ATU_ADDR2) >> AR8216_ATU_ADDR2_S;\n\t\ta->mac[4] = (val1 & AR8216_ATU_ADDR1) >> AR8216_ATU_ADDR1_S;\n\t\ta->mac[5] = (val1 & AR8216_ATU_ADDR0) >> AR8216_ATU_ADDR0_S;\n\t\tbreak;\n\t}\n}\n\nstatic int\nar8216_phy_read(struct ar8xxx_priv *priv, int addr, int regnum)\n{\n\tu32 t, val = 0xffff;\n\tint err;\n\n\tif (addr >= AR8216_NUM_PORTS)\n\t\treturn 0xffff;\n\tt = (regnum << AR8216_MDIO_CTRL_REG_ADDR_S) |\n\t    (addr << AR8216_MDIO_CTRL_PHY_ADDR_S) |\n\t    AR8216_MDIO_CTRL_MASTER_EN |\n\t    AR8216_MDIO_CTRL_BUSY |\n\t    AR8216_MDIO_CTRL_CMD_READ;\n\n\tar8xxx_write(priv, AR8216_REG_MDIO_CTRL, t);\n\terr = ar8xxx_reg_wait(priv, AR8216_REG_MDIO_CTRL,\n\t\t\t      AR8216_MDIO_CTRL_BUSY, 0, 5);\n\tif (!err)\n\t\tval = ar8xxx_read(priv, AR8216_REG_MDIO_CTRL);\n\n\treturn val & AR8216_MDIO_CTRL_DATA_M;\n}\n\nstatic int\nar8216_phy_write(struct ar8xxx_priv *priv, int addr, int regnum, u16 val)\n{\n\tu32 t;\n\tint ret;\n\n\tif (addr >= AR8216_NUM_PORTS)\n\t\treturn -EINVAL;\n\n\tt = (addr << AR8216_MDIO_CTRL_PHY_ADDR_S) |\n\t    (regnum << AR8216_MDIO_CTRL_REG_ADDR_S) |\n\t    AR8216_MDIO_CTRL_MASTER_EN |\n\t    AR8216_MDIO_CTRL_BUSY |\n\t    AR8216_MDIO_CTRL_CMD_WRITE |\n\t    val;\n\n\tar8xxx_write(priv, AR8216_REG_MDIO_CTRL, t);\n\tret = ar8xxx_reg_wait(priv, AR8216_REG_MDIO_CTRL,\n\t\t\t      AR8216_MDIO_CTRL_BUSY, 0, 5);\n\n\treturn ret;\n}\n\nstatic int\nar8229_hw_init(struct ar8xxx_priv *priv)\n{\n#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 5, 0)\n\tphy_interface_t phy_if_mode;\n#else\n\tint phy_if_mode;\n#endif\n\n\tif (priv->initialized)\n\t\treturn 0;\n\n\tar8xxx_write(priv, AR8216_REG_CTRL, AR8216_CTRL_RESET);\n\tar8xxx_reg_wait(priv, AR8216_REG_CTRL, AR8216_CTRL_RESET, 0, 1000);\n\n#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 5, 0)\n\tof_get_phy_mode(priv->pdev->of_node, &phy_if_mode);\n#else\n\tphy_if_mode = of_get_phy_mode(priv->pdev->of_node);\n#endif\n\n\tif (phy_if_mode == PHY_INTERFACE_MODE_GMII) {\n\t\tar8xxx_write(priv, AR8229_REG_OPER_MODE0,\n\t\t\t\t AR8229_OPER_MODE0_MAC_GMII_EN);\n\t} else if (phy_if_mode == PHY_INTERFACE_MODE_MII) {\n\t\tar8xxx_write(priv, AR8229_REG_OPER_MODE0,\n\t\t\t\t AR8229_OPER_MODE0_PHY_MII_EN);\n\t} else {\n\t\tpr_err(\"ar8229: unsupported mii mode\\n\");\n\t\treturn -EINVAL;\n\t}\n\n\tif (priv->port4_phy) {\n\t\tar8xxx_write(priv, AR8229_REG_OPER_MODE1,\n\t\t\t     AR8229_REG_OPER_MODE1_PHY4_MII_EN);\n\t\t/* disable port5 to prevent mii conflict */\n\t\tar8xxx_write(priv, AR8216_REG_PORT_STATUS(5), 0);\n\t}\n\n\tar8xxx_phy_init(priv);\n\n\tpriv->initialized = true;\n\treturn 0;\n}\n\nstatic void\nar8229_init_globals(struct ar8xxx_priv *priv)\n{\n\n\t/* Enable CPU port, and disable mirror port */\n\tar8xxx_write(priv, AR8216_REG_GLOBAL_CPUPORT,\n\t\t     AR8216_GLOBAL_CPUPORT_EN |\n\t\t     (15 << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));\n\n\t/* Setup TAG priority mapping */\n\tar8xxx_write(priv, AR8216_REG_TAG_PRIORITY, 0xfa50);\n\n\t/* Enable aging, MAC replacing */\n\tar8xxx_write(priv, AR8216_REG_ATU_CTRL,\n\t\t     0x2b /* 5 min age time */ |\n\t\t     AR8216_ATU_CTRL_AGE_EN |\n\t\t     AR8216_ATU_CTRL_LEARN_CHANGE);\n\n\t/* Enable ARP frame acknowledge */\n\tar8xxx_reg_set(priv, AR8229_REG_QM_CTRL,\n\t\t       AR8229_QM_CTRL_ARP_EN);\n\n\t/*\n\t * Enable Broadcast/unknown multicast and unicast frames\n\t * transmitted to the CPU port.\n\t */\n\tar8xxx_reg_set(priv, AR8216_REG_FLOOD_MASK,\n\t\t       AR8229_FLOOD_MASK_BC_DP(0) |\n\t\t       AR8229_FLOOD_MASK_MC_DP(0) |\n\t\t       AR8229_FLOOD_MASK_UC_DP(0));\n\n\t/* setup MTU */\n\tar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,\n\t\t   AR8236_GCTRL_MTU, AR8236_GCTRL_MTU);\n\n\t/* Enable MIB counters */\n\tar8xxx_reg_set(priv, AR8216_REG_MIB_FUNC,\n\t\t       AR8236_MIB_EN);\n\n\t/* setup Service TAG */\n\tar8xxx_rmw(priv, AR8216_REG_SERVICE_TAG, AR8216_SERVICE_TAG_M, 0);\n}\n\nstatic void\nar8229_init_port(struct ar8xxx_priv *priv, int port)\n{\n\t__ar8216_init_port(priv, port, true, true);\n}\n\n\nstatic int\nar7240sw_hw_init(struct ar8xxx_priv *priv)\n{\n\tif (priv->initialized)\n\t\treturn 0;\n\n\tar8xxx_write(priv, AR8216_REG_CTRL, AR8216_CTRL_RESET);\n\tar8xxx_reg_wait(priv, AR8216_REG_CTRL, AR8216_CTRL_RESET, 0, 1000);\n\n\tpriv->port4_phy = 1;\n\t/* disable port5 to prevent mii conflict */\n\tar8xxx_write(priv, AR8216_REG_PORT_STATUS(5), 0);\n\n\tar8xxx_phy_init(priv);\n\n\tpriv->initialized = true;\n\treturn 0;\n}\n\nstatic void\nar7240sw_init_globals(struct ar8xxx_priv *priv)\n{\n\n\t/* Enable CPU port, and disable mirror port */\n\tar8xxx_write(priv, AR8216_REG_GLOBAL_CPUPORT,\n\t\t     AR8216_GLOBAL_CPUPORT_EN |\n\t\t     (15 << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));\n\n\t/* Setup TAG priority mapping */\n\tar8xxx_write(priv, AR8216_REG_TAG_PRIORITY, 0xfa50);\n\n\t/* Enable ARP frame acknowledge, aging, MAC replacing */\n\tar8xxx_write(priv, AR8216_REG_ATU_CTRL,\n\t\tAR8216_ATU_CTRL_RESERVED |\n\t\t0x2b /* 5 min age time */ |\n\t\tAR8216_ATU_CTRL_AGE_EN |\n\t\tAR8216_ATU_CTRL_ARP_EN |\n\t\tAR8216_ATU_CTRL_LEARN_CHANGE);\n\n\t/* Enable Broadcast frames transmitted to the CPU */\n\tar8xxx_reg_set(priv, AR8216_REG_FLOOD_MASK,\n\t\t       AR8216_FM_CPU_BROADCAST_EN);\n\n\t/* setup MTU */\n\tar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,\n\t\t   AR8216_GCTRL_MTU,\n\t\t   AR8216_GCTRL_MTU);\n\n\t/* setup Service TAG */\n\tar8xxx_rmw(priv, AR8216_REG_SERVICE_TAG, AR8216_SERVICE_TAG_M, 0);\n}\n\nstatic void\nar7240sw_setup_port(struct ar8xxx_priv *priv, int port, u32 members)\n{\n\treturn __ar8216_setup_port(priv, port, members, false);\n}\n\nstatic void\nar8236_setup_port(struct ar8xxx_priv *priv, int port, u32 members)\n{\n\tu32 egress, ingress;\n\tu32 pvid;\n\n\tif (priv->vlan) {\n\t\tpvid = priv->vlan_id[priv->pvid[port]];\n\t\tif (priv->vlan_tagged & (1 << port))\n\t\t\tegress = AR8216_OUT_ADD_VLAN;\n\t\telse\n\t\t\tegress = AR8216_OUT_STRIP_VLAN;\n\t\tingress = AR8216_IN_SECURE;\n\t} else {\n\t\tpvid = port;\n\t\tegress = AR8216_OUT_KEEP;\n\t\tingress = AR8216_IN_PORT_ONLY;\n\t}\n\n\tar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),\n\t\t   AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |\n\t\t   AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |\n\t\t   AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,\n\t\t   AR8216_PORT_CTRL_LEARN |\n\t\t   (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |\n\t\t   (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));\n\n\tar8xxx_rmw(priv, AR8236_REG_PORT_VLAN(port),\n\t\t   AR8236_PORT_VLAN_DEFAULT_ID,\n\t\t   (pvid << AR8236_PORT_VLAN_DEFAULT_ID_S));\n\n\tar8xxx_rmw(priv, AR8236_REG_PORT_VLAN2(port),\n\t\t   AR8236_PORT_VLAN2_VLAN_MODE |\n\t\t   AR8236_PORT_VLAN2_MEMBER,\n\t\t   (ingress << AR8236_PORT_VLAN2_VLAN_MODE_S) |\n\t\t   (members << AR8236_PORT_VLAN2_MEMBER_S));\n}\n\nstatic void\nar8236_init_globals(struct ar8xxx_priv *priv)\n{\n\t/* enable jumbo frames */\n\tar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,\n\t\t   AR8316_GCTRL_MTU, 9018 + 8 + 2);\n\n\t/* enable cpu port to receive arp frames */\n\tar8xxx_reg_set(priv, AR8216_REG_ATU_CTRL,\n\t\t   AR8236_ATU_CTRL_RES);\n\n\t/*\n\t * Enable Broadcast/unknown multicast and unicast frames\n\t * transmitted to the CPU port.\n\t */\n\tar8xxx_reg_set(priv, AR8216_REG_FLOOD_MASK,\n\t\t       AR8229_FLOOD_MASK_BC_DP(0) |\n\t\t       AR8229_FLOOD_MASK_MC_DP(0) |\n\t\t       AR8229_FLOOD_MASK_UC_DP(0));\n\n\t/* Enable MIB counters */\n\tar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,\n\t\t   (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |\n\t\t   AR8236_MIB_EN);\n}\n\nstatic int\nar8316_hw_init(struct ar8xxx_priv *priv)\n{\n\tu32 val, newval;\n\n\tval = ar8xxx_read(priv, AR8316_REG_POSTRIP);\n\n\tif (priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {\n\t\tif (priv->port4_phy) {\n\t\t\t/* value taken from Ubiquiti RouterStation Pro */\n\t\t\tnewval = 0x81461bea;\n\t\t\tpr_info(\"ar8316: Using port 4 as PHY\\n\");\n\t\t} else {\n\t\t\tnewval = 0x01261be2;\n\t\t\tpr_info(\"ar8316: Using port 4 as switch port\\n\");\n\t\t}\n\t} else if (priv->phy->interface == PHY_INTERFACE_MODE_GMII) {\n\t\t/* value taken from AVM Fritz!Box 7390 sources */\n\t\tnewval = 0x010e5b71;\n\t} else {\n\t\t/* no known value for phy interface */\n\t\tpr_err(\"ar8316: unsupported mii mode: %d.\\n\",\n\t\t       priv->phy->interface);\n\t\treturn -EINVAL;\n\t}\n\n\tif (val == newval)\n\t\tgoto out;\n\n\tar8xxx_write(priv, AR8316_REG_POSTRIP, newval);\n\n\tif (priv->port4_phy &&\n\t    priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {\n\t\t/* work around for phy4 rgmii mode */\n\t\tar8xxx_phy_dbg_write(priv, 4, 0x12, 0x480c);\n\t\t/* rx delay */\n\t\tar8xxx_phy_dbg_write(priv, 4, 0x0, 0x824e);\n\t\t/* tx delay */\n\t\tar8xxx_phy_dbg_write(priv, 4, 0x5, 0x3d47);\n\t\tmsleep(1000);\n\t}\n\n\tar8xxx_phy_init(priv);\n\nout:\n\tpriv->initialized = true;\n\treturn 0;\n}\n\nstatic void\nar8316_init_globals(struct ar8xxx_priv *priv)\n{\n\t/* standard atheros magic */\n\tar8xxx_write(priv, 0x38, 0xc000050e);\n\n\t/* enable cpu port to receive multicast and broadcast frames */\n\tar8xxx_write(priv, AR8216_REG_FLOOD_MASK, 0x003f003f);\n\n\t/* enable jumbo frames */\n\tar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,\n\t\t   AR8316_GCTRL_MTU, 9018 + 8 + 2);\n\n\t/* Enable MIB counters */\n\tar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,\n\t\t   (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |\n\t\t   AR8236_MIB_EN);\n}\n\nint\nar8xxx_sw_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,\n\t\t   struct switch_val *val)\n{\n\tstruct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);\n\tpriv->vlan = !!val->value.i;\n\treturn 0;\n}\n\nint\nar8xxx_sw_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,\n\t\t   struct switch_val *val)\n{\n\tstruct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);\n\tval->value.i = priv->vlan;\n\treturn 0;\n}\n\n\nint\nar8xxx_sw_set_pvid(struct switch_dev *dev, int port, int vlan)\n{\n\tstruct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);\n\n\t/* make sure no invalid PVIDs get set */\n\n\tif (vlan < 0 || vlan >= dev->vlans ||\n\t    port < 0 || port >= AR8X16_MAX_PORTS)\n\t\treturn -EINVAL;\n\n\tpriv->pvid[port] = vlan;\n\treturn 0;\n}\n\nint\nar8xxx_sw_get_pvid(struct switch_dev *dev, int port, int *vlan)\n{\n\tstruct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);\n\n\tif (port < 0 || port >= AR8X16_MAX_PORTS)\n\t\treturn -EINVAL;\n\n\t*vlan = priv->pvid[port];\n\treturn 0;\n}\n\nstatic int\nar8xxx_sw_set_vid(struct switch_dev *dev, const struct switch_attr *attr,\n\t\t  struct switch_val *val)\n{\n\tstruct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);\n\n\tif (val->port_vlan >= dev->vlans)\n\t\treturn -EINVAL;\n\n\tpriv->vlan_id[val->port_vlan] = val->value.i;\n\treturn 0;\n}\n\nstatic int\nar8xxx_sw_get_vid(struct switch_dev *dev, const struct switch_attr *attr,\n\t\t  struct switch_val *val)\n{\n\tstruct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);\n\tval->value.i = priv->vlan_id[val->port_vlan];\n\treturn 0;\n}\n\nint\nar8xxx_sw_get_port_link(struct switch_dev *dev, int port,\n\t\t\tstruct switch_port_link *link)\n{\n\tstruct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);\n\n\tar8216_read_port_link(priv, port, link);\n\treturn 0;\n}\n\nstatic int\nar8xxx_sw_get_ports(struct switch_dev *dev, struct switch_val *val)\n{\n\tstruct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);\n\tu8 ports;\n\tint i;\n\n\tif (val->port_vlan >= dev->vlans)\n\t\treturn -EINVAL;\n\n\tports = priv->vlan_table[val->port_vlan];\n\tval->len = 0;\n\tfor (i = 0; i < dev->ports; i++) {\n\t\tstruct switch_port *p;\n\n\t\tif (!(ports & (1 << i)))\n\t\t\tcontinue;\n\n\t\tp = &val->value.ports[val->len++];\n\t\tp->id = i;\n\t\tif (priv->vlan_tagged & (1 << i))\n\t\t\tp->flags = (1 << SWITCH_PORT_FLAG_TAGGED);\n\t\telse\n\t\t\tp->flags = 0;\n\t}\n\treturn 0;\n}\n\nstatic int\nar8xxx_sw_set_ports(struct switch_dev *dev, struct switch_val *val)\n{\n\tstruct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);\n\tu8 *vt = &priv->vlan_table[val->port_vlan];\n\tint i, j;\n\n\t*vt = 0;\n\tfor (i = 0; i < val->len; i++) {\n\t\tstruct switch_port *p = &val->value.ports[i];\n\n\t\tif (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) {\n\t\t\tpriv->vlan_tagged |= (1 << p->id);\n\t\t} else {\n\t\t\tpriv->vlan_tagged &= ~(1 << p->id);\n\t\t\tpriv->pvid[p->id] = val->port_vlan;\n\n\t\t\t/* make sure that an untagged port does not\n\t\t\t * appear in other vlans */\n\t\t\tfor (j = 0; j < dev->vlans; j++) {\n\t\t\t\tif (j == val->port_vlan)\n\t\t\t\t\tcontinue;\n\t\t\t\tpriv->vlan_table[j] &= ~(1 << p->id);\n\t\t\t}\n\t\t}\n\n\t\t*vt |= 1 << p->id;\n\t}\n\treturn 0;\n}\n\nstatic void\nar8216_set_mirror_regs(struct ar8xxx_priv *priv)\n{\n\tint port;\n\n\t/* reset all mirror registers */\n\tar8xxx_rmw(priv, AR8216_REG_GLOBAL_CPUPORT,\n\t\t   AR8216_GLOBAL_CPUPORT_MIRROR_PORT,\n\t\t   (0xF << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));\n\tfor (port = 0; port < AR8216_NUM_PORTS; port++) {\n\t\tar8xxx_reg_clear(priv, AR8216_REG_PORT_CTRL(port),\n\t\t\t   AR8216_PORT_CTRL_MIRROR_RX);\n\n\t\tar8xxx_reg_clear(priv, AR8216_REG_PORT_CTRL(port),\n\t\t\t   AR8216_PORT_CTRL_MIRROR_TX);\n\t}\n\n\t/* now enable mirroring if necessary */\n\tif (priv->source_port >= AR8216_NUM_PORTS ||\n\t    priv->monitor_port >= AR8216_NUM_PORTS ||\n\t    priv->source_port == priv->monitor_port) {\n\t\treturn;\n\t}\n\n\tar8xxx_rmw(priv, AR8216_REG_GLOBAL_CPUPORT,\n\t\t   AR8216_GLOBAL_CPUPORT_MIRROR_PORT,\n\t\t   (priv->monitor_port << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));\n\n\tif (priv->mirror_rx)\n\t\tar8xxx_reg_set(priv, AR8216_REG_PORT_CTRL(priv->source_port),\n\t\t\t   AR8216_PORT_CTRL_MIRROR_RX);\n\n\tif (priv->mirror_tx)\n\t\tar8xxx_reg_set(priv, AR8216_REG_PORT_CTRL(priv->source_port),\n\t\t\t   AR8216_PORT_CTRL_MIRROR_TX);\n}\n\nstatic inline u32\nar8xxx_age_time_val(int age_time)\n{\n\treturn (age_time + AR8XXX_REG_ARL_CTRL_AGE_TIME_SECS / 2) /\n\t       AR8XXX_REG_ARL_CTRL_AGE_TIME_SECS;\n}\n\nstatic inline void\nar8xxx_set_age_time(struct ar8xxx_priv *priv, int reg)\n{\n\tu32 age_time = ar8xxx_age_time_val(priv->arl_age_time);\n\tar8xxx_rmw(priv, reg, AR8216_ATU_CTRL_AGE_TIME, age_time << AR8216_ATU_CTRL_AGE_TIME_S);\n}\n\nint\nar8xxx_sw_hw_apply(struct switch_dev *dev)\n{\n\tstruct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);\n\tconst struct ar8xxx_chip *chip = priv->chip;\n\tu8 portmask[AR8X16_MAX_PORTS];\n\tint i, j;\n\n\tmutex_lock(&priv->reg_mutex);\n\t/* flush all vlan translation unit entries */\n\tpriv->chip->vtu_flush(priv);\n\n\tmemset(portmask, 0, sizeof(portmask));\n\tif (!priv->init) {\n\t\t/* calculate the port destination masks and load vlans\n\t\t * into the vlan translation unit */\n\t\tfor (j = 0; j < dev->vlans; j++) {\n\t\t\tu8 vp = priv->vlan_table[j];\n\n\t\t\tif (!vp)\n\t\t\t\tcontinue;\n\n\t\t\tfor (i = 0; i < dev->ports; i++) {\n\t\t\t\tu8 mask = (1 << i);\n\t\t\t\tif (vp & mask)\n\t\t\t\t\tportmask[i] |= vp & ~mask;\n\t\t\t}\n\n\t\t\tchip->vtu_load_vlan(priv, priv->vlan_id[j],\n\t\t\t\t\t    priv->vlan_table[j]);\n\t\t}\n\t} else {\n\t\t/* vlan disabled:\n\t\t * isolate all ports, but connect them to the cpu port */\n\t\tfor (i = 0; i < dev->ports; i++) {\n\t\t\tif (i == AR8216_PORT_CPU)\n\t\t\t\tcontinue;\n\n\t\t\tportmask[i] = 1 << AR8216_PORT_CPU;\n\t\t\tportmask[AR8216_PORT_CPU] |= (1 << i);\n\t\t}\n\t}\n\n\t/* update the port destination mask registers and tag settings */\n\tfor (i = 0; i < dev->ports; i++) {\n\t\tchip->setup_port(priv, i, portmask[i]);\n\t}\n\n\tchip->set_mirror_regs(priv);\n\n\t/* set age time */\n\tif (chip->reg_arl_ctrl)\n\t\tar8xxx_set_age_time(priv, chip->reg_arl_ctrl);\n\n\tmutex_unlock(&priv->reg_mutex);\n\treturn 0;\n}\n\nint\nar8xxx_sw_reset_switch(struct switch_dev *dev)\n{\n\tstruct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);\n\tconst struct ar8xxx_chip *chip = priv->chip;\n\tint i;\n\n\tmutex_lock(&priv->reg_mutex);\n\tmemset(&priv->vlan, 0, sizeof(struct ar8xxx_priv) -\n\t\toffsetof(struct ar8xxx_priv, vlan));\n\n\tfor (i = 0; i < dev->vlans; i++)\n\t\tpriv->vlan_id[i] = i;\n\n\t/* Configure all ports */\n\tfor (i = 0; i < dev->ports; i++)\n\t\tchip->init_port(priv, i);\n\n\tpriv->mirror_rx = false;\n\tpriv->mirror_tx = false;\n\tpriv->source_port = 0;\n\tpriv->monitor_port = 0;\n\tpriv->arl_age_time = AR8XXX_DEFAULT_ARL_AGE_TIME;\n\n\tchip->init_globals(priv);\n\tchip->atu_flush(priv);\n\n\tmutex_unlock(&priv->reg_mutex);\n\n\treturn chip->sw_hw_apply(dev);\n}\n\nint\nar8xxx_sw_set_reset_mibs(struct switch_dev *dev,\n\t\t\t const struct switch_attr *attr,\n\t\t\t struct switch_val *val)\n{\n\tstruct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);\n\tunsigned int len;\n\tint ret;\n\n\tif (!ar8xxx_has_mib_counters(priv))\n\t\treturn -EOPNOTSUPP;\n\n\tmutex_lock(&priv->mib_lock);\n\n\tlen = priv->dev.ports * priv->chip->num_mibs *\n\t      sizeof(*priv->mib_stats);\n\tmemset(priv->mib_stats, '\\0', len);\n\tret = ar8xxx_mib_flush(priv);\n\tif (ret)\n\t\tgoto unlock;\n\n\tret = 0;\n\nunlock:\n\tmutex_unlock(&priv->mib_lock);\n\treturn ret;\n}\n\nint\nar8xxx_sw_set_mib_poll_interval(struct switch_dev *dev,\n\t\t\t       const struct switch_attr *attr,\n\t\t\t       struct switch_val *val)\n{\n\tstruct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);\n\n\tif (!ar8xxx_has_mib_counters(priv))\n\t\treturn -EOPNOTSUPP;\n\n\tar8xxx_mib_stop(priv);\n\tpriv->mib_poll_interval = val->value.i;\n\tar8xxx_mib_start(priv);\n\n\treturn 0;\n}\n\nint\nar8xxx_sw_get_mib_poll_interval(struct switch_dev *dev,\n\t\t\t       const struct switch_attr *attr,\n\t\t\t       struct switch_val *val)\n{\n\tstruct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);\n\n\tif (!ar8xxx_has_mib_counters(priv))\n\t\treturn -EOPNOTSUPP;\n\tval->value.i = priv->mib_poll_interval;\n\treturn 0;\n}\n\nint\nar8xxx_sw_set_mib_type(struct switch_dev *dev,\n\t\t\t       const struct switch_attr *attr,\n\t\t\t       struct switch_val *val)\n{\n\tstruct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);\n\n\tif (!ar8xxx_has_mib_counters(priv))\n\t\treturn -EOPNOTSUPP;\n\tpriv->mib_type = val->value.i;\n\treturn 0;\n}\n\nint\nar8xxx_sw_get_mib_type(struct switch_dev *dev,\n\t\t\t       const struct switch_attr *attr,\n\t\t\t       struct switch_val *val)\n{\n\tstruct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);\n\n\tif (!ar8xxx_has_mib_counters(priv))\n\t\treturn -EOPNOTSUPP;\n\tval->value.i = priv->mib_type;\n\treturn 0;\n}\n\nint\nar8xxx_sw_set_mirror_rx_enable(struct switch_dev *dev,\n\t\t\t       const struct switch_attr *attr,\n\t\t\t       struct switch_val *val)\n{\n\tstruct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);\n\n\tmutex_lock(&priv->reg_mutex);\n\tpriv->mirror_rx = !!val->value.i;\n\tpriv->chip->set_mirror_regs(priv);\n\tmutex_unlock(&priv->reg_mutex);\n\n\treturn 0;\n}\n\nint\nar8xxx_sw_get_mirror_rx_enable(struct switch_dev *dev,\n\t\t\t       const struct switch_attr *attr,\n\t\t\t       struct switch_val *val)\n{\n\tstruct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);\n\tval->value.i = priv->mirror_rx;\n\treturn 0;\n}\n\nint\nar8xxx_sw_set_mirror_tx_enable(struct switch_dev *dev,\n\t\t\t       const struct switch_attr *attr,\n\t\t\t       struct switch_val *val)\n{\n\tstruct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);\n\n\tmutex_lock(&priv->reg_mutex);\n\tpriv->mirror_tx = !!val->value.i;\n\tpriv->chip->set_mirror_regs(priv);\n\tmutex_unlock(&priv->reg_mutex);\n\n\treturn 0;\n}\n\nint\nar8xxx_sw_get_mirror_tx_enable(struct switch_dev *dev,\n\t\t\t       const struct switch_attr *attr,\n\t\t\t       struct switch_val *val)\n{\n\tstruct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);\n\tval->value.i = priv->mirror_tx;\n\treturn 0;\n}\n\nint\nar8xxx_sw_set_mirror_monitor_port(struct switch_dev *dev,\n\t\t\t\t  const struct switch_attr *attr,\n\t\t\t\t  struct switch_val *val)\n{\n\tstruct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);\n\n\tmutex_lock(&priv->reg_mutex);\n\tpriv->monitor_port = val->value.i;\n\tpriv->chip->set_mirror_regs(priv);\n\tmutex_unlock(&priv->reg_mutex);\n\n\treturn 0;\n}\n\nint\nar8xxx_sw_get_mirror_monitor_port(struct switch_dev *dev,\n\t\t\t\t  const struct switch_attr *attr,\n\t\t\t\t  struct switch_val *val)\n{\n\tstruct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);\n\tval->value.i = priv->monitor_port;\n\treturn 0;\n}\n\nint\nar8xxx_sw_set_mirror_source_port(struct switch_dev *dev,\n\t\t\t\t const struct switch_attr *attr,\n\t\t\t\t struct switch_val *val)\n{\n\tstruct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);\n\n\tmutex_lock(&priv->reg_mutex);\n\tpriv->source_port = val->value.i;\n\tpriv->chip->set_mirror_regs(priv);\n\tmutex_unlock(&priv->reg_mutex);\n\n\treturn 0;\n}\n\nint\nar8xxx_sw_get_mirror_source_port(struct switch_dev *dev,\n\t\t\t\t const struct switch_attr *attr,\n\t\t\t\t struct switch_val *val)\n{\n\tstruct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);\n\tval->value.i = priv->source_port;\n\treturn 0;\n}\n\nint\nar8xxx_sw_set_port_reset_mib(struct switch_dev *dev,\n\t\t\t     const struct switch_attr *attr,\n\t\t\t     struct switch_val *val)\n{\n\tstruct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);\n\tint port;\n\tint ret;\n\n\tif (!ar8xxx_has_mib_counters(priv))\n\t\treturn -EOPNOTSUPP;\n\n\tport = val->port_vlan;\n\tif (port >= dev->ports)\n\t\treturn -EINVAL;\n\n\tmutex_lock(&priv->mib_lock);\n\tret = ar8xxx_mib_capture(priv);\n\tif (ret)\n\t\tgoto unlock;\n\n\tar8xxx_mib_fetch_port_stat(priv, port, true);\n\n\tret = 0;\n\nunlock:\n\tmutex_unlock(&priv->mib_lock);\n\treturn ret;\n}\n\nstatic void\nar8xxx_byte_to_str(char *buf, int len, u64 byte)\n{\n\tunsigned long b;\n\tconst char *unit;\n\n\tif (byte >= 0x40000000) { /* 1 GiB */\n\t\tb = byte * 10 / 0x40000000;\n\t\tunit = \"GiB\";\n\t} else if (byte >= 0x100000) { /* 1 MiB */\n\t\tb = byte * 10 / 0x100000;\n\t\tunit = \"MiB\";\n\t} else if (byte >= 0x400) { /* 1 KiB */\n\t\tb = byte * 10 / 0x400;\n\t\tunit = \"KiB\";\n\t} else {\n\t\tb = byte;\n\t\tunit = \"Byte\";\n\t}\n\tif (strcmp(unit, \"Byte\"))\n\t\tsnprintf(buf, len, \"%lu.%lu %s\", b / 10, b % 10, unit);\n\telse\n\t\tsnprintf(buf, len, \"%lu %s\", b, unit);\n}\n\nint\nar8xxx_sw_get_port_mib(struct switch_dev *dev,\n\t\t       const struct switch_attr *attr,\n\t\t       struct switch_val *val)\n{\n\tstruct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);\n\tconst struct ar8xxx_chip *chip = priv->chip;\n\tu64 *mib_stats, mib_data;\n\tunsigned int port;\n\tint ret;\n\tchar *buf = priv->buf;\n\tchar buf1[64];\n\tconst char *mib_name;\n\tint i, len = 0;\n\tbool mib_stats_empty = true;\n\n\tif (!ar8xxx_has_mib_counters(priv) || !priv->mib_poll_interval)\n\t\treturn -EOPNOTSUPP;\n\n\tport = val->port_vlan;\n\tif (port >= dev->ports)\n\t\treturn -EINVAL;\n\n\tmutex_lock(&priv->mib_lock);\n\tret = ar8xxx_mib_capture(priv);\n\tif (ret)\n\t\tgoto unlock;\n\n\tar8xxx_mib_fetch_port_stat(priv, port, false);\n\n\tlen += snprintf(buf + len, sizeof(priv->buf) - len,\n\t\t\t\"MIB counters\\n\");\n\n\tmib_stats = &priv->mib_stats[port * chip->num_mibs];\n\tfor (i = 0; i < chip->num_mibs; i++) {\n\t\tif (chip->mib_decs[i].type > priv->mib_type)\n\t\t\tcontinue;\n\t\tmib_name = chip->mib_decs[i].name;\n\t\tmib_data = mib_stats[i];\n\t\tlen += snprintf(buf + len, sizeof(priv->buf) - len,\n\t\t\t\t\"%-12s: %llu\\n\", mib_name, mib_data);\n\t\tif ((!strcmp(mib_name, \"TxByte\") ||\n\t\t    !strcmp(mib_name, \"RxGoodByte\")) &&\n\t\t    mib_data >= 1024) {\n\t\t\tar8xxx_byte_to_str(buf1, sizeof(buf1), mib_data);\n\t\t\t--len; /* discard newline at the end of buf */\n\t\t\tlen += snprintf(buf + len, sizeof(priv->buf) - len,\n\t\t\t\t\t\" (%s)\\n\", buf1);\n\t\t}\n\t\tif (mib_stats_empty && mib_data)\n\t\t\tmib_stats_empty = false;\n\t}\n\n\tif (mib_stats_empty)\n\t\tlen = snprintf(buf, sizeof(priv->buf), \"No MIB data\");\n\n\tval->value.s = buf;\n\tval->len = len;\n\n\tret = 0;\n\nunlock:\n\tmutex_unlock(&priv->mib_lock);\n\treturn ret;\n}\n\nint\nar8xxx_sw_set_arl_age_time(struct switch_dev *dev, const struct switch_attr *attr,\n\t\t\t   struct switch_val *val)\n{\n\tstruct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);\n\tint age_time = val->value.i;\n\tu32 age_time_val;\n\n\tif (age_time < 0)\n\t\treturn -EINVAL;\n\n\tage_time_val = ar8xxx_age_time_val(age_time);\n\tif (age_time_val == 0 || age_time_val > 0xffff)\n\t\treturn -EINVAL;\n\n\tpriv->arl_age_time = age_time;\n\treturn 0;\n}\n\nint\nar8xxx_sw_get_arl_age_time(struct switch_dev *dev, const struct switch_attr *attr,\n                   struct switch_val *val)\n{\n\tstruct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);\n\tval->value.i = priv->arl_age_time;\n\treturn 0;\n}\n\nint\nar8xxx_sw_get_arl_table(struct switch_dev *dev,\n\t\t\tconst struct switch_attr *attr,\n\t\t\tstruct switch_val *val)\n{\n\tstruct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);\n\tstruct mii_bus *bus = priv->mii_bus;\n\tconst struct ar8xxx_chip *chip = priv->chip;\n\tchar *buf = priv->arl_buf;\n\tint i, j, k, len = 0;\n\tstruct arl_entry *a, *a1;\n\tu32 status;\n\n\tif (!chip->get_arl_entry)\n\t\treturn -EOPNOTSUPP;\n\n\tmutex_lock(&priv->reg_mutex);\n\tmutex_lock(&bus->mdio_lock);\n\n\tchip->get_arl_entry(priv, NULL, NULL, AR8XXX_ARL_INITIALIZE);\n\n\tfor(i = 0; i < AR8XXX_NUM_ARL_RECORDS; ++i) {\n\t\ta = &priv->arl_table[i];\n\t\tduplicate:\n\t\tchip->get_arl_entry(priv, a, &status, AR8XXX_ARL_GET_NEXT);\n\n\t\tif (!status)\n\t\t\tbreak;\n\n\t\t/* avoid duplicates\n\t\t * ARL table can include multiple valid entries\n\t\t * per MAC, just with differing status codes\n\t\t */\n\t\tfor (j = 0; j < i; ++j) {\n\t\t\ta1 = &priv->arl_table[j];\n\t\t\tif (!memcmp(a->mac, a1->mac, sizeof(a->mac))) {\n\t\t\t\t/* ignore ports already seen in former entry */\n\t\t\t\ta->portmap &= ~a1->portmap;\n\t\t\t\tif (!a->portmap)\n\t\t\t\t\tgoto duplicate;\n\t\t\t}\n\t\t}\n\t}\n\n\tmutex_unlock(&bus->mdio_lock);\n\n\tlen += snprintf(buf + len, sizeof(priv->arl_buf) - len,\n                        \"address resolution table\\n\");\n\n\tif (i == AR8XXX_NUM_ARL_RECORDS)\n\t\tlen += snprintf(buf + len, sizeof(priv->arl_buf) - len,\n\t\t\t\t\"Too many entries found, displaying the first %d only!\\n\",\n\t\t\t\tAR8XXX_NUM_ARL_RECORDS);\n\n\tfor (j = 0; j < priv->dev.ports; ++j) {\n\t\tfor (k = 0; k < i; ++k) {\n\t\t\ta = &priv->arl_table[k];\n\t\t\tif (!(a->portmap & BIT(j)))\n\t\t\t\tcontinue;\n\t\t\tlen += snprintf(buf + len, sizeof(priv->arl_buf) - len,\n\t\t\t\t\t\"Port %d: MAC %02x:%02x:%02x:%02x:%02x:%02x\\n\",\n\t\t\t\t\tj,\n\t\t\t\t\ta->mac[5], a->mac[4], a->mac[3],\n\t\t\t\t\ta->mac[2], a->mac[1], a->mac[0]);\n\t\t}\n\t}\n\n\tval->value.s = buf;\n\tval->len = len;\n\n\tmutex_unlock(&priv->reg_mutex);\n\n\treturn 0;\n}\n\nint\nar8xxx_sw_set_flush_arl_table(struct switch_dev *dev,\n\t\t\t      const struct switch_attr *attr,\n\t\t\t      struct switch_val *val)\n{\n\tstruct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);\n\tint ret;\n\n\tmutex_lock(&priv->reg_mutex);\n\tret = priv->chip->atu_flush(priv);\n\tmutex_unlock(&priv->reg_mutex);\n\n\treturn ret;\n}\n\nint\nar8xxx_sw_set_flush_port_arl_table(struct switch_dev *dev,\n\t\t\t\t   const struct switch_attr *attr,\n\t\t\t\t   struct switch_val *val)\n{\n\tstruct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);\n\tint port, ret;\n\n\tport = val->port_vlan;\n\tif (port >= dev->ports)\n\t\treturn -EINVAL;\n\n\tmutex_lock(&priv->reg_mutex);\n\tret = priv->chip->atu_flush_port(priv, port);\n\tmutex_unlock(&priv->reg_mutex);\n\n\treturn ret;\n}\n\nint\nar8xxx_sw_get_port_stats(struct switch_dev *dev, int port,\n\t\t\tstruct switch_port_stats *stats)\n{\n\tstruct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);\n\tu64 *mib_stats;\n\n\tif (!ar8xxx_has_mib_counters(priv) || !priv->mib_poll_interval)\n\t\treturn -EOPNOTSUPP;\n\n\tif (!(priv->chip->mib_rxb_id || priv->chip->mib_txb_id))\n\t\treturn -EOPNOTSUPP;\n\n\tif (port >= dev->ports)\n\t\treturn -EINVAL;\n\n\tmutex_lock(&priv->mib_lock);\n\n\tmib_stats = &priv->mib_stats[port * priv->chip->num_mibs];\n\n\tstats->tx_bytes = mib_stats[priv->chip->mib_txb_id];\n\tstats->rx_bytes = mib_stats[priv->chip->mib_rxb_id];\n\n\tmutex_unlock(&priv->mib_lock);\n\treturn 0;\n}\n\nstatic int\nar8xxx_phy_read(struct mii_bus *bus, int phy_addr, int reg_addr)\n{\n\tstruct ar8xxx_priv *priv = bus->priv;\n\treturn priv->chip->phy_read(priv, phy_addr, reg_addr);\n}\n\nstatic int\nar8xxx_phy_write(struct mii_bus *bus, int phy_addr, int reg_addr,\n\t\t u16 reg_val)\n{\n\tstruct ar8xxx_priv *priv = bus->priv;\n\treturn priv->chip->phy_write(priv, phy_addr, reg_addr, reg_val);\n}\n\nstatic const struct switch_attr ar8xxx_sw_attr_globals[] = {\n\t{\n\t\t.type = SWITCH_TYPE_INT,\n\t\t.name = \"enable_vlan\",\n\t\t.description = \"Enable VLAN mode\",\n\t\t.set = ar8xxx_sw_set_vlan,\n\t\t.get = ar8xxx_sw_get_vlan,\n\t\t.max = 1\n\t},\n\t{\n\t\t.type = SWITCH_TYPE_NOVAL,\n\t\t.name = \"reset_mibs\",\n\t\t.description = \"Reset all MIB counters\",\n\t\t.set = ar8xxx_sw_set_reset_mibs,\n\t},\n\t{\n\t\t.type = SWITCH_TYPE_INT,\n\t\t.name = \"ar8xxx_mib_poll_interval\",\n\t\t.description = \"MIB polling interval in msecs (0 to disable)\",\n\t\t.set = ar8xxx_sw_set_mib_poll_interval,\n\t\t.get = ar8xxx_sw_get_mib_poll_interval\n\t},\n\t{\n\t\t.type = SWITCH_TYPE_INT,\n\t\t.name = \"ar8xxx_mib_type\",\n\t\t.description = \"MIB type (0=basic 1=extended)\",\n\t\t.set = ar8xxx_sw_set_mib_type,\n\t\t.get = ar8xxx_sw_get_mib_type\n\t},\n\t{\n\t\t.type = SWITCH_TYPE_INT,\n\t\t.name = \"enable_mirror_rx\",\n\t\t.description = \"Enable mirroring of RX packets\",\n\t\t.set = ar8xxx_sw_set_mirror_rx_enable,\n\t\t.get = ar8xxx_sw_get_mirror_rx_enable,\n\t\t.max = 1\n\t},\n\t{\n\t\t.type = SWITCH_TYPE_INT,\n\t\t.name = \"enable_mirror_tx\",\n\t\t.description = \"Enable mirroring of TX packets\",\n\t\t.set = ar8xxx_sw_set_mirror_tx_enable,\n\t\t.get = ar8xxx_sw_get_mirror_tx_enable,\n\t\t.max = 1\n\t},\n\t{\n\t\t.type = SWITCH_TYPE_INT,\n\t\t.name = \"mirror_monitor_port\",\n\t\t.description = \"Mirror monitor port\",\n\t\t.set = ar8xxx_sw_set_mirror_monitor_port,\n\t\t.get = ar8xxx_sw_get_mirror_monitor_port,\n\t\t.max = AR8216_NUM_PORTS - 1\n\t},\n\t{\n\t\t.type = SWITCH_TYPE_INT,\n\t\t.name = \"mirror_source_port\",\n\t\t.description = \"Mirror source port\",\n\t\t.set = ar8xxx_sw_set_mirror_source_port,\n\t\t.get = ar8xxx_sw_get_mirror_source_port,\n\t\t.max = AR8216_NUM_PORTS - 1\n \t},\n\t{\n\t\t.type = SWITCH_TYPE_STRING,\n\t\t.name = \"arl_table\",\n\t\t.description = \"Get ARL table\",\n\t\t.set = NULL,\n\t\t.get = ar8xxx_sw_get_arl_table,\n\t},\n\t{\n\t\t.type = SWITCH_TYPE_NOVAL,\n\t\t.name = \"flush_arl_table\",\n\t\t.description = \"Flush ARL table\",\n\t\t.set = ar8xxx_sw_set_flush_arl_table,\n\t},\n};\n\nconst struct switch_attr ar8xxx_sw_attr_port[] = {\n\t{\n\t\t.type = SWITCH_TYPE_NOVAL,\n\t\t.name = \"reset_mib\",\n\t\t.description = \"Reset single port MIB counters\",\n\t\t.set = ar8xxx_sw_set_port_reset_mib,\n\t},\n\t{\n\t\t.type = SWITCH_TYPE_STRING,\n\t\t.name = \"mib\",\n\t\t.description = \"Get port's MIB counters\",\n\t\t.set = NULL,\n\t\t.get = ar8xxx_sw_get_port_mib,\n\t},\n\t{\n\t\t.type = SWITCH_TYPE_NOVAL,\n\t\t.name = \"flush_arl_table\",\n\t\t.description = \"Flush port's ARL table entries\",\n\t\t.set = ar8xxx_sw_set_flush_port_arl_table,\n\t},\n};\n\nconst struct switch_attr ar8xxx_sw_attr_vlan[1] = {\n\t{\n\t\t.type = SWITCH_TYPE_INT,\n\t\t.name = \"vid\",\n\t\t.description = \"VLAN ID (0-4094)\",\n\t\t.set = ar8xxx_sw_set_vid,\n\t\t.get = ar8xxx_sw_get_vid,\n\t\t.max = 4094,\n\t},\n};\n\nstatic const struct switch_dev_ops ar8xxx_sw_ops = {\n\t.attr_global = {\n\t\t.attr = ar8xxx_sw_attr_globals,\n\t\t.n_attr = ARRAY_SIZE(ar8xxx_sw_attr_globals),\n\t},\n\t.attr_port = {\n\t\t.attr = ar8xxx_sw_attr_port,\n\t\t.n_attr = ARRAY_SIZE(ar8xxx_sw_attr_port),\n\t},\n\t.attr_vlan = {\n\t\t.attr = ar8xxx_sw_attr_vlan,\n\t\t.n_attr = ARRAY_SIZE(ar8xxx_sw_attr_vlan),\n\t},\n\t.get_port_pvid = ar8xxx_sw_get_pvid,\n\t.set_port_pvid = ar8xxx_sw_set_pvid,\n\t.get_vlan_ports = ar8xxx_sw_get_ports,\n\t.set_vlan_ports = ar8xxx_sw_set_ports,\n\t.apply_config = ar8xxx_sw_hw_apply,\n\t.reset_switch = ar8xxx_sw_reset_switch,\n\t.get_port_link = ar8xxx_sw_get_port_link,\n\t.get_port_stats = ar8xxx_sw_get_port_stats,\n};\n\nstatic const struct ar8xxx_chip ar7240sw_chip = {\n\t.caps = AR8XXX_CAP_MIB_COUNTERS,\n\n\t.reg_port_stats_start = 0x20000,\n\t.reg_port_stats_length = 0x100,\n\t.reg_arl_ctrl = AR8216_REG_ATU_CTRL,\n\n\t.name = \"Atheros AR724X/AR933X built-in\",\n\t.ports = AR7240SW_NUM_PORTS,\n\t.vlans = AR8216_NUM_VLANS,\n\t.swops = &ar8xxx_sw_ops,\n\n\t.hw_init = ar7240sw_hw_init,\n\t.init_globals = ar7240sw_init_globals,\n\t.init_port = ar8229_init_port,\n\t.phy_read = ar8216_phy_read,\n\t.phy_write = ar8216_phy_write,\n\t.setup_port = ar7240sw_setup_port,\n\t.read_port_status = ar8216_read_port_status,\n\t.atu_flush = ar8216_atu_flush,\n\t.atu_flush_port = ar8216_atu_flush_port,\n\t.vtu_flush = ar8216_vtu_flush,\n\t.vtu_load_vlan = ar8216_vtu_load_vlan,\n\t.set_mirror_regs = ar8216_set_mirror_regs,\n\t.get_arl_entry = ar8216_get_arl_entry,\n\t.sw_hw_apply = ar8xxx_sw_hw_apply,\n\n\t.num_mibs = ARRAY_SIZE(ar8236_mibs),\n\t.mib_decs = ar8236_mibs,\n\t.mib_func = AR8216_REG_MIB_FUNC,\n\t.mib_rxb_id = AR8236_MIB_RXB_ID,\n\t.mib_txb_id = AR8236_MIB_TXB_ID,\n};\n\nstatic const struct ar8xxx_chip ar8216_chip = {\n\t.caps = AR8XXX_CAP_MIB_COUNTERS,\n\n\t.reg_port_stats_start = 0x19000,\n\t.reg_port_stats_length = 0xa0,\n\t.reg_arl_ctrl = AR8216_REG_ATU_CTRL,\n\n\t.name = \"Atheros AR8216\",\n\t.ports = AR8216_NUM_PORTS,\n\t.vlans = AR8216_NUM_VLANS,\n\t.swops = &ar8xxx_sw_ops,\n\n\t.hw_init = ar8216_hw_init,\n\t.init_globals = ar8216_init_globals,\n\t.init_port = ar8216_init_port,\n\t.setup_port = ar8216_setup_port,\n\t.read_port_status = ar8216_read_port_status,\n\t.atu_flush = ar8216_atu_flush,\n\t.atu_flush_port = ar8216_atu_flush_port,\n\t.vtu_flush = ar8216_vtu_flush,\n\t.vtu_load_vlan = ar8216_vtu_load_vlan,\n\t.set_mirror_regs = ar8216_set_mirror_regs,\n\t.get_arl_entry = ar8216_get_arl_entry,\n\t.sw_hw_apply = ar8xxx_sw_hw_apply,\n\n\t.num_mibs = ARRAY_SIZE(ar8216_mibs),\n\t.mib_decs = ar8216_mibs,\n\t.mib_func = AR8216_REG_MIB_FUNC,\n\t.mib_rxb_id = AR8216_MIB_RXB_ID,\n\t.mib_txb_id = AR8216_MIB_TXB_ID,\n};\n\nstatic const struct ar8xxx_chip ar8229_chip = {\n\t.caps = AR8XXX_CAP_MIB_COUNTERS,\n\n\t.reg_port_stats_start = 0x20000,\n\t.reg_port_stats_length = 0x100,\n\t.reg_arl_ctrl = AR8216_REG_ATU_CTRL,\n\n\t.name = \"Atheros AR8229\",\n\t.ports = AR8216_NUM_PORTS,\n\t.vlans = AR8216_NUM_VLANS,\n\t.swops = &ar8xxx_sw_ops,\n\n\t.hw_init = ar8229_hw_init,\n\t.init_globals = ar8229_init_globals,\n\t.init_port = ar8229_init_port,\n\t.phy_read = ar8216_phy_read,\n\t.phy_write = ar8216_phy_write,\n\t.setup_port = ar8236_setup_port,\n\t.read_port_status = ar8216_read_port_status,\n\t.atu_flush = ar8216_atu_flush,\n\t.atu_flush_port = ar8216_atu_flush_port,\n\t.vtu_flush = ar8216_vtu_flush,\n\t.vtu_load_vlan = ar8216_vtu_load_vlan,\n\t.set_mirror_regs = ar8216_set_mirror_regs,\n\t.get_arl_entry = ar8216_get_arl_entry,\n\t.sw_hw_apply = ar8xxx_sw_hw_apply,\n\n\t.num_mibs = ARRAY_SIZE(ar8236_mibs),\n\t.mib_decs = ar8236_mibs,\n\t.mib_func = AR8216_REG_MIB_FUNC,\n\t.mib_rxb_id = AR8236_MIB_RXB_ID,\n\t.mib_txb_id = AR8236_MIB_TXB_ID,\n};\n\nstatic const struct ar8xxx_chip ar8236_chip = {\n\t.caps = AR8XXX_CAP_MIB_COUNTERS,\n\n\t.reg_port_stats_start = 0x20000,\n\t.reg_port_stats_length = 0x100,\n\t.reg_arl_ctrl = AR8216_REG_ATU_CTRL,\n\n\t.name = \"Atheros AR8236\",\n\t.ports = AR8216_NUM_PORTS,\n\t.vlans = AR8216_NUM_VLANS,\n\t.swops = &ar8xxx_sw_ops,\n\n\t.hw_init = ar8216_hw_init,\n\t.init_globals = ar8236_init_globals,\n\t.init_port = ar8216_init_port,\n\t.setup_port = ar8236_setup_port,\n\t.read_port_status = ar8216_read_port_status,\n\t.atu_flush = ar8216_atu_flush,\n\t.atu_flush_port = ar8216_atu_flush_port,\n\t.vtu_flush = ar8216_vtu_flush,\n\t.vtu_load_vlan = ar8216_vtu_load_vlan,\n\t.set_mirror_regs = ar8216_set_mirror_regs,\n\t.get_arl_entry = ar8216_get_arl_entry,\n\t.sw_hw_apply = ar8xxx_sw_hw_apply,\n\n\t.num_mibs = ARRAY_SIZE(ar8236_mibs),\n\t.mib_decs = ar8236_mibs,\n\t.mib_func = AR8216_REG_MIB_FUNC,\n\t.mib_rxb_id = AR8236_MIB_RXB_ID,\n\t.mib_txb_id = AR8236_MIB_TXB_ID,\n};\n\nstatic const struct ar8xxx_chip ar8316_chip = {\n\t.caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,\n\n\t.reg_port_stats_start = 0x20000,\n\t.reg_port_stats_length = 0x100,\n\t.reg_arl_ctrl = AR8216_REG_ATU_CTRL,\n\n\t.name = \"Atheros AR8316\",\n\t.ports = AR8216_NUM_PORTS,\n\t.vlans = AR8X16_MAX_VLANS,\n\t.swops = &ar8xxx_sw_ops,\n\n\t.hw_init = ar8316_hw_init,\n\t.init_globals = ar8316_init_globals,\n\t.init_port = ar8216_init_port,\n\t.setup_port = ar8216_setup_port,\n\t.read_port_status = ar8216_read_port_status,\n\t.atu_flush = ar8216_atu_flush,\n\t.atu_flush_port = ar8216_atu_flush_port,\n\t.vtu_flush = ar8216_vtu_flush,\n\t.vtu_load_vlan = ar8216_vtu_load_vlan,\n\t.set_mirror_regs = ar8216_set_mirror_regs,\n\t.get_arl_entry = ar8216_get_arl_entry,\n\t.sw_hw_apply = ar8xxx_sw_hw_apply,\n\n\t.num_mibs = ARRAY_SIZE(ar8236_mibs),\n\t.mib_decs = ar8236_mibs,\n\t.mib_func = AR8216_REG_MIB_FUNC,\n\t.mib_rxb_id = AR8236_MIB_RXB_ID,\n\t.mib_txb_id = AR8236_MIB_TXB_ID,\n};\n\nstatic int\nar8xxx_read_id(struct ar8xxx_priv *priv)\n{\n\tu32 val;\n\tu16 id;\n\tint i;\n\n\tval = ar8xxx_read(priv, AR8216_REG_CTRL);\n\tif (val == ~0)\n\t\treturn -ENODEV;\n\n\tid = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);\n\tfor (i = 0; i < AR8X16_PROBE_RETRIES; i++) {\n\t\tu16 t;\n\n\t\tval = ar8xxx_read(priv, AR8216_REG_CTRL);\n\t\tif (val == ~0)\n\t\t\treturn -ENODEV;\n\n\t\tt = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);\n\t\tif (t != id)\n\t\t\treturn -ENODEV;\n\t}\n\n\tpriv->chip_ver = (id & AR8216_CTRL_VERSION) >> AR8216_CTRL_VERSION_S;\n\tpriv->chip_rev = (id & AR8216_CTRL_REVISION);\n\treturn 0;\n}\n\nstatic int\nar8xxx_id_chip(struct ar8xxx_priv *priv)\n{\n\tint ret;\n\n\tret = ar8xxx_read_id(priv);\n\tif(ret)\n\t\treturn ret;\n\n\tswitch (priv->chip_ver) {\n\tcase AR8XXX_VER_AR8216:\n\t\tpriv->chip = &ar8216_chip;\n\t\tbreak;\n\tcase AR8XXX_VER_AR8236:\n\t\tpriv->chip = &ar8236_chip;\n\t\tbreak;\n\tcase AR8XXX_VER_AR8316:\n\t\tpriv->chip = &ar8316_chip;\n\t\tbreak;\n\tcase AR8XXX_VER_AR8327:\n\t\tpriv->chip = &ar8327_chip;\n\t\tbreak;\n\tcase AR8XXX_VER_AR8337:\n\t\tpriv->chip = &ar8337_chip;\n\t\tbreak;\n\tdefault:\n\t\tpr_err(\"ar8216: Unknown Atheros device [ver=%d, rev=%d]\\n\",\n\t\t       priv->chip_ver, priv->chip_rev);\n\n\t\treturn -ENODEV;\n\t}\n\n\treturn 0;\n}\n\nstatic void\nar8xxx_mib_work_func(struct work_struct *work)\n{\n\tstruct ar8xxx_priv *priv;\n\tint err, i;\n\n\tpriv = container_of(work, struct ar8xxx_priv, mib_work.work);\n\n\tmutex_lock(&priv->mib_lock);\n\n\terr = ar8xxx_mib_capture(priv);\n\tif (err)\n\t\tgoto next_attempt;\n\n\tfor (i = 0; i < priv->dev.ports; i++)\n\t\tar8xxx_mib_fetch_port_stat(priv, i, false);\n\nnext_attempt:\n\tmutex_unlock(&priv->mib_lock);\n\tschedule_delayed_work(&priv->mib_work,\n\t\t\t      msecs_to_jiffies(priv->mib_poll_interval));\n}\n\nstatic int\nar8xxx_mib_init(struct ar8xxx_priv *priv)\n{\n\tunsigned int len;\n\n\tif (!ar8xxx_has_mib_counters(priv))\n\t\treturn 0;\n\n\tBUG_ON(!priv->chip->mib_decs || !priv->chip->num_mibs);\n\n\tlen = priv->dev.ports * priv->chip->num_mibs *\n\t      sizeof(*priv->mib_stats);\n\tpriv->mib_stats = kzalloc(len, GFP_KERNEL);\n\n\tif (!priv->mib_stats)\n\t\treturn -ENOMEM;\n\n\treturn 0;\n}\n\nstatic void\nar8xxx_mib_start(struct ar8xxx_priv *priv)\n{\n\tif (!ar8xxx_has_mib_counters(priv) || !priv->mib_poll_interval)\n\t\treturn;\n\n\tschedule_delayed_work(&priv->mib_work,\n\t\t\t      msecs_to_jiffies(priv->mib_poll_interval));\n}\n\nstatic void\nar8xxx_mib_stop(struct ar8xxx_priv *priv)\n{\n\tif (!ar8xxx_has_mib_counters(priv) || !priv->mib_poll_interval)\n\t\treturn;\n\n\tcancel_delayed_work_sync(&priv->mib_work);\n}\n\nstatic struct ar8xxx_priv *\nar8xxx_create(void)\n{\n\tstruct ar8xxx_priv *priv;\n\n\tpriv = kzalloc(sizeof(struct ar8xxx_priv), GFP_KERNEL);\n\tif (priv == NULL)\n\t\treturn NULL;\n\n\tmutex_init(&priv->reg_mutex);\n\tmutex_init(&priv->mib_lock);\n\tINIT_DELAYED_WORK(&priv->mib_work, ar8xxx_mib_work_func);\n\n\treturn priv;\n}\n\nstatic void\nar8xxx_free(struct ar8xxx_priv *priv)\n{\n\tif (priv->chip && priv->chip->cleanup)\n\t\tpriv->chip->cleanup(priv);\n\n\tkfree(priv->chip_data);\n\tkfree(priv->mib_stats);\n\tkfree(priv);\n}\n\nstatic int\nar8xxx_probe_switch(struct ar8xxx_priv *priv)\n{\n\tconst struct ar8xxx_chip *chip;\n\tstruct switch_dev *swdev;\n\tint ret;\n\n\tchip = priv->chip;\n\n\tswdev = &priv->dev;\n\tswdev->cpu_port = AR8216_PORT_CPU;\n\tswdev->name = chip->name;\n\tswdev->vlans = chip->vlans;\n\tswdev->ports = chip->ports;\n\tswdev->ops = chip->swops;\n\n\tret = ar8xxx_mib_init(priv);\n\tif (ret)\n\t\treturn ret;\n\n\treturn 0;\n}\n\nstatic int\nar8xxx_start(struct ar8xxx_priv *priv)\n{\n\tint ret;\n\n\tpriv->init = true;\n\n\tret = priv->chip->hw_init(priv);\n\tif (ret)\n\t\treturn ret;\n\n\tret = ar8xxx_sw_reset_switch(&priv->dev);\n\tif (ret)\n\t\treturn ret;\n\n\tpriv->init = false;\n\n\tar8xxx_mib_start(priv);\n\n\treturn 0;\n}\n\nstatic int\nar8xxx_phy_config_init(struct phy_device *phydev)\n{\n\tstruct ar8xxx_priv *priv = phydev->priv;\n#ifdef CONFIG_ETHERNET_PACKET_MANGLE\n\tstruct net_device *dev = phydev->attached_dev;\n#endif\n\tint ret;\n\n\tif (WARN_ON(!priv))\n\t\treturn -ENODEV;\n\n\tif (priv->chip->config_at_probe)\n\t\treturn ar8xxx_phy_check_aneg(phydev);\n\n\tpriv->phy = phydev;\n\n\tif (phydev->mdio.addr != 0) {\n\t\tif (chip_is_ar8316(priv)) {\n\t\t\t/* switch device has been initialized, reinit */\n\t\t\tpriv->dev.ports = (AR8216_NUM_PORTS - 1);\n\t\t\tpriv->initialized = false;\n\t\t\tpriv->port4_phy = true;\n\t\t\tar8316_hw_init(priv);\n\t\t\treturn 0;\n\t\t}\n\n\t\treturn 0;\n\t}\n\n\tret = ar8xxx_start(priv);\n\tif (ret)\n\t\treturn ret;\n\n#ifdef CONFIG_ETHERNET_PACKET_MANGLE\n\t/* VID fixup only needed on ar8216 */\n\tif (chip_is_ar8216(priv)) {\n\t\tdev->phy_ptr = priv;\n#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,15,0)\n\t\tdev->extra_priv_flags |= IFF_NO_IP_ALIGN;\n#else\n\t\tdev->priv_flags |= IFF_NO_IP_ALIGN;\n#endif\n\t\tdev->eth_mangle_rx = ar8216_mangle_rx;\n\t\tdev->eth_mangle_tx = ar8216_mangle_tx;\n\t}\n#endif\n\n\treturn 0;\n}\n\nstatic bool\nar8xxx_check_link_states(struct ar8xxx_priv *priv)\n{\n\tbool link_new, changed = false;\n\tu32 status;\n\tint i;\n\n\tmutex_lock(&priv->reg_mutex);\n\n\tfor (i = 0; i < priv->dev.ports; i++) {\n\t\tstatus = priv->chip->read_port_status(priv, i);\n\t\tlink_new = !!(status & AR8216_PORT_STATUS_LINK_UP);\n\t\tif (link_new == priv->link_up[i])\n\t\t\tcontinue;\n\n\t\tpriv->link_up[i] = link_new;\n\t\tchanged = true;\n\t\t/* flush ARL entries for this port if it went down*/\n\t\tif (!link_new)\n\t\t\tpriv->chip->atu_flush_port(priv, i);\n\t\tdev_info(&priv->phy->mdio.dev, \"Port %d is %s\\n\",\n\t\t\t i, link_new ? \"up\" : \"down\");\n\t}\n\n\tmutex_unlock(&priv->reg_mutex);\n\n\treturn changed;\n}\n\nstatic int\nar8xxx_phy_read_status(struct phy_device *phydev)\n{\n\tstruct ar8xxx_priv *priv = phydev->priv;\n\tstruct switch_port_link link;\n\n\t/* check for switch port link changes */\n\tar8xxx_check_link_states(priv);\n\n\tif (phydev->mdio.addr != 0)\n\t\treturn genphy_read_status(phydev);\n\n\tar8216_read_port_link(priv, phydev->mdio.addr, &link);\n\tphydev->link = !!link.link;\n\tif (!phydev->link)\n\t\treturn 0;\n\n\tswitch (link.speed) {\n\tcase SWITCH_PORT_SPEED_10:\n\t\tphydev->speed = SPEED_10;\n\t\tbreak;\n\tcase SWITCH_PORT_SPEED_100:\n\t\tphydev->speed = SPEED_100;\n\t\tbreak;\n\tcase SWITCH_PORT_SPEED_1000:\n\t\tphydev->speed = SPEED_1000;\n\t\tbreak;\n\tdefault:\n\t\tphydev->speed = 0;\n\t}\n\tphydev->duplex = link.duplex ? DUPLEX_FULL : DUPLEX_HALF;\n\n\tphydev->state = PHY_RUNNING;\n\tnetif_carrier_on(phydev->attached_dev);\n\tif (phydev->adjust_link)\n\t\tphydev->adjust_link(phydev->attached_dev);\n\n\treturn 0;\n}\n\nstatic int\nar8xxx_phy_config_aneg(struct phy_device *phydev)\n{\n\tif (phydev->mdio.addr == 0)\n\t\treturn 0;\n\n\treturn genphy_config_aneg(phydev);\n}\n\nstatic int\nar8xxx_get_features(struct phy_device *phydev)\n{\n\tstruct ar8xxx_priv *priv = phydev->priv;\n\n\tlinkmode_copy(phydev->supported, PHY_BASIC_FEATURES);\n\tif (ar8xxx_has_gige(priv))\n\t\tlinkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, phydev->supported);\n\n\treturn 0;\n}\n\nstatic const u32 ar8xxx_phy_ids[] = {\n\t0x004dd033,\n\t0x004dd034, /* AR8327 */\n\t0x004dd036, /* AR8337 */\n\t0x004dd041,\n\t0x004dd042,\n\t0x004dd043, /* AR8236 */\n};\n\nstatic bool\nar8xxx_phy_match(u32 phy_id)\n{\n\tint i;\n\n\tfor (i = 0; i < ARRAY_SIZE(ar8xxx_phy_ids); i++)\n\t\tif (phy_id == ar8xxx_phy_ids[i])\n\t\t\treturn true;\n\n\treturn false;\n}\n\nstatic bool\nar8xxx_is_possible(struct mii_bus *bus)\n{\n\tunsigned int i, found_phys = 0;\n\n\tfor (i = 0; i < 5; i++) {\n\t\tu32 phy_id;\n\n\t\tphy_id = mdiobus_read(bus, i, MII_PHYSID1) << 16;\n\t\tphy_id |= mdiobus_read(bus, i, MII_PHYSID2);\n\t\tif (ar8xxx_phy_match(phy_id)) {\n\t\t\tfound_phys++;\n\t\t} else if (phy_id) {\n\t\t\tpr_debug(\"ar8xxx: unknown PHY at %s:%02x id:%08x\\n\",\n\t\t\t\t dev_name(&bus->dev), i, phy_id);\n\t\t}\n\t}\n\treturn !!found_phys;\n}\n\nstatic int\nar8xxx_phy_probe(struct phy_device *phydev)\n{\n\tstruct ar8xxx_priv *priv;\n\tstruct switch_dev *swdev;\n\tint ret;\n\n\t/* skip PHYs at unused adresses */\n\tif (phydev->mdio.addr != 0 && phydev->mdio.addr != 3 && phydev->mdio.addr != 4)\n\t\treturn -ENODEV;\n\n\tif (!ar8xxx_is_possible(phydev->mdio.bus))\n\t\treturn -ENODEV;\n\n\tmutex_lock(&ar8xxx_dev_list_lock);\n\tlist_for_each_entry(priv, &ar8xxx_dev_list, list)\n\t\tif (priv->mii_bus == phydev->mdio.bus)\n\t\t\tgoto found;\n\n\tpriv = ar8xxx_create();\n\tif (priv == NULL) {\n\t\tret = -ENOMEM;\n\t\tgoto unlock;\n\t}\n\n\tpriv->mii_bus = phydev->mdio.bus;\n\tpriv->pdev = &phydev->mdio.dev;\n\n\tret = of_property_read_u32(priv->pdev->of_node, \"qca,mib-poll-interval\",\n\t\t\t\t   &priv->mib_poll_interval);\n\tif (ret)\n\t\tpriv->mib_poll_interval = 0;\n\n\tret = ar8xxx_id_chip(priv);\n\tif (ret)\n\t\tgoto free_priv;\n\n\tret = ar8xxx_probe_switch(priv);\n\tif (ret)\n\t\tgoto free_priv;\n\n\tswdev = &priv->dev;\n\tswdev->alias = dev_name(&priv->mii_bus->dev);\n\tret = register_switch(swdev, NULL);\n\tif (ret)\n\t\tgoto free_priv;\n\n\tpr_info(\"%s: %s rev. %u switch registered on %s\\n\",\n\t\tswdev->devname, swdev->name, priv->chip_rev,\n\t\tdev_name(&priv->mii_bus->dev));\n\n\tlist_add(&priv->list, &ar8xxx_dev_list);\n\nfound:\n\tpriv->use_count++;\n\n\tif (phydev->mdio.addr == 0 && priv->chip->config_at_probe) {\n\t\tpriv->phy = phydev;\n\n\t\tret = ar8xxx_start(priv);\n\t\tif (ret)\n\t\t\tgoto err_unregister_switch;\n\t} else if (priv->chip->phy_rgmii_set) {\n\t\tpriv->chip->phy_rgmii_set(priv, phydev);\n\t}\n\n\tphydev->priv = priv;\n\n\tmutex_unlock(&ar8xxx_dev_list_lock);\n\n\treturn 0;\n\nerr_unregister_switch:\n\tif (--priv->use_count)\n\t\tgoto unlock;\n\n\tunregister_switch(&priv->dev);\n\nfree_priv:\n\tar8xxx_free(priv);\nunlock:\n\tmutex_unlock(&ar8xxx_dev_list_lock);\n\treturn ret;\n}\n\nstatic void\nar8xxx_phy_detach(struct phy_device *phydev)\n{\n\tstruct net_device *dev = phydev->attached_dev;\n\n\tif (!dev)\n\t\treturn;\n\n#ifdef CONFIG_ETHERNET_PACKET_MANGLE\n\tdev->phy_ptr = NULL;\n#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,15,0)\n\tdev->extra_priv_flags &= ~IFF_NO_IP_ALIGN;\n#else\n\tdev->priv_flags &= ~IFF_NO_IP_ALIGN;\n#endif\n\tdev->eth_mangle_rx = NULL;\n\tdev->eth_mangle_tx = NULL;\n#endif\n}\n\nstatic void\nar8xxx_phy_remove(struct phy_device *phydev)\n{\n\tstruct ar8xxx_priv *priv = phydev->priv;\n\n\tif (WARN_ON(!priv))\n\t\treturn;\n\n\tphydev->priv = NULL;\n\n\tmutex_lock(&ar8xxx_dev_list_lock);\n\n\tif (--priv->use_count > 0) {\n\t\tmutex_unlock(&ar8xxx_dev_list_lock);\n\t\treturn;\n\t}\n\n\tlist_del(&priv->list);\n\tmutex_unlock(&ar8xxx_dev_list_lock);\n\n\tunregister_switch(&priv->dev);\n\tar8xxx_mib_stop(priv);\n\tar8xxx_free(priv);\n}\n\nstatic struct phy_driver ar8xxx_phy_driver[] = {\n\t{\n\t\t.phy_id\t\t= 0x004d0000,\n\t\t.name\t\t= \"Atheros AR8216/AR8236/AR8316\",\n\t\t.phy_id_mask\t= 0xffff0000,\n\t\t.probe\t\t= ar8xxx_phy_probe,\n\t\t.remove\t\t= ar8xxx_phy_remove,\n\t\t.detach\t\t= ar8xxx_phy_detach,\n\t\t.config_init\t= ar8xxx_phy_config_init,\n\t\t.config_aneg\t= ar8xxx_phy_config_aneg,\n\t\t.read_status\t= ar8xxx_phy_read_status,\n\t\t.get_features\t= ar8xxx_get_features,\n\t}\n};\n\nstatic const struct of_device_id ar8xxx_mdiodev_of_match[] = {\n\t{\n\t\t.compatible = \"qca,ar7240sw\",\n\t\t.data = &ar7240sw_chip,\n\t}, {\n\t\t.compatible = \"qca,ar8229\",\n\t\t.data = &ar8229_chip,\n\t}, {\n\t\t.compatible = \"qca,ar8236\",\n\t\t.data = &ar8236_chip,\n\t}, {\n\t\t.compatible = \"qca,ar8327\",\n\t\t.data = &ar8327_chip,\n\t},\n\t{ /* sentinel */ },\n};\n\nstatic int\nar8xxx_mdiodev_probe(struct mdio_device *mdiodev)\n{\n\tconst struct of_device_id *match;\n\tstruct ar8xxx_priv *priv;\n\tstruct switch_dev *swdev;\n\tstruct device_node *mdio_node;\n\tint ret;\n\n\tmatch = of_match_device(ar8xxx_mdiodev_of_match, &mdiodev->dev);\n\tif (!match)\n\t\treturn -EINVAL;\n\n\tpriv = ar8xxx_create();\n\tif (priv == NULL)\n\t\treturn -ENOMEM;\n\n\tpriv->mii_bus = mdiodev->bus;\n\tpriv->pdev = &mdiodev->dev;\n\tpriv->chip = (const struct ar8xxx_chip *) match->data;\n\n\tret = of_property_read_u32(priv->pdev->of_node, \"qca,mib-poll-interval\",\n\t\t\t\t   &priv->mib_poll_interval);\n\tif (ret)\n\t\tpriv->mib_poll_interval = 0;\n\n\tret = ar8xxx_read_id(priv);\n\tif (ret)\n\t\tgoto free_priv;\n\n\tret = ar8xxx_probe_switch(priv);\n\tif (ret)\n\t\tgoto free_priv;\n\n\tif (priv->chip->phy_read && priv->chip->phy_write) {\n\t\tpriv->sw_mii_bus = devm_mdiobus_alloc(&mdiodev->dev);\n\t\tpriv->sw_mii_bus->name = \"ar8xxx-mdio\";\n\t\tpriv->sw_mii_bus->read = ar8xxx_phy_read;\n\t\tpriv->sw_mii_bus->write = ar8xxx_phy_write;\n\t\tpriv->sw_mii_bus->priv = priv;\n\t\tpriv->sw_mii_bus->parent = &mdiodev->dev;\n\t\tsnprintf(priv->sw_mii_bus->id, MII_BUS_ID_SIZE, \"%s\",\n\t\t\t dev_name(&mdiodev->dev));\n\t\tmdio_node = of_get_child_by_name(priv->pdev->of_node, \"mdio-bus\");\n\t\tret = of_mdiobus_register(priv->sw_mii_bus, mdio_node);\n\t\tif (ret)\n\t\t\tgoto free_priv;\n\t}\n\n\tswdev = &priv->dev;\n\tswdev->alias = dev_name(&mdiodev->dev);\n\n\tif (of_property_read_bool(priv->pdev->of_node, \"qca,phy4-mii-enable\")) {\n\t\tpriv->port4_phy = true;\n\t\tswdev->ports--;\n\t}\n\n\tret = register_switch(swdev, NULL);\n\tif (ret)\n\t\tgoto free_priv;\n\n\tpr_info(\"%s: %s rev. %u switch registered on %s\\n\",\n\t\tswdev->devname, swdev->name, priv->chip_rev,\n\t\tdev_name(&priv->mii_bus->dev));\n\n\tmutex_lock(&ar8xxx_dev_list_lock);\n\tlist_add(&priv->list, &ar8xxx_dev_list);\n\tmutex_unlock(&ar8xxx_dev_list_lock);\n\n\tpriv->use_count++;\n\n\tret = ar8xxx_start(priv);\n\tif (ret)\n\t\tgoto err_unregister_switch;\n\n\tdev_set_drvdata(&mdiodev->dev, priv);\n\n\treturn 0;\n\nerr_unregister_switch:\n\tif (--priv->use_count)\n\t\treturn ret;\n\n\tunregister_switch(&priv->dev);\n\nfree_priv:\n\tar8xxx_free(priv);\n\treturn ret;\n}\n\nstatic void\nar8xxx_mdiodev_remove(struct mdio_device *mdiodev)\n{\n\tstruct ar8xxx_priv *priv = dev_get_drvdata(&mdiodev->dev);\n\n\tif (WARN_ON(!priv))\n\t\treturn;\n\n\tmutex_lock(&ar8xxx_dev_list_lock);\n\n\tif (--priv->use_count > 0) {\n\t\tmutex_unlock(&ar8xxx_dev_list_lock);\n\t\treturn;\n\t}\n\n\tlist_del(&priv->list);\n\tmutex_unlock(&ar8xxx_dev_list_lock);\n\n\tunregister_switch(&priv->dev);\n\tar8xxx_mib_stop(priv);\n\tif(priv->sw_mii_bus)\n\t\tmdiobus_unregister(priv->sw_mii_bus);\n\tar8xxx_free(priv);\n}\n\nstatic struct mdio_driver ar8xxx_mdio_driver = {\n\t.probe  = ar8xxx_mdiodev_probe,\n\t.remove = ar8xxx_mdiodev_remove,\n\t.mdiodrv.driver = {\n\t\t.name = \"ar8xxx-switch\",\n\t\t.of_match_table = ar8xxx_mdiodev_of_match,\n\t},\n};\n\nstatic int __init ar8216_init(void)\n{\n\tint ret;\n\n\tret = phy_drivers_register(ar8xxx_phy_driver,\n\t\t\t\t   ARRAY_SIZE(ar8xxx_phy_driver),\n\t\t\t\t   THIS_MODULE);\n\tif (ret)\n\t\treturn ret;\n\n\tret = mdio_driver_register(&ar8xxx_mdio_driver);\n\tif (ret)\n\t\tphy_drivers_unregister(ar8xxx_phy_driver,\n\t\t\t\t       ARRAY_SIZE(ar8xxx_phy_driver));\n\n\treturn ret;\n}\nmodule_init(ar8216_init);\n\nstatic void __exit ar8216_exit(void)\n{\n\tmdio_driver_unregister(&ar8xxx_mdio_driver);\n\tphy_drivers_unregister(ar8xxx_phy_driver,\n\t\t\t        ARRAY_SIZE(ar8xxx_phy_driver));\n}\nmodule_exit(ar8216_exit);\n\nMODULE_LICENSE(\"GPL\");\n"
  },
  {
    "path": "target/linux/generic/files/drivers/net/phy/ar8216.h",
    "content": "/*\n * ar8216.h: AR8216 switch driver\n *\n * Copyright (C) 2009 Felix Fietkau <nbd@nbd.name>\n *\n * This program is free software; you can redistribute it and/or\n * modify it under the terms of the GNU General Public License\n * as published by the Free Software Foundation; either version 2\n * of the License, or (at your option) any later version.\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n * GNU General Public License for more details.\n */\n\n#ifndef __AR8216_H\n#define __AR8216_H\n\n#define BITS(_s, _n)\t(((1UL << (_n)) - 1) << _s)\n\n#define AR8XXX_CAP_GIGE\t\t\tBIT(0)\n#define AR8XXX_CAP_MIB_COUNTERS\t\tBIT(1)\n\n#define AR8XXX_NUM_PHYS \t5\n#define AR8216_PORT_CPU\t0\n#define AR8216_NUM_PORTS\t6\n#define AR8216_NUM_VLANS\t16\n#define AR7240SW_NUM_PORTS\t5\n#define AR8316_NUM_VLANS\t4096\n\n/* size of the vlan table */\n#define AR8X16_MAX_VLANS\t128\n#define AR83X7_MAX_VLANS\t4096\n#define AR8XXX_MAX_VLANS\tAR83X7_MAX_VLANS\n\n#define AR8X16_PROBE_RETRIES\t10\n#define AR8X16_MAX_PORTS\t8\n\n#define AR8XXX_REG_ARL_CTRL_AGE_TIME_SECS\t7\n#define AR8XXX_DEFAULT_ARL_AGE_TIME\t\t300\n\n/* Atheros specific MII registers */\n#define MII_ATH_MMD_ADDR\t\t0x0d\n#define MII_ATH_MMD_DATA\t\t0x0e\n#define MII_ATH_DBG_ADDR\t\t0x1d\n#define MII_ATH_DBG_DATA\t\t0x1e\n\n#define AR8216_REG_CTRL\t\t\t0x0000\n#define   AR8216_CTRL_REVISION\t\tBITS(0, 8)\n#define   AR8216_CTRL_REVISION_S\t0\n#define   AR8216_CTRL_VERSION\t\tBITS(8, 8)\n#define   AR8216_CTRL_VERSION_S\t\t8\n#define   AR8216_CTRL_RESET\t\tBIT(31)\n\n#define AR8216_REG_FLOOD_MASK\t\t0x002C\n#define   AR8216_FM_UNI_DEST_PORTS\tBITS(0, 6)\n#define   AR8216_FM_MULTI_DEST_PORTS\tBITS(16, 6)\n#define   AR8216_FM_CPU_BROADCAST_EN\tBIT(26)\n#define   AR8229_FLOOD_MASK_UC_DP(_p)\tBIT(_p)\n#define   AR8229_FLOOD_MASK_MC_DP(_p)\tBIT(16 + (_p))\n#define   AR8229_FLOOD_MASK_BC_DP(_p)\tBIT(25 + (_p))\n\n#define AR8216_REG_GLOBAL_CTRL\t\t0x0030\n#define   AR8216_GCTRL_MTU\t\tBITS(0, 11)\n#define   AR8236_GCTRL_MTU\t\tBITS(0, 14)\n#define   AR8316_GCTRL_MTU\t\tBITS(0, 14)\n\n#define AR8216_REG_VTU\t\t\t0x0040\n#define   AR8216_VTU_OP\t\t\tBITS(0, 3)\n#define   AR8216_VTU_OP_NOOP\t\t0x0\n#define   AR8216_VTU_OP_FLUSH\t\t0x1\n#define   AR8216_VTU_OP_LOAD\t\t0x2\n#define   AR8216_VTU_OP_PURGE\t\t0x3\n#define   AR8216_VTU_OP_REMOVE_PORT\t0x4\n#define   AR8216_VTU_ACTIVE\t\tBIT(3)\n#define   AR8216_VTU_FULL\t\tBIT(4)\n#define   AR8216_VTU_PORT\t\tBITS(8, 4)\n#define   AR8216_VTU_PORT_S\t\t8\n#define   AR8216_VTU_VID\t\tBITS(16, 12)\n#define   AR8216_VTU_VID_S\t\t16\n#define   AR8216_VTU_PRIO\t\tBITS(28, 3)\n#define   AR8216_VTU_PRIO_S\t\t28\n#define   AR8216_VTU_PRIO_EN\t\tBIT(31)\n\n#define AR8216_REG_VTU_DATA\t\t0x0044\n#define   AR8216_VTUDATA_MEMBER\t\tBITS(0, 10)\n#define   AR8236_VTUDATA_MEMBER\t\tBITS(0, 7)\n#define   AR8216_VTUDATA_VALID\t\tBIT(11)\n\n#define AR8216_REG_ATU_FUNC0\t\t0x0050\n#define   AR8216_ATU_OP\t\t\tBITS(0, 3)\n#define   AR8216_ATU_OP_NOOP\t\t0x0\n#define   AR8216_ATU_OP_FLUSH\t\t0x1\n#define   AR8216_ATU_OP_LOAD\t\t0x2\n#define   AR8216_ATU_OP_PURGE\t\t0x3\n#define   AR8216_ATU_OP_FLUSH_UNLOCKED\t0x4\n#define   AR8216_ATU_OP_FLUSH_PORT\t0x5\n#define   AR8216_ATU_OP_GET_NEXT\t0x6\n#define   AR8216_ATU_ACTIVE\t\tBIT(3)\n#define   AR8216_ATU_PORT_NUM\t\tBITS(8, 4)\n#define   AR8216_ATU_PORT_NUM_S\t\t8\n#define   AR8216_ATU_FULL_VIO\t\tBIT(12)\n#define   AR8216_ATU_ADDR5\t\tBITS(16, 8)\n#define   AR8216_ATU_ADDR5_S\t\t16\n#define   AR8216_ATU_ADDR4\t\tBITS(24, 8)\n#define   AR8216_ATU_ADDR4_S\t\t24\n\n#define AR8216_REG_ATU_FUNC1\t\t0x0054\n#define   AR8216_ATU_ADDR3\t\tBITS(0, 8)\n#define   AR8216_ATU_ADDR3_S\t\t0\n#define   AR8216_ATU_ADDR2\t\tBITS(8, 8)\n#define   AR8216_ATU_ADDR2_S\t\t8\n#define   AR8216_ATU_ADDR1\t\tBITS(16, 8)\n#define   AR8216_ATU_ADDR1_S\t\t16\n#define   AR8216_ATU_ADDR0\t\tBITS(24, 8)\n#define   AR8216_ATU_ADDR0_S\t\t24\n\n#define AR8216_REG_ATU_FUNC2\t\t0x0058\n#define   AR8216_ATU_PORTS\t\tBITS(0, 6)\n#define   AR8216_ATU_PORTS_S\t\t0\n#define   AR8216_ATU_PORT0\t\tBIT(0)\n#define   AR8216_ATU_PORT1\t\tBIT(1)\n#define   AR8216_ATU_PORT2\t\tBIT(2)\n#define   AR8216_ATU_PORT3\t\tBIT(3)\n#define   AR8216_ATU_PORT4\t\tBIT(4)\n#define   AR8216_ATU_PORT5\t\tBIT(5)\n#define   AR8216_ATU_STATUS\t\tBITS(16, 4)\n#define   AR8216_ATU_STATUS_S\t\t16\n\n#define AR8216_REG_ATU_CTRL\t\t0x005C\n#define   AR8216_ATU_CTRL_AGE_EN\tBIT(17)\n#define   AR8216_ATU_CTRL_AGE_TIME\tBITS(0, 16)\n#define   AR8216_ATU_CTRL_AGE_TIME_S\t0\n#define   AR8236_ATU_CTRL_RES\t\tBIT(20)\n#define   AR8216_ATU_CTRL_LEARN_CHANGE\tBIT(18)\n#define   AR8216_ATU_CTRL_RESERVED\tBIT(19)\n#define   AR8216_ATU_CTRL_ARP_EN\tBIT(20)\n\n#define AR8216_REG_TAG_PRIORITY\t0x0070\n\n#define AR8216_REG_SERVICE_TAG\t\t0x0074\n#define  AR8216_SERVICE_TAG_M\t\tBITS(0, 16)\n\n#define AR8216_REG_MIB_FUNC\t\t0x0080\n#define   AR8216_MIB_TIMER\t\tBITS(0, 16)\n#define   AR8216_MIB_AT_HALF_EN\t\tBIT(16)\n#define   AR8216_MIB_BUSY\t\tBIT(17)\n#define   AR8216_MIB_FUNC\t\tBITS(24, 3)\n#define   AR8216_MIB_FUNC_S\t\t24\n#define   AR8216_MIB_FUNC_NO_OP\t\t0x0\n#define   AR8216_MIB_FUNC_FLUSH\t\t0x1\n#define   AR8216_MIB_FUNC_CAPTURE\t0x3\n#define   AR8236_MIB_EN\t\t\tBIT(30)\n\n#define AR8216_REG_GLOBAL_CPUPORT\t\t0x0078\n#define   AR8216_GLOBAL_CPUPORT_MIRROR_PORT\tBITS(4, 4)\n#define   AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S\t4\n#define   AR8216_GLOBAL_CPUPORT_EN\t\tBIT(8)\n\n#define AR8216_REG_MDIO_CTRL\t\t0x98\n#define   AR8216_MDIO_CTRL_DATA_M\tBITS(0, 16)\n#define   AR8216_MDIO_CTRL_REG_ADDR_S\t16\n#define   AR8216_MDIO_CTRL_PHY_ADDR_S\t21\n#define   AR8216_MDIO_CTRL_CMD_WRITE\t0\n#define   AR8216_MDIO_CTRL_CMD_READ\tBIT(27)\n#define   AR8216_MDIO_CTRL_MASTER_EN\tBIT(30)\n#define   AR8216_MDIO_CTRL_BUSY\tBIT(31)\n\n#define AR8216_PORT_OFFSET(_i)\t\t(0x0100 * (_i + 1))\n#define AR8216_REG_PORT_STATUS(_i)\t(AR8216_PORT_OFFSET(_i) + 0x0000)\n#define   AR8216_PORT_STATUS_SPEED\tBITS(0,2)\n#define   AR8216_PORT_STATUS_SPEED_S\t0\n#define   AR8216_PORT_STATUS_TXMAC\tBIT(2)\n#define   AR8216_PORT_STATUS_RXMAC\tBIT(3)\n#define   AR8216_PORT_STATUS_TXFLOW\tBIT(4)\n#define   AR8216_PORT_STATUS_RXFLOW\tBIT(5)\n#define   AR8216_PORT_STATUS_DUPLEX\tBIT(6)\n#define   AR8216_PORT_STATUS_LINK_UP\tBIT(8)\n#define   AR8216_PORT_STATUS_LINK_AUTO\tBIT(9)\n#define   AR8216_PORT_STATUS_LINK_PAUSE\tBIT(10)\n#define   AR8216_PORT_STATUS_FLOW_CONTROL  BIT(12)\n\n#define AR8216_REG_PORT_CTRL(_i)\t(AR8216_PORT_OFFSET(_i) + 0x0004)\n\n/* port forwarding state */\n#define   AR8216_PORT_CTRL_STATE\tBITS(0, 3)\n#define   AR8216_PORT_CTRL_STATE_S\t0\n\n#define   AR8216_PORT_CTRL_LEARN_LOCK\tBIT(7)\n\n/* egress 802.1q mode */\n#define   AR8216_PORT_CTRL_VLAN_MODE\tBITS(8, 2)\n#define   AR8216_PORT_CTRL_VLAN_MODE_S\t8\n\n#define   AR8216_PORT_CTRL_IGMP_SNOOP\tBIT(10)\n#define   AR8216_PORT_CTRL_HEADER\tBIT(11)\n#define   AR8216_PORT_CTRL_MAC_LOOP\tBIT(12)\n#define   AR8216_PORT_CTRL_SINGLE_VLAN\tBIT(13)\n#define   AR8216_PORT_CTRL_LEARN\tBIT(14)\n#define   AR8216_PORT_CTRL_MIRROR_TX\tBIT(16)\n#define   AR8216_PORT_CTRL_MIRROR_RX\tBIT(17)\n\n#define AR8216_REG_PORT_VLAN(_i)\t(AR8216_PORT_OFFSET(_i) + 0x0008)\n\n#define   AR8216_PORT_VLAN_DEFAULT_ID\tBITS(0, 12)\n#define   AR8216_PORT_VLAN_DEFAULT_ID_S\t0\n\n#define   AR8216_PORT_VLAN_DEST_PORTS\tBITS(16, 9)\n#define   AR8216_PORT_VLAN_DEST_PORTS_S\t16\n\n/* bit0 added to the priority field of egress frames */\n#define   AR8216_PORT_VLAN_TX_PRIO\tBIT(27)\n\n/* port default priority */\n#define   AR8216_PORT_VLAN_PRIORITY\tBITS(28, 2)\n#define   AR8216_PORT_VLAN_PRIORITY_S\t28\n\n/* ingress 802.1q mode */\n#define   AR8216_PORT_VLAN_MODE\t\tBITS(30, 2)\n#define   AR8216_PORT_VLAN_MODE_S\t30\n\n#define AR8216_REG_PORT_RATE(_i)\t(AR8216_PORT_OFFSET(_i) + 0x000c)\n#define AR8216_REG_PORT_PRIO(_i)\t(AR8216_PORT_OFFSET(_i) + 0x0010)\n\n#define AR8216_STATS_RXBROAD\t\t0x00\n#define AR8216_STATS_RXPAUSE\t\t0x04\n#define AR8216_STATS_RXMULTI\t\t0x08\n#define AR8216_STATS_RXFCSERR\t\t0x0c\n#define AR8216_STATS_RXALIGNERR\t\t0x10\n#define AR8216_STATS_RXRUNT\t\t0x14\n#define AR8216_STATS_RXFRAGMENT\t\t0x18\n#define AR8216_STATS_RX64BYTE\t\t0x1c\n#define AR8216_STATS_RX128BYTE\t\t0x20\n#define AR8216_STATS_RX256BYTE\t\t0x24\n#define AR8216_STATS_RX512BYTE\t\t0x28\n#define AR8216_STATS_RX1024BYTE\t\t0x2c\n#define AR8216_STATS_RXMAXBYTE\t\t0x30\n#define AR8216_STATS_RXTOOLONG\t\t0x34\n#define AR8216_STATS_RXGOODBYTE\t\t0x38\n#define AR8216_STATS_RXBADBYTE\t\t0x40\n#define AR8216_STATS_RXOVERFLOW\t\t0x48\n#define AR8216_STATS_FILTERED\t\t0x4c\n#define AR8216_STATS_TXBROAD\t\t0x50\n#define AR8216_STATS_TXPAUSE\t\t0x54\n#define AR8216_STATS_TXMULTI\t\t0x58\n#define AR8216_STATS_TXUNDERRUN\t\t0x5c\n#define AR8216_STATS_TX64BYTE\t\t0x60\n#define AR8216_STATS_TX128BYTE\t\t0x64\n#define AR8216_STATS_TX256BYTE\t\t0x68\n#define AR8216_STATS_TX512BYTE\t\t0x6c\n#define AR8216_STATS_TX1024BYTE\t\t0x70\n#define AR8216_STATS_TXMAXBYTE\t\t0x74\n#define AR8216_STATS_TXOVERSIZE\t\t0x78\n#define AR8216_STATS_TXBYTE\t\t0x7c\n#define AR8216_STATS_TXCOLLISION\t0x84\n#define AR8216_STATS_TXABORTCOL\t\t0x88\n#define AR8216_STATS_TXMULTICOL\t\t0x8c\n#define AR8216_STATS_TXSINGLECOL\t0x90\n#define AR8216_STATS_TXEXCDEFER\t\t0x94\n#define AR8216_STATS_TXDEFER\t\t0x98\n#define AR8216_STATS_TXLATECOL\t\t0x9c\n\n#define AR8216_MIB_RXB_ID\t\t14\t/* RxGoodByte */\n#define AR8216_MIB_TXB_ID\t\t29\t/* TxByte */\n\n#define AR8229_REG_OPER_MODE0\t\t0x04\n#define   AR8229_OPER_MODE0_MAC_GMII_EN\tBIT(6)\n#define   AR8229_OPER_MODE0_PHY_MII_EN\tBIT(10)\n\n#define AR8229_REG_OPER_MODE1\t\t0x08\n#define   AR8229_REG_OPER_MODE1_PHY4_MII_EN\tBIT(28)\n\n#define AR8229_REG_QM_CTRL\t\t0x3c\n#define   AR8229_QM_CTRL_ARP_EN\t\tBIT(15)\n\n#define AR8236_REG_PORT_VLAN(_i)\t(AR8216_PORT_OFFSET((_i)) + 0x0008)\n#define   AR8236_PORT_VLAN_DEFAULT_ID\tBITS(16, 12)\n#define   AR8236_PORT_VLAN_DEFAULT_ID_S\t16\n#define   AR8236_PORT_VLAN_PRIORITY\tBITS(29, 3)\n#define   AR8236_PORT_VLAN_PRIORITY_S\t28\n\n#define AR8236_REG_PORT_VLAN2(_i)\t(AR8216_PORT_OFFSET((_i)) + 0x000c)\n#define   AR8236_PORT_VLAN2_MEMBER\tBITS(16, 7)\n#define   AR8236_PORT_VLAN2_MEMBER_S\t16\n#define   AR8236_PORT_VLAN2_TX_PRIO\tBIT(23)\n#define   AR8236_PORT_VLAN2_VLAN_MODE\tBITS(30, 2)\n#define   AR8236_PORT_VLAN2_VLAN_MODE_S\t30\n\n#define AR8236_STATS_RXBROAD\t\t0x00\n#define AR8236_STATS_RXPAUSE\t\t0x04\n#define AR8236_STATS_RXMULTI\t\t0x08\n#define AR8236_STATS_RXFCSERR\t\t0x0c\n#define AR8236_STATS_RXALIGNERR\t\t0x10\n#define AR8236_STATS_RXRUNT\t\t0x14\n#define AR8236_STATS_RXFRAGMENT\t\t0x18\n#define AR8236_STATS_RX64BYTE\t\t0x1c\n#define AR8236_STATS_RX128BYTE\t\t0x20\n#define AR8236_STATS_RX256BYTE\t\t0x24\n#define AR8236_STATS_RX512BYTE\t\t0x28\n#define AR8236_STATS_RX1024BYTE\t\t0x2c\n#define AR8236_STATS_RX1518BYTE\t\t0x30\n#define AR8236_STATS_RXMAXBYTE\t\t0x34\n#define AR8236_STATS_RXTOOLONG\t\t0x38\n#define AR8236_STATS_RXGOODBYTE\t\t0x3c\n#define AR8236_STATS_RXBADBYTE\t\t0x44\n#define AR8236_STATS_RXOVERFLOW\t\t0x4c\n#define AR8236_STATS_FILTERED\t\t0x50\n#define AR8236_STATS_TXBROAD\t\t0x54\n#define AR8236_STATS_TXPAUSE\t\t0x58\n#define AR8236_STATS_TXMULTI\t\t0x5c\n#define AR8236_STATS_TXUNDERRUN\t\t0x60\n#define AR8236_STATS_TX64BYTE\t\t0x64\n#define AR8236_STATS_TX128BYTE\t\t0x68\n#define AR8236_STATS_TX256BYTE\t\t0x6c\n#define AR8236_STATS_TX512BYTE\t\t0x70\n#define AR8236_STATS_TX1024BYTE\t\t0x74\n#define AR8236_STATS_TX1518BYTE\t\t0x78\n#define AR8236_STATS_TXMAXBYTE\t\t0x7c\n#define AR8236_STATS_TXOVERSIZE\t\t0x80\n#define AR8236_STATS_TXBYTE\t\t0x84\n#define AR8236_STATS_TXCOLLISION\t0x8c\n#define AR8236_STATS_TXABORTCOL\t\t0x90\n#define AR8236_STATS_TXMULTICOL\t\t0x94\n#define AR8236_STATS_TXSINGLECOL\t0x98\n#define AR8236_STATS_TXEXCDEFER\t\t0x9c\n#define AR8236_STATS_TXDEFER\t\t0xa0\n#define AR8236_STATS_TXLATECOL\t\t0xa4\n\n#define AR8236_MIB_RXB_ID\t\t15\t/* RxGoodByte */\n#define AR8236_MIB_TXB_ID\t\t31\t/* TxByte */\n\n#define AR8316_REG_POSTRIP\t\t\t0x0008\n#define   AR8316_POSTRIP_MAC0_GMII_EN\t\tBIT(0)\n#define   AR8316_POSTRIP_MAC0_RGMII_EN\t\tBIT(1)\n#define   AR8316_POSTRIP_PHY4_GMII_EN\t\tBIT(2)\n#define   AR8316_POSTRIP_PHY4_RGMII_EN\t\tBIT(3)\n#define   AR8316_POSTRIP_MAC0_MAC_MODE\t\tBIT(4)\n#define   AR8316_POSTRIP_RTL_MODE\t\tBIT(5)\n#define   AR8316_POSTRIP_RGMII_RXCLK_DELAY_EN\tBIT(6)\n#define   AR8316_POSTRIP_RGMII_TXCLK_DELAY_EN\tBIT(7)\n#define   AR8316_POSTRIP_SERDES_EN\t\tBIT(8)\n#define   AR8316_POSTRIP_SEL_ANA_RST\t\tBIT(9)\n#define   AR8316_POSTRIP_GATE_25M_EN\t\tBIT(10)\n#define   AR8316_POSTRIP_SEL_CLK25M\t\tBIT(11)\n#define   AR8316_POSTRIP_HIB_PULSE_HW\t\tBIT(12)\n#define   AR8316_POSTRIP_DBG_MODE_I\t\tBIT(13)\n#define   AR8316_POSTRIP_MAC5_MAC_MODE\t\tBIT(14)\n#define   AR8316_POSTRIP_MAC5_PHY_MODE\t\tBIT(15)\n#define   AR8316_POSTRIP_POWER_DOWN_HW\t\tBIT(16)\n#define   AR8316_POSTRIP_LPW_STATE_EN\t\tBIT(17)\n#define   AR8316_POSTRIP_MAN_EN\t\t\tBIT(18)\n#define   AR8316_POSTRIP_PHY_PLL_ON\t\tBIT(19)\n#define   AR8316_POSTRIP_LPW_EXIT\t\tBIT(20)\n#define   AR8316_POSTRIP_TXDELAY_S0\t\tBIT(21)\n#define   AR8316_POSTRIP_TXDELAY_S1\t\tBIT(22)\n#define   AR8316_POSTRIP_RXDELAY_S0\t\tBIT(23)\n#define   AR8316_POSTRIP_LED_OPEN_EN\t\tBIT(24)\n#define   AR8316_POSTRIP_SPI_EN\t\t\tBIT(25)\n#define   AR8316_POSTRIP_RXDELAY_S1\t\tBIT(26)\n#define   AR8316_POSTRIP_POWER_ON_SEL\t\tBIT(31)\n\n/* port speed */\nenum {\n        AR8216_PORT_SPEED_10M = 0,\n        AR8216_PORT_SPEED_100M = 1,\n        AR8216_PORT_SPEED_1000M = 2,\n        AR8216_PORT_SPEED_ERR = 3,\n};\n\n/* ingress 802.1q mode */\nenum {\n\tAR8216_IN_PORT_ONLY = 0,\n\tAR8216_IN_PORT_FALLBACK = 1,\n\tAR8216_IN_VLAN_ONLY = 2,\n\tAR8216_IN_SECURE = 3\n};\n\n/* egress 802.1q mode */\nenum {\n\tAR8216_OUT_KEEP = 0,\n\tAR8216_OUT_STRIP_VLAN = 1,\n\tAR8216_OUT_ADD_VLAN = 2\n};\n\n/* port forwarding state */\nenum {\n\tAR8216_PORT_STATE_DISABLED = 0,\n\tAR8216_PORT_STATE_BLOCK = 1,\n\tAR8216_PORT_STATE_LISTEN = 2,\n\tAR8216_PORT_STATE_LEARN = 3,\n\tAR8216_PORT_STATE_FORWARD = 4\n};\n\n/* mib counter type */\nenum {\n\tAR8XXX_MIB_BASIC = 0,\n\tAR8XXX_MIB_EXTENDED = 1\n};\n\nenum {\n\tAR8XXX_VER_AR8216 = 0x01,\n\tAR8XXX_VER_AR8236 = 0x03,\n\tAR8XXX_VER_AR8316 = 0x10,\n\tAR8XXX_VER_AR8327 = 0x12,\n\tAR8XXX_VER_AR8337 = 0x13,\n};\n\n#define AR8XXX_NUM_ARL_RECORDS\t100\n\nenum arl_op {\n\tAR8XXX_ARL_INITIALIZE,\n\tAR8XXX_ARL_GET_NEXT\n};\n\nstruct arl_entry {\n\tu16 portmap;\n\tu8 mac[6];\n};\n\nstruct ar8xxx_priv;\n\nstruct ar8xxx_mib_desc {\n\tunsigned int size;\n\tunsigned int offset;\n\tconst char *name;\n\tu8 type;\n};\n\nstruct ar8xxx_chip {\n\tunsigned long caps;\n\tbool config_at_probe;\n\tbool mii_lo_first;\n\n\t/* parameters to calculate REG_PORT_STATS_BASE */\n\tunsigned reg_port_stats_start;\n\tunsigned reg_port_stats_length;\n\n\tunsigned reg_arl_ctrl;\n\n\tint (*hw_init)(struct ar8xxx_priv *priv);\n\tvoid (*cleanup)(struct ar8xxx_priv *priv);\n\n\tconst char *name;\n\tint vlans;\n\tint ports;\n\tconst struct switch_dev_ops *swops;\n\n\tvoid (*init_globals)(struct ar8xxx_priv *priv);\n\tvoid (*init_port)(struct ar8xxx_priv *priv, int port);\n\tvoid (*setup_port)(struct ar8xxx_priv *priv, int port, u32 members);\n\tu32 (*read_port_status)(struct ar8xxx_priv *priv, int port);\n\tu32 (*read_port_eee_status)(struct ar8xxx_priv *priv, int port);\n\tint (*atu_flush)(struct ar8xxx_priv *priv);\n\tint (*atu_flush_port)(struct ar8xxx_priv *priv, int port);\n\tvoid (*vtu_flush)(struct ar8xxx_priv *priv);\n\tvoid (*vtu_load_vlan)(struct ar8xxx_priv *priv, u32 vid, u32 port_mask);\n\tvoid (*phy_fixup)(struct ar8xxx_priv *priv, int phy);\n\tvoid (*set_mirror_regs)(struct ar8xxx_priv *priv);\n\tvoid (*get_arl_entry)(struct ar8xxx_priv *priv, struct arl_entry *a,\n\t\t\t      u32 *status, enum arl_op op);\n\tint (*sw_hw_apply)(struct switch_dev *dev);\n\tvoid (*phy_rgmii_set)(struct ar8xxx_priv *priv, struct phy_device *phydev);\n\tint (*phy_read)(struct ar8xxx_priv *priv, int addr, int regnum);\n\tint (*phy_write)(struct ar8xxx_priv *priv, int addr, int regnum, u16 val);\n\n\tconst struct ar8xxx_mib_desc *mib_decs;\n\tunsigned num_mibs;\n\tunsigned mib_func;\n\tint mib_rxb_id;\n\tint mib_txb_id;\n};\n\nstruct ar8xxx_priv {\n\tstruct switch_dev dev;\n\tstruct mii_bus *mii_bus;\n\tstruct mii_bus *sw_mii_bus;\n\tstruct phy_device *phy;\n\tstruct device *pdev;\n\n\tint (*get_port_link)(unsigned port);\n\n\tconst struct net_device_ops *ndo_old;\n\tstruct net_device_ops ndo;\n\tstruct mutex reg_mutex;\n\tu8 chip_ver;\n\tu8 chip_rev;\n\tconst struct ar8xxx_chip *chip;\n\tvoid *chip_data;\n\tbool initialized;\n\tbool port4_phy;\n\tchar buf[2048];\n\tstruct arl_entry arl_table[AR8XXX_NUM_ARL_RECORDS];\n\tchar arl_buf[AR8XXX_NUM_ARL_RECORDS * 32 + 256];\n\tbool link_up[AR8X16_MAX_PORTS];\n\n\tbool init;\n\n\tstruct mutex mib_lock;\n\tstruct delayed_work mib_work;\n\tu64 *mib_stats;\n\tu32 mib_poll_interval;\n\tu8 mib_type;\n\n\tstruct list_head list;\n\tunsigned int use_count;\n\n\t/* all fields below are cleared on reset */\n\tbool vlan;\n\n\tu16 vlan_id[AR8XXX_MAX_VLANS];\n\tu8 vlan_table[AR8XXX_MAX_VLANS];\n\tu8 vlan_tagged;\n\tu16 pvid[AR8X16_MAX_PORTS];\n\tint arl_age_time;\n\n\t/* mirroring */\n\tbool mirror_rx;\n\tbool mirror_tx;\n\tint source_port;\n\tint monitor_port;\n\tu8 port_vlan_prio[AR8X16_MAX_PORTS];\n};\n\nu32\nar8xxx_mii_read32(struct ar8xxx_priv *priv, int phy_id, int regnum);\nvoid\nar8xxx_mii_write32(struct ar8xxx_priv *priv, int phy_id, int regnum, u32 val);\nu32\nar8xxx_read(struct ar8xxx_priv *priv, int reg);\nvoid\nar8xxx_write(struct ar8xxx_priv *priv, int reg, u32 val);\nu32\nar8xxx_rmw(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val);\n\nvoid\nar8xxx_phy_dbg_read(struct ar8xxx_priv *priv, int phy_addr,\n\t\tu16 dbg_addr, u16 *dbg_data);\nvoid\nar8xxx_phy_dbg_write(struct ar8xxx_priv *priv, int phy_addr,\n\t\t     u16 dbg_addr, u16 dbg_data);\nvoid\nar8xxx_phy_mmd_write(struct ar8xxx_priv *priv, int phy_addr, u16 addr, u16 reg, u16 data);\nu16\nar8xxx_phy_mmd_read(struct ar8xxx_priv *priv, int phy_addr, u16 addr, u16 reg);\nvoid\nar8xxx_phy_init(struct ar8xxx_priv *priv);\nint\nar8xxx_sw_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,\n\t\t   struct switch_val *val);\nint\nar8xxx_sw_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,\n\t\t   struct switch_val *val);\nint\nar8xxx_sw_set_reset_mibs(struct switch_dev *dev,\n\t\t\t const struct switch_attr *attr,\n\t\t\t struct switch_val *val);\nint\nar8xxx_sw_set_mib_poll_interval(struct switch_dev *dev,\n\t\t\t       const struct switch_attr *attr,\n\t\t\t       struct switch_val *val);\nint\nar8xxx_sw_get_mib_poll_interval(struct switch_dev *dev,\n\t\t\t       const struct switch_attr *attr,\n\t\t\t       struct switch_val *val);\nint\nar8xxx_sw_set_mib_type(struct switch_dev *dev,\n\t\t\t       const struct switch_attr *attr,\n\t\t\t       struct switch_val *val);\nint\nar8xxx_sw_get_mib_type(struct switch_dev *dev,\n\t\t\t       const struct switch_attr *attr,\n\t\t\t       struct switch_val *val);\nint\nar8xxx_sw_set_mirror_rx_enable(struct switch_dev *dev,\n\t\t\t       const struct switch_attr *attr,\n\t\t\t       struct switch_val *val);\nint\nar8xxx_sw_get_mirror_rx_enable(struct switch_dev *dev,\n\t\t\t       const struct switch_attr *attr,\n\t\t\t       struct switch_val *val);\nint\nar8xxx_sw_set_mirror_tx_enable(struct switch_dev *dev,\n\t\t\t       const struct switch_attr *attr,\n\t\t\t       struct switch_val *val);\nint\nar8xxx_sw_get_mirror_tx_enable(struct switch_dev *dev,\n\t\t\t       const struct switch_attr *attr,\n\t\t\t       struct switch_val *val);\nint\nar8xxx_sw_set_mirror_monitor_port(struct switch_dev *dev,\n\t\t\t\t  const struct switch_attr *attr,\n\t\t\t\t  struct switch_val *val);\nint\nar8xxx_sw_get_mirror_monitor_port(struct switch_dev *dev,\n\t\t\t\t  const struct switch_attr *attr,\n\t\t\t\t  struct switch_val *val);\nint\nar8xxx_sw_set_mirror_source_port(struct switch_dev *dev,\n\t\t\t\t const struct switch_attr *attr,\n\t\t\t\t struct switch_val *val);\nint\nar8xxx_sw_get_mirror_source_port(struct switch_dev *dev,\n\t\t\t\t const struct switch_attr *attr,\n\t\t\t\t struct switch_val *val);\nint\nar8xxx_sw_set_pvid(struct switch_dev *dev, int port, int vlan);\nint\nar8xxx_sw_get_pvid(struct switch_dev *dev, int port, int *vlan);\nint\nar8xxx_sw_hw_apply(struct switch_dev *dev);\nint\nar8xxx_sw_reset_switch(struct switch_dev *dev);\nint\nar8xxx_sw_get_port_link(struct switch_dev *dev, int port,\n\t\t\tstruct switch_port_link *link);\nint\nar8xxx_sw_set_port_reset_mib(struct switch_dev *dev,\n                             const struct switch_attr *attr,\n                             struct switch_val *val);\nint\nar8xxx_sw_get_port_mib(struct switch_dev *dev,\n                       const struct switch_attr *attr,\n                       struct switch_val *val);\nint\nar8xxx_sw_get_arl_age_time(struct switch_dev *dev,\n\t\t\t   const struct switch_attr *attr,\n\t\t\t   struct switch_val *val);\nint\nar8xxx_sw_set_arl_age_time(struct switch_dev *dev,\n\t\t\t   const struct switch_attr *attr,\n\t\t\t   struct switch_val *val);\nint\nar8xxx_sw_get_arl_table(struct switch_dev *dev,\n\t\t\tconst struct switch_attr *attr,\n\t\t\tstruct switch_val *val);\nint\nar8xxx_sw_set_flush_arl_table(struct switch_dev *dev,\n\t\t\t      const struct switch_attr *attr,\n\t\t\t      struct switch_val *val);\nint\nar8xxx_sw_set_flush_port_arl_table(struct switch_dev *dev,\n\t\t\t\t   const struct switch_attr *attr,\n\t\t\t\t   struct switch_val *val);\nint\nar8xxx_sw_get_port_stats(struct switch_dev *dev, int port,\n\t\t\tstruct switch_port_stats *stats);\nint\nar8216_wait_bit(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val);\n\nstatic inline struct ar8xxx_priv *\nswdev_to_ar8xxx(struct switch_dev *swdev)\n{\n\treturn container_of(swdev, struct ar8xxx_priv, dev);\n}\n\nstatic inline bool ar8xxx_has_gige(struct ar8xxx_priv *priv)\n{\n\treturn priv->chip->caps & AR8XXX_CAP_GIGE;\n}\n\nstatic inline bool ar8xxx_has_mib_counters(struct ar8xxx_priv *priv)\n{\n\treturn priv->chip->caps & AR8XXX_CAP_MIB_COUNTERS;\n}\n\nstatic inline bool chip_is_ar8216(struct ar8xxx_priv *priv)\n{\n\treturn priv->chip_ver == AR8XXX_VER_AR8216;\n}\n\nstatic inline bool chip_is_ar8236(struct ar8xxx_priv *priv)\n{\n\treturn priv->chip_ver == AR8XXX_VER_AR8236;\n}\n\nstatic inline bool chip_is_ar8316(struct ar8xxx_priv *priv)\n{\n\treturn priv->chip_ver == AR8XXX_VER_AR8316;\n}\n\nstatic inline bool chip_is_ar8327(struct ar8xxx_priv *priv)\n{\n\treturn priv->chip_ver == AR8XXX_VER_AR8327;\n}\n\nstatic inline bool chip_is_ar8337(struct ar8xxx_priv *priv)\n{\n\treturn priv->chip_ver == AR8XXX_VER_AR8337;\n}\n\nstatic inline void\nar8xxx_reg_set(struct ar8xxx_priv *priv, int reg, u32 val)\n{\n\tar8xxx_rmw(priv, reg, 0, val);\n}\n\nstatic inline void\nar8xxx_reg_clear(struct ar8xxx_priv *priv, int reg, u32 val)\n{\n\tar8xxx_rmw(priv, reg, val, 0);\n}\n\nstatic inline void\nsplit_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page)\n{\n\tregaddr >>= 1;\n\t*r1 = regaddr & 0x1e;\n\n\tregaddr >>= 5;\n\t*r2 = regaddr & 0x7;\n\n\tregaddr >>= 3;\n\t*page = regaddr & 0x1ff;\n}\n\nstatic inline void\nwait_for_page_switch(void)\n{\n\tudelay(5);\n}\n\n#endif\n"
  },
  {
    "path": "target/linux/generic/files/drivers/net/phy/ar8327.c",
    "content": "/*\n * ar8327.c: AR8216 switch driver\n *\n * Copyright (C) 2009 Felix Fietkau <nbd@nbd.name>\n * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>\n *\n * This program is free software; you can redistribute it and/or\n * modify it under the terms of the GNU General Public License\n * as published by the Free Software Foundation; either version 2\n * of the License, or (at your option) any later version.\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n * GNU General Public License for more details.\n */\n\n#include <linux/list.h>\n#include <linux/bitops.h>\n#include <linux/switch.h>\n#include <linux/delay.h>\n#include <linux/phy.h>\n#include <linux/lockdep.h>\n#include <linux/ar8216_platform.h>\n#include <linux/workqueue.h>\n#include <linux/of_device.h>\n#include <linux/leds.h>\n#include <linux/mdio.h>\n\n#include \"ar8216.h\"\n#include \"ar8327.h\"\n\nextern const struct ar8xxx_mib_desc ar8236_mibs[39];\nextern const struct switch_attr ar8xxx_sw_attr_vlan[1];\n\nstatic u32\nar8327_get_pad_cfg(struct ar8327_pad_cfg *cfg)\n{\n\tu32 t;\n\n\tif (!cfg)\n\t\treturn 0;\n\n\tt = 0;\n\tswitch (cfg->mode) {\n\tcase AR8327_PAD_NC:\n\t\tbreak;\n\n\tcase AR8327_PAD_MAC2MAC_MII:\n\t\tt = AR8327_PAD_MAC_MII_EN;\n\t\tif (cfg->rxclk_sel)\n\t\t\tt |= AR8327_PAD_MAC_MII_RXCLK_SEL;\n\t\tif (cfg->txclk_sel)\n\t\t\tt |= AR8327_PAD_MAC_MII_TXCLK_SEL;\n\t\tbreak;\n\n\tcase AR8327_PAD_MAC2MAC_GMII:\n\t\tt = AR8327_PAD_MAC_GMII_EN;\n\t\tif (cfg->rxclk_sel)\n\t\t\tt |= AR8327_PAD_MAC_GMII_RXCLK_SEL;\n\t\tif (cfg->txclk_sel)\n\t\t\tt |= AR8327_PAD_MAC_GMII_TXCLK_SEL;\n\t\tbreak;\n\n\tcase AR8327_PAD_MAC_SGMII:\n\t\tt = AR8327_PAD_SGMII_EN;\n\n\t\t/*\n\t\t * WAR for the QUalcomm Atheros AP136 board.\n\t\t * It seems that RGMII TX/RX delay settings needs to be\n\t\t * applied for SGMII mode as well, The ethernet is not\n\t\t * reliable without this.\n\t\t */\n\t\tt |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S;\n\t\tt |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S;\n\t\tif (cfg->rxclk_delay_en)\n\t\t\tt |= AR8327_PAD_RGMII_RXCLK_DELAY_EN;\n\t\tif (cfg->txclk_delay_en)\n\t\t\tt |= AR8327_PAD_RGMII_TXCLK_DELAY_EN;\n\n\t\tif (cfg->sgmii_delay_en)\n\t\t\tt |= AR8327_PAD_SGMII_DELAY_EN;\n\n\t\tbreak;\n\n\tcase AR8327_PAD_MAC2PHY_MII:\n\t\tt = AR8327_PAD_PHY_MII_EN;\n\t\tif (cfg->rxclk_sel)\n\t\t\tt |= AR8327_PAD_PHY_MII_RXCLK_SEL;\n\t\tif (cfg->txclk_sel)\n\t\t\tt |= AR8327_PAD_PHY_MII_TXCLK_SEL;\n\t\tbreak;\n\n\tcase AR8327_PAD_MAC2PHY_GMII:\n\t\tt = AR8327_PAD_PHY_GMII_EN;\n\t\tif (cfg->pipe_rxclk_sel)\n\t\t\tt |= AR8327_PAD_PHY_GMII_PIPE_RXCLK_SEL;\n\t\tif (cfg->rxclk_sel)\n\t\t\tt |= AR8327_PAD_PHY_GMII_RXCLK_SEL;\n\t\tif (cfg->txclk_sel)\n\t\t\tt |= AR8327_PAD_PHY_GMII_TXCLK_SEL;\n\t\tbreak;\n\n\tcase AR8327_PAD_MAC_RGMII:\n\t\tt = AR8327_PAD_RGMII_EN;\n\t\tt |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S;\n\t\tt |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S;\n\t\tif (cfg->rxclk_delay_en)\n\t\t\tt |= AR8327_PAD_RGMII_RXCLK_DELAY_EN;\n\t\tif (cfg->txclk_delay_en)\n\t\t\tt |= AR8327_PAD_RGMII_TXCLK_DELAY_EN;\n\t\tbreak;\n\n\tcase AR8327_PAD_PHY_GMII:\n\t\tt = AR8327_PAD_PHYX_GMII_EN;\n\t\tbreak;\n\n\tcase AR8327_PAD_PHY_RGMII:\n\t\tt = AR8327_PAD_PHYX_RGMII_EN;\n\t\tbreak;\n\n\tcase AR8327_PAD_PHY_MII:\n\t\tt = AR8327_PAD_PHYX_MII_EN;\n\t\tbreak;\n\t}\n\n\treturn t;\n}\n\nstatic void\nar8327_phy_rgmii_set(struct ar8xxx_priv *priv, struct phy_device *phydev)\n{\n\tu16 phy_val = 0;\n\tint phyaddr = phydev->mdio.addr;\n\tstruct device_node *np = phydev->mdio.dev.of_node;\n\n\tif (!np)\n\t\treturn;\n\n\tif (!of_property_read_bool(np, \"qca,phy-rgmii-en\")) {\n\t\tpr_err(\"ar8327: qca,phy-rgmii-en is not specified\\n\");\n\t\treturn;\n\t}\n\tar8xxx_phy_dbg_read(priv, phyaddr,\n\t\t\t\tAR8327_PHY_MODE_SEL, &phy_val);\n\tphy_val |= AR8327_PHY_MODE_SEL_RGMII;\n\tar8xxx_phy_dbg_write(priv, phyaddr,\n\t\t\t\tAR8327_PHY_MODE_SEL, phy_val);\n\n\t/* set rgmii tx clock delay if needed */\n\tif (!of_property_read_bool(np, \"qca,txclk-delay-en\")) {\n\t\tpr_err(\"ar8327: qca,txclk-delay-en is not specified\\n\");\n\t\treturn;\n\t}\n\tar8xxx_phy_dbg_read(priv, phyaddr,\n\t\t\t\tAR8327_PHY_SYS_CTRL, &phy_val);\n\tphy_val |= AR8327_PHY_SYS_CTRL_RGMII_TX_DELAY;\n\tar8xxx_phy_dbg_write(priv, phyaddr,\n\t\t\t\tAR8327_PHY_SYS_CTRL, phy_val);\n\n\t/* set rgmii rx clock delay if needed */\n\tif (!of_property_read_bool(np, \"qca,rxclk-delay-en\")) {\n\t\tpr_err(\"ar8327: qca,rxclk-delay-en is not specified\\n\");\n\t\treturn;\n\t}\n\tar8xxx_phy_dbg_read(priv, phyaddr,\n\t\t\t\tAR8327_PHY_TEST_CTRL, &phy_val);\n\tphy_val |= AR8327_PHY_TEST_CTRL_RGMII_RX_DELAY;\n\tar8xxx_phy_dbg_write(priv, phyaddr,\n\t\t\t\tAR8327_PHY_TEST_CTRL, phy_val);\n}\n\nstatic void\nar8327_phy_fixup(struct ar8xxx_priv *priv, int phy)\n{\n\tswitch (priv->chip_rev) {\n\tcase 1:\n\t\t/* For 100M waveform */\n\t\tar8xxx_phy_dbg_write(priv, phy, 0, 0x02ea);\n\t\t/* Turn on Gigabit clock */\n\t\tar8xxx_phy_dbg_write(priv, phy, 0x3d, 0x68a0);\n\t\tbreak;\n\n\tcase 2:\n\t\tar8xxx_phy_mmd_write(priv, phy, 0x7, 0x3c, 0x0);\n\t\tfallthrough;\n\tcase 4:\n\t\tar8xxx_phy_mmd_write(priv, phy, 0x3, 0x800d, 0x803f);\n\t\tar8xxx_phy_dbg_write(priv, phy, 0x3d, 0x6860);\n\t\tar8xxx_phy_dbg_write(priv, phy, 0x5, 0x2c46);\n\t\tar8xxx_phy_dbg_write(priv, phy, 0x3c, 0x6000);\n\t\tbreak;\n\t}\n}\n\nstatic u32\nar8327_get_port_init_status(struct ar8327_port_cfg *cfg)\n{\n\tu32 t;\n\n\tif (!cfg->force_link)\n\t\treturn AR8216_PORT_STATUS_LINK_AUTO;\n\n\tt = AR8216_PORT_STATUS_TXMAC | AR8216_PORT_STATUS_RXMAC;\n\tt |= cfg->duplex ? AR8216_PORT_STATUS_DUPLEX : 0;\n\tt |= cfg->rxpause ? AR8216_PORT_STATUS_RXFLOW : 0;\n\tt |= cfg->txpause ? AR8216_PORT_STATUS_TXFLOW : 0;\n\n\tswitch (cfg->speed) {\n\tcase AR8327_PORT_SPEED_10:\n\t\tt |= AR8216_PORT_SPEED_10M;\n\t\tbreak;\n\tcase AR8327_PORT_SPEED_100:\n\t\tt |= AR8216_PORT_SPEED_100M;\n\t\tbreak;\n\tcase AR8327_PORT_SPEED_1000:\n\t\tt |= AR8216_PORT_SPEED_1000M;\n\t\tbreak;\n\t}\n\n\treturn t;\n}\n\n#define AR8327_LED_ENTRY(_num, _reg, _shift) \\\n\t[_num] = { .reg = (_reg), .shift = (_shift) }\n\nstatic const struct ar8327_led_entry\nar8327_led_map[AR8327_NUM_LEDS] = {\n\tAR8327_LED_ENTRY(AR8327_LED_PHY0_0, 0, 14),\n\tAR8327_LED_ENTRY(AR8327_LED_PHY0_1, 1, 14),\n\tAR8327_LED_ENTRY(AR8327_LED_PHY0_2, 2, 14),\n\n\tAR8327_LED_ENTRY(AR8327_LED_PHY1_0, 3, 8),\n\tAR8327_LED_ENTRY(AR8327_LED_PHY1_1, 3, 10),\n\tAR8327_LED_ENTRY(AR8327_LED_PHY1_2, 3, 12),\n\n\tAR8327_LED_ENTRY(AR8327_LED_PHY2_0, 3, 14),\n\tAR8327_LED_ENTRY(AR8327_LED_PHY2_1, 3, 16),\n\tAR8327_LED_ENTRY(AR8327_LED_PHY2_2, 3, 18),\n\n\tAR8327_LED_ENTRY(AR8327_LED_PHY3_0, 3, 20),\n\tAR8327_LED_ENTRY(AR8327_LED_PHY3_1, 3, 22),\n\tAR8327_LED_ENTRY(AR8327_LED_PHY3_2, 3, 24),\n\n\tAR8327_LED_ENTRY(AR8327_LED_PHY4_0, 0, 30),\n\tAR8327_LED_ENTRY(AR8327_LED_PHY4_1, 1, 30),\n\tAR8327_LED_ENTRY(AR8327_LED_PHY4_2, 2, 30),\n};\n\nstatic void\nar8327_set_led_pattern(struct ar8xxx_priv *priv, unsigned int led_num,\n\t\t       enum ar8327_led_pattern pattern)\n{\n\tconst struct ar8327_led_entry *entry;\n\n\tentry = &ar8327_led_map[led_num];\n\tar8xxx_rmw(priv, AR8327_REG_LED_CTRL(entry->reg),\n\t\t   (3 << entry->shift), pattern << entry->shift);\n}\n\nstatic void\nar8327_led_work_func(struct work_struct *work)\n{\n\tstruct ar8327_led *aled;\n\tu8 pattern;\n\n\taled = container_of(work, struct ar8327_led, led_work);\n\n\tpattern = aled->pattern;\n\n\tar8327_set_led_pattern(aled->sw_priv, aled->led_num,\n\t\t\t       pattern);\n}\n\nstatic void\nar8327_led_schedule_change(struct ar8327_led *aled, u8 pattern)\n{\n\tif (aled->pattern == pattern)\n\t\treturn;\n\n\taled->pattern = pattern;\n\tschedule_work(&aled->led_work);\n}\n\nstatic inline struct ar8327_led *\nled_cdev_to_ar8327_led(struct led_classdev *led_cdev)\n{\n\treturn container_of(led_cdev, struct ar8327_led, cdev);\n}\n\nstatic int\nar8327_led_blink_set(struct led_classdev *led_cdev,\n\t\t     unsigned long *delay_on,\n\t\t     unsigned long *delay_off)\n{\n\tstruct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);\n\n\tif (*delay_on == 0 && *delay_off == 0) {\n\t\t*delay_on = 125;\n\t\t*delay_off = 125;\n\t}\n\n\tif (*delay_on != 125 || *delay_off != 125) {\n\t\t/*\n\t\t * The hardware only supports blinking at 4Hz. Fall back\n\t\t * to software implementation in other cases.\n\t\t */\n\t\treturn -EINVAL;\n\t}\n\n\tspin_lock(&aled->lock);\n\n\taled->enable_hw_mode = false;\n\tar8327_led_schedule_change(aled, AR8327_LED_PATTERN_BLINK);\n\n\tspin_unlock(&aled->lock);\n\n\treturn 0;\n}\n\nstatic void\nar8327_led_set_brightness(struct led_classdev *led_cdev,\n\t\t\t  enum led_brightness brightness)\n{\n\tstruct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);\n\tu8 pattern;\n\tbool active;\n\n\tactive = (brightness != LED_OFF);\n\tactive ^= aled->active_low;\n\n\tpattern = (active) ? AR8327_LED_PATTERN_ON :\n\t\t\t     AR8327_LED_PATTERN_OFF;\n\n\tspin_lock(&aled->lock);\n\n\taled->enable_hw_mode = false;\n\tar8327_led_schedule_change(aled, pattern);\n\n\tspin_unlock(&aled->lock);\n}\n\nstatic ssize_t\nar8327_led_enable_hw_mode_show(struct device *dev,\n\t\t\t       struct device_attribute *attr,\n\t\t\t       char *buf)\n{\n\tstruct led_classdev *led_cdev = dev_get_drvdata(dev);\n\tstruct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);\n\tssize_t ret = 0;\n\n\tret += scnprintf(buf, PAGE_SIZE, \"%d\\n\", aled->enable_hw_mode);\n\n\treturn ret;\n}\n\nstatic ssize_t\nar8327_led_enable_hw_mode_store(struct device *dev,\n\t\t\t\tstruct device_attribute *attr,\n\t\t\t\tconst char *buf,\n\t\t\t\tsize_t size)\n{\n        struct led_classdev *led_cdev = dev_get_drvdata(dev);\n\tstruct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);\n\tu8 pattern;\n\tu8 value;\n\tint ret;\n\n\tret = kstrtou8(buf, 10, &value);\n\tif (ret < 0)\n\t\treturn -EINVAL;\n\n\tspin_lock(&aled->lock);\n\n\taled->enable_hw_mode = !!value;\n\tif (aled->enable_hw_mode)\n\t\tpattern = AR8327_LED_PATTERN_RULE;\n\telse\n\t\tpattern = AR8327_LED_PATTERN_OFF;\n\n\tar8327_led_schedule_change(aled, pattern);\n\n\tspin_unlock(&aled->lock);\n\n\treturn size;\n}\n\nstatic DEVICE_ATTR(enable_hw_mode,  S_IRUGO | S_IWUSR,\n\t\t   ar8327_led_enable_hw_mode_show,\n\t\t   ar8327_led_enable_hw_mode_store);\n\nstatic int\nar8327_led_register(struct ar8327_led *aled)\n{\n\tint ret;\n\n\tret = led_classdev_register(NULL, &aled->cdev);\n\tif (ret < 0)\n\t\treturn ret;\n\n\tif (aled->mode == AR8327_LED_MODE_HW) {\n\t\tret = device_create_file(aled->cdev.dev,\n\t\t\t\t\t &dev_attr_enable_hw_mode);\n\t\tif (ret)\n\t\t\tgoto err_unregister;\n\t}\n\n\treturn 0;\n\nerr_unregister:\n\tled_classdev_unregister(&aled->cdev);\n\treturn ret;\n}\n\nstatic void\nar8327_led_unregister(struct ar8327_led *aled)\n{\n\tif (aled->mode == AR8327_LED_MODE_HW)\n\t\tdevice_remove_file(aled->cdev.dev, &dev_attr_enable_hw_mode);\n\n\tled_classdev_unregister(&aled->cdev);\n\tcancel_work_sync(&aled->led_work);\n}\n\nstatic int\nar8327_led_create(struct ar8xxx_priv *priv,\n\t\t  const struct ar8327_led_info *led_info)\n{\n\tstruct ar8327_data *data = priv->chip_data;\n\tstruct ar8327_led *aled;\n\tint ret;\n\n\tif (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS))\n\t\treturn 0;\n\n\tif (!led_info->name)\n\t\treturn -EINVAL;\n\n\tif (led_info->led_num >= AR8327_NUM_LEDS)\n\t\treturn -EINVAL;\n\n\taled = kzalloc(sizeof(*aled) + strlen(led_info->name) + 1,\n\t\t       GFP_KERNEL);\n\tif (!aled)\n\t\treturn -ENOMEM;\n\n\taled->sw_priv = priv;\n\taled->led_num = led_info->led_num;\n\taled->active_low = led_info->active_low;\n\taled->mode = led_info->mode;\n\n\tif (aled->mode == AR8327_LED_MODE_HW)\n\t\taled->enable_hw_mode = true;\n\n\taled->name = (char *)(aled + 1);\n\tstrcpy(aled->name, led_info->name);\n\n\taled->cdev.name = aled->name;\n\taled->cdev.brightness_set = ar8327_led_set_brightness;\n\taled->cdev.blink_set = ar8327_led_blink_set;\n\taled->cdev.default_trigger = led_info->default_trigger;\n\n\tspin_lock_init(&aled->lock);\n\tmutex_init(&aled->mutex);\n\tINIT_WORK(&aled->led_work, ar8327_led_work_func);\n\n\tret = ar8327_led_register(aled);\n\tif (ret)\n\t\tgoto err_free;\n\n\tdata->leds[data->num_leds++] = aled;\n\n\treturn 0;\n\nerr_free:\n\tkfree(aled);\n\treturn ret;\n}\n\nstatic void\nar8327_led_destroy(struct ar8327_led *aled)\n{\n\tar8327_led_unregister(aled);\n\tkfree(aled);\n}\n\nstatic void\nar8327_leds_init(struct ar8xxx_priv *priv)\n{\n\tstruct ar8327_data *data = priv->chip_data;\n\tunsigned i;\n\n\tif (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS))\n\t\treturn;\n\n\tfor (i = 0; i < data->num_leds; i++) {\n\t\tstruct ar8327_led *aled;\n\n\t\taled = data->leds[i];\n\n\t\tif (aled->enable_hw_mode)\n\t\t\taled->pattern = AR8327_LED_PATTERN_RULE;\n\t\telse\n\t\t\taled->pattern = AR8327_LED_PATTERN_OFF;\n\n\t\tar8327_set_led_pattern(priv, aled->led_num, aled->pattern);\n\t}\n}\n\nstatic void\nar8327_leds_cleanup(struct ar8xxx_priv *priv)\n{\n\tstruct ar8327_data *data = priv->chip_data;\n\tunsigned i;\n\n\tif (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS))\n\t\treturn;\n\n\tfor (i = 0; i < data->num_leds; i++) {\n\t\tstruct ar8327_led *aled;\n\n\t\taled = data->leds[i];\n\t\tar8327_led_destroy(aled);\n\t}\n\n\tkfree(data->leds);\n}\n\nstatic int\nar8327_hw_config_pdata(struct ar8xxx_priv *priv,\n\t\t       struct ar8327_platform_data *pdata)\n{\n\tstruct ar8327_led_cfg *led_cfg;\n\tstruct ar8327_data *data = priv->chip_data;\n\tu32 pos, new_pos;\n\tu32 t;\n\n\tif (!pdata)\n\t\treturn -EINVAL;\n\n\tpriv->get_port_link = pdata->get_port_link;\n\n\tdata->port0_status = ar8327_get_port_init_status(&pdata->port0_cfg);\n\tdata->port6_status = ar8327_get_port_init_status(&pdata->port6_cfg);\n\n\tt = ar8327_get_pad_cfg(pdata->pad0_cfg);\n\tif (chip_is_ar8337(priv) && !pdata->pad0_cfg->mac06_exchange_dis)\n\t    t |= AR8337_PAD_MAC06_EXCHANGE_EN;\n\tar8xxx_write(priv, AR8327_REG_PAD0_MODE, t);\n\n\tt = ar8327_get_pad_cfg(pdata->pad5_cfg);\n\tar8xxx_write(priv, AR8327_REG_PAD5_MODE, t);\n\tt = ar8327_get_pad_cfg(pdata->pad6_cfg);\n\tar8xxx_write(priv, AR8327_REG_PAD6_MODE, t);\n\n\tpos = ar8xxx_read(priv, AR8327_REG_POWER_ON_STRAP);\n\tnew_pos = pos;\n\n\tled_cfg = pdata->led_cfg;\n\tif (led_cfg) {\n\t\tif (led_cfg->open_drain)\n\t\t\tnew_pos |= AR8327_POWER_ON_STRAP_LED_OPEN_EN;\n\t\telse\n\t\t\tnew_pos &= ~AR8327_POWER_ON_STRAP_LED_OPEN_EN;\n\n\t\tar8xxx_write(priv, AR8327_REG_LED_CTRL0, led_cfg->led_ctrl0);\n\t\tar8xxx_write(priv, AR8327_REG_LED_CTRL1, led_cfg->led_ctrl1);\n\t\tar8xxx_write(priv, AR8327_REG_LED_CTRL2, led_cfg->led_ctrl2);\n\t\tar8xxx_write(priv, AR8327_REG_LED_CTRL3, led_cfg->led_ctrl3);\n\n\t\tif (new_pos != pos)\n\t\t\tnew_pos |= AR8327_POWER_ON_STRAP_POWER_ON_SEL;\n\t}\n\n\tif (pdata->sgmii_cfg) {\n\t\tt = pdata->sgmii_cfg->sgmii_ctrl;\n\t\tif (priv->chip_rev == 1)\n\t\t\tt |= AR8327_SGMII_CTRL_EN_PLL |\n\t\t\t     AR8327_SGMII_CTRL_EN_RX |\n\t\t\t     AR8327_SGMII_CTRL_EN_TX;\n\t\telse\n\t\t\tt &= ~(AR8327_SGMII_CTRL_EN_PLL |\n\t\t\t       AR8327_SGMII_CTRL_EN_RX |\n\t\t\t       AR8327_SGMII_CTRL_EN_TX);\n\n\t\tar8xxx_write(priv, AR8327_REG_SGMII_CTRL, t);\n\n\t\tif (pdata->sgmii_cfg->serdes_aen)\n\t\t\tnew_pos &= ~AR8327_POWER_ON_STRAP_SERDES_AEN;\n\t\telse\n\t\t\tnew_pos |= AR8327_POWER_ON_STRAP_SERDES_AEN;\n\t}\n\n\tar8xxx_write(priv, AR8327_REG_POWER_ON_STRAP, new_pos);\n\n\tif (pdata->leds && pdata->num_leds) {\n\t\tint i;\n\n\t\tdata->leds = kzalloc(pdata->num_leds * sizeof(void *),\n\t\t\t\t     GFP_KERNEL);\n\t\tif (!data->leds)\n\t\t\treturn -ENOMEM;\n\n\t\tfor (i = 0; i < pdata->num_leds; i++)\n\t\t\tar8327_led_create(priv, &pdata->leds[i]);\n\t}\n\n\treturn 0;\n}\n\n#ifdef CONFIG_OF\nstatic int\nar8327_hw_config_of(struct ar8xxx_priv *priv, struct device_node *np)\n{\n\tstruct ar8327_data *data = priv->chip_data;\n\tconst __be32 *paddr;\n\tint len;\n\tint i;\n\n\tpaddr = of_get_property(np, \"qca,ar8327-initvals\", &len);\n\tif (!paddr || len < (2 * sizeof(*paddr)))\n\t\treturn -EINVAL;\n\n\tlen /= sizeof(*paddr);\n\n\tfor (i = 0; i < len - 1; i += 2) {\n\t\tu32 reg;\n\t\tu32 val;\n\n\t\treg = be32_to_cpup(paddr + i);\n\t\tval = be32_to_cpup(paddr + i + 1);\n\n\t\tswitch (reg) {\n\t\tcase AR8327_REG_PORT_STATUS(0):\n\t\t\tdata->port0_status = val;\n\t\t\tbreak;\n\t\tcase AR8327_REG_PORT_STATUS(6):\n\t\t\tdata->port6_status = val;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tar8xxx_write(priv, reg, val);\n\t\t\tbreak;\n\t\t}\n\t}\n\n\treturn 0;\n}\n#else\nstatic inline int\nar8327_hw_config_of(struct ar8xxx_priv *priv, struct device_node *np)\n{\n\treturn -EINVAL;\n}\n#endif\n\nstatic int\nar8327_hw_init(struct ar8xxx_priv *priv)\n{\n\tint ret;\n\n\tpriv->chip_data = kzalloc(sizeof(struct ar8327_data), GFP_KERNEL);\n\tif (!priv->chip_data)\n\t\treturn -ENOMEM;\n\n\tif (priv->pdev->of_node)\n\t\tret = ar8327_hw_config_of(priv, priv->pdev->of_node);\n\telse\n\t\tret = ar8327_hw_config_pdata(priv,\n\t\t\t\t\t     priv->phy->mdio.dev.platform_data);\n\n\tif (ret)\n\t\treturn ret;\n\n\tar8327_leds_init(priv);\n\n\tar8xxx_phy_init(priv);\n\n\treturn 0;\n}\n\nstatic void\nar8327_cleanup(struct ar8xxx_priv *priv)\n{\n\tar8327_leds_cleanup(priv);\n}\n\nstatic void\nar8327_init_globals(struct ar8xxx_priv *priv)\n{\n\tstruct ar8327_data *data = priv->chip_data;\n\tu32 t;\n\tint i;\n\n\t/* enable CPU port and disable mirror port */\n\tt = AR8327_FWD_CTRL0_CPU_PORT_EN |\n\t    AR8327_FWD_CTRL0_MIRROR_PORT;\n\tar8xxx_write(priv, AR8327_REG_FWD_CTRL0, t);\n\n\t/* forward multicast and broadcast frames to CPU */\n\tt = (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_UC_FLOOD_S) |\n\t    (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_MC_FLOOD_S) |\n\t    (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_BC_FLOOD_S);\n\tar8xxx_write(priv, AR8327_REG_FWD_CTRL1, t);\n\n\t/* enable jumbo frames */\n\tar8xxx_rmw(priv, AR8327_REG_MAX_FRAME_SIZE,\n\t\t   AR8327_MAX_FRAME_SIZE_MTU, 9018 + 8 + 2);\n\n\t/* Enable MIB counters */\n\tar8xxx_reg_set(priv, AR8327_REG_MODULE_EN,\n\t\t       AR8327_MODULE_EN_MIB);\n\n\t/* Disable EEE on all phy's due to stability issues */\n\tfor (i = 0; i < AR8XXX_NUM_PHYS; i++)\n\t\tdata->eee[i] = false;\n}\n\nstatic void\nar8327_init_port(struct ar8xxx_priv *priv, int port)\n{\n\tstruct ar8327_data *data = priv->chip_data;\n\tu32 t;\n\n\tif (port == AR8216_PORT_CPU)\n\t\tt = data->port0_status;\n\telse if (port == 6)\n\t\tt = data->port6_status;\n\telse\n\t\tt = AR8216_PORT_STATUS_LINK_AUTO;\n\n\tif (port != AR8216_PORT_CPU && port != 6) {\n\t\t/*hw limitation:if configure mac when there is traffic,\n\t\tport MAC may work abnormal. Need disable lan&wan mac at fisrt*/\n\t\tar8xxx_write(priv, AR8327_REG_PORT_STATUS(port), 0);\n\t\tmsleep(100);\n\t\tt |= AR8216_PORT_STATUS_FLOW_CONTROL;\n\t\tar8xxx_write(priv, AR8327_REG_PORT_STATUS(port), t);\n\t} else {\n\t\tar8xxx_write(priv, AR8327_REG_PORT_STATUS(port), t);\n\t}\n\n\tar8xxx_write(priv, AR8327_REG_PORT_HEADER(port), 0);\n\n\tar8xxx_write(priv, AR8327_REG_PORT_VLAN0(port), 0);\n\n\tt = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH << AR8327_PORT_VLAN1_OUT_MODE_S;\n\tar8xxx_write(priv, AR8327_REG_PORT_VLAN1(port), t);\n\n\tt = AR8327_PORT_LOOKUP_LEARN;\n\tt |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;\n\tar8xxx_write(priv, AR8327_REG_PORT_LOOKUP(port), t);\n}\n\nstatic u32\nar8327_read_port_status(struct ar8xxx_priv *priv, int port)\n{\n\tu32 t;\n\n\tt = ar8xxx_read(priv, AR8327_REG_PORT_STATUS(port));\n\t/* map the flow control autoneg result bits to the flow control bits\n\t * used in forced mode to allow ar8216_read_port_link detect\n\t * flow control properly if autoneg is used\n\t */\n\tif (t & AR8216_PORT_STATUS_LINK_UP &&\n\t    t & AR8216_PORT_STATUS_LINK_AUTO) {\n\t\tt &= ~(AR8216_PORT_STATUS_TXFLOW | AR8216_PORT_STATUS_RXFLOW);\n\t\tif (t & AR8327_PORT_STATUS_TXFLOW_AUTO)\n\t\t\tt |= AR8216_PORT_STATUS_TXFLOW;\n\t\tif (t & AR8327_PORT_STATUS_RXFLOW_AUTO)\n\t\t\tt |= AR8216_PORT_STATUS_RXFLOW;\n\t}\n\n\treturn t;\n}\n\nstatic u32\nar8327_read_port_eee_status(struct ar8xxx_priv *priv, int port)\n{\n\tint phy;\n\tu16 t;\n\n\tif (port >= priv->dev.ports)\n\t\treturn 0;\n\n\tif (port == 0 || port == 6)\n\t\treturn 0;\n\n\tphy = port - 1;\n\n\t/* EEE Ability Auto-negotiation Result */\n\tt = ar8xxx_phy_mmd_read(priv, phy, 0x7, 0x8000);\n\n\treturn mmd_eee_adv_to_ethtool_adv_t(t);\n}\n\nstatic int\nar8327_atu_flush(struct ar8xxx_priv *priv)\n{\n\tint ret;\n\n\tret = ar8216_wait_bit(priv, AR8327_REG_ATU_FUNC,\n\t\t\t      AR8327_ATU_FUNC_BUSY, 0);\n\tif (!ret)\n\t\tar8xxx_write(priv, AR8327_REG_ATU_FUNC,\n\t\t\t     AR8327_ATU_FUNC_OP_FLUSH |\n\t\t\t     AR8327_ATU_FUNC_BUSY);\n\n\treturn ret;\n}\n\nstatic int\nar8327_atu_flush_port(struct ar8xxx_priv *priv, int port)\n{\n\tu32 t;\n\tint ret;\n\n\tret = ar8216_wait_bit(priv, AR8327_REG_ATU_FUNC,\n\t\t\t      AR8327_ATU_FUNC_BUSY, 0);\n\tif (!ret) {\n\t\tt = (port << AR8327_ATU_PORT_NUM_S);\n\t\tt |= AR8327_ATU_FUNC_OP_FLUSH_PORT;\n\t\tt |= AR8327_ATU_FUNC_BUSY;\n\t\tar8xxx_write(priv, AR8327_REG_ATU_FUNC, t);\n\t}\n\n\treturn ret;\n}\n\nstatic int\nar8327_get_port_igmp(struct ar8xxx_priv *priv, int port)\n{\n\tu32 fwd_ctrl, frame_ack;\n\n\tfwd_ctrl = (BIT(port) << AR8327_FWD_CTRL1_IGMP_S);\n\tframe_ack = ((AR8327_FRAME_ACK_CTRL_IGMP_MLD |\n\t\t      AR8327_FRAME_ACK_CTRL_IGMP_JOIN |\n\t\t      AR8327_FRAME_ACK_CTRL_IGMP_LEAVE) <<\n\t\t     AR8327_FRAME_ACK_CTRL_S(port));\n\n\treturn (ar8xxx_read(priv, AR8327_REG_FWD_CTRL1) &\n\t\t\tfwd_ctrl) == fwd_ctrl &&\n\t\t(ar8xxx_read(priv, AR8327_REG_FRAME_ACK_CTRL(port)) &\n\t\t\tframe_ack) == frame_ack;\n}\n\nstatic void\nar8327_set_port_igmp(struct ar8xxx_priv *priv, int port, int enable)\n{\n\tint reg_frame_ack = AR8327_REG_FRAME_ACK_CTRL(port);\n\tu32 val_frame_ack = (AR8327_FRAME_ACK_CTRL_IGMP_MLD |\n\t\t\t  AR8327_FRAME_ACK_CTRL_IGMP_JOIN |\n\t\t\t  AR8327_FRAME_ACK_CTRL_IGMP_LEAVE) <<\n\t\t\t AR8327_FRAME_ACK_CTRL_S(port);\n\n\tif (enable) {\n\t\tar8xxx_rmw(priv, AR8327_REG_FWD_CTRL1,\n\t\t\t   BIT(port) << AR8327_FWD_CTRL1_MC_FLOOD_S,\n\t\t\t   BIT(port) << AR8327_FWD_CTRL1_IGMP_S);\n\t\tar8xxx_reg_set(priv, reg_frame_ack, val_frame_ack);\n\t} else {\n\t\tar8xxx_rmw(priv, AR8327_REG_FWD_CTRL1,\n\t\t\t   BIT(port) << AR8327_FWD_CTRL1_IGMP_S,\n\t\t\t   BIT(port) << AR8327_FWD_CTRL1_MC_FLOOD_S);\n\t\tar8xxx_reg_clear(priv, reg_frame_ack, val_frame_ack);\n\t}\n}\n\nstatic void\nar8327_vtu_op(struct ar8xxx_priv *priv, u32 op, u32 val)\n{\n\tif (ar8216_wait_bit(priv, AR8327_REG_VTU_FUNC1,\n\t\t\t    AR8327_VTU_FUNC1_BUSY, 0))\n\t\treturn;\n\n\tif ((op & AR8327_VTU_FUNC1_OP) == AR8327_VTU_FUNC1_OP_LOAD)\n\t\tar8xxx_write(priv, AR8327_REG_VTU_FUNC0, val);\n\n\top |= AR8327_VTU_FUNC1_BUSY;\n\tar8xxx_write(priv, AR8327_REG_VTU_FUNC1, op);\n}\n\nstatic void\nar8327_vtu_flush(struct ar8xxx_priv *priv)\n{\n\tar8327_vtu_op(priv, AR8327_VTU_FUNC1_OP_FLUSH, 0);\n}\n\nstatic void\nar8327_vtu_load_vlan(struct ar8xxx_priv *priv, u32 vid, u32 port_mask)\n{\n\tu32 op;\n\tu32 val;\n\tint i;\n\n\top = AR8327_VTU_FUNC1_OP_LOAD | (vid << AR8327_VTU_FUNC1_VID_S);\n\tval = AR8327_VTU_FUNC0_VALID | AR8327_VTU_FUNC0_IVL;\n\tfor (i = 0; i < AR8327_NUM_PORTS; i++) {\n\t\tu32 mode;\n\n\t\tif ((port_mask & BIT(i)) == 0)\n\t\t\tmode = AR8327_VTU_FUNC0_EG_MODE_NOT;\n\t\telse if (priv->vlan == 0)\n\t\t\tmode = AR8327_VTU_FUNC0_EG_MODE_KEEP;\n\t\telse if ((priv->vlan_tagged & BIT(i)) || (priv->vlan_id[priv->pvid[i]] != vid))\n\t\t\tmode = AR8327_VTU_FUNC0_EG_MODE_TAG;\n\t\telse\n\t\t\tmode = AR8327_VTU_FUNC0_EG_MODE_UNTAG;\n\n\t\tval |= mode << AR8327_VTU_FUNC0_EG_MODE_S(i);\n\t}\n\tar8327_vtu_op(priv, op, val);\n}\n\nstatic void\nar8327_setup_port(struct ar8xxx_priv *priv, int port, u32 members)\n{\n\tu32 t;\n\tu32 egress, ingress;\n\tu32 pvid = priv->vlan_id[priv->pvid[port]];\n\n\tif (priv->vlan) {\n\t\tegress = AR8327_PORT_VLAN1_OUT_MODE_UNMOD;\n\t\tingress = AR8216_IN_SECURE;\n\t} else {\n\t\tegress = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH;\n\t\tingress = AR8216_IN_PORT_ONLY;\n\t}\n\n\tt = pvid << AR8327_PORT_VLAN0_DEF_SVID_S;\n\tt |= pvid << AR8327_PORT_VLAN0_DEF_CVID_S;\n\tif (priv->vlan && priv->port_vlan_prio[port]) {\n\t\tu32 prio = priv->port_vlan_prio[port];\n\n\t\tt |= prio << AR8327_PORT_VLAN0_DEF_SPRI_S;\n\t\tt |= prio << AR8327_PORT_VLAN0_DEF_CPRI_S;\n\t}\n\tar8xxx_write(priv, AR8327_REG_PORT_VLAN0(port), t);\n\n\tt = AR8327_PORT_VLAN1_PORT_VLAN_PROP;\n\tt |= egress << AR8327_PORT_VLAN1_OUT_MODE_S;\n\tif (priv->vlan && priv->port_vlan_prio[port])\n\t\tt |= AR8327_PORT_VLAN1_VLAN_PRI_PROP;\n\n\tar8xxx_write(priv, AR8327_REG_PORT_VLAN1(port), t);\n\n\tt = members;\n\tt |= AR8327_PORT_LOOKUP_LEARN;\n\tt |= ingress << AR8327_PORT_LOOKUP_IN_MODE_S;\n\tt |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;\n\tar8xxx_write(priv, AR8327_REG_PORT_LOOKUP(port), t);\n}\n\nstatic int\nar8327_sw_get_ports(struct switch_dev *dev, struct switch_val *val)\n{\n\tstruct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);\n\tu8 ports = priv->vlan_table[val->port_vlan];\n\tint i;\n\n\tval->len = 0;\n\tfor (i = 0; i < dev->ports; i++) {\n\t\tstruct switch_port *p;\n\n\t\tif (!(ports & (1 << i)))\n\t\t\tcontinue;\n\n\t\tp = &val->value.ports[val->len++];\n\t\tp->id = i;\n\t\tif ((priv->vlan_tagged & (1 << i)) || (priv->pvid[i] != val->port_vlan))\n\t\t\tp->flags = (1 << SWITCH_PORT_FLAG_TAGGED);\n\t\telse\n\t\t\tp->flags = 0;\n\t}\n\treturn 0;\n}\n\nstatic int\nar8327_sw_set_ports(struct switch_dev *dev, struct switch_val *val)\n{\n\tstruct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);\n\tu8 *vt = &priv->vlan_table[val->port_vlan];\n\tint i;\n\n\t*vt = 0;\n\tfor (i = 0; i < val->len; i++) {\n\t\tstruct switch_port *p = &val->value.ports[i];\n\n\t\tif (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) {\n\t\t\tif (val->port_vlan == priv->pvid[p->id]) {\n\t\t\t\tpriv->vlan_tagged |= (1 << p->id);\n\t\t\t}\n\t\t} else {\n\t\t\tpriv->vlan_tagged &= ~(1 << p->id);\n\t\t\tpriv->pvid[p->id] = val->port_vlan;\n\t\t}\n\n\t\t*vt |= 1 << p->id;\n\t}\n\treturn 0;\n}\n\nstatic void\nar8327_set_mirror_regs(struct ar8xxx_priv *priv)\n{\n\tint port;\n\n\t/* reset all mirror registers */\n\tar8xxx_rmw(priv, AR8327_REG_FWD_CTRL0,\n\t\t   AR8327_FWD_CTRL0_MIRROR_PORT,\n\t\t   (0xF << AR8327_FWD_CTRL0_MIRROR_PORT_S));\n\tfor (port = 0; port < AR8327_NUM_PORTS; port++) {\n\t\tar8xxx_reg_clear(priv, AR8327_REG_PORT_LOOKUP(port),\n\t\t\t   AR8327_PORT_LOOKUP_ING_MIRROR_EN);\n\n\t\tar8xxx_reg_clear(priv, AR8327_REG_PORT_HOL_CTRL1(port),\n\t\t\t   AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN);\n\t}\n\n\t/* now enable mirroring if necessary */\n\tif (priv->source_port >= AR8327_NUM_PORTS ||\n\t    priv->monitor_port >= AR8327_NUM_PORTS ||\n\t    priv->source_port == priv->monitor_port) {\n\t\treturn;\n\t}\n\n\tar8xxx_rmw(priv, AR8327_REG_FWD_CTRL0,\n\t\t   AR8327_FWD_CTRL0_MIRROR_PORT,\n\t\t   (priv->monitor_port << AR8327_FWD_CTRL0_MIRROR_PORT_S));\n\n\tif (priv->mirror_rx)\n\t\tar8xxx_reg_set(priv, AR8327_REG_PORT_LOOKUP(priv->source_port),\n\t\t\t   AR8327_PORT_LOOKUP_ING_MIRROR_EN);\n\n\tif (priv->mirror_tx)\n\t\tar8xxx_reg_set(priv, AR8327_REG_PORT_HOL_CTRL1(priv->source_port),\n\t\t\t   AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN);\n}\n\nstatic int\nar8327_sw_set_eee(struct switch_dev *dev,\n\t\t  const struct switch_attr *attr,\n\t\t  struct switch_val *val)\n{\n\tstruct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);\n\tstruct ar8327_data *data = priv->chip_data;\n\tint port = val->port_vlan;\n\tint phy;\n\n\tif (port >= dev->ports)\n\t\treturn -EINVAL;\n\tif (port == 0 || port == 6)\n\t\treturn -EOPNOTSUPP;\n\n\tphy = port - 1;\n\n\tdata->eee[phy] = !!(val->value.i);\n\n\treturn 0;\n}\n\nstatic int\nar8327_sw_get_eee(struct switch_dev *dev,\n\t\t  const struct switch_attr *attr,\n\t\t  struct switch_val *val)\n{\n\tstruct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);\n\tconst struct ar8327_data *data = priv->chip_data;\n\tint port = val->port_vlan;\n\tint phy;\n\n\tif (port >= dev->ports)\n\t\treturn -EINVAL;\n\tif (port == 0 || port == 6)\n\t\treturn -EOPNOTSUPP;\n\n\tphy = port - 1;\n\n\tval->value.i = data->eee[phy];\n\n\treturn 0;\n}\n\nstatic void\nar8327_wait_atu_ready(struct ar8xxx_priv *priv, u16 r2, u16 r1)\n{\n\tint timeout = 20;\n\n\twhile (ar8xxx_mii_read32(priv, r2, r1) & AR8327_ATU_FUNC_BUSY && --timeout) {\n\t\tudelay(10);\n\t\tcond_resched();\n\t}\n\n\tif (!timeout)\n\t\tpr_err(\"ar8327: timeout waiting for atu to become ready\\n\");\n}\n\nstatic void ar8327_get_arl_entry(struct ar8xxx_priv *priv,\n\t\t\t\t struct arl_entry *a, u32 *status, enum arl_op op)\n{\n\tstruct mii_bus *bus = priv->mii_bus;\n\tu16 r2, page;\n\tu16 r1_data0, r1_data1, r1_data2, r1_func;\n\tu32 val0, val1, val2;\n\n\tsplit_addr(AR8327_REG_ATU_DATA0, &r1_data0, &r2, &page);\n\tr2 |= 0x10;\n\n\tr1_data1 = (AR8327_REG_ATU_DATA1 >> 1) & 0x1e;\n\tr1_data2 = (AR8327_REG_ATU_DATA2 >> 1) & 0x1e;\n\tr1_func  = (AR8327_REG_ATU_FUNC >> 1) & 0x1e;\n\n\tswitch (op) {\n\tcase AR8XXX_ARL_INITIALIZE:\n\t\t/* all ATU registers are on the same page\n\t\t* therefore set page only once\n\t\t*/\n\t\tbus->write(bus, 0x18, 0, page);\n\t\twait_for_page_switch();\n\n\t\tar8327_wait_atu_ready(priv, r2, r1_func);\n\n\t\tar8xxx_mii_write32(priv, r2, r1_data0, 0);\n\t\tar8xxx_mii_write32(priv, r2, r1_data1, 0);\n\t\tar8xxx_mii_write32(priv, r2, r1_data2, 0);\n\t\tbreak;\n\tcase AR8XXX_ARL_GET_NEXT:\n\t\tar8xxx_mii_write32(priv, r2, r1_func,\n\t\t\t\t   AR8327_ATU_FUNC_OP_GET_NEXT |\n\t\t\t\t   AR8327_ATU_FUNC_BUSY);\n\t\tar8327_wait_atu_ready(priv, r2, r1_func);\n\n\t\tval0 = ar8xxx_mii_read32(priv, r2, r1_data0);\n\t\tval1 = ar8xxx_mii_read32(priv, r2, r1_data1);\n\t\tval2 = ar8xxx_mii_read32(priv, r2, r1_data2);\n\n\t\t*status = val2 & AR8327_ATU_STATUS;\n\t\tif (!*status)\n\t\t\tbreak;\n\n\t\ta->portmap = (val1 & AR8327_ATU_PORTS) >> AR8327_ATU_PORTS_S;\n\t\ta->mac[0] = (val0 & AR8327_ATU_ADDR0) >> AR8327_ATU_ADDR0_S;\n\t\ta->mac[1] = (val0 & AR8327_ATU_ADDR1) >> AR8327_ATU_ADDR1_S;\n\t\ta->mac[2] = (val0 & AR8327_ATU_ADDR2) >> AR8327_ATU_ADDR2_S;\n\t\ta->mac[3] = (val0 & AR8327_ATU_ADDR3) >> AR8327_ATU_ADDR3_S;\n\t\ta->mac[4] = (val1 & AR8327_ATU_ADDR4) >> AR8327_ATU_ADDR4_S;\n\t\ta->mac[5] = (val1 & AR8327_ATU_ADDR5) >> AR8327_ATU_ADDR5_S;\n\t\tbreak;\n\t}\n}\n\nstatic int\nar8327_sw_hw_apply(struct switch_dev *dev)\n{\n\tstruct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);\n\tconst struct ar8327_data *data = priv->chip_data;\n\tint ret, i;\n\n\tret = ar8xxx_sw_hw_apply(dev);\n\tif (ret)\n\t\treturn ret;\n\n\tfor (i=0; i < AR8XXX_NUM_PHYS; i++) {\n\t\tif (data->eee[i])\n\t\t\tar8xxx_reg_clear(priv, AR8327_REG_EEE_CTRL,\n\t\t\t       AR8327_EEE_CTRL_DISABLE_PHY(i));\n\t\telse\n\t\t\tar8xxx_reg_set(priv, AR8327_REG_EEE_CTRL,\n\t\t\t       AR8327_EEE_CTRL_DISABLE_PHY(i));\n\t}\n\n\treturn 0;\n}\n\nint\nar8327_sw_get_port_igmp_snooping(struct switch_dev *dev,\n\t\t\t\t const struct switch_attr *attr,\n\t\t\t\t struct switch_val *val)\n{\n\tstruct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);\n\tint port = val->port_vlan;\n\n\tif (port >= dev->ports)\n\t\treturn -EINVAL;\n\n\tmutex_lock(&priv->reg_mutex);\n\tval->value.i = ar8327_get_port_igmp(priv, port);\n\tmutex_unlock(&priv->reg_mutex);\n\n\treturn 0;\n}\n\nint\nar8327_sw_set_port_igmp_snooping(struct switch_dev *dev,\n\t\t\t\t const struct switch_attr *attr,\n\t\t\t\t struct switch_val *val)\n{\n\tstruct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);\n\tint port = val->port_vlan;\n\n\tif (port >= dev->ports)\n\t\treturn -EINVAL;\n\n\tmutex_lock(&priv->reg_mutex);\n\tar8327_set_port_igmp(priv, port, val->value.i);\n\tmutex_unlock(&priv->reg_mutex);\n\n\treturn 0;\n}\n\nint\nar8327_sw_get_igmp_snooping(struct switch_dev *dev,\n\t\t\t    const struct switch_attr *attr,\n\t\t\t    struct switch_val *val)\n{\n\tint port;\n\n\tfor (port = 0; port < dev->ports; port++) {\n\t\tval->port_vlan = port;\n\t\tif (ar8327_sw_get_port_igmp_snooping(dev, attr, val) ||\n\t\t    !val->value.i)\n\t\t\tbreak;\n\t}\n\n\treturn 0;\n}\n\nint\nar8327_sw_set_igmp_snooping(struct switch_dev *dev,\n\t\t\t    const struct switch_attr *attr,\n\t\t\t    struct switch_val *val)\n{\n\tint port;\n\n\tfor (port = 0; port < dev->ports; port++) {\n\t\tval->port_vlan = port;\n\t\tif (ar8327_sw_set_port_igmp_snooping(dev, attr, val))\n\t\t\tbreak;\n\t}\n\n\treturn 0;\n}\n\nint\nar8327_sw_get_igmp_v3(struct switch_dev *dev,\n\t\t      const struct switch_attr *attr,\n\t\t      struct switch_val *val)\n{\n\tstruct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);\n\tu32 val_reg;\n\n\tmutex_lock(&priv->reg_mutex);\n\tval_reg = ar8xxx_read(priv, AR8327_REG_FRAME_ACK_CTRL1);\n\tval->value.i = ((val_reg & AR8327_FRAME_ACK_CTRL_IGMP_V3_EN) != 0);\n\tmutex_unlock(&priv->reg_mutex);\n\n\treturn 0;\n}\n\nint\nar8327_sw_set_igmp_v3(struct switch_dev *dev,\n\t\t      const struct switch_attr *attr,\n\t\t      struct switch_val *val)\n{\n\tstruct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);\n\n\tmutex_lock(&priv->reg_mutex);\n\tif (val->value.i)\n\t\tar8xxx_reg_set(priv, AR8327_REG_FRAME_ACK_CTRL1,\n\t\t\t       AR8327_FRAME_ACK_CTRL_IGMP_V3_EN);\n\telse\n\t\tar8xxx_reg_clear(priv, AR8327_REG_FRAME_ACK_CTRL1,\n\t\t\t\t AR8327_FRAME_ACK_CTRL_IGMP_V3_EN);\n\tmutex_unlock(&priv->reg_mutex);\n\n\treturn 0;\n}\n\nstatic int\nar8327_sw_set_port_vlan_prio(struct switch_dev *dev, const struct switch_attr *attr,\n\t\t\t     struct switch_val *val)\n{\n\tstruct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);\n\tint port = val->port_vlan;\n\n\tif (port >= dev->ports)\n\t\treturn -EINVAL;\n\tif (port == 0 || port == 6)\n\t\treturn -EOPNOTSUPP;\n\tif (val->value.i < 0 || val->value.i > 7)\n\t\treturn -EINVAL;\n\n\tpriv->port_vlan_prio[port] = val->value.i;\n\n\treturn 0;\n}\n\nstatic int\nar8327_sw_get_port_vlan_prio(struct switch_dev *dev, const struct switch_attr *attr,\n                  struct switch_val *val)\n{\n\tstruct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);\n\tint port = val->port_vlan;\n\n\tval->value.i = priv->port_vlan_prio[port];\n\n\treturn 0;\n}\n\nstatic const struct switch_attr ar8327_sw_attr_globals[] = {\n\t{\n\t\t.type = SWITCH_TYPE_INT,\n\t\t.name = \"enable_vlan\",\n\t\t.description = \"Enable VLAN mode\",\n\t\t.set = ar8xxx_sw_set_vlan,\n\t\t.get = ar8xxx_sw_get_vlan,\n\t\t.max = 1\n\t},\n\t{\n\t\t.type = SWITCH_TYPE_NOVAL,\n\t\t.name = \"reset_mibs\",\n\t\t.description = \"Reset all MIB counters\",\n\t\t.set = ar8xxx_sw_set_reset_mibs,\n\t},\n\t{\n\t\t.type = SWITCH_TYPE_INT,\n\t\t.name = \"ar8xxx_mib_poll_interval\",\n\t\t.description = \"MIB polling interval in msecs (0 to disable)\",\n\t\t.set = ar8xxx_sw_set_mib_poll_interval,\n\t\t.get = ar8xxx_sw_get_mib_poll_interval\n\t},\n\t{\n\t\t.type = SWITCH_TYPE_INT,\n\t\t.name = \"ar8xxx_mib_type\",\n\t\t.description = \"MIB type (0=basic 1=extended)\",\n\t\t.set = ar8xxx_sw_set_mib_type,\n\t\t.get = ar8xxx_sw_get_mib_type\n\t},\n\t{\n\t\t.type = SWITCH_TYPE_INT,\n\t\t.name = \"enable_mirror_rx\",\n\t\t.description = \"Enable mirroring of RX packets\",\n\t\t.set = ar8xxx_sw_set_mirror_rx_enable,\n\t\t.get = ar8xxx_sw_get_mirror_rx_enable,\n\t\t.max = 1\n\t},\n\t{\n\t\t.type = SWITCH_TYPE_INT,\n\t\t.name = \"enable_mirror_tx\",\n\t\t.description = \"Enable mirroring of TX packets\",\n\t\t.set = ar8xxx_sw_set_mirror_tx_enable,\n\t\t.get = ar8xxx_sw_get_mirror_tx_enable,\n\t\t.max = 1\n\t},\n\t{\n\t\t.type = SWITCH_TYPE_INT,\n\t\t.name = \"mirror_monitor_port\",\n\t\t.description = \"Mirror monitor port\",\n\t\t.set = ar8xxx_sw_set_mirror_monitor_port,\n\t\t.get = ar8xxx_sw_get_mirror_monitor_port,\n\t\t.max = AR8327_NUM_PORTS - 1\n\t},\n\t{\n\t\t.type = SWITCH_TYPE_INT,\n\t\t.name = \"mirror_source_port\",\n\t\t.description = \"Mirror source port\",\n\t\t.set = ar8xxx_sw_set_mirror_source_port,\n\t\t.get = ar8xxx_sw_get_mirror_source_port,\n\t\t.max = AR8327_NUM_PORTS - 1\n\t},\n\t{\n\t\t.type = SWITCH_TYPE_INT,\n\t\t.name = \"arl_age_time\",\n\t\t.description = \"ARL age time (secs)\",\n\t\t.set = ar8xxx_sw_set_arl_age_time,\n\t\t.get = ar8xxx_sw_get_arl_age_time,\n\t},\n\t{\n\t\t.type = SWITCH_TYPE_STRING,\n\t\t.name = \"arl_table\",\n\t\t.description = \"Get ARL table\",\n\t\t.set = NULL,\n\t\t.get = ar8xxx_sw_get_arl_table,\n\t},\n\t{\n\t\t.type = SWITCH_TYPE_NOVAL,\n\t\t.name = \"flush_arl_table\",\n\t\t.description = \"Flush ARL table\",\n\t\t.set = ar8xxx_sw_set_flush_arl_table,\n\t},\n\t{\n\t\t.type = SWITCH_TYPE_INT,\n\t\t.name = \"igmp_snooping\",\n\t\t.description = \"Enable IGMP Snooping\",\n\t\t.set = ar8327_sw_set_igmp_snooping,\n\t\t.get = ar8327_sw_get_igmp_snooping,\n\t\t.max = 1\n\t},\n\t{\n\t\t.type = SWITCH_TYPE_INT,\n\t\t.name = \"igmp_v3\",\n\t\t.description = \"Enable IGMPv3 support\",\n\t\t.set = ar8327_sw_set_igmp_v3,\n\t\t.get = ar8327_sw_get_igmp_v3,\n\t\t.max = 1\n\t},\n};\n\nstatic const struct switch_attr ar8327_sw_attr_port[] = {\n\t{\n\t\t.type = SWITCH_TYPE_NOVAL,\n\t\t.name = \"reset_mib\",\n\t\t.description = \"Reset single port MIB counters\",\n\t\t.set = ar8xxx_sw_set_port_reset_mib,\n\t},\n\t{\n\t\t.type = SWITCH_TYPE_STRING,\n\t\t.name = \"mib\",\n\t\t.description = \"Get port's MIB counters\",\n\t\t.set = NULL,\n\t\t.get = ar8xxx_sw_get_port_mib,\n\t},\n\t{\n\t\t.type = SWITCH_TYPE_INT,\n\t\t.name = \"enable_eee\",\n\t\t.description = \"Enable EEE PHY sleep mode\",\n\t\t.set = ar8327_sw_set_eee,\n\t\t.get = ar8327_sw_get_eee,\n\t\t.max = 1,\n\t},\n\t{\n\t\t.type = SWITCH_TYPE_NOVAL,\n\t\t.name = \"flush_arl_table\",\n\t\t.description = \"Flush port's ARL table entries\",\n\t\t.set = ar8xxx_sw_set_flush_port_arl_table,\n\t},\n\t{\n\t\t.type = SWITCH_TYPE_INT,\n\t\t.name = \"igmp_snooping\",\n\t\t.description = \"Enable port's IGMP Snooping\",\n\t\t.set = ar8327_sw_set_port_igmp_snooping,\n\t\t.get = ar8327_sw_get_port_igmp_snooping,\n\t\t.max = 1\n\t},\n\t{\n\t\t.type = SWITCH_TYPE_INT,\n\t\t.name = \"vlan_prio\",\n\t\t.description = \"Port VLAN default priority (VLAN PCP) (0-7)\",\n\t\t.set = ar8327_sw_set_port_vlan_prio,\n\t\t.get = ar8327_sw_get_port_vlan_prio,\n\t\t.max = 7,\n\t},\n};\n\nstatic const struct switch_dev_ops ar8327_sw_ops = {\n\t.attr_global = {\n\t\t.attr = ar8327_sw_attr_globals,\n\t\t.n_attr = ARRAY_SIZE(ar8327_sw_attr_globals),\n\t},\n\t.attr_port = {\n\t\t.attr = ar8327_sw_attr_port,\n\t\t.n_attr = ARRAY_SIZE(ar8327_sw_attr_port),\n\t},\n\t.attr_vlan = {\n\t\t.attr = ar8xxx_sw_attr_vlan,\n\t\t.n_attr = ARRAY_SIZE(ar8xxx_sw_attr_vlan),\n\t},\n\t.get_port_pvid = ar8xxx_sw_get_pvid,\n\t.set_port_pvid = ar8xxx_sw_set_pvid,\n\t.get_vlan_ports = ar8327_sw_get_ports,\n\t.set_vlan_ports = ar8327_sw_set_ports,\n\t.apply_config = ar8327_sw_hw_apply,\n\t.reset_switch = ar8xxx_sw_reset_switch,\n\t.get_port_link = ar8xxx_sw_get_port_link,\n\t.get_port_stats = ar8xxx_sw_get_port_stats,\n};\n\nconst struct ar8xxx_chip ar8327_chip = {\n\t.caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,\n\t.config_at_probe = true,\n\t.mii_lo_first = true,\n\n\t.name = \"Atheros AR8327\",\n\t.ports = AR8327_NUM_PORTS,\n\t.vlans = AR83X7_MAX_VLANS,\n\t.swops = &ar8327_sw_ops,\n\n\t.reg_port_stats_start = 0x1000,\n\t.reg_port_stats_length = 0x100,\n\t.reg_arl_ctrl = AR8327_REG_ARL_CTRL,\n\n\t.hw_init = ar8327_hw_init,\n\t.cleanup = ar8327_cleanup,\n\t.init_globals = ar8327_init_globals,\n\t.init_port = ar8327_init_port,\n\t.setup_port = ar8327_setup_port,\n\t.read_port_status = ar8327_read_port_status,\n\t.read_port_eee_status = ar8327_read_port_eee_status,\n\t.atu_flush = ar8327_atu_flush,\n\t.atu_flush_port = ar8327_atu_flush_port,\n\t.vtu_flush = ar8327_vtu_flush,\n\t.vtu_load_vlan = ar8327_vtu_load_vlan,\n\t.phy_fixup = ar8327_phy_fixup,\n\t.set_mirror_regs = ar8327_set_mirror_regs,\n\t.get_arl_entry = ar8327_get_arl_entry,\n\t.sw_hw_apply = ar8327_sw_hw_apply,\n\n\t.num_mibs = ARRAY_SIZE(ar8236_mibs),\n\t.mib_decs = ar8236_mibs,\n\t.mib_func = AR8327_REG_MIB_FUNC,\n\t.mib_rxb_id = AR8236_MIB_RXB_ID,\n\t.mib_txb_id = AR8236_MIB_TXB_ID,\n};\n\nconst struct ar8xxx_chip ar8337_chip = {\n\t.caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,\n\t.config_at_probe = true,\n\t.mii_lo_first = true,\n\n\t.name = \"Atheros AR8337\",\n\t.ports = AR8327_NUM_PORTS,\n\t.vlans = AR83X7_MAX_VLANS,\n\t.swops = &ar8327_sw_ops,\n\n\t.reg_port_stats_start = 0x1000,\n\t.reg_port_stats_length = 0x100,\n\t.reg_arl_ctrl = AR8327_REG_ARL_CTRL,\n\n\t.hw_init = ar8327_hw_init,\n\t.cleanup = ar8327_cleanup,\n\t.init_globals = ar8327_init_globals,\n\t.init_port = ar8327_init_port,\n\t.setup_port = ar8327_setup_port,\n\t.read_port_status = ar8327_read_port_status,\n\t.read_port_eee_status = ar8327_read_port_eee_status,\n\t.atu_flush = ar8327_atu_flush,\n\t.atu_flush_port = ar8327_atu_flush_port,\n\t.vtu_flush = ar8327_vtu_flush,\n\t.vtu_load_vlan = ar8327_vtu_load_vlan,\n\t.phy_fixup = ar8327_phy_fixup,\n\t.set_mirror_regs = ar8327_set_mirror_regs,\n\t.get_arl_entry = ar8327_get_arl_entry,\n\t.sw_hw_apply = ar8327_sw_hw_apply,\n\t.phy_rgmii_set = ar8327_phy_rgmii_set,\n\n\t.num_mibs = ARRAY_SIZE(ar8236_mibs),\n\t.mib_decs = ar8236_mibs,\n\t.mib_func = AR8327_REG_MIB_FUNC,\n\t.mib_rxb_id = AR8236_MIB_RXB_ID,\n\t.mib_txb_id = AR8236_MIB_TXB_ID,\n};\n"
  },
  {
    "path": "target/linux/generic/files/drivers/net/phy/ar8327.h",
    "content": "/*\n * ar8327.h: AR8216 switch driver\n *\n * Copyright (C) 2009 Felix Fietkau <nbd@nbd.name>\n *\n * This program is free software; you can redistribute it and/or\n * modify it under the terms of the GNU General Public License\n * as published by the Free Software Foundation; either version 2\n * of the License, or (at your option) any later version.\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n * GNU General Public License for more details.\n */\n\n#ifndef __AR8327_H\n#define __AR8327_H\n\n#define AR8327_NUM_PORTS\t7\n#define AR8327_NUM_LEDS\t\t15\n#define AR8327_PORTS_ALL\t0x7f\n#define AR8327_NUM_LED_CTRL_REGS\t4\n\n#define AR8327_REG_MASK\t\t\t\t0x000\n\n#define AR8327_REG_PAD0_MODE\t\t\t0x004\n#define AR8327_REG_PAD5_MODE\t\t\t0x008\n#define AR8327_REG_PAD6_MODE\t\t\t0x00c\n#define   AR8327_PAD_MAC_MII_RXCLK_SEL\t\tBIT(0)\n#define   AR8327_PAD_MAC_MII_TXCLK_SEL\t\tBIT(1)\n#define   AR8327_PAD_MAC_MII_EN\t\t\tBIT(2)\n#define   AR8327_PAD_MAC_GMII_RXCLK_SEL\t\tBIT(4)\n#define   AR8327_PAD_MAC_GMII_TXCLK_SEL\t\tBIT(5)\n#define   AR8327_PAD_MAC_GMII_EN\t\tBIT(6)\n#define   AR8327_PAD_SGMII_EN\t\t\tBIT(7)\n#define   AR8327_PAD_PHY_MII_RXCLK_SEL\t\tBIT(8)\n#define   AR8327_PAD_PHY_MII_TXCLK_SEL\t\tBIT(9)\n#define   AR8327_PAD_PHY_MII_EN\t\t\tBIT(10)\n#define   AR8327_PAD_PHY_GMII_PIPE_RXCLK_SEL\tBIT(11)\n#define   AR8327_PAD_PHY_GMII_RXCLK_SEL\t\tBIT(12)\n#define   AR8327_PAD_PHY_GMII_TXCLK_SEL\t\tBIT(13)\n#define   AR8327_PAD_PHY_GMII_EN\t\tBIT(14)\n#define   AR8327_PAD_PHYX_GMII_EN\t\tBIT(16)\n#define   AR8327_PAD_PHYX_RGMII_EN\t\tBIT(17)\n#define   AR8327_PAD_PHYX_MII_EN\t\tBIT(18)\n#define   AR8327_PAD_SGMII_DELAY_EN\t\tBIT(19)\n#define   AR8327_PAD_RGMII_RXCLK_DELAY_SEL\tBITS(20, 2)\n#define   AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S\t20\n#define   AR8327_PAD_RGMII_TXCLK_DELAY_SEL\tBITS(22, 2)\n#define   AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S\t22\n#define   AR8327_PAD_RGMII_RXCLK_DELAY_EN\tBIT(24)\n#define   AR8327_PAD_RGMII_TXCLK_DELAY_EN\tBIT(25)\n#define   AR8327_PAD_RGMII_EN\t\t\tBIT(26)\n\n#define AR8327_REG_POWER_ON_STRAP\t\t0x010\n#define   AR8327_POWER_ON_STRAP_POWER_ON_SEL\tBIT(31)\n#define   AR8327_POWER_ON_STRAP_LED_OPEN_EN\tBIT(24)\n#define   AR8327_POWER_ON_STRAP_SERDES_AEN\tBIT(7)\n\n#define AR8327_REG_INT_STATUS0\t\t\t0x020\n#define   AR8327_INT0_VT_DONE\t\t\tBIT(20)\n\n#define AR8327_REG_INT_STATUS1\t\t\t0x024\n#define AR8327_REG_INT_MASK0\t\t\t0x028\n#define AR8327_REG_INT_MASK1\t\t\t0x02c\n\n#define AR8327_REG_MODULE_EN\t\t\t0x030\n#define   AR8327_MODULE_EN_MIB\t\t\tBIT(0)\n\n#define AR8327_REG_MIB_FUNC\t\t\t0x034\n#define   AR8327_MIB_CPU_KEEP\t\t\tBIT(20)\n\n#define AR8327_REG_SERVICE_TAG\t\t\t0x048\n#define AR8327_REG_LED_CTRL(_i)\t\t\t(0x050 + (_i) * 4)\n#define AR8327_REG_LED_CTRL0\t\t\t0x050\n#define AR8327_REG_LED_CTRL1\t\t\t0x054\n#define AR8327_REG_LED_CTRL2\t\t\t0x058\n#define AR8327_REG_LED_CTRL3\t\t\t0x05c\n#define AR8327_REG_MAC_ADDR0\t\t\t0x060\n#define AR8327_REG_MAC_ADDR1\t\t\t0x064\n\n#define AR8327_REG_MAX_FRAME_SIZE\t\t0x078\n#define   AR8327_MAX_FRAME_SIZE_MTU\t\tBITS(0, 14)\n\n#define AR8327_REG_PORT_STATUS(_i)\t\t(0x07c + (_i) * 4)\n#define   AR8327_PORT_STATUS_TXFLOW_AUTO\tBIT(10)\n#define   AR8327_PORT_STATUS_RXFLOW_AUTO\tBIT(11)\n\n#define AR8327_REG_HEADER_CTRL\t\t\t0x098\n#define AR8327_REG_PORT_HEADER(_i)\t\t(0x09c + (_i) * 4)\n\n#define AR8327_REG_SGMII_CTRL\t\t\t0x0e0\n#define   AR8327_SGMII_CTRL_EN_PLL\t\tBIT(1)\n#define   AR8327_SGMII_CTRL_EN_RX\t\tBIT(2)\n#define   AR8327_SGMII_CTRL_EN_TX\t\tBIT(3)\n\n#define AR8327_REG_EEE_CTRL\t\t\t0x100\n#define   AR8327_EEE_CTRL_DISABLE_PHY(_i)\tBIT(4 + (_i) * 2)\n\n#define AR8327_REG_FRAME_ACK_CTRL0\t\t0x210\n#define   AR8327_FRAME_ACK_CTRL_IGMP_MLD_EN0\tBIT(0)\n#define   AR8327_FRAME_ACK_CTRL_IGMP_JOIN_EN0\tBIT(1)\n#define   AR8327_FRAME_ACK_CTRL_IGMP_LEAVE_EN0\tBIT(2)\n#define   AR8327_FRAME_ACK_CTRL_EAPOL_EN0\tBIT(3)\n#define   AR8327_FRAME_ACK_CTRL_DHCP_EN0\tBIT(4)\n#define   AR8327_FRAME_ACK_CTRL_ARP_ACK_EN0\tBIT(5)\n#define   AR8327_FRAME_ACK_CTRL_ARP_REQ_EN0\tBIT(6)\n#define   AR8327_FRAME_ACK_CTRL_IGMP_MLD_EN1\tBIT(8)\n#define   AR8327_FRAME_ACK_CTRL_IGMP_JOIN_EN1\tBIT(9)\n#define   AR8327_FRAME_ACK_CTRL_IGMP_LEAVE_EN1\tBIT(10)\n#define   AR8327_FRAME_ACK_CTRL_EAPOL_EN1\tBIT(11)\n#define   AR8327_FRAME_ACK_CTRL_DHCP_EN1\tBIT(12)\n#define   AR8327_FRAME_ACK_CTRL_ARP_ACK_EN1\tBIT(13)\n#define   AR8327_FRAME_ACK_CTRL_ARP_REQ_EN1\tBIT(14)\n#define   AR8327_FRAME_ACK_CTRL_IGMP_MLD_EN2\tBIT(16)\n#define   AR8327_FRAME_ACK_CTRL_IGMP_JOIN_EN2\tBIT(17)\n#define   AR8327_FRAME_ACK_CTRL_IGMP_LEAVE_EN2\tBIT(18)\n#define   AR8327_FRAME_ACK_CTRL_EAPOL_EN2\tBIT(19)\n#define   AR8327_FRAME_ACK_CTRL_DHCP_EN2\tBIT(20)\n#define   AR8327_FRAME_ACK_CTRL_ARP_ACK_EN2\tBIT(21)\n#define   AR8327_FRAME_ACK_CTRL_ARP_REQ_EN2\tBIT(22)\n#define   AR8327_FRAME_ACK_CTRL_IGMP_MLD_EN3\tBIT(24)\n#define   AR8327_FRAME_ACK_CTRL_IGMP_JOIN_EN3\tBIT(25)\n#define   AR8327_FRAME_ACK_CTRL_IGMP_LEAVE_EN3\tBIT(26)\n#define   AR8327_FRAME_ACK_CTRL_EAPOL_EN3\tBIT(27)\n#define   AR8327_FRAME_ACK_CTRL_DHCP_EN3\tBIT(28)\n#define   AR8327_FRAME_ACK_CTRL_ARP_ACK_EN3\tBIT(29)\n#define   AR8327_FRAME_ACK_CTRL_ARP_REQ_EN3\tBIT(30)\n\n#define AR8327_REG_FRAME_ACK_CTRL1\t\t0x214\n#define   AR8327_FRAME_ACK_CTRL_IGMP_MLD_EN4\tBIT(0)\n#define   AR8327_FRAME_ACK_CTRL_IGMP_JOIN_EN4\tBIT(1)\n#define   AR8327_FRAME_ACK_CTRL_IGMP_LEAVE_EN4\tBIT(2)\n#define   AR8327_FRAME_ACK_CTRL_EAPOL_EN4\tBIT(3)\n#define   AR8327_FRAME_ACK_CTRL_DHCP_EN4\tBIT(4)\n#define   AR8327_FRAME_ACK_CTRL_ARP_ACK_EN4\tBIT(5)\n#define   AR8327_FRAME_ACK_CTRL_ARP_REQ_EN4\tBIT(6)\n#define   AR8327_FRAME_ACK_CTRL_IGMP_MLD_EN5\tBIT(8)\n#define   AR8327_FRAME_ACK_CTRL_IGMP_JOIN_EN5\tBIT(9)\n#define   AR8327_FRAME_ACK_CTRL_IGMP_LEAVE_EN5\tBIT(10)\n#define   AR8327_FRAME_ACK_CTRL_EAPOL_EN5\tBIT(11)\n#define   AR8327_FRAME_ACK_CTRL_DHCP_EN5\tBIT(12)\n#define   AR8327_FRAME_ACK_CTRL_ARP_ACK_EN5\tBIT(13)\n#define   AR8327_FRAME_ACK_CTRL_ARP_REQ_EN5\tBIT(14)\n#define   AR8327_FRAME_ACK_CTRL_IGMP_MLD_EN6\tBIT(16)\n#define   AR8327_FRAME_ACK_CTRL_IGMP_JOIN_EN6\tBIT(17)\n#define   AR8327_FRAME_ACK_CTRL_IGMP_LEAVE_EN6\tBIT(18)\n#define   AR8327_FRAME_ACK_CTRL_EAPOL_EN6\tBIT(19)\n#define   AR8327_FRAME_ACK_CTRL_DHCP_EN6\tBIT(20)\n#define   AR8327_FRAME_ACK_CTRL_ARP_ACK_EN6\tBIT(21)\n#define   AR8327_FRAME_ACK_CTRL_ARP_REQ_EN6\tBIT(22)\n#define   AR8327_FRAME_ACK_CTRL_IGMP_V3_EN\tBIT(24)\n#define   AR8327_FRAME_ACK_CTRL_PPPOE_EN\tBIT(25)\n\n#define AR8327_REG_FRAME_ACK_CTRL(_i)\t\t(0x210 + ((_i) / 4) * 0x4)\n#define   AR8327_FRAME_ACK_CTRL_IGMP_MLD\tBIT(0)\n#define   AR8327_FRAME_ACK_CTRL_IGMP_JOIN\tBIT(1)\n#define   AR8327_FRAME_ACK_CTRL_IGMP_LEAVE\tBIT(2)\n#define   AR8327_FRAME_ACK_CTRL_EAPOL\t\tBIT(3)\n#define   AR8327_FRAME_ACK_CTRL_DHCP\t\tBIT(4)\n#define   AR8327_FRAME_ACK_CTRL_ARP_ACK\t\tBIT(5)\n#define   AR8327_FRAME_ACK_CTRL_ARP_REQ\t\tBIT(6)\n#define   AR8327_FRAME_ACK_CTRL_S(_i)\t\t(((_i) % 4) * 8)\n\n#define AR8327_REG_PORT_VLAN0(_i)\t\t(0x420 + (_i) * 0x8)\n#define   AR8327_PORT_VLAN0_DEF_PRI_MASK\tBITS(0, 3)\n#define   AR8327_PORT_VLAN0_DEF_SVID\t\tBITS(0, 12)\n#define   AR8327_PORT_VLAN0_DEF_SVID_S\t\t0\n#define   AR8327_PORT_VLAN0_DEF_SPRI\t\tBITS(13, 3)\n#define   AR8327_PORT_VLAN0_DEF_SPRI_S\t\t13\n#define   AR8327_PORT_VLAN0_DEF_CVID\t\tBITS(16, 12)\n#define   AR8327_PORT_VLAN0_DEF_CVID_S\t\t16\n#define   AR8327_PORT_VLAN0_DEF_CPRI\t\tBITS(29, 3)\n#define   AR8327_PORT_VLAN0_DEF_CPRI_S\t\t29\n\n#define AR8327_REG_PORT_VLAN1(_i)\t\t(0x424 + (_i) * 0x8)\n#define   AR8327_PORT_VLAN1_VLAN_PRI_PROP\tBIT(4)\n#define   AR8327_PORT_VLAN1_PORT_VLAN_PROP\tBIT(6)\n#define   AR8327_PORT_VLAN1_OUT_MODE\t\tBITS(12, 2)\n#define   AR8327_PORT_VLAN1_OUT_MODE_S\t\t12\n#define   AR8327_PORT_VLAN1_OUT_MODE_UNMOD\t0\n#define   AR8327_PORT_VLAN1_OUT_MODE_UNTAG\t1\n#define   AR8327_PORT_VLAN1_OUT_MODE_TAG\t2\n#define   AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH\t3\n\n#define AR8327_REG_ATU_DATA0\t\t\t0x600\n#define   AR8327_ATU_ADDR0\t\t\tBITS(0, 8)\n#define   AR8327_ATU_ADDR0_S\t\t\t0\n#define   AR8327_ATU_ADDR1\t\t\tBITS(8, 8)\n#define   AR8327_ATU_ADDR1_S\t\t\t8\n#define   AR8327_ATU_ADDR2\t\t\tBITS(16, 8)\n#define   AR8327_ATU_ADDR2_S\t\t\t16\n#define   AR8327_ATU_ADDR3\t\t\tBITS(24, 8)\n#define   AR8327_ATU_ADDR3_S\t\t\t24\n#define AR8327_REG_ATU_DATA1\t\t\t0x604\n#define   AR8327_ATU_ADDR4\t\t\tBITS(0, 8)\n#define   AR8327_ATU_ADDR4_S\t\t\t0\n#define   AR8327_ATU_ADDR5\t\t\tBITS(8, 8)\n#define   AR8327_ATU_ADDR5_S\t\t\t8\n#define   AR8327_ATU_PORTS\t\t\tBITS(16, 7)\n#define   AR8327_ATU_PORTS_S\t\t\t16\n#define   AR8327_ATU_PORT0\t\t\tBIT(16)\n#define   AR8327_ATU_PORT1\t\t\tBIT(17)\n#define   AR8327_ATU_PORT2\t\t\tBIT(18)\n#define   AR8327_ATU_PORT3\t\t\tBIT(19)\n#define   AR8327_ATU_PORT4\t\t\tBIT(20)\n#define   AR8327_ATU_PORT5\t\t\tBIT(21)\n#define   AR8327_ATU_PORT6\t\t\tBIT(22)\n#define AR8327_REG_ATU_DATA2\t\t\t0x608\n#define   AR8327_ATU_STATUS\t\t\tBITS(0, 4)\n\n#define AR8327_REG_ATU_FUNC\t\t\t0x60c\n#define   AR8327_ATU_FUNC_OP\t\t\tBITS(0, 4)\n#define   AR8327_ATU_FUNC_OP_NOOP\t\t0x0\n#define   AR8327_ATU_FUNC_OP_FLUSH\t\t0x1\n#define   AR8327_ATU_FUNC_OP_LOAD\t\t0x2\n#define   AR8327_ATU_FUNC_OP_PURGE\t\t0x3\n#define   AR8327_ATU_FUNC_OP_FLUSH_UNLOCKED\t0x4\n#define   AR8327_ATU_FUNC_OP_FLUSH_PORT\t\t0x5\n#define   AR8327_ATU_FUNC_OP_GET_NEXT\t\t0x6\n#define   AR8327_ATU_FUNC_OP_SEARCH_MAC\t\t0x7\n#define   AR8327_ATU_FUNC_OP_CHANGE_TRUNK\t0x8\n#define   AR8327_ATU_PORT_NUM\t\t\tBITS(8, 4)\n#define   AR8327_ATU_PORT_NUM_S\t\t\t8\n#define   AR8327_ATU_FUNC_BUSY\t\t\tBIT(31)\n\n#define AR8327_REG_VTU_FUNC0\t\t\t0x0610\n#define   AR8327_VTU_FUNC0_EG_MODE\t\tBITS(4, 14)\n#define   AR8327_VTU_FUNC0_EG_MODE_S(_i)\t(4 + (_i) * 2)\n#define   AR8327_VTU_FUNC0_EG_MODE_KEEP\t\t0\n#define   AR8327_VTU_FUNC0_EG_MODE_UNTAG\t1\n#define   AR8327_VTU_FUNC0_EG_MODE_TAG\t\t2\n#define   AR8327_VTU_FUNC0_EG_MODE_NOT\t\t3\n#define   AR8327_VTU_FUNC0_IVL\t\t\tBIT(19)\n#define   AR8327_VTU_FUNC0_VALID\t\tBIT(20)\n\n#define AR8327_REG_VTU_FUNC1\t\t\t0x0614\n#define   AR8327_VTU_FUNC1_OP\t\t\tBITS(0, 3)\n#define   AR8327_VTU_FUNC1_OP_NOOP\t\t0\n#define   AR8327_VTU_FUNC1_OP_FLUSH\t\t1\n#define   AR8327_VTU_FUNC1_OP_LOAD\t\t2\n#define   AR8327_VTU_FUNC1_OP_PURGE\t\t3\n#define   AR8327_VTU_FUNC1_OP_REMOVE_PORT\t4\n#define   AR8327_VTU_FUNC1_OP_GET_NEXT\t\t5\n#define   AR8327_VTU_FUNC1_OP_GET_ONE\t\t6\n#define   AR8327_VTU_FUNC1_FULL\t\t\tBIT(4)\n#define   AR8327_VTU_FUNC1_PORT\t\t\tBIT(8, 4)\n#define   AR8327_VTU_FUNC1_PORT_S\t\t8\n#define   AR8327_VTU_FUNC1_VID\t\t\tBIT(16, 12)\n#define   AR8327_VTU_FUNC1_VID_S\t\t16\n#define   AR8327_VTU_FUNC1_BUSY\t\t\tBIT(31)\n\n#define AR8327_REG_ARL_CTRL\t\t\t0x0618\n\n#define AR8327_REG_FWD_CTRL0\t\t\t0x620\n#define   AR8327_FWD_CTRL0_CPU_PORT_EN\t\tBIT(10)\n#define   AR8327_FWD_CTRL0_MIRROR_PORT\t\tBITS(4, 4)\n#define   AR8327_FWD_CTRL0_MIRROR_PORT_S\t4\n\n#define AR8327_REG_FWD_CTRL1\t\t\t0x624\n#define   AR8327_FWD_CTRL1_UC_FLOOD\t\tBITS(0, 7)\n#define   AR8327_FWD_CTRL1_UC_FLOOD_S\t\t0\n#define   AR8327_FWD_CTRL1_MC_FLOOD\t\tBITS(8, 7)\n#define   AR8327_FWD_CTRL1_MC_FLOOD_S\t\t8\n#define   AR8327_FWD_CTRL1_BC_FLOOD\t\tBITS(16, 7)\n#define   AR8327_FWD_CTRL1_BC_FLOOD_S\t\t16\n#define   AR8327_FWD_CTRL1_IGMP\t\t\tBITS(24, 7)\n#define   AR8327_FWD_CTRL1_IGMP_S\t\t24\n\n#define AR8327_REG_PORT_LOOKUP(_i)\t\t(0x660 + (_i) * 0xc)\n#define   AR8327_PORT_LOOKUP_MEMBER\t\tBITS(0, 7)\n#define   AR8327_PORT_LOOKUP_IN_MODE\t\tBITS(8, 2)\n#define   AR8327_PORT_LOOKUP_IN_MODE_S\t\t8\n#define   AR8327_PORT_LOOKUP_STATE\t\tBITS(16, 3)\n#define   AR8327_PORT_LOOKUP_STATE_S\t\t16\n#define   AR8327_PORT_LOOKUP_LEARN\t\tBIT(20)\n#define   AR8327_PORT_LOOKUP_ING_MIRROR_EN\tBIT(25)\n\n#define AR8327_REG_PORT_PRIO(_i)\t\t(0x664 + (_i) * 0xc)\n\n#define AR8327_REG_PORT_HOL_CTRL1(_i)\t\t(0x974 + (_i) * 0x8)\n#define   AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN\tBIT(16)\n\n#define AR8337_PAD_MAC06_EXCHANGE_EN\t\tBIT(31)\n\n#define AR8327_PHY_MODE_SEL\t\t\t0x12\n#define   AR8327_PHY_MODE_SEL_RGMII\t\tBIT(3)\n#define AR8327_PHY_TEST_CTRL\t\t\t0x0\n#define   AR8327_PHY_TEST_CTRL_RGMII_RX_DELAY\tBIT(15)\n#define AR8327_PHY_SYS_CTRL\t\t\t0x5\n#define   AR8327_PHY_SYS_CTRL_RGMII_TX_DELAY\tBIT(8)\n\nenum ar8327_led_pattern {\n\tAR8327_LED_PATTERN_OFF = 0,\n\tAR8327_LED_PATTERN_BLINK,\n\tAR8327_LED_PATTERN_ON,\n\tAR8327_LED_PATTERN_RULE,\n};\n\nstruct ar8327_led_entry {\n\tunsigned reg;\n\tunsigned shift;\n};\n\nstruct ar8327_led {\n\tstruct led_classdev cdev;\n\tstruct ar8xxx_priv *sw_priv;\n\n\tchar *name;\n\tbool active_low;\n\tu8 led_num;\n\tenum ar8327_led_mode mode;\n\n\tstruct mutex mutex;\n\tspinlock_t lock;\n\tstruct work_struct led_work;\n\tbool enable_hw_mode;\n\tenum ar8327_led_pattern pattern;\n};\n\nstruct ar8327_data {\n\tu32 port0_status;\n\tu32 port6_status;\n\n\tstruct ar8327_led **leds;\n\tunsigned int num_leds;\n\n\t/* all fields below are cleared on reset */\n\tbool eee[AR8XXX_NUM_PHYS];\n};\n\n#endif\n"
  },
  {
    "path": "target/linux/generic/files/drivers/net/phy/b53/Kconfig",
    "content": "menuconfig SWCONFIG_B53\n\ttristate \"Broadcom bcm53xx managed switch support\"\n\tdepends on SWCONFIG\n\thelp\n\t  This driver adds support for Broadcom managed switch chips. It supports\n\t  BCM5325E, BCM5365, BCM539x, BCM53115 and BCM53125 as well as BCM63XX\n\t  integrated switches.\n\nconfig SWCONFIG_B53_SPI_DRIVER\n\ttristate \"B53 SPI connected switch driver\"\n\tdepends on SWCONFIG_B53 && SPI\n\thelp\n\t  Select to enable support for registering switches configured through SPI.\n\nconfig SWCONFIG_B53_PHY_DRIVER\n\ttristate \"B53 MDIO connected switch driver\"\n\tdepends on SWCONFIG_B53\n\tselect SWCONFIG_B53_PHY_FIXUP\n\thelp\n\t  Select to enable support for registering switches configured through MDIO.\n\nconfig SWCONFIG_B53_MMAP_DRIVER\n\ttristate \"B53 MMAP connected switch driver\"\n\tdepends on SWCONFIG_B53\n\thelp\n\t  Select to enable support for memory-mapped switches like the BCM63XX\n\t  integrated switches.\n\nconfig SWCONFIG_B53_SRAB_DRIVER\n\ttristate \"B53 SRAB connected switch driver\"\n\tdepends on SWCONFIG_B53\n\thelp\n\t  Select to enable support for memory-mapped Switch Register Access\n\t  Bridge Registers (SRAB) like it is found on the BCM53010\n\nconfig SWCONFIG_B53_PHY_FIXUP\n\tbool\n"
  },
  {
    "path": "target/linux/generic/files/drivers/net/phy/b53/Makefile",
    "content": "obj-$(CONFIG_SWCONFIG_B53)\t\t+= b53_common.o\n\nobj-$(CONFIG_SWCONFIG_B53_PHY_FIXUP)\t+= b53_phy_fixup.o\n\nobj-$(CONFIG_SWCONFIG_B53_MMAP_DRIVER)\t+= b53_mmap.o\nobj-$(CONFIG_SWCONFIG_B53_SRAB_DRIVER)\t+= b53_srab.o\nobj-$(CONFIG_SWCONFIG_B53_PHY_DRIVER)\t+= b53_mdio.o\nobj-$(CONFIG_SWCONFIG_B53_SPI_DRIVER)\t+= b53_spi.o\n\nccflags-y\t\t\t\t+= -Werror\n"
  },
  {
    "path": "target/linux/generic/files/drivers/net/phy/b53/b53_common.c",
    "content": "/*\n * B53 switch driver main logic\n *\n * Copyright (C) 2011-2013 Jonas Gorski <jogo@openwrt.org>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n */\n\n#define pr_fmt(fmt) KBUILD_MODNAME \": \" fmt\n\n#include <linux/delay.h>\n#include <linux/export.h>\n#include <linux/gpio.h>\n#include <linux/kernel.h>\n#include <linux/module.h>\n#include <linux/switch.h>\n#include <linux/phy.h>\n#include <linux/of.h>\n#include <linux/of_net.h>\n#include <linux/platform_data/b53.h>\n\n#include \"b53_regs.h\"\n#include \"b53_priv.h\"\n\n/* buffer size needed for displaying all MIBs with max'd values */\n#define B53_BUF_SIZE\t1188\n\nstruct b53_mib_desc {\n\tu8 size;\n\tu8 offset;\n\tconst char *name;\n};\n\n/* BCM5365 MIB counters */\nstatic const struct b53_mib_desc b53_mibs_65[] = {\n\t{ 8, 0x00, \"TxOctets\" },\n\t{ 4, 0x08, \"TxDropPkts\" },\n\t{ 4, 0x10, \"TxBroadcastPkts\" },\n\t{ 4, 0x14, \"TxMulticastPkts\" },\n\t{ 4, 0x18, \"TxUnicastPkts\" },\n\t{ 4, 0x1c, \"TxCollisions\" },\n\t{ 4, 0x20, \"TxSingleCollision\" },\n\t{ 4, 0x24, \"TxMultipleCollision\" },\n\t{ 4, 0x28, \"TxDeferredTransmit\" },\n\t{ 4, 0x2c, \"TxLateCollision\" },\n\t{ 4, 0x30, \"TxExcessiveCollision\" },\n\t{ 4, 0x38, \"TxPausePkts\" },\n\t{ 8, 0x44, \"RxOctets\" },\n\t{ 4, 0x4c, \"RxUndersizePkts\" },\n\t{ 4, 0x50, \"RxPausePkts\" },\n\t{ 4, 0x54, \"Pkts64Octets\" },\n\t{ 4, 0x58, \"Pkts65to127Octets\" },\n\t{ 4, 0x5c, \"Pkts128to255Octets\" },\n\t{ 4, 0x60, \"Pkts256to511Octets\" },\n\t{ 4, 0x64, \"Pkts512to1023Octets\" },\n\t{ 4, 0x68, \"Pkts1024to1522Octets\" },\n\t{ 4, 0x6c, \"RxOversizePkts\" },\n\t{ 4, 0x70, \"RxJabbers\" },\n\t{ 4, 0x74, \"RxAlignmentErrors\" },\n\t{ 4, 0x78, \"RxFCSErrors\" },\n\t{ 8, 0x7c, \"RxGoodOctets\" },\n\t{ 4, 0x84, \"RxDropPkts\" },\n\t{ 4, 0x88, \"RxUnicastPkts\" },\n\t{ 4, 0x8c, \"RxMulticastPkts\" },\n\t{ 4, 0x90, \"RxBroadcastPkts\" },\n\t{ 4, 0x94, \"RxSAChanges\" },\n\t{ 4, 0x98, \"RxFragments\" },\n\t{ },\n};\n\n#define B63XX_MIB_TXB_ID\t0\t/* TxOctets */\n#define B63XX_MIB_RXB_ID\t14\t/* RxOctets */\n\n/* BCM63xx MIB counters */\nstatic const struct b53_mib_desc b53_mibs_63xx[] = {\n\t{ 8, 0x00, \"TxOctets\" },\n\t{ 4, 0x08, \"TxDropPkts\" },\n\t{ 4, 0x0c, \"TxQoSPkts\" },\n\t{ 4, 0x10, \"TxBroadcastPkts\" },\n\t{ 4, 0x14, \"TxMulticastPkts\" },\n\t{ 4, 0x18, \"TxUnicastPkts\" },\n\t{ 4, 0x1c, \"TxCollisions\" },\n\t{ 4, 0x20, \"TxSingleCollision\" },\n\t{ 4, 0x24, \"TxMultipleCollision\" },\n\t{ 4, 0x28, \"TxDeferredTransmit\" },\n\t{ 4, 0x2c, \"TxLateCollision\" },\n\t{ 4, 0x30, \"TxExcessiveCollision\" },\n\t{ 4, 0x38, \"TxPausePkts\" },\n\t{ 8, 0x3c, \"TxQoSOctets\" },\n\t{ 8, 0x44, \"RxOctets\" },\n\t{ 4, 0x4c, \"RxUndersizePkts\" },\n\t{ 4, 0x50, \"RxPausePkts\" },\n\t{ 4, 0x54, \"Pkts64Octets\" },\n\t{ 4, 0x58, \"Pkts65to127Octets\" },\n\t{ 4, 0x5c, \"Pkts128to255Octets\" },\n\t{ 4, 0x60, \"Pkts256to511Octets\" },\n\t{ 4, 0x64, \"Pkts512to1023Octets\" },\n\t{ 4, 0x68, \"Pkts1024to1522Octets\" },\n\t{ 4, 0x6c, \"RxOversizePkts\" },\n\t{ 4, 0x70, \"RxJabbers\" },\n\t{ 4, 0x74, \"RxAlignmentErrors\" },\n\t{ 4, 0x78, \"RxFCSErrors\" },\n\t{ 8, 0x7c, \"RxGoodOctets\" },\n\t{ 4, 0x84, \"RxDropPkts\" },\n\t{ 4, 0x88, \"RxUnicastPkts\" },\n\t{ 4, 0x8c, \"RxMulticastPkts\" },\n\t{ 4, 0x90, \"RxBroadcastPkts\" },\n\t{ 4, 0x94, \"RxSAChanges\" },\n\t{ 4, 0x98, \"RxFragments\" },\n\t{ 4, 0xa0, \"RxSymbolErrors\" },\n\t{ 4, 0xa4, \"RxQoSPkts\" },\n\t{ 8, 0xa8, \"RxQoSOctets\" },\n\t{ 4, 0xb0, \"Pkts1523to2047Octets\" },\n\t{ 4, 0xb4, \"Pkts2048to4095Octets\" },\n\t{ 4, 0xb8, \"Pkts4096to8191Octets\" },\n\t{ 4, 0xbc, \"Pkts8192to9728Octets\" },\n\t{ 4, 0xc0, \"RxDiscarded\" },\n\t{ }\n};\n\n#define B53XX_MIB_TXB_ID\t0\t/* TxOctets */\n#define B53XX_MIB_RXB_ID\t12\t/* RxOctets */\n\n/* MIB counters */\nstatic const struct b53_mib_desc b53_mibs[] = {\n\t{ 8, 0x00, \"TxOctets\" },\n\t{ 4, 0x08, \"TxDropPkts\" },\n\t{ 4, 0x10, \"TxBroadcastPkts\" },\n\t{ 4, 0x14, \"TxMulticastPkts\" },\n\t{ 4, 0x18, \"TxUnicastPkts\" },\n\t{ 4, 0x1c, \"TxCollisions\" },\n\t{ 4, 0x20, \"TxSingleCollision\" },\n\t{ 4, 0x24, \"TxMultipleCollision\" },\n\t{ 4, 0x28, \"TxDeferredTransmit\" },\n\t{ 4, 0x2c, \"TxLateCollision\" },\n\t{ 4, 0x30, \"TxExcessiveCollision\" },\n\t{ 4, 0x38, \"TxPausePkts\" },\n\t{ 8, 0x50, \"RxOctets\" },\n\t{ 4, 0x58, \"RxUndersizePkts\" },\n\t{ 4, 0x5c, \"RxPausePkts\" },\n\t{ 4, 0x60, \"Pkts64Octets\" },\n\t{ 4, 0x64, \"Pkts65to127Octets\" },\n\t{ 4, 0x68, \"Pkts128to255Octets\" },\n\t{ 4, 0x6c, \"Pkts256to511Octets\" },\n\t{ 4, 0x70, \"Pkts512to1023Octets\" },\n\t{ 4, 0x74, \"Pkts1024to1522Octets\" },\n\t{ 4, 0x78, \"RxOversizePkts\" },\n\t{ 4, 0x7c, \"RxJabbers\" },\n\t{ 4, 0x80, \"RxAlignmentErrors\" },\n\t{ 4, 0x84, \"RxFCSErrors\" },\n\t{ 8, 0x88, \"RxGoodOctets\" },\n\t{ 4, 0x90, \"RxDropPkts\" },\n\t{ 4, 0x94, \"RxUnicastPkts\" },\n\t{ 4, 0x98, \"RxMulticastPkts\" },\n\t{ 4, 0x9c, \"RxBroadcastPkts\" },\n\t{ 4, 0xa0, \"RxSAChanges\" },\n\t{ 4, 0xa4, \"RxFragments\" },\n\t{ 4, 0xa8, \"RxJumboPkts\" },\n\t{ 4, 0xac, \"RxSymbolErrors\" },\n\t{ 4, 0xc0, \"RxDiscarded\" },\n\t{ }\n};\n\nstatic int b53_do_vlan_op(struct b53_device *dev, u8 op)\n{\n\tunsigned int i;\n\n\tb53_write8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], VTA_START_CMD | op);\n\n\tfor (i = 0; i < 10; i++) {\n\t\tu8 vta;\n\n\t\tb53_read8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], &vta);\n\t\tif (!(vta & VTA_START_CMD))\n\t\t\treturn 0;\n\n\t\tusleep_range(100, 200);\n\t}\n\n\treturn -EIO;\n}\n\nstatic void b53_set_vlan_entry(struct b53_device *dev, u16 vid, u16 members,\n\t\t\t       u16 untag)\n{\n\tif (is5325(dev)) {\n\t\tu32 entry = 0;\n\n\t\tif (members) {\n\t\t\tentry = ((untag & VA_UNTAG_MASK_25) << VA_UNTAG_S_25) |\n\t\t\t\tmembers;\n\t\t\tif (dev->core_rev >= 3)\n\t\t\t\tentry |= VA_VALID_25_R4 | vid << VA_VID_HIGH_S;\n\t\t\telse\n\t\t\t\tentry |= VA_VALID_25;\n\t\t}\n\n\t\tb53_write32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, entry);\n\t\tb53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid |\n\t\t\t    VTA_RW_STATE_WR | VTA_RW_OP_EN);\n\t} else if (is5365(dev)) {\n\t\tu16 entry = 0;\n\n\t\tif (members)\n\t\t\tentry = ((untag & VA_UNTAG_MASK_65) << VA_UNTAG_S_65) |\n\t\t\t\tmembers | VA_VALID_65;\n\n\t\tb53_write16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, entry);\n\t\tb53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid |\n\t\t\t    VTA_RW_STATE_WR | VTA_RW_OP_EN);\n\t} else {\n\t\tb53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid);\n\t\tb53_write32(dev, B53_ARLIO_PAGE, dev->vta_regs[2],\n\t\t\t    (untag << VTE_UNTAG_S) | members);\n\n\t\tb53_do_vlan_op(dev, VTA_CMD_WRITE);\n\t}\n}\n\nvoid b53_set_forwarding(struct b53_device *dev, int enable)\n{\n\tu8 mgmt;\n\n\tb53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);\n\n\tif (enable)\n\t\tmgmt |= SM_SW_FWD_EN;\n\telse\n\t\tmgmt &= ~SM_SW_FWD_EN;\n\n\tb53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);\n}\n\nstatic void b53_enable_vlan(struct b53_device *dev, int enable)\n{\n\tu8 mgmt, vc0, vc1, vc4 = 0, vc5;\n\n\tb53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);\n\tb53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, &vc0);\n\tb53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, &vc1);\n\n\tif (is5325(dev) || is5365(dev)) {\n\t\tb53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4);\n\t\tb53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, &vc5);\n\t} else if (is63xx(dev)) {\n\t\tb53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, &vc4);\n\t\tb53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, &vc5);\n\t} else {\n\t\tb53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, &vc4);\n\t\tb53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, &vc5);\n\t}\n\n\tmgmt &= ~SM_SW_FWD_MODE;\n\n\tif (enable) {\n\t\tvc0 |= VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID;\n\t\tvc1 |= VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN;\n\t\tvc4 &= ~VC4_ING_VID_CHECK_MASK;\n\t\tvc4 |= VC4_ING_VID_VIO_DROP << VC4_ING_VID_CHECK_S;\n\t\tvc5 |= VC5_DROP_VTABLE_MISS;\n\n\t\tif (is5325(dev))\n\t\t\tvc0 &= ~VC0_RESERVED_1;\n\n\t\tif (is5325(dev) || is5365(dev))\n\t\t\tvc1 |= VC1_RX_MCST_TAG_EN;\n\n\t\tif (!is5325(dev) && !is5365(dev)) {\n\t\t\tif (dev->allow_vid_4095)\n\t\t\t\tvc5 |= VC5_VID_FFF_EN;\n\t\t\telse\n\t\t\t\tvc5 &= ~VC5_VID_FFF_EN;\n\t\t}\n\t} else {\n\t\tvc0 &= ~(VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID);\n\t\tvc1 &= ~(VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN);\n\t\tvc4 &= ~VC4_ING_VID_CHECK_MASK;\n\t\tvc5 &= ~VC5_DROP_VTABLE_MISS;\n\n\t\tif (is5325(dev) || is5365(dev))\n\t\t\tvc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S;\n\t\telse\n\t\t\tvc4 |= VC4_ING_VID_VIO_TO_IMP << VC4_ING_VID_CHECK_S;\n\n\t\tif (is5325(dev) || is5365(dev))\n\t\t\tvc1 &= ~VC1_RX_MCST_TAG_EN;\n\n\t\tif (!is5325(dev) && !is5365(dev))\n\t\t\tvc5 &= ~VC5_VID_FFF_EN;\n\t}\n\n\tb53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, vc0);\n\tb53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, vc1);\n\n\tif (is5325(dev) || is5365(dev)) {\n\t\t/* enable the high 8 bit vid check on 5325 */\n\t\tif (is5325(dev) && enable)\n\t\t\tb53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3,\n\t\t\t\t   VC3_HIGH_8BIT_EN);\n\t\telse\n\t\t\tb53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0);\n\n\t\tb53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, vc4);\n\t\tb53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, vc5);\n\t} else if (is63xx(dev)) {\n\t\tb53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3_63XX, 0);\n\t\tb53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, vc4);\n\t\tb53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, vc5);\n\t} else {\n\t\tb53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0);\n\t\tb53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, vc4);\n\t\tb53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, vc5);\n\t}\n\n\tb53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);\n}\n\nstatic int b53_set_jumbo(struct b53_device *dev, int enable, int allow_10_100)\n{\n\tu32 port_mask = 0;\n\tu16 max_size = JMS_MIN_SIZE;\n\n\tif (is5325(dev) || is5365(dev))\n\t\treturn -EINVAL;\n\n\tif (enable) {\n\t\tport_mask = dev->enabled_ports;\n\t\tmax_size = JMS_MAX_SIZE;\n\t\tif (allow_10_100)\n\t\t\tport_mask |= JPM_10_100_JUMBO_EN;\n\t}\n\n\tb53_write32(dev, B53_JUMBO_PAGE, dev->jumbo_pm_reg, port_mask);\n\treturn b53_write16(dev, B53_JUMBO_PAGE, dev->jumbo_size_reg, max_size);\n}\n\nstatic int b53_flush_arl(struct b53_device *dev)\n{\n\tunsigned int i;\n\n\tb53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,\n\t\t   FAST_AGE_DONE | FAST_AGE_DYNAMIC | FAST_AGE_STATIC);\n\n\tfor (i = 0; i < 10; i++) {\n\t\tu8 fast_age_ctrl;\n\n\t\tb53_read8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,\n\t\t\t  &fast_age_ctrl);\n\n\t\tif (!(fast_age_ctrl & FAST_AGE_DONE))\n\t\t\treturn 0;\n\n\t\tmdelay(1);\n\t}\n\n\tpr_warn(\"time out while flushing ARL\\n\");\n\n\treturn -EINVAL;\n}\n\nstatic void b53_enable_ports(struct b53_device *dev)\n{\n\tunsigned i;\n\n\tb53_for_each_port(dev, i) {\n\t\tu8 port_ctrl;\n\t\tu16 pvlan_mask;\n\n\t\t/*\n\t\t * prevent leaking packets between wan and lan in unmanaged\n\t\t * mode through port vlans.\n\t\t */\n\t\tif (dev->enable_vlan || is_cpu_port(dev, i))\n\t\t\tpvlan_mask = 0x1ff;\n\t\telse if (is531x5(dev) || is5301x(dev))\n\t\t\t/* BCM53115 may use a different port as cpu port */\n\t\t\tpvlan_mask = BIT(dev->sw_dev.cpu_port);\n\t\telse\n\t\t\tpvlan_mask = BIT(B53_CPU_PORT);\n\n\t\t/* BCM5325 CPU port is at 8 */\n\t\tif ((is5325(dev) || is5365(dev)) && i == B53_CPU_PORT_25)\n\t\t\ti = B53_CPU_PORT;\n\n\t\tif (dev->chip_id == BCM5398_DEVICE_ID && (i == 6 || i == 7))\n\t\t\t/* disable unused ports 6 & 7 */\n\t\t\tport_ctrl = PORT_CTRL_RX_DISABLE | PORT_CTRL_TX_DISABLE;\n\t\telse if (i == B53_CPU_PORT)\n\t\t\tport_ctrl = PORT_CTRL_RX_BCST_EN |\n\t\t\t\t    PORT_CTRL_RX_MCST_EN |\n\t\t\t\t    PORT_CTRL_RX_UCST_EN;\n\t\telse\n\t\t\tport_ctrl = 0;\n\n\t\tb53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i),\n\t\t\t    pvlan_mask);\n\n\t\t/* port state is handled by bcm63xx_enet driver */\n\t\tif (!is63xx(dev) && !(is5301x(dev) && i == 6))\n\t\t\tb53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(i),\n\t\t\t\t   port_ctrl);\n\t}\n}\n\nstatic void b53_enable_mib(struct b53_device *dev)\n{\n\tu8 gc;\n\n\tb53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc);\n\n\tgc &= ~(GC_RESET_MIB | GC_MIB_AC_EN);\n\n\tb53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc);\n}\n\nstatic int b53_apply(struct b53_device *dev)\n{\n\tint i;\n\n\t/* clear all vlan entries */\n\tif (is5325(dev) || is5365(dev)) {\n\t\tfor (i = 1; i < dev->sw_dev.vlans; i++)\n\t\t\tb53_set_vlan_entry(dev, i, 0, 0);\n\t} else {\n\t\tb53_do_vlan_op(dev, VTA_CMD_CLEAR);\n\t}\n\n\tb53_enable_vlan(dev, dev->enable_vlan);\n\n\t/* fill VLAN table */\n\tif (dev->enable_vlan) {\n\t\tfor (i = 0; i < dev->sw_dev.vlans; i++) {\n\t\t\tstruct b53_vlan *vlan = &dev->vlans[i];\n\n\t\t\tif (!vlan->members)\n\t\t\t\tcontinue;\n\n\t\t\tb53_set_vlan_entry(dev, i, vlan->members, vlan->untag);\n\t\t}\n\n\t\tb53_for_each_port(dev, i)\n\t\t\tb53_write16(dev, B53_VLAN_PAGE,\n\t\t\t\t    B53_VLAN_PORT_DEF_TAG(i),\n\t\t\t\t    dev->ports[i].pvid);\n\t} else {\n\t\tb53_for_each_port(dev, i)\n\t\t\tb53_write16(dev, B53_VLAN_PAGE,\n\t\t\t\t    B53_VLAN_PORT_DEF_TAG(i), 1);\n\n\t}\n\n\tb53_enable_ports(dev);\n\n\tif (!is5325(dev) && !is5365(dev))\n\t\tb53_set_jumbo(dev, dev->enable_jumbo, 1);\n\n\treturn 0;\n}\n\nstatic void b53_switch_reset_gpio(struct b53_device *dev)\n{\n\tint gpio = dev->reset_gpio;\n\n\tif (gpio < 0)\n\t\treturn;\n\n\t/*\n\t * Reset sequence: RESET low(50ms)->high(20ms)\n\t */\n\tgpio_set_value(gpio, 0);\n\tmdelay(50);\n\n\tgpio_set_value(gpio, 1);\n\tmdelay(20);\n\n\tdev->current_page = 0xff;\n}\n\nstatic int b53_configure_ports_of(struct b53_device *dev)\n{\n\tstruct device_node *dn, *pn;\n\tu32 port_num;\n\n\tdn = of_get_child_by_name(dev_of_node(dev->dev), \"ports\");\n\n\tfor_each_available_child_of_node(dn, pn) {\n\t\tstruct device_node *fixed_link;\n\n\t\tif (of_property_read_u32(pn, \"reg\", &port_num))\n\t\t\tcontinue;\n\n\t\tif (port_num > B53_CPU_PORT)\n\t\t\tcontinue;\n\n\t\tfixed_link = of_get_child_by_name(pn, \"fixed-link\");\n\t\tif (fixed_link) {\n\t\t\tu32 spd;\n\t\t\tu8 po = GMII_PO_LINK;\n#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 5, 0)\n\t\t\tphy_interface_t mode;\n#else\n\t\t\tint mode = of_get_phy_mode(pn);\n#endif\n\n#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 5, 0)\n\t\t\tof_get_phy_mode(pn, &mode);\n#endif\n\n\t\t\tif (!of_property_read_u32(fixed_link, \"speed\", &spd)) {\n\t\t\t\tswitch (spd) {\n\t\t\t\tcase 10:\n\t\t\t\t\tpo |= GMII_PO_SPEED_10M;\n\t\t\t\t\tbreak;\n\t\t\t\tcase 100:\n\t\t\t\t\tpo |= GMII_PO_SPEED_100M;\n\t\t\t\t\tbreak;\n\t\t\t\tcase 2000:\n\t\t\t\t\tif (is_imp_port(dev, port_num))\n\t\t\t\t\t\tpo |= PORT_OVERRIDE_SPEED_2000M;\n\t\t\t\t\telse\n\t\t\t\t\t\tpo |= GMII_PO_SPEED_2000M;\n\t\t\t\t\tfallthrough;\n\t\t\t\tcase 1000:\n\t\t\t\t\tpo |= GMII_PO_SPEED_1000M;\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t}\n\n\t\t\tif (of_property_read_bool(fixed_link, \"full-duplex\"))\n\t\t\t\tpo |= PORT_OVERRIDE_FULL_DUPLEX;\n\t\t\tif (of_property_read_bool(fixed_link, \"pause\"))\n\t\t\t\tpo |= GMII_PO_RX_FLOW;\n\t\t\tif (of_property_read_bool(fixed_link, \"asym-pause\"))\n\t\t\t\tpo |= GMII_PO_TX_FLOW;\n\n\t\t\tif (is_imp_port(dev, port_num)) {\n\t\t\t\tpo |= PORT_OVERRIDE_EN;\n\n\t\t\t\tif (is5325(dev) &&\n\t\t\t\t    mode == PHY_INTERFACE_MODE_REVMII)\n\t\t\t\t\tpo |= PORT_OVERRIDE_RV_MII_25;\n\n\t\t\t\tb53_write8(dev, B53_CTRL_PAGE,\n\t\t\t\t\t   B53_PORT_OVERRIDE_CTRL, po);\n\n\t\t\t\tif (is5325(dev) &&\n\t\t\t\t    mode == PHY_INTERFACE_MODE_REVMII) {\n\t\t\t\t\tb53_read8(dev, B53_CTRL_PAGE,\n\t\t\t\t\t\t  B53_PORT_OVERRIDE_CTRL, &po);\n\t\t\t\t\tif (!(po & PORT_OVERRIDE_RV_MII_25))\n\t\t\t\t\tpr_err(\"Failed to enable reverse MII mode\\n\");\n\t\t\t\t\treturn -EINVAL;\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\tpo |= GMII_PO_EN;\n\t\t\t\tb53_write8(dev, B53_CTRL_PAGE,\n\t\t\t\t\t   B53_GMII_PORT_OVERRIDE_CTRL(port_num),\n\t\t\t\t\t   po);\n\t\t\t}\n\t\t}\n\t}\n\n\treturn 0;\n}\n\nstatic int b53_configure_ports(struct b53_device *dev)\n{\n\tu8 cpu_port = dev->sw_dev.cpu_port;\n\n\t/* configure MII port if necessary */\n\tif (is5325(dev)) {\n\t\tu8 mii_port_override;\n\n\t\tb53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,\n\t\t\t  &mii_port_override);\n\t\t/* reverse mii needs to be enabled */\n\t\tif (!(mii_port_override & PORT_OVERRIDE_RV_MII_25)) {\n\t\t\tb53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,\n\t\t\t\t   mii_port_override | PORT_OVERRIDE_RV_MII_25);\n\t\t\tb53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,\n\t\t\t\t  &mii_port_override);\n\n\t\t\tif (!(mii_port_override & PORT_OVERRIDE_RV_MII_25)) {\n\t\t\t\tpr_err(\"Failed to enable reverse MII mode\\n\");\n\t\t\t\treturn -EINVAL;\n\t\t\t}\n\t\t}\n\t} else if (is531x5(dev) && cpu_port == B53_CPU_PORT) {\n\t\tu8 mii_port_override;\n\n\t\tb53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,\n\t\t\t  &mii_port_override);\n\t\tb53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,\n\t\t\t   mii_port_override | PORT_OVERRIDE_EN |\n\t\t\t   PORT_OVERRIDE_LINK);\n\n\t\t/* BCM47189 has another interface connected to the port 5 */\n\t\tif (dev->enabled_ports & BIT(5)) {\n\t\t\tu8 po_reg = B53_GMII_PORT_OVERRIDE_CTRL(5);\n\t\t\tu8 gmii_po;\n\n\t\t\tb53_read8(dev, B53_CTRL_PAGE, po_reg, &gmii_po);\n\t\t\tgmii_po |= GMII_PO_LINK |\n\t\t\t\t   GMII_PO_RX_FLOW |\n\t\t\t\t   GMII_PO_TX_FLOW |\n\t\t\t\t   GMII_PO_EN;\n\t\t\tb53_write8(dev, B53_CTRL_PAGE, po_reg, gmii_po);\n\t\t}\n\t} else if (is5301x(dev)) {\n\t\tif (cpu_port == 8) {\n\t\t\tu8 mii_port_override;\n\n\t\t\tb53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,\n\t\t\t\t  &mii_port_override);\n\t\t\tmii_port_override |= PORT_OVERRIDE_LINK |\n\t\t\t\t\t     PORT_OVERRIDE_RX_FLOW |\n\t\t\t\t\t     PORT_OVERRIDE_TX_FLOW |\n\t\t\t\t\t     PORT_OVERRIDE_SPEED_2000M |\n\t\t\t\t\t     PORT_OVERRIDE_EN;\n\t\t\tb53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,\n\t\t\t\t   mii_port_override);\n\n\t\t\t/* TODO: Ports 5 & 7 require some extra handling */\n\t\t} else {\n\t\t\tu8 po_reg = B53_GMII_PORT_OVERRIDE_CTRL(cpu_port);\n\t\t\tu8 gmii_po;\n\n\t\t\tb53_read8(dev, B53_CTRL_PAGE, po_reg, &gmii_po);\n\t\t\tgmii_po |= GMII_PO_LINK |\n\t\t\t\t   GMII_PO_RX_FLOW |\n\t\t\t\t   GMII_PO_TX_FLOW |\n\t\t\t\t   GMII_PO_EN |\n\t\t\t\t   GMII_PO_SPEED_2000M;\n\t\t\tb53_write8(dev, B53_CTRL_PAGE, po_reg, gmii_po);\n\t\t}\n\t}\n\n\treturn 0;\n}\n\nstatic int b53_switch_reset(struct b53_device *dev)\n{\n\tint ret = 0;\n\tu8 mgmt;\n\n\tb53_switch_reset_gpio(dev);\n\n\tif (is539x(dev)) {\n\t\tb53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x83);\n\t\tb53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x00);\n\t}\n\n\tb53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);\n\n\tif (!(mgmt & SM_SW_FWD_EN)) {\n\t\tmgmt &= ~SM_SW_FWD_MODE;\n\t\tmgmt |= SM_SW_FWD_EN;\n\n\t\tb53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);\n\t\tb53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);\n\n\t\tif (!(mgmt & SM_SW_FWD_EN)) {\n\t\t\tpr_err(\"Failed to enable switch!\\n\");\n\t\t\treturn -EINVAL;\n\t\t}\n\t}\n\n\t/* enable all ports */\n\tb53_enable_ports(dev);\n\n\tif (dev->dev->of_node)\n\t\tret = b53_configure_ports_of(dev);\n\telse\n\t\tret = b53_configure_ports(dev);\n\n\tif (ret)\n\t\treturn ret;\n\n\tb53_enable_mib(dev);\n\n\treturn b53_flush_arl(dev);\n}\n\n/*\n * Swconfig glue functions\n */\n\nstatic int b53_global_get_vlan_enable(struct switch_dev *dev,\n\t\t\t\t      const struct switch_attr *attr,\n\t\t\t\t      struct switch_val *val)\n{\n\tstruct b53_device *priv = sw_to_b53(dev);\n\n\tval->value.i = priv->enable_vlan;\n\n\treturn 0;\n}\n\nstatic int b53_global_set_vlan_enable(struct switch_dev *dev,\n\t\t\t\t      const struct switch_attr *attr,\n\t\t\t\t      struct switch_val *val)\n{\n\tstruct b53_device *priv = sw_to_b53(dev);\n\n\tpriv->enable_vlan = val->value.i;\n\n\treturn 0;\n}\n\nstatic int b53_global_get_jumbo_enable(struct switch_dev *dev,\n\t\t\t\t       const struct switch_attr *attr,\n\t\t\t\t       struct switch_val *val)\n{\n\tstruct b53_device *priv = sw_to_b53(dev);\n\n\tval->value.i = priv->enable_jumbo;\n\n\treturn 0;\n}\n\nstatic int b53_global_set_jumbo_enable(struct switch_dev *dev,\n\t\t\t\t       const struct switch_attr *attr,\n\t\t\t\t       struct switch_val *val)\n{\n\tstruct b53_device *priv = sw_to_b53(dev);\n\n\tpriv->enable_jumbo = val->value.i;\n\n\treturn 0;\n}\n\nstatic int b53_global_get_4095_enable(struct switch_dev *dev,\n\t\t\t\t      const struct switch_attr *attr,\n\t\t\t\t      struct switch_val *val)\n{\n\tstruct b53_device *priv = sw_to_b53(dev);\n\n\tval->value.i = priv->allow_vid_4095;\n\n\treturn 0;\n}\n\nstatic int b53_global_set_4095_enable(struct switch_dev *dev,\n\t\t\t\t      const struct switch_attr *attr,\n\t\t\t\t      struct switch_val *val)\n{\n\tstruct b53_device *priv = sw_to_b53(dev);\n\n\tpriv->allow_vid_4095 = val->value.i;\n\n\treturn 0;\n}\n\nstatic int b53_global_get_ports(struct switch_dev *dev,\n\t\t\t\tconst struct switch_attr *attr,\n\t\t\t\tstruct switch_val *val)\n{\n\tstruct b53_device *priv = sw_to_b53(dev);\n\n\tval->len = snprintf(priv->buf, B53_BUF_SIZE, \"0x%04x\",\n\t\t\t    priv->enabled_ports);\n\tval->value.s = priv->buf;\n\n\treturn 0;\n}\n\nstatic int b53_port_get_pvid(struct switch_dev *dev, int port, int *val)\n{\n\tstruct b53_device *priv = sw_to_b53(dev);\n\n\t*val = priv->ports[port].pvid;\n\n\treturn 0;\n}\n\nstatic int b53_port_set_pvid(struct switch_dev *dev, int port, int val)\n{\n\tstruct b53_device *priv = sw_to_b53(dev);\n\n\tif (val > 15 && is5325(priv))\n\t\treturn -EINVAL;\n\tif (val == 4095 && !priv->allow_vid_4095)\n\t\treturn -EINVAL;\n\n\tpriv->ports[port].pvid = val;\n\n\treturn 0;\n}\n\nstatic int b53_vlan_get_ports(struct switch_dev *dev, struct switch_val *val)\n{\n\tstruct b53_device *priv = sw_to_b53(dev);\n\tstruct switch_port *port = &val->value.ports[0];\n\tstruct b53_vlan *vlan = &priv->vlans[val->port_vlan];\n\tint i;\n\n\tval->len = 0;\n\n\tif (!vlan->members)\n\t\treturn 0;\n\n\tfor (i = 0; i < dev->ports; i++) {\n\t\tif (!(vlan->members & BIT(i)))\n\t\t\tcontinue;\n\n\n\t\tif (!(vlan->untag & BIT(i)))\n\t\t\tport->flags = BIT(SWITCH_PORT_FLAG_TAGGED);\n\t\telse\n\t\t\tport->flags = 0;\n\n\t\tport->id = i;\n\t\tval->len++;\n\t\tport++;\n\t}\n\n\treturn 0;\n}\n\nstatic int b53_vlan_set_ports(struct switch_dev *dev, struct switch_val *val)\n{\n\tstruct b53_device *priv = sw_to_b53(dev);\n\tstruct switch_port *port;\n\tstruct b53_vlan *vlan = &priv->vlans[val->port_vlan];\n\tint i;\n\n\t/* only BCM5325 and BCM5365 supports VID 0 */\n\tif (val->port_vlan == 0 && !is5325(priv) && !is5365(priv))\n\t\treturn -EINVAL;\n\n\t/* VLAN 4095 needs special handling */\n\tif (val->port_vlan == 4095 && !priv->allow_vid_4095)\n\t\treturn -EINVAL;\n\n\tport = &val->value.ports[0];\n\tvlan->members = 0;\n\tvlan->untag = 0;\n\tfor (i = 0; i < val->len; i++, port++) {\n\t\tvlan->members |= BIT(port->id);\n\n\t\tif (!(port->flags & BIT(SWITCH_PORT_FLAG_TAGGED))) {\n\t\t\tvlan->untag |= BIT(port->id);\n\t\t\tpriv->ports[port->id].pvid = val->port_vlan;\n\t\t};\n\t}\n\n\t/* ignore disabled ports */\n\tvlan->members &= priv->enabled_ports;\n\tvlan->untag &= priv->enabled_ports;\n\n\treturn 0;\n}\n\nstatic int b53_port_get_link(struct switch_dev *dev, int port,\n\t\t\t     struct switch_port_link *link)\n{\n\tstruct b53_device *priv = sw_to_b53(dev);\n\n\tif (is_cpu_port(priv, port)) {\n\t\tlink->link = 1;\n\t\tlink->duplex = 1;\n\t\tlink->speed = is5325(priv) || is5365(priv) ?\n\t\t\t\tSWITCH_PORT_SPEED_100 : SWITCH_PORT_SPEED_1000;\n\t\tlink->aneg = 0;\n\t} else if (priv->enabled_ports & BIT(port)) {\n\t\tu32 speed;\n\t\tu16 lnk, duplex;\n\n\t\tb53_read16(priv, B53_STAT_PAGE, B53_LINK_STAT, &lnk);\n\t\tb53_read16(priv, B53_STAT_PAGE, priv->duplex_reg, &duplex);\n\n\t\tlnk = (lnk >> port) & 1;\n\t\tduplex = (duplex >> port) & 1;\n\n\t\tif (is5325(priv) || is5365(priv)) {\n\t\t\tu16 tmp;\n\n\t\t\tb53_read16(priv, B53_STAT_PAGE, B53_SPEED_STAT, &tmp);\n\t\t\tspeed = SPEED_PORT_FE(tmp, port);\n\t\t} else {\n\t\t\tb53_read32(priv, B53_STAT_PAGE, B53_SPEED_STAT, &speed);\n\t\t\tspeed = SPEED_PORT_GE(speed, port);\n\t\t}\n\n\t\tlink->link = lnk;\n\t\tif (lnk) {\n\t\t\tlink->duplex = duplex;\n\t\t\tswitch (speed) {\n\t\t\tcase SPEED_STAT_10M:\n\t\t\t\tlink->speed = SWITCH_PORT_SPEED_10;\n\t\t\t\tbreak;\n\t\t\tcase SPEED_STAT_100M:\n\t\t\t\tlink->speed = SWITCH_PORT_SPEED_100;\n\t\t\t\tbreak;\n\t\t\tcase SPEED_STAT_1000M:\n\t\t\t\tlink->speed = SWITCH_PORT_SPEED_1000;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\n\t\tlink->aneg = 1;\n\t} else {\n\t\tlink->link = 0;\n\t}\n\n\treturn 0;\n\n}\n\nstatic int b53_port_set_link(struct switch_dev *sw_dev, int port,\n\t\t\t     struct switch_port_link *link)\n{\n\tstruct b53_device *dev = sw_to_b53(sw_dev);\n\n\t/*\n\t * TODO: BCM63XX requires special handling as it can have external phys\n\t * and ports might be GE or only FE\n\t */\n\tif (is63xx(dev))\n\t\treturn -ENOTSUPP;\n\n\tif (port == sw_dev->cpu_port)\n\t\treturn -EINVAL;\n\n\tif (!(BIT(port) & dev->enabled_ports))\n\t\treturn -EINVAL;\n\n\tif (link->speed == SWITCH_PORT_SPEED_1000 &&\n\t    (is5325(dev) || is5365(dev)))\n\t\treturn -EINVAL;\n\n\tif (link->speed == SWITCH_PORT_SPEED_1000 && !link->duplex)\n\t\treturn -EINVAL;\n\n\treturn switch_generic_set_link(sw_dev, port, link);\n}\n\nstatic int b53_phy_read16(struct switch_dev *dev, int addr, u8 reg, u16 *value)\n{\n\tstruct b53_device *priv = sw_to_b53(dev);\n\n\tif (priv->ops->phy_read16)\n\t\treturn priv->ops->phy_read16(priv, addr, reg, value);\n\n\treturn b53_read16(priv, B53_PORT_MII_PAGE(addr), reg, value);\n}\n\nstatic int b53_phy_write16(struct switch_dev *dev, int addr, u8 reg, u16 value)\n{\n\tstruct b53_device *priv = sw_to_b53(dev);\n\n\tif (priv->ops->phy_write16)\n\t\treturn priv->ops->phy_write16(priv, addr, reg, value);\n\n\treturn b53_write16(priv, B53_PORT_MII_PAGE(addr), reg, value);\n}\n\nstatic int b53_global_reset_switch(struct switch_dev *dev)\n{\n\tstruct b53_device *priv = sw_to_b53(dev);\n\n\t/* reset vlans */\n\tpriv->enable_vlan = 0;\n\tpriv->enable_jumbo = 0;\n\tpriv->allow_vid_4095 = 0;\n\n\tmemset(priv->vlans, 0, sizeof(*priv->vlans) * dev->vlans);\n\tmemset(priv->ports, 0, sizeof(*priv->ports) * dev->ports);\n\n\treturn b53_switch_reset(priv);\n}\n\nstatic int b53_global_apply_config(struct switch_dev *dev)\n{\n\tstruct b53_device *priv = sw_to_b53(dev);\n\n\t/* disable switching */\n\tb53_set_forwarding(priv, 0);\n\n\tb53_apply(priv);\n\n\t/* enable switching */\n\tb53_set_forwarding(priv, 1);\n\n\treturn 0;\n}\n\n\nstatic int b53_global_reset_mib(struct switch_dev *dev,\n\t\t\t\tconst struct switch_attr *attr,\n\t\t\t\tstruct switch_val *val)\n{\n\tstruct b53_device *priv = sw_to_b53(dev);\n\tu8 gc;\n\n\tb53_read8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc);\n\n\tb53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc | GC_RESET_MIB);\n\tmdelay(1);\n\tb53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc & ~GC_RESET_MIB);\n\tmdelay(1);\n\n\treturn 0;\n}\n\nstatic int b53_port_get_mib(struct switch_dev *sw_dev,\n\t\t\t    const struct switch_attr *attr,\n\t\t\t    struct switch_val *val)\n{\n\tstruct b53_device *dev = sw_to_b53(sw_dev);\n\tconst struct b53_mib_desc *mibs;\n\tint port = val->port_vlan;\n\tint len = 0;\n\n\tif (!(BIT(port) & dev->enabled_ports))\n\t\treturn -1;\n\n\tif (is5365(dev)) {\n\t\tif (port == 5)\n\t\t\tport = 8;\n\n\t\tmibs = b53_mibs_65;\n\t} else if (is63xx(dev)) {\n\t\tmibs = b53_mibs_63xx;\n\t} else {\n\t\tmibs = b53_mibs;\n\t}\n\n\tdev->buf[0] = 0;\n\n\tfor (; mibs->size > 0; mibs++) {\n\t\tu64 val;\n\n\t\tif (mibs->size == 8) {\n\t\t\tb53_read64(dev, B53_MIB_PAGE(port), mibs->offset, &val);\n\t\t} else {\n\t\t\tu32 val32;\n\n\t\t\tb53_read32(dev, B53_MIB_PAGE(port), mibs->offset,\n\t\t\t\t   &val32);\n\t\t\tval = val32;\n\t\t}\n\n\t\tlen += snprintf(dev->buf + len, B53_BUF_SIZE - len,\n\t\t\t\t\"%-20s: %llu\\n\", mibs->name, val);\n\t}\n\n\tval->len = len;\n\tval->value.s = dev->buf;\n\n\treturn 0;\n}\n\nstatic int b53_port_get_stats(struct switch_dev *sw_dev, int port,\n\t\t\t\tstruct switch_port_stats *stats)\n{\n\tstruct b53_device *dev = sw_to_b53(sw_dev);\n\tconst struct b53_mib_desc *mibs;\n\tint txb_id, rxb_id;\n\tu64 rxb, txb;\n\n\tif (!(BIT(port) & dev->enabled_ports))\n\t\treturn -EINVAL;\n\n\ttxb_id = B53XX_MIB_TXB_ID;\n\trxb_id = B53XX_MIB_RXB_ID;\n\n\tif (is5365(dev)) {\n\t\tif (port == 5)\n\t\t\tport = 8;\n\n\t\tmibs = b53_mibs_65;\n\t} else if (is63xx(dev)) {\n\t\tmibs = b53_mibs_63xx;\n\t\ttxb_id = B63XX_MIB_TXB_ID;\n\t\trxb_id = B63XX_MIB_RXB_ID;\n\t} else {\n\t\tmibs = b53_mibs;\n\t}\n\n\tdev->buf[0] = 0;\n\n\tif (mibs->size == 8) {\n\t\tb53_read64(dev, B53_MIB_PAGE(port), mibs[txb_id].offset, &txb);\n\t\tb53_read64(dev, B53_MIB_PAGE(port), mibs[rxb_id].offset, &rxb);\n\t} else {\n\t\tu32 val32;\n\n\t\tb53_read32(dev, B53_MIB_PAGE(port), mibs[txb_id].offset, &val32);\n\t\ttxb = val32;\n\n\t\tb53_read32(dev, B53_MIB_PAGE(port), mibs[rxb_id].offset, &val32);\n\t\trxb = val32;\n\t}\n\n\tstats->tx_bytes = txb;\n\tstats->rx_bytes = rxb;\n\n\treturn 0;\n}\n\nstatic struct switch_attr b53_global_ops_25[] = {\n\t{\n\t\t.type = SWITCH_TYPE_INT,\n\t\t.name = \"enable_vlan\",\n\t\t.description = \"Enable VLAN mode\",\n\t\t.set = b53_global_set_vlan_enable,\n\t\t.get = b53_global_get_vlan_enable,\n\t\t.max = 1,\n\t},\n\t{\n\t\t.type = SWITCH_TYPE_STRING,\n\t\t.name = \"ports\",\n\t\t.description = \"Available ports (as bitmask)\",\n\t\t.get = b53_global_get_ports,\n\t},\n};\n\nstatic struct switch_attr b53_global_ops_65[] = {\n\t{\n\t\t.type = SWITCH_TYPE_INT,\n\t\t.name = \"enable_vlan\",\n\t\t.description = \"Enable VLAN mode\",\n\t\t.set = b53_global_set_vlan_enable,\n\t\t.get = b53_global_get_vlan_enable,\n\t\t.max = 1,\n\t},\n\t{\n\t\t.type = SWITCH_TYPE_STRING,\n\t\t.name = \"ports\",\n\t\t.description = \"Available ports (as bitmask)\",\n\t\t.get = b53_global_get_ports,\n\t},\n\t{\n\t\t.type = SWITCH_TYPE_INT,\n\t\t.name = \"reset_mib\",\n\t\t.description = \"Reset MIB counters\",\n\t\t.set = b53_global_reset_mib,\n\t},\n};\n\nstatic struct switch_attr b53_global_ops[] = {\n\t{\n\t\t.type = SWITCH_TYPE_INT,\n\t\t.name = \"enable_vlan\",\n\t\t.description = \"Enable VLAN mode\",\n\t\t.set = b53_global_set_vlan_enable,\n\t\t.get = b53_global_get_vlan_enable,\n\t\t.max = 1,\n\t},\n\t{\n\t\t.type = SWITCH_TYPE_STRING,\n\t\t.name = \"ports\",\n\t\t.description = \"Available Ports (as bitmask)\",\n\t\t.get = b53_global_get_ports,\n\t},\n\t{\n\t\t.type = SWITCH_TYPE_INT,\n\t\t.name = \"reset_mib\",\n\t\t.description = \"Reset MIB counters\",\n\t\t.set = b53_global_reset_mib,\n\t},\n\t{\n\t\t.type = SWITCH_TYPE_INT,\n\t\t.name = \"enable_jumbo\",\n\t\t.description = \"Enable Jumbo Frames\",\n\t\t.set = b53_global_set_jumbo_enable,\n\t\t.get = b53_global_get_jumbo_enable,\n\t\t.max = 1,\n\t},\n\t{\n\t\t.type = SWITCH_TYPE_INT,\n\t\t.name = \"allow_vid_4095\",\n\t\t.description = \"Allow VID 4095\",\n\t\t.set = b53_global_set_4095_enable,\n\t\t.get = b53_global_get_4095_enable,\n\t\t.max = 1,\n\t},\n};\n\nstatic struct switch_attr b53_port_ops[] = {\n\t{\n\t\t.type = SWITCH_TYPE_STRING,\n\t\t.name = \"mib\",\n\t\t.description = \"Get port's MIB counters\",\n\t\t.get = b53_port_get_mib,\n\t},\n};\n\nstatic struct switch_attr b53_no_ops[] = {\n};\n\nstatic const struct switch_dev_ops b53_switch_ops_25 = {\n\t.attr_global = {\n\t\t.attr = b53_global_ops_25,\n\t\t.n_attr = ARRAY_SIZE(b53_global_ops_25),\n\t},\n\t.attr_port = {\n\t\t.attr = b53_no_ops,\n\t\t.n_attr = ARRAY_SIZE(b53_no_ops),\n\t},\n\t.attr_vlan = {\n\t\t.attr = b53_no_ops,\n\t\t.n_attr = ARRAY_SIZE(b53_no_ops),\n\t},\n\n\t.get_vlan_ports = b53_vlan_get_ports,\n\t.set_vlan_ports = b53_vlan_set_ports,\n\t.get_port_pvid = b53_port_get_pvid,\n\t.set_port_pvid = b53_port_set_pvid,\n\t.apply_config = b53_global_apply_config,\n\t.reset_switch = b53_global_reset_switch,\n\t.get_port_link = b53_port_get_link,\n\t.set_port_link = b53_port_set_link,\n\t.get_port_stats = b53_port_get_stats,\n\t.phy_read16 = b53_phy_read16,\n\t.phy_write16 = b53_phy_write16,\n};\n\nstatic const struct switch_dev_ops b53_switch_ops_65 = {\n\t.attr_global = {\n\t\t.attr = b53_global_ops_65,\n\t\t.n_attr = ARRAY_SIZE(b53_global_ops_65),\n\t},\n\t.attr_port = {\n\t\t.attr = b53_port_ops,\n\t\t.n_attr = ARRAY_SIZE(b53_port_ops),\n\t},\n\t.attr_vlan = {\n\t\t.attr = b53_no_ops,\n\t\t.n_attr = ARRAY_SIZE(b53_no_ops),\n\t},\n\n\t.get_vlan_ports = b53_vlan_get_ports,\n\t.set_vlan_ports = b53_vlan_set_ports,\n\t.get_port_pvid = b53_port_get_pvid,\n\t.set_port_pvid = b53_port_set_pvid,\n\t.apply_config = b53_global_apply_config,\n\t.reset_switch = b53_global_reset_switch,\n\t.get_port_link = b53_port_get_link,\n\t.set_port_link = b53_port_set_link,\n\t.get_port_stats = b53_port_get_stats,\n\t.phy_read16 = b53_phy_read16,\n\t.phy_write16 = b53_phy_write16,\n};\n\nstatic const struct switch_dev_ops b53_switch_ops = {\n\t.attr_global = {\n\t\t.attr = b53_global_ops,\n\t\t.n_attr = ARRAY_SIZE(b53_global_ops),\n\t},\n\t.attr_port = {\n\t\t.attr = b53_port_ops,\n\t\t.n_attr = ARRAY_SIZE(b53_port_ops),\n\t},\n\t.attr_vlan = {\n\t\t.attr = b53_no_ops,\n\t\t.n_attr = ARRAY_SIZE(b53_no_ops),\n\t},\n\n\t.get_vlan_ports = b53_vlan_get_ports,\n\t.set_vlan_ports = b53_vlan_set_ports,\n\t.get_port_pvid = b53_port_get_pvid,\n\t.set_port_pvid = b53_port_set_pvid,\n\t.apply_config = b53_global_apply_config,\n\t.reset_switch = b53_global_reset_switch,\n\t.get_port_link = b53_port_get_link,\n\t.set_port_link = b53_port_set_link,\n\t.get_port_stats = b53_port_get_stats,\n\t.phy_read16 = b53_phy_read16,\n\t.phy_write16 = b53_phy_write16,\n};\n\nstruct b53_chip_data {\n\tu32 chip_id;\n\tconst char *dev_name;\n\tconst char *alias;\n\tu16 vlans;\n\tu16 enabled_ports;\n\tu8 cpu_port;\n\tu8 vta_regs[3];\n\tu8 duplex_reg;\n\tu8 jumbo_pm_reg;\n\tu8 jumbo_size_reg;\n\tconst struct switch_dev_ops *sw_ops;\n};\n\n#define B53_VTA_REGS\t\\\n\t{ B53_VT_ACCESS, B53_VT_INDEX, B53_VT_ENTRY }\n#define B53_VTA_REGS_9798 \\\n\t{ B53_VT_ACCESS_9798, B53_VT_INDEX_9798, B53_VT_ENTRY_9798 }\n#define B53_VTA_REGS_63XX \\\n\t{ B53_VT_ACCESS_63XX, B53_VT_INDEX_63XX, B53_VT_ENTRY_63XX }\n\nstatic const struct b53_chip_data b53_switch_chips[] = {\n\t{\n\t\t.chip_id = BCM5325_DEVICE_ID,\n\t\t.dev_name = \"BCM5325\",\n\t\t.alias = \"bcm5325\",\n\t\t.vlans = 16,\n\t\t.enabled_ports = 0x1f,\n\t\t.cpu_port = B53_CPU_PORT_25,\n\t\t.duplex_reg = B53_DUPLEX_STAT_FE,\n\t\t.sw_ops = &b53_switch_ops_25,\n\t},\n\t{\n\t\t.chip_id = BCM5365_DEVICE_ID,\n\t\t.dev_name = \"BCM5365\",\n\t\t.alias = \"bcm5365\",\n\t\t.vlans = 256,\n\t\t.enabled_ports = 0x1f,\n\t\t.cpu_port = B53_CPU_PORT_25,\n\t\t.duplex_reg = B53_DUPLEX_STAT_FE,\n\t\t.sw_ops = &b53_switch_ops_65,\n\t},\n\t{\n\t\t.chip_id = BCM5395_DEVICE_ID,\n\t\t.dev_name = \"BCM5395\",\n\t\t.alias = \"bcm5395\",\n\t\t.vlans = 4096,\n\t\t.enabled_ports = 0x1f,\n\t\t.cpu_port = B53_CPU_PORT,\n\t\t.vta_regs = B53_VTA_REGS,\n\t\t.duplex_reg = B53_DUPLEX_STAT_GE,\n\t\t.jumbo_pm_reg = B53_JUMBO_PORT_MASK,\n\t\t.jumbo_size_reg = B53_JUMBO_MAX_SIZE,\n\t\t.sw_ops = &b53_switch_ops,\n\t},\n\t{\n\t\t.chip_id = BCM5397_DEVICE_ID,\n\t\t.dev_name = \"BCM5397\",\n\t\t.alias = \"bcm5397\",\n\t\t.vlans = 4096,\n\t\t.enabled_ports = 0x1f,\n\t\t.cpu_port = B53_CPU_PORT,\n\t\t.vta_regs = B53_VTA_REGS_9798,\n\t\t.duplex_reg = B53_DUPLEX_STAT_GE,\n\t\t.jumbo_pm_reg = B53_JUMBO_PORT_MASK,\n\t\t.jumbo_size_reg = B53_JUMBO_MAX_SIZE,\n\t\t.sw_ops = &b53_switch_ops,\n\t},\n\t{\n\t\t.chip_id = BCM5398_DEVICE_ID,\n\t\t.dev_name = \"BCM5398\",\n\t\t.alias = \"bcm5398\",\n\t\t.vlans = 4096,\n\t\t.enabled_ports = 0x7f,\n\t\t.cpu_port = B53_CPU_PORT,\n\t\t.vta_regs = B53_VTA_REGS_9798,\n\t\t.duplex_reg = B53_DUPLEX_STAT_GE,\n\t\t.jumbo_pm_reg = B53_JUMBO_PORT_MASK,\n\t\t.jumbo_size_reg = B53_JUMBO_MAX_SIZE,\n\t\t.sw_ops = &b53_switch_ops,\n\t},\n\t{\n\t\t.chip_id = BCM53115_DEVICE_ID,\n\t\t.dev_name = \"BCM53115\",\n\t\t.alias = \"bcm53115\",\n\t\t.vlans = 4096,\n\t\t.enabled_ports = 0x1f,\n\t\t.vta_regs = B53_VTA_REGS,\n\t\t.cpu_port = B53_CPU_PORT,\n\t\t.duplex_reg = B53_DUPLEX_STAT_GE,\n\t\t.jumbo_pm_reg = B53_JUMBO_PORT_MASK,\n\t\t.jumbo_size_reg = B53_JUMBO_MAX_SIZE,\n\t\t.sw_ops = &b53_switch_ops,\n\t},\n\t{\n\t\t.chip_id = BCM53125_DEVICE_ID,\n\t\t.dev_name = \"BCM53125\",\n\t\t.alias = \"bcm53125\",\n\t\t.vlans = 4096,\n\t\t.enabled_ports = 0x1f,\n\t\t.cpu_port = B53_CPU_PORT,\n\t\t.vta_regs = B53_VTA_REGS,\n\t\t.duplex_reg = B53_DUPLEX_STAT_GE,\n\t\t.jumbo_pm_reg = B53_JUMBO_PORT_MASK,\n\t\t.jumbo_size_reg = B53_JUMBO_MAX_SIZE,\n\t\t.sw_ops = &b53_switch_ops,\n\t},\n\t{\n\t\t.chip_id = BCM53128_DEVICE_ID,\n\t\t.dev_name = \"BCM53128\",\n\t\t.alias = \"bcm53128\",\n\t\t.vlans = 4096,\n\t\t.enabled_ports = 0x1ff,\n\t\t.cpu_port = B53_CPU_PORT,\n\t\t.vta_regs = B53_VTA_REGS,\n\t\t.duplex_reg = B53_DUPLEX_STAT_GE,\n\t\t.jumbo_pm_reg = B53_JUMBO_PORT_MASK,\n\t\t.jumbo_size_reg = B53_JUMBO_MAX_SIZE,\n\t\t.sw_ops = &b53_switch_ops,\n\t},\n\t{\n\t\t.chip_id = BCM63XX_DEVICE_ID,\n\t\t.dev_name = \"BCM63xx\",\n\t\t.alias = \"bcm63xx\",\n\t\t.vlans = 4096,\n\t\t.enabled_ports = 0, /* pdata must provide them */\n\t\t.cpu_port = B53_CPU_PORT,\n\t\t.vta_regs = B53_VTA_REGS_63XX,\n\t\t.duplex_reg = B53_DUPLEX_STAT_63XX,\n\t\t.jumbo_pm_reg = B53_JUMBO_PORT_MASK_63XX,\n\t\t.jumbo_size_reg = B53_JUMBO_MAX_SIZE_63XX,\n\t\t.sw_ops = &b53_switch_ops,\n\t},\n\t{\n\t\t.chip_id = BCM53010_DEVICE_ID,\n\t\t.dev_name = \"BCM53010\",\n\t\t.alias = \"bcm53011\",\n\t\t.vlans = 4096,\n\t\t.enabled_ports = 0x1f,\n\t\t.cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */\n\t\t.vta_regs = B53_VTA_REGS,\n\t\t.duplex_reg = B53_DUPLEX_STAT_GE,\n\t\t.jumbo_pm_reg = B53_JUMBO_PORT_MASK,\n\t\t.jumbo_size_reg = B53_JUMBO_MAX_SIZE,\n\t\t.sw_ops = &b53_switch_ops,\n\t},\n\t{\n\t\t.chip_id = BCM53011_DEVICE_ID,\n\t\t.dev_name = \"BCM53011\",\n\t\t.alias = \"bcm53011\",\n\t\t.vlans = 4096,\n\t\t.enabled_ports = 0x1bf,\n\t\t.cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */\n\t\t.vta_regs = B53_VTA_REGS,\n\t\t.duplex_reg = B53_DUPLEX_STAT_GE,\n\t\t.jumbo_pm_reg = B53_JUMBO_PORT_MASK,\n\t\t.jumbo_size_reg = B53_JUMBO_MAX_SIZE,\n\t\t.sw_ops = &b53_switch_ops,\n\t},\n\t{\n\t\t.chip_id = BCM53012_DEVICE_ID,\n\t\t.dev_name = \"BCM53012\",\n\t\t.alias = \"bcm53011\",\n\t\t.vlans = 4096,\n\t\t.enabled_ports = 0x1bf,\n\t\t.cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */\n\t\t.vta_regs = B53_VTA_REGS,\n\t\t.duplex_reg = B53_DUPLEX_STAT_GE,\n\t\t.jumbo_pm_reg = B53_JUMBO_PORT_MASK,\n\t\t.jumbo_size_reg = B53_JUMBO_MAX_SIZE,\n\t\t.sw_ops = &b53_switch_ops,\n\t},\n\t{\n\t\t.chip_id = BCM53018_DEVICE_ID,\n\t\t.dev_name = \"BCM53018\",\n\t\t.alias = \"bcm53018\",\n\t\t.vlans = 4096,\n\t\t.enabled_ports = 0x1f,\n\t\t.cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */\n\t\t.vta_regs = B53_VTA_REGS,\n\t\t.duplex_reg = B53_DUPLEX_STAT_GE,\n\t\t.jumbo_pm_reg = B53_JUMBO_PORT_MASK,\n\t\t.jumbo_size_reg = B53_JUMBO_MAX_SIZE,\n\t\t.sw_ops = &b53_switch_ops,\n\t},\n\t{\n\t\t.chip_id = BCM53019_DEVICE_ID,\n\t\t.dev_name = \"BCM53019\",\n\t\t.alias = \"bcm53019\",\n\t\t.vlans = 4096,\n\t\t.enabled_ports = 0x1f,\n\t\t.cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */\n\t\t.vta_regs = B53_VTA_REGS,\n\t\t.duplex_reg = B53_DUPLEX_STAT_GE,\n\t\t.jumbo_pm_reg = B53_JUMBO_PORT_MASK,\n\t\t.jumbo_size_reg = B53_JUMBO_MAX_SIZE,\n\t\t.sw_ops = &b53_switch_ops,\n\t},\n};\n\nstatic int b53_switch_init_of(struct b53_device *dev)\n{\n\tstruct device_node *dn, *pn;\n\tconst char *alias;\n\tu32 port_num;\n\tu16 ports = 0;\n\n\tdn = of_get_child_by_name(dev_of_node(dev->dev), \"ports\");\n\tif (!dn)\n\t\treturn -EINVAL;\n\n\tfor_each_available_child_of_node(dn, pn) {\n\t\tconst char *label;\n\t\tint len;\n\n\t\tif (of_property_read_u32(pn, \"reg\", &port_num))\n\t\t\tcontinue;\n\n\t\tif (port_num > B53_CPU_PORT)\n\t\t\tcontinue;\n\n\t\tports |= BIT(port_num);\n\n\t\tlabel = of_get_property(pn, \"label\", &len);\n\t\tif (label && !strcmp(label, \"cpu\"))\n\t\t\tdev->sw_dev.cpu_port = port_num;\n\t}\n\n\tdev->enabled_ports = ports;\n\n\tif (!of_property_read_string(dev_of_node(dev->dev), \"lede,alias\",\n\t\t\t\t\t\t &alias))\n\t\tdev->sw_dev.alias = devm_kstrdup(dev->dev, alias, GFP_KERNEL);\n\n\treturn 0;\n}\n\nstatic int b53_switch_init(struct b53_device *dev)\n{\n\tstruct switch_dev *sw_dev = &dev->sw_dev;\n\tunsigned i;\n\tint ret;\n\n\tfor (i = 0; i < ARRAY_SIZE(b53_switch_chips); i++) {\n\t\tconst struct b53_chip_data *chip = &b53_switch_chips[i];\n\n\t\tif (chip->chip_id == dev->chip_id) {\n\t\t\tsw_dev->name = chip->dev_name;\n\t\t\tif (!sw_dev->alias)\n\t\t\t\tsw_dev->alias = chip->alias;\n\t\t\tif (!dev->enabled_ports)\n\t\t\t\tdev->enabled_ports = chip->enabled_ports;\n\t\t\tdev->duplex_reg = chip->duplex_reg;\n\t\t\tdev->vta_regs[0] = chip->vta_regs[0];\n\t\t\tdev->vta_regs[1] = chip->vta_regs[1];\n\t\t\tdev->vta_regs[2] = chip->vta_regs[2];\n\t\t\tdev->jumbo_pm_reg = chip->jumbo_pm_reg;\n\t\t\tsw_dev->ops = chip->sw_ops;\n\t\t\tsw_dev->cpu_port = chip->cpu_port;\n\t\t\tsw_dev->vlans = chip->vlans;\n\t\t\tbreak;\n\t\t}\n\t}\n\n\tif (!sw_dev->name)\n\t\treturn -EINVAL;\n\n\t/* check which BCM5325x version we have */\n\tif (is5325(dev)) {\n\t\tu8 vc4;\n\n\t\tb53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4);\n\n\t\t/* check reserved bits */\n\t\tswitch (vc4 & 3) {\n\t\tcase 1:\n\t\t\t/* BCM5325E */\n\t\t\tbreak;\n\t\tcase 3:\n\t\t\t/* BCM5325F - do not use port 4 */\n\t\t\tdev->enabled_ports &= ~BIT(4);\n\t\t\tbreak;\n\t\tdefault:\n/* On the BCM47XX SoCs this is the supported internal switch.*/\n#ifndef CONFIG_BCM47XX\n\t\t\t/* BCM5325M */\n\t\t\treturn -EINVAL;\n#else\n\t\t\tbreak;\n#endif\n\t\t}\n\t} else if (dev->chip_id == BCM53115_DEVICE_ID) {\n\t\tu64 strap_value;\n\n\t\tb53_read48(dev, B53_STAT_PAGE, B53_STRAP_VALUE, &strap_value);\n\t\t/* use second IMP port if GMII is enabled */\n\t\tif (strap_value & SV_GMII_CTRL_115)\n\t\t\tsw_dev->cpu_port = 5;\n\t}\n\n\tif (dev_of_node(dev->dev)) {\n\t\tret = b53_switch_init_of(dev);\n\t\tif (ret)\n\t\t\treturn ret;\n\t}\n\n\tdev->enabled_ports |= BIT(sw_dev->cpu_port);\n\tsw_dev->ports = fls(dev->enabled_ports);\n\n\tdev->ports = devm_kzalloc(dev->dev,\n\t\t\t\t  sizeof(struct b53_port) * sw_dev->ports,\n\t\t\t\t  GFP_KERNEL);\n\tif (!dev->ports)\n\t\treturn -ENOMEM;\n\n\tdev->vlans = devm_kzalloc(dev->dev,\n\t\t\t\t  sizeof(struct b53_vlan) * sw_dev->vlans,\n\t\t\t\t  GFP_KERNEL);\n\tif (!dev->vlans)\n\t\treturn -ENOMEM;\n\n\tdev->buf = devm_kzalloc(dev->dev, B53_BUF_SIZE, GFP_KERNEL);\n\tif (!dev->buf)\n\t\treturn -ENOMEM;\n\n\tdev->reset_gpio = b53_switch_get_reset_gpio(dev);\n\tif (dev->reset_gpio >= 0) {\n\t\tret = devm_gpio_request_one(dev->dev, dev->reset_gpio,\n\t\t\t\t\t    GPIOF_OUT_INIT_HIGH, \"robo_reset\");\n\t\tif (ret)\n\t\t\treturn ret;\n\t}\n\n\treturn b53_switch_reset(dev);\n}\n\nstruct b53_device *b53_switch_alloc(struct device *base, struct b53_io_ops *ops,\n\t\t\t\t    void *priv)\n{\n\tstruct b53_device *dev;\n\n\tdev = devm_kzalloc(base, sizeof(*dev), GFP_KERNEL);\n\tif (!dev)\n\t\treturn NULL;\n\n\tdev->dev = base;\n\tdev->ops = ops;\n\tdev->priv = priv;\n\tmutex_init(&dev->reg_mutex);\n\n\treturn dev;\n}\nEXPORT_SYMBOL(b53_switch_alloc);\n\nint b53_switch_detect(struct b53_device *dev)\n{\n\tu32 id32;\n\tu16 tmp;\n\tu8 id8;\n\tint ret;\n\n\tret = b53_read8(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id8);\n\tif (ret)\n\t\treturn ret;\n\n\tswitch (id8) {\n\tcase 0:\n\t\t/*\n\t\t * BCM5325 and BCM5365 do not have this register so reads\n\t\t * return 0. But the read operation did succeed, so assume\n\t\t * this is one of them.\n\t\t *\n\t\t * Next check if we can write to the 5325's VTA register; for\n\t\t * 5365 it is read only.\n\t\t */\n\n\t\tb53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, 0xf);\n\t\tb53_read16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, &tmp);\n\n\t\tif (tmp == 0xf)\n\t\t\tdev->chip_id = BCM5325_DEVICE_ID;\n\t\telse\n\t\t\tdev->chip_id = BCM5365_DEVICE_ID;\n\t\tbreak;\n\tcase BCM5395_DEVICE_ID:\n\tcase BCM5397_DEVICE_ID:\n\tcase BCM5398_DEVICE_ID:\n\t\tdev->chip_id = id8;\n\t\tbreak;\n\tdefault:\n\t\tret = b53_read32(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id32);\n\t\tif (ret)\n\t\t\treturn ret;\n\n\t\tswitch (id32) {\n\t\tcase BCM53115_DEVICE_ID:\n\t\tcase BCM53125_DEVICE_ID:\n\t\tcase BCM53128_DEVICE_ID:\n\t\tcase BCM53010_DEVICE_ID:\n\t\tcase BCM53011_DEVICE_ID:\n\t\tcase BCM53012_DEVICE_ID:\n\t\tcase BCM53018_DEVICE_ID:\n\t\tcase BCM53019_DEVICE_ID:\n\t\t\tdev->chip_id = id32;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tpr_err(\"unsupported switch detected (BCM53%02x/BCM%x)\\n\",\n\t\t\t       id8, id32);\n\t\t\treturn -ENODEV;\n\t\t}\n\t}\n\n\tif (dev->chip_id == BCM5325_DEVICE_ID)\n\t\treturn b53_read8(dev, B53_STAT_PAGE, B53_REV_ID_25,\n\t\t\t\t &dev->core_rev);\n\telse\n\t\treturn b53_read8(dev, B53_MGMT_PAGE, B53_REV_ID,\n\t\t\t\t &dev->core_rev);\n}\nEXPORT_SYMBOL(b53_switch_detect);\n\nint b53_switch_register(struct b53_device *dev)\n{\n\tint ret;\n\n\tif (dev->pdata) {\n\t\tdev->chip_id = dev->pdata->chip_id;\n\t\tdev->enabled_ports = dev->pdata->enabled_ports;\n\t\tdev->sw_dev.alias = dev->pdata->alias;\n\t}\n\n\tif (!dev->chip_id && b53_switch_detect(dev))\n\t\treturn -EINVAL;\n\n\tret = b53_switch_init(dev);\n\tif (ret)\n\t\treturn ret;\n\n\tpr_info(\"found switch: %s, rev %i\\n\", dev->sw_dev.name, dev->core_rev);\n\n\treturn register_switch(&dev->sw_dev, NULL);\n}\nEXPORT_SYMBOL(b53_switch_register);\n\nMODULE_AUTHOR(\"Jonas Gorski <jogo@openwrt.org>\");\nMODULE_DESCRIPTION(\"B53 switch library\");\nMODULE_LICENSE(\"Dual BSD/GPL\");\n"
  },
  {
    "path": "target/linux/generic/files/drivers/net/phy/b53/b53_mdio.c",
    "content": "/*\n * B53 register access through MII registers\n *\n * Copyright (C) 2011-2013 Jonas Gorski <jogo@openwrt.org>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n */\n\n#include <linux/kernel.h>\n#include <linux/phy.h>\n#include <linux/module.h>\n\n#include \"b53_priv.h\"\n\n#define B53_PSEUDO_PHY\t0x1e /* Register Access Pseudo PHY */\n\n/* MII registers */\n#define REG_MII_PAGE    0x10    /* MII Page register */\n#define REG_MII_ADDR    0x11    /* MII Address register */\n#define REG_MII_DATA0   0x18    /* MII Data register 0 */\n#define REG_MII_DATA1   0x19    /* MII Data register 1 */\n#define REG_MII_DATA2   0x1a    /* MII Data register 2 */\n#define REG_MII_DATA3   0x1b    /* MII Data register 3 */\n\n#define REG_MII_PAGE_ENABLE     BIT(0)\n#define REG_MII_ADDR_WRITE      BIT(0)\n#define REG_MII_ADDR_READ       BIT(1)\n\nstatic int b53_mdio_op(struct b53_device *dev, u8 page, u8 reg, u16 op)\n{\n\tint i;\n\tu16 v;\n\tint ret;\n\tstruct mii_bus *bus = dev->priv;\n\n\tif (dev->current_page != page) {\n\t\t/* set page number */\n\t\tv = (page << 8) | REG_MII_PAGE_ENABLE;\n\t\tret = mdiobus_write(bus, B53_PSEUDO_PHY, REG_MII_PAGE, v);\n\t\tif (ret)\n\t\t\treturn ret;\n\t\tdev->current_page = page;\n\t}\n\n\t/* set register address */\n\tv = (reg << 8) | op;\n\tret = mdiobus_write(bus, B53_PSEUDO_PHY, REG_MII_ADDR, v);\n\tif (ret)\n\t\treturn ret;\n\n\t/* check if operation completed */\n\tfor (i = 0; i < 5; ++i) {\n\t\tv = mdiobus_read(bus, B53_PSEUDO_PHY, REG_MII_ADDR);\n\t\tif (!(v & (REG_MII_ADDR_WRITE | REG_MII_ADDR_READ)))\n\t\t\tbreak;\n\t\tusleep_range(10, 100);\n\t}\n\n\tif (WARN_ON(i == 5))\n\t\treturn -EIO;\n\n\treturn 0;\n}\n\nstatic int b53_mdio_read8(struct b53_device *dev, u8 page, u8 reg, u8 *val)\n{\n\tstruct mii_bus *bus = dev->priv;\n\tint ret;\n\n\tret = b53_mdio_op(dev, page, reg, REG_MII_ADDR_READ);\n\tif (ret)\n\t\treturn ret;\n\n\t*val = mdiobus_read(bus, B53_PSEUDO_PHY, REG_MII_DATA0) & 0xff;\n\n\treturn 0;\n}\n\nstatic int b53_mdio_read16(struct b53_device *dev, u8 page, u8 reg, u16 *val)\n{\n\tstruct mii_bus *bus = dev->priv;\n\tint ret;\n\n\tret = b53_mdio_op(dev, page, reg, REG_MII_ADDR_READ);\n\tif (ret)\n\t\treturn ret;\n\n\t*val = mdiobus_read(bus, B53_PSEUDO_PHY, REG_MII_DATA0);\n\n\treturn 0;\n}\n\nstatic int b53_mdio_read32(struct b53_device *dev, u8 page, u8 reg, u32 *val)\n{\n\tstruct mii_bus *bus = dev->priv;\n\tint ret;\n\n\tret = b53_mdio_op(dev, page, reg, REG_MII_ADDR_READ);\n\tif (ret)\n\t\treturn ret;\n\n\t*val = mdiobus_read(bus, B53_PSEUDO_PHY, REG_MII_DATA0);\n\t*val |= mdiobus_read(bus, B53_PSEUDO_PHY, REG_MII_DATA1) << 16;\n\n\treturn 0;\n}\n\nstatic int b53_mdio_read48(struct b53_device *dev, u8 page, u8 reg, u64 *val)\n{\n\tstruct mii_bus *bus = dev->priv;\n\tu64 temp = 0;\n\tint i;\n\tint ret;\n\n\tret = b53_mdio_op(dev, page, reg, REG_MII_ADDR_READ);\n\tif (ret)\n\t\treturn ret;\n\n\tfor (i = 2; i >= 0; i--) {\n\t\ttemp <<= 16;\n\t\ttemp |= mdiobus_read(bus, B53_PSEUDO_PHY, REG_MII_DATA0 + i);\n\t}\n\n\t*val = temp;\n\n\treturn 0;\n}\n\nstatic int b53_mdio_read64(struct b53_device *dev, u8 page, u8 reg, u64 *val)\n{\n\tstruct mii_bus *bus = dev->priv;\n\tu64 temp = 0;\n\tint i;\n\tint ret;\n\n\tret = b53_mdio_op(dev, page, reg, REG_MII_ADDR_READ);\n\tif (ret)\n\t\treturn ret;\n\n\tfor (i = 3; i >= 0; i--) {\n\t\ttemp <<= 16;\n\t\ttemp |= mdiobus_read(bus, B53_PSEUDO_PHY, REG_MII_DATA0 + i);\n\t}\n\n\t*val = temp;\n\n\treturn 0;\n}\n\nstatic int b53_mdio_write8(struct b53_device *dev, u8 page, u8 reg, u8 value)\n{\n\tstruct mii_bus *bus = dev->priv;\n\tint ret;\n\n\tret = mdiobus_write(bus, B53_PSEUDO_PHY, REG_MII_DATA0, value);\n\tif (ret)\n\t\treturn ret;\n\n\treturn b53_mdio_op(dev, page, reg, REG_MII_ADDR_WRITE);\n}\n\nstatic int b53_mdio_write16(struct b53_device *dev, u8 page, u8 reg,\n\t\t\t     u16 value)\n{\n\tstruct mii_bus *bus = dev->priv;\n\tint ret;\n\n\tret = mdiobus_write(bus, B53_PSEUDO_PHY, REG_MII_DATA0, value);\n\tif (ret)\n\t\treturn ret;\n\n\treturn b53_mdio_op(dev, page, reg, REG_MII_ADDR_WRITE);\n}\n\nstatic int b53_mdio_write32(struct b53_device *dev, u8 page, u8 reg,\n\t\t\t\t    u32 value)\n{\n\tstruct mii_bus *bus = dev->priv;\n\tunsigned int i;\n\tu32 temp = value;\n\n\tfor (i = 0; i < 2; i++) {\n\t\tint ret = mdiobus_write(bus, B53_PSEUDO_PHY, REG_MII_DATA0 + i,\n\t\t\t\t    temp & 0xffff);\n\t\tif (ret)\n\t\t\treturn ret;\n\t\ttemp >>= 16;\n\t}\n\n\treturn b53_mdio_op(dev, page, reg, REG_MII_ADDR_WRITE);\n\n}\n\nstatic int b53_mdio_write48(struct b53_device *dev, u8 page, u8 reg,\n\t\t\t\t    u64 value)\n{\n\tstruct mii_bus *bus = dev->priv;\n\tunsigned i;\n\tu64 temp = value;\n\n\tfor (i = 0; i < 3; i++) {\n\t\tint ret = mdiobus_write(bus, B53_PSEUDO_PHY, REG_MII_DATA0 + i,\n\t\t\t\t    temp & 0xffff);\n\t\tif (ret)\n\t\t\treturn ret;\n\t\ttemp >>= 16;\n\t}\n\n\treturn b53_mdio_op(dev, page, reg, REG_MII_ADDR_WRITE);\n\n}\n\nstatic int b53_mdio_write64(struct b53_device *dev, u8 page, u8 reg,\n\t\t\t     u64 value)\n{\n\tstruct mii_bus *bus = dev->priv;\n\tunsigned i;\n\tu64 temp = value;\n\n\tfor (i = 0; i < 4; i++) {\n\t\tint ret = mdiobus_write(bus, B53_PSEUDO_PHY, REG_MII_DATA0 + i,\n\t\t\t\t    temp & 0xffff);\n\t\tif (ret)\n\t\t\treturn ret;\n\t\ttemp >>= 16;\n\t}\n\n\treturn b53_mdio_op(dev, page, reg, REG_MII_ADDR_WRITE);\n}\n\nstatic int b53_mdio_phy_read16(struct b53_device *dev, int addr, u8 reg,\n\t\t\t       u16 *value)\n{\n\tstruct mii_bus *bus = dev->priv;\n\n\t*value = mdiobus_read(bus, addr, reg);\n\n\treturn 0;\n}\n\nstatic int b53_mdio_phy_write16(struct b53_device *dev, int addr, u8 reg,\n\t\t\t\tu16 value)\n{\n\tstruct mii_bus *bus = dev->priv;\n\n\treturn mdiobus_write(bus, addr, reg, value);\n}\n\nstatic struct b53_io_ops b53_mdio_ops = {\n\t.read8 = b53_mdio_read8,\n\t.read16 = b53_mdio_read16,\n\t.read32 = b53_mdio_read32,\n\t.read48 = b53_mdio_read48,\n\t.read64 = b53_mdio_read64,\n\t.write8 = b53_mdio_write8,\n\t.write16 = b53_mdio_write16,\n\t.write32 = b53_mdio_write32,\n\t.write48 = b53_mdio_write48,\n\t.write64 = b53_mdio_write64,\n\t.phy_read16 = b53_mdio_phy_read16,\n\t.phy_write16 = b53_mdio_phy_write16,\n};\n\nstatic int b53_phy_probe(struct phy_device *phydev)\n{\n\tstruct b53_device *dev;\n\tint ret;\n\n\t/* allow the generic phy driver to take over */\n\tif (phydev->mdio.addr != B53_PSEUDO_PHY && phydev->mdio.addr != 0)\n\t\treturn -ENODEV;\n\n\tdev = b53_switch_alloc(&phydev->mdio.dev, &b53_mdio_ops, phydev->mdio.bus);\n\tif (!dev)\n\t\treturn -ENOMEM;\n\n\tdev->current_page = 0xff;\n\tdev->priv = phydev->mdio.bus;\n\tdev->ops = &b53_mdio_ops;\n\tdev->pdata = NULL;\n\tmutex_init(&dev->reg_mutex);\n\n\tret = b53_switch_detect(dev);\n\tif (ret)\n\t\treturn ret;\n\n\tlinkmode_zero(phydev->supported);\n\tif (is5325(dev) || is5365(dev))\n\t\tlinkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, phydev->supported);\n\telse\n\t\tlinkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, phydev->supported);\n\n\tlinkmode_copy(phydev->advertising, phydev->supported);\n\n\tret = b53_switch_register(dev);\n\tif (ret) {\n\t\tdev_err(dev->dev, \"failed to register switch: %i\\n\", ret);\n\t\treturn ret;\n\t}\n\n\tphydev->priv = dev;\n\n\treturn 0;\n}\n\nstatic int b53_phy_config_init(struct phy_device *phydev)\n{\n\tstruct b53_device *dev = phydev->priv;\n\n\t/* we don't use page 0xff, so force a page set */\n\tdev->current_page = 0xff;\n\t/* force the ethX as alias */\n\tdev->sw_dev.alias = phydev->attached_dev->name;\n\n\treturn 0;\n}\n\nstatic void b53_phy_remove(struct phy_device *phydev)\n{\n\tstruct b53_device *priv = phydev->priv;\n\n\tif (!priv)\n\t\treturn;\n\n\tb53_switch_remove(priv);\n\n\tphydev->priv = NULL;\n}\n\nstatic int b53_phy_config_aneg(struct phy_device *phydev)\n{\n\treturn 0;\n}\n\nstatic int b53_phy_read_status(struct phy_device *phydev)\n{\n\tstruct b53_device *priv = phydev->priv;\n\n\tif (is5325(priv) || is5365(priv))\n\t\tphydev->speed = 100;\n\telse\n\t\tphydev->speed = 1000;\n\n\tphydev->duplex = DUPLEX_FULL;\n\tphydev->link = 1;\n\tphydev->state = PHY_RUNNING;\n\n\tnetif_carrier_on(phydev->attached_dev);\n\tphydev->adjust_link(phydev->attached_dev);\n\n\treturn 0;\n}\n\n/* BCM5325, BCM539x */\nstatic struct phy_driver b53_phy_driver_id1 = {\n\t.phy_id\t\t= 0x0143bc00,\n\t.name\t\t= \"Broadcom B53 (1)\",\n\t.phy_id_mask\t= 0x1ffffc00,\n\t.features\t= 0,\n\t.probe\t\t= b53_phy_probe,\n\t.remove\t\t= b53_phy_remove,\n\t.config_aneg\t= b53_phy_config_aneg,\n\t.config_init\t= b53_phy_config_init,\n\t.read_status\t= b53_phy_read_status,\n};\n\n/* BCM53125, BCM53128 */\nstatic struct phy_driver b53_phy_driver_id2 = {\n\t.phy_id\t\t= 0x03625c00,\n\t.name\t\t= \"Broadcom B53 (2)\",\n\t.phy_id_mask\t= 0x1ffffc00,\n\t.features\t= 0,\n\t.probe\t\t= b53_phy_probe,\n\t.remove\t\t= b53_phy_remove,\n\t.config_aneg\t= b53_phy_config_aneg,\n\t.config_init\t= b53_phy_config_init,\n\t.read_status\t= b53_phy_read_status,\n};\n\n/* BCM5365 */\nstatic struct phy_driver b53_phy_driver_id3 = {\n\t.phy_id\t\t= 0x00406300,\n\t.name\t\t= \"Broadcom B53 (3)\",\n\t.phy_id_mask\t= 0x1fffff00,\n\t.features\t= 0,\n\t.probe\t\t= b53_phy_probe,\n\t.remove\t\t= b53_phy_remove,\n\t.config_aneg\t= b53_phy_config_aneg,\n\t.config_init\t= b53_phy_config_init,\n\t.read_status\t= b53_phy_read_status,\n};\n\nint __init b53_phy_driver_register(void)\n{\n\tint ret;\n\n\tret = phy_driver_register(&b53_phy_driver_id1, THIS_MODULE);\n\tif (ret)\n\t\treturn ret;\n\n\tret = phy_driver_register(&b53_phy_driver_id2, THIS_MODULE);\n\tif (ret)\n\t\tgoto err1;\n\n\tret = phy_driver_register(&b53_phy_driver_id3, THIS_MODULE);\n\tif (!ret)\n\t\treturn 0;\n\n\tphy_driver_unregister(&b53_phy_driver_id2);\nerr1:\n\tphy_driver_unregister(&b53_phy_driver_id1);\n\treturn ret;\n}\n\nvoid __exit b53_phy_driver_unregister(void)\n{\n\tphy_driver_unregister(&b53_phy_driver_id3);\n\tphy_driver_unregister(&b53_phy_driver_id2);\n\tphy_driver_unregister(&b53_phy_driver_id1);\n}\n\nmodule_init(b53_phy_driver_register);\nmodule_exit(b53_phy_driver_unregister);\n\nMODULE_DESCRIPTION(\"B53 MDIO access driver\");\nMODULE_LICENSE(\"Dual BSD/GPL\");\n"
  },
  {
    "path": "target/linux/generic/files/drivers/net/phy/b53/b53_mmap.c",
    "content": "/*\n * B53 register access through memory mapped registers\n *\n * Copyright (C) 2012-2013 Jonas Gorski <jogo@openwrt.org>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n */\n\n#include <linux/kernel.h>\n#include <linux/module.h>\n#include <linux/platform_device.h>\n#include <linux/platform_data/b53.h>\n\n#include \"b53_priv.h\"\n\nstatic int b53_mmap_read8(struct b53_device *dev, u8 page, u8 reg, u8 *val)\n{\n\tu8 __iomem *regs = dev->priv;\n\n\t*val = readb(regs + (page << 8) + reg);\n\n\treturn 0;\n}\n\nstatic int b53_mmap_read16(struct b53_device *dev, u8 page, u8 reg, u16 *val)\n{\n\tu8 __iomem *regs = dev->priv;\n\n\tif (WARN_ON(reg % 2))\n\t\treturn -EINVAL;\n\n\tif (dev->pdata && dev->pdata->big_endian)\n\t\t*val = readw_be(regs + (page << 8) + reg);\n\telse\n\t\t*val = readw(regs + (page << 8) + reg);\n\n\treturn 0;\n}\n\nstatic int b53_mmap_read32(struct b53_device *dev, u8 page, u8 reg, u32 *val)\n{\n\tu8 __iomem *regs = dev->priv;\n\n\tif (WARN_ON(reg % 4))\n\t\treturn -EINVAL;\n\n\tif (dev->pdata && dev->pdata->big_endian)\n\t\t*val = readl_be(regs + (page << 8) + reg);\n\telse\n\t\t*val = readl(regs + (page << 8) + reg);\n\n\treturn 0;\n}\n\nstatic int b53_mmap_read48(struct b53_device *dev, u8 page, u8 reg, u64 *val)\n{\n\tif (WARN_ON(reg % 2))\n\t\treturn -EINVAL;\n\n\tif (reg % 4) {\n\t\tu16 lo;\n\t\tu32 hi;\n\n\t\tb53_mmap_read16(dev, page, reg, &lo);\n\t\tb53_mmap_read32(dev, page, reg + 2, &hi);\n\n\t\t*val = ((u64)hi << 16) | lo;\n\t} else {\n\t\tu32 lo;\n\t\tu16 hi;\n\n\t\tb53_mmap_read32(dev, page, reg, &lo);\n\t\tb53_mmap_read16(dev, page, reg + 4, &hi);\n\n\t\t*val = ((u64)hi << 32) | lo;\n\t}\n\n\treturn 0;\n}\n\nstatic int b53_mmap_read64(struct b53_device *dev, u8 page, u8 reg, u64 *val)\n{\n\tu32 hi, lo;\n\n\tif (WARN_ON(reg % 4))\n\t\treturn -EINVAL;\n\n\tb53_mmap_read32(dev, page, reg, &lo);\n\tb53_mmap_read32(dev, page, reg + 4, &hi);\n\n\t*val = ((u64)hi << 32) | lo;\n\n\treturn 0;\n}\n\nstatic int b53_mmap_write8(struct b53_device *dev, u8 page, u8 reg, u8 value)\n{\n\tu8 __iomem *regs = dev->priv;\n\n\twriteb(value, regs + (page << 8) + reg);\n\n\treturn 0;\n}\n\nstatic int b53_mmap_write16(struct b53_device *dev, u8 page, u8 reg,\n\t\t\t     u16 value)\n{\n\tu8 __iomem *regs = dev->priv;\n\n\tif (WARN_ON(reg % 2))\n\t\treturn -EINVAL;\n\n\tif (dev->pdata && dev->pdata->big_endian)\n\t\twritew_be(value, regs + (page << 8) + reg);\n\telse\n\t\twritew(value, regs + (page << 8) + reg);\n\n\treturn 0;\n}\n\nstatic int b53_mmap_write32(struct b53_device *dev, u8 page, u8 reg,\n\t\t\t\t    u32 value)\n{\n\tu8 __iomem *regs = dev->priv;\n\n\tif (WARN_ON(reg % 4))\n\t\treturn -EINVAL;\n\n\tif (dev->pdata && dev->pdata->big_endian)\n\t\twritel_be(value, regs + (page << 8) + reg);\n\telse\n\t\twritel(value, regs + (page << 8) + reg);\n\n\treturn 0;\n}\n\nstatic int b53_mmap_write48(struct b53_device *dev, u8 page, u8 reg,\n\t\t\t\t    u64 value)\n{\n\tif (WARN_ON(reg % 2))\n\t\treturn -EINVAL;\n\n\tif (reg % 4) {\n\t\tu32 hi = (u32)(value >> 16);\n\t\tu16 lo = (u16)value;\n\n\t\tb53_mmap_write16(dev, page, reg, lo);\n\t\tb53_mmap_write32(dev, page, reg + 2, hi);\n\t} else {\n\t\tu16 hi = (u16)(value >> 32);\n\t\tu32 lo = (u32)value;\n\n\t\tb53_mmap_write32(dev, page, reg, lo);\n\t\tb53_mmap_write16(dev, page, reg + 4, hi);\n\t}\n\n\treturn 0;\n}\n\nstatic int b53_mmap_write64(struct b53_device *dev, u8 page, u8 reg,\n\t\t\t     u64 value)\n{\n\tu32 hi, lo;\n\n\thi = (u32)(value >> 32);\n\tlo = (u32)value;\n\n\tif (WARN_ON(reg % 4))\n\t\treturn -EINVAL;\n\n\tb53_mmap_write32(dev, page, reg, lo);\n\tb53_mmap_write32(dev, page, reg + 4, hi);\n\n\treturn 0;\n}\n\nstatic struct b53_io_ops b53_mmap_ops = {\n\t.read8 = b53_mmap_read8,\n\t.read16 = b53_mmap_read16,\n\t.read32 = b53_mmap_read32,\n\t.read48 = b53_mmap_read48,\n\t.read64 = b53_mmap_read64,\n\t.write8 = b53_mmap_write8,\n\t.write16 = b53_mmap_write16,\n\t.write32 = b53_mmap_write32,\n\t.write48 = b53_mmap_write48,\n\t.write64 = b53_mmap_write64,\n};\n\nstatic int b53_mmap_probe(struct platform_device *pdev)\n{\n\tstruct b53_platform_data *pdata = pdev->dev.platform_data;\n\tstruct b53_device *dev;\n\n\tif (!pdata)\n\t\treturn -EINVAL;\n\n\tdev = b53_switch_alloc(&pdev->dev, &b53_mmap_ops, pdata->regs);\n\tif (!dev)\n\t\treturn -ENOMEM;\n\n\tif (pdata)\n\t\tdev->pdata = pdata;\n\n\tplatform_set_drvdata(pdev, dev);\n\n\treturn b53_switch_register(dev);\n}\n\nstatic int b53_mmap_remove(struct platform_device *pdev)\n{\n\tstruct b53_device *dev = platform_get_drvdata(pdev);\n\n\tif (dev)\n\t\tb53_switch_remove(dev);\n\n\treturn 0;\n}\n\nstatic struct platform_driver b53_mmap_driver = {\n\t.probe = b53_mmap_probe,\n\t.remove = b53_mmap_remove,\n\t.driver = {\n\t\t.name = \"b53-switch\",\n\t},\n};\n\nmodule_platform_driver(b53_mmap_driver);\nMODULE_AUTHOR(\"Jonas Gorski <jogo@openwrt.org>\");\nMODULE_DESCRIPTION(\"B53 MMAP access driver\");\nMODULE_LICENSE(\"Dual BSD/GPL\");\n"
  },
  {
    "path": "target/linux/generic/files/drivers/net/phy/b53/b53_phy_fixup.c",
    "content": "/*\n * B53 PHY Fixup call\n *\n * Copyright (C) 2013 Jonas Gorski <jogo@openwrt.org>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n */\n\n#include <linux/init.h>\n#include <linux/kernel.h>\n#include <linux/phy.h>\n\n#define B53_PSEUDO_PHY\t0x1e /* Register Access Pseudo PHY */\n\n#define B53_BRCM_OUI_1\t0x0143bc00\n#define B53_BRCM_OUI_2\t0x03625c00\n#define B53_BRCM_OUI_3\t0x00406300\n\nstatic int b53_phy_fixup(struct phy_device *dev)\n{\n\tstruct mii_bus *bus = dev->mdio.bus;\n\tu32 phy_id;\n\n\tif (dev->mdio.addr != B53_PSEUDO_PHY)\n\t\treturn 0;\n\n\t/* read the first port's id */\n\tphy_id = mdiobus_read(bus, 0, 2) << 16;\n\tphy_id |= mdiobus_read(bus, 0, 3);\n\n\tif ((phy_id & 0xfffffc00) == B53_BRCM_OUI_1 ||\n\t    (phy_id & 0xfffffc00) == B53_BRCM_OUI_2 ||\n\t    (phy_id & 0xffffff00) == B53_BRCM_OUI_3) {\n\t\tdev->phy_id = phy_id;\n\t}\n\n\treturn 0;\n}\n\nint __init b53_phy_fixup_register(void)\n{\n\treturn phy_register_fixup_for_id(PHY_ANY_ID, b53_phy_fixup);\n}\n\nsubsys_initcall(b53_phy_fixup_register);\n"
  },
  {
    "path": "target/linux/generic/files/drivers/net/phy/b53/b53_priv.h",
    "content": "/*\n * B53 common definitions\n *\n * Copyright (C) 2011-2013 Jonas Gorski <jogo@openwrt.org>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n */\n\n#ifndef __B53_PRIV_H\n#define __B53_PRIV_H\n\n#include <linux/kernel.h>\n#include <linux/mutex.h>\n#include <linux/switch.h>\n\nstruct b53_device;\n\nstruct b53_io_ops {\n\tint (*read8)(struct b53_device *dev, u8 page, u8 reg, u8 *value);\n\tint (*read16)(struct b53_device *dev, u8 page, u8 reg, u16 *value);\n\tint (*read32)(struct b53_device *dev, u8 page, u8 reg, u32 *value);\n\tint (*read48)(struct b53_device *dev, u8 page, u8 reg, u64 *value);\n\tint (*read64)(struct b53_device *dev, u8 page, u8 reg, u64 *value);\n\tint (*write8)(struct b53_device *dev, u8 page, u8 reg, u8 value);\n\tint (*write16)(struct b53_device *dev, u8 page, u8 reg, u16 value);\n\tint (*write32)(struct b53_device *dev, u8 page, u8 reg, u32 value);\n\tint (*write48)(struct b53_device *dev, u8 page, u8 reg, u64 value);\n\tint (*write64)(struct b53_device *dev, u8 page, u8 reg, u64 value);\n\tint (*phy_read16)(struct b53_device *dev, int addr, u8 reg, u16 *value);\n\tint (*phy_write16)(struct b53_device *dev, int addr, u8 reg, u16 value);\n};\n\nenum {\n\tBCM5325_DEVICE_ID = 0x25,\n\tBCM5365_DEVICE_ID = 0x65,\n\tBCM5395_DEVICE_ID = 0x95,\n\tBCM5397_DEVICE_ID = 0x97,\n\tBCM5398_DEVICE_ID = 0x98,\n\tBCM53115_DEVICE_ID = 0x53115,\n\tBCM53125_DEVICE_ID = 0x53125,\n\tBCM53128_DEVICE_ID = 0x53128,\n\tBCM63XX_DEVICE_ID = 0x6300,\n\tBCM53010_DEVICE_ID = 0x53010,\n\tBCM53011_DEVICE_ID = 0x53011,\n\tBCM53012_DEVICE_ID = 0x53012,\n\tBCM53018_DEVICE_ID = 0x53018,\n\tBCM53019_DEVICE_ID = 0x53019,\n};\n\n#define B53_N_PORTS\t9\n#define B53_N_PORTS_25\t6\n\nstruct b53_vlan {\n\tunsigned int\tmembers:B53_N_PORTS;\n\tunsigned int\tuntag:B53_N_PORTS;\n};\n\nstruct b53_port {\n\tunsigned int\tpvid:12;\n};\n\nstruct b53_device {\n\tstruct switch_dev sw_dev;\n\tstruct b53_platform_data *pdata;\n\n\tstruct mutex reg_mutex;\n\tconst struct b53_io_ops *ops;\n\n\t/* chip specific data */\n\tu32 chip_id;\n\tu8 core_rev;\n\tu8 vta_regs[3];\n\tu8 duplex_reg;\n\tu8 jumbo_pm_reg;\n\tu8 jumbo_size_reg;\n\tint reset_gpio;\n\n\t/* used ports mask */\n\tu16 enabled_ports;\n\n\t/* connect specific data */\n\tu8 current_page;\n\tstruct device *dev;\n\tvoid *priv;\n\n\t/* run time configuration */\n\tunsigned enable_vlan:1;\n\tunsigned enable_jumbo:1;\n\tunsigned allow_vid_4095:1;\n\n\tstruct b53_port *ports;\n\tstruct b53_vlan *vlans;\n\n\tchar *buf;\n};\n\n#define b53_for_each_port(dev, i) \\\n\tfor (i = 0; i < B53_N_PORTS; i++) \\\n\t\tif (dev->enabled_ports & BIT(i))\n\n\n\nstatic inline int is5325(struct b53_device *dev)\n{\n\treturn dev->chip_id == BCM5325_DEVICE_ID;\n}\n\nstatic inline int is5365(struct b53_device *dev)\n{\n#ifdef CONFIG_BCM47XX\n\treturn dev->chip_id == BCM5365_DEVICE_ID;\n#else\n\treturn 0;\n#endif\n}\n\nstatic inline int is5397_98(struct b53_device *dev)\n{\n\treturn dev->chip_id == BCM5397_DEVICE_ID ||\n\t\tdev->chip_id == BCM5398_DEVICE_ID;\n}\n\nstatic inline int is539x(struct b53_device *dev)\n{\n\treturn dev->chip_id == BCM5395_DEVICE_ID ||\n\t\tdev->chip_id == BCM5397_DEVICE_ID ||\n\t\tdev->chip_id == BCM5398_DEVICE_ID;\n}\n\nstatic inline int is531x5(struct b53_device *dev)\n{\n\treturn dev->chip_id == BCM53115_DEVICE_ID ||\n\t\tdev->chip_id == BCM53125_DEVICE_ID ||\n\t\tdev->chip_id == BCM53128_DEVICE_ID;\n}\n\nstatic inline int is63xx(struct b53_device *dev)\n{\n#ifdef CONFIG_BCM63XX\n\treturn dev->chip_id == BCM63XX_DEVICE_ID;\n#else\n\treturn 0;\n#endif\n}\n\nstatic inline int is5301x(struct b53_device *dev)\n{\n\treturn dev->chip_id == BCM53010_DEVICE_ID ||\n\t\tdev->chip_id == BCM53011_DEVICE_ID ||\n\t\tdev->chip_id == BCM53012_DEVICE_ID ||\n\t\tdev->chip_id == BCM53018_DEVICE_ID ||\n\t\tdev->chip_id == BCM53019_DEVICE_ID;\n}\n\n#define B53_CPU_PORT_25\t5\n#define B53_CPU_PORT\t8\n\nstatic inline int is_cpu_port(struct b53_device *dev, int port)\n{\n\treturn dev->sw_dev.cpu_port == port;\n}\n\nstatic inline int is_imp_port(struct b53_device *dev, int port)\n{\n\tif (is5325(dev) || is5365(dev))\n\t\treturn port == B53_CPU_PORT_25;\n\telse\n\t\treturn port == B53_CPU_PORT;\n}\n\nstatic inline struct b53_device *sw_to_b53(struct switch_dev *sw)\n{\n\treturn container_of(sw, struct b53_device, sw_dev);\n}\n\nstruct b53_device *b53_switch_alloc(struct device *base, struct b53_io_ops *ops,\n\t\t\t\t    void *priv);\n\nint b53_switch_detect(struct b53_device *dev);\n\nint b53_switch_register(struct b53_device *dev);\n\nstatic inline void b53_switch_remove(struct b53_device *dev)\n{\n\tunregister_switch(&dev->sw_dev);\n}\n\nstatic inline int b53_read8(struct b53_device *dev, u8 page, u8 reg, u8 *val)\n{\n\tint ret;\n\n\tmutex_lock(&dev->reg_mutex);\n\tret = dev->ops->read8(dev, page, reg, val);\n\tmutex_unlock(&dev->reg_mutex);\n\n\treturn ret;\n}\n\nstatic inline int b53_read16(struct b53_device *dev, u8 page, u8 reg, u16 *val)\n{\n\tint ret;\n\n\tmutex_lock(&dev->reg_mutex);\n\tret = dev->ops->read16(dev, page, reg, val);\n\tmutex_unlock(&dev->reg_mutex);\n\n\treturn ret;\n}\n\nstatic inline int b53_read32(struct b53_device *dev, u8 page, u8 reg, u32 *val)\n{\n\tint ret;\n\n\tmutex_lock(&dev->reg_mutex);\n\tret = dev->ops->read32(dev, page, reg, val);\n\tmutex_unlock(&dev->reg_mutex);\n\n\treturn ret;\n}\n\nstatic inline int b53_read48(struct b53_device *dev, u8 page, u8 reg, u64 *val)\n{\n\tint ret;\n\n\tmutex_lock(&dev->reg_mutex);\n\tret = dev->ops->read48(dev, page, reg, val);\n\tmutex_unlock(&dev->reg_mutex);\n\n\treturn ret;\n}\n\nstatic inline int b53_read64(struct b53_device *dev, u8 page, u8 reg, u64 *val)\n{\n\tint ret;\n\n\tmutex_lock(&dev->reg_mutex);\n\tret = dev->ops->read64(dev, page, reg, val);\n\tmutex_unlock(&dev->reg_mutex);\n\n\treturn ret;\n}\n\nstatic inline int b53_write8(struct b53_device *dev, u8 page, u8 reg, u8 value)\n{\n\tint ret;\n\n\tmutex_lock(&dev->reg_mutex);\n\tret = dev->ops->write8(dev, page, reg, value);\n\tmutex_unlock(&dev->reg_mutex);\n\n\treturn ret;\n}\n\nstatic inline int b53_write16(struct b53_device *dev, u8 page, u8 reg,\n\t\t\t      u16 value)\n{\n\tint ret;\n\n\tmutex_lock(&dev->reg_mutex);\n\tret = dev->ops->write16(dev, page, reg, value);\n\tmutex_unlock(&dev->reg_mutex);\n\n\treturn ret;\n}\n\nstatic inline int b53_write32(struct b53_device *dev, u8 page, u8 reg,\n\t\t\t      u32 value)\n{\n\tint ret;\n\n\tmutex_lock(&dev->reg_mutex);\n\tret = dev->ops->write32(dev, page, reg, value);\n\tmutex_unlock(&dev->reg_mutex);\n\n\treturn ret;\n}\n\nstatic inline int b53_write48(struct b53_device *dev, u8 page, u8 reg,\n\t\t\t      u64 value)\n{\n\tint ret;\n\n\tmutex_lock(&dev->reg_mutex);\n\tret = dev->ops->write48(dev, page, reg, value);\n\tmutex_unlock(&dev->reg_mutex);\n\n\treturn ret;\n}\n\nstatic inline int b53_write64(struct b53_device *dev, u8 page, u8 reg,\n\t\t\t       u64 value)\n{\n\tint ret;\n\n\tmutex_lock(&dev->reg_mutex);\n\tret = dev->ops->write64(dev, page, reg, value);\n\tmutex_unlock(&dev->reg_mutex);\n\n\treturn ret;\n}\n\n#ifdef CONFIG_BCM47XX\n#include <bcm47xx_board.h>\n#endif\n\n#include <linux/version.h>\n#include <linux/bcm47xx_nvram.h>\n\nstatic inline int b53_switch_get_reset_gpio(struct b53_device *dev)\n{\n#ifdef CONFIG_BCM47XX\n\tenum bcm47xx_board board = bcm47xx_board_get();\n\n\tswitch (board) {\n\tcase BCM47XX_BOARD_LINKSYS_WRT300NV11:\n\tcase BCM47XX_BOARD_LINKSYS_WRT310NV1:\n\t\treturn 8;\n\tdefault:\n\t\tbreak;\n\t}\n#endif\n\n\treturn bcm47xx_nvram_gpio_pin(\"robo_reset\");\n}\n\n#endif\n"
  },
  {
    "path": "target/linux/generic/files/drivers/net/phy/b53/b53_regs.h",
    "content": "/*\n * B53 register definitions\n *\n * Copyright (C) 2004 Broadcom Corporation\n * Copyright (C) 2011-2013 Jonas Gorski <jogo@openwrt.org>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n */\n\n#ifndef __B53_REGS_H\n#define __B53_REGS_H\n\n/* Management Port (SMP) Page offsets */\n#define B53_CTRL_PAGE\t\t\t0x00 /* Control */\n#define B53_STAT_PAGE\t\t\t0x01 /* Status */\n#define B53_MGMT_PAGE\t\t\t0x02 /* Management Mode */\n#define B53_MIB_AC_PAGE\t\t\t0x03 /* MIB Autocast */\n#define B53_ARLCTRL_PAGE\t\t0x04 /* ARL Control */\n#define B53_ARLIO_PAGE\t\t\t0x05 /* ARL Access */\n#define B53_FRAMEBUF_PAGE\t\t0x06 /* Management frame access */\n#define B53_MEM_ACCESS_PAGE\t\t0x08 /* Memory access */\n\n/* PHY Registers */\n#define B53_PORT_MII_PAGE(i)\t\t(0x10 + (i)) /* Port i MII Registers */\n#define B53_IM_PORT_PAGE\t\t0x18 /* Inverse MII Port (to EMAC) */\n#define B53_ALL_PORT_PAGE\t\t0x19 /* All ports MII (broadcast) */\n\n/* MIB registers */\n#define B53_MIB_PAGE(i)\t\t\t(0x20 + (i))\n\n/* Quality of Service (QoS) Registers */\n#define B53_QOS_PAGE\t\t\t0x30\n\n/* Port VLAN Page */\n#define B53_PVLAN_PAGE\t\t\t0x31\n\n/* VLAN Registers */\n#define B53_VLAN_PAGE\t\t\t0x34\n\n/* Jumbo Frame Registers */\n#define B53_JUMBO_PAGE\t\t\t0x40\n\n/* CFP Configuration Registers Page */\n#define B53_CFP_PAGE\t\t\t0xa1\n\n/*************************************************************************\n * Control Page registers\n *************************************************************************/\n\n/* Port Control Register (8 bit) */\n#define B53_PORT_CTRL(i)\t\t(0x00 + (i))\n#define   PORT_CTRL_RX_DISABLE\t\tBIT(0)\n#define   PORT_CTRL_TX_DISABLE\t\tBIT(1)\n#define   PORT_CTRL_RX_BCST_EN\t\tBIT(2) /* Broadcast RX (P8 only) */\n#define   PORT_CTRL_RX_MCST_EN\t\tBIT(3) /* Multicast RX (P8 only) */\n#define   PORT_CTRL_RX_UCST_EN\t\tBIT(4) /* Unicast RX (P8 only) */\n#define\t  PORT_CTRL_STP_STATE_S\t\t5\n#define   PORT_CTRL_STP_STATE_MASK\t(0x7 << PORT_CTRL_STP_STATE_S)\n\n/* SMP Control Register (8 bit) */\n#define B53_SMP_CTRL\t\t\t0x0a\n\n/* Switch Mode Control Register (8 bit) */\n#define B53_SWITCH_MODE\t\t\t0x0b\n#define   SM_SW_FWD_MODE\t\tBIT(0)\t/* 1 = Managed Mode */\n#define   SM_SW_FWD_EN\t\t\tBIT(1)\t/* Forwarding Enable */\n\n/* IMP Port state override register (8 bit) */\n#define B53_PORT_OVERRIDE_CTRL\t\t0x0e\n#define   PORT_OVERRIDE_LINK\t\tBIT(0)\n#define   PORT_OVERRIDE_FULL_DUPLEX\tBIT(1) /* 0 = Half Duplex */\n#define   PORT_OVERRIDE_SPEED_S\t\t2\n#define   PORT_OVERRIDE_SPEED_10M\t(0 << PORT_OVERRIDE_SPEED_S)\n#define   PORT_OVERRIDE_SPEED_100M\t(1 << PORT_OVERRIDE_SPEED_S)\n#define   PORT_OVERRIDE_SPEED_1000M\t(2 << PORT_OVERRIDE_SPEED_S)\n#define   PORT_OVERRIDE_RV_MII_25\tBIT(4) /* BCM5325 only */\n#define   PORT_OVERRIDE_RX_FLOW\t\tBIT(4)\n#define   PORT_OVERRIDE_TX_FLOW\t\tBIT(5)\n#define   PORT_OVERRIDE_SPEED_2000M\tBIT(6) /* BCM5301X only, requires setting 1000M */\n#define   PORT_OVERRIDE_EN\t\tBIT(7) /* Use the register contents */\n\n/* Power-down mode control */\n#define B53_PD_MODE_CTRL_25\t\t0x0f\n\n/* IP Multicast control (8 bit) */\n#define B53_IP_MULTICAST_CTRL\t\t0x21\n#define  B53_IPMC_FWD_EN\t\tBIT(1)\n#define  B53_UC_FWD_EN\t\t\tBIT(6)\n#define  B53_MC_FWD_EN\t\t\tBIT(7)\n\n/* (16 bit) */\n#define B53_UC_FLOOD_MASK\t\t0x32\n#define B53_MC_FLOOD_MASK\t\t0x34\n#define B53_IPMC_FLOOD_MASK\t\t0x36\n\n/*\n * Override Ports 0-7 State on devices with xMII interfaces (8 bit)\n *\n * For port 8 still use B53_PORT_OVERRIDE_CTRL\n * Please note that not all ports are available on every hardware, e.g. BCM5301X\n * don't include overriding port 6, BCM63xx also have some limitations.\n */\n#define B53_GMII_PORT_OVERRIDE_CTRL(i)\t(0x58 + (i))\n#define   GMII_PO_LINK\t\t\tBIT(0)\n#define   GMII_PO_FULL_DUPLEX\t\tBIT(1) /* 0 = Half Duplex */\n#define   GMII_PO_SPEED_S\t\t2\n#define   GMII_PO_SPEED_10M\t\t(0 << GMII_PO_SPEED_S)\n#define   GMII_PO_SPEED_100M\t\t(1 << GMII_PO_SPEED_S)\n#define   GMII_PO_SPEED_1000M\t\t(2 << GMII_PO_SPEED_S)\n#define   GMII_PO_RX_FLOW\t\tBIT(4)\n#define   GMII_PO_TX_FLOW\t\tBIT(5)\n#define   GMII_PO_EN\t\t\tBIT(6) /* Use the register contents */\n#define   GMII_PO_SPEED_2000M\t\tBIT(7) /* BCM5301X only, requires setting 1000M */\n\n/* Software reset register (8 bit) */\n#define B53_SOFTRESET\t\t\t0x79\n\n/* Fast Aging Control register (8 bit) */\n#define B53_FAST_AGE_CTRL\t\t0x88\n#define   FAST_AGE_STATIC\t\tBIT(0)\n#define   FAST_AGE_DYNAMIC\t\tBIT(1)\n#define   FAST_AGE_PORT\t\t\tBIT(2)\n#define   FAST_AGE_VLAN\t\t\tBIT(3)\n#define   FAST_AGE_STP\t\t\tBIT(4)\n#define   FAST_AGE_MC\t\t\tBIT(5)\n#define   FAST_AGE_DONE\t\t\tBIT(7)\n\n/*************************************************************************\n * Status Page registers\n *************************************************************************/\n\n/* Link Status Summary Register (16bit) */\n#define B53_LINK_STAT\t\t\t0x00\n\n/* Link Status Change Register (16 bit) */\n#define B53_LINK_STAT_CHANGE\t\t0x02\n\n/* Port Speed Summary Register (16 bit for FE, 32 bit for GE) */\n#define B53_SPEED_STAT\t\t\t0x04\n#define  SPEED_PORT_FE(reg, port)\t(((reg) >> (port)) & 1)\n#define  SPEED_PORT_GE(reg, port)\t(((reg) >> 2 * (port)) & 3)\n#define  SPEED_STAT_10M\t\t\t0\n#define  SPEED_STAT_100M\t\t1\n#define  SPEED_STAT_1000M\t\t2\n\n/* Duplex Status Summary (16 bit) */\n#define B53_DUPLEX_STAT_FE\t\t0x06\n#define B53_DUPLEX_STAT_GE\t\t0x08\n#define B53_DUPLEX_STAT_63XX\t\t0x0c\n\n/* Revision ID register for BCM5325 */\n#define B53_REV_ID_25\t\t\t0x50\n\n/* Strap Value (48 bit) */\n#define B53_STRAP_VALUE\t\t\t0x70\n#define   SV_GMII_CTRL_115\t\tBIT(27)\n\n/*************************************************************************\n * Management Mode Page Registers\n *************************************************************************/\n\n/* Global Management Config Register (8 bit) */\n#define B53_GLOBAL_CONFIG\t\t0x00\n#define   GC_RESET_MIB\t\t\t0x01\n#define   GC_RX_BPDU_EN\t\t\t0x02\n#define   GC_MIB_AC_HDR_EN\t\t0x10\n#define   GC_MIB_AC_EN\t\t\t0x20\n#define   GC_FRM_MGMT_PORT_M\t\t0xC0\n#define   GC_FRM_MGMT_PORT_04\t\t0x00\n#define   GC_FRM_MGMT_PORT_MII\t\t0x80\n\n/* Broadcom Header control register (8 bit) */\n#define B53_BRCM_HDR\t\t\t0x03\n#define   BRCM_HDR_P8_EN\t\tBIT(0) /* Enable tagging on port 8 */\n#define   BRCM_HDR_P5_EN\t\tBIT(1) /* Enable tagging on port 5 */\n\n/* Device ID register (8 or 32 bit) */\n#define B53_DEVICE_ID\t\t\t0x30\n\n/* Revision ID register (8 bit) */\n#define B53_REV_ID\t\t\t0x40\n\n/*************************************************************************\n * ARL Access Page Registers\n *************************************************************************/\n\n/* VLAN Table Access Register (8 bit) */\n#define B53_VT_ACCESS\t\t\t0x80\n#define B53_VT_ACCESS_9798\t\t0x60 /* for BCM5397/BCM5398 */\n#define B53_VT_ACCESS_63XX\t\t0x60 /* for BCM6328/62/68 */\n#define   VTA_CMD_WRITE\t\t\t0\n#define   VTA_CMD_READ\t\t\t1\n#define   VTA_CMD_CLEAR\t\t\t2\n#define   VTA_START_CMD\t\t\tBIT(7)\n\n/* VLAN Table Index Register (16 bit) */\n#define B53_VT_INDEX\t\t\t0x81\n#define B53_VT_INDEX_9798\t\t0x61\n#define B53_VT_INDEX_63XX\t\t0x62\n\n/* VLAN Table Entry Register (32 bit) */\n#define B53_VT_ENTRY\t\t\t0x83\n#define B53_VT_ENTRY_9798\t\t0x63\n#define B53_VT_ENTRY_63XX\t\t0x64\n#define   VTE_MEMBERS\t\t\t0x1ff\n#define   VTE_UNTAG_S\t\t\t9\n#define   VTE_UNTAG\t\t\t(0x1ff << 9)\n\n/*************************************************************************\n * Port VLAN Registers\n *************************************************************************/\n\n/* Port VLAN mask (16 bit) IMP port is always 8, also on 5325 & co */\n#define B53_PVLAN_PORT_MASK(i)\t\t((i) * 2)\n\n/*************************************************************************\n * 802.1Q Page Registers\n *************************************************************************/\n\n/* Global QoS Control (8 bit) */\n#define B53_QOS_GLOBAL_CTL\t\t0x00\n\n/* Enable 802.1Q for individual Ports (16 bit) */\n#define B53_802_1P_EN\t\t\t0x04\n\n/*************************************************************************\n * VLAN Page Registers\n *************************************************************************/\n\n/* VLAN Control 0 (8 bit) */\n#define B53_VLAN_CTRL0\t\t\t0x00\n#define   VC0_8021PF_CTRL_MASK\t\t0x3\n#define   VC0_8021PF_CTRL_NONE\t\t0x0\n#define   VC0_8021PF_CTRL_CHANGE_PRI\t0x1\n#define   VC0_8021PF_CTRL_CHANGE_VID\t0x2\n#define   VC0_8021PF_CTRL_CHANGE_BOTH\t0x3\n#define   VC0_8021QF_CTRL_MASK\t\t0xc\n#define   VC0_8021QF_CTRL_CHANGE_PRI\t0x1\n#define   VC0_8021QF_CTRL_CHANGE_VID\t0x2\n#define   VC0_8021QF_CTRL_CHANGE_BOTH\t0x3\n#define   VC0_RESERVED_1\t\tBIT(1)\n#define   VC0_DROP_VID_MISS\t\tBIT(4)\n#define   VC0_VID_HASH_VID\t\tBIT(5)\n#define   VC0_VID_CHK_EN\t\tBIT(6)\t/* Use VID,DA or VID,SA */\n#define   VC0_VLAN_EN\t\t\tBIT(7)\t/* 802.1Q VLAN Enabled */\n\n/* VLAN Control 1 (8 bit) */\n#define B53_VLAN_CTRL1\t\t\t0x01\n#define   VC1_RX_MCST_TAG_EN\t\tBIT(1)\n#define   VC1_RX_MCST_FWD_EN\t\tBIT(2)\n#define   VC1_RX_MCST_UNTAG_EN\t\tBIT(3)\n\n/* VLAN Control 2 (8 bit) */\n#define B53_VLAN_CTRL2\t\t\t0x02\n\n/* VLAN Control 3 (8 bit when BCM5325, 16 bit else) */\n#define B53_VLAN_CTRL3\t\t\t0x03\n#define B53_VLAN_CTRL3_63XX\t\t0x04\n#define   VC3_MAXSIZE_1532\t\tBIT(6) /* 5325 only */\n#define   VC3_HIGH_8BIT_EN\t\tBIT(7) /* 5325 only */\n\n/* VLAN Control 4 (8 bit) */\n#define B53_VLAN_CTRL4\t\t\t0x05\n#define B53_VLAN_CTRL4_25\t\t0x04\n#define B53_VLAN_CTRL4_63XX\t\t0x06\n#define   VC4_ING_VID_CHECK_S\t\t6\n#define   VC4_ING_VID_CHECK_MASK\t(0x3 << VC4_ING_VID_CHECK_S)\n#define   VC4_ING_VID_VIO_FWD\t\t0 /* forward, but do not learn */\n#define   VC4_ING_VID_VIO_DROP\t\t1 /* drop VID violations */\n#define   VC4_NO_ING_VID_CHK\t\t2 /* do not check */\n#define   VC4_ING_VID_VIO_TO_IMP\t3 /* redirect to MII port */\n\n/* VLAN Control 5 (8 bit) */\n#define B53_VLAN_CTRL5\t\t\t0x06\n#define B53_VLAN_CTRL5_25\t\t0x05\n#define B53_VLAN_CTRL5_63XX\t\t0x07\n#define   VC5_VID_FFF_EN\t\tBIT(2)\n#define   VC5_DROP_VTABLE_MISS\t\tBIT(3)\n\n/* VLAN Control 6 (8 bit) */\n#define B53_VLAN_CTRL6\t\t\t0x07\n#define B53_VLAN_CTRL6_63XX\t\t0x08\n\n/* VLAN Table Access Register (16 bit) */\n#define B53_VLAN_TABLE_ACCESS_25\t0x06\t/* BCM5325E/5350 */\n#define B53_VLAN_TABLE_ACCESS_65\t0x08\t/* BCM5365 */\n#define   VTA_VID_LOW_MASK_25\t\t0xf\n#define   VTA_VID_LOW_MASK_65\t\t0xff\n#define   VTA_VID_HIGH_S_25\t\t4\n#define   VTA_VID_HIGH_S_65\t\t8\n#define   VTA_VID_HIGH_MASK_25\t\t(0xff << VTA_VID_HIGH_S_25E)\n#define   VTA_VID_HIGH_MASK_65\t\t(0xf << VTA_VID_HIGH_S_65)\n#define   VTA_RW_STATE\t\t\tBIT(12)\n#define   VTA_RW_STATE_RD\t\t0\n#define   VTA_RW_STATE_WR\t\tBIT(12)\n#define   VTA_RW_OP_EN\t\t\tBIT(13)\n\n/* VLAN Read/Write Registers for (16/32 bit) */\n#define B53_VLAN_WRITE_25\t\t0x08\n#define B53_VLAN_WRITE_65\t\t0x0a\n#define B53_VLAN_READ\t\t\t0x0c\n#define   VA_MEMBER_MASK\t\t0x3f\n#define   VA_UNTAG_S_25\t\t\t6\n#define   VA_UNTAG_MASK_25\t\t0x3f\n#define   VA_UNTAG_S_65\t\t\t7\n#define   VA_UNTAG_MASK_65\t\t0x1f\n#define   VA_VID_HIGH_S\t\t\t12\n#define   VA_VID_HIGH_MASK\t\t(0xffff << VA_VID_HIGH_S)\n#define   VA_VALID_25\t\t\tBIT(20)\n#define   VA_VALID_25_R4\t\tBIT(24)\n#define   VA_VALID_65\t\t\tBIT(14)\n\n/* VLAN Port Default Tag (16 bit) */\n#define B53_VLAN_PORT_DEF_TAG(i)\t(0x10 + 2 * (i))\n\n/*************************************************************************\n * Jumbo Frame Page Registers\n *************************************************************************/\n\n/* Jumbo Enable Port Mask (bit i == port i enabled) (32 bit) */\n#define B53_JUMBO_PORT_MASK\t\t0x01\n#define B53_JUMBO_PORT_MASK_63XX\t0x04\n#define   JPM_10_100_JUMBO_EN\t\tBIT(24) /* GigE always enabled */\n\n/* Good Frame Max Size without 802.1Q TAG (16 bit) */\n#define B53_JUMBO_MAX_SIZE\t\t0x05\n#define B53_JUMBO_MAX_SIZE_63XX\t\t0x08\n#define   JMS_MIN_SIZE\t\t\t1518\n#define   JMS_MAX_SIZE\t\t\t9724\n\n/*************************************************************************\n * CFP Configuration Page Registers\n *************************************************************************/\n\n/* CFP Control Register with ports map (8 bit) */\n#define B53_CFP_CTRL\t\t\t0x00\n\n#endif /* !__B53_REGS_H */\n"
  },
  {
    "path": "target/linux/generic/files/drivers/net/phy/b53/b53_spi.c",
    "content": "/*\n * B53 register access through SPI\n *\n * Copyright (C) 2011-2013 Jonas Gorski <jogo@openwrt.org>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n */\n\n#include <asm/unaligned.h>\n\n#include <linux/kernel.h>\n#include <linux/module.h>\n#include <linux/spi/spi.h>\n#include <linux/of.h>\n#include <linux/platform_data/b53.h>\n\n#include \"b53_priv.h\"\n\n#define B53_SPI_DATA\t\t0xf0\n\n#define B53_SPI_STATUS\t\t0xfe\n#define B53_SPI_CMD_SPIF\tBIT(7)\n#define B53_SPI_CMD_RACK\tBIT(5)\n\n#define B53_SPI_CMD_READ\t0x00\n#define B53_SPI_CMD_WRITE\t0x01\n#define B53_SPI_CMD_NORMAL\t0x60\n#define B53_SPI_CMD_FAST\t0x10\n\n#define B53_SPI_PAGE_SELECT\t0xff\n\nstatic inline int b53_spi_read_reg(struct spi_device *spi, u8 reg, u8 *val,\n\t\t\t\t     unsigned len)\n{\n\tu8 txbuf[2];\n\n\ttxbuf[0] = B53_SPI_CMD_NORMAL | B53_SPI_CMD_READ;\n\ttxbuf[1] = reg;\n\n\treturn spi_write_then_read(spi, txbuf, 2, val, len);\n}\n\nstatic inline int b53_spi_clear_status(struct spi_device *spi)\n{\n\tunsigned int i;\n\tu8 rxbuf;\n\tint ret;\n\n\tfor (i = 0; i < 10; i++) {\n\t\tret = b53_spi_read_reg(spi, B53_SPI_STATUS, &rxbuf, 1);\n\t\tif (ret)\n\t\t\treturn ret;\n\n\t\tif (!(rxbuf & B53_SPI_CMD_SPIF))\n\t\t\tbreak;\n\n\t\tmdelay(1);\n\t}\n\n\tif (i == 10)\n\t\treturn -EIO;\n\n\treturn 0;\n}\n\nstatic inline int b53_spi_set_page(struct spi_device *spi, u8 page)\n{\n\tu8 txbuf[3];\n\n\ttxbuf[0] = B53_SPI_CMD_NORMAL | B53_SPI_CMD_WRITE;\n\ttxbuf[1] = B53_SPI_PAGE_SELECT;\n\ttxbuf[2] = page;\n\n\treturn spi_write(spi, txbuf, sizeof(txbuf));\n}\n\nstatic inline int b53_prepare_reg_access(struct spi_device *spi, u8 page)\n{\n\tint ret = b53_spi_clear_status(spi);\n\n\tif (ret)\n\t\treturn ret;\n\n\treturn b53_spi_set_page(spi, page);\n}\n\nstatic int b53_spi_prepare_reg_read(struct spi_device *spi, u8 reg)\n{\n\tu8 rxbuf;\n\tint retry_count;\n\tint ret;\n\n\tret = b53_spi_read_reg(spi, reg, &rxbuf, 1);\n\tif (ret)\n\t\treturn ret;\n\n\tfor (retry_count = 0; retry_count < 10; retry_count++) {\n\t\tret = b53_spi_read_reg(spi, B53_SPI_STATUS, &rxbuf, 1);\n\t\tif (ret)\n\t\t\treturn ret;\n\n\t\tif (rxbuf & B53_SPI_CMD_RACK)\n\t\t\tbreak;\n\n\t\tmdelay(1);\n\t}\n\n\tif (retry_count == 10)\n\t\treturn -EIO;\n\n\treturn 0;\n}\n\nstatic int b53_spi_read(struct b53_device *dev, u8 page, u8 reg, u8 *data,\n\t\t\tunsigned len)\n{\n\tstruct spi_device *spi = dev->priv;\n\tint ret;\n\n\tret = b53_prepare_reg_access(spi, page);\n\tif (ret)\n\t\treturn ret;\n\n\tret = b53_spi_prepare_reg_read(spi, reg);\n\tif (ret)\n\t\treturn ret;\n\n\treturn b53_spi_read_reg(spi, B53_SPI_DATA, data, len);\n}\n\nstatic int b53_spi_read8(struct b53_device *dev, u8 page, u8 reg, u8 *val)\n{\n\treturn b53_spi_read(dev, page, reg, val, 1);\n}\n\nstatic int b53_spi_read16(struct b53_device *dev, u8 page, u8 reg, u16 *val)\n{\n\tint ret = b53_spi_read(dev, page, reg, (u8 *)val, 2);\n\n\tif (!ret)\n\t\t*val = le16_to_cpu(*val);\n\n\treturn ret;\n}\n\nstatic int b53_spi_read32(struct b53_device *dev, u8 page, u8 reg, u32 *val)\n{\n\tint ret = b53_spi_read(dev, page, reg, (u8 *)val, 4);\n\n\tif (!ret)\n\t\t*val = le32_to_cpu(*val);\n\n\treturn ret;\n}\n\nstatic int b53_spi_read48(struct b53_device *dev, u8 page, u8 reg, u64 *val)\n{\n\tint ret;\n\n\t*val = 0;\n\tret = b53_spi_read(dev, page, reg, (u8 *)val, 6);\n\tif (!ret)\n\t\t*val = le64_to_cpu(*val);\n\n\treturn ret;\n}\n\nstatic int b53_spi_read64(struct b53_device *dev, u8 page, u8 reg, u64 *val)\n{\n\tint ret = b53_spi_read(dev, page, reg, (u8 *)val, 8);\n\n\tif (!ret)\n\t\t*val = le64_to_cpu(*val);\n\n\treturn ret;\n}\n\nstatic int b53_spi_write8(struct b53_device *dev, u8 page, u8 reg, u8 value)\n{\n\tstruct spi_device *spi = dev->priv;\n\tint ret;\n\tu8 txbuf[3];\n\n\tret = b53_prepare_reg_access(spi, page);\n\tif (ret)\n\t\treturn ret;\n\n\ttxbuf[0] = B53_SPI_CMD_NORMAL | B53_SPI_CMD_WRITE;\n\ttxbuf[1] = reg;\n\ttxbuf[2] = value;\n\n\treturn spi_write(spi, txbuf, sizeof(txbuf));\n}\n\nstatic int b53_spi_write16(struct b53_device *dev, u8 page, u8 reg, u16 value)\n{\n\tstruct spi_device *spi = dev->priv;\n\tint ret;\n\tu8 txbuf[4];\n\n\tret = b53_prepare_reg_access(spi, page);\n\tif (ret)\n\t\treturn ret;\n\n\ttxbuf[0] = B53_SPI_CMD_NORMAL | B53_SPI_CMD_WRITE;\n\ttxbuf[1] = reg;\n\tput_unaligned_le16(value, &txbuf[2]);\n\n\treturn spi_write(spi, txbuf, sizeof(txbuf));\n}\n\nstatic int b53_spi_write32(struct b53_device *dev, u8 page, u8 reg, u32 value)\n{\n\tstruct spi_device *spi = dev->priv;\n\tint ret;\n\tu8 txbuf[6];\n\n\tret = b53_prepare_reg_access(spi, page);\n\tif (ret)\n\t\treturn ret;\n\n\ttxbuf[0] = B53_SPI_CMD_NORMAL | B53_SPI_CMD_WRITE;\n\ttxbuf[1] = reg;\n\tput_unaligned_le32(value, &txbuf[2]);\n\n\treturn spi_write(spi, txbuf, sizeof(txbuf));\n}\n\nstatic int b53_spi_write48(struct b53_device *dev, u8 page, u8 reg, u64 value)\n{\n\tstruct spi_device *spi = dev->priv;\n\tint ret;\n\tu8 txbuf[10];\n\n\tret = b53_prepare_reg_access(spi, page);\n\tif (ret)\n\t\treturn ret;\n\n\ttxbuf[0] = B53_SPI_CMD_NORMAL | B53_SPI_CMD_WRITE;\n\ttxbuf[1] = reg;\n\tput_unaligned_le64(value, &txbuf[2]);\n\n\treturn spi_write(spi, txbuf, sizeof(txbuf) - 2);\n}\n\nstatic int b53_spi_write64(struct b53_device *dev, u8 page, u8 reg, u64 value)\n{\n\tstruct spi_device *spi = dev->priv;\n\tint ret;\n\tu8 txbuf[10];\n\n\tret = b53_prepare_reg_access(spi, page);\n\tif (ret)\n\t\treturn ret;\n\n\ttxbuf[0] = B53_SPI_CMD_NORMAL | B53_SPI_CMD_WRITE;\n\ttxbuf[1] = reg;\n\tput_unaligned_le64(value, &txbuf[2]);\n\n\treturn spi_write(spi, txbuf, sizeof(txbuf));\n}\n\nstatic struct b53_io_ops b53_spi_ops = {\n\t.read8 = b53_spi_read8,\n\t.read16 = b53_spi_read16,\n\t.read32 = b53_spi_read32,\n\t.read48 = b53_spi_read48,\n\t.read64 = b53_spi_read64,\n\t.write8 = b53_spi_write8,\n\t.write16 = b53_spi_write16,\n\t.write32 = b53_spi_write32,\n\t.write48 = b53_spi_write48,\n\t.write64 = b53_spi_write64,\n};\n\nstatic int b53_spi_probe(struct spi_device *spi)\n{\n\tstruct b53_device *dev;\n\tint ret;\n\n\tdev = b53_switch_alloc(&spi->dev, &b53_spi_ops, spi);\n\tif (!dev)\n\t\treturn -ENOMEM;\n\n\tif (spi->dev.platform_data)\n\t\tdev->pdata = spi->dev.platform_data;\n\n\tret = b53_switch_register(dev);\n\tif (ret)\n\t\treturn ret;\n\n\tspi_set_drvdata(spi, dev);\n\n\treturn 0;\n}\n\nstatic int b53_spi_remove(struct spi_device *spi)\n{\n\tstruct b53_device *dev = spi_get_drvdata(spi);\n\n\tif (dev)\n\t\tb53_switch_remove(dev);\n\n\treturn 0;\n}\n\nstatic const struct of_device_id b53_of_match[] = {\n\t{ .compatible = \"brcm,bcm5325\" },\n\t{ .compatible = \"brcm,bcm53115\" },\n\t{ .compatible = \"brcm,bcm53125\" },\n\t{ .compatible = \"brcm,bcm53128\" },\n\t{ .compatible = \"brcm,bcm5365\" },\n\t{ .compatible = \"brcm,bcm5395\" },\n\t{ .compatible = \"brcm,bcm5397\" },\n\t{ .compatible = \"brcm,bcm5398\" },\n\t{ /* sentinel */ },\n};\n\nstatic struct spi_driver b53_spi_driver = {\n\t.driver = {\n\t\t.name\t= \"b53-switch\",\n\t\t.bus\t= &spi_bus_type,\n\t\t.owner\t= THIS_MODULE,\n\t\t.of_match_table = b53_of_match,\n\t},\n\t.probe\t= b53_spi_probe,\n\t.remove\t= b53_spi_remove,\n};\n\nmodule_spi_driver(b53_spi_driver);\n\nMODULE_AUTHOR(\"Jonas Gorski <jogo@openwrt.org>\");\nMODULE_DESCRIPTION(\"B53 SPI access driver\");\nMODULE_LICENSE(\"Dual BSD/GPL\");\n"
  },
  {
    "path": "target/linux/generic/files/drivers/net/phy/b53/b53_srab.c",
    "content": "/*\n * B53 register access through Switch Register Access Bridge Registers\n *\n * Copyright (C) 2013 Hauke Mehrtens <hauke@hauke-m.de>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n */\n\n#include <linux/kernel.h>\n#include <linux/module.h>\n#include <linux/platform_device.h>\n#include <linux/platform_data/b53.h>\n\n#include \"b53_priv.h\"\n\n/* command and status register of the SRAB */\n#define B53_SRAB_CMDSTAT\t\t0x2c\n#define  B53_SRAB_CMDSTAT_RST\t\tBIT(2)\n#define  B53_SRAB_CMDSTAT_WRITE\t\tBIT(1)\n#define  B53_SRAB_CMDSTAT_GORDYN\tBIT(0)\n#define  B53_SRAB_CMDSTAT_PAGE\t\t24\n#define  B53_SRAB_CMDSTAT_REG\t\t16\n\n/* high order word of write data to switch registe */\n#define B53_SRAB_WD_H\t\t\t0x30\n\n/* low order word of write data to switch registe */\n#define B53_SRAB_WD_L\t\t\t0x34\n\n/* high order word of read data from switch register */\n#define B53_SRAB_RD_H\t\t\t0x38\n\n/* low order word of read data from switch register */\n#define B53_SRAB_RD_L\t\t\t0x3c\n\n/* command and status register of the SRAB */\n#define B53_SRAB_CTRLS\t\t\t0x40\n#define  B53_SRAB_CTRLS_RCAREQ\t\tBIT(3)\n#define  B53_SRAB_CTRLS_RCAGNT\t\tBIT(4)\n#define  B53_SRAB_CTRLS_SW_INIT_DONE\tBIT(6)\n\n/* the register captures interrupt pulses from the switch */\n#define B53_SRAB_INTR\t\t\t0x44\n\nstatic int b53_srab_request_grant(struct b53_device *dev)\n{\n\tu8 __iomem *regs = dev->priv;\n\tu32 ctrls;\n\tint i;\n\n\tctrls = readl(regs + B53_SRAB_CTRLS);\n\tctrls |= B53_SRAB_CTRLS_RCAREQ;\n\twritel(ctrls, regs + B53_SRAB_CTRLS);\n\n\tfor (i = 0; i < 20; i++) {\n\t\tctrls = readl(regs + B53_SRAB_CTRLS);\n\t\tif (ctrls & B53_SRAB_CTRLS_RCAGNT)\n\t\t\tbreak;\n\t\tusleep_range(10, 100);\n\t}\n\tif (WARN_ON(i == 5))\n\t\treturn -EIO;\n\n\treturn 0;\n}\n\nstatic void b53_srab_release_grant(struct b53_device *dev)\n{\n\tu8 __iomem *regs = dev->priv;\n\tu32 ctrls;\n\n\tctrls = readl(regs + B53_SRAB_CTRLS);\n\tctrls &= ~B53_SRAB_CTRLS_RCAREQ;\n\twritel(ctrls, regs + B53_SRAB_CTRLS);\n}\n\nstatic int b53_srab_op(struct b53_device *dev, u8 page, u8 reg, u32 op)\n{\n\tint i;\n\tu32 cmdstat;\n\tu8 __iomem *regs = dev->priv;\n\n\t/* set register address */\n\tcmdstat = (page << B53_SRAB_CMDSTAT_PAGE) |\n\t\t  (reg << B53_SRAB_CMDSTAT_REG) |\n\t\t  B53_SRAB_CMDSTAT_GORDYN |\n\t\t  op;\n\twritel(cmdstat, regs + B53_SRAB_CMDSTAT);\n\n\t/* check if operation completed */\n\tfor (i = 0; i < 5; ++i) {\n\t\tcmdstat = readl(regs + B53_SRAB_CMDSTAT);\n\t\tif (!(cmdstat & B53_SRAB_CMDSTAT_GORDYN))\n\t\t\tbreak;\n\t\tusleep_range(10, 100);\n\t}\n\n\tif (WARN_ON(i == 5))\n\t\treturn -EIO;\n\n\treturn 0;\n}\n\nstatic int b53_srab_read8(struct b53_device *dev, u8 page, u8 reg, u8 *val)\n{\n\tu8 __iomem *regs = dev->priv;\n\tint ret = 0;\n\n\tret = b53_srab_request_grant(dev);\n\tif (ret)\n\t\tgoto err;\n\n\tret = b53_srab_op(dev, page, reg, 0);\n\tif (ret)\n\t\tgoto err;\n\n\t*val = readl(regs + B53_SRAB_RD_L) & 0xff;\n\nerr:\n\tb53_srab_release_grant(dev);\n\n\treturn ret;\n}\n\nstatic int b53_srab_read16(struct b53_device *dev, u8 page, u8 reg, u16 *val)\n{\n\tu8 __iomem *regs = dev->priv;\n\tint ret = 0;\n\n\tret = b53_srab_request_grant(dev);\n\tif (ret)\n\t\tgoto err;\n\n\tret = b53_srab_op(dev, page, reg, 0);\n\tif (ret)\n\t\tgoto err;\n\n\t*val = readl(regs + B53_SRAB_RD_L) & 0xffff;\n\nerr:\n\tb53_srab_release_grant(dev);\n\n\treturn ret;\n}\n\nstatic int b53_srab_read32(struct b53_device *dev, u8 page, u8 reg, u32 *val)\n{\n\tu8 __iomem *regs = dev->priv;\n\tint ret = 0;\n\n\tret = b53_srab_request_grant(dev);\n\tif (ret)\n\t\tgoto err;\n\n\tret = b53_srab_op(dev, page, reg, 0);\n\tif (ret)\n\t\tgoto err;\n\n\t*val = readl(regs + B53_SRAB_RD_L);\n\nerr:\n\tb53_srab_release_grant(dev);\n\n\treturn ret;\n}\n\nstatic int b53_srab_read48(struct b53_device *dev, u8 page, u8 reg, u64 *val)\n{\n\tu8 __iomem *regs = dev->priv;\n\tint ret = 0;\n\n\tret = b53_srab_request_grant(dev);\n\tif (ret)\n\t\tgoto err;\n\n\tret = b53_srab_op(dev, page, reg, 0);\n\tif (ret)\n\t\tgoto err;\n\n\t*val = readl(regs + B53_SRAB_RD_L);\n\t*val += ((u64)readl(regs + B53_SRAB_RD_H) & 0xffff) << 32;\n\nerr:\n\tb53_srab_release_grant(dev);\n\n\treturn ret;\n}\n\nstatic int b53_srab_read64(struct b53_device *dev, u8 page, u8 reg, u64 *val)\n{\n\tu8 __iomem *regs = dev->priv;\n\tint ret = 0;\n\n\tret = b53_srab_request_grant(dev);\n\tif (ret)\n\t\tgoto err;\n\n\tret = b53_srab_op(dev, page, reg, 0);\n\tif (ret)\n\t\tgoto err;\n\n\t*val = readl(regs + B53_SRAB_RD_L);\n\t*val += (u64)readl(regs + B53_SRAB_RD_H) << 32;\n\nerr:\n\tb53_srab_release_grant(dev);\n\n\treturn ret;\n}\n\nstatic int b53_srab_write8(struct b53_device *dev, u8 page, u8 reg, u8 value)\n{\n\tu8 __iomem *regs = dev->priv;\n\tint ret = 0;\n\n\tret = b53_srab_request_grant(dev);\n\tif (ret)\n\t\tgoto err;\n\n\twritel(value, regs + B53_SRAB_WD_L);\n\n\tret = b53_srab_op(dev, page, reg, B53_SRAB_CMDSTAT_WRITE);\n\nerr:\n\tb53_srab_release_grant(dev);\n\n\treturn ret;\n}\n\nstatic int b53_srab_write16(struct b53_device *dev, u8 page, u8 reg,\n\t\t\t     u16 value)\n{\n\tu8 __iomem *regs = dev->priv;\n\tint ret = 0;\n\n\tret = b53_srab_request_grant(dev);\n\tif (ret)\n\t\tgoto err;\n\n\twritel(value, regs + B53_SRAB_WD_L);\n\n\tret = b53_srab_op(dev, page, reg, B53_SRAB_CMDSTAT_WRITE);\n\nerr:\n\tb53_srab_release_grant(dev);\n\n\treturn ret;\n}\n\nstatic int b53_srab_write32(struct b53_device *dev, u8 page, u8 reg,\n\t\t\t\t    u32 value)\n{\n\tu8 __iomem *regs = dev->priv;\n\tint ret = 0;\n\n\tret = b53_srab_request_grant(dev);\n\tif (ret)\n\t\tgoto err;\n\n\twritel(value, regs + B53_SRAB_WD_L);\n\n\tret = b53_srab_op(dev, page, reg, B53_SRAB_CMDSTAT_WRITE);\n\nerr:\n\tb53_srab_release_grant(dev);\n\n\treturn ret;\n\n}\n\nstatic int b53_srab_write48(struct b53_device *dev, u8 page, u8 reg,\n\t\t\t\t    u64 value)\n{\n\tu8 __iomem *regs = dev->priv;\n\tint ret = 0;\n\n\tret = b53_srab_request_grant(dev);\n\tif (ret)\n\t\tgoto err;\n\n\twritel((u32)value, regs + B53_SRAB_WD_L);\n\twritel((u16)(value >> 32), regs + B53_SRAB_WD_H);\n\n\tret = b53_srab_op(dev, page, reg, B53_SRAB_CMDSTAT_WRITE);\n\nerr:\n\tb53_srab_release_grant(dev);\n\n\treturn ret;\n\n}\n\nstatic int b53_srab_write64(struct b53_device *dev, u8 page, u8 reg,\n\t\t\t     u64 value)\n{\n\tu8 __iomem *regs = dev->priv;\n\tint ret = 0;\n\n\tret = b53_srab_request_grant(dev);\n\tif (ret)\n\t\tgoto err;\n\n\twritel((u32)value, regs + B53_SRAB_WD_L);\n\twritel((u32)(value >> 32), regs + B53_SRAB_WD_H);\n\n\tret = b53_srab_op(dev, page, reg, B53_SRAB_CMDSTAT_WRITE);\n\nerr:\n\tb53_srab_release_grant(dev);\n\n\treturn ret;\n}\n\nstatic struct b53_io_ops b53_srab_ops = {\n\t.read8 = b53_srab_read8,\n\t.read16 = b53_srab_read16,\n\t.read32 = b53_srab_read32,\n\t.read48 = b53_srab_read48,\n\t.read64 = b53_srab_read64,\n\t.write8 = b53_srab_write8,\n\t.write16 = b53_srab_write16,\n\t.write32 = b53_srab_write32,\n\t.write48 = b53_srab_write48,\n\t.write64 = b53_srab_write64,\n};\n\nstatic int b53_srab_probe(struct platform_device *pdev)\n{\n\tstruct b53_platform_data *pdata = pdev->dev.platform_data;\n\tstruct b53_device *dev;\n\n\tif (!pdata)\n\t\treturn -EINVAL;\n\n\tdev = b53_switch_alloc(&pdev->dev, &b53_srab_ops, pdata->regs);\n\tif (!dev)\n\t\treturn -ENOMEM;\n\n\tif (pdata)\n\t\tdev->pdata = pdata;\n\n\tplatform_set_drvdata(pdev, dev);\n\n\treturn b53_switch_register(dev);\n}\n\nstatic int b53_srab_remove(struct platform_device *pdev)\n{\n\tstruct b53_device *dev = platform_get_drvdata(pdev);\n\n\tif (dev)\n\t\tb53_switch_remove(dev);\n\n\treturn 0;\n}\n\nstatic struct platform_driver b53_srab_driver = {\n\t.probe = b53_srab_probe,\n\t.remove = b53_srab_remove,\n\t.driver = {\n\t\t.name = \"b53-srab-switch\",\n\t},\n};\n\nmodule_platform_driver(b53_srab_driver);\nMODULE_AUTHOR(\"Hauke Mehrtens <hauke@hauke-m.de>\");\nMODULE_DESCRIPTION(\"B53 Switch Register Access Bridge Registers (SRAB) access driver\");\nMODULE_LICENSE(\"Dual BSD/GPL\");\n"
  },
  {
    "path": "target/linux/generic/files/drivers/net/phy/ip17xx.c",
    "content": "/*\n * ip17xx.c: Swconfig configuration for IC+ IP17xx switch family\n *\n * Copyright (C) 2008 Patrick Horn <patrick.horn@gmail.com>\n * Copyright (C) 2008, 2010 Martin Mares <mj@ucw.cz>\n * Copyright (C) 2009 Felix Fietkau <nbd@nbd.name>\n *\n * This program is free software; you can redistribute it and/or\n * modify it under the terms of the GNU General Public License\n * as published by the Free Software Foundation; either version 2\n * of the License, or (at your option) any later version.\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.\tSee the\n * GNU General Public License for more details.\n */\n\n#include <linux/kernel.h>\n#include <linux/module.h>\n#include <linux/init.h>\n#include <linux/list.h>\n#include <linux/skbuff.h>\n#include <linux/mii.h>\n#include <linux/phy.h>\n#include <linux/delay.h>\n#include <linux/switch.h>\n#include <linux/device.h>\n\n#define MAX_VLANS 16\n#define MAX_PORTS 9\n#undef DUMP_MII_IO\n\ntypedef struct ip17xx_reg {\n\tu16 p;\t\t\t// phy\n\tu16 m;\t\t\t// mii\n} reg;\ntypedef char bitnum;\n\n#define NOTSUPPORTED {-1,-1}\n\n#define REG_SUPP(x) (((x).m != ((u16)-1)) && ((x).p != (u16)-1))\n\nstruct ip17xx_state;\n\n/*********** CONSTANTS ***********/\nstruct register_mappings {\n\tchar *NAME;\n\tu16 MODEL_NO;\t\t\t// Compare to bits 4-9 of MII register 0,3.\n\tbitnum NUM_PORTS;\n\tbitnum CPU_PORT;\n\n/* The default VLAN for each port.\n\t Default: 0x0001 for Ports 0,1,2,3\n\t\t  0x0002 for Ports 4,5 */\n\treg VLAN_DEFAULT_TAG_REG[MAX_PORTS];\n\n/* These ports are tagged.\n\t Default: 0x00 */\n\treg ADD_TAG_REG;\n\treg REMOVE_TAG_REG;\n\tbitnum ADD_TAG_BIT[MAX_PORTS];\n/* These ports are untagged.\n\t Default: 0x00 (i.e. do not alter any VLAN tags...)\n\t Maybe set to 0 if user disables VLANs. */\n\tbitnum REMOVE_TAG_BIT[MAX_PORTS];\n\n/* Port M and Port N are on the same VLAN.\n\t Default: All ports on all VLANs. */\n// Use register {29, 19+N/2}\n\treg VLAN_LOOKUP_REG;\n// Port 5 uses register {30, 18} but same as odd bits.\n\treg VLAN_LOOKUP_REG_5;\t\t// in a different register on IP175C.\n\tbitnum VLAN_LOOKUP_EVEN_BIT[MAX_PORTS];\n\tbitnum VLAN_LOOKUP_ODD_BIT[MAX_PORTS];\n\n/* This VLAN corresponds to which ports.\n\t Default: 0x2f,0x30,0x3f,0x3f... */\n\treg TAG_VLAN_MASK_REG;\n\tbitnum TAG_VLAN_MASK_EVEN_BIT[MAX_PORTS];\n\tbitnum TAG_VLAN_MASK_ODD_BIT[MAX_PORTS];\n\n\tint RESET_VAL;\n\treg RESET_REG;\n\n\treg MODE_REG;\n\tint MODE_VAL;\n\n/* General flags */\n\treg ROUTER_CONTROL_REG;\n\treg VLAN_CONTROL_REG;\n\tbitnum TAG_VLAN_BIT;\n\tbitnum ROUTER_EN_BIT;\n\tbitnum NUMLAN_GROUPS_MAX;\n\tbitnum NUMLAN_GROUPS_BIT;\n\n\treg MII_REGISTER_EN;\n\tbitnum MII_REGISTER_EN_BIT;\n\n\t// set to 1 for 178C, 0 for 175C.\n\tbitnum SIMPLE_VLAN_REGISTERS;\t// 175C has two vlans per register but 178C has only one.\n\n\t// Pointers to functions which manipulate hardware state\n\tint (*update_state)(struct ip17xx_state *state);\n\tint (*set_vlan_mode)(struct ip17xx_state *state);\n\tint (*reset)(struct ip17xx_state *state);\n};\n\nstatic int ip175c_update_state(struct ip17xx_state *state);\nstatic int ip175c_set_vlan_mode(struct ip17xx_state *state);\nstatic int ip175c_reset(struct ip17xx_state *state);\n\nstatic const struct register_mappings IP178C = {\n\t.NAME = \"IP178C\",\n\t.MODEL_NO = 0x18,\n\t.VLAN_DEFAULT_TAG_REG = {\n\t\t{30,3},{30,4},{30,5},{30,6},{30,7},{30,8},\n\t\t{30,9},{30,10},{30,11},\n\t},\n\n\t.ADD_TAG_REG = {30,12},\n\t.ADD_TAG_BIT = {0,1,2,3,4,5,6,7,8},\n\t.REMOVE_TAG_REG = {30,13},\n\t.REMOVE_TAG_BIT = {4,5,6,7,8,9,10,11,12},\n\n\t.SIMPLE_VLAN_REGISTERS = 1,\n\n\t.VLAN_LOOKUP_REG = {31,0},// +N\n\t.VLAN_LOOKUP_REG_5 = NOTSUPPORTED, // not used with SIMPLE_VLAN_REGISTERS\n\t.VLAN_LOOKUP_EVEN_BIT = {0,1,2,3,4,5,6,7,8},\n\t.VLAN_LOOKUP_ODD_BIT = {0,1,2,3,4,5,6,7,8},\n\n\t.TAG_VLAN_MASK_REG = {30,14}, // +N\n\t.TAG_VLAN_MASK_EVEN_BIT = {0,1,2,3,4,5,6,7,8},\n\t.TAG_VLAN_MASK_ODD_BIT = {0,1,2,3,4,5,6,7,8},\n\n\t.RESET_VAL = 0x55AA,\n\t.RESET_REG = {30,0},\n\t.MODE_VAL = 0,\n\t.MODE_REG = NOTSUPPORTED,\n\n\t.ROUTER_CONTROL_REG = {30,30},\n\t.ROUTER_EN_BIT = 11,\n\t.NUMLAN_GROUPS_MAX = 8,\n\t.NUMLAN_GROUPS_BIT = 8, // {0-2}\n\n\t.VLAN_CONTROL_REG = {30,13},\n\t.TAG_VLAN_BIT = 3,\n\n\t.CPU_PORT = 8,\n\t.NUM_PORTS = 9,\n\n\t.MII_REGISTER_EN = NOTSUPPORTED,\n\n\t.update_state = ip175c_update_state,\n\t.set_vlan_mode = ip175c_set_vlan_mode,\n\t.reset = ip175c_reset,\n};\n\nstatic const struct register_mappings IP175C = {\n\t.NAME = \"IP175C\",\n\t.MODEL_NO = 0x18,\n\t.VLAN_DEFAULT_TAG_REG = {\n\t\t{29,24},{29,25},{29,26},{29,27},{29,28},{29,30},\n\t\tNOTSUPPORTED,NOTSUPPORTED,NOTSUPPORTED\n\t},\n\n\t.ADD_TAG_REG = {29,23},\n\t.REMOVE_TAG_REG = {29,23},\n\t.ADD_TAG_BIT = {11,12,13,14,15,1,-1,-1,-1},\n\t.REMOVE_TAG_BIT = {6,7,8,9,10,0,-1,-1,-1},\n\n\t.SIMPLE_VLAN_REGISTERS = 0,\n\n\t.VLAN_LOOKUP_REG = {29,19},// +N/2\n\t.VLAN_LOOKUP_REG_5 = {30,18},\n\t.VLAN_LOOKUP_EVEN_BIT = {8,9,10,11,12,15,-1,-1,-1},\n\t.VLAN_LOOKUP_ODD_BIT = {0,1,2,3,4,7,-1,-1,-1},\n\n\t.TAG_VLAN_MASK_REG = {30,1}, // +N/2\n\t.TAG_VLAN_MASK_EVEN_BIT = {0,1,2,3,4,5,-1,-1,-1},\n\t.TAG_VLAN_MASK_ODD_BIT = {8,9,10,11,12,13,-1,-1,-1},\n\n\t.RESET_VAL = 0x175C,\n\t.RESET_REG = {30,0},\n\t.MODE_VAL = 0x175C,\n\t.MODE_REG = {29,31},\n\n\t.ROUTER_CONTROL_REG = {30,9},\n\t.ROUTER_EN_BIT = 3,\n\t.NUMLAN_GROUPS_MAX = 8,\n\t.NUMLAN_GROUPS_BIT = 0, // {0-2}\n\n\t.VLAN_CONTROL_REG = {30,9},\n\t.TAG_VLAN_BIT = 7,\n\n\t.NUM_PORTS = 6,\n\t.CPU_PORT = 5,\n\n\t.MII_REGISTER_EN = NOTSUPPORTED,\n\n\t.update_state = ip175c_update_state,\n\t.set_vlan_mode = ip175c_set_vlan_mode,\n\t.reset = ip175c_reset,\n};\n\nstatic const struct register_mappings IP175A = {\n\t.NAME = \"IP175A\",\n\t.MODEL_NO = 0x05,\n\t.VLAN_DEFAULT_TAG_REG = {\n\t\t{0,24},{0,25},{0,26},{0,27},{0,28},NOTSUPPORTED,\n\t\tNOTSUPPORTED,NOTSUPPORTED,NOTSUPPORTED\n\t},\n\n\t.ADD_TAG_REG = {0,23},\n\t.REMOVE_TAG_REG = {0,23},\n\t.ADD_TAG_BIT = {11,12,13,14,15,-1,-1,-1,-1},\n\t.REMOVE_TAG_BIT = {6,7,8,9,10,-1,-1,-1,-1},\n\n\t.SIMPLE_VLAN_REGISTERS = 0,\n\n\t// Only programmable via EEPROM\n\t.VLAN_LOOKUP_REG = NOTSUPPORTED,// +N/2\n\t.VLAN_LOOKUP_REG_5 = NOTSUPPORTED,\n\t.VLAN_LOOKUP_EVEN_BIT = {8,9,10,11,12,-1,-1,-1,-1},\n\t.VLAN_LOOKUP_ODD_BIT = {0,1,2,3,4,-1,-1,-1,-1},\n\n\t.TAG_VLAN_MASK_REG = NOTSUPPORTED, // +N/2,\n\t.TAG_VLAN_MASK_EVEN_BIT = {-1,-1,-1,-1,-1,-1,-1,-1,-1},\n\t.TAG_VLAN_MASK_ODD_BIT = {-1,-1,-1,-1,-1,-1,-1,-1,-1},\n\n\t.RESET_VAL = -1,\n\t.RESET_REG = NOTSUPPORTED,\n\t.MODE_VAL = 0,\n\t.MODE_REG = NOTSUPPORTED,\n\n\t.ROUTER_CONTROL_REG = NOTSUPPORTED,\n\t.VLAN_CONTROL_REG = NOTSUPPORTED,\n\t.TAG_VLAN_BIT = -1,\n\t.ROUTER_EN_BIT = -1,\n\t.NUMLAN_GROUPS_MAX = -1,\n\t.NUMLAN_GROUPS_BIT = -1, // {0-2}\n\n\t.NUM_PORTS = 5,\n\t.CPU_PORT = 4,\n\n\t.MII_REGISTER_EN = {0, 18},\n\t.MII_REGISTER_EN_BIT = 7,\n\n\t.update_state = ip175c_update_state,\n\t.set_vlan_mode = ip175c_set_vlan_mode,\n\t.reset = ip175c_reset,\n};\n\n\nstatic int ip175d_update_state(struct ip17xx_state *state);\nstatic int ip175d_set_vlan_mode(struct ip17xx_state *state);\nstatic int ip175d_reset(struct ip17xx_state *state);\n\nstatic const struct register_mappings IP175D = {\n\t.NAME = \"IP175D\",\n\t.MODEL_NO = 0x18,\n\n\t// The IP175D has a completely different interface, so we leave most\n\t// of the registers undefined and switch to different code paths.\n\n\t.VLAN_DEFAULT_TAG_REG = {\n\t\tNOTSUPPORTED,NOTSUPPORTED,NOTSUPPORTED,NOTSUPPORTED,\n\t\tNOTSUPPORTED,NOTSUPPORTED,NOTSUPPORTED,NOTSUPPORTED,\n\t},\n\n\t.ADD_TAG_REG = NOTSUPPORTED,\n\t.REMOVE_TAG_REG = NOTSUPPORTED,\n\n\t.SIMPLE_VLAN_REGISTERS = 0,\n\n\t.VLAN_LOOKUP_REG = NOTSUPPORTED,\n\t.VLAN_LOOKUP_REG_5 = NOTSUPPORTED,\n\t.TAG_VLAN_MASK_REG = NOTSUPPORTED,\n\n\t.RESET_VAL = 0x175D,\n\t.RESET_REG = {20,2},\n\t.MODE_REG = NOTSUPPORTED,\n\n\t.ROUTER_CONTROL_REG = NOTSUPPORTED,\n\t.ROUTER_EN_BIT = -1,\n\t.NUMLAN_GROUPS_BIT = -1,\n\n\t.VLAN_CONTROL_REG = NOTSUPPORTED,\n\t.TAG_VLAN_BIT = -1,\n\n\t.NUM_PORTS = 6,\n\t.CPU_PORT = 5,\n\n\t.MII_REGISTER_EN = NOTSUPPORTED,\n\n\t.update_state = ip175d_update_state,\n\t.set_vlan_mode = ip175d_set_vlan_mode,\n\t.reset = ip175d_reset,\n};\n\nstruct ip17xx_state {\n\tstruct switch_dev dev;\n\tstruct mii_bus *mii_bus;\n\tbool registered;\n\n\tint router_mode;\t\t// ROUTER_EN\n\tint vlan_enabled;\t\t// TAG_VLAN_EN\n\tstruct port_state {\n\t\tu16 pvid;\n\t\tunsigned int shareports;\n\t} ports[MAX_PORTS];\n\tunsigned int add_tag;\n\tunsigned int remove_tag;\n\tint num_vlans;\n\tstruct vlan_state {\n\t\tunsigned int ports;\n\t\tunsigned int tag;\t// VLAN tag (IP175D only)\n\t} vlans[MAX_VLANS];\n\tconst struct register_mappings *regs;\n\treg proc_mii; \t// phy/reg for the low level register access via swconfig\n\n\tchar buf[80];\n};\n\n#define get_state(_dev) container_of((_dev), struct ip17xx_state, dev)\n\nstatic int ip_phy_read(struct ip17xx_state *state, int port, int reg)\n{\n\tint val = mdiobus_read(state->mii_bus, port, reg);\n\tif (val < 0)\n\t\tpr_warn(\"IP17xx: Unable to get MII register %d,%d: error %d\\n\", port, reg, -val);\n#ifdef DUMP_MII_IO\n\telse\n\t\tpr_debug(\"IP17xx: Read MII(%d,%d) -> %04x\\n\", port, reg, val);\n#endif\n\treturn val;\n}\n\nstatic int ip_phy_write(struct ip17xx_state *state, int port, int reg, u16 val)\n{\n\tint err;\n\n#ifdef DUMP_MII_IO\n\tpr_debug(\"IP17xx: Write MII(%d,%d) <- %04x\\n\", port, reg, val);\n#endif\n\terr = mdiobus_write(state->mii_bus, port, reg, val);\n\tif (err < 0)\n\t\tpr_warn(\"IP17xx: Unable to write MII register %d,%d: error %d\\n\", port, reg, -err);\n\treturn err;\n}\n\nstatic int ip_phy_write_masked(struct ip17xx_state *state, int port, int reg, unsigned int mask, unsigned int data)\n{\n\tint val = ip_phy_read(state, port, reg);\n\tif (val < 0)\n\t\treturn 0;\n\treturn ip_phy_write(state, port, reg, (val & ~mask) | data);\n}\n\nstatic int getPhy(struct ip17xx_state *state, reg mii)\n{\n\tif (!REG_SUPP(mii))\n\t\treturn -EFAULT;\n\treturn ip_phy_read(state, mii.p, mii.m);\n}\n\nstatic int setPhy(struct ip17xx_state *state, reg mii, u16 value)\n{\n\tint err;\n\n\tif (!REG_SUPP(mii))\n\t\treturn -EFAULT;\n\terr = ip_phy_write(state, mii.p, mii.m, value);\n\tif (err < 0)\n\t\treturn err;\n\tmdelay(2);\n\tgetPhy(state, mii);\n\treturn 0;\n}\n\n\n/**\n * These two macros are to simplify the mapping of logical bits to the bits in hardware.\n * NOTE: these macros will return if there is an error!\n */\n\n#define GET_PORT_BITS(state, bits, addr, bit_lookup)\t\t\\\n\tdo {\t\t\t\t\t\t\t\\\n\t\tint i, val = getPhy((state), (addr));\t\t\\\n\t\tif (val < 0)\t\t\t\t\t\\\n\t\t\treturn val;\t\t\t\t\\\n\t\t(bits) = 0;\t\t\t\t\t\\\n\t\tfor (i = 0; i < MAX_PORTS; i++) {\t\t\\\n\t\t\tif ((bit_lookup)[i] == -1) continue;\t\\\n\t\t\tif (val & (1<<(bit_lookup)[i]))\t\t\\\n\t\t\t\t(bits) |= (1<<i);\t\t\\\n\t\t}\t\t\t\t\t\t\\\n\t} while (0)\n\n#define SET_PORT_BITS(state, bits, addr, bit_lookup)\t\t\\\n\tdo {\t\t\t\t\t\t\t\\\n\t\tint i, val = getPhy((state), (addr));\t\t\\\n\t\tif (val < 0)\t\t\t\t\t\\\n\t\t\treturn val;\t\t\t\t\\\n\t\tfor (i = 0; i < MAX_PORTS; i++) {\t\t\\\n\t\t\tunsigned int newmask = ((bits)&(1<<i));\t\\\n\t\t\tif ((bit_lookup)[i] == -1) continue;\t\\\n\t\t\tval &= ~(1<<(bit_lookup)[i]);\t\t\\\n\t\t\tval |= ((newmask>>i)<<(bit_lookup)[i]);\t\\\n\t\t}\t\t\t\t\t\t\\\n\t\tval = setPhy((state), (addr), val);\t\t\\\n\t\tif (val < 0)\t\t\t\t\t\\\n\t\t\treturn val;\t\t\t\t\\\n\t} while (0)\n\n\nstatic int get_model(struct ip17xx_state *state)\n{\n\tint id1, id2;\n\tint oui_id, model_no, rev_no, chip_no;\n\n\tid1 = ip_phy_read(state, 0, 2);\n\tid2 = ip_phy_read(state, 0, 3);\n\toui_id = (id1 << 6) | ((id2 >> 10) & 0x3f);\n\tmodel_no = (id2 >> 4) & 0x3f;\n\trev_no = id2 & 0xf;\n\tpr_debug(\"IP17xx: Identified oui=%06x model=%02x rev=%X\\n\", oui_id, model_no, rev_no);\n\n\tif (oui_id != 0x0090c3)  // No other oui_id should have reached us anyway\n\t\treturn -ENODEV;\n\n\tif (model_no == IP175A.MODEL_NO) {\n\t\tstate->regs = &IP175A;\n\t} else if (model_no == IP175C.MODEL_NO) {\n\t\t/*\n\t\t *  Several models share the same model_no:\n\t\t *  178C has more PHYs, so we try whether the device responds to a read from PHY5\n\t\t *  175D has a new chip ID register\n\t\t *  175C has neither\n\t\t */\n\t\tif (ip_phy_read(state, 5, 2) == 0x0243) {\n\t\t\tstate->regs = &IP178C;\n\t\t} else {\n\t\t\tchip_no = ip_phy_read(state, 20, 0);\n\t\t\tpr_debug(\"IP17xx: Chip ID register reads %04x\\n\", chip_no);\n\t\t\tif (chip_no == 0x175d) {\n\t\t\t\tstate->regs = &IP175D;\n\t\t\t} else {\n\t\t\t\tstate->regs = &IP175C;\n\t\t\t}\n\t\t}\n\t} else {\n\t\tpr_warn(\"IP17xx: Found an unknown IC+ switch with model number %02x, revision %X.\\n\", model_no, rev_no);\n\t\treturn -EPERM;\n\t}\n\treturn 0;\n}\n\n/*** Low-level functions for the older models ***/\n\n/** Only set vlan and router flags in the switch **/\nstatic int ip175c_set_flags(struct ip17xx_state *state)\n{\n\tint val;\n\n\tif (!REG_SUPP(state->regs->ROUTER_CONTROL_REG)) {\n\t\treturn 0;\n\t}\n\n\tval = getPhy(state, state->regs->ROUTER_CONTROL_REG);\n\tif (val < 0) {\n\t\treturn val;\n\t}\n\tif (state->regs->ROUTER_EN_BIT >= 0) {\n\t\tif (state->router_mode) {\n\t\t\tval |= (1<<state->regs->ROUTER_EN_BIT);\n\t\t} else {\n\t\t\tval &= (~(1<<state->regs->ROUTER_EN_BIT));\n\t\t}\n\t}\n\tif (state->regs->TAG_VLAN_BIT >= 0) {\n\t\tif (state->vlan_enabled) {\n\t\t\tval |= (1<<state->regs->TAG_VLAN_BIT);\n\t\t} else {\n\t\t\tval &= (~(1<<state->regs->TAG_VLAN_BIT));\n\t\t}\n\t}\n\tif (state->regs->NUMLAN_GROUPS_BIT >= 0) {\n\t\tval &= (~((state->regs->NUMLAN_GROUPS_MAX-1)<<state->regs->NUMLAN_GROUPS_BIT));\n\t\tif (state->num_vlans > state->regs->NUMLAN_GROUPS_MAX) {\n\t\t\tval |= state->regs->NUMLAN_GROUPS_MAX << state->regs->NUMLAN_GROUPS_BIT;\n\t\t} else if (state->num_vlans >= 1) {\n\t\t\tval |= (state->num_vlans-1) << state->regs->NUMLAN_GROUPS_BIT;\n\t\t}\n\t}\n\treturn setPhy(state, state->regs->ROUTER_CONTROL_REG, val);\n}\n\n/** Set all VLAN and port state.  Usually you should call \"correct_vlan_state\" first. **/\nstatic int ip175c_set_state(struct ip17xx_state *state)\n{\n\tint j;\n\tint i;\n\tSET_PORT_BITS(state, state->add_tag,\n\t\t\t\t  state->regs->ADD_TAG_REG, state->regs->ADD_TAG_BIT);\n\tSET_PORT_BITS(state, state->remove_tag,\n\t\t\t\t  state->regs->REMOVE_TAG_REG, state->regs->REMOVE_TAG_BIT);\n\n\tif (REG_SUPP(state->regs->VLAN_LOOKUP_REG)) {\n\t\tfor (j=0; j<state->regs->NUM_PORTS; j++) {\n\t\t\treg addr;\n\t\t\tconst bitnum *bit_lookup = (j%2==0)?\n\t\t\t\tstate->regs->VLAN_LOOKUP_EVEN_BIT:\n\t\t\t\tstate->regs->VLAN_LOOKUP_ODD_BIT;\n\n\t\t\taddr = state->regs->VLAN_LOOKUP_REG;\n\t\t\tif (state->regs->SIMPLE_VLAN_REGISTERS) {\n\t\t\t\taddr.m += j;\n\t\t\t} else {\n\t\t\t\tswitch (j) {\n\t\t\t\tcase 0:\n\t\t\t\tcase 1:\n\t\t\t\t\tbreak;\n\t\t\t\tcase 2:\n\t\t\t\tcase 3:\n\t\t\t\t\taddr.m+=1;\n\t\t\t\t\tbreak;\n\t\t\t\tcase 4:\n\t\t\t\t\taddr.m+=2;\n\t\t\t\t\tbreak;\n\t\t\t\tcase 5:\n\t\t\t\t\taddr = state->regs->VLAN_LOOKUP_REG_5;\n\t\t\t\t\tbreak;\n\t\t\t\tdefault:\n\t\t\t\t\taddr.m = -1; // shouldn't get here, but...\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t}\n\t\t\t//printf(\"shareports for %d is %02X\\n\",j,state->ports[j].shareports);\n\t\t\tif (REG_SUPP(addr)) {\n\t\t\t\tSET_PORT_BITS(state, state->ports[j].shareports, addr, bit_lookup);\n\t\t\t}\n\t\t}\n\t}\n\tif (REG_SUPP(state->regs->TAG_VLAN_MASK_REG)) {\n\t\tfor (j=0; j<MAX_VLANS; j++) {\n\t\t\treg addr = state->regs->TAG_VLAN_MASK_REG;\n\t\t\tconst bitnum *bit_lookup = (j%2==0)?\n\t\t\t\tstate->regs->TAG_VLAN_MASK_EVEN_BIT:\n\t\t\t\tstate->regs->TAG_VLAN_MASK_ODD_BIT;\n\t\t\tunsigned int vlan_mask;\n\t\t\tif (state->regs->SIMPLE_VLAN_REGISTERS) {\n\t\t\t\taddr.m += j;\n\t\t\t} else {\n\t\t\t\taddr.m += j/2;\n\t\t\t}\n\t\t\tvlan_mask = state->vlans[j].ports;\n\t\t\tSET_PORT_BITS(state, vlan_mask, addr, bit_lookup);\n\t\t}\n\t}\n\n\tfor (i=0; i<MAX_PORTS; i++) {\n\t\tif (REG_SUPP(state->regs->VLAN_DEFAULT_TAG_REG[i])) {\n\t\t\tint err = setPhy(state, state->regs->VLAN_DEFAULT_TAG_REG[i],\n\t\t\t\t\tstate->ports[i].pvid);\n\t\t\tif (err < 0) {\n\t\t\t\treturn err;\n\t\t\t}\n\t\t}\n\t}\n\n\treturn ip175c_set_flags(state);\n}\n\n/**\n *  Uses only the VLAN port mask and the add tag mask to generate the other fields:\n *  which ports are part of the same VLAN, removing vlan tags, and VLAN tag ids.\n */\nstatic void ip175c_correct_vlan_state(struct ip17xx_state *state)\n{\n\tint i, j;\n\tstate->num_vlans = 0;\n\tfor (i=0; i<MAX_VLANS; i++) {\n\t\tif (state->vlans[i].ports != 0) {\n\t\t\tstate->num_vlans = i+1; // Hack -- we need to store the \"set\" vlans somewhere...\n\t\t}\n\t}\n\n\tfor (i=0; i<state->regs->NUM_PORTS; i++) {\n\t\tunsigned int portmask = (1<<i);\n\t\tif (!state->vlan_enabled) {\n\t\t\t// Share with everybody!\n\t\t\tstate->ports[i].shareports = (1<<state->regs->NUM_PORTS)-1;\n\t\t\tcontinue;\n\t\t}\n\t\tstate->ports[i].shareports = portmask;\n\t\tfor (j=0; j<MAX_VLANS; j++) {\n\t\t\tif (state->vlans[j].ports & portmask)\n\t\t\t\tstate->ports[i].shareports |= state->vlans[j].ports;\n\t\t}\n\t}\n}\n\nstatic int ip175c_update_state(struct ip17xx_state *state)\n{\n\tip175c_correct_vlan_state(state);\n\treturn ip175c_set_state(state);\n}\n\nstatic int ip175c_set_vlan_mode(struct ip17xx_state *state)\n{\n\treturn ip175c_update_state(state);\n}\n\nstatic int ip175c_reset(struct ip17xx_state *state)\n{\n\tint err;\n\n\tif (REG_SUPP(state->regs->MODE_REG)) {\n\t\terr = setPhy(state, state->regs->MODE_REG, state->regs->MODE_VAL);\n\t\tif (err < 0)\n\t\t\treturn err;\n\t\terr = getPhy(state, state->regs->MODE_REG);\n\t\tif (err < 0)\n\t\t\treturn err;\n\t}\n\n\treturn ip175c_update_state(state);\n}\n\n/*** Low-level functions for IP175D ***/\n\nstatic int ip175d_update_state(struct ip17xx_state *state)\n{\n\tunsigned int filter_mask = 0;\n\tunsigned int ports[16], add[16], rem[16];\n\tint i, j;\n\tint err = 0;\n\n\tfor (i = 0; i < 16; i++) {\n\t\tports[i] = 0;\n\t\tadd[i] = 0;\n\t\trem[i] = 0;\n\t\tif (!state->vlan_enabled) {\n\t\t\terr |= ip_phy_write(state, 22, 14+i, i+1);\t// default tags\n\t\t\tports[i] = 0x3f;\n\t\t\tcontinue;\n\t\t}\n\t\tif (!state->vlans[i].tag) {\n\t\t\t// Reset the filter\n\t\t\terr |= ip_phy_write(state, 22, 14+i, 0);\t// tag\n\t\t\tcontinue;\n\t\t}\n\t\tfilter_mask |= 1 << i;\n\t\terr |= ip_phy_write(state, 22, 14+i, state->vlans[i].tag);\n\t\tports[i] = state->vlans[i].ports;\n\t\tfor (j = 0; j < 6; j++) {\n\t\t\tif (ports[i] & (1 << j)) {\n\t\t\t\tif (state->add_tag & (1 << j))\n\t\t\t\t\tadd[i] |= 1 << j;\n\t\t\t\tif (state->remove_tag & (1 << j))\n\t\t\t\t\trem[i] |= 1 << j;\n\t\t\t}\n\t\t}\n\t}\n\n\t// Port masks, tag adds and removals\n\tfor (i = 0; i < 8; i++) {\n\t\terr |= ip_phy_write(state, 23, i, ports[2*i] | (ports[2*i+1] << 8));\n\t\terr |= ip_phy_write(state, 23, 8+i, add[2*i] | (add[2*i+1] << 8));\n\t\terr |= ip_phy_write(state, 23, 16+i, rem[2*i] | (rem[2*i+1] << 8));\n\t}\n\terr |= ip_phy_write(state, 22, 10, filter_mask);\n\n\t// Default VLAN tag for each port\n\tfor (i = 0; i < 6; i++)\n\t\terr |= ip_phy_write(state, 22, 4+i, state->vlans[state->ports[i].pvid].tag);\n\n\treturn (err ? -EIO : 0);\n}\n\nstatic int ip175d_set_vlan_mode(struct ip17xx_state *state)\n{\n\tint i;\n\tint err = 0;\n\n\tif (state->vlan_enabled) {\n\t\t// VLAN classification rules: tag-based VLANs, use VID to classify,\n\t\t// drop packets that cannot be classified.\n\t\terr |= ip_phy_write_masked(state, 22, 0, 0x3fff, 0x003f);\n\n\t\t// Ingress rules: CFI=1 dropped, null VID is untagged, VID=1 passed,\n\t\t// VID=0xfff discarded, admin both tagged and untagged, ingress\n\t\t// filters enabled.\n\t\terr |= ip_phy_write_masked(state, 22, 1, 0x0fff, 0x0c3f);\n\n\t\t// Egress rules: IGMP processing off, keep VLAN header off\n\t\terr |= ip_phy_write_masked(state, 22, 2, 0x0fff, 0x0000);\n\t} else {\n\t\t// VLAN classification rules: everything off & clear table\n\t\terr |= ip_phy_write_masked(state, 22, 0, 0xbfff, 0x8000);\n\n\t\t// Ingress and egress rules: set to defaults\n\t\terr |= ip_phy_write_masked(state, 22, 1, 0x0fff, 0x0c3f);\n\t\terr |= ip_phy_write_masked(state, 22, 2, 0x0fff, 0x0000);\n\t}\n\n\t// Reset default VLAN for each port to 0\n\tfor (i = 0; i < 6; i++)\n\t\tstate->ports[i].pvid = 0;\n\n\terr |= ip175d_update_state(state);\n\n\treturn (err ? -EIO : 0);\n}\n\nstatic int ip175d_reset(struct ip17xx_state *state)\n{\n\tint err = 0;\n\n\t// Disable the special tagging mode\n\terr |= ip_phy_write_masked(state, 21, 22, 0x0003, 0x0000);\n\n\t// Set 802.1q protocol type\n\terr |= ip_phy_write(state, 22, 3, 0x8100);\n\n\tstate->vlan_enabled = 0;\n\terr |= ip175d_set_vlan_mode(state);\n\n\treturn (err ? -EIO : 0);\n}\n\n/*** High-level functions ***/\n\nstatic int ip17xx_get_enable_vlan(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val)\n{\n\tstruct ip17xx_state *state = get_state(dev);\n\n\tval->value.i = state->vlan_enabled;\n\treturn 0;\n}\n\nstatic void ip17xx_reset_vlan_config(struct ip17xx_state *state)\n{\n\tint i;\n\n\tstate->remove_tag = (state->vlan_enabled ? ((1<<state->regs->NUM_PORTS)-1) : 0x0000);\n\tstate->add_tag = 0x0000;\n\tfor (i = 0; i < MAX_VLANS; i++) {\n\t\tstate->vlans[i].ports = 0x0000;\n\t\tstate->vlans[i].tag = (i ? i : 16);\n\t}\n\tfor (i = 0; i < MAX_PORTS; i++)\n\t\tstate->ports[i].pvid = 0;\n}\n\nstatic int ip17xx_set_enable_vlan(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val)\n{\n\tstruct ip17xx_state *state = get_state(dev);\n\tint enable;\n\n\tenable = val->value.i;\n\tif (state->vlan_enabled == enable) {\n\t\t// Do not change any state.\n\t\treturn 0;\n\t}\n\tstate->vlan_enabled = enable;\n\n\t// Otherwise, if we are switching state, set fields to a known default.\n\tip17xx_reset_vlan_config(state);\n\n\treturn state->regs->set_vlan_mode(state);\n}\n\nstatic int ip17xx_get_ports(struct switch_dev *dev, struct switch_val *val)\n{\n\tstruct ip17xx_state *state = get_state(dev);\n\tint b;\n\tint ind;\n\tunsigned int ports;\n\n\tif (val->port_vlan >= dev->vlans || val->port_vlan < 0)\n\t\treturn -EINVAL;\n\n\tports = state->vlans[val->port_vlan].ports;\n\tb = 0;\n\tind = 0;\n\twhile (b < MAX_PORTS) {\n\t\tif (ports&1) {\n\t\t\tint istagged = ((state->add_tag >> b) & 1);\n\t\t\tval->value.ports[ind].id = b;\n\t\t\tval->value.ports[ind].flags = (istagged << SWITCH_PORT_FLAG_TAGGED);\n\t\t\tind++;\n\t\t}\n\t\tb++;\n\t\tports >>= 1;\n\t}\n\tval->len = ind;\n\n\treturn 0;\n}\n\nstatic int ip17xx_set_ports(struct switch_dev *dev, struct switch_val *val)\n{\n\tstruct ip17xx_state *state = get_state(dev);\n\tint i;\n\n\tif (val->port_vlan >= dev->vlans || val->port_vlan < 0)\n\t\treturn -EINVAL;\n\n\tstate->vlans[val->port_vlan].ports = 0;\n\tfor (i = 0; i < val->len; i++) {\n\t\tunsigned int bitmask = (1<<val->value.ports[i].id);\n\t\tstate->vlans[val->port_vlan].ports |= bitmask;\n\t\tif (val->value.ports[i].flags & (1<<SWITCH_PORT_FLAG_TAGGED)) {\n\t\t\tstate->add_tag |= bitmask;\n\t\t\tstate->remove_tag &= (~bitmask);\n\t\t} else {\n\t\t\tstate->add_tag &= (~bitmask);\n\t\t\tstate->remove_tag |= bitmask;\n\t\t}\n\t}\n\n\treturn state->regs->update_state(state);\n}\n\nstatic int ip17xx_apply(struct switch_dev *dev)\n{\n\tstruct ip17xx_state *state = get_state(dev);\n\n\tif (REG_SUPP(state->regs->MII_REGISTER_EN)) {\n\t\tint val = getPhy(state, state->regs->MII_REGISTER_EN);\n\t\tif (val < 0) {\n\t\t\treturn val;\n\t\t}\n\t\tval |= (1<<state->regs->MII_REGISTER_EN_BIT);\n\t\treturn setPhy(state, state->regs->MII_REGISTER_EN, val);\n\t}\n\treturn 0;\n}\n\nstatic int ip17xx_reset(struct switch_dev *dev)\n{\n\tstruct ip17xx_state *state = get_state(dev);\n\tint i, err;\n\n\tif (REG_SUPP(state->regs->RESET_REG)) {\n\t\terr = setPhy(state, state->regs->RESET_REG, state->regs->RESET_VAL);\n\t\tif (err < 0)\n\t\t\treturn err;\n\t\terr = getPhy(state, state->regs->RESET_REG);\n\n\t\t/*\n\t\t *  Data sheet specifies reset period to be 2 msec.\n\t\t *  (I don't see any mention of the 2ms delay in the IP178C spec, only\n\t\t *  in IP175C, but it can't hurt.)\n\t\t */\n\t\tmdelay(2);\n\t}\n\n\t/* reset switch ports */\n\tfor (i = 0; i < state->regs->NUM_PORTS-1; i++) {\n\t\terr = ip_phy_write(state, i, MII_BMCR, BMCR_RESET);\n\t\tif (err < 0)\n\t\t\treturn err;\n\t}\n\n\tstate->router_mode = 0;\n\tstate->vlan_enabled = 0;\n\tip17xx_reset_vlan_config(state);\n\n\treturn state->regs->reset(state);\n}\n\nstatic int ip17xx_get_tagged(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val)\n{\n\tstruct ip17xx_state *state = get_state(dev);\n\n\tif (state->add_tag & (1<<val->port_vlan)) {\n\t\tif (state->remove_tag & (1<<val->port_vlan))\n\t\t\tval->value.i = 3; // shouldn't ever happen.\n\t\telse\n\t\t\tval->value.i = 1;\n\t} else {\n\t\tif (state->remove_tag & (1<<val->port_vlan))\n\t\t\tval->value.i = 0;\n\t\telse\n\t\t\tval->value.i = 2;\n\t}\n\treturn 0;\n}\n\nstatic int ip17xx_set_tagged(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val)\n{\n\tstruct ip17xx_state *state = get_state(dev);\n\n\tstate->add_tag &= ~(1<<val->port_vlan);\n\tstate->remove_tag &= ~(1<<val->port_vlan);\n\n\tif (val->value.i == 0)\n\t\tstate->remove_tag |= (1<<val->port_vlan);\n\tif (val->value.i == 1)\n\t\tstate->add_tag |= (1<<val->port_vlan);\n\n\treturn state->regs->update_state(state);\n}\n\n/** Get the current phy address */\nstatic int ip17xx_get_phy(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val)\n{\n\tstruct ip17xx_state *state = get_state(dev);\n\n\tval->value.i = state->proc_mii.p;\n\treturn 0;\n}\n\n/** Set a new phy address for low level access to registers */\nstatic int ip17xx_set_phy(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val)\n{\n\tstruct ip17xx_state *state = get_state(dev);\n\tint new_reg = val->value.i;\n\n\tif (new_reg < 0 || new_reg > 31)\n\t\tstate->proc_mii.p = (u16)-1;\n\telse\n\t\tstate->proc_mii.p = (u16)new_reg;\n\treturn 0;\n}\n\n/** Get the current register number */\nstatic int ip17xx_get_reg(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val)\n{\n\tstruct ip17xx_state *state = get_state(dev);\n\n\tval->value.i = state->proc_mii.m;\n\treturn 0;\n}\n\n/** Set a new register address for low level access to registers */\nstatic int ip17xx_set_reg(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val)\n{\n\tstruct ip17xx_state *state = get_state(dev);\n\tint new_reg = val->value.i;\n\n\tif (new_reg < 0 || new_reg > 31)\n\t\tstate->proc_mii.m = (u16)-1;\n\telse\n\t\tstate->proc_mii.m = (u16)new_reg;\n\treturn 0;\n}\n\n/** Get the register content of state->proc_mii */\nstatic int ip17xx_get_val(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val)\n{\n\tstruct ip17xx_state *state = get_state(dev);\n\tint retval = -EINVAL;\n\tif (REG_SUPP(state->proc_mii))\n\t\tretval = getPhy(state, state->proc_mii);\n\n\tif (retval < 0) {\n\t\treturn retval;\n\t} else {\n\t\tval->value.i = retval;\n\t\treturn 0;\n\t}\n}\n\n/** Write a value to the register defined by phy/reg above */\nstatic int ip17xx_set_val(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val)\n{\n\tstruct ip17xx_state *state = get_state(dev);\n\tint myval, err = -EINVAL;\n\n\tmyval = val->value.i;\n\tif (myval <= 0xffff && myval >= 0 && REG_SUPP(state->proc_mii)) {\n\t\terr = setPhy(state, state->proc_mii, (u16)myval);\n\t}\n\treturn err;\n}\n\nstatic int ip17xx_read_name(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val)\n{\n\tstruct ip17xx_state *state = get_state(dev);\n\tval->value.s = state->regs->NAME; // Just a const pointer, won't be freed by swconfig.\n\treturn 0;\n}\n\nstatic int ip17xx_get_tag(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val)\n{\n\tstruct ip17xx_state *state = get_state(dev);\n\tint vlan = val->port_vlan;\n\n\tif (vlan < 0 || vlan >= MAX_VLANS)\n\t\treturn -EINVAL;\n\n\tval->value.i = state->vlans[vlan].tag;\n\treturn 0;\n}\n\nstatic int ip17xx_set_tag(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val)\n{\n\tstruct ip17xx_state *state = get_state(dev);\n\tint vlan = val->port_vlan;\n\tint tag = val->value.i;\n\n\tif (vlan < 0 || vlan >= MAX_VLANS)\n\t\treturn -EINVAL;\n\n\tif (tag < 0 || tag > 4095)\n\t\treturn -EINVAL;\n\n\tstate->vlans[vlan].tag = tag;\n\treturn state->regs->update_state(state);\n}\n\nstatic int ip17xx_set_port_speed(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val)\n{\n\tstruct ip17xx_state *state = get_state(dev);\n\tint nr = val->port_vlan;\n\tint ctrl;\n\tint autoneg;\n\tint speed;\n\tif (val->value.i == 100) {\n\t\tspeed = 1;\n\t\tautoneg = 0;\n\t} else if (val->value.i == 10) {\n\t\tspeed = 0;\n\t\tautoneg = 0;\n\t} else {\n\t\tautoneg = 1;\n\t\tspeed = 1;\n\t}\n\n\t/* Can't set speed for cpu port */\n\tif (nr == state->regs->CPU_PORT)\n\t\treturn -EINVAL;\n\n\tif (nr >= dev->ports || nr < 0)\n\t\treturn -EINVAL;\n\n\tctrl = ip_phy_read(state, nr, 0);\n\tif (ctrl < 0)\n\t\treturn -EIO;\n\n\tctrl &= (~(1<<12));\n\tctrl &= (~(1<<13));\n\tctrl |= (autoneg<<12);\n\tctrl |= (speed<<13);\n\n\treturn ip_phy_write(state, nr, 0, ctrl);\n}\n\nstatic int ip17xx_get_port_speed(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val)\n{\n\tstruct ip17xx_state *state = get_state(dev);\n\tint nr = val->port_vlan;\n\tint speed, status;\n\n\tif (nr == state->regs->CPU_PORT) {\n\t\tval->value.i = 100;\n\t\treturn 0;\n\t}\n\n\tif (nr >= dev->ports || nr < 0)\n\t\treturn -EINVAL;\n\n\tstatus = ip_phy_read(state, nr, 1);\n\tspeed = ip_phy_read(state, nr, 18);\n\tif (status < 0 || speed < 0)\n\t\treturn -EIO;\n\n\tif (status & 4)\n\t\tval->value.i = ((speed & (1<<11)) ? 100 : 10);\n\telse\n\t\tval->value.i = 0;\n\n\treturn 0;\n}\n\nstatic int ip17xx_get_port_status(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val)\n{\n\tstruct ip17xx_state *state = get_state(dev);\n\tint ctrl, speed, status;\n\tint nr = val->port_vlan;\n\tint len;\n\tchar *buf = state->buf; // fixed-length at 80.\n\n\tif (nr == state->regs->CPU_PORT) {\n\t\tsprintf(buf, \"up, 100 Mbps, cpu port\");\n\t\tval->value.s = buf;\n\t\treturn 0;\n\t}\n\n\tif (nr >= dev->ports || nr < 0)\n\t\treturn -EINVAL;\n\n\tctrl = ip_phy_read(state, nr, 0);\n\tstatus = ip_phy_read(state, nr, 1);\n\tspeed = ip_phy_read(state, nr, 18);\n\tif (ctrl < 0 || status < 0 || speed < 0)\n\t\treturn -EIO;\n\n\tif (status & 4)\n\t\tlen = sprintf(buf, \"up, %d Mbps, %s duplex\",\n\t\t\t((speed & (1<<11)) ? 100 : 10),\n\t\t\t((speed & (1<<10)) ? \"full\" : \"half\"));\n\telse\n\t\tlen = sprintf(buf, \"down\");\n\n\tif (ctrl & (1<<12)) {\n\t\tlen += sprintf(buf+len, \", auto-negotiate\");\n\t\tif (!(status & (1<<5)))\n\t\t\tlen += sprintf(buf+len, \" (in progress)\");\n\t} else {\n\t\tlen += sprintf(buf+len, \", fixed speed (%d)\",\n\t\t\t((ctrl & (1<<13)) ? 100 : 10));\n\t}\n\n\tbuf[len] = '\\0';\n\tval->value.s = buf;\n\treturn 0;\n}\n\nstatic int ip17xx_get_pvid(struct switch_dev *dev, int port, int *val)\n{\n\tstruct ip17xx_state *state = get_state(dev);\n\n\t*val = state->ports[port].pvid;\n\treturn 0;\n}\n\nstatic int ip17xx_set_pvid(struct switch_dev *dev, int port, int val)\n{\n\tstruct ip17xx_state *state = get_state(dev);\n\n\tif (val < 0 || val >= MAX_VLANS)\n\t\treturn -EINVAL;\n\n\tstate->ports[port].pvid = val;\n\treturn state->regs->update_state(state);\n}\n\n\nenum Ports {\n\tIP17XX_PORT_STATUS,\n\tIP17XX_PORT_LINK,\n\tIP17XX_PORT_TAGGED,\n\tIP17XX_PORT_PVID,\n};\n\nenum Globals {\n\tIP17XX_ENABLE_VLAN,\n\tIP17XX_GET_NAME,\n\tIP17XX_REGISTER_PHY,\n\tIP17XX_REGISTER_MII,\n\tIP17XX_REGISTER_VALUE,\n\tIP17XX_REGISTER_ERRNO,\n};\n\nenum Vlans {\n\tIP17XX_VLAN_TAG,\n};\n\nstatic const struct switch_attr ip17xx_global[] = {\n\t[IP17XX_ENABLE_VLAN] = {\n\t\t.id = IP17XX_ENABLE_VLAN,\n\t\t.type = SWITCH_TYPE_INT,\n\t\t.name  = \"enable_vlan\",\n\t\t.description = \"Flag to enable or disable VLANs and tagging\",\n\t\t.get  = ip17xx_get_enable_vlan,\n\t\t.set = ip17xx_set_enable_vlan,\n\t},\n\t[IP17XX_GET_NAME] = {\n\t\t.id = IP17XX_GET_NAME,\n\t\t.type = SWITCH_TYPE_STRING,\n\t\t.description = \"Returns the type of IC+ chip.\",\n\t\t.name  = \"name\",\n\t\t.get  = ip17xx_read_name,\n\t\t.set = NULL,\n\t},\n\t/* jal: added for low level debugging etc. */\n\t[IP17XX_REGISTER_PHY] = {\n\t\t.id = IP17XX_REGISTER_PHY,\n\t\t.type = SWITCH_TYPE_INT,\n\t\t.description = \"Direct register access: set PHY (0-4, or 29,30,31)\",\n\t\t.name  = \"phy\",\n\t\t.get  = ip17xx_get_phy,\n\t\t.set = ip17xx_set_phy,\n\t},\n\t[IP17XX_REGISTER_MII] = {\n\t\t.id = IP17XX_REGISTER_MII,\n\t\t.type = SWITCH_TYPE_INT,\n\t\t.description = \"Direct register access: set MII register number (0-31)\",\n\t\t.name  = \"reg\",\n\t\t.get  = ip17xx_get_reg,\n\t\t.set = ip17xx_set_reg,\n\t},\n\t[IP17XX_REGISTER_VALUE] = {\n\t\t.id = IP17XX_REGISTER_VALUE,\n\t\t.type = SWITCH_TYPE_INT,\n\t\t.description = \"Direct register access: read/write to register (0-65535)\",\n\t\t.name  = \"val\",\n\t\t.get  = ip17xx_get_val,\n\t\t.set = ip17xx_set_val,\n\t},\n};\n\nstatic const struct switch_attr ip17xx_vlan[] = {\n\t[IP17XX_VLAN_TAG] = {\n\t\t.id = IP17XX_VLAN_TAG,\n\t\t.type = SWITCH_TYPE_INT,\n\t\t.description = \"VLAN ID (0-4095) [IP175D only]\",\n\t\t.name = \"vid\",\n\t\t.get = ip17xx_get_tag,\n\t\t.set = ip17xx_set_tag,\n\t}\n};\n\nstatic const struct switch_attr ip17xx_port[] = {\n\t[IP17XX_PORT_STATUS] = {\n\t\t.id = IP17XX_PORT_STATUS,\n\t\t.type = SWITCH_TYPE_STRING,\n\t\t.description = \"Returns Detailed port status\",\n\t\t.name  = \"status\",\n\t\t.get  = ip17xx_get_port_status,\n\t\t.set = NULL,\n\t},\n\t[IP17XX_PORT_LINK] = {\n\t\t.id = IP17XX_PORT_LINK,\n\t\t.type = SWITCH_TYPE_INT,\n\t\t.description = \"Link speed. Can write 0 for auto-negotiate, or 10 or 100\",\n\t\t.name  = \"link\",\n\t\t.get  = ip17xx_get_port_speed,\n\t\t.set = ip17xx_set_port_speed,\n\t},\n\t[IP17XX_PORT_TAGGED] = {\n\t\t.id = IP17XX_PORT_LINK,\n\t\t.type = SWITCH_TYPE_INT,\n\t\t.description = \"0 = untag, 1 = add tags, 2 = do not alter (This value is reset if vlans are altered)\",\n\t\t.name  = \"tagged\",\n\t\t.get  = ip17xx_get_tagged,\n\t\t.set = ip17xx_set_tagged,\n\t},\n};\n\nstatic const struct switch_dev_ops ip17xx_ops = {\n\t.attr_global = {\n\t\t.attr = ip17xx_global,\n\t\t.n_attr = ARRAY_SIZE(ip17xx_global),\n\t},\n\t.attr_port = {\n\t\t.attr = ip17xx_port,\n\t\t.n_attr = ARRAY_SIZE(ip17xx_port),\n\t},\n\t.attr_vlan = {\n\t\t.attr = ip17xx_vlan,\n\t\t.n_attr = ARRAY_SIZE(ip17xx_vlan),\n\t},\n\n\t.get_port_pvid = ip17xx_get_pvid,\n\t.set_port_pvid = ip17xx_set_pvid,\n\t.get_vlan_ports = ip17xx_get_ports,\n\t.set_vlan_ports = ip17xx_set_ports,\n\t.apply_config = ip17xx_apply,\n\t.reset_switch = ip17xx_reset,\n};\n\nstatic int ip17xx_probe(struct phy_device *pdev)\n{\n\tstruct ip17xx_state *state;\n\tstruct switch_dev *dev;\n\tint err;\n\n\t/* We only attach to PHY 0, but use all available PHYs */\n\tif (pdev->mdio.addr != 0)\n\t\treturn -ENODEV;\n\n\tstate = kzalloc(sizeof(*state), GFP_KERNEL);\n\tif (!state)\n\t\treturn -ENOMEM;\n\n\tdev = &state->dev;\n\n\tpdev->priv = state;\n\tstate->mii_bus = pdev->mdio.bus;\n\n\terr = get_model(state);\n\tif (err < 0)\n\t\tgoto error;\n\n\tdev->vlans = MAX_VLANS;\n\tdev->cpu_port = state->regs->CPU_PORT;\n\tdev->ports = state->regs->NUM_PORTS;\n\tdev->name = state->regs->NAME;\n\tdev->ops = &ip17xx_ops;\n\n\tpr_info(\"IP17xx: Found %s at %s\\n\", dev->name, dev_name(&pdev->mdio.dev));\n\treturn 0;\n\nerror:\n\tkfree(state);\n\treturn err;\n}\n\nstatic int ip17xx_config_init(struct phy_device *pdev)\n{\n\tstruct ip17xx_state *state = pdev->priv;\n\tstruct net_device *dev = pdev->attached_dev;\n\tint err;\n\n\terr = register_switch(&state->dev, dev);\n\tif (err < 0)\n\t\treturn err;\n\n\tstate->registered = true;\n\tip17xx_reset(&state->dev);\n\treturn 0;\n}\n\nstatic void ip17xx_remove(struct phy_device *pdev)\n{\n\tstruct ip17xx_state *state = pdev->priv;\n\n\tif (state->registered)\n\t\tunregister_switch(&state->dev);\n\tkfree(state);\n}\n\nstatic int ip17xx_config_aneg(struct phy_device *pdev)\n{\n\treturn 0;\n}\n\nstatic int ip17xx_aneg_done(struct phy_device *pdev)\n{\n\treturn 1;\t/* Return any positive value */\n}\n\nstatic int ip17xx_read_status(struct phy_device *pdev)\n{\n\tpdev->speed = SPEED_100;\n\tpdev->duplex = DUPLEX_FULL;\n\tpdev->pause = pdev->asym_pause = 0;\n\tpdev->link = 1;\n\n\treturn 0;\n}\n\nstatic struct phy_driver ip17xx_driver[] = {\n\t{\n\t\t.name\t\t= \"IC+ IP17xx\",\n\t\t.phy_id\t\t= 0x02430c00,\n\t\t.phy_id_mask\t= 0x0ffffc00,\n\t\t.features\t= PHY_BASIC_FEATURES,\n\t\t.probe\t\t= ip17xx_probe,\n\t\t.remove\t\t= ip17xx_remove,\n\t\t.config_init\t= ip17xx_config_init,\n\t\t.config_aneg\t= ip17xx_config_aneg,\n\t\t.aneg_done\t= ip17xx_aneg_done,\n\t\t.read_status\t= ip17xx_read_status,\n\t}\n};\n\nmodule_phy_driver(ip17xx_driver);\n\nMODULE_AUTHOR(\"Patrick Horn <patrick.horn@gmail.com>\");\nMODULE_AUTHOR(\"Felix Fietkau <nbd@nbd.name>\");\nMODULE_AUTHOR(\"Martin Mares <mj@ucw.cz>\");\nMODULE_LICENSE(\"GPL\");\n"
  },
  {
    "path": "target/linux/generic/files/drivers/net/phy/psb6970.c",
    "content": "/*\n * Lantiq PSB6970 (Tantos) Switch driver\n *\n * Copyright (c) 2009,2010 Team Embedded.\n *\n * This program is free software; you can redistribute  it and/or modify it\n * under  the terms of the GNU General Public License v2 as published by the\n * Free Software Foundation.\n *\n * The switch programming done in this driver follows the \n * \"Ethernet Traffic Separation using VLAN\" Application Note as\n * published by Lantiq.\n */\n\n#include <linux/module.h>\n#include <linux/netdevice.h>\n#include <linux/switch.h>\n#include <linux/phy.h>\n#include <linux/version.h>\n\n#define PSB6970_MAX_VLANS\t\t16\n#define PSB6970_NUM_PORTS\t\t7\n#define PSB6970_DEFAULT_PORT_CPU\t6\n#define PSB6970_IS_CPU_PORT(x)\t\t((x) > 4)\n\n#define PHYADDR(_reg)\t\t((_reg >> 5) & 0xff), (_reg & 0x1f)\n\n/* --- Identification --- */\n#define PSB6970_CI0\t\t0x0100\n#define PSB6970_CI0_MASK\t0x000f\n#define PSB6970_CI1\t\t0x0101\n#define PSB6970_CI1_VAL\t\t0x2599\n#define PSB6970_CI1_MASK\t0xffff\n\n/* --- VLAN filter table --- */\n#define PSB6970_VFxL(i)\t\t((i)*2+0x10)\t/* VLAN Filter Low */\n#define PSB6970_VFxL_VV\t\t(1 << 15)\t/* VLAN_Valid */\n\n#define PSB6970_VFxH(i)\t\t((i)*2+0x11)\t/* VLAN Filter High */\n#define PSB6970_VFxH_TM_SHIFT\t7\t\t/* Tagged Member */\n\n/* --- Port registers --- */\n#define PSB6970_EC(p)\t\t((p)*0x20+2)\t/* Extended Control */\n#define PSB6970_EC_IFNTE\t(1 << 1)\t/* Input Force No Tag Enable */\n\n#define PSB6970_PBVM(p)\t\t((p)*0x20+3)\t/* Port Base VLAN Map */\n#define PSB6970_PBVM_VMCE\t(1 << 8)\n#define PSB6970_PBVM_AOVTP\t(1 << 9)\n#define PSB6970_PBVM_VSD\t(1 << 10)\n#define PSB6970_PBVM_VC\t\t(1 << 11)\t/* VID Check with VID table */\n#define PSB6970_PBVM_TBVE\t(1 << 13)\t/* Tag-Based VLAN enable */\n\n#define PSB6970_DVID(p)\t\t((p)*0x20+4)\t/* Default VLAN ID & Priority */\n\nstruct psb6970_priv {\n\tstruct switch_dev dev;\n\tstruct phy_device *phy;\n\tu16 (*read) (struct phy_device* phydev, int reg);\n\tvoid (*write) (struct phy_device* phydev, int reg, u16 val);\n\tstruct mutex reg_mutex;\n\n\t/* all fields below are cleared on reset */\n\tbool vlan;\n\tu16 vlan_id[PSB6970_MAX_VLANS];\n\tu8 vlan_table[PSB6970_MAX_VLANS];\n\tu8 vlan_tagged;\n\tu16 pvid[PSB6970_NUM_PORTS];\n};\n\n#define to_psb6970(_dev) container_of(_dev, struct psb6970_priv, dev)\n\nstatic u16 psb6970_mii_read(struct phy_device *phydev, int reg)\n{\n\tstruct mii_bus *bus = phydev->mdio.bus;\n\n\treturn bus->read(bus, PHYADDR(reg));\n}\n\nstatic void psb6970_mii_write(struct phy_device *phydev, int reg, u16 val)\n{\n\tstruct mii_bus *bus = phydev->mdio.bus;\n\n\tbus->write(bus, PHYADDR(reg), val);\n}\n\nstatic int\npsb6970_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,\n\t\t struct switch_val *val)\n{\n\tstruct psb6970_priv *priv = to_psb6970(dev);\n\tpriv->vlan = !!val->value.i;\n\treturn 0;\n}\n\nstatic int\npsb6970_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,\n\t\t struct switch_val *val)\n{\n\tstruct psb6970_priv *priv = to_psb6970(dev);\n\tval->value.i = priv->vlan;\n\treturn 0;\n}\n\nstatic int psb6970_set_pvid(struct switch_dev *dev, int port, int vlan)\n{\n\tstruct psb6970_priv *priv = to_psb6970(dev);\n\n\t/* make sure no invalid PVIDs get set */\n\tif (vlan >= dev->vlans)\n\t\treturn -EINVAL;\n\n\tpriv->pvid[port] = vlan;\n\treturn 0;\n}\n\nstatic int psb6970_get_pvid(struct switch_dev *dev, int port, int *vlan)\n{\n\tstruct psb6970_priv *priv = to_psb6970(dev);\n\t*vlan = priv->pvid[port];\n\treturn 0;\n}\n\nstatic int\npsb6970_set_vid(struct switch_dev *dev, const struct switch_attr *attr,\n\t\tstruct switch_val *val)\n{\n\tstruct psb6970_priv *priv = to_psb6970(dev);\n\tpriv->vlan_id[val->port_vlan] = val->value.i;\n\treturn 0;\n}\n\nstatic int\npsb6970_get_vid(struct switch_dev *dev, const struct switch_attr *attr,\n\t\tstruct switch_val *val)\n{\n\tstruct psb6970_priv *priv = to_psb6970(dev);\n\tval->value.i = priv->vlan_id[val->port_vlan];\n\treturn 0;\n}\n\nstatic struct switch_attr psb6970_globals[] = {\n\t{\n\t .type = SWITCH_TYPE_INT,\n\t .name = \"enable_vlan\",\n\t .description = \"Enable VLAN mode\",\n\t .set = psb6970_set_vlan,\n\t .get = psb6970_get_vlan,\n\t .max = 1},\n};\n\nstatic struct switch_attr psb6970_port[] = {\n};\n\nstatic struct switch_attr psb6970_vlan[] = {\n\t{\n\t .type = SWITCH_TYPE_INT,\n\t .name = \"vid\",\n\t .description = \"VLAN ID (0-4094)\",\n\t .set = psb6970_set_vid,\n\t .get = psb6970_get_vid,\n\t .max = 4094,\n\t },\n};\n\nstatic int psb6970_get_ports(struct switch_dev *dev, struct switch_val *val)\n{\n\tstruct psb6970_priv *priv = to_psb6970(dev);\n\tu8 ports = priv->vlan_table[val->port_vlan];\n\tint i;\n\n\tval->len = 0;\n\tfor (i = 0; i < PSB6970_NUM_PORTS; i++) {\n\t\tstruct switch_port *p;\n\n\t\tif (!(ports & (1 << i)))\n\t\t\tcontinue;\n\n\t\tp = &val->value.ports[val->len++];\n\t\tp->id = i;\n\t\tif (priv->vlan_tagged & (1 << i))\n\t\t\tp->flags = (1 << SWITCH_PORT_FLAG_TAGGED);\n\t\telse\n\t\t\tp->flags = 0;\n\t}\n\treturn 0;\n}\n\nstatic int psb6970_set_ports(struct switch_dev *dev, struct switch_val *val)\n{\n\tstruct psb6970_priv *priv = to_psb6970(dev);\n\tu8 *vt = &priv->vlan_table[val->port_vlan];\n\tint i, j;\n\n\t*vt = 0;\n\tfor (i = 0; i < val->len; i++) {\n\t\tstruct switch_port *p = &val->value.ports[i];\n\n\t\tif (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED))\n\t\t\tpriv->vlan_tagged |= (1 << p->id);\n\t\telse {\n\t\t\tpriv->vlan_tagged &= ~(1 << p->id);\n\t\t\tpriv->pvid[p->id] = val->port_vlan;\n\n\t\t\t/* make sure that an untagged port does not\n\t\t\t * appear in other vlans */\n\t\t\tfor (j = 0; j < PSB6970_MAX_VLANS; j++) {\n\t\t\t\tif (j == val->port_vlan)\n\t\t\t\t\tcontinue;\n\t\t\t\tpriv->vlan_table[j] &= ~(1 << p->id);\n\t\t\t}\n\t\t}\n\n\t\t*vt |= 1 << p->id;\n\t}\n\treturn 0;\n}\n\nstatic int psb6970_hw_apply(struct switch_dev *dev)\n{\n\tstruct psb6970_priv *priv = to_psb6970(dev);\n\tint i, j;\n\n\tmutex_lock(&priv->reg_mutex);\n\n\tif (priv->vlan) {\n\t\t/* into the vlan translation unit */\n\t\tfor (j = 0; j < PSB6970_MAX_VLANS; j++) {\n\t\t\tu8 vp = priv->vlan_table[j];\n\n\t\t\tif (vp) {\n\t\t\t\tpriv->write(priv->phy, PSB6970_VFxL(j),\n\t\t\t\t\t    PSB6970_VFxL_VV | priv->vlan_id[j]);\n\t\t\t\tpriv->write(priv->phy, PSB6970_VFxH(j),\n\t\t\t\t\t    ((vp & priv->\n\t\t\t\t\t      vlan_tagged) <<\n\t\t\t\t\t     PSB6970_VFxH_TM_SHIFT) | vp);\n\t\t\t} else\t/* clear VLAN Valid flag for unused vlans */\n\t\t\t\tpriv->write(priv->phy, PSB6970_VFxL(j), 0);\n\n\t\t}\n\t}\n\n\t/* update the port destination mask registers and tag settings */\n\tfor (i = 0; i < PSB6970_NUM_PORTS; i++) {\n\t\tint dvid = 1, pbvm = 0x7f | PSB6970_PBVM_VSD, ec = 0;\n\n\t\tif (priv->vlan) {\n\t\t\tec = PSB6970_EC_IFNTE;\n\t\t\tdvid = priv->vlan_id[priv->pvid[i]];\n\t\t\tpbvm |= PSB6970_PBVM_TBVE | PSB6970_PBVM_VMCE;\n\n\t\t\tif ((i << 1) & priv->vlan_tagged)\n\t\t\t\tpbvm |= PSB6970_PBVM_AOVTP | PSB6970_PBVM_VC;\n\t\t}\n\n\t\tpriv->write(priv->phy, PSB6970_PBVM(i), pbvm);\n\n\t\tif (!PSB6970_IS_CPU_PORT(i)) {\n\t\t\tpriv->write(priv->phy, PSB6970_EC(i), ec);\n\t\t\tpriv->write(priv->phy, PSB6970_DVID(i), dvid);\n\t\t}\n\t}\n\n\tmutex_unlock(&priv->reg_mutex);\n\treturn 0;\n}\n\nstatic int psb6970_reset_switch(struct switch_dev *dev)\n{\n\tstruct psb6970_priv *priv = to_psb6970(dev);\n\tint i;\n\n\tmutex_lock(&priv->reg_mutex);\n\n\tmemset(&priv->vlan, 0, sizeof(struct psb6970_priv) -\n\t       offsetof(struct psb6970_priv, vlan));\n\n\tfor (i = 0; i < PSB6970_MAX_VLANS; i++)\n\t\tpriv->vlan_id[i] = i;\n\n\tmutex_unlock(&priv->reg_mutex);\n\n\treturn psb6970_hw_apply(dev);\n}\n\nstatic const struct switch_dev_ops psb6970_ops = {\n\t.attr_global = {\n\t\t\t.attr = psb6970_globals,\n\t\t\t.n_attr = ARRAY_SIZE(psb6970_globals),\n\t\t\t},\n\t.attr_port = {\n\t\t      .attr = psb6970_port,\n\t\t      .n_attr = ARRAY_SIZE(psb6970_port),\n\t\t      },\n\t.attr_vlan = {\n\t\t      .attr = psb6970_vlan,\n\t\t      .n_attr = ARRAY_SIZE(psb6970_vlan),\n\t\t      },\n\t.get_port_pvid = psb6970_get_pvid,\n\t.set_port_pvid = psb6970_set_pvid,\n\t.get_vlan_ports = psb6970_get_ports,\n\t.set_vlan_ports = psb6970_set_ports,\n\t.apply_config = psb6970_hw_apply,\n\t.reset_switch = psb6970_reset_switch,\n};\n\nstatic int psb6970_config_init(struct phy_device *pdev)\n{\n\tstruct psb6970_priv *priv;\n\tstruct net_device *dev = pdev->attached_dev;\n\tstruct switch_dev *swdev;\n\tint ret;\n\n\tpriv = kzalloc(sizeof(struct psb6970_priv), GFP_KERNEL);\n\tif (priv == NULL)\n\t\treturn -ENOMEM;\n\n\tpriv->phy = pdev;\n\n\tif (pdev->mdio.addr == 0)\n\t\tprintk(KERN_INFO \"%s: psb6970 switch driver attached.\\n\",\n\t\t       pdev->attached_dev->name);\n\n\tif (pdev->mdio.addr != 0) {\n\t\tkfree(priv);\n\t\treturn 0;\n\t}\n\n\tlinkmode_zero(pdev->supported);\n\tlinkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, pdev->supported);\n\tlinkmode_copy(pdev->advertising, pdev->supported);\n\n\tmutex_init(&priv->reg_mutex);\n\tpriv->read = psb6970_mii_read;\n\tpriv->write = psb6970_mii_write;\n\n\tpdev->priv = priv;\n\n\tswdev = &priv->dev;\n\tswdev->cpu_port = PSB6970_DEFAULT_PORT_CPU;\n\tswdev->ops = &psb6970_ops;\n\n\tswdev->name = \"Lantiq PSB6970\";\n\tswdev->vlans = PSB6970_MAX_VLANS;\n\tswdev->ports = PSB6970_NUM_PORTS;\n\n\tif ((ret = register_switch(&priv->dev, pdev->attached_dev)) < 0) {\n\t\tkfree(priv);\n\t\tgoto done;\n\t}\n\n\tret = psb6970_reset_switch(&priv->dev);\n\tif (ret) {\n\t\tkfree(priv);\n\t\tgoto done;\n\t}\n\ndone:\n\treturn ret;\n}\n\nstatic int psb6970_read_status(struct phy_device *phydev)\n{\n\tphydev->speed = SPEED_100;\n\tphydev->duplex = DUPLEX_FULL;\n\tphydev->link = 1;\n\n\tphydev->state = PHY_RUNNING;\n\tnetif_carrier_on(phydev->attached_dev);\n\tphydev->adjust_link(phydev->attached_dev);\n\n\treturn 0;\n}\n\nstatic int psb6970_config_aneg(struct phy_device *phydev)\n{\n\treturn 0;\n}\n\nstatic int psb6970_probe(struct phy_device *pdev)\n{\n\treturn 0;\n}\n\nstatic void psb6970_remove(struct phy_device *pdev)\n{\n\tstruct psb6970_priv *priv = pdev->priv;\n\n\tif (!priv)\n\t\treturn;\n\n\tif (pdev->mdio.addr == 0)\n\t\tunregister_switch(&priv->dev);\n\tkfree(priv);\n}\n\nstatic int psb6970_fixup(struct phy_device *dev)\n{\n\tstruct mii_bus *bus = dev->mdio.bus;\n\tu16 reg;\n\n\t/* look for the switch on the bus */\n\treg = bus->read(bus, PHYADDR(PSB6970_CI1)) & PSB6970_CI1_MASK;\n\tif (reg != PSB6970_CI1_VAL)\n\t\treturn 0;\n\n\tdev->phy_id = (reg << 16);\n\tdev->phy_id |= bus->read(bus, PHYADDR(PSB6970_CI0)) & PSB6970_CI0_MASK;\n\n\treturn 0;\n}\n\nstatic struct phy_driver psb6970_driver = {\n\t.name = \"Lantiq PSB6970\",\n\t.phy_id = PSB6970_CI1_VAL << 16,\n\t.phy_id_mask = 0xffff0000,\n\t.features = PHY_BASIC_FEATURES,\n\t.probe = psb6970_probe,\n\t.remove = psb6970_remove,\n\t.config_init = &psb6970_config_init,\n\t.config_aneg = &psb6970_config_aneg,\n\t.read_status = &psb6970_read_status,\n};\n\nint __init psb6970_init(void)\n{\n\tphy_register_fixup_for_id(PHY_ANY_ID, psb6970_fixup);\n\treturn phy_driver_register(&psb6970_driver, THIS_MODULE);\n}\n\nmodule_init(psb6970_init);\n\nvoid __exit psb6970_exit(void)\n{\n\tphy_driver_unregister(&psb6970_driver);\n}\n\nmodule_exit(psb6970_exit);\n\nMODULE_DESCRIPTION(\"Lantiq PSB6970 Switch\");\nMODULE_AUTHOR(\"Ithamar R. Adema <ithamar.adema@team-embedded.nl>\");\nMODULE_LICENSE(\"GPL\");\n"
  },
  {
    "path": "target/linux/generic/files/drivers/net/phy/rtl8306.c",
    "content": "/*\n * rtl8306.c: RTL8306S switch driver\n *\n * Copyright (C) 2009 Felix Fietkau <nbd@nbd.name>\n *\n * This program is free software; you can redistribute it and/or\n * modify it under the terms of the GNU General Public License\n * version 2 as published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n * GNU General Public License for more details.\n */\n\n#include <linux/if.h>\n#include <linux/module.h>\n#include <linux/init.h>\n#include <linux/list.h>\n#include <linux/if_ether.h>\n#include <linux/skbuff.h>\n#include <linux/netdevice.h>\n#include <linux/netlink.h>\n#include <net/genetlink.h>\n#include <linux/switch.h>\n#include <linux/delay.h>\n#include <linux/phy.h>\n#include <linux/version.h>\n\n//#define DEBUG 1\n\n/* Global (PHY0) */\n#define RTL8306_REG_PAGE\t\t16\n#define RTL8306_REG_PAGE_LO\t\t(1 << 15)\n#define RTL8306_REG_PAGE_HI\t\t(1 << 1) /* inverted */\n\n#define RTL8306_NUM_VLANS\t\t16\n#define RTL8306_NUM_PORTS\t\t6\n#define RTL8306_PORT_CPU\t\t5\n#define RTL8306_NUM_PAGES\t\t4\n#define RTL8306_NUM_REGS\t\t32\n\n#define RTL_NAME_S          \"RTL8306S\"\n#define RTL_NAME_SD         \"RTL8306SD\"\n#define RTL_NAME_SDM        \"RTL8306SDM\"\n#define RTL_NAME_UNKNOWN    \"RTL8306(unknown)\"\n\n#define RTL8306_MAGIC\t0x8306\n\nstatic LIST_HEAD(phydevs);\n\nstruct rtl_priv {\n\tstruct list_head list;\n\tstruct switch_dev dev;\n\tint page;\n\tint type;\n\tint do_cpu;\n\tstruct mii_bus *bus;\n\tchar hwname[sizeof(RTL_NAME_UNKNOWN)];\n\tbool fixup;\n};\n\nstruct rtl_phyregs {\n\tint nway;\n\tint speed;\n\tint duplex;\n};\n\n#define to_rtl(_dev) container_of(_dev, struct rtl_priv, dev)\n\nenum {\n\tRTL_TYPE_S,\n\tRTL_TYPE_SD,\n\tRTL_TYPE_SDM,\n};\n\nstruct rtl_reg {\n\tint page;\n\tint phy;\n\tint reg;\n\tint bits;\n\tint shift;\n\tint inverted;\n};\n\n#define RTL_VLAN_REGOFS(name) \\\n\t(RTL_REG_VLAN1_##name - RTL_REG_VLAN0_##name)\n\n#define RTL_PORT_REGOFS(name) \\\n\t(RTL_REG_PORT1_##name - RTL_REG_PORT0_##name)\n\n#define RTL_PORT_REG(id, reg) \\\n\t(RTL_REG_PORT0_##reg + (id * RTL_PORT_REGOFS(reg)))\n\n#define RTL_VLAN_REG(id, reg) \\\n\t(RTL_REG_VLAN0_##reg + (id * RTL_VLAN_REGOFS(reg)))\n\n#define RTL_GLOBAL_REGATTR(reg) \\\n\t.id = RTL_REG_##reg, \\\n\t.type = SWITCH_TYPE_INT, \\\n\t.ofs = 0, \\\n\t.set = rtl_attr_set_int, \\\n\t.get = rtl_attr_get_int\n\n#define RTL_PORT_REGATTR(reg) \\\n\t.id = RTL_REG_PORT0_##reg, \\\n\t.type = SWITCH_TYPE_INT, \\\n\t.ofs = RTL_PORT_REGOFS(reg), \\\n\t.set = rtl_attr_set_port_int, \\\n\t.get = rtl_attr_get_port_int\n\n#define RTL_VLAN_REGATTR(reg) \\\n\t.id = RTL_REG_VLAN0_##reg, \\\n\t.type = SWITCH_TYPE_INT, \\\n\t.ofs = RTL_VLAN_REGOFS(reg), \\\n\t.set = rtl_attr_set_vlan_int, \\\n\t.get = rtl_attr_get_vlan_int\n\nenum rtl_regidx {\n\tRTL_REG_CHIPID,\n\tRTL_REG_CHIPVER,\n\tRTL_REG_CHIPTYPE,\n\tRTL_REG_CPUPORT,\n\n\tRTL_REG_EN_CPUPORT,\n\tRTL_REG_EN_TAG_OUT,\n\tRTL_REG_EN_TAG_CLR,\n\tRTL_REG_EN_TAG_IN,\n\tRTL_REG_TRAP_CPU,\n\tRTL_REG_CPU_LINKUP,\n\tRTL_REG_TRUNK_PORTSEL,\n\tRTL_REG_EN_TRUNK,\n\tRTL_REG_RESET,\n\n\tRTL_REG_VLAN_ENABLE,\n\tRTL_REG_VLAN_FILTER,\n\tRTL_REG_VLAN_TAG_ONLY,\n\tRTL_REG_VLAN_TAG_AWARE,\n#define RTL_VLAN_ENUM(id) \\\n\tRTL_REG_VLAN##id##_VID, \\\n\tRTL_REG_VLAN##id##_PORTMASK\n\tRTL_VLAN_ENUM(0),\n\tRTL_VLAN_ENUM(1),\n\tRTL_VLAN_ENUM(2),\n\tRTL_VLAN_ENUM(3),\n\tRTL_VLAN_ENUM(4),\n\tRTL_VLAN_ENUM(5),\n\tRTL_VLAN_ENUM(6),\n\tRTL_VLAN_ENUM(7),\n\tRTL_VLAN_ENUM(8),\n\tRTL_VLAN_ENUM(9),\n\tRTL_VLAN_ENUM(10),\n\tRTL_VLAN_ENUM(11),\n\tRTL_VLAN_ENUM(12),\n\tRTL_VLAN_ENUM(13),\n\tRTL_VLAN_ENUM(14),\n\tRTL_VLAN_ENUM(15),\n#define RTL_PORT_ENUM(id) \\\n\tRTL_REG_PORT##id##_PVID, \\\n\tRTL_REG_PORT##id##_NULL_VID_REPLACE, \\\n\tRTL_REG_PORT##id##_NON_PVID_DISCARD, \\\n\tRTL_REG_PORT##id##_VID_INSERT, \\\n\tRTL_REG_PORT##id##_TAG_INSERT, \\\n\tRTL_REG_PORT##id##_LINK, \\\n\tRTL_REG_PORT##id##_SPEED, \\\n\tRTL_REG_PORT##id##_NWAY, \\\n\tRTL_REG_PORT##id##_NRESTART, \\\n\tRTL_REG_PORT##id##_DUPLEX, \\\n\tRTL_REG_PORT##id##_RXEN, \\\n\tRTL_REG_PORT##id##_TXEN\n\tRTL_PORT_ENUM(0),\n\tRTL_PORT_ENUM(1),\n\tRTL_PORT_ENUM(2),\n\tRTL_PORT_ENUM(3),\n\tRTL_PORT_ENUM(4),\n\tRTL_PORT_ENUM(5),\n};\n\nstatic const struct rtl_reg rtl_regs[] = {\n\t[RTL_REG_CHIPID]         = { 0, 4, 30, 16,  0, 0 },\n\t[RTL_REG_CHIPVER]        = { 0, 4, 31,  8,  0, 0 },\n\t[RTL_REG_CHIPTYPE]       = { 0, 4, 31,  2,  8, 0 },\n\n\t/* CPU port number */\n\t[RTL_REG_CPUPORT]        = { 2, 4, 21,  3,  0, 0 },\n\t/* Enable CPU port function */\n\t[RTL_REG_EN_CPUPORT]     = { 3, 2, 21,  1, 15, 1 },\n\t/* Enable CPU port tag insertion */\n\t[RTL_REG_EN_TAG_OUT]     = { 3, 2, 21,  1, 12, 0 },\n\t/* Enable CPU port tag removal */\n\t[RTL_REG_EN_TAG_CLR]     = { 3, 2, 21,  1, 11, 0 },\n\t/* Enable CPU port tag checking */\n\t[RTL_REG_EN_TAG_IN]      = { 0, 4, 21,  1,  7, 0 },\n\t[RTL_REG_EN_TRUNK]       = { 0, 0, 19,  1, 11, 1 },\n\t[RTL_REG_TRUNK_PORTSEL]  = { 0, 0, 16,  1,  6, 1 },\n\t[RTL_REG_RESET]          = { 0, 0, 16,  1, 12, 0 },\n\n\t[RTL_REG_TRAP_CPU]       = { 3, 2, 22,  1,  6, 0 },\n\t[RTL_REG_CPU_LINKUP]     = { 0, 6, 22,  1, 15, 0 },\n\n\t[RTL_REG_VLAN_TAG_ONLY]  = { 0, 0, 16,  1,  8, 1 },\n\t[RTL_REG_VLAN_FILTER]    = { 0, 0, 16,  1,  9, 1 },\n\t[RTL_REG_VLAN_TAG_AWARE] = { 0, 0, 16,  1, 10, 1 },\n\t[RTL_REG_VLAN_ENABLE]    = { 0, 0, 18,  1,  8, 1 },\n\n#define RTL_VLAN_REGS(id, phy, page, regofs) \\\n\t[RTL_REG_VLAN##id##_VID] = { page, phy, 25 + regofs, 12, 0, 0 }, \\\n\t[RTL_REG_VLAN##id##_PORTMASK] = { page, phy, 24 + regofs, 6, 0, 0 }\n\tRTL_VLAN_REGS( 0, 0, 0, 0),\n\tRTL_VLAN_REGS( 1, 1, 0, 0),\n\tRTL_VLAN_REGS( 2, 2, 0, 0),\n\tRTL_VLAN_REGS( 3, 3, 0, 0),\n\tRTL_VLAN_REGS( 4, 4, 0, 0),\n\tRTL_VLAN_REGS( 5, 0, 1, 2),\n\tRTL_VLAN_REGS( 6, 1, 1, 2),\n\tRTL_VLAN_REGS( 7, 2, 1, 2),\n\tRTL_VLAN_REGS( 8, 3, 1, 2),\n\tRTL_VLAN_REGS( 9, 4, 1, 2),\n\tRTL_VLAN_REGS(10, 0, 1, 4),\n\tRTL_VLAN_REGS(11, 1, 1, 4),\n\tRTL_VLAN_REGS(12, 2, 1, 4),\n\tRTL_VLAN_REGS(13, 3, 1, 4),\n\tRTL_VLAN_REGS(14, 4, 1, 4),\n\tRTL_VLAN_REGS(15, 0, 1, 6),\n\n#define REG_PORT_SETTING(port, phy) \\\n\t[RTL_REG_PORT##port##_SPEED] = { 0, phy, 0, 1, 13, 0 }, \\\n\t[RTL_REG_PORT##port##_NWAY] = { 0, phy, 0, 1, 12, 0 }, \\\n\t[RTL_REG_PORT##port##_NRESTART] = { 0, phy, 0, 1, 9, 0 }, \\\n\t[RTL_REG_PORT##port##_DUPLEX] = { 0, phy, 0, 1, 8, 0 }, \\\n\t[RTL_REG_PORT##port##_TXEN] = { 0, phy, 24, 1, 11, 0 }, \\\n\t[RTL_REG_PORT##port##_RXEN] = { 0, phy, 24, 1, 10, 0 }, \\\n\t[RTL_REG_PORT##port##_LINK] = { 0, phy, 1, 1, 2, 0 }, \\\n\t[RTL_REG_PORT##port##_NULL_VID_REPLACE] = { 0, phy, 22, 1, 12, 0 }, \\\n\t[RTL_REG_PORT##port##_NON_PVID_DISCARD] = { 0, phy, 22, 1, 11, 0 }, \\\n\t[RTL_REG_PORT##port##_VID_INSERT] = { 0, phy, 22, 2, 9, 0 }, \\\n\t[RTL_REG_PORT##port##_TAG_INSERT] = { 0, phy, 22, 2, 0, 0 }\n\n\tREG_PORT_SETTING(0, 0),\n\tREG_PORT_SETTING(1, 1),\n\tREG_PORT_SETTING(2, 2),\n\tREG_PORT_SETTING(3, 3),\n\tREG_PORT_SETTING(4, 4),\n\tREG_PORT_SETTING(5, 6),\n\n#define REG_PORT_PVID(phy, page, regofs) \\\n\t{ page, phy, 24 + regofs, 4, 12, 0 }\n\t[RTL_REG_PORT0_PVID] = REG_PORT_PVID(0, 0, 0),\n\t[RTL_REG_PORT1_PVID] = REG_PORT_PVID(1, 0, 0),\n\t[RTL_REG_PORT2_PVID] = REG_PORT_PVID(2, 0, 0),\n\t[RTL_REG_PORT3_PVID] = REG_PORT_PVID(3, 0, 0),\n\t[RTL_REG_PORT4_PVID] = REG_PORT_PVID(4, 0, 0),\n\t[RTL_REG_PORT5_PVID] = REG_PORT_PVID(0, 1, 2),\n};\n\n\nstatic inline void\nrtl_set_page(struct rtl_priv *priv, unsigned int page)\n{\n\tstruct mii_bus *bus = priv->bus;\n\tu16 pgsel;\n\n\tif (priv->fixup)\n\t\treturn;\n\n\tif (priv->page == page)\n\t\treturn;\n\n\tBUG_ON(page > RTL8306_NUM_PAGES);\n\tpgsel = bus->read(bus, 0, RTL8306_REG_PAGE);\n\tpgsel &= ~(RTL8306_REG_PAGE_LO | RTL8306_REG_PAGE_HI);\n\tif (page & (1 << 0))\n\t\tpgsel |= RTL8306_REG_PAGE_LO;\n\tif (!(page & (1 << 1))) /* bit is inverted */\n\t\tpgsel |= RTL8306_REG_PAGE_HI;\n\tbus->write(bus, 0, RTL8306_REG_PAGE, pgsel);\n}\n\nstatic inline int\nrtl_w16(struct switch_dev *dev, unsigned int page, unsigned int phy, unsigned int reg, u16 val)\n{\n\tstruct rtl_priv *priv = to_rtl(dev);\n\tstruct mii_bus *bus = priv->bus;\n\n\trtl_set_page(priv, page);\n\tbus->write(bus, phy, reg, val);\n\tbus->read(bus, phy, reg); /* flush */\n\treturn 0;\n}\n\nstatic inline int\nrtl_r16(struct switch_dev *dev, unsigned int page, unsigned int phy, unsigned int reg)\n{\n\tstruct rtl_priv *priv = to_rtl(dev);\n\tstruct mii_bus *bus = priv->bus;\n\n\trtl_set_page(priv, page);\n\treturn bus->read(bus, phy, reg);\n}\n\nstatic inline u16\nrtl_rmw(struct switch_dev *dev, unsigned int page, unsigned int phy, unsigned int reg, u16 mask, u16 val)\n{\n\tstruct rtl_priv *priv = to_rtl(dev);\n\tstruct mii_bus *bus = priv->bus;\n\tu16 r;\n\n\trtl_set_page(priv, page);\n\tr = bus->read(bus, phy, reg);\n\tr &= ~mask;\n\tr |= val;\n\tbus->write(bus, phy, reg, r);\n\treturn bus->read(bus, phy, reg); /* flush */\n}\n\n\nstatic inline int\nrtl_get(struct switch_dev *dev, enum rtl_regidx s)\n{\n\tconst struct rtl_reg *r = &rtl_regs[s];\n\tu16 val;\n\n\tBUG_ON(s >= ARRAY_SIZE(rtl_regs));\n\tif (r->bits == 0) /* unimplemented */\n\t\treturn 0;\n\n\tval = rtl_r16(dev, r->page, r->phy, r->reg);\n\n\tif (r->shift > 0)\n\t\tval >>= r->shift;\n\n\tif (r->inverted)\n\t\tval = ~val;\n\n\tval &= (1 << r->bits) - 1;\n\n\treturn val;\n}\n\nstatic int\nrtl_set(struct switch_dev *dev, enum rtl_regidx s, unsigned int val)\n{\n\tconst struct rtl_reg *r = &rtl_regs[s];\n\tu16 mask = 0xffff;\n\n\tBUG_ON(s >= ARRAY_SIZE(rtl_regs));\n\n\tif (r->bits == 0) /* unimplemented */\n\t\treturn 0;\n\n\tif (r->shift > 0)\n\t\tval <<= r->shift;\n\n\tif (r->inverted)\n\t\tval = ~val;\n\n\tif (r->bits != 16) {\n\t\tmask = (1 << r->bits) - 1;\n\t\tmask <<= r->shift;\n\t}\n\tval &= mask;\n\treturn rtl_rmw(dev, r->page, r->phy, r->reg, mask, val);\n}\n\nstatic void\nrtl_phy_save(struct switch_dev *dev, int port, struct rtl_phyregs *regs)\n{\n\tregs->nway = rtl_get(dev, RTL_PORT_REG(port, NWAY));\n\tregs->speed = rtl_get(dev, RTL_PORT_REG(port, SPEED));\n\tregs->duplex = rtl_get(dev, RTL_PORT_REG(port, DUPLEX));\n}\n\nstatic void\nrtl_phy_restore(struct switch_dev *dev, int port, struct rtl_phyregs *regs)\n{\n\trtl_set(dev, RTL_PORT_REG(port, NWAY), regs->nway);\n\trtl_set(dev, RTL_PORT_REG(port, SPEED), regs->speed);\n\trtl_set(dev, RTL_PORT_REG(port, DUPLEX), regs->duplex);\n}\n\nstatic void\nrtl_port_set_enable(struct switch_dev *dev, int port, int enabled)\n{\n\trtl_set(dev, RTL_PORT_REG(port, RXEN), enabled);\n\trtl_set(dev, RTL_PORT_REG(port, TXEN), enabled);\n\n\tif ((port >= 5) || !enabled)\n\t\treturn;\n\n\t/* restart autonegotiation if enabled */\n\trtl_set(dev, RTL_PORT_REG(port, NRESTART), 1);\n}\n\nstatic int\nrtl_hw_apply(struct switch_dev *dev)\n{\n\tint i;\n\tint trunk_en, trunk_psel;\n\tstruct rtl_phyregs port5;\n\n\trtl_phy_save(dev, 5, &port5);\n\n\t/* disable rx/tx from PHYs */\n\tfor (i = 0; i < RTL8306_NUM_PORTS - 1; i++) {\n\t\trtl_port_set_enable(dev, i, 0);\n\t}\n\n\t/* save trunking status */\n\ttrunk_en = rtl_get(dev, RTL_REG_EN_TRUNK);\n\ttrunk_psel = rtl_get(dev, RTL_REG_TRUNK_PORTSEL);\n\n\t/* trunk port 3 and 4\n\t * XXX: Big WTF, but RealTek seems to do it */\n\trtl_set(dev, RTL_REG_EN_TRUNK, 1);\n\trtl_set(dev, RTL_REG_TRUNK_PORTSEL, 1);\n\n\t/* execute the software reset */\n\trtl_set(dev, RTL_REG_RESET, 1);\n\n\t/* wait for the reset to complete,\n\t * but don't wait for too long */\n\tfor (i = 0; i < 10; i++) {\n\t\tif (rtl_get(dev, RTL_REG_RESET) == 0)\n\t\t\tbreak;\n\n\t\tmsleep(1);\n\t}\n\n\t/* enable rx/tx from PHYs */\n\tfor (i = 0; i < RTL8306_NUM_PORTS - 1; i++) {\n\t\trtl_port_set_enable(dev, i, 1);\n\t}\n\n\t/* restore trunking settings */\n\trtl_set(dev, RTL_REG_EN_TRUNK, trunk_en);\n\trtl_set(dev, RTL_REG_TRUNK_PORTSEL, trunk_psel);\n\trtl_phy_restore(dev, 5, &port5);\n\n\trtl_set(dev, RTL_REG_CPU_LINKUP, 1);\n\n\treturn 0;\n}\n\nstatic void\nrtl_hw_init(struct switch_dev *dev)\n{\n\tstruct rtl_priv *priv = to_rtl(dev);\n\tint cpu_mask = 1 << dev->cpu_port;\n\tint i;\n\n\trtl_set(dev, RTL_REG_VLAN_ENABLE, 0);\n\trtl_set(dev, RTL_REG_VLAN_FILTER, 0);\n\trtl_set(dev, RTL_REG_EN_TRUNK, 0);\n\trtl_set(dev, RTL_REG_TRUNK_PORTSEL, 0);\n\n\t/* initialize cpu port settings */\n\tif (priv->do_cpu) {\n\t\trtl_set(dev, RTL_REG_CPUPORT, dev->cpu_port);\n\t\trtl_set(dev, RTL_REG_EN_CPUPORT, 1);\n\t} else {\n\t\trtl_set(dev, RTL_REG_CPUPORT, 7);\n\t\trtl_set(dev, RTL_REG_EN_CPUPORT, 0);\n\t}\n\trtl_set(dev, RTL_REG_EN_TAG_OUT, 0);\n\trtl_set(dev, RTL_REG_EN_TAG_IN, 0);\n\trtl_set(dev, RTL_REG_EN_TAG_CLR, 0);\n\n\t/* reset all vlans */\n\tfor (i = 0; i < RTL8306_NUM_VLANS; i++) {\n\t\trtl_set(dev, RTL_VLAN_REG(i, VID), i);\n\t\trtl_set(dev, RTL_VLAN_REG(i, PORTMASK), 0);\n\t}\n\n\t/* default to port isolation */\n\tfor (i = 0; i < RTL8306_NUM_PORTS; i++) {\n\t\tunsigned long mask;\n\n\t\tif ((1 << i) == cpu_mask)\n\t\t\tmask = ((1 << RTL8306_NUM_PORTS) - 1) & ~cpu_mask; /* all bits set */\n\t\telse\n\t\t\tmask = cpu_mask | (1 << i);\n\n\t\trtl_set(dev, RTL_VLAN_REG(i, PORTMASK), mask);\n\t\trtl_set(dev, RTL_PORT_REG(i, PVID), i);\n\t\trtl_set(dev, RTL_PORT_REG(i, NULL_VID_REPLACE), 1);\n\t\trtl_set(dev, RTL_PORT_REG(i, VID_INSERT), 1);\n\t\trtl_set(dev, RTL_PORT_REG(i, TAG_INSERT), 3);\n\t}\n\trtl_hw_apply(dev);\n}\n\n#ifdef DEBUG\nstatic int\nrtl_set_use_cpuport(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val)\n{\n\tstruct rtl_priv *priv = to_rtl(dev);\n\tpriv->do_cpu = val->value.i;\n\trtl_hw_init(dev);\n\treturn 0;\n}\n\nstatic int\nrtl_get_use_cpuport(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val)\n{\n\tstruct rtl_priv *priv = to_rtl(dev);\n\tval->value.i = priv->do_cpu;\n\treturn 0;\n}\n\nstatic int\nrtl_set_cpuport(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val)\n{\n\tdev->cpu_port = val->value.i;\n\trtl_hw_init(dev);\n\treturn 0;\n}\n\nstatic int\nrtl_get_cpuport(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val)\n{\n\tval->value.i = dev->cpu_port;\n\treturn 0;\n}\n#endif\n\nstatic int\nrtl_reset(struct switch_dev *dev)\n{\n\trtl_hw_init(dev);\n\treturn 0;\n}\n\nstatic int\nrtl_attr_set_int(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val)\n{\n\tint idx = attr->id + (val->port_vlan * attr->ofs);\n\tstruct rtl_phyregs port;\n\n\tif (attr->id >= ARRAY_SIZE(rtl_regs))\n\t\treturn -EINVAL;\n\n\tif ((attr->max > 0) && (val->value.i > attr->max))\n\t\treturn -EINVAL;\n\n\t/* access to phy register 22 on port 4/5\n\t * needs phy status save/restore */\n\tif ((val->port_vlan > 3) &&\n\t\t(rtl_regs[idx].reg == 22) &&\n\t\t(rtl_regs[idx].page == 0)) {\n\n\t\trtl_phy_save(dev, val->port_vlan, &port);\n\t\trtl_set(dev, idx, val->value.i);\n\t\trtl_phy_restore(dev, val->port_vlan, &port);\n\t} else {\n\t\trtl_set(dev, idx, val->value.i);\n\t}\n\n\treturn 0;\n}\n\nstatic int\nrtl_attr_get_int(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val)\n{\n\tint idx = attr->id + (val->port_vlan * attr->ofs);\n\n\tif (idx >= ARRAY_SIZE(rtl_regs))\n\t\treturn -EINVAL;\n\n\tval->value.i = rtl_get(dev, idx);\n\treturn 0;\n}\n\nstatic int\nrtl_attr_set_port_int(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val)\n{\n\tif (val->port_vlan >= RTL8306_NUM_PORTS)\n\t\treturn -EINVAL;\n\n\treturn rtl_attr_set_int(dev, attr, val);\n}\n\nstatic int\nrtl_attr_get_port_int(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val)\n{\n\tif (val->port_vlan >= RTL8306_NUM_PORTS)\n\t\treturn -EINVAL;\n\treturn rtl_attr_get_int(dev, attr, val);\n}\n\nstatic int \nrtl_get_port_link(struct switch_dev *dev, int port, struct switch_port_link *link)\n{\n\tif (port >= RTL8306_NUM_PORTS)\n\t\treturn -EINVAL;\n\n\t/* in case the link changes from down to up, the register is only updated on read */\n\tlink->link = rtl_get(dev, RTL_PORT_REG(port, LINK));\n\tif (!link->link)\n\t\tlink->link = rtl_get(dev, RTL_PORT_REG(port, LINK));\n\n\tif (!link->link)\n\t\treturn 0;\n\n\tlink->duplex = rtl_get(dev, RTL_PORT_REG(port, DUPLEX));\n\tlink->aneg = rtl_get(dev, RTL_PORT_REG(port, NWAY));\n\n\tif (rtl_get(dev, RTL_PORT_REG(port, SPEED)))\n\t\tlink->speed = SWITCH_PORT_SPEED_100;\n\telse\n\t\tlink->speed = SWITCH_PORT_SPEED_10;\n\n\treturn 0;\n}\n\nstatic int\nrtl_attr_set_vlan_int(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val)\n{\n\tif (val->port_vlan >= dev->vlans)\n\t\treturn -EINVAL;\n\n\treturn rtl_attr_set_int(dev, attr, val);\n}\n\nstatic int\nrtl_attr_get_vlan_int(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val)\n{\n\tif (val->port_vlan >= dev->vlans)\n\t\treturn -EINVAL;\n\n\treturn rtl_attr_get_int(dev, attr, val);\n}\n\nstatic int\nrtl_get_ports(struct switch_dev *dev, struct switch_val *val)\n{\n\tunsigned int i, mask;\n\n\tmask = rtl_get(dev, RTL_VLAN_REG(val->port_vlan, PORTMASK));\n\tfor (i = 0; i < RTL8306_NUM_PORTS; i++) {\n\t\tstruct switch_port *port;\n\n\t\tif (!(mask & (1 << i)))\n\t\t\tcontinue;\n\n\t\tport = &val->value.ports[val->len];\n\t\tport->id = i;\n\t\tif (rtl_get(dev, RTL_PORT_REG(i, TAG_INSERT)) == 2 || i == dev->cpu_port)\n\t\t\tport->flags = (1 << SWITCH_PORT_FLAG_TAGGED);\n\t\tval->len++;\n\t}\n\n\treturn 0;\n}\n\nstatic int\nrtl_set_vlan(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val)\n{\n\tstruct rtl_priv *priv = to_rtl(dev);\n\tstruct rtl_phyregs port;\n\tint en = val->value.i;\n\tint i;\n\n\trtl_set(dev, RTL_REG_EN_TAG_OUT, en && priv->do_cpu);\n\trtl_set(dev, RTL_REG_EN_TAG_IN, en && priv->do_cpu);\n\trtl_set(dev, RTL_REG_EN_TAG_CLR, en && priv->do_cpu);\n\trtl_set(dev, RTL_REG_VLAN_TAG_AWARE, en);\n\tif (en)\n\t\trtl_set(dev, RTL_REG_VLAN_FILTER, en);\n\n\tfor (i = 0; i < RTL8306_NUM_PORTS; i++) {\n\t\tif (i > 3)\n\t\t\trtl_phy_save(dev, val->port_vlan, &port);\n\t\trtl_set(dev, RTL_PORT_REG(i, NULL_VID_REPLACE), 1);\n\t\trtl_set(dev, RTL_PORT_REG(i, VID_INSERT), (en ? (i == dev->cpu_port ? 0 : 1) : 1));\n\t\trtl_set(dev, RTL_PORT_REG(i, TAG_INSERT), (en ? (i == dev->cpu_port ? 2 : 1) : 3));\n\t\tif (i > 3)\n\t\t\trtl_phy_restore(dev, val->port_vlan, &port);\n\t}\n\trtl_set(dev, RTL_REG_VLAN_ENABLE, en);\n\n\treturn 0;\n}\n\nstatic int\nrtl_get_vlan(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val)\n{\n\tval->value.i = rtl_get(dev, RTL_REG_VLAN_ENABLE);\n\treturn 0;\n}\n\nstatic int\nrtl_set_ports(struct switch_dev *dev, struct switch_val *val)\n{\n\tunsigned int mask = 0;\n\tunsigned int oldmask;\n\tint i;\n\n\tfor(i = 0; i < val->len; i++)\n\t{\n\t\tstruct switch_port *port = &val->value.ports[i];\n\t\tbool tagged = false;\n\n\t\tmask |= (1 << port->id);\n\n\t\tif (port->id == dev->cpu_port)\n\t\t\tcontinue;\n\n\t\tif ((i == dev->cpu_port) ||\n\t\t\t(port->flags & (1 << SWITCH_PORT_FLAG_TAGGED)))\n\t\t\ttagged = true;\n\n\t\t/* fix up PVIDs for added ports */\n\t\tif (!tagged)\n\t\t\trtl_set(dev, RTL_PORT_REG(port->id, PVID), val->port_vlan);\n\n\t\trtl_set(dev, RTL_PORT_REG(port->id, NON_PVID_DISCARD), (tagged ? 0 : 1));\n\t\trtl_set(dev, RTL_PORT_REG(port->id, VID_INSERT), (tagged ? 0 : 1));\n\t\trtl_set(dev, RTL_PORT_REG(port->id, TAG_INSERT), (tagged ? 2 : 1));\n\t}\n\n\toldmask = rtl_get(dev, RTL_VLAN_REG(val->port_vlan, PORTMASK));\n\trtl_set(dev, RTL_VLAN_REG(val->port_vlan, PORTMASK), mask);\n\n\t/* fix up PVIDs for removed ports, default to last vlan */\n\toldmask &= ~mask;\n\tfor (i = 0; i < RTL8306_NUM_PORTS; i++) {\n\t\tif (!(oldmask & (1 << i)))\n\t\t\tcontinue;\n\n\t\tif (i == dev->cpu_port)\n\t\t\tcontinue;\n\n\t\tif (rtl_get(dev, RTL_PORT_REG(i, PVID)) == val->port_vlan)\n\t\t\trtl_set(dev, RTL_PORT_REG(i, PVID), dev->vlans - 1);\n\t}\n\n\treturn 0;\n}\n\nstatic struct switch_attr rtl_globals[] = {\n\t{\n\t\t.type = SWITCH_TYPE_INT,\n\t\t.name = \"enable_vlan\",\n\t\t.description = \"Enable VLAN mode\",\n\t\t.max = 1,\n\t\t.set = rtl_set_vlan,\n\t\t.get = rtl_get_vlan,\n\t},\n\t{\n\t\tRTL_GLOBAL_REGATTR(EN_TRUNK),\n\t\t.name = \"trunk\",\n\t\t.description = \"Enable port trunking\",\n\t\t.max = 1,\n\t},\n\t{\n\t\tRTL_GLOBAL_REGATTR(TRUNK_PORTSEL),\n\t\t.name = \"trunk_sel\",\n\t\t.description = \"Select ports for trunking (0: 0,1 - 1: 3,4)\",\n\t\t.max = 1,\n\t},\n#ifdef DEBUG\n\t{\n\t\tRTL_GLOBAL_REGATTR(VLAN_FILTER),\n\t\t.name = \"vlan_filter\",\n\t\t.description = \"Filter incoming packets for allowed VLANS\",\n\t\t.max = 1,\n\t},\n\t{\n\t\t.type = SWITCH_TYPE_INT,\n\t\t.name = \"cpuport\",\n\t\t.description = \"CPU Port\",\n\t\t.set = rtl_set_cpuport,\n\t\t.get = rtl_get_cpuport,\n\t\t.max = RTL8306_NUM_PORTS,\n\t},\n\t{\n\t\t.type = SWITCH_TYPE_INT,\n\t\t.name = \"use_cpuport\",\n\t\t.description = \"CPU Port handling flag\",\n\t\t.set = rtl_set_use_cpuport,\n\t\t.get = rtl_get_use_cpuport,\n\t\t.max = RTL8306_NUM_PORTS,\n\t},\n\t{\n\t\tRTL_GLOBAL_REGATTR(TRAP_CPU),\n\t\t.name = \"trap_cpu\",\n\t\t.description = \"VLAN trap to CPU\",\n\t\t.max = 1,\n\t},\n\t{\n\t\tRTL_GLOBAL_REGATTR(VLAN_TAG_AWARE),\n\t\t.name = \"vlan_tag_aware\",\n\t\t.description = \"Enable VLAN tag awareness\",\n\t\t.max = 1,\n\t},\n\t{\n\t\tRTL_GLOBAL_REGATTR(VLAN_TAG_ONLY),\n\t\t.name = \"tag_only\",\n\t\t.description = \"Only accept tagged packets\",\n\t\t.max = 1,\n\t},\n#endif\n};\nstatic struct switch_attr rtl_port[] = {\n\t{\n\t\tRTL_PORT_REGATTR(PVID),\n\t\t.name = \"pvid\",\n\t\t.description = \"Port VLAN ID\",\n\t\t.max = RTL8306_NUM_VLANS - 1,\n\t},\n#ifdef DEBUG\n\t{\n\t\tRTL_PORT_REGATTR(NULL_VID_REPLACE),\n\t\t.name = \"null_vid\",\n\t\t.description = \"NULL VID gets replaced by port default vid\",\n\t\t.max = 1,\n\t},\n\t{\n\t\tRTL_PORT_REGATTR(NON_PVID_DISCARD),\n\t\t.name = \"non_pvid_discard\",\n\t\t.description = \"discard packets with VID != PVID\",\n\t\t.max = 1,\n\t},\n\t{\n\t\tRTL_PORT_REGATTR(VID_INSERT),\n\t\t.name = \"vid_insert_remove\",\n\t\t.description = \"how should the switch insert and remove vids ?\",\n\t\t.max = 3,\n\t},\n\t{\n\t\tRTL_PORT_REGATTR(TAG_INSERT),\n\t\t.name = \"tag_insert\",\n\t\t.description = \"tag insertion handling\",\n\t\t.max = 3,\n\t},\n#endif\n};\n\nstatic struct switch_attr rtl_vlan[] = {\n\t{\n\t\tRTL_VLAN_REGATTR(VID),\n\t\t.name = \"vid\",\n\t\t.description = \"VLAN ID (1-4095)\",\n\t\t.max = 4095,\n\t},\n};\n\nstatic const struct switch_dev_ops rtl8306_ops = {\n\t.attr_global = {\n\t\t.attr = rtl_globals,\n\t\t.n_attr = ARRAY_SIZE(rtl_globals),\n\t},\n\t.attr_port = {\n\t\t.attr = rtl_port,\n\t\t.n_attr = ARRAY_SIZE(rtl_port),\n\t},\n\t.attr_vlan = {\n\t\t.attr = rtl_vlan,\n\t\t.n_attr = ARRAY_SIZE(rtl_vlan),\n\t},\n\n\t.get_vlan_ports = rtl_get_ports,\n\t.set_vlan_ports = rtl_set_ports,\n\t.apply_config = rtl_hw_apply,\n\t.reset_switch = rtl_reset,\n\t.get_port_link = rtl_get_port_link,\n};\n\nstatic int\nrtl8306_config_init(struct phy_device *pdev)\n{\n\tstruct net_device *netdev = pdev->attached_dev;\n\tstruct rtl_priv *priv = pdev->priv;\n\tstruct switch_dev *dev = &priv->dev;\n\tstruct switch_val val;\n\tunsigned int chipid, chipver, chiptype;\n\tint err;\n\n\t/* Only init the switch for the primary PHY */\n\tif (pdev->mdio.addr != 0)\n\t\treturn 0;\n\n\tval.value.i = 1;\n\tpriv->dev.cpu_port = RTL8306_PORT_CPU;\n\tpriv->dev.ports = RTL8306_NUM_PORTS;\n\tpriv->dev.vlans = RTL8306_NUM_VLANS;\n\tpriv->dev.ops = &rtl8306_ops;\n\tpriv->do_cpu = 0;\n\tpriv->page = -1;\n\tpriv->bus = pdev->mdio.bus;\n\n\tchipid = rtl_get(dev, RTL_REG_CHIPID);\n\tchipver = rtl_get(dev, RTL_REG_CHIPVER);\n\tchiptype = rtl_get(dev, RTL_REG_CHIPTYPE);\n\tswitch(chiptype) {\n\tcase 0:\n\tcase 2:\n\t\tstrncpy(priv->hwname, RTL_NAME_S, sizeof(priv->hwname));\n\t\tpriv->type = RTL_TYPE_S;\n\t\tbreak;\n\tcase 1:\n\t\tstrncpy(priv->hwname, RTL_NAME_SD, sizeof(priv->hwname));\n\t\tpriv->type = RTL_TYPE_SD;\n\t\tbreak;\n\tcase 3:\n\t\tstrncpy(priv->hwname, RTL_NAME_SDM, sizeof(priv->hwname));\n\t\tpriv->type = RTL_TYPE_SDM;\n\t\tbreak;\n\tdefault:\n\t\tstrncpy(priv->hwname, RTL_NAME_UNKNOWN, sizeof(priv->hwname));\n\t\tbreak;\n\t}\n\n\tdev->name = priv->hwname;\n\trtl_hw_init(dev);\n\n\tprintk(KERN_INFO \"Registering %s switch with Chip ID: 0x%04x, version: 0x%04x\\n\", priv->hwname, chipid, chipver);\n\n\terr = register_switch(dev, netdev);\n\tif (err < 0) {\n\t\tkfree(priv);\n\t\treturn err;\n\t}\n\n\treturn 0;\n}\n\n\nstatic int\nrtl8306_fixup(struct phy_device *pdev)\n{\n\tstruct rtl_priv priv;\n\tu16 chipid;\n\n\t/* Attach to primary LAN port and WAN port */\n\tif (pdev->mdio.addr != 0 && pdev->mdio.addr != 4)\n\t\treturn 0;\n\n\tmemset(&priv, 0, sizeof(priv));\n\tpriv.fixup = true;\n\tpriv.page = -1;\n\tpriv.bus = pdev->mdio.bus;\n\tchipid = rtl_get(&priv.dev, RTL_REG_CHIPID);\n\tif (chipid == 0x5988)\n\t\tpdev->phy_id = RTL8306_MAGIC;\n\n\treturn 0;\n}\n\nstatic int\nrtl8306_probe(struct phy_device *pdev)\n{\n\tstruct rtl_priv *priv;\n\n\tlist_for_each_entry(priv, &phydevs, list) {\n\t\t/*\n\t\t * share one rtl_priv instance between virtual phy\n\t\t * devices on the same bus\n\t\t */\n\t\tif (priv->bus == pdev->mdio.bus)\n\t\t\tgoto found;\n\t}\n\tpriv = kzalloc(sizeof(struct rtl_priv), GFP_KERNEL);\n\tif (!priv)\n\t\treturn -ENOMEM;\n\n\tpriv->bus = pdev->mdio.bus;\n\nfound:\n\tpdev->priv = priv;\n\treturn 0;\n}\n\nstatic void\nrtl8306_remove(struct phy_device *pdev)\n{\n\tstruct rtl_priv *priv = pdev->priv;\n\tunregister_switch(&priv->dev);\n\tkfree(priv);\n}\n\nstatic int\nrtl8306_config_aneg(struct phy_device *pdev)\n{\n\tstruct rtl_priv *priv = pdev->priv;\n\n\t/* Only for WAN */\n\tif (pdev->mdio.addr == 0)\n\t\treturn 0;\n\n\t/* Restart autonegotiation */\n\trtl_set(&priv->dev, RTL_PORT_REG(4, NWAY), 1);\n\trtl_set(&priv->dev, RTL_PORT_REG(4, NRESTART), 1);\n\n\treturn 0;\n}\n\nstatic int\nrtl8306_read_status(struct phy_device *pdev)\n{\n\tstruct rtl_priv *priv = pdev->priv;\n\tstruct switch_dev *dev = &priv->dev;\n\n\tif (pdev->mdio.addr == 4) {\n\t\t/* WAN */\n\t\tpdev->speed = rtl_get(dev, RTL_PORT_REG(4, SPEED)) ? SPEED_100 : SPEED_10;\n\t\tpdev->duplex = rtl_get(dev, RTL_PORT_REG(4, DUPLEX)) ? DUPLEX_FULL : DUPLEX_HALF;\n\t\tpdev->link = !!rtl_get(dev, RTL_PORT_REG(4, LINK));\n\t} else {\n\t\t/* LAN */\n\t\tpdev->speed = SPEED_100;\n\t\tpdev->duplex = DUPLEX_FULL;\n\t\tpdev->link = 1;\n\t}\n\n\t/*\n\t * Bypass generic PHY status read,\n\t * it doesn't work with this switch\n\t */\n\tif (pdev->link) {\n\t\tpdev->state = PHY_RUNNING;\n\t\tnetif_carrier_on(pdev->attached_dev);\n\t\tpdev->adjust_link(pdev->attached_dev);\n\t} else {\n\t\tpdev->state = PHY_NOLINK;\n\t\tnetif_carrier_off(pdev->attached_dev);\n\t\tpdev->adjust_link(pdev->attached_dev);\n\t}\n\n\treturn 0;\n}\n\n\nstatic struct phy_driver rtl8306_driver = {\n\t.name\t\t= \"Realtek RTL8306S\",\n\t.phy_id\t\t= RTL8306_MAGIC,\n\t.phy_id_mask\t= 0xffffffff,\n\t.features\t= PHY_BASIC_FEATURES,\n\t.probe\t\t= &rtl8306_probe,\n\t.remove\t\t= &rtl8306_remove,\n\t.config_init\t= &rtl8306_config_init,\n\t.config_aneg\t= &rtl8306_config_aneg,\n\t.read_status\t= &rtl8306_read_status,\n};\n\n\nstatic int __init\nrtl_init(void)\n{\n\tphy_register_fixup_for_id(PHY_ANY_ID, rtl8306_fixup);\n\treturn phy_driver_register(&rtl8306_driver, THIS_MODULE);\n}\n\nstatic void __exit\nrtl_exit(void)\n{\n\tphy_driver_unregister(&rtl8306_driver);\n}\n\nmodule_init(rtl_init);\nmodule_exit(rtl_exit);\nMODULE_LICENSE(\"GPL\");\n\n"
  },
  {
    "path": "target/linux/generic/files/drivers/net/phy/rtl8366_smi.c",
    "content": "/*\n * Realtek RTL8366 SMI interface driver\n *\n * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of the GNU General Public License version 2 as published\n * by the Free Software Foundation.\n */\n\n#include <linux/kernel.h>\n#include <linux/module.h>\n#include <linux/device.h>\n#include <linux/delay.h>\n#include <linux/gpio.h>\n#include <linux/spinlock.h>\n#include <linux/skbuff.h>\n#include <linux/of.h>\n#include <linux/of_platform.h>\n#include <linux/of_gpio.h>\n#include <linux/rtl8366.h>\n#include <linux/version.h>\n#include <linux/of_mdio.h>\n\n#ifdef CONFIG_RTL8366_SMI_DEBUG_FS\n#include <linux/debugfs.h>\n#endif\n\n#include \"rtl8366_smi.h\"\n\n#define RTL8366_SMI_ACK_RETRY_COUNT         5\n\n#define RTL8366_SMI_HW_STOP_DELAY\t\t25\t/* msecs */\n#define RTL8366_SMI_HW_START_DELAY\t\t100\t/* msecs */\n\nstatic inline void rtl8366_smi_clk_delay(struct rtl8366_smi *smi)\n{\n\tndelay(smi->clk_delay);\n}\n\nstatic void rtl8366_smi_start(struct rtl8366_smi *smi)\n{\n\tunsigned int sda = smi->gpio_sda;\n\tunsigned int sck = smi->gpio_sck;\n\n\t/*\n\t * Set GPIO pins to output mode, with initial state:\n\t * SCK = 0, SDA = 1\n\t */\n\tgpio_direction_output(sck, 0);\n\tgpio_direction_output(sda, 1);\n\trtl8366_smi_clk_delay(smi);\n\n\t/* CLK 1: 0 -> 1, 1 -> 0 */\n\tgpio_set_value(sck, 1);\n\trtl8366_smi_clk_delay(smi);\n\tgpio_set_value(sck, 0);\n\trtl8366_smi_clk_delay(smi);\n\n\t/* CLK 2: */\n\tgpio_set_value(sck, 1);\n\trtl8366_smi_clk_delay(smi);\n\tgpio_set_value(sda, 0);\n\trtl8366_smi_clk_delay(smi);\n\tgpio_set_value(sck, 0);\n\trtl8366_smi_clk_delay(smi);\n\tgpio_set_value(sda, 1);\n}\n\nstatic void rtl8366_smi_stop(struct rtl8366_smi *smi)\n{\n\tunsigned int sda = smi->gpio_sda;\n\tunsigned int sck = smi->gpio_sck;\n\n\trtl8366_smi_clk_delay(smi);\n\tgpio_set_value(sda, 0);\n\tgpio_set_value(sck, 1);\n\trtl8366_smi_clk_delay(smi);\n\tgpio_set_value(sda, 1);\n\trtl8366_smi_clk_delay(smi);\n\tgpio_set_value(sck, 1);\n\trtl8366_smi_clk_delay(smi);\n\tgpio_set_value(sck, 0);\n\trtl8366_smi_clk_delay(smi);\n\tgpio_set_value(sck, 1);\n\n\t/* add a click */\n\trtl8366_smi_clk_delay(smi);\n\tgpio_set_value(sck, 0);\n\trtl8366_smi_clk_delay(smi);\n\tgpio_set_value(sck, 1);\n\n\t/* set GPIO pins to input mode */\n\tgpio_direction_input(sda);\n\tgpio_direction_input(sck);\n}\n\nstatic void rtl8366_smi_write_bits(struct rtl8366_smi *smi, u32 data, u32 len)\n{\n\tunsigned int sda = smi->gpio_sda;\n\tunsigned int sck = smi->gpio_sck;\n\n\tfor (; len > 0; len--) {\n\t\trtl8366_smi_clk_delay(smi);\n\n\t\t/* prepare data */\n\t\tgpio_set_value(sda, !!(data & ( 1 << (len - 1))));\n\t\trtl8366_smi_clk_delay(smi);\n\n\t\t/* clocking */\n\t\tgpio_set_value(sck, 1);\n\t\trtl8366_smi_clk_delay(smi);\n\t\tgpio_set_value(sck, 0);\n\t}\n}\n\nstatic void rtl8366_smi_read_bits(struct rtl8366_smi *smi, u32 len, u32 *data)\n{\n\tunsigned int sda = smi->gpio_sda;\n\tunsigned int sck = smi->gpio_sck;\n\n\tgpio_direction_input(sda);\n\n\tfor (*data = 0; len > 0; len--) {\n\t\tu32 u;\n\n\t\trtl8366_smi_clk_delay(smi);\n\n\t\t/* clocking */\n\t\tgpio_set_value(sck, 1);\n\t\trtl8366_smi_clk_delay(smi);\n\t\tu = !!gpio_get_value(sda);\n\t\tgpio_set_value(sck, 0);\n\n\t\t*data |= (u << (len - 1));\n\t}\n\n\tgpio_direction_output(sda, 0);\n}\n\nstatic int rtl8366_smi_wait_for_ack(struct rtl8366_smi *smi)\n{\n\tint retry_cnt;\n\n\tretry_cnt = 0;\n\tdo {\n\t\tu32 ack;\n\n\t\trtl8366_smi_read_bits(smi, 1, &ack);\n\t\tif (ack == 0)\n\t\t\tbreak;\n\n\t\tif (++retry_cnt > RTL8366_SMI_ACK_RETRY_COUNT) {\n\t\t\tdev_err(smi->parent, \"ACK timeout\\n\");\n\t\t\treturn -ETIMEDOUT;\n\t\t}\n\t} while (1);\n\n\treturn 0;\n}\n\nstatic int rtl8366_smi_write_byte(struct rtl8366_smi *smi, u8 data)\n{\n\trtl8366_smi_write_bits(smi, data, 8);\n\treturn rtl8366_smi_wait_for_ack(smi);\n}\n\nstatic int rtl8366_smi_write_byte_noack(struct rtl8366_smi *smi, u8 data)\n{\n\trtl8366_smi_write_bits(smi, data, 8);\n\treturn 0;\n}\n\nstatic int rtl8366_smi_read_byte0(struct rtl8366_smi *smi, u8 *data)\n{\n\tu32 t;\n\n\t/* read data */\n\trtl8366_smi_read_bits(smi, 8, &t);\n\t*data = (t & 0xff);\n\n\t/* send an ACK */\n\trtl8366_smi_write_bits(smi, 0x00, 1);\n\n\treturn 0;\n}\n\nstatic int rtl8366_smi_read_byte1(struct rtl8366_smi *smi, u8 *data)\n{\n\tu32 t;\n\n\t/* read data */\n\trtl8366_smi_read_bits(smi, 8, &t);\n\t*data = (t & 0xff);\n\n\t/* send an ACK */\n\trtl8366_smi_write_bits(smi, 0x01, 1);\n\n\treturn 0;\n}\n\nstatic int __rtl8366_smi_read_reg(struct rtl8366_smi *smi, u32 addr, u32 *data)\n{\n\tunsigned long flags;\n\tu8 lo = 0;\n\tu8 hi = 0;\n\tint ret;\n\n\tspin_lock_irqsave(&smi->lock, flags);\n\n\trtl8366_smi_start(smi);\n\n\t/* send READ command */\n\tret = rtl8366_smi_write_byte(smi, smi->cmd_read);\n\tif (ret)\n\t\tgoto out;\n\n\t/* set ADDR[7:0] */\n\tret = rtl8366_smi_write_byte(smi, addr & 0xff);\n\tif (ret)\n\t\tgoto out;\n\n\t/* set ADDR[15:8] */\n\tret = rtl8366_smi_write_byte(smi, addr >> 8);\n\tif (ret)\n\t\tgoto out;\n\n\t/* read DATA[7:0] */\n\trtl8366_smi_read_byte0(smi, &lo);\n\t/* read DATA[15:8] */\n\trtl8366_smi_read_byte1(smi, &hi);\n\n\t*data = ((u32) lo) | (((u32) hi) << 8);\n\n\tret = 0;\n\n out:\n\trtl8366_smi_stop(smi);\n\tspin_unlock_irqrestore(&smi->lock, flags);\n\n\treturn ret;\n}\n/* Read/write via mdiobus */\n#define MDC_MDIO_CTRL0_REG\t\t31\n#define MDC_MDIO_START_REG\t\t29\n#define MDC_MDIO_CTRL1_REG\t\t21\n#define MDC_MDIO_ADDRESS_REG\t\t23\n#define MDC_MDIO_DATA_WRITE_REG\t\t24\n#define MDC_MDIO_DATA_READ_REG\t\t25\n\n#define MDC_MDIO_START_OP\t\t0xFFFF\n#define MDC_MDIO_ADDR_OP\t\t0x000E\n#define MDC_MDIO_READ_OP\t\t0x0001\n#define MDC_MDIO_WRITE_OP\t\t0x0003\n#define MDC_REALTEK_PHY_ADDR\t\t0x0\n\nint __rtl8366_mdio_read_reg(struct rtl8366_smi *smi, u32 addr, u32 *data)\n{\n\tu32 phy_id = MDC_REALTEK_PHY_ADDR;\n\tstruct mii_bus *mbus = smi->ext_mbus;\n\n\tBUG_ON(in_interrupt());\n\n\tmutex_lock(&mbus->mdio_lock);\n\t/* Write Start command to register 29 */\n\tmbus->write(mbus, phy_id, MDC_MDIO_START_REG, MDC_MDIO_START_OP);\n\n\t/* Write address control code to register 31 */\n\tmbus->write(mbus, phy_id, MDC_MDIO_CTRL0_REG, MDC_MDIO_ADDR_OP);\n\n\t/* Write Start command to register 29 */\n\tmbus->write(mbus, phy_id, MDC_MDIO_START_REG, MDC_MDIO_START_OP);\n\n\t/* Write address to register 23 */\n\tmbus->write(mbus, phy_id, MDC_MDIO_ADDRESS_REG, addr);\n\n\t/* Write Start command to register 29 */\n\tmbus->write(mbus, phy_id, MDC_MDIO_START_REG, MDC_MDIO_START_OP);\n\n\t/* Write read control code to register 21 */\n\tmbus->write(mbus, phy_id, MDC_MDIO_CTRL1_REG, MDC_MDIO_READ_OP);\n\n\t/* Write Start command to register 29 */\n\tmbus->write(smi->ext_mbus, phy_id, MDC_MDIO_START_REG, MDC_MDIO_START_OP);\n\n\t/* Read data from register 25 */\n\t*data = mbus->read(mbus, phy_id, MDC_MDIO_DATA_READ_REG);\n\n\tmutex_unlock(&mbus->mdio_lock);\n\n\treturn 0;\n}\n\nstatic int __rtl8366_mdio_write_reg(struct rtl8366_smi *smi, u32 addr, u32 data)\n{\n\tu32 phy_id = MDC_REALTEK_PHY_ADDR;\n\tstruct mii_bus *mbus = smi->ext_mbus;\n\n\tBUG_ON(in_interrupt());\n\n\tmutex_lock(&mbus->mdio_lock);\n\n\t/* Write Start command to register 29 */\n\tmbus->write(mbus, phy_id, MDC_MDIO_START_REG, MDC_MDIO_START_OP);\n\n\t/* Write address control code to register 31 */\n\tmbus->write(mbus, phy_id, MDC_MDIO_CTRL0_REG, MDC_MDIO_ADDR_OP);\n\n\t/* Write Start command to register 29 */\n\tmbus->write(mbus, phy_id, MDC_MDIO_START_REG, MDC_MDIO_START_OP);\n\n\t/* Write address to register 23 */\n\tmbus->write(mbus, phy_id, MDC_MDIO_ADDRESS_REG, addr);\n\n\t/* Write Start command to register 29 */\n\tmbus->write(mbus, phy_id, MDC_MDIO_START_REG, MDC_MDIO_START_OP);\n\n\t/* Write data to register 24 */\n\tmbus->write(mbus, phy_id, MDC_MDIO_DATA_WRITE_REG, data);\n\n\t/* Write Start command to register 29 */\n\tmbus->write(mbus, phy_id, MDC_MDIO_START_REG, MDC_MDIO_START_OP);\n\n\t/* Write data control code to register 21 */\n\tmbus->write(mbus, phy_id, MDC_MDIO_CTRL1_REG, MDC_MDIO_WRITE_OP);\n\n\tmutex_unlock(&mbus->mdio_lock);\n\treturn 0;\n}\n\nint rtl8366_smi_read_reg(struct rtl8366_smi *smi, u32 addr, u32 *data)\n{\n\tif (smi->ext_mbus)\n\t\treturn __rtl8366_mdio_read_reg(smi, addr, data);\n\telse\n\t\treturn __rtl8366_smi_read_reg(smi, addr, data);\n}\nEXPORT_SYMBOL_GPL(rtl8366_smi_read_reg);\n\nstatic int __rtl8366_smi_write_reg(struct rtl8366_smi *smi,\n\t\t\t\t   u32 addr, u32 data, bool ack)\n{\n\tunsigned long flags;\n\tint ret;\n\n\tspin_lock_irqsave(&smi->lock, flags);\n\n\trtl8366_smi_start(smi);\n\n\t/* send WRITE command */\n\tret = rtl8366_smi_write_byte(smi, smi->cmd_write);\n\tif (ret)\n\t\tgoto out;\n\n\t/* set ADDR[7:0] */\n\tret = rtl8366_smi_write_byte(smi, addr & 0xff);\n\tif (ret)\n\t\tgoto out;\n\n\t/* set ADDR[15:8] */\n\tret = rtl8366_smi_write_byte(smi, addr >> 8);\n\tif (ret)\n\t\tgoto out;\n\n\t/* write DATA[7:0] */\n\tret = rtl8366_smi_write_byte(smi, data & 0xff);\n\tif (ret)\n\t\tgoto out;\n\n\t/* write DATA[15:8] */\n\tif (ack)\n\t\tret = rtl8366_smi_write_byte(smi, data >> 8);\n\telse\n\t\tret = rtl8366_smi_write_byte_noack(smi, data >> 8);\n\tif (ret)\n\t\tgoto out;\n\n\tret = 0;\n\n out:\n\trtl8366_smi_stop(smi);\n\tspin_unlock_irqrestore(&smi->lock, flags);\n\n\treturn ret;\n}\n\nint rtl8366_smi_write_reg(struct rtl8366_smi *smi, u32 addr, u32 data)\n{\n\tif (smi->ext_mbus)\n\t\treturn __rtl8366_mdio_write_reg(smi, addr, data);\n\telse\n\t\treturn __rtl8366_smi_write_reg(smi, addr, data, true);\n}\nEXPORT_SYMBOL_GPL(rtl8366_smi_write_reg);\n\nint rtl8366_smi_write_reg_noack(struct rtl8366_smi *smi, u32 addr, u32 data)\n{\n\treturn __rtl8366_smi_write_reg(smi, addr, data, false);\n}\nEXPORT_SYMBOL_GPL(rtl8366_smi_write_reg_noack);\n\nint rtl8366_smi_rmwr(struct rtl8366_smi *smi, u32 addr, u32 mask, u32 data)\n{\n\tu32 t;\n\tint err;\n\n\terr = rtl8366_smi_read_reg(smi, addr, &t);\n\tif (err)\n\t\treturn err;\n\n\terr = rtl8366_smi_write_reg(smi, addr, (t & ~mask) | data);\n\treturn err;\n\n}\nEXPORT_SYMBOL_GPL(rtl8366_smi_rmwr);\n\nstatic int rtl8366_reset(struct rtl8366_smi *smi)\n{\n\tif (smi->hw_reset) {\n\t\tsmi->hw_reset(smi, true);\n\t\tmsleep(RTL8366_SMI_HW_STOP_DELAY);\n\t\tsmi->hw_reset(smi, false);\n\t\tmsleep(RTL8366_SMI_HW_START_DELAY);\n\t\treturn 0;\n\t}\n\n\treturn smi->ops->reset_chip(smi);\n}\n\nstatic int rtl8366_mc_is_used(struct rtl8366_smi *smi, int mc_index, int *used)\n{\n\tint err;\n\tint i;\n\n\t*used = 0;\n\tfor (i = 0; i < smi->num_ports; i++) {\n\t\tint index = 0;\n\n\t\terr = smi->ops->get_mc_index(smi, i, &index);\n\t\tif (err)\n\t\t\treturn err;\n\n\t\tif (mc_index == index) {\n\t\t\t*used = 1;\n\t\t\tbreak;\n\t\t}\n\t}\n\n\treturn 0;\n}\n\nstatic int rtl8366_set_vlan(struct rtl8366_smi *smi, int vid, u32 member,\n\t\t\t    u32 untag, u32 fid)\n{\n\tstruct rtl8366_vlan_4k vlan4k;\n\tint err;\n\tint i;\n\n\t/* Update the 4K table */\n\terr = smi->ops->get_vlan_4k(smi, vid, &vlan4k);\n\tif (err)\n\t\treturn err;\n\n\tvlan4k.member = member;\n\tvlan4k.untag = untag;\n\tvlan4k.fid = fid;\n\terr = smi->ops->set_vlan_4k(smi, &vlan4k);\n\tif (err)\n\t\treturn err;\n\n\t/* Try to find an existing MC entry for this VID */\n\tfor (i = 0; i < smi->num_vlan_mc; i++) {\n\t\tstruct rtl8366_vlan_mc vlanmc;\n\n\t\terr = smi->ops->get_vlan_mc(smi, i, &vlanmc);\n\t\tif (err)\n\t\t\treturn err;\n\n\t\tif (vid == vlanmc.vid) {\n\t\t\t/* update the MC entry */\n\t\t\tvlanmc.member = member;\n\t\t\tvlanmc.untag = untag;\n\t\t\tvlanmc.fid = fid;\n\n\t\t\terr = smi->ops->set_vlan_mc(smi, i, &vlanmc);\n\t\t\tbreak;\n\t\t}\n\t}\n\n\treturn err;\n}\n\nstatic int rtl8366_get_pvid(struct rtl8366_smi *smi, int port, int *val)\n{\n\tstruct rtl8366_vlan_mc vlanmc;\n\tint err;\n\tint index;\n\n\terr = smi->ops->get_mc_index(smi, port, &index);\n\tif (err)\n\t\treturn err;\n\n\terr = smi->ops->get_vlan_mc(smi, index, &vlanmc);\n\tif (err)\n\t\treturn err;\n\n\t*val = vlanmc.vid;\n\treturn 0;\n}\n\nstatic int rtl8366_set_pvid(struct rtl8366_smi *smi, unsigned port,\n\t\t\t    unsigned vid)\n{\n\tstruct rtl8366_vlan_mc vlanmc;\n\tstruct rtl8366_vlan_4k vlan4k;\n\tint err;\n\tint i;\n\n\t/* Try to find an existing MC entry for this VID */\n\tfor (i = 0; i < smi->num_vlan_mc; i++) {\n\t\terr = smi->ops->get_vlan_mc(smi, i, &vlanmc);\n\t\tif (err)\n\t\t\treturn err;\n\n\t\tif (vid == vlanmc.vid) {\n\t\t\terr = smi->ops->set_vlan_mc(smi, i, &vlanmc);\n\t\t\tif (err)\n\t\t\t\treturn err;\n\n\t\t\terr = smi->ops->set_mc_index(smi, port, i);\n\t\t\treturn err;\n\t\t}\n\t}\n\n\t/* We have no MC entry for this VID, try to find an empty one */\n\tfor (i = 0; i < smi->num_vlan_mc; i++) {\n\t\terr = smi->ops->get_vlan_mc(smi, i, &vlanmc);\n\t\tif (err)\n\t\t\treturn err;\n\n\t\tif (vlanmc.vid == 0 && vlanmc.member == 0) {\n\t\t\t/* Update the entry from the 4K table */\n\t\t\terr = smi->ops->get_vlan_4k(smi, vid, &vlan4k);\n\t\t\tif (err)\n\t\t\t\treturn err;\n\n\t\t\tvlanmc.vid = vid;\n\t\t\tvlanmc.member = vlan4k.member;\n\t\t\tvlanmc.untag = vlan4k.untag;\n\t\t\tvlanmc.fid = vlan4k.fid;\n\t\t\terr = smi->ops->set_vlan_mc(smi, i, &vlanmc);\n\t\t\tif (err)\n\t\t\t\treturn err;\n\n\t\t\terr = smi->ops->set_mc_index(smi, port, i);\n\t\t\treturn err;\n\t\t}\n\t}\n\n\t/* MC table is full, try to find an unused entry and replace it */\n\tfor (i = 0; i < smi->num_vlan_mc; i++) {\n\t\tint used;\n\n\t\terr = rtl8366_mc_is_used(smi, i, &used);\n\t\tif (err)\n\t\t\treturn err;\n\n\t\tif (!used) {\n\t\t\t/* Update the entry from the 4K table */\n\t\t\terr = smi->ops->get_vlan_4k(smi, vid, &vlan4k);\n\t\t\tif (err)\n\t\t\t\treturn err;\n\n\t\t\tvlanmc.vid = vid;\n\t\t\tvlanmc.member = vlan4k.member;\n\t\t\tvlanmc.untag = vlan4k.untag;\n\t\t\tvlanmc.fid = vlan4k.fid;\n\t\t\terr = smi->ops->set_vlan_mc(smi, i, &vlanmc);\n\t\t\tif (err)\n\t\t\t\treturn err;\n\n\t\t\terr = smi->ops->set_mc_index(smi, port, i);\n\t\t\treturn err;\n\t\t}\n\t}\n\n\tdev_err(smi->parent,\n\t\t\"all VLAN member configurations are in use\\n\");\n\n\treturn -ENOSPC;\n}\n\nint rtl8366_enable_vlan(struct rtl8366_smi *smi, int enable)\n{\n\tint err;\n\n\terr = smi->ops->enable_vlan(smi, enable);\n\tif (err)\n\t\treturn err;\n\n\tsmi->vlan_enabled = enable;\n\n\tif (!enable) {\n\t\tsmi->vlan4k_enabled = 0;\n\t\terr = smi->ops->enable_vlan4k(smi, enable);\n\t}\n\n\treturn err;\n}\nEXPORT_SYMBOL_GPL(rtl8366_enable_vlan);\n\nstatic int rtl8366_enable_vlan4k(struct rtl8366_smi *smi, int enable)\n{\n\tint err;\n\n\tif (enable) {\n\t\terr = smi->ops->enable_vlan(smi, enable);\n\t\tif (err)\n\t\t\treturn err;\n\n\t\tsmi->vlan_enabled = enable;\n\t}\n\n\terr = smi->ops->enable_vlan4k(smi, enable);\n\tif (err)\n\t\treturn err;\n\n\tsmi->vlan4k_enabled = enable;\n\treturn 0;\n}\n\nint rtl8366_enable_all_ports(struct rtl8366_smi *smi, int enable)\n{\n\tint port;\n\tint err;\n\n\tfor (port = 0; port < smi->num_ports; port++) {\n\t\terr = smi->ops->enable_port(smi, port, enable);\n\t\tif (err)\n\t\t\treturn err;\n\t}\n\n\treturn 0;\n}\nEXPORT_SYMBOL_GPL(rtl8366_enable_all_ports);\n\nint rtl8366_reset_vlan(struct rtl8366_smi *smi)\n{\n\tstruct rtl8366_vlan_mc vlanmc;\n\tint err;\n\tint i;\n\n\trtl8366_enable_vlan(smi, 0);\n\trtl8366_enable_vlan4k(smi, 0);\n\n\t/* clear VLAN member configurations */\n\tvlanmc.vid = 0;\n\tvlanmc.priority = 0;\n\tvlanmc.member = 0;\n\tvlanmc.untag = 0;\n\tvlanmc.fid = 0;\n\tfor (i = 0; i < smi->num_vlan_mc; i++) {\n\t\terr = smi->ops->set_vlan_mc(smi, i, &vlanmc);\n\t\tif (err)\n\t\t\treturn err;\n\t}\n\n\treturn 0;\n}\nEXPORT_SYMBOL_GPL(rtl8366_reset_vlan);\n\nstatic int rtl8366_init_vlan(struct rtl8366_smi *smi)\n{\n\tint port;\n\tint err;\n\n\terr = rtl8366_reset_vlan(smi);\n\tif (err)\n\t\treturn err;\n\n\tfor (port = 0; port < smi->num_ports; port++) {\n\t\tu32 mask;\n\n\t\tif (port == smi->cpu_port)\n\t\t\tmask = (1 << smi->num_ports) - 1;\n\t\telse\n\t\t\tmask = (1 << port) | (1 << smi->cpu_port);\n\n\t\terr = rtl8366_set_vlan(smi, (port + 1), mask, mask, 0);\n\t\tif (err)\n\t\t\treturn err;\n\n\t\terr = rtl8366_set_pvid(smi, port, (port + 1));\n\t\tif (err)\n\t\t\treturn err;\n\t}\n\n\treturn rtl8366_enable_vlan(smi, 1);\n}\n\n#ifdef CONFIG_RTL8366_SMI_DEBUG_FS\nint rtl8366_debugfs_open(struct inode *inode, struct file *file)\n{\n\tfile->private_data = inode->i_private;\n\treturn 0;\n}\nEXPORT_SYMBOL_GPL(rtl8366_debugfs_open);\n\nstatic ssize_t rtl8366_read_debugfs_vlan_mc(struct file *file,\n\t\t\t\t\t      char __user *user_buf,\n\t\t\t\t\t      size_t count, loff_t *ppos)\n{\n\tstruct rtl8366_smi *smi = (struct rtl8366_smi *)file->private_data;\n\tint i, len = 0;\n\tchar *buf = smi->buf;\n\n\tlen += snprintf(buf + len, sizeof(smi->buf) - len,\n\t\t\t\"%2s %6s %4s %6s %6s %3s\\n\",\n\t\t\t\"id\", \"vid\",\"prio\", \"member\", \"untag\", \"fid\");\n\n\tfor (i = 0; i < smi->num_vlan_mc; ++i) {\n\t\tstruct rtl8366_vlan_mc vlanmc;\n\n\t\tsmi->ops->get_vlan_mc(smi, i, &vlanmc);\n\n\t\tlen += snprintf(buf + len, sizeof(smi->buf) - len,\n\t\t\t\t\"%2d %6d %4d 0x%04x 0x%04x %3d\\n\",\n\t\t\t\ti, vlanmc.vid, vlanmc.priority,\n\t\t\t\tvlanmc.member, vlanmc.untag, vlanmc.fid);\n\t}\n\n\treturn simple_read_from_buffer(user_buf, count, ppos, buf, len);\n}\n\n#define RTL8366_VLAN4K_PAGE_SIZE\t64\n#define RTL8366_VLAN4K_NUM_PAGES\t(4096 / RTL8366_VLAN4K_PAGE_SIZE)\n\nstatic ssize_t rtl8366_read_debugfs_vlan_4k(struct file *file,\n\t\t\t\t\t    char __user *user_buf,\n\t\t\t\t\t    size_t count, loff_t *ppos)\n{\n\tstruct rtl8366_smi *smi = (struct rtl8366_smi *)file->private_data;\n\tint i, len = 0;\n\tint offset;\n\tchar *buf = smi->buf;\n\n\tif (smi->dbg_vlan_4k_page >= RTL8366_VLAN4K_NUM_PAGES) {\n\t\tlen += snprintf(buf + len, sizeof(smi->buf) - len,\n\t\t\t\t\"invalid page: %u\\n\", smi->dbg_vlan_4k_page);\n\t\treturn simple_read_from_buffer(user_buf, count, ppos, buf, len);\n\t}\n\n\tlen += snprintf(buf + len, sizeof(smi->buf) - len,\n\t\t\t\"%4s %6s %6s %3s\\n\",\n\t\t\t\"vid\", \"member\", \"untag\", \"fid\");\n\n\toffset = RTL8366_VLAN4K_PAGE_SIZE * smi->dbg_vlan_4k_page;\n\tfor (i = 0; i < RTL8366_VLAN4K_PAGE_SIZE; i++) {\n\t\tstruct rtl8366_vlan_4k vlan4k;\n\n\t\tsmi->ops->get_vlan_4k(smi, offset + i, &vlan4k);\n\n\t\tlen += snprintf(buf + len, sizeof(smi->buf) - len,\n\t\t\t\t\"%4d 0x%04x 0x%04x %3d\\n\",\n\t\t\t\tvlan4k.vid, vlan4k.member,\n\t\t\t\tvlan4k.untag, vlan4k.fid);\n\t}\n\n\treturn simple_read_from_buffer(user_buf, count, ppos, buf, len);\n}\n\nstatic ssize_t rtl8366_read_debugfs_pvid(struct file *file,\n\t\t\t\t\t char __user *user_buf,\n\t\t\t\t\t size_t count, loff_t *ppos)\n{\n\tstruct rtl8366_smi *smi = (struct rtl8366_smi *)file->private_data;\n\tchar *buf = smi->buf;\n\tint len = 0;\n\tint i;\n\n\tlen += snprintf(buf + len, sizeof(smi->buf) - len, \"%4s %4s\\n\",\n\t\t\t\"port\", \"pvid\");\n\n\tfor (i = 0; i < smi->num_ports; i++) {\n\t\tint pvid;\n\t\tint err;\n\n\t\terr = rtl8366_get_pvid(smi, i, &pvid);\n\t\tif (err)\n\t\t\tlen += snprintf(buf + len, sizeof(smi->buf) - len,\n\t\t\t\t\"%4d error\\n\", i);\n\t\telse\n\t\t\tlen += snprintf(buf + len, sizeof(smi->buf) - len,\n\t\t\t\t\"%4d %4d\\n\", i, pvid);\n\t}\n\n\treturn simple_read_from_buffer(user_buf, count, ppos, buf, len);\n}\n\nstatic ssize_t rtl8366_read_debugfs_reg(struct file *file,\n\t\t\t\t\t char __user *user_buf,\n\t\t\t\t\t size_t count, loff_t *ppos)\n{\n\tstruct rtl8366_smi *smi = (struct rtl8366_smi *)file->private_data;\n\tu32 t, reg = smi->dbg_reg;\n\tint err, len = 0;\n\tchar *buf = smi->buf;\n\n\tmemset(buf, '\\0', sizeof(smi->buf));\n\n\terr = rtl8366_smi_read_reg(smi, reg, &t);\n\tif (err) {\n\t\tlen += snprintf(buf, sizeof(smi->buf),\n\t\t\t\t\"Read failed (reg: 0x%04x)\\n\", reg);\n\t\treturn simple_read_from_buffer(user_buf, count, ppos, buf, len);\n\t}\n\n\tlen += snprintf(buf, sizeof(smi->buf), \"reg = 0x%04x, val = 0x%04x\\n\",\n\t\t\treg, t);\n\n\treturn simple_read_from_buffer(user_buf, count, ppos, buf, len);\n}\n\nstatic ssize_t rtl8366_write_debugfs_reg(struct file *file,\n\t\t\t\t\t  const char __user *user_buf,\n\t\t\t\t\t  size_t count, loff_t *ppos)\n{\n\tstruct rtl8366_smi *smi = (struct rtl8366_smi *)file->private_data;\n\tunsigned long data;\n\tu32 reg = smi->dbg_reg;\n\tint err;\n\tsize_t len;\n\tchar *buf = smi->buf;\n\n\tlen = min(count, sizeof(smi->buf) - 1);\n\tif (copy_from_user(buf, user_buf, len)) {\n\t\tdev_err(smi->parent, \"copy from user failed\\n\");\n\t\treturn -EFAULT;\n\t}\n\n\tbuf[len] = '\\0';\n\tif (len > 0 && buf[len - 1] == '\\n')\n\t\tbuf[len - 1] = '\\0';\n\n\n\tif (kstrtoul(buf, 16, &data)) {\n\t\tdev_err(smi->parent, \"Invalid reg value %s\\n\", buf);\n\t} else {\n\t\terr = rtl8366_smi_write_reg(smi, reg, data);\n\t\tif (err) {\n\t\t\tdev_err(smi->parent,\n\t\t\t\t\"writing reg 0x%04x val 0x%04lx failed\\n\",\n\t\t\t\treg, data);\n\t\t}\n\t}\n\n\treturn count;\n}\n\nstatic ssize_t rtl8366_read_debugfs_mibs(struct file *file,\n\t\t\t\t\t char __user *user_buf,\n\t\t\t\t\t size_t count, loff_t *ppos)\n{\n\tstruct rtl8366_smi *smi = file->private_data;\n\tint i, j, len = 0;\n\tchar *buf = smi->buf;\n\n\tlen += snprintf(buf + len, sizeof(smi->buf) - len, \"%-36s\",\n\t\t\t\"Counter\");\n\n\tfor (i = 0; i < smi->num_ports; i++) {\n\t\tchar port_buf[10];\n\n\t\tsnprintf(port_buf, sizeof(port_buf), \"Port %d\", i);\n\t\tlen += snprintf(buf + len, sizeof(smi->buf) - len, \" %12s\",\n\t\t\t\tport_buf);\n\t}\n\tlen += snprintf(buf + len, sizeof(smi->buf) - len, \"\\n\");\n\n\tfor (i = 0; i < smi->num_mib_counters; i++) {\n\t\tlen += snprintf(buf + len, sizeof(smi->buf) - len, \"%-36s \",\n\t\t\t\tsmi->mib_counters[i].name);\n\t\tfor (j = 0; j < smi->num_ports; j++) {\n\t\t\tunsigned long long counter = 0;\n\n\t\t\tif (!smi->ops->get_mib_counter(smi, i, j, &counter))\n\t\t\t\tlen += snprintf(buf + len,\n\t\t\t\t\t\tsizeof(smi->buf) - len,\n\t\t\t\t\t\t\"%12llu \", counter);\n\t\t\telse\n\t\t\t\tlen += snprintf(buf + len,\n\t\t\t\t\t\tsizeof(smi->buf) - len,\n\t\t\t\t\t\t\"%12s \", \"error\");\n\t\t}\n\t\tlen += snprintf(buf + len, sizeof(smi->buf) - len, \"\\n\");\n\t}\n\n\treturn simple_read_from_buffer(user_buf, count, ppos, buf, len);\n}\n\nstatic const struct file_operations fops_rtl8366_regs = {\n\t.read\t= rtl8366_read_debugfs_reg,\n\t.write\t= rtl8366_write_debugfs_reg,\n\t.open\t= rtl8366_debugfs_open,\n\t.owner\t= THIS_MODULE\n};\n\nstatic const struct file_operations fops_rtl8366_vlan_mc = {\n\t.read\t= rtl8366_read_debugfs_vlan_mc,\n\t.open\t= rtl8366_debugfs_open,\n\t.owner\t= THIS_MODULE\n};\n\nstatic const struct file_operations fops_rtl8366_vlan_4k = {\n\t.read\t= rtl8366_read_debugfs_vlan_4k,\n\t.open\t= rtl8366_debugfs_open,\n\t.owner\t= THIS_MODULE\n};\n\nstatic const struct file_operations fops_rtl8366_pvid = {\n\t.read\t= rtl8366_read_debugfs_pvid,\n\t.open\t= rtl8366_debugfs_open,\n\t.owner\t= THIS_MODULE\n};\n\nstatic const struct file_operations fops_rtl8366_mibs = {\n\t.read = rtl8366_read_debugfs_mibs,\n\t.open = rtl8366_debugfs_open,\n\t.owner = THIS_MODULE\n};\n\nstatic void rtl8366_debugfs_init(struct rtl8366_smi *smi)\n{\n\tstruct dentry *node;\n\tstruct dentry *root;\n\n\tif (!smi->debugfs_root)\n\t\tsmi->debugfs_root = debugfs_create_dir(dev_name(smi->parent),\n\t\t\t\t\t\t       NULL);\n\n\tif (!smi->debugfs_root) {\n\t\tdev_err(smi->parent, \"Unable to create debugfs dir\\n\");\n\t\treturn;\n\t}\n\troot = smi->debugfs_root;\n\n\tnode = debugfs_create_x16(\"reg\", S_IRUGO | S_IWUSR, root,\n\t\t\t\t  &smi->dbg_reg);\n\tif (!node) {\n\t\tdev_err(smi->parent, \"Creating debugfs file '%s' failed\\n\",\n\t\t\t\"reg\");\n\t\treturn;\n\t}\n\n\tnode = debugfs_create_file(\"val\", S_IRUGO | S_IWUSR, root, smi,\n\t\t\t\t   &fops_rtl8366_regs);\n\tif (!node) {\n\t\tdev_err(smi->parent, \"Creating debugfs file '%s' failed\\n\",\n\t\t\t\"val\");\n\t\treturn;\n\t}\n\n\tnode = debugfs_create_file(\"vlan_mc\", S_IRUSR, root, smi,\n\t\t\t\t   &fops_rtl8366_vlan_mc);\n\tif (!node) {\n\t\tdev_err(smi->parent, \"Creating debugfs file '%s' failed\\n\",\n\t\t\t\"vlan_mc\");\n\t\treturn;\n\t}\n\n\tnode = debugfs_create_u8(\"vlan_4k_page\", S_IRUGO | S_IWUSR, root,\n\t\t\t\t  &smi->dbg_vlan_4k_page);\n\tif (!node) {\n\t\tdev_err(smi->parent, \"Creating debugfs file '%s' failed\\n\",\n\t\t\t\"vlan_4k_page\");\n\t\treturn;\n\t}\n\n\tnode = debugfs_create_file(\"vlan_4k\", S_IRUSR, root, smi,\n\t\t\t\t   &fops_rtl8366_vlan_4k);\n\tif (!node) {\n\t\tdev_err(smi->parent, \"Creating debugfs file '%s' failed\\n\",\n\t\t\t\"vlan_4k\");\n\t\treturn;\n\t}\n\n\tnode = debugfs_create_file(\"pvid\", S_IRUSR, root, smi,\n\t\t\t\t   &fops_rtl8366_pvid);\n\tif (!node) {\n\t\tdev_err(smi->parent, \"Creating debugfs file '%s' failed\\n\",\n\t\t\t\"pvid\");\n\t\treturn;\n\t}\n\n\tnode = debugfs_create_file(\"mibs\", S_IRUSR, smi->debugfs_root, smi,\n\t\t\t\t   &fops_rtl8366_mibs);\n\tif (!node)\n\t\tdev_err(smi->parent, \"Creating debugfs file '%s' failed\\n\",\n\t\t\t\"mibs\");\n}\n\nstatic void rtl8366_debugfs_remove(struct rtl8366_smi *smi)\n{\n\tif (smi->debugfs_root) {\n\t\tdebugfs_remove_recursive(smi->debugfs_root);\n\t\tsmi->debugfs_root = NULL;\n\t}\n}\n#else\nstatic inline void rtl8366_debugfs_init(struct rtl8366_smi *smi) {}\nstatic inline void rtl8366_debugfs_remove(struct rtl8366_smi *smi) {}\n#endif /* CONFIG_RTL8366_SMI_DEBUG_FS */\n\nstatic int rtl8366_smi_mii_init(struct rtl8366_smi *smi)\n{\n\tint ret;\n\n#ifdef CONFIG_OF\n\tstruct device_node *np = NULL;\n\n\tnp = of_get_child_by_name(smi->parent->of_node, \"mdio-bus\");\n#endif\n\n\tsmi->mii_bus = mdiobus_alloc();\n\tif (smi->mii_bus == NULL) {\n\t\tret = -ENOMEM;\n\t\tgoto err;\n\t}\n\n\tsmi->mii_bus->priv = (void *) smi;\n\tsmi->mii_bus->name = dev_name(smi->parent);\n\tsmi->mii_bus->read = smi->ops->mii_read;\n\tsmi->mii_bus->write = smi->ops->mii_write;\n\tsnprintf(smi->mii_bus->id, MII_BUS_ID_SIZE, \"%s\",\n\t\t dev_name(smi->parent));\n\tsmi->mii_bus->parent = smi->parent;\n\tsmi->mii_bus->phy_mask = ~(0x1f);\n\n#ifdef CONFIG_OF\n\tif (np)\n\t\tret = of_mdiobus_register(smi->mii_bus, np);\n\telse\n#endif\n\t\tret = mdiobus_register(smi->mii_bus);\n\n\tif (ret)\n\t\tgoto err_free;\n\n\treturn 0;\n\n err_free:\n\tmdiobus_free(smi->mii_bus);\n err:\n\treturn ret;\n}\n\nstatic void rtl8366_smi_mii_cleanup(struct rtl8366_smi *smi)\n{\n\tmdiobus_unregister(smi->mii_bus);\n\tmdiobus_free(smi->mii_bus);\n}\n\nint rtl8366_sw_reset_switch(struct switch_dev *dev)\n{\n\tstruct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);\n\tint err;\n\n\terr = rtl8366_reset(smi);\n\tif (err)\n\t\treturn err;\n\n\terr = smi->ops->setup(smi);\n\tif (err)\n\t\treturn err;\n\n\terr = rtl8366_reset_vlan(smi);\n\tif (err)\n\t\treturn err;\n\n\terr = rtl8366_enable_vlan(smi, 1);\n\tif (err)\n\t\treturn err;\n\n\treturn rtl8366_enable_all_ports(smi, 1);\n}\nEXPORT_SYMBOL_GPL(rtl8366_sw_reset_switch);\n\nint rtl8366_sw_get_port_pvid(struct switch_dev *dev, int port, int *val)\n{\n\tstruct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);\n\treturn rtl8366_get_pvid(smi, port, val);\n}\nEXPORT_SYMBOL_GPL(rtl8366_sw_get_port_pvid);\n\nint rtl8366_sw_set_port_pvid(struct switch_dev *dev, int port, int val)\n{\n\tstruct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);\n\treturn rtl8366_set_pvid(smi, port, val);\n}\nEXPORT_SYMBOL_GPL(rtl8366_sw_set_port_pvid);\n\nint rtl8366_sw_get_port_mib(struct switch_dev *dev,\n\t\t\t    const struct switch_attr *attr,\n\t\t\t    struct switch_val *val)\n{\n\tstruct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);\n\tint i, len = 0;\n\tunsigned long long counter = 0;\n\tchar *buf = smi->buf;\n\n\tif (val->port_vlan >= smi->num_ports)\n\t\treturn -EINVAL;\n\n\tlen += snprintf(buf + len, sizeof(smi->buf) - len,\n\t\t\t\"Port %d MIB counters\\n\",\n\t\t\tval->port_vlan);\n\n\tfor (i = 0; i < smi->num_mib_counters; ++i) {\n\t\tlen += snprintf(buf + len, sizeof(smi->buf) - len,\n\t\t\t\t\"%-36s: \", smi->mib_counters[i].name);\n\t\tif (!smi->ops->get_mib_counter(smi, i, val->port_vlan,\n\t\t\t\t\t       &counter))\n\t\t\tlen += snprintf(buf + len, sizeof(smi->buf) - len,\n\t\t\t\t\t\"%llu\\n\", counter);\n\t\telse\n\t\t\tlen += snprintf(buf + len, sizeof(smi->buf) - len,\n\t\t\t\t\t\"%s\\n\", \"error\");\n\t}\n\n\tval->value.s = buf;\n\tval->len = len;\n\treturn 0;\n}\nEXPORT_SYMBOL_GPL(rtl8366_sw_get_port_mib);\n\nint rtl8366_sw_get_port_stats(struct switch_dev *dev, int port,\n\t\t\t\tstruct switch_port_stats *stats,\n\t\t\t\tint txb_id, int rxb_id)\n{\n\tstruct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);\n\tunsigned long long counter = 0;\n\tint ret;\n\n\tif (port >= smi->num_ports)\n\t\treturn -EINVAL;\n\n\tret = smi->ops->get_mib_counter(smi, txb_id, port, &counter);\n\tif (ret)\n\t\treturn ret;\n\n\tstats->tx_bytes = counter;\n\n\tret = smi->ops->get_mib_counter(smi, rxb_id, port, &counter);\n\tif (ret)\n\t\treturn ret;\n\n\tstats->rx_bytes = counter;\n\n\treturn 0;\n}\nEXPORT_SYMBOL_GPL(rtl8366_sw_get_port_stats);\n\nint rtl8366_sw_get_vlan_info(struct switch_dev *dev,\n\t\t\t     const struct switch_attr *attr,\n\t\t\t     struct switch_val *val)\n{\n\tint i;\n\tu32 len = 0;\n\tstruct rtl8366_vlan_4k vlan4k;\n\tstruct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);\n\tchar *buf = smi->buf;\n\tint err;\n\n\tif (!smi->ops->is_vlan_valid(smi, val->port_vlan))\n\t\treturn -EINVAL;\n\n\tmemset(buf, '\\0', sizeof(smi->buf));\n\n\terr = smi->ops->get_vlan_4k(smi, val->port_vlan, &vlan4k);\n\tif (err)\n\t\treturn err;\n\n\tlen += snprintf(buf + len, sizeof(smi->buf) - len,\n\t\t\t\"VLAN %d: Ports: '\", vlan4k.vid);\n\n\tfor (i = 0; i < smi->num_ports; i++) {\n\t\tif (!(vlan4k.member & (1 << i)))\n\t\t\tcontinue;\n\n\t\tlen += snprintf(buf + len, sizeof(smi->buf) - len, \"%d%s\", i,\n\t\t\t\t(vlan4k.untag & (1 << i)) ? \"\" : \"t\");\n\t}\n\n\tlen += snprintf(buf + len, sizeof(smi->buf) - len,\n\t\t\t\"', members=%04x, untag=%04x, fid=%u\",\n\t\t\tvlan4k.member, vlan4k.untag, vlan4k.fid);\n\n\tval->value.s = buf;\n\tval->len = len;\n\n\treturn 0;\n}\nEXPORT_SYMBOL_GPL(rtl8366_sw_get_vlan_info);\n\nint rtl8366_sw_get_vlan_ports(struct switch_dev *dev, struct switch_val *val)\n{\n\tstruct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);\n\tstruct switch_port *port;\n\tstruct rtl8366_vlan_4k vlan4k;\n\tint i;\n\n\tif (!smi->ops->is_vlan_valid(smi, val->port_vlan))\n\t\treturn -EINVAL;\n\n\tsmi->ops->get_vlan_4k(smi, val->port_vlan, &vlan4k);\n\n\tport = &val->value.ports[0];\n\tval->len = 0;\n\tfor (i = 0; i < smi->num_ports; i++) {\n\t\tif (!(vlan4k.member & BIT(i)))\n\t\t\tcontinue;\n\n\t\tport->id = i;\n\t\tport->flags = (vlan4k.untag & BIT(i)) ?\n\t\t\t\t\t0 : BIT(SWITCH_PORT_FLAG_TAGGED);\n\t\tval->len++;\n\t\tport++;\n\t}\n\treturn 0;\n}\nEXPORT_SYMBOL_GPL(rtl8366_sw_get_vlan_ports);\n\nint rtl8366_sw_set_vlan_ports(struct switch_dev *dev, struct switch_val *val)\n{\n\tstruct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);\n\tstruct switch_port *port;\n\tu32 member = 0;\n\tu32 untag = 0;\n\tint err;\n\tint i;\n\n\tif (!smi->ops->is_vlan_valid(smi, val->port_vlan))\n\t\treturn -EINVAL;\n\n\tport = &val->value.ports[0];\n\tfor (i = 0; i < val->len; i++, port++) {\n\t\tint pvid = 0;\n\t\tmember |= BIT(port->id);\n\n\t\tif (!(port->flags & BIT(SWITCH_PORT_FLAG_TAGGED)))\n\t\t\tuntag |= BIT(port->id);\n\n\t\t/*\n\t\t * To ensure that we have a valid MC entry for this VLAN,\n\t\t * initialize the port VLAN ID here.\n\t\t */\n\t\terr = rtl8366_get_pvid(smi, port->id, &pvid);\n\t\tif (err < 0)\n\t\t\treturn err;\n\t\tif (pvid == 0) {\n\t\t\terr = rtl8366_set_pvid(smi, port->id, val->port_vlan);\n\t\t\tif (err < 0)\n\t\t\t\treturn err;\n\t\t}\n\t}\n\n\treturn rtl8366_set_vlan(smi, val->port_vlan, member, untag, 0);\n}\nEXPORT_SYMBOL_GPL(rtl8366_sw_set_vlan_ports);\n\nint rtl8366_sw_get_vlan_fid(struct switch_dev *dev,\n\t\t\t    const struct switch_attr *attr,\n\t\t\t    struct switch_val *val)\n{\n\tstruct rtl8366_vlan_4k vlan4k;\n\tstruct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);\n\tint err;\n\n\tif (!smi->ops->is_vlan_valid(smi, val->port_vlan))\n\t\treturn -EINVAL;\n\n\terr = smi->ops->get_vlan_4k(smi, val->port_vlan, &vlan4k);\n\tif (err)\n\t\treturn err;\n\n\tval->value.i = vlan4k.fid;\n\n\treturn 0;\n}\nEXPORT_SYMBOL_GPL(rtl8366_sw_get_vlan_fid);\n\nint rtl8366_sw_set_vlan_fid(struct switch_dev *dev,\n\t\t\t    const struct switch_attr *attr,\n\t\t\t    struct switch_val *val)\n{\n\tstruct rtl8366_vlan_4k vlan4k;\n\tstruct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);\n\tint err;\n\n\tif (!smi->ops->is_vlan_valid(smi, val->port_vlan))\n\t\treturn -EINVAL;\n\n\tif (val->value.i < 0 || val->value.i > attr->max)\n\t\treturn -EINVAL;\n\n\terr = smi->ops->get_vlan_4k(smi, val->port_vlan, &vlan4k);\n\tif (err)\n\t\treturn err;\n\n\treturn rtl8366_set_vlan(smi, val->port_vlan,\n\t\t\t\tvlan4k.member,\n\t\t\t\tvlan4k.untag,\n\t\t\t\tval->value.i);\n}\nEXPORT_SYMBOL_GPL(rtl8366_sw_set_vlan_fid);\n\nint rtl8366_sw_get_vlan_enable(struct switch_dev *dev,\n\t\t\t       const struct switch_attr *attr,\n\t\t\t       struct switch_val *val)\n{\n\tstruct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);\n\n\tif (attr->ofs > 2)\n\t\treturn -EINVAL;\n\n\tif (attr->ofs == 1)\n\t\tval->value.i = smi->vlan_enabled;\n\telse\n\t\tval->value.i = smi->vlan4k_enabled;\n\n\treturn 0;\n}\nEXPORT_SYMBOL_GPL(rtl8366_sw_get_vlan_enable);\n\nint rtl8366_sw_set_vlan_enable(struct switch_dev *dev,\n\t\t\t       const struct switch_attr *attr,\n\t\t\t       struct switch_val *val)\n{\n\tstruct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);\n\tint err;\n\n\tif (attr->ofs > 2)\n\t\treturn -EINVAL;\n\n\tif (attr->ofs == 1)\n\t\terr = rtl8366_enable_vlan(smi, val->value.i);\n\telse\n\t\terr = rtl8366_enable_vlan4k(smi, val->value.i);\n\n\treturn err;\n}\nEXPORT_SYMBOL_GPL(rtl8366_sw_set_vlan_enable);\n\nstruct rtl8366_smi *rtl8366_smi_alloc(struct device *parent)\n{\n\tstruct rtl8366_smi *smi;\n\n\tBUG_ON(!parent);\n\n\tsmi = kzalloc(sizeof(*smi), GFP_KERNEL);\n\tif (!smi) {\n\t\tdev_err(parent, \"no memory for private data\\n\");\n\t\treturn NULL;\n\t}\n\n\tsmi->parent = parent;\n\treturn smi;\n}\nEXPORT_SYMBOL_GPL(rtl8366_smi_alloc);\n\nstatic int __rtl8366_smi_init(struct rtl8366_smi *smi, const char *name)\n{\n\tint err;\n\n\tif (!smi->ext_mbus) {\n\t\terr = gpio_request(smi->gpio_sda, name);\n\t\tif (err) {\n\t\t\tprintk(KERN_ERR \"rtl8366_smi: gpio_request failed for %u, err=%d\\n\",\n\t\t\t\tsmi->gpio_sda, err);\n\t\t\tgoto err_out;\n\t\t}\n\n\t\terr = gpio_request(smi->gpio_sck, name);\n\t\tif (err) {\n\t\t\tprintk(KERN_ERR \"rtl8366_smi: gpio_request failed for %u, err=%d\\n\",\n\t\t\t\tsmi->gpio_sck, err);\n\t\t\tgoto err_free_sda;\n\t\t}\n\t}\n\n\tspin_lock_init(&smi->lock);\n\n\t/* start the switch */\n\tif (smi->hw_reset) {\n\t\tsmi->hw_reset(smi, false);\n\t\tmsleep(RTL8366_SMI_HW_START_DELAY);\n\t}\n\n\treturn 0;\n\n err_free_sda:\n\tgpio_free(smi->gpio_sda);\n err_out:\n\treturn err;\n}\n\nstatic void __rtl8366_smi_cleanup(struct rtl8366_smi *smi)\n{\n\tif (smi->hw_reset)\n\t\tsmi->hw_reset(smi, true);\n\n\tif (!smi->ext_mbus) {\n\t\tgpio_free(smi->gpio_sck);\n\t\tgpio_free(smi->gpio_sda);\n\t}\n}\n\nenum rtl8366_type rtl8366_smi_detect(struct rtl8366_platform_data *pdata)\n{\n\tstatic struct rtl8366_smi smi;\n\tenum rtl8366_type type = RTL8366_TYPE_UNKNOWN;\n\tu32 reg = 0;\n\n\tmemset(&smi, 0, sizeof(smi));\n\tsmi.gpio_sda = pdata->gpio_sda;\n\tsmi.gpio_sck = pdata->gpio_sck;\n\tsmi.clk_delay = 10;\n\tsmi.cmd_read  = 0xa9;\n\tsmi.cmd_write = 0xa8;\n\n\tif (__rtl8366_smi_init(&smi, \"rtl8366\"))\n\t\tgoto out;\n\n\tif (rtl8366_smi_read_reg(&smi, 0x5c, &reg))\n\t\tgoto cleanup;\n\n\tswitch(reg) {\n\tcase 0x6027:\n\t\tprintk(\"Found an RTL8366S switch\\n\");\n\t\ttype = RTL8366_TYPE_S;\n\t\tbreak;\n\tcase 0x5937:\n\t\tprintk(\"Found an RTL8366RB switch\\n\");\n\t\ttype = RTL8366_TYPE_RB;\n\t\tbreak;\n\tdefault:\n\t\tprintk(\"Found an Unknown RTL8366 switch (id=0x%04x)\\n\", reg);\n\t\tbreak;\n\t}\n\ncleanup:\n\t__rtl8366_smi_cleanup(&smi);\nout:\n\treturn type;\n}\n\nint rtl8366_smi_init(struct rtl8366_smi *smi)\n{\n\tint err;\n\n\tif (!smi->ops)\n\t\treturn -EINVAL;\n\n\terr = __rtl8366_smi_init(smi, dev_name(smi->parent));\n\tif (err)\n\t\tgoto err_out;\n\n\tif (!smi->ext_mbus)\n\t\tdev_info(smi->parent, \"using GPIO pins %u (SDA) and %u (SCK)\\n\",\n\t\t\t smi->gpio_sda, smi->gpio_sck);\n\telse\n\t\tdev_info(smi->parent, \"using MDIO bus '%s'\\n\", smi->ext_mbus->name);\n\n\terr = smi->ops->detect(smi);\n\tif (err) {\n\t\tdev_err(smi->parent, \"chip detection failed, err=%d\\n\", err);\n\t\tgoto err_free_sck;\n\t}\n\n\terr = rtl8366_reset(smi);\n\tif (err)\n\t\tgoto err_free_sck;\n\n\terr = smi->ops->setup(smi);\n\tif (err) {\n\t\tdev_err(smi->parent, \"chip setup failed, err=%d\\n\", err);\n\t\tgoto err_free_sck;\n\t}\n\n\terr = rtl8366_init_vlan(smi);\n\tif (err) {\n\t\tdev_err(smi->parent, \"VLAN initialization failed, err=%d\\n\",\n\t\t\terr);\n\t\tgoto err_free_sck;\n\t}\n\n\terr = rtl8366_enable_all_ports(smi, 1);\n\tif (err)\n\t\tgoto err_free_sck;\n\n\terr = rtl8366_smi_mii_init(smi);\n\tif (err)\n\t\tgoto err_free_sck;\n\n\trtl8366_debugfs_init(smi);\n\n\treturn 0;\n\n err_free_sck:\n\t__rtl8366_smi_cleanup(smi);\n err_out:\n\treturn err;\n}\nEXPORT_SYMBOL_GPL(rtl8366_smi_init);\n\nvoid rtl8366_smi_cleanup(struct rtl8366_smi *smi)\n{\n\trtl8366_debugfs_remove(smi);\n\trtl8366_smi_mii_cleanup(smi);\n\t__rtl8366_smi_cleanup(smi);\n}\nEXPORT_SYMBOL_GPL(rtl8366_smi_cleanup);\n\n#ifdef CONFIG_OF\nstatic void rtl8366_smi_reset(struct rtl8366_smi *smi, bool active)\n{\n\tif (active)\n\t\treset_control_assert(smi->reset);\n\telse\n\t\treset_control_deassert(smi->reset);\n}\n\nint rtl8366_smi_probe_of(struct platform_device *pdev, struct rtl8366_smi *smi)\n{\n\tint sck = of_get_named_gpio(pdev->dev.of_node, \"gpio-sck\", 0);\n\tint sda = of_get_named_gpio(pdev->dev.of_node, \"gpio-sda\", 0);\n\tstruct device_node *np = pdev->dev.of_node;\n\tstruct device_node *mdio_node;\n\n\tmdio_node = of_parse_phandle(np, \"mii-bus\", 0);\n\tif (!mdio_node) {\n\t\tdev_err(&pdev->dev, \"cannot find mdio node phandle\");\n\t\tgoto try_gpio;\n\t}\n\n\tsmi->ext_mbus = of_mdio_find_bus(mdio_node);\n\tif (!smi->ext_mbus) {\n\t\tdev_info(&pdev->dev,\n\t\t\t\"cannot find mdio bus from bus handle (yet)\");\n\t\tgoto try_gpio;\n\t}\n\n\treturn 0;\n\ntry_gpio:\n\tif (!gpio_is_valid(sck) || !gpio_is_valid(sda)) {\n\t\tif (!mdio_node) {\n\t\t\tdev_err(&pdev->dev, \"gpios missing in devictree\\n\");\n\t\t\treturn -EINVAL;\n\t\t} else {\n\t\t\treturn -EPROBE_DEFER;\n\t\t}\n\t}\n\n\tsmi->gpio_sda = sda;\n\tsmi->gpio_sck = sck;\n\tsmi->reset = devm_reset_control_get(&pdev->dev, \"switch\");\n\tif (!IS_ERR(smi->reset))\n\t\tsmi->hw_reset = rtl8366_smi_reset;\n\n\treturn 0;\n}\n#else\nstatic inline int rtl8366_smi_probe_of(struct platform_device *pdev, struct rtl8366_smi *smi)\n{\n\treturn -ENODEV;\n}\n#endif\n\nint rtl8366_smi_probe_plat(struct platform_device *pdev, struct rtl8366_smi *smi)\n{\n\tstruct rtl8366_platform_data *pdata = pdev->dev.platform_data;\n\n\tif (!pdev->dev.platform_data) {\n\t\tdev_err(&pdev->dev, \"no platform data specified\\n\");\n\t\treturn -EINVAL;\n\t}\n\n\tsmi->gpio_sda = pdata->gpio_sda;\n\tsmi->gpio_sck = pdata->gpio_sck;\n\tsmi->hw_reset = pdata->hw_reset;\n\n\treturn 0;\n}\n\n\nstruct rtl8366_smi *rtl8366_smi_probe(struct platform_device *pdev)\n{\n\tstruct rtl8366_smi *smi;\n\tint err;\n\n\tsmi = rtl8366_smi_alloc(&pdev->dev);\n\tif (!smi)\n\t\treturn NULL;\n\n\tif (pdev->dev.of_node)\n\t\terr = rtl8366_smi_probe_of(pdev, smi);\n\telse\n\t\terr = rtl8366_smi_probe_plat(pdev, smi);\n\n\tif (err)\n\t\tgoto free_smi;\n\n\treturn smi;\n\nfree_smi:\n\tkfree(smi);\n\treturn ERR_PTR(err);\n}\nEXPORT_SYMBOL_GPL(rtl8366_smi_probe);\n\nMODULE_DESCRIPTION(\"Realtek RTL8366 SMI interface driver\");\nMODULE_AUTHOR(\"Gabor Juhos <juhosg@openwrt.org>\");\nMODULE_LICENSE(\"GPL v2\");\n"
  },
  {
    "path": "target/linux/generic/files/drivers/net/phy/rtl8366_smi.h",
    "content": "/*\n * Realtek RTL8366 SMI interface driver defines\n *\n * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of the GNU General Public License version 2 as published\n * by the Free Software Foundation.\n */\n\n#ifndef _RTL8366_SMI_H\n#define _RTL8366_SMI_H\n\n#include <linux/phy.h>\n#include <linux/switch.h>\n#include <linux/platform_device.h>\n#include <linux/reset.h>\n\nstruct rtl8366_smi_ops;\nstruct rtl8366_vlan_ops;\nstruct mii_bus;\nstruct dentry;\nstruct inode;\nstruct file;\n\nstruct rtl8366_mib_counter {\n\tunsigned\tbase;\n\tunsigned\toffset;\n\tunsigned\tlength;\n\tconst char\t*name;\n};\n\nstruct rtl8366_smi {\n\tstruct device\t\t*parent;\n\tunsigned int\t\tgpio_sda;\n\tunsigned int\t\tgpio_sck;\n\tvoid\t\t\t(*hw_reset)(struct rtl8366_smi *smi, bool active);\n\tunsigned int\t\tclk_delay;\t/* ns */\n\tu8\t\t\tcmd_read;\n\tu8\t\t\tcmd_write;\n\tspinlock_t\t\tlock;\n\tstruct mii_bus\t\t*mii_bus;\n\tint\t\t\tmii_irq[PHY_MAX_ADDR];\n\tstruct switch_dev\tsw_dev;\n\n\tunsigned int\t\tcpu_port;\n\tunsigned int\t\tnum_ports;\n\tunsigned int\t\tnum_vlan_mc;\n\tunsigned int\t\tnum_mib_counters;\n\tstruct rtl8366_mib_counter *mib_counters;\n\n\tstruct rtl8366_smi_ops\t*ops;\n\n\tint\t\t\tvlan_enabled;\n\tint\t\t\tvlan4k_enabled;\n\n\tchar\t\t\tbuf[4096];\n\n\tstruct reset_control\t*reset;\n\n#ifdef CONFIG_RTL8366_SMI_DEBUG_FS\n\tstruct dentry           *debugfs_root;\n\tu16\t\t\tdbg_reg;\n\tu8\t\t\tdbg_vlan_4k_page;\n#endif\n\tstruct mii_bus\t\t*ext_mbus;\n};\n\nstruct rtl8366_vlan_mc {\n\tu16\tvid;\n\tu16\tuntag;\n\tu16\tmember;\n\tu8\tfid;\n\tu8\tpriority;\n};\n\nstruct rtl8366_vlan_4k {\n\tu16\tvid;\n\tu16\tuntag;\n\tu16\tmember;\n\tu8\tfid;\n};\n\nstruct rtl8366_smi_ops {\n\tint\t(*detect)(struct rtl8366_smi *smi);\n\tint\t(*reset_chip)(struct rtl8366_smi *smi);\n\tint\t(*setup)(struct rtl8366_smi *smi);\n\n\tint\t(*mii_read)(struct mii_bus *bus, int addr, int reg);\n\tint\t(*mii_write)(struct mii_bus *bus, int addr, int reg, u16 val);\n\n\tint\t(*get_vlan_mc)(struct rtl8366_smi *smi, u32 index,\n\t\t\t       struct rtl8366_vlan_mc *vlanmc);\n\tint\t(*set_vlan_mc)(struct rtl8366_smi *smi, u32 index,\n\t\t\t       const struct rtl8366_vlan_mc *vlanmc);\n\tint\t(*get_vlan_4k)(struct rtl8366_smi *smi, u32 vid,\n\t\t\t       struct rtl8366_vlan_4k *vlan4k);\n\tint\t(*set_vlan_4k)(struct rtl8366_smi *smi,\n\t\t\t       const struct rtl8366_vlan_4k *vlan4k);\n\tint\t(*get_mc_index)(struct rtl8366_smi *smi, int port, int *val);\n\tint\t(*set_mc_index)(struct rtl8366_smi *smi, int port, int index);\n\tint\t(*get_mib_counter)(struct rtl8366_smi *smi, int counter,\n\t\t\t\t   int port, unsigned long long *val);\n\tint\t(*is_vlan_valid)(struct rtl8366_smi *smi, unsigned vlan);\n\tint\t(*enable_vlan)(struct rtl8366_smi *smi, int enable);\n\tint\t(*enable_vlan4k)(struct rtl8366_smi *smi, int enable);\n\tint\t(*enable_port)(struct rtl8366_smi *smi, int port, int enable);\n};\n\nstruct rtl8366_smi *rtl8366_smi_alloc(struct device *parent);\nint rtl8366_smi_init(struct rtl8366_smi *smi);\nvoid rtl8366_smi_cleanup(struct rtl8366_smi *smi);\nint rtl8366_smi_write_reg(struct rtl8366_smi *smi, u32 addr, u32 data);\nint rtl8366_smi_write_reg_noack(struct rtl8366_smi *smi, u32 addr, u32 data);\nint rtl8366_smi_read_reg(struct rtl8366_smi *smi, u32 addr, u32 *data);\nint rtl8366_smi_rmwr(struct rtl8366_smi *smi, u32 addr, u32 mask, u32 data);\n\nint rtl8366_reset_vlan(struct rtl8366_smi *smi);\nint rtl8366_enable_vlan(struct rtl8366_smi *smi, int enable);\nint rtl8366_enable_all_ports(struct rtl8366_smi *smi, int enable);\n\n#ifdef CONFIG_RTL8366_SMI_DEBUG_FS\nint rtl8366_debugfs_open(struct inode *inode, struct file *file);\n#endif\n\nstatic inline struct rtl8366_smi *sw_to_rtl8366_smi(struct switch_dev *sw)\n{\n\treturn container_of(sw, struct rtl8366_smi, sw_dev);\n}\n\nint rtl8366_sw_reset_switch(struct switch_dev *dev);\nint rtl8366_sw_get_port_pvid(struct switch_dev *dev, int port, int *val);\nint rtl8366_sw_set_port_pvid(struct switch_dev *dev, int port, int val);\nint rtl8366_sw_get_port_mib(struct switch_dev *dev,\n\t\t\t    const struct switch_attr *attr,\n\t\t\t    struct switch_val *val);\nint rtl8366_sw_get_vlan_info(struct switch_dev *dev,\n\t\t\t     const struct switch_attr *attr,\n\t\t\t     struct switch_val *val);\nint rtl8366_sw_get_vlan_fid(struct switch_dev *dev,\n\t\t\t     const struct switch_attr *attr,\n\t\t\t     struct switch_val *val);\nint rtl8366_sw_set_vlan_fid(struct switch_dev *dev,\n\t\t\t     const struct switch_attr *attr,\n\t\t\t     struct switch_val *val);\nint rtl8366_sw_get_vlan_ports(struct switch_dev *dev, struct switch_val *val);\nint rtl8366_sw_set_vlan_ports(struct switch_dev *dev, struct switch_val *val);\nint rtl8366_sw_get_vlan_enable(struct switch_dev *dev,\n\t\t\t       const struct switch_attr *attr,\n\t\t\t       struct switch_val *val);\nint rtl8366_sw_set_vlan_enable(struct switch_dev *dev,\n\t\t\t       const struct switch_attr *attr,\n\t\t\t       struct switch_val *val);\nint rtl8366_sw_get_port_stats(struct switch_dev *dev, int port,\n\t\t\t\tstruct switch_port_stats *stats,\n\t\t\t\tint txb_id, int rxb_id);\n\nstruct rtl8366_smi* rtl8366_smi_probe(struct platform_device *pdev);\n\n#endif /*  _RTL8366_SMI_H */\n"
  },
  {
    "path": "target/linux/generic/files/drivers/net/phy/rtl8366rb.c",
    "content": "/*\n * Platform driver for the Realtek RTL8366RB ethernet switch\n *\n * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>\n * Copyright (C) 2010 Antti Seppälä <a.seppala@gmail.com>\n * Copyright (C) 2010 Roman Yeryomin <roman@advem.lv>\n * Copyright (C) 2011 Colin Leitner <colin.leitner@googlemail.com>\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of the GNU General Public License version 2 as published\n * by the Free Software Foundation.\n */\n\n#include <linux/kernel.h>\n#include <linux/module.h>\n#include <linux/init.h>\n#include <linux/device.h>\n#include <linux/of.h>\n#include <linux/of_platform.h>\n#include <linux/delay.h>\n#include <linux/skbuff.h>\n#include <linux/rtl8366.h>\n\n#include \"rtl8366_smi.h\"\n\n#define RTL8366RB_DRIVER_DESC\t\"Realtek RTL8366RB ethernet switch driver\"\n#define RTL8366RB_DRIVER_VER\t\"0.2.4\"\n\n#define RTL8366RB_PHY_NO_MAX\t4\n#define RTL8366RB_PHY_PAGE_MAX\t7\n#define RTL8366RB_PHY_ADDR_MAX\t31\n\n/* Switch Global Configuration register */\n#define RTL8366RB_SGCR\t\t\t\t0x0000\n#define RTL8366RB_SGCR_EN_BC_STORM_CTRL\t\tBIT(0)\n#define RTL8366RB_SGCR_MAX_LENGTH(_x)\t\t(_x << 4)\n#define RTL8366RB_SGCR_MAX_LENGTH_MASK\t\tRTL8366RB_SGCR_MAX_LENGTH(0x3)\n#define RTL8366RB_SGCR_MAX_LENGTH_1522\t\tRTL8366RB_SGCR_MAX_LENGTH(0x0)\n#define RTL8366RB_SGCR_MAX_LENGTH_1536\t\tRTL8366RB_SGCR_MAX_LENGTH(0x1)\n#define RTL8366RB_SGCR_MAX_LENGTH_1552\t\tRTL8366RB_SGCR_MAX_LENGTH(0x2)\n#define RTL8366RB_SGCR_MAX_LENGTH_9216\t\tRTL8366RB_SGCR_MAX_LENGTH(0x3)\n#define RTL8366RB_SGCR_EN_VLAN\t\t\tBIT(13)\n#define RTL8366RB_SGCR_EN_VLAN_4KTB\t\tBIT(14)\n\n/* Port Enable Control register */\n#define RTL8366RB_PECR\t\t\t\t0x0001\n\n/* Port Mirror Control Register */\n#define RTL8366RB_PMCR\t\t\t\t0x0007\n#define RTL8366RB_PMCR_SOURCE_PORT(_x)\t\t(_x)\n#define RTL8366RB_PMCR_SOURCE_PORT_MASK\t\t0x000f\n#define RTL8366RB_PMCR_MONITOR_PORT(_x)\t\t((_x) << 4)\n#define RTL8366RB_PMCR_MONITOR_PORT_MASK\t0x00f0\n#define RTL8366RB_PMCR_MIRROR_RX\t\tBIT(8)\n#define RTL8366RB_PMCR_MIRROR_TX\t\tBIT(9)\n#define RTL8366RB_PMCR_MIRROR_SPC\t\tBIT(10)\n#define RTL8366RB_PMCR_MIRROR_ISO\t\tBIT(11)\n\n/* Switch Security Control registers */\n#define RTL8366RB_SSCR0\t\t\t\t0x0002\n#define RTL8366RB_SSCR1\t\t\t\t0x0003\n#define RTL8366RB_SSCR2\t\t\t\t0x0004\n#define RTL8366RB_SSCR2_DROP_UNKNOWN_DA\t\tBIT(0)\n\n#define RTL8366RB_RESET_CTRL_REG\t\t0x0100\n#define RTL8366RB_CHIP_CTRL_RESET_HW\t\t1\n#define RTL8366RB_CHIP_CTRL_RESET_SW\t\t(1 << 1)\n\n#define RTL8366RB_CHIP_VERSION_CTRL_REG\t\t0x050A\n#define RTL8366RB_CHIP_VERSION_MASK\t\t0xf\n#define RTL8366RB_CHIP_ID_REG\t\t\t0x0509\n#define RTL8366RB_CHIP_ID_8366\t\t\t0x5937\n\n/* PHY registers control */\n#define RTL8366RB_PHY_ACCESS_CTRL_REG\t\t0x8000\n#define RTL8366RB_PHY_ACCESS_DATA_REG\t\t0x8002\n\n#define RTL8366RB_PHY_CTRL_READ\t\t\t1\n#define RTL8366RB_PHY_CTRL_WRITE\t\t0\n\n#define RTL8366RB_PHY_REG_MASK\t\t\t0x1f\n#define RTL8366RB_PHY_PAGE_OFFSET\t\t5\n#define RTL8366RB_PHY_PAGE_MASK\t\t\t(0xf << 5)\n#define RTL8366RB_PHY_NO_OFFSET\t\t\t9\n#define RTL8366RB_PHY_NO_MASK\t\t\t(0x1f << 9)\n\n#define RTL8366RB_VLAN_INGRESS_CTRL2_REG\t0x037f\n\n/* LED control registers */\n#define RTL8366RB_LED_BLINKRATE_REG\t\t0x0430\n#define RTL8366RB_LED_BLINKRATE_BIT\t\t0\n#define RTL8366RB_LED_BLINKRATE_MASK\t\t0x0007\n\n#define RTL8366RB_LED_CTRL_REG\t\t\t0x0431\n#define RTL8366RB_LED_0_1_CTRL_REG\t\t0x0432\n#define RTL8366RB_LED_2_3_CTRL_REG\t\t0x0433\n\n#define RTL8366RB_MIB_COUNT\t\t\t33\n#define RTL8366RB_GLOBAL_MIB_COUNT\t\t1\n#define RTL8366RB_MIB_COUNTER_PORT_OFFSET\t0x0050\n#define RTL8366RB_MIB_COUNTER_BASE\t\t0x1000\n#define RTL8366RB_MIB_CTRL_REG\t\t\t0x13F0\n#define RTL8366RB_MIB_CTRL_USER_MASK\t\t0x0FFC\n#define RTL8366RB_MIB_CTRL_BUSY_MASK\t\tBIT(0)\n#define RTL8366RB_MIB_CTRL_RESET_MASK\t\tBIT(1)\n#define RTL8366RB_MIB_CTRL_PORT_RESET(_p)\tBIT(2 + (_p))\n#define RTL8366RB_MIB_CTRL_GLOBAL_RESET\t\tBIT(11)\n\n#define RTL8366RB_PORT_VLAN_CTRL_BASE\t\t0x0063\n#define RTL8366RB_PORT_VLAN_CTRL_REG(_p)  \\\n\t\t(RTL8366RB_PORT_VLAN_CTRL_BASE + (_p) / 4)\n#define RTL8366RB_PORT_VLAN_CTRL_MASK\t\t0xf\n#define RTL8366RB_PORT_VLAN_CTRL_SHIFT(_p)\t(4 * ((_p) % 4))\n\n\n#define RTL8366RB_VLAN_TABLE_READ_BASE\t\t0x018C\n#define RTL8366RB_VLAN_TABLE_WRITE_BASE\t\t0x0185\n\n\n#define RTL8366RB_TABLE_ACCESS_CTRL_REG\t\t0x0180\n#define RTL8366RB_TABLE_VLAN_READ_CTRL\t\t0x0E01\n#define RTL8366RB_TABLE_VLAN_WRITE_CTRL\t\t0x0F01\n\n#define RTL8366RB_VLAN_MC_BASE(_x)\t\t(0x0020 + (_x) * 3)\n\n\n#define RTL8366RB_PORT_LINK_STATUS_BASE\t\t0x0014\n#define RTL8366RB_PORT_STATUS_SPEED_MASK\t0x0003\n#define RTL8366RB_PORT_STATUS_DUPLEX_MASK\t0x0004\n#define RTL8366RB_PORT_STATUS_LINK_MASK\t\t0x0010\n#define RTL8366RB_PORT_STATUS_TXPAUSE_MASK\t0x0020\n#define RTL8366RB_PORT_STATUS_RXPAUSE_MASK\t0x0040\n#define RTL8366RB_PORT_STATUS_AN_MASK\t\t0x0080\n\n\n#define RTL8366RB_PORT_NUM_CPU\t\t5\n#define RTL8366RB_NUM_PORTS\t\t6\n#define RTL8366RB_NUM_VLANS\t\t16\n#define RTL8366RB_NUM_LEDGROUPS\t\t4\n#define RTL8366RB_NUM_VIDS\t\t4096\n#define RTL8366RB_PRIORITYMAX\t\t7\n#define RTL8366RB_FIDMAX\t\t7\n\n\n#define RTL8366RB_PORT_1\t\t(1 << 0) /* In userspace port 0 */\n#define RTL8366RB_PORT_2\t\t(1 << 1) /* In userspace port 1 */\n#define RTL8366RB_PORT_3\t\t(1 << 2) /* In userspace port 2 */\n#define RTL8366RB_PORT_4\t\t(1 << 3) /* In userspace port 3 */\n#define RTL8366RB_PORT_5\t\t(1 << 4) /* In userspace port 4 */\n\n#define RTL8366RB_PORT_CPU\t\t(1 << 5) /* CPU port */\n\n#define RTL8366RB_PORT_ALL\t\t(RTL8366RB_PORT_1 |\t\\\n\t\t\t\t\t RTL8366RB_PORT_2 |\t\\\n\t\t\t\t\t RTL8366RB_PORT_3 |\t\\\n\t\t\t\t\t RTL8366RB_PORT_4 |\t\\\n\t\t\t\t\t RTL8366RB_PORT_5 |\t\\\n\t\t\t\t\t RTL8366RB_PORT_CPU)\n\n#define RTL8366RB_PORT_ALL_BUT_CPU\t(RTL8366RB_PORT_1 |\t\\\n\t\t\t\t\t RTL8366RB_PORT_2 |\t\\\n\t\t\t\t\t RTL8366RB_PORT_3 |\t\\\n\t\t\t\t\t RTL8366RB_PORT_4 |\t\\\n\t\t\t\t\t RTL8366RB_PORT_5)\n\n#define RTL8366RB_PORT_ALL_EXTERNAL\t(RTL8366RB_PORT_1 |\t\\\n\t\t\t\t\t RTL8366RB_PORT_2 |\t\\\n\t\t\t\t\t RTL8366RB_PORT_3 |\t\\\n\t\t\t\t\t RTL8366RB_PORT_4)\n\n#define RTL8366RB_PORT_ALL_INTERNAL\t RTL8366RB_PORT_CPU\n\n#define RTL8366RB_VLAN_VID_MASK\t\t0xfff\n#define RTL8366RB_VLAN_PRIORITY_SHIFT\t12\n#define RTL8366RB_VLAN_PRIORITY_MASK\t0x7\n#define RTL8366RB_VLAN_UNTAG_SHIFT\t8\n#define RTL8366RB_VLAN_UNTAG_MASK\t0xff\n#define RTL8366RB_VLAN_MEMBER_MASK\t0xff\n#define RTL8366RB_VLAN_FID_MASK\t\t0x7\n\n\n/* Port ingress bandwidth control */\n#define RTL8366RB_IB_BASE\t\t0x0200\n#define RTL8366RB_IB_REG(pnum)\t\t(RTL8366RB_IB_BASE + pnum)\n#define RTL8366RB_IB_BDTH_MASK\t\t0x3fff\n#define RTL8366RB_IB_PREIFG_OFFSET\t14\n#define RTL8366RB_IB_PREIFG_MASK\t(1 << RTL8366RB_IB_PREIFG_OFFSET)\n\n/* Port egress bandwidth control */\n#define RTL8366RB_EB_BASE\t\t0x02d1\n#define RTL8366RB_EB_REG(pnum)\t\t(RTL8366RB_EB_BASE + pnum)\n#define RTL8366RB_EB_BDTH_MASK\t\t0x3fff\n#define RTL8366RB_EB_PREIFG_REG\t0x02f8\n#define RTL8366RB_EB_PREIFG_OFFSET\t9\n#define RTL8366RB_EB_PREIFG_MASK\t(1 << RTL8366RB_EB_PREIFG_OFFSET)\n\n#define RTL8366RB_BDTH_SW_MAX\t\t1048512\n#define RTL8366RB_BDTH_UNIT\t\t64\n#define RTL8366RB_BDTH_REG_DEFAULT\t16383\n\n/* QOS */\n#define RTL8366RB_QOS_BIT\t\t15\n#define RTL8366RB_QOS_MASK\t\t(1 << RTL8366RB_QOS_BIT)\n/* Include/Exclude Preamble and IFG (20 bytes). 0:Exclude, 1:Include. */\n#define RTL8366RB_QOS_DEFAULT_PREIFG\t1\n\n\n#define RTL8366RB_MIB_RXB_ID\t\t0\t/* IfInOctets */\n#define RTL8366RB_MIB_TXB_ID\t\t20\t/* IfOutOctets */\n\nstatic struct rtl8366_mib_counter rtl8366rb_mib_counters[] = {\n\t{ 0,  0, 4, \"IfInOctets\"\t\t\t\t},\n\t{ 0,  4, 4, \"EtherStatsOctets\"\t\t\t\t},\n\t{ 0,  8, 2, \"EtherStatsUnderSizePkts\"\t\t\t},\n\t{ 0, 10, 2, \"EtherFragments\"\t\t\t\t},\n\t{ 0, 12, 2, \"EtherStatsPkts64Octets\"\t\t\t},\n\t{ 0, 14, 2, \"EtherStatsPkts65to127Octets\"\t\t},\n\t{ 0, 16, 2, \"EtherStatsPkts128to255Octets\"\t\t},\n\t{ 0, 18, 2, \"EtherStatsPkts256to511Octets\"\t\t},\n\t{ 0, 20, 2, \"EtherStatsPkts512to1023Octets\"\t\t},\n\t{ 0, 22, 2, \"EtherStatsPkts1024to1518Octets\"\t\t},\n\t{ 0, 24, 2, \"EtherOversizeStats\"\t\t\t},\n\t{ 0, 26, 2, \"EtherStatsJabbers\"\t\t\t\t},\n\t{ 0, 28, 2, \"IfInUcastPkts\"\t\t\t\t},\n\t{ 0, 30, 2, \"EtherStatsMulticastPkts\"\t\t\t},\n\t{ 0, 32, 2, \"EtherStatsBroadcastPkts\"\t\t\t},\n\t{ 0, 34, 2, \"EtherStatsDropEvents\"\t\t\t},\n\t{ 0, 36, 2, \"Dot3StatsFCSErrors\"\t\t\t},\n\t{ 0, 38, 2, \"Dot3StatsSymbolErrors\"\t\t\t},\n\t{ 0, 40, 2, \"Dot3InPauseFrames\"\t\t\t\t},\n\t{ 0, 42, 2, \"Dot3ControlInUnknownOpcodes\"\t\t},\n\t{ 0, 44, 4, \"IfOutOctets\"\t\t\t\t},\n\t{ 0, 48, 2, \"Dot3StatsSingleCollisionFrames\"\t\t},\n\t{ 0, 50, 2, \"Dot3StatMultipleCollisionFrames\"\t\t},\n\t{ 0, 52, 2, \"Dot3sDeferredTransmissions\"\t\t},\n\t{ 0, 54, 2, \"Dot3StatsLateCollisions\"\t\t\t},\n\t{ 0, 56, 2, \"EtherStatsCollisions\"\t\t\t},\n\t{ 0, 58, 2, \"Dot3StatsExcessiveCollisions\"\t\t},\n\t{ 0, 60, 2, \"Dot3OutPauseFrames\"\t\t\t},\n\t{ 0, 62, 2, \"Dot1dBasePortDelayExceededDiscards\"\t},\n\t{ 0, 64, 2, \"Dot1dTpPortInDiscards\"\t\t\t},\n\t{ 0, 66, 2, \"IfOutUcastPkts\"\t\t\t\t},\n\t{ 0, 68, 2, \"IfOutMulticastPkts\"\t\t\t},\n\t{ 0, 70, 2, \"IfOutBroadcastPkts\"\t\t\t},\n};\n\n#define REG_WR(_smi, _reg, _val)\t\t\t\t\t\\\n\tdo {\t\t\t\t\t\t\t\t\\\n\t\terr = rtl8366_smi_write_reg(_smi, _reg, _val);\t\t\\\n\t\tif (err)\t\t\t\t\t\t\\\n\t\t\treturn err;\t\t\t\t\t\\\n\t} while (0)\n\n#define REG_RMW(_smi, _reg, _mask, _val)\t\t\t\t\\\n\tdo {\t\t\t\t\t\t\t\t\\\n\t\terr = rtl8366_smi_rmwr(_smi, _reg, _mask, _val);\t\\\n\t\tif (err)\t\t\t\t\t\t\\\n\t\t\treturn err;\t\t\t\t\t\\\n\t} while (0)\n\nstatic int rtl8366rb_reset_chip(struct rtl8366_smi *smi)\n{\n\tint timeout = 10;\n\tu32 data;\n\n\trtl8366_smi_write_reg_noack(smi, RTL8366RB_RESET_CTRL_REG,\n\t\t\t \t    RTL8366RB_CHIP_CTRL_RESET_HW);\n\tdo {\n\t\tmsleep(1);\n\t\tif (rtl8366_smi_read_reg(smi, RTL8366RB_RESET_CTRL_REG, &data))\n\t\t\treturn -EIO;\n\n\t\tif (!(data & RTL8366RB_CHIP_CTRL_RESET_HW))\n\t\t\tbreak;\n\t} while (--timeout);\n\n\tif (!timeout) {\n\t\tprintk(\"Timeout waiting for the switch to reset\\n\");\n\t\treturn -EIO;\n\t}\n\n\treturn 0;\n}\n\nstatic int rtl8366rb_setup(struct rtl8366_smi *smi)\n{\n\tint err;\n#ifdef CONFIG_OF\n\tunsigned i;\n\tstruct device_node *np;\n\tunsigned num_initvals;\n\tconst __be32 *paddr;\n\n\tnp = smi->parent->of_node;\n\n\tpaddr = of_get_property(np, \"realtek,initvals\", &num_initvals);\n\tif (paddr) {\n\t\tdev_info(smi->parent, \"applying initvals from DTS\\n\");\n\n\t\tif (num_initvals < (2 * sizeof(*paddr)))\n\t\t\treturn -EINVAL;\n\n\t\tnum_initvals /= sizeof(*paddr);\n\n\t\tfor (i = 0; i < num_initvals - 1; i += 2) {\n\t\t\tu32 reg = be32_to_cpup(paddr + i);\n\t\t\tu32 val = be32_to_cpup(paddr + i + 1);\n\n\t\t\tREG_WR(smi, reg, val);\n\t\t}\n\t}\n#endif\n\n\t/* set maximum packet length to 1536 bytes */\n\tREG_RMW(smi, RTL8366RB_SGCR, RTL8366RB_SGCR_MAX_LENGTH_MASK,\n\t\tRTL8366RB_SGCR_MAX_LENGTH_1536);\n\n\t/* enable learning for all ports */\n\tREG_WR(smi, RTL8366RB_SSCR0, 0);\n\n\t/* enable auto ageing for all ports */\n\tREG_WR(smi, RTL8366RB_SSCR1, 0);\n\n\t/*\n\t * discard VLAN tagged packets if the port is not a member of\n\t * the VLAN with which the packets is associated.\n\t */\n\tREG_WR(smi, RTL8366RB_VLAN_INGRESS_CTRL2_REG, RTL8366RB_PORT_ALL);\n\n\t/* don't drop packets whose DA has not been learned */\n\tREG_RMW(smi, RTL8366RB_SSCR2, RTL8366RB_SSCR2_DROP_UNKNOWN_DA, 0);\n\n\treturn 0;\n}\n\nstatic int rtl8366rb_read_phy_reg(struct rtl8366_smi *smi,\n\t\t\t\t u32 phy_no, u32 page, u32 addr, u32 *data)\n{\n\tu32 reg;\n\tint ret;\n\n\tif (phy_no > RTL8366RB_PHY_NO_MAX)\n\t\treturn -EINVAL;\n\n\tif (page > RTL8366RB_PHY_PAGE_MAX)\n\t\treturn -EINVAL;\n\n\tif (addr > RTL8366RB_PHY_ADDR_MAX)\n\t\treturn -EINVAL;\n\n\tret = rtl8366_smi_write_reg(smi, RTL8366RB_PHY_ACCESS_CTRL_REG,\n\t\t\t\t    RTL8366RB_PHY_CTRL_READ);\n\tif (ret)\n\t\treturn ret;\n\n\treg = 0x8000 | (1 << (phy_no + RTL8366RB_PHY_NO_OFFSET)) |\n\t      ((page << RTL8366RB_PHY_PAGE_OFFSET) & RTL8366RB_PHY_PAGE_MASK) |\n\t      (addr & RTL8366RB_PHY_REG_MASK);\n\n\tret = rtl8366_smi_write_reg(smi, reg, 0);\n\tif (ret)\n\t\treturn ret;\n\n\tret = rtl8366_smi_read_reg(smi, RTL8366RB_PHY_ACCESS_DATA_REG, data);\n\tif (ret)\n\t\treturn ret;\n\n\treturn 0;\n}\n\nstatic int rtl8366rb_write_phy_reg(struct rtl8366_smi *smi,\n\t\t\t\t  u32 phy_no, u32 page, u32 addr, u32 data)\n{\n\tu32 reg;\n\tint ret;\n\n\tif (phy_no > RTL8366RB_PHY_NO_MAX)\n\t\treturn -EINVAL;\n\n\tif (page > RTL8366RB_PHY_PAGE_MAX)\n\t\treturn -EINVAL;\n\n\tif (addr > RTL8366RB_PHY_ADDR_MAX)\n\t\treturn -EINVAL;\n\n\tret = rtl8366_smi_write_reg(smi, RTL8366RB_PHY_ACCESS_CTRL_REG,\n\t\t\t\t    RTL8366RB_PHY_CTRL_WRITE);\n\tif (ret)\n\t\treturn ret;\n\n\treg = 0x8000 | (1 << (phy_no + RTL8366RB_PHY_NO_OFFSET)) |\n\t      ((page << RTL8366RB_PHY_PAGE_OFFSET) & RTL8366RB_PHY_PAGE_MASK) |\n\t      (addr & RTL8366RB_PHY_REG_MASK);\n\n\tret = rtl8366_smi_write_reg(smi, reg, data);\n\tif (ret)\n\t\treturn ret;\n\n\treturn 0;\n}\n\nstatic int rtl8366rb_get_mib_counter(struct rtl8366_smi *smi, int counter,\n\t\t\t\t     int port, unsigned long long *val)\n{\n\tint i;\n\tint err;\n\tu32 addr, data;\n\tu64 mibvalue;\n\n\tif (port > RTL8366RB_NUM_PORTS || counter >= RTL8366RB_MIB_COUNT)\n\t\treturn -EINVAL;\n\n\taddr = RTL8366RB_MIB_COUNTER_BASE +\n\t       RTL8366RB_MIB_COUNTER_PORT_OFFSET * (port) +\n\t       rtl8366rb_mib_counters[counter].offset;\n\n\t/*\n\t * Writing access counter address first\n\t * then ASIC will prepare 64bits counter wait for being retrived\n\t */\n\tdata = 0; /* writing data will be discard by ASIC */\n\terr = rtl8366_smi_write_reg(smi, addr, data);\n\tif (err)\n\t\treturn err;\n\n\t/* read MIB control register */\n\terr =  rtl8366_smi_read_reg(smi, RTL8366RB_MIB_CTRL_REG, &data);\n\tif (err)\n\t\treturn err;\n\n\tif (data & RTL8366RB_MIB_CTRL_BUSY_MASK)\n\t\treturn -EBUSY;\n\n\tif (data & RTL8366RB_MIB_CTRL_RESET_MASK)\n\t\treturn -EIO;\n\n\tmibvalue = 0;\n\tfor (i = rtl8366rb_mib_counters[counter].length; i > 0; i--) {\n\t\terr = rtl8366_smi_read_reg(smi, addr + (i - 1), &data);\n\t\tif (err)\n\t\t\treturn err;\n\n\t\tmibvalue = (mibvalue << 16) | (data & 0xFFFF);\n\t}\n\n\t*val = mibvalue;\n\treturn 0;\n}\n\nstatic int rtl8366rb_get_vlan_4k(struct rtl8366_smi *smi, u32 vid,\n\t\t\t\t struct rtl8366_vlan_4k *vlan4k)\n{\n\tu32 data[3];\n\tint err;\n\tint i;\n\n\tmemset(vlan4k, '\\0', sizeof(struct rtl8366_vlan_4k));\n\n\tif (vid >= RTL8366RB_NUM_VIDS)\n\t\treturn -EINVAL;\n\n\t/* write VID */\n\terr = rtl8366_smi_write_reg(smi, RTL8366RB_VLAN_TABLE_WRITE_BASE,\n\t\t\t\t    vid & RTL8366RB_VLAN_VID_MASK);\n\tif (err)\n\t\treturn err;\n\n\t/* write table access control word */\n\terr = rtl8366_smi_write_reg(smi, RTL8366RB_TABLE_ACCESS_CTRL_REG,\n\t\t\t\t    RTL8366RB_TABLE_VLAN_READ_CTRL);\n\tif (err)\n\t\treturn err;\n\n\tfor (i = 0; i < 3; i++) {\n\t\terr = rtl8366_smi_read_reg(smi,\n\t\t\t\t\t   RTL8366RB_VLAN_TABLE_READ_BASE + i,\n\t\t\t\t\t   &data[i]);\n\t\tif (err)\n\t\t\treturn err;\n\t}\n\n\tvlan4k->vid = vid;\n\tvlan4k->untag = (data[1] >> RTL8366RB_VLAN_UNTAG_SHIFT) &\n\t\t\tRTL8366RB_VLAN_UNTAG_MASK;\n\tvlan4k->member = data[1] & RTL8366RB_VLAN_MEMBER_MASK;\n\tvlan4k->fid = data[2] & RTL8366RB_VLAN_FID_MASK;\n\n\treturn 0;\n}\n\nstatic int rtl8366rb_set_vlan_4k(struct rtl8366_smi *smi,\n\t\t\t\t const struct rtl8366_vlan_4k *vlan4k)\n{\n\tu32 data[3];\n\tint err;\n\tint i;\n\n\tif (vlan4k->vid >= RTL8366RB_NUM_VIDS ||\n\t    vlan4k->member > RTL8366RB_VLAN_MEMBER_MASK ||\n\t    vlan4k->untag > RTL8366RB_VLAN_UNTAG_MASK ||\n\t    vlan4k->fid > RTL8366RB_FIDMAX)\n\t\treturn -EINVAL;\n\n\tdata[0] = vlan4k->vid & RTL8366RB_VLAN_VID_MASK;\n\tdata[1] = (vlan4k->member & RTL8366RB_VLAN_MEMBER_MASK) |\n\t\t  ((vlan4k->untag & RTL8366RB_VLAN_UNTAG_MASK) <<\n\t\t\tRTL8366RB_VLAN_UNTAG_SHIFT);\n\tdata[2] = vlan4k->fid & RTL8366RB_VLAN_FID_MASK;\n\n\tfor (i = 0; i < 3; i++) {\n\t\terr = rtl8366_smi_write_reg(smi,\n\t\t\t\t\t    RTL8366RB_VLAN_TABLE_WRITE_BASE + i,\n\t\t\t\t\t    data[i]);\n\t\tif (err)\n\t\t\treturn err;\n\t}\n\n\t/* write table access control word */\n\terr = rtl8366_smi_write_reg(smi, RTL8366RB_TABLE_ACCESS_CTRL_REG,\n\t\t\t\t    RTL8366RB_TABLE_VLAN_WRITE_CTRL);\n\n\treturn err;\n}\n\nstatic int rtl8366rb_get_vlan_mc(struct rtl8366_smi *smi, u32 index,\n\t\t\t\t struct rtl8366_vlan_mc *vlanmc)\n{\n\tu32 data[3];\n\tint err;\n\tint i;\n\n\tmemset(vlanmc, '\\0', sizeof(struct rtl8366_vlan_mc));\n\n\tif (index >= RTL8366RB_NUM_VLANS)\n\t\treturn -EINVAL;\n\n\tfor (i = 0; i < 3; i++) {\n\t\terr = rtl8366_smi_read_reg(smi,\n\t\t\t\t\t   RTL8366RB_VLAN_MC_BASE(index) + i,\n\t\t\t\t\t   &data[i]);\n\t\tif (err)\n\t\t\treturn err;\n\t}\n\n\tvlanmc->vid = data[0] & RTL8366RB_VLAN_VID_MASK;\n\tvlanmc->priority = (data[0] >> RTL8366RB_VLAN_PRIORITY_SHIFT) &\n\t\t\t   RTL8366RB_VLAN_PRIORITY_MASK;\n\tvlanmc->untag = (data[1] >> RTL8366RB_VLAN_UNTAG_SHIFT) &\n\t\t\tRTL8366RB_VLAN_UNTAG_MASK;\n\tvlanmc->member = data[1] & RTL8366RB_VLAN_MEMBER_MASK;\n\tvlanmc->fid = data[2] & RTL8366RB_VLAN_FID_MASK;\n\n\treturn 0;\n}\n\nstatic int rtl8366rb_set_vlan_mc(struct rtl8366_smi *smi, u32 index,\n\t\t\t\t const struct rtl8366_vlan_mc *vlanmc)\n{\n\tu32 data[3];\n\tint err;\n\tint i;\n\n\tif (index >= RTL8366RB_NUM_VLANS ||\n\t    vlanmc->vid >= RTL8366RB_NUM_VIDS ||\n\t    vlanmc->priority > RTL8366RB_PRIORITYMAX ||\n\t    vlanmc->member > RTL8366RB_VLAN_MEMBER_MASK ||\n\t    vlanmc->untag > RTL8366RB_VLAN_UNTAG_MASK ||\n\t    vlanmc->fid > RTL8366RB_FIDMAX)\n\t\treturn -EINVAL;\n\n\tdata[0] = (vlanmc->vid & RTL8366RB_VLAN_VID_MASK) |\n\t\t  ((vlanmc->priority & RTL8366RB_VLAN_PRIORITY_MASK) <<\n\t\t\tRTL8366RB_VLAN_PRIORITY_SHIFT);\n\tdata[1] = (vlanmc->member & RTL8366RB_VLAN_MEMBER_MASK) |\n\t\t  ((vlanmc->untag & RTL8366RB_VLAN_UNTAG_MASK) <<\n\t\t\tRTL8366RB_VLAN_UNTAG_SHIFT);\n\tdata[2] = vlanmc->fid & RTL8366RB_VLAN_FID_MASK;\n\n\tfor (i = 0; i < 3; i++) {\n\t\terr = rtl8366_smi_write_reg(smi,\n\t\t\t\t\t    RTL8366RB_VLAN_MC_BASE(index) + i,\n\t\t\t\t\t    data[i]);\n\t\tif (err)\n\t\t\treturn err;\n\t}\n\n\treturn 0;\n}\n\nstatic int rtl8366rb_get_mc_index(struct rtl8366_smi *smi, int port, int *val)\n{\n\tu32 data;\n\tint err;\n\n\tif (port >= RTL8366RB_NUM_PORTS)\n\t\treturn -EINVAL;\n\n\terr = rtl8366_smi_read_reg(smi, RTL8366RB_PORT_VLAN_CTRL_REG(port),\n\t\t\t\t   &data);\n\tif (err)\n\t\treturn err;\n\n\t*val = (data >> RTL8366RB_PORT_VLAN_CTRL_SHIFT(port)) &\n\t       RTL8366RB_PORT_VLAN_CTRL_MASK;\n\n\treturn 0;\n\n}\n\nstatic int rtl8366rb_set_mc_index(struct rtl8366_smi *smi, int port, int index)\n{\n\tif (port >= RTL8366RB_NUM_PORTS || index >= RTL8366RB_NUM_VLANS)\n\t\treturn -EINVAL;\n\n\treturn rtl8366_smi_rmwr(smi, RTL8366RB_PORT_VLAN_CTRL_REG(port),\n\t\t\t\tRTL8366RB_PORT_VLAN_CTRL_MASK <<\n\t\t\t\t\tRTL8366RB_PORT_VLAN_CTRL_SHIFT(port),\n\t\t\t\t(index & RTL8366RB_PORT_VLAN_CTRL_MASK) <<\n\t\t\t\t\tRTL8366RB_PORT_VLAN_CTRL_SHIFT(port));\n}\n\nstatic int rtl8366rb_is_vlan_valid(struct rtl8366_smi *smi, unsigned vlan)\n{\n\tunsigned max = RTL8366RB_NUM_VLANS;\n\n\tif (smi->vlan4k_enabled)\n\t\tmax = RTL8366RB_NUM_VIDS - 1;\n\n\tif (vlan == 0 || vlan >= max)\n\t\treturn 0;\n\n\treturn 1;\n}\n\nstatic int rtl8366rb_enable_vlan(struct rtl8366_smi *smi, int enable)\n{\n\treturn rtl8366_smi_rmwr(smi, RTL8366RB_SGCR, RTL8366RB_SGCR_EN_VLAN,\n\t\t\t\t(enable) ? RTL8366RB_SGCR_EN_VLAN : 0);\n}\n\nstatic int rtl8366rb_enable_vlan4k(struct rtl8366_smi *smi, int enable)\n{\n\treturn rtl8366_smi_rmwr(smi, RTL8366RB_SGCR,\n\t\t\t\tRTL8366RB_SGCR_EN_VLAN_4KTB,\n\t\t\t\t(enable) ? RTL8366RB_SGCR_EN_VLAN_4KTB : 0);\n}\n\nstatic int rtl8366rb_enable_port(struct rtl8366_smi *smi, int port, int enable)\n{\n\treturn rtl8366_smi_rmwr(smi, RTL8366RB_PECR, (1 << port),\n\t\t\t\t(enable) ? 0 : (1 << port));\n}\n\nstatic int rtl8366rb_sw_reset_mibs(struct switch_dev *dev,\n\t\t\t\t  const struct switch_attr *attr,\n\t\t\t\t  struct switch_val *val)\n{\n\tstruct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);\n\n\treturn rtl8366_smi_rmwr(smi, RTL8366RB_MIB_CTRL_REG, 0,\n\t\t\t        RTL8366RB_MIB_CTRL_GLOBAL_RESET);\n}\n\nstatic int rtl8366rb_sw_get_blinkrate(struct switch_dev *dev,\n\t\t\t\t     const struct switch_attr *attr,\n\t\t\t\t     struct switch_val *val)\n{\n\tstruct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);\n\tu32 data;\n\n\trtl8366_smi_read_reg(smi, RTL8366RB_LED_BLINKRATE_REG, &data);\n\n\tval->value.i = (data & (RTL8366RB_LED_BLINKRATE_MASK));\n\n\treturn 0;\n}\n\nstatic int rtl8366rb_sw_set_blinkrate(struct switch_dev *dev,\n\t\t\t\t    const struct switch_attr *attr,\n\t\t\t\t    struct switch_val *val)\n{\n\tstruct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);\n\n\tif (val->value.i >= 6)\n\t\treturn -EINVAL;\n\n\treturn rtl8366_smi_rmwr(smi, RTL8366RB_LED_BLINKRATE_REG,\n\t\t\t\tRTL8366RB_LED_BLINKRATE_MASK,\n\t\t\t\tval->value.i);\n}\n\nstatic int rtl8366rb_sw_get_learning_enable(struct switch_dev *dev,\n\t\t\t\t       const struct switch_attr *attr,\n\t\t\t\t       struct switch_val *val)\n{\n\tstruct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);\n\tu32 data;\n\n\trtl8366_smi_read_reg(smi, RTL8366RB_SSCR0, &data);\n\tval->value.i = !data;\n\n\treturn 0;\n}\n\n\nstatic int rtl8366rb_sw_set_learning_enable(struct switch_dev *dev,\n\t\t\t\t       const struct switch_attr *attr,\n\t\t\t\t       struct switch_val *val)\n{\n\tstruct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);\n\tu32 portmask = 0;\n\tint err = 0;\n\n\tif (!val->value.i)\n\t\tportmask = RTL8366RB_PORT_ALL;\n\n\t/* set learning for all ports */\n\tREG_WR(smi, RTL8366RB_SSCR0, portmask);\n\n\t/* set auto ageing for all ports */\n\tREG_WR(smi, RTL8366RB_SSCR1, portmask);\n\n\treturn 0;\n}\n\nstatic int rtl8366rb_sw_get_port_link(struct switch_dev *dev,\n\t\t\t\t     int port,\n\t\t\t\t     struct switch_port_link *link)\n{\n\tstruct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);\n\tu32 data = 0;\n\tu32 speed;\n\n\tif (port >= RTL8366RB_NUM_PORTS)\n\t\treturn -EINVAL;\n\n\trtl8366_smi_read_reg(smi, RTL8366RB_PORT_LINK_STATUS_BASE + (port / 2),\n\t\t\t     &data);\n\n\tif (port % 2)\n\t\tdata = data >> 8;\n\n\tlink->link = !!(data & RTL8366RB_PORT_STATUS_LINK_MASK);\n\tif (!link->link)\n\t\treturn 0;\n\n\tlink->duplex = !!(data & RTL8366RB_PORT_STATUS_DUPLEX_MASK);\n\tlink->rx_flow = !!(data & RTL8366RB_PORT_STATUS_RXPAUSE_MASK);\n\tlink->tx_flow = !!(data & RTL8366RB_PORT_STATUS_TXPAUSE_MASK);\n\tlink->aneg = !!(data & RTL8366RB_PORT_STATUS_AN_MASK);\n\n\tspeed = (data & RTL8366RB_PORT_STATUS_SPEED_MASK);\n\tswitch (speed) {\n\tcase 0:\n\t\tlink->speed = SWITCH_PORT_SPEED_10;\n\t\tbreak;\n\tcase 1:\n\t\tlink->speed = SWITCH_PORT_SPEED_100;\n\t\tbreak;\n\tcase 2:\n\t\tlink->speed = SWITCH_PORT_SPEED_1000;\n\t\tbreak;\n\tdefault:\n\t\tlink->speed = SWITCH_PORT_SPEED_UNKNOWN;\n\t\tbreak;\n\t}\n\n\treturn 0;\n}\n\nstatic int rtl8366rb_sw_set_port_led(struct switch_dev *dev,\n\t\t\t\t    const struct switch_attr *attr,\n\t\t\t\t    struct switch_val *val)\n{\n\tstruct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);\n\tu32 data;\n\tu32 mask;\n\tu32 reg;\n\n\tif (val->port_vlan >= RTL8366RB_NUM_PORTS)\n\t\treturn -EINVAL;\n\n\tif (val->port_vlan == RTL8366RB_PORT_NUM_CPU) {\n\t\treg = RTL8366RB_LED_BLINKRATE_REG;\n\t\tmask = 0xF << 4;\n\t\tdata = val->value.i << 4;\n\t} else {\n\t\treg = RTL8366RB_LED_CTRL_REG;\n\t\tmask = 0xF << (val->port_vlan * 4),\n\t\tdata = val->value.i << (val->port_vlan * 4);\n\t}\n\n\treturn rtl8366_smi_rmwr(smi, reg, mask, data);\n}\n\nstatic int rtl8366rb_sw_get_port_led(struct switch_dev *dev,\n\t\t\t\t    const struct switch_attr *attr,\n\t\t\t\t    struct switch_val *val)\n{\n\tstruct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);\n\tu32 data = 0;\n\n\tif (val->port_vlan >= RTL8366RB_NUM_LEDGROUPS)\n\t\treturn -EINVAL;\n\n\trtl8366_smi_read_reg(smi, RTL8366RB_LED_CTRL_REG, &data);\n\tval->value.i = (data >> (val->port_vlan * 4)) & 0x000F;\n\n\treturn 0;\n}\n\nstatic int rtl8366rb_sw_set_port_disable(struct switch_dev *dev,\n\t\t\t\t    const struct switch_attr *attr,\n\t\t\t\t    struct switch_val *val)\n{\n\tstruct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);\n\tu32 mask, data;\n\n\tif (val->port_vlan >= RTL8366RB_NUM_PORTS)\n\t\treturn -EINVAL;\n\n\tmask = 1 << val->port_vlan ;\n\tif (val->value.i)\n\t\tdata = mask;\n\telse\n\t\tdata = 0;\n\n\treturn rtl8366_smi_rmwr(smi, RTL8366RB_PECR, mask, data);\n}\n\nstatic int rtl8366rb_sw_get_port_disable(struct switch_dev *dev,\n\t\t\t\t    const struct switch_attr *attr,\n\t\t\t\t    struct switch_val *val)\n{\n\tstruct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);\n\tu32 data;\n\n\tif (val->port_vlan >= RTL8366RB_NUM_PORTS)\n\t\treturn -EINVAL;\n\n\trtl8366_smi_read_reg(smi, RTL8366RB_PECR, &data);\n\tif (data & (1 << val->port_vlan))\n\t\tval->value.i = 1;\n\telse\n\t\tval->value.i = 0;\n\n\treturn 0;\n}\n\nstatic int rtl8366rb_sw_set_port_rate_in(struct switch_dev *dev,\n\t\t\t\t    const struct switch_attr *attr,\n\t\t\t\t    struct switch_val *val)\n{\n\tstruct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);\n\n\tif (val->port_vlan >= RTL8366RB_NUM_PORTS)\n\t\treturn -EINVAL;\n\n\tif (val->value.i > 0 && val->value.i < RTL8366RB_BDTH_SW_MAX)\n\t\tval->value.i = (val->value.i - 1) / RTL8366RB_BDTH_UNIT;\n\telse\n\t\tval->value.i = RTL8366RB_BDTH_REG_DEFAULT;\n\n\treturn rtl8366_smi_rmwr(smi, RTL8366RB_IB_REG(val->port_vlan),\n\t\tRTL8366RB_IB_BDTH_MASK | RTL8366RB_IB_PREIFG_MASK,\n\t\tval->value.i |\n\t\t(RTL8366RB_QOS_DEFAULT_PREIFG << RTL8366RB_IB_PREIFG_OFFSET));\n\n}\n\nstatic int rtl8366rb_sw_get_port_rate_in(struct switch_dev *dev,\n\t\t\t\t    const struct switch_attr *attr,\n\t\t\t\t    struct switch_val *val)\n{\n\tstruct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);\n\tu32 data;\n\n\tif (val->port_vlan >= RTL8366RB_NUM_PORTS)\n\t\treturn -EINVAL;\n\n\trtl8366_smi_read_reg(smi, RTL8366RB_IB_REG(val->port_vlan), &data);\n\tdata &= RTL8366RB_IB_BDTH_MASK;\n\tif (data < RTL8366RB_IB_BDTH_MASK)\n\t\tdata += 1;\n\n\tval->value.i = (int)data * RTL8366RB_BDTH_UNIT;\n\n\treturn 0;\n}\n\nstatic int rtl8366rb_sw_set_port_rate_out(struct switch_dev *dev,\n\t\t\t\t    const struct switch_attr *attr,\n\t\t\t\t    struct switch_val *val)\n{\n\tstruct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);\n\n\tif (val->port_vlan >= RTL8366RB_NUM_PORTS)\n\t\treturn -EINVAL;\n\n\trtl8366_smi_rmwr(smi, RTL8366RB_EB_PREIFG_REG,\n\t\tRTL8366RB_EB_PREIFG_MASK,\n\t\t(RTL8366RB_QOS_DEFAULT_PREIFG << RTL8366RB_EB_PREIFG_OFFSET));\n\n\tif (val->value.i > 0 && val->value.i < RTL8366RB_BDTH_SW_MAX)\n\t\tval->value.i = (val->value.i - 1) / RTL8366RB_BDTH_UNIT;\n\telse\n\t\tval->value.i = RTL8366RB_BDTH_REG_DEFAULT;\n\n\treturn rtl8366_smi_rmwr(smi, RTL8366RB_EB_REG(val->port_vlan),\n\t\t\tRTL8366RB_EB_BDTH_MASK, val->value.i );\n\n}\n\nstatic int rtl8366rb_sw_get_port_rate_out(struct switch_dev *dev,\n\t\t\t\t    const struct switch_attr *attr,\n\t\t\t\t    struct switch_val *val)\n{\n\tstruct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);\n\tu32 data;\n\n\tif (val->port_vlan >= RTL8366RB_NUM_PORTS)\n\t\treturn -EINVAL;\n\n\trtl8366_smi_read_reg(smi, RTL8366RB_EB_REG(val->port_vlan), &data);\n\tdata &= RTL8366RB_EB_BDTH_MASK;\n\tif (data < RTL8366RB_EB_BDTH_MASK)\n\t\tdata += 1;\n\n\tval->value.i = (int)data * RTL8366RB_BDTH_UNIT;\n\n\treturn 0;\n}\n\nstatic int rtl8366rb_sw_set_qos_enable(struct switch_dev *dev,\n\t\t\t\t    const struct switch_attr *attr,\n\t\t\t\t    struct switch_val *val)\n{\n\tstruct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);\n\tu32 data;\n\n\tif (val->value.i)\n\t\tdata = RTL8366RB_QOS_MASK;\n\telse\n\t\tdata = 0;\n\n\treturn rtl8366_smi_rmwr(smi, RTL8366RB_SGCR, RTL8366RB_QOS_MASK, data);\n}\n\nstatic int rtl8366rb_sw_get_qos_enable(struct switch_dev *dev,\n\t\t\t\t    const struct switch_attr *attr,\n\t\t\t\t    struct switch_val *val)\n{\n\tstruct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);\n\tu32 data;\n\n\trtl8366_smi_read_reg(smi, RTL8366RB_SGCR, &data);\n\tif (data & RTL8366RB_QOS_MASK)\n\t\tval->value.i = 1;\n\telse\n\t\tval->value.i = 0;\n\n\treturn 0;\n}\n\nstatic int rtl8366rb_sw_set_mirror_rx_enable(struct switch_dev *dev,\n\t\t\t\t    const struct switch_attr *attr,\n\t\t\t\t    struct switch_val *val)\n{\n\tstruct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);\n\tu32 data;\n\n\tif (val->value.i)\n\t\tdata = RTL8366RB_PMCR_MIRROR_RX;\n\telse\n\t\tdata = 0;\n\n\treturn rtl8366_smi_rmwr(smi, RTL8366RB_PMCR, RTL8366RB_PMCR_MIRROR_RX, data);\n}\n\nstatic int rtl8366rb_sw_get_mirror_rx_enable(struct switch_dev *dev,\n\t\t\t\t    const struct switch_attr *attr,\n\t\t\t\t    struct switch_val *val)\n{\n\tstruct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);\n\tu32 data;\n\n\trtl8366_smi_read_reg(smi, RTL8366RB_PMCR, &data);\n\tif (data & RTL8366RB_PMCR_MIRROR_RX)\n\t\tval->value.i = 1;\n\telse\n\t\tval->value.i = 0;\n\n\treturn 0;\n}\n\nstatic int rtl8366rb_sw_set_mirror_tx_enable(struct switch_dev *dev,\n\t\t\t\t    const struct switch_attr *attr,\n\t\t\t\t    struct switch_val *val)\n{\n\tstruct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);\n\tu32 data;\n\n\tif (val->value.i)\n\t\tdata = RTL8366RB_PMCR_MIRROR_TX;\n\telse\n\t\tdata = 0;\n\n\treturn rtl8366_smi_rmwr(smi, RTL8366RB_PMCR, RTL8366RB_PMCR_MIRROR_TX, data);\n}\n\nstatic int rtl8366rb_sw_get_mirror_tx_enable(struct switch_dev *dev,\n\t\t\t\t    const struct switch_attr *attr,\n\t\t\t\t    struct switch_val *val)\n{\n\tstruct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);\n\tu32 data;\n\n\trtl8366_smi_read_reg(smi, RTL8366RB_PMCR, &data);\n\tif (data & RTL8366RB_PMCR_MIRROR_TX)\n\t\tval->value.i = 1;\n\telse\n\t\tval->value.i = 0;\n\n\treturn 0;\n}\n\nstatic int rtl8366rb_sw_set_monitor_isolation_enable(struct switch_dev *dev,\n\t\t\t\t    const struct switch_attr *attr,\n\t\t\t\t    struct switch_val *val)\n{\n\tstruct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);\n\tu32 data;\n\n\tif (val->value.i)\n\t\tdata = RTL8366RB_PMCR_MIRROR_ISO;\n\telse\n\t\tdata = 0;\n\n\treturn rtl8366_smi_rmwr(smi, RTL8366RB_PMCR, RTL8366RB_PMCR_MIRROR_ISO, data);\n}\n\nstatic int rtl8366rb_sw_get_monitor_isolation_enable(struct switch_dev *dev,\n\t\t\t\t    const struct switch_attr *attr,\n\t\t\t\t    struct switch_val *val)\n{\n\tstruct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);\n\tu32 data;\n\n\trtl8366_smi_read_reg(smi, RTL8366RB_PMCR, &data);\n\tif (data & RTL8366RB_PMCR_MIRROR_ISO)\n\t\tval->value.i = 1;\n\telse\n\t\tval->value.i = 0;\n\n\treturn 0;\n}\n\nstatic int rtl8366rb_sw_set_mirror_pause_frames_enable(struct switch_dev *dev,\n\t\t\t\t    const struct switch_attr *attr,\n\t\t\t\t    struct switch_val *val)\n{\n\tstruct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);\n\tu32 data;\n\n\tif (val->value.i)\n\t\tdata = RTL8366RB_PMCR_MIRROR_SPC;\n\telse\n\t\tdata = 0;\n\n\treturn rtl8366_smi_rmwr(smi, RTL8366RB_PMCR, RTL8366RB_PMCR_MIRROR_SPC, data);\n}\n\nstatic int rtl8366rb_sw_get_mirror_pause_frames_enable(struct switch_dev *dev,\n\t\t\t\t    const struct switch_attr *attr,\n\t\t\t\t    struct switch_val *val)\n{\n\tstruct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);\n\tu32 data;\n\n\trtl8366_smi_read_reg(smi, RTL8366RB_PMCR, &data);\n\tif (data & RTL8366RB_PMCR_MIRROR_SPC)\n\t\tval->value.i = 1;\n\telse\n\t\tval->value.i = 0;\n\n\treturn 0;\n}\n\nstatic int rtl8366rb_sw_set_mirror_monitor_port(struct switch_dev *dev,\n\t\t\t\t    const struct switch_attr *attr,\n\t\t\t\t    struct switch_val *val)\n{\n\tstruct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);\n\tu32 data;\n\n\tdata = RTL8366RB_PMCR_MONITOR_PORT(val->value.i);\n\n\treturn rtl8366_smi_rmwr(smi, RTL8366RB_PMCR, RTL8366RB_PMCR_MONITOR_PORT_MASK, data);\n}\n\nstatic int rtl8366rb_sw_get_mirror_monitor_port(struct switch_dev *dev,\n\t\t\t\t    const struct switch_attr *attr,\n\t\t\t\t    struct switch_val *val)\n{\n\tstruct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);\n\tu32 data;\n\n\trtl8366_smi_read_reg(smi, RTL8366RB_PMCR, &data);\n\tval->value.i = (data & RTL8366RB_PMCR_MONITOR_PORT_MASK) >> 4;\n\n\treturn 0;\n}\n\nstatic int rtl8366rb_sw_set_mirror_source_port(struct switch_dev *dev,\n\t\t\t\t    const struct switch_attr *attr,\n\t\t\t\t    struct switch_val *val)\n{\n\tstruct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);\n\tu32 data;\n\n\tdata = RTL8366RB_PMCR_SOURCE_PORT(val->value.i);\n\n\treturn rtl8366_smi_rmwr(smi, RTL8366RB_PMCR, RTL8366RB_PMCR_SOURCE_PORT_MASK, data);\n}\n\nstatic int rtl8366rb_sw_get_mirror_source_port(struct switch_dev *dev,\n\t\t\t\t    const struct switch_attr *attr,\n\t\t\t\t    struct switch_val *val)\n{\n\tstruct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);\n\tu32 data;\n\n\trtl8366_smi_read_reg(smi, RTL8366RB_PMCR, &data);\n\tval->value.i = data & RTL8366RB_PMCR_SOURCE_PORT_MASK;\n\n\treturn 0;\n}\n\nstatic int rtl8366rb_sw_reset_port_mibs(struct switch_dev *dev,\n\t\t\t\t       const struct switch_attr *attr,\n\t\t\t\t       struct switch_val *val)\n{\n\tstruct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);\n\n\tif (val->port_vlan >= RTL8366RB_NUM_PORTS)\n\t\treturn -EINVAL;\n\n\treturn rtl8366_smi_rmwr(smi, RTL8366RB_MIB_CTRL_REG, 0,\n\t\t\t\tRTL8366RB_MIB_CTRL_PORT_RESET(val->port_vlan));\n}\n\nstatic int rtl8366rb_sw_get_port_stats(struct switch_dev *dev, int port,\n\t\t\t\t\tstruct switch_port_stats *stats)\n{\n\treturn (rtl8366_sw_get_port_stats(dev, port, stats,\n\t\t\t\tRTL8366RB_MIB_TXB_ID, RTL8366RB_MIB_RXB_ID));\n}\n\nstatic struct switch_attr rtl8366rb_globals[] = {\n\t{\n\t\t.type = SWITCH_TYPE_INT,\n\t\t.name = \"enable_learning\",\n\t\t.description = \"Enable learning, enable aging\",\n\t\t.set = rtl8366rb_sw_set_learning_enable,\n\t\t.get = rtl8366rb_sw_get_learning_enable,\n\t\t.max = 1\n\t}, {\n\t\t.type = SWITCH_TYPE_INT,\n\t\t.name = \"enable_vlan\",\n\t\t.description = \"Enable VLAN mode\",\n\t\t.set = rtl8366_sw_set_vlan_enable,\n\t\t.get = rtl8366_sw_get_vlan_enable,\n\t\t.max = 1,\n\t\t.ofs = 1\n\t}, {\n\t\t.type = SWITCH_TYPE_INT,\n\t\t.name = \"enable_vlan4k\",\n\t\t.description = \"Enable VLAN 4K mode\",\n\t\t.set = rtl8366_sw_set_vlan_enable,\n\t\t.get = rtl8366_sw_get_vlan_enable,\n\t\t.max = 1,\n\t\t.ofs = 2\n\t}, {\n\t\t.type = SWITCH_TYPE_NOVAL,\n\t\t.name = \"reset_mibs\",\n\t\t.description = \"Reset all MIB counters\",\n\t\t.set = rtl8366rb_sw_reset_mibs,\n\t}, {\n\t\t.type = SWITCH_TYPE_INT,\n\t\t.name = \"blinkrate\",\n\t\t.description = \"Get/Set LED blinking rate (0 = 43ms, 1 = 84ms,\"\n\t\t\" 2 = 120ms, 3 = 170ms, 4 = 340ms, 5 = 670ms)\",\n\t\t.set = rtl8366rb_sw_set_blinkrate,\n\t\t.get = rtl8366rb_sw_get_blinkrate,\n\t\t.max = 5\n\t}, {\n\t\t.type = SWITCH_TYPE_INT,\n\t\t.name = \"enable_qos\",\n\t\t.description = \"Enable QOS\",\n\t\t.set = rtl8366rb_sw_set_qos_enable,\n\t\t.get = rtl8366rb_sw_get_qos_enable,\n\t\t.max = 1\n\t}, {\n\t\t.type = SWITCH_TYPE_INT,\n\t\t.name = \"enable_mirror_rx\",\n\t\t.description = \"Enable mirroring of RX packets\",\n\t\t.set = rtl8366rb_sw_set_mirror_rx_enable,\n\t\t.get = rtl8366rb_sw_get_mirror_rx_enable,\n\t\t.max = 1\n\t}, {\n\t\t.type = SWITCH_TYPE_INT,\n\t\t.name = \"enable_mirror_tx\",\n\t\t.description = \"Enable mirroring of TX packets\",\n\t\t.set = rtl8366rb_sw_set_mirror_tx_enable,\n\t\t.get = rtl8366rb_sw_get_mirror_tx_enable,\n\t\t.max = 1\n\t}, {\n\t\t.type = SWITCH_TYPE_INT,\n\t\t.name = \"enable_monitor_isolation\",\n\t\t.description = \"Enable isolation of monitor port (TX packets will be dropped)\",\n\t\t.set = rtl8366rb_sw_set_monitor_isolation_enable,\n\t\t.get = rtl8366rb_sw_get_monitor_isolation_enable,\n\t\t.max = 1\n\t}, {\n\t\t.type = SWITCH_TYPE_INT,\n\t\t.name = \"enable_mirror_pause_frames\",\n\t\t.description = \"Enable mirroring of RX pause frames\",\n\t\t.set = rtl8366rb_sw_set_mirror_pause_frames_enable,\n\t\t.get = rtl8366rb_sw_get_mirror_pause_frames_enable,\n\t\t.max = 1\n\t}, {\n\t\t.type = SWITCH_TYPE_INT,\n\t\t.name = \"mirror_monitor_port\",\n\t\t.description = \"Mirror monitor port\",\n\t\t.set = rtl8366rb_sw_set_mirror_monitor_port,\n\t\t.get = rtl8366rb_sw_get_mirror_monitor_port,\n\t\t.max = 5\n\t}, {\n\t\t.type = SWITCH_TYPE_INT,\n\t\t.name = \"mirror_source_port\",\n\t\t.description = \"Mirror source port\",\n\t\t.set = rtl8366rb_sw_set_mirror_source_port,\n\t\t.get = rtl8366rb_sw_get_mirror_source_port,\n\t\t.max = 5\n\t},\n};\n\nstatic struct switch_attr rtl8366rb_port[] = {\n\t{\n\t\t.type = SWITCH_TYPE_NOVAL,\n\t\t.name = \"reset_mib\",\n\t\t.description = \"Reset single port MIB counters\",\n\t\t.set = rtl8366rb_sw_reset_port_mibs,\n\t}, {\n\t\t.type = SWITCH_TYPE_STRING,\n\t\t.name = \"mib\",\n\t\t.description = \"Get MIB counters for port\",\n\t\t.max = 33,\n\t\t.set = NULL,\n\t\t.get = rtl8366_sw_get_port_mib,\n\t}, {\n\t\t.type = SWITCH_TYPE_INT,\n\t\t.name = \"led\",\n\t\t.description = \"Get/Set port group (0 - 3) led mode (0 - 15)\",\n\t\t.max = 15,\n\t\t.set = rtl8366rb_sw_set_port_led,\n\t\t.get = rtl8366rb_sw_get_port_led,\n\t}, {\n\t\t.type = SWITCH_TYPE_INT,\n\t\t.name = \"disable\",\n\t\t.description = \"Get/Set port state (enabled or disabled)\",\n\t\t.max = 1,\n\t\t.set = rtl8366rb_sw_set_port_disable,\n\t\t.get = rtl8366rb_sw_get_port_disable,\n\t}, {\n\t\t.type = SWITCH_TYPE_INT,\n\t\t.name = \"rate_in\",\n\t\t.description = \"Get/Set port ingress (incoming) bandwidth limit in kbps\",\n\t\t.max = RTL8366RB_BDTH_SW_MAX,\n\t\t.set = rtl8366rb_sw_set_port_rate_in,\n\t\t.get = rtl8366rb_sw_get_port_rate_in,\n\t}, {\n\t\t.type = SWITCH_TYPE_INT,\n\t\t.name = \"rate_out\",\n\t\t.description = \"Get/Set port egress (outgoing) bandwidth limit in kbps\",\n\t\t.max = RTL8366RB_BDTH_SW_MAX,\n\t\t.set = rtl8366rb_sw_set_port_rate_out,\n\t\t.get = rtl8366rb_sw_get_port_rate_out,\n\t},\n};\n\nstatic struct switch_attr rtl8366rb_vlan[] = {\n\t{\n\t\t.type = SWITCH_TYPE_STRING,\n\t\t.name = \"info\",\n\t\t.description = \"Get vlan information\",\n\t\t.max = 1,\n\t\t.set = NULL,\n\t\t.get = rtl8366_sw_get_vlan_info,\n\t}, {\n\t\t.type = SWITCH_TYPE_INT,\n\t\t.name = \"fid\",\n\t\t.description = \"Get/Set vlan FID\",\n\t\t.max = RTL8366RB_FIDMAX,\n\t\t.set = rtl8366_sw_set_vlan_fid,\n\t\t.get = rtl8366_sw_get_vlan_fid,\n\t},\n};\n\nstatic const struct switch_dev_ops rtl8366_ops = {\n\t.attr_global = {\n\t\t.attr = rtl8366rb_globals,\n\t\t.n_attr = ARRAY_SIZE(rtl8366rb_globals),\n\t},\n\t.attr_port = {\n\t\t.attr = rtl8366rb_port,\n\t\t.n_attr = ARRAY_SIZE(rtl8366rb_port),\n\t},\n\t.attr_vlan = {\n\t\t.attr = rtl8366rb_vlan,\n\t\t.n_attr = ARRAY_SIZE(rtl8366rb_vlan),\n\t},\n\n\t.get_vlan_ports = rtl8366_sw_get_vlan_ports,\n\t.set_vlan_ports = rtl8366_sw_set_vlan_ports,\n\t.get_port_pvid = rtl8366_sw_get_port_pvid,\n\t.set_port_pvid = rtl8366_sw_set_port_pvid,\n\t.reset_switch = rtl8366_sw_reset_switch,\n\t.get_port_link = rtl8366rb_sw_get_port_link,\n\t.get_port_stats = rtl8366rb_sw_get_port_stats,\n};\n\nstatic int rtl8366rb_switch_init(struct rtl8366_smi *smi)\n{\n\tstruct switch_dev *dev = &smi->sw_dev;\n\tint err;\n\n\tdev->name = \"RTL8366RB\";\n\tdev->cpu_port = RTL8366RB_PORT_NUM_CPU;\n\tdev->ports = RTL8366RB_NUM_PORTS;\n\tdev->vlans = RTL8366RB_NUM_VIDS;\n\tdev->ops = &rtl8366_ops;\n\tdev->alias = dev_name(smi->parent);\n\n\terr = register_switch(dev, NULL);\n\tif (err)\n\t\tdev_err(smi->parent, \"switch registration failed\\n\");\n\n\treturn err;\n}\n\nstatic void rtl8366rb_switch_cleanup(struct rtl8366_smi *smi)\n{\n\tunregister_switch(&smi->sw_dev);\n}\n\nstatic int rtl8366rb_mii_read(struct mii_bus *bus, int addr, int reg)\n{\n\tstruct rtl8366_smi *smi = bus->priv;\n\tu32 val = 0;\n\tint err;\n\n\terr = rtl8366rb_read_phy_reg(smi, addr, 0, reg, &val);\n\tif (err)\n\t\treturn 0xffff;\n\n\treturn val;\n}\n\nstatic int rtl8366rb_mii_write(struct mii_bus *bus, int addr, int reg, u16 val)\n{\n\tstruct rtl8366_smi *smi = bus->priv;\n\tu32 t;\n\tint err;\n\n\terr = rtl8366rb_write_phy_reg(smi, addr, 0, reg, val);\n\t/* flush write */\n\t(void) rtl8366rb_read_phy_reg(smi, addr, 0, reg, &t);\n\n\treturn err;\n}\n\nstatic int rtl8366rb_detect(struct rtl8366_smi *smi)\n{\n\tu32 chip_id = 0;\n\tu32 chip_ver = 0;\n\tint ret;\n\n\tret = rtl8366_smi_read_reg(smi, RTL8366RB_CHIP_ID_REG, &chip_id);\n\tif (ret) {\n\t\tdev_err(smi->parent, \"unable to read chip id\\n\");\n\t\treturn ret;\n\t}\n\n\tswitch (chip_id) {\n\tcase RTL8366RB_CHIP_ID_8366:\n\t\tbreak;\n\tdefault:\n\t\tdev_err(smi->parent, \"unknown chip id (%04x)\\n\", chip_id);\n\t\treturn -ENODEV;\n\t}\n\n\tret = rtl8366_smi_read_reg(smi, RTL8366RB_CHIP_VERSION_CTRL_REG,\n\t\t\t\t   &chip_ver);\n\tif (ret) {\n\t\tdev_err(smi->parent, \"unable to read chip version\\n\");\n\t\treturn ret;\n\t}\n\n\tdev_info(smi->parent, \"RTL%04x ver. %u chip found\\n\",\n\t\t chip_id, chip_ver & RTL8366RB_CHIP_VERSION_MASK);\n\n\treturn 0;\n}\n\nstatic struct rtl8366_smi_ops rtl8366rb_smi_ops = {\n\t.detect\t\t= rtl8366rb_detect,\n\t.reset_chip\t= rtl8366rb_reset_chip,\n\t.setup\t\t= rtl8366rb_setup,\n\n\t.mii_read\t= rtl8366rb_mii_read,\n\t.mii_write\t= rtl8366rb_mii_write,\n\n\t.get_vlan_mc\t= rtl8366rb_get_vlan_mc,\n\t.set_vlan_mc\t= rtl8366rb_set_vlan_mc,\n\t.get_vlan_4k\t= rtl8366rb_get_vlan_4k,\n\t.set_vlan_4k\t= rtl8366rb_set_vlan_4k,\n\t.get_mc_index\t= rtl8366rb_get_mc_index,\n\t.set_mc_index\t= rtl8366rb_set_mc_index,\n\t.get_mib_counter = rtl8366rb_get_mib_counter,\n\t.is_vlan_valid\t= rtl8366rb_is_vlan_valid,\n\t.enable_vlan\t= rtl8366rb_enable_vlan,\n\t.enable_vlan4k\t= rtl8366rb_enable_vlan4k,\n\t.enable_port\t= rtl8366rb_enable_port,\n};\n\nstatic int rtl8366rb_probe(struct platform_device *pdev)\n{\n\tstatic int rtl8366_smi_version_printed;\n\tstruct rtl8366_smi *smi;\n\tint err;\n\n\tif (!rtl8366_smi_version_printed++)\n\t\tprintk(KERN_NOTICE RTL8366RB_DRIVER_DESC\n\t\t       \" version \" RTL8366RB_DRIVER_VER\"\\n\");\n\n\tsmi = rtl8366_smi_probe(pdev);\n\tif (IS_ERR(smi))\n\t\treturn PTR_ERR(smi);\n\n\tsmi->clk_delay = 10;\n\tsmi->cmd_read = 0xa9;\n\tsmi->cmd_write = 0xa8;\n\tsmi->ops = &rtl8366rb_smi_ops;\n\tsmi->cpu_port = RTL8366RB_PORT_NUM_CPU;\n\tsmi->num_ports = RTL8366RB_NUM_PORTS;\n\tsmi->num_vlan_mc = RTL8366RB_NUM_VLANS;\n\tsmi->mib_counters = rtl8366rb_mib_counters;\n\tsmi->num_mib_counters = ARRAY_SIZE(rtl8366rb_mib_counters);\n\n\terr = rtl8366_smi_init(smi);\n\tif (err)\n\t\tgoto err_free_smi;\n\n\tplatform_set_drvdata(pdev, smi);\n\n\terr = rtl8366rb_switch_init(smi);\n\tif (err)\n\t\tgoto err_clear_drvdata;\n\n\treturn 0;\n\n err_clear_drvdata:\n\tplatform_set_drvdata(pdev, NULL);\n\trtl8366_smi_cleanup(smi);\n err_free_smi:\n\tkfree(smi);\n\treturn err;\n}\n\nstatic int rtl8366rb_remove(struct platform_device *pdev)\n{\n\tstruct rtl8366_smi *smi = platform_get_drvdata(pdev);\n\n\tif (smi) {\n\t\trtl8366rb_switch_cleanup(smi);\n\t\tplatform_set_drvdata(pdev, NULL);\n\t\trtl8366_smi_cleanup(smi);\n\t\tkfree(smi);\n\t}\n\n\treturn 0;\n}\n\n#ifdef CONFIG_OF\nstatic const struct of_device_id rtl8366rb_match[] = {\n\t{ .compatible = \"realtek,rtl8366rb\" },\n\t{},\n};\nMODULE_DEVICE_TABLE(of, rtl8366rb_match);\n#endif\n\nstatic struct platform_driver rtl8366rb_driver = {\n\t.driver = {\n\t\t.name\t\t= RTL8366RB_DRIVER_NAME,\n\t\t.owner\t\t= THIS_MODULE,\n\t\t.of_match_table = of_match_ptr(rtl8366rb_match),\n\t},\n\t.probe\t\t= rtl8366rb_probe,\n\t.remove\t\t= rtl8366rb_remove,\n};\n\nstatic int __init rtl8366rb_module_init(void)\n{\n\treturn platform_driver_register(&rtl8366rb_driver);\n}\nmodule_init(rtl8366rb_module_init);\n\nstatic void __exit rtl8366rb_module_exit(void)\n{\n\tplatform_driver_unregister(&rtl8366rb_driver);\n}\nmodule_exit(rtl8366rb_module_exit);\n\nMODULE_DESCRIPTION(RTL8366RB_DRIVER_DESC);\nMODULE_VERSION(RTL8366RB_DRIVER_VER);\nMODULE_AUTHOR(\"Gabor Juhos <juhosg@openwrt.org>\");\nMODULE_AUTHOR(\"Antti Seppälä <a.seppala@gmail.com>\");\nMODULE_AUTHOR(\"Roman Yeryomin <roman@advem.lv>\");\nMODULE_AUTHOR(\"Colin Leitner <colin.leitner@googlemail.com>\");\nMODULE_LICENSE(\"GPL v2\");\nMODULE_ALIAS(\"platform:\" RTL8366RB_DRIVER_NAME);\n"
  },
  {
    "path": "target/linux/generic/files/drivers/net/phy/rtl8366s.c",
    "content": "/*\n * Platform driver for the Realtek RTL8366S ethernet switch\n *\n * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>\n * Copyright (C) 2010 Antti Seppälä <a.seppala@gmail.com>\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of the GNU General Public License version 2 as published\n * by the Free Software Foundation.\n */\n\n#include <linux/kernel.h>\n#include <linux/module.h>\n#include <linux/init.h>\n#include <linux/device.h>\n#include <linux/of.h>\n#include <linux/of_platform.h>\n#include <linux/delay.h>\n#include <linux/skbuff.h>\n#include <linux/rtl8366.h>\n\n#include \"rtl8366_smi.h\"\n\n#define RTL8366S_DRIVER_DESC\t\"Realtek RTL8366S ethernet switch driver\"\n#define RTL8366S_DRIVER_VER\t\"0.2.2\"\n\n#define RTL8366S_PHY_NO_MAX\t4\n#define RTL8366S_PHY_PAGE_MAX\t7\n#define RTL8366S_PHY_ADDR_MAX\t31\n\n/* Switch Global Configuration register */\n#define RTL8366S_SGCR\t\t\t\t0x0000\n#define RTL8366S_SGCR_EN_BC_STORM_CTRL\t\tBIT(0)\n#define RTL8366S_SGCR_MAX_LENGTH(_x)\t\t(_x << 4)\n#define RTL8366S_SGCR_MAX_LENGTH_MASK\t\tRTL8366S_SGCR_MAX_LENGTH(0x3)\n#define RTL8366S_SGCR_MAX_LENGTH_1522\t\tRTL8366S_SGCR_MAX_LENGTH(0x0)\n#define RTL8366S_SGCR_MAX_LENGTH_1536\t\tRTL8366S_SGCR_MAX_LENGTH(0x1)\n#define RTL8366S_SGCR_MAX_LENGTH_1552\t\tRTL8366S_SGCR_MAX_LENGTH(0x2)\n#define RTL8366S_SGCR_MAX_LENGTH_16000\t\tRTL8366S_SGCR_MAX_LENGTH(0x3)\n#define RTL8366S_SGCR_EN_VLAN\t\t\tBIT(13)\n\n/* Port Enable Control register */\n#define RTL8366S_PECR\t\t\t\t0x0001\n\n/* Green Ethernet Feature (based on GPL_BELKIN_F5D8235-4_v1000 v1.01.24) */\n#define RTL8366S_GREEN_ETHERNET_CTRL_REG\t0x000a\n#define RTL8366S_GREEN_ETHERNET_CTRL_MASK\t0x0018\n#define RTL8366S_GREEN_ETHERNET_TX_BIT\t\t(1 << 3)\n#define RTL8366S_GREEN_ETHERNET_RX_BIT\t\t(1 << 4)\n\n/* Switch Security Control registers */\n#define RTL8366S_SSCR0\t\t\t\t0x0002\n#define RTL8366S_SSCR1\t\t\t\t0x0003\n#define RTL8366S_SSCR2\t\t\t\t0x0004\n#define RTL8366S_SSCR2_DROP_UNKNOWN_DA\t\tBIT(0)\n\n#define RTL8366S_RESET_CTRL_REG\t\t\t0x0100\n#define RTL8366S_CHIP_CTRL_RESET_HW\t\t1\n#define RTL8366S_CHIP_CTRL_RESET_SW\t\t(1 << 1)\n\n#define RTL8366S_CHIP_VERSION_CTRL_REG\t\t0x0104\n#define RTL8366S_CHIP_VERSION_MASK\t\t0xf\n#define RTL8366S_CHIP_ID_REG\t\t\t0x0105\n#define RTL8366S_CHIP_ID_8366\t\t\t0x8366\n\n/* PHY registers control */\n#define RTL8366S_PHY_ACCESS_CTRL_REG\t\t0x8028\n#define RTL8366S_PHY_ACCESS_DATA_REG\t\t0x8029\n\n#define RTL8366S_PHY_CTRL_READ\t\t\t1\n#define RTL8366S_PHY_CTRL_WRITE\t\t\t0\n\n#define RTL8366S_PHY_REG_MASK\t\t\t0x1f\n#define RTL8366S_PHY_PAGE_OFFSET\t\t5\n#define RTL8366S_PHY_PAGE_MASK\t\t\t(0x7 << 5)\n#define RTL8366S_PHY_NO_OFFSET\t\t\t9\n#define RTL8366S_PHY_NO_MASK\t\t\t(0x1f << 9)\n\n/* Green Ethernet Feature for PHY ports */\n#define RTL8366S_PHY_POWER_SAVING_CTRL_REG\t12\n#define RTL8366S_PHY_POWER_SAVING_MASK\t\t0x1000\n\n/* LED control registers */\n#define RTL8366S_LED_BLINKRATE_REG\t\t0x0420\n#define RTL8366S_LED_BLINKRATE_BIT\t\t0\n#define RTL8366S_LED_BLINKRATE_MASK\t\t0x0007\n\n#define RTL8366S_LED_CTRL_REG\t\t\t0x0421\n#define RTL8366S_LED_0_1_CTRL_REG\t\t0x0422\n#define RTL8366S_LED_2_3_CTRL_REG\t\t0x0423\n\n#define RTL8366S_MIB_COUNT\t\t\t33\n#define RTL8366S_GLOBAL_MIB_COUNT\t\t1\n#define RTL8366S_MIB_COUNTER_PORT_OFFSET\t0x0040\n#define RTL8366S_MIB_COUNTER_BASE\t\t0x1000\n#define RTL8366S_MIB_COUNTER_PORT_OFFSET2\t0x0008\n#define RTL8366S_MIB_COUNTER_BASE2\t\t0x1180\n#define RTL8366S_MIB_CTRL_REG\t\t\t0x11F0\n#define RTL8366S_MIB_CTRL_USER_MASK\t\t0x01FF\n#define RTL8366S_MIB_CTRL_BUSY_MASK\t\t0x0001\n#define RTL8366S_MIB_CTRL_RESET_MASK\t\t0x0002\n\n#define RTL8366S_MIB_CTRL_GLOBAL_RESET_MASK\t0x0004\n#define RTL8366S_MIB_CTRL_PORT_RESET_BIT\t0x0003\n#define RTL8366S_MIB_CTRL_PORT_RESET_MASK\t0x01FC\n\n\n#define RTL8366S_PORT_VLAN_CTRL_BASE\t\t0x0058\n#define RTL8366S_PORT_VLAN_CTRL_REG(_p)  \\\n\t\t(RTL8366S_PORT_VLAN_CTRL_BASE + (_p) / 4)\n#define RTL8366S_PORT_VLAN_CTRL_MASK\t\t0xf\n#define RTL8366S_PORT_VLAN_CTRL_SHIFT(_p)\t(4 * ((_p) % 4))\n\n\n#define RTL8366S_VLAN_TABLE_READ_BASE\t\t0x018B\n#define RTL8366S_VLAN_TABLE_WRITE_BASE\t\t0x0185\n\n#define RTL8366S_VLAN_TB_CTRL_REG\t\t0x010F\n\n#define RTL8366S_TABLE_ACCESS_CTRL_REG\t\t0x0180\n#define RTL8366S_TABLE_VLAN_READ_CTRL\t\t0x0E01\n#define RTL8366S_TABLE_VLAN_WRITE_CTRL\t\t0x0F01\n\n#define RTL8366S_VLAN_MC_BASE(_x)\t\t(0x0016 + (_x) * 2)\n\n#define RTL8366S_VLAN_MEMBERINGRESS_REG\t\t0x0379\n\n#define RTL8366S_PORT_LINK_STATUS_BASE\t\t0x0060\n#define RTL8366S_PORT_STATUS_SPEED_MASK\t\t0x0003\n#define RTL8366S_PORT_STATUS_DUPLEX_MASK\t0x0004\n#define RTL8366S_PORT_STATUS_LINK_MASK\t\t0x0010\n#define RTL8366S_PORT_STATUS_TXPAUSE_MASK\t0x0020\n#define RTL8366S_PORT_STATUS_RXPAUSE_MASK\t0x0040\n#define RTL8366S_PORT_STATUS_AN_MASK\t\t0x0080\n\n\n#define RTL8366S_PORT_NUM_CPU\t\t5\n#define RTL8366S_NUM_PORTS\t\t6\n#define RTL8366S_NUM_VLANS\t\t16\n#define RTL8366S_NUM_LEDGROUPS\t\t4\n#define RTL8366S_NUM_VIDS\t\t4096\n#define RTL8366S_PRIORITYMAX\t\t7\n#define RTL8366S_FIDMAX\t\t\t7\n\n\n#define RTL8366S_PORT_1\t\t\t(1 << 0) /* In userspace port 0 */\n#define RTL8366S_PORT_2\t\t\t(1 << 1) /* In userspace port 1 */\n#define RTL8366S_PORT_3\t\t\t(1 << 2) /* In userspace port 2 */\n#define RTL8366S_PORT_4\t\t\t(1 << 3) /* In userspace port 3 */\n\n#define RTL8366S_PORT_UNKNOWN\t\t(1 << 4) /* No known connection */\n#define RTL8366S_PORT_CPU\t\t(1 << 5) /* CPU port */\n\n#define RTL8366S_PORT_ALL\t\t(RTL8366S_PORT_1 |\t\\\n\t\t\t\t\t RTL8366S_PORT_2 |\t\\\n\t\t\t\t\t RTL8366S_PORT_3 |\t\\\n\t\t\t\t\t RTL8366S_PORT_4 |\t\\\n\t\t\t\t\t RTL8366S_PORT_UNKNOWN | \\\n\t\t\t\t\t RTL8366S_PORT_CPU)\n\n#define RTL8366S_PORT_ALL_BUT_CPU\t(RTL8366S_PORT_1 |\t\\\n\t\t\t\t\t RTL8366S_PORT_2 |\t\\\n\t\t\t\t\t RTL8366S_PORT_3 |\t\\\n\t\t\t\t\t RTL8366S_PORT_4 |\t\\\n\t\t\t\t\t RTL8366S_PORT_UNKNOWN)\n\n#define RTL8366S_PORT_ALL_EXTERNAL\t(RTL8366S_PORT_1 |\t\\\n\t\t\t\t\t RTL8366S_PORT_2 |\t\\\n\t\t\t\t\t RTL8366S_PORT_3 |\t\\\n\t\t\t\t\t RTL8366S_PORT_4)\n\n#define RTL8366S_PORT_ALL_INTERNAL\t(RTL8366S_PORT_UNKNOWN | \\\n\t\t\t\t\t RTL8366S_PORT_CPU)\n\n#define RTL8366S_VLAN_VID_MASK\t\t0xfff\n#define RTL8366S_VLAN_PRIORITY_SHIFT\t12\n#define RTL8366S_VLAN_PRIORITY_MASK\t0x7\n#define RTL8366S_VLAN_MEMBER_MASK\t0x3f\n#define RTL8366S_VLAN_UNTAG_SHIFT\t6\n#define RTL8366S_VLAN_UNTAG_MASK\t0x3f\n#define RTL8366S_VLAN_FID_SHIFT\t\t12\n#define RTL8366S_VLAN_FID_MASK\t\t0x7\n\n#define RTL8366S_MIB_RXB_ID\t\t0\t/* IfInOctets */\n#define RTL8366S_MIB_TXB_ID\t\t20\t/* IfOutOctets */\n\nstatic struct rtl8366_mib_counter rtl8366s_mib_counters[] = {\n\t{ 0,  0, 4, \"IfInOctets\"\t\t\t\t},\n\t{ 0,  4, 4, \"EtherStatsOctets\"\t\t\t\t},\n\t{ 0,  8, 2, \"EtherStatsUnderSizePkts\"\t\t\t},\n\t{ 0, 10, 2, \"EtherFragments\"\t\t\t\t},\n\t{ 0, 12, 2, \"EtherStatsPkts64Octets\"\t\t\t},\n\t{ 0, 14, 2, \"EtherStatsPkts65to127Octets\"\t\t},\n\t{ 0, 16, 2, \"EtherStatsPkts128to255Octets\"\t\t},\n\t{ 0, 18, 2, \"EtherStatsPkts256to511Octets\"\t\t},\n\t{ 0, 20, 2, \"EtherStatsPkts512to1023Octets\"\t\t},\n\t{ 0, 22, 2, \"EtherStatsPkts1024to1518Octets\"\t\t},\n\t{ 0, 24, 2, \"EtherOversizeStats\"\t\t\t},\n\t{ 0, 26, 2, \"EtherStatsJabbers\"\t\t\t\t},\n\t{ 0, 28, 2, \"IfInUcastPkts\"\t\t\t\t},\n\t{ 0, 30, 2, \"EtherStatsMulticastPkts\"\t\t\t},\n\t{ 0, 32, 2, \"EtherStatsBroadcastPkts\"\t\t\t},\n\t{ 0, 34, 2, \"EtherStatsDropEvents\"\t\t\t},\n\t{ 0, 36, 2, \"Dot3StatsFCSErrors\"\t\t\t},\n\t{ 0, 38, 2, \"Dot3StatsSymbolErrors\"\t\t\t},\n\t{ 0, 40, 2, \"Dot3InPauseFrames\"\t\t\t\t},\n\t{ 0, 42, 2, \"Dot3ControlInUnknownOpcodes\"\t\t},\n\t{ 0, 44, 4, \"IfOutOctets\"\t\t\t\t},\n\t{ 0, 48, 2, \"Dot3StatsSingleCollisionFrames\"\t\t},\n\t{ 0, 50, 2, \"Dot3StatMultipleCollisionFrames\"\t\t},\n\t{ 0, 52, 2, \"Dot3sDeferredTransmissions\"\t\t},\n\t{ 0, 54, 2, \"Dot3StatsLateCollisions\"\t\t\t},\n\t{ 0, 56, 2, \"EtherStatsCollisions\"\t\t\t},\n\t{ 0, 58, 2, \"Dot3StatsExcessiveCollisions\"\t\t},\n\t{ 0, 60, 2, \"Dot3OutPauseFrames\"\t\t\t},\n\t{ 0, 62, 2, \"Dot1dBasePortDelayExceededDiscards\"\t},\n\n\t/*\n\t * The following counters are accessible at a different\n\t * base address.\n\t */\n\t{ 1,  0, 2, \"Dot1dTpPortInDiscards\"\t\t\t},\n\t{ 1,  2, 2, \"IfOutUcastPkts\"\t\t\t\t},\n\t{ 1,  4, 2, \"IfOutMulticastPkts\"\t\t\t},\n\t{ 1,  6, 2, \"IfOutBroadcastPkts\"\t\t\t},\n};\n\n#define REG_WR(_smi, _reg, _val)\t\t\t\t\t\\\n\tdo {\t\t\t\t\t\t\t\t\\\n\t\terr = rtl8366_smi_write_reg(_smi, _reg, _val);\t\t\\\n\t\tif (err)\t\t\t\t\t\t\\\n\t\t\treturn err;\t\t\t\t\t\\\n\t} while (0)\n\n#define REG_RMW(_smi, _reg, _mask, _val)\t\t\t\t\\\n\tdo {\t\t\t\t\t\t\t\t\\\n\t\terr = rtl8366_smi_rmwr(_smi, _reg, _mask, _val);\t\\\n\t\tif (err)\t\t\t\t\t\t\\\n\t\t\treturn err;\t\t\t\t\t\\\n\t} while (0)\n\nstatic int rtl8366s_reset_chip(struct rtl8366_smi *smi)\n{\n\tint timeout = 10;\n\tu32 data;\n\n\trtl8366_smi_write_reg_noack(smi, RTL8366S_RESET_CTRL_REG,\n\t\t\t\t    RTL8366S_CHIP_CTRL_RESET_HW);\n\tdo {\n\t\tmsleep(1);\n\t\tif (rtl8366_smi_read_reg(smi, RTL8366S_RESET_CTRL_REG, &data))\n\t\t\treturn -EIO;\n\n\t\tif (!(data & RTL8366S_CHIP_CTRL_RESET_HW))\n\t\t\tbreak;\n\t} while (--timeout);\n\n\tif (!timeout) {\n\t\tprintk(\"Timeout waiting for the switch to reset\\n\");\n\t\treturn -EIO;\n\t}\n\n\treturn 0;\n}\n\nstatic int rtl8366s_read_phy_reg(struct rtl8366_smi *smi,\n\t\t\t\t u32 phy_no, u32 page, u32 addr, u32 *data)\n{\n\tu32 reg;\n\tint ret;\n\n\tif (phy_no > RTL8366S_PHY_NO_MAX)\n\t\treturn -EINVAL;\n\n\tif (page > RTL8366S_PHY_PAGE_MAX)\n\t\treturn -EINVAL;\n\n\tif (addr > RTL8366S_PHY_ADDR_MAX)\n\t\treturn -EINVAL;\n\n\tret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG,\n\t\t\t\t    RTL8366S_PHY_CTRL_READ);\n\tif (ret)\n\t\treturn ret;\n\n\treg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) |\n\t      ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) |\n\t      (addr & RTL8366S_PHY_REG_MASK);\n\n\tret = rtl8366_smi_write_reg(smi, reg, 0);\n\tif (ret)\n\t\treturn ret;\n\n\tret = rtl8366_smi_read_reg(smi, RTL8366S_PHY_ACCESS_DATA_REG, data);\n\tif (ret)\n\t\treturn ret;\n\n\treturn 0;\n}\n\nstatic int rtl8366s_write_phy_reg(struct rtl8366_smi *smi,\n\t\t\t\t  u32 phy_no, u32 page, u32 addr, u32 data)\n{\n\tu32 reg;\n\tint ret;\n\n\tif (phy_no > RTL8366S_PHY_NO_MAX)\n\t\treturn -EINVAL;\n\n\tif (page > RTL8366S_PHY_PAGE_MAX)\n\t\treturn -EINVAL;\n\n\tif (addr > RTL8366S_PHY_ADDR_MAX)\n\t\treturn -EINVAL;\n\n\tret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG,\n\t\t\t\t    RTL8366S_PHY_CTRL_WRITE);\n\tif (ret)\n\t\treturn ret;\n\n\treg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) |\n\t      ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) |\n\t      (addr & RTL8366S_PHY_REG_MASK);\n\n\tret = rtl8366_smi_write_reg(smi, reg, data);\n\tif (ret)\n\t\treturn ret;\n\n\treturn 0;\n}\n\nstatic int rtl8366s_set_green_port(struct rtl8366_smi *smi, int port, int enable)\n{\n\tint err;\n\tu32 phyData;\n\n\tif (port >= RTL8366S_NUM_PORTS)\n\t\treturn -EINVAL;\n\n\terr = rtl8366s_read_phy_reg(smi, port, 0, RTL8366S_PHY_POWER_SAVING_CTRL_REG, &phyData);\n\tif (err)\n\t\treturn err;\n\n\tif (enable)\n\t\tphyData |= RTL8366S_PHY_POWER_SAVING_MASK;\n\telse\n\t\tphyData &= ~RTL8366S_PHY_POWER_SAVING_MASK;\n\n\terr = rtl8366s_write_phy_reg(smi, port, 0, RTL8366S_PHY_POWER_SAVING_CTRL_REG, phyData);\n\tif (err)\n\t\treturn err;\n\n\treturn 0;\n}\n\nstatic int rtl8366s_set_green(struct rtl8366_smi *smi, int enable)\n{\n\tint err;\n\tunsigned i;\n\tu32 data = 0;\n\n\tif (!enable) {\n\t\tfor (i = 0; i <= RTL8366S_PHY_NO_MAX; i++) {\n\t\t\trtl8366s_set_green_port(smi, i, 0);\n\t\t}\n\t}\n\n\tif (enable)\n\t\tdata = (RTL8366S_GREEN_ETHERNET_TX_BIT | RTL8366S_GREEN_ETHERNET_RX_BIT);\n\n\tREG_RMW(smi, RTL8366S_GREEN_ETHERNET_CTRL_REG, RTL8366S_GREEN_ETHERNET_CTRL_MASK, data);\n\n\treturn 0;\n}\n\nstatic int rtl8366s_setup(struct rtl8366_smi *smi)\n{\n\tstruct rtl8366_platform_data *pdata;\n\tint err;\n\tunsigned i;\n#ifdef CONFIG_OF\n\tstruct device_node *np;\n\tunsigned num_initvals;\n\tconst __be32 *paddr;\n#endif\n\n\tpdata = smi->parent->platform_data;\n\tif (pdata && pdata->num_initvals && pdata->initvals) {\n\t\tdev_info(smi->parent, \"applying initvals\\n\");\n\t\tfor (i = 0; i < pdata->num_initvals; i++)\n\t\t\tREG_WR(smi, pdata->initvals[i].reg,\n\t\t\t       pdata->initvals[i].val);\n\t}\n\n#ifdef CONFIG_OF\n\tnp = smi->parent->of_node;\n\n\tpaddr = of_get_property(np, \"realtek,initvals\", &num_initvals);\n\tif (paddr) {\n\t\tdev_info(smi->parent, \"applying initvals from DTS\\n\");\n\n\t\tif (num_initvals < (2 * sizeof(*paddr)))\n\t\t\treturn -EINVAL;\n\n\t\tnum_initvals /= sizeof(*paddr);\n\n\t\tfor (i = 0; i < num_initvals - 1; i += 2) {\n\t\t\tu32 reg = be32_to_cpup(paddr + i);\n\t\t\tu32 val = be32_to_cpup(paddr + i + 1);\n\n\t\t\tREG_WR(smi, reg, val);\n\t\t}\n\t}\n\n\tif (of_property_read_bool(np, \"realtek,green-ethernet-features\")) {\n\t\tdev_info(smi->parent, \"activating Green Ethernet features\\n\");\n\n\t\terr = rtl8366s_set_green(smi, 1);\n\t\tif (err)\n\t\t\treturn err;\n\n\t\tfor (i = 0; i <= RTL8366S_PHY_NO_MAX; i++) {\n\t\t\terr = rtl8366s_set_green_port(smi, i, 1);\n\t\t\tif (err)\n\t\t\t\treturn err;\n\t\t}\n\t}\n#endif\n\n\t/* set maximum packet length to 1536 bytes */\n\tREG_RMW(smi, RTL8366S_SGCR, RTL8366S_SGCR_MAX_LENGTH_MASK,\n\t\tRTL8366S_SGCR_MAX_LENGTH_1536);\n\n\t/* enable learning for all ports */\n\tREG_WR(smi, RTL8366S_SSCR0, 0);\n\n\t/* enable auto ageing for all ports */\n\tREG_WR(smi, RTL8366S_SSCR1, 0);\n\n\t/*\n\t * discard VLAN tagged packets if the port is not a member of\n\t * the VLAN with which the packets is associated.\n\t */\n\tREG_WR(smi, RTL8366S_VLAN_MEMBERINGRESS_REG, RTL8366S_PORT_ALL);\n\n\t/* don't drop packets whose DA has not been learned */\n\tREG_RMW(smi, RTL8366S_SSCR2, RTL8366S_SSCR2_DROP_UNKNOWN_DA, 0);\n\n\treturn 0;\n}\n\nstatic int rtl8366_get_mib_counter(struct rtl8366_smi *smi, int counter,\n\t\t\t\t   int port, unsigned long long *val)\n{\n\tint i;\n\tint err;\n\tu32 addr, data;\n\tu64 mibvalue;\n\n\tif (port > RTL8366S_NUM_PORTS || counter >= RTL8366S_MIB_COUNT)\n\t\treturn -EINVAL;\n\n\tswitch (rtl8366s_mib_counters[counter].base) {\n\tcase 0:\n\t\taddr = RTL8366S_MIB_COUNTER_BASE +\n\t\t       RTL8366S_MIB_COUNTER_PORT_OFFSET * port;\n\t\tbreak;\n\n\tcase 1:\n\t\taddr = RTL8366S_MIB_COUNTER_BASE2 +\n\t\t\tRTL8366S_MIB_COUNTER_PORT_OFFSET2 * port;\n\t\tbreak;\n\n\tdefault:\n\t\treturn -EINVAL;\n\t}\n\n\taddr += rtl8366s_mib_counters[counter].offset;\n\n\t/*\n\t * Writing access counter address first\n\t * then ASIC will prepare 64bits counter wait for being retrived\n\t */\n\tdata = 0; /* writing data will be discard by ASIC */\n\terr = rtl8366_smi_write_reg(smi, addr, data);\n\tif (err)\n\t\treturn err;\n\n\t/* read MIB control register */\n\terr =  rtl8366_smi_read_reg(smi, RTL8366S_MIB_CTRL_REG, &data);\n\tif (err)\n\t\treturn err;\n\n\tif (data & RTL8366S_MIB_CTRL_BUSY_MASK)\n\t\treturn -EBUSY;\n\n\tif (data & RTL8366S_MIB_CTRL_RESET_MASK)\n\t\treturn -EIO;\n\n\tmibvalue = 0;\n\tfor (i = rtl8366s_mib_counters[counter].length; i > 0; i--) {\n\t\terr = rtl8366_smi_read_reg(smi, addr + (i - 1), &data);\n\t\tif (err)\n\t\t\treturn err;\n\n\t\tmibvalue = (mibvalue << 16) | (data & 0xFFFF);\n\t}\n\n\t*val = mibvalue;\n\treturn 0;\n}\n\nstatic int rtl8366s_get_vlan_4k(struct rtl8366_smi *smi, u32 vid,\n\t\t\t\tstruct rtl8366_vlan_4k *vlan4k)\n{\n\tu32 data[2];\n\tint err;\n\tint i;\n\n\tmemset(vlan4k, '\\0', sizeof(struct rtl8366_vlan_4k));\n\n\tif (vid >= RTL8366S_NUM_VIDS)\n\t\treturn -EINVAL;\n\n\t/* write VID */\n\terr = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE,\n\t\t\t\t    vid & RTL8366S_VLAN_VID_MASK);\n\tif (err)\n\t\treturn err;\n\n\t/* write table access control word */\n\terr = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG,\n\t\t\t\t    RTL8366S_TABLE_VLAN_READ_CTRL);\n\tif (err)\n\t\treturn err;\n\n\tfor (i = 0; i < 2; i++) {\n\t\terr = rtl8366_smi_read_reg(smi,\n\t\t\t\t\t   RTL8366S_VLAN_TABLE_READ_BASE + i,\n\t\t\t\t\t   &data[i]);\n\t\tif (err)\n\t\t\treturn err;\n\t}\n\n\tvlan4k->vid = vid;\n\tvlan4k->untag = (data[1] >> RTL8366S_VLAN_UNTAG_SHIFT) &\n\t\t\tRTL8366S_VLAN_UNTAG_MASK;\n\tvlan4k->member = data[1] & RTL8366S_VLAN_MEMBER_MASK;\n\tvlan4k->fid = (data[1] >> RTL8366S_VLAN_FID_SHIFT) &\n\t\t\tRTL8366S_VLAN_FID_MASK;\n\n\treturn 0;\n}\n\nstatic int rtl8366s_set_vlan_4k(struct rtl8366_smi *smi,\n\t\t\t\tconst struct rtl8366_vlan_4k *vlan4k)\n{\n\tu32 data[2];\n\tint err;\n\tint i;\n\n\tif (vlan4k->vid >= RTL8366S_NUM_VIDS ||\n\t    vlan4k->member > RTL8366S_VLAN_MEMBER_MASK ||\n\t    vlan4k->untag > RTL8366S_VLAN_UNTAG_MASK ||\n\t    vlan4k->fid > RTL8366S_FIDMAX)\n\t\treturn -EINVAL;\n\n\tdata[0] = vlan4k->vid & RTL8366S_VLAN_VID_MASK;\n\tdata[1] = (vlan4k->member & RTL8366S_VLAN_MEMBER_MASK) |\n\t\t  ((vlan4k->untag & RTL8366S_VLAN_UNTAG_MASK) <<\n\t\t\tRTL8366S_VLAN_UNTAG_SHIFT) |\n\t\t  ((vlan4k->fid & RTL8366S_VLAN_FID_MASK) <<\n\t\t\tRTL8366S_VLAN_FID_SHIFT);\n\n\tfor (i = 0; i < 2; i++) {\n\t\terr = rtl8366_smi_write_reg(smi,\n\t\t\t\t\t    RTL8366S_VLAN_TABLE_WRITE_BASE + i,\n\t\t\t\t\t    data[i]);\n\t\tif (err)\n\t\t\treturn err;\n\t}\n\n\t/* write table access control word */\n\terr = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG,\n\t\t\t\t    RTL8366S_TABLE_VLAN_WRITE_CTRL);\n\n\treturn err;\n}\n\nstatic int rtl8366s_get_vlan_mc(struct rtl8366_smi *smi, u32 index,\n\t\t\t\tstruct rtl8366_vlan_mc *vlanmc)\n{\n\tu32 data[2];\n\tint err;\n\tint i;\n\n\tmemset(vlanmc, '\\0', sizeof(struct rtl8366_vlan_mc));\n\n\tif (index >= RTL8366S_NUM_VLANS)\n\t\treturn -EINVAL;\n\n\tfor (i = 0; i < 2; i++) {\n\t\terr = rtl8366_smi_read_reg(smi,\n\t\t\t\t\t   RTL8366S_VLAN_MC_BASE(index) + i,\n\t\t\t\t\t   &data[i]);\n\t\tif (err)\n\t\t\treturn err;\n\t}\n\n\tvlanmc->vid = data[0] & RTL8366S_VLAN_VID_MASK;\n\tvlanmc->priority = (data[0] >> RTL8366S_VLAN_PRIORITY_SHIFT) &\n\t\t\t   RTL8366S_VLAN_PRIORITY_MASK;\n\tvlanmc->untag = (data[1] >> RTL8366S_VLAN_UNTAG_SHIFT) &\n\t\t\tRTL8366S_VLAN_UNTAG_MASK;\n\tvlanmc->member = data[1] & RTL8366S_VLAN_MEMBER_MASK;\n\tvlanmc->fid = (data[1] >> RTL8366S_VLAN_FID_SHIFT) &\n\t\t      RTL8366S_VLAN_FID_MASK;\n\n\treturn 0;\n}\n\nstatic int rtl8366s_set_vlan_mc(struct rtl8366_smi *smi, u32 index,\n\t\t\t\tconst struct rtl8366_vlan_mc *vlanmc)\n{\n\tu32 data[2];\n\tint err;\n\tint i;\n\n\tif (index >= RTL8366S_NUM_VLANS ||\n\t    vlanmc->vid >= RTL8366S_NUM_VIDS ||\n\t    vlanmc->priority > RTL8366S_PRIORITYMAX ||\n\t    vlanmc->member > RTL8366S_VLAN_MEMBER_MASK ||\n\t    vlanmc->untag > RTL8366S_VLAN_UNTAG_MASK ||\n\t    vlanmc->fid > RTL8366S_FIDMAX)\n\t\treturn -EINVAL;\n\n\tdata[0] = (vlanmc->vid & RTL8366S_VLAN_VID_MASK) |\n\t\t  ((vlanmc->priority & RTL8366S_VLAN_PRIORITY_MASK) <<\n\t\t\tRTL8366S_VLAN_PRIORITY_SHIFT);\n\tdata[1] = (vlanmc->member & RTL8366S_VLAN_MEMBER_MASK) |\n\t\t  ((vlanmc->untag & RTL8366S_VLAN_UNTAG_MASK) <<\n\t\t\tRTL8366S_VLAN_UNTAG_SHIFT) |\n\t\t  ((vlanmc->fid & RTL8366S_VLAN_FID_MASK) <<\n\t\t\tRTL8366S_VLAN_FID_SHIFT);\n\n\tfor (i = 0; i < 2; i++) {\n\t\terr = rtl8366_smi_write_reg(smi,\n\t\t\t\t\t    RTL8366S_VLAN_MC_BASE(index) + i,\n\t\t\t\t\t    data[i]);\n\t\tif (err)\n\t\t\treturn err;\n\t}\n\n\treturn 0;\n}\n\nstatic int rtl8366s_get_mc_index(struct rtl8366_smi *smi, int port, int *val)\n{\n\tu32 data;\n\tint err;\n\n\tif (port >= RTL8366S_NUM_PORTS)\n\t\treturn -EINVAL;\n\n\terr = rtl8366_smi_read_reg(smi, RTL8366S_PORT_VLAN_CTRL_REG(port),\n\t\t\t\t   &data);\n\tif (err)\n\t\treturn err;\n\n\t*val = (data >> RTL8366S_PORT_VLAN_CTRL_SHIFT(port)) &\n\t       RTL8366S_PORT_VLAN_CTRL_MASK;\n\n\treturn 0;\n}\n\nstatic int rtl8366s_set_mc_index(struct rtl8366_smi *smi, int port, int index)\n{\n\tif (port >= RTL8366S_NUM_PORTS || index >= RTL8366S_NUM_VLANS)\n\t\treturn -EINVAL;\n\n\treturn rtl8366_smi_rmwr(smi, RTL8366S_PORT_VLAN_CTRL_REG(port),\n\t\t\t\tRTL8366S_PORT_VLAN_CTRL_MASK <<\n\t\t\t\t\tRTL8366S_PORT_VLAN_CTRL_SHIFT(port),\n\t\t\t\t(index & RTL8366S_PORT_VLAN_CTRL_MASK) <<\n\t\t\t\t\tRTL8366S_PORT_VLAN_CTRL_SHIFT(port));\n}\n\nstatic int rtl8366s_enable_vlan(struct rtl8366_smi *smi, int enable)\n{\n\treturn rtl8366_smi_rmwr(smi, RTL8366S_SGCR, RTL8366S_SGCR_EN_VLAN,\n\t\t\t\t(enable) ? RTL8366S_SGCR_EN_VLAN : 0);\n}\n\nstatic int rtl8366s_enable_vlan4k(struct rtl8366_smi *smi, int enable)\n{\n\treturn rtl8366_smi_rmwr(smi, RTL8366S_VLAN_TB_CTRL_REG,\n\t\t\t\t1, (enable) ? 1 : 0);\n}\n\nstatic int rtl8366s_is_vlan_valid(struct rtl8366_smi *smi, unsigned vlan)\n{\n\tunsigned max = RTL8366S_NUM_VLANS;\n\n\tif (smi->vlan4k_enabled)\n\t\tmax = RTL8366S_NUM_VIDS - 1;\n\n\tif (vlan == 0 || vlan >= max)\n\t\treturn 0;\n\n\treturn 1;\n}\n\nstatic int rtl8366s_enable_port(struct rtl8366_smi *smi, int port, int enable)\n{\n\treturn rtl8366_smi_rmwr(smi, RTL8366S_PECR, (1 << port),\n\t\t\t\t(enable) ? 0 : (1 << port));\n}\n\nstatic int rtl8366s_sw_reset_mibs(struct switch_dev *dev,\n\t\t\t\t  const struct switch_attr *attr,\n\t\t\t\t  struct switch_val *val)\n{\n\tstruct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);\n\n\treturn rtl8366_smi_rmwr(smi, RTL8366S_MIB_CTRL_REG, 0, (1 << 2));\n}\n\nstatic int rtl8366s_sw_get_blinkrate(struct switch_dev *dev,\n\t\t\t\t     const struct switch_attr *attr,\n\t\t\t\t     struct switch_val *val)\n{\n\tstruct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);\n\tu32 data;\n\n\trtl8366_smi_read_reg(smi, RTL8366S_LED_BLINKRATE_REG, &data);\n\n\tval->value.i = (data & (RTL8366S_LED_BLINKRATE_MASK));\n\n\treturn 0;\n}\n\nstatic int rtl8366s_sw_set_blinkrate(struct switch_dev *dev,\n\t\t\t\t    const struct switch_attr *attr,\n\t\t\t\t    struct switch_val *val)\n{\n\tstruct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);\n\n\tif (val->value.i >= 6)\n\t\treturn -EINVAL;\n\n\treturn rtl8366_smi_rmwr(smi, RTL8366S_LED_BLINKRATE_REG,\n\t\t\t\tRTL8366S_LED_BLINKRATE_MASK,\n\t\t\t\tval->value.i);\n}\n\nstatic int rtl8366s_sw_get_max_length(struct switch_dev *dev,\n\t\t\t\t\tconst struct switch_attr *attr,\n\t\t\t\t\tstruct switch_val *val)\n{\n\tstruct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);\n\tu32 data;\n\n\trtl8366_smi_read_reg(smi, RTL8366S_SGCR, &data);\n\n\tval->value.i = ((data & (RTL8366S_SGCR_MAX_LENGTH_MASK)) >> 4);\n\n\treturn 0;\n}\n\nstatic int rtl8366s_sw_set_max_length(struct switch_dev *dev,\n\t\t\t\t\tconst struct switch_attr *attr,\n\t\t\t\t\tstruct switch_val *val)\n{\n\tstruct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);\n\tchar length_code;\n\n\tswitch (val->value.i) {\n\t\tcase 0:\n\t\t\tlength_code = RTL8366S_SGCR_MAX_LENGTH_1522;\n\t\t\tbreak;\n\t\tcase 1:\n\t\t\tlength_code = RTL8366S_SGCR_MAX_LENGTH_1536;\n\t\t\tbreak;\n\t\tcase 2:\n\t\t\tlength_code = RTL8366S_SGCR_MAX_LENGTH_1552;\n\t\t\tbreak;\n\t\tcase 3:\n\t\t\tlength_code = RTL8366S_SGCR_MAX_LENGTH_16000;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\treturn -EINVAL;\n\t}\n\n\treturn rtl8366_smi_rmwr(smi, RTL8366S_SGCR,\n\t\t\tRTL8366S_SGCR_MAX_LENGTH_MASK,\n\t\t\tlength_code);\n}\n\nstatic int rtl8366s_sw_get_learning_enable(struct switch_dev *dev,\n\t\t\t\t\t   const struct switch_attr *attr,\n\t\t\t\t\t   struct switch_val *val)\n{\n\tstruct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);\n\tu32 data;\n\n\trtl8366_smi_read_reg(smi,RTL8366S_SSCR0, &data);\n\tval->value.i = !data;\n\n\treturn 0;\n}\n\n\nstatic int rtl8366s_sw_set_learning_enable(struct switch_dev *dev,\n\t\t\t\t\t   const struct switch_attr *attr,\n\t\t\t\t\t   struct switch_val *val)\n{\n\tstruct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);\n\tu32 portmask = 0;\n\tint err = 0;\n\n\tif (!val->value.i)\n\t\tportmask = RTL8366S_PORT_ALL;\n\n\t/* set learning for all ports */\n\tREG_WR(smi, RTL8366S_SSCR0, portmask);\n\n\t/* set auto ageing for all ports */\n\tREG_WR(smi, RTL8366S_SSCR1, portmask);\n\n\treturn 0;\n}\n\nstatic int rtl8366s_sw_get_green(struct switch_dev *dev,\n\t\t\t      const struct switch_attr *attr,\n\t\t\t      struct switch_val *val)\n{\n\tstruct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);\n\tu32 data;\n\tint err;\n\n\terr = rtl8366_smi_read_reg(smi, RTL8366S_GREEN_ETHERNET_CTRL_REG, &data);\n\tif (err)\n\t\treturn err;\n\n\tval->value.i = ((data & (RTL8366S_GREEN_ETHERNET_TX_BIT | RTL8366S_GREEN_ETHERNET_RX_BIT)) != 0) ? 1 : 0;\n\n\treturn 0;\n}\n\nstatic int rtl8366s_sw_set_green(struct switch_dev *dev,\n\t\t\t\t const struct switch_attr *attr,\n\t\t\t\t struct switch_val *val)\n{\n\tstruct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);\n\n\treturn rtl8366s_set_green(smi, val->value.i);\n}\n\nstatic int rtl8366s_sw_get_port_link(struct switch_dev *dev,\n\t\t\t\t     int port,\n\t\t\t\t     struct switch_port_link *link)\n{\n\tstruct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);\n\tu32 data = 0;\n\tu32 speed;\n\n\tif (port >= RTL8366S_NUM_PORTS)\n\t\treturn -EINVAL;\n\n\trtl8366_smi_read_reg(smi, RTL8366S_PORT_LINK_STATUS_BASE + (port / 2),\n\t\t\t     &data);\n\n\tif (port % 2)\n\t\tdata = data >> 8;\n\n\tlink->link = !!(data & RTL8366S_PORT_STATUS_LINK_MASK);\n\tif (!link->link)\n\t\treturn 0;\n\n\tlink->duplex = !!(data & RTL8366S_PORT_STATUS_DUPLEX_MASK);\n\tlink->rx_flow = !!(data & RTL8366S_PORT_STATUS_RXPAUSE_MASK);\n\tlink->tx_flow = !!(data & RTL8366S_PORT_STATUS_TXPAUSE_MASK);\n\tlink->aneg = !!(data & RTL8366S_PORT_STATUS_AN_MASK);\n\n\tspeed = (data & RTL8366S_PORT_STATUS_SPEED_MASK);\n\tswitch (speed) {\n\tcase 0:\n\t\tlink->speed = SWITCH_PORT_SPEED_10;\n\t\tbreak;\n\tcase 1:\n\t\tlink->speed = SWITCH_PORT_SPEED_100;\n\t\tbreak;\n\tcase 2:\n\t\tlink->speed = SWITCH_PORT_SPEED_1000;\n\t\tbreak;\n\tdefault:\n\t\tlink->speed = SWITCH_PORT_SPEED_UNKNOWN;\n\t\tbreak;\n\t}\n\n\treturn 0;\n}\n\nstatic int rtl8366s_sw_set_port_led(struct switch_dev *dev,\n\t\t\t\t    const struct switch_attr *attr,\n\t\t\t\t    struct switch_val *val)\n{\n\tstruct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);\n\tu32 data;\n\tu32 mask;\n\tu32 reg;\n\n\tif (val->port_vlan >= RTL8366S_NUM_PORTS ||\n\t    (1 << val->port_vlan) == RTL8366S_PORT_UNKNOWN)\n\t\treturn -EINVAL;\n\n\tif (val->port_vlan == RTL8366S_PORT_NUM_CPU) {\n\t\treg = RTL8366S_LED_BLINKRATE_REG;\n\t\tmask = 0xF << 4;\n\t\tdata = val->value.i << 4;\n\t} else {\n\t\treg = RTL8366S_LED_CTRL_REG;\n\t\tmask = 0xF << (val->port_vlan * 4),\n\t\tdata = val->value.i << (val->port_vlan * 4);\n\t}\n\n\treturn rtl8366_smi_rmwr(smi, reg, mask, data);\n}\n\nstatic int rtl8366s_sw_get_port_led(struct switch_dev *dev,\n\t\t\t\t    const struct switch_attr *attr,\n\t\t\t\t    struct switch_val *val)\n{\n\tstruct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);\n\tu32 data = 0;\n\n\tif (val->port_vlan >= RTL8366S_NUM_LEDGROUPS)\n\t\treturn -EINVAL;\n\n\trtl8366_smi_read_reg(smi, RTL8366S_LED_CTRL_REG, &data);\n\tval->value.i = (data >> (val->port_vlan * 4)) & 0x000F;\n\n\treturn 0;\n}\n\nstatic int rtl8366s_sw_get_green_port(struct switch_dev *dev,\n\t\t\t\t      const struct switch_attr *attr,\n\t\t\t\t      struct switch_val *val)\n{\n\tstruct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);\n\tint err;\n\tu32 phyData;\n\n\tif (val->port_vlan >= RTL8366S_NUM_PORTS)\n\t\treturn -EINVAL;\n\n\terr = rtl8366s_read_phy_reg(smi, val->port_vlan, 0, RTL8366S_PHY_POWER_SAVING_CTRL_REG, &phyData);\n\tif (err)\n\t\treturn err;\n\n\tval->value.i = ((phyData & RTL8366S_PHY_POWER_SAVING_MASK) != 0) ? 1 : 0;\n\n\treturn 0;\n}\n\nstatic int rtl8366s_sw_set_green_port(struct switch_dev *dev,\n\t\t\t\t      const struct switch_attr *attr,\n\t\t\t\t      struct switch_val *val)\n{\n\tstruct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);\n\treturn rtl8366s_set_green_port(smi, val->port_vlan, val->value.i);\n}\n\nstatic int rtl8366s_sw_reset_port_mibs(struct switch_dev *dev,\n\t\t\t\t       const struct switch_attr *attr,\n\t\t\t\t       struct switch_val *val)\n{\n\tstruct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);\n\n\tif (val->port_vlan >= RTL8366S_NUM_PORTS)\n\t\treturn -EINVAL;\n\n\n\treturn rtl8366_smi_rmwr(smi, RTL8366S_MIB_CTRL_REG,\n\t\t\t\t0, (1 << (val->port_vlan + 3)));\n}\n\nstatic int rtl8366s_sw_get_port_stats(struct switch_dev *dev, int port,\n                                        struct switch_port_stats *stats)\n{\n\treturn (rtl8366_sw_get_port_stats(dev, port, stats,\n\t\t\t\tRTL8366S_MIB_TXB_ID, RTL8366S_MIB_RXB_ID));\n}\n\nstatic struct switch_attr rtl8366s_globals[] = {\n\t{\n\t\t.type = SWITCH_TYPE_INT,\n\t\t.name = \"enable_learning\",\n\t\t.description = \"Enable learning, enable aging\",\n\t\t.set = rtl8366s_sw_set_learning_enable,\n\t\t.get = rtl8366s_sw_get_learning_enable,\n\t\t.max = 1,\n\t}, {\n\t\t.type = SWITCH_TYPE_INT,\n\t\t.name = \"enable_vlan\",\n\t\t.description = \"Enable VLAN mode\",\n\t\t.set = rtl8366_sw_set_vlan_enable,\n\t\t.get = rtl8366_sw_get_vlan_enable,\n\t\t.max = 1,\n\t\t.ofs = 1\n\t}, {\n\t\t.type = SWITCH_TYPE_INT,\n\t\t.name = \"enable_vlan4k\",\n\t\t.description = \"Enable VLAN 4K mode\",\n\t\t.set = rtl8366_sw_set_vlan_enable,\n\t\t.get = rtl8366_sw_get_vlan_enable,\n\t\t.max = 1,\n\t\t.ofs = 2\n\t}, {\n\t\t.type = SWITCH_TYPE_NOVAL,\n\t\t.name = \"reset_mibs\",\n\t\t.description = \"Reset all MIB counters\",\n\t\t.set = rtl8366s_sw_reset_mibs,\n\t}, {\n\t\t.type = SWITCH_TYPE_INT,\n\t\t.name = \"blinkrate\",\n\t\t.description = \"Get/Set LED blinking rate (0 = 43ms, 1 = 84ms,\"\n\t\t\" 2 = 120ms, 3 = 170ms, 4 = 340ms, 5 = 670ms)\",\n\t\t.set = rtl8366s_sw_set_blinkrate,\n\t\t.get = rtl8366s_sw_get_blinkrate,\n\t\t.max = 5\n\t}, {\n\t\t.type = SWITCH_TYPE_INT,\n\t\t.name = \"max_length\",\n\t\t.description = \"Get/Set the maximum length of valid packets\"\n\t\t\" (0 = 1522, 1 = 1536, 2 = 1552, 3 = 16000 (9216?))\",\n\t\t.set = rtl8366s_sw_set_max_length,\n\t\t.get = rtl8366s_sw_get_max_length,\n\t\t.max = 3,\n\t}, {\n\t\t.type = SWITCH_TYPE_INT,\n\t\t.name = \"green_mode\",\n\t\t.description = \"Get/Set the router green feature\",\n\t\t.set = rtl8366s_sw_set_green,\n\t\t.get = rtl8366s_sw_get_green,\n\t\t.max = 1,\n\t},\n};\n\nstatic struct switch_attr rtl8366s_port[] = {\n\t{\n\t\t.type = SWITCH_TYPE_NOVAL,\n\t\t.name = \"reset_mib\",\n\t\t.description = \"Reset single port MIB counters\",\n\t\t.set = rtl8366s_sw_reset_port_mibs,\n\t}, {\n\t\t.type = SWITCH_TYPE_STRING,\n\t\t.name = \"mib\",\n\t\t.description = \"Get MIB counters for port\",\n\t\t.max = 33,\n\t\t.set = NULL,\n\t\t.get = rtl8366_sw_get_port_mib,\n\t}, {\n\t\t.type = SWITCH_TYPE_INT,\n\t\t.name = \"led\",\n\t\t.description = \"Get/Set port group (0 - 3) led mode (0 - 15)\",\n\t\t.max = 15,\n\t\t.set = rtl8366s_sw_set_port_led,\n\t\t.get = rtl8366s_sw_get_port_led,\n\t}, {\n\t\t.type = SWITCH_TYPE_INT,\n\t\t.name = \"green_port\",\n\t\t.description = \"Get/Set port green feature (0 - 1)\",\n\t\t.max = 1,\n\t\t.set = rtl8366s_sw_set_green_port,\n\t\t.get = rtl8366s_sw_get_green_port,\n\t},\n};\n\nstatic struct switch_attr rtl8366s_vlan[] = {\n\t{\n\t\t.type = SWITCH_TYPE_STRING,\n\t\t.name = \"info\",\n\t\t.description = \"Get vlan information\",\n\t\t.max = 1,\n\t\t.set = NULL,\n\t\t.get = rtl8366_sw_get_vlan_info,\n\t}, {\n\t\t.type = SWITCH_TYPE_INT,\n\t\t.name = \"fid\",\n\t\t.description = \"Get/Set vlan FID\",\n\t\t.max = RTL8366S_FIDMAX,\n\t\t.set = rtl8366_sw_set_vlan_fid,\n\t\t.get = rtl8366_sw_get_vlan_fid,\n\t},\n};\n\nstatic const struct switch_dev_ops rtl8366_ops = {\n\t.attr_global = {\n\t\t.attr = rtl8366s_globals,\n\t\t.n_attr = ARRAY_SIZE(rtl8366s_globals),\n\t},\n\t.attr_port = {\n\t\t.attr = rtl8366s_port,\n\t\t.n_attr = ARRAY_SIZE(rtl8366s_port),\n\t},\n\t.attr_vlan = {\n\t\t.attr = rtl8366s_vlan,\n\t\t.n_attr = ARRAY_SIZE(rtl8366s_vlan),\n\t},\n\n\t.get_vlan_ports = rtl8366_sw_get_vlan_ports,\n\t.set_vlan_ports = rtl8366_sw_set_vlan_ports,\n\t.get_port_pvid = rtl8366_sw_get_port_pvid,\n\t.set_port_pvid = rtl8366_sw_set_port_pvid,\n\t.reset_switch = rtl8366_sw_reset_switch,\n\t.get_port_link = rtl8366s_sw_get_port_link,\n\t.get_port_stats = rtl8366s_sw_get_port_stats,\n};\n\nstatic int rtl8366s_switch_init(struct rtl8366_smi *smi)\n{\n\tstruct switch_dev *dev = &smi->sw_dev;\n\tint err;\n\n\tdev->name = \"RTL8366S\";\n\tdev->cpu_port = RTL8366S_PORT_NUM_CPU;\n\tdev->ports = RTL8366S_NUM_PORTS;\n\tdev->vlans = RTL8366S_NUM_VIDS;\n\tdev->ops = &rtl8366_ops;\n\tdev->alias = dev_name(smi->parent);\n\n\terr = register_switch(dev, NULL);\n\tif (err)\n\t\tdev_err(smi->parent, \"switch registration failed\\n\");\n\n\treturn err;\n}\n\nstatic void rtl8366s_switch_cleanup(struct rtl8366_smi *smi)\n{\n\tunregister_switch(&smi->sw_dev);\n}\n\nstatic int rtl8366s_mii_read(struct mii_bus *bus, int addr, int reg)\n{\n\tstruct rtl8366_smi *smi = bus->priv;\n\tu32 val = 0;\n\tint err;\n\n\terr = rtl8366s_read_phy_reg(smi, addr, 0, reg, &val);\n\tif (err)\n\t\treturn 0xffff;\n\n\treturn val;\n}\n\nstatic int rtl8366s_mii_write(struct mii_bus *bus, int addr, int reg, u16 val)\n{\n\tstruct rtl8366_smi *smi = bus->priv;\n\tu32 t;\n\tint err;\n\n\terr = rtl8366s_write_phy_reg(smi, addr, 0, reg, val);\n\t/* flush write */\n\t(void) rtl8366s_read_phy_reg(smi, addr, 0, reg, &t);\n\n\treturn err;\n}\n\nstatic int rtl8366s_detect(struct rtl8366_smi *smi)\n{\n\tu32 chip_id = 0;\n\tu32 chip_ver = 0;\n\tint ret;\n\n\tret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_ID_REG, &chip_id);\n\tif (ret) {\n\t\tdev_err(smi->parent, \"unable to read chip id\\n\");\n\t\treturn ret;\n\t}\n\n\tswitch (chip_id) {\n\tcase RTL8366S_CHIP_ID_8366:\n\t\tbreak;\n\tdefault:\n\t\tdev_err(smi->parent, \"unknown chip id (%04x)\\n\", chip_id);\n\t\treturn -ENODEV;\n\t}\n\n\tret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_VERSION_CTRL_REG,\n\t\t\t\t   &chip_ver);\n\tif (ret) {\n\t\tdev_err(smi->parent, \"unable to read chip version\\n\");\n\t\treturn ret;\n\t}\n\n\tdev_info(smi->parent, \"RTL%04x ver. %u chip found\\n\",\n\t\t chip_id, chip_ver & RTL8366S_CHIP_VERSION_MASK);\n\n\treturn 0;\n}\n\nstatic struct rtl8366_smi_ops rtl8366s_smi_ops = {\n\t.detect\t\t= rtl8366s_detect,\n\t.reset_chip\t= rtl8366s_reset_chip,\n\t.setup\t\t= rtl8366s_setup,\n\n\t.mii_read\t= rtl8366s_mii_read,\n\t.mii_write\t= rtl8366s_mii_write,\n\n\t.get_vlan_mc\t= rtl8366s_get_vlan_mc,\n\t.set_vlan_mc\t= rtl8366s_set_vlan_mc,\n\t.get_vlan_4k\t= rtl8366s_get_vlan_4k,\n\t.set_vlan_4k\t= rtl8366s_set_vlan_4k,\n\t.get_mc_index\t= rtl8366s_get_mc_index,\n\t.set_mc_index\t= rtl8366s_set_mc_index,\n\t.get_mib_counter = rtl8366_get_mib_counter,\n\t.is_vlan_valid\t= rtl8366s_is_vlan_valid,\n\t.enable_vlan\t= rtl8366s_enable_vlan,\n\t.enable_vlan4k\t= rtl8366s_enable_vlan4k,\n\t.enable_port\t= rtl8366s_enable_port,\n};\n\nstatic int rtl8366s_probe(struct platform_device *pdev)\n{\n\tstatic int rtl8366_smi_version_printed;\n\tstruct rtl8366_smi *smi;\n\tint err;\n\n\tif (!rtl8366_smi_version_printed++)\n\t\tprintk(KERN_NOTICE RTL8366S_DRIVER_DESC\n\t\t       \" version \" RTL8366S_DRIVER_VER\"\\n\");\n\n\tsmi = rtl8366_smi_probe(pdev);\n\tif (IS_ERR(smi))\n\t\treturn PTR_ERR(smi);\n\n\tsmi->clk_delay = 10;\n\tsmi->cmd_read = 0xa9;\n\tsmi->cmd_write = 0xa8;\n\tsmi->ops = &rtl8366s_smi_ops;\n\tsmi->cpu_port = RTL8366S_PORT_NUM_CPU;\n\tsmi->num_ports = RTL8366S_NUM_PORTS;\n\tsmi->num_vlan_mc = RTL8366S_NUM_VLANS;\n\tsmi->mib_counters = rtl8366s_mib_counters;\n\tsmi->num_mib_counters = ARRAY_SIZE(rtl8366s_mib_counters);\n\n\terr = rtl8366_smi_init(smi);\n\tif (err)\n\t\tgoto err_free_smi;\n\n\tplatform_set_drvdata(pdev, smi);\n\n\terr = rtl8366s_switch_init(smi);\n\tif (err)\n\t\tgoto err_clear_drvdata;\n\n\treturn 0;\n\n err_clear_drvdata:\n\tplatform_set_drvdata(pdev, NULL);\n\trtl8366_smi_cleanup(smi);\n err_free_smi:\n\tkfree(smi);\n\treturn err;\n}\n\nstatic int rtl8366s_remove(struct platform_device *pdev)\n{\n\tstruct rtl8366_smi *smi = platform_get_drvdata(pdev);\n\n\tif (smi) {\n\t\trtl8366s_switch_cleanup(smi);\n\t\tplatform_set_drvdata(pdev, NULL);\n\t\trtl8366_smi_cleanup(smi);\n\t\tkfree(smi);\n\t}\n\n\treturn 0;\n}\n\n#ifdef CONFIG_OF\nstatic const struct of_device_id rtl8366s_match[] = {\n\t{ .compatible = \"realtek,rtl8366s\" },\n\t{},\n};\nMODULE_DEVICE_TABLE(of, rtl8366s_match);\n#endif\n\nstatic struct platform_driver rtl8366s_driver = {\n\t.driver = {\n\t\t.name\t\t= RTL8366S_DRIVER_NAME,\n\t\t.owner\t\t= THIS_MODULE,\n#ifdef CONFIG_OF\n\t\t.of_match_table = of_match_ptr(rtl8366s_match),\n#endif\n\t},\n\t.probe\t\t= rtl8366s_probe,\n\t.remove\t\t= rtl8366s_remove,\n};\n\nstatic int __init rtl8366s_module_init(void)\n{\n\treturn platform_driver_register(&rtl8366s_driver);\n}\nmodule_init(rtl8366s_module_init);\n\nstatic void __exit rtl8366s_module_exit(void)\n{\n\tplatform_driver_unregister(&rtl8366s_driver);\n}\nmodule_exit(rtl8366s_module_exit);\n\nMODULE_DESCRIPTION(RTL8366S_DRIVER_DESC);\nMODULE_VERSION(RTL8366S_DRIVER_VER);\nMODULE_AUTHOR(\"Gabor Juhos <juhosg@openwrt.org>\");\nMODULE_AUTHOR(\"Antti Seppälä <a.seppala@gmail.com>\");\nMODULE_LICENSE(\"GPL v2\");\nMODULE_ALIAS(\"platform:\" RTL8366S_DRIVER_NAME);\n"
  },
  {
    "path": "target/linux/generic/files/drivers/net/phy/rtl8367.c",
    "content": "/*\n * Platform driver for the Realtek RTL8367R/M ethernet switches\n *\n * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of the GNU General Public License version 2 as published\n * by the Free Software Foundation.\n */\n\n#include <linux/kernel.h>\n#include <linux/module.h>\n#include <linux/init.h>\n#include <linux/device.h>\n#include <linux/of.h>\n#include <linux/of_platform.h>\n#include <linux/delay.h>\n#include <linux/skbuff.h>\n#include <linux/rtl8367.h>\n\n#include \"rtl8366_smi.h\"\n\n#define RTL8367_RESET_DELAY\t1000\t/* msecs*/\n\n#define RTL8367_PHY_ADDR_MAX\t8\n#define RTL8367_PHY_REG_MAX\t31\n\n#define RTL8367_VID_MASK\t0xffff\n#define RTL8367_FID_MASK\t0xfff\n#define RTL8367_UNTAG_MASK\t0xffff\n#define RTL8367_MEMBER_MASK\t0xffff\n\n#define RTL8367_PORT_CFG_REG(_p)\t\t(0x000e + 0x20 * (_p))\n#define   RTL8367_PORT_CFG_EGRESS_MODE_SHIFT\t4\n#define   RTL8367_PORT_CFG_EGRESS_MODE_MASK\t0x3\n#define   RTL8367_PORT_CFG_EGRESS_MODE_ORIGINAL\t0\n#define   RTL8367_PORT_CFG_EGRESS_MODE_KEEP\t1\n#define   RTL8367_PORT_CFG_EGRESS_MODE_PRI\t2\n#define   RTL8367_PORT_CFG_EGRESS_MODE_REAL\t3\n\n#define RTL8367_BYPASS_LINE_RATE_REG\t\t0x03f7\n\n#define RTL8367_TA_CTRL_REG\t\t\t0x0500\n#define   RTL8367_TA_CTRL_STATUS\t\tBIT(12)\n#define   RTL8367_TA_CTRL_METHOD\t\tBIT(5)\n#define   RTL8367_TA_CTRL_CMD_SHIFT\t\t4\n#define   RTL8367_TA_CTRL_CMD_READ\t\t0\n#define   RTL8367_TA_CTRL_CMD_WRITE\t\t1\n#define   RTL8367_TA_CTRL_TABLE_SHIFT\t\t0\n#define   RTL8367_TA_CTRL_TABLE_ACLRULE\t\t1\n#define   RTL8367_TA_CTRL_TABLE_ACLACT\t\t2\n#define   RTL8367_TA_CTRL_TABLE_CVLAN\t\t3\n#define   RTL8367_TA_CTRL_TABLE_L2\t\t4\n#define   RTL8367_TA_CTRL_CVLAN_READ \\\n\t\t((RTL8367_TA_CTRL_CMD_READ << RTL8367_TA_CTRL_CMD_SHIFT) | \\\n\t\t RTL8367_TA_CTRL_TABLE_CVLAN)\n#define   RTL8367_TA_CTRL_CVLAN_WRITE \\\n\t\t((RTL8367_TA_CTRL_CMD_WRITE << RTL8367_TA_CTRL_CMD_SHIFT) | \\\n\t\t RTL8367_TA_CTRL_TABLE_CVLAN)\n\n#define RTL8367_TA_ADDR_REG\t\t\t0x0501\n#define   RTL8367_TA_ADDR_MASK\t\t\t0x3fff\n\n#define RTL8367_TA_DATA_REG(_x)\t\t\t(0x0503 + (_x))\n#define   RTL8367_TA_VLAN_DATA_SIZE\t\t4\n#define   RTL8367_TA_VLAN_VID_MASK\t\tRTL8367_VID_MASK\n#define   RTL8367_TA_VLAN_MEMBER_SHIFT\t\t0\n#define   RTL8367_TA_VLAN_MEMBER_MASK\t\tRTL8367_MEMBER_MASK\n#define   RTL8367_TA_VLAN_FID_SHIFT\t\t0\n#define   RTL8367_TA_VLAN_FID_MASK\t\tRTL8367_FID_MASK\n#define   RTL8367_TA_VLAN_UNTAG1_SHIFT\t\t14\n#define   RTL8367_TA_VLAN_UNTAG1_MASK\t\t0x3\n#define   RTL8367_TA_VLAN_UNTAG2_SHIFT\t\t0\n#define   RTL8367_TA_VLAN_UNTAG2_MASK\t\t0x3fff\n\n#define RTL8367_VLAN_PVID_CTRL_REG(_p)\t\t(0x0700 + (_p) / 2)\n#define RTL8367_VLAN_PVID_CTRL_MASK\t\t0x1f\n#define RTL8367_VLAN_PVID_CTRL_SHIFT(_p)\t(8 * ((_p) % 2))\n\n#define RTL8367_VLAN_MC_BASE(_x)\t\t(0x0728 + (_x) * 4)\n#define   RTL8367_VLAN_MC_DATA_SIZE\t\t4\n#define   RTL8367_VLAN_MC_MEMBER_SHIFT\t\t0\n#define   RTL8367_VLAN_MC_MEMBER_MASK\t\tRTL8367_MEMBER_MASK\n#define   RTL8367_VLAN_MC_FID_SHIFT\t\t0\n#define   RTL8367_VLAN_MC_FID_MASK\t\tRTL8367_FID_MASK\n#define   RTL8367_VLAN_MC_EVID_SHIFT\t\t0\n#define   RTL8367_VLAN_MC_EVID_MASK\t\tRTL8367_VID_MASK\n\n#define RTL8367_VLAN_CTRL_REG\t\t\t0x07a8\n#define   RTL8367_VLAN_CTRL_ENABLE\t\tBIT(0)\n\n#define RTL8367_VLAN_INGRESS_REG\t\t0x07a9\n\n#define RTL8367_PORT_ISOLATION_REG(_p)\t\t(0x08a2 + (_p))\n\n#define RTL8367_MIB_COUNTER_REG(_x)\t\t(0x1000 + (_x))\n\n#define RTL8367_MIB_ADDRESS_REG\t\t\t0x1004\n\n#define RTL8367_MIB_CTRL_REG(_x)\t\t(0x1005 + (_x))\n#define   RTL8367_MIB_CTRL_GLOBAL_RESET_MASK\tBIT(11)\n#define   RTL8367_MIB_CTRL_QM_RESET_MASK\tBIT(10)\n#define   RTL8367_MIB_CTRL_PORT_RESET_MASK(_p)\tBIT(2 + (_p))\n#define   RTL8367_MIB_CTRL_RESET_MASK\t\tBIT(1)\n#define   RTL8367_MIB_CTRL_BUSY_MASK\t\tBIT(0)\n\n#define RTL8367_MIB_COUNT\t\t\t36\n#define RTL8367_MIB_COUNTER_PORT_OFFSET\t\t0x0050\n\n#define RTL8367_SWC0_REG\t\t\t0x1200\n#define   RTL8367_SWC0_MAX_LENGTH_SHIFT\t\t13\n#define   RTL8367_SWC0_MAX_LENGTH(_x)\t\t((_x) << 13)\n#define   RTL8367_SWC0_MAX_LENGTH_MASK\t\tRTL8367_SWC0_MAX_LENGTH(0x3)\n#define   RTL8367_SWC0_MAX_LENGTH_1522\t\tRTL8367_SWC0_MAX_LENGTH(0)\n#define   RTL8367_SWC0_MAX_LENGTH_1536\t\tRTL8367_SWC0_MAX_LENGTH(1)\n#define   RTL8367_SWC0_MAX_LENGTH_1552\t\tRTL8367_SWC0_MAX_LENGTH(2)\n#define   RTL8367_SWC0_MAX_LENGTH_16000\t\tRTL8367_SWC0_MAX_LENGTH(3)\n\n#define RTL8367_CHIP_NUMBER_REG\t\t\t0x1300\n\n#define RTL8367_CHIP_VER_REG\t\t\t0x1301\n#define   RTL8367_CHIP_VER_RLVID_SHIFT\t\t12\n#define   RTL8367_CHIP_VER_RLVID_MASK\t\t0xf\n#define   RTL8367_CHIP_VER_MCID_SHIFT\t\t8\n#define   RTL8367_CHIP_VER_MCID_MASK\t\t0xf\n#define   RTL8367_CHIP_VER_BOID_SHIFT\t\t4\n#define   RTL8367_CHIP_VER_BOID_MASK\t\t0xf\n\n#define RTL8367_CHIP_MODE_REG\t\t\t0x1302\n#define   RTL8367_CHIP_MODE_MASK\t\t0x7\n\n#define RTL8367_CHIP_DEBUG0_REG\t\t\t0x1303\n#define   RTL8367_CHIP_DEBUG0_DUMMY0(_x)\tBIT(8 + (_x))\n\n#define RTL8367_CHIP_DEBUG1_REG\t\t\t0x1304\n\n#define RTL8367_DIS_REG\t\t\t\t0x1305\n#define   RTL8367_DIS_SKIP_MII_RXER(_x)\t\tBIT(12 + (_x))\n#define   RTL8367_DIS_RGMII_SHIFT(_x)\t\t(4 * (_x))\n#define   RTL8367_DIS_RGMII_MASK\t\t0x7\n\n#define RTL8367_EXT_RGMXF_REG(_x)\t\t(0x1306 + (_x))\n#define   RTL8367_EXT_RGMXF_DUMMY0_SHIFT\t5\n#define   RTL8367_EXT_RGMXF_DUMMY0_MASK\t0x7ff\n#define   RTL8367_EXT_RGMXF_TXDELAY_SHIFT\t3\n#define   RTL8367_EXT_RGMXF_TXDELAY_MASK\t1\n#define   RTL8367_EXT_RGMXF_RXDELAY_MASK\t0x7\n\n#define RTL8367_DI_FORCE_REG(_x)\t\t(0x1310 + (_x))\n#define   RTL8367_DI_FORCE_MODE\t\t\tBIT(12)\n#define   RTL8367_DI_FORCE_NWAY\t\t\tBIT(7)\n#define   RTL8367_DI_FORCE_TXPAUSE\t\tBIT(6)\n#define   RTL8367_DI_FORCE_RXPAUSE\t\tBIT(5)\n#define   RTL8367_DI_FORCE_LINK\t\t\tBIT(4)\n#define   RTL8367_DI_FORCE_DUPLEX\t\tBIT(2)\n#define   RTL8367_DI_FORCE_SPEED_MASK\t\t3\n#define   RTL8367_DI_FORCE_SPEED_10\t\t0\n#define   RTL8367_DI_FORCE_SPEED_100\t\t1\n#define   RTL8367_DI_FORCE_SPEED_1000\t\t2\n\n#define RTL8367_MAC_FORCE_REG(_x)\t\t(0x1312 + (_x))\n\n#define RTL8367_CHIP_RESET_REG\t\t\t0x1322\n#define   RTL8367_CHIP_RESET_SW\t\t\tBIT(1)\n#define   RTL8367_CHIP_RESET_HW\t\t\tBIT(0)\n\n#define RTL8367_PORT_STATUS_REG(_p)\t\t(0x1352 + (_p))\n#define   RTL8367_PORT_STATUS_NWAY\t\tBIT(7)\n#define   RTL8367_PORT_STATUS_TXPAUSE\t\tBIT(6)\n#define   RTL8367_PORT_STATUS_RXPAUSE\t\tBIT(5)\n#define   RTL8367_PORT_STATUS_LINK\t\tBIT(4)\n#define   RTL8367_PORT_STATUS_DUPLEX\t\tBIT(2)\n#define   RTL8367_PORT_STATUS_SPEED_MASK\t0x0003\n#define   RTL8367_PORT_STATUS_SPEED_10\t\t0\n#define   RTL8367_PORT_STATUS_SPEED_100\t\t1\n#define   RTL8367_PORT_STATUS_SPEED_1000\t2\n\n#define RTL8367_RTL_NO_REG\t\t\t0x13c0\n#define   RTL8367_RTL_NO_8367R\t\t\t0x3670\n#define   RTL8367_RTL_NO_8367M\t\t\t0x3671\n\n#define RTL8367_RTL_VER_REG\t\t\t0x13c1\n#define   RTL8367_RTL_VER_MASK\t\t\t0xf\n\n#define RTL8367_RTL_MAGIC_ID_REG\t\t0x13c2\n#define   RTL8367_RTL_MAGIC_ID_VAL\t\t0x0249\n\n#define RTL8367_LED_SYS_CONFIG_REG\t\t0x1b00\n#define RTL8367_LED_MODE_REG\t\t\t0x1b02\n#define   RTL8367_LED_MODE_RATE_M\t\t0x7\n#define   RTL8367_LED_MODE_RATE_S\t\t1\n\n#define RTL8367_LED_CONFIG_REG\t\t\t0x1b03\n#define   RTL8367_LED_CONFIG_DATA_S\t\t12\n#define   RTL8367_LED_CONFIG_DATA_M\t\t0x3\n#define   RTL8367_LED_CONFIG_SEL\t\tBIT(14)\n#define   RTL8367_LED_CONFIG_LED_CFG_M\t\t0xf\n\n#define RTL8367_PARA_LED_IO_EN1_REG\t\t0x1b24\n#define RTL8367_PARA_LED_IO_EN2_REG\t\t0x1b25\n#define   RTL8367_PARA_LED_IO_EN_PMASK\t\t0xff\n\n#define RTL8367_IA_CTRL_REG\t\t\t0x1f00\n#define   RTL8367_IA_CTRL_RW(_x)\t\t((_x) << 1)\n#define   RTL8367_IA_CTRL_RW_READ\t\tRTL8367_IA_CTRL_RW(0)\n#define   RTL8367_IA_CTRL_RW_WRITE\t\tRTL8367_IA_CTRL_RW(1)\n#define   RTL8367_IA_CTRL_CMD_MASK\t\tBIT(0)\n\n#define RTL8367_IA_STATUS_REG\t\t\t0x1f01\n#define   RTL8367_IA_STATUS_PHY_BUSY\t\tBIT(2)\n#define   RTL8367_IA_STATUS_SDS_BUSY\t\tBIT(1)\n#define   RTL8367_IA_STATUS_MDX_BUSY\t\tBIT(0)\n\n#define RTL8367_IA_ADDRESS_REG\t\t\t0x1f02\n\n#define RTL8367_IA_WRITE_DATA_REG\t\t0x1f03\n#define RTL8367_IA_READ_DATA_REG\t\t0x1f04\n\n#define RTL8367_INTERNAL_PHY_REG(_a, _r)\t(0x2000 + 32 * (_a) + (_r))\n\n#define RTL8367_CPU_PORT_NUM\t\t9\n#define RTL8367_NUM_PORTS\t\t10\n#define RTL8367_NUM_VLANS\t\t32\n#define RTL8367_NUM_LEDGROUPS\t\t4\n#define RTL8367_NUM_VIDS\t\t4096\n#define RTL8367_PRIORITYMAX\t\t7\n#define RTL8367_FIDMAX\t\t\t7\n\n#define RTL8367_PORT_0\t\t\tBIT(0)\n#define RTL8367_PORT_1\t\t\tBIT(1)\n#define RTL8367_PORT_2\t\t\tBIT(2)\n#define RTL8367_PORT_3\t\t\tBIT(3)\n#define RTL8367_PORT_4\t\t\tBIT(4)\n#define RTL8367_PORT_5\t\t\tBIT(5)\n#define RTL8367_PORT_6\t\t\tBIT(6)\n#define RTL8367_PORT_7\t\t\tBIT(7)\n#define RTL8367_PORT_E1\t\t\tBIT(8)\t/* external port 1 */\n#define RTL8367_PORT_E0\t\t\tBIT(9)\t/* external port 0 */\n\n#define RTL8367_PORTS_ALL\t\t\t\t\t\\\n\t(RTL8367_PORT_0 | RTL8367_PORT_1 | RTL8367_PORT_2 |\t\\\n\t RTL8367_PORT_3 | RTL8367_PORT_4 | RTL8367_PORT_5 |\t\\\n\t RTL8367_PORT_6 | RTL8367_PORT_7 | RTL8367_PORT_E1 |\t\\\n\t RTL8367_PORT_E0)\n\n#define RTL8367_PORTS_ALL_BUT_CPU\t\t\t\t\\\n\t(RTL8367_PORT_0 | RTL8367_PORT_1 | RTL8367_PORT_2 |\t\\\n\t RTL8367_PORT_3 | RTL8367_PORT_4 | RTL8367_PORT_5 |\t\\\n\t RTL8367_PORT_6 | RTL8367_PORT_7 | RTL8367_PORT_E1)\n\nstruct rtl8367_initval {\n\tu16 reg;\n\tu16 val;\n};\n\n#define RTL8367_MIB_RXB_ID\t\t0\t/* IfInOctets */\n#define RTL8367_MIB_TXB_ID\t\t20\t/* IfOutOctets */\n\nstatic struct rtl8366_mib_counter rtl8367_mib_counters[] = {\n\t{ 0,  0, 4, \"IfInOctets\"\t\t\t\t},\n\t{ 0,  4, 2, \"Dot3StatsFCSErrors\"\t\t\t},\n\t{ 0,  6, 2, \"Dot3StatsSymbolErrors\"\t\t\t},\n\t{ 0,  8, 2, \"Dot3InPauseFrames\"\t\t\t\t},\n\t{ 0, 10, 2, \"Dot3ControlInUnknownOpcodes\"\t\t},\n\t{ 0, 12, 2, \"EtherStatsFragments\"\t\t\t},\n\t{ 0, 14, 2, \"EtherStatsJabbers\"\t\t\t\t},\n\t{ 0, 16, 2, \"IfInUcastPkts\"\t\t\t\t},\n\t{ 0, 18, 2, \"EtherStatsDropEvents\"\t\t\t},\n\t{ 0, 20, 4, \"EtherStatsOctets\"\t\t\t\t},\n\n\t{ 0, 24, 2, \"EtherStatsUnderSizePkts\"\t\t\t},\n\t{ 0, 26, 2, \"EtherOversizeStats\"\t\t\t},\n\t{ 0, 28, 2, \"EtherStatsPkts64Octets\"\t\t\t},\n\t{ 0, 30, 2, \"EtherStatsPkts65to127Octets\"\t\t},\n\t{ 0, 32, 2, \"EtherStatsPkts128to255Octets\"\t\t},\n\t{ 0, 34, 2, \"EtherStatsPkts256to511Octets\"\t\t},\n\t{ 0, 36, 2, \"EtherStatsPkts512to1023Octets\"\t\t},\n\t{ 0, 38, 2, \"EtherStatsPkts1024to1518Octets\"\t\t},\n\t{ 0, 40, 2, \"EtherStatsMulticastPkts\"\t\t\t},\n\t{ 0, 42, 2, \"EtherStatsBroadcastPkts\"\t\t\t},\n\n\t{ 0, 44, 4, \"IfOutOctets\"\t\t\t\t},\n\n\t{ 0, 48, 2, \"Dot3StatsSingleCollisionFrames\"\t\t},\n\t{ 0, 50, 2, \"Dot3StatMultipleCollisionFrames\"\t\t},\n\t{ 0, 52, 2, \"Dot3sDeferredTransmissions\"\t\t},\n\t{ 0, 54, 2, \"Dot3StatsLateCollisions\"\t\t\t},\n\t{ 0, 56, 2, \"EtherStatsCollisions\"\t\t\t},\n\t{ 0, 58, 2, \"Dot3StatsExcessiveCollisions\"\t\t},\n\t{ 0, 60, 2, \"Dot3OutPauseFrames\"\t\t\t},\n\t{ 0, 62, 2, \"Dot1dBasePortDelayExceededDiscards\"\t},\n\t{ 0, 64, 2, \"Dot1dTpPortInDiscards\"\t\t\t},\n\t{ 0, 66, 2, \"IfOutUcastPkts\"\t\t\t\t},\n\t{ 0, 68, 2, \"IfOutMulticastPkts\"\t\t\t},\n\t{ 0, 70, 2, \"IfOutBroadcastPkts\"\t\t\t},\n\t{ 0, 72, 2, \"OutOampduPkts\"\t\t\t\t},\n\t{ 0, 74, 2, \"InOampduPkts\"\t\t\t\t},\n\t{ 0, 76, 2, \"PktgenPkts\"\t\t\t\t},\n};\n\n#define REG_RD(_smi, _reg, _val)\t\t\t\t\t\\\n\tdo {\t\t\t\t\t\t\t\t\\\n\t\terr = rtl8366_smi_read_reg(_smi, _reg, _val);\t\t\\\n\t\tif (err)\t\t\t\t\t\t\\\n\t\t\treturn err;\t\t\t\t\t\\\n\t} while (0)\n\n#define REG_WR(_smi, _reg, _val)\t\t\t\t\t\\\n\tdo {\t\t\t\t\t\t\t\t\\\n\t\terr = rtl8366_smi_write_reg(_smi, _reg, _val);\t\t\\\n\t\tif (err)\t\t\t\t\t\t\\\n\t\t\treturn err;\t\t\t\t\t\\\n\t} while (0)\n\n#define REG_RMW(_smi, _reg, _mask, _val)\t\t\t\t\\\n\tdo {\t\t\t\t\t\t\t\t\\\n\t\terr = rtl8366_smi_rmwr(_smi, _reg, _mask, _val);\t\\\n\t\tif (err)\t\t\t\t\t\t\\\n\t\t\treturn err;\t\t\t\t\t\\\n\t} while (0)\n\nstatic const struct rtl8367_initval rtl8367_initvals_0_0[] = {\n\t{0x133f, 0x0030}, {0x133e, 0x000e}, {0x221f, 0x0000}, {0x2215, 0x1006},\n\t{0x221f, 0x0005}, {0x2200, 0x00c6}, {0x221f, 0x0007}, {0x221e, 0x0048},\n\t{0x2215, 0x6412}, {0x2216, 0x6412}, {0x2217, 0x6412}, {0x2218, 0x6412},\n\t{0x2219, 0x6412}, {0x221A, 0x6412}, {0x221f, 0x0001}, {0x220c, 0xdbf0},\n\t{0x2209, 0x2576}, {0x2207, 0x287E}, {0x220A, 0x68E5}, {0x221D, 0x3DA4},\n\t{0x221C, 0xE7F7}, {0x2214, 0x7F52}, {0x2218, 0x7FCE}, {0x2208, 0x04B7},\n\t{0x2206, 0x4072}, {0x2210, 0xF05E}, {0x221B, 0xB414}, {0x221F, 0x0003},\n\t{0x221A, 0x06A6}, {0x2210, 0xF05E}, {0x2213, 0x06EB}, {0x2212, 0xF4D2},\n\t{0x220E, 0xE120}, {0x2200, 0x7C00}, {0x2202, 0x5FD0}, {0x220D, 0x0207},\n\t{0x221f, 0x0002}, {0x2205, 0x0978}, {0x2202, 0x8C01}, {0x2207, 0x3620},\n\t{0x221C, 0x0001}, {0x2203, 0x0420}, {0x2204, 0x80C8}, {0x133e, 0x0ede},\n\t{0x221f, 0x0002}, {0x220c, 0x0073}, {0x220d, 0xEB65}, {0x220e, 0x51d1},\n\t{0x220f, 0x5dcb}, {0x2210, 0x3044}, {0x2211, 0x1800}, {0x2212, 0x7E00},\n\t{0x2213, 0x0000}, {0x133f, 0x0010}, {0x133e, 0x0ffe}, {0x207f, 0x0002},\n\t{0x2074, 0x3D22}, {0x2075, 0x2000}, {0x2076, 0x6040}, {0x2077, 0x0000},\n\t{0x2078, 0x0f0a}, {0x2079, 0x50AB}, {0x207a, 0x0000}, {0x207b, 0x0f0f},\n\t{0x205f, 0x0002}, {0x2054, 0xFF00}, {0x2055, 0x000A}, {0x2056, 0x000A},\n\t{0x2057, 0x0005}, {0x2058, 0x0005}, {0x2059, 0x0000}, {0x205A, 0x0005},\n\t{0x205B, 0x0005}, {0x205C, 0x0005}, {0x209f, 0x0002}, {0x2094, 0x00AA},\n\t{0x2095, 0x00AA}, {0x2096, 0x00AA}, {0x2097, 0x00AA}, {0x2098, 0x0055},\n\t{0x2099, 0x00AA}, {0x209A, 0x00AA}, {0x209B, 0x00AA}, {0x1363, 0x8354},\n\t{0x1270, 0x3333}, {0x1271, 0x3333}, {0x1272, 0x3333}, {0x1330, 0x00DB},\n\t{0x1203, 0xff00}, {0x1200, 0x7fc4}, {0x121d, 0x1006}, {0x121e, 0x03e8},\n\t{0x121f, 0x02b3}, {0x1220, 0x028f}, {0x1221, 0x029b}, {0x1222, 0x0277},\n\t{0x1223, 0x02b3}, {0x1224, 0x028f}, {0x1225, 0x029b}, {0x1226, 0x0277},\n\t{0x1227, 0x00c0}, {0x1228, 0x00b4}, {0x122f, 0x00c0}, {0x1230, 0x00b4},\n\t{0x1229, 0x0020}, {0x122a, 0x000c}, {0x1231, 0x0030}, {0x1232, 0x0024},\n\t{0x0219, 0x0032}, {0x0200, 0x03e8}, {0x0201, 0x03e8}, {0x0202, 0x03e8},\n\t{0x0203, 0x03e8}, {0x0204, 0x03e8}, {0x0205, 0x03e8}, {0x0206, 0x03e8},\n\t{0x0207, 0x03e8}, {0x0218, 0x0032}, {0x0208, 0x029b}, {0x0209, 0x029b},\n\t{0x020a, 0x029b}, {0x020b, 0x029b}, {0x020c, 0x029b}, {0x020d, 0x029b},\n\t{0x020e, 0x029b}, {0x020f, 0x029b}, {0x0210, 0x029b}, {0x0211, 0x029b},\n\t{0x0212, 0x029b}, {0x0213, 0x029b}, {0x0214, 0x029b}, {0x0215, 0x029b},\n\t{0x0216, 0x029b}, {0x0217, 0x029b}, {0x0900, 0x0000}, {0x0901, 0x0000},\n\t{0x0902, 0x0000}, {0x0903, 0x0000}, {0x0865, 0x3210}, {0x087b, 0x0000},\n\t{0x087c, 0xff00}, {0x087d, 0x0000}, {0x087e, 0x0000}, {0x0801, 0x0100},\n\t{0x0802, 0x0100}, {0x1700, 0x014C}, {0x0301, 0x00FF}, {0x12AA, 0x0096},\n\t{0x133f, 0x0030}, {0x133e, 0x000e}, {0x221f, 0x0005}, {0x2200, 0x00C4},\n\t{0x221f, 0x0000}, {0x2210, 0x05EF}, {0x2204, 0x05E1}, {0x2200, 0x1340},\n\t{0x133f, 0x0010}, {0x20A0, 0x1940}, {0x20C0, 0x1940}, {0x20E0, 0x1940},\n};\n\nstatic const struct rtl8367_initval rtl8367_initvals_0_1[] = {\n\t{0x133f, 0x0030}, {0x133e, 0x000e}, {0x221f, 0x0000}, {0x2215, 0x1006},\n\t{0x221f, 0x0005}, {0x2200, 0x00c6}, {0x221f, 0x0007}, {0x221e, 0x0048},\n\t{0x2215, 0x6412}, {0x2216, 0x6412}, {0x2217, 0x6412}, {0x2218, 0x6412},\n\t{0x2219, 0x6412}, {0x221A, 0x6412}, {0x221f, 0x0001}, {0x220c, 0xdbf0},\n\t{0x2209, 0x2576}, {0x2207, 0x287E}, {0x220A, 0x68E5}, {0x221D, 0x3DA4},\n\t{0x221C, 0xE7F7}, {0x2214, 0x7F52}, {0x2218, 0x7FCE}, {0x2208, 0x04B7},\n\t{0x2206, 0x4072}, {0x2210, 0xF05E}, {0x221B, 0xB414}, {0x221F, 0x0003},\n\t{0x221A, 0x06A6}, {0x2210, 0xF05E}, {0x2213, 0x06EB}, {0x2212, 0xF4D2},\n\t{0x220E, 0xE120}, {0x2200, 0x7C00}, {0x2202, 0x5FD0}, {0x220D, 0x0207},\n\t{0x221f, 0x0002}, {0x2205, 0x0978}, {0x2202, 0x8C01}, {0x2207, 0x3620},\n\t{0x221C, 0x0001}, {0x2203, 0x0420}, {0x2204, 0x80C8}, {0x133e, 0x0ede},\n\t{0x221f, 0x0002}, {0x220c, 0x0073}, {0x220d, 0xEB65}, {0x220e, 0x51d1},\n\t{0x220f, 0x5dcb}, {0x2210, 0x3044}, {0x2211, 0x1800}, {0x2212, 0x7E00},\n\t{0x2213, 0x0000}, {0x133f, 0x0010}, {0x133e, 0x0ffe}, {0x207f, 0x0002},\n\t{0x2074, 0x3D22}, {0x2075, 0x2000}, {0x2076, 0x6040}, {0x2077, 0x0000},\n\t{0x2078, 0x0f0a}, {0x2079, 0x50AB}, {0x207a, 0x0000}, {0x207b, 0x0f0f},\n\t{0x205f, 0x0002}, {0x2054, 0xFF00}, {0x2055, 0x000A}, {0x2056, 0x000A},\n\t{0x2057, 0x0005}, {0x2058, 0x0005}, {0x2059, 0x0000}, {0x205A, 0x0005},\n\t{0x205B, 0x0005}, {0x205C, 0x0005}, {0x209f, 0x0002}, {0x2094, 0x00AA},\n\t{0x2095, 0x00AA}, {0x2096, 0x00AA}, {0x2097, 0x00AA}, {0x2098, 0x0055},\n\t{0x2099, 0x00AA}, {0x209A, 0x00AA}, {0x209B, 0x00AA}, {0x1363, 0x8354},\n\t{0x1270, 0x3333}, {0x1271, 0x3333}, {0x1272, 0x3333}, {0x1330, 0x00DB},\n\t{0x1203, 0xff00}, {0x1200, 0x7fc4}, {0x121d, 0x1b06}, {0x121e, 0x07f0},\n\t{0x121f, 0x0438}, {0x1220, 0x040f}, {0x1221, 0x040f}, {0x1222, 0x03eb},\n\t{0x1223, 0x0438}, {0x1224, 0x040f}, {0x1225, 0x040f}, {0x1226, 0x03eb},\n\t{0x1227, 0x0144}, {0x1228, 0x0138}, {0x122f, 0x0144}, {0x1230, 0x0138},\n\t{0x1229, 0x0020}, {0x122a, 0x000c}, {0x1231, 0x0030}, {0x1232, 0x0024},\n\t{0x0219, 0x0032}, {0x0200, 0x07d0}, {0x0201, 0x07d0}, {0x0202, 0x07d0},\n\t{0x0203, 0x07d0}, {0x0204, 0x07d0}, {0x0205, 0x07d0}, {0x0206, 0x07d0},\n\t{0x0207, 0x07d0}, {0x0218, 0x0032}, {0x0208, 0x0190}, {0x0209, 0x0190},\n\t{0x020a, 0x0190}, {0x020b, 0x0190}, {0x020c, 0x0190}, {0x020d, 0x0190},\n\t{0x020e, 0x0190}, {0x020f, 0x0190}, {0x0210, 0x0190}, {0x0211, 0x0190},\n\t{0x0212, 0x0190}, {0x0213, 0x0190}, {0x0214, 0x0190}, {0x0215, 0x0190},\n\t{0x0216, 0x0190}, {0x0217, 0x0190}, {0x0900, 0x0000}, {0x0901, 0x0000},\n\t{0x0902, 0x0000}, {0x0903, 0x0000}, {0x0865, 0x3210}, {0x087b, 0x0000},\n\t{0x087c, 0xff00}, {0x087d, 0x0000}, {0x087e, 0x0000}, {0x0801, 0x0100},\n\t{0x0802, 0x0100}, {0x1700, 0x0125}, {0x0301, 0x00FF}, {0x12AA, 0x0096},\n\t{0x133f, 0x0030}, {0x133e, 0x000e}, {0x221f, 0x0005}, {0x2200, 0x00C4},\n\t{0x221f, 0x0000}, {0x2210, 0x05EF}, {0x2204, 0x05E1}, {0x2200, 0x1340},\n\t{0x133f, 0x0010},\n};\n\nstatic const struct rtl8367_initval rtl8367_initvals_1_0[] = {\n\t{0x1B24, 0x0000}, {0x1B25, 0x0000}, {0x1B26, 0x0000}, {0x1B27, 0x0000},\n\t{0x207F, 0x0002}, {0x2079, 0x0200}, {0x207F, 0x0000}, {0x133F, 0x0030},\n\t{0x133E, 0x000E}, {0x221F, 0x0005}, {0x2201, 0x0700}, {0x2205, 0x8B82},\n\t{0x2206, 0x05CB}, {0x221F, 0x0002}, {0x2204, 0x80C2}, {0x2205, 0x0938},\n\t{0x221F, 0x0003}, {0x2212, 0xC4D2}, {0x220D, 0x0207}, {0x221F, 0x0001},\n\t{0x2207, 0x267E}, {0x221C, 0xE5F7}, {0x221B, 0x0424}, {0x221F, 0x0007},\n\t{0x221E, 0x0040}, {0x2218, 0x0000}, {0x221F, 0x0007}, {0x221E, 0x002C},\n\t{0x2218, 0x008B}, {0x221F, 0x0005}, {0x2205, 0xFFF6}, {0x2206, 0x0080},\n\t{0x2205, 0x8000}, {0x2206, 0xF8E0}, {0x2206, 0xE000}, {0x2206, 0xE1E0},\n\t{0x2206, 0x01AC}, {0x2206, 0x2408}, {0x2206, 0xE08B}, {0x2206, 0x84F7},\n\t{0x2206, 0x20E4}, {0x2206, 0x8B84}, {0x2206, 0xFC05}, {0x2206, 0xF8FA},\n\t{0x2206, 0xEF69}, {0x2206, 0xE08B}, {0x2206, 0x86AC}, {0x2206, 0x201A},\n\t{0x2206, 0xBF80}, {0x2206, 0x59D0}, {0x2206, 0x2402}, {0x2206, 0x803D},\n\t{0x2206, 0xE0E0}, {0x2206, 0xE4E1}, {0x2206, 0xE0E5}, {0x2206, 0x5806},\n\t{0x2206, 0x68C0}, {0x2206, 0xD1D2}, {0x2206, 0xE4E0}, {0x2206, 0xE4E5},\n\t{0x2206, 0xE0E5}, {0x2206, 0xEF96}, {0x2206, 0xFEFC}, {0x2206, 0x05FB},\n\t{0x2206, 0x0BFB}, {0x2206, 0x58FF}, {0x2206, 0x9E11}, {0x2206, 0x06F0},\n\t{0x2206, 0x0C81}, {0x2206, 0x8AE0}, {0x2206, 0x0019}, {0x2206, 0x1B89},\n\t{0x2206, 0xCFEB}, {0x2206, 0x19EB}, {0x2206, 0x19B0}, {0x2206, 0xEFFF},\n\t{0x2206, 0x0BFF}, {0x2206, 0x0425}, {0x2206, 0x0807}, {0x2206, 0x2640},\n\t{0x2206, 0x7227}, {0x2206, 0x267E}, {0x2206, 0x2804}, {0x2206, 0xB729},\n\t{0x2206, 0x2576}, {0x2206, 0x2A68}, {0x2206, 0xE52B}, {0x2206, 0xAD00},\n\t{0x2206, 0x2CDB}, {0x2206, 0xF02D}, {0x2206, 0x67BB}, {0x2206, 0x2E7B},\n\t{0x2206, 0x0F2F}, {0x2206, 0x7365}, {0x2206, 0x31AC}, {0x2206, 0xCC32},\n\t{0x2206, 0x2300}, {0x2206, 0x332D}, {0x2206, 0x1734}, {0x2206, 0x7F52},\n\t{0x2206, 0x3510}, {0x2206, 0x0036}, {0x2206, 0x0600}, {0x2206, 0x370C},\n\t{0x2206, 0xC038}, {0x2206, 0x7FCE}, {0x2206, 0x3CE5}, {0x2206, 0xF73D},\n\t{0x2206, 0x3DA4}, {0x2206, 0x6530}, {0x2206, 0x3E67}, {0x2206, 0x0053},\n\t{0x2206, 0x69D2}, {0x2206, 0x0F6A}, {0x2206, 0x012C}, {0x2206, 0x6C2B},\n\t{0x2206, 0x136E}, {0x2206, 0xE100}, {0x2206, 0x6F12}, {0x2206, 0xF771},\n\t{0x2206, 0x006B}, {0x2206, 0x7306}, {0x2206, 0xEB74}, {0x2206, 0x94C7},\n\t{0x2206, 0x7698}, {0x2206, 0x0A77}, {0x2206, 0x5000}, {0x2206, 0x788A},\n\t{0x2206, 0x1579}, {0x2206, 0x7F6F}, {0x2206, 0x7A06}, {0x2206, 0xA600},\n\t{0x2205, 0x8B90}, {0x2206, 0x8000}, {0x2205, 0x8B92}, {0x2206, 0x8000},\n\t{0x2205, 0x8B94}, {0x2206, 0x8014}, {0x2208, 0xFFFA}, {0x2202, 0x3C65},\n\t{0x2205, 0xFFF6}, {0x2206, 0x00F7}, {0x221F, 0x0000}, {0x221F, 0x0007},\n\t{0x221E, 0x0042}, {0x2218, 0x0000}, {0x221E, 0x002D}, {0x2218, 0xF010},\n\t{0x221E, 0x0020}, {0x2215, 0x0000}, {0x221E, 0x0023}, {0x2216, 0x8000},\n\t{0x221F, 0x0000}, {0x133F, 0x0010}, {0x133E, 0x0FFE}, {0x1362, 0x0115},\n\t{0x1363, 0x0002}, {0x1363, 0x0000}, {0x1306, 0x000C}, {0x1307, 0x000C},\n\t{0x1303, 0x0067}, {0x1304, 0x4444}, {0x1203, 0xFF00}, {0x1200, 0x7FC4},\n\t{0x121D, 0x7D16}, {0x121E, 0x03E8}, {0x121F, 0x024E}, {0x1220, 0x0230},\n\t{0x1221, 0x0244}, {0x1222, 0x0226}, {0x1223, 0x024E}, {0x1224, 0x0230},\n\t{0x1225, 0x0244}, {0x1226, 0x0226}, {0x1227, 0x00C0}, {0x1228, 0x00B4},\n\t{0x122F, 0x00C0}, {0x1230, 0x00B4}, {0x0208, 0x03E8}, {0x0209, 0x03E8},\n\t{0x020A, 0x03E8}, {0x020B, 0x03E8}, {0x020C, 0x03E8}, {0x020D, 0x03E8},\n\t{0x020E, 0x03E8}, {0x020F, 0x03E8}, {0x0210, 0x03E8}, {0x0211, 0x03E8},\n\t{0x0212, 0x03E8}, {0x0213, 0x03E8}, {0x0214, 0x03E8}, {0x0215, 0x03E8},\n\t{0x0216, 0x03E8}, {0x0217, 0x03E8}, {0x0900, 0x0000}, {0x0901, 0x0000},\n\t{0x0902, 0x0000}, {0x0903, 0x0000}, {0x0865, 0x3210}, {0x087B, 0x0000},\n\t{0x087C, 0xFF00}, {0x087D, 0x0000}, {0x087E, 0x0000}, {0x0801, 0x0100},\n\t{0x0802, 0x0100}, {0x0A20, 0x2040}, {0x0A21, 0x2040}, {0x0A22, 0x2040},\n\t{0x0A23, 0x2040}, {0x0A24, 0x2040}, {0x0A28, 0x2040}, {0x0A29, 0x2040},\n\t{0x133F, 0x0030}, {0x133E, 0x000E}, {0x221F, 0x0000}, {0x2200, 0x1340},\n\t{0x221F, 0x0000}, {0x133F, 0x0010}, {0x133E, 0x0FFE}, {0x20A0, 0x1940},\n\t{0x20C0, 0x1940}, {0x20E0, 0x1940}, {0x130c, 0x0050},\n};\n\nstatic const struct rtl8367_initval rtl8367_initvals_1_1[] = {\n\t{0x1B24, 0x0000}, {0x1B25, 0x0000}, {0x1B26, 0x0000}, {0x1B27, 0x0000},\n\t{0x207F, 0x0002}, {0x2079, 0x0200}, {0x207F, 0x0000}, {0x133F, 0x0030},\n\t{0x133E, 0x000E}, {0x221F, 0x0005}, {0x2201, 0x0700}, {0x2205, 0x8B82},\n\t{0x2206, 0x05CB}, {0x221F, 0x0002}, {0x2204, 0x80C2}, {0x2205, 0x0938},\n\t{0x221F, 0x0003}, {0x2212, 0xC4D2}, {0x220D, 0x0207}, {0x221F, 0x0001},\n\t{0x2207, 0x267E}, {0x221C, 0xE5F7}, {0x221B, 0x0424}, {0x221F, 0x0007},\n\t{0x221E, 0x0040}, {0x2218, 0x0000}, {0x221F, 0x0007}, {0x221E, 0x002C},\n\t{0x2218, 0x008B}, {0x221F, 0x0005}, {0x2205, 0xFFF6}, {0x2206, 0x0080},\n\t{0x2205, 0x8000}, {0x2206, 0xF8E0}, {0x2206, 0xE000}, {0x2206, 0xE1E0},\n\t{0x2206, 0x01AC}, {0x2206, 0x2408}, {0x2206, 0xE08B}, {0x2206, 0x84F7},\n\t{0x2206, 0x20E4}, {0x2206, 0x8B84}, {0x2206, 0xFC05}, {0x2206, 0xF8FA},\n\t{0x2206, 0xEF69}, {0x2206, 0xE08B}, {0x2206, 0x86AC}, {0x2206, 0x201A},\n\t{0x2206, 0xBF80}, {0x2206, 0x59D0}, {0x2206, 0x2402}, {0x2206, 0x803D},\n\t{0x2206, 0xE0E0}, {0x2206, 0xE4E1}, {0x2206, 0xE0E5}, {0x2206, 0x5806},\n\t{0x2206, 0x68C0}, {0x2206, 0xD1D2}, {0x2206, 0xE4E0}, {0x2206, 0xE4E5},\n\t{0x2206, 0xE0E5}, {0x2206, 0xEF96}, {0x2206, 0xFEFC}, {0x2206, 0x05FB},\n\t{0x2206, 0x0BFB}, {0x2206, 0x58FF}, {0x2206, 0x9E11}, {0x2206, 0x06F0},\n\t{0x2206, 0x0C81}, {0x2206, 0x8AE0}, {0x2206, 0x0019}, {0x2206, 0x1B89},\n\t{0x2206, 0xCFEB}, {0x2206, 0x19EB}, {0x2206, 0x19B0}, {0x2206, 0xEFFF},\n\t{0x2206, 0x0BFF}, {0x2206, 0x0425}, {0x2206, 0x0807}, {0x2206, 0x2640},\n\t{0x2206, 0x7227}, {0x2206, 0x267E}, {0x2206, 0x2804}, {0x2206, 0xB729},\n\t{0x2206, 0x2576}, {0x2206, 0x2A68}, {0x2206, 0xE52B}, {0x2206, 0xAD00},\n\t{0x2206, 0x2CDB}, {0x2206, 0xF02D}, {0x2206, 0x67BB}, {0x2206, 0x2E7B},\n\t{0x2206, 0x0F2F}, {0x2206, 0x7365}, {0x2206, 0x31AC}, {0x2206, 0xCC32},\n\t{0x2206, 0x2300}, {0x2206, 0x332D}, {0x2206, 0x1734}, {0x2206, 0x7F52},\n\t{0x2206, 0x3510}, {0x2206, 0x0036}, {0x2206, 0x0600}, {0x2206, 0x370C},\n\t{0x2206, 0xC038}, {0x2206, 0x7FCE}, {0x2206, 0x3CE5}, {0x2206, 0xF73D},\n\t{0x2206, 0x3DA4}, {0x2206, 0x6530}, {0x2206, 0x3E67}, {0x2206, 0x0053},\n\t{0x2206, 0x69D2}, {0x2206, 0x0F6A}, {0x2206, 0x012C}, {0x2206, 0x6C2B},\n\t{0x2206, 0x136E}, {0x2206, 0xE100}, {0x2206, 0x6F12}, {0x2206, 0xF771},\n\t{0x2206, 0x006B}, {0x2206, 0x7306}, {0x2206, 0xEB74}, {0x2206, 0x94C7},\n\t{0x2206, 0x7698}, {0x2206, 0x0A77}, {0x2206, 0x5000}, {0x2206, 0x788A},\n\t{0x2206, 0x1579}, {0x2206, 0x7F6F}, {0x2206, 0x7A06}, {0x2206, 0xA600},\n\t{0x2205, 0x8B90}, {0x2206, 0x8000}, {0x2205, 0x8B92}, {0x2206, 0x8000},\n\t{0x2205, 0x8B94}, {0x2206, 0x8014}, {0x2208, 0xFFFA}, {0x2202, 0x3C65},\n\t{0x2205, 0xFFF6}, {0x2206, 0x00F7}, {0x221F, 0x0000}, {0x221F, 0x0007},\n\t{0x221E, 0x0042}, {0x2218, 0x0000}, {0x221E, 0x002D}, {0x2218, 0xF010},\n\t{0x221E, 0x0020}, {0x2215, 0x0000}, {0x221E, 0x0023}, {0x2216, 0x8000},\n\t{0x221F, 0x0000}, {0x133F, 0x0010}, {0x133E, 0x0FFE}, {0x1362, 0x0115},\n\t{0x1363, 0x0002}, {0x1363, 0x0000}, {0x1306, 0x000C}, {0x1307, 0x000C},\n\t{0x1303, 0x0067}, {0x1304, 0x4444}, {0x1203, 0xFF00}, {0x1200, 0x7FC4},\n\t{0x0900, 0x0000}, {0x0901, 0x0000}, {0x0902, 0x0000}, {0x0903, 0x0000},\n\t{0x0865, 0x3210}, {0x087B, 0x0000}, {0x087C, 0xFF00}, {0x087D, 0x0000},\n\t{0x087E, 0x0000}, {0x0801, 0x0100}, {0x0802, 0x0100}, {0x0A20, 0x2040},\n\t{0x0A21, 0x2040}, {0x0A22, 0x2040}, {0x0A23, 0x2040}, {0x0A24, 0x2040},\n\t{0x0A25, 0x2040}, {0x0A26, 0x2040}, {0x0A27, 0x2040}, {0x0A28, 0x2040},\n\t{0x0A29, 0x2040}, {0x133F, 0x0030}, {0x133E, 0x000E}, {0x221F, 0x0000},\n\t{0x2200, 0x1340}, {0x221F, 0x0000}, {0x133F, 0x0010}, {0x133E, 0x0FFE},\n\t{0x1B03, 0x0876},\n};\n\nstatic const struct rtl8367_initval rtl8367_initvals_2_0[] = {\n\t{0x1b24, 0x0000}, {0x1b25, 0x0000}, {0x1b26, 0x0000}, {0x1b27, 0x0000},\n\t{0x133f, 0x0030}, {0x133e, 0x000e}, {0x221f, 0x0007}, {0x221e, 0x0048},\n\t{0x2219, 0x4012}, {0x221f, 0x0003}, {0x2201, 0x3554}, {0x2202, 0x63e8},\n\t{0x2203, 0x99c2}, {0x2204, 0x0113}, {0x2205, 0x303e}, {0x220d, 0x0207},\n\t{0x220e, 0xe100}, {0x221f, 0x0007}, {0x221e, 0x0040}, {0x2218, 0x0000},\n\t{0x221f, 0x0007}, {0x221e, 0x002c}, {0x2218, 0x008b}, {0x221f, 0x0005},\n\t{0x2205, 0xfff6}, {0x2206, 0x0080}, {0x221f, 0x0005}, {0x2205, 0x8000},\n\t{0x2206, 0x0280}, {0x2206, 0x2bf7}, {0x2206, 0x00e0}, {0x2206, 0xfff7},\n\t{0x2206, 0xa080}, {0x2206, 0x02ae}, {0x2206, 0xf602}, {0x2206, 0x804e},\n\t{0x2206, 0x0201}, {0x2206, 0x5002}, {0x2206, 0x0163}, {0x2206, 0x0201},\n\t{0x2206, 0x79e0}, {0x2206, 0x8b8c}, {0x2206, 0xe18b}, {0x2206, 0x8d1e},\n\t{0x2206, 0x01e1}, {0x2206, 0x8b8e}, {0x2206, 0x1e01}, {0x2206, 0xa000},\n\t{0x2206, 0xe4ae}, {0x2206, 0xd8bf}, {0x2206, 0x8b88}, {0x2206, 0xec00},\n\t{0x2206, 0x19a9}, {0x2206, 0x8b90}, {0x2206, 0xf9ee}, {0x2206, 0xfff6},\n\t{0x2206, 0x00ee}, {0x2206, 0xfff7}, {0x2206, 0xfce0}, {0x2206, 0xe140},\n\t{0x2206, 0xe1e1}, {0x2206, 0x41f7}, {0x2206, 0x2ff6}, {0x2206, 0x28e4},\n\t{0x2206, 0xe140}, {0x2206, 0xe5e1}, {0x2206, 0x4104}, {0x2206, 0xf8fa},\n\t{0x2206, 0xef69}, {0x2206, 0xe08b}, {0x2206, 0x86ac}, {0x2206, 0x201a},\n\t{0x2206, 0xbf80}, {0x2206, 0x77d0}, {0x2206, 0x6c02}, {0x2206, 0x2978},\n\t{0x2206, 0xe0e0}, {0x2206, 0xe4e1}, {0x2206, 0xe0e5}, {0x2206, 0x5806},\n\t{0x2206, 0x68c0}, {0x2206, 0xd1d2}, {0x2206, 0xe4e0}, {0x2206, 0xe4e5},\n\t{0x2206, 0xe0e5}, {0x2206, 0xef96}, {0x2206, 0xfefc}, {0x2206, 0x0425},\n\t{0x2206, 0x0807}, {0x2206, 0x2640}, {0x2206, 0x7227}, {0x2206, 0x267e},\n\t{0x2206, 0x2804}, {0x2206, 0xb729}, {0x2206, 0x2576}, {0x2206, 0x2a68},\n\t{0x2206, 0xe52b}, {0x2206, 0xad00}, {0x2206, 0x2cdb}, {0x2206, 0xf02d},\n\t{0x2206, 0x67bb}, {0x2206, 0x2e7b}, {0x2206, 0x0f2f}, {0x2206, 0x7365},\n\t{0x2206, 0x31ac}, {0x2206, 0xcc32}, {0x2206, 0x2300}, {0x2206, 0x332d},\n\t{0x2206, 0x1734}, {0x2206, 0x7f52}, {0x2206, 0x3510}, {0x2206, 0x0036},\n\t{0x2206, 0x0600}, {0x2206, 0x370c}, {0x2206, 0xc038}, {0x2206, 0x7fce},\n\t{0x2206, 0x3ce5}, {0x2206, 0xf73d}, {0x2206, 0x3da4}, {0x2206, 0x6530},\n\t{0x2206, 0x3e67}, {0x2206, 0x0053}, {0x2206, 0x69d2}, {0x2206, 0x0f6a},\n\t{0x2206, 0x012c}, {0x2206, 0x6c2b}, {0x2206, 0x136e}, {0x2206, 0xe100},\n\t{0x2206, 0x6f12}, {0x2206, 0xf771}, {0x2206, 0x006b}, {0x2206, 0x7306},\n\t{0x2206, 0xeb74}, {0x2206, 0x94c7}, {0x2206, 0x7698}, {0x2206, 0x0a77},\n\t{0x2206, 0x5000}, {0x2206, 0x788a}, {0x2206, 0x1579}, {0x2206, 0x7f6f},\n\t{0x2206, 0x7a06}, {0x2206, 0xa600}, {0x2201, 0x0701}, {0x2200, 0x0405},\n\t{0x221f, 0x0000}, {0x2200, 0x1340}, {0x221f, 0x0000}, {0x133f, 0x0010},\n\t{0x133e, 0x0ffe}, {0x1203, 0xff00}, {0x1200, 0x7fc4}, {0x121d, 0x7D16},\n\t{0x121e, 0x03e8}, {0x121f, 0x024e}, {0x1220, 0x0230}, {0x1221, 0x0244},\n\t{0x1222, 0x0226}, {0x1223, 0x024e}, {0x1224, 0x0230}, {0x1225, 0x0244},\n\t{0x1226, 0x0226}, {0x1227, 0x00c0}, {0x1228, 0x00b4}, {0x122f, 0x00c0},\n\t{0x1230, 0x00b4}, {0x0208, 0x03e8}, {0x0209, 0x03e8}, {0x020a, 0x03e8},\n\t{0x020b, 0x03e8}, {0x020c, 0x03e8}, {0x020d, 0x03e8}, {0x020e, 0x03e8},\n\t{0x020f, 0x03e8}, {0x0210, 0x03e8}, {0x0211, 0x03e8}, {0x0212, 0x03e8},\n\t{0x0213, 0x03e8}, {0x0214, 0x03e8}, {0x0215, 0x03e8}, {0x0216, 0x03e8},\n\t{0x0217, 0x03e8}, {0x0900, 0x0000}, {0x0901, 0x0000}, {0x0902, 0x0000},\n\t{0x0903, 0x0000}, {0x0865, 0x3210}, {0x087b, 0x0000}, {0x087c, 0xff00},\n\t{0x087d, 0x0000}, {0x087e, 0x0000}, {0x0801, 0x0100}, {0x0802, 0x0100},\n\t{0x0A20, 0x2040}, {0x0A21, 0x2040}, {0x0A22, 0x2040}, {0x0A23, 0x2040},\n\t{0x0A24, 0x2040}, {0x0A28, 0x2040}, {0x0A29, 0x2040}, {0x20A0, 0x1940},\n\t{0x20C0, 0x1940}, {0x20E0, 0x1940}, {0x130c, 0x0050},\n};\n\nstatic const struct rtl8367_initval rtl8367_initvals_2_1[] = {\n\t{0x1b24, 0x0000}, {0x1b25, 0x0000}, {0x1b26, 0x0000}, {0x1b27, 0x0000},\n\t{0x133f, 0x0030}, {0x133e, 0x000e}, {0x221f, 0x0007}, {0x221e, 0x0048},\n\t{0x2219, 0x4012}, {0x221f, 0x0003}, {0x2201, 0x3554}, {0x2202, 0x63e8},\n\t{0x2203, 0x99c2}, {0x2204, 0x0113}, {0x2205, 0x303e}, {0x220d, 0x0207},\n\t{0x220e, 0xe100}, {0x221f, 0x0007}, {0x221e, 0x0040}, {0x2218, 0x0000},\n\t{0x221f, 0x0007}, {0x221e, 0x002c}, {0x2218, 0x008b}, {0x221f, 0x0005},\n\t{0x2205, 0xfff6}, {0x2206, 0x0080}, {0x221f, 0x0005}, {0x2205, 0x8000},\n\t{0x2206, 0x0280}, {0x2206, 0x2bf7}, {0x2206, 0x00e0}, {0x2206, 0xfff7},\n\t{0x2206, 0xa080}, {0x2206, 0x02ae}, {0x2206, 0xf602}, {0x2206, 0x804e},\n\t{0x2206, 0x0201}, {0x2206, 0x5002}, {0x2206, 0x0163}, {0x2206, 0x0201},\n\t{0x2206, 0x79e0}, {0x2206, 0x8b8c}, {0x2206, 0xe18b}, {0x2206, 0x8d1e},\n\t{0x2206, 0x01e1}, {0x2206, 0x8b8e}, {0x2206, 0x1e01}, {0x2206, 0xa000},\n\t{0x2206, 0xe4ae}, {0x2206, 0xd8bf}, {0x2206, 0x8b88}, {0x2206, 0xec00},\n\t{0x2206, 0x19a9}, {0x2206, 0x8b90}, {0x2206, 0xf9ee}, {0x2206, 0xfff6},\n\t{0x2206, 0x00ee}, {0x2206, 0xfff7}, {0x2206, 0xfce0}, {0x2206, 0xe140},\n\t{0x2206, 0xe1e1}, {0x2206, 0x41f7}, {0x2206, 0x2ff6}, {0x2206, 0x28e4},\n\t{0x2206, 0xe140}, {0x2206, 0xe5e1}, {0x2206, 0x4104}, {0x2206, 0xf8fa},\n\t{0x2206, 0xef69}, {0x2206, 0xe08b}, {0x2206, 0x86ac}, {0x2206, 0x201a},\n\t{0x2206, 0xbf80}, {0x2206, 0x77d0}, {0x2206, 0x6c02}, {0x2206, 0x2978},\n\t{0x2206, 0xe0e0}, {0x2206, 0xe4e1}, {0x2206, 0xe0e5}, {0x2206, 0x5806},\n\t{0x2206, 0x68c0}, {0x2206, 0xd1d2}, {0x2206, 0xe4e0}, {0x2206, 0xe4e5},\n\t{0x2206, 0xe0e5}, {0x2206, 0xef96}, {0x2206, 0xfefc}, {0x2206, 0x0425},\n\t{0x2206, 0x0807}, {0x2206, 0x2640}, {0x2206, 0x7227}, {0x2206, 0x267e},\n\t{0x2206, 0x2804}, {0x2206, 0xb729}, {0x2206, 0x2576}, {0x2206, 0x2a68},\n\t{0x2206, 0xe52b}, {0x2206, 0xad00}, {0x2206, 0x2cdb}, {0x2206, 0xf02d},\n\t{0x2206, 0x67bb}, {0x2206, 0x2e7b}, {0x2206, 0x0f2f}, {0x2206, 0x7365},\n\t{0x2206, 0x31ac}, {0x2206, 0xcc32}, {0x2206, 0x2300}, {0x2206, 0x332d},\n\t{0x2206, 0x1734}, {0x2206, 0x7f52}, {0x2206, 0x3510}, {0x2206, 0x0036},\n\t{0x2206, 0x0600}, {0x2206, 0x370c}, {0x2206, 0xc038}, {0x2206, 0x7fce},\n\t{0x2206, 0x3ce5}, {0x2206, 0xf73d}, {0x2206, 0x3da4}, {0x2206, 0x6530},\n\t{0x2206, 0x3e67}, {0x2206, 0x0053}, {0x2206, 0x69d2}, {0x2206, 0x0f6a},\n\t{0x2206, 0x012c}, {0x2206, 0x6c2b}, {0x2206, 0x136e}, {0x2206, 0xe100},\n\t{0x2206, 0x6f12}, {0x2206, 0xf771}, {0x2206, 0x006b}, {0x2206, 0x7306},\n\t{0x2206, 0xeb74}, {0x2206, 0x94c7}, {0x2206, 0x7698}, {0x2206, 0x0a77},\n\t{0x2206, 0x5000}, {0x2206, 0x788a}, {0x2206, 0x1579}, {0x2206, 0x7f6f},\n\t{0x2206, 0x7a06}, {0x2206, 0xa600}, {0x2201, 0x0701}, {0x2200, 0x0405},\n\t{0x221f, 0x0000}, {0x2200, 0x1340}, {0x221f, 0x0000}, {0x133f, 0x0010},\n\t{0x133e, 0x0ffe}, {0x1203, 0xff00}, {0x1200, 0x7fc4}, {0x0900, 0x0000},\n\t{0x0901, 0x0000}, {0x0902, 0x0000}, {0x0903, 0x0000}, {0x0865, 0x3210},\n\t{0x087b, 0x0000}, {0x087c, 0xff00}, {0x087d, 0x0000}, {0x087e, 0x0000},\n\t{0x0801, 0x0100}, {0x0802, 0x0100}, {0x0A20, 0x2040}, {0x0A21, 0x2040},\n\t{0x0A22, 0x2040}, {0x0A23, 0x2040}, {0x0A24, 0x2040}, {0x0A25, 0x2040},\n\t{0x0A26, 0x2040}, {0x0A27, 0x2040}, {0x0A28, 0x2040}, {0x0A29, 0x2040},\n\t{0x130c, 0x0050},\n};\n\nstatic int rtl8367_write_initvals(struct rtl8366_smi *smi,\n\t\t\t\t  const struct rtl8367_initval *initvals,\n\t\t\t\t  int count)\n{\n\tint err;\n\tint i;\n\n\tfor (i = 0; i < count; i++)\n\t\tREG_WR(smi, initvals[i].reg, initvals[i].val);\n\n\treturn 0;\n}\n\nstatic int rtl8367_read_phy_reg(struct rtl8366_smi *smi,\n\t\t\t\tu32 phy_addr, u32 phy_reg, u32 *val)\n{\n\tint timeout;\n\tu32 data;\n\tint err;\n\n\tif (phy_addr > RTL8367_PHY_ADDR_MAX)\n\t\treturn -EINVAL;\n\n\tif (phy_reg > RTL8367_PHY_REG_MAX)\n\t\treturn -EINVAL;\n\n\tREG_RD(smi, RTL8367_IA_STATUS_REG, &data);\n\tif (data & RTL8367_IA_STATUS_PHY_BUSY)\n\t\treturn -ETIMEDOUT;\n\n\t/* prepare address */\n\tREG_WR(smi, RTL8367_IA_ADDRESS_REG,\n\t       RTL8367_INTERNAL_PHY_REG(phy_addr, phy_reg));\n\n\t/* send read command */\n\tREG_WR(smi, RTL8367_IA_CTRL_REG,\n\t       RTL8367_IA_CTRL_CMD_MASK | RTL8367_IA_CTRL_RW_READ);\n\n\ttimeout = 5;\n\tdo {\n\t\tREG_RD(smi, RTL8367_IA_STATUS_REG, &data);\n\t\tif ((data & RTL8367_IA_STATUS_PHY_BUSY) == 0)\n\t\t\tbreak;\n\n\t\tif (timeout--) {\n\t\t\tdev_err(smi->parent, \"phy read timed out\\n\");\n\t\t\treturn -ETIMEDOUT;\n\t\t}\n\n\t\tudelay(1);\n\t} while (1);\n\n\t/* read data */\n\tREG_RD(smi, RTL8367_IA_READ_DATA_REG, val);\n\n\tdev_dbg(smi->parent, \"phy_read: addr:%02x, reg:%02x, val:%04x\\n\",\n\t\tphy_addr, phy_reg, *val);\n\treturn 0;\n}\n\nstatic int rtl8367_write_phy_reg(struct rtl8366_smi *smi,\n\t\t\t\t u32 phy_addr, u32 phy_reg, u32 val)\n{\n\tint timeout;\n\tu32 data;\n\tint err;\n\n\tdev_dbg(smi->parent, \"phy_write: addr:%02x, reg:%02x, val:%04x\\n\",\n\t\tphy_addr, phy_reg, val);\n\n\tif (phy_addr > RTL8367_PHY_ADDR_MAX)\n\t\treturn -EINVAL;\n\n\tif (phy_reg > RTL8367_PHY_REG_MAX)\n\t\treturn -EINVAL;\n\n\tREG_RD(smi, RTL8367_IA_STATUS_REG, &data);\n\tif (data & RTL8367_IA_STATUS_PHY_BUSY)\n\t\treturn -ETIMEDOUT;\n\n\t/* preapre data */\n\tREG_WR(smi, RTL8367_IA_WRITE_DATA_REG, val);\n\n\t/* prepare address */\n\tREG_WR(smi, RTL8367_IA_ADDRESS_REG,\n\t       RTL8367_INTERNAL_PHY_REG(phy_addr, phy_reg));\n\n\t/* send write command */\n\tREG_WR(smi, RTL8367_IA_CTRL_REG,\n\t       RTL8367_IA_CTRL_CMD_MASK | RTL8367_IA_CTRL_RW_WRITE);\n\n\ttimeout = 5;\n\tdo {\n\t\tREG_RD(smi, RTL8367_IA_STATUS_REG, &data);\n\t\tif ((data & RTL8367_IA_STATUS_PHY_BUSY) == 0)\n\t\t\tbreak;\n\n\t\tif (timeout--) {\n\t\t\tdev_err(smi->parent, \"phy write timed out\\n\");\n\t\t\treturn -ETIMEDOUT;\n\t\t}\n\n\t\tudelay(1);\n\t} while (1);\n\n\treturn 0;\n}\n\nstatic int rtl8367_init_regs0(struct rtl8366_smi *smi, unsigned mode)\n{\n\tconst struct rtl8367_initval *initvals;\n\tint count;\n\tint err;\n\n\tswitch (mode) {\n\tcase 0:\n\t\tinitvals = rtl8367_initvals_0_0;\n\t\tcount = ARRAY_SIZE(rtl8367_initvals_0_0);\n\t\tbreak;\n\n\tcase 1:\n\tcase 2:\n\t\tinitvals = rtl8367_initvals_0_1;\n\t\tcount = ARRAY_SIZE(rtl8367_initvals_0_1);\n\t\tbreak;\n\n\tdefault:\n\t\tdev_err(smi->parent, \"%s: unknow mode %u\\n\", __func__, mode);\n\t\treturn -ENODEV;\n\t}\n\n\terr = rtl8367_write_initvals(smi, initvals, count);\n\tif (err)\n\t\treturn err;\n\n\t/* TODO: complete this */\n\n\treturn 0;\n}\n\nstatic int rtl8367_init_regs1(struct rtl8366_smi *smi, unsigned mode)\n{\n\tconst struct rtl8367_initval *initvals;\n\tint count;\n\n\tswitch (mode) {\n\tcase 0:\n\t\tinitvals = rtl8367_initvals_1_0;\n\t\tcount = ARRAY_SIZE(rtl8367_initvals_1_0);\n\t\tbreak;\n\n\tcase 1:\n\tcase 2:\n\t\tinitvals = rtl8367_initvals_1_1;\n\t\tcount = ARRAY_SIZE(rtl8367_initvals_1_1);\n\t\tbreak;\n\n\tdefault:\n\t\tdev_err(smi->parent, \"%s: unknow mode %u\\n\", __func__, mode);\n\t\treturn -ENODEV;\n\t}\n\n\treturn rtl8367_write_initvals(smi, initvals, count);\n}\n\nstatic int rtl8367_init_regs2(struct rtl8366_smi *smi, unsigned mode)\n{\n\tconst struct rtl8367_initval *initvals;\n\tint count;\n\n\tswitch (mode) {\n\tcase 0:\n\t\tinitvals = rtl8367_initvals_2_0;\n\t\tcount = ARRAY_SIZE(rtl8367_initvals_2_0);\n\t\tbreak;\n\n\tcase 1:\n\tcase 2:\n\t\tinitvals = rtl8367_initvals_2_1;\n\t\tcount = ARRAY_SIZE(rtl8367_initvals_2_1);\n\t\tbreak;\n\n\tdefault:\n\t\tdev_err(smi->parent, \"%s: unknow mode %u\\n\", __func__, mode);\n\t\treturn -ENODEV;\n\t}\n\n\treturn rtl8367_write_initvals(smi, initvals, count);\n}\n\nstatic int rtl8367_init_regs(struct rtl8366_smi *smi)\n{\n\tu32 data;\n\tu32 rlvid;\n\tu32 mode;\n\tint err;\n\n\tREG_WR(smi, RTL8367_RTL_MAGIC_ID_REG, RTL8367_RTL_MAGIC_ID_VAL);\n\n\tREG_RD(smi, RTL8367_CHIP_VER_REG, &data);\n\trlvid = (data >> RTL8367_CHIP_VER_RLVID_SHIFT) &\n\t\tRTL8367_CHIP_VER_RLVID_MASK;\n\n\tREG_RD(smi, RTL8367_CHIP_MODE_REG, &data);\n\tmode = data & RTL8367_CHIP_MODE_MASK;\n\n\tswitch (rlvid) {\n\tcase 0:\n\t\terr = rtl8367_init_regs0(smi, mode);\n\t\tbreak;\n\n\tcase 1:\n\t\terr = rtl8367_write_phy_reg(smi, 0, 31, 5);\n\t\tif (err)\n\t\t\tbreak;\n\n\t\terr = rtl8367_write_phy_reg(smi, 0, 5, 0x3ffe);\n\t\tif (err)\n\t\t\tbreak;\n\n\t\terr = rtl8367_read_phy_reg(smi, 0, 6, &data);\n\t\tif (err)\n\t\t\tbreak;\n\n\t\tif (data == 0x94eb) {\n\t\t\terr = rtl8367_init_regs1(smi, mode);\n\t\t} else if (data == 0x2104) {\n\t\t\terr = rtl8367_init_regs2(smi, mode);\n\t\t} else {\n\t\t\tdev_err(smi->parent, \"unknow phy data %04x\\n\", data);\n\t\t\treturn -ENODEV;\n\t\t}\n\n\t\tbreak;\n\n\tdefault:\n\t\tdev_err(smi->parent, \"unknow rlvid %u\\n\", rlvid);\n\t\terr = -ENODEV;\n\t\tbreak;\n\t}\n\n\treturn err;\n}\n\nstatic int rtl8367_reset_chip(struct rtl8366_smi *smi)\n{\n\tint timeout = 10;\n\tint err;\n\tu32 data;\n\n\tREG_WR(smi, RTL8367_CHIP_RESET_REG, RTL8367_CHIP_RESET_HW);\n\tmsleep(RTL8367_RESET_DELAY);\n\n\tdo {\n\t\tREG_RD(smi, RTL8367_CHIP_RESET_REG, &data);\n\t\tif (!(data & RTL8367_CHIP_RESET_HW))\n\t\t\tbreak;\n\n\t\tmsleep(1);\n\t} while (--timeout);\n\n\tif (!timeout) {\n\t\tdev_err(smi->parent, \"chip reset timed out\\n\");\n\t\treturn -ETIMEDOUT;\n\t}\n\n\treturn 0;\n}\n\nstatic int rtl8367_extif_set_mode(struct rtl8366_smi *smi, int id,\n\t\t\t\t  enum rtl8367_extif_mode mode)\n{\n\tint err;\n\n\t/* set port mode */\n\tswitch (mode) {\n\tcase RTL8367_EXTIF_MODE_RGMII:\n\tcase RTL8367_EXTIF_MODE_RGMII_33V:\n\t\tREG_WR(smi, RTL8367_CHIP_DEBUG0_REG, 0x0367);\n\t\tREG_WR(smi, RTL8367_CHIP_DEBUG1_REG, 0x7777);\n\t\tbreak;\n\n\tcase RTL8367_EXTIF_MODE_TMII_MAC:\n\tcase RTL8367_EXTIF_MODE_TMII_PHY:\n\t\tREG_RMW(smi, RTL8367_BYPASS_LINE_RATE_REG,\n\t\t\tBIT((id + 1) % 2), BIT((id + 1) % 2));\n\t\tbreak;\n\n\tcase RTL8367_EXTIF_MODE_GMII:\n\t\tREG_RMW(smi, RTL8367_CHIP_DEBUG0_REG,\n\t\t        RTL8367_CHIP_DEBUG0_DUMMY0(id),\n\t\t\tRTL8367_CHIP_DEBUG0_DUMMY0(id));\n\t\tREG_RMW(smi, RTL8367_EXT_RGMXF_REG(id), BIT(6), BIT(6));\n\t\tbreak;\n\n\tcase RTL8367_EXTIF_MODE_MII_MAC:\n\tcase RTL8367_EXTIF_MODE_MII_PHY:\n\tcase RTL8367_EXTIF_MODE_DISABLED:\n\t\tREG_RMW(smi, RTL8367_BYPASS_LINE_RATE_REG,\n\t\t\tBIT((id + 1) % 2), 0);\n\t\tREG_RMW(smi, RTL8367_EXT_RGMXF_REG(id), BIT(6), 0);\n\t\tbreak;\n\n\tdefault:\n\t\tdev_err(smi->parent,\n\t\t\t\"invalid mode for external interface %d\\n\", id);\n\t\treturn -EINVAL;\n\t}\n\n\tREG_RMW(smi, RTL8367_DIS_REG,\n\t\tRTL8367_DIS_RGMII_MASK << RTL8367_DIS_RGMII_SHIFT(id),\n\t\tmode << RTL8367_DIS_RGMII_SHIFT(id));\n\n\treturn 0;\n}\n\nstatic int rtl8367_extif_set_force(struct rtl8366_smi *smi, int id,\n\t\t\t\t   struct rtl8367_port_ability *pa)\n{\n\tu32 mask;\n\tu32 val;\n\tint err;\n\n\tmask = (RTL8367_DI_FORCE_MODE |\n\t\tRTL8367_DI_FORCE_NWAY |\n\t\tRTL8367_DI_FORCE_TXPAUSE |\n\t\tRTL8367_DI_FORCE_RXPAUSE |\n\t\tRTL8367_DI_FORCE_LINK |\n\t\tRTL8367_DI_FORCE_DUPLEX |\n\t\tRTL8367_DI_FORCE_SPEED_MASK);\n\n\tval = pa->speed;\n\tval |= pa->force_mode ? RTL8367_DI_FORCE_MODE : 0;\n\tval |= pa->nway ? RTL8367_DI_FORCE_NWAY : 0;\n\tval |= pa->txpause ? RTL8367_DI_FORCE_TXPAUSE : 0;\n\tval |= pa->rxpause ? RTL8367_DI_FORCE_RXPAUSE : 0;\n\tval |= pa->link ? RTL8367_DI_FORCE_LINK : 0;\n\tval |= pa->duplex ? RTL8367_DI_FORCE_DUPLEX : 0;\n\n\tREG_RMW(smi, RTL8367_DI_FORCE_REG(id), mask, val);\n\n\treturn 0;\n}\n\nstatic int rtl8367_extif_set_rgmii_delay(struct rtl8366_smi *smi, int id,\n\t\t\t\t\t unsigned txdelay, unsigned rxdelay)\n{\n\tu32 mask;\n\tu32 val;\n\tint err;\n\n\tmask = (RTL8367_EXT_RGMXF_RXDELAY_MASK |\n\t\t(RTL8367_EXT_RGMXF_TXDELAY_MASK <<\n\t\t\tRTL8367_EXT_RGMXF_TXDELAY_SHIFT));\n\n\tval = rxdelay;\n\tval |= txdelay << RTL8367_EXT_RGMXF_TXDELAY_SHIFT;\n\n\tREG_RMW(smi, RTL8367_EXT_RGMXF_REG(id), mask, val);\n\n\treturn 0;\n}\n\nstatic int rtl8367_extif_init(struct rtl8366_smi *smi, int id,\n\t\t\t      struct rtl8367_extif_config *cfg)\n{\n\tenum rtl8367_extif_mode mode;\n\tint err;\n\n\tmode = (cfg) ? cfg->mode : RTL8367_EXTIF_MODE_DISABLED;\n\n\terr = rtl8367_extif_set_mode(smi, id, mode);\n\tif (err)\n\t\treturn err;\n\n\tif (mode != RTL8367_EXTIF_MODE_DISABLED) {\n\t\terr = rtl8367_extif_set_force(smi, id, &cfg->ability);\n\t\tif (err)\n\t\t\treturn err;\n\n\t\terr = rtl8367_extif_set_rgmii_delay(smi, id, cfg->txdelay,\n\t\t\t\t\t\t     cfg->rxdelay);\n\t\tif (err)\n\t\t\treturn err;\n\t}\n\n\treturn 0;\n}\n\nstatic int rtl8367_led_group_set_ports(struct rtl8366_smi *smi,\n\t\t\t\t       unsigned int group, u16 port_mask)\n{\n\tu32 reg;\n\tu32 s;\n\tint err;\n\n\tport_mask &= RTL8367_PARA_LED_IO_EN_PMASK;\n\ts = (group % 2) * 8;\n\treg = RTL8367_PARA_LED_IO_EN1_REG + (group / 2);\n\n\tREG_RMW(smi, reg, (RTL8367_PARA_LED_IO_EN_PMASK << s), port_mask << s);\n\n\treturn 0;\n}\n\nstatic int rtl8367_led_group_set_mode(struct rtl8366_smi *smi,\n\t\t\t\t      unsigned int mode)\n{\n\tu16 mask;\n\tu16 set;\n\tint err;\n\n\tmode &= RTL8367_LED_CONFIG_DATA_M;\n\n\tmask = (RTL8367_LED_CONFIG_DATA_M << RTL8367_LED_CONFIG_DATA_S) |\n\t\tRTL8367_LED_CONFIG_SEL;\n\tset = (mode << RTL8367_LED_CONFIG_DATA_S) | RTL8367_LED_CONFIG_SEL;\n\n\tREG_RMW(smi, RTL8367_LED_CONFIG_REG, mask, set);\n\n\treturn 0;\n}\n\nstatic int rtl8367_led_group_set_config(struct rtl8366_smi *smi,\n\t\t\t\t        unsigned int led, unsigned int cfg)\n{\n\tu16 mask;\n\tu16 set;\n\tint err;\n\n\tmask = (RTL8367_LED_CONFIG_LED_CFG_M << (led * 4)) |\n\t\tRTL8367_LED_CONFIG_SEL;\n\tset = (cfg & RTL8367_LED_CONFIG_LED_CFG_M) << (led * 4);\n\n\tREG_RMW(smi, RTL8367_LED_CONFIG_REG, mask, set);\n\treturn 0;\n}\n\nstatic int rtl8367_led_op_select_parallel(struct rtl8366_smi *smi)\n{\n\tint err;\n\n\tREG_WR(smi, RTL8367_LED_SYS_CONFIG_REG, 0x1472);\n\treturn 0;\n}\n\nstatic int rtl8367_led_blinkrate_set(struct rtl8366_smi *smi, unsigned int rate)\n{\n\tu16 mask;\n\tu16 set;\n\tint err;\n\n\tmask = RTL8367_LED_MODE_RATE_M << RTL8367_LED_MODE_RATE_S;\n\tset = (rate & RTL8367_LED_MODE_RATE_M) << RTL8367_LED_MODE_RATE_S;\n\tREG_RMW(smi, RTL8367_LED_MODE_REG, mask, set);\n\n\treturn 0;\n}\n\n#ifdef CONFIG_OF\nstatic int rtl8367_extif_init_of(struct rtl8366_smi *smi, int id,\n\t\t\t\t const char *name)\n{\n\tstruct rtl8367_extif_config *cfg;\n\tconst __be32 *prop;\n\tint size;\n\tint err;\n\n\tprop = of_get_property(smi->parent->of_node, name, &size);\n\tif (!prop)\n\t\treturn rtl8367_extif_init(smi, id, NULL);\n\n\tif (size != (9 * sizeof(*prop))) {\n\t\tdev_err(smi->parent, \"%s property is invalid\\n\", name);\n\t\treturn -EINVAL;\n\t}\n\n\tcfg = kzalloc(sizeof(struct rtl8367_extif_config), GFP_KERNEL);\n\tif (!cfg)\n\t\treturn -ENOMEM;\n\n\tcfg->txdelay = be32_to_cpup(prop++);\n\tcfg->rxdelay = be32_to_cpup(prop++);\n\tcfg->mode = be32_to_cpup(prop++);\n\tcfg->ability.force_mode = be32_to_cpup(prop++);\n\tcfg->ability.txpause = be32_to_cpup(prop++);\n\tcfg->ability.rxpause = be32_to_cpup(prop++);\n\tcfg->ability.link = be32_to_cpup(prop++);\n\tcfg->ability.duplex = be32_to_cpup(prop++);\n\tcfg->ability.speed = be32_to_cpup(prop++);\n\n\terr = rtl8367_extif_init(smi, id, cfg);\n\tkfree(cfg);\n\n\treturn err;\n}\n#else\nstatic int rtl8367_extif_init_of(struct rtl8366_smi *smi, int id,\n\t\t\t\t const char *name)\n{\n\treturn -EINVAL;\n}\n#endif\n\nstatic int rtl8367_setup(struct rtl8366_smi *smi)\n{\n\tstruct rtl8367_platform_data *pdata;\n\tint err;\n\tint i;\n\n\tpdata = smi->parent->platform_data;\n\n\terr = rtl8367_init_regs(smi);\n\tif (err)\n\t\treturn err;\n\n\t/* initialize external interfaces */\n\tif (smi->parent->of_node) {\n\t\terr = rtl8367_extif_init_of(smi, 0, \"realtek,extif0\");\n\t\tif (err)\n\t\t\treturn err;\n\n\t\terr = rtl8367_extif_init_of(smi, 1, \"realtek,extif1\");\n\t\tif (err)\n\t\t\treturn err;\n\t} else {\n\t\terr = rtl8367_extif_init(smi, 0, pdata->extif0_cfg);\n\t\tif (err)\n\t\t\treturn err;\n\n\t\terr = rtl8367_extif_init(smi, 1, pdata->extif1_cfg);\n\t\tif (err)\n\t\t\treturn err;\n\t}\n\n\t/* set maximum packet length to 1536 bytes */\n\tREG_RMW(smi, RTL8367_SWC0_REG, RTL8367_SWC0_MAX_LENGTH_MASK,\n\t\tRTL8367_SWC0_MAX_LENGTH_1536);\n\n\t/*\n\t * discard VLAN tagged packets if the port is not a member of\n\t * the VLAN with which the packets is associated.\n\t */\n\tREG_WR(smi, RTL8367_VLAN_INGRESS_REG, RTL8367_PORTS_ALL);\n\n\t/*\n\t * Setup egress tag mode for each port.\n\t */\n\tfor (i = 0; i < RTL8367_NUM_PORTS; i++)\n\t\tREG_RMW(smi,\n\t\t\tRTL8367_PORT_CFG_REG(i),\n\t\t\tRTL8367_PORT_CFG_EGRESS_MODE_MASK <<\n\t\t\t\tRTL8367_PORT_CFG_EGRESS_MODE_SHIFT,\n\t\t\tRTL8367_PORT_CFG_EGRESS_MODE_ORIGINAL <<\n\t\t\t\tRTL8367_PORT_CFG_EGRESS_MODE_SHIFT);\n\n\t/* setup LEDs */\n\terr = rtl8367_led_group_set_ports(smi, 0, RTL8367_PORTS_ALL);\n\tif (err)\n\t\treturn err;\n\n\terr = rtl8367_led_group_set_mode(smi, 0);\n\tif (err)\n\t\treturn err;\n\n\terr = rtl8367_led_op_select_parallel(smi);\n\tif (err)\n\t\treturn err;\n\n\terr = rtl8367_led_blinkrate_set(smi, 1);\n\tif (err)\n\t\treturn err;\n\n\terr = rtl8367_led_group_set_config(smi, 0, 2);\n\tif (err)\n\t\treturn err;\n\n\treturn 0;\n}\n\nstatic int rtl8367_get_mib_counter(struct rtl8366_smi *smi, int counter,\n\t\t\t\t   int port, unsigned long long *val)\n{\n\tstruct rtl8366_mib_counter *mib;\n\tint offset;\n\tint i;\n\tint err;\n\tu32 addr, data;\n\tu64 mibvalue;\n\n\tif (port > RTL8367_NUM_PORTS || counter >= RTL8367_MIB_COUNT)\n\t\treturn -EINVAL;\n\n\tmib = &rtl8367_mib_counters[counter];\n\taddr = RTL8367_MIB_COUNTER_PORT_OFFSET * port + mib->offset;\n\n\t/*\n\t * Writing access counter address first\n\t * then ASIC will prepare 64bits counter wait for being retrived\n\t */\n\tREG_WR(smi, RTL8367_MIB_ADDRESS_REG, addr >> 2);\n\n\t/* read MIB control register */\n\tREG_RD(smi, RTL8367_MIB_CTRL_REG(0), &data);\n\n\tif (data & RTL8367_MIB_CTRL_BUSY_MASK)\n\t\treturn -EBUSY;\n\n\tif (data & RTL8367_MIB_CTRL_RESET_MASK)\n\t\treturn -EIO;\n\n\tif (mib->length == 4)\n\t\toffset = 3;\n\telse\n\t\toffset = (mib->offset + 1) % 4;\n\n\tmibvalue = 0;\n\tfor (i = 0; i < mib->length; i++) {\n\t\tREG_RD(smi, RTL8367_MIB_COUNTER_REG(offset - i), &data);\n\t\tmibvalue = (mibvalue << 16) | (data & 0xFFFF);\n\t}\n\n\t*val = mibvalue;\n\treturn 0;\n}\n\nstatic int rtl8367_get_vlan_4k(struct rtl8366_smi *smi, u32 vid,\n\t\t\t\tstruct rtl8366_vlan_4k *vlan4k)\n{\n\tu32 data[RTL8367_TA_VLAN_DATA_SIZE];\n\tint err;\n\tint i;\n\n\tmemset(vlan4k, '\\0', sizeof(struct rtl8366_vlan_4k));\n\n\tif (vid >= RTL8367_NUM_VIDS)\n\t\treturn -EINVAL;\n\n\t/* write VID */\n\tREG_WR(smi, RTL8367_TA_ADDR_REG, vid);\n\n\t/* write table access control word */\n\tREG_WR(smi, RTL8367_TA_CTRL_REG, RTL8367_TA_CTRL_CVLAN_READ);\n\n\tfor (i = 0; i < ARRAY_SIZE(data); i++)\n\t\tREG_RD(smi, RTL8367_TA_DATA_REG(i), &data[i]);\n\n\tvlan4k->vid = vid;\n\tvlan4k->member = (data[0] >> RTL8367_TA_VLAN_MEMBER_SHIFT) &\n\t\t\t RTL8367_TA_VLAN_MEMBER_MASK;\n\tvlan4k->fid = (data[1] >> RTL8367_TA_VLAN_FID_SHIFT) &\n\t\t      RTL8367_TA_VLAN_FID_MASK;\n\tvlan4k->untag = (data[2] >> RTL8367_TA_VLAN_UNTAG1_SHIFT) &\n\t\t\tRTL8367_TA_VLAN_UNTAG1_MASK;\n\tvlan4k->untag |= ((data[3] >> RTL8367_TA_VLAN_UNTAG2_SHIFT) &\n\t\t\t  RTL8367_TA_VLAN_UNTAG2_MASK) << 2;\n\n\treturn 0;\n}\n\nstatic int rtl8367_set_vlan_4k(struct rtl8366_smi *smi,\n\t\t\t\tconst struct rtl8366_vlan_4k *vlan4k)\n{\n\tu32 data[RTL8367_TA_VLAN_DATA_SIZE];\n\tint err;\n\tint i;\n\n\tif (vlan4k->vid >= RTL8367_NUM_VIDS ||\n\t    vlan4k->member > RTL8367_TA_VLAN_MEMBER_MASK ||\n\t    vlan4k->untag > RTL8367_UNTAG_MASK ||\n\t    vlan4k->fid > RTL8367_FIDMAX)\n\t\treturn -EINVAL;\n\n\tdata[0] = (vlan4k->member & RTL8367_TA_VLAN_MEMBER_MASK) <<\n\t\t  RTL8367_TA_VLAN_MEMBER_SHIFT;\n\tdata[1] = (vlan4k->fid & RTL8367_TA_VLAN_FID_MASK) <<\n\t\t  RTL8367_TA_VLAN_FID_SHIFT;\n\tdata[2] = (vlan4k->untag & RTL8367_TA_VLAN_UNTAG1_MASK) <<\n\t\t  RTL8367_TA_VLAN_UNTAG1_SHIFT;\n\tdata[3] = ((vlan4k->untag >> 2) & RTL8367_TA_VLAN_UNTAG2_MASK) <<\n\t\t  RTL8367_TA_VLAN_UNTAG2_SHIFT;\n\n\tfor (i = 0; i < ARRAY_SIZE(data); i++)\n\t\tREG_WR(smi, RTL8367_TA_DATA_REG(i), data[i]);\n\n\t/* write VID */\n\tREG_WR(smi, RTL8367_TA_ADDR_REG,\n\t       vlan4k->vid & RTL8367_TA_VLAN_VID_MASK);\n\n\t/* write table access control word */\n\tREG_WR(smi, RTL8367_TA_CTRL_REG, RTL8367_TA_CTRL_CVLAN_WRITE);\n\n\treturn 0;\n}\n\nstatic int rtl8367_get_vlan_mc(struct rtl8366_smi *smi, u32 index,\n\t\t\t\tstruct rtl8366_vlan_mc *vlanmc)\n{\n\tu32 data[RTL8367_VLAN_MC_DATA_SIZE];\n\tint err;\n\tint i;\n\n\tmemset(vlanmc, '\\0', sizeof(struct rtl8366_vlan_mc));\n\n\tif (index >= RTL8367_NUM_VLANS)\n\t\treturn -EINVAL;\n\n\tfor (i = 0; i < ARRAY_SIZE(data); i++)\n\t\tREG_RD(smi, RTL8367_VLAN_MC_BASE(index) + i, &data[i]);\n\n\tvlanmc->member = (data[0] >> RTL8367_VLAN_MC_MEMBER_SHIFT) &\n\t\t\t RTL8367_VLAN_MC_MEMBER_MASK;\n\tvlanmc->fid = (data[1] >> RTL8367_VLAN_MC_FID_SHIFT) &\n\t\t      RTL8367_VLAN_MC_FID_MASK;\n\tvlanmc->vid = (data[3] >> RTL8367_VLAN_MC_EVID_SHIFT) &\n\t\t      RTL8367_VLAN_MC_EVID_MASK;\n\n\treturn 0;\n}\n\nstatic int rtl8367_set_vlan_mc(struct rtl8366_smi *smi, u32 index,\n\t\t\t\tconst struct rtl8366_vlan_mc *vlanmc)\n{\n\tu32 data[RTL8367_VLAN_MC_DATA_SIZE];\n\tint err;\n\tint i;\n\n\tif (index >= RTL8367_NUM_VLANS ||\n\t    vlanmc->vid >= RTL8367_NUM_VIDS ||\n\t    vlanmc->priority > RTL8367_PRIORITYMAX ||\n\t    vlanmc->member > RTL8367_VLAN_MC_MEMBER_MASK ||\n\t    vlanmc->untag > RTL8367_UNTAG_MASK ||\n\t    vlanmc->fid > RTL8367_FIDMAX)\n\t\treturn -EINVAL;\n\n\tdata[0] = (vlanmc->member & RTL8367_VLAN_MC_MEMBER_MASK) <<\n\t\t  RTL8367_VLAN_MC_MEMBER_SHIFT;\n\tdata[1] = (vlanmc->fid & RTL8367_VLAN_MC_FID_MASK) <<\n\t\t  RTL8367_VLAN_MC_FID_SHIFT;\n\tdata[2] = 0;\n\tdata[3] = (vlanmc->vid & RTL8367_VLAN_MC_EVID_MASK) <<\n\t\t   RTL8367_VLAN_MC_EVID_SHIFT;\n\n\tfor (i = 0; i < ARRAY_SIZE(data); i++)\n\t\tREG_WR(smi, RTL8367_VLAN_MC_BASE(index) + i, data[i]);\n\n\treturn 0;\n}\n\nstatic int rtl8367_get_mc_index(struct rtl8366_smi *smi, int port, int *val)\n{\n\tu32 data;\n\tint err;\n\n\tif (port >= RTL8367_NUM_PORTS)\n\t\treturn -EINVAL;\n\n\tREG_RD(smi, RTL8367_VLAN_PVID_CTRL_REG(port), &data);\n\n\t*val = (data >> RTL8367_VLAN_PVID_CTRL_SHIFT(port)) &\n\t       RTL8367_VLAN_PVID_CTRL_MASK;\n\n\treturn 0;\n}\n\nstatic int rtl8367_set_mc_index(struct rtl8366_smi *smi, int port, int index)\n{\n\tif (port >= RTL8367_NUM_PORTS || index >= RTL8367_NUM_VLANS)\n\t\treturn -EINVAL;\n\n\treturn rtl8366_smi_rmwr(smi, RTL8367_VLAN_PVID_CTRL_REG(port),\n\t\t\t\tRTL8367_VLAN_PVID_CTRL_MASK <<\n\t\t\t\t\tRTL8367_VLAN_PVID_CTRL_SHIFT(port),\n\t\t\t\t(index & RTL8367_VLAN_PVID_CTRL_MASK) <<\n\t\t\t\t\tRTL8367_VLAN_PVID_CTRL_SHIFT(port));\n}\n\nstatic int rtl8367_enable_vlan(struct rtl8366_smi *smi, int enable)\n{\n\treturn rtl8366_smi_rmwr(smi, RTL8367_VLAN_CTRL_REG,\n\t\t\t\tRTL8367_VLAN_CTRL_ENABLE,\n\t\t\t\t(enable) ? RTL8367_VLAN_CTRL_ENABLE : 0);\n}\n\nstatic int rtl8367_enable_vlan4k(struct rtl8366_smi *smi, int enable)\n{\n\treturn 0;\n}\n\nstatic int rtl8367_is_vlan_valid(struct rtl8366_smi *smi, unsigned vlan)\n{\n\tunsigned max = RTL8367_NUM_VLANS;\n\n\tif (smi->vlan4k_enabled)\n\t\tmax = RTL8367_NUM_VIDS - 1;\n\n\tif (vlan == 0 || vlan >= max)\n\t\treturn 0;\n\n\treturn 1;\n}\n\nstatic int rtl8367_enable_port(struct rtl8366_smi *smi, int port, int enable)\n{\n\tint err;\n\n\tREG_WR(smi, RTL8367_PORT_ISOLATION_REG(port),\n\t       (enable) ? RTL8367_PORTS_ALL : 0);\n\n\treturn 0;\n}\n\nstatic int rtl8367_sw_reset_mibs(struct switch_dev *dev,\n\t\t\t\t  const struct switch_attr *attr,\n\t\t\t\t  struct switch_val *val)\n{\n\tstruct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);\n\n\treturn rtl8366_smi_rmwr(smi, RTL8367_MIB_CTRL_REG(0), 0,\n\t\t\t\tRTL8367_MIB_CTRL_GLOBAL_RESET_MASK);\n}\n\nstatic int rtl8367_sw_get_port_link(struct switch_dev *dev,\n\t\t\t\t    int port,\n\t\t\t\t    struct switch_port_link *link)\n{\n\tstruct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);\n\tu32 data = 0;\n\tu32 speed;\n\n\tif (port >= RTL8367_NUM_PORTS)\n\t\treturn -EINVAL;\n\n\trtl8366_smi_read_reg(smi, RTL8367_PORT_STATUS_REG(port), &data);\n\n\tlink->link = !!(data & RTL8367_PORT_STATUS_LINK);\n\tif (!link->link)\n\t\treturn 0;\n\n\tlink->duplex = !!(data & RTL8367_PORT_STATUS_DUPLEX);\n\tlink->rx_flow = !!(data & RTL8367_PORT_STATUS_RXPAUSE);\n\tlink->tx_flow = !!(data & RTL8367_PORT_STATUS_TXPAUSE);\n\tlink->aneg = !!(data & RTL8367_PORT_STATUS_NWAY);\n\n\tspeed = (data & RTL8367_PORT_STATUS_SPEED_MASK);\n\tswitch (speed) {\n\tcase 0:\n\t\tlink->speed = SWITCH_PORT_SPEED_10;\n\t\tbreak;\n\tcase 1:\n\t\tlink->speed = SWITCH_PORT_SPEED_100;\n\t\tbreak;\n\tcase 2:\n\t\tlink->speed = SWITCH_PORT_SPEED_1000;\n\t\tbreak;\n\tdefault:\n\t\tlink->speed = SWITCH_PORT_SPEED_UNKNOWN;\n\t\tbreak;\n\t}\n\n\treturn 0;\n}\n\nstatic int rtl8367_sw_get_max_length(struct switch_dev *dev,\n\t\t\t\t     const struct switch_attr *attr,\n\t\t\t\t     struct switch_val *val)\n{\n\tstruct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);\n\tu32 data;\n\n\trtl8366_smi_read_reg(smi, RTL8367_SWC0_REG, &data);\n\tval->value.i = (data & RTL8367_SWC0_MAX_LENGTH_MASK) >>\n\t\t\tRTL8367_SWC0_MAX_LENGTH_SHIFT;\n\n\treturn 0;\n}\n\nstatic int rtl8367_sw_set_max_length(struct switch_dev *dev,\n\t\t\t\t     const struct switch_attr *attr,\n\t\t\t\t     struct switch_val *val)\n{\n\tstruct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);\n\tu32 max_len;\n\n\tswitch (val->value.i) {\n\tcase 0:\n\t\tmax_len = RTL8367_SWC0_MAX_LENGTH_1522;\n\t\tbreak;\n\tcase 1:\n\t\tmax_len = RTL8367_SWC0_MAX_LENGTH_1536;\n\t\tbreak;\n\tcase 2:\n\t\tmax_len = RTL8367_SWC0_MAX_LENGTH_1552;\n\t\tbreak;\n\tcase 3:\n\t\tmax_len = RTL8367_SWC0_MAX_LENGTH_16000;\n\t\tbreak;\n\tdefault:\n\t\treturn -EINVAL;\n\t}\n\n\treturn rtl8366_smi_rmwr(smi, RTL8367_SWC0_REG,\n\t\t\t        RTL8367_SWC0_MAX_LENGTH_MASK, max_len);\n}\n\n\nstatic int rtl8367_sw_reset_port_mibs(struct switch_dev *dev,\n\t\t\t\t       const struct switch_attr *attr,\n\t\t\t\t       struct switch_val *val)\n{\n\tstruct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);\n\tint port;\n\n\tport = val->port_vlan;\n\tif (port >= RTL8367_NUM_PORTS)\n\t\treturn -EINVAL;\n\n\treturn rtl8366_smi_rmwr(smi, RTL8367_MIB_CTRL_REG(port / 8), 0,\n\t\t\t\tRTL8367_MIB_CTRL_PORT_RESET_MASK(port % 8));\n}\n\nstatic int rtl8367_sw_get_port_stats(struct switch_dev *dev, int port,\n                                        struct switch_port_stats *stats)\n{\n\treturn (rtl8366_sw_get_port_stats(dev, port, stats,\n\t\t\t\tRTL8367_MIB_TXB_ID, RTL8367_MIB_RXB_ID));\n}\n\nstatic struct switch_attr rtl8367_globals[] = {\n\t{\n\t\t.type = SWITCH_TYPE_INT,\n\t\t.name = \"enable_vlan\",\n\t\t.description = \"Enable VLAN mode\",\n\t\t.set = rtl8366_sw_set_vlan_enable,\n\t\t.get = rtl8366_sw_get_vlan_enable,\n\t\t.max = 1,\n\t\t.ofs = 1\n\t}, {\n\t\t.type = SWITCH_TYPE_INT,\n\t\t.name = \"enable_vlan4k\",\n\t\t.description = \"Enable VLAN 4K mode\",\n\t\t.set = rtl8366_sw_set_vlan_enable,\n\t\t.get = rtl8366_sw_get_vlan_enable,\n\t\t.max = 1,\n\t\t.ofs = 2\n\t}, {\n\t\t.type = SWITCH_TYPE_NOVAL,\n\t\t.name = \"reset_mibs\",\n\t\t.description = \"Reset all MIB counters\",\n\t\t.set = rtl8367_sw_reset_mibs,\n\t}, {\n\t\t.type = SWITCH_TYPE_INT,\n\t\t.name = \"max_length\",\n\t\t.description = \"Get/Set the maximum length of valid packets\"\n\t\t\t       \"(0:1522, 1:1536, 2:1552, 3:16000)\",\n\t\t.set = rtl8367_sw_set_max_length,\n\t\t.get = rtl8367_sw_get_max_length,\n\t\t.max = 3,\n\t}\n};\n\nstatic struct switch_attr rtl8367_port[] = {\n\t{\n\t\t.type = SWITCH_TYPE_NOVAL,\n\t\t.name = \"reset_mib\",\n\t\t.description = \"Reset single port MIB counters\",\n\t\t.set = rtl8367_sw_reset_port_mibs,\n\t}, {\n\t\t.type = SWITCH_TYPE_STRING,\n\t\t.name = \"mib\",\n\t\t.description = \"Get MIB counters for port\",\n\t\t.max = 33,\n\t\t.set = NULL,\n\t\t.get = rtl8366_sw_get_port_mib,\n\t},\n};\n\nstatic struct switch_attr rtl8367_vlan[] = {\n\t{\n\t\t.type = SWITCH_TYPE_STRING,\n\t\t.name = \"info\",\n\t\t.description = \"Get vlan information\",\n\t\t.max = 1,\n\t\t.set = NULL,\n\t\t.get = rtl8366_sw_get_vlan_info,\n\t}, {\n\t\t.type = SWITCH_TYPE_INT,\n\t\t.name = \"fid\",\n\t\t.description = \"Get/Set vlan FID\",\n\t\t.max = RTL8367_FIDMAX,\n\t\t.set = rtl8366_sw_set_vlan_fid,\n\t\t.get = rtl8366_sw_get_vlan_fid,\n\t},\n};\n\nstatic const struct switch_dev_ops rtl8367_sw_ops = {\n\t.attr_global = {\n\t\t.attr = rtl8367_globals,\n\t\t.n_attr = ARRAY_SIZE(rtl8367_globals),\n\t},\n\t.attr_port = {\n\t\t.attr = rtl8367_port,\n\t\t.n_attr = ARRAY_SIZE(rtl8367_port),\n\t},\n\t.attr_vlan = {\n\t\t.attr = rtl8367_vlan,\n\t\t.n_attr = ARRAY_SIZE(rtl8367_vlan),\n\t},\n\n\t.get_vlan_ports = rtl8366_sw_get_vlan_ports,\n\t.set_vlan_ports = rtl8366_sw_set_vlan_ports,\n\t.get_port_pvid = rtl8366_sw_get_port_pvid,\n\t.set_port_pvid = rtl8366_sw_set_port_pvid,\n\t.reset_switch = rtl8366_sw_reset_switch,\n\t.get_port_link = rtl8367_sw_get_port_link,\n\t.get_port_stats = rtl8367_sw_get_port_stats,\n};\n\nstatic int rtl8367_switch_init(struct rtl8366_smi *smi)\n{\n\tstruct switch_dev *dev = &smi->sw_dev;\n\tint err;\n\n\tdev->name = \"RTL8367\";\n\tdev->cpu_port = RTL8367_CPU_PORT_NUM;\n\tdev->ports = RTL8367_NUM_PORTS;\n\tdev->vlans = RTL8367_NUM_VIDS;\n\tdev->ops = &rtl8367_sw_ops;\n\tdev->alias = dev_name(smi->parent);\n\n\terr = register_switch(dev, NULL);\n\tif (err)\n\t\tdev_err(smi->parent, \"switch registration failed\\n\");\n\n\treturn err;\n}\n\nstatic void rtl8367_switch_cleanup(struct rtl8366_smi *smi)\n{\n\tunregister_switch(&smi->sw_dev);\n}\n\nstatic int rtl8367_mii_read(struct mii_bus *bus, int addr, int reg)\n{\n\tstruct rtl8366_smi *smi = bus->priv;\n\tu32 val = 0;\n\tint err;\n\n\terr = rtl8367_read_phy_reg(smi, addr, reg, &val);\n\tif (err)\n\t\treturn 0xffff;\n\n\treturn val;\n}\n\nstatic int rtl8367_mii_write(struct mii_bus *bus, int addr, int reg, u16 val)\n{\n\tstruct rtl8366_smi *smi = bus->priv;\n\tu32 t;\n\tint err;\n\n\terr = rtl8367_write_phy_reg(smi, addr, reg, val);\n\tif (err)\n\t\treturn err;\n\n\t/* flush write */\n\t(void) rtl8367_read_phy_reg(smi, addr, reg, &t);\n\n\treturn err;\n}\n\nstatic int rtl8367_detect(struct rtl8366_smi *smi)\n{\n\tu32 rtl_no = 0;\n\tu32 rtl_ver = 0;\n\tchar *chip_name;\n\tint ret;\n\n\tret = rtl8366_smi_read_reg(smi, RTL8367_RTL_NO_REG, &rtl_no);\n\tif (ret) {\n\t\tdev_err(smi->parent, \"unable to read chip number\\n\");\n\t\treturn ret;\n\t}\n\n\tswitch (rtl_no) {\n\tcase RTL8367_RTL_NO_8367R:\n\t\tchip_name = \"8367R\";\n\t\tbreak;\n\tcase RTL8367_RTL_NO_8367M:\n\t\tchip_name = \"8367M\";\n\t\tbreak;\n\tdefault:\n\t\tdev_err(smi->parent, \"unknown chip number (%04x)\\n\", rtl_no);\n\t\treturn -ENODEV;\n\t}\n\n\tret = rtl8366_smi_read_reg(smi, RTL8367_RTL_VER_REG, &rtl_ver);\n\tif (ret) {\n\t\tdev_err(smi->parent, \"unable to read chip version\\n\");\n\t\treturn ret;\n\t}\n\n\tdev_info(smi->parent, \"RTL%s ver. %u chip found\\n\",\n\t\t chip_name, rtl_ver & RTL8367_RTL_VER_MASK);\n\n\treturn 0;\n}\n\nstatic struct rtl8366_smi_ops rtl8367_smi_ops = {\n\t.detect\t\t= rtl8367_detect,\n\t.reset_chip\t= rtl8367_reset_chip,\n\t.setup\t\t= rtl8367_setup,\n\n\t.mii_read\t= rtl8367_mii_read,\n\t.mii_write\t= rtl8367_mii_write,\n\n\t.get_vlan_mc\t= rtl8367_get_vlan_mc,\n\t.set_vlan_mc\t= rtl8367_set_vlan_mc,\n\t.get_vlan_4k\t= rtl8367_get_vlan_4k,\n\t.set_vlan_4k\t= rtl8367_set_vlan_4k,\n\t.get_mc_index\t= rtl8367_get_mc_index,\n\t.set_mc_index\t= rtl8367_set_mc_index,\n\t.get_mib_counter = rtl8367_get_mib_counter,\n\t.is_vlan_valid\t= rtl8367_is_vlan_valid,\n\t.enable_vlan\t= rtl8367_enable_vlan,\n\t.enable_vlan4k\t= rtl8367_enable_vlan4k,\n\t.enable_port\t= rtl8367_enable_port,\n};\n\nstatic int rtl8367_probe(struct platform_device *pdev)\n{\n\tstruct rtl8366_smi *smi;\n\tint err;\n\n\tsmi = rtl8366_smi_probe(pdev);\n\tif (IS_ERR(smi))\n\t\treturn PTR_ERR(smi);\n\n\tsmi->clk_delay = 1500;\n\tsmi->cmd_read = 0xb9;\n\tsmi->cmd_write = 0xb8;\n\tsmi->ops = &rtl8367_smi_ops;\n\tsmi->cpu_port = RTL8367_CPU_PORT_NUM;\n\tsmi->num_ports = RTL8367_NUM_PORTS;\n\tsmi->num_vlan_mc = RTL8367_NUM_VLANS;\n\tsmi->mib_counters = rtl8367_mib_counters;\n\tsmi->num_mib_counters = ARRAY_SIZE(rtl8367_mib_counters);\n\n\terr = rtl8366_smi_init(smi);\n\tif (err)\n\t\tgoto err_free_smi;\n\n\tplatform_set_drvdata(pdev, smi);\n\n\terr = rtl8367_switch_init(smi);\n\tif (err)\n\t\tgoto err_clear_drvdata;\n\n\treturn 0;\n\n err_clear_drvdata:\n\tplatform_set_drvdata(pdev, NULL);\n\trtl8366_smi_cleanup(smi);\n err_free_smi:\n\tkfree(smi);\n\treturn err;\n}\n\nstatic int rtl8367_remove(struct platform_device *pdev)\n{\n\tstruct rtl8366_smi *smi = platform_get_drvdata(pdev);\n\n\tif (smi) {\n\t\trtl8367_switch_cleanup(smi);\n\t\tplatform_set_drvdata(pdev, NULL);\n\t\trtl8366_smi_cleanup(smi);\n\t\tkfree(smi);\n\t}\n\n\treturn 0;\n}\n\nstatic void rtl8367_shutdown(struct platform_device *pdev)\n{\n\tstruct rtl8366_smi *smi = platform_get_drvdata(pdev);\n\n\tif (smi)\n\t\trtl8367_reset_chip(smi);\n}\n\n#ifdef CONFIG_OF\nstatic const struct of_device_id rtl8367_match[] = {\n       { .compatible = \"realtek,rtl8367\" },\n       {},\n};\nMODULE_DEVICE_TABLE(of, rtl8367_match);\n#endif\n\nstatic struct platform_driver rtl8367_driver = {\n\t.driver = {\n\t\t.name\t\t= RTL8367_DRIVER_NAME,\n\t\t.owner\t\t= THIS_MODULE,\n#ifdef CONFIG_OF\n\t\t.of_match_table = of_match_ptr(rtl8367_match),\n#endif\n\t},\n\t.probe\t\t= rtl8367_probe,\n\t.remove\t\t= rtl8367_remove,\n\t.shutdown\t= rtl8367_shutdown,\n};\n\nstatic int __init rtl8367_module_init(void)\n{\n\treturn platform_driver_register(&rtl8367_driver);\n}\nmodule_init(rtl8367_module_init);\n\nstatic void __exit rtl8367_module_exit(void)\n{\n\tplatform_driver_unregister(&rtl8367_driver);\n}\nmodule_exit(rtl8367_module_exit);\n\nMODULE_DESCRIPTION(\"Realtek RTL8367 ethernet switch driver\");\nMODULE_AUTHOR(\"Gabor Juhos <juhosg@openwrt.org>\");\nMODULE_LICENSE(\"GPL v2\");\nMODULE_ALIAS(\"platform:\" RTL8367_DRIVER_NAME);\n"
  },
  {
    "path": "target/linux/generic/files/drivers/net/phy/rtl8367b.c",
    "content": "/*\n * Platform driver for the Realtek RTL8367R-VB ethernet switches\n *\n * Copyright (C) 2012 Gabor Juhos <juhosg@openwrt.org>\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of the GNU General Public License version 2 as published\n * by the Free Software Foundation.\n */\n\n#include <linux/kernel.h>\n#include <linux/module.h>\n#include <linux/init.h>\n#include <linux/device.h>\n#include <linux/of.h>\n#include <linux/of_platform.h>\n#include <linux/delay.h>\n#include <linux/skbuff.h>\n#include <linux/rtl8367.h>\n\n#include \"rtl8366_smi.h\"\n\n#define RTL8367B_RESET_DELAY\t1000\t/* msecs*/\n\n#define RTL8367B_PHY_ADDR_MAX\t8\n#define RTL8367B_PHY_REG_MAX\t31\n\n#define RTL8367B_VID_MASK\t0x3fff\n#define RTL8367B_FID_MASK\t0xf\n#define RTL8367B_UNTAG_MASK\t0xff\n#define RTL8367B_MEMBER_MASK\t0xff\n\n#define RTL8367B_PORT_MISC_CFG_REG(_p)\t\t(0x000e + 0x20 * (_p))\n#define   RTL8367B_PORT_MISC_CFG_EGRESS_MODE_SHIFT\t4\n#define   RTL8367B_PORT_MISC_CFG_EGRESS_MODE_MASK\t0x3\n#define   RTL8367B_PORT_MISC_CFG_EGRESS_MODE_ORIGINAL\t0\n#define   RTL8367B_PORT_MISC_CFG_EGRESS_MODE_KEEP\t1\n#define   RTL8367B_PORT_MISC_CFG_EGRESS_MODE_PRI\t2\n#define   RTL8367B_PORT_MISC_CFG_EGRESS_MODE_REAL\t3\n\n#define RTL8367B_BYPASS_LINE_RATE_REG\t\t0x03f7\n\n#define RTL8367B_TA_CTRL_REG\t\t\t0x0500 /*GOOD*/\n#define   RTL8367B_TA_CTRL_SPA_SHIFT\t\t8\n#define   RTL8367B_TA_CTRL_SPA_MASK\t\t0x7\n#define   RTL8367B_TA_CTRL_METHOD\t\tBIT(4)/*GOOD*/\n#define   RTL8367B_TA_CTRL_CMD_SHIFT\t\t3\n#define   RTL8367B_TA_CTRL_CMD_READ\t\t0\n#define   RTL8367B_TA_CTRL_CMD_WRITE\t\t1\n#define   RTL8367B_TA_CTRL_TABLE_SHIFT\t\t0 /*GOOD*/\n#define   RTL8367B_TA_CTRL_TABLE_ACLRULE\t1\n#define   RTL8367B_TA_CTRL_TABLE_ACLACT\t\t2\n#define   RTL8367B_TA_CTRL_TABLE_CVLAN\t\t3\n#define   RTL8367B_TA_CTRL_TABLE_L2\t\t4\n#define   RTL8367B_TA_CTRL_CVLAN_READ \\\n\t\t((RTL8367B_TA_CTRL_CMD_READ << RTL8367B_TA_CTRL_CMD_SHIFT) | \\\n\t\t RTL8367B_TA_CTRL_TABLE_CVLAN)\n#define   RTL8367B_TA_CTRL_CVLAN_WRITE \\\n\t\t((RTL8367B_TA_CTRL_CMD_WRITE << RTL8367B_TA_CTRL_CMD_SHIFT) | \\\n\t\t RTL8367B_TA_CTRL_TABLE_CVLAN)\n\n#define RTL8367B_TA_ADDR_REG\t\t\t0x0501/*GOOD*/\n#define   RTL8367B_TA_ADDR_MASK\t\t\t0x3fff/*GOOD*/\n\n#define RTL8367B_TA_LUT_REG\t\t\t0x0502/*GOOD*/\n\n#define RTL8367B_TA_WRDATA_REG(_x)\t\t(0x0510 + (_x))/*GOOD*/\n#define   RTL8367B_TA_VLAN_NUM_WORDS\t\t2\n#define   RTL8367B_TA_VLAN_VID_MASK\t\tRTL8367B_VID_MASK\n#define   RTL8367B_TA_VLAN0_MEMBER_SHIFT\t0\n#define   RTL8367B_TA_VLAN0_MEMBER_MASK\t\tRTL8367B_MEMBER_MASK\n#define   RTL8367B_TA_VLAN0_UNTAG_SHIFT\t\t8\n#define   RTL8367B_TA_VLAN0_UNTAG_MASK\t\tRTL8367B_MEMBER_MASK\n#define   RTL8367B_TA_VLAN1_FID_SHIFT\t\t0\n#define   RTL8367B_TA_VLAN1_FID_MASK\t\tRTL8367B_FID_MASK\n\n#define RTL8367B_TA_RDDATA_REG(_x)\t\t(0x0520 + (_x))/*GOOD*/\n\n#define RTL8367B_VLAN_PVID_CTRL_REG(_p)\t\t(0x0700 + (_p) / 2) /*GOOD*/\n#define RTL8367B_VLAN_PVID_CTRL_MASK\t\t0x1f /*GOOD*/\n#define RTL8367B_VLAN_PVID_CTRL_SHIFT(_p)\t(8 * ((_p) % 2)) /*GOOD*/\n\n#define RTL8367B_VLAN_MC_BASE(_x)\t\t(0x0728 + (_x) * 4) /*GOOD*/\n#define   RTL8367B_VLAN_MC_NUM_WORDS\t\t4 /*GOOD*/\n#define   RTL8367B_VLAN_MC0_MEMBER_SHIFT\t0/*GOOD*/\n#define   RTL8367B_VLAN_MC0_MEMBER_MASK\t\tRTL8367B_MEMBER_MASK/*GOOD*/\n#define   RTL8367B_VLAN_MC1_FID_SHIFT\t\t0/*GOOD*/\n#define   RTL8367B_VLAN_MC1_FID_MASK\t\tRTL8367B_FID_MASK/*GOOD*/\n#define   RTL8367B_VLAN_MC3_EVID_SHIFT\t\t0/*GOOD*/\n#define   RTL8367B_VLAN_MC3_EVID_MASK\t\tRTL8367B_VID_MASK/*GOOD*/\n\n#define RTL8367B_VLAN_CTRL_REG\t\t\t0x07a8 /*GOOD*/\n#define   RTL8367B_VLAN_CTRL_ENABLE\t\tBIT(0)\n\n#define RTL8367B_VLAN_INGRESS_REG\t\t0x07a9 /*GOOD*/\n\n#define RTL8367B_PORT_ISOLATION_REG(_p)\t\t(0x08a2 + (_p)) /*GOOD*/\n\n#define RTL8367B_MIB_COUNTER_REG(_x)\t\t(0x1000 + (_x))\t/*GOOD*/\n#define RTL8367B_MIB_COUNTER_PORT_OFFSET\t0x007c /*GOOD*/\n\n#define RTL8367B_MIB_ADDRESS_REG\t\t0x1004 /*GOOD*/\n\n#define RTL8367B_MIB_CTRL0_REG(_x)\t\t(0x1005 + (_x)) /*GOOD*/\n#define   RTL8367B_MIB_CTRL0_GLOBAL_RESET_MASK\tBIT(11)\t/*GOOD*/\n#define   RTL8367B_MIB_CTRL0_QM_RESET_MASK\tBIT(10) /*GOOD*/\n#define   RTL8367B_MIB_CTRL0_PORT_RESET_MASK(_p) BIT(2 + (_p)) /*GOOD*/\n#define   RTL8367B_MIB_CTRL0_RESET_MASK\t\tBIT(1) /*GOOD*/\n#define   RTL8367B_MIB_CTRL0_BUSY_MASK\t\tBIT(0) /*GOOD*/\n\n#define RTL8367B_SWC0_REG\t\t\t0x1200/*GOOD*/\n#define   RTL8367B_SWC0_MAX_LENGTH_SHIFT\t13/*GOOD*/\n#define   RTL8367B_SWC0_MAX_LENGTH(_x)\t\t((_x) << 13) /*GOOD*/\n#define   RTL8367B_SWC0_MAX_LENGTH_MASK\t\tRTL8367B_SWC0_MAX_LENGTH(0x3)\n#define   RTL8367B_SWC0_MAX_LENGTH_1522\t\tRTL8367B_SWC0_MAX_LENGTH(0)\n#define   RTL8367B_SWC0_MAX_LENGTH_1536\t\tRTL8367B_SWC0_MAX_LENGTH(1)\n#define   RTL8367B_SWC0_MAX_LENGTH_1552\t\tRTL8367B_SWC0_MAX_LENGTH(2)\n#define   RTL8367B_SWC0_MAX_LENGTH_16000\tRTL8367B_SWC0_MAX_LENGTH(3)\n\n#define RTL8367B_CHIP_NUMBER_REG\t\t0x1300/*GOOD*/\n\n#define RTL8367B_CHIP_VER_REG\t\t\t0x1301/*GOOD*/\n#define   RTL8367B_CHIP_VER_RLVID_SHIFT\t\t12/*GOOD*/\n#define   RTL8367B_CHIP_VER_RLVID_MASK\t\t0xf/*GOOD*/\n#define   RTL8367B_CHIP_VER_MCID_SHIFT\t\t8/*GOOD*/\n#define   RTL8367B_CHIP_VER_MCID_MASK\t\t0xf/*GOOD*/\n#define   RTL8367B_CHIP_VER_BOID_SHIFT\t\t4/*GOOD*/\n#define   RTL8367B_CHIP_VER_BOID_MASK\t\t0xf/*GOOD*/\n#define   RTL8367B_CHIP_VER_AFE_SHIFT\t\t0/*GOOD*/\n#define   RTL8367B_CHIP_VER_AFE_MASK\t\t0x1/*GOOD*/\n\n#define RTL8367B_CHIP_MODE_REG\t\t\t0x1302\n#define   RTL8367B_CHIP_MODE_MASK\t\t0x7\n\n#define RTL8367B_CHIP_DEBUG0_REG\t\t0x1303\n#define   RTL8367B_DEBUG0_SEL33(_x)\t\tBIT(8 + (_x))\n#define   RTL8367B_DEBUG0_DRI_OTHER\t\tBIT(7)\n#define   RTL8367B_DEBUG0_DRI_RG(_x)\t\tBIT(5 + (_x))\n#define   RTL8367B_DEBUG0_DRI(_x)\t\tBIT(3 + (_x))\n#define   RTL8367B_DEBUG0_SLR_OTHER\t\tBIT(2)\n#define   RTL8367B_DEBUG0_SLR(_x)\t\tBIT(_x)\n\n#define RTL8367B_CHIP_DEBUG1_REG\t\t0x1304\n#define   RTL8367B_DEBUG1_DN_MASK(_x)\t\t\\\n\t    GENMASK(6 + (_x)*8, 4 + (_x)*8)\n#define   RTL8367B_DEBUG1_DN_SHIFT(_x)\t\t(4 + (_x) * 8)\n#define   RTL8367B_DEBUG1_DP_MASK(_x)\t\t\\\n\t    GENMASK(2 + (_x) * 8, (_x) * 8)\n#define   RTL8367B_DEBUG1_DP_SHIFT(_x)\t\t((_x) * 8)\n\n#define RTL8367B_CHIP_DEBUG2_REG\t\t0x13e2\n#define   RTL8367B_DEBUG2_RG2_DN_MASK\t\tGENMASK(8, 6)\n#define   RTL8367B_DEBUG2_RG2_DN_SHIFT\t\t6\n#define   RTL8367B_DEBUG2_RG2_DP_MASK\t\tGENMASK(5, 3)\n#define   RTL8367B_DEBUG2_RG2_DP_SHIFT\t\t3\n#define   RTL8367B_DEBUG2_DRI_EXT2_RG\t\tBIT(2)\n#define   RTL8367B_DEBUG2_DRI_EXT2\t\tBIT(1)\n#define   RTL8367B_DEBUG2_SLR_EXT2\t\tBIT(0)\n\n#define RTL8367B_DIS_REG\t\t\t0x1305\n#define   RTL8367B_DIS_SKIP_MII_RXER(_x)\tBIT(12 + (_x))\n#define   RTL8367B_DIS_RGMII_SHIFT(_x)\t\t(4 * (_x))\n#define   RTL8367B_DIS_RGMII_MASK\t\t0x7\n\n#define RTL8367B_DIS2_REG\t\t\t0x13c3\n#define   RTL8367B_DIS2_SKIP_MII_RXER_SHIFT\t4\n#define   RTL8367B_DIS2_SKIP_MII_RXER\t\t0x10\n#define   RTL8367B_DIS2_RGMII_SHIFT\t\t0\n#define   RTL8367B_DIS2_RGMII_MASK\t\t0xf\n\n#define RTL8367B_EXT_RGMXF_REG(_x)\t\t\\\n\t  ((_x) == 2 ? 0x13c5 : 0x1306 + (_x))\n#define   RTL8367B_EXT_RGMXF_DUMMY0_SHIFT\t5\n#define   RTL8367B_EXT_RGMXF_DUMMY0_MASK\t0x7ff\n#define   RTL8367B_EXT_RGMXF_TXDELAY_SHIFT\t3\n#define   RTL8367B_EXT_RGMXF_TXDELAY_MASK\t1\n#define   RTL8367B_EXT_RGMXF_RXDELAY_MASK\t0x7\n\n#define RTL8367B_DI_FORCE_REG(_x)\t\t\\\n\t  ((_x) == 2 ? 0x13c4 : 0x1310 + (_x))\n#define   RTL8367B_DI_FORCE_MODE\t\tBIT(12)\n#define   RTL8367B_DI_FORCE_NWAY\t\tBIT(7)\n#define   RTL8367B_DI_FORCE_TXPAUSE\t\tBIT(6)\n#define   RTL8367B_DI_FORCE_RXPAUSE\t\tBIT(5)\n#define   RTL8367B_DI_FORCE_LINK\t\tBIT(4)\n#define   RTL8367B_DI_FORCE_DUPLEX\t\tBIT(2)\n#define   RTL8367B_DI_FORCE_SPEED_MASK\t\t3\n#define   RTL8367B_DI_FORCE_SPEED_10\t\t0\n#define   RTL8367B_DI_FORCE_SPEED_100\t\t1\n#define   RTL8367B_DI_FORCE_SPEED_1000\t\t2\n\n#define RTL8367B_MAC_FORCE_REG(_x)\t\t(0x1312 + (_x))\n\n#define RTL8367B_CHIP_RESET_REG\t\t\t0x1322 /*GOOD*/\n#define   RTL8367B_CHIP_RESET_SW\t\tBIT(1) /*GOOD*/\n#define   RTL8367B_CHIP_RESET_HW\t\tBIT(0) /*GOOD*/\n\n#define RTL8367B_PORT_STATUS_REG(_p)\t\t(0x1352 + (_p)) /*GOOD*/\n#define   RTL8367B_PORT_STATUS_EN_1000_SPI\tBIT(11) /*GOOD*/\n#define   RTL8367B_PORT_STATUS_EN_100_SPI\tBIT(10)/*GOOD*/\n#define   RTL8367B_PORT_STATUS_NWAY_FAULT\tBIT(9)/*GOOD*/\n#define   RTL8367B_PORT_STATUS_LINK_MASTER\tBIT(8)/*GOOD*/\n#define   RTL8367B_PORT_STATUS_NWAY\t\tBIT(7)/*GOOD*/\n#define   RTL8367B_PORT_STATUS_TXPAUSE\t\tBIT(6)/*GOOD*/\n#define   RTL8367B_PORT_STATUS_RXPAUSE\t\tBIT(5)/*GOOD*/\n#define   RTL8367B_PORT_STATUS_LINK\t\tBIT(4)/*GOOD*/\n#define   RTL8367B_PORT_STATUS_DUPLEX\t\tBIT(2)/*GOOD*/\n#define   RTL8367B_PORT_STATUS_SPEED_MASK\t0x0003/*GOOD*/\n#define   RTL8367B_PORT_STATUS_SPEED_10\t\t0/*GOOD*/\n#define   RTL8367B_PORT_STATUS_SPEED_100\t1/*GOOD*/\n#define   RTL8367B_PORT_STATUS_SPEED_1000\t2/*GOOD*/\n\n#define RTL8367B_RTL_MAGIC_ID_REG\t\t0x13c2\n#define   RTL8367B_RTL_MAGIC_ID_VAL\t\t0x0249\n\n#define RTL8367B_IA_CTRL_REG\t\t\t0x1f00\n#define   RTL8367B_IA_CTRL_RW(_x)\t\t((_x) << 1)\n#define   RTL8367B_IA_CTRL_RW_READ\t\tRTL8367B_IA_CTRL_RW(0)\n#define   RTL8367B_IA_CTRL_RW_WRITE\t\tRTL8367B_IA_CTRL_RW(1)\n#define   RTL8367B_IA_CTRL_CMD_MASK\t\tBIT(0)\n\n#define RTL8367B_IA_STATUS_REG\t\t\t0x1f01\n#define   RTL8367B_IA_STATUS_PHY_BUSY\t\tBIT(2)\n#define   RTL8367B_IA_STATUS_SDS_BUSY\t\tBIT(1)\n#define   RTL8367B_IA_STATUS_MDX_BUSY\t\tBIT(0)\n\n#define RTL8367B_IA_ADDRESS_REG\t\t\t0x1f02\n#define RTL8367B_IA_WRITE_DATA_REG\t\t0x1f03\n#define RTL8367B_IA_READ_DATA_REG\t\t0x1f04\n\n#define RTL8367B_INTERNAL_PHY_REG(_a, _r)\t(0x2000 + 32 * (_a) + (_r))\n\n#define RTL8367B_NUM_MIB_COUNTERS\t58\n\n#define RTL8367B_CPU_PORT_NUM\t\t5\n#define RTL8367B_NUM_PORTS\t\t8\n#define RTL8367B_NUM_VLANS\t\t32\n#define RTL8367B_NUM_VIDS\t\t4096\n#define RTL8367B_PRIORITYMAX\t\t7\n#define RTL8367B_FIDMAX\t\t\t7\n\n#define RTL8367B_PORT_0\t\t\tBIT(0)\n#define RTL8367B_PORT_1\t\t\tBIT(1)\n#define RTL8367B_PORT_2\t\t\tBIT(2)\n#define RTL8367B_PORT_3\t\t\tBIT(3)\n#define RTL8367B_PORT_4\t\t\tBIT(4)\n#define RTL8367B_PORT_E0\t\tBIT(5)\t/* External port 0 */\n#define RTL8367B_PORT_E1\t\tBIT(6)\t/* External port 1 */\n#define RTL8367B_PORT_E2\t\tBIT(7)\t/* External port 2 */\n\n#define RTL8367B_PORTS_ALL\t\t\t\t\t\\\n\t(RTL8367B_PORT_0 | RTL8367B_PORT_1 | RTL8367B_PORT_2 |\t\\\n\t RTL8367B_PORT_3 | RTL8367B_PORT_4 | RTL8367B_PORT_E0 | \\\n\t RTL8367B_PORT_E1 | RTL8367B_PORT_E2)\n\n#define RTL8367B_PORTS_ALL_BUT_CPU\t\t\t\t\\\n\t(RTL8367B_PORT_0 | RTL8367B_PORT_1 | RTL8367B_PORT_2 |\t\\\n\t RTL8367B_PORT_3 | RTL8367B_PORT_4 | RTL8367B_PORT_E1 |\t\\\n\t RTL8367B_PORT_E2)\n\nstruct rtl8367b_initval {\n\tu16 reg;\n\tu16 val;\n};\n\n#define RTL8367B_MIB_RXB_ID\t\t0\t/* IfInOctets */\n#define RTL8367B_MIB_TXB_ID\t\t28\t/* IfOutOctets */\n\nstatic struct rtl8366_mib_counter\nrtl8367b_mib_counters[RTL8367B_NUM_MIB_COUNTERS] = {\n\t{0,   0, 4, \"ifInOctets\"\t\t\t},\n\t{0,   4, 2, \"dot3StatsFCSErrors\"\t\t},\n\t{0,   6, 2, \"dot3StatsSymbolErrors\"\t\t},\n\t{0,   8, 2, \"dot3InPauseFrames\"\t\t\t},\n\t{0,  10, 2, \"dot3ControlInUnknownOpcodes\"\t},\n\t{0,  12, 2, \"etherStatsFragments\"\t\t},\n\t{0,  14, 2, \"etherStatsJabbers\"\t\t\t},\n\t{0,  16, 2, \"ifInUcastPkts\"\t\t\t},\n\t{0,  18, 2, \"etherStatsDropEvents\"\t\t},\n\t{0,  20, 2, \"ifInMulticastPkts\"\t\t\t},\n\t{0,  22, 2, \"ifInBroadcastPkts\"\t\t\t},\n\t{0,  24, 2, \"inMldChecksumError\"\t\t},\n\t{0,  26, 2, \"inIgmpChecksumError\"\t\t},\n\t{0,  28, 2, \"inMldSpecificQuery\"\t\t},\n\t{0,  30, 2, \"inMldGeneralQuery\"\t\t\t},\n\t{0,  32, 2, \"inIgmpSpecificQuery\"\t\t},\n\t{0,  34, 2, \"inIgmpGeneralQuery\"\t\t},\n\t{0,  36, 2, \"inMldLeaves\"\t\t\t},\n\t{0,  38, 2, \"inIgmpLeaves\"\t\t\t},\n\n\t{0,  40, 4, \"etherStatsOctets\"\t\t\t},\n\t{0,  44, 2, \"etherStatsUnderSizePkts\"\t\t},\n\t{0,  46, 2, \"etherOversizeStats\"\t\t},\n\t{0,  48, 2, \"etherStatsPkts64Octets\"\t\t},\n\t{0,  50, 2, \"etherStatsPkts65to127Octets\"\t},\n\t{0,  52, 2, \"etherStatsPkts128to255Octets\"\t},\n\t{0,  54, 2, \"etherStatsPkts256to511Octets\"\t},\n\t{0,  56, 2, \"etherStatsPkts512to1023Octets\"\t},\n\t{0,  58, 2, \"etherStatsPkts1024to1518Octets\"\t},\n\n\t{0,  60, 4, \"ifOutOctets\"\t\t\t},\n\t{0,  64, 2, \"dot3StatsSingleCollisionFrames\"\t},\n\t{0,  66, 2, \"dot3StatMultipleCollisionFrames\"\t},\n\t{0,  68, 2, \"dot3sDeferredTransmissions\"\t},\n\t{0,  70, 2, \"dot3StatsLateCollisions\"\t\t},\n\t{0,  72, 2, \"etherStatsCollisions\"\t\t},\n\t{0,  74, 2, \"dot3StatsExcessiveCollisions\"\t},\n\t{0,  76, 2, \"dot3OutPauseFrames\"\t\t},\n\t{0,  78, 2, \"ifOutDiscards\"\t\t\t},\n\t{0,  80, 2, \"dot1dTpPortInDiscards\"\t\t},\n\t{0,  82, 2, \"ifOutUcastPkts\"\t\t\t},\n\t{0,  84, 2, \"ifOutMulticastPkts\"\t\t},\n\t{0,  86, 2, \"ifOutBroadcastPkts\"\t\t},\n\t{0,  88, 2, \"outOampduPkts\"\t\t\t},\n\t{0,  90, 2, \"inOampduPkts\"\t\t\t},\n\t{0,  92, 2, \"inIgmpJoinsSuccess\"\t\t},\n\t{0,  94, 2, \"inIgmpJoinsFail\"\t\t\t},\n\t{0,  96, 2, \"inMldJoinsSuccess\"\t\t\t},\n\t{0,  98, 2, \"inMldJoinsFail\"\t\t\t},\n\t{0, 100, 2, \"inReportSuppressionDrop\"\t\t},\n\t{0, 102, 2, \"inLeaveSuppressionDrop\"\t\t},\n\t{0, 104, 2, \"outIgmpReports\"\t\t\t},\n\t{0, 106, 2, \"outIgmpLeaves\"\t\t\t},\n\t{0, 108, 2, \"outIgmpGeneralQuery\"\t\t},\n\t{0, 110, 2, \"outIgmpSpecificQuery\"\t\t},\n\t{0, 112, 2, \"outMldReports\"\t\t\t},\n\t{0, 114, 2, \"outMldLeaves\"\t\t\t},\n\t{0, 116, 2, \"outMldGeneralQuery\"\t\t},\n\t{0, 118, 2, \"outMldSpecificQuery\"\t\t},\n\t{0, 120, 2, \"inKnownMulticastPkts\"\t\t},\n};\n\n#define REG_RD(_smi, _reg, _val)\t\t\t\t\t\\\n\tdo {\t\t\t\t\t\t\t\t\\\n\t\terr = rtl8366_smi_read_reg(_smi, _reg, _val);\t\t\\\n\t\tif (err)\t\t\t\t\t\t\\\n\t\t\treturn err;\t\t\t\t\t\\\n\t} while (0)\n\n#define REG_WR(_smi, _reg, _val)\t\t\t\t\t\\\n\tdo {\t\t\t\t\t\t\t\t\\\n\t\terr = rtl8366_smi_write_reg(_smi, _reg, _val);\t\t\\\n\t\tif (err)\t\t\t\t\t\t\\\n\t\t\treturn err;\t\t\t\t\t\\\n\t} while (0)\n\n#define REG_RMW(_smi, _reg, _mask, _val)\t\t\t\t\\\n\tdo {\t\t\t\t\t\t\t\t\\\n\t\terr = rtl8366_smi_rmwr(_smi, _reg, _mask, _val);\t\\\n\t\tif (err)\t\t\t\t\t\t\\\n\t\t\treturn err;\t\t\t\t\t\\\n\t} while (0)\n\nstatic const struct rtl8367b_initval rtl8367r_vb_initvals_0[] = {\n\t{0x1B03, 0x0876}, {0x1200, 0x7FC4}, {0x0301, 0x0026}, {0x1722, 0x0E14},\n\t{0x205F, 0x0002}, {0x2059, 0x1A00}, {0x205F, 0x0000}, {0x207F, 0x0002},\n\t{0x2077, 0x0000}, {0x2078, 0x0000}, {0x2079, 0x0000}, {0x207A, 0x0000},\n\t{0x207B, 0x0000}, {0x207F, 0x0000}, {0x205F, 0x0002}, {0x2053, 0x0000},\n\t{0x2054, 0x0000}, {0x2055, 0x0000}, {0x2056, 0x0000}, {0x2057, 0x0000},\n\t{0x205F, 0x0000}, {0x12A4, 0x110A}, {0x12A6, 0x150A}, {0x13F1, 0x0013},\n\t{0x13F4, 0x0010}, {0x13F5, 0x0000}, {0x0018, 0x0F00}, {0x0038, 0x0F00},\n\t{0x0058, 0x0F00}, {0x0078, 0x0F00}, {0x0098, 0x0F00}, {0x12B6, 0x0C02},\n\t{0x12B7, 0x030F}, {0x12B8, 0x11FF}, {0x12BC, 0x0004}, {0x1362, 0x0115},\n\t{0x1363, 0x0002}, {0x1363, 0x0000}, {0x133F, 0x0030}, {0x133E, 0x000E},\n\t{0x221F, 0x0007}, {0x221E, 0x002D}, {0x2218, 0xF030}, {0x221F, 0x0007},\n\t{0x221E, 0x0023}, {0x2216, 0x0005}, {0x2215, 0x00B9}, {0x2219, 0x0044},\n\t{0x2215, 0x00BA}, {0x2219, 0x0020}, {0x2215, 0x00BB}, {0x2219, 0x00C1},\n\t{0x2215, 0x0148}, {0x2219, 0x0096}, {0x2215, 0x016E}, {0x2219, 0x0026},\n\t{0x2216, 0x0000}, {0x2216, 0x0000}, {0x221E, 0x002D}, {0x2218, 0xF010},\n\t{0x221F, 0x0007}, {0x221E, 0x0020}, {0x2215, 0x0D00}, {0x221F, 0x0000},\n\t{0x221F, 0x0000}, {0x2217, 0x2160}, {0x221F, 0x0001}, {0x2210, 0xF25E},\n\t{0x221F, 0x0007}, {0x221E, 0x0042}, {0x2215, 0x0F00}, {0x2215, 0x0F00},\n\t{0x2216, 0x7408}, {0x2215, 0x0E00}, {0x2215, 0x0F00}, {0x2215, 0x0F01},\n\t{0x2216, 0x4000}, {0x2215, 0x0E01}, {0x2215, 0x0F01}, {0x2215, 0x0F02},\n\t{0x2216, 0x9400}, {0x2215, 0x0E02}, {0x2215, 0x0F02}, {0x2215, 0x0F03},\n\t{0x2216, 0x7408}, {0x2215, 0x0E03}, {0x2215, 0x0F03}, {0x2215, 0x0F04},\n\t{0x2216, 0x4008}, {0x2215, 0x0E04}, {0x2215, 0x0F04}, {0x2215, 0x0F05},\n\t{0x2216, 0x9400}, {0x2215, 0x0E05}, {0x2215, 0x0F05}, {0x2215, 0x0F06},\n\t{0x2216, 0x0803}, {0x2215, 0x0E06}, {0x2215, 0x0F06}, {0x2215, 0x0D00},\n\t{0x2215, 0x0100}, {0x221F, 0x0001}, {0x2210, 0xF05E}, {0x221F, 0x0000},\n\t{0x2217, 0x2100}, {0x221F, 0x0000}, {0x220D, 0x0003}, {0x220E, 0x0015},\n\t{0x220D, 0x4003}, {0x220E, 0x0006}, {0x221F, 0x0000}, {0x2200, 0x1340},\n\t{0x133F, 0x0010}, {0x12A0, 0x0058}, {0x12A1, 0x0058}, {0x133E, 0x000E},\n\t{0x133F, 0x0030}, {0x221F, 0x0000}, {0x2210, 0x0166}, {0x221F, 0x0000},\n\t{0x133E, 0x000E}, {0x133F, 0x0010}, {0x133F, 0x0030}, {0x133E, 0x000E},\n\t{0x221F, 0x0005}, {0x2205, 0xFFF6}, {0x2206, 0x0080}, {0x2205, 0x8B6E},\n\t{0x2206, 0x0000}, {0x220F, 0x0100}, {0x2205, 0x8000}, {0x2206, 0x0280},\n\t{0x2206, 0x28F7}, {0x2206, 0x00E0}, {0x2206, 0xFFF7}, {0x2206, 0xA080},\n\t{0x2206, 0x02AE}, {0x2206, 0xF602}, {0x2206, 0x0153}, {0x2206, 0x0201},\n\t{0x2206, 0x6602}, {0x2206, 0x80B9}, {0x2206, 0xE08B}, {0x2206, 0x8CE1},\n\t{0x2206, 0x8B8D}, {0x2206, 0x1E01}, {0x2206, 0xE18B}, {0x2206, 0x8E1E},\n\t{0x2206, 0x01A0}, {0x2206, 0x00E7}, {0x2206, 0xAEDB}, {0x2206, 0xEEE0},\n\t{0x2206, 0x120E}, {0x2206, 0xEEE0}, {0x2206, 0x1300}, {0x2206, 0xEEE0},\n\t{0x2206, 0x2001}, {0x2206, 0xEEE0}, {0x2206, 0x2166}, {0x2206, 0xEEE0},\n\t{0x2206, 0xC463}, {0x2206, 0xEEE0}, {0x2206, 0xC5E8}, {0x2206, 0xEEE0},\n\t{0x2206, 0xC699}, {0x2206, 0xEEE0}, {0x2206, 0xC7C2}, {0x2206, 0xEEE0},\n\t{0x2206, 0xC801}, {0x2206, 0xEEE0}, {0x2206, 0xC913}, {0x2206, 0xEEE0},\n\t{0x2206, 0xCA30}, {0x2206, 0xEEE0}, {0x2206, 0xCB3E}, {0x2206, 0xEEE0},\n\t{0x2206, 0xDCE1}, {0x2206, 0xEEE0}, {0x2206, 0xDD00}, {0x2206, 0xEEE2},\n\t{0x2206, 0x0001}, {0x2206, 0xEEE2}, {0x2206, 0x0100}, {0x2206, 0xEEE4},\n\t{0x2206, 0x8860}, {0x2206, 0xEEE4}, {0x2206, 0x8902}, {0x2206, 0xEEE4},\n\t{0x2206, 0x8C00}, {0x2206, 0xEEE4}, {0x2206, 0x8D30}, {0x2206, 0xEEEA},\n\t{0x2206, 0x1480}, {0x2206, 0xEEEA}, {0x2206, 0x1503}, {0x2206, 0xEEEA},\n\t{0x2206, 0xC600}, {0x2206, 0xEEEA}, {0x2206, 0xC706}, {0x2206, 0xEE85},\n\t{0x2206, 0xEE00}, {0x2206, 0xEE85}, {0x2206, 0xEF00}, {0x2206, 0xEE8B},\n\t{0x2206, 0x6750}, {0x2206, 0xEE8B}, {0x2206, 0x6632}, {0x2206, 0xEE8A},\n\t{0x2206, 0xD448}, {0x2206, 0xEE8A}, {0x2206, 0xD548}, {0x2206, 0xEE8A},\n\t{0x2206, 0xD649}, {0x2206, 0xEE8A}, {0x2206, 0xD7F8}, {0x2206, 0xEE8B},\n\t{0x2206, 0x85E2}, {0x2206, 0xEE8B}, {0x2206, 0x8700}, {0x2206, 0xEEFF},\n\t{0x2206, 0xF600}, {0x2206, 0xEEFF}, {0x2206, 0xF7FC}, {0x2206, 0x04F8},\n\t{0x2206, 0xE08B}, {0x2206, 0x8EAD}, {0x2206, 0x2023}, {0x2206, 0xF620},\n\t{0x2206, 0xE48B}, {0x2206, 0x8E02}, {0x2206, 0x2877}, {0x2206, 0x0225},\n\t{0x2206, 0xC702}, {0x2206, 0x26A1}, {0x2206, 0x0281}, {0x2206, 0xB302},\n\t{0x2206, 0x8496}, {0x2206, 0x0202}, {0x2206, 0xA102}, {0x2206, 0x27F1},\n\t{0x2206, 0x0228}, {0x2206, 0xF902}, {0x2206, 0x2AA0}, {0x2206, 0x0282},\n\t{0x2206, 0xB8E0}, {0x2206, 0x8B8E}, {0x2206, 0xAD21}, {0x2206, 0x08F6},\n\t{0x2206, 0x21E4}, {0x2206, 0x8B8E}, {0x2206, 0x0202}, {0x2206, 0x80E0},\n\t{0x2206, 0x8B8E}, {0x2206, 0xAD22}, {0x2206, 0x05F6}, {0x2206, 0x22E4},\n\t{0x2206, 0x8B8E}, {0x2206, 0xE08B}, {0x2206, 0x8EAD}, {0x2206, 0x2305},\n\t{0x2206, 0xF623}, {0x2206, 0xE48B}, {0x2206, 0x8EE0}, {0x2206, 0x8B8E},\n\t{0x2206, 0xAD24}, {0x2206, 0x08F6}, {0x2206, 0x24E4}, {0x2206, 0x8B8E},\n\t{0x2206, 0x0227}, {0x2206, 0x6AE0}, {0x2206, 0x8B8E}, {0x2206, 0xAD25},\n\t{0x2206, 0x05F6}, {0x2206, 0x25E4}, {0x2206, 0x8B8E}, {0x2206, 0xE08B},\n\t{0x2206, 0x8EAD}, {0x2206, 0x260B}, {0x2206, 0xF626}, {0x2206, 0xE48B},\n\t{0x2206, 0x8E02}, {0x2206, 0x830D}, {0x2206, 0x021D}, {0x2206, 0x6BE0},\n\t{0x2206, 0x8B8E}, {0x2206, 0xAD27}, {0x2206, 0x05F6}, {0x2206, 0x27E4},\n\t{0x2206, 0x8B8E}, {0x2206, 0x0281}, {0x2206, 0x4402}, {0x2206, 0x045C},\n\t{0x2206, 0xFC04}, {0x2206, 0xF8E0}, {0x2206, 0x8B83}, {0x2206, 0xAD23},\n\t{0x2206, 0x30E0}, {0x2206, 0xE022}, {0x2206, 0xE1E0}, {0x2206, 0x2359},\n\t{0x2206, 0x02E0}, {0x2206, 0x85EF}, {0x2206, 0xE585}, {0x2206, 0xEFAC},\n\t{0x2206, 0x2907}, {0x2206, 0x1F01}, {0x2206, 0x9E51}, {0x2206, 0xAD29},\n\t{0x2206, 0x20E0}, {0x2206, 0x8B83}, {0x2206, 0xAD21}, {0x2206, 0x06E1},\n\t{0x2206, 0x8B84}, {0x2206, 0xAD28}, {0x2206, 0x42E0}, {0x2206, 0x8B85},\n\t{0x2206, 0xAD21}, {0x2206, 0x06E1}, {0x2206, 0x8B84}, {0x2206, 0xAD29},\n\t{0x2206, 0x36BF}, {0x2206, 0x34BF}, {0x2206, 0x022C}, {0x2206, 0x31AE},\n\t{0x2206, 0x2EE0}, {0x2206, 0x8B83}, {0x2206, 0xAD21}, {0x2206, 0x10E0},\n\t{0x2206, 0x8B84}, {0x2206, 0xF620}, {0x2206, 0xE48B}, {0x2206, 0x84EE},\n\t{0x2206, 0x8ADA}, {0x2206, 0x00EE}, {0x2206, 0x8ADB}, {0x2206, 0x00E0},\n\t{0x2206, 0x8B85}, {0x2206, 0xAD21}, {0x2206, 0x0CE0}, {0x2206, 0x8B84},\n\t{0x2206, 0xF621}, {0x2206, 0xE48B}, {0x2206, 0x84EE}, {0x2206, 0x8B72},\n\t{0x2206, 0xFFBF}, {0x2206, 0x34C2}, {0x2206, 0x022C}, {0x2206, 0x31FC},\n\t{0x2206, 0x04F8}, {0x2206, 0xFAEF}, {0x2206, 0x69E0}, {0x2206, 0x8B85},\n\t{0x2206, 0xAD21}, {0x2206, 0x42E0}, {0x2206, 0xE022}, {0x2206, 0xE1E0},\n\t{0x2206, 0x2358}, {0x2206, 0xC059}, {0x2206, 0x021E}, {0x2206, 0x01E1},\n\t{0x2206, 0x8B72}, {0x2206, 0x1F10}, {0x2206, 0x9E2F}, {0x2206, 0xE48B},\n\t{0x2206, 0x72AD}, {0x2206, 0x2123}, {0x2206, 0xE18B}, {0x2206, 0x84F7},\n\t{0x2206, 0x29E5}, {0x2206, 0x8B84}, {0x2206, 0xAC27}, {0x2206, 0x10AC},\n\t{0x2206, 0x2605}, {0x2206, 0x0205}, {0x2206, 0x23AE}, {0x2206, 0x1602},\n\t{0x2206, 0x0535}, {0x2206, 0x0282}, {0x2206, 0x30AE}, {0x2206, 0x0E02},\n\t{0x2206, 0x056A}, {0x2206, 0x0282}, {0x2206, 0x75AE}, {0x2206, 0x0602},\n\t{0x2206, 0x04DC}, {0x2206, 0x0282}, {0x2206, 0x04EF}, {0x2206, 0x96FE},\n\t{0x2206, 0xFC04}, {0x2206, 0xF8F9}, {0x2206, 0xE08B}, {0x2206, 0x87AD},\n\t{0x2206, 0x2321}, {0x2206, 0xE0EA}, {0x2206, 0x14E1}, {0x2206, 0xEA15},\n\t{0x2206, 0xAD26}, {0x2206, 0x18F6}, {0x2206, 0x27E4}, {0x2206, 0xEA14},\n\t{0x2206, 0xE5EA}, {0x2206, 0x15F6}, {0x2206, 0x26E4}, {0x2206, 0xEA14},\n\t{0x2206, 0xE5EA}, {0x2206, 0x15F7}, {0x2206, 0x27E4}, {0x2206, 0xEA14},\n\t{0x2206, 0xE5EA}, {0x2206, 0x15FD}, {0x2206, 0xFC04}, {0x2206, 0xF8F9},\n\t{0x2206, 0xE08B}, {0x2206, 0x87AD}, {0x2206, 0x233A}, {0x2206, 0xAD22},\n\t{0x2206, 0x37E0}, {0x2206, 0xE020}, {0x2206, 0xE1E0}, {0x2206, 0x21AC},\n\t{0x2206, 0x212E}, {0x2206, 0xE0EA}, {0x2206, 0x14E1}, {0x2206, 0xEA15},\n\t{0x2206, 0xF627}, {0x2206, 0xE4EA}, {0x2206, 0x14E5}, {0x2206, 0xEA15},\n\t{0x2206, 0xE2EA}, {0x2206, 0x12E3}, {0x2206, 0xEA13}, {0x2206, 0x5A8F},\n\t{0x2206, 0x6A20}, {0x2206, 0xE6EA}, {0x2206, 0x12E7}, {0x2206, 0xEA13},\n\t{0x2206, 0xF726}, {0x2206, 0xE4EA}, {0x2206, 0x14E5}, {0x2206, 0xEA15},\n\t{0x2206, 0xF727}, {0x2206, 0xE4EA}, {0x2206, 0x14E5}, {0x2206, 0xEA15},\n\t{0x2206, 0xFDFC}, {0x2206, 0x04F8}, {0x2206, 0xF9E0}, {0x2206, 0x8B87},\n\t{0x2206, 0xAD23}, {0x2206, 0x38AD}, {0x2206, 0x2135}, {0x2206, 0xE0E0},\n\t{0x2206, 0x20E1}, {0x2206, 0xE021}, {0x2206, 0xAC21}, {0x2206, 0x2CE0},\n\t{0x2206, 0xEA14}, {0x2206, 0xE1EA}, {0x2206, 0x15F6}, {0x2206, 0x27E4},\n\t{0x2206, 0xEA14}, {0x2206, 0xE5EA}, {0x2206, 0x15E2}, {0x2206, 0xEA12},\n\t{0x2206, 0xE3EA}, {0x2206, 0x135A}, {0x2206, 0x8FE6}, {0x2206, 0xEA12},\n\t{0x2206, 0xE7EA}, {0x2206, 0x13F7}, {0x2206, 0x26E4}, {0x2206, 0xEA14},\n\t{0x2206, 0xE5EA}, {0x2206, 0x15F7}, {0x2206, 0x27E4}, {0x2206, 0xEA14},\n\t{0x2206, 0xE5EA}, {0x2206, 0x15FD}, {0x2206, 0xFC04}, {0x2206, 0xF8FA},\n\t{0x2206, 0xEF69}, {0x2206, 0xE08B}, {0x2206, 0x86AD}, {0x2206, 0x2146},\n\t{0x2206, 0xE0E0}, {0x2206, 0x22E1}, {0x2206, 0xE023}, {0x2206, 0x58C0},\n\t{0x2206, 0x5902}, {0x2206, 0x1E01}, {0x2206, 0xE18B}, {0x2206, 0x651F},\n\t{0x2206, 0x109E}, {0x2206, 0x33E4}, {0x2206, 0x8B65}, {0x2206, 0xAD21},\n\t{0x2206, 0x22AD}, {0x2206, 0x272A}, {0x2206, 0xD400}, {0x2206, 0x01BF},\n\t{0x2206, 0x34F2}, {0x2206, 0x022C}, {0x2206, 0xA2BF}, {0x2206, 0x34F5},\n\t{0x2206, 0x022C}, {0x2206, 0xE0E0}, {0x2206, 0x8B67}, {0x2206, 0x1B10},\n\t{0x2206, 0xAA14}, {0x2206, 0xE18B}, {0x2206, 0x660D}, {0x2206, 0x1459},\n\t{0x2206, 0x0FAE}, {0x2206, 0x05E1}, {0x2206, 0x8B66}, {0x2206, 0x590F},\n\t{0x2206, 0xBF85}, {0x2206, 0x6102}, {0x2206, 0x2CA2}, {0x2206, 0xEF96},\n\t{0x2206, 0xFEFC}, {0x2206, 0x04F8}, {0x2206, 0xF9FA}, {0x2206, 0xFBEF},\n\t{0x2206, 0x79E2}, {0x2206, 0x8AD2}, {0x2206, 0xAC19}, {0x2206, 0x2DE0},\n\t{0x2206, 0xE036}, {0x2206, 0xE1E0}, {0x2206, 0x37EF}, {0x2206, 0x311F},\n\t{0x2206, 0x325B}, {0x2206, 0x019E}, {0x2206, 0x1F7A}, {0x2206, 0x0159},\n\t{0x2206, 0x019F}, {0x2206, 0x0ABF}, {0x2206, 0x348E}, {0x2206, 0x022C},\n\t{0x2206, 0x31F6}, {0x2206, 0x06AE}, {0x2206, 0x0FF6}, {0x2206, 0x0302},\n\t{0x2206, 0x0470}, {0x2206, 0xF703}, {0x2206, 0xF706}, {0x2206, 0xBF34},\n\t{0x2206, 0x9302}, {0x2206, 0x2C31}, {0x2206, 0xAC1A}, {0x2206, 0x25E0},\n\t{0x2206, 0xE022}, {0x2206, 0xE1E0}, {0x2206, 0x23EF}, {0x2206, 0x300D},\n\t{0x2206, 0x311F}, {0x2206, 0x325B}, {0x2206, 0x029E}, {0x2206, 0x157A},\n\t{0x2206, 0x0258}, {0x2206, 0xC4A0}, {0x2206, 0x0408}, {0x2206, 0xBF34},\n\t{0x2206, 0x9E02}, {0x2206, 0x2C31}, {0x2206, 0xAE06}, {0x2206, 0xBF34},\n\t{0x2206, 0x9C02}, {0x2206, 0x2C31}, {0x2206, 0xAC1B}, {0x2206, 0x4AE0},\n\t{0x2206, 0xE012}, {0x2206, 0xE1E0}, {0x2206, 0x13EF}, {0x2206, 0x300D},\n\t{0x2206, 0x331F}, {0x2206, 0x325B}, {0x2206, 0x1C9E}, {0x2206, 0x3AEF},\n\t{0x2206, 0x325B}, {0x2206, 0x1C9F}, {0x2206, 0x09BF}, {0x2206, 0x3498},\n\t{0x2206, 0x022C}, {0x2206, 0x3102}, {0x2206, 0x83C5}, {0x2206, 0x5A03},\n\t{0x2206, 0x0D03}, {0x2206, 0x581C}, {0x2206, 0x1E20}, {0x2206, 0x0207},\n\t{0x2206, 0xA0A0}, {0x2206, 0x000E}, {0x2206, 0x0284}, {0x2206, 0x17AD},\n\t{0x2206, 0x1817}, {0x2206, 0xBF34}, {0x2206, 0x9A02}, {0x2206, 0x2C31},\n\t{0x2206, 0xAE0F}, {0x2206, 0xBF34}, {0x2206, 0xC802}, {0x2206, 0x2C31},\n\t{0x2206, 0xBF34}, {0x2206, 0xC502}, {0x2206, 0x2C31}, {0x2206, 0x0284},\n\t{0x2206, 0x52E6}, {0x2206, 0x8AD2}, {0x2206, 0xEF97}, {0x2206, 0xFFFE},\n\t{0x2206, 0xFDFC}, {0x2206, 0x04F8}, {0x2206, 0xBF34}, {0x2206, 0xDA02},\n\t{0x2206, 0x2CE0}, {0x2206, 0xE58A}, {0x2206, 0xD3BF}, {0x2206, 0x34D4},\n\t{0x2206, 0x022C}, {0x2206, 0xE00C}, {0x2206, 0x1159}, {0x2206, 0x02E0},\n\t{0x2206, 0x8AD3}, {0x2206, 0x1E01}, {0x2206, 0xE48A}, {0x2206, 0xD3D1},\n\t{0x2206, 0x00BF}, {0x2206, 0x34DA}, {0x2206, 0x022C}, {0x2206, 0xA2D1},\n\t{0x2206, 0x01BF}, {0x2206, 0x34D4}, {0x2206, 0x022C}, {0x2206, 0xA2BF},\n\t{0x2206, 0x34CB}, {0x2206, 0x022C}, {0x2206, 0xE0E5}, {0x2206, 0x8ACE},\n\t{0x2206, 0xBF85}, {0x2206, 0x6702}, {0x2206, 0x2CE0}, {0x2206, 0xE58A},\n\t{0x2206, 0xCFBF}, {0x2206, 0x8564}, {0x2206, 0x022C}, {0x2206, 0xE0E5},\n\t{0x2206, 0x8AD0}, {0x2206, 0xBF85}, {0x2206, 0x6A02}, {0x2206, 0x2CE0},\n\t{0x2206, 0xE58A}, {0x2206, 0xD1FC}, {0x2206, 0x04F8}, {0x2206, 0xE18A},\n\t{0x2206, 0xD1BF}, {0x2206, 0x856A}, {0x2206, 0x022C}, {0x2206, 0xA2E1},\n\t{0x2206, 0x8AD0}, {0x2206, 0xBF85}, {0x2206, 0x6402}, {0x2206, 0x2CA2},\n\t{0x2206, 0xE18A}, {0x2206, 0xCFBF}, {0x2206, 0x8567}, {0x2206, 0x022C},\n\t{0x2206, 0xA2E1}, {0x2206, 0x8ACE}, {0x2206, 0xBF34}, {0x2206, 0xCB02},\n\t{0x2206, 0x2CA2}, {0x2206, 0xE18A}, {0x2206, 0xD3BF}, {0x2206, 0x34DA},\n\t{0x2206, 0x022C}, {0x2206, 0xA2E1}, {0x2206, 0x8AD3}, {0x2206, 0x0D11},\n\t{0x2206, 0xBF34}, {0x2206, 0xD402}, {0x2206, 0x2CA2}, {0x2206, 0xFC04},\n\t{0x2206, 0xF9A0}, {0x2206, 0x0405}, {0x2206, 0xE38A}, {0x2206, 0xD4AE},\n\t{0x2206, 0x13A0}, {0x2206, 0x0805}, {0x2206, 0xE38A}, {0x2206, 0xD5AE},\n\t{0x2206, 0x0BA0}, {0x2206, 0x0C05}, {0x2206, 0xE38A}, {0x2206, 0xD6AE},\n\t{0x2206, 0x03E3}, {0x2206, 0x8AD7}, {0x2206, 0xEF13}, {0x2206, 0xBF34},\n\t{0x2206, 0xCB02}, {0x2206, 0x2CA2}, {0x2206, 0xEF13}, {0x2206, 0x0D11},\n\t{0x2206, 0xBF85}, {0x2206, 0x6702}, {0x2206, 0x2CA2}, {0x2206, 0xEF13},\n\t{0x2206, 0x0D14}, {0x2206, 0xBF85}, {0x2206, 0x6402}, {0x2206, 0x2CA2},\n\t{0x2206, 0xEF13}, {0x2206, 0x0D17}, {0x2206, 0xBF85}, {0x2206, 0x6A02},\n\t{0x2206, 0x2CA2}, {0x2206, 0xFD04}, {0x2206, 0xF8E0}, {0x2206, 0x8B85},\n\t{0x2206, 0xAD27}, {0x2206, 0x2DE0}, {0x2206, 0xE036}, {0x2206, 0xE1E0},\n\t{0x2206, 0x37E1}, {0x2206, 0x8B73}, {0x2206, 0x1F10}, {0x2206, 0x9E20},\n\t{0x2206, 0xE48B}, {0x2206, 0x73AC}, {0x2206, 0x200B}, {0x2206, 0xAC21},\n\t{0x2206, 0x0DAC}, {0x2206, 0x250F}, {0x2206, 0xAC27}, {0x2206, 0x0EAE},\n\t{0x2206, 0x0F02}, {0x2206, 0x84CC}, {0x2206, 0xAE0A}, {0x2206, 0x0284},\n\t{0x2206, 0xD1AE}, {0x2206, 0x05AE}, {0x2206, 0x0302}, {0x2206, 0x84D8},\n\t{0x2206, 0xFC04}, {0x2206, 0xEE8B}, {0x2206, 0x6800}, {0x2206, 0x0402},\n\t{0x2206, 0x84E5}, {0x2206, 0x0285}, {0x2206, 0x2804}, {0x2206, 0x0285},\n\t{0x2206, 0x4904}, {0x2206, 0xEE8B}, {0x2206, 0x6800}, {0x2206, 0xEE8B},\n\t{0x2206, 0x6902}, {0x2206, 0x04F8}, {0x2206, 0xF9E0}, {0x2206, 0x8B85},\n\t{0x2206, 0xAD26}, {0x2206, 0x38D0}, {0x2206, 0x0B02}, {0x2206, 0x2B4D},\n\t{0x2206, 0x5882}, {0x2206, 0x7882}, {0x2206, 0x9F2D}, {0x2206, 0xE08B},\n\t{0x2206, 0x68E1}, {0x2206, 0x8B69}, {0x2206, 0x1F10}, {0x2206, 0x9EC8},\n\t{0x2206, 0x10E4}, {0x2206, 0x8B68}, {0x2206, 0xE0E0}, {0x2206, 0x00E1},\n\t{0x2206, 0xE001}, {0x2206, 0xF727}, {0x2206, 0xE4E0}, {0x2206, 0x00E5},\n\t{0x2206, 0xE001}, {0x2206, 0xE2E0}, {0x2206, 0x20E3}, {0x2206, 0xE021},\n\t{0x2206, 0xAD30}, {0x2206, 0xF7F6}, {0x2206, 0x27E4}, {0x2206, 0xE000},\n\t{0x2206, 0xE5E0}, {0x2206, 0x01FD}, {0x2206, 0xFC04}, {0x2206, 0xF8FA},\n\t{0x2206, 0xEF69}, {0x2206, 0xE08B}, {0x2206, 0x86AD}, {0x2206, 0x2212},\n\t{0x2206, 0xE0E0}, {0x2206, 0x14E1}, {0x2206, 0xE015}, {0x2206, 0xAD26},\n\t{0x2206, 0x9CE1}, {0x2206, 0x85E0}, {0x2206, 0xBF85}, {0x2206, 0x6D02},\n\t{0x2206, 0x2CA2}, {0x2206, 0xEF96}, {0x2206, 0xFEFC}, {0x2206, 0x04F8},\n\t{0x2206, 0xFAEF}, {0x2206, 0x69E0}, {0x2206, 0x8B86}, {0x2206, 0xAD22},\n\t{0x2206, 0x09E1}, {0x2206, 0x85E1}, {0x2206, 0xBF85}, {0x2206, 0x6D02},\n\t{0x2206, 0x2CA2}, {0x2206, 0xEF96}, {0x2206, 0xFEFC}, {0x2206, 0x0464},\n\t{0x2206, 0xE48C}, {0x2206, 0xFDE4}, {0x2206, 0x80CA}, {0x2206, 0xE480},\n\t{0x2206, 0x66E0}, {0x2206, 0x8E70}, {0x2206, 0xE076}, {0x2205, 0xE142},\n\t{0x2206, 0x0701}, {0x2205, 0xE140}, {0x2206, 0x0405}, {0x220F, 0x0000},\n\t{0x221F, 0x0000}, {0x2200, 0x1340}, {0x133E, 0x000E}, {0x133F, 0x0010},\n\t{0x13EB, 0x11BB}\n};\n\nstatic const struct rtl8367b_initval rtl8367r_vb_initvals_1[] = {\n\t{0x1B03, 0x0876}, {0x1200, 0x7FC4}, {0x1305, 0xC000}, {0x121E, 0x03CA},\n\t{0x1233, 0x0352}, {0x1234, 0x0064}, {0x1237, 0x0096}, {0x1238, 0x0078},\n\t{0x1239, 0x0084}, {0x123A, 0x0030}, {0x205F, 0x0002}, {0x2059, 0x1A00},\n\t{0x205F, 0x0000}, {0x207F, 0x0002}, {0x2077, 0x0000}, {0x2078, 0x0000},\n\t{0x2079, 0x0000}, {0x207A, 0x0000}, {0x207B, 0x0000}, {0x207F, 0x0000},\n\t{0x205F, 0x0002}, {0x2053, 0x0000}, {0x2054, 0x0000}, {0x2055, 0x0000},\n\t{0x2056, 0x0000}, {0x2057, 0x0000}, {0x205F, 0x0000}, {0x133F, 0x0030},\n\t{0x133E, 0x000E}, {0x221F, 0x0005}, {0x2205, 0x8B86}, {0x2206, 0x800E},\n\t{0x221F, 0x0000}, {0x133F, 0x0010}, {0x12A3, 0x2200}, {0x6107, 0xE58B},\n\t{0x6103, 0xA970}, {0x0018, 0x0F00}, {0x0038, 0x0F00}, {0x0058, 0x0F00},\n\t{0x0078, 0x0F00}, {0x0098, 0x0F00}, {0x133F, 0x0030}, {0x133E, 0x000E},\n\t{0x221F, 0x0005}, {0x2205, 0x8B6E}, {0x2206, 0x0000}, {0x220F, 0x0100},\n\t{0x2205, 0xFFF6}, {0x2206, 0x0080}, {0x2205, 0x8000}, {0x2206, 0x0280},\n\t{0x2206, 0x2BF7}, {0x2206, 0x00E0}, {0x2206, 0xFFF7}, {0x2206, 0xA080},\n\t{0x2206, 0x02AE}, {0x2206, 0xF602}, {0x2206, 0x0153}, {0x2206, 0x0201},\n\t{0x2206, 0x6602}, {0x2206, 0x8044}, {0x2206, 0x0201}, {0x2206, 0x7CE0},\n\t{0x2206, 0x8B8C}, {0x2206, 0xE18B}, {0x2206, 0x8D1E}, {0x2206, 0x01E1},\n\t{0x2206, 0x8B8E}, {0x2206, 0x1E01}, {0x2206, 0xA000}, {0x2206, 0xE4AE},\n\t{0x2206, 0xD8EE}, {0x2206, 0x85C0}, {0x2206, 0x00EE}, {0x2206, 0x85C1},\n\t{0x2206, 0x00EE}, {0x2206, 0x8AFC}, {0x2206, 0x07EE}, {0x2206, 0x8AFD},\n\t{0x2206, 0x73EE}, {0x2206, 0xFFF6}, {0x2206, 0x00EE}, {0x2206, 0xFFF7},\n\t{0x2206, 0xFC04}, {0x2206, 0xF8E0}, {0x2206, 0x8B8E}, {0x2206, 0xAD20},\n\t{0x2206, 0x0302}, {0x2206, 0x8050}, {0x2206, 0xFC04}, {0x2206, 0xF8F9},\n\t{0x2206, 0xE08B}, {0x2206, 0x85AD}, {0x2206, 0x2548}, {0x2206, 0xE08A},\n\t{0x2206, 0xE4E1}, {0x2206, 0x8AE5}, {0x2206, 0x7C00}, {0x2206, 0x009E},\n\t{0x2206, 0x35EE}, {0x2206, 0x8AE4}, {0x2206, 0x00EE}, {0x2206, 0x8AE5},\n\t{0x2206, 0x00E0}, {0x2206, 0x8AFC}, {0x2206, 0xE18A}, {0x2206, 0xFDE2},\n\t{0x2206, 0x85C0}, {0x2206, 0xE385}, {0x2206, 0xC102}, {0x2206, 0x2DAC},\n\t{0x2206, 0xAD20}, {0x2206, 0x12EE}, {0x2206, 0x8AE4}, {0x2206, 0x03EE},\n\t{0x2206, 0x8AE5}, {0x2206, 0xB7EE}, {0x2206, 0x85C0}, {0x2206, 0x00EE},\n\t{0x2206, 0x85C1}, {0x2206, 0x00AE}, {0x2206, 0x1115}, {0x2206, 0xE685},\n\t{0x2206, 0xC0E7}, {0x2206, 0x85C1}, {0x2206, 0xAE08}, {0x2206, 0xEE85},\n\t{0x2206, 0xC000}, {0x2206, 0xEE85}, {0x2206, 0xC100}, {0x2206, 0xFDFC},\n\t{0x2206, 0x0400}, {0x2205, 0xE142}, {0x2206, 0x0701}, {0x2205, 0xE140},\n\t{0x2206, 0x0405}, {0x220F, 0x0000}, {0x221F, 0x0000}, {0x133E, 0x000E},\n\t{0x133F, 0x0010}, {0x13EB, 0x11BB}, {0x207F, 0x0002}, {0x2073, 0x1D22},\n\t{0x207F, 0x0000}, {0x133F, 0x0030}, {0x133E, 0x000E}, {0x2200, 0x1340},\n\t{0x133E, 0x000E}, {0x133F, 0x0010},\n};\n\nstatic int rtl8367b_write_initvals(struct rtl8366_smi *smi,\n\t\t\t\t  const struct rtl8367b_initval *initvals,\n\t\t\t\t  int count)\n{\n\tint err;\n\tint i;\n\n\tfor (i = 0; i < count; i++)\n\t\tREG_WR(smi, initvals[i].reg, initvals[i].val);\n\n\treturn 0;\n}\n\nstatic int rtl8367b_read_phy_reg(struct rtl8366_smi *smi,\n\t\t\t\tu32 phy_addr, u32 phy_reg, u32 *val)\n{\n\tint timeout;\n\tu32 data;\n\tint err;\n\n\tif (phy_addr > RTL8367B_PHY_ADDR_MAX)\n\t\treturn -EINVAL;\n\n\tif (phy_reg > RTL8367B_PHY_REG_MAX)\n\t\treturn -EINVAL;\n\n\tREG_RD(smi, RTL8367B_IA_STATUS_REG, &data);\n\tif (data & RTL8367B_IA_STATUS_PHY_BUSY)\n\t\treturn -ETIMEDOUT;\n\n\t/* prepare address */\n\tREG_WR(smi, RTL8367B_IA_ADDRESS_REG,\n\t       RTL8367B_INTERNAL_PHY_REG(phy_addr, phy_reg));\n\n\t/* send read command */\n\tREG_WR(smi, RTL8367B_IA_CTRL_REG,\n\t       RTL8367B_IA_CTRL_CMD_MASK | RTL8367B_IA_CTRL_RW_READ);\n\n\ttimeout = 5;\n\tdo {\n\t\tREG_RD(smi, RTL8367B_IA_STATUS_REG, &data);\n\t\tif ((data & RTL8367B_IA_STATUS_PHY_BUSY) == 0)\n\t\t\tbreak;\n\n\t\tif (timeout--) {\n\t\t\tdev_err(smi->parent, \"phy read timed out\\n\");\n\t\t\treturn -ETIMEDOUT;\n\t\t}\n\n\t\tudelay(1);\n\t} while (1);\n\n\t/* read data */\n\tREG_RD(smi, RTL8367B_IA_READ_DATA_REG, val);\n\n\tdev_dbg(smi->parent, \"phy_read: addr:%02x, reg:%02x, val:%04x\\n\",\n\t\tphy_addr, phy_reg, *val);\n\treturn 0;\n}\n\nstatic int rtl8367b_write_phy_reg(struct rtl8366_smi *smi,\n\t\t\t\t u32 phy_addr, u32 phy_reg, u32 val)\n{\n\tint timeout;\n\tu32 data;\n\tint err;\n\n\tdev_dbg(smi->parent, \"phy_write: addr:%02x, reg:%02x, val:%04x\\n\",\n\t\tphy_addr, phy_reg, val);\n\n\tif (phy_addr > RTL8367B_PHY_ADDR_MAX)\n\t\treturn -EINVAL;\n\n\tif (phy_reg > RTL8367B_PHY_REG_MAX)\n\t\treturn -EINVAL;\n\n\tREG_RD(smi, RTL8367B_IA_STATUS_REG, &data);\n\tif (data & RTL8367B_IA_STATUS_PHY_BUSY)\n\t\treturn -ETIMEDOUT;\n\n\t/* preapre data */\n\tREG_WR(smi, RTL8367B_IA_WRITE_DATA_REG, val);\n\n\t/* prepare address */\n\tREG_WR(smi, RTL8367B_IA_ADDRESS_REG,\n\t       RTL8367B_INTERNAL_PHY_REG(phy_addr, phy_reg));\n\n\t/* send write command */\n\tREG_WR(smi, RTL8367B_IA_CTRL_REG,\n\t       RTL8367B_IA_CTRL_CMD_MASK | RTL8367B_IA_CTRL_RW_WRITE);\n\n\ttimeout = 5;\n\tdo {\n\t\tREG_RD(smi, RTL8367B_IA_STATUS_REG, &data);\n\t\tif ((data & RTL8367B_IA_STATUS_PHY_BUSY) == 0)\n\t\t\tbreak;\n\n\t\tif (timeout--) {\n\t\t\tdev_err(smi->parent, \"phy write timed out\\n\");\n\t\t\treturn -ETIMEDOUT;\n\t\t}\n\n\t\tudelay(1);\n\t} while (1);\n\n\treturn 0;\n}\n\nstatic int rtl8367b_init_regs(struct rtl8366_smi *smi)\n{\n\tconst struct rtl8367b_initval *initvals;\n\tu32 chip_ver;\n\tu32 rlvid;\n\tint count;\n\tint err;\n\n\tREG_WR(smi, RTL8367B_RTL_MAGIC_ID_REG, RTL8367B_RTL_MAGIC_ID_VAL);\n\tREG_RD(smi, RTL8367B_CHIP_VER_REG, &chip_ver);\n\n\trlvid = (chip_ver >> RTL8367B_CHIP_VER_RLVID_SHIFT) &\n\t\tRTL8367B_CHIP_VER_RLVID_MASK;\n\n\tswitch (rlvid) {\n\tcase 0:\n\t\tinitvals = rtl8367r_vb_initvals_0;\n\t\tcount = ARRAY_SIZE(rtl8367r_vb_initvals_0);\n\t\tbreak;\n\n\tcase 1:\n\t\tinitvals = rtl8367r_vb_initvals_1;\n\t\tcount = ARRAY_SIZE(rtl8367r_vb_initvals_1);\n\t\tbreak;\n\n\tdefault:\n\t\tdev_err(smi->parent, \"unknow rlvid %u\\n\", rlvid);\n\t\treturn -ENODEV;\n\t}\n\n\t/* TODO: disable RLTP */\n\n\treturn rtl8367b_write_initvals(smi, initvals, count);\n}\n\nstatic int rtl8367b_reset_chip(struct rtl8366_smi *smi)\n{\n\tint timeout = 10;\n\tint err;\n\tu32 data;\n\n\tREG_WR(smi, RTL8367B_CHIP_RESET_REG, RTL8367B_CHIP_RESET_HW);\n\tmsleep(RTL8367B_RESET_DELAY);\n\n\tdo {\n\t\tREG_RD(smi, RTL8367B_CHIP_RESET_REG, &data);\n\t\tif (!(data & RTL8367B_CHIP_RESET_HW))\n\t\t\tbreak;\n\n\t\tmsleep(1);\n\t} while (--timeout);\n\n\tif (!timeout) {\n\t\tdev_err(smi->parent, \"chip reset timed out\\n\");\n\t\treturn -ETIMEDOUT;\n\t}\n\n\treturn 0;\n}\n\nstatic int rtl8367b_extif_set_mode(struct rtl8366_smi *smi, int id,\n\t\t\t\t   enum rtl8367_extif_mode mode)\n{\n\tint err;\n\n\t/* set port mode */\n\tswitch (mode) {\n\tcase RTL8367_EXTIF_MODE_RGMII:\n\t\tREG_RMW(smi, RTL8367B_CHIP_DEBUG0_REG,\n\t\t\tRTL8367B_DEBUG0_SEL33(id),\n\t\t\tRTL8367B_DEBUG0_SEL33(id));\n\t\tif (id <= 1) {\n\t\t\tREG_RMW(smi, RTL8367B_CHIP_DEBUG0_REG,\n\t\t\t\tRTL8367B_DEBUG0_DRI(id) |\n\t\t\t\t\tRTL8367B_DEBUG0_DRI_RG(id) |\n\t\t\t\t\tRTL8367B_DEBUG0_SLR(id),\n\t\t\t\tRTL8367B_DEBUG0_DRI_RG(id) |\n\t\t\t\t\tRTL8367B_DEBUG0_SLR(id));\n\t\t\tREG_RMW(smi, RTL8367B_CHIP_DEBUG1_REG,\n\t\t\t\tRTL8367B_DEBUG1_DN_MASK(id) |\n\t\t\t\t\tRTL8367B_DEBUG1_DP_MASK(id),\n\t\t\t\t(7 << RTL8367B_DEBUG1_DN_SHIFT(id)) |\n\t\t\t\t\t(7 << RTL8367B_DEBUG1_DP_SHIFT(id)));\n\t\t} else {\n\t\t\tREG_RMW(smi, RTL8367B_CHIP_DEBUG2_REG,\n\t\t\t\tRTL8367B_DEBUG2_DRI_EXT2 |\n\t\t\t\t\tRTL8367B_DEBUG2_DRI_EXT2_RG |\n\t\t\t\t\tRTL8367B_DEBUG2_SLR_EXT2 |\n\t\t\t\t\tRTL8367B_DEBUG2_RG2_DN_MASK |\n\t\t\t\t\tRTL8367B_DEBUG2_RG2_DP_MASK,\n\t\t\t\tRTL8367B_DEBUG2_DRI_EXT2_RG |\n\t\t\t\t\tRTL8367B_DEBUG2_SLR_EXT2 |\n\t\t\t\t\t(7 << RTL8367B_DEBUG2_RG2_DN_SHIFT) |\n\t\t\t\t\t(7 << RTL8367B_DEBUG2_RG2_DP_SHIFT));\n\t\t}\n\t\tbreak;\n\n\tcase RTL8367_EXTIF_MODE_TMII_MAC:\n\tcase RTL8367_EXTIF_MODE_TMII_PHY:\n\t\tREG_RMW(smi, RTL8367B_BYPASS_LINE_RATE_REG, BIT(id), BIT(id));\n\t\tbreak;\n\n\tcase RTL8367_EXTIF_MODE_GMII:\n\t\tREG_RMW(smi, RTL8367B_CHIP_DEBUG0_REG,\n\t\t\tRTL8367B_DEBUG0_SEL33(id),\n\t\t\tRTL8367B_DEBUG0_SEL33(id));\n\t\tREG_RMW(smi, RTL8367B_EXT_RGMXF_REG(id), BIT(6), BIT(6));\n\t\tbreak;\n\n\tcase RTL8367_EXTIF_MODE_MII_MAC:\n\tcase RTL8367_EXTIF_MODE_MII_PHY:\n\tcase RTL8367_EXTIF_MODE_DISABLED:\n\t\tREG_RMW(smi, RTL8367B_BYPASS_LINE_RATE_REG, BIT(id), 0);\n\t\tREG_RMW(smi, RTL8367B_EXT_RGMXF_REG(id), BIT(6), 0);\n\t\tbreak;\n\n\tdefault:\n\t\tdev_err(smi->parent,\n\t\t\t\"invalid mode for external interface %d\\n\", id);\n\t\treturn -EINVAL;\n\t}\n\n\tif (id <= 1)\n\t\tREG_RMW(smi, RTL8367B_DIS_REG,\n\t\t\tRTL8367B_DIS_RGMII_MASK << RTL8367B_DIS_RGMII_SHIFT(id),\n\t\t\tmode << RTL8367B_DIS_RGMII_SHIFT(id));\n\telse\n\t\tREG_RMW(smi, RTL8367B_DIS2_REG,\n\t\t\tRTL8367B_DIS2_RGMII_MASK << RTL8367B_DIS2_RGMII_SHIFT,\n\t\t\tmode << RTL8367B_DIS2_RGMII_SHIFT);\n\n\treturn 0;\n}\n\nstatic int rtl8367b_extif_set_force(struct rtl8366_smi *smi, int id,\n\t\t\t\t    struct rtl8367_port_ability *pa)\n{\n\tu32 mask;\n\tu32 val;\n\tint err;\n\n\tmask = (RTL8367B_DI_FORCE_MODE |\n\t\tRTL8367B_DI_FORCE_NWAY |\n\t\tRTL8367B_DI_FORCE_TXPAUSE |\n\t\tRTL8367B_DI_FORCE_RXPAUSE |\n\t\tRTL8367B_DI_FORCE_LINK |\n\t\tRTL8367B_DI_FORCE_DUPLEX |\n\t\tRTL8367B_DI_FORCE_SPEED_MASK);\n\n\tval = pa->speed;\n\tval |= pa->force_mode ? RTL8367B_DI_FORCE_MODE : 0;\n\tval |= pa->nway ? RTL8367B_DI_FORCE_NWAY : 0;\n\tval |= pa->txpause ? RTL8367B_DI_FORCE_TXPAUSE : 0;\n\tval |= pa->rxpause ? RTL8367B_DI_FORCE_RXPAUSE : 0;\n\tval |= pa->link ? RTL8367B_DI_FORCE_LINK : 0;\n\tval |= pa->duplex ? RTL8367B_DI_FORCE_DUPLEX : 0;\n\n\tREG_RMW(smi, RTL8367B_DI_FORCE_REG(id), mask, val);\n\n\treturn 0;\n}\n\nstatic int rtl8367b_extif_set_rgmii_delay(struct rtl8366_smi *smi, int id,\n\t\t\t\t\t unsigned txdelay, unsigned rxdelay)\n{\n\tu32 mask;\n\tu32 val;\n\tint err;\n\n\tmask = (RTL8367B_EXT_RGMXF_RXDELAY_MASK |\n\t\t(RTL8367B_EXT_RGMXF_TXDELAY_MASK <<\n\t\t\tRTL8367B_EXT_RGMXF_TXDELAY_SHIFT));\n\n\tval = rxdelay;\n\tval |= txdelay << RTL8367B_EXT_RGMXF_TXDELAY_SHIFT;\n\n\tREG_RMW(smi, RTL8367B_EXT_RGMXF_REG(id), mask, val);\n\n\treturn 0;\n}\n\nstatic int rtl8367b_extif_init(struct rtl8366_smi *smi, int id,\n\t\t\t       struct rtl8367_extif_config *cfg)\n{\n\tenum rtl8367_extif_mode mode;\n\tint err;\n\n\tmode = (cfg) ? cfg->mode : RTL8367_EXTIF_MODE_DISABLED;\n\n\terr = rtl8367b_extif_set_mode(smi, id, mode);\n\tif (err)\n\t\treturn err;\n\n\tif (mode != RTL8367_EXTIF_MODE_DISABLED) {\n\t\terr = rtl8367b_extif_set_force(smi, id, &cfg->ability);\n\t\tif (err)\n\t\t\treturn err;\n\n\t\terr = rtl8367b_extif_set_rgmii_delay(smi, id, cfg->txdelay,\n\t\t\t\t\t\t     cfg->rxdelay);\n\t\tif (err)\n\t\t\treturn err;\n\t}\n\n\treturn 0;\n}\n\n#ifdef CONFIG_OF\nstatic int rtl8367b_extif_init_of(struct rtl8366_smi *smi, int id,\n\t\t\t\t  const char *name)\n{\n\tstruct rtl8367_extif_config *cfg;\n\tconst __be32 *prop;\n\tint size;\n\tint err;\n\n\tprop = of_get_property(smi->parent->of_node, name, &size);\n\tif (!prop)\n\t\treturn rtl8367b_extif_init(smi, id, NULL);\n\n\tif (size != (9 * sizeof(*prop))) {\n\t\tdev_err(smi->parent, \"%s property is invalid\\n\", name);\n\t\treturn -EINVAL;\n\t}\n\n\tcfg = kzalloc(sizeof(struct rtl8367_extif_config), GFP_KERNEL);\n\tif (!cfg)\n\t\treturn -ENOMEM;\n\n\tcfg->txdelay = be32_to_cpup(prop++);\n\tcfg->rxdelay = be32_to_cpup(prop++);\n\tcfg->mode = be32_to_cpup(prop++);\n\tcfg->ability.force_mode = be32_to_cpup(prop++);\n\tcfg->ability.txpause = be32_to_cpup(prop++);\n\tcfg->ability.rxpause = be32_to_cpup(prop++);\n\tcfg->ability.link = be32_to_cpup(prop++);\n\tcfg->ability.duplex = be32_to_cpup(prop++);\n\tcfg->ability.speed = be32_to_cpup(prop++);\n\n\terr = rtl8367b_extif_init(smi, id, cfg);\n\tkfree(cfg);\n\n\treturn err;\n}\n#else\nstatic int rtl8367b_extif_init_of(struct rtl8366_smi *smi, int id,\n\t\t\t\t  const char *name)\n{\n\treturn -EINVAL;\n}\n#endif\n\nstatic int rtl8367b_setup(struct rtl8366_smi *smi)\n{\n\tstruct rtl8367_platform_data *pdata;\n\tint err;\n\tint i;\n\n\tpdata = smi->parent->platform_data;\n\n\terr = rtl8367b_init_regs(smi);\n\tif (err)\n\t\treturn err;\n\n\t/* initialize external interfaces */\n\tif (smi->parent->of_node) {\n\t\terr = rtl8367b_extif_init_of(smi, 0, \"realtek,extif0\");\n\t\tif (err)\n\t\t\treturn err;\n\n\t\terr = rtl8367b_extif_init_of(smi, 1, \"realtek,extif1\");\n\t\tif (err)\n\t\t\treturn err;\n\n\t\terr = rtl8367b_extif_init_of(smi, 2, \"realtek,extif2\");\n\t\tif (err)\n\t\t\treturn err;\n\t} else {\n\t\terr = rtl8367b_extif_init(smi, 0, pdata->extif0_cfg);\n\t\tif (err)\n\t\t\treturn err;\n\n\t\terr = rtl8367b_extif_init(smi, 1, pdata->extif1_cfg);\n\t\tif (err)\n\t\t\treturn err;\n\t}\n\n\t/* set maximum packet length to 1536 bytes */\n\tREG_RMW(smi, RTL8367B_SWC0_REG, RTL8367B_SWC0_MAX_LENGTH_MASK,\n\t\tRTL8367B_SWC0_MAX_LENGTH_1536);\n\n\t/*\n\t * discard VLAN tagged packets if the port is not a member of\n\t * the VLAN with which the packets is associated.\n\t */\n\tREG_WR(smi, RTL8367B_VLAN_INGRESS_REG, RTL8367B_PORTS_ALL);\n\n\t/*\n\t * Setup egress tag mode for each port.\n\t */\n\tfor (i = 0; i < RTL8367B_NUM_PORTS; i++)\n\t\tREG_RMW(smi,\n\t\t\tRTL8367B_PORT_MISC_CFG_REG(i),\n\t\t\tRTL8367B_PORT_MISC_CFG_EGRESS_MODE_MASK <<\n\t\t\t\tRTL8367B_PORT_MISC_CFG_EGRESS_MODE_SHIFT,\n\t\t\tRTL8367B_PORT_MISC_CFG_EGRESS_MODE_ORIGINAL <<\n\t\t\t\tRTL8367B_PORT_MISC_CFG_EGRESS_MODE_SHIFT);\n\n\treturn 0;\n}\n\nstatic int rtl8367b_get_mib_counter(struct rtl8366_smi *smi, int counter,\n\t\t\t\t    int port, unsigned long long *val)\n{\n\tstruct rtl8366_mib_counter *mib;\n\tint offset;\n\tint i;\n\tint err;\n\tu32 addr, data;\n\tu64 mibvalue;\n\n\tif (port > RTL8367B_NUM_PORTS ||\n\t    counter >= RTL8367B_NUM_MIB_COUNTERS)\n\t\treturn -EINVAL;\n\n\tmib = &rtl8367b_mib_counters[counter];\n\taddr = RTL8367B_MIB_COUNTER_PORT_OFFSET * port + mib->offset;\n\n\t/*\n\t * Writing access counter address first\n\t * then ASIC will prepare 64bits counter wait for being retrived\n\t */\n\tREG_WR(smi, RTL8367B_MIB_ADDRESS_REG, addr >> 2);\n\n\t/* read MIB control register */\n\tREG_RD(smi, RTL8367B_MIB_CTRL0_REG(0), &data);\n\n\tif (data & RTL8367B_MIB_CTRL0_BUSY_MASK)\n\t\treturn -EBUSY;\n\n\tif (data & RTL8367B_MIB_CTRL0_RESET_MASK)\n\t\treturn -EIO;\n\n\tif (mib->length == 4)\n\t\toffset = 3;\n\telse\n\t\toffset = (mib->offset + 1) % 4;\n\n\tmibvalue = 0;\n\tfor (i = 0; i < mib->length; i++) {\n\t\tREG_RD(smi, RTL8367B_MIB_COUNTER_REG(offset - i), &data);\n\t\tmibvalue = (mibvalue << 16) | (data & 0xFFFF);\n\t}\n\n\t*val = mibvalue;\n\treturn 0;\n}\n\nstatic int rtl8367b_get_vlan_4k(struct rtl8366_smi *smi, u32 vid,\n\t\t\t\tstruct rtl8366_vlan_4k *vlan4k)\n{\n\tu32 data[RTL8367B_TA_VLAN_NUM_WORDS];\n\tint err;\n\tint i;\n\n\tmemset(vlan4k, '\\0', sizeof(struct rtl8366_vlan_4k));\n\n\tif (vid >= RTL8367B_NUM_VIDS)\n\t\treturn -EINVAL;\n\n\t/* write VID */\n\tREG_WR(smi, RTL8367B_TA_ADDR_REG, vid);\n\n\t/* write table access control word */\n\tREG_WR(smi, RTL8367B_TA_CTRL_REG, RTL8367B_TA_CTRL_CVLAN_READ);\n\n\tfor (i = 0; i < ARRAY_SIZE(data); i++)\n\t\tREG_RD(smi, RTL8367B_TA_RDDATA_REG(i), &data[i]);\n\n\tvlan4k->vid = vid;\n\tvlan4k->member = (data[0] >> RTL8367B_TA_VLAN0_MEMBER_SHIFT) &\n\t\t\t RTL8367B_TA_VLAN0_MEMBER_MASK;\n\tvlan4k->untag = (data[0] >> RTL8367B_TA_VLAN0_UNTAG_SHIFT) &\n\t\t\tRTL8367B_TA_VLAN0_UNTAG_MASK;\n\tvlan4k->fid = (data[1] >> RTL8367B_TA_VLAN1_FID_SHIFT) &\n\t\t      RTL8367B_TA_VLAN1_FID_MASK;\n\n\treturn 0;\n}\n\nstatic int rtl8367b_set_vlan_4k(struct rtl8366_smi *smi,\n\t\t\t\tconst struct rtl8366_vlan_4k *vlan4k)\n{\n\tu32 data[RTL8367B_TA_VLAN_NUM_WORDS];\n\tint err;\n\tint i;\n\n\tif (vlan4k->vid >= RTL8367B_NUM_VIDS ||\n\t    vlan4k->member > RTL8367B_TA_VLAN0_MEMBER_MASK ||\n\t    vlan4k->untag > RTL8367B_UNTAG_MASK ||\n\t    vlan4k->fid > RTL8367B_FIDMAX)\n\t\treturn -EINVAL;\n\n\tmemset(data, 0, sizeof(data));\n\n\tdata[0] = (vlan4k->member & RTL8367B_TA_VLAN0_MEMBER_MASK) <<\n\t\t  RTL8367B_TA_VLAN0_MEMBER_SHIFT;\n\tdata[0] |= (vlan4k->untag & RTL8367B_TA_VLAN0_UNTAG_MASK) <<\n\t\t   RTL8367B_TA_VLAN0_UNTAG_SHIFT;\n\tdata[1] = (vlan4k->fid & RTL8367B_TA_VLAN1_FID_MASK) <<\n\t\t  RTL8367B_TA_VLAN1_FID_SHIFT;\n\n\tfor (i = 0; i < ARRAY_SIZE(data); i++)\n\t\tREG_WR(smi, RTL8367B_TA_WRDATA_REG(i), data[i]);\n\n\t/* write VID */\n\tREG_WR(smi, RTL8367B_TA_ADDR_REG,\n\t       vlan4k->vid & RTL8367B_TA_VLAN_VID_MASK);\n\n\t/* write table access control word */\n\tREG_WR(smi, RTL8367B_TA_CTRL_REG, RTL8367B_TA_CTRL_CVLAN_WRITE);\n\n\treturn 0;\n}\n\nstatic int rtl8367b_get_vlan_mc(struct rtl8366_smi *smi, u32 index,\n\t\t\t\tstruct rtl8366_vlan_mc *vlanmc)\n{\n\tu32 data[RTL8367B_VLAN_MC_NUM_WORDS];\n\tint err;\n\tint i;\n\n\tmemset(vlanmc, '\\0', sizeof(struct rtl8366_vlan_mc));\n\n\tif (index >= RTL8367B_NUM_VLANS)\n\t\treturn -EINVAL;\n\n\tfor (i = 0; i < ARRAY_SIZE(data); i++)\n\t\tREG_RD(smi, RTL8367B_VLAN_MC_BASE(index) + i, &data[i]);\n\n\tvlanmc->member = (data[0] >> RTL8367B_VLAN_MC0_MEMBER_SHIFT) &\n\t\t\t RTL8367B_VLAN_MC0_MEMBER_MASK;\n\tvlanmc->fid = (data[1] >> RTL8367B_VLAN_MC1_FID_SHIFT) &\n\t\t      RTL8367B_VLAN_MC1_FID_MASK;\n\tvlanmc->vid = (data[3] >> RTL8367B_VLAN_MC3_EVID_SHIFT) &\n\t\t      RTL8367B_VLAN_MC3_EVID_MASK;\n\n\treturn 0;\n}\n\nstatic int rtl8367b_set_vlan_mc(struct rtl8366_smi *smi, u32 index,\n\t\t\t\tconst struct rtl8366_vlan_mc *vlanmc)\n{\n\tu32 data[RTL8367B_VLAN_MC_NUM_WORDS];\n\tint err;\n\tint i;\n\n\tif (index >= RTL8367B_NUM_VLANS ||\n\t    vlanmc->vid >= RTL8367B_NUM_VIDS ||\n\t    vlanmc->priority > RTL8367B_PRIORITYMAX ||\n\t    vlanmc->member > RTL8367B_VLAN_MC0_MEMBER_MASK ||\n\t    vlanmc->untag > RTL8367B_UNTAG_MASK ||\n\t    vlanmc->fid > RTL8367B_FIDMAX)\n\t\treturn -EINVAL;\n\n\tdata[0] = (vlanmc->member & RTL8367B_VLAN_MC0_MEMBER_MASK) <<\n\t\t  RTL8367B_VLAN_MC0_MEMBER_SHIFT;\n\tdata[1] = (vlanmc->fid & RTL8367B_VLAN_MC1_FID_MASK) <<\n\t\t  RTL8367B_VLAN_MC1_FID_SHIFT;\n\tdata[2] = 0;\n\tdata[3] = (vlanmc->vid & RTL8367B_VLAN_MC3_EVID_MASK) <<\n\t\t   RTL8367B_VLAN_MC3_EVID_SHIFT;\n\n\tfor (i = 0; i < ARRAY_SIZE(data); i++)\n\t\tREG_WR(smi, RTL8367B_VLAN_MC_BASE(index) + i, data[i]);\n\n\treturn 0;\n}\n\nstatic int rtl8367b_get_mc_index(struct rtl8366_smi *smi, int port, int *val)\n{\n\tu32 data;\n\tint err;\n\n\tif (port >= RTL8367B_NUM_PORTS)\n\t\treturn -EINVAL;\n\n\tREG_RD(smi, RTL8367B_VLAN_PVID_CTRL_REG(port), &data);\n\n\t*val = (data >> RTL8367B_VLAN_PVID_CTRL_SHIFT(port)) &\n\t       RTL8367B_VLAN_PVID_CTRL_MASK;\n\n\treturn 0;\n}\n\nstatic int rtl8367b_set_mc_index(struct rtl8366_smi *smi, int port, int index)\n{\n\tif (port >= RTL8367B_NUM_PORTS || index >= RTL8367B_NUM_VLANS)\n\t\treturn -EINVAL;\n\n\treturn rtl8366_smi_rmwr(smi, RTL8367B_VLAN_PVID_CTRL_REG(port),\n\t\t\t\tRTL8367B_VLAN_PVID_CTRL_MASK <<\n\t\t\t\t\tRTL8367B_VLAN_PVID_CTRL_SHIFT(port),\n\t\t\t\t(index & RTL8367B_VLAN_PVID_CTRL_MASK) <<\n\t\t\t\t\tRTL8367B_VLAN_PVID_CTRL_SHIFT(port));\n}\n\nstatic int rtl8367b_enable_vlan(struct rtl8366_smi *smi, int enable)\n{\n\treturn rtl8366_smi_rmwr(smi, RTL8367B_VLAN_CTRL_REG,\n\t\t\t\tRTL8367B_VLAN_CTRL_ENABLE,\n\t\t\t\t(enable) ? RTL8367B_VLAN_CTRL_ENABLE : 0);\n}\n\nstatic int rtl8367b_enable_vlan4k(struct rtl8366_smi *smi, int enable)\n{\n\treturn 0;\n}\n\nstatic int rtl8367b_is_vlan_valid(struct rtl8366_smi *smi, unsigned vlan)\n{\n\tunsigned max = RTL8367B_NUM_VLANS;\n\n\tif (smi->vlan4k_enabled)\n\t\tmax = RTL8367B_NUM_VIDS - 1;\n\n\tif (vlan == 0 || vlan >= max)\n\t\treturn 0;\n\n\treturn 1;\n}\n\nstatic int rtl8367b_enable_port(struct rtl8366_smi *smi, int port, int enable)\n{\n\tint err;\n\n\tREG_WR(smi, RTL8367B_PORT_ISOLATION_REG(port),\n\t       (enable) ? RTL8367B_PORTS_ALL : 0);\n\n\treturn 0;\n}\n\nstatic int rtl8367b_sw_reset_mibs(struct switch_dev *dev,\n\t\t\t\t  const struct switch_attr *attr,\n\t\t\t\t  struct switch_val *val)\n{\n\tstruct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);\n\n\treturn rtl8366_smi_rmwr(smi, RTL8367B_MIB_CTRL0_REG(0), 0,\n\t\t\t\tRTL8367B_MIB_CTRL0_GLOBAL_RESET_MASK);\n}\n\nstatic int rtl8367b_sw_get_port_link(struct switch_dev *dev,\n\t\t\t\t    int port,\n\t\t\t\t    struct switch_port_link *link)\n{\n\tstruct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);\n\tu32 data = 0;\n\tu32 speed;\n\n\tif (port >= RTL8367B_NUM_PORTS)\n\t\treturn -EINVAL;\n\n\trtl8366_smi_read_reg(smi, RTL8367B_PORT_STATUS_REG(port), &data);\n\n\tlink->link = !!(data & RTL8367B_PORT_STATUS_LINK);\n\tif (!link->link)\n\t\treturn 0;\n\n\tlink->duplex = !!(data & RTL8367B_PORT_STATUS_DUPLEX);\n\tlink->rx_flow = !!(data & RTL8367B_PORT_STATUS_RXPAUSE);\n\tlink->tx_flow = !!(data & RTL8367B_PORT_STATUS_TXPAUSE);\n\tlink->aneg = !!(data & RTL8367B_PORT_STATUS_NWAY);\n\n\tspeed = (data & RTL8367B_PORT_STATUS_SPEED_MASK);\n\tswitch (speed) {\n\tcase 0:\n\t\tlink->speed = SWITCH_PORT_SPEED_10;\n\t\tbreak;\n\tcase 1:\n\t\tlink->speed = SWITCH_PORT_SPEED_100;\n\t\tbreak;\n\tcase 2:\n\t\tlink->speed = SWITCH_PORT_SPEED_1000;\n\t\tbreak;\n\tdefault:\n\t\tlink->speed = SWITCH_PORT_SPEED_UNKNOWN;\n\t\tbreak;\n\t}\n\n\treturn 0;\n}\n\nstatic int rtl8367b_sw_get_max_length(struct switch_dev *dev,\n\t\t\t\t     const struct switch_attr *attr,\n\t\t\t\t     struct switch_val *val)\n{\n\tstruct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);\n\tu32 data;\n\n\trtl8366_smi_read_reg(smi, RTL8367B_SWC0_REG, &data);\n\tval->value.i = (data & RTL8367B_SWC0_MAX_LENGTH_MASK) >>\n\t\t\tRTL8367B_SWC0_MAX_LENGTH_SHIFT;\n\n\treturn 0;\n}\n\nstatic int rtl8367b_sw_set_max_length(struct switch_dev *dev,\n\t\t\t\t     const struct switch_attr *attr,\n\t\t\t\t     struct switch_val *val)\n{\n\tstruct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);\n\tu32 max_len;\n\n\tswitch (val->value.i) {\n\tcase 0:\n\t\tmax_len = RTL8367B_SWC0_MAX_LENGTH_1522;\n\t\tbreak;\n\tcase 1:\n\t\tmax_len = RTL8367B_SWC0_MAX_LENGTH_1536;\n\t\tbreak;\n\tcase 2:\n\t\tmax_len = RTL8367B_SWC0_MAX_LENGTH_1552;\n\t\tbreak;\n\tcase 3:\n\t\tmax_len = RTL8367B_SWC0_MAX_LENGTH_16000;\n\t\tbreak;\n\tdefault:\n\t\treturn -EINVAL;\n\t}\n\n\treturn rtl8366_smi_rmwr(smi, RTL8367B_SWC0_REG,\n\t\t\t        RTL8367B_SWC0_MAX_LENGTH_MASK, max_len);\n}\n\n\nstatic int rtl8367b_sw_reset_port_mibs(struct switch_dev *dev,\n\t\t\t\t       const struct switch_attr *attr,\n\t\t\t\t       struct switch_val *val)\n{\n\tstruct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);\n\tint port;\n\n\tport = val->port_vlan;\n\tif (port >= RTL8367B_NUM_PORTS)\n\t\treturn -EINVAL;\n\n\treturn rtl8366_smi_rmwr(smi, RTL8367B_MIB_CTRL0_REG(port / 8), 0,\n\t\t\t\tRTL8367B_MIB_CTRL0_PORT_RESET_MASK(port % 8));\n}\n\nstatic int rtl8367b_sw_get_port_stats(struct switch_dev *dev, int port,\n                                        struct switch_port_stats *stats)\n{\n\treturn (rtl8366_sw_get_port_stats(dev, port, stats,\n\t\t\t\tRTL8367B_MIB_TXB_ID, RTL8367B_MIB_RXB_ID));\n}\n\nstatic struct switch_attr rtl8367b_globals[] = {\n\t{\n\t\t.type = SWITCH_TYPE_INT,\n\t\t.name = \"enable_vlan\",\n\t\t.description = \"Enable VLAN mode\",\n\t\t.set = rtl8366_sw_set_vlan_enable,\n\t\t.get = rtl8366_sw_get_vlan_enable,\n\t\t.max = 1,\n\t\t.ofs = 1\n\t}, {\n\t\t.type = SWITCH_TYPE_INT,\n\t\t.name = \"enable_vlan4k\",\n\t\t.description = \"Enable VLAN 4K mode\",\n\t\t.set = rtl8366_sw_set_vlan_enable,\n\t\t.get = rtl8366_sw_get_vlan_enable,\n\t\t.max = 1,\n\t\t.ofs = 2\n\t}, {\n\t\t.type = SWITCH_TYPE_NOVAL,\n\t\t.name = \"reset_mibs\",\n\t\t.description = \"Reset all MIB counters\",\n\t\t.set = rtl8367b_sw_reset_mibs,\n\t}, {\n\t\t.type = SWITCH_TYPE_INT,\n\t\t.name = \"max_length\",\n\t\t.description = \"Get/Set the maximum length of valid packets\"\n\t\t\t       \"(0:1522, 1:1536, 2:1552, 3:16000)\",\n\t\t.set = rtl8367b_sw_set_max_length,\n\t\t.get = rtl8367b_sw_get_max_length,\n\t\t.max = 3,\n\t}\n};\n\nstatic struct switch_attr rtl8367b_port[] = {\n\t{\n\t\t.type = SWITCH_TYPE_NOVAL,\n\t\t.name = \"reset_mib\",\n\t\t.description = \"Reset single port MIB counters\",\n\t\t.set = rtl8367b_sw_reset_port_mibs,\n\t}, {\n\t\t.type = SWITCH_TYPE_STRING,\n\t\t.name = \"mib\",\n\t\t.description = \"Get MIB counters for port\",\n\t\t.max = 33,\n\t\t.set = NULL,\n\t\t.get = rtl8366_sw_get_port_mib,\n\t},\n};\n\nstatic struct switch_attr rtl8367b_vlan[] = {\n\t{\n\t\t.type = SWITCH_TYPE_STRING,\n\t\t.name = \"info\",\n\t\t.description = \"Get vlan information\",\n\t\t.max = 1,\n\t\t.set = NULL,\n\t\t.get = rtl8366_sw_get_vlan_info,\n\t},\n};\n\nstatic const struct switch_dev_ops rtl8367b_sw_ops = {\n\t.attr_global = {\n\t\t.attr = rtl8367b_globals,\n\t\t.n_attr = ARRAY_SIZE(rtl8367b_globals),\n\t},\n\t.attr_port = {\n\t\t.attr = rtl8367b_port,\n\t\t.n_attr = ARRAY_SIZE(rtl8367b_port),\n\t},\n\t.attr_vlan = {\n\t\t.attr = rtl8367b_vlan,\n\t\t.n_attr = ARRAY_SIZE(rtl8367b_vlan),\n\t},\n\n\t.get_vlan_ports = rtl8366_sw_get_vlan_ports,\n\t.set_vlan_ports = rtl8366_sw_set_vlan_ports,\n\t.get_port_pvid = rtl8366_sw_get_port_pvid,\n\t.set_port_pvid = rtl8366_sw_set_port_pvid,\n\t.reset_switch = rtl8366_sw_reset_switch,\n\t.get_port_link = rtl8367b_sw_get_port_link,\n\t.get_port_stats = rtl8367b_sw_get_port_stats,\n};\n\nstatic int rtl8367b_switch_init(struct rtl8366_smi *smi)\n{\n\tstruct switch_dev *dev = &smi->sw_dev;\n\tint err;\n\n\tdev->name = \"RTL8367B\";\n\tdev->cpu_port = smi->cpu_port;\n\tdev->ports = RTL8367B_NUM_PORTS;\n\tdev->vlans = RTL8367B_NUM_VIDS;\n\tdev->ops = &rtl8367b_sw_ops;\n\tdev->alias = dev_name(smi->parent);\n\n\terr = register_switch(dev, NULL);\n\tif (err)\n\t\tdev_err(smi->parent, \"switch registration failed\\n\");\n\n\treturn err;\n}\n\nstatic void rtl8367b_switch_cleanup(struct rtl8366_smi *smi)\n{\n\tunregister_switch(&smi->sw_dev);\n}\n\nstatic int rtl8367b_mii_read(struct mii_bus *bus, int addr, int reg)\n{\n\tstruct rtl8366_smi *smi = bus->priv;\n\tu32 val = 0;\n\tint err;\n\n\terr = rtl8367b_read_phy_reg(smi, addr, reg, &val);\n\tif (err)\n\t\treturn 0xffff;\n\n\treturn val;\n}\n\nstatic int rtl8367b_mii_write(struct mii_bus *bus, int addr, int reg, u16 val)\n{\n\tstruct rtl8366_smi *smi = bus->priv;\n\tu32 t;\n\tint err;\n\n\terr = rtl8367b_write_phy_reg(smi, addr, reg, val);\n\tif (err)\n\t\treturn err;\n\n\t/* flush write */\n\t(void) rtl8367b_read_phy_reg(smi, addr, reg, &t);\n\n\treturn err;\n}\n\nstatic int rtl8367b_detect(struct rtl8366_smi *smi)\n{\n\tconst char *chip_name;\n\tu32 chip_num;\n\tu32 chip_ver;\n\tu32 chip_mode;\n\tint ret;\n\n\t/* TODO: improve chip detection */\n\trtl8366_smi_write_reg(smi, RTL8367B_RTL_MAGIC_ID_REG,\n\t\t\t      RTL8367B_RTL_MAGIC_ID_VAL);\n\n\tret = rtl8366_smi_read_reg(smi, RTL8367B_CHIP_NUMBER_REG, &chip_num);\n\tif (ret) {\n\t\tdev_err(smi->parent, \"unable to read %s register\\n\",\n\t\t\t\"chip number\");\n\t\treturn ret;\n\t}\n\n\tret = rtl8366_smi_read_reg(smi, RTL8367B_CHIP_VER_REG, &chip_ver);\n\tif (ret) {\n\t\tdev_err(smi->parent, \"unable to read %s register\\n\",\n\t\t\t\"chip version\");\n\t\treturn ret;\n\t}\n\n\tret = rtl8366_smi_read_reg(smi, RTL8367B_CHIP_MODE_REG, &chip_mode);\n\tif (ret) {\n\t\tdev_err(smi->parent, \"unable to read %s register\\n\",\n\t\t\t\"chip mode\");\n\t\treturn ret;\n\t}\n\n\tswitch (chip_ver) {\n\tcase 0x1000:\n\t\tchip_name = \"8367RB\";\n\t\tbreak;\n\tcase 0x1010:\n\t\tchip_name = \"8367R-VB\";\n\t\tbreak;\n\tdefault:\n\t\tdev_err(smi->parent,\n\t\t\t\"unknown chip num:%04x ver:%04x, mode:%04x\\n\",\n\t\t\tchip_num, chip_ver, chip_mode);\n\t\treturn -ENODEV;\n\t}\n\n\tdev_info(smi->parent, \"RTL%s chip found\\n\", chip_name);\n\n\treturn 0;\n}\n\nstatic struct rtl8366_smi_ops rtl8367b_smi_ops = {\n\t.detect\t\t= rtl8367b_detect,\n\t.reset_chip\t= rtl8367b_reset_chip,\n\t.setup\t\t= rtl8367b_setup,\n\n\t.mii_read\t= rtl8367b_mii_read,\n\t.mii_write\t= rtl8367b_mii_write,\n\n\t.get_vlan_mc\t= rtl8367b_get_vlan_mc,\n\t.set_vlan_mc\t= rtl8367b_set_vlan_mc,\n\t.get_vlan_4k\t= rtl8367b_get_vlan_4k,\n\t.set_vlan_4k\t= rtl8367b_set_vlan_4k,\n\t.get_mc_index\t= rtl8367b_get_mc_index,\n\t.set_mc_index\t= rtl8367b_set_mc_index,\n\t.get_mib_counter = rtl8367b_get_mib_counter,\n\t.is_vlan_valid\t= rtl8367b_is_vlan_valid,\n\t.enable_vlan\t= rtl8367b_enable_vlan,\n\t.enable_vlan4k\t= rtl8367b_enable_vlan4k,\n\t.enable_port\t= rtl8367b_enable_port,\n};\n\nstatic int  rtl8367b_probe(struct platform_device *pdev)\n{\n\tstruct rtl8366_smi *smi;\n\tint err;\n\n\tsmi = rtl8366_smi_probe(pdev);\n\tif (IS_ERR(smi))\n\t\treturn PTR_ERR(smi);\n\n\tsmi->clk_delay = 1500;\n\tsmi->cmd_read = 0xb9;\n\tsmi->cmd_write = 0xb8;\n\tsmi->ops = &rtl8367b_smi_ops;\n\tsmi->num_ports = RTL8367B_NUM_PORTS;\n\tif (of_property_read_u32(pdev->dev.of_node, \"cpu_port\", &smi->cpu_port)\n\t    || smi->cpu_port >= smi->num_ports)\n\t\tsmi->cpu_port = RTL8367B_CPU_PORT_NUM;\n\tsmi->num_vlan_mc = RTL8367B_NUM_VLANS;\n\tsmi->mib_counters = rtl8367b_mib_counters;\n\tsmi->num_mib_counters = ARRAY_SIZE(rtl8367b_mib_counters);\n\n\terr = rtl8366_smi_init(smi);\n\tif (err)\n\t\tgoto err_free_smi;\n\n\tplatform_set_drvdata(pdev, smi);\n\n\terr = rtl8367b_switch_init(smi);\n\tif (err)\n\t\tgoto err_clear_drvdata;\n\n\treturn 0;\n\n err_clear_drvdata:\n\tplatform_set_drvdata(pdev, NULL);\n\trtl8366_smi_cleanup(smi);\n err_free_smi:\n\tkfree(smi);\n\treturn err;\n}\n\nstatic int rtl8367b_remove(struct platform_device *pdev)\n{\n\tstruct rtl8366_smi *smi = platform_get_drvdata(pdev);\n\n\tif (smi) {\n\t\trtl8367b_switch_cleanup(smi);\n\t\tplatform_set_drvdata(pdev, NULL);\n\t\trtl8366_smi_cleanup(smi);\n\t\tkfree(smi);\n\t}\n\n\treturn 0;\n}\n\nstatic void rtl8367b_shutdown(struct platform_device *pdev)\n{\n\tstruct rtl8366_smi *smi = platform_get_drvdata(pdev);\n\n\tif (smi)\n\t\trtl8367b_reset_chip(smi);\n}\n\n#ifdef CONFIG_OF\nstatic const struct of_device_id rtl8367b_match[] = {\n\t{ .compatible = \"realtek,rtl8367b\" },\n\t{},\n};\nMODULE_DEVICE_TABLE(of, rtl8367b_match);\n#endif\n\nstatic struct platform_driver rtl8367b_driver = {\n\t.driver = {\n\t\t.name\t\t= RTL8367B_DRIVER_NAME,\n\t\t.owner\t\t= THIS_MODULE,\n#ifdef CONFIG_OF\n\t\t.of_match_table = of_match_ptr(rtl8367b_match),\n#endif\n\t},\n\t.probe\t\t= rtl8367b_probe,\n\t.remove\t\t= rtl8367b_remove,\n\t.shutdown\t= rtl8367b_shutdown,\n};\n\nmodule_platform_driver(rtl8367b_driver);\n\nMODULE_DESCRIPTION(\"Realtek RTL8367B ethernet switch driver\");\nMODULE_AUTHOR(\"Gabor Juhos <juhosg@openwrt.org>\");\nMODULE_LICENSE(\"GPL v2\");\nMODULE_ALIAS(\"platform:\" RTL8367B_DRIVER_NAME);\n\n"
  },
  {
    "path": "target/linux/generic/files/drivers/net/phy/swconfig.c",
    "content": "/*\n * swconfig.c: Switch configuration API\n *\n * Copyright (C) 2008 Felix Fietkau <nbd@nbd.name>\n *\n * This program is free software; you can redistribute it and/or\n * modify it under the terms of the GNU General Public License\n * as published by the Free Software Foundation; either version 2\n * of the License, or (at your option) any later version.\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n * GNU General Public License for more details.\n */\n\n#include <linux/types.h>\n#include <linux/module.h>\n#include <linux/init.h>\n#include <linux/list.h>\n#include <linux/if.h>\n#include <linux/if_ether.h>\n#include <linux/capability.h>\n#include <linux/skbuff.h>\n#include <linux/switch.h>\n#include <linux/of.h>\n#include <linux/version.h>\n#include <uapi/linux/mii.h>\n\n#define SWCONFIG_DEVNAME\t\"switch%d\"\n\n#include \"swconfig_leds.c\"\n\nMODULE_AUTHOR(\"Felix Fietkau <nbd@nbd.name>\");\nMODULE_LICENSE(\"GPL\");\n\nstatic int swdev_id;\nstatic struct list_head swdevs;\nstatic DEFINE_MUTEX(swdevs_lock);\nstruct swconfig_callback;\n\nstruct swconfig_callback {\n\tstruct sk_buff *msg;\n\tstruct genlmsghdr *hdr;\n\tstruct genl_info *info;\n\tint cmd;\n\n\t/* callback for filling in the message data */\n\tint (*fill)(struct swconfig_callback *cb, void *arg);\n\n\t/* callback for closing the message before sending it */\n\tint (*close)(struct swconfig_callback *cb, void *arg);\n\n\tstruct nlattr *nest[4];\n\tint args[4];\n};\n\n/* defaults */\n\nstatic int\nswconfig_get_vlan_ports(struct switch_dev *dev, const struct switch_attr *attr,\n\t\t\tstruct switch_val *val)\n{\n\tint ret;\n\tif (val->port_vlan >= dev->vlans)\n\t\treturn -EINVAL;\n\n\tif (!dev->ops->get_vlan_ports)\n\t\treturn -EOPNOTSUPP;\n\n\tret = dev->ops->get_vlan_ports(dev, val);\n\treturn ret;\n}\n\nstatic int\nswconfig_set_vlan_ports(struct switch_dev *dev, const struct switch_attr *attr,\n\t\t\tstruct switch_val *val)\n{\n\tstruct switch_port *ports = val->value.ports;\n\tconst struct switch_dev_ops *ops = dev->ops;\n\tint i;\n\n\tif (val->port_vlan >= dev->vlans)\n\t\treturn -EINVAL;\n\n\t/* validate ports */\n\tif (val->len > dev->ports)\n\t\treturn -EINVAL;\n\n\tif (!ops->set_vlan_ports)\n\t\treturn -EOPNOTSUPP;\n\n\tfor (i = 0; i < val->len; i++) {\n\t\tif (ports[i].id >= dev->ports)\n\t\t\treturn -EINVAL;\n\n\t\tif (ops->set_port_pvid &&\n\t\t    !(ports[i].flags & (1 << SWITCH_PORT_FLAG_TAGGED)))\n\t\t\tops->set_port_pvid(dev, ports[i].id, val->port_vlan);\n\t}\n\n\treturn ops->set_vlan_ports(dev, val);\n}\n\nstatic int\nswconfig_set_pvid(struct switch_dev *dev, const struct switch_attr *attr,\n\t\t\tstruct switch_val *val)\n{\n\tif (val->port_vlan >= dev->ports)\n\t\treturn -EINVAL;\n\n\tif (!dev->ops->set_port_pvid)\n\t\treturn -EOPNOTSUPP;\n\n\treturn dev->ops->set_port_pvid(dev, val->port_vlan, val->value.i);\n}\n\nstatic int\nswconfig_get_pvid(struct switch_dev *dev, const struct switch_attr *attr,\n\t\t\tstruct switch_val *val)\n{\n\tif (val->port_vlan >= dev->ports)\n\t\treturn -EINVAL;\n\n\tif (!dev->ops->get_port_pvid)\n\t\treturn -EOPNOTSUPP;\n\n\treturn dev->ops->get_port_pvid(dev, val->port_vlan, &val->value.i);\n}\n\nstatic int\nswconfig_set_link(struct switch_dev *dev, const struct switch_attr *attr,\n\t\t\tstruct switch_val *val)\n{\n\tif (!dev->ops->set_port_link)\n\t\treturn -EOPNOTSUPP;\n\n\treturn dev->ops->set_port_link(dev, val->port_vlan, val->value.link);\n}\n\nstatic int\nswconfig_get_link(struct switch_dev *dev, const struct switch_attr *attr,\n\t\t\tstruct switch_val *val)\n{\n\tstruct switch_port_link *link = val->value.link;\n\n\tif (val->port_vlan >= dev->ports)\n\t\treturn -EINVAL;\n\n\tif (!dev->ops->get_port_link)\n\t\treturn -EOPNOTSUPP;\n\n\tmemset(link, 0, sizeof(*link));\n\treturn dev->ops->get_port_link(dev, val->port_vlan, link);\n}\n\nstatic int\nswconfig_apply_config(struct switch_dev *dev, const struct switch_attr *attr,\n\t\t\tstruct switch_val *val)\n{\n\t/* don't complain if not supported by the switch driver */\n\tif (!dev->ops->apply_config)\n\t\treturn 0;\n\n\treturn dev->ops->apply_config(dev);\n}\n\nstatic int\nswconfig_reset_switch(struct switch_dev *dev, const struct switch_attr *attr,\n\t\t\tstruct switch_val *val)\n{\n\t/* don't complain if not supported by the switch driver */\n\tif (!dev->ops->reset_switch)\n\t\treturn 0;\n\n\treturn dev->ops->reset_switch(dev);\n}\n\nenum global_defaults {\n\tGLOBAL_APPLY,\n\tGLOBAL_RESET,\n};\n\nenum vlan_defaults {\n\tVLAN_PORTS,\n};\n\nenum port_defaults {\n\tPORT_PVID,\n\tPORT_LINK,\n};\n\nstatic struct switch_attr default_global[] = {\n\t[GLOBAL_APPLY] = {\n\t\t.type = SWITCH_TYPE_NOVAL,\n\t\t.name = \"apply\",\n\t\t.description = \"Activate changes in the hardware\",\n\t\t.set = swconfig_apply_config,\n\t},\n\t[GLOBAL_RESET] = {\n\t\t.type = SWITCH_TYPE_NOVAL,\n\t\t.name = \"reset\",\n\t\t.description = \"Reset the switch\",\n\t\t.set = swconfig_reset_switch,\n\t}\n};\n\nstatic struct switch_attr default_port[] = {\n\t[PORT_PVID] = {\n\t\t.type = SWITCH_TYPE_INT,\n\t\t.name = \"pvid\",\n\t\t.description = \"Primary VLAN ID\",\n\t\t.set = swconfig_set_pvid,\n\t\t.get = swconfig_get_pvid,\n\t},\n\t[PORT_LINK] = {\n\t\t.type = SWITCH_TYPE_LINK,\n\t\t.name = \"link\",\n\t\t.description = \"Get port link information\",\n\t\t.set = swconfig_set_link,\n\t\t.get = swconfig_get_link,\n\t}\n};\n\nstatic struct switch_attr default_vlan[] = {\n\t[VLAN_PORTS] = {\n\t\t.type = SWITCH_TYPE_PORTS,\n\t\t.name = \"ports\",\n\t\t.description = \"VLAN port mapping\",\n\t\t.set = swconfig_set_vlan_ports,\n\t\t.get = swconfig_get_vlan_ports,\n\t},\n};\n\nstatic const struct switch_attr *\nswconfig_find_attr_by_name(const struct switch_attrlist *alist,\n\t\t\t\tconst char *name)\n{\n\tint i;\n\n\tfor (i = 0; i < alist->n_attr; i++)\n\t\tif (strcmp(name, alist->attr[i].name) == 0)\n\t\t\treturn &alist->attr[i];\n\n\treturn NULL;\n}\n\nstatic void swconfig_defaults_init(struct switch_dev *dev)\n{\n\tconst struct switch_dev_ops *ops = dev->ops;\n\n\tdev->def_global = 0;\n\tdev->def_vlan = 0;\n\tdev->def_port = 0;\n\n\tif (ops->get_vlan_ports || ops->set_vlan_ports)\n\t\tset_bit(VLAN_PORTS, &dev->def_vlan);\n\n\tif (ops->get_port_pvid || ops->set_port_pvid)\n\t\tset_bit(PORT_PVID, &dev->def_port);\n\n\tif (ops->get_port_link &&\n\t    !swconfig_find_attr_by_name(&ops->attr_port, \"link\"))\n\t\tset_bit(PORT_LINK, &dev->def_port);\n\n\t/* always present, can be no-op */\n\tset_bit(GLOBAL_APPLY, &dev->def_global);\n\tset_bit(GLOBAL_RESET, &dev->def_global);\n}\n\n\nstatic struct genl_family switch_fam;\n\nstatic const struct nla_policy switch_policy[SWITCH_ATTR_MAX+1] = {\n\t[SWITCH_ATTR_ID] = { .type = NLA_U32 },\n\t[SWITCH_ATTR_OP_ID] = { .type = NLA_U32 },\n\t[SWITCH_ATTR_OP_PORT] = { .type = NLA_U32 },\n\t[SWITCH_ATTR_OP_VLAN] = { .type = NLA_U32 },\n\t[SWITCH_ATTR_OP_VALUE_INT] = { .type = NLA_U32 },\n\t[SWITCH_ATTR_OP_VALUE_STR] = { .type = NLA_NUL_STRING },\n\t[SWITCH_ATTR_OP_VALUE_PORTS] = { .type = NLA_NESTED },\n\t[SWITCH_ATTR_TYPE] = { .type = NLA_U32 },\n};\n\nstatic const struct nla_policy port_policy[SWITCH_PORT_ATTR_MAX+1] = {\n\t[SWITCH_PORT_ID] = { .type = NLA_U32 },\n\t[SWITCH_PORT_FLAG_TAGGED] = { .type = NLA_FLAG },\n};\n\nstatic struct nla_policy link_policy[SWITCH_LINK_ATTR_MAX] = {\n\t[SWITCH_LINK_FLAG_DUPLEX] = { .type = NLA_FLAG },\n\t[SWITCH_LINK_FLAG_ANEG] = { .type = NLA_FLAG },\n\t[SWITCH_LINK_SPEED] = { .type = NLA_U32 },\n};\n\nstatic inline void\nswconfig_lock(void)\n{\n\tmutex_lock(&swdevs_lock);\n}\n\nstatic inline void\nswconfig_unlock(void)\n{\n\tmutex_unlock(&swdevs_lock);\n}\n\nstatic struct switch_dev *\nswconfig_get_dev(struct genl_info *info)\n{\n\tstruct switch_dev *dev = NULL;\n\tstruct switch_dev *p;\n\tint id;\n\n\tif (!info->attrs[SWITCH_ATTR_ID])\n\t\tgoto done;\n\n\tid = nla_get_u32(info->attrs[SWITCH_ATTR_ID]);\n\tswconfig_lock();\n\tlist_for_each_entry(p, &swdevs, dev_list) {\n\t\tif (id != p->id)\n\t\t\tcontinue;\n\n\t\tdev = p;\n\t\tbreak;\n\t}\n\tif (dev)\n\t\tmutex_lock(&dev->sw_mutex);\n\telse\n\t\tpr_debug(\"device %d not found\\n\", id);\n\tswconfig_unlock();\ndone:\n\treturn dev;\n}\n\nstatic inline void\nswconfig_put_dev(struct switch_dev *dev)\n{\n\tmutex_unlock(&dev->sw_mutex);\n}\n\nstatic int\nswconfig_dump_attr(struct swconfig_callback *cb, void *arg)\n{\n\tstruct switch_attr *op = arg;\n\tstruct genl_info *info = cb->info;\n\tstruct sk_buff *msg = cb->msg;\n\tint id = cb->args[0];\n\tvoid *hdr;\n\n\thdr = genlmsg_put(msg, info->snd_portid, info->snd_seq, &switch_fam,\n\t\t\tNLM_F_MULTI, SWITCH_CMD_NEW_ATTR);\n\tif (IS_ERR(hdr))\n\t\treturn -1;\n\n\tif (nla_put_u32(msg, SWITCH_ATTR_OP_ID, id))\n\t\tgoto nla_put_failure;\n\tif (nla_put_u32(msg, SWITCH_ATTR_OP_TYPE, op->type))\n\t\tgoto nla_put_failure;\n\tif (nla_put_string(msg, SWITCH_ATTR_OP_NAME, op->name))\n\t\tgoto nla_put_failure;\n\tif (op->description)\n\t\tif (nla_put_string(msg, SWITCH_ATTR_OP_DESCRIPTION,\n\t\t\top->description))\n\t\t\tgoto nla_put_failure;\n\n\tgenlmsg_end(msg, hdr);\n\treturn msg->len;\nnla_put_failure:\n\tgenlmsg_cancel(msg, hdr);\n\treturn -EMSGSIZE;\n}\n\n/* spread multipart messages across multiple message buffers */\nstatic int\nswconfig_send_multipart(struct swconfig_callback *cb, void *arg)\n{\n\tstruct genl_info *info = cb->info;\n\tint restart = 0;\n\tint err;\n\n\tdo {\n\t\tif (!cb->msg) {\n\t\t\tcb->msg = nlmsg_new(NLMSG_GOODSIZE, GFP_KERNEL);\n\t\t\tif (cb->msg == NULL)\n\t\t\t\tgoto error;\n\t\t}\n\n\t\tif (!(cb->fill(cb, arg) < 0))\n\t\t\tbreak;\n\n\t\t/* fill failed, check if this was already the second attempt */\n\t\tif (restart)\n\t\t\tgoto error;\n\n\t\t/* try again in a new message, send the current one */\n\t\trestart = 1;\n\t\tif (cb->close) {\n\t\t\tif (cb->close(cb, arg) < 0)\n\t\t\t\tgoto error;\n\t\t}\n\t\terr = genlmsg_reply(cb->msg, info);\n\t\tcb->msg = NULL;\n\t\tif (err < 0)\n\t\t\tgoto error;\n\n\t} while (restart);\n\n\treturn 0;\n\nerror:\n\tif (cb->msg)\n\t\tnlmsg_free(cb->msg);\n\treturn -1;\n}\n\nstatic int\nswconfig_list_attrs(struct sk_buff *skb, struct genl_info *info)\n{\n\tstruct genlmsghdr *hdr = nlmsg_data(info->nlhdr);\n\tconst struct switch_attrlist *alist;\n\tstruct switch_dev *dev;\n\tstruct swconfig_callback cb;\n\tint err = -EINVAL;\n\tint i;\n\n\t/* defaults */\n\tstruct switch_attr *def_list;\n\tunsigned long *def_active;\n\tint n_def;\n\n\tdev = swconfig_get_dev(info);\n\tif (!dev)\n\t\treturn -EINVAL;\n\n\tswitch (hdr->cmd) {\n\tcase SWITCH_CMD_LIST_GLOBAL:\n\t\talist = &dev->ops->attr_global;\n\t\tdef_list = default_global;\n\t\tdef_active = &dev->def_global;\n\t\tn_def = ARRAY_SIZE(default_global);\n\t\tbreak;\n\tcase SWITCH_CMD_LIST_VLAN:\n\t\talist = &dev->ops->attr_vlan;\n\t\tdef_list = default_vlan;\n\t\tdef_active = &dev->def_vlan;\n\t\tn_def = ARRAY_SIZE(default_vlan);\n\t\tbreak;\n\tcase SWITCH_CMD_LIST_PORT:\n\t\talist = &dev->ops->attr_port;\n\t\tdef_list = default_port;\n\t\tdef_active = &dev->def_port;\n\t\tn_def = ARRAY_SIZE(default_port);\n\t\tbreak;\n\tdefault:\n\t\tWARN_ON(1);\n\t\tgoto out;\n\t}\n\n\tmemset(&cb, 0, sizeof(cb));\n\tcb.info = info;\n\tcb.fill = swconfig_dump_attr;\n\tfor (i = 0; i < alist->n_attr; i++) {\n\t\tif (alist->attr[i].disabled)\n\t\t\tcontinue;\n\t\tcb.args[0] = i;\n\t\terr = swconfig_send_multipart(&cb, (void *) &alist->attr[i]);\n\t\tif (err < 0)\n\t\t\tgoto error;\n\t}\n\n\t/* defaults */\n\tfor (i = 0; i < n_def; i++) {\n\t\tif (!test_bit(i, def_active))\n\t\t\tcontinue;\n\t\tcb.args[0] = SWITCH_ATTR_DEFAULTS_OFFSET + i;\n\t\terr = swconfig_send_multipart(&cb, (void *) &def_list[i]);\n\t\tif (err < 0)\n\t\t\tgoto error;\n\t}\n\tswconfig_put_dev(dev);\n\n\tif (!cb.msg)\n\t\treturn 0;\n\n\treturn genlmsg_reply(cb.msg, info);\n\nerror:\n\tif (cb.msg)\n\t\tnlmsg_free(cb.msg);\nout:\n\tswconfig_put_dev(dev);\n\treturn err;\n}\n\nstatic const struct switch_attr *\nswconfig_lookup_attr(struct switch_dev *dev, struct genl_info *info,\n\t\tstruct switch_val *val)\n{\n\tstruct genlmsghdr *hdr = nlmsg_data(info->nlhdr);\n\tconst struct switch_attrlist *alist;\n\tconst struct switch_attr *attr = NULL;\n\tunsigned int attr_id;\n\n\t/* defaults */\n\tstruct switch_attr *def_list;\n\tunsigned long *def_active;\n\tint n_def;\n\n\tif (!info->attrs[SWITCH_ATTR_OP_ID])\n\t\tgoto done;\n\n\tswitch (hdr->cmd) {\n\tcase SWITCH_CMD_SET_GLOBAL:\n\tcase SWITCH_CMD_GET_GLOBAL:\n\t\talist = &dev->ops->attr_global;\n\t\tdef_list = default_global;\n\t\tdef_active = &dev->def_global;\n\t\tn_def = ARRAY_SIZE(default_global);\n\t\tbreak;\n\tcase SWITCH_CMD_SET_VLAN:\n\tcase SWITCH_CMD_GET_VLAN:\n\t\talist = &dev->ops->attr_vlan;\n\t\tdef_list = default_vlan;\n\t\tdef_active = &dev->def_vlan;\n\t\tn_def = ARRAY_SIZE(default_vlan);\n\t\tif (!info->attrs[SWITCH_ATTR_OP_VLAN])\n\t\t\tgoto done;\n\t\tval->port_vlan = nla_get_u32(info->attrs[SWITCH_ATTR_OP_VLAN]);\n\t\tif (val->port_vlan >= dev->vlans)\n\t\t\tgoto done;\n\t\tbreak;\n\tcase SWITCH_CMD_SET_PORT:\n\tcase SWITCH_CMD_GET_PORT:\n\t\talist = &dev->ops->attr_port;\n\t\tdef_list = default_port;\n\t\tdef_active = &dev->def_port;\n\t\tn_def = ARRAY_SIZE(default_port);\n\t\tif (!info->attrs[SWITCH_ATTR_OP_PORT])\n\t\t\tgoto done;\n\t\tval->port_vlan = nla_get_u32(info->attrs[SWITCH_ATTR_OP_PORT]);\n\t\tif (val->port_vlan >= dev->ports)\n\t\t\tgoto done;\n\t\tbreak;\n\tdefault:\n\t\tWARN_ON(1);\n\t\tgoto done;\n\t}\n\n\tif (!alist)\n\t\tgoto done;\n\n\tattr_id = nla_get_u32(info->attrs[SWITCH_ATTR_OP_ID]);\n\tif (attr_id >= SWITCH_ATTR_DEFAULTS_OFFSET) {\n\t\tattr_id -= SWITCH_ATTR_DEFAULTS_OFFSET;\n\t\tif (attr_id >= n_def)\n\t\t\tgoto done;\n\t\tif (!test_bit(attr_id, def_active))\n\t\t\tgoto done;\n\t\tattr = &def_list[attr_id];\n\t} else {\n\t\tif (attr_id >= alist->n_attr)\n\t\t\tgoto done;\n\t\tattr = &alist->attr[attr_id];\n\t}\n\n\tif (attr->disabled)\n\t\tattr = NULL;\n\ndone:\n\tif (!attr)\n\t\tpr_debug(\"attribute lookup failed\\n\");\n\tval->attr = attr;\n\treturn attr;\n}\n\nstatic int\nswconfig_parse_ports(struct sk_buff *msg, struct nlattr *head,\n\t\tstruct switch_val *val, int max)\n{\n\tstruct nlattr *nla;\n\tint rem;\n\n\tval->len = 0;\n\tnla_for_each_nested(nla, head, rem) {\n\t\tstruct nlattr *tb[SWITCH_PORT_ATTR_MAX+1];\n\t\tstruct switch_port *port;\n\n\t\tif (val->len >= max)\n\t\t\treturn -EINVAL;\n\n\t\tport = &val->value.ports[val->len];\n\n\t\tif (nla_parse_nested_deprecated(tb, SWITCH_PORT_ATTR_MAX, nla,\n\t\t\t\tport_policy, NULL))\n\t\t\treturn -EINVAL;\n\n\t\tif (!tb[SWITCH_PORT_ID])\n\t\t\treturn -EINVAL;\n\n\t\tport->id = nla_get_u32(tb[SWITCH_PORT_ID]);\n\t\tif (tb[SWITCH_PORT_FLAG_TAGGED])\n\t\t\tport->flags |= (1 << SWITCH_PORT_FLAG_TAGGED);\n\t\tval->len++;\n\t}\n\n\treturn 0;\n}\n\nstatic int\nswconfig_parse_link(struct sk_buff *msg, struct nlattr *nla,\n\t\t    struct switch_port_link *link)\n{\n\tstruct nlattr *tb[SWITCH_LINK_ATTR_MAX + 1];\n\n\tif (nla_parse_nested_deprecated(tb, SWITCH_LINK_ATTR_MAX, nla, link_policy, NULL))\n\t\treturn -EINVAL;\n\n\tlink->duplex = !!tb[SWITCH_LINK_FLAG_DUPLEX];\n\tlink->aneg = !!tb[SWITCH_LINK_FLAG_ANEG];\n\tlink->speed = nla_get_u32(tb[SWITCH_LINK_SPEED]);\n\n\treturn 0;\n}\n\nstatic int\nswconfig_set_attr(struct sk_buff *skb, struct genl_info *info)\n{\n\tconst struct switch_attr *attr;\n\tstruct switch_dev *dev;\n\tstruct switch_val val;\n\tint err = -EINVAL;\n\n\tif (!capable(CAP_NET_ADMIN))\n\t\treturn -EPERM;\n\n\tdev = swconfig_get_dev(info);\n\tif (!dev)\n\t\treturn -EINVAL;\n\n\tmemset(&val, 0, sizeof(val));\n\tattr = swconfig_lookup_attr(dev, info, &val);\n\tif (!attr || !attr->set)\n\t\tgoto error;\n\n\tval.attr = attr;\n\tswitch (attr->type) {\n\tcase SWITCH_TYPE_NOVAL:\n\t\tbreak;\n\tcase SWITCH_TYPE_INT:\n\t\tif (!info->attrs[SWITCH_ATTR_OP_VALUE_INT])\n\t\t\tgoto error;\n\t\tval.value.i =\n\t\t\tnla_get_u32(info->attrs[SWITCH_ATTR_OP_VALUE_INT]);\n\t\tbreak;\n\tcase SWITCH_TYPE_STRING:\n\t\tif (!info->attrs[SWITCH_ATTR_OP_VALUE_STR])\n\t\t\tgoto error;\n\t\tval.value.s =\n\t\t\tnla_data(info->attrs[SWITCH_ATTR_OP_VALUE_STR]);\n\t\tbreak;\n\tcase SWITCH_TYPE_PORTS:\n\t\tval.value.ports = dev->portbuf;\n\t\tmemset(dev->portbuf, 0,\n\t\t\tsizeof(struct switch_port) * dev->ports);\n\n\t\t/* TODO: implement multipart? */\n\t\tif (info->attrs[SWITCH_ATTR_OP_VALUE_PORTS]) {\n\t\t\terr = swconfig_parse_ports(skb,\n\t\t\t\tinfo->attrs[SWITCH_ATTR_OP_VALUE_PORTS],\n\t\t\t\t&val, dev->ports);\n\t\t\tif (err < 0)\n\t\t\t\tgoto error;\n\t\t} else {\n\t\t\tval.len = 0;\n\t\t\terr = 0;\n\t\t}\n\t\tbreak;\n\tcase SWITCH_TYPE_LINK:\n\t\tval.value.link = &dev->linkbuf;\n\t\tmemset(&dev->linkbuf, 0, sizeof(struct switch_port_link));\n\n\t\tif (info->attrs[SWITCH_ATTR_OP_VALUE_LINK]) {\n\t\t\terr = swconfig_parse_link(skb,\n\t\t\t\t\t\t  info->attrs[SWITCH_ATTR_OP_VALUE_LINK],\n\t\t\t\t\t\t  val.value.link);\n\t\t\tif (err < 0)\n\t\t\t\tgoto error;\n\t\t} else {\n\t\t\tval.len = 0;\n\t\t\terr = 0;\n\t\t}\n\t\tbreak;\n\tdefault:\n\t\tgoto error;\n\t}\n\n\terr = attr->set(dev, attr, &val);\nerror:\n\tswconfig_put_dev(dev);\n\treturn err;\n}\n\nstatic int\nswconfig_close_portlist(struct swconfig_callback *cb, void *arg)\n{\n\tif (cb->nest[0])\n\t\tnla_nest_end(cb->msg, cb->nest[0]);\n\treturn 0;\n}\n\nstatic int\nswconfig_send_port(struct swconfig_callback *cb, void *arg)\n{\n\tconst struct switch_port *port = arg;\n\tstruct nlattr *p = NULL;\n\n\tif (!cb->nest[0]) {\n\t\tcb->nest[0] = nla_nest_start(cb->msg, cb->cmd);\n\t\tif (!cb->nest[0])\n\t\t\treturn -1;\n\t}\n\n\tp = nla_nest_start(cb->msg, SWITCH_ATTR_PORT);\n\tif (!p)\n\t\tgoto error;\n\n\tif (nla_put_u32(cb->msg, SWITCH_PORT_ID, port->id))\n\t\tgoto nla_put_failure;\n\tif (port->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) {\n\t\tif (nla_put_flag(cb->msg, SWITCH_PORT_FLAG_TAGGED))\n\t\t\tgoto nla_put_failure;\n\t}\n\n\tnla_nest_end(cb->msg, p);\n\treturn 0;\n\nnla_put_failure:\n\t\tnla_nest_cancel(cb->msg, p);\nerror:\n\tnla_nest_cancel(cb->msg, cb->nest[0]);\n\treturn -1;\n}\n\nstatic int\nswconfig_send_ports(struct sk_buff **msg, struct genl_info *info, int attr,\n\t\tconst struct switch_val *val)\n{\n\tstruct swconfig_callback cb;\n\tint err = 0;\n\tint i;\n\n\tif (!val->value.ports)\n\t\treturn -EINVAL;\n\n\tmemset(&cb, 0, sizeof(cb));\n\tcb.cmd = attr;\n\tcb.msg = *msg;\n\tcb.info = info;\n\tcb.fill = swconfig_send_port;\n\tcb.close = swconfig_close_portlist;\n\n\tcb.nest[0] = nla_nest_start(cb.msg, cb.cmd);\n\tfor (i = 0; i < val->len; i++) {\n\t\terr = swconfig_send_multipart(&cb, &val->value.ports[i]);\n\t\tif (err)\n\t\t\tgoto done;\n\t}\n\terr = val->len;\n\tswconfig_close_portlist(&cb, NULL);\n\t*msg = cb.msg;\n\ndone:\n\treturn err;\n}\n\nstatic int\nswconfig_send_link(struct sk_buff *msg, struct genl_info *info, int attr,\n\t\t   const struct switch_port_link *link)\n{\n\tstruct nlattr *p = NULL;\n\tint err = 0;\n\n\tp = nla_nest_start(msg, attr);\n\tif (link->link) {\n\t\tif (nla_put_flag(msg, SWITCH_LINK_FLAG_LINK))\n\t\t\tgoto nla_put_failure;\n\t}\n\tif (link->duplex) {\n\t\tif (nla_put_flag(msg, SWITCH_LINK_FLAG_DUPLEX))\n\t\t\tgoto nla_put_failure;\n\t}\n\tif (link->aneg) {\n\t\tif (nla_put_flag(msg, SWITCH_LINK_FLAG_ANEG))\n\t\t\tgoto nla_put_failure;\n\t}\n\tif (link->tx_flow) {\n\t\tif (nla_put_flag(msg, SWITCH_LINK_FLAG_TX_FLOW))\n\t\t\tgoto nla_put_failure;\n\t}\n\tif (link->rx_flow) {\n\t\tif (nla_put_flag(msg, SWITCH_LINK_FLAG_RX_FLOW))\n\t\t\tgoto nla_put_failure;\n\t}\n\tif (nla_put_u32(msg, SWITCH_LINK_SPEED, link->speed))\n\t\tgoto nla_put_failure;\n\tif (link->eee & ADVERTISED_100baseT_Full) {\n\t\tif (nla_put_flag(msg, SWITCH_LINK_FLAG_EEE_100BASET))\n\t\t\tgoto nla_put_failure;\n\t}\n\tif (link->eee & ADVERTISED_1000baseT_Full) {\n\t\tif (nla_put_flag(msg, SWITCH_LINK_FLAG_EEE_1000BASET))\n\t\t\tgoto nla_put_failure;\n\t}\n\tnla_nest_end(msg, p);\n\n\treturn err;\n\nnla_put_failure:\n\tnla_nest_cancel(msg, p);\n\treturn -1;\n}\n\nstatic int\nswconfig_get_attr(struct sk_buff *skb, struct genl_info *info)\n{\n\tstruct genlmsghdr *hdr = nlmsg_data(info->nlhdr);\n\tconst struct switch_attr *attr;\n\tstruct switch_dev *dev;\n\tstruct sk_buff *msg = NULL;\n\tstruct switch_val val;\n\tint err = -EINVAL;\n\tint cmd = hdr->cmd;\n\n\tdev = swconfig_get_dev(info);\n\tif (!dev)\n\t\treturn -EINVAL;\n\n\tmemset(&val, 0, sizeof(val));\n\tattr = swconfig_lookup_attr(dev, info, &val);\n\tif (!attr || !attr->get)\n\t\tgoto error;\n\n\tif (attr->type == SWITCH_TYPE_PORTS) {\n\t\tval.value.ports = dev->portbuf;\n\t\tmemset(dev->portbuf, 0,\n\t\t\tsizeof(struct switch_port) * dev->ports);\n\t} else if (attr->type == SWITCH_TYPE_LINK) {\n\t\tval.value.link = &dev->linkbuf;\n\t\tmemset(&dev->linkbuf, 0, sizeof(struct switch_port_link));\n\t}\n\n\terr = attr->get(dev, attr, &val);\n\tif (err)\n\t\tgoto error;\n\n\tmsg = nlmsg_new(NLMSG_GOODSIZE, GFP_KERNEL);\n\tif (!msg)\n\t\tgoto error;\n\n\thdr = genlmsg_put(msg, info->snd_portid, info->snd_seq, &switch_fam,\n\t\t\t0, cmd);\n\tif (IS_ERR(hdr))\n\t\tgoto nla_put_failure;\n\n\tswitch (attr->type) {\n\tcase SWITCH_TYPE_INT:\n\t\tif (nla_put_u32(msg, SWITCH_ATTR_OP_VALUE_INT, val.value.i))\n\t\t\tgoto nla_put_failure;\n\t\tbreak;\n\tcase SWITCH_TYPE_STRING:\n\t\tif (nla_put_string(msg, SWITCH_ATTR_OP_VALUE_STR, val.value.s))\n\t\t\tgoto nla_put_failure;\n\t\tbreak;\n\tcase SWITCH_TYPE_PORTS:\n\t\terr = swconfig_send_ports(&msg, info,\n\t\t\t\tSWITCH_ATTR_OP_VALUE_PORTS, &val);\n\t\tif (err < 0)\n\t\t\tgoto nla_put_failure;\n\t\tbreak;\n\tcase SWITCH_TYPE_LINK:\n\t\terr = swconfig_send_link(msg, info,\n\t\t\t\t\t SWITCH_ATTR_OP_VALUE_LINK, val.value.link);\n\t\tif (err < 0)\n\t\t\tgoto nla_put_failure;\n\t\tbreak;\n\tdefault:\n\t\tpr_debug(\"invalid type in attribute\\n\");\n\t\terr = -EINVAL;\n\t\tgoto nla_put_failure;\n\t}\n\tgenlmsg_end(msg, hdr);\n\terr = msg->len;\n\tif (err < 0)\n\t\tgoto nla_put_failure;\n\n\tswconfig_put_dev(dev);\n\treturn genlmsg_reply(msg, info);\n\nnla_put_failure:\n\tif (msg)\n\t\tnlmsg_free(msg);\nerror:\n\tswconfig_put_dev(dev);\n\tif (!err)\n\t\terr = -ENOMEM;\n\treturn err;\n}\n\nstatic int\nswconfig_send_switch(struct sk_buff *msg, u32 pid, u32 seq, int flags,\n\t\tconst struct switch_dev *dev)\n{\n\tstruct nlattr *p = NULL, *m = NULL;\n\tvoid *hdr;\n\tint i;\n\n\thdr = genlmsg_put(msg, pid, seq, &switch_fam, flags,\n\t\t\tSWITCH_CMD_NEW_ATTR);\n\tif (IS_ERR(hdr))\n\t\treturn -1;\n\n\tif (nla_put_u32(msg, SWITCH_ATTR_ID, dev->id))\n\t\tgoto nla_put_failure;\n\tif (nla_put_string(msg, SWITCH_ATTR_DEV_NAME, dev->devname))\n\t\tgoto nla_put_failure;\n\tif (nla_put_string(msg, SWITCH_ATTR_ALIAS, dev->alias))\n\t\tgoto nla_put_failure;\n\tif (nla_put_string(msg, SWITCH_ATTR_NAME, dev->name))\n\t\tgoto nla_put_failure;\n\tif (nla_put_u32(msg, SWITCH_ATTR_VLANS, dev->vlans))\n\t\tgoto nla_put_failure;\n\tif (nla_put_u32(msg, SWITCH_ATTR_PORTS, dev->ports))\n\t\tgoto nla_put_failure;\n\tif (nla_put_u32(msg, SWITCH_ATTR_CPU_PORT, dev->cpu_port))\n\t\tgoto nla_put_failure;\n\n\tm = nla_nest_start(msg, SWITCH_ATTR_PORTMAP);\n\tif (!m)\n\t\tgoto nla_put_failure;\n\tfor (i = 0; i < dev->ports; i++) {\n\t\tp = nla_nest_start(msg, SWITCH_ATTR_PORTS);\n\t\tif (!p)\n\t\t\tcontinue;\n\t\tif (dev->portmap[i].s) {\n\t\t\tif (nla_put_string(msg, SWITCH_PORTMAP_SEGMENT,\n\t\t\t\t\t\tdev->portmap[i].s))\n\t\t\t\tgoto nla_put_failure;\n\t\t\tif (nla_put_u32(msg, SWITCH_PORTMAP_VIRT,\n\t\t\t\t\t\tdev->portmap[i].virt))\n\t\t\t\tgoto nla_put_failure;\n\t\t}\n\t\tnla_nest_end(msg, p);\n\t}\n\tnla_nest_end(msg, m);\n\tgenlmsg_end(msg, hdr);\n\treturn msg->len;\nnla_put_failure:\n\tgenlmsg_cancel(msg, hdr);\n\treturn -EMSGSIZE;\n}\n\nstatic int swconfig_dump_switches(struct sk_buff *skb,\n\t\tstruct netlink_callback *cb)\n{\n\tstruct switch_dev *dev;\n\tint start = cb->args[0];\n\tint idx = 0;\n\n\tswconfig_lock();\n\tlist_for_each_entry(dev, &swdevs, dev_list) {\n\t\tif (++idx <= start)\n\t\t\tcontinue;\n\t\tif (swconfig_send_switch(skb, NETLINK_CB(cb->skb).portid,\n\t\t\t\tcb->nlh->nlmsg_seq, NLM_F_MULTI,\n\t\t\t\tdev) < 0)\n\t\t\tbreak;\n\t}\n\tswconfig_unlock();\n\tcb->args[0] = idx;\n\n\treturn skb->len;\n}\n\nstatic int\nswconfig_done(struct netlink_callback *cb)\n{\n\treturn 0;\n}\n\nstatic struct genl_ops swconfig_ops[] = {\n\t{\n\t\t.cmd = SWITCH_CMD_LIST_GLOBAL,\n\t\t.validate = GENL_DONT_VALIDATE_STRICT | GENL_DONT_VALIDATE_DUMP,\n\t\t.doit = swconfig_list_attrs,\n\t},\n\t{\n\t\t.cmd = SWITCH_CMD_LIST_VLAN,\n\t\t.validate = GENL_DONT_VALIDATE_STRICT | GENL_DONT_VALIDATE_DUMP,\n\t\t.doit = swconfig_list_attrs,\n\t},\n\t{\n\t\t.cmd = SWITCH_CMD_LIST_PORT,\n\t\t.validate = GENL_DONT_VALIDATE_STRICT | GENL_DONT_VALIDATE_DUMP,\n\t\t.doit = swconfig_list_attrs,\n\t},\n\t{\n\t\t.cmd = SWITCH_CMD_GET_GLOBAL,\n\t\t.validate = GENL_DONT_VALIDATE_STRICT | GENL_DONT_VALIDATE_DUMP,\n\t\t.doit = swconfig_get_attr,\n\t},\n\t{\n\t\t.cmd = SWITCH_CMD_GET_VLAN,\n\t\t.validate = GENL_DONT_VALIDATE_STRICT | GENL_DONT_VALIDATE_DUMP,\n\t\t.doit = swconfig_get_attr,\n\t},\n\t{\n\t\t.cmd = SWITCH_CMD_GET_PORT,\n\t\t.validate = GENL_DONT_VALIDATE_STRICT | GENL_DONT_VALIDATE_DUMP,\n\t\t.doit = swconfig_get_attr,\n\t},\n\t{\n\t\t.cmd = SWITCH_CMD_SET_GLOBAL,\n\t\t.validate = GENL_DONT_VALIDATE_STRICT | GENL_DONT_VALIDATE_DUMP,\n\t\t.flags = GENL_ADMIN_PERM,\n\t\t.doit = swconfig_set_attr,\n\t},\n\t{\n\t\t.cmd = SWITCH_CMD_SET_VLAN,\n\t\t.validate = GENL_DONT_VALIDATE_STRICT | GENL_DONT_VALIDATE_DUMP,\n\t\t.flags = GENL_ADMIN_PERM,\n\t\t.doit = swconfig_set_attr,\n\t},\n\t{\n\t\t.cmd = SWITCH_CMD_SET_PORT,\n\t\t.validate = GENL_DONT_VALIDATE_STRICT | GENL_DONT_VALIDATE_DUMP,\n\t\t.flags = GENL_ADMIN_PERM,\n\t\t.doit = swconfig_set_attr,\n\t},\n\t{\n\t\t.cmd = SWITCH_CMD_GET_SWITCH,\n\t\t.validate = GENL_DONT_VALIDATE_STRICT | GENL_DONT_VALIDATE_DUMP,\n\t\t.dumpit = swconfig_dump_switches,\n\t\t.done = swconfig_done,\n\t}\n};\n\nstatic struct genl_family switch_fam = {\n\t.name = \"switch\",\n\t.hdrsize = 0,\n\t.version = 1,\n\t.maxattr = SWITCH_ATTR_MAX,\n\t.policy = switch_policy,\n\t.module = THIS_MODULE,\n\t.ops = swconfig_ops,\n\t.n_ops = ARRAY_SIZE(swconfig_ops),\n};\n\n#ifdef CONFIG_OF\nvoid\nof_switch_load_portmap(struct switch_dev *dev)\n{\n\tstruct device_node *port;\n\n\tif (!dev->of_node)\n\t\treturn;\n\n\tfor_each_child_of_node(dev->of_node, port) {\n\t\tconst __be32 *prop;\n\t\tconst char *segment;\n\t\tint size, phys;\n\n\t\tif (!of_device_is_compatible(port, \"swconfig,port\"))\n\t\t\tcontinue;\n\n\t\tif (of_property_read_string(port, \"swconfig,segment\", &segment))\n\t\t\tcontinue;\n\n\t\tprop = of_get_property(port, \"swconfig,portmap\", &size);\n\t\tif (!prop)\n\t\t\tcontinue;\n\n\t\tif (size != (2 * sizeof(*prop))) {\n\t\t\tpr_err(\"%s: failed to parse port mapping\\n\",\n\t\t\t\t\tport->name);\n\t\t\tcontinue;\n\t\t}\n\n\t\tphys = be32_to_cpup(prop++);\n\t\tif ((phys < 0) | (phys >= dev->ports)) {\n\t\t\tpr_err(\"%s: physical port index out of range\\n\",\n\t\t\t\t\tport->name);\n\t\t\tcontinue;\n\t\t}\n\n\t\tdev->portmap[phys].s = kstrdup(segment, GFP_KERNEL);\n\t\tdev->portmap[phys].virt = be32_to_cpup(prop);\n\t\tpr_debug(\"Found port: %s, physical: %d, virtual: %d\\n\",\n\t\t\tsegment, phys, dev->portmap[phys].virt);\n\t}\n}\n#endif\n\nint\nregister_switch(struct switch_dev *dev, struct net_device *netdev)\n{\n\tstruct switch_dev *sdev;\n\tconst int max_switches = 8 * sizeof(unsigned long);\n\tunsigned long in_use = 0;\n\tint err;\n\tint i;\n\n\tINIT_LIST_HEAD(&dev->dev_list);\n\tif (netdev) {\n\t\tdev->netdev = netdev;\n\t\tif (!dev->alias)\n\t\t\tdev->alias = netdev->name;\n\t}\n\tBUG_ON(!dev->alias);\n\n\t/* Make sure swdev_id doesn't overflow */\n\tif (swdev_id == INT_MAX) {\n\t\treturn -ENOMEM;\n\t}\n\n\tif (dev->ports > 0) {\n\t\tdev->portbuf = kzalloc(sizeof(struct switch_port) *\n\t\t\t\tdev->ports, GFP_KERNEL);\n\t\tif (!dev->portbuf)\n\t\t\treturn -ENOMEM;\n\t\tdev->portmap = kzalloc(sizeof(struct switch_portmap) *\n\t\t\t\tdev->ports, GFP_KERNEL);\n\t\tif (!dev->portmap) {\n\t\t\tkfree(dev->portbuf);\n\t\t\treturn -ENOMEM;\n\t\t}\n\t}\n\tswconfig_defaults_init(dev);\n\tmutex_init(&dev->sw_mutex);\n\tswconfig_lock();\n\tdev->id = ++swdev_id;\n\n\tlist_for_each_entry(sdev, &swdevs, dev_list) {\n\t\tif (!sscanf(sdev->devname, SWCONFIG_DEVNAME, &i))\n\t\t\tcontinue;\n\t\tif (i < 0 || i > max_switches)\n\t\t\tcontinue;\n\n\t\tset_bit(i, &in_use);\n\t}\n\ti = find_first_zero_bit(&in_use, max_switches);\n\n\tif (i == max_switches) {\n\t\tswconfig_unlock();\n\t\treturn -ENFILE;\n\t}\n\n#ifdef CONFIG_OF\n\tif (dev->ports)\n\t\tof_switch_load_portmap(dev);\n#endif\n\n\t/* fill device name */\n\tsnprintf(dev->devname, IFNAMSIZ, SWCONFIG_DEVNAME, i);\n\n\tlist_add_tail(&dev->dev_list, &swdevs);\n\tswconfig_unlock();\n\n\terr = swconfig_create_led_trigger(dev);\n\tif (err)\n\t\treturn err;\n\n\treturn 0;\n}\nEXPORT_SYMBOL_GPL(register_switch);\n\nvoid\nunregister_switch(struct switch_dev *dev)\n{\n\tswconfig_destroy_led_trigger(dev);\n\tkfree(dev->portbuf);\n\tmutex_lock(&dev->sw_mutex);\n\tswconfig_lock();\n\tlist_del(&dev->dev_list);\n\tswconfig_unlock();\n\tmutex_unlock(&dev->sw_mutex);\n}\nEXPORT_SYMBOL_GPL(unregister_switch);\n\nint\nswitch_generic_set_link(struct switch_dev *dev, int port,\n\t\t\tstruct switch_port_link *link)\n{\n\tif (WARN_ON(!dev->ops->phy_write16))\n\t\treturn -ENOTSUPP;\n\n\t/* Generic implementation */\n\tif (link->aneg) {\n\t\tdev->ops->phy_write16(dev, port, MII_BMCR, 0x0000);\n\t\tdev->ops->phy_write16(dev, port, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART);\n\t} else {\n\t\tu16 bmcr = 0;\n\n\t\tif (link->duplex)\n\t\t\tbmcr |= BMCR_FULLDPLX;\n\n\t\tswitch (link->speed) {\n\t\tcase SWITCH_PORT_SPEED_10:\n\t\t\tbreak;\n\t\tcase SWITCH_PORT_SPEED_100:\n\t\t\tbmcr |= BMCR_SPEED100;\n\t\t\tbreak;\n\t\tcase SWITCH_PORT_SPEED_1000:\n\t\t\tbmcr |= BMCR_SPEED1000;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\treturn -ENOTSUPP;\n\t\t}\n\n\t\tdev->ops->phy_write16(dev, port, MII_BMCR, bmcr);\n\t}\n\n\treturn 0;\n}\nEXPORT_SYMBOL_GPL(switch_generic_set_link);\n\nstatic int __init\nswconfig_init(void)\n{\n\tINIT_LIST_HEAD(&swdevs);\n\n\treturn genl_register_family(&switch_fam);\n}\n\nstatic void __exit\nswconfig_exit(void)\n{\n\tgenl_unregister_family(&switch_fam);\n}\n\nmodule_init(swconfig_init);\nmodule_exit(swconfig_exit);\n"
  },
  {
    "path": "target/linux/generic/files/drivers/net/phy/swconfig_leds.c",
    "content": "/*\n * swconfig_led.c: LED trigger support for the switch configuration API\n *\n * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>\n *\n * This program is free software; you can redistribute it and/or\n * modify it under the terms of the GNU General Public License\n * as published by the Free Software Foundation; either version 2\n * of the License, or (at your option) any later version.\n *\n */\n\n#ifdef CONFIG_SWCONFIG_LEDS\n\n#include <linux/leds.h>\n#include <linux/ctype.h>\n#include <linux/device.h>\n#include <linux/workqueue.h>\n\n#define SWCONFIG_LED_TIMER_INTERVAL\t(HZ / 10)\n#define SWCONFIG_LED_NUM_PORTS\t\t32\n\n#define SWCONFIG_LED_PORT_SPEED_NA\t0x01\t/* unknown speed */\n#define SWCONFIG_LED_PORT_SPEED_10\t0x02\t/* 10 Mbps */\n#define SWCONFIG_LED_PORT_SPEED_100\t0x04\t/* 100 Mbps */\n#define SWCONFIG_LED_PORT_SPEED_1000\t0x08\t/* 1000 Mbps */\n#define SWCONFIG_LED_PORT_SPEED_ALL\t(SWCONFIG_LED_PORT_SPEED_NA | \\\n\t\t\t\t\t SWCONFIG_LED_PORT_SPEED_10 | \\\n\t\t\t\t\t SWCONFIG_LED_PORT_SPEED_100 | \\\n\t\t\t\t\t SWCONFIG_LED_PORT_SPEED_1000)\n\n#define SWCONFIG_LED_MODE_LINK\t\t0x01\n#define SWCONFIG_LED_MODE_TX\t\t0x02\n#define SWCONFIG_LED_MODE_RX\t\t0x04\n#define SWCONFIG_LED_MODE_TXRX\t\t(SWCONFIG_LED_MODE_TX   | \\\n\t\t\t\t\t SWCONFIG_LED_MODE_RX)\n#define SWCONFIG_LED_MODE_ALL\t\t(SWCONFIG_LED_MODE_LINK | \\\n\t\t\t\t\t SWCONFIG_LED_MODE_TX   | \\\n\t\t\t\t\t SWCONFIG_LED_MODE_RX)\n\nstruct switch_led_trigger {\n\tstruct led_trigger trig;\n\tstruct switch_dev *swdev;\n\n\tstruct delayed_work sw_led_work;\n\tu32 port_mask;\n\tu32 port_link;\n\tunsigned long long port_tx_traffic[SWCONFIG_LED_NUM_PORTS];\n\tunsigned long long port_rx_traffic[SWCONFIG_LED_NUM_PORTS];\n\tu8 link_speed[SWCONFIG_LED_NUM_PORTS];\n};\n\nstruct swconfig_trig_data {\n\tstruct led_classdev *led_cdev;\n\tstruct switch_dev *swdev;\n\n\trwlock_t lock;\n\tu32 port_mask;\n\n\tbool prev_link;\n\tunsigned long prev_traffic;\n\tenum led_brightness prev_brightness;\n\tu8 mode;\n\tu8 speed_mask;\n};\n\nstatic void\nswconfig_trig_set_brightness(struct swconfig_trig_data *trig_data,\n\t\t\t     enum led_brightness brightness)\n{\n\tled_set_brightness(trig_data->led_cdev, brightness);\n\ttrig_data->prev_brightness = brightness;\n}\n\nstatic void\nswconfig_trig_update_port_mask(struct led_trigger *trigger)\n{\n\tstruct list_head *entry;\n\tstruct switch_led_trigger *sw_trig;\n\tu32 port_mask;\n\n\tif (!trigger)\n\t\treturn;\n\n\tsw_trig = (void *) trigger;\n\n\tport_mask = 0;\n\tread_lock(&trigger->leddev_list_lock);\n\tlist_for_each(entry, &trigger->led_cdevs) {\n\t\tstruct led_classdev *led_cdev;\n\t\tstruct swconfig_trig_data *trig_data;\n\n\t\tled_cdev = list_entry(entry, struct led_classdev, trig_list);\n\t\ttrig_data = led_cdev->trigger_data;\n\t\tif (trig_data) {\n\t\t\tread_lock(&trig_data->lock);\n\t\t\tport_mask |= trig_data->port_mask;\n\t\t\tread_unlock(&trig_data->lock);\n\t\t}\n\t}\n\tread_unlock(&trigger->leddev_list_lock);\n\n\tsw_trig->port_mask = port_mask;\n\n\tif (port_mask)\n\t\tschedule_delayed_work(&sw_trig->sw_led_work,\n\t\t\t\t      SWCONFIG_LED_TIMER_INTERVAL);\n\telse\n\t\tcancel_delayed_work_sync(&sw_trig->sw_led_work);\n}\n\nstatic ssize_t\nswconfig_trig_port_mask_store(struct device *dev, struct device_attribute *attr,\n\t\t\t      const char *buf, size_t size)\n{\n\tstruct led_classdev *led_cdev = dev_get_drvdata(dev);\n\tstruct swconfig_trig_data *trig_data = led_cdev->trigger_data;\n\tunsigned long port_mask;\n\tint ret;\n\tbool changed;\n\n\tret = kstrtoul(buf, 0, &port_mask);\n\tif (ret)\n\t\treturn ret;\n\n\twrite_lock(&trig_data->lock);\n\tchanged = (trig_data->port_mask != port_mask);\n\ttrig_data->port_mask = port_mask;\n\twrite_unlock(&trig_data->lock);\n\n\tif (changed) {\n\t\tif (port_mask == 0)\n\t\t\tswconfig_trig_set_brightness(trig_data, LED_OFF);\n\n\t\tswconfig_trig_update_port_mask(led_cdev->trigger);\n\t}\n\n\treturn size;\n}\n\nstatic ssize_t\nswconfig_trig_port_mask_show(struct device *dev, struct device_attribute *attr,\n\t\t\t     char *buf)\n{\n\tstruct led_classdev *led_cdev = dev_get_drvdata(dev);\n\tstruct swconfig_trig_data *trig_data = led_cdev->trigger_data;\n\tu32 port_mask;\n\n\tread_lock(&trig_data->lock);\n\tport_mask = trig_data->port_mask;\n\tread_unlock(&trig_data->lock);\n\n\tsprintf(buf, \"%#x\\n\", port_mask);\n\n\treturn strlen(buf) + 1;\n}\n\nstatic DEVICE_ATTR(port_mask, 0644, swconfig_trig_port_mask_show,\n\t\t   swconfig_trig_port_mask_store);\n\n/* speed_mask file handler - display value */\nstatic ssize_t swconfig_trig_speed_mask_show(struct device *dev,\n\t\t\t\t\t     struct device_attribute *attr,\n\t\t\t\t\t     char *buf)\n{\n\tstruct led_classdev *led_cdev = dev_get_drvdata(dev);\n\tstruct swconfig_trig_data *trig_data = led_cdev->trigger_data;\n\tu8 speed_mask;\n\n\tread_lock(&trig_data->lock);\n\tspeed_mask = trig_data->speed_mask;\n\tread_unlock(&trig_data->lock);\n\n\tsprintf(buf, \"%#x\\n\", speed_mask);\n\n\treturn strlen(buf) + 1;\n}\n\n/* speed_mask file handler - store value */\nstatic ssize_t swconfig_trig_speed_mask_store(struct device *dev,\n\t\t\t\t\t      struct device_attribute *attr,\n\t\t\t\t\t      const char *buf, size_t size)\n{\n\tstruct led_classdev *led_cdev = dev_get_drvdata(dev);\n\tstruct swconfig_trig_data *trig_data = led_cdev->trigger_data;\n\tu8 speed_mask;\n\tint ret;\n\n\tret = kstrtou8(buf, 0, &speed_mask);\n\tif (ret)\n\t\treturn ret;\n\n\twrite_lock(&trig_data->lock);\n\ttrig_data->speed_mask = speed_mask & SWCONFIG_LED_PORT_SPEED_ALL;\n\twrite_unlock(&trig_data->lock);\n\n\treturn size;\n}\n\n/* speed_mask special file */\nstatic DEVICE_ATTR(speed_mask, 0644, swconfig_trig_speed_mask_show,\n\t\t   swconfig_trig_speed_mask_store);\n\nstatic ssize_t swconfig_trig_mode_show(struct device *dev,\n\t\tstruct device_attribute *attr, char *buf)\n{\n\tstruct led_classdev *led_cdev = dev_get_drvdata(dev);\n\tstruct swconfig_trig_data *trig_data = led_cdev->trigger_data;\n\tu8 mode;\n\n\tread_lock(&trig_data->lock);\n\tmode = trig_data->mode;\n\tread_unlock(&trig_data->lock);\n\n\tif (mode == 0) {\n\t\tstrcpy(buf, \"none\\n\");\n\t} else {\n\t\tif (mode & SWCONFIG_LED_MODE_LINK)\n\t\t\tstrcat(buf, \"link \");\n\t\tif (mode & SWCONFIG_LED_MODE_TX)\n\t\t\tstrcat(buf, \"tx \");\n\t\tif (mode & SWCONFIG_LED_MODE_RX)\n\t\t\tstrcat(buf, \"rx \");\n\t\tstrcat(buf, \"\\n\");\n\t}\n\n\treturn strlen(buf)+1;\n}\n\nstatic ssize_t swconfig_trig_mode_store(struct device *dev,\n\t\tstruct device_attribute *attr, const char *buf, size_t size)\n{\n\tstruct led_classdev *led_cdev = dev_get_drvdata(dev);\n\tstruct swconfig_trig_data *trig_data = led_cdev->trigger_data;\n\tchar copybuf[128];\n\tint new_mode = -1;\n\tchar *p, *token;\n\n\t/* take a copy since we don't want to trash the inbound buffer when using strsep */\n\tstrncpy(copybuf, buf, sizeof(copybuf));\n\tcopybuf[sizeof(copybuf) - 1] = 0;\n\tp = copybuf;\n\n\twhile ((token = strsep(&p, \" \\t\\n\")) != NULL) {\n\t\tif (!*token)\n\t\t\tcontinue;\n\n\t\tif (new_mode < 0)\n\t\t\tnew_mode = 0;\n\n\t\tif (!strcmp(token, \"none\"))\n\t\t\tnew_mode = 0;\n\t\telse if (!strcmp(token, \"tx\"))\n\t\t\tnew_mode |= SWCONFIG_LED_MODE_TX;\n\t\telse if (!strcmp(token, \"rx\"))\n\t\t\tnew_mode |= SWCONFIG_LED_MODE_RX;\n\t\telse if (!strcmp(token, \"link\"))\n\t\t\tnew_mode |= SWCONFIG_LED_MODE_LINK;\n\t\telse\n\t\t\treturn -EINVAL;\n\t}\n\n\tif (new_mode < 0)\n\t\treturn -EINVAL;\n\n\twrite_lock(&trig_data->lock);\n\ttrig_data->mode = (u8)new_mode;\n\twrite_unlock(&trig_data->lock);\n\n\treturn size;\n}\n\n/* mode special file */\nstatic DEVICE_ATTR(mode, 0644, swconfig_trig_mode_show,\n\t\t   swconfig_trig_mode_store);\n\nstatic int\nswconfig_trig_activate(struct led_classdev *led_cdev)\n{\n\tstruct switch_led_trigger *sw_trig;\n\tstruct swconfig_trig_data *trig_data;\n\tint err;\n\n\ttrig_data = kzalloc(sizeof(struct swconfig_trig_data), GFP_KERNEL);\n\tif (!trig_data)\n\t\treturn -ENOMEM;\n\n\tsw_trig = (void *) led_cdev->trigger;\n\n\trwlock_init(&trig_data->lock);\n\ttrig_data->led_cdev = led_cdev;\n\ttrig_data->swdev = sw_trig->swdev;\n\ttrig_data->speed_mask = SWCONFIG_LED_PORT_SPEED_ALL;\n\ttrig_data->mode = SWCONFIG_LED_MODE_ALL;\n\tled_cdev->trigger_data = trig_data;\n\n\terr = device_create_file(led_cdev->dev, &dev_attr_port_mask);\n\tif (err)\n\t\tgoto err_free;\n\n\terr = device_create_file(led_cdev->dev, &dev_attr_speed_mask);\n\tif (err)\n\t\tgoto err_dev_free;\n\n\terr = device_create_file(led_cdev->dev, &dev_attr_mode);\n\tif (err)\n\t\tgoto err_mode_free;\n\n\treturn 0;\n\nerr_mode_free:\n\tdevice_remove_file(led_cdev->dev, &dev_attr_speed_mask);\n\nerr_dev_free:\n\tdevice_remove_file(led_cdev->dev, &dev_attr_port_mask);\n\nerr_free:\n\tled_cdev->trigger_data = NULL;\n\tkfree(trig_data);\n\n\treturn err;\n}\n\nstatic void\nswconfig_trig_deactivate(struct led_classdev *led_cdev)\n{\n\tstruct swconfig_trig_data *trig_data;\n\n\tswconfig_trig_update_port_mask(led_cdev->trigger);\n\n\ttrig_data = (void *) led_cdev->trigger_data;\n\tif (trig_data) {\n\t\tdevice_remove_file(led_cdev->dev, &dev_attr_port_mask);\n\t\tdevice_remove_file(led_cdev->dev, &dev_attr_speed_mask);\n\t\tdevice_remove_file(led_cdev->dev, &dev_attr_mode);\n\t\tkfree(trig_data);\n\t}\n}\n\n/*\n * link off -> led off (can't be any other reason to turn it on)\n * link on:\n *\tmode link: led on by default only if speed matches, else off\n *\tmode txrx: blink only if speed matches, else off\n */\nstatic void\nswconfig_trig_led_event(struct switch_led_trigger *sw_trig,\n\t\t\tstruct led_classdev *led_cdev)\n{\n\tstruct swconfig_trig_data *trig_data;\n\tu32 port_mask;\n\tbool link;\n\tu8 speed_mask, mode;\n\tenum led_brightness led_base, led_blink;\n\n\ttrig_data = led_cdev->trigger_data;\n\tif (!trig_data)\n\t\treturn;\n\n\tread_lock(&trig_data->lock);\n\tport_mask = trig_data->port_mask;\n\tspeed_mask = trig_data->speed_mask;\n\tmode = trig_data->mode;\n\tread_unlock(&trig_data->lock);\n\n\tlink = !!(sw_trig->port_link & port_mask);\n\tif (!link) {\n\t\tif (trig_data->prev_brightness != LED_OFF)\n\t\t\tswconfig_trig_set_brightness(trig_data, LED_OFF); /* and stop */\n\t}\n\telse {\n\t\tunsigned long traffic;\n\t\tint speedok;\t/* link speed flag */\n\t\tint i;\n\n\t\tled_base = LED_FULL;\n\t\tled_blink = LED_OFF;\n\t\ttraffic = 0;\n\t\tspeedok = 0;\n\t\tfor (i = 0; i < SWCONFIG_LED_NUM_PORTS; i++) {\n\t\t\tif (port_mask & (1 << i)) {\n\t\t\t\tif (sw_trig->link_speed[i] & speed_mask) {\n\t\t\t\t\ttraffic += ((mode & SWCONFIG_LED_MODE_TX) ?\n\t\t\t\t\t\t    sw_trig->port_tx_traffic[i] : 0) +\n\t\t\t\t\t\t((mode & SWCONFIG_LED_MODE_RX) ?\n\t\t\t\t\t\t sw_trig->port_rx_traffic[i] : 0);\n\t\t\t\t\tspeedok = 1;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n\t\tif (speedok) {\n\t\t\t/* At least one port speed matches speed_mask */\n\t\t\tif (!(mode & SWCONFIG_LED_MODE_LINK)) {\n\t\t\t\tled_base = LED_OFF;\n\t\t\t\tled_blink = LED_FULL;\n\t\t\t}\n\n\t\t\tif (trig_data->prev_brightness != led_base)\n\t\t\t\tswconfig_trig_set_brightness(trig_data,\n\t\t\t\t\t\t\t     led_base);\n\t\t\telse if (traffic != trig_data->prev_traffic)\n\t\t\t\tswconfig_trig_set_brightness(trig_data,\n\t\t\t\t\t\t\t     led_blink);\n\t\t} else if (trig_data->prev_brightness != LED_OFF)\n\t\t\tswconfig_trig_set_brightness(trig_data, LED_OFF);\n\n\t\ttrig_data->prev_traffic = traffic;\n\t}\n\n\ttrig_data->prev_link = link;\n}\n\nstatic void\nswconfig_trig_update_leds(struct switch_led_trigger *sw_trig)\n{\n\tstruct list_head *entry;\n\tstruct led_trigger *trigger;\n\n\ttrigger = &sw_trig->trig;\n\tread_lock(&trigger->leddev_list_lock);\n\tlist_for_each(entry, &trigger->led_cdevs) {\n\t\tstruct led_classdev *led_cdev;\n\n\t\tled_cdev = list_entry(entry, struct led_classdev, trig_list);\n\t\tswconfig_trig_led_event(sw_trig, led_cdev);\n\t}\n\tread_unlock(&trigger->leddev_list_lock);\n}\n\nstatic void\nswconfig_led_work_func(struct work_struct *work)\n{\n\tstruct switch_led_trigger *sw_trig;\n\tstruct switch_dev *swdev;\n\tu32 port_mask;\n\tu32 link;\n\tint i;\n\n\tsw_trig = container_of(work, struct switch_led_trigger,\n\t\t\t       sw_led_work.work);\n\n\tport_mask = sw_trig->port_mask;\n\tswdev = sw_trig->swdev;\n\n\tlink = 0;\n\tfor (i = 0; i < SWCONFIG_LED_NUM_PORTS; i++) {\n\t\tu32 port_bit;\n\n\t\tsw_trig->link_speed[i] = 0;\n\n\t\tport_bit = BIT(i);\n\t\tif ((port_mask & port_bit) == 0)\n\t\t\tcontinue;\n\n\t\tif (swdev->ops->get_port_link) {\n\t\t\tstruct switch_port_link port_link;\n\n\t\t\tmemset(&port_link, '\\0', sizeof(port_link));\n\t\t\tswdev->ops->get_port_link(swdev, i, &port_link);\n\n\t\t\tif (port_link.link) {\n\t\t\t\tlink |= port_bit;\n\t\t\t\tswitch (port_link.speed) {\n\t\t\t\tcase SWITCH_PORT_SPEED_UNKNOWN:\n\t\t\t\t\tsw_trig->link_speed[i] =\n\t\t\t\t\t\tSWCONFIG_LED_PORT_SPEED_NA;\n\t\t\t\t\tbreak;\n\t\t\t\tcase SWITCH_PORT_SPEED_10:\n\t\t\t\t\tsw_trig->link_speed[i] =\n\t\t\t\t\t\tSWCONFIG_LED_PORT_SPEED_10;\n\t\t\t\t\tbreak;\n\t\t\t\tcase SWITCH_PORT_SPEED_100:\n\t\t\t\t\tsw_trig->link_speed[i] =\n\t\t\t\t\t\tSWCONFIG_LED_PORT_SPEED_100;\n\t\t\t\t\tbreak;\n\t\t\t\tcase SWITCH_PORT_SPEED_1000:\n\t\t\t\t\tsw_trig->link_speed[i] =\n\t\t\t\t\t\tSWCONFIG_LED_PORT_SPEED_1000;\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n\t\tif (swdev->ops->get_port_stats) {\n\t\t\tstruct switch_port_stats port_stats;\n\n\t\t\tmemset(&port_stats, '\\0', sizeof(port_stats));\n\t\t\tswdev->ops->get_port_stats(swdev, i, &port_stats);\n\t\t\tsw_trig->port_tx_traffic[i] = port_stats.tx_bytes;\n\t\t\tsw_trig->port_rx_traffic[i] = port_stats.rx_bytes;\n\t\t}\n\t}\n\n\tsw_trig->port_link = link;\n\n\tswconfig_trig_update_leds(sw_trig);\n\n\tschedule_delayed_work(&sw_trig->sw_led_work,\n\t\t\t      SWCONFIG_LED_TIMER_INTERVAL);\n}\n\nstatic int\nswconfig_create_led_trigger(struct switch_dev *swdev)\n{\n\tstruct switch_led_trigger *sw_trig;\n\tint err;\n\n\tif (!swdev->ops->get_port_link)\n\t\treturn 0;\n\n\tsw_trig = kzalloc(sizeof(struct switch_led_trigger), GFP_KERNEL);\n\tif (!sw_trig)\n\t\treturn -ENOMEM;\n\n\tsw_trig->swdev = swdev;\n\tsw_trig->trig.name = swdev->devname;\n\tsw_trig->trig.activate = swconfig_trig_activate;\n\tsw_trig->trig.deactivate = swconfig_trig_deactivate;\n\n\tINIT_DELAYED_WORK(&sw_trig->sw_led_work, swconfig_led_work_func);\n\n\terr = led_trigger_register(&sw_trig->trig);\n\tif (err)\n\t\tgoto err_free;\n\n\tswdev->led_trigger = sw_trig;\n\n\treturn 0;\n\nerr_free:\n\tkfree(sw_trig);\n\treturn err;\n}\n\nstatic void\nswconfig_destroy_led_trigger(struct switch_dev *swdev)\n{\n\tstruct switch_led_trigger *sw_trig;\n\n\tsw_trig = swdev->led_trigger;\n\tif (sw_trig) {\n\t\tcancel_delayed_work_sync(&sw_trig->sw_led_work);\n\t\tled_trigger_unregister(&sw_trig->trig);\n\t\tkfree(sw_trig);\n\t}\n}\n\n#else /* SWCONFIG_LEDS */\nstatic inline int\nswconfig_create_led_trigger(struct switch_dev *swdev) { return 0; }\n\nstatic inline void\nswconfig_destroy_led_trigger(struct switch_dev *swdev) { }\n#endif /* CONFIG_SWCONFIG_LEDS */\n"
  },
  {
    "path": "target/linux/generic/files/drivers/platform/mikrotik/Kconfig",
    "content": "menuconfig MIKROTIK\n\tbool \"Platform support for MikroTik RouterBoard virtual devices\"\n\tdefault n\n\thelp\n\t  Say Y here to get to see options for the MikroTik RouterBoard platform.\n\t  This option alone does not add any kernel code.\n\n\nif MIKROTIK\n\nconfig MIKROTIK_RB_SYSFS\n\ttristate \"RouterBoot sysfs support\"\n\tdepends on MTD\n\tselect LZO_DECOMPRESS\n\tselect CRC32\n\thelp\n\t  This driver exposes RouterBoot configuration in sysfs.\n\nendif # MIKROTIK\n"
  },
  {
    "path": "target/linux/generic/files/drivers/platform/mikrotik/Makefile",
    "content": "#\n# Makefile for MikroTik RouterBoard platform specific drivers\n#\nobj-$(CONFIG_MIKROTIK_RB_SYSFS)     += routerboot.o rb_hardconfig.o rb_softconfig.o\n"
  },
  {
    "path": "target/linux/generic/files/drivers/platform/mikrotik/rb_hardconfig.c",
    "content": "// SPDX-License-Identifier: GPL-2.0-only\n/*\n * Driver for MikroTik RouterBoot hard config.\n *\n * Copyright (C) 2020 Thibaut VARÈNE <hacks+kernel@slashdirt.org>\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of the GNU General Public License version 2 as published\n * by the Free Software Foundation.\n *\n * This driver exposes the data encoded in the \"hard_config\" flash segment of\n * MikroTik RouterBOARDs devices. It presents the data in a sysfs folder\n * named \"hard_config\". The WLAN calibration data is available on demand via\n * the 'wlan_data' sysfs file in that folder.\n *\n * This driver permanently allocates a chunk of RAM as large as the hard_config\n * MTD partition, although it is technically possible to operate entirely from\n * the MTD device without using a local buffer (except when requesting WLAN\n * calibration data), at the cost of a performance penalty.\n *\n * Note: PAGE_SIZE is assumed to be >= 4K, hence the device attribute show\n * routines need not check for output overflow.\n *\n * Some constant defines extracted from routerboot.{c,h} by Gabor Juhos\n * <juhosg@openwrt.org>\n */\n\n#include <linux/types.h>\n#include <linux/init.h>\n#include <linux/kernel.h>\n#include <linux/slab.h>\n#include <linux/errno.h>\n#include <linux/kobject.h>\n#include <linux/bitops.h>\n#include <linux/string.h>\n#include <linux/mtd/mtd.h>\n#include <linux/sysfs.h>\n#include <linux/lzo.h>\n\n#include \"routerboot.h\"\n\n#define RB_HARDCONFIG_VER\t\t\"0.07\"\n#define RB_HC_PR_PFX\t\t\t\"[rb_hardconfig] \"\n\n/* ID values for hardware settings */\n#define RB_ID_FLASH_INFO\t\t0x03\n#define RB_ID_MAC_ADDRESS_PACK\t\t0x04\n#define RB_ID_BOARD_PRODUCT_CODE\t0x05\n#define RB_ID_BIOS_VERSION\t\t0x06\n#define RB_ID_SDRAM_TIMINGS\t\t0x08\n#define RB_ID_DEVICE_TIMINGS\t\t0x09\n#define RB_ID_SOFTWARE_ID\t\t0x0A\n#define RB_ID_SERIAL_NUMBER\t\t0x0B\n#define RB_ID_MEMORY_SIZE\t\t0x0D\n#define RB_ID_MAC_ADDRESS_COUNT\t\t0x0E\n#define RB_ID_HW_OPTIONS\t\t0x15\n#define RB_ID_WLAN_DATA\t\t\t0x16\n#define RB_ID_BOARD_IDENTIFIER\t\t0x17\n#define RB_ID_PRODUCT_NAME\t\t0x21\n#define RB_ID_DEFCONF\t\t\t0x26\n#define RB_ID_BOARD_REVISION\t\t0x27\n\n/* Bit definitions for hardware options */\n#define RB_HW_OPT_NO_UART\t\tBIT(0)\n#define RB_HW_OPT_HAS_VOLTAGE\t\tBIT(1)\n#define RB_HW_OPT_HAS_USB\t\tBIT(2)\n#define RB_HW_OPT_HAS_ATTINY\t\tBIT(3)\n#define RB_HW_OPT_PULSE_DUTY_CYCLE\tBIT(9)\n#define RB_HW_OPT_NO_NAND\t\tBIT(14)\n#define RB_HW_OPT_HAS_LCD\t\tBIT(15)\n#define RB_HW_OPT_HAS_POE_OUT\t\tBIT(16)\n#define RB_HW_OPT_HAS_uSD\t\tBIT(17)\n#define RB_HW_OPT_HAS_SIM\t\tBIT(18)\n#define RB_HW_OPT_HAS_SFP\t\tBIT(20)\n#define RB_HW_OPT_HAS_WIFI\t\tBIT(21)\n#define RB_HW_OPT_HAS_TS_FOR_ADC\tBIT(22)\n#define RB_HW_OPT_HAS_PLC\t\tBIT(29)\n\n/*\n * Tag ID values for ERD data.\n * Mikrotik used to pack all calibration data under a single tag id 0x1, but\n * recently switched to a new scheme where each radio calibration gets a\n * separate tag. The new scheme has tag id bit 15 always set and seems to be\n * mutually exclusive with the old scheme.\n */\n#define RB_WLAN_ERD_ID_SOLO\t\t0x0001\n#define RB_WLAN_ERD_ID_MULTI_8001\t0x8001\n#define RB_WLAN_ERD_ID_MULTI_8201\t0x8201\n\nstatic struct kobject *hc_kobj;\nstatic u8 *hc_buf;\t\t// ro buffer after init(): no locking required\nstatic size_t hc_buflen;\n\n/*\n * For LZOR style WLAN data unpacking.\n * This binary blob is prepended to the data encoded on some devices as\n * RB_ID_WLAN_DATA, the result is then first decompressed with LZO, and then\n * finally RLE-decoded.\n * This binary blob has been extracted from RouterOS by\n * https://forum.openwrt.org/u/ius\n */\nstatic const u8 hc_lzor_prefix[] = {\n\t0x00, 0x05, 0x4c, 0x4c, 0x44, 0x00, 0x34, 0xfe,\n\t0xfe, 0x34, 0x11, 0x3c, 0x1e, 0x3c, 0x2e, 0x3c,\n\t0x4c, 0x34, 0x00, 0x52, 0x62, 0x92, 0xa2, 0xb2,\n\t0xc3, 0x2a, 0x14, 0x00, 0x00, 0x05, 0xfe, 0x6a,\n\t0x3c, 0x16, 0x32, 0x16, 0x11, 0x1e, 0x12, 0x46,\n\t0x32, 0x46, 0x11, 0x4e, 0x12, 0x36, 0x32, 0x36,\n\t0x11, 0x3e, 0x12, 0x5a, 0x9a, 0x64, 0x00, 0x04,\n\t0xfe, 0x10, 0x3c, 0x00, 0x01, 0x00, 0x00, 0x28,\n\t0x0c, 0x00, 0x0f, 0xfe, 0x14, 0x00, 0x24, 0x24,\n\t0x23, 0x24, 0x24, 0x23, 0x25, 0x22, 0x21, 0x21,\n\t0x23, 0x22, 0x21, 0x22, 0x21, 0x2d, 0x38, 0x00,\n\t0x0c, 0x25, 0x25, 0x24, 0x25, 0x25, 0x24, 0x23,\n\t0x22, 0x21, 0x20, 0x23, 0x21, 0x21, 0x22, 0x21,\n\t0x2d, 0x38, 0x00, 0x28, 0xb0, 0x00, 0x00, 0x22,\n\t0x00, 0x00, 0xc0, 0xfe, 0x03, 0x00, 0xc0, 0x00,\n\t0x62, 0xff, 0x62, 0xff, 0xfe, 0x06, 0x00, 0xbb,\n\t0xff, 0xba, 0xff, 0xfe, 0x08, 0x00, 0x9e, 0xff,\n\t0xfe, 0x0a, 0x00, 0x53, 0xff, 0xfe, 0x02, 0x00,\n\t0x20, 0xff, 0xb1, 0xfe, 0xfe, 0xb2, 0xfe, 0xfe,\n\t0xed, 0xfe, 0xfe, 0xfe, 0x04, 0x00, 0x3a, 0xff,\n\t0x3a, 0xff, 0xde, 0xfd, 0x5f, 0x04, 0x33, 0xff,\n\t0x4c, 0x74, 0x03, 0x05, 0x05, 0xff, 0x6d, 0xfe,\n\t0xfe, 0x6d, 0xfe, 0xfe, 0xaf, 0x08, 0x63, 0xff,\n\t0x64, 0x6f, 0x08, 0xac, 0xff, 0xbf, 0x6d, 0x08,\n\t0x7a, 0x6d, 0x08, 0x96, 0x74, 0x04, 0x00, 0x08,\n\t0x79, 0xff, 0xda, 0xfe, 0xfe, 0xdb, 0xfe, 0xfe,\n\t0x56, 0xff, 0xfe, 0x04, 0x00, 0x5e, 0xff, 0x5e,\n\t0xff, 0x6c, 0xfe, 0xfe, 0xfe, 0x06, 0x00, 0x41,\n\t0xff, 0x7f, 0x74, 0x03, 0x00, 0x11, 0x44, 0xff,\n\t0xa9, 0xfe, 0xfe, 0xa9, 0xfe, 0xfe, 0xa5, 0x8f,\n\t0x01, 0x00, 0x08, 0x01, 0x01, 0x02, 0x04, 0x08,\n\t0x02, 0x04, 0x08, 0x08, 0x01, 0x01, 0xfe, 0x22,\n\t0x00, 0x4c, 0x60, 0x64, 0x8c, 0x90, 0xd0, 0xd4,\n\t0xd8, 0x5c, 0x10, 0x09, 0xd8, 0xff, 0xb0, 0xff,\n\t0x00, 0x00, 0xba, 0xff, 0x14, 0x00, 0xba, 0xff,\n\t0x64, 0x00, 0x00, 0x08, 0xfe, 0x06, 0x00, 0x74,\n\t0xff, 0x42, 0xff, 0xce, 0xff, 0x60, 0xff, 0x0a,\n\t0x00, 0xb4, 0x00, 0xa0, 0x00, 0xa0, 0xfe, 0x07,\n\t0x00, 0x0a, 0x00, 0xb0, 0xff, 0x96, 0x4d, 0x00,\n\t0x56, 0x57, 0x18, 0xa6, 0xff, 0x92, 0x70, 0x11,\n\t0x00, 0x12, 0x90, 0x90, 0x76, 0x5a, 0x54, 0x54,\n\t0x4c, 0x46, 0x38, 0x00, 0x10, 0x10, 0x08, 0xfe,\n\t0x05, 0x00, 0x38, 0x29, 0x25, 0x23, 0x22, 0x22,\n\t0x1f, 0x00, 0x00, 0x00, 0xf6, 0xe1, 0xdd, 0xf8,\n\t0xfe, 0x00, 0xfe, 0x15, 0x00, 0x00, 0xd0, 0x02,\n\t0x74, 0x02, 0x08, 0xf8, 0xe5, 0xde, 0x02, 0x04,\n\t0x04, 0xfd, 0x00, 0x00, 0x00, 0x07, 0x50, 0x2d,\n\t0x01, 0x90, 0x90, 0x76, 0x60, 0xb0, 0x07, 0x07,\n\t0x0c, 0x0c, 0x04, 0xfe, 0x05, 0x00, 0x66, 0x66,\n\t0x5a, 0x56, 0xbc, 0x01, 0x06, 0xfc, 0xfc, 0xf1,\n\t0xfe, 0x07, 0x00, 0x24, 0x95, 0x70, 0x64, 0x18,\n\t0x06, 0x2c, 0xff, 0xb5, 0xfe, 0xfe, 0xb5, 0xfe,\n\t0xfe, 0xe2, 0x8c, 0x24, 0x02, 0x2f, 0xff, 0x2f,\n\t0xff, 0xb4, 0x78, 0x02, 0x05, 0x73, 0xff, 0xed,\n\t0xfe, 0xfe, 0x4f, 0xff, 0x36, 0x74, 0x1e, 0x09,\n\t0x4f, 0xff, 0x50, 0xff, 0xfe, 0x16, 0x00, 0x70,\n\t0xac, 0x70, 0x8e, 0xac, 0x40, 0x0e, 0x01, 0x70,\n\t0x7f, 0x8e, 0xac, 0x6c, 0x00, 0x0b, 0xfe, 0x02,\n\t0x00, 0xfe, 0x0a, 0x2c, 0x2a, 0x2a, 0x28, 0x26,\n\t0x1e, 0x1e, 0xfe, 0x02, 0x20, 0x65, 0x20, 0x00,\n\t0x00, 0x05, 0x12, 0x00, 0x11, 0x1e, 0x11, 0x11,\n\t0x41, 0x1e, 0x41, 0x11, 0x31, 0x1e, 0x31, 0x11,\n\t0x70, 0x75, 0x7a, 0x7f, 0x84, 0x89, 0x8e, 0x93,\n\t0x98, 0x30, 0x20, 0x00, 0x02, 0x00, 0xfe, 0x06,\n\t0x3c, 0xbc, 0x32, 0x0c, 0x00, 0x00, 0x2a, 0x12,\n\t0x1e, 0x12, 0x2e, 0x12, 0xcc, 0x12, 0x11, 0x1a,\n\t0x1e, 0x1a, 0x2e, 0x1a, 0x4c, 0x10, 0x1e, 0x10,\n\t0x11, 0x18, 0x1e, 0x42, 0x1e, 0x42, 0x2e, 0x42,\n\t0xcc, 0x42, 0x11, 0x4a, 0x1e, 0x4a, 0x2e, 0x4a,\n\t0x4c, 0x40, 0x1e, 0x40, 0x11, 0x48, 0x1e, 0x32,\n\t0x1e, 0x32, 0x2e, 0x32, 0xcc, 0x32, 0x11, 0x3a,\n\t0x1e, 0x3a, 0x2e, 0x3a, 0x4c, 0x30, 0x1e, 0x30,\n\t0x11, 0x38, 0x1e, 0x27, 0x9a, 0x01, 0x9d, 0xa2,\n\t0x2f, 0x28, 0x00, 0x00, 0x46, 0xde, 0xc4, 0xbf,\n\t0xa6, 0x9d, 0x81, 0x7b, 0x5c, 0x61, 0x40, 0xc7,\n\t0xc0, 0xae, 0xa9, 0x8c, 0x83, 0x6a, 0x62, 0x50,\n\t0x3e, 0xce, 0xc2, 0xae, 0xa3, 0x8c, 0x7b, 0x6a,\n\t0x5a, 0x50, 0x35, 0xd7, 0xc2, 0xb7, 0xa4, 0x95,\n\t0x7e, 0x72, 0x5a, 0x59, 0x37, 0xfe, 0x02, 0xf8,\n\t0x8c, 0x95, 0x90, 0x8f, 0x00, 0xd7, 0xc0, 0xb7,\n\t0xa2, 0x95, 0x7b, 0x72, 0x56, 0x59, 0x32, 0xc7,\n\t0xc3, 0xae, 0xad, 0x8c, 0x85, 0x6a, 0x63, 0x50,\n\t0x3e, 0xce, 0xc3, 0xae, 0xa4, 0x8c, 0x7c, 0x6a,\n\t0x59, 0x50, 0x34, 0xd7, 0xc2, 0xb7, 0xa5, 0x95,\n\t0x7e, 0x72, 0x59, 0x59, 0x36, 0xfc, 0x05, 0x00,\n\t0x02, 0xce, 0xc5, 0xae, 0xa5, 0x95, 0x83, 0x72,\n\t0x5c, 0x59, 0x36, 0xbf, 0xc6, 0xa5, 0xab, 0x8c,\n\t0x8c, 0x6a, 0x67, 0x50, 0x41, 0x64, 0x07, 0x00,\n\t0x02, 0x95, 0x8c, 0x72, 0x65, 0x59, 0x3f, 0xce,\n\t0xc7, 0xae, 0xa8, 0x95, 0x86, 0x72, 0x5f, 0x59,\n\t0x39, 0xfe, 0x02, 0xf8, 0x8b, 0x7c, 0x0b, 0x09,\n\t0xb7, 0xc2, 0x9d, 0xa4, 0x83, 0x85, 0x6a, 0x6b,\n\t0x50, 0x44, 0xb7, 0xc1, 0x64, 0x01, 0x00, 0x06,\n\t0x61, 0x5d, 0x48, 0x3d, 0xae, 0xc4, 0x9d, 0xad,\n\t0x7b, 0x85, 0x61, 0x66, 0x48, 0x46, 0xae, 0xc3,\n\t0x95, 0xa3, 0x72, 0x7c, 0x59, 0x56, 0x38, 0x31,\n\t0x7c, 0x0b, 0x00, 0x0c, 0x96, 0x91, 0x8f, 0x00,\n\t0xb7, 0xc0, 0xa5, 0xab, 0x8c, 0x8a, 0x6a, 0x64,\n\t0x50, 0x3c, 0xb7, 0xc0, 0x9d, 0xa0, 0x83, 0x80,\n\t0x6a, 0x64, 0x50, 0x3d, 0xb7, 0xc5, 0x9d, 0xa5,\n\t0x83, 0x87, 0x6c, 0x08, 0x07, 0xae, 0xc0, 0x9d,\n\t0xa8, 0x83, 0x88, 0x6a, 0x6d, 0x50, 0x46, 0xfc,\n\t0x05, 0x00, 0x16, 0xbf, 0xc0, 0xa5, 0xa2, 0x8c,\n\t0x7f, 0x6a, 0x57, 0x50, 0x2f, 0xb7, 0xc7, 0xa5,\n\t0xb1, 0x8c, 0x8e, 0x72, 0x6d, 0x59, 0x45, 0xbf,\n\t0xc6, 0xa5, 0xa8, 0x8c, 0x87, 0x6a, 0x5f, 0x50,\n\t0x37, 0xbf, 0xc2, 0xa5, 0xa4, 0x8c, 0x83, 0x6a,\n\t0x5c, 0x50, 0x34, 0xbc, 0x05, 0x00, 0x0e, 0x90,\n\t0x00, 0xc7, 0xc2, 0xae, 0xaa, 0x95, 0x82, 0x7b,\n\t0x60, 0x61, 0x3f, 0xb7, 0xc6, 0xa5, 0xb1, 0x8c,\n\t0x8d, 0x72, 0x6b, 0x61, 0x51, 0xbf, 0xc4, 0xa5,\n\t0xa5, 0x8c, 0x82, 0x72, 0x61, 0x59, 0x39, 0x6c,\n\t0x26, 0x03, 0x95, 0x82, 0x7b, 0x61, 0x61, 0x40,\n\t0xfc, 0x05, 0x00, 0x00, 0x7e, 0xd7, 0xc3, 0xb7,\n\t0xa8, 0x9d, 0x80, 0x83, 0x5d, 0x6a, 0x3f, 0xbf,\n\t0xc7, 0xa5, 0xa8, 0x8c, 0x84, 0x72, 0x60, 0x61,\n\t0x46, 0xbf, 0xc2, 0xae, 0xb0, 0x9d, 0x92, 0x83,\n\t0x6f, 0x6a, 0x50, 0xd7, 0xc3, 0xb7, 0xa7, 0x9d,\n\t0x80, 0x83, 0x5e, 0x6a, 0x40, 0xfe, 0x02, 0xf8,\n\t0x8d, 0x96, 0x90, 0x90, 0xfe, 0x05, 0x00, 0x8a,\n\t0xc4, 0x63, 0xb8, 0x3c, 0xa6, 0x29, 0x97, 0x16,\n\t0x81, 0x84, 0xb7, 0x5b, 0xa9, 0x33, 0x94, 0x1e,\n\t0x83, 0x11, 0x70, 0xb8, 0xc2, 0x70, 0xb1, 0x4d,\n\t0xa3, 0x2a, 0x8d, 0x1b, 0x7b, 0xa8, 0xbc, 0x68,\n\t0xab, 0x47, 0x9d, 0x27, 0x87, 0x18, 0x75, 0xae,\n\t0xc6, 0x7d, 0xbb, 0x4d, 0xaa, 0x1c, 0x84, 0x11,\n\t0x72, 0xa3, 0xbb, 0x6e, 0xad, 0x3c, 0x97, 0x24,\n\t0x85, 0x16, 0x71, 0x80, 0xb2, 0x57, 0xa4, 0x30,\n\t0x8e, 0x1c, 0x7c, 0x10, 0x68, 0xbb, 0xbd, 0x75,\n\t0xac, 0x4f, 0x9e, 0x2b, 0x87, 0x1a, 0x76, 0x96,\n\t0xc5, 0x5e, 0xb5, 0x3e, 0xa5, 0x1f, 0x8c, 0x12,\n\t0x7a, 0xc1, 0xc6, 0x42, 0x9f, 0x27, 0x8c, 0x16,\n\t0x77, 0x0f, 0x67, 0x9d, 0xbc, 0x68, 0xad, 0x36,\n\t0x95, 0x20, 0x83, 0x11, 0x6d, 0x9b, 0xb8, 0x67,\n\t0xa8, 0x34, 0x90, 0x1f, 0x7c, 0x10, 0x67, 0x9e,\n\t0xc9, 0x6a, 0xbb, 0x37, 0xa4, 0x20, 0x90, 0x11,\n\t0x7b, 0xc6, 0xc8, 0x47, 0xa4, 0x2a, 0x90, 0x18,\n\t0x7b, 0x10, 0x6c, 0xae, 0xc4, 0x5d, 0xad, 0x37,\n\t0x9a, 0x1f, 0x85, 0x13, 0x75, 0x70, 0xad, 0x42,\n\t0x99, 0x25, 0x84, 0x17, 0x74, 0x0b, 0x56, 0x87,\n\t0xc8, 0x57, 0xb8, 0x2b, 0x9e, 0x19, 0x8a, 0x0d,\n\t0x74, 0xa7, 0xc8, 0x6e, 0xb9, 0x36, 0xa0, 0x1f,\n\t0x8b, 0x11, 0x75, 0x94, 0xbe, 0x4b, 0xa5, 0x2a,\n\t0x92, 0x18, 0x7c, 0x0f, 0x6b, 0xaf, 0xc0, 0x58,\n\t0xa8, 0x34, 0x94, 0x1d, 0x7d, 0x12, 0x6d, 0x82,\n\t0xc0, 0x52, 0xb0, 0x25, 0x94, 0x14, 0x7f, 0x0c,\n\t0x68, 0x84, 0xbf, 0x3e, 0xa4, 0x22, 0x8e, 0x10,\n\t0x76, 0x0b, 0x65, 0x88, 0xb6, 0x42, 0x9b, 0x26,\n\t0x87, 0x14, 0x70, 0x0c, 0x5f, 0xc5, 0xc2, 0x3e,\n\t0x97, 0x23, 0x83, 0x13, 0x6c, 0x0c, 0x5c, 0xb1,\n\t0xc9, 0x76, 0xbc, 0x4a, 0xaa, 0x20, 0x8d, 0x12,\n\t0x78, 0x93, 0xbf, 0x46, 0xa3, 0x26, 0x8d, 0x14,\n\t0x74, 0x0c, 0x62, 0xc8, 0xc4, 0x3b, 0x97, 0x21,\n\t0x82, 0x11, 0x6a, 0x0a, 0x59, 0xa3, 0xb9, 0x68,\n\t0xa9, 0x30, 0x8d, 0x1a, 0x78, 0x0f, 0x61, 0xa0,\n\t0xc9, 0x73, 0xbe, 0x50, 0xb1, 0x30, 0x9f, 0x14,\n\t0x80, 0x83, 0xb7, 0x3c, 0x9a, 0x20, 0x84, 0x0e,\n\t0x6a, 0x0a, 0x57, 0xac, 0xc2, 0x68, 0xb0, 0x2e,\n\t0x92, 0x19, 0x7c, 0x0d, 0x63, 0x93, 0xbe, 0x62,\n\t0xb0, 0x3c, 0x9e, 0x1a, 0x80, 0x0e, 0x6b, 0xbb,\n\t0x02, 0xa0, 0x02, 0xa0, 0x02, 0x6f, 0x00, 0x75,\n\t0x00, 0x75, 0x00, 0x00, 0x00, 0xad, 0x02, 0xb3,\n\t0x02, 0x6f, 0x00, 0x87, 0x00, 0x85, 0xfe, 0x03,\n\t0x00, 0xc2, 0x02, 0x82, 0x4d, 0x92, 0x6e, 0x4d,\n\t0xb1, 0xa8, 0x84, 0x01, 0x00, 0x07, 0x7e, 0x00,\n\t0xa8, 0x02, 0xa4, 0x02, 0xa4, 0x02, 0xa2, 0x00,\n\t0xa6, 0x00, 0xa6, 0x00, 0x00, 0x00, 0xb4, 0x02,\n\t0xb4, 0x02, 0x92, 0x00, 0x96, 0x00, 0x96, 0x46,\n\t0x04, 0xb0, 0x02, 0x64, 0x02, 0x0a, 0x8c, 0x00,\n\t0x90, 0x02, 0x98, 0x02, 0x98, 0x02, 0x0e, 0x01,\n\t0x11, 0x01, 0x11, 0x50, 0xc3, 0x08, 0x88, 0x02,\n\t0x88, 0x02, 0x19, 0x01, 0x02, 0x01, 0x02, 0x01,\n\t0xf3, 0x2d, 0x00, 0x00\n};\n\n/* Array of known hw_options bits with human-friendly parsing */\nstatic struct hc_hwopt {\n\tconst u32 bit;\n\tconst char *str;\n} const hc_hwopts[] = {\n\t{\n\t\t.bit = RB_HW_OPT_NO_UART,\n\t\t.str = \"no UART\\t\\t\",\n\t}, {\n\t\t.bit = RB_HW_OPT_HAS_VOLTAGE,\n\t\t.str = \"has Vreg\\t\",\n\t}, {\n\t\t.bit = RB_HW_OPT_HAS_USB,\n\t\t.str = \"has usb\\t\\t\",\n\t}, {\n\t\t.bit = RB_HW_OPT_HAS_ATTINY,\n\t\t.str = \"has ATtiny\\t\",\n\t}, {\n\t\t.bit = RB_HW_OPT_NO_NAND,\n\t\t.str = \"no NAND\\t\\t\",\n\t}, {\n\t\t.bit = RB_HW_OPT_HAS_LCD,\n\t\t.str = \"has LCD\\t\\t\",\n\t}, {\n\t\t.bit = RB_HW_OPT_HAS_POE_OUT,\n\t\t.str = \"has POE out\\t\",\n\t}, {\n\t\t.bit = RB_HW_OPT_HAS_uSD,\n\t\t.str = \"has MicroSD\\t\",\n\t}, {\n\t\t.bit = RB_HW_OPT_HAS_SIM,\n\t\t.str = \"has SIM\\t\\t\",\n\t}, {\n\t\t.bit = RB_HW_OPT_HAS_SFP,\n\t\t.str = \"has SFP\\t\\t\",\n\t}, {\n\t\t.bit = RB_HW_OPT_HAS_WIFI,\n\t\t.str = \"has WiFi\\t\",\n\t}, {\n\t\t.bit = RB_HW_OPT_HAS_TS_FOR_ADC,\n\t\t.str = \"has TS ADC\\t\",\n\t}, {\n\t\t.bit = RB_HW_OPT_HAS_PLC,\n\t\t.str = \"has PLC\\t\\t\",\n\t},\n};\n\n/*\n * The MAC is stored network-endian on all devices, in 2 32-bit segments:\n * <XX:XX:XX:XX> <XX:XX:00:00>. Kernel print has us covered.\n */\nstatic ssize_t hc_tag_show_mac(const u8 *pld, u16 pld_len, char *buf)\n{\n\tif (8 != pld_len)\n\t\treturn -EINVAL;\n\n\treturn sprintf(buf, \"%pM\\n\", pld);\n}\n\n/*\n * Print HW options in a human readable way:\n * The raw number and in decoded form\n */\nstatic ssize_t hc_tag_show_hwoptions(const u8 *pld, u16 pld_len, char *buf)\n{\n\tchar *out = buf;\n\tu32 data;\t// cpu-endian\n\tint i;\n\n\tif (sizeof(data) != pld_len)\n\t\treturn -EINVAL;\n\n\tdata = *(u32 *)pld;\n\tout += sprintf(out, \"raw\\t\\t: 0x%08x\\n\\n\", data);\n\n\tfor (i = 0; i < ARRAY_SIZE(hc_hwopts); i++)\n\t\tout += sprintf(out, \"%s: %s\\n\", hc_hwopts[i].str,\n\t\t\t       (data & hc_hwopts[i].bit) ? \"true\" : \"false\");\n\n\treturn out - buf;\n}\n\nstatic ssize_t hc_wlan_data_bin_read(struct file *filp, struct kobject *kobj,\n\t\t\t\t     struct bin_attribute *attr, char *buf,\n\t\t\t\t     loff_t off, size_t count);\n\nstatic struct hc_wlan_attr {\n\tconst u16 erd_tag_id;\n\tstruct bin_attribute battr;\n\tu16 pld_ofs;\n\tu16 pld_len;\n} hc_wd_multi_battrs[] = {\n\t{\n\t\t.erd_tag_id = RB_WLAN_ERD_ID_MULTI_8001,\n\t\t.battr = __BIN_ATTR(data_0, S_IRUSR, hc_wlan_data_bin_read, NULL, 0),\n\t}, {\n\t\t.erd_tag_id = RB_WLAN_ERD_ID_MULTI_8201,\n\t\t.battr = __BIN_ATTR(data_2, S_IRUSR, hc_wlan_data_bin_read, NULL, 0),\n\t}\n};\n\nstatic struct hc_wlan_attr hc_wd_solo_battr = {\n\t.erd_tag_id = RB_WLAN_ERD_ID_SOLO,\n\t.battr = __BIN_ATTR(wlan_data, S_IRUSR, hc_wlan_data_bin_read, NULL, 0),\n};\n\nstatic ssize_t hc_attr_show(struct kobject *kobj, struct kobj_attribute *attr,\n\t\t\t    char *buf);\n\n/* Array of known tags to publish in sysfs */\nstatic struct hc_attr {\n\tconst u16 tag_id;\n\tssize_t (* const tshow)(const u8 *pld, u16 pld_len, char *buf);\n\tstruct kobj_attribute kattr;\n\tu16 pld_ofs;\n\tu16 pld_len;\n} hc_attrs[] = {\n\t{\n\t\t.tag_id = RB_ID_FLASH_INFO,\n\t\t.tshow = routerboot_tag_show_u32s,\n\t\t.kattr = __ATTR(flash_info, S_IRUSR, hc_attr_show, NULL),\n\t}, {\n\t\t.tag_id = RB_ID_MAC_ADDRESS_PACK,\n\t\t.tshow = hc_tag_show_mac,\n\t\t.kattr = __ATTR(mac_base, S_IRUSR, hc_attr_show, NULL),\n\t}, {\n\t\t.tag_id = RB_ID_BOARD_PRODUCT_CODE,\n\t\t.tshow = routerboot_tag_show_string,\n\t\t.kattr = __ATTR(board_product_code, S_IRUSR, hc_attr_show, NULL),\n\t}, {\n\t\t.tag_id = RB_ID_BIOS_VERSION,\n\t\t.tshow = routerboot_tag_show_string,\n\t\t.kattr = __ATTR(booter_version, S_IRUSR, hc_attr_show, NULL),\n\t}, {\n\t\t.tag_id = RB_ID_SERIAL_NUMBER,\n\t\t.tshow = routerboot_tag_show_string,\n\t\t.kattr = __ATTR(board_serial, S_IRUSR, hc_attr_show, NULL),\n\t}, {\n\t\t.tag_id = RB_ID_MEMORY_SIZE,\n\t\t.tshow = routerboot_tag_show_u32s,\n\t\t.kattr = __ATTR(mem_size, S_IRUSR, hc_attr_show, NULL),\n\t}, {\n\t\t.tag_id = RB_ID_MAC_ADDRESS_COUNT,\n\t\t.tshow = routerboot_tag_show_u32s,\n\t\t.kattr = __ATTR(mac_count, S_IRUSR, hc_attr_show, NULL),\n\t}, {\n\t\t.tag_id = RB_ID_HW_OPTIONS,\n\t\t.tshow = hc_tag_show_hwoptions,\n\t\t.kattr = __ATTR(hw_options, S_IRUSR, hc_attr_show, NULL),\n\t}, {\n\t\t.tag_id = RB_ID_WLAN_DATA,\n\t\t.tshow = NULL,\n\t}, {\n\t\t.tag_id = RB_ID_BOARD_IDENTIFIER,\n\t\t.tshow = routerboot_tag_show_string,\n\t\t.kattr = __ATTR(board_identifier, S_IRUSR, hc_attr_show, NULL),\n\t}, {\n\t\t.tag_id = RB_ID_PRODUCT_NAME,\n\t\t.tshow = routerboot_tag_show_string,\n\t\t.kattr = __ATTR(product_name, S_IRUSR, hc_attr_show, NULL),\n\t}, {\n\t\t.tag_id = RB_ID_DEFCONF,\n\t\t.tshow = routerboot_tag_show_string,\n\t\t.kattr = __ATTR(defconf, S_IRUSR, hc_attr_show, NULL),\n\t}, {\n\t\t.tag_id = RB_ID_BOARD_REVISION,\n\t\t.tshow = routerboot_tag_show_string,\n\t\t.kattr = __ATTR(board_revision, S_IRUSR, hc_attr_show, NULL),\n\t}\n};\n\n/*\n * If the RB_ID_WLAN_DATA payload starts with RB_MAGIC_ERD, then past\n * that magic number the payload itself contains a routerboot tag node\n * locating the LZO-compressed calibration data. So far this scheme is only\n * known to use a single tag at id 0x1.\n */\nstatic int hc_wlan_data_unpack_erd(const u16 tag_id, const u8 *inbuf, size_t inlen,\n\t\t\t\t   void *outbuf, size_t *outlen)\n{\n\tu16 lzo_ofs, lzo_len;\n\tint ret;\n\n\t/* Find embedded tag */\n\tret = routerboot_tag_find(inbuf, inlen, tag_id, &lzo_ofs, &lzo_len);\n\tif (ret) {\n\t\tpr_debug(RB_HC_PR_PFX \"no ERD data for id 0x%04x\\n\", tag_id);\n\t\tgoto fail;\n\t}\n\n\tif (lzo_len > inlen) {\n\t\tpr_debug(RB_HC_PR_PFX \"Invalid ERD data length\\n\");\n\t\tret = -EINVAL;\n\t\tgoto fail;\n\t}\n\n\tret = lzo1x_decompress_safe(inbuf+lzo_ofs, lzo_len, outbuf, outlen);\n\tif (ret)\n\t\tpr_debug(RB_HC_PR_PFX \"LZO decompression error (%d)\\n\", ret);\n\nfail:\n\treturn ret;\n}\n\n/*\n * If the RB_ID_WLAN_DATA payload starts with RB_MAGIC_LZOR, then past\n * that magic number is a payload that must be appended to the hc_lzor_prefix,\n * the resulting blob is LZO-compressed. In the LZO decompression result,\n * the RB_MAGIC_ERD magic number (aligned) must be located. Following that\n * magic, there is one or more routerboot tag node(s) locating the RLE-encoded\n * calibration data payload.\n */\nstatic int hc_wlan_data_unpack_lzor(const u16 tag_id, const u8 *inbuf, size_t inlen,\n\t\t\t\t    void *outbuf, size_t *outlen)\n{\n\tu16 rle_ofs, rle_len;\n\tconst u32 *needle;\n\tu8 *tempbuf;\n\tsize_t templen, lzo_len;\n\tint ret;\n\n\tlzo_len = inlen + sizeof(hc_lzor_prefix);\n\tif (lzo_len > *outlen)\n\t\treturn -EFBIG;\n\n\t/* Temporary buffer same size as the outbuf */\n\ttemplen = *outlen;\n\ttempbuf = kmalloc(templen, GFP_KERNEL);\n\tif (!tempbuf)\n\t\treturn -ENOMEM;\n\n\t/* Concatenate into the outbuf */\n\tmemcpy(outbuf, hc_lzor_prefix, sizeof(hc_lzor_prefix));\n\tmemcpy(outbuf + sizeof(hc_lzor_prefix), inbuf, inlen);\n\n\t/* LZO-decompress lzo_len bytes of outbuf into the tempbuf */\n\tret = lzo1x_decompress_safe(outbuf, lzo_len, tempbuf, &templen);\n\tif (ret) {\n\t\tif (LZO_E_INPUT_NOT_CONSUMED == ret) {\n\t\t\t/*\n\t\t\t * The tag length is always aligned thus the LZO payload may be padded,\n\t\t\t * which can trigger a spurious error which we ignore here.\n\t\t\t */\n\t\t\tpr_debug(RB_HC_PR_PFX \"LZOR: LZO EOF before buffer end - this may be harmless\\n\");\n\t\t} else {\n\t\t\tpr_debug(RB_HC_PR_PFX \"LZOR: LZO decompression error (%d)\\n\", ret);\n\t\t\tgoto fail;\n\t\t}\n\t}\n\n\t/*\n\t * Post decompression we have a blob (possibly byproduct of the lzo\n\t * dictionary). We need to find RB_MAGIC_ERD. The magic number seems to\n\t * be 32bit-aligned in the decompression output.\n\t */\n\tneedle = (const u32 *)tempbuf;\n\twhile (RB_MAGIC_ERD != *needle++) {\n\t\tif ((u8 *)needle >= tempbuf+templen) {\n\t\t\tpr_debug(RB_HC_PR_PFX \"LZOR: ERD magic not found\\n\");\n\t\t\tret = -ENODATA;\n\t\t\tgoto fail;\n\t\t}\n\t};\n\ttemplen -= (u8 *)needle - tempbuf;\n\n\t/* Past magic. Look for tag node */\n\tret = routerboot_tag_find((u8 *)needle, templen, tag_id, &rle_ofs, &rle_len);\n\tif (ret) {\n\t\tpr_debug(RB_HC_PR_PFX \"LZOR: no RLE data for id 0x%04x\\n\", tag_id);\n\t\tgoto fail;\n\t}\n\n\tif (rle_len > templen) {\n\t\tpr_debug(RB_HC_PR_PFX \"LZOR: Invalid RLE data length\\n\");\n\t\tret = -EINVAL;\n\t\tgoto fail;\n\t}\n\n\t/* RLE-decode tempbuf from needle back into the outbuf */\n\tret = routerboot_rle_decode((u8 *)needle+rle_ofs, rle_len, outbuf, outlen);\n\tif (ret)\n\t\tpr_debug(RB_HC_PR_PFX \"LZOR: RLE decoding error (%d)\\n\", ret);\n\nfail:\n\tkfree(tempbuf);\n\treturn ret;\n}\n\nstatic int hc_wlan_data_unpack(const u16 tag_id, const size_t tofs, size_t tlen,\n\t\t\t       void *outbuf, size_t *outlen)\n{\n\tconst u8 *lbuf;\n\tu32 magic;\n\tint ret;\n\n\t/* Caller ensure tlen > 0. tofs is aligned */\n\tif ((tofs + tlen) > hc_buflen)\n\t\treturn -EIO;\n\n\tlbuf = hc_buf + tofs;\n\tmagic = *(u32 *)lbuf;\n\n\tret = -ENODATA;\n\tswitch (magic) {\n\tcase RB_MAGIC_LZOR:\n\t\t/* Skip magic */\n\t\tlbuf += sizeof(magic);\n\t\ttlen -= sizeof(magic);\n\t\tret = hc_wlan_data_unpack_lzor(tag_id, lbuf, tlen, outbuf, outlen);\n\t\tbreak;\n\tcase RB_MAGIC_ERD:\n\t\t/* Skip magic */\n\t\tlbuf += sizeof(magic);\n\t\ttlen -= sizeof(magic);\n\t\tret = hc_wlan_data_unpack_erd(tag_id, lbuf, tlen, outbuf, outlen);\n\t\tbreak;\n\tdefault:\n\t\t/*\n\t\t * If the RB_ID_WLAN_DATA payload doesn't start with a\n\t\t * magic number, the payload itself is the raw RLE-encoded\n\t\t * calibration data. Only RB_WLAN_ERD_ID_SOLO makes sense here.\n\t\t */\n\t\tif (RB_WLAN_ERD_ID_SOLO == tag_id) {\n\t\t\tret = routerboot_rle_decode(lbuf, tlen, outbuf, outlen);\n\t\t\tif (ret)\n\t\t\t\tpr_debug(RB_HC_PR_PFX \"RLE decoding error (%d)\\n\", ret);\n\t\t}\n\t\tbreak;\n\t}\n\n\treturn ret;\n}\n\nstatic ssize_t hc_attr_show(struct kobject *kobj, struct kobj_attribute *attr,\n\t\t\t    char *buf)\n{\n\tconst struct hc_attr *hc_attr;\n\tconst u8 *pld;\n\tu16 pld_len;\n\n\thc_attr = container_of(attr, typeof(*hc_attr), kattr);\n\n\tif (!hc_attr->pld_len)\n\t\treturn -ENOENT;\n\n\tpld = hc_buf + hc_attr->pld_ofs;\n\tpld_len = hc_attr->pld_len;\n\n\treturn hc_attr->tshow(pld, pld_len, buf);\n}\n\n/*\n * This function will allocate and free memory every time it is called. This\n * is not the fastest way to do this, but since the data is rarely read (mainly\n * at boot time to load wlan caldata), this makes it possible to save memory for\n * the system.\n */\nstatic ssize_t hc_wlan_data_bin_read(struct file *filp, struct kobject *kobj,\n\t\t\t\t     struct bin_attribute *attr, char *buf,\n\t\t\t\t     loff_t off, size_t count)\n{\n\tstruct hc_wlan_attr *hc_wattr;\n\tsize_t outlen;\n\tvoid *outbuf;\n\tint ret;\n\n\thc_wattr = container_of(attr, typeof(*hc_wattr), battr);\n\n\tif (!hc_wattr->pld_len)\n\t\treturn -ENOENT;\n\n\toutlen = RB_ART_SIZE;\n\n\t/* Don't bother unpacking if the source is already too large */\n\tif (hc_wattr->pld_len > outlen)\n\t\treturn -EFBIG;\n\n\toutbuf = kmalloc(outlen, GFP_KERNEL);\n\tif (!outbuf)\n\t\treturn -ENOMEM;\n\n\tret = hc_wlan_data_unpack(hc_wattr->erd_tag_id, hc_wattr->pld_ofs, hc_wattr->pld_len, outbuf, &outlen);\n\tif (ret) {\n\t\tkfree(outbuf);\n\t\treturn ret;\n\t}\n\n\tif (off >= outlen) {\n\t\tkfree(outbuf);\n\t\treturn 0;\n\t}\n\n\tif (off + count > outlen)\n\t\tcount = outlen - off;\n\n\tmemcpy(buf, outbuf + off, count);\n\n\tkfree(outbuf);\n\treturn count;\n}\n\nint rb_hardconfig_init(struct kobject *rb_kobj, struct mtd_info *mtd)\n{\n\tstruct kobject *hc_wlan_kobj;\n\tsize_t bytes_read, buflen, outlen;\n\tconst u8 *buf;\n\tvoid *outbuf;\n\tint i, j, ret;\n\tu32 magic;\n\n\thc_buf = NULL;\n\thc_kobj = NULL;\n\thc_wlan_kobj = NULL;\n\n\tret = __get_mtd_device(mtd);\n\tif (ret)\n\t\treturn -ENODEV;\n\n\thc_buflen = mtd->size;\n\thc_buf = kmalloc(hc_buflen, GFP_KERNEL);\n\tif (!hc_buf) {\n\t\t__put_mtd_device(mtd);\n\t\treturn -ENOMEM;\n\t}\n\n\tret = mtd_read(mtd, 0, hc_buflen, &bytes_read, hc_buf);\n\t__put_mtd_device(mtd);\n\n\tif (ret)\n\t\tgoto fail;\n\n\tif (bytes_read != hc_buflen) {\n\t\tret = -EIO;\n\t\tgoto fail;\n\t}\n\n\t/* Check we have what we expect */\n\tmagic = *(const u32 *)hc_buf;\n\tif (RB_MAGIC_HARD != magic) {\n\t\tret = -EINVAL;\n\t\tgoto fail;\n\t}\n\n\t/* Skip magic */\n\tbuf = hc_buf + sizeof(magic);\n\tbuflen = hc_buflen - sizeof(magic);\n\n\t/* Populate sysfs */\n\tret = -ENOMEM;\n\thc_kobj = kobject_create_and_add(RB_MTD_HARD_CONFIG, rb_kobj);\n\tif (!hc_kobj)\n\t\tgoto fail;\n\n\t/* Locate and publish all known tags */\n\tfor (i = 0; i < ARRAY_SIZE(hc_attrs); i++) {\n\t\tret = routerboot_tag_find(buf, buflen, hc_attrs[i].tag_id,\n\t\t\t\t\t  &hc_attrs[i].pld_ofs, &hc_attrs[i].pld_len);\n\t\tif (ret) {\n\t\t\thc_attrs[i].pld_ofs = hc_attrs[i].pld_len = 0;\n\t\t\tcontinue;\n\t\t}\n\n\t\t/* Account for skipped magic */\n\t\thc_attrs[i].pld_ofs += sizeof(magic);\n\n\t\t/*\n\t\t * Special case RB_ID_WLAN_DATA to prep and create the binary attribute.\n\t\t * We first check if the data is \"old style\" within a single tag (or no tag at all):\n\t\t * If it is we publish this single blob as a binary attribute child of hc_kobj to\n\t\t * preserve backward compatibility.\n\t\t * If it isn't and instead uses multiple ERD tags, we create a subfolder and\n\t\t * publish the known ones there.\n\t\t */\n\t\tif ((RB_ID_WLAN_DATA == hc_attrs[i].tag_id) && hc_attrs[i].pld_len) {\n\t\t\toutlen = RB_ART_SIZE;\n\t\t\toutbuf = kmalloc(outlen, GFP_KERNEL);\n\t\t\tif (!outbuf) {\n\t\t\t\tpr_warn(RB_HC_PR_PFX \"Out of memory parsing WLAN tag\\n\");\n\t\t\t\tcontinue;\n\t\t\t}\n\n\t\t\t/* Test ID_SOLO first, if found: done */\n\t\t\tret = hc_wlan_data_unpack(RB_WLAN_ERD_ID_SOLO, hc_attrs[i].pld_ofs, hc_attrs[i].pld_len, outbuf, &outlen);\n\t\t\tif (!ret) {\n\t\t\t\thc_wd_solo_battr.pld_ofs = hc_attrs[i].pld_ofs;\n\t\t\t\thc_wd_solo_battr.pld_len = hc_attrs[i].pld_len;\n\n\t\t\t\tret = sysfs_create_bin_file(hc_kobj, &hc_wd_solo_battr.battr);\n\t\t\t\tif (ret)\n\t\t\t\t\tpr_warn(RB_HC_PR_PFX \"Could not create %s sysfs entry (%d)\\n\",\n\t\t\t\t\t\thc_wd_solo_battr.battr.attr.name, ret);\n\t\t\t}\n\t\t\t/* Otherwise, create \"wlan_data\" subtree and publish known data */\n\t\t\telse {\n\t\t\t\thc_wlan_kobj = kobject_create_and_add(\"wlan_data\", hc_kobj);\n\t\t\t\tif (!hc_wlan_kobj) {\n\t\t\t\t\tkfree(outbuf);\n\t\t\t\t\tpr_warn(RB_HC_PR_PFX \"Could not create wlan_data sysfs folder\\n\");\n\t\t\t\t\tcontinue;\n\t\t\t\t}\n\n\t\t\t\tfor (j = 0; j < ARRAY_SIZE(hc_wd_multi_battrs); j++) {\n\t\t\t\t\toutlen = RB_ART_SIZE;\n\t\t\t\t\tret = hc_wlan_data_unpack(hc_wd_multi_battrs[j].erd_tag_id,\n\t\t\t\t\t\t\t\t  hc_attrs[i].pld_ofs, hc_attrs[i].pld_len, outbuf, &outlen);\n\t\t\t\t\tif (ret) {\n\t\t\t\t\t\thc_wd_multi_battrs[j].pld_ofs = hc_wd_multi_battrs[j].pld_len = 0;\n\t\t\t\t\t\tcontinue;\n\t\t\t\t\t}\n\n\t\t\t\t\thc_wd_multi_battrs[j].pld_ofs = hc_attrs[i].pld_ofs;\n\t\t\t\t\thc_wd_multi_battrs[j].pld_len = hc_attrs[i].pld_len;\n\n\t\t\t\t\tret = sysfs_create_bin_file(hc_wlan_kobj, &hc_wd_multi_battrs[j].battr);\n\t\t\t\t\tif (ret)\n\t\t\t\t\t\tpr_warn(RB_HC_PR_PFX \"Could not create wlan_data/%s sysfs entry (%d)\\n\",\n\t\t\t\t\t\t\thc_wd_multi_battrs[j].battr.attr.name, ret);\n\t\t\t\t}\n\t\t\t}\n\n\t\t\tkfree(outbuf);\n\t\t}\n\t\t/* All other tags are published via standard attributes */\n\t\telse {\n\t\t\tret = sysfs_create_file(hc_kobj, &hc_attrs[i].kattr.attr);\n\t\t\tif (ret)\n\t\t\t\tpr_warn(RB_HC_PR_PFX \"Could not create %s sysfs entry (%d)\\n\",\n\t\t\t\t       hc_attrs[i].kattr.attr.name, ret);\n\t\t}\n\t}\n\n\tpr_info(\"MikroTik RouterBOARD hardware configuration sysfs driver v\" RB_HARDCONFIG_VER \"\\n\");\n\n\treturn 0;\n\nfail:\n\tkfree(hc_buf);\n\thc_buf = NULL;\n\treturn ret;\n}\n\nvoid rb_hardconfig_exit(void)\n{\n\tkobject_put(hc_kobj);\n\thc_kobj = NULL;\n\tkfree(hc_buf);\n\thc_buf = NULL;\n}\n"
  },
  {
    "path": "target/linux/generic/files/drivers/platform/mikrotik/rb_softconfig.c",
    "content": "// SPDX-License-Identifier: GPL-2.0-only\n/*\n * Driver for MikroTik RouterBoot soft config.\n *\n * Copyright (C) 2020 Thibaut VARÈNE <hacks+kernel@slashdirt.org>\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of the GNU General Public License version 2 as published\n * by the Free Software Foundation.\n *\n * This driver exposes the data encoded in the \"soft_config\" flash segment of\n * MikroTik RouterBOARDs devices. It presents the data in a sysfs folder\n * named \"soft_config\". The data is presented in a user/machine-friendly way\n * with just as much parsing as can be generalized across mikrotik platforms\n * (as inferred from reverse-engineering).\n *\n * The known soft_config tags are presented in the \"soft_config\" sysfs folder,\n * with the addition of one specific file named \"commit\", which is only\n * available if the driver supports writes to the mtd device: no modifications\n * made to any of the other attributes are actually written back to flash media\n * until a true value is input into this file (e.g. [Yy1]). This is to avoid\n * unnecessary flash wear, and to permit to revert all changes by issuing a\n * false value ([Nn0]). Reading the content of this file shows the current\n * status of the driver: if the data in sysfs matches the content of the\n * soft_config partition, the file will read \"clean\". Otherwise, it will read\n * \"dirty\".\n *\n * The writeable sysfs files presented by this driver will accept only inputs\n * which are in a valid range for the given tag. As a design choice, the driver\n * will not assess whether the inputs are identical to the existing data.\n *\n * Note: PAGE_SIZE is assumed to be >= 4K, hence the device attribute show\n * routines need not check for output overflow.\n *\n * Some constant defines extracted from rbcfg.h by Gabor Juhos\n * <juhosg@openwrt.org>\n */\n\n#include <linux/types.h>\n#include <linux/init.h>\n#include <linux/kernel.h>\n#include <linux/slab.h>\n#include <linux/errno.h>\n#include <linux/kobject.h>\n#include <linux/string.h>\n#include <linux/mtd/mtd.h>\n#include <linux/sysfs.h>\n#include <linux/version.h>\n#include <linux/capability.h>\n#include <linux/spinlock.h>\n#include <linux/crc32.h>\n\n#ifdef CONFIG_ATH79\n #include <asm/mach-ath79/ath79.h>\n#endif\n\n#include \"routerboot.h\"\n\n#define RB_SOFTCONFIG_VER\t\t\"0.05\"\n#define RB_SC_PR_PFX\t\t\t\"[rb_softconfig] \"\n\n#define RB_SC_HAS_WRITE_SUPPORT\ttrue\n#define RB_SC_WMODE\t\t\tS_IWUSR\n#define RB_SC_RMODE\t\t\tS_IRUSR\n\n/* ID values for software settings */\n#define RB_SCID_UART_SPEED\t\t0x01\t// u32*1\n#define RB_SCID_BOOT_DELAY\t\t0x02\t// u32*1\n#define RB_SCID_BOOT_DEVICE\t\t0x03\t// u32*1\n#define RB_SCID_BOOT_KEY\t\t0x04\t// u32*1\n#define RB_SCID_CPU_MODE\t\t0x05\t// u32*1\n#define RB_SCID_BIOS_VERSION\t\t0x06\t// str\n#define RB_SCID_BOOT_PROTOCOL\t\t0x09\t// u32*1\n#define RB_SCID_CPU_FREQ_IDX\t\t0x0C\t// u32*1\n#define RB_SCID_BOOTER\t\t\t0x0D\t// u32*1\n#define RB_SCID_SILENT_BOOT\t\t0x0F\t// u32*1\n/*\n * protected_routerboot seems to use tag 0x1F. It only works in combination with\n * RouterOS, resulting in a wiped board otherwise, so it's not implemented here.\n * The tag values are as follows:\n * - off: 0x0\n * - on: the lower halfword encodes the max value in s for the reset feature,\n *\t the higher halfword encodes the min value in s for the reset feature.\n * Default value when on: 0x00140258: 0x14 = 20s / 0x258= 600s\n * See details here: https://wiki.mikrotik.com/wiki/Manual:RouterBOARD_settings#Protected_bootloader\n */\n\n/* Tag values */\n\n#define RB_UART_SPEED_115200\t\t0\n#define RB_UART_SPEED_57600\t\t1\n#define RB_UART_SPEED_38400\t\t2\n#define RB_UART_SPEED_19200\t\t3\n#define RB_UART_SPEED_9600\t\t4\n#define RB_UART_SPEED_4800\t\t5\n#define RB_UART_SPEED_2400\t\t6\n#define RB_UART_SPEED_1200\t\t7\n#define RB_UART_SPEED_OFF\t\t8\n\n/* valid boot delay: 1 - 9s in 1s increment */\n#define RB_BOOT_DELAY_MIN\t\t1\n#define RB_BOOT_DELAY_MAX\t\t9\n\n#define RB_BOOT_DEVICE_ETHER\t\t0\t// \"boot over Ethernet\"\n#define RB_BOOT_DEVICE_NANDETH\t\t1\t// \"boot from NAND, if fail then Ethernet\"\n#define RB_BOOT_DEVICE_CFCARD\t\t2\t// (not available in rbcfg)\n#define RB_BOOT_DEVICE_ETHONCE\t\t3\t// \"boot Ethernet once, then NAND\"\n#define RB_BOOT_DEVICE_NANDONLY\t\t5\t// \"boot from NAND only\"\n#define RB_BOOT_DEVICE_FLASHCFG\t\t7\t// \"boot in flash configuration mode\"\n#define RB_BOOT_DEVICE_FLSHONCE\t\t8\t// \"boot in flash configuration mode once, then NAND\"\n\n/*\n * ATH79 9xxx CPU frequency indices.\n * It is unknown if they apply to all ATH79 RBs, and some do not seem to feature\n * the upper levels (QCA955x), while F is presumably AR9344-only.\n */\n#define RB_CPU_FREQ_IDX_ATH79_9X_A\t(0 << 3)\n#define RB_CPU_FREQ_IDX_ATH79_9X_B\t(1 << 3)\t// 0x8\n#define RB_CPU_FREQ_IDX_ATH79_9X_C\t(2 << 3)\t// 0x10 - factory freq for many devices\n#define RB_CPU_FREQ_IDX_ATH79_9X_D\t(3 << 3)\t// 0x18\n#define RB_CPU_FREQ_IDX_ATH79_9X_E\t(4 << 3)\t// 0x20\n#define RB_CPU_FREQ_IDX_ATH79_9X_F\t(5 << 3)\t// 0x28\n\n#define RB_CPU_FREQ_IDX_ATH79_9X_MIN\t\t0\t// all devices support lowest setting\n#define RB_CPU_FREQ_IDX_ATH79_9X_AR9334_MAX\t5\t// stops at F\n#define RB_CPU_FREQ_IDX_ATH79_9X_QCA953X_MAX\t4\t// stops at E\n#define RB_CPU_FREQ_IDX_ATH79_9X_QCA9556_MAX\t2\t// stops at C\n#define RB_CPU_FREQ_IDX_ATH79_9X_QCA9558_MAX\t3\t// stops at D\n\n/* ATH79 7xxx CPU frequency indices. */\n#define RB_CPU_FREQ_IDX_ATH79_7X_A\t((0 * 9) << 4)\n#define RB_CPU_FREQ_IDX_ATH79_7X_B\t((1 * 9) << 4)\n#define RB_CPU_FREQ_IDX_ATH79_7X_C\t((2 * 9) << 4)\n#define RB_CPU_FREQ_IDX_ATH79_7X_D\t((3 * 9) << 4)\n#define RB_CPU_FREQ_IDX_ATH79_7X_E\t((4 * 9) << 4)\n#define RB_CPU_FREQ_IDX_ATH79_7X_F\t((5 * 9) << 4)\n#define RB_CPU_FREQ_IDX_ATH79_7X_G\t((6 * 9) << 4)\n#define RB_CPU_FREQ_IDX_ATH79_7X_H\t((7 * 9) << 4)\n\n#define RB_CPU_FREQ_IDX_ATH79_7X_MIN\t\t0\t// all devices support lowest setting\n#define RB_CPU_FREQ_IDX_ATH79_7X_AR724X_MAX\t3\t// stops at D\n#define RB_CPU_FREQ_IDX_ATH79_7X_AR7161_MAX\t7\t// stops at H - check if applies to all AR71xx devices\n\n#define RB_SC_CRC32_OFFSET\t\t4\t// located right after magic\n\nstatic struct kobject *sc_kobj;\nstatic u8 *sc_buf;\nstatic size_t sc_buflen;\nstatic rwlock_t sc_bufrwl;\t\t// rw lock to sc_buf\n\n/* MUST be used with lock held */\n#define RB_SC_CLRCRC()\t\t*(u32 *)(sc_buf + RB_SC_CRC32_OFFSET) = 0\n#define RB_SC_GETCRC()\t\t*(u32 *)(sc_buf + RB_SC_CRC32_OFFSET)\n#define RB_SC_SETCRC(_crc)\t*(u32 *)(sc_buf + RB_SC_CRC32_OFFSET) = (_crc)\n\nstruct sc_u32tvs {\n\tconst u32 val;\n\tconst char *str;\n};\n\n#define RB_SC_TVS(_val, _str) {\t\t\\\n\t.val = (_val),\t\t\t\\\n\t.str = (_str),\t\t\t\\\n}\n\nstatic ssize_t sc_tag_show_u32tvs(const u8 *pld, u16 pld_len, char *buf,\n\t\t\t\t  const struct sc_u32tvs tvs[], const int tvselmts)\n{\n\tconst char *fmt;\n\tchar *out = buf;\n\tu32 data;\t// cpu-endian\n\tint i;\n\n\t// fallback to raw hex output if we can't handle the input\n\tif (tvselmts < 0)\n\t\treturn routerboot_tag_show_u32s(pld, pld_len, buf);\n\n\tif (sizeof(data) != pld_len)\n\t\treturn -EINVAL;\n\n\tread_lock(&sc_bufrwl);\n\tdata = *(u32 *)pld;\t\t// pld aliases sc_buf\n\tread_unlock(&sc_bufrwl);\n\n\tfor (i = 0; i < tvselmts; i++) {\n\t\tfmt = (tvs[i].val == data) ? \"[%s] \" : \"%s \";\n\t\tout += sprintf(out, fmt, tvs[i].str);\n\t}\n\n\tout += sprintf(out, \"\\n\");\n\treturn out - buf;\n}\n\nstatic ssize_t sc_tag_store_u32tvs(const u8 *pld, u16 pld_len, const char *buf, size_t count,\n\t\t\t\t   const struct sc_u32tvs tvs[], const int tvselmts)\n{\n\tint i;\n\n\tif (tvselmts < 0)\n\t\treturn tvselmts;\n\n\tif (sizeof(u32) != pld_len)\n\t\treturn -EINVAL;\n\n\tfor (i = 0; i < tvselmts; i++) {\n\t\tif (sysfs_streq(buf, tvs[i].str)) {\n\t\t\twrite_lock(&sc_bufrwl);\n\t\t\t*(u32 *)pld = tvs[i].val;\t// pld aliases sc_buf\n\t\t\tRB_SC_CLRCRC();\n\t\t\twrite_unlock(&sc_bufrwl);\n\t\t\treturn count;\n\t\t}\n\t}\n\n\treturn -EINVAL;\n}\n\nstruct sc_boolts {\n\tconst char *strfalse;\n\tconst char *strtrue;\n};\n\nstatic ssize_t sc_tag_show_boolts(const u8 *pld, u16 pld_len, char *buf,\n\t\t\t\t  const struct sc_boolts *bts)\n{\n\tconst char *fmt;\n\tchar *out = buf;\n\tu32 data;\t// cpu-endian\n\n\tif (sizeof(data) != pld_len)\n\t\treturn -EINVAL;\n\n\tread_lock(&sc_bufrwl);\n\tdata = *(u32 *)pld;\t\t// pld aliases sc_buf\n\tread_unlock(&sc_bufrwl);\n\n\tfmt = (data) ? \"%s [%s]\\n\" : \"[%s] %s\\n\";\n\tout += sprintf(out, fmt, bts->strfalse, bts->strtrue);\n\n\treturn out - buf;\n}\n\nstatic ssize_t sc_tag_store_boolts(const u8 *pld, u16 pld_len, const char *buf, size_t count,\n\t\t\t\t   const struct sc_boolts *bts)\n{\n\tu32 data;\t// cpu-endian\n\n\tif (sizeof(data) != pld_len)\n\t\treturn -EINVAL;\n\n\tif (sysfs_streq(buf, bts->strfalse))\n\t\tdata = 0;\n\telse if (sysfs_streq(buf, bts->strtrue))\n\t\tdata = 1;\n\telse\n\t\treturn -EINVAL;\n\n\twrite_lock(&sc_bufrwl);\n\t*(u32 *)pld = data;\t\t// pld aliases sc_buf\n\tRB_SC_CLRCRC();\n\twrite_unlock(&sc_bufrwl);\n\n\treturn count;\n}\nstatic struct sc_u32tvs const sc_uartspeeds[] = {\n\tRB_SC_TVS(RB_UART_SPEED_OFF,\t\"off\"),\n\tRB_SC_TVS(RB_UART_SPEED_1200,\t\"1200\"),\n\tRB_SC_TVS(RB_UART_SPEED_2400,\t\"2400\"),\n\tRB_SC_TVS(RB_UART_SPEED_4800,\t\"4800\"),\n\tRB_SC_TVS(RB_UART_SPEED_9600,\t\"9600\"),\n\tRB_SC_TVS(RB_UART_SPEED_19200,\t\"19200\"),\n\tRB_SC_TVS(RB_UART_SPEED_38400,\t\"38400\"),\n\tRB_SC_TVS(RB_UART_SPEED_57600,\t\"57600\"),\n\tRB_SC_TVS(RB_UART_SPEED_115200,\t\"115200\"),\n};\n\n/*\n * While the defines are carried over from rbcfg, use strings that more clearly\n * show the actual setting purpose (especially since the NAND* settings apply\n * to both nand- and nor-based devices). \"cfcard\" was disabled in rbcfg: disable\n * it here too.\n */\nstatic struct sc_u32tvs const sc_bootdevices[] = {\n\tRB_SC_TVS(RB_BOOT_DEVICE_ETHER,\t\t\"eth\"),\n\tRB_SC_TVS(RB_BOOT_DEVICE_NANDETH,\t\"flasheth\"),\n\t//RB_SC_TVS(RB_BOOT_DEVICE_CFCARD,\t\"cfcard\"),\n\tRB_SC_TVS(RB_BOOT_DEVICE_ETHONCE,\t\"ethonce\"),\n\tRB_SC_TVS(RB_BOOT_DEVICE_NANDONLY,\t\"flash\"),\n\tRB_SC_TVS(RB_BOOT_DEVICE_FLASHCFG,\t\"cfg\"),\n\tRB_SC_TVS(RB_BOOT_DEVICE_FLSHONCE,\t\"cfgonce\"),\n};\n\nstatic struct sc_boolts const sc_bootkey = {\n\t.strfalse = \"any\",\n\t.strtrue = \"del\",\n};\n\nstatic struct sc_boolts const sc_cpumode = {\n\t.strfalse = \"powersave\",\n\t.strtrue = \"regular\",\n};\n\nstatic struct sc_boolts const sc_bootproto = {\n\t.strfalse = \"bootp\",\n\t.strtrue = \"dhcp\",\n};\n\nstatic struct sc_boolts const sc_booter = {\n\t.strfalse = \"regular\",\n\t.strtrue = \"backup\",\n};\n\nstatic struct sc_boolts const sc_silent_boot = {\n\t.strfalse = \"off\",\n\t.strtrue = \"on\",\n};\n\n#define SC_TAG_SHOW_STORE_U32TVS_FUNCS(_name)\t\t\\\nstatic ssize_t sc_tag_show_##_name(const u8 *pld, u16 pld_len, char *buf)\t\\\n{\t\t\t\t\t\t\t\t\t\t\\\n\treturn sc_tag_show_u32tvs(pld, pld_len, buf, sc_##_name, ARRAY_SIZE(sc_##_name));\t\\\n}\t\t\t\t\t\t\t\t\t\t\\\nstatic ssize_t sc_tag_store_##_name(const u8 *pld, u16 pld_len, const char *buf, size_t count)\t\\\n{\t\t\t\t\t\t\t\t\t\t\\\n\treturn sc_tag_store_u32tvs(pld, pld_len, buf, count, sc_##_name, ARRAY_SIZE(sc_##_name));\t\\\n}\n\n#define SC_TAG_SHOW_STORE_BOOLTS_FUNCS(_name)\t\t\\\nstatic ssize_t sc_tag_show_##_name(const u8 *pld, u16 pld_len, char *buf)\t\\\n{\t\t\t\t\t\t\t\t\t\t\\\n\treturn sc_tag_show_boolts(pld, pld_len, buf, &sc_##_name);\t\\\n}\t\t\t\t\t\t\t\t\t\t\\\nstatic ssize_t sc_tag_store_##_name(const u8 *pld, u16 pld_len, const char *buf, size_t count)\t\\\n{\t\t\t\t\t\t\t\t\t\t\\\n\treturn sc_tag_store_boolts(pld, pld_len, buf, count, &sc_##_name);\t\\\n}\n\nSC_TAG_SHOW_STORE_U32TVS_FUNCS(uartspeeds)\nSC_TAG_SHOW_STORE_U32TVS_FUNCS(bootdevices)\nSC_TAG_SHOW_STORE_BOOLTS_FUNCS(bootkey)\nSC_TAG_SHOW_STORE_BOOLTS_FUNCS(cpumode)\nSC_TAG_SHOW_STORE_BOOLTS_FUNCS(bootproto)\nSC_TAG_SHOW_STORE_BOOLTS_FUNCS(booter)\nSC_TAG_SHOW_STORE_BOOLTS_FUNCS(silent_boot)\n\nstatic ssize_t sc_tag_show_bootdelays(const u8 *pld, u16 pld_len, char *buf)\n{\n\tconst char *fmt;\n\tchar *out = buf;\n\tu32 data;\t// cpu-endian\n\tint i;\n\n\tif (sizeof(data) != pld_len)\n\t\treturn -EINVAL;\n\n\tread_lock(&sc_bufrwl);\n\tdata = *(u32 *)pld;\t\t// pld aliases sc_buf\n\tread_unlock(&sc_bufrwl);\n\n\tfor (i = RB_BOOT_DELAY_MIN; i <= RB_BOOT_DELAY_MAX; i++) {\n\t\tfmt = (i == data) ? \"[%d] \" : \"%d \";\n\t\tout += sprintf(out, fmt, i);\n\t}\n\n\tout += sprintf(out, \"\\n\");\n\treturn out - buf;\n}\n\nstatic ssize_t sc_tag_store_bootdelays(const u8 *pld, u16 pld_len, const char *buf, size_t count)\n{\n\tu32 data;\t// cpu-endian\n\tint ret;\n\n\tif (sizeof(data) != pld_len)\n\t\treturn -EINVAL;\n\n\tret = kstrtou32(buf, 10, &data);\n\tif (ret)\n\t\treturn ret;\n\n\tif ((data < RB_BOOT_DELAY_MIN) || (RB_BOOT_DELAY_MAX < data))\n\t\treturn -EINVAL;\n\n\twrite_lock(&sc_bufrwl);\n\t*(u32 *)pld = data;\t\t// pld aliases sc_buf\n\tRB_SC_CLRCRC();\n\twrite_unlock(&sc_bufrwl);\n\n\treturn count;\n}\n\n/* Support CPU frequency accessors only when the tag format has been asserted */\n#if defined(CONFIG_ATH79)\n/* Use the same letter-based nomenclature as RouterBOOT */\nstatic struct sc_u32tvs const sc_cpufreq_indexes_ath79_9x[] = {\n\tRB_SC_TVS(RB_CPU_FREQ_IDX_ATH79_9X_A,\t\"a\"),\n\tRB_SC_TVS(RB_CPU_FREQ_IDX_ATH79_9X_B,\t\"b\"),\n\tRB_SC_TVS(RB_CPU_FREQ_IDX_ATH79_9X_C,\t\"c\"),\n\tRB_SC_TVS(RB_CPU_FREQ_IDX_ATH79_9X_D,\t\"d\"),\n\tRB_SC_TVS(RB_CPU_FREQ_IDX_ATH79_9X_E,\t\"e\"),\n\tRB_SC_TVS(RB_CPU_FREQ_IDX_ATH79_9X_F,\t\"f\"),\n};\n\nstatic struct sc_u32tvs const sc_cpufreq_indexes_ath79_7x[] = {\n\tRB_SC_TVS(RB_CPU_FREQ_IDX_ATH79_7X_A,\t\"a\"),\n\tRB_SC_TVS(RB_CPU_FREQ_IDX_ATH79_7X_B,\t\"b\"),\n\tRB_SC_TVS(RB_CPU_FREQ_IDX_ATH79_7X_C,\t\"c\"),\n\tRB_SC_TVS(RB_CPU_FREQ_IDX_ATH79_7X_D,\t\"d\"),\n\tRB_SC_TVS(RB_CPU_FREQ_IDX_ATH79_7X_E,\t\"e\"),\n\tRB_SC_TVS(RB_CPU_FREQ_IDX_ATH79_7X_F,\t\"f\"),\n\tRB_SC_TVS(RB_CPU_FREQ_IDX_ATH79_7X_G,\t\"g\"),\n\tRB_SC_TVS(RB_CPU_FREQ_IDX_ATH79_7X_H,\t\"h\"),\n};\n\nstatic int sc_tag_cpufreq_ath79_arraysize(void)\n{\n\tint idx_max;\n\n\tif (ATH79_SOC_AR7161 == ath79_soc)\n\t\tidx_max = RB_CPU_FREQ_IDX_ATH79_7X_AR7161_MAX+1;\n\telse if (soc_is_ar724x())\n\t\tidx_max = RB_CPU_FREQ_IDX_ATH79_7X_AR724X_MAX+1;\n\telse if (soc_is_ar9344())\n\t\tidx_max = RB_CPU_FREQ_IDX_ATH79_9X_AR9334_MAX+1;\n\telse if (soc_is_qca953x())\n\t\tidx_max = RB_CPU_FREQ_IDX_ATH79_9X_QCA953X_MAX+1;\n\telse if (soc_is_qca9556())\n\t\tidx_max = RB_CPU_FREQ_IDX_ATH79_9X_QCA9556_MAX+1;\n\telse if (soc_is_qca9558())\n\t\tidx_max = RB_CPU_FREQ_IDX_ATH79_9X_QCA9558_MAX+1;\n\telse\n\t\tidx_max = -EOPNOTSUPP;\n\n\treturn idx_max;\n}\n\nstatic ssize_t sc_tag_show_cpufreq_indexes(const u8 *pld, u16 pld_len, char *buf)\n{\n\tconst struct sc_u32tvs *tvs;\n\n\tif (soc_is_ar71xx() || soc_is_ar724x())\n\t\ttvs = sc_cpufreq_indexes_ath79_7x;\n\telse\n\t\ttvs = sc_cpufreq_indexes_ath79_9x;\n\n\treturn sc_tag_show_u32tvs(pld, pld_len, buf, tvs, sc_tag_cpufreq_ath79_arraysize());\n}\n\nstatic ssize_t sc_tag_store_cpufreq_indexes(const u8 *pld, u16 pld_len, const char *buf, size_t count)\n{\n\tconst struct sc_u32tvs *tvs;\n\n\tif (soc_is_ar71xx() || soc_is_ar724x())\n\t\ttvs = sc_cpufreq_indexes_ath79_7x;\n\telse\n\t\ttvs = sc_cpufreq_indexes_ath79_9x;\n\n\treturn sc_tag_store_u32tvs(pld, pld_len, buf, count, tvs, sc_tag_cpufreq_ath79_arraysize());\n}\n#else\n /* By default we only show the raw value to help with reverse-engineering */\n #define sc_tag_show_cpufreq_indexes\trouterboot_tag_show_u32s\n #define sc_tag_store_cpufreq_indexes\tNULL\n#endif\n\nstatic ssize_t sc_attr_show(struct kobject *kobj, struct kobj_attribute *attr,\n\t\t\t    char *buf);\nstatic ssize_t sc_attr_store(struct kobject *kobj, struct kobj_attribute *attr,\n\t\t\t     const char *buf, size_t count);\n\n/* Array of known tags to publish in sysfs */\nstatic struct sc_attr {\n\tconst u16 tag_id;\n\t/* sysfs tag show attribute. Must lock sc_buf when dereferencing pld */\n\tssize_t (* const tshow)(const u8 *pld, u16 pld_len, char *buf);\n\t/* sysfs tag store attribute. Must lock sc_buf when dereferencing pld */\n\tssize_t (* const tstore)(const u8 *pld, u16 pld_len, const char *buf, size_t count);\n\tstruct kobj_attribute kattr;\n\tu16 pld_ofs;\n\tu16 pld_len;\n} sc_attrs[] = {\n\t{\n\t\t.tag_id = RB_SCID_UART_SPEED,\n\t\t.tshow = sc_tag_show_uartspeeds,\n\t\t.tstore = sc_tag_store_uartspeeds,\n\t\t.kattr = __ATTR(uart_speed, RB_SC_RMODE|RB_SC_WMODE, sc_attr_show, sc_attr_store),\n\t}, {\n\t\t.tag_id = RB_SCID_BOOT_DELAY,\n\t\t.tshow = sc_tag_show_bootdelays,\n\t\t.tstore = sc_tag_store_bootdelays,\n\t\t.kattr = __ATTR(boot_delay, RB_SC_RMODE|RB_SC_WMODE, sc_attr_show, sc_attr_store),\n\t}, {\n\t\t.tag_id = RB_SCID_BOOT_DEVICE,\n\t\t.tshow = sc_tag_show_bootdevices,\n\t\t.tstore = sc_tag_store_bootdevices,\n\t\t.kattr = __ATTR(boot_device, RB_SC_RMODE|RB_SC_WMODE, sc_attr_show, sc_attr_store),\n\t}, {\n\t\t.tag_id = RB_SCID_BOOT_KEY,\n\t\t.tshow = sc_tag_show_bootkey,\n\t\t.tstore = sc_tag_store_bootkey,\n\t\t.kattr = __ATTR(boot_key, RB_SC_RMODE|RB_SC_WMODE, sc_attr_show, sc_attr_store),\n\t}, {\n\t\t.tag_id = RB_SCID_CPU_MODE,\n\t\t.tshow = sc_tag_show_cpumode,\n\t\t.tstore = sc_tag_store_cpumode,\n\t\t.kattr = __ATTR(cpu_mode, RB_SC_RMODE|RB_SC_WMODE, sc_attr_show, sc_attr_store),\n\t}, {\n\t\t.tag_id = RB_SCID_BIOS_VERSION,\n\t\t.tshow = routerboot_tag_show_string,\n\t\t.tstore = NULL,\n\t\t.kattr = __ATTR(bios_version, RB_SC_RMODE, sc_attr_show, NULL),\n\t}, {\n\t\t.tag_id = RB_SCID_BOOT_PROTOCOL,\n\t\t.tshow = sc_tag_show_bootproto,\n\t\t.tstore = sc_tag_store_bootproto,\n\t\t.kattr = __ATTR(boot_proto, RB_SC_RMODE|RB_SC_WMODE, sc_attr_show, sc_attr_store),\n\t}, {\n\t\t.tag_id = RB_SCID_CPU_FREQ_IDX,\n\t\t.tshow = sc_tag_show_cpufreq_indexes,\n\t\t.tstore = sc_tag_store_cpufreq_indexes,\n\t\t.kattr = __ATTR(cpufreq_index, RB_SC_RMODE|RB_SC_WMODE, sc_attr_show, sc_attr_store),\n\t}, {\n\t\t.tag_id = RB_SCID_BOOTER,\n\t\t.tshow = sc_tag_show_booter,\n\t\t.tstore = sc_tag_store_booter,\n\t\t.kattr = __ATTR(booter, RB_SC_RMODE|RB_SC_WMODE, sc_attr_show, sc_attr_store),\n\t}, {\n\t\t.tag_id = RB_SCID_SILENT_BOOT,\n\t\t.tshow = sc_tag_show_silent_boot,\n\t\t.tstore = sc_tag_store_silent_boot,\n\t\t.kattr = __ATTR(silent_boot, RB_SC_RMODE|RB_SC_WMODE, sc_attr_show, sc_attr_store),\n\t},\n};\n\nstatic ssize_t sc_attr_show(struct kobject *kobj, struct kobj_attribute *attr,\n\t\t\t    char *buf)\n{\n\tconst struct sc_attr *sc_attr;\n\tconst u8 *pld;\n\tu16 pld_len;\n\n\tsc_attr = container_of(attr, typeof(*sc_attr), kattr);\n\n\tif (!sc_attr->pld_len)\n\t\treturn -ENOENT;\n\n\tpld = sc_buf + sc_attr->pld_ofs;\t// pld aliases sc_buf -> lock!\n\tpld_len = sc_attr->pld_len;\n\n\treturn sc_attr->tshow(pld, pld_len, buf);\n}\n\nstatic ssize_t sc_attr_store(struct kobject *kobj, struct kobj_attribute *attr,\n\t\t\t     const char *buf, size_t count)\n{\n\tconst struct sc_attr *sc_attr;\n\tconst u8 *pld;\n\tu16 pld_len;\n\n\tif (!RB_SC_HAS_WRITE_SUPPORT)\n\t\treturn -EOPNOTSUPP;\n\n\tif (!capable(CAP_SYS_ADMIN))\n\t\treturn -EACCES;\n\n\tsc_attr = container_of(attr, typeof(*sc_attr), kattr);\n\n\tif (!sc_attr->tstore)\n\t\treturn -EOPNOTSUPP;\n\n\tif (!sc_attr->pld_len)\n\t\treturn -ENOENT;\n\n\tpld = sc_buf + sc_attr->pld_ofs;\t// pld aliases sc_buf -> lock!\n\tpld_len = sc_attr->pld_len;\n\n\treturn sc_attr->tstore(pld, pld_len, buf, count);\n}\n\n/*\n * Shows the current buffer status:\n * \"clean\": the buffer is in sync with the mtd data\n * \"dirty\": the buffer is out of sync with the mtd data\n */\nstatic ssize_t sc_commit_show(struct kobject *kobj, struct kobj_attribute *attr,\n\t\t\t      char *buf)\n{\n\tconst char *str;\n\tchar *out = buf;\n\tu32 crc;\n\n\tread_lock(&sc_bufrwl);\n\tcrc = RB_SC_GETCRC();\n\tread_unlock(&sc_bufrwl);\n\n\tstr = (crc) ? \"clean\" : \"dirty\";\n\tout += sprintf(out, \"%s\\n\", str);\n\n\treturn out - buf;\n}\n\n/*\n * Performs buffer flushing:\n * This routine expects an input compatible with kstrtobool().\n * - a \"false\" input discards the current changes and reads data back from mtd.\n * - a \"true\" input commits the current changes to mtd.\n * If there is no pending changes, this routine is a no-op.\n * Handling failures is left as an exercise to userspace.\n */\nstatic ssize_t sc_commit_store(struct kobject *kobj, struct kobj_attribute *attr,\n\t\t\t      const char *buf, size_t count)\n{\n\tstruct mtd_info *mtd;\n\tstruct erase_info ei;\n\tsize_t bytes_rw, ret = count;\n\tbool flush;\n\tu32 crc;\n\n\tif (!RB_SC_HAS_WRITE_SUPPORT)\n\t\treturn -EOPNOTSUPP;\n\n\tread_lock(&sc_bufrwl);\n\tcrc = RB_SC_GETCRC();\n\tread_unlock(&sc_bufrwl);\n\n\tif (crc)\n\t\treturn count;\t// NO-OP\n\n\tret = kstrtobool(buf, &flush);\n\tif (ret)\n\t\treturn ret;\n\n\tmtd = get_mtd_device_nm(RB_MTD_SOFT_CONFIG);\t// TODO allow override\n\tif (IS_ERR(mtd))\n\t\treturn -ENODEV;\n\n\twrite_lock(&sc_bufrwl);\n\tif (!flush)\t// reread\n\t\tret = mtd_read(mtd, 0, mtd->size, &bytes_rw, sc_buf);\n\telse {\t// crc32 + commit\n\t\t/*\n\t\t * CRC32 is computed on the entire buffer, excluding the CRC\n\t\t * value itself. CRC is already null when we reach this point,\n\t\t * so we can compute the CRC32 on the buffer as is.\n\t\t * The expected CRC32 is Ethernet FCS style, meaning the seed is\n\t\t * ~0 and the final result is also bitflipped.\n\t\t */\n\n\t\tcrc = ~crc32(~0, sc_buf, sc_buflen);\n\t\tRB_SC_SETCRC(crc);\n\n\t\t/*\n\t\t * The soft_config partition is assumed to be entirely contained\n\t\t * in a single eraseblock.\n\t\t */\n\n\t\tei.addr = 0;\n\t\tei.len = mtd->size;\n\t\tret = mtd_erase(mtd, &ei);\n\t\tif (!ret)\n\t\t\tret = mtd_write(mtd, 0, mtd->size, &bytes_rw, sc_buf);\n\n\t\t/*\n\t\t * Handling mtd_write() failure here is a tricky situation. The\n\t\t * proposed approach is to let userspace deal with retrying,\n\t\t * with the caveat that it must try to flush the buffer again as\n\t\t * rereading the mtd contents could potentially read garbage.\n\t\t * The rationale is: even if we keep a shadow buffer of the\n\t\t * original content, there is no guarantee that we will ever be\n\t\t * able to write it anyway.\n\t\t * Regardless, it appears that RouterBOOT will ignore an invalid\n\t\t * soft_config (including a completely wiped segment) and will\n\t\t * write back factory defaults when it happens.\n\t\t */\n\t}\n\twrite_unlock(&sc_bufrwl);\n\n\tput_mtd_device(mtd);\n\n\tif (ret)\n\t\tgoto mtdfail;\n\n\tif (bytes_rw != sc_buflen) {\n\t\tret = -EIO;\n\t\tgoto mtdfail;\n\t}\n\n\treturn count;\n\nmtdfail:\n\tRB_SC_CLRCRC();\t// mark buffer content as dirty/invalid\n\treturn ret;\n}\n\nstatic struct kobj_attribute sc_kattrcommit = __ATTR(commit, RB_SC_RMODE|RB_SC_WMODE, sc_commit_show, sc_commit_store);\n\nint rb_softconfig_init(struct kobject *rb_kobj, struct mtd_info *mtd)\n{\n\tsize_t bytes_read, buflen;\n\tconst u8 *buf;\n\tint i, ret;\n\tu32 magic;\n\n\tsc_buf = NULL;\n\tsc_kobj = NULL;\n\n\tret = __get_mtd_device(mtd);\n\tif (ret)\n\t\treturn -ENODEV;\n\n\tsc_buflen = mtd->size;\n\tsc_buf = kmalloc(sc_buflen, GFP_KERNEL);\n\tif (!sc_buf) {\n\t\t__put_mtd_device(mtd);\n\t\treturn -ENOMEM;\n\t}\n\n\tret = mtd_read(mtd, 0, sc_buflen, &bytes_read, sc_buf);\n\t__put_mtd_device(mtd);\n\n\tif (ret)\n\t\tgoto fail;\n\n\tif (bytes_read != sc_buflen) {\n\t\tret = -EIO;\n\t\tgoto fail;\n\t}\n\n\t/* Check we have what we expect */\n\tmagic = *(const u32 *)sc_buf;\n\tif (RB_MAGIC_SOFT != magic) {\n\t\tret = -EINVAL;\n\t\tgoto fail;\n\t}\n\n\t/* Skip magic and 32bit CRC located immediately after */\n\tbuf = sc_buf + (sizeof(magic) + sizeof(u32));\n\tbuflen = sc_buflen - (sizeof(magic) + sizeof(u32));\n\n\t/* Populate sysfs */\n\tret = -ENOMEM;\n\tsc_kobj = kobject_create_and_add(RB_MTD_SOFT_CONFIG, rb_kobj);\n\tif (!sc_kobj)\n\t\tgoto fail;\n\n\trwlock_init(&sc_bufrwl);\n\n\t/* Locate and publish all known tags */\n\tfor (i = 0; i < ARRAY_SIZE(sc_attrs); i++) {\n\t\tret = routerboot_tag_find(buf, buflen, sc_attrs[i].tag_id,\n\t\t\t\t\t  &sc_attrs[i].pld_ofs, &sc_attrs[i].pld_len);\n\t\tif (ret) {\n\t\t\tsc_attrs[i].pld_ofs = sc_attrs[i].pld_len = 0;\n\t\t\tcontinue;\n\t\t}\n\n\t\t/* Account for skipped magic and crc32 */\n\t\tsc_attrs[i].pld_ofs += sizeof(magic) + sizeof(u32);\n\n\t\tret = sysfs_create_file(sc_kobj, &sc_attrs[i].kattr.attr);\n\t\tif (ret)\n\t\t\tpr_warn(RB_SC_PR_PFX \"Could not create %s sysfs entry (%d)\\n\",\n\t\t\t       sc_attrs[i].kattr.attr.name, ret);\n\t}\n\n\t/* Finally add the 'commit' attribute */\n\tif (RB_SC_HAS_WRITE_SUPPORT) {\n\t\tret = sysfs_create_file(sc_kobj, &sc_kattrcommit.attr);\n\t\tif (ret) {\n\t\t\tpr_err(RB_SC_PR_PFX \"Could not create %s sysfs entry (%d), aborting!\\n\",\n\t\t\t       sc_kattrcommit.attr.name, ret);\n\t\t\tgoto sysfsfail;\t// required attribute\n\t\t}\n\t}\n\n\tpr_info(\"MikroTik RouterBOARD software configuration sysfs driver v\" RB_SOFTCONFIG_VER \"\\n\");\n\n\treturn 0;\n\nsysfsfail:\n\tkobject_put(sc_kobj);\n\tsc_kobj = NULL;\nfail:\n\tkfree(sc_buf);\n\tsc_buf = NULL;\n\treturn ret;\n}\n\nvoid rb_softconfig_exit(void)\n{\n\tkobject_put(sc_kobj);\n\tsc_kobj = NULL;\n\tkfree(sc_buf);\n\tsc_buf = NULL;\n}\n"
  },
  {
    "path": "target/linux/generic/files/drivers/platform/mikrotik/routerboot.c",
    "content": "// SPDX-License-Identifier: GPL-2.0-only\n/*\n * Driver for MikroTik RouterBoot flash data. Common routines.\n *\n * Copyright (C) 2020 Thibaut VARÈNE <hacks+kernel@slashdirt.org>\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of the GNU General Public License version 2 as published\n * by the Free Software Foundation.\n */\n\n#include <linux/types.h>\n#include <linux/module.h>\n#include <linux/kernel.h>\n#include <linux/sysfs.h>\n#include <linux/mtd/mtd.h>\n\n#include \"routerboot.h\"\n\nstatic struct kobject *rb_kobj;\n\n/**\n * routerboot_tag_find() - Locate a given tag in routerboot config data.\n * @bufhead: the buffer to look into. Must start with a tag node.\n * @buflen: size of bufhead\n * @tag_id: the tag identifier to look for\n * @pld_ofs: will be updated with tag payload offset in bufhead, if tag found\n * @pld_len: will be updated with tag payload size, if tag found\n *\n * This incarnation of tag_find() does only that: it finds a specific routerboot\n * tag node in the input buffer. Routerboot tag nodes are u32 values:\n * - The low nibble is the tag identification number,\n * - The high nibble is the tag payload length (node excluded) in bytes.\n * The payload immediately follows the tag node. Tag nodes are 32bit-aligned.\n * The returned pld_ofs will always be aligned. pld_len may not end on 32bit\n * boundary (the only known case is when parsing ERD data).\n * The nodes are cpu-endian on the flash media. The payload is cpu-endian when\n * applicable. Tag nodes are not ordered (by ID) on flash.\n *\n * Return: 0 on success (tag found) or errno\n */\nint routerboot_tag_find(const u8 *bufhead, const size_t buflen, const u16 tag_id,\n\t\t\tu16 *pld_ofs, u16 *pld_len)\n{\n\tconst u32 *datum, *bufend;\n\tu32 node;\n\tu16 id, len;\n\tint ret;\n\n\tif (!bufhead || !tag_id)\n\t\treturn -EINVAL;\n\n\tret = -ENOENT;\n\tdatum = (const u32 *)bufhead;\n\tbufend = (const u32 *)(bufhead + buflen);\n\n\twhile (datum < bufend) {\n\t\tnode = *datum++;\n\n\t\t/* Tag list ends with null node */\n\t\tif (!node)\n\t\t\tbreak;\n\n\t\tid = node & 0xFFFF;\n\t\tlen = node >> 16;\n\n\t\tif (tag_id == id) {\n\t\t\tif (datum >= bufend)\n\t\t\t\tbreak;\n\n\t\t\tif (pld_ofs)\n\t\t\t\t*pld_ofs = (u16)((u8 *)datum - bufhead);\n\t\t\tif (pld_len)\n\t\t\t\t*pld_len = len;\n\n\t\t\tret = 0;\n\t\t\tbreak;\n\t\t}\n\n\t\t/*\n\t\t * The only known situation where len may not end on 32bit\n\t\t * boundary is within ERD data. Since we're only extracting\n\t\t * one tag (the first and only one) from that data, we should\n\t\t * never need to forcefully ALIGN(). Do it anyway, this is not a\n\t\t * performance path.\n\t\t */\n\t\tlen = ALIGN(len, sizeof(*datum));\n\t\tdatum += len / sizeof(*datum);\n\t}\n\n\treturn ret;\n}\n\n/**\n * routerboot_rle_decode() - Simple RLE (MikroTik variant) decoding routine.\n * @in: input buffer to decode\n * @inlen: size of in\n * @out: output buffer to write decoded data to\n * @outlen: pointer to out size when function is called, will be updated with\n * size of decoded output on return\n *\n * MikroTik's variant of RLE operates as follows, considering a signed run byte:\n * - positive run => classic RLE\n * - negative run => the next -<run> bytes must be copied verbatim\n * The API is matched to the lzo1x routines for convenience.\n *\n * NB: The output buffer cannot overlap with the input buffer.\n *\n * Return: 0 on success or errno\n */\nint routerboot_rle_decode(const u8 *in, size_t inlen, u8 *out, size_t *outlen)\n{\n\tint ret, run, nbytes;\t// use native types for speed\n\tu8 byte;\n\n\tif (!in || (inlen < 2) || !out)\n\t\treturn -EINVAL;\n\n\tret = -ENOSPC;\n\tnbytes = 0;\n\twhile (inlen >= 2) {\n\t\trun = *in++;\n\t\tinlen--;\n\n\t\t/* Verbatim copies */\n\t\tif (run & 0x80) {\n\t\t\t/* Invert run byte sign */\n\t\t\trun = ~run & 0xFF;\n\t\t\trun++;\n\n\t\t\tif (run > inlen)\n\t\t\t\tgoto fail;\n\n\t\t\tinlen -= run;\n\n\t\t\tnbytes += run;\n\t\t\tif (nbytes > *outlen)\n\t\t\t\tgoto fail;\n\n\t\t\t/* Basic memcpy */\n\t\t\twhile (run-- > 0)\n\t\t\t\t*out++ = *in++;\n\t\t}\n\t\t/* Stream of half-words RLE: <run><byte>. run == 0 is ignored */\n\t\telse {\n\t\t\tbyte = *in++;\n\t\t\tinlen--;\n\n\t\t\tnbytes += run;\n\t\t\tif (nbytes > *outlen)\n\t\t\t\tgoto fail;\n\n\t\t\twhile (run-- > 0)\n\t\t\t\t*out++ = byte;\n\t\t}\n\t}\n\n\tret = 0;\nfail:\n\t*outlen = nbytes;\n\treturn ret;\n}\n\nstatic void routerboot_mtd_notifier_add(struct mtd_info *mtd)\n{\n\t/* Currently routerboot is only known to live on NOR flash */\n\tif (mtd->type != MTD_NORFLASH)\n\t\treturn;\n\n\t/*\n\t * We ignore the following return values and always register.\n\t * These init() routines are designed so that their failed state is\n\t * always manageable by the corresponding exit() calls.\n\t * Notifier is called with MTD mutex held: use __get/__put variants.\n\t * TODO: allow partition names override\n\t */\n\tif (!strcmp(mtd->name, RB_MTD_HARD_CONFIG))\n\t\trb_hardconfig_init(rb_kobj, mtd);\n\telse if (!strcmp(mtd->name, RB_MTD_SOFT_CONFIG))\n\t\trb_softconfig_init(rb_kobj, mtd);\n}\n\nstatic void routerboot_mtd_notifier_remove(struct mtd_info *mtd)\n{\n\tif (mtd->type != MTD_NORFLASH)\n\t\treturn;\n\n\tif (!strcmp(mtd->name, RB_MTD_HARD_CONFIG))\n\t\trb_hardconfig_exit();\n\telse if (!strcmp(mtd->name, RB_MTD_SOFT_CONFIG))\n\t\trb_softconfig_exit();\n}\n\n/* Note: using a notifier prevents qualifying init()/exit() functions with __init/__exit */\nstatic struct mtd_notifier routerboot_mtd_notifier = {\n\t.add = routerboot_mtd_notifier_add,\n\t.remove = routerboot_mtd_notifier_remove,\n};\n\nstatic int __init routerboot_init(void)\n{\n\trb_kobj = kobject_create_and_add(\"mikrotik\", firmware_kobj);\n\tif (!rb_kobj)\n\t\treturn -ENOMEM;\n\n\tregister_mtd_user(&routerboot_mtd_notifier);\n\n\treturn 0;\n}\n\nstatic void __exit routerboot_exit(void)\n{\n\tunregister_mtd_user(&routerboot_mtd_notifier);\n\t/* Exit routines are idempotent */\n\trb_softconfig_exit();\n\trb_hardconfig_exit();\n\tkobject_put(rb_kobj);\t// recursive afaict\n}\n\n/* Common routines */\n\nssize_t routerboot_tag_show_string(const u8 *pld, u16 pld_len, char *buf)\n{\n\treturn scnprintf(buf, pld_len+1, \"%s\\n\", pld);\n}\n\nssize_t routerboot_tag_show_u32s(const u8 *pld, u16 pld_len, char *buf)\n{\n\tchar *out = buf;\n\tu32 *data;\t// cpu-endian\n\n\t/* Caller ensures pld_len > 0 */\n\tif (pld_len % sizeof(*data))\n\t\treturn -EINVAL;\n\n\tdata = (u32 *)pld;\n\n\tdo {\n\t\tout += sprintf(out, \"0x%08x\\n\", *data);\n\t\tdata++;\n\t} while ((pld_len -= sizeof(*data)));\n\n\treturn out - buf;\n}\n\nmodule_init(routerboot_init);\nmodule_exit(routerboot_exit);\n\nMODULE_LICENSE(\"GPL v2\");\nMODULE_DESCRIPTION(\"MikroTik RouterBoot sysfs support\");\nMODULE_AUTHOR(\"Thibaut VARENE\");\n"
  },
  {
    "path": "target/linux/generic/files/drivers/platform/mikrotik/routerboot.h",
    "content": "// SPDX-License-Identifier: GPL-2.0-only\n/*\n * Common definitions for MikroTik RouterBoot data.\n *\n * Copyright (C) 2020 Thibaut VARÈNE <hacks+kernel@slashdirt.org>\n */\n\n\n#ifndef _ROUTERBOOT_H_\n#define _ROUTERBOOT_H_\n\n#include <linux/types.h>\n\n// these magic values are stored in cpu-endianness on flash\n#define RB_MAGIC_HARD\t(('H') | ('a' << 8) | ('r' << 16) | ('d' << 24))\n#define RB_MAGIC_SOFT\t(('S') | ('o' << 8) | ('f' << 16) | ('t' << 24))\n#define RB_MAGIC_LZOR\t(('L') | ('Z' << 8) | ('O' << 16) | ('R' << 24))\n#define RB_MAGIC_ERD\t(('E' << 16) | ('R' << 8) | ('D'))\n\n#define RB_ART_SIZE\t0x10000\n\n#define RB_MTD_HARD_CONFIG\t\"hard_config\"\n#define RB_MTD_SOFT_CONFIG\t\"soft_config\"\n\nint routerboot_tag_find(const u8 *bufhead, const size_t buflen, const u16 tag_id, u16 *pld_ofs, u16 *pld_len);\nint routerboot_rle_decode(const u8 *in, size_t inlen, u8 *out, size_t *outlen);\n\nint rb_hardconfig_init(struct kobject *rb_kobj, struct mtd_info *mtd);\nvoid rb_hardconfig_exit(void);\n\nint rb_softconfig_init(struct kobject *rb_kobj, struct mtd_info *mtd);\nvoid rb_softconfig_exit(void);\n\nssize_t routerboot_tag_show_string(const u8 *pld, u16 pld_len, char *buf);\nssize_t routerboot_tag_show_u32s(const u8 *pld, u16 pld_len, char *buf);\n\n#endif /* _ROUTERBOOT_H_ */\n"
  },
  {
    "path": "target/linux/generic/files/include/dt-bindings/mtd/partitions/uimage.h",
    "content": "/* SPDX-License-Identifier: GPL-2.0-only */\n/*\n *    *** IMPORTANT ***\n * This file is not only included from C-code but also from devicetree source\n * files. As such this file MUST only contain comments and defines.\n *\n * Based on image.h from U-Boot which is\n * (C) Copyright 2008 Semihalf\n * (C) Copyright 2000-2005 Wolfgang Denk, DENX Software Engineering, wd@denx.de.\n */\n\n#ifndef __UIMAGE_H__\n#define __UIMAGE_H__\n\n/*\n * Operating System Codes\n *\n * The following are exposed to uImage header.\n * New IDs *MUST* be appended at the end of the list and *NEVER*\n * inserted for backward compatibility.\n */\n#define\tIH_OS_INVALID\t\t0\t/* Invalid OS\t*/\n#define\tIH_OS_OPENBSD\t\t1\t/* OpenBSD\t*/\n#define\tIH_OS_NETBSD\t\t2\t/* NetBSD\t*/\n#define\tIH_OS_FREEBSD\t\t3\t/* FreeBSD\t*/\n#define\tIH_OS_4_4BSD\t\t4\t/* 4.4BSD\t*/\n#define\tIH_OS_LINUX\t\t5\t/* Linux\t*/\n#define\tIH_OS_SVR4\t\t6\t/* SVR4\t\t*/\n#define\tIH_OS_ESIX\t\t7\t/* Esix\t\t*/\n#define\tIH_OS_SOLARIS\t\t8\t/* Solaris\t*/\n#define\tIH_OS_IRIX\t\t9\t/* Irix\t\t*/\n#define\tIH_OS_SCO\t       10\t/* SCO\t\t*/\n#define\tIH_OS_DELL\t       11\t/* Dell\t\t*/\n#define\tIH_OS_NCR\t       12\t/* NCR\t\t*/\n#define\tIH_OS_LYNXOS\t       13\t/* LynxOS\t*/\n#define\tIH_OS_VXWORKS\t       14\t/* VxWorks\t*/\n#define\tIH_OS_PSOS\t       15\t/* pSOS\t\t*/\n#define\tIH_OS_QNX\t       16\t/* QNX\t\t*/\n#define\tIH_OS_U_BOOT\t       17\t/* Firmware\t*/\n#define\tIH_OS_RTEMS\t       18\t/* RTEMS\t*/\n#define\tIH_OS_ARTOS\t       19\t/* ARTOS\t*/\n#define\tIH_OS_UNITY\t       20\t/* Unity OS\t*/\n#define\tIH_OS_INTEGRITY\t       21\t/* INTEGRITY\t*/\n#define\tIH_OS_OSE\t       22\t/* OSE\t\t*/\n#define\tIH_OS_PLAN9\t       23\t/* Plan 9\t*/\n#define\tIH_OS_OPENRTOS\t       24\t/* OpenRTOS\t*/\n#define\tIH_OS_ARM_TRUSTED_FIRMWARE 25    /* ARM Trusted Firmware */\n#define\tIH_OS_TEE\t       26\t/* Trusted Execution Environment */\n#define\tIH_OS_OPENSBI\t       27\t/* RISC-V OpenSBI */\n#define\tIH_OS_EFI\t       28\t/* EFI Firmware (e.g. GRUB2) */\n\n/*\n * CPU Architecture Codes (supported by Linux)\n *\n * The following are exposed to uImage header.\n * New IDs *MUST* be appended at the end of the list and *NEVER*\n * inserted for backward compatibility.\n */\n#define\tIH_ARCH_INVALID\t\t0\t/* Invalid CPU\t*/\n#define\tIH_ARCH_ALPHA\t\t1\t/* Alpha\t*/\n#define\tIH_ARCH_ARM\t\t2\t/* ARM\t\t*/\n#define\tIH_ARCH_I386\t\t3\t/* Intel x86\t*/\n#define\tIH_ARCH_IA64\t\t4\t/* IA64\t\t*/\n#define\tIH_ARCH_MIPS\t\t5\t/* MIPS\t\t*/\n#define\tIH_ARCH_MIPS64\t\t6\t/* MIPS\t 64 Bit */\n#define\tIH_ARCH_PPC\t\t7\t/* PowerPC\t*/\n#define\tIH_ARCH_S390\t\t8\t/* IBM S390\t*/\n#define\tIH_ARCH_SH\t\t9\t/* SuperH\t*/\n#define\tIH_ARCH_SPARC\t       10\t/* Sparc\t*/\n#define\tIH_ARCH_SPARC64\t       11\t/* Sparc 64 Bit */\n#define\tIH_ARCH_M68K\t       12\t/* M68K\t\t*/\n#define\tIH_ARCH_NIOS\t       13\t/* Nios-32\t*/\n#define\tIH_ARCH_MICROBLAZE     14\t/* MicroBlaze   */\n#define\tIH_ARCH_NIOS2\t       15\t/* Nios-II\t*/\n#define\tIH_ARCH_BLACKFIN       16\t/* Blackfin\t*/\n#define\tIH_ARCH_AVR32\t       17\t/* AVR32\t*/\n#define\tIH_ARCH_ST200\t       18\t/* STMicroelectronics ST200  */\n#define\tIH_ARCH_SANDBOX\t       19\t/* Sandbox architecture (test only) */\n#define\tIH_ARCH_NDS32\t       20\t/* ANDES Technology - NDS32  */\n#define\tIH_ARCH_OPENRISC       21\t/* OpenRISC 1000  */\n#define\tIH_ARCH_ARM64\t       22\t/* ARM64\t*/\n#define\tIH_ARCH_ARC\t       23\t/* Synopsys DesignWare ARC */\n#define\tIH_ARCH_X86_64\t       24\t/* AMD x86_64, Intel and Via */\n#define\tIH_ARCH_XTENSA\t       25\t/* Xtensa\t*/\n#define\tIH_ARCH_RISCV\t       26\t/* RISC-V */\n\n/*\n * Image Types\n *\n * \"Standalone Programs\" are directly runnable in the environment\n *\tprovided by U-Boot; it is expected that (if they behave\n *\twell) you can continue to work in U-Boot after return from\n *\tthe Standalone Program.\n * \"OS Kernel Images\" are usually images of some Embedded OS which\n *\twill take over control completely. Usually these programs\n *\twill install their own set of exception handlers, device\n *\tdrivers, set up the MMU, etc. - this means, that you cannot\n *\texpect to re-enter U-Boot except by resetting the CPU.\n * \"RAMDisk Images\" are more or less just data blocks, and their\n *\tparameters (address, size) are passed to an OS kernel that is\n *\tbeing started.\n * \"Multi-File Images\" contain several images, typically an OS\n *\t(Linux) kernel image and one or more data images like\n *\tRAMDisks. This construct is useful for instance when you want\n *\tto boot over the network using BOOTP etc., where the boot\n *\tserver provides just a single image file, but you want to get\n *\tfor instance an OS kernel and a RAMDisk image.\n *\n *\t\"Multi-File Images\" start with a list of image sizes, each\n *\timage size (in bytes) specified by an \"uint32_t\" in network\n *\tbyte order. This list is terminated by an \"(uint32_t)0\".\n *\tImmediately after the terminating 0 follow the images, one by\n *\tone, all aligned on \"uint32_t\" boundaries (size rounded up to\n *\ta multiple of 4 bytes - except for the last file).\n *\n * \"Firmware Images\" are binary images containing firmware (like\n *\tU-Boot or FPGA images) which usually will be programmed to\n *\tflash memory.\n *\n * \"Script files\" are command sequences that will be executed by\n *\tU-Boot's command interpreter; this feature is especially\n *\tuseful when you configure U-Boot to use a real shell (hush)\n *\tas command interpreter (=> Shell Scripts).\n *\n * The following are exposed to uImage header.\n * New IDs *MUST* be appended at the end of the list and *NEVER*\n * inserted for backward compatibility.\n */\n#define\tIH_TYPE_INVALID\t\t0\t/* Invalid Image\t\t*/\n#define\tIH_TYPE_STANDALONE\t1\t/* Standalone Program\t\t*/\n#define\tIH_TYPE_KERNEL\t\t2\t/* OS Kernel Image\t\t*/\n#define\tIH_TYPE_RAMDISK\t\t3\t/* RAMDisk Image\t\t*/\n#define\tIH_TYPE_MULTI\t\t4\t/* Multi-File Image\t\t*/\n#define\tIH_TYPE_FIRMWARE\t5\t/* Firmware Image\t\t*/\n#define\tIH_TYPE_SCRIPT\t\t6\t/* Script file\t\t\t*/\n#define\tIH_TYPE_FILESYSTEM\t7\t/* Filesystem Image (any type)\t*/\n#define\tIH_TYPE_FLATDT\t\t8\t/* Binary Flat Device Tree Blob\t*/\n#define\tIH_TYPE_KWBIMAGE\t9\t/* Kirkwood Boot Image\t\t*/\n#define\tIH_TYPE_IMXIMAGE       10\t/* Freescale IMXBoot Image\t*/\n#define\tIH_TYPE_UBLIMAGE       11\t/* Davinci UBL Image\t\t*/\n#define\tIH_TYPE_OMAPIMAGE      12\t/* TI OMAP Config Header Image\t*/\n#define\tIH_TYPE_AISIMAGE       13\t/* TI Davinci AIS Image\t\t*/\n\t/* OS Kernel Image, can run from any load address */\n#define\tIH_TYPE_KERNEL_NOLOAD  14\n#define\tIH_TYPE_PBLIMAGE       15\t/* Freescale PBL Boot Image\t*/\n#define\tIH_TYPE_MXSIMAGE       16\t/* Freescale MXSBoot Image\t*/\n#define\tIH_TYPE_GPIMAGE\t       17\t/* TI Keystone GPHeader Image\t*/\n#define\tIH_TYPE_ATMELIMAGE     18\t/* ATMEL ROM bootable Image\t*/\n#define\tIH_TYPE_SOCFPGAIMAGE   19\t/* Altera SOCFPGA CV/AV Preloader */\n#define\tIH_TYPE_X86_SETUP      20\t/* x86 setup.bin Image\t\t*/\n#define\tIH_TYPE_LPC32XXIMAGE   21\t/* x86 setup.bin Image\t\t*/\n#define\tIH_TYPE_LOADABLE       22\t/* A list of typeless images\t*/\n#define\tIH_TYPE_RKIMAGE\t       23\t/* Rockchip Boot Image\t\t*/\n#define\tIH_TYPE_RKSD\t       24\t/* Rockchip SD card\t\t*/\n#define\tIH_TYPE_RKSPI\t       25\t/* Rockchip SPI image\t\t*/\n#define\tIH_TYPE_ZYNQIMAGE      26\t/* Xilinx Zynq Boot Image */\n#define\tIH_TYPE_ZYNQMPIMAGE    27\t/* Xilinx ZynqMP Boot Image */\n#define\tIH_TYPE_ZYNQMPBIF      28\t/* Xilinx ZynqMP Boot Image (bif) */\n#define\tIH_TYPE_FPGA\t       29\t/* FPGA Image */\n#define\tIH_TYPE_VYBRIDIMAGE    30\t/* VYBRID .vyb Image */\n#define\tIH_TYPE_TEE            31\t/* Trusted Execution Environment OS Image */\n#define\tIH_TYPE_FIRMWARE_IVT   32\t/* Firmware Image with HABv4 IVT */\n#define\tIH_TYPE_PMMC           33\t/* TI Power Management Micro-Controller Firmware */\n#define\tIH_TYPE_STM32IMAGE     34\t/* STMicroelectronics STM32 Image */\n#define\tIH_TYPE_SOCFPGAIMAGE_V1 35\t/* Altera SOCFPGA A10 Preloader\t*/\n#define\tIH_TYPE_MTKIMAGE       36\t/* MediaTek BootROM loadable Image */\n#define\tIH_TYPE_IMX8MIMAGE     37\t/* Freescale IMX8MBoot Image\t*/\n#define\tIH_TYPE_IMX8IMAGE      38\t/* Freescale IMX8Boot Image\t*/\n#define\tIH_TYPE_COPRO\t       39\t/* Coprocessor Image for remoteproc*/\n\n\n/*\n * Compression Types\n *\n * The following are exposed to uImage header.\n * New IDs *MUST* be appended at the end of the list and *NEVER*\n * inserted for backward compatibility.\n */\n#define\tIH_COMP_NONE\t\t0\t/*  No\t Compression Used\t*/\n#define\tIH_COMP_GZIP\t\t1\t/* gzip\t Compression Used\t*/\n#define\tIH_COMP_BZIP2\t\t2\t/* bzip2 Compression Used\t*/\n#define\tIH_COMP_LZMA\t\t3\t/* lzma  Compression Used\t*/\n#define\tIH_COMP_LZO\t\t4\t/* lzo   Compression Used\t*/\n#define\tIH_COMP_LZ4\t\t5\t/* lz4   Compression Used\t*/\n\n\n#define LZ4F_MAGIC\t0x184D2204\t/* LZ4 Magic Number\t\t*/\n#define IH_MAGIC\t0x27051956\t/* Image Magic Number\t\t*/\n#define IH_NMLEN\t\t32\t/* Image Name Length\t\t*/\n\n/*\n * Magic values specific to \"openwrt,uimage\" partitions\n */\n#define IH_MAGIC_OKLI\t0x4f4b4c49\t/* 'OKLI'\t\t\t*/\n#define FW_EDIMAX_OFFSET\t20\t/* Edimax Firmware Offset\t*/\n#define FW_MAGIC_EDIMAX\t0x43535953\t/* Edimax Firmware Magic Number */\n\n#endif\t/* __UIMAGE_H__ */\n"
  },
  {
    "path": "target/linux/generic/files/include/linux/ar8216_platform.h",
    "content": "/*\n * AR8216 switch driver platform data\n *\n * Copyright (C) 2012 Gabor Juhos <juhosg@openwrt.org>\n *\n * This program is free software; you can redistribute it and/or\n * modify it under the terms of the GNU General Public License\n * as published by the Free Software Foundation; either version 2\n * of the License, or (at your option) any later version.\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n * GNU General Public License for more details.\n */\n\n#ifndef AR8216_PLATFORM_H\n#define AR8216_PLATFORM_H\n\nenum ar8327_pad_mode {\n\tAR8327_PAD_NC = 0,\n\tAR8327_PAD_MAC2MAC_MII,\n\tAR8327_PAD_MAC2MAC_GMII,\n\tAR8327_PAD_MAC_SGMII,\n\tAR8327_PAD_MAC2PHY_MII,\n\tAR8327_PAD_MAC2PHY_GMII,\n\tAR8327_PAD_MAC_RGMII,\n\tAR8327_PAD_PHY_GMII,\n\tAR8327_PAD_PHY_RGMII,\n\tAR8327_PAD_PHY_MII,\n};\n\nenum ar8327_clk_delay_sel {\n\tAR8327_CLK_DELAY_SEL0 = 0,\n\tAR8327_CLK_DELAY_SEL1,\n\tAR8327_CLK_DELAY_SEL2,\n\tAR8327_CLK_DELAY_SEL3,\n};\n\nstruct ar8327_pad_cfg {\n\tenum ar8327_pad_mode mode;\n\tbool rxclk_sel;\n\tbool txclk_sel;\n\tbool pipe_rxclk_sel;\n\tbool txclk_delay_en;\n\tbool rxclk_delay_en;\n\tbool sgmii_delay_en;\n\tenum ar8327_clk_delay_sel txclk_delay_sel;\n\tenum ar8327_clk_delay_sel rxclk_delay_sel;\n\tbool mac06_exchange_dis;\n};\n\nenum ar8327_port_speed {\n\tAR8327_PORT_SPEED_10 = 0,\n\tAR8327_PORT_SPEED_100,\n\tAR8327_PORT_SPEED_1000,\n};\n\nstruct ar8327_port_cfg {\n\tint force_link:1;\n\tenum ar8327_port_speed speed;\n\tint txpause:1;\n\tint rxpause:1;\n\tint duplex:1;\n};\n\nstruct ar8327_sgmii_cfg {\n\tu32 sgmii_ctrl;\n\tbool serdes_aen;\n};\n\nstruct ar8327_led_cfg {\n\tu32 led_ctrl0;\n\tu32 led_ctrl1;\n\tu32 led_ctrl2;\n\tu32 led_ctrl3;\n\tbool open_drain;\n};\n\nenum ar8327_led_num {\n\tAR8327_LED_PHY0_0 = 0,\n\tAR8327_LED_PHY0_1,\n\tAR8327_LED_PHY0_2,\n\tAR8327_LED_PHY1_0,\n\tAR8327_LED_PHY1_1,\n\tAR8327_LED_PHY1_2,\n\tAR8327_LED_PHY2_0,\n\tAR8327_LED_PHY2_1,\n\tAR8327_LED_PHY2_2,\n\tAR8327_LED_PHY3_0,\n\tAR8327_LED_PHY3_1,\n\tAR8327_LED_PHY3_2,\n\tAR8327_LED_PHY4_0,\n\tAR8327_LED_PHY4_1,\n\tAR8327_LED_PHY4_2,\n};\n\nenum ar8327_led_mode {\n\tAR8327_LED_MODE_HW = 0,\n\tAR8327_LED_MODE_SW,\n};\n\nstruct ar8327_led_info {\n\tconst char *name;\n\tconst char *default_trigger;\n\tbool active_low;\n\tenum ar8327_led_num led_num;\n\tenum ar8327_led_mode mode;\n};\n\n#define AR8327_LED_INFO(_led, _mode, _name) {\t\\\n\t.name = (_name), \t   \t\t\\\n\t.led_num = AR8327_LED_ ## _led,\t\t\\\n\t.mode = AR8327_LED_MODE_ ## _mode \t\\\n}\n\nstruct ar8327_platform_data {\n\tstruct ar8327_pad_cfg *pad0_cfg;\n\tstruct ar8327_pad_cfg *pad5_cfg;\n\tstruct ar8327_pad_cfg *pad6_cfg;\n\tstruct ar8327_sgmii_cfg *sgmii_cfg;\n\tstruct ar8327_port_cfg port0_cfg;\n\tstruct ar8327_port_cfg port6_cfg;\n\tstruct ar8327_led_cfg *led_cfg;\n\n\tint (*get_port_link)(unsigned port);\n\n\tunsigned num_leds;\n\tconst struct ar8327_led_info *leds;\n};\n\n#endif /* AR8216_PLATFORM_H */\n\n"
  },
  {
    "path": "target/linux/generic/files/include/linux/ath5k_platform.h",
    "content": "/*\n * Copyright (c) 2008 Atheros Communications Inc.\n * Copyright (c) 2009 Gabor Juhos <juhosg@openwrt.org>\n * Copyright (c) 2009 Imre Kaloz <kaloz@openwrt.org>\n * Copyright (c) 2010 Daniel Golle <daniel.golle@gmail.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n */\n\n#ifndef _LINUX_ATH5K_PLATFORM_H\n#define _LINUX_ATH5K_PLATFORM_H\n\n#define ATH5K_PLAT_EEP_MAX_WORDS\t2048\n\nstruct ath5k_platform_data {\n\tu16 *eeprom_data;\n\tu8 *macaddr;\n};\n\n#endif /* _LINUX_ATH5K_PLATFORM_H */\n"
  },
  {
    "path": "target/linux/generic/files/include/linux/ath9k_platform.h",
    "content": "/*\n * Copyright (c) 2008 Atheros Communications Inc.\n * Copyright (c) 2009 Gabor Juhos <juhosg@openwrt.org>\n * Copyright (c) 2009 Imre Kaloz <kaloz@openwrt.org>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n */\n\n#ifndef _LINUX_ATH9K_PLATFORM_H\n#define _LINUX_ATH9K_PLATFORM_H\n\n#define ATH9K_PLAT_EEP_MAX_WORDS\t2048\n\nstruct ath9k_platform_data {\n\tconst char *eeprom_name;\n\n\tu16 eeprom_data[ATH9K_PLAT_EEP_MAX_WORDS];\n\tu8 *macaddr;\n\n\tint led_pin;\n\tu32 gpio_mask;\n\tu32 gpio_val;\n\n\tu32 bt_active_pin;\n\tu32 bt_priority_pin;\n\tu32 wlan_active_pin;\n\n\tbool endian_check;\n\tbool is_clk_25mhz;\n\tbool tx_gain_buffalo;\n\tbool disable_2ghz;\n\tbool disable_5ghz;\n\tbool led_active_high;\n\n\tint (*get_mac_revision)(void);\n\tint (*external_reset)(void);\n\n\tbool use_eeprom;\n\n\tint num_leds;\n\tconst struct gpio_led *leds;\n\n\tunsigned num_btns;\n\tconst struct gpio_keys_button *btns;\n\tunsigned btn_poll_interval;\n};\n\n#endif /* _LINUX_ATH9K_PLATFORM_H */\n"
  },
  {
    "path": "target/linux/generic/files/include/linux/mtd/mtk_bmt.h",
    "content": "#ifndef __MTK_BMT_H\n#define __MTK_BMT_H\n\n#ifdef CONFIG_MTD_NAND_MTK_BMT\nint mtk_bmt_attach(struct mtd_info *mtd);\nvoid mtk_bmt_detach(struct mtd_info *mtd);\n#else\nstatic inline int mtk_bmt_attach(struct mtd_info *mtd)\n{\n\treturn 0;\n}\n\nstatic inline void mtk_bmt_detach(struct mtd_info *mtd)\n{\n}\n#endif\n\n#endif\n"
  },
  {
    "path": "target/linux/generic/files/include/linux/myloader.h",
    "content": "/*\n *  Compex's MyLoader specific definitions\n *\n *  Copyright (C) 2006-2008 Gabor Juhos <juhosg@openwrt.org>\n *\n *  This program is free software; you can redistribute it and/or modify it\n *  under the terms of the GNU General Public License version 2 as published\n *  by the Free Software Foundation.\n *\n */\n\n#ifndef _MYLOADER_H_\n#define _MYLOADER_H_\n\n/* Myloader specific magic numbers */\n#define MYLO_MAGIC_SYS_PARAMS\t0x20021107\n#define MYLO_MAGIC_PARTITIONS\t0x20021103\n#define MYLO_MAGIC_BOARD_PARAMS\t0x20021103\n\n/* Vendor ID's (seems to be same as the PCI vendor ID's) */\n#define VENID_COMPEX\t\t0x11F6\n\n/* Devices based on the ADM5120 */\n#define DEVID_COMPEX_NP27G\t0x0078\n#define DEVID_COMPEX_NP28G\t0x044C\n#define DEVID_COMPEX_NP28GHS\t0x044E\n#define DEVID_COMPEX_WP54Gv1C\t0x0514\n#define DEVID_COMPEX_WP54G\t0x0515\n#define DEVID_COMPEX_WP54AG\t0x0546\n#define DEVID_COMPEX_WPP54AG\t0x0550\n#define DEVID_COMPEX_WPP54G\t0x0555\n\n/* Devices based on the Atheros AR2317 */\n#define DEVID_COMPEX_NP25G\t0x05E6\n#define DEVID_COMPEX_WPE53G\t0x05DC\n\n/* Devices based on the Atheros AR71xx */\n#define DEVID_COMPEX_WP543\t0x0640\n#define DEVID_COMPEX_WPE72\t0x0672\n\n/* Devices based on the IXP422 */\n#define DEVID_COMPEX_WP18\t0x047E\n#define DEVID_COMPEX_NP18A\t0x0489\n\n/* Other devices */\n#define DEVID_COMPEX_NP26G8M\t0x03E8\n#define DEVID_COMPEX_NP26G16M\t0x03E9\n\nstruct mylo_partition {\n\tuint16_t\tflags;\t/* partition flags */\n\tuint16_t\ttype;\t/* type of the partition */\n\tuint32_t\taddr;\t/* relative address of the partition from the\n\t\t\t\t   flash start */\n\tuint32_t\tsize;\t/* size of the partition in bytes */\n\tuint32_t\tparam;\t/* if this is the active partition, the\n\t\t\t\t   MyLoader load code to this address */\n};\n\n#define PARTITION_FLAG_ACTIVE\t0x8000 /* this is the active partition,\n\t\t\t\t\t* MyLoader loads firmware from here */\n#define PARTITION_FLAG_ISRAM\t0x2000 /* FIXME: this is a RAM partition? */\n#define PARTIIION_FLAG_RAMLOAD\t0x1000 /* FIXME: load this partition into the RAM? */\n#define PARTITION_FLAG_PRELOAD\t0x0800 /* the partition data preloaded to RAM\n\t\t\t\t\t* before decompression */\n#define PARTITION_FLAG_LZMA\t0x0100 /* partition data compressed by LZMA */\n#define PARTITION_FLAG_HAVEHDR  0x0002 /* the partition data have a header */\n\n#define PARTITION_TYPE_FREE\t0\n#define PARTITION_TYPE_USED\t1\n\n#define MYLO_MAX_PARTITIONS\t8\t/* maximum number of partitions in the\n\t\t\t\t\t   partition table */\n\nstruct mylo_partition_table {\n\tuint32_t\tmagic;\t\t/* must be MYLO_MAGIC_PARTITIONS */\n\tuint32_t\tres0;\t\t/* unknown/unused */\n\tuint32_t\tres1;\t\t/* unknown/unused */\n\tuint32_t \tres2;\t\t/* unknown/unused */\n\tstruct mylo_partition partitions[MYLO_MAX_PARTITIONS];\n};\n\nstruct mylo_partition_header {\n\tuint32_t\tlen;\t\t/* length of the partition data */\n\tuint32_t\tcrc;\t\t/* CRC value of the partition data */\n};\n\nstruct mylo_system_params {\n\tuint32_t\tmagic;\t\t/* must be MYLO_MAGIC_SYS_PARAMS */\n\tuint32_t\tres0;\n\tuint32_t\tres1;\n\tuint32_t\tmylo_ver;\n\tuint16_t\tvid;\t\t/* Vendor ID */\n\tuint16_t\tdid;\t\t/* Device ID */\n\tuint16_t\tsvid;\t\t/* Sub Vendor ID */\n\tuint16_t\tsdid;\t\t/* Sub Device ID */\n\tuint32_t\trev;\t\t/* device revision */\n\tuint32_t\tfwhi;\n\tuint32_t\tfwlo;\n\tuint32_t\ttftp_addr;\n\tuint32_t\tprog_start;\n\tuint32_t\tflash_size;\t/* size of boot FLASH in bytes */\n\tuint32_t\tdram_size;\t/* size of onboard RAM in bytes */\n};\n\nstruct mylo_eth_addr {\n\tuint8_t\tmac[6];\n\tuint8_t\tcsum[2];\n};\n\n#define MYLO_ETHADDR_COUNT\t8\t/* maximum number of ethernet address\n\t\t\t\t\t   in the board parameters */\n\nstruct mylo_board_params {\n\tuint32_t\tmagic;\t/* must be MYLO_MAGIC_BOARD_PARAMS */\n\tuint32_t\tres0;\n\tuint32_t\tres1;\n\tuint32_t\tres2;\n\tstruct mylo_eth_addr addr[MYLO_ETHADDR_COUNT];\n};\n\n#endif /* _MYLOADER_H_*/\n"
  },
  {
    "path": "target/linux/generic/files/include/linux/platform_data/adm6996-gpio.h",
    "content": "/*\n * ADM6996 GPIO platform data\n *\n * Copyright (C) 2013 Hauke Mehrtens <hauke@hauke-m.de>\n *\n * This program is free software; you can redistribute  it and/or modify it\n * under  the terms of the GNU General Public License v2 as published by the\n * Free Software Foundation\n */\n\n#ifndef __PLATFORM_ADM6996_GPIO_H\n#define __PLATFORM_ADM6996_GPIO_H\n\n#include <linux/kernel.h>\n\nenum adm6996_model {\n\tADM6996FC = 1,\n\tADM6996M = 2,\n\tADM6996L = 3,\n};\n\nstruct adm6996_gpio_platform_data {\n\tu8 eecs;\n\tu8 eesk;\n\tu8 eedi;\n\tenum adm6996_model model;\n};\n\n#endif\n"
  },
  {
    "path": "target/linux/generic/files/include/linux/routerboot.h",
    "content": "/*\n *  Mikrotik's RouterBOOT definitions\n *\n *  Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>\n *\n *  This program is free software; you can redistribute it and/or modify it\n *  under the terms of the GNU General Public License version 2 as published\n *  by the Free Software Foundation.\n *\n */\n\n#ifndef _ROUTERBOOT_H\n#define _ROUTERBOOT_H\n\n#define RB_MAC_SIZE\t\t6\n\n/*\n * Magic numbers\n */\n#define RB_MAGIC_HARD\t0x64726148 /* \"Hard\" */\n#define RB_MAGIC_SOFT\t0x74666F53 /* \"Soft\" */\n#define RB_MAGIC_DAWN\t0x6E776144 /* \"Dawn\" */\n\n#define RB_ID_TERMINATOR\t0\n\n/*\n * ID values for Hardware settings\n */\n#define RB_ID_HARD_01\t\t1\n#define RB_ID_HARD_02\t\t2\n#define RB_ID_FLASH_INFO\t3\n#define RB_ID_MAC_ADDRESS_PACK\t4\n#define RB_ID_BOARD_NAME\t5\n#define RB_ID_BIOS_VERSION\t6\n#define RB_ID_HARD_07\t\t7\n#define RB_ID_SDRAM_TIMINGS\t8\n#define RB_ID_DEVICE_TIMINGS\t9\n#define RB_ID_SOFTWARE_ID\t10\n#define RB_ID_SERIAL_NUMBER\t11\n#define RB_ID_HARD_12\t\t12\n#define RB_ID_MEMORY_SIZE\t13\n#define RB_ID_MAC_ADDRESS_COUNT\t14\n#define RB_ID_HW_OPTIONS\t21\n#define RB_ID_WLAN_DATA\t\t22\n\n/*\n * ID values for Software settings\n */\n#define RB_ID_UART_SPEED\t1\n#define RB_ID_BOOT_DELAY\t2\n#define RB_ID_BOOT_DEVICE\t3\n#define RB_ID_BOOT_KEY\t\t4\n#define RB_ID_CPU_MODE\t\t5\n#define RB_ID_FW_VERSION\t6\n#define RB_ID_SOFT_07\t\t7\n#define RB_ID_SOFT_08\t\t8\n#define RB_ID_BOOT_PROTOCOL\t9\n#define RB_ID_SOFT_10\t\t10\n#define RB_ID_SOFT_11\t\t11\n\n/*\n * UART_SPEED values\n */\n#define RB_UART_SPEED_115200\t0\n#define RB_UART_SPEED_57600\t1\n#define RB_UART_SPEED_38400\t2\n#define RB_UART_SPEED_19200\t3\n#define RB_UART_SPEED_9600\t4\n#define RB_UART_SPEED_4800\t5\n#define RB_UART_SPEED_2400\t6\n#define RB_UART_SPEED_1200\t7\n\n/*\n * BOOT_DELAY values\n */\n#define RB_BOOT_DELAY_0SEC\t0\n#define RB_BOOT_DELAY_1SEC\t1\n#define RB_BOOT_DELAY_2SEC\t2\n\n/*\n * BOOT_DEVICE values\n */\n#define RB_BOOT_DEVICE_ETHER\t0\n#define RB_BOOT_DEVICE_NANDETH\t1\n#define RB_BOOT_DEVICE_ETHONCE\t2\n#define RB_BOOT_DEVICE_NANDONLY\t3\n\n/*\n * BOOT_KEY values\n */\n#define RB_BOOT_KEY_ANY\t\t0\n#define RB_BOOT_KEY_DEL\t\t1\n\n/*\n * CPU_MODE values\n */\n#define RB_CPU_MODE_POWERSAVE\t0\n#define RB_CPU_MODE_REGULAR\t1\n\n/*\n * BOOT_PROTOCOL values\n */\n#define RB_BOOT_PROTOCOL_BOOTP\t0\n#define RB_BOOT_PROTOCOL_DHCP\t1\n\n#endif /* _ROUTERBOOT_H */\n"
  },
  {
    "path": "target/linux/generic/files/include/linux/rt2x00_platform.h",
    "content": "/*\n * Platform data definition for the rt2x00 driver\n *\n * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of the GNU General Public License version 2 as published\n * by the Free Software Foundation.\n *\n */\n\n#ifndef _RT2X00_PLATFORM_H\n#define _RT2X00_PLATFORM_H\n\nstruct rt2x00_platform_data {\n\tchar *eeprom_file_name;\n\tconst u8 *mac_address;\n\n\tint disable_2ghz;\n\tint disable_5ghz;\n};\n\n#endif /* _RT2X00_PLATFORM_H */\n"
  },
  {
    "path": "target/linux/generic/files/include/linux/rtl8366.h",
    "content": "/*\n * Platform data definition for the Realtek RTL8366RB/S ethernet switch driver\n *\n * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of the GNU General Public License version 2 as published\n * by the Free Software Foundation.\n */\n\n#ifndef _RTL8366_H\n#define _RTL8366_H\n\n#define RTL8366_DRIVER_NAME\t\"rtl8366\"\n#define RTL8366S_DRIVER_NAME\t\"rtl8366s\"\n#define RTL8366RB_DRIVER_NAME\t\"rtl8366rb\"\n\nstruct rtl8366_smi;\n\nenum rtl8366_type {\n\tRTL8366_TYPE_UNKNOWN,\n\tRTL8366_TYPE_S,\n\tRTL8366_TYPE_RB,\n};\n\nstruct rtl8366_initval {\n\tunsigned\treg;\n\tu16\t\tval;\n};\n\nstruct rtl8366_platform_data {\n\tunsigned\tgpio_sda;\n\tunsigned\tgpio_sck;\n\tvoid\t\t(*hw_reset)(struct rtl8366_smi *smi, bool active);\n\n\tunsigned\tnum_initvals;\n\tstruct rtl8366_initval *initvals;\n};\n\nenum rtl8366_type rtl8366_smi_detect(struct rtl8366_platform_data *pdata);\n\n#endif /*  _RTL8366_H */\n"
  },
  {
    "path": "target/linux/generic/files/include/linux/rtl8367.h",
    "content": "/*\n * Platform data definition for the Realtek RTL8367 ethernet switch driver\n *\n * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of the GNU General Public License version 2 as published\n * by the Free Software Foundation.\n */\n\n#ifndef _RTL8367_H\n#define _RTL8367_H\n\n#define RTL8367_DRIVER_NAME\t\"rtl8367\"\n#define RTL8367B_DRIVER_NAME\t\"rtl8367b\"\n\nenum rtl8367_port_speed {\n\tRTL8367_PORT_SPEED_10 = 0,\n\tRTL8367_PORT_SPEED_100,\n\tRTL8367_PORT_SPEED_1000,\n};\n\nstruct rtl8367_port_ability {\n\tint force_mode;\n\tint nway;\n\tint txpause;\n\tint rxpause;\n\tint link;\n\tint duplex;\n\tenum rtl8367_port_speed speed;\n};\n\nenum rtl8367_extif_mode {\n\tRTL8367_EXTIF_MODE_DISABLED = 0,\n\tRTL8367_EXTIF_MODE_RGMII,\n\tRTL8367_EXTIF_MODE_MII_MAC,\n\tRTL8367_EXTIF_MODE_MII_PHY,\n\tRTL8367_EXTIF_MODE_TMII_MAC,\n\tRTL8367_EXTIF_MODE_TMII_PHY,\n\tRTL8367_EXTIF_MODE_GMII,\n\tRTL8367_EXTIF_MODE_RGMII_33V,\n\tRTL8367B_EXTIF_MODE_RMII_MAC = 7,\n\tRTL8367B_EXTIF_MODE_RMII_PHY,\n\tRTL8367B_EXTIF_MODE_RGMII_33V,\n};\n\nstruct rtl8367_extif_config {\n\tunsigned int txdelay;\n\tunsigned int rxdelay;\n\tenum rtl8367_extif_mode mode;\n\tstruct rtl8367_port_ability ability;\n};\n\nstruct rtl8367_platform_data {\n\tunsigned gpio_sda;\n\tunsigned gpio_sck;\n\tvoid (*hw_reset)(bool active);\n\n\tstruct rtl8367_extif_config *extif0_cfg;\n\tstruct rtl8367_extif_config *extif1_cfg;\n};\n\n#endif /*  _RTL8367_H */\n"
  },
  {
    "path": "target/linux/generic/files/include/linux/switch.h",
    "content": "/*\n * switch.h: Switch configuration API\n *\n * Copyright (C) 2008 Felix Fietkau <nbd@nbd.name>\n *\n * This program is free software; you can redistribute it and/or\n * modify it under the terms of the GNU General Public License\n * as published by the Free Software Foundation; either version 2\n * of the License, or (at your option) any later version.\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n * GNU General Public License for more details.\n */\n#ifndef _LINUX_SWITCH_H\n#define _LINUX_SWITCH_H\n\n#include <net/genetlink.h>\n#include <uapi/linux/switch.h>\n\nstruct switch_dev;\nstruct switch_op;\nstruct switch_val;\nstruct switch_attr;\nstruct switch_attrlist;\nstruct switch_led_trigger;\n\nint register_switch(struct switch_dev *dev, struct net_device *netdev);\nvoid unregister_switch(struct switch_dev *dev);\n\n/**\n * struct switch_attrlist - attribute list\n *\n * @n_attr: number of attributes\n * @attr: pointer to the attributes array\n */\nstruct switch_attrlist {\n\tint n_attr;\n\tconst struct switch_attr *attr;\n};\n\nenum switch_port_speed {\n\tSWITCH_PORT_SPEED_UNKNOWN = 0,\n\tSWITCH_PORT_SPEED_10 = 10,\n\tSWITCH_PORT_SPEED_100 = 100,\n\tSWITCH_PORT_SPEED_1000 = 1000,\n};\n\nstruct switch_port_link {\n\tbool link;\n\tbool duplex;\n\tbool aneg;\n\tbool tx_flow;\n\tbool rx_flow;\n\tenum switch_port_speed speed;\n\t/* in ethtool adv_t format */\n\tu32 eee;\n};\n\nstruct switch_port_stats {\n\tunsigned long long tx_bytes;\n\tunsigned long long rx_bytes;\n};\n\n/**\n * struct switch_dev_ops - switch driver operations\n *\n * @attr_global: global switch attribute list\n * @attr_port: port attribute list\n * @attr_vlan: vlan attribute list\n *\n * Callbacks:\n *\n * @get_vlan_ports: read the port list of a VLAN\n * @set_vlan_ports: set the port list of a VLAN\n *\n * @get_port_pvid: get the primary VLAN ID of a port\n * @set_port_pvid: set the primary VLAN ID of a port\n *\n * @apply_config: apply all changed settings to the switch\n * @reset_switch: resetting the switch\n */\nstruct switch_dev_ops {\n\tstruct switch_attrlist attr_global, attr_port, attr_vlan;\n\n\tint (*get_vlan_ports)(struct switch_dev *dev, struct switch_val *val);\n\tint (*set_vlan_ports)(struct switch_dev *dev, struct switch_val *val);\n\n\tint (*get_port_pvid)(struct switch_dev *dev, int port, int *val);\n\tint (*set_port_pvid)(struct switch_dev *dev, int port, int val);\n\n\tint (*apply_config)(struct switch_dev *dev);\n\tint (*reset_switch)(struct switch_dev *dev);\n\n\tint (*get_port_link)(struct switch_dev *dev, int port,\n\t\t\t     struct switch_port_link *link);\n\tint (*set_port_link)(struct switch_dev *dev, int port,\n\t\t\t     struct switch_port_link *link);\n\tint (*get_port_stats)(struct switch_dev *dev, int port,\n\t\t\t      struct switch_port_stats *stats);\n\n\tint (*phy_read16)(struct switch_dev *dev, int addr, u8 reg, u16 *value);\n\tint (*phy_write16)(struct switch_dev *dev, int addr, u8 reg, u16 value);\n};\n\nstruct switch_dev {\n\tstruct device_node *of_node;\n\tconst struct switch_dev_ops *ops;\n\t/* will be automatically filled */\n\tchar devname[IFNAMSIZ];\n\n\tconst char *name;\n\t/* NB: either alias or netdev must be set */\n\tconst char *alias;\n\tstruct net_device *netdev;\n\n\tunsigned int ports;\n\tunsigned int vlans;\n\tunsigned int cpu_port;\n\n\t/* the following fields are internal for swconfig */\n\tunsigned int id;\n\tstruct list_head dev_list;\n\tunsigned long def_global, def_port, def_vlan;\n\n\tstruct mutex sw_mutex;\n\tstruct switch_port *portbuf;\n\tstruct switch_portmap *portmap;\n\tstruct switch_port_link linkbuf;\n\n\tchar buf[128];\n\n#ifdef CONFIG_SWCONFIG_LEDS\n\tstruct switch_led_trigger *led_trigger;\n#endif\n};\n\nstruct switch_port {\n\tu32 id;\n\tu32 flags;\n};\n\nstruct switch_portmap {\n\tu32 virt;\n\tconst char *s;\n};\n\nstruct switch_val {\n\tconst struct switch_attr *attr;\n\tunsigned int port_vlan;\n\tunsigned int len;\n\tunion {\n\t\tconst char *s;\n\t\tu32 i;\n\t\tstruct switch_port *ports;\n\t\tstruct switch_port_link *link;\n\t} value;\n};\n\nstruct switch_attr {\n\tint disabled;\n\tint type;\n\tconst char *name;\n\tconst char *description;\n\n\tint (*set)(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val);\n\tint (*get)(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val);\n\n\t/* for driver internal use */\n\tint id;\n\tint ofs;\n\tint max;\n};\n\nint switch_generic_set_link(struct switch_dev *dev, int port,\n\t\t\t    struct switch_port_link *link);\n\n#endif /* _LINUX_SWITCH_H */\n"
  },
  {
    "path": "target/linux/generic/files/include/uapi/linux/switch.h",
    "content": "/*\n * switch.h: Switch configuration API\n *\n * Copyright (C) 2008 Felix Fietkau <nbd@nbd.name>\n *\n * This program is free software; you can redistribute it and/or\n * modify it under the terms of the GNU General Public License\n * as published by the Free Software Foundation; either version 2\n * of the License, or (at your option) any later version.\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n * GNU General Public License for more details.\n */\n\n#ifndef _UAPI_LINUX_SWITCH_H\n#define _UAPI_LINUX_SWITCH_H\n\n#include <linux/types.h>\n#include <linux/netdevice.h>\n#include <linux/netlink.h>\n#include <linux/genetlink.h>\n#ifndef __KERNEL__\n#include <netlink/netlink.h>\n#include <netlink/genl/genl.h>\n#include <netlink/genl/ctrl.h>\n#endif\n\n/* main attributes */\nenum {\n\tSWITCH_ATTR_UNSPEC,\n\t/* global */\n\tSWITCH_ATTR_TYPE,\n\t/* device */\n\tSWITCH_ATTR_ID,\n\tSWITCH_ATTR_DEV_NAME,\n\tSWITCH_ATTR_ALIAS,\n\tSWITCH_ATTR_NAME,\n\tSWITCH_ATTR_VLANS,\n\tSWITCH_ATTR_PORTS,\n\tSWITCH_ATTR_PORTMAP,\n\tSWITCH_ATTR_CPU_PORT,\n\t/* attributes */\n\tSWITCH_ATTR_OP_ID,\n\tSWITCH_ATTR_OP_TYPE,\n\tSWITCH_ATTR_OP_NAME,\n\tSWITCH_ATTR_OP_PORT,\n\tSWITCH_ATTR_OP_VLAN,\n\tSWITCH_ATTR_OP_VALUE_INT,\n\tSWITCH_ATTR_OP_VALUE_STR,\n\tSWITCH_ATTR_OP_VALUE_PORTS,\n\tSWITCH_ATTR_OP_VALUE_LINK,\n\tSWITCH_ATTR_OP_DESCRIPTION,\n\t/* port lists */\n\tSWITCH_ATTR_PORT,\n\tSWITCH_ATTR_MAX\n};\n\nenum {\n\t/* port map */\n\tSWITCH_PORTMAP_PORTS,\n\tSWITCH_PORTMAP_SEGMENT,\n\tSWITCH_PORTMAP_VIRT,\n\tSWITCH_PORTMAP_MAX\n};\n\n/* commands */\nenum {\n\tSWITCH_CMD_UNSPEC,\n\tSWITCH_CMD_GET_SWITCH,\n\tSWITCH_CMD_NEW_ATTR,\n\tSWITCH_CMD_LIST_GLOBAL,\n\tSWITCH_CMD_GET_GLOBAL,\n\tSWITCH_CMD_SET_GLOBAL,\n\tSWITCH_CMD_LIST_PORT,\n\tSWITCH_CMD_GET_PORT,\n\tSWITCH_CMD_SET_PORT,\n\tSWITCH_CMD_LIST_VLAN,\n\tSWITCH_CMD_GET_VLAN,\n\tSWITCH_CMD_SET_VLAN\n};\n\n/* data types */\nenum switch_val_type {\n\tSWITCH_TYPE_UNSPEC,\n\tSWITCH_TYPE_INT,\n\tSWITCH_TYPE_STRING,\n\tSWITCH_TYPE_PORTS,\n\tSWITCH_TYPE_LINK,\n\tSWITCH_TYPE_NOVAL,\n};\n\n/* port nested attributes */\nenum {\n\tSWITCH_PORT_UNSPEC,\n\tSWITCH_PORT_ID,\n\tSWITCH_PORT_FLAG_TAGGED,\n\tSWITCH_PORT_ATTR_MAX\n};\n\n/* link nested attributes */\nenum {\n\tSWITCH_LINK_UNSPEC,\n\tSWITCH_LINK_FLAG_LINK,\n\tSWITCH_LINK_FLAG_DUPLEX,\n\tSWITCH_LINK_FLAG_ANEG,\n\tSWITCH_LINK_FLAG_TX_FLOW,\n\tSWITCH_LINK_FLAG_RX_FLOW,\n\tSWITCH_LINK_SPEED,\n\tSWITCH_LINK_FLAG_EEE_100BASET,\n\tSWITCH_LINK_FLAG_EEE_1000BASET,\n\tSWITCH_LINK_ATTR_MAX,\n};\n\n#define SWITCH_ATTR_DEFAULTS_OFFSET\t0x1000\n\n\n#endif /* _UAPI_LINUX_SWITCH_H */\n"
  },
  {
    "path": "target/linux/generic/hack-5.10/204-module_strip.patch",
    "content": "From a779a482fb9b9f8fcdf8b2519c789b4b9bb5dd05 Mon Sep 17 00:00:00 2001\nFrom: Felix Fietkau <nbd@nbd.name>\nDate: Fri, 7 Jul 2017 16:56:48 +0200\nSubject: build: add a hack for removing non-essential module info\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n include/linux/module.h      | 13 ++++++++-----\n include/linux/moduleparam.h | 15 ++++++++++++---\n init/Kconfig                |  7 +++++++\n kernel/module.c             |  5 ++++-\n scripts/mod/modpost.c       | 12 ++++++++++++\n 5 files changed, 43 insertions(+), 9 deletions(-)\n\n--- a/include/linux/module.h\n+++ b/include/linux/module.h\n@@ -161,6 +161,7 @@ extern void cleanup_module(void);\n \n /* Generic info of form tag = \"info\" */\n #define MODULE_INFO(tag, info) __MODULE_INFO(tag, tag, info)\n+#define MODULE_INFO_STRIP(tag, info) __MODULE_INFO_STRIP(tag, tag, info)\n \n /* For userspace: you can also call me... */\n #define MODULE_ALIAS(_alias) MODULE_INFO(alias, _alias)\n@@ -230,12 +231,12 @@ extern void cleanup_module(void);\n  * Author(s), use \"Name <email>\" or just \"Name\", for multiple\n  * authors use multiple MODULE_AUTHOR() statements/lines.\n  */\n-#define MODULE_AUTHOR(_author) MODULE_INFO(author, _author)\n+#define MODULE_AUTHOR(_author) MODULE_INFO_STRIP(author, _author)\n \n /* What your module does. */\n-#define MODULE_DESCRIPTION(_description) MODULE_INFO(description, _description)\n+#define MODULE_DESCRIPTION(_description) MODULE_INFO_STRIP(description, _description)\n \n-#ifdef MODULE\n+#if defined(MODULE) && !defined(CONFIG_MODULE_STRIPPED)\n /* Creates an alias so file2alias.c can find device table. */\n #define MODULE_DEVICE_TABLE(type, name)\t\t\t\t\t\\\n extern typeof(name) __mod_##type##__##name##_device_table\t\t\\\n@@ -262,7 +263,9 @@ extern typeof(name) __mod_##type##__##na\n  */\n \n #if defined(MODULE) || !defined(CONFIG_SYSFS)\n-#define MODULE_VERSION(_version) MODULE_INFO(version, _version)\n+#define MODULE_VERSION(_version) MODULE_INFO_STRIP(version, _version)\n+#elif defined(CONFIG_MODULE_STRIPPED)\n+#define MODULE_VERSION(_version) __MODULE_INFO_DISABLED(version)\n #else\n #define MODULE_VERSION(_version)\t\t\t\t\t\\\n \tMODULE_INFO(version, _version);\t\t\t\t\t\\\n@@ -285,7 +288,7 @@ extern typeof(name) __mod_##type##__##na\n /* Optional firmware file (or files) needed by the module\n  * format is simply firmware file name.  Multiple firmware\n  * files require multiple MODULE_FIRMWARE() specifiers */\n-#define MODULE_FIRMWARE(_firmware) MODULE_INFO(firmware, _firmware)\n+#define MODULE_FIRMWARE(_firmware) MODULE_INFO_STRIP(firmware, _firmware)\n \n #define MODULE_IMPORT_NS(ns) MODULE_INFO(import_ns, #ns)\n \n--- a/include/linux/moduleparam.h\n+++ b/include/linux/moduleparam.h\n@@ -20,6 +20,16 @@\n /* Chosen so that structs with an unsigned long line up. */\n #define MAX_PARAM_PREFIX_LEN (64 - sizeof(unsigned long))\n \n+/* This struct is here for syntactic coherency, it is not used */\n+#define __MODULE_INFO_DISABLED(name)\t\t\t\t\t  \\\n+  struct __UNIQUE_ID(name) {}\n+\n+#ifdef CONFIG_MODULE_STRIPPED\n+#define __MODULE_INFO_STRIP(tag, name, info) __MODULE_INFO_DISABLED(name)\n+#else\n+#define __MODULE_INFO_STRIP(tag, name, info) __MODULE_INFO(tag, name, info)\n+#endif\n+\n #define __MODULE_INFO(tag, name, info)\t\t\t\t\t  \\\n static const char __UNIQUE_ID(name)[]\t\t\t\t\t  \\\n   __used __section(\".modinfo\") __attribute__((unused, aligned(1)))\t  \\\n@@ -31,7 +41,7 @@ static const char __UNIQUE_ID(name)[]\n /* One for each parameter, describing how to use it.  Some files do\n    multiple of these per line, so can't just use MODULE_INFO. */\n #define MODULE_PARM_DESC(_parm, desc) \\\n-\t__MODULE_INFO(parm, _parm, #_parm \":\" desc)\n+\t__MODULE_INFO_STRIP(parm, _parm, #_parm \":\" desc)\n \n struct kernel_param;\n \n--- a/init/Kconfig\n+++ b/init/Kconfig\n@@ -2347,6 +2347,13 @@ config UNUSED_KSYMS_WHITELIST\n \t  one per line. The path can be absolute, or relative to the kernel\n \t  source tree.\n \n+config MODULE_STRIPPED\n+\tbool \"Reduce module size\"\n+\tdepends on MODULES\n+\thelp\n+\t  Remove module parameter descriptions, author info, version, aliases,\n+\t  device tables, etc.\n+\n endif # MODULES\n \n config MODULES_TREE_LOOKUP\n--- a/kernel/module.c\n+++ b/kernel/module.c\n@@ -1285,6 +1285,7 @@ static struct module_attribute *modinfo_\n \n static const char vermagic[] = VERMAGIC_STRING;\n \n+#if defined(CONFIG_MODVERSIONS) || !defined(CONFIG_MODULE_STRIPPED)\n static int try_to_force_load(struct module *mod, const char *reason)\n {\n #ifdef CONFIG_MODULE_FORCE_LOAD\n@@ -1296,6 +1297,7 @@ static int try_to_force_load(struct modu\n \treturn -ENOEXEC;\n #endif\n }\n+#endif\n \n #ifdef CONFIG_MODVERSIONS\n \n@@ -3247,9 +3249,11 @@ static int setup_load_info(struct load_i\n \n static int check_modinfo(struct module *mod, struct load_info *info, int flags)\n {\n-\tconst char *modmagic = get_modinfo(info, \"vermagic\");\n \tint err;\n \n+#ifndef CONFIG_MODULE_STRIPPED\n+\tconst char *modmagic = get_modinfo(info, \"vermagic\");\n+\n \tif (flags & MODULE_INIT_IGNORE_VERMAGIC)\n \t\tmodmagic = NULL;\n \n@@ -3270,6 +3274,7 @@ static int check_modinfo(struct module *\n \t\t\t\tmod->name);\n \t\tadd_taint_module(mod, TAINT_OOT_MODULE, LOCKDEP_STILL_OK);\n \t}\n+#endif\n \n \tcheck_modinfo_retpoline(mod, info);\n \n--- a/scripts/mod/modpost.c\n+++ b/scripts/mod/modpost.c\n@@ -2037,7 +2037,9 @@ static void read_symbols(const char *mod\n \t\tsymname = remove_dot(info.strtab + sym->st_name);\n \n \t\thandle_symbol(mod, &info, sym, symname);\n+#ifndef CONFIG_MODULE_STRIPPED\n \t\thandle_moddevtable(mod, &info, sym, symname);\n+#endif\n \t}\n \n \tfor (sym = info.symtab_start; sym < info.symtab_stop; sym++) {\n@@ -2250,8 +2252,10 @@ static void add_header(struct buffer *b,\n \tbuf_printf(b, \"\\n\");\n \tbuf_printf(b, \"BUILD_SALT;\\n\");\n \tbuf_printf(b, \"\\n\");\n+#ifndef CONFIG_MODULE_STRIPPED\n \tbuf_printf(b, \"MODULE_INFO(vermagic, VERMAGIC_STRING);\\n\");\n \tbuf_printf(b, \"MODULE_INFO(name, KBUILD_MODNAME);\\n\");\n+#endif\n \tbuf_printf(b, \"\\n\");\n \tbuf_printf(b, \"__visible struct module __this_module\\n\");\n \tbuf_printf(b, \"__section(\\\".gnu.linkonce.this_module\\\") = {\\n\");\n@@ -2268,8 +2272,10 @@ static void add_header(struct buffer *b,\n \n static void add_intree_flag(struct buffer *b, int is_intree)\n {\n+#ifndef CONFIG_MODULE_STRIPPED\n \tif (is_intree)\n \t\tbuf_printf(b, \"\\nMODULE_INFO(intree, \\\"Y\\\");\\n\");\n+#endif\n }\n \n /* Cannot check for assembler */\n@@ -2282,8 +2288,10 @@ static void add_retpoline(struct buffer\n \n static void add_staging_flag(struct buffer *b, const char *name)\n {\n+#ifndef CONFIG_MODULE_STRIPPED\n \tif (strstarts(name, \"drivers/staging\"))\n \t\tbuf_printf(b, \"\\nMODULE_INFO(staging, \\\"Y\\\");\\n\");\n+#endif\n }\n \n /**\n@@ -2367,11 +2375,13 @@ static void add_depends(struct buffer *b\n \n static void add_srcversion(struct buffer *b, struct module *mod)\n {\n+#ifndef CONFIG_MODULE_STRIPPED\n \tif (mod->srcversion[0]) {\n \t\tbuf_printf(b, \"\\n\");\n \t\tbuf_printf(b, \"MODULE_INFO(srcversion, \\\"%s\\\");\\n\",\n \t\t\t   mod->srcversion);\n \t}\n+#endif\n }\n \n static void write_buf(struct buffer *b, const char *fname)\n@@ -2630,7 +2640,9 @@ int main(int argc, char **argv)\n \t\tadd_staging_flag(&buf, mod->name);\n \t\terr |= add_versions(&buf, mod);\n \t\tadd_depends(&buf, mod);\n+#ifndef CONFIG_MODULE_STRIPPED\n \t\tadd_moddevtable(&buf, mod);\n+#endif\n \t\tadd_srcversion(&buf, mod);\n \n \t\tsprintf(fname, \"%s.mod.c\", mod->name);\n"
  },
  {
    "path": "target/linux/generic/hack-5.10/205-kconfig-exit.patch",
    "content": "--- a/scripts/kconfig/conf.c\n+++ b/scripts/kconfig/conf.c\n@@ -215,6 +215,8 @@ static int conf_sym(struct menu *menu)\n \t\t\t\tbreak;\n \t\t\tcontinue;\n \t\tcase 0:\n+\t\t\tif (!sym_has_value(sym) && !tty_stdio && getenv(\"FAIL_ON_UNCONFIGURED\"))\n+\t\t\t\texit(1);\n \t\t\tnewval = oldval;\n \t\t\tbreak;\n \t\tcase '?':\n"
  },
  {
    "path": "target/linux/generic/hack-5.10/210-darwin_scripts_include.patch",
    "content": "From db7c30dcd9a0391bf13b62c9f91e144d762ef43a Mon Sep 17 00:00:00 2001\nFrom: Florian Fainelli <f.fainelli@gmail.com>\nDate: Fri, 7 Jul 2017 17:00:49 +0200\nSubject: Add an OSX specific patch to make the kernel be compiled\n\nlede-commit: 3fc2a24f0422b2f55f9ed43f116db3111f700526\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n scripts/kconfig/Makefile   |    3 +\n scripts/mod/elf.h          | 3007 ++++++++++++++++++++++++++++++++++++++++++++\n scripts/mod/mk_elfconfig.c |    4 +\n scripts/mod/modpost.h      |    4 +\n 4 files changed, 3018 insertions(+)\n create mode 100644 scripts/mod/elf.h\n\n--- /dev/null\n+++ b/scripts/mod/elf.h\n@@ -0,0 +1,3007 @@\n+/* This file defines standard ELF types, structures, and macros.\n+   Copyright (C) 1995-2012 Free Software Foundation, Inc.\n+   This file is part of the GNU C Library.\n+\n+   The GNU C Library is free software; you can redistribute it and/or\n+   modify it under the terms of the GNU Lesser General Public\n+   License as published by the Free Software Foundation; either\n+   version 2.1 of the License, or (at your option) any later version.\n+\n+   The GNU C Library is distributed in the hope that it will be useful,\n+   but WITHOUT ANY WARRANTY; without even the implied warranty of\n+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\n+   Lesser General Public License for more details.\n+\n+   You should have received a copy of the GNU Lesser General Public\n+   License along with the GNU C Library; if not, see\n+   <http://www.gnu.org/licenses/>.  */\n+\n+#ifndef _ELF_H\n+#define\t_ELF_H 1\n+\n+/* Standard ELF types.  */\n+\n+#include <stdint.h>\n+\n+/* Type for a 16-bit quantity.  */\n+typedef uint16_t Elf32_Half;\n+typedef uint16_t Elf64_Half;\n+\n+/* Types for signed and unsigned 32-bit quantities.  */\n+typedef uint32_t Elf32_Word;\n+typedef\tint32_t  Elf32_Sword;\n+typedef uint32_t Elf64_Word;\n+typedef\tint32_t  Elf64_Sword;\n+\n+/* Types for signed and unsigned 64-bit quantities.  */\n+typedef uint64_t Elf32_Xword;\n+typedef\tint64_t  Elf32_Sxword;\n+typedef uint64_t Elf64_Xword;\n+typedef\tint64_t  Elf64_Sxword;\n+\n+/* Type of addresses.  */\n+typedef uint32_t Elf32_Addr;\n+typedef uint64_t Elf64_Addr;\n+\n+/* Type of file offsets.  */\n+typedef uint32_t Elf32_Off;\n+typedef uint64_t Elf64_Off;\n+\n+/* Type for section indices, which are 16-bit quantities.  */\n+typedef uint16_t Elf32_Section;\n+typedef uint16_t Elf64_Section;\n+\n+/* Type for version symbol information.  */\n+typedef Elf32_Half Elf32_Versym;\n+typedef Elf64_Half Elf64_Versym;\n+\n+\n+/* The ELF file header.  This appears at the start of every ELF file.  */\n+\n+#define EI_NIDENT (16)\n+\n+typedef struct\n+{\n+  unsigned char\te_ident[EI_NIDENT];\t/* Magic number and other info */\n+  Elf32_Half\te_type;\t\t\t/* Object file type */\n+  Elf32_Half\te_machine;\t\t/* Architecture */\n+  Elf32_Word\te_version;\t\t/* Object file version */\n+  Elf32_Addr\te_entry;\t\t/* Entry point virtual address */\n+  Elf32_Off\te_phoff;\t\t/* Program header table file offset */\n+  Elf32_Off\te_shoff;\t\t/* Section header table file offset */\n+  Elf32_Word\te_flags;\t\t/* Processor-specific flags */\n+  Elf32_Half\te_ehsize;\t\t/* ELF header size in bytes */\n+  Elf32_Half\te_phentsize;\t\t/* Program header table entry size */\n+  Elf32_Half\te_phnum;\t\t/* Program header table entry count */\n+  Elf32_Half\te_shentsize;\t\t/* Section header table entry size */\n+  Elf32_Half\te_shnum;\t\t/* Section header table entry count */\n+  Elf32_Half\te_shstrndx;\t\t/* Section header string table index */\n+} Elf32_Ehdr;\n+\n+typedef struct\n+{\n+  unsigned char\te_ident[EI_NIDENT];\t/* Magic number and other info */\n+  Elf64_Half\te_type;\t\t\t/* Object file type */\n+  Elf64_Half\te_machine;\t\t/* Architecture */\n+  Elf64_Word\te_version;\t\t/* Object file version */\n+  Elf64_Addr\te_entry;\t\t/* Entry point virtual address */\n+  Elf64_Off\te_phoff;\t\t/* Program header table file offset */\n+  Elf64_Off\te_shoff;\t\t/* Section header table file offset */\n+  Elf64_Word\te_flags;\t\t/* Processor-specific flags */\n+  Elf64_Half\te_ehsize;\t\t/* ELF header size in bytes */\n+  Elf64_Half\te_phentsize;\t\t/* Program header table entry size */\n+  Elf64_Half\te_phnum;\t\t/* Program header table entry count */\n+  Elf64_Half\te_shentsize;\t\t/* Section header table entry size */\n+  Elf64_Half\te_shnum;\t\t/* Section header table entry count */\n+  Elf64_Half\te_shstrndx;\t\t/* Section header string table index */\n+} Elf64_Ehdr;\n+\n+/* Fields in the e_ident array.  The EI_* macros are indices into the\n+   array.  The macros under each EI_* macro are the values the byte\n+   may have.  */\n+\n+#define EI_MAG0\t\t0\t\t/* File identification byte 0 index */\n+#define ELFMAG0\t\t0x7f\t\t/* Magic number byte 0 */\n+\n+#define EI_MAG1\t\t1\t\t/* File identification byte 1 index */\n+#define ELFMAG1\t\t'E'\t\t/* Magic number byte 1 */\n+\n+#define EI_MAG2\t\t2\t\t/* File identification byte 2 index */\n+#define ELFMAG2\t\t'L'\t\t/* Magic number byte 2 */\n+\n+#define EI_MAG3\t\t3\t\t/* File identification byte 3 index */\n+#define ELFMAG3\t\t'F'\t\t/* Magic number byte 3 */\n+\n+/* Conglomeration of the identification bytes, for easy testing as a word.  */\n+#define\tELFMAG\t\t\"\\177ELF\"\n+#define\tSELFMAG\t\t4\n+\n+#define EI_CLASS\t4\t\t/* File class byte index */\n+#define ELFCLASSNONE\t0\t\t/* Invalid class */\n+#define ELFCLASS32\t1\t\t/* 32-bit objects */\n+#define ELFCLASS64\t2\t\t/* 64-bit objects */\n+#define ELFCLASSNUM\t3\n+\n+#define EI_DATA\t\t5\t\t/* Data encoding byte index */\n+#define ELFDATANONE\t0\t\t/* Invalid data encoding */\n+#define ELFDATA2LSB\t1\t\t/* 2's complement, little endian */\n+#define ELFDATA2MSB\t2\t\t/* 2's complement, big endian */\n+#define ELFDATANUM\t3\n+\n+#define EI_VERSION\t6\t\t/* File version byte index */\n+\t\t\t\t\t/* Value must be EV_CURRENT */\n+\n+#define EI_OSABI\t7\t\t/* OS ABI identification */\n+#define ELFOSABI_NONE\t\t0\t/* UNIX System V ABI */\n+#define ELFOSABI_SYSV\t\t0\t/* Alias.  */\n+#define ELFOSABI_HPUX\t\t1\t/* HP-UX */\n+#define ELFOSABI_NETBSD\t\t2\t/* NetBSD.  */\n+#define ELFOSABI_GNU\t\t3\t/* Object uses GNU ELF extensions.  */\n+#define ELFOSABI_LINUX\t\tELFOSABI_GNU /* Compatibility alias.  */\n+#define ELFOSABI_SOLARIS\t6\t/* Sun Solaris.  */\n+#define ELFOSABI_AIX\t\t7\t/* IBM AIX.  */\n+#define ELFOSABI_IRIX\t\t8\t/* SGI Irix.  */\n+#define ELFOSABI_FREEBSD\t9\t/* FreeBSD.  */\n+#define ELFOSABI_TRU64\t\t10\t/* Compaq TRU64 UNIX.  */\n+#define ELFOSABI_MODESTO\t11\t/* Novell Modesto.  */\n+#define ELFOSABI_OPENBSD\t12\t/* OpenBSD.  */\n+#define ELFOSABI_ARM_AEABI\t64\t/* ARM EABI */\n+#define ELFOSABI_ARM\t\t97\t/* ARM */\n+#define ELFOSABI_STANDALONE\t255\t/* Standalone (embedded) application */\n+\n+#define EI_ABIVERSION\t8\t\t/* ABI version */\n+\n+#define EI_PAD\t\t9\t\t/* Byte index of padding bytes */\n+\n+/* Legal values for e_type (object file type).  */\n+\n+#define ET_NONE\t\t0\t\t/* No file type */\n+#define ET_REL\t\t1\t\t/* Relocatable file */\n+#define ET_EXEC\t\t2\t\t/* Executable file */\n+#define ET_DYN\t\t3\t\t/* Shared object file */\n+#define ET_CORE\t\t4\t\t/* Core file */\n+#define\tET_NUM\t\t5\t\t/* Number of defined types */\n+#define ET_LOOS\t\t0xfe00\t\t/* OS-specific range start */\n+#define ET_HIOS\t\t0xfeff\t\t/* OS-specific range end */\n+#define ET_LOPROC\t0xff00\t\t/* Processor-specific range start */\n+#define ET_HIPROC\t0xffff\t\t/* Processor-specific range end */\n+\n+/* Legal values for e_machine (architecture).  */\n+\n+#define EM_NONE\t\t 0\t\t/* No machine */\n+#define EM_M32\t\t 1\t\t/* AT&T WE 32100 */\n+#define EM_SPARC\t 2\t\t/* SUN SPARC */\n+#define EM_386\t\t 3\t\t/* Intel 80386 */\n+#define EM_68K\t\t 4\t\t/* Motorola m68k family */\n+#define EM_88K\t\t 5\t\t/* Motorola m88k family */\n+#define EM_860\t\t 7\t\t/* Intel 80860 */\n+#define EM_MIPS\t\t 8\t\t/* MIPS R3000 big-endian */\n+#define EM_S370\t\t 9\t\t/* IBM System/370 */\n+#define EM_MIPS_RS3_LE\t10\t\t/* MIPS R3000 little-endian */\n+\n+#define EM_PARISC\t15\t\t/* HPPA */\n+#define EM_VPP500\t17\t\t/* Fujitsu VPP500 */\n+#define EM_SPARC32PLUS\t18\t\t/* Sun's \"v8plus\" */\n+#define EM_960\t\t19\t\t/* Intel 80960 */\n+#define EM_PPC\t\t20\t\t/* PowerPC */\n+#define EM_PPC64\t21\t\t/* PowerPC 64-bit */\n+#define EM_S390\t\t22\t\t/* IBM S390 */\n+\n+#define EM_V800\t\t36\t\t/* NEC V800 series */\n+#define EM_FR20\t\t37\t\t/* Fujitsu FR20 */\n+#define EM_RH32\t\t38\t\t/* TRW RH-32 */\n+#define EM_RCE\t\t39\t\t/* Motorola RCE */\n+#define EM_ARM\t\t40\t\t/* ARM */\n+#define EM_FAKE_ALPHA\t41\t\t/* Digital Alpha */\n+#define EM_SH\t\t42\t\t/* Hitachi SH */\n+#define EM_SPARCV9\t43\t\t/* SPARC v9 64-bit */\n+#define EM_TRICORE\t44\t\t/* Siemens Tricore */\n+#define EM_ARC\t\t45\t\t/* Argonaut RISC Core */\n+#define EM_H8_300\t46\t\t/* Hitachi H8/300 */\n+#define EM_H8_300H\t47\t\t/* Hitachi H8/300H */\n+#define EM_H8S\t\t48\t\t/* Hitachi H8S */\n+#define EM_H8_500\t49\t\t/* Hitachi H8/500 */\n+#define EM_IA_64\t50\t\t/* Intel Merced */\n+#define EM_MIPS_X\t51\t\t/* Stanford MIPS-X */\n+#define EM_COLDFIRE\t52\t\t/* Motorola Coldfire */\n+#define EM_68HC12\t53\t\t/* Motorola M68HC12 */\n+#define EM_MMA\t\t54\t\t/* Fujitsu MMA Multimedia Accelerator*/\n+#define EM_PCP\t\t55\t\t/* Siemens PCP */\n+#define EM_NCPU\t\t56\t\t/* Sony nCPU embeeded RISC */\n+#define EM_NDR1\t\t57\t\t/* Denso NDR1 microprocessor */\n+#define EM_STARCORE\t58\t\t/* Motorola Start*Core processor */\n+#define EM_ME16\t\t59\t\t/* Toyota ME16 processor */\n+#define EM_ST100\t60\t\t/* STMicroelectronic ST100 processor */\n+#define EM_TINYJ\t61\t\t/* Advanced Logic Corp. Tinyj emb.fam*/\n+#define EM_X86_64\t62\t\t/* AMD x86-64 architecture */\n+#define EM_PDSP\t\t63\t\t/* Sony DSP Processor */\n+\n+#define EM_FX66\t\t66\t\t/* Siemens FX66 microcontroller */\n+#define EM_ST9PLUS\t67\t\t/* STMicroelectronics ST9+ 8/16 mc */\n+#define EM_ST7\t\t68\t\t/* STmicroelectronics ST7 8 bit mc */\n+#define EM_68HC16\t69\t\t/* Motorola MC68HC16 microcontroller */\n+#define EM_68HC11\t70\t\t/* Motorola MC68HC11 microcontroller */\n+#define EM_68HC08\t71\t\t/* Motorola MC68HC08 microcontroller */\n+#define EM_68HC05\t72\t\t/* Motorola MC68HC05 microcontroller */\n+#define EM_SVX\t\t73\t\t/* Silicon Graphics SVx */\n+#define EM_ST19\t\t74\t\t/* STMicroelectronics ST19 8 bit mc */\n+#define EM_VAX\t\t75\t\t/* Digital VAX */\n+#define EM_CRIS\t\t76\t\t/* Axis Communications 32-bit embedded processor */\n+#define EM_JAVELIN\t77\t\t/* Infineon Technologies 32-bit embedded processor */\n+#define EM_FIREPATH\t78\t\t/* Element 14 64-bit DSP Processor */\n+#define EM_ZSP\t\t79\t\t/* LSI Logic 16-bit DSP Processor */\n+#define EM_MMIX\t\t80\t\t/* Donald Knuth's educational 64-bit processor */\n+#define EM_HUANY\t81\t\t/* Harvard University machine-independent object files */\n+#define EM_PRISM\t82\t\t/* SiTera Prism */\n+#define EM_AVR\t\t83\t\t/* Atmel AVR 8-bit microcontroller */\n+#define EM_FR30\t\t84\t\t/* Fujitsu FR30 */\n+#define EM_D10V\t\t85\t\t/* Mitsubishi D10V */\n+#define EM_D30V\t\t86\t\t/* Mitsubishi D30V */\n+#define EM_V850\t\t87\t\t/* NEC v850 */\n+#define EM_M32R\t\t88\t\t/* Mitsubishi M32R */\n+#define EM_MN10300\t89\t\t/* Matsushita MN10300 */\n+#define EM_MN10200\t90\t\t/* Matsushita MN10200 */\n+#define EM_PJ\t\t91\t\t/* picoJava */\n+#define EM_OPENRISC\t92\t\t/* OpenRISC 32-bit embedded processor */\n+#define EM_ARC_A5\t93\t\t/* ARC Cores Tangent-A5 */\n+#define EM_XTENSA\t94\t\t/* Tensilica Xtensa Architecture */\n+#define EM_TILEPRO\t188\t\t/* Tilera TILEPro */\n+#define EM_TILEGX\t191\t\t/* Tilera TILE-Gx */\n+#define EM_NUM\t\t192\n+\n+/* If it is necessary to assign new unofficial EM_* values, please\n+   pick large random numbers (0x8523, 0xa7f2, etc.) to minimize the\n+   chances of collision with official or non-GNU unofficial values.  */\n+\n+#define EM_ALPHA\t0x9026\n+\n+/* Legal values for e_version (version).  */\n+\n+#define EV_NONE\t\t0\t\t/* Invalid ELF version */\n+#define EV_CURRENT\t1\t\t/* Current version */\n+#define EV_NUM\t\t2\n+\n+/* Section header.  */\n+\n+typedef struct\n+{\n+  Elf32_Word\tsh_name;\t\t/* Section name (string tbl index) */\n+  Elf32_Word\tsh_type;\t\t/* Section type */\n+  Elf32_Word\tsh_flags;\t\t/* Section flags */\n+  Elf32_Addr\tsh_addr;\t\t/* Section virtual addr at execution */\n+  Elf32_Off\tsh_offset;\t\t/* Section file offset */\n+  Elf32_Word\tsh_size;\t\t/* Section size in bytes */\n+  Elf32_Word\tsh_link;\t\t/* Link to another section */\n+  Elf32_Word\tsh_info;\t\t/* Additional section information */\n+  Elf32_Word\tsh_addralign;\t\t/* Section alignment */\n+  Elf32_Word\tsh_entsize;\t\t/* Entry size if section holds table */\n+} Elf32_Shdr;\n+\n+typedef struct\n+{\n+  Elf64_Word\tsh_name;\t\t/* Section name (string tbl index) */\n+  Elf64_Word\tsh_type;\t\t/* Section type */\n+  Elf64_Xword\tsh_flags;\t\t/* Section flags */\n+  Elf64_Addr\tsh_addr;\t\t/* Section virtual addr at execution */\n+  Elf64_Off\tsh_offset;\t\t/* Section file offset */\n+  Elf64_Xword\tsh_size;\t\t/* Section size in bytes */\n+  Elf64_Word\tsh_link;\t\t/* Link to another section */\n+  Elf64_Word\tsh_info;\t\t/* Additional section information */\n+  Elf64_Xword\tsh_addralign;\t\t/* Section alignment */\n+  Elf64_Xword\tsh_entsize;\t\t/* Entry size if section holds table */\n+} Elf64_Shdr;\n+\n+/* Special section indices.  */\n+\n+#define SHN_UNDEF\t0\t\t/* Undefined section */\n+#define SHN_LORESERVE\t0xff00\t\t/* Start of reserved indices */\n+#define SHN_LOPROC\t0xff00\t\t/* Start of processor-specific */\n+#define SHN_BEFORE\t0xff00\t\t/* Order section before all others\n+\t\t\t\t\t   (Solaris).  */\n+#define SHN_AFTER\t0xff01\t\t/* Order section after all others\n+\t\t\t\t\t   (Solaris).  */\n+#define SHN_HIPROC\t0xff1f\t\t/* End of processor-specific */\n+#define SHN_LOOS\t0xff20\t\t/* Start of OS-specific */\n+#define SHN_HIOS\t0xff3f\t\t/* End of OS-specific */\n+#define SHN_ABS\t\t0xfff1\t\t/* Associated symbol is absolute */\n+#define SHN_COMMON\t0xfff2\t\t/* Associated symbol is common */\n+#define SHN_XINDEX\t0xffff\t\t/* Index is in extra table.  */\n+#define SHN_HIRESERVE\t0xffff\t\t/* End of reserved indices */\n+\n+/* Legal values for sh_type (section type).  */\n+\n+#define SHT_NULL\t  0\t\t/* Section header table entry unused */\n+#define SHT_PROGBITS\t  1\t\t/* Program data */\n+#define SHT_SYMTAB\t  2\t\t/* Symbol table */\n+#define SHT_STRTAB\t  3\t\t/* String table */\n+#define SHT_RELA\t  4\t\t/* Relocation entries with addends */\n+#define SHT_HASH\t  5\t\t/* Symbol hash table */\n+#define SHT_DYNAMIC\t  6\t\t/* Dynamic linking information */\n+#define SHT_NOTE\t  7\t\t/* Notes */\n+#define SHT_NOBITS\t  8\t\t/* Program space with no data (bss) */\n+#define SHT_REL\t\t  9\t\t/* Relocation entries, no addends */\n+#define SHT_SHLIB\t  10\t\t/* Reserved */\n+#define SHT_DYNSYM\t  11\t\t/* Dynamic linker symbol table */\n+#define SHT_INIT_ARRAY\t  14\t\t/* Array of constructors */\n+#define SHT_FINI_ARRAY\t  15\t\t/* Array of destructors */\n+#define SHT_PREINIT_ARRAY 16\t\t/* Array of pre-constructors */\n+#define SHT_GROUP\t  17\t\t/* Section group */\n+#define SHT_SYMTAB_SHNDX  18\t\t/* Extended section indeces */\n+#define\tSHT_NUM\t\t  19\t\t/* Number of defined types.  */\n+#define SHT_LOOS\t  0x60000000\t/* Start OS-specific.  */\n+#define SHT_GNU_ATTRIBUTES 0x6ffffff5\t/* Object attributes.  */\n+#define SHT_GNU_HASH\t  0x6ffffff6\t/* GNU-style hash table.  */\n+#define SHT_GNU_LIBLIST\t  0x6ffffff7\t/* Prelink library list */\n+#define SHT_CHECKSUM\t  0x6ffffff8\t/* Checksum for DSO content.  */\n+#define SHT_LOSUNW\t  0x6ffffffa\t/* Sun-specific low bound.  */\n+#define SHT_SUNW_move\t  0x6ffffffa\n+#define SHT_SUNW_COMDAT   0x6ffffffb\n+#define SHT_SUNW_syminfo  0x6ffffffc\n+#define SHT_GNU_verdef\t  0x6ffffffd\t/* Version definition section.  */\n+#define SHT_GNU_verneed\t  0x6ffffffe\t/* Version needs section.  */\n+#define SHT_GNU_versym\t  0x6fffffff\t/* Version symbol table.  */\n+#define SHT_HISUNW\t  0x6fffffff\t/* Sun-specific high bound.  */\n+#define SHT_HIOS\t  0x6fffffff\t/* End OS-specific type */\n+#define SHT_LOPROC\t  0x70000000\t/* Start of processor-specific */\n+#define SHT_HIPROC\t  0x7fffffff\t/* End of processor-specific */\n+#define SHT_LOUSER\t  0x80000000\t/* Start of application-specific */\n+#define SHT_HIUSER\t  0x8fffffff\t/* End of application-specific */\n+\n+/* Legal values for sh_flags (section flags).  */\n+\n+#define SHF_WRITE\t     (1 << 0)\t/* Writable */\n+#define SHF_ALLOC\t     (1 << 1)\t/* Occupies memory during execution */\n+#define SHF_EXECINSTR\t     (1 << 2)\t/* Executable */\n+#define SHF_MERGE\t     (1 << 4)\t/* Might be merged */\n+#define SHF_STRINGS\t     (1 << 5)\t/* Contains nul-terminated strings */\n+#define SHF_INFO_LINK\t     (1 << 6)\t/* `sh_info' contains SHT index */\n+#define SHF_LINK_ORDER\t     (1 << 7)\t/* Preserve order after combining */\n+#define SHF_OS_NONCONFORMING (1 << 8)\t/* Non-standard OS specific handling\n+\t\t\t\t\t   required */\n+#define SHF_GROUP\t     (1 << 9)\t/* Section is member of a group.  */\n+#define SHF_TLS\t\t     (1 << 10)\t/* Section hold thread-local data.  */\n+#define SHF_MASKOS\t     0x0ff00000\t/* OS-specific.  */\n+#define SHF_MASKPROC\t     0xf0000000\t/* Processor-specific */\n+#define SHF_ORDERED\t     (1 << 30)\t/* Special ordering requirement\n+\t\t\t\t\t   (Solaris).  */\n+#define SHF_EXCLUDE\t     (1 << 31)\t/* Section is excluded unless\n+\t\t\t\t\t   referenced or allocated (Solaris).*/\n+\n+/* Section group handling.  */\n+#define GRP_COMDAT\t0x1\t\t/* Mark group as COMDAT.  */\n+\n+/* Symbol table entry.  */\n+\n+typedef struct\n+{\n+  Elf32_Word\tst_name;\t\t/* Symbol name (string tbl index) */\n+  Elf32_Addr\tst_value;\t\t/* Symbol value */\n+  Elf32_Word\tst_size;\t\t/* Symbol size */\n+  unsigned char\tst_info;\t\t/* Symbol type and binding */\n+  unsigned char\tst_other;\t\t/* Symbol visibility */\n+  Elf32_Section\tst_shndx;\t\t/* Section index */\n+} Elf32_Sym;\n+\n+typedef struct\n+{\n+  Elf64_Word\tst_name;\t\t/* Symbol name (string tbl index) */\n+  unsigned char\tst_info;\t\t/* Symbol type and binding */\n+  unsigned char st_other;\t\t/* Symbol visibility */\n+  Elf64_Section\tst_shndx;\t\t/* Section index */\n+  Elf64_Addr\tst_value;\t\t/* Symbol value */\n+  Elf64_Xword\tst_size;\t\t/* Symbol size */\n+} Elf64_Sym;\n+\n+/* The syminfo section if available contains additional information about\n+   every dynamic symbol.  */\n+\n+typedef struct\n+{\n+  Elf32_Half si_boundto;\t\t/* Direct bindings, symbol bound to */\n+  Elf32_Half si_flags;\t\t\t/* Per symbol flags */\n+} Elf32_Syminfo;\n+\n+typedef struct\n+{\n+  Elf64_Half si_boundto;\t\t/* Direct bindings, symbol bound to */\n+  Elf64_Half si_flags;\t\t\t/* Per symbol flags */\n+} Elf64_Syminfo;\n+\n+/* Possible values for si_boundto.  */\n+#define SYMINFO_BT_SELF\t\t0xffff\t/* Symbol bound to self */\n+#define SYMINFO_BT_PARENT\t0xfffe\t/* Symbol bound to parent */\n+#define SYMINFO_BT_LOWRESERVE\t0xff00\t/* Beginning of reserved entries */\n+\n+/* Possible bitmasks for si_flags.  */\n+#define SYMINFO_FLG_DIRECT\t0x0001\t/* Direct bound symbol */\n+#define SYMINFO_FLG_PASSTHRU\t0x0002\t/* Pass-thru symbol for translator */\n+#define SYMINFO_FLG_COPY\t0x0004\t/* Symbol is a copy-reloc */\n+#define SYMINFO_FLG_LAZYLOAD\t0x0008\t/* Symbol bound to object to be lazy\n+\t\t\t\t\t   loaded */\n+/* Syminfo version values.  */\n+#define SYMINFO_NONE\t\t0\n+#define SYMINFO_CURRENT\t\t1\n+#define SYMINFO_NUM\t\t2\n+\n+\n+/* How to extract and insert information held in the st_info field.  */\n+\n+#define ELF32_ST_BIND(val)\t\t(((unsigned char) (val)) >> 4)\n+#define ELF32_ST_TYPE(val)\t\t((val) & 0xf)\n+#define ELF32_ST_INFO(bind, type)\t(((bind) << 4) + ((type) & 0xf))\n+\n+/* Both Elf32_Sym and Elf64_Sym use the same one-byte st_info field.  */\n+#define ELF64_ST_BIND(val)\t\tELF32_ST_BIND (val)\n+#define ELF64_ST_TYPE(val)\t\tELF32_ST_TYPE (val)\n+#define ELF64_ST_INFO(bind, type)\tELF32_ST_INFO ((bind), (type))\n+\n+/* Legal values for ST_BIND subfield of st_info (symbol binding).  */\n+\n+#define STB_LOCAL\t0\t\t/* Local symbol */\n+#define STB_GLOBAL\t1\t\t/* Global symbol */\n+#define STB_WEAK\t2\t\t/* Weak symbol */\n+#define\tSTB_NUM\t\t3\t\t/* Number of defined types.  */\n+#define STB_LOOS\t10\t\t/* Start of OS-specific */\n+#define STB_GNU_UNIQUE\t10\t\t/* Unique symbol.  */\n+#define STB_HIOS\t12\t\t/* End of OS-specific */\n+#define STB_LOPROC\t13\t\t/* Start of processor-specific */\n+#define STB_HIPROC\t15\t\t/* End of processor-specific */\n+\n+/* Legal values for ST_TYPE subfield of st_info (symbol type).  */\n+\n+#define STT_NOTYPE\t0\t\t/* Symbol type is unspecified */\n+#define STT_OBJECT\t1\t\t/* Symbol is a data object */\n+#define STT_FUNC\t2\t\t/* Symbol is a code object */\n+#define STT_SECTION\t3\t\t/* Symbol associated with a section */\n+#define STT_FILE\t4\t\t/* Symbol's name is file name */\n+#define STT_COMMON\t5\t\t/* Symbol is a common data object */\n+#define STT_TLS\t\t6\t\t/* Symbol is thread-local data object*/\n+#define\tSTT_NUM\t\t7\t\t/* Number of defined types.  */\n+#define STT_LOOS\t10\t\t/* Start of OS-specific */\n+#define STT_GNU_IFUNC\t10\t\t/* Symbol is indirect code object */\n+#define STT_HIOS\t12\t\t/* End of OS-specific */\n+#define STT_LOPROC\t13\t\t/* Start of processor-specific */\n+#define STT_HIPROC\t15\t\t/* End of processor-specific */\n+\n+\n+/* Symbol table indices are found in the hash buckets and chain table\n+   of a symbol hash table section.  This special index value indicates\n+   the end of a chain, meaning no further symbols are found in that bucket.  */\n+\n+#define STN_UNDEF\t0\t\t/* End of a chain.  */\n+\n+\n+/* How to extract and insert information held in the st_other field.  */\n+\n+#define ELF32_ST_VISIBILITY(o)\t((o) & 0x03)\n+\n+/* For ELF64 the definitions are the same.  */\n+#define ELF64_ST_VISIBILITY(o)\tELF32_ST_VISIBILITY (o)\n+\n+/* Symbol visibility specification encoded in the st_other field.  */\n+#define STV_DEFAULT\t0\t\t/* Default symbol visibility rules */\n+#define STV_INTERNAL\t1\t\t/* Processor specific hidden class */\n+#define STV_HIDDEN\t2\t\t/* Sym unavailable in other modules */\n+#define STV_PROTECTED\t3\t\t/* Not preemptible, not exported */\n+\n+\n+/* Relocation table entry without addend (in section of type SHT_REL).  */\n+\n+typedef struct\n+{\n+  Elf32_Addr\tr_offset;\t\t/* Address */\n+  Elf32_Word\tr_info;\t\t\t/* Relocation type and symbol index */\n+} Elf32_Rel;\n+\n+/* I have seen two different definitions of the Elf64_Rel and\n+   Elf64_Rela structures, so we'll leave them out until Novell (or\n+   whoever) gets their act together.  */\n+/* The following, at least, is used on Sparc v9, MIPS, and Alpha.  */\n+\n+typedef struct\n+{\n+  Elf64_Addr\tr_offset;\t\t/* Address */\n+  Elf64_Xword\tr_info;\t\t\t/* Relocation type and symbol index */\n+} Elf64_Rel;\n+\n+/* Relocation table entry with addend (in section of type SHT_RELA).  */\n+\n+typedef struct\n+{\n+  Elf32_Addr\tr_offset;\t\t/* Address */\n+  Elf32_Word\tr_info;\t\t\t/* Relocation type and symbol index */\n+  Elf32_Sword\tr_addend;\t\t/* Addend */\n+} Elf32_Rela;\n+\n+typedef struct\n+{\n+  Elf64_Addr\tr_offset;\t\t/* Address */\n+  Elf64_Xword\tr_info;\t\t\t/* Relocation type and symbol index */\n+  Elf64_Sxword\tr_addend;\t\t/* Addend */\n+} Elf64_Rela;\n+\n+/* How to extract and insert information held in the r_info field.  */\n+\n+#define ELF32_R_SYM(val)\t\t((val) >> 8)\n+#define ELF32_R_TYPE(val)\t\t((val) & 0xff)\n+#define ELF32_R_INFO(sym, type)\t\t(((sym) << 8) + ((type) & 0xff))\n+\n+#define ELF64_R_SYM(i)\t\t\t((i) >> 32)\n+#define ELF64_R_TYPE(i)\t\t\t((i) & 0xffffffff)\n+#define ELF64_R_INFO(sym,type)\t\t((((Elf64_Xword) (sym)) << 32) + (type))\n+\n+/* Program segment header.  */\n+\n+typedef struct\n+{\n+  Elf32_Word\tp_type;\t\t\t/* Segment type */\n+  Elf32_Off\tp_offset;\t\t/* Segment file offset */\n+  Elf32_Addr\tp_vaddr;\t\t/* Segment virtual address */\n+  Elf32_Addr\tp_paddr;\t\t/* Segment physical address */\n+  Elf32_Word\tp_filesz;\t\t/* Segment size in file */\n+  Elf32_Word\tp_memsz;\t\t/* Segment size in memory */\n+  Elf32_Word\tp_flags;\t\t/* Segment flags */\n+  Elf32_Word\tp_align;\t\t/* Segment alignment */\n+} Elf32_Phdr;\n+\n+typedef struct\n+{\n+  Elf64_Word\tp_type;\t\t\t/* Segment type */\n+  Elf64_Word\tp_flags;\t\t/* Segment flags */\n+  Elf64_Off\tp_offset;\t\t/* Segment file offset */\n+  Elf64_Addr\tp_vaddr;\t\t/* Segment virtual address */\n+  Elf64_Addr\tp_paddr;\t\t/* Segment physical address */\n+  Elf64_Xword\tp_filesz;\t\t/* Segment size in file */\n+  Elf64_Xword\tp_memsz;\t\t/* Segment size in memory */\n+  Elf64_Xword\tp_align;\t\t/* Segment alignment */\n+} Elf64_Phdr;\n+\n+/* Special value for e_phnum.  This indicates that the real number of\n+   program headers is too large to fit into e_phnum.  Instead the real\n+   value is in the field sh_info of section 0.  */\n+\n+#define PN_XNUM\t\t0xffff\n+\n+/* Legal values for p_type (segment type).  */\n+\n+#define\tPT_NULL\t\t0\t\t/* Program header table entry unused */\n+#define PT_LOAD\t\t1\t\t/* Loadable program segment */\n+#define PT_DYNAMIC\t2\t\t/* Dynamic linking information */\n+#define PT_INTERP\t3\t\t/* Program interpreter */\n+#define PT_NOTE\t\t4\t\t/* Auxiliary information */\n+#define PT_SHLIB\t5\t\t/* Reserved */\n+#define PT_PHDR\t\t6\t\t/* Entry for header table itself */\n+#define PT_TLS\t\t7\t\t/* Thread-local storage segment */\n+#define\tPT_NUM\t\t8\t\t/* Number of defined types */\n+#define PT_LOOS\t\t0x60000000\t/* Start of OS-specific */\n+#define PT_GNU_EH_FRAME\t0x6474e550\t/* GCC .eh_frame_hdr segment */\n+#define PT_GNU_STACK\t0x6474e551\t/* Indicates stack executability */\n+#define PT_GNU_RELRO\t0x6474e552\t/* Read-only after relocation */\n+#define PT_LOSUNW\t0x6ffffffa\n+#define PT_SUNWBSS\t0x6ffffffa\t/* Sun Specific segment */\n+#define PT_SUNWSTACK\t0x6ffffffb\t/* Stack segment */\n+#define PT_HISUNW\t0x6fffffff\n+#define PT_HIOS\t\t0x6fffffff\t/* End of OS-specific */\n+#define PT_LOPROC\t0x70000000\t/* Start of processor-specific */\n+#define PT_HIPROC\t0x7fffffff\t/* End of processor-specific */\n+\n+/* Legal values for p_flags (segment flags).  */\n+\n+#define PF_X\t\t(1 << 0)\t/* Segment is executable */\n+#define PF_W\t\t(1 << 1)\t/* Segment is writable */\n+#define PF_R\t\t(1 << 2)\t/* Segment is readable */\n+#define PF_MASKOS\t0x0ff00000\t/* OS-specific */\n+#define PF_MASKPROC\t0xf0000000\t/* Processor-specific */\n+\n+/* Legal values for note segment descriptor types for core files. */\n+\n+#define NT_PRSTATUS\t1\t\t/* Contains copy of prstatus struct */\n+#define NT_FPREGSET\t2\t\t/* Contains copy of fpregset struct */\n+#define NT_PRPSINFO\t3\t\t/* Contains copy of prpsinfo struct */\n+#define NT_PRXREG\t4\t\t/* Contains copy of prxregset struct */\n+#define NT_TASKSTRUCT\t4\t\t/* Contains copy of task structure */\n+#define NT_PLATFORM\t5\t\t/* String from sysinfo(SI_PLATFORM) */\n+#define NT_AUXV\t\t6\t\t/* Contains copy of auxv array */\n+#define NT_GWINDOWS\t7\t\t/* Contains copy of gwindows struct */\n+#define NT_ASRS\t\t8\t\t/* Contains copy of asrset struct */\n+#define NT_PSTATUS\t10\t\t/* Contains copy of pstatus struct */\n+#define NT_PSINFO\t13\t\t/* Contains copy of psinfo struct */\n+#define NT_PRCRED\t14\t\t/* Contains copy of prcred struct */\n+#define NT_UTSNAME\t15\t\t/* Contains copy of utsname struct */\n+#define NT_LWPSTATUS\t16\t\t/* Contains copy of lwpstatus struct */\n+#define NT_LWPSINFO\t17\t\t/* Contains copy of lwpinfo struct */\n+#define NT_PRFPXREG\t20\t\t/* Contains copy of fprxregset struct */\n+#define NT_PRXFPREG\t0x46e62b7f\t/* Contains copy of user_fxsr_struct */\n+#define NT_PPC_VMX\t0x100\t\t/* PowerPC Altivec/VMX registers */\n+#define NT_PPC_SPE\t0x101\t\t/* PowerPC SPE/EVR registers */\n+#define NT_PPC_VSX\t0x102\t\t/* PowerPC VSX registers */\n+#define NT_386_TLS\t0x200\t\t/* i386 TLS slots (struct user_desc) */\n+#define NT_386_IOPERM\t0x201\t\t/* x86 io permission bitmap (1=deny) */\n+#define NT_X86_XSTATE\t0x202\t\t/* x86 extended state using xsave */\n+\n+/* Legal values for the note segment descriptor types for object files.  */\n+\n+#define NT_VERSION\t1\t\t/* Contains a version string.  */\n+\n+\n+/* Dynamic section entry.  */\n+\n+typedef struct\n+{\n+  Elf32_Sword\td_tag;\t\t\t/* Dynamic entry type */\n+  union\n+    {\n+      Elf32_Word d_val;\t\t\t/* Integer value */\n+      Elf32_Addr d_ptr;\t\t\t/* Address value */\n+    } d_un;\n+} Elf32_Dyn;\n+\n+typedef struct\n+{\n+  Elf64_Sxword\td_tag;\t\t\t/* Dynamic entry type */\n+  union\n+    {\n+      Elf64_Xword d_val;\t\t/* Integer value */\n+      Elf64_Addr d_ptr;\t\t\t/* Address value */\n+    } d_un;\n+} Elf64_Dyn;\n+\n+/* Legal values for d_tag (dynamic entry type).  */\n+\n+#define DT_NULL\t\t0\t\t/* Marks end of dynamic section */\n+#define DT_NEEDED\t1\t\t/* Name of needed library */\n+#define DT_PLTRELSZ\t2\t\t/* Size in bytes of PLT relocs */\n+#define DT_PLTGOT\t3\t\t/* Processor defined value */\n+#define DT_HASH\t\t4\t\t/* Address of symbol hash table */\n+#define DT_STRTAB\t5\t\t/* Address of string table */\n+#define DT_SYMTAB\t6\t\t/* Address of symbol table */\n+#define DT_RELA\t\t7\t\t/* Address of Rela relocs */\n+#define DT_RELASZ\t8\t\t/* Total size of Rela relocs */\n+#define DT_RELAENT\t9\t\t/* Size of one Rela reloc */\n+#define DT_STRSZ\t10\t\t/* Size of string table */\n+#define DT_SYMENT\t11\t\t/* Size of one symbol table entry */\n+#define DT_INIT\t\t12\t\t/* Address of init function */\n+#define DT_FINI\t\t13\t\t/* Address of termination function */\n+#define DT_SONAME\t14\t\t/* Name of shared object */\n+#define DT_RPATH\t15\t\t/* Library search path (deprecated) */\n+#define DT_SYMBOLIC\t16\t\t/* Start symbol search here */\n+#define DT_REL\t\t17\t\t/* Address of Rel relocs */\n+#define DT_RELSZ\t18\t\t/* Total size of Rel relocs */\n+#define DT_RELENT\t19\t\t/* Size of one Rel reloc */\n+#define DT_PLTREL\t20\t\t/* Type of reloc in PLT */\n+#define DT_DEBUG\t21\t\t/* For debugging; unspecified */\n+#define DT_TEXTREL\t22\t\t/* Reloc might modify .text */\n+#define DT_JMPREL\t23\t\t/* Address of PLT relocs */\n+#define\tDT_BIND_NOW\t24\t\t/* Process relocations of object */\n+#define\tDT_INIT_ARRAY\t25\t\t/* Array with addresses of init fct */\n+#define\tDT_FINI_ARRAY\t26\t\t/* Array with addresses of fini fct */\n+#define\tDT_INIT_ARRAYSZ\t27\t\t/* Size in bytes of DT_INIT_ARRAY */\n+#define\tDT_FINI_ARRAYSZ\t28\t\t/* Size in bytes of DT_FINI_ARRAY */\n+#define DT_RUNPATH\t29\t\t/* Library search path */\n+#define DT_FLAGS\t30\t\t/* Flags for the object being loaded */\n+#define DT_ENCODING\t32\t\t/* Start of encoded range */\n+#define DT_PREINIT_ARRAY 32\t\t/* Array with addresses of preinit fct*/\n+#define DT_PREINIT_ARRAYSZ 33\t\t/* size in bytes of DT_PREINIT_ARRAY */\n+#define\tDT_NUM\t\t34\t\t/* Number used */\n+#define DT_LOOS\t\t0x6000000d\t/* Start of OS-specific */\n+#define DT_HIOS\t\t0x6ffff000\t/* End of OS-specific */\n+#define DT_LOPROC\t0x70000000\t/* Start of processor-specific */\n+#define DT_HIPROC\t0x7fffffff\t/* End of processor-specific */\n+#define\tDT_PROCNUM\tDT_MIPS_NUM\t/* Most used by any processor */\n+\n+/* DT_* entries which fall between DT_VALRNGHI & DT_VALRNGLO use the\n+   Dyn.d_un.d_val field of the Elf*_Dyn structure.  This follows Sun's\n+   approach.  */\n+#define DT_VALRNGLO\t0x6ffffd00\n+#define DT_GNU_PRELINKED 0x6ffffdf5\t/* Prelinking timestamp */\n+#define DT_GNU_CONFLICTSZ 0x6ffffdf6\t/* Size of conflict section */\n+#define DT_GNU_LIBLISTSZ 0x6ffffdf7\t/* Size of library list */\n+#define DT_CHECKSUM\t0x6ffffdf8\n+#define DT_PLTPADSZ\t0x6ffffdf9\n+#define DT_MOVEENT\t0x6ffffdfa\n+#define DT_MOVESZ\t0x6ffffdfb\n+#define DT_FEATURE_1\t0x6ffffdfc\t/* Feature selection (DTF_*).  */\n+#define DT_POSFLAG_1\t0x6ffffdfd\t/* Flags for DT_* entries, effecting\n+\t\t\t\t\t   the following DT_* entry.  */\n+#define DT_SYMINSZ\t0x6ffffdfe\t/* Size of syminfo table (in bytes) */\n+#define DT_SYMINENT\t0x6ffffdff\t/* Entry size of syminfo */\n+#define DT_VALRNGHI\t0x6ffffdff\n+#define DT_VALTAGIDX(tag)\t(DT_VALRNGHI - (tag))\t/* Reverse order! */\n+#define DT_VALNUM 12\n+\n+/* DT_* entries which fall between DT_ADDRRNGHI & DT_ADDRRNGLO use the\n+   Dyn.d_un.d_ptr field of the Elf*_Dyn structure.\n+\n+   If any adjustment is made to the ELF object after it has been\n+   built these entries will need to be adjusted.  */\n+#define DT_ADDRRNGLO\t0x6ffffe00\n+#define DT_GNU_HASH\t0x6ffffef5\t/* GNU-style hash table.  */\n+#define DT_TLSDESC_PLT\t0x6ffffef6\n+#define DT_TLSDESC_GOT\t0x6ffffef7\n+#define DT_GNU_CONFLICT\t0x6ffffef8\t/* Start of conflict section */\n+#define DT_GNU_LIBLIST\t0x6ffffef9\t/* Library list */\n+#define DT_CONFIG\t0x6ffffefa\t/* Configuration information.  */\n+#define DT_DEPAUDIT\t0x6ffffefb\t/* Dependency auditing.  */\n+#define DT_AUDIT\t0x6ffffefc\t/* Object auditing.  */\n+#define\tDT_PLTPAD\t0x6ffffefd\t/* PLT padding.  */\n+#define\tDT_MOVETAB\t0x6ffffefe\t/* Move table.  */\n+#define DT_SYMINFO\t0x6ffffeff\t/* Syminfo table.  */\n+#define DT_ADDRRNGHI\t0x6ffffeff\n+#define DT_ADDRTAGIDX(tag)\t(DT_ADDRRNGHI - (tag))\t/* Reverse order! */\n+#define DT_ADDRNUM 11\n+\n+/* The versioning entry types.  The next are defined as part of the\n+   GNU extension.  */\n+#define DT_VERSYM\t0x6ffffff0\n+\n+#define DT_RELACOUNT\t0x6ffffff9\n+#define DT_RELCOUNT\t0x6ffffffa\n+\n+/* These were chosen by Sun.  */\n+#define DT_FLAGS_1\t0x6ffffffb\t/* State flags, see DF_1_* below.  */\n+#define\tDT_VERDEF\t0x6ffffffc\t/* Address of version definition\n+\t\t\t\t\t   table */\n+#define\tDT_VERDEFNUM\t0x6ffffffd\t/* Number of version definitions */\n+#define\tDT_VERNEED\t0x6ffffffe\t/* Address of table with needed\n+\t\t\t\t\t   versions */\n+#define\tDT_VERNEEDNUM\t0x6fffffff\t/* Number of needed versions */\n+#define DT_VERSIONTAGIDX(tag)\t(DT_VERNEEDNUM - (tag))\t/* Reverse order! */\n+#define DT_VERSIONTAGNUM 16\n+\n+/* Sun added these machine-independent extensions in the \"processor-specific\"\n+   range.  Be compatible.  */\n+#define DT_AUXILIARY    0x7ffffffd      /* Shared object to load before self */\n+#define DT_FILTER       0x7fffffff      /* Shared object to get values from */\n+#define DT_EXTRATAGIDX(tag)\t((Elf32_Word)-((Elf32_Sword) (tag) <<1>>1)-1)\n+#define DT_EXTRANUM\t3\n+\n+/* Values of `d_un.d_val' in the DT_FLAGS entry.  */\n+#define DF_ORIGIN\t0x00000001\t/* Object may use DF_ORIGIN */\n+#define DF_SYMBOLIC\t0x00000002\t/* Symbol resolutions starts here */\n+#define DF_TEXTREL\t0x00000004\t/* Object contains text relocations */\n+#define DF_BIND_NOW\t0x00000008\t/* No lazy binding for this object */\n+#define DF_STATIC_TLS\t0x00000010\t/* Module uses the static TLS model */\n+\n+/* State flags selectable in the `d_un.d_val' element of the DT_FLAGS_1\n+   entry in the dynamic section.  */\n+#define DF_1_NOW\t0x00000001\t/* Set RTLD_NOW for this object.  */\n+#define DF_1_GLOBAL\t0x00000002\t/* Set RTLD_GLOBAL for this object.  */\n+#define DF_1_GROUP\t0x00000004\t/* Set RTLD_GROUP for this object.  */\n+#define DF_1_NODELETE\t0x00000008\t/* Set RTLD_NODELETE for this object.*/\n+#define DF_1_LOADFLTR\t0x00000010\t/* Trigger filtee loading at runtime.*/\n+#define DF_1_INITFIRST\t0x00000020\t/* Set RTLD_INITFIRST for this object*/\n+#define DF_1_NOOPEN\t0x00000040\t/* Set RTLD_NOOPEN for this object.  */\n+#define DF_1_ORIGIN\t0x00000080\t/* $ORIGIN must be handled.  */\n+#define DF_1_DIRECT\t0x00000100\t/* Direct binding enabled.  */\n+#define DF_1_TRANS\t0x00000200\n+#define DF_1_INTERPOSE\t0x00000400\t/* Object is used to interpose.  */\n+#define DF_1_NODEFLIB\t0x00000800\t/* Ignore default lib search path.  */\n+#define DF_1_NODUMP\t0x00001000\t/* Object can't be dldump'ed.  */\n+#define DF_1_CONFALT\t0x00002000\t/* Configuration alternative created.*/\n+#define DF_1_ENDFILTEE\t0x00004000\t/* Filtee terminates filters search. */\n+#define\tDF_1_DISPRELDNE\t0x00008000\t/* Disp reloc applied at build time. */\n+#define\tDF_1_DISPRELPND\t0x00010000\t/* Disp reloc applied at run-time.  */\n+\n+/* Flags for the feature selection in DT_FEATURE_1.  */\n+#define DTF_1_PARINIT\t0x00000001\n+#define DTF_1_CONFEXP\t0x00000002\n+\n+/* Flags in the DT_POSFLAG_1 entry effecting only the next DT_* entry.  */\n+#define DF_P1_LAZYLOAD\t0x00000001\t/* Lazyload following object.  */\n+#define DF_P1_GROUPPERM\t0x00000002\t/* Symbols from next object are not\n+\t\t\t\t\t   generally available.  */\n+\n+/* Version definition sections.  */\n+\n+typedef struct\n+{\n+  Elf32_Half\tvd_version;\t\t/* Version revision */\n+  Elf32_Half\tvd_flags;\t\t/* Version information */\n+  Elf32_Half\tvd_ndx;\t\t\t/* Version Index */\n+  Elf32_Half\tvd_cnt;\t\t\t/* Number of associated aux entries */\n+  Elf32_Word\tvd_hash;\t\t/* Version name hash value */\n+  Elf32_Word\tvd_aux;\t\t\t/* Offset in bytes to verdaux array */\n+  Elf32_Word\tvd_next;\t\t/* Offset in bytes to next verdef\n+\t\t\t\t\t   entry */\n+} Elf32_Verdef;\n+\n+typedef struct\n+{\n+  Elf64_Half\tvd_version;\t\t/* Version revision */\n+  Elf64_Half\tvd_flags;\t\t/* Version information */\n+  Elf64_Half\tvd_ndx;\t\t\t/* Version Index */\n+  Elf64_Half\tvd_cnt;\t\t\t/* Number of associated aux entries */\n+  Elf64_Word\tvd_hash;\t\t/* Version name hash value */\n+  Elf64_Word\tvd_aux;\t\t\t/* Offset in bytes to verdaux array */\n+  Elf64_Word\tvd_next;\t\t/* Offset in bytes to next verdef\n+\t\t\t\t\t   entry */\n+} Elf64_Verdef;\n+\n+\n+/* Legal values for vd_version (version revision).  */\n+#define VER_DEF_NONE\t0\t\t/* No version */\n+#define VER_DEF_CURRENT\t1\t\t/* Current version */\n+#define VER_DEF_NUM\t2\t\t/* Given version number */\n+\n+/* Legal values for vd_flags (version information flags).  */\n+#define VER_FLG_BASE\t0x1\t\t/* Version definition of file itself */\n+#define VER_FLG_WEAK\t0x2\t\t/* Weak version identifier */\n+\n+/* Versym symbol index values.  */\n+#define\tVER_NDX_LOCAL\t\t0\t/* Symbol is local.  */\n+#define\tVER_NDX_GLOBAL\t\t1\t/* Symbol is global.  */\n+#define\tVER_NDX_LORESERVE\t0xff00\t/* Beginning of reserved entries.  */\n+#define\tVER_NDX_ELIMINATE\t0xff01\t/* Symbol is to be eliminated.  */\n+\n+/* Auxialiary version information.  */\n+\n+typedef struct\n+{\n+  Elf32_Word\tvda_name;\t\t/* Version or dependency names */\n+  Elf32_Word\tvda_next;\t\t/* Offset in bytes to next verdaux\n+\t\t\t\t\t   entry */\n+} Elf32_Verdaux;\n+\n+typedef struct\n+{\n+  Elf64_Word\tvda_name;\t\t/* Version or dependency names */\n+  Elf64_Word\tvda_next;\t\t/* Offset in bytes to next verdaux\n+\t\t\t\t\t   entry */\n+} Elf64_Verdaux;\n+\n+\n+/* Version dependency section.  */\n+\n+typedef struct\n+{\n+  Elf32_Half\tvn_version;\t\t/* Version of structure */\n+  Elf32_Half\tvn_cnt;\t\t\t/* Number of associated aux entries */\n+  Elf32_Word\tvn_file;\t\t/* Offset of filename for this\n+\t\t\t\t\t   dependency */\n+  Elf32_Word\tvn_aux;\t\t\t/* Offset in bytes to vernaux array */\n+  Elf32_Word\tvn_next;\t\t/* Offset in bytes to next verneed\n+\t\t\t\t\t   entry */\n+} Elf32_Verneed;\n+\n+typedef struct\n+{\n+  Elf64_Half\tvn_version;\t\t/* Version of structure */\n+  Elf64_Half\tvn_cnt;\t\t\t/* Number of associated aux entries */\n+  Elf64_Word\tvn_file;\t\t/* Offset of filename for this\n+\t\t\t\t\t   dependency */\n+  Elf64_Word\tvn_aux;\t\t\t/* Offset in bytes to vernaux array */\n+  Elf64_Word\tvn_next;\t\t/* Offset in bytes to next verneed\n+\t\t\t\t\t   entry */\n+} Elf64_Verneed;\n+\n+\n+/* Legal values for vn_version (version revision).  */\n+#define VER_NEED_NONE\t 0\t\t/* No version */\n+#define VER_NEED_CURRENT 1\t\t/* Current version */\n+#define VER_NEED_NUM\t 2\t\t/* Given version number */\n+\n+/* Auxiliary needed version information.  */\n+\n+typedef struct\n+{\n+  Elf32_Word\tvna_hash;\t\t/* Hash value of dependency name */\n+  Elf32_Half\tvna_flags;\t\t/* Dependency specific information */\n+  Elf32_Half\tvna_other;\t\t/* Unused */\n+  Elf32_Word\tvna_name;\t\t/* Dependency name string offset */\n+  Elf32_Word\tvna_next;\t\t/* Offset in bytes to next vernaux\n+\t\t\t\t\t   entry */\n+} Elf32_Vernaux;\n+\n+typedef struct\n+{\n+  Elf64_Word\tvna_hash;\t\t/* Hash value of dependency name */\n+  Elf64_Half\tvna_flags;\t\t/* Dependency specific information */\n+  Elf64_Half\tvna_other;\t\t/* Unused */\n+  Elf64_Word\tvna_name;\t\t/* Dependency name string offset */\n+  Elf64_Word\tvna_next;\t\t/* Offset in bytes to next vernaux\n+\t\t\t\t\t   entry */\n+} Elf64_Vernaux;\n+\n+\n+/* Legal values for vna_flags.  */\n+#define VER_FLG_WEAK\t0x2\t\t/* Weak version identifier */\n+\n+\n+/* Auxiliary vector.  */\n+\n+/* This vector is normally only used by the program interpreter.  The\n+   usual definition in an ABI supplement uses the name auxv_t.  The\n+   vector is not usually defined in a standard <elf.h> file, but it\n+   can't hurt.  We rename it to avoid conflicts.  The sizes of these\n+   types are an arrangement between the exec server and the program\n+   interpreter, so we don't fully specify them here.  */\n+\n+typedef struct\n+{\n+  uint32_t a_type;\t\t/* Entry type */\n+  union\n+    {\n+      uint32_t a_val;\t\t/* Integer value */\n+      /* We use to have pointer elements added here.  We cannot do that,\n+\t though, since it does not work when using 32-bit definitions\n+\t on 64-bit platforms and vice versa.  */\n+    } a_un;\n+} Elf32_auxv_t;\n+\n+typedef struct\n+{\n+  uint64_t a_type;\t\t/* Entry type */\n+  union\n+    {\n+      uint64_t a_val;\t\t/* Integer value */\n+      /* We use to have pointer elements added here.  We cannot do that,\n+\t though, since it does not work when using 32-bit definitions\n+\t on 64-bit platforms and vice versa.  */\n+    } a_un;\n+} Elf64_auxv_t;\n+\n+/* Legal values for a_type (entry type).  */\n+\n+#define AT_NULL\t\t0\t\t/* End of vector */\n+#define AT_IGNORE\t1\t\t/* Entry should be ignored */\n+#define AT_EXECFD\t2\t\t/* File descriptor of program */\n+#define AT_PHDR\t\t3\t\t/* Program headers for program */\n+#define AT_PHENT\t4\t\t/* Size of program header entry */\n+#define AT_PHNUM\t5\t\t/* Number of program headers */\n+#define AT_PAGESZ\t6\t\t/* System page size */\n+#define AT_BASE\t\t7\t\t/* Base address of interpreter */\n+#define AT_FLAGS\t8\t\t/* Flags */\n+#define AT_ENTRY\t9\t\t/* Entry point of program */\n+#define AT_NOTELF\t10\t\t/* Program is not ELF */\n+#define AT_UID\t\t11\t\t/* Real uid */\n+#define AT_EUID\t\t12\t\t/* Effective uid */\n+#define AT_GID\t\t13\t\t/* Real gid */\n+#define AT_EGID\t\t14\t\t/* Effective gid */\n+#define AT_CLKTCK\t17\t\t/* Frequency of times() */\n+\n+/* Some more special a_type values describing the hardware.  */\n+#define AT_PLATFORM\t15\t\t/* String identifying platform.  */\n+#define AT_HWCAP\t16\t\t/* Machine dependent hints about\n+\t\t\t\t\t   processor capabilities.  */\n+\n+/* This entry gives some information about the FPU initialization\n+   performed by the kernel.  */\n+#define AT_FPUCW\t18\t\t/* Used FPU control word.  */\n+\n+/* Cache block sizes.  */\n+#define AT_DCACHEBSIZE\t19\t\t/* Data cache block size.  */\n+#define AT_ICACHEBSIZE\t20\t\t/* Instruction cache block size.  */\n+#define AT_UCACHEBSIZE\t21\t\t/* Unified cache block size.  */\n+\n+/* A special ignored value for PPC, used by the kernel to control the\n+   interpretation of the AUXV. Must be > 16.  */\n+#define AT_IGNOREPPC\t22\t\t/* Entry should be ignored.  */\n+\n+#define\tAT_SECURE\t23\t\t/* Boolean, was exec setuid-like?  */\n+\n+#define AT_BASE_PLATFORM 24\t\t/* String identifying real platforms.*/\n+\n+#define AT_RANDOM\t25\t\t/* Address of 16 random bytes.  */\n+\n+#define AT_EXECFN\t31\t\t/* Filename of executable.  */\n+\n+/* Pointer to the global system page used for system calls and other\n+   nice things.  */\n+#define AT_SYSINFO\t32\n+#define AT_SYSINFO_EHDR\t33\n+\n+/* Shapes of the caches.  Bits 0-3 contains associativity; bits 4-7 contains\n+   log2 of line size; mask those to get cache size.  */\n+#define AT_L1I_CACHESHAPE\t34\n+#define AT_L1D_CACHESHAPE\t35\n+#define AT_L2_CACHESHAPE\t36\n+#define AT_L3_CACHESHAPE\t37\n+\n+/* Note section contents.  Each entry in the note section begins with\n+   a header of a fixed form.  */\n+\n+typedef struct\n+{\n+  Elf32_Word n_namesz;\t\t\t/* Length of the note's name.  */\n+  Elf32_Word n_descsz;\t\t\t/* Length of the note's descriptor.  */\n+  Elf32_Word n_type;\t\t\t/* Type of the note.  */\n+} Elf32_Nhdr;\n+\n+typedef struct\n+{\n+  Elf64_Word n_namesz;\t\t\t/* Length of the note's name.  */\n+  Elf64_Word n_descsz;\t\t\t/* Length of the note's descriptor.  */\n+  Elf64_Word n_type;\t\t\t/* Type of the note.  */\n+} Elf64_Nhdr;\n+\n+/* Known names of notes.  */\n+\n+/* Solaris entries in the note section have this name.  */\n+#define ELF_NOTE_SOLARIS\t\"SUNW Solaris\"\n+\n+/* Note entries for GNU systems have this name.  */\n+#define ELF_NOTE_GNU\t\t\"GNU\"\n+\n+\n+/* Defined types of notes for Solaris.  */\n+\n+/* Value of descriptor (one word) is desired pagesize for the binary.  */\n+#define ELF_NOTE_PAGESIZE_HINT\t1\n+\n+\n+/* Defined note types for GNU systems.  */\n+\n+/* ABI information.  The descriptor consists of words:\n+   word 0: OS descriptor\n+   word 1: major version of the ABI\n+   word 2: minor version of the ABI\n+   word 3: subminor version of the ABI\n+*/\n+#define NT_GNU_ABI_TAG\t1\n+#define ELF_NOTE_ABI\tNT_GNU_ABI_TAG /* Old name.  */\n+\n+/* Known OSes.  These values can appear in word 0 of an\n+   NT_GNU_ABI_TAG note section entry.  */\n+#define ELF_NOTE_OS_LINUX\t0\n+#define ELF_NOTE_OS_GNU\t\t1\n+#define ELF_NOTE_OS_SOLARIS2\t2\n+#define ELF_NOTE_OS_FREEBSD\t3\n+\n+/* Synthetic hwcap information.  The descriptor begins with two words:\n+   word 0: number of entries\n+   word 1: bitmask of enabled entries\n+   Then follow variable-length entries, one byte followed by a\n+   '\\0'-terminated hwcap name string.  The byte gives the bit\n+   number to test if enabled, (1U << bit) & bitmask.  */\n+#define NT_GNU_HWCAP\t2\n+\n+/* Build ID bits as generated by ld --build-id.\n+   The descriptor consists of any nonzero number of bytes.  */\n+#define NT_GNU_BUILD_ID\t3\n+\n+/* Version note generated by GNU gold containing a version string.  */\n+#define NT_GNU_GOLD_VERSION\t4\n+\n+\n+/* Move records.  */\n+typedef struct\n+{\n+  Elf32_Xword m_value;\t\t/* Symbol value.  */\n+  Elf32_Word m_info;\t\t/* Size and index.  */\n+  Elf32_Word m_poffset;\t\t/* Symbol offset.  */\n+  Elf32_Half m_repeat;\t\t/* Repeat count.  */\n+  Elf32_Half m_stride;\t\t/* Stride info.  */\n+} Elf32_Move;\n+\n+typedef struct\n+{\n+  Elf64_Xword m_value;\t\t/* Symbol value.  */\n+  Elf64_Xword m_info;\t\t/* Size and index.  */\n+  Elf64_Xword m_poffset;\t/* Symbol offset.  */\n+  Elf64_Half m_repeat;\t\t/* Repeat count.  */\n+  Elf64_Half m_stride;\t\t/* Stride info.  */\n+} Elf64_Move;\n+\n+/* Macro to construct move records.  */\n+#define ELF32_M_SYM(info)\t((info) >> 8)\n+#define ELF32_M_SIZE(info)\t((unsigned char) (info))\n+#define ELF32_M_INFO(sym, size)\t(((sym) << 8) + (unsigned char) (size))\n+\n+#define ELF64_M_SYM(info)\tELF32_M_SYM (info)\n+#define ELF64_M_SIZE(info)\tELF32_M_SIZE (info)\n+#define ELF64_M_INFO(sym, size)\tELF32_M_INFO (sym, size)\n+\n+\n+/* Motorola 68k specific definitions.  */\n+\n+/* Values for Elf32_Ehdr.e_flags.  */\n+#define EF_CPU32\t0x00810000\n+\n+/* m68k relocs.  */\n+\n+#define R_68K_NONE\t0\t\t/* No reloc */\n+#define R_68K_32\t1\t\t/* Direct 32 bit  */\n+#define R_68K_16\t2\t\t/* Direct 16 bit  */\n+#define R_68K_8\t\t3\t\t/* Direct 8 bit  */\n+#define R_68K_PC32\t4\t\t/* PC relative 32 bit */\n+#define R_68K_PC16\t5\t\t/* PC relative 16 bit */\n+#define R_68K_PC8\t6\t\t/* PC relative 8 bit */\n+#define R_68K_GOT32\t7\t\t/* 32 bit PC relative GOT entry */\n+#define R_68K_GOT16\t8\t\t/* 16 bit PC relative GOT entry */\n+#define R_68K_GOT8\t9\t\t/* 8 bit PC relative GOT entry */\n+#define R_68K_GOT32O\t10\t\t/* 32 bit GOT offset */\n+#define R_68K_GOT16O\t11\t\t/* 16 bit GOT offset */\n+#define R_68K_GOT8O\t12\t\t/* 8 bit GOT offset */\n+#define R_68K_PLT32\t13\t\t/* 32 bit PC relative PLT address */\n+#define R_68K_PLT16\t14\t\t/* 16 bit PC relative PLT address */\n+#define R_68K_PLT8\t15\t\t/* 8 bit PC relative PLT address */\n+#define R_68K_PLT32O\t16\t\t/* 32 bit PLT offset */\n+#define R_68K_PLT16O\t17\t\t/* 16 bit PLT offset */\n+#define R_68K_PLT8O\t18\t\t/* 8 bit PLT offset */\n+#define R_68K_COPY\t19\t\t/* Copy symbol at runtime */\n+#define R_68K_GLOB_DAT\t20\t\t/* Create GOT entry */\n+#define R_68K_JMP_SLOT\t21\t\t/* Create PLT entry */\n+#define R_68K_RELATIVE\t22\t\t/* Adjust by program base */\n+#define R_68K_TLS_GD32      25          /* 32 bit GOT offset for GD */\n+#define R_68K_TLS_GD16      26          /* 16 bit GOT offset for GD */\n+#define R_68K_TLS_GD8       27          /* 8 bit GOT offset for GD */\n+#define R_68K_TLS_LDM32     28          /* 32 bit GOT offset for LDM */\n+#define R_68K_TLS_LDM16     29          /* 16 bit GOT offset for LDM */\n+#define R_68K_TLS_LDM8      30          /* 8 bit GOT offset for LDM */\n+#define R_68K_TLS_LDO32     31          /* 32 bit module-relative offset */\n+#define R_68K_TLS_LDO16     32          /* 16 bit module-relative offset */\n+#define R_68K_TLS_LDO8      33          /* 8 bit module-relative offset */\n+#define R_68K_TLS_IE32      34          /* 32 bit GOT offset for IE */\n+#define R_68K_TLS_IE16      35          /* 16 bit GOT offset for IE */\n+#define R_68K_TLS_IE8       36          /* 8 bit GOT offset for IE */\n+#define R_68K_TLS_LE32      37          /* 32 bit offset relative to\n+\t\t\t\t\t   static TLS block */\n+#define R_68K_TLS_LE16      38          /* 16 bit offset relative to\n+\t\t\t\t\t   static TLS block */\n+#define R_68K_TLS_LE8       39          /* 8 bit offset relative to\n+\t\t\t\t\t   static TLS block */\n+#define R_68K_TLS_DTPMOD32  40          /* 32 bit module number */\n+#define R_68K_TLS_DTPREL32  41          /* 32 bit module-relative offset */\n+#define R_68K_TLS_TPREL32   42          /* 32 bit TP-relative offset */\n+/* Keep this the last entry.  */\n+#define R_68K_NUM\t43\n+\n+/* Intel 80386 specific definitions.  */\n+\n+/* i386 relocs.  */\n+\n+#define R_386_NONE\t   0\t\t/* No reloc */\n+#define R_386_32\t   1\t\t/* Direct 32 bit  */\n+#define R_386_PC32\t   2\t\t/* PC relative 32 bit */\n+#define R_386_GOT32\t   3\t\t/* 32 bit GOT entry */\n+#define R_386_PLT32\t   4\t\t/* 32 bit PLT address */\n+#define R_386_COPY\t   5\t\t/* Copy symbol at runtime */\n+#define R_386_GLOB_DAT\t   6\t\t/* Create GOT entry */\n+#define R_386_JMP_SLOT\t   7\t\t/* Create PLT entry */\n+#define R_386_RELATIVE\t   8\t\t/* Adjust by program base */\n+#define R_386_GOTOFF\t   9\t\t/* 32 bit offset to GOT */\n+#define R_386_GOTPC\t   10\t\t/* 32 bit PC relative offset to GOT */\n+#define R_386_32PLT\t   11\n+#define R_386_TLS_TPOFF\t   14\t\t/* Offset in static TLS block */\n+#define R_386_TLS_IE\t   15\t\t/* Address of GOT entry for static TLS\n+\t\t\t\t\t   block offset */\n+#define R_386_TLS_GOTIE\t   16\t\t/* GOT entry for static TLS block\n+\t\t\t\t\t   offset */\n+#define R_386_TLS_LE\t   17\t\t/* Offset relative to static TLS\n+\t\t\t\t\t   block */\n+#define R_386_TLS_GD\t   18\t\t/* Direct 32 bit for GNU version of\n+\t\t\t\t\t   general dynamic thread local data */\n+#define R_386_TLS_LDM\t   19\t\t/* Direct 32 bit for GNU version of\n+\t\t\t\t\t   local dynamic thread local data\n+\t\t\t\t\t   in LE code */\n+#define R_386_16\t   20\n+#define R_386_PC16\t   21\n+#define R_386_8\t\t   22\n+#define R_386_PC8\t   23\n+#define R_386_TLS_GD_32\t   24\t\t/* Direct 32 bit for general dynamic\n+\t\t\t\t\t   thread local data */\n+#define R_386_TLS_GD_PUSH  25\t\t/* Tag for pushl in GD TLS code */\n+#define R_386_TLS_GD_CALL  26\t\t/* Relocation for call to\n+\t\t\t\t\t   __tls_get_addr() */\n+#define R_386_TLS_GD_POP   27\t\t/* Tag for popl in GD TLS code */\n+#define R_386_TLS_LDM_32   28\t\t/* Direct 32 bit for local dynamic\n+\t\t\t\t\t   thread local data in LE code */\n+#define R_386_TLS_LDM_PUSH 29\t\t/* Tag for pushl in LDM TLS code */\n+#define R_386_TLS_LDM_CALL 30\t\t/* Relocation for call to\n+\t\t\t\t\t   __tls_get_addr() in LDM code */\n+#define R_386_TLS_LDM_POP  31\t\t/* Tag for popl in LDM TLS code */\n+#define R_386_TLS_LDO_32   32\t\t/* Offset relative to TLS block */\n+#define R_386_TLS_IE_32\t   33\t\t/* GOT entry for negated static TLS\n+\t\t\t\t\t   block offset */\n+#define R_386_TLS_LE_32\t   34\t\t/* Negated offset relative to static\n+\t\t\t\t\t   TLS block */\n+#define R_386_TLS_DTPMOD32 35\t\t/* ID of module containing symbol */\n+#define R_386_TLS_DTPOFF32 36\t\t/* Offset in TLS block */\n+#define R_386_TLS_TPOFF32  37\t\t/* Negated offset in static TLS block */\n+/* 38? */\n+#define R_386_TLS_GOTDESC  39\t\t/* GOT offset for TLS descriptor.  */\n+#define R_386_TLS_DESC_CALL 40\t\t/* Marker of call through TLS\n+\t\t\t\t\t   descriptor for\n+\t\t\t\t\t   relaxation.  */\n+#define R_386_TLS_DESC     41\t\t/* TLS descriptor containing\n+\t\t\t\t\t   pointer to code and to\n+\t\t\t\t\t   argument, returning the TLS\n+\t\t\t\t\t   offset for the symbol.  */\n+#define R_386_IRELATIVE\t   42\t\t/* Adjust indirectly by program base */\n+/* Keep this the last entry.  */\n+#define R_386_NUM\t   43\n+\n+/* SUN SPARC specific definitions.  */\n+\n+/* Legal values for ST_TYPE subfield of st_info (symbol type).  */\n+\n+#define STT_SPARC_REGISTER\t13\t/* Global register reserved to app. */\n+\n+/* Values for Elf64_Ehdr.e_flags.  */\n+\n+#define EF_SPARCV9_MM\t\t3\n+#define EF_SPARCV9_TSO\t\t0\n+#define EF_SPARCV9_PSO\t\t1\n+#define EF_SPARCV9_RMO\t\t2\n+#define EF_SPARC_LEDATA\t\t0x800000 /* little endian data */\n+#define EF_SPARC_EXT_MASK\t0xFFFF00\n+#define EF_SPARC_32PLUS\t\t0x000100 /* generic V8+ features */\n+#define EF_SPARC_SUN_US1\t0x000200 /* Sun UltraSPARC1 extensions */\n+#define EF_SPARC_HAL_R1\t\t0x000400 /* HAL R1 extensions */\n+#define EF_SPARC_SUN_US3\t0x000800 /* Sun UltraSPARCIII extensions */\n+\n+/* SPARC relocs.  */\n+\n+#define R_SPARC_NONE\t\t0\t/* No reloc */\n+#define R_SPARC_8\t\t1\t/* Direct 8 bit */\n+#define R_SPARC_16\t\t2\t/* Direct 16 bit */\n+#define R_SPARC_32\t\t3\t/* Direct 32 bit */\n+#define R_SPARC_DISP8\t\t4\t/* PC relative 8 bit */\n+#define R_SPARC_DISP16\t\t5\t/* PC relative 16 bit */\n+#define R_SPARC_DISP32\t\t6\t/* PC relative 32 bit */\n+#define R_SPARC_WDISP30\t\t7\t/* PC relative 30 bit shifted */\n+#define R_SPARC_WDISP22\t\t8\t/* PC relative 22 bit shifted */\n+#define R_SPARC_HI22\t\t9\t/* High 22 bit */\n+#define R_SPARC_22\t\t10\t/* Direct 22 bit */\n+#define R_SPARC_13\t\t11\t/* Direct 13 bit */\n+#define R_SPARC_LO10\t\t12\t/* Truncated 10 bit */\n+#define R_SPARC_GOT10\t\t13\t/* Truncated 10 bit GOT entry */\n+#define R_SPARC_GOT13\t\t14\t/* 13 bit GOT entry */\n+#define R_SPARC_GOT22\t\t15\t/* 22 bit GOT entry shifted */\n+#define R_SPARC_PC10\t\t16\t/* PC relative 10 bit truncated */\n+#define R_SPARC_PC22\t\t17\t/* PC relative 22 bit shifted */\n+#define R_SPARC_WPLT30\t\t18\t/* 30 bit PC relative PLT address */\n+#define R_SPARC_COPY\t\t19\t/* Copy symbol at runtime */\n+#define R_SPARC_GLOB_DAT\t20\t/* Create GOT entry */\n+#define R_SPARC_JMP_SLOT\t21\t/* Create PLT entry */\n+#define R_SPARC_RELATIVE\t22\t/* Adjust by program base */\n+#define R_SPARC_UA32\t\t23\t/* Direct 32 bit unaligned */\n+\n+/* Additional Sparc64 relocs.  */\n+\n+#define R_SPARC_PLT32\t\t24\t/* Direct 32 bit ref to PLT entry */\n+#define R_SPARC_HIPLT22\t\t25\t/* High 22 bit PLT entry */\n+#define R_SPARC_LOPLT10\t\t26\t/* Truncated 10 bit PLT entry */\n+#define R_SPARC_PCPLT32\t\t27\t/* PC rel 32 bit ref to PLT entry */\n+#define R_SPARC_PCPLT22\t\t28\t/* PC rel high 22 bit PLT entry */\n+#define R_SPARC_PCPLT10\t\t29\t/* PC rel trunc 10 bit PLT entry */\n+#define R_SPARC_10\t\t30\t/* Direct 10 bit */\n+#define R_SPARC_11\t\t31\t/* Direct 11 bit */\n+#define R_SPARC_64\t\t32\t/* Direct 64 bit */\n+#define R_SPARC_OLO10\t\t33\t/* 10bit with secondary 13bit addend */\n+#define R_SPARC_HH22\t\t34\t/* Top 22 bits of direct 64 bit */\n+#define R_SPARC_HM10\t\t35\t/* High middle 10 bits of ... */\n+#define R_SPARC_LM22\t\t36\t/* Low middle 22 bits of ... */\n+#define R_SPARC_PC_HH22\t\t37\t/* Top 22 bits of pc rel 64 bit */\n+#define R_SPARC_PC_HM10\t\t38\t/* High middle 10 bit of ... */\n+#define R_SPARC_PC_LM22\t\t39\t/* Low miggle 22 bits of ... */\n+#define R_SPARC_WDISP16\t\t40\t/* PC relative 16 bit shifted */\n+#define R_SPARC_WDISP19\t\t41\t/* PC relative 19 bit shifted */\n+#define R_SPARC_GLOB_JMP\t42\t/* was part of v9 ABI but was removed */\n+#define R_SPARC_7\t\t43\t/* Direct 7 bit */\n+#define R_SPARC_5\t\t44\t/* Direct 5 bit */\n+#define R_SPARC_6\t\t45\t/* Direct 6 bit */\n+#define R_SPARC_DISP64\t\t46\t/* PC relative 64 bit */\n+#define R_SPARC_PLT64\t\t47\t/* Direct 64 bit ref to PLT entry */\n+#define R_SPARC_HIX22\t\t48\t/* High 22 bit complemented */\n+#define R_SPARC_LOX10\t\t49\t/* Truncated 11 bit complemented */\n+#define R_SPARC_H44\t\t50\t/* Direct high 12 of 44 bit */\n+#define R_SPARC_M44\t\t51\t/* Direct mid 22 of 44 bit */\n+#define R_SPARC_L44\t\t52\t/* Direct low 10 of 44 bit */\n+#define R_SPARC_REGISTER\t53\t/* Global register usage */\n+#define R_SPARC_UA64\t\t54\t/* Direct 64 bit unaligned */\n+#define R_SPARC_UA16\t\t55\t/* Direct 16 bit unaligned */\n+#define R_SPARC_TLS_GD_HI22\t56\n+#define R_SPARC_TLS_GD_LO10\t57\n+#define R_SPARC_TLS_GD_ADD\t58\n+#define R_SPARC_TLS_GD_CALL\t59\n+#define R_SPARC_TLS_LDM_HI22\t60\n+#define R_SPARC_TLS_LDM_LO10\t61\n+#define R_SPARC_TLS_LDM_ADD\t62\n+#define R_SPARC_TLS_LDM_CALL\t63\n+#define R_SPARC_TLS_LDO_HIX22\t64\n+#define R_SPARC_TLS_LDO_LOX10\t65\n+#define R_SPARC_TLS_LDO_ADD\t66\n+#define R_SPARC_TLS_IE_HI22\t67\n+#define R_SPARC_TLS_IE_LO10\t68\n+#define R_SPARC_TLS_IE_LD\t69\n+#define R_SPARC_TLS_IE_LDX\t70\n+#define R_SPARC_TLS_IE_ADD\t71\n+#define R_SPARC_TLS_LE_HIX22\t72\n+#define R_SPARC_TLS_LE_LOX10\t73\n+#define R_SPARC_TLS_DTPMOD32\t74\n+#define R_SPARC_TLS_DTPMOD64\t75\n+#define R_SPARC_TLS_DTPOFF32\t76\n+#define R_SPARC_TLS_DTPOFF64\t77\n+#define R_SPARC_TLS_TPOFF32\t78\n+#define R_SPARC_TLS_TPOFF64\t79\n+#define R_SPARC_GOTDATA_HIX22\t80\n+#define R_SPARC_GOTDATA_LOX10\t81\n+#define R_SPARC_GOTDATA_OP_HIX22\t82\n+#define R_SPARC_GOTDATA_OP_LOX10\t83\n+#define R_SPARC_GOTDATA_OP\t84\n+#define R_SPARC_H34\t\t85\n+#define R_SPARC_SIZE32\t\t86\n+#define R_SPARC_SIZE64\t\t87\n+#define R_SPARC_WDISP10\t\t88\n+#define R_SPARC_JMP_IREL\t248\n+#define R_SPARC_IRELATIVE\t249\n+#define R_SPARC_GNU_VTINHERIT\t250\n+#define R_SPARC_GNU_VTENTRY\t251\n+#define R_SPARC_REV32\t\t252\n+/* Keep this the last entry.  */\n+#define R_SPARC_NUM\t\t253\n+\n+/* For Sparc64, legal values for d_tag of Elf64_Dyn.  */\n+\n+#define DT_SPARC_REGISTER 0x70000001\n+#define DT_SPARC_NUM\t2\n+\n+/* MIPS R3000 specific definitions.  */\n+\n+/* Legal values for e_flags field of Elf32_Ehdr.  */\n+\n+#define EF_MIPS_NOREORDER   1\t\t/* A .noreorder directive was used */\n+#define EF_MIPS_PIC\t    2\t\t/* Contains PIC code */\n+#define EF_MIPS_CPIC\t    4\t\t/* Uses PIC calling sequence */\n+#define EF_MIPS_XGOT\t    8\n+#define EF_MIPS_64BIT_WHIRL 16\n+#define EF_MIPS_ABI2\t    32\n+#define EF_MIPS_ABI_ON32    64\n+#define EF_MIPS_ARCH\t    0xf0000000\t/* MIPS architecture level */\n+\n+/* Legal values for MIPS architecture level.  */\n+\n+#define EF_MIPS_ARCH_1\t    0x00000000\t/* -mips1 code.  */\n+#define EF_MIPS_ARCH_2\t    0x10000000\t/* -mips2 code.  */\n+#define EF_MIPS_ARCH_3\t    0x20000000\t/* -mips3 code.  */\n+#define EF_MIPS_ARCH_4\t    0x30000000\t/* -mips4 code.  */\n+#define EF_MIPS_ARCH_5\t    0x40000000\t/* -mips5 code.  */\n+#define EF_MIPS_ARCH_32\t    0x60000000\t/* MIPS32 code.  */\n+#define EF_MIPS_ARCH_64\t    0x70000000\t/* MIPS64 code.  */\n+\n+/* The following are non-official names and should not be used.  */\n+\n+#define E_MIPS_ARCH_1\t  0x00000000\t/* -mips1 code.  */\n+#define E_MIPS_ARCH_2\t  0x10000000\t/* -mips2 code.  */\n+#define E_MIPS_ARCH_3\t  0x20000000\t/* -mips3 code.  */\n+#define E_MIPS_ARCH_4\t  0x30000000\t/* -mips4 code.  */\n+#define E_MIPS_ARCH_5\t  0x40000000\t/* -mips5 code.  */\n+#define E_MIPS_ARCH_32\t  0x60000000\t/* MIPS32 code.  */\n+#define E_MIPS_ARCH_64\t  0x70000000\t/* MIPS64 code.  */\n+\n+/* Special section indices.  */\n+\n+#define SHN_MIPS_ACOMMON    0xff00\t/* Allocated common symbols */\n+#define SHN_MIPS_TEXT\t    0xff01\t/* Allocated test symbols.  */\n+#define SHN_MIPS_DATA\t    0xff02\t/* Allocated data symbols.  */\n+#define SHN_MIPS_SCOMMON    0xff03\t/* Small common symbols */\n+#define SHN_MIPS_SUNDEFINED 0xff04\t/* Small undefined symbols */\n+\n+/* Legal values for sh_type field of Elf32_Shdr.  */\n+\n+#define SHT_MIPS_LIBLIST       0x70000000 /* Shared objects used in link */\n+#define SHT_MIPS_MSYM\t       0x70000001\n+#define SHT_MIPS_CONFLICT      0x70000002 /* Conflicting symbols */\n+#define SHT_MIPS_GPTAB\t       0x70000003 /* Global data area sizes */\n+#define SHT_MIPS_UCODE\t       0x70000004 /* Reserved for SGI/MIPS compilers */\n+#define SHT_MIPS_DEBUG\t       0x70000005 /* MIPS ECOFF debugging information*/\n+#define SHT_MIPS_REGINFO       0x70000006 /* Register usage information */\n+#define SHT_MIPS_PACKAGE       0x70000007\n+#define SHT_MIPS_PACKSYM       0x70000008\n+#define SHT_MIPS_RELD\t       0x70000009\n+#define SHT_MIPS_IFACE         0x7000000b\n+#define SHT_MIPS_CONTENT       0x7000000c\n+#define SHT_MIPS_OPTIONS       0x7000000d /* Miscellaneous options.  */\n+#define SHT_MIPS_SHDR\t       0x70000010\n+#define SHT_MIPS_FDESC\t       0x70000011\n+#define SHT_MIPS_EXTSYM\t       0x70000012\n+#define SHT_MIPS_DENSE\t       0x70000013\n+#define SHT_MIPS_PDESC\t       0x70000014\n+#define SHT_MIPS_LOCSYM\t       0x70000015\n+#define SHT_MIPS_AUXSYM\t       0x70000016\n+#define SHT_MIPS_OPTSYM\t       0x70000017\n+#define SHT_MIPS_LOCSTR\t       0x70000018\n+#define SHT_MIPS_LINE\t       0x70000019\n+#define SHT_MIPS_RFDESC\t       0x7000001a\n+#define SHT_MIPS_DELTASYM      0x7000001b\n+#define SHT_MIPS_DELTAINST     0x7000001c\n+#define SHT_MIPS_DELTACLASS    0x7000001d\n+#define SHT_MIPS_DWARF         0x7000001e /* DWARF debugging information.  */\n+#define SHT_MIPS_DELTADECL     0x7000001f\n+#define SHT_MIPS_SYMBOL_LIB    0x70000020\n+#define SHT_MIPS_EVENTS\t       0x70000021 /* Event section.  */\n+#define SHT_MIPS_TRANSLATE     0x70000022\n+#define SHT_MIPS_PIXIE\t       0x70000023\n+#define SHT_MIPS_XLATE\t       0x70000024\n+#define SHT_MIPS_XLATE_DEBUG   0x70000025\n+#define SHT_MIPS_WHIRL\t       0x70000026\n+#define SHT_MIPS_EH_REGION     0x70000027\n+#define SHT_MIPS_XLATE_OLD     0x70000028\n+#define SHT_MIPS_PDR_EXCEPTION 0x70000029\n+\n+/* Legal values for sh_flags field of Elf32_Shdr.  */\n+\n+#define SHF_MIPS_GPREL\t 0x10000000\t/* Must be part of global data area */\n+#define SHF_MIPS_MERGE\t 0x20000000\n+#define SHF_MIPS_ADDR\t 0x40000000\n+#define SHF_MIPS_STRINGS 0x80000000\n+#define SHF_MIPS_NOSTRIP 0x08000000\n+#define SHF_MIPS_LOCAL\t 0x04000000\n+#define SHF_MIPS_NAMES\t 0x02000000\n+#define SHF_MIPS_NODUPE\t 0x01000000\n+\n+\n+/* Symbol tables.  */\n+\n+/* MIPS specific values for `st_other'.  */\n+#define STO_MIPS_DEFAULT\t\t0x0\n+#define STO_MIPS_INTERNAL\t\t0x1\n+#define STO_MIPS_HIDDEN\t\t\t0x2\n+#define STO_MIPS_PROTECTED\t\t0x3\n+#define STO_MIPS_PLT\t\t\t0x8\n+#define STO_MIPS_SC_ALIGN_UNUSED\t0xff\n+\n+/* MIPS specific values for `st_info'.  */\n+#define STB_MIPS_SPLIT_COMMON\t\t13\n+\n+/* Entries found in sections of type SHT_MIPS_GPTAB.  */\n+\n+typedef union\n+{\n+  struct\n+    {\n+      Elf32_Word gt_current_g_value;\t/* -G value used for compilation */\n+      Elf32_Word gt_unused;\t\t/* Not used */\n+    } gt_header;\t\t\t/* First entry in section */\n+  struct\n+    {\n+      Elf32_Word gt_g_value;\t\t/* If this value were used for -G */\n+      Elf32_Word gt_bytes;\t\t/* This many bytes would be used */\n+    } gt_entry;\t\t\t\t/* Subsequent entries in section */\n+} Elf32_gptab;\n+\n+/* Entry found in sections of type SHT_MIPS_REGINFO.  */\n+\n+typedef struct\n+{\n+  Elf32_Word\tri_gprmask;\t\t/* General registers used */\n+  Elf32_Word\tri_cprmask[4];\t\t/* Coprocessor registers used */\n+  Elf32_Sword\tri_gp_value;\t\t/* $gp register value */\n+} Elf32_RegInfo;\n+\n+/* Entries found in sections of type SHT_MIPS_OPTIONS.  */\n+\n+typedef struct\n+{\n+  unsigned char kind;\t\t/* Determines interpretation of the\n+\t\t\t\t   variable part of descriptor.  */\n+  unsigned char size;\t\t/* Size of descriptor, including header.  */\n+  Elf32_Section section;\t/* Section header index of section affected,\n+\t\t\t\t   0 for global options.  */\n+  Elf32_Word info;\t\t/* Kind-specific information.  */\n+} Elf_Options;\n+\n+/* Values for `kind' field in Elf_Options.  */\n+\n+#define ODK_NULL\t0\t/* Undefined.  */\n+#define ODK_REGINFO\t1\t/* Register usage information.  */\n+#define ODK_EXCEPTIONS\t2\t/* Exception processing options.  */\n+#define ODK_PAD\t\t3\t/* Section padding options.  */\n+#define ODK_HWPATCH\t4\t/* Hardware workarounds performed */\n+#define ODK_FILL\t5\t/* record the fill value used by the linker. */\n+#define ODK_TAGS\t6\t/* reserve space for desktop tools to write. */\n+#define ODK_HWAND\t7\t/* HW workarounds.  'AND' bits when merging. */\n+#define ODK_HWOR\t8\t/* HW workarounds.  'OR' bits when merging.  */\n+\n+/* Values for `info' in Elf_Options for ODK_EXCEPTIONS entries.  */\n+\n+#define OEX_FPU_MIN\t0x1f\t/* FPE's which MUST be enabled.  */\n+#define OEX_FPU_MAX\t0x1f00\t/* FPE's which MAY be enabled.  */\n+#define OEX_PAGE0\t0x10000\t/* page zero must be mapped.  */\n+#define OEX_SMM\t\t0x20000\t/* Force sequential memory mode?  */\n+#define OEX_FPDBUG\t0x40000\t/* Force floating point debug mode?  */\n+#define OEX_PRECISEFP\tOEX_FPDBUG\n+#define OEX_DISMISS\t0x80000\t/* Dismiss invalid address faults?  */\n+\n+#define OEX_FPU_INVAL\t0x10\n+#define OEX_FPU_DIV0\t0x08\n+#define OEX_FPU_OFLO\t0x04\n+#define OEX_FPU_UFLO\t0x02\n+#define OEX_FPU_INEX\t0x01\n+\n+/* Masks for `info' in Elf_Options for an ODK_HWPATCH entry.  */\n+\n+#define OHW_R4KEOP\t0x1\t/* R4000 end-of-page patch.  */\n+#define OHW_R8KPFETCH\t0x2\t/* may need R8000 prefetch patch.  */\n+#define OHW_R5KEOP\t0x4\t/* R5000 end-of-page patch.  */\n+#define OHW_R5KCVTL\t0x8\t/* R5000 cvt.[ds].l bug.  clean=1.  */\n+\n+#define OPAD_PREFIX\t0x1\n+#define OPAD_POSTFIX\t0x2\n+#define OPAD_SYMBOL\t0x4\n+\n+/* Entry found in `.options' section.  */\n+\n+typedef struct\n+{\n+  Elf32_Word hwp_flags1;\t/* Extra flags.  */\n+  Elf32_Word hwp_flags2;\t/* Extra flags.  */\n+} Elf_Options_Hw;\n+\n+/* Masks for `info' in ElfOptions for ODK_HWAND and ODK_HWOR entries.  */\n+\n+#define OHWA0_R4KEOP_CHECKED\t0x00000001\n+#define OHWA1_R4KEOP_CLEAN\t0x00000002\n+\n+/* MIPS relocs.  */\n+\n+#define R_MIPS_NONE\t\t0\t/* No reloc */\n+#define R_MIPS_16\t\t1\t/* Direct 16 bit */\n+#define R_MIPS_32\t\t2\t/* Direct 32 bit */\n+#define R_MIPS_REL32\t\t3\t/* PC relative 32 bit */\n+#define R_MIPS_26\t\t4\t/* Direct 26 bit shifted */\n+#define R_MIPS_HI16\t\t5\t/* High 16 bit */\n+#define R_MIPS_LO16\t\t6\t/* Low 16 bit */\n+#define R_MIPS_GPREL16\t\t7\t/* GP relative 16 bit */\n+#define R_MIPS_LITERAL\t\t8\t/* 16 bit literal entry */\n+#define R_MIPS_GOT16\t\t9\t/* 16 bit GOT entry */\n+#define R_MIPS_PC16\t\t10\t/* PC relative 16 bit */\n+#define R_MIPS_CALL16\t\t11\t/* 16 bit GOT entry for function */\n+#define R_MIPS_GPREL32\t\t12\t/* GP relative 32 bit */\n+\n+#define R_MIPS_SHIFT5\t\t16\n+#define R_MIPS_SHIFT6\t\t17\n+#define R_MIPS_64\t\t18\n+#define R_MIPS_GOT_DISP\t\t19\n+#define R_MIPS_GOT_PAGE\t\t20\n+#define R_MIPS_GOT_OFST\t\t21\n+#define R_MIPS_GOT_HI16\t\t22\n+#define R_MIPS_GOT_LO16\t\t23\n+#define R_MIPS_SUB\t\t24\n+#define R_MIPS_INSERT_A\t\t25\n+#define R_MIPS_INSERT_B\t\t26\n+#define R_MIPS_DELETE\t\t27\n+#define R_MIPS_HIGHER\t\t28\n+#define R_MIPS_HIGHEST\t\t29\n+#define R_MIPS_CALL_HI16\t30\n+#define R_MIPS_CALL_LO16\t31\n+#define R_MIPS_SCN_DISP\t\t32\n+#define R_MIPS_REL16\t\t33\n+#define R_MIPS_ADD_IMMEDIATE\t34\n+#define R_MIPS_PJUMP\t\t35\n+#define R_MIPS_RELGOT\t\t36\n+#define R_MIPS_JALR\t\t37\n+#define R_MIPS_TLS_DTPMOD32\t38\t/* Module number 32 bit */\n+#define R_MIPS_TLS_DTPREL32\t39\t/* Module-relative offset 32 bit */\n+#define R_MIPS_TLS_DTPMOD64\t40\t/* Module number 64 bit */\n+#define R_MIPS_TLS_DTPREL64\t41\t/* Module-relative offset 64 bit */\n+#define R_MIPS_TLS_GD\t\t42\t/* 16 bit GOT offset for GD */\n+#define R_MIPS_TLS_LDM\t\t43\t/* 16 bit GOT offset for LDM */\n+#define R_MIPS_TLS_DTPREL_HI16\t44\t/* Module-relative offset, high 16 bits */\n+#define R_MIPS_TLS_DTPREL_LO16\t45\t/* Module-relative offset, low 16 bits */\n+#define R_MIPS_TLS_GOTTPREL\t46\t/* 16 bit GOT offset for IE */\n+#define R_MIPS_TLS_TPREL32\t47\t/* TP-relative offset, 32 bit */\n+#define R_MIPS_TLS_TPREL64\t48\t/* TP-relative offset, 64 bit */\n+#define R_MIPS_TLS_TPREL_HI16\t49\t/* TP-relative offset, high 16 bits */\n+#define R_MIPS_TLS_TPREL_LO16\t50\t/* TP-relative offset, low 16 bits */\n+#define R_MIPS_GLOB_DAT\t\t51\n+#define R_MIPS_COPY\t\t126\n+#define R_MIPS_JUMP_SLOT        127\n+/* Keep this the last entry.  */\n+#define R_MIPS_NUM\t\t128\n+\n+/* Legal values for p_type field of Elf32_Phdr.  */\n+\n+#define PT_MIPS_REGINFO\t0x70000000\t/* Register usage information */\n+#define PT_MIPS_RTPROC  0x70000001\t/* Runtime procedure table. */\n+#define PT_MIPS_OPTIONS 0x70000002\n+\n+/* Special program header types.  */\n+\n+#define PF_MIPS_LOCAL\t0x10000000\n+\n+/* Legal values for d_tag field of Elf32_Dyn.  */\n+\n+#define DT_MIPS_RLD_VERSION  0x70000001\t/* Runtime linker interface version */\n+#define DT_MIPS_TIME_STAMP   0x70000002\t/* Timestamp */\n+#define DT_MIPS_ICHECKSUM    0x70000003\t/* Checksum */\n+#define DT_MIPS_IVERSION     0x70000004\t/* Version string (string tbl index) */\n+#define DT_MIPS_FLAGS\t     0x70000005\t/* Flags */\n+#define DT_MIPS_BASE_ADDRESS 0x70000006\t/* Base address */\n+#define DT_MIPS_MSYM\t     0x70000007\n+#define DT_MIPS_CONFLICT     0x70000008\t/* Address of CONFLICT section */\n+#define DT_MIPS_LIBLIST\t     0x70000009\t/* Address of LIBLIST section */\n+#define DT_MIPS_LOCAL_GOTNO  0x7000000a\t/* Number of local GOT entries */\n+#define DT_MIPS_CONFLICTNO   0x7000000b\t/* Number of CONFLICT entries */\n+#define DT_MIPS_LIBLISTNO    0x70000010\t/* Number of LIBLIST entries */\n+#define DT_MIPS_SYMTABNO     0x70000011\t/* Number of DYNSYM entries */\n+#define DT_MIPS_UNREFEXTNO   0x70000012\t/* First external DYNSYM */\n+#define DT_MIPS_GOTSYM\t     0x70000013\t/* First GOT entry in DYNSYM */\n+#define DT_MIPS_HIPAGENO     0x70000014\t/* Number of GOT page table entries */\n+#define DT_MIPS_RLD_MAP\t     0x70000016\t/* Address of run time loader map.  */\n+#define DT_MIPS_DELTA_CLASS  0x70000017\t/* Delta C++ class definition.  */\n+#define DT_MIPS_DELTA_CLASS_NO    0x70000018 /* Number of entries in\n+\t\t\t\t\t\tDT_MIPS_DELTA_CLASS.  */\n+#define DT_MIPS_DELTA_INSTANCE    0x70000019 /* Delta C++ class instances.  */\n+#define DT_MIPS_DELTA_INSTANCE_NO 0x7000001a /* Number of entries in\n+\t\t\t\t\t\tDT_MIPS_DELTA_INSTANCE.  */\n+#define DT_MIPS_DELTA_RELOC  0x7000001b /* Delta relocations.  */\n+#define DT_MIPS_DELTA_RELOC_NO 0x7000001c /* Number of entries in\n+\t\t\t\t\t     DT_MIPS_DELTA_RELOC.  */\n+#define DT_MIPS_DELTA_SYM    0x7000001d /* Delta symbols that Delta\n+\t\t\t\t\t   relocations refer to.  */\n+#define DT_MIPS_DELTA_SYM_NO 0x7000001e /* Number of entries in\n+\t\t\t\t\t   DT_MIPS_DELTA_SYM.  */\n+#define DT_MIPS_DELTA_CLASSSYM 0x70000020 /* Delta symbols that hold the\n+\t\t\t\t\t     class declaration.  */\n+#define DT_MIPS_DELTA_CLASSSYM_NO 0x70000021 /* Number of entries in\n+\t\t\t\t\t\tDT_MIPS_DELTA_CLASSSYM.  */\n+#define DT_MIPS_CXX_FLAGS    0x70000022 /* Flags indicating for C++ flavor.  */\n+#define DT_MIPS_PIXIE_INIT   0x70000023\n+#define DT_MIPS_SYMBOL_LIB   0x70000024\n+#define DT_MIPS_LOCALPAGE_GOTIDX 0x70000025\n+#define DT_MIPS_LOCAL_GOTIDX 0x70000026\n+#define DT_MIPS_HIDDEN_GOTIDX 0x70000027\n+#define DT_MIPS_PROTECTED_GOTIDX 0x70000028\n+#define DT_MIPS_OPTIONS\t     0x70000029 /* Address of .options.  */\n+#define DT_MIPS_INTERFACE    0x7000002a /* Address of .interface.  */\n+#define DT_MIPS_DYNSTR_ALIGN 0x7000002b\n+#define DT_MIPS_INTERFACE_SIZE 0x7000002c /* Size of the .interface section. */\n+#define DT_MIPS_RLD_TEXT_RESOLVE_ADDR 0x7000002d /* Address of rld_text_rsolve\n+\t\t\t\t\t\t    function stored in GOT.  */\n+#define DT_MIPS_PERF_SUFFIX  0x7000002e /* Default suffix of dso to be added\n+\t\t\t\t\t   by rld on dlopen() calls.  */\n+#define DT_MIPS_COMPACT_SIZE 0x7000002f /* (O32)Size of compact rel section. */\n+#define DT_MIPS_GP_VALUE     0x70000030 /* GP value for aux GOTs.  */\n+#define DT_MIPS_AUX_DYNAMIC  0x70000031 /* Address of aux .dynamic.  */\n+/* The address of .got.plt in an executable using the new non-PIC ABI.  */\n+#define DT_MIPS_PLTGOT\t     0x70000032\n+/* The base of the PLT in an executable using the new non-PIC ABI if that\n+   PLT is writable.  For a non-writable PLT, this is omitted or has a zero\n+   value.  */\n+#define DT_MIPS_RWPLT        0x70000034\n+#define DT_MIPS_NUM\t     0x35\n+\n+/* Legal values for DT_MIPS_FLAGS Elf32_Dyn entry.  */\n+\n+#define RHF_NONE\t\t   0\t\t/* No flags */\n+#define RHF_QUICKSTART\t\t   (1 << 0)\t/* Use quickstart */\n+#define RHF_NOTPOT\t\t   (1 << 1)\t/* Hash size not power of 2 */\n+#define RHF_NO_LIBRARY_REPLACEMENT (1 << 2)\t/* Ignore LD_LIBRARY_PATH */\n+#define RHF_NO_MOVE\t\t   (1 << 3)\n+#define RHF_SGI_ONLY\t\t   (1 << 4)\n+#define RHF_GUARANTEE_INIT\t   (1 << 5)\n+#define RHF_DELTA_C_PLUS_PLUS\t   (1 << 6)\n+#define RHF_GUARANTEE_START_INIT   (1 << 7)\n+#define RHF_PIXIE\t\t   (1 << 8)\n+#define RHF_DEFAULT_DELAY_LOAD\t   (1 << 9)\n+#define RHF_REQUICKSTART\t   (1 << 10)\n+#define RHF_REQUICKSTARTED\t   (1 << 11)\n+#define RHF_CORD\t\t   (1 << 12)\n+#define RHF_NO_UNRES_UNDEF\t   (1 << 13)\n+#define RHF_RLD_ORDER_SAFE\t   (1 << 14)\n+\n+/* Entries found in sections of type SHT_MIPS_LIBLIST.  */\n+\n+typedef struct\n+{\n+  Elf32_Word l_name;\t\t/* Name (string table index) */\n+  Elf32_Word l_time_stamp;\t/* Timestamp */\n+  Elf32_Word l_checksum;\t/* Checksum */\n+  Elf32_Word l_version;\t\t/* Interface version */\n+  Elf32_Word l_flags;\t\t/* Flags */\n+} Elf32_Lib;\n+\n+typedef struct\n+{\n+  Elf64_Word l_name;\t\t/* Name (string table index) */\n+  Elf64_Word l_time_stamp;\t/* Timestamp */\n+  Elf64_Word l_checksum;\t/* Checksum */\n+  Elf64_Word l_version;\t\t/* Interface version */\n+  Elf64_Word l_flags;\t\t/* Flags */\n+} Elf64_Lib;\n+\n+\n+/* Legal values for l_flags.  */\n+\n+#define LL_NONE\t\t  0\n+#define LL_EXACT_MATCH\t  (1 << 0)\t/* Require exact match */\n+#define LL_IGNORE_INT_VER (1 << 1)\t/* Ignore interface version */\n+#define LL_REQUIRE_MINOR  (1 << 2)\n+#define LL_EXPORTS\t  (1 << 3)\n+#define LL_DELAY_LOAD\t  (1 << 4)\n+#define LL_DELTA\t  (1 << 5)\n+\n+/* Entries found in sections of type SHT_MIPS_CONFLICT.  */\n+\n+typedef Elf32_Addr Elf32_Conflict;\n+\n+\n+/* HPPA specific definitions.  */\n+\n+/* Legal values for e_flags field of Elf32_Ehdr.  */\n+\n+#define EF_PARISC_TRAPNIL\t0x00010000 /* Trap nil pointer dereference.  */\n+#define EF_PARISC_EXT\t\t0x00020000 /* Program uses arch. extensions. */\n+#define EF_PARISC_LSB\t\t0x00040000 /* Program expects little endian. */\n+#define EF_PARISC_WIDE\t\t0x00080000 /* Program expects wide mode.  */\n+#define EF_PARISC_NO_KABP\t0x00100000 /* No kernel assisted branch\n+\t\t\t\t\t      prediction.  */\n+#define EF_PARISC_LAZYSWAP\t0x00400000 /* Allow lazy swapping.  */\n+#define EF_PARISC_ARCH\t\t0x0000ffff /* Architecture version.  */\n+\n+/* Defined values for `e_flags & EF_PARISC_ARCH' are:  */\n+\n+#define EFA_PARISC_1_0\t\t    0x020b /* PA-RISC 1.0 big-endian.  */\n+#define EFA_PARISC_1_1\t\t    0x0210 /* PA-RISC 1.1 big-endian.  */\n+#define EFA_PARISC_2_0\t\t    0x0214 /* PA-RISC 2.0 big-endian.  */\n+\n+/* Additional section indeces.  */\n+\n+#define SHN_PARISC_ANSI_COMMON\t0xff00\t   /* Section for tenatively declared\n+\t\t\t\t\t      symbols in ANSI C.  */\n+#define SHN_PARISC_HUGE_COMMON\t0xff01\t   /* Common blocks in huge model.  */\n+\n+/* Legal values for sh_type field of Elf32_Shdr.  */\n+\n+#define SHT_PARISC_EXT\t\t0x70000000 /* Contains product specific ext. */\n+#define SHT_PARISC_UNWIND\t0x70000001 /* Unwind information.  */\n+#define SHT_PARISC_DOC\t\t0x70000002 /* Debug info for optimized code. */\n+\n+/* Legal values for sh_flags field of Elf32_Shdr.  */\n+\n+#define SHF_PARISC_SHORT\t0x20000000 /* Section with short addressing. */\n+#define SHF_PARISC_HUGE\t\t0x40000000 /* Section far from gp.  */\n+#define SHF_PARISC_SBP\t\t0x80000000 /* Static branch prediction code. */\n+\n+/* Legal values for ST_TYPE subfield of st_info (symbol type).  */\n+\n+#define STT_PARISC_MILLICODE\t13\t/* Millicode function entry point.  */\n+\n+#define STT_HP_OPAQUE\t\t(STT_LOOS + 0x1)\n+#define STT_HP_STUB\t\t(STT_LOOS + 0x2)\n+\n+/* HPPA relocs.  */\n+\n+#define R_PARISC_NONE\t\t0\t/* No reloc.  */\n+#define R_PARISC_DIR32\t\t1\t/* Direct 32-bit reference.  */\n+#define R_PARISC_DIR21L\t\t2\t/* Left 21 bits of eff. address.  */\n+#define R_PARISC_DIR17R\t\t3\t/* Right 17 bits of eff. address.  */\n+#define R_PARISC_DIR17F\t\t4\t/* 17 bits of eff. address.  */\n+#define R_PARISC_DIR14R\t\t6\t/* Right 14 bits of eff. address.  */\n+#define R_PARISC_PCREL32\t9\t/* 32-bit rel. address.  */\n+#define R_PARISC_PCREL21L\t10\t/* Left 21 bits of rel. address.  */\n+#define R_PARISC_PCREL17R\t11\t/* Right 17 bits of rel. address.  */\n+#define R_PARISC_PCREL17F\t12\t/* 17 bits of rel. address.  */\n+#define R_PARISC_PCREL14R\t14\t/* Right 14 bits of rel. address.  */\n+#define R_PARISC_DPREL21L\t18\t/* Left 21 bits of rel. address.  */\n+#define R_PARISC_DPREL14R\t22\t/* Right 14 bits of rel. address.  */\n+#define R_PARISC_GPREL21L\t26\t/* GP-relative, left 21 bits.  */\n+#define R_PARISC_GPREL14R\t30\t/* GP-relative, right 14 bits.  */\n+#define R_PARISC_LTOFF21L\t34\t/* LT-relative, left 21 bits.  */\n+#define R_PARISC_LTOFF14R\t38\t/* LT-relative, right 14 bits.  */\n+#define R_PARISC_SECREL32\t41\t/* 32 bits section rel. address.  */\n+#define R_PARISC_SEGBASE\t48\t/* No relocation, set segment base.  */\n+#define R_PARISC_SEGREL32\t49\t/* 32 bits segment rel. address.  */\n+#define R_PARISC_PLTOFF21L\t50\t/* PLT rel. address, left 21 bits.  */\n+#define R_PARISC_PLTOFF14R\t54\t/* PLT rel. address, right 14 bits.  */\n+#define R_PARISC_LTOFF_FPTR32\t57\t/* 32 bits LT-rel. function pointer. */\n+#define R_PARISC_LTOFF_FPTR21L\t58\t/* LT-rel. fct ptr, left 21 bits. */\n+#define R_PARISC_LTOFF_FPTR14R\t62\t/* LT-rel. fct ptr, right 14 bits. */\n+#define R_PARISC_FPTR64\t\t64\t/* 64 bits function address.  */\n+#define R_PARISC_PLABEL32\t65\t/* 32 bits function address.  */\n+#define R_PARISC_PLABEL21L\t66\t/* Left 21 bits of fdesc address.  */\n+#define R_PARISC_PLABEL14R\t70\t/* Right 14 bits of fdesc address.  */\n+#define R_PARISC_PCREL64\t72\t/* 64 bits PC-rel. address.  */\n+#define R_PARISC_PCREL22F\t74\t/* 22 bits PC-rel. address.  */\n+#define R_PARISC_PCREL14WR\t75\t/* PC-rel. address, right 14 bits.  */\n+#define R_PARISC_PCREL14DR\t76\t/* PC rel. address, right 14 bits.  */\n+#define R_PARISC_PCREL16F\t77\t/* 16 bits PC-rel. address.  */\n+#define R_PARISC_PCREL16WF\t78\t/* 16 bits PC-rel. address.  */\n+#define R_PARISC_PCREL16DF\t79\t/* 16 bits PC-rel. address.  */\n+#define R_PARISC_DIR64\t\t80\t/* 64 bits of eff. address.  */\n+#define R_PARISC_DIR14WR\t83\t/* 14 bits of eff. address.  */\n+#define R_PARISC_DIR14DR\t84\t/* 14 bits of eff. address.  */\n+#define R_PARISC_DIR16F\t\t85\t/* 16 bits of eff. address.  */\n+#define R_PARISC_DIR16WF\t86\t/* 16 bits of eff. address.  */\n+#define R_PARISC_DIR16DF\t87\t/* 16 bits of eff. address.  */\n+#define R_PARISC_GPREL64\t88\t/* 64 bits of GP-rel. address.  */\n+#define R_PARISC_GPREL14WR\t91\t/* GP-rel. address, right 14 bits.  */\n+#define R_PARISC_GPREL14DR\t92\t/* GP-rel. address, right 14 bits.  */\n+#define R_PARISC_GPREL16F\t93\t/* 16 bits GP-rel. address.  */\n+#define R_PARISC_GPREL16WF\t94\t/* 16 bits GP-rel. address.  */\n+#define R_PARISC_GPREL16DF\t95\t/* 16 bits GP-rel. address.  */\n+#define R_PARISC_LTOFF64\t96\t/* 64 bits LT-rel. address.  */\n+#define R_PARISC_LTOFF14WR\t99\t/* LT-rel. address, right 14 bits.  */\n+#define R_PARISC_LTOFF14DR\t100\t/* LT-rel. address, right 14 bits.  */\n+#define R_PARISC_LTOFF16F\t101\t/* 16 bits LT-rel. address.  */\n+#define R_PARISC_LTOFF16WF\t102\t/* 16 bits LT-rel. address.  */\n+#define R_PARISC_LTOFF16DF\t103\t/* 16 bits LT-rel. address.  */\n+#define R_PARISC_SECREL64\t104\t/* 64 bits section rel. address.  */\n+#define R_PARISC_SEGREL64\t112\t/* 64 bits segment rel. address.  */\n+#define R_PARISC_PLTOFF14WR\t115\t/* PLT-rel. address, right 14 bits.  */\n+#define R_PARISC_PLTOFF14DR\t116\t/* PLT-rel. address, right 14 bits.  */\n+#define R_PARISC_PLTOFF16F\t117\t/* 16 bits LT-rel. address.  */\n+#define R_PARISC_PLTOFF16WF\t118\t/* 16 bits PLT-rel. address.  */\n+#define R_PARISC_PLTOFF16DF\t119\t/* 16 bits PLT-rel. address.  */\n+#define R_PARISC_LTOFF_FPTR64\t120\t/* 64 bits LT-rel. function ptr.  */\n+#define R_PARISC_LTOFF_FPTR14WR\t123\t/* LT-rel. fct. ptr., right 14 bits. */\n+#define R_PARISC_LTOFF_FPTR14DR\t124\t/* LT-rel. fct. ptr., right 14 bits. */\n+#define R_PARISC_LTOFF_FPTR16F\t125\t/* 16 bits LT-rel. function ptr.  */\n+#define R_PARISC_LTOFF_FPTR16WF\t126\t/* 16 bits LT-rel. function ptr.  */\n+#define R_PARISC_LTOFF_FPTR16DF\t127\t/* 16 bits LT-rel. function ptr.  */\n+#define R_PARISC_LORESERVE\t128\n+#define R_PARISC_COPY\t\t128\t/* Copy relocation.  */\n+#define R_PARISC_IPLT\t\t129\t/* Dynamic reloc, imported PLT */\n+#define R_PARISC_EPLT\t\t130\t/* Dynamic reloc, exported PLT */\n+#define R_PARISC_TPREL32\t153\t/* 32 bits TP-rel. address.  */\n+#define R_PARISC_TPREL21L\t154\t/* TP-rel. address, left 21 bits.  */\n+#define R_PARISC_TPREL14R\t158\t/* TP-rel. address, right 14 bits.  */\n+#define R_PARISC_LTOFF_TP21L\t162\t/* LT-TP-rel. address, left 21 bits. */\n+#define R_PARISC_LTOFF_TP14R\t166\t/* LT-TP-rel. address, right 14 bits.*/\n+#define R_PARISC_LTOFF_TP14F\t167\t/* 14 bits LT-TP-rel. address.  */\n+#define R_PARISC_TPREL64\t216\t/* 64 bits TP-rel. address.  */\n+#define R_PARISC_TPREL14WR\t219\t/* TP-rel. address, right 14 bits.  */\n+#define R_PARISC_TPREL14DR\t220\t/* TP-rel. address, right 14 bits.  */\n+#define R_PARISC_TPREL16F\t221\t/* 16 bits TP-rel. address.  */\n+#define R_PARISC_TPREL16WF\t222\t/* 16 bits TP-rel. address.  */\n+#define R_PARISC_TPREL16DF\t223\t/* 16 bits TP-rel. address.  */\n+#define R_PARISC_LTOFF_TP64\t224\t/* 64 bits LT-TP-rel. address.  */\n+#define R_PARISC_LTOFF_TP14WR\t227\t/* LT-TP-rel. address, right 14 bits.*/\n+#define R_PARISC_LTOFF_TP14DR\t228\t/* LT-TP-rel. address, right 14 bits.*/\n+#define R_PARISC_LTOFF_TP16F\t229\t/* 16 bits LT-TP-rel. address.  */\n+#define R_PARISC_LTOFF_TP16WF\t230\t/* 16 bits LT-TP-rel. address.  */\n+#define R_PARISC_LTOFF_TP16DF\t231\t/* 16 bits LT-TP-rel. address.  */\n+#define R_PARISC_GNU_VTENTRY\t232\n+#define R_PARISC_GNU_VTINHERIT\t233\n+#define R_PARISC_TLS_GD21L\t234\t/* GD 21-bit left.  */\n+#define R_PARISC_TLS_GD14R\t235\t/* GD 14-bit right.  */\n+#define R_PARISC_TLS_GDCALL\t236\t/* GD call to __t_g_a.  */\n+#define R_PARISC_TLS_LDM21L\t237\t/* LD module 21-bit left.  */\n+#define R_PARISC_TLS_LDM14R\t238\t/* LD module 14-bit right.  */\n+#define R_PARISC_TLS_LDMCALL\t239\t/* LD module call to __t_g_a.  */\n+#define R_PARISC_TLS_LDO21L\t240\t/* LD offset 21-bit left.  */\n+#define R_PARISC_TLS_LDO14R\t241\t/* LD offset 14-bit right.  */\n+#define R_PARISC_TLS_DTPMOD32\t242\t/* DTP module 32-bit.  */\n+#define R_PARISC_TLS_DTPMOD64\t243\t/* DTP module 64-bit.  */\n+#define R_PARISC_TLS_DTPOFF32\t244\t/* DTP offset 32-bit.  */\n+#define R_PARISC_TLS_DTPOFF64\t245\t/* DTP offset 32-bit.  */\n+#define R_PARISC_TLS_LE21L\tR_PARISC_TPREL21L\n+#define R_PARISC_TLS_LE14R\tR_PARISC_TPREL14R\n+#define R_PARISC_TLS_IE21L\tR_PARISC_LTOFF_TP21L\n+#define R_PARISC_TLS_IE14R\tR_PARISC_LTOFF_TP14R\n+#define R_PARISC_TLS_TPREL32\tR_PARISC_TPREL32\n+#define R_PARISC_TLS_TPREL64\tR_PARISC_TPREL64\n+#define R_PARISC_HIRESERVE\t255\n+\n+/* Legal values for p_type field of Elf32_Phdr/Elf64_Phdr.  */\n+\n+#define PT_HP_TLS\t\t(PT_LOOS + 0x0)\n+#define PT_HP_CORE_NONE\t\t(PT_LOOS + 0x1)\n+#define PT_HP_CORE_VERSION\t(PT_LOOS + 0x2)\n+#define PT_HP_CORE_KERNEL\t(PT_LOOS + 0x3)\n+#define PT_HP_CORE_COMM\t\t(PT_LOOS + 0x4)\n+#define PT_HP_CORE_PROC\t\t(PT_LOOS + 0x5)\n+#define PT_HP_CORE_LOADABLE\t(PT_LOOS + 0x6)\n+#define PT_HP_CORE_STACK\t(PT_LOOS + 0x7)\n+#define PT_HP_CORE_SHM\t\t(PT_LOOS + 0x8)\n+#define PT_HP_CORE_MMF\t\t(PT_LOOS + 0x9)\n+#define PT_HP_PARALLEL\t\t(PT_LOOS + 0x10)\n+#define PT_HP_FASTBIND\t\t(PT_LOOS + 0x11)\n+#define PT_HP_OPT_ANNOT\t\t(PT_LOOS + 0x12)\n+#define PT_HP_HSL_ANNOT\t\t(PT_LOOS + 0x13)\n+#define PT_HP_STACK\t\t(PT_LOOS + 0x14)\n+\n+#define PT_PARISC_ARCHEXT\t0x70000000\n+#define PT_PARISC_UNWIND\t0x70000001\n+\n+/* Legal values for p_flags field of Elf32_Phdr/Elf64_Phdr.  */\n+\n+#define PF_PARISC_SBP\t\t0x08000000\n+\n+#define PF_HP_PAGE_SIZE\t\t0x00100000\n+#define PF_HP_FAR_SHARED\t0x00200000\n+#define PF_HP_NEAR_SHARED\t0x00400000\n+#define PF_HP_CODE\t\t0x01000000\n+#define PF_HP_MODIFY\t\t0x02000000\n+#define PF_HP_LAZYSWAP\t\t0x04000000\n+#define PF_HP_SBP\t\t0x08000000\n+\n+\n+/* Alpha specific definitions.  */\n+\n+/* Legal values for e_flags field of Elf64_Ehdr.  */\n+\n+#define EF_ALPHA_32BIT\t\t1\t/* All addresses must be < 2GB.  */\n+#define EF_ALPHA_CANRELAX\t2\t/* Relocations for relaxing exist.  */\n+\n+/* Legal values for sh_type field of Elf64_Shdr.  */\n+\n+/* These two are primerily concerned with ECOFF debugging info.  */\n+#define SHT_ALPHA_DEBUG\t\t0x70000001\n+#define SHT_ALPHA_REGINFO\t0x70000002\n+\n+/* Legal values for sh_flags field of Elf64_Shdr.  */\n+\n+#define SHF_ALPHA_GPREL\t\t0x10000000\n+\n+/* Legal values for st_other field of Elf64_Sym.  */\n+#define STO_ALPHA_NOPV\t\t0x80\t/* No PV required.  */\n+#define STO_ALPHA_STD_GPLOAD\t0x88\t/* PV only used for initial ldgp.  */\n+\n+/* Alpha relocs.  */\n+\n+#define R_ALPHA_NONE\t\t0\t/* No reloc */\n+#define R_ALPHA_REFLONG\t\t1\t/* Direct 32 bit */\n+#define R_ALPHA_REFQUAD\t\t2\t/* Direct 64 bit */\n+#define R_ALPHA_GPREL32\t\t3\t/* GP relative 32 bit */\n+#define R_ALPHA_LITERAL\t\t4\t/* GP relative 16 bit w/optimization */\n+#define R_ALPHA_LITUSE\t\t5\t/* Optimization hint for LITERAL */\n+#define R_ALPHA_GPDISP\t\t6\t/* Add displacement to GP */\n+#define R_ALPHA_BRADDR\t\t7\t/* PC+4 relative 23 bit shifted */\n+#define R_ALPHA_HINT\t\t8\t/* PC+4 relative 16 bit shifted */\n+#define R_ALPHA_SREL16\t\t9\t/* PC relative 16 bit */\n+#define R_ALPHA_SREL32\t\t10\t/* PC relative 32 bit */\n+#define R_ALPHA_SREL64\t\t11\t/* PC relative 64 bit */\n+#define R_ALPHA_GPRELHIGH\t17\t/* GP relative 32 bit, high 16 bits */\n+#define R_ALPHA_GPRELLOW\t18\t/* GP relative 32 bit, low 16 bits */\n+#define R_ALPHA_GPREL16\t\t19\t/* GP relative 16 bit */\n+#define R_ALPHA_COPY\t\t24\t/* Copy symbol at runtime */\n+#define R_ALPHA_GLOB_DAT\t25\t/* Create GOT entry */\n+#define R_ALPHA_JMP_SLOT\t26\t/* Create PLT entry */\n+#define R_ALPHA_RELATIVE\t27\t/* Adjust by program base */\n+#define R_ALPHA_TLS_GD_HI\t28\n+#define R_ALPHA_TLSGD\t\t29\n+#define R_ALPHA_TLS_LDM\t\t30\n+#define R_ALPHA_DTPMOD64\t31\n+#define R_ALPHA_GOTDTPREL\t32\n+#define R_ALPHA_DTPREL64\t33\n+#define R_ALPHA_DTPRELHI\t34\n+#define R_ALPHA_DTPRELLO\t35\n+#define R_ALPHA_DTPREL16\t36\n+#define R_ALPHA_GOTTPREL\t37\n+#define R_ALPHA_TPREL64\t\t38\n+#define R_ALPHA_TPRELHI\t\t39\n+#define R_ALPHA_TPRELLO\t\t40\n+#define R_ALPHA_TPREL16\t\t41\n+/* Keep this the last entry.  */\n+#define R_ALPHA_NUM\t\t46\n+\n+/* Magic values of the LITUSE relocation addend.  */\n+#define LITUSE_ALPHA_ADDR\t0\n+#define LITUSE_ALPHA_BASE\t1\n+#define LITUSE_ALPHA_BYTOFF\t2\n+#define LITUSE_ALPHA_JSR\t3\n+#define LITUSE_ALPHA_TLS_GD\t4\n+#define LITUSE_ALPHA_TLS_LDM\t5\n+\n+/* Legal values for d_tag of Elf64_Dyn.  */\n+#define DT_ALPHA_PLTRO\t\t(DT_LOPROC + 0)\n+#define DT_ALPHA_NUM\t\t1\n+\n+/* PowerPC specific declarations */\n+\n+/* Values for Elf32/64_Ehdr.e_flags.  */\n+#define EF_PPC_EMB\t\t0x80000000\t/* PowerPC embedded flag */\n+\n+/* Cygnus local bits below */\n+#define EF_PPC_RELOCATABLE\t0x00010000\t/* PowerPC -mrelocatable flag*/\n+#define EF_PPC_RELOCATABLE_LIB\t0x00008000\t/* PowerPC -mrelocatable-lib\n+\t\t\t\t\t\t   flag */\n+\n+/* PowerPC relocations defined by the ABIs */\n+#define R_PPC_NONE\t\t0\n+#define R_PPC_ADDR32\t\t1\t/* 32bit absolute address */\n+#define R_PPC_ADDR24\t\t2\t/* 26bit address, 2 bits ignored.  */\n+#define R_PPC_ADDR16\t\t3\t/* 16bit absolute address */\n+#define R_PPC_ADDR16_LO\t\t4\t/* lower 16bit of absolute address */\n+#define R_PPC_ADDR16_HI\t\t5\t/* high 16bit of absolute address */\n+#define R_PPC_ADDR16_HA\t\t6\t/* adjusted high 16bit */\n+#define R_PPC_ADDR14\t\t7\t/* 16bit address, 2 bits ignored */\n+#define R_PPC_ADDR14_BRTAKEN\t8\n+#define R_PPC_ADDR14_BRNTAKEN\t9\n+#define R_PPC_REL24\t\t10\t/* PC relative 26 bit */\n+#define R_PPC_REL14\t\t11\t/* PC relative 16 bit */\n+#define R_PPC_REL14_BRTAKEN\t12\n+#define R_PPC_REL14_BRNTAKEN\t13\n+#define R_PPC_GOT16\t\t14\n+#define R_PPC_GOT16_LO\t\t15\n+#define R_PPC_GOT16_HI\t\t16\n+#define R_PPC_GOT16_HA\t\t17\n+#define R_PPC_PLTREL24\t\t18\n+#define R_PPC_COPY\t\t19\n+#define R_PPC_GLOB_DAT\t\t20\n+#define R_PPC_JMP_SLOT\t\t21\n+#define R_PPC_RELATIVE\t\t22\n+#define R_PPC_LOCAL24PC\t\t23\n+#define R_PPC_UADDR32\t\t24\n+#define R_PPC_UADDR16\t\t25\n+#define R_PPC_REL32\t\t26\n+#define R_PPC_PLT32\t\t27\n+#define R_PPC_PLTREL32\t\t28\n+#define R_PPC_PLT16_LO\t\t29\n+#define R_PPC_PLT16_HI\t\t30\n+#define R_PPC_PLT16_HA\t\t31\n+#define R_PPC_SDAREL16\t\t32\n+#define R_PPC_SECTOFF\t\t33\n+#define R_PPC_SECTOFF_LO\t34\n+#define R_PPC_SECTOFF_HI\t35\n+#define R_PPC_SECTOFF_HA\t36\n+\n+/* PowerPC relocations defined for the TLS access ABI.  */\n+#define R_PPC_TLS\t\t67 /* none\t(sym+add)@tls */\n+#define R_PPC_DTPMOD32\t\t68 /* word32\t(sym+add)@dtpmod */\n+#define R_PPC_TPREL16\t\t69 /* half16*\t(sym+add)@tprel */\n+#define R_PPC_TPREL16_LO\t70 /* half16\t(sym+add)@tprel@l */\n+#define R_PPC_TPREL16_HI\t71 /* half16\t(sym+add)@tprel@h */\n+#define R_PPC_TPREL16_HA\t72 /* half16\t(sym+add)@tprel@ha */\n+#define R_PPC_TPREL32\t\t73 /* word32\t(sym+add)@tprel */\n+#define R_PPC_DTPREL16\t\t74 /* half16*\t(sym+add)@dtprel */\n+#define R_PPC_DTPREL16_LO\t75 /* half16\t(sym+add)@dtprel@l */\n+#define R_PPC_DTPREL16_HI\t76 /* half16\t(sym+add)@dtprel@h */\n+#define R_PPC_DTPREL16_HA\t77 /* half16\t(sym+add)@dtprel@ha */\n+#define R_PPC_DTPREL32\t\t78 /* word32\t(sym+add)@dtprel */\n+#define R_PPC_GOT_TLSGD16\t79 /* half16*\t(sym+add)@got@tlsgd */\n+#define R_PPC_GOT_TLSGD16_LO\t80 /* half16\t(sym+add)@got@tlsgd@l */\n+#define R_PPC_GOT_TLSGD16_HI\t81 /* half16\t(sym+add)@got@tlsgd@h */\n+#define R_PPC_GOT_TLSGD16_HA\t82 /* half16\t(sym+add)@got@tlsgd@ha */\n+#define R_PPC_GOT_TLSLD16\t83 /* half16*\t(sym+add)@got@tlsld */\n+#define R_PPC_GOT_TLSLD16_LO\t84 /* half16\t(sym+add)@got@tlsld@l */\n+#define R_PPC_GOT_TLSLD16_HI\t85 /* half16\t(sym+add)@got@tlsld@h */\n+#define R_PPC_GOT_TLSLD16_HA\t86 /* half16\t(sym+add)@got@tlsld@ha */\n+#define R_PPC_GOT_TPREL16\t87 /* half16*\t(sym+add)@got@tprel */\n+#define R_PPC_GOT_TPREL16_LO\t88 /* half16\t(sym+add)@got@tprel@l */\n+#define R_PPC_GOT_TPREL16_HI\t89 /* half16\t(sym+add)@got@tprel@h */\n+#define R_PPC_GOT_TPREL16_HA\t90 /* half16\t(sym+add)@got@tprel@ha */\n+#define R_PPC_GOT_DTPREL16\t91 /* half16*\t(sym+add)@got@dtprel */\n+#define R_PPC_GOT_DTPREL16_LO\t92 /* half16*\t(sym+add)@got@dtprel@l */\n+#define R_PPC_GOT_DTPREL16_HI\t93 /* half16*\t(sym+add)@got@dtprel@h */\n+#define R_PPC_GOT_DTPREL16_HA\t94 /* half16*\t(sym+add)@got@dtprel@ha */\n+\n+/* The remaining relocs are from the Embedded ELF ABI, and are not\n+   in the SVR4 ELF ABI.  */\n+#define R_PPC_EMB_NADDR32\t101\n+#define R_PPC_EMB_NADDR16\t102\n+#define R_PPC_EMB_NADDR16_LO\t103\n+#define R_PPC_EMB_NADDR16_HI\t104\n+#define R_PPC_EMB_NADDR16_HA\t105\n+#define R_PPC_EMB_SDAI16\t106\n+#define R_PPC_EMB_SDA2I16\t107\n+#define R_PPC_EMB_SDA2REL\t108\n+#define R_PPC_EMB_SDA21\t\t109\t/* 16 bit offset in SDA */\n+#define R_PPC_EMB_MRKREF\t110\n+#define R_PPC_EMB_RELSEC16\t111\n+#define R_PPC_EMB_RELST_LO\t112\n+#define R_PPC_EMB_RELST_HI\t113\n+#define R_PPC_EMB_RELST_HA\t114\n+#define R_PPC_EMB_BIT_FLD\t115\n+#define R_PPC_EMB_RELSDA\t116\t/* 16 bit relative offset in SDA */\n+\n+/* Diab tool relocations.  */\n+#define R_PPC_DIAB_SDA21_LO\t180\t/* like EMB_SDA21, but lower 16 bit */\n+#define R_PPC_DIAB_SDA21_HI\t181\t/* like EMB_SDA21, but high 16 bit */\n+#define R_PPC_DIAB_SDA21_HA\t182\t/* like EMB_SDA21, adjusted high 16 */\n+#define R_PPC_DIAB_RELSDA_LO\t183\t/* like EMB_RELSDA, but lower 16 bit */\n+#define R_PPC_DIAB_RELSDA_HI\t184\t/* like EMB_RELSDA, but high 16 bit */\n+#define R_PPC_DIAB_RELSDA_HA\t185\t/* like EMB_RELSDA, adjusted high 16 */\n+\n+/* GNU extension to support local ifunc.  */\n+#define R_PPC_IRELATIVE\t\t248\n+\n+/* GNU relocs used in PIC code sequences.  */\n+#define R_PPC_REL16\t\t249\t/* half16   (sym+add-.) */\n+#define R_PPC_REL16_LO\t\t250\t/* half16   (sym+add-.)@l */\n+#define R_PPC_REL16_HI\t\t251\t/* half16   (sym+add-.)@h */\n+#define R_PPC_REL16_HA\t\t252\t/* half16   (sym+add-.)@ha */\n+\n+/* This is a phony reloc to handle any old fashioned TOC16 references\n+   that may still be in object files.  */\n+#define R_PPC_TOC16\t\t255\n+\n+/* PowerPC specific values for the Dyn d_tag field.  */\n+#define DT_PPC_GOT\t\t(DT_LOPROC + 0)\n+#define DT_PPC_NUM\t\t1\n+\n+/* PowerPC64 relocations defined by the ABIs */\n+#define R_PPC64_NONE\t\tR_PPC_NONE\n+#define R_PPC64_ADDR32\t\tR_PPC_ADDR32 /* 32bit absolute address */\n+#define R_PPC64_ADDR24\t\tR_PPC_ADDR24 /* 26bit address, word aligned */\n+#define R_PPC64_ADDR16\t\tR_PPC_ADDR16 /* 16bit absolute address */\n+#define R_PPC64_ADDR16_LO\tR_PPC_ADDR16_LO\t/* lower 16bits of address */\n+#define R_PPC64_ADDR16_HI\tR_PPC_ADDR16_HI\t/* high 16bits of address. */\n+#define R_PPC64_ADDR16_HA\tR_PPC_ADDR16_HA /* adjusted high 16bits.  */\n+#define R_PPC64_ADDR14\t\tR_PPC_ADDR14 /* 16bit address, word aligned */\n+#define R_PPC64_ADDR14_BRTAKEN\tR_PPC_ADDR14_BRTAKEN\n+#define R_PPC64_ADDR14_BRNTAKEN\tR_PPC_ADDR14_BRNTAKEN\n+#define R_PPC64_REL24\t\tR_PPC_REL24 /* PC-rel. 26 bit, word aligned */\n+#define R_PPC64_REL14\t\tR_PPC_REL14 /* PC relative 16 bit */\n+#define R_PPC64_REL14_BRTAKEN\tR_PPC_REL14_BRTAKEN\n+#define R_PPC64_REL14_BRNTAKEN\tR_PPC_REL14_BRNTAKEN\n+#define R_PPC64_GOT16\t\tR_PPC_GOT16\n+#define R_PPC64_GOT16_LO\tR_PPC_GOT16_LO\n+#define R_PPC64_GOT16_HI\tR_PPC_GOT16_HI\n+#define R_PPC64_GOT16_HA\tR_PPC_GOT16_HA\n+\n+#define R_PPC64_COPY\t\tR_PPC_COPY\n+#define R_PPC64_GLOB_DAT\tR_PPC_GLOB_DAT\n+#define R_PPC64_JMP_SLOT\tR_PPC_JMP_SLOT\n+#define R_PPC64_RELATIVE\tR_PPC_RELATIVE\n+\n+#define R_PPC64_UADDR32\t\tR_PPC_UADDR32\n+#define R_PPC64_UADDR16\t\tR_PPC_UADDR16\n+#define R_PPC64_REL32\t\tR_PPC_REL32\n+#define R_PPC64_PLT32\t\tR_PPC_PLT32\n+#define R_PPC64_PLTREL32\tR_PPC_PLTREL32\n+#define R_PPC64_PLT16_LO\tR_PPC_PLT16_LO\n+#define R_PPC64_PLT16_HI\tR_PPC_PLT16_HI\n+#define R_PPC64_PLT16_HA\tR_PPC_PLT16_HA\n+\n+#define R_PPC64_SECTOFF\t\tR_PPC_SECTOFF\n+#define R_PPC64_SECTOFF_LO\tR_PPC_SECTOFF_LO\n+#define R_PPC64_SECTOFF_HI\tR_PPC_SECTOFF_HI\n+#define R_PPC64_SECTOFF_HA\tR_PPC_SECTOFF_HA\n+#define R_PPC64_ADDR30\t\t37 /* word30 (S + A - P) >> 2 */\n+#define R_PPC64_ADDR64\t\t38 /* doubleword64 S + A */\n+#define R_PPC64_ADDR16_HIGHER\t39 /* half16 #higher(S + A) */\n+#define R_PPC64_ADDR16_HIGHERA\t40 /* half16 #highera(S + A) */\n+#define R_PPC64_ADDR16_HIGHEST\t41 /* half16 #highest(S + A) */\n+#define R_PPC64_ADDR16_HIGHESTA\t42 /* half16 #highesta(S + A) */\n+#define R_PPC64_UADDR64\t\t43 /* doubleword64 S + A */\n+#define R_PPC64_REL64\t\t44 /* doubleword64 S + A - P */\n+#define R_PPC64_PLT64\t\t45 /* doubleword64 L + A */\n+#define R_PPC64_PLTREL64\t46 /* doubleword64 L + A - P */\n+#define R_PPC64_TOC16\t\t47 /* half16* S + A - .TOC */\n+#define R_PPC64_TOC16_LO\t48 /* half16 #lo(S + A - .TOC.) */\n+#define R_PPC64_TOC16_HI\t49 /* half16 #hi(S + A - .TOC.) */\n+#define R_PPC64_TOC16_HA\t50 /* half16 #ha(S + A - .TOC.) */\n+#define R_PPC64_TOC\t\t51 /* doubleword64 .TOC */\n+#define R_PPC64_PLTGOT16\t52 /* half16* M + A */\n+#define R_PPC64_PLTGOT16_LO\t53 /* half16 #lo(M + A) */\n+#define R_PPC64_PLTGOT16_HI\t54 /* half16 #hi(M + A) */\n+#define R_PPC64_PLTGOT16_HA\t55 /* half16 #ha(M + A) */\n+\n+#define R_PPC64_ADDR16_DS\t56 /* half16ds* (S + A) >> 2 */\n+#define R_PPC64_ADDR16_LO_DS\t57 /* half16ds  #lo(S + A) >> 2 */\n+#define R_PPC64_GOT16_DS\t58 /* half16ds* (G + A) >> 2 */\n+#define R_PPC64_GOT16_LO_DS\t59 /* half16ds  #lo(G + A) >> 2 */\n+#define R_PPC64_PLT16_LO_DS\t60 /* half16ds  #lo(L + A) >> 2 */\n+#define R_PPC64_SECTOFF_DS\t61 /* half16ds* (R + A) >> 2 */\n+#define R_PPC64_SECTOFF_LO_DS\t62 /* half16ds  #lo(R + A) >> 2 */\n+#define R_PPC64_TOC16_DS\t63 /* half16ds* (S + A - .TOC.) >> 2 */\n+#define R_PPC64_TOC16_LO_DS\t64 /* half16ds  #lo(S + A - .TOC.) >> 2 */\n+#define R_PPC64_PLTGOT16_DS\t65 /* half16ds* (M + A) >> 2 */\n+#define R_PPC64_PLTGOT16_LO_DS\t66 /* half16ds  #lo(M + A) >> 2 */\n+\n+/* PowerPC64 relocations defined for the TLS access ABI.  */\n+#define R_PPC64_TLS\t\t67 /* none\t(sym+add)@tls */\n+#define R_PPC64_DTPMOD64\t68 /* doubleword64 (sym+add)@dtpmod */\n+#define R_PPC64_TPREL16\t\t69 /* half16*\t(sym+add)@tprel */\n+#define R_PPC64_TPREL16_LO\t70 /* half16\t(sym+add)@tprel@l */\n+#define R_PPC64_TPREL16_HI\t71 /* half16\t(sym+add)@tprel@h */\n+#define R_PPC64_TPREL16_HA\t72 /* half16\t(sym+add)@tprel@ha */\n+#define R_PPC64_TPREL64\t\t73 /* doubleword64 (sym+add)@tprel */\n+#define R_PPC64_DTPREL16\t74 /* half16*\t(sym+add)@dtprel */\n+#define R_PPC64_DTPREL16_LO\t75 /* half16\t(sym+add)@dtprel@l */\n+#define R_PPC64_DTPREL16_HI\t76 /* half16\t(sym+add)@dtprel@h */\n+#define R_PPC64_DTPREL16_HA\t77 /* half16\t(sym+add)@dtprel@ha */\n+#define R_PPC64_DTPREL64\t78 /* doubleword64 (sym+add)@dtprel */\n+#define R_PPC64_GOT_TLSGD16\t79 /* half16*\t(sym+add)@got@tlsgd */\n+#define R_PPC64_GOT_TLSGD16_LO\t80 /* half16\t(sym+add)@got@tlsgd@l */\n+#define R_PPC64_GOT_TLSGD16_HI\t81 /* half16\t(sym+add)@got@tlsgd@h */\n+#define R_PPC64_GOT_TLSGD16_HA\t82 /* half16\t(sym+add)@got@tlsgd@ha */\n+#define R_PPC64_GOT_TLSLD16\t83 /* half16*\t(sym+add)@got@tlsld */\n+#define R_PPC64_GOT_TLSLD16_LO\t84 /* half16\t(sym+add)@got@tlsld@l */\n+#define R_PPC64_GOT_TLSLD16_HI\t85 /* half16\t(sym+add)@got@tlsld@h */\n+#define R_PPC64_GOT_TLSLD16_HA\t86 /* half16\t(sym+add)@got@tlsld@ha */\n+#define R_PPC64_GOT_TPREL16_DS\t87 /* half16ds*\t(sym+add)@got@tprel */\n+#define R_PPC64_GOT_TPREL16_LO_DS 88 /* half16ds (sym+add)@got@tprel@l */\n+#define R_PPC64_GOT_TPREL16_HI\t89 /* half16\t(sym+add)@got@tprel@h */\n+#define R_PPC64_GOT_TPREL16_HA\t90 /* half16\t(sym+add)@got@tprel@ha */\n+#define R_PPC64_GOT_DTPREL16_DS\t91 /* half16ds*\t(sym+add)@got@dtprel */\n+#define R_PPC64_GOT_DTPREL16_LO_DS 92 /* half16ds (sym+add)@got@dtprel@l */\n+#define R_PPC64_GOT_DTPREL16_HI\t93 /* half16\t(sym+add)@got@dtprel@h */\n+#define R_PPC64_GOT_DTPREL16_HA\t94 /* half16\t(sym+add)@got@dtprel@ha */\n+#define R_PPC64_TPREL16_DS\t95 /* half16ds*\t(sym+add)@tprel */\n+#define R_PPC64_TPREL16_LO_DS\t96 /* half16ds\t(sym+add)@tprel@l */\n+#define R_PPC64_TPREL16_HIGHER\t97 /* half16\t(sym+add)@tprel@higher */\n+#define R_PPC64_TPREL16_HIGHERA\t98 /* half16\t(sym+add)@tprel@highera */\n+#define R_PPC64_TPREL16_HIGHEST\t99 /* half16\t(sym+add)@tprel@highest */\n+#define R_PPC64_TPREL16_HIGHESTA 100 /* half16\t(sym+add)@tprel@highesta */\n+#define R_PPC64_DTPREL16_DS\t101 /* half16ds* (sym+add)@dtprel */\n+#define R_PPC64_DTPREL16_LO_DS\t102 /* half16ds\t(sym+add)@dtprel@l */\n+#define R_PPC64_DTPREL16_HIGHER\t103 /* half16\t(sym+add)@dtprel@higher */\n+#define R_PPC64_DTPREL16_HIGHERA 104 /* half16\t(sym+add)@dtprel@highera */\n+#define R_PPC64_DTPREL16_HIGHEST 105 /* half16\t(sym+add)@dtprel@highest */\n+#define R_PPC64_DTPREL16_HIGHESTA 106 /* half16\t(sym+add)@dtprel@highesta */\n+\n+/* GNU extension to support local ifunc.  */\n+#define R_PPC64_JMP_IREL\t247\n+#define R_PPC64_IRELATIVE\t248\n+#define R_PPC64_REL16\t\t249\t/* half16   (sym+add-.) */\n+#define R_PPC64_REL16_LO\t250\t/* half16   (sym+add-.)@l */\n+#define R_PPC64_REL16_HI\t251\t/* half16   (sym+add-.)@h */\n+#define R_PPC64_REL16_HA\t252\t/* half16   (sym+add-.)@ha */\n+\n+/* PowerPC64 specific values for the Dyn d_tag field.  */\n+#define DT_PPC64_GLINK  (DT_LOPROC + 0)\n+#define DT_PPC64_OPD\t(DT_LOPROC + 1)\n+#define DT_PPC64_OPDSZ\t(DT_LOPROC + 2)\n+#define DT_PPC64_NUM    3\n+\n+\n+/* ARM specific declarations */\n+\n+/* Processor specific flags for the ELF header e_flags field.  */\n+#define EF_ARM_RELEXEC\t\t0x01\n+#define EF_ARM_HASENTRY\t\t0x02\n+#define EF_ARM_INTERWORK\t0x04\n+#define EF_ARM_APCS_26\t\t0x08\n+#define EF_ARM_APCS_FLOAT\t0x10\n+#define EF_ARM_PIC\t\t0x20\n+#define EF_ARM_ALIGN8\t\t0x40 /* 8-bit structure alignment is in use */\n+#define EF_ARM_NEW_ABI\t\t0x80\n+#define EF_ARM_OLD_ABI\t\t0x100\n+#define EF_ARM_SOFT_FLOAT\t0x200\n+#define EF_ARM_VFP_FLOAT\t0x400\n+#define EF_ARM_MAVERICK_FLOAT\t0x800\n+\n+\n+/* Other constants defined in the ARM ELF spec. version B-01.  */\n+/* NB. These conflict with values defined above.  */\n+#define EF_ARM_SYMSARESORTED\t0x04\n+#define EF_ARM_DYNSYMSUSESEGIDX\t0x08\n+#define EF_ARM_MAPSYMSFIRST\t0x10\n+#define EF_ARM_EABIMASK\t\t0XFF000000\n+\n+/* Constants defined in AAELF.  */\n+#define EF_ARM_BE8\t    0x00800000\n+#define EF_ARM_LE8\t    0x00400000\n+\n+#define EF_ARM_EABI_VERSION(flags)\t((flags) & EF_ARM_EABIMASK)\n+#define EF_ARM_EABI_UNKNOWN\t0x00000000\n+#define EF_ARM_EABI_VER1\t0x01000000\n+#define EF_ARM_EABI_VER2\t0x02000000\n+#define EF_ARM_EABI_VER3\t0x03000000\n+#define EF_ARM_EABI_VER4\t0x04000000\n+#define EF_ARM_EABI_VER5\t0x05000000\n+\n+/* Additional symbol types for Thumb.  */\n+#define STT_ARM_TFUNC\t\tSTT_LOPROC /* A Thumb function.  */\n+#define STT_ARM_16BIT\t\tSTT_HIPROC /* A Thumb label.  */\n+\n+/* ARM-specific values for sh_flags */\n+#define SHF_ARM_ENTRYSECT\t0x10000000 /* Section contains an entry point */\n+#define SHF_ARM_COMDEF\t\t0x80000000 /* Section may be multiply defined\n+\t\t\t\t\t      in the input to a link step.  */\n+\n+/* ARM-specific program header flags */\n+#define PF_ARM_SB\t\t0x10000000 /* Segment contains the location\n+\t\t\t\t\t      addressed by the static base. */\n+#define PF_ARM_PI\t\t0x20000000 /* Position-independent segment.  */\n+#define PF_ARM_ABS\t\t0x40000000 /* Absolute segment.  */\n+\n+/* Processor specific values for the Phdr p_type field.  */\n+#define PT_ARM_EXIDX\t\t(PT_LOPROC + 1)\t/* ARM unwind segment.  */\n+\n+/* Processor specific values for the Shdr sh_type field.  */\n+#define SHT_ARM_EXIDX\t\t(SHT_LOPROC + 1) /* ARM unwind section.  */\n+#define SHT_ARM_PREEMPTMAP\t(SHT_LOPROC + 2) /* Preemption details.  */\n+#define SHT_ARM_ATTRIBUTES\t(SHT_LOPROC + 3) /* ARM attributes section.  */\n+\n+\n+/* ARM relocs.  */\n+\n+#define R_ARM_NONE\t\t0\t/* No reloc */\n+#define R_ARM_PC24\t\t1\t/* PC relative 26 bit branch */\n+#define R_ARM_ABS32\t\t2\t/* Direct 32 bit  */\n+#define R_ARM_REL32\t\t3\t/* PC relative 32 bit */\n+#define R_ARM_PC13\t\t4\n+#define R_ARM_ABS16\t\t5\t/* Direct 16 bit */\n+#define R_ARM_ABS12\t\t6\t/* Direct 12 bit */\n+#define R_ARM_THM_ABS5\t\t7\n+#define R_ARM_ABS8\t\t8\t/* Direct 8 bit */\n+#define R_ARM_SBREL32\t\t9\n+#define R_ARM_THM_PC22\t\t10\n+#define R_ARM_THM_PC8\t\t11\n+#define R_ARM_AMP_VCALL9\t12\n+#define R_ARM_SWI24\t\t13\t/* Obsolete static relocation.  */\n+#define R_ARM_TLS_DESC\t\t13      /* Dynamic relocation.  */\n+#define R_ARM_THM_SWI8\t\t14\n+#define R_ARM_XPC25\t\t15\n+#define R_ARM_THM_XPC22\t\t16\n+#define R_ARM_TLS_DTPMOD32\t17\t/* ID of module containing symbol */\n+#define R_ARM_TLS_DTPOFF32\t18\t/* Offset in TLS block */\n+#define R_ARM_TLS_TPOFF32\t19\t/* Offset in static TLS block */\n+#define R_ARM_COPY\t\t20\t/* Copy symbol at runtime */\n+#define R_ARM_GLOB_DAT\t\t21\t/* Create GOT entry */\n+#define R_ARM_JUMP_SLOT\t\t22\t/* Create PLT entry */\n+#define R_ARM_RELATIVE\t\t23\t/* Adjust by program base */\n+#define R_ARM_GOTOFF\t\t24\t/* 32 bit offset to GOT */\n+#define R_ARM_GOTPC\t\t25\t/* 32 bit PC relative offset to GOT */\n+#define R_ARM_GOT32\t\t26\t/* 32 bit GOT entry */\n+#define R_ARM_PLT32\t\t27\t/* 32 bit PLT address */\n+#define R_ARM_ALU_PCREL_7_0\t32\n+#define R_ARM_ALU_PCREL_15_8\t33\n+#define R_ARM_ALU_PCREL_23_15\t34\n+#define R_ARM_LDR_SBREL_11_0\t35\n+#define R_ARM_ALU_SBREL_19_12\t36\n+#define R_ARM_ALU_SBREL_27_20\t37\n+#define R_ARM_TLS_GOTDESC\t90\n+#define R_ARM_TLS_CALL\t\t91\n+#define R_ARM_TLS_DESCSEQ\t92\n+#define R_ARM_THM_TLS_CALL\t93\n+#define R_ARM_GNU_VTENTRY\t100\n+#define R_ARM_GNU_VTINHERIT\t101\n+#define R_ARM_THM_PC11\t\t102\t/* thumb unconditional branch */\n+#define R_ARM_THM_PC9\t\t103\t/* thumb conditional branch */\n+#define R_ARM_TLS_GD32\t\t104\t/* PC-rel 32 bit for global dynamic\n+\t\t\t\t\t   thread local data */\n+#define R_ARM_TLS_LDM32\t\t105\t/* PC-rel 32 bit for local dynamic\n+\t\t\t\t\t   thread local data */\n+#define R_ARM_TLS_LDO32\t\t106\t/* 32 bit offset relative to TLS\n+\t\t\t\t\t   block */\n+#define R_ARM_TLS_IE32\t\t107\t/* PC-rel 32 bit for GOT entry of\n+\t\t\t\t\t   static TLS block offset */\n+#define R_ARM_TLS_LE32\t\t108\t/* 32 bit offset relative to static\n+\t\t\t\t\t   TLS block */\n+#define\tR_ARM_THM_TLS_DESCSEQ\t129\n+#define R_ARM_IRELATIVE\t\t160\n+#define R_ARM_RXPC25\t\t249\n+#define R_ARM_RSBREL32\t\t250\n+#define R_ARM_THM_RPC22\t\t251\n+#define R_ARM_RREL32\t\t252\n+#define R_ARM_RABS22\t\t253\n+#define R_ARM_RPC24\t\t254\n+#define R_ARM_RBASE\t\t255\n+/* Keep this the last entry.  */\n+#define R_ARM_NUM\t\t256\n+\n+/* IA-64 specific declarations.  */\n+\n+/* Processor specific flags for the Ehdr e_flags field.  */\n+#define EF_IA_64_MASKOS\t\t0x0000000f\t/* os-specific flags */\n+#define EF_IA_64_ABI64\t\t0x00000010\t/* 64-bit ABI */\n+#define EF_IA_64_ARCH\t\t0xff000000\t/* arch. version mask */\n+\n+/* Processor specific values for the Phdr p_type field.  */\n+#define PT_IA_64_ARCHEXT\t(PT_LOPROC + 0)\t/* arch extension bits */\n+#define PT_IA_64_UNWIND\t\t(PT_LOPROC + 1)\t/* ia64 unwind bits */\n+#define PT_IA_64_HP_OPT_ANOT\t(PT_LOOS + 0x12)\n+#define PT_IA_64_HP_HSL_ANOT\t(PT_LOOS + 0x13)\n+#define PT_IA_64_HP_STACK\t(PT_LOOS + 0x14)\n+\n+/* Processor specific flags for the Phdr p_flags field.  */\n+#define PF_IA_64_NORECOV\t0x80000000\t/* spec insns w/o recovery */\n+\n+/* Processor specific values for the Shdr sh_type field.  */\n+#define SHT_IA_64_EXT\t\t(SHT_LOPROC + 0) /* extension bits */\n+#define SHT_IA_64_UNWIND\t(SHT_LOPROC + 1) /* unwind bits */\n+\n+/* Processor specific flags for the Shdr sh_flags field.  */\n+#define SHF_IA_64_SHORT\t\t0x10000000\t/* section near gp */\n+#define SHF_IA_64_NORECOV\t0x20000000\t/* spec insns w/o recovery */\n+\n+/* Processor specific values for the Dyn d_tag field.  */\n+#define DT_IA_64_PLT_RESERVE\t(DT_LOPROC + 0)\n+#define DT_IA_64_NUM\t\t1\n+\n+/* IA-64 relocations.  */\n+#define R_IA64_NONE\t\t0x00\t/* none */\n+#define R_IA64_IMM14\t\t0x21\t/* symbol + addend, add imm14 */\n+#define R_IA64_IMM22\t\t0x22\t/* symbol + addend, add imm22 */\n+#define R_IA64_IMM64\t\t0x23\t/* symbol + addend, mov imm64 */\n+#define R_IA64_DIR32MSB\t\t0x24\t/* symbol + addend, data4 MSB */\n+#define R_IA64_DIR32LSB\t\t0x25\t/* symbol + addend, data4 LSB */\n+#define R_IA64_DIR64MSB\t\t0x26\t/* symbol + addend, data8 MSB */\n+#define R_IA64_DIR64LSB\t\t0x27\t/* symbol + addend, data8 LSB */\n+#define R_IA64_GPREL22\t\t0x2a\t/* @gprel(sym + add), add imm22 */\n+#define R_IA64_GPREL64I\t\t0x2b\t/* @gprel(sym + add), mov imm64 */\n+#define R_IA64_GPREL32MSB\t0x2c\t/* @gprel(sym + add), data4 MSB */\n+#define R_IA64_GPREL32LSB\t0x2d\t/* @gprel(sym + add), data4 LSB */\n+#define R_IA64_GPREL64MSB\t0x2e\t/* @gprel(sym + add), data8 MSB */\n+#define R_IA64_GPREL64LSB\t0x2f\t/* @gprel(sym + add), data8 LSB */\n+#define R_IA64_LTOFF22\t\t0x32\t/* @ltoff(sym + add), add imm22 */\n+#define R_IA64_LTOFF64I\t\t0x33\t/* @ltoff(sym + add), mov imm64 */\n+#define R_IA64_PLTOFF22\t\t0x3a\t/* @pltoff(sym + add), add imm22 */\n+#define R_IA64_PLTOFF64I\t0x3b\t/* @pltoff(sym + add), mov imm64 */\n+#define R_IA64_PLTOFF64MSB\t0x3e\t/* @pltoff(sym + add), data8 MSB */\n+#define R_IA64_PLTOFF64LSB\t0x3f\t/* @pltoff(sym + add), data8 LSB */\n+#define R_IA64_FPTR64I\t\t0x43\t/* @fptr(sym + add), mov imm64 */\n+#define R_IA64_FPTR32MSB\t0x44\t/* @fptr(sym + add), data4 MSB */\n+#define R_IA64_FPTR32LSB\t0x45\t/* @fptr(sym + add), data4 LSB */\n+#define R_IA64_FPTR64MSB\t0x46\t/* @fptr(sym + add), data8 MSB */\n+#define R_IA64_FPTR64LSB\t0x47\t/* @fptr(sym + add), data8 LSB */\n+#define R_IA64_PCREL60B\t\t0x48\t/* @pcrel(sym + add), brl */\n+#define R_IA64_PCREL21B\t\t0x49\t/* @pcrel(sym + add), ptb, call */\n+#define R_IA64_PCREL21M\t\t0x4a\t/* @pcrel(sym + add), chk.s */\n+#define R_IA64_PCREL21F\t\t0x4b\t/* @pcrel(sym + add), fchkf */\n+#define R_IA64_PCREL32MSB\t0x4c\t/* @pcrel(sym + add), data4 MSB */\n+#define R_IA64_PCREL32LSB\t0x4d\t/* @pcrel(sym + add), data4 LSB */\n+#define R_IA64_PCREL64MSB\t0x4e\t/* @pcrel(sym + add), data8 MSB */\n+#define R_IA64_PCREL64LSB\t0x4f\t/* @pcrel(sym + add), data8 LSB */\n+#define R_IA64_LTOFF_FPTR22\t0x52\t/* @ltoff(@fptr(s+a)), imm22 */\n+#define R_IA64_LTOFF_FPTR64I\t0x53\t/* @ltoff(@fptr(s+a)), imm64 */\n+#define R_IA64_LTOFF_FPTR32MSB\t0x54\t/* @ltoff(@fptr(s+a)), data4 MSB */\n+#define R_IA64_LTOFF_FPTR32LSB\t0x55\t/* @ltoff(@fptr(s+a)), data4 LSB */\n+#define R_IA64_LTOFF_FPTR64MSB\t0x56\t/* @ltoff(@fptr(s+a)), data8 MSB */\n+#define R_IA64_LTOFF_FPTR64LSB\t0x57\t/* @ltoff(@fptr(s+a)), data8 LSB */\n+#define R_IA64_SEGREL32MSB\t0x5c\t/* @segrel(sym + add), data4 MSB */\n+#define R_IA64_SEGREL32LSB\t0x5d\t/* @segrel(sym + add), data4 LSB */\n+#define R_IA64_SEGREL64MSB\t0x5e\t/* @segrel(sym + add), data8 MSB */\n+#define R_IA64_SEGREL64LSB\t0x5f\t/* @segrel(sym + add), data8 LSB */\n+#define R_IA64_SECREL32MSB\t0x64\t/* @secrel(sym + add), data4 MSB */\n+#define R_IA64_SECREL32LSB\t0x65\t/* @secrel(sym + add), data4 LSB */\n+#define R_IA64_SECREL64MSB\t0x66\t/* @secrel(sym + add), data8 MSB */\n+#define R_IA64_SECREL64LSB\t0x67\t/* @secrel(sym + add), data8 LSB */\n+#define R_IA64_REL32MSB\t\t0x6c\t/* data 4 + REL */\n+#define R_IA64_REL32LSB\t\t0x6d\t/* data 4 + REL */\n+#define R_IA64_REL64MSB\t\t0x6e\t/* data 8 + REL */\n+#define R_IA64_REL64LSB\t\t0x6f\t/* data 8 + REL */\n+#define R_IA64_LTV32MSB\t\t0x74\t/* symbol + addend, data4 MSB */\n+#define R_IA64_LTV32LSB\t\t0x75\t/* symbol + addend, data4 LSB */\n+#define R_IA64_LTV64MSB\t\t0x76\t/* symbol + addend, data8 MSB */\n+#define R_IA64_LTV64LSB\t\t0x77\t/* symbol + addend, data8 LSB */\n+#define R_IA64_PCREL21BI\t0x79\t/* @pcrel(sym + add), 21bit inst */\n+#define R_IA64_PCREL22\t\t0x7a\t/* @pcrel(sym + add), 22bit inst */\n+#define R_IA64_PCREL64I\t\t0x7b\t/* @pcrel(sym + add), 64bit inst */\n+#define R_IA64_IPLTMSB\t\t0x80\t/* dynamic reloc, imported PLT, MSB */\n+#define R_IA64_IPLTLSB\t\t0x81\t/* dynamic reloc, imported PLT, LSB */\n+#define R_IA64_COPY\t\t0x84\t/* copy relocation */\n+#define R_IA64_SUB\t\t0x85\t/* Addend and symbol difference */\n+#define R_IA64_LTOFF22X\t\t0x86\t/* LTOFF22, relaxable.  */\n+#define R_IA64_LDXMOV\t\t0x87\t/* Use of LTOFF22X.  */\n+#define R_IA64_TPREL14\t\t0x91\t/* @tprel(sym + add), imm14 */\n+#define R_IA64_TPREL22\t\t0x92\t/* @tprel(sym + add), imm22 */\n+#define R_IA64_TPREL64I\t\t0x93\t/* @tprel(sym + add), imm64 */\n+#define R_IA64_TPREL64MSB\t0x96\t/* @tprel(sym + add), data8 MSB */\n+#define R_IA64_TPREL64LSB\t0x97\t/* @tprel(sym + add), data8 LSB */\n+#define R_IA64_LTOFF_TPREL22\t0x9a\t/* @ltoff(@tprel(s+a)), imm2 */\n+#define R_IA64_DTPMOD64MSB\t0xa6\t/* @dtpmod(sym + add), data8 MSB */\n+#define R_IA64_DTPMOD64LSB\t0xa7\t/* @dtpmod(sym + add), data8 LSB */\n+#define R_IA64_LTOFF_DTPMOD22\t0xaa\t/* @ltoff(@dtpmod(sym + add)), imm22 */\n+#define R_IA64_DTPREL14\t\t0xb1\t/* @dtprel(sym + add), imm14 */\n+#define R_IA64_DTPREL22\t\t0xb2\t/* @dtprel(sym + add), imm22 */\n+#define R_IA64_DTPREL64I\t0xb3\t/* @dtprel(sym + add), imm64 */\n+#define R_IA64_DTPREL32MSB\t0xb4\t/* @dtprel(sym + add), data4 MSB */\n+#define R_IA64_DTPREL32LSB\t0xb5\t/* @dtprel(sym + add), data4 LSB */\n+#define R_IA64_DTPREL64MSB\t0xb6\t/* @dtprel(sym + add), data8 MSB */\n+#define R_IA64_DTPREL64LSB\t0xb7\t/* @dtprel(sym + add), data8 LSB */\n+#define R_IA64_LTOFF_DTPREL22\t0xba\t/* @ltoff(@dtprel(s+a)), imm22 */\n+\n+/* SH specific declarations */\n+\n+/* Processor specific flags for the ELF header e_flags field.  */\n+#define EF_SH_MACH_MASK\t\t0x1f\n+#define EF_SH_UNKNOWN\t\t0x0\n+#define EF_SH1\t\t\t0x1\n+#define EF_SH2\t\t\t0x2\n+#define EF_SH3\t\t\t0x3\n+#define EF_SH_DSP\t\t0x4\n+#define EF_SH3_DSP\t\t0x5\n+#define EF_SH4AL_DSP\t\t0x6\n+#define EF_SH3E\t\t\t0x8\n+#define EF_SH4\t\t\t0x9\n+#define EF_SH2E\t\t\t0xb\n+#define EF_SH4A\t\t\t0xc\n+#define EF_SH2A\t\t\t0xd\n+#define EF_SH4_NOFPU\t\t0x10\n+#define EF_SH4A_NOFPU\t\t0x11\n+#define EF_SH4_NOMMU_NOFPU\t0x12\n+#define EF_SH2A_NOFPU\t\t0x13\n+#define EF_SH3_NOMMU\t\t0x14\n+#define EF_SH2A_SH4_NOFPU\t0x15\n+#define EF_SH2A_SH3_NOFPU\t0x16\n+#define EF_SH2A_SH4\t\t0x17\n+#define EF_SH2A_SH3E\t\t0x18\n+\n+/* SH relocs.  */\n+#define\tR_SH_NONE\t\t0\n+#define\tR_SH_DIR32\t\t1\n+#define\tR_SH_REL32\t\t2\n+#define\tR_SH_DIR8WPN\t\t3\n+#define\tR_SH_IND12W\t\t4\n+#define\tR_SH_DIR8WPL\t\t5\n+#define\tR_SH_DIR8WPZ\t\t6\n+#define\tR_SH_DIR8BP\t\t7\n+#define\tR_SH_DIR8W\t\t8\n+#define\tR_SH_DIR8L\t\t9\n+#define\tR_SH_SWITCH16\t\t25\n+#define\tR_SH_SWITCH32\t\t26\n+#define\tR_SH_USES\t\t27\n+#define\tR_SH_COUNT\t\t28\n+#define\tR_SH_ALIGN\t\t29\n+#define\tR_SH_CODE\t\t30\n+#define\tR_SH_DATA\t\t31\n+#define\tR_SH_LABEL\t\t32\n+#define\tR_SH_SWITCH8\t\t33\n+#define\tR_SH_GNU_VTINHERIT\t34\n+#define\tR_SH_GNU_VTENTRY\t35\n+#define\tR_SH_TLS_GD_32\t\t144\n+#define\tR_SH_TLS_LD_32\t\t145\n+#define\tR_SH_TLS_LDO_32\t\t146\n+#define\tR_SH_TLS_IE_32\t\t147\n+#define\tR_SH_TLS_LE_32\t\t148\n+#define\tR_SH_TLS_DTPMOD32\t149\n+#define\tR_SH_TLS_DTPOFF32\t150\n+#define\tR_SH_TLS_TPOFF32\t151\n+#define\tR_SH_GOT32\t\t160\n+#define\tR_SH_PLT32\t\t161\n+#define\tR_SH_COPY\t\t162\n+#define\tR_SH_GLOB_DAT\t\t163\n+#define\tR_SH_JMP_SLOT\t\t164\n+#define\tR_SH_RELATIVE\t\t165\n+#define\tR_SH_GOTOFF\t\t166\n+#define\tR_SH_GOTPC\t\t167\n+/* Keep this the last entry.  */\n+#define\tR_SH_NUM\t\t256\n+\n+/* S/390 specific definitions.  */\n+\n+/* Valid values for the e_flags field.  */\n+\n+#define EF_S390_HIGH_GPRS    0x00000001  /* High GPRs kernel facility needed.  */\n+\n+/* Additional s390 relocs */\n+\n+#define R_390_NONE\t\t0\t/* No reloc.  */\n+#define R_390_8\t\t\t1\t/* Direct 8 bit.  */\n+#define R_390_12\t\t2\t/* Direct 12 bit.  */\n+#define R_390_16\t\t3\t/* Direct 16 bit.  */\n+#define R_390_32\t\t4\t/* Direct 32 bit.  */\n+#define R_390_PC32\t\t5\t/* PC relative 32 bit.\t*/\n+#define R_390_GOT12\t\t6\t/* 12 bit GOT offset.  */\n+#define R_390_GOT32\t\t7\t/* 32 bit GOT offset.  */\n+#define R_390_PLT32\t\t8\t/* 32 bit PC relative PLT address.  */\n+#define R_390_COPY\t\t9\t/* Copy symbol at runtime.  */\n+#define R_390_GLOB_DAT\t\t10\t/* Create GOT entry.  */\n+#define R_390_JMP_SLOT\t\t11\t/* Create PLT entry.  */\n+#define R_390_RELATIVE\t\t12\t/* Adjust by program base.  */\n+#define R_390_GOTOFF32\t\t13\t/* 32 bit offset to GOT.\t */\n+#define R_390_GOTPC\t\t14\t/* 32 bit PC relative offset to GOT.  */\n+#define R_390_GOT16\t\t15\t/* 16 bit GOT offset.  */\n+#define R_390_PC16\t\t16\t/* PC relative 16 bit.\t*/\n+#define R_390_PC16DBL\t\t17\t/* PC relative 16 bit shifted by 1.  */\n+#define R_390_PLT16DBL\t\t18\t/* 16 bit PC rel. PLT shifted by 1.  */\n+#define R_390_PC32DBL\t\t19\t/* PC relative 32 bit shifted by 1.  */\n+#define R_390_PLT32DBL\t\t20\t/* 32 bit PC rel. PLT shifted by 1.  */\n+#define R_390_GOTPCDBL\t\t21\t/* 32 bit PC rel. GOT shifted by 1.  */\n+#define R_390_64\t\t22\t/* Direct 64 bit.  */\n+#define R_390_PC64\t\t23\t/* PC relative 64 bit.\t*/\n+#define R_390_GOT64\t\t24\t/* 64 bit GOT offset.  */\n+#define R_390_PLT64\t\t25\t/* 64 bit PC relative PLT address.  */\n+#define R_390_GOTENT\t\t26\t/* 32 bit PC rel. to GOT entry >> 1. */\n+#define R_390_GOTOFF16\t\t27\t/* 16 bit offset to GOT. */\n+#define R_390_GOTOFF64\t\t28\t/* 64 bit offset to GOT. */\n+#define R_390_GOTPLT12\t\t29\t/* 12 bit offset to jump slot.\t*/\n+#define R_390_GOTPLT16\t\t30\t/* 16 bit offset to jump slot.\t*/\n+#define R_390_GOTPLT32\t\t31\t/* 32 bit offset to jump slot.\t*/\n+#define R_390_GOTPLT64\t\t32\t/* 64 bit offset to jump slot.\t*/\n+#define R_390_GOTPLTENT\t\t33\t/* 32 bit rel. offset to jump slot.  */\n+#define R_390_PLTOFF16\t\t34\t/* 16 bit offset from GOT to PLT. */\n+#define R_390_PLTOFF32\t\t35\t/* 32 bit offset from GOT to PLT. */\n+#define R_390_PLTOFF64\t\t36\t/* 16 bit offset from GOT to PLT. */\n+#define R_390_TLS_LOAD\t\t37\t/* Tag for load insn in TLS code.  */\n+#define R_390_TLS_GDCALL\t38\t/* Tag for function call in general\n+\t\t\t\t\t   dynamic TLS code. */\n+#define R_390_TLS_LDCALL\t39\t/* Tag for function call in local\n+\t\t\t\t\t   dynamic TLS code. */\n+#define R_390_TLS_GD32\t\t40\t/* Direct 32 bit for general dynamic\n+\t\t\t\t\t   thread local data.  */\n+#define R_390_TLS_GD64\t\t41\t/* Direct 64 bit for general dynamic\n+\t\t\t\t\t  thread local data.  */\n+#define R_390_TLS_GOTIE12\t42\t/* 12 bit GOT offset for static TLS\n+\t\t\t\t\t   block offset.  */\n+#define R_390_TLS_GOTIE32\t43\t/* 32 bit GOT offset for static TLS\n+\t\t\t\t\t   block offset.  */\n+#define R_390_TLS_GOTIE64\t44\t/* 64 bit GOT offset for static TLS\n+\t\t\t\t\t   block offset. */\n+#define R_390_TLS_LDM32\t\t45\t/* Direct 32 bit for local dynamic\n+\t\t\t\t\t   thread local data in LE code.  */\n+#define R_390_TLS_LDM64\t\t46\t/* Direct 64 bit for local dynamic\n+\t\t\t\t\t   thread local data in LE code.  */\n+#define R_390_TLS_IE32\t\t47\t/* 32 bit address of GOT entry for\n+\t\t\t\t\t   negated static TLS block offset.  */\n+#define R_390_TLS_IE64\t\t48\t/* 64 bit address of GOT entry for\n+\t\t\t\t\t   negated static TLS block offset.  */\n+#define R_390_TLS_IEENT\t\t49\t/* 32 bit rel. offset to GOT entry for\n+\t\t\t\t\t   negated static TLS block offset.  */\n+#define R_390_TLS_LE32\t\t50\t/* 32 bit negated offset relative to\n+\t\t\t\t\t   static TLS block.  */\n+#define R_390_TLS_LE64\t\t51\t/* 64 bit negated offset relative to\n+\t\t\t\t\t   static TLS block.  */\n+#define R_390_TLS_LDO32\t\t52\t/* 32 bit offset relative to TLS\n+\t\t\t\t\t   block.  */\n+#define R_390_TLS_LDO64\t\t53\t/* 64 bit offset relative to TLS\n+\t\t\t\t\t   block.  */\n+#define R_390_TLS_DTPMOD\t54\t/* ID of module containing symbol.  */\n+#define R_390_TLS_DTPOFF\t55\t/* Offset in TLS block.\t */\n+#define R_390_TLS_TPOFF\t\t56\t/* Negated offset in static TLS\n+\t\t\t\t\t   block.  */\n+#define R_390_20\t\t57\t/* Direct 20 bit.  */\n+#define R_390_GOT20\t\t58\t/* 20 bit GOT offset.  */\n+#define R_390_GOTPLT20\t\t59\t/* 20 bit offset to jump slot.  */\n+#define R_390_TLS_GOTIE20\t60\t/* 20 bit GOT offset for static TLS\n+\t\t\t\t\t   block offset.  */\n+#define R_390_IRELATIVE         61      /* STT_GNU_IFUNC relocation.  */\n+/* Keep this the last entry.  */\n+#define R_390_NUM\t\t62\n+\n+\n+/* CRIS relocations.  */\n+#define R_CRIS_NONE\t\t0\n+#define R_CRIS_8\t\t1\n+#define R_CRIS_16\t\t2\n+#define R_CRIS_32\t\t3\n+#define R_CRIS_8_PCREL\t\t4\n+#define R_CRIS_16_PCREL\t\t5\n+#define R_CRIS_32_PCREL\t\t6\n+#define R_CRIS_GNU_VTINHERIT\t7\n+#define R_CRIS_GNU_VTENTRY\t8\n+#define R_CRIS_COPY\t\t9\n+#define R_CRIS_GLOB_DAT\t\t10\n+#define R_CRIS_JUMP_SLOT\t11\n+#define R_CRIS_RELATIVE\t\t12\n+#define R_CRIS_16_GOT\t\t13\n+#define R_CRIS_32_GOT\t\t14\n+#define R_CRIS_16_GOTPLT\t15\n+#define R_CRIS_32_GOTPLT\t16\n+#define R_CRIS_32_GOTREL\t17\n+#define R_CRIS_32_PLT_GOTREL\t18\n+#define R_CRIS_32_PLT_PCREL\t19\n+\n+#define R_CRIS_NUM\t\t20\n+\n+\n+/* AMD x86-64 relocations.  */\n+#define R_X86_64_NONE\t\t0\t/* No reloc */\n+#define R_X86_64_64\t\t1\t/* Direct 64 bit  */\n+#define R_X86_64_PC32\t\t2\t/* PC relative 32 bit signed */\n+#define R_X86_64_GOT32\t\t3\t/* 32 bit GOT entry */\n+#define R_X86_64_PLT32\t\t4\t/* 32 bit PLT address */\n+#define R_X86_64_COPY\t\t5\t/* Copy symbol at runtime */\n+#define R_X86_64_GLOB_DAT\t6\t/* Create GOT entry */\n+#define R_X86_64_JUMP_SLOT\t7\t/* Create PLT entry */\n+#define R_X86_64_RELATIVE\t8\t/* Adjust by program base */\n+#define R_X86_64_GOTPCREL\t9\t/* 32 bit signed PC relative\n+\t\t\t\t\t   offset to GOT */\n+#define R_X86_64_32\t\t10\t/* Direct 32 bit zero extended */\n+#define R_X86_64_32S\t\t11\t/* Direct 32 bit sign extended */\n+#define R_X86_64_16\t\t12\t/* Direct 16 bit zero extended */\n+#define R_X86_64_PC16\t\t13\t/* 16 bit sign extended pc relative */\n+#define R_X86_64_8\t\t14\t/* Direct 8 bit sign extended  */\n+#define R_X86_64_PC8\t\t15\t/* 8 bit sign extended pc relative */\n+#define R_X86_64_DTPMOD64\t16\t/* ID of module containing symbol */\n+#define R_X86_64_DTPOFF64\t17\t/* Offset in module's TLS block */\n+#define R_X86_64_TPOFF64\t18\t/* Offset in initial TLS block */\n+#define R_X86_64_TLSGD\t\t19\t/* 32 bit signed PC relative offset\n+\t\t\t\t\t   to two GOT entries for GD symbol */\n+#define R_X86_64_TLSLD\t\t20\t/* 32 bit signed PC relative offset\n+\t\t\t\t\t   to two GOT entries for LD symbol */\n+#define R_X86_64_DTPOFF32\t21\t/* Offset in TLS block */\n+#define R_X86_64_GOTTPOFF\t22\t/* 32 bit signed PC relative offset\n+\t\t\t\t\t   to GOT entry for IE symbol */\n+#define R_X86_64_TPOFF32\t23\t/* Offset in initial TLS block */\n+#define R_X86_64_PC64\t\t24\t/* PC relative 64 bit */\n+#define R_X86_64_GOTOFF64\t25\t/* 64 bit offset to GOT */\n+#define R_X86_64_GOTPC32\t26\t/* 32 bit signed pc relative\n+\t\t\t\t\t   offset to GOT */\n+#define R_X86_64_GOT64\t\t27\t/* 64-bit GOT entry offset */\n+#define R_X86_64_GOTPCREL64\t28\t/* 64-bit PC relative offset\n+\t\t\t\t\t   to GOT entry */\n+#define R_X86_64_GOTPC64\t29\t/* 64-bit PC relative offset to GOT */\n+#define R_X86_64_GOTPLT64\t30 \t/* like GOT64, says PLT entry needed */\n+#define R_X86_64_PLTOFF64\t31\t/* 64-bit GOT relative offset\n+\t\t\t\t\t   to PLT entry */\n+#define R_X86_64_SIZE32\t\t32\t/* Size of symbol plus 32-bit addend */\n+#define R_X86_64_SIZE64\t\t33\t/* Size of symbol plus 64-bit addend */\n+#define R_X86_64_GOTPC32_TLSDESC 34\t/* GOT offset for TLS descriptor.  */\n+#define R_X86_64_TLSDESC_CALL   35\t/* Marker for call through TLS\n+\t\t\t\t\t   descriptor.  */\n+#define R_X86_64_TLSDESC        36\t/* TLS descriptor.  */\n+#define R_X86_64_IRELATIVE\t37\t/* Adjust indirectly by program base */\n+#define R_X86_64_RELATIVE64\t38\t/* 64-bit adjust by program base */\n+\n+#define R_X86_64_NUM\t\t39\n+\n+\n+/* AM33 relocations.  */\n+#define R_MN10300_NONE\t\t0\t/* No reloc.  */\n+#define R_MN10300_32\t\t1\t/* Direct 32 bit.  */\n+#define R_MN10300_16\t\t2\t/* Direct 16 bit.  */\n+#define R_MN10300_8\t\t3\t/* Direct 8 bit.  */\n+#define R_MN10300_PCREL32\t4\t/* PC-relative 32-bit.  */\n+#define R_MN10300_PCREL16\t5\t/* PC-relative 16-bit signed.  */\n+#define R_MN10300_PCREL8\t6\t/* PC-relative 8-bit signed.  */\n+#define R_MN10300_GNU_VTINHERIT\t7\t/* Ancient C++ vtable garbage... */\n+#define R_MN10300_GNU_VTENTRY\t8\t/* ... collection annotation.  */\n+#define R_MN10300_24\t\t9\t/* Direct 24 bit.  */\n+#define R_MN10300_GOTPC32\t10\t/* 32-bit PCrel offset to GOT.  */\n+#define R_MN10300_GOTPC16\t11\t/* 16-bit PCrel offset to GOT.  */\n+#define R_MN10300_GOTOFF32\t12\t/* 32-bit offset from GOT.  */\n+#define R_MN10300_GOTOFF24\t13\t/* 24-bit offset from GOT.  */\n+#define R_MN10300_GOTOFF16\t14\t/* 16-bit offset from GOT.  */\n+#define R_MN10300_PLT32\t\t15\t/* 32-bit PCrel to PLT entry.  */\n+#define R_MN10300_PLT16\t\t16\t/* 16-bit PCrel to PLT entry.  */\n+#define R_MN10300_GOT32\t\t17\t/* 32-bit offset to GOT entry.  */\n+#define R_MN10300_GOT24\t\t18\t/* 24-bit offset to GOT entry.  */\n+#define R_MN10300_GOT16\t\t19\t/* 16-bit offset to GOT entry.  */\n+#define R_MN10300_COPY\t\t20\t/* Copy symbol at runtime.  */\n+#define R_MN10300_GLOB_DAT\t21\t/* Create GOT entry.  */\n+#define R_MN10300_JMP_SLOT\t22\t/* Create PLT entry.  */\n+#define R_MN10300_RELATIVE\t23\t/* Adjust by program base.  */\n+\n+#define R_MN10300_NUM\t\t24\n+\n+\n+/* M32R relocs.  */\n+#define R_M32R_NONE\t\t0\t/* No reloc. */\n+#define R_M32R_16\t\t1\t/* Direct 16 bit. */\n+#define R_M32R_32\t\t2\t/* Direct 32 bit. */\n+#define R_M32R_24\t\t3\t/* Direct 24 bit. */\n+#define R_M32R_10_PCREL\t\t4\t/* PC relative 10 bit shifted. */\n+#define R_M32R_18_PCREL\t\t5\t/* PC relative 18 bit shifted. */\n+#define R_M32R_26_PCREL\t\t6\t/* PC relative 26 bit shifted. */\n+#define R_M32R_HI16_ULO\t\t7\t/* High 16 bit with unsigned low. */\n+#define R_M32R_HI16_SLO\t\t8\t/* High 16 bit with signed low. */\n+#define R_M32R_LO16\t\t9\t/* Low 16 bit. */\n+#define R_M32R_SDA16\t\t10\t/* 16 bit offset in SDA. */\n+#define R_M32R_GNU_VTINHERIT\t11\n+#define R_M32R_GNU_VTENTRY\t12\n+/* M32R relocs use SHT_RELA.  */\n+#define R_M32R_16_RELA\t\t33\t/* Direct 16 bit. */\n+#define R_M32R_32_RELA\t\t34\t/* Direct 32 bit. */\n+#define R_M32R_24_RELA\t\t35\t/* Direct 24 bit. */\n+#define R_M32R_10_PCREL_RELA\t36\t/* PC relative 10 bit shifted. */\n+#define R_M32R_18_PCREL_RELA\t37\t/* PC relative 18 bit shifted. */\n+#define R_M32R_26_PCREL_RELA\t38\t/* PC relative 26 bit shifted. */\n+#define R_M32R_HI16_ULO_RELA\t39\t/* High 16 bit with unsigned low */\n+#define R_M32R_HI16_SLO_RELA\t40\t/* High 16 bit with signed low */\n+#define R_M32R_LO16_RELA\t41\t/* Low 16 bit */\n+#define R_M32R_SDA16_RELA\t42\t/* 16 bit offset in SDA */\n+#define R_M32R_RELA_GNU_VTINHERIT\t43\n+#define R_M32R_RELA_GNU_VTENTRY\t44\n+#define R_M32R_REL32\t\t45\t/* PC relative 32 bit.  */\n+\n+#define R_M32R_GOT24\t\t48\t/* 24 bit GOT entry */\n+#define R_M32R_26_PLTREL\t49\t/* 26 bit PC relative to PLT shifted */\n+#define R_M32R_COPY\t\t50\t/* Copy symbol at runtime */\n+#define R_M32R_GLOB_DAT\t\t51\t/* Create GOT entry */\n+#define R_M32R_JMP_SLOT\t\t52\t/* Create PLT entry */\n+#define R_M32R_RELATIVE\t\t53\t/* Adjust by program base */\n+#define R_M32R_GOTOFF\t\t54\t/* 24 bit offset to GOT */\n+#define R_M32R_GOTPC24\t\t55\t/* 24 bit PC relative offset to GOT */\n+#define R_M32R_GOT16_HI_ULO\t56\t/* High 16 bit GOT entry with unsigned\n+\t\t\t\t\t   low */\n+#define R_M32R_GOT16_HI_SLO\t57\t/* High 16 bit GOT entry with signed\n+\t\t\t\t\t   low */\n+#define R_M32R_GOT16_LO\t\t58\t/* Low 16 bit GOT entry */\n+#define R_M32R_GOTPC_HI_ULO\t59\t/* High 16 bit PC relative offset to\n+\t\t\t\t\t   GOT with unsigned low */\n+#define R_M32R_GOTPC_HI_SLO\t60\t/* High 16 bit PC relative offset to\n+\t\t\t\t\t   GOT with signed low */\n+#define R_M32R_GOTPC_LO\t\t61\t/* Low 16 bit PC relative offset to\n+\t\t\t\t\t   GOT */\n+#define R_M32R_GOTOFF_HI_ULO\t62\t/* High 16 bit offset to GOT\n+\t\t\t\t\t   with unsigned low */\n+#define R_M32R_GOTOFF_HI_SLO\t63\t/* High 16 bit offset to GOT\n+\t\t\t\t\t   with signed low */\n+#define R_M32R_GOTOFF_LO\t64\t/* Low 16 bit offset to GOT */\n+#define R_M32R_NUM\t\t256\t/* Keep this the last entry. */\n+\n+\n+/* TILEPro relocations.  */\n+#define R_TILEPRO_NONE\t\t0\t/* No reloc */\n+#define R_TILEPRO_32\t\t1\t/* Direct 32 bit */\n+#define R_TILEPRO_16\t\t2\t/* Direct 16 bit */\n+#define R_TILEPRO_8\t\t3\t/* Direct 8 bit */\n+#define R_TILEPRO_32_PCREL\t4\t/* PC relative 32 bit */\n+#define R_TILEPRO_16_PCREL\t5\t/* PC relative 16 bit */\n+#define R_TILEPRO_8_PCREL\t6\t/* PC relative 8 bit */\n+#define R_TILEPRO_LO16\t\t7\t/* Low 16 bit */\n+#define R_TILEPRO_HI16\t\t8\t/* High 16 bit */\n+#define R_TILEPRO_HA16\t\t9\t/* High 16 bit, adjusted */\n+#define R_TILEPRO_COPY\t\t10\t/* Copy relocation */\n+#define R_TILEPRO_GLOB_DAT\t11\t/* Create GOT entry */\n+#define R_TILEPRO_JMP_SLOT\t12\t/* Create PLT entry */\n+#define R_TILEPRO_RELATIVE\t13\t/* Adjust by program base */\n+#define R_TILEPRO_BROFF_X1\t14\t/* X1 pipe branch offset */\n+#define R_TILEPRO_JOFFLONG_X1\t15\t/* X1 pipe jump offset */\n+#define R_TILEPRO_JOFFLONG_X1_PLT 16\t/* X1 pipe jump offset to PLT */\n+#define R_TILEPRO_IMM8_X0\t17\t/* X0 pipe 8-bit */\n+#define R_TILEPRO_IMM8_Y0\t18\t/* Y0 pipe 8-bit */\n+#define R_TILEPRO_IMM8_X1\t19\t/* X1 pipe 8-bit */\n+#define R_TILEPRO_IMM8_Y1\t20\t/* Y1 pipe 8-bit */\n+#define R_TILEPRO_MT_IMM15_X1\t21\t/* X1 pipe mtspr */\n+#define R_TILEPRO_MF_IMM15_X1\t22\t/* X1 pipe mfspr */\n+#define R_TILEPRO_IMM16_X0\t23\t/* X0 pipe 16-bit */\n+#define R_TILEPRO_IMM16_X1\t24\t/* X1 pipe 16-bit */\n+#define R_TILEPRO_IMM16_X0_LO\t25\t/* X0 pipe low 16-bit */\n+#define R_TILEPRO_IMM16_X1_LO\t26\t/* X1 pipe low 16-bit */\n+#define R_TILEPRO_IMM16_X0_HI\t27\t/* X0 pipe high 16-bit */\n+#define R_TILEPRO_IMM16_X1_HI\t28\t/* X1 pipe high 16-bit */\n+#define R_TILEPRO_IMM16_X0_HA\t29\t/* X0 pipe high 16-bit, adjusted */\n+#define R_TILEPRO_IMM16_X1_HA\t30\t/* X1 pipe high 16-bit, adjusted */\n+#define R_TILEPRO_IMM16_X0_PCREL 31\t/* X0 pipe PC relative 16 bit */\n+#define R_TILEPRO_IMM16_X1_PCREL 32\t/* X1 pipe PC relative 16 bit */\n+#define R_TILEPRO_IMM16_X0_LO_PCREL 33\t/* X0 pipe PC relative low 16 bit */\n+#define R_TILEPRO_IMM16_X1_LO_PCREL 34\t/* X1 pipe PC relative low 16 bit */\n+#define R_TILEPRO_IMM16_X0_HI_PCREL 35\t/* X0 pipe PC relative high 16 bit */\n+#define R_TILEPRO_IMM16_X1_HI_PCREL 36\t/* X1 pipe PC relative high 16 bit */\n+#define R_TILEPRO_IMM16_X0_HA_PCREL 37\t/* X0 pipe PC relative ha() 16 bit */\n+#define R_TILEPRO_IMM16_X1_HA_PCREL 38\t/* X1 pipe PC relative ha() 16 bit */\n+#define R_TILEPRO_IMM16_X0_GOT\t39\t/* X0 pipe 16-bit GOT offset */\n+#define R_TILEPRO_IMM16_X1_GOT\t40\t/* X1 pipe 16-bit GOT offset */\n+#define R_TILEPRO_IMM16_X0_GOT_LO 41\t/* X0 pipe low 16-bit GOT offset */\n+#define R_TILEPRO_IMM16_X1_GOT_LO 42\t/* X1 pipe low 16-bit GOT offset */\n+#define R_TILEPRO_IMM16_X0_GOT_HI 43\t/* X0 pipe high 16-bit GOT offset */\n+#define R_TILEPRO_IMM16_X1_GOT_HI 44\t/* X1 pipe high 16-bit GOT offset */\n+#define R_TILEPRO_IMM16_X0_GOT_HA 45\t/* X0 pipe ha() 16-bit GOT offset */\n+#define R_TILEPRO_IMM16_X1_GOT_HA 46\t/* X1 pipe ha() 16-bit GOT offset */\n+#define R_TILEPRO_MMSTART_X0\t47\t/* X0 pipe mm \"start\" */\n+#define R_TILEPRO_MMEND_X0\t48\t/* X0 pipe mm \"end\" */\n+#define R_TILEPRO_MMSTART_X1\t49\t/* X1 pipe mm \"start\" */\n+#define R_TILEPRO_MMEND_X1\t50\t/* X1 pipe mm \"end\" */\n+#define R_TILEPRO_SHAMT_X0\t51\t/* X0 pipe shift amount */\n+#define R_TILEPRO_SHAMT_X1\t52\t/* X1 pipe shift amount */\n+#define R_TILEPRO_SHAMT_Y0\t53\t/* Y0 pipe shift amount */\n+#define R_TILEPRO_SHAMT_Y1\t54\t/* Y1 pipe shift amount */\n+#define R_TILEPRO_DEST_IMM8_X1\t55\t/* X1 pipe destination 8-bit */\n+/* Relocs 56-59 are currently not defined.  */\n+#define R_TILEPRO_TLS_GD_CALL\t60\t/* \"jal\" for TLS GD */\n+#define R_TILEPRO_IMM8_X0_TLS_GD_ADD 61\t/* X0 pipe \"addi\" for TLS GD */\n+#define R_TILEPRO_IMM8_X1_TLS_GD_ADD 62\t/* X1 pipe \"addi\" for TLS GD */\n+#define R_TILEPRO_IMM8_Y0_TLS_GD_ADD 63\t/* Y0 pipe \"addi\" for TLS GD */\n+#define R_TILEPRO_IMM8_Y1_TLS_GD_ADD 64\t/* Y1 pipe \"addi\" for TLS GD */\n+#define R_TILEPRO_TLS_IE_LOAD\t65\t/* \"lw_tls\" for TLS IE */\n+#define R_TILEPRO_IMM16_X0_TLS_GD 66\t/* X0 pipe 16-bit TLS GD offset */\n+#define R_TILEPRO_IMM16_X1_TLS_GD 67\t/* X1 pipe 16-bit TLS GD offset */\n+#define R_TILEPRO_IMM16_X0_TLS_GD_LO 68\t/* X0 pipe low 16-bit TLS GD offset */\n+#define R_TILEPRO_IMM16_X1_TLS_GD_LO 69\t/* X1 pipe low 16-bit TLS GD offset */\n+#define R_TILEPRO_IMM16_X0_TLS_GD_HI 70\t/* X0 pipe high 16-bit TLS GD offset */\n+#define R_TILEPRO_IMM16_X1_TLS_GD_HI 71\t/* X1 pipe high 16-bit TLS GD offset */\n+#define R_TILEPRO_IMM16_X0_TLS_GD_HA 72\t/* X0 pipe ha() 16-bit TLS GD offset */\n+#define R_TILEPRO_IMM16_X1_TLS_GD_HA 73\t/* X1 pipe ha() 16-bit TLS GD offset */\n+#define R_TILEPRO_IMM16_X0_TLS_IE 74\t/* X0 pipe 16-bit TLS IE offset */\n+#define R_TILEPRO_IMM16_X1_TLS_IE 75\t/* X1 pipe 16-bit TLS IE offset */\n+#define R_TILEPRO_IMM16_X0_TLS_IE_LO 76\t/* X0 pipe low 16-bit TLS IE offset */\n+#define R_TILEPRO_IMM16_X1_TLS_IE_LO 77\t/* X1 pipe low 16-bit TLS IE offset */\n+#define R_TILEPRO_IMM16_X0_TLS_IE_HI 78\t/* X0 pipe high 16-bit TLS IE offset */\n+#define R_TILEPRO_IMM16_X1_TLS_IE_HI 79\t/* X1 pipe high 16-bit TLS IE offset */\n+#define R_TILEPRO_IMM16_X0_TLS_IE_HA 80\t/* X0 pipe ha() 16-bit TLS IE offset */\n+#define R_TILEPRO_IMM16_X1_TLS_IE_HA 81\t/* X1 pipe ha() 16-bit TLS IE offset */\n+#define R_TILEPRO_TLS_DTPMOD32\t82\t/* ID of module containing symbol */\n+#define R_TILEPRO_TLS_DTPOFF32\t83\t/* Offset in TLS block */\n+#define R_TILEPRO_TLS_TPOFF32\t84\t/* Offset in static TLS block */\n+#define R_TILEPRO_IMM16_X0_TLS_LE 85\t/* X0 pipe 16-bit TLS LE offset */\n+#define R_TILEPRO_IMM16_X1_TLS_LE 86\t/* X1 pipe 16-bit TLS LE offset */\n+#define R_TILEPRO_IMM16_X0_TLS_LE_LO 87\t/* X0 pipe low 16-bit TLS LE offset */\n+#define R_TILEPRO_IMM16_X1_TLS_LE_LO 88\t/* X1 pipe low 16-bit TLS LE offset */\n+#define R_TILEPRO_IMM16_X0_TLS_LE_HI 89\t/* X0 pipe high 16-bit TLS LE offset */\n+#define R_TILEPRO_IMM16_X1_TLS_LE_HI 90\t/* X1 pipe high 16-bit TLS LE offset */\n+#define R_TILEPRO_IMM16_X0_TLS_LE_HA 91\t/* X0 pipe ha() 16-bit TLS LE offset */\n+#define R_TILEPRO_IMM16_X1_TLS_LE_HA 92\t/* X1 pipe ha() 16-bit TLS LE offset */\n+\n+#define R_TILEPRO_GNU_VTINHERIT\t128\t/* GNU C++ vtable hierarchy */\n+#define R_TILEPRO_GNU_VTENTRY\t129\t/* GNU C++ vtable member usage */\n+\n+#define R_TILEPRO_NUM\t\t130\n+\n+\n+/* TILE-Gx relocations.  */\n+#define R_TILEGX_NONE\t\t0\t/* No reloc */\n+#define R_TILEGX_64\t\t1\t/* Direct 64 bit */\n+#define R_TILEGX_32\t\t2\t/* Direct 32 bit */\n+#define R_TILEGX_16\t\t3\t/* Direct 16 bit */\n+#define R_TILEGX_8\t\t4\t/* Direct 8 bit */\n+#define R_TILEGX_64_PCREL\t5\t/* PC relative 64 bit */\n+#define R_TILEGX_32_PCREL\t6\t/* PC relative 32 bit */\n+#define R_TILEGX_16_PCREL\t7\t/* PC relative 16 bit */\n+#define R_TILEGX_8_PCREL\t8\t/* PC relative 8 bit */\n+#define R_TILEGX_HW0\t\t9\t/* hword 0 16-bit */\n+#define R_TILEGX_HW1\t\t10\t/* hword 1 16-bit */\n+#define R_TILEGX_HW2\t\t11\t/* hword 2 16-bit */\n+#define R_TILEGX_HW3\t\t12\t/* hword 3 16-bit */\n+#define R_TILEGX_HW0_LAST\t13\t/* last hword 0 16-bit */\n+#define R_TILEGX_HW1_LAST\t14\t/* last hword 1 16-bit */\n+#define R_TILEGX_HW2_LAST\t15\t/* last hword 2 16-bit */\n+#define R_TILEGX_COPY\t\t16\t/* Copy relocation */\n+#define R_TILEGX_GLOB_DAT\t17\t/* Create GOT entry */\n+#define R_TILEGX_JMP_SLOT\t18\t/* Create PLT entry */\n+#define R_TILEGX_RELATIVE\t19\t/* Adjust by program base */\n+#define R_TILEGX_BROFF_X1\t20\t/* X1 pipe branch offset */\n+#define R_TILEGX_JUMPOFF_X1\t21\t/* X1 pipe jump offset */\n+#define R_TILEGX_JUMPOFF_X1_PLT\t22\t/* X1 pipe jump offset to PLT */\n+#define R_TILEGX_IMM8_X0\t23\t/* X0 pipe 8-bit */\n+#define R_TILEGX_IMM8_Y0\t24\t/* Y0 pipe 8-bit */\n+#define R_TILEGX_IMM8_X1\t25\t/* X1 pipe 8-bit */\n+#define R_TILEGX_IMM8_Y1\t26\t/* Y1 pipe 8-bit */\n+#define R_TILEGX_DEST_IMM8_X1\t27\t/* X1 pipe destination 8-bit */\n+#define R_TILEGX_MT_IMM14_X1\t28\t/* X1 pipe mtspr */\n+#define R_TILEGX_MF_IMM14_X1\t29\t/* X1 pipe mfspr */\n+#define R_TILEGX_MMSTART_X0\t30\t/* X0 pipe mm \"start\" */\n+#define R_TILEGX_MMEND_X0\t31\t/* X0 pipe mm \"end\" */\n+#define R_TILEGX_SHAMT_X0\t32\t/* X0 pipe shift amount */\n+#define R_TILEGX_SHAMT_X1\t33\t/* X1 pipe shift amount */\n+#define R_TILEGX_SHAMT_Y0\t34\t/* Y0 pipe shift amount */\n+#define R_TILEGX_SHAMT_Y1\t35\t/* Y1 pipe shift amount */\n+#define R_TILEGX_IMM16_X0_HW0\t36\t/* X0 pipe hword 0 */\n+#define R_TILEGX_IMM16_X1_HW0\t37\t/* X1 pipe hword 0 */\n+#define R_TILEGX_IMM16_X0_HW1\t38\t/* X0 pipe hword 1 */\n+#define R_TILEGX_IMM16_X1_HW1\t39\t/* X1 pipe hword 1 */\n+#define R_TILEGX_IMM16_X0_HW2\t40\t/* X0 pipe hword 2 */\n+#define R_TILEGX_IMM16_X1_HW2\t41\t/* X1 pipe hword 2 */\n+#define R_TILEGX_IMM16_X0_HW3\t42\t/* X0 pipe hword 3 */\n+#define R_TILEGX_IMM16_X1_HW3\t43\t/* X1 pipe hword 3 */\n+#define R_TILEGX_IMM16_X0_HW0_LAST 44\t/* X0 pipe last hword 0 */\n+#define R_TILEGX_IMM16_X1_HW0_LAST 45\t/* X1 pipe last hword 0 */\n+#define R_TILEGX_IMM16_X0_HW1_LAST 46\t/* X0 pipe last hword 1 */\n+#define R_TILEGX_IMM16_X1_HW1_LAST 47\t/* X1 pipe last hword 1 */\n+#define R_TILEGX_IMM16_X0_HW2_LAST 48\t/* X0 pipe last hword 2 */\n+#define R_TILEGX_IMM16_X1_HW2_LAST 49\t/* X1 pipe last hword 2 */\n+#define R_TILEGX_IMM16_X0_HW0_PCREL 50\t/* X0 pipe PC relative hword 0 */\n+#define R_TILEGX_IMM16_X1_HW0_PCREL 51\t/* X1 pipe PC relative hword 0 */\n+#define R_TILEGX_IMM16_X0_HW1_PCREL 52\t/* X0 pipe PC relative hword 1 */\n+#define R_TILEGX_IMM16_X1_HW1_PCREL 53\t/* X1 pipe PC relative hword 1 */\n+#define R_TILEGX_IMM16_X0_HW2_PCREL 54\t/* X0 pipe PC relative hword 2 */\n+#define R_TILEGX_IMM16_X1_HW2_PCREL 55\t/* X1 pipe PC relative hword 2 */\n+#define R_TILEGX_IMM16_X0_HW3_PCREL 56\t/* X0 pipe PC relative hword 3 */\n+#define R_TILEGX_IMM16_X1_HW3_PCREL 57\t/* X1 pipe PC relative hword 3 */\n+#define R_TILEGX_IMM16_X0_HW0_LAST_PCREL 58 /* X0 pipe PC-rel last hword 0 */\n+#define R_TILEGX_IMM16_X1_HW0_LAST_PCREL 59 /* X1 pipe PC-rel last hword 0 */\n+#define R_TILEGX_IMM16_X0_HW1_LAST_PCREL 60 /* X0 pipe PC-rel last hword 1 */\n+#define R_TILEGX_IMM16_X1_HW1_LAST_PCREL 61 /* X1 pipe PC-rel last hword 1 */\n+#define R_TILEGX_IMM16_X0_HW2_LAST_PCREL 62 /* X0 pipe PC-rel last hword 2 */\n+#define R_TILEGX_IMM16_X1_HW2_LAST_PCREL 63 /* X1 pipe PC-rel last hword 2 */\n+#define R_TILEGX_IMM16_X0_HW0_GOT 64\t/* X0 pipe hword 0 GOT offset */\n+#define R_TILEGX_IMM16_X1_HW0_GOT 65\t/* X1 pipe hword 0 GOT offset */\n+/* Relocs 66-71 are currently not defined.  */\n+#define R_TILEGX_IMM16_X0_HW0_LAST_GOT 72 /* X0 pipe last hword 0 GOT offset */\n+#define R_TILEGX_IMM16_X1_HW0_LAST_GOT 73 /* X1 pipe last hword 0 GOT offset */\n+#define R_TILEGX_IMM16_X0_HW1_LAST_GOT 74 /* X0 pipe last hword 1 GOT offset */\n+#define R_TILEGX_IMM16_X1_HW1_LAST_GOT 75 /* X1 pipe last hword 1 GOT offset */\n+/* Relocs 76-77 are currently not defined.  */\n+#define R_TILEGX_IMM16_X0_HW0_TLS_GD 78\t/* X0 pipe hword 0 TLS GD offset */\n+#define R_TILEGX_IMM16_X1_HW0_TLS_GD 79\t/* X1 pipe hword 0 TLS GD offset */\n+#define R_TILEGX_IMM16_X0_HW0_TLS_LE 80\t/* X0 pipe hword 0 TLS LE offset */\n+#define R_TILEGX_IMM16_X1_HW0_TLS_LE 81\t/* X1 pipe hword 0 TLS LE offset */\n+#define R_TILEGX_IMM16_X0_HW0_LAST_TLS_LE 82 /* X0 pipe last hword 0 LE off */\n+#define R_TILEGX_IMM16_X1_HW0_LAST_TLS_LE 83 /* X1 pipe last hword 0 LE off */\n+#define R_TILEGX_IMM16_X0_HW1_LAST_TLS_LE 84 /* X0 pipe last hword 1 LE off */\n+#define R_TILEGX_IMM16_X1_HW1_LAST_TLS_LE 85 /* X1 pipe last hword 1 LE off */\n+#define R_TILEGX_IMM16_X0_HW0_LAST_TLS_GD 86 /* X0 pipe last hword 0 GD off */\n+#define R_TILEGX_IMM16_X1_HW0_LAST_TLS_GD 87 /* X1 pipe last hword 0 GD off */\n+#define R_TILEGX_IMM16_X0_HW1_LAST_TLS_GD 88 /* X0 pipe last hword 1 GD off */\n+#define R_TILEGX_IMM16_X1_HW1_LAST_TLS_GD 89 /* X1 pipe last hword 1 GD off */\n+/* Relocs 90-91 are currently not defined.  */\n+#define R_TILEGX_IMM16_X0_HW0_TLS_IE 92\t/* X0 pipe hword 0 TLS IE offset */\n+#define R_TILEGX_IMM16_X1_HW0_TLS_IE 93\t/* X1 pipe hword 0 TLS IE offset */\n+/* Relocs 94-99 are currently not defined.  */\n+#define R_TILEGX_IMM16_X0_HW0_LAST_TLS_IE 100 /* X0 pipe last hword 0 IE off */\n+#define R_TILEGX_IMM16_X1_HW0_LAST_TLS_IE 101 /* X1 pipe last hword 0 IE off */\n+#define R_TILEGX_IMM16_X0_HW1_LAST_TLS_IE 102 /* X0 pipe last hword 1 IE off */\n+#define R_TILEGX_IMM16_X1_HW1_LAST_TLS_IE 103 /* X1 pipe last hword 1 IE off */\n+/* Relocs 104-105 are currently not defined.  */\n+#define R_TILEGX_TLS_DTPMOD64\t106\t/* 64-bit ID of symbol's module */\n+#define R_TILEGX_TLS_DTPOFF64\t107\t/* 64-bit offset in TLS block */\n+#define R_TILEGX_TLS_TPOFF64\t108\t/* 64-bit offset in static TLS block */\n+#define R_TILEGX_TLS_DTPMOD32\t109\t/* 32-bit ID of symbol's module */\n+#define R_TILEGX_TLS_DTPOFF32\t110\t/* 32-bit offset in TLS block */\n+#define R_TILEGX_TLS_TPOFF32\t111\t/* 32-bit offset in static TLS block */\n+#define R_TILEGX_TLS_GD_CALL\t112\t/* \"jal\" for TLS GD */\n+#define R_TILEGX_IMM8_X0_TLS_GD_ADD 113\t/* X0 pipe \"addi\" for TLS GD */\n+#define R_TILEGX_IMM8_X1_TLS_GD_ADD 114\t/* X1 pipe \"addi\" for TLS GD */\n+#define R_TILEGX_IMM8_Y0_TLS_GD_ADD 115\t/* Y0 pipe \"addi\" for TLS GD */\n+#define R_TILEGX_IMM8_Y1_TLS_GD_ADD 116\t/* Y1 pipe \"addi\" for TLS GD */\n+#define R_TILEGX_TLS_IE_LOAD\t117\t/* \"ld_tls\" for TLS IE */\n+#define R_TILEGX_IMM8_X0_TLS_ADD 118\t/* X0 pipe \"addi\" for TLS GD/IE */\n+#define R_TILEGX_IMM8_X1_TLS_ADD 119\t/* X1 pipe \"addi\" for TLS GD/IE */\n+#define R_TILEGX_IMM8_Y0_TLS_ADD 120\t/* Y0 pipe \"addi\" for TLS GD/IE */\n+#define R_TILEGX_IMM8_Y1_TLS_ADD 121\t/* Y1 pipe \"addi\" for TLS GD/IE */\n+\n+#define R_TILEGX_GNU_VTINHERIT\t128\t/* GNU C++ vtable hierarchy */\n+#define R_TILEGX_GNU_VTENTRY\t129\t/* GNU C++ vtable member usage */\n+\n+#define R_TILEGX_NUM\t\t130\n+\n+#endif\t/* elf.h */\n--- a/scripts/mod/mk_elfconfig.c\n+++ b/scripts/mod/mk_elfconfig.c\n@@ -2,7 +2,11 @@\n #include <stdio.h>\n #include <stdlib.h>\n #include <string.h>\n+#ifndef __APPLE__\n #include <elf.h>\n+#else\n+#include \"elf.h\"\n+#endif\n \n int\n main(int argc, char **argv)\n--- a/scripts/mod/modpost.h\n+++ b/scripts/mod/modpost.h\n@@ -8,7 +8,11 @@\n #include <sys/mman.h>\n #include <fcntl.h>\n #include <unistd.h>\n+#if !(defined(__APPLE__) || defined(__CYGWIN__))\n #include <elf.h>\n+#else\n+#include \"elf.h\"\n+#endif\n \n #include \"elfconfig.h\"\n \n"
  },
  {
    "path": "target/linux/generic/hack-5.10/211-darwin-uuid-typedef-clash.patch",
    "content": "From e44fc2af1ddc452b6659d08c16973d65c73b7d0a Mon Sep 17 00:00:00 2001\nFrom: Kevin Darbyshire-Bryant <ldir@darbyshire-bryant.me.uk>\nDate: Wed, 5 Feb 2020 18:36:43 +0000\nSubject: [PATCH] file2alias: build on macos\n\nSigned-off-by: Kevin Darbyshire-Bryant <ldir@darbyshire-bryant.me.uk>\n---\n scripts/mod/file2alias.c | 3 +++\n 1 file changed, 3 insertions(+)\n\n--- a/scripts/mod/file2alias.c\n+++ b/scripts/mod/file2alias.c\n@@ -38,6 +38,9 @@ typedef struct {\n \t__u8 b[16];\n } guid_t;\n \n+#ifdef __APPLE__\n+#define uuid_t compat_uuid_t\n+#endif\n /* backwards compatibility, don't use in new code */\n typedef struct {\n \t__u8 b[16];\n"
  },
  {
    "path": "target/linux/generic/hack-5.10/212-tools_portability.patch",
    "content": "From 48232d3d931c95953ce2ddfe7da7bb164aef6a73 Mon Sep 17 00:00:00 2001\nFrom: Felix Fietkau <nbd@nbd.name>\nDate: Fri, 7 Jul 2017 17:03:16 +0200\nSubject: fix portability of some includes files in tools/ used on the host\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n tools/include/tools/be_byteshift.h |  4 ++++\n tools/include/tools/le_byteshift.h |  4 ++++\n tools/include/tools/linux_types.h  | 22 ++++++++++++++++++++++\n 3 files changed, 30 insertions(+)\n create mode 100644 tools/include/tools/linux_types.h\n\n--- a/tools/include/tools/be_byteshift.h\n+++ b/tools/include/tools/be_byteshift.h\n@@ -2,6 +2,10 @@\n #ifndef _TOOLS_BE_BYTESHIFT_H\n #define _TOOLS_BE_BYTESHIFT_H\n \n+#ifndef __linux__\n+#include \"linux_types.h\"\n+#endif\n+\n #include <stdint.h>\n \n static inline uint16_t __get_unaligned_be16(const uint8_t *p)\n--- a/tools/include/tools/le_byteshift.h\n+++ b/tools/include/tools/le_byteshift.h\n@@ -2,6 +2,10 @@\n #ifndef _TOOLS_LE_BYTESHIFT_H\n #define _TOOLS_LE_BYTESHIFT_H\n \n+#ifndef __linux__\n+#include \"linux_types.h\"\n+#endif\n+\n #include <stdint.h>\n \n static inline uint16_t __get_unaligned_le16(const uint8_t *p)\n--- /dev/null\n+++ b/tools/include/tools/linux_types.h\n@@ -0,0 +1,26 @@\n+#ifndef __LINUX_TYPES_H\n+#define __LINUX_TYPES_H\n+\n+#include <stdint.h>\n+\n+typedef int8_t __s8;\n+typedef uint8_t __u8;\n+typedef uint8_t __be8;\n+typedef uint8_t __le8;\n+\n+typedef int16_t __s16;\n+typedef uint16_t __u16;\n+typedef uint16_t __be16;\n+typedef uint16_t __le16;\n+\n+typedef int32_t __s32;\n+typedef uint32_t __u32;\n+typedef uint32_t __be32;\n+typedef uint32_t __le32;\n+\n+typedef int64_t __s64;\n+typedef uint64_t __u64;\n+typedef uint64_t __be64;\n+typedef uint64_t __le64;\n+\n+#endif\n--- a/tools/include/linux/types.h\n+++ b/tools/include/linux/types.h\n@@ -7,8 +7,12 @@\n #include <stdint.h>\n \n #define __SANE_USERSPACE_TYPES__\t/* For PPC64, to get LL64 types */\n+#ifndef __linux__\n+#include <tools/linux_types.h>\n+#else\n #include <asm/types.h>\n #include <asm/posix_types.h>\n+#endif\n \n struct page;\n struct kmem_cache;\n--- a/tools/perf/pmu-events/jevents.c\n+++ b/tools/perf/pmu-events/jevents.c\n@@ -1,4 +1,6 @@\n+#ifdef __linux__\n #define  _XOPEN_SOURCE 500\t/* needed for nftw() */\n+#endif\n #define  _GNU_SOURCE\t\t/* needed for asprintf() */\n \n /* Parse event JSON files */\n@@ -35,6 +37,7 @@\n #include <stdlib.h>\n #include <errno.h>\n #include <string.h>\n+#include <strings.h>\n #include <ctype.h>\n #include <unistd.h>\n #include <stdarg.h>\n--- a/tools/perf/pmu-events/json.c\n+++ b/tools/perf/pmu-events/json.c\n@@ -38,7 +38,6 @@\n #include <unistd.h>\n #include \"jsmn.h\"\n #include \"json.h\"\n-#include <linux/kernel.h>\n \n \n static char *mapfile(const char *fn, size_t *size)\n"
  },
  {
    "path": "target/linux/generic/hack-5.10/214-spidev_h_portability.patch",
    "content": "From be9be95ff10e16a5b4ad36f903978d0cc5747024 Mon Sep 17 00:00:00 2001\nFrom: Felix Fietkau <nbd@nbd.name>\nDate: Fri, 7 Jul 2017 17:04:08 +0200\nSubject: kernel: fix linux/spi/spidev.h portability issues with musl\n\nFelix will try to get this define included into musl\n\nlede-commit: 795e7cf60de19e7a076a46874fab7bb88b43bbff\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n include/uapi/linux/spi/spidev.h | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/include/uapi/linux/spi/spidev.h\n+++ b/include/uapi/linux/spi/spidev.h\n@@ -121,7 +121,7 @@ struct spi_ioc_transfer {\n \n /* not all platforms use <asm-generic/ioctl.h> or _IOC_TYPECHECK() ... */\n #define SPI_MSGSIZE(N) \\\n-\t((((N)*(sizeof (struct spi_ioc_transfer))) < (1 << _IOC_SIZEBITS)) \\\n+\t((((N)*(sizeof (struct spi_ioc_transfer))) < (1 << 13)) \\\n \t\t? ((N)*(sizeof (struct spi_ioc_transfer))) : 0)\n #define SPI_IOC_MESSAGE(N) _IOW(SPI_IOC_MAGIC, 0, char[SPI_MSGSIZE(N)])\n \n"
  },
  {
    "path": "target/linux/generic/hack-5.10/220-arm-gc_sections.patch",
    "content": "From e3d8676f5722b7622685581e06e8f53e6138e3ab Mon Sep 17 00:00:00 2001\nFrom: Felix Fietkau <nbd@nbd.name>\nDate: Sat, 15 Jul 2017 23:42:36 +0200\nSubject: use -ffunction-sections, -fdata-sections and --gc-sections\n\nIn combination with kernel symbol export stripping this significantly reduces\nthe kernel image size. Used on both ARM and MIPS architectures.\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\nSigned-off-by: Jonas Gorski <jogo@openwrt.org>\nSigned-off-by: Gabor Juhos <juhosg@openwrt.org>\n---\n--- a/arch/arm/Kconfig\n+++ b/arch/arm/Kconfig\n@@ -114,6 +114,7 @@ config ARM\n \tselect HAVE_UID16\n \tselect HAVE_VIRT_CPU_ACCOUNTING_GEN\n \tselect IRQ_FORCED_THREADING\n+\tselect HAVE_LD_DEAD_CODE_DATA_ELIMINATION\n \tselect MODULES_USE_ELF_REL\n \tselect NEED_DMA_MAP_STATE\n \tselect OF_EARLY_FLATTREE if OF\n--- a/arch/arm/boot/compressed/Makefile\n+++ b/arch/arm/boot/compressed/Makefile\n@@ -100,6 +100,7 @@ $(foreach o, $(libfdt_objs) atags_to_fdt\n ifdef building_out_of_srctree\n $(shell rm -f $(addprefix $(obj)/, fdt_rw.c fdt_ro.c fdt_wip.c fdt.c))\n endif\n+KBUILD_CFLAGS_KERNEL := $(patsubst -f%-sections,,$(KBUILD_CFLAGS_KERNEL))\n \n targets       := vmlinux vmlinux.lds piggy_data piggy.o \\\n \t\t lib1funcs.o ashldi3.o bswapsdi2.o \\\n--- a/arch/arm/kernel/vmlinux.lds.S\n+++ b/arch/arm/kernel/vmlinux.lds.S\n@@ -75,7 +75,7 @@ SECTIONS\n \t. = ALIGN(4);\n \t__ex_table : AT(ADDR(__ex_table) - LOAD_OFFSET) {\n \t\t__start___ex_table = .;\n-\t\tARM_MMU_KEEP(*(__ex_table))\n+\t\tKEEP(*(__ex_table))\n \t\t__stop___ex_table = .;\n \t}\n \n@@ -100,24 +100,24 @@ SECTIONS\n \t}\n \t.init.arch.info : {\n \t\t__arch_info_begin = .;\n-\t\t*(.arch.info.init)\n+\t\tKEEP(*(.arch.info.init))\n \t\t__arch_info_end = .;\n \t}\n \t.init.tagtable : {\n \t\t__tagtable_begin = .;\n-\t\t*(.taglist.init)\n+\t\tKEEP(*(.taglist.init))\n \t\t__tagtable_end = .;\n \t}\n #ifdef CONFIG_SMP_ON_UP\n \t.init.smpalt : {\n \t\t__smpalt_begin = .;\n-\t\t*(.alt.smp.init)\n+\t\tKEEP(*(.alt.smp.init))\n \t\t__smpalt_end = .;\n \t}\n #endif\n \t.init.pv_table : {\n \t\t__pv_table_begin = .;\n-\t\t*(.pv_table)\n+\t\tKEEP(*(.pv_table))\n \t\t__pv_table_end = .;\n \t}\n \n--- a/arch/arm/include/asm/vmlinux.lds.h\n+++ b/arch/arm/include/asm/vmlinux.lds.h\n@@ -42,13 +42,13 @@\n #define PROC_INFO\t\t\t\t\t\t\t\\\n \t\t. = ALIGN(4);\t\t\t\t\t\t\\\n \t\t__proc_info_begin = .;\t\t\t\t\t\\\n-\t\t*(.proc.info.init)\t\t\t\t\t\\\n+\t\tKEEP(*(.proc.info.init))\t\t\t\t\\\n \t\t__proc_info_end = .;\n \n #define IDMAP_TEXT\t\t\t\t\t\t\t\\\n \t\tALIGN_FUNCTION();\t\t\t\t\t\\\n \t\t__idmap_text_start = .;\t\t\t\t\t\\\n-\t\t*(.idmap.text)\t\t\t\t\t\t\\\n+\t\tKEEP(*(.idmap.text))\t\t\t\t\t\\\n \t\t__idmap_text_end = .;\t\t\t\t\t\\\n \n #define ARM_DISCARD\t\t\t\t\t\t\t\\\n@@ -109,12 +109,12 @@\n \t. = ALIGN(8);\t\t\t\t\t\t\t\\\n \t.ARM.unwind_idx : {\t\t\t\t\t\t\\\n \t\t__start_unwind_idx = .;\t\t\t\t\t\\\n-\t\t*(.ARM.exidx*)\t\t\t\t\t\t\\\n+\t\tKEEP(*(.ARM.exidx*))\t\t\t\t\t\\\n \t\t__stop_unwind_idx = .;\t\t\t\t\t\\\n \t}\t\t\t\t\t\t\t\t\\\n \t.ARM.unwind_tab : {\t\t\t\t\t\t\\\n \t\t__start_unwind_tab = .;\t\t\t\t\t\\\n-\t\t*(.ARM.extab*)\t\t\t\t\t\t\\\n+\t\tKEEP(*(.ARM.extab*))\t\t\t\t\t\\\n \t\t__stop_unwind_tab = .;\t\t\t\t\t\\\n \t}\n \n@@ -126,7 +126,7 @@\n \t__vectors_lma = .;\t\t\t\t\t\t\\\n \tOVERLAY 0xffff0000 : NOCROSSREFS AT(__vectors_lma) {\t\t\\\n \t\t.vectors {\t\t\t\t\t\t\\\n-\t\t\t*(.vectors)\t\t\t\t\t\\\n+\t\t\tKEEP(*(.vectors))\t\t\t\t\\\n \t\t}\t\t\t\t\t\t\t\\\n \t\t.vectors.bhb.loop8 {\t\t\t\t\t\\\n \t\t\t*(.vectors.bhb.loop8)\t\t\t\t\\\n@@ -144,7 +144,7 @@\n \t\t\t\t\t\t\t\t\t\\\n \t__stubs_lma = .;\t\t\t\t\t\t\\\n \t.stubs ADDR(.vectors) + 0x1000 : AT(__stubs_lma) {\t\t\\\n-\t\t*(.stubs)\t\t\t\t\t\t\\\n+\t\tKEEP(*(.stubs))\t\t\t\t\t\t\\\n \t}\t\t\t\t\t\t\t\t\\\n \tARM_LMA(__stubs, .stubs);\t\t\t\t\t\\\n \t. = __stubs_lma + SIZEOF(.stubs);\t\t\t\t\\\n"
  },
  {
    "path": "target/linux/generic/hack-5.10/221-module_exports.patch",
    "content": "From b14784e7883390c20ed3ff904892255404a5914b Mon Sep 17 00:00:00 2001\nFrom: Felix Fietkau <nbd@nbd.name>\nDate: Fri, 7 Jul 2017 17:05:53 +0200\nSubject: add an optional config option for stripping all unnecessary symbol exports from the kernel image\n\nlede-commit: bb5a40c64b7c4f4848509fa0a6625055fc9e66cc\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n include/asm-generic/vmlinux.lds.h | 18 +++++++++++++++---\n include/linux/export.h            |  9 ++++++++-\n scripts/Makefile.build            |  2 +-\n 3 files changed, 24 insertions(+), 5 deletions(-)\n\n--- a/include/asm-generic/vmlinux.lds.h\n+++ b/include/asm-generic/vmlinux.lds.h\n@@ -81,6 +81,16 @@\n #define RO_EXCEPTION_TABLE\n #endif\n \n+#ifndef SYMTAB_KEEP\n+#define SYMTAB_KEEP KEEP(*(SORT(___ksymtab+*)))\n+#define SYMTAB_KEEP_GPL KEEP(*(SORT(___ksymtab_gpl+*)))\n+#endif\n+\n+#ifndef SYMTAB_DISCARD\n+#define SYMTAB_DISCARD\n+#define SYMTAB_DISCARD_GPL\n+#endif\n+\n /* Align . to a 8 byte boundary equals to maximum function alignment. */\n #define ALIGN_FUNCTION()  . = ALIGN(8)\n \n@@ -473,14 +483,14 @@\n \t/* Kernel symbol table: Normal symbols */\t\t\t\\\n \t__ksymtab         : AT(ADDR(__ksymtab) - LOAD_OFFSET) {\t\t\\\n \t\t__start___ksymtab = .;\t\t\t\t\t\\\n-\t\tKEEP(*(SORT(___ksymtab+*)))\t\t\t\t\\\n+\t\tSYMTAB_KEEP\t\t\t\t\t\t\\\n \t\t__stop___ksymtab = .;\t\t\t\t\t\\\n \t}\t\t\t\t\t\t\t\t\\\n \t\t\t\t\t\t\t\t\t\\\n \t/* Kernel symbol table: GPL-only symbols */\t\t\t\\\n \t__ksymtab_gpl     : AT(ADDR(__ksymtab_gpl) - LOAD_OFFSET) {\t\\\n \t\t__start___ksymtab_gpl = .;\t\t\t\t\\\n-\t\tKEEP(*(SORT(___ksymtab_gpl+*)))\t\t\t\t\\\n+\t\tSYMTAB_KEEP_GPL\t\t\t\t\t\t\\\n \t\t__stop___ksymtab_gpl = .;\t\t\t\t\\\n \t}\t\t\t\t\t\t\t\t\\\n \t\t\t\t\t\t\t\t\t\\\n@@ -542,7 +552,7 @@\n \t\t\t\t\t\t\t\t\t\\\n \t/* Kernel symbol table: strings */\t\t\t\t\\\n         __ksymtab_strings : AT(ADDR(__ksymtab_strings) - LOAD_OFFSET) {\t\\\n-\t\t*(__ksymtab_strings)\t\t\t\t\t\\\n+\t\t*(__ksymtab_strings+*)\t\t\t\t\t\\\n \t}\t\t\t\t\t\t\t\t\\\n \t\t\t\t\t\t\t\t\t\\\n \t/* __*init sections */\t\t\t\t\t\t\\\n@@ -1019,6 +1029,8 @@\n \n #define COMMON_DISCARDS\t\t\t\t\t\t\t\\\n \tSANITIZER_DISCARDS\t\t\t\t\t\t\\\n+\tSYMTAB_DISCARD\t\t\t\t\t\t\t\\\n+\tSYMTAB_DISCARD_GPL\t\t\t\t\t\t\\\n \t*(.discard)\t\t\t\t\t\t\t\\\n \t*(.discard.*)\t\t\t\t\t\t\t\\\n \t*(.modinfo)\t\t\t\t\t\t\t\\\n--- a/include/linux/export.h\n+++ b/include/linux/export.h\n@@ -82,6 +82,12 @@ struct kernel_symbol {\n \n #else\n \n+#ifdef MODULE\n+#define __EXPORT_SUFFIX(sym)\n+#else\n+#define __EXPORT_SUFFIX(sym) \"+\" #sym\n+#endif\n+\n /*\n  * For every exported symbol, do the following:\n  *\n@@ -99,7 +105,7 @@ struct kernel_symbol {\n \textern const char __kstrtab_##sym[];\t\t\t\t\t\\\n \textern const char __kstrtabns_##sym[];\t\t\t\t\t\\\n \t__CRC_SYMBOL(sym, sec);\t\t\t\t\t\t\t\\\n-\tasm(\"\t.section \\\"__ksymtab_strings\\\",\\\"aMS\\\",%progbits,1\t\\n\"\t\\\n+\tasm(\"\t.section \\\"__ksymtab_strings\" __EXPORT_SUFFIX(sym) \"\\\",\\\"aMS\\\",%progbits,1\t\\n\"\t\\\n \t    \"__kstrtab_\" #sym \":\t\t\t\t\t\\n\"\t\\\n \t    \"\t.asciz \t\\\"\" #sym \"\\\"\t\t\t\t\t\\n\"\t\\\n \t    \"__kstrtabns_\" #sym \":\t\t\t\t\t\\n\"\t\\\n--- a/scripts/Makefile.build\n+++ b/scripts/Makefile.build\n@@ -367,7 +367,7 @@ targets += $(lib-y) $(always-y) $(MAKECM\n # Linker scripts preprocessor (.lds.S -> .lds)\n # ---------------------------------------------------------------------------\n quiet_cmd_cpp_lds_S = LDS     $@\n-      cmd_cpp_lds_S = $(CPP) $(cpp_flags) -P -U$(ARCH) \\\n+      cmd_cpp_lds_S = $(CPP) $(EXTRA_LDSFLAGS) $(cpp_flags) -P -U$(ARCH) \\\n \t                     -D__ASSEMBLY__ -DLINKER_SCRIPT -o $@ $<\n \n $(obj)/%.lds: $(src)/%.lds.S FORCE\n"
  },
  {
    "path": "target/linux/generic/hack-5.10/230-openwrt_lzma_options.patch",
    "content": "From b3d00b452467f621317953d9e4c6f9ae8dcfd271 Mon Sep 17 00:00:00 2001\nFrom: Imre Kaloz <kaloz@openwrt.org>\nDate: Fri, 7 Jul 2017 17:06:55 +0200\nSubject: use the openwrt lzma options for now\n\nlede-commit: 548de949f392049420a6a1feeef118b30ab8ea8c\nSigned-off-by: Imre Kaloz <kaloz@openwrt.org>\n---\n lib/decompress.c              |  1 +\n scripts/Makefile.lib          |  2 +-\n usr/gen_initramfs_list.sh | 10 +++++-----\n 3 files changed, 7 insertions(+), 6 deletions(-)\n\n--- a/lib/decompress.c\n+++ b/lib/decompress.c\n@@ -53,6 +53,7 @@ static const struct compress_format comp\n \t{ {0x1f, 0x9e}, \"gzip\", gunzip },\n \t{ {0x42, 0x5a}, \"bzip2\", bunzip2 },\n \t{ {0x5d, 0x00}, \"lzma\", unlzma },\n+\t{ {0x6d, 0x00}, \"lzma-openwrt\", unlzma },\n \t{ {0xfd, 0x37}, \"xz\", unxz },\n \t{ {0x89, 0x4c}, \"lzo\", unlzo },\n \t{ {0x02, 0x21}, \"lz4\", unlz4 },\n--- a/scripts/Makefile.lib\n+++ b/scripts/Makefile.lib\n@@ -370,7 +370,7 @@ quiet_cmd_bzip2 = BZIP2   $@\n # ---------------------------------------------------------------------------\n \n quiet_cmd_lzma = LZMA    $@\n-      cmd_lzma = { cat $(real-prereqs) | $(LZMA) -9; $(size_append); } > $@\n+      cmd_lzma = { cat $(real-prereqs) | $(LZMA) e -d20 -lc1 -lp2 -pb2 -eos -si -so; $(size_append); } > $@\n \n quiet_cmd_lzo = LZO     $@\n       cmd_lzo = { cat $(real-prereqs) | $(KLZOP) -9; $(size_append); } > $@\n"
  },
  {
    "path": "target/linux/generic/hack-5.10/249-udp-tunnel-selection.patch",
    "content": "--- a/net/ipv4/Kconfig\n+++ b/net/ipv4/Kconfig\n@@ -315,7 +315,7 @@ config NET_IPVTI\n \t  on top.\n \n config NET_UDP_TUNNEL\n-\ttristate\n+\ttristate \"IP: UDP tunneling support\"\n \tselect NET_IP_TUNNEL\n \tdefault n\n \n"
  },
  {
    "path": "target/linux/generic/hack-5.10/250-netfilter_depends.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nSubject: hack: net: remove bogus netfilter dependencies\n\nlede-commit: 589d2a377dee27d206fc3725325309cf649e4df6\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n net/netfilter/Kconfig | 2 --\n 1 file changed, 2 deletions(-)\n\n--- a/net/netfilter/Kconfig\n+++ b/net/netfilter/Kconfig\n@@ -228,7 +228,6 @@ config NF_CONNTRACK_FTP\n \n config NF_CONNTRACK_H323\n \ttristate \"H.323 protocol support\"\n-\tdepends on IPV6 || IPV6=n\n \tdepends on NETFILTER_ADVANCED\n \thelp\n \t  H.323 is a VoIP signalling protocol from ITU-T. As one of the most\n@@ -1072,7 +1071,6 @@ config NETFILTER_XT_TARGET_SECMARK\n \n config NETFILTER_XT_TARGET_TCPMSS\n \ttristate '\"TCPMSS\" target support'\n-\tdepends on IPV6 || IPV6=n\n \tdefault m if NETFILTER_ADVANCED=n\n \thelp\n \t  This option adds a `TCPMSS' target, which allows you to alter the\n"
  },
  {
    "path": "target/linux/generic/hack-5.10/251-kconfig.patch",
    "content": "From da3c50704f14132f4adf80d48e9a4cd5d46e54c9 Mon Sep 17 00:00:00 2001\nFrom: John Crispin <john@phrozen.org>\nDate: Fri, 7 Jul 2017 17:09:21 +0200\nSubject: kconfig: owrt specifc dependencies\n\nSigned-off-by: John Crispin <john@phrozen.org>\n---\n crypto/Kconfig        | 10 +++++-----\n drivers/bcma/Kconfig  |  1 +\n drivers/ssb/Kconfig   |  3 ++-\n lib/Kconfig           |  8 ++++----\n net/netfilter/Kconfig |  2 +-\n net/wireless/Kconfig  | 17 ++++++++++-------\n sound/core/Kconfig    |  4 ++--\n 7 files changed, 25 insertions(+), 20 deletions(-)\n\n--- a/crypto/Kconfig\n+++ b/crypto/Kconfig\n@@ -33,7 +33,7 @@ config CRYPTO_FIPS\n \t  this is.\n \n config CRYPTO_ALGAPI\n-\ttristate\n+\ttristate \"ALGAPI\"\n \tselect CRYPTO_ALGAPI2\n \thelp\n \t  This option provides the API for cryptographic algorithms.\n@@ -42,7 +42,7 @@ config CRYPTO_ALGAPI2\n \ttristate\n \n config CRYPTO_AEAD\n-\ttristate\n+\ttristate \"AEAD\"\n \tselect CRYPTO_AEAD2\n \tselect CRYPTO_ALGAPI\n \n@@ -53,7 +53,7 @@ config CRYPTO_AEAD2\n \tselect CRYPTO_RNG2\n \n config CRYPTO_SKCIPHER\n-\ttristate\n+\ttristate \"SKCIPHER\"\n \tselect CRYPTO_SKCIPHER2\n \tselect CRYPTO_ALGAPI\n \n@@ -63,7 +63,7 @@ config CRYPTO_SKCIPHER2\n \tselect CRYPTO_RNG2\n \n config CRYPTO_HASH\n-\ttristate\n+\ttristate \"HASH\"\n \tselect CRYPTO_HASH2\n \tselect CRYPTO_ALGAPI\n \n@@ -72,7 +72,7 @@ config CRYPTO_HASH2\n \tselect CRYPTO_ALGAPI2\n \n config CRYPTO_RNG\n-\ttristate\n+\ttristate \"RNG\"\n \tselect CRYPTO_RNG2\n \tselect CRYPTO_ALGAPI\n \n--- a/drivers/bcma/Kconfig\n+++ b/drivers/bcma/Kconfig\n@@ -16,6 +16,7 @@ if BCMA\n # Support for Block-I/O. SELECT this from the driver that needs it.\n config BCMA_BLOCKIO\n \tbool\n+\tdefault y\n \n config BCMA_HOST_PCI_POSSIBLE\n \tbool\n--- a/drivers/ssb/Kconfig\n+++ b/drivers/ssb/Kconfig\n@@ -29,6 +29,7 @@ config SSB_SPROM\n config SSB_BLOCKIO\n \tbool\n \tdepends on SSB\n+\tdefault y\n \n config SSB_PCIHOST_POSSIBLE\n \tbool\n@@ -49,7 +50,7 @@ config SSB_PCIHOST\n config SSB_B43_PCI_BRIDGE\n \tbool\n \tdepends on SSB_PCIHOST\n-\tdefault n\n+\tdefault y\n \n config SSB_PCMCIAHOST_POSSIBLE\n \tbool\n--- a/lib/Kconfig\n+++ b/lib/Kconfig\n@@ -418,16 +418,16 @@ config BCH_CONST_T\n # Textsearch support is select'ed if needed\n #\n config TEXTSEARCH\n-\tbool\n+\tbool \"Textsearch support\"\n \n config TEXTSEARCH_KMP\n-\ttristate\n+\ttristate \"Textsearch KMP\"\n \n config TEXTSEARCH_BM\n-\ttristate\n+\ttristate \"Textsearch BM\"\n \n config TEXTSEARCH_FSM\n-\ttristate\n+\ttristate \"Textsearch FSM\"\n \n config BTREE\n \tbool\n--- a/net/netfilter/Kconfig\n+++ b/net/netfilter/Kconfig\n@@ -11,7 +11,7 @@ config NETFILTER_INGRESS\n \t  infrastructure.\n \n config NETFILTER_NETLINK\n-\ttristate\n+\ttristate \"Netfilter NFNETLINK interface\"\n \n config NETFILTER_FAMILY_BRIDGE\n \tbool\n--- a/net/wireless/Kconfig\n+++ b/net/wireless/Kconfig\n@@ -1,6 +1,6 @@\n # SPDX-License-Identifier: GPL-2.0-only\n config WIRELESS_EXT\n-\tbool\n+\tbool \"Wireless extensions\"\n \n config WEXT_CORE\n \tdef_bool y\n@@ -12,10 +12,10 @@ config WEXT_PROC\n \tdepends on WEXT_CORE\n \n config WEXT_SPY\n-\tbool\n+\tbool \"WEXT_SPY\"\n \n config WEXT_PRIV\n-\tbool\n+\tbool \"WEXT_PRIV\"\n \n config CFG80211\n \ttristate \"cfg80211 - wireless configuration API\"\n@@ -204,7 +204,7 @@ config CFG80211_WEXT_EXPORT\n endif # CFG80211\n \n config LIB80211\n-\ttristate\n+\ttristate \"LIB80211\"\n \tdefault n\n \thelp\n \t  This options enables a library of common routines used\n@@ -213,17 +213,17 @@ config LIB80211\n \t  Drivers should select this themselves if needed.\n \n config LIB80211_CRYPT_WEP\n-\ttristate\n+\ttristate \"LIB80211_CRYPT_WEP\"\n \tselect CRYPTO_LIB_ARC4\n \n config LIB80211_CRYPT_CCMP\n-\ttristate\n+\ttristate \"LIB80211_CRYPT_CCMP\"\n \tselect CRYPTO\n \tselect CRYPTO_AES\n \tselect CRYPTO_CCM\n \n config LIB80211_CRYPT_TKIP\n-\ttristate\n+\ttristate \"LIB80211_CRYPT_TKIP\"\n \tselect CRYPTO_LIB_ARC4\n \n config LIB80211_DEBUG\n--- a/sound/core/Kconfig\n+++ b/sound/core/Kconfig\n@@ -17,7 +17,7 @@ config SND_DMAENGINE_PCM\n \ttristate\n \n config SND_HWDEP\n-\ttristate\n+\ttristate \"Sound hardware support\"\n \n config SND_SEQ_DEVICE\n \ttristate\n@@ -27,7 +27,7 @@ config SND_RAWMIDI\n \tselect SND_SEQ_DEVICE if SND_SEQUENCER != n\n \n config SND_COMPRESS_OFFLOAD\n-\ttristate\n+\ttristate \"Compression offloading support\"\n \n config SND_JACK\n \tbool\n"
  },
  {
    "path": "target/linux/generic/hack-5.10/252-SATA_PMP.patch",
    "content": "From 8c817e33be829c7249c2cfd59ff48ad5fac6a31d Mon Sep 17 00:00:00 2001\nFrom: Sungbo Eo <mans0n@gorani.run>\nDate: Fri, 7 Jul 2017 17:09:21 +0200\nSubject: [PATCH] kconfig: solidify SATA_PMP config\n\nSATA_PMP option in kernel config file disappears for every kernel_oldconfig refresh.\nTo prevent this, SATA_HOST is now selected automatically when SATA_PMP is enabled.\nThis patch can be dropped if SATA_MV is ever re-added into the config.\n---\n drivers/ata/Kconfig | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/drivers/ata/Kconfig\n+++ b/drivers/ata/Kconfig\n@@ -112,7 +112,7 @@ config SATA_ZPODD\n \n config SATA_PMP\n \tbool \"SATA Port Multiplier support\"\n-\tdepends on SATA_HOST\n+\tselect SATA_HOST\n \tdefault y\n \thelp\n \t  This option adds support for SATA Port Multipliers\n"
  },
  {
    "path": "target/linux/generic/hack-5.10/253-ksmbd-config.patch",
    "content": "--- a/init/Kconfig\n+++ b/init/Kconfig\n@@ -2379,7 +2379,7 @@ config PADATA\n \tbool\n \n config ASN1\n-\ttristate\n+\ttristate \"ASN1\"\n \thelp\n \t  Build a simple ASN.1 grammar compiler that produces a bytecode output\n \t  that can be interpreted by the ASN.1 stream decoder and used to\n--- a/lib/Kconfig\n+++ b/lib/Kconfig\n@@ -589,7 +589,7 @@ config LIBFDT\n \tbool\n \n config OID_REGISTRY\n-\ttristate\n+\ttristate \"OID\"\n \thelp\n \t  Enable fast lookup object identifier registry.\n \n"
  },
  {
    "path": "target/linux/generic/hack-5.10/259-regmap_dynamic.patch",
    "content": "From 811d9e2268a62b830cfe93cd8bc929afcb8b198b Mon Sep 17 00:00:00 2001\nFrom: Felix Fietkau <nbd@nbd.name>\nDate: Sat, 15 Jul 2017 21:12:38 +0200\nSubject: kernel: move regmap bloat out of the kernel image if it is only being used in modules\n\nlede-commit: 96f39119815028073583e4fca3a9c5fe9141e998\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n drivers/base/regmap/Kconfig  | 15 ++++++++++-----\n drivers/base/regmap/Makefile | 12 ++++++++----\n drivers/base/regmap/regmap.c |  3 +++\n include/linux/regmap.h       |  2 +-\n 4 files changed, 22 insertions(+), 10 deletions(-)\n\n--- a/drivers/base/regmap/Kconfig\n+++ b/drivers/base/regmap/Kconfig\n@@ -4,9 +4,8 @@\n # subsystems should select the appropriate symbols.\n \n config REGMAP\n-\tdefault y if (REGMAP_I2C || REGMAP_SPI || REGMAP_SPMI || REGMAP_W1 || REGMAP_AC97 || REGMAP_MMIO || REGMAP_IRQ || REGMAP_SOUNDWIRE || REGMAP_SCCB || REGMAP_I3C || REGMAP_SPI_AVMM)\n \tselect IRQ_DOMAIN if REGMAP_IRQ\n-\tbool\n+\ttristate\n \n config REGCACHE_COMPRESSED\n \tselect LZO_COMPRESS\n@@ -14,46 +13,59 @@ config REGCACHE_COMPRESSED\n \tbool\n \n config REGMAP_AC97\n+\tselect REGMAP\n \ttristate\n \n config REGMAP_I2C\n \ttristate\n+\tselect REGMAP\n \tdepends on I2C\n \n config REGMAP_SLIMBUS\n \ttristate\n+\tselect REGMAP\n \tdepends on SLIMBUS\n \n config REGMAP_SPI\n \ttristate\n+\tselect REGMAP\n+\tdepends on SPI_MASTER\n \tdepends on SPI\n \n config REGMAP_SPMI\n \ttristate\n+\tselect REGMAP\n \tdepends on SPMI\n \n config REGMAP_W1\n \ttristate\n+\tselect REGMAP\n \tdepends on W1\n \n config REGMAP_MMIO\n \ttristate\n+\tselect REGMAP\n \n config REGMAP_IRQ\n \tbool\n+\tselect REGMAP\n \n config REGMAP_SOUNDWIRE\n \ttristate\n+\tselect REGMAP\n \tdepends on SOUNDWIRE\n \n config REGMAP_SCCB\n \ttristate\n+\tselect REGMAP\n \tdepends on I2C\n \n config REGMAP_I3C\n \ttristate\n+\tselect REGMAP\n \tdepends on I3C\n \n config REGMAP_SPI_AVMM\n \ttristate\n+\tselect REGMAP\n \tdepends on SPI\n--- a/drivers/base/regmap/Makefile\n+++ b/drivers/base/regmap/Makefile\n@@ -2,10 +2,14 @@\n # For include/trace/define_trace.h to include trace.h\n CFLAGS_regmap.o := -I$(src)\n \n-obj-$(CONFIG_REGMAP) += regmap.o regcache.o\n-obj-$(CONFIG_REGMAP) += regcache-rbtree.o regcache-flat.o\n-obj-$(CONFIG_REGCACHE_COMPRESSED) += regcache-lzo.o\n-obj-$(CONFIG_DEBUG_FS) += regmap-debugfs.o\n+regmap-core-objs = regmap.o regcache.o regcache-rbtree.o regcache-flat.o\n+ifdef CONFIG_DEBUG_FS\n+regmap-core-objs += regmap-debugfs.o\n+endif\n+ifdef CONFIG_REGCACHE_COMPRESSED\n+regmap-core-objs += regcache-lzo.o\n+endif\n+obj-$(CONFIG_REGMAP) += regmap-core.o\n obj-$(CONFIG_REGMAP_AC97) += regmap-ac97.o\n obj-$(CONFIG_REGMAP_I2C) += regmap-i2c.o\n obj-$(CONFIG_REGMAP_SLIMBUS) += regmap-slimbus.o\n--- a/drivers/base/regmap/regmap.c\n+++ b/drivers/base/regmap/regmap.c\n@@ -9,6 +9,7 @@\n #include <linux/device.h>\n #include <linux/slab.h>\n #include <linux/export.h>\n+#include <linux/module.h>\n #include <linux/mutex.h>\n #include <linux/err.h>\n #include <linux/property.h>\n@@ -3298,3 +3299,5 @@ static int __init regmap_initcall(void)\n \treturn 0;\n }\n postcore_initcall(regmap_initcall);\n+\n+MODULE_LICENSE(\"GPL\");\n--- a/include/linux/regmap.h\n+++ b/include/linux/regmap.h\n@@ -179,7 +179,7 @@ struct reg_sequence {\n \t__ret ?: __tmp; \\\n })\n \n-#ifdef CONFIG_REGMAP\n+#if IS_REACHABLE(CONFIG_REGMAP)\n \n enum regmap_endian {\n \t/* Unspecified -> 0 -> Backwards compatible default */\n"
  },
  {
    "path": "target/linux/generic/hack-5.10/260-crypto_test_dependencies.patch",
    "content": "From fd1799b0bf5efa46dd3e6dfbbf3955564807e508 Mon Sep 17 00:00:00 2001\nFrom: Felix Fietkau <nbd@nbd.name>\nDate: Fri, 7 Jul 2017 17:12:51 +0200\nSubject: kernel: prevent cryptomgr from pulling in useless extra dependencies for tests that are not run\n\nReduces kernel size after LZMA by about 5k on MIPS\n\nlede-commit: 044c316167e076479a344c59905e5b435b84a77f\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n crypto/Kconfig   | 13 ++++++-------\n crypto/algboss.c |  4 ++++\n 2 files changed, 10 insertions(+), 7 deletions(-)\n\n--- a/crypto/Kconfig\n+++ b/crypto/Kconfig\n@@ -120,13 +120,13 @@ config CRYPTO_MANAGER\n \t  cbc(aes).\n \n config CRYPTO_MANAGER2\n-\tdef_tristate CRYPTO_MANAGER || (CRYPTO_MANAGER!=n && CRYPTO_ALGAPI=y)\n-\tselect CRYPTO_AEAD2\n-\tselect CRYPTO_HASH2\n-\tselect CRYPTO_SKCIPHER2\n-\tselect CRYPTO_AKCIPHER2\n-\tselect CRYPTO_KPP2\n-\tselect CRYPTO_ACOMP2\n+\tdef_tristate CRYPTO_MANAGER || (CRYPTO_MANAGER!=n && CRYPTO_ALGAPI=y && !CRYPTO_MANAGER_DISABLE_TESTS)\n+\tselect CRYPTO_AEAD2 if !CRYPTO_MANAGER_DISABLE_TESTS\n+\tselect CRYPTO_HASH2 if !CRYPTO_MANAGER_DISABLE_TESTS\n+\tselect CRYPTO_SKCIPHER2 if !CRYPTO_MANAGER_DISABLE_TESTS\n+\tselect CRYPTO_AKCIPHER2 if !CRYPTO_MANAGER_DISABLE_TESTS\n+\tselect CRYPTO_KPP2 if !CRYPTO_MANAGER_DISABLE_TESTS\n+\tselect CRYPTO_ACOMP2 if !CRYPTO_MANAGER_DISABLE_TESTS\n \n config CRYPTO_USER\n \ttristate \"Userspace cryptographic algorithm configuration\"\n--- a/crypto/algboss.c\n+++ b/crypto/algboss.c\n@@ -230,8 +230,12 @@ static int cryptomgr_schedule_test(struc\n \ttype = alg->cra_flags;\n \n \t/* Do not test internal algorithms. */\n+#ifdef CONFIG_CRYPTO_MANAGER_DISABLE_TESTS\n+\ttype |= CRYPTO_ALG_TESTED;\n+#else\n \tif (type & CRYPTO_ALG_INTERNAL)\n \t\ttype |= CRYPTO_ALG_TESTED;\n+#endif\n \n \tparam->type = type;\n \n"
  },
  {
    "path": "target/linux/generic/hack-5.10/261-lib-arc4-unhide.patch",
    "content": "This makes it possible to select CONFIG_CRYPTO_LIB_ARC4 directly. We \nneed this to be able to compile this into the kernel and make use of it \nfrom backports.\n\n--- a/lib/crypto/Kconfig\n+++ b/lib/crypto/Kconfig\n@@ -6,7 +6,7 @@ config CRYPTO_LIB_AES\n \ttristate\n \n config CRYPTO_LIB_ARC4\n-\ttristate\n+\ttristate \"ARC4 cipher library\"\n \n config CRYPTO_ARCH_HAVE_LIB_BLAKE2S\n \ttristate\n"
  },
  {
    "path": "target/linux/generic/hack-5.10/280-rfkill-stubs.patch",
    "content": "From 236c1acdfef5958010ac9814a9872e0a46fd78ee Mon Sep 17 00:00:00 2001\nFrom: John Crispin <john@phrozen.org>\nDate: Fri, 7 Jul 2017 17:13:44 +0200\nSubject: rfkill: add fake rfkill support\n\nallow building of modules depending on RFKILL even if RFKILL is not enabled.\n\nSigned-off-by: John Crispin <john@phrozen.org>\n---\n include/linux/rfkill.h |  2 +-\n net/Makefile           |  2 +-\n net/rfkill/Kconfig     | 14 +++++++++-----\n net/rfkill/Makefile    |  2 +-\n 4 files changed, 12 insertions(+), 8 deletions(-)\n\n--- a/include/linux/rfkill.h\n+++ b/include/linux/rfkill.h\n@@ -64,7 +64,7 @@ struct rfkill_ops {\n \tint\t(*set_block)(void *data, bool blocked);\n };\n \n-#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)\n+#if defined(CONFIG_RFKILL_FULL) || defined(CONFIG_RFKILL_FULL_MODULE)\n /**\n  * rfkill_alloc - Allocate rfkill structure\n  * @name: name of the struct -- the string is not copied internally\n--- a/net/Makefile\n+++ b/net/Makefile\n@@ -53,7 +53,7 @@ obj-$(CONFIG_TIPC)\t\t+= tipc/\n obj-$(CONFIG_NETLABEL)\t\t+= netlabel/\n obj-$(CONFIG_IUCV)\t\t+= iucv/\n obj-$(CONFIG_SMC)\t\t+= smc/\n-obj-$(CONFIG_RFKILL)\t\t+= rfkill/\n+obj-$(CONFIG_RFKILL_FULL)\t+= rfkill/\n obj-$(CONFIG_NET_9P)\t\t+= 9p/\n obj-$(CONFIG_CAIF)\t\t+= caif/\n ifneq ($(CONFIG_DCB),)\n--- a/net/rfkill/Kconfig\n+++ b/net/rfkill/Kconfig\n@@ -2,7 +2,11 @@\n #\n # RF switch subsystem configuration\n #\n-menuconfig RFKILL\n+config RFKILL\n+\tbool\n+\tdefault y\n+\n+menuconfig RFKILL_FULL\n \ttristate \"RF switch subsystem support\"\n \thelp\n \t  Say Y here if you want to have control over RF switches\n@@ -14,19 +18,19 @@ menuconfig RFKILL\n # LED trigger support\n config RFKILL_LEDS\n \tbool\n-\tdepends on RFKILL\n+\tdepends on RFKILL_FULL\n \tdepends on LEDS_TRIGGERS = y || RFKILL = LEDS_TRIGGERS\n \tdefault y\n \n config RFKILL_INPUT\n \tbool \"RF switch input support\" if EXPERT\n-\tdepends on RFKILL\n+\tdepends on RFKILL_FULL\n \tdepends on INPUT = y || RFKILL = INPUT\n \tdefault y if !EXPERT\n \n config RFKILL_GPIO\n \ttristate \"GPIO RFKILL driver\"\n-\tdepends on RFKILL\n+\tdepends on RFKILL_FULL\n \tdepends on GPIOLIB || COMPILE_TEST\n \tdefault n\n \thelp\n--- a/net/rfkill/Makefile\n+++ b/net/rfkill/Makefile\n@@ -5,5 +5,5 @@\n \n rfkill-y\t\t\t+= core.o\n rfkill-$(CONFIG_RFKILL_INPUT)\t+= input.o\n-obj-$(CONFIG_RFKILL)\t\t+= rfkill.o\n+obj-$(CONFIG_RFKILL_FULL)\t+= rfkill.o\n obj-$(CONFIG_RFKILL_GPIO)\t+= rfkill-gpio.o\n"
  },
  {
    "path": "target/linux/generic/hack-5.10/300-MIPS-r4k_cache-use-more-efficient-cache-blast.patch",
    "content": "From: Ben Menchaca <ben.menchaca@qca.qualcomm.com>\nDate: Fri, 7 Jun 2013 18:35:22 -0500\nSubject: MIPS: r4k_cache: use more efficient cache blast\n\nOptimize the compiler output for larger cache blast cases that are\ncommon for DMA-based networking.\n\nSigned-off-by: Ben Menchaca <ben.menchaca@qca.qualcomm.com>\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n--- a/arch/mips/include/asm/r4kcache.h\n+++ b/arch/mips/include/asm/r4kcache.h\n@@ -296,14 +296,46 @@ static inline void prot##extra##blast_##\n \t\t\t\t\t\t    unsigned long end)\t\\\n {\t\t\t\t\t\t\t\t\t\\\n \tunsigned long lsize = cpu_##desc##_line_size();\t\t\t\\\n+\tunsigned long lsize_2 = lsize * 2;\t\t\t\t\\\n+\tunsigned long lsize_3 = lsize * 3;\t\t\t\t\\\n+\tunsigned long lsize_4 = lsize * 4;\t\t\t\t\\\n+\tunsigned long lsize_5 = lsize * 5;\t\t\t\t\\\n+\tunsigned long lsize_6 = lsize * 6;\t\t\t\t\\\n+\tunsigned long lsize_7 = lsize * 7;\t\t\t\t\\\n+\tunsigned long lsize_8 = lsize * 8;\t\t\t\t\\\n \tunsigned long addr = start & ~(lsize - 1);\t\t\t\\\n-\tunsigned long aend = (end - 1) & ~(lsize - 1);\t\t\t\\\n+\tunsigned long aend = (end + lsize - 1) & ~(lsize - 1);\t\t\\\n+\tint lines = (aend - addr) / lsize;\t\t\t\t\\\n \t\t\t\t\t\t\t\t\t\\\n-\twhile (1) {\t\t\t\t\t\t\t\\\n+\twhile (lines >= 8) {\t\t\t\t\t\t\\\n+\t\tprot##cache_op(hitop, addr);\t\t\t\t\\\n+\t\tprot##cache_op(hitop, addr + lsize);\t\t\t\\\n+\t\tprot##cache_op(hitop, addr + lsize_2);\t\t\t\\\n+\t\tprot##cache_op(hitop, addr + lsize_3);\t\t\t\\\n+\t\tprot##cache_op(hitop, addr + lsize_4);\t\t\t\\\n+\t\tprot##cache_op(hitop, addr + lsize_5);\t\t\t\\\n+\t\tprot##cache_op(hitop, addr + lsize_6);\t\t\t\\\n+\t\tprot##cache_op(hitop, addr + lsize_7);\t\t\t\\\n+\t\taddr += lsize_8;\t\t\t\t\t\\\n+\t\tlines -= 8;\t\t\t\t\t\t\\\n+\t}\t\t\t\t\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\tif (lines & 0x4) {\t\t\t\t\t\t\\\n+\t\tprot##cache_op(hitop, addr);\t\t\t\t\\\n+\t\tprot##cache_op(hitop, addr + lsize);\t\t\t\\\n+\t\tprot##cache_op(hitop, addr + lsize_2);\t\t\t\\\n+\t\tprot##cache_op(hitop, addr + lsize_3);\t\t\t\\\n+\t\taddr += lsize_4;\t\t\t\t\t\\\n+\t}\t\t\t\t\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\tif (lines & 0x2) {\t\t\t\t\t\t\\\n+\t\tprot##cache_op(hitop, addr);\t\t\t\t\\\n+\t\tprot##cache_op(hitop, addr + lsize);\t\t\t\\\n+\t\taddr += lsize_2;\t\t\t\t\t\\\n+\t}\t\t\t\t\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\tif (lines & 0x1) {\t\t\t\t\t\t\\\n \t\tprot##cache_op(hitop, addr);\t\t\t\t\\\n-\t\tif (addr == aend)\t\t\t\t\t\\\n-\t\t\tbreak;\t\t\t\t\t\t\\\n-\t\taddr += lsize;\t\t\t\t\t\t\\\n \t}\t\t\t\t\t\t\t\t\\\n }\n \n"
  },
  {
    "path": "target/linux/generic/hack-5.10/301-mips_image_cmdline_hack.patch",
    "content": "From: John Crispin <john@phrozen.org>\nSubject: hack: kernel: add generic image_cmdline hack to MIPS targets\n\nlede-commit: d59f5b3a987a48508257a0ddbaeadc7909f9f976\nSigned-off-by: Gabor Juhos <juhosg@openwrt.org>\n---\n arch/mips/Kconfig       | 4 ++++\n arch/mips/kernel/head.S | 6 ++++++\n 2 files changed, 10 insertions(+)\n\n--- a/arch/mips/Kconfig\n+++ b/arch/mips/Kconfig\n@@ -1170,6 +1170,10 @@ config MIPS_MSC\n config SYNC_R4K\n \tbool\n \n+config IMAGE_CMDLINE_HACK\n+\tbool \"OpenWrt specific image command line hack\"\n+\tdefault n\n+\n config NO_IOPORT_MAP\n \tdef_bool n\n \n--- a/arch/mips/kernel/head.S\n+++ b/arch/mips/kernel/head.S\n@@ -79,6 +79,12 @@ FEXPORT(__kernel_entry)\n \tj\tkernel_entry\n #endif /* CONFIG_BOOT_RAW */\n \n+#ifdef CONFIG_IMAGE_CMDLINE_HACK\n+\t.ascii\t\"CMDLINE:\"\n+EXPORT(__image_cmdline)\n+\t.fill\t0x400\n+#endif /* CONFIG_IMAGE_CMDLINE_HACK */\n+\n \t__REF\n \n NESTED(kernel_entry, 16, sp)\t\t\t# kernel entry point\n"
  },
  {
    "path": "target/linux/generic/hack-5.10/321-powerpc_crtsavres_prereq.patch",
    "content": "From 107c0964cb8db7ca28ac5199426414fdab3c274d Mon Sep 17 00:00:00 2001\nFrom: \"Alexandros C. Couloumbis\" <alex@ozo.com>\nDate: Fri, 7 Jul 2017 17:14:51 +0200\nSubject: hack: arch: powerpc: drop register save/restore library from modules\n\nUpstream GCC uses a libgcc function for saving/restoring registers. This\nmakes the code bigger, and upstream kernels need to carry that function\nfor every single kernel module. Our GCC is patched to avoid those\nreferences, so we can drop the extra bloat for modules.\n\nlede-commit: e8e1084654f50904e6bf77b70b2de3f137d7b3ec\nSigned-off-by: Alexandros C. Couloumbis <alex@ozo.com>\n---\n arch/powerpc/Makefile | 1 -\n 1 file changed, 1 deletion(-)\n\n--- a/arch/powerpc/Makefile\n+++ b/arch/powerpc/Makefile\n@@ -61,19 +61,6 @@ machine-$(CONFIG_PPC64) += 64\n machine-$(CONFIG_CPU_LITTLE_ENDIAN) += le\n UTS_MACHINE := $(subst $(space),,$(machine-y))\n \n-# XXX This needs to be before we override LD below\n-ifdef CONFIG_PPC32\n-KBUILD_LDFLAGS_MODULE += arch/powerpc/lib/crtsavres.o\n-else\n-ifeq ($(call ld-ifversion, -ge, 225000000, y),y)\n-# Have the linker provide sfpr if possible.\n-# There is a corresponding test in arch/powerpc/lib/Makefile\n-KBUILD_LDFLAGS_MODULE += --save-restore-funcs\n-else\n-KBUILD_LDFLAGS_MODULE += arch/powerpc/lib/crtsavres.o\n-endif\n-endif\n-\n ifdef CONFIG_CPU_LITTLE_ENDIAN\n KBUILD_CFLAGS\t+= -mlittle-endian\n KBUILD_LDFLAGS\t+= -EL\n"
  },
  {
    "path": "target/linux/generic/hack-5.10/401-mtd-super-don-t-reply-on-mtdblock-device-minor.patch",
    "content": "From f9760b158f610b1792a222cc924073724c061bfb Mon Sep 17 00:00:00 2001\nFrom: Daniel Golle <daniel@makrotopia.org>\nDate: Wed, 7 Apr 2021 22:37:57 +0100\nSubject: [PATCH 1/2] mtd: super: don't reply on mtdblock device minor\nTo: linux-mtd@lists.infradead.org\nCc: Vignesh Raghavendra <vigneshr@ti.com>,\n    Richard Weinberger <richard@nod.at>,\n    Miquel Raynal <miquel.raynal@bootlin.com>,\n    David Woodhouse <dwmw2@infradead.org>\n\nFor blktrans devices with partitions (ie. part_bits != 0) the\nassumption that the minor number of the mtdblock device matches\nthe mtdnum doesn't hold true.\nProperly resolve mtd device from blktrans layer instead.\n\nSigned-off-by: Daniel Golle <daniel@makrotopia.org>\n---\n drivers/mtd/mtdsuper.c | 33 ++++++++++++++++++++++++++-------\n 1 file changed, 26 insertions(+), 7 deletions(-)\n\n--- a/drivers/mtd/mtdsuper.c\n+++ b/drivers/mtd/mtdsuper.c\n@@ -9,6 +9,7 @@\n  */\n \n #include <linux/mtd/super.h>\n+#include <linux/mtd/blktrans.h>\n #include <linux/namei.h>\n #include <linux/export.h>\n #include <linux/ctype.h>\n@@ -121,7 +122,8 @@ int get_tree_mtd(struct fs_context *fc,\n {\n #ifdef CONFIG_BLOCK\n \tstruct block_device *bdev;\n-\tint ret, major;\n+\tstruct mtd_blktrans_dev *blktrans_dev;\n+\tint ret, major, part_bits;\n #endif\n \tint mtdnr;\n \n@@ -169,21 +171,38 @@ int get_tree_mtd(struct fs_context *fc,\n \t/* try the old way - the hack where we allowed users to mount\n \t * /dev/mtdblock$(n) but didn't actually _use_ the blockdev\n \t */\n-\tbdev = lookup_bdev(fc->source);\n+\tbdev = blkdev_get_by_path(fc->source, FMODE_READ, NULL);\n \tif (IS_ERR(bdev)) {\n \t\tret = PTR_ERR(bdev);\n \t\terrorf(fc, \"MTD: Couldn't look up '%s': %d\", fc->source, ret);\n \t\treturn ret;\n \t}\n-\tpr_debug(\"MTDSB: lookup_bdev() returned 0\\n\");\n+\tpr_debug(\"MTDSB: blkdev_get_by_path() returned 0\\n\");\n \n \tmajor = MAJOR(bdev->bd_dev);\n-\tmtdnr = MINOR(bdev->bd_dev);\n-\tbdput(bdev);\n \n-\tif (major == MTD_BLOCK_MAJOR)\n-\t\treturn mtd_get_sb_by_nr(fc, mtdnr, fill_super);\n+\tif (major == MTD_BLOCK_MAJOR) {\n+\t\tif (!bdev->bd_disk) {\n+\t\t\tblkdev_put(bdev, FMODE_READ);\n+\t\t\tBUG();\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\n+\t\tblktrans_dev = (struct mtd_blktrans_dev *)(bdev->bd_disk->private_data);\n+\t\tif (!blktrans_dev || !blktrans_dev->tr) {\n+\t\t\tblkdev_put(bdev, FMODE_READ);\n+\t\t\tBUG();\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t\tmtdnr = blktrans_dev->devnum;\n+\t\tpart_bits = blktrans_dev->tr->part_bits;\n+\t\tblkdev_put(bdev, FMODE_READ);\n+\t\tif (MINOR(bdev->bd_dev) != (mtdnr << part_bits))\n+\t\t\treturn -EINVAL;\n \n+\t\treturn mtd_get_sb_by_nr(fc, mtdnr, fill_super);\n+\t}\n+\tblkdev_put(bdev, FMODE_READ);\n #endif /* CONFIG_BLOCK */\n \n \tif (!(fc->sb_flags & SB_SILENT))\n"
  },
  {
    "path": "target/linux/generic/hack-5.10/402-mtd-blktrans-call-add-disks-after-mtd-device.patch",
    "content": "From 0bccc3722bdd88e8ae995e77ef9f7b77ee4cbdee Mon Sep 17 00:00:00 2001\nFrom: Daniel Golle <daniel@makrotopia.org>\nDate: Wed, 7 Apr 2021 22:45:54 +0100\nSubject: [PATCH 2/2] mtd: blktrans: call add disks after mtd device\nTo: linux-mtd@lists.infradead.org\nCc: Vignesh Raghavendra <vigneshr@ti.com>,\n    Richard Weinberger <richard@nod.at>,\n    Miquel Raynal <miquel.raynal@bootlin.com>,\n    David Woodhouse <dwmw2@infradead.org>\n\nCalling device_add_disk while holding mtd_table_mutex leads\nto deadlock in case part_bits!=0 as block partition parsers\nwill try to open the newly created disks, trying to acquire\nmutex once again.\nMove device_add_disk to additional function called after\nadd partitions of an MTD device have been added and locks\nhave been released.\n\nSigned-off-by: Daniel Golle <daniel@makrotopia.org>\n---\n drivers/mtd/mtd_blkdevs.c    | 33 ++++++++++++++++++++++++++-------\n drivers/mtd/mtdcore.c        |  3 +++\n include/linux/mtd/blktrans.h |  1 +\n 3 files changed, 30 insertions(+), 7 deletions(-)\n\n--- a/drivers/mtd/mtd_blkdevs.c\n+++ b/drivers/mtd/mtd_blkdevs.c\n@@ -457,13 +457,6 @@ int add_mtd_blktrans_dev(struct mtd_blkt\n \tif (new->readonly)\n \t\tset_disk_ro(gd, 1);\n \n-\tdevice_add_disk(&new->mtd->dev, gd, NULL);\n-\n-\tif (new->disk_attributes) {\n-\t\tret = sysfs_create_group(&disk_to_dev(gd)->kobj,\n-\t\t\t\t\tnew->disk_attributes);\n-\t\tWARN_ON(ret);\n-\t}\n \treturn 0;\n error4:\n \tkfree(new->tag_set);\n@@ -475,6 +468,27 @@ error1:\n \treturn ret;\n }\n \n+void register_mtd_blktrans_devs(void)\n+{\n+\tstruct mtd_blktrans_ops *tr;\n+\tstruct mtd_blktrans_dev *dev, *next;\n+\tint ret;\n+\n+\tlist_for_each_entry(tr, &blktrans_majors, list) {\n+\t\tlist_for_each_entry_safe(dev, next, &tr->devs, list) {\n+\t\t\tif (dev->disk->flags & GENHD_FL_UP)\n+\t\t\t\tcontinue;\n+\n+\t\t\tdevice_add_disk(&dev->mtd->dev, dev->disk, NULL);\n+\t\t\tif (dev->disk_attributes) {\n+\t\t\t\tret = sysfs_create_group(&disk_to_dev(dev->disk)->kobj,\n+\t\t\t\t\t\t\tdev->disk_attributes);\n+\t\t\t\tWARN_ON(ret);\n+\t\t\t}\n+\t\t}\n+\t}\n+}\n+\n int del_mtd_blktrans_dev(struct mtd_blktrans_dev *old)\n {\n \tunsigned long flags;\n--- a/drivers/mtd/mtdcore.c\n+++ b/drivers/mtd/mtdcore.c\n@@ -31,6 +31,7 @@\n \n #include <linux/mtd/mtd.h>\n #include <linux/mtd/partitions.h>\n+#include <linux/mtd/blktrans.h>\n \n #include \"mtdcore.h\"\n \n@@ -851,6 +852,8 @@ int mtd_device_parse_register(struct mtd\n \t\tregister_reboot_notifier(&mtd->reboot_notifier);\n \t}\n \n+\tregister_mtd_blktrans_devs();\n+\n out:\n \tif (ret && device_is_registered(&mtd->dev))\n \t\tdel_mtd_device(mtd);\n--- a/include/linux/mtd/blktrans.h\n+++ b/include/linux/mtd/blktrans.h\n@@ -76,6 +76,6 @@ extern int deregister_mtd_blktrans(struc\n extern int add_mtd_blktrans_dev(struct mtd_blktrans_dev *dev);\n extern int del_mtd_blktrans_dev(struct mtd_blktrans_dev *dev);\n extern int mtd_blktrans_cease_background(struct mtd_blktrans_dev *dev);\n-\n+extern void register_mtd_blktrans_devs(void);\n \n #endif /* __MTD_TRANS_H__ */\n"
  },
  {
    "path": "target/linux/generic/hack-5.10/410-block-fit-partition-parser.patch",
    "content": "--- a/block/blk.h\n+++ b/block/blk.h\n@@ -361,6 +361,8 @@ char *disk_name(struct gendisk *hd, int\n #define ADDPART_FLAG_NONE\t0\n #define ADDPART_FLAG_RAID\t1\n #define ADDPART_FLAG_WHOLEDISK\t2\n+#define ADDPART_FLAG_READONLY\t4\n+#define ADDPART_FLAG_ROOTDEV\t8\n void delete_partition(struct hd_struct *part);\n int bdev_add_partition(struct block_device *bdev, int partno,\n \t\tsector_t start, sector_t length);\n--- a/block/partitions/Kconfig\n+++ b/block/partitions/Kconfig\n@@ -101,6 +101,13 @@ config ATARI_PARTITION\n \t  Say Y here if you would like to use hard disks under Linux which\n \t  were partitioned under the Atari OS.\n \n+config FIT_PARTITION\n+\tbool \"Flattened-Image-Tree (FIT) partition support\" if PARTITION_ADVANCED\n+\tdefault n\n+\thelp\n+\t  Say Y here if your system needs to mount the filesystem part of\n+\t  a Flattened-Image-Tree (FIT) image commonly used with Das U-Boot.\n+\n config IBM_PARTITION\n \tbool \"IBM disk label and partition support\"\n \tdepends on PARTITION_ADVANCED && S390\n--- a/block/partitions/Makefile\n+++ b/block/partitions/Makefile\n@@ -8,6 +8,7 @@ obj-$(CONFIG_ACORN_PARTITION) += acorn.o\n obj-$(CONFIG_AMIGA_PARTITION) += amiga.o\n obj-$(CONFIG_ATARI_PARTITION) += atari.o\n obj-$(CONFIG_AIX_PARTITION) += aix.o\n+obj-$(CONFIG_FIT_PARTITION) += fit.o\n obj-$(CONFIG_CMDLINE_PARTITION) += cmdline.o\n obj-$(CONFIG_MAC_PARTITION) += mac.o\n obj-$(CONFIG_LDM_PARTITION) += ldm.o\n--- a/block/partitions/check.h\n+++ b/block/partitions/check.h\n@@ -58,6 +58,7 @@ int amiga_partition(struct parsed_partit\n int atari_partition(struct parsed_partitions *state);\n int cmdline_partition(struct parsed_partitions *state);\n int efi_partition(struct parsed_partitions *state);\n+int fit_partition(struct parsed_partitions *state);\n int ibm_partition(struct parsed_partitions *);\n int karma_partition(struct parsed_partitions *state);\n int ldm_partition(struct parsed_partitions *state);\n@@ -68,3 +69,5 @@ int sgi_partition(struct parsed_partitio\n int sun_partition(struct parsed_partitions *state);\n int sysv68_partition(struct parsed_partitions *state);\n int ultrix_partition(struct parsed_partitions *state);\n+\n+int parse_fit_partitions(struct parsed_partitions *state, u64 start_sector, u64 nr_sectors, int *slot, int add_remain);\n--- a/block/partitions/core.c\n+++ b/block/partitions/core.c\n@@ -10,6 +10,10 @@\n #include <linux/vmalloc.h>\n #include <linux/blktrace_api.h>\n #include <linux/raid/detect.h>\n+#ifdef CONFIG_FIT_PARTITION\n+#include <linux/root_dev.h>\n+#endif\n+\n #include \"check.h\"\n \n static int (*check_part[])(struct parsed_partitions *) = {\n@@ -46,6 +50,9 @@ static int (*check_part[])(struct parsed\n #ifdef CONFIG_EFI_PARTITION\n \tefi_partition,\t\t/* this must come before msdos */\n #endif\n+#ifdef CONFIG_FIT_PARTITION\n+\tfit_partition,\n+#endif\n #ifdef CONFIG_SGI_PARTITION\n \tsgi_partition,\n #endif\n@@ -694,6 +701,14 @@ static bool blk_add_partition(struct gen\n \t    (state->parts[p].flags & ADDPART_FLAG_RAID))\n \t\tmd_autodetect_dev(part_to_dev(part)->devt);\n \n+#ifdef CONFIG_FIT_PARTITION\n+\tif ((state->parts[p].flags & ADDPART_FLAG_ROOTDEV) && ROOT_DEV == 0)\n+\t\tROOT_DEV = part_to_dev(part)->devt;\n+\n+\tif (state->parts[p].flags & ADDPART_FLAG_READONLY)\n+\t\tpart->policy = true;\n+#endif\n+\n \treturn true;\n }\n \n--- a/drivers/mtd/ubi/block.c\n+++ b/drivers/mtd/ubi/block.c\n@@ -396,7 +396,11 @@ int ubiblock_create(struct ubi_volume_in\n \tdev->leb_size = vi->usable_leb_size;\n \n \t/* Initialize the gendisk of this ubiblock device */\n+#ifdef CONFIG_FIT_PARTITION\n+\tgd = alloc_disk(0);\n+#else\n \tgd = alloc_disk(1);\n+#endif\n \tif (!gd) {\n \t\tpr_err(\"UBI: block: alloc_disk failed\\n\");\n \t\tret = -ENODEV;\n@@ -413,6 +417,9 @@ int ubiblock_create(struct ubi_volume_in\n \t\tgoto out_put_disk;\n \t}\n \tgd->private_data = dev;\n+#ifdef CONFIG_FIT_PARTITION\n+\tgd->flags |= GENHD_FL_EXT_DEVT;\n+#endif\n \tsprintf(gd->disk_name, \"ubiblock%d_%d\", dev->ubi_num, dev->vol_id);\n \tset_capacity(gd, disk_capacity);\n \tdev->gd = gd;\n--- a/block/partitions/efi.c\n+++ b/block/partitions/efi.c\n@@ -706,6 +706,9 @@ int efi_partition(struct parsed_partitio\n \tgpt_entry *ptes = NULL;\n \tu32 i;\n \tunsigned ssz = bdev_logical_block_size(state->bdev) / 512;\n+#ifdef CONFIG_FIT_PARTITION\n+\tu32 extra_slot = 64;\n+#endif\n \n \tif (!find_valid_gpt(state, &gpt, &ptes) || !gpt || !ptes) {\n \t\tkfree(gpt);\n@@ -739,6 +742,11 @@ int efi_partition(struct parsed_partitio\n \t\t\t\tARRAY_SIZE(ptes[i].partition_name));\n \t\tutf16_le_to_7bit(ptes[i].partition_name, label_max, info->volname);\n \t\tstate->parts[i + 1].has_info = true;\n+#ifdef CONFIG_FIT_PARTITION\n+\t\t/* If this is a U-Boot FIT volume it may have subpartitions */\n+\t\tif (!efi_guidcmp(ptes[i].partition_type_guid, PARTITION_LINUX_FIT_GUID))\n+\t\t\t(void) parse_fit_partitions(state, start * ssz, size * ssz, &extra_slot, 1);\n+#endif\n \t}\n \tkfree(ptes);\n \tkfree(gpt);\n--- a/block/partitions/efi.h\n+++ b/block/partitions/efi.h\n@@ -52,6 +52,9 @@\n #define PARTITION_LINUX_LVM_GUID \\\n     EFI_GUID( 0xe6d6d379, 0xf507, 0x44c2, \\\n               0xa2, 0x3c, 0x23, 0x8f, 0x2a, 0x3d, 0xf9, 0x28)\n+#define PARTITION_LINUX_FIT_GUID \\\n+    EFI_GUID( 0xcae9be83, 0xb15f, 0x49cc, \\\n+              0x86, 0x3f, 0x08, 0x1b, 0x74, 0x4a, 0x2d, 0x93)\n \n typedef struct _gpt_header {\n \t__le64 signature;\n--- a/drivers/mtd/mtdblock.c\n+++ b/drivers/mtd/mtdblock.c\n@@ -334,7 +334,11 @@ static void mtdblock_remove_dev(struct m\n static struct mtd_blktrans_ops mtdblock_tr = {\n \t.name\t\t= \"mtdblock\",\n \t.major\t\t= MTD_BLOCK_MAJOR,\n+#ifdef CONFIG_FIT_PARTITION\n+\t.part_bits\t= 2,\n+#else\n \t.part_bits\t= 0,\n+#endif\n \t.blksize \t= 512,\n \t.open\t\t= mtdblock_open,\n \t.flush\t\t= mtdblock_flush,\n--- a/drivers/mtd/mtd_blkdevs.c\n+++ b/drivers/mtd/mtd_blkdevs.c\n@@ -407,18 +407,8 @@ int add_mtd_blktrans_dev(struct mtd_blkt\n \tgd->first_minor = (new->devnum) << tr->part_bits;\n \tgd->fops = &mtd_block_ops;\n \n-\tif (tr->part_bits)\n-\t\tif (new->devnum < 26)\n-\t\t\tsnprintf(gd->disk_name, sizeof(gd->disk_name),\n-\t\t\t\t \"%s%c\", tr->name, 'a' + new->devnum);\n-\t\telse\n-\t\t\tsnprintf(gd->disk_name, sizeof(gd->disk_name),\n-\t\t\t\t \"%s%c%c\", tr->name,\n-\t\t\t\t 'a' - 1 + new->devnum / 26,\n-\t\t\t\t 'a' + new->devnum % 26);\n-\telse\n-\t\tsnprintf(gd->disk_name, sizeof(gd->disk_name),\n-\t\t\t \"%s%d\", tr->name, new->devnum);\n+\tsnprintf(gd->disk_name, sizeof(gd->disk_name),\n+\t\t \"%s%d\", tr->name, new->devnum);\n \n \tset_capacity(gd, ((u64)new->size * tr->blksize) >> 9);\n \n--- a/block/partitions/msdos.c\n+++ b/block/partitions/msdos.c\n@@ -563,6 +563,15 @@ static void parse_minix(struct parsed_pa\n #endif /* CONFIG_MINIX_SUBPARTITION */\n }\n \n+static void parse_fit_mbr(struct parsed_partitions *state,\n+\t\t\t  sector_t offset, sector_t size, int origin)\n+{\n+#ifdef CONFIG_FIT_PARTITION\n+\tu32 extra_slot = 64;\n+\t(void) parse_fit_partitions(state, offset, size, &extra_slot, 1);\n+#endif /* CONFIG_FIT_PARTITION */\n+}\n+\n static struct {\n \tunsigned char id;\n \tvoid (*parse)(struct parsed_partitions *, sector_t, sector_t, int);\n@@ -574,6 +583,7 @@ static struct {\n \t{UNIXWARE_PARTITION, parse_unixware},\n \t{SOLARIS_X86_PARTITION, parse_solaris_x86},\n \t{NEW_SOLARIS_X86_PARTITION, parse_solaris_x86},\n+\t{FIT_PARTITION, parse_fit_mbr},\n \t{0, NULL},\n };\n \n--- a/include/linux/msdos_partition.h\n+++ b/include/linux/msdos_partition.h\n@@ -31,6 +31,7 @@ enum msdos_sys_ind {\n \tLINUX_LVM_PARTITION = 0x8e,\n \tLINUX_RAID_PARTITION = 0xfd,\t/* autodetect RAID partition */\n \n+\tFIT_PARTITION = 0x2e,\t\t/* U-Boot uImage.FIT */\n \tSOLARIS_X86_PARTITION =\t0x82,\t/* also Linux swap partitions */\n \tNEW_SOLARIS_X86_PARTITION = 0xbf,\n \n"
  },
  {
    "path": "target/linux/generic/hack-5.10/420-mtd-set-rootfs-to-be-root-dev.patch",
    "content": "From: Gabor Juhos <juhosg@openwrt.org>\nSubject: kernel/3.1[02]: move MTD root device setup code to mtdcore\n\nThe current code only allows to automatically set\nroot device on MTD partitions. Move the code to MTD\ncore to allow to use it with all MTD devices.\n\nSigned-off-by: Gabor Juhos <juhosg@openwrt.org>\n---\n drivers/mtd/mtdcore.c | 10 ++++++++++\n 1 file changed, 10 insertions(+)\n\n--- a/drivers/mtd/mtdcore.c\n+++ b/drivers/mtd/mtdcore.c\n@@ -27,6 +27,7 @@\n #include <linux/reboot.h>\n #include <linux/leds.h>\n #include <linux/debugfs.h>\n+#include <linux/root_dev.h>\n #include <linux/nvmem-provider.h>\n \n #include <linux/mtd/mtd.h>\n@@ -694,6 +695,19 @@ int add_mtd_device(struct mtd_info *mtd)\n \t   of this try_ nonsense, and no bitching about it\n \t   either. :) */\n \t__module_get(THIS_MODULE);\n+\n+\tif (!strcmp(mtd->name, \"rootfs\") &&\n+\t    IS_ENABLED(CONFIG_MTD_ROOTFS_ROOT_DEV) &&\n+\t    ROOT_DEV == 0) {\n+\t\tunsigned int index = mtd->index;\n+\t\tpr_notice(\"mtd: device %d (%s) set to be root filesystem\\n\",\n+\t\t\t  mtd->index, mtd->name);\n+#ifdef CONFIG_FIT_PARTITION\n+\t\tindex <<= 2;\n+#endif\n+\t\tROOT_DEV = MKDEV(MTD_BLOCK_MAJOR, index);\n+\t}\n+\n \treturn 0;\n \n fail_nvmem_add:\n"
  },
  {
    "path": "target/linux/generic/hack-5.10/421-drivers-mtd-parsers-add-nvmem-support-to-cmdlinepart.patch",
    "content": "From 6fa9e3678eb002246df1280322b6a024853950a5 Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Mon, 11 Oct 2021 00:53:14 +0200\nSubject: [PATCH] drivers: mtd: parsers: add nvmem support to cmdlinepart\n\nAssuming cmdlinepart is only one level deep partition scheme and that\nstatic partition are also defined in DTS, we can assign an of_node for\npartition declared from bootargs. cmdlinepart have priority than\nfiexed-partition parser so in this specific case the parser doesn't\nassign an of_node. Fix this by searching a defined of_node using a\nsimilar fixed_partition parser and if a partition is found with the same\nlabel, check that it has the same offset and size and return the DT\nof_node to correctly use NVMEM cells.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\n---\n drivers/mtd/parsers/cmdlinepart.c | 71 +++++++++++++++++++++++++++++++\n 1 file changed, 71 insertions(+)\n\n--- a/drivers/mtd/parsers/cmdlinepart.c\n+++ b/drivers/mtd/parsers/cmdlinepart.c\n@@ -43,6 +43,7 @@\n #include <linux/mtd/partitions.h>\n #include <linux/module.h>\n #include <linux/err.h>\n+#include <linux/of.h>\n \n /* debug macro */\n #if 0\n@@ -323,6 +324,68 @@ static int mtdpart_setup_real(char *s)\n \treturn 0;\n }\n \n+static int search_fixed_partition(struct mtd_info *master,\n+\t\t\t\t  struct mtd_partition *target_part,\n+\t\t\t\t  struct mtd_partition *fixed_part)\n+{\n+\tstruct device_node *mtd_node;\n+\tstruct device_node *ofpart_node;\n+\tstruct device_node *pp;\n+\tstruct mtd_partition part;\n+\tconst char *partname;\n+\n+\tmtd_node = mtd_get_of_node(master);\n+\tif (!mtd_node)\n+\t\treturn -EINVAL;\n+\n+\tofpart_node = of_get_child_by_name(mtd_node, \"partitions\");\n+\n+\tfor_each_child_of_node(ofpart_node,  pp) {\n+\t\tconst __be32 *reg;\n+\t\tint len;\n+\t\tint a_cells, s_cells;\n+\n+\t\treg = of_get_property(pp, \"reg\", &len);\n+\t\tif (!reg) {\n+\t\t\tpr_debug(\"%s: ofpart partition %pOF (%pOF) missing reg property.\\n\",\n+\t\t\t\t master->name, pp,\n+\t\t\t\t mtd_node);\n+\t\t\tcontinue;\n+\t\t}\n+\n+\t\ta_cells = of_n_addr_cells(pp);\n+\t\ts_cells = of_n_size_cells(pp);\n+\t\tif (len / 4 != a_cells + s_cells) {\n+\t\t\tpr_debug(\"%s: ofpart partition %pOF (%pOF) error parsing reg property.\\n\",\n+\t\t\t\t master->name, pp,\n+\t\t\t\t mtd_node);\n+\t\t\tcontinue;\n+\t\t}\n+\n+\t\tpart.offset = of_read_number(reg, a_cells);\n+\t\tpart.size = of_read_number(reg + a_cells, s_cells);\n+\t\tpart.of_node = pp;\n+\n+\t\tpartname = of_get_property(pp, \"label\", &len);\n+\t\tif (!partname)\n+\t\t\tpartname = of_get_property(pp, \"name\", &len);\n+\t\tpart.name = partname;\n+\n+\t\tif (!strncmp(target_part->name, part.name, len)) {\n+\t\t\tif (part.offset != target_part->offset)\n+\t\t\t\treturn -EINVAL;\n+\n+\t\t\tif (part.size != target_part->size)\n+\t\t\t\treturn -EINVAL;\n+\n+\t\t\tmemcpy(fixed_part, &part, sizeof(struct mtd_partition));\n+\t\t\treturn 0;\n+\t\t}\n+\t}\n+\n+\treturn -EINVAL;\n+}\n+\n /*\n  * Main function to be called from the MTD mapping driver/device to\n  * obtain the partitioning information. At this point the command line\n@@ -338,6 +401,7 @@ static int parse_cmdline_partitions(stru\n \tint i, err;\n \tstruct cmdline_mtd_partition *part;\n \tconst char *mtd_id = master->name;\n+\tstruct mtd_partition fixed_part;\n \n \t/* parse command line */\n \tif (!cmdline_parsed) {\n@@ -382,6 +446,13 @@ static int parse_cmdline_partitions(stru\n \t\t\t\tsizeof(*part->parts) * (part->num_parts - i));\n \t\t\ti--;\n \t\t}\n+\n+\t\terr = search_fixed_partition(master, &part->parts[i], &fixed_part);\n+\t\tif (!err) {\n+\t\t\tpart->parts[i].of_node = fixed_part.of_node;\n+\t\t\tpr_info(\"Found partition defined in DT for %s. Assigning OF node to support nvmem.\",\n+\t\t\t\tpart->parts[i].name);\n+\t\t}\n \t}\n \n \t*pparts = kmemdup(part->parts, sizeof(*part->parts) * part->num_parts,\n"
  },
  {
    "path": "target/linux/generic/hack-5.10/430-mtk-bmt-support.patch",
    "content": "--- a/drivers/mtd/nand/Kconfig\n+++ b/drivers/mtd/nand/Kconfig\n@@ -15,6 +15,10 @@ config MTD_NAND_ECC\n        bool\n        depends on MTD_NAND_CORE\n \n+config MTD_NAND_MTK_BMT\n+\tbool \"Support MediaTek NAND Bad-block Management Table\"\n+\tdefault n\n+\n endmenu\n \n endmenu\n--- a/drivers/mtd/nand/Makefile\n+++ b/drivers/mtd/nand/Makefile\n@@ -2,6 +2,7 @@\n \n nandcore-objs := core.o bbt.o\n obj-$(CONFIG_MTD_NAND_CORE) += nandcore.o\n+obj-$(CONFIG_MTD_NAND_MTK_BMT)\t+= mtk_bmt.o mtk_bmt_v2.o mtk_bmt_bbt.o mtk_bmt_nmbm.o\n \n obj-y\t+= onenand/\n obj-y\t+= raw/\n"
  },
  {
    "path": "target/linux/generic/hack-5.10/531-debloat_lzma.patch",
    "content": "From 3fd297761ac246c54d7723c57fca95c112b99465 Mon Sep 17 00:00:00 2001\nFrom: Felix Fietkau <nbd@nbd.name>\nDate: Sat, 15 Jul 2017 21:15:44 +0200\nSubject: lzma: de-bloat the lzma library used by jffs2\n\nlede-commit: 3fd1dd08fbcbb78b34efefd32c3032e5c99108d6\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n include/linux/lzma/LzFind.h  |  17 ---\n include/linux/lzma/LzmaDec.h | 101 ---------------\n include/linux/lzma/LzmaEnc.h |  20 ---\n lib/lzma/LzFind.c            | 287 ++++---------------------------------------\n lib/lzma/LzmaDec.c           |  86 +------------\n lib/lzma/LzmaEnc.c           | 172 ++------------------------\n 6 files changed, 42 insertions(+), 641 deletions(-)\n\n--- a/include/linux/lzma/LzFind.h\n+++ b/include/linux/lzma/LzFind.h\n@@ -55,11 +55,6 @@ typedef struct _CMatchFinder\n \n #define Inline_MatchFinder_GetNumAvailableBytes(p) ((p)->streamPos - (p)->pos)\n \n-int MatchFinder_NeedMove(CMatchFinder *p);\n-Byte *MatchFinder_GetPointerToCurrentPos(CMatchFinder *p);\n-void MatchFinder_MoveBlock(CMatchFinder *p);\n-void MatchFinder_ReadIfRequired(CMatchFinder *p);\n-\n void MatchFinder_Construct(CMatchFinder *p);\n \n /* Conditions:\n@@ -70,12 +65,6 @@ int MatchFinder_Create(CMatchFinder *p,\n     UInt32 keepAddBufferBefore, UInt32 matchMaxLen, UInt32 keepAddBufferAfter,\n     ISzAlloc *alloc);\n void MatchFinder_Free(CMatchFinder *p, ISzAlloc *alloc);\n-void MatchFinder_Normalize3(UInt32 subValue, CLzRef *items, UInt32 numItems);\n-void MatchFinder_ReduceOffsets(CMatchFinder *p, UInt32 subValue);\n-\n-UInt32 * GetMatchesSpec1(UInt32 lenLimit, UInt32 curMatch, UInt32 pos, const Byte *buffer, CLzRef *son,\n-    UInt32 _cyclicBufferPos, UInt32 _cyclicBufferSize, UInt32 _cutValue,\n-    UInt32 *distances, UInt32 maxLen);\n \n /*\n Conditions:\n@@ -102,12 +91,6 @@ typedef struct _IMatchFinder\n \n void MatchFinder_CreateVTable(CMatchFinder *p, IMatchFinder *vTable);\n \n-void MatchFinder_Init(CMatchFinder *p);\n-UInt32 Bt3Zip_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances);\n-UInt32 Hc3Zip_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances);\n-void Bt3Zip_MatchFinder_Skip(CMatchFinder *p, UInt32 num);\n-void Hc3Zip_MatchFinder_Skip(CMatchFinder *p, UInt32 num);\n-\n #ifdef __cplusplus\n }\n #endif\n--- a/include/linux/lzma/LzmaDec.h\n+++ b/include/linux/lzma/LzmaDec.h\n@@ -31,14 +31,6 @@ typedef struct _CLzmaProps\n   UInt32 dicSize;\n } CLzmaProps;\n \n-/* LzmaProps_Decode - decodes properties\n-Returns:\n-  SZ_OK\n-  SZ_ERROR_UNSUPPORTED - Unsupported properties\n-*/\n-\n-SRes LzmaProps_Decode(CLzmaProps *p, const Byte *data, unsigned size);\n-\n \n /* ---------- LZMA Decoder state ---------- */\n \n@@ -70,8 +62,6 @@ typedef struct\n \n #define LzmaDec_Construct(p) { (p)->dic = 0; (p)->probs = 0; }\n \n-void LzmaDec_Init(CLzmaDec *p);\n-\n /* There are two types of LZMA streams:\n      0) Stream with end mark. That end mark adds about 6 bytes to compressed size.\n      1) Stream without end mark. You must know exact uncompressed size to decompress such stream. */\n@@ -108,97 +98,6 @@ typedef enum\n \n /* ELzmaStatus is used only as output value for function call */\n \n-\n-/* ---------- Interfaces ---------- */\n-\n-/* There are 3 levels of interfaces:\n-     1) Dictionary Interface\n-     2) Buffer Interface\n-     3) One Call Interface\n-   You can select any of these interfaces, but don't mix functions from different\n-   groups for same object. */\n-\n-\n-/* There are two variants to allocate state for Dictionary Interface:\n-     1) LzmaDec_Allocate / LzmaDec_Free\n-     2) LzmaDec_AllocateProbs / LzmaDec_FreeProbs\n-   You can use variant 2, if you set dictionary buffer manually.\n-   For Buffer Interface you must always use variant 1.\n-\n-LzmaDec_Allocate* can return:\n-  SZ_OK\n-  SZ_ERROR_MEM         - Memory allocation error\n-  SZ_ERROR_UNSUPPORTED - Unsupported properties\n-*/\n-\n-SRes LzmaDec_AllocateProbs(CLzmaDec *p, const Byte *props, unsigned propsSize, ISzAlloc *alloc);\n-void LzmaDec_FreeProbs(CLzmaDec *p, ISzAlloc *alloc);\n-\n-SRes LzmaDec_Allocate(CLzmaDec *state, const Byte *prop, unsigned propsSize, ISzAlloc *alloc);\n-void LzmaDec_Free(CLzmaDec *state, ISzAlloc *alloc);\n-\n-/* ---------- Dictionary Interface ---------- */\n-\n-/* You can use it, if you want to eliminate the overhead for data copying from\n-   dictionary to some other external buffer.\n-   You must work with CLzmaDec variables directly in this interface.\n-\n-   STEPS:\n-     LzmaDec_Constr()\n-     LzmaDec_Allocate()\n-     for (each new stream)\n-     {\n-       LzmaDec_Init()\n-       while (it needs more decompression)\n-       {\n-         LzmaDec_DecodeToDic()\n-         use data from CLzmaDec::dic and update CLzmaDec::dicPos\n-       }\n-     }\n-     LzmaDec_Free()\n-*/\n-\n-/* LzmaDec_DecodeToDic\n-\n-   The decoding to internal dictionary buffer (CLzmaDec::dic).\n-   You must manually update CLzmaDec::dicPos, if it reaches CLzmaDec::dicBufSize !!!\n-\n-finishMode:\n-  It has meaning only if the decoding reaches output limit (dicLimit).\n-  LZMA_FINISH_ANY - Decode just dicLimit bytes.\n-  LZMA_FINISH_END - Stream must be finished after dicLimit.\n-\n-Returns:\n-  SZ_OK\n-    status:\n-      LZMA_STATUS_FINISHED_WITH_MARK\n-      LZMA_STATUS_NOT_FINISHED\n-      LZMA_STATUS_NEEDS_MORE_INPUT\n-      LZMA_STATUS_MAYBE_FINISHED_WITHOUT_MARK\n-  SZ_ERROR_DATA - Data error\n-*/\n-\n-SRes LzmaDec_DecodeToDic(CLzmaDec *p, SizeT dicLimit,\n-    const Byte *src, SizeT *srcLen, ELzmaFinishMode finishMode, ELzmaStatus *status);\n-\n-\n-/* ---------- Buffer Interface ---------- */\n-\n-/* It's zlib-like interface.\n-   See LzmaDec_DecodeToDic description for information about STEPS and return results,\n-   but you must use LzmaDec_DecodeToBuf instead of LzmaDec_DecodeToDic and you don't need\n-   to work with CLzmaDec variables manually.\n-\n-finishMode:\n-  It has meaning only if the decoding reaches output limit (*destLen).\n-  LZMA_FINISH_ANY - Decode just destLen bytes.\n-  LZMA_FINISH_END - Stream must be finished after (*destLen).\n-*/\n-\n-SRes LzmaDec_DecodeToBuf(CLzmaDec *p, Byte *dest, SizeT *destLen,\n-    const Byte *src, SizeT *srcLen, ELzmaFinishMode finishMode, ELzmaStatus *status);\n-\n-\n /* ---------- One Call Interface ---------- */\n \n /* LzmaDecode\n--- a/include/linux/lzma/LzmaEnc.h\n+++ b/include/linux/lzma/LzmaEnc.h\n@@ -31,9 +31,6 @@ typedef struct _CLzmaEncProps\n } CLzmaEncProps;\n \n void LzmaEncProps_Init(CLzmaEncProps *p);\n-void LzmaEncProps_Normalize(CLzmaEncProps *p);\n-UInt32 LzmaEncProps_GetDictSize(const CLzmaEncProps *props2);\n-\n \n /* ---------- CLzmaEncHandle Interface ---------- */\n \n@@ -53,26 +50,9 @@ CLzmaEncHandle LzmaEnc_Create(ISzAlloc *\n void LzmaEnc_Destroy(CLzmaEncHandle p, ISzAlloc *alloc, ISzAlloc *allocBig);\n SRes LzmaEnc_SetProps(CLzmaEncHandle p, const CLzmaEncProps *props);\n SRes LzmaEnc_WriteProperties(CLzmaEncHandle p, Byte *properties, SizeT *size);\n-SRes LzmaEnc_Encode(CLzmaEncHandle p, ISeqOutStream *outStream, ISeqInStream *inStream,\n-    ICompressProgress *progress, ISzAlloc *alloc, ISzAlloc *allocBig);\n SRes LzmaEnc_MemEncode(CLzmaEncHandle p, Byte *dest, SizeT *destLen, const Byte *src, SizeT srcLen,\n     int writeEndMark, ICompressProgress *progress, ISzAlloc *alloc, ISzAlloc *allocBig);\n \n-/* ---------- One Call Interface ---------- */\n-\n-/* LzmaEncode\n-Return code:\n-  SZ_OK               - OK\n-  SZ_ERROR_MEM        - Memory allocation error\n-  SZ_ERROR_PARAM      - Incorrect paramater\n-  SZ_ERROR_OUTPUT_EOF - output buffer overflow\n-  SZ_ERROR_THREAD     - errors in multithreading functions (only for Mt version)\n-*/\n-\n-SRes LzmaEncode(Byte *dest, SizeT *destLen, const Byte *src, SizeT srcLen,\n-    const CLzmaEncProps *props, Byte *propsEncoded, SizeT *propsSize, int writeEndMark,\n-    ICompressProgress *progress, ISzAlloc *alloc, ISzAlloc *allocBig);\n-\n #ifdef __cplusplus\n }\n #endif\n--- a/lib/lzma/LzFind.c\n+++ b/lib/lzma/LzFind.c\n@@ -14,9 +14,15 @@\n \n #define kStartMaxLen 3\n \n+#if 0\n+#define DIRECT_INPUT\tp->directInput\n+#else\n+#define DIRECT_INPUT\t1\n+#endif\n+\n static void LzInWindow_Free(CMatchFinder *p, ISzAlloc *alloc)\n {\n-  if (!p->directInput)\n+  if (!DIRECT_INPUT)\n   {\n     alloc->Free(alloc, p->bufferBase);\n     p->bufferBase = 0;\n@@ -28,7 +34,7 @@ static void LzInWindow_Free(CMatchFinder\n static int LzInWindow_Create(CMatchFinder *p, UInt32 keepSizeReserv, ISzAlloc *alloc)\n {\n   UInt32 blockSize = p->keepSizeBefore + p->keepSizeAfter + keepSizeReserv;\n-  if (p->directInput)\n+  if (DIRECT_INPUT)\n   {\n     p->blockSize = blockSize;\n     return 1;\n@@ -42,12 +48,12 @@ static int LzInWindow_Create(CMatchFinde\n   return (p->bufferBase != 0);\n }\n \n-Byte *MatchFinder_GetPointerToCurrentPos(CMatchFinder *p) { return p->buffer; }\n-Byte MatchFinder_GetIndexByte(CMatchFinder *p, Int32 index) { return p->buffer[index]; }\n+static Byte *MatchFinder_GetPointerToCurrentPos(CMatchFinder *p) { return p->buffer; }\n+static Byte MatchFinder_GetIndexByte(CMatchFinder *p, Int32 index) { return p->buffer[index]; }\n \n-UInt32 MatchFinder_GetNumAvailableBytes(CMatchFinder *p) { return p->streamPos - p->pos; }\n+static UInt32 MatchFinder_GetNumAvailableBytes(CMatchFinder *p) { return p->streamPos - p->pos; }\n \n-void MatchFinder_ReduceOffsets(CMatchFinder *p, UInt32 subValue)\n+static void MatchFinder_ReduceOffsets(CMatchFinder *p, UInt32 subValue)\n {\n   p->posLimit -= subValue;\n   p->pos -= subValue;\n@@ -58,7 +64,7 @@ static void MatchFinder_ReadBlock(CMatch\n {\n   if (p->streamEndWasReached || p->result != SZ_OK)\n     return;\n-  if (p->directInput)\n+  if (DIRECT_INPUT)\n   {\n     UInt32 curSize = 0xFFFFFFFF - p->streamPos;\n     if (curSize > p->directInputRem)\n@@ -89,7 +95,7 @@ static void MatchFinder_ReadBlock(CMatch\n   }\n }\n \n-void MatchFinder_MoveBlock(CMatchFinder *p)\n+static void MatchFinder_MoveBlock(CMatchFinder *p)\n {\n   memmove(p->bufferBase,\n     p->buffer - p->keepSizeBefore,\n@@ -97,22 +103,14 @@ void MatchFinder_MoveBlock(CMatchFinder\n   p->buffer = p->bufferBase + p->keepSizeBefore;\n }\n \n-int MatchFinder_NeedMove(CMatchFinder *p)\n+static int MatchFinder_NeedMove(CMatchFinder *p)\n {\n-  if (p->directInput)\n+  if (DIRECT_INPUT)\n     return 0;\n   /* if (p->streamEndWasReached) return 0; */\n   return ((size_t)(p->bufferBase + p->blockSize - p->buffer) <= p->keepSizeAfter);\n }\n \n-void MatchFinder_ReadIfRequired(CMatchFinder *p)\n-{\n-  if (p->streamEndWasReached)\n-    return;\n-  if (p->keepSizeAfter >= p->streamPos - p->pos)\n-    MatchFinder_ReadBlock(p);\n-}\n-\n static void MatchFinder_CheckAndMoveAndRead(CMatchFinder *p)\n {\n   if (MatchFinder_NeedMove(p))\n@@ -268,7 +266,7 @@ static void MatchFinder_SetLimits(CMatch\n   p->posLimit = p->pos + limit;\n }\n \n-void MatchFinder_Init(CMatchFinder *p)\n+static void MatchFinder_Init(CMatchFinder *p)\n {\n   UInt32 i;\n   for (i = 0; i < p->hashSizeSum; i++)\n@@ -287,7 +285,7 @@ static UInt32 MatchFinder_GetSubValue(CM\n   return (p->pos - p->historySize - 1) & kNormalizeMask;\n }\n \n-void MatchFinder_Normalize3(UInt32 subValue, CLzRef *items, UInt32 numItems)\n+static void MatchFinder_Normalize3(UInt32 subValue, CLzRef *items, UInt32 numItems)\n {\n   UInt32 i;\n   for (i = 0; i < numItems; i++)\n@@ -319,38 +317,7 @@ static void MatchFinder_CheckLimits(CMat\n   MatchFinder_SetLimits(p);\n }\n \n-static UInt32 * Hc_GetMatchesSpec(UInt32 lenLimit, UInt32 curMatch, UInt32 pos, const Byte *cur, CLzRef *son,\n-    UInt32 _cyclicBufferPos, UInt32 _cyclicBufferSize, UInt32 cutValue,\n-    UInt32 *distances, UInt32 maxLen)\n-{\n-  son[_cyclicBufferPos] = curMatch;\n-  for (;;)\n-  {\n-    UInt32 delta = pos - curMatch;\n-    if (cutValue-- == 0 || delta >= _cyclicBufferSize)\n-      return distances;\n-    {\n-      const Byte *pb = cur - delta;\n-      curMatch = son[_cyclicBufferPos - delta + ((delta > _cyclicBufferPos) ? _cyclicBufferSize : 0)];\n-      if (pb[maxLen] == cur[maxLen] && *pb == *cur)\n-      {\n-        UInt32 len = 0;\n-        while (++len != lenLimit)\n-          if (pb[len] != cur[len])\n-            break;\n-        if (maxLen < len)\n-        {\n-          *distances++ = maxLen = len;\n-          *distances++ = delta - 1;\n-          if (len == lenLimit)\n-            return distances;\n-        }\n-      }\n-    }\n-  }\n-}\n-\n-UInt32 * GetMatchesSpec1(UInt32 lenLimit, UInt32 curMatch, UInt32 pos, const Byte *cur, CLzRef *son,\n+static UInt32 * GetMatchesSpec1(UInt32 lenLimit, UInt32 curMatch, UInt32 pos, const Byte *cur, CLzRef *son,\n     UInt32 _cyclicBufferPos, UInt32 _cyclicBufferSize, UInt32 cutValue,\n     UInt32 *distances, UInt32 maxLen)\n {\n@@ -460,10 +427,10 @@ static void SkipMatchesSpec(UInt32 lenLi\n   p->buffer++; \\\n   if (++p->pos == p->posLimit) MatchFinder_CheckLimits(p);\n \n-#define MOVE_POS_RET MOVE_POS return offset;\n-\n static void MatchFinder_MovePos(CMatchFinder *p) { MOVE_POS; }\n \n+#define MOVE_POS_RET MatchFinder_MovePos(p); return offset;\n+\n #define GET_MATCHES_HEADER2(minLen, ret_op) \\\n   UInt32 lenLimit; UInt32 hashValue; const Byte *cur; UInt32 curMatch; \\\n   lenLimit = p->lenLimit; { if (lenLimit < minLen) { MatchFinder_MovePos(p); ret_op; }} \\\n@@ -479,62 +446,7 @@ static void MatchFinder_MovePos(CMatchFi\n   distances + offset, maxLen) - distances); MOVE_POS_RET;\n \n #define SKIP_FOOTER \\\n-  SkipMatchesSpec(lenLimit, curMatch, MF_PARAMS(p)); MOVE_POS;\n-\n-static UInt32 Bt2_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances)\n-{\n-  UInt32 offset;\n-  GET_MATCHES_HEADER(2)\n-  HASH2_CALC;\n-  curMatch = p->hash[hashValue];\n-  p->hash[hashValue] = p->pos;\n-  offset = 0;\n-  GET_MATCHES_FOOTER(offset, 1)\n-}\n-\n-UInt32 Bt3Zip_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances)\n-{\n-  UInt32 offset;\n-  GET_MATCHES_HEADER(3)\n-  HASH_ZIP_CALC;\n-  curMatch = p->hash[hashValue];\n-  p->hash[hashValue] = p->pos;\n-  offset = 0;\n-  GET_MATCHES_FOOTER(offset, 2)\n-}\n-\n-static UInt32 Bt3_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances)\n-{\n-  UInt32 hash2Value, delta2, maxLen, offset;\n-  GET_MATCHES_HEADER(3)\n-\n-  HASH3_CALC;\n-\n-  delta2 = p->pos - p->hash[hash2Value];\n-  curMatch = p->hash[kFix3HashSize + hashValue];\n-\n-  p->hash[hash2Value] =\n-  p->hash[kFix3HashSize + hashValue] = p->pos;\n-\n-\n-  maxLen = 2;\n-  offset = 0;\n-  if (delta2 < p->cyclicBufferSize && *(cur - delta2) == *cur)\n-  {\n-    for (; maxLen != lenLimit; maxLen++)\n-      if (cur[(ptrdiff_t)maxLen - delta2] != cur[maxLen])\n-        break;\n-    distances[0] = maxLen;\n-    distances[1] = delta2 - 1;\n-    offset = 2;\n-    if (maxLen == lenLimit)\n-    {\n-      SkipMatchesSpec(lenLimit, curMatch, MF_PARAMS(p));\n-      MOVE_POS_RET;\n-    }\n-  }\n-  GET_MATCHES_FOOTER(offset, maxLen)\n-}\n+  SkipMatchesSpec(lenLimit, curMatch, MF_PARAMS(p)); MatchFinder_MovePos(p);\n \n static UInt32 Bt4_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances)\n {\n@@ -583,108 +495,6 @@ static UInt32 Bt4_MatchFinder_GetMatches\n   GET_MATCHES_FOOTER(offset, maxLen)\n }\n \n-static UInt32 Hc4_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances)\n-{\n-  UInt32 hash2Value, hash3Value, delta2, delta3, maxLen, offset;\n-  GET_MATCHES_HEADER(4)\n-\n-  HASH4_CALC;\n-\n-  delta2 = p->pos - p->hash[                hash2Value];\n-  delta3 = p->pos - p->hash[kFix3HashSize + hash3Value];\n-  curMatch = p->hash[kFix4HashSize + hashValue];\n-\n-  p->hash[                hash2Value] =\n-  p->hash[kFix3HashSize + hash3Value] =\n-  p->hash[kFix4HashSize + hashValue] = p->pos;\n-\n-  maxLen = 1;\n-  offset = 0;\n-  if (delta2 < p->cyclicBufferSize && *(cur - delta2) == *cur)\n-  {\n-    distances[0] = maxLen = 2;\n-    distances[1] = delta2 - 1;\n-    offset = 2;\n-  }\n-  if (delta2 != delta3 && delta3 < p->cyclicBufferSize && *(cur - delta3) == *cur)\n-  {\n-    maxLen = 3;\n-    distances[offset + 1] = delta3 - 1;\n-    offset += 2;\n-    delta2 = delta3;\n-  }\n-  if (offset != 0)\n-  {\n-    for (; maxLen != lenLimit; maxLen++)\n-      if (cur[(ptrdiff_t)maxLen - delta2] != cur[maxLen])\n-        break;\n-    distances[offset - 2] = maxLen;\n-    if (maxLen == lenLimit)\n-    {\n-      p->son[p->cyclicBufferPos] = curMatch;\n-      MOVE_POS_RET;\n-    }\n-  }\n-  if (maxLen < 3)\n-    maxLen = 3;\n-  offset = (UInt32)(Hc_GetMatchesSpec(lenLimit, curMatch, MF_PARAMS(p),\n-    distances + offset, maxLen) - (distances));\n-  MOVE_POS_RET\n-}\n-\n-UInt32 Hc3Zip_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances)\n-{\n-  UInt32 offset;\n-  GET_MATCHES_HEADER(3)\n-  HASH_ZIP_CALC;\n-  curMatch = p->hash[hashValue];\n-  p->hash[hashValue] = p->pos;\n-  offset = (UInt32)(Hc_GetMatchesSpec(lenLimit, curMatch, MF_PARAMS(p),\n-    distances, 2) - (distances));\n-  MOVE_POS_RET\n-}\n-\n-static void Bt2_MatchFinder_Skip(CMatchFinder *p, UInt32 num)\n-{\n-  do\n-  {\n-    SKIP_HEADER(2)\n-    HASH2_CALC;\n-    curMatch = p->hash[hashValue];\n-    p->hash[hashValue] = p->pos;\n-    SKIP_FOOTER\n-  }\n-  while (--num != 0);\n-}\n-\n-void Bt3Zip_MatchFinder_Skip(CMatchFinder *p, UInt32 num)\n-{\n-  do\n-  {\n-    SKIP_HEADER(3)\n-    HASH_ZIP_CALC;\n-    curMatch = p->hash[hashValue];\n-    p->hash[hashValue] = p->pos;\n-    SKIP_FOOTER\n-  }\n-  while (--num != 0);\n-}\n-\n-static void Bt3_MatchFinder_Skip(CMatchFinder *p, UInt32 num)\n-{\n-  do\n-  {\n-    UInt32 hash2Value;\n-    SKIP_HEADER(3)\n-    HASH3_CALC;\n-    curMatch = p->hash[kFix3HashSize + hashValue];\n-    p->hash[hash2Value] =\n-    p->hash[kFix3HashSize + hashValue] = p->pos;\n-    SKIP_FOOTER\n-  }\n-  while (--num != 0);\n-}\n-\n static void Bt4_MatchFinder_Skip(CMatchFinder *p, UInt32 num)\n {\n   do\n@@ -701,61 +511,12 @@ static void Bt4_MatchFinder_Skip(CMatchF\n   while (--num != 0);\n }\n \n-static void Hc4_MatchFinder_Skip(CMatchFinder *p, UInt32 num)\n-{\n-  do\n-  {\n-    UInt32 hash2Value, hash3Value;\n-    SKIP_HEADER(4)\n-    HASH4_CALC;\n-    curMatch = p->hash[kFix4HashSize + hashValue];\n-    p->hash[                hash2Value] =\n-    p->hash[kFix3HashSize + hash3Value] =\n-    p->hash[kFix4HashSize + hashValue] = p->pos;\n-    p->son[p->cyclicBufferPos] = curMatch;\n-    MOVE_POS\n-  }\n-  while (--num != 0);\n-}\n-\n-void Hc3Zip_MatchFinder_Skip(CMatchFinder *p, UInt32 num)\n-{\n-  do\n-  {\n-    SKIP_HEADER(3)\n-    HASH_ZIP_CALC;\n-    curMatch = p->hash[hashValue];\n-    p->hash[hashValue] = p->pos;\n-    p->son[p->cyclicBufferPos] = curMatch;\n-    MOVE_POS\n-  }\n-  while (--num != 0);\n-}\n-\n void MatchFinder_CreateVTable(CMatchFinder *p, IMatchFinder *vTable)\n {\n   vTable->Init = (Mf_Init_Func)MatchFinder_Init;\n   vTable->GetIndexByte = (Mf_GetIndexByte_Func)MatchFinder_GetIndexByte;\n   vTable->GetNumAvailableBytes = (Mf_GetNumAvailableBytes_Func)MatchFinder_GetNumAvailableBytes;\n   vTable->GetPointerToCurrentPos = (Mf_GetPointerToCurrentPos_Func)MatchFinder_GetPointerToCurrentPos;\n-  if (!p->btMode)\n-  {\n-    vTable->GetMatches = (Mf_GetMatches_Func)Hc4_MatchFinder_GetMatches;\n-    vTable->Skip = (Mf_Skip_Func)Hc4_MatchFinder_Skip;\n-  }\n-  else if (p->numHashBytes == 2)\n-  {\n-    vTable->GetMatches = (Mf_GetMatches_Func)Bt2_MatchFinder_GetMatches;\n-    vTable->Skip = (Mf_Skip_Func)Bt2_MatchFinder_Skip;\n-  }\n-  else if (p->numHashBytes == 3)\n-  {\n-    vTable->GetMatches = (Mf_GetMatches_Func)Bt3_MatchFinder_GetMatches;\n-    vTable->Skip = (Mf_Skip_Func)Bt3_MatchFinder_Skip;\n-  }\n-  else\n-  {\n-    vTable->GetMatches = (Mf_GetMatches_Func)Bt4_MatchFinder_GetMatches;\n-    vTable->Skip = (Mf_Skip_Func)Bt4_MatchFinder_Skip;\n-  }\n+  vTable->GetMatches = (Mf_GetMatches_Func)Bt4_MatchFinder_GetMatches;\n+  vTable->Skip = (Mf_Skip_Func)Bt4_MatchFinder_Skip;\n }\n--- a/lib/lzma/LzmaDec.c\n+++ b/lib/lzma/LzmaDec.c\n@@ -682,7 +682,7 @@ static void LzmaDec_InitRc(CLzmaDec *p,\n   p->needFlush = 0;\n }\n \n-void LzmaDec_InitDicAndState(CLzmaDec *p, Bool initDic, Bool initState)\n+static void LzmaDec_InitDicAndState(CLzmaDec *p, Bool initDic, Bool initState)\n {\n   p->needFlush = 1;\n   p->remainLen = 0;\n@@ -698,7 +698,7 @@ void LzmaDec_InitDicAndState(CLzmaDec *p\n     p->needInitState = 1;\n }\n \n-void LzmaDec_Init(CLzmaDec *p)\n+static void LzmaDec_Init(CLzmaDec *p)\n {\n   p->dicPos = 0;\n   LzmaDec_InitDicAndState(p, True, True);\n@@ -716,7 +716,7 @@ static void LzmaDec_InitStateReal(CLzmaD\n   p->needInitState = 0;\n }\n \n-SRes LzmaDec_DecodeToDic(CLzmaDec *p, SizeT dicLimit, const Byte *src, SizeT *srcLen,\n+static SRes LzmaDec_DecodeToDic(CLzmaDec *p, SizeT dicLimit, const Byte *src, SizeT *srcLen,\n     ELzmaFinishMode finishMode, ELzmaStatus *status)\n {\n   SizeT inSize = *srcLen;\n@@ -837,65 +837,13 @@ SRes LzmaDec_DecodeToDic(CLzmaDec *p, Si\n   return (p->code == 0) ? SZ_OK : SZ_ERROR_DATA;\n }\n \n-SRes LzmaDec_DecodeToBuf(CLzmaDec *p, Byte *dest, SizeT *destLen, const Byte *src, SizeT *srcLen, ELzmaFinishMode finishMode, ELzmaStatus *status)\n-{\n-  SizeT outSize = *destLen;\n-  SizeT inSize = *srcLen;\n-  *srcLen = *destLen = 0;\n-  for (;;)\n-  {\n-    SizeT inSizeCur = inSize, outSizeCur, dicPos;\n-    ELzmaFinishMode curFinishMode;\n-    SRes res;\n-    if (p->dicPos == p->dicBufSize)\n-      p->dicPos = 0;\n-    dicPos = p->dicPos;\n-    if (outSize > p->dicBufSize - dicPos)\n-    {\n-      outSizeCur = p->dicBufSize;\n-      curFinishMode = LZMA_FINISH_ANY;\n-    }\n-    else\n-    {\n-      outSizeCur = dicPos + outSize;\n-      curFinishMode = finishMode;\n-    }\n-\n-    res = LzmaDec_DecodeToDic(p, outSizeCur, src, &inSizeCur, curFinishMode, status);\n-    src += inSizeCur;\n-    inSize -= inSizeCur;\n-    *srcLen += inSizeCur;\n-    outSizeCur = p->dicPos - dicPos;\n-    memcpy(dest, p->dic + dicPos, outSizeCur);\n-    dest += outSizeCur;\n-    outSize -= outSizeCur;\n-    *destLen += outSizeCur;\n-    if (res != 0)\n-      return res;\n-    if (outSizeCur == 0 || outSize == 0)\n-      return SZ_OK;\n-  }\n-}\n-\n-void LzmaDec_FreeProbs(CLzmaDec *p, ISzAlloc *alloc)\n+static void LzmaDec_FreeProbs(CLzmaDec *p, ISzAlloc *alloc)\n {\n   alloc->Free(alloc, p->probs);\n   p->probs = 0;\n }\n \n-static void LzmaDec_FreeDict(CLzmaDec *p, ISzAlloc *alloc)\n-{\n-  alloc->Free(alloc, p->dic);\n-  p->dic = 0;\n-}\n-\n-void LzmaDec_Free(CLzmaDec *p, ISzAlloc *alloc)\n-{\n-  LzmaDec_FreeProbs(p, alloc);\n-  LzmaDec_FreeDict(p, alloc);\n-}\n-\n-SRes LzmaProps_Decode(CLzmaProps *p, const Byte *data, unsigned size)\n+static SRes LzmaProps_Decode(CLzmaProps *p, const Byte *data, unsigned size)\n {\n   UInt32 dicSize;\n   Byte d;\n@@ -935,7 +883,7 @@ static SRes LzmaDec_AllocateProbs2(CLzma\n   return SZ_OK;\n }\n \n-SRes LzmaDec_AllocateProbs(CLzmaDec *p, const Byte *props, unsigned propsSize, ISzAlloc *alloc)\n+static SRes LzmaDec_AllocateProbs(CLzmaDec *p, const Byte *props, unsigned propsSize, ISzAlloc *alloc)\n {\n   CLzmaProps propNew;\n   RINOK(LzmaProps_Decode(&propNew, props, propsSize));\n@@ -943,28 +891,6 @@ SRes LzmaDec_AllocateProbs(CLzmaDec *p,\n   p->prop = propNew;\n   return SZ_OK;\n }\n-\n-SRes LzmaDec_Allocate(CLzmaDec *p, const Byte *props, unsigned propsSize, ISzAlloc *alloc)\n-{\n-  CLzmaProps propNew;\n-  SizeT dicBufSize;\n-  RINOK(LzmaProps_Decode(&propNew, props, propsSize));\n-  RINOK(LzmaDec_AllocateProbs2(p, &propNew, alloc));\n-  dicBufSize = propNew.dicSize;\n-  if (p->dic == 0 || dicBufSize != p->dicBufSize)\n-  {\n-    LzmaDec_FreeDict(p, alloc);\n-    p->dic = (Byte *)alloc->Alloc(alloc, dicBufSize);\n-    if (p->dic == 0)\n-    {\n-      LzmaDec_FreeProbs(p, alloc);\n-      return SZ_ERROR_MEM;\n-    }\n-  }\n-  p->dicBufSize = dicBufSize;\n-  p->prop = propNew;\n-  return SZ_OK;\n-}\n \n SRes LzmaDecode(Byte *dest, SizeT *destLen, const Byte *src, SizeT *srcLen,\n     const Byte *propData, unsigned propSize, ELzmaFinishMode finishMode,\n--- a/lib/lzma/LzmaEnc.c\n+++ b/lib/lzma/LzmaEnc.c\n@@ -53,7 +53,7 @@ void LzmaEncProps_Init(CLzmaEncProps *p)\n   p->writeEndMark = 0;\n }\n \n-void LzmaEncProps_Normalize(CLzmaEncProps *p)\n+static void LzmaEncProps_Normalize(CLzmaEncProps *p)\n {\n   int level = p->level;\n   if (level < 0) level = 5;\n@@ -76,7 +76,7 @@ void LzmaEncProps_Normalize(CLzmaEncProp\n       #endif\n }\n \n-UInt32 LzmaEncProps_GetDictSize(const CLzmaEncProps *props2)\n+static UInt32 __maybe_unused LzmaEncProps_GetDictSize(const CLzmaEncProps *props2)\n {\n   CLzmaEncProps props = *props2;\n   LzmaEncProps_Normalize(&props);\n@@ -93,7 +93,7 @@ UInt32 LzmaEncProps_GetDictSize(const CL\n \n #define BSR2_RET(pos, res) { unsigned long i; _BitScanReverse(&i, (pos)); res = (i + i) + ((pos >> (i - 1)) & 1); }\n \n-UInt32 GetPosSlot1(UInt32 pos)\n+static UInt32 GetPosSlot1(UInt32 pos)\n {\n   UInt32 res;\n   BSR2_RET(pos, res);\n@@ -107,7 +107,7 @@ UInt32 GetPosSlot1(UInt32 pos)\n #define kNumLogBits (9 + (int)sizeof(size_t) / 2)\n #define kDicLogSizeMaxCompress ((kNumLogBits - 1) * 2 + 7)\n \n-void LzmaEnc_FastPosInit(Byte *g_FastPos)\n+static void LzmaEnc_FastPosInit(Byte *g_FastPos)\n {\n   int c = 2, slotFast;\n   g_FastPos[0] = 0;\n@@ -339,58 +339,6 @@ typedef struct\n   CSaveState saveState;\n } CLzmaEnc;\n \n-void LzmaEnc_SaveState(CLzmaEncHandle pp)\n-{\n-  CLzmaEnc *p = (CLzmaEnc *)pp;\n-  CSaveState *dest = &p->saveState;\n-  int i;\n-  dest->lenEnc = p->lenEnc;\n-  dest->repLenEnc = p->repLenEnc;\n-  dest->state = p->state;\n-\n-  for (i = 0; i < kNumStates; i++)\n-  {\n-    memcpy(dest->isMatch[i], p->isMatch[i], sizeof(p->isMatch[i]));\n-    memcpy(dest->isRep0Long[i], p->isRep0Long[i], sizeof(p->isRep0Long[i]));\n-  }\n-  for (i = 0; i < kNumLenToPosStates; i++)\n-    memcpy(dest->posSlotEncoder[i], p->posSlotEncoder[i], sizeof(p->posSlotEncoder[i]));\n-  memcpy(dest->isRep, p->isRep, sizeof(p->isRep));\n-  memcpy(dest->isRepG0, p->isRepG0, sizeof(p->isRepG0));\n-  memcpy(dest->isRepG1, p->isRepG1, sizeof(p->isRepG1));\n-  memcpy(dest->isRepG2, p->isRepG2, sizeof(p->isRepG2));\n-  memcpy(dest->posEncoders, p->posEncoders, sizeof(p->posEncoders));\n-  memcpy(dest->posAlignEncoder, p->posAlignEncoder, sizeof(p->posAlignEncoder));\n-  memcpy(dest->reps, p->reps, sizeof(p->reps));\n-  memcpy(dest->litProbs, p->litProbs, (0x300 << p->lclp) * sizeof(CLzmaProb));\n-}\n-\n-void LzmaEnc_RestoreState(CLzmaEncHandle pp)\n-{\n-  CLzmaEnc *dest = (CLzmaEnc *)pp;\n-  const CSaveState *p = &dest->saveState;\n-  int i;\n-  dest->lenEnc = p->lenEnc;\n-  dest->repLenEnc = p->repLenEnc;\n-  dest->state = p->state;\n-\n-  for (i = 0; i < kNumStates; i++)\n-  {\n-    memcpy(dest->isMatch[i], p->isMatch[i], sizeof(p->isMatch[i]));\n-    memcpy(dest->isRep0Long[i], p->isRep0Long[i], sizeof(p->isRep0Long[i]));\n-  }\n-  for (i = 0; i < kNumLenToPosStates; i++)\n-    memcpy(dest->posSlotEncoder[i], p->posSlotEncoder[i], sizeof(p->posSlotEncoder[i]));\n-  memcpy(dest->isRep, p->isRep, sizeof(p->isRep));\n-  memcpy(dest->isRepG0, p->isRepG0, sizeof(p->isRepG0));\n-  memcpy(dest->isRepG1, p->isRepG1, sizeof(p->isRepG1));\n-  memcpy(dest->isRepG2, p->isRepG2, sizeof(p->isRepG2));\n-  memcpy(dest->posEncoders, p->posEncoders, sizeof(p->posEncoders));\n-  memcpy(dest->posAlignEncoder, p->posAlignEncoder, sizeof(p->posAlignEncoder));\n-  memcpy(dest->reps, p->reps, sizeof(p->reps));\n-  memcpy(dest->litProbs, p->litProbs, (0x300 << dest->lclp) * sizeof(CLzmaProb));\n-}\n-\n SRes LzmaEnc_SetProps(CLzmaEncHandle pp, const CLzmaEncProps *props2)\n {\n   CLzmaEnc *p = (CLzmaEnc *)pp;\n@@ -600,7 +548,7 @@ static void LitEnc_EncodeMatched(CRangeE\n   while (symbol < 0x10000);\n }\n \n-void LzmaEnc_InitPriceTables(UInt32 *ProbPrices)\n+static void LzmaEnc_InitPriceTables(UInt32 *ProbPrices)\n {\n   UInt32 i;\n   for (i = (1 << kNumMoveReducingBits) / 2; i < kBitModelTotal; i += (1 << kNumMoveReducingBits))\n@@ -1676,7 +1624,7 @@ static void FillDistancesPrices(CLzmaEnc\n   p->matchPriceCount = 0;\n }\n \n-void LzmaEnc_Construct(CLzmaEnc *p)\n+static void LzmaEnc_Construct(CLzmaEnc *p)\n {\n   RangeEnc_Construct(&p->rc);\n   MatchFinder_Construct(&p->matchFinderBase);\n@@ -1709,7 +1657,7 @@ CLzmaEncHandle LzmaEnc_Create(ISzAlloc *\n   return p;\n }\n \n-void LzmaEnc_FreeLits(CLzmaEnc *p, ISzAlloc *alloc)\n+static void LzmaEnc_FreeLits(CLzmaEnc *p, ISzAlloc *alloc)\n {\n   alloc->Free(alloc, p->litProbs);\n   alloc->Free(alloc, p->saveState.litProbs);\n@@ -1717,7 +1665,7 @@ void LzmaEnc_FreeLits(CLzmaEnc *p, ISzAl\n   p->saveState.litProbs = 0;\n }\n \n-void LzmaEnc_Destruct(CLzmaEnc *p, ISzAlloc *alloc, ISzAlloc *allocBig)\n+static void LzmaEnc_Destruct(CLzmaEnc *p, ISzAlloc *alloc, ISzAlloc *allocBig)\n {\n   #ifndef _7ZIP_ST\n   MatchFinderMt_Destruct(&p->matchFinderMt, allocBig);\n@@ -1947,7 +1895,7 @@ static SRes LzmaEnc_Alloc(CLzmaEnc *p, U\n   return SZ_OK;\n }\n \n-void LzmaEnc_Init(CLzmaEnc *p)\n+static void LzmaEnc_Init(CLzmaEnc *p)\n {\n   UInt32 i;\n   p->state = 0;\n@@ -2005,7 +1953,7 @@ void LzmaEnc_Init(CLzmaEnc *p)\n   p->lpMask = (1 << p->lp) - 1;\n }\n \n-void LzmaEnc_InitPrices(CLzmaEnc *p)\n+static void LzmaEnc_InitPrices(CLzmaEnc *p)\n {\n   if (!p->fastMode)\n   {\n@@ -2037,26 +1985,6 @@ static SRes LzmaEnc_AllocAndInit(CLzmaEn\n   return SZ_OK;\n }\n \n-static SRes LzmaEnc_Prepare(CLzmaEncHandle pp, ISeqOutStream *outStream, ISeqInStream *inStream,\n-    ISzAlloc *alloc, ISzAlloc *allocBig)\n-{\n-  CLzmaEnc *p = (CLzmaEnc *)pp;\n-  p->matchFinderBase.stream = inStream;\n-  p->needInit = 1;\n-  p->rc.outStream = outStream;\n-  return LzmaEnc_AllocAndInit(p, 0, alloc, allocBig);\n-}\n-\n-SRes LzmaEnc_PrepareForLzma2(CLzmaEncHandle pp,\n-    ISeqInStream *inStream, UInt32 keepWindowSize,\n-    ISzAlloc *alloc, ISzAlloc *allocBig)\n-{\n-  CLzmaEnc *p = (CLzmaEnc *)pp;\n-  p->matchFinderBase.stream = inStream;\n-  p->needInit = 1;\n-  return LzmaEnc_AllocAndInit(p, keepWindowSize, alloc, allocBig);\n-}\n-\n static void LzmaEnc_SetInputBuf(CLzmaEnc *p, const Byte *src, SizeT srcLen)\n {\n   p->matchFinderBase.directInput = 1;\n@@ -2064,7 +1992,7 @@ static void LzmaEnc_SetInputBuf(CLzmaEnc\n   p->matchFinderBase.directInputRem = srcLen;\n }\n \n-SRes LzmaEnc_MemPrepare(CLzmaEncHandle pp, const Byte *src, SizeT srcLen,\n+static SRes LzmaEnc_MemPrepare(CLzmaEncHandle pp, const Byte *src, SizeT srcLen,\n     UInt32 keepWindowSize, ISzAlloc *alloc, ISzAlloc *allocBig)\n {\n   CLzmaEnc *p = (CLzmaEnc *)pp;\n@@ -2074,7 +2002,7 @@ SRes LzmaEnc_MemPrepare(CLzmaEncHandle p\n   return LzmaEnc_AllocAndInit(p, keepWindowSize, alloc, allocBig);\n }\n \n-void LzmaEnc_Finish(CLzmaEncHandle pp)\n+static void LzmaEnc_Finish(CLzmaEncHandle pp)\n {\n   #ifndef _7ZIP_ST\n   CLzmaEnc *p = (CLzmaEnc *)pp;\n@@ -2107,53 +2035,6 @@ static size_t MyWrite(void *pp, const vo\n   return size;\n }\n \n-\n-UInt32 LzmaEnc_GetNumAvailableBytes(CLzmaEncHandle pp)\n-{\n-  const CLzmaEnc *p = (CLzmaEnc *)pp;\n-  return p->matchFinder.GetNumAvailableBytes(p->matchFinderObj);\n-}\n-\n-const Byte *LzmaEnc_GetCurBuf(CLzmaEncHandle pp)\n-{\n-  const CLzmaEnc *p = (CLzmaEnc *)pp;\n-  return p->matchFinder.GetPointerToCurrentPos(p->matchFinderObj) - p->additionalOffset;\n-}\n-\n-SRes LzmaEnc_CodeOneMemBlock(CLzmaEncHandle pp, Bool reInit,\n-    Byte *dest, size_t *destLen, UInt32 desiredPackSize, UInt32 *unpackSize)\n-{\n-  CLzmaEnc *p = (CLzmaEnc *)pp;\n-  UInt64 nowPos64;\n-  SRes res;\n-  CSeqOutStreamBuf outStream;\n-\n-  outStream.funcTable.Write = MyWrite;\n-  outStream.data = dest;\n-  outStream.rem = *destLen;\n-  outStream.overflow = False;\n-\n-  p->writeEndMark = False;\n-  p->finished = False;\n-  p->result = SZ_OK;\n-\n-  if (reInit)\n-    LzmaEnc_Init(p);\n-  LzmaEnc_InitPrices(p);\n-  nowPos64 = p->nowPos64;\n-  RangeEnc_Init(&p->rc);\n-  p->rc.outStream = &outStream.funcTable;\n-\n-  res = LzmaEnc_CodeOneBlock(p, True, desiredPackSize, *unpackSize);\n-\n-  *unpackSize = (UInt32)(p->nowPos64 - nowPos64);\n-  *destLen -= outStream.rem;\n-  if (outStream.overflow)\n-    return SZ_ERROR_OUTPUT_EOF;\n-\n-  return res;\n-}\n-\n static SRes LzmaEnc_Encode2(CLzmaEnc *p, ICompressProgress *progress)\n {\n   SRes res = SZ_OK;\n@@ -2184,13 +2065,6 @@ static SRes LzmaEnc_Encode2(CLzmaEnc *p,\n   return res;\n }\n \n-SRes LzmaEnc_Encode(CLzmaEncHandle pp, ISeqOutStream *outStream, ISeqInStream *inStream, ICompressProgress *progress,\n-    ISzAlloc *alloc, ISzAlloc *allocBig)\n-{\n-  RINOK(LzmaEnc_Prepare(pp, outStream, inStream, alloc, allocBig));\n-  return LzmaEnc_Encode2((CLzmaEnc *)pp, progress);\n-}\n-\n SRes LzmaEnc_WriteProperties(CLzmaEncHandle pp, Byte *props, SizeT *size)\n {\n   CLzmaEnc *p = (CLzmaEnc *)pp;\n@@ -2247,25 +2121,3 @@ SRes LzmaEnc_MemEncode(CLzmaEncHandle pp\n     return SZ_ERROR_OUTPUT_EOF;\n   return res;\n }\n-\n-SRes LzmaEncode(Byte *dest, SizeT *destLen, const Byte *src, SizeT srcLen,\n-    const CLzmaEncProps *props, Byte *propsEncoded, SizeT *propsSize, int writeEndMark,\n-    ICompressProgress *progress, ISzAlloc *alloc, ISzAlloc *allocBig)\n-{\n-  CLzmaEnc *p = (CLzmaEnc *)LzmaEnc_Create(alloc);\n-  SRes res;\n-  if (p == 0)\n-    return SZ_ERROR_MEM;\n-\n-  res = LzmaEnc_SetProps(p, props);\n-  if (res == SZ_OK)\n-  {\n-    res = LzmaEnc_WriteProperties(p, propsEncoded, propsSize);\n-    if (res == SZ_OK)\n-      res = LzmaEnc_MemEncode(p, dest, destLen, src, srcLen,\n-          writeEndMark, progress, alloc, allocBig);\n-  }\n-\n-  LzmaEnc_Destroy(p, alloc, allocBig);\n-  return res;\n-}\n"
  },
  {
    "path": "target/linux/generic/hack-5.10/600-bridge_offload.patch",
    "content": "--- a/include/linux/if_bridge.h\n+++ b/include/linux/if_bridge.h\n@@ -57,6 +57,7 @@ struct br_ip_list {\n #define BR_MRP_LOST_CONT\tBIT(18)\n #define BR_MRP_LOST_IN_CONT\tBIT(19)\n #define BR_BPDU_FILTER\t\tBIT(20)\n+#define BR_OFFLOAD\t\tBIT(21)\n \n #define BR_DEFAULT_AGEING_TIME\t(300 * HZ)\n \n--- a/net/bridge/Makefile\n+++ b/net/bridge/Makefile\n@@ -5,7 +5,7 @@\n \n obj-$(CONFIG_BRIDGE) += bridge.o\n \n-bridge-y\t:= br.o br_device.o br_fdb.o br_forward.o br_if.o br_input.o \\\n+bridge-y\t:= br.o br_device.o br_fdb.o br_forward.o br_if.o br_input.o br_offload.o \\\n \t\t\tbr_ioctl.o br_stp.o br_stp_bpdu.o \\\n \t\t\tbr_stp_if.o br_stp_timer.o br_netlink.o \\\n \t\t\tbr_netlink_tunnel.o br_arp_nd_proxy.o\n--- a/net/bridge/br.c\n+++ b/net/bridge/br.c\n@@ -18,6 +18,7 @@\n #include <net/switchdev.h>\n \n #include \"br_private.h\"\n+#include \"br_private_offload.h\"\n \n /*\n  * Handle changes in state of network devices enslaved to a bridge.\n@@ -332,6 +333,10 @@ static int __init br_init(void)\n \tif (err)\n \t\tgoto err_out;\n \n+\terr = br_offload_init();\n+\tif (err)\n+\t\tgoto err_out0;\n+\n \terr = register_pernet_subsys(&br_net_ops);\n \tif (err)\n \t\tgoto err_out1;\n@@ -375,6 +380,8 @@ err_out3:\n err_out2:\n \tunregister_pernet_subsys(&br_net_ops);\n err_out1:\n+\tbr_offload_fini();\n+err_out0:\n \tbr_fdb_fini();\n err_out:\n \tstp_proto_unregister(&br_stp_proto);\n@@ -396,6 +403,7 @@ static void __exit br_deinit(void)\n #if IS_ENABLED(CONFIG_ATM_LANE)\n \tbr_fdb_test_addr_hook = NULL;\n #endif\n+\tbr_offload_fini();\n \tbr_fdb_fini();\n }\n \n--- a/net/bridge/br_device.c\n+++ b/net/bridge/br_device.c\n@@ -529,6 +529,8 @@ void br_dev_setup(struct net_device *dev\n \tbr->bridge_hello_time = br->hello_time = 2 * HZ;\n \tbr->bridge_forward_delay = br->forward_delay = 15 * HZ;\n \tbr->bridge_ageing_time = br->ageing_time = BR_DEFAULT_AGEING_TIME;\n+\tbr->offload_cache_size = 128;\n+\tbr->offload_cache_reserved = 8;\n \tdev->max_mtu = ETH_MAX_MTU;\n \n \tbr_netfilter_rtable_init(br);\n--- a/net/bridge/br_fdb.c\n+++ b/net/bridge/br_fdb.c\n@@ -23,6 +23,7 @@\n #include <net/switchdev.h>\n #include <trace/events/bridge.h>\n #include \"br_private.h\"\n+#include \"br_private_offload.h\"\n \n static const struct rhashtable_params br_fdb_rht_params = {\n \t.head_offset = offsetof(struct net_bridge_fdb_entry, rhnode),\n@@ -513,6 +514,8 @@ static struct net_bridge_fdb_entry *fdb_\n \t\tfdb->key.vlan_id = vid;\n \t\tfdb->flags = flags;\n \t\tfdb->updated = fdb->used = jiffies;\n+\t\tINIT_HLIST_HEAD(&fdb->offload_in);\n+\t\tINIT_HLIST_HEAD(&fdb->offload_out);\n \t\tif (rhashtable_lookup_insert_fast(&br->fdb_hash_tbl,\n \t\t\t\t\t\t  &fdb->rhnode,\n \t\t\t\t\t\t  br_fdb_rht_params)) {\n@@ -734,6 +737,8 @@ static void fdb_notify(struct net_bridge\n \tstruct sk_buff *skb;\n \tint err = -ENOBUFS;\n \n+\tbr_offload_fdb_update(fdb);\n+\n \tif (swdev_notify)\n \t\tbr_switchdev_fdb_notify(br, fdb, type);\n \n--- a/net/bridge/br_forward.c\n+++ b/net/bridge/br_forward.c\n@@ -16,6 +16,7 @@\n #include <linux/if_vlan.h>\n #include <linux/netfilter_bridge.h>\n #include \"br_private.h\"\n+#include \"br_private_offload.h\"\n \n /* Don't forward packets to originating port or forwarding disabled */\n static inline int should_deliver(const struct net_bridge_port *p,\n@@ -32,6 +33,8 @@ static inline int should_deliver(const s\n \n int br_dev_queue_push_xmit(struct net *net, struct sock *sk, struct sk_buff *skb)\n {\n+\tbr_offload_output(skb);\n+\n \tskb_push(skb, ETH_HLEN);\n \tif (!is_skb_forwardable(skb->dev, skb))\n \t\tgoto drop;\n--- a/net/bridge/br_if.c\n+++ b/net/bridge/br_if.c\n@@ -25,6 +25,7 @@\n #include <net/net_namespace.h>\n \n #include \"br_private.h\"\n+#include \"br_private_offload.h\"\n \n /*\n  * Determine initial path cost based on speed.\n@@ -427,7 +428,7 @@ static struct net_bridge_port *new_nbp(s\n \tp->path_cost = port_cost(dev);\n \tp->priority = 0x8000 >> BR_PORT_BITS;\n \tp->port_no = index;\n-\tp->flags = BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD | BR_BCAST_FLOOD;\n+\tp->flags = BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD | BR_BCAST_FLOOD | BR_OFFLOAD;\n \tbr_init_port(p);\n \tbr_set_state(p, BR_STATE_DISABLED);\n \tbr_stp_port_timer_init(p);\n@@ -777,6 +778,9 @@ void br_port_flags_change(struct net_bri\n \n \tif (mask & BR_NEIGH_SUPPRESS)\n \t\tbr_recalculate_neigh_suppress_enabled(br);\n+\n+\tif (mask & BR_OFFLOAD)\n+\t\tbr_offload_port_state(p);\n }\n \n bool br_port_flag_is_set(const struct net_device *dev, unsigned long flag)\n--- a/net/bridge/br_input.c\n+++ b/net/bridge/br_input.c\n@@ -22,6 +22,7 @@\n #include <linux/rculist.h>\n #include \"br_private.h\"\n #include \"br_private_tunnel.h\"\n+#include \"br_private_offload.h\"\n \n static int\n br_netif_receive_skb(struct net *net, struct sock *sk, struct sk_buff *skb)\n@@ -162,6 +163,7 @@ int br_handle_frame_finish(struct net *n\n \t\t\tdst->used = now;\n \t\tbr_forward(dst->dst, skb, local_rcv, false);\n \t} else {\n+\t\tbr_offload_skb_disable(skb);\n \t\tif (!mcast_hit)\n \t\t\tbr_flood(br, skb, pkt_type, local_rcv, false);\n \t\telse\n@@ -280,6 +282,9 @@ static rx_handler_result_t br_handle_fra\n \tmemset(skb->cb, 0, sizeof(struct br_input_skb_cb));\n \n \tp = br_port_get_rcu(skb->dev);\n+\tif (br_offload_input(p, skb))\n+\t\treturn RX_HANDLER_CONSUMED;\n+\n \tif (p->flags & BR_VLAN_TUNNEL) {\n \t\tif (br_handle_ingress_vlan_tunnel(skb, p,\n \t\t\t\t\t\t  nbp_vlan_group_rcu(p)))\n--- /dev/null\n+++ b/net/bridge/br_offload.c\n@@ -0,0 +1,436 @@\n+// SPDX-License-Identifier: GPL-2.0-only\n+#include <linux/kernel.h>\n+#include <linux/workqueue.h>\n+#include \"br_private.h\"\n+#include \"br_private_offload.h\"\n+\n+static DEFINE_SPINLOCK(offload_lock);\n+\n+struct bridge_flow_key {\n+\tu8 dest[ETH_ALEN];\n+\tu8 src[ETH_ALEN];\n+#ifdef CONFIG_BRIDGE_VLAN_FILTERING\n+\tu16 vlan_tag;\n+\tbool vlan_present;\n+#endif\n+};\n+\n+struct bridge_flow {\n+\tstruct net_bridge_port *port;\n+\tstruct rhash_head node;\n+\tstruct bridge_flow_key key;\n+#ifdef CONFIG_BRIDGE_VLAN_FILTERING\n+\tbool vlan_out_present;\n+\tu16 vlan_out;\n+#endif\n+\n+\tunsigned long used;\n+\tstruct net_bridge_fdb_entry *fdb_in, *fdb_out;\n+\tstruct hlist_node fdb_list_in, fdb_list_out;\n+\n+\tstruct rcu_head rcu;\n+};\n+\n+static const struct rhashtable_params flow_params = {\n+\t.automatic_shrinking = true,\n+\t.head_offset = offsetof(struct bridge_flow, node),\n+\t.key_len = sizeof(struct bridge_flow_key),\n+\t.key_offset = offsetof(struct bridge_flow, key),\n+};\n+\n+static struct kmem_cache *offload_cache __read_mostly;\n+\n+static void\n+flow_rcu_free(struct rcu_head *head)\n+{\n+\tstruct bridge_flow *flow;\n+\n+\tflow = container_of(head, struct bridge_flow, rcu);\n+\tkmem_cache_free(offload_cache, flow);\n+}\n+\n+static void\n+__br_offload_flow_free(struct bridge_flow *flow)\n+{\n+\tflow->used = 0;\n+\thlist_del(&flow->fdb_list_in);\n+\thlist_del(&flow->fdb_list_out);\n+\n+\tcall_rcu(&flow->rcu, flow_rcu_free);\n+}\n+\n+static void\n+br_offload_flow_free(struct bridge_flow *flow)\n+{\n+\tif (rhashtable_remove_fast(&flow->port->offload.rht, &flow->node,\n+\t\t\t\t   flow_params) != 0)\n+\t\treturn;\n+\n+\t__br_offload_flow_free(flow);\n+}\n+\n+static bool\n+br_offload_flow_fdb_refresh_time(struct bridge_flow *flow,\n+\t\t\t\t struct net_bridge_fdb_entry *fdb)\n+{\n+\tif (!time_after(flow->used, fdb->updated))\n+\t\treturn false;\n+\n+\tfdb->updated = flow->used;\n+\n+\treturn true;\n+}\n+\n+\n+static void\n+br_offload_flow_refresh_time(struct bridge_flow *flow)\n+{\n+\tbr_offload_flow_fdb_refresh_time(flow, flow->fdb_in);\n+\tbr_offload_flow_fdb_refresh_time(flow, flow->fdb_out);\n+}\n+\n+static void\n+br_offload_destroy_cb(void *ptr, void *arg)\n+{\n+\tstruct bridge_flow *flow = ptr;\n+\n+\t__br_offload_flow_free(flow);\n+}\n+\n+static bool\n+br_offload_need_gc(struct net_bridge_port *p)\n+{\n+\treturn (atomic_read(&p->offload.rht.nelems) +\n+\t        p->br->offload_cache_reserved) >= p->br->offload_cache_size;\n+}\n+\n+static void\n+br_offload_gc_work(struct work_struct *work)\n+{\n+\tstruct rhashtable_iter hti;\n+\tstruct net_bridge_port *p;\n+\tstruct bridge_flow *gc_flow = NULL;\n+\tstruct bridge_flow *flow;\n+\tunsigned long gc_used;\n+\n+\tp = container_of(work, struct net_bridge_port, offload.gc_work);\n+\n+\tif (!br_offload_need_gc(p))\n+\t\treturn;\n+\n+\trhashtable_walk_enter(&p->offload.rht, &hti);\n+\trhashtable_walk_start(&hti);\n+\twhile ((flow = rhashtable_walk_next(&hti)) != NULL) {\n+\t\tunsigned long used;\n+\n+\t\tif (IS_ERR(flow))\n+\t\t\tcontinue;\n+\n+\t\tused = READ_ONCE(flow->used);\n+\t\tif (!used)\n+\t\t\tcontinue;\n+\n+\t\tif (gc_flow && !time_before(used, gc_used))\n+\t\t\tcontinue;\n+\n+\t\tgc_flow = flow;\n+\t\tgc_used = used;\n+\t}\n+\trhashtable_walk_stop(&hti);\n+\trhashtable_walk_exit(&hti);\n+\n+\tif (!gc_flow)\n+\t\treturn;\n+\n+\tspin_lock_bh(&offload_lock);\n+\tif (br_offload_need_gc(p) && gc_flow &&\n+\t    gc_flow->used == gc_used)\n+\t\tbr_offload_flow_free(gc_flow);\n+\tif (p->offload.enabled && br_offload_need_gc(p))\n+\t\tqueue_work(system_long_wq, work);\n+\tspin_unlock_bh(&offload_lock);\n+\n+}\n+\n+void br_offload_port_state(struct net_bridge_port *p)\n+{\n+\tstruct net_bridge_port_offload *o = &p->offload;\n+\tbool enabled = true;\n+\tbool flush = false;\n+\n+\tif (p->state != BR_STATE_FORWARDING ||\n+\t    !(p->flags & BR_OFFLOAD))\n+\t\tenabled = false;\n+\n+\tspin_lock_bh(&offload_lock);\n+\tif (o->enabled == enabled)\n+\t\tgoto out;\n+\n+\tif (enabled) {\n+\t\tif (!o->gc_work.func)\n+\t\t\tINIT_WORK(&o->gc_work, br_offload_gc_work);\n+\t\trhashtable_init(&o->rht, &flow_params);\n+\t} else {\n+\t\tflush = true;\n+\t\trhashtable_free_and_destroy(&o->rht, br_offload_destroy_cb, o);\n+\t}\n+\n+\to->enabled = enabled;\n+\n+out:\n+\tspin_unlock_bh(&offload_lock);\n+\n+\tif (flush)\n+\t\tflush_work(&o->gc_work);\n+}\n+\n+void br_offload_fdb_update(const struct net_bridge_fdb_entry *fdb)\n+{\n+\tstruct bridge_flow *f;\n+\tstruct hlist_node *tmp;\n+\n+\tspin_lock_bh(&offload_lock);\n+\n+\thlist_for_each_entry_safe(f, tmp, &fdb->offload_in, fdb_list_in)\n+\t\tbr_offload_flow_free(f);\n+\n+\thlist_for_each_entry_safe(f, tmp, &fdb->offload_out, fdb_list_out)\n+\t\tbr_offload_flow_free(f);\n+\n+\tspin_unlock_bh(&offload_lock);\n+}\n+\n+static void\n+br_offload_prepare_key(struct net_bridge_port *p, struct bridge_flow_key *key,\n+\t\t       struct sk_buff *skb)\n+{\n+\tmemset(key, 0, sizeof(*key));\n+\tmemcpy(key, eth_hdr(skb), 2 * ETH_ALEN);\n+#ifdef CONFIG_BRIDGE_VLAN_FILTERING\n+\tif (!br_opt_get(p->br, BROPT_VLAN_ENABLED))\n+\t\treturn;\n+\n+\tif (!skb_vlan_tag_present(skb) || skb->vlan_proto != p->br->vlan_proto)\n+\t\treturn;\n+\n+\tkey->vlan_present = true;\n+\tkey->vlan_tag = skb_vlan_tag_get_id(skb);\n+#endif\n+}\n+\n+void br_offload_output(struct sk_buff *skb)\n+{\n+\tstruct net_bridge_port_offload *o;\n+\tstruct br_input_skb_cb *cb = (struct br_input_skb_cb *)skb->cb;\n+\tstruct net_bridge_port *p, *inp;\n+\tstruct net_device *dev;\n+\tstruct net_bridge_fdb_entry *fdb_in, *fdb_out;\n+\tstruct net_bridge_vlan_group *vg;\n+\tstruct bridge_flow_key key;\n+\tstruct bridge_flow *flow;\n+\tu16 vlan;\n+\n+\tif (!cb->offload)\n+\t\treturn;\n+\n+\trcu_read_lock();\n+\n+\tp = br_port_get_rcu(skb->dev);\n+\tif (!p)\n+\t\tgoto out;\n+\n+\to = &p->offload;\n+\tif (!o->enabled)\n+\t\tgoto out;\n+\n+\tif (atomic_read(&p->offload.rht.nelems) >= p->br->offload_cache_size)\n+\t\tgoto out;\n+\n+\tdev = dev_get_by_index_rcu(dev_net(p->br->dev), cb->input_ifindex);\n+\tif (!dev)\n+\t\tgoto out;\n+\n+\tinp = br_port_get_rcu(dev);\n+\tif (!inp)\n+\t\tgoto out;\n+\n+\tvg = nbp_vlan_group_rcu(inp);\n+\tvlan = cb->input_vlan_present ? cb->input_vlan_tag : br_get_pvid(vg);\n+\tfdb_in = br_fdb_find_rcu(p->br, eth_hdr(skb)->h_source, vlan);\n+\tif (!fdb_in)\n+\t\tgoto out;\n+\n+\tvg = nbp_vlan_group_rcu(p);\n+\tvlan = skb_vlan_tag_present(skb) ? skb_vlan_tag_get_id(skb) : br_get_pvid(vg);\n+\tfdb_out = br_fdb_find_rcu(p->br, eth_hdr(skb)->h_dest, vlan);\n+\tif (!fdb_out)\n+\t\tgoto out;\n+\n+\tbr_offload_prepare_key(p, &key, skb);\n+#ifdef CONFIG_BRIDGE_VLAN_FILTERING\n+\tkey.vlan_present = cb->input_vlan_present;\n+\tkey.vlan_tag = cb->input_vlan_tag;\n+#endif\n+\n+\tflow = kmem_cache_alloc(offload_cache, GFP_ATOMIC);\n+\tflow->port = fdb_in->dst;\n+\tmemcpy(&flow->key, &key, sizeof(key));\n+\n+#ifdef CONFIG_BRIDGE_VLAN_FILTERING\n+\tflow->vlan_out_present = skb_vlan_tag_present(skb);\n+\tflow->vlan_out = skb_vlan_tag_get(skb);\n+#endif\n+\n+\tflow->fdb_in = fdb_in;\n+\tflow->fdb_out = fdb_out;\n+\tflow->used = jiffies;\n+\n+\tspin_lock_bh(&offload_lock);\n+\tif (!o->enabled ||\n+\t    atomic_read(&p->offload.rht.nelems) >= p->br->offload_cache_size ||\n+\t    rhashtable_insert_fast(&flow->port->offload.rht, &flow->node, flow_params)) {\n+\t\tkmem_cache_free(offload_cache, flow);\n+\t\tgoto out_unlock;\n+\t}\n+\n+\thlist_add_head(&flow->fdb_list_in, &fdb_in->offload_in);\n+\thlist_add_head(&flow->fdb_list_out, &fdb_out->offload_out);\n+\n+\tif (br_offload_need_gc(p))\n+\t\tqueue_work(system_long_wq, &p->offload.gc_work);\n+\n+out_unlock:\n+\tspin_unlock_bh(&offload_lock);\n+\n+out:\n+\trcu_read_unlock();\n+}\n+\n+bool br_offload_input(struct net_bridge_port *p, struct sk_buff *skb)\n+{\n+\tstruct net_bridge_port_offload *o = &p->offload;\n+\tstruct br_input_skb_cb *cb = (struct br_input_skb_cb *)skb->cb;\n+\tstruct bridge_flow_key key;\n+\tstruct net_bridge_port *dst;\n+\tstruct bridge_flow *flow;\n+\tunsigned long now = jiffies;\n+\tbool ret = false;\n+\n+\tif (skb->len < sizeof(key))\n+\t\treturn false;\n+\n+\tif (!o->enabled)\n+\t\treturn false;\n+\n+\tif (is_multicast_ether_addr(eth_hdr(skb)->h_dest))\n+\t\treturn false;\n+\n+\tbr_offload_prepare_key(p, &key, skb);\n+\n+\trcu_read_lock();\n+\tflow = rhashtable_lookup(&o->rht, &key, flow_params);\n+\tif (!flow) {\n+\t\tcb->offload = 1;\n+#ifdef CONFIG_BRIDGE_VLAN_FILTERING\n+\t\tcb->input_vlan_present = key.vlan_present != 0;\n+\t\tcb->input_vlan_tag = key.vlan_tag;\n+\t\tcb->input_ifindex = p->dev->ifindex;\n+#endif\n+\t\tgoto out;\n+\t}\n+\n+\tif (flow->fdb_in->dst != p)\n+\t\tgoto out;\n+\n+\tdst = flow->fdb_out->dst;\n+\tif (!dst)\n+\t\tgoto out;\n+\n+\tret = true;\n+#ifdef CONFIG_BRIDGE_VLAN_FILTERING\n+\tif (!flow->vlan_out_present && key.vlan_present) {\n+\t\t__vlan_hwaccel_clear_tag(skb);\n+\t} else if (flow->vlan_out_present) {\n+\t\tif (skb_vlan_tag_present(skb) &&\n+\t\t    skb->vlan_proto != p->br->vlan_proto) {\n+\t\t\t/* Protocol-mismatch, empty out vlan_tci for new tag */\n+\t\t\tskb_push(skb, ETH_HLEN);\n+\t\t\tskb = vlan_insert_tag_set_proto(skb, skb->vlan_proto,\n+\t\t\t\t\t\t\tskb_vlan_tag_get(skb));\n+\t\t\tif (unlikely(!skb))\n+\t\t\t\tgoto out;\n+\n+\t\t\tskb_pull(skb, ETH_HLEN);\n+\t\t\tskb_reset_mac_len(skb);\n+\t\t}\n+\n+\t\t__vlan_hwaccel_put_tag(skb, p->br->vlan_proto,\n+\t\t\t\t       flow->vlan_out);\n+\t}\n+#endif\n+\n+\tskb->dev = dst->dev;\n+\tskb_push(skb, ETH_HLEN);\n+\n+\tif (skb_warn_if_lro(skb) || !is_skb_forwardable(skb->dev, skb)) {\n+\t\tkfree_skb(skb);\n+\t\tgoto out;\n+\t}\n+\n+\tif (now - flow->used >= HZ) {\n+\t\tflow->used = now;\n+\t\tbr_offload_flow_refresh_time(flow);\n+\t}\n+\n+\tskb_forward_csum(skb);\n+\tdev_queue_xmit(skb);\n+\n+out:\n+\trcu_read_unlock();\n+\treturn ret;\n+}\n+\n+static void\n+br_offload_check_gc(struct net_bridge *br)\n+{\n+\tstruct net_bridge_port *p;\n+\n+\tspin_lock_bh(&br->lock);\n+\tlist_for_each_entry(p, &br->port_list, list)\n+\t\tif (br_offload_need_gc(p))\n+\t\t\tqueue_work(system_long_wq, &p->offload.gc_work);\n+\tspin_unlock_bh(&br->lock);\n+}\n+\n+\n+int br_offload_set_cache_size(struct net_bridge *br, unsigned long val)\n+{\n+\tbr->offload_cache_size = val;\n+\tbr_offload_check_gc(br);\n+\n+\treturn 0;\n+}\n+\n+int br_offload_set_cache_reserved(struct net_bridge *br, unsigned long val)\n+{\n+\tbr->offload_cache_reserved = val;\n+\tbr_offload_check_gc(br);\n+\n+\treturn 0;\n+}\n+\n+int __init br_offload_init(void)\n+{\n+\toffload_cache = kmem_cache_create(\"bridge_offload_cache\",\n+\t\t\t\t\t  sizeof(struct bridge_flow),\n+\t\t\t\t\t  0, SLAB_HWCACHE_ALIGN, NULL);\n+\tif (!offload_cache)\n+\t\treturn -ENOMEM;\n+\n+\treturn 0;\n+}\n+\n+void br_offload_fini(void)\n+{\n+\tkmem_cache_destroy(offload_cache);\n+}\n--- a/net/bridge/br_private.h\n+++ b/net/bridge/br_private.h\n@@ -207,7 +207,13 @@ struct net_bridge_fdb_entry {\n \tunsigned long\t\t\tupdated ____cacheline_aligned_in_smp;\n \tunsigned long\t\t\tused;\n \n-\tstruct rcu_head\t\t\trcu;\n+\tunion {\n+\t\tstruct {\n+\t\t\tstruct hlist_head\t\toffload_in;\n+\t\t\tstruct hlist_head\t\toffload_out;\n+\t\t};\n+\t\tstruct rcu_head\t\t\trcu;\n+\t};\n };\n \n #define MDB_PG_FLAGS_PERMANENT\tBIT(0)\n@@ -280,6 +286,12 @@ struct net_bridge_mdb_entry {\n \tstruct rcu_head\t\t\trcu;\n };\n \n+struct net_bridge_port_offload {\n+\tstruct rhashtable\t\trht;\n+\tstruct work_struct\t\tgc_work;\n+\tbool\t\t\t\tenabled;\n+};\n+\n struct net_bridge_port {\n \tstruct net_bridge\t\t*br;\n \tstruct net_device\t\t*dev;\n@@ -337,6 +349,7 @@ struct net_bridge_port {\n \tu16\t\t\t\tbackup_redirected_cnt;\n \n \tstruct bridge_stp_xstats\tstp_xstats;\n+\tstruct net_bridge_port_offload\toffload;\n };\n \n #define kobj_to_brport(obj)\tcontainer_of(obj, struct net_bridge_port, kobj)\n@@ -475,6 +488,9 @@ struct net_bridge {\n \tstruct kobject\t\t\t*ifobj;\n \tu32\t\t\t\tauto_cnt;\n \n+\tu32\t\t\t\toffload_cache_size;\n+\tu32\t\t\t\toffload_cache_reserved;\n+\n #ifdef CONFIG_NET_SWITCHDEV\n \tint offload_fwd_mark;\n #endif\n@@ -501,6 +517,10 @@ struct br_input_skb_cb {\n #ifdef CONFIG_NETFILTER_FAMILY_BRIDGE\n \tu8 br_netfilter_broute:1;\n #endif\n+\tu8 offload:1;\n+\tu8 input_vlan_present:1;\n+\tu16 input_vlan_tag;\n+\tint input_ifindex;\n \n #ifdef CONFIG_NET_SWITCHDEV\n \tint offload_fwd_mark;\n--- /dev/null\n+++ b/net/bridge/br_private_offload.h\n@@ -0,0 +1,21 @@\n+#ifndef __BR_OFFLOAD_H\n+#define __BR_OFFLOAD_H\n+\n+bool br_offload_input(struct net_bridge_port *p, struct sk_buff *skb);\n+void br_offload_output(struct sk_buff *skb);\n+void br_offload_port_state(struct net_bridge_port *p);\n+void br_offload_fdb_update(const struct net_bridge_fdb_entry *fdb);\n+int br_offload_init(void);\n+void br_offload_fini(void);\n+int br_offload_set_cache_size(struct net_bridge *br, unsigned long val);\n+int br_offload_set_cache_reserved(struct net_bridge *br, unsigned long val);\n+\n+static inline void br_offload_skb_disable(struct sk_buff *skb)\n+{\n+\tstruct br_input_skb_cb *cb = (struct br_input_skb_cb *)skb->cb;\n+\n+\tif (cb->offload)\n+\t\tcb->offload = 0;\n+}\n+\n+#endif\n--- a/net/bridge/br_stp.c\n+++ b/net/bridge/br_stp.c\n@@ -12,6 +12,7 @@\n \n #include \"br_private.h\"\n #include \"br_private_stp.h\"\n+#include \"br_private_offload.h\"\n \n /* since time values in bpdu are in jiffies and then scaled (1/256)\n  * before sending, make sure that is at least one STP tick.\n@@ -52,6 +53,8 @@ void br_set_state(struct net_bridge_port\n \t\t\t\t(unsigned int) p->port_no, p->dev->name,\n \t\t\t\tbr_port_state_names[p->state]);\n \n+\tbr_offload_port_state(p);\n+\n \tif (p->br->stp_enabled == BR_KERNEL_STP) {\n \t\tswitch (p->state) {\n \t\tcase BR_STATE_BLOCKING:\n--- a/net/bridge/br_sysfs_br.c\n+++ b/net/bridge/br_sysfs_br.c\n@@ -18,6 +18,7 @@\n #include <linux/sched/signal.h>\n \n #include \"br_private.h\"\n+#include \"br_private_offload.h\"\n \n #define to_bridge(cd)\t((struct net_bridge *)netdev_priv(to_net_dev(cd)))\n \n@@ -842,6 +843,38 @@ static ssize_t vlan_stats_per_port_store\n static DEVICE_ATTR_RW(vlan_stats_per_port);\n #endif\n \n+static ssize_t offload_cache_size_show(struct device *d,\n+\t\t\t\t       struct device_attribute *attr,\n+\t\t\t\t       char *buf)\n+{\n+\tstruct net_bridge *br = to_bridge(d);\n+\treturn sprintf(buf, \"%u\\n\", br->offload_cache_size);\n+}\n+\n+static ssize_t offload_cache_size_store(struct device *d,\n+\t\t\t\t\tstruct device_attribute *attr,\n+\t\t\t\t\tconst char *buf, size_t len)\n+{\n+\treturn store_bridge_parm(d, buf, len, br_offload_set_cache_size);\n+}\n+static DEVICE_ATTR_RW(offload_cache_size);\n+\n+static ssize_t offload_cache_reserved_show(struct device *d,\n+\t\t\t\t       struct device_attribute *attr,\n+\t\t\t\t       char *buf)\n+{\n+\tstruct net_bridge *br = to_bridge(d);\n+\treturn sprintf(buf, \"%u\\n\", br->offload_cache_reserved);\n+}\n+\n+static ssize_t offload_cache_reserved_store(struct device *d,\n+\t\t\t\t\tstruct device_attribute *attr,\n+\t\t\t\t\tconst char *buf, size_t len)\n+{\n+\treturn store_bridge_parm(d, buf, len, br_offload_set_cache_reserved);\n+}\n+static DEVICE_ATTR_RW(offload_cache_reserved);\n+\n static struct attribute *bridge_attrs[] = {\n \t&dev_attr_forward_delay.attr,\n \t&dev_attr_hello_time.attr,\n@@ -896,6 +929,8 @@ static struct attribute *bridge_attrs[]\n \t&dev_attr_vlan_stats_enabled.attr,\n \t&dev_attr_vlan_stats_per_port.attr,\n #endif\n+\t&dev_attr_offload_cache_size.attr,\n+\t&dev_attr_offload_cache_reserved.attr,\n \tNULL\n };\n \n--- a/net/bridge/br_sysfs_if.c\n+++ b/net/bridge/br_sysfs_if.c\n@@ -234,6 +234,7 @@ BRPORT_ATTR_FLAG(broadcast_flood, BR_BCA\n BRPORT_ATTR_FLAG(neigh_suppress, BR_NEIGH_SUPPRESS);\n BRPORT_ATTR_FLAG(isolated, BR_ISOLATED);\n BRPORT_ATTR_FLAG(bpdu_filter, BR_BPDU_FILTER);\n+BRPORT_ATTR_FLAG(offload, BR_OFFLOAD);\n \n #ifdef CONFIG_BRIDGE_IGMP_SNOOPING\n static ssize_t show_multicast_router(struct net_bridge_port *p, char *buf)\n@@ -288,6 +289,7 @@ static const struct brport_attribute *br\n \t&brport_attr_isolated,\n \t&brport_attr_bpdu_filter,\n \t&brport_attr_backup_port,\n+\t&brport_attr_offload,\n \tNULL\n };\n \n--- a/net/bridge/br_vlan_tunnel.c\n+++ b/net/bridge/br_vlan_tunnel.c\n@@ -15,6 +15,7 @@\n \n #include \"br_private.h\"\n #include \"br_private_tunnel.h\"\n+#include \"br_private_offload.h\"\n \n static inline int br_vlan_tunid_cmp(struct rhashtable_compare_arg *arg,\n \t\t\t\t    const void *ptr)\n@@ -180,6 +181,7 @@ int br_handle_ingress_vlan_tunnel(struct\n \tskb_dst_drop(skb);\n \n \t__vlan_hwaccel_put_tag(skb, p->br->vlan_proto, vlan->vid);\n+\tbr_offload_skb_disable(skb);\n \n \treturn 0;\n }\n@@ -203,6 +205,7 @@ int br_handle_egress_vlan_tunnel(struct\n \tif (err)\n \t\treturn err;\n \n+\tbr_offload_skb_disable(skb);\n \ttunnel_dst = rcu_dereference(vlan->tinfo.tunnel_dst);\n \tif (tunnel_dst && dst_hold_safe(&tunnel_dst->dst))\n \t\tskb_dst_set(skb, &tunnel_dst->dst);\n"
  },
  {
    "path": "target/linux/generic/hack-5.10/645-netfilter-connmark-introduce-set-dscpmark.patch",
    "content": "From eda40b8c8c82e0f2789d6bc8bf63846dce2e8f32 Mon Sep 17 00:00:00 2001\nFrom: Kevin Darbyshire-Bryant <ldir@darbyshire-bryant.me.uk>\nDate: Sat, 23 Mar 2019 09:29:49 +0000\nSubject: [PATCH] netfilter: connmark: introduce set-dscpmark\n\nset-dscpmark is a method of storing the DSCP of an ip packet into\nconntrack mark.  In combination with a suitable tc filter action\n(act_ctinfo) DSCP values are able to be stored in the mark on egress and\nrestored on ingress across links that otherwise alter or bleach DSCP.\n\nThis is useful for qdiscs such as CAKE which are able to shape according\nto policies based on DSCP.\n\nIngress classification is traditionally a challenging task since\niptables rules haven't yet run and tc filter/eBPF programs are pre-NAT\nlookups, hence are unable to see internal IPv4 addresses as used on the\ntypical home masquerading gateway.\n\nx_tables CONNMARK set-dscpmark target solves the problem of storing the\nDSCP to the conntrack mark in a way suitable for the new act_ctinfo tc\naction to restore.\n\nThe set-dscpmark option accepts 2 parameters, a 32bit 'dscpmask' and a\n32bit 'statemask'.  The dscp mask must be 6 contiguous bits and\nrepresents the area where the DSCP will be stored in the connmark.  The\nstate mask is a minimum 1 bit length mask that must not overlap with the\ndscpmask.  It represents a flag which is set when the DSCP has been\nstored in the conntrack mark. This is useful to implement a 'one shot'\niptables based classification where the 'complicated' iptables rules are\nonly run once to classify the connection on initial (egress) packet and\nsubsequent packets are all marked/restored with the same DSCP.  A state\nmask of zero disables the setting of a status bit/s.\n\nexample syntax with a suitably modified iptables user space application:\n\niptables -A QOS_MARK_eth0 -t mangle -j CONNMARK --set-dscpmark 0xfc000000/0x01000000\n\nWould store the DSCP in the top 6 bits of the 32bit mark field, and use\nthe LSB of the top byte as the 'DSCP has been stored' marker.\n\n|----0xFC----conntrack mark----000000---|\n| Bits 31-26 | bit 25 | bit24 |~~~ Bit 0|\n| DSCP       | unused | flag  |unused   |\n|-----------------------0x01---000000---|\n      ^                   ^\n      |                   |\n      ---|             Conditional flag\n         |             set this when dscp\n|-ip diffserv-|        stored in mark\n| 6 bits      |\n|-------------|\n\nan identically configured tc action to restore looks like:\n\ntc filter show dev eth0 ingress\nfilter parent ffff: protocol all pref 10 u32 chain 0\nfilter parent ffff: protocol all pref 10 u32 chain 0 fh 800: ht divisor 1\nfilter parent ffff: protocol all pref 10 u32 chain 0 fh 800::800 order 2048 key ht 800 bkt 0 flowid 1: not_in_hw\n  match 00000000/00000000 at 0\n\taction order 1: ctinfo zone 0 pipe\n\t index 2 ref 1 bind 1 dscp 0xfc000000/0x1000000\n\n\taction order 2: mirred (Egress Redirect to device ifb4eth0) stolen\n\tindex 1 ref 1 bind 1\n\n|----0xFC----conntrack mark----000000---|\n| Bits 31-26 | bit 25 | bit24 |~~~ Bit 0|\n| DSCP       | unused | flag  |unused   |\n|-----------------------0x01---000000---|\n      |                   |\n      |                   |\n      ---|             Conditional flag\n         v             only restore if set\n|-ip diffserv-|\n| 6 bits      |\n|-------------|\n\nSigned-off-by: Kevin Darbyshire-Bryant <ldir@darbyshire-bryant.me.uk>\n---\n include/uapi/linux/netfilter/xt_connmark.h | 10 ++++\n net/netfilter/xt_connmark.c                | 55 ++++++++++++++++++----\n 2 files changed, 57 insertions(+), 8 deletions(-)\n\n--- a/include/uapi/linux/netfilter/xt_connmark.h\n+++ b/include/uapi/linux/netfilter/xt_connmark.h\n@@ -20,6 +20,11 @@ enum {\n };\n \n enum {\n+\tXT_CONNMARK_VALUE =\t(1 << 0),\n+\tXT_CONNMARK_DSCP = \t(1 << 1)\n+};\n+\n+enum {\n \tD_SHIFT_LEFT = 0,\n \tD_SHIFT_RIGHT,\n };\n@@ -34,6 +39,11 @@ struct xt_connmark_tginfo2 {\n \t__u8 shift_dir, shift_bits, mode;\n };\n \n+struct xt_connmark_tginfo3 {\n+\t__u32 ctmark, ctmask, nfmask;\n+\t__u8 shift_dir, shift_bits, mode, func;\n+};\n+\n struct xt_connmark_mtinfo1 {\n \t__u32 mark, mask;\n \t__u8 invert;\n--- a/net/netfilter/xt_connmark.c\n+++ b/net/netfilter/xt_connmark.c\n@@ -24,12 +24,13 @@ MODULE_ALIAS(\"ipt_connmark\");\n MODULE_ALIAS(\"ip6t_connmark\");\n \n static unsigned int\n-connmark_tg_shift(struct sk_buff *skb, const struct xt_connmark_tginfo2 *info)\n+connmark_tg_shift(struct sk_buff *skb, const struct xt_connmark_tginfo3 *info)\n {\n \tenum ip_conntrack_info ctinfo;\n \tu_int32_t new_targetmark;\n \tstruct nf_conn *ct;\n \tu_int32_t newmark;\n+\tu_int8_t dscp;\n \n \tct = nf_ct_get(skb, &ctinfo);\n \tif (ct == NULL)\n@@ -37,12 +38,24 @@ connmark_tg_shift(struct sk_buff *skb, c\n \n \tswitch (info->mode) {\n \tcase XT_CONNMARK_SET:\n-\t\tnewmark = (ct->mark & ~info->ctmask) ^ info->ctmark;\n-\t\tif (info->shift_dir == D_SHIFT_RIGHT)\n-\t\t\tnewmark >>= info->shift_bits;\n-\t\telse\n-\t\t\tnewmark <<= info->shift_bits;\n+\t\tnewmark = ct->mark;\n+\t\tif (info->func & XT_CONNMARK_VALUE) {\n+\t\t\tnewmark = (newmark & ~info->ctmask) ^ info->ctmark;\n+\t\t\tif (info->shift_dir == D_SHIFT_RIGHT)\n+\t\t\t\tnewmark >>= info->shift_bits;\n+\t\t\telse\n+\t\t\t\tnewmark <<= info->shift_bits;\n+\t\t} else if (info->func & XT_CONNMARK_DSCP) {\n+\t\t\tif (skb->protocol == htons(ETH_P_IP))\n+\t\t\t\tdscp = ipv4_get_dsfield(ip_hdr(skb)) >> 2;\n+\t\t\telse if (skb->protocol == htons(ETH_P_IPV6))\n+\t\t\t\tdscp = ipv6_get_dsfield(ipv6_hdr(skb)) >> 2;\n+\t\t\telse\t/* protocol doesn't have diffserv */\n+\t\t\t\tbreak;\n \n+\t\t\tnewmark = (newmark & ~info->ctmark) |\n+\t\t\t\t  (info->ctmask | (dscp << info->shift_bits));\n+\t\t}\n \t\tif (ct->mark != newmark) {\n \t\t\tct->mark = newmark;\n \t\t\tnf_conntrack_event_cache(IPCT_MARK, ct);\n@@ -81,20 +94,36 @@ static unsigned int\n connmark_tg(struct sk_buff *skb, const struct xt_action_param *par)\n {\n \tconst struct xt_connmark_tginfo1 *info = par->targinfo;\n-\tconst struct xt_connmark_tginfo2 info2 = {\n+\tconst struct xt_connmark_tginfo3 info3 = {\n \t\t.ctmark\t= info->ctmark,\n \t\t.ctmask\t= info->ctmask,\n \t\t.nfmask\t= info->nfmask,\n \t\t.mode\t= info->mode,\n+\t\t.func\t= XT_CONNMARK_VALUE\n \t};\n \n-\treturn connmark_tg_shift(skb, &info2);\n+\treturn connmark_tg_shift(skb, &info3);\n }\n \n static unsigned int\n connmark_tg_v2(struct sk_buff *skb, const struct xt_action_param *par)\n {\n \tconst struct xt_connmark_tginfo2 *info = par->targinfo;\n+\tconst struct xt_connmark_tginfo3 info3 = {\n+\t\t.ctmark\t= info->ctmark,\n+\t\t.ctmask\t= info->ctmask,\n+\t\t.nfmask\t= info->nfmask,\n+\t\t.mode\t= info->mode,\n+\t\t.func\t= XT_CONNMARK_VALUE\n+\t};\n+\n+\treturn connmark_tg_shift(skb, &info3);\n+}\n+\n+static unsigned int\n+connmark_tg_v3(struct sk_buff *skb, const struct xt_action_param *par)\n+{\n+\tconst struct xt_connmark_tginfo3 *info = par->targinfo;\n \n \treturn connmark_tg_shift(skb, info);\n }\n@@ -165,6 +194,16 @@ static struct xt_target connmark_tg_reg[\n \t\t.targetsize     = sizeof(struct xt_connmark_tginfo2),\n \t\t.destroy        = connmark_tg_destroy,\n \t\t.me             = THIS_MODULE,\n+\t},\n+\t{\n+\t\t.name           = \"CONNMARK\",\n+\t\t.revision       = 3,\n+\t\t.family         = NFPROTO_UNSPEC,\n+\t\t.checkentry     = connmark_tg_check,\n+\t\t.target         = connmark_tg_v3,\n+\t\t.targetsize     = sizeof(struct xt_connmark_tginfo3),\n+\t\t.destroy        = connmark_tg_destroy,\n+\t\t.me             = THIS_MODULE,\n \t}\n };\n \n"
  },
  {
    "path": "target/linux/generic/hack-5.10/650-netfilter-add-xt_FLOWOFFLOAD-target.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nDate: Tue, 20 Feb 2018 15:56:02 +0100\nSubject: [PATCH] netfilter: add xt_FLOWOFFLOAD target\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n create mode 100644 net/netfilter/xt_OFFLOAD.c\n\n--- a/net/ipv4/netfilter/Kconfig\n+++ b/net/ipv4/netfilter/Kconfig\n@@ -56,8 +56,6 @@ config NF_TABLES_ARP\n \thelp\n \t  This option enables the ARP support for nf_tables.\n \n-endif # NF_TABLES\n-\n config NF_FLOW_TABLE_IPV4\n \ttristate \"Netfilter flow table IPv4 module\"\n \tdepends on NF_FLOW_TABLE\n@@ -66,6 +64,8 @@ config NF_FLOW_TABLE_IPV4\n \n \t  To compile it as a module, choose M here.\n \n+endif # NF_TABLES\n+\n config NF_DUP_IPV4\n \ttristate \"Netfilter IPv4 packet duplication to alternate destination\"\n \tdepends on !NF_CONNTRACK || NF_CONNTRACK\n--- a/net/ipv6/netfilter/Kconfig\n+++ b/net/ipv6/netfilter/Kconfig\n@@ -45,7 +45,6 @@ config NFT_FIB_IPV6\n \t  multicast or blackhole.\n \n endif # NF_TABLES_IPV6\n-endif # NF_TABLES\n \n config NF_FLOW_TABLE_IPV6\n \ttristate \"Netfilter flow table IPv6 module\"\n@@ -55,6 +54,8 @@ config NF_FLOW_TABLE_IPV6\n \n \t  To compile it as a module, choose M here.\n \n+endif # NF_TABLES\n+\n config NF_DUP_IPV6\n \ttristate \"Netfilter IPv6 packet duplication to alternate destination\"\n \tdepends on !NF_CONNTRACK || NF_CONNTRACK\n--- a/net/netfilter/Kconfig\n+++ b/net/netfilter/Kconfig\n@@ -683,8 +683,6 @@ config NFT_FIB_NETDEV\n \n endif # NF_TABLES_NETDEV\n \n-endif # NF_TABLES\n-\n config NF_FLOW_TABLE_INET\n \ttristate \"Netfilter flow table mixed IPv4/IPv6 module\"\n \tdepends on NF_FLOW_TABLE\n@@ -693,11 +691,12 @@ config NF_FLOW_TABLE_INET\n \n \t  To compile it as a module, choose M here.\n \n+endif # NF_TABLES\n+\n config NF_FLOW_TABLE\n \ttristate \"Netfilter flow table module\"\n \tdepends on NETFILTER_INGRESS\n \tdepends on NF_CONNTRACK\n-\tdepends on NF_TABLES\n \thelp\n \t  This option adds the flow table core infrastructure.\n \n@@ -977,6 +976,15 @@ config NETFILTER_XT_TARGET_NOTRACK\n \tdepends on NETFILTER_ADVANCED\n \tselect NETFILTER_XT_TARGET_CT\n \n+config NETFILTER_XT_TARGET_FLOWOFFLOAD\n+\ttristate '\"FLOWOFFLOAD\" target support'\n+\tdepends on NF_FLOW_TABLE\n+\tdepends on NETFILTER_INGRESS\n+\thelp\n+\t  This option adds a `FLOWOFFLOAD' target, which uses the nf_flow_offload\n+\t  module to speed up processing of packets by bypassing the usual\n+\t  netfilter chains\n+\n config NETFILTER_XT_TARGET_RATEEST\n \ttristate '\"RATEEST\" target support'\n \tdepends on NETFILTER_ADVANCED\n--- a/net/netfilter/Makefile\n+++ b/net/netfilter/Makefile\n@@ -145,6 +145,7 @@ obj-$(CONFIG_NETFILTER_XT_TARGET_CLASSIF\n obj-$(CONFIG_NETFILTER_XT_TARGET_CONNSECMARK) += xt_CONNSECMARK.o\n obj-$(CONFIG_NETFILTER_XT_TARGET_CT) += xt_CT.o\n obj-$(CONFIG_NETFILTER_XT_TARGET_DSCP) += xt_DSCP.o\n+obj-$(CONFIG_NETFILTER_XT_TARGET_FLOWOFFLOAD) += xt_FLOWOFFLOAD.o\n obj-$(CONFIG_NETFILTER_XT_TARGET_HL) += xt_HL.o\n obj-$(CONFIG_NETFILTER_XT_TARGET_HMARK) += xt_HMARK.o\n obj-$(CONFIG_NETFILTER_XT_TARGET_LED) += xt_LED.o\n--- /dev/null\n+++ b/net/netfilter/xt_FLOWOFFLOAD.c\n@@ -0,0 +1,712 @@\n+/*\n+ * Copyright (C) 2018-2021 Felix Fietkau <nbd@nbd.name>\n+ *\n+ * This program is free software; you can redistribute it and/or modify\n+ * it under the terms of the GNU General Public License version 2 as\n+ * published by the Free Software Foundation.\n+ */\n+#include <linux/module.h>\n+#include <linux/init.h>\n+#include <linux/netfilter.h>\n+#include <linux/netfilter/xt_FLOWOFFLOAD.h>\n+#include <linux/if_vlan.h>\n+#include <linux/if_pppox.h>\n+#include <linux/ppp_defs.h>\n+#include <net/ip.h>\n+#include <net/netfilter/nf_conntrack.h>\n+#include <net/netfilter/nf_conntrack_extend.h>\n+#include <net/netfilter/nf_conntrack_helper.h>\n+#include <net/netfilter/nf_flow_table.h>\n+\n+struct xt_flowoffload_hook {\n+\tstruct hlist_node list;\n+\tstruct nf_hook_ops ops;\n+\tstruct net *net;\n+\tbool registered;\n+\tbool used;\n+};\n+\n+struct xt_flowoffload_table {\n+\tstruct nf_flowtable ft;\n+\tstruct hlist_head hooks;\n+\tstruct delayed_work work;\n+};\n+\n+struct nf_forward_info {\n+\tconst struct net_device *indev;\n+\tconst struct net_device *outdev;\n+\tconst struct net_device *hw_outdev;\n+\tstruct id {\n+\t\t__u16\tid;\n+\t\t__be16\tproto;\n+\t} encap[NF_FLOW_TABLE_ENCAP_MAX];\n+\tu8 num_encaps;\n+\tu8 ingress_vlans;\n+\tu8 h_source[ETH_ALEN];\n+\tu8 h_dest[ETH_ALEN];\n+\tenum flow_offload_xmit_type xmit_type;\n+};\n+\n+static DEFINE_SPINLOCK(hooks_lock);\n+\n+struct xt_flowoffload_table flowtable[2];\n+\n+static inline __be16 nf_flow_pppoe_proto(const struct sk_buff *skb)\n+{\n+\t__be16 proto;\n+\n+\tproto = *((__be16 *)(skb_mac_header(skb) + ETH_HLEN +\n+\t\t\t     sizeof(struct pppoe_hdr)));\n+\tswitch (proto) {\n+\tcase htons(PPP_IP):\n+\t\treturn htons(ETH_P_IP);\n+\tcase htons(PPP_IPV6):\n+\t\treturn htons(ETH_P_IPV6);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static unsigned int\n+xt_flowoffload_net_hook(void *priv, struct sk_buff *skb,\n+\t\t\tconst struct nf_hook_state *state)\n+{\n+\tstruct vlan_ethhdr *veth;\n+\t__be16 proto;\n+\n+\tswitch (skb->protocol) {\n+\tcase htons(ETH_P_8021Q):\n+\t\tveth = (struct vlan_ethhdr *)skb_mac_header(skb);\n+\t\tproto = veth->h_vlan_encapsulated_proto;\n+\t\tbreak;\n+\tcase htons(ETH_P_PPP_SES):\n+\t\tproto = nf_flow_pppoe_proto(skb);\n+\t\tbreak;\n+\tdefault:\n+\t\tproto = skb->protocol;\n+\t\tbreak;\n+\t}\n+\n+\tswitch (proto) {\n+\tcase htons(ETH_P_IP):\n+\t\treturn nf_flow_offload_ip_hook(priv, skb, state);\n+\tcase htons(ETH_P_IPV6):\n+\t\treturn nf_flow_offload_ipv6_hook(priv, skb, state);\n+\t}\n+\n+\treturn NF_ACCEPT;\n+}\n+\n+static int\n+xt_flowoffload_create_hook(struct xt_flowoffload_table *table,\n+\t\t\t   struct net_device *dev)\n+{\n+\tstruct xt_flowoffload_hook *hook;\n+\tstruct nf_hook_ops *ops;\n+\n+\thook = kzalloc(sizeof(*hook), GFP_ATOMIC);\n+\tif (!hook)\n+\t\treturn -ENOMEM;\n+\n+\tops = &hook->ops;\n+\tops->pf = NFPROTO_NETDEV;\n+\tops->hooknum = NF_NETDEV_INGRESS;\n+\tops->priority = 10;\n+\tops->priv = &table->ft;\n+\tops->hook = xt_flowoffload_net_hook;\n+\tops->dev = dev;\n+\n+\thlist_add_head(&hook->list, &table->hooks);\n+\tmod_delayed_work(system_power_efficient_wq, &table->work, 0);\n+\n+\treturn 0;\n+}\n+\n+static struct xt_flowoffload_hook *\n+flow_offload_lookup_hook(struct xt_flowoffload_table *table,\n+\t\t\t struct net_device *dev)\n+{\n+\tstruct xt_flowoffload_hook *hook;\n+\n+\thlist_for_each_entry(hook, &table->hooks, list) {\n+\t\tif (hook->ops.dev == dev)\n+\t\t\treturn hook;\n+\t}\n+\n+\treturn NULL;\n+}\n+\n+static void\n+xt_flowoffload_check_device(struct xt_flowoffload_table *table,\n+\t\t\t    struct net_device *dev)\n+{\n+\tstruct xt_flowoffload_hook *hook;\n+\n+\tif (!dev)\n+\t\treturn;\n+\n+\tspin_lock_bh(&hooks_lock);\n+\thook = flow_offload_lookup_hook(table, dev);\n+\tif (hook)\n+\t\thook->used = true;\n+\telse\n+\t\txt_flowoffload_create_hook(table, dev);\n+\tspin_unlock_bh(&hooks_lock);\n+}\n+\n+static void\n+xt_flowoffload_register_hooks(struct xt_flowoffload_table *table)\n+{\n+\tstruct xt_flowoffload_hook *hook;\n+\n+restart:\n+\thlist_for_each_entry(hook, &table->hooks, list) {\n+\t\tif (hook->registered)\n+\t\t\tcontinue;\n+\n+\t\thook->registered = true;\n+\t\thook->net = dev_net(hook->ops.dev);\n+\t\tspin_unlock_bh(&hooks_lock);\n+\t\tnf_register_net_hook(hook->net, &hook->ops);\n+\t\tif (table->ft.flags & NF_FLOWTABLE_HW_OFFLOAD)\n+\t\t\ttable->ft.type->setup(&table->ft, hook->ops.dev,\n+\t\t\t\t\t      FLOW_BLOCK_BIND);\n+\t\tspin_lock_bh(&hooks_lock);\n+\t\tgoto restart;\n+\t}\n+\n+}\n+\n+static bool\n+xt_flowoffload_cleanup_hooks(struct xt_flowoffload_table *table)\n+{\n+\tstruct xt_flowoffload_hook *hook;\n+\tbool active = false;\n+\n+restart:\n+\tspin_lock_bh(&hooks_lock);\n+\thlist_for_each_entry(hook, &table->hooks, list) {\n+\t\tif (hook->used || !hook->registered) {\n+\t\t\tactive = true;\n+\t\t\tcontinue;\n+\t\t}\n+\n+\t\thlist_del(&hook->list);\n+\t\tspin_unlock_bh(&hooks_lock);\n+\t\tif (table->ft.flags & NF_FLOWTABLE_HW_OFFLOAD)\n+\t\t\ttable->ft.type->setup(&table->ft, hook->ops.dev,\n+\t\t\t\t\t      FLOW_BLOCK_UNBIND);\n+\t\tnf_unregister_net_hook(hook->net, &hook->ops);\n+\t\tkfree(hook);\n+\t\tgoto restart;\n+\t}\n+\tspin_unlock_bh(&hooks_lock);\n+\n+\treturn active;\n+}\n+\n+static void\n+xt_flowoffload_check_hook(struct flow_offload *flow, void *data)\n+{\n+\tstruct xt_flowoffload_table *table = data;\n+\tstruct flow_offload_tuple *tuple0 = &flow->tuplehash[0].tuple;\n+\tstruct flow_offload_tuple *tuple1 = &flow->tuplehash[1].tuple;\n+\tstruct xt_flowoffload_hook *hook;\n+\n+\tspin_lock_bh(&hooks_lock);\n+\thlist_for_each_entry(hook, &table->hooks, list) {\n+\t\tif (hook->ops.dev->ifindex != tuple0->iifidx &&\n+\t\t    hook->ops.dev->ifindex != tuple1->iifidx)\n+\t\t\tcontinue;\n+\n+\t\thook->used = true;\n+\t}\n+\tspin_unlock_bh(&hooks_lock);\n+}\n+\n+static void\n+xt_flowoffload_hook_work(struct work_struct *work)\n+{\n+\tstruct xt_flowoffload_table *table;\n+\tstruct xt_flowoffload_hook *hook;\n+\tint err;\n+\n+\ttable = container_of(work, struct xt_flowoffload_table, work.work);\n+\n+\tspin_lock_bh(&hooks_lock);\n+\txt_flowoffload_register_hooks(table);\n+\thlist_for_each_entry(hook, &table->hooks, list)\n+\t\thook->used = false;\n+\tspin_unlock_bh(&hooks_lock);\n+\n+\terr = nf_flow_table_iterate(&table->ft, xt_flowoffload_check_hook,\n+\t\t\t\t    table);\n+\tif (err && err != -EAGAIN)\n+\t\tgoto out;\n+\n+\tif (!xt_flowoffload_cleanup_hooks(table))\n+\t\treturn;\n+\n+out:\n+\tqueue_delayed_work(system_power_efficient_wq, &table->work, HZ);\n+}\n+\n+static bool\n+xt_flowoffload_skip(struct sk_buff *skb, int family)\n+{\n+\tif (skb_sec_path(skb))\n+\t\treturn true;\n+\n+\tif (family == NFPROTO_IPV4) {\n+\t\tconst struct ip_options *opt = &(IPCB(skb)->opt);\n+\n+\t\tif (unlikely(opt->optlen))\n+\t\t\treturn true;\n+\t}\n+\n+\treturn false;\n+}\n+\n+static enum flow_offload_xmit_type nf_xmit_type(struct dst_entry *dst)\n+{\n+\tif (dst_xfrm(dst))\n+\t\treturn FLOW_OFFLOAD_XMIT_XFRM;\n+\n+\treturn FLOW_OFFLOAD_XMIT_NEIGH;\n+}\n+\n+static void nf_default_forward_path(struct nf_flow_route *route,\n+\t\t\t\t    struct dst_entry *dst_cache,\n+\t\t\t\t    enum ip_conntrack_dir dir,\n+\t\t\t\t    struct net_device **dev)\n+{\n+\tdev[!dir] = dst_cache->dev;\n+\troute->tuple[!dir].in.ifindex\t= dst_cache->dev->ifindex;\n+\troute->tuple[dir].dst\t\t= dst_cache;\n+\troute->tuple[dir].xmit_type\t= nf_xmit_type(dst_cache);\n+}\n+\n+static bool nf_is_valid_ether_device(const struct net_device *dev)\n+{\n+\tif (!dev || (dev->flags & IFF_LOOPBACK) || dev->type != ARPHRD_ETHER ||\n+\t    dev->addr_len != ETH_ALEN || !is_valid_ether_addr(dev->dev_addr))\n+\t\treturn false;\n+\n+\treturn true;\n+}\n+\n+static void nf_dev_path_info(const struct net_device_path_stack *stack,\n+\t\t\t     struct nf_forward_info *info,\n+\t\t\t     unsigned char *ha)\n+{\n+\tconst struct net_device_path *path;\n+\tint i;\n+\n+\tmemcpy(info->h_dest, ha, ETH_ALEN);\n+\n+\tfor (i = 0; i < stack->num_paths; i++) {\n+\t\tpath = &stack->path[i];\n+\t\tswitch (path->type) {\n+\t\tcase DEV_PATH_ETHERNET:\n+\t\tcase DEV_PATH_DSA:\n+\t\tcase DEV_PATH_VLAN:\n+\t\tcase DEV_PATH_PPPOE:\n+\t\t\tinfo->indev = path->dev;\n+\t\t\tif (is_zero_ether_addr(info->h_source))\n+\t\t\t\tmemcpy(info->h_source, path->dev->dev_addr, ETH_ALEN);\n+\n+\t\t\tif (path->type == DEV_PATH_ETHERNET)\n+\t\t\t\tbreak;\n+\t\t\tif (path->type == DEV_PATH_DSA) {\n+\t\t\t\ti = stack->num_paths;\n+\t\t\t\tbreak;\n+\t\t\t}\n+\n+\t\t\t/* DEV_PATH_VLAN and DEV_PATH_PPPOE */\n+\t\t\tif (info->num_encaps >= NF_FLOW_TABLE_ENCAP_MAX) {\n+\t\t\t\tinfo->indev = NULL;\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t\tif (!info->outdev)\n+\t\t\t\tinfo->outdev = path->dev;\n+\t\t\tinfo->encap[info->num_encaps].id = path->encap.id;\n+\t\t\tinfo->encap[info->num_encaps].proto = path->encap.proto;\n+\t\t\tinfo->num_encaps++;\n+\t\t\tif (path->type == DEV_PATH_PPPOE)\n+\t\t\t\tmemcpy(info->h_dest, path->encap.h_dest, ETH_ALEN);\n+\t\t\tbreak;\n+\t\tcase DEV_PATH_BRIDGE:\n+\t\t\tif (is_zero_ether_addr(info->h_source))\n+\t\t\t\tmemcpy(info->h_source, path->dev->dev_addr, ETH_ALEN);\n+\n+\t\t\tswitch (path->bridge.vlan_mode) {\n+\t\t\tcase DEV_PATH_BR_VLAN_UNTAG_HW:\n+\t\t\t\tinfo->ingress_vlans |= BIT(info->num_encaps - 1);\n+\t\t\t\tbreak;\n+\t\t\tcase DEV_PATH_BR_VLAN_TAG:\n+\t\t\t\tinfo->encap[info->num_encaps].id = path->bridge.vlan_id;\n+\t\t\t\tinfo->encap[info->num_encaps].proto = path->bridge.vlan_proto;\n+\t\t\t\tinfo->num_encaps++;\n+\t\t\t\tbreak;\n+\t\t\tcase DEV_PATH_BR_VLAN_UNTAG:\n+\t\t\t\tinfo->num_encaps--;\n+\t\t\t\tbreak;\n+\t\t\tcase DEV_PATH_BR_VLAN_KEEP:\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tinfo->indev = NULL;\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\tif (!info->outdev)\n+\t\tinfo->outdev = info->indev;\n+\n+\tinfo->hw_outdev = info->indev;\n+\n+\tif (nf_is_valid_ether_device(info->indev))\n+\t\tinfo->xmit_type = FLOW_OFFLOAD_XMIT_DIRECT;\n+}\n+\n+static int nf_dev_fill_forward_path(const struct nf_flow_route *route,\n+\t\t\t\t     const struct dst_entry *dst_cache,\n+\t\t\t\t     const struct nf_conn *ct,\n+\t\t\t\t     enum ip_conntrack_dir dir, u8 *ha,\n+\t\t\t\t     struct net_device_path_stack *stack)\n+{\n+\tconst void *daddr = &ct->tuplehash[!dir].tuple.src.u3;\n+\tstruct net_device *dev = dst_cache->dev;\n+\tstruct neighbour *n;\n+\tu8 nud_state;\n+\n+\tif (!nf_is_valid_ether_device(dev))\n+\t\tgoto out;\n+\n+\tn = dst_neigh_lookup(dst_cache, daddr);\n+\tif (!n)\n+\t\treturn -1;\n+\n+\tread_lock_bh(&n->lock);\n+\tnud_state = n->nud_state;\n+\tether_addr_copy(ha, n->ha);\n+\tread_unlock_bh(&n->lock);\n+\tneigh_release(n);\n+\n+\tif (!(nud_state & NUD_VALID))\n+\t\treturn -1;\n+\n+out:\n+\treturn dev_fill_forward_path(dev, ha, stack);\n+}\n+\n+static void nf_dev_forward_path(struct nf_flow_route *route,\n+\t\t\t\tconst struct nf_conn *ct,\n+\t\t\t\tenum ip_conntrack_dir dir,\n+\t\t\t\tstruct net_device **devs)\n+{\n+\tconst struct dst_entry *dst = route->tuple[dir].dst;\n+\tstruct net_device_path_stack stack;\n+\tstruct nf_forward_info info = {};\n+\tunsigned char ha[ETH_ALEN];\n+\tint i;\n+\n+\tif (nf_dev_fill_forward_path(route, dst, ct, dir, ha, &stack) >= 0)\n+\t\tnf_dev_path_info(&stack, &info, ha);\n+\n+\tdevs[!dir] = (struct net_device *)info.indev;\n+\tif (!info.indev)\n+\t\treturn;\n+\n+\troute->tuple[!dir].in.ifindex = info.indev->ifindex;\n+\tfor (i = 0; i < info.num_encaps; i++) {\n+\t\troute->tuple[!dir].in.encap[i].id = info.encap[i].id;\n+\t\troute->tuple[!dir].in.encap[i].proto = info.encap[i].proto;\n+\t}\n+\troute->tuple[!dir].in.num_encaps = info.num_encaps;\n+\troute->tuple[!dir].in.ingress_vlans = info.ingress_vlans;\n+\n+\tif (info.xmit_type == FLOW_OFFLOAD_XMIT_DIRECT) {\n+\t\tmemcpy(route->tuple[dir].out.h_source, info.h_source, ETH_ALEN);\n+\t\tmemcpy(route->tuple[dir].out.h_dest, info.h_dest, ETH_ALEN);\n+\t\troute->tuple[dir].out.ifindex = info.outdev->ifindex;\n+\t\troute->tuple[dir].out.hw_ifindex = info.hw_outdev->ifindex;\n+\t\troute->tuple[dir].xmit_type = info.xmit_type;\n+\t}\n+}\n+\n+static int\n+xt_flowoffload_route(struct sk_buff *skb, const struct nf_conn *ct,\n+\t\t     const struct xt_action_param *par,\n+\t\t     struct nf_flow_route *route, enum ip_conntrack_dir dir,\n+\t\t     struct net_device **devs)\n+{\n+\tstruct dst_entry *this_dst = skb_dst(skb);\n+\tstruct dst_entry *other_dst = NULL;\n+\tstruct flowi fl;\n+\n+\tmemset(&fl, 0, sizeof(fl));\n+\tswitch (xt_family(par)) {\n+\tcase NFPROTO_IPV4:\n+\t\tfl.u.ip4.daddr = ct->tuplehash[dir].tuple.src.u3.ip;\n+\t\tfl.u.ip4.flowi4_oif = xt_in(par)->ifindex;\n+\t\tbreak;\n+\tcase NFPROTO_IPV6:\n+\t\tfl.u.ip6.saddr = ct->tuplehash[!dir].tuple.dst.u3.in6;\n+\t\tfl.u.ip6.daddr = ct->tuplehash[dir].tuple.src.u3.in6;\n+\t\tfl.u.ip6.flowi6_oif = xt_in(par)->ifindex;\n+\t\tbreak;\n+\t}\n+\n+\tnf_route(xt_net(par), &other_dst, &fl, false, xt_family(par));\n+\tif (!other_dst)\n+\t\treturn -ENOENT;\n+\n+\tnf_default_forward_path(route, this_dst, dir, devs);\n+\tnf_default_forward_path(route, other_dst, !dir, devs);\n+\n+\tif (route->tuple[dir].xmit_type\t== FLOW_OFFLOAD_XMIT_NEIGH &&\n+\t    route->tuple[!dir].xmit_type == FLOW_OFFLOAD_XMIT_NEIGH) {\n+\t\tnf_dev_forward_path(route, ct, dir, devs);\n+\t\tnf_dev_forward_path(route, ct, !dir, devs);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static unsigned int\n+flowoffload_tg(struct sk_buff *skb, const struct xt_action_param *par)\n+{\n+\tstruct xt_flowoffload_table *table;\n+\tconst struct xt_flowoffload_target_info *info = par->targinfo;\n+\tstruct tcphdr _tcph, *tcph = NULL;\n+\tenum ip_conntrack_info ctinfo;\n+\tenum ip_conntrack_dir dir;\n+\tstruct nf_flow_route route = {};\n+\tstruct flow_offload *flow = NULL;\n+\tstruct net_device *devs[2] = {};\n+\tstruct nf_conn *ct;\n+\tstruct net *net;\n+\n+\tif (xt_flowoffload_skip(skb, xt_family(par)))\n+\t\treturn XT_CONTINUE;\n+\n+\tct = nf_ct_get(skb, &ctinfo);\n+\tif (ct == NULL)\n+\t\treturn XT_CONTINUE;\n+\n+\tswitch (ct->tuplehash[IP_CT_DIR_ORIGINAL].tuple.dst.protonum) {\n+\tcase IPPROTO_TCP:\n+\t\tif (ct->proto.tcp.state != TCP_CONNTRACK_ESTABLISHED)\n+\t\t\treturn XT_CONTINUE;\n+\n+\t\ttcph = skb_header_pointer(skb, par->thoff,\n+\t\t\t\t\t  sizeof(_tcph), &_tcph);\n+\t\tif (unlikely(!tcph || tcph->fin || tcph->rst))\n+\t\t\treturn XT_CONTINUE;\n+\t\tbreak;\n+\tcase IPPROTO_UDP:\n+\t\tbreak;\n+\tdefault:\n+\t\treturn XT_CONTINUE;\n+\t}\n+\n+\tif (nf_ct_ext_exist(ct, NF_CT_EXT_HELPER) ||\n+\t    ct->status & (IPS_SEQ_ADJUST | IPS_NAT_CLASH))\n+\t\treturn XT_CONTINUE;\n+\n+\tif (!nf_ct_is_confirmed(ct))\n+\t\treturn XT_CONTINUE;\n+\n+\tdevs[dir] = xt_out(par);\n+\tdevs[!dir] = xt_in(par);\n+\n+\tif (!devs[dir] || !devs[!dir])\n+\t\treturn XT_CONTINUE;\n+\n+\tif (test_and_set_bit(IPS_OFFLOAD_BIT, &ct->status))\n+\t\treturn XT_CONTINUE;\n+\n+\tdir = CTINFO2DIR(ctinfo);\n+\n+\tif (xt_flowoffload_route(skb, ct, par, &route, dir, devs) < 0)\n+\t\tgoto err_flow_route;\n+\n+\tflow = flow_offload_alloc(ct);\n+\tif (!flow)\n+\t\tgoto err_flow_alloc;\n+\n+\tif (flow_offload_route_init(flow, &route) < 0)\n+\t\tgoto err_flow_add;\n+\n+\tif (tcph) {\n+\t\tct->proto.tcp.seen[0].flags |= IP_CT_TCP_FLAG_BE_LIBERAL;\n+\t\tct->proto.tcp.seen[1].flags |= IP_CT_TCP_FLAG_BE_LIBERAL;\n+\t}\n+\n+\ttable = &flowtable[!!(info->flags & XT_FLOWOFFLOAD_HW)];\n+\n+\tnet = read_pnet(&table->ft.net);\n+\tif (!net)\n+\t\twrite_pnet(&table->ft.net, xt_net(par));\n+\n+\tif (flow_offload_add(&table->ft, flow) < 0)\n+\t\tgoto err_flow_add;\n+\n+\txt_flowoffload_check_device(table, devs[0]);\n+\txt_flowoffload_check_device(table, devs[1]);\n+\n+\tdst_release(route.tuple[!dir].dst);\n+\n+\treturn XT_CONTINUE;\n+\n+err_flow_add:\n+\tflow_offload_free(flow);\n+err_flow_alloc:\n+\tdst_release(route.tuple[!dir].dst);\n+err_flow_route:\n+\tclear_bit(IPS_OFFLOAD_BIT, &ct->status);\n+\n+\treturn XT_CONTINUE;\n+}\n+\n+static int flowoffload_chk(const struct xt_tgchk_param *par)\n+{\n+\tstruct xt_flowoffload_target_info *info = par->targinfo;\n+\n+\tif (info->flags & ~XT_FLOWOFFLOAD_MASK)\n+\t\treturn -EINVAL;\n+\n+\treturn 0;\n+}\n+\n+static struct xt_target offload_tg_reg __read_mostly = {\n+\t.family\t\t= NFPROTO_UNSPEC,\n+\t.name\t\t= \"FLOWOFFLOAD\",\n+\t.revision\t= 0,\n+\t.targetsize\t= sizeof(struct xt_flowoffload_target_info),\n+\t.usersize\t= sizeof(struct xt_flowoffload_target_info),\n+\t.checkentry\t= flowoffload_chk,\n+\t.target\t\t= flowoffload_tg,\n+\t.me\t\t= THIS_MODULE,\n+};\n+\n+static int flow_offload_netdev_event(struct notifier_block *this,\n+\t\t\t\t     unsigned long event, void *ptr)\n+{\n+\tstruct xt_flowoffload_hook *hook0, *hook1;\n+\tstruct net_device *dev = netdev_notifier_info_to_dev(ptr);\n+\n+\tif (event != NETDEV_UNREGISTER)\n+\t\treturn NOTIFY_DONE;\n+\n+\tspin_lock_bh(&hooks_lock);\n+\thook0 = flow_offload_lookup_hook(&flowtable[0], dev);\n+\tif (hook0)\n+\t\thlist_del(&hook0->list);\n+\n+\thook1 = flow_offload_lookup_hook(&flowtable[1], dev);\n+\tif (hook1)\n+\t\thlist_del(&hook1->list);\n+\tspin_unlock_bh(&hooks_lock);\n+\n+\tif (hook0) {\n+\t\tnf_unregister_net_hook(hook0->net, &hook0->ops);\n+\t\tkfree(hook0);\n+\t}\n+\n+\tif (hook1) {\n+\t\tnf_unregister_net_hook(hook1->net, &hook1->ops);\n+\t\tkfree(hook1);\n+\t}\n+\n+\tnf_flow_table_cleanup(dev);\n+\n+\treturn NOTIFY_DONE;\n+}\n+\n+static struct notifier_block flow_offload_netdev_notifier = {\n+\t.notifier_call\t= flow_offload_netdev_event,\n+};\n+\n+static int nf_flow_rule_route_inet(struct net *net,\n+\t\t\t\t   const struct flow_offload *flow,\n+\t\t\t\t   enum flow_offload_tuple_dir dir,\n+\t\t\t\t   struct nf_flow_rule *flow_rule)\n+{\n+\tconst struct flow_offload_tuple *flow_tuple = &flow->tuplehash[dir].tuple;\n+\tint err;\n+\n+\tswitch (flow_tuple->l3proto) {\n+\tcase NFPROTO_IPV4:\n+\t\terr = nf_flow_rule_route_ipv4(net, flow, dir, flow_rule);\n+\t\tbreak;\n+\tcase NFPROTO_IPV6:\n+\t\terr = nf_flow_rule_route_ipv6(net, flow, dir, flow_rule);\n+\t\tbreak;\n+\tdefault:\n+\t\terr = -1;\n+\t\tbreak;\n+\t}\n+\n+\treturn err;\n+}\n+\n+static struct nf_flowtable_type flowtable_inet = {\n+\t.family\t\t= NFPROTO_INET,\n+\t.init\t\t= nf_flow_table_init,\n+\t.setup\t\t= nf_flow_table_offload_setup,\n+\t.action\t\t= nf_flow_rule_route_inet,\n+\t.free\t\t= nf_flow_table_free,\n+\t.hook\t\t= xt_flowoffload_net_hook,\n+\t.owner\t\t= THIS_MODULE,\n+};\n+\n+static int init_flowtable(struct xt_flowoffload_table *tbl)\n+{\n+\tINIT_DELAYED_WORK(&tbl->work, xt_flowoffload_hook_work);\n+\ttbl->ft.type = &flowtable_inet;\n+\n+\treturn nf_flow_table_init(&tbl->ft);\n+}\n+\n+static int __init xt_flowoffload_tg_init(void)\n+{\n+\tint ret;\n+\n+\tregister_netdevice_notifier(&flow_offload_netdev_notifier);\n+\n+\tret = init_flowtable(&flowtable[0]);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = init_flowtable(&flowtable[1]);\n+\tif (ret)\n+\t\tgoto cleanup;\n+\n+\tflowtable[1].ft.flags = NF_FLOWTABLE_HW_OFFLOAD;\n+\n+\tret = xt_register_target(&offload_tg_reg);\n+\tif (ret)\n+\t\tgoto cleanup2;\n+\n+\treturn 0;\n+\n+cleanup2:\n+\tnf_flow_table_free(&flowtable[1].ft);\n+cleanup:\n+\tnf_flow_table_free(&flowtable[0].ft);\n+\treturn ret;\n+}\n+\n+static void __exit xt_flowoffload_tg_exit(void)\n+{\n+\txt_unregister_target(&offload_tg_reg);\n+\tunregister_netdevice_notifier(&flow_offload_netdev_notifier);\n+\tnf_flow_table_free(&flowtable[0].ft);\n+\tnf_flow_table_free(&flowtable[1].ft);\n+}\n+\n+MODULE_LICENSE(\"GPL\");\n+module_init(xt_flowoffload_tg_init);\n+module_exit(xt_flowoffload_tg_exit);\n--- a/net/netfilter/nf_flow_table_core.c\n+++ b/net/netfilter/nf_flow_table_core.c\n@@ -7,7 +7,6 @@\n #include <linux/netdevice.h>\n #include <net/ip.h>\n #include <net/ip6_route.h>\n-#include <net/netfilter/nf_tables.h>\n #include <net/netfilter/nf_flow_table.h>\n #include <net/netfilter/nf_conntrack.h>\n #include <net/netfilter/nf_conntrack_core.h>\n@@ -401,8 +400,7 @@ flow_offload_lookup(struct nf_flowtable\n }\n EXPORT_SYMBOL_GPL(flow_offload_lookup);\n \n-static int\n-nf_flow_table_iterate(struct nf_flowtable *flow_table,\n+int nf_flow_table_iterate(struct nf_flowtable *flow_table,\n \t\t      void (*iter)(struct flow_offload *flow, void *data),\n \t\t      void *data)\n {\n@@ -434,6 +432,7 @@ nf_flow_table_iterate(struct nf_flowtabl\n \n \treturn err;\n }\n+EXPORT_SYMBOL_GPL(nf_flow_table_iterate);\n \n static bool flow_offload_stale_dst(struct flow_offload_tuple *tuple)\n {\n--- /dev/null\n+++ b/include/uapi/linux/netfilter/xt_FLOWOFFLOAD.h\n@@ -0,0 +1,17 @@\n+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */\n+#ifndef _XT_FLOWOFFLOAD_H\n+#define _XT_FLOWOFFLOAD_H\n+\n+#include <linux/types.h>\n+\n+enum {\n+\tXT_FLOWOFFLOAD_HW\t= 1 << 0,\n+\n+\tXT_FLOWOFFLOAD_MASK\t= XT_FLOWOFFLOAD_HW\n+};\n+\n+struct xt_flowoffload_target_info {\n+\t__u32 flags;\n+};\n+\n+#endif /* _XT_FLOWOFFLOAD_H */\n--- a/include/net/netfilter/nf_flow_table.h\n+++ b/include/net/netfilter/nf_flow_table.h\n@@ -270,6 +270,10 @@ void nf_flow_table_free(struct nf_flowta\n \n void flow_offload_teardown(struct flow_offload *flow);\n \n+int nf_flow_table_iterate(struct nf_flowtable *flow_table,\n+\t\t\t  void (*iter)(struct flow_offload *flow, void *data),\n+\t\t\t  void *data);\n+\n void nf_flow_snat_port(const struct flow_offload *flow,\n \t\t       struct sk_buff *skb, unsigned int thoff,\n \t\t       u8 protocol, enum flow_offload_tuple_dir dir);\n"
  },
  {
    "path": "target/linux/generic/hack-5.10/651-wireless_mesh_header.patch",
    "content": "From 6d3bc769657b0ee7c7506dad9911111c4226a7ea Mon Sep 17 00:00:00 2001\nFrom: Imre Kaloz <kaloz@openwrt.org>\nDate: Fri, 7 Jul 2017 17:21:05 +0200\nSubject: mac80211: increase wireless mesh header size\n\nlede-commit 3d4466cfd8f75f717efdb1f96fdde3c70d865fc1\nSigned-off-by: Imre Kaloz <kaloz@openwrt.org>\n---\n include/linux/netdevice.h | 4 ++--\n 1 file changed, 2 insertions(+), 2 deletions(-)\n\n--- a/include/linux/netdevice.h\n+++ b/include/linux/netdevice.h\n@@ -144,8 +144,8 @@ static inline bool dev_xmit_complete(int\n \n #if defined(CONFIG_HYPERV_NET)\n # define LL_MAX_HEADER 128\n-#elif defined(CONFIG_WLAN) || IS_ENABLED(CONFIG_AX25)\n-# if defined(CONFIG_MAC80211_MESH)\n+#elif defined(CONFIG_WLAN) || IS_ENABLED(CONFIG_AX25) || 1\n+# if defined(CONFIG_MAC80211_MESH) || 1\n #  define LL_MAX_HEADER 128\n # else\n #  define LL_MAX_HEADER 96\n"
  },
  {
    "path": "target/linux/generic/hack-5.10/660-fq_codel_defaults.patch",
    "content": "From a6ccb238939b25851474a279b20367fd24a0e816 Mon Sep 17 00:00:00 2001\nFrom: Felix Fietkau <nbd@nbd.name>\nDate: Fri, 7 Jul 2017 17:21:53 +0200\nSubject:  hack: net: fq_codel: tune defaults for small devices\n\nAssume that x86_64 devices always have a big memory and do not need this \noptimization compared to devices with only 32 MB or 64 MB RAM.\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n net/sched/sch_fq_codel.c | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/net/sched/sch_fq_codel.c\n+++ b/net/sched/sch_fq_codel.c\n@@ -469,7 +469,11 @@ static int fq_codel_init(struct Qdisc *s\n \n \tsch->limit = 10*1024;\n \tq->flows_cnt = 1024;\n+#ifdef CONFIG_X86_64\n \tq->memory_limit = 32 << 20; /* 32 MBytes */\n+#else\n+\tq->memory_limit = 4 << 20; /* 4 MBytes */\n+#endif\n \tq->drop_batch_size = 64;\n \tq->quantum = psched_mtu(qdisc_dev(sch));\n \tINIT_LIST_HEAD(&q->new_flows);\n"
  },
  {
    "path": "target/linux/generic/hack-5.10/661-kernel-ct-size-the-hashtable-more-adequately.patch",
    "content": "From 804fbb3f2ec9283f7b778e057a68bfff440a0be6 Mon Sep 17 00:00:00 2001\nFrom: Rui Salvaterra <rsalvaterra@gmail.com>\nDate: Wed, 30 Mar 2022 22:51:55 +0100\nSubject: [PATCH] kernel: ct: size the hashtable more adequately\n\nTo set the default size of the connection tracking hash table, a divider of\n16384 becomes inadequate for a router handling lots of connections. Divide by\n2048 instead, making the default size scale better with the available RAM.\n\nSigned-off-by: Rui Salvaterra <rsalvaterra@gmail.com>\n---\n net/netfilter/nf_conntrack_core.c | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/net/netfilter/nf_conntrack_core.c\n+++ b/net/netfilter/nf_conntrack_core.c\n@@ -2576,7 +2576,7 @@ int nf_conntrack_init_start(void)\n \n \tif (!nf_conntrack_htable_size) {\n \t\tnf_conntrack_htable_size\n-\t\t\t= (((nr_pages << PAGE_SHIFT) / 16384)\n+\t\t\t= (((nr_pages << PAGE_SHIFT) / 2048)\n \t\t\t   / sizeof(struct hlist_head));\n \t\tif (BITS_PER_LONG >= 64 &&\n \t\t    nr_pages > (4 * (1024 * 1024 * 1024 / PAGE_SIZE)))\n"
  },
  {
    "path": "target/linux/generic/hack-5.10/700-swconfig_switch_drivers.patch",
    "content": "From 36e516290611e613aa92996cb4339561452695b4 Mon Sep 17 00:00:00 2001\nFrom: Felix Fietkau <nbd@nbd.name>\nDate: Fri, 7 Jul 2017 17:24:23 +0200\nSubject: net: swconfig: adds openwrt switch layer\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n drivers/net/phy/Kconfig   | 83 +++++++++++++++++++++++++++++++++++++++++++++++\n drivers/net/phy/Makefile  | 15 +++++++++\n include/uapi/linux/Kbuild |  1 +\n 3 files changed, 99 insertions(+)\n\n--- a/drivers/net/phy/Kconfig\n+++ b/drivers/net/phy/Kconfig\n@@ -61,6 +61,80 @@ config SFP\n \tdepends on HWMON || HWMON=n\n \tselect MDIO_I2C\n \n+comment \"Switch configuration API + drivers\"\n+\n+config SWCONFIG\n+\ttristate \"Switch configuration API\"\n+\thelp\n+\t  Switch configuration API using netlink. This allows\n+\t  you to configure the VLAN features of certain switches.\n+\n+config SWCONFIG_LEDS\n+\tbool \"Switch LED trigger support\"\n+\tdepends on (SWCONFIG && LEDS_TRIGGERS)\n+\n+config ADM6996_PHY\n+\ttristate \"Driver for ADM6996 switches\"\n+\tselect SWCONFIG\n+\thelp\n+\t  Currently supports the ADM6996FC and ADM6996M switches.\n+\t  Support for FC is very limited.\n+\n+config AR8216_PHY\n+\ttristate \"Driver for Atheros AR8216 switches\"\n+\tselect SWCONFIG\n+\tselect ETHERNET_PACKET_MANGLE\n+\n+config AR8216_PHY_LEDS\n+\tbool \"Atheros AR8216 switch LED support\"\n+\tdepends on (AR8216_PHY && LEDS_CLASS)\n+\n+source \"drivers/net/phy/b53/Kconfig\"\n+\n+config IP17XX_PHY\n+\ttristate \"Driver for IC+ IP17xx switches\"\n+\tselect SWCONFIG\n+\n+config PSB6970_PHY\n+\ttristate \"Lantiq XWAY Tantos (PSB6970) Ethernet switch\"\n+\tselect SWCONFIG\n+\n+config RTL8306_PHY\n+\ttristate \"Driver for Realtek RTL8306S switches\"\n+\tselect SWCONFIG\n+\n+config RTL8366_SMI\n+\ttristate \"Driver for the RTL8366 SMI interface\"\n+\tdepends on GPIOLIB\n+\thelp\n+\t  This module implements the SMI interface protocol which is used\n+\t  by some RTL8366 ethernet switch devices via the generic GPIO API.\n+\n+if RTL8366_SMI\n+\n+config RTL8366_SMI_DEBUG_FS\n+\tbool \"RTL8366 SMI interface debugfs support\"\n+        depends on DEBUG_FS\n+        default n\n+\n+config RTL8366S_PHY\n+\ttristate \"Driver for the Realtek RTL8366S switch\"\n+\tselect SWCONFIG\n+\n+config RTL8366RB_PHY\n+\ttristate \"Driver for the Realtek RTL8366RB switch\"\n+\tselect SWCONFIG\n+\n+config RTL8367_PHY\n+\ttristate \"Driver for the Realtek RTL8367R/M switches\"\n+\tselect SWCONFIG\n+\n+config RTL8367B_PHY\n+\ttristate \"Driver fot the Realtek RTL8367R-VB switch\"\n+\tselect SWCONFIG\n+\n+endif # RTL8366_SMI\n+\n comment \"MII PHY device drivers\"\n \n config AMD_PHY\n--- a/drivers/net/phy/Makefile\n+++ b/drivers/net/phy/Makefile\n@@ -24,6 +24,19 @@ libphy-$(CONFIG_LED_TRIGGER_PHY)\t+= phy_\n obj-$(CONFIG_PHYLINK)\t\t+= phylink.o\n obj-$(CONFIG_PHYLIB)\t\t+= libphy.o\n \n+obj-$(CONFIG_SWCONFIG)\t\t+= swconfig.o\n+obj-$(CONFIG_ADM6996_PHY)\t+= adm6996.o\n+obj-$(CONFIG_AR8216_PHY)\t+= ar8216.o ar8327.o\n+obj-$(CONFIG_SWCONFIG_B53)\t+= b53/\n+obj-$(CONFIG_IP17XX_PHY)\t+= ip17xx.o\n+obj-$(CONFIG_PSB6970_PHY)\t+= psb6970.o\n+obj-$(CONFIG_RTL8306_PHY)\t+= rtl8306.o\n+obj-$(CONFIG_RTL8366_SMI)\t+= rtl8366_smi.o\n+obj-$(CONFIG_RTL8366S_PHY)\t+= rtl8366s.o\n+obj-$(CONFIG_RTL8366RB_PHY)\t+= rtl8366rb.o\n+obj-$(CONFIG_RTL8367_PHY)\t+= rtl8367.o\n+obj-$(CONFIG_RTL8367B_PHY)\t+= rtl8367b.o\n+\n obj-$(CONFIG_NETWORK_PHY_TIMESTAMPING) += mii_timestamper.o\n \n obj-$(CONFIG_SFP)\t\t+= sfp.o\n--- a/include/linux/platform_data/b53.h\n+++ b/include/linux/platform_data/b53.h\n@@ -29,6 +29,9 @@ struct b53_platform_data {\n \tu32 chip_id;\n \tu16 enabled_ports;\n \n+\t/* allow to specify an ethX alias */\n+\tconst char *alias;\n+\n \t/* only used by MMAP'd driver */\n \tunsigned big_endian:1;\n \tvoid __iomem *regs;\n"
  },
  {
    "path": "target/linux/generic/hack-5.10/711-net-dsa-mv88e6xxx-disable-ATU-violation.patch",
    "content": "--- a/drivers/net/dsa/mv88e6xxx/chip.c\n+++ b/drivers/net/dsa/mv88e6xxx/chip.c\n@@ -2705,6 +2705,9 @@ static int mv88e6xxx_setup_port(struct m\n \tif (dsa_is_cpu_port(ds, port))\n \t\treg = 0;\n \n+\t/* Disable ATU member violation interrupt */\n+\treg |= MV88E6XXX_PORT_ASSOC_VECTOR_IGNORE_WRONG;\n+\n \terr = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR,\n \t\t\t\t   reg);\n \tif (err)\n"
  },
  {
    "path": "target/linux/generic/hack-5.10/720-net-phy-add-aqr-phys.patch",
    "content": "From: Birger Koblitz <git@birger-koblitz.de>\nDate: Sun, 5 Sep 2021 15:13:10 +0200\nSubject: [PATCH] kernel: Add AQR113C and AQR813 support\n\nThis hack adds support for the Aquantia 4th generation, 10GBit\nPHYs AQR113C and AQR813.\n\nSigned-off-by: Birger Koblitz <git@birger-koblitz.de>\n\n--- a/drivers/net/phy/aquantia_main.c\n+++ b/drivers/net/phy/aquantia_main.c\n@@ -20,8 +20,10 @@\n #define PHY_ID_AQR105\t0x03a1b4a2\n #define PHY_ID_AQR106\t0x03a1b4d0\n #define PHY_ID_AQR107\t0x03a1b4e0\n+#define PHY_ID_AQR113C\t0x31c31c12\n #define PHY_ID_AQCS109\t0x03a1b5c2\n #define PHY_ID_AQR405\t0x03a1b4b0\n+#define PHY_ID_AQR813\t0x31c31cb2\n \n #define MDIO_PHYXS_VEND_IF_STATUS\t\t0xe812\n #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK\tGENMASK(7, 3)\n@@ -330,6 +332,49 @@ static int aqr107_read_rate(struct phy_d\n \treturn 0;\n }\n \n+static int aqr113c_read_status(struct phy_device *phydev)\n+{\n+\tint val, ret;\n+\n+\tret = aqr_read_status(phydev);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tif (!phydev->link || phydev->autoneg == AUTONEG_DISABLE)\n+\t\treturn 0;\n+\n+\t// On AQR113C, the speed returned by aqr_read_status is wrong\n+\taqr107_read_rate(phydev);\n+\n+\tval = phy_read_mmd(phydev, MDIO_MMD_PHYXS, MDIO_PHYXS_VEND_IF_STATUS);\n+\tif (val < 0)\n+\t\treturn val;\n+\n+\tswitch (FIELD_GET(MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK, val)) {\n+\tcase MDIO_PHYXS_VEND_IF_STATUS_TYPE_KR:\n+\t\tphydev->interface = PHY_INTERFACE_MODE_10GKR;\n+\t\tbreak;\n+\tcase MDIO_PHYXS_VEND_IF_STATUS_TYPE_XFI:\n+\t\tphydev->interface = PHY_INTERFACE_MODE_10GBASER;\n+\t\tbreak;\n+\tcase MDIO_PHYXS_VEND_IF_STATUS_TYPE_USXGMII:\n+\t\tphydev->interface = PHY_INTERFACE_MODE_USXGMII;\n+\t\tbreak;\n+\tcase MDIO_PHYXS_VEND_IF_STATUS_TYPE_SGMII:\n+\t\tphydev->interface = PHY_INTERFACE_MODE_SGMII;\n+\t\tbreak;\n+\tcase MDIO_PHYXS_VEND_IF_STATUS_TYPE_OCSGMII:\n+\t\tphydev->interface = PHY_INTERFACE_MODE_2500BASEX;\n+\t\tbreak;\n+\tdefault:\n+\t\tphydev->interface = PHY_INTERFACE_MODE_NA;\n+\t\tbreak;\n+\t}\n+\n+\t/* Read downshifted rate from vendor register */\n+\treturn aqr107_read_rate(phydev);\n+}\n+\n static int aqr107_read_status(struct phy_device *phydev)\n {\n \tint val, ret;\n@@ -460,7 +505,7 @@ static void aqr107_chip_info(struct phy_\n \tbuild_id = FIELD_GET(VEND1_GLOBAL_RSVD_STAT1_FW_BUILD_ID, val);\n \tprov_id = FIELD_GET(VEND1_GLOBAL_RSVD_STAT1_PROV_ID, val);\n \n-\tphydev_dbg(phydev, \"FW %u.%u, Build %u, Provisioning %u\\n\",\n+\tphydev_info(phydev, \"FW %u.%u, Build %u, Provisioning %u\\n\",\n \t\t   fw_major, fw_minor, build_id, prov_id);\n }\n \n@@ -632,6 +677,24 @@ static struct phy_driver aqr_driver[] =\n \t.link_change_notify = aqr107_link_change_notify,\n },\n {\n+\tPHY_ID_MATCH_MODEL(PHY_ID_AQR113C),\n+\t.name\t\t= \"Aquantia AQR113C\",\n+\t.probe\t\t= aqr107_probe,\n+\t.config_init\t= aqr107_config_init,\n+\t.config_aneg    = aqr_config_aneg,\n+\t.config_intr\t= aqr_config_intr,\n+\t.ack_interrupt\t= aqr_ack_interrupt,\n+\t.read_status\t= aqr113c_read_status,\n+\t.get_tunable    = aqr107_get_tunable,\n+\t.set_tunable    = aqr107_set_tunable,\n+\t.suspend\t= aqr107_suspend,\n+\t.resume\t\t= aqr107_resume,\n+\t.get_sset_count\t= aqr107_get_sset_count,\n+\t.get_strings\t= aqr107_get_strings,\n+\t.get_stats\t= aqr107_get_stats,\n+\t.link_change_notify = aqr107_link_change_notify,\n+},\n+{\n \tPHY_ID_MATCH_MODEL(PHY_ID_AQCS109),\n \t.name\t\t= \"Aquantia AQCS109\",\n \t.probe\t\t= aqr107_probe,\n@@ -657,6 +720,24 @@ static struct phy_driver aqr_driver[] =\n \t.ack_interrupt\t= aqr_ack_interrupt,\n \t.read_status\t= aqr_read_status,\n },\n+{\n+\tPHY_ID_MATCH_MODEL(PHY_ID_AQR813),\n+\t.name\t\t= \"Aquantia AQR813\",\n+\t.probe\t\t= aqr107_probe,\n+\t.config_init\t= aqr107_config_init,\n+\t.config_aneg    = aqr_config_aneg,\n+\t.config_intr\t= aqr_config_intr,\n+\t.ack_interrupt\t= aqr_ack_interrupt,\n+\t.read_status\t= aqr113c_read_status,\n+\t.get_tunable    = aqr107_get_tunable,\n+\t.set_tunable    = aqr107_set_tunable,\n+\t.suspend\t= aqr107_suspend,\n+\t.resume\t\t= aqr107_resume,\n+\t.get_sset_count\t= aqr107_get_sset_count,\n+\t.get_strings\t= aqr107_get_strings,\n+\t.get_stats\t= aqr107_get_stats,\n+\t.link_change_notify = aqr107_link_change_notify,\n+},\n };\n \n module_phy_driver(aqr_driver);\n@@ -667,8 +748,10 @@ static struct mdio_device_id __maybe_unu\n \t{ PHY_ID_MATCH_MODEL(PHY_ID_AQR105) },\n \t{ PHY_ID_MATCH_MODEL(PHY_ID_AQR106) },\n \t{ PHY_ID_MATCH_MODEL(PHY_ID_AQR107) },\n+\t{ PHY_ID_MATCH_MODEL(PHY_ID_AQR113C) },\n \t{ PHY_ID_MATCH_MODEL(PHY_ID_AQCS109) },\n \t{ PHY_ID_MATCH_MODEL(PHY_ID_AQR405) },\n+\t{ PHY_ID_MATCH_MODEL(PHY_ID_AQR813) },\n \t{ }\n };\n \n"
  },
  {
    "path": "target/linux/generic/hack-5.10/721-net-add-packet-mangeling.patch",
    "content": "From ffe387740bbe88dd88bbe04d6375902708003d6e Mon Sep 17 00:00:00 2001\nFrom: Felix Fietkau <nbd@nbd.name>\nDate: Fri, 7 Jul 2017 17:25:00 +0200\nSubject: net: add packet mangeling\n\nar8216 switches have a hardware bug, which renders normal 802.1q support\nunusable. Packet mangling is required to fix up the vlan for incoming\npackets.\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n include/linux/netdevice.h | 11 +++++++++++\n include/linux/skbuff.h    | 14 ++++----------\n net/Kconfig               |  6 ++++++\n net/core/dev.c            | 20 +++++++++++++++-----\n net/core/skbuff.c         | 17 +++++++++++++++++\n net/ethernet/eth.c        |  6 ++++++\n 6 files changed, 59 insertions(+), 15 deletions(-)\n\n--- a/include/linux/netdevice.h\n+++ b/include/linux/netdevice.h\n@@ -1625,6 +1625,7 @@ enum netdev_priv_flags {\n \tIFF_FAILOVER_SLAVE\t\t= 1<<28,\n \tIFF_L3MDEV_RX_HANDLER\t\t= 1<<29,\n \tIFF_LIVE_RENAME_OK\t\t= 1<<30,\n+\tIFF_NO_IP_ALIGN\t\t\t= 1<<31,\n };\n \n #define IFF_802_1Q_VLAN\t\t\tIFF_802_1Q_VLAN\n@@ -1657,6 +1658,7 @@ enum netdev_priv_flags {\n #define IFF_FAILOVER_SLAVE\t\tIFF_FAILOVER_SLAVE\n #define IFF_L3MDEV_RX_HANDLER\t\tIFF_L3MDEV_RX_HANDLER\n #define IFF_LIVE_RENAME_OK\t\tIFF_LIVE_RENAME_OK\n+#define IFF_NO_IP_ALIGN\t\t\tIFF_NO_IP_ALIGN\n \n /* Specifies the type of the struct net_device::ml_priv pointer */\n enum netdev_ml_priv_type {\n@@ -1997,6 +1999,11 @@ struct net_device {\n \tconst struct tlsdev_ops *tlsdev_ops;\n #endif\n \n+#ifdef CONFIG_ETHERNET_PACKET_MANGLE\n+\tvoid (*eth_mangle_rx)(struct net_device *dev, struct sk_buff *skb);\n+\tstruct sk_buff *(*eth_mangle_tx)(struct net_device *dev, struct sk_buff *skb);\n+#endif\n+\n \tconst struct header_ops *header_ops;\n \n \tunsigned int\t\tflags;\n@@ -2087,6 +2094,10 @@ struct net_device {\n \tstruct mpls_dev __rcu\t*mpls_ptr;\n #endif\n \n+#ifdef CONFIG_ETHERNET_PACKET_MANGLE\n+\tvoid\t\t\t*phy_ptr; /* PHY device specific data */\n+#endif\n+\n /*\n  * Cache lines mostly used on receive path (including eth_type_trans())\n  */\n--- a/include/linux/skbuff.h\n+++ b/include/linux/skbuff.h\n@@ -2710,6 +2710,10 @@ static inline int pskb_trim(struct sk_bu\n \treturn (len < skb->len) ? __pskb_trim(skb, len) : 0;\n }\n \n+extern struct sk_buff *__netdev_alloc_skb_ip_align(struct net_device *dev,\n+\t\tunsigned int length, gfp_t gfp);\n+\n+\n /**\n  *\tpskb_trim_unique - remove end from a paged unique (not cloned) buffer\n  *\t@skb: buffer to alter\n@@ -2841,16 +2845,6 @@ static inline struct sk_buff *dev_alloc_\n }\n \n \n-static inline struct sk_buff *__netdev_alloc_skb_ip_align(struct net_device *dev,\n-\t\tunsigned int length, gfp_t gfp)\n-{\n-\tstruct sk_buff *skb = __netdev_alloc_skb(dev, length + NET_IP_ALIGN, gfp);\n-\n-\tif (NET_IP_ALIGN && skb)\n-\t\tskb_reserve(skb, NET_IP_ALIGN);\n-\treturn skb;\n-}\n-\n static inline struct sk_buff *netdev_alloc_skb_ip_align(struct net_device *dev,\n \t\tunsigned int length)\n {\n--- a/net/Kconfig\n+++ b/net/Kconfig\n@@ -26,6 +26,12 @@ menuconfig NET\n \n if NET\n \n+config ETHERNET_PACKET_MANGLE\n+\tbool\n+\thelp\n+\t  This option can be selected by phy drivers that need to mangle\n+\t  packets going in or out of an ethernet device.\n+\n config WANT_COMPAT_NETLINK_MESSAGES\n \tbool\n \thelp\n--- a/net/core/dev.c\n+++ b/net/core/dev.c\n@@ -3650,6 +3650,11 @@ static int xmit_one(struct sk_buff *skb,\n \tif (dev_nit_active(dev))\n \t\tdev_queue_xmit_nit(skb, dev);\n \n+#ifdef CONFIG_ETHERNET_PACKET_MANGLE\n+\tif (dev->eth_mangle_tx && !(skb = dev->eth_mangle_tx(dev, skb)))\n+\t\treturn NETDEV_TX_OK;\n+#endif\n+\n \tlen = skb->len;\n \tPRANDOM_ADD_NOISE(skb, dev, txq, len + jiffies);\n \ttrace_net_dev_start_xmit(skb, dev);\n--- a/net/core/skbuff.c\n+++ b/net/core/skbuff.c\n@@ -60,6 +60,7 @@\n #include <linux/prefetch.h>\n #include <linux/if_vlan.h>\n #include <linux/mpls.h>\n+#include <linux/if.h>\n \n #include <net/protocol.h>\n #include <net/dst.h>\n@@ -553,6 +554,22 @@ skb_fail:\n }\n EXPORT_SYMBOL(__napi_alloc_skb);\n \n+struct sk_buff *__netdev_alloc_skb_ip_align(struct net_device *dev,\n+\t\tunsigned int length, gfp_t gfp)\n+{\n+\tstruct sk_buff *skb = __netdev_alloc_skb(dev, length + NET_IP_ALIGN, gfp);\n+\n+#ifdef CONFIG_ETHERNET_PACKET_MANGLE\n+\tif (dev && (dev->priv_flags & IFF_NO_IP_ALIGN))\n+\t\treturn skb;\n+#endif\n+\n+\tif (NET_IP_ALIGN && skb)\n+\t\tskb_reserve(skb, NET_IP_ALIGN);\n+\treturn skb;\n+}\n+EXPORT_SYMBOL(__netdev_alloc_skb_ip_align);\n+\n void skb_add_rx_frag(struct sk_buff *skb, int i, struct page *page, int off,\n \t\t     int size, unsigned int truesize)\n {\n--- a/net/ethernet/eth.c\n+++ b/net/ethernet/eth.c\n@@ -171,6 +171,12 @@ __be16 eth_type_trans(struct sk_buff *sk\n \tconst struct ethhdr *eth;\n \n \tskb->dev = dev;\n+\n+#ifdef CONFIG_ETHERNET_PACKET_MANGLE\n+\tif (dev->eth_mangle_rx)\n+\t\tdev->eth_mangle_rx(dev, skb);\n+#endif\n+\n \tskb_reset_mac_header(skb);\n \n \teth = (struct ethhdr *)skb->data;\n"
  },
  {
    "path": "target/linux/generic/hack-5.10/722-net-phy-aquantia-enable-AQR112-and-AQR412.patch",
    "content": "From 5f62951fba63a9f9cfff564209426bdea5fcc371 Mon Sep 17 00:00:00 2001\nFrom: Alex Marginean <alexandru.marginean@nxp.com>\nDate: Tue, 27 Aug 2019 15:16:56 +0300\nSubject: [PATCH] drivers: net: phy: aquantia: enable AQR112 and AQR412\n\nAdds support for AQR112 and AQR412 which is mostly based on existing code\nwith the addition of code configuring the protocol on system side.\nThis allows changing the system side protocol without having to deploy a\ndifferent firmware on the PHY.\n\nSigned-off-by: Alex Marginean <alexandru.marginean@nxp.com>\n---\n drivers/net/phy/aquantia_main.c | 88 +++++++++++++++++++++++++++++++++++++++++\n 1 file changed, 88 insertions(+)\n\n--- a/drivers/net/phy/aquantia_main.c\n+++ b/drivers/net/phy/aquantia_main.c\n@@ -20,9 +20,11 @@\n #define PHY_ID_AQR105\t0x03a1b4a2\n #define PHY_ID_AQR106\t0x03a1b4d0\n #define PHY_ID_AQR107\t0x03a1b4e0\n+#define PHY_ID_AQR112\t0x03a1b662\n #define PHY_ID_AQR113C\t0x31c31c12\n #define PHY_ID_AQCS109\t0x03a1b5c2\n #define PHY_ID_AQR405\t0x03a1b4b0\n+#define PHY_ID_AQR412\t0x03a1b712\n #define PHY_ID_AQR813\t0x31c31cb2\n \n #define MDIO_PHYXS_VEND_IF_STATUS\t\t0xe812\n@@ -123,6 +125,29 @@\n #define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL2\tBIT(1)\n #define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL3\tBIT(0)\n \n+/* registers in MDIO_MMD_VEND1 region */\n+#define AQUANTIA_VND1_GLOBAL_SC\t\t\t0x000\n+#define  AQUANTIA_VND1_GLOBAL_SC_LP\t\tBIT(0xb)\n+\n+/* global start rate, the protocol associated with this speed is used by default\n+ * on SI.\n+ */\n+#define AQUANTIA_VND1_GSTART_RATE\t\t0x31a\n+#define  AQUANTIA_VND1_GSTART_RATE_OFF\t\t0\n+#define  AQUANTIA_VND1_GSTART_RATE_100M\t\t1\n+#define  AQUANTIA_VND1_GSTART_RATE_1G\t\t2\n+#define  AQUANTIA_VND1_GSTART_RATE_10G\t\t3\n+#define  AQUANTIA_VND1_GSTART_RATE_2_5G\t\t4\n+#define  AQUANTIA_VND1_GSTART_RATE_5G\t\t5\n+\n+/* SYSCFG registers for 100M, 1G, 2.5G, 5G, 10G */\n+#define AQUANTIA_VND1_GSYSCFG_BASE\t\t0x31b\n+#define AQUANTIA_VND1_GSYSCFG_100M\t\t0\n+#define AQUANTIA_VND1_GSYSCFG_1G\t\t1\n+#define AQUANTIA_VND1_GSYSCFG_2_5G\t\t2\n+#define AQUANTIA_VND1_GSYSCFG_5G\t\t3\n+#define AQUANTIA_VND1_GSYSCFG_10G\t\t4\n+\n struct aqr107_hw_stat {\n \tconst char *name;\n \tint reg;\n@@ -243,6 +268,51 @@ static int aqr_config_aneg(struct phy_de\n \treturn genphy_c45_check_and_restart_aneg(phydev, changed);\n }\n \n+static struct {\n+\tu16 syscfg;\n+\tint cnt;\n+\tu16 start_rate;\n+} aquantia_syscfg[PHY_INTERFACE_MODE_MAX] = {\n+\t[PHY_INTERFACE_MODE_SGMII] =      {0x04b, AQUANTIA_VND1_GSYSCFG_1G,\n+\t\t\t\t\t   AQUANTIA_VND1_GSTART_RATE_1G},\n+\t[PHY_INTERFACE_MODE_2500BASEX] = {0x144, AQUANTIA_VND1_GSYSCFG_2_5G,\n+\t\t\t\t\t   AQUANTIA_VND1_GSTART_RATE_2_5G},\n+\t[PHY_INTERFACE_MODE_XGMII] =      {0x100, AQUANTIA_VND1_GSYSCFG_10G,\n+\t\t\t\t\t   AQUANTIA_VND1_GSTART_RATE_10G},\n+\t[PHY_INTERFACE_MODE_USXGMII] =    {0x080, AQUANTIA_VND1_GSYSCFG_10G,\n+\t\t\t\t\t   AQUANTIA_VND1_GSTART_RATE_10G},\n+};\n+\n+/* Sets up protocol on system side before calling aqr_config_aneg */\n+static int aqr_config_aneg_set_prot(struct phy_device *phydev)\n+{\n+\tint if_type = phydev->interface;\n+\tint i;\n+\n+\tif (!aquantia_syscfg[if_type].cnt)\n+\t\treturn 0;\n+\n+\t/* set PHY in low power mode so we can configure protocols */\n+\tphy_write_mmd(phydev, MDIO_MMD_VEND1, AQUANTIA_VND1_GLOBAL_SC,\n+\t\t      AQUANTIA_VND1_GLOBAL_SC_LP);\n+\tmdelay(10);\n+\n+\t/* set the default rate to enable the SI link */\n+\tphy_write_mmd(phydev, MDIO_MMD_VEND1, AQUANTIA_VND1_GSTART_RATE,\n+\t\t      aquantia_syscfg[if_type].start_rate);\n+\n+\tfor (i = 0; i <= aquantia_syscfg[if_type].cnt; i++)\n+\t\tphy_write_mmd(phydev, MDIO_MMD_VEND1,\n+\t\t\t      AQUANTIA_VND1_GSYSCFG_BASE + i,\n+\t\t\t      aquantia_syscfg[if_type].syscfg);\n+\n+\t/* wake PHY back up */\n+\tphy_write_mmd(phydev, MDIO_MMD_VEND1, AQUANTIA_VND1_GLOBAL_SC, 0);\n+\tmdelay(10);\n+\n+\treturn aqr_config_aneg(phydev);\n+}\n+\n static int aqr_config_intr(struct phy_device *phydev)\n {\n \tbool en = phydev->interrupts == PHY_INTERRUPT_ENABLED;\n@@ -738,6 +808,30 @@ static struct phy_driver aqr_driver[] =\n \t.get_stats\t= aqr107_get_stats,\n \t.link_change_notify = aqr107_link_change_notify,\n },\n+{\n+\tPHY_ID_MATCH_MODEL(PHY_ID_AQR112),\n+\t.name\t\t= \"Aquantia AQR112\",\n+\t.probe\t\t= aqr107_probe,\n+\t.config_aneg\t= aqr_config_aneg_set_prot,\n+\t.config_intr\t= aqr_config_intr,\n+\t.ack_interrupt\t= aqr_ack_interrupt,\n+\t.read_status\t= aqr107_read_status,\n+\t.get_sset_count\t= aqr107_get_sset_count,\n+\t.get_strings\t= aqr107_get_strings,\n+\t.get_stats\t= aqr107_get_stats,\n+},\n+{\n+\tPHY_ID_MATCH_MODEL(PHY_ID_AQR412),\n+\t.name\t\t= \"Aquantia AQR412\",\n+\t.probe\t\t= aqr107_probe,\n+\t.config_aneg\t= aqr_config_aneg_set_prot,\n+\t.config_intr\t= aqr_config_intr,\n+\t.ack_interrupt\t= aqr_ack_interrupt,\n+\t.read_status\t= aqr107_read_status,\n+\t.get_sset_count\t= aqr107_get_sset_count,\n+\t.get_strings\t= aqr107_get_strings,\n+\t.get_stats\t= aqr107_get_stats,\n+},\n };\n \n module_phy_driver(aqr_driver);\n@@ -748,9 +842,11 @@ static struct mdio_device_id __maybe_unu\n \t{ PHY_ID_MATCH_MODEL(PHY_ID_AQR105) },\n \t{ PHY_ID_MATCH_MODEL(PHY_ID_AQR106) },\n \t{ PHY_ID_MATCH_MODEL(PHY_ID_AQR107) },\n+\t{ PHY_ID_MATCH_MODEL(PHY_ID_AQR112) },\n \t{ PHY_ID_MATCH_MODEL(PHY_ID_AQR113C) },\n \t{ PHY_ID_MATCH_MODEL(PHY_ID_AQCS109) },\n \t{ PHY_ID_MATCH_MODEL(PHY_ID_AQR405) },\n+\t{ PHY_ID_MATCH_MODEL(PHY_ID_AQR412) },\n \t{ PHY_ID_MATCH_MODEL(PHY_ID_AQR813) },\n \t{ }\n };\n"
  },
  {
    "path": "target/linux/generic/hack-5.10/723-net-phy-aquantia-fix-system-side-protocol-mi.patch",
    "content": "From 5f008cb22f60da4e10375f22266c1a4e20b1252e Mon Sep 17 00:00:00 2001\nFrom: Alex Marginean <alexandru.marginean@nxp.com>\nDate: Fri, 20 Sep 2019 18:22:52 +0300\nSubject: [PATCH] drivers: net: phy: aquantia: fix system side protocol\n misconfiguration\n\nDo not set up protocols for speeds that are not supported by FW.  Enabling\nthese protocols leads to link issues on system side.\n\nSigned-off-by: Alex Marginean <alexandru.marginean@nxp.com>\n---\n drivers/net/phy/aquantia_main.c | 8 +++++++-\n 1 file changed, 7 insertions(+), 1 deletion(-)\n\n--- a/drivers/net/phy/aquantia_main.c\n+++ b/drivers/net/phy/aquantia_main.c\n@@ -301,10 +301,16 @@ static int aqr_config_aneg_set_prot(stru\n \tphy_write_mmd(phydev, MDIO_MMD_VEND1, AQUANTIA_VND1_GSTART_RATE,\n \t\t      aquantia_syscfg[if_type].start_rate);\n \n-\tfor (i = 0; i <= aquantia_syscfg[if_type].cnt; i++)\n+\tfor (i = 0; i <= aquantia_syscfg[if_type].cnt; i++) {\n+\t\tu16 reg = phy_read_mmd(phydev, MDIO_MMD_VEND1,\n+\t\t\t\t       AQUANTIA_VND1_GSYSCFG_BASE + i);\n+\t\tif (!reg)\n+\t\t\tcontinue;\n+\n \t\tphy_write_mmd(phydev, MDIO_MMD_VEND1,\n \t\t\t      AQUANTIA_VND1_GSYSCFG_BASE + i,\n \t\t\t      aquantia_syscfg[if_type].syscfg);\n+\t}\n \n \t/* wake PHY back up */\n \tphy_write_mmd(phydev, MDIO_MMD_VEND1, AQUANTIA_VND1_GLOBAL_SC, 0);\n"
  },
  {
    "path": "target/linux/generic/hack-5.10/724-net-phy-aquantia-Add-AQR113-driver-support.patch",
    "content": "From 2e677e4ae8f8330f68013163b060d0fda3a43095 Mon Sep 17 00:00:00 2001\nFrom: \"Langer, Thomas\" <tlanger@maxlinear.com>\nDate: Fri, 9 Jul 2021 17:36:46 +0200\nSubject: [PATCH] PONRTSYS-8842: aquantia: Add AQR113 driver support\n\nAdd a new entry for AQR113 PHY_ID\n---\n drivers/net/phy/aquantia_main.c | 10 ++++++++++\n 1 file changed, 10 insertions(+)\n\n--- a/drivers/net/phy/aquantia_main.c\n+++ b/drivers/net/phy/aquantia_main.c\n@@ -21,6 +21,7 @@\n #define PHY_ID_AQR106\t0x03a1b4d0\n #define PHY_ID_AQR107\t0x03a1b4e0\n #define PHY_ID_AQR112\t0x03a1b662\n+#define PHY_ID_AQR113\t0x31c31c40\n #define PHY_ID_AQR113C\t0x31c31c12\n #define PHY_ID_AQCS109\t0x03a1b5c2\n #define PHY_ID_AQR405\t0x03a1b4b0\n@@ -827,6 +828,14 @@ static struct phy_driver aqr_driver[] =\n \t.get_stats\t= aqr107_get_stats,\n },\n {\n+\tPHY_ID_MATCH_MODEL(PHY_ID_AQR113),\n+\t.name\t\t= \"Aquantia AQR113\",\n+\t.config_aneg\t= aqr_config_aneg,\n+\t.config_intr\t= aqr_config_intr,\n+\t.ack_interrupt\t= aqr_ack_interrupt,\n+\t.read_status\t= aqr107_read_status,\n+},\n+{\n \tPHY_ID_MATCH_MODEL(PHY_ID_AQR412),\n \t.name\t\t= \"Aquantia AQR412\",\n \t.probe\t\t= aqr107_probe,\n@@ -849,6 +858,7 @@ static struct mdio_device_id __maybe_unu\n \t{ PHY_ID_MATCH_MODEL(PHY_ID_AQR106) },\n \t{ PHY_ID_MATCH_MODEL(PHY_ID_AQR107) },\n \t{ PHY_ID_MATCH_MODEL(PHY_ID_AQR112) },\n+\t{ PHY_ID_MATCH_MODEL(PHY_ID_AQR113) },\n \t{ PHY_ID_MATCH_MODEL(PHY_ID_AQR113C) },\n \t{ PHY_ID_MATCH_MODEL(PHY_ID_AQCS109) },\n \t{ PHY_ID_MATCH_MODEL(PHY_ID_AQR405) },\n"
  },
  {
    "path": "target/linux/generic/hack-5.10/725-net-phy-aquantia-add-PHY_IDs-for-AQR112-variants.patch",
    "content": "From 3b92ee7b7899b6beffb2b484c58326e36612a873 Mon Sep 17 00:00:00 2001\nFrom: Daniel Golle <daniel@makrotopia.org>\nDate: Thu, 23 Dec 2021 14:52:56 +0000\nSubject: [PATCH] net: phy: aquantia: add PHY_ID for AQR112R\n\nAs advised by Ian Chang this PHY is used in Puzzle devices.\n\nSigned-off-by: Daniel Golle <daniel@makrotopia.org>\n---\n drivers/net/phy/aquantia_main.c | 10 ++++++++++\n 1 file changed, 10 insertions(+)\n\n--- a/drivers/net/phy/aquantia_main.c\n+++ b/drivers/net/phy/aquantia_main.c\n@@ -21,6 +21,8 @@\n #define PHY_ID_AQR106\t0x03a1b4d0\n #define PHY_ID_AQR107\t0x03a1b4e0\n #define PHY_ID_AQR112\t0x03a1b662\n+#define PHY_ID_AQR112C\t0x03a1b790\n+#define PHY_ID_AQR112R\t0x31c31d12\n #define PHY_ID_AQR113\t0x31c31c40\n #define PHY_ID_AQR113C\t0x31c31c12\n #define PHY_ID_AQCS109\t0x03a1b5c2\n@@ -828,6 +830,30 @@ static struct phy_driver aqr_driver[] =\n \t.get_stats\t= aqr107_get_stats,\n },\n {\n+\tPHY_ID_MATCH_MODEL(PHY_ID_AQR112C),\n+\t.name\t\t= \"Aquantia AQR112C\",\n+\t.probe\t\t= aqr107_probe,\n+\t.config_aneg\t= aqr_config_aneg_set_prot,\n+\t.config_intr\t= aqr_config_intr,\n+\t.ack_interrupt\t= aqr_ack_interrupt,\n+\t.read_status\t= aqr107_read_status,\n+\t.get_sset_count\t= aqr107_get_sset_count,\n+\t.get_strings\t= aqr107_get_strings,\n+\t.get_stats\t= aqr107_get_stats,\n+},\n+{\n+\tPHY_ID_MATCH_MODEL(PHY_ID_AQR112R),\n+\t.name\t\t= \"Aquantia AQR112R\",\n+\t.probe\t\t= aqr107_probe,\n+\t.config_aneg\t= aqr_config_aneg_set_prot,\n+\t.config_intr\t= aqr_config_intr,\n+\t.ack_interrupt\t= aqr_ack_interrupt,\n+\t.read_status\t= aqr107_read_status,\n+\t.get_sset_count\t= aqr107_get_sset_count,\n+\t.get_strings\t= aqr107_get_strings,\n+\t.get_stats\t= aqr107_get_stats,\n+},\n+{\n \tPHY_ID_MATCH_MODEL(PHY_ID_AQR113),\n \t.name\t\t= \"Aquantia AQR113\",\n \t.config_aneg\t= aqr_config_aneg,\n@@ -858,6 +884,8 @@ static struct mdio_device_id __maybe_unu\n \t{ PHY_ID_MATCH_MODEL(PHY_ID_AQR106) },\n \t{ PHY_ID_MATCH_MODEL(PHY_ID_AQR107) },\n \t{ PHY_ID_MATCH_MODEL(PHY_ID_AQR112) },\n+\t{ PHY_ID_MATCH_MODEL(PHY_ID_AQR112C) },\n+\t{ PHY_ID_MATCH_MODEL(PHY_ID_AQR112R) },\n \t{ PHY_ID_MATCH_MODEL(PHY_ID_AQR113) },\n \t{ PHY_ID_MATCH_MODEL(PHY_ID_AQR113C) },\n \t{ PHY_ID_MATCH_MODEL(PHY_ID_AQCS109) },\n"
  },
  {
    "path": "target/linux/generic/hack-5.10/760-net-usb-r8152-add-LED-configuration-from-OF.patch",
    "content": "From 82985725e071f2a5735052f18e109a32aeac3a0b Mon Sep 17 00:00:00 2001\nFrom: David Bauer <mail@david-bauer.net>\nDate: Sun, 26 Jul 2020 02:38:31 +0200\nSubject: [PATCH] net: usb: r8152: add LED configuration from OF\n\nThis adds the ability to configure the LED configuration register using\nOF. This way, the correct value for board specific LED configuration can\nbe determined.\n\nSigned-off-by: David Bauer <mail@david-bauer.net>\n---\n drivers/net/usb/r8152.c | 23 +++++++++++++++++++++++\n 1 file changed, 23 insertions(+)\n\n--- a/drivers/net/usb/r8152.c\n+++ b/drivers/net/usb/r8152.c\n@@ -11,6 +11,7 @@\n #include <linux/mii.h>\n #include <linux/ethtool.h>\n #include <linux/usb.h>\n+#include <linux/of.h>\n #include <linux/crc32.h>\n #include <linux/if_vlan.h>\n #include <linux/uaccess.h>\n@@ -6780,6 +6781,22 @@ static void rtl_tally_reset(struct r8152\n \tocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data);\n }\n \n+static int r8152_led_configuration(struct r8152 *tp)\n+{\n+\tu32 led_data;\n+\tint ret;\n+\n+\tret = of_property_read_u32(tp->udev->dev.of_node, \"realtek,led-data\",\n+\t\t\t\t\t\t\t\t&led_data);\n+\n+\tif (ret)\n+\t\treturn ret;\n+\t\n+\tocp_write_word(tp, MCU_TYPE_PLA, PLA_LEDSEL, led_data);\n+\n+\treturn 0;\n+}\n+\n static void r8152b_init(struct r8152 *tp)\n {\n \tu32 ocp_data;\n@@ -6821,6 +6838,8 @@ static void r8152b_init(struct r8152 *tp\n \tocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);\n \tocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);\n \tocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);\n+\n+\tr8152_led_configuration(tp);\n }\n \n static void r8153_init(struct r8152 *tp)\n@@ -6961,6 +6980,8 @@ static void r8153_init(struct r8152 *tp)\n \t\ttp->coalesce = COALESCE_SLOW;\n \t\tbreak;\n \t}\n+\n+\tr8152_led_configuration(tp);\n }\n \n static void r8153b_init(struct r8152 *tp)\n@@ -7043,6 +7064,8 @@ static void r8153b_init(struct r8152 *tp\n \trtl_tally_reset(tp);\n \n \ttp->coalesce = 15000;\t/* 15 us */\n+\n+\tr8152_led_configuration(tp);\n }\n \n static void r8153c_init(struct r8152 *tp)\n"
  },
  {
    "path": "target/linux/generic/hack-5.10/761-dt-bindings-net-add-RTL8152-binding-documentation.patch",
    "content": "From 3ee05f4aa64fc86af3be5bc176ba5808de9260a7 Mon Sep 17 00:00:00 2001\nFrom: David Bauer <mail@david-bauer.net>\nDate: Sun, 26 Jul 2020 15:30:33 +0200\nSubject: [PATCH] dt-bindings: net: add RTL8152 binding documentation\n\nAdd binding documentation for the Realtek RTL8152 / RTL8153 USB ethernet\nadapters.\n\nSigned-off-by: David Bauer <mail@david-bauer.net>\n---\n .../bindings/net/realtek,rtl8152.yaml         | 36 +++++++++++++++++++\n 1 file changed, 36 insertions(+)\n create mode 100644 Documentation/devicetree/bindings/net/realtek,rtl8152.yaml\n\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/net/realtek,rtl8152.yaml\n@@ -0,0 +1,36 @@\n+# SPDX-License-Identifier: GPL-2.0\n+%YAML 1.2\n+---\n+$id: http://devicetree.org/schemas/net/realtek,rtl8152.yaml#\n+$schema: http://devicetree.org/meta-schemas/core.yaml#\n+\n+title: Realtek RTL8152/RTL8153 series USB ethernet\n+\n+maintainers:\n+  - David Bauer <mail@david-bauer.net>\n+\n+properties:\n+  compatible:\n+    oneOf:\n+      - items:\n+          - enum:\n+              - realtek,rtl8152\n+              - realtek,rtl8153\n+\n+  reg:\n+    description: The device number on the USB bus\n+\n+  realtek,led-data:\n+    description: Value to be written to the LED configuration register.\n+\n+required:\n+  - compatible\n+  - reg\n+\n+examples:\n+  - |\n+    usb-eth@2 {\n+      compatible = \"realtek,rtl8153\";\n+      reg = <2>;\n+      realtek,led-data = <0x87>;\n+    };\n\\ No newline at end of file\n"
  },
  {
    "path": "target/linux/generic/hack-5.10/773-bgmac-add-srab-switch.patch",
    "content": "From 3cb240533ab787899dc7f17aa7d6c5b4810e2e58 Mon Sep 17 00:00:00 2001\nFrom: Hauke Mehrtens <hauke@hauke-m.de>\nDate: Fri, 7 Jul 2017 17:26:01 +0200\nSubject: bcm53xx: bgmac: use srab switch driver\n\nuse the srab switch driver on these SoCs.\n\nSigned-off-by: Hauke Mehrtens <hauke@hauke-m.de>\n---\n drivers/net/ethernet/broadcom/bgmac-bcma.c |  1 +\n drivers/net/ethernet/broadcom/bgmac.c      | 24 ++++++++++++++++++++++++\n drivers/net/ethernet/broadcom/bgmac.h      |  4 ++++\n 3 files changed, 29 insertions(+)\n\n--- a/drivers/net/ethernet/broadcom/bgmac-bcma.c\n+++ b/drivers/net/ethernet/broadcom/bgmac-bcma.c\n@@ -280,6 +280,7 @@ static int bgmac_probe(struct bcma_devic\n \t\tbgmac->feature_flags |= BGMAC_FEAT_CLKCTLST;\n \t\tbgmac->feature_flags |= BGMAC_FEAT_NO_RESET;\n \t\tbgmac->feature_flags |= BGMAC_FEAT_FORCE_SPEED_2500;\n+\t\tbgmac->feature_flags |= BGMAC_FEAT_SRAB;\n \t\tbreak;\n \tdefault:\n \t\tbgmac->feature_flags |= BGMAC_FEAT_CLKCTLST;\n--- a/drivers/net/ethernet/broadcom/bgmac.c\n+++ b/drivers/net/ethernet/broadcom/bgmac.c\n@@ -12,6 +12,7 @@\n #include <linux/bcma/bcma.h>\n #include <linux/etherdevice.h>\n #include <linux/interrupt.h>\n+#include <linux/platform_data/b53.h>\n #include <linux/bcm47xx_nvram.h>\n #include <linux/phy.h>\n #include <linux/phy_fixed.h>\n@@ -1408,6 +1409,17 @@ static const struct ethtool_ops bgmac_et\n \t.set_link_ksettings     = phy_ethtool_set_link_ksettings,\n };\n \n+static struct b53_platform_data bgmac_b53_pdata = {\n+};\n+\n+static struct platform_device bgmac_b53_dev = {\n+\t.name\t\t= \"b53-srab-switch\",\n+\t.id\t\t= -1,\n+\t.dev\t\t= {\n+\t\t.platform_data = &bgmac_b53_pdata,\n+\t},\n+};\n+\n /**************************************************\n  * MII\n  **************************************************/\n@@ -1542,6 +1554,14 @@ int bgmac_enet_probe(struct bgmac *bgmac\n \t/* Omit FCS from max MTU size */\n \tnet_dev->max_mtu = BGMAC_RX_MAX_FRAME_SIZE - ETH_FCS_LEN;\n \n+\tif ((bgmac->feature_flags & BGMAC_FEAT_SRAB) && !bgmac_b53_pdata.regs) {\n+\t\tbgmac_b53_pdata.regs = ioremap(0x18007000, 0x1000);\n+\n+\t\terr = platform_device_register(&bgmac_b53_dev);\n+\t\tif (!err)\n+\t\t\tbgmac->b53_device = &bgmac_b53_dev;\n+\t}\n+\n \terr = register_netdev(bgmac->net_dev);\n \tif (err) {\n \t\tdev_err(bgmac->dev, \"Cannot register net device\\n\");\n@@ -1564,6 +1584,10 @@ EXPORT_SYMBOL_GPL(bgmac_enet_probe);\n \n void bgmac_enet_remove(struct bgmac *bgmac)\n {\n+\tif (bgmac->b53_device)\n+\t\tplatform_device_unregister(&bgmac_b53_dev);\n+\tbgmac->b53_device = NULL;\n+\n \tunregister_netdev(bgmac->net_dev);\n \tphy_disconnect(bgmac->net_dev->phydev);\n \tnetif_napi_del(&bgmac->napi);\n--- a/drivers/net/ethernet/broadcom/bgmac.h\n+++ b/drivers/net/ethernet/broadcom/bgmac.h\n@@ -428,6 +428,7 @@\n #define BGMAC_FEAT_CC4_IF_SW_TYPE_RGMII\tBIT(18)\n #define BGMAC_FEAT_CC7_IF_TYPE_RGMII\tBIT(19)\n #define BGMAC_FEAT_IDM_MASK\t\tBIT(20)\n+#define BGMAC_FEAT_SRAB\t\t\tBIT(21)\n \n struct bgmac_slot_info {\n \tunion {\n@@ -533,6 +534,9 @@ struct bgmac {\n \tvoid (*cmn_maskset32)(struct bgmac *bgmac, u16 offset, u32 mask,\n \t\t\t      u32 set);\n \tint (*phy_connect)(struct bgmac *bgmac);\n+\n+\t/* platform device for associated switch */\n+\tstruct platform_device *b53_device;\n };\n \n struct bgmac *bgmac_alloc(struct device *dev);\n"
  },
  {
    "path": "target/linux/generic/hack-5.10/780-usb-net-MeigLink_modem_support.patch",
    "content": "--- a/drivers/net/usb/qmi_wwan.c\n+++ b/drivers/net/usb/qmi_wwan.c\n@@ -1024,6 +1024,7 @@ static const struct usb_device_id produc\n \t{QMI_MATCH_FF_FF_FF(0x2c7c, 0x0512)},\t/* Quectel EG12/EM12 */\n \t{QMI_MATCH_FF_FF_FF(0x2c7c, 0x0620)},\t/* Quectel EM160R-GL */\n \t{QMI_MATCH_FF_FF_FF(0x2c7c, 0x0800)},\t/* Quectel RM500Q-GL */\n+\t{QMI_MATCH_FF_FF_FF(0x05c6, 0xf601)},   /* MeigLink SLM750 */\n \n \t/* 3. Combined interface devices matching on interface number */\n \t{QMI_FIXED_INTF(0x0408, 0xea42, 4)},\t/* Yota / Megafon M100-1 */\n--- a/drivers/usb/serial/option.c\n+++ b/drivers/usb/serial/option.c\n@@ -243,6 +243,8 @@ static void option_instat_callback(struc\n #define UBLOX_PRODUCT_R6XX\t\t\t0x90fa\n /* These Yuga products use Qualcomm's vendor ID */\n #define YUGA_PRODUCT_CLM920_NC5\t\t\t0x9625\n+/* These MeigLink products use Qualcomm's vendor ID */\n+#define MEIGLINK_PRODUCT_SLM750\t\t\t0xf601\n \n #define QUECTEL_VENDOR_ID\t\t\t0x2c7c\n /* These Quectel products use Quectel's vendor ID */\n@@ -1127,6 +1129,11 @@ static const struct usb_device_id option\n \t{ USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_EG95, 0xff, 0, 0) },\n \t{ USB_DEVICE(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_BG96),\n \t  .driver_info = RSVD(4) },\n+\t/* Meiglink products using Qualcomm vendor ID */\n+\t// Works OK. In case of some issues check macros that are used by Quectel Products\n+\t{ USB_DEVICE_AND_INTERFACE_INFO(QUALCOMM_VENDOR_ID, MEIGLINK_PRODUCT_SLM750, 0xff, 0xff, 0xff),\n+\t  .driver_info = NUMEP2 },\n+\t{ USB_DEVICE_AND_INTERFACE_INFO(QUALCOMM_VENDOR_ID, MEIGLINK_PRODUCT_SLM750, 0xff, 0, 0) },\n \t{ USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_EP06, 0xff, 0xff, 0xff),\n \t  .driver_info = RSVD(1) | RSVD(2) | RSVD(3) | RSVD(4) | NUMEP2 },\n \t{ USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_EP06, 0xff, 0, 0) },\n"
  },
  {
    "path": "target/linux/generic/hack-5.10/800-GPIO-add-named-gpio-exports.patch",
    "content": "From cc809a441d8f2924f785eb863dfa6aef47a25b0b Mon Sep 17 00:00:00 2001\nFrom: John Crispin <blogic@openwrt.org>\nDate: Tue, 12 Aug 2014 20:49:27 +0200\nSubject: [PATCH 30/36] GPIO: add named gpio exports\n\nSigned-off-by: John Crispin <blogic@openwrt.org>\n--- a/drivers/gpio/gpiolib-of.c\n+++ b/drivers/gpio/gpiolib-of.c\n@@ -19,6 +19,8 @@\n #include <linux/pinctrl/pinctrl.h>\n #include <linux/slab.h>\n #include <linux/gpio/machine.h>\n+#include <linux/init.h>\n+#include <linux/platform_device.h>\n \n #include \"gpiolib.h\"\n #include \"gpiolib-of.h\"\n@@ -1039,3 +1041,72 @@ void of_gpiochip_remove(struct gpio_chip\n {\n \tof_node_put(chip->of_node);\n }\n+\n+#ifdef CONFIG_GPIO_SYSFS\n+\n+static struct of_device_id gpio_export_ids[] = {\n+\t{ .compatible = \"gpio-export\" },\n+\t{ /* sentinel */ }\n+};\n+\n+static int of_gpio_export_probe(struct platform_device *pdev)\n+{\n+\tstruct device_node *np = pdev->dev.of_node;\n+\tstruct device_node *cnp;\n+\tu32 val;\n+\tint nb = 0;\n+\n+\tfor_each_child_of_node(np, cnp) {\n+\t\tconst char *name = NULL;\n+\t\tint gpio;\n+\t\tbool dmc;\n+\t\tint max_gpio = 1;\n+\t\tint i;\n+\n+\t\tof_property_read_string(cnp, \"gpio-export,name\", &name);\n+\n+\t\tif (!name)\n+\t\t\tmax_gpio = of_gpio_count(cnp);\n+\n+\t\tfor (i = 0; i < max_gpio; i++) {\n+\t\t\tunsigned flags = 0;\n+\t\t\tenum of_gpio_flags of_flags;\n+\n+\t\t\tgpio = of_get_gpio_flags(cnp, i, &of_flags);\n+\t\t\tif (!gpio_is_valid(gpio))\n+\t\t\t\treturn gpio;\n+\n+\t\t\tif (of_flags == OF_GPIO_ACTIVE_LOW)\n+\t\t\t\tflags |= GPIOF_ACTIVE_LOW;\n+\n+\t\t\tif (!of_property_read_u32(cnp, \"gpio-export,output\", &val))\n+\t\t\t\tflags |= val ? GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW;\n+\t\t\telse\n+\t\t\t\tflags |= GPIOF_IN;\n+\n+\t\t\tif (devm_gpio_request_one(&pdev->dev, gpio, flags, name ? name : of_node_full_name(np)))\n+\t\t\t\tcontinue;\n+\n+\t\t\tdmc = of_property_read_bool(cnp, \"gpio-export,direction_may_change\");\n+\t\t\tgpio_export_with_name(gpio, dmc, name);\n+\t\t\tnb++;\n+\t\t}\n+\t}\n+\n+\tdev_info(&pdev->dev, \"%d gpio(s) exported\\n\", nb);\n+\n+\treturn 0;\n+}\n+\n+static struct platform_driver gpio_export_driver = {\n+\t.driver\t\t= {\n+\t\t.name\t\t= \"gpio-export\",\n+\t\t.owner\t= THIS_MODULE,\n+\t\t.of_match_table\t= of_match_ptr(gpio_export_ids),\n+\t},\n+\t.probe\t\t= of_gpio_export_probe,\n+};\n+\n+module_platform_driver(gpio_export_driver);\n+\n+#endif\n--- a/include/asm-generic/gpio.h\n+++ b/include/asm-generic/gpio.h\n@@ -125,6 +125,12 @@ static inline int gpio_export(unsigned g\n \treturn gpiod_export(gpio_to_desc(gpio), direction_may_change);\n }\n \n+int __gpiod_export(struct gpio_desc *desc, bool direction_may_change, const char *name);\n+static inline int gpio_export_with_name(unsigned gpio, bool direction_may_change, const char *name)\n+{\n+\treturn __gpiod_export(gpio_to_desc(gpio), direction_may_change, name);\n+}\n+\n static inline int gpio_export_link(struct device *dev, const char *name,\n \t\t\t\t   unsigned gpio)\n {\n--- a/include/linux/gpio/consumer.h\n+++ b/include/linux/gpio/consumer.h\n@@ -715,6 +715,7 @@ static inline void devm_acpi_dev_remove_\n \n #if IS_ENABLED(CONFIG_GPIOLIB) && IS_ENABLED(CONFIG_GPIO_SYSFS)\n \n+int _gpiod_export(struct gpio_desc *desc, bool direction_may_change, const char *name);\n int gpiod_export(struct gpio_desc *desc, bool direction_may_change);\n int gpiod_export_link(struct device *dev, const char *name,\n \t\t      struct gpio_desc *desc);\n@@ -722,6 +723,13 @@ void gpiod_unexport(struct gpio_desc *de\n \n #else  /* CONFIG_GPIOLIB && CONFIG_GPIO_SYSFS */\n \n+static inline int _gpiod_export(struct gpio_desc *desc,\n+\t\t\t       bool direction_may_change,\n+\t\t\t       const char *name)\n+{\n+\treturn -ENOSYS;\n+}\n+\n static inline int gpiod_export(struct gpio_desc *desc,\n \t\t\t       bool direction_may_change)\n {\n--- a/drivers/gpio/gpiolib-sysfs.c\n+++ b/drivers/gpio/gpiolib-sysfs.c\n@@ -572,7 +572,7 @@ static struct class gpio_class = {\n  *\n  * Returns zero on success, else an error.\n  */\n-int gpiod_export(struct gpio_desc *desc, bool direction_may_change)\n+int __gpiod_export(struct gpio_desc *desc, bool direction_may_change, const char *name)\n {\n \tstruct gpio_chip\t*chip;\n \tstruct gpio_device\t*gdev;\n@@ -634,6 +634,8 @@ int gpiod_export(struct gpio_desc *desc,\n \toffset = gpio_chip_hwgpio(desc);\n \tif (chip->names && chip->names[offset])\n \t\tioname = chip->names[offset];\n+\tif (name)\n+\t\tioname = name;\n \n \tdev = device_create_with_groups(&gpio_class, &gdev->dev,\n \t\t\t\t\tMKDEV(0, 0), data, gpio_groups,\n@@ -655,6 +657,12 @@ err_unlock:\n \tgpiod_dbg(desc, \"%s: status %d\\n\", __func__, status);\n \treturn status;\n }\n+EXPORT_SYMBOL_GPL(__gpiod_export);\n+\n+int gpiod_export(struct gpio_desc *desc, bool direction_may_change)\n+{\n+\treturn __gpiod_export(desc, direction_may_change, NULL);\n+}\n EXPORT_SYMBOL_GPL(gpiod_export);\n \n static int match_export(struct device *dev, const void *desc)\n"
  },
  {
    "path": "target/linux/generic/hack-5.10/901-debloat_sock_diag.patch",
    "content": "From 3b6115d6b57a263bdc8c9b1df273bd4a7955eead Mon Sep 17 00:00:00 2001\nFrom: Felix Fietkau <nbd@nbd.name>\nDate: Sat, 8 Jul 2017 08:16:31 +0200\nSubject: debloat: add some debloat patches, strip down procfs and make O_DIRECT support optional, saves ~15K after lzma on MIPS\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n net/Kconfig         | 3 +++\n net/core/Makefile   | 3 ++-\n net/core/sock.c     | 2 ++\n net/ipv4/Kconfig    | 1 +\n net/netlink/Kconfig | 1 +\n net/packet/Kconfig  | 1 +\n net/unix/Kconfig    | 1 +\n 7 files changed, 11 insertions(+), 1 deletion(-)\n\n--- a/net/Kconfig\n+++ b/net/Kconfig\n@@ -104,6 +104,9 @@ source \"net/mptcp/Kconfig\"\n \n endif # if INET\n \n+config SOCK_DIAG\n+\tbool\n+\n config NETWORK_SECMARK\n \tbool \"Security Marking\"\n \thelp\n--- a/net/core/Makefile\n+++ b/net/core/Makefile\n@@ -10,9 +10,10 @@ obj-$(CONFIG_SYSCTL) += sysctl_net_core.\n \n obj-y\t\t     += dev.o dev_addr_lists.o dst.o netevent.o \\\n \t\t\tneighbour.o rtnetlink.o utils.o link_watch.o filter.o \\\n-\t\t\tsock_diag.o dev_ioctl.o tso.o sock_reuseport.o \\\n+ \t\t\tdev_ioctl.o tso.o sock_reuseport.o \\\n \t\t\tfib_notifier.o xdp.o flow_offload.o\n \n+obj-$(CONFIG_SOCK_DIAG) += sock_diag.o\n obj-y += net-sysfs.o\n obj-$(CONFIG_PAGE_POOL) += page_pool.o\n obj-$(CONFIG_PROC_FS) += net-procfs.o\n--- a/net/core/sock.c\n+++ b/net/core/sock.c\n@@ -114,6 +114,7 @@\n #include <linux/memcontrol.h>\n #include <linux/prefetch.h>\n #include <linux/compat.h>\n+#include <linux/cookie.h>\n \n #include <linux/uaccess.h>\n \n@@ -141,6 +142,7 @@\n \n static DEFINE_MUTEX(proto_list_mutex);\n static LIST_HEAD(proto_list);\n+DEFINE_COOKIE(sock_cookie);\n \n static void sock_inuse_add(struct net *net, int val);\n \n@@ -526,6 +528,18 @@ discard_and_relse:\n }\n EXPORT_SYMBOL(__sk_receive_skb);\n \n+u64 __sock_gen_cookie(struct sock *sk)\n+{\n+\twhile (1) {\n+\t\tu64 res = atomic64_read(&sk->sk_cookie);\n+\n+\t\tif (res)\n+\t\t\treturn res;\n+\t\tres = gen_cookie_next(&sock_cookie);\n+\t\tatomic64_cmpxchg(&sk->sk_cookie, 0, res);\n+\t}\n+}\n+\n struct dst_entry *__sk_dst_check(struct sock *sk, u32 cookie)\n {\n \tstruct dst_entry *dst = __sk_dst_get(sk);\n@@ -1834,9 +1848,11 @@ static void __sk_free(struct sock *sk)\n \tif (likely(sk->sk_net_refcnt))\n \t\tsock_inuse_add(sock_net(sk), -1);\n \n+#ifdef CONFIG_SOCK_DIAG\n \tif (unlikely(sk->sk_net_refcnt && sock_diag_has_destroy_listeners(sk)))\n \t\tsock_diag_broadcast_destroy(sk);\n \telse\n+#endif\n \t\tsk_destruct(sk);\n }\n \n--- a/net/core/sock_diag.c\n+++ b/net/core/sock_diag.c\n@@ -11,7 +11,6 @@\n #include <linux/tcp.h>\n #include <linux/workqueue.h>\n #include <linux/nospec.h>\n-#include <linux/cookie.h>\n #include <linux/inet_diag.h>\n #include <linux/sock_diag.h>\n \n@@ -20,20 +19,6 @@ static int (*inet_rcv_compat)(struct sk_\n static DEFINE_MUTEX(sock_diag_table_mutex);\n static struct workqueue_struct *broadcast_wq;\n \n-DEFINE_COOKIE(sock_cookie);\n-\n-u64 __sock_gen_cookie(struct sock *sk)\n-{\n-\twhile (1) {\n-\t\tu64 res = atomic64_read(&sk->sk_cookie);\n-\n-\t\tif (res)\n-\t\t\treturn res;\n-\t\tres = gen_cookie_next(&sock_cookie);\n-\t\tatomic64_cmpxchg(&sk->sk_cookie, 0, res);\n-\t}\n-}\n-\n int sock_diag_check_cookie(struct sock *sk, const __u32 *cookie)\n {\n \tu64 res;\n--- a/net/ipv4/Kconfig\n+++ b/net/ipv4/Kconfig\n@@ -414,6 +414,7 @@ config INET_TUNNEL\n \n config INET_DIAG\n \ttristate \"INET: socket monitoring interface\"\n+\tselect SOCK_DIAG\n \tdefault y\n \thelp\n \t  Support for INET (TCP, DCCP, etc) socket monitoring interface used by\n--- a/net/netlink/Kconfig\n+++ b/net/netlink/Kconfig\n@@ -5,6 +5,7 @@\n \n config NETLINK_DIAG\n \ttristate \"NETLINK: socket monitoring interface\"\n+\tselect SOCK_DIAG\n \tdefault n\n \thelp\n \t  Support for NETLINK socket monitoring interface used by the ss tool.\n--- a/net/packet/Kconfig\n+++ b/net/packet/Kconfig\n@@ -19,6 +19,7 @@ config PACKET\n config PACKET_DIAG\n \ttristate \"Packet: sockets monitoring interface\"\n \tdepends on PACKET\n+\tselect SOCK_DIAG\n \tdefault n\n \thelp\n \t  Support for PF_PACKET sockets monitoring interface used by the ss tool.\n--- a/net/unix/Kconfig\n+++ b/net/unix/Kconfig\n@@ -28,6 +28,7 @@ config UNIX_SCM\n config UNIX_DIAG\n \ttristate \"UNIX: socket monitoring interface\"\n \tdepends on UNIX\n+\tselect SOCK_DIAG\n \tdefault n\n \thelp\n \t  Support for UNIX socket monitoring interface used by the ss tool.\n"
  },
  {
    "path": "target/linux/generic/hack-5.10/902-debloat_proc.patch",
    "content": "From 9e3f1d0805b2d919904dd9a4ff0d956314cc3cba Mon Sep 17 00:00:00 2001\nFrom: Felix Fietkau <nbd@nbd.name>\nDate: Sat, 8 Jul 2017 08:20:09 +0200\nSubject: debloat: procfs\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n fs/locks.c               |  2 ++\n fs/proc/Kconfig          |  5 +++++\n fs/proc/consoles.c       |  3 +++\n fs/proc/proc_tty.c       | 11 ++++++++++-\n include/net/snmp.h       | 18 +++++++++++++++++-\n ipc/msg.c                |  3 +++\n ipc/sem.c                |  2 ++\n ipc/shm.c                |  2 ++\n ipc/util.c               |  3 +++\n kernel/exec_domain.c     |  2 ++\n kernel/irq/proc.c        |  9 +++++++++\n kernel/time/timer_list.c |  2 ++\n mm/vmalloc.c             |  2 ++\n mm/vmstat.c              |  8 +++++---\n net/8021q/vlanproc.c     |  6 ++++++\n net/core/net-procfs.c    | 18 ++++++++++++------\n net/core/sock.c          |  2 ++\n net/ipv4/fib_trie.c      | 18 ++++++++++++------\n net/ipv4/proc.c          |  3 +++\n net/ipv4/route.c         |  3 +++\n 20 files changed, 105 insertions(+), 17 deletions(-)\n\n--- a/fs/locks.c\n+++ b/fs/locks.c\n@@ -2993,6 +2993,8 @@ static const struct seq_operations locks\n \n static int __init proc_locks_init(void)\n {\n+\tif (IS_ENABLED(CONFIG_PROC_STRIPPED))\n+\t\treturn 0;\n \tproc_create_seq_private(\"locks\", 0, NULL, &locks_seq_operations,\n \t\t\tsizeof(struct locks_iterator), NULL);\n \treturn 0;\n--- a/fs/proc/Kconfig\n+++ b/fs/proc/Kconfig\n@@ -100,6 +100,11 @@ config PROC_CHILDREN\n \t  Say Y if you are running any user-space software which takes benefit from\n \t  this interface. For example, rkt is such a piece of software.\n \n+config PROC_STRIPPED\n+\tdefault n\n+\tdepends on EXPERT\n+\tbool \"Strip non-essential /proc functionality to reduce code size\"\n+\n config PROC_PID_ARCH_STATUS\n \tdef_bool n\n \tdepends on PROC_FS\n--- a/fs/proc/consoles.c\n+++ b/fs/proc/consoles.c\n@@ -92,6 +92,9 @@ static const struct seq_operations conso\n \n static int __init proc_consoles_init(void)\n {\n+\tif (IS_ENABLED(CONFIG_PROC_STRIPPED))\n+\t\treturn 0;\n+\n \tproc_create_seq(\"consoles\", 0, NULL, &consoles_op);\n \treturn 0;\n }\n--- a/fs/proc/proc_tty.c\n+++ b/fs/proc/proc_tty.c\n@@ -133,7 +133,10 @@ static const struct seq_operations tty_d\n void proc_tty_register_driver(struct tty_driver *driver)\n {\n \tstruct proc_dir_entry *ent;\n-\t\t\n+\n+\tif (IS_ENABLED(CONFIG_PROC_STRIPPED))\n+\t\treturn;\n+\n \tif (!driver->driver_name || driver->proc_entry ||\n \t    !driver->ops->proc_show)\n \t\treturn;\n@@ -150,6 +153,9 @@ void proc_tty_unregister_driver(struct t\n {\n \tstruct proc_dir_entry *ent;\n \n+\tif (IS_ENABLED(CONFIG_PROC_STRIPPED))\n+\t\treturn;\n+\n \tent = driver->proc_entry;\n \tif (!ent)\n \t\treturn;\n@@ -164,6 +170,9 @@ void proc_tty_unregister_driver(struct t\n  */\n void __init proc_tty_init(void)\n {\n+\tif (IS_ENABLED(CONFIG_PROC_STRIPPED))\n+\t\treturn;\n+\n \tif (!proc_mkdir(\"tty\", NULL))\n \t\treturn;\n \tproc_mkdir(\"tty/ldisc\", NULL);\t/* Preserved: it's userspace visible */\n--- a/include/net/snmp.h\n+++ b/include/net/snmp.h\n@@ -124,6 +124,21 @@ struct linux_tls_mib {\n #define DECLARE_SNMP_STAT(type, name)\t\\\n \textern __typeof__(type) __percpu *name\n \n+#ifdef CONFIG_PROC_STRIPPED\n+#define __SNMP_STATS_DUMMY(mib)\t\\\n+\tdo { (void) mib->mibs[0]; } while(0)\n+\n+#define __SNMP_INC_STATS(mib, field) __SNMP_STATS_DUMMY(mib)\n+#define SNMP_INC_STATS_ATOMIC_LONG(mib, field) __SNMP_STATS_DUMMY(mib)\n+#define SNMP_INC_STATS(mib, field) __SNMP_STATS_DUMMY(mib)\n+#define SNMP_DEC_STATS(mib, field) __SNMP_STATS_DUMMY(mib)\n+#define __SNMP_ADD_STATS(mib, field, addend) __SNMP_STATS_DUMMY(mib)\n+#define SNMP_ADD_STATS(mib, field, addend) __SNMP_STATS_DUMMY(mib)\n+#define SNMP_UPD_PO_STATS(mib, basefield, addend) __SNMP_STATS_DUMMY(mib)\n+#define __SNMP_UPD_PO_STATS(mib, basefield, addend) __SNMP_STATS_DUMMY(mib)\n+\n+#else\n+\n #define __SNMP_INC_STATS(mib, field)\t\\\n \t\t\t__this_cpu_inc(mib->mibs[field])\n \n@@ -154,8 +169,9 @@ struct linux_tls_mib {\n \t\t__this_cpu_add(ptr[basefield##OCTETS], addend);\t\\\n \t} while (0)\n \n+#endif\n \n-#if BITS_PER_LONG==32\n+#if (BITS_PER_LONG==32) && !defined(CONFIG_PROC_STRIPPED)\n \n #define __SNMP_ADD_STATS64(mib, field, addend) \t\t\t\t\\\n \tdo {\t\t\t\t\t\t\t\t\\\n--- a/ipc/msg.c\n+++ b/ipc/msg.c\n@@ -1350,6 +1350,9 @@ void __init msg_init(void)\n {\n \tmsg_init_ns(&init_ipc_ns);\n \n+\tif (IS_ENABLED(CONFIG_PROC_STRIPPED))\n+\t\treturn;\n+\n \tipc_init_proc_interface(\"sysvipc/msg\",\n \t\t\t\t\"       key      msqid perms      cbytes       qnum lspid lrpid   uid   gid  cuid  cgid      stime      rtime      ctime\\n\",\n \t\t\t\tIPC_MSG_IDS, sysvipc_msg_proc_show);\n--- a/ipc/sem.c\n+++ b/ipc/sem.c\n@@ -266,6 +266,8 @@ void sem_exit_ns(struct ipc_namespace *n\n void __init sem_init(void)\n {\n \tsem_init_ns(&init_ipc_ns);\n+\tif (IS_ENABLED(CONFIG_PROC_STRIPPED))\n+\t\treturn;\n \tipc_init_proc_interface(\"sysvipc/sem\",\n \t\t\t\t\"       key      semid perms      nsems   uid   gid  cuid  cgid      otime      ctime\\n\",\n \t\t\t\tIPC_SEM_IDS, sysvipc_sem_proc_show);\n--- a/ipc/shm.c\n+++ b/ipc/shm.c\n@@ -154,6 +154,8 @@ pure_initcall(ipc_ns_init);\n \n void __init shm_init(void)\n {\n+\tif (IS_ENABLED(CONFIG_PROC_STRIPPED))\n+\t\treturn;\n \tipc_init_proc_interface(\"sysvipc/shm\",\n #if BITS_PER_LONG <= 32\n \t\t\t\t\"       key      shmid perms       size  cpid  lpid nattch   uid   gid  cuid  cgid      atime      dtime      ctime        rss       swap\\n\",\n--- a/ipc/util.c\n+++ b/ipc/util.c\n@@ -140,6 +140,9 @@ void __init ipc_init_proc_interface(cons\n \tstruct proc_dir_entry *pde;\n \tstruct ipc_proc_iface *iface;\n \n+\tif (IS_ENABLED(CONFIG_PROC_STRIPPED))\n+\t\treturn;\n+\n \tiface = kmalloc(sizeof(*iface), GFP_KERNEL);\n \tif (!iface)\n \t\treturn;\n--- a/kernel/exec_domain.c\n+++ b/kernel/exec_domain.c\n@@ -29,6 +29,8 @@ static int execdomains_proc_show(struct\n \n static int __init proc_execdomains_init(void)\n {\n+\tif (IS_ENABLED(CONFIG_PROC_STRIPPED))\n+\t\treturn 0;\n \tproc_create_single(\"execdomains\", 0, NULL, execdomains_proc_show);\n \treturn 0;\n }\n--- a/kernel/irq/proc.c\n+++ b/kernel/irq/proc.c\n@@ -341,6 +341,9 @@ void register_irq_proc(unsigned int irq,\n \tvoid __maybe_unused *irqp = (void *)(unsigned long) irq;\n \tchar name [MAX_NAMELEN];\n \n+\tif (IS_ENABLED(CONFIG_PROC_STRIPPED) && !IS_ENABLED(CONFIG_SMP))\n+\t\treturn;\n+\n \tif (!root_irq_dir || (desc->irq_data.chip == &no_irq_chip))\n \t\treturn;\n \n@@ -394,6 +397,9 @@ void unregister_irq_proc(unsigned int ir\n {\n \tchar name [MAX_NAMELEN];\n \n+\tif (IS_ENABLED(CONFIG_PROC_STRIPPED) && !IS_ENABLED(CONFIG_SMP))\n+\t\treturn;\n+\n \tif (!root_irq_dir || !desc->dir)\n \t\treturn;\n #ifdef CONFIG_SMP\n@@ -432,6 +438,9 @@ void init_irq_proc(void)\n \tunsigned int irq;\n \tstruct irq_desc *desc;\n \n+\tif (IS_ENABLED(CONFIG_PROC_STRIPPED) && !IS_ENABLED(CONFIG_SMP))\n+\t\treturn;\n+\n \t/* create /proc/irq */\n \troot_irq_dir = proc_mkdir(\"irq\", NULL);\n \tif (!root_irq_dir)\n--- a/kernel/time/timer_list.c\n+++ b/kernel/time/timer_list.c\n@@ -370,6 +370,8 @@ static int __init init_timer_list_procfs\n {\n \tstruct proc_dir_entry *pe;\n \n+\tif (IS_ENABLED(CONFIG_PROC_STRIPPED))\n+\t\treturn 0;\n \tpe = proc_create_seq_private(\"timer_list\", 0400, NULL, &timer_list_sops,\n \t\t\tsizeof(struct timer_list_iter), NULL);\n \tif (!pe)\n--- a/mm/vmalloc.c\n+++ b/mm/vmalloc.c\n@@ -3572,6 +3572,8 @@ static const struct seq_operations vmall\n \n static int __init proc_vmalloc_init(void)\n {\n+\tif (IS_ENABLED(CONFIG_PROC_STRIPPED))\n+\t\treturn 0;\n \tif (IS_ENABLED(CONFIG_NUMA))\n \t\tproc_create_seq_private(\"vmallocinfo\", 0400, NULL,\n \t\t\t\t&vmalloc_op,\n--- a/mm/vmstat.c\n+++ b/mm/vmstat.c\n@@ -2044,10 +2044,12 @@ void __init init_mm_internals(void)\n \tstart_shepherd_timer();\n #endif\n #ifdef CONFIG_PROC_FS\n-\tproc_create_seq(\"buddyinfo\", 0444, NULL, &fragmentation_op);\n-\tproc_create_seq(\"pagetypeinfo\", 0400, NULL, &pagetypeinfo_op);\n+\tif (!IS_ENABLED(CONFIG_PROC_STRIPPED)) {\n+\t\tproc_create_seq(\"buddyinfo\", 0444, NULL, &fragmentation_op);\n+\t\tproc_create_seq(\"pagetypeinfo\", 0400, NULL, &pagetypeinfo_op);\n+\t\tproc_create_seq(\"zoneinfo\", 0444, NULL, &zoneinfo_op);\n+\t}\n \tproc_create_seq(\"vmstat\", 0444, NULL, &vmstat_op);\n-\tproc_create_seq(\"zoneinfo\", 0444, NULL, &zoneinfo_op);\n #endif\n }\n \n--- a/net/8021q/vlanproc.c\n+++ b/net/8021q/vlanproc.c\n@@ -93,6 +93,9 @@ void vlan_proc_cleanup(struct net *net)\n {\n \tstruct vlan_net *vn = net_generic(net, vlan_net_id);\n \n+\tif (IS_ENABLED(CONFIG_PROC_STRIPPED))\n+\t\treturn;\n+\n \tif (vn->proc_vlan_conf)\n \t\tremove_proc_entry(name_conf, vn->proc_vlan_dir);\n \n@@ -112,6 +115,9 @@ int __net_init vlan_proc_init(struct net\n {\n \tstruct vlan_net *vn = net_generic(net, vlan_net_id);\n \n+\tif (IS_ENABLED(CONFIG_PROC_STRIPPED))\n+\t\treturn 0;\n+\n \tvn->proc_vlan_dir = proc_net_mkdir(net, name_root, net->proc_net);\n \tif (!vn->proc_vlan_dir)\n \t\tgoto err;\n--- a/net/core/net-procfs.c\n+++ b/net/core/net-procfs.c\n@@ -320,10 +320,12 @@ static int __net_init dev_proc_net_init(\n \tif (!proc_create_net(\"dev\", 0444, net->proc_net, &dev_seq_ops,\n \t\t\tsizeof(struct seq_net_private)))\n \t\tgoto out;\n-\tif (!proc_create_seq(\"softnet_stat\", 0444, net->proc_net,\n+\tif (!IS_ENABLED(CONFIG_PROC_STRIPPED) &&\n+\t\t\t!proc_create_seq(\"softnet_stat\", 0444, net->proc_net,\n \t\t\t &softnet_seq_ops))\n \t\tgoto out_dev;\n-\tif (!proc_create_net(\"ptype\", 0444, net->proc_net, &ptype_seq_ops,\n+\tif (!IS_ENABLED(CONFIG_PROC_STRIPPED) &&\n+\t\t\t!proc_create_net(\"ptype\", 0444, net->proc_net, &ptype_seq_ops,\n \t\t\tsizeof(struct seq_net_private)))\n \t\tgoto out_softnet;\n \n@@ -333,9 +335,11 @@ static int __net_init dev_proc_net_init(\n out:\n \treturn rc;\n out_ptype:\n-\tremove_proc_entry(\"ptype\", net->proc_net);\n+\tif (!IS_ENABLED(CONFIG_PROC_STRIPPED))\n+\t\tremove_proc_entry(\"ptype\", net->proc_net);\n out_softnet:\n-\tremove_proc_entry(\"softnet_stat\", net->proc_net);\n+\tif (!IS_ENABLED(CONFIG_PROC_STRIPPED))\n+\t\tremove_proc_entry(\"softnet_stat\", net->proc_net);\n out_dev:\n \tremove_proc_entry(\"dev\", net->proc_net);\n \tgoto out;\n@@ -345,8 +349,10 @@ static void __net_exit dev_proc_net_exit\n {\n \twext_proc_exit(net);\n \n-\tremove_proc_entry(\"ptype\", net->proc_net);\n-\tremove_proc_entry(\"softnet_stat\", net->proc_net);\n+\tif (!IS_ENABLED(CONFIG_PROC_STRIPPED)) {\n+\t\tremove_proc_entry(\"ptype\", net->proc_net);\n+\t\tremove_proc_entry(\"softnet_stat\", net->proc_net);\n+\t}\n \tremove_proc_entry(\"dev\", net->proc_net);\n }\n \n--- a/net/core/sock.c\n+++ b/net/core/sock.c\n@@ -3699,6 +3699,8 @@ static __net_initdata struct pernet_oper\n \n static int __init proto_init(void)\n {\n+\tif (IS_ENABLED(CONFIG_PROC_STRIPPED))\n+\t\treturn 0;\n \treturn register_pernet_subsys(&proto_net_ops);\n }\n \n--- a/net/ipv4/fib_trie.c\n+++ b/net/ipv4/fib_trie.c\n@@ -2986,11 +2986,13 @@ static const struct seq_operations fib_r\n \n int __net_init fib_proc_init(struct net *net)\n {\n-\tif (!proc_create_net(\"fib_trie\", 0444, net->proc_net, &fib_trie_seq_ops,\n+\tif (!IS_ENABLED(CONFIG_PROC_STRIPPED) &&\n+\t\t\t!proc_create_net(\"fib_trie\", 0444, net->proc_net, &fib_trie_seq_ops,\n \t\t\tsizeof(struct fib_trie_iter)))\n \t\tgoto out1;\n \n-\tif (!proc_create_net_single(\"fib_triestat\", 0444, net->proc_net,\n+\tif (!IS_ENABLED(CONFIG_PROC_STRIPPED) &&\n+\t\t\t!proc_create_net_single(\"fib_triestat\", 0444, net->proc_net,\n \t\t\tfib_triestat_seq_show, NULL))\n \t\tgoto out2;\n \n@@ -3001,17 +3003,21 @@ int __net_init fib_proc_init(struct net\n \treturn 0;\n \n out3:\n-\tremove_proc_entry(\"fib_triestat\", net->proc_net);\n+\tif (!IS_ENABLED(CONFIG_PROC_STRIPPED))\n+\t\tremove_proc_entry(\"fib_triestat\", net->proc_net);\n out2:\n-\tremove_proc_entry(\"fib_trie\", net->proc_net);\n+\tif (!IS_ENABLED(CONFIG_PROC_STRIPPED))\n+\t\tremove_proc_entry(\"fib_trie\", net->proc_net);\n out1:\n \treturn -ENOMEM;\n }\n \n void __net_exit fib_proc_exit(struct net *net)\n {\n-\tremove_proc_entry(\"fib_trie\", net->proc_net);\n-\tremove_proc_entry(\"fib_triestat\", net->proc_net);\n+\tif (!IS_ENABLED(CONFIG_PROC_STRIPPED)) {\n+\t\tremove_proc_entry(\"fib_trie\", net->proc_net);\n+\t\tremove_proc_entry(\"fib_triestat\", net->proc_net);\n+\t}\n \tremove_proc_entry(\"route\", net->proc_net);\n }\n \n--- a/net/ipv4/proc.c\n+++ b/net/ipv4/proc.c\n@@ -528,5 +528,8 @@ static __net_initdata struct pernet_oper\n \n int __init ip_misc_proc_init(void)\n {\n+\tif (IS_ENABLED(CONFIG_PROC_STRIPPED))\n+\t\treturn 0;\n+\n \treturn register_pernet_subsys(&ip_proc_ops);\n }\n--- a/net/ipv4/route.c\n+++ b/net/ipv4/route.c\n@@ -410,6 +410,9 @@ static struct pernet_operations ip_rt_pr\n \n static int __init ip_rt_proc_init(void)\n {\n+\tif (IS_ENABLED(CONFIG_PROC_STRIPPED))\n+\t\treturn 0;\n+\n \treturn register_pernet_subsys(&ip_rt_proc_ops);\n }\n \n"
  },
  {
    "path": "target/linux/generic/hack-5.10/904-debloat_dma_buf.patch",
    "content": "From e3692cb2fcd5ba1244512a0f43b8118f65f1c375 Mon Sep 17 00:00:00 2001\nFrom: Felix Fietkau <nbd@nbd.name>\nDate: Sat, 8 Jul 2017 08:20:43 +0200\nSubject: debloat: dmabuf\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n drivers/base/Kconfig      |  2 +-\n drivers/dma-buf/Makefile  | 10 +++++++---\n drivers/dma-buf/dma-buf.c |  4 +++-\n kernel/sched/core.c       |  1 +\n 4 files changed, 12 insertions(+), 5 deletions(-)\n\n--- a/drivers/base/Kconfig\n+++ b/drivers/base/Kconfig\n@@ -184,7 +184,7 @@ config SOC_BUS\n source \"drivers/base/regmap/Kconfig\"\n \n config DMA_SHARED_BUFFER\n-\tbool\n+\ttristate\n \tdefault n\n \tselect IRQ_WORK\n \thelp\n--- a/drivers/dma-buf/heaps/Makefile\n+++ b/drivers/dma-buf/heaps/Makefile\n@@ -1,4 +1,4 @@\n # SPDX-License-Identifier: GPL-2.0\n-obj-y\t\t\t\t\t+= heap-helpers.o\n-obj-$(CONFIG_DMABUF_HEAPS_SYSTEM)\t+= system_heap.o\n-obj-$(CONFIG_DMABUF_HEAPS_CMA)\t\t+= cma_heap.o\n+dma-buf-objs-y\t\t\t\t\t+= heap-helpers.o\n+dma-buf-objs-$(CONFIG_DMABUF_HEAPS_SYSTEM)\t+= system_heap.o\n+dma-buf-objs-$(CONFIG_DMABUF_HEAPS_CMA)\t\t+= cma_heap.o\n--- a/drivers/dma-buf/Makefile\n+++ b/drivers/dma-buf/Makefile\n@@ -1,15 +1,19 @@\n # SPDX-License-Identifier: GPL-2.0-only\n-obj-y := dma-buf.o dma-fence.o dma-fence-array.o dma-fence-chain.o \\\n+obj-$(CONFIG_DMA_SHARED_BUFFER) := dma-shared-buffer.o\n+\n+dma-buf-objs-y := dma-buf.o dma-fence.o dma-fence-array.o dma-fence-chain.o \\\n \t dma-resv.o seqno-fence.o\n-obj-$(CONFIG_DMABUF_HEAPS)\t+= dma-heap.o\n-obj-$(CONFIG_DMABUF_HEAPS)\t+= heaps/\n-obj-$(CONFIG_SYNC_FILE)\t\t+= sync_file.o\n-obj-$(CONFIG_SW_SYNC)\t\t+= sw_sync.o sync_debug.o\n-obj-$(CONFIG_UDMABUF)\t\t+= udmabuf.o\n+dma-buf-objs-$(CONFIG_DMABUF_HEAPS)\t+= dma-heap.o\n+obj-$(CONFIG_DMABUF_HEAPS)\t\t+= heaps/\n+dma-buf-objs-$(CONFIG_SYNC_FILE)\t+= sync_file.o\n+dma-buf-objs-$(CONFIG_SW_SYNC)\t\t+= sw_sync.o sync_debug.o\n+dma-buf-objs-$(CONFIG_UDMABUF)\t\t+= udmabuf.o\n \n dmabuf_selftests-y := \\\n \tselftest.o \\\n \tst-dma-fence.o \\\n \tst-dma-fence-chain.o\n \n-obj-$(CONFIG_DMABUF_SELFTESTS)\t+= dmabuf_selftests.o\n+dma-buf-objs-$(CONFIG_DMABUF_SELFTESTS)\t+= dmabuf_selftests.o\n+\n+dma-shared-buffer-objs :=  $(dma-buf-objs-y)\n--- a/drivers/dma-buf/dma-buf.c\n+++ b/drivers/dma-buf/dma-buf.c\n@@ -1419,4 +1419,5 @@ static void __exit dma_buf_deinit(void)\n \tdma_buf_uninit_debugfs();\n \tkern_unmount(dma_buf_mnt);\n }\n-__exitcall(dma_buf_deinit);\n+module_exit(dma_buf_deinit);\n+MODULE_LICENSE(\"GPL\");\n--- a/kernel/sched/core.c\n+++ b/kernel/sched/core.c\n@@ -3066,6 +3066,7 @@ int wake_up_state(struct task_struct *p,\n {\n \treturn try_to_wake_up(p, state, 0);\n }\n+EXPORT_SYMBOL_GPL(wake_up_state);\n \n /*\n  * Perform scheduler related setup for a newly forked process p.\n--- a/fs/d_path.c\n+++ b/fs/d_path.c\n@@ -311,6 +311,7 @@ char *dynamic_dname(struct dentry *dentr\n \tbuffer += buflen - sz;\n \treturn memcpy(buffer, temp, sz);\n }\n+EXPORT_SYMBOL_GPL(dynamic_dname);\n \n char *simple_dname(struct dentry *dentry, char *buffer, int buflen)\n {\n"
  },
  {
    "path": "target/linux/generic/hack-5.10/910-kobject_uevent.patch",
    "content": "From 0d37e6edc09c99e683dd91ca0e83bbc0df8477b3 Mon Sep 17 00:00:00 2001\nFrom: Felix Fietkau <nbd@nbd.name>\nDate: Sun, 16 Jul 2017 16:56:10 +0200\nSubject: lib: add uevent_next_seqnum()\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n include/linux/kobject.h |  5 +++++\n lib/kobject_uevent.c    | 37 +++++++++++++++++++++++++++++++++++++\n 2 files changed, 42 insertions(+)\n\n--- a/lib/kobject_uevent.c\n+++ b/lib/kobject_uevent.c\n@@ -179,6 +179,18 @@ out:\n \treturn r;\n }\n \n+u64 uevent_next_seqnum(void)\n+{\n+\tu64 seq;\n+\n+\tmutex_lock(&uevent_sock_mutex);\n+\tseq = ++uevent_seqnum;\n+\tmutex_unlock(&uevent_sock_mutex);\n+\n+\treturn seq;\n+}\n+EXPORT_SYMBOL_GPL(uevent_next_seqnum);\n+\n /**\n  * kobject_synth_uevent - send synthetic uevent with arguments\n  *\n"
  },
  {
    "path": "target/linux/generic/hack-5.10/911-kobject_add_broadcast_uevent.patch",
    "content": "From 0d37e6edc09c99e683dd91ca0e83bbc0df8477b3 Mon Sep 17 00:00:00 2001\nFrom: Felix Fietkau <nbd@nbd.name>\nDate: Sun, 16 Jul 2017 16:56:10 +0200\nSubject: lib: add uevent_next_seqnum()\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n include/linux/kobject.h |  5 +++++\n lib/kobject_uevent.c    | 37 +++++++++++++++++++++++++++++++++++++\n 2 files changed, 42 insertions(+)\n\n--- a/include/linux/kobject.h\n+++ b/include/linux/kobject.h\n@@ -32,6 +32,8 @@\n #define UEVENT_NUM_ENVP\t\t\t64\t/* number of env pointers */\n #define UEVENT_BUFFER_SIZE\t\t2048\t/* buffer for the variables */\n \n+struct sk_buff;\n+\n #ifdef CONFIG_UEVENT_HELPER\n /* path to the userspace helper executed on an event */\n extern char uevent_helper[];\n@@ -244,4 +246,7 @@ int kobject_synth_uevent(struct kobject\n __printf(2, 3)\n int add_uevent_var(struct kobj_uevent_env *env, const char *format, ...);\n \n+int broadcast_uevent(struct sk_buff *skb, __u32 pid, __u32 group,\n+\t\t     gfp_t allocation);\n+\n #endif /* _KOBJECT_H_ */\n--- a/lib/kobject_uevent.c\n+++ b/lib/kobject_uevent.c\n@@ -691,6 +691,43 @@ int add_uevent_var(struct kobj_uevent_en\n EXPORT_SYMBOL_GPL(add_uevent_var);\n \n #if defined(CONFIG_NET)\n+int broadcast_uevent(struct sk_buff *skb, __u32 pid, __u32 group,\n+\t\t     gfp_t allocation)\n+{\n+\tstruct uevent_sock *ue_sk;\n+\tint err = 0;\n+\n+\t/* send netlink message */\n+\tmutex_lock(&uevent_sock_mutex);\n+\tlist_for_each_entry(ue_sk, &uevent_sock_list, list) {\n+\t\tstruct sock *uevent_sock = ue_sk->sk;\n+\t\tstruct sk_buff *skb2;\n+\n+\t\tskb2 = skb_clone(skb, allocation);\n+\t\tif (!skb2)\n+\t\t\tbreak;\n+\n+\t\terr = netlink_broadcast(uevent_sock, skb2, pid, group,\n+\t\t\t\t\tallocation);\n+\t\tif (err)\n+\t\t\tbreak;\n+\t}\n+\tmutex_unlock(&uevent_sock_mutex);\n+\n+\tkfree_skb(skb);\n+\treturn err;\n+}\n+#else\n+int broadcast_uevent(struct sk_buff *skb, __u32 pid, __u32 group,\n+\t\t     gfp_t allocation)\n+{\n+\tkfree_skb(skb);\n+\treturn 0;\n+}\n+#endif\n+EXPORT_SYMBOL_GPL(broadcast_uevent);\n+\n+#if defined(CONFIG_NET)\n static int uevent_net_broadcast(struct sock *usk, struct sk_buff *skb,\n \t\t\t\tstruct netlink_ext_ack *extack)\n {\n"
  },
  {
    "path": "target/linux/generic/hack-5.10/920-device_tree_cmdline.patch",
    "content": "--- a/drivers/of/fdt.c\n+++ b/drivers/of/fdt.c\n@@ -1055,6 +1055,9 @@ int __init early_init_dt_scan_chosen(uns\n \tp = of_get_flat_dt_prop(node, \"bootargs\", &l);\n \tif (p != NULL && l > 0)\n \t\tstrlcpy(data, p, min(l, COMMAND_LINE_SIZE));\n+\tp = of_get_flat_dt_prop(node, \"bootargs-append\", &l);\n+\tif (p != NULL && l > 0)\n+\t\tstrlcat(data, p, min_t(int, strlen(data) + (int)l, COMMAND_LINE_SIZE));\n \n \t/*\n \t * CONFIG_CMDLINE is meant to be a default in case nothing else\n"
  },
  {
    "path": "target/linux/generic/hack-5.15/204-module_strip.patch",
    "content": "From a779a482fb9b9f8fcdf8b2519c789b4b9bb5dd05 Mon Sep 17 00:00:00 2001\nFrom: Felix Fietkau <nbd@nbd.name>\nDate: Fri, 7 Jul 2017 16:56:48 +0200\nSubject: build: add a hack for removing non-essential module info\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n include/linux/module.h      | 13 ++++++++-----\n include/linux/moduleparam.h | 15 ++++++++++++---\n init/Kconfig                |  7 +++++++\n kernel/module.c             |  5 ++++-\n scripts/mod/modpost.c       | 12 ++++++++++++\n 5 files changed, 43 insertions(+), 9 deletions(-)\n\n--- a/include/linux/module.h\n+++ b/include/linux/module.h\n@@ -164,6 +164,7 @@ extern void cleanup_module(void);\n \n /* Generic info of form tag = \"info\" */\n #define MODULE_INFO(tag, info) __MODULE_INFO(tag, tag, info)\n+#define MODULE_INFO_STRIP(tag, info) __MODULE_INFO_STRIP(tag, tag, info)\n \n /* For userspace: you can also call me... */\n #define MODULE_ALIAS(_alias) MODULE_INFO(alias, _alias)\n@@ -233,12 +234,12 @@ extern void cleanup_module(void);\n  * Author(s), use \"Name <email>\" or just \"Name\", for multiple\n  * authors use multiple MODULE_AUTHOR() statements/lines.\n  */\n-#define MODULE_AUTHOR(_author) MODULE_INFO(author, _author)\n+#define MODULE_AUTHOR(_author) MODULE_INFO_STRIP(author, _author)\n \n /* What your module does. */\n-#define MODULE_DESCRIPTION(_description) MODULE_INFO(description, _description)\n+#define MODULE_DESCRIPTION(_description) MODULE_INFO_STRIP(description, _description)\n \n-#ifdef MODULE\n+#if defined(MODULE) && !defined(CONFIG_MODULE_STRIPPED)\n /* Creates an alias so file2alias.c can find device table. */\n #define MODULE_DEVICE_TABLE(type, name)\t\t\t\t\t\\\n extern typeof(name) __mod_##type##__##name##_device_table\t\t\\\n@@ -265,7 +266,9 @@ extern typeof(name) __mod_##type##__##na\n  */\n \n #if defined(MODULE) || !defined(CONFIG_SYSFS)\n-#define MODULE_VERSION(_version) MODULE_INFO(version, _version)\n+#define MODULE_VERSION(_version) MODULE_INFO_STRIP(version, _version)\n+#elif defined(CONFIG_MODULE_STRIPPED)\n+#define MODULE_VERSION(_version) __MODULE_INFO_DISABLED(version)\n #else\n #define MODULE_VERSION(_version)\t\t\t\t\t\\\n \tMODULE_INFO(version, _version);\t\t\t\t\t\\\n@@ -288,7 +291,7 @@ extern typeof(name) __mod_##type##__##na\n /* Optional firmware file (or files) needed by the module\n  * format is simply firmware file name.  Multiple firmware\n  * files require multiple MODULE_FIRMWARE() specifiers */\n-#define MODULE_FIRMWARE(_firmware) MODULE_INFO(firmware, _firmware)\n+#define MODULE_FIRMWARE(_firmware) MODULE_INFO_STRIP(firmware, _firmware)\n \n #define MODULE_IMPORT_NS(ns) MODULE_INFO(import_ns, #ns)\n \n--- a/include/linux/moduleparam.h\n+++ b/include/linux/moduleparam.h\n@@ -20,6 +20,16 @@\n /* Chosen so that structs with an unsigned long line up. */\n #define MAX_PARAM_PREFIX_LEN (64 - sizeof(unsigned long))\n \n+/* This struct is here for syntactic coherency, it is not used */\n+#define __MODULE_INFO_DISABLED(name)\t\t\t\t\t  \\\n+  struct __UNIQUE_ID(name) {}\n+\n+#ifdef CONFIG_MODULE_STRIPPED\n+#define __MODULE_INFO_STRIP(tag, name, info) __MODULE_INFO_DISABLED(name)\n+#else\n+#define __MODULE_INFO_STRIP(tag, name, info) __MODULE_INFO(tag, name, info)\n+#endif\n+\n #define __MODULE_INFO(tag, name, info)\t\t\t\t\t  \\\n \tstatic const char __UNIQUE_ID(name)[]\t\t\t\t  \\\n \t\t__used __section(\".modinfo\") __aligned(1)\t\t  \\\n@@ -31,7 +41,7 @@\n /* One for each parameter, describing how to use it.  Some files do\n    multiple of these per line, so can't just use MODULE_INFO. */\n #define MODULE_PARM_DESC(_parm, desc) \\\n-\t__MODULE_INFO(parm, _parm, #_parm \":\" desc)\n+\t__MODULE_INFO_STRIP(parm, _parm, #_parm \":\" desc)\n \n struct kernel_param;\n \n--- a/init/Kconfig\n+++ b/init/Kconfig\n@@ -2347,6 +2347,13 @@ config UNUSED_KSYMS_WHITELIST\n \t  one per line. The path can be absolute, or relative to the kernel\n \t  source tree.\n \n+config MODULE_STRIPPED\n+\tbool \"Reduce module size\"\n+\tdepends on MODULES\n+\thelp\n+\t  Remove module parameter descriptions, author info, version, aliases,\n+\t  device tables, etc.\n+\n endif # MODULES\n \n config MODULES_TREE_LOOKUP\n--- a/kernel/module.c\n+++ b/kernel/module.c\n@@ -1218,6 +1218,7 @@ static struct module_attribute *modinfo_\n \n static const char vermagic[] = VERMAGIC_STRING;\n \n+#if defined(CONFIG_MODVERSIONS) || !defined(CONFIG_MODULE_STRIPPED)\n static int try_to_force_load(struct module *mod, const char *reason)\n {\n #ifdef CONFIG_MODULE_FORCE_LOAD\n@@ -1229,6 +1230,7 @@ static int try_to_force_load(struct modu\n \treturn -ENOEXEC;\n #endif\n }\n+#endif\n \n #ifdef CONFIG_MODVERSIONS\n \n@@ -3227,9 +3229,11 @@ static int setup_load_info(struct load_i\n \n static int check_modinfo(struct module *mod, struct load_info *info, int flags)\n {\n-\tconst char *modmagic = get_modinfo(info, \"vermagic\");\n \tint err;\n \n+#ifndef CONFIG_MODULE_STRIPPED\n+\tconst char *modmagic = get_modinfo(info, \"vermagic\");\n+\n \tif (flags & MODULE_INIT_IGNORE_VERMAGIC)\n \t\tmodmagic = NULL;\n \n@@ -3250,6 +3254,7 @@ static int check_modinfo(struct module *\n \t\t\t\tmod->name);\n \t\tadd_taint_module(mod, TAINT_OOT_MODULE, LOCKDEP_STILL_OK);\n \t}\n+#endif\n \n \tcheck_modinfo_retpoline(mod, info);\n \n--- a/scripts/mod/modpost.c\n+++ b/scripts/mod/modpost.c\n@@ -2033,7 +2033,9 @@ static void read_symbols(const char *mod\n \t\tsymname = remove_dot(info.strtab + sym->st_name);\n \n \t\thandle_symbol(mod, &info, sym, symname);\n+#ifndef CONFIG_MODULE_STRIPPED\n \t\thandle_moddevtable(mod, &info, sym, symname);\n+#endif\n \t}\n \n \tfor (sym = info.symtab_start; sym < info.symtab_stop; sym++) {\n@@ -2212,8 +2214,10 @@ static void add_header(struct buffer *b,\n \tbuf_printf(b, \"BUILD_SALT;\\n\");\n \tbuf_printf(b, \"BUILD_LTO_INFO;\\n\");\n \tbuf_printf(b, \"\\n\");\n+#ifndef CONFIG_MODULE_STRIPPED\n \tbuf_printf(b, \"MODULE_INFO(vermagic, VERMAGIC_STRING);\\n\");\n \tbuf_printf(b, \"MODULE_INFO(name, KBUILD_MODNAME);\\n\");\n+#endif\n \tbuf_printf(b, \"\\n\");\n \tbuf_printf(b, \"__visible struct module __this_module\\n\");\n \tbuf_printf(b, \"__section(\\\".gnu.linkonce.this_module\\\") = {\\n\");\n@@ -2230,8 +2234,10 @@ static void add_header(struct buffer *b,\n \n static void add_intree_flag(struct buffer *b, int is_intree)\n {\n+#ifndef CONFIG_MODULE_STRIPPED\n \tif (is_intree)\n \t\tbuf_printf(b, \"\\nMODULE_INFO(intree, \\\"Y\\\");\\n\");\n+#endif\n }\n \n /* Cannot check for assembler */\n@@ -2244,8 +2250,10 @@ static void add_retpoline(struct buffer\n \n static void add_staging_flag(struct buffer *b, const char *name)\n {\n+#ifndef CONFIG_MODULE_STRIPPED\n \tif (strstarts(name, \"drivers/staging\"))\n \t\tbuf_printf(b, \"\\nMODULE_INFO(staging, \\\"Y\\\");\\n\");\n+#endif\n }\n \n /**\n@@ -2325,11 +2333,13 @@ static void add_depends(struct buffer *b\n \n static void add_srcversion(struct buffer *b, struct module *mod)\n {\n+#ifndef CONFIG_MODULE_STRIPPED\n \tif (mod->srcversion[0]) {\n \t\tbuf_printf(b, \"\\n\");\n \t\tbuf_printf(b, \"MODULE_INFO(srcversion, \\\"%s\\\");\\n\",\n \t\t\t   mod->srcversion);\n \t}\n+#endif\n }\n \n static void write_buf(struct buffer *b, const char *fname)\n@@ -2578,7 +2588,9 @@ int main(int argc, char **argv)\n \t\tadd_staging_flag(&buf, mod->name);\n \t\tadd_versions(&buf, mod);\n \t\tadd_depends(&buf, mod);\n+#ifndef CONFIG_MODULE_STRIPPED\n \t\tadd_moddevtable(&buf, mod);\n+#endif\n \t\tadd_srcversion(&buf, mod);\n \n \t\tsprintf(fname, \"%s.mod.c\", mod->name);\n"
  },
  {
    "path": "target/linux/generic/hack-5.15/205-kconfig-exit.patch",
    "content": "--- a/scripts/kconfig/conf.c\n+++ b/scripts/kconfig/conf.c\n@@ -435,6 +435,8 @@ static int conf_sym(struct menu *menu)\n \t\t\t\tbreak;\n \t\t\tcontinue;\n \t\tcase 0:\n+\t\t\tif (!sym_has_value(sym) && !tty_stdio && getenv(\"FAIL_ON_UNCONFIGURED\"))\n+\t\t\t\texit(1);\n \t\t\tnewval = oldval;\n \t\t\tbreak;\n \t\tcase '?':\n"
  },
  {
    "path": "target/linux/generic/hack-5.15/210-darwin_scripts_include.patch",
    "content": "From db7c30dcd9a0391bf13b62c9f91e144d762ef43a Mon Sep 17 00:00:00 2001\nFrom: Florian Fainelli <f.fainelli@gmail.com>\nDate: Fri, 7 Jul 2017 17:00:49 +0200\nSubject: Add an OSX specific patch to make the kernel be compiled\n\nlede-commit: 3fc2a24f0422b2f55f9ed43f116db3111f700526\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n---\n scripts/kconfig/Makefile   |    3 +\n scripts/mod/elf.h          | 3007 ++++++++++++++++++++++++++++++++++++++++++++\n scripts/mod/mk_elfconfig.c |    4 +\n scripts/mod/modpost.h      |    4 +\n 4 files changed, 3018 insertions(+)\n create mode 100644 scripts/mod/elf.h\n\n--- /dev/null\n+++ b/scripts/mod/elf.h\n@@ -0,0 +1,3007 @@\n+/* This file defines standard ELF types, structures, and macros.\n+   Copyright (C) 1995-2012 Free Software Foundation, Inc.\n+   This file is part of the GNU C Library.\n+\n+   The GNU C Library is free software; you can redistribute it and/or\n+   modify it under the terms of the GNU Lesser General Public\n+   License as published by the Free Software Foundation; either\n+   version 2.1 of the License, or (at your option) any later version.\n+\n+   The GNU C Library is distributed in the hope that it will be useful,\n+   but WITHOUT ANY WARRANTY; without even the implied warranty of\n+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\n+   Lesser General Public License for more details.\n+\n+   You should have received a copy of the GNU Lesser General Public\n+   License along with the GNU C Library; if not, see\n+   <http://www.gnu.org/licenses/>.  */\n+\n+#ifndef _ELF_H\n+#define\t_ELF_H 1\n+\n+/* Standard ELF types.  */\n+\n+#include <stdint.h>\n+\n+/* Type for a 16-bit quantity.  */\n+typedef uint16_t Elf32_Half;\n+typedef uint16_t Elf64_Half;\n+\n+/* Types for signed and unsigned 32-bit quantities.  */\n+typedef uint32_t Elf32_Word;\n+typedef\tint32_t  Elf32_Sword;\n+typedef uint32_t Elf64_Word;\n+typedef\tint32_t  Elf64_Sword;\n+\n+/* Types for signed and unsigned 64-bit quantities.  */\n+typedef uint64_t Elf32_Xword;\n+typedef\tint64_t  Elf32_Sxword;\n+typedef uint64_t Elf64_Xword;\n+typedef\tint64_t  Elf64_Sxword;\n+\n+/* Type of addresses.  */\n+typedef uint32_t Elf32_Addr;\n+typedef uint64_t Elf64_Addr;\n+\n+/* Type of file offsets.  */\n+typedef uint32_t Elf32_Off;\n+typedef uint64_t Elf64_Off;\n+\n+/* Type for section indices, which are 16-bit quantities.  */\n+typedef uint16_t Elf32_Section;\n+typedef uint16_t Elf64_Section;\n+\n+/* Type for version symbol information.  */\n+typedef Elf32_Half Elf32_Versym;\n+typedef Elf64_Half Elf64_Versym;\n+\n+\n+/* The ELF file header.  This appears at the start of every ELF file.  */\n+\n+#define EI_NIDENT (16)\n+\n+typedef struct\n+{\n+  unsigned char\te_ident[EI_NIDENT];\t/* Magic number and other info */\n+  Elf32_Half\te_type;\t\t\t/* Object file type */\n+  Elf32_Half\te_machine;\t\t/* Architecture */\n+  Elf32_Word\te_version;\t\t/* Object file version */\n+  Elf32_Addr\te_entry;\t\t/* Entry point virtual address */\n+  Elf32_Off\te_phoff;\t\t/* Program header table file offset */\n+  Elf32_Off\te_shoff;\t\t/* Section header table file offset */\n+  Elf32_Word\te_flags;\t\t/* Processor-specific flags */\n+  Elf32_Half\te_ehsize;\t\t/* ELF header size in bytes */\n+  Elf32_Half\te_phentsize;\t\t/* Program header table entry size */\n+  Elf32_Half\te_phnum;\t\t/* Program header table entry count */\n+  Elf32_Half\te_shentsize;\t\t/* Section header table entry size */\n+  Elf32_Half\te_shnum;\t\t/* Section header table entry count */\n+  Elf32_Half\te_shstrndx;\t\t/* Section header string table index */\n+} Elf32_Ehdr;\n+\n+typedef struct\n+{\n+  unsigned char\te_ident[EI_NIDENT];\t/* Magic number and other info */\n+  Elf64_Half\te_type;\t\t\t/* Object file type */\n+  Elf64_Half\te_machine;\t\t/* Architecture */\n+  Elf64_Word\te_version;\t\t/* Object file version */\n+  Elf64_Addr\te_entry;\t\t/* Entry point virtual address */\n+  Elf64_Off\te_phoff;\t\t/* Program header table file offset */\n+  Elf64_Off\te_shoff;\t\t/* Section header table file offset */\n+  Elf64_Word\te_flags;\t\t/* Processor-specific flags */\n+  Elf64_Half\te_ehsize;\t\t/* ELF header size in bytes */\n+  Elf64_Half\te_phentsize;\t\t/* Program header table entry size */\n+  Elf64_Half\te_phnum;\t\t/* Program header table entry count */\n+  Elf64_Half\te_shentsize;\t\t/* Section header table entry size */\n+  Elf64_Half\te_shnum;\t\t/* Section header table entry count */\n+  Elf64_Half\te_shstrndx;\t\t/* Section header string table index */\n+} Elf64_Ehdr;\n+\n+/* Fields in the e_ident array.  The EI_* macros are indices into the\n+   array.  The macros under each EI_* macro are the values the byte\n+   may have.  */\n+\n+#define EI_MAG0\t\t0\t\t/* File identification byte 0 index */\n+#define ELFMAG0\t\t0x7f\t\t/* Magic number byte 0 */\n+\n+#define EI_MAG1\t\t1\t\t/* File identification byte 1 index */\n+#define ELFMAG1\t\t'E'\t\t/* Magic number byte 1 */\n+\n+#define EI_MAG2\t\t2\t\t/* File identification byte 2 index */\n+#define ELFMAG2\t\t'L'\t\t/* Magic number byte 2 */\n+\n+#define EI_MAG3\t\t3\t\t/* File identification byte 3 index */\n+#define ELFMAG3\t\t'F'\t\t/* Magic number byte 3 */\n+\n+/* Conglomeration of the identification bytes, for easy testing as a word.  */\n+#define\tELFMAG\t\t\"\\177ELF\"\n+#define\tSELFMAG\t\t4\n+\n+#define EI_CLASS\t4\t\t/* File class byte index */\n+#define ELFCLASSNONE\t0\t\t/* Invalid class */\n+#define ELFCLASS32\t1\t\t/* 32-bit objects */\n+#define ELFCLASS64\t2\t\t/* 64-bit objects */\n+#define ELFCLASSNUM\t3\n+\n+#define EI_DATA\t\t5\t\t/* Data encoding byte index */\n+#define ELFDATANONE\t0\t\t/* Invalid data encoding */\n+#define ELFDATA2LSB\t1\t\t/* 2's complement, little endian */\n+#define ELFDATA2MSB\t2\t\t/* 2's complement, big endian */\n+#define ELFDATANUM\t3\n+\n+#define EI_VERSION\t6\t\t/* File version byte index */\n+\t\t\t\t\t/* Value must be EV_CURRENT */\n+\n+#define EI_OSABI\t7\t\t/* OS ABI identification */\n+#define ELFOSABI_NONE\t\t0\t/* UNIX System V ABI */\n+#define ELFOSABI_SYSV\t\t0\t/* Alias.  */\n+#define ELFOSABI_HPUX\t\t1\t/* HP-UX */\n+#define ELFOSABI_NETBSD\t\t2\t/* NetBSD.  */\n+#define ELFOSABI_GNU\t\t3\t/* Object uses GNU ELF extensions.  */\n+#define ELFOSABI_LINUX\t\tELFOSABI_GNU /* Compatibility alias.  */\n+#define ELFOSABI_SOLARIS\t6\t/* Sun Solaris.  */\n+#define ELFOSABI_AIX\t\t7\t/* IBM AIX.  */\n+#define ELFOSABI_IRIX\t\t8\t/* SGI Irix.  */\n+#define ELFOSABI_FREEBSD\t9\t/* FreeBSD.  */\n+#define ELFOSABI_TRU64\t\t10\t/* Compaq TRU64 UNIX.  */\n+#define ELFOSABI_MODESTO\t11\t/* Novell Modesto.  */\n+#define ELFOSABI_OPENBSD\t12\t/* OpenBSD.  */\n+#define ELFOSABI_ARM_AEABI\t64\t/* ARM EABI */\n+#define ELFOSABI_ARM\t\t97\t/* ARM */\n+#define ELFOSABI_STANDALONE\t255\t/* Standalone (embedded) application */\n+\n+#define EI_ABIVERSION\t8\t\t/* ABI version */\n+\n+#define EI_PAD\t\t9\t\t/* Byte index of padding bytes */\n+\n+/* Legal values for e_type (object file type).  */\n+\n+#define ET_NONE\t\t0\t\t/* No file type */\n+#define ET_REL\t\t1\t\t/* Relocatable file */\n+#define ET_EXEC\t\t2\t\t/* Executable file */\n+#define ET_DYN\t\t3\t\t/* Shared object file */\n+#define ET_CORE\t\t4\t\t/* Core file */\n+#define\tET_NUM\t\t5\t\t/* Number of defined types */\n+#define ET_LOOS\t\t0xfe00\t\t/* OS-specific range start */\n+#define ET_HIOS\t\t0xfeff\t\t/* OS-specific range end */\n+#define ET_LOPROC\t0xff00\t\t/* Processor-specific range start */\n+#define ET_HIPROC\t0xffff\t\t/* Processor-specific range end */\n+\n+/* Legal values for e_machine (architecture).  */\n+\n+#define EM_NONE\t\t 0\t\t/* No machine */\n+#define EM_M32\t\t 1\t\t/* AT&T WE 32100 */\n+#define EM_SPARC\t 2\t\t/* SUN SPARC */\n+#define EM_386\t\t 3\t\t/* Intel 80386 */\n+#define EM_68K\t\t 4\t\t/* Motorola m68k family */\n+#define EM_88K\t\t 5\t\t/* Motorola m88k family */\n+#define EM_860\t\t 7\t\t/* Intel 80860 */\n+#define EM_MIPS\t\t 8\t\t/* MIPS R3000 big-endian */\n+#define EM_S370\t\t 9\t\t/* IBM System/370 */\n+#define EM_MIPS_RS3_LE\t10\t\t/* MIPS R3000 little-endian */\n+\n+#define EM_PARISC\t15\t\t/* HPPA */\n+#define EM_VPP500\t17\t\t/* Fujitsu VPP500 */\n+#define EM_SPARC32PLUS\t18\t\t/* Sun's \"v8plus\" */\n+#define EM_960\t\t19\t\t/* Intel 80960 */\n+#define EM_PPC\t\t20\t\t/* PowerPC */\n+#define EM_PPC64\t21\t\t/* PowerPC 64-bit */\n+#define EM_S390\t\t22\t\t/* IBM S390 */\n+\n+#define EM_V800\t\t36\t\t/* NEC V800 series */\n+#define EM_FR20\t\t37\t\t/* Fujitsu FR20 */\n+#define EM_RH32\t\t38\t\t/* TRW RH-32 */\n+#define EM_RCE\t\t39\t\t/* Motorola RCE */\n+#define EM_ARM\t\t40\t\t/* ARM */\n+#define EM_FAKE_ALPHA\t41\t\t/* Digital Alpha */\n+#define EM_SH\t\t42\t\t/* Hitachi SH */\n+#define EM_SPARCV9\t43\t\t/* SPARC v9 64-bit */\n+#define EM_TRICORE\t44\t\t/* Siemens Tricore */\n+#define EM_ARC\t\t45\t\t/* Argonaut RISC Core */\n+#define EM_H8_300\t46\t\t/* Hitachi H8/300 */\n+#define EM_H8_300H\t47\t\t/* Hitachi H8/300H */\n+#define EM_H8S\t\t48\t\t/* Hitachi H8S */\n+#define EM_H8_500\t49\t\t/* Hitachi H8/500 */\n+#define EM_IA_64\t50\t\t/* Intel Merced */\n+#define EM_MIPS_X\t51\t\t/* Stanford MIPS-X */\n+#define EM_COLDFIRE\t52\t\t/* Motorola Coldfire */\n+#define EM_68HC12\t53\t\t/* Motorola M68HC12 */\n+#define EM_MMA\t\t54\t\t/* Fujitsu MMA Multimedia Accelerator*/\n+#define EM_PCP\t\t55\t\t/* Siemens PCP */\n+#define EM_NCPU\t\t56\t\t/* Sony nCPU embeeded RISC */\n+#define EM_NDR1\t\t57\t\t/* Denso NDR1 microprocessor */\n+#define EM_STARCORE\t58\t\t/* Motorola Start*Core processor */\n+#define EM_ME16\t\t59\t\t/* Toyota ME16 processor */\n+#define EM_ST100\t60\t\t/* STMicroelectronic ST100 processor */\n+#define EM_TINYJ\t61\t\t/* Advanced Logic Corp. Tinyj emb.fam*/\n+#define EM_X86_64\t62\t\t/* AMD x86-64 architecture */\n+#define EM_PDSP\t\t63\t\t/* Sony DSP Processor */\n+\n+#define EM_FX66\t\t66\t\t/* Siemens FX66 microcontroller */\n+#define EM_ST9PLUS\t67\t\t/* STMicroelectronics ST9+ 8/16 mc */\n+#define EM_ST7\t\t68\t\t/* STmicroelectronics ST7 8 bit mc */\n+#define EM_68HC16\t69\t\t/* Motorola MC68HC16 microcontroller */\n+#define EM_68HC11\t70\t\t/* Motorola MC68HC11 microcontroller */\n+#define EM_68HC08\t71\t\t/* Motorola MC68HC08 microcontroller */\n+#define EM_68HC05\t72\t\t/* Motorola MC68HC05 microcontroller */\n+#define EM_SVX\t\t73\t\t/* Silicon Graphics SVx */\n+#define EM_ST19\t\t74\t\t/* STMicroelectronics ST19 8 bit mc */\n+#define EM_VAX\t\t75\t\t/* Digital VAX */\n+#define EM_CRIS\t\t76\t\t/* Axis Communications 32-bit embedded processor */\n+#define EM_JAVELIN\t77\t\t/* Infineon Technologies 32-bit embedded processor */\n+#define EM_FIREPATH\t78\t\t/* Element 14 64-bit DSP Processor */\n+#define EM_ZSP\t\t79\t\t/* LSI Logic 16-bit DSP Processor */\n+#define EM_MMIX\t\t80\t\t/* Donald Knuth's educational 64-bit processor */\n+#define EM_HUANY\t81\t\t/* Harvard University machine-independent object files */\n+#define EM_PRISM\t82\t\t/* SiTera Prism */\n+#define EM_AVR\t\t83\t\t/* Atmel AVR 8-bit microcontroller */\n+#define EM_FR30\t\t84\t\t/* Fujitsu FR30 */\n+#define EM_D10V\t\t85\t\t/* Mitsubishi D10V */\n+#define EM_D30V\t\t86\t\t/* Mitsubishi D30V */\n+#define EM_V850\t\t87\t\t/* NEC v850 */\n+#define EM_M32R\t\t88\t\t/* Mitsubishi M32R */\n+#define EM_MN10300\t89\t\t/* Matsushita MN10300 */\n+#define EM_MN10200\t90\t\t/* Matsushita MN10200 */\n+#define EM_PJ\t\t91\t\t/* picoJava */\n+#define EM_OPENRISC\t92\t\t/* OpenRISC 32-bit embedded processor */\n+#define EM_ARC_A5\t93\t\t/* ARC Cores Tangent-A5 */\n+#define EM_XTENSA\t94\t\t/* Tensilica Xtensa Architecture */\n+#define EM_TILEPRO\t188\t\t/* Tilera TILEPro */\n+#define EM_TILEGX\t191\t\t/* Tilera TILE-Gx */\n+#define EM_NUM\t\t192\n+\n+/* If it is necessary to assign new unofficial EM_* values, please\n+   pick large random numbers (0x8523, 0xa7f2, etc.) to minimize the\n+   chances of collision with official or non-GNU unofficial values.  */\n+\n+#define EM_ALPHA\t0x9026\n+\n+/* Legal values for e_version (version).  */\n+\n+#define EV_NONE\t\t0\t\t/* Invalid ELF version */\n+#define EV_CURRENT\t1\t\t/* Current version */\n+#define EV_NUM\t\t2\n+\n+/* Section header.  */\n+\n+typedef struct\n+{\n+  Elf32_Word\tsh_name;\t\t/* Section name (string tbl index) */\n+  Elf32_Word\tsh_type;\t\t/* Section type */\n+  Elf32_Word\tsh_flags;\t\t/* Section flags */\n+  Elf32_Addr\tsh_addr;\t\t/* Section virtual addr at execution */\n+  Elf32_Off\tsh_offset;\t\t/* Section file offset */\n+  Elf32_Word\tsh_size;\t\t/* Section size in bytes */\n+  Elf32_Word\tsh_link;\t\t/* Link to another section */\n+  Elf32_Word\tsh_info;\t\t/* Additional section information */\n+  Elf32_Word\tsh_addralign;\t\t/* Section alignment */\n+  Elf32_Word\tsh_entsize;\t\t/* Entry size if section holds table */\n+} Elf32_Shdr;\n+\n+typedef struct\n+{\n+  Elf64_Word\tsh_name;\t\t/* Section name (string tbl index) */\n+  Elf64_Word\tsh_type;\t\t/* Section type */\n+  Elf64_Xword\tsh_flags;\t\t/* Section flags */\n+  Elf64_Addr\tsh_addr;\t\t/* Section virtual addr at execution */\n+  Elf64_Off\tsh_offset;\t\t/* Section file offset */\n+  Elf64_Xword\tsh_size;\t\t/* Section size in bytes */\n+  Elf64_Word\tsh_link;\t\t/* Link to another section */\n+  Elf64_Word\tsh_info;\t\t/* Additional section information */\n+  Elf64_Xword\tsh_addralign;\t\t/* Section alignment */\n+  Elf64_Xword\tsh_entsize;\t\t/* Entry size if section holds table */\n+} Elf64_Shdr;\n+\n+/* Special section indices.  */\n+\n+#define SHN_UNDEF\t0\t\t/* Undefined section */\n+#define SHN_LORESERVE\t0xff00\t\t/* Start of reserved indices */\n+#define SHN_LOPROC\t0xff00\t\t/* Start of processor-specific */\n+#define SHN_BEFORE\t0xff00\t\t/* Order section before all others\n+\t\t\t\t\t   (Solaris).  */\n+#define SHN_AFTER\t0xff01\t\t/* Order section after all others\n+\t\t\t\t\t   (Solaris).  */\n+#define SHN_HIPROC\t0xff1f\t\t/* End of processor-specific */\n+#define SHN_LOOS\t0xff20\t\t/* Start of OS-specific */\n+#define SHN_HIOS\t0xff3f\t\t/* End of OS-specific */\n+#define SHN_ABS\t\t0xfff1\t\t/* Associated symbol is absolute */\n+#define SHN_COMMON\t0xfff2\t\t/* Associated symbol is common */\n+#define SHN_XINDEX\t0xffff\t\t/* Index is in extra table.  */\n+#define SHN_HIRESERVE\t0xffff\t\t/* End of reserved indices */\n+\n+/* Legal values for sh_type (section type).  */\n+\n+#define SHT_NULL\t  0\t\t/* Section header table entry unused */\n+#define SHT_PROGBITS\t  1\t\t/* Program data */\n+#define SHT_SYMTAB\t  2\t\t/* Symbol table */\n+#define SHT_STRTAB\t  3\t\t/* String table */\n+#define SHT_RELA\t  4\t\t/* Relocation entries with addends */\n+#define SHT_HASH\t  5\t\t/* Symbol hash table */\n+#define SHT_DYNAMIC\t  6\t\t/* Dynamic linking information */\n+#define SHT_NOTE\t  7\t\t/* Notes */\n+#define SHT_NOBITS\t  8\t\t/* Program space with no data (bss) */\n+#define SHT_REL\t\t  9\t\t/* Relocation entries, no addends */\n+#define SHT_SHLIB\t  10\t\t/* Reserved */\n+#define SHT_DYNSYM\t  11\t\t/* Dynamic linker symbol table */\n+#define SHT_INIT_ARRAY\t  14\t\t/* Array of constructors */\n+#define SHT_FINI_ARRAY\t  15\t\t/* Array of destructors */\n+#define SHT_PREINIT_ARRAY 16\t\t/* Array of pre-constructors */\n+#define SHT_GROUP\t  17\t\t/* Section group */\n+#define SHT_SYMTAB_SHNDX  18\t\t/* Extended section indeces */\n+#define\tSHT_NUM\t\t  19\t\t/* Number of defined types.  */\n+#define SHT_LOOS\t  0x60000000\t/* Start OS-specific.  */\n+#define SHT_GNU_ATTRIBUTES 0x6ffffff5\t/* Object attributes.  */\n+#define SHT_GNU_HASH\t  0x6ffffff6\t/* GNU-style hash table.  */\n+#define SHT_GNU_LIBLIST\t  0x6ffffff7\t/* Prelink library list */\n+#define SHT_CHECKSUM\t  0x6ffffff8\t/* Checksum for DSO content.  */\n+#define SHT_LOSUNW\t  0x6ffffffa\t/* Sun-specific low bound.  */\n+#define SHT_SUNW_move\t  0x6ffffffa\n+#define SHT_SUNW_COMDAT   0x6ffffffb\n+#define SHT_SUNW_syminfo  0x6ffffffc\n+#define SHT_GNU_verdef\t  0x6ffffffd\t/* Version definition section.  */\n+#define SHT_GNU_verneed\t  0x6ffffffe\t/* Version needs section.  */\n+#define SHT_GNU_versym\t  0x6fffffff\t/* Version symbol table.  */\n+#define SHT_HISUNW\t  0x6fffffff\t/* Sun-specific high bound.  */\n+#define SHT_HIOS\t  0x6fffffff\t/* End OS-specific type */\n+#define SHT_LOPROC\t  0x70000000\t/* Start of processor-specific */\n+#define SHT_HIPROC\t  0x7fffffff\t/* End of processor-specific */\n+#define SHT_LOUSER\t  0x80000000\t/* Start of application-specific */\n+#define SHT_HIUSER\t  0x8fffffff\t/* End of application-specific */\n+\n+/* Legal values for sh_flags (section flags).  */\n+\n+#define SHF_WRITE\t     (1 << 0)\t/* Writable */\n+#define SHF_ALLOC\t     (1 << 1)\t/* Occupies memory during execution */\n+#define SHF_EXECINSTR\t     (1 << 2)\t/* Executable */\n+#define SHF_MERGE\t     (1 << 4)\t/* Might be merged */\n+#define SHF_STRINGS\t     (1 << 5)\t/* Contains nul-terminated strings */\n+#define SHF_INFO_LINK\t     (1 << 6)\t/* `sh_info' contains SHT index */\n+#define SHF_LINK_ORDER\t     (1 << 7)\t/* Preserve order after combining */\n+#define SHF_OS_NONCONFORMING (1 << 8)\t/* Non-standard OS specific handling\n+\t\t\t\t\t   required */\n+#define SHF_GROUP\t     (1 << 9)\t/* Section is member of a group.  */\n+#define SHF_TLS\t\t     (1 << 10)\t/* Section hold thread-local data.  */\n+#define SHF_MASKOS\t     0x0ff00000\t/* OS-specific.  */\n+#define SHF_MASKPROC\t     0xf0000000\t/* Processor-specific */\n+#define SHF_ORDERED\t     (1 << 30)\t/* Special ordering requirement\n+\t\t\t\t\t   (Solaris).  */\n+#define SHF_EXCLUDE\t     (1 << 31)\t/* Section is excluded unless\n+\t\t\t\t\t   referenced or allocated (Solaris).*/\n+\n+/* Section group handling.  */\n+#define GRP_COMDAT\t0x1\t\t/* Mark group as COMDAT.  */\n+\n+/* Symbol table entry.  */\n+\n+typedef struct\n+{\n+  Elf32_Word\tst_name;\t\t/* Symbol name (string tbl index) */\n+  Elf32_Addr\tst_value;\t\t/* Symbol value */\n+  Elf32_Word\tst_size;\t\t/* Symbol size */\n+  unsigned char\tst_info;\t\t/* Symbol type and binding */\n+  unsigned char\tst_other;\t\t/* Symbol visibility */\n+  Elf32_Section\tst_shndx;\t\t/* Section index */\n+} Elf32_Sym;\n+\n+typedef struct\n+{\n+  Elf64_Word\tst_name;\t\t/* Symbol name (string tbl index) */\n+  unsigned char\tst_info;\t\t/* Symbol type and binding */\n+  unsigned char st_other;\t\t/* Symbol visibility */\n+  Elf64_Section\tst_shndx;\t\t/* Section index */\n+  Elf64_Addr\tst_value;\t\t/* Symbol value */\n+  Elf64_Xword\tst_size;\t\t/* Symbol size */\n+} Elf64_Sym;\n+\n+/* The syminfo section if available contains additional information about\n+   every dynamic symbol.  */\n+\n+typedef struct\n+{\n+  Elf32_Half si_boundto;\t\t/* Direct bindings, symbol bound to */\n+  Elf32_Half si_flags;\t\t\t/* Per symbol flags */\n+} Elf32_Syminfo;\n+\n+typedef struct\n+{\n+  Elf64_Half si_boundto;\t\t/* Direct bindings, symbol bound to */\n+  Elf64_Half si_flags;\t\t\t/* Per symbol flags */\n+} Elf64_Syminfo;\n+\n+/* Possible values for si_boundto.  */\n+#define SYMINFO_BT_SELF\t\t0xffff\t/* Symbol bound to self */\n+#define SYMINFO_BT_PARENT\t0xfffe\t/* Symbol bound to parent */\n+#define SYMINFO_BT_LOWRESERVE\t0xff00\t/* Beginning of reserved entries */\n+\n+/* Possible bitmasks for si_flags.  */\n+#define SYMINFO_FLG_DIRECT\t0x0001\t/* Direct bound symbol */\n+#define SYMINFO_FLG_PASSTHRU\t0x0002\t/* Pass-thru symbol for translator */\n+#define SYMINFO_FLG_COPY\t0x0004\t/* Symbol is a copy-reloc */\n+#define SYMINFO_FLG_LAZYLOAD\t0x0008\t/* Symbol bound to object to be lazy\n+\t\t\t\t\t   loaded */\n+/* Syminfo version values.  */\n+#define SYMINFO_NONE\t\t0\n+#define SYMINFO_CURRENT\t\t1\n+#define SYMINFO_NUM\t\t2\n+\n+\n+/* How to extract and insert information held in the st_info field.  */\n+\n+#define ELF32_ST_BIND(val)\t\t(((unsigned char) (val)) >> 4)\n+#define ELF32_ST_TYPE(val)\t\t((val) & 0xf)\n+#define ELF32_ST_INFO(bind, type)\t(((bind) << 4) + ((type) & 0xf))\n+\n+/* Both Elf32_Sym and Elf64_Sym use the same one-byte st_info field.  */\n+#define ELF64_ST_BIND(val)\t\tELF32_ST_BIND (val)\n+#define ELF64_ST_TYPE(val)\t\tELF32_ST_TYPE (val)\n+#define ELF64_ST_INFO(bind, type)\tELF32_ST_INFO ((bind), (type))\n+\n+/* Legal values for ST_BIND subfield of st_info (symbol binding).  */\n+\n+#define STB_LOCAL\t0\t\t/* Local symbol */\n+#define STB_GLOBAL\t1\t\t/* Global symbol */\n+#define STB_WEAK\t2\t\t/* Weak symbol */\n+#define\tSTB_NUM\t\t3\t\t/* Number of defined types.  */\n+#define STB_LOOS\t10\t\t/* Start of OS-specific */\n+#define STB_GNU_UNIQUE\t10\t\t/* Unique symbol.  */\n+#define STB_HIOS\t12\t\t/* End of OS-specific */\n+#define STB_LOPROC\t13\t\t/* Start of processor-specific */\n+#define STB_HIPROC\t15\t\t/* End of processor-specific */\n+\n+/* Legal values for ST_TYPE subfield of st_info (symbol type).  */\n+\n+#define STT_NOTYPE\t0\t\t/* Symbol type is unspecified */\n+#define STT_OBJECT\t1\t\t/* Symbol is a data object */\n+#define STT_FUNC\t2\t\t/* Symbol is a code object */\n+#define STT_SECTION\t3\t\t/* Symbol associated with a section */\n+#define STT_FILE\t4\t\t/* Symbol's name is file name */\n+#define STT_COMMON\t5\t\t/* Symbol is a common data object */\n+#define STT_TLS\t\t6\t\t/* Symbol is thread-local data object*/\n+#define\tSTT_NUM\t\t7\t\t/* Number of defined types.  */\n+#define STT_LOOS\t10\t\t/* Start of OS-specific */\n+#define STT_GNU_IFUNC\t10\t\t/* Symbol is indirect code object */\n+#define STT_HIOS\t12\t\t/* End of OS-specific */\n+#define STT_LOPROC\t13\t\t/* Start of processor-specific */\n+#define STT_HIPROC\t15\t\t/* End of processor-specific */\n+\n+\n+/* Symbol table indices are found in the hash buckets and chain table\n+   of a symbol hash table section.  This special index value indicates\n+   the end of a chain, meaning no further symbols are found in that bucket.  */\n+\n+#define STN_UNDEF\t0\t\t/* End of a chain.  */\n+\n+\n+/* How to extract and insert information held in the st_other field.  */\n+\n+#define ELF32_ST_VISIBILITY(o)\t((o) & 0x03)\n+\n+/* For ELF64 the definitions are the same.  */\n+#define ELF64_ST_VISIBILITY(o)\tELF32_ST_VISIBILITY (o)\n+\n+/* Symbol visibility specification encoded in the st_other field.  */\n+#define STV_DEFAULT\t0\t\t/* Default symbol visibility rules */\n+#define STV_INTERNAL\t1\t\t/* Processor specific hidden class */\n+#define STV_HIDDEN\t2\t\t/* Sym unavailable in other modules */\n+#define STV_PROTECTED\t3\t\t/* Not preemptible, not exported */\n+\n+\n+/* Relocation table entry without addend (in section of type SHT_REL).  */\n+\n+typedef struct\n+{\n+  Elf32_Addr\tr_offset;\t\t/* Address */\n+  Elf32_Word\tr_info;\t\t\t/* Relocation type and symbol index */\n+} Elf32_Rel;\n+\n+/* I have seen two different definitions of the Elf64_Rel and\n+   Elf64_Rela structures, so we'll leave them out until Novell (or\n+   whoever) gets their act together.  */\n+/* The following, at least, is used on Sparc v9, MIPS, and Alpha.  */\n+\n+typedef struct\n+{\n+  Elf64_Addr\tr_offset;\t\t/* Address */\n+  Elf64_Xword\tr_info;\t\t\t/* Relocation type and symbol index */\n+} Elf64_Rel;\n+\n+/* Relocation table entry with addend (in section of type SHT_RELA).  */\n+\n+typedef struct\n+{\n+  Elf32_Addr\tr_offset;\t\t/* Address */\n+  Elf32_Word\tr_info;\t\t\t/* Relocation type and symbol index */\n+  Elf32_Sword\tr_addend;\t\t/* Addend */\n+} Elf32_Rela;\n+\n+typedef struct\n+{\n+  Elf64_Addr\tr_offset;\t\t/* Address */\n+  Elf64_Xword\tr_info;\t\t\t/* Relocation type and symbol index */\n+  Elf64_Sxword\tr_addend;\t\t/* Addend */\n+} Elf64_Rela;\n+\n+/* How to extract and insert information held in the r_info field.  */\n+\n+#define ELF32_R_SYM(val)\t\t((val) >> 8)\n+#define ELF32_R_TYPE(val)\t\t((val) & 0xff)\n+#define ELF32_R_INFO(sym, type)\t\t(((sym) << 8) + ((type) & 0xff))\n+\n+#define ELF64_R_SYM(i)\t\t\t((i) >> 32)\n+#define ELF64_R_TYPE(i)\t\t\t((i) & 0xffffffff)\n+#define ELF64_R_INFO(sym,type)\t\t((((Elf64_Xword) (sym)) << 32) + (type))\n+\n+/* Program segment header.  */\n+\n+typedef struct\n+{\n+  Elf32_Word\tp_type;\t\t\t/* Segment type */\n+  Elf32_Off\tp_offset;\t\t/* Segment file offset */\n+  Elf32_Addr\tp_vaddr;\t\t/* Segment virtual address */\n+  Elf32_Addr\tp_paddr;\t\t/* Segment physical address */\n+  Elf32_Word\tp_filesz;\t\t/* Segment size in file */\n+  Elf32_Word\tp_memsz;\t\t/* Segment size in memory */\n+  Elf32_Word\tp_flags;\t\t/* Segment flags */\n+  Elf32_Word\tp_align;\t\t/* Segment alignment */\n+} Elf32_Phdr;\n+\n+typedef struct\n+{\n+  Elf64_Word\tp_type;\t\t\t/* Segment type */\n+  Elf64_Word\tp_flags;\t\t/* Segment flags */\n+  Elf64_Off\tp_offset;\t\t/* Segment file offset */\n+  Elf64_Addr\tp_vaddr;\t\t/* Segment virtual address */\n+  Elf64_Addr\tp_paddr;\t\t/* Segment physical address */\n+  Elf64_Xword\tp_filesz;\t\t/* Segment size in file */\n+  Elf64_Xword\tp_memsz;\t\t/* Segment size in memory */\n+  Elf64_Xword\tp_align;\t\t/* Segment alignment */\n+} Elf64_Phdr;\n+\n+/* Special value for e_phnum.  This indicates that the real number of\n+   program headers is too large to fit into e_phnum.  Instead the real\n+   value is in the field sh_info of section 0.  */\n+\n+#define PN_XNUM\t\t0xffff\n+\n+/* Legal values for p_type (segment type).  */\n+\n+#define\tPT_NULL\t\t0\t\t/* Program header table entry unused */\n+#define PT_LOAD\t\t1\t\t/* Loadable program segment */\n+#define PT_DYNAMIC\t2\t\t/* Dynamic linking information */\n+#define PT_INTERP\t3\t\t/* Program interpreter */\n+#define PT_NOTE\t\t4\t\t/* Auxiliary information */\n+#define PT_SHLIB\t5\t\t/* Reserved */\n+#define PT_PHDR\t\t6\t\t/* Entry for header table itself */\n+#define PT_TLS\t\t7\t\t/* Thread-local storage segment */\n+#define\tPT_NUM\t\t8\t\t/* Number of defined types */\n+#define PT_LOOS\t\t0x60000000\t/* Start of OS-specific */\n+#define PT_GNU_EH_FRAME\t0x6474e550\t/* GCC .eh_frame_hdr segment */\n+#define PT_GNU_STACK\t0x6474e551\t/* Indicates stack executability */\n+#define PT_GNU_RELRO\t0x6474e552\t/* Read-only after relocation */\n+#define PT_LOSUNW\t0x6ffffffa\n+#define PT_SUNWBSS\t0x6ffffffa\t/* Sun Specific segment */\n+#define PT_SUNWSTACK\t0x6ffffffb\t/* Stack segment */\n+#define PT_HISUNW\t0x6fffffff\n+#define PT_HIOS\t\t0x6fffffff\t/* End of OS-specific */\n+#define PT_LOPROC\t0x70000000\t/* Start of processor-specific */\n+#define PT_HIPROC\t0x7fffffff\t/* End of processor-specific */\n+\n+/* Legal values for p_flags (segment flags).  */\n+\n+#define PF_X\t\t(1 << 0)\t/* Segment is executable */\n+#define PF_W\t\t(1 << 1)\t/* Segment is writable */\n+#define PF_R\t\t(1 << 2)\t/* Segment is readable */\n+#define PF_MASKOS\t0x0ff00000\t/* OS-specific */\n+#define PF_MASKPROC\t0xf0000000\t/* Processor-specific */\n+\n+/* Legal values for note segment descriptor types for core files. */\n+\n+#define NT_PRSTATUS\t1\t\t/* Contains copy of prstatus struct */\n+#define NT_FPREGSET\t2\t\t/* Contains copy of fpregset struct */\n+#define NT_PRPSINFO\t3\t\t/* Contains copy of prpsinfo struct */\n+#define NT_PRXREG\t4\t\t/* Contains copy of prxregset struct */\n+#define NT_TASKSTRUCT\t4\t\t/* Contains copy of task structure */\n+#define NT_PLATFORM\t5\t\t/* String from sysinfo(SI_PLATFORM) */\n+#define NT_AUXV\t\t6\t\t/* Contains copy of auxv array */\n+#define NT_GWINDOWS\t7\t\t/* Contains copy of gwindows struct */\n+#define NT_ASRS\t\t8\t\t/* Contains copy of asrset struct */\n+#define NT_PSTATUS\t10\t\t/* Contains copy of pstatus struct */\n+#define NT_PSINFO\t13\t\t/* Contains copy of psinfo struct */\n+#define NT_PRCRED\t14\t\t/* Contains copy of prcred struct */\n+#define NT_UTSNAME\t15\t\t/* Contains copy of utsname struct */\n+#define NT_LWPSTATUS\t16\t\t/* Contains copy of lwpstatus struct */\n+#define NT_LWPSINFO\t17\t\t/* Contains copy of lwpinfo struct */\n+#define NT_PRFPXREG\t20\t\t/* Contains copy of fprxregset struct */\n+#define NT_PRXFPREG\t0x46e62b7f\t/* Contains copy of user_fxsr_struct */\n+#define NT_PPC_VMX\t0x100\t\t/* PowerPC Altivec/VMX registers */\n+#define NT_PPC_SPE\t0x101\t\t/* PowerPC SPE/EVR registers */\n+#define NT_PPC_VSX\t0x102\t\t/* PowerPC VSX registers */\n+#define NT_386_TLS\t0x200\t\t/* i386 TLS slots (struct user_desc) */\n+#define NT_386_IOPERM\t0x201\t\t/* x86 io permission bitmap (1=deny) */\n+#define NT_X86_XSTATE\t0x202\t\t/* x86 extended state using xsave */\n+\n+/* Legal values for the note segment descriptor types for object files.  */\n+\n+#define NT_VERSION\t1\t\t/* Contains a version string.  */\n+\n+\n+/* Dynamic section entry.  */\n+\n+typedef struct\n+{\n+  Elf32_Sword\td_tag;\t\t\t/* Dynamic entry type */\n+  union\n+    {\n+      Elf32_Word d_val;\t\t\t/* Integer value */\n+      Elf32_Addr d_ptr;\t\t\t/* Address value */\n+    } d_un;\n+} Elf32_Dyn;\n+\n+typedef struct\n+{\n+  Elf64_Sxword\td_tag;\t\t\t/* Dynamic entry type */\n+  union\n+    {\n+      Elf64_Xword d_val;\t\t/* Integer value */\n+      Elf64_Addr d_ptr;\t\t\t/* Address value */\n+    } d_un;\n+} Elf64_Dyn;\n+\n+/* Legal values for d_tag (dynamic entry type).  */\n+\n+#define DT_NULL\t\t0\t\t/* Marks end of dynamic section */\n+#define DT_NEEDED\t1\t\t/* Name of needed library */\n+#define DT_PLTRELSZ\t2\t\t/* Size in bytes of PLT relocs */\n+#define DT_PLTGOT\t3\t\t/* Processor defined value */\n+#define DT_HASH\t\t4\t\t/* Address of symbol hash table */\n+#define DT_STRTAB\t5\t\t/* Address of string table */\n+#define DT_SYMTAB\t6\t\t/* Address of symbol table */\n+#define DT_RELA\t\t7\t\t/* Address of Rela relocs */\n+#define DT_RELASZ\t8\t\t/* Total size of Rela relocs */\n+#define DT_RELAENT\t9\t\t/* Size of one Rela reloc */\n+#define DT_STRSZ\t10\t\t/* Size of string table */\n+#define DT_SYMENT\t11\t\t/* Size of one symbol table entry */\n+#define DT_INIT\t\t12\t\t/* Address of init function */\n+#define DT_FINI\t\t13\t\t/* Address of termination function */\n+#define DT_SONAME\t14\t\t/* Name of shared object */\n+#define DT_RPATH\t15\t\t/* Library search path (deprecated) */\n+#define DT_SYMBOLIC\t16\t\t/* Start symbol search here */\n+#define DT_REL\t\t17\t\t/* Address of Rel relocs */\n+#define DT_RELSZ\t18\t\t/* Total size of Rel relocs */\n+#define DT_RELENT\t19\t\t/* Size of one Rel reloc */\n+#define DT_PLTREL\t20\t\t/* Type of reloc in PLT */\n+#define DT_DEBUG\t21\t\t/* For debugging; unspecified */\n+#define DT_TEXTREL\t22\t\t/* Reloc might modify .text */\n+#define DT_JMPREL\t23\t\t/* Address of PLT relocs */\n+#define\tDT_BIND_NOW\t24\t\t/* Process relocations of object */\n+#define\tDT_INIT_ARRAY\t25\t\t/* Array with addresses of init fct */\n+#define\tDT_FINI_ARRAY\t26\t\t/* Array with addresses of fini fct */\n+#define\tDT_INIT_ARRAYSZ\t27\t\t/* Size in bytes of DT_INIT_ARRAY */\n+#define\tDT_FINI_ARRAYSZ\t28\t\t/* Size in bytes of DT_FINI_ARRAY */\n+#define DT_RUNPATH\t29\t\t/* Library search path */\n+#define DT_FLAGS\t30\t\t/* Flags for the object being loaded */\n+#define DT_ENCODING\t32\t\t/* Start of encoded range */\n+#define DT_PREINIT_ARRAY 32\t\t/* Array with addresses of preinit fct*/\n+#define DT_PREINIT_ARRAYSZ 33\t\t/* size in bytes of DT_PREINIT_ARRAY */\n+#define\tDT_NUM\t\t34\t\t/* Number used */\n+#define DT_LOOS\t\t0x6000000d\t/* Start of OS-specific */\n+#define DT_HIOS\t\t0x6ffff000\t/* End of OS-specific */\n+#define DT_LOPROC\t0x70000000\t/* Start of processor-specific */\n+#define DT_HIPROC\t0x7fffffff\t/* End of processor-specific */\n+#define\tDT_PROCNUM\tDT_MIPS_NUM\t/* Most used by any processor */\n+\n+/* DT_* entries which fall between DT_VALRNGHI & DT_VALRNGLO use the\n+   Dyn.d_un.d_val field of the Elf*_Dyn structure.  This follows Sun's\n+   approach.  */\n+#define DT_VALRNGLO\t0x6ffffd00\n+#define DT_GNU_PRELINKED 0x6ffffdf5\t/* Prelinking timestamp */\n+#define DT_GNU_CONFLICTSZ 0x6ffffdf6\t/* Size of conflict section */\n+#define DT_GNU_LIBLISTSZ 0x6ffffdf7\t/* Size of library list */\n+#define DT_CHECKSUM\t0x6ffffdf8\n+#define DT_PLTPADSZ\t0x6ffffdf9\n+#define DT_MOVEENT\t0x6ffffdfa\n+#define DT_MOVESZ\t0x6ffffdfb\n+#define DT_FEATURE_1\t0x6ffffdfc\t/* Feature selection (DTF_*).  */\n+#define DT_POSFLAG_1\t0x6ffffdfd\t/* Flags for DT_* entries, effecting\n+\t\t\t\t\t   the following DT_* entry.  */\n+#define DT_SYMINSZ\t0x6ffffdfe\t/* Size of syminfo table (in bytes) */\n+#define DT_SYMINENT\t0x6ffffdff\t/* Entry size of syminfo */\n+#define DT_VALRNGHI\t0x6ffffdff\n+#define DT_VALTAGIDX(tag)\t(DT_VALRNGHI - (tag))\t/* Reverse order! */\n+#define DT_VALNUM 12\n+\n+/* DT_* entries which fall between DT_ADDRRNGHI & DT_ADDRRNGLO use the\n+   Dyn.d_un.d_ptr field of the Elf*_Dyn structure.\n+\n+   If any adjustment is made to the ELF object after it has been\n+   built these entries will need to be adjusted.  */\n+#define DT_ADDRRNGLO\t0x6ffffe00\n+#define DT_GNU_HASH\t0x6ffffef5\t/* GNU-style hash table.  */\n+#define DT_TLSDESC_PLT\t0x6ffffef6\n+#define DT_TLSDESC_GOT\t0x6ffffef7\n+#define DT_GNU_CONFLICT\t0x6ffffef8\t/* Start of conflict section */\n+#define DT_GNU_LIBLIST\t0x6ffffef9\t/* Library list */\n+#define DT_CONFIG\t0x6ffffefa\t/* Configuration information.  */\n+#define DT_DEPAUDIT\t0x6ffffefb\t/* Dependency auditing.  */\n+#define DT_AUDIT\t0x6ffffefc\t/* Object auditing.  */\n+#define\tDT_PLTPAD\t0x6ffffefd\t/* PLT padding.  */\n+#define\tDT_MOVETAB\t0x6ffffefe\t/* Move table.  */\n+#define DT_SYMINFO\t0x6ffffeff\t/* Syminfo table.  */\n+#define DT_ADDRRNGHI\t0x6ffffeff\n+#define DT_ADDRTAGIDX(tag)\t(DT_ADDRRNGHI - (tag))\t/* Reverse order! */\n+#define DT_ADDRNUM 11\n+\n+/* The versioning entry types.  The next are defined as part of the\n+   GNU extension.  */\n+#define DT_VERSYM\t0x6ffffff0\n+\n+#define DT_RELACOUNT\t0x6ffffff9\n+#define DT_RELCOUNT\t0x6ffffffa\n+\n+/* These were chosen by Sun.  */\n+#define DT_FLAGS_1\t0x6ffffffb\t/* State flags, see DF_1_* below.  */\n+#define\tDT_VERDEF\t0x6ffffffc\t/* Address of version definition\n+\t\t\t\t\t   table */\n+#define\tDT_VERDEFNUM\t0x6ffffffd\t/* Number of version definitions */\n+#define\tDT_VERNEED\t0x6ffffffe\t/* Address of table with needed\n+\t\t\t\t\t   versions */\n+#define\tDT_VERNEEDNUM\t0x6fffffff\t/* Number of needed versions */\n+#define DT_VERSIONTAGIDX(tag)\t(DT_VERNEEDNUM - (tag))\t/* Reverse order! */\n+#define DT_VERSIONTAGNUM 16\n+\n+/* Sun added these machine-independent extensions in the \"processor-specific\"\n+   range.  Be compatible.  */\n+#define DT_AUXILIARY    0x7ffffffd      /* Shared object to load before self */\n+#define DT_FILTER       0x7fffffff      /* Shared object to get values from */\n+#define DT_EXTRATAGIDX(tag)\t((Elf32_Word)-((Elf32_Sword) (tag) <<1>>1)-1)\n+#define DT_EXTRANUM\t3\n+\n+/* Values of `d_un.d_val' in the DT_FLAGS entry.  */\n+#define DF_ORIGIN\t0x00000001\t/* Object may use DF_ORIGIN */\n+#define DF_SYMBOLIC\t0x00000002\t/* Symbol resolutions starts here */\n+#define DF_TEXTREL\t0x00000004\t/* Object contains text relocations */\n+#define DF_BIND_NOW\t0x00000008\t/* No lazy binding for this object */\n+#define DF_STATIC_TLS\t0x00000010\t/* Module uses the static TLS model */\n+\n+/* State flags selectable in the `d_un.d_val' element of the DT_FLAGS_1\n+   entry in the dynamic section.  */\n+#define DF_1_NOW\t0x00000001\t/* Set RTLD_NOW for this object.  */\n+#define DF_1_GLOBAL\t0x00000002\t/* Set RTLD_GLOBAL for this object.  */\n+#define DF_1_GROUP\t0x00000004\t/* Set RTLD_GROUP for this object.  */\n+#define DF_1_NODELETE\t0x00000008\t/* Set RTLD_NODELETE for this object.*/\n+#define DF_1_LOADFLTR\t0x00000010\t/* Trigger filtee loading at runtime.*/\n+#define DF_1_INITFIRST\t0x00000020\t/* Set RTLD_INITFIRST for this object*/\n+#define DF_1_NOOPEN\t0x00000040\t/* Set RTLD_NOOPEN for this object.  */\n+#define DF_1_ORIGIN\t0x00000080\t/* $ORIGIN must be handled.  */\n+#define DF_1_DIRECT\t0x00000100\t/* Direct binding enabled.  */\n+#define DF_1_TRANS\t0x00000200\n+#define DF_1_INTERPOSE\t0x00000400\t/* Object is used to interpose.  */\n+#define DF_1_NODEFLIB\t0x00000800\t/* Ignore default lib search path.  */\n+#define DF_1_NODUMP\t0x00001000\t/* Object can't be dldump'ed.  */\n+#define DF_1_CONFALT\t0x00002000\t/* Configuration alternative created.*/\n+#define DF_1_ENDFILTEE\t0x00004000\t/* Filtee terminates filters search. */\n+#define\tDF_1_DISPRELDNE\t0x00008000\t/* Disp reloc applied at build time. */\n+#define\tDF_1_DISPRELPND\t0x00010000\t/* Disp reloc applied at run-time.  */\n+\n+/* Flags for the feature selection in DT_FEATURE_1.  */\n+#define DTF_1_PARINIT\t0x00000001\n+#define DTF_1_CONFEXP\t0x00000002\n+\n+/* Flags in the DT_POSFLAG_1 entry effecting only the next DT_* entry.  */\n+#define DF_P1_LAZYLOAD\t0x00000001\t/* Lazyload following object.  */\n+#define DF_P1_GROUPPERM\t0x00000002\t/* Symbols from next object are not\n+\t\t\t\t\t   generally available.  */\n+\n+/* Version definition sections.  */\n+\n+typedef struct\n+{\n+  Elf32_Half\tvd_version;\t\t/* Version revision */\n+  Elf32_Half\tvd_flags;\t\t/* Version information */\n+  Elf32_Half\tvd_ndx;\t\t\t/* Version Index */\n+  Elf32_Half\tvd_cnt;\t\t\t/* Number of associated aux entries */\n+  Elf32_Word\tvd_hash;\t\t/* Version name hash value */\n+  Elf32_Word\tvd_aux;\t\t\t/* Offset in bytes to verdaux array */\n+  Elf32_Word\tvd_next;\t\t/* Offset in bytes to next verdef\n+\t\t\t\t\t   entry */\n+} Elf32_Verdef;\n+\n+typedef struct\n+{\n+  Elf64_Half\tvd_version;\t\t/* Version revision */\n+  Elf64_Half\tvd_flags;\t\t/* Version information */\n+  Elf64_Half\tvd_ndx;\t\t\t/* Version Index */\n+  Elf64_Half\tvd_cnt;\t\t\t/* Number of associated aux entries */\n+  Elf64_Word\tvd_hash;\t\t/* Version name hash value */\n+  Elf64_Word\tvd_aux;\t\t\t/* Offset in bytes to verdaux array */\n+  Elf64_Word\tvd_next;\t\t/* Offset in bytes to next verdef\n+\t\t\t\t\t   entry */\n+} Elf64_Verdef;\n+\n+\n+/* Legal values for vd_version (version revision).  */\n+#define VER_DEF_NONE\t0\t\t/* No version */\n+#define VER_DEF_CURRENT\t1\t\t/* Current version */\n+#define VER_DEF_NUM\t2\t\t/* Given version number */\n+\n+/* Legal values for vd_flags (version information flags).  */\n+#define VER_FLG_BASE\t0x1\t\t/* Version definition of file itself */\n+#define VER_FLG_WEAK\t0x2\t\t/* Weak version identifier */\n+\n+/* Versym symbol index values.  */\n+#define\tVER_NDX_LOCAL\t\t0\t/* Symbol is local.  */\n+#define\tVER_NDX_GLOBAL\t\t1\t/* Symbol is global.  */\n+#define\tVER_NDX_LORESERVE\t0xff00\t/* Beginning of reserved entries.  */\n+#define\tVER_NDX_ELIMINATE\t0xff01\t/* Symbol is to be eliminated.  */\n+\n+/* Auxialiary version information.  */\n+\n+typedef struct\n+{\n+  Elf32_Word\tvda_name;\t\t/* Version or dependency names */\n+  Elf32_Word\tvda_next;\t\t/* Offset in bytes to next verdaux\n+\t\t\t\t\t   entry */\n+} Elf32_Verdaux;\n+\n+typedef struct\n+{\n+  Elf64_Word\tvda_name;\t\t/* Version or dependency names */\n+  Elf64_Word\tvda_next;\t\t/* Offset in bytes to next verdaux\n+\t\t\t\t\t   entry */\n+} Elf64_Verdaux;\n+\n+\n+/* Version dependency section.  */\n+\n+typedef struct\n+{\n+  Elf32_Half\tvn_version;\t\t/* Version of structure */\n+  Elf32_Half\tvn_cnt;\t\t\t/* Number of associated aux entries */\n+  Elf32_Word\tvn_file;\t\t/* Offset of filename for this\n+\t\t\t\t\t   dependency */\n+  Elf32_Word\tvn_aux;\t\t\t/* Offset in bytes to vernaux array */\n+  Elf32_Word\tvn_next;\t\t/* Offset in bytes to next verneed\n+\t\t\t\t\t   entry */\n+} Elf32_Verneed;\n+\n+typedef struct\n+{\n+  Elf64_Half\tvn_version;\t\t/* Version of structure */\n+  Elf64_Half\tvn_cnt;\t\t\t/* Number of associated aux entries */\n+  Elf64_Word\tvn_file;\t\t/* Offset of filename for this\n+\t\t\t\t\t   dependency */\n+  Elf64_Word\tvn_aux;\t\t\t/* Offset in bytes to vernaux array */\n+  Elf64_Word\tvn_next;\t\t/* Offset in bytes to next verneed\n+\t\t\t\t\t   entry */\n+} Elf64_Verneed;\n+\n+\n+/* Legal values for vn_version (version revision).  */\n+#define VER_NEED_NONE\t 0\t\t/* No version */\n+#define VER_NEED_CURRENT 1\t\t/* Current version */\n+#define VER_NEED_NUM\t 2\t\t/* Given version number */\n+\n+/* Auxiliary needed version information.  */\n+\n+typedef struct\n+{\n+  Elf32_Word\tvna_hash;\t\t/* Hash value of dependency name */\n+  Elf32_Half\tvna_flags;\t\t/* Dependency specific information */\n+  Elf32_Half\tvna_other;\t\t/* Unused */\n+  Elf32_Word\tvna_name;\t\t/* Dependency name string offset */\n+  Elf32_Word\tvna_next;\t\t/* Offset in bytes to next vernaux\n+\t\t\t\t\t   entry */\n+} Elf32_Vernaux;\n+\n+typedef struct\n+{\n+  Elf64_Word\tvna_hash;\t\t/* Hash value of dependency name */\n+  Elf64_Half\tvna_flags;\t\t/* Dependency specific information */\n+  Elf64_Half\tvna_other;\t\t/* Unused */\n+  Elf64_Word\tvna_name;\t\t/* Dependency name string offset */\n+  Elf64_Word\tvna_next;\t\t/* Offset in bytes to next vernaux\n+\t\t\t\t\t   entry */\n+} Elf64_Vernaux;\n+\n+\n+/* Legal values for vna_flags.  */\n+#define VER_FLG_WEAK\t0x2\t\t/* Weak version identifier */\n+\n+\n+/* Auxiliary vector.  */\n+\n+/* This vector is normally only used by the program interpreter.  The\n+   usual definition in an ABI supplement uses the name auxv_t.  The\n+   vector is not usually defined in a standard <elf.h> file, but it\n+   can't hurt.  We rename it to avoid conflicts.  The sizes of these\n+   types are an arrangement between the exec server and the program\n+   interpreter, so we don't fully specify them here.  */\n+\n+typedef struct\n+{\n+  uint32_t a_type;\t\t/* Entry type */\n+  union\n+    {\n+      uint32_t a_val;\t\t/* Integer value */\n+      /* We use to have pointer elements added here.  We cannot do that,\n+\t though, since it does not work when using 32-bit definitions\n+\t on 64-bit platforms and vice versa.  */\n+    } a_un;\n+} Elf32_auxv_t;\n+\n+typedef struct\n+{\n+  uint64_t a_type;\t\t/* Entry type */\n+  union\n+    {\n+      uint64_t a_val;\t\t/* Integer value */\n+      /* We use to have pointer elements added here.  We cannot do that,\n+\t though, since it does not work when using 32-bit definitions\n+\t on 64-bit platforms and vice versa.  */\n+    } a_un;\n+} Elf64_auxv_t;\n+\n+/* Legal values for a_type (entry type).  */\n+\n+#define AT_NULL\t\t0\t\t/* End of vector */\n+#define AT_IGNORE\t1\t\t/* Entry should be ignored */\n+#define AT_EXECFD\t2\t\t/* File descriptor of program */\n+#define AT_PHDR\t\t3\t\t/* Program headers for program */\n+#define AT_PHENT\t4\t\t/* Size of program header entry */\n+#define AT_PHNUM\t5\t\t/* Number of program headers */\n+#define AT_PAGESZ\t6\t\t/* System page size */\n+#define AT_BASE\t\t7\t\t/* Base address of interpreter */\n+#define AT_FLAGS\t8\t\t/* Flags */\n+#define AT_ENTRY\t9\t\t/* Entry point of program */\n+#define AT_NOTELF\t10\t\t/* Program is not ELF */\n+#define AT_UID\t\t11\t\t/* Real uid */\n+#define AT_EUID\t\t12\t\t/* Effective uid */\n+#define AT_GID\t\t13\t\t/* Real gid */\n+#define AT_EGID\t\t14\t\t/* Effective gid */\n+#define AT_CLKTCK\t17\t\t/* Frequency of times() */\n+\n+/* Some more special a_type values describing the hardware.  */\n+#define AT_PLATFORM\t15\t\t/* String identifying platform.  */\n+#define AT_HWCAP\t16\t\t/* Machine dependent hints about\n+\t\t\t\t\t   processor capabilities.  */\n+\n+/* This entry gives some information about the FPU initialization\n+   performed by the kernel.  */\n+#define AT_FPUCW\t18\t\t/* Used FPU control word.  */\n+\n+/* Cache block sizes.  */\n+#define AT_DCACHEBSIZE\t19\t\t/* Data cache block size.  */\n+#define AT_ICACHEBSIZE\t20\t\t/* Instruction cache block size.  */\n+#define AT_UCACHEBSIZE\t21\t\t/* Unified cache block size.  */\n+\n+/* A special ignored value for PPC, used by the kernel to control the\n+   interpretation of the AUXV. Must be > 16.  */\n+#define AT_IGNOREPPC\t22\t\t/* Entry should be ignored.  */\n+\n+#define\tAT_SECURE\t23\t\t/* Boolean, was exec setuid-like?  */\n+\n+#define AT_BASE_PLATFORM 24\t\t/* String identifying real platforms.*/\n+\n+#define AT_RANDOM\t25\t\t/* Address of 16 random bytes.  */\n+\n+#define AT_EXECFN\t31\t\t/* Filename of executable.  */\n+\n+/* Pointer to the global system page used for system calls and other\n+   nice things.  */\n+#define AT_SYSINFO\t32\n+#define AT_SYSINFO_EHDR\t33\n+\n+/* Shapes of the caches.  Bits 0-3 contains associativity; bits 4-7 contains\n+   log2 of line size; mask those to get cache size.  */\n+#define AT_L1I_CACHESHAPE\t34\n+#define AT_L1D_CACHESHAPE\t35\n+#define AT_L2_CACHESHAPE\t36\n+#define AT_L3_CACHESHAPE\t37\n+\n+/* Note section contents.  Each entry in the note section begins with\n+   a header of a fixed form.  */\n+\n+typedef struct\n+{\n+  Elf32_Word n_namesz;\t\t\t/* Length of the note's name.  */\n+  Elf32_Word n_descsz;\t\t\t/* Length of the note's descriptor.  */\n+  Elf32_Word n_type;\t\t\t/* Type of the note.  */\n+} Elf32_Nhdr;\n+\n+typedef struct\n+{\n+  Elf64_Word n_namesz;\t\t\t/* Length of the note's name.  */\n+  Elf64_Word n_descsz;\t\t\t/* Length of the note's descriptor.  */\n+  Elf64_Word n_type;\t\t\t/* Type of the note.  */\n+} Elf64_Nhdr;\n+\n+/* Known names of notes.  */\n+\n+/* Solaris entries in the note section have this name.  */\n+#define ELF_NOTE_SOLARIS\t\"SUNW Solaris\"\n+\n+/* Note entries for GNU systems have this name.  */\n+#define ELF_NOTE_GNU\t\t\"GNU\"\n+\n+\n+/* Defined types of notes for Solaris.  */\n+\n+/* Value of descriptor (one word) is desired pagesize for the binary.  */\n+#define ELF_NOTE_PAGESIZE_HINT\t1\n+\n+\n+/* Defined note types for GNU systems.  */\n+\n+/* ABI information.  The descriptor consists of words:\n+   word 0: OS descriptor\n+   word 1: major version of the ABI\n+   word 2: minor version of the ABI\n+   word 3: subminor version of the ABI\n+*/\n+#define NT_GNU_ABI_TAG\t1\n+#define ELF_NOTE_ABI\tNT_GNU_ABI_TAG /* Old name.  */\n+\n+/* Known OSes.  These values can appear in word 0 of an\n+   NT_GNU_ABI_TAG note section entry.  */\n+#define ELF_NOTE_OS_LINUX\t0\n+#define ELF_NOTE_OS_GNU\t\t1\n+#define ELF_NOTE_OS_SOLARIS2\t2\n+#define ELF_NOTE_OS_FREEBSD\t3\n+\n+/* Synthetic hwcap information.  The descriptor begins with two words:\n+   word 0: number of entries\n+   word 1: bitmask of enabled entries\n+   Then follow variable-length entries, one byte followed by a\n+   '\\0'-terminated hwcap name string.  The byte gives the bit\n+   number to test if enabled, (1U << bit) & bitmask.  */\n+#define NT_GNU_HWCAP\t2\n+\n+/* Build ID bits as generated by ld --build-id.\n+   The descriptor consists of any nonzero number of bytes.  */\n+#define NT_GNU_BUILD_ID\t3\n+\n+/* Version note generated by GNU gold containing a version string.  */\n+#define NT_GNU_GOLD_VERSION\t4\n+\n+\n+/* Move records.  */\n+typedef struct\n+{\n+  Elf32_Xword m_value;\t\t/* Symbol value.  */\n+  Elf32_Word m_info;\t\t/* Size and index.  */\n+  Elf32_Word m_poffset;\t\t/* Symbol offset.  */\n+  Elf32_Half m_repeat;\t\t/* Repeat count.  */\n+  Elf32_Half m_stride;\t\t/* Stride info.  */\n+} Elf32_Move;\n+\n+typedef struct\n+{\n+  Elf64_Xword m_value;\t\t/* Symbol value.  */\n+  Elf64_Xword m_info;\t\t/* Size and index.  */\n+  Elf64_Xword m_poffset;\t/* Symbol offset.  */\n+  Elf64_Half m_repeat;\t\t/* Repeat count.  */\n+  Elf64_Half m_stride;\t\t/* Stride info.  */\n+} Elf64_Move;\n+\n+/* Macro to construct move records.  */\n+#define ELF32_M_SYM(info)\t((info) >> 8)\n+#define ELF32_M_SIZE(info)\t((unsigned char) (info))\n+#define ELF32_M_INFO(sym, size)\t(((sym) << 8) + (unsigned char) (size))\n+\n+#define ELF64_M_SYM(info)\tELF32_M_SYM (info)\n+#define ELF64_M_SIZE(info)\tELF32_M_SIZE (info)\n+#define ELF64_M_INFO(sym, size)\tELF32_M_INFO (sym, size)\n+\n+\n+/* Motorola 68k specific definitions.  */\n+\n+/* Values for Elf32_Ehdr.e_flags.  */\n+#define EF_CPU32\t0x00810000\n+\n+/* m68k relocs.  */\n+\n+#define R_68K_NONE\t0\t\t/* No reloc */\n+#define R_68K_32\t1\t\t/* Direct 32 bit  */\n+#define R_68K_16\t2\t\t/* Direct 16 bit  */\n+#define R_68K_8\t\t3\t\t/* Direct 8 bit  */\n+#define R_68K_PC32\t4\t\t/* PC relative 32 bit */\n+#define R_68K_PC16\t5\t\t/* PC relative 16 bit */\n+#define R_68K_PC8\t6\t\t/* PC relative 8 bit */\n+#define R_68K_GOT32\t7\t\t/* 32 bit PC relative GOT entry */\n+#define R_68K_GOT16\t8\t\t/* 16 bit PC relative GOT entry */\n+#define R_68K_GOT8\t9\t\t/* 8 bit PC relative GOT entry */\n+#define R_68K_GOT32O\t10\t\t/* 32 bit GOT offset */\n+#define R_68K_GOT16O\t11\t\t/* 16 bit GOT offset */\n+#define R_68K_GOT8O\t12\t\t/* 8 bit GOT offset */\n+#define R_68K_PLT32\t13\t\t/* 32 bit PC relative PLT address */\n+#define R_68K_PLT16\t14\t\t/* 16 bit PC relative PLT address */\n+#define R_68K_PLT8\t15\t\t/* 8 bit PC relative PLT address */\n+#define R_68K_PLT32O\t16\t\t/* 32 bit PLT offset */\n+#define R_68K_PLT16O\t17\t\t/* 16 bit PLT offset */\n+#define R_68K_PLT8O\t18\t\t/* 8 bit PLT offset */\n+#define R_68K_COPY\t19\t\t/* Copy symbol at runtime */\n+#define R_68K_GLOB_DAT\t20\t\t/* Create GOT entry */\n+#define R_68K_JMP_SLOT\t21\t\t/* Create PLT entry */\n+#define R_68K_RELATIVE\t22\t\t/* Adjust by program base */\n+#define R_68K_TLS_GD32      25          /* 32 bit GOT offset for GD */\n+#define R_68K_TLS_GD16      26          /* 16 bit GOT offset for GD */\n+#define R_68K_TLS_GD8       27          /* 8 bit GOT offset for GD */\n+#define R_68K_TLS_LDM32     28          /* 32 bit GOT offset for LDM */\n+#define R_68K_TLS_LDM16     29          /* 16 bit GOT offset for LDM */\n+#define R_68K_TLS_LDM8      30          /* 8 bit GOT offset for LDM */\n+#define R_68K_TLS_LDO32     31          /* 32 bit module-relative offset */\n+#define R_68K_TLS_LDO16     32          /* 16 bit module-relative offset */\n+#define R_68K_TLS_LDO8      33          /* 8 bit module-relative offset */\n+#define R_68K_TLS_IE32      34          /* 32 bit GOT offset for IE */\n+#define R_68K_TLS_IE16      35          /* 16 bit GOT offset for IE */\n+#define R_68K_TLS_IE8       36          /* 8 bit GOT offset for IE */\n+#define R_68K_TLS_LE32      37          /* 32 bit offset relative to\n+\t\t\t\t\t   static TLS block */\n+#define R_68K_TLS_LE16      38          /* 16 bit offset relative to\n+\t\t\t\t\t   static TLS block */\n+#define R_68K_TLS_LE8       39          /* 8 bit offset relative to\n+\t\t\t\t\t   static TLS block */\n+#define R_68K_TLS_DTPMOD32  40          /* 32 bit module number */\n+#define R_68K_TLS_DTPREL32  41          /* 32 bit module-relative offset */\n+#define R_68K_TLS_TPREL32   42          /* 32 bit TP-relative offset */\n+/* Keep this the last entry.  */\n+#define R_68K_NUM\t43\n+\n+/* Intel 80386 specific definitions.  */\n+\n+/* i386 relocs.  */\n+\n+#define R_386_NONE\t   0\t\t/* No reloc */\n+#define R_386_32\t   1\t\t/* Direct 32 bit  */\n+#define R_386_PC32\t   2\t\t/* PC relative 32 bit */\n+#define R_386_GOT32\t   3\t\t/* 32 bit GOT entry */\n+#define R_386_PLT32\t   4\t\t/* 32 bit PLT address */\n+#define R_386_COPY\t   5\t\t/* Copy symbol at runtime */\n+#define R_386_GLOB_DAT\t   6\t\t/* Create GOT entry */\n+#define R_386_JMP_SLOT\t   7\t\t/* Create PLT entry */\n+#define R_386_RELATIVE\t   8\t\t/* Adjust by program base */\n+#define R_386_GOTOFF\t   9\t\t/* 32 bit offset to GOT */\n+#define R_386_GOTPC\t   10\t\t/* 32 bit PC relative offset to GOT */\n+#define R_386_32PLT\t   11\n+#define R_386_TLS_TPOFF\t   14\t\t/* Offset in static TLS block */\n+#define R_386_TLS_IE\t   15\t\t/* Address of GOT entry for static TLS\n+\t\t\t\t\t   block offset */\n+#define R_386_TLS_GOTIE\t   16\t\t/* GOT entry for static TLS block\n+\t\t\t\t\t   offset */\n+#define R_386_TLS_LE\t   17\t\t/* Offset relative to static TLS\n+\t\t\t\t\t   block */\n+#define R_386_TLS_GD\t   18\t\t/* Direct 32 bit for GNU version of\n+\t\t\t\t\t   general dynamic thread local data */\n+#define R_386_TLS_LDM\t   19\t\t/* Direct 32 bit for GNU version of\n+\t\t\t\t\t   local dynamic thread local data\n+\t\t\t\t\t   in LE code */\n+#define R_386_16\t   20\n+#define R_386_PC16\t   21\n+#define R_386_8\t\t   22\n+#define R_386_PC8\t   23\n+#define R_386_TLS_GD_32\t   24\t\t/* Direct 32 bit for general dynamic\n+\t\t\t\t\t   thread local data */\n+#define R_386_TLS_GD_PUSH  25\t\t/* Tag for pushl in GD TLS code */\n+#define R_386_TLS_GD_CALL  26\t\t/* Relocation for call to\n+\t\t\t\t\t   __tls_get_addr() */\n+#define R_386_TLS_GD_POP   27\t\t/* Tag for popl in GD TLS code */\n+#define R_386_TLS_LDM_32   28\t\t/* Direct 32 bit for local dynamic\n+\t\t\t\t\t   thread local data in LE code */\n+#define R_386_TLS_LDM_PUSH 29\t\t/* Tag for pushl in LDM TLS code */\n+#define R_386_TLS_LDM_CALL 30\t\t/* Relocation for call to\n+\t\t\t\t\t   __tls_get_addr() in LDM code */\n+#define R_386_TLS_LDM_POP  31\t\t/* Tag for popl in LDM TLS code */\n+#define R_386_TLS_LDO_32   32\t\t/* Offset relative to TLS block */\n+#define R_386_TLS_IE_32\t   33\t\t/* GOT entry for negated static TLS\n+\t\t\t\t\t   block offset */\n+#define R_386_TLS_LE_32\t   34\t\t/* Negated offset relative to static\n+\t\t\t\t\t   TLS block */\n+#define R_386_TLS_DTPMOD32 35\t\t/* ID of module containing symbol */\n+#define R_386_TLS_DTPOFF32 36\t\t/* Offset in TLS block */\n+#define R_386_TLS_TPOFF32  37\t\t/* Negated offset in static TLS block */\n+/* 38? */\n+#define R_386_TLS_GOTDESC  39\t\t/* GOT offset for TLS descriptor.  */\n+#define R_386_TLS_DESC_CALL 40\t\t/* Marker of call through TLS\n+\t\t\t\t\t   descriptor for\n+\t\t\t\t\t   relaxation.  */\n+#define R_386_TLS_DESC     41\t\t/* TLS descriptor containing\n+\t\t\t\t\t   pointer to code and to\n+\t\t\t\t\t   argument, returning the TLS\n+\t\t\t\t\t   offset for the symbol.  */\n+#define R_386_IRELATIVE\t   42\t\t/* Adjust indirectly by program base */\n+/* Keep this the last entry.  */\n+#define R_386_NUM\t   43\n+\n+/* SUN SPARC specific definitions.  */\n+\n+/* Legal values for ST_TYPE subfield of st_info (symbol type).  */\n+\n+#define STT_SPARC_REGISTER\t13\t/* Global register reserved to app. */\n+\n+/* Values for Elf64_Ehdr.e_flags.  */\n+\n+#define EF_SPARCV9_MM\t\t3\n+#define EF_SPARCV9_TSO\t\t0\n+#define EF_SPARCV9_PSO\t\t1\n+#define EF_SPARCV9_RMO\t\t2\n+#define EF_SPARC_LEDATA\t\t0x800000 /* little endian data */\n+#define EF_SPARC_EXT_MASK\t0xFFFF00\n+#define EF_SPARC_32PLUS\t\t0x000100 /* generic V8+ features */\n+#define EF_SPARC_SUN_US1\t0x000200 /* Sun UltraSPARC1 extensions */\n+#define EF_SPARC_HAL_R1\t\t0x000400 /* HAL R1 extensions */\n+#define EF_SPARC_SUN_US3\t0x000800 /* Sun UltraSPARCIII extensions */\n+\n+/* SPARC relocs.  */\n+\n+#define R_SPARC_NONE\t\t0\t/* No reloc */\n+#define R_SPARC_8\t\t1\t/* Direct 8 bit */\n+#define R_SPARC_16\t\t2\t/* Direct 16 bit */\n+#define R_SPARC_32\t\t3\t/* Direct 32 bit */\n+#define R_SPARC_DISP8\t\t4\t/* PC relative 8 bit */\n+#define R_SPARC_DISP16\t\t5\t/* PC relative 16 bit */\n+#define R_SPARC_DISP32\t\t6\t/* PC relative 32 bit */\n+#define R_SPARC_WDISP30\t\t7\t/* PC relative 30 bit shifted */\n+#define R_SPARC_WDISP22\t\t8\t/* PC relative 22 bit shifted */\n+#define R_SPARC_HI22\t\t9\t/* High 22 bit */\n+#define R_SPARC_22\t\t10\t/* Direct 22 bit */\n+#define R_SPARC_13\t\t11\t/* Direct 13 bit */\n+#define R_SPARC_LO10\t\t12\t/* Truncated 10 bit */\n+#define R_SPARC_GOT10\t\t13\t/* Truncated 10 bit GOT entry */\n+#define R_SPARC_GOT13\t\t14\t/* 13 bit GOT entry */\n+#define R_SPARC_GOT22\t\t15\t/* 22 bit GOT entry shifted */\n+#define R_SPARC_PC10\t\t16\t/* PC relative 10 bit truncated */\n+#define R_SPARC_PC22\t\t17\t/* PC relative 22 bit shifted */\n+#define R_SPARC_WPLT30\t\t18\t/* 30 bit PC relative PLT address */\n+#define R_SPARC_COPY\t\t19\t/* Copy symbol at runtime */\n+#define R_SPARC_GLOB_DAT\t20\t/* Create GOT entry */\n+#define R_SPARC_JMP_SLOT\t21\t/* Create PLT entry */\n+#define R_SPARC_RELATIVE\t22\t/* Adjust by program base */\n+#define R_SPARC_UA32\t\t23\t/* Direct 32 bit unaligned */\n+\n+/* Additional Sparc64 relocs.  */\n+\n+#define R_SPARC_PLT32\t\t24\t/* Direct 32 bit ref to PLT entry */\n+#define R_SPARC_HIPLT22\t\t25\t/* High 22 bit PLT entry */\n+#define R_SPARC_LOPLT10\t\t26\t/* Truncated 10 bit PLT entry */\n+#define R_SPARC_PCPLT32\t\t27\t/* PC rel 32 bit ref to PLT entry */\n+#define R_SPARC_PCPLT22\t\t28\t/* PC rel high 22 bit PLT entry */\n+#define R_SPARC_PCPLT10\t\t29\t/* PC rel trunc 10 bit PLT entry */\n+#define R_SPARC_10\t\t30\t/* Direct 10 bit */\n+#define R_SPARC_11\t\t31\t/* Direct 11 bit */\n+#define R_SPARC_64\t\t32\t/* Direct 64 bit */\n+#define R_SPARC_OLO10\t\t33\t/* 10bit with secondary 13bit addend */\n+#define R_SPARC_HH22\t\t34\t/* Top 22 bits of direct 64 bit */\n+#define R_SPARC_HM10\t\t35\t/* High middle 10 bits of ... */\n+#define R_SPARC_LM22\t\t36\t/* Low middle 22 bits of ... */\n+#define R_SPARC_PC_HH22\t\t37\t/* Top 22 bits of pc rel 64 bit */\n+#define R_SPARC_PC_HM10\t\t38\t/* High middle 10 bit of ... */\n+#define R_SPARC_PC_LM22\t\t39\t/* Low miggle 22 bits of ... */\n+#define R_SPARC_WDISP16\t\t40\t/* PC relative 16 bit shifted */\n+#define R_SPARC_WDISP19\t\t41\t/* PC relative 19 bit shifted */\n+#define R_SPARC_GLOB_JMP\t42\t/* was part of v9 ABI but was removed */\n+#define R_SPARC_7\t\t43\t/* Direct 7 bit */\n+#define R_SPARC_5\t\t44\t/* Direct 5 bit */\n+#define R_SPARC_6\t\t45\t/* Direct 6 bit */\n+#define R_SPARC_DISP64\t\t46\t/* PC relative 64 bit */\n+#define R_SPARC_PLT64\t\t47\t/* Direct 64 bit ref to PLT entry */\n+#define R_SPARC_HIX22\t\t48\t/* High 22 bit complemented */\n+#define R_SPARC_LOX10\t\t49\t/* Truncated 11 bit complemented */\n+#define R_SPARC_H44\t\t50\t/* Direct high 12 of 44 bit */\n+#define R_SPARC_M44\t\t51\t/* Direct mid 22 of 44 bit */\n+#define R_SPARC_L44\t\t52\t/* Direct low 10 of 44 bit */\n+#define R_SPARC_REGISTER\t53\t/* Global register usage */\n+#define R_SPARC_UA64\t\t54\t/* Direct 64 bit unaligned */\n+#define R_SPARC_UA16\t\t55\t/* Direct 16 bit unaligned */\n+#define R_SPARC_TLS_GD_HI22\t56\n+#define R_SPARC_TLS_GD_LO10\t57\n+#define R_SPARC_TLS_GD_ADD\t58\n+#define R_SPARC_TLS_GD_CALL\t59\n+#define R_SPARC_TLS_LDM_HI22\t60\n+#define R_SPARC_TLS_LDM_LO10\t61\n+#define R_SPARC_TLS_LDM_ADD\t62\n+#define R_SPARC_TLS_LDM_CALL\t63\n+#define R_SPARC_TLS_LDO_HIX22\t64\n+#define R_SPARC_TLS_LDO_LOX10\t65\n+#define R_SPARC_TLS_LDO_ADD\t66\n+#define R_SPARC_TLS_IE_HI22\t67\n+#define R_SPARC_TLS_IE_LO10\t68\n+#define R_SPARC_TLS_IE_LD\t69\n+#define R_SPARC_TLS_IE_LDX\t70\n+#define R_SPARC_TLS_IE_ADD\t71\n+#define R_SPARC_TLS_LE_HIX22\t72\n+#define R_SPARC_TLS_LE_LOX10\t73\n+#define R_SPARC_TLS_DTPMOD32\t74\n+#define R_SPARC_TLS_DTPMOD64\t75\n+#define R_SPARC_TLS_DTPOFF32\t76\n+#define R_SPARC_TLS_DTPOFF64\t77\n+#define R_SPARC_TLS_TPOFF32\t78\n+#define R_SPARC_TLS_TPOFF64\t79\n+#define R_SPARC_GOTDATA_HIX22\t80\n+#define R_SPARC_GOTDATA_LOX10\t81\n+#define R_SPARC_GOTDATA_OP_HIX22\t82\n+#define R_SPARC_GOTDATA_OP_LOX10\t83\n+#define R_SPARC_GOTDATA_OP\t84\n+#define R_SPARC_H34\t\t85\n+#define R_SPARC_SIZE32\t\t86\n+#define R_SPARC_SIZE64\t\t87\n+#define R_SPARC_WDISP10\t\t88\n+#define R_SPARC_JMP_IREL\t248\n+#define R_SPARC_IRELATIVE\t249\n+#define R_SPARC_GNU_VTINHERIT\t250\n+#define R_SPARC_GNU_VTENTRY\t251\n+#define R_SPARC_REV32\t\t252\n+/* Keep this the last entry.  */\n+#define R_SPARC_NUM\t\t253\n+\n+/* For Sparc64, legal values for d_tag of Elf64_Dyn.  */\n+\n+#define DT_SPARC_REGISTER 0x70000001\n+#define DT_SPARC_NUM\t2\n+\n+/* MIPS R3000 specific definitions.  */\n+\n+/* Legal values for e_flags field of Elf32_Ehdr.  */\n+\n+#define EF_MIPS_NOREORDER   1\t\t/* A .noreorder directive was used */\n+#define EF_MIPS_PIC\t    2\t\t/* Contains PIC code */\n+#define EF_MIPS_CPIC\t    4\t\t/* Uses PIC calling sequence */\n+#define EF_MIPS_XGOT\t    8\n+#define EF_MIPS_64BIT_WHIRL 16\n+#define EF_MIPS_ABI2\t    32\n+#define EF_MIPS_ABI_ON32    64\n+#define EF_MIPS_ARCH\t    0xf0000000\t/* MIPS architecture level */\n+\n+/* Legal values for MIPS architecture level.  */\n+\n+#define EF_MIPS_ARCH_1\t    0x00000000\t/* -mips1 code.  */\n+#define EF_MIPS_ARCH_2\t    0x10000000\t/* -mips2 code.  */\n+#define EF_MIPS_ARCH_3\t    0x20000000\t/* -mips3 code.  */\n+#define EF_MIPS_ARCH_4\t    0x30000000\t/* -mips4 code.  */\n+#define EF_MIPS_ARCH_5\t    0x40000000\t/* -mips5 code.  */\n+#define EF_MIPS_ARCH_32\t    0x60000000\t/* MIPS32 code.  */\n+#define EF_MIPS_ARCH_64\t    0x70000000\t/* MIPS64 code.  */\n+\n+/* The following are non-official names and should not be used.  */\n+\n+#define E_MIPS_ARCH_1\t  0x00000000\t/* -mips1 code.  */\n+#define E_MIPS_ARCH_2\t  0x10000000\t/* -mips2 code.  */\n+#define E_MIPS_ARCH_3\t  0x20000000\t/* -mips3 code.  */\n+#define E_MIPS_ARCH_4\t  0x30000000\t/* -mips4 code.  */\n+#define E_MIPS_ARCH_5\t  0x40000000\t/* -mips5 code.  */\n+#define E_MIPS_ARCH_32\t  0x60000000\t/* MIPS32 code.  */\n+#define E_MIPS_ARCH_64\t  0x70000000\t/* MIPS64 code.  */\n+\n+/* Special section indices.  */\n+\n+#define SHN_MIPS_ACOMMON    0xff00\t/* Allocated common symbols */\n+#define SHN_MIPS_TEXT\t    0xff01\t/* Allocated test symbols.  */\n+#define SHN_MIPS_DATA\t    0xff02\t/* Allocated data symbols.  */\n+#define SHN_MIPS_SCOMMON    0xff03\t/* Small common symbols */\n+#define SHN_MIPS_SUNDEFINED 0xff04\t/* Small undefined symbols */\n+\n+/* Legal values for sh_type field of Elf32_Shdr.  */\n+\n+#define SHT_MIPS_LIBLIST       0x70000000 /* Shared objects used in link */\n+#define SHT_MIPS_MSYM\t       0x70000001\n+#define SHT_MIPS_CONFLICT      0x70000002 /* Conflicting symbols */\n+#define SHT_MIPS_GPTAB\t       0x70000003 /* Global data area sizes */\n+#define SHT_MIPS_UCODE\t       0x70000004 /* Reserved for SGI/MIPS compilers */\n+#define SHT_MIPS_DEBUG\t       0x70000005 /* MIPS ECOFF debugging information*/\n+#define SHT_MIPS_REGINFO       0x70000006 /* Register usage information */\n+#define SHT_MIPS_PACKAGE       0x70000007\n+#define SHT_MIPS_PACKSYM       0x70000008\n+#define SHT_MIPS_RELD\t       0x70000009\n+#define SHT_MIPS_IFACE         0x7000000b\n+#define SHT_MIPS_CONTENT       0x7000000c\n+#define SHT_MIPS_OPTIONS       0x7000000d /* Miscellaneous options.  */\n+#define SHT_MIPS_SHDR\t       0x70000010\n+#define SHT_MIPS_FDESC\t       0x70000011\n+#define SHT_MIPS_EXTSYM\t       0x70000012\n+#define SHT_MIPS_DENSE\t       0x70000013\n+#define SHT_MIPS_PDESC\t       0x70000014\n+#define SHT_MIPS_LOCSYM\t       0x70000015\n+#define SHT_MIPS_AUXSYM\t       0x70000016\n+#define SHT_MIPS_OPTSYM\t       0x70000017\n+#define SHT_MIPS_LOCSTR\t       0x70000018\n+#define SHT_MIPS_LINE\t       0x70000019\n+#define SHT_MIPS_RFDESC\t       0x7000001a\n+#define SHT_MIPS_DELTASYM      0x7000001b\n+#define SHT_MIPS_DELTAINST     0x7000001c\n+#define SHT_MIPS_DELTACLASS    0x7000001d\n+#define SHT_MIPS_DWARF         0x7000001e /* DWARF debugging information.  */\n+#define SHT_MIPS_DELTADECL     0x7000001f\n+#define SHT_MIPS_SYMBOL_LIB    0x70000020\n+#define SHT_MIPS_EVENTS\t       0x70000021 /* Event section.  */\n+#define SHT_MIPS_TRANSLATE     0x70000022\n+#define SHT_MIPS_PIXIE\t       0x70000023\n+#define SHT_MIPS_XLATE\t       0x70000024\n+#define SHT_MIPS_XLATE_DEBUG   0x70000025\n+#define SHT_MIPS_WHIRL\t       0x70000026\n+#define SHT_MIPS_EH_REGION     0x70000027\n+#define SHT_MIPS_XLATE_OLD     0x70000028\n+#define SHT_MIPS_PDR_EXCEPTION 0x70000029\n+\n+/* Legal values for sh_flags field of Elf32_Shdr.  */\n+\n+#define SHF_MIPS_GPREL\t 0x10000000\t/* Must be part of global data area */\n+#define SHF_MIPS_MERGE\t 0x20000000\n+#define SHF_MIPS_ADDR\t 0x40000000\n+#define SHF_MIPS_STRINGS 0x80000000\n+#define SHF_MIPS_NOSTRIP 0x08000000\n+#define SHF_MIPS_LOCAL\t 0x04000000\n+#define SHF_MIPS_NAMES\t 0x02000000\n+#define SHF_MIPS_NODUPE\t 0x01000000\n+\n+\n+/* Symbol tables.  */\n+\n+/* MIPS specific values for `st_other'.  */\n+#define STO_MIPS_DEFAULT\t\t0x0\n+#define STO_MIPS_INTERNAL\t\t0x1\n+#define STO_MIPS_HIDDEN\t\t\t0x2\n+#define STO_MIPS_PROTECTED\t\t0x3\n+#define STO_MIPS_PLT\t\t\t0x8\n+#define STO_MIPS_SC_ALIGN_UNUSED\t0xff\n+\n+/* MIPS specific values for `st_info'.  */\n+#define STB_MIPS_SPLIT_COMMON\t\t13\n+\n+/* Entries found in sections of type SHT_MIPS_GPTAB.  */\n+\n+typedef union\n+{\n+  struct\n+    {\n+      Elf32_Word gt_current_g_value;\t/* -G value used for compilation */\n+      Elf32_Word gt_unused;\t\t/* Not used */\n+    } gt_header;\t\t\t/* First entry in section */\n+  struct\n+    {\n+      Elf32_Word gt_g_value;\t\t/* If this value were used for -G */\n+      Elf32_Word gt_bytes;\t\t/* This many bytes would be used */\n+    } gt_entry;\t\t\t\t/* Subsequent entries in section */\n+} Elf32_gptab;\n+\n+/* Entry found in sections of type SHT_MIPS_REGINFO.  */\n+\n+typedef struct\n+{\n+  Elf32_Word\tri_gprmask;\t\t/* General registers used */\n+  Elf32_Word\tri_cprmask[4];\t\t/* Coprocessor registers used */\n+  Elf32_Sword\tri_gp_value;\t\t/* $gp register value */\n+} Elf32_RegInfo;\n+\n+/* Entries found in sections of type SHT_MIPS_OPTIONS.  */\n+\n+typedef struct\n+{\n+  unsigned char kind;\t\t/* Determines interpretation of the\n+\t\t\t\t   variable part of descriptor.  */\n+  unsigned char size;\t\t/* Size of descriptor, including header.  */\n+  Elf32_Section section;\t/* Section header index of section affected,\n+\t\t\t\t   0 for global options.  */\n+  Elf32_Word info;\t\t/* Kind-specific information.  */\n+} Elf_Options;\n+\n+/* Values for `kind' field in Elf_Options.  */\n+\n+#define ODK_NULL\t0\t/* Undefined.  */\n+#define ODK_REGINFO\t1\t/* Register usage information.  */\n+#define ODK_EXCEPTIONS\t2\t/* Exception processing options.  */\n+#define ODK_PAD\t\t3\t/* Section padding options.  */\n+#define ODK_HWPATCH\t4\t/* Hardware workarounds performed */\n+#define ODK_FILL\t5\t/* record the fill value used by the linker. */\n+#define ODK_TAGS\t6\t/* reserve space for desktop tools to write. */\n+#define ODK_HWAND\t7\t/* HW workarounds.  'AND' bits when merging. */\n+#define ODK_HWOR\t8\t/* HW workarounds.  'OR' bits when merging.  */\n+\n+/* Values for `info' in Elf_Options for ODK_EXCEPTIONS entries.  */\n+\n+#define OEX_FPU_MIN\t0x1f\t/* FPE's which MUST be enabled.  */\n+#define OEX_FPU_MAX\t0x1f00\t/* FPE's which MAY be enabled.  */\n+#define OEX_PAGE0\t0x10000\t/* page zero must be mapped.  */\n+#define OEX_SMM\t\t0x20000\t/* Force sequential memory mode?  */\n+#define OEX_FPDBUG\t0x40000\t/* Force floating point debug mode?  */\n+#define OEX_PRECISEFP\tOEX_FPDBUG\n+#define OEX_DISMISS\t0x80000\t/* Dismiss invalid address faults?  */\n+\n+#define OEX_FPU_INVAL\t0x10\n+#define OEX_FPU_DIV0\t0x08\n+#define OEX_FPU_OFLO\t0x04\n+#define OEX_FPU_UFLO\t0x02\n+#define OEX_FPU_INEX\t0x01\n+\n+/* Masks for `info' in Elf_Options for an ODK_HWPATCH entry.  */\n+\n+#define OHW_R4KEOP\t0x1\t/* R4000 end-of-page patch.  */\n+#define OHW_R8KPFETCH\t0x2\t/* may need R8000 prefetch patch.  */\n+#define OHW_R5KEOP\t0x4\t/* R5000 end-of-page patch.  */\n+#define OHW_R5KCVTL\t0x8\t/* R5000 cvt.[ds].l bug.  clean=1.  */\n+\n+#define OPAD_PREFIX\t0x1\n+#define OPAD_POSTFIX\t0x2\n+#define OPAD_SYMBOL\t0x4\n+\n+/* Entry found in `.options' section.  */\n+\n+typedef struct\n+{\n+  Elf32_Word hwp_flags1;\t/* Extra flags.  */\n+  Elf32_Word hwp_flags2;\t/* Extra flags.  */\n+} Elf_Options_Hw;\n+\n+/* Masks for `info' in ElfOptions for ODK_HWAND and ODK_HWOR entries.  */\n+\n+#define OHWA0_R4KEOP_CHECKED\t0x00000001\n+#define OHWA1_R4KEOP_CLEAN\t0x00000002\n+\n+/* MIPS relocs.  */\n+\n+#define R_MIPS_NONE\t\t0\t/* No reloc */\n+#define R_MIPS_16\t\t1\t/* Direct 16 bit */\n+#define R_MIPS_32\t\t2\t/* Direct 32 bit */\n+#define R_MIPS_REL32\t\t3\t/* PC relative 32 bit */\n+#define R_MIPS_26\t\t4\t/* Direct 26 bit shifted */\n+#define R_MIPS_HI16\t\t5\t/* High 16 bit */\n+#define R_MIPS_LO16\t\t6\t/* Low 16 bit */\n+#define R_MIPS_GPREL16\t\t7\t/* GP relative 16 bit */\n+#define R_MIPS_LITERAL\t\t8\t/* 16 bit literal entry */\n+#define R_MIPS_GOT16\t\t9\t/* 16 bit GOT entry */\n+#define R_MIPS_PC16\t\t10\t/* PC relative 16 bit */\n+#define R_MIPS_CALL16\t\t11\t/* 16 bit GOT entry for function */\n+#define R_MIPS_GPREL32\t\t12\t/* GP relative 32 bit */\n+\n+#define R_MIPS_SHIFT5\t\t16\n+#define R_MIPS_SHIFT6\t\t17\n+#define R_MIPS_64\t\t18\n+#define R_MIPS_GOT_DISP\t\t19\n+#define R_MIPS_GOT_PAGE\t\t20\n+#define R_MIPS_GOT_OFST\t\t21\n+#define R_MIPS_GOT_HI16\t\t22\n+#define R_MIPS_GOT_LO16\t\t23\n+#define R_MIPS_SUB\t\t24\n+#define R_MIPS_INSERT_A\t\t25\n+#define R_MIPS_INSERT_B\t\t26\n+#define R_MIPS_DELETE\t\t27\n+#define R_MIPS_HIGHER\t\t28\n+#define R_MIPS_HIGHEST\t\t29\n+#define R_MIPS_CALL_HI16\t30\n+#define R_MIPS_CALL_LO16\t31\n+#define R_MIPS_SCN_DISP\t\t32\n+#define R_MIPS_REL16\t\t33\n+#define R_MIPS_ADD_IMMEDIATE\t34\n+#define R_MIPS_PJUMP\t\t35\n+#define R_MIPS_RELGOT\t\t36\n+#define R_MIPS_JALR\t\t37\n+#define R_MIPS_TLS_DTPMOD32\t38\t/* Module number 32 bit */\n+#define R_MIPS_TLS_DTPREL32\t39\t/* Module-relative offset 32 bit */\n+#define R_MIPS_TLS_DTPMOD64\t40\t/* Module number 64 bit */\n+#define R_MIPS_TLS_DTPREL64\t41\t/* Module-relative offset 64 bit */\n+#define R_MIPS_TLS_GD\t\t42\t/* 16 bit GOT offset for GD */\n+#define R_MIPS_TLS_LDM\t\t43\t/* 16 bit GOT offset for LDM */\n+#define R_MIPS_TLS_DTPREL_HI16\t44\t/* Module-relative offset, high 16 bits */\n+#define R_MIPS_TLS_DTPREL_LO16\t45\t/* Module-relative offset, low 16 bits */\n+#define R_MIPS_TLS_GOTTPREL\t46\t/* 16 bit GOT offset for IE */\n+#define R_MIPS_TLS_TPREL32\t47\t/* TP-relative offset, 32 bit */\n+#define R_MIPS_TLS_TPREL64\t48\t/* TP-relative offset, 64 bit */\n+#define R_MIPS_TLS_TPREL_HI16\t49\t/* TP-relative offset, high 16 bits */\n+#define R_MIPS_TLS_TPREL_LO16\t50\t/* TP-relative offset, low 16 bits */\n+#define R_MIPS_GLOB_DAT\t\t51\n+#define R_MIPS_COPY\t\t126\n+#define R_MIPS_JUMP_SLOT        127\n+/* Keep this the last entry.  */\n+#define R_MIPS_NUM\t\t128\n+\n+/* Legal values for p_type field of Elf32_Phdr.  */\n+\n+#define PT_MIPS_REGINFO\t0x70000000\t/* Register usage information */\n+#define PT_MIPS_RTPROC  0x70000001\t/* Runtime procedure table. */\n+#define PT_MIPS_OPTIONS 0x70000002\n+\n+/* Special program header types.  */\n+\n+#define PF_MIPS_LOCAL\t0x10000000\n+\n+/* Legal values for d_tag field of Elf32_Dyn.  */\n+\n+#define DT_MIPS_RLD_VERSION  0x70000001\t/* Runtime linker interface version */\n+#define DT_MIPS_TIME_STAMP   0x70000002\t/* Timestamp */\n+#define DT_MIPS_ICHECKSUM    0x70000003\t/* Checksum */\n+#define DT_MIPS_IVERSION     0x70000004\t/* Version string (string tbl index) */\n+#define DT_MIPS_FLAGS\t     0x70000005\t/* Flags */\n+#define DT_MIPS_BASE_ADDRESS 0x70000006\t/* Base address */\n+#define DT_MIPS_MSYM\t     0x70000007\n+#define DT_MIPS_CONFLICT     0x70000008\t/* Address of CONFLICT section */\n+#define DT_MIPS_LIBLIST\t     0x70000009\t/* Address of LIBLIST section */\n+#define DT_MIPS_LOCAL_GOTNO  0x7000000a\t/* Number of local GOT entries */\n+#define DT_MIPS_CONFLICTNO   0x7000000b\t/* Number of CONFLICT entries */\n+#define DT_MIPS_LIBLISTNO    0x70000010\t/* Number of LIBLIST entries */\n+#define DT_MIPS_SYMTABNO     0x70000011\t/* Number of DYNSYM entries */\n+#define DT_MIPS_UNREFEXTNO   0x70000012\t/* First external DYNSYM */\n+#define DT_MIPS_GOTSYM\t     0x70000013\t/* First GOT entry in DYNSYM */\n+#define DT_MIPS_HIPAGENO     0x70000014\t/* Number of GOT page table entries */\n+#define DT_MIPS_RLD_MAP\t     0x70000016\t/* Address of run time loader map.  */\n+#define DT_MIPS_DELTA_CLASS  0x70000017\t/* Delta C++ class definition.  */\n+#define DT_MIPS_DELTA_CLASS_NO    0x70000018 /* Number of entries in\n+\t\t\t\t\t\tDT_MIPS_DELTA_CLASS.  */\n+#define DT_MIPS_DELTA_INSTANCE    0x70000019 /* Delta C++ class instances.  */\n+#define DT_MIPS_DELTA_INSTANCE_NO 0x7000001a /* Number of entries in\n+\t\t\t\t\t\tDT_MIPS_DELTA_INSTANCE.  */\n+#define DT_MIPS_DELTA_RELOC  0x7000001b /* Delta relocations.  */\n+#define DT_MIPS_DELTA_RELOC_NO 0x7000001c /* Number of entries in\n+\t\t\t\t\t     DT_MIPS_DELTA_RELOC.  */\n+#define DT_MIPS_DELTA_SYM    0x7000001d /* Delta symbols that Delta\n+\t\t\t\t\t   relocations refer to.  */\n+#define DT_MIPS_DELTA_SYM_NO 0x7000001e /* Number of entries in\n+\t\t\t\t\t   DT_MIPS_DELTA_SYM.  */\n+#define DT_MIPS_DELTA_CLASSSYM 0x70000020 /* Delta symbols that hold the\n+\t\t\t\t\t     class declaration.  */\n+#define DT_MIPS_DELTA_CLASSSYM_NO 0x70000021 /* Number of entries in\n+\t\t\t\t\t\tDT_MIPS_DELTA_CLASSSYM.  */\n+#define DT_MIPS_CXX_FLAGS    0x70000022 /* Flags indicating for C++ flavor.  */\n+#define DT_MIPS_PIXIE_INIT   0x70000023\n+#define DT_MIPS_SYMBOL_LIB   0x70000024\n+#define DT_MIPS_LOCALPAGE_GOTIDX 0x70000025\n+#define DT_MIPS_LOCAL_GOTIDX 0x70000026\n+#define DT_MIPS_HIDDEN_GOTIDX 0x70000027\n+#define DT_MIPS_PROTECTED_GOTIDX 0x70000028\n+#define DT_MIPS_OPTIONS\t     0x70000029 /* Address of .options.  */\n+#define DT_MIPS_INTERFACE    0x7000002a /* Address of .interface.  */\n+#define DT_MIPS_DYNSTR_ALIGN 0x7000002b\n+#define DT_MIPS_INTERFACE_SIZE 0x7000002c /* Size of the .interface section. */\n+#define DT_MIPS_RLD_TEXT_RESOLVE_ADDR 0x7000002d /* Address of rld_text_rsolve\n+\t\t\t\t\t\t    function stored in GOT.  */\n+#define DT_MIPS_PERF_SUFFIX  0x7000002e /* Default suffix of dso to be added\n+\t\t\t\t\t   by rld on dlopen() calls.  */\n+#define DT_MIPS_COMPACT_SIZE 0x7000002f /* (O32)Size of compact rel section. */\n+#define DT_MIPS_GP_VALUE     0x70000030 /* GP value for aux GOTs.  */\n+#define DT_MIPS_AUX_DYNAMIC  0x70000031 /* Address of aux .dynamic.  */\n+/* The address of .got.plt in an executable using the new non-PIC ABI.  */\n+#define DT_MIPS_PLTGOT\t     0x70000032\n+/* The base of the PLT in an executable using the new non-PIC ABI if that\n+   PLT is writable.  For a non-writable PLT, this is omitted or has a zero\n+   value.  */\n+#define DT_MIPS_RWPLT        0x70000034\n+#define DT_MIPS_NUM\t     0x35\n+\n+/* Legal values for DT_MIPS_FLAGS Elf32_Dyn entry.  */\n+\n+#define RHF_NONE\t\t   0\t\t/* No flags */\n+#define RHF_QUICKSTART\t\t   (1 << 0)\t/* Use quickstart */\n+#define RHF_NOTPOT\t\t   (1 << 1)\t/* Hash size not power of 2 */\n+#define RHF_NO_LIBRARY_REPLACEMENT (1 << 2)\t/* Ignore LD_LIBRARY_PATH */\n+#define RHF_NO_MOVE\t\t   (1 << 3)\n+#define RHF_SGI_ONLY\t\t   (1 << 4)\n+#define RHF_GUARANTEE_INIT\t   (1 << 5)\n+#define RHF_DELTA_C_PLUS_PLUS\t   (1 << 6)\n+#define RHF_GUARANTEE_START_INIT   (1 << 7)\n+#define RHF_PIXIE\t\t   (1 << 8)\n+#define RHF_DEFAULT_DELAY_LOAD\t   (1 << 9)\n+#define RHF_REQUICKSTART\t   (1 << 10)\n+#define RHF_REQUICKSTARTED\t   (1 << 11)\n+#define RHF_CORD\t\t   (1 << 12)\n+#define RHF_NO_UNRES_UNDEF\t   (1 << 13)\n+#define RHF_RLD_ORDER_SAFE\t   (1 << 14)\n+\n+/* Entries found in sections of type SHT_MIPS_LIBLIST.  */\n+\n+typedef struct\n+{\n+  Elf32_Word l_name;\t\t/* Name (string table index) */\n+  Elf32_Word l_time_stamp;\t/* Timestamp */\n+  Elf32_Word l_checksum;\t/* Checksum */\n+  Elf32_Word l_version;\t\t/* Interface version */\n+  Elf32_Word l_flags;\t\t/* Flags */\n+} Elf32_Lib;\n+\n+typedef struct\n+{\n+  Elf64_Word l_name;\t\t/* Name (string table index) */\n+  Elf64_Word l_time_stamp;\t/* Timestamp */\n+  Elf64_Word l_checksum;\t/* Checksum */\n+  Elf64_Word l_version;\t\t/* Interface version */\n+  Elf64_Word l_flags;\t\t/* Flags */\n+} Elf64_Lib;\n+\n+\n+/* Legal values for l_flags.  */\n+\n+#define LL_NONE\t\t  0\n+#define LL_EXACT_MATCH\t  (1 << 0)\t/* Require exact match */\n+#define LL_IGNORE_INT_VER (1 << 1)\t/* Ignore interface version */\n+#define LL_REQUIRE_MINOR  (1 << 2)\n+#define LL_EXPORTS\t  (1 << 3)\n+#define LL_DELAY_LOAD\t  (1 << 4)\n+#define LL_DELTA\t  (1 << 5)\n+\n+/* Entries found in sections of type SHT_MIPS_CONFLICT.  */\n+\n+typedef Elf32_Addr Elf32_Conflict;\n+\n+\n+/* HPPA specific definitions.  */\n+\n+/* Legal values for e_flags field of Elf32_Ehdr.  */\n+\n+#define EF_PARISC_TRAPNIL\t0x00010000 /* Trap nil pointer dereference.  */\n+#define EF_PARISC_EXT\t\t0x00020000 /* Program uses arch. extensions. */\n+#define EF_PARISC_LSB\t\t0x00040000 /* Program expects little endian. */\n+#define EF_PARISC_WIDE\t\t0x00080000 /* Program expects wide mode.  */\n+#define EF_PARISC_NO_KABP\t0x00100000 /* No kernel assisted branch\n+\t\t\t\t\t      prediction.  */\n+#define EF_PARISC_LAZYSWAP\t0x00400000 /* Allow lazy swapping.  */\n+#define EF_PARISC_ARCH\t\t0x0000ffff /* Architecture version.  */\n+\n+/* Defined values for `e_flags & EF_PARISC_ARCH' are:  */\n+\n+#define EFA_PARISC_1_0\t\t    0x020b /* PA-RISC 1.0 big-endian.  */\n+#define EFA_PARISC_1_1\t\t    0x0210 /* PA-RISC 1.1 big-endian.  */\n+#define EFA_PARISC_2_0\t\t    0x0214 /* PA-RISC 2.0 big-endian.  */\n+\n+/* Additional section indeces.  */\n+\n+#define SHN_PARISC_ANSI_COMMON\t0xff00\t   /* Section for tenatively declared\n+\t\t\t\t\t      symbols in ANSI C.  */\n+#define SHN_PARISC_HUGE_COMMON\t0xff01\t   /* Common blocks in huge model.  */\n+\n+/* Legal values for sh_type field of Elf32_Shdr.  */\n+\n+#define SHT_PARISC_EXT\t\t0x70000000 /* Contains product specific ext. */\n+#define SHT_PARISC_UNWIND\t0x70000001 /* Unwind information.  */\n+#define SHT_PARISC_DOC\t\t0x70000002 /* Debug info for optimized code. */\n+\n+/* Legal values for sh_flags field of Elf32_Shdr.  */\n+\n+#define SHF_PARISC_SHORT\t0x20000000 /* Section with short addressing. */\n+#define SHF_PARISC_HUGE\t\t0x40000000 /* Section far from gp.  */\n+#define SHF_PARISC_SBP\t\t0x80000000 /* Static branch prediction code. */\n+\n+/* Legal values for ST_TYPE subfield of st_info (symbol type).  */\n+\n+#define STT_PARISC_MILLICODE\t13\t/* Millicode function entry point.  */\n+\n+#define STT_HP_OPAQUE\t\t(STT_LOOS + 0x1)\n+#define STT_HP_STUB\t\t(STT_LOOS + 0x2)\n+\n+/* HPPA relocs.  */\n+\n+#define R_PARISC_NONE\t\t0\t/* No reloc.  */\n+#define R_PARISC_DIR32\t\t1\t/* Direct 32-bit reference.  */\n+#define R_PARISC_DIR21L\t\t2\t/* Left 21 bits of eff. address.  */\n+#define R_PARISC_DIR17R\t\t3\t/* Right 17 bits of eff. address.  */\n+#define R_PARISC_DIR17F\t\t4\t/* 17 bits of eff. address.  */\n+#define R_PARISC_DIR14R\t\t6\t/* Right 14 bits of eff. address.  */\n+#define R_PARISC_PCREL32\t9\t/* 32-bit rel. address.  */\n+#define R_PARISC_PCREL21L\t10\t/* Left 21 bits of rel. address.  */\n+#define R_PARISC_PCREL17R\t11\t/* Right 17 bits of rel. address.  */\n+#define R_PARISC_PCREL17F\t12\t/* 17 bits of rel. address.  */\n+#define R_PARISC_PCREL14R\t14\t/* Right 14 bits of rel. address.  */\n+#define R_PARISC_DPREL21L\t18\t/* Left 21 bits of rel. address.  */\n+#define R_PARISC_DPREL14R\t22\t/* Right 14 bits of rel. address.  */\n+#define R_PARISC_GPREL21L\t26\t/* GP-relative, left 21 bits.  */\n+#define R_PARISC_GPREL14R\t30\t/* GP-relative, right 14 bits.  */\n+#define R_PARISC_LTOFF21L\t34\t/* LT-relative, left 21 bits.  */\n+#define R_PARISC_LTOFF14R\t38\t/* LT-relative, right 14 bits.  */\n+#define R_PARISC_SECREL32\t41\t/* 32 bits section rel. address.  */\n+#define R_PARISC_SEGBASE\t48\t/* No relocation, set segment base.  */\n+#define R_PARISC_SEGREL32\t49\t/* 32 bits segment rel. address.  */\n+#define R_PARISC_PLTOFF21L\t50\t/* PLT rel. address, left 21 bits.  */\n+#define R_PARISC_PLTOFF14R\t54\t/* PLT rel. address, right 14 bits.  */\n+#define R_PARISC_LTOFF_FPTR32\t57\t/* 32 bits LT-rel. function pointer. */\n+#define R_PARISC_LTOFF_FPTR21L\t58\t/* LT-rel. fct ptr, left 21 bits. */\n+#define R_PARISC_LTOFF_FPTR14R\t62\t/* LT-rel. fct ptr, right 14 bits. */\n+#define R_PARISC_FPTR64\t\t64\t/* 64 bits function address.  */\n+#define R_PARISC_PLABEL32\t65\t/* 32 bits function address.  */\n+#define R_PARISC_PLABEL21L\t66\t/* Left 21 bits of fdesc address.  */\n+#define R_PARISC_PLABEL14R\t70\t/* Right 14 bits of fdesc address.  */\n+#define R_PARISC_PCREL64\t72\t/* 64 bits PC-rel. address.  */\n+#define R_PARISC_PCREL22F\t74\t/* 22 bits PC-rel. address.  */\n+#define R_PARISC_PCREL14WR\t75\t/* PC-rel. address, right 14 bits.  */\n+#define R_PARISC_PCREL14DR\t76\t/* PC rel. address, right 14 bits.  */\n+#define R_PARISC_PCREL16F\t77\t/* 16 bits PC-rel. address.  */\n+#define R_PARISC_PCREL16WF\t78\t/* 16 bits PC-rel. address.  */\n+#define R_PARISC_PCREL16DF\t79\t/* 16 bits PC-rel. address.  */\n+#define R_PARISC_DIR64\t\t80\t/* 64 bits of eff. address.  */\n+#define R_PARISC_DIR14WR\t83\t/* 14 bits of eff. address.  */\n+#define R_PARISC_DIR14DR\t84\t/* 14 bits of eff. address.  */\n+#define R_PARISC_DIR16F\t\t85\t/* 16 bits of eff. address.  */\n+#define R_PARISC_DIR16WF\t86\t/* 16 bits of eff. address.  */\n+#define R_PARISC_DIR16DF\t87\t/* 16 bits of eff. address.  */\n+#define R_PARISC_GPREL64\t88\t/* 64 bits of GP-rel. address.  */\n+#define R_PARISC_GPREL14WR\t91\t/* GP-rel. address, right 14 bits.  */\n+#define R_PARISC_GPREL14DR\t92\t/* GP-rel. address, right 14 bits.  */\n+#define R_PARISC_GPREL16F\t93\t/* 16 bits GP-rel. address.  */\n+#define R_PARISC_GPREL16WF\t94\t/* 16 bits GP-rel. address.  */\n+#define R_PARISC_GPREL16DF\t95\t/* 16 bits GP-rel. address.  */\n+#define R_PARISC_LTOFF64\t96\t/* 64 bits LT-rel. address.  */\n+#define R_PARISC_LTOFF14WR\t99\t/* LT-rel. address, right 14 bits.  */\n+#define R_PARISC_LTOFF14DR\t100\t/* LT-rel. address, right 14 bits.  */\n+#define R_PARISC_LTOFF16F\t101\t/* 16 bits LT-rel. address.  */\n+#define R_PARISC_LTOFF16WF\t102\t/* 16 bits LT-rel. address.  */\n+#define R_PARISC_LTOFF16DF\t103\t/* 16 bits LT-rel. address.  */\n+#define R_PARISC_SECREL64\t104\t/* 64 bits section rel. address.  */\n+#define R_PARISC_SEGREL64\t112\t/* 64 bits segment rel. address.  */\n+#define R_PARISC_PLTOFF14WR\t115\t/* PLT-rel. address, right 14 bits.  */\n+#define R_PARISC_PLTOFF14DR\t116\t/* PLT-rel. address, right 14 bits.  */\n+#define R_PARISC_PLTOFF16F\t117\t/* 16 bits LT-rel. address.  */\n+#define R_PARISC_PLTOFF16WF\t118\t/* 16 bits PLT-rel. address.  */\n+#define R_PARISC_PLTOFF16DF\t119\t/* 16 bits PLT-rel. address.  */\n+#define R_PARISC_LTOFF_FPTR64\t120\t/* 64 bits LT-rel. function ptr.  */\n+#define R_PARISC_LTOFF_FPTR14WR\t123\t/* LT-rel. fct. ptr., right 14 bits. */\n+#define R_PARISC_LTOFF_FPTR14DR\t124\t/* LT-rel. fct. ptr., right 14 bits. */\n+#define R_PARISC_LTOFF_FPTR16F\t125\t/* 16 bits LT-rel. function ptr.  */\n+#define R_PARISC_LTOFF_FPTR16WF\t126\t/* 16 bits LT-rel. function ptr.  */\n+#define R_PARISC_LTOFF_FPTR16DF\t127\t/* 16 bits LT-rel. function ptr.  */\n+#define R_PARISC_LORESERVE\t128\n+#define R_PARISC_COPY\t\t128\t/* Copy relocation.  */\n+#define R_PARISC_IPLT\t\t129\t/* Dynamic reloc, imported PLT */\n+#define R_PARISC_EPLT\t\t130\t/* Dynamic reloc, exported PLT */\n+#define R_PARISC_TPREL32\t153\t/* 32 bits TP-rel. address.  */\n+#define R_PARISC_TPREL21L\t154\t/* TP-rel. address, left 21 bits.  */\n+#define R_PARISC_TPREL14R\t158\t/* TP-rel. address, right 14 bits.  */\n+#define R_PARISC_LTOFF_TP21L\t162\t/* LT-TP-rel. address, left 21 bits. */\n+#define R_PARISC_LTOFF_TP14R\t166\t/* LT-TP-rel. address, right 14 bits.*/\n+#define R_PARISC_LTOFF_TP14F\t167\t/* 14 bits LT-TP-rel. address.  */\n+#define R_PARISC_TPREL64\t216\t/* 64 bits TP-rel. address.  */\n+#define R_PARISC_TPREL14WR\t219\t/* TP-rel. address, right 14 bits.  */\n+#define R_PARISC_TPREL14DR\t220\t/* TP-rel. address, right 14 bits.  */\n+#define R_PARISC_TPREL16F\t221\t/* 16 bits TP-rel. address.  */\n+#define R_PARISC_TPREL16WF\t222\t/* 16 bits TP-rel. address.  */\n+#define R_PARISC_TPREL16DF\t223\t/* 16 bits TP-rel. address.  */\n+#define R_PARISC_LTOFF_TP64\t224\t/* 64 bits LT-TP-rel. address.  */\n+#define R_PARISC_LTOFF_TP14WR\t227\t/* LT-TP-rel. address, right 14 bits.*/\n+#define R_PARISC_LTOFF_TP14DR\t228\t/* LT-TP-rel. address, right 14 bits.*/\n+#define R_PARISC_LTOFF_TP16F\t229\t/* 16 bits LT-TP-rel. address.  */\n+#define R_PARISC_LTOFF_TP16WF\t230\t/* 16 bits LT-TP-rel. address.  */\n+#define R_PARISC_LTOFF_TP16DF\t231\t/* 16 bits LT-TP-rel. address.  */\n+#define R_PARISC_GNU_VTENTRY\t232\n+#define R_PARISC_GNU_VTINHERIT\t233\n+#define R_PARISC_TLS_GD21L\t234\t/* GD 21-bit left.  */\n+#define R_PARISC_TLS_GD14R\t235\t/* GD 14-bit right.  */\n+#define R_PARISC_TLS_GDCALL\t236\t/* GD call to __t_g_a.  */\n+#define R_PARISC_TLS_LDM21L\t237\t/* LD module 21-bit left.  */\n+#define R_PARISC_TLS_LDM14R\t238\t/* LD module 14-bit right.  */\n+#define R_PARISC_TLS_LDMCALL\t239\t/* LD module call to __t_g_a.  */\n+#define R_PARISC_TLS_LDO21L\t240\t/* LD offset 21-bit left.  */\n+#define R_PARISC_TLS_LDO14R\t241\t/* LD offset 14-bit right.  */\n+#define R_PARISC_TLS_DTPMOD32\t242\t/* DTP module 32-bit.  */\n+#define R_PARISC_TLS_DTPMOD64\t243\t/* DTP module 64-bit.  */\n+#define R_PARISC_TLS_DTPOFF32\t244\t/* DTP offset 32-bit.  */\n+#define R_PARISC_TLS_DTPOFF64\t245\t/* DTP offset 32-bit.  */\n+#define R_PARISC_TLS_LE21L\tR_PARISC_TPREL21L\n+#define R_PARISC_TLS_LE14R\tR_PARISC_TPREL14R\n+#define R_PARISC_TLS_IE21L\tR_PARISC_LTOFF_TP21L\n+#define R_PARISC_TLS_IE14R\tR_PARISC_LTOFF_TP14R\n+#define R_PARISC_TLS_TPREL32\tR_PARISC_TPREL32\n+#define R_PARISC_TLS_TPREL64\tR_PARISC_TPREL64\n+#define R_PARISC_HIRESERVE\t255\n+\n+/* Legal values for p_type field of Elf32_Phdr/Elf64_Phdr.  */\n+\n+#define PT_HP_TLS\t\t(PT_LOOS + 0x0)\n+#define PT_HP_CORE_NONE\t\t(PT_LOOS + 0x1)\n+#define PT_HP_CORE_VERSION\t(PT_LOOS + 0x2)\n+#define PT_HP_CORE_KERNEL\t(PT_LOOS + 0x3)\n+#define PT_HP_CORE_COMM\t\t(PT_LOOS + 0x4)\n+#define PT_HP_CORE_PROC\t\t(PT_LOOS + 0x5)\n+#define PT_HP_CORE_LOADABLE\t(PT_LOOS + 0x6)\n+#define PT_HP_CORE_STACK\t(PT_LOOS + 0x7)\n+#define PT_HP_CORE_SHM\t\t(PT_LOOS + 0x8)\n+#define PT_HP_CORE_MMF\t\t(PT_LOOS + 0x9)\n+#define PT_HP_PARALLEL\t\t(PT_LOOS + 0x10)\n+#define PT_HP_FASTBIND\t\t(PT_LOOS + 0x11)\n+#define PT_HP_OPT_ANNOT\t\t(PT_LOOS + 0x12)\n+#define PT_HP_HSL_ANNOT\t\t(PT_LOOS + 0x13)\n+#define PT_HP_STACK\t\t(PT_LOOS + 0x14)\n+\n+#define PT_PARISC_ARCHEXT\t0x70000000\n+#define PT_PARISC_UNWIND\t0x70000001\n+\n+/* Legal values for p_flags field of Elf32_Phdr/Elf64_Phdr.  */\n+\n+#define PF_PARISC_SBP\t\t0x08000000\n+\n+#define PF_HP_PAGE_SIZE\t\t0x00100000\n+#define PF_HP_FAR_SHARED\t0x00200000\n+#define PF_HP_NEAR_SHARED\t0x00400000\n+#define PF_HP_CODE\t\t0x01000000\n+#define PF_HP_MODIFY\t\t0x02000000\n+#define PF_HP_LAZYSWAP\t\t0x04000000\n+#define PF_HP_SBP\t\t0x08000000\n+\n+\n+/* Alpha specific definitions.  */\n+\n+/* Legal values for e_flags field of Elf64_Ehdr.  */\n+\n+#define EF_ALPHA_32BIT\t\t1\t/* All addresses must be < 2GB.  */\n+#define EF_ALPHA_CANRELAX\t2\t/* Relocations for relaxing exist.  */\n+\n+/* Legal values for sh_type field of Elf64_Shdr.  */\n+\n+/* These two are primerily concerned with ECOFF debugging info.  */\n+#define SHT_ALPHA_DEBUG\t\t0x70000001\n+#define SHT_ALPHA_REGINFO\t0x70000002\n+\n+/* Legal values for sh_flags field of Elf64_Shdr.  */\n+\n+#define SHF_ALPHA_GPREL\t\t0x10000000\n+\n+/* Legal values for st_other field of Elf64_Sym.  */\n+#define STO_ALPHA_NOPV\t\t0x80\t/* No PV required.  */\n+#define STO_ALPHA_STD_GPLOAD\t0x88\t/* PV only used for initial ldgp.  */\n+\n+/* Alpha relocs.  */\n+\n+#define R_ALPHA_NONE\t\t0\t/* No reloc */\n+#define R_ALPHA_REFLONG\t\t1\t/* Direct 32 bit */\n+#define R_ALPHA_REFQUAD\t\t2\t/* Direct 64 bit */\n+#define R_ALPHA_GPREL32\t\t3\t/* GP relative 32 bit */\n+#define R_ALPHA_LITERAL\t\t4\t/* GP relative 16 bit w/optimization */\n+#define R_ALPHA_LITUSE\t\t5\t/* Optimization hint for LITERAL */\n+#define R_ALPHA_GPDISP\t\t6\t/* Add displacement to GP */\n+#define R_ALPHA_BRADDR\t\t7\t/* PC+4 relative 23 bit shifted */\n+#define R_ALPHA_HINT\t\t8\t/* PC+4 relative 16 bit shifted */\n+#define R_ALPHA_SREL16\t\t9\t/* PC relative 16 bit */\n+#define R_ALPHA_SREL32\t\t10\t/* PC relative 32 bit */\n+#define R_ALPHA_SREL64\t\t11\t/* PC relative 64 bit */\n+#define R_ALPHA_GPRELHIGH\t17\t/* GP relative 32 bit, high 16 bits */\n+#define R_ALPHA_GPRELLOW\t18\t/* GP relative 32 bit, low 16 bits */\n+#define R_ALPHA_GPREL16\t\t19\t/* GP relative 16 bit */\n+#define R_ALPHA_COPY\t\t24\t/* Copy symbol at runtime */\n+#define R_ALPHA_GLOB_DAT\t25\t/* Create GOT entry */\n+#define R_ALPHA_JMP_SLOT\t26\t/* Create PLT entry */\n+#define R_ALPHA_RELATIVE\t27\t/* Adjust by program base */\n+#define R_ALPHA_TLS_GD_HI\t28\n+#define R_ALPHA_TLSGD\t\t29\n+#define R_ALPHA_TLS_LDM\t\t30\n+#define R_ALPHA_DTPMOD64\t31\n+#define R_ALPHA_GOTDTPREL\t32\n+#define R_ALPHA_DTPREL64\t33\n+#define R_ALPHA_DTPRELHI\t34\n+#define R_ALPHA_DTPRELLO\t35\n+#define R_ALPHA_DTPREL16\t36\n+#define R_ALPHA_GOTTPREL\t37\n+#define R_ALPHA_TPREL64\t\t38\n+#define R_ALPHA_TPRELHI\t\t39\n+#define R_ALPHA_TPRELLO\t\t40\n+#define R_ALPHA_TPREL16\t\t41\n+/* Keep this the last entry.  */\n+#define R_ALPHA_NUM\t\t46\n+\n+/* Magic values of the LITUSE relocation addend.  */\n+#define LITUSE_ALPHA_ADDR\t0\n+#define LITUSE_ALPHA_BASE\t1\n+#define LITUSE_ALPHA_BYTOFF\t2\n+#define LITUSE_ALPHA_JSR\t3\n+#define LITUSE_ALPHA_TLS_GD\t4\n+#define LITUSE_ALPHA_TLS_LDM\t5\n+\n+/* Legal values for d_tag of Elf64_Dyn.  */\n+#define DT_ALPHA_PLTRO\t\t(DT_LOPROC + 0)\n+#define DT_ALPHA_NUM\t\t1\n+\n+/* PowerPC specific declarations */\n+\n+/* Values for Elf32/64_Ehdr.e_flags.  */\n+#define EF_PPC_EMB\t\t0x80000000\t/* PowerPC embedded flag */\n+\n+/* Cygnus local bits below */\n+#define EF_PPC_RELOCATABLE\t0x00010000\t/* PowerPC -mrelocatable flag*/\n+#define EF_PPC_RELOCATABLE_LIB\t0x00008000\t/* PowerPC -mrelocatable-lib\n+\t\t\t\t\t\t   flag */\n+\n+/* PowerPC relocations defined by the ABIs */\n+#define R_PPC_NONE\t\t0\n+#define R_PPC_ADDR32\t\t1\t/* 32bit absolute address */\n+#define R_PPC_ADDR24\t\t2\t/* 26bit address, 2 bits ignored.  */\n+#define R_PPC_ADDR16\t\t3\t/* 16bit absolute address */\n+#define R_PPC_ADDR16_LO\t\t4\t/* lower 16bit of absolute address */\n+#define R_PPC_ADDR16_HI\t\t5\t/* high 16bit of absolute address */\n+#define R_PPC_ADDR16_HA\t\t6\t/* adjusted high 16bit */\n+#define R_PPC_ADDR14\t\t7\t/* 16bit address, 2 bits ignored */\n+#define R_PPC_ADDR14_BRTAKEN\t8\n+#define R_PPC_ADDR14_BRNTAKEN\t9\n+#define R_PPC_REL24\t\t10\t/* PC relative 26 bit */\n+#define R_PPC_REL14\t\t11\t/* PC relative 16 bit */\n+#define R_PPC_REL14_BRTAKEN\t12\n+#define R_PPC_REL14_BRNTAKEN\t13\n+#define R_PPC_GOT16\t\t14\n+#define R_PPC_GOT16_LO\t\t15\n+#define R_PPC_GOT16_HI\t\t16\n+#define R_PPC_GOT16_HA\t\t17\n+#define R_PPC_PLTREL24\t\t18\n+#define R_PPC_COPY\t\t19\n+#define R_PPC_GLOB_DAT\t\t20\n+#define R_PPC_JMP_SLOT\t\t21\n+#define R_PPC_RELATIVE\t\t22\n+#define R_PPC_LOCAL24PC\t\t23\n+#define R_PPC_UADDR32\t\t24\n+#define R_PPC_UADDR16\t\t25\n+#define R_PPC_REL32\t\t26\n+#define R_PPC_PLT32\t\t27\n+#define R_PPC_PLTREL32\t\t28\n+#define R_PPC_PLT16_LO\t\t29\n+#define R_PPC_PLT16_HI\t\t30\n+#define R_PPC_PLT16_HA\t\t31\n+#define R_PPC_SDAREL16\t\t32\n+#define R_PPC_SECTOFF\t\t33\n+#define R_PPC_SECTOFF_LO\t34\n+#define R_PPC_SECTOFF_HI\t35\n+#define R_PPC_SECTOFF_HA\t36\n+\n+/* PowerPC relocations defined for the TLS access ABI.  */\n+#define R_PPC_TLS\t\t67 /* none\t(sym+add)@tls */\n+#define R_PPC_DTPMOD32\t\t68 /* word32\t(sym+add)@dtpmod */\n+#define R_PPC_TPREL16\t\t69 /* half16*\t(sym+add)@tprel */\n+#define R_PPC_TPREL16_LO\t70 /* half16\t(sym+add)@tprel@l */\n+#define R_PPC_TPREL16_HI\t71 /* half16\t(sym+add)@tprel@h */\n+#define R_PPC_TPREL16_HA\t72 /* half16\t(sym+add)@tprel@ha */\n+#define R_PPC_TPREL32\t\t73 /* word32\t(sym+add)@tprel */\n+#define R_PPC_DTPREL16\t\t74 /* half16*\t(sym+add)@dtprel */\n+#define R_PPC_DTPREL16_LO\t75 /* half16\t(sym+add)@dtprel@l */\n+#define R_PPC_DTPREL16_HI\t76 /* half16\t(sym+add)@dtprel@h */\n+#define R_PPC_DTPREL16_HA\t77 /* half16\t(sym+add)@dtprel@ha */\n+#define R_PPC_DTPREL32\t\t78 /* word32\t(sym+add)@dtprel */\n+#define R_PPC_GOT_TLSGD16\t79 /* half16*\t(sym+add)@got@tlsgd */\n+#define R_PPC_GOT_TLSGD16_LO\t80 /* half16\t(sym+add)@got@tlsgd@l */\n+#define R_PPC_GOT_TLSGD16_HI\t81 /* half16\t(sym+add)@got@tlsgd@h */\n+#define R_PPC_GOT_TLSGD16_HA\t82 /* half16\t(sym+add)@got@tlsgd@ha */\n+#define R_PPC_GOT_TLSLD16\t83 /* half16*\t(sym+add)@got@tlsld */\n+#define R_PPC_GOT_TLSLD16_LO\t84 /* half16\t(sym+add)@got@tlsld@l */\n+#define R_PPC_GOT_TLSLD16_HI\t85 /* half16\t(sym+add)@got@tlsld@h */\n+#define R_PPC_GOT_TLSLD16_HA\t86 /* half16\t(sym+add)@got@tlsld@ha */\n+#define R_PPC_GOT_TPREL16\t87 /* half16*\t(sym+add)@got@tprel */\n+#define R_PPC_GOT_TPREL16_LO\t88 /* half16\t(sym+add)@got@tprel@l */\n+#define R_PPC_GOT_TPREL16_HI\t89 /* half16\t(sym+add)@got@tprel@h */\n+#define R_PPC_GOT_TPREL16_HA\t90 /* half16\t(sym+add)@got@tprel@ha */\n+#define R_PPC_GOT_DTPREL16\t91 /* half16*\t(sym+add)@got@dtprel */\n+#define R_PPC_GOT_DTPREL16_LO\t92 /* half16*\t(sym+add)@got@dtprel@l */\n+#define R_PPC_GOT_DTPREL16_HI\t93 /* half16*\t(sym+add)@got@dtprel@h */\n+#define R_PPC_GOT_DTPREL16_HA\t94 /* half16*\t(sym+add)@got@dtprel@ha */\n+\n+/* The remaining relocs are from the Embedded ELF ABI, and are not\n+   in the SVR4 ELF ABI.  */\n+#define R_PPC_EMB_NADDR32\t101\n+#define R_PPC_EMB_NADDR16\t102\n+#define R_PPC_EMB_NADDR16_LO\t103\n+#define R_PPC_EMB_NADDR16_HI\t104\n+#define R_PPC_EMB_NADDR16_HA\t105\n+#define R_PPC_EMB_SDAI16\t106\n+#define R_PPC_EMB_SDA2I16\t107\n+#define R_PPC_EMB_SDA2REL\t108\n+#define R_PPC_EMB_SDA21\t\t109\t/* 16 bit offset in SDA */\n+#define R_PPC_EMB_MRKREF\t110\n+#define R_PPC_EMB_RELSEC16\t111\n+#define R_PPC_EMB_RELST_LO\t112\n+#define R_PPC_EMB_RELST_HI\t113\n+#define R_PPC_EMB_RELST_HA\t114\n+#define R_PPC_EMB_BIT_FLD\t115\n+#define R_PPC_EMB_RELSDA\t116\t/* 16 bit relative offset in SDA */\n+\n+/* Diab tool relocations.  */\n+#define R_PPC_DIAB_SDA21_LO\t180\t/* like EMB_SDA21, but lower 16 bit */\n+#define R_PPC_DIAB_SDA21_HI\t181\t/* like EMB_SDA21, but high 16 bit */\n+#define R_PPC_DIAB_SDA21_HA\t182\t/* like EMB_SDA21, adjusted high 16 */\n+#define R_PPC_DIAB_RELSDA_LO\t183\t/* like EMB_RELSDA, but lower 16 bit */\n+#define R_PPC_DIAB_RELSDA_HI\t184\t/* like EMB_RELSDA, but high 16 bit */\n+#define R_PPC_DIAB_RELSDA_HA\t185\t/* like EMB_RELSDA, adjusted high 16 */\n+\n+/* GNU extension to support local ifunc.  */\n+#define R_PPC_IRELATIVE\t\t248\n+\n+/* GNU relocs used in PIC code sequences.  */\n+#define R_PPC_REL16\t\t249\t/* half16   (sym+add-.) */\n+#define R_PPC_REL16_LO\t\t250\t/* half16   (sym+add-.)@l */\n+#define R_PPC_REL16_HI\t\t251\t/* half16   (sym+add-.)@h */\n+#define R_PPC_REL16_HA\t\t252\t/* half16   (sym+add-.)@ha */\n+\n+/* This is a phony reloc to handle any old fashioned TOC16 references\n+   that may still be in object files.  */\n+#define R_PPC_TOC16\t\t255\n+\n+/* PowerPC specific values for the Dyn d_tag field.  */\n+#define DT_PPC_GOT\t\t(DT_LOPROC + 0)\n+#define DT_PPC_NUM\t\t1\n+\n+/* PowerPC64 relocations defined by the ABIs */\n+#define R_PPC64_NONE\t\tR_PPC_NONE\n+#define R_PPC64_ADDR32\t\tR_PPC_ADDR32 /* 32bit absolute address */\n+#define R_PPC64_ADDR24\t\tR_PPC_ADDR24 /* 26bit address, word aligned */\n+#define R_PPC64_ADDR16\t\tR_PPC_ADDR16 /* 16bit absolute address */\n+#define R_PPC64_ADDR16_LO\tR_PPC_ADDR16_LO\t/* lower 16bits of address */\n+#define R_PPC64_ADDR16_HI\tR_PPC_ADDR16_HI\t/* high 16bits of address. */\n+#define R_PPC64_ADDR16_HA\tR_PPC_ADDR16_HA /* adjusted high 16bits.  */\n+#define R_PPC64_ADDR14\t\tR_PPC_ADDR14 /* 16bit address, word aligned */\n+#define R_PPC64_ADDR14_BRTAKEN\tR_PPC_ADDR14_BRTAKEN\n+#define R_PPC64_ADDR14_BRNTAKEN\tR_PPC_ADDR14_BRNTAKEN\n+#define R_PPC64_REL24\t\tR_PPC_REL24 /* PC-rel. 26 bit, word aligned */\n+#define R_PPC64_REL14\t\tR_PPC_REL14 /* PC relative 16 bit */\n+#define R_PPC64_REL14_BRTAKEN\tR_PPC_REL14_BRTAKEN\n+#define R_PPC64_REL14_BRNTAKEN\tR_PPC_REL14_BRNTAKEN\n+#define R_PPC64_GOT16\t\tR_PPC_GOT16\n+#define R_PPC64_GOT16_LO\tR_PPC_GOT16_LO\n+#define R_PPC64_GOT16_HI\tR_PPC_GOT16_HI\n+#define R_PPC64_GOT16_HA\tR_PPC_GOT16_HA\n+\n+#define R_PPC64_COPY\t\tR_PPC_COPY\n+#define R_PPC64_GLOB_DAT\tR_PPC_GLOB_DAT\n+#define R_PPC64_JMP_SLOT\tR_PPC_JMP_SLOT\n+#define R_PPC64_RELATIVE\tR_PPC_RELATIVE\n+\n+#define R_PPC64_UADDR32\t\tR_PPC_UADDR32\n+#define R_PPC64_UADDR16\t\tR_PPC_UADDR16\n+#define R_PPC64_REL32\t\tR_PPC_REL32\n+#define R_PPC64_PLT32\t\tR_PPC_PLT32\n+#define R_PPC64_PLTREL32\tR_PPC_PLTREL32\n+#define R_PPC64_PLT16_LO\tR_PPC_PLT16_LO\n+#define R_PPC64_PLT16_HI\tR_PPC_PLT16_HI\n+#define R_PPC64_PLT16_HA\tR_PPC_PLT16_HA\n+\n+#define R_PPC64_SECTOFF\t\tR_PPC_SECTOFF\n+#define R_PPC64_SECTOFF_LO\tR_PPC_SECTOFF_LO\n+#define R_PPC64_SECTOFF_HI\tR_PPC_SECTOFF_HI\n+#define R_PPC64_SECTOFF_HA\tR_PPC_SECTOFF_HA\n+#define R_PPC64_ADDR30\t\t37 /* word30 (S + A - P) >> 2 */\n+#define R_PPC64_ADDR64\t\t38 /* doubleword64 S + A */\n+#define R_PPC64_ADDR16_HIGHER\t39 /* half16 #higher(S + A) */\n+#define R_PPC64_ADDR16_HIGHERA\t40 /* half16 #highera(S + A) */\n+#define R_PPC64_ADDR16_HIGHEST\t41 /* half16 #highest(S + A) */\n+#define R_PPC64_ADDR16_HIGHESTA\t42 /* half16 #highesta(S + A) */\n+#define R_PPC64_UADDR64\t\t43 /* doubleword64 S + A */\n+#define R_PPC64_REL64\t\t44 /* doubleword64 S + A - P */\n+#define R_PPC64_PLT64\t\t45 /* doubleword64 L + A */\n+#define R_PPC64_PLTREL64\t46 /* doubleword64 L + A - P */\n+#define R_PPC64_TOC16\t\t47 /* half16* S + A - .TOC */\n+#define R_PPC64_TOC16_LO\t48 /* half16 #lo(S + A - .TOC.) */\n+#define R_PPC64_TOC16_HI\t49 /* half16 #hi(S + A - .TOC.) */\n+#define R_PPC64_TOC16_HA\t50 /* half16 #ha(S + A - .TOC.) */\n+#define R_PPC64_TOC\t\t51 /* doubleword64 .TOC */\n+#define R_PPC64_PLTGOT16\t52 /* half16* M + A */\n+#define R_PPC64_PLTGOT16_LO\t53 /* half16 #lo(M + A) */\n+#define R_PPC64_PLTGOT16_HI\t54 /* half16 #hi(M + A) */\n+#define R_PPC64_PLTGOT16_HA\t55 /* half16 #ha(M + A) */\n+\n+#define R_PPC64_ADDR16_DS\t56 /* half16ds* (S + A) >> 2 */\n+#define R_PPC64_ADDR16_LO_DS\t57 /* half16ds  #lo(S + A) >> 2 */\n+#define R_PPC64_GOT16_DS\t58 /* half16ds* (G + A) >> 2 */\n+#define R_PPC64_GOT16_LO_DS\t59 /* half16ds  #lo(G + A) >> 2 */\n+#define R_PPC64_PLT16_LO_DS\t60 /* half16ds  #lo(L + A) >> 2 */\n+#define R_PPC64_SECTOFF_DS\t61 /* half16ds* (R + A) >> 2 */\n+#define R_PPC64_SECTOFF_LO_DS\t62 /* half16ds  #lo(R + A) >> 2 */\n+#define R_PPC64_TOC16_DS\t63 /* half16ds* (S + A - .TOC.) >> 2 */\n+#define R_PPC64_TOC16_LO_DS\t64 /* half16ds  #lo(S + A - .TOC.) >> 2 */\n+#define R_PPC64_PLTGOT16_DS\t65 /* half16ds* (M + A) >> 2 */\n+#define R_PPC64_PLTGOT16_LO_DS\t66 /* half16ds  #lo(M + A) >> 2 */\n+\n+/* PowerPC64 relocations defined for the TLS access ABI.  */\n+#define R_PPC64_TLS\t\t67 /* none\t(sym+add)@tls */\n+#define R_PPC64_DTPMOD64\t68 /* doubleword64 (sym+add)@dtpmod */\n+#define R_PPC64_TPREL16\t\t69 /* half16*\t(sym+add)@tprel */\n+#define R_PPC64_TPREL16_LO\t70 /* half16\t(sym+add)@tprel@l */\n+#define R_PPC64_TPREL16_HI\t71 /* half16\t(sym+add)@tprel@h */\n+#define R_PPC64_TPREL16_HA\t72 /* half16\t(sym+add)@tprel@ha */\n+#define R_PPC64_TPREL64\t\t73 /* doubleword64 (sym+add)@tprel */\n+#define R_PPC64_DTPREL16\t74 /* half16*\t(sym+add)@dtprel */\n+#define R_PPC64_DTPREL16_LO\t75 /* half16\t(sym+add)@dtprel@l */\n+#define R_PPC64_DTPREL16_HI\t76 /* half16\t(sym+add)@dtprel@h */\n+#define R_PPC64_DTPREL16_HA\t77 /* half16\t(sym+add)@dtprel@ha */\n+#define R_PPC64_DTPREL64\t78 /* doubleword64 (sym+add)@dtprel */\n+#define R_PPC64_GOT_TLSGD16\t79 /* half16*\t(sym+add)@got@tlsgd */\n+#define R_PPC64_GOT_TLSGD16_LO\t80 /* half16\t(sym+add)@got@tlsgd@l */\n+#define R_PPC64_GOT_TLSGD16_HI\t81 /* half16\t(sym+add)@got@tlsgd@h */\n+#define R_PPC64_GOT_TLSGD16_HA\t82 /* half16\t(sym+add)@got@tlsgd@ha */\n+#define R_PPC64_GOT_TLSLD16\t83 /* half16*\t(sym+add)@got@tlsld */\n+#define R_PPC64_GOT_TLSLD16_LO\t84 /* half16\t(sym+add)@got@tlsld@l */\n+#define R_PPC64_GOT_TLSLD16_HI\t85 /* half16\t(sym+add)@got@tlsld@h */\n+#define R_PPC64_GOT_TLSLD16_HA\t86 /* half16\t(sym+add)@got@tlsld@ha */\n+#define R_PPC64_GOT_TPREL16_DS\t87 /* half16ds*\t(sym+add)@got@tprel */\n+#define R_PPC64_GOT_TPREL16_LO_DS 88 /* half16ds (sym+add)@got@tprel@l */\n+#define R_PPC64_GOT_TPREL16_HI\t89 /* half16\t(sym+add)@got@tprel@h */\n+#define R_PPC64_GOT_TPREL16_HA\t90 /* half16\t(sym+add)@got@tprel@ha */\n+#define R_PPC64_GOT_DTPREL16_DS\t91 /* half16ds*\t(sym+add)@got@dtprel */\n+#define R_PPC64_GOT_DTPREL16_LO_DS 92 /* half16ds (sym+add)@got@dtprel@l */\n+#define R_PPC64_GOT_DTPREL16_HI\t93 /* half16\t(sym+add)@got@dtprel@h */\n+#define R_PPC64_GOT_DTPREL16_HA\t94 /* half16\t(sym+add)@got@dtprel@ha */\n+#define R_PPC64_TPREL16_DS\t95 /* half16ds*\t(sym+add)@tprel */\n+#define R_PPC64_TPREL16_LO_DS\t96 /* half16ds\t(sym+add)@tprel@l */\n+#define R_PPC64_TPREL16_HIGHER\t97 /* half16\t(sym+add)@tprel@higher */\n+#define R_PPC64_TPREL16_HIGHERA\t98 /* half16\t(sym+add)@tprel@highera */\n+#define R_PPC64_TPREL16_HIGHEST\t99 /* half16\t(sym+add)@tprel@highest */\n+#define R_PPC64_TPREL16_HIGHESTA 100 /* half16\t(sym+add)@tprel@highesta */\n+#define R_PPC64_DTPREL16_DS\t101 /* half16ds* (sym+add)@dtprel */\n+#define R_PPC64_DTPREL16_LO_DS\t102 /* half16ds\t(sym+add)@dtprel@l */\n+#define R_PPC64_DTPREL16_HIGHER\t103 /* half16\t(sym+add)@dtprel@higher */\n+#define R_PPC64_DTPREL16_HIGHERA 104 /* half16\t(sym+add)@dtprel@highera */\n+#define R_PPC64_DTPREL16_HIGHEST 105 /* half16\t(sym+add)@dtprel@highest */\n+#define R_PPC64_DTPREL16_HIGHESTA 106 /* half16\t(sym+add)@dtprel@highesta */\n+\n+/* GNU extension to support local ifunc.  */\n+#define R_PPC64_JMP_IREL\t247\n+#define R_PPC64_IRELATIVE\t248\n+#define R_PPC64_REL16\t\t249\t/* half16   (sym+add-.) */\n+#define R_PPC64_REL16_LO\t250\t/* half16   (sym+add-.)@l */\n+#define R_PPC64_REL16_HI\t251\t/* half16   (sym+add-.)@h */\n+#define R_PPC64_REL16_HA\t252\t/* half16   (sym+add-.)@ha */\n+\n+/* PowerPC64 specific values for the Dyn d_tag field.  */\n+#define DT_PPC64_GLINK  (DT_LOPROC + 0)\n+#define DT_PPC64_OPD\t(DT_LOPROC + 1)\n+#define DT_PPC64_OPDSZ\t(DT_LOPROC + 2)\n+#define DT_PPC64_NUM    3\n+\n+\n+/* ARM specific declarations */\n+\n+/* Processor specific flags for the ELF header e_flags field.  */\n+#define EF_ARM_RELEXEC\t\t0x01\n+#define EF_ARM_HASENTRY\t\t0x02\n+#define EF_ARM_INTERWORK\t0x04\n+#define EF_ARM_APCS_26\t\t0x08\n+#define EF_ARM_APCS_FLOAT\t0x10\n+#define EF_ARM_PIC\t\t0x20\n+#define EF_ARM_ALIGN8\t\t0x40 /* 8-bit structure alignment is in use */\n+#define EF_ARM_NEW_ABI\t\t0x80\n+#define EF_ARM_OLD_ABI\t\t0x100\n+#define EF_ARM_SOFT_FLOAT\t0x200\n+#define EF_ARM_VFP_FLOAT\t0x400\n+#define EF_ARM_MAVERICK_FLOAT\t0x800\n+\n+\n+/* Other constants defined in the ARM ELF spec. version B-01.  */\n+/* NB. These conflict with values defined above.  */\n+#define EF_ARM_SYMSARESORTED\t0x04\n+#define EF_ARM_DYNSYMSUSESEGIDX\t0x08\n+#define EF_ARM_MAPSYMSFIRST\t0x10\n+#define EF_ARM_EABIMASK\t\t0XFF000000\n+\n+/* Constants defined in AAELF.  */\n+#define EF_ARM_BE8\t    0x00800000\n+#define EF_ARM_LE8\t    0x00400000\n+\n+#define EF_ARM_EABI_VERSION(flags)\t((flags) & EF_ARM_EABIMASK)\n+#define EF_ARM_EABI_UNKNOWN\t0x00000000\n+#define EF_ARM_EABI_VER1\t0x01000000\n+#define EF_ARM_EABI_VER2\t0x02000000\n+#define EF_ARM_EABI_VER3\t0x03000000\n+#define EF_ARM_EABI_VER4\t0x04000000\n+#define EF_ARM_EABI_VER5\t0x05000000\n+\n+/* Additional symbol types for Thumb.  */\n+#define STT_ARM_TFUNC\t\tSTT_LOPROC /* A Thumb function.  */\n+#define STT_ARM_16BIT\t\tSTT_HIPROC /* A Thumb label.  */\n+\n+/* ARM-specific values for sh_flags */\n+#define SHF_ARM_ENTRYSECT\t0x10000000 /* Section contains an entry point */\n+#define SHF_ARM_COMDEF\t\t0x80000000 /* Section may be multiply defined\n+\t\t\t\t\t      in the input to a link step.  */\n+\n+/* ARM-specific program header flags */\n+#define PF_ARM_SB\t\t0x10000000 /* Segment contains the location\n+\t\t\t\t\t      addressed by the static base. */\n+#define PF_ARM_PI\t\t0x20000000 /* Position-independent segment.  */\n+#define PF_ARM_ABS\t\t0x40000000 /* Absolute segment.  */\n+\n+/* Processor specific values for the Phdr p_type field.  */\n+#define PT_ARM_EXIDX\t\t(PT_LOPROC + 1)\t/* ARM unwind segment.  */\n+\n+/* Processor specific values for the Shdr sh_type field.  */\n+#define SHT_ARM_EXIDX\t\t(SHT_LOPROC + 1) /* ARM unwind section.  */\n+#define SHT_ARM_PREEMPTMAP\t(SHT_LOPROC + 2) /* Preemption details.  */\n+#define SHT_ARM_ATTRIBUTES\t(SHT_LOPROC + 3) /* ARM attributes section.  */\n+\n+\n+/* ARM relocs.  */\n+\n+#define R_ARM_NONE\t\t0\t/* No reloc */\n+#define R_ARM_PC24\t\t1\t/* PC relative 26 bit branch */\n+#define R_ARM_ABS32\t\t2\t/* Direct 32 bit  */\n+#define R_ARM_REL32\t\t3\t/* PC relative 32 bit */\n+#define R_ARM_PC13\t\t4\n+#define R_ARM_ABS16\t\t5\t/* Direct 16 bit */\n+#define R_ARM_ABS12\t\t6\t/* Direct 12 bit */\n+#define R_ARM_THM_ABS5\t\t7\n+#define R_ARM_ABS8\t\t8\t/* Direct 8 bit */\n+#define R_ARM_SBREL32\t\t9\n+#define R_ARM_THM_PC22\t\t10\n+#define R_ARM_THM_PC8\t\t11\n+#define R_ARM_AMP_VCALL9\t12\n+#define R_ARM_SWI24\t\t13\t/* Obsolete static relocation.  */\n+#define R_ARM_TLS_DESC\t\t13      /* Dynamic relocation.  */\n+#define R_ARM_THM_SWI8\t\t14\n+#define R_ARM_XPC25\t\t15\n+#define R_ARM_THM_XPC22\t\t16\n+#define R_ARM_TLS_DTPMOD32\t17\t/* ID of module containing symbol */\n+#define R_ARM_TLS_DTPOFF32\t18\t/* Offset in TLS block */\n+#define R_ARM_TLS_TPOFF32\t19\t/* Offset in static TLS block */\n+#define R_ARM_COPY\t\t20\t/* Copy symbol at runtime */\n+#define R_ARM_GLOB_DAT\t\t21\t/* Create GOT entry */\n+#define R_ARM_JUMP_SLOT\t\t22\t/* Create PLT entry */\n+#define R_ARM_RELATIVE\t\t23\t/* Adjust by program base */\n+#define R_ARM_GOTOFF\t\t24\t/* 32 bit offset to GOT */\n+#define R_ARM_GOTPC\t\t25\t/* 32 bit PC relative offset to GOT */\n+#define R_ARM_GOT32\t\t26\t/* 32 bit GOT entry */\n+#define R_ARM_PLT32\t\t27\t/* 32 bit PLT address */\n+#define R_ARM_ALU_PCREL_7_0\t32\n+#define R_ARM_ALU_PCREL_15_8\t33\n+#define R_ARM_ALU_PCREL_23_15\t34\n+#define R_ARM_LDR_SBREL_11_0\t35\n+#define R_ARM_ALU_SBREL_19_12\t36\n+#define R_ARM_ALU_SBREL_27_20\t37\n+#define R_ARM_TLS_GOTDESC\t90\n+#define R_ARM_TLS_CALL\t\t91\n+#define R_ARM_TLS_DESCSEQ\t92\n+#define R_ARM_THM_TLS_CALL\t93\n+#define R_ARM_GNU_VTENTRY\t100\n+#define R_ARM_GNU_VTINHERIT\t101\n+#define R_ARM_THM_PC11\t\t102\t/* thumb unconditional branch */\n+#define R_ARM_THM_PC9\t\t103\t/* thumb conditional branch */\n+#define R_ARM_TLS_GD32\t\t104\t/* PC-rel 32 bit for global dynamic\n+\t\t\t\t\t   thread local data */\n+#define R_ARM_TLS_LDM32\t\t105\t/* PC-rel 32 bit for local dynamic\n+\t\t\t\t\t   thread local data */\n+#define R_ARM_TLS_LDO32\t\t106\t/* 32 bit offset relative to TLS\n+\t\t\t\t\t   block */\n+#define R_ARM_TLS_IE32\t\t107\t/* PC-rel 32 bit for GOT entry of\n+\t\t\t\t\t   static TLS block offset */\n+#define R_ARM_TLS_LE32\t\t108\t/* 32 bit offset relative to static\n+\t\t\t\t\t   TLS block */\n+#define\tR_ARM_THM_TLS_DESCSEQ\t129\n+#define R_ARM_IRELATIVE\t\t160\n+#define R_ARM_RXPC25\t\t249\n+#define R_ARM_RSBREL32\t\t250\n+#define R_ARM_THM_RPC22\t\t251\n+#define R_ARM_RREL32\t\t252\n+#define R_ARM_RABS22\t\t253\n+#define R_ARM_RPC24\t\t254\n+#define R_ARM_RBASE\t\t255\n+/* Keep this the last entry.  */\n+#define R_ARM_NUM\t\t256\n+\n+/* IA-64 specific declarations.  */\n+\n+/* Processor specific flags for the Ehdr e_flags field.  */\n+#define EF_IA_64_MASKOS\t\t0x0000000f\t/* os-specific flags */\n+#define EF_IA_64_ABI64\t\t0x00000010\t/* 64-bit ABI */\n+#define EF_IA_64_ARCH\t\t0xff000000\t/* arch. version mask */\n+\n+/* Processor specific values for the Phdr p_type field.  */\n+#define PT_IA_64_ARCHEXT\t(PT_LOPROC + 0)\t/* arch extension bits */\n+#define PT_IA_64_UNWIND\t\t(PT_LOPROC + 1)\t/* ia64 unwind bits */\n+#define PT_IA_64_HP_OPT_ANOT\t(PT_LOOS + 0x12)\n+#define PT_IA_64_HP_HSL_ANOT\t(PT_LOOS + 0x13)\n+#define PT_IA_64_HP_STACK\t(PT_LOOS + 0x14)\n+\n+/* Processor specific flags for the Phdr p_flags field.  */\n+#define PF_IA_64_NORECOV\t0x80000000\t/* spec insns w/o recovery */\n+\n+/* Processor specific values for the Shdr sh_type field.  */\n+#define SHT_IA_64_EXT\t\t(SHT_LOPROC + 0) /* extension bits */\n+#define SHT_IA_64_UNWIND\t(SHT_LOPROC + 1) /* unwind bits */\n+\n+/* Processor specific flags for the Shdr sh_flags field.  */\n+#define SHF_IA_64_SHORT\t\t0x10000000\t/* section near gp */\n+#define SHF_IA_64_NORECOV\t0x20000000\t/* spec insns w/o recovery */\n+\n+/* Processor specific values for the Dyn d_tag field.  */\n+#define DT_IA_64_PLT_RESERVE\t(DT_LOPROC + 0)\n+#define DT_IA_64_NUM\t\t1\n+\n+/* IA-64 relocations.  */\n+#define R_IA64_NONE\t\t0x00\t/* none */\n+#define R_IA64_IMM14\t\t0x21\t/* symbol + addend, add imm14 */\n+#define R_IA64_IMM22\t\t0x22\t/* symbol + addend, add imm22 */\n+#define R_IA64_IMM64\t\t0x23\t/* symbol + addend, mov imm64 */\n+#define R_IA64_DIR32MSB\t\t0x24\t/* symbol + addend, data4 MSB */\n+#define R_IA64_DIR32LSB\t\t0x25\t/* symbol + addend, data4 LSB */\n+#define R_IA64_DIR64MSB\t\t0x26\t/* symbol + addend, data8 MSB */\n+#define R_IA64_DIR64LSB\t\t0x27\t/* symbol + addend, data8 LSB */\n+#define R_IA64_GPREL22\t\t0x2a\t/* @gprel(sym + add), add imm22 */\n+#define R_IA64_GPREL64I\t\t0x2b\t/* @gprel(sym + add), mov imm64 */\n+#define R_IA64_GPREL32MSB\t0x2c\t/* @gprel(sym + add), data4 MSB */\n+#define R_IA64_GPREL32LSB\t0x2d\t/* @gprel(sym + add), data4 LSB */\n+#define R_IA64_GPREL64MSB\t0x2e\t/* @gprel(sym + add), data8 MSB */\n+#define R_IA64_GPREL64LSB\t0x2f\t/* @gprel(sym + add), data8 LSB */\n+#define R_IA64_LTOFF22\t\t0x32\t/* @ltoff(sym + add), add imm22 */\n+#define R_IA64_LTOFF64I\t\t0x33\t/* @ltoff(sym + add), mov imm64 */\n+#define R_IA64_PLTOFF22\t\t0x3a\t/* @pltoff(sym + add), add imm22 */\n+#define R_IA64_PLTOFF64I\t0x3b\t/* @pltoff(sym + add), mov imm64 */\n+#define R_IA64_PLTOFF64MSB\t0x3e\t/* @pltoff(sym + add), data8 MSB */\n+#define R_IA64_PLTOFF64LSB\t0x3f\t/* @pltoff(sym + add), data8 LSB */\n+#define R_IA64_FPTR64I\t\t0x43\t/* @fptr(sym + add), mov imm64 */\n+#define R_IA64_FPTR32MSB\t0x44\t/* @fptr(sym + add), data4 MSB */\n+#define R_IA64_FPTR32LSB\t0x45\t/* @fptr(sym + add), data4 LSB */\n+#define R_IA64_FPTR64MSB\t0x46\t/* @fptr(sym + add), data8 MSB */\n+#define R_IA64_FPTR64LSB\t0x47\t/* @fptr(sym + add), data8 LSB */\n+#define R_IA64_PCREL60B\t\t0x48\t/* @pcrel(sym + add), brl */\n+#define R_IA64_PCREL21B\t\t0x49\t/* @pcrel(sym + add), ptb, call */\n+#define R_IA64_PCREL21M\t\t0x4a\t/* @pcrel(sym + add), chk.s */\n+#define R_IA64_PCREL21F\t\t0x4b\t/* @pcrel(sym + add), fchkf */\n+#define R_IA64_PCREL32MSB\t0x4c\t/* @pcrel(sym + add), data4 MSB */\n+#define R_IA64_PCREL32LSB\t0x4d\t/* @pcrel(sym + add), data4 LSB */\n+#define R_IA64_PCREL64MSB\t0x4e\t/* @pcrel(sym + add), data8 MSB */\n+#define R_IA64_PCREL64LSB\t0x4f\t/* @pcrel(sym + add), data8 LSB */\n+#define R_IA64_LTOFF_FPTR22\t0x52\t/* @ltoff(@fptr(s+a)), imm22 */\n+#define R_IA64_LTOFF_FPTR64I\t0x53\t/* @ltoff(@fptr(s+a)), imm64 */\n+#define R_IA64_LTOFF_FPTR32MSB\t0x54\t/* @ltoff(@fptr(s+a)), data4 MSB */\n+#define R_IA64_LTOFF_FPTR32LSB\t0x55\t/* @ltoff(@fptr(s+a)), data4 LSB */\n+#define R_IA64_LTOFF_FPTR64MSB\t0x56\t/* @ltoff(@fptr(s+a)), data8 MSB */\n+#define R_IA64_LTOFF_FPTR64LSB\t0x57\t/* @ltoff(@fptr(s+a)), data8 LSB */\n+#define R_IA64_SEGREL32MSB\t0x5c\t/* @segrel(sym + add), data4 MSB */\n+#define R_IA64_SEGREL32LSB\t0x5d\t/* @segrel(sym + add), data4 LSB */\n+#define R_IA64_SEGREL64MSB\t0x5e\t/* @segrel(sym + add), data8 MSB */\n+#define R_IA64_SEGREL64LSB\t0x5f\t/* @segrel(sym + add), data8 LSB */\n+#define R_IA64_SECREL32MSB\t0x64\t/* @secrel(sym + add), data4 MSB */\n+#define R_IA64_SECREL32LSB\t0x65\t/* @secrel(sym + add), data4 LSB */\n+#define R_IA64_SECREL64MSB\t0x66\t/* @secrel(sym + add), data8 MSB */\n+#define R_IA64_SECREL64LSB\t0x67\t/* @secrel(sym + add), data8 LSB */\n+#define R_IA64_REL32MSB\t\t0x6c\t/* data 4 + REL */\n+#define R_IA64_REL32LSB\t\t0x6d\t/* data 4 + REL */\n+#define R_IA64_REL64MSB\t\t0x6e\t/* data 8 + REL */\n+#define R_IA64_REL64LSB\t\t0x6f\t/* data 8 + REL */\n+#define R_IA64_LTV32MSB\t\t0x74\t/* symbol + addend, data4 MSB */\n+#define R_IA64_LTV32LSB\t\t0x75\t/* symbol + addend, data4 LSB */\n+#define R_IA64_LTV64MSB\t\t0x76\t/* symbol + addend, data8 MSB */\n+#define R_IA64_LTV64LSB\t\t0x77\t/* symbol + addend, data8 LSB */\n+#define R_IA64_PCREL21BI\t0x79\t/* @pcrel(sym + add), 21bit inst */\n+#define R_IA64_PCREL22\t\t0x7a\t/* @pcrel(sym + add), 22bit inst */\n+#define R_IA64_PCREL64I\t\t0x7b\t/* @pcrel(sym + add), 64bit inst */\n+#define R_IA64_IPLTMSB\t\t0x80\t/* dynamic reloc, imported PLT, MSB */\n+#define R_IA64_IPLTLSB\t\t0x81\t/* dynamic reloc, imported PLT, LSB */\n+#define R_IA64_COPY\t\t0x84\t/* copy relocation */\n+#define R_IA64_SUB\t\t0x85\t/* Addend and symbol difference */\n+#define R_IA64_LTOFF22X\t\t0x86\t/* LTOFF22, relaxable.  */\n+#define R_IA64_LDXMOV\t\t0x87\t/* Use of LTOFF22X.  */\n+#define R_IA64_TPREL14\t\t0x91\t/* @tprel(sym + add), imm14 */\n+#define R_IA64_TPREL22\t\t0x92\t/* @tprel(sym + add), imm22 */\n+#define R_IA64_TPREL64I\t\t0x93\t/* @tprel(sym + add), imm64 */\n+#define R_IA64_TPREL64MSB\t0x96\t/* @tprel(sym + add), data8 MSB */\n+#define R_IA64_TPREL64LSB\t0x97\t/* @tprel(sym + add), data8 LSB */\n+#define R_IA64_LTOFF_TPREL22\t0x9a\t/* @ltoff(@tprel(s+a)), imm2 */\n+#define R_IA64_DTPMOD64MSB\t0xa6\t/* @dtpmod(sym + add), data8 MSB */\n+#define R_IA64_DTPMOD64LSB\t0xa7\t/* @dtpmod(sym + add), data8 LSB */\n+#define R_IA64_LTOFF_DTPMOD22\t0xaa\t/* @ltoff(@dtpmod(sym + add)), imm22 */\n+#define R_IA64_DTPREL14\t\t0xb1\t/* @dtprel(sym + add), imm14 */\n+#define R_IA64_DTPREL22\t\t0xb2\t/* @dtprel(sym + add), imm22 */\n+#define R_IA64_DTPREL64I\t0xb3\t/* @dtprel(sym + add), imm64 */\n+#define R_IA64_DTPREL32MSB\t0xb4\t/* @dtprel(sym + add), data4 MSB */\n+#define R_IA64_DTPREL32LSB\t0xb5\t/* @dtprel(sym + add), data4 LSB */\n+#define R_IA64_DTPREL64MSB\t0xb6\t/* @dtprel(sym + add), data8 MSB */\n+#define R_IA64_DTPREL64LSB\t0xb7\t/* @dtprel(sym + add), data8 LSB */\n+#define R_IA64_LTOFF_DTPREL22\t0xba\t/* @ltoff(@dtprel(s+a)), imm22 */\n+\n+/* SH specific declarations */\n+\n+/* Processor specific flags for the ELF header e_flags field.  */\n+#define EF_SH_MACH_MASK\t\t0x1f\n+#define EF_SH_UNKNOWN\t\t0x0\n+#define EF_SH1\t\t\t0x1\n+#define EF_SH2\t\t\t0x2\n+#define EF_SH3\t\t\t0x3\n+#define EF_SH_DSP\t\t0x4\n+#define EF_SH3_DSP\t\t0x5\n+#define EF_SH4AL_DSP\t\t0x6\n+#define EF_SH3E\t\t\t0x8\n+#define EF_SH4\t\t\t0x9\n+#define EF_SH2E\t\t\t0xb\n+#define EF_SH4A\t\t\t0xc\n+#define EF_SH2A\t\t\t0xd\n+#define EF_SH4_NOFPU\t\t0x10\n+#define EF_SH4A_NOFPU\t\t0x11\n+#define EF_SH4_NOMMU_NOFPU\t0x12\n+#define EF_SH2A_NOFPU\t\t0x13\n+#define EF_SH3_NOMMU\t\t0x14\n+#define EF_SH2A_SH4_NOFPU\t0x15\n+#define EF_SH2A_SH3_NOFPU\t0x16\n+#define EF_SH2A_SH4\t\t0x17\n+#define EF_SH2A_SH3E\t\t0x18\n+\n+/* SH relocs.  */\n+#define\tR_SH_NONE\t\t0\n+#define\tR_SH_DIR32\t\t1\n+#define\tR_SH_REL32\t\t2\n+#define\tR_SH_DIR8WPN\t\t3\n+#define\tR_SH_IND12W\t\t4\n+#define\tR_SH_DIR8WPL\t\t5\n+#define\tR_SH_DIR8WPZ\t\t6\n+#define\tR_SH_DIR8BP\t\t7\n+#define\tR_SH_DIR8W\t\t8\n+#define\tR_SH_DIR8L\t\t9\n+#define\tR_SH_SWITCH16\t\t25\n+#define\tR_SH_SWITCH32\t\t26\n+#define\tR_SH_USES\t\t27\n+#define\tR_SH_COUNT\t\t28\n+#define\tR_SH_ALIGN\t\t29\n+#define\tR_SH_CODE\t\t30\n+#define\tR_SH_DATA\t\t31\n+#define\tR_SH_LABEL\t\t32\n+#define\tR_SH_SWITCH8\t\t33\n+#define\tR_SH_GNU_VTINHERIT\t34\n+#define\tR_SH_GNU_VTENTRY\t35\n+#define\tR_SH_TLS_GD_32\t\t144\n+#define\tR_SH_TLS_LD_32\t\t145\n+#define\tR_SH_TLS_LDO_32\t\t146\n+#define\tR_SH_TLS_IE_32\t\t147\n+#define\tR_SH_TLS_LE_32\t\t148\n+#define\tR_SH_TLS_DTPMOD32\t149\n+#define\tR_SH_TLS_DTPOFF32\t150\n+#define\tR_SH_TLS_TPOFF32\t151\n+#define\tR_SH_GOT32\t\t160\n+#define\tR_SH_PLT32\t\t161\n+#define\tR_SH_COPY\t\t162\n+#define\tR_SH_GLOB_DAT\t\t163\n+#define\tR_SH_JMP_SLOT\t\t164\n+#define\tR_SH_RELATIVE\t\t165\n+#define\tR_SH_GOTOFF\t\t166\n+#define\tR_SH_GOTPC\t\t167\n+/* Keep this the last entry.  */\n+#define\tR_SH_NUM\t\t256\n+\n+/* S/390 specific definitions.  */\n+\n+/* Valid values for the e_flags field.  */\n+\n+#define EF_S390_HIGH_GPRS    0x00000001  /* High GPRs kernel facility needed.  */\n+\n+/* Additional s390 relocs */\n+\n+#define R_390_NONE\t\t0\t/* No reloc.  */\n+#define R_390_8\t\t\t1\t/* Direct 8 bit.  */\n+#define R_390_12\t\t2\t/* Direct 12 bit.  */\n+#define R_390_16\t\t3\t/* Direct 16 bit.  */\n+#define R_390_32\t\t4\t/* Direct 32 bit.  */\n+#define R_390_PC32\t\t5\t/* PC relative 32 bit.\t*/\n+#define R_390_GOT12\t\t6\t/* 12 bit GOT offset.  */\n+#define R_390_GOT32\t\t7\t/* 32 bit GOT offset.  */\n+#define R_390_PLT32\t\t8\t/* 32 bit PC relative PLT address.  */\n+#define R_390_COPY\t\t9\t/* Copy symbol at runtime.  */\n+#define R_390_GLOB_DAT\t\t10\t/* Create GOT entry.  */\n+#define R_390_JMP_SLOT\t\t11\t/* Create PLT entry.  */\n+#define R_390_RELATIVE\t\t12\t/* Adjust by program base.  */\n+#define R_390_GOTOFF32\t\t13\t/* 32 bit offset to GOT.\t */\n+#define R_390_GOTPC\t\t14\t/* 32 bit PC relative offset to GOT.  */\n+#define R_390_GOT16\t\t15\t/* 16 bit GOT offset.  */\n+#define R_390_PC16\t\t16\t/* PC relative 16 bit.\t*/\n+#define R_390_PC16DBL\t\t17\t/* PC relative 16 bit shifted by 1.  */\n+#define R_390_PLT16DBL\t\t18\t/* 16 bit PC rel. PLT shifted by 1.  */\n+#define R_390_PC32DBL\t\t19\t/* PC relative 32 bit shifted by 1.  */\n+#define R_390_PLT32DBL\t\t20\t/* 32 bit PC rel. PLT shifted by 1.  */\n+#define R_390_GOTPCDBL\t\t21\t/* 32 bit PC rel. GOT shifted by 1.  */\n+#define R_390_64\t\t22\t/* Direct 64 bit.  */\n+#define R_390_PC64\t\t23\t/* PC relative 64 bit.\t*/\n+#define R_390_GOT64\t\t24\t/* 64 bit GOT offset.  */\n+#define R_390_PLT64\t\t25\t/* 64 bit PC relative PLT address.  */\n+#define R_390_GOTENT\t\t26\t/* 32 bit PC rel. to GOT entry >> 1. */\n+#define R_390_GOTOFF16\t\t27\t/* 16 bit offset to GOT. */\n+#define R_390_GOTOFF64\t\t28\t/* 64 bit offset to GOT. */\n+#define R_390_GOTPLT12\t\t29\t/* 12 bit offset to jump slot.\t*/\n+#define R_390_GOTPLT16\t\t30\t/* 16 bit offset to jump slot.\t*/\n+#define R_390_GOTPLT32\t\t31\t/* 32 bit offset to jump slot.\t*/\n+#define R_390_GOTPLT64\t\t32\t/* 64 bit offset to jump slot.\t*/\n+#define R_390_GOTPLTENT\t\t33\t/* 32 bit rel. offset to jump slot.  */\n+#define R_390_PLTOFF16\t\t34\t/* 16 bit offset from GOT to PLT. */\n+#define R_390_PLTOFF32\t\t35\t/* 32 bit offset from GOT to PLT. */\n+#define R_390_PLTOFF64\t\t36\t/* 16 bit offset from GOT to PLT. */\n+#define R_390_TLS_LOAD\t\t37\t/* Tag for load insn in TLS code.  */\n+#define R_390_TLS_GDCALL\t38\t/* Tag for function call in general\n+\t\t\t\t\t   dynamic TLS code. */\n+#define R_390_TLS_LDCALL\t39\t/* Tag for function call in local\n+\t\t\t\t\t   dynamic TLS code. */\n+#define R_390_TLS_GD32\t\t40\t/* Direct 32 bit for general dynamic\n+\t\t\t\t\t   thread local data.  */\n+#define R_390_TLS_GD64\t\t41\t/* Direct 64 bit for general dynamic\n+\t\t\t\t\t  thread local data.  */\n+#define R_390_TLS_GOTIE12\t42\t/* 12 bit GOT offset for static TLS\n+\t\t\t\t\t   block offset.  */\n+#define R_390_TLS_GOTIE32\t43\t/* 32 bit GOT offset for static TLS\n+\t\t\t\t\t   block offset.  */\n+#define R_390_TLS_GOTIE64\t44\t/* 64 bit GOT offset for static TLS\n+\t\t\t\t\t   block offset. */\n+#define R_390_TLS_LDM32\t\t45\t/* Direct 32 bit for local dynamic\n+\t\t\t\t\t   thread local data in LE code.  */\n+#define R_390_TLS_LDM64\t\t46\t/* Direct 64 bit for local dynamic\n+\t\t\t\t\t   thread local data in LE code.  */\n+#define R_390_TLS_IE32\t\t47\t/* 32 bit address of GOT entry for\n+\t\t\t\t\t   negated static TLS block offset.  */\n+#define R_390_TLS_IE64\t\t48\t/* 64 bit address of GOT entry for\n+\t\t\t\t\t   negated static TLS block offset.  */\n+#define R_390_TLS_IEENT\t\t49\t/* 32 bit rel. offset to GOT entry for\n+\t\t\t\t\t   negated static TLS block offset.  */\n+#define R_390_TLS_LE32\t\t50\t/* 32 bit negated offset relative to\n+\t\t\t\t\t   static TLS block.  */\n+#define R_390_TLS_LE64\t\t51\t/* 64 bit negated offset relative to\n+\t\t\t\t\t   static TLS block.  */\n+#define R_390_TLS_LDO32\t\t52\t/* 32 bit offset relative to TLS\n+\t\t\t\t\t   block.  */\n+#define R_390_TLS_LDO64\t\t53\t/* 64 bit offset relative to TLS\n+\t\t\t\t\t   block.  */\n+#define R_390_TLS_DTPMOD\t54\t/* ID of module containing symbol.  */\n+#define R_390_TLS_DTPOFF\t55\t/* Offset in TLS block.\t */\n+#define R_390_TLS_TPOFF\t\t56\t/* Negated offset in static TLS\n+\t\t\t\t\t   block.  */\n+#define R_390_20\t\t57\t/* Direct 20 bit.  */\n+#define R_390_GOT20\t\t58\t/* 20 bit GOT offset.  */\n+#define R_390_GOTPLT20\t\t59\t/* 20 bit offset to jump slot.  */\n+#define R_390_TLS_GOTIE20\t60\t/* 20 bit GOT offset for static TLS\n+\t\t\t\t\t   block offset.  */\n+#define R_390_IRELATIVE         61      /* STT_GNU_IFUNC relocation.  */\n+/* Keep this the last entry.  */\n+#define R_390_NUM\t\t62\n+\n+\n+/* CRIS relocations.  */\n+#define R_CRIS_NONE\t\t0\n+#define R_CRIS_8\t\t1\n+#define R_CRIS_16\t\t2\n+#define R_CRIS_32\t\t3\n+#define R_CRIS_8_PCREL\t\t4\n+#define R_CRIS_16_PCREL\t\t5\n+#define R_CRIS_32_PCREL\t\t6\n+#define R_CRIS_GNU_VTINHERIT\t7\n+#define R_CRIS_GNU_VTENTRY\t8\n+#define R_CRIS_COPY\t\t9\n+#define R_CRIS_GLOB_DAT\t\t10\n+#define R_CRIS_JUMP_SLOT\t11\n+#define R_CRIS_RELATIVE\t\t12\n+#define R_CRIS_16_GOT\t\t13\n+#define R_CRIS_32_GOT\t\t14\n+#define R_CRIS_16_GOTPLT\t15\n+#define R_CRIS_32_GOTPLT\t16\n+#define R_CRIS_32_GOTREL\t17\n+#define R_CRIS_32_PLT_GOTREL\t18\n+#define R_CRIS_32_PLT_PCREL\t19\n+\n+#define R_CRIS_NUM\t\t20\n+\n+\n+/* AMD x86-64 relocations.  */\n+#define R_X86_64_NONE\t\t0\t/* No reloc */\n+#define R_X86_64_64\t\t1\t/* Direct 64 bit  */\n+#define R_X86_64_PC32\t\t2\t/* PC relative 32 bit signed */\n+#define R_X86_64_GOT32\t\t3\t/* 32 bit GOT entry */\n+#define R_X86_64_PLT32\t\t4\t/* 32 bit PLT address */\n+#define R_X86_64_COPY\t\t5\t/* Copy symbol at runtime */\n+#define R_X86_64_GLOB_DAT\t6\t/* Create GOT entry */\n+#define R_X86_64_JUMP_SLOT\t7\t/* Create PLT entry */\n+#define R_X86_64_RELATIVE\t8\t/* Adjust by program base */\n+#define R_X86_64_GOTPCREL\t9\t/* 32 bit signed PC relative\n+\t\t\t\t\t   offset to GOT */\n+#define R_X86_64_32\t\t10\t/* Direct 32 bit zero extended */\n+#define R_X86_64_32S\t\t11\t/* Direct 32 bit sign extended */\n+#define R_X86_64_16\t\t12\t/* Direct 16 bit zero extended */\n+#define R_X86_64_PC16\t\t13\t/* 16 bit sign extended pc relative */\n+#define R_X86_64_8\t\t14\t/* Direct 8 bit sign extended  */\n+#define R_X86_64_PC8\t\t15\t/* 8 bit sign extended pc relative */\n+#define R_X86_64_DTPMOD64\t16\t/* ID of module containing symbol */\n+#define R_X86_64_DTPOFF64\t17\t/* Offset in module's TLS block */\n+#define R_X86_64_TPOFF64\t18\t/* Offset in initial TLS block */\n+#define R_X86_64_TLSGD\t\t19\t/* 32 bit signed PC relative offset\n+\t\t\t\t\t   to two GOT entries for GD symbol */\n+#define R_X86_64_TLSLD\t\t20\t/* 32 bit signed PC relative offset\n+\t\t\t\t\t   to two GOT entries for LD symbol */\n+#define R_X86_64_DTPOFF32\t21\t/* Offset in TLS block */\n+#define R_X86_64_GOTTPOFF\t22\t/* 32 bit signed PC relative offset\n+\t\t\t\t\t   to GOT entry for IE symbol */\n+#define R_X86_64_TPOFF32\t23\t/* Offset in initial TLS block */\n+#define R_X86_64_PC64\t\t24\t/* PC relative 64 bit */\n+#define R_X86_64_GOTOFF64\t25\t/* 64 bit offset to GOT */\n+#define R_X86_64_GOTPC32\t26\t/* 32 bit signed pc relative\n+\t\t\t\t\t   offset to GOT */\n+#define R_X86_64_GOT64\t\t27\t/* 64-bit GOT entry offset */\n+#define R_X86_64_GOTPCREL64\t28\t/* 64-bit PC relative offset\n+\t\t\t\t\t   to GOT entry */\n+#define R_X86_64_GOTPC64\t29\t/* 64-bit PC relative offset to GOT */\n+#define R_X86_64_GOTPLT64\t30 \t/* like GOT64, says PLT entry needed */\n+#define R_X86_64_PLTOFF64\t31\t/* 64-bit GOT relative offset\n+\t\t\t\t\t   to PLT entry */\n+#define R_X86_64_SIZE32\t\t32\t/* Size of symbol plus 32-bit addend */\n+#define R_X86_64_SIZE64\t\t33\t/* Size of symbol plus 64-bit addend */\n+#define R_X86_64_GOTPC32_TLSDESC 34\t/* GOT offset for TLS descriptor.  */\n+#define R_X86_64_TLSDESC_CALL   35\t/* Marker for call through TLS\n+\t\t\t\t\t   descriptor.  */\n+#define R_X86_64_TLSDESC        36\t/* TLS descriptor.  */\n+#define R_X86_64_IRELATIVE\t37\t/* Adjust indirectly by program base */\n+#define R_X86_64_RELATIVE64\t38\t/* 64-bit adjust by program base */\n+\n+#define R_X86_64_NUM\t\t39\n+\n+\n+/* AM33 relocations.  */\n+#define R_MN10300_NONE\t\t0\t/* No reloc.  */\n+#define R_MN10300_32\t\t1\t/* Direct 32 bit.  */\n+#define R_MN10300_16\t\t2\t/* Direct 16 bit.  */\n+#define R_MN10300_8\t\t3\t/* Direct 8 bit.  */\n+#define R_MN10300_PCREL32\t4\t/* PC-relative 32-bit.  */\n+#define R_MN10300_PCREL16\t5\t/* PC-relative 16-bit signed.  */\n+#define R_MN10300_PCREL8\t6\t/* PC-relative 8-bit signed.  */\n+#define R_MN10300_GNU_VTINHERIT\t7\t/* Ancient C++ vtable garbage... */\n+#define R_MN10300_GNU_VTENTRY\t8\t/* ... collection annotation.  */\n+#define R_MN10300_24\t\t9\t/* Direct 24 bit.  */\n+#define R_MN10300_GOTPC32\t10\t/* 32-bit PCrel offset to GOT.  */\n+#define R_MN10300_GOTPC16\t11\t/* 16-bit PCrel offset to GOT.  */\n+#define R_MN10300_GOTOFF32\t12\t/* 32-bit offset from GOT.  */\n+#define R_MN10300_GOTOFF24\t13\t/* 24-bit offset from GOT.  */\n+#define R_MN10300_GOTOFF16\t14\t/* 16-bit offset from GOT.  */\n+#define R_MN10300_PLT32\t\t15\t/* 32-bit PCrel to PLT entry.  */\n+#define R_MN10300_PLT16\t\t16\t/* 16-bit PCrel to PLT entry.  */\n+#define R_MN10300_GOT32\t\t17\t/* 32-bit offset to GOT entry.  */\n+#define R_MN10300_GOT24\t\t18\t/* 24-bit offset to GOT entry.  */\n+#define R_MN10300_GOT16\t\t19\t/* 16-bit offset to GOT entry.  */\n+#define R_MN10300_COPY\t\t20\t/* Copy symbol at runtime.  */\n+#define R_MN10300_GLOB_DAT\t21\t/* Create GOT entry.  */\n+#define R_MN10300_JMP_SLOT\t22\t/* Create PLT entry.  */\n+#define R_MN10300_RELATIVE\t23\t/* Adjust by program base.  */\n+\n+#define R_MN10300_NUM\t\t24\n+\n+\n+/* M32R relocs.  */\n+#define R_M32R_NONE\t\t0\t/* No reloc. */\n+#define R_M32R_16\t\t1\t/* Direct 16 bit. */\n+#define R_M32R_32\t\t2\t/* Direct 32 bit. */\n+#define R_M32R_24\t\t3\t/* Direct 24 bit. */\n+#define R_M32R_10_PCREL\t\t4\t/* PC relative 10 bit shifted. */\n+#define R_M32R_18_PCREL\t\t5\t/* PC relative 18 bit shifted. */\n+#define R_M32R_26_PCREL\t\t6\t/* PC relative 26 bit shifted. */\n+#define R_M32R_HI16_ULO\t\t7\t/* High 16 bit with unsigned low. */\n+#define R_M32R_HI16_SLO\t\t8\t/* High 16 bit with signed low. */\n+#define R_M32R_LO16\t\t9\t/* Low 16 bit. */\n+#define R_M32R_SDA16\t\t10\t/* 16 bit offset in SDA. */\n+#define R_M32R_GNU_VTINHERIT\t11\n+#define R_M32R_GNU_VTENTRY\t12\n+/* M32R relocs use SHT_RELA.  */\n+#define R_M32R_16_RELA\t\t33\t/* Direct 16 bit. */\n+#define R_M32R_32_RELA\t\t34\t/* Direct 32 bit. */\n+#define R_M32R_24_RELA\t\t35\t/* Direct 24 bit. */\n+#define R_M32R_10_PCREL_RELA\t36\t/* PC relative 10 bit shifted. */\n+#define R_M32R_18_PCREL_RELA\t37\t/* PC relative 18 bit shifted. */\n+#define R_M32R_26_PCREL_RELA\t38\t/* PC relative 26 bit shifted. */\n+#define R_M32R_HI16_ULO_RELA\t39\t/* High 16 bit with unsigned low */\n+#define R_M32R_HI16_SLO_RELA\t40\t/* High 16 bit with signed low */\n+#define R_M32R_LO16_RELA\t41\t/* Low 16 bit */\n+#define R_M32R_SDA16_RELA\t42\t/* 16 bit offset in SDA */\n+#define R_M32R_RELA_GNU_VTINHERIT\t43\n+#define R_M32R_RELA_GNU_VTENTRY\t44\n+#define R_M32R_REL32\t\t45\t/* PC relative 32 bit.  */\n+\n+#define R_M32R_GOT24\t\t48\t/* 24 bit GOT entry */\n+#define R_M32R_26_PLTREL\t49\t/* 26 bit PC relative to PLT shifted */\n+#define R_M32R_COPY\t\t50\t/* Copy symbol at runtime */\n+#define R_M32R_GLOB_DAT\t\t51\t/* Create GOT entry */\n+#define R_M32R_JMP_SLOT\t\t52\t/* Create PLT entry */\n+#define R_M32R_RELATIVE\t\t53\t/* Adjust by program base */\n+#define R_M32R_GOTOFF\t\t54\t/* 24 bit offset to GOT */\n+#define R_M32R_GOTPC24\t\t55\t/* 24 bit PC relative offset to GOT */\n+#define R_M32R_GOT16_HI_ULO\t56\t/* High 16 bit GOT entry with unsigned\n+\t\t\t\t\t   low */\n+#define R_M32R_GOT16_HI_SLO\t57\t/* High 16 bit GOT entry with signed\n+\t\t\t\t\t   low */\n+#define R_M32R_GOT16_LO\t\t58\t/* Low 16 bit GOT entry */\n+#define R_M32R_GOTPC_HI_ULO\t59\t/* High 16 bit PC relative offset to\n+\t\t\t\t\t   GOT with unsigned low */\n+#define R_M32R_GOTPC_HI_SLO\t60\t/* High 16 bit PC relative offset to\n+\t\t\t\t\t   GOT with signed low */\n+#define R_M32R_GOTPC_LO\t\t61\t/* Low 16 bit PC relative offset to\n+\t\t\t\t\t   GOT */\n+#define R_M32R_GOTOFF_HI_ULO\t62\t/* High 16 bit offset to GOT\n+\t\t\t\t\t   with unsigned low */\n+#define R_M32R_GOTOFF_HI_SLO\t63\t/* High 16 bit offset to GOT\n+\t\t\t\t\t   with signed low */\n+#define R_M32R_GOTOFF_LO\t64\t/* Low 16 bit offset to GOT */\n+#define R_M32R_NUM\t\t256\t/* Keep this the last entry. */\n+\n+\n+/* TILEPro relocations.  */\n+#define R_TILEPRO_NONE\t\t0\t/* No reloc */\n+#define R_TILEPRO_32\t\t1\t/* Direct 32 bit */\n+#define R_TILEPRO_16\t\t2\t/* Direct 16 bit */\n+#define R_TILEPRO_8\t\t3\t/* Direct 8 bit */\n+#define R_TILEPRO_32_PCREL\t4\t/* PC relative 32 bit */\n+#define R_TILEPRO_16_PCREL\t5\t/* PC relative 16 bit */\n+#define R_TILEPRO_8_PCREL\t6\t/* PC relative 8 bit */\n+#define R_TILEPRO_LO16\t\t7\t/* Low 16 bit */\n+#define R_TILEPRO_HI16\t\t8\t/* High 16 bit */\n+#define R_TILEPRO_HA16\t\t9\t/* High 16 bit, adjusted */\n+#define R_TILEPRO_COPY\t\t10\t/* Copy relocation */\n+#define R_TILEPRO_GLOB_DAT\t11\t/* Create GOT entry */\n+#define R_TILEPRO_JMP_SLOT\t12\t/* Create PLT entry */\n+#define R_TILEPRO_RELATIVE\t13\t/* Adjust by program base */\n+#define R_TILEPRO_BROFF_X1\t14\t/* X1 pipe branch offset */\n+#define R_TILEPRO_JOFFLONG_X1\t15\t/* X1 pipe jump offset */\n+#define R_TILEPRO_JOFFLONG_X1_PLT 16\t/* X1 pipe jump offset to PLT */\n+#define R_TILEPRO_IMM8_X0\t17\t/* X0 pipe 8-bit */\n+#define R_TILEPRO_IMM8_Y0\t18\t/* Y0 pipe 8-bit */\n+#define R_TILEPRO_IMM8_X1\t19\t/* X1 pipe 8-bit */\n+#define R_TILEPRO_IMM8_Y1\t20\t/* Y1 pipe 8-bit */\n+#define R_TILEPRO_MT_IMM15_X1\t21\t/* X1 pipe mtspr */\n+#define R_TILEPRO_MF_IMM15_X1\t22\t/* X1 pipe mfspr */\n+#define R_TILEPRO_IMM16_X0\t23\t/* X0 pipe 16-bit */\n+#define R_TILEPRO_IMM16_X1\t24\t/* X1 pipe 16-bit */\n+#define R_TILEPRO_IMM16_X0_LO\t25\t/* X0 pipe low 16-bit */\n+#define R_TILEPRO_IMM16_X1_LO\t26\t/* X1 pipe low 16-bit */\n+#define R_TILEPRO_IMM16_X0_HI\t27\t/* X0 pipe high 16-bit */\n+#define R_TILEPRO_IMM16_X1_HI\t28\t/* X1 pipe high 16-bit */\n+#define R_TILEPRO_IMM16_X0_HA\t29\t/* X0 pipe high 16-bit, adjusted */\n+#define R_TILEPRO_IMM16_X1_HA\t30\t/* X1 pipe high 16-bit, adjusted */\n+#define R_TILEPRO_IMM16_X0_PCREL 31\t/* X0 pipe PC relative 16 bit */\n+#define R_TILEPRO_IMM16_X1_PCREL 32\t/* X1 pipe PC relative 16 bit */\n+#define R_TILEPRO_IMM16_X0_LO_PCREL 33\t/* X0 pipe PC relative low 16 bit */\n+#define R_TILEPRO_IMM16_X1_LO_PCREL 34\t/* X1 pipe PC relative low 16 bit */\n+#define R_TILEPRO_IMM16_X0_HI_PCREL 35\t/* X0 pipe PC relative high 16 bit */\n+#define R_TILEPRO_IMM16_X1_HI_PCREL 36\t/* X1 pipe PC relative high 16 bit */\n+#define R_TILEPRO_IMM16_X0_HA_PCREL 37\t/* X0 pipe PC relative ha() 16 bit */\n+#define R_TILEPRO_IMM16_X1_HA_PCREL 38\t/* X1 pipe PC relative ha() 16 bit */\n+#define R_TILEPRO_IMM16_X0_GOT\t39\t/* X0 pipe 16-bit GOT offset */\n+#define R_TILEPRO_IMM16_X1_GOT\t40\t/* X1 pipe 16-bit GOT offset */\n+#define R_TILEPRO_IMM16_X0_GOT_LO 41\t/* X0 pipe low 16-bit GOT offset */\n+#define R_TILEPRO_IMM16_X1_GOT_LO 42\t/* X1 pipe low 16-bit GOT offset */\n+#define R_TILEPRO_IMM16_X0_GOT_HI 43\t/* X0 pipe high 16-bit GOT offset */\n+#define R_TILEPRO_IMM16_X1_GOT_HI 44\t/* X1 pipe high 16-bit GOT offset */\n+#define R_TILEPRO_IMM16_X0_GOT_HA 45\t/* X0 pipe ha() 16-bit GOT offset */\n+#define R_TILEPRO_IMM16_X1_GOT_HA 46\t/* X1 pipe ha() 16-bit GOT offset */\n+#define R_TILEPRO_MMSTART_X0\t47\t/* X0 pipe mm \"start\" */\n+#define R_TILEPRO_MMEND_X0\t48\t/* X0 pipe mm \"end\" */\n+#define R_TILEPRO_MMSTART_X1\t49\t/* X1 pipe mm \"start\" */\n+#define R_TILEPRO_MMEND_X1\t50\t/* X1 pipe mm \"end\" */\n+#define R_TILEPRO_SHAMT_X0\t51\t/* X0 pipe shift amount */\n+#define R_TILEPRO_SHAMT_X1\t52\t/* X1 pipe shift amount */\n+#define R_TILEPRO_SHAMT_Y0\t53\t/* Y0 pipe shift amount */\n+#define R_TILEPRO_SHAMT_Y1\t54\t/* Y1 pipe shift amount */\n+#define R_TILEPRO_DEST_IMM8_X1\t55\t/* X1 pipe destination 8-bit */\n+/* Relocs 56-59 are currently not defined.  */\n+#define R_TILEPRO_TLS_GD_CALL\t60\t/* \"jal\" for TLS GD */\n+#define R_TILEPRO_IMM8_X0_TLS_GD_ADD 61\t/* X0 pipe \"addi\" for TLS GD */\n+#define R_TILEPRO_IMM8_X1_TLS_GD_ADD 62\t/* X1 pipe \"addi\" for TLS GD */\n+#define R_TILEPRO_IMM8_Y0_TLS_GD_ADD 63\t/* Y0 pipe \"addi\" for TLS GD */\n+#define R_TILEPRO_IMM8_Y1_TLS_GD_ADD 64\t/* Y1 pipe \"addi\" for TLS GD */\n+#define R_TILEPRO_TLS_IE_LOAD\t65\t/* \"lw_tls\" for TLS IE */\n+#define R_TILEPRO_IMM16_X0_TLS_GD 66\t/* X0 pipe 16-bit TLS GD offset */\n+#define R_TILEPRO_IMM16_X1_TLS_GD 67\t/* X1 pipe 16-bit TLS GD offset */\n+#define R_TILEPRO_IMM16_X0_TLS_GD_LO 68\t/* X0 pipe low 16-bit TLS GD offset */\n+#define R_TILEPRO_IMM16_X1_TLS_GD_LO 69\t/* X1 pipe low 16-bit TLS GD offset */\n+#define R_TILEPRO_IMM16_X0_TLS_GD_HI 70\t/* X0 pipe high 16-bit TLS GD offset */\n+#define R_TILEPRO_IMM16_X1_TLS_GD_HI 71\t/* X1 pipe high 16-bit TLS GD offset */\n+#define R_TILEPRO_IMM16_X0_TLS_GD_HA 72\t/* X0 pipe ha() 16-bit TLS GD offset */\n+#define R_TILEPRO_IMM16_X1_TLS_GD_HA 73\t/* X1 pipe ha() 16-bit TLS GD offset */\n+#define R_TILEPRO_IMM16_X0_TLS_IE 74\t/* X0 pipe 16-bit TLS IE offset */\n+#define R_TILEPRO_IMM16_X1_TLS_IE 75\t/* X1 pipe 16-bit TLS IE offset */\n+#define R_TILEPRO_IMM16_X0_TLS_IE_LO 76\t/* X0 pipe low 16-bit TLS IE offset */\n+#define R_TILEPRO_IMM16_X1_TLS_IE_LO 77\t/* X1 pipe low 16-bit TLS IE offset */\n+#define R_TILEPRO_IMM16_X0_TLS_IE_HI 78\t/* X0 pipe high 16-bit TLS IE offset */\n+#define R_TILEPRO_IMM16_X1_TLS_IE_HI 79\t/* X1 pipe high 16-bit TLS IE offset */\n+#define R_TILEPRO_IMM16_X0_TLS_IE_HA 80\t/* X0 pipe ha() 16-bit TLS IE offset */\n+#define R_TILEPRO_IMM16_X1_TLS_IE_HA 81\t/* X1 pipe ha() 16-bit TLS IE offset */\n+#define R_TILEPRO_TLS_DTPMOD32\t82\t/* ID of module containing symbol */\n+#define R_TILEPRO_TLS_DTPOFF32\t83\t/* Offset in TLS block */\n+#define R_TILEPRO_TLS_TPOFF32\t84\t/* Offset in static TLS block */\n+#define R_TILEPRO_IMM16_X0_TLS_LE 85\t/* X0 pipe 16-bit TLS LE offset */\n+#define R_TILEPRO_IMM16_X1_TLS_LE 86\t/* X1 pipe 16-bit TLS LE offset */\n+#define R_TILEPRO_IMM16_X0_TLS_LE_LO 87\t/* X0 pipe low 16-bit TLS LE offset */\n+#define R_TILEPRO_IMM16_X1_TLS_LE_LO 88\t/* X1 pipe low 16-bit TLS LE offset */\n+#define R_TILEPRO_IMM16_X0_TLS_LE_HI 89\t/* X0 pipe high 16-bit TLS LE offset */\n+#define R_TILEPRO_IMM16_X1_TLS_LE_HI 90\t/* X1 pipe high 16-bit TLS LE offset */\n+#define R_TILEPRO_IMM16_X0_TLS_LE_HA 91\t/* X0 pipe ha() 16-bit TLS LE offset */\n+#define R_TILEPRO_IMM16_X1_TLS_LE_HA 92\t/* X1 pipe ha() 16-bit TLS LE offset */\n+\n+#define R_TILEPRO_GNU_VTINHERIT\t128\t/* GNU C++ vtable hierarchy */\n+#define R_TILEPRO_GNU_VTENTRY\t129\t/* GNU C++ vtable member usage */\n+\n+#define R_TILEPRO_NUM\t\t130\n+\n+\n+/* TILE-Gx relocations.  */\n+#define R_TILEGX_NONE\t\t0\t/* No reloc */\n+#define R_TILEGX_64\t\t1\t/* Direct 64 bit */\n+#define R_TILEGX_32\t\t2\t/* Direct 32 bit */\n+#define R_TILEGX_16\t\t3\t/* Direct 16 bit */\n+#define R_TILEGX_8\t\t4\t/* Direct 8 bit */\n+#define R_TILEGX_64_PCREL\t5\t/* PC relative 64 bit */\n+#define R_TILEGX_32_PCREL\t6\t/* PC relative 32 bit */\n+#define R_TILEGX_16_PCREL\t7\t/* PC relative 16 bit */\n+#define R_TILEGX_8_PCREL\t8\t/* PC relative 8 bit */\n+#define R_TILEGX_HW0\t\t9\t/* hword 0 16-bit */\n+#define R_TILEGX_HW1\t\t10\t/* hword 1 16-bit */\n+#define R_TILEGX_HW2\t\t11\t/* hword 2 16-bit */\n+#define R_TILEGX_HW3\t\t12\t/* hword 3 16-bit */\n+#define R_TILEGX_HW0_LAST\t13\t/* last hword 0 16-bit */\n+#define R_TILEGX_HW1_LAST\t14\t/* last hword 1 16-bit */\n+#define R_TILEGX_HW2_LAST\t15\t/* last hword 2 16-bit */\n+#define R_TILEGX_COPY\t\t16\t/* Copy relocation */\n+#define R_TILEGX_GLOB_DAT\t17\t/* Create GOT entry */\n+#define R_TILEGX_JMP_SLOT\t18\t/* Create PLT entry */\n+#define R_TILEGX_RELATIVE\t19\t/* Adjust by program base */\n+#define R_TILEGX_BROFF_X1\t20\t/* X1 pipe branch offset */\n+#define R_TILEGX_JUMPOFF_X1\t21\t/* X1 pipe jump offset */\n+#define R_TILEGX_JUMPOFF_X1_PLT\t22\t/* X1 pipe jump offset to PLT */\n+#define R_TILEGX_IMM8_X0\t23\t/* X0 pipe 8-bit */\n+#define R_TILEGX_IMM8_Y0\t24\t/* Y0 pipe 8-bit */\n+#define R_TILEGX_IMM8_X1\t25\t/* X1 pipe 8-bit */\n+#define R_TILEGX_IMM8_Y1\t26\t/* Y1 pipe 8-bit */\n+#define R_TILEGX_DEST_IMM8_X1\t27\t/* X1 pipe destination 8-bit */\n+#define R_TILEGX_MT_IMM14_X1\t28\t/* X1 pipe mtspr */\n+#define R_TILEGX_MF_IMM14_X1\t29\t/* X1 pipe mfspr */\n+#define R_TILEGX_MMSTART_X0\t30\t/* X0 pipe mm \"start\" */\n+#define R_TILEGX_MMEND_X0\t31\t/* X0 pipe mm \"end\" */\n+#define R_TILEGX_SHAMT_X0\t32\t/* X0 pipe shift amount */\n+#define R_TILEGX_SHAMT_X1\t33\t/* X1 pipe shift amount */\n+#define R_TILEGX_SHAMT_Y0\t34\t/* Y0 pipe shift amount */\n+#define R_TILEGX_SHAMT_Y1\t35\t/* Y1 pipe shift amount */\n+#define R_TILEGX_IMM16_X0_HW0\t36\t/* X0 pipe hword 0 */\n+#define R_TILEGX_IMM16_X1_HW0\t37\t/* X1 pipe hword 0 */\n+#define R_TILEGX_IMM16_X0_HW1\t38\t/* X0 pipe hword 1 */\n+#define R_TILEGX_IMM16_X1_HW1\t39\t/* X1 pipe hword 1 */\n+#define R_TILEGX_IMM16_X0_HW2\t40\t/* X0 pipe hword 2 */\n+#define R_TILEGX_IMM16_X1_HW2\t41\t/* X1 pipe hword 2 */\n+#define R_TILEGX_IMM16_X0_HW3\t42\t/* X0 pipe hword 3 */\n+#define R_TILEGX_IMM16_X1_HW3\t43\t/* X1 pipe hword 3 */\n+#define R_TILEGX_IMM16_X0_HW0_LAST 44\t/* X0 pipe last hword 0 */\n+#define R_TILEGX_IMM16_X1_HW0_LAST 45\t/* X1 pipe last hword 0 */\n+#define R_TILEGX_IMM16_X0_HW1_LAST 46\t/* X0 pipe last hword 1 */\n+#define R_TILEGX_IMM16_X1_HW1_LAST 47\t/* X1 pipe last hword 1 */\n+#define R_TILEGX_IMM16_X0_HW2_LAST 48\t/* X0 pipe last hword 2 */\n+#define R_TILEGX_IMM16_X1_HW2_LAST 49\t/* X1 pipe last hword 2 */\n+#define R_TILEGX_IMM16_X0_HW0_PCREL 50\t/* X0 pipe PC relative hword 0 */\n+#define R_TILEGX_IMM16_X1_HW0_PCREL 51\t/* X1 pipe PC relative hword 0 */\n+#define R_TILEGX_IMM16_X0_HW1_PCREL 52\t/* X0 pipe PC relative hword 1 */\n+#define R_TILEGX_IMM16_X1_HW1_PCREL 53\t/* X1 pipe PC relative hword 1 */\n+#define R_TILEGX_IMM16_X0_HW2_PCREL 54\t/* X0 pipe PC relative hword 2 */\n+#define R_TILEGX_IMM16_X1_HW2_PCREL 55\t/* X1 pipe PC relative hword 2 */\n+#define R_TILEGX_IMM16_X0_HW3_PCREL 56\t/* X0 pipe PC relative hword 3 */\n+#define R_TILEGX_IMM16_X1_HW3_PCREL 57\t/* X1 pipe PC relative hword 3 */\n+#define R_TILEGX_IMM16_X0_HW0_LAST_PCREL 58 /* X0 pipe PC-rel last hword 0 */\n+#define R_TILEGX_IMM16_X1_HW0_LAST_PCREL 59 /* X1 pipe PC-rel last hword 0 */\n+#define R_TILEGX_IMM16_X0_HW1_LAST_PCREL 60 /* X0 pipe PC-rel last hword 1 */\n+#define R_TILEGX_IMM16_X1_HW1_LAST_PCREL 61 /* X1 pipe PC-rel last hword 1 */\n+#define R_TILEGX_IMM16_X0_HW2_LAST_PCREL 62 /* X0 pipe PC-rel last hword 2 */\n+#define R_TILEGX_IMM16_X1_HW2_LAST_PCREL 63 /* X1 pipe PC-rel last hword 2 */\n+#define R_TILEGX_IMM16_X0_HW0_GOT 64\t/* X0 pipe hword 0 GOT offset */\n+#define R_TILEGX_IMM16_X1_HW0_GOT 65\t/* X1 pipe hword 0 GOT offset */\n+/* Relocs 66-71 are currently not defined.  */\n+#define R_TILEGX_IMM16_X0_HW0_LAST_GOT 72 /* X0 pipe last hword 0 GOT offset */\n+#define R_TILEGX_IMM16_X1_HW0_LAST_GOT 73 /* X1 pipe last hword 0 GOT offset */\n+#define R_TILEGX_IMM16_X0_HW1_LAST_GOT 74 /* X0 pipe last hword 1 GOT offset */\n+#define R_TILEGX_IMM16_X1_HW1_LAST_GOT 75 /* X1 pipe last hword 1 GOT offset */\n+/* Relocs 76-77 are currently not defined.  */\n+#define R_TILEGX_IMM16_X0_HW0_TLS_GD 78\t/* X0 pipe hword 0 TLS GD offset */\n+#define R_TILEGX_IMM16_X1_HW0_TLS_GD 79\t/* X1 pipe hword 0 TLS GD offset */\n+#define R_TILEGX_IMM16_X0_HW0_TLS_LE 80\t/* X0 pipe hword 0 TLS LE offset */\n+#define R_TILEGX_IMM16_X1_HW0_TLS_LE 81\t/* X1 pipe hword 0 TLS LE offset */\n+#define R_TILEGX_IMM16_X0_HW0_LAST_TLS_LE 82 /* X0 pipe last hword 0 LE off */\n+#define R_TILEGX_IMM16_X1_HW0_LAST_TLS_LE 83 /* X1 pipe last hword 0 LE off */\n+#define R_TILEGX_IMM16_X0_HW1_LAST_TLS_LE 84 /* X0 pipe last hword 1 LE off */\n+#define R_TILEGX_IMM16_X1_HW1_LAST_TLS_LE 85 /* X1 pipe last hword 1 LE off */\n+#define R_TILEGX_IMM16_X0_HW0_LAST_TLS_GD 86 /* X0 pipe last hword 0 GD off */\n+#define R_TILEGX_IMM16_X1_HW0_LAST_TLS_GD 87 /* X1 pipe last hword 0 GD off */\n+#define R_TILEGX_IMM16_X0_HW1_LAST_TLS_GD 88 /* X0 pipe last hword 1 GD off */\n+#define R_TILEGX_IMM16_X1_HW1_LAST_TLS_GD 89 /* X1 pipe last hword 1 GD off */\n+/* Relocs 90-91 are currently not defined.  */\n+#define R_TILEGX_IMM16_X0_HW0_TLS_IE 92\t/* X0 pipe hword 0 TLS IE offset */\n+#define R_TILEGX_IMM16_X1_HW0_TLS_IE 93\t/* X1 pipe hword 0 TLS IE offset */\n+/* Relocs 94-99 are currently not defined.  */\n+#define R_TILEGX_IMM16_X0_HW0_LAST_TLS_IE 100 /* X0 pipe last hword 0 IE off */\n+#define R_TILEGX_IMM16_X1_HW0_LAST_TLS_IE 101 /* X1 pipe last hword 0 IE off */\n+#define R_TILEGX_IMM16_X0_HW1_LAST_TLS_IE 102 /* X0 pipe last hword 1 IE off */\n+#define R_TILEGX_IMM16_X1_HW1_LAST_TLS_IE 103 /* X1 pipe last hword 1 IE off */\n+/* Relocs 104-105 are currently not defined.  */\n+#define R_TILEGX_TLS_DTPMOD64\t106\t/* 64-bit ID of symbol's module */\n+#define R_TILEGX_TLS_DTPOFF64\t107\t/* 64-bit offset in TLS block */\n+#define R_TILEGX_TLS_TPOFF64\t108\t/* 64-bit offset in static TLS block */\n+#define R_TILEGX_TLS_DTPMOD32\t109\t/* 32-bit ID of symbol's module */\n+#define R_TILEGX_TLS_DTPOFF32\t110\t/* 32-bit offset in TLS block */\n+#define R_TILEGX_TLS_TPOFF32\t111\t/* 32-bit offset in static TLS block */\n+#define R_TILEGX_TLS_GD_CALL\t112\t/* \"jal\" for TLS GD */\n+#define R_TILEGX_IMM8_X0_TLS_GD_ADD 113\t/* X0 pipe \"addi\" for TLS GD */\n+#define R_TILEGX_IMM8_X1_TLS_GD_ADD 114\t/* X1 pipe \"addi\" for TLS GD */\n+#define R_TILEGX_IMM8_Y0_TLS_GD_ADD 115\t/* Y0 pipe \"addi\" for TLS GD */\n+#define R_TILEGX_IMM8_Y1_TLS_GD_ADD 116\t/* Y1 pipe \"addi\" for TLS GD */\n+#define R_TILEGX_TLS_IE_LOAD\t117\t/* \"ld_tls\" for TLS IE */\n+#define R_TILEGX_IMM8_X0_TLS_ADD 118\t/* X0 pipe \"addi\" for TLS GD/IE */\n+#define R_TILEGX_IMM8_X1_TLS_ADD 119\t/* X1 pipe \"addi\" for TLS GD/IE */\n+#define R_TILEGX_IMM8_Y0_TLS_ADD 120\t/* Y0 pipe \"addi\" for TLS GD/IE */\n+#define R_TILEGX_IMM8_Y1_TLS_ADD 121\t/* Y1 pipe \"addi\" for TLS GD/IE */\n+\n+#define R_TILEGX_GNU_VTINHERIT\t128\t/* GNU C++ vtable hierarchy */\n+#define R_TILEGX_GNU_VTENTRY\t129\t/* GNU C++ vtable member usage */\n+\n+#define R_TILEGX_NUM\t\t130\n+\n+#endif\t/* elf.h */\n--- a/scripts/mod/mk_elfconfig.c\n+++ b/scripts/mod/mk_elfconfig.c\n@@ -2,7 +2,11 @@\n #include <stdio.h>\n #include <stdlib.h>\n #include <string.h>\n+#ifndef __APPLE__\n #include <elf.h>\n+#else\n+#include \"elf.h\"\n+#endif\n \n int\n main(int argc, char **argv)\n--- a/scripts/mod/modpost.h\n+++ b/scripts/mod/modpost.h\n@@ -8,7 +8,11 @@\n #include <sys/mman.h>\n #include <fcntl.h>\n #include <unistd.h>\n+#if !(defined(__APPLE__) || defined(__CYGWIN__))\n #include <elf.h>\n+#else\n+#include \"elf.h\"\n+#endif\n \n #include \"elfconfig.h\"\n \n"
  },
  {
    "path": "target/linux/generic/hack-5.15/211-darwin-uuid-typedef-clash.patch",
    "content": "From e44fc2af1ddc452b6659d08c16973d65c73b7d0a Mon Sep 17 00:00:00 2001\nFrom: Kevin Darbyshire-Bryant <ldir@darbyshire-bryant.me.uk>\nDate: Wed, 5 Feb 2020 18:36:43 +0000\nSubject: [PATCH] file2alias: build on macos\n\nSigned-off-by: Kevin Darbyshire-Bryant <ldir@darbyshire-bryant.me.uk>\n---\n scripts/mod/file2alias.c | 3 +++\n 1 file changed, 3 insertions(+)\n\n--- a/scripts/mod/file2alias.c\n+++ b/scripts/mod/file2alias.c\n@@ -38,6 +38,9 @@ typedef struct {\n \t__u8 b[16];\n } guid_t;\n \n+#ifdef __APPLE__\n+#define uuid_t compat_uuid_t\n+#endif\n /* backwards compatibility, don't use in new code */\n typedef struct {\n \t__u8 b[16];\n"
  },
  {
    "path": "target/linux/generic/hack-5.15/212-tools_portability.patch",
    "content": "From 48232d3d931c95953ce2ddfe7da7bb164aef6a73 Mon Sep 17 00:00:00 2001\nFrom: Felix Fietkau <nbd@nbd.name>\nDate: Fri, 7 Jul 2017 17:03:16 +0200\nSubject: fix portability of some includes files in tools/ used on the host\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n tools/include/tools/be_byteshift.h |  4 ++++\n tools/include/tools/le_byteshift.h |  4 ++++\n tools/include/tools/linux_types.h  | 22 ++++++++++++++++++++++\n 3 files changed, 30 insertions(+)\n create mode 100644 tools/include/tools/linux_types.h\n\n--- a/tools/include/tools/be_byteshift.h\n+++ b/tools/include/tools/be_byteshift.h\n@@ -2,6 +2,10 @@\n #ifndef _TOOLS_BE_BYTESHIFT_H\n #define _TOOLS_BE_BYTESHIFT_H\n \n+#ifndef __linux__\n+#include \"linux_types.h\"\n+#endif\n+\n #include <stdint.h>\n \n static inline uint16_t __get_unaligned_be16(const uint8_t *p)\n--- a/tools/include/tools/le_byteshift.h\n+++ b/tools/include/tools/le_byteshift.h\n@@ -2,6 +2,10 @@\n #ifndef _TOOLS_LE_BYTESHIFT_H\n #define _TOOLS_LE_BYTESHIFT_H\n \n+#ifndef __linux__\n+#include \"linux_types.h\"\n+#endif\n+\n #include <stdint.h>\n \n static inline uint16_t __get_unaligned_le16(const uint8_t *p)\n--- /dev/null\n+++ b/tools/include/tools/linux_types.h\n@@ -0,0 +1,26 @@\n+#ifndef __LINUX_TYPES_H\n+#define __LINUX_TYPES_H\n+\n+#include <stdint.h>\n+\n+typedef int8_t __s8;\n+typedef uint8_t __u8;\n+typedef uint8_t __be8;\n+typedef uint8_t __le8;\n+\n+typedef int16_t __s16;\n+typedef uint16_t __u16;\n+typedef uint16_t __be16;\n+typedef uint16_t __le16;\n+\n+typedef int32_t __s32;\n+typedef uint32_t __u32;\n+typedef uint32_t __be32;\n+typedef uint32_t __le32;\n+\n+typedef int64_t __s64;\n+typedef uint64_t __u64;\n+typedef uint64_t __be64;\n+typedef uint64_t __le64;\n+\n+#endif\n--- a/tools/include/linux/types.h\n+++ b/tools/include/linux/types.h\n@@ -10,8 +10,12 @@\n #define __SANE_USERSPACE_TYPES__\t/* For PPC64, to get LL64 types */\n #endif\n \n+#ifndef __linux__\n+#include <tools/linux_types.h>\n+#else\n #include <asm/types.h>\n #include <asm/posix_types.h>\n+#endif\n \n struct page;\n struct kmem_cache;\n--- a/tools/perf/pmu-events/jevents.c\n+++ b/tools/perf/pmu-events/jevents.c\n@@ -1,4 +1,6 @@\n+#ifdef __linux__\n #define  _XOPEN_SOURCE 500\t/* needed for nftw() */\n+#endif\n #define  _GNU_SOURCE\t\t/* needed for asprintf() */\n \n /* Parse event JSON files */\n@@ -35,6 +37,7 @@\n #include <stdlib.h>\n #include <errno.h>\n #include <string.h>\n+#include <strings.h>\n #include <ctype.h>\n #include <unistd.h>\n #include <stdarg.h>\n--- a/tools/perf/pmu-events/json.c\n+++ b/tools/perf/pmu-events/json.c\n@@ -38,7 +38,6 @@\n #include <unistd.h>\n #include \"jsmn.h\"\n #include \"json.h\"\n-#include <linux/kernel.h>\n \n \n static char *mapfile(const char *fn, size_t *size)\n"
  },
  {
    "path": "target/linux/generic/hack-5.15/214-spidev_h_portability.patch",
    "content": "From be9be95ff10e16a5b4ad36f903978d0cc5747024 Mon Sep 17 00:00:00 2001\nFrom: Felix Fietkau <nbd@nbd.name>\nDate: Fri, 7 Jul 2017 17:04:08 +0200\nSubject: kernel: fix linux/spi/spidev.h portability issues with musl\n\nFelix will try to get this define included into musl\n\nlede-commit: 795e7cf60de19e7a076a46874fab7bb88b43bbff\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n include/uapi/linux/spi/spidev.h | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/include/uapi/linux/spi/spidev.h\n+++ b/include/uapi/linux/spi/spidev.h\n@@ -93,7 +93,7 @@ struct spi_ioc_transfer {\n \n /* not all platforms use <asm-generic/ioctl.h> or _IOC_TYPECHECK() ... */\n #define SPI_MSGSIZE(N) \\\n-\t((((N)*(sizeof (struct spi_ioc_transfer))) < (1 << _IOC_SIZEBITS)) \\\n+\t((((N)*(sizeof (struct spi_ioc_transfer))) < (1 << 13)) \\\n \t\t? ((N)*(sizeof (struct spi_ioc_transfer))) : 0)\n #define SPI_IOC_MESSAGE(N) _IOW(SPI_IOC_MAGIC, 0, char[SPI_MSGSIZE(N)])\n \n"
  },
  {
    "path": "target/linux/generic/hack-5.15/220-arm-gc_sections.patch",
    "content": "From e3d8676f5722b7622685581e06e8f53e6138e3ab Mon Sep 17 00:00:00 2001\nFrom: Felix Fietkau <nbd@nbd.name>\nDate: Sat, 15 Jul 2017 23:42:36 +0200\nSubject: use -ffunction-sections, -fdata-sections and --gc-sections\n\nIn combination with kernel symbol export stripping this significantly reduces\nthe kernel image size. Used on both ARM and MIPS architectures.\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\nSigned-off-by: Jonas Gorski <jogo@openwrt.org>\nSigned-off-by: Gabor Juhos <juhosg@openwrt.org>\n---\n--- a/arch/arm/Kconfig\n+++ b/arch/arm/Kconfig\n@@ -117,6 +117,7 @@ config ARM\n \tselect HAVE_UID16\n \tselect HAVE_VIRT_CPU_ACCOUNTING_GEN\n \tselect IRQ_FORCED_THREADING\n+\tselect HAVE_LD_DEAD_CODE_DATA_ELIMINATION\n \tselect MODULES_USE_ELF_REL\n \tselect NEED_DMA_MAP_STATE\n \tselect OF_EARLY_FLATTREE if OF\n--- a/arch/arm/boot/compressed/Makefile\n+++ b/arch/arm/boot/compressed/Makefile\n@@ -92,6 +92,7 @@ endif\n ifeq ($(CONFIG_USE_OF),y)\n OBJS\t+= $(libfdt_objs) fdt_check_mem_start.o\n endif\n+KBUILD_CFLAGS_KERNEL := $(patsubst -f%-sections,,$(KBUILD_CFLAGS_KERNEL))\n \n # -fstack-protector-strong triggers protection checks in this code,\n # but it is being used too early to link to meaningful stack_chk logic.\n--- a/arch/arm/kernel/vmlinux.lds.S\n+++ b/arch/arm/kernel/vmlinux.lds.S\n@@ -75,7 +75,7 @@ SECTIONS\n \t. = ALIGN(4);\n \t__ex_table : AT(ADDR(__ex_table) - LOAD_OFFSET) {\n \t\t__start___ex_table = .;\n-\t\tARM_MMU_KEEP(*(__ex_table))\n+\t\tKEEP(*(__ex_table))\n \t\t__stop___ex_table = .;\n \t}\n \n@@ -100,24 +100,24 @@ SECTIONS\n \t}\n \t.init.arch.info : {\n \t\t__arch_info_begin = .;\n-\t\t*(.arch.info.init)\n+\t\tKEEP(*(.arch.info.init))\n \t\t__arch_info_end = .;\n \t}\n \t.init.tagtable : {\n \t\t__tagtable_begin = .;\n-\t\t*(.taglist.init)\n+\t\tKEEP(*(.taglist.init))\n \t\t__tagtable_end = .;\n \t}\n #ifdef CONFIG_SMP_ON_UP\n \t.init.smpalt : {\n \t\t__smpalt_begin = .;\n-\t\t*(.alt.smp.init)\n+\t\tKEEP(*(.alt.smp.init))\n \t\t__smpalt_end = .;\n \t}\n #endif\n \t.init.pv_table : {\n \t\t__pv_table_begin = .;\n-\t\t*(.pv_table)\n+\t\tKEEP(*(.pv_table))\n \t\t__pv_table_end = .;\n \t}\n \n--- a/arch/arm/include/asm/vmlinux.lds.h\n+++ b/arch/arm/include/asm/vmlinux.lds.h\n@@ -42,13 +42,13 @@\n #define PROC_INFO\t\t\t\t\t\t\t\\\n \t\t. = ALIGN(4);\t\t\t\t\t\t\\\n \t\t__proc_info_begin = .;\t\t\t\t\t\\\n-\t\t*(.proc.info.init)\t\t\t\t\t\\\n+\t\tKEEP(*(.proc.info.init))\t\t\t\t\\\n \t\t__proc_info_end = .;\n \n #define IDMAP_TEXT\t\t\t\t\t\t\t\\\n \t\tALIGN_FUNCTION();\t\t\t\t\t\\\n \t\t__idmap_text_start = .;\t\t\t\t\t\\\n-\t\t*(.idmap.text)\t\t\t\t\t\t\\\n+\t\tKEEP(*(.idmap.text))\t\t\t\t\t\\\n \t\t__idmap_text_end = .;\t\t\t\t\t\\\n \n #define ARM_DISCARD\t\t\t\t\t\t\t\\\n@@ -109,12 +109,12 @@\n \t. = ALIGN(8);\t\t\t\t\t\t\t\\\n \t.ARM.unwind_idx : {\t\t\t\t\t\t\\\n \t\t__start_unwind_idx = .;\t\t\t\t\t\\\n-\t\t*(.ARM.exidx*)\t\t\t\t\t\t\\\n+\t\tKEEP(*(.ARM.exidx*))\t\t\t\t\t\\\n \t\t__stop_unwind_idx = .;\t\t\t\t\t\\\n \t}\t\t\t\t\t\t\t\t\\\n \t.ARM.unwind_tab : {\t\t\t\t\t\t\\\n \t\t__start_unwind_tab = .;\t\t\t\t\t\\\n-\t\t*(.ARM.extab*)\t\t\t\t\t\t\\\n+\t\tKEEP(*(.ARM.extab*))\t\t\t\t\t\\\n \t\t__stop_unwind_tab = .;\t\t\t\t\t\\\n \t}\n \n@@ -126,7 +126,7 @@\n \t__vectors_lma = .;\t\t\t\t\t\t\\\n \tOVERLAY 0xffff0000 : NOCROSSREFS AT(__vectors_lma) {\t\t\\\n \t\t.vectors {\t\t\t\t\t\t\\\n-\t\t\t*(.vectors)\t\t\t\t\t\\\n+\t\t\tKEEP(*(.vectors))\t\t\t\t\\\n \t\t}\t\t\t\t\t\t\t\\\n \t\t.vectors.bhb.loop8 {\t\t\t\t\t\\\n \t\t\t*(.vectors.bhb.loop8)\t\t\t\t\\\n@@ -144,7 +144,7 @@\n \t\t\t\t\t\t\t\t\t\\\n \t__stubs_lma = .;\t\t\t\t\t\t\\\n \t.stubs ADDR(.vectors) + 0x1000 : AT(__stubs_lma) {\t\t\\\n-\t\t*(.stubs)\t\t\t\t\t\t\\\n+\t\tKEEP(*(.stubs))\t\t\t\t\t\t\\\n \t}\t\t\t\t\t\t\t\t\\\n \tARM_LMA(__stubs, .stubs);\t\t\t\t\t\\\n \t. = __stubs_lma + SIZEOF(.stubs);\t\t\t\t\\\n"
  },
  {
    "path": "target/linux/generic/hack-5.15/221-module_exports.patch",
    "content": "From b14784e7883390c20ed3ff904892255404a5914b Mon Sep 17 00:00:00 2001\nFrom: Felix Fietkau <nbd@nbd.name>\nDate: Fri, 7 Jul 2017 17:05:53 +0200\nSubject: add an optional config option for stripping all unnecessary symbol exports from the kernel image\n\nlede-commit: bb5a40c64b7c4f4848509fa0a6625055fc9e66cc\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n include/asm-generic/vmlinux.lds.h | 18 +++++++++++++++---\n include/linux/export.h            |  9 ++++++++-\n scripts/Makefile.build            |  2 +-\n 3 files changed, 24 insertions(+), 5 deletions(-)\n\n--- a/include/asm-generic/vmlinux.lds.h\n+++ b/include/asm-generic/vmlinux.lds.h\n@@ -81,6 +81,16 @@\n #define RO_EXCEPTION_TABLE\n #endif\n \n+#ifndef SYMTAB_KEEP\n+#define SYMTAB_KEEP KEEP(*(SORT(___ksymtab+*)))\n+#define SYMTAB_KEEP_GPL KEEP(*(SORT(___ksymtab_gpl+*)))\n+#endif\n+\n+#ifndef SYMTAB_DISCARD\n+#define SYMTAB_DISCARD\n+#define SYMTAB_DISCARD_GPL\n+#endif\n+\n /* Align . to a 8 byte boundary equals to maximum function alignment. */\n #define ALIGN_FUNCTION()  . = ALIGN(8)\n \n@@ -484,14 +494,14 @@\n \t/* Kernel symbol table: Normal symbols */\t\t\t\\\n \t__ksymtab         : AT(ADDR(__ksymtab) - LOAD_OFFSET) {\t\t\\\n \t\t__start___ksymtab = .;\t\t\t\t\t\\\n-\t\tKEEP(*(SORT(___ksymtab+*)))\t\t\t\t\\\n+\t\tSYMTAB_KEEP\t\t\t\t\t\t\\\n \t\t__stop___ksymtab = .;\t\t\t\t\t\\\n \t}\t\t\t\t\t\t\t\t\\\n \t\t\t\t\t\t\t\t\t\\\n \t/* Kernel symbol table: GPL-only symbols */\t\t\t\\\n \t__ksymtab_gpl     : AT(ADDR(__ksymtab_gpl) - LOAD_OFFSET) {\t\\\n \t\t__start___ksymtab_gpl = .;\t\t\t\t\\\n-\t\tKEEP(*(SORT(___ksymtab_gpl+*)))\t\t\t\t\\\n+\t\tSYMTAB_KEEP_GPL\t\t\t\t\t\t\\\n \t\t__stop___ksymtab_gpl = .;\t\t\t\t\\\n \t}\t\t\t\t\t\t\t\t\\\n \t\t\t\t\t\t\t\t\t\\\n@@ -511,7 +521,7 @@\n \t\t\t\t\t\t\t\t\t\\\n \t/* Kernel symbol table: strings */\t\t\t\t\\\n         __ksymtab_strings : AT(ADDR(__ksymtab_strings) - LOAD_OFFSET) {\t\\\n-\t\t*(__ksymtab_strings)\t\t\t\t\t\\\n+\t\t*(__ksymtab_strings+*)\t\t\t\t\t\\\n \t}\t\t\t\t\t\t\t\t\\\n \t\t\t\t\t\t\t\t\t\\\n \t/* __*init sections */\t\t\t\t\t\t\\\n@@ -1018,6 +1028,8 @@\n \n #define COMMON_DISCARDS\t\t\t\t\t\t\t\\\n \tSANITIZER_DISCARDS\t\t\t\t\t\t\\\n+\tSYMTAB_DISCARD\t\t\t\t\t\t\t\\\n+\tSYMTAB_DISCARD_GPL\t\t\t\t\t\t\\\n \t*(.discard)\t\t\t\t\t\t\t\\\n \t*(.discard.*)\t\t\t\t\t\t\t\\\n \t*(.modinfo)\t\t\t\t\t\t\t\\\n--- a/include/linux/export.h\n+++ b/include/linux/export.h\n@@ -82,6 +82,12 @@ struct kernel_symbol {\n \n #else\n \n+#ifdef MODULE\n+#define __EXPORT_SUFFIX(sym)\n+#else\n+#define __EXPORT_SUFFIX(sym) \"+\" #sym\n+#endif\n+\n /*\n  * For every exported symbol, do the following:\n  *\n@@ -99,7 +105,7 @@ struct kernel_symbol {\n \textern const char __kstrtab_##sym[];\t\t\t\t\t\\\n \textern const char __kstrtabns_##sym[];\t\t\t\t\t\\\n \t__CRC_SYMBOL(sym, sec);\t\t\t\t\t\t\t\\\n-\tasm(\"\t.section \\\"__ksymtab_strings\\\",\\\"aMS\\\",%progbits,1\t\\n\"\t\\\n+\tasm(\"\t.section \\\"__ksymtab_strings\" __EXPORT_SUFFIX(sym) \"\\\",\\\"aMS\\\",%progbits,1\t\\n\"\t\\\n \t    \"__kstrtab_\" #sym \":\t\t\t\t\t\\n\"\t\\\n \t    \"\t.asciz \t\\\"\" #sym \"\\\"\t\t\t\t\t\\n\"\t\\\n \t    \"__kstrtabns_\" #sym \":\t\t\t\t\t\\n\"\t\\\n--- a/scripts/Makefile.build\n+++ b/scripts/Makefile.build\n@@ -385,7 +385,7 @@ targets += $(real-dtb-y) $(lib-y) $(alwa\n # Linker scripts preprocessor (.lds.S -> .lds)\n # ---------------------------------------------------------------------------\n quiet_cmd_cpp_lds_S = LDS     $@\n-      cmd_cpp_lds_S = $(CPP) $(cpp_flags) -P -U$(ARCH) \\\n+      cmd_cpp_lds_S = $(CPP) $(EXTRA_LDSFLAGS) $(cpp_flags) -P -U$(ARCH) \\\n \t                     -D__ASSEMBLY__ -DLINKER_SCRIPT -o $@ $<\n \n $(obj)/%.lds: $(src)/%.lds.S FORCE\n"
  },
  {
    "path": "target/linux/generic/hack-5.15/230-openwrt_lzma_options.patch",
    "content": "From b3d00b452467f621317953d9e4c6f9ae8dcfd271 Mon Sep 17 00:00:00 2001\nFrom: Imre Kaloz <kaloz@openwrt.org>\nDate: Fri, 7 Jul 2017 17:06:55 +0200\nSubject: use the openwrt lzma options for now\n\nlede-commit: 548de949f392049420a6a1feeef118b30ab8ea8c\nSigned-off-by: Imre Kaloz <kaloz@openwrt.org>\n---\n lib/decompress.c              |  1 +\n scripts/Makefile.lib          |  2 +-\n usr/gen_initramfs_list.sh | 10 +++++-----\n 3 files changed, 7 insertions(+), 6 deletions(-)\n\n--- a/lib/decompress.c\n+++ b/lib/decompress.c\n@@ -53,6 +53,7 @@ static const struct compress_format comp\n \t{ {0x1f, 0x9e}, \"gzip\", gunzip },\n \t{ {0x42, 0x5a}, \"bzip2\", bunzip2 },\n \t{ {0x5d, 0x00}, \"lzma\", unlzma },\n+\t{ {0x6d, 0x00}, \"lzma-openwrt\", unlzma },\n \t{ {0xfd, 0x37}, \"xz\", unxz },\n \t{ {0x89, 0x4c}, \"lzo\", unlzo },\n \t{ {0x02, 0x21}, \"lz4\", unlz4 },\n--- a/scripts/Makefile.lib\n+++ b/scripts/Makefile.lib\n@@ -413,7 +413,7 @@ quiet_cmd_bzip2 = BZIP2   $@\n # ---------------------------------------------------------------------------\n \n quiet_cmd_lzma = LZMA    $@\n-      cmd_lzma = { cat $(real-prereqs) | $(LZMA) -9; $(size_append); } > $@\n+      cmd_lzma = { cat $(real-prereqs) | $(LZMA) e -d20 -lc1 -lp2 -pb2 -eos -si -so; $(size_append); } > $@\n \n quiet_cmd_lzo = LZO     $@\n       cmd_lzo = { cat $(real-prereqs) | $(KLZOP) -9; $(size_append); } > $@\n"
  },
  {
    "path": "target/linux/generic/hack-5.15/249-udp-tunnel-selection.patch",
    "content": "--- a/net/ipv4/Kconfig\n+++ b/net/ipv4/Kconfig\n@@ -315,7 +315,7 @@ config NET_IPVTI\n \t  on top.\n \n config NET_UDP_TUNNEL\n-\ttristate\n+\ttristate \"IP: UDP tunneling support\"\n \tselect NET_IP_TUNNEL\n \tdefault n\n \n"
  },
  {
    "path": "target/linux/generic/hack-5.15/250-netfilter_depends.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nSubject: hack: net: remove bogus netfilter dependencies\n\nlede-commit: 589d2a377dee27d206fc3725325309cf649e4df6\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n net/netfilter/Kconfig | 2 --\n 1 file changed, 2 deletions(-)\n\n--- a/net/netfilter/Kconfig\n+++ b/net/netfilter/Kconfig\n@@ -243,7 +243,6 @@ config NF_CONNTRACK_FTP\n \n config NF_CONNTRACK_H323\n \ttristate \"H.323 protocol support\"\n-\tdepends on IPV6 || IPV6=n\n \tdepends on NETFILTER_ADVANCED\n \thelp\n \t  H.323 is a VoIP signalling protocol from ITU-T. As one of the most\n@@ -1106,7 +1105,6 @@ config NETFILTER_XT_TARGET_SECMARK\n \n config NETFILTER_XT_TARGET_TCPMSS\n \ttristate '\"TCPMSS\" target support'\n-\tdepends on IPV6 || IPV6=n\n \tdefault m if NETFILTER_ADVANCED=n\n \thelp\n \t  This option adds a `TCPMSS' target, which allows you to alter the\n"
  },
  {
    "path": "target/linux/generic/hack-5.15/251-kconfig.patch",
    "content": "From da3c50704f14132f4adf80d48e9a4cd5d46e54c9 Mon Sep 17 00:00:00 2001\nFrom: John Crispin <john@phrozen.org>\nDate: Fri, 7 Jul 2017 17:09:21 +0200\nSubject: kconfig: owrt specifc dependencies\n\nSigned-off-by: John Crispin <john@phrozen.org>\n---\n crypto/Kconfig        | 10 +++++-----\n drivers/bcma/Kconfig  |  1 +\n drivers/ssb/Kconfig   |  3 ++-\n lib/Kconfig           |  8 ++++----\n net/netfilter/Kconfig |  2 +-\n net/wireless/Kconfig  | 17 ++++++++++-------\n sound/core/Kconfig    |  4 ++--\n 7 files changed, 25 insertions(+), 20 deletions(-)\n\n--- a/crypto/Kconfig\n+++ b/crypto/Kconfig\n@@ -33,7 +33,7 @@ config CRYPTO_FIPS\n \t  this is.\n \n config CRYPTO_ALGAPI\n-\ttristate\n+\ttristate \"ALGAPI\"\n \tselect CRYPTO_ALGAPI2\n \thelp\n \t  This option provides the API for cryptographic algorithms.\n@@ -42,7 +42,7 @@ config CRYPTO_ALGAPI2\n \ttristate\n \n config CRYPTO_AEAD\n-\ttristate\n+\ttristate \"AEAD\"\n \tselect CRYPTO_AEAD2\n \tselect CRYPTO_ALGAPI\n \n@@ -53,7 +53,7 @@ config CRYPTO_AEAD2\n \tselect CRYPTO_RNG2\n \n config CRYPTO_SKCIPHER\n-\ttristate\n+\ttristate \"SKCIPHER\"\n \tselect CRYPTO_SKCIPHER2\n \tselect CRYPTO_ALGAPI\n \n@@ -63,7 +63,7 @@ config CRYPTO_SKCIPHER2\n \tselect CRYPTO_RNG2\n \n config CRYPTO_HASH\n-\ttristate\n+\ttristate \"HASH\"\n \tselect CRYPTO_HASH2\n \tselect CRYPTO_ALGAPI\n \n@@ -72,7 +72,7 @@ config CRYPTO_HASH2\n \tselect CRYPTO_ALGAPI2\n \n config CRYPTO_RNG\n-\ttristate\n+\ttristate \"RNG\"\n \tselect CRYPTO_RNG2\n \tselect CRYPTO_ALGAPI\n \n--- a/drivers/bcma/Kconfig\n+++ b/drivers/bcma/Kconfig\n@@ -16,6 +16,7 @@ if BCMA\n # Support for Block-I/O. SELECT this from the driver that needs it.\n config BCMA_BLOCKIO\n \tbool\n+\tdefault y\n \n config BCMA_HOST_PCI_POSSIBLE\n \tbool\n--- a/drivers/ssb/Kconfig\n+++ b/drivers/ssb/Kconfig\n@@ -29,6 +29,7 @@ config SSB_SPROM\n config SSB_BLOCKIO\n \tbool\n \tdepends on SSB\n+\tdefault y\n \n config SSB_PCIHOST_POSSIBLE\n \tbool\n@@ -49,7 +50,7 @@ config SSB_PCIHOST\n config SSB_B43_PCI_BRIDGE\n \tbool\n \tdepends on SSB_PCIHOST\n-\tdefault n\n+\tdefault y\n \n config SSB_PCMCIAHOST_POSSIBLE\n \tbool\n--- a/lib/Kconfig\n+++ b/lib/Kconfig\n@@ -438,16 +438,16 @@ config BCH_CONST_T\n # Textsearch support is select'ed if needed\n #\n config TEXTSEARCH\n-\tbool\n+\tbool \"Textsearch support\"\n \n config TEXTSEARCH_KMP\n-\ttristate\n+\ttristate \"Textsearch KMP\"\n \n config TEXTSEARCH_BM\n-\ttristate\n+\ttristate \"Textsearch BM\"\n \n config TEXTSEARCH_FSM\n-\ttristate\n+\ttristate \"Textsearch FSM\"\n \n config BTREE\n \tbool\n--- a/net/netfilter/Kconfig\n+++ b/net/netfilter/Kconfig\n@@ -11,7 +11,7 @@ config NETFILTER_INGRESS\n \t  infrastructure.\n \n config NETFILTER_NETLINK\n-\ttristate\n+\ttristate \"Netfilter NFNETLINK interface\"\n \n config NETFILTER_FAMILY_BRIDGE\n \tbool\n--- a/net/wireless/Kconfig\n+++ b/net/wireless/Kconfig\n@@ -1,6 +1,6 @@\n # SPDX-License-Identifier: GPL-2.0-only\n config WIRELESS_EXT\n-\tbool\n+\tbool \"Wireless extensions\"\n \n config WEXT_CORE\n \tdef_bool y\n@@ -12,10 +12,10 @@ config WEXT_PROC\n \tdepends on WEXT_CORE\n \n config WEXT_SPY\n-\tbool\n+\tbool \"WEXT_SPY\"\n \n config WEXT_PRIV\n-\tbool\n+\tbool \"WEXT_PRIV\"\n \n config CFG80211\n \ttristate \"cfg80211 - wireless configuration API\"\n@@ -204,7 +204,7 @@ config CFG80211_WEXT_EXPORT\n endif # CFG80211\n \n config LIB80211\n-\ttristate\n+\ttristate \"LIB80211\"\n \tdefault n\n \thelp\n \t  This options enables a library of common routines used\n@@ -213,17 +213,17 @@ config LIB80211\n \t  Drivers should select this themselves if needed.\n \n config LIB80211_CRYPT_WEP\n-\ttristate\n+\ttristate \"LIB80211_CRYPT_WEP\"\n \tselect CRYPTO_LIB_ARC4\n \n config LIB80211_CRYPT_CCMP\n-\ttristate\n+\ttristate \"LIB80211_CRYPT_CCMP\"\n \tselect CRYPTO\n \tselect CRYPTO_AES\n \tselect CRYPTO_CCM\n \n config LIB80211_CRYPT_TKIP\n-\ttristate\n+\ttristate \"LIB80211_CRYPT_TKIP\"\n \tselect CRYPTO_LIB_ARC4\n \n config LIB80211_DEBUG\n--- a/sound/core/Kconfig\n+++ b/sound/core/Kconfig\n@@ -17,7 +17,7 @@ config SND_DMAENGINE_PCM\n \ttristate\n \n config SND_HWDEP\n-\ttristate\n+\ttristate \"Sound hardware support\"\n \n config SND_SEQ_DEVICE\n \ttristate\n@@ -27,7 +27,7 @@ config SND_RAWMIDI\n \tselect SND_SEQ_DEVICE if SND_SEQUENCER != n\n \n config SND_COMPRESS_OFFLOAD\n-\ttristate\n+\ttristate \"Compression offloading support\"\n \n config SND_JACK\n \tbool\n"
  },
  {
    "path": "target/linux/generic/hack-5.15/252-SATA_PMP.patch",
    "content": "From 8c817e33be829c7249c2cfd59ff48ad5fac6a31d Mon Sep 17 00:00:00 2001\nFrom: Sungbo Eo <mans0n@gorani.run>\nDate: Fri, 7 Jul 2017 17:09:21 +0200\nSubject: [PATCH] kconfig: solidify SATA_PMP config\n\nSATA_PMP option in kernel config file disappears for every kernel_oldconfig refresh.\nTo prevent this, SATA_HOST is now selected automatically when SATA_PMP is enabled.\nThis patch can be dropped if SATA_MV is ever re-added into the config.\n---\n drivers/ata/Kconfig | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/drivers/ata/Kconfig\n+++ b/drivers/ata/Kconfig\n@@ -112,7 +112,7 @@ config SATA_ZPODD\n \n config SATA_PMP\n \tbool \"SATA Port Multiplier support\"\n-\tdepends on SATA_HOST\n+\tselect SATA_HOST\n \tdefault y\n \thelp\n \t  This option adds support for SATA Port Multipliers\n"
  },
  {
    "path": "target/linux/generic/hack-5.15/253-ksmbd-config.patch",
    "content": "--- a/init/Kconfig\n+++ b/init/Kconfig\n@@ -2379,7 +2379,7 @@ config PADATA\n \tbool\n \n config ASN1\n-\ttristate\n+\ttristate \"ASN1\"\n \thelp\n \t  Build a simple ASN.1 grammar compiler that produces a bytecode output\n \t  that can be interpreted by the ASN.1 stream decoder and used to\n--- a/lib/Kconfig\n+++ b/lib/Kconfig\n@@ -609,7 +609,7 @@ config LIBFDT\n \tbool\n \n config OID_REGISTRY\n-\ttristate\n+\ttristate \"OID\"\n \thelp\n \t  Enable fast lookup object identifier registry.\n \n"
  },
  {
    "path": "target/linux/generic/hack-5.15/259-regmap_dynamic.patch",
    "content": "From 811d9e2268a62b830cfe93cd8bc929afcb8b198b Mon Sep 17 00:00:00 2001\nFrom: Felix Fietkau <nbd@nbd.name>\nDate: Sat, 15 Jul 2017 21:12:38 +0200\nSubject: kernel: move regmap bloat out of the kernel image if it is only being used in modules\n\nlede-commit: 96f39119815028073583e4fca3a9c5fe9141e998\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n drivers/base/regmap/Kconfig  | 15 ++++++++++-----\n drivers/base/regmap/Makefile | 12 ++++++++----\n drivers/base/regmap/regmap.c |  3 +++\n include/linux/regmap.h       |  2 +-\n 4 files changed, 22 insertions(+), 10 deletions(-)\n\n--- a/drivers/base/regmap/Kconfig\n+++ b/drivers/base/regmap/Kconfig\n@@ -4,10 +4,9 @@\n # subsystems should select the appropriate symbols.\n \n config REGMAP\n-\tdefault y if (REGMAP_I2C || REGMAP_SPI || REGMAP_SPMI || REGMAP_W1 || REGMAP_AC97 || REGMAP_MMIO || REGMAP_IRQ || REGMAP_SOUNDWIRE || REGMAP_SOUNDWIRE_MBQ || REGMAP_SCCB || REGMAP_I3C || REGMAP_SPI_AVMM || REGMAP_MDIO)\n \tselect IRQ_DOMAIN if REGMAP_IRQ\n \tselect MDIO_BUS if REGMAP_MDIO\n-\tbool\n+\ttristate\n \n config REGCACHE_COMPRESSED\n \tselect LZO_COMPRESS\n@@ -15,53 +14,67 @@ config REGCACHE_COMPRESSED\n \tbool\n \n config REGMAP_AC97\n+\tselect REGMAP\n \ttristate\n \n config REGMAP_I2C\n+\tselect REGMAP\n \ttristate\n \tdepends on I2C\n \n config REGMAP_SLIMBUS\n+\tselect REGMAP\n \ttristate\n \tdepends on SLIMBUS\n \n config REGMAP_SPI\n+\tselect REGMAP\n \ttristate\n \tdepends on SPI\n \n config REGMAP_SPMI\n+\tselect REGMAP\n \ttristate\n \tdepends on SPMI\n \n config REGMAP_W1\n+\tselect REGMAP\n \ttristate\n \tdepends on W1\n \n config REGMAP_MDIO\n+\tselect REGMAP\n \ttristate\n \n config REGMAP_MMIO\n+\tselect REGMAP\n \ttristate\n \n config REGMAP_IRQ\n+\tselect REGMAP\n \tbool\n \n config REGMAP_SOUNDWIRE\n+\tselect REGMAP\n \ttristate\n \tdepends on SOUNDWIRE\n \n config REGMAP_SOUNDWIRE_MBQ\n+\tselect REGMAP\n \ttristate\n \tdepends on SOUNDWIRE\n \n config REGMAP_SCCB\n+\tselect REGMAP\n \ttristate\n \tdepends on I2C\n \n config REGMAP_I3C\n+\tselect REGMAP\n \ttristate\n \tdepends on I3C\n \n config REGMAP_SPI_AVMM\n+\tselect REGMAP\n \ttristate\n \tdepends on SPI\n--- a/drivers/base/regmap/Makefile\n+++ b/drivers/base/regmap/Makefile\n@@ -2,10 +2,14 @@\n # For include/trace/define_trace.h to include trace.h\n CFLAGS_regmap.o := -I$(src)\n \n-obj-$(CONFIG_REGMAP) += regmap.o regcache.o\n-obj-$(CONFIG_REGMAP) += regcache-rbtree.o regcache-flat.o\n-obj-$(CONFIG_REGCACHE_COMPRESSED) += regcache-lzo.o\n-obj-$(CONFIG_DEBUG_FS) += regmap-debugfs.o\n+regmap-core-objs = regmap.o regcache.o regcache-rbtree.o regcache-flat.o\n+ifdef CONFIG_DEBUG_FS\n+regmap-core-objs += regmap-debugfs.o\n+endif\n+ifdef CONFIG_REGCACHE_COMPRESSED\n+regmap-core-objs += regcache-lzo.o\n+endif\n+obj-$(CONFIG_REGMAP) += regmap-core.o\n obj-$(CONFIG_REGMAP_AC97) += regmap-ac97.o\n obj-$(CONFIG_REGMAP_I2C) += regmap-i2c.o\n obj-$(CONFIG_REGMAP_SLIMBUS) += regmap-slimbus.o\n--- a/drivers/base/regmap/regmap.c\n+++ b/drivers/base/regmap/regmap.c\n@@ -9,6 +9,7 @@\n #include <linux/device.h>\n #include <linux/slab.h>\n #include <linux/export.h>\n+#include <linux/module.h>\n #include <linux/mutex.h>\n #include <linux/err.h>\n #include <linux/property.h>\n@@ -3341,3 +3342,5 @@ static int __init regmap_initcall(void)\n \treturn 0;\n }\n postcore_initcall(regmap_initcall);\n+\n+MODULE_LICENSE(\"GPL\");\n--- a/include/linux/regmap.h\n+++ b/include/linux/regmap.h\n@@ -180,7 +180,7 @@ struct reg_sequence {\n \t__ret ?: __tmp; \\\n })\n \n-#ifdef CONFIG_REGMAP\n+#if IS_REACHABLE(CONFIG_REGMAP)\n \n enum regmap_endian {\n \t/* Unspecified -> 0 -> Backwards compatible default */\n"
  },
  {
    "path": "target/linux/generic/hack-5.15/260-crypto_test_dependencies.patch",
    "content": "From fd1799b0bf5efa46dd3e6dfbbf3955564807e508 Mon Sep 17 00:00:00 2001\nFrom: Felix Fietkau <nbd@nbd.name>\nDate: Fri, 7 Jul 2017 17:12:51 +0200\nSubject: kernel: prevent cryptomgr from pulling in useless extra dependencies for tests that are not run\n\nReduces kernel size after LZMA by about 5k on MIPS\n\nlede-commit: 044c316167e076479a344c59905e5b435b84a77f\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n crypto/Kconfig   | 13 ++++++-------\n crypto/algboss.c |  4 ++++\n 2 files changed, 10 insertions(+), 7 deletions(-)\n\n--- a/crypto/Kconfig\n+++ b/crypto/Kconfig\n@@ -120,13 +120,13 @@ config CRYPTO_MANAGER\n \t  cbc(aes).\n \n config CRYPTO_MANAGER2\n-\tdef_tristate CRYPTO_MANAGER || (CRYPTO_MANAGER!=n && CRYPTO_ALGAPI=y)\n-\tselect CRYPTO_AEAD2\n-\tselect CRYPTO_HASH2\n-\tselect CRYPTO_SKCIPHER2\n-\tselect CRYPTO_AKCIPHER2\n-\tselect CRYPTO_KPP2\n-\tselect CRYPTO_ACOMP2\n+\tdef_tristate CRYPTO_MANAGER || (CRYPTO_MANAGER!=n && CRYPTO_ALGAPI=y && !CRYPTO_MANAGER_DISABLE_TESTS)\n+\tselect CRYPTO_AEAD2 if !CRYPTO_MANAGER_DISABLE_TESTS\n+\tselect CRYPTO_HASH2 if !CRYPTO_MANAGER_DISABLE_TESTS\n+\tselect CRYPTO_SKCIPHER2 if !CRYPTO_MANAGER_DISABLE_TESTS\n+\tselect CRYPTO_AKCIPHER2 if !CRYPTO_MANAGER_DISABLE_TESTS\n+\tselect CRYPTO_KPP2 if !CRYPTO_MANAGER_DISABLE_TESTS\n+\tselect CRYPTO_ACOMP2 if !CRYPTO_MANAGER_DISABLE_TESTS\n \n config CRYPTO_USER\n \ttristate \"Userspace cryptographic algorithm configuration\"\n--- a/crypto/algboss.c\n+++ b/crypto/algboss.c\n@@ -211,8 +211,12 @@ static int cryptomgr_schedule_test(struc\n \ttype = alg->cra_flags;\n \n \t/* Do not test internal algorithms. */\n+#ifdef CONFIG_CRYPTO_MANAGER_DISABLE_TESTS\n+\ttype |= CRYPTO_ALG_TESTED;\n+#else\n \tif (type & CRYPTO_ALG_INTERNAL)\n \t\ttype |= CRYPTO_ALG_TESTED;\n+#endif\n \n \tparam->type = type;\n \n"
  },
  {
    "path": "target/linux/generic/hack-5.15/261-lib-arc4-unhide.patch",
    "content": "This makes it possible to select CONFIG_CRYPTO_LIB_ARC4 directly. We \nneed this to be able to compile this into the kernel and make use of it \nfrom backports.\n\n--- a/lib/crypto/Kconfig\n+++ b/lib/crypto/Kconfig\n@@ -6,7 +6,7 @@ config CRYPTO_LIB_AES\n \ttristate\n \n config CRYPTO_LIB_ARC4\n-\ttristate\n+\ttristate \"ARC4 cipher library\"\n \n config CRYPTO_ARCH_HAVE_LIB_BLAKE2S\n \ttristate\n"
  },
  {
    "path": "target/linux/generic/hack-5.15/280-rfkill-stubs.patch",
    "content": "From 236c1acdfef5958010ac9814a9872e0a46fd78ee Mon Sep 17 00:00:00 2001\nFrom: John Crispin <john@phrozen.org>\nDate: Fri, 7 Jul 2017 17:13:44 +0200\nSubject: rfkill: add fake rfkill support\n\nallow building of modules depending on RFKILL even if RFKILL is not enabled.\n\nSigned-off-by: John Crispin <john@phrozen.org>\n---\n include/linux/rfkill.h |  2 +-\n net/Makefile           |  2 +-\n net/rfkill/Kconfig     | 14 +++++++++-----\n net/rfkill/Makefile    |  2 +-\n 4 files changed, 12 insertions(+), 8 deletions(-)\n\n--- a/include/linux/rfkill.h\n+++ b/include/linux/rfkill.h\n@@ -64,7 +64,7 @@ struct rfkill_ops {\n \tint\t(*set_block)(void *data, bool blocked);\n };\n \n-#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)\n+#if defined(CONFIG_RFKILL_FULL) || defined(CONFIG_RFKILL_FULL_MODULE)\n /**\n  * rfkill_alloc - Allocate rfkill structure\n  * @name: name of the struct -- the string is not copied internally\n--- a/net/Makefile\n+++ b/net/Makefile\n@@ -52,7 +52,7 @@ obj-$(CONFIG_TIPC)\t\t+= tipc/\n obj-$(CONFIG_NETLABEL)\t\t+= netlabel/\n obj-$(CONFIG_IUCV)\t\t+= iucv/\n obj-$(CONFIG_SMC)\t\t+= smc/\n-obj-$(CONFIG_RFKILL)\t\t+= rfkill/\n+obj-$(CONFIG_RFKILL_FULL)\t+= rfkill/\n obj-$(CONFIG_NET_9P)\t\t+= 9p/\n obj-$(CONFIG_CAIF)\t\t+= caif/\n obj-$(CONFIG_DCB)\t\t+= dcb/\n--- a/net/rfkill/Kconfig\n+++ b/net/rfkill/Kconfig\n@@ -2,7 +2,11 @@\n #\n # RF switch subsystem configuration\n #\n-menuconfig RFKILL\n+config RFKILL\n+\tbool\n+\tdefault y\n+\n+menuconfig RFKILL_FULL\n \ttristate \"RF switch subsystem support\"\n \thelp\n \t  Say Y here if you want to have control over RF switches\n@@ -14,19 +18,19 @@ menuconfig RFKILL\n # LED trigger support\n config RFKILL_LEDS\n \tbool\n-\tdepends on RFKILL\n+\tdepends on RFKILL_FULL\n \tdepends on LEDS_TRIGGERS = y || RFKILL = LEDS_TRIGGERS\n \tdefault y\n \n config RFKILL_INPUT\n \tbool \"RF switch input support\" if EXPERT\n-\tdepends on RFKILL\n+\tdepends on RFKILL_FULL\n \tdepends on INPUT = y || RFKILL = INPUT\n \tdefault y if !EXPERT\n \n config RFKILL_GPIO\n \ttristate \"GPIO RFKILL driver\"\n-\tdepends on RFKILL\n+\tdepends on RFKILL_FULL\n \tdepends on GPIOLIB || COMPILE_TEST\n \tdefault n\n \thelp\n--- a/net/rfkill/Makefile\n+++ b/net/rfkill/Makefile\n@@ -5,5 +5,5 @@\n \n rfkill-y\t\t\t+= core.o\n rfkill-$(CONFIG_RFKILL_INPUT)\t+= input.o\n-obj-$(CONFIG_RFKILL)\t\t+= rfkill.o\n+obj-$(CONFIG_RFKILL_FULL)\t+= rfkill.o\n obj-$(CONFIG_RFKILL_GPIO)\t+= rfkill-gpio.o\n"
  },
  {
    "path": "target/linux/generic/hack-5.15/300-MIPS-r4k_cache-use-more-efficient-cache-blast.patch",
    "content": "From: Ben Menchaca <ben.menchaca@qca.qualcomm.com>\nDate: Fri, 7 Jun 2013 18:35:22 -0500\nSubject: MIPS: r4k_cache: use more efficient cache blast\n\nOptimize the compiler output for larger cache blast cases that are\ncommon for DMA-based networking.\n\nSigned-off-by: Ben Menchaca <ben.menchaca@qca.qualcomm.com>\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n--- a/arch/mips/include/asm/r4kcache.h\n+++ b/arch/mips/include/asm/r4kcache.h\n@@ -286,14 +286,46 @@ static inline void prot##extra##blast_##\n \t\t\t\t\t\t    unsigned long end)\t\\\n {\t\t\t\t\t\t\t\t\t\\\n \tunsigned long lsize = cpu_##desc##_line_size();\t\t\t\\\n+\tunsigned long lsize_2 = lsize * 2;\t\t\t\t\\\n+\tunsigned long lsize_3 = lsize * 3;\t\t\t\t\\\n+\tunsigned long lsize_4 = lsize * 4;\t\t\t\t\\\n+\tunsigned long lsize_5 = lsize * 5;\t\t\t\t\\\n+\tunsigned long lsize_6 = lsize * 6;\t\t\t\t\\\n+\tunsigned long lsize_7 = lsize * 7;\t\t\t\t\\\n+\tunsigned long lsize_8 = lsize * 8;\t\t\t\t\\\n \tunsigned long addr = start & ~(lsize - 1);\t\t\t\\\n-\tunsigned long aend = (end - 1) & ~(lsize - 1);\t\t\t\\\n+\tunsigned long aend = (end + lsize - 1) & ~(lsize - 1);\t\t\\\n+\tint lines = (aend - addr) / lsize;\t\t\t\t\\\n \t\t\t\t\t\t\t\t\t\\\n-\twhile (1) {\t\t\t\t\t\t\t\\\n+\twhile (lines >= 8) {\t\t\t\t\t\t\\\n+\t\tprot##cache_op(hitop, addr);\t\t\t\t\\\n+\t\tprot##cache_op(hitop, addr + lsize);\t\t\t\\\n+\t\tprot##cache_op(hitop, addr + lsize_2);\t\t\t\\\n+\t\tprot##cache_op(hitop, addr + lsize_3);\t\t\t\\\n+\t\tprot##cache_op(hitop, addr + lsize_4);\t\t\t\\\n+\t\tprot##cache_op(hitop, addr + lsize_5);\t\t\t\\\n+\t\tprot##cache_op(hitop, addr + lsize_6);\t\t\t\\\n+\t\tprot##cache_op(hitop, addr + lsize_7);\t\t\t\\\n+\t\taddr += lsize_8;\t\t\t\t\t\\\n+\t\tlines -= 8;\t\t\t\t\t\t\\\n+\t}\t\t\t\t\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\tif (lines & 0x4) {\t\t\t\t\t\t\\\n+\t\tprot##cache_op(hitop, addr);\t\t\t\t\\\n+\t\tprot##cache_op(hitop, addr + lsize);\t\t\t\\\n+\t\tprot##cache_op(hitop, addr + lsize_2);\t\t\t\\\n+\t\tprot##cache_op(hitop, addr + lsize_3);\t\t\t\\\n+\t\taddr += lsize_4;\t\t\t\t\t\\\n+\t}\t\t\t\t\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\tif (lines & 0x2) {\t\t\t\t\t\t\\\n+\t\tprot##cache_op(hitop, addr);\t\t\t\t\\\n+\t\tprot##cache_op(hitop, addr + lsize);\t\t\t\\\n+\t\taddr += lsize_2;\t\t\t\t\t\\\n+\t}\t\t\t\t\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+\tif (lines & 0x1) {\t\t\t\t\t\t\\\n \t\tprot##cache_op(hitop, addr);\t\t\t\t\\\n-\t\tif (addr == aend)\t\t\t\t\t\\\n-\t\t\tbreak;\t\t\t\t\t\t\\\n-\t\taddr += lsize;\t\t\t\t\t\t\\\n \t}\t\t\t\t\t\t\t\t\\\n }\n \n"
  },
  {
    "path": "target/linux/generic/hack-5.15/301-mips_image_cmdline_hack.patch",
    "content": "From: John Crispin <john@phrozen.org>\nSubject: hack: kernel: add generic image_cmdline hack to MIPS targets\n\nlede-commit: d59f5b3a987a48508257a0ddbaeadc7909f9f976\nSigned-off-by: Gabor Juhos <juhosg@openwrt.org>\n---\n arch/mips/Kconfig       | 4 ++++\n arch/mips/kernel/head.S | 6 ++++++\n 2 files changed, 10 insertions(+)\n\n--- a/arch/mips/Kconfig\n+++ b/arch/mips/Kconfig\n@@ -1180,6 +1180,10 @@ config MIPS_MSC\n config SYNC_R4K\n \tbool\n \n+config IMAGE_CMDLINE_HACK\n+\tbool \"OpenWrt specific image command line hack\"\n+\tdefault n\n+\n config NO_IOPORT_MAP\n \tdef_bool n\n \n--- a/arch/mips/kernel/head.S\n+++ b/arch/mips/kernel/head.S\n@@ -79,6 +79,12 @@ FEXPORT(__kernel_entry)\n \tj\tkernel_entry\n #endif /* CONFIG_BOOT_RAW */\n \n+#ifdef CONFIG_IMAGE_CMDLINE_HACK\n+\t.ascii\t\"CMDLINE:\"\n+EXPORT(__image_cmdline)\n+\t.fill\t0x400\n+#endif /* CONFIG_IMAGE_CMDLINE_HACK */\n+\n \t__REF\n \n NESTED(kernel_entry, 16, sp)\t\t\t# kernel entry point\n"
  },
  {
    "path": "target/linux/generic/hack-5.15/321-powerpc_crtsavres_prereq.patch",
    "content": "From 107c0964cb8db7ca28ac5199426414fdab3c274d Mon Sep 17 00:00:00 2001\nFrom: \"Alexandros C. Couloumbis\" <alex@ozo.com>\nDate: Fri, 7 Jul 2017 17:14:51 +0200\nSubject: hack: arch: powerpc: drop register save/restore library from modules\n\nUpstream GCC uses a libgcc function for saving/restoring registers. This\nmakes the code bigger, and upstream kernels need to carry that function\nfor every single kernel module. Our GCC is patched to avoid those\nreferences, so we can drop the extra bloat for modules.\n\nlede-commit: e8e1084654f50904e6bf77b70b2de3f137d7b3ec\nSigned-off-by: Alexandros C. Couloumbis <alex@ozo.com>\n---\n arch/powerpc/Makefile | 1 -\n 1 file changed, 1 deletion(-)\n\n--- a/arch/powerpc/Makefile\n+++ b/arch/powerpc/Makefile\n@@ -61,19 +61,6 @@ machine-$(CONFIG_PPC64) += 64\n machine-$(CONFIG_CPU_LITTLE_ENDIAN) += le\n UTS_MACHINE := $(subst $(space),,$(machine-y))\n \n-# XXX This needs to be before we override LD below\n-ifdef CONFIG_PPC32\n-KBUILD_LDFLAGS_MODULE += arch/powerpc/lib/crtsavres.o\n-else\n-ifeq ($(call ld-ifversion, -ge, 22500, y),y)\n-# Have the linker provide sfpr if possible.\n-# There is a corresponding test in arch/powerpc/lib/Makefile\n-KBUILD_LDFLAGS_MODULE += --save-restore-funcs\n-else\n-KBUILD_LDFLAGS_MODULE += arch/powerpc/lib/crtsavres.o\n-endif\n-endif\n-\n ifdef CONFIG_CPU_LITTLE_ENDIAN\n KBUILD_CFLAGS\t+= -mlittle-endian\n KBUILD_LDFLAGS\t+= -EL\n"
  },
  {
    "path": "target/linux/generic/hack-5.15/402-mtd-blktrans-call-add-disks-after-mtd-device.patch",
    "content": "From 0bccc3722bdd88e8ae995e77ef9f7b77ee4cbdee Mon Sep 17 00:00:00 2001\nFrom: Daniel Golle <daniel@makrotopia.org>\nDate: Wed, 7 Apr 2021 22:45:54 +0100\nSubject: [PATCH 2/2] mtd: blktrans: call add disks after mtd device\nTo: linux-mtd@lists.infradead.org\nCc: Vignesh Raghavendra <vigneshr@ti.com>,\n    Richard Weinberger <richard@nod.at>,\n    Miquel Raynal <miquel.raynal@bootlin.com>,\n    David Woodhouse <dwmw2@infradead.org>\n\nCalling device_add_disk while holding mtd_table_mutex leads\nto deadlock in case part_bits!=0 as block partition parsers\nwill try to open the newly created disks, trying to acquire\nmutex once again.\nMove device_add_disk to additional function called after\nadd partitions of an MTD device have been added and locks\nhave been released.\n\nSigned-off-by: Daniel Golle <daniel@makrotopia.org>\n---\n drivers/mtd/mtd_blkdevs.c    | 33 ++++++++++++++++++++++++++-------\n drivers/mtd/mtdcore.c        |  3 +++\n include/linux/mtd/blktrans.h |  1 +\n 3 files changed, 30 insertions(+), 7 deletions(-)\n\n--- a/drivers/mtd/mtd_blkdevs.c\n+++ b/drivers/mtd/mtd_blkdevs.c\n@@ -384,13 +384,6 @@ int add_mtd_blktrans_dev(struct mtd_blkt\n \tif (new->readonly)\n \t\tset_disk_ro(gd, 1);\n \n-\tdevice_add_disk(&new->mtd->dev, gd, NULL);\n-\n-\tif (new->disk_attributes) {\n-\t\tret = sysfs_create_group(&disk_to_dev(gd)->kobj,\n-\t\t\t\t\tnew->disk_attributes);\n-\t\tWARN_ON(ret);\n-\t}\n \treturn 0;\n \n out_free_tag_set:\n@@ -402,6 +395,27 @@ out_list_del:\n \treturn ret;\n }\n \n+void register_mtd_blktrans_devs(void)\n+{\n+\tstruct mtd_blktrans_ops *tr;\n+\tstruct mtd_blktrans_dev *dev, *next;\n+\tint ret;\n+\n+\tlist_for_each_entry(tr, &blktrans_majors, list) {\n+\t\tlist_for_each_entry_safe(dev, next, &tr->devs, list) {\n+\t\t\tif (disk_live(dev->disk))\n+\t\t\t\tcontinue;\n+\n+\t\t\tdevice_add_disk(&dev->mtd->dev, dev->disk, NULL);\n+\t\t\tif (dev->disk_attributes) {\n+\t\t\t\tret = sysfs_create_group(&disk_to_dev(dev->disk)->kobj,\n+\t\t\t\t\t\t\tdev->disk_attributes);\n+\t\t\t\tWARN_ON(ret);\n+\t\t\t}\n+\t\t}\n+\t}\n+}\n+\n int del_mtd_blktrans_dev(struct mtd_blktrans_dev *old)\n {\n \tunsigned long flags;\n--- a/drivers/mtd/mtdcore.c\n+++ b/drivers/mtd/mtdcore.c\n@@ -31,6 +31,7 @@\n \n #include <linux/mtd/mtd.h>\n #include <linux/mtd/partitions.h>\n+#include <linux/mtd/blktrans.h>\n \n #include \"mtdcore.h\"\n \n@@ -1002,6 +1003,8 @@ int mtd_device_parse_register(struct mtd\n \n \tret = mtd_otp_nvmem_add(mtd);\n \n+\tregister_mtd_blktrans_devs();\n+\n out:\n \tif (ret && device_is_registered(&mtd->dev))\n \t\tdel_mtd_device(mtd);\n--- a/include/linux/mtd/blktrans.h\n+++ b/include/linux/mtd/blktrans.h\n@@ -76,6 +76,7 @@ extern int deregister_mtd_blktrans(struc\n extern int add_mtd_blktrans_dev(struct mtd_blktrans_dev *dev);\n extern int del_mtd_blktrans_dev(struct mtd_blktrans_dev *dev);\n extern int mtd_blktrans_cease_background(struct mtd_blktrans_dev *dev);\n+extern void register_mtd_blktrans_devs(void);\n \n /**\n  * module_mtd_blktrans() - Helper macro for registering a mtd blktrans driver\n"
  },
  {
    "path": "target/linux/generic/hack-5.15/410-block-fit-partition-parser.patch",
    "content": "--- a/block/blk.h\n+++ b/block/blk.h\n@@ -354,6 +354,8 @@ void blk_free_ext_minor(unsigned int min\n #define ADDPART_FLAG_NONE\t0\n #define ADDPART_FLAG_RAID\t1\n #define ADDPART_FLAG_WHOLEDISK\t2\n+#define ADDPART_FLAG_READONLY\t4\n+#define ADDPART_FLAG_ROOTDEV\t8\n int bdev_add_partition(struct gendisk *disk, int partno, sector_t start,\n \t\tsector_t length);\n int bdev_del_partition(struct gendisk *disk, int partno);\n--- a/block/partitions/Kconfig\n+++ b/block/partitions/Kconfig\n@@ -101,6 +101,13 @@ config ATARI_PARTITION\n \t  Say Y here if you would like to use hard disks under Linux which\n \t  were partitioned under the Atari OS.\n \n+config FIT_PARTITION\n+\tbool \"Flattened-Image-Tree (FIT) partition support\" if PARTITION_ADVANCED\n+\tdefault n\n+\thelp\n+\t  Say Y here if your system needs to mount the filesystem part of\n+\t  a Flattened-Image-Tree (FIT) image commonly used with Das U-Boot.\n+\n config IBM_PARTITION\n \tbool \"IBM disk label and partition support\"\n \tdepends on PARTITION_ADVANCED && S390\n--- a/block/partitions/Makefile\n+++ b/block/partitions/Makefile\n@@ -8,6 +8,7 @@ obj-$(CONFIG_ACORN_PARTITION) += acorn.o\n obj-$(CONFIG_AMIGA_PARTITION) += amiga.o\n obj-$(CONFIG_ATARI_PARTITION) += atari.o\n obj-$(CONFIG_AIX_PARTITION) += aix.o\n+obj-$(CONFIG_FIT_PARTITION) += fit.o\n obj-$(CONFIG_CMDLINE_PARTITION) += cmdline.o\n obj-$(CONFIG_MAC_PARTITION) += mac.o\n obj-$(CONFIG_LDM_PARTITION) += ldm.o\n--- a/block/partitions/check.h\n+++ b/block/partitions/check.h\n@@ -58,6 +58,7 @@ int amiga_partition(struct parsed_partit\n int atari_partition(struct parsed_partitions *state);\n int cmdline_partition(struct parsed_partitions *state);\n int efi_partition(struct parsed_partitions *state);\n+int fit_partition(struct parsed_partitions *state);\n int ibm_partition(struct parsed_partitions *);\n int karma_partition(struct parsed_partitions *state);\n int ldm_partition(struct parsed_partitions *state);\n@@ -68,3 +69,5 @@ int sgi_partition(struct parsed_partitio\n int sun_partition(struct parsed_partitions *state);\n int sysv68_partition(struct parsed_partitions *state);\n int ultrix_partition(struct parsed_partitions *state);\n+\n+int parse_fit_partitions(struct parsed_partitions *state, u64 start_sector, u64 nr_sectors, int *slot, int add_remain);\n--- a/block/partitions/core.c\n+++ b/block/partitions/core.c\n@@ -12,6 +12,10 @@\n #include <linux/vmalloc.h>\n #include <linux/blktrace_api.h>\n #include <linux/raid/detect.h>\n+#ifdef CONFIG_FIT_PARTITION\n+#include <linux/root_dev.h>\n+#endif\n+\n #include \"check.h\"\n \n static int (*check_part[])(struct parsed_partitions *) = {\n@@ -48,6 +52,9 @@ static int (*check_part[])(struct parsed\n #ifdef CONFIG_EFI_PARTITION\n \tefi_partition,\t\t/* this must come before msdos */\n #endif\n+#ifdef CONFIG_FIT_PARTITION\n+\tfit_partition,\n+#endif\n #ifdef CONFIG_SGI_PARTITION\n \tsgi_partition,\n #endif\n@@ -408,6 +415,11 @@ static struct block_device *add_partitio\n \t\t\tgoto out_del;\n \t}\n \n+#ifdef CONFIG_FIT_PARTITION\n+\tif (flags & ADDPART_FLAG_READONLY)\n+\t\tbdev->bd_read_only = true;\n+#endif\n+\n \t/* everything is up and running, commence */\n \terr = xa_insert(&disk->part_tbl, partno, bdev, GFP_KERNEL);\n \tif (err)\n@@ -598,6 +610,11 @@ static bool blk_add_partition(struct gen\n \t    (state->parts[p].flags & ADDPART_FLAG_RAID))\n \t\tmd_autodetect_dev(part->bd_dev);\n \n+#ifdef CONFIG_FIT_PARTITION\n+\tif ((state->parts[p].flags & ADDPART_FLAG_ROOTDEV) && ROOT_DEV == 0)\n+\t\tROOT_DEV = part->bd_dev;\n+#endif\n+\n \treturn true;\n }\n \n--- a/drivers/mtd/ubi/block.c\n+++ b/drivers/mtd/ubi/block.c\n@@ -428,6 +428,9 @@ int ubiblock_create(struct ubi_volume_in\n \t\tgoto out_cleanup_disk;\n \t}\n \tgd->private_data = dev;\n+#ifdef CONFIG_FIT_PARTITION\n+\tgd->flags |= GENHD_FL_EXT_DEVT;\n+#endif\n \tsprintf(gd->disk_name, \"ubiblock%d_%d\", dev->ubi_num, dev->vol_id);\n \tset_capacity(gd, disk_capacity);\n \tdev->gd = gd;\n--- a/drivers/mtd/mtd_blkdevs.c\n+++ b/drivers/mtd/mtd_blkdevs.c\n@@ -345,6 +345,8 @@ int add_mtd_blktrans_dev(struct mtd_blkt\n \tgd->first_minor = (new->devnum) << tr->part_bits;\n \tgd->minors = 1 << tr->part_bits;\n \tgd->fops = &mtd_block_ops;\n+\tif (IS_ENABLED(CONFIG_FIT_PARTITION) && !mtd_type_is_nand(new->mtd))\n+\t\tgd->flags |= GENHD_FL_EXT_DEVT;\n \n \tif (tr->part_bits)\n \t\tif (new->devnum < 26)\n--- a/block/partitions/efi.c\n+++ b/block/partitions/efi.c\n@@ -716,6 +716,9 @@ int efi_partition(struct parsed_partitio\n \tgpt_entry *ptes = NULL;\n \tu32 i;\n \tunsigned ssz = queue_logical_block_size(state->disk->queue) / 512;\n+#ifdef CONFIG_FIT_PARTITION\n+\tu32 extra_slot = 64;\n+#endif\n \n \tif (!find_valid_gpt(state, &gpt, &ptes) || !gpt || !ptes) {\n \t\tkfree(gpt);\n@@ -749,6 +752,11 @@ int efi_partition(struct parsed_partitio\n \t\t\t\tARRAY_SIZE(ptes[i].partition_name));\n \t\tutf16_le_to_7bit(ptes[i].partition_name, label_max, info->volname);\n \t\tstate->parts[i + 1].has_info = true;\n+#ifdef CONFIG_FIT_PARTITION\n+\t\t/* If this is a U-Boot FIT volume it may have subpartitions */\n+\t\tif (!efi_guidcmp(ptes[i].partition_type_guid, PARTITION_LINUX_FIT_GUID))\n+\t\t\t(void) parse_fit_partitions(state, start * ssz, size * ssz, &extra_slot, 1);\n+#endif\n \t}\n \tkfree(ptes);\n \tkfree(gpt);\n--- a/block/partitions/efi.h\n+++ b/block/partitions/efi.h\n@@ -52,6 +52,9 @@\n #define PARTITION_LINUX_LVM_GUID \\\n     EFI_GUID( 0xe6d6d379, 0xf507, 0x44c2, \\\n               0xa2, 0x3c, 0x23, 0x8f, 0x2a, 0x3d, 0xf9, 0x28)\n+#define PARTITION_LINUX_FIT_GUID \\\n+    EFI_GUID( 0xcae9be83, 0xb15f, 0x49cc, \\\n+              0x86, 0x3f, 0x08, 0x1b, 0x74, 0x4a, 0x2d, 0x93)\n \n typedef struct _gpt_header {\n \t__le64 signature;\n--- a/block/partitions/msdos.c\n+++ b/block/partitions/msdos.c\n@@ -564,6 +564,15 @@ static void parse_minix(struct parsed_pa\n #endif /* CONFIG_MINIX_SUBPARTITION */\n }\n \n+static void parse_fit_mbr(struct parsed_partitions *state,\n+\t\t\t  sector_t offset, sector_t size, int origin)\n+{\n+#ifdef CONFIG_FIT_PARTITION\n+\tu32 extra_slot = 64;\n+\t(void) parse_fit_partitions(state, offset, size, &extra_slot, 1);\n+#endif /* CONFIG_FIT_PARTITION */\n+}\n+\n static struct {\n \tunsigned char id;\n \tvoid (*parse)(struct parsed_partitions *, sector_t, sector_t, int);\n@@ -575,6 +584,7 @@ static struct {\n \t{UNIXWARE_PARTITION, parse_unixware},\n \t{SOLARIS_X86_PARTITION, parse_solaris_x86},\n \t{NEW_SOLARIS_X86_PARTITION, parse_solaris_x86},\n+\t{FIT_PARTITION, parse_fit_mbr},\n \t{0, NULL},\n };\n \n--- a/include/linux/msdos_partition.h\n+++ b/include/linux/msdos_partition.h\n@@ -31,6 +31,7 @@ enum msdos_sys_ind {\n \tLINUX_LVM_PARTITION = 0x8e,\n \tLINUX_RAID_PARTITION = 0xfd,\t/* autodetect RAID partition */\n \n+\tFIT_PARTITION = 0x2e,\t\t/* U-Boot uImage.FIT */\n \tSOLARIS_X86_PARTITION =\t0x82,\t/* also Linux swap partitions */\n \tNEW_SOLARIS_X86_PARTITION = 0xbf,\n \n"
  },
  {
    "path": "target/linux/generic/hack-5.15/420-mtd-set-rootfs-to-be-root-dev.patch",
    "content": "From: Gabor Juhos <juhosg@openwrt.org>\nSubject: kernel/3.1[02]: move MTD root device setup code to mtdcore\n\nThe current code only allows to automatically set\nroot device on MTD partitions. Move the code to MTD\ncore to allow to use it with all MTD devices.\n\nSigned-off-by: Gabor Juhos <juhosg@openwrt.org>\n---\n drivers/mtd/mtdcore.c | 10 ++++++++++\n 1 file changed, 10 insertions(+)\n\n--- a/drivers/mtd/mtdcore.c\n+++ b/drivers/mtd/mtdcore.c\n@@ -27,6 +27,7 @@\n #include <linux/reboot.h>\n #include <linux/leds.h>\n #include <linux/debugfs.h>\n+#include <linux/root_dev.h>\n #include <linux/nvmem-provider.h>\n \n #include <linux/mtd/mtd.h>\n@@ -697,6 +698,16 @@ int add_mtd_device(struct mtd_info *mtd)\n \t   of this try_ nonsense, and no bitching about it\n \t   either. :) */\n \t__module_get(THIS_MODULE);\n+\n+\tif (!strcmp(mtd->name, \"rootfs\") &&\n+\t    IS_ENABLED(CONFIG_MTD_ROOTFS_ROOT_DEV) &&\n+\t    ROOT_DEV == 0) {\n+\t\tunsigned int index = mtd->index;\n+\t\tpr_notice(\"mtd: device %d (%s) set to be root filesystem\\n\",\n+\t\t\t  mtd->index, mtd->name);\n+\t\tROOT_DEV = MKDEV(MTD_BLOCK_MAJOR, index);\n+\t}\n+\n \treturn 0;\n \n fail_nvmem_add:\n"
  },
  {
    "path": "target/linux/generic/hack-5.15/421-drivers-mtd-parsers-add-nvmem-support-to-cmdlinepart.patch",
    "content": "From 6fa9e3678eb002246df1280322b6a024853950a5 Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Mon, 11 Oct 2021 00:53:14 +0200\nSubject: [PATCH] drivers: mtd: parsers: add nvmem support to cmdlinepart\n\nAssuming cmdlinepart is only one level deep partition scheme and that\nstatic partition are also defined in DTS, we can assign an of_node for\npartition declared from bootargs. cmdlinepart have priority than\nfiexed-partition parser so in this specific case the parser doesn't\nassign an of_node. Fix this by searching a defined of_node using a\nsimilar fixed_partition parser and if a partition is found with the same\nlabel, check that it has the same offset and size and return the DT\nof_node to correctly use NVMEM cells.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\n---\n drivers/mtd/parsers/cmdlinepart.c | 71 +++++++++++++++++++++++++++++++\n 1 file changed, 71 insertions(+)\n\n--- a/drivers/mtd/parsers/cmdlinepart.c\n+++ b/drivers/mtd/parsers/cmdlinepart.c\n@@ -43,6 +43,7 @@\n #include <linux/mtd/partitions.h>\n #include <linux/module.h>\n #include <linux/err.h>\n+#include <linux/of.h>\n \n /* debug macro */\n #if 0\n@@ -323,6 +324,68 @@ static int mtdpart_setup_real(char *s)\n \treturn 0;\n }\n \n+static int search_fixed_partition(struct mtd_info *master,\n+\t\t\t\t  struct mtd_partition *target_part,\n+\t\t\t\t  struct mtd_partition *fixed_part)\n+{\n+\tstruct device_node *mtd_node;\n+\tstruct device_node *ofpart_node;\n+\tstruct device_node *pp;\n+\tstruct mtd_partition part;\n+\tconst char *partname;\n+\n+\tmtd_node = mtd_get_of_node(master);\n+\tif (!mtd_node)\n+\t\treturn -EINVAL;\n+\n+\tofpart_node = of_get_child_by_name(mtd_node, \"partitions\");\n+\n+\tfor_each_child_of_node(ofpart_node,  pp) {\n+\t\tconst __be32 *reg;\n+\t\tint len;\n+\t\tint a_cells, s_cells;\n+\n+\t\treg = of_get_property(pp, \"reg\", &len);\n+\t\tif (!reg) {\n+\t\t\tpr_debug(\"%s: ofpart partition %pOF (%pOF) missing reg property.\\n\",\n+\t\t\t\t master->name, pp,\n+\t\t\t\t mtd_node);\n+\t\t\tcontinue;\n+\t\t}\n+\n+\t\ta_cells = of_n_addr_cells(pp);\n+\t\ts_cells = of_n_size_cells(pp);\n+\t\tif (len / 4 != a_cells + s_cells) {\n+\t\t\tpr_debug(\"%s: ofpart partition %pOF (%pOF) error parsing reg property.\\n\",\n+\t\t\t\t master->name, pp,\n+\t\t\t\t mtd_node);\n+\t\t\tcontinue;\n+\t\t}\n+\n+\t\tpart.offset = of_read_number(reg, a_cells);\n+\t\tpart.size = of_read_number(reg + a_cells, s_cells);\n+\t\tpart.of_node = pp;\n+\n+\t\tpartname = of_get_property(pp, \"label\", &len);\n+\t\tif (!partname)\n+\t\t\tpartname = of_get_property(pp, \"name\", &len);\n+\t\tpart.name = partname;\n+\n+\t\tif (!strncmp(target_part->name, part.name, len)) {\n+\t\t\tif (part.offset != target_part->offset)\n+\t\t\t\treturn -EINVAL;\n+\n+\t\t\tif (part.size != target_part->size)\n+\t\t\t\treturn -EINVAL;\n+\n+\t\t\tmemcpy(fixed_part, &part, sizeof(struct mtd_partition));\n+\t\t\treturn 0;\n+\t\t}\n+\t}\n+\n+\treturn -EINVAL;\n+}\n+\n /*\n  * Main function to be called from the MTD mapping driver/device to\n  * obtain the partitioning information. At this point the command line\n@@ -338,6 +401,7 @@ static int parse_cmdline_partitions(stru\n \tint i, err;\n \tstruct cmdline_mtd_partition *part;\n \tconst char *mtd_id = master->name;\n+\tstruct mtd_partition fixed_part;\n \n \t/* parse command line */\n \tif (!cmdline_parsed) {\n@@ -382,6 +446,13 @@ static int parse_cmdline_partitions(stru\n \t\t\t\tsizeof(*part->parts) * (part->num_parts - i));\n \t\t\ti--;\n \t\t}\n+\n+\t\terr = search_fixed_partition(master, &part->parts[i], &fixed_part);\n+\t\tif (!err) {\n+\t\t\tpart->parts[i].of_node = fixed_part.of_node;\n+\t\t\tpr_info(\"Found partition defined in DT for %s. Assigning OF node to support nvmem.\",\n+\t\t\t\tpart->parts[i].name);\n+\t\t}\n \t}\n \n \t*pparts = kmemdup(part->parts, sizeof(*part->parts) * part->num_parts,\n"
  },
  {
    "path": "target/linux/generic/hack-5.15/430-mtk-bmt-support.patch",
    "content": "--- a/drivers/mtd/nand/Kconfig\n+++ b/drivers/mtd/nand/Kconfig\n@@ -46,6 +46,10 @@ config MTD_NAND_ECC_SW_BCH\n \t  ECC codes. They are used with NAND devices requiring more than 1 bit\n \t  of error correction.\n \n+config MTD_NAND_MTK_BMT\n+\tbool \"Support MediaTek NAND Bad-block Management Table\"\n+\tdefault n\n+\n endmenu\n \n endmenu\n--- a/drivers/mtd/nand/Makefile\n+++ b/drivers/mtd/nand/Makefile\n@@ -2,6 +2,7 @@\n \n nandcore-objs := core.o bbt.o\n obj-$(CONFIG_MTD_NAND_CORE) += nandcore.o\n+obj-$(CONFIG_MTD_NAND_MTK_BMT)\t+= mtk_bmt.o mtk_bmt_v2.o mtk_bmt_bbt.o mtk_bmt_nmbm.o\n \n obj-y\t+= onenand/\n obj-y\t+= raw/\n"
  },
  {
    "path": "target/linux/generic/hack-5.15/531-debloat_lzma.patch",
    "content": "From 3fd297761ac246c54d7723c57fca95c112b99465 Mon Sep 17 00:00:00 2001\nFrom: Felix Fietkau <nbd@nbd.name>\nDate: Sat, 15 Jul 2017 21:15:44 +0200\nSubject: lzma: de-bloat the lzma library used by jffs2\n\nlede-commit: 3fd1dd08fbcbb78b34efefd32c3032e5c99108d6\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n include/linux/lzma/LzFind.h  |  17 ---\n include/linux/lzma/LzmaDec.h | 101 ---------------\n include/linux/lzma/LzmaEnc.h |  20 ---\n lib/lzma/LzFind.c            | 287 ++++---------------------------------------\n lib/lzma/LzmaDec.c           |  86 +------------\n lib/lzma/LzmaEnc.c           | 172 ++------------------------\n 6 files changed, 42 insertions(+), 641 deletions(-)\n\n--- a/include/linux/lzma/LzFind.h\n+++ b/include/linux/lzma/LzFind.h\n@@ -55,11 +55,6 @@ typedef struct _CMatchFinder\n \n #define Inline_MatchFinder_GetNumAvailableBytes(p) ((p)->streamPos - (p)->pos)\n \n-int MatchFinder_NeedMove(CMatchFinder *p);\n-Byte *MatchFinder_GetPointerToCurrentPos(CMatchFinder *p);\n-void MatchFinder_MoveBlock(CMatchFinder *p);\n-void MatchFinder_ReadIfRequired(CMatchFinder *p);\n-\n void MatchFinder_Construct(CMatchFinder *p);\n \n /* Conditions:\n@@ -70,12 +65,6 @@ int MatchFinder_Create(CMatchFinder *p,\n     UInt32 keepAddBufferBefore, UInt32 matchMaxLen, UInt32 keepAddBufferAfter,\n     ISzAlloc *alloc);\n void MatchFinder_Free(CMatchFinder *p, ISzAlloc *alloc);\n-void MatchFinder_Normalize3(UInt32 subValue, CLzRef *items, UInt32 numItems);\n-void MatchFinder_ReduceOffsets(CMatchFinder *p, UInt32 subValue);\n-\n-UInt32 * GetMatchesSpec1(UInt32 lenLimit, UInt32 curMatch, UInt32 pos, const Byte *buffer, CLzRef *son,\n-    UInt32 _cyclicBufferPos, UInt32 _cyclicBufferSize, UInt32 _cutValue,\n-    UInt32 *distances, UInt32 maxLen);\n \n /*\n Conditions:\n@@ -102,12 +91,6 @@ typedef struct _IMatchFinder\n \n void MatchFinder_CreateVTable(CMatchFinder *p, IMatchFinder *vTable);\n \n-void MatchFinder_Init(CMatchFinder *p);\n-UInt32 Bt3Zip_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances);\n-UInt32 Hc3Zip_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances);\n-void Bt3Zip_MatchFinder_Skip(CMatchFinder *p, UInt32 num);\n-void Hc3Zip_MatchFinder_Skip(CMatchFinder *p, UInt32 num);\n-\n #ifdef __cplusplus\n }\n #endif\n--- a/include/linux/lzma/LzmaDec.h\n+++ b/include/linux/lzma/LzmaDec.h\n@@ -31,14 +31,6 @@ typedef struct _CLzmaProps\n   UInt32 dicSize;\n } CLzmaProps;\n \n-/* LzmaProps_Decode - decodes properties\n-Returns:\n-  SZ_OK\n-  SZ_ERROR_UNSUPPORTED - Unsupported properties\n-*/\n-\n-SRes LzmaProps_Decode(CLzmaProps *p, const Byte *data, unsigned size);\n-\n \n /* ---------- LZMA Decoder state ---------- */\n \n@@ -70,8 +62,6 @@ typedef struct\n \n #define LzmaDec_Construct(p) { (p)->dic = 0; (p)->probs = 0; }\n \n-void LzmaDec_Init(CLzmaDec *p);\n-\n /* There are two types of LZMA streams:\n      0) Stream with end mark. That end mark adds about 6 bytes to compressed size.\n      1) Stream without end mark. You must know exact uncompressed size to decompress such stream. */\n@@ -108,97 +98,6 @@ typedef enum\n \n /* ELzmaStatus is used only as output value for function call */\n \n-\n-/* ---------- Interfaces ---------- */\n-\n-/* There are 3 levels of interfaces:\n-     1) Dictionary Interface\n-     2) Buffer Interface\n-     3) One Call Interface\n-   You can select any of these interfaces, but don't mix functions from different\n-   groups for same object. */\n-\n-\n-/* There are two variants to allocate state for Dictionary Interface:\n-     1) LzmaDec_Allocate / LzmaDec_Free\n-     2) LzmaDec_AllocateProbs / LzmaDec_FreeProbs\n-   You can use variant 2, if you set dictionary buffer manually.\n-   For Buffer Interface you must always use variant 1.\n-\n-LzmaDec_Allocate* can return:\n-  SZ_OK\n-  SZ_ERROR_MEM         - Memory allocation error\n-  SZ_ERROR_UNSUPPORTED - Unsupported properties\n-*/\n-\n-SRes LzmaDec_AllocateProbs(CLzmaDec *p, const Byte *props, unsigned propsSize, ISzAlloc *alloc);\n-void LzmaDec_FreeProbs(CLzmaDec *p, ISzAlloc *alloc);\n-\n-SRes LzmaDec_Allocate(CLzmaDec *state, const Byte *prop, unsigned propsSize, ISzAlloc *alloc);\n-void LzmaDec_Free(CLzmaDec *state, ISzAlloc *alloc);\n-\n-/* ---------- Dictionary Interface ---------- */\n-\n-/* You can use it, if you want to eliminate the overhead for data copying from\n-   dictionary to some other external buffer.\n-   You must work with CLzmaDec variables directly in this interface.\n-\n-   STEPS:\n-     LzmaDec_Constr()\n-     LzmaDec_Allocate()\n-     for (each new stream)\n-     {\n-       LzmaDec_Init()\n-       while (it needs more decompression)\n-       {\n-         LzmaDec_DecodeToDic()\n-         use data from CLzmaDec::dic and update CLzmaDec::dicPos\n-       }\n-     }\n-     LzmaDec_Free()\n-*/\n-\n-/* LzmaDec_DecodeToDic\n-\n-   The decoding to internal dictionary buffer (CLzmaDec::dic).\n-   You must manually update CLzmaDec::dicPos, if it reaches CLzmaDec::dicBufSize !!!\n-\n-finishMode:\n-  It has meaning only if the decoding reaches output limit (dicLimit).\n-  LZMA_FINISH_ANY - Decode just dicLimit bytes.\n-  LZMA_FINISH_END - Stream must be finished after dicLimit.\n-\n-Returns:\n-  SZ_OK\n-    status:\n-      LZMA_STATUS_FINISHED_WITH_MARK\n-      LZMA_STATUS_NOT_FINISHED\n-      LZMA_STATUS_NEEDS_MORE_INPUT\n-      LZMA_STATUS_MAYBE_FINISHED_WITHOUT_MARK\n-  SZ_ERROR_DATA - Data error\n-*/\n-\n-SRes LzmaDec_DecodeToDic(CLzmaDec *p, SizeT dicLimit,\n-    const Byte *src, SizeT *srcLen, ELzmaFinishMode finishMode, ELzmaStatus *status);\n-\n-\n-/* ---------- Buffer Interface ---------- */\n-\n-/* It's zlib-like interface.\n-   See LzmaDec_DecodeToDic description for information about STEPS and return results,\n-   but you must use LzmaDec_DecodeToBuf instead of LzmaDec_DecodeToDic and you don't need\n-   to work with CLzmaDec variables manually.\n-\n-finishMode:\n-  It has meaning only if the decoding reaches output limit (*destLen).\n-  LZMA_FINISH_ANY - Decode just destLen bytes.\n-  LZMA_FINISH_END - Stream must be finished after (*destLen).\n-*/\n-\n-SRes LzmaDec_DecodeToBuf(CLzmaDec *p, Byte *dest, SizeT *destLen,\n-    const Byte *src, SizeT *srcLen, ELzmaFinishMode finishMode, ELzmaStatus *status);\n-\n-\n /* ---------- One Call Interface ---------- */\n \n /* LzmaDecode\n--- a/include/linux/lzma/LzmaEnc.h\n+++ b/include/linux/lzma/LzmaEnc.h\n@@ -31,9 +31,6 @@ typedef struct _CLzmaEncProps\n } CLzmaEncProps;\n \n void LzmaEncProps_Init(CLzmaEncProps *p);\n-void LzmaEncProps_Normalize(CLzmaEncProps *p);\n-UInt32 LzmaEncProps_GetDictSize(const CLzmaEncProps *props2);\n-\n \n /* ---------- CLzmaEncHandle Interface ---------- */\n \n@@ -53,26 +50,9 @@ CLzmaEncHandle LzmaEnc_Create(ISzAlloc *\n void LzmaEnc_Destroy(CLzmaEncHandle p, ISzAlloc *alloc, ISzAlloc *allocBig);\n SRes LzmaEnc_SetProps(CLzmaEncHandle p, const CLzmaEncProps *props);\n SRes LzmaEnc_WriteProperties(CLzmaEncHandle p, Byte *properties, SizeT *size);\n-SRes LzmaEnc_Encode(CLzmaEncHandle p, ISeqOutStream *outStream, ISeqInStream *inStream,\n-    ICompressProgress *progress, ISzAlloc *alloc, ISzAlloc *allocBig);\n SRes LzmaEnc_MemEncode(CLzmaEncHandle p, Byte *dest, SizeT *destLen, const Byte *src, SizeT srcLen,\n     int writeEndMark, ICompressProgress *progress, ISzAlloc *alloc, ISzAlloc *allocBig);\n \n-/* ---------- One Call Interface ---------- */\n-\n-/* LzmaEncode\n-Return code:\n-  SZ_OK               - OK\n-  SZ_ERROR_MEM        - Memory allocation error\n-  SZ_ERROR_PARAM      - Incorrect paramater\n-  SZ_ERROR_OUTPUT_EOF - output buffer overflow\n-  SZ_ERROR_THREAD     - errors in multithreading functions (only for Mt version)\n-*/\n-\n-SRes LzmaEncode(Byte *dest, SizeT *destLen, const Byte *src, SizeT srcLen,\n-    const CLzmaEncProps *props, Byte *propsEncoded, SizeT *propsSize, int writeEndMark,\n-    ICompressProgress *progress, ISzAlloc *alloc, ISzAlloc *allocBig);\n-\n #ifdef __cplusplus\n }\n #endif\n--- a/lib/lzma/LzFind.c\n+++ b/lib/lzma/LzFind.c\n@@ -14,9 +14,15 @@\n \n #define kStartMaxLen 3\n \n+#if 0\n+#define DIRECT_INPUT\tp->directInput\n+#else\n+#define DIRECT_INPUT\t1\n+#endif\n+\n static void LzInWindow_Free(CMatchFinder *p, ISzAlloc *alloc)\n {\n-  if (!p->directInput)\n+  if (!DIRECT_INPUT)\n   {\n     alloc->Free(alloc, p->bufferBase);\n     p->bufferBase = 0;\n@@ -28,7 +34,7 @@ static void LzInWindow_Free(CMatchFinder\n static int LzInWindow_Create(CMatchFinder *p, UInt32 keepSizeReserv, ISzAlloc *alloc)\n {\n   UInt32 blockSize = p->keepSizeBefore + p->keepSizeAfter + keepSizeReserv;\n-  if (p->directInput)\n+  if (DIRECT_INPUT)\n   {\n     p->blockSize = blockSize;\n     return 1;\n@@ -42,12 +48,12 @@ static int LzInWindow_Create(CMatchFinde\n   return (p->bufferBase != 0);\n }\n \n-Byte *MatchFinder_GetPointerToCurrentPos(CMatchFinder *p) { return p->buffer; }\n-Byte MatchFinder_GetIndexByte(CMatchFinder *p, Int32 index) { return p->buffer[index]; }\n+static Byte *MatchFinder_GetPointerToCurrentPos(CMatchFinder *p) { return p->buffer; }\n+static Byte MatchFinder_GetIndexByte(CMatchFinder *p, Int32 index) { return p->buffer[index]; }\n \n-UInt32 MatchFinder_GetNumAvailableBytes(CMatchFinder *p) { return p->streamPos - p->pos; }\n+static UInt32 MatchFinder_GetNumAvailableBytes(CMatchFinder *p) { return p->streamPos - p->pos; }\n \n-void MatchFinder_ReduceOffsets(CMatchFinder *p, UInt32 subValue)\n+static void MatchFinder_ReduceOffsets(CMatchFinder *p, UInt32 subValue)\n {\n   p->posLimit -= subValue;\n   p->pos -= subValue;\n@@ -58,7 +64,7 @@ static void MatchFinder_ReadBlock(CMatch\n {\n   if (p->streamEndWasReached || p->result != SZ_OK)\n     return;\n-  if (p->directInput)\n+  if (DIRECT_INPUT)\n   {\n     UInt32 curSize = 0xFFFFFFFF - p->streamPos;\n     if (curSize > p->directInputRem)\n@@ -89,7 +95,7 @@ static void MatchFinder_ReadBlock(CMatch\n   }\n }\n \n-void MatchFinder_MoveBlock(CMatchFinder *p)\n+static void MatchFinder_MoveBlock(CMatchFinder *p)\n {\n   memmove(p->bufferBase,\n     p->buffer - p->keepSizeBefore,\n@@ -97,22 +103,14 @@ void MatchFinder_MoveBlock(CMatchFinder\n   p->buffer = p->bufferBase + p->keepSizeBefore;\n }\n \n-int MatchFinder_NeedMove(CMatchFinder *p)\n+static int MatchFinder_NeedMove(CMatchFinder *p)\n {\n-  if (p->directInput)\n+  if (DIRECT_INPUT)\n     return 0;\n   /* if (p->streamEndWasReached) return 0; */\n   return ((size_t)(p->bufferBase + p->blockSize - p->buffer) <= p->keepSizeAfter);\n }\n \n-void MatchFinder_ReadIfRequired(CMatchFinder *p)\n-{\n-  if (p->streamEndWasReached)\n-    return;\n-  if (p->keepSizeAfter >= p->streamPos - p->pos)\n-    MatchFinder_ReadBlock(p);\n-}\n-\n static void MatchFinder_CheckAndMoveAndRead(CMatchFinder *p)\n {\n   if (MatchFinder_NeedMove(p))\n@@ -268,7 +266,7 @@ static void MatchFinder_SetLimits(CMatch\n   p->posLimit = p->pos + limit;\n }\n \n-void MatchFinder_Init(CMatchFinder *p)\n+static void MatchFinder_Init(CMatchFinder *p)\n {\n   UInt32 i;\n   for (i = 0; i < p->hashSizeSum; i++)\n@@ -287,7 +285,7 @@ static UInt32 MatchFinder_GetSubValue(CM\n   return (p->pos - p->historySize - 1) & kNormalizeMask;\n }\n \n-void MatchFinder_Normalize3(UInt32 subValue, CLzRef *items, UInt32 numItems)\n+static void MatchFinder_Normalize3(UInt32 subValue, CLzRef *items, UInt32 numItems)\n {\n   UInt32 i;\n   for (i = 0; i < numItems; i++)\n@@ -319,38 +317,7 @@ static void MatchFinder_CheckLimits(CMat\n   MatchFinder_SetLimits(p);\n }\n \n-static UInt32 * Hc_GetMatchesSpec(UInt32 lenLimit, UInt32 curMatch, UInt32 pos, const Byte *cur, CLzRef *son,\n-    UInt32 _cyclicBufferPos, UInt32 _cyclicBufferSize, UInt32 cutValue,\n-    UInt32 *distances, UInt32 maxLen)\n-{\n-  son[_cyclicBufferPos] = curMatch;\n-  for (;;)\n-  {\n-    UInt32 delta = pos - curMatch;\n-    if (cutValue-- == 0 || delta >= _cyclicBufferSize)\n-      return distances;\n-    {\n-      const Byte *pb = cur - delta;\n-      curMatch = son[_cyclicBufferPos - delta + ((delta > _cyclicBufferPos) ? _cyclicBufferSize : 0)];\n-      if (pb[maxLen] == cur[maxLen] && *pb == *cur)\n-      {\n-        UInt32 len = 0;\n-        while (++len != lenLimit)\n-          if (pb[len] != cur[len])\n-            break;\n-        if (maxLen < len)\n-        {\n-          *distances++ = maxLen = len;\n-          *distances++ = delta - 1;\n-          if (len == lenLimit)\n-            return distances;\n-        }\n-      }\n-    }\n-  }\n-}\n-\n-UInt32 * GetMatchesSpec1(UInt32 lenLimit, UInt32 curMatch, UInt32 pos, const Byte *cur, CLzRef *son,\n+static UInt32 * GetMatchesSpec1(UInt32 lenLimit, UInt32 curMatch, UInt32 pos, const Byte *cur, CLzRef *son,\n     UInt32 _cyclicBufferPos, UInt32 _cyclicBufferSize, UInt32 cutValue,\n     UInt32 *distances, UInt32 maxLen)\n {\n@@ -460,10 +427,10 @@ static void SkipMatchesSpec(UInt32 lenLi\n   p->buffer++; \\\n   if (++p->pos == p->posLimit) MatchFinder_CheckLimits(p);\n \n-#define MOVE_POS_RET MOVE_POS return offset;\n-\n static void MatchFinder_MovePos(CMatchFinder *p) { MOVE_POS; }\n \n+#define MOVE_POS_RET MatchFinder_MovePos(p); return offset;\n+\n #define GET_MATCHES_HEADER2(minLen, ret_op) \\\n   UInt32 lenLimit; UInt32 hashValue; const Byte *cur; UInt32 curMatch; \\\n   lenLimit = p->lenLimit; { if (lenLimit < minLen) { MatchFinder_MovePos(p); ret_op; }} \\\n@@ -479,62 +446,7 @@ static void MatchFinder_MovePos(CMatchFi\n   distances + offset, maxLen) - distances); MOVE_POS_RET;\n \n #define SKIP_FOOTER \\\n-  SkipMatchesSpec(lenLimit, curMatch, MF_PARAMS(p)); MOVE_POS;\n-\n-static UInt32 Bt2_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances)\n-{\n-  UInt32 offset;\n-  GET_MATCHES_HEADER(2)\n-  HASH2_CALC;\n-  curMatch = p->hash[hashValue];\n-  p->hash[hashValue] = p->pos;\n-  offset = 0;\n-  GET_MATCHES_FOOTER(offset, 1)\n-}\n-\n-UInt32 Bt3Zip_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances)\n-{\n-  UInt32 offset;\n-  GET_MATCHES_HEADER(3)\n-  HASH_ZIP_CALC;\n-  curMatch = p->hash[hashValue];\n-  p->hash[hashValue] = p->pos;\n-  offset = 0;\n-  GET_MATCHES_FOOTER(offset, 2)\n-}\n-\n-static UInt32 Bt3_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances)\n-{\n-  UInt32 hash2Value, delta2, maxLen, offset;\n-  GET_MATCHES_HEADER(3)\n-\n-  HASH3_CALC;\n-\n-  delta2 = p->pos - p->hash[hash2Value];\n-  curMatch = p->hash[kFix3HashSize + hashValue];\n-\n-  p->hash[hash2Value] =\n-  p->hash[kFix3HashSize + hashValue] = p->pos;\n-\n-\n-  maxLen = 2;\n-  offset = 0;\n-  if (delta2 < p->cyclicBufferSize && *(cur - delta2) == *cur)\n-  {\n-    for (; maxLen != lenLimit; maxLen++)\n-      if (cur[(ptrdiff_t)maxLen - delta2] != cur[maxLen])\n-        break;\n-    distances[0] = maxLen;\n-    distances[1] = delta2 - 1;\n-    offset = 2;\n-    if (maxLen == lenLimit)\n-    {\n-      SkipMatchesSpec(lenLimit, curMatch, MF_PARAMS(p));\n-      MOVE_POS_RET;\n-    }\n-  }\n-  GET_MATCHES_FOOTER(offset, maxLen)\n-}\n+  SkipMatchesSpec(lenLimit, curMatch, MF_PARAMS(p)); MatchFinder_MovePos(p);\n \n static UInt32 Bt4_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances)\n {\n@@ -583,108 +495,6 @@ static UInt32 Bt4_MatchFinder_GetMatches\n   GET_MATCHES_FOOTER(offset, maxLen)\n }\n \n-static UInt32 Hc4_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances)\n-{\n-  UInt32 hash2Value, hash3Value, delta2, delta3, maxLen, offset;\n-  GET_MATCHES_HEADER(4)\n-\n-  HASH4_CALC;\n-\n-  delta2 = p->pos - p->hash[                hash2Value];\n-  delta3 = p->pos - p->hash[kFix3HashSize + hash3Value];\n-  curMatch = p->hash[kFix4HashSize + hashValue];\n-\n-  p->hash[                hash2Value] =\n-  p->hash[kFix3HashSize + hash3Value] =\n-  p->hash[kFix4HashSize + hashValue] = p->pos;\n-\n-  maxLen = 1;\n-  offset = 0;\n-  if (delta2 < p->cyclicBufferSize && *(cur - delta2) == *cur)\n-  {\n-    distances[0] = maxLen = 2;\n-    distances[1] = delta2 - 1;\n-    offset = 2;\n-  }\n-  if (delta2 != delta3 && delta3 < p->cyclicBufferSize && *(cur - delta3) == *cur)\n-  {\n-    maxLen = 3;\n-    distances[offset + 1] = delta3 - 1;\n-    offset += 2;\n-    delta2 = delta3;\n-  }\n-  if (offset != 0)\n-  {\n-    for (; maxLen != lenLimit; maxLen++)\n-      if (cur[(ptrdiff_t)maxLen - delta2] != cur[maxLen])\n-        break;\n-    distances[offset - 2] = maxLen;\n-    if (maxLen == lenLimit)\n-    {\n-      p->son[p->cyclicBufferPos] = curMatch;\n-      MOVE_POS_RET;\n-    }\n-  }\n-  if (maxLen < 3)\n-    maxLen = 3;\n-  offset = (UInt32)(Hc_GetMatchesSpec(lenLimit, curMatch, MF_PARAMS(p),\n-    distances + offset, maxLen) - (distances));\n-  MOVE_POS_RET\n-}\n-\n-UInt32 Hc3Zip_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances)\n-{\n-  UInt32 offset;\n-  GET_MATCHES_HEADER(3)\n-  HASH_ZIP_CALC;\n-  curMatch = p->hash[hashValue];\n-  p->hash[hashValue] = p->pos;\n-  offset = (UInt32)(Hc_GetMatchesSpec(lenLimit, curMatch, MF_PARAMS(p),\n-    distances, 2) - (distances));\n-  MOVE_POS_RET\n-}\n-\n-static void Bt2_MatchFinder_Skip(CMatchFinder *p, UInt32 num)\n-{\n-  do\n-  {\n-    SKIP_HEADER(2)\n-    HASH2_CALC;\n-    curMatch = p->hash[hashValue];\n-    p->hash[hashValue] = p->pos;\n-    SKIP_FOOTER\n-  }\n-  while (--num != 0);\n-}\n-\n-void Bt3Zip_MatchFinder_Skip(CMatchFinder *p, UInt32 num)\n-{\n-  do\n-  {\n-    SKIP_HEADER(3)\n-    HASH_ZIP_CALC;\n-    curMatch = p->hash[hashValue];\n-    p->hash[hashValue] = p->pos;\n-    SKIP_FOOTER\n-  }\n-  while (--num != 0);\n-}\n-\n-static void Bt3_MatchFinder_Skip(CMatchFinder *p, UInt32 num)\n-{\n-  do\n-  {\n-    UInt32 hash2Value;\n-    SKIP_HEADER(3)\n-    HASH3_CALC;\n-    curMatch = p->hash[kFix3HashSize + hashValue];\n-    p->hash[hash2Value] =\n-    p->hash[kFix3HashSize + hashValue] = p->pos;\n-    SKIP_FOOTER\n-  }\n-  while (--num != 0);\n-}\n-\n static void Bt4_MatchFinder_Skip(CMatchFinder *p, UInt32 num)\n {\n   do\n@@ -701,61 +511,12 @@ static void Bt4_MatchFinder_Skip(CMatchF\n   while (--num != 0);\n }\n \n-static void Hc4_MatchFinder_Skip(CMatchFinder *p, UInt32 num)\n-{\n-  do\n-  {\n-    UInt32 hash2Value, hash3Value;\n-    SKIP_HEADER(4)\n-    HASH4_CALC;\n-    curMatch = p->hash[kFix4HashSize + hashValue];\n-    p->hash[                hash2Value] =\n-    p->hash[kFix3HashSize + hash3Value] =\n-    p->hash[kFix4HashSize + hashValue] = p->pos;\n-    p->son[p->cyclicBufferPos] = curMatch;\n-    MOVE_POS\n-  }\n-  while (--num != 0);\n-}\n-\n-void Hc3Zip_MatchFinder_Skip(CMatchFinder *p, UInt32 num)\n-{\n-  do\n-  {\n-    SKIP_HEADER(3)\n-    HASH_ZIP_CALC;\n-    curMatch = p->hash[hashValue];\n-    p->hash[hashValue] = p->pos;\n-    p->son[p->cyclicBufferPos] = curMatch;\n-    MOVE_POS\n-  }\n-  while (--num != 0);\n-}\n-\n void MatchFinder_CreateVTable(CMatchFinder *p, IMatchFinder *vTable)\n {\n   vTable->Init = (Mf_Init_Func)MatchFinder_Init;\n   vTable->GetIndexByte = (Mf_GetIndexByte_Func)MatchFinder_GetIndexByte;\n   vTable->GetNumAvailableBytes = (Mf_GetNumAvailableBytes_Func)MatchFinder_GetNumAvailableBytes;\n   vTable->GetPointerToCurrentPos = (Mf_GetPointerToCurrentPos_Func)MatchFinder_GetPointerToCurrentPos;\n-  if (!p->btMode)\n-  {\n-    vTable->GetMatches = (Mf_GetMatches_Func)Hc4_MatchFinder_GetMatches;\n-    vTable->Skip = (Mf_Skip_Func)Hc4_MatchFinder_Skip;\n-  }\n-  else if (p->numHashBytes == 2)\n-  {\n-    vTable->GetMatches = (Mf_GetMatches_Func)Bt2_MatchFinder_GetMatches;\n-    vTable->Skip = (Mf_Skip_Func)Bt2_MatchFinder_Skip;\n-  }\n-  else if (p->numHashBytes == 3)\n-  {\n-    vTable->GetMatches = (Mf_GetMatches_Func)Bt3_MatchFinder_GetMatches;\n-    vTable->Skip = (Mf_Skip_Func)Bt3_MatchFinder_Skip;\n-  }\n-  else\n-  {\n-    vTable->GetMatches = (Mf_GetMatches_Func)Bt4_MatchFinder_GetMatches;\n-    vTable->Skip = (Mf_Skip_Func)Bt4_MatchFinder_Skip;\n-  }\n+  vTable->GetMatches = (Mf_GetMatches_Func)Bt4_MatchFinder_GetMatches;\n+  vTable->Skip = (Mf_Skip_Func)Bt4_MatchFinder_Skip;\n }\n--- a/lib/lzma/LzmaDec.c\n+++ b/lib/lzma/LzmaDec.c\n@@ -682,7 +682,7 @@ static void LzmaDec_InitRc(CLzmaDec *p,\n   p->needFlush = 0;\n }\n \n-void LzmaDec_InitDicAndState(CLzmaDec *p, Bool initDic, Bool initState)\n+static void LzmaDec_InitDicAndState(CLzmaDec *p, Bool initDic, Bool initState)\n {\n   p->needFlush = 1;\n   p->remainLen = 0;\n@@ -698,7 +698,7 @@ void LzmaDec_InitDicAndState(CLzmaDec *p\n     p->needInitState = 1;\n }\n \n-void LzmaDec_Init(CLzmaDec *p)\n+static void LzmaDec_Init(CLzmaDec *p)\n {\n   p->dicPos = 0;\n   LzmaDec_InitDicAndState(p, True, True);\n@@ -716,7 +716,7 @@ static void LzmaDec_InitStateReal(CLzmaD\n   p->needInitState = 0;\n }\n \n-SRes LzmaDec_DecodeToDic(CLzmaDec *p, SizeT dicLimit, const Byte *src, SizeT *srcLen,\n+static SRes LzmaDec_DecodeToDic(CLzmaDec *p, SizeT dicLimit, const Byte *src, SizeT *srcLen,\n     ELzmaFinishMode finishMode, ELzmaStatus *status)\n {\n   SizeT inSize = *srcLen;\n@@ -837,65 +837,13 @@ SRes LzmaDec_DecodeToDic(CLzmaDec *p, Si\n   return (p->code == 0) ? SZ_OK : SZ_ERROR_DATA;\n }\n \n-SRes LzmaDec_DecodeToBuf(CLzmaDec *p, Byte *dest, SizeT *destLen, const Byte *src, SizeT *srcLen, ELzmaFinishMode finishMode, ELzmaStatus *status)\n-{\n-  SizeT outSize = *destLen;\n-  SizeT inSize = *srcLen;\n-  *srcLen = *destLen = 0;\n-  for (;;)\n-  {\n-    SizeT inSizeCur = inSize, outSizeCur, dicPos;\n-    ELzmaFinishMode curFinishMode;\n-    SRes res;\n-    if (p->dicPos == p->dicBufSize)\n-      p->dicPos = 0;\n-    dicPos = p->dicPos;\n-    if (outSize > p->dicBufSize - dicPos)\n-    {\n-      outSizeCur = p->dicBufSize;\n-      curFinishMode = LZMA_FINISH_ANY;\n-    }\n-    else\n-    {\n-      outSizeCur = dicPos + outSize;\n-      curFinishMode = finishMode;\n-    }\n-\n-    res = LzmaDec_DecodeToDic(p, outSizeCur, src, &inSizeCur, curFinishMode, status);\n-    src += inSizeCur;\n-    inSize -= inSizeCur;\n-    *srcLen += inSizeCur;\n-    outSizeCur = p->dicPos - dicPos;\n-    memcpy(dest, p->dic + dicPos, outSizeCur);\n-    dest += outSizeCur;\n-    outSize -= outSizeCur;\n-    *destLen += outSizeCur;\n-    if (res != 0)\n-      return res;\n-    if (outSizeCur == 0 || outSize == 0)\n-      return SZ_OK;\n-  }\n-}\n-\n-void LzmaDec_FreeProbs(CLzmaDec *p, ISzAlloc *alloc)\n+static void LzmaDec_FreeProbs(CLzmaDec *p, ISzAlloc *alloc)\n {\n   alloc->Free(alloc, p->probs);\n   p->probs = 0;\n }\n \n-static void LzmaDec_FreeDict(CLzmaDec *p, ISzAlloc *alloc)\n-{\n-  alloc->Free(alloc, p->dic);\n-  p->dic = 0;\n-}\n-\n-void LzmaDec_Free(CLzmaDec *p, ISzAlloc *alloc)\n-{\n-  LzmaDec_FreeProbs(p, alloc);\n-  LzmaDec_FreeDict(p, alloc);\n-}\n-\n-SRes LzmaProps_Decode(CLzmaProps *p, const Byte *data, unsigned size)\n+static SRes LzmaProps_Decode(CLzmaProps *p, const Byte *data, unsigned size)\n {\n   UInt32 dicSize;\n   Byte d;\n@@ -935,7 +883,7 @@ static SRes LzmaDec_AllocateProbs2(CLzma\n   return SZ_OK;\n }\n \n-SRes LzmaDec_AllocateProbs(CLzmaDec *p, const Byte *props, unsigned propsSize, ISzAlloc *alloc)\n+static SRes LzmaDec_AllocateProbs(CLzmaDec *p, const Byte *props, unsigned propsSize, ISzAlloc *alloc)\n {\n   CLzmaProps propNew;\n   RINOK(LzmaProps_Decode(&propNew, props, propsSize));\n@@ -943,28 +891,6 @@ SRes LzmaDec_AllocateProbs(CLzmaDec *p,\n   p->prop = propNew;\n   return SZ_OK;\n }\n-\n-SRes LzmaDec_Allocate(CLzmaDec *p, const Byte *props, unsigned propsSize, ISzAlloc *alloc)\n-{\n-  CLzmaProps propNew;\n-  SizeT dicBufSize;\n-  RINOK(LzmaProps_Decode(&propNew, props, propsSize));\n-  RINOK(LzmaDec_AllocateProbs2(p, &propNew, alloc));\n-  dicBufSize = propNew.dicSize;\n-  if (p->dic == 0 || dicBufSize != p->dicBufSize)\n-  {\n-    LzmaDec_FreeDict(p, alloc);\n-    p->dic = (Byte *)alloc->Alloc(alloc, dicBufSize);\n-    if (p->dic == 0)\n-    {\n-      LzmaDec_FreeProbs(p, alloc);\n-      return SZ_ERROR_MEM;\n-    }\n-  }\n-  p->dicBufSize = dicBufSize;\n-  p->prop = propNew;\n-  return SZ_OK;\n-}\n \n SRes LzmaDecode(Byte *dest, SizeT *destLen, const Byte *src, SizeT *srcLen,\n     const Byte *propData, unsigned propSize, ELzmaFinishMode finishMode,\n--- a/lib/lzma/LzmaEnc.c\n+++ b/lib/lzma/LzmaEnc.c\n@@ -53,7 +53,7 @@ void LzmaEncProps_Init(CLzmaEncProps *p)\n   p->writeEndMark = 0;\n }\n \n-void LzmaEncProps_Normalize(CLzmaEncProps *p)\n+static void LzmaEncProps_Normalize(CLzmaEncProps *p)\n {\n   int level = p->level;\n   if (level < 0) level = 5;\n@@ -76,7 +76,7 @@ void LzmaEncProps_Normalize(CLzmaEncProp\n       #endif\n }\n \n-UInt32 LzmaEncProps_GetDictSize(const CLzmaEncProps *props2)\n+static UInt32 __maybe_unused LzmaEncProps_GetDictSize(const CLzmaEncProps *props2)\n {\n   CLzmaEncProps props = *props2;\n   LzmaEncProps_Normalize(&props);\n@@ -93,7 +93,7 @@ UInt32 LzmaEncProps_GetDictSize(const CL\n \n #define BSR2_RET(pos, res) { unsigned long i; _BitScanReverse(&i, (pos)); res = (i + i) + ((pos >> (i - 1)) & 1); }\n \n-UInt32 GetPosSlot1(UInt32 pos)\n+static UInt32 GetPosSlot1(UInt32 pos)\n {\n   UInt32 res;\n   BSR2_RET(pos, res);\n@@ -107,7 +107,7 @@ UInt32 GetPosSlot1(UInt32 pos)\n #define kNumLogBits (9 + (int)sizeof(size_t) / 2)\n #define kDicLogSizeMaxCompress ((kNumLogBits - 1) * 2 + 7)\n \n-void LzmaEnc_FastPosInit(Byte *g_FastPos)\n+static void LzmaEnc_FastPosInit(Byte *g_FastPos)\n {\n   int c = 2, slotFast;\n   g_FastPos[0] = 0;\n@@ -339,58 +339,6 @@ typedef struct\n   CSaveState saveState;\n } CLzmaEnc;\n \n-void LzmaEnc_SaveState(CLzmaEncHandle pp)\n-{\n-  CLzmaEnc *p = (CLzmaEnc *)pp;\n-  CSaveState *dest = &p->saveState;\n-  int i;\n-  dest->lenEnc = p->lenEnc;\n-  dest->repLenEnc = p->repLenEnc;\n-  dest->state = p->state;\n-\n-  for (i = 0; i < kNumStates; i++)\n-  {\n-    memcpy(dest->isMatch[i], p->isMatch[i], sizeof(p->isMatch[i]));\n-    memcpy(dest->isRep0Long[i], p->isRep0Long[i], sizeof(p->isRep0Long[i]));\n-  }\n-  for (i = 0; i < kNumLenToPosStates; i++)\n-    memcpy(dest->posSlotEncoder[i], p->posSlotEncoder[i], sizeof(p->posSlotEncoder[i]));\n-  memcpy(dest->isRep, p->isRep, sizeof(p->isRep));\n-  memcpy(dest->isRepG0, p->isRepG0, sizeof(p->isRepG0));\n-  memcpy(dest->isRepG1, p->isRepG1, sizeof(p->isRepG1));\n-  memcpy(dest->isRepG2, p->isRepG2, sizeof(p->isRepG2));\n-  memcpy(dest->posEncoders, p->posEncoders, sizeof(p->posEncoders));\n-  memcpy(dest->posAlignEncoder, p->posAlignEncoder, sizeof(p->posAlignEncoder));\n-  memcpy(dest->reps, p->reps, sizeof(p->reps));\n-  memcpy(dest->litProbs, p->litProbs, (0x300 << p->lclp) * sizeof(CLzmaProb));\n-}\n-\n-void LzmaEnc_RestoreState(CLzmaEncHandle pp)\n-{\n-  CLzmaEnc *dest = (CLzmaEnc *)pp;\n-  const CSaveState *p = &dest->saveState;\n-  int i;\n-  dest->lenEnc = p->lenEnc;\n-  dest->repLenEnc = p->repLenEnc;\n-  dest->state = p->state;\n-\n-  for (i = 0; i < kNumStates; i++)\n-  {\n-    memcpy(dest->isMatch[i], p->isMatch[i], sizeof(p->isMatch[i]));\n-    memcpy(dest->isRep0Long[i], p->isRep0Long[i], sizeof(p->isRep0Long[i]));\n-  }\n-  for (i = 0; i < kNumLenToPosStates; i++)\n-    memcpy(dest->posSlotEncoder[i], p->posSlotEncoder[i], sizeof(p->posSlotEncoder[i]));\n-  memcpy(dest->isRep, p->isRep, sizeof(p->isRep));\n-  memcpy(dest->isRepG0, p->isRepG0, sizeof(p->isRepG0));\n-  memcpy(dest->isRepG1, p->isRepG1, sizeof(p->isRepG1));\n-  memcpy(dest->isRepG2, p->isRepG2, sizeof(p->isRepG2));\n-  memcpy(dest->posEncoders, p->posEncoders, sizeof(p->posEncoders));\n-  memcpy(dest->posAlignEncoder, p->posAlignEncoder, sizeof(p->posAlignEncoder));\n-  memcpy(dest->reps, p->reps, sizeof(p->reps));\n-  memcpy(dest->litProbs, p->litProbs, (0x300 << dest->lclp) * sizeof(CLzmaProb));\n-}\n-\n SRes LzmaEnc_SetProps(CLzmaEncHandle pp, const CLzmaEncProps *props2)\n {\n   CLzmaEnc *p = (CLzmaEnc *)pp;\n@@ -600,7 +548,7 @@ static void LitEnc_EncodeMatched(CRangeE\n   while (symbol < 0x10000);\n }\n \n-void LzmaEnc_InitPriceTables(UInt32 *ProbPrices)\n+static void LzmaEnc_InitPriceTables(UInt32 *ProbPrices)\n {\n   UInt32 i;\n   for (i = (1 << kNumMoveReducingBits) / 2; i < kBitModelTotal; i += (1 << kNumMoveReducingBits))\n@@ -1676,7 +1624,7 @@ static void FillDistancesPrices(CLzmaEnc\n   p->matchPriceCount = 0;\n }\n \n-void LzmaEnc_Construct(CLzmaEnc *p)\n+static void LzmaEnc_Construct(CLzmaEnc *p)\n {\n   RangeEnc_Construct(&p->rc);\n   MatchFinder_Construct(&p->matchFinderBase);\n@@ -1709,7 +1657,7 @@ CLzmaEncHandle LzmaEnc_Create(ISzAlloc *\n   return p;\n }\n \n-void LzmaEnc_FreeLits(CLzmaEnc *p, ISzAlloc *alloc)\n+static void LzmaEnc_FreeLits(CLzmaEnc *p, ISzAlloc *alloc)\n {\n   alloc->Free(alloc, p->litProbs);\n   alloc->Free(alloc, p->saveState.litProbs);\n@@ -1717,7 +1665,7 @@ void LzmaEnc_FreeLits(CLzmaEnc *p, ISzAl\n   p->saveState.litProbs = 0;\n }\n \n-void LzmaEnc_Destruct(CLzmaEnc *p, ISzAlloc *alloc, ISzAlloc *allocBig)\n+static void LzmaEnc_Destruct(CLzmaEnc *p, ISzAlloc *alloc, ISzAlloc *allocBig)\n {\n   #ifndef _7ZIP_ST\n   MatchFinderMt_Destruct(&p->matchFinderMt, allocBig);\n@@ -1947,7 +1895,7 @@ static SRes LzmaEnc_Alloc(CLzmaEnc *p, U\n   return SZ_OK;\n }\n \n-void LzmaEnc_Init(CLzmaEnc *p)\n+static void LzmaEnc_Init(CLzmaEnc *p)\n {\n   UInt32 i;\n   p->state = 0;\n@@ -2005,7 +1953,7 @@ void LzmaEnc_Init(CLzmaEnc *p)\n   p->lpMask = (1 << p->lp) - 1;\n }\n \n-void LzmaEnc_InitPrices(CLzmaEnc *p)\n+static void LzmaEnc_InitPrices(CLzmaEnc *p)\n {\n   if (!p->fastMode)\n   {\n@@ -2037,26 +1985,6 @@ static SRes LzmaEnc_AllocAndInit(CLzmaEn\n   return SZ_OK;\n }\n \n-static SRes LzmaEnc_Prepare(CLzmaEncHandle pp, ISeqOutStream *outStream, ISeqInStream *inStream,\n-    ISzAlloc *alloc, ISzAlloc *allocBig)\n-{\n-  CLzmaEnc *p = (CLzmaEnc *)pp;\n-  p->matchFinderBase.stream = inStream;\n-  p->needInit = 1;\n-  p->rc.outStream = outStream;\n-  return LzmaEnc_AllocAndInit(p, 0, alloc, allocBig);\n-}\n-\n-SRes LzmaEnc_PrepareForLzma2(CLzmaEncHandle pp,\n-    ISeqInStream *inStream, UInt32 keepWindowSize,\n-    ISzAlloc *alloc, ISzAlloc *allocBig)\n-{\n-  CLzmaEnc *p = (CLzmaEnc *)pp;\n-  p->matchFinderBase.stream = inStream;\n-  p->needInit = 1;\n-  return LzmaEnc_AllocAndInit(p, keepWindowSize, alloc, allocBig);\n-}\n-\n static void LzmaEnc_SetInputBuf(CLzmaEnc *p, const Byte *src, SizeT srcLen)\n {\n   p->matchFinderBase.directInput = 1;\n@@ -2064,7 +1992,7 @@ static void LzmaEnc_SetInputBuf(CLzmaEnc\n   p->matchFinderBase.directInputRem = srcLen;\n }\n \n-SRes LzmaEnc_MemPrepare(CLzmaEncHandle pp, const Byte *src, SizeT srcLen,\n+static SRes LzmaEnc_MemPrepare(CLzmaEncHandle pp, const Byte *src, SizeT srcLen,\n     UInt32 keepWindowSize, ISzAlloc *alloc, ISzAlloc *allocBig)\n {\n   CLzmaEnc *p = (CLzmaEnc *)pp;\n@@ -2074,7 +2002,7 @@ SRes LzmaEnc_MemPrepare(CLzmaEncHandle p\n   return LzmaEnc_AllocAndInit(p, keepWindowSize, alloc, allocBig);\n }\n \n-void LzmaEnc_Finish(CLzmaEncHandle pp)\n+static void LzmaEnc_Finish(CLzmaEncHandle pp)\n {\n   #ifndef _7ZIP_ST\n   CLzmaEnc *p = (CLzmaEnc *)pp;\n@@ -2107,53 +2035,6 @@ static size_t MyWrite(void *pp, const vo\n   return size;\n }\n \n-\n-UInt32 LzmaEnc_GetNumAvailableBytes(CLzmaEncHandle pp)\n-{\n-  const CLzmaEnc *p = (CLzmaEnc *)pp;\n-  return p->matchFinder.GetNumAvailableBytes(p->matchFinderObj);\n-}\n-\n-const Byte *LzmaEnc_GetCurBuf(CLzmaEncHandle pp)\n-{\n-  const CLzmaEnc *p = (CLzmaEnc *)pp;\n-  return p->matchFinder.GetPointerToCurrentPos(p->matchFinderObj) - p->additionalOffset;\n-}\n-\n-SRes LzmaEnc_CodeOneMemBlock(CLzmaEncHandle pp, Bool reInit,\n-    Byte *dest, size_t *destLen, UInt32 desiredPackSize, UInt32 *unpackSize)\n-{\n-  CLzmaEnc *p = (CLzmaEnc *)pp;\n-  UInt64 nowPos64;\n-  SRes res;\n-  CSeqOutStreamBuf outStream;\n-\n-  outStream.funcTable.Write = MyWrite;\n-  outStream.data = dest;\n-  outStream.rem = *destLen;\n-  outStream.overflow = False;\n-\n-  p->writeEndMark = False;\n-  p->finished = False;\n-  p->result = SZ_OK;\n-\n-  if (reInit)\n-    LzmaEnc_Init(p);\n-  LzmaEnc_InitPrices(p);\n-  nowPos64 = p->nowPos64;\n-  RangeEnc_Init(&p->rc);\n-  p->rc.outStream = &outStream.funcTable;\n-\n-  res = LzmaEnc_CodeOneBlock(p, True, desiredPackSize, *unpackSize);\n-\n-  *unpackSize = (UInt32)(p->nowPos64 - nowPos64);\n-  *destLen -= outStream.rem;\n-  if (outStream.overflow)\n-    return SZ_ERROR_OUTPUT_EOF;\n-\n-  return res;\n-}\n-\n static SRes LzmaEnc_Encode2(CLzmaEnc *p, ICompressProgress *progress)\n {\n   SRes res = SZ_OK;\n@@ -2184,13 +2065,6 @@ static SRes LzmaEnc_Encode2(CLzmaEnc *p,\n   return res;\n }\n \n-SRes LzmaEnc_Encode(CLzmaEncHandle pp, ISeqOutStream *outStream, ISeqInStream *inStream, ICompressProgress *progress,\n-    ISzAlloc *alloc, ISzAlloc *allocBig)\n-{\n-  RINOK(LzmaEnc_Prepare(pp, outStream, inStream, alloc, allocBig));\n-  return LzmaEnc_Encode2((CLzmaEnc *)pp, progress);\n-}\n-\n SRes LzmaEnc_WriteProperties(CLzmaEncHandle pp, Byte *props, SizeT *size)\n {\n   CLzmaEnc *p = (CLzmaEnc *)pp;\n@@ -2247,25 +2121,3 @@ SRes LzmaEnc_MemEncode(CLzmaEncHandle pp\n     return SZ_ERROR_OUTPUT_EOF;\n   return res;\n }\n-\n-SRes LzmaEncode(Byte *dest, SizeT *destLen, const Byte *src, SizeT srcLen,\n-    const CLzmaEncProps *props, Byte *propsEncoded, SizeT *propsSize, int writeEndMark,\n-    ICompressProgress *progress, ISzAlloc *alloc, ISzAlloc *allocBig)\n-{\n-  CLzmaEnc *p = (CLzmaEnc *)LzmaEnc_Create(alloc);\n-  SRes res;\n-  if (p == 0)\n-    return SZ_ERROR_MEM;\n-\n-  res = LzmaEnc_SetProps(p, props);\n-  if (res == SZ_OK)\n-  {\n-    res = LzmaEnc_WriteProperties(p, propsEncoded, propsSize);\n-    if (res == SZ_OK)\n-      res = LzmaEnc_MemEncode(p, dest, destLen, src, srcLen,\n-          writeEndMark, progress, alloc, allocBig);\n-  }\n-\n-  LzmaEnc_Destroy(p, alloc, allocBig);\n-  return res;\n-}\n"
  },
  {
    "path": "target/linux/generic/hack-5.15/600-bridge_offload.patch",
    "content": "--- a/include/linux/if_bridge.h\n+++ b/include/linux/if_bridge.h\n@@ -59,6 +59,7 @@ struct br_ip_list {\n #define BR_MRP_LOST_IN_CONT\tBIT(19)\n #define BR_TX_FWD_OFFLOAD\tBIT(20)\n #define BR_BPDU_FILTER\t\tBIT(21)\n+#define BR_OFFLOAD\t\tBIT(22)\n \n #define BR_DEFAULT_AGEING_TIME\t(300 * HZ)\n \n--- a/net/bridge/Makefile\n+++ b/net/bridge/Makefile\n@@ -5,7 +5,7 @@\n \n obj-$(CONFIG_BRIDGE) += bridge.o\n \n-bridge-y\t:= br.o br_device.o br_fdb.o br_forward.o br_if.o br_input.o \\\n+bridge-y\t:= br.o br_device.o br_fdb.o br_forward.o br_if.o br_input.o br_offload.o \\\n \t\t\tbr_ioctl.o br_stp.o br_stp_bpdu.o \\\n \t\t\tbr_stp_if.o br_stp_timer.o br_netlink.o \\\n \t\t\tbr_netlink_tunnel.o br_arp_nd_proxy.o\n--- a/net/bridge/br.c\n+++ b/net/bridge/br.c\n@@ -18,6 +18,7 @@\n #include <net/switchdev.h>\n \n #include \"br_private.h\"\n+#include \"br_private_offload.h\"\n \n /*\n  * Handle changes in state of network devices enslaved to a bridge.\n@@ -381,6 +382,10 @@ static int __init br_init(void)\n \tif (err)\n \t\tgoto err_out;\n \n+\terr = br_offload_init();\n+\tif (err)\n+\t\tgoto err_out0;\n+\n \terr = register_pernet_subsys(&br_net_ops);\n \tif (err)\n \t\tgoto err_out1;\n@@ -430,6 +435,8 @@ err_out3:\n err_out2:\n \tunregister_pernet_subsys(&br_net_ops);\n err_out1:\n+\tbr_offload_fini();\n+err_out0:\n \tbr_fdb_fini();\n err_out:\n \tstp_proto_unregister(&br_stp_proto);\n@@ -452,6 +459,7 @@ static void __exit br_deinit(void)\n #if IS_ENABLED(CONFIG_ATM_LANE)\n \tbr_fdb_test_addr_hook = NULL;\n #endif\n+\tbr_offload_fini();\n \tbr_fdb_fini();\n }\n \n--- a/net/bridge/br_device.c\n+++ b/net/bridge/br_device.c\n@@ -524,6 +524,8 @@ void br_dev_setup(struct net_device *dev\n \tbr->bridge_hello_time = br->hello_time = 2 * HZ;\n \tbr->bridge_forward_delay = br->forward_delay = 15 * HZ;\n \tbr->bridge_ageing_time = br->ageing_time = BR_DEFAULT_AGEING_TIME;\n+\tbr->offload_cache_size = 128;\n+\tbr->offload_cache_reserved = 8;\n \tdev->max_mtu = ETH_MAX_MTU;\n \n \tbr_netfilter_rtable_init(br);\n--- a/net/bridge/br_fdb.c\n+++ b/net/bridge/br_fdb.c\n@@ -23,6 +23,7 @@\n #include <net/switchdev.h>\n #include <trace/events/bridge.h>\n #include \"br_private.h\"\n+#include \"br_private_offload.h\"\n \n static const struct rhashtable_params br_fdb_rht_params = {\n \t.head_offset = offsetof(struct net_bridge_fdb_entry, rhnode),\n@@ -518,6 +519,8 @@ static struct net_bridge_fdb_entry *fdb_\n \t\tfdb->key.vlan_id = vid;\n \t\tfdb->flags = flags;\n \t\tfdb->updated = fdb->used = jiffies;\n+\t\tINIT_HLIST_HEAD(&fdb->offload_in);\n+\t\tINIT_HLIST_HEAD(&fdb->offload_out);\n \t\tif (rhashtable_lookup_insert_fast(&br->fdb_hash_tbl,\n \t\t\t\t\t\t  &fdb->rhnode,\n \t\t\t\t\t\t  br_fdb_rht_params)) {\n@@ -794,6 +797,8 @@ static void fdb_notify(struct net_bridge\n \tstruct sk_buff *skb;\n \tint err = -ENOBUFS;\n \n+\tbr_offload_fdb_update(fdb);\n+\n \tif (swdev_notify)\n \t\tbr_switchdev_fdb_notify(br, fdb, type);\n \n--- a/net/bridge/br_forward.c\n+++ b/net/bridge/br_forward.c\n@@ -16,6 +16,7 @@\n #include <linux/if_vlan.h>\n #include <linux/netfilter_bridge.h>\n #include \"br_private.h\"\n+#include \"br_private_offload.h\"\n \n /* Don't forward packets to originating port or forwarding disabled */\n static inline int should_deliver(const struct net_bridge_port *p,\n@@ -32,6 +33,8 @@ static inline int should_deliver(const s\n \n int br_dev_queue_push_xmit(struct net *net, struct sock *sk, struct sk_buff *skb)\n {\n+\tbr_offload_output(skb);\n+\n \tskb_push(skb, ETH_HLEN);\n \tif (!is_skb_forwardable(skb->dev, skb))\n \t\tgoto drop;\n--- a/net/bridge/br_if.c\n+++ b/net/bridge/br_if.c\n@@ -25,6 +25,7 @@\n #include <net/net_namespace.h>\n \n #include \"br_private.h\"\n+#include \"br_private_offload.h\"\n \n /*\n  * Determine initial path cost based on speed.\n@@ -428,7 +429,7 @@ static struct net_bridge_port *new_nbp(s\n \tp->path_cost = port_cost(dev);\n \tp->priority = 0x8000 >> BR_PORT_BITS;\n \tp->port_no = index;\n-\tp->flags = BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD | BR_BCAST_FLOOD;\n+\tp->flags = BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD | BR_BCAST_FLOOD | BR_OFFLOAD;\n \tbr_init_port(p);\n \tbr_set_state(p, BR_STATE_DISABLED);\n \tbr_stp_port_timer_init(p);\n@@ -771,6 +772,9 @@ void br_port_flags_change(struct net_bri\n \n \tif (mask & BR_NEIGH_SUPPRESS)\n \t\tbr_recalculate_neigh_suppress_enabled(br);\n+\n+\tif (mask & BR_OFFLOAD)\n+\t\tbr_offload_port_state(p);\n }\n \n bool br_port_flag_is_set(const struct net_device *dev, unsigned long flag)\n--- a/net/bridge/br_input.c\n+++ b/net/bridge/br_input.c\n@@ -22,6 +22,7 @@\n #include <linux/rculist.h>\n #include \"br_private.h\"\n #include \"br_private_tunnel.h\"\n+#include \"br_private_offload.h\"\n \n static int\n br_netif_receive_skb(struct net *net, struct sock *sk, struct sk_buff *skb)\n@@ -164,6 +165,7 @@ int br_handle_frame_finish(struct net *n\n \t\t\tdst->used = now;\n \t\tbr_forward(dst->dst, skb, local_rcv, false);\n \t} else {\n+\t\tbr_offload_skb_disable(skb);\n \t\tif (!mcast_hit)\n \t\t\tbr_flood(br, skb, pkt_type, local_rcv, false);\n \t\telse\n@@ -297,6 +299,9 @@ static rx_handler_result_t br_handle_fra\n \tmemset(skb->cb, 0, sizeof(struct br_input_skb_cb));\n \n \tp = br_port_get_rcu(skb->dev);\n+\tif (br_offload_input(p, skb))\n+\t\treturn RX_HANDLER_CONSUMED;\n+\n \tif (p->flags & BR_VLAN_TUNNEL)\n \t\tbr_handle_ingress_vlan_tunnel(skb, p, nbp_vlan_group_rcu(p));\n \n--- /dev/null\n+++ b/net/bridge/br_offload.c\n@@ -0,0 +1,438 @@\n+// SPDX-License-Identifier: GPL-2.0-only\n+#include <linux/kernel.h>\n+#include <linux/workqueue.h>\n+#include \"br_private.h\"\n+#include \"br_private_offload.h\"\n+\n+static DEFINE_SPINLOCK(offload_lock);\n+\n+struct bridge_flow_key {\n+\tu8 dest[ETH_ALEN];\n+\tu8 src[ETH_ALEN];\n+#ifdef CONFIG_BRIDGE_VLAN_FILTERING\n+\tu16 vlan_tag;\n+\tbool vlan_present;\n+#endif\n+};\n+\n+struct bridge_flow {\n+\tstruct net_bridge_port *port;\n+\tstruct rhash_head node;\n+\tstruct bridge_flow_key key;\n+#ifdef CONFIG_BRIDGE_VLAN_FILTERING\n+\tbool vlan_out_present;\n+\tu16 vlan_out;\n+#endif\n+\n+\tunsigned long used;\n+\tstruct net_bridge_fdb_entry *fdb_in, *fdb_out;\n+\tstruct hlist_node fdb_list_in, fdb_list_out;\n+\n+\tstruct rcu_head rcu;\n+};\n+\n+static const struct rhashtable_params flow_params = {\n+\t.automatic_shrinking = true,\n+\t.head_offset = offsetof(struct bridge_flow, node),\n+\t.key_len = sizeof(struct bridge_flow_key),\n+\t.key_offset = offsetof(struct bridge_flow, key),\n+};\n+\n+static struct kmem_cache *offload_cache __read_mostly;\n+\n+static void\n+flow_rcu_free(struct rcu_head *head)\n+{\n+\tstruct bridge_flow *flow;\n+\n+\tflow = container_of(head, struct bridge_flow, rcu);\n+\tkmem_cache_free(offload_cache, flow);\n+}\n+\n+static void\n+__br_offload_flow_free(struct bridge_flow *flow)\n+{\n+\tflow->used = 0;\n+\thlist_del(&flow->fdb_list_in);\n+\thlist_del(&flow->fdb_list_out);\n+\n+\tcall_rcu(&flow->rcu, flow_rcu_free);\n+}\n+\n+static void\n+br_offload_flow_free(struct bridge_flow *flow)\n+{\n+\tif (rhashtable_remove_fast(&flow->port->offload.rht, &flow->node,\n+\t\t\t\t   flow_params) != 0)\n+\t\treturn;\n+\n+\t__br_offload_flow_free(flow);\n+}\n+\n+static bool\n+br_offload_flow_fdb_refresh_time(struct bridge_flow *flow,\n+\t\t\t\t struct net_bridge_fdb_entry *fdb)\n+{\n+\tif (!time_after(flow->used, fdb->updated))\n+\t\treturn false;\n+\n+\tfdb->updated = flow->used;\n+\n+\treturn true;\n+}\n+\n+\n+static void\n+br_offload_flow_refresh_time(struct bridge_flow *flow)\n+{\n+\tbr_offload_flow_fdb_refresh_time(flow, flow->fdb_in);\n+\tbr_offload_flow_fdb_refresh_time(flow, flow->fdb_out);\n+}\n+\n+static void\n+br_offload_destroy_cb(void *ptr, void *arg)\n+{\n+\tstruct bridge_flow *flow = ptr;\n+\n+\t__br_offload_flow_free(flow);\n+}\n+\n+static bool\n+br_offload_need_gc(struct net_bridge_port *p)\n+{\n+\treturn (atomic_read(&p->offload.rht.nelems) +\n+\t        p->br->offload_cache_reserved) >= p->br->offload_cache_size;\n+}\n+\n+static void\n+br_offload_gc_work(struct work_struct *work)\n+{\n+\tstruct rhashtable_iter hti;\n+\tstruct net_bridge_port *p;\n+\tstruct bridge_flow *gc_flow = NULL;\n+\tstruct bridge_flow *flow;\n+\tunsigned long gc_used;\n+\n+\tp = container_of(work, struct net_bridge_port, offload.gc_work);\n+\n+\tif (!br_offload_need_gc(p))\n+\t\treturn;\n+\n+\trhashtable_walk_enter(&p->offload.rht, &hti);\n+\trhashtable_walk_start(&hti);\n+\twhile ((flow = rhashtable_walk_next(&hti)) != NULL) {\n+\t\tunsigned long used;\n+\n+\t\tif (IS_ERR(flow))\n+\t\t\tcontinue;\n+\n+\t\tused = READ_ONCE(flow->used);\n+\t\tif (!used)\n+\t\t\tcontinue;\n+\n+\t\tif (gc_flow && !time_before(used, gc_used))\n+\t\t\tcontinue;\n+\n+\t\tgc_flow = flow;\n+\t\tgc_used = used;\n+\t}\n+\trhashtable_walk_stop(&hti);\n+\trhashtable_walk_exit(&hti);\n+\n+\tif (!gc_flow)\n+\t\treturn;\n+\n+\tspin_lock_bh(&offload_lock);\n+\tif (br_offload_need_gc(p) && gc_flow &&\n+\t    gc_flow->used == gc_used)\n+\t\tbr_offload_flow_free(gc_flow);\n+\tif (p->offload.enabled && br_offload_need_gc(p))\n+\t\tqueue_work(system_long_wq, work);\n+\tspin_unlock_bh(&offload_lock);\n+\n+}\n+\n+void br_offload_port_state(struct net_bridge_port *p)\n+{\n+\tstruct net_bridge_port_offload *o = &p->offload;\n+\tbool enabled = true;\n+\tbool flush = false;\n+\n+\tif (p->state != BR_STATE_FORWARDING ||\n+\t    !(p->flags & BR_OFFLOAD))\n+\t\tenabled = false;\n+\n+\tspin_lock_bh(&offload_lock);\n+\tif (o->enabled == enabled)\n+\t\tgoto out;\n+\n+\tif (enabled) {\n+\t\tif (!o->gc_work.func)\n+\t\t\tINIT_WORK(&o->gc_work, br_offload_gc_work);\n+\t\trhashtable_init(&o->rht, &flow_params);\n+\t} else {\n+\t\tflush = true;\n+\t\trhashtable_free_and_destroy(&o->rht, br_offload_destroy_cb, o);\n+\t}\n+\n+\to->enabled = enabled;\n+\n+out:\n+\tspin_unlock_bh(&offload_lock);\n+\n+\tif (flush)\n+\t\tflush_work(&o->gc_work);\n+}\n+\n+void br_offload_fdb_update(const struct net_bridge_fdb_entry *fdb)\n+{\n+\tstruct bridge_flow *f;\n+\tstruct hlist_node *tmp;\n+\n+\tspin_lock_bh(&offload_lock);\n+\n+\thlist_for_each_entry_safe(f, tmp, &fdb->offload_in, fdb_list_in)\n+\t\tbr_offload_flow_free(f);\n+\n+\thlist_for_each_entry_safe(f, tmp, &fdb->offload_out, fdb_list_out)\n+\t\tbr_offload_flow_free(f);\n+\n+\tspin_unlock_bh(&offload_lock);\n+}\n+\n+static void\n+br_offload_prepare_key(struct net_bridge_port *p, struct bridge_flow_key *key,\n+\t\t       struct sk_buff *skb)\n+{\n+\tmemset(key, 0, sizeof(*key));\n+\tmemcpy(key, eth_hdr(skb), 2 * ETH_ALEN);\n+#ifdef CONFIG_BRIDGE_VLAN_FILTERING\n+\tif (!br_opt_get(p->br, BROPT_VLAN_ENABLED))\n+\t\treturn;\n+\n+\tif (!skb_vlan_tag_present(skb) || skb->vlan_proto != p->br->vlan_proto)\n+\t\treturn;\n+\n+\tkey->vlan_present = true;\n+\tkey->vlan_tag = skb_vlan_tag_get_id(skb);\n+#endif\n+}\n+\n+void br_offload_output(struct sk_buff *skb)\n+{\n+\tstruct net_bridge_port_offload *o;\n+\tstruct br_input_skb_cb *cb = (struct br_input_skb_cb *)skb->cb;\n+\tstruct net_bridge_port *p, *inp;\n+\tstruct net_device *dev;\n+\tstruct net_bridge_fdb_entry *fdb_in, *fdb_out;\n+\tstruct net_bridge_vlan_group *vg;\n+\tstruct bridge_flow_key key;\n+\tstruct bridge_flow *flow;\n+\tu16 vlan;\n+\n+\tif (!cb->offload)\n+\t\treturn;\n+\n+\trcu_read_lock();\n+\n+\tp = br_port_get_rcu(skb->dev);\n+\tif (!p)\n+\t\tgoto out;\n+\n+\to = &p->offload;\n+\tif (!o->enabled)\n+\t\tgoto out;\n+\n+\tif (atomic_read(&p->offload.rht.nelems) >= p->br->offload_cache_size)\n+\t\tgoto out;\n+\n+\tdev = dev_get_by_index_rcu(dev_net(p->br->dev), cb->input_ifindex);\n+\tif (!dev)\n+\t\tgoto out;\n+\n+\tinp = br_port_get_rcu(dev);\n+\tif (!inp)\n+\t\tgoto out;\n+\n+\tvg = nbp_vlan_group_rcu(inp);\n+\tvlan = cb->input_vlan_present ? cb->input_vlan_tag : br_get_pvid(vg);\n+\tfdb_in = br_fdb_find_rcu(p->br, eth_hdr(skb)->h_source, vlan);\n+\tif (!fdb_in)\n+\t\tgoto out;\n+\n+\tvg = nbp_vlan_group_rcu(p);\n+\tvlan = skb_vlan_tag_present(skb) ? skb_vlan_tag_get_id(skb) : br_get_pvid(vg);\n+\tfdb_out = br_fdb_find_rcu(p->br, eth_hdr(skb)->h_dest, vlan);\n+\tif (!fdb_out)\n+\t\tgoto out;\n+\n+\tbr_offload_prepare_key(p, &key, skb);\n+#ifdef CONFIG_BRIDGE_VLAN_FILTERING\n+\tkey.vlan_present = cb->input_vlan_present;\n+\tkey.vlan_tag = cb->input_vlan_tag;\n+#endif\n+\n+\tflow = kmem_cache_alloc(offload_cache, GFP_ATOMIC);\n+\tflow->port = fdb_in->dst;\n+\tmemcpy(&flow->key, &key, sizeof(key));\n+\n+#ifdef CONFIG_BRIDGE_VLAN_FILTERING\n+\tflow->vlan_out_present = skb_vlan_tag_present(skb);\n+\tflow->vlan_out = skb_vlan_tag_get(skb);\n+#endif\n+\n+\tflow->fdb_in = fdb_in;\n+\tflow->fdb_out = fdb_out;\n+\tflow->used = jiffies;\n+\n+\tspin_lock_bh(&offload_lock);\n+\tif (!o->enabled ||\n+\t    atomic_read(&p->offload.rht.nelems) >= p->br->offload_cache_size ||\n+\t    rhashtable_insert_fast(&flow->port->offload.rht, &flow->node, flow_params)) {\n+\t\tkmem_cache_free(offload_cache, flow);\n+\t\tgoto out_unlock;\n+\t}\n+\n+\thlist_add_head(&flow->fdb_list_in, &fdb_in->offload_in);\n+\thlist_add_head(&flow->fdb_list_out, &fdb_out->offload_out);\n+\n+\tif (br_offload_need_gc(p))\n+\t\tqueue_work(system_long_wq, &p->offload.gc_work);\n+\n+out_unlock:\n+\tspin_unlock_bh(&offload_lock);\n+\n+out:\n+\trcu_read_unlock();\n+}\n+\n+bool br_offload_input(struct net_bridge_port *p, struct sk_buff *skb)\n+{\n+\tstruct net_bridge_port_offload *o = &p->offload;\n+\tstruct br_input_skb_cb *cb = (struct br_input_skb_cb *)skb->cb;\n+\tstruct bridge_flow_key key;\n+\tstruct net_bridge_port *dst;\n+\tstruct bridge_flow *flow;\n+\tunsigned long now = jiffies;\n+\tbool ret = false;\n+\n+\tif (skb->len < sizeof(key))\n+\t\treturn false;\n+\n+\tif (!o->enabled)\n+\t\treturn false;\n+\n+\tif (is_multicast_ether_addr(eth_hdr(skb)->h_dest))\n+\t\treturn false;\n+\n+\tbr_offload_prepare_key(p, &key, skb);\n+\n+\trcu_read_lock();\n+\tflow = rhashtable_lookup(&o->rht, &key, flow_params);\n+\tif (!flow) {\n+\t\tcb->offload = 1;\n+#ifdef CONFIG_BRIDGE_VLAN_FILTERING\n+\t\tcb->input_vlan_present = key.vlan_present != 0;\n+\t\tcb->input_vlan_tag = key.vlan_tag;\n+\t\tcb->input_ifindex = p->dev->ifindex;\n+#endif\n+\t\tgoto out;\n+\t}\n+\n+\tif (flow->fdb_in->dst != p)\n+\t\tgoto out;\n+\n+\tdst = flow->fdb_out->dst;\n+\tif (!dst)\n+\t\tgoto out;\n+\n+\tret = true;\n+#ifdef CONFIG_BRIDGE_VLAN_FILTERING\n+\tif (!flow->vlan_out_present && key.vlan_present) {\n+\t\t__vlan_hwaccel_clear_tag(skb);\n+\t} else if (flow->vlan_out_present) {\n+\t\tif (skb_vlan_tag_present(skb) &&\n+\t\t    skb->vlan_proto != p->br->vlan_proto) {\n+\t\t\t/* Protocol-mismatch, empty out vlan_tci for new tag */\n+\t\t\tskb_push(skb, ETH_HLEN);\n+\t\t\tskb = vlan_insert_tag_set_proto(skb, skb->vlan_proto,\n+\t\t\t\t\t\t\tskb_vlan_tag_get(skb));\n+\t\t\tif (unlikely(!skb))\n+\t\t\t\tgoto out;\n+\n+\t\t\tskb_pull(skb, ETH_HLEN);\n+\t\t\tskb_reset_mac_len(skb);\n+\t\t}\n+\n+\t\t__vlan_hwaccel_put_tag(skb, p->br->vlan_proto,\n+\t\t\t\t       flow->vlan_out);\n+\t}\n+#endif\n+\n+\tskb->dev = dst->dev;\n+\tskb_push(skb, ETH_HLEN);\n+\n+\tif (skb_warn_if_lro(skb) || !is_skb_forwardable(skb->dev, skb)) {\n+\t\tkfree_skb(skb);\n+\t\tgoto out;\n+\t}\n+\n+\tif (now - flow->used >= HZ) {\n+\t\tflow->used = now;\n+\t\tbr_offload_flow_refresh_time(flow);\n+\t}\n+\n+\tskb_forward_csum(skb);\n+\tdev_queue_xmit(skb);\n+\n+out:\n+\trcu_read_unlock();\n+\treturn ret;\n+}\n+\n+static void\n+br_offload_check_gc(struct net_bridge *br)\n+{\n+\tstruct net_bridge_port *p;\n+\n+\tspin_lock_bh(&br->lock);\n+\tlist_for_each_entry(p, &br->port_list, list)\n+\t\tif (br_offload_need_gc(p))\n+\t\t\tqueue_work(system_long_wq, &p->offload.gc_work);\n+\tspin_unlock_bh(&br->lock);\n+}\n+\n+\n+int br_offload_set_cache_size(struct net_bridge *br, unsigned long val,\n+\t\t\t       struct netlink_ext_ack *extack)\n+{\n+\tbr->offload_cache_size = val;\n+\tbr_offload_check_gc(br);\n+\n+\treturn 0;\n+}\n+\n+int br_offload_set_cache_reserved(struct net_bridge *br, unsigned long val,\n+\t\t\t\t   struct netlink_ext_ack *extack)\n+{\n+\tbr->offload_cache_reserved = val;\n+\tbr_offload_check_gc(br);\n+\n+\treturn 0;\n+}\n+\n+int __init br_offload_init(void)\n+{\n+\toffload_cache = kmem_cache_create(\"bridge_offload_cache\",\n+\t\t\t\t\t  sizeof(struct bridge_flow),\n+\t\t\t\t\t  0, SLAB_HWCACHE_ALIGN, NULL);\n+\tif (!offload_cache)\n+\t\treturn -ENOMEM;\n+\n+\treturn 0;\n+}\n+\n+void br_offload_fini(void)\n+{\n+\tkmem_cache_destroy(offload_cache);\n+}\n--- a/net/bridge/br_private.h\n+++ b/net/bridge/br_private.h\n@@ -268,7 +268,13 @@ struct net_bridge_fdb_entry {\n \tunsigned long\t\t\tupdated ____cacheline_aligned_in_smp;\n \tunsigned long\t\t\tused;\n \n-\tstruct rcu_head\t\t\trcu;\n+\tunion {\n+\t\tstruct {\n+\t\t\tstruct hlist_head\t\toffload_in;\n+\t\t\tstruct hlist_head\t\toffload_out;\n+\t\t};\n+\t\tstruct rcu_head\t\t\trcu;\n+\t};\n };\n \n #define MDB_PG_FLAGS_PERMANENT\tBIT(0)\n@@ -343,6 +349,12 @@ struct net_bridge_mdb_entry {\n \tstruct rcu_head\t\t\trcu;\n };\n \n+struct net_bridge_port_offload {\n+\tstruct rhashtable\t\trht;\n+\tstruct work_struct\t\tgc_work;\n+\tbool\t\t\t\tenabled;\n+};\n+\n struct net_bridge_port {\n \tstruct net_bridge\t\t*br;\n \tstruct net_device\t\t*dev;\n@@ -403,6 +415,7 @@ struct net_bridge_port {\n \tu16\t\t\t\tbackup_redirected_cnt;\n \n \tstruct bridge_stp_xstats\tstp_xstats;\n+\tstruct net_bridge_port_offload\toffload;\n };\n \n #define kobj_to_brport(obj)\tcontainer_of(obj, struct net_bridge_port, kobj)\n@@ -519,6 +532,9 @@ struct net_bridge {\n \tstruct kobject\t\t\t*ifobj;\n \tu32\t\t\t\tauto_cnt;\n \n+\tu32\t\t\t\toffload_cache_size;\n+\tu32\t\t\t\toffload_cache_reserved;\n+\n #ifdef CONFIG_NET_SWITCHDEV\n \t/* Counter used to make sure that hardware domains get unique\n \t * identifiers in case a bridge spans multiple switchdev instances.\n@@ -553,6 +569,10 @@ struct br_input_skb_cb {\n #ifdef CONFIG_NETFILTER_FAMILY_BRIDGE\n \tu8 br_netfilter_broute:1;\n #endif\n+\tu8 offload:1;\n+\tu8 input_vlan_present:1;\n+\tu16 input_vlan_tag;\n+\tint input_ifindex;\n \n #ifdef CONFIG_NET_SWITCHDEV\n \t/* Set if TX data plane offloading is used towards at least one\n--- /dev/null\n+++ b/net/bridge/br_private_offload.h\n@@ -0,0 +1,23 @@\n+#ifndef __BR_OFFLOAD_H\n+#define __BR_OFFLOAD_H\n+\n+bool br_offload_input(struct net_bridge_port *p, struct sk_buff *skb);\n+void br_offload_output(struct sk_buff *skb);\n+void br_offload_port_state(struct net_bridge_port *p);\n+void br_offload_fdb_update(const struct net_bridge_fdb_entry *fdb);\n+int br_offload_init(void);\n+void br_offload_fini(void);\n+int br_offload_set_cache_size(struct net_bridge *br, unsigned long val,\n+\t\t\t       struct netlink_ext_ack *extack);\n+int br_offload_set_cache_reserved(struct net_bridge *br, unsigned long val,\n+\t\t\t \t   struct netlink_ext_ack *extack);\n+\n+static inline void br_offload_skb_disable(struct sk_buff *skb)\n+{\n+\tstruct br_input_skb_cb *cb = (struct br_input_skb_cb *)skb->cb;\n+\n+\tif (cb->offload)\n+\t\tcb->offload = 0;\n+}\n+\n+#endif\n--- a/net/bridge/br_stp.c\n+++ b/net/bridge/br_stp.c\n@@ -12,6 +12,7 @@\n \n #include \"br_private.h\"\n #include \"br_private_stp.h\"\n+#include \"br_private_offload.h\"\n \n /* since time values in bpdu are in jiffies and then scaled (1/256)\n  * before sending, make sure that is at least one STP tick.\n@@ -52,6 +53,8 @@ void br_set_state(struct net_bridge_port\n \t\t\t\t(unsigned int) p->port_no, p->dev->name,\n \t\t\t\tbr_port_state_names[p->state]);\n \n+\tbr_offload_port_state(p);\n+\n \tif (p->br->stp_enabled == BR_KERNEL_STP) {\n \t\tswitch (p->state) {\n \t\tcase BR_STATE_BLOCKING:\n--- a/net/bridge/br_sysfs_br.c\n+++ b/net/bridge/br_sysfs_br.c\n@@ -18,6 +18,7 @@\n #include <linux/sched/signal.h>\n \n #include \"br_private.h\"\n+#include \"br_private_offload.h\"\n \n /* IMPORTANT: new bridge options must be added with netlink support only\n  *            please do not add new sysfs entries\n@@ -930,6 +931,38 @@ static ssize_t vlan_stats_per_port_store\n static DEVICE_ATTR_RW(vlan_stats_per_port);\n #endif\n \n+static ssize_t offload_cache_size_show(struct device *d,\n+\t\t\t\t       struct device_attribute *attr,\n+\t\t\t\t       char *buf)\n+{\n+\tstruct net_bridge *br = to_bridge(d);\n+\treturn sprintf(buf, \"%u\\n\", br->offload_cache_size);\n+}\n+\n+static ssize_t offload_cache_size_store(struct device *d,\n+\t\t\t\t\tstruct device_attribute *attr,\n+\t\t\t\t\tconst char *buf, size_t len)\n+{\n+\treturn store_bridge_parm(d, buf, len, br_offload_set_cache_size);\n+}\n+static DEVICE_ATTR_RW(offload_cache_size);\n+\n+static ssize_t offload_cache_reserved_show(struct device *d,\n+\t\t\t\t       struct device_attribute *attr,\n+\t\t\t\t       char *buf)\n+{\n+\tstruct net_bridge *br = to_bridge(d);\n+\treturn sprintf(buf, \"%u\\n\", br->offload_cache_reserved);\n+}\n+\n+static ssize_t offload_cache_reserved_store(struct device *d,\n+\t\t\t\t\tstruct device_attribute *attr,\n+\t\t\t\t\tconst char *buf, size_t len)\n+{\n+\treturn store_bridge_parm(d, buf, len, br_offload_set_cache_reserved);\n+}\n+static DEVICE_ATTR_RW(offload_cache_reserved);\n+\n static struct attribute *bridge_attrs[] = {\n \t&dev_attr_forward_delay.attr,\n \t&dev_attr_hello_time.attr,\n@@ -984,6 +1017,8 @@ static struct attribute *bridge_attrs[]\n \t&dev_attr_vlan_stats_enabled.attr,\n \t&dev_attr_vlan_stats_per_port.attr,\n #endif\n+\t&dev_attr_offload_cache_size.attr,\n+\t&dev_attr_offload_cache_reserved.attr,\n \tNULL\n };\n \n--- a/net/bridge/br_sysfs_if.c\n+++ b/net/bridge/br_sysfs_if.c\n@@ -241,6 +241,7 @@ BRPORT_ATTR_FLAG(broadcast_flood, BR_BCA\n BRPORT_ATTR_FLAG(neigh_suppress, BR_NEIGH_SUPPRESS);\n BRPORT_ATTR_FLAG(isolated, BR_ISOLATED);\n BRPORT_ATTR_FLAG(bpdu_filter, BR_BPDU_FILTER);\n+BRPORT_ATTR_FLAG(offload, BR_OFFLOAD);\n \n #ifdef CONFIG_BRIDGE_IGMP_SNOOPING\n static ssize_t show_multicast_router(struct net_bridge_port *p, char *buf)\n@@ -295,6 +296,7 @@ static const struct brport_attribute *br\n \t&brport_attr_isolated,\n \t&brport_attr_bpdu_filter,\n \t&brport_attr_backup_port,\n+\t&brport_attr_offload,\n \tNULL\n };\n \n--- a/net/bridge/br_vlan_tunnel.c\n+++ b/net/bridge/br_vlan_tunnel.c\n@@ -15,6 +15,7 @@\n \n #include \"br_private.h\"\n #include \"br_private_tunnel.h\"\n+#include \"br_private_offload.h\"\n \n static inline int br_vlan_tunid_cmp(struct rhashtable_compare_arg *arg,\n \t\t\t\t    const void *ptr)\n@@ -180,6 +181,7 @@ void br_handle_ingress_vlan_tunnel(struc\n \tskb_dst_drop(skb);\n \n \t__vlan_hwaccel_put_tag(skb, p->br->vlan_proto, vlan->vid);\n+\tbr_offload_skb_disable(skb);\n }\n \n int br_handle_egress_vlan_tunnel(struct sk_buff *skb,\n@@ -201,6 +203,7 @@ int br_handle_egress_vlan_tunnel(struct\n \tif (err)\n \t\treturn err;\n \n+\tbr_offload_skb_disable(skb);\n \ttunnel_dst = rcu_dereference(vlan->tinfo.tunnel_dst);\n \tif (tunnel_dst && dst_hold_safe(&tunnel_dst->dst))\n \t\tskb_dst_set(skb, &tunnel_dst->dst);\n"
  },
  {
    "path": "target/linux/generic/hack-5.15/645-netfilter-connmark-introduce-set-dscpmark.patch",
    "content": "From eda40b8c8c82e0f2789d6bc8bf63846dce2e8f32 Mon Sep 17 00:00:00 2001\nFrom: Kevin Darbyshire-Bryant <ldir@darbyshire-bryant.me.uk>\nDate: Sat, 23 Mar 2019 09:29:49 +0000\nSubject: [PATCH] netfilter: connmark: introduce set-dscpmark\n\nset-dscpmark is a method of storing the DSCP of an ip packet into\nconntrack mark.  In combination with a suitable tc filter action\n(act_ctinfo) DSCP values are able to be stored in the mark on egress and\nrestored on ingress across links that otherwise alter or bleach DSCP.\n\nThis is useful for qdiscs such as CAKE which are able to shape according\nto policies based on DSCP.\n\nIngress classification is traditionally a challenging task since\niptables rules haven't yet run and tc filter/eBPF programs are pre-NAT\nlookups, hence are unable to see internal IPv4 addresses as used on the\ntypical home masquerading gateway.\n\nx_tables CONNMARK set-dscpmark target solves the problem of storing the\nDSCP to the conntrack mark in a way suitable for the new act_ctinfo tc\naction to restore.\n\nThe set-dscpmark option accepts 2 parameters, a 32bit 'dscpmask' and a\n32bit 'statemask'.  The dscp mask must be 6 contiguous bits and\nrepresents the area where the DSCP will be stored in the connmark.  The\nstate mask is a minimum 1 bit length mask that must not overlap with the\ndscpmask.  It represents a flag which is set when the DSCP has been\nstored in the conntrack mark. This is useful to implement a 'one shot'\niptables based classification where the 'complicated' iptables rules are\nonly run once to classify the connection on initial (egress) packet and\nsubsequent packets are all marked/restored with the same DSCP.  A state\nmask of zero disables the setting of a status bit/s.\n\nexample syntax with a suitably modified iptables user space application:\n\niptables -A QOS_MARK_eth0 -t mangle -j CONNMARK --set-dscpmark 0xfc000000/0x01000000\n\nWould store the DSCP in the top 6 bits of the 32bit mark field, and use\nthe LSB of the top byte as the 'DSCP has been stored' marker.\n\n|----0xFC----conntrack mark----000000---|\n| Bits 31-26 | bit 25 | bit24 |~~~ Bit 0|\n| DSCP       | unused | flag  |unused   |\n|-----------------------0x01---000000---|\n      ^                   ^\n      |                   |\n      ---|             Conditional flag\n         |             set this when dscp\n|-ip diffserv-|        stored in mark\n| 6 bits      |\n|-------------|\n\nan identically configured tc action to restore looks like:\n\ntc filter show dev eth0 ingress\nfilter parent ffff: protocol all pref 10 u32 chain 0\nfilter parent ffff: protocol all pref 10 u32 chain 0 fh 800: ht divisor 1\nfilter parent ffff: protocol all pref 10 u32 chain 0 fh 800::800 order 2048 key ht 800 bkt 0 flowid 1: not_in_hw\n  match 00000000/00000000 at 0\n\taction order 1: ctinfo zone 0 pipe\n\t index 2 ref 1 bind 1 dscp 0xfc000000/0x1000000\n\n\taction order 2: mirred (Egress Redirect to device ifb4eth0) stolen\n\tindex 1 ref 1 bind 1\n\n|----0xFC----conntrack mark----000000---|\n| Bits 31-26 | bit 25 | bit24 |~~~ Bit 0|\n| DSCP       | unused | flag  |unused   |\n|-----------------------0x01---000000---|\n      |                   |\n      |                   |\n      ---|             Conditional flag\n         v             only restore if set\n|-ip diffserv-|\n| 6 bits      |\n|-------------|\n\nSigned-off-by: Kevin Darbyshire-Bryant <ldir@darbyshire-bryant.me.uk>\n---\n include/uapi/linux/netfilter/xt_connmark.h | 10 ++++\n net/netfilter/xt_connmark.c                | 55 ++++++++++++++++++----\n 2 files changed, 57 insertions(+), 8 deletions(-)\n\n--- a/include/uapi/linux/netfilter/xt_connmark.h\n+++ b/include/uapi/linux/netfilter/xt_connmark.h\n@@ -20,6 +20,11 @@ enum {\n };\n \n enum {\n+\tXT_CONNMARK_VALUE =\t(1 << 0),\n+\tXT_CONNMARK_DSCP = \t(1 << 1)\n+};\n+\n+enum {\n \tD_SHIFT_LEFT = 0,\n \tD_SHIFT_RIGHT,\n };\n@@ -34,6 +39,11 @@ struct xt_connmark_tginfo2 {\n \t__u8 shift_dir, shift_bits, mode;\n };\n \n+struct xt_connmark_tginfo3 {\n+\t__u32 ctmark, ctmask, nfmask;\n+\t__u8 shift_dir, shift_bits, mode, func;\n+};\n+\n struct xt_connmark_mtinfo1 {\n \t__u32 mark, mask;\n \t__u8 invert;\n--- a/net/netfilter/xt_connmark.c\n+++ b/net/netfilter/xt_connmark.c\n@@ -24,12 +24,13 @@ MODULE_ALIAS(\"ipt_connmark\");\n MODULE_ALIAS(\"ip6t_connmark\");\n \n static unsigned int\n-connmark_tg_shift(struct sk_buff *skb, const struct xt_connmark_tginfo2 *info)\n+connmark_tg_shift(struct sk_buff *skb, const struct xt_connmark_tginfo3 *info)\n {\n \tenum ip_conntrack_info ctinfo;\n \tu_int32_t new_targetmark;\n \tstruct nf_conn *ct;\n \tu_int32_t newmark;\n+\tu_int8_t dscp;\n \n \tct = nf_ct_get(skb, &ctinfo);\n \tif (ct == NULL)\n@@ -37,12 +38,24 @@ connmark_tg_shift(struct sk_buff *skb, c\n \n \tswitch (info->mode) {\n \tcase XT_CONNMARK_SET:\n-\t\tnewmark = (ct->mark & ~info->ctmask) ^ info->ctmark;\n-\t\tif (info->shift_dir == D_SHIFT_RIGHT)\n-\t\t\tnewmark >>= info->shift_bits;\n-\t\telse\n-\t\t\tnewmark <<= info->shift_bits;\n+\t\tnewmark = ct->mark;\n+\t\tif (info->func & XT_CONNMARK_VALUE) {\n+\t\t\tnewmark = (newmark & ~info->ctmask) ^ info->ctmark;\n+\t\t\tif (info->shift_dir == D_SHIFT_RIGHT)\n+\t\t\t\tnewmark >>= info->shift_bits;\n+\t\t\telse\n+\t\t\t\tnewmark <<= info->shift_bits;\n+\t\t} else if (info->func & XT_CONNMARK_DSCP) {\n+\t\t\tif (skb->protocol == htons(ETH_P_IP))\n+\t\t\t\tdscp = ipv4_get_dsfield(ip_hdr(skb)) >> 2;\n+\t\t\telse if (skb->protocol == htons(ETH_P_IPV6))\n+\t\t\t\tdscp = ipv6_get_dsfield(ipv6_hdr(skb)) >> 2;\n+\t\t\telse\t/* protocol doesn't have diffserv */\n+\t\t\t\tbreak;\n \n+\t\t\tnewmark = (newmark & ~info->ctmark) |\n+\t\t\t\t  (info->ctmask | (dscp << info->shift_bits));\n+\t\t}\n \t\tif (ct->mark != newmark) {\n \t\t\tct->mark = newmark;\n \t\t\tnf_conntrack_event_cache(IPCT_MARK, ct);\n@@ -81,20 +94,36 @@ static unsigned int\n connmark_tg(struct sk_buff *skb, const struct xt_action_param *par)\n {\n \tconst struct xt_connmark_tginfo1 *info = par->targinfo;\n-\tconst struct xt_connmark_tginfo2 info2 = {\n+\tconst struct xt_connmark_tginfo3 info3 = {\n \t\t.ctmark\t= info->ctmark,\n \t\t.ctmask\t= info->ctmask,\n \t\t.nfmask\t= info->nfmask,\n \t\t.mode\t= info->mode,\n+\t\t.func\t= XT_CONNMARK_VALUE\n \t};\n \n-\treturn connmark_tg_shift(skb, &info2);\n+\treturn connmark_tg_shift(skb, &info3);\n }\n \n static unsigned int\n connmark_tg_v2(struct sk_buff *skb, const struct xt_action_param *par)\n {\n \tconst struct xt_connmark_tginfo2 *info = par->targinfo;\n+\tconst struct xt_connmark_tginfo3 info3 = {\n+\t\t.ctmark\t= info->ctmark,\n+\t\t.ctmask\t= info->ctmask,\n+\t\t.nfmask\t= info->nfmask,\n+\t\t.mode\t= info->mode,\n+\t\t.func\t= XT_CONNMARK_VALUE\n+\t};\n+\n+\treturn connmark_tg_shift(skb, &info3);\n+}\n+\n+static unsigned int\n+connmark_tg_v3(struct sk_buff *skb, const struct xt_action_param *par)\n+{\n+\tconst struct xt_connmark_tginfo3 *info = par->targinfo;\n \n \treturn connmark_tg_shift(skb, info);\n }\n@@ -165,6 +194,16 @@ static struct xt_target connmark_tg_reg[\n \t\t.targetsize     = sizeof(struct xt_connmark_tginfo2),\n \t\t.destroy        = connmark_tg_destroy,\n \t\t.me             = THIS_MODULE,\n+\t},\n+\t{\n+\t\t.name           = \"CONNMARK\",\n+\t\t.revision       = 3,\n+\t\t.family         = NFPROTO_UNSPEC,\n+\t\t.checkentry     = connmark_tg_check,\n+\t\t.target         = connmark_tg_v3,\n+\t\t.targetsize     = sizeof(struct xt_connmark_tginfo3),\n+\t\t.destroy        = connmark_tg_destroy,\n+\t\t.me             = THIS_MODULE,\n \t}\n };\n \n"
  },
  {
    "path": "target/linux/generic/hack-5.15/650-netfilter-add-xt_FLOWOFFLOAD-target.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nDate: Tue, 20 Feb 2018 15:56:02 +0100\nSubject: [PATCH] netfilter: add xt_FLOWOFFLOAD target\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n create mode 100644 net/netfilter/xt_OFFLOAD.c\n\n--- a/net/ipv4/netfilter/Kconfig\n+++ b/net/ipv4/netfilter/Kconfig\n@@ -56,8 +56,6 @@ config NF_TABLES_ARP\n \thelp\n \t  This option enables the ARP support for nf_tables.\n \n-endif # NF_TABLES\n-\n config NF_FLOW_TABLE_IPV4\n \ttristate \"Netfilter flow table IPv4 module\"\n \tdepends on NF_FLOW_TABLE\n@@ -66,6 +64,8 @@ config NF_FLOW_TABLE_IPV4\n \n \t  To compile it as a module, choose M here.\n \n+endif # NF_TABLES\n+\n config NF_DUP_IPV4\n \ttristate \"Netfilter IPv4 packet duplication to alternate destination\"\n \tdepends on !NF_CONNTRACK || NF_CONNTRACK\n--- a/net/ipv6/netfilter/Kconfig\n+++ b/net/ipv6/netfilter/Kconfig\n@@ -45,7 +45,6 @@ config NFT_FIB_IPV6\n \t  multicast or blackhole.\n \n endif # NF_TABLES_IPV6\n-endif # NF_TABLES\n \n config NF_FLOW_TABLE_IPV6\n \ttristate \"Netfilter flow table IPv6 module\"\n@@ -55,6 +54,8 @@ config NF_FLOW_TABLE_IPV6\n \n \t  To compile it as a module, choose M here.\n \n+endif # NF_TABLES\n+\n config NF_DUP_IPV6\n \ttristate \"Netfilter IPv6 packet duplication to alternate destination\"\n \tdepends on !NF_CONNTRACK || NF_CONNTRACK\n--- a/net/netfilter/Kconfig\n+++ b/net/netfilter/Kconfig\n@@ -708,8 +708,6 @@ config NFT_REJECT_NETDEV\n \n endif # NF_TABLES_NETDEV\n \n-endif # NF_TABLES\n-\n config NF_FLOW_TABLE_INET\n \ttristate \"Netfilter flow table mixed IPv4/IPv6 module\"\n \tdepends on NF_FLOW_TABLE\n@@ -718,11 +716,12 @@ config NF_FLOW_TABLE_INET\n \n \t  To compile it as a module, choose M here.\n \n+endif # NF_TABLES\n+\n config NF_FLOW_TABLE\n \ttristate \"Netfilter flow table module\"\n \tdepends on NETFILTER_INGRESS\n \tdepends on NF_CONNTRACK\n-\tdepends on NF_TABLES\n \thelp\n \t  This option adds the flow table core infrastructure.\n \n@@ -1011,6 +1010,15 @@ config NETFILTER_XT_TARGET_NOTRACK\n \tdepends on NETFILTER_ADVANCED\n \tselect NETFILTER_XT_TARGET_CT\n \n+config NETFILTER_XT_TARGET_FLOWOFFLOAD\n+\ttristate '\"FLOWOFFLOAD\" target support'\n+\tdepends on NF_FLOW_TABLE\n+\tdepends on NETFILTER_INGRESS\n+\thelp\n+\t  This option adds a `FLOWOFFLOAD' target, which uses the nf_flow_offload\n+\t  module to speed up processing of packets by bypassing the usual\n+\t  netfilter chains\n+\n config NETFILTER_XT_TARGET_RATEEST\n \ttristate '\"RATEEST\" target support'\n \tdepends on NETFILTER_ADVANCED\n--- a/net/netfilter/Makefile\n+++ b/net/netfilter/Makefile\n@@ -143,6 +143,7 @@ obj-$(CONFIG_NETFILTER_XT_TARGET_CLASSIF\n obj-$(CONFIG_NETFILTER_XT_TARGET_CONNSECMARK) += xt_CONNSECMARK.o\n obj-$(CONFIG_NETFILTER_XT_TARGET_CT) += xt_CT.o\n obj-$(CONFIG_NETFILTER_XT_TARGET_DSCP) += xt_DSCP.o\n+obj-$(CONFIG_NETFILTER_XT_TARGET_FLOWOFFLOAD) += xt_FLOWOFFLOAD.o\n obj-$(CONFIG_NETFILTER_XT_TARGET_HL) += xt_HL.o\n obj-$(CONFIG_NETFILTER_XT_TARGET_HMARK) += xt_HMARK.o\n obj-$(CONFIG_NETFILTER_XT_TARGET_LED) += xt_LED.o\n--- /dev/null\n+++ b/net/netfilter/xt_FLOWOFFLOAD.c\n@@ -0,0 +1,694 @@\n+/*\n+ * Copyright (C) 2018-2021 Felix Fietkau <nbd@nbd.name>\n+ *\n+ * This program is free software; you can redistribute it and/or modify\n+ * it under the terms of the GNU General Public License version 2 as\n+ * published by the Free Software Foundation.\n+ */\n+#include <linux/module.h>\n+#include <linux/init.h>\n+#include <linux/netfilter.h>\n+#include <linux/netfilter/xt_FLOWOFFLOAD.h>\n+#include <linux/if_vlan.h>\n+#include <net/ip.h>\n+#include <net/netfilter/nf_conntrack.h>\n+#include <net/netfilter/nf_conntrack_extend.h>\n+#include <net/netfilter/nf_conntrack_helper.h>\n+#include <net/netfilter/nf_flow_table.h>\n+\n+struct xt_flowoffload_hook {\n+\tstruct hlist_node list;\n+\tstruct nf_hook_ops ops;\n+\tstruct net *net;\n+\tbool registered;\n+\tbool used;\n+};\n+\n+struct xt_flowoffload_table {\n+\tstruct nf_flowtable ft;\n+\tstruct hlist_head hooks;\n+\tstruct delayed_work work;\n+};\n+\n+struct nf_forward_info {\n+\tconst struct net_device *indev;\n+\tconst struct net_device *outdev;\n+\tconst struct net_device *hw_outdev;\n+\tstruct id {\n+\t\t__u16\tid;\n+\t\t__be16\tproto;\n+\t} encap[NF_FLOW_TABLE_ENCAP_MAX];\n+\tu8 num_encaps;\n+\tu8 ingress_vlans;\n+\tu8 h_source[ETH_ALEN];\n+\tu8 h_dest[ETH_ALEN];\n+\tenum flow_offload_xmit_type xmit_type;\n+};\n+\n+static DEFINE_SPINLOCK(hooks_lock);\n+\n+struct xt_flowoffload_table flowtable[2];\n+\n+static unsigned int\n+xt_flowoffload_net_hook(void *priv, struct sk_buff *skb,\n+\t\t\tconst struct nf_hook_state *state)\n+{\n+\tstruct vlan_ethhdr *veth;\n+\t__be16 proto;\n+\n+\tswitch (skb->protocol) {\n+\tcase htons(ETH_P_8021Q):\n+\t\tveth = (struct vlan_ethhdr *)skb_mac_header(skb);\n+\t\tproto = veth->h_vlan_encapsulated_proto;\n+\t\tbreak;\n+\tcase htons(ETH_P_PPP_SES):\n+\t\tproto = nf_flow_pppoe_proto(skb);\n+\t\tbreak;\n+\tdefault:\n+\t\tproto = skb->protocol;\n+\t\tbreak;\n+\t}\n+\n+\tswitch (proto) {\n+\tcase htons(ETH_P_IP):\n+\t\treturn nf_flow_offload_ip_hook(priv, skb, state);\n+\tcase htons(ETH_P_IPV6):\n+\t\treturn nf_flow_offload_ipv6_hook(priv, skb, state);\n+\t}\n+\n+\treturn NF_ACCEPT;\n+}\n+\n+static int\n+xt_flowoffload_create_hook(struct xt_flowoffload_table *table,\n+\t\t\t   struct net_device *dev)\n+{\n+\tstruct xt_flowoffload_hook *hook;\n+\tstruct nf_hook_ops *ops;\n+\n+\thook = kzalloc(sizeof(*hook), GFP_ATOMIC);\n+\tif (!hook)\n+\t\treturn -ENOMEM;\n+\n+\tops = &hook->ops;\n+\tops->pf = NFPROTO_NETDEV;\n+\tops->hooknum = NF_NETDEV_INGRESS;\n+\tops->priority = 10;\n+\tops->priv = &table->ft;\n+\tops->hook = xt_flowoffload_net_hook;\n+\tops->dev = dev;\n+\n+\thlist_add_head(&hook->list, &table->hooks);\n+\tmod_delayed_work(system_power_efficient_wq, &table->work, 0);\n+\n+\treturn 0;\n+}\n+\n+static struct xt_flowoffload_hook *\n+flow_offload_lookup_hook(struct xt_flowoffload_table *table,\n+\t\t\t struct net_device *dev)\n+{\n+\tstruct xt_flowoffload_hook *hook;\n+\n+\thlist_for_each_entry(hook, &table->hooks, list) {\n+\t\tif (hook->ops.dev == dev)\n+\t\t\treturn hook;\n+\t}\n+\n+\treturn NULL;\n+}\n+\n+static void\n+xt_flowoffload_check_device(struct xt_flowoffload_table *table,\n+\t\t\t    struct net_device *dev)\n+{\n+\tstruct xt_flowoffload_hook *hook;\n+\n+\tif (!dev)\n+\t\treturn;\n+\n+\tspin_lock_bh(&hooks_lock);\n+\thook = flow_offload_lookup_hook(table, dev);\n+\tif (hook)\n+\t\thook->used = true;\n+\telse\n+\t\txt_flowoffload_create_hook(table, dev);\n+\tspin_unlock_bh(&hooks_lock);\n+}\n+\n+static void\n+xt_flowoffload_register_hooks(struct xt_flowoffload_table *table)\n+{\n+\tstruct xt_flowoffload_hook *hook;\n+\n+restart:\n+\thlist_for_each_entry(hook, &table->hooks, list) {\n+\t\tif (hook->registered)\n+\t\t\tcontinue;\n+\n+\t\thook->registered = true;\n+\t\thook->net = dev_net(hook->ops.dev);\n+\t\tspin_unlock_bh(&hooks_lock);\n+\t\tnf_register_net_hook(hook->net, &hook->ops);\n+\t\tif (table->ft.flags & NF_FLOWTABLE_HW_OFFLOAD)\n+\t\t\ttable->ft.type->setup(&table->ft, hook->ops.dev,\n+\t\t\t\t\t      FLOW_BLOCK_BIND);\n+\t\tspin_lock_bh(&hooks_lock);\n+\t\tgoto restart;\n+\t}\n+\n+}\n+\n+static bool\n+xt_flowoffload_cleanup_hooks(struct xt_flowoffload_table *table)\n+{\n+\tstruct xt_flowoffload_hook *hook;\n+\tbool active = false;\n+\n+restart:\n+\tspin_lock_bh(&hooks_lock);\n+\thlist_for_each_entry(hook, &table->hooks, list) {\n+\t\tif (hook->used || !hook->registered) {\n+\t\t\tactive = true;\n+\t\t\tcontinue;\n+\t\t}\n+\n+\t\thlist_del(&hook->list);\n+\t\tspin_unlock_bh(&hooks_lock);\n+\t\tif (table->ft.flags & NF_FLOWTABLE_HW_OFFLOAD)\n+\t\t\ttable->ft.type->setup(&table->ft, hook->ops.dev,\n+\t\t\t\t\t      FLOW_BLOCK_UNBIND);\n+\t\tnf_unregister_net_hook(hook->net, &hook->ops);\n+\t\tkfree(hook);\n+\t\tgoto restart;\n+\t}\n+\tspin_unlock_bh(&hooks_lock);\n+\n+\treturn active;\n+}\n+\n+static void\n+xt_flowoffload_check_hook(struct flow_offload *flow, void *data)\n+{\n+\tstruct xt_flowoffload_table *table = data;\n+\tstruct flow_offload_tuple *tuple0 = &flow->tuplehash[0].tuple;\n+\tstruct flow_offload_tuple *tuple1 = &flow->tuplehash[1].tuple;\n+\tstruct xt_flowoffload_hook *hook;\n+\n+\tspin_lock_bh(&hooks_lock);\n+\thlist_for_each_entry(hook, &table->hooks, list) {\n+\t\tif (hook->ops.dev->ifindex != tuple0->iifidx &&\n+\t\t    hook->ops.dev->ifindex != tuple1->iifidx)\n+\t\t\tcontinue;\n+\n+\t\thook->used = true;\n+\t}\n+\tspin_unlock_bh(&hooks_lock);\n+}\n+\n+static void\n+xt_flowoffload_hook_work(struct work_struct *work)\n+{\n+\tstruct xt_flowoffload_table *table;\n+\tstruct xt_flowoffload_hook *hook;\n+\tint err;\n+\n+\ttable = container_of(work, struct xt_flowoffload_table, work.work);\n+\n+\tspin_lock_bh(&hooks_lock);\n+\txt_flowoffload_register_hooks(table);\n+\thlist_for_each_entry(hook, &table->hooks, list)\n+\t\thook->used = false;\n+\tspin_unlock_bh(&hooks_lock);\n+\n+\terr = nf_flow_table_iterate(&table->ft, xt_flowoffload_check_hook,\n+\t\t\t\t    table);\n+\tif (err && err != -EAGAIN)\n+\t\tgoto out;\n+\n+\tif (!xt_flowoffload_cleanup_hooks(table))\n+\t\treturn;\n+\n+out:\n+\tqueue_delayed_work(system_power_efficient_wq, &table->work, HZ);\n+}\n+\n+static bool\n+xt_flowoffload_skip(struct sk_buff *skb, int family)\n+{\n+\tif (skb_sec_path(skb))\n+\t\treturn true;\n+\n+\tif (family == NFPROTO_IPV4) {\n+\t\tconst struct ip_options *opt = &(IPCB(skb)->opt);\n+\n+\t\tif (unlikely(opt->optlen))\n+\t\t\treturn true;\n+\t}\n+\n+\treturn false;\n+}\n+\n+static enum flow_offload_xmit_type nf_xmit_type(struct dst_entry *dst)\n+{\n+\tif (dst_xfrm(dst))\n+\t\treturn FLOW_OFFLOAD_XMIT_XFRM;\n+\n+\treturn FLOW_OFFLOAD_XMIT_NEIGH;\n+}\n+\n+static void nf_default_forward_path(struct nf_flow_route *route,\n+\t\t\t\t    struct dst_entry *dst_cache,\n+\t\t\t\t    enum ip_conntrack_dir dir,\n+\t\t\t\t    struct net_device **dev)\n+{\n+\tdev[!dir] = dst_cache->dev;\n+\troute->tuple[!dir].in.ifindex\t= dst_cache->dev->ifindex;\n+\troute->tuple[dir].dst\t\t= dst_cache;\n+\troute->tuple[dir].xmit_type\t= nf_xmit_type(dst_cache);\n+}\n+\n+static bool nf_is_valid_ether_device(const struct net_device *dev)\n+{\n+\tif (!dev || (dev->flags & IFF_LOOPBACK) || dev->type != ARPHRD_ETHER ||\n+\t    dev->addr_len != ETH_ALEN || !is_valid_ether_addr(dev->dev_addr))\n+\t\treturn false;\n+\n+\treturn true;\n+}\n+\n+static void nf_dev_path_info(const struct net_device_path_stack *stack,\n+\t\t\t     struct nf_forward_info *info,\n+\t\t\t     unsigned char *ha)\n+{\n+\tconst struct net_device_path *path;\n+\tint i;\n+\n+\tmemcpy(info->h_dest, ha, ETH_ALEN);\n+\n+\tfor (i = 0; i < stack->num_paths; i++) {\n+\t\tpath = &stack->path[i];\n+\t\tswitch (path->type) {\n+\t\tcase DEV_PATH_ETHERNET:\n+\t\tcase DEV_PATH_DSA:\n+\t\tcase DEV_PATH_VLAN:\n+\t\tcase DEV_PATH_PPPOE:\n+\t\t\tinfo->indev = path->dev;\n+\t\t\tif (is_zero_ether_addr(info->h_source))\n+\t\t\t\tmemcpy(info->h_source, path->dev->dev_addr, ETH_ALEN);\n+\n+\t\t\tif (path->type == DEV_PATH_ETHERNET)\n+\t\t\t\tbreak;\n+\t\t\tif (path->type == DEV_PATH_DSA) {\n+\t\t\t\ti = stack->num_paths;\n+\t\t\t\tbreak;\n+\t\t\t}\n+\n+\t\t\t/* DEV_PATH_VLAN and DEV_PATH_PPPOE */\n+\t\t\tif (info->num_encaps >= NF_FLOW_TABLE_ENCAP_MAX) {\n+\t\t\t\tinfo->indev = NULL;\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t\tif (!info->outdev)\n+\t\t\t\tinfo->outdev = path->dev;\n+\t\t\tinfo->encap[info->num_encaps].id = path->encap.id;\n+\t\t\tinfo->encap[info->num_encaps].proto = path->encap.proto;\n+\t\t\tinfo->num_encaps++;\n+\t\t\tif (path->type == DEV_PATH_PPPOE)\n+\t\t\t\tmemcpy(info->h_dest, path->encap.h_dest, ETH_ALEN);\n+\t\t\tbreak;\n+\t\tcase DEV_PATH_BRIDGE:\n+\t\t\tif (is_zero_ether_addr(info->h_source))\n+\t\t\t\tmemcpy(info->h_source, path->dev->dev_addr, ETH_ALEN);\n+\n+\t\t\tswitch (path->bridge.vlan_mode) {\n+\t\t\tcase DEV_PATH_BR_VLAN_UNTAG_HW:\n+\t\t\t\tinfo->ingress_vlans |= BIT(info->num_encaps - 1);\n+\t\t\t\tbreak;\n+\t\t\tcase DEV_PATH_BR_VLAN_TAG:\n+\t\t\t\tinfo->encap[info->num_encaps].id = path->bridge.vlan_id;\n+\t\t\t\tinfo->encap[info->num_encaps].proto = path->bridge.vlan_proto;\n+\t\t\t\tinfo->num_encaps++;\n+\t\t\t\tbreak;\n+\t\t\tcase DEV_PATH_BR_VLAN_UNTAG:\n+\t\t\t\tinfo->num_encaps--;\n+\t\t\t\tbreak;\n+\t\t\tcase DEV_PATH_BR_VLAN_KEEP:\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tinfo->indev = NULL;\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\tif (!info->outdev)\n+\t\tinfo->outdev = info->indev;\n+\n+\tinfo->hw_outdev = info->indev;\n+\n+\tif (nf_is_valid_ether_device(info->indev))\n+\t\tinfo->xmit_type = FLOW_OFFLOAD_XMIT_DIRECT;\n+}\n+\n+static int nf_dev_fill_forward_path(const struct nf_flow_route *route,\n+\t\t\t\t     const struct dst_entry *dst_cache,\n+\t\t\t\t     const struct nf_conn *ct,\n+\t\t\t\t     enum ip_conntrack_dir dir, u8 *ha,\n+\t\t\t\t     struct net_device_path_stack *stack)\n+{\n+\tconst void *daddr = &ct->tuplehash[!dir].tuple.src.u3;\n+\tstruct net_device *dev = dst_cache->dev;\n+\tstruct neighbour *n;\n+\tu8 nud_state;\n+\n+\tif (!nf_is_valid_ether_device(dev))\n+\t\tgoto out;\n+\n+\tn = dst_neigh_lookup(dst_cache, daddr);\n+\tif (!n)\n+\t\treturn -1;\n+\n+\tread_lock_bh(&n->lock);\n+\tnud_state = n->nud_state;\n+\tether_addr_copy(ha, n->ha);\n+\tread_unlock_bh(&n->lock);\n+\tneigh_release(n);\n+\n+\tif (!(nud_state & NUD_VALID))\n+\t\treturn -1;\n+\n+out:\n+\treturn dev_fill_forward_path(dev, ha, stack);\n+}\n+\n+static void nf_dev_forward_path(struct nf_flow_route *route,\n+\t\t\t\tconst struct nf_conn *ct,\n+\t\t\t\tenum ip_conntrack_dir dir,\n+\t\t\t\tstruct net_device **devs)\n+{\n+\tconst struct dst_entry *dst = route->tuple[dir].dst;\n+\tstruct net_device_path_stack stack;\n+\tstruct nf_forward_info info = {};\n+\tunsigned char ha[ETH_ALEN];\n+\tint i;\n+\n+\tif (nf_dev_fill_forward_path(route, dst, ct, dir, ha, &stack) >= 0)\n+\t\tnf_dev_path_info(&stack, &info, ha);\n+\n+\tdevs[!dir] = (struct net_device *)info.indev;\n+\tif (!info.indev)\n+\t\treturn;\n+\n+\troute->tuple[!dir].in.ifindex = info.indev->ifindex;\n+\tfor (i = 0; i < info.num_encaps; i++) {\n+\t\troute->tuple[!dir].in.encap[i].id = info.encap[i].id;\n+\t\troute->tuple[!dir].in.encap[i].proto = info.encap[i].proto;\n+\t}\n+\troute->tuple[!dir].in.num_encaps = info.num_encaps;\n+\troute->tuple[!dir].in.ingress_vlans = info.ingress_vlans;\n+\n+\tif (info.xmit_type == FLOW_OFFLOAD_XMIT_DIRECT) {\n+\t\tmemcpy(route->tuple[dir].out.h_source, info.h_source, ETH_ALEN);\n+\t\tmemcpy(route->tuple[dir].out.h_dest, info.h_dest, ETH_ALEN);\n+\t\troute->tuple[dir].out.ifindex = info.outdev->ifindex;\n+\t\troute->tuple[dir].out.hw_ifindex = info.hw_outdev->ifindex;\n+\t\troute->tuple[dir].xmit_type = info.xmit_type;\n+\t}\n+}\n+\n+static int\n+xt_flowoffload_route(struct sk_buff *skb, const struct nf_conn *ct,\n+\t\t     const struct xt_action_param *par,\n+\t\t     struct nf_flow_route *route, enum ip_conntrack_dir dir,\n+\t\t     struct net_device **devs)\n+{\n+\tstruct dst_entry *this_dst = skb_dst(skb);\n+\tstruct dst_entry *other_dst = NULL;\n+\tstruct flowi fl;\n+\n+\tmemset(&fl, 0, sizeof(fl));\n+\tswitch (xt_family(par)) {\n+\tcase NFPROTO_IPV4:\n+\t\tfl.u.ip4.daddr = ct->tuplehash[dir].tuple.src.u3.ip;\n+\t\tfl.u.ip4.flowi4_oif = xt_in(par)->ifindex;\n+\t\tbreak;\n+\tcase NFPROTO_IPV6:\n+\t\tfl.u.ip6.saddr = ct->tuplehash[!dir].tuple.dst.u3.in6;\n+\t\tfl.u.ip6.daddr = ct->tuplehash[dir].tuple.src.u3.in6;\n+\t\tfl.u.ip6.flowi6_oif = xt_in(par)->ifindex;\n+\t\tbreak;\n+\t}\n+\n+\tnf_route(xt_net(par), &other_dst, &fl, false, xt_family(par));\n+\tif (!other_dst)\n+\t\treturn -ENOENT;\n+\n+\tnf_default_forward_path(route, this_dst, dir, devs);\n+\tnf_default_forward_path(route, other_dst, !dir, devs);\n+\n+\tif (route->tuple[dir].xmit_type\t== FLOW_OFFLOAD_XMIT_NEIGH &&\n+\t    route->tuple[!dir].xmit_type == FLOW_OFFLOAD_XMIT_NEIGH) {\n+\t\tnf_dev_forward_path(route, ct, dir, devs);\n+\t\tnf_dev_forward_path(route, ct, !dir, devs);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static unsigned int\n+flowoffload_tg(struct sk_buff *skb, const struct xt_action_param *par)\n+{\n+\tstruct xt_flowoffload_table *table;\n+\tconst struct xt_flowoffload_target_info *info = par->targinfo;\n+\tstruct tcphdr _tcph, *tcph = NULL;\n+\tenum ip_conntrack_info ctinfo;\n+\tenum ip_conntrack_dir dir;\n+\tstruct nf_flow_route route = {};\n+\tstruct flow_offload *flow = NULL;\n+\tstruct net_device *devs[2] = {};\n+\tstruct nf_conn *ct;\n+\tstruct net *net;\n+\n+\tif (xt_flowoffload_skip(skb, xt_family(par)))\n+\t\treturn XT_CONTINUE;\n+\n+\tct = nf_ct_get(skb, &ctinfo);\n+\tif (ct == NULL)\n+\t\treturn XT_CONTINUE;\n+\n+\tswitch (ct->tuplehash[IP_CT_DIR_ORIGINAL].tuple.dst.protonum) {\n+\tcase IPPROTO_TCP:\n+\t\tif (ct->proto.tcp.state != TCP_CONNTRACK_ESTABLISHED)\n+\t\t\treturn XT_CONTINUE;\n+\n+\t\ttcph = skb_header_pointer(skb, par->thoff,\n+\t\t\t\t\t  sizeof(_tcph), &_tcph);\n+\t\tif (unlikely(!tcph || tcph->fin || tcph->rst))\n+\t\t\treturn XT_CONTINUE;\n+\t\tbreak;\n+\tcase IPPROTO_UDP:\n+\t\tbreak;\n+\tdefault:\n+\t\treturn XT_CONTINUE;\n+\t}\n+\n+\tif (nf_ct_ext_exist(ct, NF_CT_EXT_HELPER) ||\n+\t    ct->status & (IPS_SEQ_ADJUST | IPS_NAT_CLASH))\n+\t\treturn XT_CONTINUE;\n+\n+\tif (!nf_ct_is_confirmed(ct))\n+\t\treturn XT_CONTINUE;\n+\n+\tdevs[dir] = xt_out(par);\n+\tdevs[!dir] = xt_in(par);\n+\n+\tif (!devs[dir] || !devs[!dir])\n+\t\treturn XT_CONTINUE;\n+\n+\tif (test_and_set_bit(IPS_OFFLOAD_BIT, &ct->status))\n+\t\treturn XT_CONTINUE;\n+\n+\tdir = CTINFO2DIR(ctinfo);\n+\n+\tif (xt_flowoffload_route(skb, ct, par, &route, dir, devs) < 0)\n+\t\tgoto err_flow_route;\n+\n+\tflow = flow_offload_alloc(ct);\n+\tif (!flow)\n+\t\tgoto err_flow_alloc;\n+\n+\tif (flow_offload_route_init(flow, &route) < 0)\n+\t\tgoto err_flow_add;\n+\n+\tif (tcph) {\n+\t\tct->proto.tcp.seen[0].flags |= IP_CT_TCP_FLAG_BE_LIBERAL;\n+\t\tct->proto.tcp.seen[1].flags |= IP_CT_TCP_FLAG_BE_LIBERAL;\n+\t}\n+\n+\ttable = &flowtable[!!(info->flags & XT_FLOWOFFLOAD_HW)];\n+\n+\tnet = read_pnet(&table->ft.net);\n+\tif (!net)\n+\t\twrite_pnet(&table->ft.net, xt_net(par));\n+\n+\tif (flow_offload_add(&table->ft, flow) < 0)\n+\t\tgoto err_flow_add;\n+\n+\txt_flowoffload_check_device(table, devs[0]);\n+\txt_flowoffload_check_device(table, devs[1]);\n+\n+\tdst_release(route.tuple[!dir].dst);\n+\n+\treturn XT_CONTINUE;\n+\n+err_flow_add:\n+\tflow_offload_free(flow);\n+err_flow_alloc:\n+\tdst_release(route.tuple[!dir].dst);\n+err_flow_route:\n+\tclear_bit(IPS_OFFLOAD_BIT, &ct->status);\n+\n+\treturn XT_CONTINUE;\n+}\n+\n+static int flowoffload_chk(const struct xt_tgchk_param *par)\n+{\n+\tstruct xt_flowoffload_target_info *info = par->targinfo;\n+\n+\tif (info->flags & ~XT_FLOWOFFLOAD_MASK)\n+\t\treturn -EINVAL;\n+\n+\treturn 0;\n+}\n+\n+static struct xt_target offload_tg_reg __read_mostly = {\n+\t.family\t\t= NFPROTO_UNSPEC,\n+\t.name\t\t= \"FLOWOFFLOAD\",\n+\t.revision\t= 0,\n+\t.targetsize\t= sizeof(struct xt_flowoffload_target_info),\n+\t.usersize\t= sizeof(struct xt_flowoffload_target_info),\n+\t.checkentry\t= flowoffload_chk,\n+\t.target\t\t= flowoffload_tg,\n+\t.me\t\t= THIS_MODULE,\n+};\n+\n+static int flow_offload_netdev_event(struct notifier_block *this,\n+\t\t\t\t     unsigned long event, void *ptr)\n+{\n+\tstruct xt_flowoffload_hook *hook0, *hook1;\n+\tstruct net_device *dev = netdev_notifier_info_to_dev(ptr);\n+\n+\tif (event != NETDEV_UNREGISTER)\n+\t\treturn NOTIFY_DONE;\n+\n+\tspin_lock_bh(&hooks_lock);\n+\thook0 = flow_offload_lookup_hook(&flowtable[0], dev);\n+\tif (hook0)\n+\t\thlist_del(&hook0->list);\n+\n+\thook1 = flow_offload_lookup_hook(&flowtable[1], dev);\n+\tif (hook1)\n+\t\thlist_del(&hook1->list);\n+\tspin_unlock_bh(&hooks_lock);\n+\n+\tif (hook0) {\n+\t\tnf_unregister_net_hook(hook0->net, &hook0->ops);\n+\t\tkfree(hook0);\n+\t}\n+\n+\tif (hook1) {\n+\t\tnf_unregister_net_hook(hook1->net, &hook1->ops);\n+\t\tkfree(hook1);\n+\t}\n+\n+\tnf_flow_table_cleanup(dev);\n+\n+\treturn NOTIFY_DONE;\n+}\n+\n+static struct notifier_block flow_offload_netdev_notifier = {\n+\t.notifier_call\t= flow_offload_netdev_event,\n+};\n+\n+static int nf_flow_rule_route_inet(struct net *net,\n+\t\t\t\t   const struct flow_offload *flow,\n+\t\t\t\t   enum flow_offload_tuple_dir dir,\n+\t\t\t\t   struct nf_flow_rule *flow_rule)\n+{\n+\tconst struct flow_offload_tuple *flow_tuple = &flow->tuplehash[dir].tuple;\n+\tint err;\n+\n+\tswitch (flow_tuple->l3proto) {\n+\tcase NFPROTO_IPV4:\n+\t\terr = nf_flow_rule_route_ipv4(net, flow, dir, flow_rule);\n+\t\tbreak;\n+\tcase NFPROTO_IPV6:\n+\t\terr = nf_flow_rule_route_ipv6(net, flow, dir, flow_rule);\n+\t\tbreak;\n+\tdefault:\n+\t\terr = -1;\n+\t\tbreak;\n+\t}\n+\n+\treturn err;\n+}\n+\n+static struct nf_flowtable_type flowtable_inet = {\n+\t.family\t\t= NFPROTO_INET,\n+\t.init\t\t= nf_flow_table_init,\n+\t.setup\t\t= nf_flow_table_offload_setup,\n+\t.action\t\t= nf_flow_rule_route_inet,\n+\t.free\t\t= nf_flow_table_free,\n+\t.hook\t\t= xt_flowoffload_net_hook,\n+\t.owner\t\t= THIS_MODULE,\n+};\n+\n+static int init_flowtable(struct xt_flowoffload_table *tbl)\n+{\n+\tINIT_DELAYED_WORK(&tbl->work, xt_flowoffload_hook_work);\n+\ttbl->ft.type = &flowtable_inet;\n+\n+\treturn nf_flow_table_init(&tbl->ft);\n+}\n+\n+static int __init xt_flowoffload_tg_init(void)\n+{\n+\tint ret;\n+\n+\tregister_netdevice_notifier(&flow_offload_netdev_notifier);\n+\n+\tret = init_flowtable(&flowtable[0]);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = init_flowtable(&flowtable[1]);\n+\tif (ret)\n+\t\tgoto cleanup;\n+\n+\tflowtable[1].ft.flags = NF_FLOWTABLE_HW_OFFLOAD;\n+\n+\tret = xt_register_target(&offload_tg_reg);\n+\tif (ret)\n+\t\tgoto cleanup2;\n+\n+\treturn 0;\n+\n+cleanup2:\n+\tnf_flow_table_free(&flowtable[1].ft);\n+cleanup:\n+\tnf_flow_table_free(&flowtable[0].ft);\n+\treturn ret;\n+}\n+\n+static void __exit xt_flowoffload_tg_exit(void)\n+{\n+\txt_unregister_target(&offload_tg_reg);\n+\tunregister_netdevice_notifier(&flow_offload_netdev_notifier);\n+\tnf_flow_table_free(&flowtable[0].ft);\n+\tnf_flow_table_free(&flowtable[1].ft);\n+}\n+\n+MODULE_LICENSE(\"GPL\");\n+module_init(xt_flowoffload_tg_init);\n+module_exit(xt_flowoffload_tg_exit);\n--- a/net/netfilter/nf_flow_table_core.c\n+++ b/net/netfilter/nf_flow_table_core.c\n@@ -7,7 +7,6 @@\n #include <linux/netdevice.h>\n #include <net/ip.h>\n #include <net/ip6_route.h>\n-#include <net/netfilter/nf_tables.h>\n #include <net/netfilter/nf_flow_table.h>\n #include <net/netfilter/nf_conntrack.h>\n #include <net/netfilter/nf_conntrack_core.h>\n@@ -399,8 +398,7 @@ flow_offload_lookup(struct nf_flowtable\n }\n EXPORT_SYMBOL_GPL(flow_offload_lookup);\n \n-static int\n-nf_flow_table_iterate(struct nf_flowtable *flow_table,\n+int nf_flow_table_iterate(struct nf_flowtable *flow_table,\n \t\t      void (*iter)(struct flow_offload *flow, void *data),\n \t\t      void *data)\n {\n@@ -432,6 +430,7 @@ nf_flow_table_iterate(struct nf_flowtabl\n \n \treturn err;\n }\n+EXPORT_SYMBOL_GPL(nf_flow_table_iterate);\n \n static bool flow_offload_stale_dst(struct flow_offload_tuple *tuple)\n {\n--- /dev/null\n+++ b/include/uapi/linux/netfilter/xt_FLOWOFFLOAD.h\n@@ -0,0 +1,17 @@\n+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */\n+#ifndef _XT_FLOWOFFLOAD_H\n+#define _XT_FLOWOFFLOAD_H\n+\n+#include <linux/types.h>\n+\n+enum {\n+\tXT_FLOWOFFLOAD_HW\t= 1 << 0,\n+\n+\tXT_FLOWOFFLOAD_MASK\t= XT_FLOWOFFLOAD_HW\n+};\n+\n+struct xt_flowoffload_target_info {\n+\t__u32 flags;\n+};\n+\n+#endif /* _XT_FLOWOFFLOAD_H */\n--- a/include/net/netfilter/nf_flow_table.h\n+++ b/include/net/netfilter/nf_flow_table.h\n@@ -275,6 +275,10 @@ void nf_flow_table_free(struct nf_flowta\n \n void flow_offload_teardown(struct flow_offload *flow);\n \n+int nf_flow_table_iterate(struct nf_flowtable *flow_table,\n+\t\t\t  void (*iter)(struct flow_offload *flow, void *data),\n+\t\t\t  void *data);\n+\n void nf_flow_snat_port(const struct flow_offload *flow,\n \t\t       struct sk_buff *skb, unsigned int thoff,\n \t\t       u8 protocol, enum flow_offload_tuple_dir dir);\n"
  },
  {
    "path": "target/linux/generic/hack-5.15/651-wireless_mesh_header.patch",
    "content": "From 6d3bc769657b0ee7c7506dad9911111c4226a7ea Mon Sep 17 00:00:00 2001\nFrom: Imre Kaloz <kaloz@openwrt.org>\nDate: Fri, 7 Jul 2017 17:21:05 +0200\nSubject: mac80211: increase wireless mesh header size\n\nlede-commit 3d4466cfd8f75f717efdb1f96fdde3c70d865fc1\nSigned-off-by: Imre Kaloz <kaloz@openwrt.org>\n---\n include/linux/netdevice.h | 4 ++--\n 1 file changed, 2 insertions(+), 2 deletions(-)\n\n--- a/include/linux/netdevice.h\n+++ b/include/linux/netdevice.h\n@@ -145,8 +145,8 @@ static inline bool dev_xmit_complete(int\n \n #if defined(CONFIG_HYPERV_NET)\n # define LL_MAX_HEADER 128\n-#elif defined(CONFIG_WLAN) || IS_ENABLED(CONFIG_AX25)\n-# if defined(CONFIG_MAC80211_MESH)\n+#elif defined(CONFIG_WLAN) || IS_ENABLED(CONFIG_AX25) || 1\n+# if defined(CONFIG_MAC80211_MESH) || 1\n #  define LL_MAX_HEADER 128\n # else\n #  define LL_MAX_HEADER 96\n"
  },
  {
    "path": "target/linux/generic/hack-5.15/660-fq_codel_defaults.patch",
    "content": "From a6ccb238939b25851474a279b20367fd24a0e816 Mon Sep 17 00:00:00 2001\nFrom: Felix Fietkau <nbd@nbd.name>\nDate: Fri, 7 Jul 2017 17:21:53 +0200\nSubject:  hack: net: fq_codel: tune defaults for small devices\n\nAssume that x86_64 devices always have a big memory and do not need this \noptimization compared to devices with only 32 MB or 64 MB RAM.\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n net/sched/sch_fq_codel.c | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/net/sched/sch_fq_codel.c\n+++ b/net/sched/sch_fq_codel.c\n@@ -469,7 +469,11 @@ static int fq_codel_init(struct Qdisc *s\n \n \tsch->limit = 10*1024;\n \tq->flows_cnt = 1024;\n+#ifdef CONFIG_X86_64\n \tq->memory_limit = 32 << 20; /* 32 MBytes */\n+#else\n+\tq->memory_limit = 4 << 20; /* 4 MBytes */\n+#endif\n \tq->drop_batch_size = 64;\n \tq->quantum = psched_mtu(qdisc_dev(sch));\n \tINIT_LIST_HEAD(&q->new_flows);\n"
  },
  {
    "path": "target/linux/generic/hack-5.15/661-kernel-ct-size-the-hashtable-more-adequately.patch",
    "content": "From 804fbb3f2ec9283f7b778e057a68bfff440a0be6 Mon Sep 17 00:00:00 2001\nFrom: Rui Salvaterra <rsalvaterra@gmail.com>\nDate: Wed, 30 Mar 2022 22:51:55 +0100\nSubject: [PATCH] kernel: ct: size the hashtable more adequately\n\nTo set the default size of the connection tracking hash table, a divider of\n16384 becomes inadequate for a router handling lots of connections. Divide by\n2048 instead, making the default size scale better with the available RAM.\n\nSigned-off-by: Rui Salvaterra <rsalvaterra@gmail.com>\n---\n net/netfilter/nf_conntrack_core.c | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/net/netfilter/nf_conntrack_core.c\n+++ b/net/netfilter/nf_conntrack_core.c\n@@ -2727,7 +2727,7 @@ int nf_conntrack_init_start(void)\n \n \tif (!nf_conntrack_htable_size) {\n \t\tnf_conntrack_htable_size\n-\t\t\t= (((nr_pages << PAGE_SHIFT) / 16384)\n+\t\t\t= (((nr_pages << PAGE_SHIFT) / 2048)\n \t\t\t   / sizeof(struct hlist_head));\n \t\tif (BITS_PER_LONG >= 64 &&\n \t\t    nr_pages > (4 * (1024 * 1024 * 1024 / PAGE_SIZE)))\n"
  },
  {
    "path": "target/linux/generic/hack-5.15/700-swconfig_switch_drivers.patch",
    "content": "From 36e516290611e613aa92996cb4339561452695b4 Mon Sep 17 00:00:00 2001\nFrom: Felix Fietkau <nbd@nbd.name>\nDate: Fri, 7 Jul 2017 17:24:23 +0200\nSubject: net: swconfig: adds openwrt switch layer\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n drivers/net/phy/Kconfig   | 83 +++++++++++++++++++++++++++++++++++++++++++++++\n drivers/net/phy/Makefile  | 15 +++++++++\n include/uapi/linux/Kbuild |  1 +\n 3 files changed, 99 insertions(+)\n\n--- a/drivers/net/phy/Kconfig\n+++ b/drivers/net/phy/Kconfig\n@@ -61,6 +61,80 @@ config SFP\n \tdepends on HWMON || HWMON=n\n \tselect MDIO_I2C\n \n+comment \"Switch configuration API + drivers\"\n+\n+config SWCONFIG\n+\ttristate \"Switch configuration API\"\n+\thelp\n+\t  Switch configuration API using netlink. This allows\n+\t  you to configure the VLAN features of certain switches.\n+\n+config SWCONFIG_LEDS\n+\tbool \"Switch LED trigger support\"\n+\tdepends on (SWCONFIG && LEDS_TRIGGERS)\n+\n+config ADM6996_PHY\n+\ttristate \"Driver for ADM6996 switches\"\n+\tselect SWCONFIG\n+\thelp\n+\t  Currently supports the ADM6996FC and ADM6996M switches.\n+\t  Support for FC is very limited.\n+\n+config AR8216_PHY\n+\ttristate \"Driver for Atheros AR8216 switches\"\n+\tselect SWCONFIG\n+\n+config AR8216_PHY_LEDS\n+\tbool \"Atheros AR8216 switch LED support\"\n+\tdepends on (AR8216_PHY && LEDS_CLASS)\n+\n+source \"drivers/net/phy/b53/Kconfig\"\n+\n+config IP17XX_PHY\n+\ttristate \"Driver for IC+ IP17xx switches\"\n+\tselect SWCONFIG\n+\n+config PSB6970_PHY\n+\ttristate \"Lantiq XWAY Tantos (PSB6970) Ethernet switch\"\n+\tselect SWCONFIG\n+\tselect ETHERNET_PACKET_MANGLE\n+\n+config RTL8306_PHY\n+\ttristate \"Driver for Realtek RTL8306S switches\"\n+\tselect SWCONFIG\n+\n+config RTL8366_SMI\n+\ttristate \"Driver for the RTL8366 SMI interface\"\n+\tdepends on GPIOLIB\n+\thelp\n+\t  This module implements the SMI interface protocol which is used\n+\t  by some RTL8366 ethernet switch devices via the generic GPIO API.\n+\n+if RTL8366_SMI\n+\n+config RTL8366_SMI_DEBUG_FS\n+\tbool \"RTL8366 SMI interface debugfs support\"\n+        depends on DEBUG_FS\n+        default n\n+\n+config RTL8366S_PHY\n+\ttristate \"Driver for the Realtek RTL8366S switch\"\n+\tselect SWCONFIG\n+\n+config RTL8366RB_PHY\n+\ttristate \"Driver for the Realtek RTL8366RB switch\"\n+\tselect SWCONFIG\n+\n+config RTL8367_PHY\n+\ttristate \"Driver for the Realtek RTL8367R/M switches\"\n+\tselect SWCONFIG\n+\n+config RTL8367B_PHY\n+\ttristate \"Driver fot the Realtek RTL8367R-VB switch\"\n+\tselect SWCONFIG\n+\n+endif # RTL8366_SMI\n+\n comment \"MII PHY device drivers\"\n \n config AMD_PHY\n--- a/drivers/net/phy/Makefile\n+++ b/drivers/net/phy/Makefile\n@@ -24,6 +24,19 @@ libphy-$(CONFIG_LED_TRIGGER_PHY)\t+= phy_\n obj-$(CONFIG_PHYLINK)\t\t+= phylink.o\n obj-$(CONFIG_PHYLIB)\t\t+= libphy.o\n \n+obj-$(CONFIG_SWCONFIG)\t\t+= swconfig.o\n+obj-$(CONFIG_ADM6996_PHY)\t+= adm6996.o\n+obj-$(CONFIG_AR8216_PHY)\t+= ar8216.o ar8327.o\n+obj-$(CONFIG_SWCONFIG_B53)\t+= b53/\n+obj-$(CONFIG_IP17XX_PHY)\t+= ip17xx.o\n+obj-$(CONFIG_PSB6970_PHY)\t+= psb6970.o\n+obj-$(CONFIG_RTL8306_PHY)\t+= rtl8306.o\n+obj-$(CONFIG_RTL8366_SMI)\t+= rtl8366_smi.o\n+obj-$(CONFIG_RTL8366S_PHY)\t+= rtl8366s.o\n+obj-$(CONFIG_RTL8366RB_PHY)\t+= rtl8366rb.o\n+obj-$(CONFIG_RTL8367_PHY)\t+= rtl8367.o\n+obj-$(CONFIG_RTL8367B_PHY)\t+= rtl8367b.o\n+\n obj-$(CONFIG_NETWORK_PHY_TIMESTAMPING) += mii_timestamper.o\n \n obj-$(CONFIG_SFP)\t\t+= sfp.o\n--- a/include/linux/platform_data/b53.h\n+++ b/include/linux/platform_data/b53.h\n@@ -29,6 +29,9 @@ struct b53_platform_data {\n \tu32 chip_id;\n \tu16 enabled_ports;\n \n+\t/* allow to specify an ethX alias */\n+\tconst char *alias;\n+\n \t/* only used by MMAP'd driver */\n \tunsigned big_endian:1;\n \tvoid __iomem *regs;\n"
  },
  {
    "path": "target/linux/generic/hack-5.15/710-net-dsa-mv88e6xxx-default-VID-1.patch",
    "content": "--- a/drivers/net/dsa/mv88e6xxx/chip.c\n+++ b/drivers/net/dsa/mv88e6xxx/chip.c\n@@ -2321,6 +2321,7 @@ static int mv88e6xxx_port_fdb_add(struct\n \tstruct mv88e6xxx_chip *chip = ds->priv;\n \tint err;\n \n+\tvid = vid ? : 1;\n \tmv88e6xxx_reg_lock(chip);\n \terr = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,\n \t\t\t\t\t   MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);\n@@ -2335,6 +2336,7 @@ static int mv88e6xxx_port_fdb_del(struct\n \tstruct mv88e6xxx_chip *chip = ds->priv;\n \tint err;\n \n+\tvid = vid ? : 1;\n \tmv88e6xxx_reg_lock(chip);\n \terr = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 0);\n \tmv88e6xxx_reg_unlock(chip);\n"
  },
  {
    "path": "target/linux/generic/hack-5.15/711-net-dsa-mv88e6xxx-disable-ATU-violation.patch",
    "content": "--- a/drivers/net/dsa/mv88e6xxx/chip.c\n+++ b/drivers/net/dsa/mv88e6xxx/chip.c\n@@ -2983,6 +2983,9 @@ static int mv88e6xxx_setup_port(struct m\n \telse\n \t\treg = 1 << port;\n \n+\t/* Disable ATU member violation interrupt */\n+\treg |= MV88E6XXX_PORT_ASSOC_VECTOR_IGNORE_WRONG;\n+\n \terr = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR,\n \t\t\t\t   reg);\n \tif (err)\n"
  },
  {
    "path": "target/linux/generic/hack-5.15/720-net-phy-add-aqr-phys.patch",
    "content": "From: Birger Koblitz <git@birger-koblitz.de>\nDate: Sun, 5 Sep 2021 15:13:10 +0200\nSubject: [PATCH] kernel: Add AQR113C and AQR813 support\n\nThis hack adds support for the Aquantia 4th generation, 10GBit\nPHYs AQR113C and AQR813.\n\nSigned-off-by: Birger Koblitz <git@birger-koblitz.de>\n\n--- a/drivers/net/phy/aquantia_main.c\n+++ b/drivers/net/phy/aquantia_main.c\n@@ -20,8 +20,10 @@\n #define PHY_ID_AQR105\t0x03a1b4a2\n #define PHY_ID_AQR106\t0x03a1b4d0\n #define PHY_ID_AQR107\t0x03a1b4e0\n+#define PHY_ID_AQR113C\t0x31c31c12\n #define PHY_ID_AQCS109\t0x03a1b5c2\n #define PHY_ID_AQR405\t0x03a1b4b0\n+#define PHY_ID_AQR813\t0x31c31cb2\n \n #define MDIO_PHYXS_VEND_IF_STATUS\t\t0xe812\n #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK\tGENMASK(7, 3)\n@@ -359,6 +361,49 @@ static int aqr107_read_rate(struct phy_d\n \treturn 0;\n }\n \n+static int aqr113c_read_status(struct phy_device *phydev)\n+{\n+\tint val, ret;\n+\n+\tret = aqr_read_status(phydev);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tif (!phydev->link || phydev->autoneg == AUTONEG_DISABLE)\n+\t\treturn 0;\n+\n+\t// On AQR113C, the speed returned by aqr_read_status is wrong\n+\taqr107_read_rate(phydev);\n+\n+\tval = phy_read_mmd(phydev, MDIO_MMD_PHYXS, MDIO_PHYXS_VEND_IF_STATUS);\n+\tif (val < 0)\n+\t\treturn val;\n+\n+\tswitch (FIELD_GET(MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK, val)) {\n+\tcase MDIO_PHYXS_VEND_IF_STATUS_TYPE_KR:\n+\t\tphydev->interface = PHY_INTERFACE_MODE_10GKR;\n+\t\tbreak;\n+\tcase MDIO_PHYXS_VEND_IF_STATUS_TYPE_XFI:\n+\t\tphydev->interface = PHY_INTERFACE_MODE_10GBASER;\n+\t\tbreak;\n+\tcase MDIO_PHYXS_VEND_IF_STATUS_TYPE_USXGMII:\n+\t\tphydev->interface = PHY_INTERFACE_MODE_USXGMII;\n+\t\tbreak;\n+\tcase MDIO_PHYXS_VEND_IF_STATUS_TYPE_SGMII:\n+\t\tphydev->interface = PHY_INTERFACE_MODE_SGMII;\n+\t\tbreak;\n+\tcase MDIO_PHYXS_VEND_IF_STATUS_TYPE_OCSGMII:\n+\t\tphydev->interface = PHY_INTERFACE_MODE_2500BASEX;\n+\t\tbreak;\n+\tdefault:\n+\t\tphydev->interface = PHY_INTERFACE_MODE_NA;\n+\t\tbreak;\n+\t}\n+\n+\t/* Read downshifted rate from vendor register */\n+\treturn aqr107_read_rate(phydev);\n+}\n+\n static int aqr107_read_status(struct phy_device *phydev)\n {\n \tint val, ret;\n@@ -489,7 +534,7 @@ static void aqr107_chip_info(struct phy_\n \tbuild_id = FIELD_GET(VEND1_GLOBAL_RSVD_STAT1_FW_BUILD_ID, val);\n \tprov_id = FIELD_GET(VEND1_GLOBAL_RSVD_STAT1_PROV_ID, val);\n \n-\tphydev_dbg(phydev, \"FW %u.%u, Build %u, Provisioning %u\\n\",\n+\tphydev_info(phydev, \"FW %u.%u, Build %u, Provisioning %u\\n\",\n \t\t   fw_major, fw_minor, build_id, prov_id);\n }\n \n@@ -661,6 +706,24 @@ static struct phy_driver aqr_driver[] =\n \t.link_change_notify = aqr107_link_change_notify,\n },\n {\n+\tPHY_ID_MATCH_MODEL(PHY_ID_AQR113C),\n+\t.name\t\t= \"Aquantia AQR113C\",\n+\t.probe\t\t= aqr107_probe,\n+\t.config_init\t= aqr107_config_init,\n+\t.config_aneg    = aqr_config_aneg,\n+\t.config_intr\t= aqr_config_intr,\n+\t.handle_interrupt = aqr_handle_interrupt,\n+\t.read_status\t= aqr113c_read_status,\n+\t.get_tunable    = aqr107_get_tunable,\n+\t.set_tunable    = aqr107_set_tunable,\n+\t.suspend\t= aqr107_suspend,\n+\t.resume\t\t= aqr107_resume,\n+\t.get_sset_count\t= aqr107_get_sset_count,\n+\t.get_strings\t= aqr107_get_strings,\n+\t.get_stats\t= aqr107_get_stats,\n+\t.link_change_notify = aqr107_link_change_notify,\n+},\n+{\n \tPHY_ID_MATCH_MODEL(PHY_ID_AQCS109),\n \t.name\t\t= \"Aquantia AQCS109\",\n \t.probe\t\t= aqr107_probe,\n@@ -686,6 +749,24 @@ static struct phy_driver aqr_driver[] =\n \t.handle_interrupt = aqr_handle_interrupt,\n \t.read_status\t= aqr_read_status,\n },\n+{\n+\tPHY_ID_MATCH_MODEL(PHY_ID_AQR813),\n+\t.name\t\t= \"Aquantia AQR813\",\n+\t.probe\t\t= aqr107_probe,\n+\t.config_init\t= aqr107_config_init,\n+\t.config_aneg    = aqr_config_aneg,\n+\t.config_intr\t= aqr_config_intr,\n+\t.handle_interrupt = aqr_handle_interrupt,\n+\t.read_status\t= aqr113c_read_status,\n+\t.get_tunable    = aqr107_get_tunable,\n+\t.set_tunable    = aqr107_set_tunable,\n+\t.suspend\t= aqr107_suspend,\n+\t.resume\t\t= aqr107_resume,\n+\t.get_sset_count\t= aqr107_get_sset_count,\n+\t.get_strings\t= aqr107_get_strings,\n+\t.get_stats\t= aqr107_get_stats,\n+\t.link_change_notify = aqr107_link_change_notify,\n+},\n };\n \n module_phy_driver(aqr_driver);\n@@ -696,8 +777,10 @@ static struct mdio_device_id __maybe_unu\n \t{ PHY_ID_MATCH_MODEL(PHY_ID_AQR105) },\n \t{ PHY_ID_MATCH_MODEL(PHY_ID_AQR106) },\n \t{ PHY_ID_MATCH_MODEL(PHY_ID_AQR107) },\n+\t{ PHY_ID_MATCH_MODEL(PHY_ID_AQR113C) },\n \t{ PHY_ID_MATCH_MODEL(PHY_ID_AQCS109) },\n \t{ PHY_ID_MATCH_MODEL(PHY_ID_AQR405) },\n+\t{ PHY_ID_MATCH_MODEL(PHY_ID_AQR813) },\n \t{ }\n };\n \n"
  },
  {
    "path": "target/linux/generic/hack-5.15/721-net-add-packet-mangeling.patch",
    "content": "From ffe387740bbe88dd88bbe04d6375902708003d6e Mon Sep 17 00:00:00 2001\nFrom: Felix Fietkau <nbd@nbd.name>\nDate: Fri, 7 Jul 2017 17:25:00 +0200\nSubject: net: add packet mangeling\n\nar8216 switches have a hardware bug, which renders normal 802.1q support\nunusable. Packet mangling is required to fix up the vlan for incoming\npackets.\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n include/linux/netdevice.h | 11 +++++++++++\n include/linux/skbuff.h    | 14 ++++----------\n net/Kconfig               |  6 ++++++\n net/core/dev.c            | 20 +++++++++++++++-----\n net/core/skbuff.c         | 17 +++++++++++++++++\n net/ethernet/eth.c        |  6 ++++++\n 6 files changed, 59 insertions(+), 15 deletions(-)\n\n--- a/include/linux/netdevice.h\n+++ b/include/linux/netdevice.h\n@@ -1655,6 +1655,10 @@ enum netdev_priv_flags {\n \tIFF_TX_SKB_NO_LINEAR\t\t= 1<<31,\n };\n \n+enum netdev_extra_priv_flags {\n+\tIFF_NO_IP_ALIGN\t\t\t= 1<<0,\n+};\n+\n #define IFF_802_1Q_VLAN\t\t\tIFF_802_1Q_VLAN\n #define IFF_EBRIDGE\t\t\tIFF_EBRIDGE\n #define IFF_BONDING\t\t\tIFF_BONDING\n@@ -1687,6 +1691,7 @@ enum netdev_priv_flags {\n #define IFF_L3MDEV_RX_HANDLER\t\tIFF_L3MDEV_RX_HANDLER\n #define IFF_LIVE_RENAME_OK\t\tIFF_LIVE_RENAME_OK\n #define IFF_TX_SKB_NO_LINEAR\t\tIFF_TX_SKB_NO_LINEAR\n+#define IFF_NO_IP_ALIGN\t\t\tIFF_NO_IP_ALIGN\n \n /* Specifies the type of the struct net_device::ml_priv pointer */\n enum netdev_ml_priv_type {\n@@ -1988,6 +1993,7 @@ struct net_device {\n \t/* Read-mostly cache-line for fast-path access */\n \tunsigned int\t\tflags;\n \tunsigned int\t\tpriv_flags;\n+\tunsigned int\t\textra_priv_flags;\n \tconst struct net_device_ops *netdev_ops;\n \tint\t\t\tifindex;\n \tunsigned short\t\tgflags;\n@@ -2048,6 +2054,11 @@ struct net_device {\n \tconst struct tlsdev_ops *tlsdev_ops;\n #endif\n \n+#ifdef CONFIG_ETHERNET_PACKET_MANGLE\n+\tvoid (*eth_mangle_rx)(struct net_device *dev, struct sk_buff *skb);\n+\tstruct sk_buff *(*eth_mangle_tx)(struct net_device *dev, struct sk_buff *skb);\n+#endif\n+\n \tconst struct header_ops *header_ops;\n \n \tunsigned char\t\toperstate;\n@@ -2122,6 +2133,10 @@ struct net_device {\n \tstruct mctp_dev __rcu\t*mctp_ptr;\n #endif\n \n+#ifdef CONFIG_ETHERNET_PACKET_MANGLE\n+\tvoid\t\t\t*phy_ptr; /* PHY device specific data */\n+#endif\n+\n /*\n  * Cache lines mostly used on receive path (including eth_type_trans())\n  */\n--- a/include/linux/skbuff.h\n+++ b/include/linux/skbuff.h\n@@ -2771,6 +2771,10 @@ static inline int pskb_trim(struct sk_bu\n \treturn (len < skb->len) ? __pskb_trim(skb, len) : 0;\n }\n \n+extern struct sk_buff *__netdev_alloc_skb_ip_align(struct net_device *dev,\n+\t\tunsigned int length, gfp_t gfp);\n+\n+\n /**\n  *\tpskb_trim_unique - remove end from a paged unique (not cloned) buffer\n  *\t@skb: buffer to alter\n@@ -2921,16 +2925,6 @@ static inline struct sk_buff *dev_alloc_\n }\n \n \n-static inline struct sk_buff *__netdev_alloc_skb_ip_align(struct net_device *dev,\n-\t\tunsigned int length, gfp_t gfp)\n-{\n-\tstruct sk_buff *skb = __netdev_alloc_skb(dev, length + NET_IP_ALIGN, gfp);\n-\n-\tif (NET_IP_ALIGN && skb)\n-\t\tskb_reserve(skb, NET_IP_ALIGN);\n-\treturn skb;\n-}\n-\n static inline struct sk_buff *netdev_alloc_skb_ip_align(struct net_device *dev,\n \t\tunsigned int length)\n {\n--- a/net/Kconfig\n+++ b/net/Kconfig\n@@ -26,6 +26,12 @@ menuconfig NET\n \n if NET\n \n+config ETHERNET_PACKET_MANGLE\n+\tbool\n+\thelp\n+\t  This option can be selected by phy drivers that need to mangle\n+\t  packets going in or out of an ethernet device.\n+\n config WANT_COMPAT_NETLINK_MESSAGES\n \tbool\n \thelp\n--- a/net/core/dev.c\n+++ b/net/core/dev.c\n@@ -3582,6 +3582,11 @@ static int xmit_one(struct sk_buff *skb,\n \tif (dev_nit_active(dev))\n \t\tdev_queue_xmit_nit(skb, dev);\n \n+#ifdef CONFIG_ETHERNET_PACKET_MANGLE\n+\tif (dev->eth_mangle_tx && !(skb = dev->eth_mangle_tx(dev, skb)))\n+\t\treturn NETDEV_TX_OK;\n+#endif\n+\n \tlen = skb->len;\n \tPRANDOM_ADD_NOISE(skb, dev, txq, len + jiffies);\n \ttrace_net_dev_start_xmit(skb, dev);\n--- a/net/core/skbuff.c\n+++ b/net/core/skbuff.c\n@@ -61,6 +61,7 @@\n #include <linux/if_vlan.h>\n #include <linux/mpls.h>\n #include <linux/kcov.h>\n+#include <linux/if.h>\n \n #include <net/protocol.h>\n #include <net/dst.h>\n@@ -602,6 +603,22 @@ skb_fail:\n }\n EXPORT_SYMBOL(__napi_alloc_skb);\n \n+struct sk_buff *__netdev_alloc_skb_ip_align(struct net_device *dev,\n+\t\tunsigned int length, gfp_t gfp)\n+{\n+\tstruct sk_buff *skb = __netdev_alloc_skb(dev, length + NET_IP_ALIGN, gfp);\n+\n+#ifdef CONFIG_ETHERNET_PACKET_MANGLE\n+\tif (dev && (dev->extra_priv_flags & IFF_NO_IP_ALIGN))\n+\t\treturn skb;\n+#endif\n+\n+\tif (NET_IP_ALIGN && skb)\n+\t\tskb_reserve(skb, NET_IP_ALIGN);\n+\treturn skb;\n+}\n+EXPORT_SYMBOL(__netdev_alloc_skb_ip_align);\n+\n void skb_add_rx_frag(struct sk_buff *skb, int i, struct page *page, int off,\n \t\t     int size, unsigned int truesize)\n {\n--- a/net/ethernet/eth.c\n+++ b/net/ethernet/eth.c\n@@ -170,6 +170,12 @@ __be16 eth_type_trans(struct sk_buff *sk\n \tconst struct ethhdr *eth;\n \n \tskb->dev = dev;\n+\n+#ifdef CONFIG_ETHERNET_PACKET_MANGLE\n+\tif (dev->eth_mangle_rx)\n+\t\tdev->eth_mangle_rx(dev, skb);\n+#endif\n+\n \tskb_reset_mac_header(skb);\n \n \teth = (struct ethhdr *)skb->data;\n"
  },
  {
    "path": "target/linux/generic/hack-5.15/722-net-phy-aquantia-enable-AQR112-and-AQR412.patch",
    "content": "From 5f62951fba63a9f9cfff564209426bdea5fcc371 Mon Sep 17 00:00:00 2001\nFrom: Alex Marginean <alexandru.marginean@nxp.com>\nDate: Tue, 27 Aug 2019 15:16:56 +0300\nSubject: [PATCH] drivers: net: phy: aquantia: enable AQR112 and AQR412\n\nAdds support for AQR112 and AQR412 which is mostly based on existing code\nwith the addition of code configuring the protocol on system side.\nThis allows changing the system side protocol without having to deploy a\ndifferent firmware on the PHY.\n\nSigned-off-by: Alex Marginean <alexandru.marginean@nxp.com>\n---\n drivers/net/phy/aquantia_main.c | 88 +++++++++++++++++++++++++++++++++++++++++\n 1 file changed, 88 insertions(+)\n\n--- a/drivers/net/phy/aquantia_main.c\n+++ b/drivers/net/phy/aquantia_main.c\n@@ -20,9 +20,11 @@\n #define PHY_ID_AQR105\t0x03a1b4a2\n #define PHY_ID_AQR106\t0x03a1b4d0\n #define PHY_ID_AQR107\t0x03a1b4e0\n+#define PHY_ID_AQR112\t0x03a1b662\n #define PHY_ID_AQR113C\t0x31c31c12\n #define PHY_ID_AQCS109\t0x03a1b5c2\n #define PHY_ID_AQR405\t0x03a1b4b0\n+#define PHY_ID_AQR412\t0x03a1b712\n #define PHY_ID_AQR813\t0x31c31cb2\n \n #define MDIO_PHYXS_VEND_IF_STATUS\t\t0xe812\n@@ -124,6 +126,29 @@\n #define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL2\tBIT(1)\n #define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL3\tBIT(0)\n \n+/* registers in MDIO_MMD_VEND1 region */\n+#define AQUANTIA_VND1_GLOBAL_SC\t\t\t0x000\n+#define  AQUANTIA_VND1_GLOBAL_SC_LP\t\tBIT(0xb)\n+\n+/* global start rate, the protocol associated with this speed is used by default\n+ * on SI.\n+ */\n+#define AQUANTIA_VND1_GSTART_RATE\t\t0x31a\n+#define  AQUANTIA_VND1_GSTART_RATE_OFF\t\t0\n+#define  AQUANTIA_VND1_GSTART_RATE_100M\t\t1\n+#define  AQUANTIA_VND1_GSTART_RATE_1G\t\t2\n+#define  AQUANTIA_VND1_GSTART_RATE_10G\t\t3\n+#define  AQUANTIA_VND1_GSTART_RATE_2_5G\t\t4\n+#define  AQUANTIA_VND1_GSTART_RATE_5G\t\t5\n+\n+/* SYSCFG registers for 100M, 1G, 2.5G, 5G, 10G */\n+#define AQUANTIA_VND1_GSYSCFG_BASE\t\t0x31b\n+#define AQUANTIA_VND1_GSYSCFG_100M\t\t0\n+#define AQUANTIA_VND1_GSYSCFG_1G\t\t1\n+#define AQUANTIA_VND1_GSYSCFG_2_5G\t\t2\n+#define AQUANTIA_VND1_GSYSCFG_5G\t\t3\n+#define AQUANTIA_VND1_GSYSCFG_10G\t\t4\n+\n struct aqr107_hw_stat {\n \tconst char *name;\n \tint reg;\n@@ -244,6 +269,51 @@ static int aqr_config_aneg(struct phy_de\n \treturn genphy_c45_check_and_restart_aneg(phydev, changed);\n }\n \n+static struct {\n+\tu16 syscfg;\n+\tint cnt;\n+\tu16 start_rate;\n+} aquantia_syscfg[PHY_INTERFACE_MODE_MAX] = {\n+\t[PHY_INTERFACE_MODE_SGMII] =      {0x04b, AQUANTIA_VND1_GSYSCFG_1G,\n+\t\t\t\t\t   AQUANTIA_VND1_GSTART_RATE_1G},\n+\t[PHY_INTERFACE_MODE_2500BASEX] = {0x144, AQUANTIA_VND1_GSYSCFG_2_5G,\n+\t\t\t\t\t   AQUANTIA_VND1_GSTART_RATE_2_5G},\n+\t[PHY_INTERFACE_MODE_XGMII] =      {0x100, AQUANTIA_VND1_GSYSCFG_10G,\n+\t\t\t\t\t   AQUANTIA_VND1_GSTART_RATE_10G},\n+\t[PHY_INTERFACE_MODE_USXGMII] =    {0x080, AQUANTIA_VND1_GSYSCFG_10G,\n+\t\t\t\t\t   AQUANTIA_VND1_GSTART_RATE_10G},\n+};\n+\n+/* Sets up protocol on system side before calling aqr_config_aneg */\n+static int aqr_config_aneg_set_prot(struct phy_device *phydev)\n+{\n+\tint if_type = phydev->interface;\n+\tint i;\n+\n+\tif (!aquantia_syscfg[if_type].cnt)\n+\t\treturn 0;\n+\n+\t/* set PHY in low power mode so we can configure protocols */\n+\tphy_write_mmd(phydev, MDIO_MMD_VEND1, AQUANTIA_VND1_GLOBAL_SC,\n+\t\t      AQUANTIA_VND1_GLOBAL_SC_LP);\n+\tmdelay(10);\n+\n+\t/* set the default rate to enable the SI link */\n+\tphy_write_mmd(phydev, MDIO_MMD_VEND1, AQUANTIA_VND1_GSTART_RATE,\n+\t\t      aquantia_syscfg[if_type].start_rate);\n+\n+\tfor (i = 0; i <= aquantia_syscfg[if_type].cnt; i++)\n+\t\tphy_write_mmd(phydev, MDIO_MMD_VEND1,\n+\t\t\t      AQUANTIA_VND1_GSYSCFG_BASE + i,\n+\t\t\t      aquantia_syscfg[if_type].syscfg);\n+\n+\t/* wake PHY back up */\n+\tphy_write_mmd(phydev, MDIO_MMD_VEND1, AQUANTIA_VND1_GLOBAL_SC, 0);\n+\tmdelay(10);\n+\n+\treturn aqr_config_aneg(phydev);\n+}\n+\n static int aqr_config_intr(struct phy_device *phydev)\n {\n \tbool en = phydev->interrupts == PHY_INTERRUPT_ENABLED;\n@@ -767,6 +837,30 @@ static struct phy_driver aqr_driver[] =\n \t.get_stats\t= aqr107_get_stats,\n \t.link_change_notify = aqr107_link_change_notify,\n },\n+{\n+\tPHY_ID_MATCH_MODEL(PHY_ID_AQR112),\n+\t.name\t\t= \"Aquantia AQR112\",\n+\t.probe\t\t= aqr107_probe,\n+\t.config_aneg\t= aqr_config_aneg_set_prot,\n+\t.config_intr\t= aqr_config_intr,\n+\t.handle_interrupt = aqr_handle_interrupt,\n+\t.read_status\t= aqr107_read_status,\n+\t.get_sset_count\t= aqr107_get_sset_count,\n+\t.get_strings\t= aqr107_get_strings,\n+\t.get_stats\t= aqr107_get_stats,\n+},\n+{\n+\tPHY_ID_MATCH_MODEL(PHY_ID_AQR412),\n+\t.name\t\t= \"Aquantia AQR412\",\n+\t.probe\t\t= aqr107_probe,\n+\t.config_aneg\t= aqr_config_aneg_set_prot,\n+\t.config_intr\t= aqr_config_intr,\n+\t.handle_interrupt = aqr_handle_interrupt,\n+\t.read_status\t= aqr107_read_status,\n+\t.get_sset_count\t= aqr107_get_sset_count,\n+\t.get_strings\t= aqr107_get_strings,\n+\t.get_stats\t= aqr107_get_stats,\n+},\n };\n \n module_phy_driver(aqr_driver);\n@@ -777,9 +871,11 @@ static struct mdio_device_id __maybe_unu\n \t{ PHY_ID_MATCH_MODEL(PHY_ID_AQR105) },\n \t{ PHY_ID_MATCH_MODEL(PHY_ID_AQR106) },\n \t{ PHY_ID_MATCH_MODEL(PHY_ID_AQR107) },\n+\t{ PHY_ID_MATCH_MODEL(PHY_ID_AQR112) },\n \t{ PHY_ID_MATCH_MODEL(PHY_ID_AQR113C) },\n \t{ PHY_ID_MATCH_MODEL(PHY_ID_AQCS109) },\n \t{ PHY_ID_MATCH_MODEL(PHY_ID_AQR405) },\n+\t{ PHY_ID_MATCH_MODEL(PHY_ID_AQR412) },\n \t{ PHY_ID_MATCH_MODEL(PHY_ID_AQR813) },\n \t{ }\n };\n"
  },
  {
    "path": "target/linux/generic/hack-5.15/723-net-phy-aquantia-fix-system-side-protocol-mi.patch",
    "content": "From 5f008cb22f60da4e10375f22266c1a4e20b1252e Mon Sep 17 00:00:00 2001\nFrom: Alex Marginean <alexandru.marginean@nxp.com>\nDate: Fri, 20 Sep 2019 18:22:52 +0300\nSubject: [PATCH] drivers: net: phy: aquantia: fix system side protocol\n misconfiguration\n\nDo not set up protocols for speeds that are not supported by FW.  Enabling\nthese protocols leads to link issues on system side.\n\nSigned-off-by: Alex Marginean <alexandru.marginean@nxp.com>\n---\n drivers/net/phy/aquantia_main.c | 8 +++++++-\n 1 file changed, 7 insertions(+), 1 deletion(-)\n\n--- a/drivers/net/phy/aquantia_main.c\n+++ b/drivers/net/phy/aquantia_main.c\n@@ -302,10 +302,16 @@ static int aqr_config_aneg_set_prot(stru\n \tphy_write_mmd(phydev, MDIO_MMD_VEND1, AQUANTIA_VND1_GSTART_RATE,\n \t\t      aquantia_syscfg[if_type].start_rate);\n \n-\tfor (i = 0; i <= aquantia_syscfg[if_type].cnt; i++)\n+\tfor (i = 0; i <= aquantia_syscfg[if_type].cnt; i++) {\n+\t\tu16 reg = phy_read_mmd(phydev, MDIO_MMD_VEND1,\n+\t\t\t\t       AQUANTIA_VND1_GSYSCFG_BASE + i);\n+\t\tif (!reg)\n+\t\t\tcontinue;\n+\n \t\tphy_write_mmd(phydev, MDIO_MMD_VEND1,\n \t\t\t      AQUANTIA_VND1_GSYSCFG_BASE + i,\n \t\t\t      aquantia_syscfg[if_type].syscfg);\n+\t}\n \n \t/* wake PHY back up */\n \tphy_write_mmd(phydev, MDIO_MMD_VEND1, AQUANTIA_VND1_GLOBAL_SC, 0);\n"
  },
  {
    "path": "target/linux/generic/hack-5.15/724-net-phy-aquantia-Add-AQR113-driver-support.patch",
    "content": "From 2e677e4ae8f8330f68013163b060d0fda3a43095 Mon Sep 17 00:00:00 2001\nFrom: \"Langer, Thomas\" <tlanger@maxlinear.com>\nDate: Fri, 9 Jul 2021 17:36:46 +0200\nSubject: [PATCH] PONRTSYS-8842: aquantia: Add AQR113 driver support\n\nAdd a new entry for AQR113 PHY_ID\n---\n drivers/net/phy/aquantia_main.c | 10 ++++++++++\n 1 file changed, 10 insertions(+)\n\n--- a/drivers/net/phy/aquantia_main.c\n+++ b/drivers/net/phy/aquantia_main.c\n@@ -21,6 +21,7 @@\n #define PHY_ID_AQR106\t0x03a1b4d0\n #define PHY_ID_AQR107\t0x03a1b4e0\n #define PHY_ID_AQR112\t0x03a1b662\n+#define PHY_ID_AQR113\t0x31c31c40\n #define PHY_ID_AQR113C\t0x31c31c12\n #define PHY_ID_AQCS109\t0x03a1b5c2\n #define PHY_ID_AQR405\t0x03a1b4b0\n@@ -856,6 +857,14 @@ static struct phy_driver aqr_driver[] =\n \t.get_stats\t= aqr107_get_stats,\n },\n {\n+\tPHY_ID_MATCH_MODEL(PHY_ID_AQR113),\n+\t.name\t\t= \"Aquantia AQR113\",\n+\t.config_aneg\t= aqr_config_aneg,\n+\t.config_intr\t= aqr_config_intr,\n+\t.handle_interrupt = aqr_handle_interrupt,\n+\t.read_status\t= aqr107_read_status,\n+},\n+{\n \tPHY_ID_MATCH_MODEL(PHY_ID_AQR412),\n \t.name\t\t= \"Aquantia AQR412\",\n \t.probe\t\t= aqr107_probe,\n@@ -878,6 +887,7 @@ static struct mdio_device_id __maybe_unu\n \t{ PHY_ID_MATCH_MODEL(PHY_ID_AQR106) },\n \t{ PHY_ID_MATCH_MODEL(PHY_ID_AQR107) },\n \t{ PHY_ID_MATCH_MODEL(PHY_ID_AQR112) },\n+\t{ PHY_ID_MATCH_MODEL(PHY_ID_AQR113) },\n \t{ PHY_ID_MATCH_MODEL(PHY_ID_AQR113C) },\n \t{ PHY_ID_MATCH_MODEL(PHY_ID_AQCS109) },\n \t{ PHY_ID_MATCH_MODEL(PHY_ID_AQR405) },\n"
  },
  {
    "path": "target/linux/generic/hack-5.15/725-net-phy-aquantia-add-PHY_IDs-for-AQR112-variants.patch",
    "content": "From 3b92ee7b7899b6beffb2b484c58326e36612a873 Mon Sep 17 00:00:00 2001\nFrom: Daniel Golle <daniel@makrotopia.org>\nDate: Thu, 23 Dec 2021 14:52:56 +0000\nSubject: [PATCH] net: phy: aquantia: add PHY_ID for AQR112R\n\nAs advised by Ian Chang this PHY is used in Puzzle devices.\n\nSigned-off-by: Daniel Golle <daniel@makrotopia.org>\n---\n drivers/net/phy/aquantia_main.c | 10 ++++++++++\n 1 file changed, 10 insertions(+)\n\n--- a/drivers/net/phy/aquantia_main.c\n+++ b/drivers/net/phy/aquantia_main.c\n@@ -21,6 +21,8 @@\n #define PHY_ID_AQR106\t0x03a1b4d0\n #define PHY_ID_AQR107\t0x03a1b4e0\n #define PHY_ID_AQR112\t0x03a1b662\n+#define PHY_ID_AQR112C\t0x03a1b790\n+#define PHY_ID_AQR112R\t0x31c31d12\n #define PHY_ID_AQR113\t0x31c31c40\n #define PHY_ID_AQR113C\t0x31c31c12\n #define PHY_ID_AQCS109\t0x03a1b5c2\n@@ -857,6 +859,30 @@ static struct phy_driver aqr_driver[] =\n \t.get_stats\t= aqr107_get_stats,\n },\n {\n+\tPHY_ID_MATCH_MODEL(PHY_ID_AQR112C),\n+\t.name\t\t= \"Aquantia AQR112C\",\n+\t.probe\t\t= aqr107_probe,\n+\t.config_aneg\t= aqr_config_aneg_set_prot,\n+\t.config_intr\t= aqr_config_intr,\n+\t.handle_interrupt = aqr_handle_interrupt,\n+\t.read_status\t= aqr107_read_status,\n+\t.get_sset_count\t= aqr107_get_sset_count,\n+\t.get_strings\t= aqr107_get_strings,\n+\t.get_stats\t= aqr107_get_stats,\n+},\n+{\n+\tPHY_ID_MATCH_MODEL(PHY_ID_AQR112R),\n+\t.name\t\t= \"Aquantia AQR112R\",\n+\t.probe\t\t= aqr107_probe,\n+\t.config_aneg\t= aqr_config_aneg_set_prot,\n+\t.config_intr\t= aqr_config_intr,\n+\t.handle_interrupt = aqr_handle_interrupt,\n+\t.read_status\t= aqr107_read_status,\n+\t.get_sset_count\t= aqr107_get_sset_count,\n+\t.get_strings\t= aqr107_get_strings,\n+\t.get_stats\t= aqr107_get_stats,\n+},\n+{\n \tPHY_ID_MATCH_MODEL(PHY_ID_AQR113),\n \t.name\t\t= \"Aquantia AQR113\",\n \t.config_aneg\t= aqr_config_aneg,\n@@ -887,6 +913,8 @@ static struct mdio_device_id __maybe_unu\n \t{ PHY_ID_MATCH_MODEL(PHY_ID_AQR106) },\n \t{ PHY_ID_MATCH_MODEL(PHY_ID_AQR107) },\n \t{ PHY_ID_MATCH_MODEL(PHY_ID_AQR112) },\n+\t{ PHY_ID_MATCH_MODEL(PHY_ID_AQR112C) },\n+\t{ PHY_ID_MATCH_MODEL(PHY_ID_AQR112R) },\n \t{ PHY_ID_MATCH_MODEL(PHY_ID_AQR113) },\n \t{ PHY_ID_MATCH_MODEL(PHY_ID_AQR113C) },\n \t{ PHY_ID_MATCH_MODEL(PHY_ID_AQCS109) },\n"
  },
  {
    "path": "target/linux/generic/hack-5.15/760-net-usb-r8152-add-LED-configuration-from-OF.patch",
    "content": "From 82985725e071f2a5735052f18e109a32aeac3a0b Mon Sep 17 00:00:00 2001\nFrom: David Bauer <mail@david-bauer.net>\nDate: Sun, 26 Jul 2020 02:38:31 +0200\nSubject: [PATCH] net: usb: r8152: add LED configuration from OF\n\nThis adds the ability to configure the LED configuration register using\nOF. This way, the correct value for board specific LED configuration can\nbe determined.\n\nSigned-off-by: David Bauer <mail@david-bauer.net>\n---\n drivers/net/usb/r8152.c | 23 +++++++++++++++++++++++\n 1 file changed, 23 insertions(+)\n\n--- a/drivers/net/usb/r8152.c\n+++ b/drivers/net/usb/r8152.c\n@@ -11,6 +11,7 @@\n #include <linux/mii.h>\n #include <linux/ethtool.h>\n #include <linux/usb.h>\n+#include <linux/of.h>\n #include <linux/crc32.h>\n #include <linux/if_vlan.h>\n #include <linux/uaccess.h>\n@@ -6852,6 +6853,22 @@ static void rtl_tally_reset(struct r8152\n \tocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data);\n }\n \n+static int r8152_led_configuration(struct r8152 *tp)\n+{\n+\tu32 led_data;\n+\tint ret;\n+\n+\tret = of_property_read_u32(tp->udev->dev.of_node, \"realtek,led-data\",\n+\t\t\t\t\t\t\t\t&led_data);\n+\n+\tif (ret)\n+\t\treturn ret;\n+\t\n+\tocp_write_word(tp, MCU_TYPE_PLA, PLA_LEDSEL, led_data);\n+\n+\treturn 0;\n+}\n+\n static void r8152b_init(struct r8152 *tp)\n {\n \tu32 ocp_data;\n@@ -6893,6 +6910,8 @@ static void r8152b_init(struct r8152 *tp\n \tocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);\n \tocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);\n \tocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);\n+\n+\tr8152_led_configuration(tp);\n }\n \n static void r8153_init(struct r8152 *tp)\n@@ -7033,6 +7052,8 @@ static void r8153_init(struct r8152 *tp)\n \t\ttp->coalesce = COALESCE_SLOW;\n \t\tbreak;\n \t}\n+\n+\tr8152_led_configuration(tp);\n }\n \n static void r8153b_init(struct r8152 *tp)\n@@ -7115,6 +7136,8 @@ static void r8153b_init(struct r8152 *tp\n \trtl_tally_reset(tp);\n \n \ttp->coalesce = 15000;\t/* 15 us */\n+\n+\tr8152_led_configuration(tp);\n }\n \n static void r8153c_init(struct r8152 *tp)\n"
  },
  {
    "path": "target/linux/generic/hack-5.15/761-dt-bindings-net-add-RTL8152-binding-documentation.patch",
    "content": "From 3ee05f4aa64fc86af3be5bc176ba5808de9260a7 Mon Sep 17 00:00:00 2001\nFrom: David Bauer <mail@david-bauer.net>\nDate: Sun, 26 Jul 2020 15:30:33 +0200\nSubject: [PATCH] dt-bindings: net: add RTL8152 binding documentation\n\nAdd binding documentation for the Realtek RTL8152 / RTL8153 USB ethernet\nadapters.\n\nSigned-off-by: David Bauer <mail@david-bauer.net>\n---\n .../bindings/net/realtek,rtl8152.yaml         | 36 +++++++++++++++++++\n 1 file changed, 36 insertions(+)\n create mode 100644 Documentation/devicetree/bindings/net/realtek,rtl8152.yaml\n\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/net/realtek,rtl8152.yaml\n@@ -0,0 +1,36 @@\n+# SPDX-License-Identifier: GPL-2.0\n+%YAML 1.2\n+---\n+$id: http://devicetree.org/schemas/net/realtek,rtl8152.yaml#\n+$schema: http://devicetree.org/meta-schemas/core.yaml#\n+\n+title: Realtek RTL8152/RTL8153 series USB ethernet\n+\n+maintainers:\n+  - David Bauer <mail@david-bauer.net>\n+\n+properties:\n+  compatible:\n+    oneOf:\n+      - items:\n+          - enum:\n+              - realtek,rtl8152\n+              - realtek,rtl8153\n+\n+  reg:\n+    description: The device number on the USB bus\n+\n+  realtek,led-data:\n+    description: Value to be written to the LED configuration register.\n+\n+required:\n+  - compatible\n+  - reg\n+\n+examples:\n+  - |\n+    usb-eth@2 {\n+      compatible = \"realtek,rtl8153\";\n+      reg = <2>;\n+      realtek,led-data = <0x87>;\n+    };\n\\ No newline at end of file\n"
  },
  {
    "path": "target/linux/generic/hack-5.15/773-bgmac-add-srab-switch.patch",
    "content": "From 3cb240533ab787899dc7f17aa7d6c5b4810e2e58 Mon Sep 17 00:00:00 2001\nFrom: Hauke Mehrtens <hauke@hauke-m.de>\nDate: Fri, 7 Jul 2017 17:26:01 +0200\nSubject: bcm53xx: bgmac: use srab switch driver\n\nuse the srab switch driver on these SoCs.\n\nSigned-off-by: Hauke Mehrtens <hauke@hauke-m.de>\n---\n drivers/net/ethernet/broadcom/bgmac-bcma.c |  1 +\n drivers/net/ethernet/broadcom/bgmac.c      | 24 ++++++++++++++++++++++++\n drivers/net/ethernet/broadcom/bgmac.h      |  4 ++++\n 3 files changed, 29 insertions(+)\n\n--- a/drivers/net/ethernet/broadcom/bgmac-bcma.c\n+++ b/drivers/net/ethernet/broadcom/bgmac-bcma.c\n@@ -280,6 +280,7 @@ static int bgmac_probe(struct bcma_devic\n \t\tbgmac->feature_flags |= BGMAC_FEAT_CLKCTLST;\n \t\tbgmac->feature_flags |= BGMAC_FEAT_NO_RESET;\n \t\tbgmac->feature_flags |= BGMAC_FEAT_FORCE_SPEED_2500;\n+\t\tbgmac->feature_flags |= BGMAC_FEAT_SRAB;\n \t\tbreak;\n \tdefault:\n \t\tbgmac->feature_flags |= BGMAC_FEAT_CLKCTLST;\n--- a/drivers/net/ethernet/broadcom/bgmac.c\n+++ b/drivers/net/ethernet/broadcom/bgmac.c\n@@ -12,6 +12,7 @@\n #include <linux/bcma/bcma.h>\n #include <linux/etherdevice.h>\n #include <linux/interrupt.h>\n+#include <linux/platform_data/b53.h>\n #include <linux/bcm47xx_nvram.h>\n #include <linux/phy.h>\n #include <linux/phy_fixed.h>\n@@ -1408,6 +1409,17 @@ static const struct ethtool_ops bgmac_et\n \t.set_link_ksettings     = phy_ethtool_set_link_ksettings,\n };\n \n+static struct b53_platform_data bgmac_b53_pdata = {\n+};\n+\n+static struct platform_device bgmac_b53_dev = {\n+\t.name\t\t= \"b53-srab-switch\",\n+\t.id\t\t= -1,\n+\t.dev\t\t= {\n+\t\t.platform_data = &bgmac_b53_pdata,\n+\t},\n+};\n+\n /**************************************************\n  * MII\n  **************************************************/\n@@ -1542,6 +1554,14 @@ int bgmac_enet_probe(struct bgmac *bgmac\n \t/* Omit FCS from max MTU size */\n \tnet_dev->max_mtu = BGMAC_RX_MAX_FRAME_SIZE - ETH_FCS_LEN;\n \n+\tif ((bgmac->feature_flags & BGMAC_FEAT_SRAB) && !bgmac_b53_pdata.regs) {\n+\t\tbgmac_b53_pdata.regs = ioremap(0x18007000, 0x1000);\n+\n+\t\terr = platform_device_register(&bgmac_b53_dev);\n+\t\tif (!err)\n+\t\t\tbgmac->b53_device = &bgmac_b53_dev;\n+\t}\n+\n \terr = register_netdev(bgmac->net_dev);\n \tif (err) {\n \t\tdev_err(bgmac->dev, \"Cannot register net device\\n\");\n@@ -1564,6 +1584,10 @@ EXPORT_SYMBOL_GPL(bgmac_enet_probe);\n \n void bgmac_enet_remove(struct bgmac *bgmac)\n {\n+\tif (bgmac->b53_device)\n+\t\tplatform_device_unregister(&bgmac_b53_dev);\n+\tbgmac->b53_device = NULL;\n+\n \tunregister_netdev(bgmac->net_dev);\n \tphy_disconnect(bgmac->net_dev->phydev);\n \tnetif_napi_del(&bgmac->napi);\n--- a/drivers/net/ethernet/broadcom/bgmac.h\n+++ b/drivers/net/ethernet/broadcom/bgmac.h\n@@ -390,6 +390,7 @@\n #define BGMAC_FEAT_CC4_IF_SW_TYPE_RGMII\tBIT(18)\n #define BGMAC_FEAT_CC7_IF_TYPE_RGMII\tBIT(19)\n #define BGMAC_FEAT_IDM_MASK\t\tBIT(20)\n+#define BGMAC_FEAT_SRAB\t\t\tBIT(21)\n \n struct bgmac_slot_info {\n \tunion {\n@@ -495,6 +496,9 @@ struct bgmac {\n \tvoid (*cmn_maskset32)(struct bgmac *bgmac, u16 offset, u32 mask,\n \t\t\t      u32 set);\n \tint (*phy_connect)(struct bgmac *bgmac);\n+\n+\t/* platform device for associated switch */\n+\tstruct platform_device *b53_device;\n };\n \n struct bgmac *bgmac_alloc(struct device *dev);\n"
  },
  {
    "path": "target/linux/generic/hack-5.15/780-usb-net-MeigLink_modem_support.patch",
    "content": "--- a/drivers/net/usb/qmi_wwan.c\n+++ b/drivers/net/usb/qmi_wwan.c\n@@ -1085,6 +1085,7 @@ static const struct usb_device_id produc\n \t{QMI_MATCH_FF_FF_FF(0x2c7c, 0x0512)},\t/* Quectel EG12/EM12 */\n \t{QMI_MATCH_FF_FF_FF(0x2c7c, 0x0620)},\t/* Quectel EM160R-GL */\n \t{QMI_MATCH_FF_FF_FF(0x2c7c, 0x0800)},\t/* Quectel RM500Q-GL */\n+\t{QMI_MATCH_FF_FF_FF(0x05c6, 0xf601)},   /* MeigLink SLM750 */\n \n \t/* 3. Combined interface devices matching on interface number */\n \t{QMI_FIXED_INTF(0x0408, 0xea42, 4)},\t/* Yota / Megafon M100-1 */\n--- a/drivers/usb/serial/option.c\n+++ b/drivers/usb/serial/option.c\n@@ -243,6 +243,8 @@ static void option_instat_callback(struc\n #define UBLOX_PRODUCT_R6XX\t\t\t0x90fa\n /* These Yuga products use Qualcomm's vendor ID */\n #define YUGA_PRODUCT_CLM920_NC5\t\t\t0x9625\n+/* These MeigLink products use Qualcomm's vendor ID */\n+#define MEIGLINK_PRODUCT_SLM750\t\t\t0xf601\n \n #define QUECTEL_VENDOR_ID\t\t\t0x2c7c\n /* These Quectel products use Quectel's vendor ID */\n@@ -1129,6 +1131,11 @@ static const struct usb_device_id option\n \t{ USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_EG95, 0xff, 0, 0) },\n \t{ USB_DEVICE(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_BG96),\n \t  .driver_info = RSVD(4) },\n+\t/* Meiglink products using Qualcomm vendor ID */\n+\t// Works OK. In case of some issues check macros that are used by Quectel Products\n+\t{ USB_DEVICE_AND_INTERFACE_INFO(QUALCOMM_VENDOR_ID, MEIGLINK_PRODUCT_SLM750, 0xff, 0xff, 0xff),\n+\t  .driver_info = NUMEP2 },\n+\t{ USB_DEVICE_AND_INTERFACE_INFO(QUALCOMM_VENDOR_ID, MEIGLINK_PRODUCT_SLM750, 0xff, 0, 0) },\n \t{ USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_EP06, 0xff, 0xff, 0xff),\n \t  .driver_info = RSVD(1) | RSVD(2) | RSVD(3) | RSVD(4) | NUMEP2 },\n \t{ USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_EP06, 0xff, 0, 0) },\n"
  },
  {
    "path": "target/linux/generic/hack-5.15/800-GPIO-add-named-gpio-exports.patch",
    "content": "From cc809a441d8f2924f785eb863dfa6aef47a25b0b Mon Sep 17 00:00:00 2001\nFrom: John Crispin <blogic@openwrt.org>\nDate: Tue, 12 Aug 2014 20:49:27 +0200\nSubject: [PATCH 30/36] GPIO: add named gpio exports\n\nSigned-off-by: John Crispin <blogic@openwrt.org>\n--- a/drivers/gpio/gpiolib-of.c\n+++ b/drivers/gpio/gpiolib-of.c\n@@ -19,6 +19,8 @@\n #include <linux/pinctrl/pinctrl.h>\n #include <linux/slab.h>\n #include <linux/gpio/machine.h>\n+#include <linux/init.h>\n+#include <linux/platform_device.h>\n \n #include \"gpiolib.h\"\n #include \"gpiolib-of.h\"\n@@ -1052,3 +1054,72 @@ void of_gpio_dev_init(struct gpio_chip *\n \telse\n \t\tgc->of_node = gdev->dev.of_node;\n }\n+\n+#ifdef CONFIG_GPIO_SYSFS\n+\n+static struct of_device_id gpio_export_ids[] = {\n+\t{ .compatible = \"gpio-export\" },\n+\t{ /* sentinel */ }\n+};\n+\n+static int of_gpio_export_probe(struct platform_device *pdev)\n+{\n+\tstruct device_node *np = pdev->dev.of_node;\n+\tstruct device_node *cnp;\n+\tu32 val;\n+\tint nb = 0;\n+\n+\tfor_each_child_of_node(np, cnp) {\n+\t\tconst char *name = NULL;\n+\t\tint gpio;\n+\t\tbool dmc;\n+\t\tint max_gpio = 1;\n+\t\tint i;\n+\n+\t\tof_property_read_string(cnp, \"gpio-export,name\", &name);\n+\n+\t\tif (!name)\n+\t\t\tmax_gpio = of_gpio_count(cnp);\n+\n+\t\tfor (i = 0; i < max_gpio; i++) {\n+\t\t\tunsigned flags = 0;\n+\t\t\tenum of_gpio_flags of_flags;\n+\n+\t\t\tgpio = of_get_gpio_flags(cnp, i, &of_flags);\n+\t\t\tif (!gpio_is_valid(gpio))\n+\t\t\t\treturn gpio;\n+\n+\t\t\tif (of_flags == OF_GPIO_ACTIVE_LOW)\n+\t\t\t\tflags |= GPIOF_ACTIVE_LOW;\n+\n+\t\t\tif (!of_property_read_u32(cnp, \"gpio-export,output\", &val))\n+\t\t\t\tflags |= val ? GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW;\n+\t\t\telse\n+\t\t\t\tflags |= GPIOF_IN;\n+\n+\t\t\tif (devm_gpio_request_one(&pdev->dev, gpio, flags, name ? name : of_node_full_name(np)))\n+\t\t\t\tcontinue;\n+\n+\t\t\tdmc = of_property_read_bool(cnp, \"gpio-export,direction_may_change\");\n+\t\t\tgpio_export_with_name(gpio, dmc, name);\n+\t\t\tnb++;\n+\t\t}\n+\t}\n+\n+\tdev_info(&pdev->dev, \"%d gpio(s) exported\\n\", nb);\n+\n+\treturn 0;\n+}\n+\n+static struct platform_driver gpio_export_driver = {\n+\t.driver\t\t= {\n+\t\t.name\t\t= \"gpio-export\",\n+\t\t.owner\t= THIS_MODULE,\n+\t\t.of_match_table\t= of_match_ptr(gpio_export_ids),\n+\t},\n+\t.probe\t\t= of_gpio_export_probe,\n+};\n+\n+module_platform_driver(gpio_export_driver);\n+\n+#endif\n--- a/include/asm-generic/gpio.h\n+++ b/include/asm-generic/gpio.h\n@@ -125,6 +125,12 @@ static inline int gpio_export(unsigned g\n \treturn gpiod_export(gpio_to_desc(gpio), direction_may_change);\n }\n \n+int __gpiod_export(struct gpio_desc *desc, bool direction_may_change, const char *name);\n+static inline int gpio_export_with_name(unsigned gpio, bool direction_may_change, const char *name)\n+{\n+\treturn __gpiod_export(gpio_to_desc(gpio), direction_may_change, name);\n+}\n+\n static inline int gpio_export_link(struct device *dev, const char *name,\n \t\t\t\t   unsigned gpio)\n {\n--- a/include/linux/gpio/consumer.h\n+++ b/include/linux/gpio/consumer.h\n@@ -715,6 +715,7 @@ static inline void devm_acpi_dev_remove_\n \n #if IS_ENABLED(CONFIG_GPIOLIB) && IS_ENABLED(CONFIG_GPIO_SYSFS)\n \n+int _gpiod_export(struct gpio_desc *desc, bool direction_may_change, const char *name);\n int gpiod_export(struct gpio_desc *desc, bool direction_may_change);\n int gpiod_export_link(struct device *dev, const char *name,\n \t\t      struct gpio_desc *desc);\n@@ -722,6 +723,13 @@ void gpiod_unexport(struct gpio_desc *de\n \n #else  /* CONFIG_GPIOLIB && CONFIG_GPIO_SYSFS */\n \n+static inline int _gpiod_export(struct gpio_desc *desc,\n+\t\t\t       bool direction_may_change,\n+\t\t\t       const char *name)\n+{\n+\treturn -ENOSYS;\n+}\n+\n static inline int gpiod_export(struct gpio_desc *desc,\n \t\t\t       bool direction_may_change)\n {\n--- a/drivers/gpio/gpiolib-sysfs.c\n+++ b/drivers/gpio/gpiolib-sysfs.c\n@@ -561,7 +561,7 @@ static struct class gpio_class = {\n  *\n  * Returns zero on success, else an error.\n  */\n-int gpiod_export(struct gpio_desc *desc, bool direction_may_change)\n+int __gpiod_export(struct gpio_desc *desc, bool direction_may_change, const char *name)\n {\n \tstruct gpio_chip\t*chip;\n \tstruct gpio_device\t*gdev;\n@@ -623,6 +623,8 @@ int gpiod_export(struct gpio_desc *desc,\n \toffset = gpio_chip_hwgpio(desc);\n \tif (chip->names && chip->names[offset])\n \t\tioname = chip->names[offset];\n+\tif (name)\n+\t\tioname = name;\n \n \tdev = device_create_with_groups(&gpio_class, &gdev->dev,\n \t\t\t\t\tMKDEV(0, 0), data, gpio_groups,\n@@ -644,6 +646,12 @@ err_unlock:\n \tgpiod_dbg(desc, \"%s: status %d\\n\", __func__, status);\n \treturn status;\n }\n+EXPORT_SYMBOL_GPL(__gpiod_export);\n+\n+int gpiod_export(struct gpio_desc *desc, bool direction_may_change)\n+{\n+\treturn __gpiod_export(desc, direction_may_change, NULL);\n+}\n EXPORT_SYMBOL_GPL(gpiod_export);\n \n static int match_export(struct device *dev, const void *desc)\n"
  },
  {
    "path": "target/linux/generic/hack-5.15/901-debloat_sock_diag.patch",
    "content": "From 3b6115d6b57a263bdc8c9b1df273bd4a7955eead Mon Sep 17 00:00:00 2001\nFrom: Felix Fietkau <nbd@nbd.name>\nDate: Sat, 8 Jul 2017 08:16:31 +0200\nSubject: debloat: add some debloat patches, strip down procfs and make O_DIRECT support optional, saves ~15K after lzma on MIPS\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n net/Kconfig         | 3 +++\n net/core/Makefile   | 3 ++-\n net/core/sock.c     | 2 ++\n net/ipv4/Kconfig    | 1 +\n net/netlink/Kconfig | 1 +\n net/packet/Kconfig  | 1 +\n net/unix/Kconfig    | 1 +\n 7 files changed, 11 insertions(+), 1 deletion(-)\n\n--- a/net/Kconfig\n+++ b/net/Kconfig\n@@ -104,6 +104,9 @@ source \"net/mptcp/Kconfig\"\n \n endif # if INET\n \n+config SOCK_DIAG\n+\tbool\n+\n config NETWORK_SECMARK\n \tbool \"Security Marking\"\n \thelp\n--- a/net/core/Makefile\n+++ b/net/core/Makefile\n@@ -10,9 +10,10 @@ obj-$(CONFIG_SYSCTL) += sysctl_net_core.\n \n obj-y\t\t     += dev.o dev_addr_lists.o dst.o netevent.o \\\n \t\t\tneighbour.o rtnetlink.o utils.o link_watch.o filter.o \\\n-\t\t\tsock_diag.o dev_ioctl.o tso.o sock_reuseport.o \\\n+ \t\t\tdev_ioctl.o tso.o sock_reuseport.o \\\n \t\t\tfib_notifier.o xdp.o flow_offload.o\n \n+obj-$(CONFIG_SOCK_DIAG) += sock_diag.o\n obj-y += net-sysfs.o\n obj-$(CONFIG_PAGE_POOL) += page_pool.o\n obj-$(CONFIG_PROC_FS) += net-procfs.o\n--- a/net/core/sock.c\n+++ b/net/core/sock.c\n@@ -114,6 +114,7 @@\n #include <linux/memcontrol.h>\n #include <linux/prefetch.h>\n #include <linux/compat.h>\n+#include <linux/cookie.h>\n \n #include <linux/uaccess.h>\n \n@@ -143,6 +144,7 @@\n \n static DEFINE_MUTEX(proto_list_mutex);\n static LIST_HEAD(proto_list);\n+DEFINE_COOKIE(sock_cookie);\n \n static void sock_inuse_add(struct net *net, int val);\n \n@@ -545,6 +547,18 @@ discard_and_relse:\n }\n EXPORT_SYMBOL(__sk_receive_skb);\n \n+u64 __sock_gen_cookie(struct sock *sk)\n+{\n+\twhile (1) {\n+\t\tu64 res = atomic64_read(&sk->sk_cookie);\n+\n+\t\tif (res)\n+\t\t\treturn res;\n+\t\tres = gen_cookie_next(&sock_cookie);\n+\t\tatomic64_cmpxchg(&sk->sk_cookie, 0, res);\n+\t}\n+}\n+\n INDIRECT_CALLABLE_DECLARE(struct dst_entry *ip6_dst_check(struct dst_entry *,\n \t\t\t\t\t\t\t  u32));\n INDIRECT_CALLABLE_DECLARE(struct dst_entry *ipv4_dst_check(struct dst_entry *,\n@@ -1983,9 +1997,11 @@ static void __sk_free(struct sock *sk)\n \tif (likely(sk->sk_net_refcnt))\n \t\tsock_inuse_add(sock_net(sk), -1);\n \n+#ifdef CONFIG_SOCK_DIAG\n \tif (unlikely(sk->sk_net_refcnt && sock_diag_has_destroy_listeners(sk)))\n \t\tsock_diag_broadcast_destroy(sk);\n \telse\n+#endif\n \t\tsk_destruct(sk);\n }\n \n--- a/net/core/sock_diag.c\n+++ b/net/core/sock_diag.c\n@@ -11,7 +11,6 @@\n #include <linux/tcp.h>\n #include <linux/workqueue.h>\n #include <linux/nospec.h>\n-#include <linux/cookie.h>\n #include <linux/inet_diag.h>\n #include <linux/sock_diag.h>\n \n@@ -20,20 +19,6 @@ static int (*inet_rcv_compat)(struct sk_\n static DEFINE_MUTEX(sock_diag_table_mutex);\n static struct workqueue_struct *broadcast_wq;\n \n-DEFINE_COOKIE(sock_cookie);\n-\n-u64 __sock_gen_cookie(struct sock *sk)\n-{\n-\twhile (1) {\n-\t\tu64 res = atomic64_read(&sk->sk_cookie);\n-\n-\t\tif (res)\n-\t\t\treturn res;\n-\t\tres = gen_cookie_next(&sock_cookie);\n-\t\tatomic64_cmpxchg(&sk->sk_cookie, 0, res);\n-\t}\n-}\n-\n int sock_diag_check_cookie(struct sock *sk, const __u32 *cookie)\n {\n \tu64 res;\n--- a/net/ipv4/Kconfig\n+++ b/net/ipv4/Kconfig\n@@ -414,6 +414,7 @@ config INET_TUNNEL\n \n config INET_DIAG\n \ttristate \"INET: socket monitoring interface\"\n+\tselect SOCK_DIAG\n \tdefault y\n \thelp\n \t  Support for INET (TCP, DCCP, etc) socket monitoring interface used by\n--- a/net/netlink/Kconfig\n+++ b/net/netlink/Kconfig\n@@ -5,6 +5,7 @@\n \n config NETLINK_DIAG\n \ttristate \"NETLINK: socket monitoring interface\"\n+\tselect SOCK_DIAG\n \tdefault n\n \thelp\n \t  Support for NETLINK socket monitoring interface used by the ss tool.\n--- a/net/packet/Kconfig\n+++ b/net/packet/Kconfig\n@@ -19,6 +19,7 @@ config PACKET\n config PACKET_DIAG\n \ttristate \"Packet: sockets monitoring interface\"\n \tdepends on PACKET\n+\tselect SOCK_DIAG\n \tdefault n\n \thelp\n \t  Support for PF_PACKET sockets monitoring interface used by the ss tool.\n--- a/net/unix/Kconfig\n+++ b/net/unix/Kconfig\n@@ -33,6 +33,7 @@ config\tAF_UNIX_OOB\n config UNIX_DIAG\n \ttristate \"UNIX: socket monitoring interface\"\n \tdepends on UNIX\n+\tselect SOCK_DIAG\n \tdefault n\n \thelp\n \t  Support for UNIX socket monitoring interface used by the ss tool.\n"
  },
  {
    "path": "target/linux/generic/hack-5.15/902-debloat_proc.patch",
    "content": "From 9e3f1d0805b2d919904dd9a4ff0d956314cc3cba Mon Sep 17 00:00:00 2001\nFrom: Felix Fietkau <nbd@nbd.name>\nDate: Sat, 8 Jul 2017 08:20:09 +0200\nSubject: debloat: procfs\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n fs/locks.c               |  2 ++\n fs/proc/Kconfig          |  5 +++++\n fs/proc/consoles.c       |  3 +++\n fs/proc/proc_tty.c       | 11 ++++++++++-\n include/net/snmp.h       | 18 +++++++++++++++++-\n ipc/msg.c                |  3 +++\n ipc/sem.c                |  2 ++\n ipc/shm.c                |  2 ++\n ipc/util.c               |  3 +++\n kernel/exec_domain.c     |  2 ++\n kernel/irq/proc.c        |  9 +++++++++\n kernel/time/timer_list.c |  2 ++\n mm/vmalloc.c             |  2 ++\n mm/vmstat.c              |  8 +++++---\n net/8021q/vlanproc.c     |  6 ++++++\n net/core/net-procfs.c    | 18 ++++++++++++------\n net/core/sock.c          |  2 ++\n net/ipv4/fib_trie.c      | 18 ++++++++++++------\n net/ipv4/proc.c          |  3 +++\n net/ipv4/route.c         |  3 +++\n 20 files changed, 105 insertions(+), 17 deletions(-)\n\n--- a/fs/locks.c\n+++ b/fs/locks.c\n@@ -2929,6 +2929,8 @@ static const struct seq_operations locks\n \n static int __init proc_locks_init(void)\n {\n+\tif (IS_ENABLED(CONFIG_PROC_STRIPPED))\n+\t\treturn 0;\n \tproc_create_seq_private(\"locks\", 0, NULL, &locks_seq_operations,\n \t\t\tsizeof(struct locks_iterator), NULL);\n \treturn 0;\n--- a/fs/proc/Kconfig\n+++ b/fs/proc/Kconfig\n@@ -100,6 +100,11 @@ config PROC_CHILDREN\n \t  Say Y if you are running any user-space software which takes benefit from\n \t  this interface. For example, rkt is such a piece of software.\n \n+config PROC_STRIPPED\n+\tdefault n\n+\tdepends on EXPERT\n+\tbool \"Strip non-essential /proc functionality to reduce code size\"\n+\n config PROC_PID_ARCH_STATUS\n \tdef_bool n\n \tdepends on PROC_FS\n--- a/fs/proc/consoles.c\n+++ b/fs/proc/consoles.c\n@@ -92,6 +92,9 @@ static const struct seq_operations conso\n \n static int __init proc_consoles_init(void)\n {\n+\tif (IS_ENABLED(CONFIG_PROC_STRIPPED))\n+\t\treturn 0;\n+\n \tproc_create_seq(\"consoles\", 0, NULL, &consoles_op);\n \treturn 0;\n }\n--- a/fs/proc/proc_tty.c\n+++ b/fs/proc/proc_tty.c\n@@ -133,7 +133,10 @@ static const struct seq_operations tty_d\n void proc_tty_register_driver(struct tty_driver *driver)\n {\n \tstruct proc_dir_entry *ent;\n-\t\t\n+\n+\tif (IS_ENABLED(CONFIG_PROC_STRIPPED))\n+\t\treturn;\n+\n \tif (!driver->driver_name || driver->proc_entry ||\n \t    !driver->ops->proc_show)\n \t\treturn;\n@@ -150,6 +153,9 @@ void proc_tty_unregister_driver(struct t\n {\n \tstruct proc_dir_entry *ent;\n \n+\tif (IS_ENABLED(CONFIG_PROC_STRIPPED))\n+\t\treturn;\n+\n \tent = driver->proc_entry;\n \tif (!ent)\n \t\treturn;\n@@ -164,6 +170,9 @@ void proc_tty_unregister_driver(struct t\n  */\n void __init proc_tty_init(void)\n {\n+\tif (IS_ENABLED(CONFIG_PROC_STRIPPED))\n+\t\treturn;\n+\n \tif (!proc_mkdir(\"tty\", NULL))\n \t\treturn;\n \tproc_mkdir(\"tty/ldisc\", NULL);\t/* Preserved: it's userspace visible */\n--- a/include/net/snmp.h\n+++ b/include/net/snmp.h\n@@ -124,6 +124,21 @@ struct linux_tls_mib {\n #define DECLARE_SNMP_STAT(type, name)\t\\\n \textern __typeof__(type) __percpu *name\n \n+#ifdef CONFIG_PROC_STRIPPED\n+#define __SNMP_STATS_DUMMY(mib)\t\\\n+\tdo { (void) mib->mibs[0]; } while(0)\n+\n+#define __SNMP_INC_STATS(mib, field) __SNMP_STATS_DUMMY(mib)\n+#define SNMP_INC_STATS_ATOMIC_LONG(mib, field) __SNMP_STATS_DUMMY(mib)\n+#define SNMP_INC_STATS(mib, field) __SNMP_STATS_DUMMY(mib)\n+#define SNMP_DEC_STATS(mib, field) __SNMP_STATS_DUMMY(mib)\n+#define __SNMP_ADD_STATS(mib, field, addend) __SNMP_STATS_DUMMY(mib)\n+#define SNMP_ADD_STATS(mib, field, addend) __SNMP_STATS_DUMMY(mib)\n+#define SNMP_UPD_PO_STATS(mib, basefield, addend) __SNMP_STATS_DUMMY(mib)\n+#define __SNMP_UPD_PO_STATS(mib, basefield, addend) __SNMP_STATS_DUMMY(mib)\n+\n+#else\n+\n #define __SNMP_INC_STATS(mib, field)\t\\\n \t\t\t__this_cpu_inc(mib->mibs[field])\n \n@@ -154,8 +169,9 @@ struct linux_tls_mib {\n \t\t__this_cpu_add(ptr[basefield##OCTETS], addend);\t\\\n \t} while (0)\n \n+#endif\n \n-#if BITS_PER_LONG==32\n+#if (BITS_PER_LONG==32) && !defined(CONFIG_PROC_STRIPPED)\n \n #define __SNMP_ADD_STATS64(mib, field, addend) \t\t\t\t\\\n \tdo {\t\t\t\t\t\t\t\t\\\n--- a/ipc/msg.c\n+++ b/ipc/msg.c\n@@ -1350,6 +1350,9 @@ void __init msg_init(void)\n {\n \tmsg_init_ns(&init_ipc_ns);\n \n+\tif (IS_ENABLED(CONFIG_PROC_STRIPPED))\n+\t\treturn;\n+\n \tipc_init_proc_interface(\"sysvipc/msg\",\n \t\t\t\t\"       key      msqid perms      cbytes       qnum lspid lrpid   uid   gid  cuid  cgid      stime      rtime      ctime\\n\",\n \t\t\t\tIPC_MSG_IDS, sysvipc_msg_proc_show);\n--- a/ipc/sem.c\n+++ b/ipc/sem.c\n@@ -268,6 +268,8 @@ void sem_exit_ns(struct ipc_namespace *n\n void __init sem_init(void)\n {\n \tsem_init_ns(&init_ipc_ns);\n+\tif (IS_ENABLED(CONFIG_PROC_STRIPPED))\n+\t\treturn;\n \tipc_init_proc_interface(\"sysvipc/sem\",\n \t\t\t\t\"       key      semid perms      nsems   uid   gid  cuid  cgid      otime      ctime\\n\",\n \t\t\t\tIPC_SEM_IDS, sysvipc_sem_proc_show);\n--- a/ipc/shm.c\n+++ b/ipc/shm.c\n@@ -154,6 +154,8 @@ pure_initcall(ipc_ns_init);\n \n void __init shm_init(void)\n {\n+\tif (IS_ENABLED(CONFIG_PROC_STRIPPED))\n+\t\treturn;\n \tipc_init_proc_interface(\"sysvipc/shm\",\n #if BITS_PER_LONG <= 32\n \t\t\t\t\"       key      shmid perms       size  cpid  lpid nattch   uid   gid  cuid  cgid      atime      dtime      ctime        rss       swap\\n\",\n--- a/ipc/util.c\n+++ b/ipc/util.c\n@@ -141,6 +141,9 @@ void __init ipc_init_proc_interface(cons\n \tstruct proc_dir_entry *pde;\n \tstruct ipc_proc_iface *iface;\n \n+\tif (IS_ENABLED(CONFIG_PROC_STRIPPED))\n+\t\treturn;\n+\n \tiface = kmalloc(sizeof(*iface), GFP_KERNEL);\n \tif (!iface)\n \t\treturn;\n--- a/kernel/exec_domain.c\n+++ b/kernel/exec_domain.c\n@@ -29,6 +29,8 @@ static int execdomains_proc_show(struct\n \n static int __init proc_execdomains_init(void)\n {\n+\tif (IS_ENABLED(CONFIG_PROC_STRIPPED))\n+\t\treturn 0;\n \tproc_create_single(\"execdomains\", 0, NULL, execdomains_proc_show);\n \treturn 0;\n }\n--- a/kernel/irq/proc.c\n+++ b/kernel/irq/proc.c\n@@ -341,6 +341,9 @@ void register_irq_proc(unsigned int irq,\n \tvoid __maybe_unused *irqp = (void *)(unsigned long) irq;\n \tchar name [MAX_NAMELEN];\n \n+\tif (IS_ENABLED(CONFIG_PROC_STRIPPED) && !IS_ENABLED(CONFIG_SMP))\n+\t\treturn;\n+\n \tif (!root_irq_dir || (desc->irq_data.chip == &no_irq_chip))\n \t\treturn;\n \n@@ -394,6 +397,9 @@ void unregister_irq_proc(unsigned int ir\n {\n \tchar name [MAX_NAMELEN];\n \n+\tif (IS_ENABLED(CONFIG_PROC_STRIPPED) && !IS_ENABLED(CONFIG_SMP))\n+\t\treturn;\n+\n \tif (!root_irq_dir || !desc->dir)\n \t\treturn;\n #ifdef CONFIG_SMP\n@@ -432,6 +438,9 @@ void init_irq_proc(void)\n \tunsigned int irq;\n \tstruct irq_desc *desc;\n \n+\tif (IS_ENABLED(CONFIG_PROC_STRIPPED) && !IS_ENABLED(CONFIG_SMP))\n+\t\treturn;\n+\n \t/* create /proc/irq */\n \troot_irq_dir = proc_mkdir(\"irq\", NULL);\n \tif (!root_irq_dir)\n--- a/kernel/time/timer_list.c\n+++ b/kernel/time/timer_list.c\n@@ -350,6 +350,8 @@ static int __init init_timer_list_procfs\n {\n \tstruct proc_dir_entry *pe;\n \n+\tif (IS_ENABLED(CONFIG_PROC_STRIPPED))\n+\t\treturn 0;\n \tpe = proc_create_seq_private(\"timer_list\", 0400, NULL, &timer_list_sops,\n \t\t\tsizeof(struct timer_list_iter), NULL);\n \tif (!pe)\n--- a/mm/vmalloc.c\n+++ b/mm/vmalloc.c\n@@ -3962,6 +3962,8 @@ static const struct seq_operations vmall\n \n static int __init proc_vmalloc_init(void)\n {\n+\tif (IS_ENABLED(CONFIG_PROC_STRIPPED))\n+\t\treturn 0;\n \tif (IS_ENABLED(CONFIG_NUMA))\n \t\tproc_create_seq_private(\"vmallocinfo\", 0400, NULL,\n \t\t\t\t&vmalloc_op,\n--- a/mm/vmstat.c\n+++ b/mm/vmstat.c\n@@ -2083,10 +2083,12 @@ void __init init_mm_internals(void)\n \tstart_shepherd_timer();\n #endif\n #ifdef CONFIG_PROC_FS\n-\tproc_create_seq(\"buddyinfo\", 0444, NULL, &fragmentation_op);\n-\tproc_create_seq(\"pagetypeinfo\", 0400, NULL, &pagetypeinfo_op);\n+\tif (!IS_ENABLED(CONFIG_PROC_STRIPPED)) {\n+\t\tproc_create_seq(\"buddyinfo\", 0444, NULL, &fragmentation_op);\n+\t\tproc_create_seq(\"pagetypeinfo\", 0400, NULL, &pagetypeinfo_op);\n+\t\tproc_create_seq(\"zoneinfo\", 0444, NULL, &zoneinfo_op);\n+\t}\n \tproc_create_seq(\"vmstat\", 0444, NULL, &vmstat_op);\n-\tproc_create_seq(\"zoneinfo\", 0444, NULL, &zoneinfo_op);\n #endif\n }\n \n--- a/net/8021q/vlanproc.c\n+++ b/net/8021q/vlanproc.c\n@@ -93,6 +93,9 @@ void vlan_proc_cleanup(struct net *net)\n {\n \tstruct vlan_net *vn = net_generic(net, vlan_net_id);\n \n+\tif (IS_ENABLED(CONFIG_PROC_STRIPPED))\n+\t\treturn;\n+\n \tif (vn->proc_vlan_conf)\n \t\tremove_proc_entry(name_conf, vn->proc_vlan_dir);\n \n@@ -112,6 +115,9 @@ int __net_init vlan_proc_init(struct net\n {\n \tstruct vlan_net *vn = net_generic(net, vlan_net_id);\n \n+\tif (IS_ENABLED(CONFIG_PROC_STRIPPED))\n+\t\treturn 0;\n+\n \tvn->proc_vlan_dir = proc_net_mkdir(net, name_root, net->proc_net);\n \tif (!vn->proc_vlan_dir)\n \t\tgoto err;\n--- a/net/core/net-procfs.c\n+++ b/net/core/net-procfs.c\n@@ -317,10 +317,12 @@ static int __net_init dev_proc_net_init(\n \tif (!proc_create_net(\"dev\", 0444, net->proc_net, &dev_seq_ops,\n \t\t\tsizeof(struct seq_net_private)))\n \t\tgoto out;\n-\tif (!proc_create_seq(\"softnet_stat\", 0444, net->proc_net,\n+\tif (!IS_ENABLED(CONFIG_PROC_STRIPPED) &&\n+\t\t\t!proc_create_seq(\"softnet_stat\", 0444, net->proc_net,\n \t\t\t &softnet_seq_ops))\n \t\tgoto out_dev;\n-\tif (!proc_create_net(\"ptype\", 0444, net->proc_net, &ptype_seq_ops,\n+\tif (!IS_ENABLED(CONFIG_PROC_STRIPPED) &&\n+\t\t\t!proc_create_net(\"ptype\", 0444, net->proc_net, &ptype_seq_ops,\n \t\t\tsizeof(struct seq_net_private)))\n \t\tgoto out_softnet;\n \n@@ -330,9 +332,11 @@ static int __net_init dev_proc_net_init(\n out:\n \treturn rc;\n out_ptype:\n-\tremove_proc_entry(\"ptype\", net->proc_net);\n+\tif (!IS_ENABLED(CONFIG_PROC_STRIPPED))\n+\t\tremove_proc_entry(\"ptype\", net->proc_net);\n out_softnet:\n-\tremove_proc_entry(\"softnet_stat\", net->proc_net);\n+\tif (!IS_ENABLED(CONFIG_PROC_STRIPPED))\n+\t\tremove_proc_entry(\"softnet_stat\", net->proc_net);\n out_dev:\n \tremove_proc_entry(\"dev\", net->proc_net);\n \tgoto out;\n@@ -342,8 +346,10 @@ static void __net_exit dev_proc_net_exit\n {\n \twext_proc_exit(net);\n \n-\tremove_proc_entry(\"ptype\", net->proc_net);\n-\tremove_proc_entry(\"softnet_stat\", net->proc_net);\n+\tif (!IS_ENABLED(CONFIG_PROC_STRIPPED)) {\n+\t\tremove_proc_entry(\"ptype\", net->proc_net);\n+\t\tremove_proc_entry(\"softnet_stat\", net->proc_net);\n+\t}\n \tremove_proc_entry(\"dev\", net->proc_net);\n }\n \n--- a/net/core/sock.c\n+++ b/net/core/sock.c\n@@ -3855,6 +3855,8 @@ static __net_initdata struct pernet_oper\n \n static int __init proto_init(void)\n {\n+\tif (IS_ENABLED(CONFIG_PROC_STRIPPED))\n+\t\treturn 0;\n \treturn register_pernet_subsys(&proto_net_ops);\n }\n \n--- a/net/ipv4/fib_trie.c\n+++ b/net/ipv4/fib_trie.c\n@@ -3019,11 +3019,13 @@ static const struct seq_operations fib_r\n \n int __net_init fib_proc_init(struct net *net)\n {\n-\tif (!proc_create_net(\"fib_trie\", 0444, net->proc_net, &fib_trie_seq_ops,\n+\tif (!IS_ENABLED(CONFIG_PROC_STRIPPED) &&\n+\t\t\t!proc_create_net(\"fib_trie\", 0444, net->proc_net, &fib_trie_seq_ops,\n \t\t\tsizeof(struct fib_trie_iter)))\n \t\tgoto out1;\n \n-\tif (!proc_create_net_single(\"fib_triestat\", 0444, net->proc_net,\n+\tif (!IS_ENABLED(CONFIG_PROC_STRIPPED) &&\n+\t\t\t!proc_create_net_single(\"fib_triestat\", 0444, net->proc_net,\n \t\t\tfib_triestat_seq_show, NULL))\n \t\tgoto out2;\n \n@@ -3034,17 +3036,21 @@ int __net_init fib_proc_init(struct net\n \treturn 0;\n \n out3:\n-\tremove_proc_entry(\"fib_triestat\", net->proc_net);\n+\tif (!IS_ENABLED(CONFIG_PROC_STRIPPED))\n+\t\tremove_proc_entry(\"fib_triestat\", net->proc_net);\n out2:\n-\tremove_proc_entry(\"fib_trie\", net->proc_net);\n+\tif (!IS_ENABLED(CONFIG_PROC_STRIPPED))\n+\t\tremove_proc_entry(\"fib_trie\", net->proc_net);\n out1:\n \treturn -ENOMEM;\n }\n \n void __net_exit fib_proc_exit(struct net *net)\n {\n-\tremove_proc_entry(\"fib_trie\", net->proc_net);\n-\tremove_proc_entry(\"fib_triestat\", net->proc_net);\n+\tif (!IS_ENABLED(CONFIG_PROC_STRIPPED)) {\n+\t\tremove_proc_entry(\"fib_trie\", net->proc_net);\n+\t\tremove_proc_entry(\"fib_triestat\", net->proc_net);\n+\t}\n \tremove_proc_entry(\"route\", net->proc_net);\n }\n \n--- a/net/ipv4/proc.c\n+++ b/net/ipv4/proc.c\n@@ -553,5 +553,8 @@ static __net_initdata struct pernet_oper\n \n int __init ip_misc_proc_init(void)\n {\n+\tif (IS_ENABLED(CONFIG_PROC_STRIPPED))\n+\t\treturn 0;\n+\n \treturn register_pernet_subsys(&ip_proc_ops);\n }\n--- a/net/ipv4/route.c\n+++ b/net/ipv4/route.c\n@@ -387,6 +387,9 @@ static struct pernet_operations ip_rt_pr\n \n static int __init ip_rt_proc_init(void)\n {\n+\tif (IS_ENABLED(CONFIG_PROC_STRIPPED))\n+\t\treturn 0;\n+\n \treturn register_pernet_subsys(&ip_rt_proc_ops);\n }\n \n"
  },
  {
    "path": "target/linux/generic/hack-5.15/904-debloat_dma_buf.patch",
    "content": "From e3692cb2fcd5ba1244512a0f43b8118f65f1c375 Mon Sep 17 00:00:00 2001\nFrom: Felix Fietkau <nbd@nbd.name>\nDate: Sat, 8 Jul 2017 08:20:43 +0200\nSubject: debloat: dmabuf\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n drivers/base/Kconfig      |  2 +-\n drivers/dma-buf/Makefile  | 10 +++++++---\n drivers/dma-buf/dma-buf.c |  4 +++-\n kernel/sched/core.c       |  1 +\n 4 files changed, 12 insertions(+), 5 deletions(-)\n\n--- a/drivers/base/Kconfig\n+++ b/drivers/base/Kconfig\n@@ -187,7 +187,7 @@ config SOC_BUS\n source \"drivers/base/regmap/Kconfig\"\n \n config DMA_SHARED_BUFFER\n-\tbool\n+\ttristate\n \tdefault n\n \tselect IRQ_WORK\n \thelp\n--- a/drivers/dma-buf/heaps/Makefile\n+++ b/drivers/dma-buf/heaps/Makefile\n@@ -1,3 +1,3 @@\n # SPDX-License-Identifier: GPL-2.0\n-obj-$(CONFIG_DMABUF_HEAPS_SYSTEM)\t+= system_heap.o\n-obj-$(CONFIG_DMABUF_HEAPS_CMA)\t\t+= cma_heap.o\n+dma-buf-objs-$(CONFIG_DMABUF_HEAPS_SYSTEM)\t+= system_heap.o\n+dma-buf-objs-$(CONFIG_DMABUF_HEAPS_CMA)\t\t+= cma_heap.o\n--- a/drivers/dma-buf/Makefile\n+++ b/drivers/dma-buf/Makefile\n@@ -1,16 +1,20 @@\n # SPDX-License-Identifier: GPL-2.0-only\n-obj-y := dma-buf.o dma-fence.o dma-fence-array.o dma-fence-chain.o \\\n+obj-$(CONFIG_DMA_SHARED_BUFFER) := dma-shared-buffer.o\n+\n+dma-buf-objs-y := dma-buf.o dma-fence.o dma-fence-array.o dma-fence-chain.o \\\n \t dma-resv.o seqno-fence.o\n-obj-$(CONFIG_DMABUF_HEAPS)\t+= dma-heap.o\n-obj-$(CONFIG_DMABUF_HEAPS)\t+= heaps/\n-obj-$(CONFIG_SYNC_FILE)\t\t+= sync_file.o\n-obj-$(CONFIG_SW_SYNC)\t\t+= sw_sync.o sync_debug.o\n-obj-$(CONFIG_UDMABUF)\t\t+= udmabuf.o\n-obj-$(CONFIG_DMABUF_SYSFS_STATS) += dma-buf-sysfs-stats.o\n+dma-buf-objs-$(CONFIG_DMABUF_HEAPS)\t+= dma-heap.o\n+obj-$(CONFIG_DMABUF_HEAPS)\t\t+= heaps/\n+dma-buf-objs-$(CONFIG_SYNC_FILE)\t+= sync_file.o\n+dma-buf-objs-$(CONFIG_SW_SYNC)\t\t+= sw_sync.o sync_debug.o\n+dma-buf-objs-$(CONFIG_UDMABUF)\t\t+= udmabuf.o\n+dma-buf-objs-$(CONFIG_DMABUF_SYSFS_STATS) += udmabuf.o\n \n dmabuf_selftests-y := \\\n \tselftest.o \\\n \tst-dma-fence.o \\\n \tst-dma-fence-chain.o\n \n-obj-$(CONFIG_DMABUF_SELFTESTS)\t+= dmabuf_selftests.o\n+dma-buf-objs-$(CONFIG_DMABUF_SELFTESTS)\t+= dmabuf_selftests.o\n+\n+dma-shared-buffer-objs :=  $(dma-buf-objs-y)\n--- a/drivers/dma-buf/dma-buf.c\n+++ b/drivers/dma-buf/dma-buf.c\n@@ -1498,4 +1498,5 @@ static void __exit dma_buf_deinit(void)\n \tkern_unmount(dma_buf_mnt);\n \tdma_buf_uninit_sysfs_statistics();\n }\n-__exitcall(dma_buf_deinit);\n+module_exit(dma_buf_deinit);\n+MODULE_LICENSE(\"GPL\");\n--- a/kernel/sched/core.c\n+++ b/kernel/sched/core.c\n@@ -4175,6 +4175,7 @@ int wake_up_state(struct task_struct *p,\n {\n \treturn try_to_wake_up(p, state, 0);\n }\n+EXPORT_SYMBOL_GPL(wake_up_state);\n \n /*\n  * Perform scheduler related setup for a newly forked process p.\n--- a/fs/d_path.c\n+++ b/fs/d_path.c\n@@ -316,6 +316,7 @@ char *dynamic_dname(struct dentry *dentr\n \tbuffer += buflen - sz;\n \treturn memcpy(buffer, temp, sz);\n }\n+EXPORT_SYMBOL_GPL(dynamic_dname);\n \n char *simple_dname(struct dentry *dentry, char *buffer, int buflen)\n {\n"
  },
  {
    "path": "target/linux/generic/hack-5.15/910-kobject_uevent.patch",
    "content": "From 0d37e6edc09c99e683dd91ca0e83bbc0df8477b3 Mon Sep 17 00:00:00 2001\nFrom: Felix Fietkau <nbd@nbd.name>\nDate: Sun, 16 Jul 2017 16:56:10 +0200\nSubject: lib: add uevent_next_seqnum()\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n include/linux/kobject.h |  5 +++++\n lib/kobject_uevent.c    | 37 +++++++++++++++++++++++++++++++++++++\n 2 files changed, 42 insertions(+)\n\n--- a/lib/kobject_uevent.c\n+++ b/lib/kobject_uevent.c\n@@ -179,6 +179,18 @@ out:\n \treturn r;\n }\n \n+u64 uevent_next_seqnum(void)\n+{\n+\tu64 seq;\n+\n+\tmutex_lock(&uevent_sock_mutex);\n+\tseq = ++uevent_seqnum;\n+\tmutex_unlock(&uevent_sock_mutex);\n+\n+\treturn seq;\n+}\n+EXPORT_SYMBOL_GPL(uevent_next_seqnum);\n+\n /**\n  * kobject_synth_uevent - send synthetic uevent with arguments\n  *\n"
  },
  {
    "path": "target/linux/generic/hack-5.15/911-kobject_add_broadcast_uevent.patch",
    "content": "From 0d37e6edc09c99e683dd91ca0e83bbc0df8477b3 Mon Sep 17 00:00:00 2001\nFrom: Felix Fietkau <nbd@nbd.name>\nDate: Sun, 16 Jul 2017 16:56:10 +0200\nSubject: lib: add uevent_next_seqnum()\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n include/linux/kobject.h |  5 +++++\n lib/kobject_uevent.c    | 37 +++++++++++++++++++++++++++++++++++++\n 2 files changed, 42 insertions(+)\n\n--- a/include/linux/kobject.h\n+++ b/include/linux/kobject.h\n@@ -32,6 +32,8 @@\n #define UEVENT_NUM_ENVP\t\t\t64\t/* number of env pointers */\n #define UEVENT_BUFFER_SIZE\t\t2048\t/* buffer for the variables */\n \n+struct sk_buff;\n+\n #ifdef CONFIG_UEVENT_HELPER\n /* path to the userspace helper executed on an event */\n extern char uevent_helper[];\n@@ -244,4 +246,7 @@ int kobject_synth_uevent(struct kobject\n __printf(2, 3)\n int add_uevent_var(struct kobj_uevent_env *env, const char *format, ...);\n \n+int broadcast_uevent(struct sk_buff *skb, __u32 pid, __u32 group,\n+\t\t     gfp_t allocation);\n+\n #endif /* _KOBJECT_H_ */\n--- a/lib/kobject_uevent.c\n+++ b/lib/kobject_uevent.c\n@@ -691,6 +691,43 @@ int add_uevent_var(struct kobj_uevent_en\n EXPORT_SYMBOL_GPL(add_uevent_var);\n \n #if defined(CONFIG_NET)\n+int broadcast_uevent(struct sk_buff *skb, __u32 pid, __u32 group,\n+\t\t     gfp_t allocation)\n+{\n+\tstruct uevent_sock *ue_sk;\n+\tint err = 0;\n+\n+\t/* send netlink message */\n+\tmutex_lock(&uevent_sock_mutex);\n+\tlist_for_each_entry(ue_sk, &uevent_sock_list, list) {\n+\t\tstruct sock *uevent_sock = ue_sk->sk;\n+\t\tstruct sk_buff *skb2;\n+\n+\t\tskb2 = skb_clone(skb, allocation);\n+\t\tif (!skb2)\n+\t\t\tbreak;\n+\n+\t\terr = netlink_broadcast(uevent_sock, skb2, pid, group,\n+\t\t\t\t\tallocation);\n+\t\tif (err)\n+\t\t\tbreak;\n+\t}\n+\tmutex_unlock(&uevent_sock_mutex);\n+\n+\tkfree_skb(skb);\n+\treturn err;\n+}\n+#else\n+int broadcast_uevent(struct sk_buff *skb, __u32 pid, __u32 group,\n+\t\t     gfp_t allocation)\n+{\n+\tkfree_skb(skb);\n+\treturn 0;\n+}\n+#endif\n+EXPORT_SYMBOL_GPL(broadcast_uevent);\n+\n+#if defined(CONFIG_NET)\n static int uevent_net_broadcast(struct sock *usk, struct sk_buff *skb,\n \t\t\t\tstruct netlink_ext_ack *extack)\n {\n"
  },
  {
    "path": "target/linux/generic/hack-5.15/920-device_tree_cmdline.patch",
    "content": "--- a/drivers/of/fdt.c\n+++ b/drivers/of/fdt.c\n@@ -1158,6 +1158,9 @@ int __init early_init_dt_scan_chosen(uns\n \tp = of_get_flat_dt_prop(node, \"bootargs\", &l);\n \tif (p != NULL && l > 0)\n \t\tstrlcpy(data, p, min(l, COMMAND_LINE_SIZE));\n+\tp = of_get_flat_dt_prop(node, \"bootargs-append\", &l);\n+\tif (p != NULL && l > 0)\n+\t\tstrlcat(data, p, min_t(int, strlen(data) + (int)l, COMMAND_LINE_SIZE));\n \n \t/*\n \t * CONFIG_CMDLINE is meant to be a default in case nothing else\n"
  },
  {
    "path": "target/linux/generic/image/Makefile",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2006-2010 OpenWrt.org\n\ninclude $(TOPDIR)/rules.mk\ninclude $(INCLUDE_DIR)/image.mk\n\n# use default targets for everything\n\n$(eval $(call BuildImage))\n"
  },
  {
    "path": "target/linux/generic/image/initramfs-base-files.txt",
    "content": "nod /dev/console 600 0 0 c 5 1\nnod /dev/null 666 0 0 c 1 3\nnod /dev/zero 666 0 0 c 1 5\nnod /dev/tty 666 0 0 c 5 0\nnod /dev/tty0 660 0 0 c 4 0\nnod /dev/tty1 660 0 0 c 4 1\nnod /dev/random 666 0 0 c 1 8\nnod /dev/urandom 666 0 0 c 1 9\ndir /dev/pts 755 0 0\n"
  },
  {
    "path": "target/linux/generic/image/lzma-loader/Makefile",
    "content": "# \n# Copyright (C) 2006 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME := loader\nPKG_VERSION := 0.05\n\nPKG_BUILD_DIR := $(KDIR)/$(PKG_NAME)-$(PKG_VERSION)$(LOADER_TYPE)\n\n$(PKG_BUILD_DIR)/.prepared:\n\tmkdir $(PKG_BUILD_DIR)\n\t$(CP) ./src/* $(PKG_BUILD_DIR)/\n\ttouch $@\n\n$(PKG_BUILD_DIR)/lzma.elf: $(PKG_BUILD_DIR)/.prepared $(PKG_BUILD_DIR)/vmlinux.lzma\n\tPATH=\"$(TARGET_PATH)\" $(MAKE) -C $(PKG_BUILD_DIR) \\\n\t\tCC=\"$(TARGET_CC)\" CROSS_COMPILE=\"$(TARGET_CROSS)\" \\\n\t\tRAMSIZE=$(RAMSIZE) \\\n\t\tLOADADDR=$(LOADADDR) \\\n\t\tKERNEL_ENTRY=$(KERNEL_ENTRY) \\\n\t\tIMAGE_COPY=$(IMAGE_COPY)\n\n\n$(PKG_BUILD_DIR)/vmlinux.lzma: $(KDIR)/vmlinux.lzma\n\t$(CP) $< $@\n\n$(KDIR)/loader$(LOADER_TYPE).elf: $(PKG_BUILD_DIR)/lzma.elf\n\t$(CP) $< $@\n\n$(KDIR)/loader$(LOADER_TYPE).bin: $(PKG_BUILD_DIR)/lzma.bin\n\t$(CP) $< $@\n\ndownload: \nprepare: $(PKG_BUILD_DIR)/.prepared\ncompile: $(KDIR)/loader$(LOADER_TYPE).elf $(KDIR)/loader$(LOADER_TYPE).bin\ninstall:\n\nclean:\n\trm -rf $(PKG_BUILD_DIR)\n\trm -f $(KDIR)/loader.elf\n\trm -f $(KDIR)/loader.bin\n"
  },
  {
    "path": "target/linux/generic/image/lzma-loader/src/LzmaDecode.c",
    "content": "/*\n  LzmaDecode.c\n  LZMA Decoder (optimized for Speed version)\n  \n  LZMA SDK 4.22 Copyright (c) 1999-2005 Igor Pavlov (2005-06-10)\n  http://www.7-zip.org/\n\n  LZMA SDK is licensed under two licenses:\n  1) GNU Lesser General Public License (GNU LGPL)\n  2) Common Public License (CPL)\n  It means that you can select one of these two licenses and \n  follow rules of that license.\n\n  SPECIAL EXCEPTION:\n  Igor Pavlov, as the author of this Code, expressly permits you to \n  statically or dynamically link your Code (or bind by name) to the \n  interfaces of this file without subjecting your linked Code to the \n  terms of the CPL or GNU LGPL. Any modifications or additions \n  to this file, however, are subject to the LGPL or CPL terms.\n*/\n\n#include \"LzmaDecode.h\"\n\n#ifndef Byte\n#define Byte unsigned char\n#endif\n\n#define kNumTopBits 24\n#define kTopValue ((UInt32)1 << kNumTopBits)\n\n#define kNumBitModelTotalBits 11\n#define kBitModelTotal (1 << kNumBitModelTotalBits)\n#define kNumMoveBits 5\n\n#define RC_READ_BYTE (*Buffer++)\n\n#define RC_INIT2 Code = 0; Range = 0xFFFFFFFF; \\\n  { int i; for(i = 0; i < 5; i++) { RC_TEST; Code = (Code << 8) | RC_READ_BYTE; }}\n\n#ifdef _LZMA_IN_CB\n\n#define RC_TEST { if (Buffer == BufferLim) \\\n  { SizeT size; int result = InCallback->Read(InCallback, &Buffer, &size); if (result != LZMA_RESULT_OK) return result; \\\n  BufferLim = Buffer + size; if (size == 0) return LZMA_RESULT_DATA_ERROR; }}\n\n#define RC_INIT Buffer = BufferLim = 0; RC_INIT2\n\n#else\n\n#define RC_TEST { if (Buffer == BufferLim) return LZMA_RESULT_DATA_ERROR; }\n\n#define RC_INIT(buffer, bufferSize) Buffer = buffer; BufferLim = buffer + bufferSize; RC_INIT2\n \n#endif\n\n#define RC_NORMALIZE if (Range < kTopValue) { RC_TEST; Range <<= 8; Code = (Code << 8) | RC_READ_BYTE; }\n\n#define IfBit0(p) RC_NORMALIZE; bound = (Range >> kNumBitModelTotalBits) * *(p); if (Code < bound)\n#define UpdateBit0(p) Range = bound; *(p) += (kBitModelTotal - *(p)) >> kNumMoveBits;\n#define UpdateBit1(p) Range -= bound; Code -= bound; *(p) -= (*(p)) >> kNumMoveBits;\n\n#define RC_GET_BIT2(p, mi, A0, A1) IfBit0(p) \\\n  { UpdateBit0(p); mi <<= 1; A0; } else \\\n  { UpdateBit1(p); mi = (mi + mi) + 1; A1; } \n  \n#define RC_GET_BIT(p, mi) RC_GET_BIT2(p, mi, ; , ;)               \n\n#define RangeDecoderBitTreeDecode(probs, numLevels, res) \\\n  { int i = numLevels; res = 1; \\\n  do { CProb *p = probs + res; RC_GET_BIT(p, res) } while(--i != 0); \\\n  res -= (1 << numLevels); }\n\n\n#define kNumPosBitsMax 4\n#define kNumPosStatesMax (1 << kNumPosBitsMax)\n\n#define kLenNumLowBits 3\n#define kLenNumLowSymbols (1 << kLenNumLowBits)\n#define kLenNumMidBits 3\n#define kLenNumMidSymbols (1 << kLenNumMidBits)\n#define kLenNumHighBits 8\n#define kLenNumHighSymbols (1 << kLenNumHighBits)\n\n#define LenChoice 0\n#define LenChoice2 (LenChoice + 1)\n#define LenLow (LenChoice2 + 1)\n#define LenMid (LenLow + (kNumPosStatesMax << kLenNumLowBits))\n#define LenHigh (LenMid + (kNumPosStatesMax << kLenNumMidBits))\n#define kNumLenProbs (LenHigh + kLenNumHighSymbols) \n\n\n#define kNumStates 12\n#define kNumLitStates 7\n\n#define kStartPosModelIndex 4\n#define kEndPosModelIndex 14\n#define kNumFullDistances (1 << (kEndPosModelIndex >> 1))\n\n#define kNumPosSlotBits 6\n#define kNumLenToPosStates 4\n\n#define kNumAlignBits 4\n#define kAlignTableSize (1 << kNumAlignBits)\n\n#define kMatchMinLen 2\n\n#define IsMatch 0\n#define IsRep (IsMatch + (kNumStates << kNumPosBitsMax))\n#define IsRepG0 (IsRep + kNumStates)\n#define IsRepG1 (IsRepG0 + kNumStates)\n#define IsRepG2 (IsRepG1 + kNumStates)\n#define IsRep0Long (IsRepG2 + kNumStates)\n#define PosSlot (IsRep0Long + (kNumStates << kNumPosBitsMax))\n#define SpecPos (PosSlot + (kNumLenToPosStates << kNumPosSlotBits))\n#define Align (SpecPos + kNumFullDistances - kEndPosModelIndex)\n#define LenCoder (Align + kAlignTableSize)\n#define RepLenCoder (LenCoder + kNumLenProbs)\n#define Literal (RepLenCoder + kNumLenProbs)\n\n#if Literal != LZMA_BASE_SIZE\nStopCompilingDueBUG\n#endif\n\n#if 0\nint LzmaDecodeProperties(CLzmaProperties *propsRes, const unsigned char *propsData, int size)\n{\n  unsigned char prop0;\n  if (size < LZMA_PROPERTIES_SIZE)\n    return LZMA_RESULT_DATA_ERROR;\n  prop0 = propsData[0];\n  if (prop0 >= (9 * 5 * 5))\n    return LZMA_RESULT_DATA_ERROR;\n  {\n    for (propsRes->pb = 0; prop0 >= (9 * 5); propsRes->pb++, prop0 -= (9 * 5));\n    for (propsRes->lp = 0; prop0 >= 9; propsRes->lp++, prop0 -= 9);\n    propsRes->lc = prop0;\n    /*\n    unsigned char remainder = (unsigned char)(prop0 / 9);\n    propsRes->lc = prop0 % 9;\n    propsRes->pb = remainder / 5;\n    propsRes->lp = remainder % 5;\n    */\n  }\n\n  #ifdef _LZMA_OUT_READ\n  {\n    int i;\n    propsRes->DictionarySize = 0;\n    for (i = 0; i < 4; i++)\n      propsRes->DictionarySize += (UInt32)(propsData[1 + i]) << (i * 8);\n    if (propsRes->DictionarySize == 0)\n      propsRes->DictionarySize = 1;\n  }\n  #endif\n  return LZMA_RESULT_OK;\n}\n#endif\n\n#define kLzmaStreamWasFinishedId (-1)\n\nint LzmaDecode(CLzmaDecoderState *vs,\n    #ifdef _LZMA_IN_CB\n    ILzmaInCallback *InCallback,\n    #else\n    const unsigned char *inStream, SizeT inSize, SizeT *inSizeProcessed,\n    #endif\n    unsigned char *outStream, SizeT outSize, SizeT *outSizeProcessed)\n{\n  CProb *p = vs->Probs;\n  SizeT nowPos = 0;\n  Byte previousByte = 0;\n  UInt32 posStateMask = (1 << (vs->Properties.pb)) - 1;\n  UInt32 literalPosMask = (1 << (vs->Properties.lp)) - 1;\n  int lc = vs->Properties.lc;\n\n  #ifdef _LZMA_OUT_READ\n  \n  UInt32 Range = vs->Range;\n  UInt32 Code = vs->Code;\n  #ifdef _LZMA_IN_CB\n  const Byte *Buffer = vs->Buffer;\n  const Byte *BufferLim = vs->BufferLim;\n  #else\n  const Byte *Buffer = inStream;\n  const Byte *BufferLim = inStream + inSize;\n  #endif\n  int state = vs->State;\n  UInt32 rep0 = vs->Reps[0], rep1 = vs->Reps[1], rep2 = vs->Reps[2], rep3 = vs->Reps[3];\n  int len = vs->RemainLen;\n  UInt32 globalPos = vs->GlobalPos;\n  UInt32 distanceLimit = vs->DistanceLimit;\n\n  Byte *dictionary = vs->Dictionary;\n  UInt32 dictionarySize = vs->Properties.DictionarySize;\n  UInt32 dictionaryPos = vs->DictionaryPos;\n\n  Byte tempDictionary[4];\n\n  #ifndef _LZMA_IN_CB\n  *inSizeProcessed = 0;\n  #endif\n  *outSizeProcessed = 0;\n  if (len == kLzmaStreamWasFinishedId)\n    return LZMA_RESULT_OK;\n\n  if (dictionarySize == 0)\n  {\n    dictionary = tempDictionary;\n    dictionarySize = 1;\n    tempDictionary[0] = vs->TempDictionary[0];\n  }\n\n  if (len == kLzmaNeedInitId)\n  {\n    {\n      UInt32 numProbs = Literal + ((UInt32)LZMA_LIT_SIZE << (lc + vs->Properties.lp));\n      UInt32 i;\n      for (i = 0; i < numProbs; i++)\n        p[i] = kBitModelTotal >> 1; \n      rep0 = rep1 = rep2 = rep3 = 1;\n      state = 0;\n      globalPos = 0;\n      distanceLimit = 0;\n      dictionaryPos = 0;\n      dictionary[dictionarySize - 1] = 0;\n      #ifdef _LZMA_IN_CB\n      RC_INIT;\n      #else\n      RC_INIT(inStream, inSize);\n      #endif\n    }\n    len = 0;\n  }\n  while(len != 0 && nowPos < outSize)\n  {\n    UInt32 pos = dictionaryPos - rep0;\n    if (pos >= dictionarySize)\n      pos += dictionarySize;\n    outStream[nowPos++] = dictionary[dictionaryPos] = dictionary[pos];\n    if (++dictionaryPos == dictionarySize)\n      dictionaryPos = 0;\n    len--;\n  }\n  if (dictionaryPos == 0)\n    previousByte = dictionary[dictionarySize - 1];\n  else\n    previousByte = dictionary[dictionaryPos - 1];\n\n  #else /* if !_LZMA_OUT_READ */\n\n  int state = 0;\n  UInt32 rep0 = 1, rep1 = 1, rep2 = 1, rep3 = 1;\n  int len = 0;\n  const Byte *Buffer;\n  const Byte *BufferLim;\n  UInt32 Range;\n  UInt32 Code;\n\n  #ifndef _LZMA_IN_CB\n  *inSizeProcessed = 0;\n  #endif\n  *outSizeProcessed = 0;\n\n  {\n    UInt32 i;\n    UInt32 numProbs = Literal + ((UInt32)LZMA_LIT_SIZE << (lc + vs->Properties.lp));\n    for (i = 0; i < numProbs; i++)\n      p[i] = kBitModelTotal >> 1;\n  }\n  \n  #ifdef _LZMA_IN_CB\n  RC_INIT;\n  #else\n  RC_INIT(inStream, inSize);\n  #endif\n\n  #endif /* _LZMA_OUT_READ */\n\n  while(nowPos < outSize)\n  {\n    CProb *prob;\n    UInt32 bound;\n    int posState = (int)(\n        (nowPos \n        #ifdef _LZMA_OUT_READ\n        + globalPos\n        #endif\n        )\n        & posStateMask);\n\n    prob = p + IsMatch + (state << kNumPosBitsMax) + posState;\n    IfBit0(prob)\n    {\n      int symbol = 1;\n      UpdateBit0(prob)\n      prob = p + Literal + (LZMA_LIT_SIZE * \n        (((\n        (nowPos \n        #ifdef _LZMA_OUT_READ\n        + globalPos\n        #endif\n        )\n        & literalPosMask) << lc) + (previousByte >> (8 - lc))));\n\n      if (state >= kNumLitStates)\n      {\n        int matchByte;\n        #ifdef _LZMA_OUT_READ\n        UInt32 pos = dictionaryPos - rep0;\n        if (pos >= dictionarySize)\n          pos += dictionarySize;\n        matchByte = dictionary[pos];\n        #else\n        matchByte = outStream[nowPos - rep0];\n        #endif\n        do\n        {\n          int bit;\n          CProb *probLit;\n          matchByte <<= 1;\n          bit = (matchByte & 0x100);\n          probLit = prob + 0x100 + bit + symbol;\n          RC_GET_BIT2(probLit, symbol, if (bit != 0) break, if (bit == 0) break)\n        }\n        while (symbol < 0x100);\n      }\n      while (symbol < 0x100)\n      {\n        CProb *probLit = prob + symbol;\n        RC_GET_BIT(probLit, symbol)\n      }\n      previousByte = (Byte)symbol;\n\n      outStream[nowPos++] = previousByte;\n      #ifdef _LZMA_OUT_READ\n      if (distanceLimit < dictionarySize)\n        distanceLimit++;\n\n      dictionary[dictionaryPos] = previousByte;\n      if (++dictionaryPos == dictionarySize)\n        dictionaryPos = 0;\n      #endif\n      if (state < 4) state = 0;\n      else if (state < 10) state -= 3;\n      else state -= 6;\n    }\n    else             \n    {\n      UpdateBit1(prob);\n      prob = p + IsRep + state;\n      IfBit0(prob)\n      {\n        UpdateBit0(prob);\n        rep3 = rep2;\n        rep2 = rep1;\n        rep1 = rep0;\n        state = state < kNumLitStates ? 0 : 3;\n        prob = p + LenCoder;\n      }\n      else\n      {\n        UpdateBit1(prob);\n        prob = p + IsRepG0 + state;\n        IfBit0(prob)\n        {\n          UpdateBit0(prob);\n          prob = p + IsRep0Long + (state << kNumPosBitsMax) + posState;\n          IfBit0(prob)\n          {\n            #ifdef _LZMA_OUT_READ\n            UInt32 pos;\n            #endif\n            UpdateBit0(prob);\n            \n            #ifdef _LZMA_OUT_READ\n            if (distanceLimit == 0)\n            #else\n            if (nowPos == 0)\n            #endif\n              return LZMA_RESULT_DATA_ERROR;\n            \n            state = state < kNumLitStates ? 9 : 11;\n            #ifdef _LZMA_OUT_READ\n            pos = dictionaryPos - rep0;\n            if (pos >= dictionarySize)\n              pos += dictionarySize;\n            previousByte = dictionary[pos];\n            dictionary[dictionaryPos] = previousByte;\n            if (++dictionaryPos == dictionarySize)\n              dictionaryPos = 0;\n            #else\n            previousByte = outStream[nowPos - rep0];\n            #endif\n            outStream[nowPos++] = previousByte;\n            #ifdef _LZMA_OUT_READ\n            if (distanceLimit < dictionarySize)\n              distanceLimit++;\n            #endif\n\n            continue;\n          }\n          else\n          {\n            UpdateBit1(prob);\n          }\n        }\n        else\n        {\n          UInt32 distance;\n          UpdateBit1(prob);\n          prob = p + IsRepG1 + state;\n          IfBit0(prob)\n          {\n            UpdateBit0(prob);\n            distance = rep1;\n          }\n          else \n          {\n            UpdateBit1(prob);\n            prob = p + IsRepG2 + state;\n            IfBit0(prob)\n            {\n              UpdateBit0(prob);\n              distance = rep2;\n            }\n            else\n            {\n              UpdateBit1(prob);\n              distance = rep3;\n              rep3 = rep2;\n            }\n            rep2 = rep1;\n          }\n          rep1 = rep0;\n          rep0 = distance;\n        }\n        state = state < kNumLitStates ? 8 : 11;\n        prob = p + RepLenCoder;\n      }\n      {\n        int numBits, offset;\n        CProb *probLen = prob + LenChoice;\n        IfBit0(probLen)\n        {\n          UpdateBit0(probLen);\n          probLen = prob + LenLow + (posState << kLenNumLowBits);\n          offset = 0;\n          numBits = kLenNumLowBits;\n        }\n        else\n        {\n          UpdateBit1(probLen);\n          probLen = prob + LenChoice2;\n          IfBit0(probLen)\n          {\n            UpdateBit0(probLen);\n            probLen = prob + LenMid + (posState << kLenNumMidBits);\n            offset = kLenNumLowSymbols;\n            numBits = kLenNumMidBits;\n          }\n          else\n          {\n            UpdateBit1(probLen);\n            probLen = prob + LenHigh;\n            offset = kLenNumLowSymbols + kLenNumMidSymbols;\n            numBits = kLenNumHighBits;\n          }\n        }\n        RangeDecoderBitTreeDecode(probLen, numBits, len);\n        len += offset;\n      }\n\n      if (state < 4)\n      {\n        int posSlot;\n        state += kNumLitStates;\n        prob = p + PosSlot +\n            ((len < kNumLenToPosStates ? len : kNumLenToPosStates - 1) << \n            kNumPosSlotBits);\n        RangeDecoderBitTreeDecode(prob, kNumPosSlotBits, posSlot);\n        if (posSlot >= kStartPosModelIndex)\n        {\n          int numDirectBits = ((posSlot >> 1) - 1);\n          rep0 = (2 | ((UInt32)posSlot & 1));\n          if (posSlot < kEndPosModelIndex)\n          {\n            rep0 <<= numDirectBits;\n            prob = p + SpecPos + rep0 - posSlot - 1;\n          }\n          else\n          {\n            numDirectBits -= kNumAlignBits;\n            do\n            {\n              RC_NORMALIZE\n              Range >>= 1;\n              rep0 <<= 1;\n              if (Code >= Range)\n              {\n                Code -= Range;\n                rep0 |= 1;\n              }\n            }\n            while (--numDirectBits != 0);\n            prob = p + Align;\n            rep0 <<= kNumAlignBits;\n            numDirectBits = kNumAlignBits;\n          }\n          {\n            int i = 1;\n            int mi = 1;\n            do\n            {\n              CProb *prob3 = prob + mi;\n              RC_GET_BIT2(prob3, mi, ; , rep0 |= i);\n              i <<= 1;\n            }\n            while(--numDirectBits != 0);\n          }\n        }\n        else\n          rep0 = posSlot;\n        if (++rep0 == (UInt32)(0))\n        {\n          /* it's for stream version */\n          len = kLzmaStreamWasFinishedId;\n          break;\n        }\n      }\n\n      len += kMatchMinLen;\n      #ifdef _LZMA_OUT_READ\n      if (rep0 > distanceLimit) \n      #else\n      if (rep0 > nowPos)\n      #endif\n        return LZMA_RESULT_DATA_ERROR;\n\n      #ifdef _LZMA_OUT_READ\n      if (dictionarySize - distanceLimit > (UInt32)len)\n        distanceLimit += len;\n      else\n        distanceLimit = dictionarySize;\n      #endif\n\n      do\n      {\n        #ifdef _LZMA_OUT_READ\n        UInt32 pos = dictionaryPos - rep0;\n        if (pos >= dictionarySize)\n          pos += dictionarySize;\n        previousByte = dictionary[pos];\n        dictionary[dictionaryPos] = previousByte;\n        if (++dictionaryPos == dictionarySize)\n          dictionaryPos = 0;\n        #else\n        previousByte = outStream[nowPos - rep0];\n        #endif\n        len--;\n        outStream[nowPos++] = previousByte;\n      }\n      while(len != 0 && nowPos < outSize);\n    }\n  }\n  RC_NORMALIZE;\n\n  #ifdef _LZMA_OUT_READ\n  vs->Range = Range;\n  vs->Code = Code;\n  vs->DictionaryPos = dictionaryPos;\n  vs->GlobalPos = globalPos + (UInt32)nowPos;\n  vs->DistanceLimit = distanceLimit;\n  vs->Reps[0] = rep0;\n  vs->Reps[1] = rep1;\n  vs->Reps[2] = rep2;\n  vs->Reps[3] = rep3;\n  vs->State = state;\n  vs->RemainLen = len;\n  vs->TempDictionary[0] = tempDictionary[0];\n  #endif\n\n  #ifdef _LZMA_IN_CB\n  vs->Buffer = Buffer;\n  vs->BufferLim = BufferLim;\n  #else\n  *inSizeProcessed = (SizeT)(Buffer - inStream);\n  #endif\n  *outSizeProcessed = nowPos;\n  return LZMA_RESULT_OK;\n}\n"
  },
  {
    "path": "target/linux/generic/image/lzma-loader/src/LzmaDecode.h",
    "content": "/* \n  LzmaDecode.h\n  LZMA Decoder interface\n\n  LZMA SDK 4.21 Copyright (c) 1999-2005 Igor Pavlov (2005-06-08)\n  http://www.7-zip.org/\n\n  LZMA SDK is licensed under two licenses:\n  1) GNU Lesser General Public License (GNU LGPL)\n  2) Common Public License (CPL)\n  It means that you can select one of these two licenses and \n  follow rules of that license.\n\n  SPECIAL EXCEPTION:\n  Igor Pavlov, as the author of this code, expressly permits you to \n  statically or dynamically link your code (or bind by name) to the \n  interfaces of this file without subjecting your linked code to the \n  terms of the CPL or GNU LGPL. Any modifications or additions \n  to this file, however, are subject to the LGPL or CPL terms.\n*/\n\n#ifndef __LZMADECODE_H\n#define __LZMADECODE_H\n\n/* #define _LZMA_IN_CB */\n/* Use callback for input data */\n\n/* #define _LZMA_OUT_READ */\n/* Use read function for output data */\n\n/* #define _LZMA_PROB32 */\n/* It can increase speed on some 32-bit CPUs, \n   but memory usage will be doubled in that case */\n\n/* #define _LZMA_LOC_OPT */\n/* Enable local speed optimizations inside code */\n\n/* #define _LZMA_SYSTEM_SIZE_T */\n/* Use system's size_t. You can use it to enable 64-bit sizes supporting*/\n\n#ifndef UInt32\n#ifdef _LZMA_UINT32_IS_ULONG\n#define UInt32 unsigned long\n#else\n#define UInt32 unsigned int\n#endif\n#endif\n\n#ifndef SizeT\n#ifdef _LZMA_SYSTEM_SIZE_T\n#include <stddef.h>\n#define SizeT size_t\n#else\n#define SizeT UInt32\n#endif\n#endif\n\n#ifdef _LZMA_PROB32\n#define CProb UInt32\n#else\n#define CProb unsigned short\n#endif\n\n#define LZMA_RESULT_OK 0\n#define LZMA_RESULT_DATA_ERROR 1\n\n#ifdef _LZMA_IN_CB\ntypedef struct _ILzmaInCallback\n{\n  int (*Read)(void *object, const unsigned char **buffer, SizeT *bufferSize);\n} ILzmaInCallback;\n#endif\n\n#define LZMA_BASE_SIZE 1846\n#define LZMA_LIT_SIZE 768\n\n#define LZMA_PROPERTIES_SIZE 5\n\ntypedef struct _CLzmaProperties\n{\n  int lc;\n  int lp;\n  int pb;\n  #ifdef _LZMA_OUT_READ\n  UInt32 DictionarySize;\n  #endif\n}CLzmaProperties;\n\nint LzmaDecodeProperties(CLzmaProperties *propsRes, const unsigned char *propsData, int size);\n\n#define LzmaGetNumProbs(Properties) (LZMA_BASE_SIZE + (LZMA_LIT_SIZE << ((Properties)->lc + (Properties)->lp)))\n\n#define kLzmaNeedInitId (-2)\n\ntypedef struct _CLzmaDecoderState\n{\n  CLzmaProperties Properties;\n  CProb *Probs;\n\n  #ifdef _LZMA_IN_CB\n  const unsigned char *Buffer;\n  const unsigned char *BufferLim;\n  #endif\n\n  #ifdef _LZMA_OUT_READ\n  unsigned char *Dictionary;\n  UInt32 Range;\n  UInt32 Code;\n  UInt32 DictionaryPos;\n  UInt32 GlobalPos;\n  UInt32 DistanceLimit;\n  UInt32 Reps[4];\n  int State;\n  int RemainLen;\n  unsigned char TempDictionary[4];\n  #endif\n} CLzmaDecoderState;\n\n#ifdef _LZMA_OUT_READ\n#define LzmaDecoderInit(vs) { (vs)->RemainLen = kLzmaNeedInitId; }\n#endif\n\nint LzmaDecode(CLzmaDecoderState *vs,\n    #ifdef _LZMA_IN_CB\n    ILzmaInCallback *inCallback,\n    #else\n    const unsigned char *inStream, SizeT inSize, SizeT *inSizeProcessed,\n    #endif\n    unsigned char *outStream, SizeT outSize, SizeT *outSizeProcessed);\n\n#endif\n"
  },
  {
    "path": "target/linux/generic/image/lzma-loader/src/Makefile",
    "content": "# \n# Copyright (C) 2006 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\nRAMSTART = 0x80000000\nRAMSIZE = 0x00100000\t\t# 1MB\nLOADADDR = 0x80400000\t\t# RAM start + 4M\nKERNEL_ENTRY = 0x80001000\nIMAGE_COPY:=0\n\nCROSS_COMPILE = mips-linux-\n\nOBJCOPY:= $(CROSS_COMPILE)objcopy -O binary -R .reginfo -R .note -R .comment -R .mdebug -S\nCFLAGS := -fno-builtin -Os -G 0 -ffunction-sections -mno-abicalls -fno-pic -mabi=32 -march=mips32 -Wa,-32 -Wa,-march=mips32 -Wa,-mips32 -Wa,--trap -Wall -DRAMSTART=${RAMSTART} -DRAMSIZE=${RAMSIZE} -DKERNEL_ENTRY=${KERNEL_ENTRY} -D_LZMA_IN_CB\nifeq ($(IMAGE_COPY),1)\nCFLAGS += -DLOADADDR=${LOADADDR} -DIMAGE_COPY=1\nendif\n\n.S.s:\n\t$(CPP) $(CFLAGS) $< -o $*.s\n.S.o:\n\t$(CC) $(CFLAGS) -c $< -o $*.o\n.c.o:\n\t$(CC) $(CFLAGS) -c $< -o $*.o\n\nCC =       $(CROSS_COMPILE)gcc\nLD =       $(CROSS_COMPILE)ld\nOBJDUMP =  $(CROSS_COMPILE)objdump\n\nO_FORMAT = $(shell $(OBJDUMP) -i | head -2 | grep elf32)\n\n# Drop some uninteresting sections in the kernel.\n# This is only relevant for ELF kernels but doesn't hurt a.out\ndrop-sections   = .reginfo .mdebug .comment\nstrip-flags     = $(addprefix --remove-section=,$(drop-sections))\n\nall : lzma.elf lzma.bin\n\nlzma.lds: lzma.lds.in\n\tsed -e 's,@LOADADDR@,$(LOADADDR),g' -e 's,@ENTRY@,_start,g' $< >$@\n\nkernel.o: vmlinux.lzma lzma.lds\n\t$(LD) -r -b binary --oformat $(O_FORMAT) -o $@ $<\n\nlzma.bin: lzma.elf\n\t$(OBJCOPY) $< $@\n\nifeq ($(IMAGE_COPY),1)\nLOADER_ENTRY ?= $(KERNEL_ENTRY)\nlzma.o: decompress.o LzmaDecode.o kernel.o\n\tsed -e 's,@LOADADDR@,$(LOADADDR),g' -e 's,@ENTRY@,entry,g' lzma.lds.in >lzma-stage2.lds\n\t$(LD) -static --no-warn-mismatch -e entry -Tlzma-stage2.lds -o temp-$@ $^\n\t$(OBJCOPY) temp-$@ lzma.tmp\n\t@echo \"SECTIONS { .data : { code_start = .; *(.data) code_stop = .; }}\" > lzma-data.lds\n\t$(LD) -no-warn-mismatch -T lzma-data.lds -r -o $@ -b binary lzma.tmp --oformat $(O_FORMAT)\n\t\nlzma.elf: start.o lzma.o\n\tsed -e 's,@LOADADDR@,$(LOADER_ENTRY),g' lzma-copy.lds.in >lzma-copy.lds\n\t$(LD) -s -Tlzma-copy.lds -o $@ $^\nelse\nlzma.elf: start.o decompress.o LzmaDecode.o kernel.o\n\t$(LD) -s -Tlzma.lds -o $@ $^\nendif\n\nclean:\n\trm -f *.o lzma.elf lzma.bin *.tmp *.lds\n"
  },
  {
    "path": "target/linux/generic/image/lzma-loader/src/decompress.c",
    "content": "/*\n * LZMA compressed kernel decompressor for bcm947xx boards\n *\n * Copyright (C) 2005 by Oleg I. Vdovikin <oleg@cs.msu.su>\n *\n * This program is free software; you can redistribute it and/or modify\n * it under the terms of the GNU General Public License as published by\n * the Free Software Foundation; either version 2 of the License, or\n * (at your option) any later version.\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU\n * General Public License for more details.\n *\n * You should have received a copy of the GNU General Public License\n * along with this program; if not, write to the Free Software\n * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\n *\n *\n * Please note, this was code based on the bunzip2 decompressor code\n * by Manuel Novoa III  (mjn3@codepoet.org), although the only thing left\n * is an idea and part of original vendor code\n *\n *\n * 12-Mar-2005  Mineharu Takahara <mtakahar@yahoo.com>\n *   pass actual output size to decoder (stream mode\n *   compressed input is not a requirement anymore)\n *\n * 24-Apr-2005 Oleg I. Vdovikin\n *   reordered functions using lds script, removed forward decl\n *\n * ??-Nov-2005 Mike Baker\n *   reorder the script as an lzma wrapper; do not depend on flash access\n */\n\n#include \"LzmaDecode.h\"\n\n#define KSEG0\t\t\t0x80000000\n#define KSEG1\t\t\t0xa0000000\n\n#define KSEG1ADDR(a)\t\t((((unsigned)(a)) & 0x1fffffffU) | KSEG1)\n\n#define Index_Invalidate_I\t0x00\n#define Index_Writeback_Inv_D   0x01\n\n#define cache_unroll(base,op)\t\\\n\t__asm__ __volatile__(\t\t\\\n\t\t\".set noreorder;\\n\"\t\t\\\n\t\t\".set mips3;\\n\"\t\t\t\\\n\t\t\"cache %1, (%0);\\n\"\t\t\\\n\t\t\".set mips0;\\n\"\t\t\t\\\n\t\t\".set reorder\\n\"\t\t\\\n\t\t:\t\t\t\t\t\t\\\n\t\t: \"r\" (base),\t\t\t\\\n\t\t  \"i\" (op));\n\n\nstatic __inline__ void blast_icache(unsigned long size, unsigned long lsize)\n{\n\tunsigned long start = KSEG0;\n\tunsigned long end = (start + size);\n\n\twhile(start < end) {\n\t\tcache_unroll(start,Index_Invalidate_I);\n\t\tstart += lsize;\n\t}\n}\n\nstatic __inline__ void blast_dcache(unsigned long size, unsigned long lsize)\n{\n\tunsigned long start = KSEG0;\n\tunsigned long end = (start + size);\n\n\twhile(start < end) {\n\t\tcache_unroll(start,Index_Writeback_Inv_D);\n\t\tstart += lsize;\n\t}\n}\n\nunsigned char *data;\n\nstatic int read_byte(void *object, unsigned char **buffer, UInt32 *bufferSize)\n{\n\t*bufferSize = 1;\n\t*buffer = data;\n\t++data;\n\treturn LZMA_RESULT_OK;\n}\n\nstatic __inline__ unsigned char get_byte(void)\n{\n\tunsigned char *buffer;\n\tUInt32 fake;\n\t\n\treturn read_byte(0, &buffer, &fake), *buffer;\n}\n\n/* This puts lzma workspace 128k below RAM end. \n * That should be enough for both lzma and stack\n */\nstatic char *buffer = (char *)(RAMSTART + RAMSIZE - 0x00020000);\nextern char lzma_start[];\nextern char lzma_end[];\n\n/* should be the first function */\nvoid entry(unsigned long icache_size, unsigned long icache_lsize, \n\tunsigned long dcache_size, unsigned long dcache_lsize)\n{\n\tunsigned int i;  /* temp value */\n\tunsigned int osize; /* uncompressed size */\n\tvolatile unsigned int arg0, arg1, arg2, arg3;\n\n\t/* restore argument registers */\n\t__asm__ __volatile__ (\"ori %0, $12, 0\":\"=r\"(arg0));\n\t__asm__ __volatile__ (\"ori %0, $13, 0\":\"=r\"(arg1));\n\t__asm__ __volatile__ (\"ori %0, $14, 0\":\"=r\"(arg2));\n\t__asm__ __volatile__ (\"ori %0, $15, 0\":\"=r\"(arg3));\n\n\tILzmaInCallback callback;\n\tCLzmaDecoderState vs;\n\tcallback.Read = read_byte;\n\n\tdata = lzma_start;\n\n\t/* lzma args */\n\ti = get_byte();\n\tvs.Properties.lc = i % 9, i = i / 9;\n\tvs.Properties.lp = i % 5, vs.Properties.pb = i / 5;\n\n\tvs.Probs = (CProb *)buffer;\n\n\t/* skip rest of the LZMA coder property */\n\tfor (i = 0; i < 4; i++)\n\t\tget_byte();\n\n\t/* read the lower half of uncompressed size in the header */\n\tosize = ((unsigned int)get_byte()) +\n\t\t((unsigned int)get_byte() << 8) +\n\t\t((unsigned int)get_byte() << 16) +\n\t\t((unsigned int)get_byte() << 24);\n\n\t/* skip rest of the header (upper half of uncompressed size) */\n\tfor (i = 0; i < 4; i++) \n\t\tget_byte();\n\n\t/* decompress kernel */\n\tif ((i = LzmaDecode(&vs, &callback,\n\t(unsigned char*)KERNEL_ENTRY, osize, &osize)) == LZMA_RESULT_OK)\n\t{\n\t\tblast_dcache(dcache_size, dcache_lsize);\n\t\tblast_icache(icache_size, icache_lsize);\n\n\t\t/* Jump to load address */\n\t\t((void (*)(int a0, int a1, int a2, int a3)) KERNEL_ENTRY)(arg0, arg1, arg2, arg3);\n\t}\n}\n"
  },
  {
    "path": "target/linux/generic/image/lzma-loader/src/lzma-copy.lds.in",
    "content": "OUTPUT_ARCH(mips)\nENTRY(_start)\nSECTIONS\n{\n  /* Read-only sections, merged into text segment: */\n  . = @LOADADDR@;\n  .text      :\n  {\n    _ftext = . ;\n    *(.text)\n    *(.rodata)\n  } =0\n\n  .reginfo : { *(.reginfo) }\n\n  .bss       :\n  {\n   *(.bss)\n  }\n}\n"
  },
  {
    "path": "target/linux/generic/image/lzma-loader/src/lzma.lds.in",
    "content": "OUTPUT_ARCH(mips)\nENTRY(@ENTRY@)\nSECTIONS\n{\n  /* Read-only sections, merged into text segment: */\n  . = @LOADADDR@;\n  .text      :\n  {\n    _ftext = . ;\n    *(.text.entry)\n    *(.text)\n    *(.rodata)\n    lzma_start = .;\n    kernel.o\n    lzma_end = .;\n  } =0\n\n  .reginfo : { *(.reginfo) }\n\n  .bss       :\n  {\n   *(.bss)\n  }\n}\n"
  },
  {
    "path": "target/linux/generic/image/lzma-loader/src/print.c",
    "content": "/*\n * Copyright (C) 2001 MontaVista Software Inc.\n * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net\n *\n * This program is free software; you can redistribute  it and/or modify it\n * under  the terms of  the GNU General  Public License as published by the\n * Free Software Foundation;  either version 2 of the  License, or (at your\n * option) any later version.\n *\n */\n\n#include\t\"print.h\"\n\n/* macros */\n#define\t\tIsDigit(x)\t( ((x) >= '0') && ((x) <= '9') )\n#define\t\tCtod(x)\t\t( (x) - '0')\n\n/* forward declaration */\nextern int PrintChar(char *, char, int, int);\nextern int PrintString(char *, char *, int, int);\nextern int PrintNum(char *, unsigned long, int, int, int, int, char, int);\n\n/* private variable */\nstatic const char theFatalMsg[] = \"fatal error in lp_Print!\";\n\n/* -*-\n * A low level printf() function.\n */\nvoid\nlp_Print(void (*output)(void *, char *, int), \n\t void * arg,\n\t char *fmt, \n\t va_list ap)\n{\n\n#define \tOUTPUT(arg, s, l)  \\\n  { if (((l) < 0) || ((l) > LP_MAX_BUF)) { \\\n       (*output)(arg, (char*)theFatalMsg, sizeof(theFatalMsg)-1); for(;;); \\\n    } else { \\\n      (*output)(arg, s, l); \\\n    } \\\n  }\n    \n    char buf[LP_MAX_BUF];\n\n    char c;\n    char *s;\n    long int num;\n\n    int longFlag;\n    int negFlag;\n    int width;\n    int prec;\n    int ladjust;\n    char padc;\n\n    int length;\n\n    for(;;) {\n\t{ \n\t    /* scan for the next '%' */\n\t    char *fmtStart = fmt;\n\t    while ( (*fmt != '\\0') && (*fmt != '%')) {\n\t\tfmt ++;\n\t    }\n\n\t    /* flush the string found so far */\n\t    OUTPUT(arg, fmtStart, fmt-fmtStart);\n\n\t    /* are we hitting the end? */\n\t    if (*fmt == '\\0') break;\n\t}\n\n\t/* we found a '%' */\n\tfmt ++;\n\t\n\t/* check for long */\n\tif (*fmt == 'l') {\n\t    longFlag = 1;\n\t    fmt ++;\n\t} else {\n\t    longFlag = 0;\n\t}\n\n\t/* check for other prefixes */\n\twidth = 0;\n\tprec = -1;\n\tladjust = 0;\n\tpadc = ' ';\n\n\tif (*fmt == '-') {\n\t    ladjust = 1;\n\t    fmt ++;\n\t}\n\n\tif (*fmt == '0') {\n\t    padc = '0';\n\t    fmt++;\n\t}\n\n\tif (IsDigit(*fmt)) {\n\t    while (IsDigit(*fmt)) {\n\t\twidth = 10 * width + Ctod(*fmt++);\n\t    }\n\t}\n\n\tif (*fmt == '.') {\n\t    fmt ++;\n\t    if (IsDigit(*fmt)) {\n\t\tprec = 0;\n\t\twhile (IsDigit(*fmt)) {\n\t\t    prec = prec*10 + Ctod(*fmt++);\n\t\t}\n\t    }\n\t}\n\n\n\t/* check format flag */\n\tnegFlag = 0;\n\tswitch (*fmt) {\n\t case 'b':\n\t    if (longFlag) { \n\t\tnum = va_arg(ap, long int); \n\t    } else { \n\t\tnum = va_arg(ap, int);\n\t    }\n\t    length = PrintNum(buf, num, 2, 0, width, ladjust, padc, 0);\n\t    OUTPUT(arg, buf, length);\n\t    break;\n\n\t case 'd':\n\t case 'D':\n\t    if (longFlag) { \n\t\tnum = va_arg(ap, long int);\n\t    } else { \n\t\tnum = va_arg(ap, int); \n\t    }\n\t    if (num < 0) {\n\t\tnum = - num;\n\t\tnegFlag = 1;\n\t    }\n\t    length = PrintNum(buf, num, 10, negFlag, width, ladjust, padc, 0);\n\t    OUTPUT(arg, buf, length);\n\t    break;\n\n\t case 'o':\n\t case 'O':\n\t    if (longFlag) { \n\t\tnum = va_arg(ap, long int);\n\t    } else { \n\t\tnum = va_arg(ap, int); \n\t    }\n\t    length = PrintNum(buf, num, 8, 0, width, ladjust, padc, 0);\n\t    OUTPUT(arg, buf, length);\n\t    break;\n\n\t case 'u':\n\t case 'U':\n\t    if (longFlag) { \n\t\tnum = va_arg(ap, long int);\n\t    } else { \n\t\tnum = va_arg(ap, int); \n\t    }\n\t    length = PrintNum(buf, num, 10, 0, width, ladjust, padc, 0);\n\t    OUTPUT(arg, buf, length);\n\t    break;\n\t    \n\t case 'x':\n\t    if (longFlag) { \n\t\tnum = va_arg(ap, long int);\n\t    } else { \n\t\tnum = va_arg(ap, int); \n\t    }\n\t    length = PrintNum(buf, num, 16, 0, width, ladjust, padc, 0);\n\t    OUTPUT(arg, buf, length);\n\t    break;\n\n\t case 'X':\n\t    if (longFlag) { \n\t\tnum = va_arg(ap, long int);\n\t    } else { \n\t\tnum = va_arg(ap, int); \n\t    }\n\t    length = PrintNum(buf, num, 16, 0, width, ladjust, padc, 1);\n\t    OUTPUT(arg, buf, length);\n\t    break;\n\n\t case 'c':\n\t    c = (char)va_arg(ap, int);\n\t    length = PrintChar(buf, c, width, ladjust);\n\t    OUTPUT(arg, buf, length);\n\t    break;\n\n\t case 's':\n\t    s = (char*)va_arg(ap, char *);\n\t    length = PrintString(buf, s, width, ladjust);\n\t    OUTPUT(arg, buf, length);\n\t    break;\n\n\t case '\\0':\n\t    fmt --;\n\t    break;\n\n\t default:\n\t    /* output this char as it is */\n\t    OUTPUT(arg, fmt, 1);\n\t}\t/* switch (*fmt) */\n\n\tfmt ++;\n    }\t\t/* for(;;) */\n\n    /* special termination call */\n    OUTPUT(arg, \"\\0\", 1);\n}\n\n\n/* --------------- local help functions --------------------- */\nint\nPrintChar(char * buf, char c, int length, int ladjust)\n{\n    int i;\n    \n    if (length < 1) length = 1;\n    if (ladjust) {\n\t*buf = c;\n\tfor (i=1; i< length; i++) buf[i] = ' ';\n    } else {\n\tfor (i=0; i< length-1; i++) buf[i] = ' ';\n\tbuf[length - 1] = c;\n    }\n    return length;\n}\n\nint\nPrintString(char * buf, char* s, int length, int ladjust)\n{\n    int i;\n    int len=0;\n    char* s1 = s;\n    while (*s1++) len++;\n    if (length < len) length = len;\n\n    if (ladjust) {\n\tfor (i=0; i< len; i++) buf[i] = s[i];\n\tfor (i=len; i< length; i++) buf[i] = ' ';\n    } else {\n\tfor (i=0; i< length-len; i++) buf[i] = ' ';\n\tfor (i=length-len; i < length; i++) buf[i] = s[i-length+len];\n    }\n    return length;\n}\n\nint\nPrintNum(char * buf, unsigned long u, int base, int negFlag, \n\t int length, int ladjust, char padc, int upcase)\n{\n    /* algorithm :\n     *  1. prints the number from left to right in reverse form.\n     *  2. fill the remaining spaces with padc if length is longer than\n     *     the actual length\n     *     TRICKY : if left adjusted, no \"0\" padding.\n     *\t\t    if negtive, insert  \"0\" padding between \"0\" and number.\n     *  3. if (!ladjust) we reverse the whole string including paddings\n     *  4. otherwise we only reverse the actual string representing the num.\n     */\n\n    int actualLength =0;\n    char *p = buf;\n    int i;\n\n    do {\n\tint tmp = u %base;\n\tif (tmp <= 9) {\n\t    *p++ = '0' + tmp;\n\t} else if (upcase) {\n\t    *p++ = 'A' + tmp - 10;\n\t} else {\n\t    *p++ = 'a' + tmp - 10;\n\t}\n\tu /= base;\n    } while (u != 0);\n\n    if (negFlag) {\n\t*p++ = '-';\n    }\n\n    /* figure out actual length and adjust the maximum length */\n    actualLength = p - buf;\n    if (length < actualLength) length = actualLength;\n\n    /* add padding */\n    if (ladjust) {\n\tpadc = ' ';\n    }\n    if (negFlag && !ladjust && (padc == '0')) {\n\tfor (i = actualLength-1; i< length-1; i++) buf[i] = padc;\n\tbuf[length -1] = '-';\n    } else {\n\tfor (i = actualLength; i< length; i++) buf[i] = padc;\n    }\n\t    \n\n    /* prepare to reverse the string */\n    {\n\tint begin = 0;\n\tint end;\n\tif (ladjust) {\n\t    end = actualLength - 1;\n\t} else {\n\t    end = length -1;\n\t}\n\n\twhile (end > begin) {\n\t    char tmp = buf[begin];\n\t    buf[begin] = buf[end];\n\t    buf[end] = tmp;\n\t    begin ++;\n\t    end --;\n\t}\n    }\n\n    /* adjust the string pointer */\n    return length;\n}\n"
  },
  {
    "path": "target/linux/generic/image/lzma-loader/src/print.h",
    "content": "/*\n * Copyright (C) 2001 MontaVista Software Inc.\n * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net\n *\n * This program is free software; you can redistribute  it and/or modify it\n * under  the terms of  the GNU General  Public License as published by the\n * Free Software Foundation;  either version 2 of the  License, or (at your\n * option) any later version.\n *\n */\n\n#ifndef _print_h_\n#define _print_h_\n\n#include <stdarg.h>\n\n/* this is the maximum width for a variable */\n#define\t\tLP_MAX_BUF\t80\n\n/* -*-\n * output function takes an void pointer which is passed in as the\n * second argument in lp_Print().  This black-box argument gives output\n * function a way to track state.\n *\n * The second argument in output function is a pointer to char buffer.\n * The third argument specifies the number of chars to outputed.\n *\n * output function cannot assume the buffer is null-terminated after\n * l number of chars.\n */\nvoid lp_Print(void (*output)(void *, char *, int), \n\t      void * arg,\n\t      char *fmt, \n\t      va_list ap);\n\n#endif\n"
  },
  {
    "path": "target/linux/generic/image/lzma-loader/src/printf.c",
    "content": "/*\n * Copyright (C) 2001 MontaVista Software Inc.\n * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net\n *\n * This program is free software; you can redistribute  it and/or modify it\n * under  the terms of  the GNU General  Public License as published by the\n * Free Software Foundation;  either version 2 of the  License, or (at your\n * option) any later version.\n *\n */\n\n#include \"printf.h\"\n#include \"print.h\"\n#include \"uart16550.h\"\n\nstatic void myoutput(void *arg, char *s, int l)\n{\n    int i;\n\n    // special termination call\n    if ((l==1) && (s[0] == '\\0')) return;\n    \n    for (i=0; i< l; i++) {\n\tUart16550Put(s[i]);\n\tif (s[i] == '\\n') Uart16550Put('\\r');\n    }\n}\n\nvoid printf(char *fmt, ...)\n{\n    va_list ap;\n    va_start(ap, fmt);\n    lp_Print(myoutput, 0, fmt, ap);\n    va_end(ap);\n}\n"
  },
  {
    "path": "target/linux/generic/image/lzma-loader/src/printf.h",
    "content": "/*\n * Copyright (C) 2001 MontaVista Software Inc.\n * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net\n *\n * This program is free software; you can redistribute  it and/or modify it\n * under  the terms of  the GNU General  Public License as published by the\n * Free Software Foundation;  either version 2 of the  License, or (at your\n * option) any later version.\n *\n */\n\n#ifndef _printf_h_\n#define _printf_h_\n\n#include <stdarg.h>\nvoid printf(char *fmt, ...);\n\n#endif /* _printf_h_ */\n"
  },
  {
    "path": "target/linux/generic/image/lzma-loader/src/start.S",
    "content": "#include <asm/asm.h>\n#include <asm/regdef.h>\n\n#define KSEG0\t\t0x80000000\n\n#define C0_CONFIG\t$16\n#define C0_TAGLO\t$28\n#define C0_TAGHI\t$29\n\n#define\tCONF1_DA_SHIFT\t7\t\t\t/* D$ associativity */\n#define CONF1_DA_MASK\t0x00000380\n#define CONF1_DA_BASE\t1\n#define CONF1_DL_SHIFT\t10\t\t\t/* D$ line size */\n#define CONF1_DL_MASK\t0x00001c00\n#define CONF1_DL_BASE\t2\n#define CONF1_DS_SHIFT\t13\t\t\t/* D$ sets/way */\n#define CONF1_DS_MASK\t0x0000e000\n#define CONF1_DS_BASE\t64\n#define CONF1_IA_SHIFT\t16\t\t\t/* I$ associativity */\n#define CONF1_IA_MASK\t0x00070000\n#define CONF1_IA_BASE\t1\n#define CONF1_IL_SHIFT\t19\t\t\t/* I$ line size */\n#define CONF1_IL_MASK\t0x00380000\n#define CONF1_IL_BASE\t2\n#define CONF1_IS_SHIFT\t22\t\t\t/* Instruction cache sets/way */\n#define CONF1_IS_MASK\t0x01c00000\n#define CONF1_IS_BASE\t64\n\n#define Index_Invalidate_I\t0x00\n#define Index_Writeback_Inv_D   0x01\n\nLEAF(_start)\n\n\t.set\tmips32\n\t.set noreorder\n\n\t/* save argument registers */\n\tmove t4, a0\n\tmove t5, a1\n\tmove t6, a2\n\tmove t7, a3\n\n\t/* set up stack */\n\tli\tsp, RAMSTART + RAMSIZE - 16\n\n#ifdef IMAGE_COPY\n\t/* Copy decompressor code to the right place */\n\tli  t2, LOADADDR\n\tadd a0, t2, 0\n\tla  a1, code_start\n\tla  a2, code_stop\n$L1:\n\tlw  t0, 0(a1)\n\tsw  t0, 0(a0)\n\tadd a1, 4\n\tadd a0, 4\n\tblt a1, a2, $L1\n\tnop\n#endif\n\n\t/* At this point we need to invalidate dcache and */\n\t/* icache before jumping to new code */\n\n1:\t/* Get cache sizes */\n\tmfc0\ts0,C0_CONFIG,1\n\n\tli\ts1,CONF1_DL_MASK\n\tand\ts1,s0\n\tbeq\ts1,zero,nodc\n\tnop\n\n\tsrl\ts1,CONF1_DL_SHIFT\n\tli\tt0,CONF1_DL_BASE\n\tsll\ts1,t0,s1\t\t/* s1 has D$ cache line size */\n\n\tli\ts2,CONF1_DA_MASK\n\tand\ts2,s0\n\tsrl\ts2,CONF1_DA_SHIFT\n\taddiu\ts2,CONF1_DA_BASE\t/* s2 now has D$ associativity */\n\n\tli\tt0,CONF1_DS_MASK\n\tand\tt0,s0\n\tsrl\tt0,CONF1_DS_SHIFT\n\tli\ts3,CONF1_DS_BASE\n\tsll\ts3,s3,t0\t\t/* s3 has D$ sets per way */\n\n\tmultu\ts2,s3\t\t\t/* sets/way * associativity */\n\tmflo\tt0\t\t\t/* total cache lines */\n\n\tmultu\ts1,t0\t\t\t/* D$ linesize * lines */\n\tmflo\ts2\t\t\t/* s2 is now D$ size in bytes */\n\n\t/* Initilize the D$: */\n\tmtc0\tzero,C0_TAGLO\n\tmtc0\tzero,C0_TAGHI\n\n\tli\tt0,KSEG0\t\t/* Just an address for the first $ line */\n\taddu\tt1,t0,s2\t\t/*  + size of cache == end */\n\n1:\tcache\tIndex_Writeback_Inv_D,0(t0)\n\tbne\tt0,t1,1b\n\taddu\tt0,s1\n\nnodc:\n\t/* Now we get to do it all again for the I$ */\n\n\tmove\ts3,zero\t\t\t/* just in case there is no icache */\n\tmove\ts4,zero\n\n\tli\tt0,CONF1_IL_MASK\n\tand\tt0,s0\n\tbeq\tt0,zero,noic\n\tnop\n\n\tsrl\tt0,CONF1_IL_SHIFT\n\tli\ts3,CONF1_IL_BASE\n\tsll\ts3,t0\t\t\t/* s3 has I$ cache line size */\n\n\tli\tt0,CONF1_IA_MASK\n\tand\tt0,s0\n\tsrl\tt0,CONF1_IA_SHIFT\n\taddiu\ts4,t0,CONF1_IA_BASE\t/* s4 now has I$ associativity */\n\n\tli\tt0,CONF1_IS_MASK\n\tand\tt0,s0\n\tsrl\tt0,CONF1_IS_SHIFT\n\tli\ts5,CONF1_IS_BASE\n\tsll\ts5,t0\t\t\t/* s5 has I$ sets per way */\n\n\tmultu\ts4,s5\t\t\t/* sets/way * associativity */\n\tmflo\tt0\t\t\t/* s4 is now total cache lines */\n\n\tmultu\ts3,t0\t\t\t/* I$ linesize * lines */\n\tmflo\ts4\t\t\t/* s4 is cache size in bytes */\n\n\t/* Initilize the I$: */\n\tmtc0\tzero,C0_TAGLO\n\tmtc0\tzero,C0_TAGHI\n\n\tli\tt0,KSEG0\t\t/* Just an address for the first $ line */\n\taddu\tt1,t0,s4\t\t/*  + size of cache == end */\n\n1:\tcache\tIndex_Invalidate_I,0(t0)\n\tbne\tt0,t1,1b\n\taddu\tt0,s3\nnoic:\n\t/* jump to main */\n\tmove    a0,s4\t\t\t/* icache size */\n\tmove    a1,s3\t\t\t/* icache line size */\n\tmove    a2,s2\t\t\t/* dcache size */\n#ifdef IMAGE_COPY\n\tjal\t\tt2\n#else\n\tjal     entry\n#endif\n\tmove    a3,s1\t\t\t/* dcache line size */\n\n\t.set reorder\nEND(_start)\n\n"
  },
  {
    "path": "target/linux/generic/image/lzma-loader/src/uart16550.c",
    "content": "/*\n * Copyright (C) 2001 MontaVista Software Inc.\n * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net\n *\n * This program is free software; you can redistribute  it and/or modify it\n * under  the terms of  the GNU General  Public License as published by the\n * Free Software Foundation;  either version 2 of the  License, or (at your\n * option) any later version.\n *\n */\n\n\n#include \"uart16550.h\"\n\n/* === CONFIG === */\n\n#define         BASE                    0xb8058000\n#define         MAX_BAUD                1152000\n#define         REG_OFFSET              4\n\n/* === END OF CONFIG === */\n\n/* register offset */\n#define         OFS_RCV_BUFFER          (0*REG_OFFSET)\n#define         OFS_TRANS_HOLD          (0*REG_OFFSET)\n#define         OFS_SEND_BUFFER         (0*REG_OFFSET)\n#define         OFS_INTR_ENABLE         (1*REG_OFFSET)\n#define         OFS_INTR_ID             (2*REG_OFFSET)\n#define         OFS_DATA_FORMAT         (3*REG_OFFSET)\n#define         OFS_LINE_CONTROL        (3*REG_OFFSET)\n#define         OFS_MODEM_CONTROL       (4*REG_OFFSET)\n#define         OFS_RS232_OUTPUT        (4*REG_OFFSET)\n#define         OFS_LINE_STATUS         (5*REG_OFFSET)\n#define         OFS_MODEM_STATUS        (6*REG_OFFSET)\n#define         OFS_RS232_INPUT         (6*REG_OFFSET)\n#define         OFS_SCRATCH_PAD         (7*REG_OFFSET)\n\n#define         OFS_DIVISOR_LSB         (0*REG_OFFSET)\n#define         OFS_DIVISOR_MSB         (1*REG_OFFSET)\n\n\n/* memory-mapped read/write of the port */\n#define         UART16550_READ(y)    (*((volatile uint32*)(BASE + y)))\n#define         UART16550_WRITE(y, z)  ((*((volatile uint32*)(BASE + y))) = z)\n\n#define DEBUG_LED (*(unsigned short*)0xb7ffffc0)\n#define OutputLED(x)  (DEBUG_LED = x)\n\nvoid Uart16550Init(uint32 baud, uint8 data, uint8 parity, uint8 stop)\n{\n    /* disable interrupts */\n    UART16550_WRITE(OFS_INTR_ENABLE, 0);\n\n    /* set up buad rate */\n    { \n        uint32 divisor;\n       \n        /* set DIAB bit */\n        UART16550_WRITE(OFS_LINE_CONTROL, 0x80);\n        \n        /* set divisor */\n        divisor = MAX_BAUD / baud;\n        UART16550_WRITE(OFS_DIVISOR_LSB, divisor & 0xff);\n        UART16550_WRITE(OFS_DIVISOR_MSB, (divisor & 0xff00)>>8);\n\n        /* clear DIAB bit */\n        UART16550_WRITE(OFS_LINE_CONTROL, 0x0);\n    }\n\n    /* set data format */\n    UART16550_WRITE(OFS_DATA_FORMAT, data | parity | stop);\n}\n\nuint8 Uart16550GetPoll()\n{\n    while((UART16550_READ(OFS_LINE_STATUS) & 0x1) == 0);\n    return UART16550_READ(OFS_RCV_BUFFER);\n}\n\n\nvoid Uart16550Put(uint8 byte)\n{\n    while ((UART16550_READ(OFS_LINE_STATUS) &0x20) == 0);\n    UART16550_WRITE(OFS_SEND_BUFFER, byte);\n}\n\n"
  },
  {
    "path": "target/linux/generic/image/lzma-loader/src/uart16550.h",
    "content": "/*\n * Copyright (C) 2001 MontaVista Software Inc.\n * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net\n *\n * This program is free software; you can redistribute  it and/or modify it\n * under  the terms of  the GNU General  Public License as published by the\n * Free Software Foundation;  either version 2 of the  License, or (at your\n * option) any later version.\n *\n */\n\n#ifndef _uart16550_h_\n#define _uart16550_h_\n\ntypedef         unsigned char uint8;\ntypedef         unsigned int  uint32;\n\n#define         UART16550_BAUD_2400             2400\n#define         UART16550_BAUD_4800             4800\n#define         UART16550_BAUD_9600             9600\n#define         UART16550_BAUD_19200            19200\n#define         UART16550_BAUD_38400            38400\n#define         UART16550_BAUD_57600            57600\n#define         UART16550_BAUD_115200           115200\n\n#define         UART16550_PARITY_NONE           0\n#define         UART16550_PARITY_ODD            0x08\n#define         UART16550_PARITY_EVEN           0x18\n#define         UART16550_PARITY_MARK           0x28\n#define         UART16550_PARITY_SPACE          0x38\n\n#define         UART16550_DATA_5BIT             0x0\n#define         UART16550_DATA_6BIT             0x1\n#define         UART16550_DATA_7BIT             0x2\n#define         UART16550_DATA_8BIT             0x3\n\n#define         UART16550_STOP_1BIT             0x0\n#define         UART16550_STOP_2BIT             0x4\n\nvoid Uart16550Init(uint32 baud, uint8 data, uint8 parity, uint8 stop);\n\n/* blocking call */\nuint8 Uart16550GetPoll();\n\nvoid Uart16550Put(uint8 byte);\n\n#endif\n"
  },
  {
    "path": "target/linux/generic/image/relocate/Makefile",
    "content": "#\n# Makefile for the kernel relocation stub for MIPS devices\n#\n# Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>\n# Copyright (C) 2015 Felix Fietkau <nbd@nbd.name>\n#\n# Some parts of this file was based on the OpenWrt specific lzma-loader\n# for the BCM47xx and ADM5120 based boards:\n#\tCopyright (C) 2004 Manuel Novoa III (mjn3@codepoet.org)\n#\tCopyright (C) 2005 Mineharu Takahara <mtakahar@yahoo.com>\n#\tCopyright (C) 2005 by Oleg I. Vdovikin <oleg@cs.msu.su>\n#\n# This program is free software; you can redistribute it and/or modify it\n# under the terms of the GNU General Public License version 2 as published\n# by the Free Software Foundation.\n#\n\nLOADADDR\t:=\nLZMA_TEXT_START\t:= 0x81000000\nLOADER_DATA\t:=\nBOARD\t\t:=\nFLASH_OFFS\t:=\nFLASH_MAX\t:=\nPLATFORM\t:=\nCACHELINE_SIZE\t:= 32\n\nCC\t\t:= $(CROSS_COMPILE)gcc\nLD\t\t:= $(CROSS_COMPILE)ld\nOBJCOPY\t\t:= $(CROSS_COMPILE)objcopy\nOBJDUMP\t\t:= $(CROSS_COMPILE)objdump\n\nBIN_FLAGS\t:= -O binary -R .reginfo -R .note -R .comment -R .mdebug \\\n\t\t   -R .MIPS.abiflags -S\n\nCFLAGS\t\t= -D__KERNEL__ -Wall -Wstrict-prototypes -Wno-trigraphs -Os \\\n\t\t  -fno-strict-aliasing -fno-common -fomit-frame-pointer -G 0 \\\n\t\t  -mno-abicalls -fno-pic -ffunction-sections -pipe -mlong-calls \\\n\t\t  -fno-common -ffreestanding -fhonour-copts \\\n\t\t  -mabi=32 -march=mips32r2 \\\n\t\t  -Wa,-32 -Wa,-march=mips32r2 -Wa,-mips32r2 -Wa,--trap \\\n\t\t  -DCONFIG_CACHELINE_SIZE=$(CACHELINE_SIZE) \\\n\t\t  -DKERNEL_ADDR=$(KERNEL_ADDR)\n\nASFLAGS\t\t= $(CFLAGS) -D__ASSEMBLY__\n\nLDFLAGS\t\t= -static --gc-sections -no-warn-mismatch\nLDFLAGS\t\t+= -e startup -T loader.lds -Ttext $(LZMA_TEXT_START)\n\nO_FORMAT \t= $(shell $(OBJDUMP) -i | head -2 | grep elf32)\n\nOBJECTS\t\t:= head.o\n\nall: head.o loader.bin\n\n# Don't build dependencies, this may die if $(CC) isn't gcc\ndep:\n\ninstall:\n\n%.o : %.c\n\t$(CC) $(CFLAGS) -c -o $@ $<\n\n%.o : %.S\n\t$(CC) $(ASFLAGS) -c -o $@ $<\n\nloader: $(OBJECTS)\n\t$(LD) $(LDFLAGS) -o $@ $(OBJECTS)\n\nloader.bin: loader\n\t$(OBJCOPY) $(BIN_FLAGS) $< $@\n\nmrproper: clean\n\nclean:\n\trm -f loader *.elf *.bin *.o\n"
  },
  {
    "path": "target/linux/generic/image/relocate/cacheops.h",
    "content": "/*\n * Cache operations for the cache instruction.\n *\n * This file is subject to the terms and conditions of the GNU General Public\n * License.  See the file \"COPYING\" in the main directory of this archive\n * for more details.\n *\n * (C) Copyright 1996, 97, 99, 2002, 03 Ralf Baechle\n * (C) Copyright 1999 Silicon Graphics, Inc.\n */\n#ifndef\t__ASM_CACHEOPS_H\n#define\t__ASM_CACHEOPS_H\n\n/*\n * Cache Operations available on all MIPS processors with R4000-style caches\n */\n#define Index_Invalidate_I      0x00\n#define Index_Writeback_Inv_D   0x01\n#define Index_Load_Tag_I\t0x04\n#define Index_Load_Tag_D\t0x05\n#define Index_Store_Tag_I\t0x08\n#define Index_Store_Tag_D\t0x09\n#if defined(CONFIG_CPU_LOONGSON2)\n#define Hit_Invalidate_I\t0x00\n#else\n#define Hit_Invalidate_I\t0x10\n#endif\n#define Hit_Invalidate_D\t0x11\n#define Hit_Writeback_Inv_D\t0x15\n\n/*\n * R4000-specific cacheops\n */\n#define Create_Dirty_Excl_D\t0x0d\n#define Fill\t\t\t0x14\n#define Hit_Writeback_I\t\t0x18\n#define Hit_Writeback_D\t\t0x19\n\n/*\n * R4000SC and R4400SC-specific cacheops\n */\n#define Index_Invalidate_SI     0x02\n#define Index_Writeback_Inv_SD  0x03\n#define Index_Load_Tag_SI\t0x06\n#define Index_Load_Tag_SD\t0x07\n#define Index_Store_Tag_SI\t0x0A\n#define Index_Store_Tag_SD\t0x0B\n#define Create_Dirty_Excl_SD\t0x0f\n#define Hit_Invalidate_SI\t0x12\n#define Hit_Invalidate_SD\t0x13\n#define Hit_Writeback_Inv_SD\t0x17\n#define Hit_Writeback_SD\t0x1b\n#define Hit_Set_Virtual_SI\t0x1e\n#define Hit_Set_Virtual_SD\t0x1f\n\n/*\n * R5000-specific cacheops\n */\n#define R5K_Page_Invalidate_S\t0x17\n\n/*\n * RM7000-specific cacheops\n */\n#define Page_Invalidate_T\t0x16\n\n/*\n * R10000-specific cacheops\n *\n * Cacheops 0x02, 0x06, 0x0a, 0x0c-0x0e, 0x16, 0x1a and 0x1e are unused.\n * Most of the _S cacheops are identical to the R4000SC _SD cacheops.\n */\n#define Index_Writeback_Inv_S\t0x03\n#define Index_Load_Tag_S\t0x07\n#define Index_Store_Tag_S\t0x0B\n#define Hit_Invalidate_S\t0x13\n#define Cache_Barrier\t\t0x14\n#define Hit_Writeback_Inv_S\t0x17\n#define Index_Load_Data_I\t0x18\n#define Index_Load_Data_D\t0x19\n#define Index_Load_Data_S\t0x1b\n#define Index_Store_Data_I\t0x1c\n#define Index_Store_Data_D\t0x1d\n#define Index_Store_Data_S\t0x1f\n\n#endif\t/* __ASM_CACHEOPS_H */\n"
  },
  {
    "path": "target/linux/generic/image/relocate/cp0regdef.h",
    "content": "/*\n * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle\n *\n * Copyright (C) 2001, Monta Vista Software\n * Author: jsun@mvista.com or jsun@junsun.net\n */\n#ifndef _cp0regdef_h_\n#define _cp0regdef_h_\n\n#define CP0_INDEX $0\n#define CP0_RANDOM $1\n#define CP0_ENTRYLO0 $2\n#define CP0_ENTRYLO1 $3\n#define CP0_CONTEXT $4\n#define CP0_PAGEMASK $5\n#define CP0_WIRED $6\n#define CP0_BADVADDR $8\n#define CP0_COUNT $9\n#define CP0_ENTRYHI $10\n#define CP0_COMPARE $11\n#define CP0_STATUS $12\n#define CP0_CAUSE $13\n#define CP0_EPC $14\n#define CP0_PRID $15\n#define CP0_CONFIG $16\n#define CP0_LLADDR $17\n#define CP0_WATCHLO $18\n#define CP0_WATCHHI $19\n#define CP0_XCONTEXT $20\n#define CP0_FRAMEMASK $21\n#define CP0_DIAGNOSTIC $22\n#define CP0_PERFORMANCE $25\n#define CP0_ECC $26\n#define CP0_CACHEERR $27\n#define CP0_TAGLO $28\n#define CP0_TAGHI $29\n#define CP0_ERROREPC $30\n\n#endif\n"
  },
  {
    "path": "target/linux/generic/image/relocate/head.S",
    "content": "/*\n * Kernel relocation stub for MIPS devices\n *\n * Copyright (C) 2015 Felix Fietkau <nbd@nbd.name>\n *\n * Based on:\n *\n * LZMA compressed kernel loader for Atheros AR7XXX/AR9XXX based boards\n *\n * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>\n *\n * Some parts of this code was based on the OpenWrt specific lzma-loader\n * for the BCM47xx and ADM5120 based boards:\n *\tCopyright (C) 2004 Manuel Novoa III (mjn3@codepoet.org)\n *\tCopyright (C) 2005 by Oleg I. Vdovikin <oleg@cs.msu.su>\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of the GNU General Public License version 2 as published\n * by the Free Software Foundation.\n */\n\n#include <asm/asm.h>\n#include <asm/regdef.h>\n#include \"cp0regdef.h\"\n#include \"cacheops.h\"\n\n#define KSEG0\t\t0x80000000\n\n\t.macro\tehb\n\tsll     zero, 3\n\t.endm\n\n\t.macro reset\n\tli t0, 0xbe000034\n\tlw t1, 0(t0)\n\tori t1, 1\n\tsw t1, 0(t0)\n\t.endm\n\n\t.text\n\nLEAF(startup)\n\t.set noreorder\n\t.set mips32\n\n\t.fill 0x10000\n\n\tmtc0\tzero, CP0_WATCHLO\t# clear watch registers\n\tmtc0\tzero, CP0_WATCHHI\n\tmtc0\tzero, CP0_CAUSE\t\t# clear before writing status register\n\n\tmfc0\tt0, CP0_STATUS\n\tli\tt1, 0x1000001f\n\tor\tt0, t1\n\txori\tt0, 0x1f\n\tmtc0\tt0, CP0_STATUS\n\tehb\n\n\tmtc0\tzero, CP0_COUNT\n\tmtc0\tzero, CP0_COMPARE\n\tehb\n\n\tla\tt0, __reloc_label\t# get linked address of label\n\tbal\t__reloc_label\t\t# branch and link to label to\n\tnop\t\t\t\t# get actual address\n__reloc_label:\n\tsubu\tt0, ra, t0\t\t# get reloc_delta\n\n\t/* Copy our code to the right place */\n\tla\tt1, _code_start\t\t# get linked address of _code_start\n\tla\tt2, _code_end\t\t# get linked address of _code_end\n\n\taddu\tt4, t2, t0\t\t# calculate actual address of _code_end\n\tlw\tt5, 0(t4)\t\t# get extra data size\n\n\tadd\tt2, t5\n\tadd\tt2, 4\n\n\tadd\tt0, t1\t\t\t# calculate actual address of _code_start\n\n__reloc_copy:\n\tlw\tt3, 0(t0)\n\tsw\tt3, 0(t1)\n\tadd\tt1, 4\n\tblt\tt1, t2, __reloc_copy\n\tadd\tt0, 4\n\n\t/* flush cache */\n\tla\tt0, _code_start\n\tla\tt1, _code_end\n\n\tli\tt2, ~(CONFIG_CACHELINE_SIZE - 1)\n\tand\tt0, t2\n\tand\tt1, t2\n\tli\tt2, CONFIG_CACHELINE_SIZE\n\n\tb\t__flush_check\n\tnop\n\n__flush_line:\n\tcache\tHit_Writeback_Inv_D, 0(t0)\n\tcache\tHit_Invalidate_I, 0(t0)\n\tadd\tt0, t2\n\n__flush_check:\n\tbne\tt0, t1, __flush_line\n\tnop\n\n\tsync\n\n\tla\tt0, __reloc_back\n\tj\tt0\n\tnop\n\n__reloc_back:\n\tla\tt0, _code_end\n\tadd\tt0, 4\n\n\taddu\tt1, t0, t5\n\n\tli\tt2, KERNEL_ADDR\n\n__kernel_copy:\n\tlw\tt3, 0(t0)\n\tsw\tt3, 0(t2)\n\tadd\tt0, 4\n\tblt\tt0, t1, __kernel_copy\n\tadd\tt2, 4\n\n\t/* flush cache */\n\tli\tt0, KERNEL_ADDR\n\taddu\tt1, t0, t5\n\n\tadd t1, CONFIG_CACHELINE_SIZE - 1\n\tli\tt2, ~(CONFIG_CACHELINE_SIZE - 1)\n\tand\tt0, t2\n\tand\tt1, t2\n\tli\tt2, CONFIG_CACHELINE_SIZE\n\n\tb\t__kernel_flush_check\n\tnop\n\n__kernel_flush_line:\n\tcache\tHit_Writeback_Inv_D, 0(t0)\n\tcache\tHit_Invalidate_I, 0(t0)\n\tadd\tt0, t2\n\n__kernel_flush_check:\n\tbne\tt0, t1, __kernel_flush_line\n\tnop\n\n\tsync\n\n\tli\tt0, KERNEL_ADDR\n\tjr\tt0\n\tnop\n\n\t.set reorder\nEND(startup)\n"
  },
  {
    "path": "target/linux/generic/image/relocate/loader.lds",
    "content": "OUTPUT_ARCH(mips)\nSECTIONS {\n\t.text : {\n\t\t_code_start = .;\n\t\t*(.text)\n\t\t*(.text.*)\n\t\t*(.rodata)\n\t\t*(.rodata.*)\n\t\t*(.data)\n\t\t*(.data.*)\n\t}\n\n\t. = ALIGN(32);\n\n\t_code_end = .;\n}\n"
  },
  {
    "path": "target/linux/generic/other-files/init",
    "content": "#!/bin/sh\n# Copyright (C) 2006 OpenWrt.org\nexport INITRAMFS=1\n\n# switch to tmpfs to allow run daemons in jail on initramfs boot\nDIRS=$(echo *)\nNEW_ROOT=/new_root\n\nmkdir -p $NEW_ROOT\nmount -t tmpfs tmpfs $NEW_ROOT\n\ncp -pr $DIRS $NEW_ROOT\n\nexec switch_root $NEW_ROOT /sbin/init\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/050-dtc-checks-Drop-interrupt-provider-address-cells-check.patch",
    "content": "From d8d1a9a77863a8c7031ae82a1d461aa78eb72a7b Mon Sep 17 00:00:00 2001\nFrom: Rob Herring <robh@kernel.org>\nDate: Mon, 11 Oct 2021 14:12:43 -0500\nSubject: [PATCH] checks: Drop interrupt provider '#address-cells' check\n\n'#address-cells' is only needed when parsing 'interrupt-map' properties, so\nremove it from the common interrupt-provider test.\n\nCc: Andre Przywara <andre.przywara@arm.com>\nReviewed-by: David Gibson <david@gibson.dropbear.id.au>\nSigned-off-by: Rob Herring <robh@kernel.org>\nMessage-Id: <20211011191245.1009682-3-robh@kernel.org>\nSigned-off-by: David Gibson <david@gibson.dropbear.id.au>\n---\n--- a/scripts/dtc/checks.c\n+++ b/scripts/dtc/checks.c\n@@ -1569,11 +1569,6 @@ static void check_interrupt_provider(str\n \tif (!prop)\n \t\tFAIL(c, dti, node,\n \t\t     \"Missing #interrupt-cells in interrupt provider\");\n-\n-\tprop = get_property(node, \"#address-cells\");\n-\tif (!prop)\n-\t\tFAIL(c, dti, node,\n-\t\t     \"Missing #address-cells in interrupt provider\");\n }\n WARNING(interrupt_provider, check_interrupt_provider, NULL);\n \n"
  },
  {
    "path": "target/linux/generic/pending-5.10/100-compiler.h-only-include-asm-rwonce.h-for-kernel-code.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nDate: Thu, 22 Oct 2020 22:00:03 +0200\nSubject: [PATCH] compiler.h: only include asm/rwonce.h for kernel code\n\nThis header file is not in uapi, which makes any user space code that includes\nlinux/compiler.h to fail with the error 'asm/rwonce.h: No such file or directory'\n\nFixes: e506ea451254 (\"compiler.h: Split {READ,WRITE}_ONCE definitions out into rwonce.h\")\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n\n--- a/include/linux/compiler.h\n+++ b/include/linux/compiler.h\n@@ -213,6 +213,8 @@ void ftrace_likely_update(struct ftrace_\n \t__v;\t\t\t\t\t\t\t\t\\\n })\n \n+#include <asm/rwonce.h>\n+\n #endif /* __KERNEL__ */\n \n /*\n@@ -245,6 +247,4 @@ static inline void *offset_to_ptr(const\n  */\n #define prevent_tail_call_optimization()\tmb()\n \n-#include <asm/rwonce.h>\n-\n #endif /* __LINUX_COMPILER_H */\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/101-Use-stddefs.h-instead-of-compiler.h.patch",
    "content": "--- a/include/uapi/linux/swab.h\n+++ b/include/uapi/linux/swab.h\n@@ -3,7 +3,7 @@\n #define _UAPI_LINUX_SWAB_H\n \n #include <linux/types.h>\n-#include <linux/compiler.h>\n+#include <linux/stddef.h>\n #include <asm/bitsperlong.h>\n #include <asm/swab.h>\n \n"
  },
  {
    "path": "target/linux/generic/pending-5.10/102-MIPS-only-process-negative-stack-offsets-on-stack-tr.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nDate: Wed, 18 Apr 2018 10:50:05 +0200\nSubject: [PATCH] MIPS: only process negative stack offsets on stack traces\n\nFixes endless back traces in cases where the compiler emits a stack\npointer increase in a branch delay slot (probably for some form of\nfunction return).\n\n[    3.475442] BUG: MAX_STACK_TRACE_ENTRIES too low!\n[    3.480070] turning off the locking correctness validator.\n[    3.485521] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.14.34 #0\n[    3.491475] Stack : 00000000 00000000 00000000 00000000 80e0fce2 00000034 00000000 00000000\n[    3.499764]         87c3838c 80696377 8061047c 00000000 00000001 00000001 87c2d850 6534689f\n[    3.508059]         00000000 00000000 80e10000 00000000 00000000 000000cf 0000000f 00000000\n[    3.516353]         00000000 806a0000 00076891 00000000 00000000 00000000 ffffffff 00000000\n[    3.524648]         806c0000 00000004 80e10000 806a0000 00000003 80690000 00000000 80700000\n[    3.532942]         ...\n[    3.535362] Call Trace:\n[    3.537818] [<80010a48>] show_stack+0x58/0x100\n[    3.542207] [<804c2f78>] dump_stack+0xe8/0x170\n[    3.546613] [<80079f90>] save_trace+0xf0/0x110\n[    3.551010] [<8007b1ec>] mark_lock+0x33c/0x78c\n[    3.555413] [<8007bf48>] __lock_acquire+0x2ac/0x1a08\n[    3.560337] [<8007de60>] lock_acquire+0x64/0x8c\n[    3.564846] [<804e1570>] _raw_spin_lock_irqsave+0x54/0x78\n[    3.570186] [<801b618c>] kernfs_notify+0x94/0xac\n[    3.574770] [<801b7b10>] sysfs_notify+0x74/0xa0\n[    3.579257] [<801b618c>] kernfs_notify+0x94/0xac\n[    3.583839] [<801b7b10>] sysfs_notify+0x74/0xa0\n[    3.588329] [<801b618c>] kernfs_notify+0x94/0xac\n[    3.592911] [<801b7b10>] sysfs_notify+0x74/0xa0\n[    3.597401] [<801b618c>] kernfs_notify+0x94/0xac\n[    3.601983] [<801b7b10>] sysfs_notify+0x74/0xa0\n[    3.606473] [<801b618c>] kernfs_notify+0x94/0xac\n[    3.611055] [<801b7b10>] sysfs_notify+0x74/0xa0\n[    3.615545] [<801b618c>] kernfs_notify+0x94/0xac\n[    3.620125] [<801b7b10>] sysfs_notify+0x74/0xa0\n[    3.624619] [<801b618c>] kernfs_notify+0x94/0xac\n[    3.629197] [<801b7b10>] sysfs_notify+0x74/0xa0\n[    3.633691] [<801b618c>] kernfs_notify+0x94/0xac\n[    3.638269] [<801b7b10>] sysfs_notify+0x74/0xa0\n[    3.642763] [<801b618c>] kernfs_notify+0x94/0xac\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n\n--- a/arch/mips/kernel/process.c\n+++ b/arch/mips/kernel/process.c\n@@ -380,6 +380,8 @@ static inline int is_sp_move_ins(union m\n \n \tif (ip->i_format.opcode == addiu_op ||\n \t    ip->i_format.opcode == daddiu_op) {\n+\t\tif (ip->i_format.simmediate > 0)\n+\t\t\treturn 0;\n \t\t*frame_size = -ip->i_format.simmediate;\n \t\treturn 1;\n \t}\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/120-Fix-alloc_node_mem_map-with-ARCH_PFN_OFFSET-calcu.patch",
    "content": "From: Tobias Wolf <dev-NTEO@vplace.de>\nSubject: mm: Fix alloc_node_mem_map with ARCH_PFN_OFFSET calculation\n\nAn rt288x (ralink) based router (Belkin F5D8235 v1) does not boot with any\nkernel beyond version 4.3 resulting in:\n\nBUG: Bad page state in process swapper  pfn:086ac\n\nbisect resulted in:\n\na1c34a3bf00af2cede839879502e12dc68491ad5 is the first bad commit\ncommit a1c34a3bf00af2cede839879502e12dc68491ad5\nAuthor: Laura Abbott <laura@labbott.name>\nDate:   Thu Nov 5 18:48:46 2015 -0800\n\n    mm: Don't offset memmap for flatmem\n\n    Srinivas Kandagatla reported bad page messages when trying to remove the\n    bottom 2MB on an ARM based IFC6410 board\n\n      BUG: Bad page state in process swapper  pfn:fffa8\n      page:ef7fb500 count:0 mapcount:0 mapping:  (null) index:0x0\n      flags: 0x96640253(locked|error|dirty|active|arch_1|reclaim|mlocked)\n      page dumped because: PAGE_FLAGS_CHECK_AT_FREE flag(s) set\n      bad because of flags:\n      flags: 0x200041(locked|active|mlocked)\n      Modules linked in:\n      CPU: 0 PID: 0 Comm: swapper Not tainted 3.19.0-rc3-00007-g412f9ba-dirty\n#816\n      Hardware name: Qualcomm (Flattened Device Tree)\n        unwind_backtrace\n        show_stack\n        dump_stack\n        bad_page\n        free_pages_prepare\n        free_hot_cold_page\n        __free_pages\n        free_highmem_page\n        mem_init\n        start_kernel\n      Disabling lock debugging due to kernel taint\n    [...]\n:040000 040000 2de013c372345fd471cd58f0553c9b38b0ef1cc4\n0a8156f848733dfa21e16c196dfb6c0a76290709 M      mm\n\nThis fix for ARM does not account ARCH_PFN_OFFSET for mem_map as later used by\npage_to_pfn anymore.\n\nThe following output was generated with two hacked in printk statements:\n\nprintk(\"before %p vs. %p or %p\\n\", mem_map, mem_map - offset, mem_map -\n(pgdat->node_start_pfn - ARCH_PFN_OFFSET));\n\t\tif (page_to_pfn(mem_map) != pgdat->node_start_pfn)\n\t\t\tmem_map -= offset + (pgdat->node_start_pfn - ARCH_PFN_OFFSET);\nprintk(\"after %p\\n\", mem_map);\n\nOutput:\n\n[    0.000000] before 8861b280 vs. 8861b280 or 8851b280\n[    0.000000] after 8851b280\n\nAs seen in the first line mem_map with subtraction of offset does not equal the\nmem_map after subtraction of ARCH_PFN_OFFSET.\n\nAfter adding the offset of ARCH_PFN_OFFSET as well to mem_map as the\npreviously calculated offset is zero for the named platform it is able to boot\n4.4 and 4.9-rc7 again.\n\nSigned-off-by: Tobias Wolf <dev-NTEO@vplace.de>\n---\n\n--- a/mm/page_alloc.c\n+++ b/mm/page_alloc.c\n@@ -7055,7 +7055,7 @@ static void __ref alloc_node_mem_map(str\n \tif (pgdat == NODE_DATA(0)) {\n \t\tmem_map = NODE_DATA(0)->node_mem_map;\n \t\tif (page_to_pfn(mem_map) != pgdat->node_start_pfn)\n-\t\t\tmem_map -= offset;\n+\t\t\tmem_map -= offset + (pgdat->node_start_pfn - ARCH_PFN_OFFSET);\n \t}\n #endif\n }\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/130-add-linux-spidev-compatible-si3210.patch",
    "content": "From: Giuseppe Lippolis <giu.lippolis@gmail.com>\nSubject: Add the linux,spidev compatible in spidev Several device in ramips have this binding in the dts\n\nSigned-off-by: Giuseppe Lippolis <giu.lippolis@gmail.com>\n---\n drivers/spi/spidev.c | 1 +\n 1 file changed, 1 insertion(+)\n\n--- a/drivers/spi/spidev.c\n+++ b/drivers/spi/spidev.c\n@@ -682,6 +682,7 @@ static const struct of_device_id spidev_\n \t{ .compatible = \"lwn,bk4\" },\n \t{ .compatible = \"dh,dhcom-board\" },\n \t{ .compatible = \"menlo,m53cpld\" },\n+\t{ .compatible = \"siliconlabs,si3210\" },\n \t{},\n };\n MODULE_DEVICE_TABLE(of, spidev_dt_ids);\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/140-jffs2-use-.rename2-and-add-RENAME_WHITEOUT-support.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nSubject: jffs2: use .rename2 and add RENAME_WHITEOUT support\n\nIt is required for renames on overlayfs\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n\n--- a/fs/jffs2/dir.c\n+++ b/fs/jffs2/dir.c\n@@ -609,7 +609,8 @@ static int jffs2_rmdir (struct inode *di\n \treturn ret;\n }\n \n-static int jffs2_mknod (struct inode *dir_i, struct dentry *dentry, umode_t mode, dev_t rdev)\n+static int __jffs2_mknod (struct inode *dir_i, struct dentry *dentry,\n+\t\t\t  umode_t mode, dev_t rdev, bool whiteout)\n {\n \tstruct jffs2_inode_info *f, *dir_f;\n \tstruct jffs2_sb_info *c;\n@@ -748,7 +749,11 @@ static int jffs2_mknod (struct inode *di\n \tmutex_unlock(&dir_f->sem);\n \tjffs2_complete_reservation(c);\n \n-\td_instantiate_new(dentry, inode);\n+\tif (!whiteout)\n+\t\td_instantiate_new(dentry, inode);\n+\telse\n+\t\tunlock_new_inode(inode);\n+\n \treturn 0;\n \n  fail:\n@@ -756,6 +761,17 @@ static int jffs2_mknod (struct inode *di\n \treturn ret;\n }\n \n+static int jffs2_mknod (struct inode *dir_i, struct dentry *dentry, umode_t mode, dev_t rdev)\n+{\n+\treturn __jffs2_mknod(dir_i, dentry, mode, rdev, false);\n+}\n+\n+static int jffs2_whiteout (struct inode *old_dir, struct dentry *old_dentry)\n+{\n+\treturn __jffs2_mknod(old_dir, old_dentry, S_IFCHR | WHITEOUT_MODE,\n+\t\t\t     WHITEOUT_DEV, true);\n+}\n+\n static int jffs2_rename (struct inode *old_dir_i, struct dentry *old_dentry,\n \t\t\t struct inode *new_dir_i, struct dentry *new_dentry,\n \t\t\t unsigned int flags)\n@@ -766,7 +782,7 @@ static int jffs2_rename (struct inode *o\n \tuint8_t type;\n \tuint32_t now;\n \n-\tif (flags & ~RENAME_NOREPLACE)\n+\tif (flags & ~(RENAME_NOREPLACE|RENAME_WHITEOUT))\n \t\treturn -EINVAL;\n \n \t/* The VFS will check for us and prevent trying to rename a\n@@ -832,9 +848,14 @@ static int jffs2_rename (struct inode *o\n \tif (d_is_dir(old_dentry) && !victim_f)\n \t\tinc_nlink(new_dir_i);\n \n-\t/* Unlink the original */\n-\tret = jffs2_do_unlink(c, JFFS2_INODE_INFO(old_dir_i),\n-\t\t\t      old_dentry->d_name.name, old_dentry->d_name.len, NULL, now);\n+\tif (flags & RENAME_WHITEOUT)\n+\t\t/* Replace with whiteout */\n+\t\tret = jffs2_whiteout(old_dir_i, old_dentry);\n+\telse\n+\t\t/* Unlink the original */\n+\t\tret = jffs2_do_unlink(c, JFFS2_INODE_INFO(old_dir_i),\n+\t\t\t\t      old_dentry->d_name.name,\n+\t\t\t\t      old_dentry->d_name.len, NULL, now);\n \n \t/* We don't touch inode->i_nlink */\n \n"
  },
  {
    "path": "target/linux/generic/pending-5.10/141-jffs2-add-RENAME_EXCHANGE-support.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nSubject: jffs2: add RENAME_EXCHANGE support\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n\n--- a/fs/jffs2/dir.c\n+++ b/fs/jffs2/dir.c\n@@ -779,18 +779,31 @@ static int jffs2_rename (struct inode *o\n \tint ret;\n \tstruct jffs2_sb_info *c = JFFS2_SB_INFO(old_dir_i->i_sb);\n \tstruct jffs2_inode_info *victim_f = NULL;\n+\tstruct inode *fst_inode = d_inode(old_dentry);\n+\tstruct inode *snd_inode = d_inode(new_dentry);\n \tuint8_t type;\n \tuint32_t now;\n \n-\tif (flags & ~(RENAME_NOREPLACE|RENAME_WHITEOUT))\n+\tif (flags & ~(RENAME_NOREPLACE|RENAME_WHITEOUT|RENAME_EXCHANGE))\n \t\treturn -EINVAL;\n \n+\tif ((flags & RENAME_EXCHANGE) && (old_dir_i != new_dir_i)) {\n+\t\tif (S_ISDIR(fst_inode->i_mode) && !S_ISDIR(snd_inode->i_mode)) {\n+\t\t\tinc_nlink(new_dir_i);\n+\t\t\tdrop_nlink(old_dir_i);\n+\t\t}\n+\t\telse if (!S_ISDIR(fst_inode->i_mode) && S_ISDIR(snd_inode->i_mode)) {\n+\t\t\tdrop_nlink(new_dir_i);\n+\t\t\tinc_nlink(old_dir_i);\n+\t\t}\n+\t}\n+\n \t/* The VFS will check for us and prevent trying to rename a\n \t * file over a directory and vice versa, but if it's a directory,\n \t * the VFS can't check whether the victim is empty. The filesystem\n \t * needs to do that for itself.\n \t */\n-\tif (d_really_is_positive(new_dentry)) {\n+\tif (d_really_is_positive(new_dentry) && !(flags & RENAME_EXCHANGE)) {\n \t\tvictim_f = JFFS2_INODE_INFO(d_inode(new_dentry));\n \t\tif (d_is_dir(new_dentry)) {\n \t\t\tstruct jffs2_full_dirent *fd;\n@@ -825,7 +838,7 @@ static int jffs2_rename (struct inode *o\n \tif (ret)\n \t\treturn ret;\n \n-\tif (victim_f) {\n+\tif (victim_f && !(flags & RENAME_EXCHANGE)) {\n \t\t/* There was a victim. Kill it off nicely */\n \t\tif (d_is_dir(new_dentry))\n \t\t\tclear_nlink(d_inode(new_dentry));\n@@ -851,6 +864,12 @@ static int jffs2_rename (struct inode *o\n \tif (flags & RENAME_WHITEOUT)\n \t\t/* Replace with whiteout */\n \t\tret = jffs2_whiteout(old_dir_i, old_dentry);\n+\telse if (flags & RENAME_EXCHANGE)\n+\t\t/* Replace the original */\n+\t\tret = jffs2_do_link(c, JFFS2_INODE_INFO(old_dir_i),\n+\t\t\t\t    d_inode(new_dentry)->i_ino, type,\n+\t\t\t\t    old_dentry->d_name.name, old_dentry->d_name.len,\n+\t\t\t\t    now);\n \telse\n \t\t/* Unlink the original */\n \t\tret = jffs2_do_unlink(c, JFFS2_INODE_INFO(old_dir_i),\n@@ -882,7 +901,7 @@ static int jffs2_rename (struct inode *o\n \t\treturn ret;\n \t}\n \n-\tif (d_is_dir(old_dentry))\n+\tif (d_is_dir(old_dentry) && !(flags & RENAME_EXCHANGE))\n \t\tdrop_nlink(old_dir_i);\n \n \tnew_dir_i->i_mtime = new_dir_i->i_ctime = old_dir_i->i_mtime = old_dir_i->i_ctime = ITIME(now);\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/142-jffs2-add-splice-ops.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nSubject: jffs2: add splice ops\n\nAdd splice_read using generic_file_splice_read.\nAdd splice_write using iter_file_splice_write\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n\n--- a/fs/jffs2/file.c\n+++ b/fs/jffs2/file.c\n@@ -53,6 +53,8 @@ const struct file_operations jffs2_file_\n \t.open =\t\tgeneric_file_open,\n  \t.read_iter =\tgeneric_file_read_iter,\n  \t.write_iter =\tgeneric_file_write_iter,\n+\t.splice_read =\tgeneric_file_splice_read,\n+\t.splice_write =\titer_file_splice_write,\n \t.unlocked_ioctl=jffs2_ioctl,\n \t.mmap =\t\tgeneric_file_readonly_mmap,\n \t.fsync =\tjffs2_fsync,\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/150-bridge_allow_receiption_on_disabled_port.patch",
    "content": "From: Stephen Hemminger <stephen@networkplumber.org>\nSubject: bridge: allow receiption on disabled port\n\nWhen an ethernet device is enslaved to a bridge, and the bridge STP\ndetects loss of carrier (or operational state down), then normally\npacket receiption is blocked.\n\nThis breaks control applications like WPA which maybe expecting to\nreceive packets to negotiate to bring link up. The bridge needs to\nblock forwarding packets from these disabled ports, but there is no\nhard requirement to not allow local packet delivery.\n\nSigned-off-by: Stephen Hemminger <stephen@networkplumber.org>\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n\n--- a/net/bridge/br_input.c\n+++ b/net/bridge/br_input.c\n@@ -195,6 +195,9 @@ static void __br_handle_local_finish(str\n /* note: already called with rcu_read_lock */\n static int br_handle_local_finish(struct net *net, struct sock *sk, struct sk_buff *skb)\n {\n+\tstruct net_bridge_port *p = br_port_get_rcu(skb->dev);\n+\n+\tif (p->state != BR_STATE_DISABLED)\n \t__br_handle_local_finish(skb);\n \n \t/* return 1 to signal the okfn() was called so it's ok to use the skb */\n@@ -348,6 +351,17 @@ static rx_handler_result_t br_handle_fra\n \n forward:\n \tswitch (p->state) {\n+\tcase BR_STATE_DISABLED:\n+\t\tif (ether_addr_equal(p->br->dev->dev_addr, dest))\n+\t\t\tskb->pkt_type = PACKET_HOST;\n+\n+\t\tif (NF_HOOK(NFPROTO_BRIDGE, NF_BR_PRE_ROUTING,\n+\t\t\tdev_net(skb->dev), NULL, skb, skb->dev, NULL,\n+\t\t\tbr_handle_local_finish) == 1) {\n+\t\t\treturn RX_HANDLER_PASS;\n+\t\t}\n+\t\tbreak;\n+\n \tcase BR_STATE_FORWARDING:\n \tcase BR_STATE_LEARNING:\n \t\tif (ether_addr_equal(p->br->dev->dev_addr, dest))\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/190-rtc-rs5c372-support_alarms_up_to_1_week.patch",
    "content": "From: Daniel González Cabanelas <dgcbueu@gmail.com>\nSubject: [PATCH 1/2] rtc: rs5c372: support alarms up to 1 week\n\nThe Ricoh R2221x, R2223x, RS5C372, RV5C387A chips can handle 1 week\nalarms.\n\nRead the \"wday\" alarm register and convert it to a date to support up 1\nweek in our driver.\n\nSigned-off-by: Daniel González Cabanelas <dgcbueu@gmail.com>\n---\n drivers/rtc/rtc-rs5c372.c | 48 ++++++++++++++++++++++++++++++++++-----\n 1 file changed, 42 insertions(+), 6 deletions(-)\n\n--- a/drivers/rtc/rtc-rs5c372.c\n+++ b/drivers/rtc/rtc-rs5c372.c\n@@ -393,7 +393,9 @@ static int rs5c_read_alarm(struct device\n {\n \tstruct i2c_client\t*client = to_i2c_client(dev);\n \tstruct rs5c372\t\t*rs5c = i2c_get_clientdata(client);\n-\tint\t\t\tstatus;\n+\tint\t\t\tstatus, wday_offs;\n+\tstruct rtc_time \trtc;\n+\tunsigned long \t\talarm_secs;\n \n \tstatus = rs5c_get_regs(rs5c);\n \tif (status < 0)\n@@ -403,6 +405,30 @@ static int rs5c_read_alarm(struct device\n \tt->time.tm_sec = 0;\n \tt->time.tm_min = bcd2bin(rs5c->regs[RS5C_REG_ALARM_A_MIN] & 0x7f);\n \tt->time.tm_hour = rs5c_reg2hr(rs5c, rs5c->regs[RS5C_REG_ALARM_A_HOURS]);\n+\tt->time.tm_wday = ffs(rs5c->regs[RS5C_REG_ALARM_A_WDAY] & 0x7f) - 1;\n+\n+\t/* determine the day, month and year based on alarm wday, taking as a\n+\t * reference the current time from the rtc\n+\t */\n+\tstatus = rs5c372_rtc_read_time(dev, &rtc);\n+\tif (status < 0)\n+\t\treturn status;\n+\n+\twday_offs = t->time.tm_wday - rtc.tm_wday;\n+\talarm_secs = mktime64(rtc.tm_year + 1900,\n+\t\t\t      rtc.tm_mon + 1,\n+\t\t\t      rtc.tm_mday + wday_offs,\n+\t\t\t      t->time.tm_hour,\n+\t\t\t      t->time.tm_min,\n+\t\t\t      t->time.tm_sec);\n+\n+\tif (wday_offs < 0 || (wday_offs == 0 &&\n+\t\t\t      (t->time.tm_hour < rtc.tm_hour ||\n+\t\t\t       (t->time.tm_hour == rtc.tm_hour &&\n+\t\t\t\tt->time.tm_min <= rtc.tm_min))))\n+\t\talarm_secs += 7 * 86400;\n+\n+\trtc_time64_to_tm(alarm_secs, &t->time);\n \n \t/* ... and status */\n \tt->enabled = !!(rs5c->regs[RS5C_REG_CTRL1] & RS5C_CTRL1_AALE);\n@@ -417,12 +443,20 @@ static int rs5c_set_alarm(struct device\n \tstruct rs5c372\t\t*rs5c = i2c_get_clientdata(client);\n \tint\t\t\tstatus, addr, i;\n \tunsigned char\t\tbuf[3];\n+\tstruct rtc_time \trtc_tm;\n+\tunsigned long \t\trtc_secs, alarm_secs;\n \n-\t/* only handle up to 24 hours in the future, like RTC_ALM_SET */\n-\tif (t->time.tm_mday != -1\n-\t\t\t|| t->time.tm_mon != -1\n-\t\t\t|| t->time.tm_year != -1)\n+\t/* chip only can handle alarms up to one week in the future*/\n+\tstatus = rs5c372_rtc_read_time(dev, &rtc_tm);\n+\tif (status)\n+\t\treturn status;\n+\trtc_secs = rtc_tm_to_time64(&rtc_tm);\n+\talarm_secs = rtc_tm_to_time64(&t->time);\n+\tif (alarm_secs >= rtc_secs + 7 * 86400) {\n+\t\tdev_err(dev, \"%s: alarm maximum is one week in the future (%d)\\n\",\n+\t\t\t__func__, status);\n \t\treturn -EINVAL;\n+\t}\n \n \t/* REVISIT: round up tm_sec */\n \n@@ -443,7 +477,9 @@ static int rs5c_set_alarm(struct device\n \t/* set alarm */\n \tbuf[0] = bin2bcd(t->time.tm_min);\n \tbuf[1] = rs5c_hr2reg(rs5c, t->time.tm_hour);\n-\tbuf[2] = 0x7f;\t/* any/all days */\n+\t/* each bit is the day of the week, 0x7f means all days */\n+\tbuf[2] = (t->time.tm_wday >= 0 && t->time.tm_wday < 7) ?\n+\t\t  BIT(t->time.tm_wday) : 0x7f;\n \n \tfor (i = 0; i < sizeof(buf); i++) {\n \t\taddr = RS5C_ADDR(RS5C_REG_ALARM_A_MIN + i);\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/191-rtc-rs5c372-let_the_alarm_to_be_used_as_wakeup_source.patch",
    "content": "From: Daniel González Cabanelas <dgcbueu@gmail.com>\nSubject: [PATCH 2/2] rtc: rs5c372: let the alarm to be used as wakeup source\n\nCurrently there is no use for the interrupts on the rs5c372 RTC and the\nwakealarm isn't enabled. There are some devices like NASes which use this\nRTC to wake up from the power off state when the INTR pin is activated by\nthe alarm clock.\n\nEnable the alarm and let to be used as a wakeup source.\n\nTested on a Buffalo LS421DE NAS.\n\nSigned-off-by: Daniel González Cabanelas <dgcbueu@gmail.com>\n---\n drivers/rtc/rtc-rs5c372.c | 16 ++++++++++++++++\n 1 file changed, 16 insertions(+)\n\n--- a/drivers/rtc/rtc-rs5c372.c\n+++ b/drivers/rtc/rtc-rs5c372.c\n@@ -654,6 +654,7 @@ static int rs5c372_probe(struct i2c_clie\n \tint err = 0;\n \tint smbus_mode = 0;\n \tstruct rs5c372 *rs5c372;\n+\tbool rs5c372_can_wakeup_device = false;\n \n \tdev_dbg(&client->dev, \"%s\\n\", __func__);\n \n@@ -689,6 +690,12 @@ static int rs5c372_probe(struct i2c_clie\n \telse\n \t\trs5c372->type = id->driver_data;\n \n+#ifdef CONFIG_OF\n+\tif(of_property_read_bool(client->dev.of_node,\n+\t\t\t\t\t      \"wakeup-source\"))\n+\t\trs5c372_can_wakeup_device = true;\n+#endif\n+\n \t/* we read registers 0x0f then 0x00-0x0f; skip the first one */\n \trs5c372->regs = &rs5c372->buf[1];\n \trs5c372->smbus = smbus_mode;\n@@ -722,6 +729,8 @@ static int rs5c372_probe(struct i2c_clie\n \t\tgoto exit;\n \t}\n \n+\trs5c372->has_irq = 1;\n+\n \t/* if the oscillator lost power and no other software (like\n \t * the bootloader) set it up, do it here.\n \t *\n@@ -748,6 +757,10 @@ static int rs5c372_probe(struct i2c_clie\n \t\t\t);\n \n \t/* REVISIT use client->irq to register alarm irq ... */\n+\tif (rs5c372_can_wakeup_device) {\n+\t\tdevice_init_wakeup(&client->dev, true);\n+\t}\n+\n \trs5c372->rtc = devm_rtc_device_register(&client->dev,\n \t\t\t\t\trs5c372_driver.driver.name,\n \t\t\t\t\t&rs5c372_rtc_ops, THIS_MODULE);\n@@ -761,6 +774,9 @@ static int rs5c372_probe(struct i2c_clie\n \tif (err)\n \t\tgoto exit;\n \n+\t/* the rs5c372 alarm only supports a minute accuracy */\n+\trs5c372->rtc->uie_unsupported = 1;\n+\n \treturn 0;\n \n exit:\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/201-extra_optimization.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nSubject: Upgrade to Linux 2.6.19\n\n- Includes large parts of the patch from #1021 by dpalffy\n- Includes RB532 NAND driver changes by n0-1\n\n[john@phrozen.org: feix will add this to his upstream queue]\n\nlede-commit: bff468813f78f81e36ebb2a3f4354de7365e640f\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n Makefile | 6 +++---\n 1 file changed, 3 insertions(+), 3 deletions(-)\n\n--- a/Makefile\n+++ b/Makefile\n@@ -735,11 +735,11 @@ KBUILD_CFLAGS\t+= $(call cc-disable-warni\n KBUILD_CFLAGS\t+= $(call cc-disable-warning, address-of-packed-member)\n \n ifdef CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE\n-KBUILD_CFLAGS += -O2\n+KBUILD_CFLAGS += -O2 $(EXTRA_OPTIMIZATION)\n else ifdef CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE_O3\n-KBUILD_CFLAGS += -O3\n+KBUILD_CFLAGS += -O3 $(EXTRA_OPTIMIZATION)\n else ifdef CONFIG_CC_OPTIMIZE_FOR_SIZE\n-KBUILD_CFLAGS += -Os\n+KBUILD_CFLAGS += -Os -fno-reorder-blocks -fno-tree-ch $(EXTRA_OPTIMIZATION)\n endif\n \n # Tell gcc to never replace conditional load with a non-conditional one\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/203-kallsyms_uncompressed.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nSubject: kernel: add a config option for keeping the kallsyms table uncompressed, saving ~9kb kernel size after lzma on ar71xx\n\n[john@phrozen.org: added to my upstream queue 30.12.2016]\nlede-commit: e0e3509b5ce2ccf93d4d67ea907613f5f7ec2eed\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n init/Kconfig            | 11 +++++++++++\n kernel/kallsyms.c       |  8 ++++++++\n scripts/kallsyms.c      | 12 ++++++++++++\n scripts/link-vmlinux.sh |  4 ++++\n 4 files changed, 35 insertions(+)\n\n--- a/init/Kconfig\n+++ b/init/Kconfig\n@@ -1384,6 +1384,17 @@ config SYSCTL_ARCH_UNALIGN_ALLOW\n \t  the unaligned access emulation.\n \t  see arch/parisc/kernel/unaligned.c for reference\n \n+config KALLSYMS_UNCOMPRESSED\n+\tbool \"Keep kallsyms uncompressed\"\n+\tdepends on KALLSYMS\n+\thelp\n+\t\tNormally kallsyms contains compressed symbols (using a token table),\n+\t\treducing the uncompressed kernel image size. Keeping the symbol table\n+\t\tuncompressed significantly improves the size of this part in compressed\n+\t\tkernel images.\n+\n+\t\tSay N unless you need compressed kernel images to be small.\n+\n config HAVE_PCSPKR_PLATFORM\n \tbool\n \n--- a/kernel/kallsyms.c\n+++ b/kernel/kallsyms.c\n@@ -77,6 +77,11 @@ static unsigned int kallsyms_expand_symb\n \t * For every byte on the compressed symbol data, copy the table\n \t * entry for that byte.\n \t */\n+#ifdef CONFIG_KALLSYMS_UNCOMPRESSED\n+\tmemcpy(result, data + 1, len - 1);\n+\tresult += len - 1;\n+\tlen = 0;\n+#endif\n \twhile (len) {\n \t\ttptr = &kallsyms_token_table[kallsyms_token_index[*data]];\n \t\tdata++;\n@@ -109,6 +114,9 @@ tail:\n  */\n static char kallsyms_get_symbol_type(unsigned int off)\n {\n+#ifdef CONFIG_KALLSYMS_UNCOMPRESSED\n+\treturn kallsyms_names[off + 1];\n+#endif\n \t/*\n \t * Get just the first code, look it up in the token table,\n \t * and return the first char from this token.\n--- a/scripts/kallsyms.c\n+++ b/scripts/kallsyms.c\n@@ -58,6 +58,7 @@ static struct addr_range percpu_range =\n static struct sym_entry **table;\n static unsigned int table_size, table_cnt;\n static int all_symbols;\n+static int uncompressed;\n static int absolute_percpu;\n static int base_relative;\n \n@@ -486,6 +487,9 @@ static void write_src(void)\n \n \tfree(markers);\n \n+\tif (uncompressed)\n+\t\treturn;\n+\n \toutput_label(\"kallsyms_token_table\");\n \toff = 0;\n \tfor (i = 0; i < 256; i++) {\n@@ -537,6 +541,9 @@ static unsigned char *find_token(unsigne\n {\n \tint i;\n \n+\tif (uncompressed)\n+\t\treturn NULL;\n+\n \tfor (i = 0; i < len - 1; i++) {\n \t\tif (str[i] == token[0] && str[i+1] == token[1])\n \t\t\treturn &str[i];\n@@ -609,6 +616,9 @@ static void optimize_result(void)\n {\n \tint i, best;\n \n+\tif (uncompressed)\n+\t\treturn;\n+\n \t/* using the '\\0' symbol last allows compress_symbols to use standard\n \t * fast string functions */\n \tfor (i = 255; i >= 0; i--) {\n@@ -773,6 +783,8 @@ int main(int argc, char **argv)\n \t\t\t\tabsolute_percpu = 1;\n \t\t\telse if (strcmp(argv[i], \"--base-relative\") == 0)\n \t\t\t\tbase_relative = 1;\n+\t\t\telse if (strcmp(argv[i], \"--uncompressed\") == 0)\n+\t\t\t\tuncompressed = 1;\n \t\t\telse\n \t\t\t\tusage();\n \t\t}\n--- a/scripts/link-vmlinux.sh\n+++ b/scripts/link-vmlinux.sh\n@@ -186,6 +186,10 @@ kallsyms()\n \t\tkallsymopt=\"${kallsymopt} --base-relative\"\n \tfi\n \n+\tif [ -n \"${CONFIG_KALLSYMS_UNCOMPRESSED}\" ]; then\n+\t\tkallsymopt=\"${kallsymopt} --uncompressed\"\n+\tfi\n+\n \tinfo KSYMS ${2}\n \t${NM} -n ${1} | scripts/kallsyms ${kallsymopt} > ${2}\n }\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/205-backtrace_module_info.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nSubject: kernel: when KALLSYMS is disabled, print module address + size for matching backtrace entries\n\n[john@phrozen.org: felix will add this to his upstream queue]\n\nlede-commit 53827cdc824556cda910b23ce5030c363b8f1461\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n lib/vsprintf.c | 15 +++++++++++----\n 1 file changed, 11 insertions(+), 4 deletions(-)\n\n--- a/lib/vsprintf.c\n+++ b/lib/vsprintf.c\n@@ -983,8 +983,10 @@ char *symbol_string(char *buf, char *end\n \t\t    struct printf_spec spec, const char *fmt)\n {\n \tunsigned long value;\n-#ifdef CONFIG_KALLSYMS\n \tchar sym[KSYM_SYMBOL_LEN];\n+#ifndef CONFIG_KALLSYMS\n+\tstruct module *mod;\n+\tint len;\n #endif\n \n \tif (fmt[1] == 'R')\n@@ -1001,8 +1003,14 @@ char *symbol_string(char *buf, char *end\n \n \treturn string_nocheck(buf, end, sym, spec);\n #else\n-\treturn special_hex_number(buf, end, value, sizeof(void *));\n+\tlen = snprintf(sym, sizeof(sym), \"0x%lx\", value);\n+\tmod = __module_address(value);\n+\tif (mod)\n+\t\tsnprintf(sym + len, sizeof(sym) - len, \" [%s@%p+0x%x]\",\n+\t\t\t mod->name, mod->core_layout.base,\n+\t\t\t mod->core_layout.size);\n #endif\n+\treturn string(buf, end, sym, spec);\n }\n \n static const struct printf_spec default_str_spec = {\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/240-remove-unsane-filenames-from-deps_initramfs-list.patch",
    "content": "From: Gabor Juhos <juhosg@openwrt.org>\nSubject: usr: sanitize deps_initramfs list\n\nIf any filename in the intramfs dependency\nlist contains a colon, that causes a kernel\nbuild error like this:\n\n/devel/openwrt/build_dir/linux-ar71xx_generic/linux-3.6.6/usr/Makefile:58: *** multiple target patterns.  Stop.\nmake[5]: *** [usr] Error 2\n\nFix it by removing such filenames from the\ndeps_initramfs list.\n\nSigned-off-by: Gabor Juhos <juhosg@openwrt.org>\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n usr/Makefile | 8 +++++---\n 1 file changed, 5 insertions(+), 3 deletions(-)\n\n--- a/usr/Makefile\n+++ b/usr/Makefile\n@@ -61,6 +61,8 @@ hostprogs := gen_init_cpio\n # The dependency list is generated by gen_initramfs.sh -l\n -include $(obj)/.initramfs_data.cpio.d\n \n+deps_initramfs := $(foreach v,$(deps_initramfs),$(if $(findstring :,$(v)),,$(v)))\n+\n # do not try to update files included in initramfs\n $(deps_initramfs): ;\n \n"
  },
  {
    "path": "target/linux/generic/pending-5.10/261-enable_wilink_platform_without_drivers.patch",
    "content": "From: Imre Kaloz <kaloz@openwrt.org>\nSubject: [PATCH] hack: net: wireless: make the wl12xx glue code available with\n compat-wireless, too\n\nSigned-off-by: Imre Kaloz <kaloz@openwrt.org>\n---\n drivers/net/wireless/ti/Kconfig | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/drivers/net/wireless/ti/Kconfig\n+++ b/drivers/net/wireless/ti/Kconfig\n@@ -20,7 +20,7 @@ source \"drivers/net/wireless/ti/wlcore/K\n \n config WILINK_PLATFORM_DATA\n \tbool \"TI WiLink platform data\"\n-\tdepends on WLCORE_SDIO || WL1251_SDIO\n+\tdepends on WLCORE_SDIO || WL1251_SDIO || ARCH_OMAP2PLUS\n \tdefault y\n \thelp\n \tSmall platform data bit needed to pass data to the sdio modules.\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/270-platform-mikrotik-build-bits.patch",
    "content": "From c2deb5ef01a0ef09088832744cbace9e239a6ee0 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Thibaut=20VAR=C3=88NE?= <hacks@slashdirt.org>\nDate: Sat, 28 Mar 2020 12:11:50 +0100\nSubject: [PATCH] generic: platform/mikrotik build bits (5.4)\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nThis patch adds platform/mikrotik kernel build bits\n\nSigned-off-by: Thibaut VARÈNE <hacks@slashdirt.org>\n---\n drivers/platform/Kconfig  | 2 ++\n drivers/platform/Makefile | 1 +\n 2 files changed, 3 insertions(+)\n\n--- a/drivers/platform/Kconfig\n+++ b/drivers/platform/Kconfig\n@@ -13,3 +13,5 @@ source \"drivers/platform/chrome/Kconfig\"\n source \"drivers/platform/mellanox/Kconfig\"\n \n source \"drivers/platform/olpc/Kconfig\"\n+\n+source \"drivers/platform/mikrotik/Kconfig\"\n--- a/drivers/platform/Makefile\n+++ b/drivers/platform/Makefile\n@@ -9,3 +9,4 @@ obj-$(CONFIG_MIPS)\t\t+= mips/\n obj-$(CONFIG_OLPC_EC)\t\t+= olpc/\n obj-$(CONFIG_GOLDFISH)\t\t+= goldfish/\n obj-$(CONFIG_CHROME_PLATFORMS)\t+= chrome/\n+obj-$(CONFIG_MIKROTIK)\t\t+= mikrotik/\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/300-mips_expose_boot_raw.patch",
    "content": "From: Mark Miller <mark@mirell.org>\nSubject: mips: expose CONFIG_BOOT_RAW\n\nThis exposes the CONFIG_BOOT_RAW symbol in Kconfig. This is needed on\ncertain Broadcom chipsets running CFE in order to load the kernel.\n\nSigned-off-by: Mark Miller <mark@mirell.org>\nAcked-by: Rob Landley <rob@landley.net>\n---\n--- a/arch/mips/Kconfig\n+++ b/arch/mips/Kconfig\n@@ -1085,9 +1085,6 @@ config FW_ARC\n config ARCH_MAY_HAVE_PC_FDC\n \tbool\n \n-config BOOT_RAW\n-\tbool\n-\n config CEVT_BCM1480\n \tbool\n \n@@ -3182,6 +3179,18 @@ choice\n \t\tbool \"Extend builtin kernel arguments with bootloader arguments\"\n endchoice\n \n+config BOOT_RAW\n+\tbool \"Enable the kernel to be executed from the load address\"\n+\tdefault n\n+\thelp\n+\t Allow the kernel to be executed from the load address for\n+\t bootloaders which cannot read the ELF format. This places\n+\t a jump to start_kernel at the load address.\n+\n+\t If unsure, say N.\n+\n+\n+\n endmenu\n \n config LOCKDEP_SUPPORT\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/302-mips_no_branch_likely.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nSubject: mips: use -mno-branch-likely for kernel and userspace\n\nsaves ~11k kernel size after lzma and ~12k squashfs size in the\n\nlede-commit: 41a039f46450ffae9483d6216422098669da2900\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n arch/mips/Makefile | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/arch/mips/Makefile\n+++ b/arch/mips/Makefile\n@@ -95,7 +95,7 @@ all-$(CONFIG_SYS_SUPPORTS_ZBOOT)+= vmlin\n # machines may also.  Since BFD is incredibly buggy with respect to\n # crossformat linking we rely on the elf2ecoff tool for format conversion.\n #\n-cflags-y\t\t\t+= -G 0 -mno-abicalls -fno-pic -pipe\n+cflags-y\t\t\t+= -G 0 -mno-abicalls -fno-pic -pipe -mno-branch-likely\n cflags-y\t\t\t+= -msoft-float\n LDFLAGS_vmlinux\t\t\t+= -G 0 -static -n -nostdlib\n KBUILD_AFLAGS_MODULE\t\t+= -mlong-calls\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/305-mips_module_reloc.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nSubject: mips: replace -mlong-calls with -mno-long-calls to make function calls faster in kernel modules to achieve this, try to\n\nlede-commit: 3b3d64743ba2a874df9d70cd19e242205b0a788c\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n arch/mips/Makefile             |   5 +\n arch/mips/include/asm/module.h |   5 +\n arch/mips/kernel/module.c      | 279 ++++++++++++++++++++++++++++++++++++++++-\n 3 files changed, 284 insertions(+), 5 deletions(-)\n\n--- a/arch/mips/Makefile\n+++ b/arch/mips/Makefile\n@@ -98,8 +98,18 @@ all-$(CONFIG_SYS_SUPPORTS_ZBOOT)+= vmlin\n cflags-y\t\t\t+= -G 0 -mno-abicalls -fno-pic -pipe -mno-branch-likely\n cflags-y\t\t\t+= -msoft-float\n LDFLAGS_vmlinux\t\t\t+= -G 0 -static -n -nostdlib\n+ifdef CONFIG_64BIT\n KBUILD_AFLAGS_MODULE\t\t+= -mlong-calls\n KBUILD_CFLAGS_MODULE\t\t+= -mlong-calls\n+else\n+  ifdef CONFIG_DYNAMIC_FTRACE\n+    KBUILD_AFLAGS_MODULE\t+= -mlong-calls\n+    KBUILD_CFLAGS_MODULE\t+= -mlong-calls\n+  else\n+    KBUILD_AFLAGS_MODULE\t+= -mno-long-calls\n+    KBUILD_CFLAGS_MODULE\t+= -mno-long-calls\n+  endif\n+endif\n \n ifeq ($(CONFIG_RELOCATABLE),y)\n LDFLAGS_vmlinux\t\t\t+= --emit-relocs\n--- a/arch/mips/include/asm/module.h\n+++ b/arch/mips/include/asm/module.h\n@@ -12,6 +12,11 @@ struct mod_arch_specific {\n \tconst struct exception_table_entry *dbe_start;\n \tconst struct exception_table_entry *dbe_end;\n \tstruct mips_hi16 *r_mips_hi16_list;\n+\n+\tvoid *phys_plt_tbl;\n+\tvoid *virt_plt_tbl;\n+\tunsigned int phys_plt_offset;\n+\tunsigned int virt_plt_offset;\n };\n \n typedef uint8_t Elf64_Byte;\t\t/* Type for a 8-bit quantity.  */\n--- a/arch/mips/kernel/module.c\n+++ b/arch/mips/kernel/module.c\n@@ -31,14 +31,221 @@ struct mips_hi16 {\n static LIST_HEAD(dbe_list);\n static DEFINE_SPINLOCK(dbe_lock);\n \n-#ifdef MODULE_START\n+/*\n+ * Get the potential max trampolines size required of the init and\n+ * non-init sections. Only used if we cannot find enough contiguous\n+ * physically mapped memory to put the module into.\n+ */\n+static unsigned int\n+get_plt_size(const Elf_Ehdr *hdr, const Elf_Shdr *sechdrs,\n+             const char *secstrings, unsigned int symindex, bool is_init)\n+{\n+\tunsigned long ret = 0;\n+\tunsigned int i, j;\n+\tElf_Sym *syms;\n+\n+\t/* Everything marked ALLOC (this includes the exported symbols) */\n+\tfor (i = 1; i < hdr->e_shnum; ++i) {\n+\t\tunsigned int info = sechdrs[i].sh_info;\n+\n+\t\tif (sechdrs[i].sh_type != SHT_REL\n+\t\t    && sechdrs[i].sh_type != SHT_RELA)\n+\t\t\tcontinue;\n+\n+\t\t/* Not a valid relocation section? */\n+\t\tif (info >= hdr->e_shnum)\n+\t\t\tcontinue;\n+\n+\t\t/* Don't bother with non-allocated sections */\n+\t\tif (!(sechdrs[info].sh_flags & SHF_ALLOC))\n+\t\t\tcontinue;\n+\n+\t\t/* If it's called *.init*, and we're not init, we're\n+                   not interested */\n+\t\tif ((strstr(secstrings + sechdrs[i].sh_name, \".init\") != 0)\n+\t\t    != is_init)\n+\t\t\tcontinue;\n+\n+\t\tsyms = (Elf_Sym *) sechdrs[symindex].sh_addr;\n+\t\tif (sechdrs[i].sh_type == SHT_REL) {\n+\t\t\tElf_Mips_Rel *rel = (void *) sechdrs[i].sh_addr;\n+\t\t\tunsigned int size = sechdrs[i].sh_size / sizeof(*rel);\n+\n+\t\t\tfor (j = 0; j < size; ++j) {\n+\t\t\t\tElf_Sym *sym;\n+\n+\t\t\t\tif (ELF_MIPS_R_TYPE(rel[j]) != R_MIPS_26)\n+\t\t\t\t\tcontinue;\n+\n+\t\t\t\tsym = syms + ELF_MIPS_R_SYM(rel[j]);\n+\t\t\t\tif (!is_init && sym->st_shndx != SHN_UNDEF)\n+\t\t\t\t\tcontinue;\n+\n+\t\t\t\tret += 4 * sizeof(int);\n+\t\t\t}\n+\t\t} else {\n+\t\t\tElf_Mips_Rela *rela = (void *) sechdrs[i].sh_addr;\n+\t\t\tunsigned int size = sechdrs[i].sh_size / sizeof(*rela);\n+\n+\t\t\tfor (j = 0; j < size; ++j) {\n+\t\t\t\tElf_Sym *sym;\n+\n+\t\t\t\tif (ELF_MIPS_R_TYPE(rela[j]) != R_MIPS_26)\n+\t\t\t\t\tcontinue;\n+\n+\t\t\t\tsym = syms + ELF_MIPS_R_SYM(rela[j]);\n+\t\t\t\tif (!is_init && sym->st_shndx != SHN_UNDEF)\n+\t\t\t\t\tcontinue;\n+\n+\t\t\t\tret += 4 * sizeof(int);\n+\t\t\t}\n+\t\t}\n+\t}\n+\n+\treturn ret;\n+}\n+\n+#ifndef MODULE_START\n+static void *alloc_phys(unsigned long size)\n+{\n+\tunsigned order;\n+\tstruct page *page;\n+\tstruct page *p;\n+\n+\tsize = PAGE_ALIGN(size);\n+\torder = get_order(size);\n+\n+\tpage = alloc_pages(GFP_KERNEL | __GFP_NORETRY | __GFP_NOWARN |\n+\t\t\t__GFP_THISNODE, order);\n+\tif (!page)\n+\t\treturn NULL;\n+\n+\tsplit_page(page, order);\n+\n+\t/* mark all pages except for the last one */\n+\tfor (p = page; p + 1 < page + (size >> PAGE_SHIFT); ++p)\n+\t\tset_bit(PG_owner_priv_1, &p->flags);\n+\n+\tfor (p = page + (size >> PAGE_SHIFT); p < page + (1 << order); ++p)\n+\t\t__free_page(p);\n+\n+\treturn page_address(page);\n+}\n+#endif\n+\n+static void free_phys(void *ptr)\n+{\n+\tstruct page *page;\n+\tbool free;\n+\n+\tpage = virt_to_page(ptr);\n+\tdo {\n+\t\tfree = test_and_clear_bit(PG_owner_priv_1, &page->flags);\n+\t\t__free_page(page);\n+\t\tpage++;\n+\t} while (free);\n+}\n+\n+\n void *module_alloc(unsigned long size)\n {\n+#ifdef MODULE_START\n \treturn __vmalloc_node_range(size, 1, MODULE_START, MODULE_END,\n \t\t\t\tGFP_KERNEL, PAGE_KERNEL, 0, NUMA_NO_NODE,\n \t\t\t\t__builtin_return_address(0));\n+#else\n+\tvoid *ptr;\n+\n+\tif (size == 0)\n+\t\treturn NULL;\n+\n+\tptr = alloc_phys(size);\n+\n+\t/* If we failed to allocate physically contiguous memory,\n+\t * fall back to regular vmalloc. The module loader code will\n+\t * create jump tables to handle long jumps */\n+\tif (!ptr)\n+\t\treturn vmalloc(size);\n+\n+\treturn ptr;\n+#endif\n }\n+\n+static inline bool is_phys_addr(void *ptr)\n+{\n+#ifdef CONFIG_64BIT\n+\treturn (KSEGX((unsigned long)ptr) == CKSEG0);\n+#else\n+\treturn (KSEGX(ptr) == KSEG0);\n #endif\n+}\n+\n+/* Free memory returned from module_alloc */\n+void module_memfree(void *module_region)\n+{\n+\tif (is_phys_addr(module_region))\n+\t\tfree_phys(module_region);\n+\telse\n+\t\tvfree(module_region);\n+}\n+\n+static void *__module_alloc(int size, bool phys)\n+{\n+\tvoid *ptr;\n+\n+\tif (phys)\n+\t\tptr = kmalloc(size, GFP_KERNEL);\n+\telse\n+\t\tptr = vmalloc(size);\n+\treturn ptr;\n+}\n+\n+static void __module_free(void *ptr)\n+{\n+\tif (is_phys_addr(ptr))\n+\t\tkfree(ptr);\n+\telse\n+\t\tvfree(ptr);\n+}\n+\n+int module_frob_arch_sections(Elf_Ehdr *hdr, Elf_Shdr *sechdrs,\n+\t\t\t      char *secstrings, struct module *mod)\n+{\n+\tunsigned int symindex = 0;\n+\tunsigned int core_size, init_size;\n+\tint i;\n+\n+\tmod->arch.phys_plt_offset = 0;\n+\tmod->arch.virt_plt_offset = 0;\n+\tmod->arch.phys_plt_tbl = NULL;\n+\tmod->arch.virt_plt_tbl = NULL;\n+\n+\tif (IS_ENABLED(CONFIG_64BIT))\n+\t\treturn 0;\n+\n+\tfor (i = 1; i < hdr->e_shnum; i++)\n+\t\tif (sechdrs[i].sh_type == SHT_SYMTAB)\n+\t\t\tsymindex = i;\n+\n+\tcore_size = get_plt_size(hdr, sechdrs, secstrings, symindex, false);\n+\tinit_size = get_plt_size(hdr, sechdrs, secstrings, symindex, true);\n+\n+\tif ((core_size + init_size) == 0)\n+\t\treturn 0;\n+\n+\tmod->arch.phys_plt_tbl = __module_alloc(core_size + init_size, 1);\n+\tif (!mod->arch.phys_plt_tbl)\n+\t\treturn -ENOMEM;\n+\n+\tmod->arch.virt_plt_tbl = __module_alloc(core_size + init_size, 0);\n+\tif (!mod->arch.virt_plt_tbl) {\n+\t\t__module_free(mod->arch.phys_plt_tbl);\n+\t\tmod->arch.phys_plt_tbl = NULL;\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\treturn 0;\n+}\n \n static int apply_r_mips_none(struct module *me, u32 *location,\n \t\t\t     u32 base, Elf_Addr v, bool rela)\n@@ -54,9 +261,40 @@ static int apply_r_mips_32(struct module\n \treturn 0;\n }\n \n+static Elf_Addr add_plt_entry_to(unsigned *plt_offset,\n+\t\t\t\t void *start, Elf_Addr v)\n+{\n+\tunsigned *tramp = start + *plt_offset;\n+\t*plt_offset += 4 * sizeof(int);\n+\n+\t/* adjust carry for addiu */\n+\tif (v & 0x00008000)\n+\t\tv += 0x10000;\n+\n+\ttramp[0] = 0x3c190000 | (v >> 16);      /* lui t9, hi16 */\n+\ttramp[1] = 0x27390000 | (v & 0xffff);   /* addiu t9, t9, lo16 */\n+\ttramp[2] = 0x03200008;                  /* jr t9 */\n+\ttramp[3] = 0x00000000;                  /* nop */\n+\n+\treturn (Elf_Addr) tramp;\n+}\n+\n+static Elf_Addr add_plt_entry(struct module *me, void *location, Elf_Addr v)\n+{\n+\tif (is_phys_addr(location))\n+\t\treturn add_plt_entry_to(&me->arch.phys_plt_offset,\n+\t\t\t\tme->arch.phys_plt_tbl, v);\n+\telse\n+\t\treturn add_plt_entry_to(&me->arch.virt_plt_offset,\n+\t\t\t\tme->arch.virt_plt_tbl, v);\n+\n+}\n+\n static int apply_r_mips_26(struct module *me, u32 *location,\n \t\t\t   u32 base, Elf_Addr v, bool rela)\n {\n+\tu32 ofs = base & 0x03ffffff;\n+\n \tif (v % 4) {\n \t\tpr_err(\"module %s: dangerous R_MIPS_26 relocation\\n\",\n \t\t       me->name);\n@@ -64,13 +302,17 @@ static int apply_r_mips_26(struct module\n \t}\n \n \tif ((v & 0xf0000000) != (((unsigned long)location + 4) & 0xf0000000)) {\n-\t\tpr_err(\"module %s: relocation overflow\\n\",\n-\t\t       me->name);\n-\t\treturn -ENOEXEC;\n+\t\tv = add_plt_entry(me, location, v + (ofs << 2));\n+\t\tif (!v) {\n+\t\t\tpr_err(\"module %s: relocation overflow\\n\",\n+\t\t\t       me->name);\n+\t\t\treturn -ENOEXEC;\n+\t\t}\n+\t\tofs = 0;\n \t}\n \n \t*location = (*location & ~0x03ffffff) |\n-\t\t    ((base + (v >> 2)) & 0x03ffffff);\n+\t\t    ((ofs + (v >> 2)) & 0x03ffffff);\n \n \treturn 0;\n }\n@@ -446,9 +688,36 @@ int module_finalize(const Elf_Ehdr *hdr,\n \t\tlist_add(&me->arch.dbe_list, &dbe_list);\n \t\tspin_unlock_irq(&dbe_lock);\n \t}\n+\n+\t/* Get rid of the fixup trampoline if we're running the module\n+\t * from physically mapped address space */\n+\tif (me->arch.phys_plt_offset == 0) {\n+\t\t__module_free(me->arch.phys_plt_tbl);\n+\t\tme->arch.phys_plt_tbl = NULL;\n+\t}\n+\tif (me->arch.virt_plt_offset == 0) {\n+\t\t__module_free(me->arch.virt_plt_tbl);\n+\t\tme->arch.virt_plt_tbl = NULL;\n+\t}\n+\n \treturn 0;\n }\n \n+void module_arch_freeing_init(struct module *mod)\n+{\n+\tif (mod->state == MODULE_STATE_LIVE)\n+\t\treturn;\n+\n+\tif (mod->arch.phys_plt_tbl) {\n+\t\t__module_free(mod->arch.phys_plt_tbl);\n+\t\tmod->arch.phys_plt_tbl = NULL;\n+\t}\n+\tif (mod->arch.virt_plt_tbl) {\n+\t\t__module_free(mod->arch.virt_plt_tbl);\n+\t\tmod->arch.virt_plt_tbl = NULL;\n+\t}\n+}\n+\n void module_arch_cleanup(struct module *mod)\n {\n \tspin_lock_irq(&dbe_lock);\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/307-mips_highmem_offset.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nSubject: kernel: adjust mips highmem offset to avoid the need for -mlong-calls on systems with >256M RAM\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n arch/mips/include/asm/mach-generic/spaces.h | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/arch/mips/include/asm/mach-generic/spaces.h\n+++ b/arch/mips/include/asm/mach-generic/spaces.h\n@@ -54,7 +54,7 @@\n  * Memory above this physical address will be considered highmem.\n  */\n #ifndef HIGHMEM_START\n-#define HIGHMEM_START\t\t_AC(0x20000000, UL)\n+#define HIGHMEM_START\t\t_AC(0x10000000, UL)\n #endif\n \n #endif /* CONFIG_32BIT */\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/308-mips32r2_tune.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nSubject: kernel: add -mtune=34kc to MIPS CFLAGS when building for mips32r2\n\nThis provides a good tradeoff across at least 24Kc-74Kc, while also\nproducing smaller code.\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n arch/mips/Makefile | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/arch/mips/Makefile\n+++ b/arch/mips/Makefile\n@@ -174,7 +174,7 @@ cflags-$(CONFIG_CPU_VR41XX)\t+= -march=r4\n cflags-$(CONFIG_CPU_R4X00)\t+= -march=r4600 -Wa,--trap\n cflags-$(CONFIG_CPU_TX49XX)\t+= -march=r4600 -Wa,--trap\n cflags-$(CONFIG_CPU_MIPS32_R1)\t+= -march=mips32 -Wa,--trap\n-cflags-$(CONFIG_CPU_MIPS32_R2)\t+= -march=mips32r2 -Wa,--trap\n+cflags-$(CONFIG_CPU_MIPS32_R2)\t+= -march=mips32r2 -mtune=34kc -Wa,--trap\n cflags-$(CONFIG_CPU_MIPS32_R5)\t+= -march=mips32r5 -Wa,--trap -modd-spreg\n cflags-$(CONFIG_CPU_MIPS32_R6)\t+= -march=mips32r6 -Wa,--trap -modd-spreg\n cflags-$(CONFIG_CPU_MIPS64_R1)\t+= -march=mips64 -Wa,--trap\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/309-MIPS-Add-CPU-option-reporting-to-proc-cpuinfo.patch",
    "content": "From 87ec87c2ad615c1a177cd08ef5fa29fc739f6e50 Mon Sep 17 00:00:00 2001\nFrom: Hauke Mehrtens <hauke@hauke-m.de>\nDate: Sun, 23 Dec 2018 18:06:53 +0100\nSubject: [PATCH] MIPS: Add CPU option reporting to /proc/cpuinfo\n\nMany MIPS CPUs have optional CPU features which are not activates for\nall CPU cores. Print the CPU options which are implemented in the core\nin /proc/cpuinfo. This makes it possible to see what features are\nsupported and which are not supported. This should cover all standard\nMIPS extensions, before it only printed information about the main MIPS\nASEs.\n\nSigned-off-by: Hauke Mehrtens <hauke@hauke-m.de>\n---\n arch/mips/kernel/proc.c | 116 ++++++++++++++++++++++++++++++++++++++++\n 1 file changed, 116 insertions(+)\n\n--- a/arch/mips/kernel/proc.c\n+++ b/arch/mips/kernel/proc.c\n@@ -138,6 +138,120 @@ static int show_cpuinfo(struct seq_file\n \t\tseq_printf(m, \"micromips kernel\\t: %s\\n\",\n \t\t      (read_c0_config3() & MIPS_CONF3_ISA_OE) ?  \"yes\" : \"no\");\n \t}\n+\n+\tseq_printf(m, \"Options implemented\\t:\");\n+\tif (cpu_has_tlb)\n+\t\tseq_printf(m, \"%s\", \" tlb\");\n+\tif (cpu_has_ftlb)\n+\t\tseq_printf(m, \"%s\", \" ftlb\");\n+\tif (cpu_has_tlbinv)\n+\t\tseq_printf(m, \"%s\", \" tlbinv\");\n+\tif (cpu_has_segments)\n+\t\tseq_printf(m, \"%s\", \" segments\");\n+\tif (cpu_has_rixiex)\n+\t\tseq_printf(m, \"%s\", \" rixiex\");\n+\tif (cpu_has_ldpte)\n+\t\tseq_printf(m, \"%s\", \" ldpte\");\n+\tif (cpu_has_maar)\n+\t\tseq_printf(m, \"%s\", \" maar\");\n+\tif (cpu_has_rw_llb)\n+\t\tseq_printf(m, \"%s\", \" rw_llb\");\n+\tif (cpu_has_4kex)\n+\t\tseq_printf(m, \"%s\", \" 4kex\");\n+\tif (cpu_has_3k_cache)\n+\t\tseq_printf(m, \"%s\", \" 3k_cache\");\n+\tif (cpu_has_4k_cache)\n+\t\tseq_printf(m, \"%s\", \" 4k_cache\");\n+\tif (cpu_has_6k_cache)\n+\t\tseq_printf(m, \"%s\", \" 6k_cache\");\n+\tif (cpu_has_8k_cache)\n+\t\tseq_printf(m, \"%s\", \" 8k_cache\");\n+\tif (cpu_has_tx39_cache)\n+\t\tseq_printf(m, \"%s\", \" tx39_cache\");\n+\tif (cpu_has_octeon_cache)\n+\t\tseq_printf(m, \"%s\", \" octeon_cache\");\n+\tif (cpu_has_fpu)\n+\t\tseq_printf(m, \"%s\", \" fpu\");\n+\tif (cpu_has_32fpr)\n+\t\tseq_printf(m, \"%s\", \" 32fpr\");\n+\tif (cpu_has_cache_cdex_p)\n+\t\tseq_printf(m, \"%s\", \" cache_cdex_p\");\n+\tif (cpu_has_cache_cdex_s)\n+\t\tseq_printf(m, \"%s\", \" cache_cdex_s\");\n+\tif (cpu_has_prefetch)\n+\t\tseq_printf(m, \"%s\", \" prefetch\");\n+\tif (cpu_has_mcheck)\n+\t\tseq_printf(m, \"%s\", \" mcheck\");\n+\tif (cpu_has_ejtag)\n+\t\tseq_printf(m, \"%s\", \" ejtag\");\n+\tif (cpu_has_llsc)\n+\t\tseq_printf(m, \"%s\", \" llsc\");\n+\tif (cpu_has_guestctl0ext)\n+\t\tseq_printf(m, \"%s\", \" guestctl0ext\");\n+\tif (cpu_has_guestctl1)\n+\t\tseq_printf(m, \"%s\", \" guestctl1\");\n+\tif (cpu_has_guestctl2)\n+\t\tseq_printf(m, \"%s\", \" guestctl2\");\n+\tif (cpu_has_guestid)\n+\t\tseq_printf(m, \"%s\", \" guestid\");\n+\tif (cpu_has_drg)\n+\t\tseq_printf(m, \"%s\", \" drg\");\n+\tif (cpu_has_rixi)\n+\t\tseq_printf(m, \"%s\", \" rixi\");\n+\tif (cpu_has_lpa)\n+\t\tseq_printf(m, \"%s\", \" lpa\");\n+\tif (cpu_has_mvh)\n+\t\tseq_printf(m, \"%s\", \" mvh\");\n+\tif (cpu_has_vtag_icache)\n+\t\tseq_printf(m, \"%s\", \" vtag_icache\");\n+\tif (cpu_has_dc_aliases)\n+\t\tseq_printf(m, \"%s\", \" dc_aliases\");\n+\tif (cpu_has_ic_fills_f_dc)\n+\t\tseq_printf(m, \"%s\", \" ic_fills_f_dc\");\n+\tif (cpu_has_pindexed_dcache)\n+\t\tseq_printf(m, \"%s\", \" pindexed_dcache\");\n+\tif (cpu_has_userlocal)\n+\t\tseq_printf(m, \"%s\", \" userlocal\");\n+\tif (cpu_has_nofpuex)\n+\t\tseq_printf(m, \"%s\", \" nofpuex\");\n+\tif (cpu_has_vint)\n+\t\tseq_printf(m, \"%s\", \" vint\");\n+\tif (cpu_has_veic)\n+\t\tseq_printf(m, \"%s\", \" veic\");\n+\tif (cpu_has_inclusive_pcaches)\n+\t\tseq_printf(m, \"%s\", \" inclusive_pcaches\");\n+\tif (cpu_has_perf_cntr_intr_bit)\n+\t\tseq_printf(m, \"%s\", \" perf_cntr_intr_bit\");\n+\tif (cpu_has_ufr)\n+\t\tseq_printf(m, \"%s\", \" ufr\");\n+\tif (cpu_has_fre)\n+\t\tseq_printf(m, \"%s\", \" fre\");\n+\tif (cpu_has_cdmm)\n+\t\tseq_printf(m, \"%s\", \" cdmm\");\n+\tif (cpu_has_small_pages)\n+\t\tseq_printf(m, \"%s\", \" small_pages\");\n+\tif (cpu_has_nan_legacy)\n+\t\tseq_printf(m, \"%s\", \" nan_legacy\");\n+\tif (cpu_has_nan_2008)\n+\t\tseq_printf(m, \"%s\", \" nan_2008\");\n+\tif (cpu_has_ebase_wg)\n+\t\tseq_printf(m, \"%s\", \" ebase_wg\");\n+\tif (cpu_has_badinstr)\n+\t\tseq_printf(m, \"%s\", \" badinstr\");\n+\tif (cpu_has_badinstrp)\n+\t\tseq_printf(m, \"%s\", \" badinstrp\");\n+\tif (cpu_has_contextconfig)\n+\t\tseq_printf(m, \"%s\", \" contextconfig\");\n+\tif (cpu_has_perf)\n+\t\tseq_printf(m, \"%s\", \" perf\");\n+\tif (cpu_has_shared_ftlb_ram)\n+\t\tseq_printf(m, \"%s\", \" shared_ftlb_ram\");\n+\tif (cpu_has_shared_ftlb_entries)\n+\t\tseq_printf(m, \"%s\", \" shared_ftlb_entries\");\n+\tif (cpu_has_mipsmt_pertccounters)\n+\t\tseq_printf(m, \"%s\", \" mipsmt_pertccounters\");\n+\tseq_printf(m, \"\\n\");\n+\n \tseq_printf(m, \"shadow register sets\\t: %d\\n\",\n \t\t      cpu_data[n].srsets);\n \tseq_printf(m, \"kscratch registers\\t: %d\\n\",\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/310-arm_module_unresolved_weak_sym.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nSubject: fix errors in unresolved weak symbols on arm\n\nlede-commit: 570699d4838a907c3ef9f2819bf19eb72997b32f\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n arch/arm/kernel/module.c | 4 ++++\n 1 file changed, 4 insertions(+)\n\n--- a/arch/arm/kernel/module.c\n+++ b/arch/arm/kernel/module.c\n@@ -105,6 +105,10 @@ apply_relocate(Elf32_Shdr *sechdrs, cons\n \t\t\treturn -ENOEXEC;\n \t\t}\n \n+\t\tif ((IS_ERR_VALUE(sym->st_value) || !sym->st_value) &&\n+\t\t    ELF_ST_BIND(sym->st_info) == STB_WEAK)\n+\t\t\tcontinue;\n+\n \t\tloc = dstsec->sh_addr + rel->r_offset;\n \n \t\tswitch (ELF32_R_TYPE(rel->r_info)) {\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/330-MIPS-kexec-Accept-command-line-parameters-from-users.patch",
    "content": "From: Yousong Zhou <yszhou4tech@gmail.com>\nSubject: MIPS: kexec: Accept command line parameters from userspace.\n\nSigned-off-by: Yousong Zhou <yszhou4tech@gmail.com>\n---\n arch/mips/kernel/machine_kexec.c   |  153 +++++++++++++++++++++++++++++++-----\n arch/mips/kernel/machine_kexec.h   |   20 +++++\n arch/mips/kernel/relocate_kernel.S |   21 +++--\n 3 files changed, 167 insertions(+), 27 deletions(-)\n create mode 100644 arch/mips/kernel/machine_kexec.h\n\n--- a/arch/mips/kernel/machine_kexec.c\n+++ b/arch/mips/kernel/machine_kexec.c\n@@ -9,14 +9,11 @@\n #include <linux/delay.h>\n #include <linux/libfdt.h>\n \n+#include <asm/bootinfo.h>\n #include <asm/cacheflush.h>\n #include <asm/page.h>\n-\n-extern const unsigned char relocate_new_kernel[];\n-extern const size_t relocate_new_kernel_size;\n-\n-extern unsigned long kexec_start_address;\n-extern unsigned long kexec_indirection_page;\n+#include <linux/uaccess.h>\n+#include \"machine_kexec.h\"\n \n static unsigned long reboot_code_buffer;\n \n@@ -30,6 +27,101 @@ void (*_crash_smp_send_stop)(void) = NUL\n void (*_machine_kexec_shutdown)(void) = NULL;\n void (*_machine_crash_shutdown)(struct pt_regs *regs) = NULL;\n \n+static void machine_kexec_print_args(void)\n+{\n+\tunsigned long argc = (int)kexec_args[0];\n+\tint i;\n+\n+\tpr_info(\"kexec_args[0] (argc): %lu\\n\", argc);\n+\tpr_info(\"kexec_args[1] (argv): %p\\n\", (void *)kexec_args[1]);\n+\tpr_info(\"kexec_args[2] (env ): %p\\n\", (void *)kexec_args[2]);\n+\tpr_info(\"kexec_args[3] (desc): %p\\n\", (void *)kexec_args[3]);\n+\n+\tfor (i = 0; i < argc; i++) {\n+\t\tpr_info(\"kexec_argv[%d] = %p, %s\\n\",\n+\t\t\t\ti, kexec_argv[i], kexec_argv[i]);\n+\t}\n+}\n+\n+static void machine_kexec_init_argv(struct kimage *image)\n+{\n+\tvoid __user *buf = NULL;\n+\tsize_t bufsz;\n+\tsize_t size;\n+\tint i;\n+\n+\tbufsz = 0;\n+\tfor (i = 0; i < image->nr_segments; i++) {\n+\t\tstruct kexec_segment *seg;\n+\n+\t\tseg = &image->segment[i];\n+\t\tif (seg->bufsz < 6)\n+\t\t\tcontinue;\n+\n+\t\tif (strncmp((char *) seg->buf, \"kexec \", 6))\n+\t\t\tcontinue;\n+\n+\t\tbuf = seg->buf;\n+\t\tbufsz = seg->bufsz;\n+\t\tbreak;\n+\t}\n+\n+\tif (!buf)\n+\t\treturn;\n+\n+\tsize = KEXEC_COMMAND_LINE_SIZE;\n+\tsize = min(size, bufsz);\n+\tif (size < bufsz)\n+\t\tpr_warn(\"kexec command line truncated to %zd bytes\\n\", size);\n+\n+\t/* Copy to kernel space */\n+\tif (copy_from_user(kexec_argv_buf, buf, size))\n+\t\tpr_warn(\"kexec command line copy to kernel space failed\\n\");\n+\n+\tkexec_argv_buf[size - 1] = 0;\n+}\n+\n+static void machine_kexec_parse_argv(struct kimage *image)\n+{\n+\tchar *reboot_code_buffer;\n+\tint reloc_delta;\n+\tchar *ptr;\n+\tint argc;\n+\tint i;\n+\n+\tptr = kexec_argv_buf;\n+\targc = 0;\n+\n+\t/*\n+\t * convert command line string to array of parameters\n+\t * (as bootloader does).\n+\t */\n+\twhile (ptr && *ptr && (KEXEC_MAX_ARGC > argc)) {\n+\t\tif (*ptr == ' ') {\n+\t\t\t*ptr++ = '\\0';\n+\t\t\tcontinue;\n+\t\t}\n+\n+\t\tkexec_argv[argc++] = ptr;\n+\t\tptr = strchr(ptr, ' ');\n+\t}\n+\n+\tif (!argc)\n+\t\treturn;\n+\n+\tkexec_args[0] = argc;\n+\tkexec_args[1] = (unsigned long)kexec_argv;\n+\tkexec_args[2] = 0;\n+\tkexec_args[3] = 0;\n+\n+\treboot_code_buffer = page_address(image->control_code_page);\n+\treloc_delta = reboot_code_buffer - (char *)kexec_relocate_new_kernel;\n+\n+\tkexec_args[1] += reloc_delta;\n+\tfor (i = 0; i < argc; i++)\n+\t\tkexec_argv[i] += reloc_delta;\n+}\n+\n static void kexec_image_info(const struct kimage *kimage)\n {\n \tunsigned long i;\n@@ -99,6 +191,18 @@ machine_kexec_prepare(struct kimage *kim\n #endif\n \n \tkexec_image_info(kimage);\n+\t/*\n+\t * Whenever arguments passed from kexec-tools, Init the arguments as\n+\t * the original ones to try avoiding booting failure.\n+\t */\n+\n+\tkexec_args[0] = fw_arg0;\n+\tkexec_args[1] = fw_arg1;\n+\tkexec_args[2] = fw_arg2;\n+\tkexec_args[3] = fw_arg3;\n+\n+\tmachine_kexec_init_argv(kimage);\n+\tmachine_kexec_parse_argv(kimage);\n \n \tif (_machine_kexec_prepare)\n \t\treturn _machine_kexec_prepare(kimage);\n@@ -161,7 +265,7 @@ machine_crash_shutdown(struct pt_regs *r\n void kexec_nonboot_cpu_jump(void)\n {\n \tlocal_flush_icache_range((unsigned long)relocated_kexec_smp_wait,\n-\t\t\t\t reboot_code_buffer + relocate_new_kernel_size);\n+\t\t\t\t reboot_code_buffer + KEXEC_RELOCATE_NEW_KERNEL_SIZE);\n \n \trelocated_kexec_smp_wait(NULL);\n }\n@@ -199,7 +303,7 @@ void kexec_reboot(void)\n \t * machine_kexec() CPU.\n \t */\n \tlocal_flush_icache_range(reboot_code_buffer,\n-\t\t\t\t reboot_code_buffer + relocate_new_kernel_size);\n+\t\t\t\t reboot_code_buffer + KEXEC_RELOCATE_NEW_KERNEL_SIZE);\n \n \tdo_kexec = (void *)reboot_code_buffer;\n \tdo_kexec();\n@@ -212,10 +316,12 @@ machine_kexec(struct kimage *image)\n \tunsigned long *ptr;\n \n \treboot_code_buffer =\n-\t  (unsigned long)page_address(image->control_code_page);\n+\t\t(unsigned long)page_address(image->control_code_page);\n+\tpr_info(\"reboot_code_buffer = %p\\n\", (void *)reboot_code_buffer);\n \n \tkexec_start_address =\n \t\t(unsigned long) phys_to_virt(image->start);\n+\tpr_info(\"kexec_start_address = %p\\n\", (void *)kexec_start_address);\n \n \tif (image->type == KEXEC_TYPE_DEFAULT) {\n \t\tkexec_indirection_page =\n@@ -223,9 +329,19 @@ machine_kexec(struct kimage *image)\n \t} else {\n \t\tkexec_indirection_page = (unsigned long)&image->head;\n \t}\n+\tpr_info(\"kexec_indirection_page = %p\\n\", (void *)kexec_indirection_page);\n \n-\tmemcpy((void*)reboot_code_buffer, relocate_new_kernel,\n-\t       relocate_new_kernel_size);\n+\tpr_info(\"Where is memcpy: %p\\n\", memcpy);\n+\tpr_info(\"kexec_relocate_new_kernel = %p, kexec_relocate_new_kernel_end = %p\\n\",\n+\t\t(void *)kexec_relocate_new_kernel, &kexec_relocate_new_kernel_end);\n+\tpr_info(\"Copy %lu bytes from %p to %p\\n\", KEXEC_RELOCATE_NEW_KERNEL_SIZE,\n+\t\t(void *)kexec_relocate_new_kernel, (void *)reboot_code_buffer);\n+\tmemcpy((void*)reboot_code_buffer, kexec_relocate_new_kernel,\n+\t       KEXEC_RELOCATE_NEW_KERNEL_SIZE);\n+\n+\tpr_info(\"Before _print_args().\\n\");\n+\tmachine_kexec_print_args();\n+\tpr_info(\"Before eval loop.\\n\");\n \n \t/*\n \t * The generic kexec code builds a page list with physical\n@@ -256,7 +372,7 @@ machine_kexec(struct kimage *image)\n #ifdef CONFIG_SMP\n \t/* All secondary cpus now may jump to kexec_wait cycle */\n \trelocated_kexec_smp_wait = reboot_code_buffer +\n-\t\t(void *)(kexec_smp_wait - relocate_new_kernel);\n+\t\t(void *)(kexec_smp_wait - kexec_relocate_new_kernel);\n \tsmp_wmb();\n \tatomic_set(&kexec_ready_to_reboot, 1);\n #endif\n--- /dev/null\n+++ b/arch/mips/kernel/machine_kexec.h\n@@ -0,0 +1,20 @@\n+#ifndef _MACHINE_KEXEC_H\n+#define _MACHINE_KEXEC_H\n+\n+#ifndef __ASSEMBLY__\n+extern const unsigned char kexec_relocate_new_kernel[];\n+extern unsigned long kexec_relocate_new_kernel_end;\n+extern unsigned long kexec_start_address;\n+extern unsigned long kexec_indirection_page;\n+\n+extern char kexec_argv_buf[];\n+extern char *kexec_argv[];\n+\n+#define KEXEC_RELOCATE_NEW_KERNEL_SIZE\t((unsigned long)&kexec_relocate_new_kernel_end - (unsigned long)kexec_relocate_new_kernel)\n+#endif /* !__ASSEMBLY__ */\n+\n+#define KEXEC_COMMAND_LINE_SIZE\t\t256\n+#define KEXEC_ARGV_SIZE\t\t\t(KEXEC_COMMAND_LINE_SIZE / 16)\n+#define KEXEC_MAX_ARGC\t\t\t(KEXEC_ARGV_SIZE / sizeof(long))\n+\n+#endif\n--- a/arch/mips/kernel/relocate_kernel.S\n+++ b/arch/mips/kernel/relocate_kernel.S\n@@ -10,8 +10,9 @@\n #include <asm/mipsregs.h>\n #include <asm/stackframe.h>\n #include <asm/addrspace.h>\n+#include \"machine_kexec.h\"\n \n-LEAF(relocate_new_kernel)\n+LEAF(kexec_relocate_new_kernel)\n \tPTR_L a0,\targ0\n \tPTR_L a1,\targ1\n \tPTR_L a2,\targ2\n@@ -96,7 +97,7 @@ done:\n #endif\n \t/* jump to kexec_start_address */\n \tj\t\ts1\n-\tEND(relocate_new_kernel)\n+\tEND(kexec_relocate_new_kernel)\n \n #ifdef CONFIG_SMP\n /*\n@@ -182,9 +183,15 @@ kexec_indirection_page:\n \tPTR\t\t0\n \t.size\t\tkexec_indirection_page, PTRSIZE\n \n-relocate_new_kernel_end:\n+kexec_argv_buf:\n+\tEXPORT(kexec_argv_buf)\n+\t.skip\t\tKEXEC_COMMAND_LINE_SIZE\n+\t.size\t\tkexec_argv_buf, KEXEC_COMMAND_LINE_SIZE\n+\n+kexec_argv:\n+\tEXPORT(kexec_argv)\n+\t.skip\t\tKEXEC_ARGV_SIZE\n+\t.size\t\tkexec_argv, KEXEC_ARGV_SIZE\n \n-relocate_new_kernel_size:\n-\tEXPORT(relocate_new_kernel_size)\n-\tPTR\t\trelocate_new_kernel_end - relocate_new_kernel\n-\t.size\t\trelocate_new_kernel_size, PTRSIZE\n+kexec_relocate_new_kernel_end:\n+\tEXPORT(kexec_relocate_new_kernel_end)\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/332-arc-add-OWRTDTB-section.patch",
    "content": "From bb0c3b0175240bf152fd7c644821a0cf9f77c37c Mon Sep 17 00:00:00 2001\nFrom: Evgeniy Didin <Evgeniy.Didin@synopsys.com>\nDate: Fri, 15 Mar 2019 18:53:38 +0300\nSubject: [PATCH] arc add OWRTDTB section\n\nThis change allows OpenWRT to patch resulting kernel binary with\nexternal .dtb.\n\nThat allows us to re-use exactky the same vmlinux on different boards\ngiven its ARC core configurations match (at least cache line sizes etc).\n\n\"\"patch-dtb\" searches for ASCII \"OWRTDTB:\" strign and copies external\n.dtb right after it, keeping the string in place.\n\nSigned-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>\nSigned-off-by: Alexey Brodkin <abrodkin@synopsys.com>\nSigned-off-by: Evgeniy Didin <Evgeniy.Didin@synopsys.com>\n---\n arch/arc/kernel/head.S        | 10 ++++++++++\n arch/arc/kernel/setup.c       |  4 +++-\n arch/arc/kernel/vmlinux.lds.S | 13 +++++++++++++\n 3 files changed, 26 insertions(+), 1 deletion(-)\n\n--- a/arch/arc/kernel/head.S\n+++ b/arch/arc/kernel/head.S\n@@ -88,6 +88,16 @@\n \tDSP_EARLY_INIT\n .endm\n \n+\t; Here \"patch-dtb\" will embed external .dtb\n+\t; Note \"patch-dtb\" searches for ASCII \"OWRTDTB:\" string\n+\t; and pastes .dtb right after it, hense the string precedes\n+\t; __image_dtb symbol.\n+\t.section .owrt, \"aw\",@progbits\n+\t.ascii  \"OWRTDTB:\"\n+ENTRY(__image_dtb)\n+\t.fill   0x4000\n+END(__image_dtb)\n+\n \t.section .init.text, \"ax\",@progbits\n \n ;----------------------------------------------------------------\n--- a/arch/arc/kernel/setup.c\n+++ b/arch/arc/kernel/setup.c\n@@ -495,6 +495,8 @@ static inline bool uboot_arg_invalid(uns\n /* We always pass 0 as magic from U-boot */\n #define UBOOT_MAGIC_VALUE\t0\n \n+extern struct boot_param_header __image_dtb;\n+\n void __init handle_uboot_args(void)\n {\n \tbool use_embedded_dtb = true;\n@@ -533,7 +535,7 @@ void __init handle_uboot_args(void)\n ignore_uboot_args:\n \n \tif (use_embedded_dtb) {\n-\t\tmachine_desc = setup_machine_fdt(__dtb_start);\n+\t\tmachine_desc = setup_machine_fdt(&__image_dtb);\n \t\tif (!machine_desc)\n \t\t\tpanic(\"Embedded DT invalid\\n\");\n \t}\n--- a/arch/arc/kernel/vmlinux.lds.S\n+++ b/arch/arc/kernel/vmlinux.lds.S\n@@ -27,6 +27,19 @@ SECTIONS\n \n \t. = CONFIG_LINUX_LINK_BASE;\n \n+\t/*\n+\t* In OpenWRT we want to patch built binary embedding .dtb of choice.\n+\t* This is implemented with \"patch-dtb\" utility which searches for\n+\t* \"OWRTDTB:\" string in first 16k of image and if it is found\n+\t* copies .dtb right after mentioned string.\n+\t*\n+\t* Note: \"OWRTDTB:\" won't be overwritten with .dtb, .dtb will follow it.\n+\t*/\n+ \t.owrt : {\n+\t\t*(.owrt)\n+\t. = ALIGN(PAGE_SIZE);\n+\t}\n+\n \t_int_vec_base_lds = .;\n \t.vector : {\n \t\t*(.vector)\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/333-arc-enable-unaligned-access-in-kernel-mode.patch",
    "content": "From: Alexey Brodkin <abrodkin@synopsys.com>\nSubject: arc: enable unaligned access in kernel mode\n\nThis enables misaligned access handling even in kernel mode.\nSome wireless drivers (ath9k-htc and mt7601u) use misaligned accesses\nhere and there and to cope with that without fixing stuff in the drivers\nwe're just gracefully handling it on ARC.\n\nSigned-off-by: Alexey Brodkin <abrodkin@synopsys.com>\n---\n arch/arc/kernel/unaligned.c | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/arch/arc/kernel/unaligned.c\n+++ b/arch/arc/kernel/unaligned.c\n@@ -202,7 +202,7 @@ int misaligned_fixup(unsigned long addre\n \tchar buf[TASK_COMM_LEN];\n \n \t/* handle user mode only and only if enabled by sysadmin */\n-\tif (!user_mode(regs) || !unaligned_enabled)\n+\tif (!unaligned_enabled)\n \t\treturn 1;\n \n \tif (no_unaligned_warning) {\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/342-powerpc-Enable-kernel-XZ-compression-option-on-PPC_8.patch",
    "content": "From 66770a004afe10df11d3902e16eaa0c2c39436bb Mon Sep 17 00:00:00 2001\nFrom: Pawel Dembicki <paweldembicki@gmail.com>\nDate: Fri, 24 May 2019 17:56:19 +0200\nSubject: [PATCH] powerpc: Enable kernel XZ compression option on PPC_85xx\n\nEnable kernel XZ compression option on PPC_85xx. Tested with\nsimpleImage on TP-Link TL-WDR4900 (Freescale P1014 processor).\n\nSuggested-by: Christian Lamparter <chunkeey@gmail.com>\nSigned-off-by: Pawel Dembicki <paweldembicki@gmail.com>\n---\n arch/powerpc/Kconfig | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/arch/powerpc/Kconfig\n+++ b/arch/powerpc/Kconfig\n@@ -214,7 +214,7 @@ config PPC\n \tselect HAVE_KERNEL_GZIP\n \tselect HAVE_KERNEL_LZMA\t\t\tif DEFAULT_UIMAGE\n \tselect HAVE_KERNEL_LZO\t\t\tif DEFAULT_UIMAGE\n-\tselect HAVE_KERNEL_XZ\t\t\tif PPC_BOOK3S || 44x\n+\tselect HAVE_KERNEL_XZ\t\t\tif PPC_BOOK3S || 44x || PPC_85xx\n \tselect HAVE_KPROBES\n \tselect HAVE_KPROBES_ON_FTRACE\n \tselect HAVE_KRETPROBES\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/400-mtd-mtdsplit-support.patch",
    "content": "--- a/drivers/mtd/Kconfig\n+++ b/drivers/mtd/Kconfig\n@@ -12,6 +12,25 @@ menuconfig MTD\n \n if MTD\n \n+menu \"OpenWrt specific MTD options\"\n+\n+config MTD_ROOTFS_ROOT_DEV\n+\tbool \"Automatically set 'rootfs' partition to be root filesystem\"\n+\tdefault y\n+\n+config MTD_SPLIT_FIRMWARE\n+\tbool \"Automatically split firmware partition for kernel+rootfs\"\n+\tdefault y\n+\n+config MTD_SPLIT_FIRMWARE_NAME\n+\tstring \"Firmware partition name\"\n+\tdepends on MTD_SPLIT_FIRMWARE\n+\tdefault \"firmware\"\n+\n+source \"drivers/mtd/mtdsplit/Kconfig\"\n+\n+endmenu\n+\n config MTD_TESTS\n \ttristate \"MTD tests support (DANGEROUS)\"\n \tdepends on m\n--- a/drivers/mtd/mtdpart.c\n+++ b/drivers/mtd/mtdpart.c\n@@ -15,10 +15,12 @@\n #include <linux/kmod.h>\n #include <linux/mtd/mtd.h>\n #include <linux/mtd/partitions.h>\n+#include <linux/magic.h>\n #include <linux/err.h>\n #include <linux/of.h>\n \n #include \"mtdcore.h\"\n+#include \"mtdsplit/mtdsplit.h\"\n \n /*\n  * MTD methods which simply translate the effective address and pass through\n@@ -236,6 +238,146 @@ static int mtd_add_partition_attrs(struc\n \treturn ret;\n }\n \n+static DEFINE_SPINLOCK(part_parser_lock);\n+static LIST_HEAD(part_parsers);\n+\n+static struct mtd_part_parser *mtd_part_parser_get(const char *name)\n+{\n+\tstruct mtd_part_parser *p, *ret = NULL;\n+\n+\tspin_lock(&part_parser_lock);\n+\n+\tlist_for_each_entry(p, &part_parsers, list)\n+\t\tif (!strcmp(p->name, name) && try_module_get(p->owner)) {\n+\t\t\tret = p;\n+\t\t\tbreak;\n+\t\t}\n+\n+\tspin_unlock(&part_parser_lock);\n+\n+\treturn ret;\n+}\n+\n+static inline void mtd_part_parser_put(const struct mtd_part_parser *p)\n+{\n+\tmodule_put(p->owner);\n+}\n+\n+static struct mtd_part_parser *\n+get_partition_parser_by_type(enum mtd_parser_type type,\n+\t\t\t     struct mtd_part_parser *start)\n+{\n+\tstruct mtd_part_parser *p, *ret = NULL;\n+\n+\tspin_lock(&part_parser_lock);\n+\n+\tp = list_prepare_entry(start, &part_parsers, list);\n+\tif (start)\n+\t\tmtd_part_parser_put(start);\n+\n+\tlist_for_each_entry_continue(p, &part_parsers, list) {\n+\t\tif (p->type == type && try_module_get(p->owner)) {\n+\t\t\tret = p;\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\n+\tspin_unlock(&part_parser_lock);\n+\n+\treturn ret;\n+}\n+\n+static int parse_mtd_partitions_by_type(struct mtd_info *master,\n+\t\t\t\t\tenum mtd_parser_type type,\n+\t\t\t\t\tconst struct mtd_partition **pparts,\n+\t\t\t\t\tstruct mtd_part_parser_data *data)\n+{\n+\tstruct mtd_part_parser *prev = NULL;\n+\tint ret = 0;\n+\n+\twhile (1) {\n+\t\tstruct mtd_part_parser *parser;\n+\n+\t\tparser = get_partition_parser_by_type(type, prev);\n+\t\tif (!parser)\n+\t\t\tbreak;\n+\n+\t\tret = (*parser->parse_fn)(master, pparts, data);\n+\n+\t\tif (ret > 0) {\n+\t\t\tmtd_part_parser_put(parser);\n+\t\t\tprintk(KERN_NOTICE\n+\t\t\t       \"%d %s partitions found on MTD device %s\\n\",\n+\t\t\t       ret, parser->name, master->name);\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\tprev = parser;\n+\t}\n+\n+\treturn ret;\n+}\n+\n+static int\n+run_parsers_by_type(struct mtd_info *child, enum mtd_parser_type type)\n+{\n+\tstruct mtd_partition *parts;\n+\tint nr_parts;\n+\tint i;\n+\n+\tnr_parts = parse_mtd_partitions_by_type(child, type, (const struct mtd_partition **)&parts,\n+\t\t\t\t\t\tNULL);\n+\tif (nr_parts <= 0)\n+\t\treturn nr_parts;\n+\n+\tif (WARN_ON(!parts))\n+\t\treturn 0;\n+\n+\tfor (i = 0; i < nr_parts; i++) {\n+\t\t/* adjust partition offsets */\n+\t\tparts[i].offset += child->part.offset;\n+\n+\t\tmtd_add_partition(child->parent,\n+\t\t\t\t  parts[i].name,\n+\t\t\t\t  parts[i].offset,\n+\t\t\t\t  parts[i].size);\n+\t}\n+\n+\tkfree(parts);\n+\n+\treturn nr_parts;\n+}\n+\n+#ifdef CONFIG_MTD_SPLIT_FIRMWARE_NAME\n+#define SPLIT_FIRMWARE_NAME\tCONFIG_MTD_SPLIT_FIRMWARE_NAME\n+#else\n+#define SPLIT_FIRMWARE_NAME\t\"unused\"\n+#endif\n+\n+static void split_firmware(struct mtd_info *master, struct mtd_info *part)\n+{\n+\trun_parsers_by_type(part, MTD_PARSER_TYPE_FIRMWARE);\n+}\n+\n+static void mtd_partition_split(struct mtd_info *master, struct mtd_info *part)\n+{\n+\tstatic int rootfs_found = 0;\n+\n+\tif (rootfs_found)\n+\t\treturn;\n+\n+\tif (!strcmp(part->name, \"rootfs\")) {\n+\t\trun_parsers_by_type(part, MTD_PARSER_TYPE_ROOTFS);\n+\n+\t\trootfs_found = 1;\n+\t}\n+\n+\tif (IS_ENABLED(CONFIG_MTD_SPLIT_FIRMWARE) &&\n+\t    !strcmp(part->name, SPLIT_FIRMWARE_NAME) &&\n+\t    !of_find_property(mtd_get_of_node(part), \"compatible\", NULL))\n+\t\tsplit_firmware(master, part);\n+}\n+\n int mtd_add_partition(struct mtd_info *parent, const char *name,\n \t\t      long long offset, long long length)\n {\n@@ -274,6 +416,7 @@ int mtd_add_partition(struct mtd_info *p\n \tif (ret)\n \t\tgoto err_remove_part;\n \n+\tmtd_partition_split(parent, child);\n \tmtd_add_partition_attrs(child);\n \n \treturn 0;\n@@ -422,6 +565,7 @@ int add_mtd_partitions(struct mtd_info *\n \t\t\tgoto err_del_partitions;\n \t\t}\n \n+\t\tmtd_partition_split(master, child);\n \t\tmtd_add_partition_attrs(child);\n \n \t\t/* Look for subpartitions */\n@@ -438,31 +582,6 @@ err_del_partitions:\n \treturn ret;\n }\n \n-static DEFINE_SPINLOCK(part_parser_lock);\n-static LIST_HEAD(part_parsers);\n-\n-static struct mtd_part_parser *mtd_part_parser_get(const char *name)\n-{\n-\tstruct mtd_part_parser *p, *ret = NULL;\n-\n-\tspin_lock(&part_parser_lock);\n-\n-\tlist_for_each_entry(p, &part_parsers, list)\n-\t\tif (!strcmp(p->name, name) && try_module_get(p->owner)) {\n-\t\t\tret = p;\n-\t\t\tbreak;\n-\t\t}\n-\n-\tspin_unlock(&part_parser_lock);\n-\n-\treturn ret;\n-}\n-\n-static inline void mtd_part_parser_put(const struct mtd_part_parser *p)\n-{\n-\tmodule_put(p->owner);\n-}\n-\n /*\n  * Many partition parsers just expected the core to kfree() all their data in\n  * one chunk. Do that by default.\n--- a/include/linux/mtd/partitions.h\n+++ b/include/linux/mtd/partitions.h\n@@ -75,6 +75,12 @@ struct mtd_part_parser_data {\n  * Functions dealing with the various ways of partitioning the space\n  */\n \n+enum mtd_parser_type {\n+\tMTD_PARSER_TYPE_DEVICE = 0,\n+\tMTD_PARSER_TYPE_ROOTFS,\n+\tMTD_PARSER_TYPE_FIRMWARE,\n+};\n+\n struct mtd_part_parser {\n \tstruct list_head list;\n \tstruct module *owner;\n@@ -83,6 +89,7 @@ struct mtd_part_parser {\n \tint (*parse_fn)(struct mtd_info *, const struct mtd_partition **,\n \t\t\tstruct mtd_part_parser_data *);\n \tvoid (*cleanup)(const struct mtd_partition *pparts, int nr_parts);\n+\tenum mtd_parser_type type;\n };\n \n /* Container for passing around a set of parsed partitions */\n--- a/drivers/mtd/Makefile\n+++ b/drivers/mtd/Makefile\n@@ -9,6 +9,8 @@ mtd-y\t\t\t\t:= mtdcore.o mtdsuper.o mtdconc\n \n obj-y\t\t\t\t+= parsers/\n \n+obj-$(CONFIG_MTD_SPLIT)\t\t+= mtdsplit/\n+\n # 'Users' - code which presents functionality to userspace.\n obj-$(CONFIG_MTD_BLKDEVS)\t+= mtd_blkdevs.o\n obj-$(CONFIG_MTD_BLOCK)\t\t+= mtdblock.o\n--- a/include/linux/mtd/mtd.h\n+++ b/include/linux/mtd/mtd.h\n@@ -608,6 +608,24 @@ static inline void mtd_align_erase_req(s\n \t\treq->len += mtd->erasesize - mod;\n }\n \n+static inline uint64_t mtd_roundup_to_eb(uint64_t sz, struct mtd_info *mtd)\n+{\n+\tif (mtd_mod_by_eb(sz, mtd) == 0)\n+\t\treturn sz;\n+\n+\t/* Round up to next erase block */\n+\treturn (mtd_div_by_eb(sz, mtd) + 1) * mtd->erasesize;\n+}\n+\n+static inline uint64_t mtd_rounddown_to_eb(uint64_t sz, struct mtd_info *mtd)\n+{\n+\tif (mtd_mod_by_eb(sz, mtd) == 0)\n+\t\treturn sz;\n+\n+\t/* Round down to the start of the current erase block */\n+\treturn (mtd_div_by_eb(sz, mtd)) * mtd->erasesize;\n+}\n+\n static inline uint32_t mtd_div_by_ws(uint64_t sz, struct mtd_info *mtd)\n {\n \tif (mtd->writesize_shift)\n@@ -680,6 +698,13 @@ extern void __put_mtd_device(struct mtd_\n extern struct mtd_info *get_mtd_device_nm(const char *name);\n extern void put_mtd_device(struct mtd_info *mtd);\n \n+static inline uint64_t mtdpart_get_offset(const struct mtd_info *mtd)\n+{\n+\tif (!mtd_is_partition(mtd))\n+\t\treturn 0;\n+\n+\treturn mtd->part.offset;\n+}\n \n struct mtd_notifier {\n \tvoid (*add)(struct mtd_info *mtd);\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/402-mtd-spi-nor-write-support-for-minor-aligned-partitions.patch",
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Tue,\n 8 Jun 2021 00:07:35 -0400 (EDT)\nFrom: John Thomson <git@johnthomson.fastmail.com.au>\nTo: Miquel Raynal <miquel.raynal@bootlin.com>,\n Richard Weinberger <richard@nod.at>, Vignesh Raghavendra <vigneshr@ti.com>,\n Tudor Ambarus <tudor.ambarus@microchip.com>,\n Michael Walle <michael@walle.cc>, Pratyush Yadav <p.yadav@ti.com>,\n linux-mtd@lists.infradead.org\nCc: linux-kernel@vger.kernel.org,\n John Thomson <git@johnthomson.fastmail.com.au>,\n kernel test robot <lkp@intel.com>, Dan Carpenter <dan.carpenter@oracle.com>\nSubject: [PATCH] mtd: spi-nor: write support for minor aligned partitions\nDate: Tue,  8 Jun 2021 14:07:19 +1000\nMessage-Id: <20210608040719.14431-1-git@johnthomson.fastmail.com.au>\nX-Mailer: git-send-email 2.31.1\nMIME-Version: 1.0\nX-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 \nX-CRM114-CacheID: sfid-20210607_210745_712053_67A7D864 \nX-CRM114-Status: GOOD (  26.99  )\nX-Spam-Score: -0.8 (/)\nX-Spam-Report: Spam detection software,\n running on the system \"bombadil.infradead.org\",\n has NOT identified this incoming email as spam.  The original\n message has been attached to this so you can view it or label\n similar future email.  If you have any questions, see\n the administrator of that system for details.\n Content preview:  Do not prevent writing to mtd partitions where a partition\n boundary sits on a minor erasesize boundary. This addresses a FIXME that\n has been present since the start of the linux git history: /* Doesn' [...]\n Content analysis details:   (-0.8 points, 5.0 required)\n pts rule name              description\n ---- ----------------------\n --------------------------------------------------\n -0.7 RCVD_IN_DNSWL_LOW      RBL: Sender listed at https://www.dnswl.org/,\n low trust [66.111.4.221 listed in list.dnswl.org]\n -0.0 SPF_PASS               SPF: sender matches SPF record\n -0.0 SPF_HELO_PASS          SPF: HELO matches SPF record\n 0.0 RCVD_IN_MSPIKE_H3      RBL: Good reputation (+3)\n [66.111.4.221 listed in wl.mailspike.net]\n -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature\n 0.1 DKIM_SIGNED            Message has a DKIM or DK signature,\n not necessarily\n valid\n -0.1 DKIM_VALID_EF          Message has a valid DKIM or DK signature from\n envelope-from domain\n 0.0 RCVD_IN_MSPIKE_WL      Mailspike good senders\nX-BeenThere: linux-mtd@lists.infradead.org\nX-Mailman-Version: 2.1.34\nPrecedence: list\nList-Id: Linux MTD discussion mailing list <linux-mtd.lists.infradead.org>\nList-Unsubscribe: <http://lists.infradead.org/mailman/options/linux-mtd>,\n <mailto:linux-mtd-request@lists.infradead.org?subject=unsubscribe>\nList-Archive: <http://lists.infradead.org/pipermail/linux-mtd/>\nList-Post: <mailto:linux-mtd@lists.infradead.org>\nList-Help: <mailto:linux-mtd-request@lists.infradead.org?subject=help>\nList-Subscribe: <http://lists.infradead.org/mailman/listinfo/linux-mtd>,\n <mailto:linux-mtd-request@lists.infradead.org?subject=subscribe>\nSender: \"linux-mtd\" <linux-mtd-bounces@lists.infradead.org>\nErrors-To: linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org\n\nDo not prevent writing to mtd partitions where a partition boundary sits\non a minor erasesize boundary.\nThis addresses a FIXME that has been present since the start of the\nlinux git history:\n/* Doesn't start on a boundary of major erase size */\n/* FIXME: Let it be writable if it is on a boundary of\n * _minor_ erase size though */\n\nAllow a uniform erase region spi-nor device to be configured\nto use the non-uniform erase regions code path for an erase with:\nCONFIG_MTD_SPI_NOR_USE_VARIABLE_ERASE=y\n\nOn supporting hardware (SECT_4K: majority of current SPI-NOR device)\nprovide the facility for an erase to use the least number\nof SPI-NOR operations, as well as access to 4K erase without\nrequiring CONFIG_MTD_SPI_NOR_USE_4K_SECTORS\n\nIntroduce erasesize_minor to the mtd struct,\nthe smallest erasesize supported by the device\n\nOn existing devices, this is useful where write support is wanted\nfor data on a 4K partition, such as some u-boot-env partitions,\nor RouterBoot soft_config, while still netting the performance\nbenefits of using 64K sectors\n\nPerformance:\ntime mtd erase firmware\nOpenWrt 5.10 ramips MT7621 w25q128jv 0xfc0000 partition length\n\nWithout this patch\nMTD_SPI_NOR_USE_4K_SECTORS=y\t|n\nreal    2m 11.66s\t\t|0m 50.86s\nuser    0m 0.00s\t\t|0m 0.00s\nsys     1m 56.20s\t\t|0m 50.80s\n\nWith this patch\nMTD_SPI_NOR_USE_VARIABLE_ERASE=n|y\t\t|4K_SECTORS=y\nreal    0m 51.68s\t\t|0m 50.85s\t|2m 12.89s\nuser    0m 0.00s\t\t|0m 0.00s\t|0m 0.01s\nsys     0m 46.94s\t\t|0m 50.38s\t|2m 12.46s\n\nSigned-off-by: John Thomson <git@johnthomson.fastmail.com.au>\n---\nHave not tested on variable erase regions device.\n\ncheckpatch does not like the printk(KERN_WARNING\nthese should be changed separately beforehand?\n\nChanges RFC -> v1:\nFix uninitialized variable smatch warning\nReported-by: kernel test robot <lkp@intel.com>\nReported-by: Dan Carpenter <dan.carpenter@oracle.com>\n---\n drivers/mtd/mtdpart.c       | 52 ++++++++++++++++++++++++++++---------\n drivers/mtd/spi-nor/Kconfig | 10 +++++++\n drivers/mtd/spi-nor/core.c  | 10 +++++--\n include/linux/mtd/mtd.h     |  2 ++\n 4 files changed, 60 insertions(+), 14 deletions(-)\n\n--- a/drivers/mtd/mtdpart.c\n+++ b/drivers/mtd/mtdpart.c\n@@ -40,10 +40,11 @@ static struct mtd_info *allocate_partiti\n \tstruct mtd_info *master = mtd_get_master(parent);\n \tint wr_alignment = (parent->flags & MTD_NO_ERASE) ?\n \t\t\t   master->writesize : master->erasesize;\n+\tint wr_alignment_minor = 0;\n \tu64 parent_size = mtd_is_partition(parent) ?\n \t\t\t  parent->part.size : parent->size;\n \tstruct mtd_info *child;\n-\tu32 remainder;\n+\tu32 remainder, remainder_minor;\n \tchar *name;\n \tu64 tmp;\n \n@@ -145,6 +146,7 @@ static struct mtd_info *allocate_partiti\n \t\tint i, max = parent->numeraseregions;\n \t\tu64 end = child->part.offset + child->part.size;\n \t\tstruct mtd_erase_region_info *regions = parent->eraseregions;\n+\t\tuint32_t erasesize_minor = child->erasesize;\n \n \t\t/* Find the first erase regions which is part of this\n \t\t * partition. */\n@@ -155,15 +157,24 @@ static struct mtd_info *allocate_partiti\n \t\tif (i > 0)\n \t\t\ti--;\n \n-\t\t/* Pick biggest erasesize */\n \t\tfor (; i < max && regions[i].offset < end; i++) {\n+\t\t\t/* Pick biggest erasesize */\n \t\t\tif (child->erasesize < regions[i].erasesize)\n \t\t\t\tchild->erasesize = regions[i].erasesize;\n+\t\t\t/* Pick smallest non-zero erasesize */\n+\t\t\tif ((erasesize_minor > regions[i].erasesize) && (regions[i].erasesize > 0))\n+\t\t\t\terasesize_minor = regions[i].erasesize;\n \t\t}\n+\n+\t\tif (erasesize_minor < child->erasesize)\n+\t\t\tchild->erasesize_minor = erasesize_minor;\n+\n \t\tBUG_ON(child->erasesize == 0);\n \t} else {\n \t\t/* Single erase size */\n \t\tchild->erasesize = master->erasesize;\n+\t\tif (master->erasesize_minor)\n+\t\t\tchild->erasesize_minor = master->erasesize_minor;\n \t}\n \n \t/*\n@@ -171,26 +182,43 @@ static struct mtd_info *allocate_partiti\n \t * exposes several regions with different erasesize. Adjust\n \t * wr_alignment accordingly.\n \t */\n-\tif (!(child->flags & MTD_NO_ERASE))\n+\tif (!(child->flags & MTD_NO_ERASE)) {\n \t\twr_alignment = child->erasesize;\n+\t\tif (IS_ENABLED(CONFIG_MTD_SPI_NOR_USE_VARIABLE_ERASE) && child->erasesize_minor)\n+\t\t\twr_alignment_minor = child->erasesize_minor;\n+\t}\n \n \ttmp = mtd_get_master_ofs(child, 0);\n \tremainder = do_div(tmp, wr_alignment);\n \tif ((child->flags & MTD_WRITEABLE) && remainder) {\n-\t\t/* Doesn't start on a boundary of major erase size */\n-\t\t/* FIXME: Let it be writable if it is on a boundary of\n-\t\t * _minor_ erase size though */\n-\t\tchild->flags &= ~MTD_WRITEABLE;\n-\t\tprintk(KERN_WARNING\"mtd: partition \\\"%s\\\" doesn't start on an erase/write block boundary -- force read-only\\n\",\n-\t\t\tpart->name);\n+\t\tif (wr_alignment_minor) {\n+\t\t\ttmp = mtd_get_master_ofs(child, 0);\n+\t\t\tremainder_minor = do_div(tmp, wr_alignment_minor);\n+\t\t\tif (remainder_minor == 0)\n+\t\t\t\tchild->erasesize = child->erasesize_minor;\n+\t\t}\n+\n+\t\tif ((!wr_alignment_minor) || (wr_alignment_minor && remainder_minor != 0)) {\n+\t\t\tchild->flags &= ~MTD_WRITEABLE;\n+\t\t\tprintk(KERN_WARNING\"mtd: partition \\\"%s\\\" doesn't start on an erase/write block boundary -- force read-only\\n\",\n+\t\t\t\tpart->name);\n+\t\t}\n \t}\n \n \ttmp = mtd_get_master_ofs(child, 0) + child->part.size;\n \tremainder = do_div(tmp, wr_alignment);\n \tif ((child->flags & MTD_WRITEABLE) && remainder) {\n-\t\tchild->flags &= ~MTD_WRITEABLE;\n-\t\tprintk(KERN_WARNING\"mtd: partition \\\"%s\\\" doesn't end on an erase/write block -- force read-only\\n\",\n-\t\t\tpart->name);\n+\t\tif (wr_alignment_minor) {\n+\t\t\ttmp = mtd_get_master_ofs(child, 0) + child->part.size;\n+\t\t\tremainder_minor = do_div(tmp, wr_alignment_minor);\n+\t\t\tif (remainder_minor == 0)\n+\t\t\t\tchild->erasesize = child->erasesize_minor;\n+\t\t}\n+\t\tif ((!wr_alignment_minor) || (wr_alignment_minor && remainder_minor != 0)) {\n+\t\t\tchild->flags &= ~MTD_WRITEABLE;\n+\t\t\tprintk(KERN_WARNING\"mtd: partition \\\"%s\\\" doesn't end on an erase/write block -- force read-only\\n\",\n+\t\t\t\tpart->name);\n+\t\t}\n \t}\n \n \tchild->size = child->part.size;\n--- a/drivers/mtd/spi-nor/Kconfig\n+++ b/drivers/mtd/spi-nor/Kconfig\n@@ -10,6 +10,16 @@ menuconfig MTD_SPI_NOR\n \n if MTD_SPI_NOR\n \n+config MTD_SPI_NOR_USE_VARIABLE_ERASE\n+\tbool \"Disable uniform_erase to allow use of all hardware supported erasesizes\"\n+\tdepends on !MTD_SPI_NOR_USE_4K_SECTORS\n+\tdefault n\n+\thelp\n+\t  Allow mixed use of all hardware supported erasesizes,\n+\t  by forcing spi_nor to use the multiple eraseregions code path.\n+\t  For example: A 68K erase will use one 64K erase, and one 4K erase\n+\t  on supporting hardware.\n+\n config MTD_SPI_NOR_USE_4K_SECTORS\n \tbool \"Use small 4096 B erase sectors\"\n \tdefault y\n--- a/drivers/mtd/spi-nor/core.c\n+++ b/drivers/mtd/spi-nor/core.c\n@@ -1075,6 +1075,8 @@ static u8 spi_nor_convert_3to4_erase(u8\n \n static bool spi_nor_has_uniform_erase(const struct spi_nor *nor)\n {\n+\tif (IS_ENABLED(CONFIG_MTD_SPI_NOR_USE_VARIABLE_ERASE))\n+\t\treturn false;\n \treturn !!nor->params->erase_map.uniform_erase_type;\n }\n \n@@ -2560,6 +2562,7 @@ static int spi_nor_select_erase(struct s\n {\n \tstruct spi_nor_erase_map *map = &nor->params->erase_map;\n \tconst struct spi_nor_erase_type *erase = NULL;\n+\tconst struct spi_nor_erase_type *erase_minor = NULL;\n \tstruct mtd_info *mtd = &nor->mtd;\n \tu32 wanted_size = nor->info->sector_size;\n \tint i;\n@@ -2592,8 +2595,9 @@ static int spi_nor_select_erase(struct s\n \t */\n \tfor (i = SNOR_ERASE_TYPE_MAX - 1; i >= 0; i--) {\n \t\tif (map->erase_type[i].size) {\n-\t\t\terase = &map->erase_type[i];\n-\t\t\tbreak;\n+\t\t\tif (!erase)\n+\t\t\t\terase = &map->erase_type[i];\n+\t\t\terase_minor = &map->erase_type[i];\n \t\t}\n \t}\n \n@@ -2601,6 +2605,8 @@ static int spi_nor_select_erase(struct s\n \t\treturn -EINVAL;\n \n \tmtd->erasesize = erase->size;\n+\tif (erase_minor && erase_minor->size < erase->size)\n+\t\tmtd->erasesize_minor = erase_minor->size;\n \treturn 0;\n }\n \n--- a/include/linux/mtd/mtd.h\n+++ b/include/linux/mtd/mtd.h\n@@ -242,6 +242,8 @@ struct mtd_info {\n \t * information below if they desire\n \t */\n \tuint32_t erasesize;\n+\t/* \"Minor\" (smallest) erase size supported by the whole device */\n+\tuint32_t erasesize_minor;\n \t/* Minimal writable flash unit size. In case of NOR flash it is 1 (even\n \t * though individual bits can be cleared), in case of NAND flash it is\n \t * one NAND page (or half, or one-fourths of it), in case of ECC-ed NOR\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/410-mtd-parsers-ofpart-fix-parsing-subpartitions.patch",
    "content": "From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nDate: Thu, 6 May 2021 12:33:58 +0200\nSubject: [PATCH] mtd: parsers: ofpart: fix parsing subpartitions\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nofpart was recently patched to not scan random partition nodes as\nsubpartitions. That change unfortunately broke scanning valid\nsubpartitions like:\n\npartitions {\n\tcompatible = \"fixed-partitions\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tpartition@0 {\n\t\tcompatible = \"fixed-partitions\";\n\t\tlabel = \"bootloader\";\n\t\treg = <0x0 0x100000>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"config\";\n\t\t\treg = <0x80000 0x80000>;\n\t\t};\n\t};\n};\n\nFix that regression by adding 1 more code path. We actually need 3\nconditional blocks to support 3 possible cases. This change also makes\ncode easier to understand & follow.\n\nReported-by: David Bauer <mail@david-bauer.net>\nFixes: 2d751203aacf (\"mtd: parsers: ofpart: limit parsing of deprecated DT syntax\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\n---\n drivers/mtd/parsers/ofpart_core.c | 26 ++++++++++++++------------\n 1 file changed, 14 insertions(+), 12 deletions(-)\n\n--- a/drivers/mtd/parsers/ofpart_core.c\n+++ b/drivers/mtd/parsers/ofpart_core.c\n@@ -57,20 +57,22 @@ static int parse_fixed_partitions(struct\n \tif (!mtd_node)\n \t\treturn 0;\n \n-\tofpart_node = of_get_child_by_name(mtd_node, \"partitions\");\n-\tif (!ofpart_node && !master->parent) {\n-\t\t/*\n-\t\t * We might get here even when ofpart isn't used at all (e.g.,\n-\t\t * when using another parser), so don't be louder than\n-\t\t * KERN_DEBUG\n-\t\t */\n-\t\tpr_debug(\"%s: 'partitions' subnode not found on %pOF. Trying to parse direct subnodes as partitions.\\n\",\n-\t\t\t master->name, mtd_node);\n+\tif (!master->parent) { /* Master */\n+\t\tofpart_node = of_get_child_by_name(mtd_node, \"partitions\");\n+\t\tif (!ofpart_node) {\n+\t\t\t/*\n+\t\t\t * We might get here even when ofpart isn't used at all (e.g.,\n+\t\t\t * when using another parser), so don't be louder than\n+\t\t\t * KERN_DEBUG\n+\t\t\t */\n+\t\t\tpr_debug(\"%s: 'partitions' subnode not found on %pOF. Trying to parse direct subnodes as partitions.\\n\",\n+\t\t\t\tmaster->name, mtd_node);\n+\t\t\tofpart_node = mtd_node;\n+\t\t\tdedicated = false;\n+\t\t}\n+\t} else { /* Partition */\n \t\tofpart_node = mtd_node;\n-\t\tdedicated = false;\n \t}\n-\tif (!ofpart_node)\n-\t\treturn 0;\n \n \tof_id = of_match_node(parse_ofpart_match_table, ofpart_node);\n \tif (dedicated && !of_id) {\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/419-mtd-redboot-add-of_match_table-with-DT-binding.patch",
    "content": "From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nSubject: [PATCH] mtd: redboot: add of_match_table with DT binding\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nThis allows parsing RedBoot compatible partitions for properly described\nflash device in DT.\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\n---\n\n--- a/drivers/mtd/parsers/redboot.c\n+++ b/drivers/mtd/parsers/redboot.c\n@@ -305,6 +305,7 @@ static int parse_redboot_partitions(stru\n \n static const struct of_device_id mtd_parser_redboot_of_match_table[] = {\n \t{ .compatible = \"redboot-fis\" },\n+\t{ .compatible = \"ecoscentric,redboot-fis-partitions\" },\n \t{},\n };\n MODULE_DEVICE_TABLE(of, mtd_parser_redboot_of_match_table);\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/420-mtd-redboot_space.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nSubject: add patch for including unpartitioned space in the rootfs partition for redboot devices (if applicable)\n\n[john@phrozen.org: used by ixp and others]\n\nlede-commit: 394918851f84e4d00fa16eb900e7700e95091f00\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n drivers/mtd/redboot.c | 19 +++++++++++++------\n 1 file changed, 13 insertions(+), 6 deletions(-)\n\n--- a/drivers/mtd/parsers/redboot.c\n+++ b/drivers/mtd/parsers/redboot.c\n@@ -279,14 +279,21 @@ static int parse_redboot_partitions(stru\n #endif\n \t\tnames += strlen(names)+1;\n \n-#ifdef CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED\n \t\tif(fl->next && fl->img->flash_base + fl->img->size + master->erasesize <= fl->next->img->flash_base) {\n-\t\t\ti++;\n-\t\t\tparts[i].offset = parts[i-1].size + parts[i-1].offset;\n-\t\t\tparts[i].size = fl->next->img->flash_base - parts[i].offset;\n-\t\t\tparts[i].name = nullname;\n-\t\t}\n+\t\t\tif (!strcmp(parts[i].name, \"rootfs\")) {\n+\t\t\t\tparts[i].size = fl->next->img->flash_base;\n+\t\t\t\tparts[i].size &= ~(master->erasesize - 1);\n+\t\t\t\tparts[i].size -= parts[i].offset;\n+#ifdef CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED\n+\t\t\t\tnrparts--;\n+\t\t\t} else {\n+\t\t\t\ti++;\n+\t\t\t\tparts[i].offset = parts[i-1].size + parts[i-1].offset;\n+\t\t\t\tparts[i].size = fl->next->img->flash_base - parts[i].offset;\n+\t\t\t\tparts[i].name = nullname;\n #endif\n+\t\t\t}\n+\t\t}\n \t\ttmp_fl = fl;\n \t\tfl = fl->next;\n \t\tkfree(tmp_fl);\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/430-mtd-add-myloader-partition-parser.patch",
    "content": "From: Florian Fainelli <f.fainelli@gmail.com>\nSubject: Add myloader partition table parser\n\n[john@phozen.org: shoud be upstreamable]\n\nlede-commit: d8bf22859b51faa09d22c056fe221a45d2f7a3b8\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n[adjust for kernel 5.4, add myloader.c to patch]\nSigned-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>\n\n--- a/drivers/mtd/parsers/Kconfig\n+++ b/drivers/mtd/parsers/Kconfig\n@@ -57,6 +57,22 @@ config MTD_CMDLINE_PARTS\n \n \t  If unsure, say 'N'.\n \n+config MTD_MYLOADER_PARTS\n+\ttristate \"MyLoader partition parsing\"\n+\tdepends on ADM5120 || ATH25 || ATH79\n+\thelp\n+\t  MyLoader is a bootloader which allows the user to define partitions\n+\t  in flash devices, by putting a table in the second erase block\n+\t  on the device, similar to a partition table. This table gives the \n+\t  offsets and lengths of the user defined partitions.\n+\n+\t  If you need code which can detect and parse these tables, and\n+\t  register MTD 'partitions' corresponding to each image detected,\n+\t  enable this option.\n+\n+\t  You will still need the parsing functions to be called by the driver\n+\t  for your particular device. It won't happen automatically.\n+\n config MTD_OF_PARTS\n \ttristate \"OpenFirmware (device tree) partitioning parser\"\n \tdefault y\n--- a/drivers/mtd/parsers/Makefile\n+++ b/drivers/mtd/parsers/Makefile\n@@ -3,6 +3,7 @@ obj-$(CONFIG_MTD_AR7_PARTS)\t\t+= ar7part.\n obj-$(CONFIG_MTD_BCM47XX_PARTS)\t\t+= bcm47xxpart.o\n obj-$(CONFIG_MTD_BCM63XX_PARTS)\t\t+= bcm63xxpart.o\n obj-$(CONFIG_MTD_CMDLINE_PARTS)\t\t+= cmdlinepart.o\n+obj-$(CONFIG_MTD_MYLOADER_PARTS)\t\t+= myloader.o\n obj-$(CONFIG_MTD_OF_PARTS)\t\t+= ofpart.o\n ofpart-y\t\t\t\t+= ofpart_core.o\n ofpart-$(CONFIG_MTD_OF_PARTS_BCM4908)\t+= ofpart_bcm4908.o\n--- /dev/null\n+++ b/drivers/mtd/parsers/myloader.c\n@@ -0,0 +1,181 @@\n+/*\n+ *  Parse MyLoader-style flash partition tables and produce a Linux partition\n+ *  array to match.\n+ *\n+ *  Copyright (C) 2007-2009 Gabor Juhos <juhosg@openwrt.org>\n+ *\n+ *  This file was based on drivers/mtd/redboot.c\n+ *  Author: Red Hat, Inc. - David Woodhouse <dwmw2@cambridge.redhat.com>\n+ *\n+ *  This program is free software; you can redistribute it and/or modify it\n+ *  under the terms of the GNU General Public License version 2 as published\n+ *  by the Free Software Foundation.\n+ */\n+\n+#include <linux/kernel.h>\n+#include <linux/module.h>\n+#include <linux/version.h>\n+#include <linux/slab.h>\n+#include <linux/init.h>\n+#include <linux/vmalloc.h>\n+#include <linux/mtd/mtd.h>\n+#include <linux/mtd/partitions.h>\n+#include <linux/byteorder/generic.h>\n+#include <linux/myloader.h>\n+\n+#define BLOCK_LEN_MIN\t\t0x10000\n+#define PART_NAME_LEN\t\t32\n+\n+struct part_data {\n+\tstruct mylo_partition_table\ttab;\n+\tchar names[MYLO_MAX_PARTITIONS][PART_NAME_LEN];\n+};\n+\n+static int myloader_parse_partitions(struct mtd_info *master,\n+\t\t\t\t     const struct mtd_partition **pparts,\n+\t\t\t\t     struct mtd_part_parser_data *data)\n+{\n+\tstruct part_data *buf;\n+\tstruct mylo_partition_table *tab;\n+\tstruct mylo_partition *part;\n+\tstruct mtd_partition *mtd_parts;\n+\tstruct mtd_partition *mtd_part;\n+\tint num_parts;\n+\tint ret, i;\n+\tsize_t retlen;\n+\tchar *names;\n+\tunsigned long offset;\n+\tunsigned long blocklen;\n+\n+\tbuf = vmalloc(sizeof(*buf));\n+\tif (!buf) {\n+\t\treturn -ENOMEM;\n+\t\tgoto out;\n+\t}\n+\ttab = &buf->tab;\n+\n+\tblocklen = master->erasesize;\n+\tif (blocklen < BLOCK_LEN_MIN)\n+\t\tblocklen = BLOCK_LEN_MIN;\n+\n+\toffset = blocklen;\n+\n+\t/* Find the partition table */\n+\tfor (i = 0; i < 4; i++, offset += blocklen) {\n+\t\tprintk(KERN_DEBUG \"%s: searching for MyLoader partition table\"\n+\t\t\t\t\" at offset 0x%lx\\n\", master->name, offset);\n+\n+\t\tret = mtd_read(master, offset, sizeof(*buf), &retlen,\n+\t\t\t       (void *)buf);\n+\t\tif (ret)\n+\t\t\tgoto out_free_buf;\n+\n+\t\tif (retlen != sizeof(*buf)) {\n+\t\t\tret = -EIO;\n+\t\t\tgoto out_free_buf;\n+\t\t}\n+\n+\t\t/* Check for Partition Table magic number */\n+\t\tif (tab->magic == le32_to_cpu(MYLO_MAGIC_PARTITIONS))\n+\t\t\tbreak;\n+\n+\t}\n+\n+\tif (tab->magic != le32_to_cpu(MYLO_MAGIC_PARTITIONS)) {\n+\t\tprintk(KERN_DEBUG \"%s: no MyLoader partition table found\\n\",\n+\t\t\tmaster->name);\n+\t\tret = 0;\n+\t\tgoto out_free_buf;\n+\t}\n+\n+\t/* The MyLoader and the Partition Table is always present */\n+\tnum_parts = 2;\n+\n+\t/* Detect number of used partitions */\n+\tfor (i = 0; i < MYLO_MAX_PARTITIONS; i++) {\n+\t\tpart = &tab->partitions[i];\n+\n+\t\tif (le16_to_cpu(part->type) == PARTITION_TYPE_FREE)\n+\t\t\tcontinue;\n+\n+\t\tnum_parts++;\n+\t}\n+\n+\tmtd_parts = kzalloc((num_parts * sizeof(*mtd_part) +\n+\t\t\t\tnum_parts * PART_NAME_LEN), GFP_KERNEL);\n+\n+\tif (!mtd_parts) {\n+\t\tret = -ENOMEM;\n+\t\tgoto out_free_buf;\n+\t}\n+\n+\tmtd_part = mtd_parts;\n+\tnames = (char *)&mtd_parts[num_parts];\n+\n+\tstrncpy(names, \"myloader\", PART_NAME_LEN);\n+\tmtd_part->name = names;\n+\tmtd_part->offset = 0;\n+\tmtd_part->size = offset;\n+\tmtd_part->mask_flags = MTD_WRITEABLE;\n+\tmtd_part++;\n+\tnames += PART_NAME_LEN;\n+\n+\tstrncpy(names, \"partition_table\", PART_NAME_LEN);\n+\tmtd_part->name = names;\n+\tmtd_part->offset = offset;\n+\tmtd_part->size = blocklen;\n+\tmtd_part->mask_flags = MTD_WRITEABLE;\n+\tmtd_part++;\n+\tnames += PART_NAME_LEN;\n+\n+\tfor (i = 0; i < MYLO_MAX_PARTITIONS; i++) {\n+\t\tpart = &tab->partitions[i];\n+\n+\t\tif (le16_to_cpu(part->type) == PARTITION_TYPE_FREE)\n+\t\t\tcontinue;\n+\n+\t\tif ((buf->names[i][0]) && (buf->names[i][0] != '\\xff'))\n+\t\t\tstrncpy(names, buf->names[i], PART_NAME_LEN);\n+\t\telse\n+\t\t\tsnprintf(names, PART_NAME_LEN, \"partition%d\", i);\n+\n+\t\tmtd_part->offset = le32_to_cpu(part->addr);\n+\t\tmtd_part->size = le32_to_cpu(part->size);\n+\t\tmtd_part->name = names;\n+\t\tmtd_part++;\n+\t\tnames += PART_NAME_LEN;\n+\t}\n+\n+\t*pparts = mtd_parts;\n+\tret = num_parts;\n+\n+ out_free_buf:\n+\tvfree(buf);\n+ out:\n+\treturn ret;\n+}\n+\n+static struct mtd_part_parser myloader_mtd_parser = {\n+\t.owner\t\t= THIS_MODULE,\n+\t.parse_fn\t= myloader_parse_partitions,\n+\t.name\t\t= \"MyLoader\",\n+};\n+\n+static int __init myloader_mtd_parser_init(void)\n+{\n+\tregister_mtd_parser(&myloader_mtd_parser);\n+\n+\treturn 0;\n+}\n+\n+static void __exit myloader_mtd_parser_exit(void)\n+{\n+\tderegister_mtd_parser(&myloader_mtd_parser);\n+}\n+\n+module_init(myloader_mtd_parser_init);\n+module_exit(myloader_mtd_parser_exit);\n+\n+MODULE_AUTHOR(\"Gabor Juhos <juhosg@openwrt.org>\");\n+MODULE_DESCRIPTION(\"Parsing code for MyLoader partition tables\");\n+MODULE_LICENSE(\"GPL v2\");\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/431-mtd-bcm47xxpart-check-for-bad-blocks-when-calculatin.patch",
    "content": "From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <zajec5@gmail.com>\nSubject: [PATCH] mtd: bcm47xxpart: check for bad blocks when calculating offsets\n\nSigned-off-by: Rafał Miłecki <zajec5@gmail.com>\n---\n\n--- a/drivers/mtd/parsers/parser_trx.c\n+++ b/drivers/mtd/parsers/parser_trx.c\n@@ -25,6 +25,33 @@ struct trx_header {\n \tuint32_t offset[3];\n } __packed;\n \n+/*\n+ * Calculate real end offset (address) for a given amount of data. It checks\n+ * all blocks skipping bad ones.\n+ */\n+static size_t parser_trx_real_offset(struct mtd_info *mtd, size_t bytes)\n+{\n+\tsize_t real_offset = 0;\n+\n+\tif (mtd_block_isbad(mtd, real_offset))\n+\t\tpr_warn(\"Base offset shouldn't be at bad block\");\n+\n+\twhile (bytes >= mtd->erasesize) {\n+\t\tbytes -= mtd->erasesize;\n+\t\treal_offset += mtd->erasesize;\n+\t\twhile (mtd_block_isbad(mtd, real_offset)) {\n+\t\t\treal_offset += mtd->erasesize;\n+\n+\t\t\tif (real_offset >= mtd->size)\n+\t\t\t\treturn real_offset - mtd->erasesize;\n+\t\t}\n+\t}\n+\n+\treal_offset += bytes;\n+\n+\treturn real_offset;\n+}\n+\n static const char *parser_trx_data_part_name(struct mtd_info *master,\n \t\t\t\t\t     size_t offset)\n {\n@@ -86,21 +113,21 @@ static int parser_trx_parse(struct mtd_i\n \tif (trx.offset[2]) {\n \t\tpart = &parts[curr_part++];\n \t\tpart->name = \"loader\";\n-\t\tpart->offset = trx.offset[i];\n+\t\tpart->offset = parser_trx_real_offset(mtd, trx.offset[i]);\n \t\ti++;\n \t}\n \n \tif (trx.offset[i]) {\n \t\tpart = &parts[curr_part++];\n \t\tpart->name = \"linux\";\n-\t\tpart->offset = trx.offset[i];\n+\t\tpart->offset = parser_trx_real_offset(mtd, trx.offset[i]);\n \t\ti++;\n \t}\n \n \tif (trx.offset[i]) {\n \t\tpart = &parts[curr_part++];\n-\t\tpart->name = parser_trx_data_part_name(mtd, trx.offset[i]);\n-\t\tpart->offset = trx.offset[i];\n+\t\tpart->offset = parser_trx_real_offset(mtd, trx.offset[i]);\n+\t\tpart->name = parser_trx_data_part_name(mtd, part->offset);\n \t\ti++;\n \t}\n \n"
  },
  {
    "path": "target/linux/generic/pending-5.10/432-mtd-bcm47xxpart-detect-T_Meter-partition.patch",
    "content": "From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <zajec5@gmail.com>\nSubject: mtd: bcm47xxpart: detect T_Meter partition\n\nIt can be found on many Netgear devices. It consists of many 0x30 blocks\nstarting with 4D 54.\n\nSigned-off-by: Rafał Miłecki <zajec5@gmail.com>\n---\n drivers/mtd/bcm47xxpart.c | 10 ++++++++++\n 1 file changed, 10 insertions(+)\n\n--- a/drivers/mtd/parsers/bcm47xxpart.c\n+++ b/drivers/mtd/parsers/bcm47xxpart.c\n@@ -35,6 +35,7 @@\n #define NVRAM_HEADER\t\t\t0x48534C46\t/* FLSH */\n #define POT_MAGIC1\t\t\t0x54544f50\t/* POTT */\n #define POT_MAGIC2\t\t\t0x504f\t\t/* OP */\n+#define T_METER_MAGIC\t\t\t0x4D540000\t/* MT */\n #define ML_MAGIC1\t\t\t0x39685a42\n #define ML_MAGIC2\t\t\t0x26594131\n #define TRX_MAGIC\t\t\t0x30524448\n@@ -178,6 +179,15 @@ static int bcm47xxpart_parse(struct mtd_\n \t\t\t\t\t     MTD_WRITEABLE);\n \t\t\tcontinue;\n \t\t}\n+\n+\t\t/* T_Meter */\n+\t\tif ((le32_to_cpu(buf[0x000 / 4]) & 0xFFFF0000) == T_METER_MAGIC &&\n+\t\t    (le32_to_cpu(buf[0x030 / 4]) & 0xFFFF0000) == T_METER_MAGIC &&\n+\t\t    (le32_to_cpu(buf[0x060 / 4]) & 0xFFFF0000) == T_METER_MAGIC) {\n+\t\t\tbcm47xxpart_add_part(&parts[curr_part++], \"T_Meter\", offset,\n+\t\t\t\t\t     MTD_WRITEABLE);\n+\t\t\tcontinue;\n+\t\t}\n \n \t\t/* TRX */\n \t\tif (buf[0x000 / 4] == TRX_MAGIC) {\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/435-mtd-add-routerbootpart-parser-config.patch",
    "content": "From 4437e01fb6bca63fccdba5d6c44888b0935885c2 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Thibaut=20VAR=C3=88NE?= <hacks@slashdirt.org>\nDate: Tue, 24 Mar 2020 11:45:07 +0100\nSubject: [PATCH] generic: routerboot partition build bits (5.4)\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nThis patch adds routerbootpart kernel build bits\n\nSigned-off-by: Thibaut VARÈNE <hacks@slashdirt.org>\n---\n drivers/mtd/parsers/Kconfig  | 9 +++++++++\n drivers/mtd/parsers/Makefile | 1 +\n 2 files changed, 10 insertions(+)\n\n--- a/drivers/mtd/parsers/Kconfig\n+++ b/drivers/mtd/parsers/Kconfig\n@@ -195,3 +195,12 @@ config MTD_REDBOOT_PARTS_READONLY\n \t  'FIS directory' images, enable this option.\n \n endif # MTD_REDBOOT_PARTS\n+\n+config MTD_ROUTERBOOT_PARTS\n+\ttristate \"RouterBoot flash partition parser\"\n+\tdepends on MTD && OF\n+\thelp\n+\t MikroTik RouterBoot is implemented as a multi segment system on the\n+\t flash, some of which are fixed and some of which are located at\n+\t variable offsets. This parser handles both cases via properly\n+\t formatted DTS.\n--- a/drivers/mtd/parsers/Makefile\n+++ b/drivers/mtd/parsers/Makefile\n@@ -13,3 +13,4 @@ obj-$(CONFIG_MTD_AFS_PARTS)\t\t+= afs.o\n obj-$(CONFIG_MTD_PARSER_TRX)\t\t+= parser_trx.o\n obj-$(CONFIG_MTD_SHARPSL_PARTS)\t\t+= sharpslpart.o\n obj-$(CONFIG_MTD_REDBOOT_PARTS)\t\t+= redboot.o\n+obj-$(CONFIG_MTD_ROUTERBOOT_PARTS)\t\t+= routerbootpart.o\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/444-mtd-nand-rawnand-add-support-for-Toshiba-TC58NVG0S3H.patch",
    "content": "From 35ca7e3e6ccd120d694a3425f37fc6374ad2e11e Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Andreas=20B=C3=B6hler?= <dev@aboehler.at>\nDate: Wed, 20 Apr 2022 12:08:38 +0200\nSubject: [PATCH] mtd: rawnand: add support for Toshiba TC58NVG0S3HTA00\n NAND flash\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nThe Toshiba TC58NVG0S3HTA00 is detected with 64 byte OOB while the flash\nhas 128 bytes OOB. This adds a static NAND ID entry to correct this.\n\nTested on FRITZ!Box 7530 flashed with OpenWrt.\n\nSigned-off-by: Andreas Böhler <dev@aboehler.at>\n---\n drivers/mtd/nand/raw/nand_ids.c | 3 +++\n 1 file changed, 3 insertions(+)\n\ndiff --git a/drivers/mtd/nand/raw/nand_ids.c b/drivers/mtd/nand/raw/nand_ids.c\nindex 6e41902be35f..d64adbd1ce6b 100644\n--- a/drivers/mtd/nand/raw/nand_ids.c\n+++ b/drivers/mtd/nand/raw/nand_ids.c\n@@ -29,6 +29,9 @@ struct nand_flash_dev nand_flash_ids[] = {\n \t{\"TC58NVG0S3E 1G 3.3V 8-bit\",\n \t\t{ .id = {0x98, 0xd1, 0x90, 0x15, 0x76, 0x14, 0x01, 0x00} },\n \t\t  SZ_2K, SZ_128, SZ_128K, 0, 8, 64, NAND_ECC_INFO(1, SZ_512), },\n+\t{\"TC58NVG0S3HTA00 1G 3.3V 8-bit\",\n+\t\t{ .id = {0x98, 0xf1, 0x80, 0x15} },\n+\t\t  SZ_2K, SZ_128, SZ_128K, 0, 4, 128, NAND_ECC_INFO(8, SZ_512), },\n \t{\"TC58NVG2S0F 4G 3.3V 8-bit\",\n \t\t{ .id = {0x98, 0xdc, 0x90, 0x26, 0x76, 0x15, 0x01, 0x08} },\n \t\t  SZ_4K, SZ_512, SZ_256K, 0, 8, 224, NAND_ECC_INFO(4, SZ_512) },\n-- \n2.35.1\n\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/460-mtd-cfi_cmdset_0002-no-erase_suspend.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nSubject: kernel: disable cfi cmdset 0002 erase suspend\n\non some platforms, erase suspend leads to data corruption and lockups when write\nops collide with erase ops. this has been observed on the buffalo wzr-hp-g300nh.\nrather than play whack-a-mole with a hard to reproduce issue on a variety of devices,\nsimply disable erase suspend, as it will usually not produce any useful gain on\nthe small filesystems used on embedded hardware.\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n drivers/mtd/chips/cfi_cmdset_0002.c | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/drivers/mtd/chips/cfi_cmdset_0002.c\n+++ b/drivers/mtd/chips/cfi_cmdset_0002.c\n@@ -913,7 +913,7 @@ static int get_chip(struct map_info *map\n \t\treturn 0;\n \n \tcase FL_ERASING:\n-\t\tif (!cfip || !(cfip->EraseSuspend & (0x1|0x2)) ||\n+\t\tif (1 /* no suspend */ || !cfip || !(cfip->EraseSuspend & (0x1|0x2)) ||\n \t\t    !(mode == FL_READY || mode == FL_POINT ||\n \t\t    (mode == FL_WRITING && (cfip->EraseSuspend & 0x2))))\n \t\t\tgoto sleep;\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/461-mtd-cfi_cmdset_0002-add-buffer-write-cmd-timeout.patch",
    "content": "From: George Kashperko <george@znau.edu.ua>\nSubject: Issue map read after Write Buffer Load command to ensure chip is ready to receive data.\n\nSigned-off-by: George Kashperko <george@znau.edu.ua>\n---\n drivers/mtd/chips/cfi_cmdset_0002.c |    1 +\n 1 file changed, 1 insertion(+)\n--- a/drivers/mtd/chips/cfi_cmdset_0002.c\n+++ b/drivers/mtd/chips/cfi_cmdset_0002.c\n@@ -2057,6 +2057,7 @@ static int __xipram do_write_buffer(stru\n \n \t/* Write Buffer Load */\n \tmap_write(map, CMD(0x25), cmd_adr);\n+\t(void) map_read(map, cmd_adr);\n \n \tchip->state = FL_WRITING_TO_BUFFER;\n \n"
  },
  {
    "path": "target/linux/generic/pending-5.10/465-m25p80-mx-disable-software-protection.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nSubject: Disable software protection bits for Macronix flashes.\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n drivers/mtd/spi-nor/spi-nor.c | 1 +\n 1 file changed, 1 insertion(+)\n\n--- a/drivers/mtd/spi-nor/macronix.c\n+++ b/drivers/mtd/spi-nor/macronix.c\n@@ -93,6 +93,7 @@ static void macronix_default_init(struct\n {\n \tnor->params->quad_enable = spi_nor_sr1_bit6_quad_enable;\n \tnor->params->set_4byte_addr_mode = spi_nor_set_4byte_addr_mode;\n+\tnor->flags |= SNOR_F_HAS_LOCK;\n }\n \n static const struct spi_nor_fixups macronix_fixups = {\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/470-mtd-spi-nor-support-limiting-4K-sectors-support-base.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nDate: Sat, 4 Nov 2017 07:40:23 +0100\nSubject: [PATCH] mtd: spi-nor: support limiting 4K sectors support based on\n flash size\n\nSome devices need 4K sectors to be able to deal with small flash chips.\nFor instance, w25x05 is 64 KiB in size, and without 4K sectors, the\nentire chip is just one erase block.\nOn bigger flash chip sizes, using 4K sectors can significantly slow down\nmany operations, including using a writable filesystem. There are several\nplatforms where it makes sense to use a single kernel on both kinds of\ndevices.\n\nTo support this properly, allow configuring an upper flash chip size\nlimit for 4K sectors support.\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n\n--- a/drivers/mtd/spi-nor/Kconfig\n+++ b/drivers/mtd/spi-nor/Kconfig\n@@ -34,6 +34,17 @@ config MTD_SPI_NOR_USE_4K_SECTORS\n \t  Please note that some tools/drivers/filesystems may not work with\n \t  4096 B erase size (e.g. UBIFS requires 15 KiB as a minimum).\n \n+config MTD_SPI_NOR_USE_4K_SECTORS_LIMIT\n+\tint \"Maximum flash chip size to use 4K sectors on (in KiB)\"\n+\tdepends on MTD_SPI_NOR_USE_4K_SECTORS\n+\tdefault \"4096\"\n+\thelp\n+\t  There are many flash chips that support 4K sectors, but are so large\n+\t  that using them significantly slows down writing large amounts of\n+\t  data or using a writable filesystem.\n+\t  Any flash chip larger than the size specified in this option will\n+\t  not use 4K sectors.\n+\n source \"drivers/mtd/spi-nor/controllers/Kconfig\"\n \n endif # MTD_SPI_NOR\n--- a/drivers/mtd/spi-nor/core.c\n+++ b/drivers/mtd/spi-nor/core.c\n@@ -2792,6 +2792,21 @@ static void spi_nor_info_init_params(str\n \t */\n \terase_mask = 0;\n \ti = 0;\n+#ifdef CONFIG_MTD_SPI_NOR_USE_4K_SECTORS\n+\tif ((info->flags & SECT_4K_PMC) && (params->size <=\n+\t\t   CONFIG_MTD_SPI_NOR_USE_4K_SECTORS_LIMIT * 1024)) {\n+\t\terase_mask |= BIT(i);\n+\t\tspi_nor_set_erase_type(&map->erase_type[i], 4096u,\n+\t\t\t\t       SPINOR_OP_BE_4K_PMC);\n+\t\ti++;\n+\t} else if ((info->flags & SECT_4K) && (params->size <=\n+\t    CONFIG_MTD_SPI_NOR_USE_4K_SECTORS_LIMIT * 1024)) {\n+\t\terase_mask |= BIT(i);\n+\t\tspi_nor_set_erase_type(&map->erase_type[i], 4096u,\n+\t\t\t\t       SPINOR_OP_BE_4K);\n+\t\ti++;\n+\t}\n+#else\n \tif (info->flags & SECT_4K_PMC) {\n \t\terase_mask |= BIT(i);\n \t\tspi_nor_set_erase_type(&map->erase_type[i], 4096u,\n@@ -2803,6 +2818,7 @@ static void spi_nor_info_init_params(str\n \t\t\t\t       SPINOR_OP_BE_4K);\n \t\ti++;\n \t}\n+#endif\n \terase_mask |= BIT(i);\n \tspi_nor_set_erase_type(&map->erase_type[i], info->sector_size,\n \t\t\t       SPINOR_OP_SE);\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/476-mtd-spi-nor-add-eon-en25q128.patch",
    "content": "From: Piotr Dymacz <pepe2k@gmail.com>\nSubject: kernel/mtd: add support for EON EN25Q128\n\nSigned-off-by: Piotr Dymacz <pepe2k@gmail.com>\n---\n drivers/mtd/spi-nor/spi-nor.c | 1 +\n 1 file changed, 1 insertion(+)\n\n--- a/drivers/mtd/spi-nor/eon.c\n+++ b/drivers/mtd/spi-nor/eon.c\n@@ -15,6 +15,7 @@ static const struct flash_info eon_parts\n \t{ \"en25q32b\",   INFO(0x1c3016, 0, 64 * 1024,   64, 0) },\n \t{ \"en25p64\",    INFO(0x1c2017, 0, 64 * 1024,  128, 0) },\n \t{ \"en25q64\",    INFO(0x1c3017, 0, 64 * 1024,  128, SECT_4K) },\n+\t{ \"en25q128\",   INFO(0x1c3018, 0, 64 * 1024,  256, SECT_4K) },\n \t{ \"en25q80a\",   INFO(0x1c3014, 0, 64 * 1024,   16,\n \t\t\t     SECT_4K | SPI_NOR_DUAL_READ) },\n \t{ \"en25qh16\",   INFO(0x1c7015, 0, 64 * 1024,   32,\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/479-mtd-spi-nor-add-xtx-xt25f128b.patch",
    "content": "From patchwork Thu Feb  6 17:19:41 2020\nContent-Type: text/plain; charset=\"utf-8\"\nMIME-Version: 1.0\nContent-Transfer-Encoding: 7bit\nX-Patchwork-Submitter: Daniel Golle <daniel@makrotopia.org>\nX-Patchwork-Id: 1234465\nDate: Thu, 6 Feb 2020 19:19:41 +0200\nFrom: Daniel Golle <daniel@makrotopia.org>\nTo: linux-mtd@lists.infradead.org\nSubject: [PATCH v2] mtd: spi-nor: Add support for xt25f128b chip\nMessage-ID: <20200206171941.GA2398@makrotopia.org>\nMIME-Version: 1.0\nContent-Disposition: inline\nList-Subscribe: <http://lists.infradead.org/mailman/listinfo/linux-mtd>,\n <mailto:linux-mtd-request@lists.infradead.org?subject=subscribe>\nCc: Eitan Cohen <eitan@neot-semadar.com>, Piotr Dymacz <pepe2k@gmail.com>,\n Tudor Ambarus <tudor.ambarus@microchip.com>\nSender: \"linux-mtd\" <linux-mtd-bounces@lists.infradead.org>\nErrors-To: linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org\n\nAdd XT25F128B made by XTX Technology (Shenzhen) Limited.\nThis chip supports dual and quad read and uniform 4K-byte erase.\nVerified on Teltonika RUT955 which comes with XT25F128B in recent\nversions of the device.\n\nSigned-off-by: Daniel Golle <daniel@makrotopia.org>\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n drivers/mtd/spi-nor/spi-nor.c | 4 ++++\n 1 file changed, 4 insertions(+)\n\n--- a/drivers/mtd/spi-nor/Makefile\n+++ b/drivers/mtd/spi-nor/Makefile\n@@ -17,6 +17,7 @@ spi-nor-objs\t\t\t+= sst.o\n spi-nor-objs\t\t\t+= winbond.o\n spi-nor-objs\t\t\t+= xilinx.o\n spi-nor-objs\t\t\t+= xmc.o\n+spi-nor-objs\t\t\t+= xtx.o\n obj-$(CONFIG_MTD_SPI_NOR)\t+= spi-nor.o\n \n obj-$(CONFIG_MTD_SPI_NOR)\t+= controllers/\n--- /dev/null\n+++ b/drivers/mtd/spi-nor/xtx.c\n@@ -0,0 +1,15 @@\n+// SPDX-License-Identifier: GPL-2.0\n+#include <linux/mtd/spi-nor.h>\n+\n+#include \"core.h\"\n+\n+static const struct flash_info xtx_parts[] = {\n+\t/* XTX Technology (Shenzhen) Limited */\n+\t{ \"xt25f128b\", INFO(0x0B4018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },\n+};\n+\n+const struct spi_nor_manufacturer spi_nor_xtx = {\n+\t.name = \"xtx\",\n+\t.parts = xtx_parts,\n+\t.nparts = ARRAY_SIZE(xtx_parts),\n+};\n--- a/drivers/mtd/spi-nor/core.c\n+++ b/drivers/mtd/spi-nor/core.c\n@@ -2028,6 +2028,7 @@ static const struct spi_nor_manufacturer\n \t&spi_nor_winbond,\n \t&spi_nor_xilinx,\n \t&spi_nor_xmc,\n+\t&spi_nor_xtx,\n };\n \n static const struct flash_info *\n--- a/drivers/mtd/spi-nor/core.h\n+++ b/drivers/mtd/spi-nor/core.h\n@@ -398,6 +398,7 @@ extern const struct spi_nor_manufacturer\n extern const struct spi_nor_manufacturer spi_nor_winbond;\n extern const struct spi_nor_manufacturer spi_nor_xilinx;\n extern const struct spi_nor_manufacturer spi_nor_xmc;\n+extern const struct spi_nor_manufacturer spi_nor_xtx;\n \n int spi_nor_write_enable(struct spi_nor *nor);\n int spi_nor_write_disable(struct spi_nor *nor);\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/482-mtd-spi-nor-add-support-for-Gigadevice-GD25D05.patch",
    "content": "From d68b4aa22e8c625685bfad642dd7337948dc0ad1 Mon Sep 17 00:00:00 2001\nFrom: Koen Vandeputte <koen.vandeputte@ncentric.com>\nDate: Mon, 6 Jan 2020 13:07:56 +0100\nSubject: [PATCH] mtd: spi-nor: add support for Gigadevice GD25D05\n\nSigned-off-by: Koen Vandeputte <koen.vandeputte@ncentric.com>\n---\n drivers/mtd/spi-nor/spi-nor.c | 5 +++++\n 1 file changed, 5 insertions(+)\n\n--- a/drivers/mtd/spi-nor/gigadevice.c\n+++ b/drivers/mtd/spi-nor/gigadevice.c\n@@ -24,6 +24,9 @@ static struct spi_nor_fixups gd25q256_fi\n };\n \n static const struct flash_info gigadevice_parts[] = {\n+\t{ \"gd25q05\", INFO(0xc84010, 0, 64 * 1024,  1,\n+\t\t\t  SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |\n+\t\t\t  SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },\n \t{ \"gd25q16\", INFO(0xc84015, 0, 64 * 1024,  32,\n \t\t\t  SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |\n \t\t\t  SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/483-mtd-spi-nor-add-gd25q512.patch",
    "content": "--- a/drivers/mtd/spi-nor/gigadevice.c\n+++ b/drivers/mtd/spi-nor/gigadevice.c\n@@ -53,6 +53,9 @@ static const struct flash_info gigadevic\n \t\t\t   SPI_NOR_4B_OPCODES | SPI_NOR_HAS_LOCK |\n \t\t\t   SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6)\n \t\t.fixups = &gd25q256_fixups },\n+\t{ \"gd25q512\", INFO(0xc84020, 0, 64 * 1024, 1024,\n+\t\t\t   SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |\n+\t\t\t   SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4B_OPCODES) },\n };\n \n const struct spi_nor_manufacturer spi_nor_gigadevice = {\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/483-mtd-spinand-add-support-for-xtx-xt26g0xa.patch",
    "content": "From a07e31adf2753cad2fd9790db5bfc047c81e8152 Mon Sep 17 00:00:00 2001\nFrom: Felix Matouschek <felix@matouschek.org>\nDate: Fri, 2 Jul 2021 20:31:23 +0200\nSubject: [PATCH] mtd: spinand: Add support for XTX XT26G0xA\n\nAdd support for XTX Technology XT26G01AXXXXX, XTX26G02AXXXXX and\nXTX26G04AXXXXX SPI NAND.\n\nThese are 3V, 1G/2G/4Gbit serial SLC NAND flash devices with on-die ECC\n(8bit strength per 512bytes).\n\nTested on Teltonika RUTX10 flashed with OpenWrt.\n\nDatasheets available at\nhttp://www.xtxtech.com/download/?AId=225\nhttps://datasheet.lcsc.com/szlcsc/2005251034_XTX-XT26G01AWSEGA_C558841.pdf\n\nSigned-off-by: Felix Matouschek <felix@matouschek.org>\n---\n drivers/mtd/nand/spi/Makefile |   2 +-\n drivers/mtd/nand/spi/core.c   |   1 +\n drivers/mtd/nand/spi/xtx.c    | 122 ++++++++++++++++++++++++++++++++++\n include/linux/mtd/spinand.h   |   1 +\n 4 files changed, 125 insertions(+), 1 deletion(-)\n create mode 100644 drivers/mtd/nand/spi/xtx.c\n\n--- a/drivers/mtd/nand/spi/Makefile\n+++ b/drivers/mtd/nand/spi/Makefile\n@@ -1,3 +1,3 @@\n # SPDX-License-Identifier: GPL-2.0\n-spinand-objs := core.o gigadevice.o macronix.o micron.o paragon.o toshiba.o winbond.o\n+spinand-objs := core.o gigadevice.o macronix.o micron.o paragon.o toshiba.o winbond.o xtx.o\n obj-$(CONFIG_MTD_SPI_NAND) += spinand.o\n--- a/drivers/mtd/nand/spi/core.c\n+++ b/drivers/mtd/nand/spi/core.c\n@@ -760,6 +760,7 @@ static const struct spinand_manufacturer\n \t&paragon_spinand_manufacturer,\n \t&toshiba_spinand_manufacturer,\n \t&winbond_spinand_manufacturer,\n+\t&xtx_spinand_manufacturer,\n };\n \n static int spinand_manufacturer_match(struct spinand_device *spinand,\n--- /dev/null\n+++ b/drivers/mtd/nand/spi/xtx.c\n@@ -0,0 +1,122 @@\n+// SPDX-License-Identifier: GPL-2.0\n+/*\n+ * Author:\n+ * Felix Matouschek <felix@matouschek.org>\n+ */\n+\n+#include <linux/device.h>\n+#include <linux/kernel.h>\n+#include <linux/mtd/spinand.h>\n+\n+#define SPINAND_MFR_XTX\t0x0B\n+\n+#define XT26G0XA_STATUS_ECC_MASK\tGENMASK(5, 2)\n+#define XT26G0XA_STATUS_ECC_NO_DETECTED\t(0 << 2)\n+#define XT26G0XA_STATUS_ECC_8_CORRECTED\t(3 << 4)\n+#define XT26G0XA_STATUS_ECC_UNCOR_ERROR\t(2 << 4)\n+\n+static SPINAND_OP_VARIANTS(read_cache_variants,\n+\t\tSPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 1, NULL, 0),\n+\t\tSPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),\n+\t\tSPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),\n+\t\tSPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),\n+\t\tSPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),\n+\t\tSPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));\n+\n+static SPINAND_OP_VARIANTS(write_cache_variants,\n+\t\tSPINAND_PROG_LOAD_X4(true, 0, NULL, 0),\n+\t\tSPINAND_PROG_LOAD(true, 0, NULL, 0));\n+\n+static SPINAND_OP_VARIANTS(update_cache_variants,\n+\t\tSPINAND_PROG_LOAD_X4(false, 0, NULL, 0),\n+\t\tSPINAND_PROG_LOAD(false, 0, NULL, 0));\n+\n+static int xt26g0xa_ooblayout_ecc(struct mtd_info *mtd, int section,\n+\t\t\t\t   struct mtd_oob_region *region)\n+{\n+\tif (section)\n+\t\treturn -ERANGE;\n+\n+\tregion->offset = 48;\n+\tregion->length = 16;\n+\n+\treturn 0;\n+}\n+\n+static int xt26g0xa_ooblayout_free(struct mtd_info *mtd, int section,\n+\t\t\t\t   struct mtd_oob_region *region)\n+{\n+\tif (section)\n+\t\treturn -ERANGE;\n+\n+\tregion->offset = 1;\n+\tregion->length = 47;\n+\n+\treturn 0;\n+}\n+\n+static const struct mtd_ooblayout_ops xt26g0xa_ooblayout = {\n+\t.ecc = xt26g0xa_ooblayout_ecc,\n+\t.free = xt26g0xa_ooblayout_free,\n+};\n+\n+static int xt26g0xa_ecc_get_status(struct spinand_device *spinand,\n+\t\t\t\t\t u8 status)\n+{\n+\tswitch (status & XT26G0XA_STATUS_ECC_MASK) {\n+\tcase XT26G0XA_STATUS_ECC_NO_DETECTED:\n+\t\treturn 0;\n+\tcase XT26G0XA_STATUS_ECC_8_CORRECTED:\n+\t\treturn 8;\n+\tcase XT26G0XA_STATUS_ECC_UNCOR_ERROR:\n+\t\treturn -EBADMSG;\n+\tdefault: /* (1 << 2) through (7 << 2) are 1-7 corrected errors */\n+\t\treturn (status & XT26G0XA_STATUS_ECC_MASK) >> 2;\n+\t}\n+\n+\treturn -EINVAL;\n+}\n+\n+static const struct spinand_info xtx_spinand_table[] = {\n+\tSPINAND_INFO(\"XT26G01A\",\n+\t\t     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xE1),\n+\t\t     NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),\n+\t\t     NAND_ECCREQ(8, 512),\n+\t\t     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,\n+\t\t\t\t\t      &write_cache_variants,\n+\t\t\t\t\t      &update_cache_variants),\n+\t\t     SPINAND_HAS_QE_BIT,\n+\t\t     SPINAND_ECCINFO(&xt26g0xa_ooblayout,\n+\t\t\t\t     xt26g0xa_ecc_get_status)),\n+\tSPINAND_INFO(\"XT26G02A\",\n+\t\t     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xE2),\n+\t\t     NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 1, 1, 1),\n+\t\t     NAND_ECCREQ(8, 512),\n+\t\t     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,\n+\t\t\t\t\t      &write_cache_variants,\n+\t\t\t\t\t      &update_cache_variants),\n+\t\t     SPINAND_HAS_QE_BIT,\n+\t\t     SPINAND_ECCINFO(&xt26g0xa_ooblayout,\n+\t\t\t\t     xt26g0xa_ecc_get_status)),\n+\tSPINAND_INFO(\"XT26G04A\",\n+\t\t     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xE3),\n+\t\t     NAND_MEMORG(1, 2048, 64, 128, 2048, 40, 1, 1, 1),\n+\t\t     NAND_ECCREQ(8, 512),\n+\t\t     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,\n+\t\t\t\t\t      &write_cache_variants,\n+\t\t\t\t\t      &update_cache_variants),\n+\t\t     SPINAND_HAS_QE_BIT,\n+\t\t     SPINAND_ECCINFO(&xt26g0xa_ooblayout,\n+\t\t\t\t     xt26g0xa_ecc_get_status)),\n+};\n+\n+static const struct spinand_manufacturer_ops xtx_spinand_manuf_ops = {\n+};\n+\n+const struct spinand_manufacturer xtx_spinand_manufacturer = {\n+\t.id = SPINAND_MFR_XTX,\n+\t.name = \"XTX\",\n+\t.chips = xtx_spinand_table,\n+\t.nchips = ARRAY_SIZE(xtx_spinand_table),\n+\t.ops = &xtx_spinand_manuf_ops,\n+};\n--- a/include/linux/mtd/spinand.h\n+++ b/include/linux/mtd/spinand.h\n@@ -244,6 +244,7 @@ extern const struct spinand_manufacturer\n extern const struct spinand_manufacturer paragon_spinand_manufacturer;\n extern const struct spinand_manufacturer toshiba_spinand_manufacturer;\n extern const struct spinand_manufacturer winbond_spinand_manufacturer;\n+extern const struct spinand_manufacturer xtx_spinand_manufacturer;\n \n /**\n  * struct spinand_op_variants - SPI NAND operation variants\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/484-mtd-spi-nor-add-esmt-f25l16pa.patch",
    "content": "--- a/drivers/mtd/spi-nor/esmt.c\n+++ b/drivers/mtd/spi-nor/esmt.c\n@@ -10,6 +10,8 @@\n \n static const struct flash_info esmt_parts[] = {\n \t/* ESMT */\n+\t{ \"f25l16pa-2s\", INFO(0x8c2115, 0, 64 * 1024, 32,\n+\t\t\t   SECT_4K | SPI_NOR_HAS_LOCK) },\n \t{ \"f25l32pa\", INFO(0x8c2016, 0, 64 * 1024, 64,\n \t\t\t   SECT_4K | SPI_NOR_HAS_LOCK) },\n \t{ \"f25l32qa\", INFO(0x8c4116, 0, 64 * 1024, 64,\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/485-mtd-spi-nor-add-xmc-xm25qh128c.patch",
    "content": "--- a/drivers/mtd/spi-nor/xmc.c\n+++ b/drivers/mtd/spi-nor/xmc.c\n@@ -14,6 +14,8 @@ static const struct flash_info xmc_parts\n \t\t\t    SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },\n \t{ \"XM25QH128A\", INFO(0x207018, 0, 64 * 1024, 256,\n \t\t\t     SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },\n+\t{ \"XM25QH128C\", INFO(0x204018, 0, 64 * 1024, 256,\n+\t\t\t     SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },\n };\n \n const struct spi_nor_manufacturer spi_nor_xmc = {\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/490-ubi-auto-attach-mtd-device-named-ubi-or-data-on-boot.patch",
    "content": "From: Daniel Golle <daniel@makrotopia.org>\nSubject: ubi: auto-attach mtd device named \"ubi\" or \"data\" on boot\n\nSigned-off-by: Daniel Golle <daniel@makrotopia.org>\n---\n drivers/mtd/ubi/build.c | 36 ++++++++++++++++++++++++++++++++++++\n 1 file changed, 36 insertions(+)\n\n--- a/drivers/mtd/ubi/build.c\n+++ b/drivers/mtd/ubi/build.c\n@@ -1185,6 +1185,73 @@ static struct mtd_info * __init open_mtd\n \treturn mtd;\n }\n \n+/*\n+ * This function tries attaching mtd partitions named either \"ubi\" or \"data\"\n+ * during boot.\n+ */\n+static void __init ubi_auto_attach(void)\n+{\n+\tint err;\n+\tstruct mtd_info *mtd;\n+\tloff_t offset = 0;\n+\tsize_t len;\n+\tchar magic[4];\n+\n+\t/* try attaching mtd device named \"ubi\" or \"data\" */\n+\tmtd = open_mtd_device(\"ubi\");\n+\tif (IS_ERR(mtd))\n+\t\tmtd = open_mtd_device(\"data\");\n+\n+\tif (IS_ERR(mtd))\n+\t\treturn;\n+\n+\t/* get the first not bad block */\n+\tif (mtd_can_have_bb(mtd))\n+\t\twhile (mtd_block_isbad(mtd, offset)) {\n+\t\t\toffset += mtd->erasesize;\n+\n+\t\t\tif (offset > mtd->size) {\n+\t\t\t\tpr_err(\"UBI error: Failed to find a non-bad \"\n+\t\t\t\t       \"block on mtd%d\\n\", mtd->index);\n+\t\t\t\tgoto cleanup;\n+\t\t\t}\n+\t\t}\n+\n+\t/* check if the read from flash was successful */\n+\terr = mtd_read(mtd, offset, 4, &len, (void *) magic);\n+\tif ((err && !mtd_is_bitflip(err)) || len != 4) {\n+\t\tpr_err(\"UBI error: unable to read from mtd%d\\n\", mtd->index);\n+\t\tgoto cleanup;\n+\t}\n+\n+\t/* check for a valid ubi magic */\n+\tif (strncmp(magic, \"UBI#\", 4)) {\n+\t\tpr_err(\"UBI error: no valid UBI magic found inside mtd%d\\n\", mtd->index);\n+\t\tgoto cleanup;\n+\t}\n+\n+\t/* don't auto-add media types where UBI doesn't makes sense */\n+\tif (mtd->type != MTD_NANDFLASH &&\n+\t    mtd->type != MTD_NORFLASH &&\n+\t    mtd->type != MTD_DATAFLASH &&\n+\t    mtd->type != MTD_MLCNANDFLASH)\n+\t\tgoto cleanup;\n+\n+\tmutex_lock(&ubi_devices_mutex);\n+\tpr_notice(\"UBI: auto-attach mtd%d\\n\", mtd->index);\n+\terr = ubi_attach_mtd_dev(mtd, UBI_DEV_NUM_AUTO, 0, 0);\n+\tmutex_unlock(&ubi_devices_mutex);\n+\tif (err < 0) {\n+\t\tpr_err(\"UBI error: cannot attach mtd%d\\n\", mtd->index);\n+\t\tgoto cleanup;\n+\t}\n+\n+\treturn;\n+\n+cleanup:\n+\tput_mtd_device(mtd);\n+}\n+\n static int __init ubi_init(void)\n {\n \tint err, i, k;\n@@ -1268,6 +1335,12 @@ static int __init ubi_init(void)\n \t\t}\n \t}\n \n+\t/* auto-attach mtd devices only if built-in to the kernel and no ubi.mtd\n+\t * parameter was given */\n+\tif (IS_ENABLED(CONFIG_MTD_ROOTFS_ROOT_DEV) &&\n+\t    !ubi_is_module() && !mtd_devs)\n+\t\tubi_auto_attach();\n+\n \terr = ubiblock_init();\n \tif (err) {\n \t\tpr_err(\"UBI error: block: cannot initialize, error %d\\n\", err);\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/491-ubi-auto-create-ubiblock-device-for-rootfs.patch",
    "content": "From: Daniel Golle <daniel@makrotopia.org>\nSubject: ubi: auto-create ubiblock device for rootfs\n\nSigned-off-by: Daniel Golle <daniel@makrotopia.org>\n---\n drivers/mtd/ubi/block.c | 42 ++++++++++++++++++++++++++++++++++++++++++\n 1 file changed, 42 insertions(+)\n\n--- a/drivers/mtd/ubi/block.c\n+++ b/drivers/mtd/ubi/block.c\n@@ -652,6 +652,47 @@ static void __init ubiblock_create_from_\n \t}\n }\n \n+#define UBIFS_NODE_MAGIC  0x06101831\n+static inline int ubi_vol_is_ubifs(struct ubi_volume_desc *desc)\n+{\n+\tint ret;\n+\tuint32_t magic_of, magic;\n+\tret = ubi_read(desc, 0, (char *)&magic_of, 0, 4);\n+\tif (ret)\n+\t\treturn 0;\n+\tmagic = le32_to_cpu(magic_of);\n+\treturn magic == UBIFS_NODE_MAGIC;\n+}\n+\n+static void __init ubiblock_create_auto_rootfs(void)\n+{\n+\tint ubi_num, ret, is_ubifs;\n+\tstruct ubi_volume_desc *desc;\n+\tstruct ubi_volume_info vi;\n+\n+\tfor (ubi_num = 0; ubi_num < UBI_MAX_DEVICES; ubi_num++) {\n+\t\tdesc = ubi_open_volume_nm(ubi_num, \"rootfs\", UBI_READONLY);\n+\t\tif (IS_ERR(desc))\n+\t\t\tdesc = ubi_open_volume_nm(ubi_num, \"fit\", UBI_READONLY);;\n+\n+\t\tif (IS_ERR(desc))\n+\t\t\tcontinue;\n+\n+\t\tubi_get_volume_info(desc, &vi);\n+\t\tis_ubifs = ubi_vol_is_ubifs(desc);\n+\t\tubi_close_volume(desc);\n+\t\tif (is_ubifs)\n+\t\t\tbreak;\n+\n+\t\tret = ubiblock_create(&vi);\n+\t\tif (ret)\n+\t\t\tpr_err(\"UBI error: block: can't add '%s' volume, err=%d\\n\",\n+\t\t\t\tvi.name, ret);\n+\t\t/* always break if we get here */\n+\t\tbreak;\n+\t}\n+}\n+\n static void ubiblock_remove_all(void)\n {\n \tstruct ubiblock *next;\n@@ -684,6 +725,10 @@ int __init ubiblock_init(void)\n \t */\n \tubiblock_create_from_param();\n \n+\t/* auto-attach \"rootfs\" volume if existing and non-ubifs */\n+\tif (IS_ENABLED(CONFIG_MTD_ROOTFS_ROOT_DEV))\n+\t\tubiblock_create_auto_rootfs();\n+\n \t/*\n \t * Block devices are only created upon user requests, so we ignore\n \t * existing volumes.\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/492-try-auto-mounting-ubi0-rootfs-in-init-do_mounts.c.patch",
    "content": "From: Daniel Golle <daniel@makrotopia.org>\nSubject: try auto-mounting ubi0:rootfs in init/do_mounts.c\n\nSigned-off-by: Daniel Golle <daniel@makrotopia.org>\n---\n init/do_mounts.c | 26 +++++++++++++++++++++++++-\n 1 file changed, 25 insertions(+), 1 deletion(-)\n\n--- a/init/do_mounts.c\n+++ b/init/do_mounts.c\n@@ -474,7 +474,30 @@ retry:\n out:\n \tput_page(page);\n }\n- \n+\n+#ifdef CONFIG_MTD_ROOTFS_ROOT_DEV\n+static int __init mount_ubi_rootfs(void)\n+{\n+\tint flags = MS_SILENT;\n+\tint err, tried = 0;\n+\n+\twhile (tried < 2) {\n+\t\terr = do_mount_root(\"ubi0:rootfs\", \"ubifs\", flags, \\\n+\t\t\t\t\troot_mount_data);\n+\t\tswitch (err) {\n+\t\t\tcase -EACCES:\n+\t\t\t\tflags |= MS_RDONLY;\n+\t\t\t\ttried++;\n+\t\t\t\tbreak;\n+\t\t\tdefault:\n+\t\t\t\treturn err;\n+\t\t}\n+\t}\n+\n+\treturn -EINVAL;\n+}\n+#endif\n+\n #ifdef CONFIG_ROOT_NFS\n \n #define NFSROOT_TIMEOUT_MIN\t5\n@@ -567,6 +590,10 @@ void __init mount_root(void)\n \t\treturn;\n \t}\n #endif\n+#ifdef CONFIG_MTD_ROOTFS_ROOT_DEV\n+\tif (!mount_ubi_rootfs())\n+\t\treturn;\n+#endif\n #ifdef CONFIG_BLOCK\n \t{\n \t\tint err = create_dev(\"/dev/root\", ROOT_DEV);\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/493-ubi-set-ROOT_DEV-to-ubiblock-rootfs-if-unset.patch",
    "content": "From: Daniel Golle <daniel@makrotopia.org>\nSubject: ubi: set ROOT_DEV to ubiblock \"rootfs\" if unset\n\nSigned-off-by: Daniel Golle <daniel@makrotopia.org>\n---\n drivers/mtd/ubi/block.c | 10 ++++++++++\n 1 file changed, 10 insertions(+)\n\n--- a/drivers/mtd/ubi/block.c\n+++ b/drivers/mtd/ubi/block.c\n@@ -42,6 +42,7 @@\n #include <linux/scatterlist.h>\n #include <linux/idr.h>\n #include <asm/div64.h>\n+#include <linux/root_dev.h>\n \n #include \"ubi-media.h\"\n #include \"ubi.h\"\n@@ -458,6 +459,15 @@ int ubiblock_create(struct ubi_volume_in\n \tdev_info(disk_to_dev(dev->gd), \"created from ubi%d:%d(%s)\",\n \t\t dev->ubi_num, dev->vol_id, vi->name);\n \tmutex_unlock(&devices_mutex);\n+\n+\tif (!strcmp(vi->name, \"rootfs\") &&\n+\t    IS_ENABLED(CONFIG_MTD_ROOTFS_ROOT_DEV) &&\n+\t    ROOT_DEV == 0) {\n+\t\tpr_notice(\"ubiblock: device ubiblock%d_%d (%s) set to be root filesystem\\n\",\n+\t\t\t  dev->ubi_num, dev->vol_id, vi->name);\n+\t\tROOT_DEV = MKDEV(gd->major, gd->first_minor);\n+\t}\n+\n \treturn 0;\n \n out_free_queue:\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/494-mtd-ubi-add-EOF-marker-support.patch",
    "content": "From: Gabor Juhos <juhosg@openwrt.org>\nSubject: mtd: add EOF marker support to the UBI layer\n\nSigned-off-by: Gabor Juhos <juhosg@openwrt.org>\n---\n drivers/mtd/ubi/attach.c | 25 ++++++++++++++++++++++---\n drivers/mtd/ubi/ubi.h    |  1 +\n 2 files changed, 23 insertions(+), 3 deletions(-)\n\n--- a/drivers/mtd/ubi/attach.c\n+++ b/drivers/mtd/ubi/attach.c\n@@ -926,6 +926,13 @@ static bool vol_ignored(int vol_id)\n #endif\n }\n \n+static bool ec_hdr_has_eof(struct ubi_ec_hdr *ech)\n+{\n+\treturn ech->padding1[0] == 'E' &&\n+\t       ech->padding1[1] == 'O' &&\n+\t       ech->padding1[2] == 'F';\n+}\n+\n /**\n  * scan_peb - scan and process UBI headers of a PEB.\n  * @ubi: UBI device description object\n@@ -958,9 +965,21 @@ static int scan_peb(struct ubi_device *u\n \t\treturn 0;\n \t}\n \n-\terr = ubi_io_read_ec_hdr(ubi, pnum, ech, 0);\n-\tif (err < 0)\n-\t\treturn err;\n+\tif (!ai->eof_found) {\n+\t\terr = ubi_io_read_ec_hdr(ubi, pnum, ech, 0);\n+\t\tif (err < 0)\n+\t\t\treturn err;\n+\n+\t\tif (ec_hdr_has_eof(ech)) {\n+\t\t\tpr_notice(\"UBI: EOF marker found, PEBs from %d will be erased\\n\",\n+\t\t\t\tpnum);\n+\t\t\tai->eof_found = true;\n+\t\t}\n+\t}\n+\n+\tif (ai->eof_found)\n+\t\terr = UBI_IO_FF_BITFLIPS;\n+\n \tswitch (err) {\n \tcase 0:\n \t\tbreak;\n--- a/drivers/mtd/ubi/ubi.h\n+++ b/drivers/mtd/ubi/ubi.h\n@@ -782,6 +782,7 @@ struct ubi_attach_info {\n \tint mean_ec;\n \tuint64_t ec_sum;\n \tint ec_count;\n+\tbool eof_found;\n \tstruct kmem_cache *aeb_slab_cache;\n \tstruct ubi_ec_hdr *ech;\n \tstruct ubi_vid_io_buf *vidb;\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/495-mtd-core-add-get_mtd_device_by_node.patch",
    "content": "From 1bd1b740f208d1cf4071932cc51860d37266c402 Mon Sep 17 00:00:00 2001\nFrom: Bernhard Frauendienst <kernel@nospam.obeliks.de>\nDate: Sat, 1 Sep 2018 00:30:11 +0200\nSubject: [PATCH 495/497] mtd: core: add get_mtd_device_by_node\n\nAdd function to retrieve a mtd device by its OF node. Since drivers can\nassign arbitrary names to mtd devices in the absence of a label\nproperty, there is no other reliable way to retrieve a mtd device for a\ngiven OF node.\n\nSigned-off-by: Bernhard Frauendienst <kernel@nospam.obeliks.de>\nReviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>\n---\n drivers/mtd/mtdcore.c   | 38 ++++++++++++++++++++++++++++++++++++++\n include/linux/mtd/mtd.h |  2 ++\n 2 files changed, 40 insertions(+)\n\n--- a/drivers/mtd/mtdcore.c\n+++ b/drivers/mtd/mtdcore.c\n@@ -1046,6 +1046,44 @@ out_unlock:\n }\n EXPORT_SYMBOL_GPL(get_mtd_device_nm);\n \n+/**\n+ *\tget_mtd_device_by_node - obtain a validated handle for an MTD device\n+ *\tby of_node\n+ *\t@of_node: OF node of MTD device to open\n+ *\n+ *\tThis function returns MTD device description structure in case of\n+ *\tsuccess and an error code in case of failure.\n+ */\n+struct mtd_info *get_mtd_device_by_node(const struct device_node *of_node)\n+{\n+\tint err = -ENODEV;\n+\tstruct mtd_info *mtd = NULL, *other;\n+\n+\tmutex_lock(&mtd_table_mutex);\n+\n+\tmtd_for_each_device(other) {\n+\t\tif (of_node == other->dev.of_node) {\n+\t\t\tmtd = other;\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\n+\tif (!mtd)\n+\t\tgoto out_unlock;\n+\n+\terr = __get_mtd_device(mtd);\n+\tif (err)\n+\t\tgoto out_unlock;\n+\n+\tmutex_unlock(&mtd_table_mutex);\n+\treturn mtd;\n+\n+out_unlock:\n+\tmutex_unlock(&mtd_table_mutex);\n+\treturn ERR_PTR(err);\n+}\n+EXPORT_SYMBOL_GPL(get_mtd_device_by_node);\n+\n void put_mtd_device(struct mtd_info *mtd)\n {\n \tmutex_lock(&mtd_table_mutex);\n--- a/include/linux/mtd/mtd.h\n+++ b/include/linux/mtd/mtd.h\n@@ -698,6 +698,8 @@ extern struct mtd_info *get_mtd_device(s\n extern int __get_mtd_device(struct mtd_info *mtd);\n extern void __put_mtd_device(struct mtd_info *mtd);\n extern struct mtd_info *get_mtd_device_nm(const char *name);\n+extern struct mtd_info *get_mtd_device_by_node(\n+\t\tconst struct device_node *of_node);\n extern void put_mtd_device(struct mtd_info *mtd);\n \n static inline uint64_t mtdpart_get_offset(const struct mtd_info *mtd)\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/496-dt-bindings-add-bindings-for-mtd-concat-devices.patch",
    "content": "From 5734c6669fba7ddb5ef491ccff7159d15dba0b59 Mon Sep 17 00:00:00 2001\nFrom: Bernhard Frauendienst <kernel@nospam.obeliks.de>\nDate: Wed, 5 Sep 2018 01:32:51 +0200\nSubject: [PATCH 496/497] dt-bindings: add bindings for mtd-concat devices\n\nDocument virtual mtd-concat device bindings.\n\nSigned-off-by: Bernhard Frauendienst <kernel@nospam.obeliks.de>\n---\n .../devicetree/bindings/mtd/mtd-concat.txt    | 36 +++++++++++++++++++\n 1 file changed, 36 insertions(+)\n create mode 100644 Documentation/devicetree/bindings/mtd/mtd-concat.txt\n\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/mtd/mtd-concat.txt\n@@ -0,0 +1,36 @@\n+Virtual MTD concat device\n+\n+Requires properties:\n+- devices: list of phandles to mtd nodes that should be concatenated\n+\n+Example:\n+\n+&spi {\n+\tflash0: flash@0 {\n+\t\t...\n+\t};\n+\tflash1: flash@1 {\n+\t\t...\n+\t};\n+};\n+\n+flash {\n+\tcompatible = \"mtd-concat\";\n+\n+\tdevices = <&flash0 &flash1>;\n+\n+\tpartitions {\n+\t\tcompatible = \"fixed-partitions\";\n+\n+\t\tpartition@0 {\n+\t\t\tlabel = \"boot\";\n+\t\t\treg = <0x0000000 0x0040000>;\n+\t\t\tread-only;\n+\t\t};\n+\n+\t\tpartition@40000 {\n+\t\t\tlabel = \"firmware\";\n+\t\t\treg = <0x0040000 0x1fc0000>;\n+\t\t};\n+\t}\n+}\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/497-mtd-mtdconcat-add-dt-driver-for-concat-devices.patch",
    "content": "From e53f712d8eac71f54399b61038ccf87d2cee99d7 Mon Sep 17 00:00:00 2001\nFrom: Bernhard Frauendienst <kernel@nospam.obeliks.de>\nDate: Sat, 25 Aug 2018 12:35:22 +0200\nSubject: [PATCH 497/497] mtd: mtdconcat: add dt driver for concat devices\n\nSome mtd drivers like physmap variants have support for concatenating\nmultiple mtd devices, but there is no generic way to define such a\nconcat device from within the device tree.\n\nThis is useful for some SoC boards that use multiple flash chips as\nmemory banks of a single mtd device, with partitions spanning chip\nborders.\n\nThis commit adds a driver for creating virtual mtd-concat devices. They\nmust have a compatible = \"mtd-concat\" line, and define a list of devices\nto concat in the 'devices' property, for example:\n\nflash {\n  compatible = \"mtd-concat\";\n\n  devices = <&flash0 &flash1>;\n\n  partitions {\n    ...\n  };\n};\n\nThe driver is added to the very end of the mtd Makefile to increase the\nlikelyhood of all child devices already being loaded at the time of\nprobing, preventing unnecessary deferred probes.\n\nSigned-off-by: Bernhard Frauendienst <kernel@nospam.obeliks.de>\n---\n drivers/mtd/Kconfig                 |   2 +\n drivers/mtd/Makefile                |   3 +\n drivers/mtd/composite/Kconfig       |  12 +++\n drivers/mtd/composite/Makefile      |   6 ++\n drivers/mtd/composite/virt_concat.c | 128 ++++++++++++++++++++++++++++\n 5 files changed, 151 insertions(+)\n create mode 100644 drivers/mtd/composite/Kconfig\n create mode 100644 drivers/mtd/composite/Makefile\n create mode 100644 drivers/mtd/composite/virt_concat.c\n\n--- a/drivers/mtd/Kconfig\n+++ b/drivers/mtd/Kconfig\n@@ -238,4 +238,6 @@ source \"drivers/mtd/ubi/Kconfig\"\n \n source \"drivers/mtd/hyperbus/Kconfig\"\n \n+source \"drivers/mtd/composite/Kconfig\"\n+\n endif # MTD\n--- a/drivers/mtd/Makefile\n+++ b/drivers/mtd/Makefile\n@@ -33,3 +33,6 @@ obj-y\t\t+= chips/ lpddr/ maps/ devices/ n\n obj-$(CONFIG_MTD_SPI_NOR)\t+= spi-nor/\n obj-$(CONFIG_MTD_UBI)\t\t+= ubi/\n obj-$(CONFIG_MTD_HYPERBUS)\t+= hyperbus/\n+\n+# Composite drivers must be loaded last\n+obj-y\t\t\t\t+= composite/\n--- /dev/null\n+++ b/drivers/mtd/composite/Kconfig\n@@ -0,0 +1,12 @@\n+menu \"Composite MTD device drivers\"\n+\tdepends on MTD!=n\n+\n+config MTD_VIRT_CONCAT\n+\ttristate \"Virtual concat MTD device\"\n+\thelp\n+\t  This driver allows creation of a virtual MTD concat device, which\n+\t  concatenates multiple underlying MTD devices to a single device.\n+\t  This is required by some SoC boards where multiple memory banks are\n+\t  used as one device with partitions spanning across device boundaries.\n+\n+endmenu\n--- /dev/null\n+++ b/drivers/mtd/composite/Makefile\n@@ -0,0 +1,6 @@\n+# SPDX-License-Identifier: GPL-2.0\n+#\n+# linux/drivers/mtd/composite/Makefile\n+#\n+\n+obj-$(CONFIG_MTD_VIRT_CONCAT)   += virt_concat.o\n--- /dev/null\n+++ b/drivers/mtd/composite/virt_concat.c\n@@ -0,0 +1,128 @@\n+// SPDX-License-Identifier: GPL-2.0+\n+/*\n+ * Virtual concat MTD device driver\n+ *\n+ * Copyright (C) 2018 Bernhard Frauendienst\n+ * Author: Bernhard Frauendienst, kernel@nospam.obeliks.de\n+ */\n+\n+#include <linux/module.h>\n+#include <linux/device.h>\n+#include <linux/mtd/concat.h>\n+#include <linux/mtd/mtd.h>\n+#include <linux/mtd/partitions.h>\n+#include <linux/of.h>\n+#include <linux/of_platform.h>\n+#include <linux/slab.h>\n+\n+/*\n+ * struct of_virt_concat - platform device driver data.\n+ * @cmtd the final mtd_concat device\n+ * @num_devices the number of devices in @devices\n+ * @devices points to an array of devices already loaded\n+ */\n+struct of_virt_concat {\n+\tstruct mtd_info\t*cmtd;\n+\tint num_devices;\n+\tstruct mtd_info\t**devices;\n+};\n+\n+static int virt_concat_remove(struct platform_device *pdev)\n+{\n+\tstruct of_virt_concat *info;\n+\tint i;\n+\n+\tinfo = platform_get_drvdata(pdev);\n+\tif (!info)\n+\t\treturn 0;\n+\n+\t// unset data for when this is called after a probe error\n+\tplatform_set_drvdata(pdev, NULL);\n+\n+\tif (info->cmtd) {\n+\t\tmtd_device_unregister(info->cmtd);\n+\t\tmtd_concat_destroy(info->cmtd);\n+\t}\n+\n+\tif (info->devices) {\n+\t\tfor (i = 0; i < info->num_devices; i++)\n+\t\t\tput_mtd_device(info->devices[i]);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int virt_concat_probe(struct platform_device *pdev)\n+{\n+\tstruct device_node *node = pdev->dev.of_node;\n+\tstruct of_phandle_iterator it;\n+\tstruct of_virt_concat *info;\n+\tstruct mtd_info *mtd;\n+\tint err = 0, count;\n+\n+\tcount = of_count_phandle_with_args(node, \"devices\", NULL);\n+\tif (count <= 0)\n+\t\treturn -EINVAL;\n+\n+\tinfo = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);\n+\tif (!info)\n+\t\treturn -ENOMEM;\n+\tinfo->devices = devm_kcalloc(&pdev->dev, count,\n+\t\t\t\t     sizeof(*(info->devices)), GFP_KERNEL);\n+\tif (!info->devices) {\n+\t\terr = -ENOMEM;\n+\t\tgoto err_remove;\n+\t}\n+\n+\tplatform_set_drvdata(pdev, info);\n+\n+\tof_for_each_phandle(&it, err, node, \"devices\", NULL, 0) {\n+\t\tmtd = get_mtd_device_by_node(it.node);\n+\t\tif (IS_ERR(mtd)) {\n+\t\t\tof_node_put(it.node);\n+\t\t\terr = -EPROBE_DEFER;\n+\t\t\tgoto err_remove;\n+\t\t}\n+\n+\t\tinfo->devices[info->num_devices++] = mtd;\n+\t}\n+\n+\tinfo->cmtd = mtd_concat_create(info->devices, info->num_devices,\n+\t\t\t\t       dev_name(&pdev->dev));\n+\tif (!info->cmtd) {\n+\t\terr = -ENXIO;\n+\t\tgoto err_remove;\n+\t}\n+\n+\tinfo->cmtd->dev.parent = &pdev->dev;\n+\tmtd_set_of_node(info->cmtd, node);\n+\tmtd_device_register(info->cmtd, NULL, 0);\n+\n+\treturn 0;\n+\n+err_remove:\n+\tvirt_concat_remove(pdev);\n+\n+\treturn err;\n+}\n+\n+static const struct of_device_id virt_concat_of_match[] = {\n+\t{ .compatible = \"mtd-concat\", },\n+\t{ /* sentinel */ }\n+};\n+MODULE_DEVICE_TABLE(of, virt_concat_of_match);\n+\n+static struct platform_driver virt_concat_driver = {\n+\t.probe = virt_concat_probe,\n+\t.remove = virt_concat_remove,\n+\t.driver\t = {\n+\t\t.name   = \"virt-mtdconcat\",\n+\t\t.of_match_table = virt_concat_of_match,\n+\t},\n+};\n+\n+module_platform_driver(virt_concat_driver);\n+\n+MODULE_LICENSE(\"GPL v2\");\n+MODULE_AUTHOR(\"Bernhard Frauendienst <kernel@nospam.obeliks.de>\");\n+MODULE_DESCRIPTION(\"Virtual concat MTD device driver\");\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/498-mtd-spi-nor-locking-support-for-MX25L6405D.patch",
    "content": "From 8bf2ce6ea4ee840b70f55a27f80e1cd308051b13 Mon Sep 17 00:00:00 2001\nFrom: Nick Hainke <vincent@systemli.org>\nDate: Mon, 27 Dec 2021 00:38:13 +0100\nSubject: [PATCH 1/2] mtd: spi-nor: locking support for MX25L6405D\n\nMacronix MX25L6405D supports locking with four block-protection bits.\nCurrently, the driver only sets three bits.  If the bootloader does not\nsustain the flash chip in an unlocked state, the flash might be\nnon-writeable. Add the corresponding flag to enable locking support with\nfour bits in the status register.\n\nTested on Nanostation M2 XM.\n\nSimilar to commit 7ea40b54e83b (\"mtd: spi-nor: enable locking support for\nMX25L12805D\")\n\nSigned-off-by: David Bauer <mail@david-bauer.net>\nSigned-off-by: Nick Hainke <vincent@systemli.org>\n---\n drivers/mtd/spi-nor/macronix.c | 3 ++-\n 1 file changed, 2 insertions(+), 1 deletion(-)\n\n--- a/drivers/mtd/spi-nor/macronix.c\n+++ b/drivers/mtd/spi-nor/macronix.c\n@@ -42,7 +42,8 @@ static const struct flash_info macronix_\n \t{ \"mx25l1606e\",  INFO(0xc22015, 0, 64 * 1024,  32, SECT_4K) },\n \t{ \"mx25l3205d\",  INFO(0xc22016, 0, 64 * 1024,  64, SECT_4K) },\n \t{ \"mx25l3255e\",  INFO(0xc29e16, 0, 64 * 1024,  64, SECT_4K) },\n-\t{ \"mx25l6405d\",  INFO(0xc22017, 0, 64 * 1024, 128, SECT_4K) },\n+\t{ \"mx25l6405d\",  INFO(0xc22017, 0, 64 * 1024, 128, SECT_4K |\n+\t\t\t      SPI_NOR_HAS_LOCK | SPI_NOR_4BIT_BP) },\n \t{ \"mx25u2033e\",  INFO(0xc22532, 0, 64 * 1024,   4, SECT_4K) },\n \t{ \"mx25u3235f\",\t INFO(0xc22536, 0, 64 * 1024,  64,\n \t\t\t      SECT_4K | SPI_NOR_DUAL_READ |\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/499-mtd-spi-nor-disable-16-bit-sr-for-macronix.patch",
    "content": "From 245224608b5368c10407da07557e546743d3c489 Mon Sep 17 00:00:00 2001\nFrom: Nick Hainke <vincent@systemli.org>\nDate: Mon, 27 Dec 2021 09:33:13 +0100\nSubject: [PATCH 2/2] mtd: spi-nor: disable 16-bit-sr for macronix\n\nMacronix flash chips seem to consist of only one status register.\nThese chips will not work with the \"16-bit Write Status (01h) Command\".\nDisable SNOR_F_HAS_16BIT_SR for all Macronix chips.\n\nTested with MX25L6405D.\n\nFixes: 39d1e3340c73 (\"mtd: spi-nor: Fix clearing of QE bit on\nlock()/unlock()\")\n\nSigned-off-by: David Bauer <mail@david-bauer.net>\nSigned-off-by: Nick Hainke <vincent@systemli.org>\n---\n drivers/mtd/spi-nor/macronix.c | 1 +\n 1 file changed, 1 insertion(+)\n\n--- a/drivers/mtd/spi-nor/macronix.c\n+++ b/drivers/mtd/spi-nor/macronix.c\n@@ -94,6 +94,7 @@ static void macronix_default_init(struct\n {\n \tnor->params->quad_enable = spi_nor_sr1_bit6_quad_enable;\n \tnor->params->set_4byte_addr_mode = spi_nor_set_4byte_addr_mode;\n+\tnor->flags &= ~SNOR_F_HAS_16BIT_SR;\n \tnor->flags |= SNOR_F_HAS_LOCK;\n }\n \n"
  },
  {
    "path": "target/linux/generic/pending-5.10/500-fs_cdrom_dependencies.patch",
    "content": "--- a/fs/hfs/Kconfig\n+++ b/fs/hfs/Kconfig\n@@ -2,6 +2,7 @@\n config HFS_FS\n \ttristate \"Apple Macintosh file system support\"\n \tdepends on BLOCK\n+\tselect CDROM\n \tselect NLS\n \thelp\n \t  If you say Y here, you will be able to mount Macintosh-formatted\n--- a/fs/hfsplus/Kconfig\n+++ b/fs/hfsplus/Kconfig\n@@ -2,6 +2,7 @@\n config HFSPLUS_FS\n \ttristate \"Apple Extended HFS file system support\"\n \tdepends on BLOCK\n+\tselect CDROM\n \tselect NLS\n \tselect NLS_UTF8\n \thelp\n--- a/fs/isofs/Kconfig\n+++ b/fs/isofs/Kconfig\n@@ -1,6 +1,7 @@\n # SPDX-License-Identifier: GPL-2.0-only\n config ISO9660_FS\n \ttristate \"ISO 9660 CDROM file system support\"\n+\tselect CDROM\n \thelp\n \t  This is the standard file system used on CD-ROMs.  It was previously\n \t  known as \"High Sierra File System\" and is called \"hsfs\" on other\n--- a/fs/udf/Kconfig\n+++ b/fs/udf/Kconfig\n@@ -1,6 +1,7 @@\n # SPDX-License-Identifier: GPL-2.0-only\n config UDF_FS\n \ttristate \"UDF file system support\"\n+\tselect CDROM\n \tselect CRC_ITU_T\n \tselect NLS\n \thelp\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/530-jffs2_make_lzma_available.patch",
    "content": "From: Alexandros C. Couloumbis <alex@ozo.com>\nSubject: fs: add jffs2/lzma support (not activated by default yet)\n\nlede-commit: c2c88d315fa0e881f8b19da07b62859b915b11b2\nSigned-off-by: Alexandros C. Couloumbis <alex@ozo.com>\n---\n fs/jffs2/Kconfig             |    9 +\n fs/jffs2/Makefile            |    3 +\n fs/jffs2/compr.c             |    6 +\n fs/jffs2/compr.h             |   10 +-\n fs/jffs2/compr_lzma.c        |  128 +++\n fs/jffs2/super.c             |   33 +-\n include/linux/lzma.h         |   62 ++\n include/linux/lzma/LzFind.h  |  115 +++\n include/linux/lzma/LzHash.h  |   54 +\n include/linux/lzma/LzmaDec.h |  231 +++++\n include/linux/lzma/LzmaEnc.h |   80 ++\n include/linux/lzma/Types.h   |  226 +++++\n include/uapi/linux/jffs2.h   |    1 +\n lib/Kconfig                  |    6 +\n lib/Makefile                 |   12 +\n lib/lzma/LzFind.c            |  761 ++++++++++++++\n lib/lzma/LzmaDec.c           |  999 +++++++++++++++++++\n lib/lzma/LzmaEnc.c           | 2271 ++++++++++++++++++++++++++++++++++++++++++\n lib/lzma/Makefile            |    7 +\n 19 files changed, 5008 insertions(+), 6 deletions(-)\n create mode 100644 fs/jffs2/compr_lzma.c\n create mode 100644 include/linux/lzma.h\n create mode 100644 include/linux/lzma/LzFind.h\n create mode 100644 include/linux/lzma/LzHash.h\n create mode 100644 include/linux/lzma/LzmaDec.h\n create mode 100644 include/linux/lzma/LzmaEnc.h\n create mode 100644 include/linux/lzma/Types.h\n create mode 100644 lib/lzma/LzFind.c\n create mode 100644 lib/lzma/LzmaDec.c\n create mode 100644 lib/lzma/LzmaEnc.c\n create mode 100644 lib/lzma/Makefile\n\n--- a/fs/jffs2/Kconfig\n+++ b/fs/jffs2/Kconfig\n@@ -136,6 +136,15 @@ config JFFS2_LZO\n \t  This feature was added in July, 2007. Say 'N' if you need\n \t  compatibility with older bootloaders or kernels.\n \n+config JFFS2_LZMA\n+\tbool \"JFFS2 LZMA compression support\" if JFFS2_COMPRESSION_OPTIONS\n+\tselect LZMA_COMPRESS\n+\tselect LZMA_DECOMPRESS\n+\tdepends on JFFS2_FS\n+\tdefault n\n+\thelp\n+\t  JFFS2 wrapper to the LZMA C SDK\n+\n config JFFS2_RTIME\n \tbool \"JFFS2 RTIME compression support\" if JFFS2_COMPRESSION_OPTIONS\n \tdepends on JFFS2_FS\n--- a/fs/jffs2/Makefile\n+++ b/fs/jffs2/Makefile\n@@ -19,4 +19,7 @@ jffs2-$(CONFIG_JFFS2_RUBIN)\t+= compr_rub\n jffs2-$(CONFIG_JFFS2_RTIME)\t+= compr_rtime.o\n jffs2-$(CONFIG_JFFS2_ZLIB)\t+= compr_zlib.o\n jffs2-$(CONFIG_JFFS2_LZO)\t+= compr_lzo.o\n+jffs2-$(CONFIG_JFFS2_LZMA)\t+= compr_lzma.o\n jffs2-$(CONFIG_JFFS2_SUMMARY)   += summary.o\n+\n+CFLAGS_compr_lzma.o += -Iinclude/linux -Ilib/lzma\n--- a/fs/jffs2/compr.c\n+++ b/fs/jffs2/compr.c\n@@ -378,6 +378,9 @@ int __init jffs2_compressors_init(void)\n #ifdef CONFIG_JFFS2_LZO\n \tjffs2_lzo_init();\n #endif\n+#ifdef CONFIG_JFFS2_LZMA\n+\tjffs2_lzma_init();\n+#endif\n /* Setting default compression mode */\n #ifdef CONFIG_JFFS2_CMODE_NONE\n \tjffs2_compression_mode = JFFS2_COMPR_MODE_NONE;\n@@ -401,6 +404,9 @@ int __init jffs2_compressors_init(void)\n int jffs2_compressors_exit(void)\n {\n /* Unregistering compressors */\n+#ifdef CONFIG_JFFS2_LZMA\n+\tjffs2_lzma_exit();\n+#endif\n #ifdef CONFIG_JFFS2_LZO\n \tjffs2_lzo_exit();\n #endif\n--- a/fs/jffs2/compr.h\n+++ b/fs/jffs2/compr.h\n@@ -29,9 +29,9 @@\n #define JFFS2_DYNRUBIN_PRIORITY  20\n #define JFFS2_LZARI_PRIORITY     30\n #define JFFS2_RTIME_PRIORITY     50\n-#define JFFS2_ZLIB_PRIORITY      60\n-#define JFFS2_LZO_PRIORITY       80\n-\n+#define JFFS2_LZMA_PRIORITY      70\n+#define JFFS2_ZLIB_PRIORITY      80\n+#define JFFS2_LZO_PRIORITY       90\n \n #define JFFS2_RUBINMIPS_DISABLED /* RUBINs will be used only */\n #define JFFS2_DYNRUBIN_DISABLED  /*\t   for decompression */\n@@ -101,5 +101,9 @@ void jffs2_zlib_exit(void);\n int jffs2_lzo_init(void);\n void jffs2_lzo_exit(void);\n #endif\n+#ifdef CONFIG_JFFS2_LZMA\n+int jffs2_lzma_init(void);\n+void jffs2_lzma_exit(void);\n+#endif\n \n #endif /* __JFFS2_COMPR_H__ */\n--- /dev/null\n+++ b/fs/jffs2/compr_lzma.c\n@@ -0,0 +1,128 @@\n+/*\n+ * JFFS2 -- Journalling Flash File System, Version 2.\n+ *\n+ * For licensing information, see the file 'LICENCE' in this directory.\n+ *\n+ * JFFS2 wrapper to the LZMA C SDK\n+ *\n+ */\n+\n+#include <linux/lzma.h>\n+#include \"compr.h\"\n+\n+#ifdef __KERNEL__\n+\tstatic DEFINE_MUTEX(deflate_mutex);\n+#endif\n+\n+CLzmaEncHandle *p;\n+Byte propsEncoded[LZMA_PROPS_SIZE];\n+SizeT propsSize = sizeof(propsEncoded);\n+\n+STATIC void lzma_free_workspace(void)\n+{\n+\tLzmaEnc_Destroy(p, &lzma_alloc, &lzma_alloc);\n+}\n+\n+STATIC int INIT lzma_alloc_workspace(CLzmaEncProps *props)\n+{\n+\tif ((p = (CLzmaEncHandle *)LzmaEnc_Create(&lzma_alloc)) == NULL)\n+\t{\n+\t\tPRINT_ERROR(\"Failed to allocate lzma deflate workspace\\n\");\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\tif (LzmaEnc_SetProps(p, props) != SZ_OK)\n+\t{\n+\t\tlzma_free_workspace();\n+\t\treturn -1;\n+\t}\n+\n+\tif (LzmaEnc_WriteProperties(p, propsEncoded, &propsSize) != SZ_OK)\n+\t{\n+\t\tlzma_free_workspace();\n+\t\treturn -1;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+STATIC int jffs2_lzma_compress(unsigned char *data_in, unsigned char *cpage_out,\n+\t\t\t      uint32_t *sourcelen, uint32_t *dstlen)\n+{\n+\tSizeT compress_size = (SizeT)(*dstlen);\n+\tint ret;\n+\n+\t#ifdef __KERNEL__\n+\t\tmutex_lock(&deflate_mutex);\n+\t#endif\n+\n+\tret = LzmaEnc_MemEncode(p, cpage_out, &compress_size, data_in, *sourcelen,\n+\t\t0, NULL, &lzma_alloc, &lzma_alloc);\n+\n+\t#ifdef __KERNEL__\n+\t\tmutex_unlock(&deflate_mutex);\n+\t#endif\n+\n+\tif (ret != SZ_OK)\n+\t\treturn -1;\n+\n+\t*dstlen = (uint32_t)compress_size;\n+\n+\treturn 0;\n+}\n+\n+STATIC int jffs2_lzma_decompress(unsigned char *data_in, unsigned char *cpage_out,\n+\t\t\t\t uint32_t srclen, uint32_t destlen)\n+{\n+\tint ret;\n+\tSizeT dl = (SizeT)destlen;\n+\tSizeT sl = (SizeT)srclen;\n+\tELzmaStatus status;\n+\n+\tret = LzmaDecode(cpage_out, &dl, data_in, &sl, propsEncoded,\n+\t\tpropsSize, LZMA_FINISH_ANY, &status, &lzma_alloc);\n+\n+\tif (ret != SZ_OK || status == LZMA_STATUS_NOT_FINISHED || dl != (SizeT)destlen)\n+\t\treturn -1;\n+\n+\treturn 0;\n+}\n+\n+static struct jffs2_compressor jffs2_lzma_comp = {\n+\t.priority = JFFS2_LZMA_PRIORITY,\n+\t.name = \"lzma\",\n+\t.compr = JFFS2_COMPR_LZMA,\n+\t.compress = &jffs2_lzma_compress,\n+\t.decompress = &jffs2_lzma_decompress,\n+\t.disabled = 0,\n+};\n+\n+int INIT jffs2_lzma_init(void)\n+{\n+\tint ret;\n+\tCLzmaEncProps props;\n+\tLzmaEncProps_Init(&props);\n+\n+\tprops.dictSize = LZMA_BEST_DICT(0x2000);\n+\tprops.level = LZMA_BEST_LEVEL;\n+\tprops.lc = LZMA_BEST_LC;\n+\tprops.lp = LZMA_BEST_LP;\n+\tprops.pb = LZMA_BEST_PB;\n+\tprops.fb = LZMA_BEST_FB;\n+\n+\tret = lzma_alloc_workspace(&props);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\tret = jffs2_register_compressor(&jffs2_lzma_comp);\n+\tif (ret)\n+\t\tlzma_free_workspace();\n+\n+\treturn ret;\n+}\n+\n+void jffs2_lzma_exit(void)\n+{\n+\tjffs2_unregister_compressor(&jffs2_lzma_comp);\n+\tlzma_free_workspace();\n+}\n--- a/fs/jffs2/super.c\n+++ b/fs/jffs2/super.c\n@@ -374,14 +374,41 @@ static int __init init_jffs2_fs(void)\n \tBUILD_BUG_ON(sizeof(struct jffs2_raw_inode) != 68);\n \tBUILD_BUG_ON(sizeof(struct jffs2_raw_summary) != 32);\n \n-\tpr_info(\"version 2.2.\"\n+\tpr_info(\"version 2.2\"\n #ifdef CONFIG_JFFS2_FS_WRITEBUFFER\n \t       \" (NAND)\"\n #endif\n #ifdef CONFIG_JFFS2_SUMMARY\n-\t       \" (SUMMARY) \"\n+\t       \" (SUMMARY)\"\n #endif\n-\t       \" © 2001-2006 Red Hat, Inc.\\n\");\n+#ifdef CONFIG_JFFS2_ZLIB\n+\t       \" (ZLIB)\"\n+#endif\n+#ifdef CONFIG_JFFS2_LZO\n+\t       \" (LZO)\"\n+#endif\n+#ifdef CONFIG_JFFS2_LZMA\n+\t       \" (LZMA)\"\n+#endif\n+#ifdef CONFIG_JFFS2_RTIME\n+\t       \" (RTIME)\"\n+#endif\n+#ifdef CONFIG_JFFS2_RUBIN\n+\t       \" (RUBIN)\"\n+#endif\n+#ifdef  CONFIG_JFFS2_CMODE_NONE\n+\t       \" (CMODE_NONE)\"\n+#endif\n+#ifdef CONFIG_JFFS2_CMODE_PRIORITY\n+\t       \" (CMODE_PRIORITY)\"\n+#endif\n+#ifdef CONFIG_JFFS2_CMODE_SIZE\n+\t       \" (CMODE_SIZE)\"\n+#endif\n+#ifdef CONFIG_JFFS2_CMODE_FAVOURLZO\n+\t       \" (CMODE_FAVOURLZO)\"\n+#endif\n+\t       \" (c) 2001-2006 Red Hat, Inc.\\n\");\n \n \tjffs2_inode_cachep = kmem_cache_create(\"jffs2_i\",\n \t\t\t\t\t     sizeof(struct jffs2_inode_info),\n--- /dev/null\n+++ b/include/linux/lzma.h\n@@ -0,0 +1,62 @@\n+#ifndef __LZMA_H__\n+#define __LZMA_H__\n+\n+#ifdef __KERNEL__\n+\t#include <linux/kernel.h>\n+\t#include <linux/sched.h>\n+\t#include <linux/slab.h>\n+\t#include <linux/vmalloc.h>\n+\t#include <linux/init.h>\n+\t#define LZMA_MALLOC vmalloc\n+\t#define LZMA_FREE vfree\n+\t#define PRINT_ERROR(msg) printk(KERN_WARNING #msg)\n+\t#define INIT __init\n+\t#define STATIC static\n+#else\n+\t#include <stdint.h>\n+\t#include <stdlib.h>\n+\t#include <stdio.h>\n+\t#include <unistd.h>\n+\t#include <string.h>\n+\t#include <asm/types.h>\n+\t#include <errno.h>\n+\t#include <linux/jffs2.h>\n+\t#ifndef PAGE_SIZE\n+\t\textern int page_size;\n+\t\t#define PAGE_SIZE page_size\n+\t#endif\n+\t#define LZMA_MALLOC malloc\n+\t#define LZMA_FREE free\n+\t#define PRINT_ERROR(msg) fprintf(stderr, msg)\n+\t#define INIT\n+\t#define STATIC\n+#endif\n+\n+#include \"lzma/LzmaDec.h\"\n+#include \"lzma/LzmaEnc.h\"\n+\n+#define LZMA_BEST_LEVEL (9)\n+#define LZMA_BEST_LC    (0)\n+#define LZMA_BEST_LP    (0)\n+#define LZMA_BEST_PB    (0)\n+#define LZMA_BEST_FB  (273)\n+\n+#define LZMA_BEST_DICT(n) (((int)((n) / 2)) * 2)\n+\n+static void *p_lzma_malloc(void *p, size_t size)\n+{\n+\tif (size == 0)\n+\t\treturn NULL;\n+\n+\treturn LZMA_MALLOC(size);\n+}\n+\n+static void p_lzma_free(void *p, void *address)\n+{\n+\tif (address != NULL)\n+\t\tLZMA_FREE(address);\n+}\n+\n+static ISzAlloc lzma_alloc = { .Alloc = p_lzma_malloc, .Free = p_lzma_free };\n+\n+#endif\n--- /dev/null\n+++ b/include/linux/lzma/LzFind.h\n@@ -0,0 +1,115 @@\n+/* LzFind.h -- Match finder for LZ algorithms\n+2009-04-22 : Igor Pavlov : Public domain */\n+\n+#ifndef __LZ_FIND_H\n+#define __LZ_FIND_H\n+\n+#include \"Types.h\"\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+typedef UInt32 CLzRef;\n+\n+typedef struct _CMatchFinder\n+{\n+  Byte *buffer;\n+  UInt32 pos;\n+  UInt32 posLimit;\n+  UInt32 streamPos;\n+  UInt32 lenLimit;\n+\n+  UInt32 cyclicBufferPos;\n+  UInt32 cyclicBufferSize; /* it must be = (historySize + 1) */\n+\n+  UInt32 matchMaxLen;\n+  CLzRef *hash;\n+  CLzRef *son;\n+  UInt32 hashMask;\n+  UInt32 cutValue;\n+\n+  Byte *bufferBase;\n+  ISeqInStream *stream;\n+  int streamEndWasReached;\n+\n+  UInt32 blockSize;\n+  UInt32 keepSizeBefore;\n+  UInt32 keepSizeAfter;\n+\n+  UInt32 numHashBytes;\n+  int directInput;\n+  size_t directInputRem;\n+  int btMode;\n+  int bigHash;\n+  UInt32 historySize;\n+  UInt32 fixedHashSize;\n+  UInt32 hashSizeSum;\n+  UInt32 numSons;\n+  SRes result;\n+  UInt32 crc[256];\n+} CMatchFinder;\n+\n+#define Inline_MatchFinder_GetPointerToCurrentPos(p) ((p)->buffer)\n+#define Inline_MatchFinder_GetIndexByte(p, index) ((p)->buffer[(Int32)(index)])\n+\n+#define Inline_MatchFinder_GetNumAvailableBytes(p) ((p)->streamPos - (p)->pos)\n+\n+int MatchFinder_NeedMove(CMatchFinder *p);\n+Byte *MatchFinder_GetPointerToCurrentPos(CMatchFinder *p);\n+void MatchFinder_MoveBlock(CMatchFinder *p);\n+void MatchFinder_ReadIfRequired(CMatchFinder *p);\n+\n+void MatchFinder_Construct(CMatchFinder *p);\n+\n+/* Conditions:\n+     historySize <= 3 GB\n+     keepAddBufferBefore + matchMaxLen + keepAddBufferAfter < 511MB\n+*/\n+int MatchFinder_Create(CMatchFinder *p, UInt32 historySize,\n+    UInt32 keepAddBufferBefore, UInt32 matchMaxLen, UInt32 keepAddBufferAfter,\n+    ISzAlloc *alloc);\n+void MatchFinder_Free(CMatchFinder *p, ISzAlloc *alloc);\n+void MatchFinder_Normalize3(UInt32 subValue, CLzRef *items, UInt32 numItems);\n+void MatchFinder_ReduceOffsets(CMatchFinder *p, UInt32 subValue);\n+\n+UInt32 * GetMatchesSpec1(UInt32 lenLimit, UInt32 curMatch, UInt32 pos, const Byte *buffer, CLzRef *son,\n+    UInt32 _cyclicBufferPos, UInt32 _cyclicBufferSize, UInt32 _cutValue,\n+    UInt32 *distances, UInt32 maxLen);\n+\n+/*\n+Conditions:\n+  Mf_GetNumAvailableBytes_Func must be called before each Mf_GetMatchLen_Func.\n+  Mf_GetPointerToCurrentPos_Func's result must be used only before any other function\n+*/\n+\n+typedef void (*Mf_Init_Func)(void *object);\n+typedef Byte (*Mf_GetIndexByte_Func)(void *object, Int32 index);\n+typedef UInt32 (*Mf_GetNumAvailableBytes_Func)(void *object);\n+typedef const Byte * (*Mf_GetPointerToCurrentPos_Func)(void *object);\n+typedef UInt32 (*Mf_GetMatches_Func)(void *object, UInt32 *distances);\n+typedef void (*Mf_Skip_Func)(void *object, UInt32);\n+\n+typedef struct _IMatchFinder\n+{\n+  Mf_Init_Func Init;\n+  Mf_GetIndexByte_Func GetIndexByte;\n+  Mf_GetNumAvailableBytes_Func GetNumAvailableBytes;\n+  Mf_GetPointerToCurrentPos_Func GetPointerToCurrentPos;\n+  Mf_GetMatches_Func GetMatches;\n+  Mf_Skip_Func Skip;\n+} IMatchFinder;\n+\n+void MatchFinder_CreateVTable(CMatchFinder *p, IMatchFinder *vTable);\n+\n+void MatchFinder_Init(CMatchFinder *p);\n+UInt32 Bt3Zip_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances);\n+UInt32 Hc3Zip_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances);\n+void Bt3Zip_MatchFinder_Skip(CMatchFinder *p, UInt32 num);\n+void Hc3Zip_MatchFinder_Skip(CMatchFinder *p, UInt32 num);\n+\n+#ifdef __cplusplus\n+}\n+#endif\n+\n+#endif\n--- /dev/null\n+++ b/include/linux/lzma/LzHash.h\n@@ -0,0 +1,54 @@\n+/* LzHash.h -- HASH functions for LZ algorithms\n+2009-02-07 : Igor Pavlov : Public domain */\n+\n+#ifndef __LZ_HASH_H\n+#define __LZ_HASH_H\n+\n+#define kHash2Size (1 << 10)\n+#define kHash3Size (1 << 16)\n+#define kHash4Size (1 << 20)\n+\n+#define kFix3HashSize (kHash2Size)\n+#define kFix4HashSize (kHash2Size + kHash3Size)\n+#define kFix5HashSize (kHash2Size + kHash3Size + kHash4Size)\n+\n+#define HASH2_CALC hashValue = cur[0] | ((UInt32)cur[1] << 8);\n+\n+#define HASH3_CALC { \\\n+  UInt32 temp = p->crc[cur[0]] ^ cur[1]; \\\n+  hash2Value = temp & (kHash2Size - 1); \\\n+  hashValue = (temp ^ ((UInt32)cur[2] << 8)) & p->hashMask; }\n+\n+#define HASH4_CALC { \\\n+  UInt32 temp = p->crc[cur[0]] ^ cur[1]; \\\n+  hash2Value = temp & (kHash2Size - 1); \\\n+  hash3Value = (temp ^ ((UInt32)cur[2] << 8)) & (kHash3Size - 1); \\\n+  hashValue = (temp ^ ((UInt32)cur[2] << 8) ^ (p->crc[cur[3]] << 5)) & p->hashMask; }\n+\n+#define HASH5_CALC { \\\n+  UInt32 temp = p->crc[cur[0]] ^ cur[1]; \\\n+  hash2Value = temp & (kHash2Size - 1); \\\n+  hash3Value = (temp ^ ((UInt32)cur[2] << 8)) & (kHash3Size - 1); \\\n+  hash4Value = (temp ^ ((UInt32)cur[2] << 8) ^ (p->crc[cur[3]] << 5)); \\\n+  hashValue = (hash4Value ^ (p->crc[cur[4]] << 3)) & p->hashMask; \\\n+  hash4Value &= (kHash4Size - 1); }\n+\n+/* #define HASH_ZIP_CALC hashValue = ((cur[0] | ((UInt32)cur[1] << 8)) ^ p->crc[cur[2]]) & 0xFFFF; */\n+#define HASH_ZIP_CALC hashValue = ((cur[2] | ((UInt32)cur[0] << 8)) ^ p->crc[cur[1]]) & 0xFFFF;\n+\n+\n+#define MT_HASH2_CALC \\\n+  hash2Value = (p->crc[cur[0]] ^ cur[1]) & (kHash2Size - 1);\n+\n+#define MT_HASH3_CALC { \\\n+  UInt32 temp = p->crc[cur[0]] ^ cur[1]; \\\n+  hash2Value = temp & (kHash2Size - 1); \\\n+  hash3Value = (temp ^ ((UInt32)cur[2] << 8)) & (kHash3Size - 1); }\n+\n+#define MT_HASH4_CALC { \\\n+  UInt32 temp = p->crc[cur[0]] ^ cur[1]; \\\n+  hash2Value = temp & (kHash2Size - 1); \\\n+  hash3Value = (temp ^ ((UInt32)cur[2] << 8)) & (kHash3Size - 1); \\\n+  hash4Value = (temp ^ ((UInt32)cur[2] << 8) ^ (p->crc[cur[3]] << 5)) & (kHash4Size - 1); }\n+\n+#endif\n--- /dev/null\n+++ b/include/linux/lzma/LzmaDec.h\n@@ -0,0 +1,231 @@\n+/* LzmaDec.h -- LZMA Decoder\n+2009-02-07 : Igor Pavlov : Public domain */\n+\n+#ifndef __LZMA_DEC_H\n+#define __LZMA_DEC_H\n+\n+#include \"Types.h\"\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+/* #define _LZMA_PROB32 */\n+/* _LZMA_PROB32 can increase the speed on some CPUs,\n+   but memory usage for CLzmaDec::probs will be doubled in that case */\n+\n+#ifdef _LZMA_PROB32\n+#define CLzmaProb UInt32\n+#else\n+#define CLzmaProb UInt16\n+#endif\n+\n+\n+/* ---------- LZMA Properties ---------- */\n+\n+#define LZMA_PROPS_SIZE 5\n+\n+typedef struct _CLzmaProps\n+{\n+  unsigned lc, lp, pb;\n+  UInt32 dicSize;\n+} CLzmaProps;\n+\n+/* LzmaProps_Decode - decodes properties\n+Returns:\n+  SZ_OK\n+  SZ_ERROR_UNSUPPORTED - Unsupported properties\n+*/\n+\n+SRes LzmaProps_Decode(CLzmaProps *p, const Byte *data, unsigned size);\n+\n+\n+/* ---------- LZMA Decoder state ---------- */\n+\n+/* LZMA_REQUIRED_INPUT_MAX = number of required input bytes for worst case.\n+   Num bits = log2((2^11 / 31) ^ 22) + 26 < 134 + 26 = 160; */\n+\n+#define LZMA_REQUIRED_INPUT_MAX 20\n+\n+typedef struct\n+{\n+  CLzmaProps prop;\n+  CLzmaProb *probs;\n+  Byte *dic;\n+  const Byte *buf;\n+  UInt32 range, code;\n+  SizeT dicPos;\n+  SizeT dicBufSize;\n+  UInt32 processedPos;\n+  UInt32 checkDicSize;\n+  unsigned state;\n+  UInt32 reps[4];\n+  unsigned remainLen;\n+  int needFlush;\n+  int needInitState;\n+  UInt32 numProbs;\n+  unsigned tempBufSize;\n+  Byte tempBuf[LZMA_REQUIRED_INPUT_MAX];\n+} CLzmaDec;\n+\n+#define LzmaDec_Construct(p) { (p)->dic = 0; (p)->probs = 0; }\n+\n+void LzmaDec_Init(CLzmaDec *p);\n+\n+/* There are two types of LZMA streams:\n+     0) Stream with end mark. That end mark adds about 6 bytes to compressed size.\n+     1) Stream without end mark. You must know exact uncompressed size to decompress such stream. */\n+\n+typedef enum\n+{\n+  LZMA_FINISH_ANY,   /* finish at any point */\n+  LZMA_FINISH_END    /* block must be finished at the end */\n+} ELzmaFinishMode;\n+\n+/* ELzmaFinishMode has meaning only if the decoding reaches output limit !!!\n+\n+   You must use LZMA_FINISH_END, when you know that current output buffer\n+   covers last bytes of block. In other cases you must use LZMA_FINISH_ANY.\n+\n+   If LZMA decoder sees end marker before reaching output limit, it returns SZ_OK,\n+   and output value of destLen will be less than output buffer size limit.\n+   You can check status result also.\n+\n+   You can use multiple checks to test data integrity after full decompression:\n+     1) Check Result and \"status\" variable.\n+     2) Check that output(destLen) = uncompressedSize, if you know real uncompressedSize.\n+     3) Check that output(srcLen) = compressedSize, if you know real compressedSize.\n+        You must use correct finish mode in that case. */\n+\n+typedef enum\n+{\n+  LZMA_STATUS_NOT_SPECIFIED,               /* use main error code instead */\n+  LZMA_STATUS_FINISHED_WITH_MARK,          /* stream was finished with end mark. */\n+  LZMA_STATUS_NOT_FINISHED,                /* stream was not finished */\n+  LZMA_STATUS_NEEDS_MORE_INPUT,            /* you must provide more input bytes */\n+  LZMA_STATUS_MAYBE_FINISHED_WITHOUT_MARK  /* there is probability that stream was finished without end mark */\n+} ELzmaStatus;\n+\n+/* ELzmaStatus is used only as output value for function call */\n+\n+\n+/* ---------- Interfaces ---------- */\n+\n+/* There are 3 levels of interfaces:\n+     1) Dictionary Interface\n+     2) Buffer Interface\n+     3) One Call Interface\n+   You can select any of these interfaces, but don't mix functions from different\n+   groups for same object. */\n+\n+\n+/* There are two variants to allocate state for Dictionary Interface:\n+     1) LzmaDec_Allocate / LzmaDec_Free\n+     2) LzmaDec_AllocateProbs / LzmaDec_FreeProbs\n+   You can use variant 2, if you set dictionary buffer manually.\n+   For Buffer Interface you must always use variant 1.\n+\n+LzmaDec_Allocate* can return:\n+  SZ_OK\n+  SZ_ERROR_MEM         - Memory allocation error\n+  SZ_ERROR_UNSUPPORTED - Unsupported properties\n+*/\n+\n+SRes LzmaDec_AllocateProbs(CLzmaDec *p, const Byte *props, unsigned propsSize, ISzAlloc *alloc);\n+void LzmaDec_FreeProbs(CLzmaDec *p, ISzAlloc *alloc);\n+\n+SRes LzmaDec_Allocate(CLzmaDec *state, const Byte *prop, unsigned propsSize, ISzAlloc *alloc);\n+void LzmaDec_Free(CLzmaDec *state, ISzAlloc *alloc);\n+\n+/* ---------- Dictionary Interface ---------- */\n+\n+/* You can use it, if you want to eliminate the overhead for data copying from\n+   dictionary to some other external buffer.\n+   You must work with CLzmaDec variables directly in this interface.\n+\n+   STEPS:\n+     LzmaDec_Constr()\n+     LzmaDec_Allocate()\n+     for (each new stream)\n+     {\n+       LzmaDec_Init()\n+       while (it needs more decompression)\n+       {\n+         LzmaDec_DecodeToDic()\n+         use data from CLzmaDec::dic and update CLzmaDec::dicPos\n+       }\n+     }\n+     LzmaDec_Free()\n+*/\n+\n+/* LzmaDec_DecodeToDic\n+\n+   The decoding to internal dictionary buffer (CLzmaDec::dic).\n+   You must manually update CLzmaDec::dicPos, if it reaches CLzmaDec::dicBufSize !!!\n+\n+finishMode:\n+  It has meaning only if the decoding reaches output limit (dicLimit).\n+  LZMA_FINISH_ANY - Decode just dicLimit bytes.\n+  LZMA_FINISH_END - Stream must be finished after dicLimit.\n+\n+Returns:\n+  SZ_OK\n+    status:\n+      LZMA_STATUS_FINISHED_WITH_MARK\n+      LZMA_STATUS_NOT_FINISHED\n+      LZMA_STATUS_NEEDS_MORE_INPUT\n+      LZMA_STATUS_MAYBE_FINISHED_WITHOUT_MARK\n+  SZ_ERROR_DATA - Data error\n+*/\n+\n+SRes LzmaDec_DecodeToDic(CLzmaDec *p, SizeT dicLimit,\n+    const Byte *src, SizeT *srcLen, ELzmaFinishMode finishMode, ELzmaStatus *status);\n+\n+\n+/* ---------- Buffer Interface ---------- */\n+\n+/* It's zlib-like interface.\n+   See LzmaDec_DecodeToDic description for information about STEPS and return results,\n+   but you must use LzmaDec_DecodeToBuf instead of LzmaDec_DecodeToDic and you don't need\n+   to work with CLzmaDec variables manually.\n+\n+finishMode:\n+  It has meaning only if the decoding reaches output limit (*destLen).\n+  LZMA_FINISH_ANY - Decode just destLen bytes.\n+  LZMA_FINISH_END - Stream must be finished after (*destLen).\n+*/\n+\n+SRes LzmaDec_DecodeToBuf(CLzmaDec *p, Byte *dest, SizeT *destLen,\n+    const Byte *src, SizeT *srcLen, ELzmaFinishMode finishMode, ELzmaStatus *status);\n+\n+\n+/* ---------- One Call Interface ---------- */\n+\n+/* LzmaDecode\n+\n+finishMode:\n+  It has meaning only if the decoding reaches output limit (*destLen).\n+  LZMA_FINISH_ANY - Decode just destLen bytes.\n+  LZMA_FINISH_END - Stream must be finished after (*destLen).\n+\n+Returns:\n+  SZ_OK\n+    status:\n+      LZMA_STATUS_FINISHED_WITH_MARK\n+      LZMA_STATUS_NOT_FINISHED\n+      LZMA_STATUS_MAYBE_FINISHED_WITHOUT_MARK\n+  SZ_ERROR_DATA - Data error\n+  SZ_ERROR_MEM  - Memory allocation error\n+  SZ_ERROR_UNSUPPORTED - Unsupported properties\n+  SZ_ERROR_INPUT_EOF - It needs more bytes in input buffer (src).\n+*/\n+\n+SRes LzmaDecode(Byte *dest, SizeT *destLen, const Byte *src, SizeT *srcLen,\n+    const Byte *propData, unsigned propSize, ELzmaFinishMode finishMode,\n+    ELzmaStatus *status, ISzAlloc *alloc);\n+\n+#ifdef __cplusplus\n+}\n+#endif\n+\n+#endif\n--- /dev/null\n+++ b/include/linux/lzma/LzmaEnc.h\n@@ -0,0 +1,80 @@\n+/*  LzmaEnc.h -- LZMA Encoder\n+2009-02-07 : Igor Pavlov : Public domain */\n+\n+#ifndef __LZMA_ENC_H\n+#define __LZMA_ENC_H\n+\n+#include \"Types.h\"\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+#define LZMA_PROPS_SIZE 5\n+\n+typedef struct _CLzmaEncProps\n+{\n+  int level;       /*  0 <= level <= 9 */\n+  UInt32 dictSize; /* (1 << 12) <= dictSize <= (1 << 27) for 32-bit version\n+                      (1 << 12) <= dictSize <= (1 << 30) for 64-bit version\n+                       default = (1 << 24) */\n+  int lc;          /* 0 <= lc <= 8, default = 3 */\n+  int lp;          /* 0 <= lp <= 4, default = 0 */\n+  int pb;          /* 0 <= pb <= 4, default = 2 */\n+  int algo;        /* 0 - fast, 1 - normal, default = 1 */\n+  int fb;          /* 5 <= fb <= 273, default = 32 */\n+  int btMode;      /* 0 - hashChain Mode, 1 - binTree mode - normal, default = 1 */\n+  int numHashBytes; /* 2, 3 or 4, default = 4 */\n+  UInt32 mc;        /* 1 <= mc <= (1 << 30), default = 32 */\n+  unsigned writeEndMark;  /* 0 - do not write EOPM, 1 - write EOPM, default = 0 */\n+  int numThreads;  /* 1 or 2, default = 2 */\n+} CLzmaEncProps;\n+\n+void LzmaEncProps_Init(CLzmaEncProps *p);\n+void LzmaEncProps_Normalize(CLzmaEncProps *p);\n+UInt32 LzmaEncProps_GetDictSize(const CLzmaEncProps *props2);\n+\n+\n+/* ---------- CLzmaEncHandle Interface ---------- */\n+\n+/* LzmaEnc_* functions can return the following exit codes:\n+Returns:\n+  SZ_OK           - OK\n+  SZ_ERROR_MEM    - Memory allocation error\n+  SZ_ERROR_PARAM  - Incorrect paramater in props\n+  SZ_ERROR_WRITE  - Write callback error.\n+  SZ_ERROR_PROGRESS - some break from progress callback\n+  SZ_ERROR_THREAD - errors in multithreading functions (only for Mt version)\n+*/\n+\n+typedef void * CLzmaEncHandle;\n+\n+CLzmaEncHandle LzmaEnc_Create(ISzAlloc *alloc);\n+void LzmaEnc_Destroy(CLzmaEncHandle p, ISzAlloc *alloc, ISzAlloc *allocBig);\n+SRes LzmaEnc_SetProps(CLzmaEncHandle p, const CLzmaEncProps *props);\n+SRes LzmaEnc_WriteProperties(CLzmaEncHandle p, Byte *properties, SizeT *size);\n+SRes LzmaEnc_Encode(CLzmaEncHandle p, ISeqOutStream *outStream, ISeqInStream *inStream,\n+    ICompressProgress *progress, ISzAlloc *alloc, ISzAlloc *allocBig);\n+SRes LzmaEnc_MemEncode(CLzmaEncHandle p, Byte *dest, SizeT *destLen, const Byte *src, SizeT srcLen,\n+    int writeEndMark, ICompressProgress *progress, ISzAlloc *alloc, ISzAlloc *allocBig);\n+\n+/* ---------- One Call Interface ---------- */\n+\n+/* LzmaEncode\n+Return code:\n+  SZ_OK               - OK\n+  SZ_ERROR_MEM        - Memory allocation error\n+  SZ_ERROR_PARAM      - Incorrect paramater\n+  SZ_ERROR_OUTPUT_EOF - output buffer overflow\n+  SZ_ERROR_THREAD     - errors in multithreading functions (only for Mt version)\n+*/\n+\n+SRes LzmaEncode(Byte *dest, SizeT *destLen, const Byte *src, SizeT srcLen,\n+    const CLzmaEncProps *props, Byte *propsEncoded, SizeT *propsSize, int writeEndMark,\n+    ICompressProgress *progress, ISzAlloc *alloc, ISzAlloc *allocBig);\n+\n+#ifdef __cplusplus\n+}\n+#endif\n+\n+#endif\n--- /dev/null\n+++ b/include/linux/lzma/Types.h\n@@ -0,0 +1,226 @@\n+/* Types.h -- Basic types\n+2009-11-23 : Igor Pavlov : Public domain */\n+\n+#ifndef __7Z_TYPES_H\n+#define __7Z_TYPES_H\n+\n+#include <stddef.h>\n+\n+#ifdef _WIN32\n+#include <windows.h>\n+#endif\n+\n+#ifndef EXTERN_C_BEGIN\n+#ifdef __cplusplus\n+#define EXTERN_C_BEGIN extern \"C\" {\n+#define EXTERN_C_END }\n+#else\n+#define EXTERN_C_BEGIN\n+#define EXTERN_C_END\n+#endif\n+#endif\n+\n+EXTERN_C_BEGIN\n+\n+#define SZ_OK 0\n+\n+#define SZ_ERROR_DATA 1\n+#define SZ_ERROR_MEM 2\n+#define SZ_ERROR_CRC 3\n+#define SZ_ERROR_UNSUPPORTED 4\n+#define SZ_ERROR_PARAM 5\n+#define SZ_ERROR_INPUT_EOF 6\n+#define SZ_ERROR_OUTPUT_EOF 7\n+#define SZ_ERROR_READ 8\n+#define SZ_ERROR_WRITE 9\n+#define SZ_ERROR_PROGRESS 10\n+#define SZ_ERROR_FAIL 11\n+#define SZ_ERROR_THREAD 12\n+\n+#define SZ_ERROR_ARCHIVE 16\n+#define SZ_ERROR_NO_ARCHIVE 17\n+\n+typedef int SRes;\n+\n+#ifdef _WIN32\n+typedef DWORD WRes;\n+#else\n+typedef int WRes;\n+#endif\n+\n+#ifndef RINOK\n+#define RINOK(x) { int __result__ = (x); if (__result__ != 0) return __result__; }\n+#endif\n+\n+typedef unsigned char Byte;\n+typedef short Int16;\n+typedef unsigned short UInt16;\n+\n+#ifdef _LZMA_UINT32_IS_ULONG\n+typedef long Int32;\n+typedef unsigned long UInt32;\n+#else\n+typedef int Int32;\n+typedef unsigned int UInt32;\n+#endif\n+\n+#ifdef _SZ_NO_INT_64\n+\n+/* define _SZ_NO_INT_64, if your compiler doesn't support 64-bit integers.\n+   NOTES: Some code will work incorrectly in that case! */\n+\n+typedef long Int64;\n+typedef unsigned long UInt64;\n+\n+#else\n+\n+#if defined(_MSC_VER) || defined(__BORLANDC__)\n+typedef __int64 Int64;\n+typedef unsigned __int64 UInt64;\n+#else\n+typedef long long int Int64;\n+typedef unsigned long long int UInt64;\n+#endif\n+\n+#endif\n+\n+#ifdef _LZMA_NO_SYSTEM_SIZE_T\n+typedef UInt32 SizeT;\n+#else\n+typedef size_t SizeT;\n+#endif\n+\n+typedef int Bool;\n+#define True 1\n+#define False 0\n+\n+\n+#ifdef _WIN32\n+#define MY_STD_CALL __stdcall\n+#else\n+#define MY_STD_CALL\n+#endif\n+\n+#ifdef _MSC_VER\n+\n+#if _MSC_VER >= 1300\n+#define MY_NO_INLINE __declspec(noinline)\n+#else\n+#define MY_NO_INLINE\n+#endif\n+\n+#define MY_CDECL __cdecl\n+#define MY_FAST_CALL __fastcall\n+\n+#else\n+\n+#define MY_CDECL\n+#define MY_FAST_CALL\n+\n+#endif\n+\n+\n+/* The following interfaces use first parameter as pointer to structure */\n+\n+typedef struct\n+{\n+  SRes (*Read)(void *p, void *buf, size_t *size);\n+    /* if (input(*size) != 0 && output(*size) == 0) means end_of_stream.\n+       (output(*size) < input(*size)) is allowed */\n+} ISeqInStream;\n+\n+/* it can return SZ_ERROR_INPUT_EOF */\n+SRes SeqInStream_Read(ISeqInStream *stream, void *buf, size_t size);\n+SRes SeqInStream_Read2(ISeqInStream *stream, void *buf, size_t size, SRes errorType);\n+SRes SeqInStream_ReadByte(ISeqInStream *stream, Byte *buf);\n+\n+typedef struct\n+{\n+  size_t (*Write)(void *p, const void *buf, size_t size);\n+    /* Returns: result - the number of actually written bytes.\n+       (result < size) means error */\n+} ISeqOutStream;\n+\n+typedef enum\n+{\n+  SZ_SEEK_SET = 0,\n+  SZ_SEEK_CUR = 1,\n+  SZ_SEEK_END = 2\n+} ESzSeek;\n+\n+typedef struct\n+{\n+  SRes (*Read)(void *p, void *buf, size_t *size);  /* same as ISeqInStream::Read */\n+  SRes (*Seek)(void *p, Int64 *pos, ESzSeek origin);\n+} ISeekInStream;\n+\n+typedef struct\n+{\n+  SRes (*Look)(void *p, void **buf, size_t *size);\n+    /* if (input(*size) != 0 && output(*size) == 0) means end_of_stream.\n+       (output(*size) > input(*size)) is not allowed\n+       (output(*size) < input(*size)) is allowed */\n+  SRes (*Skip)(void *p, size_t offset);\n+    /* offset must be <= output(*size) of Look */\n+\n+  SRes (*Read)(void *p, void *buf, size_t *size);\n+    /* reads directly (without buffer). It's same as ISeqInStream::Read */\n+  SRes (*Seek)(void *p, Int64 *pos, ESzSeek origin);\n+} ILookInStream;\n+\n+SRes LookInStream_LookRead(ILookInStream *stream, void *buf, size_t *size);\n+SRes LookInStream_SeekTo(ILookInStream *stream, UInt64 offset);\n+\n+/* reads via ILookInStream::Read */\n+SRes LookInStream_Read2(ILookInStream *stream, void *buf, size_t size, SRes errorType);\n+SRes LookInStream_Read(ILookInStream *stream, void *buf, size_t size);\n+\n+#define LookToRead_BUF_SIZE (1 << 14)\n+\n+typedef struct\n+{\n+  ILookInStream s;\n+  ISeekInStream *realStream;\n+  size_t pos;\n+  size_t size;\n+  Byte buf[LookToRead_BUF_SIZE];\n+} CLookToRead;\n+\n+void LookToRead_CreateVTable(CLookToRead *p, int lookahead);\n+void LookToRead_Init(CLookToRead *p);\n+\n+typedef struct\n+{\n+  ISeqInStream s;\n+  ILookInStream *realStream;\n+} CSecToLook;\n+\n+void SecToLook_CreateVTable(CSecToLook *p);\n+\n+typedef struct\n+{\n+  ISeqInStream s;\n+  ILookInStream *realStream;\n+} CSecToRead;\n+\n+void SecToRead_CreateVTable(CSecToRead *p);\n+\n+typedef struct\n+{\n+  SRes (*Progress)(void *p, UInt64 inSize, UInt64 outSize);\n+    /* Returns: result. (result != SZ_OK) means break.\n+       Value (UInt64)(Int64)-1 for size means unknown value. */\n+} ICompressProgress;\n+\n+typedef struct\n+{\n+  void *(*Alloc)(void *p, size_t size);\n+  void (*Free)(void *p, void *address); /* address can be 0 */\n+} ISzAlloc;\n+\n+#define IAlloc_Alloc(p, size) (p)->Alloc((p), size)\n+#define IAlloc_Free(p, a) (p)->Free((p), a)\n+\n+EXTERN_C_END\n+\n+#endif\n--- a/include/uapi/linux/jffs2.h\n+++ b/include/uapi/linux/jffs2.h\n@@ -46,6 +46,7 @@\n #define JFFS2_COMPR_DYNRUBIN\t0x05\n #define JFFS2_COMPR_ZLIB\t0x06\n #define JFFS2_COMPR_LZO\t\t0x07\n+#define JFFS2_COMPR_LZMA\t0x08\n /* Compatibility flags. */\n #define JFFS2_COMPAT_MASK 0xc000      /* What do to if an unknown nodetype is found */\n #define JFFS2_NODE_ACCURATE 0x2000\n--- a/lib/Kconfig\n+++ b/lib/Kconfig\n@@ -315,6 +315,12 @@ config ZSTD_DECOMPRESS\n \n source \"lib/xz/Kconfig\"\n \n+config LZMA_COMPRESS\n+    tristate\n+\n+config LZMA_DECOMPRESS\n+    tristate\n+\n #\n # These all provide a common interface (hence the apparent duplication with\n # ZLIB_INFLATE; DECOMPRESS_GZIP is just a wrapper.)\n--- a/lib/Makefile\n+++ b/lib/Makefile\n@@ -136,6 +136,16 @@ CFLAGS_kobject.o += -DDEBUG\n CFLAGS_kobject_uevent.o += -DDEBUG\n endif\n \n+ifdef CONFIG_JFFS2_ZLIB\n+  CONFIG_ZLIB_INFLATE:=y\n+  CONFIG_ZLIB_DEFLATE:=y\n+endif\n+\n+ifdef CONFIG_JFFS2_LZMA\n+  CONFIG_LZMA_DECOMPRESS:=y\n+  CONFIG_LZMA_COMPRESS:=y\n+endif\n+\n obj-$(CONFIG_DEBUG_INFO_REDUCED) += debug_info.o\n CFLAGS_debug_info.o += $(call cc-option, -femit-struct-debug-detailed=any)\n \n@@ -191,6 +201,8 @@ obj-$(CONFIG_ZSTD_COMPRESS) += zstd/\n obj-$(CONFIG_ZSTD_DECOMPRESS) += zstd/\n obj-$(CONFIG_XZ_DEC) += xz/\n obj-$(CONFIG_RAID6_PQ) += raid6/\n+obj-$(CONFIG_LZMA_COMPRESS) += lzma/\n+obj-$(CONFIG_LZMA_DECOMPRESS) += lzma/\n \n lib-$(CONFIG_DECOMPRESS_GZIP) += decompress_inflate.o\n lib-$(CONFIG_DECOMPRESS_BZIP2) += decompress_bunzip2.o\n--- /dev/null\n+++ b/lib/lzma/LzFind.c\n@@ -0,0 +1,761 @@\n+/* LzFind.c -- Match finder for LZ algorithms\n+2009-04-22 : Igor Pavlov : Public domain */\n+\n+#include <string.h>\n+\n+#include \"LzFind.h\"\n+#include \"LzHash.h\"\n+\n+#define kEmptyHashValue 0\n+#define kMaxValForNormalize ((UInt32)0xFFFFFFFF)\n+#define kNormalizeStepMin (1 << 10) /* it must be power of 2 */\n+#define kNormalizeMask (~(kNormalizeStepMin - 1))\n+#define kMaxHistorySize ((UInt32)3 << 30)\n+\n+#define kStartMaxLen 3\n+\n+static void LzInWindow_Free(CMatchFinder *p, ISzAlloc *alloc)\n+{\n+  if (!p->directInput)\n+  {\n+    alloc->Free(alloc, p->bufferBase);\n+    p->bufferBase = 0;\n+  }\n+}\n+\n+/* keepSizeBefore + keepSizeAfter + keepSizeReserv must be < 4G) */\n+\n+static int LzInWindow_Create(CMatchFinder *p, UInt32 keepSizeReserv, ISzAlloc *alloc)\n+{\n+  UInt32 blockSize = p->keepSizeBefore + p->keepSizeAfter + keepSizeReserv;\n+  if (p->directInput)\n+  {\n+    p->blockSize = blockSize;\n+    return 1;\n+  }\n+  if (p->bufferBase == 0 || p->blockSize != blockSize)\n+  {\n+    LzInWindow_Free(p, alloc);\n+    p->blockSize = blockSize;\n+    p->bufferBase = (Byte *)alloc->Alloc(alloc, (size_t)blockSize);\n+  }\n+  return (p->bufferBase != 0);\n+}\n+\n+Byte *MatchFinder_GetPointerToCurrentPos(CMatchFinder *p) { return p->buffer; }\n+Byte MatchFinder_GetIndexByte(CMatchFinder *p, Int32 index) { return p->buffer[index]; }\n+\n+UInt32 MatchFinder_GetNumAvailableBytes(CMatchFinder *p) { return p->streamPos - p->pos; }\n+\n+void MatchFinder_ReduceOffsets(CMatchFinder *p, UInt32 subValue)\n+{\n+  p->posLimit -= subValue;\n+  p->pos -= subValue;\n+  p->streamPos -= subValue;\n+}\n+\n+static void MatchFinder_ReadBlock(CMatchFinder *p)\n+{\n+  if (p->streamEndWasReached || p->result != SZ_OK)\n+    return;\n+  if (p->directInput)\n+  {\n+    UInt32 curSize = 0xFFFFFFFF - p->streamPos;\n+    if (curSize > p->directInputRem)\n+      curSize = (UInt32)p->directInputRem;\n+    p->directInputRem -= curSize;\n+    p->streamPos += curSize;\n+    if (p->directInputRem == 0)\n+      p->streamEndWasReached = 1;\n+    return;\n+  }\n+  for (;;)\n+  {\n+    Byte *dest = p->buffer + (p->streamPos - p->pos);\n+    size_t size = (p->bufferBase + p->blockSize - dest);\n+    if (size == 0)\n+      return;\n+    p->result = p->stream->Read(p->stream, dest, &size);\n+    if (p->result != SZ_OK)\n+      return;\n+    if (size == 0)\n+    {\n+      p->streamEndWasReached = 1;\n+      return;\n+    }\n+    p->streamPos += (UInt32)size;\n+    if (p->streamPos - p->pos > p->keepSizeAfter)\n+      return;\n+  }\n+}\n+\n+void MatchFinder_MoveBlock(CMatchFinder *p)\n+{\n+  memmove(p->bufferBase,\n+    p->buffer - p->keepSizeBefore,\n+    (size_t)(p->streamPos - p->pos + p->keepSizeBefore));\n+  p->buffer = p->bufferBase + p->keepSizeBefore;\n+}\n+\n+int MatchFinder_NeedMove(CMatchFinder *p)\n+{\n+  if (p->directInput)\n+    return 0;\n+  /* if (p->streamEndWasReached) return 0; */\n+  return ((size_t)(p->bufferBase + p->blockSize - p->buffer) <= p->keepSizeAfter);\n+}\n+\n+void MatchFinder_ReadIfRequired(CMatchFinder *p)\n+{\n+  if (p->streamEndWasReached)\n+    return;\n+  if (p->keepSizeAfter >= p->streamPos - p->pos)\n+    MatchFinder_ReadBlock(p);\n+}\n+\n+static void MatchFinder_CheckAndMoveAndRead(CMatchFinder *p)\n+{\n+  if (MatchFinder_NeedMove(p))\n+    MatchFinder_MoveBlock(p);\n+  MatchFinder_ReadBlock(p);\n+}\n+\n+static void MatchFinder_SetDefaultSettings(CMatchFinder *p)\n+{\n+  p->cutValue = 32;\n+  p->btMode = 1;\n+  p->numHashBytes = 4;\n+  p->bigHash = 0;\n+}\n+\n+#define kCrcPoly 0xEDB88320\n+\n+void MatchFinder_Construct(CMatchFinder *p)\n+{\n+  UInt32 i;\n+  p->bufferBase = 0;\n+  p->directInput = 0;\n+  p->hash = 0;\n+  MatchFinder_SetDefaultSettings(p);\n+\n+  for (i = 0; i < 256; i++)\n+  {\n+    UInt32 r = i;\n+    int j;\n+    for (j = 0; j < 8; j++)\n+      r = (r >> 1) ^ (kCrcPoly & ~((r & 1) - 1));\n+    p->crc[i] = r;\n+  }\n+}\n+\n+static void MatchFinder_FreeThisClassMemory(CMatchFinder *p, ISzAlloc *alloc)\n+{\n+  alloc->Free(alloc, p->hash);\n+  p->hash = 0;\n+}\n+\n+void MatchFinder_Free(CMatchFinder *p, ISzAlloc *alloc)\n+{\n+  MatchFinder_FreeThisClassMemory(p, alloc);\n+  LzInWindow_Free(p, alloc);\n+}\n+\n+static CLzRef* AllocRefs(UInt32 num, ISzAlloc *alloc)\n+{\n+  size_t sizeInBytes = (size_t)num * sizeof(CLzRef);\n+  if (sizeInBytes / sizeof(CLzRef) != num)\n+    return 0;\n+  return (CLzRef *)alloc->Alloc(alloc, sizeInBytes);\n+}\n+\n+int MatchFinder_Create(CMatchFinder *p, UInt32 historySize,\n+    UInt32 keepAddBufferBefore, UInt32 matchMaxLen, UInt32 keepAddBufferAfter,\n+    ISzAlloc *alloc)\n+{\n+  UInt32 sizeReserv;\n+  if (historySize > kMaxHistorySize)\n+  {\n+    MatchFinder_Free(p, alloc);\n+    return 0;\n+  }\n+  sizeReserv = historySize >> 1;\n+  if (historySize > ((UInt32)2 << 30))\n+    sizeReserv = historySize >> 2;\n+  sizeReserv += (keepAddBufferBefore + matchMaxLen + keepAddBufferAfter) / 2 + (1 << 19);\n+\n+  p->keepSizeBefore = historySize + keepAddBufferBefore + 1;\n+  p->keepSizeAfter = matchMaxLen + keepAddBufferAfter;\n+  /* we need one additional byte, since we use MoveBlock after pos++ and before dictionary using */\n+  if (LzInWindow_Create(p, sizeReserv, alloc))\n+  {\n+    UInt32 newCyclicBufferSize = historySize + 1;\n+    UInt32 hs;\n+    p->matchMaxLen = matchMaxLen;\n+    {\n+      p->fixedHashSize = 0;\n+      if (p->numHashBytes == 2)\n+        hs = (1 << 16) - 1;\n+      else\n+      {\n+        hs = historySize - 1;\n+        hs |= (hs >> 1);\n+        hs |= (hs >> 2);\n+        hs |= (hs >> 4);\n+        hs |= (hs >> 8);\n+        hs >>= 1;\n+        hs |= 0xFFFF; /* don't change it! It's required for Deflate */\n+        if (hs > (1 << 24))\n+        {\n+          if (p->numHashBytes == 3)\n+            hs = (1 << 24) - 1;\n+          else\n+            hs >>= 1;\n+        }\n+      }\n+      p->hashMask = hs;\n+      hs++;\n+      if (p->numHashBytes > 2) p->fixedHashSize += kHash2Size;\n+      if (p->numHashBytes > 3) p->fixedHashSize += kHash3Size;\n+      if (p->numHashBytes > 4) p->fixedHashSize += kHash4Size;\n+      hs += p->fixedHashSize;\n+    }\n+\n+    {\n+      UInt32 prevSize = p->hashSizeSum + p->numSons;\n+      UInt32 newSize;\n+      p->historySize = historySize;\n+      p->hashSizeSum = hs;\n+      p->cyclicBufferSize = newCyclicBufferSize;\n+      p->numSons = (p->btMode ? newCyclicBufferSize * 2 : newCyclicBufferSize);\n+      newSize = p->hashSizeSum + p->numSons;\n+      if (p->hash != 0 && prevSize == newSize)\n+        return 1;\n+      MatchFinder_FreeThisClassMemory(p, alloc);\n+      p->hash = AllocRefs(newSize, alloc);\n+      if (p->hash != 0)\n+      {\n+        p->son = p->hash + p->hashSizeSum;\n+        return 1;\n+      }\n+    }\n+  }\n+  MatchFinder_Free(p, alloc);\n+  return 0;\n+}\n+\n+static void MatchFinder_SetLimits(CMatchFinder *p)\n+{\n+  UInt32 limit = kMaxValForNormalize - p->pos;\n+  UInt32 limit2 = p->cyclicBufferSize - p->cyclicBufferPos;\n+  if (limit2 < limit)\n+    limit = limit2;\n+  limit2 = p->streamPos - p->pos;\n+  if (limit2 <= p->keepSizeAfter)\n+  {\n+    if (limit2 > 0)\n+      limit2 = 1;\n+  }\n+  else\n+    limit2 -= p->keepSizeAfter;\n+  if (limit2 < limit)\n+    limit = limit2;\n+  {\n+    UInt32 lenLimit = p->streamPos - p->pos;\n+    if (lenLimit > p->matchMaxLen)\n+      lenLimit = p->matchMaxLen;\n+    p->lenLimit = lenLimit;\n+  }\n+  p->posLimit = p->pos + limit;\n+}\n+\n+void MatchFinder_Init(CMatchFinder *p)\n+{\n+  UInt32 i;\n+  for (i = 0; i < p->hashSizeSum; i++)\n+    p->hash[i] = kEmptyHashValue;\n+  p->cyclicBufferPos = 0;\n+  p->buffer = p->bufferBase;\n+  p->pos = p->streamPos = p->cyclicBufferSize;\n+  p->result = SZ_OK;\n+  p->streamEndWasReached = 0;\n+  MatchFinder_ReadBlock(p);\n+  MatchFinder_SetLimits(p);\n+}\n+\n+static UInt32 MatchFinder_GetSubValue(CMatchFinder *p)\n+{\n+  return (p->pos - p->historySize - 1) & kNormalizeMask;\n+}\n+\n+void MatchFinder_Normalize3(UInt32 subValue, CLzRef *items, UInt32 numItems)\n+{\n+  UInt32 i;\n+  for (i = 0; i < numItems; i++)\n+  {\n+    UInt32 value = items[i];\n+    if (value <= subValue)\n+      value = kEmptyHashValue;\n+    else\n+      value -= subValue;\n+    items[i] = value;\n+  }\n+}\n+\n+static void MatchFinder_Normalize(CMatchFinder *p)\n+{\n+  UInt32 subValue = MatchFinder_GetSubValue(p);\n+  MatchFinder_Normalize3(subValue, p->hash, p->hashSizeSum + p->numSons);\n+  MatchFinder_ReduceOffsets(p, subValue);\n+}\n+\n+static void MatchFinder_CheckLimits(CMatchFinder *p)\n+{\n+  if (p->pos == kMaxValForNormalize)\n+    MatchFinder_Normalize(p);\n+  if (!p->streamEndWasReached && p->keepSizeAfter == p->streamPos - p->pos)\n+    MatchFinder_CheckAndMoveAndRead(p);\n+  if (p->cyclicBufferPos == p->cyclicBufferSize)\n+    p->cyclicBufferPos = 0;\n+  MatchFinder_SetLimits(p);\n+}\n+\n+static UInt32 * Hc_GetMatchesSpec(UInt32 lenLimit, UInt32 curMatch, UInt32 pos, const Byte *cur, CLzRef *son,\n+    UInt32 _cyclicBufferPos, UInt32 _cyclicBufferSize, UInt32 cutValue,\n+    UInt32 *distances, UInt32 maxLen)\n+{\n+  son[_cyclicBufferPos] = curMatch;\n+  for (;;)\n+  {\n+    UInt32 delta = pos - curMatch;\n+    if (cutValue-- == 0 || delta >= _cyclicBufferSize)\n+      return distances;\n+    {\n+      const Byte *pb = cur - delta;\n+      curMatch = son[_cyclicBufferPos - delta + ((delta > _cyclicBufferPos) ? _cyclicBufferSize : 0)];\n+      if (pb[maxLen] == cur[maxLen] && *pb == *cur)\n+      {\n+        UInt32 len = 0;\n+        while (++len != lenLimit)\n+          if (pb[len] != cur[len])\n+            break;\n+        if (maxLen < len)\n+        {\n+          *distances++ = maxLen = len;\n+          *distances++ = delta - 1;\n+          if (len == lenLimit)\n+            return distances;\n+        }\n+      }\n+    }\n+  }\n+}\n+\n+UInt32 * GetMatchesSpec1(UInt32 lenLimit, UInt32 curMatch, UInt32 pos, const Byte *cur, CLzRef *son,\n+    UInt32 _cyclicBufferPos, UInt32 _cyclicBufferSize, UInt32 cutValue,\n+    UInt32 *distances, UInt32 maxLen)\n+{\n+  CLzRef *ptr0 = son + (_cyclicBufferPos << 1) + 1;\n+  CLzRef *ptr1 = son + (_cyclicBufferPos << 1);\n+  UInt32 len0 = 0, len1 = 0;\n+  for (;;)\n+  {\n+    UInt32 delta = pos - curMatch;\n+    if (cutValue-- == 0 || delta >= _cyclicBufferSize)\n+    {\n+      *ptr0 = *ptr1 = kEmptyHashValue;\n+      return distances;\n+    }\n+    {\n+      CLzRef *pair = son + ((_cyclicBufferPos - delta + ((delta > _cyclicBufferPos) ? _cyclicBufferSize : 0)) << 1);\n+      const Byte *pb = cur - delta;\n+      UInt32 len = (len0 < len1 ? len0 : len1);\n+      if (pb[len] == cur[len])\n+      {\n+        if (++len != lenLimit && pb[len] == cur[len])\n+          while (++len != lenLimit)\n+            if (pb[len] != cur[len])\n+              break;\n+        if (maxLen < len)\n+        {\n+          *distances++ = maxLen = len;\n+          *distances++ = delta - 1;\n+          if (len == lenLimit)\n+          {\n+            *ptr1 = pair[0];\n+            *ptr0 = pair[1];\n+            return distances;\n+          }\n+        }\n+      }\n+      if (pb[len] < cur[len])\n+      {\n+        *ptr1 = curMatch;\n+        ptr1 = pair + 1;\n+        curMatch = *ptr1;\n+        len1 = len;\n+      }\n+      else\n+      {\n+        *ptr0 = curMatch;\n+        ptr0 = pair;\n+        curMatch = *ptr0;\n+        len0 = len;\n+      }\n+    }\n+  }\n+}\n+\n+static void SkipMatchesSpec(UInt32 lenLimit, UInt32 curMatch, UInt32 pos, const Byte *cur, CLzRef *son,\n+    UInt32 _cyclicBufferPos, UInt32 _cyclicBufferSize, UInt32 cutValue)\n+{\n+  CLzRef *ptr0 = son + (_cyclicBufferPos << 1) + 1;\n+  CLzRef *ptr1 = son + (_cyclicBufferPos << 1);\n+  UInt32 len0 = 0, len1 = 0;\n+  for (;;)\n+  {\n+    UInt32 delta = pos - curMatch;\n+    if (cutValue-- == 0 || delta >= _cyclicBufferSize)\n+    {\n+      *ptr0 = *ptr1 = kEmptyHashValue;\n+      return;\n+    }\n+    {\n+      CLzRef *pair = son + ((_cyclicBufferPos - delta + ((delta > _cyclicBufferPos) ? _cyclicBufferSize : 0)) << 1);\n+      const Byte *pb = cur - delta;\n+      UInt32 len = (len0 < len1 ? len0 : len1);\n+      if (pb[len] == cur[len])\n+      {\n+        while (++len != lenLimit)\n+          if (pb[len] != cur[len])\n+            break;\n+        {\n+          if (len == lenLimit)\n+          {\n+            *ptr1 = pair[0];\n+            *ptr0 = pair[1];\n+            return;\n+          }\n+        }\n+      }\n+      if (pb[len] < cur[len])\n+      {\n+        *ptr1 = curMatch;\n+        ptr1 = pair + 1;\n+        curMatch = *ptr1;\n+        len1 = len;\n+      }\n+      else\n+      {\n+        *ptr0 = curMatch;\n+        ptr0 = pair;\n+        curMatch = *ptr0;\n+        len0 = len;\n+      }\n+    }\n+  }\n+}\n+\n+#define MOVE_POS \\\n+  ++p->cyclicBufferPos; \\\n+  p->buffer++; \\\n+  if (++p->pos == p->posLimit) MatchFinder_CheckLimits(p);\n+\n+#define MOVE_POS_RET MOVE_POS return offset;\n+\n+static void MatchFinder_MovePos(CMatchFinder *p) { MOVE_POS; }\n+\n+#define GET_MATCHES_HEADER2(minLen, ret_op) \\\n+  UInt32 lenLimit; UInt32 hashValue; const Byte *cur; UInt32 curMatch; \\\n+  lenLimit = p->lenLimit; { if (lenLimit < minLen) { MatchFinder_MovePos(p); ret_op; }} \\\n+  cur = p->buffer;\n+\n+#define GET_MATCHES_HEADER(minLen) GET_MATCHES_HEADER2(minLen, return 0)\n+#define SKIP_HEADER(minLen)        GET_MATCHES_HEADER2(minLen, continue)\n+\n+#define MF_PARAMS(p) p->pos, p->buffer, p->son, p->cyclicBufferPos, p->cyclicBufferSize, p->cutValue\n+\n+#define GET_MATCHES_FOOTER(offset, maxLen) \\\n+  offset = (UInt32)(GetMatchesSpec1(lenLimit, curMatch, MF_PARAMS(p), \\\n+  distances + offset, maxLen) - distances); MOVE_POS_RET;\n+\n+#define SKIP_FOOTER \\\n+  SkipMatchesSpec(lenLimit, curMatch, MF_PARAMS(p)); MOVE_POS;\n+\n+static UInt32 Bt2_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances)\n+{\n+  UInt32 offset;\n+  GET_MATCHES_HEADER(2)\n+  HASH2_CALC;\n+  curMatch = p->hash[hashValue];\n+  p->hash[hashValue] = p->pos;\n+  offset = 0;\n+  GET_MATCHES_FOOTER(offset, 1)\n+}\n+\n+UInt32 Bt3Zip_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances)\n+{\n+  UInt32 offset;\n+  GET_MATCHES_HEADER(3)\n+  HASH_ZIP_CALC;\n+  curMatch = p->hash[hashValue];\n+  p->hash[hashValue] = p->pos;\n+  offset = 0;\n+  GET_MATCHES_FOOTER(offset, 2)\n+}\n+\n+static UInt32 Bt3_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances)\n+{\n+  UInt32 hash2Value, delta2, maxLen, offset;\n+  GET_MATCHES_HEADER(3)\n+\n+  HASH3_CALC;\n+\n+  delta2 = p->pos - p->hash[hash2Value];\n+  curMatch = p->hash[kFix3HashSize + hashValue];\n+\n+  p->hash[hash2Value] =\n+  p->hash[kFix3HashSize + hashValue] = p->pos;\n+\n+\n+  maxLen = 2;\n+  offset = 0;\n+  if (delta2 < p->cyclicBufferSize && *(cur - delta2) == *cur)\n+  {\n+    for (; maxLen != lenLimit; maxLen++)\n+      if (cur[(ptrdiff_t)maxLen - delta2] != cur[maxLen])\n+        break;\n+    distances[0] = maxLen;\n+    distances[1] = delta2 - 1;\n+    offset = 2;\n+    if (maxLen == lenLimit)\n+    {\n+      SkipMatchesSpec(lenLimit, curMatch, MF_PARAMS(p));\n+      MOVE_POS_RET;\n+    }\n+  }\n+  GET_MATCHES_FOOTER(offset, maxLen)\n+}\n+\n+static UInt32 Bt4_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances)\n+{\n+  UInt32 hash2Value, hash3Value, delta2, delta3, maxLen, offset;\n+  GET_MATCHES_HEADER(4)\n+\n+  HASH4_CALC;\n+\n+  delta2 = p->pos - p->hash[                hash2Value];\n+  delta3 = p->pos - p->hash[kFix3HashSize + hash3Value];\n+  curMatch = p->hash[kFix4HashSize + hashValue];\n+\n+  p->hash[                hash2Value] =\n+  p->hash[kFix3HashSize + hash3Value] =\n+  p->hash[kFix4HashSize + hashValue] = p->pos;\n+\n+  maxLen = 1;\n+  offset = 0;\n+  if (delta2 < p->cyclicBufferSize && *(cur - delta2) == *cur)\n+  {\n+    distances[0] = maxLen = 2;\n+    distances[1] = delta2 - 1;\n+    offset = 2;\n+  }\n+  if (delta2 != delta3 && delta3 < p->cyclicBufferSize && *(cur - delta3) == *cur)\n+  {\n+    maxLen = 3;\n+    distances[offset + 1] = delta3 - 1;\n+    offset += 2;\n+    delta2 = delta3;\n+  }\n+  if (offset != 0)\n+  {\n+    for (; maxLen != lenLimit; maxLen++)\n+      if (cur[(ptrdiff_t)maxLen - delta2] != cur[maxLen])\n+        break;\n+    distances[offset - 2] = maxLen;\n+    if (maxLen == lenLimit)\n+    {\n+      SkipMatchesSpec(lenLimit, curMatch, MF_PARAMS(p));\n+      MOVE_POS_RET;\n+    }\n+  }\n+  if (maxLen < 3)\n+    maxLen = 3;\n+  GET_MATCHES_FOOTER(offset, maxLen)\n+}\n+\n+static UInt32 Hc4_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances)\n+{\n+  UInt32 hash2Value, hash3Value, delta2, delta3, maxLen, offset;\n+  GET_MATCHES_HEADER(4)\n+\n+  HASH4_CALC;\n+\n+  delta2 = p->pos - p->hash[                hash2Value];\n+  delta3 = p->pos - p->hash[kFix3HashSize + hash3Value];\n+  curMatch = p->hash[kFix4HashSize + hashValue];\n+\n+  p->hash[                hash2Value] =\n+  p->hash[kFix3HashSize + hash3Value] =\n+  p->hash[kFix4HashSize + hashValue] = p->pos;\n+\n+  maxLen = 1;\n+  offset = 0;\n+  if (delta2 < p->cyclicBufferSize && *(cur - delta2) == *cur)\n+  {\n+    distances[0] = maxLen = 2;\n+    distances[1] = delta2 - 1;\n+    offset = 2;\n+  }\n+  if (delta2 != delta3 && delta3 < p->cyclicBufferSize && *(cur - delta3) == *cur)\n+  {\n+    maxLen = 3;\n+    distances[offset + 1] = delta3 - 1;\n+    offset += 2;\n+    delta2 = delta3;\n+  }\n+  if (offset != 0)\n+  {\n+    for (; maxLen != lenLimit; maxLen++)\n+      if (cur[(ptrdiff_t)maxLen - delta2] != cur[maxLen])\n+        break;\n+    distances[offset - 2] = maxLen;\n+    if (maxLen == lenLimit)\n+    {\n+      p->son[p->cyclicBufferPos] = curMatch;\n+      MOVE_POS_RET;\n+    }\n+  }\n+  if (maxLen < 3)\n+    maxLen = 3;\n+  offset = (UInt32)(Hc_GetMatchesSpec(lenLimit, curMatch, MF_PARAMS(p),\n+    distances + offset, maxLen) - (distances));\n+  MOVE_POS_RET\n+}\n+\n+UInt32 Hc3Zip_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances)\n+{\n+  UInt32 offset;\n+  GET_MATCHES_HEADER(3)\n+  HASH_ZIP_CALC;\n+  curMatch = p->hash[hashValue];\n+  p->hash[hashValue] = p->pos;\n+  offset = (UInt32)(Hc_GetMatchesSpec(lenLimit, curMatch, MF_PARAMS(p),\n+    distances, 2) - (distances));\n+  MOVE_POS_RET\n+}\n+\n+static void Bt2_MatchFinder_Skip(CMatchFinder *p, UInt32 num)\n+{\n+  do\n+  {\n+    SKIP_HEADER(2)\n+    HASH2_CALC;\n+    curMatch = p->hash[hashValue];\n+    p->hash[hashValue] = p->pos;\n+    SKIP_FOOTER\n+  }\n+  while (--num != 0);\n+}\n+\n+void Bt3Zip_MatchFinder_Skip(CMatchFinder *p, UInt32 num)\n+{\n+  do\n+  {\n+    SKIP_HEADER(3)\n+    HASH_ZIP_CALC;\n+    curMatch = p->hash[hashValue];\n+    p->hash[hashValue] = p->pos;\n+    SKIP_FOOTER\n+  }\n+  while (--num != 0);\n+}\n+\n+static void Bt3_MatchFinder_Skip(CMatchFinder *p, UInt32 num)\n+{\n+  do\n+  {\n+    UInt32 hash2Value;\n+    SKIP_HEADER(3)\n+    HASH3_CALC;\n+    curMatch = p->hash[kFix3HashSize + hashValue];\n+    p->hash[hash2Value] =\n+    p->hash[kFix3HashSize + hashValue] = p->pos;\n+    SKIP_FOOTER\n+  }\n+  while (--num != 0);\n+}\n+\n+static void Bt4_MatchFinder_Skip(CMatchFinder *p, UInt32 num)\n+{\n+  do\n+  {\n+    UInt32 hash2Value, hash3Value;\n+    SKIP_HEADER(4)\n+    HASH4_CALC;\n+    curMatch = p->hash[kFix4HashSize + hashValue];\n+    p->hash[                hash2Value] =\n+    p->hash[kFix3HashSize + hash3Value] = p->pos;\n+    p->hash[kFix4HashSize + hashValue] = p->pos;\n+    SKIP_FOOTER\n+  }\n+  while (--num != 0);\n+}\n+\n+static void Hc4_MatchFinder_Skip(CMatchFinder *p, UInt32 num)\n+{\n+  do\n+  {\n+    UInt32 hash2Value, hash3Value;\n+    SKIP_HEADER(4)\n+    HASH4_CALC;\n+    curMatch = p->hash[kFix4HashSize + hashValue];\n+    p->hash[                hash2Value] =\n+    p->hash[kFix3HashSize + hash3Value] =\n+    p->hash[kFix4HashSize + hashValue] = p->pos;\n+    p->son[p->cyclicBufferPos] = curMatch;\n+    MOVE_POS\n+  }\n+  while (--num != 0);\n+}\n+\n+void Hc3Zip_MatchFinder_Skip(CMatchFinder *p, UInt32 num)\n+{\n+  do\n+  {\n+    SKIP_HEADER(3)\n+    HASH_ZIP_CALC;\n+    curMatch = p->hash[hashValue];\n+    p->hash[hashValue] = p->pos;\n+    p->son[p->cyclicBufferPos] = curMatch;\n+    MOVE_POS\n+  }\n+  while (--num != 0);\n+}\n+\n+void MatchFinder_CreateVTable(CMatchFinder *p, IMatchFinder *vTable)\n+{\n+  vTable->Init = (Mf_Init_Func)MatchFinder_Init;\n+  vTable->GetIndexByte = (Mf_GetIndexByte_Func)MatchFinder_GetIndexByte;\n+  vTable->GetNumAvailableBytes = (Mf_GetNumAvailableBytes_Func)MatchFinder_GetNumAvailableBytes;\n+  vTable->GetPointerToCurrentPos = (Mf_GetPointerToCurrentPos_Func)MatchFinder_GetPointerToCurrentPos;\n+  if (!p->btMode)\n+  {\n+    vTable->GetMatches = (Mf_GetMatches_Func)Hc4_MatchFinder_GetMatches;\n+    vTable->Skip = (Mf_Skip_Func)Hc4_MatchFinder_Skip;\n+  }\n+  else if (p->numHashBytes == 2)\n+  {\n+    vTable->GetMatches = (Mf_GetMatches_Func)Bt2_MatchFinder_GetMatches;\n+    vTable->Skip = (Mf_Skip_Func)Bt2_MatchFinder_Skip;\n+  }\n+  else if (p->numHashBytes == 3)\n+  {\n+    vTable->GetMatches = (Mf_GetMatches_Func)Bt3_MatchFinder_GetMatches;\n+    vTable->Skip = (Mf_Skip_Func)Bt3_MatchFinder_Skip;\n+  }\n+  else\n+  {\n+    vTable->GetMatches = (Mf_GetMatches_Func)Bt4_MatchFinder_GetMatches;\n+    vTable->Skip = (Mf_Skip_Func)Bt4_MatchFinder_Skip;\n+  }\n+}\n--- /dev/null\n+++ b/lib/lzma/LzmaDec.c\n@@ -0,0 +1,999 @@\n+/* LzmaDec.c -- LZMA Decoder\n+2009-09-20 : Igor Pavlov : Public domain */\n+\n+#include \"LzmaDec.h\"\n+\n+#include <string.h>\n+\n+#define kNumTopBits 24\n+#define kTopValue ((UInt32)1 << kNumTopBits)\n+\n+#define kNumBitModelTotalBits 11\n+#define kBitModelTotal (1 << kNumBitModelTotalBits)\n+#define kNumMoveBits 5\n+\n+#define RC_INIT_SIZE 5\n+\n+#define NORMALIZE if (range < kTopValue) { range <<= 8; code = (code << 8) | (*buf++); }\n+\n+#define IF_BIT_0(p) ttt = *(p); NORMALIZE; bound = (range >> kNumBitModelTotalBits) * ttt; if (code < bound)\n+#define UPDATE_0(p) range = bound; *(p) = (CLzmaProb)(ttt + ((kBitModelTotal - ttt) >> kNumMoveBits));\n+#define UPDATE_1(p) range -= bound; code -= bound; *(p) = (CLzmaProb)(ttt - (ttt >> kNumMoveBits));\n+#define GET_BIT2(p, i, A0, A1) IF_BIT_0(p) \\\n+  { UPDATE_0(p); i = (i + i); A0; } else \\\n+  { UPDATE_1(p); i = (i + i) + 1; A1; }\n+#define GET_BIT(p, i) GET_BIT2(p, i, ; , ;)\n+\n+#define TREE_GET_BIT(probs, i) { GET_BIT((probs + i), i); }\n+#define TREE_DECODE(probs, limit, i) \\\n+  { i = 1; do { TREE_GET_BIT(probs, i); } while (i < limit); i -= limit; }\n+\n+/* #define _LZMA_SIZE_OPT */\n+\n+#ifdef _LZMA_SIZE_OPT\n+#define TREE_6_DECODE(probs, i) TREE_DECODE(probs, (1 << 6), i)\n+#else\n+#define TREE_6_DECODE(probs, i) \\\n+  { i = 1; \\\n+  TREE_GET_BIT(probs, i); \\\n+  TREE_GET_BIT(probs, i); \\\n+  TREE_GET_BIT(probs, i); \\\n+  TREE_GET_BIT(probs, i); \\\n+  TREE_GET_BIT(probs, i); \\\n+  TREE_GET_BIT(probs, i); \\\n+  i -= 0x40; }\n+#endif\n+\n+#define NORMALIZE_CHECK if (range < kTopValue) { if (buf >= bufLimit) return DUMMY_ERROR; range <<= 8; code = (code << 8) | (*buf++); }\n+\n+#define IF_BIT_0_CHECK(p) ttt = *(p); NORMALIZE_CHECK; bound = (range >> kNumBitModelTotalBits) * ttt; if (code < bound)\n+#define UPDATE_0_CHECK range = bound;\n+#define UPDATE_1_CHECK range -= bound; code -= bound;\n+#define GET_BIT2_CHECK(p, i, A0, A1) IF_BIT_0_CHECK(p) \\\n+  { UPDATE_0_CHECK; i = (i + i); A0; } else \\\n+  { UPDATE_1_CHECK; i = (i + i) + 1; A1; }\n+#define GET_BIT_CHECK(p, i) GET_BIT2_CHECK(p, i, ; , ;)\n+#define TREE_DECODE_CHECK(probs, limit, i) \\\n+  { i = 1; do { GET_BIT_CHECK(probs + i, i) } while (i < limit); i -= limit; }\n+\n+\n+#define kNumPosBitsMax 4\n+#define kNumPosStatesMax (1 << kNumPosBitsMax)\n+\n+#define kLenNumLowBits 3\n+#define kLenNumLowSymbols (1 << kLenNumLowBits)\n+#define kLenNumMidBits 3\n+#define kLenNumMidSymbols (1 << kLenNumMidBits)\n+#define kLenNumHighBits 8\n+#define kLenNumHighSymbols (1 << kLenNumHighBits)\n+\n+#define LenChoice 0\n+#define LenChoice2 (LenChoice + 1)\n+#define LenLow (LenChoice2 + 1)\n+#define LenMid (LenLow + (kNumPosStatesMax << kLenNumLowBits))\n+#define LenHigh (LenMid + (kNumPosStatesMax << kLenNumMidBits))\n+#define kNumLenProbs (LenHigh + kLenNumHighSymbols)\n+\n+\n+#define kNumStates 12\n+#define kNumLitStates 7\n+\n+#define kStartPosModelIndex 4\n+#define kEndPosModelIndex 14\n+#define kNumFullDistances (1 << (kEndPosModelIndex >> 1))\n+\n+#define kNumPosSlotBits 6\n+#define kNumLenToPosStates 4\n+\n+#define kNumAlignBits 4\n+#define kAlignTableSize (1 << kNumAlignBits)\n+\n+#define kMatchMinLen 2\n+#define kMatchSpecLenStart (kMatchMinLen + kLenNumLowSymbols + kLenNumMidSymbols + kLenNumHighSymbols)\n+\n+#define IsMatch 0\n+#define IsRep (IsMatch + (kNumStates << kNumPosBitsMax))\n+#define IsRepG0 (IsRep + kNumStates)\n+#define IsRepG1 (IsRepG0 + kNumStates)\n+#define IsRepG2 (IsRepG1 + kNumStates)\n+#define IsRep0Long (IsRepG2 + kNumStates)\n+#define PosSlot (IsRep0Long + (kNumStates << kNumPosBitsMax))\n+#define SpecPos (PosSlot + (kNumLenToPosStates << kNumPosSlotBits))\n+#define Align (SpecPos + kNumFullDistances - kEndPosModelIndex)\n+#define LenCoder (Align + kAlignTableSize)\n+#define RepLenCoder (LenCoder + kNumLenProbs)\n+#define Literal (RepLenCoder + kNumLenProbs)\n+\n+#define LZMA_BASE_SIZE 1846\n+#define LZMA_LIT_SIZE 768\n+\n+#define LzmaProps_GetNumProbs(p) ((UInt32)LZMA_BASE_SIZE + (LZMA_LIT_SIZE << ((p)->lc + (p)->lp)))\n+\n+#if Literal != LZMA_BASE_SIZE\n+StopCompilingDueBUG\n+#endif\n+\n+#define LZMA_DIC_MIN (1 << 12)\n+\n+/* First LZMA-symbol is always decoded.\n+And it decodes new LZMA-symbols while (buf < bufLimit), but \"buf\" is without last normalization\n+Out:\n+  Result:\n+    SZ_OK - OK\n+    SZ_ERROR_DATA - Error\n+  p->remainLen:\n+    < kMatchSpecLenStart : normal remain\n+    = kMatchSpecLenStart : finished\n+    = kMatchSpecLenStart + 1 : Flush marker\n+    = kMatchSpecLenStart + 2 : State Init Marker\n+*/\n+\n+static int MY_FAST_CALL LzmaDec_DecodeReal(CLzmaDec *p, SizeT limit, const Byte *bufLimit)\n+{\n+  CLzmaProb *probs = p->probs;\n+\n+  unsigned state = p->state;\n+  UInt32 rep0 = p->reps[0], rep1 = p->reps[1], rep2 = p->reps[2], rep3 = p->reps[3];\n+  unsigned pbMask = ((unsigned)1 << (p->prop.pb)) - 1;\n+  unsigned lpMask = ((unsigned)1 << (p->prop.lp)) - 1;\n+  unsigned lc = p->prop.lc;\n+\n+  Byte *dic = p->dic;\n+  SizeT dicBufSize = p->dicBufSize;\n+  SizeT dicPos = p->dicPos;\n+\n+  UInt32 processedPos = p->processedPos;\n+  UInt32 checkDicSize = p->checkDicSize;\n+  unsigned len = 0;\n+\n+  const Byte *buf = p->buf;\n+  UInt32 range = p->range;\n+  UInt32 code = p->code;\n+\n+  do\n+  {\n+    CLzmaProb *prob;\n+    UInt32 bound;\n+    unsigned ttt;\n+    unsigned posState = processedPos & pbMask;\n+\n+    prob = probs + IsMatch + (state << kNumPosBitsMax) + posState;\n+    IF_BIT_0(prob)\n+    {\n+      unsigned symbol;\n+      UPDATE_0(prob);\n+      prob = probs + Literal;\n+      if (checkDicSize != 0 || processedPos != 0)\n+        prob += (LZMA_LIT_SIZE * (((processedPos & lpMask) << lc) +\n+        (dic[(dicPos == 0 ? dicBufSize : dicPos) - 1] >> (8 - lc))));\n+\n+      if (state < kNumLitStates)\n+      {\n+        state -= (state < 4) ? state : 3;\n+        symbol = 1;\n+        do { GET_BIT(prob + symbol, symbol) } while (symbol < 0x100);\n+      }\n+      else\n+      {\n+        unsigned matchByte = p->dic[(dicPos - rep0) + ((dicPos < rep0) ? dicBufSize : 0)];\n+        unsigned offs = 0x100;\n+        state -= (state < 10) ? 3 : 6;\n+        symbol = 1;\n+        do\n+        {\n+          unsigned bit;\n+          CLzmaProb *probLit;\n+          matchByte <<= 1;\n+          bit = (matchByte & offs);\n+          probLit = prob + offs + bit + symbol;\n+          GET_BIT2(probLit, symbol, offs &= ~bit, offs &= bit)\n+        }\n+        while (symbol < 0x100);\n+      }\n+      dic[dicPos++] = (Byte)symbol;\n+      processedPos++;\n+      continue;\n+    }\n+    else\n+    {\n+      UPDATE_1(prob);\n+      prob = probs + IsRep + state;\n+      IF_BIT_0(prob)\n+      {\n+        UPDATE_0(prob);\n+        state += kNumStates;\n+        prob = probs + LenCoder;\n+      }\n+      else\n+      {\n+        UPDATE_1(prob);\n+        if (checkDicSize == 0 && processedPos == 0)\n+          return SZ_ERROR_DATA;\n+        prob = probs + IsRepG0 + state;\n+        IF_BIT_0(prob)\n+        {\n+          UPDATE_0(prob);\n+          prob = probs + IsRep0Long + (state << kNumPosBitsMax) + posState;\n+          IF_BIT_0(prob)\n+          {\n+            UPDATE_0(prob);\n+            dic[dicPos] = dic[(dicPos - rep0) + ((dicPos < rep0) ? dicBufSize : 0)];\n+            dicPos++;\n+            processedPos++;\n+            state = state < kNumLitStates ? 9 : 11;\n+            continue;\n+          }\n+          UPDATE_1(prob);\n+        }\n+        else\n+        {\n+          UInt32 distance;\n+          UPDATE_1(prob);\n+          prob = probs + IsRepG1 + state;\n+          IF_BIT_0(prob)\n+          {\n+            UPDATE_0(prob);\n+            distance = rep1;\n+          }\n+          else\n+          {\n+            UPDATE_1(prob);\n+            prob = probs + IsRepG2 + state;\n+            IF_BIT_0(prob)\n+            {\n+              UPDATE_0(prob);\n+              distance = rep2;\n+            }\n+            else\n+            {\n+              UPDATE_1(prob);\n+              distance = rep3;\n+              rep3 = rep2;\n+            }\n+            rep2 = rep1;\n+          }\n+          rep1 = rep0;\n+          rep0 = distance;\n+        }\n+        state = state < kNumLitStates ? 8 : 11;\n+        prob = probs + RepLenCoder;\n+      }\n+      {\n+        unsigned limit, offset;\n+        CLzmaProb *probLen = prob + LenChoice;\n+        IF_BIT_0(probLen)\n+        {\n+          UPDATE_0(probLen);\n+          probLen = prob + LenLow + (posState << kLenNumLowBits);\n+          offset = 0;\n+          limit = (1 << kLenNumLowBits);\n+        }\n+        else\n+        {\n+          UPDATE_1(probLen);\n+          probLen = prob + LenChoice2;\n+          IF_BIT_0(probLen)\n+          {\n+            UPDATE_0(probLen);\n+            probLen = prob + LenMid + (posState << kLenNumMidBits);\n+            offset = kLenNumLowSymbols;\n+            limit = (1 << kLenNumMidBits);\n+          }\n+          else\n+          {\n+            UPDATE_1(probLen);\n+            probLen = prob + LenHigh;\n+            offset = kLenNumLowSymbols + kLenNumMidSymbols;\n+            limit = (1 << kLenNumHighBits);\n+          }\n+        }\n+        TREE_DECODE(probLen, limit, len);\n+        len += offset;\n+      }\n+\n+      if (state >= kNumStates)\n+      {\n+        UInt32 distance;\n+        prob = probs + PosSlot +\n+            ((len < kNumLenToPosStates ? len : kNumLenToPosStates - 1) << kNumPosSlotBits);\n+        TREE_6_DECODE(prob, distance);\n+        if (distance >= kStartPosModelIndex)\n+        {\n+          unsigned posSlot = (unsigned)distance;\n+          int numDirectBits = (int)(((distance >> 1) - 1));\n+          distance = (2 | (distance & 1));\n+          if (posSlot < kEndPosModelIndex)\n+          {\n+            distance <<= numDirectBits;\n+            prob = probs + SpecPos + distance - posSlot - 1;\n+            {\n+              UInt32 mask = 1;\n+              unsigned i = 1;\n+              do\n+              {\n+                GET_BIT2(prob + i, i, ; , distance |= mask);\n+                mask <<= 1;\n+              }\n+              while (--numDirectBits != 0);\n+            }\n+          }\n+          else\n+          {\n+            numDirectBits -= kNumAlignBits;\n+            do\n+            {\n+              NORMALIZE\n+              range >>= 1;\n+\n+              {\n+                UInt32 t;\n+                code -= range;\n+                t = (0 - ((UInt32)code >> 31)); /* (UInt32)((Int32)code >> 31) */\n+                distance = (distance << 1) + (t + 1);\n+                code += range & t;\n+              }\n+              /*\n+              distance <<= 1;\n+              if (code >= range)\n+              {\n+                code -= range;\n+                distance |= 1;\n+              }\n+              */\n+            }\n+            while (--numDirectBits != 0);\n+            prob = probs + Align;\n+            distance <<= kNumAlignBits;\n+            {\n+              unsigned i = 1;\n+              GET_BIT2(prob + i, i, ; , distance |= 1);\n+              GET_BIT2(prob + i, i, ; , distance |= 2);\n+              GET_BIT2(prob + i, i, ; , distance |= 4);\n+              GET_BIT2(prob + i, i, ; , distance |= 8);\n+            }\n+            if (distance == (UInt32)0xFFFFFFFF)\n+            {\n+              len += kMatchSpecLenStart;\n+              state -= kNumStates;\n+              break;\n+            }\n+          }\n+        }\n+        rep3 = rep2;\n+        rep2 = rep1;\n+        rep1 = rep0;\n+        rep0 = distance + 1;\n+        if (checkDicSize == 0)\n+        {\n+          if (distance >= processedPos)\n+            return SZ_ERROR_DATA;\n+        }\n+        else if (distance >= checkDicSize)\n+          return SZ_ERROR_DATA;\n+        state = (state < kNumStates + kNumLitStates) ? kNumLitStates : kNumLitStates + 3;\n+      }\n+\n+      len += kMatchMinLen;\n+\n+      if (limit == dicPos)\n+        return SZ_ERROR_DATA;\n+      {\n+        SizeT rem = limit - dicPos;\n+        unsigned curLen = ((rem < len) ? (unsigned)rem : len);\n+        SizeT pos = (dicPos - rep0) + ((dicPos < rep0) ? dicBufSize : 0);\n+\n+        processedPos += curLen;\n+\n+        len -= curLen;\n+        if (pos + curLen <= dicBufSize)\n+        {\n+          Byte *dest = dic + dicPos;\n+          ptrdiff_t src = (ptrdiff_t)pos - (ptrdiff_t)dicPos;\n+          const Byte *lim = dest + curLen;\n+          dicPos += curLen;\n+          do\n+            *(dest) = (Byte)*(dest + src);\n+          while (++dest != lim);\n+        }\n+        else\n+        {\n+          do\n+          {\n+            dic[dicPos++] = dic[pos];\n+            if (++pos == dicBufSize)\n+              pos = 0;\n+          }\n+          while (--curLen != 0);\n+        }\n+      }\n+    }\n+  }\n+  while (dicPos < limit && buf < bufLimit);\n+  NORMALIZE;\n+  p->buf = buf;\n+  p->range = range;\n+  p->code = code;\n+  p->remainLen = len;\n+  p->dicPos = dicPos;\n+  p->processedPos = processedPos;\n+  p->reps[0] = rep0;\n+  p->reps[1] = rep1;\n+  p->reps[2] = rep2;\n+  p->reps[3] = rep3;\n+  p->state = state;\n+\n+  return SZ_OK;\n+}\n+\n+static void MY_FAST_CALL LzmaDec_WriteRem(CLzmaDec *p, SizeT limit)\n+{\n+  if (p->remainLen != 0 && p->remainLen < kMatchSpecLenStart)\n+  {\n+    Byte *dic = p->dic;\n+    SizeT dicPos = p->dicPos;\n+    SizeT dicBufSize = p->dicBufSize;\n+    unsigned len = p->remainLen;\n+    UInt32 rep0 = p->reps[0];\n+    if (limit - dicPos < len)\n+      len = (unsigned)(limit - dicPos);\n+\n+    if (p->checkDicSize == 0 && p->prop.dicSize - p->processedPos <= len)\n+      p->checkDicSize = p->prop.dicSize;\n+\n+    p->processedPos += len;\n+    p->remainLen -= len;\n+    while (len-- != 0)\n+    {\n+      dic[dicPos] = dic[(dicPos - rep0) + ((dicPos < rep0) ? dicBufSize : 0)];\n+      dicPos++;\n+    }\n+    p->dicPos = dicPos;\n+  }\n+}\n+\n+static int MY_FAST_CALL LzmaDec_DecodeReal2(CLzmaDec *p, SizeT limit, const Byte *bufLimit)\n+{\n+  do\n+  {\n+    SizeT limit2 = limit;\n+    if (p->checkDicSize == 0)\n+    {\n+      UInt32 rem = p->prop.dicSize - p->processedPos;\n+      if (limit - p->dicPos > rem)\n+        limit2 = p->dicPos + rem;\n+    }\n+    RINOK(LzmaDec_DecodeReal(p, limit2, bufLimit));\n+    if (p->processedPos >= p->prop.dicSize)\n+      p->checkDicSize = p->prop.dicSize;\n+    LzmaDec_WriteRem(p, limit);\n+  }\n+  while (p->dicPos < limit && p->buf < bufLimit && p->remainLen < kMatchSpecLenStart);\n+\n+  if (p->remainLen > kMatchSpecLenStart)\n+  {\n+    p->remainLen = kMatchSpecLenStart;\n+  }\n+  return 0;\n+}\n+\n+typedef enum\n+{\n+  DUMMY_ERROR, /* unexpected end of input stream */\n+  DUMMY_LIT,\n+  DUMMY_MATCH,\n+  DUMMY_REP\n+} ELzmaDummy;\n+\n+static ELzmaDummy LzmaDec_TryDummy(const CLzmaDec *p, const Byte *buf, SizeT inSize)\n+{\n+  UInt32 range = p->range;\n+  UInt32 code = p->code;\n+  const Byte *bufLimit = buf + inSize;\n+  CLzmaProb *probs = p->probs;\n+  unsigned state = p->state;\n+  ELzmaDummy res;\n+\n+  {\n+    CLzmaProb *prob;\n+    UInt32 bound;\n+    unsigned ttt;\n+    unsigned posState = (p->processedPos) & ((1 << p->prop.pb) - 1);\n+\n+    prob = probs + IsMatch + (state << kNumPosBitsMax) + posState;\n+    IF_BIT_0_CHECK(prob)\n+    {\n+      UPDATE_0_CHECK\n+\n+      /* if (bufLimit - buf >= 7) return DUMMY_LIT; */\n+\n+      prob = probs + Literal;\n+      if (p->checkDicSize != 0 || p->processedPos != 0)\n+        prob += (LZMA_LIT_SIZE *\n+          ((((p->processedPos) & ((1 << (p->prop.lp)) - 1)) << p->prop.lc) +\n+          (p->dic[(p->dicPos == 0 ? p->dicBufSize : p->dicPos) - 1] >> (8 - p->prop.lc))));\n+\n+      if (state < kNumLitStates)\n+      {\n+        unsigned symbol = 1;\n+        do { GET_BIT_CHECK(prob + symbol, symbol) } while (symbol < 0x100);\n+      }\n+      else\n+      {\n+        unsigned matchByte = p->dic[p->dicPos - p->reps[0] +\n+            ((p->dicPos < p->reps[0]) ? p->dicBufSize : 0)];\n+        unsigned offs = 0x100;\n+        unsigned symbol = 1;\n+        do\n+        {\n+          unsigned bit;\n+          CLzmaProb *probLit;\n+          matchByte <<= 1;\n+          bit = (matchByte & offs);\n+          probLit = prob + offs + bit + symbol;\n+          GET_BIT2_CHECK(probLit, symbol, offs &= ~bit, offs &= bit)\n+        }\n+        while (symbol < 0x100);\n+      }\n+      res = DUMMY_LIT;\n+    }\n+    else\n+    {\n+      unsigned len;\n+      UPDATE_1_CHECK;\n+\n+      prob = probs + IsRep + state;\n+      IF_BIT_0_CHECK(prob)\n+      {\n+        UPDATE_0_CHECK;\n+        state = 0;\n+        prob = probs + LenCoder;\n+        res = DUMMY_MATCH;\n+      }\n+      else\n+      {\n+        UPDATE_1_CHECK;\n+        res = DUMMY_REP;\n+        prob = probs + IsRepG0 + state;\n+        IF_BIT_0_CHECK(prob)\n+        {\n+          UPDATE_0_CHECK;\n+          prob = probs + IsRep0Long + (state << kNumPosBitsMax) + posState;\n+          IF_BIT_0_CHECK(prob)\n+          {\n+            UPDATE_0_CHECK;\n+            NORMALIZE_CHECK;\n+            return DUMMY_REP;\n+          }\n+          else\n+          {\n+            UPDATE_1_CHECK;\n+          }\n+        }\n+        else\n+        {\n+          UPDATE_1_CHECK;\n+          prob = probs + IsRepG1 + state;\n+          IF_BIT_0_CHECK(prob)\n+          {\n+            UPDATE_0_CHECK;\n+          }\n+          else\n+          {\n+            UPDATE_1_CHECK;\n+            prob = probs + IsRepG2 + state;\n+            IF_BIT_0_CHECK(prob)\n+            {\n+              UPDATE_0_CHECK;\n+            }\n+            else\n+            {\n+              UPDATE_1_CHECK;\n+            }\n+          }\n+        }\n+        state = kNumStates;\n+        prob = probs + RepLenCoder;\n+      }\n+      {\n+        unsigned limit, offset;\n+        CLzmaProb *probLen = prob + LenChoice;\n+        IF_BIT_0_CHECK(probLen)\n+        {\n+          UPDATE_0_CHECK;\n+          probLen = prob + LenLow + (posState << kLenNumLowBits);\n+          offset = 0;\n+          limit = 1 << kLenNumLowBits;\n+        }\n+        else\n+        {\n+          UPDATE_1_CHECK;\n+          probLen = prob + LenChoice2;\n+          IF_BIT_0_CHECK(probLen)\n+          {\n+            UPDATE_0_CHECK;\n+            probLen = prob + LenMid + (posState << kLenNumMidBits);\n+            offset = kLenNumLowSymbols;\n+            limit = 1 << kLenNumMidBits;\n+          }\n+          else\n+          {\n+            UPDATE_1_CHECK;\n+            probLen = prob + LenHigh;\n+            offset = kLenNumLowSymbols + kLenNumMidSymbols;\n+            limit = 1 << kLenNumHighBits;\n+          }\n+        }\n+        TREE_DECODE_CHECK(probLen, limit, len);\n+        len += offset;\n+      }\n+\n+      if (state < 4)\n+      {\n+        unsigned posSlot;\n+        prob = probs + PosSlot +\n+            ((len < kNumLenToPosStates ? len : kNumLenToPosStates - 1) <<\n+            kNumPosSlotBits);\n+        TREE_DECODE_CHECK(prob, 1 << kNumPosSlotBits, posSlot);\n+        if (posSlot >= kStartPosModelIndex)\n+        {\n+          int numDirectBits = ((posSlot >> 1) - 1);\n+\n+          /* if (bufLimit - buf >= 8) return DUMMY_MATCH; */\n+\n+          if (posSlot < kEndPosModelIndex)\n+          {\n+            prob = probs + SpecPos + ((2 | (posSlot & 1)) << numDirectBits) - posSlot - 1;\n+          }\n+          else\n+          {\n+            numDirectBits -= kNumAlignBits;\n+            do\n+            {\n+              NORMALIZE_CHECK\n+              range >>= 1;\n+              code -= range & (((code - range) >> 31) - 1);\n+              /* if (code >= range) code -= range; */\n+            }\n+            while (--numDirectBits != 0);\n+            prob = probs + Align;\n+            numDirectBits = kNumAlignBits;\n+          }\n+          {\n+            unsigned i = 1;\n+            do\n+            {\n+              GET_BIT_CHECK(prob + i, i);\n+            }\n+            while (--numDirectBits != 0);\n+          }\n+        }\n+      }\n+    }\n+  }\n+  NORMALIZE_CHECK;\n+  return res;\n+}\n+\n+\n+static void LzmaDec_InitRc(CLzmaDec *p, const Byte *data)\n+{\n+  p->code = ((UInt32)data[1] << 24) | ((UInt32)data[2] << 16) | ((UInt32)data[3] << 8) | ((UInt32)data[4]);\n+  p->range = 0xFFFFFFFF;\n+  p->needFlush = 0;\n+}\n+\n+void LzmaDec_InitDicAndState(CLzmaDec *p, Bool initDic, Bool initState)\n+{\n+  p->needFlush = 1;\n+  p->remainLen = 0;\n+  p->tempBufSize = 0;\n+\n+  if (initDic)\n+  {\n+    p->processedPos = 0;\n+    p->checkDicSize = 0;\n+    p->needInitState = 1;\n+  }\n+  if (initState)\n+    p->needInitState = 1;\n+}\n+\n+void LzmaDec_Init(CLzmaDec *p)\n+{\n+  p->dicPos = 0;\n+  LzmaDec_InitDicAndState(p, True, True);\n+}\n+\n+static void LzmaDec_InitStateReal(CLzmaDec *p)\n+{\n+  UInt32 numProbs = Literal + ((UInt32)LZMA_LIT_SIZE << (p->prop.lc + p->prop.lp));\n+  UInt32 i;\n+  CLzmaProb *probs = p->probs;\n+  for (i = 0; i < numProbs; i++)\n+    probs[i] = kBitModelTotal >> 1;\n+  p->reps[0] = p->reps[1] = p->reps[2] = p->reps[3] = 1;\n+  p->state = 0;\n+  p->needInitState = 0;\n+}\n+\n+SRes LzmaDec_DecodeToDic(CLzmaDec *p, SizeT dicLimit, const Byte *src, SizeT *srcLen,\n+    ELzmaFinishMode finishMode, ELzmaStatus *status)\n+{\n+  SizeT inSize = *srcLen;\n+  (*srcLen) = 0;\n+  LzmaDec_WriteRem(p, dicLimit);\n+\n+  *status = LZMA_STATUS_NOT_SPECIFIED;\n+\n+  while (p->remainLen != kMatchSpecLenStart)\n+  {\n+      int checkEndMarkNow;\n+\n+      if (p->needFlush != 0)\n+      {\n+        for (; inSize > 0 && p->tempBufSize < RC_INIT_SIZE; (*srcLen)++, inSize--)\n+          p->tempBuf[p->tempBufSize++] = *src++;\n+        if (p->tempBufSize < RC_INIT_SIZE)\n+        {\n+          *status = LZMA_STATUS_NEEDS_MORE_INPUT;\n+          return SZ_OK;\n+        }\n+        if (p->tempBuf[0] != 0)\n+          return SZ_ERROR_DATA;\n+\n+        LzmaDec_InitRc(p, p->tempBuf);\n+        p->tempBufSize = 0;\n+      }\n+\n+      checkEndMarkNow = 0;\n+      if (p->dicPos >= dicLimit)\n+      {\n+        if (p->remainLen == 0 && p->code == 0)\n+        {\n+          *status = LZMA_STATUS_MAYBE_FINISHED_WITHOUT_MARK;\n+          return SZ_OK;\n+        }\n+        if (finishMode == LZMA_FINISH_ANY)\n+        {\n+          *status = LZMA_STATUS_NOT_FINISHED;\n+          return SZ_OK;\n+        }\n+        if (p->remainLen != 0)\n+        {\n+          *status = LZMA_STATUS_NOT_FINISHED;\n+          return SZ_ERROR_DATA;\n+        }\n+        checkEndMarkNow = 1;\n+      }\n+\n+      if (p->needInitState)\n+        LzmaDec_InitStateReal(p);\n+\n+      if (p->tempBufSize == 0)\n+      {\n+        SizeT processed;\n+        const Byte *bufLimit;\n+        if (inSize < LZMA_REQUIRED_INPUT_MAX || checkEndMarkNow)\n+        {\n+          int dummyRes = LzmaDec_TryDummy(p, src, inSize);\n+          if (dummyRes == DUMMY_ERROR)\n+          {\n+            memcpy(p->tempBuf, src, inSize);\n+            p->tempBufSize = (unsigned)inSize;\n+            (*srcLen) += inSize;\n+            *status = LZMA_STATUS_NEEDS_MORE_INPUT;\n+            return SZ_OK;\n+          }\n+          if (checkEndMarkNow && dummyRes != DUMMY_MATCH)\n+          {\n+            *status = LZMA_STATUS_NOT_FINISHED;\n+            return SZ_ERROR_DATA;\n+          }\n+          bufLimit = src;\n+        }\n+        else\n+          bufLimit = src + inSize - LZMA_REQUIRED_INPUT_MAX;\n+        p->buf = src;\n+        if (LzmaDec_DecodeReal2(p, dicLimit, bufLimit) != 0)\n+          return SZ_ERROR_DATA;\n+        processed = (SizeT)(p->buf - src);\n+        (*srcLen) += processed;\n+        src += processed;\n+        inSize -= processed;\n+      }\n+      else\n+      {\n+        unsigned rem = p->tempBufSize, lookAhead = 0;\n+        while (rem < LZMA_REQUIRED_INPUT_MAX && lookAhead < inSize)\n+          p->tempBuf[rem++] = src[lookAhead++];\n+        p->tempBufSize = rem;\n+        if (rem < LZMA_REQUIRED_INPUT_MAX || checkEndMarkNow)\n+        {\n+          int dummyRes = LzmaDec_TryDummy(p, p->tempBuf, rem);\n+          if (dummyRes == DUMMY_ERROR)\n+          {\n+            (*srcLen) += lookAhead;\n+            *status = LZMA_STATUS_NEEDS_MORE_INPUT;\n+            return SZ_OK;\n+          }\n+          if (checkEndMarkNow && dummyRes != DUMMY_MATCH)\n+          {\n+            *status = LZMA_STATUS_NOT_FINISHED;\n+            return SZ_ERROR_DATA;\n+          }\n+        }\n+        p->buf = p->tempBuf;\n+        if (LzmaDec_DecodeReal2(p, dicLimit, p->buf) != 0)\n+          return SZ_ERROR_DATA;\n+        lookAhead -= (rem - (unsigned)(p->buf - p->tempBuf));\n+        (*srcLen) += lookAhead;\n+        src += lookAhead;\n+        inSize -= lookAhead;\n+        p->tempBufSize = 0;\n+      }\n+  }\n+  if (p->code == 0)\n+    *status = LZMA_STATUS_FINISHED_WITH_MARK;\n+  return (p->code == 0) ? SZ_OK : SZ_ERROR_DATA;\n+}\n+\n+SRes LzmaDec_DecodeToBuf(CLzmaDec *p, Byte *dest, SizeT *destLen, const Byte *src, SizeT *srcLen, ELzmaFinishMode finishMode, ELzmaStatus *status)\n+{\n+  SizeT outSize = *destLen;\n+  SizeT inSize = *srcLen;\n+  *srcLen = *destLen = 0;\n+  for (;;)\n+  {\n+    SizeT inSizeCur = inSize, outSizeCur, dicPos;\n+    ELzmaFinishMode curFinishMode;\n+    SRes res;\n+    if (p->dicPos == p->dicBufSize)\n+      p->dicPos = 0;\n+    dicPos = p->dicPos;\n+    if (outSize > p->dicBufSize - dicPos)\n+    {\n+      outSizeCur = p->dicBufSize;\n+      curFinishMode = LZMA_FINISH_ANY;\n+    }\n+    else\n+    {\n+      outSizeCur = dicPos + outSize;\n+      curFinishMode = finishMode;\n+    }\n+\n+    res = LzmaDec_DecodeToDic(p, outSizeCur, src, &inSizeCur, curFinishMode, status);\n+    src += inSizeCur;\n+    inSize -= inSizeCur;\n+    *srcLen += inSizeCur;\n+    outSizeCur = p->dicPos - dicPos;\n+    memcpy(dest, p->dic + dicPos, outSizeCur);\n+    dest += outSizeCur;\n+    outSize -= outSizeCur;\n+    *destLen += outSizeCur;\n+    if (res != 0)\n+      return res;\n+    if (outSizeCur == 0 || outSize == 0)\n+      return SZ_OK;\n+  }\n+}\n+\n+void LzmaDec_FreeProbs(CLzmaDec *p, ISzAlloc *alloc)\n+{\n+  alloc->Free(alloc, p->probs);\n+  p->probs = 0;\n+}\n+\n+static void LzmaDec_FreeDict(CLzmaDec *p, ISzAlloc *alloc)\n+{\n+  alloc->Free(alloc, p->dic);\n+  p->dic = 0;\n+}\n+\n+void LzmaDec_Free(CLzmaDec *p, ISzAlloc *alloc)\n+{\n+  LzmaDec_FreeProbs(p, alloc);\n+  LzmaDec_FreeDict(p, alloc);\n+}\n+\n+SRes LzmaProps_Decode(CLzmaProps *p, const Byte *data, unsigned size)\n+{\n+  UInt32 dicSize;\n+  Byte d;\n+\n+  if (size < LZMA_PROPS_SIZE)\n+    return SZ_ERROR_UNSUPPORTED;\n+  else\n+    dicSize = data[1] | ((UInt32)data[2] << 8) | ((UInt32)data[3] << 16) | ((UInt32)data[4] << 24);\n+\n+  if (dicSize < LZMA_DIC_MIN)\n+    dicSize = LZMA_DIC_MIN;\n+  p->dicSize = dicSize;\n+\n+  d = data[0];\n+  if (d >= (9 * 5 * 5))\n+    return SZ_ERROR_UNSUPPORTED;\n+\n+  p->lc = d % 9;\n+  d /= 9;\n+  p->pb = d / 5;\n+  p->lp = d % 5;\n+\n+  return SZ_OK;\n+}\n+\n+static SRes LzmaDec_AllocateProbs2(CLzmaDec *p, const CLzmaProps *propNew, ISzAlloc *alloc)\n+{\n+  UInt32 numProbs = LzmaProps_GetNumProbs(propNew);\n+  if (p->probs == 0 || numProbs != p->numProbs)\n+  {\n+    LzmaDec_FreeProbs(p, alloc);\n+    p->probs = (CLzmaProb *)alloc->Alloc(alloc, numProbs * sizeof(CLzmaProb));\n+    p->numProbs = numProbs;\n+    if (p->probs == 0)\n+      return SZ_ERROR_MEM;\n+  }\n+  return SZ_OK;\n+}\n+\n+SRes LzmaDec_AllocateProbs(CLzmaDec *p, const Byte *props, unsigned propsSize, ISzAlloc *alloc)\n+{\n+  CLzmaProps propNew;\n+  RINOK(LzmaProps_Decode(&propNew, props, propsSize));\n+  RINOK(LzmaDec_AllocateProbs2(p, &propNew, alloc));\n+  p->prop = propNew;\n+  return SZ_OK;\n+}\n+\n+SRes LzmaDec_Allocate(CLzmaDec *p, const Byte *props, unsigned propsSize, ISzAlloc *alloc)\n+{\n+  CLzmaProps propNew;\n+  SizeT dicBufSize;\n+  RINOK(LzmaProps_Decode(&propNew, props, propsSize));\n+  RINOK(LzmaDec_AllocateProbs2(p, &propNew, alloc));\n+  dicBufSize = propNew.dicSize;\n+  if (p->dic == 0 || dicBufSize != p->dicBufSize)\n+  {\n+    LzmaDec_FreeDict(p, alloc);\n+    p->dic = (Byte *)alloc->Alloc(alloc, dicBufSize);\n+    if (p->dic == 0)\n+    {\n+      LzmaDec_FreeProbs(p, alloc);\n+      return SZ_ERROR_MEM;\n+    }\n+  }\n+  p->dicBufSize = dicBufSize;\n+  p->prop = propNew;\n+  return SZ_OK;\n+}\n+\n+SRes LzmaDecode(Byte *dest, SizeT *destLen, const Byte *src, SizeT *srcLen,\n+    const Byte *propData, unsigned propSize, ELzmaFinishMode finishMode,\n+    ELzmaStatus *status, ISzAlloc *alloc)\n+{\n+  CLzmaDec p;\n+  SRes res;\n+  SizeT inSize = *srcLen;\n+  SizeT outSize = *destLen;\n+  *srcLen = *destLen = 0;\n+  if (inSize < RC_INIT_SIZE)\n+    return SZ_ERROR_INPUT_EOF;\n+\n+  LzmaDec_Construct(&p);\n+  res = LzmaDec_AllocateProbs(&p, propData, propSize, alloc);\n+  if (res != 0)\n+    return res;\n+  p.dic = dest;\n+  p.dicBufSize = outSize;\n+\n+  LzmaDec_Init(&p);\n+\n+  *srcLen = inSize;\n+  res = LzmaDec_DecodeToDic(&p, outSize, src, srcLen, finishMode, status);\n+\n+  if (res == SZ_OK && *status == LZMA_STATUS_NEEDS_MORE_INPUT)\n+    res = SZ_ERROR_INPUT_EOF;\n+\n+  (*destLen) = p.dicPos;\n+  LzmaDec_FreeProbs(&p, alloc);\n+  return res;\n+}\n--- /dev/null\n+++ b/lib/lzma/LzmaEnc.c\n@@ -0,0 +1,2271 @@\n+/* LzmaEnc.c -- LZMA Encoder\n+2009-11-24 : Igor Pavlov : Public domain */\n+\n+#include <string.h>\n+\n+/* #define SHOW_STAT */\n+/* #define SHOW_STAT2 */\n+\n+#if defined(SHOW_STAT) || defined(SHOW_STAT2)\n+#include <stdio.h>\n+#endif\n+\n+#include \"LzmaEnc.h\"\n+\n+/* disable MT */\n+#define _7ZIP_ST\n+\n+#include \"LzFind.h\"\n+#ifndef _7ZIP_ST\n+#include \"LzFindMt.h\"\n+#endif\n+\n+#ifdef SHOW_STAT\n+static int ttt = 0;\n+#endif\n+\n+#define kBlockSizeMax ((1 << LZMA_NUM_BLOCK_SIZE_BITS) - 1)\n+\n+#define kBlockSize (9 << 10)\n+#define kUnpackBlockSize (1 << 18)\n+#define kMatchArraySize (1 << 21)\n+#define kMatchRecordMaxSize ((LZMA_MATCH_LEN_MAX * 2 + 3) * LZMA_MATCH_LEN_MAX)\n+\n+#define kNumMaxDirectBits (31)\n+\n+#define kNumTopBits 24\n+#define kTopValue ((UInt32)1 << kNumTopBits)\n+\n+#define kNumBitModelTotalBits 11\n+#define kBitModelTotal (1 << kNumBitModelTotalBits)\n+#define kNumMoveBits 5\n+#define kProbInitValue (kBitModelTotal >> 1)\n+\n+#define kNumMoveReducingBits 4\n+#define kNumBitPriceShiftBits 4\n+#define kBitPrice (1 << kNumBitPriceShiftBits)\n+\n+void LzmaEncProps_Init(CLzmaEncProps *p)\n+{\n+  p->level = 5;\n+  p->dictSize = p->mc = 0;\n+  p->lc = p->lp = p->pb = p->algo = p->fb = p->btMode = p->numHashBytes = p->numThreads = -1;\n+  p->writeEndMark = 0;\n+}\n+\n+void LzmaEncProps_Normalize(CLzmaEncProps *p)\n+{\n+  int level = p->level;\n+  if (level < 0) level = 5;\n+  p->level = level;\n+  if (p->dictSize == 0) p->dictSize = (level <= 5 ? (1 << (level * 2 + 14)) : (level == 6 ? (1 << 25) : (1 << 26)));\n+  if (p->lc < 0) p->lc = 3;\n+  if (p->lp < 0) p->lp = 0;\n+  if (p->pb < 0) p->pb = 2;\n+  if (p->algo < 0) p->algo = (level < 5 ? 0 : 1);\n+  if (p->fb < 0) p->fb = (level < 7 ? 32 : 64);\n+  if (p->btMode < 0) p->btMode = (p->algo == 0 ? 0 : 1);\n+  if (p->numHashBytes < 0) p->numHashBytes = 4;\n+  if (p->mc == 0)  p->mc = (16 + (p->fb >> 1)) >> (p->btMode ? 0 : 1);\n+  if (p->numThreads < 0)\n+    p->numThreads =\n+      #ifndef _7ZIP_ST\n+      ((p->btMode && p->algo) ? 2 : 1);\n+      #else\n+      1;\n+      #endif\n+}\n+\n+UInt32 LzmaEncProps_GetDictSize(const CLzmaEncProps *props2)\n+{\n+  CLzmaEncProps props = *props2;\n+  LzmaEncProps_Normalize(&props);\n+  return props.dictSize;\n+}\n+\n+/* #define LZMA_LOG_BSR */\n+/* Define it for Intel's CPU */\n+\n+\n+#ifdef LZMA_LOG_BSR\n+\n+#define kDicLogSizeMaxCompress 30\n+\n+#define BSR2_RET(pos, res) { unsigned long i; _BitScanReverse(&i, (pos)); res = (i + i) + ((pos >> (i - 1)) & 1); }\n+\n+UInt32 GetPosSlot1(UInt32 pos)\n+{\n+  UInt32 res;\n+  BSR2_RET(pos, res);\n+  return res;\n+}\n+#define GetPosSlot2(pos, res) { BSR2_RET(pos, res); }\n+#define GetPosSlot(pos, res) { if (pos < 2) res = pos; else BSR2_RET(pos, res); }\n+\n+#else\n+\n+#define kNumLogBits (9 + (int)sizeof(size_t) / 2)\n+#define kDicLogSizeMaxCompress ((kNumLogBits - 1) * 2 + 7)\n+\n+void LzmaEnc_FastPosInit(Byte *g_FastPos)\n+{\n+  int c = 2, slotFast;\n+  g_FastPos[0] = 0;\n+  g_FastPos[1] = 1;\n+\n+  for (slotFast = 2; slotFast < kNumLogBits * 2; slotFast++)\n+  {\n+    UInt32 k = (1 << ((slotFast >> 1) - 1));\n+    UInt32 j;\n+    for (j = 0; j < k; j++, c++)\n+      g_FastPos[c] = (Byte)slotFast;\n+  }\n+}\n+\n+#define BSR2_RET(pos, res) { UInt32 i = 6 + ((kNumLogBits - 1) & \\\n+  (0 - (((((UInt32)1 << (kNumLogBits + 6)) - 1) - pos) >> 31))); \\\n+  res = p->g_FastPos[pos >> i] + (i * 2); }\n+/*\n+#define BSR2_RET(pos, res) { res = (pos < (1 << (kNumLogBits + 6))) ? \\\n+  p->g_FastPos[pos >> 6] + 12 : \\\n+  p->g_FastPos[pos >> (6 + kNumLogBits - 1)] + (6 + (kNumLogBits - 1)) * 2; }\n+*/\n+\n+#define GetPosSlot1(pos) p->g_FastPos[pos]\n+#define GetPosSlot2(pos, res) { BSR2_RET(pos, res); }\n+#define GetPosSlot(pos, res) { if (pos < kNumFullDistances) res = p->g_FastPos[pos]; else BSR2_RET(pos, res); }\n+\n+#endif\n+\n+\n+#define LZMA_NUM_REPS 4\n+\n+typedef unsigned CState;\n+\n+typedef struct\n+{\n+  UInt32 price;\n+\n+  CState state;\n+  int prev1IsChar;\n+  int prev2;\n+\n+  UInt32 posPrev2;\n+  UInt32 backPrev2;\n+\n+  UInt32 posPrev;\n+  UInt32 backPrev;\n+  UInt32 backs[LZMA_NUM_REPS];\n+} COptimal;\n+\n+#define kNumOpts (1 << 12)\n+\n+#define kNumLenToPosStates 4\n+#define kNumPosSlotBits 6\n+#define kDicLogSizeMin 0\n+#define kDicLogSizeMax 32\n+#define kDistTableSizeMax (kDicLogSizeMax * 2)\n+\n+\n+#define kNumAlignBits 4\n+#define kAlignTableSize (1 << kNumAlignBits)\n+#define kAlignMask (kAlignTableSize - 1)\n+\n+#define kStartPosModelIndex 4\n+#define kEndPosModelIndex 14\n+#define kNumPosModels (kEndPosModelIndex - kStartPosModelIndex)\n+\n+#define kNumFullDistances (1 << (kEndPosModelIndex >> 1))\n+\n+#ifdef _LZMA_PROB32\n+#define CLzmaProb UInt32\n+#else\n+#define CLzmaProb UInt16\n+#endif\n+\n+#define LZMA_PB_MAX 4\n+#define LZMA_LC_MAX 8\n+#define LZMA_LP_MAX 4\n+\n+#define LZMA_NUM_PB_STATES_MAX (1 << LZMA_PB_MAX)\n+\n+\n+#define kLenNumLowBits 3\n+#define kLenNumLowSymbols (1 << kLenNumLowBits)\n+#define kLenNumMidBits 3\n+#define kLenNumMidSymbols (1 << kLenNumMidBits)\n+#define kLenNumHighBits 8\n+#define kLenNumHighSymbols (1 << kLenNumHighBits)\n+\n+#define kLenNumSymbolsTotal (kLenNumLowSymbols + kLenNumMidSymbols + kLenNumHighSymbols)\n+\n+#define LZMA_MATCH_LEN_MIN 2\n+#define LZMA_MATCH_LEN_MAX (LZMA_MATCH_LEN_MIN + kLenNumSymbolsTotal - 1)\n+\n+#define kNumStates 12\n+\n+typedef struct\n+{\n+  CLzmaProb choice;\n+  CLzmaProb choice2;\n+  CLzmaProb low[LZMA_NUM_PB_STATES_MAX << kLenNumLowBits];\n+  CLzmaProb mid[LZMA_NUM_PB_STATES_MAX << kLenNumMidBits];\n+  CLzmaProb high[kLenNumHighSymbols];\n+} CLenEnc;\n+\n+typedef struct\n+{\n+  CLenEnc p;\n+  UInt32 prices[LZMA_NUM_PB_STATES_MAX][kLenNumSymbolsTotal];\n+  UInt32 tableSize;\n+  UInt32 counters[LZMA_NUM_PB_STATES_MAX];\n+} CLenPriceEnc;\n+\n+typedef struct\n+{\n+  UInt32 range;\n+  Byte cache;\n+  UInt64 low;\n+  UInt64 cacheSize;\n+  Byte *buf;\n+  Byte *bufLim;\n+  Byte *bufBase;\n+  ISeqOutStream *outStream;\n+  UInt64 processed;\n+  SRes res;\n+} CRangeEnc;\n+\n+typedef struct\n+{\n+  CLzmaProb *litProbs;\n+\n+  CLzmaProb isMatch[kNumStates][LZMA_NUM_PB_STATES_MAX];\n+  CLzmaProb isRep[kNumStates];\n+  CLzmaProb isRepG0[kNumStates];\n+  CLzmaProb isRepG1[kNumStates];\n+  CLzmaProb isRepG2[kNumStates];\n+  CLzmaProb isRep0Long[kNumStates][LZMA_NUM_PB_STATES_MAX];\n+\n+  CLzmaProb posSlotEncoder[kNumLenToPosStates][1 << kNumPosSlotBits];\n+  CLzmaProb posEncoders[kNumFullDistances - kEndPosModelIndex];\n+  CLzmaProb posAlignEncoder[1 << kNumAlignBits];\n+\n+  CLenPriceEnc lenEnc;\n+  CLenPriceEnc repLenEnc;\n+\n+  UInt32 reps[LZMA_NUM_REPS];\n+  UInt32 state;\n+} CSaveState;\n+\n+typedef struct\n+{\n+  IMatchFinder matchFinder;\n+  void *matchFinderObj;\n+\n+  #ifndef _7ZIP_ST\n+  Bool mtMode;\n+  CMatchFinderMt matchFinderMt;\n+  #endif\n+\n+  CMatchFinder matchFinderBase;\n+\n+  #ifndef _7ZIP_ST\n+  Byte pad[128];\n+  #endif\n+\n+  UInt32 optimumEndIndex;\n+  UInt32 optimumCurrentIndex;\n+\n+  UInt32 longestMatchLength;\n+  UInt32 numPairs;\n+  UInt32 numAvail;\n+  COptimal opt[kNumOpts];\n+\n+  #ifndef LZMA_LOG_BSR\n+  Byte g_FastPos[1 << kNumLogBits];\n+  #endif\n+\n+  UInt32 ProbPrices[kBitModelTotal >> kNumMoveReducingBits];\n+  UInt32 matches[LZMA_MATCH_LEN_MAX * 2 + 2 + 1];\n+  UInt32 numFastBytes;\n+  UInt32 additionalOffset;\n+  UInt32 reps[LZMA_NUM_REPS];\n+  UInt32 state;\n+\n+  UInt32 posSlotPrices[kNumLenToPosStates][kDistTableSizeMax];\n+  UInt32 distancesPrices[kNumLenToPosStates][kNumFullDistances];\n+  UInt32 alignPrices[kAlignTableSize];\n+  UInt32 alignPriceCount;\n+\n+  UInt32 distTableSize;\n+\n+  unsigned lc, lp, pb;\n+  unsigned lpMask, pbMask;\n+\n+  CLzmaProb *litProbs;\n+\n+  CLzmaProb isMatch[kNumStates][LZMA_NUM_PB_STATES_MAX];\n+  CLzmaProb isRep[kNumStates];\n+  CLzmaProb isRepG0[kNumStates];\n+  CLzmaProb isRepG1[kNumStates];\n+  CLzmaProb isRepG2[kNumStates];\n+  CLzmaProb isRep0Long[kNumStates][LZMA_NUM_PB_STATES_MAX];\n+\n+  CLzmaProb posSlotEncoder[kNumLenToPosStates][1 << kNumPosSlotBits];\n+  CLzmaProb posEncoders[kNumFullDistances - kEndPosModelIndex];\n+  CLzmaProb posAlignEncoder[1 << kNumAlignBits];\n+\n+  CLenPriceEnc lenEnc;\n+  CLenPriceEnc repLenEnc;\n+\n+  unsigned lclp;\n+\n+  Bool fastMode;\n+\n+  CRangeEnc rc;\n+\n+  Bool writeEndMark;\n+  UInt64 nowPos64;\n+  UInt32 matchPriceCount;\n+  Bool finished;\n+  Bool multiThread;\n+\n+  SRes result;\n+  UInt32 dictSize;\n+  UInt32 matchFinderCycles;\n+\n+  int needInit;\n+\n+  CSaveState saveState;\n+} CLzmaEnc;\n+\n+void LzmaEnc_SaveState(CLzmaEncHandle pp)\n+{\n+  CLzmaEnc *p = (CLzmaEnc *)pp;\n+  CSaveState *dest = &p->saveState;\n+  int i;\n+  dest->lenEnc = p->lenEnc;\n+  dest->repLenEnc = p->repLenEnc;\n+  dest->state = p->state;\n+\n+  for (i = 0; i < kNumStates; i++)\n+  {\n+    memcpy(dest->isMatch[i], p->isMatch[i], sizeof(p->isMatch[i]));\n+    memcpy(dest->isRep0Long[i], p->isRep0Long[i], sizeof(p->isRep0Long[i]));\n+  }\n+  for (i = 0; i < kNumLenToPosStates; i++)\n+    memcpy(dest->posSlotEncoder[i], p->posSlotEncoder[i], sizeof(p->posSlotEncoder[i]));\n+  memcpy(dest->isRep, p->isRep, sizeof(p->isRep));\n+  memcpy(dest->isRepG0, p->isRepG0, sizeof(p->isRepG0));\n+  memcpy(dest->isRepG1, p->isRepG1, sizeof(p->isRepG1));\n+  memcpy(dest->isRepG2, p->isRepG2, sizeof(p->isRepG2));\n+  memcpy(dest->posEncoders, p->posEncoders, sizeof(p->posEncoders));\n+  memcpy(dest->posAlignEncoder, p->posAlignEncoder, sizeof(p->posAlignEncoder));\n+  memcpy(dest->reps, p->reps, sizeof(p->reps));\n+  memcpy(dest->litProbs, p->litProbs, (0x300 << p->lclp) * sizeof(CLzmaProb));\n+}\n+\n+void LzmaEnc_RestoreState(CLzmaEncHandle pp)\n+{\n+  CLzmaEnc *dest = (CLzmaEnc *)pp;\n+  const CSaveState *p = &dest->saveState;\n+  int i;\n+  dest->lenEnc = p->lenEnc;\n+  dest->repLenEnc = p->repLenEnc;\n+  dest->state = p->state;\n+\n+  for (i = 0; i < kNumStates; i++)\n+  {\n+    memcpy(dest->isMatch[i], p->isMatch[i], sizeof(p->isMatch[i]));\n+    memcpy(dest->isRep0Long[i], p->isRep0Long[i], sizeof(p->isRep0Long[i]));\n+  }\n+  for (i = 0; i < kNumLenToPosStates; i++)\n+    memcpy(dest->posSlotEncoder[i], p->posSlotEncoder[i], sizeof(p->posSlotEncoder[i]));\n+  memcpy(dest->isRep, p->isRep, sizeof(p->isRep));\n+  memcpy(dest->isRepG0, p->isRepG0, sizeof(p->isRepG0));\n+  memcpy(dest->isRepG1, p->isRepG1, sizeof(p->isRepG1));\n+  memcpy(dest->isRepG2, p->isRepG2, sizeof(p->isRepG2));\n+  memcpy(dest->posEncoders, p->posEncoders, sizeof(p->posEncoders));\n+  memcpy(dest->posAlignEncoder, p->posAlignEncoder, sizeof(p->posAlignEncoder));\n+  memcpy(dest->reps, p->reps, sizeof(p->reps));\n+  memcpy(dest->litProbs, p->litProbs, (0x300 << dest->lclp) * sizeof(CLzmaProb));\n+}\n+\n+SRes LzmaEnc_SetProps(CLzmaEncHandle pp, const CLzmaEncProps *props2)\n+{\n+  CLzmaEnc *p = (CLzmaEnc *)pp;\n+  CLzmaEncProps props = *props2;\n+  LzmaEncProps_Normalize(&props);\n+\n+  if (props.lc > LZMA_LC_MAX || props.lp > LZMA_LP_MAX || props.pb > LZMA_PB_MAX ||\n+      props.dictSize > (1 << kDicLogSizeMaxCompress) || props.dictSize > (1 << 30))\n+    return SZ_ERROR_PARAM;\n+  p->dictSize = props.dictSize;\n+  p->matchFinderCycles = props.mc;\n+  {\n+    unsigned fb = props.fb;\n+    if (fb < 5)\n+      fb = 5;\n+    if (fb > LZMA_MATCH_LEN_MAX)\n+      fb = LZMA_MATCH_LEN_MAX;\n+    p->numFastBytes = fb;\n+  }\n+  p->lc = props.lc;\n+  p->lp = props.lp;\n+  p->pb = props.pb;\n+  p->fastMode = (props.algo == 0);\n+  p->matchFinderBase.btMode = props.btMode;\n+  {\n+    UInt32 numHashBytes = 4;\n+    if (props.btMode)\n+    {\n+      if (props.numHashBytes < 2)\n+        numHashBytes = 2;\n+      else if (props.numHashBytes < 4)\n+        numHashBytes = props.numHashBytes;\n+    }\n+    p->matchFinderBase.numHashBytes = numHashBytes;\n+  }\n+\n+  p->matchFinderBase.cutValue = props.mc;\n+\n+  p->writeEndMark = props.writeEndMark;\n+\n+  #ifndef _7ZIP_ST\n+  /*\n+  if (newMultiThread != _multiThread)\n+  {\n+    ReleaseMatchFinder();\n+    _multiThread = newMultiThread;\n+  }\n+  */\n+  p->multiThread = (props.numThreads > 1);\n+  #endif\n+\n+  return SZ_OK;\n+}\n+\n+static const int kLiteralNextStates[kNumStates] = {0, 0, 0, 0, 1, 2, 3, 4,  5,  6,   4, 5};\n+static const int kMatchNextStates[kNumStates]   = {7, 7, 7, 7, 7, 7, 7, 10, 10, 10, 10, 10};\n+static const int kRepNextStates[kNumStates]     = {8, 8, 8, 8, 8, 8, 8, 11, 11, 11, 11, 11};\n+static const int kShortRepNextStates[kNumStates]= {9, 9, 9, 9, 9, 9, 9, 11, 11, 11, 11, 11};\n+\n+#define IsCharState(s) ((s) < 7)\n+\n+#define GetLenToPosState(len) (((len) < kNumLenToPosStates + 1) ? (len) - 2 : kNumLenToPosStates - 1)\n+\n+#define kInfinityPrice (1 << 30)\n+\n+static void RangeEnc_Construct(CRangeEnc *p)\n+{\n+  p->outStream = 0;\n+  p->bufBase = 0;\n+}\n+\n+#define RangeEnc_GetProcessed(p) ((p)->processed + ((p)->buf - (p)->bufBase) + (p)->cacheSize)\n+\n+#define RC_BUF_SIZE (1 << 16)\n+static int RangeEnc_Alloc(CRangeEnc *p, ISzAlloc *alloc)\n+{\n+  if (p->bufBase == 0)\n+  {\n+    p->bufBase = (Byte *)alloc->Alloc(alloc, RC_BUF_SIZE);\n+    if (p->bufBase == 0)\n+      return 0;\n+    p->bufLim = p->bufBase + RC_BUF_SIZE;\n+  }\n+  return 1;\n+}\n+\n+static void RangeEnc_Free(CRangeEnc *p, ISzAlloc *alloc)\n+{\n+  alloc->Free(alloc, p->bufBase);\n+  p->bufBase = 0;\n+}\n+\n+static void RangeEnc_Init(CRangeEnc *p)\n+{\n+  /* Stream.Init(); */\n+  p->low = 0;\n+  p->range = 0xFFFFFFFF;\n+  p->cacheSize = 1;\n+  p->cache = 0;\n+\n+  p->buf = p->bufBase;\n+\n+  p->processed = 0;\n+  p->res = SZ_OK;\n+}\n+\n+static void RangeEnc_FlushStream(CRangeEnc *p)\n+{\n+  size_t num;\n+  if (p->res != SZ_OK)\n+    return;\n+  num = p->buf - p->bufBase;\n+  if (num != p->outStream->Write(p->outStream, p->bufBase, num))\n+    p->res = SZ_ERROR_WRITE;\n+  p->processed += num;\n+  p->buf = p->bufBase;\n+}\n+\n+static void MY_FAST_CALL RangeEnc_ShiftLow(CRangeEnc *p)\n+{\n+  if ((UInt32)p->low < (UInt32)0xFF000000 || (int)(p->low >> 32) != 0)\n+  {\n+    Byte temp = p->cache;\n+    do\n+    {\n+      Byte *buf = p->buf;\n+      *buf++ = (Byte)(temp + (Byte)(p->low >> 32));\n+      p->buf = buf;\n+      if (buf == p->bufLim)\n+        RangeEnc_FlushStream(p);\n+      temp = 0xFF;\n+    }\n+    while (--p->cacheSize != 0);\n+    p->cache = (Byte)((UInt32)p->low >> 24);\n+  }\n+  p->cacheSize++;\n+  p->low = (UInt32)p->low << 8;\n+}\n+\n+static void RangeEnc_FlushData(CRangeEnc *p)\n+{\n+  int i;\n+  for (i = 0; i < 5; i++)\n+    RangeEnc_ShiftLow(p);\n+}\n+\n+static void RangeEnc_EncodeDirectBits(CRangeEnc *p, UInt32 value, int numBits)\n+{\n+  do\n+  {\n+    p->range >>= 1;\n+    p->low += p->range & (0 - ((value >> --numBits) & 1));\n+    if (p->range < kTopValue)\n+    {\n+      p->range <<= 8;\n+      RangeEnc_ShiftLow(p);\n+    }\n+  }\n+  while (numBits != 0);\n+}\n+\n+static void RangeEnc_EncodeBit(CRangeEnc *p, CLzmaProb *prob, UInt32 symbol)\n+{\n+  UInt32 ttt = *prob;\n+  UInt32 newBound = (p->range >> kNumBitModelTotalBits) * ttt;\n+  if (symbol == 0)\n+  {\n+    p->range = newBound;\n+    ttt += (kBitModelTotal - ttt) >> kNumMoveBits;\n+  }\n+  else\n+  {\n+    p->low += newBound;\n+    p->range -= newBound;\n+    ttt -= ttt >> kNumMoveBits;\n+  }\n+  *prob = (CLzmaProb)ttt;\n+  if (p->range < kTopValue)\n+  {\n+    p->range <<= 8;\n+    RangeEnc_ShiftLow(p);\n+  }\n+}\n+\n+static void LitEnc_Encode(CRangeEnc *p, CLzmaProb *probs, UInt32 symbol)\n+{\n+  symbol |= 0x100;\n+  do\n+  {\n+    RangeEnc_EncodeBit(p, probs + (symbol >> 8), (symbol >> 7) & 1);\n+    symbol <<= 1;\n+  }\n+  while (symbol < 0x10000);\n+}\n+\n+static void LitEnc_EncodeMatched(CRangeEnc *p, CLzmaProb *probs, UInt32 symbol, UInt32 matchByte)\n+{\n+  UInt32 offs = 0x100;\n+  symbol |= 0x100;\n+  do\n+  {\n+    matchByte <<= 1;\n+    RangeEnc_EncodeBit(p, probs + (offs + (matchByte & offs) + (symbol >> 8)), (symbol >> 7) & 1);\n+    symbol <<= 1;\n+    offs &= ~(matchByte ^ symbol);\n+  }\n+  while (symbol < 0x10000);\n+}\n+\n+void LzmaEnc_InitPriceTables(UInt32 *ProbPrices)\n+{\n+  UInt32 i;\n+  for (i = (1 << kNumMoveReducingBits) / 2; i < kBitModelTotal; i += (1 << kNumMoveReducingBits))\n+  {\n+    const int kCyclesBits = kNumBitPriceShiftBits;\n+    UInt32 w = i;\n+    UInt32 bitCount = 0;\n+    int j;\n+    for (j = 0; j < kCyclesBits; j++)\n+    {\n+      w = w * w;\n+      bitCount <<= 1;\n+      while (w >= ((UInt32)1 << 16))\n+      {\n+        w >>= 1;\n+        bitCount++;\n+      }\n+    }\n+    ProbPrices[i >> kNumMoveReducingBits] = ((kNumBitModelTotalBits << kCyclesBits) - 15 - bitCount);\n+  }\n+}\n+\n+\n+#define GET_PRICE(prob, symbol) \\\n+  p->ProbPrices[((prob) ^ (((-(int)(symbol))) & (kBitModelTotal - 1))) >> kNumMoveReducingBits];\n+\n+#define GET_PRICEa(prob, symbol) \\\n+  ProbPrices[((prob) ^ ((-((int)(symbol))) & (kBitModelTotal - 1))) >> kNumMoveReducingBits];\n+\n+#define GET_PRICE_0(prob) p->ProbPrices[(prob) >> kNumMoveReducingBits]\n+#define GET_PRICE_1(prob) p->ProbPrices[((prob) ^ (kBitModelTotal - 1)) >> kNumMoveReducingBits]\n+\n+#define GET_PRICE_0a(prob) ProbPrices[(prob) >> kNumMoveReducingBits]\n+#define GET_PRICE_1a(prob) ProbPrices[((prob) ^ (kBitModelTotal - 1)) >> kNumMoveReducingBits]\n+\n+static UInt32 LitEnc_GetPrice(const CLzmaProb *probs, UInt32 symbol, UInt32 *ProbPrices)\n+{\n+  UInt32 price = 0;\n+  symbol |= 0x100;\n+  do\n+  {\n+    price += GET_PRICEa(probs[symbol >> 8], (symbol >> 7) & 1);\n+    symbol <<= 1;\n+  }\n+  while (symbol < 0x10000);\n+  return price;\n+}\n+\n+static UInt32 LitEnc_GetPriceMatched(const CLzmaProb *probs, UInt32 symbol, UInt32 matchByte, UInt32 *ProbPrices)\n+{\n+  UInt32 price = 0;\n+  UInt32 offs = 0x100;\n+  symbol |= 0x100;\n+  do\n+  {\n+    matchByte <<= 1;\n+    price += GET_PRICEa(probs[offs + (matchByte & offs) + (symbol >> 8)], (symbol >> 7) & 1);\n+    symbol <<= 1;\n+    offs &= ~(matchByte ^ symbol);\n+  }\n+  while (symbol < 0x10000);\n+  return price;\n+}\n+\n+\n+static void RcTree_Encode(CRangeEnc *rc, CLzmaProb *probs, int numBitLevels, UInt32 symbol)\n+{\n+  UInt32 m = 1;\n+  int i;\n+  for (i = numBitLevels; i != 0;)\n+  {\n+    UInt32 bit;\n+    i--;\n+    bit = (symbol >> i) & 1;\n+    RangeEnc_EncodeBit(rc, probs + m, bit);\n+    m = (m << 1) | bit;\n+  }\n+}\n+\n+static void RcTree_ReverseEncode(CRangeEnc *rc, CLzmaProb *probs, int numBitLevels, UInt32 symbol)\n+{\n+  UInt32 m = 1;\n+  int i;\n+  for (i = 0; i < numBitLevels; i++)\n+  {\n+    UInt32 bit = symbol & 1;\n+    RangeEnc_EncodeBit(rc, probs + m, bit);\n+    m = (m << 1) | bit;\n+    symbol >>= 1;\n+  }\n+}\n+\n+static UInt32 RcTree_GetPrice(const CLzmaProb *probs, int numBitLevels, UInt32 symbol, UInt32 *ProbPrices)\n+{\n+  UInt32 price = 0;\n+  symbol |= (1 << numBitLevels);\n+  while (symbol != 1)\n+  {\n+    price += GET_PRICEa(probs[symbol >> 1], symbol & 1);\n+    symbol >>= 1;\n+  }\n+  return price;\n+}\n+\n+static UInt32 RcTree_ReverseGetPrice(const CLzmaProb *probs, int numBitLevels, UInt32 symbol, UInt32 *ProbPrices)\n+{\n+  UInt32 price = 0;\n+  UInt32 m = 1;\n+  int i;\n+  for (i = numBitLevels; i != 0; i--)\n+  {\n+    UInt32 bit = symbol & 1;\n+    symbol >>= 1;\n+    price += GET_PRICEa(probs[m], bit);\n+    m = (m << 1) | bit;\n+  }\n+  return price;\n+}\n+\n+\n+static void LenEnc_Init(CLenEnc *p)\n+{\n+  unsigned i;\n+  p->choice = p->choice2 = kProbInitValue;\n+  for (i = 0; i < (LZMA_NUM_PB_STATES_MAX << kLenNumLowBits); i++)\n+    p->low[i] = kProbInitValue;\n+  for (i = 0; i < (LZMA_NUM_PB_STATES_MAX << kLenNumMidBits); i++)\n+    p->mid[i] = kProbInitValue;\n+  for (i = 0; i < kLenNumHighSymbols; i++)\n+    p->high[i] = kProbInitValue;\n+}\n+\n+static void LenEnc_Encode(CLenEnc *p, CRangeEnc *rc, UInt32 symbol, UInt32 posState)\n+{\n+  if (symbol < kLenNumLowSymbols)\n+  {\n+    RangeEnc_EncodeBit(rc, &p->choice, 0);\n+    RcTree_Encode(rc, p->low + (posState << kLenNumLowBits), kLenNumLowBits, symbol);\n+  }\n+  else\n+  {\n+    RangeEnc_EncodeBit(rc, &p->choice, 1);\n+    if (symbol < kLenNumLowSymbols + kLenNumMidSymbols)\n+    {\n+      RangeEnc_EncodeBit(rc, &p->choice2, 0);\n+      RcTree_Encode(rc, p->mid + (posState << kLenNumMidBits), kLenNumMidBits, symbol - kLenNumLowSymbols);\n+    }\n+    else\n+    {\n+      RangeEnc_EncodeBit(rc, &p->choice2, 1);\n+      RcTree_Encode(rc, p->high, kLenNumHighBits, symbol - kLenNumLowSymbols - kLenNumMidSymbols);\n+    }\n+  }\n+}\n+\n+static void LenEnc_SetPrices(CLenEnc *p, UInt32 posState, UInt32 numSymbols, UInt32 *prices, UInt32 *ProbPrices)\n+{\n+  UInt32 a0 = GET_PRICE_0a(p->choice);\n+  UInt32 a1 = GET_PRICE_1a(p->choice);\n+  UInt32 b0 = a1 + GET_PRICE_0a(p->choice2);\n+  UInt32 b1 = a1 + GET_PRICE_1a(p->choice2);\n+  UInt32 i = 0;\n+  for (i = 0; i < kLenNumLowSymbols; i++)\n+  {\n+    if (i >= numSymbols)\n+      return;\n+    prices[i] = a0 + RcTree_GetPrice(p->low + (posState << kLenNumLowBits), kLenNumLowBits, i, ProbPrices);\n+  }\n+  for (; i < kLenNumLowSymbols + kLenNumMidSymbols; i++)\n+  {\n+    if (i >= numSymbols)\n+      return;\n+    prices[i] = b0 + RcTree_GetPrice(p->mid + (posState << kLenNumMidBits), kLenNumMidBits, i - kLenNumLowSymbols, ProbPrices);\n+  }\n+  for (; i < numSymbols; i++)\n+    prices[i] = b1 + RcTree_GetPrice(p->high, kLenNumHighBits, i - kLenNumLowSymbols - kLenNumMidSymbols, ProbPrices);\n+}\n+\n+static void MY_FAST_CALL LenPriceEnc_UpdateTable(CLenPriceEnc *p, UInt32 posState, UInt32 *ProbPrices)\n+{\n+  LenEnc_SetPrices(&p->p, posState, p->tableSize, p->prices[posState], ProbPrices);\n+  p->counters[posState] = p->tableSize;\n+}\n+\n+static void LenPriceEnc_UpdateTables(CLenPriceEnc *p, UInt32 numPosStates, UInt32 *ProbPrices)\n+{\n+  UInt32 posState;\n+  for (posState = 0; posState < numPosStates; posState++)\n+    LenPriceEnc_UpdateTable(p, posState, ProbPrices);\n+}\n+\n+static void LenEnc_Encode2(CLenPriceEnc *p, CRangeEnc *rc, UInt32 symbol, UInt32 posState, Bool updatePrice, UInt32 *ProbPrices)\n+{\n+  LenEnc_Encode(&p->p, rc, symbol, posState);\n+  if (updatePrice)\n+    if (--p->counters[posState] == 0)\n+      LenPriceEnc_UpdateTable(p, posState, ProbPrices);\n+}\n+\n+\n+\n+\n+static void MovePos(CLzmaEnc *p, UInt32 num)\n+{\n+  #ifdef SHOW_STAT\n+  ttt += num;\n+  printf(\"\\n MovePos %d\", num);\n+  #endif\n+  if (num != 0)\n+  {\n+    p->additionalOffset += num;\n+    p->matchFinder.Skip(p->matchFinderObj, num);\n+  }\n+}\n+\n+static UInt32 ReadMatchDistances(CLzmaEnc *p, UInt32 *numDistancePairsRes)\n+{\n+  UInt32 lenRes = 0, numPairs;\n+  p->numAvail = p->matchFinder.GetNumAvailableBytes(p->matchFinderObj);\n+  numPairs = p->matchFinder.GetMatches(p->matchFinderObj, p->matches);\n+  #ifdef SHOW_STAT\n+  printf(\"\\n i = %d numPairs = %d    \", ttt, numPairs / 2);\n+  ttt++;\n+  {\n+    UInt32 i;\n+    for (i = 0; i < numPairs; i += 2)\n+      printf(\"%2d %6d   | \", p->matches[i], p->matches[i + 1]);\n+  }\n+  #endif\n+  if (numPairs > 0)\n+  {\n+    lenRes = p->matches[numPairs - 2];\n+    if (lenRes == p->numFastBytes)\n+    {\n+      const Byte *pby = p->matchFinder.GetPointerToCurrentPos(p->matchFinderObj) - 1;\n+      UInt32 distance = p->matches[numPairs - 1] + 1;\n+      UInt32 numAvail = p->numAvail;\n+      if (numAvail > LZMA_MATCH_LEN_MAX)\n+        numAvail = LZMA_MATCH_LEN_MAX;\n+      {\n+        const Byte *pby2 = pby - distance;\n+        for (; lenRes < numAvail && pby[lenRes] == pby2[lenRes]; lenRes++);\n+      }\n+    }\n+  }\n+  p->additionalOffset++;\n+  *numDistancePairsRes = numPairs;\n+  return lenRes;\n+}\n+\n+\n+#define MakeAsChar(p) (p)->backPrev = (UInt32)(-1); (p)->prev1IsChar = False;\n+#define MakeAsShortRep(p) (p)->backPrev = 0; (p)->prev1IsChar = False;\n+#define IsShortRep(p) ((p)->backPrev == 0)\n+\n+static UInt32 GetRepLen1Price(CLzmaEnc *p, UInt32 state, UInt32 posState)\n+{\n+  return\n+    GET_PRICE_0(p->isRepG0[state]) +\n+    GET_PRICE_0(p->isRep0Long[state][posState]);\n+}\n+\n+static UInt32 GetPureRepPrice(CLzmaEnc *p, UInt32 repIndex, UInt32 state, UInt32 posState)\n+{\n+  UInt32 price;\n+  if (repIndex == 0)\n+  {\n+    price = GET_PRICE_0(p->isRepG0[state]);\n+    price += GET_PRICE_1(p->isRep0Long[state][posState]);\n+  }\n+  else\n+  {\n+    price = GET_PRICE_1(p->isRepG0[state]);\n+    if (repIndex == 1)\n+      price += GET_PRICE_0(p->isRepG1[state]);\n+    else\n+    {\n+      price += GET_PRICE_1(p->isRepG1[state]);\n+      price += GET_PRICE(p->isRepG2[state], repIndex - 2);\n+    }\n+  }\n+  return price;\n+}\n+\n+static UInt32 GetRepPrice(CLzmaEnc *p, UInt32 repIndex, UInt32 len, UInt32 state, UInt32 posState)\n+{\n+  return p->repLenEnc.prices[posState][len - LZMA_MATCH_LEN_MIN] +\n+    GetPureRepPrice(p, repIndex, state, posState);\n+}\n+\n+static UInt32 Backward(CLzmaEnc *p, UInt32 *backRes, UInt32 cur)\n+{\n+  UInt32 posMem = p->opt[cur].posPrev;\n+  UInt32 backMem = p->opt[cur].backPrev;\n+  p->optimumEndIndex = cur;\n+  do\n+  {\n+    if (p->opt[cur].prev1IsChar)\n+    {\n+      MakeAsChar(&p->opt[posMem])\n+      p->opt[posMem].posPrev = posMem - 1;\n+      if (p->opt[cur].prev2)\n+      {\n+        p->opt[posMem - 1].prev1IsChar = False;\n+        p->opt[posMem - 1].posPrev = p->opt[cur].posPrev2;\n+        p->opt[posMem - 1].backPrev = p->opt[cur].backPrev2;\n+      }\n+    }\n+    {\n+      UInt32 posPrev = posMem;\n+      UInt32 backCur = backMem;\n+\n+      backMem = p->opt[posPrev].backPrev;\n+      posMem = p->opt[posPrev].posPrev;\n+\n+      p->opt[posPrev].backPrev = backCur;\n+      p->opt[posPrev].posPrev = cur;\n+      cur = posPrev;\n+    }\n+  }\n+  while (cur != 0);\n+  *backRes = p->opt[0].backPrev;\n+  p->optimumCurrentIndex  = p->opt[0].posPrev;\n+  return p->optimumCurrentIndex;\n+}\n+\n+#define LIT_PROBS(pos, prevByte) (p->litProbs + ((((pos) & p->lpMask) << p->lc) + ((prevByte) >> (8 - p->lc))) * 0x300)\n+\n+static UInt32 GetOptimum(CLzmaEnc *p, UInt32 position, UInt32 *backRes)\n+{\n+  UInt32 numAvail, mainLen, numPairs, repMaxIndex, i, posState, lenEnd, len, cur;\n+  UInt32 matchPrice, repMatchPrice, normalMatchPrice;\n+  UInt32 reps[LZMA_NUM_REPS], repLens[LZMA_NUM_REPS];\n+  UInt32 *matches;\n+  const Byte *data;\n+  Byte curByte, matchByte;\n+  if (p->optimumEndIndex != p->optimumCurrentIndex)\n+  {\n+    const COptimal *opt = &p->opt[p->optimumCurrentIndex];\n+    UInt32 lenRes = opt->posPrev - p->optimumCurrentIndex;\n+    *backRes = opt->backPrev;\n+    p->optimumCurrentIndex = opt->posPrev;\n+    return lenRes;\n+  }\n+  p->optimumCurrentIndex = p->optimumEndIndex = 0;\n+\n+  if (p->additionalOffset == 0)\n+    mainLen = ReadMatchDistances(p, &numPairs);\n+  else\n+  {\n+    mainLen = p->longestMatchLength;\n+    numPairs = p->numPairs;\n+  }\n+\n+  numAvail = p->numAvail;\n+  if (numAvail < 2)\n+  {\n+    *backRes = (UInt32)(-1);\n+    return 1;\n+  }\n+  if (numAvail > LZMA_MATCH_LEN_MAX)\n+    numAvail = LZMA_MATCH_LEN_MAX;\n+\n+  data = p->matchFinder.GetPointerToCurrentPos(p->matchFinderObj) - 1;\n+  repMaxIndex = 0;\n+  for (i = 0; i < LZMA_NUM_REPS; i++)\n+  {\n+    UInt32 lenTest;\n+    const Byte *data2;\n+    reps[i] = p->reps[i];\n+    data2 = data - (reps[i] + 1);\n+    if (data[0] != data2[0] || data[1] != data2[1])\n+    {\n+      repLens[i] = 0;\n+      continue;\n+    }\n+    for (lenTest = 2; lenTest < numAvail && data[lenTest] == data2[lenTest]; lenTest++);\n+    repLens[i] = lenTest;\n+    if (lenTest > repLens[repMaxIndex])\n+      repMaxIndex = i;\n+  }\n+  if (repLens[repMaxIndex] >= p->numFastBytes)\n+  {\n+    UInt32 lenRes;\n+    *backRes = repMaxIndex;\n+    lenRes = repLens[repMaxIndex];\n+    MovePos(p, lenRes - 1);\n+    return lenRes;\n+  }\n+\n+  matches = p->matches;\n+  if (mainLen >= p->numFastBytes)\n+  {\n+    *backRes = matches[numPairs - 1] + LZMA_NUM_REPS;\n+    MovePos(p, mainLen - 1);\n+    return mainLen;\n+  }\n+  curByte = *data;\n+  matchByte = *(data - (reps[0] + 1));\n+\n+  if (mainLen < 2 && curByte != matchByte && repLens[repMaxIndex] < 2)\n+  {\n+    *backRes = (UInt32)-1;\n+    return 1;\n+  }\n+\n+  p->opt[0].state = (CState)p->state;\n+\n+  posState = (position & p->pbMask);\n+\n+  {\n+    const CLzmaProb *probs = LIT_PROBS(position, *(data - 1));\n+    p->opt[1].price = GET_PRICE_0(p->isMatch[p->state][posState]) +\n+        (!IsCharState(p->state) ?\n+          LitEnc_GetPriceMatched(probs, curByte, matchByte, p->ProbPrices) :\n+          LitEnc_GetPrice(probs, curByte, p->ProbPrices));\n+  }\n+\n+  MakeAsChar(&p->opt[1]);\n+\n+  matchPrice = GET_PRICE_1(p->isMatch[p->state][posState]);\n+  repMatchPrice = matchPrice + GET_PRICE_1(p->isRep[p->state]);\n+\n+  if (matchByte == curByte)\n+  {\n+    UInt32 shortRepPrice = repMatchPrice + GetRepLen1Price(p, p->state, posState);\n+    if (shortRepPrice < p->opt[1].price)\n+    {\n+      p->opt[1].price = shortRepPrice;\n+      MakeAsShortRep(&p->opt[1]);\n+    }\n+  }\n+  lenEnd = ((mainLen >= repLens[repMaxIndex]) ? mainLen : repLens[repMaxIndex]);\n+\n+  if (lenEnd < 2)\n+  {\n+    *backRes = p->opt[1].backPrev;\n+    return 1;\n+  }\n+\n+  p->opt[1].posPrev = 0;\n+  for (i = 0; i < LZMA_NUM_REPS; i++)\n+    p->opt[0].backs[i] = reps[i];\n+\n+  len = lenEnd;\n+  do\n+    p->opt[len--].price = kInfinityPrice;\n+  while (len >= 2);\n+\n+  for (i = 0; i < LZMA_NUM_REPS; i++)\n+  {\n+    UInt32 repLen = repLens[i];\n+    UInt32 price;\n+    if (repLen < 2)\n+      continue;\n+    price = repMatchPrice + GetPureRepPrice(p, i, p->state, posState);\n+    do\n+    {\n+      UInt32 curAndLenPrice = price + p->repLenEnc.prices[posState][repLen - 2];\n+      COptimal *opt = &p->opt[repLen];\n+      if (curAndLenPrice < opt->price)\n+      {\n+        opt->price = curAndLenPrice;\n+        opt->posPrev = 0;\n+        opt->backPrev = i;\n+        opt->prev1IsChar = False;\n+      }\n+    }\n+    while (--repLen >= 2);\n+  }\n+\n+  normalMatchPrice = matchPrice + GET_PRICE_0(p->isRep[p->state]);\n+\n+  len = ((repLens[0] >= 2) ? repLens[0] + 1 : 2);\n+  if (len <= mainLen)\n+  {\n+    UInt32 offs = 0;\n+    while (len > matches[offs])\n+      offs += 2;\n+    for (; ; len++)\n+    {\n+      COptimal *opt;\n+      UInt32 distance = matches[offs + 1];\n+\n+      UInt32 curAndLenPrice = normalMatchPrice + p->lenEnc.prices[posState][len - LZMA_MATCH_LEN_MIN];\n+      UInt32 lenToPosState = GetLenToPosState(len);\n+      if (distance < kNumFullDistances)\n+        curAndLenPrice += p->distancesPrices[lenToPosState][distance];\n+      else\n+      {\n+        UInt32 slot;\n+        GetPosSlot2(distance, slot);\n+        curAndLenPrice += p->alignPrices[distance & kAlignMask] + p->posSlotPrices[lenToPosState][slot];\n+      }\n+      opt = &p->opt[len];\n+      if (curAndLenPrice < opt->price)\n+      {\n+        opt->price = curAndLenPrice;\n+        opt->posPrev = 0;\n+        opt->backPrev = distance + LZMA_NUM_REPS;\n+        opt->prev1IsChar = False;\n+      }\n+      if (len == matches[offs])\n+      {\n+        offs += 2;\n+        if (offs == numPairs)\n+          break;\n+      }\n+    }\n+  }\n+\n+  cur = 0;\n+\n+    #ifdef SHOW_STAT2\n+    if (position >= 0)\n+    {\n+      unsigned i;\n+      printf(\"\\n pos = %4X\", position);\n+      for (i = cur; i <= lenEnd; i++)\n+      printf(\"\\nprice[%4X] = %d\", position - cur + i, p->opt[i].price);\n+    }\n+    #endif\n+\n+  for (;;)\n+  {\n+    UInt32 numAvailFull, newLen, numPairs, posPrev, state, posState, startLen;\n+    UInt32 curPrice, curAnd1Price, matchPrice, repMatchPrice;\n+    Bool nextIsChar;\n+    Byte curByte, matchByte;\n+    const Byte *data;\n+    COptimal *curOpt;\n+    COptimal *nextOpt;\n+\n+    cur++;\n+    if (cur == lenEnd)\n+      return Backward(p, backRes, cur);\n+\n+    newLen = ReadMatchDistances(p, &numPairs);\n+    if (newLen >= p->numFastBytes)\n+    {\n+      p->numPairs = numPairs;\n+      p->longestMatchLength = newLen;\n+      return Backward(p, backRes, cur);\n+    }\n+    position++;\n+    curOpt = &p->opt[cur];\n+    posPrev = curOpt->posPrev;\n+    if (curOpt->prev1IsChar)\n+    {\n+      posPrev--;\n+      if (curOpt->prev2)\n+      {\n+        state = p->opt[curOpt->posPrev2].state;\n+        if (curOpt->backPrev2 < LZMA_NUM_REPS)\n+          state = kRepNextStates[state];\n+        else\n+          state = kMatchNextStates[state];\n+      }\n+      else\n+        state = p->opt[posPrev].state;\n+      state = kLiteralNextStates[state];\n+    }\n+    else\n+      state = p->opt[posPrev].state;\n+    if (posPrev == cur - 1)\n+    {\n+      if (IsShortRep(curOpt))\n+        state = kShortRepNextStates[state];\n+      else\n+        state = kLiteralNextStates[state];\n+    }\n+    else\n+    {\n+      UInt32 pos;\n+      const COptimal *prevOpt;\n+      if (curOpt->prev1IsChar && curOpt->prev2)\n+      {\n+        posPrev = curOpt->posPrev2;\n+        pos = curOpt->backPrev2;\n+        state = kRepNextStates[state];\n+      }\n+      else\n+      {\n+        pos = curOpt->backPrev;\n+        if (pos < LZMA_NUM_REPS)\n+          state = kRepNextStates[state];\n+        else\n+          state = kMatchNextStates[state];\n+      }\n+      prevOpt = &p->opt[posPrev];\n+      if (pos < LZMA_NUM_REPS)\n+      {\n+        UInt32 i;\n+        reps[0] = prevOpt->backs[pos];\n+        for (i = 1; i <= pos; i++)\n+          reps[i] = prevOpt->backs[i - 1];\n+        for (; i < LZMA_NUM_REPS; i++)\n+          reps[i] = prevOpt->backs[i];\n+      }\n+      else\n+      {\n+        UInt32 i;\n+        reps[0] = (pos - LZMA_NUM_REPS);\n+        for (i = 1; i < LZMA_NUM_REPS; i++)\n+          reps[i] = prevOpt->backs[i - 1];\n+      }\n+    }\n+    curOpt->state = (CState)state;\n+\n+    curOpt->backs[0] = reps[0];\n+    curOpt->backs[1] = reps[1];\n+    curOpt->backs[2] = reps[2];\n+    curOpt->backs[3] = reps[3];\n+\n+    curPrice = curOpt->price;\n+    nextIsChar = False;\n+    data = p->matchFinder.GetPointerToCurrentPos(p->matchFinderObj) - 1;\n+    curByte = *data;\n+    matchByte = *(data - (reps[0] + 1));\n+\n+    posState = (position & p->pbMask);\n+\n+    curAnd1Price = curPrice + GET_PRICE_0(p->isMatch[state][posState]);\n+    {\n+      const CLzmaProb *probs = LIT_PROBS(position, *(data - 1));\n+      curAnd1Price +=\n+        (!IsCharState(state) ?\n+          LitEnc_GetPriceMatched(probs, curByte, matchByte, p->ProbPrices) :\n+          LitEnc_GetPrice(probs, curByte, p->ProbPrices));\n+    }\n+\n+    nextOpt = &p->opt[cur + 1];\n+\n+    if (curAnd1Price < nextOpt->price)\n+    {\n+      nextOpt->price = curAnd1Price;\n+      nextOpt->posPrev = cur;\n+      MakeAsChar(nextOpt);\n+      nextIsChar = True;\n+    }\n+\n+    matchPrice = curPrice + GET_PRICE_1(p->isMatch[state][posState]);\n+    repMatchPrice = matchPrice + GET_PRICE_1(p->isRep[state]);\n+\n+    if (matchByte == curByte && !(nextOpt->posPrev < cur && nextOpt->backPrev == 0))\n+    {\n+      UInt32 shortRepPrice = repMatchPrice + GetRepLen1Price(p, state, posState);\n+      if (shortRepPrice <= nextOpt->price)\n+      {\n+        nextOpt->price = shortRepPrice;\n+        nextOpt->posPrev = cur;\n+        MakeAsShortRep(nextOpt);\n+        nextIsChar = True;\n+      }\n+    }\n+    numAvailFull = p->numAvail;\n+    {\n+      UInt32 temp = kNumOpts - 1 - cur;\n+      if (temp < numAvailFull)\n+        numAvailFull = temp;\n+    }\n+\n+    if (numAvailFull < 2)\n+      continue;\n+    numAvail = (numAvailFull <= p->numFastBytes ? numAvailFull : p->numFastBytes);\n+\n+    if (!nextIsChar && matchByte != curByte) /* speed optimization */\n+    {\n+      /* try Literal + rep0 */\n+      UInt32 temp;\n+      UInt32 lenTest2;\n+      const Byte *data2 = data - (reps[0] + 1);\n+      UInt32 limit = p->numFastBytes + 1;\n+      if (limit > numAvailFull)\n+        limit = numAvailFull;\n+\n+      for (temp = 1; temp < limit && data[temp] == data2[temp]; temp++);\n+      lenTest2 = temp - 1;\n+      if (lenTest2 >= 2)\n+      {\n+        UInt32 state2 = kLiteralNextStates[state];\n+        UInt32 posStateNext = (position + 1) & p->pbMask;\n+        UInt32 nextRepMatchPrice = curAnd1Price +\n+            GET_PRICE_1(p->isMatch[state2][posStateNext]) +\n+            GET_PRICE_1(p->isRep[state2]);\n+        /* for (; lenTest2 >= 2; lenTest2--) */\n+        {\n+          UInt32 curAndLenPrice;\n+          COptimal *opt;\n+          UInt32 offset = cur + 1 + lenTest2;\n+          while (lenEnd < offset)\n+            p->opt[++lenEnd].price = kInfinityPrice;\n+          curAndLenPrice = nextRepMatchPrice + GetRepPrice(p, 0, lenTest2, state2, posStateNext);\n+          opt = &p->opt[offset];\n+          if (curAndLenPrice < opt->price)\n+          {\n+            opt->price = curAndLenPrice;\n+            opt->posPrev = cur + 1;\n+            opt->backPrev = 0;\n+            opt->prev1IsChar = True;\n+            opt->prev2 = False;\n+          }\n+        }\n+      }\n+    }\n+\n+    startLen = 2; /* speed optimization */\n+    {\n+    UInt32 repIndex;\n+    for (repIndex = 0; repIndex < LZMA_NUM_REPS; repIndex++)\n+    {\n+      UInt32 lenTest;\n+      UInt32 lenTestTemp;\n+      UInt32 price;\n+      const Byte *data2 = data - (reps[repIndex] + 1);\n+      if (data[0] != data2[0] || data[1] != data2[1])\n+        continue;\n+      for (lenTest = 2; lenTest < numAvail && data[lenTest] == data2[lenTest]; lenTest++);\n+      while (lenEnd < cur + lenTest)\n+        p->opt[++lenEnd].price = kInfinityPrice;\n+      lenTestTemp = lenTest;\n+      price = repMatchPrice + GetPureRepPrice(p, repIndex, state, posState);\n+      do\n+      {\n+        UInt32 curAndLenPrice = price + p->repLenEnc.prices[posState][lenTest - 2];\n+        COptimal *opt = &p->opt[cur + lenTest];\n+        if (curAndLenPrice < opt->price)\n+        {\n+          opt->price = curAndLenPrice;\n+          opt->posPrev = cur;\n+          opt->backPrev = repIndex;\n+          opt->prev1IsChar = False;\n+        }\n+      }\n+      while (--lenTest >= 2);\n+      lenTest = lenTestTemp;\n+\n+      if (repIndex == 0)\n+        startLen = lenTest + 1;\n+\n+      /* if (_maxMode) */\n+        {\n+          UInt32 lenTest2 = lenTest + 1;\n+          UInt32 limit = lenTest2 + p->numFastBytes;\n+          UInt32 nextRepMatchPrice;\n+          if (limit > numAvailFull)\n+            limit = numAvailFull;\n+          for (; lenTest2 < limit && data[lenTest2] == data2[lenTest2]; lenTest2++);\n+          lenTest2 -= lenTest + 1;\n+          if (lenTest2 >= 2)\n+          {\n+            UInt32 state2 = kRepNextStates[state];\n+            UInt32 posStateNext = (position + lenTest) & p->pbMask;\n+            UInt32 curAndLenCharPrice =\n+                price + p->repLenEnc.prices[posState][lenTest - 2] +\n+                GET_PRICE_0(p->isMatch[state2][posStateNext]) +\n+                LitEnc_GetPriceMatched(LIT_PROBS(position + lenTest, data[lenTest - 1]),\n+                    data[lenTest], data2[lenTest], p->ProbPrices);\n+            state2 = kLiteralNextStates[state2];\n+            posStateNext = (position + lenTest + 1) & p->pbMask;\n+            nextRepMatchPrice = curAndLenCharPrice +\n+                GET_PRICE_1(p->isMatch[state2][posStateNext]) +\n+                GET_PRICE_1(p->isRep[state2]);\n+\n+            /* for (; lenTest2 >= 2; lenTest2--) */\n+            {\n+              UInt32 curAndLenPrice;\n+              COptimal *opt;\n+              UInt32 offset = cur + lenTest + 1 + lenTest2;\n+              while (lenEnd < offset)\n+                p->opt[++lenEnd].price = kInfinityPrice;\n+              curAndLenPrice = nextRepMatchPrice + GetRepPrice(p, 0, lenTest2, state2, posStateNext);\n+              opt = &p->opt[offset];\n+              if (curAndLenPrice < opt->price)\n+              {\n+                opt->price = curAndLenPrice;\n+                opt->posPrev = cur + lenTest + 1;\n+                opt->backPrev = 0;\n+                opt->prev1IsChar = True;\n+                opt->prev2 = True;\n+                opt->posPrev2 = cur;\n+                opt->backPrev2 = repIndex;\n+              }\n+            }\n+          }\n+        }\n+    }\n+    }\n+    /* for (UInt32 lenTest = 2; lenTest <= newLen; lenTest++) */\n+    if (newLen > numAvail)\n+    {\n+      newLen = numAvail;\n+      for (numPairs = 0; newLen > matches[numPairs]; numPairs += 2);\n+      matches[numPairs] = newLen;\n+      numPairs += 2;\n+    }\n+    if (newLen >= startLen)\n+    {\n+      UInt32 normalMatchPrice = matchPrice + GET_PRICE_0(p->isRep[state]);\n+      UInt32 offs, curBack, posSlot;\n+      UInt32 lenTest;\n+      while (lenEnd < cur + newLen)\n+        p->opt[++lenEnd].price = kInfinityPrice;\n+\n+      offs = 0;\n+      while (startLen > matches[offs])\n+        offs += 2;\n+      curBack = matches[offs + 1];\n+      GetPosSlot2(curBack, posSlot);\n+      for (lenTest = /*2*/ startLen; ; lenTest++)\n+      {\n+        UInt32 curAndLenPrice = normalMatchPrice + p->lenEnc.prices[posState][lenTest - LZMA_MATCH_LEN_MIN];\n+        UInt32 lenToPosState = GetLenToPosState(lenTest);\n+        COptimal *opt;\n+        if (curBack < kNumFullDistances)\n+          curAndLenPrice += p->distancesPrices[lenToPosState][curBack];\n+        else\n+          curAndLenPrice += p->posSlotPrices[lenToPosState][posSlot] + p->alignPrices[curBack & kAlignMask];\n+\n+        opt = &p->opt[cur + lenTest];\n+        if (curAndLenPrice < opt->price)\n+        {\n+          opt->price = curAndLenPrice;\n+          opt->posPrev = cur;\n+          opt->backPrev = curBack + LZMA_NUM_REPS;\n+          opt->prev1IsChar = False;\n+        }\n+\n+        if (/*_maxMode && */lenTest == matches[offs])\n+        {\n+          /* Try Match + Literal + Rep0 */\n+          const Byte *data2 = data - (curBack + 1);\n+          UInt32 lenTest2 = lenTest + 1;\n+          UInt32 limit = lenTest2 + p->numFastBytes;\n+          UInt32 nextRepMatchPrice;\n+          if (limit > numAvailFull)\n+            limit = numAvailFull;\n+          for (; lenTest2 < limit && data[lenTest2] == data2[lenTest2]; lenTest2++);\n+          lenTest2 -= lenTest + 1;\n+          if (lenTest2 >= 2)\n+          {\n+            UInt32 state2 = kMatchNextStates[state];\n+            UInt32 posStateNext = (position + lenTest) & p->pbMask;\n+            UInt32 curAndLenCharPrice = curAndLenPrice +\n+                GET_PRICE_0(p->isMatch[state2][posStateNext]) +\n+                LitEnc_GetPriceMatched(LIT_PROBS(position + lenTest, data[lenTest - 1]),\n+                    data[lenTest], data2[lenTest], p->ProbPrices);\n+            state2 = kLiteralNextStates[state2];\n+            posStateNext = (posStateNext + 1) & p->pbMask;\n+            nextRepMatchPrice = curAndLenCharPrice +\n+                GET_PRICE_1(p->isMatch[state2][posStateNext]) +\n+                GET_PRICE_1(p->isRep[state2]);\n+\n+            /* for (; lenTest2 >= 2; lenTest2--) */\n+            {\n+              UInt32 offset = cur + lenTest + 1 + lenTest2;\n+              UInt32 curAndLenPrice;\n+              COptimal *opt;\n+              while (lenEnd < offset)\n+                p->opt[++lenEnd].price = kInfinityPrice;\n+              curAndLenPrice = nextRepMatchPrice + GetRepPrice(p, 0, lenTest2, state2, posStateNext);\n+              opt = &p->opt[offset];\n+              if (curAndLenPrice < opt->price)\n+              {\n+                opt->price = curAndLenPrice;\n+                opt->posPrev = cur + lenTest + 1;\n+                opt->backPrev = 0;\n+                opt->prev1IsChar = True;\n+                opt->prev2 = True;\n+                opt->posPrev2 = cur;\n+                opt->backPrev2 = curBack + LZMA_NUM_REPS;\n+              }\n+            }\n+          }\n+          offs += 2;\n+          if (offs == numPairs)\n+            break;\n+          curBack = matches[offs + 1];\n+          if (curBack >= kNumFullDistances)\n+            GetPosSlot2(curBack, posSlot);\n+        }\n+      }\n+    }\n+  }\n+}\n+\n+#define ChangePair(smallDist, bigDist) (((bigDist) >> 7) > (smallDist))\n+\n+static UInt32 GetOptimumFast(CLzmaEnc *p, UInt32 *backRes)\n+{\n+  UInt32 numAvail, mainLen, mainDist, numPairs, repIndex, repLen, i;\n+  const Byte *data;\n+  const UInt32 *matches;\n+\n+  if (p->additionalOffset == 0)\n+    mainLen = ReadMatchDistances(p, &numPairs);\n+  else\n+  {\n+    mainLen = p->longestMatchLength;\n+    numPairs = p->numPairs;\n+  }\n+\n+  numAvail = p->numAvail;\n+  *backRes = (UInt32)-1;\n+  if (numAvail < 2)\n+    return 1;\n+  if (numAvail > LZMA_MATCH_LEN_MAX)\n+    numAvail = LZMA_MATCH_LEN_MAX;\n+  data = p->matchFinder.GetPointerToCurrentPos(p->matchFinderObj) - 1;\n+\n+  repLen = repIndex = 0;\n+  for (i = 0; i < LZMA_NUM_REPS; i++)\n+  {\n+    UInt32 len;\n+    const Byte *data2 = data - (p->reps[i] + 1);\n+    if (data[0] != data2[0] || data[1] != data2[1])\n+      continue;\n+    for (len = 2; len < numAvail && data[len] == data2[len]; len++);\n+    if (len >= p->numFastBytes)\n+    {\n+      *backRes = i;\n+      MovePos(p, len - 1);\n+      return len;\n+    }\n+    if (len > repLen)\n+    {\n+      repIndex = i;\n+      repLen = len;\n+    }\n+  }\n+\n+  matches = p->matches;\n+  if (mainLen >= p->numFastBytes)\n+  {\n+    *backRes = matches[numPairs - 1] + LZMA_NUM_REPS;\n+    MovePos(p, mainLen - 1);\n+    return mainLen;\n+  }\n+\n+  mainDist = 0; /* for GCC */\n+  if (mainLen >= 2)\n+  {\n+    mainDist = matches[numPairs - 1];\n+    while (numPairs > 2 && mainLen == matches[numPairs - 4] + 1)\n+    {\n+      if (!ChangePair(matches[numPairs - 3], mainDist))\n+        break;\n+      numPairs -= 2;\n+      mainLen = matches[numPairs - 2];\n+      mainDist = matches[numPairs - 1];\n+    }\n+    if (mainLen == 2 && mainDist >= 0x80)\n+      mainLen = 1;\n+  }\n+\n+  if (repLen >= 2 && (\n+        (repLen + 1 >= mainLen) ||\n+        (repLen + 2 >= mainLen && mainDist >= (1 << 9)) ||\n+        (repLen + 3 >= mainLen && mainDist >= (1 << 15))))\n+  {\n+    *backRes = repIndex;\n+    MovePos(p, repLen - 1);\n+    return repLen;\n+  }\n+\n+  if (mainLen < 2 || numAvail <= 2)\n+    return 1;\n+\n+  p->longestMatchLength = ReadMatchDistances(p, &p->numPairs);\n+  if (p->longestMatchLength >= 2)\n+  {\n+    UInt32 newDistance = matches[p->numPairs - 1];\n+    if ((p->longestMatchLength >= mainLen && newDistance < mainDist) ||\n+        (p->longestMatchLength == mainLen + 1 && !ChangePair(mainDist, newDistance)) ||\n+        (p->longestMatchLength > mainLen + 1) ||\n+        (p->longestMatchLength + 1 >= mainLen && mainLen >= 3 && ChangePair(newDistance, mainDist)))\n+      return 1;\n+  }\n+\n+  data = p->matchFinder.GetPointerToCurrentPos(p->matchFinderObj) - 1;\n+  for (i = 0; i < LZMA_NUM_REPS; i++)\n+  {\n+    UInt32 len, limit;\n+    const Byte *data2 = data - (p->reps[i] + 1);\n+    if (data[0] != data2[0] || data[1] != data2[1])\n+      continue;\n+    limit = mainLen - 1;\n+    for (len = 2; len < limit && data[len] == data2[len]; len++);\n+    if (len >= limit)\n+      return 1;\n+  }\n+  *backRes = mainDist + LZMA_NUM_REPS;\n+  MovePos(p, mainLen - 2);\n+  return mainLen;\n+}\n+\n+static void WriteEndMarker(CLzmaEnc *p, UInt32 posState)\n+{\n+  UInt32 len;\n+  RangeEnc_EncodeBit(&p->rc, &p->isMatch[p->state][posState], 1);\n+  RangeEnc_EncodeBit(&p->rc, &p->isRep[p->state], 0);\n+  p->state = kMatchNextStates[p->state];\n+  len = LZMA_MATCH_LEN_MIN;\n+  LenEnc_Encode2(&p->lenEnc, &p->rc, len - LZMA_MATCH_LEN_MIN, posState, !p->fastMode, p->ProbPrices);\n+  RcTree_Encode(&p->rc, p->posSlotEncoder[GetLenToPosState(len)], kNumPosSlotBits, (1 << kNumPosSlotBits) - 1);\n+  RangeEnc_EncodeDirectBits(&p->rc, (((UInt32)1 << 30) - 1) >> kNumAlignBits, 30 - kNumAlignBits);\n+  RcTree_ReverseEncode(&p->rc, p->posAlignEncoder, kNumAlignBits, kAlignMask);\n+}\n+\n+static SRes CheckErrors(CLzmaEnc *p)\n+{\n+  if (p->result != SZ_OK)\n+    return p->result;\n+  if (p->rc.res != SZ_OK)\n+    p->result = SZ_ERROR_WRITE;\n+  if (p->matchFinderBase.result != SZ_OK)\n+    p->result = SZ_ERROR_READ;\n+  if (p->result != SZ_OK)\n+    p->finished = True;\n+  return p->result;\n+}\n+\n+static SRes Flush(CLzmaEnc *p, UInt32 nowPos)\n+{\n+  /* ReleaseMFStream(); */\n+  p->finished = True;\n+  if (p->writeEndMark)\n+    WriteEndMarker(p, nowPos & p->pbMask);\n+  RangeEnc_FlushData(&p->rc);\n+  RangeEnc_FlushStream(&p->rc);\n+  return CheckErrors(p);\n+}\n+\n+static void FillAlignPrices(CLzmaEnc *p)\n+{\n+  UInt32 i;\n+  for (i = 0; i < kAlignTableSize; i++)\n+    p->alignPrices[i] = RcTree_ReverseGetPrice(p->posAlignEncoder, kNumAlignBits, i, p->ProbPrices);\n+  p->alignPriceCount = 0;\n+}\n+\n+static void FillDistancesPrices(CLzmaEnc *p)\n+{\n+  UInt32 tempPrices[kNumFullDistances];\n+  UInt32 i, lenToPosState;\n+  for (i = kStartPosModelIndex; i < kNumFullDistances; i++)\n+  {\n+    UInt32 posSlot = GetPosSlot1(i);\n+    UInt32 footerBits = ((posSlot >> 1) - 1);\n+    UInt32 base = ((2 | (posSlot & 1)) << footerBits);\n+    tempPrices[i] = RcTree_ReverseGetPrice(p->posEncoders + base - posSlot - 1, footerBits, i - base, p->ProbPrices);\n+  }\n+\n+  for (lenToPosState = 0; lenToPosState < kNumLenToPosStates; lenToPosState++)\n+  {\n+    UInt32 posSlot;\n+    const CLzmaProb *encoder = p->posSlotEncoder[lenToPosState];\n+    UInt32 *posSlotPrices = p->posSlotPrices[lenToPosState];\n+    for (posSlot = 0; posSlot < p->distTableSize; posSlot++)\n+      posSlotPrices[posSlot] = RcTree_GetPrice(encoder, kNumPosSlotBits, posSlot, p->ProbPrices);\n+    for (posSlot = kEndPosModelIndex; posSlot < p->distTableSize; posSlot++)\n+      posSlotPrices[posSlot] += ((((posSlot >> 1) - 1) - kNumAlignBits) << kNumBitPriceShiftBits);\n+\n+    {\n+      UInt32 *distancesPrices = p->distancesPrices[lenToPosState];\n+      UInt32 i;\n+      for (i = 0; i < kStartPosModelIndex; i++)\n+        distancesPrices[i] = posSlotPrices[i];\n+      for (; i < kNumFullDistances; i++)\n+        distancesPrices[i] = posSlotPrices[GetPosSlot1(i)] + tempPrices[i];\n+    }\n+  }\n+  p->matchPriceCount = 0;\n+}\n+\n+void LzmaEnc_Construct(CLzmaEnc *p)\n+{\n+  RangeEnc_Construct(&p->rc);\n+  MatchFinder_Construct(&p->matchFinderBase);\n+  #ifndef _7ZIP_ST\n+  MatchFinderMt_Construct(&p->matchFinderMt);\n+  p->matchFinderMt.MatchFinder = &p->matchFinderBase;\n+  #endif\n+\n+  {\n+    CLzmaEncProps props;\n+    LzmaEncProps_Init(&props);\n+    LzmaEnc_SetProps(p, &props);\n+  }\n+\n+  #ifndef LZMA_LOG_BSR\n+  LzmaEnc_FastPosInit(p->g_FastPos);\n+  #endif\n+\n+  LzmaEnc_InitPriceTables(p->ProbPrices);\n+  p->litProbs = 0;\n+  p->saveState.litProbs = 0;\n+}\n+\n+CLzmaEncHandle LzmaEnc_Create(ISzAlloc *alloc)\n+{\n+  void *p;\n+  p = alloc->Alloc(alloc, sizeof(CLzmaEnc));\n+  if (p != 0)\n+    LzmaEnc_Construct((CLzmaEnc *)p);\n+  return p;\n+}\n+\n+void LzmaEnc_FreeLits(CLzmaEnc *p, ISzAlloc *alloc)\n+{\n+  alloc->Free(alloc, p->litProbs);\n+  alloc->Free(alloc, p->saveState.litProbs);\n+  p->litProbs = 0;\n+  p->saveState.litProbs = 0;\n+}\n+\n+void LzmaEnc_Destruct(CLzmaEnc *p, ISzAlloc *alloc, ISzAlloc *allocBig)\n+{\n+  #ifndef _7ZIP_ST\n+  MatchFinderMt_Destruct(&p->matchFinderMt, allocBig);\n+  #endif\n+  MatchFinder_Free(&p->matchFinderBase, allocBig);\n+  LzmaEnc_FreeLits(p, alloc);\n+  RangeEnc_Free(&p->rc, alloc);\n+}\n+\n+void LzmaEnc_Destroy(CLzmaEncHandle p, ISzAlloc *alloc, ISzAlloc *allocBig)\n+{\n+  LzmaEnc_Destruct((CLzmaEnc *)p, alloc, allocBig);\n+  alloc->Free(alloc, p);\n+}\n+\n+static SRes LzmaEnc_CodeOneBlock(CLzmaEnc *p, Bool useLimits, UInt32 maxPackSize, UInt32 maxUnpackSize)\n+{\n+  UInt32 nowPos32, startPos32;\n+  if (p->needInit)\n+  {\n+    p->matchFinder.Init(p->matchFinderObj);\n+    p->needInit = 0;\n+  }\n+\n+  if (p->finished)\n+    return p->result;\n+  RINOK(CheckErrors(p));\n+\n+  nowPos32 = (UInt32)p->nowPos64;\n+  startPos32 = nowPos32;\n+\n+  if (p->nowPos64 == 0)\n+  {\n+    UInt32 numPairs;\n+    Byte curByte;\n+    if (p->matchFinder.GetNumAvailableBytes(p->matchFinderObj) == 0)\n+      return Flush(p, nowPos32);\n+    ReadMatchDistances(p, &numPairs);\n+    RangeEnc_EncodeBit(&p->rc, &p->isMatch[p->state][0], 0);\n+    p->state = kLiteralNextStates[p->state];\n+    curByte = p->matchFinder.GetIndexByte(p->matchFinderObj, 0 - p->additionalOffset);\n+    LitEnc_Encode(&p->rc, p->litProbs, curByte);\n+    p->additionalOffset--;\n+    nowPos32++;\n+  }\n+\n+  if (p->matchFinder.GetNumAvailableBytes(p->matchFinderObj) != 0)\n+  for (;;)\n+  {\n+    UInt32 pos, len, posState;\n+\n+    if (p->fastMode)\n+      len = GetOptimumFast(p, &pos);\n+    else\n+      len = GetOptimum(p, nowPos32, &pos);\n+\n+    #ifdef SHOW_STAT2\n+    printf(\"\\n pos = %4X,   len = %d   pos = %d\", nowPos32, len, pos);\n+    #endif\n+\n+    posState = nowPos32 & p->pbMask;\n+    if (len == 1 && pos == (UInt32)-1)\n+    {\n+      Byte curByte;\n+      CLzmaProb *probs;\n+      const Byte *data;\n+\n+      RangeEnc_EncodeBit(&p->rc, &p->isMatch[p->state][posState], 0);\n+      data = p->matchFinder.GetPointerToCurrentPos(p->matchFinderObj) - p->additionalOffset;\n+      curByte = *data;\n+      probs = LIT_PROBS(nowPos32, *(data - 1));\n+      if (IsCharState(p->state))\n+        LitEnc_Encode(&p->rc, probs, curByte);\n+      else\n+        LitEnc_EncodeMatched(&p->rc, probs, curByte, *(data - p->reps[0] - 1));\n+      p->state = kLiteralNextStates[p->state];\n+    }\n+    else\n+    {\n+      RangeEnc_EncodeBit(&p->rc, &p->isMatch[p->state][posState], 1);\n+      if (pos < LZMA_NUM_REPS)\n+      {\n+        RangeEnc_EncodeBit(&p->rc, &p->isRep[p->state], 1);\n+        if (pos == 0)\n+        {\n+          RangeEnc_EncodeBit(&p->rc, &p->isRepG0[p->state], 0);\n+          RangeEnc_EncodeBit(&p->rc, &p->isRep0Long[p->state][posState], ((len == 1) ? 0 : 1));\n+        }\n+        else\n+        {\n+          UInt32 distance = p->reps[pos];\n+          RangeEnc_EncodeBit(&p->rc, &p->isRepG0[p->state], 1);\n+          if (pos == 1)\n+            RangeEnc_EncodeBit(&p->rc, &p->isRepG1[p->state], 0);\n+          else\n+          {\n+            RangeEnc_EncodeBit(&p->rc, &p->isRepG1[p->state], 1);\n+            RangeEnc_EncodeBit(&p->rc, &p->isRepG2[p->state], pos - 2);\n+            if (pos == 3)\n+              p->reps[3] = p->reps[2];\n+            p->reps[2] = p->reps[1];\n+          }\n+          p->reps[1] = p->reps[0];\n+          p->reps[0] = distance;\n+        }\n+        if (len == 1)\n+          p->state = kShortRepNextStates[p->state];\n+        else\n+        {\n+          LenEnc_Encode2(&p->repLenEnc, &p->rc, len - LZMA_MATCH_LEN_MIN, posState, !p->fastMode, p->ProbPrices);\n+          p->state = kRepNextStates[p->state];\n+        }\n+      }\n+      else\n+      {\n+        UInt32 posSlot;\n+        RangeEnc_EncodeBit(&p->rc, &p->isRep[p->state], 0);\n+        p->state = kMatchNextStates[p->state];\n+        LenEnc_Encode2(&p->lenEnc, &p->rc, len - LZMA_MATCH_LEN_MIN, posState, !p->fastMode, p->ProbPrices);\n+        pos -= LZMA_NUM_REPS;\n+        GetPosSlot(pos, posSlot);\n+        RcTree_Encode(&p->rc, p->posSlotEncoder[GetLenToPosState(len)], kNumPosSlotBits, posSlot);\n+\n+        if (posSlot >= kStartPosModelIndex)\n+        {\n+          UInt32 footerBits = ((posSlot >> 1) - 1);\n+          UInt32 base = ((2 | (posSlot & 1)) << footerBits);\n+          UInt32 posReduced = pos - base;\n+\n+          if (posSlot < kEndPosModelIndex)\n+            RcTree_ReverseEncode(&p->rc, p->posEncoders + base - posSlot - 1, footerBits, posReduced);\n+          else\n+          {\n+            RangeEnc_EncodeDirectBits(&p->rc, posReduced >> kNumAlignBits, footerBits - kNumAlignBits);\n+            RcTree_ReverseEncode(&p->rc, p->posAlignEncoder, kNumAlignBits, posReduced & kAlignMask);\n+            p->alignPriceCount++;\n+          }\n+        }\n+        p->reps[3] = p->reps[2];\n+        p->reps[2] = p->reps[1];\n+        p->reps[1] = p->reps[0];\n+        p->reps[0] = pos;\n+        p->matchPriceCount++;\n+      }\n+    }\n+    p->additionalOffset -= len;\n+    nowPos32 += len;\n+    if (p->additionalOffset == 0)\n+    {\n+      UInt32 processed;\n+      if (!p->fastMode)\n+      {\n+        if (p->matchPriceCount >= (1 << 7))\n+          FillDistancesPrices(p);\n+        if (p->alignPriceCount >= kAlignTableSize)\n+          FillAlignPrices(p);\n+      }\n+      if (p->matchFinder.GetNumAvailableBytes(p->matchFinderObj) == 0)\n+        break;\n+      processed = nowPos32 - startPos32;\n+      if (useLimits)\n+      {\n+        if (processed + kNumOpts + 300 >= maxUnpackSize ||\n+            RangeEnc_GetProcessed(&p->rc) + kNumOpts * 2 >= maxPackSize)\n+          break;\n+      }\n+      else if (processed >= (1 << 15))\n+      {\n+        p->nowPos64 += nowPos32 - startPos32;\n+        return CheckErrors(p);\n+      }\n+    }\n+  }\n+  p->nowPos64 += nowPos32 - startPos32;\n+  return Flush(p, nowPos32);\n+}\n+\n+#define kBigHashDicLimit ((UInt32)1 << 24)\n+\n+static SRes LzmaEnc_Alloc(CLzmaEnc *p, UInt32 keepWindowSize, ISzAlloc *alloc, ISzAlloc *allocBig)\n+{\n+  UInt32 beforeSize = kNumOpts;\n+  Bool btMode;\n+  if (!RangeEnc_Alloc(&p->rc, alloc))\n+    return SZ_ERROR_MEM;\n+  btMode = (p->matchFinderBase.btMode != 0);\n+  #ifndef _7ZIP_ST\n+  p->mtMode = (p->multiThread && !p->fastMode && btMode);\n+  #endif\n+\n+  {\n+    unsigned lclp = p->lc + p->lp;\n+    if (p->litProbs == 0 || p->saveState.litProbs == 0 || p->lclp != lclp)\n+    {\n+      LzmaEnc_FreeLits(p, alloc);\n+      p->litProbs = (CLzmaProb *)alloc->Alloc(alloc, (0x300 << lclp) * sizeof(CLzmaProb));\n+      p->saveState.litProbs = (CLzmaProb *)alloc->Alloc(alloc, (0x300 << lclp) * sizeof(CLzmaProb));\n+      if (p->litProbs == 0 || p->saveState.litProbs == 0)\n+      {\n+        LzmaEnc_FreeLits(p, alloc);\n+        return SZ_ERROR_MEM;\n+      }\n+      p->lclp = lclp;\n+    }\n+  }\n+\n+  p->matchFinderBase.bigHash = (p->dictSize > kBigHashDicLimit);\n+\n+  if (beforeSize + p->dictSize < keepWindowSize)\n+    beforeSize = keepWindowSize - p->dictSize;\n+\n+  #ifndef _7ZIP_ST\n+  if (p->mtMode)\n+  {\n+    RINOK(MatchFinderMt_Create(&p->matchFinderMt, p->dictSize, beforeSize, p->numFastBytes, LZMA_MATCH_LEN_MAX, allocBig));\n+    p->matchFinderObj = &p->matchFinderMt;\n+    MatchFinderMt_CreateVTable(&p->matchFinderMt, &p->matchFinder);\n+  }\n+  else\n+  #endif\n+  {\n+    if (!MatchFinder_Create(&p->matchFinderBase, p->dictSize, beforeSize, p->numFastBytes, LZMA_MATCH_LEN_MAX, allocBig))\n+      return SZ_ERROR_MEM;\n+    p->matchFinderObj = &p->matchFinderBase;\n+    MatchFinder_CreateVTable(&p->matchFinderBase, &p->matchFinder);\n+  }\n+  return SZ_OK;\n+}\n+\n+void LzmaEnc_Init(CLzmaEnc *p)\n+{\n+  UInt32 i;\n+  p->state = 0;\n+  for (i = 0 ; i < LZMA_NUM_REPS; i++)\n+    p->reps[i] = 0;\n+\n+  RangeEnc_Init(&p->rc);\n+\n+\n+  for (i = 0; i < kNumStates; i++)\n+  {\n+    UInt32 j;\n+    for (j = 0; j < LZMA_NUM_PB_STATES_MAX; j++)\n+    {\n+      p->isMatch[i][j] = kProbInitValue;\n+      p->isRep0Long[i][j] = kProbInitValue;\n+    }\n+    p->isRep[i] = kProbInitValue;\n+    p->isRepG0[i] = kProbInitValue;\n+    p->isRepG1[i] = kProbInitValue;\n+    p->isRepG2[i] = kProbInitValue;\n+  }\n+\n+  {\n+    UInt32 num = 0x300 << (p->lp + p->lc);\n+    for (i = 0; i < num; i++)\n+      p->litProbs[i] = kProbInitValue;\n+  }\n+\n+  {\n+    for (i = 0; i < kNumLenToPosStates; i++)\n+    {\n+      CLzmaProb *probs = p->posSlotEncoder[i];\n+      UInt32 j;\n+      for (j = 0; j < (1 << kNumPosSlotBits); j++)\n+        probs[j] = kProbInitValue;\n+    }\n+  }\n+  {\n+    for (i = 0; i < kNumFullDistances - kEndPosModelIndex; i++)\n+      p->posEncoders[i] = kProbInitValue;\n+  }\n+\n+  LenEnc_Init(&p->lenEnc.p);\n+  LenEnc_Init(&p->repLenEnc.p);\n+\n+  for (i = 0; i < (1 << kNumAlignBits); i++)\n+    p->posAlignEncoder[i] = kProbInitValue;\n+\n+  p->optimumEndIndex = 0;\n+  p->optimumCurrentIndex = 0;\n+  p->additionalOffset = 0;\n+\n+  p->pbMask = (1 << p->pb) - 1;\n+  p->lpMask = (1 << p->lp) - 1;\n+}\n+\n+void LzmaEnc_InitPrices(CLzmaEnc *p)\n+{\n+  if (!p->fastMode)\n+  {\n+    FillDistancesPrices(p);\n+    FillAlignPrices(p);\n+  }\n+\n+  p->lenEnc.tableSize =\n+  p->repLenEnc.tableSize =\n+      p->numFastBytes + 1 - LZMA_MATCH_LEN_MIN;\n+  LenPriceEnc_UpdateTables(&p->lenEnc, 1 << p->pb, p->ProbPrices);\n+  LenPriceEnc_UpdateTables(&p->repLenEnc, 1 << p->pb, p->ProbPrices);\n+}\n+\n+static SRes LzmaEnc_AllocAndInit(CLzmaEnc *p, UInt32 keepWindowSize, ISzAlloc *alloc, ISzAlloc *allocBig)\n+{\n+  UInt32 i;\n+  for (i = 0; i < (UInt32)kDicLogSizeMaxCompress; i++)\n+    if (p->dictSize <= ((UInt32)1 << i))\n+      break;\n+  p->distTableSize = i * 2;\n+\n+  p->finished = False;\n+  p->result = SZ_OK;\n+  RINOK(LzmaEnc_Alloc(p, keepWindowSize, alloc, allocBig));\n+  LzmaEnc_Init(p);\n+  LzmaEnc_InitPrices(p);\n+  p->nowPos64 = 0;\n+  return SZ_OK;\n+}\n+\n+static SRes LzmaEnc_Prepare(CLzmaEncHandle pp, ISeqOutStream *outStream, ISeqInStream *inStream,\n+    ISzAlloc *alloc, ISzAlloc *allocBig)\n+{\n+  CLzmaEnc *p = (CLzmaEnc *)pp;\n+  p->matchFinderBase.stream = inStream;\n+  p->needInit = 1;\n+  p->rc.outStream = outStream;\n+  return LzmaEnc_AllocAndInit(p, 0, alloc, allocBig);\n+}\n+\n+SRes LzmaEnc_PrepareForLzma2(CLzmaEncHandle pp,\n+    ISeqInStream *inStream, UInt32 keepWindowSize,\n+    ISzAlloc *alloc, ISzAlloc *allocBig)\n+{\n+  CLzmaEnc *p = (CLzmaEnc *)pp;\n+  p->matchFinderBase.stream = inStream;\n+  p->needInit = 1;\n+  return LzmaEnc_AllocAndInit(p, keepWindowSize, alloc, allocBig);\n+}\n+\n+static void LzmaEnc_SetInputBuf(CLzmaEnc *p, const Byte *src, SizeT srcLen)\n+{\n+  p->matchFinderBase.directInput = 1;\n+  p->matchFinderBase.bufferBase = (Byte *)src;\n+  p->matchFinderBase.directInputRem = srcLen;\n+}\n+\n+SRes LzmaEnc_MemPrepare(CLzmaEncHandle pp, const Byte *src, SizeT srcLen,\n+    UInt32 keepWindowSize, ISzAlloc *alloc, ISzAlloc *allocBig)\n+{\n+  CLzmaEnc *p = (CLzmaEnc *)pp;\n+  LzmaEnc_SetInputBuf(p, src, srcLen);\n+  p->needInit = 1;\n+\n+  return LzmaEnc_AllocAndInit(p, keepWindowSize, alloc, allocBig);\n+}\n+\n+void LzmaEnc_Finish(CLzmaEncHandle pp)\n+{\n+  #ifndef _7ZIP_ST\n+  CLzmaEnc *p = (CLzmaEnc *)pp;\n+  if (p->mtMode)\n+    MatchFinderMt_ReleaseStream(&p->matchFinderMt);\n+  #else\n+  pp = pp;\n+  #endif\n+}\n+\n+typedef struct\n+{\n+  ISeqOutStream funcTable;\n+  Byte *data;\n+  SizeT rem;\n+  Bool overflow;\n+} CSeqOutStreamBuf;\n+\n+static size_t MyWrite(void *pp, const void *data, size_t size)\n+{\n+  CSeqOutStreamBuf *p = (CSeqOutStreamBuf *)pp;\n+  if (p->rem < size)\n+  {\n+    size = p->rem;\n+    p->overflow = True;\n+  }\n+  memcpy(p->data, data, size);\n+  p->rem -= size;\n+  p->data += size;\n+  return size;\n+}\n+\n+\n+UInt32 LzmaEnc_GetNumAvailableBytes(CLzmaEncHandle pp)\n+{\n+  const CLzmaEnc *p = (CLzmaEnc *)pp;\n+  return p->matchFinder.GetNumAvailableBytes(p->matchFinderObj);\n+}\n+\n+const Byte *LzmaEnc_GetCurBuf(CLzmaEncHandle pp)\n+{\n+  const CLzmaEnc *p = (CLzmaEnc *)pp;\n+  return p->matchFinder.GetPointerToCurrentPos(p->matchFinderObj) - p->additionalOffset;\n+}\n+\n+SRes LzmaEnc_CodeOneMemBlock(CLzmaEncHandle pp, Bool reInit,\n+    Byte *dest, size_t *destLen, UInt32 desiredPackSize, UInt32 *unpackSize)\n+{\n+  CLzmaEnc *p = (CLzmaEnc *)pp;\n+  UInt64 nowPos64;\n+  SRes res;\n+  CSeqOutStreamBuf outStream;\n+\n+  outStream.funcTable.Write = MyWrite;\n+  outStream.data = dest;\n+  outStream.rem = *destLen;\n+  outStream.overflow = False;\n+\n+  p->writeEndMark = False;\n+  p->finished = False;\n+  p->result = SZ_OK;\n+\n+  if (reInit)\n+    LzmaEnc_Init(p);\n+  LzmaEnc_InitPrices(p);\n+  nowPos64 = p->nowPos64;\n+  RangeEnc_Init(&p->rc);\n+  p->rc.outStream = &outStream.funcTable;\n+\n+  res = LzmaEnc_CodeOneBlock(p, True, desiredPackSize, *unpackSize);\n+\n+  *unpackSize = (UInt32)(p->nowPos64 - nowPos64);\n+  *destLen -= outStream.rem;\n+  if (outStream.overflow)\n+    return SZ_ERROR_OUTPUT_EOF;\n+\n+  return res;\n+}\n+\n+static SRes LzmaEnc_Encode2(CLzmaEnc *p, ICompressProgress *progress)\n+{\n+  SRes res = SZ_OK;\n+\n+  #ifndef _7ZIP_ST\n+  Byte allocaDummy[0x300];\n+  int i = 0;\n+  for (i = 0; i < 16; i++)\n+    allocaDummy[i] = (Byte)i;\n+  #endif\n+\n+  for (;;)\n+  {\n+    res = LzmaEnc_CodeOneBlock(p, False, 0, 0);\n+    if (res != SZ_OK || p->finished != 0)\n+      break;\n+    if (progress != 0)\n+    {\n+      res = progress->Progress(progress, p->nowPos64, RangeEnc_GetProcessed(&p->rc));\n+      if (res != SZ_OK)\n+      {\n+        res = SZ_ERROR_PROGRESS;\n+        break;\n+      }\n+    }\n+  }\n+  LzmaEnc_Finish(p);\n+  return res;\n+}\n+\n+SRes LzmaEnc_Encode(CLzmaEncHandle pp, ISeqOutStream *outStream, ISeqInStream *inStream, ICompressProgress *progress,\n+    ISzAlloc *alloc, ISzAlloc *allocBig)\n+{\n+  RINOK(LzmaEnc_Prepare(pp, outStream, inStream, alloc, allocBig));\n+  return LzmaEnc_Encode2((CLzmaEnc *)pp, progress);\n+}\n+\n+SRes LzmaEnc_WriteProperties(CLzmaEncHandle pp, Byte *props, SizeT *size)\n+{\n+  CLzmaEnc *p = (CLzmaEnc *)pp;\n+  int i;\n+  UInt32 dictSize = p->dictSize;\n+  if (*size < LZMA_PROPS_SIZE)\n+    return SZ_ERROR_PARAM;\n+  *size = LZMA_PROPS_SIZE;\n+  props[0] = (Byte)((p->pb * 5 + p->lp) * 9 + p->lc);\n+\n+  for (i = 11; i <= 30; i++)\n+  {\n+    if (dictSize <= ((UInt32)2 << i))\n+    {\n+      dictSize = (2 << i);\n+      break;\n+    }\n+    if (dictSize <= ((UInt32)3 << i))\n+    {\n+      dictSize = (3 << i);\n+      break;\n+    }\n+  }\n+\n+  for (i = 0; i < 4; i++)\n+    props[1 + i] = (Byte)(dictSize >> (8 * i));\n+  return SZ_OK;\n+}\n+\n+SRes LzmaEnc_MemEncode(CLzmaEncHandle pp, Byte *dest, SizeT *destLen, const Byte *src, SizeT srcLen,\n+    int writeEndMark, ICompressProgress *progress, ISzAlloc *alloc, ISzAlloc *allocBig)\n+{\n+  SRes res;\n+  CLzmaEnc *p = (CLzmaEnc *)pp;\n+\n+  CSeqOutStreamBuf outStream;\n+\n+  LzmaEnc_SetInputBuf(p, src, srcLen);\n+\n+  outStream.funcTable.Write = MyWrite;\n+  outStream.data = dest;\n+  outStream.rem = *destLen;\n+  outStream.overflow = False;\n+\n+  p->writeEndMark = writeEndMark;\n+\n+  p->rc.outStream = &outStream.funcTable;\n+  res = LzmaEnc_MemPrepare(pp, src, srcLen, 0, alloc, allocBig);\n+  if (res == SZ_OK)\n+    res = LzmaEnc_Encode2(p, progress);\n+\n+  *destLen -= outStream.rem;\n+  if (outStream.overflow)\n+    return SZ_ERROR_OUTPUT_EOF;\n+  return res;\n+}\n+\n+SRes LzmaEncode(Byte *dest, SizeT *destLen, const Byte *src, SizeT srcLen,\n+    const CLzmaEncProps *props, Byte *propsEncoded, SizeT *propsSize, int writeEndMark,\n+    ICompressProgress *progress, ISzAlloc *alloc, ISzAlloc *allocBig)\n+{\n+  CLzmaEnc *p = (CLzmaEnc *)LzmaEnc_Create(alloc);\n+  SRes res;\n+  if (p == 0)\n+    return SZ_ERROR_MEM;\n+\n+  res = LzmaEnc_SetProps(p, props);\n+  if (res == SZ_OK)\n+  {\n+    res = LzmaEnc_WriteProperties(p, propsEncoded, propsSize);\n+    if (res == SZ_OK)\n+      res = LzmaEnc_MemEncode(p, dest, destLen, src, srcLen,\n+          writeEndMark, progress, alloc, allocBig);\n+  }\n+\n+  LzmaEnc_Destroy(p, alloc, allocBig);\n+  return res;\n+}\n--- /dev/null\n+++ b/lib/lzma/Makefile\n@@ -0,0 +1,7 @@\n+lzma_compress-objs := LzFind.o LzmaEnc.o\n+lzma_decompress-objs := LzmaDec.o\n+\n+obj-$(CONFIG_LZMA_COMPRESS) += lzma_compress.o\n+obj-$(CONFIG_LZMA_DECOMPRESS) += lzma_decompress.o\n+\n+EXTRA_CFLAGS += -Iinclude/linux -Iinclude/linux/lzma -include types.h\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/532-jffs2_eofdetect.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nSubject: fs: jffs2: EOF marker\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n fs/jffs2/build.c | 10 ++++++++++\n fs/jffs2/scan.c  | 21 +++++++++++++++++++--\n 2 files changed, 29 insertions(+), 2 deletions(-)\n\n--- a/fs/jffs2/build.c\n+++ b/fs/jffs2/build.c\n@@ -117,6 +117,16 @@ static int jffs2_build_filesystem(struct\n \tdbg_fsbuild(\"scanned flash completely\\n\");\n \tjffs2_dbg_dump_block_lists_nolock(c);\n \n+\tif (c->flags & (1 << 7)) {\n+\t\tprintk(\"%s(): unlocking the mtd device... \", __func__);\n+\t\tmtd_unlock(c->mtd, 0, c->mtd->size);\n+\t\tprintk(\"done.\\n\");\n+\n+\t\tprintk(\"%s(): erasing all blocks after the end marker... \", __func__);\n+\t\tjffs2_erase_pending_blocks(c, -1);\n+\t\tprintk(\"done.\\n\");\n+\t}\n+\n \tdbg_fsbuild(\"pass 1 starting\\n\");\n \tc->flags |= JFFS2_SB_FLAG_BUILDING;\n \t/* Now scan the directory tree, increasing nlink according to every dirent found. */\n--- a/fs/jffs2/scan.c\n+++ b/fs/jffs2/scan.c\n@@ -148,8 +148,14 @@ int jffs2_scan_medium(struct jffs2_sb_in\n \t\t/* reset summary info for next eraseblock scan */\n \t\tjffs2_sum_reset_collected(s);\n \n-\t\tret = jffs2_scan_eraseblock(c, jeb, buf_size?flashbuf:(flashbuf+jeb->offset),\n-\t\t\t\t\t\tbuf_size, s);\n+\t\tif (c->flags & (1 << 7)) {\n+\t\t\tif (mtd_block_isbad(c->mtd, jeb->offset))\n+\t\t\t\tret = BLK_STATE_BADBLOCK;\n+\t\t\telse\n+\t\t\t\tret = BLK_STATE_ALLFF;\n+\t\t} else\n+\t\t\tret = jffs2_scan_eraseblock(c, jeb, buf_size?flashbuf:(flashbuf+jeb->offset),\n+\t\t\t\t\t\t\tbuf_size, s);\n \n \t\tif (ret < 0)\n \t\t\tgoto out;\n@@ -567,6 +573,17 @@ full_scan:\n \t\t\treturn err;\n \t}\n \n+\tif ((buf[0] == 0xde) &&\n+\t\t(buf[1] == 0xad) &&\n+\t\t(buf[2] == 0xc0) &&\n+\t\t(buf[3] == 0xde)) {\n+\t\t/* end of filesystem. erase everything after this point */\n+\t\tprintk(\"%s(): End of filesystem marker found at 0x%x\\n\", __func__, jeb->offset);\n+\t\tc->flags |= (1 << 7);\n+\n+\t\treturn BLK_STATE_ALLFF;\n+\t}\n+\n \t/* We temporarily use 'ofs' as a pointer into the buffer/jeb */\n \tofs = 0;\n \tmax_ofs = EMPTY_SCAN_SIZE(c->sector_size);\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/600-netfilter_conntrack_flush.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nSubject: netfilter: add support for flushing conntrack via /proc\n\nlede-commit 8193bbe59a74d34d6a26d4a8cb857b1952905314\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n net/netfilter/nf_conntrack_standalone.c | 59 ++++++++++++++++++++++++++++++++-\n 1 file changed, 58 insertions(+), 1 deletion(-)\n\n--- a/net/netfilter/nf_conntrack_standalone.c\n+++ b/net/netfilter/nf_conntrack_standalone.c\n@@ -9,6 +9,7 @@\n #include <linux/percpu.h>\n #include <linux/netdevice.h>\n #include <linux/security.h>\n+#include <linux/inet.h>\n #include <net/net_namespace.h>\n #ifdef CONFIG_SYSCTL\n #include <linux/sysctl.h>\n@@ -457,6 +458,56 @@ static int ct_cpu_seq_show(struct seq_fi\n \treturn 0;\n }\n \n+struct kill_request {\n+\tu16 family;\n+\tunion nf_inet_addr addr;\n+};\n+\n+static int kill_matching(struct nf_conn *i, void *data)\n+{\n+\tstruct kill_request *kr = data;\n+\tstruct nf_conntrack_tuple *t1 = &i->tuplehash[IP_CT_DIR_ORIGINAL].tuple;\n+\tstruct nf_conntrack_tuple *t2 = &i->tuplehash[IP_CT_DIR_REPLY].tuple;\n+\n+\tif (!kr->family)\n+\t\treturn 1;\n+\n+\tif (t1->src.l3num != kr->family)\n+\t\treturn 0;\n+\n+\treturn (nf_inet_addr_cmp(&kr->addr, &t1->src.u3) ||\n+\t        nf_inet_addr_cmp(&kr->addr, &t1->dst.u3) ||\n+\t        nf_inet_addr_cmp(&kr->addr, &t2->src.u3) ||\n+\t        nf_inet_addr_cmp(&kr->addr, &t2->dst.u3));\n+}\n+\n+static int ct_file_write(struct file *file, char *buf, size_t count)\n+{\n+\tstruct seq_file *seq = file->private_data;\n+\tstruct net *net = seq_file_net(seq);\n+\tstruct kill_request kr = { };\n+\n+\tif (count == 0)\n+\t\treturn 0;\n+\n+\tif (count >= INET6_ADDRSTRLEN)\n+\t\tcount = INET6_ADDRSTRLEN - 1;\n+\n+\tif (strnchr(buf, count, ':')) {\n+\t\tkr.family = AF_INET6;\n+\t\tif (!in6_pton(buf, count, (void *)&kr.addr, '\\n', NULL))\n+\t\t\treturn -EINVAL;\n+\t} else if (strnchr(buf, count, '.')) {\n+\t\tkr.family = AF_INET;\n+\t\tif (!in4_pton(buf, count, (void *)&kr.addr, '\\n', NULL))\n+\t\t\treturn -EINVAL;\n+\t}\n+\n+\tnf_ct_iterate_cleanup_net(net, kill_matching, &kr, 0, 0);\n+\n+\treturn 0;\n+}\n+\n static const struct seq_operations ct_cpu_seq_ops = {\n \t.start\t= ct_cpu_seq_start,\n \t.next\t= ct_cpu_seq_next,\n@@ -470,8 +521,9 @@ static int nf_conntrack_standalone_init_\n \tkuid_t root_uid;\n \tkgid_t root_gid;\n \n-\tpde = proc_create_net(\"nf_conntrack\", 0440, net->proc_net, &ct_seq_ops,\n-\t\t\tsizeof(struct ct_iter_state));\n+\tpde = proc_create_net_data_write(\"nf_conntrack\", 0440, net->proc_net,\n+\t\t\t\t\t &ct_seq_ops, &ct_file_write,\n+\t\t\t\t\t sizeof(struct ct_iter_state), NULL);\n \tif (!pde)\n \t\tgoto out_nf_conntrack;\n \n"
  },
  {
    "path": "target/linux/generic/pending-5.10/610-netfilter_match_bypass_default_checks.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nSubject: kernel: add a new version of my netfilter speedup patches for linux 2.6.39 and 3.0\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n include/uapi/linux/netfilter_ipv4/ip_tables.h |  1 +\n net/ipv4/netfilter/ip_tables.c                | 37 +++++++++++++++++++++++++++\n 2 files changed, 38 insertions(+)\n\n--- a/include/uapi/linux/netfilter_ipv4/ip_tables.h\n+++ b/include/uapi/linux/netfilter_ipv4/ip_tables.h\n@@ -89,6 +89,7 @@ struct ipt_ip {\n #define IPT_F_FRAG\t\t0x01\t/* Set if rule is a fragment rule */\n #define IPT_F_GOTO\t\t0x02\t/* Set if jump is a goto */\n #define IPT_F_MASK\t\t0x03\t/* All possible flag bits mask. */\n+#define IPT_F_NO_DEF_MATCH\t0x80\t/* Internal: no default match rules present */\n \n /* Values for \"inv\" field in struct ipt_ip. */\n #define IPT_INV_VIA_IN\t\t0x01\t/* Invert the sense of IN IFACE. */\n--- a/net/ipv4/netfilter/ip_tables.c\n+++ b/net/ipv4/netfilter/ip_tables.c\n@@ -50,6 +50,9 @@ ip_packet_match(const struct iphdr *ip,\n {\n \tunsigned long ret;\n \n+\tif (ipinfo->flags & IPT_F_NO_DEF_MATCH)\n+\t\treturn true;\n+\n \tif (NF_INVF(ipinfo, IPT_INV_SRCIP,\n \t\t    (ip->saddr & ipinfo->smsk.s_addr) != ipinfo->src.s_addr) ||\n \t    NF_INVF(ipinfo, IPT_INV_DSTIP,\n@@ -80,6 +83,29 @@ ip_packet_match(const struct iphdr *ip,\n \treturn true;\n }\n \n+static void\n+ip_checkdefault(struct ipt_ip *ip)\n+{\n+\tstatic const char iface_mask[IFNAMSIZ] = {};\n+\n+\tif (ip->invflags || ip->flags & IPT_F_FRAG)\n+\t\treturn;\n+\n+\tif (memcmp(ip->iniface_mask, iface_mask, IFNAMSIZ) != 0)\n+\t\treturn;\n+\n+\tif (memcmp(ip->outiface_mask, iface_mask, IFNAMSIZ) != 0)\n+\t\treturn;\n+\n+\tif (ip->smsk.s_addr || ip->dmsk.s_addr)\n+\t\treturn;\n+\n+\tif (ip->proto)\n+\t\treturn;\n+\n+\tip->flags |= IPT_F_NO_DEF_MATCH;\n+}\n+\n static bool\n ip_checkentry(const struct ipt_ip *ip)\n {\n@@ -524,6 +550,8 @@ find_check_entry(struct ipt_entry *e, st\n \tstruct xt_mtchk_param mtpar;\n \tstruct xt_entry_match *ematch;\n \n+\tip_checkdefault(&e->ip);\n+\n \tif (!xt_percpu_counter_alloc(alloc_state, &e->counters))\n \t\treturn -ENOMEM;\n \n@@ -818,6 +846,7 @@ copy_entries_to_user(unsigned int total_\n \tconst struct xt_table_info *private = table->private;\n \tint ret = 0;\n \tconst void *loc_cpu_entry;\n+\tu8 flags;\n \n \tcounters = alloc_counters(table);\n \tif (IS_ERR(counters))\n@@ -845,6 +874,14 @@ copy_entries_to_user(unsigned int total_\n \t\t\tgoto free_counters;\n \t\t}\n \n+\t\tflags = e->ip.flags & IPT_F_MASK;\n+\t\tif (copy_to_user(userptr + off\n+\t\t\t\t + offsetof(struct ipt_entry, ip.flags),\n+\t\t\t\t &flags, sizeof(flags)) != 0) {\n+\t\t\tret = -EFAULT;\n+\t\t\tgoto free_counters;\n+\t\t}\n+\n \t\tfor (i = sizeof(struct ipt_entry);\n \t\t     i < e->target_offset;\n \t\t     i += m->u.match_size) {\n@@ -1223,12 +1260,15 @@ compat_copy_entry_to_user(struct ipt_ent\n \tcompat_uint_t origsize;\n \tconst struct xt_entry_match *ematch;\n \tint ret = 0;\n+\tu8 flags = e->ip.flags & IPT_F_MASK;\n \n \torigsize = *size;\n \tce = *dstptr;\n \tif (copy_to_user(ce, e, sizeof(struct ipt_entry)) != 0 ||\n \t    copy_to_user(&ce->counters, &counters[i],\n-\t    sizeof(counters[i])) != 0)\n+\t    sizeof(counters[i])) != 0 ||\n+\t    copy_to_user(&ce->ip.flags, &flags,\n+\t    sizeof(flags)) != 0)\n \t\treturn -EFAULT;\n \n \t*dstptr += sizeof(struct compat_ipt_entry);\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/611-netfilter_match_bypass_default_table.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nSubject: netfilter: match bypass default table\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n net/ipv4/netfilter/ip_tables.c | 79 +++++++++++++++++++++++++++++++-----------\n 1 file changed, 58 insertions(+), 21 deletions(-)\n\n--- a/net/ipv4/netfilter/ip_tables.c\n+++ b/net/ipv4/netfilter/ip_tables.c\n@@ -246,6 +246,33 @@ struct ipt_entry *ipt_next_entry(const s\n \treturn (void *)entry + entry->next_offset;\n }\n \n+static bool\n+ipt_handle_default_rule(struct ipt_entry *e, unsigned int *verdict)\n+{\n+\tstruct xt_entry_target *t;\n+\tstruct xt_standard_target *st;\n+\n+\tif (e->target_offset != sizeof(struct ipt_entry))\n+\t\treturn false;\n+\n+\tif (!(e->ip.flags & IPT_F_NO_DEF_MATCH))\n+\t\treturn false;\n+\n+\tt = ipt_get_target(e);\n+\tif (t->u.kernel.target->target)\n+\t\treturn false;\n+\n+\tst = (struct xt_standard_target *) t;\n+\tif (st->verdict == XT_RETURN)\n+\t\treturn false;\n+\n+\tif (st->verdict >= 0)\n+\t\treturn false;\n+\n+\t*verdict = (unsigned)(-st->verdict) - 1;\n+\treturn true;\n+}\n+\n /* Returns one of the generic firewall policies, like NF_ACCEPT. */\n unsigned int\n ipt_do_table(struct sk_buff *skb,\n@@ -266,27 +293,28 @@ ipt_do_table(struct sk_buff *skb,\n \tunsigned int addend;\n \n \t/* Initialization */\n+\tWARN_ON(!(table->valid_hooks & (1 << hook)));\n+\tlocal_bh_disable();\n+\tprivate = READ_ONCE(table->private); /* Address dependency. */\n+\tcpu        = smp_processor_id();\n+\ttable_base = private->entries;\n+\n+\te = get_entry(table_base, private->hook_entry[hook]);\n+\tif (ipt_handle_default_rule(e, &verdict)) {\n+\t\tstruct xt_counters *counter;\n+\n+\t\tcounter = xt_get_this_cpu_counter(&e->counters);\n+\t\tADD_COUNTER(*counter, skb->len, 1);\n+\t\tlocal_bh_enable();\n+\t\treturn verdict;\n+\t}\n+\n \tstackidx = 0;\n \tip = ip_hdr(skb);\n \tindev = state->in ? state->in->name : nulldevname;\n \toutdev = state->out ? state->out->name : nulldevname;\n-\t/* We handle fragments by dealing with the first fragment as\n-\t * if it was a normal packet.  All other fragments are treated\n-\t * normally, except that they will NEVER match rules that ask\n-\t * things we don't know, ie. tcp syn flag or ports).  If the\n-\t * rule is also a fragment-specific rule, non-fragments won't\n-\t * match it. */\n-\tacpar.fragoff = ntohs(ip->frag_off) & IP_OFFSET;\n-\tacpar.thoff   = ip_hdrlen(skb);\n-\tacpar.hotdrop = false;\n-\tacpar.state   = state;\n \n-\tWARN_ON(!(table->valid_hooks & (1 << hook)));\n-\tlocal_bh_disable();\n \taddend = xt_write_recseq_begin();\n-\tprivate = READ_ONCE(table->private); /* Address dependency. */\n-\tcpu        = smp_processor_id();\n-\ttable_base = private->entries;\n \tjumpstack  = (struct ipt_entry **)private->jumpstack[cpu];\n \n \t/* Switch to alternate jumpstack if we're being invoked via TEE.\n@@ -299,7 +327,16 @@ ipt_do_table(struct sk_buff *skb,\n \tif (static_key_false(&xt_tee_enabled))\n \t\tjumpstack += private->stacksize * __this_cpu_read(nf_skb_duplicated);\n \n-\te = get_entry(table_base, private->hook_entry[hook]);\n+\t/* We handle fragments by dealing with the first fragment as\n+\t * if it was a normal packet.  All other fragments are treated\n+\t * normally, except that they will NEVER match rules that ask\n+\t * things we don't know, ie. tcp syn flag or ports).  If the\n+\t * rule is also a fragment-specific rule, non-fragments won't\n+\t * match it. */\n+\tacpar.fragoff = ntohs(ip->frag_off) & IP_OFFSET;\n+\tacpar.thoff   = ip_hdrlen(skb);\n+\tacpar.hotdrop = false;\n+\tacpar.state   = state;\n \n \tdo {\n \t\tconst struct xt_entry_target *t;\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/612-netfilter_match_reduce_memory_access.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nSubject: netfilter: reduce match memory access\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n net/ipv4/netfilter/ip_tables.c | 4 ++--\n 1 file changed, 2 insertions(+), 2 deletions(-)\n\n--- a/net/ipv4/netfilter/ip_tables.c\n+++ b/net/ipv4/netfilter/ip_tables.c\n@@ -53,9 +53,9 @@ ip_packet_match(const struct iphdr *ip,\n \tif (ipinfo->flags & IPT_F_NO_DEF_MATCH)\n \t\treturn true;\n \n-\tif (NF_INVF(ipinfo, IPT_INV_SRCIP,\n+\tif (NF_INVF(ipinfo, IPT_INV_SRCIP, ipinfo->smsk.s_addr &&\n \t\t    (ip->saddr & ipinfo->smsk.s_addr) != ipinfo->src.s_addr) ||\n-\t    NF_INVF(ipinfo, IPT_INV_DSTIP,\n+\t    NF_INVF(ipinfo, IPT_INV_DSTIP, ipinfo->dmsk.s_addr &&\n \t\t    (ip->daddr & ipinfo->dmsk.s_addr) != ipinfo->dst.s_addr))\n \t\treturn false;\n \n"
  },
  {
    "path": "target/linux/generic/pending-5.10/613-netfilter_optional_tcp_window_check.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nSubject: netfilter: optional tcp window check\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n net/netfilter/nf_conntrack_proto_tcp.c | 13 +++++++++++++\n 1 file changed, 13 insertions(+)\n\n--- a/net/netfilter/nf_conntrack_proto_tcp.c\n+++ b/net/netfilter/nf_conntrack_proto_tcp.c\n@@ -31,6 +31,9 @@\n #include <net/netfilter/ipv4/nf_conntrack_ipv4.h>\n #include <net/netfilter/ipv6/nf_conntrack_ipv6.h>\n \n+/* Do not check the TCP window for incoming packets  */\n+static int nf_ct_tcp_no_window_check __read_mostly = 1;\n+\n /* \"Be conservative in what you do,\n     be liberal in what you accept from others.\"\n     If it's non-zero, we mark only out of window RST segments as INVALID. */\n@@ -476,6 +479,9 @@ static bool tcp_in_window(const struct n\n \ts32 receiver_offset;\n \tbool res, in_recv_win;\n \n+\tif (nf_ct_tcp_no_window_check)\n+\t\treturn true;\n+\n \t/*\n \t * Get the required data from the packet.\n \t */\n@@ -1139,7 +1145,7 @@ int nf_conntrack_tcp_packet(struct nf_co\n \t\t IP_CT_TCP_FLAG_DATA_UNACKNOWLEDGED &&\n \t\t timeouts[new_state] > timeouts[TCP_CONNTRACK_UNACK])\n \t\ttimeout = timeouts[TCP_CONNTRACK_UNACK];\n-\telse if (ct->proto.tcp.last_win == 0 &&\n+\telse if (!nf_ct_tcp_no_window_check && ct->proto.tcp.last_win == 0 &&\n \t\t timeouts[new_state] > timeouts[TCP_CONNTRACK_RETRANS])\n \t\ttimeout = timeouts[TCP_CONNTRACK_RETRANS];\n \telse\n--- a/net/netfilter/nf_conntrack_standalone.c\n+++ b/net/netfilter/nf_conntrack_standalone.c\n@@ -25,6 +25,9 @@\n #include <net/netfilter/nf_conntrack_timestamp.h>\n #include <linux/rculist_nulls.h>\n \n+/* Do not check the TCP window for incoming packets  */\n+static int nf_ct_tcp_no_window_check __read_mostly = 1;\n+\n static bool enable_hooks __read_mostly;\n MODULE_PARM_DESC(enable_hooks, \"Always enable conntrack hooks\");\n module_param(enable_hooks, bool, 0000);\n@@ -660,6 +663,7 @@ enum nf_ct_sysctl_index {\n \tNF_SYSCTL_CT_PROTO_TIMEOUT_GRE_STREAM,\n #endif\n \n+\tNF_SYSCTL_CT_PROTO_TCP_NO_WINDOW_CHECK,\n \t__NF_SYSCTL_CT_LAST_SYSCTL,\n };\n \n@@ -1014,6 +1018,13 @@ static struct ctl_table nf_ct_sysctl_tab\n \t\t.proc_handler   = proc_dointvec_jiffies,\n \t},\n #endif\n+\t[NF_SYSCTL_CT_PROTO_TCP_NO_WINDOW_CHECK] = {\n+\t\t.procname       = \"nf_conntrack_tcp_no_window_check\",\n+\t\t.data           = &nf_ct_tcp_no_window_check,\n+\t\t.maxlen         = sizeof(unsigned int),\n+\t\t.mode           = 0644,\n+\t\t.proc_handler   = proc_dointvec,\n+\t},\n \t{}\n };\n \n"
  },
  {
    "path": "target/linux/generic/pending-5.10/620-net_sched-codel-do-not-defer-queue-length-update.patch",
    "content": "From: Konstantin Khlebnikov <khlebnikov@yandex-team.ru>\nDate: Mon, 21 Aug 2017 11:14:14 +0300\nSubject: [PATCH] net_sched/codel: do not defer queue length update\n\nWhen codel wants to drop last packet in ->dequeue() it cannot call\nqdisc_tree_reduce_backlog() right away - it will notify parent qdisc\nabout zero qlen and HTB/HFSC will deactivate class. The same class will\nbe deactivated second time by caller of ->dequeue(). Currently codel and\nfq_codel defer update. This triggers warning in HFSC when it's qlen != 0\nbut there is no active classes.\n\nThis patch update parent queue length immediately: just temporary increase\nqlen around qdisc_tree_reduce_backlog() to prevent first class deactivation\nif we have skb to return.\n\nThis might open another problem in HFSC - now operation peek could fail and\ndeactivate parent class.\n\nSigned-off-by: Konstantin Khlebnikov <khlebnikov@yandex-team.ru>\nLink: https://bugzilla.kernel.org/show_bug.cgi?id=109581\n---\n\n--- a/net/sched/sch_codel.c\n+++ b/net/sched/sch_codel.c\n@@ -95,11 +95,17 @@ static struct sk_buff *codel_qdisc_deque\n \t\t\t    &q->stats, qdisc_pkt_len, codel_get_enqueue_time,\n \t\t\t    drop_func, dequeue_func);\n \n-\t/* We cant call qdisc_tree_reduce_backlog() if our qlen is 0,\n-\t * or HTB crashes. Defer it for next round.\n+\t/* If our qlen is 0 qdisc_tree_reduce_backlog() will deactivate\n+\t * parent class, dequeue in parent qdisc will do the same if we\n+\t * return skb. Temporary increment qlen if we have skb.\n \t */\n-\tif (q->stats.drop_count && sch->q.qlen) {\n-\t\tqdisc_tree_reduce_backlog(sch, q->stats.drop_count, q->stats.drop_len);\n+\tif (q->stats.drop_count) {\n+\t\tif (skb)\n+\t\t\tsch->q.qlen++;\n+\t\tqdisc_tree_reduce_backlog(sch, q->stats.drop_count,\n+\t\t\t\t\t  q->stats.drop_len);\n+\t\tif (skb)\n+\t\t\tsch->q.qlen--;\n \t\tq->stats.drop_count = 0;\n \t\tq->stats.drop_len = 0;\n \t}\n--- a/net/sched/sch_fq_codel.c\n+++ b/net/sched/sch_fq_codel.c\n@@ -304,6 +304,21 @@ begin:\n \t\t\t    &flow->cvars, &q->cstats, qdisc_pkt_len,\n \t\t\t    codel_get_enqueue_time, drop_func, dequeue_func);\n \n+\t/* If our qlen is 0 qdisc_tree_reduce_backlog() will deactivate\n+\t * parent class, dequeue in parent qdisc will do the same if we\n+\t * return skb. Temporary increment qlen if we have skb.\n+\t */\n+\tif (q->cstats.drop_count) {\n+\t\tif (skb)\n+\t\t\tsch->q.qlen++;\n+\t\tqdisc_tree_reduce_backlog(sch, q->cstats.drop_count,\n+\t\t\t\t\t  q->cstats.drop_len);\n+\t\tif (skb)\n+\t\t\tsch->q.qlen--;\n+\t\tq->cstats.drop_count = 0;\n+\t\tq->cstats.drop_len = 0;\n+\t}\n+\n \tif (!skb) {\n \t\t/* force a pass through old_flows to prevent starvation */\n \t\tif ((head == &q->new_flows) && !list_empty(&q->old_flows))\n@@ -314,15 +329,6 @@ begin:\n \t}\n \tqdisc_bstats_update(sch, skb);\n \tflow->deficit -= qdisc_pkt_len(skb);\n-\t/* We cant call qdisc_tree_reduce_backlog() if our qlen is 0,\n-\t * or HTB crashes. Defer it for next round.\n-\t */\n-\tif (q->cstats.drop_count && sch->q.qlen) {\n-\t\tqdisc_tree_reduce_backlog(sch, q->cstats.drop_count,\n-\t\t\t\t\t  q->cstats.drop_len);\n-\t\tq->cstats.drop_count = 0;\n-\t\tq->cstats.drop_len = 0;\n-\t}\n \treturn skb;\n }\n \n"
  },
  {
    "path": "target/linux/generic/pending-5.10/630-packet_socket_type.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nSubject: net: add an optimization for dealing with raw sockets\n\nlede-commit: 4898039703d7315f0f3431c860123338ec3be0f6\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n include/uapi/linux/if_packet.h |  3 +++\n net/packet/af_packet.c         | 34 +++++++++++++++++++++++++++-------\n net/packet/internal.h          |  1 +\n 3 files changed, 31 insertions(+), 7 deletions(-)\n\n--- a/include/uapi/linux/if_packet.h\n+++ b/include/uapi/linux/if_packet.h\n@@ -33,6 +33,8 @@ struct sockaddr_ll {\n #define PACKET_KERNEL\t\t7\t\t/* To kernel space\t*/\n /* Unused, PACKET_FASTROUTE and PACKET_LOOPBACK are invisible to user space */\n #define PACKET_FASTROUTE\t6\t\t/* Fastrouted frame\t*/\n+#define PACKET_MASK_ANY\t\t0xffffffff\t/* mask for packet type bits */\n+\n \n /* Packet socket options */\n \n@@ -59,6 +61,7 @@ struct sockaddr_ll {\n #define PACKET_ROLLOVER_STATS\t\t21\n #define PACKET_FANOUT_DATA\t\t22\n #define PACKET_IGNORE_OUTGOING\t\t23\n+#define PACKET_RECV_TYPE\t\t24\n \n #define PACKET_FANOUT_HASH\t\t0\n #define PACKET_FANOUT_LB\t\t1\n--- a/net/packet/af_packet.c\n+++ b/net/packet/af_packet.c\n@@ -1822,6 +1822,7 @@ static int packet_rcv_spkt(struct sk_buf\n {\n \tstruct sock *sk;\n \tstruct sockaddr_pkt *spkt;\n+\tstruct packet_sock *po;\n \n \t/*\n \t *\tWhen we registered the protocol we saved the socket in the data\n@@ -1829,6 +1830,7 @@ static int packet_rcv_spkt(struct sk_buf\n \t */\n \n \tsk = pt->af_packet_priv;\n+\tpo = pkt_sk(sk);\n \n \t/*\n \t *\tYank back the headers [hope the device set this\n@@ -1841,7 +1843,7 @@ static int packet_rcv_spkt(struct sk_buf\n \t *\tso that this procedure is noop.\n \t */\n \n-\tif (skb->pkt_type == PACKET_LOOPBACK)\n+\tif (!(po->pkt_type & (1 << skb->pkt_type)))\n \t\tgoto out;\n \n \tif (!net_eq(dev_net(dev), sock_net(sk)))\n@@ -2079,12 +2081,12 @@ static int packet_rcv(struct sk_buff *sk\n \tunsigned int snaplen, res;\n \tbool is_drop_n_account = false;\n \n-\tif (skb->pkt_type == PACKET_LOOPBACK)\n-\t\tgoto drop;\n-\n \tsk = pt->af_packet_priv;\n \tpo = pkt_sk(sk);\n \n+\tif (!(po->pkt_type & (1 << skb->pkt_type)))\n+\t\tgoto drop;\n+\n \tif (!net_eq(dev_net(dev), sock_net(sk)))\n \t\tgoto drop;\n \n@@ -2210,12 +2212,12 @@ static int tpacket_rcv(struct sk_buff *s\n \tBUILD_BUG_ON(TPACKET_ALIGN(sizeof(*h.h2)) != 32);\n \tBUILD_BUG_ON(TPACKET_ALIGN(sizeof(*h.h3)) != 48);\n \n-\tif (skb->pkt_type == PACKET_LOOPBACK)\n-\t\tgoto drop;\n-\n \tsk = pt->af_packet_priv;\n \tpo = pkt_sk(sk);\n \n+\tif (!(po->pkt_type & (1 << skb->pkt_type)))\n+\t\tgoto drop;\n+\n \tif (!net_eq(dev_net(dev), sock_net(sk)))\n \t\tgoto drop;\n \n@@ -3330,6 +3332,7 @@ static int packet_create(struct net *net\n \tmutex_init(&po->pg_vec_lock);\n \tpo->rollover = NULL;\n \tpo->prot_hook.func = packet_rcv;\n+\tpo->pkt_type = PACKET_MASK_ANY & ~(1 << PACKET_LOOPBACK);\n \n \tif (sock->type == SOCK_PACKET)\n \t\tpo->prot_hook.func = packet_rcv_spkt;\n@@ -3974,6 +3977,16 @@ packet_setsockopt(struct socket *sock, i\n \t\tpo->xmit = val ? packet_direct_xmit : dev_queue_xmit;\n \t\treturn 0;\n \t}\n+\tcase PACKET_RECV_TYPE:\n+\t{\n+\t\tunsigned int val;\n+\t\tif (optlen != sizeof(val))\n+\t\t\treturn -EINVAL;\n+\t\tif (copy_from_sockptr(&val, optval, sizeof(val)))\n+\t\t\treturn -EFAULT;\n+\t\tpo->pkt_type = val & ~BIT(PACKET_LOOPBACK);\n+\t\treturn 0;\n+\t}\n \tdefault:\n \t\treturn -ENOPROTOOPT;\n \t}\n@@ -4030,6 +4043,13 @@ static int packet_getsockopt(struct sock\n \tcase PACKET_VNET_HDR:\n \t\tval = po->has_vnet_hdr;\n \t\tbreak;\n+\tcase PACKET_RECV_TYPE:\n+\t\tif (len > sizeof(unsigned int))\n+\t\t\tlen = sizeof(unsigned int);\n+\t\tval = po->pkt_type;\n+\n+\t\tdata = &val;\n+\t\tbreak;\n \tcase PACKET_VERSION:\n \t\tval = po->tp_version;\n \t\tbreak;\n--- a/net/packet/internal.h\n+++ b/net/packet/internal.h\n@@ -137,6 +137,7 @@ struct packet_sock {\n \tint\t\t\t(*xmit)(struct sk_buff *skb);\n \tstruct packet_type\tprot_hook ____cacheline_aligned_in_smp;\n \tatomic_t\t\ttp_drops ____cacheline_aligned_in_smp;\n+\tunsigned int\t\tpkt_type;\n };\n \n static struct packet_sock *pkt_sk(struct sock *sk)\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/655-increase_skb_pad.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nSubject: kernel: add a few patches for avoiding unnecessary skb reallocations - significantly improves ethernet<->wireless performance\n\nlede-commit: 6f89cffc9add6939d44a6b54cf9a5e77849aa7fd\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n include/linux/skbuff.h | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/include/linux/skbuff.h\n+++ b/include/linux/skbuff.h\n@@ -2676,7 +2676,7 @@ static inline int pskb_network_may_pull(\n  * NET_IP_ALIGN(2) + ethernet_header(14) + IP_header(20/40) + ports(8)\n  */\n #ifndef NET_SKB_PAD\n-#define NET_SKB_PAD\tmax(32, L1_CACHE_BYTES)\n+#define NET_SKB_PAD\tmax(64, L1_CACHE_BYTES)\n #endif\n \n int ___pskb_trim(struct sk_buff *skb, unsigned int len);\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/666-Add-support-for-MAP-E-FMRs-mesh-mode.patch",
    "content": "From: Steven Barth <steven@midlink.org>\nSubject: Add support for MAP-E FMRs (mesh mode)\n\nMAP-E FMRs (draft-ietf-softwire-map-10) are rules for IPv4-communication\nbetween MAP CEs (mesh mode) without the need to forward such data to a\nborder relay. This is similar to how 6rd works but for IPv4 over IPv6.\n\nSigned-off-by: Steven Barth <cyrus@openwrt.org>\n---\n include/net/ip6_tunnel.h       |  13 ++\n include/uapi/linux/if_tunnel.h |  13 ++\n net/ipv6/ip6_tunnel.c          | 276 +++++++++++++++++++++++++++++++++++++++--\n 3 files changed, 291 insertions(+), 11 deletions(-)\n\n--- a/include/net/ip6_tunnel.h\n+++ b/include/net/ip6_tunnel.h\n@@ -18,6 +18,18 @@\n /* determine capability on a per-packet basis */\n #define IP6_TNL_F_CAP_PER_PACKET 0x40000\n \n+/* IPv6 tunnel FMR */\n+struct __ip6_tnl_fmr {\n+\tstruct __ip6_tnl_fmr *next; /* next fmr in list */\n+\tstruct in6_addr ip6_prefix;\n+\tstruct in_addr ip4_prefix;\n+\n+\t__u8 ip6_prefix_len;\n+\t__u8 ip4_prefix_len;\n+\t__u8 ea_len;\n+\t__u8 offset;\n+};\n+\n struct __ip6_tnl_parm {\n \tchar name[IFNAMSIZ];\t/* name of tunnel device */\n \tint link;\t\t/* ifindex of underlying L2 interface */\n@@ -29,6 +41,7 @@ struct __ip6_tnl_parm {\n \t__u32 flags;\t\t/* tunnel flags */\n \tstruct in6_addr laddr;\t/* local tunnel end-point address */\n \tstruct in6_addr raddr;\t/* remote tunnel end-point address */\n+\tstruct __ip6_tnl_fmr *fmrs;\t/* FMRs */\n \n \t__be16\t\t\ti_flags;\n \t__be16\t\t\to_flags;\n--- a/include/uapi/linux/if_tunnel.h\n+++ b/include/uapi/linux/if_tunnel.h\n@@ -77,10 +77,23 @@ enum {\n \tIFLA_IPTUN_ENCAP_DPORT,\n \tIFLA_IPTUN_COLLECT_METADATA,\n \tIFLA_IPTUN_FWMARK,\n+\tIFLA_IPTUN_FMRS,\n \t__IFLA_IPTUN_MAX,\n };\n #define IFLA_IPTUN_MAX\t(__IFLA_IPTUN_MAX - 1)\n \n+enum {\n+\tIFLA_IPTUN_FMR_UNSPEC,\n+\tIFLA_IPTUN_FMR_IP6_PREFIX,\n+\tIFLA_IPTUN_FMR_IP4_PREFIX,\n+\tIFLA_IPTUN_FMR_IP6_PREFIX_LEN,\n+\tIFLA_IPTUN_FMR_IP4_PREFIX_LEN,\n+\tIFLA_IPTUN_FMR_EA_LEN,\n+\tIFLA_IPTUN_FMR_OFFSET,\n+\t__IFLA_IPTUN_FMR_MAX,\n+};\n+#define IFLA_IPTUN_FMR_MAX (__IFLA_IPTUN_FMR_MAX - 1)\n+\n enum tunnel_encap_types {\n \tTUNNEL_ENCAP_NONE,\n \tTUNNEL_ENCAP_FOU,\n--- a/net/ipv6/ip6_tunnel.c\n+++ b/net/ipv6/ip6_tunnel.c\n@@ -11,6 +11,9 @@\n  *      linux/net/ipv6/sit.c and linux/net/ipv4/ipip.c\n  *\n  *      RFC 2473\n+ *\n+ *      Changes:\n+ *      Steven Barth <cyrus@openwrt.org>:           MAP-E FMR support\n  */\n \n #define pr_fmt(fmt) KBUILD_MODNAME \": \" fmt\n@@ -67,9 +70,9 @@ static bool log_ecn_error = true;\n module_param(log_ecn_error, bool, 0644);\n MODULE_PARM_DESC(log_ecn_error, \"Log packets received with corrupted ECN\");\n \n-static u32 HASH(const struct in6_addr *addr1, const struct in6_addr *addr2)\n+static u32 HASH(const struct in6_addr *addr)\n {\n-\tu32 hash = ipv6_addr_hash(addr1) ^ ipv6_addr_hash(addr2);\n+\tu32 hash = ipv6_addr_hash(addr);\n \n \treturn hash_32(hash, IP6_TUNNEL_HASH_SIZE_SHIFT);\n }\n@@ -144,17 +147,33 @@ static struct ip6_tnl *\n ip6_tnl_lookup(struct net *net, int link,\n \t       const struct in6_addr *remote, const struct in6_addr *local)\n {\n-\tunsigned int hash = HASH(remote, local);\n+\tunsigned int hash = HASH(local);\n \tstruct ip6_tnl *t, *cand = NULL;\n \tstruct ip6_tnl_net *ip6n = net_generic(net, ip6_tnl_net_id);\n \tstruct in6_addr any;\n \n \tfor_each_ip6_tunnel_rcu(ip6n->tnls_r_l[hash]) {\n \t\tif (!ipv6_addr_equal(local, &t->parms.laddr) ||\n-\t\t    !ipv6_addr_equal(remote, &t->parms.raddr) ||\n \t\t    !(t->dev->flags & IFF_UP))\n \t\t\tcontinue;\n \n+\t\tif (!ipv6_addr_equal(remote, &t->parms.raddr)) {\n+\t\t\tstruct __ip6_tnl_fmr *fmr;\n+\t\t\tbool found = false;\n+\n+\t\t\tfor (fmr = t->parms.fmrs; fmr; fmr = fmr->next) {\n+\t\t\t\tif (!ipv6_prefix_equal(remote, &fmr->ip6_prefix,\n+\t\t\t\t\t\t       fmr->ip6_prefix_len))\n+\t\t\t\t\tcontinue;\n+\n+\t\t\t\tfound = true;\n+\t\t\t\tbreak;\n+\t\t\t}\n+\n+\t\t\tif (!found)\n+\t\t\t\tcontinue;\n+\t\t}\n+\n \t\tif (link == t->parms.link)\n \t\t\treturn t;\n \t\telse\n@@ -162,7 +181,7 @@ ip6_tnl_lookup(struct net *net, int link\n \t}\n \n \tmemset(&any, 0, sizeof(any));\n-\thash = HASH(&any, local);\n+\thash = HASH(local);\n \tfor_each_ip6_tunnel_rcu(ip6n->tnls_r_l[hash]) {\n \t\tif (!ipv6_addr_equal(local, &t->parms.laddr) ||\n \t\t    !ipv6_addr_any(&t->parms.raddr) ||\n@@ -175,7 +194,7 @@ ip6_tnl_lookup(struct net *net, int link\n \t\t\tcand = t;\n \t}\n \n-\thash = HASH(remote, &any);\n+\thash = HASH(&any);\n \tfor_each_ip6_tunnel_rcu(ip6n->tnls_r_l[hash]) {\n \t\tif (!ipv6_addr_equal(remote, &t->parms.raddr) ||\n \t\t    !ipv6_addr_any(&t->parms.laddr) ||\n@@ -223,7 +242,7 @@ ip6_tnl_bucket(struct ip6_tnl_net *ip6n,\n \n \tif (!ipv6_addr_any(remote) || !ipv6_addr_any(local)) {\n \t\tprio = 1;\n-\t\th = HASH(remote, local);\n+\t\th = HASH(local);\n \t}\n \treturn &ip6n->tnls[prio][h];\n }\n@@ -405,6 +424,12 @@ ip6_tnl_dev_uninit(struct net_device *de\n \tstruct net *net = t->net;\n \tstruct ip6_tnl_net *ip6n = net_generic(net, ip6_tnl_net_id);\n \n+\twhile (t->parms.fmrs) {\n+\t\tstruct __ip6_tnl_fmr *next = t->parms.fmrs->next;\n+\t\tkfree(t->parms.fmrs);\n+\t\tt->parms.fmrs = next;\n+\t}\n+\n \tif (dev == ip6n->fb_tnl_dev)\n \t\tRCU_INIT_POINTER(ip6n->tnls_wc[0], NULL);\n \telse\n@@ -821,6 +846,107 @@ int ip6_tnl_rcv_ctl(struct ip6_tnl *t,\n }\n EXPORT_SYMBOL_GPL(ip6_tnl_rcv_ctl);\n \n+/**\n+ * ip4ip6_fmr_calc - calculate target / source IPv6-address based on FMR\n+ *   @dest: destination IPv6 address buffer\n+ *   @skb: received socket buffer\n+ *   @fmr: MAP FMR\n+ *   @xmit: Calculate for xmit or rcv\n+ **/\n+static void ip4ip6_fmr_calc(struct in6_addr *dest,\n+\t\tconst struct iphdr *iph, const uint8_t *end,\n+\t\tconst struct __ip6_tnl_fmr *fmr, bool xmit)\n+{\n+\tint psidlen = fmr->ea_len - (32 - fmr->ip4_prefix_len);\n+\tu8 *portp = NULL;\n+\tbool use_dest_addr;\n+\tconst struct iphdr *dsth = iph;\n+\n+\tif ((u8*)dsth >= end)\n+\t\treturn;\n+\n+\t/* find significant IP header */\n+\tif (iph->protocol == IPPROTO_ICMP) {\n+\t\tstruct icmphdr *ih = (struct icmphdr*)(((u8*)dsth) + dsth->ihl * 4);\n+\t\tif (ih && ((u8*)&ih[1]) <= end && (\n+\t\t\tih->type == ICMP_DEST_UNREACH ||\n+\t\t\tih->type == ICMP_SOURCE_QUENCH ||\n+\t\t\tih->type == ICMP_TIME_EXCEEDED ||\n+\t\t\tih->type == ICMP_PARAMETERPROB ||\n+\t\t\tih->type == ICMP_REDIRECT))\n+\t\t\t\tdsth = (const struct iphdr*)&ih[1];\n+\t}\n+\n+\t/* in xmit-path use dest port by default and source port only if\n+\t\tthis is an ICMP reply to something else; vice versa in rcv-path */\n+\tuse_dest_addr = (xmit && dsth == iph) || (!xmit && dsth != iph);\n+\n+\t/* get dst port */\n+\tif (((u8*)&dsth[1]) <= end && (\n+\t\tdsth->protocol == IPPROTO_UDP ||\n+\t\tdsth->protocol == IPPROTO_TCP ||\n+\t\tdsth->protocol == IPPROTO_SCTP ||\n+\t\tdsth->protocol == IPPROTO_DCCP)) {\n+\t\t\t/* for UDP, TCP, SCTP and DCCP source and dest port\n+\t\t\tfollow IPv4 header directly */\n+\t\t\tportp = ((u8*)dsth) + dsth->ihl * 4;\n+\n+\t\t\tif (use_dest_addr)\n+\t\t\t\tportp += sizeof(u16);\n+\t} else if (iph->protocol == IPPROTO_ICMP) {\n+\t\tstruct icmphdr *ih = (struct icmphdr*)(((u8*)dsth) + dsth->ihl * 4);\n+\n+\t\t/* use icmp identifier as port */\n+\t\tif (((u8*)&ih) <= end && (\n+\t\t    (use_dest_addr && (\n+\t\t    ih->type == ICMP_ECHOREPLY ||\n+\t\t\tih->type == ICMP_TIMESTAMPREPLY ||\n+\t\t\tih->type == ICMP_INFO_REPLY ||\n+\t\t\tih->type == ICMP_ADDRESSREPLY)) ||\n+\t\t\t(!use_dest_addr && (\n+\t\t\tih->type == ICMP_ECHO ||\n+\t\t\tih->type == ICMP_TIMESTAMP ||\n+\t\t\tih->type == ICMP_INFO_REQUEST ||\n+\t\t\tih->type == ICMP_ADDRESS)\n+\t\t\t)))\n+\t\t\t\tportp = (u8*)&ih->un.echo.id;\n+\t}\n+\n+\tif ((portp && &portp[2] <= end) || psidlen == 0) {\n+\t\tint frombyte = fmr->ip6_prefix_len / 8;\n+\t\tint fromrem = fmr->ip6_prefix_len % 8;\n+\t\tint bytes = sizeof(struct in6_addr) - frombyte;\n+\t\tconst u32 *addr = (use_dest_addr) ? &iph->daddr : &iph->saddr;\n+\t\tu64 eabits = ((u64)ntohl(*addr)) << (32 + fmr->ip4_prefix_len);\n+\t\tu64 t = 0;\n+\n+\t\t/* extract PSID from port and add it to eabits */\n+\t\tu16 psidbits = 0;\n+\t\tif (psidlen > 0) {\n+\t\t\tpsidbits = ((u16)portp[0]) << 8 | ((u16)portp[1]);\n+\t\t\tpsidbits >>= 16 - psidlen - fmr->offset;\n+\t\t\tpsidbits = (u16)(psidbits << (16 - psidlen));\n+\t\t\teabits |= ((u64)psidbits) << (48 - (fmr->ea_len - psidlen));\n+\t\t}\n+\n+\t\t/* rewrite destination address */\n+\t\t*dest = fmr->ip6_prefix;\n+\t\tmemcpy(&dest->s6_addr[10], addr, sizeof(*addr));\n+\t\tdest->s6_addr16[7] = htons(psidbits >> (16 - psidlen));\n+\n+\t\tif (bytes > sizeof(u64))\n+\t\t\tbytes = sizeof(u64);\n+\n+\t\t/* insert eabits */\n+\t\tmemcpy(&t, &dest->s6_addr[frombyte], bytes);\n+\t\tt = be64_to_cpu(t) & ~(((((u64)1) << fmr->ea_len) - 1)\n+\t\t\t<< (64 - fmr->ea_len - fromrem));\n+\t\tt = cpu_to_be64(t | (eabits >> fromrem));\n+\t\tmemcpy(&dest->s6_addr[frombyte], &t, bytes);\n+\t}\n+}\n+\n+\n static int __ip6_tnl_rcv(struct ip6_tnl *tunnel, struct sk_buff *skb,\n \t\t\t const struct tnl_ptk_info *tpi,\n \t\t\t struct metadata_dst *tun_dst,\n@@ -873,6 +999,27 @@ static int __ip6_tnl_rcv(struct ip6_tnl\n \tskb_reset_network_header(skb);\n \tmemset(skb->cb, 0, sizeof(struct inet6_skb_parm));\n \n+\tif (tpi->proto == htons(ETH_P_IP) && tunnel->parms.fmrs &&\n+\t\t!ipv6_addr_equal(&ipv6h->saddr, &tunnel->parms.raddr)) {\n+\t\t\t/* Packet didn't come from BR, so lookup FMR */\n+\t\t\tstruct __ip6_tnl_fmr *fmr;\n+\t\t\tstruct in6_addr expected = tunnel->parms.raddr;\n+\t\t\tfor (fmr = tunnel->parms.fmrs; fmr; fmr = fmr->next)\n+\t\t\t\tif (ipv6_prefix_equal(&ipv6h->saddr,\n+\t\t\t\t\t&fmr->ip6_prefix, fmr->ip6_prefix_len))\n+\t\t\t\t\t\tbreak;\n+\n+\t\t\t/* Check that IPv6 matches IPv4 source to prevent spoofing */\n+\t\t\tif (fmr)\n+\t\t\t\tip4ip6_fmr_calc(&expected, ip_hdr(skb),\n+\t\t\t\t\t\tskb_tail_pointer(skb), fmr, false);\n+\n+\t\t\tif (!ipv6_addr_equal(&ipv6h->saddr, &expected)) {\n+\t\t\t\trcu_read_unlock();\n+\t\t\t\tgoto drop;\n+\t\t\t}\n+\t}\n+\n \t__skb_tunnel_rx(skb, tunnel->dev, tunnel->net);\n \n \terr = dscp_ecn_decapsulate(tunnel, ipv6h, skb);\n@@ -1024,6 +1171,7 @@ static void init_tel_txopt(struct ipv6_t\n \topt->ops.opt_nflen = 8;\n }\n \n+\n /**\n  * ip6_tnl_addr_conflict - compare packet addresses to tunnel's own\n  *   @t: the outgoing tunnel device\n@@ -1304,6 +1452,7 @@ ipxip6_tnl_xmit(struct sk_buff *skb, str\n \t\tu8 protocol)\n {\n \tstruct ip6_tnl *t = netdev_priv(dev);\n+\tstruct __ip6_tnl_fmr *fmr;\n \tstruct ipv6hdr *ipv6h;\n \tconst struct iphdr  *iph;\n \tint encap_limit = -1;\n@@ -1403,6 +1552,18 @@ ipxip6_tnl_xmit(struct sk_buff *skb, str\n \tfl6.flowi6_uid = sock_net_uid(dev_net(dev), NULL);\n \tdsfield = INET_ECN_encapsulate(dsfield, orig_dsfield);\n \n+\t/* try to find matching FMR */\n+\tfor (fmr = t->parms.fmrs; fmr; fmr = fmr->next) {\n+\t\tunsigned mshift = 32 - fmr->ip4_prefix_len;\n+\t\tif (ntohl(fmr->ip4_prefix.s_addr) >> mshift ==\n+\t\t\t\tntohl(ip_hdr(skb)->daddr) >> mshift)\n+\t\t\tbreak;\n+\t}\n+\n+\t/* change dstaddr according to FMR */\n+\tif (fmr)\n+\t\tip4ip6_fmr_calc(&fl6.daddr, ip_hdr(skb), skb_tail_pointer(skb), fmr, true);\n+\n \tif (iptunnel_handle_offloads(skb, SKB_GSO_IPXIP6))\n \t\treturn -1;\n \n@@ -1555,6 +1716,14 @@ ip6_tnl_change(struct ip6_tnl *t, const\n \tt->parms.link = p->link;\n \tt->parms.proto = p->proto;\n \tt->parms.fwmark = p->fwmark;\n+\n+\twhile (t->parms.fmrs) {\n+\t\tstruct __ip6_tnl_fmr *next = t->parms.fmrs->next;\n+\t\tkfree(t->parms.fmrs);\n+\t\tt->parms.fmrs = next;\n+\t}\n+\tt->parms.fmrs = p->fmrs;\n+\n \tdst_cache_reset(&t->dst_cache);\n \tip6_tnl_link_config(t);\n \treturn 0;\n@@ -1593,6 +1762,7 @@ ip6_tnl_parm_from_user(struct __ip6_tnl_\n \tp->flowinfo = u->flowinfo;\n \tp->link = u->link;\n \tp->proto = u->proto;\n+\tp->fmrs = NULL;\n \tmemcpy(p->name, u->name, sizeof(u->name));\n }\n \n@@ -1978,6 +2148,15 @@ static int ip6_tnl_validate(struct nlatt\n \treturn 0;\n }\n \n+static const struct nla_policy ip6_tnl_fmr_policy[IFLA_IPTUN_FMR_MAX + 1] = {\n+\t[IFLA_IPTUN_FMR_IP6_PREFIX] = { .len = sizeof(struct in6_addr) },\n+\t[IFLA_IPTUN_FMR_IP4_PREFIX] = { .len = sizeof(struct in_addr) },\n+\t[IFLA_IPTUN_FMR_IP6_PREFIX_LEN] = { .type = NLA_U8 },\n+\t[IFLA_IPTUN_FMR_IP4_PREFIX_LEN] = { .type = NLA_U8 },\n+\t[IFLA_IPTUN_FMR_EA_LEN] = { .type = NLA_U8 },\n+\t[IFLA_IPTUN_FMR_OFFSET] = { .type = NLA_U8 }\n+};\n+\n static void ip6_tnl_netlink_parms(struct nlattr *data[],\n \t\t\t\t  struct __ip6_tnl_parm *parms)\n {\n@@ -2015,6 +2194,46 @@ static void ip6_tnl_netlink_parms(struct\n \n \tif (data[IFLA_IPTUN_FWMARK])\n \t\tparms->fwmark = nla_get_u32(data[IFLA_IPTUN_FWMARK]);\n+\n+\tif (data[IFLA_IPTUN_FMRS]) {\n+\t\tunsigned rem;\n+\t\tstruct nlattr *fmr;\n+\t\tnla_for_each_nested(fmr, data[IFLA_IPTUN_FMRS], rem) {\n+\t\t\tstruct nlattr *fmrd[IFLA_IPTUN_FMR_MAX + 1], *c;\n+\t\t\tstruct __ip6_tnl_fmr *nfmr;\n+\n+\t\t\tnla_parse_nested(fmrd, IFLA_IPTUN_FMR_MAX,\n+\t\t\t\tfmr, ip6_tnl_fmr_policy, NULL);\n+\n+\t\t\tif (!(nfmr = kzalloc(sizeof(*nfmr), GFP_KERNEL)))\n+\t\t\t\tcontinue;\n+\n+\t\t\tnfmr->offset = 6;\n+\n+\t\t\tif ((c = fmrd[IFLA_IPTUN_FMR_IP6_PREFIX]))\n+\t\t\t\tnla_memcpy(&nfmr->ip6_prefix, fmrd[IFLA_IPTUN_FMR_IP6_PREFIX],\n+\t\t\t\t\tsizeof(nfmr->ip6_prefix));\n+\n+\t\t\tif ((c = fmrd[IFLA_IPTUN_FMR_IP4_PREFIX]))\n+\t\t\t\tnla_memcpy(&nfmr->ip4_prefix, fmrd[IFLA_IPTUN_FMR_IP4_PREFIX],\n+\t\t\t\t\tsizeof(nfmr->ip4_prefix));\n+\n+\t\t\tif ((c = fmrd[IFLA_IPTUN_FMR_IP6_PREFIX_LEN]))\n+\t\t\t\tnfmr->ip6_prefix_len = nla_get_u8(c);\n+\n+\t\t\tif ((c = fmrd[IFLA_IPTUN_FMR_IP4_PREFIX_LEN]))\n+\t\t\t\tnfmr->ip4_prefix_len = nla_get_u8(c);\n+\n+\t\t\tif ((c = fmrd[IFLA_IPTUN_FMR_EA_LEN]))\n+\t\t\t\tnfmr->ea_len = nla_get_u8(c);\n+\n+\t\t\tif ((c = fmrd[IFLA_IPTUN_FMR_OFFSET]))\n+\t\t\t\tnfmr->offset = nla_get_u8(c);\n+\n+\t\t\tnfmr->next = parms->fmrs;\n+\t\t\tparms->fmrs = nfmr;\n+\t\t}\n+\t}\n }\n \n static bool ip6_tnl_netlink_encap_parms(struct nlattr *data[],\n@@ -2130,6 +2349,12 @@ static void ip6_tnl_dellink(struct net_d\n \n static size_t ip6_tnl_get_size(const struct net_device *dev)\n {\n+\tconst struct ip6_tnl *t = netdev_priv(dev);\n+\tstruct __ip6_tnl_fmr *c;\n+\tint fmrs = 0;\n+\tfor (c = t->parms.fmrs; c; c = c->next)\n+\t\t++fmrs;\n+\n \treturn\n \t\t/* IFLA_IPTUN_LINK */\n \t\tnla_total_size(4) +\n@@ -2159,6 +2384,24 @@ static size_t ip6_tnl_get_size(const str\n \t\tnla_total_size(0) +\n \t\t/* IFLA_IPTUN_FWMARK */\n \t\tnla_total_size(4) +\n+\t\t/* IFLA_IPTUN_FMRS */\n+\t\tnla_total_size(0) +\n+\t\t(\n+\t\t\t/* nest */\n+\t\t\tnla_total_size(0) +\n+\t\t\t/* IFLA_IPTUN_FMR_IP6_PREFIX */\n+\t\t\tnla_total_size(sizeof(struct in6_addr)) +\n+\t\t\t/* IFLA_IPTUN_FMR_IP4_PREFIX */\n+\t\t\tnla_total_size(sizeof(struct in_addr)) +\n+\t\t\t/* IFLA_IPTUN_FMR_EA_LEN */\n+\t\t\tnla_total_size(1) +\n+\t\t\t/* IFLA_IPTUN_FMR_IP6_PREFIX_LEN */\n+\t\t\tnla_total_size(1) +\n+\t\t\t/* IFLA_IPTUN_FMR_IP4_PREFIX_LEN */\n+\t\t\tnla_total_size(1) +\n+\t\t\t/* IFLA_IPTUN_FMR_OFFSET */\n+\t\t\tnla_total_size(1)\n+\t\t) * fmrs +\n \t\t0;\n }\n \n@@ -2166,6 +2409,9 @@ static int ip6_tnl_fill_info(struct sk_b\n {\n \tstruct ip6_tnl *tunnel = netdev_priv(dev);\n \tstruct __ip6_tnl_parm *parm = &tunnel->parms;\n+\tstruct __ip6_tnl_fmr *c;\n+\tint fmrcnt = 0;\n+\tstruct nlattr *fmrs;\n \n \tif (nla_put_u32(skb, IFLA_IPTUN_LINK, parm->link) ||\n \t    nla_put_in6_addr(skb, IFLA_IPTUN_LOCAL, &parm->laddr) ||\n@@ -2175,9 +2421,27 @@ static int ip6_tnl_fill_info(struct sk_b\n \t    nla_put_be32(skb, IFLA_IPTUN_FLOWINFO, parm->flowinfo) ||\n \t    nla_put_u32(skb, IFLA_IPTUN_FLAGS, parm->flags) ||\n \t    nla_put_u8(skb, IFLA_IPTUN_PROTO, parm->proto) ||\n-\t    nla_put_u32(skb, IFLA_IPTUN_FWMARK, parm->fwmark))\n+\t    nla_put_u32(skb, IFLA_IPTUN_FWMARK, parm->fwmark) ||\n+\t    !(fmrs = nla_nest_start(skb, IFLA_IPTUN_FMRS)))\n \t\tgoto nla_put_failure;\n \n+\tfor (c = parm->fmrs; c; c = c->next) {\n+\t\tstruct nlattr *fmr = nla_nest_start(skb, ++fmrcnt);\n+\t\tif (!fmr ||\n+\t\t\tnla_put(skb, IFLA_IPTUN_FMR_IP6_PREFIX,\n+\t\t\t\tsizeof(c->ip6_prefix), &c->ip6_prefix) ||\n+\t\t\tnla_put(skb, IFLA_IPTUN_FMR_IP4_PREFIX,\n+\t\t\t\tsizeof(c->ip4_prefix), &c->ip4_prefix) ||\n+\t\t\tnla_put_u8(skb, IFLA_IPTUN_FMR_IP6_PREFIX_LEN, c->ip6_prefix_len) ||\n+\t\t\tnla_put_u8(skb, IFLA_IPTUN_FMR_IP4_PREFIX_LEN, c->ip4_prefix_len) ||\n+\t\t\tnla_put_u8(skb, IFLA_IPTUN_FMR_EA_LEN, c->ea_len) ||\n+\t\t\tnla_put_u8(skb, IFLA_IPTUN_FMR_OFFSET, c->offset))\n+\t\t\t\tgoto nla_put_failure;\n+\n+\t\tnla_nest_end(skb, fmr);\n+\t}\n+\tnla_nest_end(skb, fmrs);\n+\n \tif (nla_put_u16(skb, IFLA_IPTUN_ENCAP_TYPE, tunnel->encap.type) ||\n \t    nla_put_be16(skb, IFLA_IPTUN_ENCAP_SPORT, tunnel->encap.sport) ||\n \t    nla_put_be16(skb, IFLA_IPTUN_ENCAP_DPORT, tunnel->encap.dport) ||\n@@ -2217,6 +2481,7 @@ static const struct nla_policy ip6_tnl_p\n \t[IFLA_IPTUN_ENCAP_DPORT]\t= { .type = NLA_U16 },\n \t[IFLA_IPTUN_COLLECT_METADATA]\t= { .type = NLA_FLAG },\n \t[IFLA_IPTUN_FWMARK]\t\t= { .type = NLA_U32 },\n+\t[IFLA_IPTUN_FMRS]\t\t= { .type = NLA_NESTED },\n };\n \n static struct rtnl_link_ops ip6_link_ops __read_mostly = {\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/670-ipv6-allow-rejecting-with-source-address-failed-policy.patch",
    "content": "From: Jonas Gorski <jogo@openwrt.org>\nSubject: ipv6: allow rejecting with \"source address failed policy\"\n\nRFC6204 L-14 requires rejecting traffic from invalid addresses with\nICMPv6 Destination Unreachable, Code 5 (Source address failed ingress/\negress policy) on the LAN side, so add an appropriate rule for that.\n\nSigned-off-by: Jonas Gorski <jogo@openwrt.org>\n---\n include/net/netns/ipv6.h       |  1 +\n include/uapi/linux/fib_rules.h |  4 +++\n include/uapi/linux/rtnetlink.h |  1 +\n net/ipv4/fib_semantics.c       |  4 +++\n net/ipv4/fib_trie.c            |  1 +\n net/ipv4/ipmr.c                |  1 +\n net/ipv6/fib6_rules.c          |  4 +++\n net/ipv6/ip6mr.c               |  2 ++\n net/ipv6/route.c               | 58 +++++++++++++++++++++++++++++++++++++++++-\n 9 files changed, 75 insertions(+), 1 deletion(-)\n\n--- a/include/net/netns/ipv6.h\n+++ b/include/net/netns/ipv6.h\n@@ -88,6 +88,7 @@ struct netns_ipv6 {\n \tunsigned int\t\tfib6_routes_require_src;\n #endif\n \tstruct rt6_info         *ip6_prohibit_entry;\n+\tstruct rt6_info\t\t*ip6_policy_failed_entry;\n \tstruct rt6_info         *ip6_blk_hole_entry;\n \tstruct fib6_table       *fib6_local_tbl;\n \tstruct fib_rules_ops    *fib6_rules_ops;\n--- a/include/uapi/linux/fib_rules.h\n+++ b/include/uapi/linux/fib_rules.h\n@@ -82,6 +82,10 @@ enum {\n \tFR_ACT_BLACKHOLE,\t/* Drop without notification */\n \tFR_ACT_UNREACHABLE,\t/* Drop with ENETUNREACH */\n \tFR_ACT_PROHIBIT,\t/* Drop with EACCES */\n+\tFR_ACT_RES9,\n+\tFR_ACT_RES10,\n+\tFR_ACT_RES11,\n+\tFR_ACT_POLICY_FAILED,\t/* Drop with EACCES */\n \t__FR_ACT_MAX,\n };\n \n--- a/include/uapi/linux/rtnetlink.h\n+++ b/include/uapi/linux/rtnetlink.h\n@@ -249,6 +249,7 @@ enum {\n \tRTN_THROW,\t\t/* Not in this table\t\t*/\n \tRTN_NAT,\t\t/* Translate this address\t*/\n \tRTN_XRESOLVE,\t\t/* Use external resolver\t*/\n+\tRTN_POLICY_FAILED,\t/* Failed ingress/egress policy */\n \t__RTN_MAX\n };\n \n--- a/net/ipv4/fib_semantics.c\n+++ b/net/ipv4/fib_semantics.c\n@@ -142,6 +142,10 @@ const struct fib_prop fib_props[RTN_MAX\n \t\t.error\t= -EINVAL,\n \t\t.scope\t= RT_SCOPE_NOWHERE,\n \t},\n+\t[RTN_POLICY_FAILED] = {\n+\t\t.error\t= -EACCES,\n+\t\t.scope\t= RT_SCOPE_UNIVERSE,\n+\t},\n };\n \n static void rt_fibinfo_free(struct rtable __rcu **rtp)\n--- a/net/ipv4/fib_trie.c\n+++ b/net/ipv4/fib_trie.c\n@@ -2734,6 +2734,7 @@ static const char *const rtn_type_names[\n \t[RTN_THROW] = \"THROW\",\n \t[RTN_NAT] = \"NAT\",\n \t[RTN_XRESOLVE] = \"XRESOLVE\",\n+\t[RTN_POLICY_FAILED] = \"POLICY_FAILED\",\n };\n \n static inline const char *rtn_type(char *buf, size_t len, unsigned int t)\n--- a/net/ipv4/ipmr.c\n+++ b/net/ipv4/ipmr.c\n@@ -175,6 +175,7 @@ static int ipmr_rule_action(struct fib_r\n \tcase FR_ACT_UNREACHABLE:\n \t\treturn -ENETUNREACH;\n \tcase FR_ACT_PROHIBIT:\n+\tcase FR_ACT_POLICY_FAILED:\n \t\treturn -EACCES;\n \tcase FR_ACT_BLACKHOLE:\n \tdefault:\n--- a/net/ipv6/fib6_rules.c\n+++ b/net/ipv6/fib6_rules.c\n@@ -220,6 +220,10 @@ static int __fib6_rule_action(struct fib\n \t\terr = -EACCES;\n \t\trt = net->ipv6.ip6_prohibit_entry;\n \t\tgoto discard_pkt;\n+\tcase FR_ACT_POLICY_FAILED:\n+\t\terr = -EACCES;\n+\t\trt = net->ipv6.ip6_policy_failed_entry;\n+\t\tgoto discard_pkt;\n \t}\n \n \ttb_id = fib_rule_get_table(rule, arg);\n--- a/net/ipv6/ip6mr.c\n+++ b/net/ipv6/ip6mr.c\n@@ -163,6 +163,8 @@ static int ip6mr_rule_action(struct fib_\n \t\treturn -ENETUNREACH;\n \tcase FR_ACT_PROHIBIT:\n \t\treturn -EACCES;\n+\tcase FR_ACT_POLICY_FAILED:\n+\t\treturn -EACCES;\n \tcase FR_ACT_BLACKHOLE:\n \tdefault:\n \t\treturn -EINVAL;\n--- a/net/ipv6/route.c\n+++ b/net/ipv6/route.c\n@@ -95,6 +95,8 @@ static int\t\tip6_pkt_discard(struct sk_bu\n static int\t\tip6_pkt_discard_out(struct net *net, struct sock *sk, struct sk_buff *skb);\n static int\t\tip6_pkt_prohibit(struct sk_buff *skb);\n static int\t\tip6_pkt_prohibit_out(struct net *net, struct sock *sk, struct sk_buff *skb);\n+static int\t\tip6_pkt_policy_failed(struct sk_buff *skb);\n+static int\t\tip6_pkt_policy_failed_out(struct net *net, struct sock *sk, struct sk_buff *skb);\n static void\t\tip6_link_failure(struct sk_buff *skb);\n static void\t\tip6_rt_update_pmtu(struct dst_entry *dst, struct sock *sk,\n \t\t\t\t\t   struct sk_buff *skb, u32 mtu,\n@@ -310,6 +312,18 @@ static const struct rt6_info ip6_prohibi\n \t.rt6i_flags\t= (RTF_REJECT | RTF_NONEXTHOP),\n };\n \n+static const struct rt6_info ip6_policy_failed_entry_template = {\n+\t.dst = {\n+\t\t.__refcnt\t= ATOMIC_INIT(1),\n+\t\t.__use\t\t= 1,\n+\t\t.obsolete\t= DST_OBSOLETE_FORCE_CHK,\n+\t\t.error\t\t= -EACCES,\n+\t\t.input\t\t= ip6_pkt_policy_failed,\n+\t\t.output\t\t= ip6_pkt_policy_failed_out,\n+\t},\n+\t.rt6i_flags\t= (RTF_REJECT | RTF_NONEXTHOP),\n+};\n+\n static const struct rt6_info ip6_blk_hole_entry_template = {\n \t.dst = {\n \t\t.__refcnt\t= ATOMIC_INIT(1),\n@@ -1031,6 +1045,7 @@ static const int fib6_prop[RTN_MAX + 1]\n \t[RTN_BLACKHOLE]\t= -EINVAL,\n \t[RTN_UNREACHABLE] = -EHOSTUNREACH,\n \t[RTN_PROHIBIT]\t= -EACCES,\n+\t[RTN_POLICY_FAILED] = -EACCES,\n \t[RTN_THROW]\t= -EAGAIN,\n \t[RTN_NAT]\t= -EINVAL,\n \t[RTN_XRESOLVE]\t= -EINVAL,\n@@ -1066,6 +1081,10 @@ static void ip6_rt_init_dst_reject(struc\n \t\trt->dst.output = ip6_pkt_prohibit_out;\n \t\trt->dst.input = ip6_pkt_prohibit;\n \t\tbreak;\n+\tcase RTN_POLICY_FAILED:\n+\t\trt->dst.output = ip6_pkt_policy_failed_out;\n+\t\trt->dst.input = ip6_pkt_policy_failed;\n+\t\tbreak;\n \tcase RTN_THROW:\n \tcase RTN_UNREACHABLE:\n \tdefault:\n@@ -4449,6 +4468,17 @@ static int ip6_pkt_prohibit_out(struct n\n \treturn ip6_pkt_drop(skb, ICMPV6_ADM_PROHIBITED, IPSTATS_MIB_OUTNOROUTES);\n }\n \n+static int ip6_pkt_policy_failed(struct sk_buff *skb)\n+{\n+\treturn ip6_pkt_drop(skb, ICMPV6_POLICY_FAIL, IPSTATS_MIB_INNOROUTES);\n+}\n+\n+static int ip6_pkt_policy_failed_out(struct net *net, struct sock *sk, struct sk_buff *skb)\n+{\n+\tskb->dev = skb_dst(skb)->dev;\n+\treturn ip6_pkt_drop(skb, ICMPV6_POLICY_FAIL, IPSTATS_MIB_OUTNOROUTES);\n+}\n+\n /*\n  *\tAllocate a dst for local (unicast / anycast) address.\n  */\n@@ -4929,7 +4959,8 @@ static int rtm_to_fib6_config(struct sk_\n \tif (rtm->rtm_type == RTN_UNREACHABLE ||\n \t    rtm->rtm_type == RTN_BLACKHOLE ||\n \t    rtm->rtm_type == RTN_PROHIBIT ||\n-\t    rtm->rtm_type == RTN_THROW)\n+\t    rtm->rtm_type == RTN_THROW ||\n+\t    rtm->rtm_type == RTN_POLICY_FAILED)\n \t\tcfg->fc_flags |= RTF_REJECT;\n \n \tif (rtm->rtm_type == RTN_LOCAL)\n@@ -6128,6 +6159,8 @@ static int ip6_route_dev_notify(struct n\n #ifdef CONFIG_IPV6_MULTIPLE_TABLES\n \t\tnet->ipv6.ip6_prohibit_entry->dst.dev = dev;\n \t\tnet->ipv6.ip6_prohibit_entry->rt6i_idev = in6_dev_get(dev);\n+\t\tnet->ipv6.ip6_policy_failed_entry->dst.dev = dev;\n+\t\tnet->ipv6.ip6_policy_failed_entry->rt6i_idev = in6_dev_get(dev);\n \t\tnet->ipv6.ip6_blk_hole_entry->dst.dev = dev;\n \t\tnet->ipv6.ip6_blk_hole_entry->rt6i_idev = in6_dev_get(dev);\n #endif\n@@ -6139,6 +6172,7 @@ static int ip6_route_dev_notify(struct n\n \t\tin6_dev_put_clear(&net->ipv6.ip6_null_entry->rt6i_idev);\n #ifdef CONFIG_IPV6_MULTIPLE_TABLES\n \t\tin6_dev_put_clear(&net->ipv6.ip6_prohibit_entry->rt6i_idev);\n+\t\tin6_dev_put_clear(&net->ipv6.ip6_policy_failed_entry->rt6i_idev);\n \t\tin6_dev_put_clear(&net->ipv6.ip6_blk_hole_entry->rt6i_idev);\n #endif\n \t}\n@@ -6330,6 +6364,8 @@ static int __net_init ip6_route_net_init\n \n #ifdef CONFIG_IPV6_MULTIPLE_TABLES\n \tnet->ipv6.fib6_has_custom_rules = false;\n+\n+\n \tnet->ipv6.ip6_prohibit_entry = kmemdup(&ip6_prohibit_entry_template,\n \t\t\t\t\t       sizeof(*net->ipv6.ip6_prohibit_entry),\n \t\t\t\t\t       GFP_KERNEL);\n@@ -6340,11 +6376,21 @@ static int __net_init ip6_route_net_init\n \t\t\t ip6_template_metrics, true);\n \tINIT_LIST_HEAD(&net->ipv6.ip6_prohibit_entry->rt6i_uncached);\n \n+\tnet->ipv6.ip6_policy_failed_entry =\n+\t\t\t\tkmemdup(&ip6_policy_failed_entry_template,\n+\t\t\t\tsizeof(*net->ipv6.ip6_policy_failed_entry), GFP_KERNEL);\n+\tif (!net->ipv6.ip6_policy_failed_entry)\n+\t\tgoto out_ip6_prohibit_entry;\n+\tnet->ipv6.ip6_policy_failed_entry->dst.ops = &net->ipv6.ip6_dst_ops;\n+\tdst_init_metrics(&net->ipv6.ip6_policy_failed_entry->dst,\n+\t\t\t ip6_template_metrics, true);\n+\tINIT_LIST_HEAD(&net->ipv6.ip6_policy_failed_entry->rt6i_uncached);\n+\n \tnet->ipv6.ip6_blk_hole_entry = kmemdup(&ip6_blk_hole_entry_template,\n \t\t\t\t\t       sizeof(*net->ipv6.ip6_blk_hole_entry),\n \t\t\t\t\t       GFP_KERNEL);\n \tif (!net->ipv6.ip6_blk_hole_entry)\n-\t\tgoto out_ip6_prohibit_entry;\n+\t\tgoto out_ip6_policy_failed_entry;\n \tnet->ipv6.ip6_blk_hole_entry->dst.ops = &net->ipv6.ip6_dst_ops;\n \tdst_init_metrics(&net->ipv6.ip6_blk_hole_entry->dst,\n \t\t\t ip6_template_metrics, true);\n@@ -6371,6 +6417,8 @@ out:\n \treturn ret;\n \n #ifdef CONFIG_IPV6_MULTIPLE_TABLES\n+out_ip6_policy_failed_entry:\n+\tkfree(net->ipv6.ip6_policy_failed_entry);\n out_ip6_prohibit_entry:\n \tkfree(net->ipv6.ip6_prohibit_entry);\n out_ip6_null_entry:\n@@ -6390,6 +6438,7 @@ static void __net_exit ip6_route_net_exi\n \tkfree(net->ipv6.ip6_null_entry);\n #ifdef CONFIG_IPV6_MULTIPLE_TABLES\n \tkfree(net->ipv6.ip6_prohibit_entry);\n+\tkfree(net->ipv6.ip6_policy_failed_entry);\n \tkfree(net->ipv6.ip6_blk_hole_entry);\n #endif\n \tdst_entries_destroy(&net->ipv6.ip6_dst_ops);\n@@ -6467,6 +6516,9 @@ void __init ip6_route_init_special_entri\n \tinit_net.ipv6.ip6_prohibit_entry->rt6i_idev = in6_dev_get(init_net.loopback_dev);\n \tinit_net.ipv6.ip6_blk_hole_entry->dst.dev = init_net.loopback_dev;\n \tinit_net.ipv6.ip6_blk_hole_entry->rt6i_idev = in6_dev_get(init_net.loopback_dev);\n+\tinit_net.ipv6.ip6_policy_failed_entry->dst.dev = init_net.loopback_dev;\n+\tinit_net.ipv6.ip6_policy_failed_entry->rt6i_idev =\n+\t\tin6_dev_get(init_net.loopback_dev);\n   #endif\n }\n \n"
  },
  {
    "path": "target/linux/generic/pending-5.10/671-net-provide-defines-for-_POLICY_FAILED-until-all-cod.patch",
    "content": "From: Jonas Gorski <jogo@openwrt.org>\nSubject: net: provide defines for _POLICY_FAILED until all code is updated\n\nUpstream introduced ICMPV6_POLICY_FAIL for code 5 of destination\nunreachable, conflicting with our name.\n\nAdd appropriate defines to allow our code to build with the new\nname until we have updated our local patches for older kernels\nand userspace packages.\n\nSigned-off-by: Jonas Gorski <jogo@openwrt.org>\n---\n include/uapi/linux/fib_rules.h | 2 ++\n include/uapi/linux/icmpv6.h    | 2 ++\n include/uapi/linux/rtnetlink.h | 2 ++\n 3 files changed, 6 insertions(+)\n\n--- a/include/uapi/linux/fib_rules.h\n+++ b/include/uapi/linux/fib_rules.h\n@@ -89,6 +89,8 @@ enum {\n \t__FR_ACT_MAX,\n };\n \n+#define FR_ACT_FAILED_POLICY FR_ACT_POLICY_FAILED\n+\n #define FR_ACT_MAX (__FR_ACT_MAX - 1)\n \n #endif\n--- a/include/uapi/linux/icmpv6.h\n+++ b/include/uapi/linux/icmpv6.h\n@@ -126,6 +126,8 @@ struct icmp6hdr {\n #define ICMPV6_POLICY_FAIL\t\t5\n #define ICMPV6_REJECT_ROUTE\t\t6\n \n+#define ICMPV6_FAILED_POLICY\t\tICMPV6_POLICY_FAIL\n+\n /*\n  *\tCodes for Time Exceeded\n  */\n--- a/include/uapi/linux/rtnetlink.h\n+++ b/include/uapi/linux/rtnetlink.h\n@@ -253,6 +253,8 @@ enum {\n \t__RTN_MAX\n };\n \n+#define RTN_FAILED_POLICY RTN_POLICY_FAILED\n+\n #define RTN_MAX (__RTN_MAX - 1)\n \n \n"
  },
  {
    "path": "target/linux/generic/pending-5.10/680-NET-skip-GRO-for-foreign-MAC-addresses.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nSubject: net: replace GRO optimization patch with a new one that supports VLANs/bridges with different MAC addresses\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n include/linux/netdevice.h |  2 ++\n include/linux/skbuff.h    |  3 ++-\n net/core/dev.c            | 48 +++++++++++++++++++++++++++++++++++++++++++++++\n net/ethernet/eth.c        | 18 +++++++++++++++++-\n 4 files changed, 69 insertions(+), 2 deletions(-)\n\n--- a/include/linux/netdevice.h\n+++ b/include/linux/netdevice.h\n@@ -2036,6 +2036,8 @@ struct net_device {\n \tstruct netdev_hw_addr_list\tmc;\n \tstruct netdev_hw_addr_list\tdev_addrs;\n \n+\tunsigned char\t\tlocal_addr_mask[MAX_ADDR_LEN];\n+\n #ifdef CONFIG_SYSFS\n \tstruct kset\t\t*queues_kset;\n #endif\n--- a/include/linux/skbuff.h\n+++ b/include/linux/skbuff.h\n@@ -858,6 +858,7 @@ struct sk_buff {\n #ifdef CONFIG_TLS_DEVICE\n \t__u8\t\t\tdecrypted:1;\n #endif\n+\t__u8\t\t\tgro_skip:1;\n \n #ifdef CONFIG_NET_SCHED\n \t__u16\t\t\ttc_index;\t/* traffic control index */\n--- a/net/core/dev.c\n+++ b/net/core/dev.c\n@@ -6062,6 +6062,9 @@ static enum gro_result dev_gro_receive(s\n \tint same_flow;\n \tint grow;\n \n+\tif (skb->gro_skip)\n+\t\tgoto normal;\n+\n \tif (netif_elide_gro(skb->dev))\n \t\tgoto normal;\n \n@@ -8039,6 +8042,48 @@ static void __netdev_adjacent_dev_unlink\n \t\t\t\t\t   &upper_dev->adj_list.lower);\n }\n \n+static void __netdev_addr_mask(unsigned char *mask, const unsigned char *addr,\n+\t\t\t       struct net_device *dev)\n+{\n+\tint i;\n+\n+\tfor (i = 0; i < dev->addr_len; i++)\n+\t\tmask[i] |= addr[i] ^ dev->dev_addr[i];\n+}\n+\n+static void __netdev_upper_mask(unsigned char *mask, struct net_device *dev,\n+\t\t\t\tstruct net_device *lower)\n+{\n+\tstruct net_device *cur;\n+\tstruct list_head *iter;\n+\n+\tnetdev_for_each_upper_dev_rcu(dev, cur, iter) {\n+\t\t__netdev_addr_mask(mask, cur->dev_addr, lower);\n+\t\t__netdev_upper_mask(mask, cur, lower);\n+\t}\n+}\n+\n+static void __netdev_update_addr_mask(struct net_device *dev)\n+{\n+\tunsigned char mask[MAX_ADDR_LEN];\n+\tstruct net_device *cur;\n+\tstruct list_head *iter;\n+\n+\tmemset(mask, 0, sizeof(mask));\n+\t__netdev_upper_mask(mask, dev, dev);\n+\tmemcpy(dev->local_addr_mask, mask, dev->addr_len);\n+\n+\tnetdev_for_each_lower_dev(dev, cur, iter)\n+\t\t__netdev_update_addr_mask(cur);\n+}\n+\n+static void netdev_update_addr_mask(struct net_device *dev)\n+{\n+\trcu_read_lock();\n+\t__netdev_update_addr_mask(dev);\n+\trcu_read_unlock();\n+}\n+\n static int __netdev_upper_dev_link(struct net_device *dev,\n \t\t\t\t   struct net_device *upper_dev, bool master,\n \t\t\t\t   void *upper_priv, void *upper_info,\n@@ -8090,6 +8135,7 @@ static int __netdev_upper_dev_link(struc\n \tif (ret)\n \t\treturn ret;\n \n+\tnetdev_update_addr_mask(dev);\n \tret = call_netdevice_notifiers_info(NETDEV_CHANGEUPPER,\n \t\t\t\t\t    &changeupper_info.info);\n \tret = notifier_to_errno(ret);\n@@ -8186,6 +8232,7 @@ static void __netdev_upper_dev_unlink(st\n \n \t__netdev_adjacent_dev_unlink_neighbour(dev, upper_dev);\n \n+\tnetdev_update_addr_mask(dev);\n \tcall_netdevice_notifiers_info(NETDEV_CHANGEUPPER,\n \t\t\t\t      &changeupper_info.info);\n \n@@ -8972,6 +9019,7 @@ int dev_set_mac_address(struct net_devic\n \tif (err)\n \t\treturn err;\n \tdev->addr_assign_type = NET_ADDR_SET;\n+\tnetdev_update_addr_mask(dev);\n \tcall_netdevice_notifiers(NETDEV_CHANGEADDR, dev);\n \tadd_device_randomness(dev->dev_addr, dev->addr_len);\n \treturn 0;\n--- a/net/ethernet/eth.c\n+++ b/net/ethernet/eth.c\n@@ -143,6 +143,18 @@ u32 eth_get_headlen(const struct net_dev\n }\n EXPORT_SYMBOL(eth_get_headlen);\n \n+static inline bool\n+eth_check_local_mask(const void *addr1, const void *addr2, const void *mask)\n+{\n+\tconst u16 *a1 = addr1;\n+\tconst u16 *a2 = addr2;\n+\tconst u16 *m = mask;\n+\n+\treturn (((a1[0] ^ a2[0]) & ~m[0]) |\n+\t\t((a1[1] ^ a2[1]) & ~m[1]) |\n+\t\t((a1[2] ^ a2[2]) & ~m[2]));\n+}\n+\n /**\n  * eth_type_trans - determine the packet's protocol ID.\n  * @skb: received socket data\n@@ -174,6 +186,10 @@ __be16 eth_type_trans(struct sk_buff *sk\n \t\t} else {\n \t\t\tskb->pkt_type = PACKET_OTHERHOST;\n \t\t}\n+\n+\t\tif (eth_check_local_mask(eth->h_dest, dev->dev_addr,\n+\t\t\t\t\t dev->local_addr_mask))\n+\t\t\tskb->gro_skip = 1;\n \t}\n \n \t/*\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/682-of_net-add-mac-address-increment-support.patch",
    "content": "From 844c273286f328acf0dab5fbd5d864366b4904dc Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Tue, 30 Mar 2021 18:21:14 +0200\nSubject: [PATCH] of_net: add mac-address-increment support\n\nLots of embedded devices use the mac-address of other interface\nextracted from nvmem cells and increments it by one or two. Add two\nbindings to integrate this and directly use the right mac-address for\nthe interface. Some example are some routers that use the gmac\nmac-address stored in the art partition and increments it by one for the\nwifi. mac-address-increment-byte bindings is used to tell what byte of\nthe mac-address has to be increased (if not defined the last byte is\nincreased) and mac-address-increment tells how much the byte decided\nearly has to be increased.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\n---\n drivers/of/of_net.c | 43 +++++++++++++++++++++++++++++++++++++++----\n 1 file changed, 39 insertions(+), 4 deletions(-)\n\n--- a/drivers/of/of_net.c\n+++ b/drivers/of/of_net.c\n@@ -115,27 +115,62 @@ static int of_get_mac_addr_nvmem(struct\n  * this case, the real MAC is in 'local-mac-address', and 'mac-address' exists\n  * but is all zeros.\n  *\n+ * DT can tell the system to increment the mac-address after is extracted by\n+ * using:\n+ * - mac-address-increment-byte to decide what byte to increase\n+ *   (if not defined is increased the last byte)\n+ * - mac-address-increment to decide how much to increase. The value WILL\n+ *   overflow to other bytes if the increment is over 255 or the total\n+ *   increment will exceed 255 of the current byte.\n+ *   (example 00:01:02:03:04:ff + 1 == 00:01:02:03:05:00)\n+ *   (example 00:01:02:03:04:fe + 5 == 00:01:02:03:05:03)\n+ *\n  * Return: 0 on success and errno in case of error.\n */\n int of_get_mac_address(struct device_node *np, u8 *addr)\n {\n+\tu32 inc_idx, mac_inc, mac_val;\n \tint ret;\n \n+\t/* Check first if the increment byte is present and valid.\n+\t * If not set assume to increment the last byte if found.\n+\t */\n+\tif (of_property_read_u32(np, \"mac-address-increment-byte\", &inc_idx))\n+\t\tinc_idx = 5;\n+\tif (inc_idx < 3 || inc_idx > 5)\n+\t\treturn -EINVAL;\n+\n \tif (!np)\n \t\treturn -ENODEV;\n \n \tret = of_get_mac_addr(np, \"mac-address\", addr);\n \tif (!ret)\n-\t\treturn 0;\n+\t\tgoto found;\n \n \tret = of_get_mac_addr(np, \"local-mac-address\", addr);\n \tif (!ret)\n-\t\treturn 0;\n+\t\tgoto found;\n \n \tret = of_get_mac_addr(np, \"address\", addr);\n \tif (!ret)\n-\t\treturn 0;\n+\t\tgoto found;\n+\n+\tret = of_get_mac_addr_nvmem(np, addr);\n+\tif (ret)\n+\t\treturn ret;\n+\n+found:\n+\tif (!of_property_read_u32(np, \"mac-address-increment\", &mac_inc)) {\n+\t\t/* Convert to a contiguous value */\n+\t\tmac_val = (addr[3] << 16) + (addr[4] << 8) + addr[5];\n+\t\tmac_val += mac_inc << 8 * (5-inc_idx);\n+\n+\t\t/* Apply the incremented value handling overflow case */\n+\t\taddr[3] = (mac_val >> 16) & 0xff;\n+\t\taddr[4] = (mac_val >> 8) & 0xff;\n+\t\taddr[5] = (mac_val >> 0) & 0xff;\n+\t}\n \n-\treturn of_get_mac_addr_nvmem(np, addr);\n+\treturn ret;\n }\n EXPORT_SYMBOL(of_get_mac_address);\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/683-of_net-add-mac-address-to-of-tree.patch",
    "content": "--- a/drivers/of/of_net.c\n+++ b/drivers/of/of_net.c\n@@ -95,6 +95,27 @@ static int of_get_mac_addr_nvmem(struct\n \treturn 0;\n }\n \n+static int of_add_mac_address(struct device_node *np, u8* addr)\n+{\n+\tstruct property *prop;\n+\n+\tprop = kzalloc(sizeof(*prop), GFP_KERNEL);\n+\tif (!prop)\n+\t\treturn -ENOMEM;\n+\n+\tprop->name = \"mac-address\";\n+\tprop->length = ETH_ALEN;\n+\tprop->value = kmemdup(addr, ETH_ALEN, GFP_KERNEL);\n+\tif (!prop->value || of_update_property(np, prop))\n+\t\tgoto free;\n+\n+\treturn 0;\n+free:\n+\tkfree(prop->value);\n+\tkfree(prop);\n+\treturn -ENOMEM;\n+}\n+\n /**\n  * Search the device tree for the best MAC address to use.  'mac-address' is\n  * checked first, because that is supposed to contain to \"most recent\" MAC\n@@ -171,6 +192,7 @@ found:\n \t\taddr[5] = (mac_val >> 0) & 0xff;\n \t}\n \n+\tof_add_mac_address(np, addr);\n \treturn ret;\n }\n EXPORT_SYMBOL(of_get_mac_address);\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/700-net-ethernet-mtk_eth_soc-avoid-creating-duplicate-of.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nDate: Thu, 8 Jul 2021 07:08:29 +0200\nSubject: [PATCH] net: ethernet: mtk_eth_soc: avoid creating duplicate offload\n entries\n\nSometimes multiple CLS_REPLACE calls are issued for the same connection.\nrhashtable_insert_fast does not check for these duplicates, so multiple\nhardware flow entries can be created.\nFix this by checking for an existing entry early\n\nFixes: 502e84e2382d (\"net: ethernet: mtk_eth_soc: add flow offloading support\")\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n\n--- a/drivers/net/ethernet/mediatek/mtk_ppe_offload.c\n+++ b/drivers/net/ethernet/mediatek/mtk_ppe_offload.c\n@@ -187,6 +187,9 @@ mtk_flow_offload_replace(struct mtk_eth\n \tint hash;\n \tint i;\n \n+\tif (rhashtable_lookup(&eth->flow_table, &f->cookie, mtk_flow_ht_params))\n+\t\treturn -EEXIST;\n+\n \tif (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_META)) {\n \t\tstruct flow_match_meta match;\n \n"
  },
  {
    "path": "target/linux/generic/pending-5.10/701-00-net-ethernet-mtk_eth_soc-add-support-for-coherent-DM.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nDate: Sat, 5 Feb 2022 17:59:07 +0100\nSubject: [PATCH] net: ethernet: mtk_eth_soc: add support for coherent\n DMA\n\nIt improves performance by eliminating the need for a cache flush on rx and tx\nIn preparation for supporting WED (Wireless Ethernet Dispatch), also add a\nfunction for disabling coherent DMA at runtime.\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n\n--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c\n+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c\n@@ -9,6 +9,7 @@\n #include <linux/of_device.h>\n #include <linux/of_mdio.h>\n #include <linux/of_net.h>\n+#include <linux/of_address.h>\n #include <linux/mfd/syscon.h>\n #include <linux/regmap.h>\n #include <linux/clk.h>\n@@ -821,7 +822,7 @@ static int mtk_init_fq_dma(struct mtk_et\n \tdma_addr_t dma_addr;\n \tint i;\n \n-\teth->scratch_ring = dma_alloc_coherent(eth->dev,\n+\teth->scratch_ring = dma_alloc_coherent(eth->dma_dev,\n \t\t\t\t\t       cnt * sizeof(struct mtk_tx_dma),\n \t\t\t\t\t       &eth->phy_scratch_ring,\n \t\t\t\t\t       GFP_ATOMIC);\n@@ -833,10 +834,10 @@ static int mtk_init_fq_dma(struct mtk_et\n \tif (unlikely(!eth->scratch_head))\n \t\treturn -ENOMEM;\n \n-\tdma_addr = dma_map_single(eth->dev,\n+\tdma_addr = dma_map_single(eth->dma_dev,\n \t\t\t\t  eth->scratch_head, cnt * MTK_QDMA_PAGE_SIZE,\n \t\t\t\t  DMA_FROM_DEVICE);\n-\tif (unlikely(dma_mapping_error(eth->dev, dma_addr)))\n+\tif (unlikely(dma_mapping_error(eth->dma_dev, dma_addr)))\n \t\treturn -ENOMEM;\n \n \tphy_ring_tail = eth->phy_scratch_ring +\n@@ -890,26 +891,26 @@ static void mtk_tx_unmap(struct mtk_eth\n {\n \tif (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {\n \t\tif (tx_buf->flags & MTK_TX_FLAGS_SINGLE0) {\n-\t\t\tdma_unmap_single(eth->dev,\n+\t\t\tdma_unmap_single(eth->dma_dev,\n \t\t\t\t\t dma_unmap_addr(tx_buf, dma_addr0),\n \t\t\t\t\t dma_unmap_len(tx_buf, dma_len0),\n \t\t\t\t\t DMA_TO_DEVICE);\n \t\t} else if (tx_buf->flags & MTK_TX_FLAGS_PAGE0) {\n-\t\t\tdma_unmap_page(eth->dev,\n+\t\t\tdma_unmap_page(eth->dma_dev,\n \t\t\t\t       dma_unmap_addr(tx_buf, dma_addr0),\n \t\t\t\t       dma_unmap_len(tx_buf, dma_len0),\n \t\t\t\t       DMA_TO_DEVICE);\n \t\t}\n \t} else {\n \t\tif (dma_unmap_len(tx_buf, dma_len0)) {\n-\t\t\tdma_unmap_page(eth->dev,\n+\t\t\tdma_unmap_page(eth->dma_dev,\n \t\t\t\t       dma_unmap_addr(tx_buf, dma_addr0),\n \t\t\t\t       dma_unmap_len(tx_buf, dma_len0),\n \t\t\t\t       DMA_TO_DEVICE);\n \t\t}\n \n \t\tif (dma_unmap_len(tx_buf, dma_len1)) {\n-\t\t\tdma_unmap_page(eth->dev,\n+\t\t\tdma_unmap_page(eth->dma_dev,\n \t\t\t\t       dma_unmap_addr(tx_buf, dma_addr1),\n \t\t\t\t       dma_unmap_len(tx_buf, dma_len1),\n \t\t\t\t       DMA_TO_DEVICE);\n@@ -987,9 +988,9 @@ static int mtk_tx_map(struct sk_buff *sk\n \tif (skb_vlan_tag_present(skb))\n \t\ttxd4 |= TX_DMA_INS_VLAN | skb_vlan_tag_get(skb);\n \n-\tmapped_addr = dma_map_single(eth->dev, skb->data,\n+\tmapped_addr = dma_map_single(eth->dma_dev, skb->data,\n \t\t\t\t     skb_headlen(skb), DMA_TO_DEVICE);\n-\tif (unlikely(dma_mapping_error(eth->dev, mapped_addr)))\n+\tif (unlikely(dma_mapping_error(eth->dma_dev, mapped_addr)))\n \t\treturn -ENOMEM;\n \n \tWRITE_ONCE(itxd->txd1, mapped_addr);\n@@ -1028,10 +1029,10 @@ static int mtk_tx_map(struct sk_buff *sk\n \n \n \t\t\tfrag_map_size = min(frag_size, MTK_TX_DMA_BUF_LEN);\n-\t\t\tmapped_addr = skb_frag_dma_map(eth->dev, frag, offset,\n+\t\t\tmapped_addr = skb_frag_dma_map(eth->dma_dev, frag, offset,\n \t\t\t\t\t\t       frag_map_size,\n \t\t\t\t\t\t       DMA_TO_DEVICE);\n-\t\t\tif (unlikely(dma_mapping_error(eth->dev, mapped_addr)))\n+\t\t\tif (unlikely(dma_mapping_error(eth->dma_dev, mapped_addr)))\n \t\t\t\tgoto err_dma;\n \n \t\t\tif (i == nr_frags - 1 &&\n@@ -1309,18 +1310,18 @@ static int mtk_poll_rx(struct napi_struc\n \t\t\tnetdev->stats.rx_dropped++;\n \t\t\tgoto release_desc;\n \t\t}\n-\t\tdma_addr = dma_map_single(eth->dev,\n+\t\tdma_addr = dma_map_single(eth->dma_dev,\n \t\t\t\t\t  new_data + NET_SKB_PAD +\n \t\t\t\t\t  eth->ip_align,\n \t\t\t\t\t  ring->buf_size,\n \t\t\t\t\t  DMA_FROM_DEVICE);\n-\t\tif (unlikely(dma_mapping_error(eth->dev, dma_addr))) {\n+\t\tif (unlikely(dma_mapping_error(eth->dma_dev, dma_addr))) {\n \t\t\tskb_free_frag(new_data);\n \t\t\tnetdev->stats.rx_dropped++;\n \t\t\tgoto release_desc;\n \t\t}\n \n-\t\tdma_unmap_single(eth->dev, trxd.rxd1,\n+\t\tdma_unmap_single(eth->dma_dev, trxd.rxd1,\n \t\t\t\t ring->buf_size, DMA_FROM_DEVICE);\n \n \t\t/* receive data */\n@@ -1593,7 +1594,7 @@ static int mtk_tx_alloc(struct mtk_eth *\n \tif (!ring->buf)\n \t\tgoto no_tx_mem;\n \n-\tring->dma = dma_alloc_coherent(eth->dev, MTK_DMA_SIZE * sz,\n+\tring->dma = dma_alloc_coherent(eth->dma_dev, MTK_DMA_SIZE * sz,\n \t\t\t\t       &ring->phys, GFP_ATOMIC);\n \tif (!ring->dma)\n \t\tgoto no_tx_mem;\n@@ -1611,7 +1612,7 @@ static int mtk_tx_alloc(struct mtk_eth *\n \t * descriptors in ring->dma_pdma.\n \t */\n \tif (!MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {\n-\t\tring->dma_pdma = dma_alloc_coherent(eth->dev, MTK_DMA_SIZE * sz,\n+\t\tring->dma_pdma = dma_alloc_coherent(eth->dma_dev, MTK_DMA_SIZE * sz,\n \t\t\t\t\t\t    &ring->phys_pdma,\n \t\t\t\t\t\t    GFP_ATOMIC);\n \t\tif (!ring->dma_pdma)\n@@ -1670,7 +1671,7 @@ static void mtk_tx_clean(struct mtk_eth\n \t}\n \n \tif (ring->dma) {\n-\t\tdma_free_coherent(eth->dev,\n+\t\tdma_free_coherent(eth->dma_dev,\n \t\t\t\t  MTK_DMA_SIZE * sizeof(*ring->dma),\n \t\t\t\t  ring->dma,\n \t\t\t\t  ring->phys);\n@@ -1678,7 +1679,7 @@ static void mtk_tx_clean(struct mtk_eth\n \t}\n \n \tif (ring->dma_pdma) {\n-\t\tdma_free_coherent(eth->dev,\n+\t\tdma_free_coherent(eth->dma_dev,\n \t\t\t\t  MTK_DMA_SIZE * sizeof(*ring->dma_pdma),\n \t\t\t\t  ring->dma_pdma,\n \t\t\t\t  ring->phys_pdma);\n@@ -1723,18 +1724,18 @@ static int mtk_rx_alloc(struct mtk_eth *\n \t\t\treturn -ENOMEM;\n \t}\n \n-\tring->dma = dma_alloc_coherent(eth->dev,\n+\tring->dma = dma_alloc_coherent(eth->dma_dev,\n \t\t\t\t       rx_dma_size * sizeof(*ring->dma),\n \t\t\t\t       &ring->phys, GFP_ATOMIC);\n \tif (!ring->dma)\n \t\treturn -ENOMEM;\n \n \tfor (i = 0; i < rx_dma_size; i++) {\n-\t\tdma_addr_t dma_addr = dma_map_single(eth->dev,\n+\t\tdma_addr_t dma_addr = dma_map_single(eth->dma_dev,\n \t\t\t\tring->data[i] + NET_SKB_PAD + eth->ip_align,\n \t\t\t\tring->buf_size,\n \t\t\t\tDMA_FROM_DEVICE);\n-\t\tif (unlikely(dma_mapping_error(eth->dev, dma_addr)))\n+\t\tif (unlikely(dma_mapping_error(eth->dma_dev, dma_addr)))\n \t\t\treturn -ENOMEM;\n \t\tring->dma[i].rxd1 = (unsigned int)dma_addr;\n \n@@ -1770,7 +1771,7 @@ static void mtk_rx_clean(struct mtk_eth\n \t\t\t\tcontinue;\n \t\t\tif (!ring->dma[i].rxd1)\n \t\t\t\tcontinue;\n-\t\t\tdma_unmap_single(eth->dev,\n+\t\t\tdma_unmap_single(eth->dma_dev,\n \t\t\t\t\t ring->dma[i].rxd1,\n \t\t\t\t\t ring->buf_size,\n \t\t\t\t\t DMA_FROM_DEVICE);\n@@ -1781,7 +1782,7 @@ static void mtk_rx_clean(struct mtk_eth\n \t}\n \n \tif (ring->dma) {\n-\t\tdma_free_coherent(eth->dev,\n+\t\tdma_free_coherent(eth->dma_dev,\n \t\t\t\t  ring->dma_size * sizeof(*ring->dma),\n \t\t\t\t  ring->dma,\n \t\t\t\t  ring->phys);\n@@ -2134,7 +2135,7 @@ static void mtk_dma_free(struct mtk_eth\n \t\tif (eth->netdev[i])\n \t\t\tnetdev_reset_queue(eth->netdev[i]);\n \tif (eth->scratch_ring) {\n-\t\tdma_free_coherent(eth->dev,\n+\t\tdma_free_coherent(eth->dma_dev,\n \t\t\t\t  MTK_DMA_SIZE * sizeof(struct mtk_tx_dma),\n \t\t\t\t  eth->scratch_ring,\n \t\t\t\t  eth->phy_scratch_ring);\n@@ -2482,6 +2483,8 @@ static void mtk_dim_tx(struct work_struc\n \n static int mtk_hw_init(struct mtk_eth *eth)\n {\n+\tu32 dma_mask = ETHSYS_DMA_AG_MAP_PDMA | ETHSYS_DMA_AG_MAP_QDMA |\n+\t\t       ETHSYS_DMA_AG_MAP_PPE;\n \tint i, val, ret;\n \n \tif (test_and_set_bit(MTK_HW_INIT, &eth->state))\n@@ -2494,6 +2497,10 @@ static int mtk_hw_init(struct mtk_eth *e\n \tif (ret)\n \t\tgoto err_disable_pm;\n \n+\tif (eth->ethsys)\n+\t\tregmap_update_bits(eth->ethsys, ETHSYS_DMA_AG_MAP, dma_mask,\n+\t\t\t\t   of_dma_is_coherent(eth->dma_dev->of_node) * dma_mask);\n+\n \tif (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) {\n \t\tret = device_reset(eth->dev);\n \t\tif (ret) {\n@@ -3043,6 +3050,35 @@ free_netdev:\n \treturn err;\n }\n \n+void mtk_eth_set_dma_device(struct mtk_eth *eth, struct device *dma_dev)\n+{\n+\tstruct net_device *dev, *tmp;\n+\tLIST_HEAD(dev_list);\n+\tint i;\n+\n+\trtnl_lock();\n+\n+\tfor (i = 0; i < MTK_MAC_COUNT; i++) {\n+\t\tdev = eth->netdev[i];\n+\n+\t\tif (!dev || !(dev->flags & IFF_UP))\n+\t\t\tcontinue;\n+\n+\t\tlist_add_tail(&dev->close_list, &dev_list);\n+\t}\n+\n+\tdev_close_many(&dev_list, false);\n+\n+\teth->dma_dev = dma_dev;\n+\n+\tlist_for_each_entry_safe(dev, tmp, &dev_list, close_list) {\n+\t\tlist_del_init(&dev->close_list);\n+\t\tdev_open(dev, NULL);\n+\t}\n+\n+\trtnl_unlock();\n+}\n+\n static int mtk_probe(struct platform_device *pdev)\n {\n \tstruct device_node *mac_np;\n@@ -3056,6 +3092,7 @@ static int mtk_probe(struct platform_dev\n \teth->soc = of_device_get_match_data(&pdev->dev);\n \n \teth->dev = &pdev->dev;\n+\teth->dma_dev = &pdev->dev;\n \teth->base = devm_platform_ioremap_resource(pdev, 0);\n \tif (IS_ERR(eth->base))\n \t\treturn PTR_ERR(eth->base);\n@@ -3104,6 +3141,16 @@ static int mtk_probe(struct platform_dev\n \t\t}\n \t}\n \n+\tif (of_dma_is_coherent(pdev->dev.of_node)) {\n+\t\tstruct regmap *cci;\n+\n+\t\tcci = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,\n+\t\t\t\t\t\t      \"mediatek,cci-control\");\n+\t\t/* enable CPU/bus coherency */\n+\t\tif (!IS_ERR(cci))\n+\t\t\tregmap_write(cci, 0, 3);\n+\t}\n+\n \tif (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) {\n \t\teth->sgmii = devm_kzalloc(eth->dev, sizeof(*eth->sgmii),\n \t\t\t\t\t  GFP_KERNEL);\n--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h\n+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h\n@@ -456,6 +456,12 @@\n #define RSTCTRL_FE\t\tBIT(6)\n #define RSTCTRL_PPE\t\tBIT(31)\n \n+/* ethernet dma channel agent map */\n+#define ETHSYS_DMA_AG_MAP\t0x408\n+#define ETHSYS_DMA_AG_MAP_PDMA\tBIT(0)\n+#define ETHSYS_DMA_AG_MAP_QDMA\tBIT(1)\n+#define ETHSYS_DMA_AG_MAP_PPE\tBIT(2)\n+\n /* SGMII subsystem config registers */\n /* Register to auto-negotiation restart */\n #define SGMSYS_PCS_CONTROL_1\t0x0\n@@ -873,6 +879,7 @@ struct mtk_sgmii {\n /* struct mtk_eth -\tThis is the main datasructure for holding the state\n  *\t\t\tof the driver\n  * @dev:\t\tThe device pointer\n+ * @dev:\t\tThe device pointer used for dma mapping/alloc\n  * @base:\t\tThe mapped register i/o base\n  * @page_lock:\t\tMake sure that register operations are atomic\n  * @tx_irq__lock:\tMake sure that IRQ register operations are atomic\n@@ -916,6 +923,7 @@ struct mtk_sgmii {\n \n struct mtk_eth {\n \tstruct device\t\t\t*dev;\n+\tstruct device\t\t\t*dma_dev;\n \tvoid __iomem\t\t\t*base;\n \tspinlock_t\t\t\tpage_lock;\n \tspinlock_t\t\t\ttx_irq_lock;\n@@ -1014,6 +1022,7 @@ int mtk_gmac_rgmii_path_setup(struct mtk\n int mtk_eth_offload_init(struct mtk_eth *eth);\n int mtk_eth_setup_tc(struct net_device *dev, enum tc_setup_type type,\n \t\t     void *type_data);\n+void mtk_eth_set_dma_device(struct mtk_eth *eth, struct device *dma_dev);\n \n \n #endif /* MTK_ETH_H */\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/701-01-arm64-dts-mediatek-mt7622-add-support-for-coherent-D.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nDate: Mon, 7 Feb 2022 10:27:22 +0100\nSubject: [PATCH] arm64: dts: mediatek: mt7622: add support for coherent\n DMA\n\nIt improves performance by eliminating the need for a cache flush on rx and tx\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n\n--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi\n+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi\n@@ -357,7 +357,7 @@\n \t\t};\n \n \t\tcci_control2: slave-if@5000 {\n-\t\t\tcompatible = \"arm,cci-400-ctrl-if\";\n+\t\t\tcompatible = \"arm,cci-400-ctrl-if\", \"syscon\";\n \t\t\tinterface-type = \"ace\";\n \t\t\treg = <0x5000 0x1000>;\n \t\t};\n@@ -936,6 +936,8 @@\n \t\tpower-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>;\n \t\tmediatek,ethsys = <&ethsys>;\n \t\tmediatek,sgmiisys = <&sgmiisys>;\n+\t\tmediatek,cci-control = <&cci_control2>;\n+\t\tdma-coherent;\n \t\t#address-cells = <1>;\n \t\t#size-cells = <0>;\n \t\tstatus = \"disabled\";\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/701-02-net-ethernet-mtk_eth_soc-add-support-for-Wireless-Et.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nDate: Sat, 5 Feb 2022 17:56:08 +0100\nSubject: [PATCH] net: ethernet: mtk_eth_soc: add support for Wireless\n Ethernet Dispatch (WED)\n\nThe Wireless Ethernet Dispatch subsystem on the MT7622 SoC can be\nconfigured to intercept and handle access to the DMA queues and\nPCIe interrupts for a MT7615/MT7915 wireless card.\nIt can manage the internal WDMA (Wireless DMA) controller, which allows\nethernet packets to be passed from the packet switch engine (PSE) to the\nwireless card, bypassing the CPU entirely.\nThis can be used to implement hardware flow offloading from ethernet to\nWLAN.\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n create mode 100644 drivers/net/ethernet/mediatek/mtk_wed.c\n create mode 100644 drivers/net/ethernet/mediatek/mtk_wed.h\n create mode 100644 drivers/net/ethernet/mediatek/mtk_wed_debugfs.c\n create mode 100644 drivers/net/ethernet/mediatek/mtk_wed_ops.c\n create mode 100644 drivers/net/ethernet/mediatek/mtk_wed_regs.h\n create mode 100644 include/linux/soc/mediatek/mtk_wed.h\n\n--- a/drivers/net/ethernet/mediatek/Kconfig\n+++ b/drivers/net/ethernet/mediatek/Kconfig\n@@ -7,6 +7,10 @@ config NET_VENDOR_MEDIATEK\n \n if NET_VENDOR_MEDIATEK\n \n+config NET_MEDIATEK_SOC_WED\n+\tdepends on ARCH_MEDIATEK || COMPILE_TEST\n+\tdef_bool NET_MEDIATEK_SOC != n\n+\n config NET_MEDIATEK_SOC\n \ttristate \"MediaTek SoC Gigabit Ethernet support\"\n \tselect PHYLINK\n--- a/drivers/net/ethernet/mediatek/Makefile\n+++ b/drivers/net/ethernet/mediatek/Makefile\n@@ -5,4 +5,9 @@\n \n obj-$(CONFIG_NET_MEDIATEK_SOC) += mtk_eth.o\n mtk_eth-y := mtk_eth_soc.o mtk_sgmii.o mtk_eth_path.o mtk_ppe.o mtk_ppe_debugfs.o mtk_ppe_offload.o\n+mtk_eth-$(CONFIG_NET_MEDIATEK_SOC_WED) += mtk_wed.o\n+ifdef CONFIG_DEBUG_FS\n+mtk_eth-$(CONFIG_NET_MEDIATEK_SOC_WED) += mtk_wed_debugfs.o\n+endif\n+obj-$(CONFIG_NET_MEDIATEK_SOC_WED) += mtk_wed_ops.o\n obj-$(CONFIG_NET_MEDIATEK_STAR_EMAC) += mtk_star_emac.o\n--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c\n+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c\n@@ -24,6 +24,7 @@\n #include <net/dsa.h>\n \n #include \"mtk_eth_soc.h\"\n+#include \"mtk_wed.h\"\n \n static int mtk_msg_level = -1;\n module_param_named(msg_level, mtk_msg_level, int, 0);\n@@ -3173,6 +3174,22 @@ static int mtk_probe(struct platform_dev\n \t\t}\n \t}\n \n+\tfor (i = 0;; i++) {\n+\t\tstruct device_node *np = of_parse_phandle(pdev->dev.of_node,\n+\t\t\t\t\t\t\t  \"mediatek,wed\", i);\n+\t\tstatic const u32 wdma_regs[] = {\n+\t\t\tMTK_WDMA0_BASE,\n+\t\t\tMTK_WDMA1_BASE\n+\t\t};\n+\t\tvoid __iomem *wdma;\n+\n+\t\tif (!np || i >= ARRAY_SIZE(wdma_regs))\n+\t\t\tbreak;\n+\n+\t\twdma = eth->base + wdma_regs[i];\n+\t\tmtk_wed_add_hw(np, eth, wdma, i);\n+\t}\n+\n \tfor (i = 0; i < 3; i++) {\n \t\tif (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT) && i > 0)\n \t\t\teth->irq[i] = eth->irq[0];\n--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h\n+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h\n@@ -295,6 +295,9 @@\n #define MTK_GDM1_TX_GPCNT\t0x2438\n #define MTK_STAT_OFFSET\t\t0x40\n \n+#define MTK_WDMA0_BASE\t\t0x2800\n+#define MTK_WDMA1_BASE\t\t0x2c00\n+\n /* QDMA descriptor txd4 */\n #define TX_DMA_CHKSUM\t\t(0x7 << 29)\n #define TX_DMA_TSO\t\tBIT(28)\n--- /dev/null\n+++ b/drivers/net/ethernet/mediatek/mtk_wed.c\n@@ -0,0 +1,875 @@\n+// SPDX-License-Identifier: GPL-2.0-only\n+/* Copyright (C) 2021 Felix Fietkau <nbd@nbd.name> */\n+\n+#include <linux/kernel.h>\n+#include <linux/slab.h>\n+#include <linux/module.h>\n+#include <linux/bitfield.h>\n+#include <linux/dma-mapping.h>\n+#include <linux/skbuff.h>\n+#include <linux/of_platform.h>\n+#include <linux/of_address.h>\n+#include <linux/mfd/syscon.h>\n+#include <linux/debugfs.h>\n+#include <linux/soc/mediatek/mtk_wed.h>\n+#include \"mtk_eth_soc.h\"\n+#include \"mtk_wed_regs.h\"\n+#include \"mtk_wed.h\"\n+#include \"mtk_ppe.h\"\n+\n+#define MTK_PCIE_BASE(n)\t\t(0x1a143000 + (n) * 0x2000)\n+\n+#define MTK_WED_PKT_SIZE\t\t1900\n+#define MTK_WED_BUF_SIZE\t\t2048\n+#define MTK_WED_BUF_PER_PAGE\t\t(PAGE_SIZE / 2048)\n+\n+#define MTK_WED_TX_RING_SIZE\t\t2048\n+#define MTK_WED_WDMA_RING_SIZE\t\t1024\n+\n+static struct mtk_wed_hw *hw_list[2];\n+static DEFINE_MUTEX(hw_lock);\n+\n+static void\n+wed_m32(struct mtk_wed_device *dev, u32 reg, u32 mask, u32 val)\n+{\n+\tregmap_update_bits(dev->hw->regs, reg, mask | val, val);\n+}\n+\n+static void\n+wed_set(struct mtk_wed_device *dev, u32 reg, u32 mask)\n+{\n+\treturn wed_m32(dev, reg, 0, mask);\n+}\n+\n+static void\n+wed_clr(struct mtk_wed_device *dev, u32 reg, u32 mask)\n+{\n+\treturn wed_m32(dev, reg, mask, 0);\n+}\n+\n+static void\n+wdma_m32(struct mtk_wed_device *dev, u32 reg, u32 mask, u32 val)\n+{\n+\twdma_w32(dev, reg, (wdma_r32(dev, reg) & ~mask) | val);\n+}\n+\n+static void\n+wdma_set(struct mtk_wed_device *dev, u32 reg, u32 mask)\n+{\n+\twdma_m32(dev, reg, 0, mask);\n+}\n+\n+static u32\n+mtk_wed_read_reset(struct mtk_wed_device *dev)\n+{\n+\treturn wed_r32(dev, MTK_WED_RESET);\n+}\n+\n+static void\n+mtk_wed_reset(struct mtk_wed_device *dev, u32 mask)\n+{\n+\tu32 status;\n+\n+\twed_w32(dev, MTK_WED_RESET, mask);\n+\tif (readx_poll_timeout(mtk_wed_read_reset, dev, status,\n+\t\t\t       !(status & mask), 0, 1000))\n+\t\tWARN_ON_ONCE(1);\n+}\n+\n+static struct mtk_wed_hw *\n+mtk_wed_assign(struct mtk_wed_device *dev)\n+{\n+\tstruct mtk_wed_hw *hw;\n+\n+\thw = hw_list[pci_domain_nr(dev->wlan.pci_dev->bus)];\n+\tif (!hw || hw->wed_dev)\n+\t\treturn NULL;\n+\n+\thw->wed_dev = dev;\n+\treturn hw;\n+}\n+\n+static int\n+mtk_wed_buffer_alloc(struct mtk_wed_device *dev)\n+{\n+\tstruct mtk_wdma_desc *desc;\n+\tdma_addr_t desc_phys;\n+\tvoid **page_list;\n+\tint token = dev->wlan.token_start;\n+\tint ring_size;\n+\tint n_pages;\n+\tint i, page_idx;\n+\n+\tring_size = dev->wlan.nbuf & ~(MTK_WED_BUF_PER_PAGE - 1);\n+\tn_pages = ring_size / MTK_WED_BUF_PER_PAGE;\n+\n+\tpage_list = kcalloc(n_pages, sizeof(*page_list), GFP_KERNEL);\n+\tif (!page_list)\n+\t\treturn -ENOMEM;\n+\n+\tdev->buf_ring.size = ring_size;\n+\tdev->buf_ring.pages = page_list;\n+\n+\tdesc = dma_alloc_coherent(dev->hw->dev, ring_size * sizeof(*desc),\n+\t\t\t\t  &desc_phys, GFP_KERNEL);\n+\tif (!desc)\n+\t\treturn -ENOMEM;\n+\n+\tdev->buf_ring.desc = desc;\n+\tdev->buf_ring.desc_phys = desc_phys;\n+\n+\tfor (i = 0, page_idx = 0; i < ring_size; i += MTK_WED_BUF_PER_PAGE) {\n+\t\tdma_addr_t page_phys, buf_phys;\n+\t\tstruct page *page;\n+\t\tvoid *buf;\n+\t\tint s;\n+\n+\t\tpage = __dev_alloc_pages(GFP_KERNEL, 0);\n+\t\tif (!page)\n+\t\t\treturn -ENOMEM;\n+\n+\t\tpage_phys = dma_map_page(dev->hw->dev, page, 0, PAGE_SIZE,\n+\t\t\t\t\t DMA_BIDIRECTIONAL);\n+\t\tif (dma_mapping_error(dev->hw->dev, page_phys)) {\n+\t\t\t__free_page(page);\n+\t\t\treturn -ENOMEM;\n+\t\t}\n+\n+\t\tpage_list[page_idx++] = page;\n+\t\tdma_sync_single_for_cpu(dev->hw->dev, page_phys, PAGE_SIZE,\n+\t\t\t\t\tDMA_BIDIRECTIONAL);\n+\n+\t\tbuf = page_to_virt(page);\n+\t\tbuf_phys = page_phys;\n+\n+\t\tfor (s = 0; s < MTK_WED_BUF_PER_PAGE; s++) {\n+\t\t\tu32 txd_size;\n+\n+\t\t\ttxd_size = dev->wlan.init_buf(buf, buf_phys, token++);\n+\n+\t\t\tdesc->buf0 = buf_phys;\n+\t\t\tdesc->buf1 = buf_phys + txd_size;\n+\t\t\tdesc->ctrl = FIELD_PREP(MTK_WDMA_DESC_CTRL_LEN0,\n+\t\t\t\t\t\ttxd_size) |\n+\t\t\t\t     FIELD_PREP(MTK_WDMA_DESC_CTRL_LEN1,\n+\t\t\t\t\t\tMTK_WED_BUF_SIZE - txd_size) |\n+\t\t\t\t     MTK_WDMA_DESC_CTRL_LAST_SEG1;\n+\t\t\tdesc->info = 0;\n+\t\t\tdesc++;\n+\n+\t\t\tbuf += MTK_WED_BUF_SIZE;\n+\t\t\tbuf_phys += MTK_WED_BUF_SIZE;\n+\t\t}\n+\n+\t\tdma_sync_single_for_device(dev->hw->dev, page_phys, PAGE_SIZE,\n+\t\t\t\t\t   DMA_BIDIRECTIONAL);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static void\n+mtk_wed_free_buffer(struct mtk_wed_device *dev)\n+{\n+\tstruct mtk_wdma_desc *desc = dev->buf_ring.desc;\n+\tvoid **page_list = dev->buf_ring.pages;\n+\tint page_idx;\n+\tint i;\n+\n+\tif (!page_list)\n+\t\treturn;\n+\n+\tif (!desc)\n+\t\tgoto free_pagelist;\n+\n+\tfor (i = 0, page_idx = 0; i < dev->buf_ring.size; i += MTK_WED_BUF_PER_PAGE) {\n+\t\tvoid *page = page_list[page_idx++];\n+\n+\t\tif (!page)\n+\t\t\tbreak;\n+\n+\t\tdma_unmap_page(dev->hw->dev, desc[i].buf0,\n+\t\t\t       PAGE_SIZE, DMA_BIDIRECTIONAL);\n+\t\t__free_page(page);\n+\t}\n+\n+\tdma_free_coherent(dev->hw->dev, dev->buf_ring.size * sizeof(*desc),\n+\t\t\t  desc, dev->buf_ring.desc_phys);\n+\n+free_pagelist:\n+\tkfree(page_list);\n+}\n+\n+static void\n+mtk_wed_free_ring(struct mtk_wed_device *dev, struct mtk_wed_ring *ring)\n+{\n+\tif (!ring->desc)\n+\t\treturn;\n+\n+\tdma_free_coherent(dev->hw->dev, ring->size * sizeof(*ring->desc),\n+\t\t\t  ring->desc, ring->desc_phys);\n+}\n+\n+static void\n+mtk_wed_free_tx_rings(struct mtk_wed_device *dev)\n+{\n+\tint i;\n+\n+\tfor (i = 0; i < ARRAY_SIZE(dev->tx_ring); i++)\n+\t\tmtk_wed_free_ring(dev, &dev->tx_ring[i]);\n+\tfor (i = 0; i < ARRAY_SIZE(dev->tx_wdma); i++)\n+\t\tmtk_wed_free_ring(dev, &dev->tx_wdma[i]);\n+}\n+\n+static void\n+mtk_wed_set_ext_int(struct mtk_wed_device *dev, bool en)\n+{\n+\tu32 mask = MTK_WED_EXT_INT_STATUS_ERROR_MASK;\n+\n+\tif (!dev->hw->num_flows)\n+\t\tmask &= ~MTK_WED_EXT_INT_STATUS_TKID_WO_PYLD;\n+\n+\twed_w32(dev, MTK_WED_EXT_INT_MASK, en ? mask : 0);\n+\twed_r32(dev, MTK_WED_EXT_INT_MASK);\n+}\n+\n+static void\n+mtk_wed_stop(struct mtk_wed_device *dev)\n+{\n+\tregmap_write(dev->hw->mirror, dev->hw->index * 4, 0);\n+\tmtk_wed_set_ext_int(dev, false);\n+\n+\twed_clr(dev, MTK_WED_CTRL,\n+\t\tMTK_WED_CTRL_WDMA_INT_AGENT_EN |\n+\t\tMTK_WED_CTRL_WPDMA_INT_AGENT_EN |\n+\t\tMTK_WED_CTRL_WED_TX_BM_EN |\n+\t\tMTK_WED_CTRL_WED_TX_FREE_AGENT_EN);\n+\twed_w32(dev, MTK_WED_WPDMA_INT_TRIGGER, 0);\n+\twed_w32(dev, MTK_WED_WDMA_INT_TRIGGER, 0);\n+\twdma_w32(dev, MTK_WDMA_INT_MASK, 0);\n+\twdma_w32(dev, MTK_WDMA_INT_GRP2, 0);\n+\twed_w32(dev, MTK_WED_WPDMA_INT_MASK, 0);\n+\n+\twed_clr(dev, MTK_WED_GLO_CFG,\n+\t\tMTK_WED_GLO_CFG_TX_DMA_EN |\n+\t\tMTK_WED_GLO_CFG_RX_DMA_EN);\n+\twed_clr(dev, MTK_WED_WPDMA_GLO_CFG,\n+\t\tMTK_WED_WPDMA_GLO_CFG_TX_DRV_EN |\n+\t\tMTK_WED_WPDMA_GLO_CFG_RX_DRV_EN);\n+\twed_clr(dev, MTK_WED_WDMA_GLO_CFG,\n+\t\tMTK_WED_WDMA_GLO_CFG_RX_DRV_EN);\n+}\n+\n+static void\n+mtk_wed_detach(struct mtk_wed_device *dev)\n+{\n+\tstruct device_node *wlan_node = dev->wlan.pci_dev->dev.of_node;\n+\tstruct mtk_wed_hw *hw = dev->hw;\n+\n+\tmutex_lock(&hw_lock);\n+\n+\tmtk_wed_stop(dev);\n+\n+\twdma_w32(dev, MTK_WDMA_RESET_IDX, MTK_WDMA_RESET_IDX_RX);\n+\twdma_w32(dev, MTK_WDMA_RESET_IDX, 0);\n+\n+\tmtk_wed_reset(dev, MTK_WED_RESET_WED);\n+\n+\tmtk_wed_free_buffer(dev);\n+\tmtk_wed_free_tx_rings(dev);\n+\n+\tif (of_dma_is_coherent(wlan_node))\n+\t\tregmap_update_bits(hw->hifsys, HIFSYS_DMA_AG_MAP,\n+\t\t\t\t   BIT(hw->index), BIT(hw->index));\n+\n+\tif (!hw_list[!hw->index]->wed_dev &&\n+\t    hw->eth->dma_dev != hw->eth->dev)\n+\t\tmtk_eth_set_dma_device(hw->eth, hw->eth->dev);\n+\n+\tmemset(dev, 0, sizeof(*dev));\n+\tmodule_put(THIS_MODULE);\n+\n+\thw->wed_dev = NULL;\n+\tmutex_unlock(&hw_lock);\n+}\n+\n+static void\n+mtk_wed_hw_init_early(struct mtk_wed_device *dev)\n+{\n+\tu32 mask, set;\n+\tu32 offset;\n+\n+\tmtk_wed_stop(dev);\n+\tmtk_wed_reset(dev, MTK_WED_RESET_WED);\n+\n+\tmask = MTK_WED_WDMA_GLO_CFG_BT_SIZE |\n+\t       MTK_WED_WDMA_GLO_CFG_DYNAMIC_DMAD_RECYCLE |\n+\t       MTK_WED_WDMA_GLO_CFG_RX_DIS_FSM_AUTO_IDLE;\n+\tset = FIELD_PREP(MTK_WED_WDMA_GLO_CFG_BT_SIZE, 2) |\n+\t      MTK_WED_WDMA_GLO_CFG_DYNAMIC_SKIP_DMAD_PREP |\n+\t      MTK_WED_WDMA_GLO_CFG_IDLE_DMAD_SUPPLY;\n+\twed_m32(dev, MTK_WED_WDMA_GLO_CFG, mask, set);\n+\n+\twdma_set(dev, MTK_WDMA_GLO_CFG, MTK_WDMA_GLO_CFG_RX_INFO_PRERES);\n+\n+\toffset = dev->hw->index ? 0x04000400 : 0;\n+\twed_w32(dev, MTK_WED_WDMA_OFFSET0, 0x2a042a20 + offset);\n+\twed_w32(dev, MTK_WED_WDMA_OFFSET1, 0x29002800 + offset);\n+\n+\twed_w32(dev, MTK_WED_PCIE_CFG_BASE, MTK_PCIE_BASE(dev->hw->index));\n+\twed_w32(dev, MTK_WED_WPDMA_CFG_BASE, dev->wlan.wpdma_phys);\n+}\n+\n+static void\n+mtk_wed_hw_init(struct mtk_wed_device *dev)\n+{\n+\tif (dev->init_done)\n+\t\treturn;\n+\n+\tdev->init_done = true;\n+\tmtk_wed_set_ext_int(dev, false);\n+\twed_w32(dev, MTK_WED_TX_BM_CTRL,\n+\t\tMTK_WED_TX_BM_CTRL_PAUSE |\n+\t\tFIELD_PREP(MTK_WED_TX_BM_CTRL_VLD_GRP_NUM,\n+\t\t\t   dev->buf_ring.size / 128) |\n+\t\tFIELD_PREP(MTK_WED_TX_BM_CTRL_RSV_GRP_NUM,\n+\t\t\t   MTK_WED_TX_RING_SIZE / 256));\n+\n+\twed_w32(dev, MTK_WED_TX_BM_BASE, dev->buf_ring.desc_phys);\n+\n+\twed_w32(dev, MTK_WED_TX_BM_TKID,\n+\t\tFIELD_PREP(MTK_WED_TX_BM_TKID_START,\n+\t\t\t   dev->wlan.token_start) |\n+\t\tFIELD_PREP(MTK_WED_TX_BM_TKID_END,\n+\t\t\t   dev->wlan.token_start + dev->wlan.nbuf - 1));\n+\n+\twed_w32(dev, MTK_WED_TX_BM_BUF_LEN, MTK_WED_PKT_SIZE);\n+\n+\twed_w32(dev, MTK_WED_TX_BM_DYN_THR,\n+\t\tFIELD_PREP(MTK_WED_TX_BM_DYN_THR_LO, 1) |\n+\t\tMTK_WED_TX_BM_DYN_THR_HI);\n+\n+\tmtk_wed_reset(dev, MTK_WED_RESET_TX_BM);\n+\n+\twed_set(dev, MTK_WED_CTRL,\n+\t\tMTK_WED_CTRL_WED_TX_BM_EN |\n+\t\tMTK_WED_CTRL_WED_TX_FREE_AGENT_EN);\n+\n+\twed_clr(dev, MTK_WED_TX_BM_CTRL, MTK_WED_TX_BM_CTRL_PAUSE);\n+}\n+\n+static void\n+mtk_wed_ring_reset(struct mtk_wdma_desc *desc, int size)\n+{\n+\tint i;\n+\n+\tfor (i = 0; i < size; i++) {\n+\t\tdesc[i].buf0 = 0;\n+\t\tdesc[i].ctrl = cpu_to_le32(MTK_WDMA_DESC_CTRL_DMA_DONE);\n+\t\tdesc[i].buf1 = 0;\n+\t\tdesc[i].info = 0;\n+\t}\n+}\n+\n+static u32\n+mtk_wed_check_busy(struct mtk_wed_device *dev)\n+{\n+\tif (wed_r32(dev, MTK_WED_GLO_CFG) & MTK_WED_GLO_CFG_TX_DMA_BUSY)\n+\t\treturn true;\n+\n+\tif (wed_r32(dev, MTK_WED_WPDMA_GLO_CFG) &\n+\t    MTK_WED_WPDMA_GLO_CFG_TX_DRV_BUSY)\n+\t\treturn true;\n+\n+\tif (wed_r32(dev, MTK_WED_CTRL) & MTK_WED_CTRL_WDMA_INT_AGENT_BUSY)\n+\t\treturn true;\n+\n+\tif (wed_r32(dev, MTK_WED_WDMA_GLO_CFG) &\n+\t    MTK_WED_WDMA_GLO_CFG_RX_DRV_BUSY)\n+\t\treturn true;\n+\n+\tif (wdma_r32(dev, MTK_WDMA_GLO_CFG) &\n+\t    MTK_WED_WDMA_GLO_CFG_RX_DRV_BUSY)\n+\t\treturn true;\n+\n+\tif (wed_r32(dev, MTK_WED_CTRL) &\n+\t    (MTK_WED_CTRL_WED_TX_BM_BUSY | MTK_WED_CTRL_WED_TX_FREE_AGENT_BUSY))\n+\t\treturn true;\n+\n+\treturn false;\n+}\n+\n+static int\n+mtk_wed_poll_busy(struct mtk_wed_device *dev)\n+{\n+\tint sleep = 15000;\n+\tint timeout = 100 * sleep;\n+\tu32 val;\n+\n+\treturn read_poll_timeout(mtk_wed_check_busy, val, !val, sleep,\n+\t\t\t\t timeout, false, dev);\n+}\n+\n+static void\n+mtk_wed_reset_dma(struct mtk_wed_device *dev)\n+{\n+\tbool busy = false;\n+\tu32 val;\n+\tint i;\n+\n+\tfor (i = 0; i < ARRAY_SIZE(dev->tx_ring); i++) {\n+\t\tstruct mtk_wdma_desc *desc = dev->tx_ring[i].desc;\n+\n+\t\tif (!desc)\n+\t\t\tcontinue;\n+\n+\t\tmtk_wed_ring_reset(desc, MTK_WED_TX_RING_SIZE);\n+\t}\n+\n+\tif (mtk_wed_poll_busy(dev))\n+\t\tbusy = mtk_wed_check_busy(dev);\n+\n+\tif (busy) {\n+\t\tmtk_wed_reset(dev, MTK_WED_RESET_WED_TX_DMA);\n+\t} else {\n+\t\twed_w32(dev, MTK_WED_RESET_IDX,\n+\t\t\tMTK_WED_RESET_IDX_TX |\n+\t\t\tMTK_WED_RESET_IDX_RX);\n+\t\twed_w32(dev, MTK_WED_RESET_IDX, 0);\n+\t}\n+\n+\twdma_w32(dev, MTK_WDMA_RESET_IDX, MTK_WDMA_RESET_IDX_RX);\n+\twdma_w32(dev, MTK_WDMA_RESET_IDX, 0);\n+\n+\tif (busy) {\n+\t\tmtk_wed_reset(dev, MTK_WED_RESET_WDMA_INT_AGENT);\n+\t\tmtk_wed_reset(dev, MTK_WED_RESET_WDMA_RX_DRV);\n+\t} else {\n+\t\twed_w32(dev, MTK_WED_WDMA_RESET_IDX,\n+\t\t\tMTK_WED_WDMA_RESET_IDX_RX | MTK_WED_WDMA_RESET_IDX_DRV);\n+\t\twed_w32(dev, MTK_WED_WDMA_RESET_IDX, 0);\n+\n+\t\twed_set(dev, MTK_WED_WDMA_GLO_CFG,\n+\t\t\tMTK_WED_WDMA_GLO_CFG_RST_INIT_COMPLETE);\n+\n+\t\twed_clr(dev, MTK_WED_WDMA_GLO_CFG,\n+\t\t\tMTK_WED_WDMA_GLO_CFG_RST_INIT_COMPLETE);\n+\t}\n+\n+\tfor (i = 0; i < 100; i++) {\n+\t\tval = wed_r32(dev, MTK_WED_TX_BM_INTF);\n+\t\tif (FIELD_GET(MTK_WED_TX_BM_INTF_TKFIFO_FDEP, val) == 0x40)\n+\t\t\tbreak;\n+\t}\n+\n+\tmtk_wed_reset(dev, MTK_WED_RESET_TX_FREE_AGENT);\n+\tmtk_wed_reset(dev, MTK_WED_RESET_TX_BM);\n+\n+\tif (busy) {\n+\t\tmtk_wed_reset(dev, MTK_WED_RESET_WPDMA_INT_AGENT);\n+\t\tmtk_wed_reset(dev, MTK_WED_RESET_WPDMA_TX_DRV);\n+\t\tmtk_wed_reset(dev, MTK_WED_RESET_WPDMA_RX_DRV);\n+\t} else {\n+\t\twed_w32(dev, MTK_WED_WPDMA_RESET_IDX,\n+\t\t\tMTK_WED_WPDMA_RESET_IDX_TX |\n+\t\t\tMTK_WED_WPDMA_RESET_IDX_RX);\n+\t\twed_w32(dev, MTK_WED_WPDMA_RESET_IDX, 0);\n+\t}\n+\n+}\n+\n+static int\n+mtk_wed_ring_alloc(struct mtk_wed_device *dev, struct mtk_wed_ring *ring,\n+\t\t   int size)\n+{\n+\tring->desc = dma_alloc_coherent(dev->hw->dev,\n+\t\t\t\t\tsize * sizeof(*ring->desc),\n+\t\t\t\t\t&ring->desc_phys, GFP_KERNEL);\n+\tif (!ring->desc)\n+\t\treturn -ENOMEM;\n+\n+\tring->size = size;\n+\tmtk_wed_ring_reset(ring->desc, size);\n+\n+\treturn 0;\n+}\n+\n+static int\n+mtk_wed_wdma_ring_setup(struct mtk_wed_device *dev, int idx, int size)\n+{\n+\tstruct mtk_wed_ring *wdma = &dev->tx_wdma[idx];\n+\n+\tif (mtk_wed_ring_alloc(dev, wdma, MTK_WED_WDMA_RING_SIZE))\n+\t\treturn -ENOMEM;\n+\n+\twdma_w32(dev, MTK_WDMA_RING_RX(idx) + MTK_WED_RING_OFS_BASE,\n+\t\t wdma->desc_phys);\n+\twdma_w32(dev, MTK_WDMA_RING_RX(idx) + MTK_WED_RING_OFS_COUNT,\n+\t\t size);\n+\twdma_w32(dev, MTK_WDMA_RING_RX(idx) + MTK_WED_RING_OFS_CPU_IDX, 0);\n+\n+\twed_w32(dev, MTK_WED_WDMA_RING_RX(idx) + MTK_WED_RING_OFS_BASE,\n+\t\twdma->desc_phys);\n+\twed_w32(dev, MTK_WED_WDMA_RING_RX(idx) + MTK_WED_RING_OFS_COUNT,\n+\t\tsize);\n+\n+\treturn 0;\n+}\n+\n+static void\n+mtk_wed_start(struct mtk_wed_device *dev, u32 irq_mask)\n+{\n+\tu32 wdma_mask;\n+\tu32 val;\n+\tint i;\n+\n+\tfor (i = 0; i < ARRAY_SIZE(dev->tx_wdma); i++)\n+\t\tif (!dev->tx_wdma[i].desc)\n+\t\t\tmtk_wed_wdma_ring_setup(dev, i, 16);\n+\n+\twdma_mask = FIELD_PREP(MTK_WDMA_INT_MASK_RX_DONE, GENMASK(1, 0));\n+\n+\tmtk_wed_hw_init(dev);\n+\n+\twed_set(dev, MTK_WED_CTRL,\n+\t\tMTK_WED_CTRL_WDMA_INT_AGENT_EN |\n+\t\tMTK_WED_CTRL_WPDMA_INT_AGENT_EN |\n+\t\tMTK_WED_CTRL_WED_TX_BM_EN |\n+\t\tMTK_WED_CTRL_WED_TX_FREE_AGENT_EN);\n+\n+\twed_w32(dev, MTK_WED_PCIE_INT_TRIGGER, MTK_WED_PCIE_INT_TRIGGER_STATUS);\n+\n+\twed_w32(dev, MTK_WED_WPDMA_INT_TRIGGER,\n+\t\tMTK_WED_WPDMA_INT_TRIGGER_RX_DONE |\n+\t\tMTK_WED_WPDMA_INT_TRIGGER_TX_DONE);\n+\n+\twed_set(dev, MTK_WED_WPDMA_INT_CTRL,\n+\t\tMTK_WED_WPDMA_INT_CTRL_SUBRT_ADV);\n+\n+\twed_w32(dev, MTK_WED_WDMA_INT_TRIGGER, wdma_mask);\n+\twed_clr(dev, MTK_WED_WDMA_INT_CTRL, wdma_mask);\n+\n+\twdma_w32(dev, MTK_WDMA_INT_MASK, wdma_mask);\n+\twdma_w32(dev, MTK_WDMA_INT_GRP2, wdma_mask);\n+\n+\twed_w32(dev, MTK_WED_WPDMA_INT_MASK, irq_mask);\n+\twed_w32(dev, MTK_WED_INT_MASK, irq_mask);\n+\n+\twed_set(dev, MTK_WED_GLO_CFG,\n+\t\tMTK_WED_GLO_CFG_TX_DMA_EN |\n+\t\tMTK_WED_GLO_CFG_RX_DMA_EN);\n+\twed_set(dev, MTK_WED_WPDMA_GLO_CFG,\n+\t\tMTK_WED_WPDMA_GLO_CFG_TX_DRV_EN |\n+\t\tMTK_WED_WPDMA_GLO_CFG_RX_DRV_EN);\n+\twed_set(dev, MTK_WED_WDMA_GLO_CFG,\n+\t\tMTK_WED_WDMA_GLO_CFG_RX_DRV_EN);\n+\n+\tmtk_wed_set_ext_int(dev, true);\n+\tval = dev->wlan.wpdma_phys |\n+\t      MTK_PCIE_MIRROR_MAP_EN |\n+\t      FIELD_PREP(MTK_PCIE_MIRROR_MAP_WED_ID, dev->hw->index);\n+\n+\tif (dev->hw->index)\n+\t\tval |= BIT(1);\n+\tval |= BIT(0);\n+\tregmap_write(dev->hw->mirror, dev->hw->index * 4, val);\n+\n+\tdev->running = true;\n+}\n+\n+static int\n+mtk_wed_attach(struct mtk_wed_device *dev)\n+\t__releases(RCU)\n+{\n+\tstruct mtk_wed_hw *hw;\n+\tint ret = 0;\n+\n+\tRCU_LOCKDEP_WARN(!rcu_read_lock_held(),\n+\t\t\t \"mtk_wed_attach without holding the RCU read lock\");\n+\n+\tif (pci_domain_nr(dev->wlan.pci_dev->bus) > 1 ||\n+\t    !try_module_get(THIS_MODULE))\n+\t\tret = -ENODEV;\n+\n+\trcu_read_unlock();\n+\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tmutex_lock(&hw_lock);\n+\n+\thw = mtk_wed_assign(dev);\n+\tif (!hw) {\n+\t\tmodule_put(THIS_MODULE);\n+\t\tret = -ENODEV;\n+\t\tgoto out;\n+\t}\n+\n+\tdev_info(&dev->wlan.pci_dev->dev, \"attaching wed device %d\\n\", hw->index);\n+\n+\tdev->hw = hw;\n+\tdev->dev = hw->dev;\n+\tdev->irq = hw->irq;\n+\tdev->wdma_idx = hw->index;\n+\n+\tif (hw->eth->dma_dev == hw->eth->dev &&\n+\t    of_dma_is_coherent(hw->eth->dev->of_node))\n+\t\tmtk_eth_set_dma_device(hw->eth, hw->dev);\n+\n+\tret = mtk_wed_buffer_alloc(dev);\n+\tif (ret) {\n+\t\tmtk_wed_detach(dev);\n+\t\tgoto out;\n+\t}\n+\n+\tmtk_wed_hw_init_early(dev);\n+\tregmap_update_bits(hw->hifsys, HIFSYS_DMA_AG_MAP, BIT(hw->index), 0);\n+\n+out:\n+\tmutex_unlock(&hw_lock);\n+\n+\treturn ret;\n+}\n+\n+static int\n+mtk_wed_tx_ring_setup(struct mtk_wed_device *dev, int idx, void __iomem *regs)\n+{\n+\tstruct mtk_wed_ring *ring = &dev->tx_ring[idx];\n+\n+\t/*\n+\t * Tx ring redirection:\n+\t * Instead of configuring the WLAN PDMA TX ring directly, the WLAN\n+\t * driver allocated DMA ring gets configured into WED MTK_WED_RING_TX(n)\n+\t * registers.\n+\t *\n+\t * WED driver posts its own DMA ring as WLAN PDMA TX and configures it\n+\t * into MTK_WED_WPDMA_RING_TX(n) registers.\n+\t * It gets filled with packets picked up from WED TX ring and from\n+\t * WDMA RX.\n+\t */\n+\n+\tBUG_ON(idx > ARRAY_SIZE(dev->tx_ring));\n+\n+\tif (mtk_wed_ring_alloc(dev, ring, MTK_WED_TX_RING_SIZE))\n+\t\treturn -ENOMEM;\n+\n+\tif (mtk_wed_wdma_ring_setup(dev, idx, MTK_WED_WDMA_RING_SIZE))\n+\t\treturn -ENOMEM;\n+\n+\tring->reg_base = MTK_WED_RING_TX(idx);\n+\tring->wpdma = regs;\n+\n+\t/* WED -> WPDMA */\n+\twpdma_tx_w32(dev, idx, MTK_WED_RING_OFS_BASE, ring->desc_phys);\n+\twpdma_tx_w32(dev, idx, MTK_WED_RING_OFS_COUNT, MTK_WED_TX_RING_SIZE);\n+\twpdma_tx_w32(dev, idx, MTK_WED_RING_OFS_CPU_IDX, 0);\n+\n+\twed_w32(dev, MTK_WED_WPDMA_RING_TX(idx) + MTK_WED_RING_OFS_BASE,\n+\t\tring->desc_phys);\n+\twed_w32(dev, MTK_WED_WPDMA_RING_TX(idx) + MTK_WED_RING_OFS_COUNT,\n+\t\tMTK_WED_TX_RING_SIZE);\n+\twed_w32(dev, MTK_WED_WPDMA_RING_TX(idx) + MTK_WED_RING_OFS_CPU_IDX, 0);\n+\n+\treturn 0;\n+}\n+\n+static int\n+mtk_wed_txfree_ring_setup(struct mtk_wed_device *dev, void __iomem *regs)\n+{\n+\tstruct mtk_wed_ring *ring = &dev->txfree_ring;\n+\tint i;\n+\n+\t/*\n+\t * For txfree event handling, the same DMA ring is shared between WED\n+\t * and WLAN. The WLAN driver accesses the ring index registers through\n+\t * WED\n+\t */\n+\tring->reg_base = MTK_WED_RING_RX(1);\n+\tring->wpdma = regs;\n+\n+\tfor (i = 0; i < 12; i += 4) {\n+\t\tu32 val = readl(regs + i);\n+\n+\t\twed_w32(dev, MTK_WED_RING_RX(1) + i, val);\n+\t\twed_w32(dev, MTK_WED_WPDMA_RING_RX(1) + i, val);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static u32\n+mtk_wed_irq_get(struct mtk_wed_device *dev, u32 mask)\n+{\n+\tu32 val;\n+\n+\tval = wed_r32(dev, MTK_WED_EXT_INT_STATUS);\n+\twed_w32(dev, MTK_WED_EXT_INT_STATUS, val);\n+\tval &= MTK_WED_EXT_INT_STATUS_ERROR_MASK;\n+\tif (!dev->hw->num_flows)\n+\t\tval &= ~MTK_WED_EXT_INT_STATUS_TKID_WO_PYLD;\n+\tif (val && net_ratelimit())\n+\t\tpr_err(\"mtk_wed%d: error status=%08x\\n\", dev->hw->index, val);\n+\n+\tval = wed_r32(dev, MTK_WED_INT_STATUS);\n+\tval &= mask;\n+\twed_w32(dev, MTK_WED_INT_STATUS, val); /* ACK */\n+\n+\treturn val;\n+}\n+\n+static void\n+mtk_wed_irq_set_mask(struct mtk_wed_device *dev, u32 mask)\n+{\n+\tif (!dev->running)\n+\t\treturn;\n+\n+\tmtk_wed_set_ext_int(dev, !!mask);\n+\twed_w32(dev, MTK_WED_INT_MASK, mask);\n+}\n+\n+int mtk_wed_flow_add(int index)\n+{\n+\tstruct mtk_wed_hw *hw = hw_list[index];\n+\tint ret;\n+\n+\tif (!hw || !hw->wed_dev)\n+\t\treturn -ENODEV;\n+\n+\tif (hw->num_flows) {\n+\t\thw->num_flows++;\n+\t\treturn 0;\n+\t}\n+\n+\tmutex_lock(&hw_lock);\n+\tif (!hw->wed_dev) {\n+\t\tret = -ENODEV;\n+\t\tgoto out;\n+\t}\n+\n+\tret = hw->wed_dev->wlan.offload_enable(hw->wed_dev);\n+\tif (!ret)\n+\t\thw->num_flows++;\n+\tmtk_wed_set_ext_int(hw->wed_dev, true);\n+\n+out:\n+\tmutex_unlock(&hw_lock);\n+\n+\treturn ret;\n+}\n+\n+void mtk_wed_flow_remove(int index)\n+{\n+\tstruct mtk_wed_hw *hw = hw_list[index];\n+\n+\tif (!hw)\n+\t\treturn;\n+\n+\tif (--hw->num_flows)\n+\t\treturn;\n+\n+\tmutex_lock(&hw_lock);\n+\tif (!hw->wed_dev)\n+\t\tgoto out;\n+\n+\thw->wed_dev->wlan.offload_disable(hw->wed_dev);\n+\tmtk_wed_set_ext_int(hw->wed_dev, true);\n+\n+out:\n+\tmutex_unlock(&hw_lock);\n+}\n+\n+void mtk_wed_add_hw(struct device_node *np, struct mtk_eth *eth,\n+\t\t    void __iomem *wdma, int index)\n+{\n+\tstatic const struct mtk_wed_ops wed_ops = {\n+\t\t.attach = mtk_wed_attach,\n+\t\t.tx_ring_setup = mtk_wed_tx_ring_setup,\n+\t\t.txfree_ring_setup = mtk_wed_txfree_ring_setup,\n+\t\t.start = mtk_wed_start,\n+\t\t.stop = mtk_wed_stop,\n+\t\t.reset_dma = mtk_wed_reset_dma,\n+\t\t.reg_read = wed_r32,\n+\t\t.reg_write = wed_w32,\n+\t\t.irq_get = mtk_wed_irq_get,\n+\t\t.irq_set_mask = mtk_wed_irq_set_mask,\n+\t\t.detach = mtk_wed_detach,\n+\t};\n+\tstruct device_node *eth_np = eth->dev->of_node;\n+\tstruct platform_device *pdev;\n+\tstruct mtk_wed_hw *hw;\n+\tstruct regmap *regs;\n+\tint irq;\n+\n+\tif (!np)\n+\t\treturn;\n+\n+\tpdev = of_find_device_by_node(np);\n+\tif (!pdev)\n+\t\treturn;\n+\n+\tget_device(&pdev->dev);\n+\tirq = platform_get_irq(pdev, 0);\n+\tif (irq < 0)\n+\t\treturn;\n+\n+\tregs = syscon_regmap_lookup_by_phandle(np, NULL);\n+\tif (!regs)\n+\t\treturn;\n+\n+\trcu_assign_pointer(mtk_soc_wed_ops, &wed_ops);\n+\n+\tmutex_lock(&hw_lock);\n+\n+\tif (WARN_ON(hw_list[index]))\n+\t\tgoto unlock;\n+\n+\thw = kzalloc(sizeof(*hw), GFP_KERNEL);\n+\thw->node = np;\n+\thw->regs = regs;\n+\thw->eth = eth;\n+\thw->dev = &pdev->dev;\n+\thw->wdma = wdma;\n+\thw->index = index;\n+\thw->irq = irq;\n+\thw->mirror = syscon_regmap_lookup_by_phandle(eth_np,\n+\t\t\t\t\t\t     \"mediatek,pcie-mirror\");\n+\thw->hifsys = syscon_regmap_lookup_by_phandle(eth_np,\n+\t\t\t\t\t\t     \"mediatek,hifsys\");\n+\tif (IS_ERR(hw->mirror) || IS_ERR(hw->hifsys)) {\n+\t\tkfree(hw);\n+\t\tgoto unlock;\n+\t}\n+\n+\tif (!index) {\n+\t\tregmap_write(hw->mirror, 0, 0);\n+\t\tregmap_write(hw->mirror, 4, 0);\n+\t}\n+\tmtk_wed_hw_add_debugfs(hw);\n+\n+\thw_list[index] = hw;\n+\n+unlock:\n+\tmutex_unlock(&hw_lock);\n+}\n+\n+void mtk_wed_exit(void)\n+{\n+\tint i;\n+\n+\trcu_assign_pointer(mtk_soc_wed_ops, NULL);\n+\n+\tsynchronize_rcu();\n+\n+\tfor (i = 0; i < ARRAY_SIZE(hw_list); i++) {\n+\t\tstruct mtk_wed_hw *hw;\n+\n+\t\thw = hw_list[i];\n+\t\tif (!hw)\n+\t\t\tcontinue;\n+\n+\t\thw_list[i] = NULL;\n+\t\tdebugfs_remove(hw->debugfs_dir);\n+\t\tput_device(hw->dev);\n+\t\tkfree(hw);\n+\t}\n+}\n--- /dev/null\n+++ b/drivers/net/ethernet/mediatek/mtk_wed.h\n@@ -0,0 +1,128 @@\n+// SPDX-License-Identifier: GPL-2.0-only\n+/* Copyright (C) 2021 Felix Fietkau <nbd@nbd.name> */\n+\n+#ifndef __MTK_WED_PRIV_H\n+#define __MTK_WED_PRIV_H\n+\n+#include <linux/soc/mediatek/mtk_wed.h>\n+#include <linux/debugfs.h>\n+#include <linux/regmap.h>\n+\n+struct mtk_eth;\n+\n+struct mtk_wed_hw {\n+\tstruct device_node *node;\n+\tstruct mtk_eth *eth;\n+\tstruct regmap *regs;\n+\tstruct regmap *hifsys;\n+\tstruct device *dev;\n+\tvoid __iomem *wdma;\n+\tstruct regmap *mirror;\n+\tstruct dentry *debugfs_dir;\n+\tstruct mtk_wed_device *wed_dev;\n+\tu32 debugfs_reg;\n+\tu32 num_flows;\n+\tchar dirname[5];\n+\tint irq;\n+\tint index;\n+};\n+\n+\n+#ifdef CONFIG_NET_MEDIATEK_SOC_WED\n+static inline void\n+wed_w32(struct mtk_wed_device *dev, u32 reg, u32 val)\n+{\n+\tregmap_write(dev->hw->regs, reg, val);\n+}\n+\n+static inline u32\n+wed_r32(struct mtk_wed_device *dev, u32 reg)\n+{\n+\tunsigned int val;\n+\n+\tregmap_read(dev->hw->regs, reg, &val);\n+\n+\treturn val;\n+}\n+\n+static inline void\n+wdma_w32(struct mtk_wed_device *dev, u32 reg, u32 val)\n+{\n+\twritel(val, dev->hw->wdma + reg);\n+}\n+\n+static inline u32\n+wdma_r32(struct mtk_wed_device *dev, u32 reg)\n+{\n+\treturn readl(dev->hw->wdma + reg);\n+}\n+\n+static inline u32\n+wpdma_tx_r32(struct mtk_wed_device *dev, int ring, u32 reg)\n+{\n+\tif (!dev->tx_ring[ring].wpdma)\n+\t\treturn 0;\n+\n+\treturn readl(dev->tx_ring[ring].wpdma + reg);\n+}\n+\n+static inline void\n+wpdma_tx_w32(struct mtk_wed_device *dev, int ring, u32 reg, u32 val)\n+{\n+\tif (!dev->tx_ring[ring].wpdma)\n+\t\treturn;\n+\n+\twritel(val, dev->tx_ring[ring].wpdma + reg);\n+}\n+\n+static inline u32\n+wpdma_txfree_r32(struct mtk_wed_device *dev, u32 reg)\n+{\n+\tif (!dev->txfree_ring.wpdma)\n+\t\treturn 0;\n+\n+\treturn readl(dev->txfree_ring.wpdma + reg);\n+}\n+\n+static inline void\n+wpdma_txfree_w32(struct mtk_wed_device *dev, u32 reg, u32 val)\n+{\n+\tif (!dev->txfree_ring.wpdma)\n+\t\treturn;\n+\n+\twritel(val, dev->txfree_ring.wpdma + reg);\n+}\n+\n+void mtk_wed_add_hw(struct device_node *np, struct mtk_eth *eth,\n+\t\t    void __iomem *wdma, int index);\n+void mtk_wed_exit(void);\n+int mtk_wed_flow_add(int index);\n+void mtk_wed_flow_remove(int index);\n+#else\n+static inline void\n+mtk_wed_add_hw(struct device_node *np, struct mtk_eth *eth,\n+\t       void __iomem *wdma, int index)\n+{\n+}\n+static inline void\n+mtk_wed_exit(void)\n+{\n+}\n+static inline int mtk_wed_flow_add(int index)\n+{\n+\treturn -EINVAL;\n+}\n+static inline void mtk_wed_flow_remove(int index)\n+{\n+}\n+#endif\n+\n+#ifdef CONFIG_DEBUG_FS\n+void mtk_wed_hw_add_debugfs(struct mtk_wed_hw *hw);\n+#else\n+static inline void mtk_wed_hw_add_debugfs(struct mtk_wed_hw *hw)\n+{\n+}\n+#endif\n+\n+#endif\n--- /dev/null\n+++ b/drivers/net/ethernet/mediatek/mtk_wed_debugfs.c\n@@ -0,0 +1,175 @@\n+// SPDX-License-Identifier: GPL-2.0-only\n+/* Copyright (C) 2021 Felix Fietkau <nbd@nbd.name> */\n+\n+#include <linux/seq_file.h>\n+#include \"mtk_wed.h\"\n+#include \"mtk_wed_regs.h\"\n+\n+struct reg_dump {\n+\tconst char *name;\n+\tu16 offset;\n+\tu8 type;\n+\tu8 base;\n+};\n+\n+enum {\n+\tDUMP_TYPE_STRING,\n+\tDUMP_TYPE_WED,\n+\tDUMP_TYPE_WDMA,\n+\tDUMP_TYPE_WPDMA_TX,\n+\tDUMP_TYPE_WPDMA_TXFREE,\n+};\n+\n+#define DUMP_STR(_str) { _str, 0, DUMP_TYPE_STRING }\n+#define DUMP_REG(_reg, ...) { #_reg, MTK_##_reg, __VA_ARGS__ }\n+#define DUMP_RING(_prefix, _base, ...)\t\t\t\t\\\n+\t{ _prefix \" BASE\", _base, __VA_ARGS__ },\t\t\\\n+\t{ _prefix \" CNT\",  _base + 0x4, __VA_ARGS__ },\t\\\n+\t{ _prefix \" CIDX\", _base + 0x8, __VA_ARGS__ },\t\\\n+\t{ _prefix \" DIDX\", _base + 0xc, __VA_ARGS__ }\n+\n+#define DUMP_WED(_reg) DUMP_REG(_reg, DUMP_TYPE_WED)\n+#define DUMP_WED_RING(_base) DUMP_RING(#_base, MTK_##_base, DUMP_TYPE_WED)\n+\n+#define DUMP_WDMA(_reg) DUMP_REG(_reg, DUMP_TYPE_WDMA)\n+#define DUMP_WDMA_RING(_base) DUMP_RING(#_base, MTK_##_base, DUMP_TYPE_WDMA)\n+\n+#define DUMP_WPDMA_TX_RING(_n) DUMP_RING(\"WPDMA_TX\" #_n, 0, DUMP_TYPE_WPDMA_TX, _n)\n+#define DUMP_WPDMA_TXFREE_RING DUMP_RING(\"WPDMA_RX1\", 0, DUMP_TYPE_WPDMA_TXFREE)\n+\n+static void\n+print_reg_val(struct seq_file *s, const char *name, u32 val)\n+{\n+\tseq_printf(s, \"%-32s %08x\\n\", name, val);\n+}\n+\n+static void\n+dump_wed_regs(struct seq_file *s, struct mtk_wed_device *dev,\n+\t      const struct reg_dump *regs, int n_regs)\n+{\n+\tconst struct reg_dump *cur;\n+\tu32 val;\n+\n+\tfor (cur = regs; cur < &regs[n_regs]; cur++) {\n+\t\tswitch (cur->type) {\n+\t\tcase DUMP_TYPE_STRING:\n+\t\t\tseq_printf(s, \"%s======== %s:\\n\",\n+\t\t\t\t   cur > regs ? \"\\n\" : \"\",\n+\t\t\t\t   cur->name);\n+\t\t\tcontinue;\n+\t\tcase DUMP_TYPE_WED:\n+\t\t\tval = wed_r32(dev, cur->offset);\n+\t\t\tbreak;\n+\t\tcase DUMP_TYPE_WDMA:\n+\t\t\tval = wdma_r32(dev, cur->offset);\n+\t\t\tbreak;\n+\t\tcase DUMP_TYPE_WPDMA_TX:\n+\t\t\tval = wpdma_tx_r32(dev, cur->base, cur->offset);\n+\t\t\tbreak;\n+\t\tcase DUMP_TYPE_WPDMA_TXFREE:\n+\t\t\tval = wpdma_txfree_r32(dev, cur->offset);\n+\t\t\tbreak;\n+\t\t}\n+\t\tprint_reg_val(s, cur->name, val);\n+\t}\n+}\n+\n+\n+static int\n+wed_txinfo_show(struct seq_file *s, void *data)\n+{\n+\tstatic const struct reg_dump regs[] = {\n+\t\tDUMP_STR(\"WED TX\"),\n+\t\tDUMP_WED(WED_TX_MIB(0)),\n+\t\tDUMP_WED_RING(WED_RING_TX(0)),\n+\n+\t\tDUMP_WED(WED_TX_MIB(1)),\n+\t\tDUMP_WED_RING(WED_RING_TX(1)),\n+\n+\t\tDUMP_STR(\"WPDMA TX\"),\n+\t\tDUMP_WED(WED_WPDMA_TX_MIB(0)),\n+\t\tDUMP_WED_RING(WED_WPDMA_RING_TX(0)),\n+\t\tDUMP_WED(WED_WPDMA_TX_COHERENT_MIB(0)),\n+\n+\t\tDUMP_WED(WED_WPDMA_TX_MIB(1)),\n+\t\tDUMP_WED_RING(WED_WPDMA_RING_TX(1)),\n+\t\tDUMP_WED(WED_WPDMA_TX_COHERENT_MIB(1)),\n+\n+\t\tDUMP_STR(\"WPDMA TX\"),\n+\t\tDUMP_WPDMA_TX_RING(0),\n+\t\tDUMP_WPDMA_TX_RING(1),\n+\n+\t\tDUMP_STR(\"WED WDMA RX\"),\n+\t\tDUMP_WED(WED_WDMA_RX_MIB(0)),\n+\t\tDUMP_WED_RING(WED_WDMA_RING_RX(0)),\n+\t\tDUMP_WED(WED_WDMA_RX_THRES(0)),\n+\t\tDUMP_WED(WED_WDMA_RX_RECYCLE_MIB(0)),\n+\t\tDUMP_WED(WED_WDMA_RX_PROCESSED_MIB(0)),\n+\n+\t\tDUMP_WED(WED_WDMA_RX_MIB(1)),\n+\t\tDUMP_WED_RING(WED_WDMA_RING_RX(1)),\n+\t\tDUMP_WED(WED_WDMA_RX_THRES(1)),\n+\t\tDUMP_WED(WED_WDMA_RX_RECYCLE_MIB(1)),\n+\t\tDUMP_WED(WED_WDMA_RX_PROCESSED_MIB(1)),\n+\n+\t\tDUMP_STR(\"WDMA RX\"),\n+\t\tDUMP_WDMA(WDMA_GLO_CFG),\n+\t\tDUMP_WDMA_RING(WDMA_RING_RX(0)),\n+\t\tDUMP_WDMA_RING(WDMA_RING_RX(1)),\n+\t};\n+\tstruct mtk_wed_hw *hw = s->private;\n+\tstruct mtk_wed_device *dev = hw->wed_dev;\n+\n+\tif (!dev)\n+\t\treturn 0;\n+\n+\tdump_wed_regs(s, dev, regs, ARRAY_SIZE(regs));\n+\n+\treturn 0;\n+}\n+DEFINE_SHOW_ATTRIBUTE(wed_txinfo);\n+\n+\n+static int\n+mtk_wed_reg_set(void *data, u64 val)\n+{\n+\tstruct mtk_wed_hw *hw = data;\n+\n+\tregmap_write(hw->regs, hw->debugfs_reg, val);\n+\n+\treturn 0;\n+}\n+\n+static int\n+mtk_wed_reg_get(void *data, u64 *val)\n+{\n+\tstruct mtk_wed_hw *hw = data;\n+\tunsigned int regval;\n+\tint ret;\n+\n+\tret = regmap_read(hw->regs, hw->debugfs_reg, &regval);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\t*val = regval;\n+\n+\treturn 0;\n+}\n+\n+DEFINE_DEBUGFS_ATTRIBUTE(fops_regval, mtk_wed_reg_get, mtk_wed_reg_set,\n+             \"0x%08llx\\n\");\n+\n+void mtk_wed_hw_add_debugfs(struct mtk_wed_hw *hw)\n+{\n+\tstruct dentry *dir;\n+\n+\tsnprintf(hw->dirname, sizeof(hw->dirname), \"wed%d\", hw->index);\n+\tdir = debugfs_create_dir(hw->dirname, NULL);\n+\tif (!dir)\n+\t\treturn;\n+\n+\thw->debugfs_dir = dir;\n+\tdebugfs_create_u32(\"regidx\", 0600, dir, &hw->debugfs_reg);\n+\tdebugfs_create_file_unsafe(\"regval\", 0600, dir, hw, &fops_regval);\n+\tdebugfs_create_file_unsafe(\"txinfo\", 0400, dir, hw, &wed_txinfo_fops);\n+}\n--- /dev/null\n+++ b/drivers/net/ethernet/mediatek/mtk_wed_ops.c\n@@ -0,0 +1,8 @@\n+// SPDX-License-Identifier: GPL-2.0-only\n+/* Copyright (C) 2020 Felix Fietkau <nbd@nbd.name> */\n+\n+#include <linux/kernel.h>\n+#include <linux/soc/mediatek/mtk_wed.h>\n+\n+const struct mtk_wed_ops __rcu *mtk_soc_wed_ops;\n+EXPORT_SYMBOL_GPL(mtk_soc_wed_ops);\n--- /dev/null\n+++ b/drivers/net/ethernet/mediatek/mtk_wed_regs.h\n@@ -0,0 +1,251 @@\n+// SPDX-License-Identifier: GPL-2.0-only\n+/* Copyright (C) 2020 Felix Fietkau <nbd@nbd.name> */\n+\n+#ifndef __MTK_WED_REGS_H\n+#define __MTK_WED_REGS_H\n+\n+#define MTK_WDMA_DESC_CTRL_LEN1\t\t\tGENMASK(14, 0)\n+#define MTK_WDMA_DESC_CTRL_LAST_SEG1\t\tBIT(15)\n+#define MTK_WDMA_DESC_CTRL_BURST\t\tBIT(16)\n+#define MTK_WDMA_DESC_CTRL_LEN0\t\t\tGENMASK(29, 16)\n+#define MTK_WDMA_DESC_CTRL_LAST_SEG0\t\tBIT(30)\n+#define MTK_WDMA_DESC_CTRL_DMA_DONE\t\tBIT(31)\n+\n+struct mtk_wdma_desc {\n+\t__le32 buf0;\n+\t__le32 ctrl;\n+\t__le32 buf1;\n+\t__le32 info;\n+} __packed __aligned(4);\n+\n+#define MTK_WED_RESET\t\t\t\t\t0x008\n+#define MTK_WED_RESET_TX_BM\t\t\t\tBIT(0)\n+#define MTK_WED_RESET_TX_FREE_AGENT\t\t\tBIT(4)\n+#define MTK_WED_RESET_WPDMA_TX_DRV\t\t\tBIT(8)\n+#define MTK_WED_RESET_WPDMA_RX_DRV\t\t\tBIT(9)\n+#define MTK_WED_RESET_WPDMA_INT_AGENT\t\t\tBIT(11)\n+#define MTK_WED_RESET_WED_TX_DMA\t\t\tBIT(12)\n+#define MTK_WED_RESET_WDMA_RX_DRV\t\t\tBIT(17)\n+#define MTK_WED_RESET_WDMA_INT_AGENT\t\t\tBIT(19)\n+#define MTK_WED_RESET_WED\t\t\t\tBIT(31)\n+\n+#define MTK_WED_CTRL\t\t\t\t\t0x00c\n+#define MTK_WED_CTRL_WPDMA_INT_AGENT_EN\t\t\tBIT(0)\n+#define MTK_WED_CTRL_WPDMA_INT_AGENT_BUSY\t\tBIT(1)\n+#define MTK_WED_CTRL_WDMA_INT_AGENT_EN\t\t\tBIT(2)\n+#define MTK_WED_CTRL_WDMA_INT_AGENT_BUSY\t\tBIT(3)\n+#define MTK_WED_CTRL_WED_TX_BM_EN\t\t\tBIT(8)\n+#define MTK_WED_CTRL_WED_TX_BM_BUSY\t\t\tBIT(9)\n+#define MTK_WED_CTRL_WED_TX_FREE_AGENT_EN\t\tBIT(10)\n+#define MTK_WED_CTRL_WED_TX_FREE_AGENT_BUSY\t\tBIT(11)\n+#define MTK_WED_CTRL_RESERVE_EN\t\t\t\tBIT(12)\n+#define MTK_WED_CTRL_RESERVE_BUSY\t\t\tBIT(13)\n+#define MTK_WED_CTRL_FINAL_DIDX_READ\t\t\tBIT(24)\n+#define MTK_WED_CTRL_MIB_READ_CLEAR\t\t\tBIT(28)\n+\n+#define MTK_WED_EXT_INT_STATUS\t\t\t\t0x020\n+#define MTK_WED_EXT_INT_STATUS_TF_LEN_ERR\t\tBIT(0)\n+#define MTK_WED_EXT_INT_STATUS_TKID_WO_PYLD\t\tBIT(1)\n+#define MTK_WED_EXT_INT_STATUS_TKID_TITO_INVALID\tBIT(4)\n+#define MTK_WED_EXT_INT_STATUS_TX_FBUF_LO_TH\t\tBIT(8)\n+#define MTK_WED_EXT_INT_STATUS_TX_FBUF_HI_TH\t\tBIT(9)\n+#define MTK_WED_EXT_INT_STATUS_RX_FBUF_LO_TH\t\tBIT(12)\n+#define MTK_WED_EXT_INT_STATUS_RX_FBUF_HI_TH\t\tBIT(13)\n+#define MTK_WED_EXT_INT_STATUS_RX_DRV_R_RESP_ERR\tBIT(16)\n+#define MTK_WED_EXT_INT_STATUS_RX_DRV_W_RESP_ERR\tBIT(17)\n+#define MTK_WED_EXT_INT_STATUS_RX_DRV_COHERENT\t\tBIT(18)\n+#define MTK_WED_EXT_INT_STATUS_RX_DRV_INIT_WDMA_EN\tBIT(19)\n+#define MTK_WED_EXT_INT_STATUS_RX_DRV_BM_DMAD_COHERENT\tBIT(20)\n+#define MTK_WED_EXT_INT_STATUS_TX_DRV_R_RESP_ERR\tBIT(21)\n+#define MTK_WED_EXT_INT_STATUS_TX_DRV_W_RESP_ERR\tBIT(22)\n+#define MTK_WED_EXT_INT_STATUS_RX_DRV_DMA_RECYCLE\tBIT(24)\n+#define MTK_WED_EXT_INT_STATUS_ERROR_MASK\t\t(MTK_WED_EXT_INT_STATUS_TF_LEN_ERR | \\\n+\t\t\t\t\t\t\t MTK_WED_EXT_INT_STATUS_TKID_WO_PYLD | \\\n+\t\t\t\t\t\t\t MTK_WED_EXT_INT_STATUS_TKID_TITO_INVALID | \\\n+\t\t\t\t\t\t\t MTK_WED_EXT_INT_STATUS_RX_DRV_R_RESP_ERR | \\\n+\t\t\t\t\t\t\t MTK_WED_EXT_INT_STATUS_RX_DRV_W_RESP_ERR | \\\n+\t\t\t\t\t\t\t MTK_WED_EXT_INT_STATUS_RX_DRV_INIT_WDMA_EN | \\\n+\t\t\t\t\t\t\t MTK_WED_EXT_INT_STATUS_TX_DRV_R_RESP_ERR | \\\n+\t\t\t\t\t\t\t MTK_WED_EXT_INT_STATUS_TX_DRV_W_RESP_ERR)\n+\n+#define MTK_WED_EXT_INT_MASK\t\t\t\t0x028\n+\n+#define MTK_WED_STATUS\t\t\t\t\t0x060\n+#define MTK_WED_STATUS_TX\t\t\t\tGENMASK(15, 8)\n+\n+#define MTK_WED_TX_BM_CTRL\t\t\t\t0x080\n+#define MTK_WED_TX_BM_CTRL_VLD_GRP_NUM\t\t\tGENMASK(6, 0)\n+#define MTK_WED_TX_BM_CTRL_RSV_GRP_NUM\t\t\tGENMASK(22, 16)\n+#define MTK_WED_TX_BM_CTRL_PAUSE\t\t\tBIT(28)\n+\n+#define MTK_WED_TX_BM_BASE\t\t\t\t0x084\n+\n+#define MTK_WED_TX_BM_TKID\t\t\t\t0x088\n+#define MTK_WED_TX_BM_TKID_START\t\t\tGENMASK(15, 0)\n+#define MTK_WED_TX_BM_TKID_END\t\t\t\tGENMASK(31, 16)\n+\n+#define MTK_WED_TX_BM_BUF_LEN\t\t\t\t0x08c\n+\n+#define MTK_WED_TX_BM_INTF\t\t\t\t0x09c\n+#define MTK_WED_TX_BM_INTF_TKID\t\t\t\tGENMASK(15, 0)\n+#define MTK_WED_TX_BM_INTF_TKFIFO_FDEP\t\t\tGENMASK(23, 16)\n+#define MTK_WED_TX_BM_INTF_TKID_VALID\t\t\tBIT(28)\n+#define MTK_WED_TX_BM_INTF_TKID_READ\t\t\tBIT(29)\n+\n+#define MTK_WED_TX_BM_DYN_THR\t\t\t\t0x0a0\n+#define MTK_WED_TX_BM_DYN_THR_LO\t\t\tGENMASK(6, 0)\n+#define MTK_WED_TX_BM_DYN_THR_HI\t\t\tGENMASK(22, 16)\n+\n+#define MTK_WED_INT_STATUS\t\t\t\t0x200\n+#define MTK_WED_INT_MASK\t\t\t\t0x204\n+\n+#define MTK_WED_GLO_CFG\t\t\t\t\t0x208\n+#define MTK_WED_GLO_CFG_TX_DMA_EN\t\t\tBIT(0)\n+#define MTK_WED_GLO_CFG_TX_DMA_BUSY\t\t\tBIT(1)\n+#define MTK_WED_GLO_CFG_RX_DMA_EN\t\t\tBIT(2)\n+#define MTK_WED_GLO_CFG_RX_DMA_BUSY\t\t\tBIT(3)\n+#define MTK_WED_GLO_CFG_RX_BT_SIZE\t\t\tGENMASK(5, 4)\n+#define MTK_WED_GLO_CFG_TX_WB_DDONE\t\t\tBIT(6)\n+#define MTK_WED_GLO_CFG_BIG_ENDIAN\t\t\tBIT(7)\n+#define MTK_WED_GLO_CFG_DIS_BT_SIZE_ALIGN\t\tBIT(8)\n+#define MTK_WED_GLO_CFG_TX_BT_SIZE_LO\t\t\tBIT(9)\n+#define MTK_WED_GLO_CFG_MULTI_DMA_EN\t\t\tGENMASK(11, 10)\n+#define MTK_WED_GLO_CFG_FIFO_LITTLE_ENDIAN\t\tBIT(12)\n+#define MTK_WED_GLO_CFG_MI_DEPTH_RD\t\t\tGENMASK(21, 13)\n+#define MTK_WED_GLO_CFG_TX_BT_SIZE_HI\t\t\tGENMASK(23, 22)\n+#define MTK_WED_GLO_CFG_SW_RESET\t\t\tBIT(24)\n+#define MTK_WED_GLO_CFG_FIRST_TOKEN_ONLY\t\tBIT(26)\n+#define MTK_WED_GLO_CFG_OMIT_RX_INFO\t\t\tBIT(27)\n+#define MTK_WED_GLO_CFG_OMIT_TX_INFO\t\t\tBIT(28)\n+#define MTK_WED_GLO_CFG_BYTE_SWAP\t\t\tBIT(29)\n+#define MTK_WED_GLO_CFG_RX_2B_OFFSET\t\t\tBIT(31)\n+\n+#define MTK_WED_RESET_IDX\t\t\t\t0x20c\n+#define MTK_WED_RESET_IDX_TX\t\t\t\tGENMASK(3, 0)\n+#define MTK_WED_RESET_IDX_RX\t\t\t\tGENMASK(17, 16)\n+\n+#define MTK_WED_TX_MIB(_n)\t\t\t\t(0x2a0 + (_n) * 4)\n+\n+#define MTK_WED_RING_TX(_n)\t\t\t\t(0x300 + (_n) * 0x10)\n+\n+#define MTK_WED_RING_RX(_n)\t\t\t\t(0x400 + (_n) * 0x10)\n+\n+#define MTK_WED_WPDMA_INT_TRIGGER\t\t\t0x504\n+#define MTK_WED_WPDMA_INT_TRIGGER_RX_DONE\t\tBIT(1)\n+#define MTK_WED_WPDMA_INT_TRIGGER_TX_DONE\t\tGENMASK(5, 4)\n+\n+#define MTK_WED_WPDMA_GLO_CFG\t\t\t\t0x508\n+#define MTK_WED_WPDMA_GLO_CFG_TX_DRV_EN\t\t\tBIT(0)\n+#define MTK_WED_WPDMA_GLO_CFG_TX_DRV_BUSY\t\tBIT(1)\n+#define MTK_WED_WPDMA_GLO_CFG_RX_DRV_EN\t\t\tBIT(2)\n+#define MTK_WED_WPDMA_GLO_CFG_RX_DRV_BUSY\t\tBIT(3)\n+#define MTK_WED_WPDMA_GLO_CFG_RX_BT_SIZE\t\tGENMASK(5, 4)\n+#define MTK_WED_WPDMA_GLO_CFG_TX_WB_DDONE\t\tBIT(6)\n+#define MTK_WED_WPDMA_GLO_CFG_BIG_ENDIAN\t\tBIT(7)\n+#define MTK_WED_WPDMA_GLO_CFG_DIS_BT_SIZE_ALIGN\t\tBIT(8)\n+#define MTK_WED_WPDMA_GLO_CFG_TX_BT_SIZE_LO\t\tBIT(9)\n+#define MTK_WED_WPDMA_GLO_CFG_MULTI_DMA_EN\t\tGENMASK(11, 10)\n+#define MTK_WED_WPDMA_GLO_CFG_FIFO_LITTLE_ENDIAN\tBIT(12)\n+#define MTK_WED_WPDMA_GLO_CFG_MI_DEPTH_RD\t\tGENMASK(21, 13)\n+#define MTK_WED_WPDMA_GLO_CFG_TX_BT_SIZE_HI\t\tGENMASK(23, 22)\n+#define MTK_WED_WPDMA_GLO_CFG_SW_RESET\t\t\tBIT(24)\n+#define MTK_WED_WPDMA_GLO_CFG_FIRST_TOKEN_ONLY\t\tBIT(26)\n+#define MTK_WED_WPDMA_GLO_CFG_OMIT_RX_INFO\t\tBIT(27)\n+#define MTK_WED_WPDMA_GLO_CFG_OMIT_TX_INFO\t\tBIT(28)\n+#define MTK_WED_WPDMA_GLO_CFG_BYTE_SWAP\t\t\tBIT(29)\n+#define MTK_WED_WPDMA_GLO_CFG_RX_2B_OFFSET\t\tBIT(31)\n+\n+#define MTK_WED_WPDMA_RESET_IDX\t\t\t\t0x50c\n+#define MTK_WED_WPDMA_RESET_IDX_TX\t\t\tGENMASK(3, 0)\n+#define MTK_WED_WPDMA_RESET_IDX_RX\t\t\tGENMASK(17, 16)\n+\n+#define MTK_WED_WPDMA_INT_CTRL\t\t\t\t0x520\n+#define MTK_WED_WPDMA_INT_CTRL_SUBRT_ADV\t\tBIT(21)\n+\n+#define MTK_WED_WPDMA_INT_MASK\t\t\t\t0x524\n+\n+#define MTK_WED_PCIE_CFG_BASE\t\t\t\t0x560\n+\n+#define MTK_WED_PCIE_INT_TRIGGER\t\t\t0x570\n+#define MTK_WED_PCIE_INT_TRIGGER_STATUS\t\t\tBIT(16)\n+\n+#define MTK_WED_WPDMA_CFG_BASE\t\t\t\t0x580\n+\n+#define MTK_WED_WPDMA_TX_MIB(_n)\t\t\t(0x5a0 + (_n) * 4)\n+#define MTK_WED_WPDMA_TX_COHERENT_MIB(_n)\t\t(0x5d0 + (_n) * 4)\n+\n+#define MTK_WED_WPDMA_RING_TX(_n)\t\t\t(0x600 + (_n) * 0x10)\n+#define MTK_WED_WPDMA_RING_RX(_n)\t\t\t(0x700 + (_n) * 0x10)\n+#define MTK_WED_WDMA_RING_RX(_n)\t\t\t(0x900 + (_n) * 0x10)\n+#define MTK_WED_WDMA_RX_THRES(_n)\t\t\t(0x940 + (_n) * 0x4)\n+\n+#define MTK_WED_WDMA_GLO_CFG\t\t\t\t0xa04\n+#define MTK_WED_WDMA_GLO_CFG_TX_DRV_EN\t\t\tBIT(0)\n+#define MTK_WED_WDMA_GLO_CFG_RX_DRV_EN\t\t\tBIT(2)\n+#define MTK_WED_WDMA_GLO_CFG_RX_DRV_BUSY\t\tBIT(3)\n+#define MTK_WED_WDMA_GLO_CFG_BT_SIZE\t\t\tGENMASK(5, 4)\n+#define MTK_WED_WDMA_GLO_CFG_TX_WB_DDONE\t\tBIT(6)\n+#define MTK_WED_WDMA_GLO_CFG_RX_DIS_FSM_AUTO_IDLE\tBIT(13)\n+#define MTK_WED_WDMA_GLO_CFG_WCOMPLETE_SEL\t\tBIT(16)\n+#define MTK_WED_WDMA_GLO_CFG_INIT_PHASE_RXDMA_BYPASS\tBIT(17)\n+#define MTK_WED_WDMA_GLO_CFG_INIT_PHASE_BYPASS\t\tBIT(18)\n+#define MTK_WED_WDMA_GLO_CFG_FSM_RETURN_IDLE\t\tBIT(19)\n+#define MTK_WED_WDMA_GLO_CFG_WAIT_COHERENT\t\tBIT(20)\n+#define MTK_WED_WDMA_GLO_CFG_AXI_W_AFTER_AW\t\tBIT(21)\n+#define MTK_WED_WDMA_GLO_CFG_IDLE_DMAD_SUPPLY_SINGLE_W\tBIT(22)\n+#define MTK_WED_WDMA_GLO_CFG_IDLE_DMAD_SUPPLY\t\tBIT(23)\n+#define MTK_WED_WDMA_GLO_CFG_DYNAMIC_SKIP_DMAD_PREP\tBIT(24)\n+#define MTK_WED_WDMA_GLO_CFG_DYNAMIC_DMAD_RECYCLE\tBIT(25)\n+#define MTK_WED_WDMA_GLO_CFG_RST_INIT_COMPLETE\t\tBIT(26)\n+#define MTK_WED_WDMA_GLO_CFG_RXDRV_CLKGATE_BYPASS\tBIT(30)\n+\n+#define MTK_WED_WDMA_RESET_IDX\t\t\t\t0xa08\n+#define MTK_WED_WDMA_RESET_IDX_RX\t\t\tGENMASK(17, 16)\n+#define MTK_WED_WDMA_RESET_IDX_DRV\t\t\tGENMASK(25, 24)\n+\n+#define MTK_WED_WDMA_INT_TRIGGER\t\t\t0xa28\n+#define MTK_WED_WDMA_INT_TRIGGER_RX_DONE\t\tGENMASK(17, 16)\n+\n+#define MTK_WED_WDMA_INT_CTRL\t\t\t\t0xa2c\n+#define MTK_WED_WDMA_INT_CTRL_POLL_SRC_SEL\t\tGENMASK(17, 16)\n+\n+#define MTK_WED_WDMA_OFFSET0\t\t\t\t0xaa4\n+#define MTK_WED_WDMA_OFFSET1\t\t\t\t0xaa8\n+\n+#define MTK_WED_WDMA_RX_MIB(_n)\t\t\t\t(0xae0 + (_n) * 4)\n+#define MTK_WED_WDMA_RX_RECYCLE_MIB(_n)\t\t\t(0xae8 + (_n) * 4)\n+#define MTK_WED_WDMA_RX_PROCESSED_MIB(_n)\t\t(0xaf0 + (_n) * 4)\n+\n+#define MTK_WED_RING_OFS_BASE\t\t\t\t0x00\n+#define MTK_WED_RING_OFS_COUNT\t\t\t\t0x04\n+#define MTK_WED_RING_OFS_CPU_IDX\t\t\t0x08\n+#define MTK_WED_RING_OFS_DMA_IDX\t\t\t0x0c\n+\n+#define MTK_WDMA_RING_RX(_n)\t\t\t\t(0x100 + (_n) * 0x10)\n+\n+#define MTK_WDMA_GLO_CFG\t\t\t\t0x204\n+#define MTK_WDMA_GLO_CFG_RX_INFO_PRERES\t\t\tGENMASK(28, 26)\n+\n+#define MTK_WDMA_RESET_IDX\t\t\t\t0x208\n+#define MTK_WDMA_RESET_IDX_TX\t\t\t\tGENMASK(3, 0)\n+#define MTK_WDMA_RESET_IDX_RX\t\t\t\tGENMASK(17, 16)\n+\n+#define MTK_WDMA_INT_MASK\t\t\t\t0x228\n+#define MTK_WDMA_INT_MASK_TX_DONE\t\t\tGENMASK(3, 0)\n+#define MTK_WDMA_INT_MASK_RX_DONE\t\t\tGENMASK(17, 16)\n+#define MTK_WDMA_INT_MASK_TX_DELAY\t\t\tBIT(28)\n+#define MTK_WDMA_INT_MASK_TX_COHERENT\t\t\tBIT(29)\n+#define MTK_WDMA_INT_MASK_RX_DELAY\t\t\tBIT(30)\n+#define MTK_WDMA_INT_MASK_RX_COHERENT\t\t\tBIT(31)\n+\n+#define MTK_WDMA_INT_GRP1\t\t\t\t0x250\n+#define MTK_WDMA_INT_GRP2\t\t\t\t0x254\n+\n+#define MTK_PCIE_MIRROR_MAP(n)\t\t\t\t((n) ? 0x4 : 0x0)\n+#define MTK_PCIE_MIRROR_MAP_EN\t\t\t\tBIT(0)\n+#define MTK_PCIE_MIRROR_MAP_WED_ID\t\t\tBIT(1)\n+\n+/* DMA channel mapping */\n+#define HIFSYS_DMA_AG_MAP\t\t\t\t0x008\n+\n+#endif\n--- /dev/null\n+++ b/include/linux/soc/mediatek/mtk_wed.h\n@@ -0,0 +1,131 @@\n+#ifndef __MTK_WED_H\n+#define __MTK_WED_H\n+\n+#include <linux/kernel.h>\n+#include <linux/rcupdate.h>\n+#include <linux/regmap.h>\n+#include <linux/pci.h>\n+\n+#define MTK_WED_TX_QUEUES\t\t2\n+\n+struct mtk_wed_hw;\n+struct mtk_wdma_desc;\n+\n+struct mtk_wed_ring {\n+\tstruct mtk_wdma_desc *desc;\n+\tdma_addr_t desc_phys;\n+\tint size;\n+\n+\tu32 reg_base;\n+\tvoid __iomem *wpdma;\n+};\n+\n+struct mtk_wed_device {\n+#ifdef CONFIG_NET_MEDIATEK_SOC_WED\n+\tconst struct mtk_wed_ops *ops;\n+\tstruct device *dev;\n+\tstruct mtk_wed_hw *hw;\n+\tbool init_done, running;\n+\tint wdma_idx;\n+\tint irq;\n+\n+\tstruct mtk_wed_ring tx_ring[MTK_WED_TX_QUEUES];\n+\tstruct mtk_wed_ring txfree_ring;\n+\tstruct mtk_wed_ring tx_wdma[MTK_WED_TX_QUEUES];\n+\n+\tstruct {\n+\t\tint size;\n+\t\tvoid **pages;\n+\t\tstruct mtk_wdma_desc *desc;\n+\t\tdma_addr_t desc_phys;\n+\t} buf_ring;\n+\n+\t/* filled by driver: */\n+\tstruct {\n+\t\tstruct pci_dev *pci_dev;\n+\n+\t\tu32 wpdma_phys;\n+\n+\t\tu16 token_start;\n+\t\tunsigned int nbuf;\n+\n+\t\tu32 (*init_buf)(void *ptr, dma_addr_t phys, int token_id);\n+\t\tint (*offload_enable)(struct mtk_wed_device *wed);\n+\t\tvoid (*offload_disable)(struct mtk_wed_device *wed);\n+\t} wlan;\n+#endif\n+};\n+\n+struct mtk_wed_ops {\n+\tint (*attach)(struct mtk_wed_device *dev);\n+\tint (*tx_ring_setup)(struct mtk_wed_device *dev, int ring,\n+\t\t\t     void __iomem *regs);\n+\tint (*txfree_ring_setup)(struct mtk_wed_device *dev,\n+\t\t\t\t void __iomem *regs);\n+\tvoid (*detach)(struct mtk_wed_device *dev);\n+\n+\tvoid (*stop)(struct mtk_wed_device *dev);\n+\tvoid (*start)(struct mtk_wed_device *dev, u32 irq_mask);\n+\tvoid (*reset_dma)(struct mtk_wed_device *dev);\n+\n+\tu32 (*reg_read)(struct mtk_wed_device *dev, u32 reg);\n+\tvoid (*reg_write)(struct mtk_wed_device *dev, u32 reg, u32 val);\n+\n+\tu32 (*irq_get)(struct mtk_wed_device *dev, u32 mask);\n+\tvoid (*irq_set_mask)(struct mtk_wed_device *dev, u32 mask);\n+};\n+\n+extern const struct mtk_wed_ops __rcu *mtk_soc_wed_ops;\n+\n+static inline int\n+mtk_wed_device_attach(struct mtk_wed_device *dev)\n+{\n+\tint ret = -ENODEV;\n+\n+#ifdef CONFIG_NET_MEDIATEK_SOC_WED\n+\trcu_read_lock();\n+\tdev->ops = rcu_dereference(mtk_soc_wed_ops);\n+\tif (dev->ops)\n+\t\tret = dev->ops->attach(dev);\n+\telse\n+\t\trcu_read_unlock();\n+\n+\tif (ret)\n+\t\tdev->ops = NULL;\n+#endif\n+\n+\treturn ret;\n+}\n+\n+#ifdef CONFIG_NET_MEDIATEK_SOC_WED\n+#define mtk_wed_device_active(_dev) !!(_dev)->ops\n+#define mtk_wed_device_detach(_dev) (_dev)->ops->detach(_dev)\n+#define mtk_wed_device_start(_dev, _mask) (_dev)->ops->start(_dev, _mask)\n+#define mtk_wed_device_tx_ring_setup(_dev, _ring, _regs) \\\n+\t(_dev)->ops->tx_ring_setup(_dev, _ring, _regs)\n+#define mtk_wed_device_txfree_ring_setup(_dev, _regs) \\\n+\t(_dev)->ops->txfree_ring_setup(_dev, _regs)\n+#define mtk_wed_device_reg_read(_dev, _reg) \\\n+\t(_dev)->ops->reg_read(_dev, _reg)\n+#define mtk_wed_device_reg_write(_dev, _reg, _val) \\\n+\t(_dev)->ops->reg_write(_dev, _reg, _val)\n+#define mtk_wed_device_irq_get(_dev, _mask) \\\n+\t(_dev)->ops->irq_get(_dev, _mask)\n+#define mtk_wed_device_irq_set_mask(_dev, _mask) \\\n+\t(_dev)->ops->irq_set_mask(_dev, _mask)\n+#else\n+static inline bool mtk_wed_device_active(struct mtk_wed_device *dev)\n+{\n+\treturn false;\n+}\n+#define mtk_wed_device_detach(_dev) do {} while (0)\n+#define mtk_wed_device_start(_dev, _mask) do {} while (0)\n+#define mtk_wed_device_tx_ring_setup(_dev, _ring, _regs) -ENODEV\n+#define mtk_wed_device_txfree_ring_setup(_dev, _ring, _regs) -ENODEV\n+#define mtk_wed_device_reg_read(_dev, _reg) 0\n+#define mtk_wed_device_reg_write(_dev, _reg, _val) do {} while (0)\n+#define mtk_wed_device_irq_get(_dev, _mask) 0\n+#define mtk_wed_device_irq_set_mask(_dev, _mask) do {} while (0)\n+#endif\n+\n+#endif\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/701-03-net-ethernet-mtk_eth_soc-implement-flow-offloading-t.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nDate: Sat, 5 Feb 2022 18:29:22 +0100\nSubject: [PATCH] net: ethernet: mtk_eth_soc: implement flow offloading\n to WED devices\n\nThis allows hardware flow offloading from Ethernet to WLAN on MT7622 SoC\n\nCo-developed-by: Lorenzo Bianconi <lorenzo@kernel.org>\nSigned-off-by: Lorenzo Bianconi <lorenzo@kernel.org>\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n\n--- a/drivers/net/ethernet/mediatek/mtk_ppe.c\n+++ b/drivers/net/ethernet/mediatek/mtk_ppe.c\n@@ -329,6 +329,24 @@ int mtk_foe_entry_set_pppoe(struct mtk_f\n \treturn 0;\n }\n \n+int mtk_foe_entry_set_wdma(struct mtk_foe_entry *entry, int wdma_idx, int txq,\n+\t\t\t   int bss, int wcid)\n+{\n+\tstruct mtk_foe_mac_info *l2 = mtk_foe_entry_l2(entry);\n+\tu32 *ib2 = mtk_foe_entry_ib2(entry);\n+\n+\t*ib2 &= ~MTK_FOE_IB2_PORT_MG;\n+\t*ib2 |= MTK_FOE_IB2_WDMA_WINFO;\n+\tif (wdma_idx)\n+\t\t*ib2 |= MTK_FOE_IB2_WDMA_DEVIDX;\n+\n+\tl2->vlan2 = FIELD_PREP(MTK_FOE_VLAN2_WINFO_BSS, bss) |\n+\t\t    FIELD_PREP(MTK_FOE_VLAN2_WINFO_WCID, wcid) |\n+\t\t    FIELD_PREP(MTK_FOE_VLAN2_WINFO_RING, txq);\n+\n+\treturn 0;\n+}\n+\n static inline bool mtk_foe_entry_usable(struct mtk_foe_entry *entry)\n {\n \treturn !(entry->ib1 & MTK_FOE_IB1_STATIC) &&\n--- a/drivers/net/ethernet/mediatek/mtk_ppe.h\n+++ b/drivers/net/ethernet/mediatek/mtk_ppe.h\n@@ -48,9 +48,9 @@ enum {\n #define MTK_FOE_IB2_DEST_PORT\t\tGENMASK(7, 5)\n #define MTK_FOE_IB2_MULTICAST\t\tBIT(8)\n \n-#define MTK_FOE_IB2_WHNAT_QID2\t\tGENMASK(13, 12)\n-#define MTK_FOE_IB2_WHNAT_DEVIDX\tBIT(16)\n-#define MTK_FOE_IB2_WHNAT_NAT\t\tBIT(17)\n+#define MTK_FOE_IB2_WDMA_QID2\t\tGENMASK(13, 12)\n+#define MTK_FOE_IB2_WDMA_DEVIDX\t\tBIT(16)\n+#define MTK_FOE_IB2_WDMA_WINFO\t\tBIT(17)\n \n #define MTK_FOE_IB2_PORT_MG\t\tGENMASK(17, 12)\n \n@@ -58,9 +58,9 @@ enum {\n \n #define MTK_FOE_IB2_DSCP\t\tGENMASK(31, 24)\n \n-#define MTK_FOE_VLAN2_WHNAT_BSS\t\tGEMMASK(5, 0)\n-#define MTK_FOE_VLAN2_WHNAT_WCID\tGENMASK(13, 6)\n-#define MTK_FOE_VLAN2_WHNAT_RING\tGENMASK(15, 14)\n+#define MTK_FOE_VLAN2_WINFO_BSS\t\tGENMASK(5, 0)\n+#define MTK_FOE_VLAN2_WINFO_WCID\tGENMASK(13, 6)\n+#define MTK_FOE_VLAN2_WINFO_RING\tGENMASK(15, 14)\n \n enum {\n \tMTK_FOE_STATE_INVALID,\n@@ -281,6 +281,8 @@ int mtk_foe_entry_set_ipv6_tuple(struct\n int mtk_foe_entry_set_dsa(struct mtk_foe_entry *entry, int port);\n int mtk_foe_entry_set_vlan(struct mtk_foe_entry *entry, int vid);\n int mtk_foe_entry_set_pppoe(struct mtk_foe_entry *entry, int sid);\n+int mtk_foe_entry_set_wdma(struct mtk_foe_entry *entry, int wdma_idx, int txq,\n+\t\t\t   int bss, int wcid);\n int mtk_foe_entry_commit(struct mtk_ppe *ppe, struct mtk_foe_entry *entry,\n \t\t\t u16 timestamp);\n int mtk_ppe_debugfs_init(struct mtk_ppe *ppe);\n--- a/drivers/net/ethernet/mediatek/mtk_ppe_offload.c\n+++ b/drivers/net/ethernet/mediatek/mtk_ppe_offload.c\n@@ -11,6 +11,7 @@\n #include <net/pkt_cls.h>\n #include <net/dsa.h>\n #include \"mtk_eth_soc.h\"\n+#include \"mtk_wed.h\"\n \n struct mtk_flow_data {\n \tstruct ethhdr eth;\n@@ -40,6 +41,7 @@ struct mtk_flow_entry {\n \tstruct rhash_head node;\n \tunsigned long cookie;\n \tu16 hash;\n+\ts8 wed_index;\n };\n \n static const struct rhashtable_params mtk_flow_ht_params = {\n@@ -81,6 +83,35 @@ mtk_flow_offload_mangle_eth(const struct\n \tmemcpy(dest, src, act->mangle.mask ? 2 : 4);\n }\n \n+static int\n+mtk_flow_get_wdma_info(struct net_device *dev, const u8 *addr, struct mtk_wdma_info *info)\n+{\n+\tstruct net_device_path_ctx ctx = {\n+\t\t.dev = dev,\n+\t\t.daddr = addr,\n+\t};\n+\tstruct net_device_path path = {};\n+\n+\tif (!IS_ENABLED(CONFIG_NET_MEDIATEK_SOC_WED))\n+\t\treturn -1;\n+\n+\tif (!dev->netdev_ops->ndo_fill_forward_path)\n+\t\treturn -1;\n+\n+\tif (dev->netdev_ops->ndo_fill_forward_path(&ctx, &path))\n+\t\treturn -1;\n+\n+\tif (path.type != DEV_PATH_MTK_WDMA)\n+\t\treturn -1;\n+\n+\tinfo->wdma_idx = path.mtk_wdma.wdma_idx;\n+\tinfo->queue = path.mtk_wdma.queue;\n+\tinfo->bss = path.mtk_wdma.bss;\n+\tinfo->wcid = path.mtk_wdma.wcid;\n+\n+\treturn 0;\n+}\n+\n \n static int\n mtk_flow_mangle_ports(const struct flow_action_entry *act,\n@@ -150,10 +181,20 @@ mtk_flow_get_dsa_port(struct net_device\n \n static int\n mtk_flow_set_output_device(struct mtk_eth *eth, struct mtk_foe_entry *foe,\n-\t\t\t   struct net_device *dev)\n+\t\t\t   struct net_device *dev, const u8 *dest_mac,\n+\t\t\t   int *wed_index)\n {\n+\tstruct mtk_wdma_info info = {};\n \tint pse_port, dsa_port;\n \n+\tif (mtk_flow_get_wdma_info(dev, dest_mac, &info) == 0) {\n+\t\tmtk_foe_entry_set_wdma(foe, info.wdma_idx, info.queue, info.bss,\n+\t\t\t\t       info.wcid);\n+\t\tpse_port = 3;\n+\t\t*wed_index = info.wdma_idx;\n+\t\tgoto out;\n+\t}\n+\n \tdsa_port = mtk_flow_get_dsa_port(&dev);\n \tif (dsa_port >= 0)\n \t\tmtk_foe_entry_set_dsa(foe, dsa_port);\n@@ -165,6 +206,7 @@ mtk_flow_set_output_device(struct mtk_et\n \telse\n \t\treturn -EOPNOTSUPP;\n \n+out:\n \tmtk_foe_entry_set_pse_port(foe, pse_port);\n \n \treturn 0;\n@@ -180,6 +222,7 @@ mtk_flow_offload_replace(struct mtk_eth\n \tstruct net_device *odev = NULL;\n \tstruct mtk_flow_entry *entry;\n \tint offload_type = 0;\n+\tint wed_index = -1;\n \tu16 addr_type = 0;\n \tu32 timestamp;\n \tu8 l4proto = 0;\n@@ -327,10 +370,14 @@ mtk_flow_offload_replace(struct mtk_eth\n \tif (data.pppoe.num == 1)\n \t\tmtk_foe_entry_set_pppoe(&foe, data.pppoe.sid);\n \n-\terr = mtk_flow_set_output_device(eth, &foe, odev);\n+\terr = mtk_flow_set_output_device(eth, &foe, odev, data.eth.h_dest,\n+\t\t\t\t\t &wed_index);\n \tif (err)\n \t\treturn err;\n \n+\tif (wed_index >= 0 && (err = mtk_wed_flow_add(wed_index)) < 0)\n+\t\treturn err;\n+\n \tentry = kzalloc(sizeof(*entry), GFP_KERNEL);\n \tif (!entry)\n \t\treturn -ENOMEM;\n@@ -344,6 +391,7 @@ mtk_flow_offload_replace(struct mtk_eth\n \t}\n \n \tentry->hash = hash;\n+\tentry->wed_index = wed_index;\n \terr = rhashtable_insert_fast(&eth->flow_table, &entry->node,\n \t\t\t\t     mtk_flow_ht_params);\n \tif (err < 0)\n@@ -354,6 +402,8 @@ clear_flow:\n \tmtk_foe_entry_clear(&eth->ppe, hash);\n free:\n \tkfree(entry);\n+\tif (wed_index >= 0)\n+\t    mtk_wed_flow_remove(wed_index);\n \treturn err;\n }\n \n@@ -370,6 +420,8 @@ mtk_flow_offload_destroy(struct mtk_eth\n \tmtk_foe_entry_clear(&eth->ppe, entry->hash);\n \trhashtable_remove_fast(&eth->flow_table, &entry->node,\n \t\t\t       mtk_flow_ht_params);\n+\tif (entry->wed_index >= 0)\n+\t\tmtk_wed_flow_remove(entry->wed_index);\n \tkfree(entry);\n \n \treturn 0;\n--- a/drivers/net/ethernet/mediatek/mtk_wed.h\n+++ b/drivers/net/ethernet/mediatek/mtk_wed.h\n@@ -7,6 +7,7 @@\n #include <linux/soc/mediatek/mtk_wed.h>\n #include <linux/debugfs.h>\n #include <linux/regmap.h>\n+#include <linux/netdevice.h>\n \n struct mtk_eth;\n \n@@ -27,6 +28,12 @@ struct mtk_wed_hw {\n \tint index;\n };\n \n+struct mtk_wdma_info {\n+\tu8 wdma_idx;\n+\tu8 queue;\n+\tu16 wcid;\n+\tu8 bss;\n+};\n \n #ifdef CONFIG_NET_MEDIATEK_SOC_WED\n static inline void\n--- a/include/linux/netdevice.h\n+++ b/include/linux/netdevice.h\n@@ -833,6 +833,7 @@ enum net_device_path_type {\n \tDEV_PATH_BRIDGE,\n \tDEV_PATH_PPPOE,\n \tDEV_PATH_DSA,\n+\tDEV_PATH_MTK_WDMA,\n };\n \n struct net_device_path {\n@@ -858,6 +859,12 @@ struct net_device_path {\n \t\t\tint port;\n \t\t\tu16 proto;\n \t\t} dsa;\n+\t\tstruct {\n+\t\t\tu8 wdma_idx;\n+\t\t\tu8 queue;\n+\t\t\tu16 wcid;\n+\t\t\tu8 bss;\n+\t\t} mtk_wdma;\n \t};\n };\n \n--- a/net/core/dev.c\n+++ b/net/core/dev.c\n@@ -883,6 +883,10 @@ int dev_fill_forward_path(const struct n\n \t\tif (WARN_ON_ONCE(last_dev == ctx.dev))\n \t\t\treturn -1;\n \t}\n+\n+\tif (!ctx.dev)\n+\t\treturn ret;\n+\n \tpath = dev_fwd_path(stack);\n \tif (!path)\n \t\treturn -1;\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/701-04-arm64-dts-mediatek-mt7622-introduce-nodes-for-Wirele.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nDate: Sat, 5 Feb 2022 18:36:36 +0100\nSubject: [PATCH] arm64: dts: mediatek: mt7622: introduce nodes for\n Wireless Ethernet Dispatch\n\nIntroduce wed0 and wed1 nodes in order to enable offloading forwarding\nbetween ethernet and wireless devices on the mt7622 chipset.\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n\n--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi\n+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi\n@@ -892,6 +892,11 @@\n \t\t};\n \t};\n \n+\thifsys: syscon@1af00000 {\n+\t\tcompatible = \"mediatek,mt7622-hifsys\", \"syscon\";\n+\t\treg = <0 0x1af00000 0 0x70>;\n+\t};\n+\n \tethsys: syscon@1b000000 {\n \t\tcompatible = \"mediatek,mt7622-ethsys\",\n \t\t\t     \"syscon\";\n@@ -910,6 +915,26 @@\n \t\t#dma-cells = <1>;\n \t};\n \n+\tpcie_mirror: pcie-mirror@10000400 {\n+\t\tcompatible = \"mediatek,mt7622-pcie-mirror\",\n+\t\t\t     \"syscon\";\n+\t\treg = <0 0x10000400 0 0x10>;\n+\t};\n+\n+\twed0: wed@1020a000 {\n+\t\tcompatible = \"mediatek,mt7622-wed\",\n+\t\t\t     \"syscon\";\n+\t\treg = <0 0x1020a000 0 0x1000>;\n+\t\tinterrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_LOW>;\n+\t};\n+\n+\twed1: wed@1020b000 {\n+\t\tcompatible = \"mediatek,mt7622-wed\",\n+\t\t\t     \"syscon\";\n+\t\treg = <0 0x1020b000 0 0x1000>;\n+\t\tinterrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_LOW>;\n+\t};\n+\n \teth: ethernet@1b100000 {\n \t\tcompatible = \"mediatek,mt7622-eth\",\n \t\t\t     \"mediatek,mt2701-eth\",\n@@ -937,6 +962,9 @@\n \t\tmediatek,ethsys = <&ethsys>;\n \t\tmediatek,sgmiisys = <&sgmiisys>;\n \t\tmediatek,cci-control = <&cci_control2>;\n+\t\tmediatek,wed = <&wed0>, <&wed1>;\n+\t\tmediatek,pcie-mirror = <&pcie_mirror>;\n+\t\tmediatek,hifsys = <&hifsys>;\n \t\tdma-coherent;\n \t\t#address-cells = <1>;\n \t\t#size-cells = <0>;\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/701-05-net-ethernet-mtk_eth_soc-add-ipv6-flow-offload-suppo.patch",
    "content": "From: David Bentham <db260179@gmail.com>\nDate: Mon, 21 Feb 2022 15:36:16 +0100\nSubject: [PATCH] net: ethernet: mtk_eth_soc: add ipv6 flow offload\n support\n\nAdd the missing IPv6 flow offloading support for routing only.\nHardware flow offloading is done by the packet processing engine (PPE)\nof the Ethernet MAC and as it doesn't support mangling of IPv6 packets,\nIPv6 NAT cannot be supported.\n\nSigned-off-by: David Bentham <db260179@gmail.com>\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n\n--- a/drivers/net/ethernet/mediatek/mtk_ppe_offload.c\n+++ b/drivers/net/ethernet/mediatek/mtk_ppe_offload.c\n@@ -7,6 +7,7 @@\n #include <linux/rhashtable.h>\n #include <linux/if_ether.h>\n #include <linux/ip.h>\n+#include <linux/ipv6.h>\n #include <net/flow_offload.h>\n #include <net/pkt_cls.h>\n #include <net/dsa.h>\n@@ -21,6 +22,11 @@ struct mtk_flow_data {\n \t\t\t__be32 src_addr;\n \t\t\t__be32 dst_addr;\n \t\t} v4;\n+\n+\t\tstruct {\n+\t\t\tstruct in6_addr src_addr;\n+\t\t\tstruct in6_addr dst_addr;\n+\t\t} v6;\n \t};\n \n \t__be16 src_port;\n@@ -66,6 +72,14 @@ mtk_flow_set_ipv4_addr(struct mtk_foe_en\n \t\t\t\t\t    data->v4.dst_addr, data->dst_port);\n }\n \n+static int\n+mtk_flow_set_ipv6_addr(struct mtk_foe_entry *foe, struct mtk_flow_data *data)\n+{\n+\treturn mtk_foe_entry_set_ipv6_tuple(foe,\n+\t\t\t\t\t    data->v6.src_addr.s6_addr32, data->src_port,\n+\t\t\t\t\t    data->v6.dst_addr.s6_addr32, data->dst_port);\n+}\n+\n static void\n mtk_flow_offload_mangle_eth(const struct flow_action_entry *act, void *eth)\n {\n@@ -297,6 +311,9 @@ mtk_flow_offload_replace(struct mtk_eth\n \tcase FLOW_DISSECTOR_KEY_IPV4_ADDRS:\n \t\toffload_type = MTK_PPE_PKT_TYPE_IPV4_HNAPT;\n \t\tbreak;\n+\tcase FLOW_DISSECTOR_KEY_IPV6_ADDRS:\n+\t\toffload_type = MTK_PPE_PKT_TYPE_IPV6_ROUTE_5T;\n+\t\tbreak;\n \tdefault:\n \t\treturn -EOPNOTSUPP;\n \t}\n@@ -332,6 +349,17 @@ mtk_flow_offload_replace(struct mtk_eth\n \t\tmtk_flow_set_ipv4_addr(&foe, &data, false);\n \t}\n \n+\tif (addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) {\n+\t\tstruct flow_match_ipv6_addrs addrs;\n+\n+\t\tflow_rule_match_ipv6_addrs(rule, &addrs);\n+\n+\t\tdata.v6.src_addr = addrs.key->src;\n+\t\tdata.v6.dst_addr = addrs.key->dst;\n+\n+\t\tmtk_flow_set_ipv6_addr(&foe, &data);\n+\t}\n+\n \tflow_action_for_each(i, act, &rule->action) {\n \t\tif (act->id != FLOW_ACTION_MANGLE)\n \t\t\tcontinue;\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/701-06-net-ethernet-mtk_eth_soc-support-TC_SETUP_BLOCK-for-.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nDate: Mon, 21 Feb 2022 15:37:21 +0100\nSubject: [PATCH] net: ethernet: mtk_eth_soc: support TC_SETUP_BLOCK for\n PPE offload\n\nThis allows offload entries to be created from user space\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n\n--- a/drivers/net/ethernet/mediatek/mtk_ppe_offload.c\n+++ b/drivers/net/ethernet/mediatek/mtk_ppe_offload.c\n@@ -564,10 +564,13 @@ mtk_eth_setup_tc_block(struct net_device\n int mtk_eth_setup_tc(struct net_device *dev, enum tc_setup_type type,\n \t\t     void *type_data)\n {\n-\tif (type == TC_SETUP_FT)\n+\tswitch (type) {\n+\tcase TC_SETUP_BLOCK:\n+\tcase TC_SETUP_FT:\n \t\treturn mtk_eth_setup_tc_block(dev, type_data);\n-\n-\treturn -EOPNOTSUPP;\n+\tdefault:\n+\t\treturn -EOPNOTSUPP;\n+\t}\n }\n \n int mtk_eth_offload_init(struct mtk_eth *eth)\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/701-07-net-ethernet-mtk_eth_soc-allocate-struct-mtk_ppe-sep.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nDate: Mon, 21 Feb 2022 15:38:20 +0100\nSubject: [PATCH] net: ethernet: mtk_eth_soc: allocate struct mtk_ppe\n separately\n\nPreparation for adding more data to it, which will increase its size.\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n\n--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c\n+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c\n@@ -2305,7 +2305,7 @@ static int mtk_open(struct net_device *d\n \t\tif (err)\n \t\t\treturn err;\n \n-\t\tif (eth->soc->offload_version && mtk_ppe_start(&eth->ppe) == 0)\n+\t\tif (eth->soc->offload_version && mtk_ppe_start(eth->ppe) == 0)\n \t\t\tgdm_config = MTK_GDMA_TO_PPE;\n \n \t\tmtk_gdm_config(eth, gdm_config);\n@@ -2379,7 +2379,7 @@ static int mtk_stop(struct net_device *d\n \tmtk_dma_free(eth);\n \n \tif (eth->soc->offload_version)\n-\t\tmtk_ppe_stop(&eth->ppe);\n+\t\tmtk_ppe_stop(eth->ppe);\n \n \treturn 0;\n }\n@@ -3265,10 +3265,11 @@ static int mtk_probe(struct platform_dev\n \t}\n \n \tif (eth->soc->offload_version) {\n-\t\terr = mtk_ppe_init(&eth->ppe, eth->dev,\n-\t\t\t\t   eth->base + MTK_ETH_PPE_BASE, 2);\n-\t\tif (err)\n+\t\teth->ppe = mtk_ppe_init(eth->dev, eth->base + MTK_ETH_PPE_BASE, 2);\n+\t\tif (!eth->ppe) {\n+\t\t\terr = -ENOMEM;\n \t\t\tgoto err_free_dev;\n+\t\t}\n \n \t\terr = mtk_eth_offload_init(eth);\n \t\tif (err)\n--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h\n+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h\n@@ -976,7 +976,7 @@ struct mtk_eth {\n \tu32\t\t\t\trx_dma_l4_valid;\n \tint\t\t\t\tip_align;\n \n-\tstruct mtk_ppe\t\t\tppe;\n+\tstruct mtk_ppe\t\t\t*ppe;\n \tstruct rhashtable\t\tflow_table;\n };\n \n--- a/drivers/net/ethernet/mediatek/mtk_ppe.c\n+++ b/drivers/net/ethernet/mediatek/mtk_ppe.c\n@@ -384,10 +384,15 @@ int mtk_foe_entry_commit(struct mtk_ppe\n \treturn hash;\n }\n \n-int mtk_ppe_init(struct mtk_ppe *ppe, struct device *dev, void __iomem *base,\n+struct mtk_ppe *mtk_ppe_init(struct device *dev, void __iomem *base,\n \t\t int version)\n {\n \tstruct mtk_foe_entry *foe;\n+\tstruct mtk_ppe *ppe;\n+\n+\tppe = devm_kzalloc(dev, sizeof(*ppe), GFP_KERNEL);\n+\tif (!ppe)\n+\t\treturn NULL;\n \n \t/* need to allocate a separate device, since it PPE DMA access is\n \t * not coherent.\n@@ -399,13 +404,13 @@ int mtk_ppe_init(struct mtk_ppe *ppe, st\n \tfoe = dmam_alloc_coherent(ppe->dev, MTK_PPE_ENTRIES * sizeof(*foe),\n \t\t\t\t  &ppe->foe_phys, GFP_KERNEL);\n \tif (!foe)\n-\t\treturn -ENOMEM;\n+\t\treturn NULL;\n \n \tppe->foe_table = foe;\n \n \tmtk_ppe_debugfs_init(ppe);\n \n-\treturn 0;\n+\treturn ppe;\n }\n \n static void mtk_ppe_init_foe_table(struct mtk_ppe *ppe)\n--- a/drivers/net/ethernet/mediatek/mtk_ppe.h\n+++ b/drivers/net/ethernet/mediatek/mtk_ppe.h\n@@ -246,8 +246,7 @@ struct mtk_ppe {\n \tvoid *acct_table;\n };\n \n-int mtk_ppe_init(struct mtk_ppe *ppe, struct device *dev, void __iomem *base,\n-\t\t int version);\n+struct mtk_ppe *mtk_ppe_init(struct device *dev, void __iomem *base, int version);\n int mtk_ppe_start(struct mtk_ppe *ppe);\n int mtk_ppe_stop(struct mtk_ppe *ppe);\n \n--- a/drivers/net/ethernet/mediatek/mtk_ppe_offload.c\n+++ b/drivers/net/ethernet/mediatek/mtk_ppe_offload.c\n@@ -412,7 +412,7 @@ mtk_flow_offload_replace(struct mtk_eth\n \n \tentry->cookie = f->cookie;\n \ttimestamp = mtk_eth_timestamp(eth);\n-\thash = mtk_foe_entry_commit(&eth->ppe, &foe, timestamp);\n+\thash = mtk_foe_entry_commit(eth->ppe, &foe, timestamp);\n \tif (hash < 0) {\n \t\terr = hash;\n \t\tgoto free;\n@@ -427,7 +427,7 @@ mtk_flow_offload_replace(struct mtk_eth\n \n \treturn 0;\n clear_flow:\n-\tmtk_foe_entry_clear(&eth->ppe, hash);\n+\tmtk_foe_entry_clear(eth->ppe, hash);\n free:\n \tkfree(entry);\n \tif (wed_index >= 0)\n@@ -445,7 +445,7 @@ mtk_flow_offload_destroy(struct mtk_eth\n \tif (!entry)\n \t\treturn -ENOENT;\n \n-\tmtk_foe_entry_clear(&eth->ppe, entry->hash);\n+\tmtk_foe_entry_clear(eth->ppe, entry->hash);\n \trhashtable_remove_fast(&eth->flow_table, &entry->node,\n \t\t\t       mtk_flow_ht_params);\n \tif (entry->wed_index >= 0)\n@@ -467,7 +467,7 @@ mtk_flow_offload_stats(struct mtk_eth *e\n \tif (!entry)\n \t\treturn -ENOENT;\n \n-\ttimestamp = mtk_foe_entry_timestamp(&eth->ppe, entry->hash);\n+\ttimestamp = mtk_foe_entry_timestamp(eth->ppe, entry->hash);\n \tif (timestamp < 0)\n \t\treturn -ETIMEDOUT;\n \n@@ -523,7 +523,7 @@ mtk_eth_setup_tc_block(struct net_device\n \tstruct flow_block_cb *block_cb;\n \tflow_setup_cb_t *cb;\n \n-\tif (!eth->ppe.foe_table)\n+\tif (!eth->ppe || !eth->ppe->foe_table)\n \t\treturn -EOPNOTSUPP;\n \n \tif (f->binder_type != FLOW_BLOCK_BINDER_TYPE_CLSACT_INGRESS)\n@@ -575,7 +575,7 @@ int mtk_eth_setup_tc(struct net_device *\n \n int mtk_eth_offload_init(struct mtk_eth *eth)\n {\n-\tif (!eth->ppe.foe_table)\n+\tif (!eth->ppe || !eth->ppe->foe_table)\n \t\treturn 0;\n \n \treturn rhashtable_init(&eth->flow_table, &mtk_flow_ht_params);\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/701-08-net-ethernet-mtk_eth_soc-rework-hardware-flow-table-.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nDate: Mon, 21 Feb 2022 15:39:18 +0100\nSubject: [PATCH] net: ethernet: mtk_eth_soc: rework hardware flow table\n management\n\nThe hardware was designed to handle flow detection and creation of flow entries\nby itself, relying on the software primarily for filling in egress routing\ninformation.\nWhen there is a hash collision between multiple flows, this allows the hardware\nto maintain the entry for the most active flow.\nAdditionally, the hardware only keeps offloading active for entries with at\nleast 30 packets per second.\n\nWith this rework, the code no longer creates a hardware entries directly.\nInstead, the hardware entry is only created when the PPE reports a matching\nunbound flow with the minimum target rate.\nIn order to reduce CPU overhead, looking for flows belonging to a hash entry\nis rate limited to once every 100ms.\n\nThis rework is also used as preparation for emulating bridge offload by\nmanaging L4 offload entries on demand.\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n\n--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c\n+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c\n@@ -21,6 +21,7 @@\n #include <linux/pinctrl/devinfo.h>\n #include <linux/phylink.h>\n #include <linux/jhash.h>\n+#include <linux/bitfield.h>\n #include <net/dsa.h>\n \n #include \"mtk_eth_soc.h\"\n@@ -1274,7 +1275,7 @@ static int mtk_poll_rx(struct napi_struc\n \t\tstruct net_device *netdev;\n \t\tunsigned int pktlen;\n \t\tdma_addr_t dma_addr;\n-\t\tu32 hash;\n+\t\tu32 hash, reason;\n \t\tint mac;\n \n \t\tring = mtk_get_rx_ring(eth);\n@@ -1350,6 +1351,11 @@ static int mtk_poll_rx(struct napi_struc\n \t\t\tskb_set_hash(skb, hash, PKT_HASH_TYPE_L4);\n \t\t}\n \n+\t\treason = FIELD_GET(MTK_RXD4_PPE_CPU_REASON, trxd.rxd4);\n+\t\tif (reason == MTK_PPE_CPU_REASON_HIT_UNBIND_RATE_REACHED)\n+\t\t\tmtk_ppe_check_skb(eth->ppe, skb,\n+\t\t\t\t\t  trxd.rxd4 & MTK_RXD4_FOE_ENTRY);\n+\n \t\tif (netdev->features & NETIF_F_HW_VLAN_CTAG_RX &&\n \t\t    (trxd.rxd2 & RX_DMA_VTAG))\n \t\t\t__vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),\n@@ -3265,7 +3271,7 @@ static int mtk_probe(struct platform_dev\n \t}\n \n \tif (eth->soc->offload_version) {\n-\t\teth->ppe = mtk_ppe_init(eth->dev, eth->base + MTK_ETH_PPE_BASE, 2);\n+\t\teth->ppe = mtk_ppe_init(eth, eth->base + MTK_ETH_PPE_BASE, 2);\n \t\tif (!eth->ppe) {\n \t\t\terr = -ENOMEM;\n \t\t\tgoto err_free_dev;\n--- a/drivers/net/ethernet/mediatek/mtk_ppe.c\n+++ b/drivers/net/ethernet/mediatek/mtk_ppe.c\n@@ -6,9 +6,12 @@\n #include <linux/iopoll.h>\n #include <linux/etherdevice.h>\n #include <linux/platform_device.h>\n+#include \"mtk_eth_soc.h\"\n #include \"mtk_ppe.h\"\n #include \"mtk_ppe_regs.h\"\n \n+static DEFINE_SPINLOCK(ppe_lock);\n+\n static void ppe_w32(struct mtk_ppe *ppe, u32 reg, u32 val)\n {\n \twritel(val, ppe->base + reg);\n@@ -41,6 +44,11 @@ static u32 ppe_clear(struct mtk_ppe *ppe\n \treturn ppe_m32(ppe, reg, val, 0);\n }\n \n+static u32 mtk_eth_timestamp(struct mtk_eth *eth)\n+{\n+\treturn mtk_r32(eth, 0x0010) & MTK_FOE_IB1_BIND_TIMESTAMP;\n+}\n+\n static int mtk_ppe_wait_busy(struct mtk_ppe *ppe)\n {\n \tint ret;\n@@ -353,26 +361,59 @@ static inline bool mtk_foe_entry_usable(\n \t       FIELD_GET(MTK_FOE_IB1_STATE, entry->ib1) != MTK_FOE_STATE_BIND;\n }\n \n-int mtk_foe_entry_commit(struct mtk_ppe *ppe, struct mtk_foe_entry *entry,\n-\t\t\t u16 timestamp)\n+static bool\n+mtk_flow_entry_match(struct mtk_flow_entry *entry, struct mtk_foe_entry *data)\n+{\n+\tint type, len;\n+\n+\tif ((data->ib1 ^ entry->data.ib1) & MTK_FOE_IB1_UDP)\n+\t\treturn false;\n+\n+\ttype = FIELD_GET(MTK_FOE_IB1_PACKET_TYPE, entry->data.ib1);\n+\tif (type > MTK_PPE_PKT_TYPE_IPV4_DSLITE)\n+\t\tlen = offsetof(struct mtk_foe_entry, ipv6._rsv);\n+\telse\n+\t\tlen = offsetof(struct mtk_foe_entry, ipv4.ib2);\n+\n+\treturn !memcmp(&entry->data.data, &data->data, len - 4);\n+}\n+\n+static void\n+mtk_flow_entry_update(struct mtk_ppe *ppe, struct mtk_flow_entry *entry)\n {\n \tstruct mtk_foe_entry *hwe;\n-\tu32 hash;\n+\tstruct mtk_foe_entry foe;\n \n+\tspin_lock_bh(&ppe_lock);\n+\tif (entry->hash == 0xffff)\n+\t\tgoto out;\n+\n+\thwe = &ppe->foe_table[entry->hash];\n+\tmemcpy(&foe, hwe, sizeof(foe));\n+\tif (!mtk_flow_entry_match(entry, &foe)) {\n+\t\tentry->hash = 0xffff;\n+\t\tgoto out;\n+\t}\n+\n+\tentry->data.ib1 = foe.ib1;\n+\n+out:\n+\tspin_unlock_bh(&ppe_lock);\n+}\n+\n+static void\n+__mtk_foe_entry_commit(struct mtk_ppe *ppe, struct mtk_foe_entry *entry,\n+\t\t       u16 hash)\n+{\n+\tstruct mtk_foe_entry *hwe;\n+\tu16 timestamp;\n+\n+\ttimestamp = mtk_eth_timestamp(ppe->eth);\n \ttimestamp &= MTK_FOE_IB1_BIND_TIMESTAMP;\n \tentry->ib1 &= ~MTK_FOE_IB1_BIND_TIMESTAMP;\n \tentry->ib1 |= FIELD_PREP(MTK_FOE_IB1_BIND_TIMESTAMP, timestamp);\n \n-\thash = mtk_ppe_hash_entry(entry);\n \thwe = &ppe->foe_table[hash];\n-\tif (!mtk_foe_entry_usable(hwe)) {\n-\t\thwe++;\n-\t\thash++;\n-\n-\t\tif (!mtk_foe_entry_usable(hwe))\n-\t\t\treturn -ENOSPC;\n-\t}\n-\n \tmemcpy(&hwe->data, &entry->data, sizeof(hwe->data));\n \twmb();\n \thwe->ib1 = entry->ib1;\n@@ -380,13 +421,77 @@ int mtk_foe_entry_commit(struct mtk_ppe\n \tdma_wmb();\n \n \tmtk_ppe_cache_clear(ppe);\n+}\n \n-\treturn hash;\n+void mtk_foe_entry_clear(struct mtk_ppe *ppe, struct mtk_flow_entry *entry)\n+{\n+\tspin_lock_bh(&ppe_lock);\n+\thlist_del_init(&entry->list);\n+\tif (entry->hash != 0xffff) {\n+\t\tppe->foe_table[entry->hash].ib1 &= ~MTK_FOE_IB1_STATE;\n+\t\tppe->foe_table[entry->hash].ib1 |= FIELD_PREP(MTK_FOE_IB1_STATE,\n+\t\t\t\t\t\t\t      MTK_FOE_STATE_BIND);\n+\t\tdma_wmb();\n+\t}\n+\tentry->hash = 0xffff;\n+\tspin_unlock_bh(&ppe_lock);\n+}\n+\n+int mtk_foe_entry_commit(struct mtk_ppe *ppe, struct mtk_flow_entry *entry)\n+{\n+\tu32 hash = mtk_ppe_hash_entry(&entry->data);\n+\n+\tentry->hash = 0xffff;\n+\tspin_lock_bh(&ppe_lock);\n+\thlist_add_head(&entry->list, &ppe->foe_flow[hash / 2]);\n+\tspin_unlock_bh(&ppe_lock);\n+\n+\treturn 0;\n+}\n+\n+void __mtk_ppe_check_skb(struct mtk_ppe *ppe, struct sk_buff *skb, u16 hash)\n+{\n+\tstruct hlist_head *head = &ppe->foe_flow[hash / 2];\n+\tstruct mtk_flow_entry *entry;\n+\tstruct mtk_foe_entry *hwe = &ppe->foe_table[hash];\n+\tbool found = false;\n+\n+\tif (hlist_empty(head))\n+\t\treturn;\n+\n+\tspin_lock_bh(&ppe_lock);\n+\thlist_for_each_entry(entry, head, list) {\n+\t\tif (found || !mtk_flow_entry_match(entry, hwe)) {\n+\t\t\tif (entry->hash != 0xffff)\n+\t\t\t\tentry->hash = 0xffff;\n+\t\t\tcontinue;\n+\t\t}\n+\n+\t\tentry->hash = hash;\n+\t\t__mtk_foe_entry_commit(ppe, &entry->data, hash);\n+\t\tfound = true;\n+\t}\n+\tspin_unlock_bh(&ppe_lock);\n+}\n+\n+int mtk_foe_entry_idle_time(struct mtk_ppe *ppe, struct mtk_flow_entry *entry)\n+{\n+\tu16 now = mtk_eth_timestamp(ppe->eth) & MTK_FOE_IB1_BIND_TIMESTAMP;\n+\tu16 timestamp;\n+\n+\tmtk_flow_entry_update(ppe, entry);\n+\ttimestamp = entry->data.ib1 & MTK_FOE_IB1_BIND_TIMESTAMP;\n+\n+\tif (timestamp > now)\n+\t\treturn MTK_FOE_IB1_BIND_TIMESTAMP + 1 - timestamp + now;\n+\telse\n+\t\treturn now - timestamp;\n }\n \n-struct mtk_ppe *mtk_ppe_init(struct device *dev, void __iomem *base,\n+struct mtk_ppe *mtk_ppe_init(struct mtk_eth *eth, void __iomem *base,\n \t\t int version)\n {\n+\tstruct device *dev = eth->dev;\n \tstruct mtk_foe_entry *foe;\n \tstruct mtk_ppe *ppe;\n \n@@ -398,6 +503,7 @@ struct mtk_ppe *mtk_ppe_init(struct devi\n \t * not coherent.\n \t */\n \tppe->base = base;\n+\tppe->eth = eth;\n \tppe->dev = dev;\n \tppe->version = version;\n \n--- a/drivers/net/ethernet/mediatek/mtk_ppe.h\n+++ b/drivers/net/ethernet/mediatek/mtk_ppe.h\n@@ -235,7 +235,17 @@ enum {\n \tMTK_PPE_CPU_REASON_INVALID\t\t\t= 0x1f,\n };\n \n+struct mtk_flow_entry {\n+\tstruct rhash_head node;\n+\tstruct hlist_node list;\n+\tunsigned long cookie;\n+\tstruct mtk_foe_entry data;\n+\tu16 hash;\n+\ts8 wed_index;\n+};\n+\n struct mtk_ppe {\n+\tstruct mtk_eth *eth;\n \tstruct device *dev;\n \tvoid __iomem *base;\n \tint version;\n@@ -243,18 +253,33 @@ struct mtk_ppe {\n \tstruct mtk_foe_entry *foe_table;\n \tdma_addr_t foe_phys;\n \n+\tu16 foe_check_time[MTK_PPE_ENTRIES];\n+\tstruct hlist_head foe_flow[MTK_PPE_ENTRIES / 2];\n+\n \tvoid *acct_table;\n };\n \n-struct mtk_ppe *mtk_ppe_init(struct device *dev, void __iomem *base, int version);\n+struct mtk_ppe *mtk_ppe_init(struct mtk_eth *eth, void __iomem *base, int version);\n int mtk_ppe_start(struct mtk_ppe *ppe);\n int mtk_ppe_stop(struct mtk_ppe *ppe);\n \n+void __mtk_ppe_check_skb(struct mtk_ppe *ppe, struct sk_buff *skb, u16 hash);\n+\n static inline void\n-mtk_foe_entry_clear(struct mtk_ppe *ppe, u16 hash)\n+mtk_ppe_check_skb(struct mtk_ppe *ppe, struct sk_buff *skb, u16 hash)\n {\n-\tppe->foe_table[hash].ib1 = 0;\n-\tdma_wmb();\n+\tu16 now, diff;\n+\n+\tif (!ppe)\n+\t\treturn;\n+\n+\tnow = (u16)jiffies;\n+\tdiff = now - ppe->foe_check_time[hash];\n+\tif (diff < HZ / 10)\n+\t\treturn;\n+\n+\tppe->foe_check_time[hash] = now;\n+\t__mtk_ppe_check_skb(ppe, skb, hash);\n }\n \n static inline int\n@@ -282,8 +307,9 @@ int mtk_foe_entry_set_vlan(struct mtk_fo\n int mtk_foe_entry_set_pppoe(struct mtk_foe_entry *entry, int sid);\n int mtk_foe_entry_set_wdma(struct mtk_foe_entry *entry, int wdma_idx, int txq,\n \t\t\t   int bss, int wcid);\n-int mtk_foe_entry_commit(struct mtk_ppe *ppe, struct mtk_foe_entry *entry,\n-\t\t\t u16 timestamp);\n+int mtk_foe_entry_commit(struct mtk_ppe *ppe, struct mtk_flow_entry *entry);\n+void mtk_foe_entry_clear(struct mtk_ppe *ppe, struct mtk_flow_entry *entry);\n+int mtk_foe_entry_idle_time(struct mtk_ppe *ppe, struct mtk_flow_entry *entry);\n int mtk_ppe_debugfs_init(struct mtk_ppe *ppe);\n \n #endif\n--- a/drivers/net/ethernet/mediatek/mtk_ppe_offload.c\n+++ b/drivers/net/ethernet/mediatek/mtk_ppe_offload.c\n@@ -43,13 +43,6 @@ struct mtk_flow_data {\n \t} pppoe;\n };\n \n-struct mtk_flow_entry {\n-\tstruct rhash_head node;\n-\tunsigned long cookie;\n-\tu16 hash;\n-\ts8 wed_index;\n-};\n-\n static const struct rhashtable_params mtk_flow_ht_params = {\n \t.head_offset = offsetof(struct mtk_flow_entry, node),\n \t.key_offset = offsetof(struct mtk_flow_entry, cookie),\n@@ -57,12 +50,6 @@ static const struct rhashtable_params mt\n \t.automatic_shrinking = true,\n };\n \n-static u32\n-mtk_eth_timestamp(struct mtk_eth *eth)\n-{\n-\treturn mtk_r32(eth, 0x0010) & MTK_FOE_IB1_BIND_TIMESTAMP;\n-}\n-\n static int\n mtk_flow_set_ipv4_addr(struct mtk_foe_entry *foe, struct mtk_flow_data *data,\n \t\t       bool egress)\n@@ -238,10 +225,8 @@ mtk_flow_offload_replace(struct mtk_eth\n \tint offload_type = 0;\n \tint wed_index = -1;\n \tu16 addr_type = 0;\n-\tu32 timestamp;\n \tu8 l4proto = 0;\n \tint err = 0;\n-\tint hash;\n \tint i;\n \n \tif (rhashtable_lookup(&eth->flow_table, &f->cookie, mtk_flow_ht_params))\n@@ -411,23 +396,21 @@ mtk_flow_offload_replace(struct mtk_eth\n \t\treturn -ENOMEM;\n \n \tentry->cookie = f->cookie;\n-\ttimestamp = mtk_eth_timestamp(eth);\n-\thash = mtk_foe_entry_commit(eth->ppe, &foe, timestamp);\n-\tif (hash < 0) {\n-\t\terr = hash;\n+\tmemcpy(&entry->data, &foe, sizeof(entry->data));\n+\tentry->wed_index = wed_index;\n+\n+\tif (mtk_foe_entry_commit(eth->ppe, entry) < 0)\n \t\tgoto free;\n-\t}\n \n-\tentry->hash = hash;\n-\tentry->wed_index = wed_index;\n \terr = rhashtable_insert_fast(&eth->flow_table, &entry->node,\n \t\t\t\t     mtk_flow_ht_params);\n \tif (err < 0)\n-\t\tgoto clear_flow;\n+\t\tgoto clear;\n \n \treturn 0;\n-clear_flow:\n-\tmtk_foe_entry_clear(eth->ppe, hash);\n+\n+clear:\n+\tmtk_foe_entry_clear(eth->ppe, entry);\n free:\n \tkfree(entry);\n \tif (wed_index >= 0)\n@@ -445,7 +428,7 @@ mtk_flow_offload_destroy(struct mtk_eth\n \tif (!entry)\n \t\treturn -ENOENT;\n \n-\tmtk_foe_entry_clear(eth->ppe, entry->hash);\n+\tmtk_foe_entry_clear(eth->ppe, entry);\n \trhashtable_remove_fast(&eth->flow_table, &entry->node,\n \t\t\t       mtk_flow_ht_params);\n \tif (entry->wed_index >= 0)\n@@ -459,7 +442,6 @@ static int\n mtk_flow_offload_stats(struct mtk_eth *eth, struct flow_cls_offload *f)\n {\n \tstruct mtk_flow_entry *entry;\n-\tint timestamp;\n \tu32 idle;\n \n \tentry = rhashtable_lookup(&eth->flow_table, &f->cookie,\n@@ -467,11 +449,7 @@ mtk_flow_offload_stats(struct mtk_eth *e\n \tif (!entry)\n \t\treturn -ENOENT;\n \n-\ttimestamp = mtk_foe_entry_timestamp(eth->ppe, entry->hash);\n-\tif (timestamp < 0)\n-\t\treturn -ETIMEDOUT;\n-\n-\tidle = mtk_eth_timestamp(eth) - timestamp;\n+\tidle = mtk_foe_entry_idle_time(eth->ppe, entry);\n \tf->stats.lastused = jiffies - idle * HZ;\n \n \treturn 0;\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/701-09-net-ethernet-mtk_eth_soc-remove-bridge-flow-offload-.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nDate: Mon, 21 Feb 2022 15:55:19 +0100\nSubject: [PATCH] net: ethernet: mtk_eth_soc: remove bridge flow offload\n type entry support\n\nAccording to MediaTek, this feature is not supported in current hardware\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n\n--- a/drivers/net/ethernet/mediatek/mtk_ppe.c\n+++ b/drivers/net/ethernet/mediatek/mtk_ppe.c\n@@ -84,13 +84,6 @@ static u32 mtk_ppe_hash_entry(struct mtk\n \tu32 hash;\n \n \tswitch (FIELD_GET(MTK_FOE_IB1_PACKET_TYPE, e->ib1)) {\n-\t\tcase MTK_PPE_PKT_TYPE_BRIDGE:\n-\t\t\thv1 = e->bridge.src_mac_lo;\n-\t\t\thv1 ^= ((e->bridge.src_mac_hi & 0xffff) << 16);\n-\t\t\thv2 = e->bridge.src_mac_hi >> 16;\n-\t\t\thv2 ^= e->bridge.dest_mac_lo;\n-\t\t\thv3 = e->bridge.dest_mac_hi;\n-\t\t\tbreak;\n \t\tcase MTK_PPE_PKT_TYPE_IPV4_ROUTE:\n \t\tcase MTK_PPE_PKT_TYPE_IPV4_HNAPT:\n \t\t\thv1 = e->ipv4.orig.ports;\n@@ -572,7 +565,6 @@ int mtk_ppe_start(struct mtk_ppe *ppe)\n \t      MTK_PPE_FLOW_CFG_IP4_NAT |\n \t      MTK_PPE_FLOW_CFG_IP4_NAPT |\n \t      MTK_PPE_FLOW_CFG_IP4_DSLITE |\n-\t      MTK_PPE_FLOW_CFG_L2_BRIDGE |\n \t      MTK_PPE_FLOW_CFG_IP4_NAT_FRAG;\n \tppe_w32(ppe, MTK_PPE_FLOW_CFG, val);\n \n--- a/drivers/net/ethernet/mediatek/mtk_ppe_debugfs.c\n+++ b/drivers/net/ethernet/mediatek/mtk_ppe_debugfs.c\n@@ -32,7 +32,6 @@ static const char *mtk_foe_pkt_type_str(\n \tstatic const char * const type_str[] = {\n \t\t[MTK_PPE_PKT_TYPE_IPV4_HNAPT] = \"IPv4 5T\",\n \t\t[MTK_PPE_PKT_TYPE_IPV4_ROUTE] = \"IPv4 3T\",\n-\t\t[MTK_PPE_PKT_TYPE_BRIDGE] = \"L2\",\n \t\t[MTK_PPE_PKT_TYPE_IPV4_DSLITE] = \"DS-LITE\",\n \t\t[MTK_PPE_PKT_TYPE_IPV6_ROUTE_3T] = \"IPv6 3T\",\n \t\t[MTK_PPE_PKT_TYPE_IPV6_ROUTE_5T] = \"IPv6 5T\",\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/701-10-net-ethernet-mtk_eth_soc-support-creating-mac-addres.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nDate: Wed, 23 Feb 2022 10:56:34 +0100\nSubject: [PATCH] net: ethernet: mtk_eth_soc: support creating mac\n address based offload entries\n\nThis will be used to implement a limited form of bridge offloading.\nSince the hardware does not support flow table entries with just source\nand destination MAC address, the driver has to emulate it.\n\nThe hardware automatically creates entries entries for incoming flows, even\nwhen they are bridged instead of routed, and reports when packets for these\nflows have reached the minimum PPS rate for offloading.\n\nAfter this happens, we look up the L2 flow offload entry based on the MAC\nheader and fill in the output routing information in the flow table.\nThe dynamically created per-flow entries are automatically removed when\neither the hardware flowtable entry expires, is replaced, or if the offload\nrule they belong to is removed\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n\n--- a/drivers/net/ethernet/mediatek/mtk_ppe.c\n+++ b/drivers/net/ethernet/mediatek/mtk_ppe.c\n@@ -6,12 +6,22 @@\n #include <linux/iopoll.h>\n #include <linux/etherdevice.h>\n #include <linux/platform_device.h>\n+#include <linux/if_ether.h>\n+#include <linux/if_vlan.h>\n+#include <net/dsa.h>\n #include \"mtk_eth_soc.h\"\n #include \"mtk_ppe.h\"\n #include \"mtk_ppe_regs.h\"\n \n static DEFINE_SPINLOCK(ppe_lock);\n \n+static const struct rhashtable_params mtk_flow_l2_ht_params = {\n+\t.head_offset = offsetof(struct mtk_flow_entry, l2_node),\n+\t.key_offset = offsetof(struct mtk_flow_entry, data.bridge),\n+\t.key_len = offsetof(struct mtk_foe_bridge, key_end),\n+\t.automatic_shrinking = true,\n+};\n+\n static void ppe_w32(struct mtk_ppe *ppe, u32 reg, u32 val)\n {\n \twritel(val, ppe->base + reg);\n@@ -123,6 +133,9 @@ mtk_foe_entry_l2(struct mtk_foe_entry *e\n {\n \tint type = FIELD_GET(MTK_FOE_IB1_PACKET_TYPE, entry->ib1);\n \n+\tif (type == MTK_PPE_PKT_TYPE_BRIDGE)\n+\t\treturn &entry->bridge.l2;\n+\n \tif (type >= MTK_PPE_PKT_TYPE_IPV4_DSLITE)\n \t\treturn &entry->ipv6.l2;\n \n@@ -134,6 +147,9 @@ mtk_foe_entry_ib2(struct mtk_foe_entry *\n {\n \tint type = FIELD_GET(MTK_FOE_IB1_PACKET_TYPE, entry->ib1);\n \n+\tif (type == MTK_PPE_PKT_TYPE_BRIDGE)\n+\t\treturn &entry->bridge.ib2;\n+\n \tif (type >= MTK_PPE_PKT_TYPE_IPV4_DSLITE)\n \t\treturn &entry->ipv6.ib2;\n \n@@ -168,7 +184,12 @@ int mtk_foe_entry_prepare(struct mtk_foe\n \tif (type == MTK_PPE_PKT_TYPE_IPV6_ROUTE_3T)\n \t\tentry->ipv6.ports = ports_pad;\n \n-\tif (type >= MTK_PPE_PKT_TYPE_IPV4_DSLITE) {\n+\tif (type == MTK_PPE_PKT_TYPE_BRIDGE) {\n+\t\tether_addr_copy(entry->bridge.src_mac, src_mac);\n+\t\tether_addr_copy(entry->bridge.dest_mac, dest_mac);\n+\t\tentry->bridge.ib2 = val;\n+\t\tl2 = &entry->bridge.l2;\n+\t} else if (type >= MTK_PPE_PKT_TYPE_IPV4_DSLITE) {\n \t\tentry->ipv6.ib2 = val;\n \t\tl2 = &entry->ipv6.l2;\n \t} else {\n@@ -372,12 +393,96 @@ mtk_flow_entry_match(struct mtk_flow_ent\n }\n \n static void\n+__mtk_foe_entry_clear(struct mtk_ppe *ppe, struct mtk_flow_entry *entry)\n+{\n+\tstruct hlist_head *head;\n+\tstruct hlist_node *tmp;\n+\n+\tif (entry->type == MTK_FLOW_TYPE_L2) {\n+\t\trhashtable_remove_fast(&ppe->l2_flows, &entry->l2_node,\n+\t\t\t\t       mtk_flow_l2_ht_params);\n+\n+\t\thead = &entry->l2_flows;\n+\t\thlist_for_each_entry_safe(entry, tmp, head, l2_data.list)\n+\t\t\t__mtk_foe_entry_clear(ppe, entry);\n+\t\treturn;\n+\t}\n+\n+\thlist_del_init(&entry->list);\n+\tif (entry->hash != 0xffff) {\n+\t\tppe->foe_table[entry->hash].ib1 &= ~MTK_FOE_IB1_STATE;\n+\t\tppe->foe_table[entry->hash].ib1 |= FIELD_PREP(MTK_FOE_IB1_STATE,\n+\t\t\t\t\t\t\t      MTK_FOE_STATE_BIND);\n+\t\tdma_wmb();\n+\t}\n+\tentry->hash = 0xffff;\n+\n+\tif (entry->type != MTK_FLOW_TYPE_L2_SUBFLOW)\n+\t\treturn;\n+\n+\thlist_del_init(&entry->l2_data.list);\n+\tkfree(entry);\n+}\n+\n+static int __mtk_foe_entry_idle_time(struct mtk_ppe *ppe, u32 ib1)\n+{\n+\tu16 timestamp;\n+\tu16 now;\n+\n+\tnow = mtk_eth_timestamp(ppe->eth) & MTK_FOE_IB1_BIND_TIMESTAMP;\n+\ttimestamp = ib1 & MTK_FOE_IB1_BIND_TIMESTAMP;\n+\n+\tif (timestamp > now)\n+\t\treturn MTK_FOE_IB1_BIND_TIMESTAMP + 1 - timestamp + now;\n+\telse\n+\t\treturn now - timestamp;\n+}\n+\n+static void\n+mtk_flow_entry_update_l2(struct mtk_ppe *ppe, struct mtk_flow_entry *entry)\n+{\n+\tstruct mtk_flow_entry *cur;\n+\tstruct mtk_foe_entry *hwe;\n+\tstruct hlist_node *tmp;\n+\tint idle;\n+\n+\tidle = __mtk_foe_entry_idle_time(ppe, entry->data.ib1);\n+\thlist_for_each_entry_safe(cur, tmp, &entry->l2_flows, l2_data.list) {\n+\t\tint cur_idle;\n+\t\tu32 ib1;\n+\n+\t\thwe = &ppe->foe_table[cur->hash];\n+\t\tib1 = READ_ONCE(hwe->ib1);\n+\n+\t\tif (FIELD_GET(MTK_FOE_IB1_STATE, ib1) != MTK_FOE_STATE_BIND) {\n+\t\t\tcur->hash = 0xffff;\n+\t\t\t__mtk_foe_entry_clear(ppe, cur);\n+\t\t\tcontinue;\n+\t\t}\n+\n+\t\tcur_idle = __mtk_foe_entry_idle_time(ppe, ib1);\n+\t\tif (cur_idle >= idle)\n+\t\t\tcontinue;\n+\n+\t\tidle = cur_idle;\n+\t\tentry->data.ib1 &= ~MTK_FOE_IB1_BIND_TIMESTAMP;\n+\t\tentry->data.ib1 |= hwe->ib1 & MTK_FOE_IB1_BIND_TIMESTAMP;\n+\t}\n+}\n+\n+static void\n mtk_flow_entry_update(struct mtk_ppe *ppe, struct mtk_flow_entry *entry)\n {\n \tstruct mtk_foe_entry *hwe;\n \tstruct mtk_foe_entry foe;\n \n \tspin_lock_bh(&ppe_lock);\n+\n+\tif (entry->type == MTK_FLOW_TYPE_L2) {\n+\t\tmtk_flow_entry_update_l2(ppe, entry);\n+\t\tgoto out;\n+\t}\n+\n \tif (entry->hash == 0xffff)\n \t\tgoto out;\n \n@@ -419,21 +524,28 @@ __mtk_foe_entry_commit(struct mtk_ppe *p\n void mtk_foe_entry_clear(struct mtk_ppe *ppe, struct mtk_flow_entry *entry)\n {\n \tspin_lock_bh(&ppe_lock);\n-\thlist_del_init(&entry->list);\n-\tif (entry->hash != 0xffff) {\n-\t\tppe->foe_table[entry->hash].ib1 &= ~MTK_FOE_IB1_STATE;\n-\t\tppe->foe_table[entry->hash].ib1 |= FIELD_PREP(MTK_FOE_IB1_STATE,\n-\t\t\t\t\t\t\t      MTK_FOE_STATE_BIND);\n-\t\tdma_wmb();\n-\t}\n-\tentry->hash = 0xffff;\n+\t__mtk_foe_entry_clear(ppe, entry);\n \tspin_unlock_bh(&ppe_lock);\n }\n \n+static int\n+mtk_foe_entry_commit_l2(struct mtk_ppe *ppe, struct mtk_flow_entry *entry)\n+{\n+\tentry->type = MTK_FLOW_TYPE_L2;\n+\n+\treturn rhashtable_insert_fast(&ppe->l2_flows, &entry->l2_node,\n+\t\t\t\t      mtk_flow_l2_ht_params);\n+}\n+\n int mtk_foe_entry_commit(struct mtk_ppe *ppe, struct mtk_flow_entry *entry)\n {\n-\tu32 hash = mtk_ppe_hash_entry(&entry->data);\n+\tint type = FIELD_GET(MTK_FOE_IB1_PACKET_TYPE, entry->data.ib1);\n+\tu32 hash;\n+\n+\tif (type == MTK_PPE_PKT_TYPE_BRIDGE)\n+\t\treturn mtk_foe_entry_commit_l2(ppe, entry);\n \n+\thash = mtk_ppe_hash_entry(&entry->data);\n \tentry->hash = 0xffff;\n \tspin_lock_bh(&ppe_lock);\n \thlist_add_head(&entry->list, &ppe->foe_flow[hash / 2]);\n@@ -442,18 +554,72 @@ int mtk_foe_entry_commit(struct mtk_ppe\n \treturn 0;\n }\n \n+static void\n+mtk_foe_entry_commit_subflow(struct mtk_ppe *ppe, struct mtk_flow_entry *entry,\n+\t\t\t     u16 hash)\n+{\n+\tstruct mtk_flow_entry *flow_info;\n+\tstruct mtk_foe_entry foe, *hwe;\n+\tstruct mtk_foe_mac_info *l2;\n+\tu32 ib1_mask = MTK_FOE_IB1_PACKET_TYPE | MTK_FOE_IB1_UDP;\n+\tint type;\n+\n+\tflow_info = kzalloc(offsetof(struct mtk_flow_entry, l2_data.end),\n+\t\t\t    GFP_ATOMIC);\n+\tif (!flow_info)\n+\t\treturn;\n+\n+\tflow_info->l2_data.base_flow = entry;\n+\tflow_info->type = MTK_FLOW_TYPE_L2_SUBFLOW;\n+\tflow_info->hash = hash;\n+\thlist_add_head(&flow_info->list, &ppe->foe_flow[hash / 2]);\n+\thlist_add_head(&flow_info->l2_data.list, &entry->l2_flows);\n+\n+\thwe = &ppe->foe_table[hash];\n+\tmemcpy(&foe, hwe, sizeof(foe));\n+\tfoe.ib1 &= ib1_mask;\n+\tfoe.ib1 |= entry->data.ib1 & ~ib1_mask;\n+\n+\tl2 = mtk_foe_entry_l2(&foe);\n+\tmemcpy(l2, &entry->data.bridge.l2, sizeof(*l2));\n+\n+\ttype = FIELD_GET(MTK_FOE_IB1_PACKET_TYPE, foe.ib1);\n+\tif (type == MTK_PPE_PKT_TYPE_IPV4_HNAPT)\n+\t\tmemcpy(&foe.ipv4.new, &foe.ipv4.orig, sizeof(foe.ipv4.new));\n+\telse if (type >= MTK_PPE_PKT_TYPE_IPV6_ROUTE_3T && l2->etype == ETH_P_IP)\n+\t\tl2->etype = ETH_P_IPV6;\n+\n+\t*mtk_foe_entry_ib2(&foe) = entry->data.bridge.ib2;\n+\n+\t__mtk_foe_entry_commit(ppe, &foe, hash);\n+}\n+\n void __mtk_ppe_check_skb(struct mtk_ppe *ppe, struct sk_buff *skb, u16 hash)\n {\n \tstruct hlist_head *head = &ppe->foe_flow[hash / 2];\n-\tstruct mtk_flow_entry *entry;\n \tstruct mtk_foe_entry *hwe = &ppe->foe_table[hash];\n+\tstruct mtk_flow_entry *entry;\n+\tstruct mtk_foe_bridge key = {};\n+\tstruct ethhdr *eh;\n \tbool found = false;\n-\n-\tif (hlist_empty(head))\n-\t\treturn;\n+\tu8 *tag;\n \n \tspin_lock_bh(&ppe_lock);\n+\n+\tif (FIELD_GET(MTK_FOE_IB1_STATE, hwe->ib1) == MTK_FOE_STATE_BIND)\n+\t\tgoto out;\n+\n \thlist_for_each_entry(entry, head, list) {\n+\t\tif (entry->type == MTK_FLOW_TYPE_L2_SUBFLOW) {\n+\t\t\tif (unlikely(FIELD_GET(MTK_FOE_IB1_STATE, hwe->ib1) ==\n+\t\t\t\t     MTK_FOE_STATE_BIND))\n+\t\t\t\tcontinue;\n+\n+\t\t\tentry->hash = 0xffff;\n+\t\t\t__mtk_foe_entry_clear(ppe, entry);\n+\t\t\tcontinue;\n+\t\t}\n+\n \t\tif (found || !mtk_flow_entry_match(entry, hwe)) {\n \t\t\tif (entry->hash != 0xffff)\n \t\t\t\tentry->hash = 0xffff;\n@@ -464,21 +630,50 @@ void __mtk_ppe_check_skb(struct mtk_ppe\n \t\t__mtk_foe_entry_commit(ppe, &entry->data, hash);\n \t\tfound = true;\n \t}\n+\n+\tif (found)\n+\t\tgoto out;\n+\n+\teh = eth_hdr(skb);\n+\tether_addr_copy(key.dest_mac, eh->h_dest);\n+\tether_addr_copy(key.src_mac, eh->h_source);\n+\ttag = skb->data - 2;\n+\tkey.vlan = 0;\n+\tswitch (skb->protocol) {\n+#if IS_ENABLED(CONFIG_NET_DSA)\n+\tcase htons(ETH_P_XDSA):\n+\t\tif (!netdev_uses_dsa(skb->dev) ||\n+\t\t    skb->dev->dsa_ptr->tag_ops->proto != DSA_TAG_PROTO_MTK)\n+\t\t\tgoto out;\n+\n+\t\ttag += 4;\n+\t\tif (get_unaligned_be16(tag) != ETH_P_8021Q)\n+\t\t\tbreak;\n+\n+\t\tfallthrough;\n+#endif\n+\tcase htons(ETH_P_8021Q):\n+\t\tkey.vlan = get_unaligned_be16(tag + 2) & VLAN_VID_MASK;\n+\t\tbreak;\n+\tdefault:\n+\t\tbreak;\n+\t}\n+\n+\tentry = rhashtable_lookup_fast(&ppe->l2_flows, &key, mtk_flow_l2_ht_params);\n+\tif (!entry)\n+\t\tgoto out;\n+\n+\tmtk_foe_entry_commit_subflow(ppe, entry, hash);\n+\n+out:\n \tspin_unlock_bh(&ppe_lock);\n }\n \n int mtk_foe_entry_idle_time(struct mtk_ppe *ppe, struct mtk_flow_entry *entry)\n {\n-\tu16 now = mtk_eth_timestamp(ppe->eth) & MTK_FOE_IB1_BIND_TIMESTAMP;\n-\tu16 timestamp;\n-\n \tmtk_flow_entry_update(ppe, entry);\n-\ttimestamp = entry->data.ib1 & MTK_FOE_IB1_BIND_TIMESTAMP;\n \n-\tif (timestamp > now)\n-\t\treturn MTK_FOE_IB1_BIND_TIMESTAMP + 1 - timestamp + now;\n-\telse\n-\t\treturn now - timestamp;\n+\treturn __mtk_foe_entry_idle_time(ppe, entry->data.ib1);\n }\n \n struct mtk_ppe *mtk_ppe_init(struct mtk_eth *eth, void __iomem *base,\n@@ -492,6 +687,8 @@ struct mtk_ppe *mtk_ppe_init(struct mtk_\n \tif (!ppe)\n \t\treturn NULL;\n \n+\trhashtable_init(&ppe->l2_flows, &mtk_flow_l2_ht_params);\n+\n \t/* need to allocate a separate device, since it PPE DMA access is\n \t * not coherent.\n \t */\n--- a/drivers/net/ethernet/mediatek/mtk_ppe.h\n+++ b/drivers/net/ethernet/mediatek/mtk_ppe.h\n@@ -6,6 +6,7 @@\n \n #include <linux/kernel.h>\n #include <linux/bitfield.h>\n+#include <linux/rhashtable.h>\n \n #define MTK_ETH_PPE_BASE\t\t0xc00\n \n@@ -84,19 +85,16 @@ struct mtk_foe_mac_info {\n \tu16 src_mac_lo;\n };\n \n+/* software-only entry type */\n struct mtk_foe_bridge {\n-\tu32 dest_mac_hi;\n-\n-\tu16 src_mac_lo;\n-\tu16 dest_mac_lo;\n+\tu8 dest_mac[ETH_ALEN];\n+\tu8 src_mac[ETH_ALEN];\n+\tu16 vlan;\n \n-\tu32 src_mac_hi;\n+\tstruct {} key_end;\n \n \tu32 ib2;\n \n-\tu32 _rsv[5];\n-\n-\tu32 udf_tsid;\n \tstruct mtk_foe_mac_info l2;\n };\n \n@@ -235,13 +233,33 @@ enum {\n \tMTK_PPE_CPU_REASON_INVALID\t\t\t= 0x1f,\n };\n \n+enum {\n+\tMTK_FLOW_TYPE_L4,\n+\tMTK_FLOW_TYPE_L2,\n+\tMTK_FLOW_TYPE_L2_SUBFLOW,\n+};\n+\n struct mtk_flow_entry {\n+\tunion {\n+\t\tstruct hlist_node list;\n+\t\tstruct {\n+\t\t\tstruct rhash_head l2_node;\n+\t\t\tstruct hlist_head l2_flows;\n+\t\t};\n+\t};\n+\tu8 type;\n+\ts8 wed_index;\n+\tu16 hash;\n+\tunion {\n+\t\tstruct mtk_foe_entry data;\n+\t\tstruct {\n+\t\t\tstruct mtk_flow_entry *base_flow;\n+\t\t\tstruct hlist_node list;\n+\t\t\tstruct {} end;\n+\t\t} l2_data;\n+\t};\n \tstruct rhash_head node;\n-\tstruct hlist_node list;\n \tunsigned long cookie;\n-\tstruct mtk_foe_entry data;\n-\tu16 hash;\n-\ts8 wed_index;\n };\n \n struct mtk_ppe {\n@@ -256,6 +274,8 @@ struct mtk_ppe {\n \tu16 foe_check_time[MTK_PPE_ENTRIES];\n \tstruct hlist_head foe_flow[MTK_PPE_ENTRIES / 2];\n \n+\tstruct rhashtable l2_flows;\n+\n \tvoid *acct_table;\n };\n \n--- a/drivers/net/ethernet/mediatek/mtk_ppe_offload.c\n+++ b/drivers/net/ethernet/mediatek/mtk_ppe_offload.c\n@@ -32,6 +32,8 @@ struct mtk_flow_data {\n \t__be16 src_port;\n \t__be16 dst_port;\n \n+\tu16 vlan_in;\n+\n \tstruct {\n \t\tu16 id;\n \t\t__be16 proto;\n@@ -258,9 +260,45 @@ mtk_flow_offload_replace(struct mtk_eth\n \t\treturn -EOPNOTSUPP;\n \t}\n \n+\tswitch (addr_type) {\n+\tcase 0:\n+\t\toffload_type = MTK_PPE_PKT_TYPE_BRIDGE;\n+\t\tif (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) {\n+\t\t\tstruct flow_match_eth_addrs match;\n+\n+\t\t\tflow_rule_match_eth_addrs(rule, &match);\n+\t\t\tmemcpy(data.eth.h_dest, match.key->dst, ETH_ALEN);\n+\t\t\tmemcpy(data.eth.h_source, match.key->src, ETH_ALEN);\n+\t\t} else {\n+\t\t\treturn -EOPNOTSUPP;\n+\t\t}\n+\n+\t\tif (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN)) {\n+\t\t\tstruct flow_match_vlan match;\n+\n+\t\t\tflow_rule_match_vlan(rule, &match);\n+\n+\t\t\tif (match.key->vlan_tpid != cpu_to_be16(ETH_P_8021Q))\n+\t\t\t\treturn -EOPNOTSUPP;\n+\n+\t\t\tdata.vlan_in = match.key->vlan_id;\n+\t\t}\n+\t\tbreak;\n+\tcase FLOW_DISSECTOR_KEY_IPV4_ADDRS:\n+\t\toffload_type = MTK_PPE_PKT_TYPE_IPV4_HNAPT;\n+\t\tbreak;\n+\tcase FLOW_DISSECTOR_KEY_IPV6_ADDRS:\n+\t\toffload_type = MTK_PPE_PKT_TYPE_IPV6_ROUTE_5T;\n+\t\tbreak;\n+\tdefault:\n+\t\treturn -EOPNOTSUPP;\n+\t}\n+\n \tflow_action_for_each(i, act, &rule->action) {\n \t\tswitch (act->id) {\n \t\tcase FLOW_ACTION_MANGLE:\n+\t\t\tif (offload_type == MTK_PPE_PKT_TYPE_BRIDGE)\n+\t\t\t\treturn -EOPNOTSUPP;\n \t\t\tif (act->mangle.htype == FLOW_ACT_MANGLE_HDR_TYPE_ETH)\n \t\t\t\tmtk_flow_offload_mangle_eth(act, &data.eth);\n \t\t\tbreak;\n@@ -292,17 +330,6 @@ mtk_flow_offload_replace(struct mtk_eth\n \t\t}\n \t}\n \n-\tswitch (addr_type) {\n-\tcase FLOW_DISSECTOR_KEY_IPV4_ADDRS:\n-\t\toffload_type = MTK_PPE_PKT_TYPE_IPV4_HNAPT;\n-\t\tbreak;\n-\tcase FLOW_DISSECTOR_KEY_IPV6_ADDRS:\n-\t\toffload_type = MTK_PPE_PKT_TYPE_IPV6_ROUTE_5T;\n-\t\tbreak;\n-\tdefault:\n-\t\treturn -EOPNOTSUPP;\n-\t}\n-\n \tif (!is_valid_ether_addr(data.eth.h_source) ||\n \t    !is_valid_ether_addr(data.eth.h_dest))\n \t\treturn -EINVAL;\n@@ -316,10 +343,13 @@ mtk_flow_offload_replace(struct mtk_eth\n \tif (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_PORTS)) {\n \t\tstruct flow_match_ports ports;\n \n+\t\tif (offload_type == MTK_PPE_PKT_TYPE_BRIDGE)\n+\t\t\treturn -EOPNOTSUPP;\n+\n \t\tflow_rule_match_ports(rule, &ports);\n \t\tdata.src_port = ports.key->src;\n \t\tdata.dst_port = ports.key->dst;\n-\t} else {\n+\t} else if (offload_type != MTK_PPE_PKT_TYPE_BRIDGE) {\n \t\treturn -EOPNOTSUPP;\n \t}\n \n@@ -349,6 +379,9 @@ mtk_flow_offload_replace(struct mtk_eth\n \t\tif (act->id != FLOW_ACTION_MANGLE)\n \t\t\tcontinue;\n \n+\t\tif (offload_type == MTK_PPE_PKT_TYPE_BRIDGE)\n+\t\t\treturn -EOPNOTSUPP;\n+\n \t\tswitch (act->mangle.htype) {\n \t\tcase FLOW_ACT_MANGLE_HDR_TYPE_TCP:\n \t\tcase FLOW_ACT_MANGLE_HDR_TYPE_UDP:\n@@ -374,6 +407,9 @@ mtk_flow_offload_replace(struct mtk_eth\n \t\t\treturn err;\n \t}\n \n+\tif (offload_type == MTK_PPE_PKT_TYPE_BRIDGE)\n+\t\tfoe.bridge.vlan = data.vlan_in;\n+\n \tif (data.vlan.num == 1) {\n \t\tif (data.vlan.proto != htons(ETH_P_8021Q))\n \t\t\treturn -EOPNOTSUPP;\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/702-net-ethernet-mtk_eth_soc-enable-threaded-NAPI.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nDate: Mon, 21 Mar 2022 20:39:59 +0100\nSubject: [PATCH] net: ethernet: mtk_eth_soc: enable threaded NAPI\n\nThis can improve performance under load by ensuring that NAPI processing is\nnot pinned on CPU 0.\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n\n--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c\n+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c\n@@ -2179,8 +2179,8 @@ static irqreturn_t mtk_handle_irq_rx(int\n \n \teth->rx_events++;\n \tif (likely(napi_schedule_prep(&eth->rx_napi))) {\n-\t\t__napi_schedule(&eth->rx_napi);\n \t\tmtk_rx_irq_disable(eth, MTK_RX_DONE_INT);\n+\t\t__napi_schedule(&eth->rx_napi);\n \t}\n \n \treturn IRQ_HANDLED;\n@@ -2192,8 +2192,8 @@ static irqreturn_t mtk_handle_irq_tx(int\n \n \teth->tx_events++;\n \tif (likely(napi_schedule_prep(&eth->tx_napi))) {\n-\t\t__napi_schedule(&eth->tx_napi);\n \t\tmtk_tx_irq_disable(eth, MTK_TX_DONE_INT);\n+\t\t__napi_schedule(&eth->tx_napi);\n \t}\n \n \treturn IRQ_HANDLED;\n@@ -3300,6 +3300,8 @@ static int mtk_probe(struct platform_dev\n \t * for NAPI to work\n \t */\n \tinit_dummy_netdev(&eth->dummy_dev);\n+\teth->dummy_dev.threaded = 1;\n+\tstrcpy(eth->dummy_dev.name, \"mtk_eth\");\n \tnetif_napi_add(&eth->dummy_dev, &eth->tx_napi, mtk_napi_tx,\n \t\t       MTK_NAPI_WEIGHT);\n \tnetif_napi_add(&eth->dummy_dev, &eth->rx_napi, mtk_napi_rx,\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/703-phy-add-detach-callback-to-struct-phy_driver.patch",
    "content": "From: Gabor Juhos <juhosg@openwrt.org>\nSubject: generic: add detach callback to struct phy_driver\n\nlede-commit: fe61fc2d7d0b3fb348b502f68f98243b3ddf5867\n\nSigned-off-by: Gabor Juhos <juhosg@openwrt.org>\n---\n drivers/net/phy/phy_device.c | 3 +++\n include/linux/phy.h          | 6 ++++++\n 2 files changed, 9 insertions(+)\n\n--- a/drivers/net/phy/phy_device.c\n+++ b/drivers/net/phy/phy_device.c\n@@ -1651,6 +1651,9 @@ void phy_detach(struct phy_device *phyde\n \tstruct module *ndev_owner = NULL;\n \tstruct mii_bus *bus;\n \n+\tif (phydev->drv && phydev->drv->detach)\n+\t\tphydev->drv->detach(phydev);\n+\n \tif (phydev->sysfs_links) {\n \t\tif (dev)\n \t\t\tsysfs_remove_link(&dev->dev.kobj, \"phydev\");\n--- a/include/linux/phy.h\n+++ b/include/linux/phy.h\n@@ -765,6 +765,12 @@ struct phy_driver {\n \t/** @handle_interrupt: Override default interrupt handling */\n \tirqreturn_t (*handle_interrupt)(struct phy_device *phydev);\n \n+\t/*\n+\t * Called before an ethernet device is detached\n+\t * from the PHY.\n+\t */\n+\tvoid (*detach)(struct phy_device *phydev);\n+\n \t/** @remove: Clears up any memory if needed */\n \tvoid (*remove)(struct phy_device *phydev);\n \n"
  },
  {
    "path": "target/linux/generic/pending-5.10/704-00-netfilter-flowtable-fix-excessive-hw-offload-attempt.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nDate: Fri, 6 May 2022 12:37:23 +0200\nSubject: [PATCH] netfilter: flowtable: fix excessive hw offload attempts\n after failure\n\nIf a flow cannot be offloaded, the code currently repeatedly tries again as\nquickly as possible, which can significantly increase system load.\nFix this by limiting flow timeout update and hardware offload retry to once\nper second.\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n\n--- a/net/netfilter/nf_flow_table_core.c\n+++ b/net/netfilter/nf_flow_table_core.c\n@@ -331,8 +331,10 @@ void flow_offload_refresh(struct nf_flow\n \tu32 timeout;\n \n \ttimeout = nf_flowtable_time_stamp + flow_offload_get_timeout(flow);\n-\tif (READ_ONCE(flow->timeout) != timeout)\n+\tif (timeout - READ_ONCE(flow->timeout) > HZ)\n \t\tWRITE_ONCE(flow->timeout, timeout);\n+\telse\n+\t\treturn;\n \n \tif (likely(!nf_flowtable_hw_offload(flow_table)))\n \t\treturn;\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/704-01-netfilter-nft_flow_offload-skip-dst-neigh-lookup-for.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nDate: Fri, 6 May 2022 12:43:58 +0200\nSubject: [PATCH] netfilter: nft_flow_offload: skip dst neigh lookup for\n ppp devices\n\nThe dst entry does not contain a valid hardware address, so skip the lookup\nin order to avoid running into errors here.\nThe proper hardware address is filled in from nft_dev_path_info\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n\n--- a/net/netfilter/nft_flow_offload.c\n+++ b/net/netfilter/nft_flow_offload.c\n@@ -36,6 +36,15 @@ static void nft_default_forward_path(str\n \troute->tuple[dir].xmit_type\t= nft_xmit_type(dst_cache);\n }\n \n+static bool nft_is_valid_ether_device(const struct net_device *dev)\n+{\n+\tif (!dev || (dev->flags & IFF_LOOPBACK) || dev->type != ARPHRD_ETHER ||\n+\t    dev->addr_len != ETH_ALEN || !is_valid_ether_addr(dev->dev_addr))\n+\t\treturn false;\n+\n+\treturn true;\n+}\n+\n static int nft_dev_fill_forward_path(const struct nf_flow_route *route,\n \t\t\t\t     const struct dst_entry *dst_cache,\n \t\t\t\t     const struct nf_conn *ct,\n@@ -47,6 +56,9 @@ static int nft_dev_fill_forward_path(con\n \tstruct neighbour *n;\n \tu8 nud_state;\n \n+\tif (!nft_is_valid_ether_device(dev))\n+\t\tgoto out;\n+\n \tn = dst_neigh_lookup(dst_cache, daddr);\n \tif (!n)\n \t\treturn -1;\n@@ -60,6 +72,7 @@ static int nft_dev_fill_forward_path(con\n \tif (!(nud_state & NUD_VALID))\n \t\treturn -1;\n \n+out:\n \treturn dev_fill_forward_path(dev, ha, stack);\n }\n \n@@ -78,15 +91,6 @@ struct nft_forward_info {\n \tenum flow_offload_xmit_type xmit_type;\n };\n \n-static bool nft_is_valid_ether_device(const struct net_device *dev)\n-{\n-\tif (!dev || (dev->flags & IFF_LOOPBACK) || dev->type != ARPHRD_ETHER ||\n-\t    dev->addr_len != ETH_ALEN || !is_valid_ether_addr(dev->dev_addr))\n-\t\treturn false;\n-\n-\treturn true;\n-}\n-\n static void nft_dev_path_info(const struct net_device_path_stack *stack,\n \t\t\t      struct nft_forward_info *info,\n \t\t\t      unsigned char *ha, struct nf_flowtable *flowtable)\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/704-02-net-fix-dev_fill_forward_path-with-pppoe-bridge.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nDate: Fri, 6 May 2022 13:54:44 +0200\nSubject: [PATCH] net: fix dev_fill_forward_path with pppoe + bridge\n\nWhen calling dev_fill_forward_path on a pppoe device, the provided destination\naddress is invalid. In order for the bridge fdb lookup to succeed, the pppoe\ncode needs to update ctx->daddr to the correct value.\nFix this by storing the address inside struct net_device_path_ctx\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n\n--- a/drivers/net/ethernet/mediatek/mtk_ppe_offload.c\n+++ b/drivers/net/ethernet/mediatek/mtk_ppe_offload.c\n@@ -91,7 +91,6 @@ mtk_flow_get_wdma_info(struct net_device\n {\n \tstruct net_device_path_ctx ctx = {\n \t\t.dev = dev,\n-\t\t.daddr = addr,\n \t};\n \tstruct net_device_path path = {};\n \n@@ -101,6 +100,7 @@ mtk_flow_get_wdma_info(struct net_device\n \tif (!dev->netdev_ops->ndo_fill_forward_path)\n \t\treturn -1;\n \n+\tmemcpy(ctx.daddr, addr, sizeof(ctx.daddr));\n \tif (dev->netdev_ops->ndo_fill_forward_path(&ctx, &path))\n \t\treturn -1;\n \n--- a/drivers/net/ppp/pppoe.c\n+++ b/drivers/net/ppp/pppoe.c\n@@ -988,6 +988,7 @@ static int pppoe_fill_forward_path(struc\n \tpath->encap.proto = htons(ETH_P_PPP_SES);\n \tpath->encap.id = be16_to_cpu(po->num);\n \tmemcpy(path->encap.h_dest, po->pppoe_pa.remote, ETH_ALEN);\n+\tmemcpy(ctx->daddr, po->pppoe_pa.remote, ETH_ALEN);\n \tpath->dev = ctx->dev;\n \tctx->dev = dev;\n \n--- a/include/linux/netdevice.h\n+++ b/include/linux/netdevice.h\n@@ -878,7 +878,7 @@ struct net_device_path_stack {\n \n struct net_device_path_ctx {\n \tconst struct net_device *dev;\n-\tconst u8\t\t*daddr;\n+\tu8\t\t\tdaddr[ETH_ALEN];\n \n \tint\t\t\tnum_vlans;\n \tstruct {\n--- a/net/core/dev.c\n+++ b/net/core/dev.c\n@@ -863,11 +863,11 @@ int dev_fill_forward_path(const struct n\n \tconst struct net_device *last_dev;\n \tstruct net_device_path_ctx ctx = {\n \t\t.dev\t= dev,\n-\t\t.daddr\t= daddr,\n \t};\n \tstruct net_device_path *path;\n \tint ret = 0;\n \n+\tmemcpy(ctx.daddr, daddr, sizeof(ctx.daddr));\n \tstack->num_paths = 0;\n \twhile (ctx.dev && ctx.dev->netdev_ops->ndo_fill_forward_path) {\n \t\tlast_dev = ctx.dev;\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/704-03-netfilter-nft_flow_offload-fix-offload-with-pppoe-vl.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nDate: Fri, 6 May 2022 15:15:06 +0200\nSubject: [PATCH] netfilter: nft_flow_offload: fix offload with pppoe +\n vlan\n\nWhen running a combination of PPPoE on top of a VLAN, we need to set\ninfo->outdev to the PPPoE device, otherwise PPPoE encap is skipped\nduring software offload.\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n\n--- a/net/netfilter/nft_flow_offload.c\n+++ b/net/netfilter/nft_flow_offload.c\n@@ -123,7 +123,8 @@ static void nft_dev_path_info(const stru\n \t\t\t\tinfo->indev = NULL;\n \t\t\t\tbreak;\n \t\t\t}\n-\t\t\tinfo->outdev = path->dev;\n+\t\t\tif (!info->outdev)\n+\t\t\t\tinfo->outdev = path->dev;\n \t\t\tinfo->encap[info->num_encaps].id = path->encap.id;\n \t\t\tinfo->encap[info->num_encaps].proto = path->encap.proto;\n \t\t\tinfo->num_encaps++;\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/705-net-dsa-tag_mtk-add-padding-for-tx-packets.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nDate: Fri, 6 May 2022 21:38:42 +0200\nSubject: [PATCH] net: dsa: tag_mtk: add padding for tx packets\n\nPadding for transmitted packets needs to account for the special tag.\nWith not enough padding, garbage bytes are inserted by the switch at the\nend of small packets.\n\nFixes: 5cd8985a1909 (\"net-next: dsa: add Mediatek tag RX/TX handler\")\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n\n--- a/net/dsa/tag_mtk.c\n+++ b/net/dsa/tag_mtk.c\n@@ -25,6 +25,14 @@ static struct sk_buff *mtk_tag_xmit(stru\n \tu8 xmit_tpid;\n \tu8 *mtk_tag;\n \n+\t/* The Ethernet switch we are interfaced with needs packets to be at\n+\t * least 64 bytes (including FCS) otherwise their padding might be\n+\t * corrupted. With tags enabled, we need to make sure that packets are\n+\t * at least 68 bytes (including FCS and tag).\n+\t */\n+\tif (__skb_put_padto(skb, ETH_ZLEN + MTK_HDR_LEN, false))\n+\t\treturn NULL;\n+\n \t/* Build the special tag after the MAC Source Address. If VLAN header\n \t * is present, it's required that VLAN header and special tag is\n \t * being combined. Only in this way we can allow the switch can parse\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/710-bridge-add-knob-for-filtering-rx-tx-BPDU-pack.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nDate: Fri, 27 Aug 2021 12:22:32 +0200\nSubject: [PATCH] bridge: add knob for filtering rx/tx BPDU packets on a port\n\nSome devices (e.g. wireless APs) can't have devices behind them be part of\na bridge topology with redundant links, due to address limitations.\nAdditionally, broadcast traffic on these devices is somewhat expensive, due to\nthe low data rate and wakeups of clients in powersave mode.\nThis knob can be used to ensure that BPDU packets are never sent or forwarded\nto/from these devices\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n\n--- a/include/linux/if_bridge.h\n+++ b/include/linux/if_bridge.h\n@@ -56,6 +56,7 @@ struct br_ip_list {\n #define BR_MRP_AWARE\t\tBIT(17)\n #define BR_MRP_LOST_CONT\tBIT(18)\n #define BR_MRP_LOST_IN_CONT\tBIT(19)\n+#define BR_BPDU_FILTER\t\tBIT(20)\n \n #define BR_DEFAULT_AGEING_TIME\t(300 * HZ)\n \n--- a/net/bridge/br_forward.c\n+++ b/net/bridge/br_forward.c\n@@ -191,6 +191,7 @@ out:\n void br_flood(struct net_bridge *br, struct sk_buff *skb,\n \t      enum br_pkt_type pkt_type, bool local_rcv, bool local_orig)\n {\n+\tconst unsigned char *dest = eth_hdr(skb)->h_dest;\n \tstruct net_bridge_port *prev = NULL;\n \tstruct net_bridge_port *p;\n \n@@ -206,6 +207,10 @@ void br_flood(struct net_bridge *br, str\n \t\tcase BR_PKT_MULTICAST:\n \t\t\tif (!(p->flags & BR_MCAST_FLOOD) && skb->dev != br->dev)\n \t\t\t\tcontinue;\n+\t\t\tif ((p->flags & BR_BPDU_FILTER) &&\n+\t\t\t    unlikely(is_link_local_ether_addr(dest) &&\n+\t\t\t\t     dest[5] == 0))\n+\t\t\t\tcontinue;\n \t\t\tbreak;\n \t\tcase BR_PKT_BROADCAST:\n \t\t\tif (!(p->flags & BR_BCAST_FLOOD) && skb->dev != br->dev)\n--- a/net/bridge/br_input.c\n+++ b/net/bridge/br_input.c\n@@ -305,6 +305,8 @@ static rx_handler_result_t br_handle_fra\n \t\tfwd_mask |= p->group_fwd_mask;\n \t\tswitch (dest[5]) {\n \t\tcase 0x00:\t/* Bridge Group Address */\n+\t\t\tif (p->flags & BR_BPDU_FILTER)\n+\t\t\t\tgoto drop;\n \t\t\t/* If STP is turned off,\n \t\t\t   then must forward to keep loop detection */\n \t\t\tif (p->br->stp_enabled == BR_NO_STP ||\n--- a/net/bridge/br_sysfs_if.c\n+++ b/net/bridge/br_sysfs_if.c\n@@ -233,6 +233,7 @@ BRPORT_ATTR_FLAG(multicast_flood, BR_MCA\n BRPORT_ATTR_FLAG(broadcast_flood, BR_BCAST_FLOOD);\n BRPORT_ATTR_FLAG(neigh_suppress, BR_NEIGH_SUPPRESS);\n BRPORT_ATTR_FLAG(isolated, BR_ISOLATED);\n+BRPORT_ATTR_FLAG(bpdu_filter, BR_BPDU_FILTER);\n \n #ifdef CONFIG_BRIDGE_IGMP_SNOOPING\n static ssize_t show_multicast_router(struct net_bridge_port *p, char *buf)\n@@ -285,6 +286,7 @@ static const struct brport_attribute *br\n \t&brport_attr_group_fwd_mask,\n \t&brport_attr_neigh_suppress,\n \t&brport_attr_isolated,\n+\t&brport_attr_bpdu_filter,\n \t&brport_attr_backup_port,\n \tNULL\n };\n--- a/net/bridge/br_stp_bpdu.c\n+++ b/net/bridge/br_stp_bpdu.c\n@@ -80,7 +80,8 @@ void br_send_config_bpdu(struct net_brid\n {\n \tunsigned char buf[35];\n \n-\tif (p->br->stp_enabled != BR_KERNEL_STP)\n+\tif (p->br->stp_enabled != BR_KERNEL_STP ||\n+\t    (p->flags & BR_BPDU_FILTER))\n \t\treturn;\n \n \tbuf[0] = 0;\n@@ -127,7 +128,8 @@ void br_send_tcn_bpdu(struct net_bridge_\n {\n \tunsigned char buf[4];\n \n-\tif (p->br->stp_enabled != BR_KERNEL_STP)\n+\tif (p->br->stp_enabled != BR_KERNEL_STP ||\n+\t    (p->flags & BR_BPDU_FILTER))\n \t\treturn;\n \n \tbuf[0] = 0;\n@@ -172,6 +174,9 @@ void br_stp_rcv(const struct stp_proto *\n \tif (!(br->dev->flags & IFF_UP))\n \t\tgoto out;\n \n+\tif (p->flags & BR_BPDU_FILTER)\n+\t\tgoto out;\n+\n \tif (p->state == BR_STATE_DISABLED)\n \t\tgoto out;\n \n--- a/include/uapi/linux/if_link.h\n+++ b/include/uapi/linux/if_link.h\n@@ -524,6 +524,7 @@ enum {\n \tIFLA_BRPORT_BACKUP_PORT,\n \tIFLA_BRPORT_MRP_RING_OPEN,\n \tIFLA_BRPORT_MRP_IN_OPEN,\n+\tIFLA_BRPORT_BPDU_FILTER,\n \t__IFLA_BRPORT_MAX\n };\n #define IFLA_BRPORT_MAX (__IFLA_BRPORT_MAX - 1)\n--- a/net/bridge/br_netlink.c\n+++ b/net/bridge/br_netlink.c\n@@ -137,6 +137,7 @@ static inline size_t br_port_info_size(v\n \t\t+ nla_total_size(1)\t/* IFLA_BRPORT_VLAN_TUNNEL */\n \t\t+ nla_total_size(1)\t/* IFLA_BRPORT_NEIGH_SUPPRESS */\n \t\t+ nla_total_size(1)\t/* IFLA_BRPORT_ISOLATED */\n+\t\t+ nla_total_size(1)\t/* IFLA_BRPORT_BPDU_FILTER */\n \t\t+ nla_total_size(sizeof(struct ifla_bridge_id))\t/* IFLA_BRPORT_ROOT_ID */\n \t\t+ nla_total_size(sizeof(struct ifla_bridge_id))\t/* IFLA_BRPORT_BRIDGE_ID */\n \t\t+ nla_total_size(sizeof(u16))\t/* IFLA_BRPORT_DESIGNATED_PORT */\n@@ -220,7 +221,8 @@ static int br_port_fill_attrs(struct sk_\n \t\t\t\t\t\t\t  BR_MRP_LOST_CONT)) ||\n \t    nla_put_u8(skb, IFLA_BRPORT_MRP_IN_OPEN,\n \t\t       !!(p->flags & BR_MRP_LOST_IN_CONT)) ||\n-\t    nla_put_u8(skb, IFLA_BRPORT_ISOLATED, !!(p->flags & BR_ISOLATED)))\n+\t    nla_put_u8(skb, IFLA_BRPORT_ISOLATED, !!(p->flags & BR_ISOLATED)) ||\n+\t    nla_put_u8(skb, IFLA_BRPORT_BPDU_FILTER, !!(p->flags & BR_BPDU_FILTER)))\n \t\treturn -EMSGSIZE;\n \n \ttimerval = br_timer_value(&p->message_age_timer);\n@@ -728,6 +730,7 @@ static const struct nla_policy br_port_p\n \t[IFLA_BRPORT_NEIGH_SUPPRESS] = { .type = NLA_U8 },\n \t[IFLA_BRPORT_ISOLATED]\t= { .type = NLA_U8 },\n \t[IFLA_BRPORT_BACKUP_PORT] = { .type = NLA_U32 },\n+\t[IFLA_BRPORT_BPDU_FILTER] = { .type = NLA_U8 },\n };\n \n /* Change the state of the port and notify spanning tree */\n@@ -826,6 +829,10 @@ static int br_setport(struct net_bridge_\n \tif (err)\n \t\treturn err;\n \n+\terr = br_set_port_flag(p, tb, IFLA_BRPORT_BPDU_FILTER, BR_BPDU_FILTER);\n+\tif (err)\n+\t\treturn err;\n+\n \tbr_vlan_tunnel_old = (p->flags & BR_VLAN_TUNNEL) ? true : false;\n \terr = br_set_port_flag(p, tb, IFLA_BRPORT_VLAN_TUNNEL, BR_VLAN_TUNNEL);\n \tif (err)\n--- a/net/core/rtnetlink.c\n+++ b/net/core/rtnetlink.c\n@@ -55,7 +55,7 @@\n #include <net/net_namespace.h>\n \n #define RTNL_MAX_TYPE\t\t50\n-#define RTNL_SLAVE_MAX_TYPE\t36\n+#define RTNL_SLAVE_MAX_TYPE\t37\n \n struct rtnl_link {\n \trtnl_doit_func\t\tdoit;\n@@ -4695,7 +4695,9 @@ int ndo_dflt_bridge_getlink(struct sk_bu\n \t    brport_nla_put_flag(skb, flags, mask,\n \t\t\t\tIFLA_BRPORT_MCAST_FLOOD, BR_MCAST_FLOOD) ||\n \t    brport_nla_put_flag(skb, flags, mask,\n-\t\t\t\tIFLA_BRPORT_BCAST_FLOOD, BR_BCAST_FLOOD)) {\n+\t\t\t\tIFLA_BRPORT_BCAST_FLOOD, BR_BCAST_FLOOD) ||\n+\t    brport_nla_put_flag(skb, flags, mask,\n+\t\t\t\tIFLA_BRPORT_BPDU_FILTER, BR_BPDU_FILTER)) {\n \t\tnla_nest_cancel(skb, protinfo);\n \t\tgoto nla_put_failure;\n \t}\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/730-net-phy-at803x-fix-feature-detection.patch",
    "content": "From 97ca310aa18a93329ef5cd68c20de89761962f45 Mon Sep 17 00:00:00 2001\nFrom: David Bauer <mail@david-bauer.net>\nDate: Sun, 13 Jun 2021 12:19:36 +0200\nSubject: [PATCH] net: phy: at803x: fix feature detection\n\nAR8031/AR8033 have different status registers for copper\nand fiber operation. However, the extended status register\nis the same for both operation modes.\n\nAs a result of that, ESTATUS_1000_XFULL is set to 1 even when\noperating in copper TP mode.\n\nRemove this mode from the supported link modes, as this driver\ncurrently only supports copper operation.\n\nSigned-off-by: David Bauer <mail@david-bauer.net>\n---\n drivers/net/phy/at803x.c | 30 +++++++++++++++++++++++++++++-\n 1 file changed, 29 insertions(+), 1 deletion(-)\n\n--- a/drivers/net/phy/at803x.c\n+++ b/drivers/net/phy/at803x.c\n@@ -1032,6 +1032,34 @@ static int at803x_set_tunable(struct phy\n \t}\n }\n \n+static int at803x_get_features(struct phy_device *phydev)\n+{\n+\tint err;\n+\n+\terr = genphy_read_abilities(phydev);\n+\tif (err)\n+\t\treturn err;\n+\n+\tif (!at803x_match_phy_id(phydev, ATH8031_PHY_ID))\n+\t\treturn 0;\n+\n+\t/* AR8031/AR8033 have different status registers\n+\t * for copper and fiber operation. However, the\n+\t * extended status register is the same for both\n+\t * operation modes.\n+\t *\n+\t * As a result of that, ESTATUS_1000_XFULL is set\n+\t * to 1 even when operating in copper TP mode.\n+\t *\n+\t * Remove this mode from the supported link modes,\n+\t * as this driver currently only supports copper\n+\t * operation.\n+\t */\n+\tlinkmode_clear_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT,\n+\t\t\t   phydev->supported);\n+\treturn 0;\n+}\n+\n static int at803x_cable_test_result_trans(u16 status)\n {\n \tswitch (FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status)) {\n@@ -1364,7 +1392,7 @@ static struct phy_driver at803x_driver[]\n \t.resume\t\t\t= at803x_resume,\n \t.read_page\t\t= at803x_read_page,\n \t.write_page\t\t= at803x_write_page,\n-\t/* PHY_GBIT_FEATURES */\n+\t.get_features\t\t= at803x_get_features,\n \t.read_status\t\t= at803x_read_status,\n \t.aneg_done\t\t= at803x_aneg_done,\n \t.ack_interrupt\t\t= &at803x_ack_interrupt,\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/760-net-dsa-mv88e6xxx-fix-vlan-setup.patch",
    "content": "From a1b291f3f6c80a6c5ccad7283fc472d77a2a4763 Mon Sep 17 00:00:00 2001\nFrom: Russell King <rmk+kernel@armlinux.org.uk>\nDate: Sun, 22 Dec 2019 12:40:11 +0000\nSubject: [PATCH] net: dsa: mv88e6xxx: fix vlan setup\n\nProvide an option that drivers can set to indicate they want to receive\nvlan configuration even when vlan filtering is disabled. This is safe\nfor Marvell DSA bridges, which do not look up ingress traffic in the\nVTU if the port is in 8021Q disabled state. Whether this change is\nsuitable for all DSA bridges is not known.\n\nSigned-off-by: Russell King <rmk+kernel@armlinux.org.uk>\nSigned-off-by: DENG Qingfang <dqfext@gmail.com>\n---\n drivers/net/dsa/mv88e6xxx/chip.c |  1 +\n 1 file changed, 1 insertion(+)\n\n--- a/drivers/net/dsa/mv88e6xxx/chip.c\n+++ b/drivers/net/dsa/mv88e6xxx/chip.c\n@@ -2917,6 +2917,7 @@ static int mv88e6xxx_setup(struct dsa_sw\n \n \tchip->ds = ds;\n \tds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip);\n+\tds->configure_vlan_while_not_filtering = true;\n \n \tmv88e6xxx_reg_lock(chip);\n \n"
  },
  {
    "path": "target/linux/generic/pending-5.10/762-net-bridge-switchdev-Refactor-br_switchdev_fdb_notif.patch",
    "content": "From 46fe6cecb296d850c1ee2b333e57093ac4b733f3 Mon Sep 17 00:00:00 2001\nFrom: Tobias Waldekranz <tobias@waldekranz.com>\nDate: Sat, 16 Jan 2021 02:25:09 +0100\nSubject: [PATCH] net: bridge: switchdev: Refactor br_switchdev_fdb_notify\n\nInstead of having to add more and more arguments to\nbr_switchdev_fdb_call_notifiers, get rid of it and build the info\nstruct directly in br_switchdev_fdb_notify.\n\nSigned-off-by: Tobias Waldekranz <tobias@waldekranz.com>\nReviewed-by: Vladimir Oltean <olteanv@gmail.com>\n---\n net/bridge/br_switchdev.c | 41 +++++++++++----------------------------\n 1 file changed, 11 insertions(+), 30 deletions(-)\n\n--- a/net/bridge/br_switchdev.c\n+++ b/net/bridge/br_switchdev.c\n@@ -102,25 +102,16 @@ int br_switchdev_set_port_flag(struct ne\n \treturn 0;\n }\n \n-static void\n-br_switchdev_fdb_call_notifiers(bool adding, const unsigned char *mac,\n-\t\t\t\tu16 vid, struct net_device *dev,\n-\t\t\t\tbool added_by_user, bool offloaded)\n-{\n-\tstruct switchdev_notifier_fdb_info info;\n-\tunsigned long notifier_type;\n-\n-\tinfo.addr = mac;\n-\tinfo.vid = vid;\n-\tinfo.added_by_user = added_by_user;\n-\tinfo.offloaded = offloaded;\n-\tnotifier_type = adding ? SWITCHDEV_FDB_ADD_TO_DEVICE : SWITCHDEV_FDB_DEL_TO_DEVICE;\n-\tcall_switchdev_notifiers(notifier_type, dev, &info.info, NULL);\n-}\n-\n void\n br_switchdev_fdb_notify(const struct net_bridge_fdb_entry *fdb, int type)\n {\n+\tstruct switchdev_notifier_fdb_info info = {\n+\t\t.addr = fdb->key.addr.addr,\n+\t\t.vid = fdb->key.vlan_id,\n+\t\t.added_by_user = test_bit(BR_FDB_ADDED_BY_USER, &fdb->flags),\n+\t\t.offloaded = test_bit(BR_FDB_OFFLOADED, &fdb->flags),\n+\t};\n+\n \tif (!fdb->dst)\n \t\treturn;\n \tif (test_bit(BR_FDB_LOCAL, &fdb->flags))\n@@ -128,22 +119,12 @@ br_switchdev_fdb_notify(const struct net\n \n \tswitch (type) {\n \tcase RTM_DELNEIGH:\n-\t\tbr_switchdev_fdb_call_notifiers(false, fdb->key.addr.addr,\n-\t\t\t\t\t\tfdb->key.vlan_id,\n-\t\t\t\t\t\tfdb->dst->dev,\n-\t\t\t\t\t\ttest_bit(BR_FDB_ADDED_BY_USER,\n-\t\t\t\t\t\t\t &fdb->flags),\n-\t\t\t\t\t\ttest_bit(BR_FDB_OFFLOADED,\n-\t\t\t\t\t\t\t &fdb->flags));\n+\t\tcall_switchdev_notifiers(SWITCHDEV_FDB_DEL_TO_DEVICE,\n+\t\t\t\t\t fdb->dst->dev, &info.info, NULL);\n \t\tbreak;\n \tcase RTM_NEWNEIGH:\n-\t\tbr_switchdev_fdb_call_notifiers(true, fdb->key.addr.addr,\n-\t\t\t\t\t\tfdb->key.vlan_id,\n-\t\t\t\t\t\tfdb->dst->dev,\n-\t\t\t\t\t\ttest_bit(BR_FDB_ADDED_BY_USER,\n-\t\t\t\t\t\t\t &fdb->flags),\n-\t\t\t\t\t\ttest_bit(BR_FDB_OFFLOADED,\n-\t\t\t\t\t\t\t &fdb->flags));\n+\t\tcall_switchdev_notifiers(SWITCHDEV_FDB_ADD_TO_DEVICE,\n+\t\t\t\t\t fdb->dst->dev, &info.info, NULL);\n \t\tbreak;\n \t}\n }\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/763-net-bridge-switchdev-Include-local-flag-in-FDB-notif.patch",
    "content": "From ec5be4f79026282925ae383caa431a8d41e3456a Mon Sep 17 00:00:00 2001\nFrom: Tobias Waldekranz <tobias@waldekranz.com>\nDate: Sat, 16 Jan 2021 02:25:10 +0100\nSubject: [PATCH] net: bridge: switchdev: Include local flag in FDB\n notifications\n\nSome switchdev drivers, notably DSA, ignore all dynamically learned\naddress notifications (!added_by_user) as these are autonomously added\nby the switch. Previously, such a notification was indistinguishable\nfrom a local address notification. Include a local bit in the\nnotification so that the two classes can be discriminated.\n\nThis allows DSA-like devices to add local addresses to the hardware\nFDB (with the CPU as the destination), thereby avoiding flows towards\nthe CPU being flooded by the switch as unknown unicast.\n\nSigned-off-by: Tobias Waldekranz <tobias@waldekranz.com>\n---\n include/net/switchdev.h   | 1 +\n net/bridge/br_switchdev.c | 1 +\n 2 files changed, 2 insertions(+)\n\n--- a/include/net/switchdev.h\n+++ b/include/net/switchdev.h\n@@ -224,6 +224,7 @@ struct switchdev_notifier_fdb_info {\n \tconst unsigned char *addr;\n \tu16 vid;\n \tu8 added_by_user:1,\n+\t   local:1,\n \t   offloaded:1;\n };\n \n--- a/net/bridge/br_switchdev.c\n+++ b/net/bridge/br_switchdev.c\n@@ -109,6 +109,7 @@ br_switchdev_fdb_notify(const struct net\n \t\t.addr = fdb->key.addr.addr,\n \t\t.vid = fdb->key.vlan_id,\n \t\t.added_by_user = test_bit(BR_FDB_ADDED_BY_USER, &fdb->flags),\n+\t\t.local = test_bit(BR_FDB_LOCAL, &fdb->flags),\n \t\t.offloaded = test_bit(BR_FDB_OFFLOADED, &fdb->flags),\n \t};\n \n"
  },
  {
    "path": "target/linux/generic/pending-5.10/764-net-bridge-switchdev-Send-FDB-notifications-for-host.patch",
    "content": "From 2e50fd9322047253c327550b4485cf8761035a8c Mon Sep 17 00:00:00 2001\nFrom: Tobias Waldekranz <tobias@waldekranz.com>\nDate: Sat, 16 Jan 2021 02:25:11 +0100\nSubject: [PATCH] net: bridge: switchdev: Send FDB notifications for host\n addresses\n\nTreat addresses added to the bridge itself in the same way as regular\nports and send out a notification so that drivers may sync it down to\nthe hardware FDB.\n\nSigned-off-by: Tobias Waldekranz <tobias@waldekranz.com>\n---\n net/bridge/br_fdb.c       |  4 ++--\n net/bridge/br_private.h   |  7 ++++---\n net/bridge/br_switchdev.c | 11 +++++------\n 3 files changed, 11 insertions(+), 11 deletions(-)\n\n--- a/net/bridge/br_fdb.c\n+++ b/net/bridge/br_fdb.c\n@@ -602,7 +602,7 @@ void br_fdb_update(struct net_bridge *br\n \t\t\t/* fastpath: update of existing entry */\n \t\t\tif (unlikely(source != fdb->dst &&\n \t\t\t\t     !test_bit(BR_FDB_STICKY, &fdb->flags))) {\n-\t\t\t\tbr_switchdev_fdb_notify(fdb, RTM_DELNEIGH);\n+\t\t\t\tbr_switchdev_fdb_notify(br, fdb, RTM_DELNEIGH);\n \t\t\t\tfdb->dst = source;\n \t\t\t\tfdb_modified = true;\n \t\t\t\t/* Take over HW learned entry */\n@@ -735,7 +735,7 @@ static void fdb_notify(struct net_bridge\n \tint err = -ENOBUFS;\n \n \tif (swdev_notify)\n-\t\tbr_switchdev_fdb_notify(fdb, type);\n+\t\tbr_switchdev_fdb_notify(br, fdb, type);\n \n \tskb = nlmsg_new(fdb_nlmsg_size(), GFP_ATOMIC);\n \tif (skb == NULL)\n--- a/net/bridge/br_private.h\n+++ b/net/bridge/br_private.h\n@@ -1525,8 +1525,8 @@ bool nbp_switchdev_allowed_egress(const\n int br_switchdev_set_port_flag(struct net_bridge_port *p,\n \t\t\t       unsigned long flags,\n \t\t\t       unsigned long mask);\n-void br_switchdev_fdb_notify(const struct net_bridge_fdb_entry *fdb,\n-\t\t\t     int type);\n+void br_switchdev_fdb_notify(struct net_bridge *br,\n+\t\t\t     const struct net_bridge_fdb_entry *fdb, int type);\n int br_switchdev_port_vlan_add(struct net_device *dev, u16 vid, u16 flags,\n \t\t\t       struct netlink_ext_ack *extack);\n int br_switchdev_port_vlan_del(struct net_device *dev, u16 vid);\n@@ -1572,7 +1572,8 @@ static inline int br_switchdev_port_vlan\n }\n \n static inline void\n-br_switchdev_fdb_notify(const struct net_bridge_fdb_entry *fdb, int type)\n+br_switchdev_fdb_notify(struct net_bridge *br,\n+\t\t\tconst struct net_bridge_fdb_entry *fdb, int type)\n {\n }\n \n--- a/net/bridge/br_switchdev.c\n+++ b/net/bridge/br_switchdev.c\n@@ -103,7 +103,8 @@ int br_switchdev_set_port_flag(struct ne\n }\n \n void\n-br_switchdev_fdb_notify(const struct net_bridge_fdb_entry *fdb, int type)\n+br_switchdev_fdb_notify(struct net_bridge *br,\n+\t\t\tconst struct net_bridge_fdb_entry *fdb, int type)\n {\n \tstruct switchdev_notifier_fdb_info info = {\n \t\t.addr = fdb->key.addr.addr,\n@@ -112,20 +113,19 @@ br_switchdev_fdb_notify(const struct net\n \t\t.local = test_bit(BR_FDB_LOCAL, &fdb->flags),\n \t\t.offloaded = test_bit(BR_FDB_OFFLOADED, &fdb->flags),\n \t};\n+\tstruct net_device *dev = fdb->dst ? fdb->dst->dev : br->dev;\n \n-\tif (!fdb->dst)\n-\t\treturn;\n \tif (test_bit(BR_FDB_LOCAL, &fdb->flags))\n \t\treturn;\n \n \tswitch (type) {\n \tcase RTM_DELNEIGH:\n \t\tcall_switchdev_notifiers(SWITCHDEV_FDB_DEL_TO_DEVICE,\n-\t\t\t\t\t fdb->dst->dev, &info.info, NULL);\n+\t\t\t\t\t dev, &info.info, NULL);\n \t\tbreak;\n \tcase RTM_NEWNEIGH:\n \t\tcall_switchdev_notifiers(SWITCHDEV_FDB_ADD_TO_DEVICE,\n-\t\t\t\t\t fdb->dst->dev, &info.info, NULL);\n+\t\t\t\t\t dev, &info.info, NULL);\n \t\tbreak;\n \t}\n }\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/765-net-dsa-Include-local-addresses-in-assisted-CPU-port.patch",
    "content": "From dd082716b43a3684b2f473ae5d1e76d1c076d86d Mon Sep 17 00:00:00 2001\nFrom: Tobias Waldekranz <tobias@waldekranz.com>\nDate: Sat, 16 Jan 2021 02:25:12 +0100\nSubject: [PATCH] net: dsa: Include local addresses in assisted CPU port\n learning\n\nAdd local addresses (i.e. the ports' MAC addresses) to the hardware\nFDB when assisted CPU port learning is enabled.\n\nNOTE: The bridge's own MAC address is also \"local\". If that address is\nnot shared with any port, the bridge's MAC is not be added by this\nfunctionality - but the following commit takes care of that case.\n\nSigned-off-by: Tobias Waldekranz <tobias@waldekranz.com>\n---\n net/dsa/slave.c | 8 +++++---\n 1 file changed, 5 insertions(+), 3 deletions(-)\n\n--- a/net/dsa/slave.c\n+++ b/net/dsa/slave.c\n@@ -2192,10 +2192,12 @@ static int dsa_slave_switchdev_event(str\n \t\tfdb_info = ptr;\n \n \t\tif (dsa_slave_dev_check(dev)) {\n-\t\t\tif (!fdb_info->added_by_user)\n-\t\t\t\treturn NOTIFY_OK;\n-\n \t\t\tdp = dsa_slave_to_port(dev);\n+\n+\t\t\tif (fdb_info->local && dp->ds->assisted_learning_on_cpu_port)\n+\t\t\t\tdp = dp->cpu_dp;\n+\t\t\telse if (!fdb_info->added_by_user)\n+\t\t\t\treturn NOTIFY_OK;\n \t\t} else {\n \t\t\t/* Snoop addresses learnt on foreign interfaces\n \t\t\t * bridged with us, for switches that don't\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/766-net-dsa-Include-bridge-addresses-in-assisted-CPU-por.patch",
    "content": "From 0663ebde114a6fb2c28c622ba5212b302d4d2581 Mon Sep 17 00:00:00 2001\nFrom: Tobias Waldekranz <tobias@waldekranz.com>\nDate: Sat, 16 Jan 2021 02:25:13 +0100\nSubject: [PATCH] net: dsa: Include bridge addresses in assisted CPU port\n learning\n\nNow that notifications are sent out for addresses added to the bridge\nitself, extend DSA to include those addresses in the hardware FDB when\nassisted CPU port learning is enabled.\n\nSigned-off-by: Tobias Waldekranz <tobias@waldekranz.com>\n---\n net/dsa/slave.c | 6 +++++-\n 1 file changed, 5 insertions(+), 1 deletion(-)\n\n--- a/net/dsa/slave.c\n+++ b/net/dsa/slave.c\n@@ -2206,7 +2206,11 @@ static int dsa_slave_switchdev_event(str\n \t\t\tstruct net_device *br_dev;\n \t\t\tstruct dsa_slave_priv *p;\n \n-\t\t\tbr_dev = netdev_master_upper_dev_get_rcu(dev);\n+\t\t\tif (netif_is_bridge_master(dev))\n+\t\t\t\tbr_dev = dev;\n+\t\t\telse\n+\t\t\t\tbr_dev = netdev_master_upper_dev_get_rcu(dev);\n+\n \t\t\tif (!br_dev)\n \t\t\t\treturn NOTIFY_DONE;\n \n"
  },
  {
    "path": "target/linux/generic/pending-5.10/767-net-dsa-Sync-static-FDB-entries-on-foreign-interface.patch",
    "content": "From 81e39fd78db82fb51b05fff309b9c521f1a0bc5a Mon Sep 17 00:00:00 2001\nFrom: Tobias Waldekranz <tobias@waldekranz.com>\nDate: Sat, 16 Jan 2021 02:25:14 +0100\nSubject: [PATCH] net: dsa: Sync static FDB entries on foreign interfaces to\n hardware\n\nReuse the \"assisted_learning_on_cpu_port\" functionality to always add\nentries for user-configured entries on foreign interfaces, even if\nassisted_learning_on_cpu_port is not enabled. E.g. in this situation:\n\n   br0\n   / \\\nswp0 dummy0\n\n$ bridge fdb add 02:00:de:ad:00:01 dev dummy0 vlan 1 master\n\nResults in DSA adding an entry in the hardware FDB, pointing this\naddress towards the CPU port.\n\nThe same is true for entries added to the bridge itself, e.g:\n\n$ bridge fdb add 02:00:de:ad:00:01 dev br0 vlan 1 self\n\nSigned-off-by: Tobias Waldekranz <tobias@waldekranz.com>\n---\n net/dsa/slave.c | 12 ++++++++----\n 1 file changed, 8 insertions(+), 4 deletions(-)\n\n--- a/net/dsa/slave.c\n+++ b/net/dsa/slave.c\n@@ -2199,9 +2199,12 @@ static int dsa_slave_switchdev_event(str\n \t\t\telse if (!fdb_info->added_by_user)\n \t\t\t\treturn NOTIFY_OK;\n \t\t} else {\n-\t\t\t/* Snoop addresses learnt on foreign interfaces\n-\t\t\t * bridged with us, for switches that don't\n-\t\t\t * automatically learn SA from CPU-injected traffic\n+\t\t\t/* Snoop addresses added to foreign interfaces\n+\t\t\t * bridged with us, or the bridge\n+\t\t\t * itself. Dynamically learned addresses can\n+\t\t\t * also be added for switches that don't\n+\t\t\t * automatically learn SA from CPU-injected\n+\t\t\t * traffic.\n \t\t\t */\n \t\t\tstruct net_device *br_dev;\n \t\t\tstruct dsa_slave_priv *p;\n@@ -2223,7 +2226,8 @@ static int dsa_slave_switchdev_event(str\n \n \t\t\tdp = p->dp->cpu_dp;\n \n-\t\t\tif (!dp->ds->assisted_learning_on_cpu_port)\n+\t\t\tif (!fdb_info->added_by_user &&\n+\t\t\t    !dp->ds->assisted_learning_on_cpu_port)\n \t\t\t\treturn NOTIFY_DONE;\n \t\t}\n \n"
  },
  {
    "path": "target/linux/generic/pending-5.10/768-net-dsa-mv88e6xxx-Request-assisted-learning-on-CPU-port.patch",
    "content": "From:   Tobias Waldekranz <tobias@waldekranz.com>\nSubject: [RFC net-next 7/7] net: dsa: mv88e6xxx: Request assisted learning on CPU port\nDate:   Sat, 16 Jan 2021 02:25:15 +0100\nArchived-At: <https://lore.kernel.org/netdev/20210116012515.3152-8-tobias@waldekranz.com/>\n\nWhile the hardware is capable of performing learning on the CPU port,\nit requires alot of additions to the bridge's forwarding path in order\nto handle multi-destination traffic correctly.\n\nUntil that is in place, opt for the next best thing and let DSA sync\nthe relevant addresses down to the hardware FDB.\n\nSigned-off-by: Tobias Waldekranz <tobias@waldekranz.com>\n---\n drivers/net/dsa/mv88e6xxx/chip.c | 1 +\n 1 file changed, 1 insertion(+)\n\n--- a/drivers/net/dsa/mv88e6xxx/chip.c\n+++ b/drivers/net/dsa/mv88e6xxx/chip.c\n@@ -5485,6 +5485,7 @@ static int mv88e6xxx_register_switch(str\n \tds->ops = &mv88e6xxx_switch_ops;\n \tds->ageing_time_min = chip->info->age_time_coeff;\n \tds->ageing_time_max = chip->info->age_time_coeff * U8_MAX;\n+\tds->assisted_learning_on_cpu_port = true;\n \n \tdev_set_drvdata(dev, ds);\n \n"
  },
  {
    "path": "target/linux/generic/pending-5.10/780-ARM-kirkwood-add-missing-linux-if_ether.h-for-ETH_AL.patch",
    "content": "From patchwork Thu Aug  5 22:23:30 2021\nContent-Type: text/plain; charset=\"utf-8\"\nMIME-Version: 1.0\nContent-Transfer-Encoding: 7bit\nX-Patchwork-Submitter: Daniel Golle <daniel@makrotopia.org>\nX-Patchwork-Id: 12422209\nDate: Thu, 5 Aug 2021 23:23:30 +0100\nFrom: Daniel Golle <daniel@makrotopia.org>\nTo: linux-arm-kernel@lists.infradead.org, netdev@vger.kernel.org,\n linux-kernel@vger.kernel.org\nCc: \"David S. Miller\" <davem@davemloft.net>, Andrew Lunn <andrew@lunn.ch>,\n Michael Walle <michael@walle.cc>\nSubject: [PATCH] ARM: kirkwood: add missing <linux/if_ether.h> for ETH_ALEN\nMessage-ID: <YQxk4jrbm31NM1US@makrotopia.org>\nMIME-Version: 1.0\nContent-Disposition: inline\nX-BeenThere: linux-arm-kernel@lists.infradead.org\nX-Mailman-Version: 2.1.34\nPrecedence: list\nList-Id: <linux-arm-kernel.lists.infradead.org>\nList-Archive: <http://lists.infradead.org/pipermail/linux-arm-kernel/>\nSender: \"linux-arm-kernel\" <linux-arm-kernel-bounces@lists.infradead.org>\n\nAfter commit 83216e3988cd1 (\"of: net: pass the dst buffer to\nof_get_mac_address()\") build fails for kirkwood as ETH_ALEN is not\ndefined.\n\narch/arm/mach-mvebu/kirkwood.c: In function 'kirkwood_dt_eth_fixup':\narch/arm/mach-mvebu/kirkwood.c:87:13: error: 'ETH_ALEN' undeclared (first use in this function); did you mean 'ESTALE'?\n   u8 tmpmac[ETH_ALEN];\n             ^~~~~~~~\n             ESTALE\narch/arm/mach-mvebu/kirkwood.c:87:13: note: each undeclared identifier is reported only once for each function it appears in\narch/arm/mach-mvebu/kirkwood.c:87:6: warning: unused variable 'tmpmac' [-Wunused-variable]\n   u8 tmpmac[ETH_ALEN];\n      ^~~~~~\nmake[5]: *** [scripts/Makefile.build:262: arch/arm/mach-mvebu/kirkwood.o] Error 1\nmake[5]: *** Waiting for unfinished jobs....\n\nAdd missing #include <linux/if_ether.h> to fix this.\n\nCc: David S. Miller <davem@davemloft.net>\nCc: Andrew Lunn <andrew@lunn.ch>\nCc: Michael Walle <michael@walle.cc>\nReported-by: https://buildbot.openwrt.org/master/images/#/builders/56/builds/220/steps/44/logs/stdio\nFixes: 83216e3988cd1 (\"of: net: pass the dst buffer to of_get_mac_address()\")\nSigned-off-by: Daniel Golle <daniel@makrotopia.org>\n---\n arch/arm/mach-mvebu/kirkwood.c | 1 +\n 1 file changed, 1 insertion(+)\n\n--- a/arch/arm/mach-mvebu/kirkwood.c\n+++ b/arch/arm/mach-mvebu/kirkwood.c\n@@ -14,6 +14,7 @@\n #include <linux/kernel.h>\n #include <linux/init.h>\n #include <linux/mbus.h>\n+#include <linux/if_ether.h>\n #include <linux/of.h>\n #include <linux/of_address.h>\n #include <linux/of_net.h>\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/800-bcma-get-SoC-device-struct-copy-its-DMA-params-to-th.patch",
    "content": "From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nSubject: [PATCH] bcma: get SoC device struct & copy its DMA params to the\n subdevices\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nFor bus devices to be fully usable it's required to set their DMA\nparameters.\n\nFor years it has been missing and remained unnoticed because of\nmips_dma_alloc_coherent() silently handling the empty coherent_dma_mask.\nKernel 4.19 came with a lot of DMA changes and caused a regression on\nthe bcm47xx. Starting with the commit f8c55dc6e828 (\"MIPS: use generic\ndma noncoherent ops for simple noncoherent platforms\") DMA coherent\nallocations just fail. Example:\n[    1.114914] bgmac_bcma bcma0:2: Allocation of TX ring 0x200 failed\n[    1.121215] bgmac_bcma bcma0:2: Unable to alloc memory for DMA\n[    1.127626] bgmac_bcma: probe of bcma0:2 failed with error -12\n[    1.133838] bgmac_bcma: Broadcom 47xx GBit MAC driver loaded\n\nThis change fixes above regression in addition to the MIPS bcm47xx\ncommit 321c46b91550 (\"MIPS: BCM47XX: Setup struct device for the SoC\").\n\nIt also fixes another *old* GPIO regression caused by a parent pointing\nto the NULL:\n[    0.157054] missing gpiochip .dev parent pointer\n[    0.157287] bcma: bus0: Error registering GPIO driver: -22\nintroduced by the commit 74f4e0cc6108 (\"bcma: switch GPIO portions to\nuse GPIOLIB_IRQCHIP\").\n\nFixes: f8c55dc6e828 (\"MIPS: use generic dma noncoherent ops for simple noncoherent platforms\")\nFixes: 74f4e0cc6108 (\"bcma: switch GPIO portions to use GPIOLIB_IRQCHIP\")\nCc: linux-mips@linux-mips.org\nCc: Christoph Hellwig <hch@lst.de>\nCc: Linus Walleij <linus.walleij@linaro.org>\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\n---\n\n--- a/drivers/bcma/host_soc.c\n+++ b/drivers/bcma/host_soc.c\n@@ -191,6 +191,8 @@ int __init bcma_host_soc_init(struct bcm\n \tstruct bcma_bus *bus = &soc->bus;\n \tint err;\n \n+\tbus->dev = soc->dev;\n+\n \t/* Scan bus and initialize it */\n \terr = bcma_bus_early_register(bus);\n \tif (err)\n--- a/drivers/bcma/main.c\n+++ b/drivers/bcma/main.c\n@@ -241,8 +241,10 @@ void bcma_prepare_core(struct bcma_bus *\n \tcore->dev.bus = &bcma_bus_type;\n \tdev_set_name(&core->dev, \"bcma%d:%d\", bus->num, core->core_index);\n \tcore->dev.parent = bus->dev;\n-\tif (bus->dev)\n+\tif (bus->dev) {\n \t\tbcma_of_fill_device(bus->dev, core);\n+\t\tdma_coerce_mask_and_coherent(&core->dev, bus->dev->coherent_dma_mask);\n+\t}\n \n \tswitch (bus->hosttype) {\n \tcase BCMA_HOSTTYPE_PCI:\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/801-gpio-gpio-cascade-add-generic-GPIO-cascade.patch",
    "content": "From fc23ea48ba52c24f201fe5ca0132ee1a3de5a70a Mon Sep 17 00:00:00 2001\nFrom: Mauri Sandberg <maukka@ext.kapsi.fi>\nDate: Thu, 25 Mar 2021 11:48:05 +0200\nSubject: [PATCH 2/2] gpio: gpio-cascade: add generic GPIO cascade\n\nAdds support for building cascades of GPIO lines. That is, it allows\nsetups when there is one upstream line and multiple cascaded lines, out\nof which one can be chosen at a time. The status of the upstream line\ncan be conveyed to the selected cascaded line or, vice versa, the status\nof the cascaded line can be conveyed to the upstream line.\n\nA multiplexer is being used to select, which cascaded GPIO line is being\nused at any given time.\n\nAt the moment only input direction is supported. In future it should be\npossible to add support for output direction, too.\n\nSigned-off-by: Mauri Sandberg <maukka@ext.kapsi.fi>\nReviewed-by: Linus Walleij <linus.walleij@linaro.org>\nReviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>\n---\nv7 -> v8:\n - rearrange members in struct gpio_cascade\n - cosmetic changes in file header and in one function declaration\n - added Reviewed-by tags by Linus and Andy\nv6 -> v7:\n - In Kconfig add info about module name\n - adhere to new convention that allows lines longer than 80 chars\n - use dev_probe_err with upstream gpio line too\n - refactor for cleaner exit of probe function.\nv5 -> v6:\n - In Kconfig, remove dependency to OF_GPIO and select only MULTIPLEXER\n - refactor code preferring one-liners\n - clean up prints, removing them from success-path.\n - don't explicitly set gpio_chip.of_node as it's done in the GPIO library\n - use devm_gpiochip_add_data instead of gpiochip_add\nv4 -> v5:\n - renamed gpio-mux-input -> gpio-cascade. refactored code accordingly\n   here and there and changed to use new bindings and compatible string\n   - ambigious and vague 'pin' was rename to 'upstream_line'\n - dropped Tested-by and Reviewed-by due to changes in bindings\n - dropped Reported-by suggested by an automatic bot as it was not really\n   appropriate to begin with\n - functionally it's the same as v4\nv3 -> v4:\n - Changed author email\n - Included Tested-by and Reviewed-by from Drew\nv2 -> v3:\n - use managed device resources\n - update Kconfig description\nv1 -> v2:\n - removed .owner from platform_driver as per test bot's instruction\n - added MODULE_AUTHOR, MODULE_DESCRIPTION, MODULE_LICENSE\n - added gpio_mux_input_get_direction as it's recommended for all chips\n - removed because this is input only chip: gpio_mux_input_set_value\n - removed because they are not needed for input/output only chips:\n     gpio_mux_input_direction_input\n     gpio_mux_input_direction_output\n - fixed typo in an error message\n - added info message about successful registration\n - removed can_sleep flag as this does not sleep while getting GPIO value\n   like I2C or SPI do\n - Updated description in Kconfig\n---\n drivers/gpio/Kconfig        |  15 +++++\n drivers/gpio/Makefile       |   1 +\n drivers/gpio/gpio-cascade.c | 117 ++++++++++++++++++++++++++++++++++++\n 3 files changed, 133 insertions(+)\n create mode 100644 drivers/gpio/gpio-cascade.c\n\n--- a/drivers/gpio/Kconfig\n+++ b/drivers/gpio/Kconfig\n@@ -1617,4 +1617,19 @@ config GPIO_MOCKUP\n \t  tools/testing/selftests/gpio/gpio-mockup.sh. Reference the usage in\n \t  it.\n \n+comment \"Other GPIO expanders\"\n+\n+config GPIO_CASCADE\n+\ttristate \"General GPIO cascade\"\n+\tselect MULTIPLEXER\n+\thelp\n+\t  Say yes here to enable support for generic GPIO cascade.\n+\n+\t  This allows building one-to-many cascades of GPIO lines using\n+\t  different types of multiplexers readily available. At the\n+\t  moment only input lines are supported.\n+\n+\t  To build the driver as a module choose 'm' and the resulting module\n+\t  will be called 'gpio-cascade'.\n+\n endif\n--- a/drivers/gpio/Makefile\n+++ b/drivers/gpio/Makefile\n@@ -44,6 +44,7 @@ obj-$(CONFIG_GPIO_BD9571MWV)\t\t+= gpio-bd\n obj-$(CONFIG_GPIO_BRCMSTB)\t\t+= gpio-brcmstb.o\n obj-$(CONFIG_GPIO_BT8XX)\t\t+= gpio-bt8xx.o\n obj-$(CONFIG_GPIO_CADENCE)\t\t+= gpio-cadence.o\n+obj-$(CONFIG_GPIO_CASCADE)\t\t+= gpio-cascade.o\n obj-$(CONFIG_GPIO_CLPS711X)\t\t+= gpio-clps711x.o\n obj-$(CONFIG_GPIO_SNPS_CREG)\t\t+= gpio-creg-snps.o\n obj-$(CONFIG_GPIO_CRYSTAL_COVE)\t\t+= gpio-crystalcove.o\n--- /dev/null\n+++ b/drivers/gpio/gpio-cascade.c\n@@ -0,0 +1,117 @@\n+// SPDX-License-Identifier: GPL-2.0-only\n+/*\n+ *  A generic GPIO cascade driver\n+ *\n+ *  Copyright (C) 2021 Mauri Sandberg <maukka@ext.kapsi.fi>\n+ *\n+ * This allows building cascades of GPIO lines in a manner illustrated\n+ * below:\n+ *\n+ *                 /|---- Cascaded GPIO line 0\n+ *  Upstream      | |---- Cascaded GPIO line 1\n+ *  GPIO line ----+ | .\n+ *                | | .\n+ *                 \\|---- Cascaded GPIO line n\n+ *\n+ * A multiplexer is being used to select, which cascaded line is being\n+ * addressed at any given time.\n+ *\n+ * At the moment only input mode is supported due to lack of means for\n+ * testing output functionality. At least theoretically output should be\n+ * possible with open drain constructions.\n+ */\n+\n+#include <linux/module.h>\n+#include <linux/slab.h>\n+#include <linux/platform_device.h>\n+#include <linux/mux/consumer.h>\n+\n+#include <linux/gpio/consumer.h>\n+#include <linux/gpio/driver.h>\n+\n+struct gpio_cascade {\n+\tstruct gpio_chip\tgpio_chip;\n+\tstruct device\t\t*parent;\n+\tstruct mux_control\t*mux_control;\n+\tstruct gpio_desc\t*upstream_line;\n+};\n+\n+static struct gpio_cascade *chip_to_cascade(struct gpio_chip *gc)\n+{\n+\treturn container_of(gc, struct gpio_cascade, gpio_chip);\n+}\n+\n+static int gpio_cascade_get_direction(struct gpio_chip *gc, unsigned int offset)\n+{\n+\treturn GPIO_LINE_DIRECTION_IN;\n+}\n+\n+static int gpio_cascade_get_value(struct gpio_chip *gc, unsigned int offset)\n+{\n+\tstruct gpio_cascade *cas = chip_to_cascade(gc);\n+\tint ret;\n+\n+\tret = mux_control_select(cas->mux_control, offset);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = gpiod_get_value(cas->upstream_line);\n+\tmux_control_deselect(cas->mux_control);\n+\treturn ret;\n+}\n+\n+static int gpio_cascade_probe(struct platform_device *pdev)\n+{\n+\tstruct device *dev = &pdev->dev;\n+\tstruct gpio_cascade *cas;\n+\tstruct mux_control *mc;\n+\tstruct gpio_desc *upstream;\n+\tstruct gpio_chip *gc;\n+\n+\tcas = devm_kzalloc(dev, sizeof(*cas), GFP_KERNEL);\n+\tif (!cas)\n+\t\treturn -ENOMEM;\n+\n+\tmc = devm_mux_control_get(dev, NULL);\n+\tif (IS_ERR(mc))\n+\t\treturn dev_err_probe(dev, PTR_ERR(mc), \"unable to get mux-control\\n\");\n+\n+\tcas->mux_control = mc;\n+\tupstream = devm_gpiod_get(dev, \"upstream\",  GPIOD_IN);\n+\tif (IS_ERR(upstream))\n+\t\treturn dev_err_probe(dev, PTR_ERR(upstream), \"unable to claim upstream GPIO line\\n\");\n+\n+\tcas->upstream_line = upstream;\n+\tcas->parent = dev;\n+\n+\tgc = &cas->gpio_chip;\n+\tgc->get = gpio_cascade_get_value;\n+\tgc->get_direction = gpio_cascade_get_direction;\n+\tgc->base = -1;\n+\tgc->ngpio = mux_control_states(mc);\n+\tgc->label = dev_name(cas->parent);\n+\tgc->parent = cas->parent;\n+\tgc->owner = THIS_MODULE;\n+\n+\tplatform_set_drvdata(pdev, cas);\n+\treturn devm_gpiochip_add_data(dev, &cas->gpio_chip, NULL);\n+}\n+\n+static const struct of_device_id gpio_cascade_id[] = {\n+\t{ .compatible = \"gpio-cascade\" },\n+\t{ /* sentinel */ }\n+};\n+MODULE_DEVICE_TABLE(of, gpio_cascade_id);\n+\n+static struct platform_driver gpio_cascade_driver = {\n+\t.driver\t= {\n+\t\t.name\t\t= \"gpio-cascade\",\n+\t\t.of_match_table = gpio_cascade_id,\n+\t},\n+\t.probe\t= gpio_cascade_probe,\n+};\n+module_platform_driver(gpio_cascade_driver);\n+\n+MODULE_AUTHOR(\"Mauri Sandberg <maukka@ext.kapsi.fi>\");\n+MODULE_DESCRIPTION(\"Generic GPIO cascade\");\n+MODULE_LICENSE(\"GPL\");\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/810-pci_disable_common_quirks.patch",
    "content": "From: Gabor Juhos <juhosg@openwrt.org>\nSubject: debloat: add kernel config option to disabling common PCI quirks\n\nSigned-off-by: Gabor Juhos <juhosg@openwrt.org>\n---\n drivers/pci/Kconfig  | 6 ++++++\n drivers/pci/quirks.c | 6 ++++++\n 2 files changed, 12 insertions(+)\n\n--- a/drivers/pci/Kconfig\n+++ b/drivers/pci/Kconfig\n@@ -118,6 +118,13 @@ config XEN_PCIDEV_FRONTEND\n \t  The PCI device frontend driver allows the kernel to import arbitrary\n \t  PCI devices from a PCI backend to support PCI driver domains.\n \n+config PCI_DISABLE_COMMON_QUIRKS\n+\tbool \"PCI disable common quirks\"\n+\tdepends on PCI\n+\thelp\n+\t  If you don't know what to do here, say N.\n+\n+\n config PCI_ATS\n \tbool\n \n--- a/drivers/pci/quirks.c\n+++ b/drivers/pci/quirks.c\n@@ -206,6 +206,7 @@ static void quirk_mmio_always_on(struct\n DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID, PCI_ANY_ID,\n \t\t\t\tPCI_CLASS_BRIDGE_HOST, 8, quirk_mmio_always_on);\n \n+#ifndef CONFIG_PCI_DISABLE_COMMON_QUIRKS\n /*\n  * The Mellanox Tavor device gives false positive parity errors.  Mark this\n  * device with a broken_parity_status to allow PCI scanning code to \"skip\"\n@@ -3335,6 +3336,8 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_I\n DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata);\n DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata);\n \n+#endif /* !CONFIG_PCI_DISABLE_COMMON_QUIRKS */\n+\n /*\n  * Ivytown NTB BAR sizes are misreported by the hardware due to an erratum.\n  * To work around this, query the size it should be configured to by the\n@@ -3360,6 +3363,8 @@ static void quirk_intel_ntb(struct pci_d\n DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e08, quirk_intel_ntb);\n DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e0d, quirk_intel_ntb);\n \n+#ifndef CONFIG_PCI_DISABLE_COMMON_QUIRKS\n+\n /*\n  * Some BIOS implementations leave the Intel GPU interrupts enabled, even\n  * though no one is handling them (e.g., if the i915 driver is never\n@@ -3398,6 +3403,8 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_IN\n DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq);\n DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0152, disable_igfx_irq);\n \n+#endif /* !CONFIG_PCI_DISABLE_COMMON_QUIRKS */\n+\n /*\n  * PCI devices which are on Intel chips can skip the 10ms delay\n  * before entering D3 mode.\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/811-pci_disable_usb_common_quirks.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nSubject: debloat: disable common USB quirks\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n drivers/usb/host/pci-quirks.c | 16 ++++++++++++++++\n drivers/usb/host/pci-quirks.h | 18 +++++++++++++++++-\n include/linux/usb/hcd.h       |  7 +++++++\n 3 files changed, 40 insertions(+), 1 deletion(-)\n\n--- a/drivers/usb/host/pci-quirks.c\n+++ b/drivers/usb/host/pci-quirks.c\n@@ -128,6 +128,8 @@ struct amd_chipset_type {\n \tu8 rev;\n };\n \n+#ifndef CONFIG_PCI_DISABLE_COMMON_QUIRKS\n+\n static struct amd_chipset_info {\n \tstruct pci_dev\t*nb_dev;\n \tstruct pci_dev\t*smbus_dev;\n@@ -633,6 +635,10 @@ bool usb_amd_pt_check_port(struct device\n }\n EXPORT_SYMBOL_GPL(usb_amd_pt_check_port);\n \n+#endif /* CONFIG_PCI_DISABLE_COMMON_QUIRKS */\n+\n+#if IS_ENABLED(CONFIG_USB_UHCI_HCD)\n+\n /*\n  * Make sure the controller is completely inactive, unable to\n  * generate interrupts or do DMA.\n@@ -712,8 +718,17 @@ reset_needed:\n \tuhci_reset_hc(pdev, base);\n \treturn 1;\n }\n+#else\n+int uhci_check_and_reset_hc(struct pci_dev *pdev, unsigned long base)\n+{\n+\treturn 0;\n+}\n+\n+#endif\n EXPORT_SYMBOL_GPL(uhci_check_and_reset_hc);\n \n+#ifndef CONFIG_PCI_DISABLE_COMMON_QUIRKS\n+\n static inline int io_type_enabled(struct pci_dev *pdev, unsigned int mask)\n {\n \tu16 cmd;\n@@ -1285,3 +1300,4 @@ static void quirk_usb_early_handoff(stru\n }\n DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID,\n \t\t\tPCI_CLASS_SERIAL_USB, 8, quirk_usb_early_handoff);\n+#endif\n--- a/drivers/usb/host/pci-quirks.h\n+++ b/drivers/usb/host/pci-quirks.h\n@@ -5,6 +5,9 @@\n #ifdef CONFIG_USB_PCI\n void uhci_reset_hc(struct pci_dev *pdev, unsigned long base);\n int uhci_check_and_reset_hc(struct pci_dev *pdev, unsigned long base);\n+#endif  /* CONFIG_USB_PCI */\n+\n+#if defined(CONFIG_USB_PCI) && !defined(CONFIG_PCI_DISABLE_COMMON_QUIRKS)\n int usb_hcd_amd_remote_wakeup_quirk(struct pci_dev *pdev);\n bool usb_amd_hang_symptom_quirk(void);\n bool usb_amd_prefetch_quirk(void);\n@@ -19,6 +22,18 @@ void sb800_prefetch(struct device *dev,\n bool usb_amd_pt_check_port(struct device *device, int port);\n #else\n struct pci_dev;\n+static inline int usb_amd_quirk_pll_check(void)\n+{\n+\treturn 0;\n+}\n+static inline bool usb_amd_hang_symptom_quirk(void)\n+{\n+\treturn false;\n+}\n+static inline bool usb_amd_prefetch_quirk(void)\n+{\n+\treturn false;\n+}\n static inline void usb_amd_quirk_pll_disable(void) {}\n static inline void usb_amd_quirk_pll_enable(void) {}\n static inline void usb_asmedia_modifyflowcontrol(struct pci_dev *pdev) {}\n@@ -29,6 +44,11 @@ static inline bool usb_amd_pt_check_port\n {\n \treturn false;\n }\n+static inline void usb_enable_intel_xhci_ports(struct pci_dev *xhci_pdev) {}\n+static inline bool usb_xhci_needs_pci_reset(struct pci_dev *pdev)\n+{\n+\treturn false;\n+}\n #endif  /* CONFIG_USB_PCI */\n \n #endif  /*  __LINUX_USB_PCI_QUIRKS_H  */\n--- a/include/linux/usb/hcd.h\n+++ b/include/linux/usb/hcd.h\n@@ -484,7 +484,14 @@ extern int usb_hcd_pci_probe(struct pci_\n extern void usb_hcd_pci_remove(struct pci_dev *dev);\n extern void usb_hcd_pci_shutdown(struct pci_dev *dev);\n \n+#ifndef CONFIG_PCI_DISABLE_COMMON_QUIRKS\n extern int usb_hcd_amd_remote_wakeup_quirk(struct pci_dev *dev);\n+#else\n+static inline int usb_hcd_amd_remote_wakeup_quirk(struct pci_dev *dev)\n+{\n+\treturn 0;\n+}\n+#endif\n \n #ifdef CONFIG_PM\n extern const struct dev_pm_ops usb_hcd_pci_pm_ops;\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/820-w1-gpio-fix-problem-with-platfom-data-in-w1-gpio.patch",
    "content": "From d9c8bc8c1408f3e8529db6e4e04017b4c579c342 Mon Sep 17 00:00:00 2001\nFrom: Pawel Dembicki <paweldembicki@gmail.com>\nDate: Sun, 18 Feb 2018 17:08:04 +0100\nSubject: [PATCH] w1: gpio: fix problem with platfom data in w1-gpio\n\nIn devices, where fdt is used, is impossible to apply platform data\nwithout proper fdt node.\n\nThis patch allow to use platform data in devices with fdt.\n\nSigned-off-by: Pawel Dembicki <paweldembicki@gmail.com>\n---\n drivers/w1/masters/w1-gpio.c | 7 +++----\n 1 file changed, 3 insertions(+), 4 deletions(-)\n\n--- a/drivers/w1/masters/w1-gpio.c\n+++ b/drivers/w1/masters/w1-gpio.c\n@@ -76,7 +76,7 @@ static int w1_gpio_probe(struct platform\n \tenum gpiod_flags gflags = GPIOD_OUT_LOW_OPEN_DRAIN;\n \tint err;\n \n-\tif (of_have_populated_dt()) {\n+\tif (of_have_populated_dt() && !dev_get_platdata(&pdev->dev)) {\n \t\tpdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);\n \t\tif (!pdata)\n \t\t\treturn -ENOMEM;\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/834-ledtrig-libata.patch",
    "content": "From: Daniel Golle <daniel@makrotopia.org>\nSubject: libata: add ledtrig support\n\nThis adds a LED trigger for each ATA port indicating disk activity.\n\nAs this is needed only on specific platforms (NAS SoCs and such),\nthese platforms should define ARCH_WANTS_LIBATA_LEDS if there\nare boards with LED(s) intended to indicate ATA disk activity and\nneed the OS to take care of that.\nIn that way, if not selected, LED trigger support not will be\nincluded in libata-core and both, codepaths and structures remain\nuntouched.\n\nSigned-off-by: Daniel Golle <daniel@makrotopia.org>\n---\n drivers/ata/Kconfig       | 16 ++++++++++++++++\n drivers/ata/libata-core.c | 41 +++++++++++++++++++++++++++++++++++++++++\n include/linux/libata.h    |  9 +++++++++\n 3 files changed, 66 insertions(+)\n\n--- a/drivers/ata/Kconfig\n+++ b/drivers/ata/Kconfig\n@@ -67,6 +67,22 @@ config ATA_FORCE\n \n \t  If unsure, say Y.\n \n+config ARCH_WANT_LIBATA_LEDS\n+\tbool\n+\n+config ATA_LEDS\n+\tbool \"support ATA port LED triggers\"\n+\tdepends on ARCH_WANT_LIBATA_LEDS\n+\tselect NEW_LEDS\n+\tselect LEDS_CLASS\n+\tselect LEDS_TRIGGERS\n+\tdefault y\n+\thelp\n+\t  This option adds a LED trigger for each registered ATA port.\n+\t  It is used to drive disk activity leds connected via GPIO.\n+\n+\t  If unsure, say N.\n+\n config ATA_ACPI\n \tbool \"ATA ACPI Support\"\n \tdepends on ACPI\n--- a/drivers/ata/libata-core.c\n+++ b/drivers/ata/libata-core.c\n@@ -650,6 +650,19 @@ u64 ata_tf_read_block(const struct ata_t\n \treturn block;\n }\n \n+#ifdef CONFIG_ATA_LEDS\n+#define LIBATA_BLINK_DELAY 20 /* ms */\n+static inline void ata_led_act(struct ata_port *ap)\n+{\n+\tunsigned long led_delay = LIBATA_BLINK_DELAY;\n+\n+\tif (unlikely(!ap->ledtrig))\n+\t\treturn;\n+\n+\tled_trigger_blink_oneshot(ap->ledtrig, &led_delay, &led_delay, 0);\n+}\n+#endif\n+\n /**\n  *\tata_build_rw_tf - Build ATA taskfile for given read/write request\n  *\t@tf: Target ATA taskfile\n@@ -4551,6 +4564,9 @@ struct ata_queued_cmd *ata_qc_new_init(s\n \t\tif (tag < 0)\n \t\t\treturn NULL;\n \t}\n+#ifdef CONFIG_ATA_LEDS\n+\tata_led_act(ap);\n+#endif\n \n \tqc = __ata_qc_from_tag(ap, tag);\n \tqc->tag = qc->hw_tag = tag;\n@@ -5329,6 +5345,9 @@ struct ata_port *ata_port_alloc(struct a\n \tap->stats.unhandled_irq = 1;\n \tap->stats.idle_irq = 1;\n #endif\n+#ifdef CONFIG_ATA_LEDS\n+\tap->ledtrig = kzalloc(sizeof(struct led_trigger), GFP_KERNEL);\n+#endif\n \tata_sff_port_init(ap);\n \n \treturn ap;\n@@ -5364,6 +5383,12 @@ static void ata_host_release(struct kref\n \n \t\tkfree(ap->pmp_link);\n \t\tkfree(ap->slave_link);\n+#ifdef CONFIG_ATA_LEDS\n+\t\tif (ap->ledtrig) {\n+\t\t\tled_trigger_unregister(ap->ledtrig);\n+\t\t\tkfree(ap->ledtrig);\n+\t\t};\n+#endif\n \t\tkfree(ap);\n \t\thost->ports[i] = NULL;\n \t}\n@@ -5770,7 +5795,23 @@ int ata_host_register(struct ata_host *h\n \t\thost->ports[i]->print_id = atomic_inc_return(&ata_print_id);\n \t\thost->ports[i]->local_port_no = i + 1;\n \t}\n+#ifdef CONFIG_ATA_LEDS\n+\tfor (i = 0; i < host->n_ports; i++) {\n+\t\tif (unlikely(!host->ports[i]->ledtrig))\n+\t\t\tcontinue;\n \n+\t\tsnprintf(host->ports[i]->ledtrig_name,\n+\t\t\tsizeof(host->ports[i]->ledtrig_name), \"ata%u\",\n+\t\t\thost->ports[i]->print_id);\n+\n+\t\thost->ports[i]->ledtrig->name = host->ports[i]->ledtrig_name;\n+\n+\t\tif (led_trigger_register(host->ports[i]->ledtrig)) {\n+\t\t\tkfree(host->ports[i]->ledtrig);\n+\t\t\thost->ports[i]->ledtrig = NULL;\n+\t\t}\n+\t}\n+#endif\n \t/* Create associated sysfs transport objects  */\n \tfor (i = 0; i < host->n_ports; i++) {\n \t\trc = ata_tport_add(host->dev,host->ports[i]);\n--- a/include/linux/libata.h\n+++ b/include/linux/libata.h\n@@ -23,6 +23,9 @@\n #include <linux/cdrom.h>\n #include <linux/sched.h>\n #include <linux/async.h>\n+#ifdef CONFIG_ATA_LEDS\n+#include <linux/leds.h>\n+#endif\n \n /*\n  * Define if arch has non-standard setup.  This is a _PCI_ standard\n@@ -883,6 +886,12 @@ struct ata_port {\n #ifdef CONFIG_ATA_ACPI\n \tstruct ata_acpi_gtm\t__acpi_init_gtm; /* use ata_acpi_init_gtm() */\n #endif\n+\n+#ifdef CONFIG_ATA_LEDS\n+\tstruct led_trigger\t*ledtrig;\n+\tchar\t\t\tledtrig_name[8];\n+#endif\n+\n \t/* owned by EH */\n \tu8\t\t\tsector_buf[ATA_SECT_SIZE] ____cacheline_aligned;\n };\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/840-hwrng-bcm2835-set-quality-to-1000.patch",
    "content": "From d6988cf1d16faac56899918bb2b1be8d85155e3f Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com>\nDate: Sat, 20 Feb 2021 18:36:38 +0100\nSubject: [PATCH] hwrng: bcm2835: set quality to 1000\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nThis allows devices without a high precission timer to reduce boot from >100s\nto <30s.\n\nSigned-off-by: Álvaro Fernández Rojas <noltari@gmail.com>\n---\n drivers/char/hw_random/bcm2835-rng.c | 1 +\n 1 file changed, 1 insertion(+)\n\n--- a/drivers/char/hw_random/bcm2835-rng.c\n+++ b/drivers/char/hw_random/bcm2835-rng.c\n@@ -163,6 +163,7 @@ static int bcm2835_rng_probe(struct plat\n \tpriv->rng.init = bcm2835_rng_init;\n \tpriv->rng.read = bcm2835_rng_read;\n \tpriv->rng.cleanup = bcm2835_rng_cleanup;\n+\tpriv->rng.quality = 1000;\n \n \tif (dev_of_node(dev)) {\n \t\trng_id = of_match_node(bcm2835_rng_of_match, dev->of_node);\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/842-net-qmi_wwan-add-ZTE-MF286D-modem-19d2-1485.patch",
    "content": "From 078c6a1cbd4cd7496048786beec2e312577bebbf Mon Sep 17 00:00:00 2001\nFrom: Pawel Dembicki <paweldembicki@gmail.com>\nDate: Tue, 11 Jan 2022 23:11:32 +0100\nSubject: [PATCH] net: qmi_wwan: add ZTE MF286D modem 19d2:1485\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nModem from ZTE MF286D is an Qualcomm MDM9250 based 3G/4G modem.\n\nT:  Bus=02 Lev=01 Prnt=01 Port=00 Cnt=01 Dev#=  3 Spd=5000 MxCh= 0\nD:  Ver= 3.00 Cls=00(>ifc ) Sub=00 Prot=00 MxPS= 9 #Cfgs=  1\nP:  Vendor=19d2 ProdID=1485 Rev=52.87\nS:  Manufacturer=ZTE,Incorporated\nS:  Product=ZTE Technologies MSM\nS:  SerialNumber=MF286DZTED000000\nC:* #Ifs= 7 Cfg#= 1 Atr=80 MxPwr=896mA\nA:  FirstIf#= 0 IfCount= 2 Cls=02(comm.) Sub=06 Prot=00\nI:* If#= 0 Alt= 0 #EPs= 1 Cls=02(comm.) Sub=02 Prot=ff Driver=rndis_host\nE:  Ad=82(I) Atr=03(Int.) MxPS=   8 Ivl=32ms\nI:* If#= 1 Alt= 0 #EPs= 2 Cls=0a(data ) Sub=00 Prot=00 Driver=rndis_host\nE:  Ad=81(I) Atr=02(Bulk) MxPS=1024 Ivl=0ms\nE:  Ad=01(O) Atr=02(Bulk) MxPS=1024 Ivl=0ms\nI:* If#= 2 Alt= 0 #EPs= 2 Cls=ff(vend.) Sub=ff Prot=ff Driver=option\nE:  Ad=83(I) Atr=02(Bulk) MxPS=1024 Ivl=0ms\nE:  Ad=02(O) Atr=02(Bulk) MxPS=1024 Ivl=0ms\nI:* If#= 3 Alt= 0 #EPs= 3 Cls=ff(vend.) Sub=ff Prot=ff Driver=option\nE:  Ad=85(I) Atr=03(Int.) MxPS=  10 Ivl=32ms\nE:  Ad=84(I) Atr=02(Bulk) MxPS=1024 Ivl=0ms\nE:  Ad=03(O) Atr=02(Bulk) MxPS=1024 Ivl=0ms\nI:* If#= 4 Alt= 0 #EPs= 3 Cls=ff(vend.) Sub=ff Prot=ff Driver=option\nE:  Ad=87(I) Atr=03(Int.) MxPS=  10 Ivl=32ms\nE:  Ad=86(I) Atr=02(Bulk) MxPS=1024 Ivl=0ms\nE:  Ad=04(O) Atr=02(Bulk) MxPS=1024 Ivl=0ms\nI:* If#= 5 Alt= 0 #EPs= 3 Cls=ff(vend.) Sub=ff Prot=ff Driver=qmi_wwan\nE:  Ad=88(I) Atr=03(Int.) MxPS=   8 Ivl=32ms\nE:  Ad=8e(I) Atr=02(Bulk) MxPS=1024 Ivl=0ms\nE:  Ad=0f(O) Atr=02(Bulk) MxPS=1024 Ivl=0ms\nI:* If#= 6 Alt= 0 #EPs= 2 Cls=ff(vend.) Sub=42 Prot=01 Driver=usbfs\nE:  Ad=05(O) Atr=02(Bulk) MxPS=1024 Ivl=0ms\nE:  Ad=89(I) Atr=02(Bulk) MxPS=1024 Ivl=0ms\n\nSigned-off-by: Pawel Dembicki <paweldembicki@gmail.com>\nAcked-by: Bjørn Mork <bjorn@mork.no>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/usb/qmi_wwan.c | 1 +\n 1 file changed, 1 insertion(+)\n\n--- a/drivers/net/usb/qmi_wwan.c\n+++ b/drivers/net/usb/qmi_wwan.c\n@@ -1252,6 +1252,7 @@ static const struct usb_device_id produc\n \t{QMI_FIXED_INTF(0x19d2, 0x1426, 2)},\t/* ZTE MF91 */\n \t{QMI_FIXED_INTF(0x19d2, 0x1428, 2)},\t/* Telewell TW-LTE 4G v2 */\n \t{QMI_FIXED_INTF(0x19d2, 0x1432, 3)},\t/* ZTE ME3620 */\n+\t{QMI_FIXED_INTF(0x19d2, 0x1485, 5)},\t/* ZTE MF286D */\n \t{QMI_FIXED_INTF(0x19d2, 0x2002, 4)},\t/* ZTE (Vodafone) K3765-Z */\n \t{QMI_FIXED_INTF(0x2001, 0x7e16, 3)},\t/* D-Link DWM-221 */\n \t{QMI_FIXED_INTF(0x2001, 0x7e19, 4)},\t/* D-Link DWM-221 B1 */\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/850-0001-PCI-aardvark-Replace-custom-PCIE_CORE_INT_-macros-wi.patch",
    "content": "From 43f3f187e6f62ca40802afe39495c8a3e20b4bfa Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>\nDate: Mon, 10 Jan 2022 01:50:50 +0100\nSubject: [PATCH] PCI: aardvark: Replace custom PCIE_CORE_INT_* macros with\n PCI_INTERRUPT_*\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nHeader file linux/pci.h defines enum pci_interrupt_pin with corresponding\nPCI_INTERRUPT_* values.\n\nSigned-off-by: Pali Rohár <pali@kernel.org>\nSigned-off-by: Marek Behún <kabel@kernel.org>\n---\n drivers/pci/controller/pci-aardvark.c | 6 +-----\n 1 file changed, 1 insertion(+), 5 deletions(-)\n\n--- a/drivers/pci/controller/pci-aardvark.c\n+++ b/drivers/pci/controller/pci-aardvark.c\n@@ -37,10 +37,6 @@\n #define     PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN\t\t\tBIT(6)\n #define     PCIE_CORE_ERR_CAPCTL_ECRC_CHCK\t\t\tBIT(7)\n #define     PCIE_CORE_ERR_CAPCTL_ECRC_CHCK_RCV\t\t\tBIT(8)\n-#define     PCIE_CORE_INT_A_ASSERT_ENABLE\t\t\t1\n-#define     PCIE_CORE_INT_B_ASSERT_ENABLE\t\t\t2\n-#define     PCIE_CORE_INT_C_ASSERT_ENABLE\t\t\t3\n-#define     PCIE_CORE_INT_D_ASSERT_ENABLE\t\t\t4\n /* PIO registers base address and register offsets */\n #define PIO_BASE_ADDR\t\t\t\t0x4000\n #define PIO_CTRL\t\t\t\t(PIO_BASE_ADDR + 0x0)\n@@ -968,7 +964,7 @@ static int advk_sw_pci_bridge_init(struc\n \tbridge->conf.pref_mem_limit = cpu_to_le16(PCI_PREF_RANGE_TYPE_64);\n \n \t/* Support interrupt A for MSI feature */\n-\tbridge->conf.intpin = PCIE_CORE_INT_A_ASSERT_ENABLE;\n+\tbridge->conf.intpin = PCI_INTERRUPT_INTA;\n \n \t/* Aardvark HW provides PCIe Capability structure in version 2 */\n \tbridge->pcie_conf.cap = cpu_to_le16(2);\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/850-0002-PCI-aardvark-Fix-reading-MSI-interrupt-number.patch",
    "content": "From a29a7d01cd778854e08108461cba321a63d98871 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>\nDate: Fri, 2 Jul 2021 16:39:47 +0200\nSubject: [PATCH] PCI: aardvark: Fix reading MSI interrupt number\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nIn advk_pcie_handle_msi() the authors expect that when bit i in the W1C\nregister PCIE_MSI_STATUS_REG is cleared, the PCIE_MSI_PAYLOAD_REG is\nupdated to contain the MSI number corresponding to index i.\n\nExperiments show that this is not so, and instead PCIE_MSI_PAYLOAD_REG\nalways contains the number of the last received MSI, overall.\n\nDo not read PCIE_MSI_PAYLOAD_REG register for determining MSI interrupt\nnumber. Since Aardvark already forbids more than 32 interrupts and uses\nown allocated hwirq numbers, the msi_idx already corresponds to the\nreceived MSI number.\n\nFixes: 8c39d710363c (\"PCI: aardvark: Add Aardvark PCI host controller driver\")\nSigned-off-by: Pali Rohár <pali@kernel.org>\nSigned-off-by: Marek Behún <kabel@kernel.org>\n---\n drivers/pci/controller/pci-aardvark.c | 13 ++++++-------\n 1 file changed, 6 insertions(+), 7 deletions(-)\n\n--- a/drivers/pci/controller/pci-aardvark.c\n+++ b/drivers/pci/controller/pci-aardvark.c\n@@ -1391,7 +1391,7 @@ static void advk_pcie_remove_irq_domain(\n static void advk_pcie_handle_msi(struct advk_pcie *pcie)\n {\n \tu32 msi_val, msi_mask, msi_status, msi_idx;\n-\tu16 msi_data;\n+\tint virq;\n \n \tmsi_mask = advk_readl(pcie, PCIE_MSI_MASK_REG);\n \tmsi_val = advk_readl(pcie, PCIE_MSI_STATUS_REG);\n@@ -1401,13 +1401,12 @@ static void advk_pcie_handle_msi(struct\n \t\tif (!(BIT(msi_idx) & msi_status))\n \t\t\tcontinue;\n \n-\t\t/*\n-\t\t * msi_idx contains bits [4:0] of the msi_data and msi_data\n-\t\t * contains 16bit MSI interrupt number\n-\t\t */\n \t\tadvk_writel(pcie, BIT(msi_idx), PCIE_MSI_STATUS_REG);\n-\t\tmsi_data = advk_readl(pcie, PCIE_MSI_PAYLOAD_REG) & PCIE_MSI_DATA_MASK;\n-\t\tgeneric_handle_irq(msi_data);\n+\t\tvirq = irq_find_mapping(pcie->msi_inner_domain, msi_idx);\n+\t\tif (virq)\n+\t\t\tgeneric_handle_irq(virq);\n+\t\telse\n+\t\t\tdev_err_ratelimited(&pcie->pdev->dev, \"unexpected MSI 0x%02x\\n\", msi_idx);\n \t}\n \n \tadvk_writel(pcie, PCIE_ISR0_MSI_INT_PENDING,\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/850-0004-PCI-aardvark-Rewrite-IRQ-code-to-chained-IRQ-handler.patch",
    "content": "From 0cd5141d1866afb23286fe90cd846441fe7aeb39 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>\nDate: Sat, 27 Mar 2021 14:44:11 +0100\nSubject: [PATCH] PCI: aardvark: Rewrite IRQ code to chained IRQ handler\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nRewrite the code to use irq_set_chained_handler_and_data() handler with\nchained_irq_enter() and chained_irq_exit() processing instead of using\ndevm_request_irq().\n\nadvk_pcie_irq_handler() reads IRQ status bits and calls other functions\nbased on which bits are set. These functions then read its own IRQ status\nbits and calls other aardvark functions based on these bits. Finally\ngeneric_handle_domain_irq() with translated linux IRQ numbers are called.\n\nSigned-off-by: Pali Rohár <pali@kernel.org>\nSigned-off-by: Marek Behún <kabel@kernel.org>\n---\n drivers/pci/controller/pci-aardvark.c | 48 +++++++++++++++------------\n 1 file changed, 26 insertions(+), 22 deletions(-)\n\n--- a/drivers/pci/controller/pci-aardvark.c\n+++ b/drivers/pci/controller/pci-aardvark.c\n@@ -275,6 +275,7 @@ struct advk_pcie {\n \t\tu32 actions;\n \t} wins[OB_WIN_COUNT];\n \tu8 wins_count;\n+\tint irq;\n \tstruct irq_domain *irq_domain;\n \tstruct irq_chip irq_chip;\n \traw_spinlock_t irq_lock;\n@@ -1444,21 +1445,26 @@ static void advk_pcie_handle_int(struct\n \t}\n }\n \n-static irqreturn_t advk_pcie_irq_handler(int irq, void *arg)\n+static void advk_pcie_irq_handler(struct irq_desc *desc)\n {\n-\tstruct advk_pcie *pcie = arg;\n-\tu32 status;\n+\tstruct advk_pcie *pcie = irq_desc_get_handler_data(desc);\n+\tstruct irq_chip *chip = irq_desc_get_chip(desc);\n+\tu32 val, mask, status;\n \n-\tstatus = advk_readl(pcie, HOST_CTRL_INT_STATUS_REG);\n-\tif (!(status & PCIE_IRQ_CORE_INT))\n-\t\treturn IRQ_NONE;\n+\tchained_irq_enter(chip, desc);\n \n-\tadvk_pcie_handle_int(pcie);\n+\tval = advk_readl(pcie, HOST_CTRL_INT_STATUS_REG);\n+\tmask = advk_readl(pcie, HOST_CTRL_INT_MASK_REG);\n+\tstatus = val & ((~mask) & PCIE_IRQ_ALL_MASK);\n \n-\t/* Clear interrupt */\n-\tadvk_writel(pcie, PCIE_IRQ_CORE_INT, HOST_CTRL_INT_STATUS_REG);\n+\tif (status & PCIE_IRQ_CORE_INT) {\n+\t\tadvk_pcie_handle_int(pcie);\n \n-\treturn IRQ_HANDLED;\n+\t\t/* Clear interrupt */\n+\t\tadvk_writel(pcie, PCIE_IRQ_CORE_INT, HOST_CTRL_INT_STATUS_REG);\n+\t}\n+\n+\tchained_irq_exit(chip, desc);\n }\n \n static void __maybe_unused advk_pcie_disable_phy(struct advk_pcie *pcie)\n@@ -1525,7 +1531,7 @@ static int advk_pcie_probe(struct platfo\n \tstruct advk_pcie *pcie;\n \tstruct pci_host_bridge *bridge;\n \tstruct resource_entry *entry;\n-\tint ret, irq;\n+\tint ret;\n \n \tbridge = devm_pci_alloc_host_bridge(dev, sizeof(struct advk_pcie));\n \tif (!bridge)\n@@ -1613,17 +1619,9 @@ static int advk_pcie_probe(struct platfo\n \tif (IS_ERR(pcie->base))\n \t\treturn PTR_ERR(pcie->base);\n \n-\tirq = platform_get_irq(pdev, 0);\n-\tif (irq < 0)\n-\t\treturn irq;\n-\n-\tret = devm_request_irq(dev, irq, advk_pcie_irq_handler,\n-\t\t\t       IRQF_SHARED | IRQF_NO_THREAD, \"advk-pcie\",\n-\t\t\t       pcie);\n-\tif (ret) {\n-\t\tdev_err(dev, \"Failed to register interrupt\\n\");\n-\t\treturn ret;\n-\t}\n+\tpcie->irq = platform_get_irq(pdev, 0);\n+\tif (pcie->irq < 0)\n+\t\treturn pcie->irq;\n \n \tpcie->reset_gpio = devm_gpiod_get_from_of_node(dev, dev->of_node,\n \t\t\t\t\t\t       \"reset-gpios\", 0,\n@@ -1672,11 +1670,14 @@ static int advk_pcie_probe(struct platfo\n \t\treturn ret;\n \t}\n \n+\tirq_set_chained_handler_and_data(pcie->irq, advk_pcie_irq_handler, pcie);\n+\n \tbridge->sysdata = pcie;\n \tbridge->ops = &advk_pcie_ops;\n \n \tret = pci_host_probe(bridge);\n \tif (ret < 0) {\n+\t\tirq_set_chained_handler_and_data(pcie->irq, NULL, NULL);\n \t\tadvk_pcie_remove_msi_irq_domain(pcie);\n \t\tadvk_pcie_remove_irq_domain(pcie);\n \t\treturn ret;\n@@ -1724,6 +1725,9 @@ static int advk_pcie_remove(struct platf\n \tadvk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_REG);\n \tadvk_writel(pcie, PCIE_IRQ_ALL_MASK, HOST_CTRL_INT_STATUS_REG);\n \n+\t/* Remove IRQ handler */\n+\tirq_set_chained_handler_and_data(pcie->irq, NULL, NULL);\n+\n \t/* Remove IRQ domains */\n \tadvk_pcie_remove_msi_irq_domain(pcie);\n \tadvk_pcie_remove_irq_domain(pcie);\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/850-0005-PCI-aardvark-Check-return-value-of-generic_handle_do.patch",
    "content": "From 69c1f2c6f45a556361fd8e8d2d4eb20e2c8d3d95 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>\nDate: Thu, 18 Mar 2021 17:04:32 +0100\nSubject: [PATCH] PCI: aardvark: Check return value of\n generic_handle_domain_irq() when processing INTx IRQ\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nIt is possible that we receive spurious INTx interrupt. Check for the\nreturn value of generic_handle_domain_irq() when processing INTx IRQ.\n\nSigned-off-by: Pali Rohár <pali@kernel.org>\nSigned-off-by: Marek Behún <kabel@kernel.org>\n---\n drivers/pci/controller/pci-aardvark.c | 4 +++-\n 1 file changed, 3 insertions(+), 1 deletion(-)\n\n--- a/drivers/pci/controller/pci-aardvark.c\n+++ b/drivers/pci/controller/pci-aardvark.c\n@@ -1441,7 +1441,9 @@ static void advk_pcie_handle_int(struct\n \t\t\t    PCIE_ISR1_REG);\n \n \t\tvirq = irq_find_mapping(pcie->irq_domain, i);\n-\t\tgeneric_handle_irq(virq);\n+\t\tif (generic_handle_irq(virq) == -EINVAL)\n+\t\t\tdev_err_ratelimited(&pcie->pdev->dev, \"unexpected INT%c IRQ\\n\",\n+\t\t\t\t\t    (char)i + 'A');\n \t}\n }\n \n"
  },
  {
    "path": "target/linux/generic/pending-5.10/850-0006-PCI-aardvark-Make-MSI-irq_chip-structures-static-dri.patch",
    "content": "From 5eb36a6b9508da442aac80f4df23e3951bbfa7aa Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Marek=20Beh=C3=BAn?= <kabel@kernel.org>\nDate: Mon, 10 Jan 2022 00:03:41 +0100\nSubject: [PATCH] PCI: aardvark: Make MSI irq_chip structures static driver\n structures\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nMarc Zyngier says [1] that we should use struct irq_chip as a global\nstatic struct in the driver. Even though the structure currently\ncontains a dynamic member (parent_device), Marc says [2] that he plans\nto kill it and make the structure completely static.\n\nConvert Aardvark's priv->msi_bottom_irq_chip and priv->msi_irq_chip to\nstatic driver structure.\n\n[1] https://lore.kernel.org/linux-pci/877dbcvngf.wl-maz@kernel.org/\n[2] https://lore.kernel.org/linux-pci/874k6gvkhz.wl-maz@kernel.org/\n\nSigned-off-by: Marek Behún <kabel@kernel.org>\n---\n drivers/pci/controller/pci-aardvark.c | 26 ++++++++++++--------------\n 1 file changed, 12 insertions(+), 14 deletions(-)\n\n--- a/drivers/pci/controller/pci-aardvark.c\n+++ b/drivers/pci/controller/pci-aardvark.c\n@@ -281,8 +281,6 @@ struct advk_pcie {\n \traw_spinlock_t irq_lock;\n \tstruct irq_domain *msi_domain;\n \tstruct irq_domain *msi_inner_domain;\n-\tstruct irq_chip msi_bottom_irq_chip;\n-\tstruct irq_chip msi_irq_chip;\n \tstruct msi_domain_info msi_domain_info;\n \tDECLARE_BITMAP(msi_used, MSI_IRQ_NUM);\n \tstruct mutex msi_used_lock;\n@@ -1201,6 +1199,12 @@ static int advk_msi_set_affinity(struct\n \treturn -EINVAL;\n }\n \n+static struct irq_chip advk_msi_bottom_irq_chip = {\n+\t.name\t\t\t= \"MSI\",\n+\t.irq_compose_msi_msg\t= advk_msi_irq_compose_msi_msg,\n+\t.irq_set_affinity\t= advk_msi_set_affinity,\n+};\n+\n static int advk_msi_irq_domain_alloc(struct irq_domain *domain,\n \t\t\t\t     unsigned int virq,\n \t\t\t\t     unsigned int nr_irqs, void *args)\n@@ -1217,7 +1221,7 @@ static int advk_msi_irq_domain_alloc(str\n \n \tfor (i = 0; i < nr_irqs; i++)\n \t\tirq_domain_set_info(domain, virq + i, hwirq + i,\n-\t\t\t\t    &pcie->msi_bottom_irq_chip,\n+\t\t\t\t    &advk_msi_bottom_irq_chip,\n \t\t\t\t    domain->host_data, handle_simple_irq,\n \t\t\t\t    NULL, NULL);\n \n@@ -1287,29 +1291,23 @@ static const struct irq_domain_ops advk_\n \t.xlate = irq_domain_xlate_onecell,\n };\n \n+static struct irq_chip advk_msi_irq_chip = {\n+\t.name = \"advk-MSI\",\n+};\n+\n static int advk_pcie_init_msi_irq_domain(struct advk_pcie *pcie)\n {\n \tstruct device *dev = &pcie->pdev->dev;\n \tstruct device_node *node = dev->of_node;\n-\tstruct irq_chip *bottom_ic, *msi_ic;\n \tstruct msi_domain_info *msi_di;\n \tphys_addr_t msi_msg_phys;\n \n \tmutex_init(&pcie->msi_used_lock);\n \n-\tbottom_ic = &pcie->msi_bottom_irq_chip;\n-\n-\tbottom_ic->name = \"MSI\";\n-\tbottom_ic->irq_compose_msi_msg = advk_msi_irq_compose_msi_msg;\n-\tbottom_ic->irq_set_affinity = advk_msi_set_affinity;\n-\n-\tmsi_ic = &pcie->msi_irq_chip;\n-\tmsi_ic->name = \"advk-MSI\";\n-\n \tmsi_di = &pcie->msi_domain_info;\n \tmsi_di->flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |\n \t\tMSI_FLAG_MULTI_PCI_MSI;\n-\tmsi_di->chip = msi_ic;\n+\tmsi_di->chip = &advk_msi_irq_chip;\n \n \tmsi_msg_phys = virt_to_phys(&pcie->msi_msg);\n \n"
  },
  {
    "path": "target/linux/generic/pending-5.10/850-0007-PCI-aardvark-Make-msi_domain_info-structure-a-static.patch",
    "content": "From c092ab8994f1f777054c0179a9deb40b87ee606f Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Marek=20Beh=C3=BAn?= <kabel@kernel.org>\nDate: Mon, 10 Jan 2022 00:10:46 +0100\nSubject: [PATCH] PCI: aardvark: Make msi_domain_info structure a static driver\n structure\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nMake Aardvark's msi_domain_info structure into a private driver structure.\nDomain info is same for every potential instatination of a controller.\n\nSigned-off-by: Marek Behún <kabel@kernel.org>\n---\n drivers/pci/controller/pci-aardvark.c | 16 ++++++++--------\n 1 file changed, 8 insertions(+), 8 deletions(-)\n\n--- a/drivers/pci/controller/pci-aardvark.c\n+++ b/drivers/pci/controller/pci-aardvark.c\n@@ -281,7 +281,6 @@ struct advk_pcie {\n \traw_spinlock_t irq_lock;\n \tstruct irq_domain *msi_domain;\n \tstruct irq_domain *msi_inner_domain;\n-\tstruct msi_domain_info msi_domain_info;\n \tDECLARE_BITMAP(msi_used, MSI_IRQ_NUM);\n \tstruct mutex msi_used_lock;\n \tu16 msi_msg;\n@@ -1295,20 +1294,20 @@ static struct irq_chip advk_msi_irq_chip\n \t.name = \"advk-MSI\",\n };\n \n+static struct msi_domain_info advk_msi_domain_info = {\n+\t.flags\t= MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |\n+\t\t  MSI_FLAG_MULTI_PCI_MSI,\n+\t.chip\t= &advk_msi_irq_chip,\n+};\n+\n static int advk_pcie_init_msi_irq_domain(struct advk_pcie *pcie)\n {\n \tstruct device *dev = &pcie->pdev->dev;\n \tstruct device_node *node = dev->of_node;\n-\tstruct msi_domain_info *msi_di;\n \tphys_addr_t msi_msg_phys;\n \n \tmutex_init(&pcie->msi_used_lock);\n \n-\tmsi_di = &pcie->msi_domain_info;\n-\tmsi_di->flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |\n-\t\tMSI_FLAG_MULTI_PCI_MSI;\n-\tmsi_di->chip = &advk_msi_irq_chip;\n-\n \tmsi_msg_phys = virt_to_phys(&pcie->msi_msg);\n \n \tadvk_writel(pcie, lower_32_bits(msi_msg_phys),\n@@ -1324,7 +1323,8 @@ static int advk_pcie_init_msi_irq_domain\n \n \tpcie->msi_domain =\n \t\tpci_msi_create_irq_domain(of_node_to_fwnode(node),\n-\t\t\t\t\t  msi_di, pcie->msi_inner_domain);\n+\t\t\t\t\t  &advk_msi_domain_info,\n+\t\t\t\t\t  pcie->msi_inner_domain);\n \tif (!pcie->msi_domain) {\n \t\tirq_domain_remove(pcie->msi_inner_domain);\n \t\treturn -ENOMEM;\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/850-0008-PCI-aardvark-Use-dev_fwnode-instead-of-of_node_to_fw.patch",
    "content": "From 59029739d42b439628e2f64f3d8f2db9be97deff Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Marek=20Beh=C3=BAn?= <kabel@kernel.org>\nDate: Mon, 10 Jan 2022 00:15:17 +0100\nSubject: [PATCH] PCI: aardvark: Use dev_fwnode() instead of\n of_node_to_fwnode(dev->of_node)\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nUse simple\n  dev_fwnode(dev)\ninstead of\n  struct device_node *node = dev->of_node;\n  of_node_to_fwnode(node)\nespecially since the node variable is not used elsewhere in the function.\n\nSigned-off-by: Marek Behún <kabel@kernel.org>\n---\n drivers/pci/controller/pci-aardvark.c | 3 +--\n 1 file changed, 1 insertion(+), 2 deletions(-)\n\n--- a/drivers/pci/controller/pci-aardvark.c\n+++ b/drivers/pci/controller/pci-aardvark.c\n@@ -1303,7 +1303,6 @@ static struct msi_domain_info advk_msi_d\n static int advk_pcie_init_msi_irq_domain(struct advk_pcie *pcie)\n {\n \tstruct device *dev = &pcie->pdev->dev;\n-\tstruct device_node *node = dev->of_node;\n \tphys_addr_t msi_msg_phys;\n \n \tmutex_init(&pcie->msi_used_lock);\n@@ -1322,7 +1321,7 @@ static int advk_pcie_init_msi_irq_domain\n \t\treturn -ENOMEM;\n \n \tpcie->msi_domain =\n-\t\tpci_msi_create_irq_domain(of_node_to_fwnode(node),\n+\t\tpci_msi_create_irq_domain(dev_fwnode(dev),\n \t\t\t\t\t  &advk_msi_domain_info,\n \t\t\t\t\t  pcie->msi_inner_domain);\n \tif (!pcie->msi_domain) {\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/850-0009-PCI-aardvark-Refactor-unmasking-summary-MSI-interrup.patch",
    "content": "From 98feaf97bc64fc640a6c5b1394cd18fc7cd7dac8 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>\nDate: Sun, 28 Mar 2021 14:34:49 +0200\nSubject: [PATCH] PCI: aardvark: Refactor unmasking summary MSI interrupt\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nRefactor the masking of ISR0/1 Sources and unmasking of summary MSI interrupt\nso that it corresponds to the comments:\n- first mask all ISR0/1\n- then unmask all MSIs\n- then unmask summary MSI interrupt\n\nSigned-off-by: Pali Rohár <pali@kernel.org>\nSigned-off-by: Marek Behún <kabel@kernel.org>\n---\n drivers/pci/controller/pci-aardvark.c | 10 ++++++----\n 1 file changed, 6 insertions(+), 4 deletions(-)\n\n--- a/drivers/pci/controller/pci-aardvark.c\n+++ b/drivers/pci/controller/pci-aardvark.c\n@@ -578,15 +578,17 @@ static void advk_pcie_setup_hw(struct ad\n \tadvk_writel(pcie, PCIE_IRQ_ALL_MASK, HOST_CTRL_INT_STATUS_REG);\n \n \t/* Disable All ISR0/1 Sources */\n-\treg = PCIE_ISR0_ALL_MASK;\n-\treg &= ~PCIE_ISR0_MSI_INT_PENDING;\n-\tadvk_writel(pcie, reg, PCIE_ISR0_MASK_REG);\n-\n+\tadvk_writel(pcie, PCIE_ISR0_ALL_MASK, PCIE_ISR0_MASK_REG);\n \tadvk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_MASK_REG);\n \n \t/* Unmask all MSIs */\n \tadvk_writel(pcie, ~(u32)PCIE_MSI_ALL_MASK, PCIE_MSI_MASK_REG);\n \n+\t/* Unmask summary MSI interrupt */\n+\treg = advk_readl(pcie, PCIE_ISR0_MASK_REG);\n+\treg &= ~PCIE_ISR0_MSI_INT_PENDING;\n+\tadvk_writel(pcie, reg, PCIE_ISR0_MASK_REG);\n+\n \t/* Enable summary interrupt for GIC SPI source */\n \treg = PCIE_IRQ_ALL_MASK & (~PCIE_IRQ_ENABLE_INTS_MASK);\n \tadvk_writel(pcie, reg, HOST_CTRL_INT_MASK_REG);\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/850-0010-PCI-aardvark-Add-support-for-masking-MSI-interrupts.patch",
    "content": "From 7f353accca6e4a3222991c65b1a6801503973bd3 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>\nDate: Fri, 2 Jul 2021 16:44:10 +0200\nSubject: [PATCH] PCI: aardvark: Add support for masking MSI interrupts\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nWe should not unmask MSIs at setup, but only when kernel asks for them\nto be unmasked.\n\nAt setup, mask all MSIs, and implement IRQ chip callbacks for masking\nand unmasking particular MSIs.\n\nSigned-off-by: Pali Rohár <pali@kernel.org>\nSigned-off-by: Marek Behún <kabel@kernel.org>\n---\n drivers/pci/controller/pci-aardvark.c | 54 ++++++++++++++++++++++++---\n 1 file changed, 49 insertions(+), 5 deletions(-)\n\n--- a/drivers/pci/controller/pci-aardvark.c\n+++ b/drivers/pci/controller/pci-aardvark.c\n@@ -281,6 +281,7 @@ struct advk_pcie {\n \traw_spinlock_t irq_lock;\n \tstruct irq_domain *msi_domain;\n \tstruct irq_domain *msi_inner_domain;\n+\traw_spinlock_t msi_irq_lock;\n \tDECLARE_BITMAP(msi_used, MSI_IRQ_NUM);\n \tstruct mutex msi_used_lock;\n \tu16 msi_msg;\n@@ -577,12 +578,10 @@ static void advk_pcie_setup_hw(struct ad\n \tadvk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_REG);\n \tadvk_writel(pcie, PCIE_IRQ_ALL_MASK, HOST_CTRL_INT_STATUS_REG);\n \n-\t/* Disable All ISR0/1 Sources */\n+\t/* Disable All ISR0/1 and MSI Sources */\n \tadvk_writel(pcie, PCIE_ISR0_ALL_MASK, PCIE_ISR0_MASK_REG);\n \tadvk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_MASK_REG);\n-\n-\t/* Unmask all MSIs */\n-\tadvk_writel(pcie, ~(u32)PCIE_MSI_ALL_MASK, PCIE_MSI_MASK_REG);\n+\tadvk_writel(pcie, PCIE_MSI_ALL_MASK, PCIE_MSI_MASK_REG);\n \n \t/* Unmask summary MSI interrupt */\n \treg = advk_readl(pcie, PCIE_ISR0_MASK_REG);\n@@ -1200,10 +1199,52 @@ static int advk_msi_set_affinity(struct\n \treturn -EINVAL;\n }\n \n+static void advk_msi_irq_mask(struct irq_data *d)\n+{\n+\tstruct advk_pcie *pcie = d->domain->host_data;\n+\tirq_hw_number_t hwirq = irqd_to_hwirq(d);\n+\tunsigned long flags;\n+\tu32 mask;\n+\n+\traw_spin_lock_irqsave(&pcie->msi_irq_lock, flags);\n+\tmask = advk_readl(pcie, PCIE_MSI_MASK_REG);\n+\tmask |= BIT(hwirq);\n+\tadvk_writel(pcie, mask, PCIE_MSI_MASK_REG);\n+\traw_spin_unlock_irqrestore(&pcie->msi_irq_lock, flags);\n+}\n+\n+static void advk_msi_irq_unmask(struct irq_data *d)\n+{\n+\tstruct advk_pcie *pcie = d->domain->host_data;\n+\tirq_hw_number_t hwirq = irqd_to_hwirq(d);\n+\tunsigned long flags;\n+\tu32 mask;\n+\n+\traw_spin_lock_irqsave(&pcie->msi_irq_lock, flags);\n+\tmask = advk_readl(pcie, PCIE_MSI_MASK_REG);\n+\tmask &= ~BIT(hwirq);\n+\tadvk_writel(pcie, mask, PCIE_MSI_MASK_REG);\n+\traw_spin_unlock_irqrestore(&pcie->msi_irq_lock, flags);\n+}\n+\n+static void advk_msi_top_irq_mask(struct irq_data *d)\n+{\n+\tpci_msi_mask_irq(d);\n+\tirq_chip_mask_parent(d);\n+}\n+\n+static void advk_msi_top_irq_unmask(struct irq_data *d)\n+{\n+\tpci_msi_unmask_irq(d);\n+\tirq_chip_unmask_parent(d);\n+}\n+\n static struct irq_chip advk_msi_bottom_irq_chip = {\n \t.name\t\t\t= \"MSI\",\n \t.irq_compose_msi_msg\t= advk_msi_irq_compose_msi_msg,\n \t.irq_set_affinity\t= advk_msi_set_affinity,\n+\t.irq_mask\t\t= advk_msi_irq_mask,\n+\t.irq_unmask\t\t= advk_msi_irq_unmask,\n };\n \n static int advk_msi_irq_domain_alloc(struct irq_domain *domain,\n@@ -1293,7 +1334,9 @@ static const struct irq_domain_ops advk_\n };\n \n static struct irq_chip advk_msi_irq_chip = {\n-\t.name = \"advk-MSI\",\n+\t.name\t\t= \"advk-MSI\",\n+\t.irq_mask\t= advk_msi_top_irq_mask,\n+\t.irq_unmask\t= advk_msi_top_irq_unmask,\n };\n \n static struct msi_domain_info advk_msi_domain_info = {\n@@ -1307,6 +1350,7 @@ static int advk_pcie_init_msi_irq_domain\n \tstruct device *dev = &pcie->pdev->dev;\n \tphys_addr_t msi_msg_phys;\n \n+\traw_spin_lock_init(&pcie->msi_irq_lock);\n \tmutex_init(&pcie->msi_used_lock);\n \n \tmsi_msg_phys = virt_to_phys(&pcie->msi_msg);\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/850-0011-PCI-aardvark-Fix-setting-MSI-address.patch",
    "content": "From fa73c200f181436eab859374657c53a73778d8ad Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>\nDate: Fri, 26 Mar 2021 17:35:44 +0100\nSubject: [PATCH] PCI: aardvark: Fix setting MSI address\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nMSI address for receiving MSI interrupts needs to be correctly set before\nenabling processing of MSI interrupts.\n\nMove code for setting PCIE_MSI_ADDR_LOW_REG and PCIE_MSI_ADDR_HIGH_REG\nfrom advk_pcie_init_msi_irq_domain() to advk_pcie_setup_hw(), before\nenabling PCIE_CORE_CTRL2_MSI_ENABLE.\n\nAfter this we can remove the now unused member msi_msg, which was used\nonly for MSI doorbell address. MSI address can be any address which cannot\nbe used to DMA to. So change it to the address of the main struct advk_pcie.\n\nFixes: 8c39d710363c (\"PCI: aardvark: Add Aardvark PCI host controller driver\")\nSigned-off-by: Pali Rohár <pali@kernel.org>\nAcked-by: Marc Zyngier <maz@kernel.org>\nSigned-off-by: Marek Behún <kabel@kernel.org>\nCc: stable@vger.kernel.org # f21a8b1b6837 (\"PCI: aardvark: Move to MSI handling using generic MSI support\")\n---\n drivers/pci/controller/pci-aardvark.c | 21 +++++++++------------\n 1 file changed, 9 insertions(+), 12 deletions(-)\n\n--- a/drivers/pci/controller/pci-aardvark.c\n+++ b/drivers/pci/controller/pci-aardvark.c\n@@ -284,7 +284,6 @@ struct advk_pcie {\n \traw_spinlock_t msi_irq_lock;\n \tDECLARE_BITMAP(msi_used, MSI_IRQ_NUM);\n \tstruct mutex msi_used_lock;\n-\tu16 msi_msg;\n \tint link_gen;\n \tstruct pci_bridge_emul bridge;\n \tstruct gpio_desc *reset_gpio;\n@@ -479,6 +478,7 @@ static void advk_pcie_disable_ob_win(str\n \n static void advk_pcie_setup_hw(struct advk_pcie *pcie)\n {\n+\tphys_addr_t msi_addr;\n \tu32 reg;\n \tint i;\n \n@@ -567,6 +567,11 @@ static void advk_pcie_setup_hw(struct ad\n \treg |= LANE_COUNT_1;\n \tadvk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);\n \n+\t/* Set MSI address */\n+\tmsi_addr = virt_to_phys(pcie);\n+\tadvk_writel(pcie, lower_32_bits(msi_addr), PCIE_MSI_ADDR_LOW_REG);\n+\tadvk_writel(pcie, upper_32_bits(msi_addr), PCIE_MSI_ADDR_HIGH_REG);\n+\n \t/* Enable MSI */\n \treg = advk_readl(pcie, PCIE_CORE_CTRL2_REG);\n \treg |= PCIE_CORE_CTRL2_MSI_ENABLE;\n@@ -1186,10 +1191,10 @@ static void advk_msi_irq_compose_msi_msg\n \t\t\t\t\t struct msi_msg *msg)\n {\n \tstruct advk_pcie *pcie = irq_data_get_irq_chip_data(data);\n-\tphys_addr_t msi_msg = virt_to_phys(&pcie->msi_msg);\n+\tphys_addr_t msi_addr = virt_to_phys(pcie);\n \n-\tmsg->address_lo = lower_32_bits(msi_msg);\n-\tmsg->address_hi = upper_32_bits(msi_msg);\n+\tmsg->address_lo = lower_32_bits(msi_addr);\n+\tmsg->address_hi = upper_32_bits(msi_addr);\n \tmsg->data = data->hwirq;\n }\n \n@@ -1348,18 +1353,10 @@ static struct msi_domain_info advk_msi_d\n static int advk_pcie_init_msi_irq_domain(struct advk_pcie *pcie)\n {\n \tstruct device *dev = &pcie->pdev->dev;\n-\tphys_addr_t msi_msg_phys;\n \n \traw_spin_lock_init(&pcie->msi_irq_lock);\n \tmutex_init(&pcie->msi_used_lock);\n \n-\tmsi_msg_phys = virt_to_phys(&pcie->msi_msg);\n-\n-\tadvk_writel(pcie, lower_32_bits(msi_msg_phys),\n-\t\t    PCIE_MSI_ADDR_LOW_REG);\n-\tadvk_writel(pcie, upper_32_bits(msi_msg_phys),\n-\t\t    PCIE_MSI_ADDR_HIGH_REG);\n-\n \tpcie->msi_inner_domain =\n \t\tirq_domain_add_linear(NULL, MSI_IRQ_NUM,\n \t\t\t\t      &advk_msi_domain_ops, pcie);\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/850-0012-PCI-aardvark-Enable-MSI-X-support.patch",
    "content": "From 735a4ac9782b96fbe1543c578aa8334364f21abd Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>\nDate: Fri, 2 Apr 2021 14:05:24 +0200\nSubject: [PATCH] PCI: aardvark: Enable MSI-X support\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nAccording to PCI 3.0 specification, sending both MSI and MSI-X interrupts\nis done by DWORD memory write operation to doorbell message address. The\nwrite operation for MSI has zero upper 16 bits and the MSI interrupt number\nin the lower 16 bits, while the write operation for MSI-X contains a 32-bit\nvalue from MSI-X table.\n\nSince the driver only uses interrupt numbers from range 0..31, the upper\n16 bits of the DWORD memory write operation to doorbell message address\nare zero even for MSI-X interrupts. Thus we can enable MSI-X interrupts.\n\nTesting proves that kernel can correctly receive MSI-X interrupts from PCIe\ncards which supports both MSI and MSI-X interrupts.\n\nSigned-off-by: Pali Rohár <pali@kernel.org>\nSigned-off-by: Marek Behún <kabel@kernel.org>\n---\n drivers/pci/controller/pci-aardvark.c | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/drivers/pci/controller/pci-aardvark.c\n+++ b/drivers/pci/controller/pci-aardvark.c\n@@ -1346,7 +1346,7 @@ static struct irq_chip advk_msi_irq_chip\n \n static struct msi_domain_info advk_msi_domain_info = {\n \t.flags\t= MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |\n-\t\t  MSI_FLAG_MULTI_PCI_MSI,\n+\t\t  MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX,\n \t.chip\t= &advk_msi_irq_chip,\n };\n \n"
  },
  {
    "path": "target/linux/generic/pending-5.10/850-0013-PCI-aardvark-Add-support-for-ERR-interrupt-on-emulat.patch",
    "content": "From 7f3e55a3890fa26d15e2e4e90213962d1a7f6df9 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>\nDate: Fri, 12 Feb 2021 20:32:55 +0100\nSubject: [PATCH] PCI: aardvark: Add support for ERR interrupt on emulated\n bridge\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nERR interrupt is triggered when corresponding bit is unmasked in both ISR0\nand PCI_EXP_DEVCTL registers. Unmasking ERR bits in PCI_EXP_DEVCTL register\nis not enough. This means that currently the ERR interrupt is never\ntriggered.\n\nUnmask ERR bits in ISR0 register at driver probe time. ERR interrupt is not\ntriggered until ERR bits are unmasked also in PCI_EXP_DEVCTL register,\nwhich is done by AER driver. So it is safe to unconditionally unmask all\nERR bits in aardvark probe.\n\nAardvark HW sets PCI_ERR_ROOT_AER_IRQ to zero and when corresponding bits\nin ISR0 and PCI_EXP_DEVCTL are enabled, the HW triggers a generic interrupt\non GIC. Chain this interrupt to PCIe interrupt 0 with\ngeneric_handle_domain_irq() to allow processing of ERR interrupts.\n\nSigned-off-by: Pali Rohár <pali@kernel.org>\nSigned-off-by: Marek Behún <kabel@kernel.org>\n---\n drivers/pci/controller/pci-aardvark.c | 36 ++++++++++++++++++++++++++-\n 1 file changed, 35 insertions(+), 1 deletion(-)\n\n--- a/drivers/pci/controller/pci-aardvark.c\n+++ b/drivers/pci/controller/pci-aardvark.c\n@@ -97,6 +97,10 @@\n #define PCIE_MSG_PM_PME_MASK\t\t\tBIT(7)\n #define PCIE_ISR0_MASK_REG\t\t\t(CONTROL_BASE_ADDR + 0x44)\n #define     PCIE_ISR0_MSI_INT_PENDING\t\tBIT(24)\n+#define     PCIE_ISR0_CORR_ERR\t\t\tBIT(11)\n+#define     PCIE_ISR0_NFAT_ERR\t\t\tBIT(12)\n+#define     PCIE_ISR0_FAT_ERR\t\t\tBIT(13)\n+#define     PCIE_ISR0_ERR_MASK\t\t\tGENMASK(13, 11)\n #define     PCIE_ISR0_INTX_ASSERT(val)\t\tBIT(16 + (val))\n #define     PCIE_ISR0_INTX_DEASSERT(val)\tBIT(20 + (val))\n #define     PCIE_ISR0_ALL_MASK\t\t\tGENMASK(31, 0)\n@@ -785,11 +789,15 @@ advk_pci_bridge_emul_base_conf_read(stru\n \tcase PCI_INTERRUPT_LINE: {\n \t\t/*\n \t\t * From the whole 32bit register we support reading from HW only\n-\t\t * one bit: PCI_BRIDGE_CTL_BUS_RESET.\n+\t\t * two bits: PCI_BRIDGE_CTL_BUS_RESET and PCI_BRIDGE_CTL_SERR.\n \t\t * Other bits are retrieved only from emulated config buffer.\n \t\t */\n \t\t__le32 *cfgspace = (__le32 *)&bridge->conf;\n \t\tu32 val = le32_to_cpu(cfgspace[PCI_INTERRUPT_LINE / 4]);\n+\t\tif (advk_readl(pcie, PCIE_ISR0_MASK_REG) & PCIE_ISR0_ERR_MASK)\n+\t\t\tval &= ~(PCI_BRIDGE_CTL_SERR << 16);\n+\t\telse\n+\t\t\tval |= PCI_BRIDGE_CTL_SERR << 16;\n \t\tif (advk_readl(pcie, PCIE_CORE_CTRL1_REG) & HOT_RESET_GEN)\n \t\t\tval |= PCI_BRIDGE_CTL_BUS_RESET << 16;\n \t\telse\n@@ -815,6 +823,19 @@ advk_pci_bridge_emul_base_conf_write(str\n \t\tbreak;\n \n \tcase PCI_INTERRUPT_LINE:\n+\t\t/*\n+\t\t * According to Figure 6-3: Pseudo Logic Diagram for Error\n+\t\t * Message Controls in PCIe base specification, SERR# Enable bit\n+\t\t * in Bridge Control register enable receiving of ERR_* messages\n+\t\t */\n+\t\tif (mask & (PCI_BRIDGE_CTL_SERR << 16)) {\n+\t\t\tu32 val = advk_readl(pcie, PCIE_ISR0_MASK_REG);\n+\t\t\tif (new & (PCI_BRIDGE_CTL_SERR << 16))\n+\t\t\t\tval &= ~PCIE_ISR0_ERR_MASK;\n+\t\t\telse\n+\t\t\t\tval |= PCIE_ISR0_ERR_MASK;\n+\t\t\tadvk_writel(pcie, val, PCIE_ISR0_MASK_REG);\n+\t\t}\n \t\tif (mask & (PCI_BRIDGE_CTL_BUS_RESET << 16)) {\n \t\t\tu32 val = advk_readl(pcie, PCIE_CORE_CTRL1_REG);\n \t\t\tif (new & (PCI_BRIDGE_CTL_BUS_RESET << 16))\n@@ -1468,6 +1489,19 @@ static void advk_pcie_handle_int(struct\n \tisr1_mask = advk_readl(pcie, PCIE_ISR1_MASK_REG);\n \tisr1_status = isr1_val & ((~isr1_mask) & PCIE_ISR1_ALL_MASK);\n \n+\t/* Process ERR interrupt */\n+\tif (isr0_status & PCIE_ISR0_ERR_MASK) {\n+\t\tadvk_writel(pcie, PCIE_ISR0_ERR_MASK, PCIE_ISR0_REG);\n+\n+\t\t/*\n+\t\t * Aardvark HW returns zero for PCI_ERR_ROOT_AER_IRQ, so use\n+\t\t * PCIe interrupt 0\n+\t\t */\n+\t\tvirq = irq_find_mapping(pcie->irq_domain, 0);\n+\t\tif (generic_handle_irq(virq) == -EINVAL)\n+\t\t\tdev_err_ratelimited(&pcie->pdev->dev, \"unhandled ERR IRQ\\n\");\n+\t}\n+\n \t/* Process MSI interrupts */\n \tif (isr0_status & PCIE_ISR0_MSI_INT_PENDING)\n \t\tadvk_pcie_handle_msi(pcie);\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/850-0015-PCI-aardvark-Optimize-writing-PCI_EXP_RTCTL_PMEIE-an.patch",
    "content": "From 3fe0073d116d9902df08761c1cf0d733dd4c38fc Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>\nDate: Wed, 8 Dec 2021 06:03:50 +0100\nSubject: [PATCH] PCI: aardvark: Optimize writing PCI_EXP_RTCTL_PMEIE and\n PCI_EXP_RTSTA_PME on emulated bridge\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nTo optimize advk_pci_bridge_emul_pcie_conf_write() code, touch\nPCIE_ISR0_REG and PCIE_ISR0_MASK_REG registers only when it is really\nneeded, when processing PCI_EXP_RTCTL_PMEIE and PCI_EXP_RTSTA_PME bits.\n\nSigned-off-by: Pali Rohár <pali@kernel.org>\nSigned-off-by: Marek Behún <kabel@kernel.org>\n---\n drivers/pci/controller/pci-aardvark.c | 20 +++++++++++---------\n 1 file changed, 11 insertions(+), 9 deletions(-)\n\n--- a/drivers/pci/controller/pci-aardvark.c\n+++ b/drivers/pci/controller/pci-aardvark.c\n@@ -932,19 +932,21 @@ advk_pci_bridge_emul_pcie_conf_write(str\n \t\t\tadvk_pcie_wait_for_retrain(pcie);\n \t\tbreak;\n \n-\tcase PCI_EXP_RTCTL: {\n+\tcase PCI_EXP_RTCTL:\n \t\t/* Only mask/unmask PME interrupt */\n-\t\tu32 val = advk_readl(pcie, PCIE_ISR0_MASK_REG) &\n-\t\t\t~PCIE_MSG_PM_PME_MASK;\n-\t\tif ((new & PCI_EXP_RTCTL_PMEIE) == 0)\n-\t\t\tval |= PCIE_MSG_PM_PME_MASK;\n-\t\tadvk_writel(pcie, val, PCIE_ISR0_MASK_REG);\n+\t\tif (mask & PCI_EXP_RTCTL_PMEIE) {\n+\t\t\tu32 val = advk_readl(pcie, PCIE_ISR0_MASK_REG);\n+\t\t\tif (new & PCI_EXP_RTCTL_PMEIE)\n+\t\t\t\tval &= ~PCIE_MSG_PM_PME_MASK;\n+\t\t\telse\n+\t\t\t\tval |= PCIE_MSG_PM_PME_MASK;\n+\t\t\tadvk_writel(pcie, val, PCIE_ISR0_MASK_REG);\n+\t\t}\n \t\tbreak;\n-\t}\n \n \tcase PCI_EXP_RTSTA:\n-\t\tnew = (new & PCI_EXP_RTSTA_PME) >> 9;\n-\t\tadvk_writel(pcie, new, PCIE_ISR0_REG);\n+\t\tif (new & PCI_EXP_RTSTA_PME)\n+\t\t\tadvk_writel(pcie, PCIE_MSG_PM_PME_MASK, PCIE_ISR0_REG);\n \t\tbreak;\n \n \tcase PCI_EXP_DEVCTL:\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/850-0016-PCI-aardvark-Add-support-for-PME-interrupts.patch",
    "content": "From 7acd8ef92e8789e10b5d736d73cea3b625087f26 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>\nDate: Wed, 8 Dec 2021 06:07:44 +0100\nSubject: [PATCH] PCI: aardvark: Add support for PME interrupts\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nCurrently enabling PCI_EXP_RTSTA_PME bit in PCI_EXP_RTCTL register does\nnothing. This is because PCIe PME driver expects to receive PCIe interrupt\ndefined in PCI_EXP_FLAGS_IRQ register, but aardvark hardware does not\ntrigger PCIe INTx/MSI interrupt for PME event, rather it triggers custom\naardvark interrupt which this driver is not processing yet.\n\nFix this issue by handling PME interrupt in advk_pcie_handle_int() and\nchaining it to PCIe interrupt 0 with generic_handle_domain_irq() (since\naardvark sets PCI_EXP_FLAGS_IRQ to zero). With this change PCIe PME driver\nfinally starts receiving PME interrupt.\n\nSigned-off-by: Pali Rohár <pali@kernel.org>\nSigned-off-by: Marek Behún <kabel@kernel.org>\n---\n drivers/pci/controller/pci-aardvark.c | 13 +++++++++++++\n 1 file changed, 13 insertions(+)\n\n--- a/drivers/pci/controller/pci-aardvark.c\n+++ b/drivers/pci/controller/pci-aardvark.c\n@@ -1491,6 +1491,19 @@ static void advk_pcie_handle_int(struct\n \tisr1_mask = advk_readl(pcie, PCIE_ISR1_MASK_REG);\n \tisr1_status = isr1_val & ((~isr1_mask) & PCIE_ISR1_ALL_MASK);\n \n+\t/* Process PME interrupt */\n+\tif (isr0_status & PCIE_MSG_PM_PME_MASK) {\n+\t\t/*\n+\t\t * Do not clear PME interrupt bit in ISR0, it is cleared by IRQ\n+\t\t * receiver by writing to the PCI_EXP_RTSTA register of emulated\n+\t\t * root bridge. Aardvark HW returns zero for PCI_EXP_FLAGS_IRQ,\n+\t\t * so use PCIe interrupt 0.\n+\t\t */\n+\t\tvirq = irq_find_mapping(pcie->irq_domain, 0);\n+\t\tif (generic_handle_irq(virq) == -EINVAL)\n+\t\t\tdev_err_ratelimited(&pcie->pdev->dev, \"unhandled PME IRQ\\n\");\n+\t}\n+\n \t/* Process ERR interrupt */\n \tif (isr0_status & PCIE_ISR0_ERR_MASK) {\n \t\tadvk_writel(pcie, PCIE_ISR0_ERR_MASK, PCIE_ISR0_REG);\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/850-0017-PCI-aardvark-Fix-support-for-PME-requester-on-emulat.patch",
    "content": "From 68727b545332327b4c2f9c0f8d006be8970e7832 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>\nDate: Fri, 19 Feb 2021 14:22:22 +0100\nSubject: [PATCH] PCI: aardvark: Fix support for PME requester on emulated\n bridge\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nEnable aardvark PME interrupt unconditionally by unmasking it and read PME\nrequester ID to emulated bridge config space immediately after receiving\ninterrupt.\n\nPME requester ID is stored in the PCIE_MSG_LOG_REG register, which contains\nthe last inbound message. So when new inbound message is received by HW\n(including non-PM), the content in PCIE_MSG_LOG_REG register is replaced by\na new value.\n\nPCIe specification mandates that subsequent PMEs are kept pending until the\nPME Status Register bit is cleared by software by writing a 1b.\n\nSupport for masking/unmasking PME interrupt on emulated bridge via\nPCI_EXP_RTCTL_PMEIE bit is now implemented only in emulated bridge config\nspace, to ensure that we do not miss any aardvark PME interrupt.\n\nReading of PCI_EXP_RTCAP and PCI_EXP_RTSTA registers is simplified as final\nvalue is now always stored into emulated bridge config space by the\ninterrupt handler, so there is no need to implement support for these\nregisters in read_pcie callback.\n\nClearing of W1C bit PCI_EXP_RTSTA_PME is now also simplified as it is done\nby pci-bridge-emul.c code for emulated bridge config space. So there is no\nneed to implement support for clearing this bit in write_pcie callback.\n\nSigned-off-by: Pali Rohár <pali@kernel.org>\nSigned-off-by: Marek Behún <kabel@kernel.org>\n---\n drivers/pci/controller/pci-aardvark.c | 94 +++++++++++++++------------\n 1 file changed, 52 insertions(+), 42 deletions(-)\n\n--- a/drivers/pci/controller/pci-aardvark.c\n+++ b/drivers/pci/controller/pci-aardvark.c\n@@ -597,6 +597,11 @@ static void advk_pcie_setup_hw(struct ad\n \treg &= ~PCIE_ISR0_MSI_INT_PENDING;\n \tadvk_writel(pcie, reg, PCIE_ISR0_MASK_REG);\n \n+\t/* Unmask PME interrupt for processing of PME requester */\n+\treg = advk_readl(pcie, PCIE_ISR0_MASK_REG);\n+\treg &= ~PCIE_MSG_PM_PME_MASK;\n+\tadvk_writel(pcie, reg, PCIE_ISR0_MASK_REG);\n+\n \t/* Enable summary interrupt for GIC SPI source */\n \treg = PCIE_IRQ_ALL_MASK & (~PCIE_IRQ_ENABLE_INTS_MASK);\n \tadvk_writel(pcie, reg, HOST_CTRL_INT_MASK_REG);\n@@ -863,22 +868,11 @@ advk_pci_bridge_emul_pcie_conf_read(stru\n \t\t*value = PCI_EXP_SLTSTA_PDS << 16;\n \t\treturn PCI_BRIDGE_EMUL_HANDLED;\n \n-\tcase PCI_EXP_RTCTL: {\n-\t\tu32 val = advk_readl(pcie, PCIE_ISR0_MASK_REG);\n-\t\t*value = (val & PCIE_MSG_PM_PME_MASK) ? 0 : PCI_EXP_RTCTL_PMEIE;\n-\t\t*value |= le16_to_cpu(bridge->pcie_conf.rootctl) & PCI_EXP_RTCTL_CRSSVE;\n-\t\t*value |= PCI_EXP_RTCAP_CRSVIS << 16;\n-\t\treturn PCI_BRIDGE_EMUL_HANDLED;\n-\t}\n-\n-\tcase PCI_EXP_RTSTA: {\n-\t\tu32 isr0 = advk_readl(pcie, PCIE_ISR0_REG);\n-\t\tu32 msglog = advk_readl(pcie, PCIE_MSG_LOG_REG);\n-\t\t*value = msglog >> 16;\n-\t\tif (isr0 & PCIE_MSG_PM_PME_MASK)\n-\t\t\t*value |= PCI_EXP_RTSTA_PME;\n-\t\treturn PCI_BRIDGE_EMUL_HANDLED;\n-\t}\n+\t/*\n+\t * PCI_EXP_RTCTL and PCI_EXP_RTSTA are also supported, but do not need\n+\t * to be handled here, because their values are stored in emulated\n+\t * config space buffer, and we read them from there when needed.\n+\t */\n \n \tcase PCI_EXP_LNKCAP: {\n \t\tu32 val = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + reg);\n@@ -932,22 +926,19 @@ advk_pci_bridge_emul_pcie_conf_write(str\n \t\t\tadvk_pcie_wait_for_retrain(pcie);\n \t\tbreak;\n \n-\tcase PCI_EXP_RTCTL:\n-\t\t/* Only mask/unmask PME interrupt */\n-\t\tif (mask & PCI_EXP_RTCTL_PMEIE) {\n-\t\t\tu32 val = advk_readl(pcie, PCIE_ISR0_MASK_REG);\n-\t\t\tif (new & PCI_EXP_RTCTL_PMEIE)\n-\t\t\t\tval &= ~PCIE_MSG_PM_PME_MASK;\n-\t\t\telse\n-\t\t\t\tval |= PCIE_MSG_PM_PME_MASK;\n-\t\t\tadvk_writel(pcie, val, PCIE_ISR0_MASK_REG);\n-\t\t}\n+\tcase PCI_EXP_RTCTL: {\n+\t\tu16 rootctl = le16_to_cpu(bridge->pcie_conf.rootctl);\n+\t\t/* Only emulation of PMEIE and CRSSVE bits is provided */\n+\t\trootctl &= PCI_EXP_RTCTL_PMEIE | PCI_EXP_RTCTL_CRSSVE;\n+\t\tbridge->pcie_conf.rootctl = cpu_to_le16(rootctl);\n \t\tbreak;\n+\t}\n \n-\tcase PCI_EXP_RTSTA:\n-\t\tif (new & PCI_EXP_RTSTA_PME)\n-\t\t\tadvk_writel(pcie, PCIE_MSG_PM_PME_MASK, PCIE_ISR0_REG);\n-\t\tbreak;\n+\t/*\n+\t * PCI_EXP_RTSTA is also supported, but does not need to be handled\n+\t * here, because its value is stored in emulated config space buffer,\n+\t * and we write it there when needed.\n+\t */\n \n \tcase PCI_EXP_DEVCTL:\n \tcase PCI_EXP_DEVCTL2:\n@@ -1452,6 +1443,34 @@ static void advk_pcie_remove_irq_domain(\n \tirq_domain_remove(pcie->irq_domain);\n }\n \n+static void advk_pcie_handle_pme(struct advk_pcie *pcie)\n+{\n+\tu32 requester = advk_readl(pcie, PCIE_MSG_LOG_REG) >> 16;\n+\tint virq;\n+\n+\tadvk_writel(pcie, PCIE_MSG_PM_PME_MASK, PCIE_ISR0_REG);\n+\n+\t/*\n+\t * PCIE_MSG_LOG_REG contains the last inbound message, so store\n+\t * the requester ID only when PME was not asserted yet.\n+\t * Also do not trigger PME interrupt when PME is still asserted.\n+\t */\n+\tif (!(le32_to_cpu(pcie->bridge.pcie_conf.rootsta) & PCI_EXP_RTSTA_PME)) {\n+\t\tpcie->bridge.pcie_conf.rootsta = cpu_to_le32(requester | PCI_EXP_RTSTA_PME);\n+\n+\t\t/*\n+\t\t * Trigger PME interrupt only if PMEIE bit in Root Control is set.\n+\t\t * Aardvark HW returns zero for PCI_EXP_FLAGS_IRQ, so use PCIe interrupt 0.\n+\t\t */\n+\t\tif (!(le16_to_cpu(pcie->bridge.pcie_conf.rootctl) & PCI_EXP_RTCTL_PMEIE))\n+\t\t\treturn;\n+\n+\t\tvirq = irq_find_mapping(pcie->irq_domain, 0);\n+\t\tif (generic_handle_irq(virq) == -EINVAL)\n+\t\t\tdev_err_ratelimited(&pcie->pdev->dev, \"unhandled PME IRQ\\n\");\n+\t}\n+}\n+\n static void advk_pcie_handle_msi(struct advk_pcie *pcie)\n {\n \tu32 msi_val, msi_mask, msi_status, msi_idx;\n@@ -1491,18 +1510,9 @@ static void advk_pcie_handle_int(struct\n \tisr1_mask = advk_readl(pcie, PCIE_ISR1_MASK_REG);\n \tisr1_status = isr1_val & ((~isr1_mask) & PCIE_ISR1_ALL_MASK);\n \n-\t/* Process PME interrupt */\n-\tif (isr0_status & PCIE_MSG_PM_PME_MASK) {\n-\t\t/*\n-\t\t * Do not clear PME interrupt bit in ISR0, it is cleared by IRQ\n-\t\t * receiver by writing to the PCI_EXP_RTSTA register of emulated\n-\t\t * root bridge. Aardvark HW returns zero for PCI_EXP_FLAGS_IRQ,\n-\t\t * so use PCIe interrupt 0.\n-\t\t */\n-\t\tvirq = irq_find_mapping(pcie->irq_domain, 0);\n-\t\tif (generic_handle_irq(virq) == -EINVAL)\n-\t\t\tdev_err_ratelimited(&pcie->pdev->dev, \"unhandled PME IRQ\\n\");\n-\t}\n+\t/* Process PME interrupt as the first one to do not miss PME requester id */\n+\tif (isr0_status & PCIE_MSG_PM_PME_MASK)\n+\t\tadvk_pcie_handle_pme(pcie);\n \n \t/* Process ERR interrupt */\n \tif (isr0_status & PCIE_ISR0_ERR_MASK) {\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/850-0018-PCI-aardvark-Use-separate-INTA-interrupt-for-emulate.patch",
    "content": "From db305233136f5aa2444a8287a279384e8458c458 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>\nDate: Thu, 1 Apr 2021 20:12:48 +0200\nSubject: [PATCH] PCI: aardvark: Use separate INTA interrupt for emulated root\n bridge\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nEmulated root bridge currently provides only one Legacy INTA interrupt\nwhich is used for reporting PCIe PME and ERR events and handled by kernel\nPCIe PME and AER drivers.\n\nAardvark HW reports these PME and ERR events separately, so there is no\nneed to mix real INTA interrupt and emulated INTA interrupt for PCIe PME\nand AER drivers.\n\nRegister a new advk-RP (as in Root Port) irq chip and a new irq domain\nfor emulated root bridge and use this new separate irq domain for\nproviding INTA interrupt from emulated root bridge for PME and ERR events.\n\nThe real INTA interrupt from real devices is now separate.\n\nA custom map_irq callback function on PCI host bridge structure is used to\nallocate IRQ mapping for emulated root bridge from new irq domain. Original\ncallback of_irq_parse_and_map_pci() is used for all other devices as before.\n\nSigned-off-by: Pali Rohár <pali@kernel.org>\nSigned-off-by: Marek Behún <kabel@kernel.org>\n---\n drivers/pci/controller/pci-aardvark.c | 69 ++++++++++++++++++++++++++-\n 1 file changed, 67 insertions(+), 2 deletions(-)\n\n--- a/drivers/pci/controller/pci-aardvark.c\n+++ b/drivers/pci/controller/pci-aardvark.c\n@@ -280,6 +280,7 @@ struct advk_pcie {\n \t} wins[OB_WIN_COUNT];\n \tu8 wins_count;\n \tint irq;\n+\tstruct irq_domain *rp_irq_domain;\n \tstruct irq_domain *irq_domain;\n \tstruct irq_chip irq_chip;\n \traw_spinlock_t irq_lock;\n@@ -1443,6 +1444,44 @@ static void advk_pcie_remove_irq_domain(\n \tirq_domain_remove(pcie->irq_domain);\n }\n \n+static struct irq_chip advk_rp_irq_chip = {\n+\t.name = \"advk-RP\",\n+};\n+\n+static int advk_pcie_rp_irq_map(struct irq_domain *h,\n+\t\t\t\tunsigned int virq, irq_hw_number_t hwirq)\n+{\n+\tstruct advk_pcie *pcie = h->host_data;\n+\n+\tirq_set_chip_and_handler(virq, &advk_rp_irq_chip, handle_simple_irq);\n+\tirq_set_chip_data(virq, pcie);\n+\n+\treturn 0;\n+}\n+\n+static const struct irq_domain_ops advk_pcie_rp_irq_domain_ops = {\n+\t.map = advk_pcie_rp_irq_map,\n+\t.xlate = irq_domain_xlate_onecell,\n+};\n+\n+static int advk_pcie_init_rp_irq_domain(struct advk_pcie *pcie)\n+{\n+\tpcie->rp_irq_domain = irq_domain_add_linear(NULL, 1,\n+\t\t\t\t\t\t    &advk_pcie_rp_irq_domain_ops,\n+\t\t\t\t\t\t    pcie);\n+\tif (!pcie->rp_irq_domain) {\n+\t\tdev_err(&pcie->pdev->dev, \"Failed to add Root Port IRQ domain\\n\");\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static void advk_pcie_remove_rp_irq_domain(struct advk_pcie *pcie)\n+{\n+\tirq_domain_remove(pcie->rp_irq_domain);\n+}\n+\n static void advk_pcie_handle_pme(struct advk_pcie *pcie)\n {\n \tu32 requester = advk_readl(pcie, PCIE_MSG_LOG_REG) >> 16;\n@@ -1465,7 +1504,7 @@ static void advk_pcie_handle_pme(struct\n \t\tif (!(le16_to_cpu(pcie->bridge.pcie_conf.rootctl) & PCI_EXP_RTCTL_PMEIE))\n \t\t\treturn;\n \n-\t\tvirq = irq_find_mapping(pcie->irq_domain, 0);\n+\t\tvirq = irq_find_mapping(pcie->rp_irq_domain, 0);\n \t\tif (generic_handle_irq(virq) == -EINVAL)\n \t\t\tdev_err_ratelimited(&pcie->pdev->dev, \"unhandled PME IRQ\\n\");\n \t}\n@@ -1522,7 +1561,7 @@ static void advk_pcie_handle_int(struct\n \t\t * Aardvark HW returns zero for PCI_ERR_ROOT_AER_IRQ, so use\n \t\t * PCIe interrupt 0\n \t\t */\n-\t\tvirq = irq_find_mapping(pcie->irq_domain, 0);\n+\t\tvirq = irq_find_mapping(pcie->rp_irq_domain, 0);\n \t\tif (generic_handle_irq(virq) == -EINVAL)\n \t\t\tdev_err_ratelimited(&pcie->pdev->dev, \"unhandled ERR IRQ\\n\");\n \t}\n@@ -1568,6 +1607,21 @@ static void advk_pcie_irq_handler(struct\n \tchained_irq_exit(chip, desc);\n }\n \n+static int advk_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)\n+{\n+\tstruct advk_pcie *pcie = dev->bus->sysdata;\n+\n+\t/*\n+\t * Emulated root bridge has its own emulated irq chip and irq domain.\n+\t * Argument pin is the INTx pin (1=INTA, 2=INTB, 3=INTC, 4=INTD) and\n+\t * hwirq for irq_create_mapping() is indexed from zero.\n+\t */\n+\tif (pci_is_root_bus(dev->bus))\n+\t\treturn irq_create_mapping(pcie->rp_irq_domain, pin - 1);\n+\telse\n+\t\treturn of_irq_parse_and_map_pci(dev, slot, pin);\n+}\n+\n static void __maybe_unused advk_pcie_disable_phy(struct advk_pcie *pcie)\n {\n \tphy_power_off(pcie->phy);\n@@ -1771,14 +1825,24 @@ static int advk_pcie_probe(struct platfo\n \t\treturn ret;\n \t}\n \n+\tret = advk_pcie_init_rp_irq_domain(pcie);\n+\tif (ret) {\n+\t\tdev_err(dev, \"Failed to initialize irq\\n\");\n+\t\tadvk_pcie_remove_msi_irq_domain(pcie);\n+\t\tadvk_pcie_remove_irq_domain(pcie);\n+\t\treturn ret;\n+\t}\n+\n \tirq_set_chained_handler_and_data(pcie->irq, advk_pcie_irq_handler, pcie);\n \n \tbridge->sysdata = pcie;\n \tbridge->ops = &advk_pcie_ops;\n+\tbridge->map_irq = advk_pcie_map_irq;\n \n \tret = pci_host_probe(bridge);\n \tif (ret < 0) {\n \t\tirq_set_chained_handler_and_data(pcie->irq, NULL, NULL);\n+\t\tadvk_pcie_remove_rp_irq_domain(pcie);\n \t\tadvk_pcie_remove_msi_irq_domain(pcie);\n \t\tadvk_pcie_remove_irq_domain(pcie);\n \t\treturn ret;\n@@ -1830,6 +1894,7 @@ static int advk_pcie_remove(struct platf\n \tirq_set_chained_handler_and_data(pcie->irq, NULL, NULL);\n \n \t/* Remove IRQ domains */\n+\tadvk_pcie_remove_rp_irq_domain(pcie);\n \tadvk_pcie_remove_msi_irq_domain(pcie);\n \tadvk_pcie_remove_irq_domain(pcie);\n \n"
  },
  {
    "path": "target/linux/generic/pending-5.10/850-0019-PCI-aardvark-Remove-irq_mask_ack-callback-for-INTx-i.patch",
    "content": "From 8c9eef96e24f34ff8b62b230700416b822691a37 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>\nDate: Thu, 1 Apr 2021 14:24:12 +0200\nSubject: [PATCH] PCI: aardvark: Remove irq_mask_ack callback for INTx\n interrupts\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nCallback for irq_mask_ack is the same as for irq_mask. As there is no\nspecial handling for irq_ack, there is no need to define irq_mask_ack too.\n\nSigned-off-by: Pali Rohár <pali@kernel.org>\nAcked-by: Marc Zyngier <maz@kernel.org>\nSigned-off-by: Marek Behún <kabel@kernel.org>\n---\n drivers/pci/controller/pci-aardvark.c | 1 -\n 1 file changed, 1 deletion(-)\n\n--- a/drivers/pci/controller/pci-aardvark.c\n+++ b/drivers/pci/controller/pci-aardvark.c\n@@ -1422,7 +1422,6 @@ static int advk_pcie_init_irq_domain(str\n \t}\n \n \tirq_chip->irq_mask = advk_pcie_irq_mask;\n-\tirq_chip->irq_mask_ack = advk_pcie_irq_mask;\n \tirq_chip->irq_unmask = advk_pcie_irq_unmask;\n \n \tpcie->irq_domain =\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/850-0020-PCI-aardvark-Don-t-mask-irq-when-mapping.patch",
    "content": "From dc01fca5a9d9c09ce9a3fb2bc2e7715c37ff3bd9 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>\nDate: Thu, 1 Apr 2021 14:30:06 +0200\nSubject: [PATCH] PCI: aardvark: Don't mask irq when mapping\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nBy default, all Legacy INTx interrupts are masked, so there is no need to\nmask this interrupt during irq_map callback.\n\nSigned-off-by: Pali Rohár <pali@kernel.org>\nSigned-off-by: Marek Behún <kabel@kernel.org>\n---\n drivers/pci/controller/pci-aardvark.c | 1 -\n 1 file changed, 1 deletion(-)\n\n--- a/drivers/pci/controller/pci-aardvark.c\n+++ b/drivers/pci/controller/pci-aardvark.c\n@@ -1339,7 +1339,6 @@ static int advk_pcie_irq_map(struct irq_\n {\n \tstruct advk_pcie *pcie = h->host_data;\n \n-\tadvk_pcie_irq_mask(irq_get_irq_data(virq));\n \tirq_set_status_flags(virq, IRQ_LEVEL);\n \tirq_set_chip_and_handler(virq, &pcie->irq_chip,\n \t\t\t\t handle_level_irq);\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/850-0021-PCI-aardvark-Drop-__maybe_unused-from-advk_pcie_disa.patch",
    "content": "From a511c99262ce19ee06908d27212b39ec4c5aeb17 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Marek=20Beh=C3=BAn?= <kabel@kernel.org>\nDate: Wed, 8 Dec 2021 04:40:29 +0100\nSubject: [PATCH] PCI: aardvark: Drop __maybe_unused from\n advk_pcie_disable_phy()\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nThis function is now always used in driver remove method, drop the\n__maybe_unused attribute.\n\nSigned-off-by: Marek Behún <kabel@kernel.org>\n---\n drivers/pci/controller/pci-aardvark.c | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/drivers/pci/controller/pci-aardvark.c\n+++ b/drivers/pci/controller/pci-aardvark.c\n@@ -1620,7 +1620,7 @@ static int advk_pcie_map_irq(const struc\n \t\treturn of_irq_parse_and_map_pci(dev, slot, pin);\n }\n \n-static void __maybe_unused advk_pcie_disable_phy(struct advk_pcie *pcie)\n+static void advk_pcie_disable_phy(struct advk_pcie *pcie)\n {\n \tphy_power_off(pcie->phy);\n \tphy_exit(pcie->phy);\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/850-0022-PCI-aardvark-Update-comment-about-link-going-down-af.patch",
    "content": "From bafda858364003a70b9cda84282f9761587f8033 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Marek=20Beh=C3=BAn?= <kabel@kernel.org>\nDate: Mon, 10 Jan 2022 00:47:38 +0100\nSubject: [PATCH] PCI: aardvark: Update comment about link going down after\n link-up\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nUpdate the comment about what happens when link goes down after we have\nchecked for link-up. If a PIO request is done while link-down, we have\na serious problem.\n\nSigned-off-by: Marek Behún <kabel@kernel.org>\n---\n drivers/pci/controller/pci-aardvark.c | 8 ++++++--\n 1 file changed, 6 insertions(+), 2 deletions(-)\n\n--- a/drivers/pci/controller/pci-aardvark.c\n+++ b/drivers/pci/controller/pci-aardvark.c\n@@ -1005,8 +1005,12 @@ static bool advk_pcie_valid_device(struc\n \t\treturn false;\n \n \t/*\n-\t * If the link goes down after we check for link-up, nothing bad\n-\t * happens but the config access times out.\n+\t * If the link goes down after we check for link-up, we have a problem:\n+\t * if a PIO request is executed while link-down, the whole controller\n+\t * gets stuck in a non-functional state, and even after link comes up\n+\t * again, PIO requests won't work anymore, and a reset of the whole PCIe\n+\t * controller is needed. Therefore we need to prevent sending PIO\n+\t * requests while the link is down.\n \t */\n \tif (!pci_is_root_bus(bus) && !advk_pcie_link_up(pcie))\n \t\treturn false;\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/850-0023-PCI-aardvark-Make-main-irq_chip-structure-a-static-d.patch",
    "content": "From 663b9f99bb35dbc0c7b685f71ee3668a60d31320 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Marek=20Beh=C3=BAn?= <kabel@kernel.org>\nDate: Mon, 10 Jan 2022 02:02:00 +0100\nSubject: [PATCH] PCI: aardvark: Make main irq_chip structure a static driver\n structure\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nMarc Zyngier says [1] that we should use struct irq_chip as a global\nstatic struct in the driver. Even though the structure currently\ncontains a dynamic member (parent_device), Marc says [2] that he plans\nto kill it and make the structure completely static.\n\nWe have already converted others irq_chip structures in this driver in\nthis way, but we omitted this one because the .name member is\ndynamically created from device's name, and the name is displayed in\nsysfs, so changing it would break sysfs ABI.\n\nThe rationale for changing the name (to \"advk-INT\") in spite of sysfs\nABI, and thus allowing to convert to a static structure, is that after\nthe other changes we made in this series, the IRQ chip is basically\nsomething different: it no logner generates ERR and PME interrupts (they\nare generated by emulated bridge's rp_irq_chip).\n\n[1] https://lore.kernel.org/linux-pci/877dbcvngf.wl-maz@kernel.org/\n[2] https://lore.kernel.org/linux-pci/874k6gvkhz.wl-maz@kernel.org/\n\nSigned-off-by: Marek Behún <kabel@kernel.org>\n---\n drivers/pci/controller/pci-aardvark.c | 25 +++++++------------------\n 1 file changed, 7 insertions(+), 18 deletions(-)\n\n--- a/drivers/pci/controller/pci-aardvark.c\n+++ b/drivers/pci/controller/pci-aardvark.c\n@@ -282,7 +282,6 @@ struct advk_pcie {\n \tint irq;\n \tstruct irq_domain *rp_irq_domain;\n \tstruct irq_domain *irq_domain;\n-\tstruct irq_chip irq_chip;\n \traw_spinlock_t irq_lock;\n \tstruct irq_domain *msi_domain;\n \tstruct irq_domain *msi_inner_domain;\n@@ -1338,14 +1337,19 @@ static void advk_pcie_irq_unmask(struct\n \traw_spin_unlock_irqrestore(&pcie->irq_lock, flags);\n }\n \n+static struct irq_chip advk_irq_chip = {\n+\t.name\t\t= \"advk-INT\",\n+\t.irq_mask\t= advk_pcie_irq_mask,\n+\t.irq_unmask\t= advk_pcie_irq_unmask,\n+};\n+\n static int advk_pcie_irq_map(struct irq_domain *h,\n \t\t\t     unsigned int virq, irq_hw_number_t hwirq)\n {\n \tstruct advk_pcie *pcie = h->host_data;\n \n \tirq_set_status_flags(virq, IRQ_LEVEL);\n-\tirq_set_chip_and_handler(virq, &pcie->irq_chip,\n-\t\t\t\t handle_level_irq);\n+\tirq_set_chip_and_handler(virq, &advk_irq_chip, handle_level_irq);\n \tirq_set_chip_data(virq, pcie);\n \n \treturn 0;\n@@ -1404,7 +1408,6 @@ static int advk_pcie_init_irq_domain(str\n \tstruct device *dev = &pcie->pdev->dev;\n \tstruct device_node *node = dev->of_node;\n \tstruct device_node *pcie_intc_node;\n-\tstruct irq_chip *irq_chip;\n \tint ret = 0;\n \n \traw_spin_lock_init(&pcie->irq_lock);\n@@ -1415,28 +1418,14 @@ static int advk_pcie_init_irq_domain(str\n \t\treturn -ENODEV;\n \t}\n \n-\tirq_chip = &pcie->irq_chip;\n-\n-\tirq_chip->name = devm_kasprintf(dev, GFP_KERNEL, \"%s-irq\",\n-\t\t\t\t\tdev_name(dev));\n-\tif (!irq_chip->name) {\n-\t\tret = -ENOMEM;\n-\t\tgoto out_put_node;\n-\t}\n-\n-\tirq_chip->irq_mask = advk_pcie_irq_mask;\n-\tirq_chip->irq_unmask = advk_pcie_irq_unmask;\n-\n \tpcie->irq_domain =\n \t\tirq_domain_add_linear(pcie_intc_node, PCI_NUM_INTX,\n \t\t\t\t      &advk_pcie_irq_domain_ops, pcie);\n \tif (!pcie->irq_domain) {\n \t\tdev_err(dev, \"Failed to get a INTx IRQ domain\\n\");\n \t\tret = -ENOMEM;\n-\t\tgoto out_put_node;\n \t}\n \n-out_put_node:\n \tof_node_put(pcie_intc_node);\n \treturn ret;\n }\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/851-0001-phy-marvell-phy-mvebu-a3700-comphy-Remove-port-from-.patch",
    "content": "From a719f7ba7fcba05d85801c6f0267f389a21627c1 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>\nDate: Fri, 24 Sep 2021 13:03:02 +0200\nSubject: [PATCH] phy: marvell: phy-mvebu-a3700-comphy: Remove port from driver\n configuration\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nPort number is encoded into argument for SMC call. It is zero for SATA,\nPCIe and also both USB 3.0 PHYs. It is non-zero only for Ethernet PHY\n(incorrectly called SGMII) on lane 0. Ethernet PHY on lane 1 also uses zero\nport number.\n\nSo construct \"port\" bits for SMC call argument can be constructed directly\nfrom PHY type and lane number.\n\nChange driver code to always pass zero port number for non-ethernet PHYs\nand for ethernet PHYs determinate port number from lane number. This\nsimplifies the driver.\n\nAs port number from DT PHY configuration is not used anymore, remove whole\ndriver code which parses it. This also simplifies the driver.\n\nSigned-off-by: Pali Rohár <pali@kernel.org>\nSigned-off-by: Marek Behún <kabel@kernel.org>\nReviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>\n---\n drivers/phy/marvell/phy-mvebu-a3700-comphy.c | 62 +++++++++-----------\n 1 file changed, 29 insertions(+), 33 deletions(-)\n\n--- a/drivers/phy/marvell/phy-mvebu-a3700-comphy.c\n+++ b/drivers/phy/marvell/phy-mvebu-a3700-comphy.c\n@@ -20,7 +20,6 @@\n #include <linux/platform_device.h>\n \n #define MVEBU_A3700_COMPHY_LANES\t\t3\n-#define MVEBU_A3700_COMPHY_PORTS\t\t2\n \n /* COMPHY Fast SMC function identifiers */\n #define COMPHY_SIP_POWER_ON\t\t\t0x82000001\n@@ -45,51 +44,47 @@\n #define COMPHY_FW_NET(mode, idx, speed)\t\t(COMPHY_FW_MODE(mode) | \\\n \t\t\t\t\t\t ((idx) << 8) |\t\\\n \t\t\t\t\t\t ((speed) << 2))\n-#define COMPHY_FW_PCIE(mode, idx, speed, width)\t(COMPHY_FW_NET(mode, idx, speed) | \\\n+#define COMPHY_FW_PCIE(mode, speed, width)\t(COMPHY_FW_NET(mode, 0, speed) | \\\n \t\t\t\t\t\t ((width) << 18))\n \n struct mvebu_a3700_comphy_conf {\n \tunsigned int lane;\n \tenum phy_mode mode;\n \tint submode;\n-\tunsigned int port;\n \tu32 fw_mode;\n };\n \n-#define MVEBU_A3700_COMPHY_CONF(_lane, _mode, _smode, _port, _fw)\t\\\n+#define MVEBU_A3700_COMPHY_CONF(_lane, _mode, _smode, _fw)\t\t\\\n \t{\t\t\t\t\t\t\t\t\\\n \t\t.lane = _lane,\t\t\t\t\t\t\\\n \t\t.mode = _mode,\t\t\t\t\t\t\\\n \t\t.submode = _smode,\t\t\t\t\t\\\n-\t\t.port = _port,\t\t\t\t\t\t\\\n \t\t.fw_mode = _fw,\t\t\t\t\t\t\\\n \t}\n \n-#define MVEBU_A3700_COMPHY_CONF_GEN(_lane, _mode, _port, _fw) \\\n-\tMVEBU_A3700_COMPHY_CONF(_lane, _mode, PHY_INTERFACE_MODE_NA, _port, _fw)\n+#define MVEBU_A3700_COMPHY_CONF_GEN(_lane, _mode, _fw) \\\n+\tMVEBU_A3700_COMPHY_CONF(_lane, _mode, PHY_INTERFACE_MODE_NA, _fw)\n \n-#define MVEBU_A3700_COMPHY_CONF_ETH(_lane, _smode, _port, _fw) \\\n-\tMVEBU_A3700_COMPHY_CONF(_lane, PHY_MODE_ETHERNET, _smode, _port, _fw)\n+#define MVEBU_A3700_COMPHY_CONF_ETH(_lane, _smode, _fw) \\\n+\tMVEBU_A3700_COMPHY_CONF(_lane, PHY_MODE_ETHERNET, _smode, _fw)\n \n static const struct mvebu_a3700_comphy_conf mvebu_a3700_comphy_modes[] = {\n \t/* lane 0 */\n-\tMVEBU_A3700_COMPHY_CONF_GEN(0, PHY_MODE_USB_HOST_SS, 0,\n+\tMVEBU_A3700_COMPHY_CONF_GEN(0, PHY_MODE_USB_HOST_SS,\n \t\t\t\t    COMPHY_FW_MODE_USB3H),\n-\tMVEBU_A3700_COMPHY_CONF_ETH(0, PHY_INTERFACE_MODE_SGMII, 1,\n+\tMVEBU_A3700_COMPHY_CONF_ETH(0, PHY_INTERFACE_MODE_SGMII,\n \t\t\t\t    COMPHY_FW_MODE_SGMII),\n-\tMVEBU_A3700_COMPHY_CONF_ETH(0, PHY_INTERFACE_MODE_2500BASEX, 1,\n+\tMVEBU_A3700_COMPHY_CONF_ETH(0, PHY_INTERFACE_MODE_2500BASEX,\n \t\t\t\t    COMPHY_FW_MODE_2500BASEX),\n \t/* lane 1 */\n-\tMVEBU_A3700_COMPHY_CONF_GEN(1, PHY_MODE_PCIE, 0,\n-\t\t\t\t    COMPHY_FW_MODE_PCIE),\n-\tMVEBU_A3700_COMPHY_CONF_ETH(1, PHY_INTERFACE_MODE_SGMII, 0,\n+\tMVEBU_A3700_COMPHY_CONF_GEN(1, PHY_MODE_PCIE, COMPHY_FW_MODE_PCIE),\n+\tMVEBU_A3700_COMPHY_CONF_ETH(1, PHY_INTERFACE_MODE_SGMII,\n \t\t\t\t    COMPHY_FW_MODE_SGMII),\n-\tMVEBU_A3700_COMPHY_CONF_ETH(1, PHY_INTERFACE_MODE_2500BASEX, 0,\n+\tMVEBU_A3700_COMPHY_CONF_ETH(1, PHY_INTERFACE_MODE_2500BASEX,\n \t\t\t\t    COMPHY_FW_MODE_2500BASEX),\n \t/* lane 2 */\n-\tMVEBU_A3700_COMPHY_CONF_GEN(2, PHY_MODE_SATA, 0,\n-\t\t\t\t    COMPHY_FW_MODE_SATA),\n-\tMVEBU_A3700_COMPHY_CONF_GEN(2, PHY_MODE_USB_HOST_SS, 0,\n+\tMVEBU_A3700_COMPHY_CONF_GEN(2, PHY_MODE_SATA, COMPHY_FW_MODE_SATA),\n+\tMVEBU_A3700_COMPHY_CONF_GEN(2, PHY_MODE_USB_HOST_SS,\n \t\t\t\t    COMPHY_FW_MODE_USB3H),\n };\n \n@@ -98,7 +93,6 @@ struct mvebu_a3700_comphy_lane {\n \tunsigned int id;\n \tenum phy_mode mode;\n \tint submode;\n-\tint port;\n };\n \n static int mvebu_a3700_comphy_smc(unsigned long function, unsigned long lane,\n@@ -120,7 +114,7 @@ static int mvebu_a3700_comphy_smc(unsign\n \t}\n }\n \n-static int mvebu_a3700_comphy_get_fw_mode(int lane, int port,\n+static int mvebu_a3700_comphy_get_fw_mode(int lane,\n \t\t\t\t\t  enum phy_mode mode,\n \t\t\t\t\t  int submode)\n {\n@@ -132,7 +126,6 @@ static int mvebu_a3700_comphy_get_fw_mod\n \n \tfor (i = 0; i < n; i++) {\n \t\tif (mvebu_a3700_comphy_modes[i].lane == lane &&\n-\t\t    mvebu_a3700_comphy_modes[i].port == port &&\n \t\t    mvebu_a3700_comphy_modes[i].mode == mode &&\n \t\t    mvebu_a3700_comphy_modes[i].submode == submode)\n \t\t\tbreak;\n@@ -153,7 +146,7 @@ static int mvebu_a3700_comphy_set_mode(s\n \tif (submode == PHY_INTERFACE_MODE_1000BASEX)\n \t\tsubmode = PHY_INTERFACE_MODE_SGMII;\n \n-\tfw_mode = mvebu_a3700_comphy_get_fw_mode(lane->id, lane->port, mode,\n+\tfw_mode = mvebu_a3700_comphy_get_fw_mode(lane->id, mode,\n \t\t\t\t\t\t submode);\n \tif (fw_mode < 0) {\n \t\tdev_err(lane->dev, \"invalid COMPHY mode\\n\");\n@@ -172,9 +165,10 @@ static int mvebu_a3700_comphy_power_on(s\n \tstruct mvebu_a3700_comphy_lane *lane = phy_get_drvdata(phy);\n \tu32 fw_param;\n \tint fw_mode;\n+\tint fw_port;\n \tint ret;\n \n-\tfw_mode = mvebu_a3700_comphy_get_fw_mode(lane->id, lane->port,\n+\tfw_mode = mvebu_a3700_comphy_get_fw_mode(lane->id,\n \t\t\t\t\t\t lane->mode, lane->submode);\n \tif (fw_mode < 0) {\n \t\tdev_err(lane->dev, \"invalid COMPHY mode\\n\");\n@@ -191,17 +185,18 @@ static int mvebu_a3700_comphy_power_on(s\n \t\tfw_param = COMPHY_FW_MODE(fw_mode);\n \t\tbreak;\n \tcase PHY_MODE_ETHERNET:\n+\t\tfw_port = (lane->id == 0) ? 1 : 0;\n \t\tswitch (lane->submode) {\n \t\tcase PHY_INTERFACE_MODE_SGMII:\n \t\t\tdev_dbg(lane->dev, \"set lane %d to SGMII mode\\n\",\n \t\t\t\tlane->id);\n-\t\t\tfw_param = COMPHY_FW_NET(fw_mode, lane->port,\n+\t\t\tfw_param = COMPHY_FW_NET(fw_mode, fw_port,\n \t\t\t\t\t\t COMPHY_FW_SPEED_1_25G);\n \t\t\tbreak;\n \t\tcase PHY_INTERFACE_MODE_2500BASEX:\n \t\t\tdev_dbg(lane->dev, \"set lane %d to 2500BASEX mode\\n\",\n \t\t\t\tlane->id);\n-\t\t\tfw_param = COMPHY_FW_NET(fw_mode, lane->port,\n+\t\t\tfw_param = COMPHY_FW_NET(fw_mode, fw_port,\n \t\t\t\t\t\t COMPHY_FW_SPEED_3_125G);\n \t\t\tbreak;\n \t\tdefault:\n@@ -212,8 +207,7 @@ static int mvebu_a3700_comphy_power_on(s\n \t\tbreak;\n \tcase PHY_MODE_PCIE:\n \t\tdev_dbg(lane->dev, \"set lane %d to PCIe mode\\n\", lane->id);\n-\t\tfw_param = COMPHY_FW_PCIE(fw_mode, lane->port,\n-\t\t\t\t\t  COMPHY_FW_SPEED_5G,\n+\t\tfw_param = COMPHY_FW_PCIE(fw_mode, COMPHY_FW_SPEED_5G,\n \t\t\t\t\t  phy->attrs.bus_width);\n \t\tbreak;\n \tdefault:\n@@ -247,17 +241,20 @@ static struct phy *mvebu_a3700_comphy_xl\n \t\t\t\t\t    struct of_phandle_args *args)\n {\n \tstruct mvebu_a3700_comphy_lane *lane;\n+\tunsigned int port;\n \tstruct phy *phy;\n \n-\tif (WARN_ON(args->args[0] >= MVEBU_A3700_COMPHY_PORTS))\n-\t\treturn ERR_PTR(-EINVAL);\n-\n \tphy = of_phy_simple_xlate(dev, args);\n \tif (IS_ERR(phy))\n \t\treturn phy;\n \n \tlane = phy_get_drvdata(phy);\n-\tlane->port = args->args[0];\n+\n+\tport = args->args[0];\n+\tif (port != 0 && (port != 1 || lane->id != 0)) {\n+\t\tdev_err(lane->dev, \"invalid port number %u\\n\", port);\n+\t\treturn ERR_PTR(-EINVAL);\n+\t}\n \n \treturn phy;\n }\n@@ -302,7 +299,6 @@ static int mvebu_a3700_comphy_probe(stru\n \t\tlane->mode = PHY_MODE_INVALID;\n \t\tlane->submode = PHY_INTERFACE_MODE_NA;\n \t\tlane->id = lane_id;\n-\t\tlane->port = -1;\n \t\tphy_set_drvdata(phy, lane);\n \t}\n \n"
  },
  {
    "path": "target/linux/generic/pending-5.10/851-0002-phy-marvell-phy-mvebu-a3700-comphy-Add-native-kernel.patch",
    "content": "From 9d276da259cce20b2ed7a868b6e6a6a205f7bb04 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>\nDate: Thu, 23 Sep 2021 19:20:13 +0200\nSubject: [PATCH] phy: marvell: phy-mvebu-a3700-comphy: Add native kernel\n implementation\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nRemove old RPC implementation and add a new native kernel implementation.\n\nThe old implementation uses ARM SMC API to issue RPC calls to ARM Trusted\nFirmware which provides real implementation of PHY configuration.\n\nBut older versions of ARM Trusted Firmware do not provide this PHY\nconfiguration functionality, simply returning: operation not supported; or\nworse, some versions provide the configuration functionality incorrectly.\n\nFor example the firmware shipped in ESPRESSObin board has this older\nversion of ARM Trusted Firmware and therefore SATA, USB 3.0 and PCIe\nfunctionality do not work with newer versions of Linux kernel.\n\nDue to the above reasons, the following commits were introduced into Linux,\nto workaround these issues by ignoring -EOPNOTSUPP error code from\nphy-mvebu-a3700-comphy driver function phy_power_on():\n\ncommit 45aefe3d2251 (\"ata: ahci: mvebu: Make SATA PHY optional for Armada\n3720\")\ncommit 3241929b67d2 (\"usb: host: xhci: mvebu: make USB 3.0 PHY optional for\nArmada 3720\")\ncommit b0c6ae0f8948 (\"PCI: aardvark: Fix initialization with old Marvell's\nArm Trusted Firmware\")\n\nReplace this RPC implementation with proper native kernel implementation,\nwhich is independent on the firmware. Never return -EOPNOTSUPP for proper\narguments.\n\nThis should solve multiple issues with real-world boards, where it is not\npossible or really inconvenient to change the firmware. Let's eliminate\nthese issues.\n\nThis implementation is ported directly from Armada 3720 comphy driver found\nin newest version of ARM Trusted Firmware source code, but with various\nfixes of register names, some added comments, some refactoring due to the\noriginal code not conforming to kernel standards. Also PCIe mode poweroff\nsupport was added here, and PHY reset support. These changes are also going\nto be sent to ARM Trusted Firmware.\n\nSigned-off-by: Pali Rohár <pali@kernel.org>\nAcked-by: Miquel Raynal <miquel.raynal@bootlin.com>\n[ Pali did the porting from ATF.\n  I (Marek) then fixed some register names, some various other things,\n  added some comments and refactored the code to kernel standards. Also\n  fixed PHY poweroff and added PHY reset. ]\nSigned-off-by: Marek Behún <kabel@kernel.org>\n---\n drivers/phy/marvell/phy-mvebu-a3700-comphy.c | 1351 ++++++++++++++++--\n 1 file changed, 1234 insertions(+), 117 deletions(-)\n\n--- a/drivers/phy/marvell/phy-mvebu-a3700-comphy.c\n+++ b/drivers/phy/marvell/phy-mvebu-a3700-comphy.c\n@@ -5,12 +5,16 @@\n  * Authors:\n  *   Evan Wang <xswang@marvell.com>\n  *   Miquèl Raynal <miquel.raynal@bootlin.com>\n+ *   Pali Rohár <pali@kernel.org>\n+ *   Marek Behún <kabel@kernel.org>\n  *\n  * Structure inspired from phy-mvebu-cp110-comphy.c written by Antoine Tenart.\n- * SMC call initial support done by Grzegorz Jaszczyk.\n+ * Comphy code from ARM Trusted Firmware ported by Pali Rohár <pali@kernel.org>\n+ * and Marek Behún <kabel@kernel.org>.\n  */\n \n-#include <linux/arm-smccc.h>\n+#include <linux/bitfield.h>\n+#include <linux/clk.h>\n #include <linux/io.h>\n #include <linux/iopoll.h>\n #include <linux/mfd/syscon.h>\n@@ -18,103 +22,1147 @@\n #include <linux/phy.h>\n #include <linux/phy/phy.h>\n #include <linux/platform_device.h>\n+#include <linux/spinlock.h>\n \n-#define MVEBU_A3700_COMPHY_LANES\t\t3\n+#define PLL_SET_DELAY_US\t\t600\n+#define COMPHY_PLL_SLEEP\t\t1000\n+#define COMPHY_PLL_TIMEOUT\t\t150000\n+\n+/* Comphy lane2 indirect access register offset */\n+#define COMPHY_LANE2_INDIR_ADDR\t\t0x0\n+#define COMPHY_LANE2_INDIR_DATA\t\t0x4\n+\n+/* SATA and USB3 PHY offset compared to SATA PHY */\n+#define COMPHY_LANE2_REGS_BASE\t\t0x200\n+\n+/*\n+ * When accessing common PHY lane registers directly, we need to shift by 1,\n+ * since the registers are 16-bit.\n+ */\n+#define COMPHY_LANE_REG_DIRECT(reg)\t(((reg) & 0x7FF) << 1)\n+\n+/* COMPHY registers */\n+#define COMPHY_POWER_PLL_CTRL\t\t0x01\n+#define PU_IVREF_BIT\t\t\tBIT(15)\n+#define PU_PLL_BIT\t\t\tBIT(14)\n+#define PU_RX_BIT\t\t\tBIT(13)\n+#define PU_TX_BIT\t\t\tBIT(12)\n+#define PU_TX_INTP_BIT\t\t\tBIT(11)\n+#define PU_DFE_BIT\t\t\tBIT(10)\n+#define RESET_DTL_RX_BIT\t\tBIT(9)\n+#define PLL_LOCK_BIT\t\t\tBIT(8)\n+#define REF_FREF_SEL_MASK\t\tGENMASK(4, 0)\n+#define REF_FREF_SEL_SERDES_25MHZ\tFIELD_PREP(REF_FREF_SEL_MASK, 0x1)\n+#define REF_FREF_SEL_SERDES_40MHZ\tFIELD_PREP(REF_FREF_SEL_MASK, 0x3)\n+#define REF_FREF_SEL_SERDES_50MHZ\tFIELD_PREP(REF_FREF_SEL_MASK, 0x4)\n+#define REF_FREF_SEL_PCIE_USB3_25MHZ\tFIELD_PREP(REF_FREF_SEL_MASK, 0x2)\n+#define REF_FREF_SEL_PCIE_USB3_40MHZ\tFIELD_PREP(REF_FREF_SEL_MASK, 0x3)\n+#define COMPHY_MODE_MASK\t\tGENMASK(7, 5)\n+#define COMPHY_MODE_SATA\t\tFIELD_PREP(COMPHY_MODE_MASK, 0x0)\n+#define COMPHY_MODE_PCIE\t\tFIELD_PREP(COMPHY_MODE_MASK, 0x3)\n+#define COMPHY_MODE_SERDES\t\tFIELD_PREP(COMPHY_MODE_MASK, 0x4)\n+#define COMPHY_MODE_USB3\t\tFIELD_PREP(COMPHY_MODE_MASK, 0x5)\n+\n+#define COMPHY_KVCO_CAL_CTRL\t\t0x02\n+#define USE_MAX_PLL_RATE_BIT\t\tBIT(12)\n+#define SPEED_PLL_MASK\t\t\tGENMASK(7, 2)\n+#define SPEED_PLL_VALUE_16\t\tFIELD_PREP(SPEED_PLL_MASK, 0x10)\n+\n+#define COMPHY_DIG_LOOPBACK_EN\t\t0x23\n+#define SEL_DATA_WIDTH_MASK\t\tGENMASK(11, 10)\n+#define DATA_WIDTH_10BIT\t\tFIELD_PREP(SEL_DATA_WIDTH_MASK, 0x0)\n+#define DATA_WIDTH_20BIT\t\tFIELD_PREP(SEL_DATA_WIDTH_MASK, 0x1)\n+#define DATA_WIDTH_40BIT\t\tFIELD_PREP(SEL_DATA_WIDTH_MASK, 0x2)\n+#define PLL_READY_TX_BIT\t\tBIT(4)\n+\n+#define COMPHY_SYNC_PATTERN\t\t0x24\n+#define TXD_INVERT_BIT\t\t\tBIT(10)\n+#define RXD_INVERT_BIT\t\t\tBIT(11)\n+\n+#define COMPHY_SYNC_MASK_GEN\t\t0x25\n+#define PHY_GEN_MAX_MASK\t\tGENMASK(11, 10)\n+#define PHY_GEN_MAX_USB3_5G\t\tFIELD_PREP(PHY_GEN_MAX_MASK, 0x1)\n+\n+#define COMPHY_ISOLATION_CTRL\t\t0x26\n+#define PHY_ISOLATE_MODE\t\tBIT(15)\n+\n+#define COMPHY_GEN2_SET2\t\t0x3e\n+#define GS2_TX_SSC_AMP_MASK\t\tGENMASK(15, 9)\n+#define GS2_TX_SSC_AMP_4128\t\tFIELD_PREP(GS2_TX_SSC_AMP_MASK, 0x20)\n+#define GS2_VREG_RXTX_MAS_ISET_MASK\tGENMASK(8, 7)\n+#define GS2_VREG_RXTX_MAS_ISET_60U\tFIELD_PREP(GS2_VREG_RXTX_MAS_ISET_MASK,\\\n+\t\t\t\t\t\t   0x0)\n+#define GS2_VREG_RXTX_MAS_ISET_80U\tFIELD_PREP(GS2_VREG_RXTX_MAS_ISET_MASK,\\\n+\t\t\t\t\t\t   0x1)\n+#define GS2_VREG_RXTX_MAS_ISET_100U\tFIELD_PREP(GS2_VREG_RXTX_MAS_ISET_MASK,\\\n+\t\t\t\t\t\t   0x2)\n+#define GS2_VREG_RXTX_MAS_ISET_120U\tFIELD_PREP(GS2_VREG_RXTX_MAS_ISET_MASK,\\\n+\t\t\t\t\t\t   0x3)\n+#define GS2_RSVD_6_0_MASK\t\tGENMASK(6, 0)\n+\n+#define COMPHY_GEN3_SET2\t\t0x3f\n+\n+#define COMPHY_IDLE_SYNC_EN\t\t0x48\n+#define IDLE_SYNC_EN\t\t\tBIT(12)\n+\n+#define COMPHY_MISC_CTRL0\t\t0x4F\n+#define CLK100M_125M_EN\t\t\tBIT(4)\n+#define TXDCLK_2X_SEL\t\t\tBIT(6)\n+#define CLK500M_EN\t\t\tBIT(7)\n+#define PHY_REF_CLK_SEL\t\t\tBIT(10)\n+\n+#define COMPHY_SFT_RESET\t\t0x52\n+#define SFT_RST\t\t\t\tBIT(9)\n+#define SFT_RST_NO_REG\t\t\tBIT(10)\n+\n+#define COMPHY_MISC_CTRL1\t\t0x73\n+#define SEL_BITS_PCIE_FORCE\t\tBIT(15)\n+\n+#define COMPHY_GEN2_SET3\t\t0x112\n+#define GS3_FFE_CAP_SEL_MASK\t\tGENMASK(3, 0)\n+#define GS3_FFE_CAP_SEL_VALUE\t\tFIELD_PREP(GS3_FFE_CAP_SEL_MASK, 0xF)\n+\n+/* PIPE registers */\n+#define COMPHY_PIPE_LANE_CFG0\t\t0x180\n+#define PRD_TXDEEMPH0_MASK\t\tBIT(0)\n+#define PRD_TXMARGIN_MASK\t\tGENMASK(3, 1)\n+#define PRD_TXSWING_MASK\t\tBIT(4)\n+#define CFG_TX_ALIGN_POS_MASK\t\tGENMASK(8, 5)\n+\n+#define COMPHY_PIPE_LANE_CFG1\t\t0x181\n+#define PRD_TXDEEMPH1_MASK\t\tBIT(15)\n+#define USE_MAX_PLL_RATE_EN\t\tBIT(9)\n+#define TX_DET_RX_MODE\t\t\tBIT(6)\n+#define GEN2_TX_DATA_DLY_MASK\t\tGENMASK(4, 3)\n+#define GEN2_TX_DATA_DLY_DEFT\t\tFIELD_PREP(GEN2_TX_DATA_DLY_MASK, 2)\n+#define TX_ELEC_IDLE_MODE_EN\t\tBIT(0)\n+\n+#define COMPHY_PIPE_LANE_STAT1\t\t0x183\n+#define TXDCLK_PCLK_EN\t\t\tBIT(0)\n+\n+#define COMPHY_PIPE_LANE_CFG4\t\t0x188\n+#define SPREAD_SPECTRUM_CLK_EN\t\tBIT(7)\n+\n+#define COMPHY_PIPE_RST_CLK_CTRL\t0x1C1\n+#define PIPE_SOFT_RESET\t\t\tBIT(0)\n+#define PIPE_REG_RESET\t\t\tBIT(1)\n+#define MODE_CORE_CLK_FREQ_SEL\t\tBIT(9)\n+#define MODE_PIPE_WIDTH_32\t\tBIT(3)\n+#define MODE_REFDIV_MASK\t\tGENMASK(5, 4)\n+#define MODE_REFDIV_BY_4\t\tFIELD_PREP(MODE_REFDIV_MASK, 0x2)\n+\n+#define COMPHY_PIPE_TEST_MODE_CTRL\t0x1C2\n+#define MODE_MARGIN_OVERRIDE\t\tBIT(2)\n+\n+#define COMPHY_PIPE_CLK_SRC_LO\t\t0x1C3\n+#define MODE_CLK_SRC\t\t\tBIT(0)\n+#define BUNDLE_PERIOD_SEL\t\tBIT(1)\n+#define BUNDLE_PERIOD_SCALE_MASK\tGENMASK(3, 2)\n+#define BUNDLE_SAMPLE_CTRL\t\tBIT(4)\n+#define PLL_READY_DLY_MASK\t\tGENMASK(7, 5)\n+#define CFG_SEL_20B\t\t\tBIT(15)\n+\n+#define COMPHY_PIPE_PWR_MGM_TIM1\t0x1D0\n+#define CFG_PM_OSCCLK_WAIT_MASK\t\tGENMASK(15, 12)\n+#define CFG_PM_RXDEN_WAIT_MASK\t\tGENMASK(11, 8)\n+#define CFG_PM_RXDEN_WAIT_1_UNIT\tFIELD_PREP(CFG_PM_RXDEN_WAIT_MASK, 0x1)\n+#define CFG_PM_RXDLOZ_WAIT_MASK\t\tGENMASK(7, 0)\n+#define CFG_PM_RXDLOZ_WAIT_7_UNIT\tFIELD_PREP(CFG_PM_RXDLOZ_WAIT_MASK, 0x7)\n+#define CFG_PM_RXDLOZ_WAIT_12_UNIT\tFIELD_PREP(CFG_PM_RXDLOZ_WAIT_MASK, 0xC)\n+\n+/*\n+ * This register is not from PHY lane register space. It only exists in the\n+ * indirect register space, before the actual PHY lane 2 registers. So the\n+ * offset is absolute, not relative to COMPHY_LANE2_REGS_BASE.\n+ * It is used only for SATA PHY initialization.\n+ */\n+#define COMPHY_RESERVED_REG\t\t0x0E\n+#define PHYCTRL_FRM_PIN_BIT\t\tBIT(13)\n \n-/* COMPHY Fast SMC function identifiers */\n-#define COMPHY_SIP_POWER_ON\t\t\t0x82000001\n-#define COMPHY_SIP_POWER_OFF\t\t\t0x82000002\n-#define COMPHY_SIP_PLL_LOCK\t\t\t0x82000003\n-\n-#define COMPHY_FW_MODE_SATA\t\t\t0x1\n-#define COMPHY_FW_MODE_SGMII\t\t\t0x2\n-#define COMPHY_FW_MODE_2500BASEX\t\t0x3\n-#define COMPHY_FW_MODE_USB3H\t\t\t0x4\n-#define COMPHY_FW_MODE_USB3D\t\t\t0x5\n-#define COMPHY_FW_MODE_PCIE\t\t\t0x6\n-#define COMPHY_FW_MODE_USB3\t\t\t0xa\n-\n-#define COMPHY_FW_SPEED_1_25G\t\t\t0 /* SGMII 1G */\n-#define COMPHY_FW_SPEED_2_5G\t\t\t1\n-#define COMPHY_FW_SPEED_3_125G\t\t\t2 /* 2500BASE-X */\n-#define COMPHY_FW_SPEED_5G\t\t\t3\n-#define COMPHY_FW_SPEED_MAX\t\t\t0x3F\n-\n-#define COMPHY_FW_MODE(mode)\t\t\t((mode) << 12)\n-#define COMPHY_FW_NET(mode, idx, speed)\t\t(COMPHY_FW_MODE(mode) | \\\n-\t\t\t\t\t\t ((idx) << 8) |\t\\\n-\t\t\t\t\t\t ((speed) << 2))\n-#define COMPHY_FW_PCIE(mode, speed, width)\t(COMPHY_FW_NET(mode, 0, speed) | \\\n-\t\t\t\t\t\t ((width) << 18))\n+/* South Bridge PHY Configuration Registers */\n+#define COMPHY_PHY_REG(lane, reg)\t(((1 - (lane)) * 0x28) + ((reg) & 0x3f))\n+\n+/*\n+ * lane0: USB3/GbE1 PHY Configuration 1\n+ * lane1: PCIe/GbE0 PHY Configuration 1\n+ * (used only by SGMII code)\n+ */\n+#define COMPHY_PHY_CFG1\t\t\t0x0\n+#define PIN_PU_IVREF_BIT\t\tBIT(1)\n+#define PIN_RESET_CORE_BIT\t\tBIT(11)\n+#define PIN_RESET_COMPHY_BIT\t\tBIT(12)\n+#define PIN_PU_PLL_BIT\t\t\tBIT(16)\n+#define PIN_PU_RX_BIT\t\t\tBIT(17)\n+#define PIN_PU_TX_BIT\t\t\tBIT(18)\n+#define PIN_TX_IDLE_BIT\t\t\tBIT(19)\n+#define GEN_RX_SEL_MASK\t\t\tGENMASK(25, 22)\n+#define GEN_RX_SEL_VALUE(val)\t\tFIELD_PREP(GEN_RX_SEL_MASK, (val))\n+#define GEN_TX_SEL_MASK\t\t\tGENMASK(29, 26)\n+#define GEN_TX_SEL_VALUE(val)\t\tFIELD_PREP(GEN_TX_SEL_MASK, (val))\n+#define SERDES_SPEED_1_25_G\t\t0x6\n+#define SERDES_SPEED_3_125_G\t\t0x8\n+#define PHY_RX_INIT_BIT\t\t\tBIT(30)\n+\n+/*\n+ * lane0: USB3/GbE1 PHY Status 1\n+ * lane1: PCIe/GbE0 PHY Status 1\n+ * (used only by SGMII code)\n+ */\n+#define COMPHY_PHY_STAT1\t\t0x18\n+#define PHY_RX_INIT_DONE_BIT\t\tBIT(0)\n+#define PHY_PLL_READY_RX_BIT\t\tBIT(2)\n+#define PHY_PLL_READY_TX_BIT\t\tBIT(3)\n+\n+/* PHY Selector */\n+#define COMPHY_SELECTOR_PHY_REG\t\t\t0xFC\n+/* bit0: 0: Lane1 is GbE0; 1: Lane1 is PCIe */\n+#define COMPHY_SELECTOR_PCIE_GBE0_SEL_BIT\tBIT(0)\n+/* bit4: 0: Lane0 is GbE1; 1: Lane0 is USB3 */\n+#define COMPHY_SELECTOR_USB3_GBE1_SEL_BIT\tBIT(4)\n+/* bit8: 0: Lane0 is USB3 instead of GbE1, Lane2 is SATA; 1: Lane2 is USB3 */\n+#define COMPHY_SELECTOR_USB3_PHY_SEL_BIT\tBIT(8)\n \n struct mvebu_a3700_comphy_conf {\n \tunsigned int lane;\n \tenum phy_mode mode;\n \tint submode;\n-\tu32 fw_mode;\n };\n \n-#define MVEBU_A3700_COMPHY_CONF(_lane, _mode, _smode, _fw)\t\t\\\n+#define MVEBU_A3700_COMPHY_CONF(_lane, _mode, _smode)\t\t\t\\\n \t{\t\t\t\t\t\t\t\t\\\n \t\t.lane = _lane,\t\t\t\t\t\t\\\n \t\t.mode = _mode,\t\t\t\t\t\t\\\n \t\t.submode = _smode,\t\t\t\t\t\\\n-\t\t.fw_mode = _fw,\t\t\t\t\t\t\\\n \t}\n \n-#define MVEBU_A3700_COMPHY_CONF_GEN(_lane, _mode, _fw) \\\n-\tMVEBU_A3700_COMPHY_CONF(_lane, _mode, PHY_INTERFACE_MODE_NA, _fw)\n+#define MVEBU_A3700_COMPHY_CONF_GEN(_lane, _mode) \\\n+\tMVEBU_A3700_COMPHY_CONF(_lane, _mode, PHY_INTERFACE_MODE_NA)\n \n-#define MVEBU_A3700_COMPHY_CONF_ETH(_lane, _smode, _fw) \\\n-\tMVEBU_A3700_COMPHY_CONF(_lane, PHY_MODE_ETHERNET, _smode, _fw)\n+#define MVEBU_A3700_COMPHY_CONF_ETH(_lane, _smode) \\\n+\tMVEBU_A3700_COMPHY_CONF(_lane, PHY_MODE_ETHERNET, _smode)\n \n static const struct mvebu_a3700_comphy_conf mvebu_a3700_comphy_modes[] = {\n \t/* lane 0 */\n-\tMVEBU_A3700_COMPHY_CONF_GEN(0, PHY_MODE_USB_HOST_SS,\n-\t\t\t\t    COMPHY_FW_MODE_USB3H),\n-\tMVEBU_A3700_COMPHY_CONF_ETH(0, PHY_INTERFACE_MODE_SGMII,\n-\t\t\t\t    COMPHY_FW_MODE_SGMII),\n-\tMVEBU_A3700_COMPHY_CONF_ETH(0, PHY_INTERFACE_MODE_2500BASEX,\n-\t\t\t\t    COMPHY_FW_MODE_2500BASEX),\n+\tMVEBU_A3700_COMPHY_CONF_GEN(0, PHY_MODE_USB_HOST_SS),\n+\tMVEBU_A3700_COMPHY_CONF_ETH(0, PHY_INTERFACE_MODE_SGMII),\n+\tMVEBU_A3700_COMPHY_CONF_ETH(0, PHY_INTERFACE_MODE_1000BASEX),\n+\tMVEBU_A3700_COMPHY_CONF_ETH(0, PHY_INTERFACE_MODE_2500BASEX),\n \t/* lane 1 */\n-\tMVEBU_A3700_COMPHY_CONF_GEN(1, PHY_MODE_PCIE, COMPHY_FW_MODE_PCIE),\n-\tMVEBU_A3700_COMPHY_CONF_ETH(1, PHY_INTERFACE_MODE_SGMII,\n-\t\t\t\t    COMPHY_FW_MODE_SGMII),\n-\tMVEBU_A3700_COMPHY_CONF_ETH(1, PHY_INTERFACE_MODE_2500BASEX,\n-\t\t\t\t    COMPHY_FW_MODE_2500BASEX),\n+\tMVEBU_A3700_COMPHY_CONF_GEN(1, PHY_MODE_PCIE),\n+\tMVEBU_A3700_COMPHY_CONF_ETH(1, PHY_INTERFACE_MODE_SGMII),\n+\tMVEBU_A3700_COMPHY_CONF_ETH(1, PHY_INTERFACE_MODE_1000BASEX),\n+\tMVEBU_A3700_COMPHY_CONF_ETH(1, PHY_INTERFACE_MODE_2500BASEX),\n \t/* lane 2 */\n-\tMVEBU_A3700_COMPHY_CONF_GEN(2, PHY_MODE_SATA, COMPHY_FW_MODE_SATA),\n-\tMVEBU_A3700_COMPHY_CONF_GEN(2, PHY_MODE_USB_HOST_SS,\n-\t\t\t\t    COMPHY_FW_MODE_USB3H),\n+\tMVEBU_A3700_COMPHY_CONF_GEN(2, PHY_MODE_SATA),\n+\tMVEBU_A3700_COMPHY_CONF_GEN(2, PHY_MODE_USB_HOST_SS),\n+};\n+\n+struct mvebu_a3700_comphy_priv {\n+\tvoid __iomem *comphy_regs;\n+\tvoid __iomem *lane0_phy_regs; /* USB3 and GbE1 */\n+\tvoid __iomem *lane1_phy_regs; /* PCIe and GbE0 */\n+\tvoid __iomem *lane2_phy_indirect; /* SATA and USB3 */\n+\tspinlock_t lock; /* for PHY selector access */\n+\tbool xtal_is_40m;\n };\n \n struct mvebu_a3700_comphy_lane {\n+\tstruct mvebu_a3700_comphy_priv *priv;\n \tstruct device *dev;\n \tunsigned int id;\n \tenum phy_mode mode;\n \tint submode;\n+\tbool invert_tx;\n+\tbool invert_rx;\n+\tbool needs_reset;\n+};\n+\n+struct gbe_phy_init_data_fix {\n+\tu16 addr;\n+\tu16 value;\n+};\n+\n+/* Changes to 40M1G25 mode data required for running 40M3G125 init mode */\n+static struct gbe_phy_init_data_fix gbe_phy_init_fix[] = {\n+\t{ 0x005, 0x07CC }, { 0x015, 0x0000 }, { 0x01B, 0x0000 },\n+\t{ 0x01D, 0x0000 }, { 0x01E, 0x0000 }, { 0x01F, 0x0000 },\n+\t{ 0x020, 0x0000 }, { 0x021, 0x0030 }, { 0x026, 0x0888 },\n+\t{ 0x04D, 0x0152 }, { 0x04F, 0xA020 }, { 0x050, 0x07CC },\n+\t{ 0x053, 0xE9CA }, { 0x055, 0xBD97 }, { 0x071, 0x3015 },\n+\t{ 0x076, 0x03AA }, { 0x07C, 0x0FDF }, { 0x0C2, 0x3030 },\n+\t{ 0x0C3, 0x8000 }, { 0x0E2, 0x5550 }, { 0x0E3, 0x12A4 },\n+\t{ 0x0E4, 0x7D00 }, { 0x0E6, 0x0C83 }, { 0x101, 0xFCC0 },\n+\t{ 0x104, 0x0C10 }\n };\n \n-static int mvebu_a3700_comphy_smc(unsigned long function, unsigned long lane,\n-\t\t\t\t  unsigned long mode)\n+/* 40M1G25 mode init data */\n+static u16 gbe_phy_init[512] = {\n+\t/* 0       1       2       3       4       5       6       7 */\n+\t/*-----------------------------------------------------------*/\n+\t/* 8       9       A       B       C       D       E       F */\n+\t0x3110, 0xFD83, 0x6430, 0x412F, 0x82C0, 0x06FA, 0x4500, 0x6D26,\t/* 00 */\n+\t0xAFC0, 0x8000, 0xC000, 0x0000, 0x2000, 0x49CC, 0x0BC9, 0x2A52,\t/* 08 */\n+\t0x0BD2, 0x0CDE, 0x13D2, 0x0CE8, 0x1149, 0x10E0, 0x0000, 0x0000,\t/* 10 */\n+\t0x0000, 0x0000, 0x0000, 0x0001, 0x0000, 0x4134, 0x0D2D, 0xFFFF,\t/* 18 */\n+\t0xFFE0, 0x4030, 0x1016, 0x0030, 0x0000, 0x0800, 0x0866, 0x0000,\t/* 20 */\n+\t0x0000, 0x0000, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,\t/* 28 */\n+\t0xFFFF, 0xFFFF, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\t/* 30 */\n+\t0x0000, 0x0000, 0x000F, 0x6A62, 0x1988, 0x3100, 0x3100, 0x3100,\t/* 38 */\n+\t0x3100, 0xA708, 0x2430, 0x0830, 0x1030, 0x4610, 0xFF00, 0xFF00,\t/* 40 */\n+\t0x0060, 0x1000, 0x0400, 0x0040, 0x00F0, 0x0155, 0x1100, 0xA02A,\t/* 48 */\n+\t0x06FA, 0x0080, 0xB008, 0xE3ED, 0x5002, 0xB592, 0x7A80, 0x0001,\t/* 50 */\n+\t0x020A, 0x8820, 0x6014, 0x8054, 0xACAA, 0xFC88, 0x2A02, 0x45CF,\t/* 58 */\n+\t0x000F, 0x1817, 0x2860, 0x064F, 0x0000, 0x0204, 0x1800, 0x6000,\t/* 60 */\n+\t0x810F, 0x4F23, 0x4000, 0x4498, 0x0850, 0x0000, 0x000E, 0x1002,\t/* 68 */\n+\t0x9D3A, 0x3009, 0xD066, 0x0491, 0x0001, 0x6AB0, 0x0399, 0x3780,\t/* 70 */\n+\t0x0040, 0x5AC0, 0x4A80, 0x0000, 0x01DF, 0x0000, 0x0007, 0x0000,\t/* 78 */\n+\t0x2D54, 0x00A1, 0x4000, 0x0100, 0xA20A, 0x0000, 0x0000, 0x0000,\t/* 80 */\n+\t0x0000, 0x0000, 0x0000, 0x7400, 0x0E81, 0x1000, 0x1242, 0x0210,\t/* 88 */\n+\t0x80DF, 0x0F1F, 0x2F3F, 0x4F5F, 0x6F7F, 0x0F1F, 0x2F3F, 0x4F5F,\t/* 90 */\n+\t0x6F7F, 0x4BAD, 0x0000, 0x0000, 0x0800, 0x0000, 0x2400, 0xB651,\t/* 98 */\n+\t0xC9E0, 0x4247, 0x0A24, 0x0000, 0xAF19, 0x1004, 0x0000, 0x0000,\t/* A0 */\n+\t0x0000, 0x0013, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\t/* A8 */\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\t/* B0 */\n+\t0x0000, 0x0000, 0x0000, 0x0060, 0x0000, 0x0000, 0x0000, 0x0000,\t/* B8 */\n+\t0x0000, 0x0000, 0x3010, 0xFA00, 0x0000, 0x0000, 0x0000, 0x0003,\t/* C0 */\n+\t0x1618, 0x8200, 0x8000, 0x0400, 0x050F, 0x0000, 0x0000, 0x0000,\t/* C8 */\n+\t0x4C93, 0x0000, 0x1000, 0x1120, 0x0010, 0x1242, 0x1242, 0x1E00,\t/* D0 */\n+\t0x0000, 0x0000, 0x0000, 0x00F8, 0x0000, 0x0041, 0x0800, 0x0000,\t/* D8 */\n+\t0x82A0, 0x572E, 0x2490, 0x14A9, 0x4E00, 0x0000, 0x0803, 0x0541,\t/* E0 */\n+\t0x0C15, 0x0000, 0x0000, 0x0400, 0x2626, 0x0000, 0x0000, 0x4200,\t/* E8 */\n+\t0x0000, 0xAA55, 0x1020, 0x0000, 0x0000, 0x5010, 0x0000, 0x0000,\t/* F0 */\n+\t0x0000, 0x0000, 0x5000, 0x0000, 0x0000, 0x0000, 0x02F2, 0x0000,\t/* F8 */\n+\t0x101F, 0xFDC0, 0x4000, 0x8010, 0x0110, 0x0006, 0x0000, 0x0000,\t/*100 */\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\t/*108 */\n+\t0x04CF, 0x0000, 0x04CF, 0x0000, 0x04CF, 0x0000, 0x04C6, 0x0000,\t/*110 */\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\t/*118 */\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\t/*120 */\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\t/*128 */\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\t/*130 */\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\t/*138 */\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\t/*140 */\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\t/*148 */\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\t/*150 */\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\t/*158 */\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\t/*160 */\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\t/*168 */\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\t/*170 */\n+\t0x0000, 0x0000, 0x0000, 0x00F0, 0x08A2, 0x3112, 0x0A14, 0x0000,\t/*178 */\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\t/*180 */\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\t/*188 */\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\t/*190 */\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\t/*198 */\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\t/*1A0 */\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\t/*1A8 */\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\t/*1B0 */\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\t/*1B8 */\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\t/*1C0 */\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\t/*1C8 */\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\t/*1D0 */\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\t/*1D8 */\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\t/*1E0 */\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\t/*1E8 */\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\t/*1F0 */\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000\t/*1F8 */\n+};\n+\n+static inline void comphy_reg_set(void __iomem *addr, u32 data, u32 mask)\n {\n-\tstruct arm_smccc_res res;\n-\ts32 ret;\n+\tu32 val;\n \n-\tarm_smccc_smc(function, lane, mode, 0, 0, 0, 0, 0, &res);\n-\tret = res.a0;\n+\tval = readl(addr);\n+\tval = (val & ~mask) | (data & mask);\n+\twritel(val, addr);\n+}\n \n-\tswitch (ret) {\n-\tcase SMCCC_RET_SUCCESS:\n-\t\treturn 0;\n-\tcase SMCCC_RET_NOT_SUPPORTED:\n-\t\treturn -EOPNOTSUPP;\n+static inline void comphy_reg_set16(void __iomem *addr, u16 data, u16 mask)\n+{\n+\tu16 val;\n+\n+\tval = readw(addr);\n+\tval = (val & ~mask) | (data & mask);\n+\twritew(val, addr);\n+}\n+\n+/* Used for accessing lane 2 registers (SATA/USB3 PHY) */\n+static void comphy_set_indirect(struct mvebu_a3700_comphy_priv *priv,\n+\t\t\t\tu32 offset, u16 data, u16 mask)\n+{\n+\twritel(offset,\n+\t       priv->lane2_phy_indirect + COMPHY_LANE2_INDIR_ADDR);\n+\tcomphy_reg_set(priv->lane2_phy_indirect + COMPHY_LANE2_INDIR_DATA,\n+\t\t       data, mask);\n+}\n+\n+static void comphy_lane_reg_set(struct mvebu_a3700_comphy_lane *lane,\n+\t\t\t\tu16 reg, u16 data, u16 mask)\n+{\n+\tif (lane->id == 2) {\n+\t\t/* lane 2 PHY registers are accessed indirectly */\n+\t\tcomphy_set_indirect(lane->priv,\n+\t\t\t\t    reg + COMPHY_LANE2_REGS_BASE,\n+\t\t\t\t    data, mask);\n+\t} else {\n+\t\tvoid __iomem *base = lane->id == 1 ?\n+\t\t\t\t     lane->priv->lane1_phy_regs :\n+\t\t\t\t     lane->priv->lane0_phy_regs;\n+\n+\t\tcomphy_reg_set16(base + COMPHY_LANE_REG_DIRECT(reg),\n+\t\t\t\t data, mask);\n+\t}\n+}\n+\n+static int comphy_lane_reg_poll(struct mvebu_a3700_comphy_lane *lane,\n+\t\t\t\tu16 reg, u16 bits,\n+\t\t\t\tulong sleep_us, ulong timeout_us)\n+{\n+\tint ret;\n+\n+\tif (lane->id == 2) {\n+\t\tu32 data;\n+\n+\t\t/* lane 2 PHY registers are accessed indirectly */\n+\t\twritel(reg + COMPHY_LANE2_REGS_BASE,\n+\t\t       lane->priv->lane2_phy_indirect +\n+\t\t       COMPHY_LANE2_INDIR_ADDR);\n+\n+\t\tret = readl_poll_timeout(lane->priv->lane2_phy_indirect +\n+\t\t\t\t\t COMPHY_LANE2_INDIR_DATA,\n+\t\t\t\t\t data, (data & bits) == bits,\n+\t\t\t\t\t sleep_us, timeout_us);\n+\t} else {\n+\t\tvoid __iomem *base = lane->id == 1 ?\n+\t\t\t\t     lane->priv->lane1_phy_regs :\n+\t\t\t\t     lane->priv->lane0_phy_regs;\n+\t\tu16 data;\n+\n+\t\tret = readw_poll_timeout(base + COMPHY_LANE_REG_DIRECT(reg),\n+\t\t\t\t\t data, (data & bits) == bits,\n+\t\t\t\t\t sleep_us, timeout_us);\n+\t}\n+\n+\treturn ret;\n+}\n+\n+static void comphy_periph_reg_set(struct mvebu_a3700_comphy_lane *lane,\n+\t\t\t\t  u8 reg, u32 data, u32 mask)\n+{\n+\tcomphy_reg_set(lane->priv->comphy_regs + COMPHY_PHY_REG(lane->id, reg),\n+\t\t       data, mask);\n+}\n+\n+static int comphy_periph_reg_poll(struct mvebu_a3700_comphy_lane *lane,\n+\t\t\t\t  u8 reg, u32 bits,\n+\t\t\t\t  ulong sleep_us, ulong timeout_us)\n+{\n+\tu32 data;\n+\n+\treturn readl_poll_timeout(lane->priv->comphy_regs +\n+\t\t\t\t  COMPHY_PHY_REG(lane->id, reg),\n+\t\t\t\t  data, (data & bits) == bits,\n+\t\t\t\t  sleep_us, timeout_us);\n+}\n+\n+/* PHY selector configures with corresponding modes */\n+static int\n+mvebu_a3700_comphy_set_phy_selector(struct mvebu_a3700_comphy_lane *lane)\n+{\n+\tu32 old, new, clr = 0, set = 0;\n+\tunsigned long flags;\n+\n+\tswitch (lane->mode) {\n+\tcase PHY_MODE_SATA:\n+\t\t/* SATA must be in Lane2 */\n+\t\tif (lane->id == 2)\n+\t\t\tclr = COMPHY_SELECTOR_USB3_PHY_SEL_BIT;\n+\t\telse\n+\t\t\tgoto error;\n+\t\tbreak;\n+\n+\tcase PHY_MODE_ETHERNET:\n+\t\tif (lane->id == 0)\n+\t\t\tclr = COMPHY_SELECTOR_USB3_GBE1_SEL_BIT;\n+\t\telse if (lane->id == 1)\n+\t\t\tclr = COMPHY_SELECTOR_PCIE_GBE0_SEL_BIT;\n+\t\telse\n+\t\t\tgoto error;\n+\t\tbreak;\n+\n+\tcase PHY_MODE_USB_HOST_SS:\n+\t\tif (lane->id == 2)\n+\t\t\tset = COMPHY_SELECTOR_USB3_PHY_SEL_BIT;\n+\t\telse if (lane->id == 0)\n+\t\t\tset = COMPHY_SELECTOR_USB3_GBE1_SEL_BIT;\n+\t\telse\n+\t\t\tgoto error;\n+\t\tbreak;\n+\n+\tcase PHY_MODE_PCIE:\n+\t\t/* PCIE must be in Lane1 */\n+\t\tif (lane->id == 1)\n+\t\t\tset = COMPHY_SELECTOR_PCIE_GBE0_SEL_BIT;\n+\t\telse\n+\t\t\tgoto error;\n+\t\tbreak;\n+\n+\tdefault:\n+\t\tgoto error;\n+\t}\n+\n+\tspin_lock_irqsave(&lane->priv->lock, flags);\n+\n+\told = readl(lane->priv->comphy_regs + COMPHY_SELECTOR_PHY_REG);\n+\tnew = (old & ~clr) | set;\n+\twritel(new, lane->priv->comphy_regs + COMPHY_SELECTOR_PHY_REG);\n+\n+\tspin_unlock_irqrestore(&lane->priv->lock, flags);\n+\n+\tdev_dbg(lane->dev,\n+\t\t\"COMPHY[%d] mode[%d] changed PHY selector 0x%08x -> 0x%08x\\n\",\n+\t\tlane->id, lane->mode, old, new);\n+\n+\treturn 0;\n+error:\n+\tdev_err(lane->dev, \"COMPHY[%d] mode[%d] is invalid\\n\", lane->id,\n+\t\tlane->mode);\n+\treturn -EINVAL;\n+}\n+\n+static int\n+mvebu_a3700_comphy_sata_power_on(struct mvebu_a3700_comphy_lane *lane)\n+{\n+\tu32 mask, data, ref_clk;\n+\tint ret;\n+\n+\t/* Configure phy selector for SATA */\n+\tret = mvebu_a3700_comphy_set_phy_selector(lane);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\t/* Clear phy isolation mode to make it work in normal mode */\n+\tcomphy_lane_reg_set(lane, COMPHY_ISOLATION_CTRL,\n+\t\t\t    0x0, PHY_ISOLATE_MODE);\n+\n+\t/* 0. Check the Polarity invert bits */\n+\tdata = 0x0;\n+\tif (lane->invert_tx)\n+\t\tdata |= TXD_INVERT_BIT;\n+\tif (lane->invert_rx)\n+\t\tdata |= RXD_INVERT_BIT;\n+\tmask = TXD_INVERT_BIT | RXD_INVERT_BIT;\n+\tcomphy_lane_reg_set(lane, COMPHY_SYNC_PATTERN, data, mask);\n+\n+\t/* 1. Select 40-bit data width */\n+\tcomphy_lane_reg_set(lane, COMPHY_DIG_LOOPBACK_EN,\n+\t\t\t    DATA_WIDTH_40BIT, SEL_DATA_WIDTH_MASK);\n+\n+\t/* 2. Select reference clock(25M) and PHY mode (SATA) */\n+\tif (lane->priv->xtal_is_40m)\n+\t\tref_clk = REF_FREF_SEL_SERDES_40MHZ;\n+\telse\n+\t\tref_clk = REF_FREF_SEL_SERDES_25MHZ;\n+\n+\tdata = ref_clk | COMPHY_MODE_SATA;\n+\tmask = REF_FREF_SEL_MASK | COMPHY_MODE_MASK;\n+\tcomphy_lane_reg_set(lane, COMPHY_POWER_PLL_CTRL, data, mask);\n+\n+\t/* 3. Use maximum PLL rate (no power save) */\n+\tcomphy_lane_reg_set(lane, COMPHY_KVCO_CAL_CTRL,\n+\t\t\t    USE_MAX_PLL_RATE_BIT, USE_MAX_PLL_RATE_BIT);\n+\n+\t/* 4. Reset reserved bit */\n+\tcomphy_set_indirect(lane->priv, COMPHY_RESERVED_REG,\n+\t\t\t    0x0, PHYCTRL_FRM_PIN_BIT);\n+\n+\t/* 5. Set vendor-specific configuration (It is done in sata driver) */\n+\t/* XXX: in U-Boot below sequence was executed in this place, in Linux\n+\t * not.  Now it is done only in U-Boot before this comphy\n+\t * initialization - tests shows that it works ok, but in case of any\n+\t * future problem it is left for reference.\n+\t *   reg_set(MVEBU_REGS_BASE + 0xe00a0, 0, 0xffffffff);\n+\t *   reg_set(MVEBU_REGS_BASE + 0xe00a4, BIT(6), BIT(6));\n+\t */\n+\n+\t/* Wait for > 55 us to allow PLL be enabled */\n+\tudelay(PLL_SET_DELAY_US);\n+\n+\t/* Polling status */\n+\tret = comphy_lane_reg_poll(lane, COMPHY_DIG_LOOPBACK_EN,\n+\t\t\t\t   PLL_READY_TX_BIT, COMPHY_PLL_SLEEP,\n+\t\t\t\t   COMPHY_PLL_TIMEOUT);\n+\tif (ret) {\n+\t\tdev_err(lane->dev, \"Failed to lock SATA PLL\\n\");\n+\t\treturn ret;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static void comphy_gbe_phy_init(struct mvebu_a3700_comphy_lane *lane,\n+\t\t\t\tbool is_1gbps)\n+{\n+\tint addr, fix_idx;\n+\tu16 val;\n+\n+\tfix_idx = 0;\n+\tfor (addr = 0; addr < 512; addr++) {\n+\t\t/*\n+\t\t * All PHY register values are defined in full for 3.125Gbps\n+\t\t * SERDES speed. The values required for 1.25 Gbps are almost\n+\t\t * the same and only few registers should be \"fixed\" in\n+\t\t * comparison to 3.125 Gbps values. These register values are\n+\t\t * stored in \"gbe_phy_init_fix\" array.\n+\t\t */\n+\t\tif (!is_1gbps && gbe_phy_init_fix[fix_idx].addr == addr) {\n+\t\t\t/* Use new value */\n+\t\t\tval = gbe_phy_init_fix[fix_idx].value;\n+\t\t\tif (fix_idx < ARRAY_SIZE(gbe_phy_init_fix))\n+\t\t\t\tfix_idx++;\n+\t\t} else {\n+\t\t\tval = gbe_phy_init[addr];\n+\t\t}\n+\n+\t\tcomphy_lane_reg_set(lane, addr, val, 0xFFFF);\n+\t}\n+}\n+\n+static int\n+mvebu_a3700_comphy_ethernet_power_on(struct mvebu_a3700_comphy_lane *lane)\n+{\n+\tu32 mask, data, speed_sel;\n+\tint ret;\n+\n+\t/* Set selector */\n+\tret = mvebu_a3700_comphy_set_phy_selector(lane);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\t/*\n+\t * 1. Reset PHY by setting PHY input port PIN_RESET=1.\n+\t * 2. Set PHY input port PIN_TX_IDLE=1, PIN_PU_IVREF=1 to keep\n+\t *    PHY TXP/TXN output to idle state during PHY initialization\n+\t * 3. Set PHY input port PIN_PU_PLL=0, PIN_PU_RX=0, PIN_PU_TX=0.\n+\t */\n+\tdata = PIN_PU_IVREF_BIT | PIN_TX_IDLE_BIT | PIN_RESET_COMPHY_BIT;\n+\tmask = data | PIN_RESET_CORE_BIT | PIN_PU_PLL_BIT | PIN_PU_RX_BIT |\n+\t       PIN_PU_TX_BIT | PHY_RX_INIT_BIT;\n+\tcomphy_periph_reg_set(lane, COMPHY_PHY_CFG1, data, mask);\n+\n+\t/* 4. Release reset to the PHY by setting PIN_RESET=0. */\n+\tdata = 0x0;\n+\tmask = PIN_RESET_COMPHY_BIT;\n+\tcomphy_periph_reg_set(lane, COMPHY_PHY_CFG1, data, mask);\n+\n+\t/*\n+\t * 5. Set PIN_PHY_GEN_TX[3:0] and PIN_PHY_GEN_RX[3:0] to decide COMPHY\n+\t * bit rate\n+\t */\n+\tswitch (lane->submode) {\n+\tcase PHY_INTERFACE_MODE_SGMII:\n+\tcase PHY_INTERFACE_MODE_1000BASEX:\n+\t\t/* SGMII 1G, SerDes speed 1.25G */\n+\t\tspeed_sel = SERDES_SPEED_1_25_G;\n+\t\tbreak;\n+\tcase PHY_INTERFACE_MODE_2500BASEX:\n+\t\t/* 2500Base-X, SerDes speed 3.125G */\n+\t\tspeed_sel = SERDES_SPEED_3_125_G;\n+\t\tbreak;\n \tdefault:\n+\t\t/* Other rates are not supported */\n+\t\tdev_err(lane->dev,\n+\t\t\t\"unsupported phy speed %d on comphy lane%d\\n\",\n+\t\t\tlane->submode, lane->id);\n \t\treturn -EINVAL;\n \t}\n+\tdata = GEN_RX_SEL_VALUE(speed_sel) | GEN_TX_SEL_VALUE(speed_sel);\n+\tmask = GEN_RX_SEL_MASK | GEN_TX_SEL_MASK;\n+\tcomphy_periph_reg_set(lane, COMPHY_PHY_CFG1, data, mask);\n+\n+\t/*\n+\t * 6. Wait 10mS for bandgap and reference clocks to stabilize; then\n+\t * start SW programming.\n+\t */\n+\tmdelay(10);\n+\n+\t/* 7. Program COMPHY register PHY_MODE */\n+\tdata = COMPHY_MODE_SERDES;\n+\tmask = COMPHY_MODE_MASK;\n+\tcomphy_lane_reg_set(lane, COMPHY_POWER_PLL_CTRL, data, mask);\n+\n+\t/*\n+\t * 8. Set COMPHY register REFCLK_SEL to select the correct REFCLK\n+\t * source\n+\t */\n+\tdata = 0x0;\n+\tmask = PHY_REF_CLK_SEL;\n+\tcomphy_lane_reg_set(lane, COMPHY_MISC_CTRL0, data, mask);\n+\n+\t/*\n+\t * 9. Set correct reference clock frequency in COMPHY register\n+\t * REF_FREF_SEL.\n+\t */\n+\tif (lane->priv->xtal_is_40m)\n+\t\tdata = REF_FREF_SEL_SERDES_50MHZ;\n+\telse\n+\t\tdata = REF_FREF_SEL_SERDES_25MHZ;\n+\n+\tmask = REF_FREF_SEL_MASK;\n+\tcomphy_lane_reg_set(lane, COMPHY_POWER_PLL_CTRL, data, mask);\n+\n+\t/* 10. Program COMPHY register PHY_GEN_MAX[1:0]\n+\t * This step is mentioned in the flow received from verification team.\n+\t * However the PHY_GEN_MAX value is only meaningful for other interfaces\n+\t * (not SERDES). For instance, it selects SATA speed 1.5/3/6 Gbps or\n+\t * PCIe speed 2.5/5 Gbps\n+\t */\n+\n+\t/*\n+\t * 11. Program COMPHY register SEL_BITS to set correct parallel data\n+\t * bus width\n+\t */\n+\tdata = DATA_WIDTH_10BIT;\n+\tmask = SEL_DATA_WIDTH_MASK;\n+\tcomphy_lane_reg_set(lane, COMPHY_DIG_LOOPBACK_EN, data, mask);\n+\n+\t/*\n+\t * 12. As long as DFE function needs to be enabled in any mode,\n+\t * COMPHY register DFE_UPDATE_EN[5:0] shall be programmed to 0x3F\n+\t * for real chip during COMPHY power on.\n+\t * The step 14 exists (and empty) in the original initialization flow\n+\t * obtained from the verification team. According to the functional\n+\t * specification DFE_UPDATE_EN already has the default value 0x3F\n+\t */\n+\n+\t/*\n+\t * 13. Program COMPHY GEN registers.\n+\t * These registers should be programmed based on the lab testing result\n+\t * to achieve optimal performance. Please contact the CEA group to get\n+\t * the related GEN table during real chip bring-up. We only required to\n+\t * run though the entire registers programming flow defined by\n+\t * \"comphy_gbe_phy_init\" when the REF clock is 40 MHz. For REF clock\n+\t * 25 MHz the default values stored in PHY registers are OK.\n+\t */\n+\tdev_dbg(lane->dev, \"Running C-DPI phy init %s mode\\n\",\n+\t\tlane->submode == PHY_INTERFACE_MODE_2500BASEX ? \"2G5\" : \"1G\");\n+\tif (lane->priv->xtal_is_40m)\n+\t\tcomphy_gbe_phy_init(lane,\n+\t\t\t\t    lane->submode != PHY_INTERFACE_MODE_2500BASEX);\n+\n+\t/*\n+\t * 14. [Simulation Only] should not be used for real chip.\n+\t * By pass power up calibration by programming EXT_FORCE_CAL_DONE\n+\t * (R02h[9]) to 1 to shorten COMPHY simulation time.\n+\t */\n+\n+\t/*\n+\t * 15. [Simulation Only: should not be used for real chip]\n+\t * Program COMPHY register FAST_DFE_TIMER_EN=1 to shorten RX training\n+\t * simulation time.\n+\t */\n+\n+\t/*\n+\t * 16. Check the PHY Polarity invert bit\n+\t */\n+\tdata = 0x0;\n+\tif (lane->invert_tx)\n+\t\tdata |= TXD_INVERT_BIT;\n+\tif (lane->invert_rx)\n+\t\tdata |= RXD_INVERT_BIT;\n+\tmask = TXD_INVERT_BIT | RXD_INVERT_BIT;\n+\tcomphy_lane_reg_set(lane, COMPHY_SYNC_PATTERN, data, mask);\n+\n+\t/*\n+\t * 17. Set PHY input ports PIN_PU_PLL, PIN_PU_TX and PIN_PU_RX to 1 to\n+\t * start PHY power up sequence. All the PHY register programming should\n+\t * be done before PIN_PU_PLL=1. There should be no register programming\n+\t * for normal PHY operation from this point.\n+\t */\n+\tdata = PIN_PU_PLL_BIT | PIN_PU_RX_BIT | PIN_PU_TX_BIT;\n+\tmask = data;\n+\tcomphy_periph_reg_set(lane, COMPHY_PHY_CFG1, data, mask);\n+\n+\t/*\n+\t * 18. Wait for PHY power up sequence to finish by checking output ports\n+\t * PIN_PLL_READY_TX=1 and PIN_PLL_READY_RX=1.\n+\t */\n+\tret = comphy_periph_reg_poll(lane, COMPHY_PHY_STAT1,\n+\t\t\t\t     PHY_PLL_READY_TX_BIT |\n+\t\t\t\t     PHY_PLL_READY_RX_BIT,\n+\t\t\t\t     COMPHY_PLL_SLEEP, COMPHY_PLL_TIMEOUT);\n+\tif (ret) {\n+\t\tdev_err(lane->dev, \"Failed to lock PLL for SERDES PHY %d\\n\",\n+\t\t\tlane->id);\n+\t\treturn ret;\n+\t}\n+\n+\t/*\n+\t * 19. Set COMPHY input port PIN_TX_IDLE=0\n+\t */\n+\tcomphy_periph_reg_set(lane, COMPHY_PHY_CFG1, 0x0, PIN_TX_IDLE_BIT);\n+\n+\t/*\n+\t * 20. After valid data appear on PIN_RXDATA bus, set PIN_RX_INIT=1. To\n+\t * start RX initialization. PIN_RX_INIT_DONE will be cleared to 0 by the\n+\t * PHY After RX initialization is done, PIN_RX_INIT_DONE will be set to\n+\t * 1 by COMPHY Set PIN_RX_INIT=0 after PIN_RX_INIT_DONE= 1. Please\n+\t * refer to RX initialization part for details.\n+\t */\n+\tcomphy_periph_reg_set(lane, COMPHY_PHY_CFG1,\n+\t\t\t      PHY_RX_INIT_BIT, PHY_RX_INIT_BIT);\n+\n+\tret = comphy_periph_reg_poll(lane, COMPHY_PHY_STAT1,\n+\t\t\t\t     PHY_PLL_READY_TX_BIT |\n+\t\t\t\t     PHY_PLL_READY_RX_BIT,\n+\t\t\t\t     COMPHY_PLL_SLEEP, COMPHY_PLL_TIMEOUT);\n+\tif (ret) {\n+\t\tdev_err(lane->dev, \"Failed to lock PLL for SERDES PHY %d\\n\",\n+\t\t\tlane->id);\n+\t\treturn ret;\n+\t}\n+\n+\tret = comphy_periph_reg_poll(lane, COMPHY_PHY_STAT1,\n+\t\t\t\t     PHY_RX_INIT_DONE_BIT,\n+\t\t\t\t     COMPHY_PLL_SLEEP, COMPHY_PLL_TIMEOUT);\n+\tif (ret) {\n+\t\tdev_err(lane->dev, \"Failed to init RX of SERDES PHY %d\\n\",\n+\t\t\tlane->id);\n+\t\treturn ret;\n+\t}\n+\n+\treturn 0;\n }\n \n-static int mvebu_a3700_comphy_get_fw_mode(int lane,\n+static int\n+mvebu_a3700_comphy_usb3_power_on(struct mvebu_a3700_comphy_lane *lane)\n+{\n+\tu32 mask, data, cfg, ref_clk;\n+\tint ret;\n+\n+\t/* Set phy seclector */\n+\tret = mvebu_a3700_comphy_set_phy_selector(lane);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\t/*\n+\t * 0. Set PHY OTG Control(0x5d034), bit 4, Power up OTG module The\n+\t * register belong to UTMI module, so it is set in UTMI phy driver.\n+\t */\n+\n+\t/*\n+\t * 1. Set PRD_TXDEEMPH (3.5db de-emph)\n+\t */\n+\tdata = PRD_TXDEEMPH0_MASK;\n+\tmask = PRD_TXDEEMPH0_MASK | PRD_TXMARGIN_MASK | PRD_TXSWING_MASK |\n+\t       CFG_TX_ALIGN_POS_MASK;\n+\tcomphy_lane_reg_set(lane, COMPHY_PIPE_LANE_CFG0, data, mask);\n+\n+\t/*\n+\t * 2. Set BIT0: enable transmitter in high impedance mode\n+\t *    Set BIT[3:4]: delay 2 clock cycles for HiZ off latency\n+\t *    Set BIT6: Tx detect Rx at HiZ mode\n+\t *    Unset BIT15: set to 0 to set USB3 De-emphasize level to -3.5db\n+\t *            together with bit 0 of COMPHY_PIPE_LANE_CFG0 register\n+\t */\n+\tdata = TX_DET_RX_MODE | GEN2_TX_DATA_DLY_DEFT | TX_ELEC_IDLE_MODE_EN;\n+\tmask = PRD_TXDEEMPH1_MASK | TX_DET_RX_MODE | GEN2_TX_DATA_DLY_MASK |\n+\t       TX_ELEC_IDLE_MODE_EN;\n+\tcomphy_lane_reg_set(lane, COMPHY_PIPE_LANE_CFG1, data, mask);\n+\n+\t/*\n+\t * 3. Set Spread Spectrum Clock Enabled\n+\t */\n+\tcomphy_lane_reg_set(lane, COMPHY_PIPE_LANE_CFG4,\n+\t\t\t    SPREAD_SPECTRUM_CLK_EN, SPREAD_SPECTRUM_CLK_EN);\n+\n+\t/*\n+\t * 4. Set Override Margining Controls From the MAC:\n+\t *    Use margining signals from lane configuration\n+\t */\n+\tcomphy_lane_reg_set(lane, COMPHY_PIPE_TEST_MODE_CTRL,\n+\t\t\t    MODE_MARGIN_OVERRIDE, 0xFFFF);\n+\n+\t/*\n+\t * 5. Set Lane-to-Lane Bundle Clock Sampling Period = per PCLK cycles\n+\t *    set Mode Clock Source = PCLK is generated from REFCLK\n+\t */\n+\tdata = 0x0;\n+\tmask = MODE_CLK_SRC | BUNDLE_PERIOD_SEL | BUNDLE_PERIOD_SCALE_MASK |\n+\t       BUNDLE_SAMPLE_CTRL | PLL_READY_DLY_MASK;\n+\tcomphy_lane_reg_set(lane, COMPHY_PIPE_CLK_SRC_LO, data, mask);\n+\n+\t/*\n+\t * 6. Set G2 Spread Spectrum Clock Amplitude at 4K\n+\t */\n+\tcomphy_lane_reg_set(lane, COMPHY_GEN2_SET2,\n+\t\t\t    GS2_TX_SSC_AMP_4128, GS2_TX_SSC_AMP_MASK);\n+\n+\t/*\n+\t * 7. Unset G3 Spread Spectrum Clock Amplitude\n+\t *    set G3 TX and RX Register Master Current Select\n+\t */\n+\tdata = GS2_VREG_RXTX_MAS_ISET_60U;\n+\tmask = GS2_TX_SSC_AMP_MASK | GS2_VREG_RXTX_MAS_ISET_MASK |\n+\t       GS2_RSVD_6_0_MASK;\n+\tcomphy_lane_reg_set(lane, COMPHY_GEN3_SET2, data, mask);\n+\n+\t/*\n+\t * 8. Check crystal jumper setting and program the Power and PLL Control\n+\t * accordingly Change RX wait\n+\t */\n+\tif (lane->priv->xtal_is_40m) {\n+\t\tref_clk = REF_FREF_SEL_PCIE_USB3_40MHZ;\n+\t\tcfg = CFG_PM_RXDLOZ_WAIT_12_UNIT;\n+\t} else {\n+\t\tref_clk = REF_FREF_SEL_PCIE_USB3_25MHZ;\n+\t\tcfg = CFG_PM_RXDLOZ_WAIT_7_UNIT;\n+\t}\n+\n+\tdata = PU_IVREF_BIT | PU_PLL_BIT | PU_RX_BIT | PU_TX_BIT |\n+\t       PU_TX_INTP_BIT | PU_DFE_BIT | COMPHY_MODE_USB3 | ref_clk;\n+\tmask = PU_IVREF_BIT | PU_PLL_BIT | PU_RX_BIT | PU_TX_BIT |\n+\t       PU_TX_INTP_BIT | PU_DFE_BIT | PLL_LOCK_BIT | COMPHY_MODE_MASK |\n+\t       REF_FREF_SEL_MASK;\n+\tcomphy_lane_reg_set(lane, COMPHY_POWER_PLL_CTRL, data, mask);\n+\n+\tdata = CFG_PM_RXDEN_WAIT_1_UNIT | cfg;\n+\tmask = CFG_PM_OSCCLK_WAIT_MASK | CFG_PM_RXDEN_WAIT_MASK |\n+\t       CFG_PM_RXDLOZ_WAIT_MASK;\n+\tcomphy_lane_reg_set(lane, COMPHY_PIPE_PWR_MGM_TIM1, data, mask);\n+\n+\t/*\n+\t * 9. Enable idle sync\n+\t */\n+\tcomphy_lane_reg_set(lane, COMPHY_IDLE_SYNC_EN,\n+\t\t\t    IDLE_SYNC_EN, IDLE_SYNC_EN);\n+\n+\t/*\n+\t * 10. Enable the output of 500M clock\n+\t */\n+\tcomphy_lane_reg_set(lane, COMPHY_MISC_CTRL0, CLK500M_EN, CLK500M_EN);\n+\n+\t/*\n+\t * 11. Set 20-bit data width\n+\t */\n+\tcomphy_lane_reg_set(lane, COMPHY_DIG_LOOPBACK_EN,\n+\t\t\t    DATA_WIDTH_20BIT, 0xFFFF);\n+\n+\t/*\n+\t * 12. Override Speed_PLL value and use MAC PLL\n+\t */\n+\tdata = SPEED_PLL_VALUE_16 | USE_MAX_PLL_RATE_BIT;\n+\tmask = 0xFFFF;\n+\tcomphy_lane_reg_set(lane, COMPHY_KVCO_CAL_CTRL, data, mask);\n+\n+\t/*\n+\t * 13. Check the Polarity invert bit\n+\t */\n+\tdata = 0x0;\n+\tif (lane->invert_tx)\n+\t\tdata |= TXD_INVERT_BIT;\n+\tif (lane->invert_rx)\n+\t\tdata |= RXD_INVERT_BIT;\n+\tmask = TXD_INVERT_BIT | RXD_INVERT_BIT;\n+\tcomphy_lane_reg_set(lane, COMPHY_SYNC_PATTERN, data, mask);\n+\n+\t/*\n+\t * 14. Set max speed generation to USB3.0 5Gbps\n+\t */\n+\tcomphy_lane_reg_set(lane, COMPHY_SYNC_MASK_GEN,\n+\t\t\t    PHY_GEN_MAX_USB3_5G, PHY_GEN_MAX_MASK);\n+\n+\t/*\n+\t * 15. Set capacitor value for FFE gain peaking to 0xF\n+\t */\n+\tcomphy_lane_reg_set(lane, COMPHY_GEN2_SET3,\n+\t\t\t    GS3_FFE_CAP_SEL_VALUE, GS3_FFE_CAP_SEL_MASK);\n+\n+\t/*\n+\t * 16. Release SW reset\n+\t */\n+\tdata = MODE_CORE_CLK_FREQ_SEL | MODE_PIPE_WIDTH_32 | MODE_REFDIV_BY_4;\n+\tmask = 0xFFFF;\n+\tcomphy_lane_reg_set(lane, COMPHY_PIPE_RST_CLK_CTRL, data, mask);\n+\n+\t/* Wait for > 55 us to allow PCLK be enabled */\n+\tudelay(PLL_SET_DELAY_US);\n+\n+\tret = comphy_lane_reg_poll(lane, COMPHY_PIPE_LANE_STAT1, TXDCLK_PCLK_EN,\n+\t\t\t\t   COMPHY_PLL_SLEEP, COMPHY_PLL_TIMEOUT);\n+\tif (ret) {\n+\t\tdev_err(lane->dev, \"Failed to lock USB3 PLL\\n\");\n+\t\treturn ret;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int\n+mvebu_a3700_comphy_pcie_power_on(struct mvebu_a3700_comphy_lane *lane)\n+{\n+\tu32 mask, data, ref_clk;\n+\tint ret;\n+\n+\t/* Configure phy selector for PCIe */\n+\tret = mvebu_a3700_comphy_set_phy_selector(lane);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\t/* 1. Enable max PLL. */\n+\tcomphy_lane_reg_set(lane, COMPHY_PIPE_LANE_CFG1,\n+\t\t\t    USE_MAX_PLL_RATE_EN, USE_MAX_PLL_RATE_EN);\n+\n+\t/* 2. Select 20 bit SERDES interface. */\n+\tcomphy_lane_reg_set(lane, COMPHY_PIPE_CLK_SRC_LO,\n+\t\t\t    CFG_SEL_20B, CFG_SEL_20B);\n+\n+\t/* 3. Force to use reg setting for PCIe mode */\n+\tcomphy_lane_reg_set(lane, COMPHY_MISC_CTRL1,\n+\t\t\t    SEL_BITS_PCIE_FORCE, SEL_BITS_PCIE_FORCE);\n+\n+\t/* 4. Change RX wait */\n+\tdata = CFG_PM_RXDEN_WAIT_1_UNIT | CFG_PM_RXDLOZ_WAIT_12_UNIT;\n+\tmask = CFG_PM_OSCCLK_WAIT_MASK | CFG_PM_RXDEN_WAIT_MASK |\n+\t       CFG_PM_RXDLOZ_WAIT_MASK;\n+\tcomphy_lane_reg_set(lane, COMPHY_PIPE_PWR_MGM_TIM1, data, mask);\n+\n+\t/* 5. Enable idle sync */\n+\tcomphy_lane_reg_set(lane, COMPHY_IDLE_SYNC_EN,\n+\t\t\t    IDLE_SYNC_EN, IDLE_SYNC_EN);\n+\n+\t/* 6. Enable the output of 100M/125M/500M clock */\n+\tdata = CLK500M_EN | TXDCLK_2X_SEL | CLK100M_125M_EN;\n+\tmask = data;\n+\tcomphy_lane_reg_set(lane, COMPHY_MISC_CTRL0, data, mask);\n+\n+\t/*\n+\t * 7. Enable TX, PCIE global register, 0xd0074814, it is done in\n+\t * PCI-E driver\n+\t */\n+\n+\t/*\n+\t * 8. Check crystal jumper setting and program the Power and PLL\n+\t * Control accordingly\n+\t */\n+\n+\tif (lane->priv->xtal_is_40m)\n+\t\tref_clk = REF_FREF_SEL_PCIE_USB3_40MHZ;\n+\telse\n+\t\tref_clk = REF_FREF_SEL_PCIE_USB3_25MHZ;\n+\n+\tdata = PU_IVREF_BIT | PU_PLL_BIT | PU_RX_BIT | PU_TX_BIT |\n+\t       PU_TX_INTP_BIT | PU_DFE_BIT | COMPHY_MODE_PCIE | ref_clk;\n+\tmask = 0xFFFF;\n+\tcomphy_lane_reg_set(lane, COMPHY_POWER_PLL_CTRL, data, mask);\n+\n+\t/* 9. Override Speed_PLL value and use MAC PLL */\n+\tcomphy_lane_reg_set(lane, COMPHY_KVCO_CAL_CTRL,\n+\t\t\t    SPEED_PLL_VALUE_16 | USE_MAX_PLL_RATE_BIT,\n+\t\t\t    0xFFFF);\n+\n+\t/* 10. Check the Polarity invert bit */\n+\tdata = 0x0;\n+\tif (lane->invert_tx)\n+\t\tdata |= TXD_INVERT_BIT;\n+\tif (lane->invert_rx)\n+\t\tdata |= RXD_INVERT_BIT;\n+\tmask = TXD_INVERT_BIT | RXD_INVERT_BIT;\n+\tcomphy_lane_reg_set(lane, COMPHY_SYNC_PATTERN, data, mask);\n+\n+\t/* 11. Release SW reset */\n+\tdata = MODE_CORE_CLK_FREQ_SEL | MODE_PIPE_WIDTH_32;\n+\tmask = data | PIPE_SOFT_RESET | MODE_REFDIV_MASK;\n+\tcomphy_lane_reg_set(lane, COMPHY_PIPE_RST_CLK_CTRL, data, mask);\n+\n+\t/* Wait for > 55 us to allow PCLK be enabled */\n+\tudelay(PLL_SET_DELAY_US);\n+\n+\tret = comphy_lane_reg_poll(lane, COMPHY_PIPE_LANE_STAT1, TXDCLK_PCLK_EN,\n+\t\t\t\t   COMPHY_PLL_SLEEP, COMPHY_PLL_TIMEOUT);\n+\tif (ret) {\n+\t\tdev_err(lane->dev, \"Failed to lock PCIE PLL\\n\");\n+\t\treturn ret;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static void\n+mvebu_a3700_comphy_usb3_power_off(struct mvebu_a3700_comphy_lane *lane)\n+{\n+\t/*\n+\t * Currently the USB3 MAC sets the USB3 PHY to low state, so we do not\n+\t * need to power off USB3 PHY again.\n+\t */\n+}\n+\n+static void\n+mvebu_a3700_comphy_sata_power_off(struct mvebu_a3700_comphy_lane *lane)\n+{\n+\t/* Set phy isolation mode */\n+\tcomphy_lane_reg_set(lane, COMPHY_ISOLATION_CTRL,\n+\t\t\t    PHY_ISOLATE_MODE, PHY_ISOLATE_MODE);\n+\n+\t/* Power off PLL, Tx, Rx */\n+\tcomphy_lane_reg_set(lane, COMPHY_POWER_PLL_CTRL,\n+\t\t\t    0x0, PU_PLL_BIT | PU_RX_BIT | PU_TX_BIT);\n+}\n+\n+static void\n+mvebu_a3700_comphy_ethernet_power_off(struct mvebu_a3700_comphy_lane *lane)\n+{\n+\tu32 mask, data;\n+\n+\tdata = PIN_RESET_CORE_BIT | PIN_RESET_COMPHY_BIT | PIN_PU_IVREF_BIT |\n+\t       PHY_RX_INIT_BIT;\n+\tmask = data;\n+\tcomphy_periph_reg_set(lane, COMPHY_PHY_CFG1, data, mask);\n+}\n+\n+static void\n+mvebu_a3700_comphy_pcie_power_off(struct mvebu_a3700_comphy_lane *lane)\n+{\n+\t/* Power off PLL, Tx, Rx */\n+\tcomphy_lane_reg_set(lane, COMPHY_POWER_PLL_CTRL,\n+\t\t\t    0x0, PU_PLL_BIT | PU_RX_BIT | PU_TX_BIT);\n+}\n+\n+static int mvebu_a3700_comphy_reset(struct phy *phy)\n+{\n+\tstruct mvebu_a3700_comphy_lane *lane = phy_get_drvdata(phy);\n+\tu16 mask, data;\n+\n+\tdev_dbg(lane->dev, \"resetting lane %d\\n\", lane->id);\n+\n+\t/* COMPHY reset for internal logic */\n+\tcomphy_lane_reg_set(lane, COMPHY_SFT_RESET,\n+\t\t\t    SFT_RST_NO_REG, SFT_RST_NO_REG);\n+\n+\t/* COMPHY register reset (cleared automatically) */\n+\tcomphy_lane_reg_set(lane, COMPHY_SFT_RESET, SFT_RST, SFT_RST);\n+\n+\t/* PIPE soft and register reset */\n+\tdata = PIPE_SOFT_RESET | PIPE_REG_RESET;\n+\tmask = data;\n+\tcomphy_lane_reg_set(lane, COMPHY_PIPE_RST_CLK_CTRL, data, mask);\n+\n+\t/* Release PIPE register reset */\n+\tcomphy_lane_reg_set(lane, COMPHY_PIPE_RST_CLK_CTRL,\n+\t\t\t    0x0, PIPE_REG_RESET);\n+\n+\t/* Reset SB configuration register (only for lanes 0 and 1) */\n+\tif (lane->id == 0 || lane->id == 1) {\n+\t\tu32 mask, data;\n+\n+\t\tdata = PIN_RESET_CORE_BIT | PIN_RESET_COMPHY_BIT |\n+\t\t       PIN_PU_PLL_BIT | PIN_PU_RX_BIT | PIN_PU_TX_BIT;\n+\t\tmask = data | PIN_PU_IVREF_BIT | PIN_TX_IDLE_BIT;\n+\t\tcomphy_periph_reg_set(lane, COMPHY_PHY_CFG1, data, mask);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static bool mvebu_a3700_comphy_check_mode(int lane,\n \t\t\t\t\t  enum phy_mode mode,\n \t\t\t\t\t  int submode)\n {\n@@ -122,7 +1170,7 @@ static int mvebu_a3700_comphy_get_fw_mod\n \n \t/* Unused PHY mux value is 0x0 */\n \tif (mode == PHY_MODE_INVALID)\n-\t\treturn -EINVAL;\n+\t\treturn false;\n \n \tfor (i = 0; i < n; i++) {\n \t\tif (mvebu_a3700_comphy_modes[i].lane == lane &&\n@@ -132,27 +1180,30 @@ static int mvebu_a3700_comphy_get_fw_mod\n \t}\n \n \tif (i == n)\n-\t\treturn -EINVAL;\n+\t\treturn false;\n \n-\treturn mvebu_a3700_comphy_modes[i].fw_mode;\n+\treturn true;\n }\n \n static int mvebu_a3700_comphy_set_mode(struct phy *phy, enum phy_mode mode,\n \t\t\t\t       int submode)\n {\n \tstruct mvebu_a3700_comphy_lane *lane = phy_get_drvdata(phy);\n-\tint fw_mode;\n-\n-\tif (submode == PHY_INTERFACE_MODE_1000BASEX)\n-\t\tsubmode = PHY_INTERFACE_MODE_SGMII;\n \n-\tfw_mode = mvebu_a3700_comphy_get_fw_mode(lane->id, mode,\n-\t\t\t\t\t\t submode);\n-\tif (fw_mode < 0) {\n+\tif (!mvebu_a3700_comphy_check_mode(lane->id, mode, submode)) {\n \t\tdev_err(lane->dev, \"invalid COMPHY mode\\n\");\n-\t\treturn fw_mode;\n+\t\treturn -EINVAL;\n \t}\n \n+\t/* Mode cannot be changed while the PHY is powered on */\n+\tif (phy->power_count &&\n+\t    (lane->mode != mode || lane->submode != submode))\n+\t\treturn -EBUSY;\n+\n+\t/* If changing mode, ensure reset is called */\n+\tif (lane->mode != PHY_MODE_INVALID && lane->mode != mode)\n+\t\tlane->needs_reset = true;\n+\n \t/* Just remember the mode, ->power_on() will do the real setup */\n \tlane->mode = mode;\n \tlane->submode = submode;\n@@ -163,76 +1214,68 @@ static int mvebu_a3700_comphy_set_mode(s\n static int mvebu_a3700_comphy_power_on(struct phy *phy)\n {\n \tstruct mvebu_a3700_comphy_lane *lane = phy_get_drvdata(phy);\n-\tu32 fw_param;\n-\tint fw_mode;\n-\tint fw_port;\n \tint ret;\n \n-\tfw_mode = mvebu_a3700_comphy_get_fw_mode(lane->id,\n-\t\t\t\t\t\t lane->mode, lane->submode);\n-\tif (fw_mode < 0) {\n+\tif (!mvebu_a3700_comphy_check_mode(lane->id, lane->mode,\n+\t\t\t\t\t   lane->submode)) {\n \t\tdev_err(lane->dev, \"invalid COMPHY mode\\n\");\n-\t\treturn fw_mode;\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (lane->needs_reset) {\n+\t\tret = mvebu_a3700_comphy_reset(phy);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\n+\t\tlane->needs_reset = false;\n \t}\n \n \tswitch (lane->mode) {\n \tcase PHY_MODE_USB_HOST_SS:\n \t\tdev_dbg(lane->dev, \"set lane %d to USB3 host mode\\n\", lane->id);\n-\t\tfw_param = COMPHY_FW_MODE(fw_mode);\n-\t\tbreak;\n+\t\treturn mvebu_a3700_comphy_usb3_power_on(lane);\n \tcase PHY_MODE_SATA:\n \t\tdev_dbg(lane->dev, \"set lane %d to SATA mode\\n\", lane->id);\n-\t\tfw_param = COMPHY_FW_MODE(fw_mode);\n-\t\tbreak;\n+\t\treturn mvebu_a3700_comphy_sata_power_on(lane);\n \tcase PHY_MODE_ETHERNET:\n-\t\tfw_port = (lane->id == 0) ? 1 : 0;\n-\t\tswitch (lane->submode) {\n-\t\tcase PHY_INTERFACE_MODE_SGMII:\n-\t\t\tdev_dbg(lane->dev, \"set lane %d to SGMII mode\\n\",\n-\t\t\t\tlane->id);\n-\t\t\tfw_param = COMPHY_FW_NET(fw_mode, fw_port,\n-\t\t\t\t\t\t COMPHY_FW_SPEED_1_25G);\n-\t\t\tbreak;\n-\t\tcase PHY_INTERFACE_MODE_2500BASEX:\n-\t\t\tdev_dbg(lane->dev, \"set lane %d to 2500BASEX mode\\n\",\n-\t\t\t\tlane->id);\n-\t\t\tfw_param = COMPHY_FW_NET(fw_mode, fw_port,\n-\t\t\t\t\t\t COMPHY_FW_SPEED_3_125G);\n-\t\t\tbreak;\n-\t\tdefault:\n-\t\t\tdev_err(lane->dev, \"unsupported PHY submode (%d)\\n\",\n-\t\t\t\tlane->submode);\n-\t\t\treturn -ENOTSUPP;\n-\t\t}\n-\t\tbreak;\n+\t\tdev_dbg(lane->dev, \"set lane %d to Ethernet mode\\n\", lane->id);\n+\t\treturn mvebu_a3700_comphy_ethernet_power_on(lane);\n \tcase PHY_MODE_PCIE:\n \t\tdev_dbg(lane->dev, \"set lane %d to PCIe mode\\n\", lane->id);\n-\t\tfw_param = COMPHY_FW_PCIE(fw_mode, COMPHY_FW_SPEED_5G,\n-\t\t\t\t\t  phy->attrs.bus_width);\n-\t\tbreak;\n+\t\treturn mvebu_a3700_comphy_pcie_power_on(lane);\n \tdefault:\n \t\tdev_err(lane->dev, \"unsupported PHY mode (%d)\\n\", lane->mode);\n-\t\treturn -ENOTSUPP;\n+\t\treturn -EOPNOTSUPP;\n \t}\n-\n-\tret = mvebu_a3700_comphy_smc(COMPHY_SIP_POWER_ON, lane->id, fw_param);\n-\tif (ret == -EOPNOTSUPP)\n-\t\tdev_err(lane->dev,\n-\t\t\t\"unsupported SMC call, try updating your firmware\\n\");\n-\n-\treturn ret;\n }\n \n static int mvebu_a3700_comphy_power_off(struct phy *phy)\n {\n \tstruct mvebu_a3700_comphy_lane *lane = phy_get_drvdata(phy);\n \n-\treturn mvebu_a3700_comphy_smc(COMPHY_SIP_POWER_OFF, lane->id, 0);\n+\tswitch (lane->mode) {\n+\tcase PHY_MODE_USB_HOST_SS:\n+\t\tmvebu_a3700_comphy_usb3_power_off(lane);\n+\t\treturn 0;\n+\tcase PHY_MODE_SATA:\n+\t\tmvebu_a3700_comphy_sata_power_off(lane);\n+\t\treturn 0;\n+\tcase PHY_MODE_ETHERNET:\n+\t\tmvebu_a3700_comphy_ethernet_power_off(lane);\n+\t\treturn 0;\n+\tcase PHY_MODE_PCIE:\n+\t\tmvebu_a3700_comphy_pcie_power_off(lane);\n+\t\treturn 0;\n+\tdefault:\n+\t\tdev_err(lane->dev, \"invalid COMPHY mode\\n\");\n+\t\treturn -EINVAL;\n+\t}\n }\n \n static const struct phy_ops mvebu_a3700_comphy_ops = {\n \t.power_on\t= mvebu_a3700_comphy_power_on,\n \t.power_off\t= mvebu_a3700_comphy_power_off,\n+\t.reset\t\t= mvebu_a3700_comphy_reset,\n \t.set_mode\t= mvebu_a3700_comphy_set_mode,\n \t.owner\t\t= THIS_MODULE,\n };\n@@ -256,13 +1299,75 @@ static struct phy *mvebu_a3700_comphy_xl\n \t\treturn ERR_PTR(-EINVAL);\n \t}\n \n+\tlane->invert_tx = args->args[1] & BIT(0);\n+\tlane->invert_rx = args->args[1] & BIT(1);\n+\n \treturn phy;\n }\n \n static int mvebu_a3700_comphy_probe(struct platform_device *pdev)\n {\n+\tstruct mvebu_a3700_comphy_priv *priv;\n \tstruct phy_provider *provider;\n \tstruct device_node *child;\n+\tstruct resource *res;\n+\tstruct clk *clk;\n+\tint ret;\n+\n+\tpriv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);\n+\tif (!priv)\n+\t\treturn -ENOMEM;\n+\n+\tspin_lock_init(&priv->lock);\n+\n+\tres = platform_get_resource_byname(pdev, IORESOURCE_MEM, \"comphy\");\n+\tpriv->comphy_regs = devm_ioremap_resource(&pdev->dev, res);\n+\tif (IS_ERR(priv->comphy_regs))\n+\t\treturn PTR_ERR(priv->comphy_regs);\n+\n+\tres = platform_get_resource_byname(pdev, IORESOURCE_MEM,\n+\t\t\t\t\t   \"lane1_pcie_gbe\");\n+\tpriv->lane1_phy_regs = devm_ioremap_resource(&pdev->dev, res);\n+\tif (IS_ERR(priv->lane1_phy_regs))\n+\t\treturn PTR_ERR(priv->lane1_phy_regs);\n+\n+\tres = platform_get_resource_byname(pdev, IORESOURCE_MEM,\n+\t\t\t\t\t   \"lane0_usb3_gbe\");\n+\tpriv->lane0_phy_regs = devm_ioremap_resource(&pdev->dev, res);\n+\tif (IS_ERR(priv->lane0_phy_regs))\n+\t\treturn PTR_ERR(priv->lane0_phy_regs);\n+\n+\tres = platform_get_resource_byname(pdev, IORESOURCE_MEM,\n+\t\t\t\t\t   \"lane2_sata_usb3\");\n+\tpriv->lane2_phy_indirect = devm_ioremap_resource(&pdev->dev, res);\n+\tif (IS_ERR(priv->lane2_phy_indirect))\n+\t\treturn PTR_ERR(priv->lane2_phy_indirect);\n+\n+\t/*\n+\t * Driver needs to know if reference xtal clock is 40MHz or 25MHz.\n+\t * Old DT bindings do not have xtal clk present. So do not fail here\n+\t * and expects that default 25MHz reference clock is used.\n+\t */\n+\tclk = clk_get(&pdev->dev, \"xtal\");\n+\tif (IS_ERR(clk)) {\n+\t\tif (PTR_ERR(clk) == -EPROBE_DEFER)\n+\t\t\treturn -EPROBE_DEFER;\n+\t\tdev_warn(&pdev->dev, \"missing 'xtal' clk (%ld)\\n\",\n+\t\t\t PTR_ERR(clk));\n+\t} else {\n+\t\tret = clk_prepare_enable(clk);\n+\t\tif (ret) {\n+\t\t\tdev_warn(&pdev->dev, \"enabling xtal clk failed (%d)\\n\",\n+\t\t\t\t ret);\n+\t\t} else {\n+\t\t\tif (clk_get_rate(clk) == 40000000)\n+\t\t\t\tpriv->xtal_is_40m = true;\n+\t\t\tclk_disable_unprepare(clk);\n+\t\t}\n+\t\tclk_put(clk);\n+\t}\n+\n+\tdev_set_drvdata(&pdev->dev, priv);\n \n \tfor_each_available_child_of_node(pdev->dev.of_node, child) {\n \t\tstruct mvebu_a3700_comphy_lane *lane;\n@@ -277,7 +1382,7 @@ static int mvebu_a3700_comphy_probe(stru\n \t\t\tcontinue;\n \t\t}\n \n-\t\tif (lane_id >= MVEBU_A3700_COMPHY_LANES) {\n+\t\tif (lane_id >= 3) {\n \t\t\tdev_err(&pdev->dev, \"invalid 'reg' property\\n\");\n \t\t\tcontinue;\n \t\t}\n@@ -295,11 +1400,21 @@ static int mvebu_a3700_comphy_probe(stru\n \t\t\treturn PTR_ERR(phy);\n \t\t}\n \n+\t\tlane->priv = priv;\n \t\tlane->dev = &pdev->dev;\n \t\tlane->mode = PHY_MODE_INVALID;\n \t\tlane->submode = PHY_INTERFACE_MODE_NA;\n \t\tlane->id = lane_id;\n+\t\tlane->invert_tx = false;\n+\t\tlane->invert_rx = false;\n \t\tphy_set_drvdata(phy, lane);\n+\n+\t\t/*\n+\t\t * To avoid relying on the bootloader/firmware configuration,\n+\t\t * power off all comphys.\n+\t\t */\n+\t\tmvebu_a3700_comphy_reset(phy);\n+\t\tlane->needs_reset = false;\n \t}\n \n \tprovider = devm_of_phy_provider_register(&pdev->dev,\n@@ -323,5 +1438,7 @@ static struct platform_driver mvebu_a370\n module_platform_driver(mvebu_a3700_comphy_driver);\n \n MODULE_AUTHOR(\"Miquèl Raynal <miquel.raynal@bootlin.com>\");\n+MODULE_AUTHOR(\"Pali Rohár <pali@kernel.org>\");\n+MODULE_AUTHOR(\"Marek Behún <kabel@kernel.org>\");\n MODULE_DESCRIPTION(\"Common PHY driver for A3700\");\n MODULE_LICENSE(\"GPL v2\");\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/851-0003-arm64-dts-marvell-armada-37xx-Add-xtal-clock-to-comp.patch",
    "content": "From 66c51c39fd4bf05e99debf0e71de5704231c57dc Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>\nDate: Thu, 23 Sep 2021 19:26:26 +0200\nSubject: [PATCH] arm64: dts: marvell: armada-37xx: Add xtal clock to comphy\n node\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nKernel driver phy-mvebu-a3700-comphy.c needs to know the rate of the\nreference xtal clock. So add missing xtal clock source into comphy device\ntree node. If the property is not present, the driver defaults to 25 MHz\nxtal rate (which, as far as we know, is used by all the existing boards).\n\nSigned-off-by: Pali Rohár <pali@kernel.org>\nSigned-off-by: Marek Behún <kabel@kernel.org>\n---\n arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 2 ++\n 1 file changed, 2 insertions(+)\n\n--- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi\n+++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi\n@@ -265,6 +265,8 @@\n \t\t\t\t\t    \"lane2_sata_usb3\";\n \t\t\t\t#address-cells = <1>;\n \t\t\t\t#size-cells = <0>;\n+\t\t\t\tclocks = <&xtalclk>;\n+\t\t\t\tclock-names = \"xtal\";\n \n \t\t\t\tcomphy0: phy@0 {\n \t\t\t\t\treg = <0>;\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/851-0004-Revert-ata-ahci-mvebu-Make-SATA-PHY-optional-for-Arm.patch",
    "content": "From 750bb44dbbe9dfb4ba3e1f8a746b831b39ba3cd9 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>\nDate: Thu, 23 Sep 2021 19:35:57 +0200\nSubject: [PATCH] Revert \"ata: ahci: mvebu: Make SATA PHY optional for Armada\n 3720\"\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nThis reverts commit 45aefe3d2251e4e229d7662052739f96ad1d08d9.\n\nArmada 3720 PHY driver (phy-mvebu-a3700-comphy.c) does not return\n-EOPNOTSUPP from phy_power_on() callback anymore.\n\nSo remove AHCI_HFLAG_IGN_NOTSUPP_POWER_ON flag from Armada 3720 plat data.\n\nAHCI_HFLAG_IGN_NOTSUPP_POWER_ON is not used by any other ahci driver, so\nremove this flag completely.\n\nSigned-off-by: Pali Rohár <pali@kernel.org>\nSigned-off-by: Marek Behún <kabel@kernel.org>\nAcked-by: Miquel Raynal <miquel.raynal@bootlin.com>\n---\n drivers/ata/ahci.h             | 2 --\n drivers/ata/ahci_mvebu.c       | 2 +-\n drivers/ata/libahci_platform.c | 2 +-\n 3 files changed, 2 insertions(+), 4 deletions(-)\n\n--- a/drivers/ata/ahci.h\n+++ b/drivers/ata/ahci.h\n@@ -240,8 +240,6 @@ enum {\n \t\t\t\t\t\t\tas default lpm_policy */\n \tAHCI_HFLAG_SUSPEND_PHYS\t\t= (1 << 26), /* handle PHYs during\n \t\t\t\t\t\t\tsuspend/resume */\n-\tAHCI_HFLAG_IGN_NOTSUPP_POWER_ON\t= (1 << 27), /* ignore -EOPNOTSUPP\n-\t\t\t\t\t\t\tfrom phy_power_on() */\n \tAHCI_HFLAG_NO_SXS\t\t= (1 << 28), /* SXS not supported */\n \n \t/* ap->flags bits */\n--- a/drivers/ata/ahci_mvebu.c\n+++ b/drivers/ata/ahci_mvebu.c\n@@ -227,7 +227,7 @@ static const struct ahci_mvebu_plat_data\n \n static const struct ahci_mvebu_plat_data ahci_mvebu_armada_3700_plat_data = {\n \t.plat_config = ahci_mvebu_armada_3700_config,\n-\t.flags = AHCI_HFLAG_SUSPEND_PHYS | AHCI_HFLAG_IGN_NOTSUPP_POWER_ON,\n+\t.flags = AHCI_HFLAG_SUSPEND_PHYS,\n };\n \n static const struct of_device_id ahci_mvebu_of_match[] = {\n--- a/drivers/ata/libahci_platform.c\n+++ b/drivers/ata/libahci_platform.c\n@@ -59,7 +59,7 @@ int ahci_platform_enable_phys(struct ahc\n \t\t}\n \n \t\trc = phy_power_on(hpriv->phys[i]);\n-\t\tif (rc && !(rc == -EOPNOTSUPP && (hpriv->flags & AHCI_HFLAG_IGN_NOTSUPP_POWER_ON))) {\n+\t\tif (rc) {\n \t\t\tphy_exit(hpriv->phys[i]);\n \t\t\tgoto disable_phys;\n \t\t}\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/851-0005-Revert-usb-host-xhci-mvebu-make-USB-3.0-PHY-optional.patch",
    "content": "From 9f0dfb279b1dd505d5e10b10e4a78a62030978d8 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>\nDate: Thu, 23 Sep 2021 19:40:06 +0200\nSubject: [PATCH] Revert \"usb: host: xhci: mvebu: make USB 3.0 PHY optional for\n Armada 3720\"\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nThis reverts commit 3241929b67d28c83945d3191c6816a3271fd6b85.\n\nArmada 3720 phy driver (phy-mvebu-a3700-comphy.c) does not return\n-EOPNOTSUPP from phy_power_on() callback anymore.\n\nSo remove XHCI_SKIP_PHY_INIT flag from xhci_mvebu_a3700_plat_setup() and\nthen also whole xhci_mvebu_a3700_plat_setup() function which is there just\nto handle -EOPNOTSUPP for XHCI_SKIP_PHY_INIT.\n\nxhci plat_setup callback is not used by any other xhci plat driver, so\nremove this callback completely.\n\nSigned-off-by: Pali Rohár <pali@kernel.org>\nSigned-off-by: Marek Behún <kabel@kernel.org>\nAcked-by: Miquel Raynal <miquel.raynal@bootlin.com>\n---\n drivers/usb/host/xhci-mvebu.c | 42 -----------------------------------\n drivers/usb/host/xhci-mvebu.h |  6 -----\n drivers/usb/host/xhci-plat.c  | 20 +----------------\n drivers/usb/host/xhci-plat.h  |  1 -\n 4 files changed, 1 insertion(+), 68 deletions(-)\n\n--- a/drivers/usb/host/xhci-mvebu.c\n+++ b/drivers/usb/host/xhci-mvebu.c\n@@ -8,7 +8,6 @@\n #include <linux/mbus.h>\n #include <linux/of.h>\n #include <linux/platform_device.h>\n-#include <linux/phy/phy.h>\n \n #include <linux/usb.h>\n #include <linux/usb/hcd.h>\n@@ -74,47 +73,6 @@ int xhci_mvebu_mbus_init_quirk(struct us\n \n \treturn 0;\n }\n-\n-int xhci_mvebu_a3700_plat_setup(struct usb_hcd *hcd)\n-{\n-\tstruct xhci_hcd *xhci = hcd_to_xhci(hcd);\n-\tstruct device *dev = hcd->self.controller;\n-\tstruct phy *phy;\n-\tint ret;\n-\n-\t/* Old bindings miss the PHY handle */\n-\tphy = of_phy_get(dev->of_node, \"usb3-phy\");\n-\tif (IS_ERR(phy) && PTR_ERR(phy) == -EPROBE_DEFER)\n-\t\treturn -EPROBE_DEFER;\n-\telse if (IS_ERR(phy))\n-\t\tgoto phy_out;\n-\n-\tret = phy_init(phy);\n-\tif (ret)\n-\t\tgoto phy_put;\n-\n-\tret = phy_set_mode(phy, PHY_MODE_USB_HOST_SS);\n-\tif (ret)\n-\t\tgoto phy_exit;\n-\n-\tret = phy_power_on(phy);\n-\tif (ret == -EOPNOTSUPP) {\n-\t\t/* Skip initializatin of XHCI PHY when it is unsupported by firmware */\n-\t\tdev_warn(dev, \"PHY unsupported by firmware\\n\");\n-\t\txhci->quirks |= XHCI_SKIP_PHY_INIT;\n-\t}\n-\tif (ret)\n-\t\tgoto phy_exit;\n-\n-\tphy_power_off(phy);\n-phy_exit:\n-\tphy_exit(phy);\n-phy_put:\n-\tof_phy_put(phy);\n-phy_out:\n-\n-\treturn 0;\n-}\n \n int xhci_mvebu_a3700_init_quirk(struct usb_hcd *hcd)\n {\n--- a/drivers/usb/host/xhci-mvebu.h\n+++ b/drivers/usb/host/xhci-mvebu.h\n@@ -12,18 +12,12 @@ struct usb_hcd;\n \n #if IS_ENABLED(CONFIG_USB_XHCI_MVEBU)\n int xhci_mvebu_mbus_init_quirk(struct usb_hcd *hcd);\n-int xhci_mvebu_a3700_plat_setup(struct usb_hcd *hcd);\n int xhci_mvebu_a3700_init_quirk(struct usb_hcd *hcd);\n #else\n static inline int xhci_mvebu_mbus_init_quirk(struct usb_hcd *hcd)\n {\n \treturn 0;\n }\n-\n-static inline int xhci_mvebu_a3700_plat_setup(struct usb_hcd *hcd)\n-{\n-\treturn 0;\n-}\n \n static inline int xhci_mvebu_a3700_init_quirk(struct usb_hcd *hcd)\n {\n--- a/drivers/usb/host/xhci-plat.c\n+++ b/drivers/usb/host/xhci-plat.c\n@@ -44,16 +44,6 @@ static void xhci_priv_plat_start(struct\n \t\tpriv->plat_start(hcd);\n }\n \n-static int xhci_priv_plat_setup(struct usb_hcd *hcd)\n-{\n-\tstruct xhci_plat_priv *priv = hcd_to_xhci_priv(hcd);\n-\n-\tif (!priv->plat_setup)\n-\t\treturn 0;\n-\n-\treturn priv->plat_setup(hcd);\n-}\n-\n static int xhci_priv_init_quirk(struct usb_hcd *hcd)\n {\n \tstruct xhci_plat_priv *priv = hcd_to_xhci_priv(hcd);\n@@ -121,7 +111,6 @@ static const struct xhci_plat_priv xhci_\n };\n \n static const struct xhci_plat_priv xhci_plat_marvell_armada3700 = {\n-\t.plat_setup = xhci_mvebu_a3700_plat_setup,\n \t.init_quirk = xhci_mvebu_a3700_init_quirk,\n };\n \n@@ -341,14 +330,7 @@ static int xhci_plat_probe(struct platfo\n \n \thcd->tpl_support = of_usb_host_tpl_support(sysdev->of_node);\n \txhci->shared_hcd->tpl_support = hcd->tpl_support;\n-\n-\tif (priv) {\n-\t\tret = xhci_priv_plat_setup(hcd);\n-\t\tif (ret)\n-\t\t\tgoto disable_usb_phy;\n-\t}\n-\n-\tif ((xhci->quirks & XHCI_SKIP_PHY_INIT) || (priv && (priv->quirks & XHCI_SKIP_PHY_INIT)))\n+\tif (priv && (priv->quirks & XHCI_SKIP_PHY_INIT))\n \t\thcd->skip_phy_initialization = 1;\n \n \tif (priv && (priv->quirks & XHCI_SG_TRB_CACHE_SIZE_QUIRK))\n--- a/drivers/usb/host/xhci-plat.h\n+++ b/drivers/usb/host/xhci-plat.h\n@@ -13,7 +13,6 @@\n struct xhci_plat_priv {\n \tconst char *firmware_name;\n \tunsigned long long quirks;\n-\tint (*plat_setup)(struct usb_hcd *);\n \tvoid (*plat_start)(struct usb_hcd *);\n \tint (*init_quirk)(struct usb_hcd *);\n \tint (*suspend_quirk)(struct usb_hcd *);\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/851-0006-Revert-PCI-aardvark-Fix-initialization-with-old-Marv.patch",
    "content": "From 9a352062b7e3857742389dff6f64393481dc755e Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>\nDate: Thu, 23 Sep 2021 19:37:05 +0200\nSubject: [PATCH] Revert \"PCI: aardvark: Fix initialization with old Marvell's\n Arm Trusted Firmware\"\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nThis reverts commit b0c6ae0f8948a2be6bf4e8b4bbab9ca1343289b6.\n\nArmada 3720 phy driver (phy-mvebu-a3700-comphy.c) does not return\n-EOPNOTSUPP from phy_power_on() callback anymore.\n\nSo remove dead code which handles -EOPNOTSUPP return value.\n\nSigned-off-by: Pali Rohár <pali@kernel.org>\nSigned-off-by: Marek Behún <kabel@kernel.org>\nAcked-by: Miquel Raynal <miquel.raynal@bootlin.com>\n---\n drivers/pci/controller/pci-aardvark.c | 4 +---\n 1 file changed, 1 insertion(+), 3 deletions(-)\n\n--- a/drivers/pci/controller/pci-aardvark.c\n+++ b/drivers/pci/controller/pci-aardvark.c\n@@ -1637,9 +1637,7 @@ static int advk_pcie_enable_phy(struct a\n \t}\n \n \tret = phy_power_on(pcie->phy);\n-\tif (ret == -EOPNOTSUPP) {\n-\t\tdev_warn(&pcie->pdev->dev, \"PHY unsupported by firmware\\n\");\n-\t} else if (ret) {\n+\tif (ret) {\n \t\tphy_exit(pcie->phy);\n \t\treturn ret;\n \t}\n"
  },
  {
    "path": "target/linux/generic/pending-5.10/920-mangle_bootargs.patch",
    "content": "From: Imre Kaloz <kaloz@openwrt.org>\nSubject: init: add CONFIG_MANGLE_BOOTARGS and disable it by default\n\nEnabling this option renames the bootloader supplied root=\nand rootfstype= variables, which might have to be know but\nwould break the automatisms OpenWrt uses.\n\nSigned-off-by: Imre Kaloz <kaloz@openwrt.org>\n---\n init/Kconfig |  9 +++++++++\n init/main.c  | 24 ++++++++++++++++++++++++\n 2 files changed, 33 insertions(+)\n\n--- a/init/Kconfig\n+++ b/init/Kconfig\n@@ -1800,6 +1800,15 @@ config EMBEDDED\n \t  an embedded system so certain expert options are available\n \t  for configuration.\n \n+config MANGLE_BOOTARGS\n+\tbool \"Rename offending bootargs\"\n+\tdepends on EXPERT\n+\thelp\n+\t  Sometimes the bootloader passed bogus root= and rootfstype=\n+\t  parameters to the kernel, and while you want to ignore them,\n+\t  you need to know the values f.e. to support dual firmware\n+\t  layouts on the flash.\n+\n config HAVE_PERF_EVENTS\n \tbool\n \thelp\n--- a/init/main.c\n+++ b/init/main.c\n@@ -608,6 +608,29 @@ static inline void setup_nr_cpu_ids(void\n static inline void smp_prepare_cpus(unsigned int maxcpus) { }\n #endif\n \n+#ifdef CONFIG_MANGLE_BOOTARGS\n+static void __init mangle_bootargs(char *command_line)\n+{\n+\tchar *rootdev;\n+\tchar *rootfs;\n+\n+\trootdev = strstr(command_line, \"root=/dev/mtdblock\");\n+\n+\tif (rootdev)\n+\t\tstrncpy(rootdev, \"mangled_rootblock=\", 18);\n+\n+\trootfs = strstr(command_line, \"rootfstype\");\n+\n+\tif (rootfs)\n+\t\tstrncpy(rootfs, \"mangled_fs\", 10);\n+\n+}\n+#else\n+static void __init mangle_bootargs(char *command_line)\n+{\n+}\n+#endif\n+\n /*\n  * We need to store the untouched command line for future reference.\n  * We also need to store the touched command line since the parameter\n@@ -869,6 +892,7 @@ asmlinkage __visible void __init __no_sa\n \tpr_notice(\"%s\", linux_banner);\n \tearly_security_init();\n \tsetup_arch(&command_line);\n+\tmangle_bootargs(command_line);\n \tsetup_boot_config(command_line);\n \tsetup_command_line(command_line);\n \tsetup_nr_cpu_ids();\n"
  },
  {
    "path": "target/linux/generic/pending-5.15/050-dtc-checks-Drop-interrupt-provider-address-cells-check.patch",
    "content": "From d8d1a9a77863a8c7031ae82a1d461aa78eb72a7b Mon Sep 17 00:00:00 2001\nFrom: Rob Herring <robh@kernel.org>\nDate: Mon, 11 Oct 2021 14:12:43 -0500\nSubject: [PATCH] checks: Drop interrupt provider '#address-cells' check\n\n'#address-cells' is only needed when parsing 'interrupt-map' properties, so\nremove it from the common interrupt-provider test.\n\nCc: Andre Przywara <andre.przywara@arm.com>\nReviewed-by: David Gibson <david@gibson.dropbear.id.au>\nSigned-off-by: Rob Herring <robh@kernel.org>\nMessage-Id: <20211011191245.1009682-3-robh@kernel.org>\nSigned-off-by: David Gibson <david@gibson.dropbear.id.au>\n---\n--- a/scripts/dtc/checks.c\n+++ b/scripts/dtc/checks.c\n@@ -1569,11 +1569,6 @@ static void check_interrupt_provider(str\n \tif (!prop)\n \t\tFAIL(c, dti, node,\n \t\t     \"Missing #interrupt-cells in interrupt provider\");\n-\n-\tprop = get_property(node, \"#address-cells\");\n-\tif (!prop)\n-\t\tFAIL(c, dti, node,\n-\t\t     \"Missing #address-cells in interrupt provider\");\n }\n WARNING(interrupt_provider, check_interrupt_provider, NULL);\n \n"
  },
  {
    "path": "target/linux/generic/pending-5.15/100-compiler.h-only-include-asm-rwonce.h-for-kernel-code.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nDate: Thu, 22 Oct 2020 22:00:03 +0200\nSubject: [PATCH] compiler.h: only include asm/rwonce.h for kernel code\n\nThis header file is not in uapi, which makes any user space code that includes\nlinux/compiler.h to fail with the error 'asm/rwonce.h: No such file or directory'\n\nFixes: e506ea451254 (\"compiler.h: Split {READ,WRITE}_ONCE definitions out into rwonce.h\")\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n\n--- a/include/linux/compiler.h\n+++ b/include/linux/compiler.h\n@@ -220,6 +220,8 @@ void ftrace_likely_update(struct ftrace_\n #define function_nocfi(x) (x)\n #endif\n \n+#include <asm/rwonce.h>\n+\n #endif /* __KERNEL__ */\n \n /*\n@@ -252,6 +254,4 @@ static inline void *offset_to_ptr(const\n  */\n #define prevent_tail_call_optimization()\tmb()\n \n-#include <asm/rwonce.h>\n-\n #endif /* __LINUX_COMPILER_H */\n"
  },
  {
    "path": "target/linux/generic/pending-5.15/101-Use-stddefs.h-instead-of-compiler.h.patch",
    "content": "--- a/include/uapi/linux/swab.h\n+++ b/include/uapi/linux/swab.h\n@@ -3,7 +3,7 @@\n #define _UAPI_LINUX_SWAB_H\n \n #include <linux/types.h>\n-#include <linux/compiler.h>\n+#include <linux/stddef.h>\n #include <asm/bitsperlong.h>\n #include <asm/swab.h>\n \n"
  },
  {
    "path": "target/linux/generic/pending-5.15/102-MIPS-only-process-negative-stack-offsets-on-stack-tr.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nDate: Wed, 18 Apr 2018 10:50:05 +0200\nSubject: [PATCH] MIPS: only process negative stack offsets on stack traces\n\nFixes endless back traces in cases where the compiler emits a stack\npointer increase in a branch delay slot (probably for some form of\nfunction return).\n\n[    3.475442] BUG: MAX_STACK_TRACE_ENTRIES too low!\n[    3.480070] turning off the locking correctness validator.\n[    3.485521] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.14.34 #0\n[    3.491475] Stack : 00000000 00000000 00000000 00000000 80e0fce2 00000034 00000000 00000000\n[    3.499764]         87c3838c 80696377 8061047c 00000000 00000001 00000001 87c2d850 6534689f\n[    3.508059]         00000000 00000000 80e10000 00000000 00000000 000000cf 0000000f 00000000\n[    3.516353]         00000000 806a0000 00076891 00000000 00000000 00000000 ffffffff 00000000\n[    3.524648]         806c0000 00000004 80e10000 806a0000 00000003 80690000 00000000 80700000\n[    3.532942]         ...\n[    3.535362] Call Trace:\n[    3.537818] [<80010a48>] show_stack+0x58/0x100\n[    3.542207] [<804c2f78>] dump_stack+0xe8/0x170\n[    3.546613] [<80079f90>] save_trace+0xf0/0x110\n[    3.551010] [<8007b1ec>] mark_lock+0x33c/0x78c\n[    3.555413] [<8007bf48>] __lock_acquire+0x2ac/0x1a08\n[    3.560337] [<8007de60>] lock_acquire+0x64/0x8c\n[    3.564846] [<804e1570>] _raw_spin_lock_irqsave+0x54/0x78\n[    3.570186] [<801b618c>] kernfs_notify+0x94/0xac\n[    3.574770] [<801b7b10>] sysfs_notify+0x74/0xa0\n[    3.579257] [<801b618c>] kernfs_notify+0x94/0xac\n[    3.583839] [<801b7b10>] sysfs_notify+0x74/0xa0\n[    3.588329] [<801b618c>] kernfs_notify+0x94/0xac\n[    3.592911] [<801b7b10>] sysfs_notify+0x74/0xa0\n[    3.597401] [<801b618c>] kernfs_notify+0x94/0xac\n[    3.601983] [<801b7b10>] sysfs_notify+0x74/0xa0\n[    3.606473] [<801b618c>] kernfs_notify+0x94/0xac\n[    3.611055] [<801b7b10>] sysfs_notify+0x74/0xa0\n[    3.615545] [<801b618c>] kernfs_notify+0x94/0xac\n[    3.620125] [<801b7b10>] sysfs_notify+0x74/0xa0\n[    3.624619] [<801b618c>] kernfs_notify+0x94/0xac\n[    3.629197] [<801b7b10>] sysfs_notify+0x74/0xa0\n[    3.633691] [<801b618c>] kernfs_notify+0x94/0xac\n[    3.638269] [<801b7b10>] sysfs_notify+0x74/0xa0\n[    3.642763] [<801b618c>] kernfs_notify+0x94/0xac\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n\n--- a/arch/mips/kernel/process.c\n+++ b/arch/mips/kernel/process.c\n@@ -393,6 +393,8 @@ static inline int is_sp_move_ins(union m\n \n \tif (ip->i_format.opcode == addiu_op ||\n \t    ip->i_format.opcode == daddiu_op) {\n+\t\tif (ip->i_format.simmediate > 0)\n+\t\t\treturn 0;\n \t\t*frame_size = -ip->i_format.simmediate;\n \t\treturn 1;\n \t}\n"
  },
  {
    "path": "target/linux/generic/pending-5.15/120-Fix-alloc_node_mem_map-with-ARCH_PFN_OFFSET-calcu.patch",
    "content": "From: Tobias Wolf <dev-NTEO@vplace.de>\nSubject: mm: Fix alloc_node_mem_map with ARCH_PFN_OFFSET calculation\n\nAn rt288x (ralink) based router (Belkin F5D8235 v1) does not boot with any\nkernel beyond version 4.3 resulting in:\n\nBUG: Bad page state in process swapper  pfn:086ac\n\nbisect resulted in:\n\na1c34a3bf00af2cede839879502e12dc68491ad5 is the first bad commit\ncommit a1c34a3bf00af2cede839879502e12dc68491ad5\nAuthor: Laura Abbott <laura@labbott.name>\nDate:   Thu Nov 5 18:48:46 2015 -0800\n\n    mm: Don't offset memmap for flatmem\n\n    Srinivas Kandagatla reported bad page messages when trying to remove the\n    bottom 2MB on an ARM based IFC6410 board\n\n      BUG: Bad page state in process swapper  pfn:fffa8\n      page:ef7fb500 count:0 mapcount:0 mapping:  (null) index:0x0\n      flags: 0x96640253(locked|error|dirty|active|arch_1|reclaim|mlocked)\n      page dumped because: PAGE_FLAGS_CHECK_AT_FREE flag(s) set\n      bad because of flags:\n      flags: 0x200041(locked|active|mlocked)\n      Modules linked in:\n      CPU: 0 PID: 0 Comm: swapper Not tainted 3.19.0-rc3-00007-g412f9ba-dirty\n#816\n      Hardware name: Qualcomm (Flattened Device Tree)\n        unwind_backtrace\n        show_stack\n        dump_stack\n        bad_page\n        free_pages_prepare\n        free_hot_cold_page\n        __free_pages\n        free_highmem_page\n        mem_init\n        start_kernel\n      Disabling lock debugging due to kernel taint\n    [...]\n:040000 040000 2de013c372345fd471cd58f0553c9b38b0ef1cc4\n0a8156f848733dfa21e16c196dfb6c0a76290709 M      mm\n\nThis fix for ARM does not account ARCH_PFN_OFFSET for mem_map as later used by\npage_to_pfn anymore.\n\nThe following output was generated with two hacked in printk statements:\n\nprintk(\"before %p vs. %p or %p\\n\", mem_map, mem_map - offset, mem_map -\n(pgdat->node_start_pfn - ARCH_PFN_OFFSET));\n\t\tif (page_to_pfn(mem_map) != pgdat->node_start_pfn)\n\t\t\tmem_map -= offset + (pgdat->node_start_pfn - ARCH_PFN_OFFSET);\nprintk(\"after %p\\n\", mem_map);\n\nOutput:\n\n[    0.000000] before 8861b280 vs. 8861b280 or 8851b280\n[    0.000000] after 8851b280\n\nAs seen in the first line mem_map with subtraction of offset does not equal the\nmem_map after subtraction of ARCH_PFN_OFFSET.\n\nAfter adding the offset of ARCH_PFN_OFFSET as well to mem_map as the\npreviously calculated offset is zero for the named platform it is able to boot\n4.4 and 4.9-rc7 again.\n\nSigned-off-by: Tobias Wolf <dev-NTEO@vplace.de>\n---\n\n--- a/mm/page_alloc.c\n+++ b/mm/page_alloc.c\n@@ -7552,7 +7552,7 @@ static void __init alloc_node_mem_map(st\n \tif (pgdat == NODE_DATA(0)) {\n \t\tmem_map = NODE_DATA(0)->node_mem_map;\n \t\tif (page_to_pfn(mem_map) != pgdat->node_start_pfn)\n-\t\t\tmem_map -= offset;\n+\t\t\tmem_map -= offset + (pgdat->node_start_pfn - ARCH_PFN_OFFSET);\n \t}\n #endif\n }\n"
  },
  {
    "path": "target/linux/generic/pending-5.15/130-add-linux-spidev-compatible-si3210.patch",
    "content": "From: Giuseppe Lippolis <giu.lippolis@gmail.com>\nSubject: Add the linux,spidev compatible in spidev Several device in ramips have this binding in the dts\n\nSigned-off-by: Giuseppe Lippolis <giu.lippolis@gmail.com>\n---\n drivers/spi/spidev.c | 1 +\n 1 file changed, 1 insertion(+)\n\n--- a/drivers/spi/spidev.c\n+++ b/drivers/spi/spidev.c\n@@ -696,6 +696,7 @@ static const struct of_device_id spidev_\n \t{ .compatible = \"menlo,m53cpld\" },\n \t{ .compatible = \"cisco,spi-petra\" },\n \t{ .compatible = \"micron,spi-authenta\" },\n+\t{ .compatible = \"siliconlabs,si3210\" },\n \t{},\n };\n MODULE_DEVICE_TABLE(of, spidev_dt_ids);\n"
  },
  {
    "path": "target/linux/generic/pending-5.15/140-jffs2-use-.rename2-and-add-RENAME_WHITEOUT-support.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nSubject: jffs2: use .rename2 and add RENAME_WHITEOUT support\n\nIt is required for renames on overlayfs\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n\n--- a/fs/jffs2/dir.c\n+++ b/fs/jffs2/dir.c\n@@ -614,8 +614,8 @@ static int jffs2_rmdir (struct inode *di\n \treturn ret;\n }\n \n-static int jffs2_mknod (struct user_namespace *mnt_userns, struct inode *dir_i,\n-\t\t        struct dentry *dentry, umode_t mode, dev_t rdev)\n+static int __jffs2_mknod (struct user_namespace *mnt_userns, struct inode *dir_i,\n+\t\t\t  struct dentry *dentry, umode_t mode, dev_t rdev, bool whiteout)\n {\n \tstruct jffs2_inode_info *f, *dir_f;\n \tstruct jffs2_sb_info *c;\n@@ -754,7 +754,11 @@ static int jffs2_mknod (struct user_name\n \tmutex_unlock(&dir_f->sem);\n \tjffs2_complete_reservation(c);\n \n-\td_instantiate_new(dentry, inode);\n+\tif (!whiteout)\n+\t\td_instantiate_new(dentry, inode);\n+\telse\n+\t\tunlock_new_inode(inode);\n+\n \treturn 0;\n \n  fail:\n@@ -762,6 +766,19 @@ static int jffs2_mknod (struct user_name\n \treturn ret;\n }\n \n+static int jffs2_mknod (struct user_namespace *mnt_userns, struct inode *dir_i,\n+\t\t\t  struct dentry *dentry, umode_t mode, dev_t rdev)\n+{\n+\treturn __jffs2_mknod(mnt_userns, dir_i, dentry, mode, rdev, false);\n+}\n+\n+static int jffs2_whiteout (struct user_namespace *mnt_userns, struct inode *old_dir,\n+\t\t\t    struct dentry *old_dentry)\n+{\n+\treturn __jffs2_mknod(mnt_userns, old_dir, old_dentry, S_IFCHR | WHITEOUT_MODE,\n+\t\t\t     WHITEOUT_DEV, true);\n+}\n+\n static int jffs2_rename (struct user_namespace *mnt_userns,\n \t\t\t struct inode *old_dir_i, struct dentry *old_dentry,\n \t\t\t struct inode *new_dir_i, struct dentry *new_dentry,\n@@ -773,7 +790,7 @@ static int jffs2_rename (struct user_nam\n \tuint8_t type;\n \tuint32_t now;\n \n-\tif (flags & ~RENAME_NOREPLACE)\n+\tif (flags & ~(RENAME_NOREPLACE|RENAME_WHITEOUT))\n \t\treturn -EINVAL;\n \n \t/* The VFS will check for us and prevent trying to rename a\n@@ -839,9 +856,14 @@ static int jffs2_rename (struct user_nam\n \tif (d_is_dir(old_dentry) && !victim_f)\n \t\tinc_nlink(new_dir_i);\n \n-\t/* Unlink the original */\n-\tret = jffs2_do_unlink(c, JFFS2_INODE_INFO(old_dir_i),\n-\t\t\t      old_dentry->d_name.name, old_dentry->d_name.len, NULL, now);\n+\tif (flags & RENAME_WHITEOUT)\n+\t\t/* Replace with whiteout */\n+\t\tret = jffs2_whiteout(mnt_userns, old_dir_i, old_dentry);\n+\telse\n+\t\t/* Unlink the original */\n+\t\tret = jffs2_do_unlink(c, JFFS2_INODE_INFO(old_dir_i),\n+\t\t\t\t      old_dentry->d_name.name,\n+\t\t\t\t      old_dentry->d_name.len, NULL, now);\n \n \t/* We don't touch inode->i_nlink */\n \n"
  },
  {
    "path": "target/linux/generic/pending-5.15/141-jffs2-add-RENAME_EXCHANGE-support.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nSubject: jffs2: add RENAME_EXCHANGE support\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n\n--- a/fs/jffs2/dir.c\n+++ b/fs/jffs2/dir.c\n@@ -787,18 +787,31 @@ static int jffs2_rename (struct user_nam\n \tint ret;\n \tstruct jffs2_sb_info *c = JFFS2_SB_INFO(old_dir_i->i_sb);\n \tstruct jffs2_inode_info *victim_f = NULL;\n+\tstruct inode *fst_inode = d_inode(old_dentry);\n+\tstruct inode *snd_inode = d_inode(new_dentry);\n \tuint8_t type;\n \tuint32_t now;\n \n-\tif (flags & ~(RENAME_NOREPLACE|RENAME_WHITEOUT))\n+\tif (flags & ~(RENAME_NOREPLACE|RENAME_WHITEOUT|RENAME_EXCHANGE))\n \t\treturn -EINVAL;\n \n+\tif ((flags & RENAME_EXCHANGE) && (old_dir_i != new_dir_i)) {\n+\t\tif (S_ISDIR(fst_inode->i_mode) && !S_ISDIR(snd_inode->i_mode)) {\n+\t\t\tinc_nlink(new_dir_i);\n+\t\t\tdrop_nlink(old_dir_i);\n+\t\t}\n+\t\telse if (!S_ISDIR(fst_inode->i_mode) && S_ISDIR(snd_inode->i_mode)) {\n+\t\t\tdrop_nlink(new_dir_i);\n+\t\t\tinc_nlink(old_dir_i);\n+\t\t}\n+\t}\n+\n \t/* The VFS will check for us and prevent trying to rename a\n \t * file over a directory and vice versa, but if it's a directory,\n \t * the VFS can't check whether the victim is empty. The filesystem\n \t * needs to do that for itself.\n \t */\n-\tif (d_really_is_positive(new_dentry)) {\n+\tif (d_really_is_positive(new_dentry) && !(flags & RENAME_EXCHANGE)) {\n \t\tvictim_f = JFFS2_INODE_INFO(d_inode(new_dentry));\n \t\tif (d_is_dir(new_dentry)) {\n \t\t\tstruct jffs2_full_dirent *fd;\n@@ -833,7 +846,7 @@ static int jffs2_rename (struct user_nam\n \tif (ret)\n \t\treturn ret;\n \n-\tif (victim_f) {\n+\tif (victim_f && !(flags & RENAME_EXCHANGE)) {\n \t\t/* There was a victim. Kill it off nicely */\n \t\tif (d_is_dir(new_dentry))\n \t\t\tclear_nlink(d_inode(new_dentry));\n@@ -859,6 +872,12 @@ static int jffs2_rename (struct user_nam\n \tif (flags & RENAME_WHITEOUT)\n \t\t/* Replace with whiteout */\n \t\tret = jffs2_whiteout(mnt_userns, old_dir_i, old_dentry);\n+\telse if (flags & RENAME_EXCHANGE)\n+\t\t/* Replace the original */\n+\t\tret = jffs2_do_link(c, JFFS2_INODE_INFO(old_dir_i),\n+\t\t\t\t    d_inode(new_dentry)->i_ino, type,\n+\t\t\t\t    old_dentry->d_name.name, old_dentry->d_name.len,\n+\t\t\t\t    now);\n \telse\n \t\t/* Unlink the original */\n \t\tret = jffs2_do_unlink(c, JFFS2_INODE_INFO(old_dir_i),\n@@ -890,7 +909,7 @@ static int jffs2_rename (struct user_nam\n \t\treturn ret;\n \t}\n \n-\tif (d_is_dir(old_dentry))\n+\tif (d_is_dir(old_dentry) && !(flags & RENAME_EXCHANGE))\n \t\tdrop_nlink(old_dir_i);\n \n \tnew_dir_i->i_mtime = new_dir_i->i_ctime = old_dir_i->i_mtime = old_dir_i->i_ctime = ITIME(now);\n"
  },
  {
    "path": "target/linux/generic/pending-5.15/142-jffs2-add-splice-ops.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nSubject: jffs2: add splice ops\n\nAdd splice_read using generic_file_splice_read.\nAdd splice_write using iter_file_splice_write\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n\n--- a/fs/jffs2/file.c\n+++ b/fs/jffs2/file.c\n@@ -53,6 +53,8 @@ const struct file_operations jffs2_file_\n \t.open =\t\tgeneric_file_open,\n  \t.read_iter =\tgeneric_file_read_iter,\n  \t.write_iter =\tgeneric_file_write_iter,\n+\t.splice_read =\tgeneric_file_splice_read,\n+\t.splice_write =\titer_file_splice_write,\n \t.unlocked_ioctl=jffs2_ioctl,\n \t.mmap =\t\tgeneric_file_readonly_mmap,\n \t.fsync =\tjffs2_fsync,\n"
  },
  {
    "path": "target/linux/generic/pending-5.15/150-bridge_allow_receiption_on_disabled_port.patch",
    "content": "From: Stephen Hemminger <stephen@networkplumber.org>\nSubject: bridge: allow receiption on disabled port\n\nWhen an ethernet device is enslaved to a bridge, and the bridge STP\ndetects loss of carrier (or operational state down), then normally\npacket receiption is blocked.\n\nThis breaks control applications like WPA which maybe expecting to\nreceive packets to negotiate to bring link up. The bridge needs to\nblock forwarding packets from these disabled ports, but there is no\nhard requirement to not allow local packet delivery.\n\nSigned-off-by: Stephen Hemminger <stephen@networkplumber.org>\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n\n--- a/net/bridge/br_input.c\n+++ b/net/bridge/br_input.c\n@@ -197,6 +197,9 @@ static void __br_handle_local_finish(str\n /* note: already called with rcu_read_lock */\n static int br_handle_local_finish(struct net *net, struct sock *sk, struct sk_buff *skb)\n {\n+\tstruct net_bridge_port *p = br_port_get_rcu(skb->dev);\n+\n+\tif (p->state != BR_STATE_DISABLED)\n \t__br_handle_local_finish(skb);\n \n \t/* return 1 to signal the okfn() was called so it's ok to use the skb */\n@@ -362,6 +365,17 @@ static rx_handler_result_t br_handle_fra\n \n forward:\n \tswitch (p->state) {\n+\tcase BR_STATE_DISABLED:\n+\t\tif (ether_addr_equal(p->br->dev->dev_addr, dest))\n+\t\t\tskb->pkt_type = PACKET_HOST;\n+\n+\t\tif (NF_HOOK(NFPROTO_BRIDGE, NF_BR_PRE_ROUTING,\n+\t\t\tdev_net(skb->dev), NULL, skb, skb->dev, NULL,\n+\t\t\tbr_handle_local_finish) == 1) {\n+\t\t\treturn RX_HANDLER_PASS;\n+\t\t}\n+\t\tbreak;\n+\n \tcase BR_STATE_FORWARDING:\n \tcase BR_STATE_LEARNING:\n \t\tif (ether_addr_equal(p->br->dev->dev_addr, dest))\n"
  },
  {
    "path": "target/linux/generic/pending-5.15/190-rtc-rs5c372-support_alarms_up_to_1_week.patch",
    "content": "From: Daniel González Cabanelas <dgcbueu@gmail.com>\nSubject: [PATCH 1/2] rtc: rs5c372: support alarms up to 1 week\n\nThe Ricoh R2221x, R2223x, RS5C372, RV5C387A chips can handle 1 week\nalarms.\n\nRead the \"wday\" alarm register and convert it to a date to support up 1\nweek in our driver.\n\nSigned-off-by: Daniel González Cabanelas <dgcbueu@gmail.com>\n---\n drivers/rtc/rtc-rs5c372.c | 48 ++++++++++++++++++++++++++++++++++-----\n 1 file changed, 42 insertions(+), 6 deletions(-)\n\n--- a/drivers/rtc/rtc-rs5c372.c\n+++ b/drivers/rtc/rtc-rs5c372.c\n@@ -393,7 +393,9 @@ static int rs5c_read_alarm(struct device\n {\n \tstruct i2c_client\t*client = to_i2c_client(dev);\n \tstruct rs5c372\t\t*rs5c = i2c_get_clientdata(client);\n-\tint\t\t\tstatus;\n+\tint\t\t\tstatus, wday_offs;\n+\tstruct rtc_time \trtc;\n+\tunsigned long \t\talarm_secs;\n \n \tstatus = rs5c_get_regs(rs5c);\n \tif (status < 0)\n@@ -403,6 +405,30 @@ static int rs5c_read_alarm(struct device\n \tt->time.tm_sec = 0;\n \tt->time.tm_min = bcd2bin(rs5c->regs[RS5C_REG_ALARM_A_MIN] & 0x7f);\n \tt->time.tm_hour = rs5c_reg2hr(rs5c, rs5c->regs[RS5C_REG_ALARM_A_HOURS]);\n+\tt->time.tm_wday = ffs(rs5c->regs[RS5C_REG_ALARM_A_WDAY] & 0x7f) - 1;\n+\n+\t/* determine the day, month and year based on alarm wday, taking as a\n+\t * reference the current time from the rtc\n+\t */\n+\tstatus = rs5c372_rtc_read_time(dev, &rtc);\n+\tif (status < 0)\n+\t\treturn status;\n+\n+\twday_offs = t->time.tm_wday - rtc.tm_wday;\n+\talarm_secs = mktime64(rtc.tm_year + 1900,\n+\t\t\t      rtc.tm_mon + 1,\n+\t\t\t      rtc.tm_mday + wday_offs,\n+\t\t\t      t->time.tm_hour,\n+\t\t\t      t->time.tm_min,\n+\t\t\t      t->time.tm_sec);\n+\n+\tif (wday_offs < 0 || (wday_offs == 0 &&\n+\t\t\t      (t->time.tm_hour < rtc.tm_hour ||\n+\t\t\t       (t->time.tm_hour == rtc.tm_hour &&\n+\t\t\t\tt->time.tm_min <= rtc.tm_min))))\n+\t\talarm_secs += 7 * 86400;\n+\n+\trtc_time64_to_tm(alarm_secs, &t->time);\n \n \t/* ... and status */\n \tt->enabled = !!(rs5c->regs[RS5C_REG_CTRL1] & RS5C_CTRL1_AALE);\n@@ -417,12 +443,20 @@ static int rs5c_set_alarm(struct device\n \tstruct rs5c372\t\t*rs5c = i2c_get_clientdata(client);\n \tint\t\t\tstatus, addr, i;\n \tunsigned char\t\tbuf[3];\n+\tstruct rtc_time \trtc_tm;\n+\tunsigned long \t\trtc_secs, alarm_secs;\n \n-\t/* only handle up to 24 hours in the future, like RTC_ALM_SET */\n-\tif (t->time.tm_mday != -1\n-\t\t\t|| t->time.tm_mon != -1\n-\t\t\t|| t->time.tm_year != -1)\n+\t/* chip only can handle alarms up to one week in the future*/\n+\tstatus = rs5c372_rtc_read_time(dev, &rtc_tm);\n+\tif (status)\n+\t\treturn status;\n+\trtc_secs = rtc_tm_to_time64(&rtc_tm);\n+\talarm_secs = rtc_tm_to_time64(&t->time);\n+\tif (alarm_secs >= rtc_secs + 7 * 86400) {\n+\t\tdev_err(dev, \"%s: alarm maximum is one week in the future (%d)\\n\",\n+\t\t\t__func__, status);\n \t\treturn -EINVAL;\n+\t}\n \n \t/* REVISIT: round up tm_sec */\n \n@@ -443,7 +477,9 @@ static int rs5c_set_alarm(struct device\n \t/* set alarm */\n \tbuf[0] = bin2bcd(t->time.tm_min);\n \tbuf[1] = rs5c_hr2reg(rs5c, t->time.tm_hour);\n-\tbuf[2] = 0x7f;\t/* any/all days */\n+\t/* each bit is the day of the week, 0x7f means all days */\n+\tbuf[2] = (t->time.tm_wday >= 0 && t->time.tm_wday < 7) ?\n+\t\t  BIT(t->time.tm_wday) : 0x7f;\n \n \tfor (i = 0; i < sizeof(buf); i++) {\n \t\taddr = RS5C_ADDR(RS5C_REG_ALARM_A_MIN + i);\n"
  },
  {
    "path": "target/linux/generic/pending-5.15/191-rtc-rs5c372-let_the_alarm_to_be_used_as_wakeup_source.patch",
    "content": "From: Daniel González Cabanelas <dgcbueu@gmail.com>\nSubject: [PATCH 2/2] rtc: rs5c372: let the alarm to be used as wakeup source\n\nCurrently there is no use for the interrupts on the rs5c372 RTC and the\nwakealarm isn't enabled. There are some devices like NASes which use this\nRTC to wake up from the power off state when the INTR pin is activated by\nthe alarm clock.\n\nEnable the alarm and let to be used as a wakeup source.\n\nTested on a Buffalo LS421DE NAS.\n\nSigned-off-by: Daniel González Cabanelas <dgcbueu@gmail.com>\n---\n drivers/rtc/rtc-rs5c372.c | 16 ++++++++++++++++\n 1 file changed, 16 insertions(+)\n\n--- a/drivers/rtc/rtc-rs5c372.c\n+++ b/drivers/rtc/rtc-rs5c372.c\n@@ -654,6 +654,7 @@ static int rs5c372_probe(struct i2c_clie\n \tint err = 0;\n \tint smbus_mode = 0;\n \tstruct rs5c372 *rs5c372;\n+\tbool rs5c372_can_wakeup_device = false;\n \n \tdev_dbg(&client->dev, \"%s\\n\", __func__);\n \n@@ -689,6 +690,12 @@ static int rs5c372_probe(struct i2c_clie\n \telse\n \t\trs5c372->type = id->driver_data;\n \n+#ifdef CONFIG_OF\n+\tif(of_property_read_bool(client->dev.of_node,\n+\t\t\t\t\t      \"wakeup-source\"))\n+\t\trs5c372_can_wakeup_device = true;\n+#endif\n+\n \t/* we read registers 0x0f then 0x00-0x0f; skip the first one */\n \trs5c372->regs = &rs5c372->buf[1];\n \trs5c372->smbus = smbus_mode;\n@@ -722,6 +729,8 @@ static int rs5c372_probe(struct i2c_clie\n \t\tgoto exit;\n \t}\n \n+\trs5c372->has_irq = 1;\n+\n \t/* if the oscillator lost power and no other software (like\n \t * the bootloader) set it up, do it here.\n \t *\n@@ -748,6 +757,10 @@ static int rs5c372_probe(struct i2c_clie\n \t\t\t);\n \n \t/* REVISIT use client->irq to register alarm irq ... */\n+\tif (rs5c372_can_wakeup_device) {\n+\t\tdevice_init_wakeup(&client->dev, true);\n+\t}\n+\n \trs5c372->rtc = devm_rtc_device_register(&client->dev,\n \t\t\t\t\trs5c372_driver.driver.name,\n \t\t\t\t\t&rs5c372_rtc_ops, THIS_MODULE);\n@@ -761,6 +774,9 @@ static int rs5c372_probe(struct i2c_clie\n \tif (err)\n \t\tgoto exit;\n \n+\t/* the rs5c372 alarm only supports a minute accuracy */\n+\trs5c372->rtc->uie_unsupported = 1;\n+\n \treturn 0;\n \n exit:\n"
  },
  {
    "path": "target/linux/generic/pending-5.15/201-extra_optimization.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nSubject: Upgrade to Linux 2.6.19\n\n- Includes large parts of the patch from #1021 by dpalffy\n- Includes RB532 NAND driver changes by n0-1\n\n[john@phrozen.org: feix will add this to his upstream queue]\n\nlede-commit: bff468813f78f81e36ebb2a3f4354de7365e640f\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n Makefile | 6 +++---\n 1 file changed, 3 insertions(+), 3 deletions(-)\n\n--- a/Makefile\n+++ b/Makefile\n@@ -752,11 +752,11 @@ KBUILD_CFLAGS\t+= $(call cc-disable-warni\n KBUILD_CFLAGS\t+= $(call cc-disable-warning, address-of-packed-member)\n \n ifdef CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE\n-KBUILD_CFLAGS += -O2\n+KBUILD_CFLAGS += -O2 $(EXTRA_OPTIMIZATION)\n else ifdef CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE_O3\n-KBUILD_CFLAGS += -O3\n+KBUILD_CFLAGS += -O3 $(EXTRA_OPTIMIZATION)\n else ifdef CONFIG_CC_OPTIMIZE_FOR_SIZE\n-KBUILD_CFLAGS += -Os\n+KBUILD_CFLAGS += -Os -fno-reorder-blocks -fno-tree-ch $(EXTRA_OPTIMIZATION)\n endif\n \n # Tell gcc to never replace conditional load with a non-conditional one\n"
  },
  {
    "path": "target/linux/generic/pending-5.15/203-kallsyms_uncompressed.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nSubject: kernel: add a config option for keeping the kallsyms table uncompressed, saving ~9kb kernel size after lzma on ar71xx\n\n[john@phrozen.org: added to my upstream queue 30.12.2016]\nlede-commit: e0e3509b5ce2ccf93d4d67ea907613f5f7ec2eed\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n init/Kconfig            | 11 +++++++++++\n kernel/kallsyms.c       |  8 ++++++++\n scripts/kallsyms.c      | 12 ++++++++++++\n scripts/link-vmlinux.sh |  4 ++++\n 4 files changed, 35 insertions(+)\n\n--- a/init/Kconfig\n+++ b/init/Kconfig\n@@ -1438,6 +1438,17 @@ config SYSCTL_ARCH_UNALIGN_ALLOW\n \t  the unaligned access emulation.\n \t  see arch/parisc/kernel/unaligned.c for reference\n \n+config KALLSYMS_UNCOMPRESSED\n+\tbool \"Keep kallsyms uncompressed\"\n+\tdepends on KALLSYMS\n+\thelp\n+\t\tNormally kallsyms contains compressed symbols (using a token table),\n+\t\treducing the uncompressed kernel image size. Keeping the symbol table\n+\t\tuncompressed significantly improves the size of this part in compressed\n+\t\tkernel images.\n+\n+\t\tSay N unless you need compressed kernel images to be small.\n+\n config HAVE_PCSPKR_PLATFORM\n \tbool\n \n--- a/kernel/kallsyms.c\n+++ b/kernel/kallsyms.c\n@@ -80,6 +80,11 @@ static unsigned int kallsyms_expand_symb\n \t * For every byte on the compressed symbol data, copy the table\n \t * entry for that byte.\n \t */\n+#ifdef CONFIG_KALLSYMS_UNCOMPRESSED\n+\tmemcpy(result, data + 1, len - 1);\n+\tresult += len - 1;\n+\tlen = 0;\n+#endif\n \twhile (len) {\n \t\ttptr = &kallsyms_token_table[kallsyms_token_index[*data]];\n \t\tdata++;\n@@ -112,6 +117,9 @@ tail:\n  */\n static char kallsyms_get_symbol_type(unsigned int off)\n {\n+#ifdef CONFIG_KALLSYMS_UNCOMPRESSED\n+\treturn kallsyms_names[off + 1];\n+#endif\n \t/*\n \t * Get just the first code, look it up in the token table,\n \t * and return the first char from this token.\n--- a/scripts/kallsyms.c\n+++ b/scripts/kallsyms.c\n@@ -58,6 +58,7 @@ static struct addr_range percpu_range =\n static struct sym_entry **table;\n static unsigned int table_size, table_cnt;\n static int all_symbols;\n+static int uncompressed;\n static int absolute_percpu;\n static int base_relative;\n \n@@ -486,6 +487,9 @@ static void write_src(void)\n \n \tfree(markers);\n \n+\tif (uncompressed)\n+\t\treturn;\n+\n \toutput_label(\"kallsyms_token_table\");\n \toff = 0;\n \tfor (i = 0; i < 256; i++) {\n@@ -537,6 +541,9 @@ static unsigned char *find_token(unsigne\n {\n \tint i;\n \n+\tif (uncompressed)\n+\t\treturn NULL;\n+\n \tfor (i = 0; i < len - 1; i++) {\n \t\tif (str[i] == token[0] && str[i+1] == token[1])\n \t\t\treturn &str[i];\n@@ -609,6 +616,9 @@ static void optimize_result(void)\n {\n \tint i, best;\n \n+\tif (uncompressed)\n+\t\treturn;\n+\n \t/* using the '\\0' symbol last allows compress_symbols to use standard\n \t * fast string functions */\n \tfor (i = 255; i >= 0; i--) {\n@@ -773,6 +783,8 @@ int main(int argc, char **argv)\n \t\t\t\tabsolute_percpu = 1;\n \t\t\telse if (strcmp(argv[i], \"--base-relative\") == 0)\n \t\t\t\tbase_relative = 1;\n+\t\t\telse if (strcmp(argv[i], \"--uncompressed\") == 0)\n+\t\t\t\tuncompressed = 1;\n \t\t\telse\n \t\t\t\tusage();\n \t\t}\n--- a/scripts/link-vmlinux.sh\n+++ b/scripts/link-vmlinux.sh\n@@ -260,6 +260,10 @@ kallsyms()\n \t\tkallsymopt=\"${kallsymopt} --base-relative\"\n \tfi\n \n+\tif [ -n \"${CONFIG_KALLSYMS_UNCOMPRESSED}\" ]; then\n+\t\tkallsymopt=\"${kallsymopt} --uncompressed\"\n+\tfi\n+\n \tinfo KSYMS ${2}\n \t${NM} -n ${1} | scripts/kallsyms ${kallsymopt} > ${2}\n }\n"
  },
  {
    "path": "target/linux/generic/pending-5.15/205-backtrace_module_info.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nSubject: kernel: when KALLSYMS is disabled, print module address + size for matching backtrace entries\n\n[john@phrozen.org: felix will add this to his upstream queue]\n\nlede-commit 53827cdc824556cda910b23ce5030c363b8f1461\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n lib/vsprintf.c | 15 +++++++++++----\n 1 file changed, 11 insertions(+), 4 deletions(-)\n\n--- a/lib/vsprintf.c\n+++ b/lib/vsprintf.c\n@@ -1001,8 +1001,10 @@ char *symbol_string(char *buf, char *end\n \t\t    struct printf_spec spec, const char *fmt)\n {\n \tunsigned long value;\n-#ifdef CONFIG_KALLSYMS\n \tchar sym[KSYM_SYMBOL_LEN];\n+#ifndef CONFIG_KALLSYMS\n+\tstruct module *mod;\n+\tint len;\n #endif\n \n \tif (fmt[1] == 'R')\n@@ -1023,8 +1025,14 @@ char *symbol_string(char *buf, char *end\n \n \treturn string_nocheck(buf, end, sym, spec);\n #else\n-\treturn special_hex_number(buf, end, value, sizeof(void *));\n+\tlen = snprintf(sym, sizeof(sym), \"0x%lx\", value);\n+\tmod = __module_address(value);\n+\tif (mod)\n+\t\tsnprintf(sym + len, sizeof(sym) - len, \" [%s@%p+0x%x]\",\n+\t\t\t mod->name, mod->core_layout.base,\n+\t\t\t mod->core_layout.size);\n #endif\n+\treturn string(buf, end, sym, spec);\n }\n \n static const struct printf_spec default_str_spec = {\n"
  },
  {
    "path": "target/linux/generic/pending-5.15/240-remove-unsane-filenames-from-deps_initramfs-list.patch",
    "content": "From: Gabor Juhos <juhosg@openwrt.org>\nSubject: usr: sanitize deps_initramfs list\n\nIf any filename in the intramfs dependency\nlist contains a colon, that causes a kernel\nbuild error like this:\n\n/devel/openwrt/build_dir/linux-ar71xx_generic/linux-3.6.6/usr/Makefile:58: *** multiple target patterns.  Stop.\nmake[5]: *** [usr] Error 2\n\nFix it by removing such filenames from the\ndeps_initramfs list.\n\nSigned-off-by: Gabor Juhos <juhosg@openwrt.org>\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n usr/Makefile | 8 +++++---\n 1 file changed, 5 insertions(+), 3 deletions(-)\n\n--- a/usr/Makefile\n+++ b/usr/Makefile\n@@ -61,6 +61,8 @@ hostprogs := gen_init_cpio\n # The dependency list is generated by gen_initramfs.sh -l\n -include $(obj)/.initramfs_data.cpio.d\n \n+deps_initramfs := $(foreach v,$(deps_initramfs),$(if $(findstring :,$(v)),,$(v)))\n+\n # do not try to update files included in initramfs\n $(deps_initramfs): ;\n \n"
  },
  {
    "path": "target/linux/generic/pending-5.15/261-enable_wilink_platform_without_drivers.patch",
    "content": "From: Imre Kaloz <kaloz@openwrt.org>\nSubject: [PATCH] hack: net: wireless: make the wl12xx glue code available with\n compat-wireless, too\n\nSigned-off-by: Imre Kaloz <kaloz@openwrt.org>\n---\n drivers/net/wireless/ti/Kconfig | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/drivers/net/wireless/ti/Kconfig\n+++ b/drivers/net/wireless/ti/Kconfig\n@@ -20,7 +20,7 @@ source \"drivers/net/wireless/ti/wlcore/K\n \n config WILINK_PLATFORM_DATA\n \tbool \"TI WiLink platform data\"\n-\tdepends on WLCORE_SDIO || WL1251_SDIO\n+\tdepends on WLCORE_SDIO || WL1251_SDIO || ARCH_OMAP2PLUS\n \tdefault y\n \thelp\n \tSmall platform data bit needed to pass data to the sdio modules.\n"
  },
  {
    "path": "target/linux/generic/pending-5.15/270-platform-mikrotik-build-bits.patch",
    "content": "From c2deb5ef01a0ef09088832744cbace9e239a6ee0 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Thibaut=20VAR=C3=88NE?= <hacks@slashdirt.org>\nDate: Sat, 28 Mar 2020 12:11:50 +0100\nSubject: [PATCH] generic: platform/mikrotik build bits (5.4)\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nThis patch adds platform/mikrotik kernel build bits\n\nSigned-off-by: Thibaut VARÈNE <hacks@slashdirt.org>\n---\n drivers/platform/Kconfig  | 2 ++\n drivers/platform/Makefile | 1 +\n 2 files changed, 3 insertions(+)\n\n--- a/drivers/platform/Kconfig\n+++ b/drivers/platform/Kconfig\n@@ -15,3 +15,5 @@ source \"drivers/platform/mellanox/Kconfi\n source \"drivers/platform/olpc/Kconfig\"\n \n source \"drivers/platform/surface/Kconfig\"\n+\n+source \"drivers/platform/mikrotik/Kconfig\"\n--- a/drivers/platform/Makefile\n+++ b/drivers/platform/Makefile\n@@ -10,3 +10,4 @@ obj-$(CONFIG_OLPC_EC)\t\t+= olpc/\n obj-$(CONFIG_GOLDFISH)\t\t+= goldfish/\n obj-$(CONFIG_CHROME_PLATFORMS)\t+= chrome/\n obj-$(CONFIG_SURFACE_PLATFORMS)\t+= surface/\n+obj-$(CONFIG_MIKROTIK)\t\t+= mikrotik/\n"
  },
  {
    "path": "target/linux/generic/pending-5.15/300-mips_expose_boot_raw.patch",
    "content": "From: Mark Miller <mark@mirell.org>\nSubject: mips: expose CONFIG_BOOT_RAW\n\nThis exposes the CONFIG_BOOT_RAW symbol in Kconfig. This is needed on\ncertain Broadcom chipsets running CFE in order to load the kernel.\n\nSigned-off-by: Mark Miller <mark@mirell.org>\nAcked-by: Rob Landley <rob@landley.net>\n---\n--- a/arch/mips/Kconfig\n+++ b/arch/mips/Kconfig\n@@ -1100,9 +1100,6 @@ config FW_ARC\n config ARCH_MAY_HAVE_PC_FDC\n \tbool\n \n-config BOOT_RAW\n-\tbool\n-\n config CEVT_BCM1480\n \tbool\n \n@@ -3182,6 +3179,18 @@ choice\n \t\tbool \"Extend builtin kernel arguments with bootloader arguments\"\n endchoice\n \n+config BOOT_RAW\n+\tbool \"Enable the kernel to be executed from the load address\"\n+\tdefault n\n+\thelp\n+\t Allow the kernel to be executed from the load address for\n+\t bootloaders which cannot read the ELF format. This places\n+\t a jump to start_kernel at the load address.\n+\n+\t If unsure, say N.\n+\n+\n+\n endmenu\n \n config LOCKDEP_SUPPORT\n"
  },
  {
    "path": "target/linux/generic/pending-5.15/302-mips_no_branch_likely.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nSubject: mips: use -mno-branch-likely for kernel and userspace\n\nsaves ~11k kernel size after lzma and ~12k squashfs size in the\n\nlede-commit: 41a039f46450ffae9483d6216422098669da2900\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n arch/mips/Makefile | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/arch/mips/Makefile\n+++ b/arch/mips/Makefile\n@@ -95,7 +95,7 @@ all-$(CONFIG_SYS_SUPPORTS_ZBOOT)+= vmlin\n # machines may also.  Since BFD is incredibly buggy with respect to\n # crossformat linking we rely on the elf2ecoff tool for format conversion.\n #\n-cflags-y\t\t\t+= -G 0 -mno-abicalls -fno-pic -pipe\n+cflags-y\t\t\t+= -G 0 -mno-abicalls -fno-pic -pipe -mno-branch-likely\n cflags-y\t\t\t+= -msoft-float\n LDFLAGS_vmlinux\t\t\t+= -G 0 -static -n -nostdlib\n KBUILD_AFLAGS_MODULE\t\t+= -mlong-calls\n"
  },
  {
    "path": "target/linux/generic/pending-5.15/305-mips_module_reloc.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nSubject: mips: replace -mlong-calls with -mno-long-calls to make function calls faster in kernel modules to achieve this, try to\n\nlede-commit: 3b3d64743ba2a874df9d70cd19e242205b0a788c\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n arch/mips/Makefile             |   5 +\n arch/mips/include/asm/module.h |   5 +\n arch/mips/kernel/module.c      | 279 ++++++++++++++++++++++++++++++++++++++++-\n 3 files changed, 284 insertions(+), 5 deletions(-)\n\n--- a/arch/mips/Makefile\n+++ b/arch/mips/Makefile\n@@ -98,8 +98,18 @@ all-$(CONFIG_SYS_SUPPORTS_ZBOOT)+= vmlin\n cflags-y\t\t\t+= -G 0 -mno-abicalls -fno-pic -pipe -mno-branch-likely\n cflags-y\t\t\t+= -msoft-float\n LDFLAGS_vmlinux\t\t\t+= -G 0 -static -n -nostdlib\n+ifdef CONFIG_64BIT\n KBUILD_AFLAGS_MODULE\t\t+= -mlong-calls\n KBUILD_CFLAGS_MODULE\t\t+= -mlong-calls\n+else\n+  ifdef CONFIG_DYNAMIC_FTRACE\n+    KBUILD_AFLAGS_MODULE\t+= -mlong-calls\n+    KBUILD_CFLAGS_MODULE\t+= -mlong-calls\n+  else\n+    KBUILD_AFLAGS_MODULE\t+= -mno-long-calls\n+    KBUILD_CFLAGS_MODULE\t+= -mno-long-calls\n+  endif\n+endif\n \n ifeq ($(CONFIG_RELOCATABLE),y)\n LDFLAGS_vmlinux\t\t\t+= --emit-relocs\n--- a/arch/mips/include/asm/module.h\n+++ b/arch/mips/include/asm/module.h\n@@ -12,6 +12,11 @@ struct mod_arch_specific {\n \tconst struct exception_table_entry *dbe_start;\n \tconst struct exception_table_entry *dbe_end;\n \tstruct mips_hi16 *r_mips_hi16_list;\n+\n+\tvoid *phys_plt_tbl;\n+\tvoid *virt_plt_tbl;\n+\tunsigned int phys_plt_offset;\n+\tunsigned int virt_plt_offset;\n };\n \n typedef uint8_t Elf64_Byte;\t\t/* Type for a 8-bit quantity.  */\n--- a/arch/mips/kernel/module.c\n+++ b/arch/mips/kernel/module.c\n@@ -31,23 +31,261 @@ struct mips_hi16 {\n static LIST_HEAD(dbe_list);\n static DEFINE_SPINLOCK(dbe_lock);\n \n-#ifdef MODULE_START\n+/*\n+ * Get the potential max trampolines size required of the init and\n+ * non-init sections. Only used if we cannot find enough contiguous\n+ * physically mapped memory to put the module into.\n+ */\n+static unsigned int\n+get_plt_size(const Elf_Ehdr *hdr, const Elf_Shdr *sechdrs,\n+             const char *secstrings, unsigned int symindex, bool is_init)\n+{\n+\tunsigned long ret = 0;\n+\tunsigned int i, j;\n+\tElf_Sym *syms;\n+\n+\t/* Everything marked ALLOC (this includes the exported symbols) */\n+\tfor (i = 1; i < hdr->e_shnum; ++i) {\n+\t\tunsigned int info = sechdrs[i].sh_info;\n+\n+\t\tif (sechdrs[i].sh_type != SHT_REL\n+\t\t    && sechdrs[i].sh_type != SHT_RELA)\n+\t\t\tcontinue;\n+\n+\t\t/* Not a valid relocation section? */\n+\t\tif (info >= hdr->e_shnum)\n+\t\t\tcontinue;\n+\n+\t\t/* Don't bother with non-allocated sections */\n+\t\tif (!(sechdrs[info].sh_flags & SHF_ALLOC))\n+\t\t\tcontinue;\n+\n+\t\t/* If it's called *.init*, and we're not init, we're\n+                   not interested */\n+\t\tif ((strstr(secstrings + sechdrs[i].sh_name, \".init\") != 0)\n+\t\t    != is_init)\n+\t\t\tcontinue;\n+\n+\t\tsyms = (Elf_Sym *) sechdrs[symindex].sh_addr;\n+\t\tif (sechdrs[i].sh_type == SHT_REL) {\n+\t\t\tElf_Mips_Rel *rel = (void *) sechdrs[i].sh_addr;\n+\t\t\tunsigned int size = sechdrs[i].sh_size / sizeof(*rel);\n+\n+\t\t\tfor (j = 0; j < size; ++j) {\n+\t\t\t\tElf_Sym *sym;\n+\n+\t\t\t\tif (ELF_MIPS_R_TYPE(rel[j]) != R_MIPS_26)\n+\t\t\t\t\tcontinue;\n+\n+\t\t\t\tsym = syms + ELF_MIPS_R_SYM(rel[j]);\n+\t\t\t\tif (!is_init && sym->st_shndx != SHN_UNDEF)\n+\t\t\t\t\tcontinue;\n+\n+\t\t\t\tret += 4 * sizeof(int);\n+\t\t\t}\n+\t\t} else {\n+\t\t\tElf_Mips_Rela *rela = (void *) sechdrs[i].sh_addr;\n+\t\t\tunsigned int size = sechdrs[i].sh_size / sizeof(*rela);\n+\n+\t\t\tfor (j = 0; j < size; ++j) {\n+\t\t\t\tElf_Sym *sym;\n+\n+\t\t\t\tif (ELF_MIPS_R_TYPE(rela[j]) != R_MIPS_26)\n+\t\t\t\t\tcontinue;\n+\n+\t\t\t\tsym = syms + ELF_MIPS_R_SYM(rela[j]);\n+\t\t\t\tif (!is_init && sym->st_shndx != SHN_UNDEF)\n+\t\t\t\t\tcontinue;\n+\n+\t\t\t\tret += 4 * sizeof(int);\n+\t\t\t}\n+\t\t}\n+\t}\n+\n+\treturn ret;\n+}\n+\n+#ifndef MODULE_START\n+static void *alloc_phys(unsigned long size)\n+{\n+\tunsigned order;\n+\tstruct page *page;\n+\tstruct page *p;\n+\n+\tsize = PAGE_ALIGN(size);\n+\torder = get_order(size);\n+\n+\tpage = alloc_pages(GFP_KERNEL | __GFP_NORETRY | __GFP_NOWARN |\n+\t\t\t__GFP_THISNODE, order);\n+\tif (!page)\n+\t\treturn NULL;\n+\n+\tsplit_page(page, order);\n+\n+\t/* mark all pages except for the last one */\n+\tfor (p = page; p + 1 < page + (size >> PAGE_SHIFT); ++p)\n+\t\tset_bit(PG_owner_priv_1, &p->flags);\n+\n+\tfor (p = page + (size >> PAGE_SHIFT); p < page + (1 << order); ++p)\n+\t\t__free_page(p);\n+\n+\treturn page_address(page);\n+}\n+#endif\n+\n+static void free_phys(void *ptr)\n+{\n+\tstruct page *page;\n+\tbool free;\n+\n+\tpage = virt_to_page(ptr);\n+\tdo {\n+\t\tfree = test_and_clear_bit(PG_owner_priv_1, &page->flags);\n+\t\t__free_page(page);\n+\t\tpage++;\n+\t} while (free);\n+}\n+\n+\n void *module_alloc(unsigned long size)\n {\n+#ifdef MODULE_START\n \treturn __vmalloc_node_range(size, 1, MODULE_START, MODULE_END,\n \t\t\t\tGFP_KERNEL, PAGE_KERNEL, 0, NUMA_NO_NODE,\n \t\t\t\t__builtin_return_address(0));\n+#else\n+\tvoid *ptr;\n+\n+\tif (size == 0)\n+\t\treturn NULL;\n+\n+\tptr = alloc_phys(size);\n+\n+\t/* If we failed to allocate physically contiguous memory,\n+\t * fall back to regular vmalloc. The module loader code will\n+\t * create jump tables to handle long jumps */\n+\tif (!ptr)\n+\t\treturn vmalloc(size);\n+\n+\treturn ptr;\n+#endif\n }\n+\n+static inline bool is_phys_addr(void *ptr)\n+{\n+#ifdef CONFIG_64BIT\n+\treturn (KSEGX((unsigned long)ptr) == CKSEG0);\n+#else\n+\treturn (KSEGX(ptr) == KSEG0);\n #endif\n+}\n+\n+/* Free memory returned from module_alloc */\n+void module_memfree(void *module_region)\n+{\n+\tif (is_phys_addr(module_region))\n+\t\tfree_phys(module_region);\n+\telse\n+\t\tvfree(module_region);\n+}\n+\n+static void *__module_alloc(int size, bool phys)\n+{\n+\tvoid *ptr;\n+\n+\tif (phys)\n+\t\tptr = kmalloc(size, GFP_KERNEL);\n+\telse\n+\t\tptr = vmalloc(size);\n+\treturn ptr;\n+}\n+\n+static void __module_free(void *ptr)\n+{\n+\tif (is_phys_addr(ptr))\n+\t\tkfree(ptr);\n+\telse\n+\t\tvfree(ptr);\n+}\n+\n+int module_frob_arch_sections(Elf_Ehdr *hdr, Elf_Shdr *sechdrs,\n+\t\t\t      char *secstrings, struct module *mod)\n+{\n+\tunsigned int symindex = 0;\n+\tunsigned int core_size, init_size;\n+\tint i;\n+\n+\tmod->arch.phys_plt_offset = 0;\n+\tmod->arch.virt_plt_offset = 0;\n+\tmod->arch.phys_plt_tbl = NULL;\n+\tmod->arch.virt_plt_tbl = NULL;\n+\n+\tif (IS_ENABLED(CONFIG_64BIT))\n+\t\treturn 0;\n+\n+\tfor (i = 1; i < hdr->e_shnum; i++)\n+\t\tif (sechdrs[i].sh_type == SHT_SYMTAB)\n+\t\t\tsymindex = i;\n+\n+\tcore_size = get_plt_size(hdr, sechdrs, secstrings, symindex, false);\n+\tinit_size = get_plt_size(hdr, sechdrs, secstrings, symindex, true);\n+\n+\tif ((core_size + init_size) == 0)\n+\t\treturn 0;\n+\n+\tmod->arch.phys_plt_tbl = __module_alloc(core_size + init_size, 1);\n+\tif (!mod->arch.phys_plt_tbl)\n+\t\treturn -ENOMEM;\n+\n+\tmod->arch.virt_plt_tbl = __module_alloc(core_size + init_size, 0);\n+\tif (!mod->arch.virt_plt_tbl) {\n+\t\t__module_free(mod->arch.phys_plt_tbl);\n+\t\tmod->arch.phys_plt_tbl = NULL;\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\treturn 0;\n+}\n \n static void apply_r_mips_32(u32 *location, u32 base, Elf_Addr v)\n {\n \t*location = base + v;\n }\n \n+static Elf_Addr add_plt_entry_to(unsigned *plt_offset,\n+\t\t\t\t void *start, Elf_Addr v)\n+{\n+\tunsigned *tramp = start + *plt_offset;\n+\t*plt_offset += 4 * sizeof(int);\n+\n+\t/* adjust carry for addiu */\n+\tif (v & 0x00008000)\n+\t\tv += 0x10000;\n+\n+\ttramp[0] = 0x3c190000 | (v >> 16);      /* lui t9, hi16 */\n+\ttramp[1] = 0x27390000 | (v & 0xffff);   /* addiu t9, t9, lo16 */\n+\ttramp[2] = 0x03200008;                  /* jr t9 */\n+\ttramp[3] = 0x00000000;                  /* nop */\n+\n+\treturn (Elf_Addr) tramp;\n+}\n+\n+static Elf_Addr add_plt_entry(struct module *me, void *location, Elf_Addr v)\n+{\n+\tif (is_phys_addr(location))\n+\t\treturn add_plt_entry_to(&me->arch.phys_plt_offset,\n+\t\t\t\tme->arch.phys_plt_tbl, v);\n+\telse\n+\t\treturn add_plt_entry_to(&me->arch.virt_plt_offset,\n+\t\t\t\tme->arch.virt_plt_tbl, v);\n+\n+}\n+\n static int apply_r_mips_26(struct module *me, u32 *location, u32 base,\n \t\t\t   Elf_Addr v)\n {\n+\tu32 ofs = base & 0x03ffffff;\n+\n \tif (v % 4) {\n \t\tpr_err(\"module %s: dangerous R_MIPS_26 relocation\\n\",\n \t\t       me->name);\n@@ -55,13 +293,17 @@ static int apply_r_mips_26(struct module\n \t}\n \n \tif ((v & 0xf0000000) != (((unsigned long)location + 4) & 0xf0000000)) {\n-\t\tpr_err(\"module %s: relocation overflow\\n\",\n-\t\t       me->name);\n-\t\treturn -ENOEXEC;\n+\t\tv = add_plt_entry(me, location, v + (ofs << 2));\n+\t\tif (!v) {\n+\t\t\tpr_err(\"module %s: relocation overflow\\n\",\n+\t\t\t       me->name);\n+\t\t\treturn -ENOEXEC;\n+\t\t}\n+\t\tofs = 0;\n \t}\n \n \t*location = (*location & ~0x03ffffff) |\n-\t\t    ((base + (v >> 2)) & 0x03ffffff);\n+\t\t    ((ofs + (v >> 2)) & 0x03ffffff);\n \n \treturn 0;\n }\n@@ -441,9 +683,36 @@ int module_finalize(const Elf_Ehdr *hdr,\n \t\tlist_add(&me->arch.dbe_list, &dbe_list);\n \t\tspin_unlock_irq(&dbe_lock);\n \t}\n+\n+\t/* Get rid of the fixup trampoline if we're running the module\n+\t * from physically mapped address space */\n+\tif (me->arch.phys_plt_offset == 0) {\n+\t\t__module_free(me->arch.phys_plt_tbl);\n+\t\tme->arch.phys_plt_tbl = NULL;\n+\t}\n+\tif (me->arch.virt_plt_offset == 0) {\n+\t\t__module_free(me->arch.virt_plt_tbl);\n+\t\tme->arch.virt_plt_tbl = NULL;\n+\t}\n+\n \treturn 0;\n }\n \n+void module_arch_freeing_init(struct module *mod)\n+{\n+\tif (mod->state == MODULE_STATE_LIVE)\n+\t\treturn;\n+\n+\tif (mod->arch.phys_plt_tbl) {\n+\t\t__module_free(mod->arch.phys_plt_tbl);\n+\t\tmod->arch.phys_plt_tbl = NULL;\n+\t}\n+\tif (mod->arch.virt_plt_tbl) {\n+\t\t__module_free(mod->arch.virt_plt_tbl);\n+\t\tmod->arch.virt_plt_tbl = NULL;\n+\t}\n+}\n+\n void module_arch_cleanup(struct module *mod)\n {\n \tspin_lock_irq(&dbe_lock);\n"
  },
  {
    "path": "target/linux/generic/pending-5.15/307-mips_highmem_offset.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nSubject: kernel: adjust mips highmem offset to avoid the need for -mlong-calls on systems with >256M RAM\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n arch/mips/include/asm/mach-generic/spaces.h | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/arch/mips/include/asm/mach-generic/spaces.h\n+++ b/arch/mips/include/asm/mach-generic/spaces.h\n@@ -46,7 +46,7 @@\n  * Memory above this physical address will be considered highmem.\n  */\n #ifndef HIGHMEM_START\n-#define HIGHMEM_START\t\t_AC(0x20000000, UL)\n+#define HIGHMEM_START\t\t_AC(0x10000000, UL)\n #endif\n \n #endif /* CONFIG_32BIT */\n"
  },
  {
    "path": "target/linux/generic/pending-5.15/308-mips32r2_tune.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nSubject: kernel: add -mtune=34kc to MIPS CFLAGS when building for mips32r2\n\nThis provides a good tradeoff across at least 24Kc-74Kc, while also\nproducing smaller code.\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n arch/mips/Makefile | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/arch/mips/Makefile\n+++ b/arch/mips/Makefile\n@@ -175,7 +175,7 @@ cflags-$(CONFIG_CPU_VR41XX)\t+= -march=r4\n cflags-$(CONFIG_CPU_R4X00)\t+= -march=r4600 -Wa,--trap\n cflags-$(CONFIG_CPU_TX49XX)\t+= -march=r4600 -Wa,--trap\n cflags-$(CONFIG_CPU_MIPS32_R1)\t+= -march=mips32 -Wa,--trap\n-cflags-$(CONFIG_CPU_MIPS32_R2)\t+= -march=mips32r2 -Wa,--trap\n+cflags-$(CONFIG_CPU_MIPS32_R2)\t+= -march=mips32r2 -mtune=34kc -Wa,--trap\n cflags-$(CONFIG_CPU_MIPS32_R5)\t+= -march=mips32r5 -Wa,--trap -modd-spreg\n cflags-$(CONFIG_CPU_MIPS32_R6)\t+= -march=mips32r6 -Wa,--trap -modd-spreg\n cflags-$(CONFIG_CPU_MIPS64_R1)\t+= -march=mips64 -Wa,--trap\n"
  },
  {
    "path": "target/linux/generic/pending-5.15/309-MIPS-Add-CPU-option-reporting-to-proc-cpuinfo.patch",
    "content": "From 87ec87c2ad615c1a177cd08ef5fa29fc739f6e50 Mon Sep 17 00:00:00 2001\nFrom: Hauke Mehrtens <hauke@hauke-m.de>\nDate: Sun, 23 Dec 2018 18:06:53 +0100\nSubject: [PATCH] MIPS: Add CPU option reporting to /proc/cpuinfo\n\nMany MIPS CPUs have optional CPU features which are not activates for\nall CPU cores. Print the CPU options which are implemented in the core\nin /proc/cpuinfo. This makes it possible to see what features are\nsupported and which are not supported. This should cover all standard\nMIPS extensions, before it only printed information about the main MIPS\nASEs.\n\nSigned-off-by: Hauke Mehrtens <hauke@hauke-m.de>\n---\n arch/mips/kernel/proc.c | 116 ++++++++++++++++++++++++++++++++++++++++\n 1 file changed, 116 insertions(+)\n\n--- a/arch/mips/kernel/proc.c\n+++ b/arch/mips/kernel/proc.c\n@@ -138,6 +138,116 @@ static int show_cpuinfo(struct seq_file\n \t\tseq_printf(m, \"micromips kernel\\t: %s\\n\",\n \t\t      (read_c0_config3() & MIPS_CONF3_ISA_OE) ?  \"yes\" : \"no\");\n \t}\n+\n+\tseq_printf(m, \"Options implemented\\t:\");\n+\tif (cpu_has_tlb)\n+\t\tseq_printf(m, \"%s\", \" tlb\");\n+\tif (cpu_has_ftlb)\n+\t\tseq_printf(m, \"%s\", \" ftlb\");\n+\tif (cpu_has_tlbinv)\n+\t\tseq_printf(m, \"%s\", \" tlbinv\");\n+\tif (cpu_has_segments)\n+\t\tseq_printf(m, \"%s\", \" segments\");\n+\tif (cpu_has_rixiex)\n+\t\tseq_printf(m, \"%s\", \" rixiex\");\n+\tif (cpu_has_ldpte)\n+\t\tseq_printf(m, \"%s\", \" ldpte\");\n+\tif (cpu_has_maar)\n+\t\tseq_printf(m, \"%s\", \" maar\");\n+\tif (cpu_has_rw_llb)\n+\t\tseq_printf(m, \"%s\", \" rw_llb\");\n+\tif (cpu_has_4kex)\n+\t\tseq_printf(m, \"%s\", \" 4kex\");\n+\tif (cpu_has_3k_cache)\n+\t\tseq_printf(m, \"%s\", \" 3k_cache\");\n+\tif (cpu_has_4k_cache)\n+\t\tseq_printf(m, \"%s\", \" 4k_cache\");\n+\tif (cpu_has_tx39_cache)\n+\t\tseq_printf(m, \"%s\", \" tx39_cache\");\n+\tif (cpu_has_octeon_cache)\n+\t\tseq_printf(m, \"%s\", \" octeon_cache\");\n+\tif (cpu_has_fpu)\n+\t\tseq_printf(m, \"%s\", \" fpu\");\n+\tif (cpu_has_32fpr)\n+\t\tseq_printf(m, \"%s\", \" 32fpr\");\n+\tif (cpu_has_cache_cdex_p)\n+\t\tseq_printf(m, \"%s\", \" cache_cdex_p\");\n+\tif (cpu_has_cache_cdex_s)\n+\t\tseq_printf(m, \"%s\", \" cache_cdex_s\");\n+\tif (cpu_has_prefetch)\n+\t\tseq_printf(m, \"%s\", \" prefetch\");\n+\tif (cpu_has_mcheck)\n+\t\tseq_printf(m, \"%s\", \" mcheck\");\n+\tif (cpu_has_ejtag)\n+\t\tseq_printf(m, \"%s\", \" ejtag\");\n+\tif (cpu_has_llsc)\n+\t\tseq_printf(m, \"%s\", \" llsc\");\n+\tif (cpu_has_guestctl0ext)\n+\t\tseq_printf(m, \"%s\", \" guestctl0ext\");\n+\tif (cpu_has_guestctl1)\n+\t\tseq_printf(m, \"%s\", \" guestctl1\");\n+\tif (cpu_has_guestctl2)\n+\t\tseq_printf(m, \"%s\", \" guestctl2\");\n+\tif (cpu_has_guestid)\n+\t\tseq_printf(m, \"%s\", \" guestid\");\n+\tif (cpu_has_drg)\n+\t\tseq_printf(m, \"%s\", \" drg\");\n+\tif (cpu_has_rixi)\n+\t\tseq_printf(m, \"%s\", \" rixi\");\n+\tif (cpu_has_lpa)\n+\t\tseq_printf(m, \"%s\", \" lpa\");\n+\tif (cpu_has_mvh)\n+\t\tseq_printf(m, \"%s\", \" mvh\");\n+\tif (cpu_has_vtag_icache)\n+\t\tseq_printf(m, \"%s\", \" vtag_icache\");\n+\tif (cpu_has_dc_aliases)\n+\t\tseq_printf(m, \"%s\", \" dc_aliases\");\n+\tif (cpu_has_ic_fills_f_dc)\n+\t\tseq_printf(m, \"%s\", \" ic_fills_f_dc\");\n+\tif (cpu_has_pindexed_dcache)\n+\t\tseq_printf(m, \"%s\", \" pindexed_dcache\");\n+\tif (cpu_has_userlocal)\n+\t\tseq_printf(m, \"%s\", \" userlocal\");\n+\tif (cpu_has_nofpuex)\n+\t\tseq_printf(m, \"%s\", \" nofpuex\");\n+\tif (cpu_has_vint)\n+\t\tseq_printf(m, \"%s\", \" vint\");\n+\tif (cpu_has_veic)\n+\t\tseq_printf(m, \"%s\", \" veic\");\n+\tif (cpu_has_inclusive_pcaches)\n+\t\tseq_printf(m, \"%s\", \" inclusive_pcaches\");\n+\tif (cpu_has_perf_cntr_intr_bit)\n+\t\tseq_printf(m, \"%s\", \" perf_cntr_intr_bit\");\n+\tif (cpu_has_ufr)\n+\t\tseq_printf(m, \"%s\", \" ufr\");\n+\tif (cpu_has_fre)\n+\t\tseq_printf(m, \"%s\", \" fre\");\n+\tif (cpu_has_cdmm)\n+\t\tseq_printf(m, \"%s\", \" cdmm\");\n+\tif (cpu_has_small_pages)\n+\t\tseq_printf(m, \"%s\", \" small_pages\");\n+\tif (cpu_has_nan_legacy)\n+\t\tseq_printf(m, \"%s\", \" nan_legacy\");\n+\tif (cpu_has_nan_2008)\n+\t\tseq_printf(m, \"%s\", \" nan_2008\");\n+\tif (cpu_has_ebase_wg)\n+\t\tseq_printf(m, \"%s\", \" ebase_wg\");\n+\tif (cpu_has_badinstr)\n+\t\tseq_printf(m, \"%s\", \" badinstr\");\n+\tif (cpu_has_badinstrp)\n+\t\tseq_printf(m, \"%s\", \" badinstrp\");\n+\tif (cpu_has_contextconfig)\n+\t\tseq_printf(m, \"%s\", \" contextconfig\");\n+\tif (cpu_has_perf)\n+\t\tseq_printf(m, \"%s\", \" perf\");\n+\tif (cpu_has_shared_ftlb_ram)\n+\t\tseq_printf(m, \"%s\", \" shared_ftlb_ram\");\n+\tif (cpu_has_shared_ftlb_entries)\n+\t\tseq_printf(m, \"%s\", \" shared_ftlb_entries\");\n+\tif (cpu_has_mipsmt_pertccounters)\n+\t\tseq_printf(m, \"%s\", \" mipsmt_pertccounters\");\n+\tseq_printf(m, \"\\n\");\n+\n \tseq_printf(m, \"shadow register sets\\t: %d\\n\",\n \t\t      cpu_data[n].srsets);\n \tseq_printf(m, \"kscratch registers\\t: %d\\n\",\n"
  },
  {
    "path": "target/linux/generic/pending-5.15/310-arm_module_unresolved_weak_sym.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nSubject: fix errors in unresolved weak symbols on arm\n\nlede-commit: 570699d4838a907c3ef9f2819bf19eb72997b32f\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n arch/arm/kernel/module.c | 4 ++++\n 1 file changed, 4 insertions(+)\n\n--- a/arch/arm/kernel/module.c\n+++ b/arch/arm/kernel/module.c\n@@ -105,6 +105,10 @@ apply_relocate(Elf32_Shdr *sechdrs, cons\n \t\t\treturn -ENOEXEC;\n \t\t}\n \n+\t\tif ((IS_ERR_VALUE(sym->st_value) || !sym->st_value) &&\n+\t\t    ELF_ST_BIND(sym->st_info) == STB_WEAK)\n+\t\t\tcontinue;\n+\n \t\tloc = dstsec->sh_addr + rel->r_offset;\n \n \t\tswitch (ELF32_R_TYPE(rel->r_info)) {\n"
  },
  {
    "path": "target/linux/generic/pending-5.15/330-MIPS-kexec-Accept-command-line-parameters-from-users.patch",
    "content": "From: Yousong Zhou <yszhou4tech@gmail.com>\nSubject: MIPS: kexec: Accept command line parameters from userspace.\n\nSigned-off-by: Yousong Zhou <yszhou4tech@gmail.com>\n---\n arch/mips/kernel/machine_kexec.c   |  153 +++++++++++++++++++++++++++++++-----\n arch/mips/kernel/machine_kexec.h   |   20 +++++\n arch/mips/kernel/relocate_kernel.S |   21 +++--\n 3 files changed, 167 insertions(+), 27 deletions(-)\n create mode 100644 arch/mips/kernel/machine_kexec.h\n\n--- a/arch/mips/kernel/machine_kexec.c\n+++ b/arch/mips/kernel/machine_kexec.c\n@@ -9,14 +9,11 @@\n #include <linux/delay.h>\n #include <linux/libfdt.h>\n \n+#include <asm/bootinfo.h>\n #include <asm/cacheflush.h>\n #include <asm/page.h>\n-\n-extern const unsigned char relocate_new_kernel[];\n-extern const size_t relocate_new_kernel_size;\n-\n-extern unsigned long kexec_start_address;\n-extern unsigned long kexec_indirection_page;\n+#include <linux/uaccess.h>\n+#include \"machine_kexec.h\"\n \n static unsigned long reboot_code_buffer;\n \n@@ -30,6 +27,101 @@ void (*_crash_smp_send_stop)(void) = NUL\n void (*_machine_kexec_shutdown)(void) = NULL;\n void (*_machine_crash_shutdown)(struct pt_regs *regs) = NULL;\n \n+static void machine_kexec_print_args(void)\n+{\n+\tunsigned long argc = (int)kexec_args[0];\n+\tint i;\n+\n+\tpr_info(\"kexec_args[0] (argc): %lu\\n\", argc);\n+\tpr_info(\"kexec_args[1] (argv): %p\\n\", (void *)kexec_args[1]);\n+\tpr_info(\"kexec_args[2] (env ): %p\\n\", (void *)kexec_args[2]);\n+\tpr_info(\"kexec_args[3] (desc): %p\\n\", (void *)kexec_args[3]);\n+\n+\tfor (i = 0; i < argc; i++) {\n+\t\tpr_info(\"kexec_argv[%d] = %p, %s\\n\",\n+\t\t\t\ti, kexec_argv[i], kexec_argv[i]);\n+\t}\n+}\n+\n+static void machine_kexec_init_argv(struct kimage *image)\n+{\n+\tvoid __user *buf = NULL;\n+\tsize_t bufsz;\n+\tsize_t size;\n+\tint i;\n+\n+\tbufsz = 0;\n+\tfor (i = 0; i < image->nr_segments; i++) {\n+\t\tstruct kexec_segment *seg;\n+\n+\t\tseg = &image->segment[i];\n+\t\tif (seg->bufsz < 6)\n+\t\t\tcontinue;\n+\n+\t\tif (strncmp((char *) seg->buf, \"kexec \", 6))\n+\t\t\tcontinue;\n+\n+\t\tbuf = seg->buf;\n+\t\tbufsz = seg->bufsz;\n+\t\tbreak;\n+\t}\n+\n+\tif (!buf)\n+\t\treturn;\n+\n+\tsize = KEXEC_COMMAND_LINE_SIZE;\n+\tsize = min(size, bufsz);\n+\tif (size < bufsz)\n+\t\tpr_warn(\"kexec command line truncated to %zd bytes\\n\", size);\n+\n+\t/* Copy to kernel space */\n+\tif (copy_from_user(kexec_argv_buf, buf, size))\n+\t\tpr_warn(\"kexec command line copy to kernel space failed\\n\");\n+\n+\tkexec_argv_buf[size - 1] = 0;\n+}\n+\n+static void machine_kexec_parse_argv(struct kimage *image)\n+{\n+\tchar *reboot_code_buffer;\n+\tint reloc_delta;\n+\tchar *ptr;\n+\tint argc;\n+\tint i;\n+\n+\tptr = kexec_argv_buf;\n+\targc = 0;\n+\n+\t/*\n+\t * convert command line string to array of parameters\n+\t * (as bootloader does).\n+\t */\n+\twhile (ptr && *ptr && (KEXEC_MAX_ARGC > argc)) {\n+\t\tif (*ptr == ' ') {\n+\t\t\t*ptr++ = '\\0';\n+\t\t\tcontinue;\n+\t\t}\n+\n+\t\tkexec_argv[argc++] = ptr;\n+\t\tptr = strchr(ptr, ' ');\n+\t}\n+\n+\tif (!argc)\n+\t\treturn;\n+\n+\tkexec_args[0] = argc;\n+\tkexec_args[1] = (unsigned long)kexec_argv;\n+\tkexec_args[2] = 0;\n+\tkexec_args[3] = 0;\n+\n+\treboot_code_buffer = page_address(image->control_code_page);\n+\treloc_delta = reboot_code_buffer - (char *)kexec_relocate_new_kernel;\n+\n+\tkexec_args[1] += reloc_delta;\n+\tfor (i = 0; i < argc; i++)\n+\t\tkexec_argv[i] += reloc_delta;\n+}\n+\n static void kexec_image_info(const struct kimage *kimage)\n {\n \tunsigned long i;\n@@ -99,6 +191,18 @@ machine_kexec_prepare(struct kimage *kim\n #endif\n \n \tkexec_image_info(kimage);\n+\t/*\n+\t * Whenever arguments passed from kexec-tools, Init the arguments as\n+\t * the original ones to try avoiding booting failure.\n+\t */\n+\n+\tkexec_args[0] = fw_arg0;\n+\tkexec_args[1] = fw_arg1;\n+\tkexec_args[2] = fw_arg2;\n+\tkexec_args[3] = fw_arg3;\n+\n+\tmachine_kexec_init_argv(kimage);\n+\tmachine_kexec_parse_argv(kimage);\n \n \tif (_machine_kexec_prepare)\n \t\treturn _machine_kexec_prepare(kimage);\n@@ -161,7 +265,7 @@ machine_crash_shutdown(struct pt_regs *r\n void kexec_nonboot_cpu_jump(void)\n {\n \tlocal_flush_icache_range((unsigned long)relocated_kexec_smp_wait,\n-\t\t\t\t reboot_code_buffer + relocate_new_kernel_size);\n+\t\t\t\t reboot_code_buffer + KEXEC_RELOCATE_NEW_KERNEL_SIZE);\n \n \trelocated_kexec_smp_wait(NULL);\n }\n@@ -199,7 +303,7 @@ void kexec_reboot(void)\n \t * machine_kexec() CPU.\n \t */\n \tlocal_flush_icache_range(reboot_code_buffer,\n-\t\t\t\t reboot_code_buffer + relocate_new_kernel_size);\n+\t\t\t\t reboot_code_buffer + KEXEC_RELOCATE_NEW_KERNEL_SIZE);\n \n \tdo_kexec = (void *)reboot_code_buffer;\n \tdo_kexec();\n@@ -212,10 +316,12 @@ machine_kexec(struct kimage *image)\n \tunsigned long *ptr;\n \n \treboot_code_buffer =\n-\t  (unsigned long)page_address(image->control_code_page);\n+\t\t(unsigned long)page_address(image->control_code_page);\n+\tpr_info(\"reboot_code_buffer = %p\\n\", (void *)reboot_code_buffer);\n \n \tkexec_start_address =\n \t\t(unsigned long) phys_to_virt(image->start);\n+\tpr_info(\"kexec_start_address = %p\\n\", (void *)kexec_start_address);\n \n \tif (image->type == KEXEC_TYPE_DEFAULT) {\n \t\tkexec_indirection_page =\n@@ -223,9 +329,19 @@ machine_kexec(struct kimage *image)\n \t} else {\n \t\tkexec_indirection_page = (unsigned long)&image->head;\n \t}\n+\tpr_info(\"kexec_indirection_page = %p\\n\", (void *)kexec_indirection_page);\n \n-\tmemcpy((void*)reboot_code_buffer, relocate_new_kernel,\n-\t       relocate_new_kernel_size);\n+\tpr_info(\"Where is memcpy: %p\\n\", memcpy);\n+\tpr_info(\"kexec_relocate_new_kernel = %p, kexec_relocate_new_kernel_end = %p\\n\",\n+\t\t(void *)kexec_relocate_new_kernel, &kexec_relocate_new_kernel_end);\n+\tpr_info(\"Copy %lu bytes from %p to %p\\n\", KEXEC_RELOCATE_NEW_KERNEL_SIZE,\n+\t\t(void *)kexec_relocate_new_kernel, (void *)reboot_code_buffer);\n+\tmemcpy((void*)reboot_code_buffer, kexec_relocate_new_kernel,\n+\t       KEXEC_RELOCATE_NEW_KERNEL_SIZE);\n+\n+\tpr_info(\"Before _print_args().\\n\");\n+\tmachine_kexec_print_args();\n+\tpr_info(\"Before eval loop.\\n\");\n \n \t/*\n \t * The generic kexec code builds a page list with physical\n@@ -256,7 +372,7 @@ machine_kexec(struct kimage *image)\n #ifdef CONFIG_SMP\n \t/* All secondary cpus now may jump to kexec_wait cycle */\n \trelocated_kexec_smp_wait = reboot_code_buffer +\n-\t\t(void *)(kexec_smp_wait - relocate_new_kernel);\n+\t\t(void *)(kexec_smp_wait - kexec_relocate_new_kernel);\n \tsmp_wmb();\n \tatomic_set(&kexec_ready_to_reboot, 1);\n #endif\n--- /dev/null\n+++ b/arch/mips/kernel/machine_kexec.h\n@@ -0,0 +1,20 @@\n+#ifndef _MACHINE_KEXEC_H\n+#define _MACHINE_KEXEC_H\n+\n+#ifndef __ASSEMBLY__\n+extern const unsigned char kexec_relocate_new_kernel[];\n+extern unsigned long kexec_relocate_new_kernel_end;\n+extern unsigned long kexec_start_address;\n+extern unsigned long kexec_indirection_page;\n+\n+extern char kexec_argv_buf[];\n+extern char *kexec_argv[];\n+\n+#define KEXEC_RELOCATE_NEW_KERNEL_SIZE\t((unsigned long)&kexec_relocate_new_kernel_end - (unsigned long)kexec_relocate_new_kernel)\n+#endif /* !__ASSEMBLY__ */\n+\n+#define KEXEC_COMMAND_LINE_SIZE\t\t256\n+#define KEXEC_ARGV_SIZE\t\t\t(KEXEC_COMMAND_LINE_SIZE / 16)\n+#define KEXEC_MAX_ARGC\t\t\t(KEXEC_ARGV_SIZE / sizeof(long))\n+\n+#endif\n--- a/arch/mips/kernel/relocate_kernel.S\n+++ b/arch/mips/kernel/relocate_kernel.S\n@@ -10,10 +10,11 @@\n #include <asm/mipsregs.h>\n #include <asm/stackframe.h>\n #include <asm/addrspace.h>\n+#include \"machine_kexec.h\"\n \n #include <kernel-entry-init.h>\n \n-LEAF(relocate_new_kernel)\n+LEAF(kexec_relocate_new_kernel)\n \tPTR_L a0,\targ0\n \tPTR_L a1,\targ1\n \tPTR_L a2,\targ2\n@@ -98,7 +99,7 @@ done:\n #endif\n \t/* jump to kexec_start_address */\n \tj\t\ts1\n-\tEND(relocate_new_kernel)\n+\tEND(kexec_relocate_new_kernel)\n \n #ifdef CONFIG_SMP\n /*\n@@ -181,9 +182,15 @@ kexec_indirection_page:\n \tPTR_WD\t\t0\n \t.size\t\tkexec_indirection_page, PTRSIZE\n \n-relocate_new_kernel_end:\n+kexec_argv_buf:\n+\tEXPORT(kexec_argv_buf)\n+\t.skip\t\tKEXEC_COMMAND_LINE_SIZE\n+\t.size\t\tkexec_argv_buf, KEXEC_COMMAND_LINE_SIZE\n+\n+kexec_argv:\n+\tEXPORT(kexec_argv)\n+\t.skip\t\tKEXEC_ARGV_SIZE\n+\t.size\t\tkexec_argv, KEXEC_ARGV_SIZE\n \n-relocate_new_kernel_size:\n-\tEXPORT(relocate_new_kernel_size)\n-\tPTR_WD\t\trelocate_new_kernel_end - relocate_new_kernel\n-\t.size\t\trelocate_new_kernel_size, PTRSIZE\n+kexec_relocate_new_kernel_end:\n+\tEXPORT(kexec_relocate_new_kernel_end)\n"
  },
  {
    "path": "target/linux/generic/pending-5.15/332-arc-add-OWRTDTB-section.patch",
    "content": "From bb0c3b0175240bf152fd7c644821a0cf9f77c37c Mon Sep 17 00:00:00 2001\nFrom: Evgeniy Didin <Evgeniy.Didin@synopsys.com>\nDate: Fri, 15 Mar 2019 18:53:38 +0300\nSubject: [PATCH] arc add OWRTDTB section\n\nThis change allows OpenWRT to patch resulting kernel binary with\nexternal .dtb.\n\nThat allows us to re-use exactky the same vmlinux on different boards\ngiven its ARC core configurations match (at least cache line sizes etc).\n\n\"\"patch-dtb\" searches for ASCII \"OWRTDTB:\" strign and copies external\n.dtb right after it, keeping the string in place.\n\nSigned-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>\nSigned-off-by: Alexey Brodkin <abrodkin@synopsys.com>\nSigned-off-by: Evgeniy Didin <Evgeniy.Didin@synopsys.com>\n---\n arch/arc/kernel/head.S        | 10 ++++++++++\n arch/arc/kernel/setup.c       |  4 +++-\n arch/arc/kernel/vmlinux.lds.S | 13 +++++++++++++\n 3 files changed, 26 insertions(+), 1 deletion(-)\n\n--- a/arch/arc/kernel/head.S\n+++ b/arch/arc/kernel/head.S\n@@ -88,6 +88,16 @@\n \tDSP_EARLY_INIT\n .endm\n \n+\t; Here \"patch-dtb\" will embed external .dtb\n+\t; Note \"patch-dtb\" searches for ASCII \"OWRTDTB:\" string\n+\t; and pastes .dtb right after it, hense the string precedes\n+\t; __image_dtb symbol.\n+\t.section .owrt, \"aw\",@progbits\n+\t.ascii  \"OWRTDTB:\"\n+ENTRY(__image_dtb)\n+\t.fill   0x4000\n+END(__image_dtb)\n+\n \t.section .init.text, \"ax\",@progbits\n \n ;----------------------------------------------------------------\n--- a/arch/arc/kernel/setup.c\n+++ b/arch/arc/kernel/setup.c\n@@ -495,6 +495,8 @@ static inline bool uboot_arg_invalid(uns\n /* We always pass 0 as magic from U-boot */\n #define UBOOT_MAGIC_VALUE\t0\n \n+extern struct boot_param_header __image_dtb;\n+\n void __init handle_uboot_args(void)\n {\n \tbool use_embedded_dtb = true;\n@@ -533,7 +535,7 @@ void __init handle_uboot_args(void)\n ignore_uboot_args:\n \n \tif (use_embedded_dtb) {\n-\t\tmachine_desc = setup_machine_fdt(__dtb_start);\n+\t\tmachine_desc = setup_machine_fdt(&__image_dtb);\n \t\tif (!machine_desc)\n \t\t\tpanic(\"Embedded DT invalid\\n\");\n \t}\n--- a/arch/arc/kernel/vmlinux.lds.S\n+++ b/arch/arc/kernel/vmlinux.lds.S\n@@ -27,6 +27,19 @@ SECTIONS\n \n \t. = CONFIG_LINUX_LINK_BASE;\n \n+\t/*\n+\t* In OpenWRT we want to patch built binary embedding .dtb of choice.\n+\t* This is implemented with \"patch-dtb\" utility which searches for\n+\t* \"OWRTDTB:\" string in first 16k of image and if it is found\n+\t* copies .dtb right after mentioned string.\n+\t*\n+\t* Note: \"OWRTDTB:\" won't be overwritten with .dtb, .dtb will follow it.\n+\t*/\n+ \t.owrt : {\n+\t\t*(.owrt)\n+\t. = ALIGN(PAGE_SIZE);\n+\t}\n+\n \t_int_vec_base_lds = .;\n \t.vector : {\n \t\t*(.vector)\n"
  },
  {
    "path": "target/linux/generic/pending-5.15/333-arc-enable-unaligned-access-in-kernel-mode.patch",
    "content": "From: Alexey Brodkin <abrodkin@synopsys.com>\nSubject: arc: enable unaligned access in kernel mode\n\nThis enables misaligned access handling even in kernel mode.\nSome wireless drivers (ath9k-htc and mt7601u) use misaligned accesses\nhere and there and to cope with that without fixing stuff in the drivers\nwe're just gracefully handling it on ARC.\n\nSigned-off-by: Alexey Brodkin <abrodkin@synopsys.com>\n---\n arch/arc/kernel/unaligned.c | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/arch/arc/kernel/unaligned.c\n+++ b/arch/arc/kernel/unaligned.c\n@@ -202,7 +202,7 @@ int misaligned_fixup(unsigned long addre\n \tchar buf[TASK_COMM_LEN];\n \n \t/* handle user mode only and only if enabled by sysadmin */\n-\tif (!user_mode(regs) || !unaligned_enabled)\n+\tif (!unaligned_enabled)\n \t\treturn 1;\n \n \tif (no_unaligned_warning) {\n"
  },
  {
    "path": "target/linux/generic/pending-5.15/342-powerpc-Enable-kernel-XZ-compression-option-on-PPC_8.patch",
    "content": "From 66770a004afe10df11d3902e16eaa0c2c39436bb Mon Sep 17 00:00:00 2001\nFrom: Pawel Dembicki <paweldembicki@gmail.com>\nDate: Fri, 24 May 2019 17:56:19 +0200\nSubject: [PATCH] powerpc: Enable kernel XZ compression option on PPC_85xx\n\nEnable kernel XZ compression option on PPC_85xx. Tested with\nsimpleImage on TP-Link TL-WDR4900 (Freescale P1014 processor).\n\nSuggested-by: Christian Lamparter <chunkeey@gmail.com>\nSigned-off-by: Pawel Dembicki <paweldembicki@gmail.com>\n---\n arch/powerpc/Kconfig | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/arch/powerpc/Kconfig\n+++ b/arch/powerpc/Kconfig\n@@ -222,7 +222,7 @@ config PPC\n \tselect HAVE_KERNEL_GZIP\n \tselect HAVE_KERNEL_LZMA\t\t\tif DEFAULT_UIMAGE\n \tselect HAVE_KERNEL_LZO\t\t\tif DEFAULT_UIMAGE\n-\tselect HAVE_KERNEL_XZ\t\t\tif PPC_BOOK3S || 44x\n+\tselect HAVE_KERNEL_XZ\t\t\tif PPC_BOOK3S || 44x || PPC_85xx\n \tselect HAVE_KPROBES\n \tselect HAVE_KPROBES_ON_FTRACE\n \tselect HAVE_KRETPROBES\n"
  },
  {
    "path": "target/linux/generic/pending-5.15/400-mtd-mtdsplit-support.patch",
    "content": "--- a/drivers/mtd/Kconfig\n+++ b/drivers/mtd/Kconfig\n@@ -12,6 +12,25 @@ menuconfig MTD\n \n if MTD\n \n+menu \"OpenWrt specific MTD options\"\n+\n+config MTD_ROOTFS_ROOT_DEV\n+\tbool \"Automatically set 'rootfs' partition to be root filesystem\"\n+\tdefault y\n+\n+config MTD_SPLIT_FIRMWARE\n+\tbool \"Automatically split firmware partition for kernel+rootfs\"\n+\tdefault y\n+\n+config MTD_SPLIT_FIRMWARE_NAME\n+\tstring \"Firmware partition name\"\n+\tdepends on MTD_SPLIT_FIRMWARE\n+\tdefault \"firmware\"\n+\n+source \"drivers/mtd/mtdsplit/Kconfig\"\n+\n+endmenu\n+\n config MTD_TESTS\n \ttristate \"MTD tests support (DANGEROUS)\"\n \tdepends on m\n--- a/drivers/mtd/mtdpart.c\n+++ b/drivers/mtd/mtdpart.c\n@@ -15,10 +15,12 @@\n #include <linux/kmod.h>\n #include <linux/mtd/mtd.h>\n #include <linux/mtd/partitions.h>\n+#include <linux/magic.h>\n #include <linux/err.h>\n #include <linux/of.h>\n \n #include \"mtdcore.h\"\n+#include \"mtdsplit/mtdsplit.h\"\n \n /*\n  * MTD methods which simply translate the effective address and pass through\n@@ -235,6 +237,146 @@ static int mtd_add_partition_attrs(struc\n \treturn ret;\n }\n \n+static DEFINE_SPINLOCK(part_parser_lock);\n+static LIST_HEAD(part_parsers);\n+\n+static struct mtd_part_parser *mtd_part_parser_get(const char *name)\n+{\n+\tstruct mtd_part_parser *p, *ret = NULL;\n+\n+\tspin_lock(&part_parser_lock);\n+\n+\tlist_for_each_entry(p, &part_parsers, list)\n+\t\tif (!strcmp(p->name, name) && try_module_get(p->owner)) {\n+\t\t\tret = p;\n+\t\t\tbreak;\n+\t\t}\n+\n+\tspin_unlock(&part_parser_lock);\n+\n+\treturn ret;\n+}\n+\n+static inline void mtd_part_parser_put(const struct mtd_part_parser *p)\n+{\n+\tmodule_put(p->owner);\n+}\n+\n+static struct mtd_part_parser *\n+get_partition_parser_by_type(enum mtd_parser_type type,\n+\t\t\t     struct mtd_part_parser *start)\n+{\n+\tstruct mtd_part_parser *p, *ret = NULL;\n+\n+\tspin_lock(&part_parser_lock);\n+\n+\tp = list_prepare_entry(start, &part_parsers, list);\n+\tif (start)\n+\t\tmtd_part_parser_put(start);\n+\n+\tlist_for_each_entry_continue(p, &part_parsers, list) {\n+\t\tif (p->type == type && try_module_get(p->owner)) {\n+\t\t\tret = p;\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\n+\tspin_unlock(&part_parser_lock);\n+\n+\treturn ret;\n+}\n+\n+static int parse_mtd_partitions_by_type(struct mtd_info *master,\n+\t\t\t\t\tenum mtd_parser_type type,\n+\t\t\t\t\tconst struct mtd_partition **pparts,\n+\t\t\t\t\tstruct mtd_part_parser_data *data)\n+{\n+\tstruct mtd_part_parser *prev = NULL;\n+\tint ret = 0;\n+\n+\twhile (1) {\n+\t\tstruct mtd_part_parser *parser;\n+\n+\t\tparser = get_partition_parser_by_type(type, prev);\n+\t\tif (!parser)\n+\t\t\tbreak;\n+\n+\t\tret = (*parser->parse_fn)(master, pparts, data);\n+\n+\t\tif (ret > 0) {\n+\t\t\tmtd_part_parser_put(parser);\n+\t\t\tprintk(KERN_NOTICE\n+\t\t\t       \"%d %s partitions found on MTD device %s\\n\",\n+\t\t\t       ret, parser->name, master->name);\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\tprev = parser;\n+\t}\n+\n+\treturn ret;\n+}\n+\n+static int\n+run_parsers_by_type(struct mtd_info *child, enum mtd_parser_type type)\n+{\n+\tstruct mtd_partition *parts;\n+\tint nr_parts;\n+\tint i;\n+\n+\tnr_parts = parse_mtd_partitions_by_type(child, type, (const struct mtd_partition **)&parts,\n+\t\t\t\t\t\tNULL);\n+\tif (nr_parts <= 0)\n+\t\treturn nr_parts;\n+\n+\tif (WARN_ON(!parts))\n+\t\treturn 0;\n+\n+\tfor (i = 0; i < nr_parts; i++) {\n+\t\t/* adjust partition offsets */\n+\t\tparts[i].offset += child->part.offset;\n+\n+\t\tmtd_add_partition(child->parent,\n+\t\t\t\t  parts[i].name,\n+\t\t\t\t  parts[i].offset,\n+\t\t\t\t  parts[i].size);\n+\t}\n+\n+\tkfree(parts);\n+\n+\treturn nr_parts;\n+}\n+\n+#ifdef CONFIG_MTD_SPLIT_FIRMWARE_NAME\n+#define SPLIT_FIRMWARE_NAME\tCONFIG_MTD_SPLIT_FIRMWARE_NAME\n+#else\n+#define SPLIT_FIRMWARE_NAME\t\"unused\"\n+#endif\n+\n+static void split_firmware(struct mtd_info *master, struct mtd_info *part)\n+{\n+\trun_parsers_by_type(part, MTD_PARSER_TYPE_FIRMWARE);\n+}\n+\n+static void mtd_partition_split(struct mtd_info *master, struct mtd_info *part)\n+{\n+\tstatic int rootfs_found = 0;\n+\n+\tif (rootfs_found)\n+\t\treturn;\n+\n+\tif (!strcmp(part->name, \"rootfs\")) {\n+\t\trun_parsers_by_type(part, MTD_PARSER_TYPE_ROOTFS);\n+\n+\t\trootfs_found = 1;\n+\t}\n+\n+\tif (IS_ENABLED(CONFIG_MTD_SPLIT_FIRMWARE) &&\n+\t    !strcmp(part->name, SPLIT_FIRMWARE_NAME) &&\n+\t    !of_find_property(mtd_get_of_node(part), \"compatible\", NULL))\n+\t\tsplit_firmware(master, part);\n+}\n+\n int mtd_add_partition(struct mtd_info *parent, const char *name,\n \t\t      long long offset, long long length)\n {\n@@ -273,6 +415,7 @@ int mtd_add_partition(struct mtd_info *p\n \tif (ret)\n \t\tgoto err_remove_part;\n \n+\tmtd_partition_split(parent, child);\n \tmtd_add_partition_attrs(child);\n \n \treturn 0;\n@@ -421,6 +564,7 @@ int add_mtd_partitions(struct mtd_info *\n \t\t\tgoto err_del_partitions;\n \t\t}\n \n+\t\tmtd_partition_split(master, child);\n \t\tmtd_add_partition_attrs(child);\n \n \t\t/* Look for subpartitions */\n@@ -437,31 +581,6 @@ err_del_partitions:\n \treturn ret;\n }\n \n-static DEFINE_SPINLOCK(part_parser_lock);\n-static LIST_HEAD(part_parsers);\n-\n-static struct mtd_part_parser *mtd_part_parser_get(const char *name)\n-{\n-\tstruct mtd_part_parser *p, *ret = NULL;\n-\n-\tspin_lock(&part_parser_lock);\n-\n-\tlist_for_each_entry(p, &part_parsers, list)\n-\t\tif (!strcmp(p->name, name) && try_module_get(p->owner)) {\n-\t\t\tret = p;\n-\t\t\tbreak;\n-\t\t}\n-\n-\tspin_unlock(&part_parser_lock);\n-\n-\treturn ret;\n-}\n-\n-static inline void mtd_part_parser_put(const struct mtd_part_parser *p)\n-{\n-\tmodule_put(p->owner);\n-}\n-\n /*\n  * Many partition parsers just expected the core to kfree() all their data in\n  * one chunk. Do that by default.\n--- a/include/linux/mtd/partitions.h\n+++ b/include/linux/mtd/partitions.h\n@@ -75,6 +75,12 @@ struct mtd_part_parser_data {\n  * Functions dealing with the various ways of partitioning the space\n  */\n \n+enum mtd_parser_type {\n+\tMTD_PARSER_TYPE_DEVICE = 0,\n+\tMTD_PARSER_TYPE_ROOTFS,\n+\tMTD_PARSER_TYPE_FIRMWARE,\n+};\n+\n struct mtd_part_parser {\n \tstruct list_head list;\n \tstruct module *owner;\n@@ -83,6 +89,7 @@ struct mtd_part_parser {\n \tint (*parse_fn)(struct mtd_info *, const struct mtd_partition **,\n \t\t\tstruct mtd_part_parser_data *);\n \tvoid (*cleanup)(const struct mtd_partition *pparts, int nr_parts);\n+\tenum mtd_parser_type type;\n };\n \n /* Container for passing around a set of parsed partitions */\n--- a/drivers/mtd/Makefile\n+++ b/drivers/mtd/Makefile\n@@ -9,6 +9,8 @@ mtd-y\t\t\t\t:= mtdcore.o mtdsuper.o mtdconc\n \n obj-y\t\t\t\t+= parsers/\n \n+obj-$(CONFIG_MTD_SPLIT)\t\t+= mtdsplit/\n+\n # 'Users' - code which presents functionality to userspace.\n obj-$(CONFIG_MTD_BLKDEVS)\t+= mtd_blkdevs.o\n obj-$(CONFIG_MTD_BLOCK)\t\t+= mtdblock.o\n--- a/include/linux/mtd/mtd.h\n+++ b/include/linux/mtd/mtd.h\n@@ -613,6 +613,24 @@ static inline void mtd_align_erase_req(s\n \t\treq->len += mtd->erasesize - mod;\n }\n \n+static inline uint64_t mtd_roundup_to_eb(uint64_t sz, struct mtd_info *mtd)\n+{\n+\tif (mtd_mod_by_eb(sz, mtd) == 0)\n+\t\treturn sz;\n+\n+\t/* Round up to next erase block */\n+\treturn (mtd_div_by_eb(sz, mtd) + 1) * mtd->erasesize;\n+}\n+\n+static inline uint64_t mtd_rounddown_to_eb(uint64_t sz, struct mtd_info *mtd)\n+{\n+\tif (mtd_mod_by_eb(sz, mtd) == 0)\n+\t\treturn sz;\n+\n+\t/* Round down to the start of the current erase block */\n+\treturn (mtd_div_by_eb(sz, mtd)) * mtd->erasesize;\n+}\n+\n static inline uint32_t mtd_div_by_ws(uint64_t sz, struct mtd_info *mtd)\n {\n \tif (mtd->writesize_shift)\n@@ -685,6 +703,13 @@ extern void __put_mtd_device(struct mtd_\n extern struct mtd_info *get_mtd_device_nm(const char *name);\n extern void put_mtd_device(struct mtd_info *mtd);\n \n+static inline uint64_t mtdpart_get_offset(const struct mtd_info *mtd)\n+{\n+\tif (!mtd_is_partition(mtd))\n+\t\treturn 0;\n+\n+\treturn mtd->part.offset;\n+}\n \n struct mtd_notifier {\n \tvoid (*add)(struct mtd_info *mtd);\n"
  },
  {
    "path": "target/linux/generic/pending-5.15/402-mtd-spi-nor-write-support-for-minor-aligned-partitions.patch",
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Tue,\n 8 Jun 2021 00:07:35 -0400 (EDT)\nFrom: John Thomson <git@johnthomson.fastmail.com.au>\nTo: Miquel Raynal <miquel.raynal@bootlin.com>,\n Richard Weinberger <richard@nod.at>, Vignesh Raghavendra <vigneshr@ti.com>,\n Tudor Ambarus <tudor.ambarus@microchip.com>,\n Michael Walle <michael@walle.cc>, Pratyush Yadav <p.yadav@ti.com>,\n linux-mtd@lists.infradead.org\nCc: linux-kernel@vger.kernel.org,\n John Thomson <git@johnthomson.fastmail.com.au>,\n kernel test robot <lkp@intel.com>, Dan Carpenter <dan.carpenter@oracle.com>\nSubject: [PATCH] mtd: spi-nor: write support for minor aligned partitions\nDate: Tue,  8 Jun 2021 14:07:19 +1000\nMessage-Id: <20210608040719.14431-1-git@johnthomson.fastmail.com.au>\nX-Mailer: git-send-email 2.31.1\nMIME-Version: 1.0\nX-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 \nX-CRM114-CacheID: sfid-20210607_210745_712053_67A7D864 \nX-CRM114-Status: GOOD (  26.99  )\nX-Spam-Score: -0.8 (/)\nX-Spam-Report: Spam detection software,\n running on the system \"bombadil.infradead.org\",\n has NOT identified this incoming email as spam.  The original\n message has been attached to this so you can view it or label\n similar future email.  If you have any questions, see\n the administrator of that system for details.\n Content preview:  Do not prevent writing to mtd partitions where a partition\n boundary sits on a minor erasesize boundary. This addresses a FIXME that\n has been present since the start of the linux git history: /* Doesn' [...]\n Content analysis details:   (-0.8 points, 5.0 required)\n pts rule name              description\n ---- ----------------------\n --------------------------------------------------\n -0.7 RCVD_IN_DNSWL_LOW      RBL: Sender listed at https://www.dnswl.org/,\n low trust [66.111.4.221 listed in list.dnswl.org]\n -0.0 SPF_PASS               SPF: sender matches SPF record\n -0.0 SPF_HELO_PASS          SPF: HELO matches SPF record\n 0.0 RCVD_IN_MSPIKE_H3      RBL: Good reputation (+3)\n [66.111.4.221 listed in wl.mailspike.net]\n -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature\n 0.1 DKIM_SIGNED            Message has a DKIM or DK signature,\n not necessarily\n valid\n -0.1 DKIM_VALID_EF          Message has a valid DKIM or DK signature from\n envelope-from domain\n 0.0 RCVD_IN_MSPIKE_WL      Mailspike good senders\nX-BeenThere: linux-mtd@lists.infradead.org\nX-Mailman-Version: 2.1.34\nPrecedence: list\nList-Id: Linux MTD discussion mailing list <linux-mtd.lists.infradead.org>\nList-Unsubscribe: <http://lists.infradead.org/mailman/options/linux-mtd>,\n <mailto:linux-mtd-request@lists.infradead.org?subject=unsubscribe>\nList-Archive: <http://lists.infradead.org/pipermail/linux-mtd/>\nList-Post: <mailto:linux-mtd@lists.infradead.org>\nList-Help: <mailto:linux-mtd-request@lists.infradead.org?subject=help>\nList-Subscribe: <http://lists.infradead.org/mailman/listinfo/linux-mtd>,\n <mailto:linux-mtd-request@lists.infradead.org?subject=subscribe>\nSender: \"linux-mtd\" <linux-mtd-bounces@lists.infradead.org>\nErrors-To: linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org\n\nDo not prevent writing to mtd partitions where a partition boundary sits\non a minor erasesize boundary.\nThis addresses a FIXME that has been present since the start of the\nlinux git history:\n/* Doesn't start on a boundary of major erase size */\n/* FIXME: Let it be writable if it is on a boundary of\n * _minor_ erase size though */\n\nAllow a uniform erase region spi-nor device to be configured\nto use the non-uniform erase regions code path for an erase with:\nCONFIG_MTD_SPI_NOR_USE_VARIABLE_ERASE=y\n\nOn supporting hardware (SECT_4K: majority of current SPI-NOR device)\nprovide the facility for an erase to use the least number\nof SPI-NOR operations, as well as access to 4K erase without\nrequiring CONFIG_MTD_SPI_NOR_USE_4K_SECTORS\n\nIntroduce erasesize_minor to the mtd struct,\nthe smallest erasesize supported by the device\n\nOn existing devices, this is useful where write support is wanted\nfor data on a 4K partition, such as some u-boot-env partitions,\nor RouterBoot soft_config, while still netting the performance\nbenefits of using 64K sectors\n\nPerformance:\ntime mtd erase firmware\nOpenWrt 5.10 ramips MT7621 w25q128jv 0xfc0000 partition length\n\nWithout this patch\nMTD_SPI_NOR_USE_4K_SECTORS=y\t|n\nreal    2m 11.66s\t\t|0m 50.86s\nuser    0m 0.00s\t\t|0m 0.00s\nsys     1m 56.20s\t\t|0m 50.80s\n\nWith this patch\nMTD_SPI_NOR_USE_VARIABLE_ERASE=n|y\t\t|4K_SECTORS=y\nreal    0m 51.68s\t\t|0m 50.85s\t|2m 12.89s\nuser    0m 0.00s\t\t|0m 0.00s\t|0m 0.01s\nsys     0m 46.94s\t\t|0m 50.38s\t|2m 12.46s\n\nSigned-off-by: John Thomson <git@johnthomson.fastmail.com.au>\n---\nHave not tested on variable erase regions device.\n\ncheckpatch does not like the printk(KERN_WARNING\nthese should be changed separately beforehand?\n\nChanges RFC -> v1:\nFix uninitialized variable smatch warning\nReported-by: kernel test robot <lkp@intel.com>\nReported-by: Dan Carpenter <dan.carpenter@oracle.com>\n---\n drivers/mtd/mtdpart.c       | 52 ++++++++++++++++++++++++++++---------\n drivers/mtd/spi-nor/Kconfig | 10 +++++++\n drivers/mtd/spi-nor/core.c  | 10 +++++--\n include/linux/mtd/mtd.h     |  2 ++\n 4 files changed, 60 insertions(+), 14 deletions(-)\n\n--- a/drivers/mtd/mtdpart.c\n+++ b/drivers/mtd/mtdpart.c\n@@ -40,10 +40,11 @@ static struct mtd_info *allocate_partiti\n \tstruct mtd_info *master = mtd_get_master(parent);\n \tint wr_alignment = (parent->flags & MTD_NO_ERASE) ?\n \t\t\t   master->writesize : master->erasesize;\n+\tint wr_alignment_minor = 0;\n \tu64 parent_size = mtd_is_partition(parent) ?\n \t\t\t  parent->part.size : parent->size;\n \tstruct mtd_info *child;\n-\tu32 remainder;\n+\tu32 remainder, remainder_minor;\n \tchar *name;\n \tu64 tmp;\n \n@@ -145,6 +146,7 @@ static struct mtd_info *allocate_partiti\n \t\tint i, max = parent->numeraseregions;\n \t\tu64 end = child->part.offset + child->part.size;\n \t\tstruct mtd_erase_region_info *regions = parent->eraseregions;\n+\t\tuint32_t erasesize_minor = child->erasesize;\n \n \t\t/* Find the first erase regions which is part of this\n \t\t * partition. */\n@@ -155,15 +157,24 @@ static struct mtd_info *allocate_partiti\n \t\tif (i > 0)\n \t\t\ti--;\n \n-\t\t/* Pick biggest erasesize */\n \t\tfor (; i < max && regions[i].offset < end; i++) {\n+\t\t\t/* Pick biggest erasesize */\n \t\t\tif (child->erasesize < regions[i].erasesize)\n \t\t\t\tchild->erasesize = regions[i].erasesize;\n+\t\t\t/* Pick smallest non-zero erasesize */\n+\t\t\tif ((erasesize_minor > regions[i].erasesize) && (regions[i].erasesize > 0))\n+\t\t\t\terasesize_minor = regions[i].erasesize;\n \t\t}\n+\n+\t\tif (erasesize_minor < child->erasesize)\n+\t\t\tchild->erasesize_minor = erasesize_minor;\n+\n \t\tBUG_ON(child->erasesize == 0);\n \t} else {\n \t\t/* Single erase size */\n \t\tchild->erasesize = master->erasesize;\n+\t\tif (master->erasesize_minor)\n+\t\t\tchild->erasesize_minor = master->erasesize_minor;\n \t}\n \n \t/*\n@@ -171,26 +182,43 @@ static struct mtd_info *allocate_partiti\n \t * exposes several regions with different erasesize. Adjust\n \t * wr_alignment accordingly.\n \t */\n-\tif (!(child->flags & MTD_NO_ERASE))\n+\tif (!(child->flags & MTD_NO_ERASE)) {\n \t\twr_alignment = child->erasesize;\n+\t\tif (IS_ENABLED(CONFIG_MTD_SPI_NOR_USE_VARIABLE_ERASE) && child->erasesize_minor)\n+\t\t\twr_alignment_minor = child->erasesize_minor;\n+\t}\n \n \ttmp = mtd_get_master_ofs(child, 0);\n \tremainder = do_div(tmp, wr_alignment);\n \tif ((child->flags & MTD_WRITEABLE) && remainder) {\n-\t\t/* Doesn't start on a boundary of major erase size */\n-\t\t/* FIXME: Let it be writable if it is on a boundary of\n-\t\t * _minor_ erase size though */\n-\t\tchild->flags &= ~MTD_WRITEABLE;\n-\t\tprintk(KERN_WARNING\"mtd: partition \\\"%s\\\" doesn't start on an erase/write block boundary -- force read-only\\n\",\n-\t\t\tpart->name);\n+\t\tif (wr_alignment_minor) {\n+\t\t\ttmp = mtd_get_master_ofs(child, 0);\n+\t\t\tremainder_minor = do_div(tmp, wr_alignment_minor);\n+\t\t\tif (remainder_minor == 0)\n+\t\t\t\tchild->erasesize = child->erasesize_minor;\n+\t\t}\n+\n+\t\tif ((!wr_alignment_minor) || (wr_alignment_minor && remainder_minor != 0)) {\n+\t\t\tchild->flags &= ~MTD_WRITEABLE;\n+\t\t\tprintk(KERN_WARNING\"mtd: partition \\\"%s\\\" doesn't start on an erase/write block boundary -- force read-only\\n\",\n+\t\t\t\tpart->name);\n+\t\t}\n \t}\n \n \ttmp = mtd_get_master_ofs(child, 0) + child->part.size;\n \tremainder = do_div(tmp, wr_alignment);\n \tif ((child->flags & MTD_WRITEABLE) && remainder) {\n-\t\tchild->flags &= ~MTD_WRITEABLE;\n-\t\tprintk(KERN_WARNING\"mtd: partition \\\"%s\\\" doesn't end on an erase/write block -- force read-only\\n\",\n-\t\t\tpart->name);\n+\t\tif (wr_alignment_minor) {\n+\t\t\ttmp = mtd_get_master_ofs(child, 0) + child->part.size;\n+\t\t\tremainder_minor = do_div(tmp, wr_alignment_minor);\n+\t\t\tif (remainder_minor == 0)\n+\t\t\t\tchild->erasesize = child->erasesize_minor;\n+\t\t}\n+\t\tif ((!wr_alignment_minor) || (wr_alignment_minor && remainder_minor != 0)) {\n+\t\t\tchild->flags &= ~MTD_WRITEABLE;\n+\t\t\tprintk(KERN_WARNING\"mtd: partition \\\"%s\\\" doesn't end on an erase/write block -- force read-only\\n\",\n+\t\t\t\tpart->name);\n+\t\t}\n \t}\n \n \tchild->size = child->part.size;\n--- a/drivers/mtd/spi-nor/Kconfig\n+++ b/drivers/mtd/spi-nor/Kconfig\n@@ -10,6 +10,16 @@ menuconfig MTD_SPI_NOR\n \n if MTD_SPI_NOR\n \n+config MTD_SPI_NOR_USE_VARIABLE_ERASE\n+\tbool \"Disable uniform_erase to allow use of all hardware supported erasesizes\"\n+\tdepends on !MTD_SPI_NOR_USE_4K_SECTORS\n+\tdefault n\n+\thelp\n+\t  Allow mixed use of all hardware supported erasesizes,\n+\t  by forcing spi_nor to use the multiple eraseregions code path.\n+\t  For example: A 68K erase will use one 64K erase, and one 4K erase\n+\t  on supporting hardware.\n+\n config MTD_SPI_NOR_USE_4K_SECTORS\n \tbool \"Use small 4096 B erase sectors\"\n \tdefault y\n--- a/drivers/mtd/spi-nor/core.c\n+++ b/drivers/mtd/spi-nor/core.c\n@@ -1262,6 +1262,8 @@ static u8 spi_nor_convert_3to4_erase(u8\n \n static bool spi_nor_has_uniform_erase(const struct spi_nor *nor)\n {\n+\tif (IS_ENABLED(CONFIG_MTD_SPI_NOR_USE_VARIABLE_ERASE))\n+\t\treturn false;\n \treturn !!nor->params->erase_map.uniform_erase_type;\n }\n \n@@ -2379,6 +2381,7 @@ static int spi_nor_select_erase(struct s\n {\n \tstruct spi_nor_erase_map *map = &nor->params->erase_map;\n \tconst struct spi_nor_erase_type *erase = NULL;\n+\tconst struct spi_nor_erase_type *erase_minor = NULL;\n \tstruct mtd_info *mtd = &nor->mtd;\n \tu32 wanted_size = nor->info->sector_size;\n \tint i;\n@@ -2411,8 +2414,9 @@ static int spi_nor_select_erase(struct s\n \t */\n \tfor (i = SNOR_ERASE_TYPE_MAX - 1; i >= 0; i--) {\n \t\tif (map->erase_type[i].size) {\n-\t\t\terase = &map->erase_type[i];\n-\t\t\tbreak;\n+\t\t\tif (!erase)\n+\t\t\t\terase = &map->erase_type[i];\n+\t\t\terase_minor = &map->erase_type[i];\n \t\t}\n \t}\n \n@@ -2420,6 +2424,8 @@ static int spi_nor_select_erase(struct s\n \t\treturn -EINVAL;\n \n \tmtd->erasesize = erase->size;\n+\tif (erase_minor && erase_minor->size < erase->size)\n+\t\tmtd->erasesize_minor = erase_minor->size;\n \treturn 0;\n }\n \n--- a/include/linux/mtd/mtd.h\n+++ b/include/linux/mtd/mtd.h\n@@ -243,6 +243,8 @@ struct mtd_info {\n \t * information below if they desire\n \t */\n \tuint32_t erasesize;\n+\t/* \"Minor\" (smallest) erase size supported by the whole device */\n+\tuint32_t erasesize_minor;\n \t/* Minimal writable flash unit size. In case of NOR flash it is 1 (even\n \t * though individual bits can be cleared), in case of NAND flash it is\n \t * one NAND page (or half, or one-fourths of it), in case of ECC-ed NOR\n"
  },
  {
    "path": "target/linux/generic/pending-5.15/419-mtd-redboot-add-of_match_table-with-DT-binding.patch",
    "content": "From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nSubject: [PATCH] mtd: redboot: add of_match_table with DT binding\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nThis allows parsing RedBoot compatible partitions for properly described\nflash device in DT.\n\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\n---\n\n--- a/drivers/mtd/parsers/redboot.c\n+++ b/drivers/mtd/parsers/redboot.c\n@@ -304,6 +304,7 @@ nogood:\n \n static const struct of_device_id mtd_parser_redboot_of_match_table[] = {\n \t{ .compatible = \"redboot-fis\" },\n+\t{ .compatible = \"ecoscentric,redboot-fis-partitions\" },\n \t{},\n };\n MODULE_DEVICE_TABLE(of, mtd_parser_redboot_of_match_table);\n"
  },
  {
    "path": "target/linux/generic/pending-5.15/420-mtd-redboot_space.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nSubject: add patch for including unpartitioned space in the rootfs partition for redboot devices (if applicable)\n\n[john@phrozen.org: used by ixp and others]\n\nlede-commit: 394918851f84e4d00fa16eb900e7700e95091f00\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n drivers/mtd/redboot.c | 19 +++++++++++++------\n 1 file changed, 13 insertions(+), 6 deletions(-)\n\n--- a/drivers/mtd/parsers/redboot.c\n+++ b/drivers/mtd/parsers/redboot.c\n@@ -277,14 +277,21 @@ nogood:\n #endif\n \t\tnames += strlen(names) + 1;\n \n-#ifdef CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED\n \t\tif (fl->next && fl->img->flash_base + fl->img->size + master->erasesize <= fl->next->img->flash_base) {\n-\t\t\ti++;\n-\t\t\tparts[i].offset = parts[i - 1].size + parts[i - 1].offset;\n-\t\t\tparts[i].size = fl->next->img->flash_base - parts[i].offset;\n-\t\t\tparts[i].name = nullname;\n-\t\t}\n+\t\t\tif (!strcmp(parts[i].name, \"rootfs\")) {\n+\t\t\t\tparts[i].size = fl->next->img->flash_base;\n+\t\t\t\tparts[i].size &= ~(master->erasesize - 1);\n+\t\t\t\tparts[i].size -= parts[i].offset;\n+#ifdef CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED\n+\t\t\t\tnrparts--;\n+\t\t\t} else {\n+\t\t\t\ti++;\n+\t\t\t\tparts[i].offset = parts[i-1].size + parts[i-1].offset;\n+\t\t\t\tparts[i].size = fl->next->img->flash_base - parts[i].offset;\n+\t\t\t\tparts[i].name = nullname;\n #endif\n+\t\t\t}\n+\t\t}\n \t\ttmp_fl = fl;\n \t\tfl = fl->next;\n \t\tkfree(tmp_fl);\n"
  },
  {
    "path": "target/linux/generic/pending-5.15/430-mtd-add-myloader-partition-parser.patch",
    "content": "From: Florian Fainelli <f.fainelli@gmail.com>\nSubject: Add myloader partition table parser\n\n[john@phozen.org: shoud be upstreamable]\n\nlede-commit: d8bf22859b51faa09d22c056fe221a45d2f7a3b8\nSigned-off-by: Florian Fainelli <f.fainelli@gmail.com>\n[adjust for kernel 5.4, add myloader.c to patch]\nSigned-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>\n\n--- a/drivers/mtd/parsers/Kconfig\n+++ b/drivers/mtd/parsers/Kconfig\n@@ -57,6 +57,22 @@ config MTD_CMDLINE_PARTS\n \n \t  If unsure, say 'N'.\n \n+config MTD_MYLOADER_PARTS\n+\ttristate \"MyLoader partition parsing\"\n+\tdepends on ADM5120 || ATH25 || ATH79\n+\thelp\n+\t  MyLoader is a bootloader which allows the user to define partitions\n+\t  in flash devices, by putting a table in the second erase block\n+\t  on the device, similar to a partition table. This table gives the \n+\t  offsets and lengths of the user defined partitions.\n+\n+\t  If you need code which can detect and parse these tables, and\n+\t  register MTD 'partitions' corresponding to each image detected,\n+\t  enable this option.\n+\n+\t  You will still need the parsing functions to be called by the driver\n+\t  for your particular device. It won't happen automatically.\n+\n config MTD_OF_PARTS\n \ttristate \"OpenFirmware (device tree) partitioning parser\"\n \tdefault y\n--- a/drivers/mtd/parsers/Makefile\n+++ b/drivers/mtd/parsers/Makefile\n@@ -3,6 +3,7 @@ obj-$(CONFIG_MTD_AR7_PARTS)\t\t+= ar7part.\n obj-$(CONFIG_MTD_BCM47XX_PARTS)\t\t+= bcm47xxpart.o\n obj-$(CONFIG_MTD_BCM63XX_PARTS)\t\t+= bcm63xxpart.o\n obj-$(CONFIG_MTD_CMDLINE_PARTS)\t\t+= cmdlinepart.o\n+obj-$(CONFIG_MTD_MYLOADER_PARTS)\t\t+= myloader.o\n obj-$(CONFIG_MTD_OF_PARTS)\t\t+= ofpart.o\n ofpart-y\t\t\t\t+= ofpart_core.o\n ofpart-$(CONFIG_MTD_OF_PARTS_BCM4908)\t+= ofpart_bcm4908.o\n--- /dev/null\n+++ b/drivers/mtd/parsers/myloader.c\n@@ -0,0 +1,181 @@\n+/*\n+ *  Parse MyLoader-style flash partition tables and produce a Linux partition\n+ *  array to match.\n+ *\n+ *  Copyright (C) 2007-2009 Gabor Juhos <juhosg@openwrt.org>\n+ *\n+ *  This file was based on drivers/mtd/redboot.c\n+ *  Author: Red Hat, Inc. - David Woodhouse <dwmw2@cambridge.redhat.com>\n+ *\n+ *  This program is free software; you can redistribute it and/or modify it\n+ *  under the terms of the GNU General Public License version 2 as published\n+ *  by the Free Software Foundation.\n+ */\n+\n+#include <linux/kernel.h>\n+#include <linux/module.h>\n+#include <linux/version.h>\n+#include <linux/slab.h>\n+#include <linux/init.h>\n+#include <linux/vmalloc.h>\n+#include <linux/mtd/mtd.h>\n+#include <linux/mtd/partitions.h>\n+#include <linux/byteorder/generic.h>\n+#include <linux/myloader.h>\n+\n+#define BLOCK_LEN_MIN\t\t0x10000\n+#define PART_NAME_LEN\t\t32\n+\n+struct part_data {\n+\tstruct mylo_partition_table\ttab;\n+\tchar names[MYLO_MAX_PARTITIONS][PART_NAME_LEN];\n+};\n+\n+static int myloader_parse_partitions(struct mtd_info *master,\n+\t\t\t\t     const struct mtd_partition **pparts,\n+\t\t\t\t     struct mtd_part_parser_data *data)\n+{\n+\tstruct part_data *buf;\n+\tstruct mylo_partition_table *tab;\n+\tstruct mylo_partition *part;\n+\tstruct mtd_partition *mtd_parts;\n+\tstruct mtd_partition *mtd_part;\n+\tint num_parts;\n+\tint ret, i;\n+\tsize_t retlen;\n+\tchar *names;\n+\tunsigned long offset;\n+\tunsigned long blocklen;\n+\n+\tbuf = vmalloc(sizeof(*buf));\n+\tif (!buf) {\n+\t\treturn -ENOMEM;\n+\t\tgoto out;\n+\t}\n+\ttab = &buf->tab;\n+\n+\tblocklen = master->erasesize;\n+\tif (blocklen < BLOCK_LEN_MIN)\n+\t\tblocklen = BLOCK_LEN_MIN;\n+\n+\toffset = blocklen;\n+\n+\t/* Find the partition table */\n+\tfor (i = 0; i < 4; i++, offset += blocklen) {\n+\t\tprintk(KERN_DEBUG \"%s: searching for MyLoader partition table\"\n+\t\t\t\t\" at offset 0x%lx\\n\", master->name, offset);\n+\n+\t\tret = mtd_read(master, offset, sizeof(*buf), &retlen,\n+\t\t\t       (void *)buf);\n+\t\tif (ret)\n+\t\t\tgoto out_free_buf;\n+\n+\t\tif (retlen != sizeof(*buf)) {\n+\t\t\tret = -EIO;\n+\t\t\tgoto out_free_buf;\n+\t\t}\n+\n+\t\t/* Check for Partition Table magic number */\n+\t\tif (tab->magic == le32_to_cpu(MYLO_MAGIC_PARTITIONS))\n+\t\t\tbreak;\n+\n+\t}\n+\n+\tif (tab->magic != le32_to_cpu(MYLO_MAGIC_PARTITIONS)) {\n+\t\tprintk(KERN_DEBUG \"%s: no MyLoader partition table found\\n\",\n+\t\t\tmaster->name);\n+\t\tret = 0;\n+\t\tgoto out_free_buf;\n+\t}\n+\n+\t/* The MyLoader and the Partition Table is always present */\n+\tnum_parts = 2;\n+\n+\t/* Detect number of used partitions */\n+\tfor (i = 0; i < MYLO_MAX_PARTITIONS; i++) {\n+\t\tpart = &tab->partitions[i];\n+\n+\t\tif (le16_to_cpu(part->type) == PARTITION_TYPE_FREE)\n+\t\t\tcontinue;\n+\n+\t\tnum_parts++;\n+\t}\n+\n+\tmtd_parts = kzalloc((num_parts * sizeof(*mtd_part) +\n+\t\t\t\tnum_parts * PART_NAME_LEN), GFP_KERNEL);\n+\n+\tif (!mtd_parts) {\n+\t\tret = -ENOMEM;\n+\t\tgoto out_free_buf;\n+\t}\n+\n+\tmtd_part = mtd_parts;\n+\tnames = (char *)&mtd_parts[num_parts];\n+\n+\tstrncpy(names, \"myloader\", PART_NAME_LEN);\n+\tmtd_part->name = names;\n+\tmtd_part->offset = 0;\n+\tmtd_part->size = offset;\n+\tmtd_part->mask_flags = MTD_WRITEABLE;\n+\tmtd_part++;\n+\tnames += PART_NAME_LEN;\n+\n+\tstrncpy(names, \"partition_table\", PART_NAME_LEN);\n+\tmtd_part->name = names;\n+\tmtd_part->offset = offset;\n+\tmtd_part->size = blocklen;\n+\tmtd_part->mask_flags = MTD_WRITEABLE;\n+\tmtd_part++;\n+\tnames += PART_NAME_LEN;\n+\n+\tfor (i = 0; i < MYLO_MAX_PARTITIONS; i++) {\n+\t\tpart = &tab->partitions[i];\n+\n+\t\tif (le16_to_cpu(part->type) == PARTITION_TYPE_FREE)\n+\t\t\tcontinue;\n+\n+\t\tif ((buf->names[i][0]) && (buf->names[i][0] != '\\xff'))\n+\t\t\tstrncpy(names, buf->names[i], PART_NAME_LEN);\n+\t\telse\n+\t\t\tsnprintf(names, PART_NAME_LEN, \"partition%d\", i);\n+\n+\t\tmtd_part->offset = le32_to_cpu(part->addr);\n+\t\tmtd_part->size = le32_to_cpu(part->size);\n+\t\tmtd_part->name = names;\n+\t\tmtd_part++;\n+\t\tnames += PART_NAME_LEN;\n+\t}\n+\n+\t*pparts = mtd_parts;\n+\tret = num_parts;\n+\n+ out_free_buf:\n+\tvfree(buf);\n+ out:\n+\treturn ret;\n+}\n+\n+static struct mtd_part_parser myloader_mtd_parser = {\n+\t.owner\t\t= THIS_MODULE,\n+\t.parse_fn\t= myloader_parse_partitions,\n+\t.name\t\t= \"MyLoader\",\n+};\n+\n+static int __init myloader_mtd_parser_init(void)\n+{\n+\tregister_mtd_parser(&myloader_mtd_parser);\n+\n+\treturn 0;\n+}\n+\n+static void __exit myloader_mtd_parser_exit(void)\n+{\n+\tderegister_mtd_parser(&myloader_mtd_parser);\n+}\n+\n+module_init(myloader_mtd_parser_init);\n+module_exit(myloader_mtd_parser_exit);\n+\n+MODULE_AUTHOR(\"Gabor Juhos <juhosg@openwrt.org>\");\n+MODULE_DESCRIPTION(\"Parsing code for MyLoader partition tables\");\n+MODULE_LICENSE(\"GPL v2\");\n"
  },
  {
    "path": "target/linux/generic/pending-5.15/431-mtd-bcm47xxpart-check-for-bad-blocks-when-calculatin.patch",
    "content": "From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <zajec5@gmail.com>\nSubject: [PATCH] mtd: bcm47xxpart: check for bad blocks when calculating offsets\n\nSigned-off-by: Rafał Miłecki <zajec5@gmail.com>\n---\n\n--- a/drivers/mtd/parsers/parser_trx.c\n+++ b/drivers/mtd/parsers/parser_trx.c\n@@ -25,6 +25,33 @@ struct trx_header {\n \tuint32_t offset[3];\n } __packed;\n \n+/*\n+ * Calculate real end offset (address) for a given amount of data. It checks\n+ * all blocks skipping bad ones.\n+ */\n+static size_t parser_trx_real_offset(struct mtd_info *mtd, size_t bytes)\n+{\n+\tsize_t real_offset = 0;\n+\n+\tif (mtd_block_isbad(mtd, real_offset))\n+\t\tpr_warn(\"Base offset shouldn't be at bad block\");\n+\n+\twhile (bytes >= mtd->erasesize) {\n+\t\tbytes -= mtd->erasesize;\n+\t\treal_offset += mtd->erasesize;\n+\t\twhile (mtd_block_isbad(mtd, real_offset)) {\n+\t\t\treal_offset += mtd->erasesize;\n+\n+\t\t\tif (real_offset >= mtd->size)\n+\t\t\t\treturn real_offset - mtd->erasesize;\n+\t\t}\n+\t}\n+\n+\treal_offset += bytes;\n+\n+\treturn real_offset;\n+}\n+\n static const char *parser_trx_data_part_name(struct mtd_info *master,\n \t\t\t\t\t     size_t offset)\n {\n@@ -86,21 +113,21 @@ static int parser_trx_parse(struct mtd_i\n \tif (trx.offset[2]) {\n \t\tpart = &parts[curr_part++];\n \t\tpart->name = \"loader\";\n-\t\tpart->offset = trx.offset[i];\n+\t\tpart->offset = parser_trx_real_offset(mtd, trx.offset[i]);\n \t\ti++;\n \t}\n \n \tif (trx.offset[i]) {\n \t\tpart = &parts[curr_part++];\n \t\tpart->name = \"linux\";\n-\t\tpart->offset = trx.offset[i];\n+\t\tpart->offset = parser_trx_real_offset(mtd, trx.offset[i]);\n \t\ti++;\n \t}\n \n \tif (trx.offset[i]) {\n \t\tpart = &parts[curr_part++];\n-\t\tpart->name = parser_trx_data_part_name(mtd, trx.offset[i]);\n-\t\tpart->offset = trx.offset[i];\n+\t\tpart->offset = parser_trx_real_offset(mtd, trx.offset[i]);\n+\t\tpart->name = parser_trx_data_part_name(mtd, part->offset);\n \t\ti++;\n \t}\n \n"
  },
  {
    "path": "target/linux/generic/pending-5.15/432-mtd-bcm47xxpart-detect-T_Meter-partition.patch",
    "content": "From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <zajec5@gmail.com>\nSubject: mtd: bcm47xxpart: detect T_Meter partition\n\nIt can be found on many Netgear devices. It consists of many 0x30 blocks\nstarting with 4D 54.\n\nSigned-off-by: Rafał Miłecki <zajec5@gmail.com>\n---\n drivers/mtd/bcm47xxpart.c | 10 ++++++++++\n 1 file changed, 10 insertions(+)\n\n--- a/drivers/mtd/parsers/bcm47xxpart.c\n+++ b/drivers/mtd/parsers/bcm47xxpart.c\n@@ -35,6 +35,7 @@\n #define NVRAM_HEADER\t\t\t0x48534C46\t/* FLSH */\n #define POT_MAGIC1\t\t\t0x54544f50\t/* POTT */\n #define POT_MAGIC2\t\t\t0x504f\t\t/* OP */\n+#define T_METER_MAGIC\t\t\t0x4D540000\t/* MT */\n #define ML_MAGIC1\t\t\t0x39685a42\n #define ML_MAGIC2\t\t\t0x26594131\n #define TRX_MAGIC\t\t\t0x30524448\n@@ -178,6 +179,15 @@ static int bcm47xxpart_parse(struct mtd_\n \t\t\t\t\t     MTD_WRITEABLE);\n \t\t\tcontinue;\n \t\t}\n+\n+\t\t/* T_Meter */\n+\t\tif ((le32_to_cpu(buf[0x000 / 4]) & 0xFFFF0000) == T_METER_MAGIC &&\n+\t\t    (le32_to_cpu(buf[0x030 / 4]) & 0xFFFF0000) == T_METER_MAGIC &&\n+\t\t    (le32_to_cpu(buf[0x060 / 4]) & 0xFFFF0000) == T_METER_MAGIC) {\n+\t\t\tbcm47xxpart_add_part(&parts[curr_part++], \"T_Meter\", offset,\n+\t\t\t\t\t     MTD_WRITEABLE);\n+\t\t\tcontinue;\n+\t\t}\n \n \t\t/* TRX */\n \t\tif (buf[0x000 / 4] == TRX_MAGIC) {\n"
  },
  {
    "path": "target/linux/generic/pending-5.15/435-mtd-add-routerbootpart-parser-config.patch",
    "content": "From 4437e01fb6bca63fccdba5d6c44888b0935885c2 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Thibaut=20VAR=C3=88NE?= <hacks@slashdirt.org>\nDate: Tue, 24 Mar 2020 11:45:07 +0100\nSubject: [PATCH] generic: routerboot partition build bits (5.4)\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nThis patch adds routerbootpart kernel build bits\n\nSigned-off-by: Thibaut VARÈNE <hacks@slashdirt.org>\n---\n drivers/mtd/parsers/Kconfig  | 9 +++++++++\n drivers/mtd/parsers/Makefile | 1 +\n 2 files changed, 10 insertions(+)\n\n--- a/drivers/mtd/parsers/Kconfig\n+++ b/drivers/mtd/parsers/Kconfig\n@@ -202,3 +202,12 @@ config MTD_QCOMSMEM_PARTS\n \thelp\n \t  This provides support for parsing partitions from Shared Memory (SMEM)\n \t  for NAND and SPI flash on Qualcomm platforms.\n+\n+config MTD_ROUTERBOOT_PARTS\n+\ttristate \"RouterBoot flash partition parser\"\n+\tdepends on MTD && OF\n+\thelp\n+\t MikroTik RouterBoot is implemented as a multi segment system on the\n+\t flash, some of which are fixed and some of which are located at\n+\t variable offsets. This parser handles both cases via properly\n+\t formatted DTS.\n--- a/drivers/mtd/parsers/Makefile\n+++ b/drivers/mtd/parsers/Makefile\n@@ -14,3 +14,4 @@ obj-$(CONFIG_MTD_PARSER_TRX)\t\t+= parser_\n obj-$(CONFIG_MTD_SHARPSL_PARTS)\t\t+= sharpslpart.o\n obj-$(CONFIG_MTD_REDBOOT_PARTS)\t\t+= redboot.o\n obj-$(CONFIG_MTD_QCOMSMEM_PARTS)\t+= qcomsmempart.o\n+obj-$(CONFIG_MTD_ROUTERBOOT_PARTS)\t\t+= routerbootpart.o\n"
  },
  {
    "path": "target/linux/generic/pending-5.15/444-mtd-nand-rawnand-add-support-for-Toshiba-TC58NVG0S3H.patch",
    "content": "From 35ca7e3e6ccd120d694a3425f37fc6374ad2e11e Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Andreas=20B=C3=B6hler?= <dev@aboehler.at>\nDate: Wed, 20 Apr 2022 12:08:38 +0200\nSubject: [PATCH] mtd: rawnand: add support for Toshiba TC58NVG0S3HTA00\n NAND flash\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nThe Toshiba TC58NVG0S3HTA00 is detected with 64 byte OOB while the flash\nhas 128 bytes OOB. This adds a static NAND ID entry to correct this.\n\nTested on FRITZ!Box 7530 flashed with OpenWrt.\n\nSigned-off-by: Andreas Böhler <dev@aboehler.at>\n---\n drivers/mtd/nand/raw/nand_ids.c | 3 +++\n 1 file changed, 3 insertions(+)\n\ndiff --git a/drivers/mtd/nand/raw/nand_ids.c b/drivers/mtd/nand/raw/nand_ids.c\nindex 6e41902be35f..d64adbd1ce6b 100644\n--- a/drivers/mtd/nand/raw/nand_ids.c\n+++ b/drivers/mtd/nand/raw/nand_ids.c\n@@ -29,6 +29,9 @@ struct nand_flash_dev nand_flash_ids[] = {\n \t{\"TC58NVG0S3E 1G 3.3V 8-bit\",\n \t\t{ .id = {0x98, 0xd1, 0x90, 0x15, 0x76, 0x14, 0x01, 0x00} },\n \t\t  SZ_2K, SZ_128, SZ_128K, 0, 8, 64, NAND_ECC_INFO(1, SZ_512), },\n+\t{\"TC58NVG0S3HTA00 1G 3.3V 8-bit\",\n+\t\t{ .id = {0x98, 0xf1, 0x80, 0x15} },\n+\t\t  SZ_2K, SZ_128, SZ_128K, 0, 4, 128, NAND_ECC_INFO(8, SZ_512), },\n \t{\"TC58NVG2S0F 4G 3.3V 8-bit\",\n \t\t{ .id = {0x98, 0xdc, 0x90, 0x26, 0x76, 0x15, 0x01, 0x08} },\n \t\t  SZ_4K, SZ_512, SZ_256K, 0, 8, 224, NAND_ECC_INFO(4, SZ_512) },\n-- \n2.35.1\n\n"
  },
  {
    "path": "target/linux/generic/pending-5.15/460-mtd-cfi_cmdset_0002-no-erase_suspend.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nSubject: kernel: disable cfi cmdset 0002 erase suspend\n\non some platforms, erase suspend leads to data corruption and lockups when write\nops collide with erase ops. this has been observed on the buffalo wzr-hp-g300nh.\nrather than play whack-a-mole with a hard to reproduce issue on a variety of devices,\nsimply disable erase suspend, as it will usually not produce any useful gain on\nthe small filesystems used on embedded hardware.\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n drivers/mtd/chips/cfi_cmdset_0002.c | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/drivers/mtd/chips/cfi_cmdset_0002.c\n+++ b/drivers/mtd/chips/cfi_cmdset_0002.c\n@@ -914,7 +914,7 @@ static int get_chip(struct map_info *map\n \t\treturn 0;\n \n \tcase FL_ERASING:\n-\t\tif (!cfip || !(cfip->EraseSuspend & (0x1|0x2)) ||\n+\t\tif (1 /* no suspend */ || !cfip || !(cfip->EraseSuspend & (0x1|0x2)) ||\n \t\t    !(mode == FL_READY || mode == FL_POINT ||\n \t\t    (mode == FL_WRITING && (cfip->EraseSuspend & 0x2))))\n \t\t\tgoto sleep;\n"
  },
  {
    "path": "target/linux/generic/pending-5.15/461-mtd-cfi_cmdset_0002-add-buffer-write-cmd-timeout.patch",
    "content": "From: George Kashperko <george@znau.edu.ua>\nSubject: Issue map read after Write Buffer Load command to ensure chip is ready to receive data.\n\nSigned-off-by: George Kashperko <george@znau.edu.ua>\n---\n drivers/mtd/chips/cfi_cmdset_0002.c |    1 +\n 1 file changed, 1 insertion(+)\n--- a/drivers/mtd/chips/cfi_cmdset_0002.c\n+++ b/drivers/mtd/chips/cfi_cmdset_0002.c\n@@ -2058,6 +2058,7 @@ static int __xipram do_write_buffer(stru\n \n \t/* Write Buffer Load */\n \tmap_write(map, CMD(0x25), cmd_adr);\n+\t(void) map_read(map, cmd_adr);\n \n \tchip->state = FL_WRITING_TO_BUFFER;\n \n"
  },
  {
    "path": "target/linux/generic/pending-5.15/465-m25p80-mx-disable-software-protection.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nSubject: Disable software protection bits for Macronix flashes.\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n drivers/mtd/spi-nor/spi-nor.c | 1 +\n 1 file changed, 1 insertion(+)\n\n--- a/drivers/mtd/spi-nor/macronix.c\n+++ b/drivers/mtd/spi-nor/macronix.c\n@@ -93,6 +93,7 @@ static void macronix_default_init(struct\n {\n \tnor->params->quad_enable = spi_nor_sr1_bit6_quad_enable;\n \tnor->params->set_4byte_addr_mode = spi_nor_set_4byte_addr_mode;\n+\tnor->flags |= SNOR_F_HAS_LOCK;\n }\n \n static const struct spi_nor_fixups macronix_fixups = {\n"
  },
  {
    "path": "target/linux/generic/pending-5.15/470-mtd-spi-nor-support-limiting-4K-sectors-support-base.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nDate: Sat, 4 Nov 2017 07:40:23 +0100\nSubject: [PATCH] mtd: spi-nor: support limiting 4K sectors support based on\n flash size\n\nSome devices need 4K sectors to be able to deal with small flash chips.\nFor instance, w25x05 is 64 KiB in size, and without 4K sectors, the\nentire chip is just one erase block.\nOn bigger flash chip sizes, using 4K sectors can significantly slow down\nmany operations, including using a writable filesystem. There are several\nplatforms where it makes sense to use a single kernel on both kinds of\ndevices.\n\nTo support this properly, allow configuring an upper flash chip size\nlimit for 4K sectors support.\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n\n--- a/drivers/mtd/spi-nor/Kconfig\n+++ b/drivers/mtd/spi-nor/Kconfig\n@@ -78,6 +78,17 @@ config MTD_SPI_NOR_SWP_KEEP\n \n endchoice\n \n+config MTD_SPI_NOR_USE_4K_SECTORS_LIMIT\n+\tint \"Maximum flash chip size to use 4K sectors on (in KiB)\"\n+\tdepends on MTD_SPI_NOR_USE_4K_SECTORS\n+\tdefault \"4096\"\n+\thelp\n+\t  There are many flash chips that support 4K sectors, but are so large\n+\t  that using them significantly slows down writing large amounts of\n+\t  data or using a writable filesystem.\n+\t  Any flash chip larger than the size specified in this option will\n+\t  not use 4K sectors.\n+\n source \"drivers/mtd/spi-nor/controllers/Kconfig\"\n \n endif # MTD_SPI_NOR\n--- a/drivers/mtd/spi-nor/core.c\n+++ b/drivers/mtd/spi-nor/core.c\n@@ -2631,6 +2631,21 @@ static void spi_nor_info_init_params(str\n \t */\n \terase_mask = 0;\n \ti = 0;\n+#ifdef CONFIG_MTD_SPI_NOR_USE_4K_SECTORS\n+\tif ((info->flags & SECT_4K_PMC) && (params->size <=\n+\t\t   CONFIG_MTD_SPI_NOR_USE_4K_SECTORS_LIMIT * 1024)) {\n+\t\terase_mask |= BIT(i);\n+\t\tspi_nor_set_erase_type(&map->erase_type[i], 4096u,\n+\t\t\t\t       SPINOR_OP_BE_4K_PMC);\n+\t\ti++;\n+\t} else if ((info->flags & SECT_4K) && (params->size <=\n+\t    CONFIG_MTD_SPI_NOR_USE_4K_SECTORS_LIMIT * 1024)) {\n+\t\terase_mask |= BIT(i);\n+\t\tspi_nor_set_erase_type(&map->erase_type[i], 4096u,\n+\t\t\t\t       SPINOR_OP_BE_4K);\n+\t\ti++;\n+\t}\n+#else\n \tif (info->flags & SECT_4K_PMC) {\n \t\terase_mask |= BIT(i);\n \t\tspi_nor_set_erase_type(&map->erase_type[i], 4096u,\n@@ -2642,6 +2657,7 @@ static void spi_nor_info_init_params(str\n \t\t\t\t       SPINOR_OP_BE_4K);\n \t\ti++;\n \t}\n+#endif\n \terase_mask |= BIT(i);\n \tspi_nor_set_erase_type(&map->erase_type[i], info->sector_size,\n \t\t\t       SPINOR_OP_SE);\n"
  },
  {
    "path": "target/linux/generic/pending-5.15/476-mtd-spi-nor-add-eon-en25q128.patch",
    "content": "From: Piotr Dymacz <pepe2k@gmail.com>\nSubject: kernel/mtd: add support for EON EN25Q128\n\nSigned-off-by: Piotr Dymacz <pepe2k@gmail.com>\n---\n drivers/mtd/spi-nor/spi-nor.c | 1 +\n 1 file changed, 1 insertion(+)\n\n--- a/drivers/mtd/spi-nor/eon.c\n+++ b/drivers/mtd/spi-nor/eon.c\n@@ -15,6 +15,7 @@ static const struct flash_info eon_parts\n \t{ \"en25q32b\",   INFO(0x1c3016, 0, 64 * 1024,   64, 0) },\n \t{ \"en25p64\",    INFO(0x1c2017, 0, 64 * 1024,  128, 0) },\n \t{ \"en25q64\",    INFO(0x1c3017, 0, 64 * 1024,  128, SECT_4K) },\n+\t{ \"en25q128\",   INFO(0x1c3018, 0, 64 * 1024,  256, SECT_4K) },\n \t{ \"en25q80a\",   INFO(0x1c3014, 0, 64 * 1024,   16,\n \t\t\t     SECT_4K | SPI_NOR_DUAL_READ) },\n \t{ \"en25qh16\",   INFO(0x1c7015, 0, 64 * 1024,   32,\n"
  },
  {
    "path": "target/linux/generic/pending-5.15/479-mtd-spi-nor-add-xtx-xt25f128b.patch",
    "content": "From patchwork Thu Feb  6 17:19:41 2020\nContent-Type: text/plain; charset=\"utf-8\"\nMIME-Version: 1.0\nContent-Transfer-Encoding: 7bit\nX-Patchwork-Submitter: Daniel Golle <daniel@makrotopia.org>\nX-Patchwork-Id: 1234465\nDate: Thu, 6 Feb 2020 19:19:41 +0200\nFrom: Daniel Golle <daniel@makrotopia.org>\nTo: linux-mtd@lists.infradead.org\nSubject: [PATCH v2] mtd: spi-nor: Add support for xt25f128b chip\nMessage-ID: <20200206171941.GA2398@makrotopia.org>\nMIME-Version: 1.0\nContent-Disposition: inline\nList-Subscribe: <http://lists.infradead.org/mailman/listinfo/linux-mtd>,\n <mailto:linux-mtd-request@lists.infradead.org?subject=subscribe>\nCc: Eitan Cohen <eitan@neot-semadar.com>, Piotr Dymacz <pepe2k@gmail.com>,\n Tudor Ambarus <tudor.ambarus@microchip.com>\nSender: \"linux-mtd\" <linux-mtd-bounces@lists.infradead.org>\nErrors-To: linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org\n\nAdd XT25F128B made by XTX Technology (Shenzhen) Limited.\nThis chip supports dual and quad read and uniform 4K-byte erase.\nVerified on Teltonika RUT955 which comes with XT25F128B in recent\nversions of the device.\n\nSigned-off-by: Daniel Golle <daniel@makrotopia.org>\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n drivers/mtd/spi-nor/spi-nor.c | 4 ++++\n 1 file changed, 4 insertions(+)\n\n--- a/drivers/mtd/spi-nor/Makefile\n+++ b/drivers/mtd/spi-nor/Makefile\n@@ -17,6 +17,7 @@ spi-nor-objs\t\t\t+= sst.o\n spi-nor-objs\t\t\t+= winbond.o\n spi-nor-objs\t\t\t+= xilinx.o\n spi-nor-objs\t\t\t+= xmc.o\n+spi-nor-objs\t\t\t+= xtx.o\n obj-$(CONFIG_MTD_SPI_NOR)\t+= spi-nor.o\n \n obj-$(CONFIG_MTD_SPI_NOR)\t+= controllers/\n--- /dev/null\n+++ b/drivers/mtd/spi-nor/xtx.c\n@@ -0,0 +1,15 @@\n+// SPDX-License-Identifier: GPL-2.0\n+#include <linux/mtd/spi-nor.h>\n+\n+#include \"core.h\"\n+\n+static const struct flash_info xtx_parts[] = {\n+\t/* XTX Technology (Shenzhen) Limited */\n+\t{ \"xt25f128b\", INFO(0x0B4018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },\n+};\n+\n+const struct spi_nor_manufacturer spi_nor_xtx = {\n+\t.name = \"xtx\",\n+\t.parts = xtx_parts,\n+\t.nparts = ARRAY_SIZE(xtx_parts),\n+};\n--- a/drivers/mtd/spi-nor/core.c\n+++ b/drivers/mtd/spi-nor/core.c\n@@ -1848,6 +1848,7 @@ static const struct spi_nor_manufacturer\n \t&spi_nor_winbond,\n \t&spi_nor_xilinx,\n \t&spi_nor_xmc,\n+\t&spi_nor_xtx,\n };\n \n static const struct flash_info *\n--- a/drivers/mtd/spi-nor/core.h\n+++ b/drivers/mtd/spi-nor/core.h\n@@ -489,6 +489,7 @@ extern const struct spi_nor_manufacturer\n extern const struct spi_nor_manufacturer spi_nor_winbond;\n extern const struct spi_nor_manufacturer spi_nor_xilinx;\n extern const struct spi_nor_manufacturer spi_nor_xmc;\n+extern const struct spi_nor_manufacturer spi_nor_xtx;\n \n extern const struct attribute_group *spi_nor_sysfs_groups[];\n \n"
  },
  {
    "path": "target/linux/generic/pending-5.15/482-mtd-spi-nor-add-support-for-Gigadevice-GD25D05.patch",
    "content": "From d68b4aa22e8c625685bfad642dd7337948dc0ad1 Mon Sep 17 00:00:00 2001\nFrom: Koen Vandeputte <koen.vandeputte@ncentric.com>\nDate: Mon, 6 Jan 2020 13:07:56 +0100\nSubject: [PATCH] mtd: spi-nor: add support for Gigadevice GD25D05\n\nSigned-off-by: Koen Vandeputte <koen.vandeputte@ncentric.com>\n---\n drivers/mtd/spi-nor/spi-nor.c | 5 +++++\n 1 file changed, 5 insertions(+)\n\n--- a/drivers/mtd/spi-nor/gigadevice.c\n+++ b/drivers/mtd/spi-nor/gigadevice.c\n@@ -24,6 +24,9 @@ static struct spi_nor_fixups gd25q256_fi\n };\n \n static const struct flash_info gigadevice_parts[] = {\n+\t{ \"gd25q05\", INFO(0xc84010, 0, 64 * 1024,  1,\n+\t\t\t  SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |\n+\t\t\t  SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },\n \t{ \"gd25q16\", INFO(0xc84015, 0, 64 * 1024,  32,\n \t\t\t  SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |\n \t\t\t  SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },\n"
  },
  {
    "path": "target/linux/generic/pending-5.15/483-mtd-spi-nor-add-gd25q512.patch",
    "content": "--- a/drivers/mtd/spi-nor/gigadevice.c\n+++ b/drivers/mtd/spi-nor/gigadevice.c\n@@ -53,6 +53,9 @@ static const struct flash_info gigadevic\n \t\t\t   SPI_NOR_4B_OPCODES | SPI_NOR_HAS_LOCK |\n \t\t\t   SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6)\n \t\t.fixups = &gd25q256_fixups },\n+\t{ \"gd25q512\", INFO(0xc84020, 0, 64 * 1024, 1024,\n+\t\t\t   SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |\n+\t\t\t   SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4B_OPCODES) },\n };\n \n const struct spi_nor_manufacturer spi_nor_gigadevice = {\n"
  },
  {
    "path": "target/linux/generic/pending-5.15/483-mtd-spinand-add-support-for-xtx-xt26g0xa.patch",
    "content": "From a07e31adf2753cad2fd9790db5bfc047c81e8152 Mon Sep 17 00:00:00 2001\nFrom: Felix Matouschek <felix@matouschek.org>\nDate: Fri, 2 Jul 2021 20:31:23 +0200\nSubject: [PATCH] mtd: spinand: Add support for XTX XT26G0xA\n\nAdd support for XTX Technology XT26G01AXXXXX, XTX26G02AXXXXX and\nXTX26G04AXXXXX SPI NAND.\n\nThese are 3V, 1G/2G/4Gbit serial SLC NAND flash devices with on-die ECC\n(8bit strength per 512bytes).\n\nTested on Teltonika RUTX10 flashed with OpenWrt.\n\nDatasheets available at\nhttp://www.xtxtech.com/download/?AId=225\nhttps://datasheet.lcsc.com/szlcsc/2005251034_XTX-XT26G01AWSEGA_C558841.pdf\n\nSigned-off-by: Felix Matouschek <felix@matouschek.org>\n---\n drivers/mtd/nand/spi/Makefile |   2 +-\n drivers/mtd/nand/spi/core.c   |   1 +\n drivers/mtd/nand/spi/xtx.c    | 122 ++++++++++++++++++++++++++++++++++\n include/linux/mtd/spinand.h   |   1 +\n 4 files changed, 125 insertions(+), 1 deletion(-)\n create mode 100644 drivers/mtd/nand/spi/xtx.c\n\n--- a/drivers/mtd/nand/spi/Makefile\n+++ b/drivers/mtd/nand/spi/Makefile\n@@ -1,3 +1,3 @@\n # SPDX-License-Identifier: GPL-2.0\n-spinand-objs := core.o gigadevice.o macronix.o micron.o paragon.o toshiba.o winbond.o\n+spinand-objs := core.o gigadevice.o macronix.o micron.o paragon.o toshiba.o winbond.o xtx.o\n obj-$(CONFIG_MTD_SPI_NAND) += spinand.o\n--- a/drivers/mtd/nand/spi/core.c\n+++ b/drivers/mtd/nand/spi/core.c\n@@ -902,6 +902,7 @@ static const struct spinand_manufacturer\n \t&paragon_spinand_manufacturer,\n \t&toshiba_spinand_manufacturer,\n \t&winbond_spinand_manufacturer,\n+\t&xtx_spinand_manufacturer,\n };\n \n static int spinand_manufacturer_match(struct spinand_device *spinand,\n--- /dev/null\n+++ b/drivers/mtd/nand/spi/xtx.c\n@@ -0,0 +1,122 @@\n+// SPDX-License-Identifier: GPL-2.0\n+/*\n+ * Author:\n+ * Felix Matouschek <felix@matouschek.org>\n+ */\n+\n+#include <linux/device.h>\n+#include <linux/kernel.h>\n+#include <linux/mtd/spinand.h>\n+\n+#define SPINAND_MFR_XTX\t0x0B\n+\n+#define XT26G0XA_STATUS_ECC_MASK\tGENMASK(5, 2)\n+#define XT26G0XA_STATUS_ECC_NO_DETECTED\t(0 << 2)\n+#define XT26G0XA_STATUS_ECC_8_CORRECTED\t(3 << 4)\n+#define XT26G0XA_STATUS_ECC_UNCOR_ERROR\t(2 << 4)\n+\n+static SPINAND_OP_VARIANTS(read_cache_variants,\n+\t\tSPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 1, NULL, 0),\n+\t\tSPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),\n+\t\tSPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),\n+\t\tSPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),\n+\t\tSPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),\n+\t\tSPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));\n+\n+static SPINAND_OP_VARIANTS(write_cache_variants,\n+\t\tSPINAND_PROG_LOAD_X4(true, 0, NULL, 0),\n+\t\tSPINAND_PROG_LOAD(true, 0, NULL, 0));\n+\n+static SPINAND_OP_VARIANTS(update_cache_variants,\n+\t\tSPINAND_PROG_LOAD_X4(false, 0, NULL, 0),\n+\t\tSPINAND_PROG_LOAD(false, 0, NULL, 0));\n+\n+static int xt26g0xa_ooblayout_ecc(struct mtd_info *mtd, int section,\n+\t\t\t\t   struct mtd_oob_region *region)\n+{\n+\tif (section)\n+\t\treturn -ERANGE;\n+\n+\tregion->offset = 48;\n+\tregion->length = 16;\n+\n+\treturn 0;\n+}\n+\n+static int xt26g0xa_ooblayout_free(struct mtd_info *mtd, int section,\n+\t\t\t\t   struct mtd_oob_region *region)\n+{\n+\tif (section)\n+\t\treturn -ERANGE;\n+\n+\tregion->offset = 1;\n+\tregion->length = 47;\n+\n+\treturn 0;\n+}\n+\n+static const struct mtd_ooblayout_ops xt26g0xa_ooblayout = {\n+\t.ecc = xt26g0xa_ooblayout_ecc,\n+\t.free = xt26g0xa_ooblayout_free,\n+};\n+\n+static int xt26g0xa_ecc_get_status(struct spinand_device *spinand,\n+\t\t\t\t\t u8 status)\n+{\n+\tswitch (status & XT26G0XA_STATUS_ECC_MASK) {\n+\tcase XT26G0XA_STATUS_ECC_NO_DETECTED:\n+\t\treturn 0;\n+\tcase XT26G0XA_STATUS_ECC_8_CORRECTED:\n+\t\treturn 8;\n+\tcase XT26G0XA_STATUS_ECC_UNCOR_ERROR:\n+\t\treturn -EBADMSG;\n+\tdefault: /* (1 << 2) through (7 << 2) are 1-7 corrected errors */\n+\t\treturn (status & XT26G0XA_STATUS_ECC_MASK) >> 2;\n+\t}\n+\n+\treturn -EINVAL;\n+}\n+\n+static const struct spinand_info xtx_spinand_table[] = {\n+\tSPINAND_INFO(\"XT26G01A\",\n+\t\t     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xE1),\n+\t\t     NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),\n+\t\t     NAND_ECCREQ(8, 512),\n+\t\t     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,\n+\t\t\t\t\t      &write_cache_variants,\n+\t\t\t\t\t      &update_cache_variants),\n+\t\t     SPINAND_HAS_QE_BIT,\n+\t\t     SPINAND_ECCINFO(&xt26g0xa_ooblayout,\n+\t\t\t\t     xt26g0xa_ecc_get_status)),\n+\tSPINAND_INFO(\"XT26G02A\",\n+\t\t     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xE2),\n+\t\t     NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 1, 1, 1),\n+\t\t     NAND_ECCREQ(8, 512),\n+\t\t     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,\n+\t\t\t\t\t      &write_cache_variants,\n+\t\t\t\t\t      &update_cache_variants),\n+\t\t     SPINAND_HAS_QE_BIT,\n+\t\t     SPINAND_ECCINFO(&xt26g0xa_ooblayout,\n+\t\t\t\t     xt26g0xa_ecc_get_status)),\n+\tSPINAND_INFO(\"XT26G04A\",\n+\t\t     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xE3),\n+\t\t     NAND_MEMORG(1, 2048, 64, 128, 2048, 40, 1, 1, 1),\n+\t\t     NAND_ECCREQ(8, 512),\n+\t\t     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,\n+\t\t\t\t\t      &write_cache_variants,\n+\t\t\t\t\t      &update_cache_variants),\n+\t\t     SPINAND_HAS_QE_BIT,\n+\t\t     SPINAND_ECCINFO(&xt26g0xa_ooblayout,\n+\t\t\t\t     xt26g0xa_ecc_get_status)),\n+};\n+\n+static const struct spinand_manufacturer_ops xtx_spinand_manuf_ops = {\n+};\n+\n+const struct spinand_manufacturer xtx_spinand_manufacturer = {\n+\t.id = SPINAND_MFR_XTX,\n+\t.name = \"XTX\",\n+\t.chips = xtx_spinand_table,\n+\t.nchips = ARRAY_SIZE(xtx_spinand_table),\n+\t.ops = &xtx_spinand_manuf_ops,\n+};\n--- a/include/linux/mtd/spinand.h\n+++ b/include/linux/mtd/spinand.h\n@@ -266,6 +266,7 @@ extern const struct spinand_manufacturer\n extern const struct spinand_manufacturer paragon_spinand_manufacturer;\n extern const struct spinand_manufacturer toshiba_spinand_manufacturer;\n extern const struct spinand_manufacturer winbond_spinand_manufacturer;\n+extern const struct spinand_manufacturer xtx_spinand_manufacturer;\n \n /**\n  * struct spinand_op_variants - SPI NAND operation variants\n"
  },
  {
    "path": "target/linux/generic/pending-5.15/484-mtd-spi-nor-add-esmt-f25l16pa.patch",
    "content": "--- a/drivers/mtd/spi-nor/esmt.c\n+++ b/drivers/mtd/spi-nor/esmt.c\n@@ -10,6 +10,8 @@\n \n static const struct flash_info esmt_parts[] = {\n \t/* ESMT */\n+\t{ \"f25l16pa-2s\", INFO(0x8c2115, 0, 64 * 1024, 32,\n+\t\t\t   SECT_4K | SPI_NOR_HAS_LOCK) },\n \t{ \"f25l32pa\", INFO(0x8c2016, 0, 64 * 1024, 64,\n \t\t\t   SECT_4K | SPI_NOR_HAS_LOCK | SPI_NOR_SWP_IS_VOLATILE) },\n \t{ \"f25l32qa\", INFO(0x8c4116, 0, 64 * 1024, 64,\n"
  },
  {
    "path": "target/linux/generic/pending-5.15/485-mtd-spi-nor-add-xmc-xm25qh128c.patch",
    "content": "--- a/drivers/mtd/spi-nor/xmc.c\n+++ b/drivers/mtd/spi-nor/xmc.c\n@@ -14,6 +14,8 @@ static const struct flash_info xmc_parts\n \t\t\t    SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },\n \t{ \"XM25QH128A\", INFO(0x207018, 0, 64 * 1024, 256,\n \t\t\t     SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },\n+\t{ \"XM25QH128C\", INFO(0x204018, 0, 64 * 1024, 256,\n+\t\t\t     SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },\n };\n \n const struct spi_nor_manufacturer spi_nor_xmc = {\n"
  },
  {
    "path": "target/linux/generic/pending-5.15/486-01-mtd-spinand-add-support-for-ESMT-F50x1G41LB.patch",
    "content": "From a43b844cb40bf1b783055fdc81b7f991e21e7e76 Mon Sep 17 00:00:00 2001\nFrom: Chuanhong Guo <gch981213@gmail.com>\nDate: Wed, 13 Apr 2022 11:58:17 +0800\nSubject: [PATCH] mtd: spinand: add support for ESMT F50x1G41LB\n\nThis patch adds support for ESMT F50L1G41LB and F50D1G41LB.\nIt seems that ESMT likes to use random JEDEC ID from other vendors.\nTheir 1G chips uses 0xc8 from GigaDevice and 2G/4G chips uses 0x2c from\nMicron. For this reason, the ESMT entry is named esmt_c8 with explicit\nJEDEC ID in variable name.\n\nDatasheets:\nhttps://www.esmt.com.tw/upload/pdf/ESMT/datasheets/F50L1G41LB(2M).pdf\nhttps://www.esmt.com.tw/upload/pdf/ESMT/datasheets/F50D1G41LB(2M).pdf\n\nSigned-off-by: Chuanhong Guo <gch981213@gmail.com>\n---\n drivers/mtd/nand/spi/Makefile |  2 +-\n drivers/mtd/nand/spi/core.c   |  1 +\n drivers/mtd/nand/spi/esmt.c   | 89 +++++++++++++++++++++++++++++++++++\n include/linux/mtd/spinand.h   |  1 +\n 4 files changed, 92 insertions(+), 1 deletion(-)\n create mode 100644 drivers/mtd/nand/spi/esmt.c\n\n--- a/drivers/mtd/nand/spi/Makefile\n+++ b/drivers/mtd/nand/spi/Makefile\n@@ -1,3 +1,3 @@\n # SPDX-License-Identifier: GPL-2.0\n-spinand-objs := core.o gigadevice.o macronix.o micron.o paragon.o toshiba.o winbond.o xtx.o\n+spinand-objs := core.o esmt.o gigadevice.o macronix.o micron.o paragon.o toshiba.o winbond.o xtx.o\n obj-$(CONFIG_MTD_SPI_NAND) += spinand.o\n--- a/drivers/mtd/nand/spi/core.c\n+++ b/drivers/mtd/nand/spi/core.c\n@@ -896,6 +896,7 @@ static const struct nand_ops spinand_ops\n };\n \n static const struct spinand_manufacturer *spinand_manufacturers[] = {\n+\t&esmt_c8_spinand_manufacturer,\n \t&gigadevice_spinand_manufacturer,\n \t&macronix_spinand_manufacturer,\n \t&micron_spinand_manufacturer,\n--- /dev/null\n+++ b/drivers/mtd/nand/spi/esmt.c\n@@ -0,0 +1,89 @@\n+// SPDX-License-Identifier: GPL-2.0\n+/*\n+ * Author:\n+ *\tChuanhong Guo <gch981213@gmail.com>\n+ */\n+\n+#include <linux/device.h>\n+#include <linux/kernel.h>\n+#include <linux/mtd/spinand.h>\n+\n+/* ESMT uses GigaDevice 0xc8 JECDEC ID on some SPI NANDs */\n+#define SPINAND_MFR_ESMT_C8\t\t\t0xc8\n+\n+static SPINAND_OP_VARIANTS(read_cache_variants,\n+\t\t\t   SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),\n+\t\t\t   SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),\n+\t\t\t   SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),\n+\t\t\t   SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),\n+\t\t\t   SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),\n+\t\t\t   SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));\n+\n+static SPINAND_OP_VARIANTS(write_cache_variants,\n+\t\t\t   SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),\n+\t\t\t   SPINAND_PROG_LOAD(true, 0, NULL, 0));\n+\n+static SPINAND_OP_VARIANTS(update_cache_variants,\n+\t\t\t   SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),\n+\t\t\t   SPINAND_PROG_LOAD(false, 0, NULL, 0));\n+\n+static int f50l1g41lb_ooblayout_ecc(struct mtd_info *mtd, int section,\n+\t\t\t\t    struct mtd_oob_region *region)\n+{\n+\tif (section > 3)\n+\t\treturn -ERANGE;\n+\n+\tregion->offset = 16 * section + 8;\n+\tregion->length = 8;\n+\n+\treturn 0;\n+}\n+\n+static int f50l1g41lb_ooblayout_free(struct mtd_info *mtd, int section,\n+\t\t\t\t     struct mtd_oob_region *region)\n+{\n+\tif (section > 3)\n+\t\treturn -ERANGE;\n+\n+\tregion->offset = 16 * section + 2;\n+\tregion->length = 6;\n+\n+\treturn 0;\n+}\n+\n+static const struct mtd_ooblayout_ops f50l1g41lb_ooblayout = {\n+\t.ecc = f50l1g41lb_ooblayout_ecc,\n+\t.free = f50l1g41lb_ooblayout_free,\n+};\n+\n+static const struct spinand_info esmt_c8_spinand_table[] = {\n+\tSPINAND_INFO(\"F50L1G41LB\",\n+\t\t     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x01),\n+\t\t     NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),\n+\t\t     NAND_ECCREQ(1, 512),\n+\t\t     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,\n+\t\t\t\t\t      &write_cache_variants,\n+\t\t\t\t\t      &update_cache_variants),\n+\t\t     0,\n+\t\t     SPINAND_ECCINFO(&f50l1g41lb_ooblayout, NULL)),\n+\tSPINAND_INFO(\"F50D1G41LB\",\n+\t\t     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x11),\n+\t\t     NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),\n+\t\t     NAND_ECCREQ(1, 512),\n+\t\t     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,\n+\t\t\t\t\t      &write_cache_variants,\n+\t\t\t\t\t      &update_cache_variants),\n+\t\t     0,\n+\t\t     SPINAND_ECCINFO(&f50l1g41lb_ooblayout, NULL)),\n+};\n+\n+static const struct spinand_manufacturer_ops esmt_spinand_manuf_ops = {\n+};\n+\n+const struct spinand_manufacturer esmt_c8_spinand_manufacturer = {\n+\t.id = SPINAND_MFR_ESMT_C8,\n+\t.name = \"ESMT\",\n+\t.chips = esmt_c8_spinand_table,\n+\t.nchips = ARRAY_SIZE(esmt_c8_spinand_table),\n+\t.ops = &esmt_spinand_manuf_ops,\n+};\n--- a/include/linux/mtd/spinand.h\n+++ b/include/linux/mtd/spinand.h\n@@ -260,6 +260,7 @@ struct spinand_manufacturer {\n };\n \n /* SPI NAND manufacturers */\n+extern const struct spinand_manufacturer esmt_c8_spinand_manufacturer;\n extern const struct spinand_manufacturer gigadevice_spinand_manufacturer;\n extern const struct spinand_manufacturer macronix_spinand_manufacturer;\n extern const struct spinand_manufacturer micron_spinand_manufacturer;\n"
  },
  {
    "path": "target/linux/generic/pending-5.15/490-ubi-auto-attach-mtd-device-named-ubi-or-data-on-boot.patch",
    "content": "From: Daniel Golle <daniel@makrotopia.org>\nSubject: ubi: auto-attach mtd device named \"ubi\" or \"data\" on boot\n\nSigned-off-by: Daniel Golle <daniel@makrotopia.org>\n---\n drivers/mtd/ubi/build.c | 36 ++++++++++++++++++++++++++++++++++++\n 1 file changed, 36 insertions(+)\n\n--- a/drivers/mtd/ubi/build.c\n+++ b/drivers/mtd/ubi/build.c\n@@ -1184,6 +1184,73 @@ static struct mtd_info * __init open_mtd\n \treturn mtd;\n }\n \n+/*\n+ * This function tries attaching mtd partitions named either \"ubi\" or \"data\"\n+ * during boot.\n+ */\n+static void __init ubi_auto_attach(void)\n+{\n+\tint err;\n+\tstruct mtd_info *mtd;\n+\tloff_t offset = 0;\n+\tsize_t len;\n+\tchar magic[4];\n+\n+\t/* try attaching mtd device named \"ubi\" or \"data\" */\n+\tmtd = open_mtd_device(\"ubi\");\n+\tif (IS_ERR(mtd))\n+\t\tmtd = open_mtd_device(\"data\");\n+\n+\tif (IS_ERR(mtd))\n+\t\treturn;\n+\n+\t/* get the first not bad block */\n+\tif (mtd_can_have_bb(mtd))\n+\t\twhile (mtd_block_isbad(mtd, offset)) {\n+\t\t\toffset += mtd->erasesize;\n+\n+\t\t\tif (offset > mtd->size) {\n+\t\t\t\tpr_err(\"UBI error: Failed to find a non-bad \"\n+\t\t\t\t       \"block on mtd%d\\n\", mtd->index);\n+\t\t\t\tgoto cleanup;\n+\t\t\t}\n+\t\t}\n+\n+\t/* check if the read from flash was successful */\n+\terr = mtd_read(mtd, offset, 4, &len, (void *) magic);\n+\tif ((err && !mtd_is_bitflip(err)) || len != 4) {\n+\t\tpr_err(\"UBI error: unable to read from mtd%d\\n\", mtd->index);\n+\t\tgoto cleanup;\n+\t}\n+\n+\t/* check for a valid ubi magic */\n+\tif (strncmp(magic, \"UBI#\", 4)) {\n+\t\tpr_err(\"UBI error: no valid UBI magic found inside mtd%d\\n\", mtd->index);\n+\t\tgoto cleanup;\n+\t}\n+\n+\t/* don't auto-add media types where UBI doesn't makes sense */\n+\tif (mtd->type != MTD_NANDFLASH &&\n+\t    mtd->type != MTD_NORFLASH &&\n+\t    mtd->type != MTD_DATAFLASH &&\n+\t    mtd->type != MTD_MLCNANDFLASH)\n+\t\tgoto cleanup;\n+\n+\tmutex_lock(&ubi_devices_mutex);\n+\tpr_notice(\"UBI: auto-attach mtd%d\\n\", mtd->index);\n+\terr = ubi_attach_mtd_dev(mtd, UBI_DEV_NUM_AUTO, 0, 0);\n+\tmutex_unlock(&ubi_devices_mutex);\n+\tif (err < 0) {\n+\t\tpr_err(\"UBI error: cannot attach mtd%d\\n\", mtd->index);\n+\t\tgoto cleanup;\n+\t}\n+\n+\treturn;\n+\n+cleanup:\n+\tput_mtd_device(mtd);\n+}\n+\n static int __init ubi_init(void)\n {\n \tint err, i, k;\n@@ -1267,6 +1334,12 @@ static int __init ubi_init(void)\n \t\t}\n \t}\n \n+\t/* auto-attach mtd devices only if built-in to the kernel and no ubi.mtd\n+\t * parameter was given */\n+\tif (IS_ENABLED(CONFIG_MTD_ROOTFS_ROOT_DEV) &&\n+\t    !ubi_is_module() && !mtd_devs)\n+\t\tubi_auto_attach();\n+\n \terr = ubiblock_init();\n \tif (err) {\n \t\tpr_err(\"UBI error: block: cannot initialize, error %d\\n\", err);\n"
  },
  {
    "path": "target/linux/generic/pending-5.15/491-ubi-auto-create-ubiblock-device-for-rootfs.patch",
    "content": "From: Daniel Golle <daniel@makrotopia.org>\nSubject: ubi: auto-create ubiblock device for rootfs\n\nSigned-off-by: Daniel Golle <daniel@makrotopia.org>\n---\n drivers/mtd/ubi/block.c | 42 ++++++++++++++++++++++++++++++++++++++++++\n 1 file changed, 42 insertions(+)\n\n--- a/drivers/mtd/ubi/block.c\n+++ b/drivers/mtd/ubi/block.c\n@@ -642,6 +642,47 @@ static void __init ubiblock_create_from_\n \t}\n }\n \n+#define UBIFS_NODE_MAGIC  0x06101831\n+static inline int ubi_vol_is_ubifs(struct ubi_volume_desc *desc)\n+{\n+\tint ret;\n+\tuint32_t magic_of, magic;\n+\tret = ubi_read(desc, 0, (char *)&magic_of, 0, 4);\n+\tif (ret)\n+\t\treturn 0;\n+\tmagic = le32_to_cpu(magic_of);\n+\treturn magic == UBIFS_NODE_MAGIC;\n+}\n+\n+static void __init ubiblock_create_auto_rootfs(void)\n+{\n+\tint ubi_num, ret, is_ubifs;\n+\tstruct ubi_volume_desc *desc;\n+\tstruct ubi_volume_info vi;\n+\n+\tfor (ubi_num = 0; ubi_num < UBI_MAX_DEVICES; ubi_num++) {\n+\t\tdesc = ubi_open_volume_nm(ubi_num, \"rootfs\", UBI_READONLY);\n+\t\tif (IS_ERR(desc))\n+\t\t\tdesc = ubi_open_volume_nm(ubi_num, \"fit\", UBI_READONLY);;\n+\n+\t\tif (IS_ERR(desc))\n+\t\t\tcontinue;\n+\n+\t\tubi_get_volume_info(desc, &vi);\n+\t\tis_ubifs = ubi_vol_is_ubifs(desc);\n+\t\tubi_close_volume(desc);\n+\t\tif (is_ubifs)\n+\t\t\tbreak;\n+\n+\t\tret = ubiblock_create(&vi);\n+\t\tif (ret)\n+\t\t\tpr_err(\"UBI error: block: can't add '%s' volume, err=%d\\n\",\n+\t\t\t\tvi.name, ret);\n+\t\t/* always break if we get here */\n+\t\tbreak;\n+\t}\n+}\n+\n static void ubiblock_remove_all(void)\n {\n \tstruct ubiblock *next;\n@@ -674,6 +715,10 @@ int __init ubiblock_init(void)\n \t */\n \tubiblock_create_from_param();\n \n+\t/* auto-attach \"rootfs\" volume if existing and non-ubifs */\n+\tif (IS_ENABLED(CONFIG_MTD_ROOTFS_ROOT_DEV))\n+\t\tubiblock_create_auto_rootfs();\n+\n \t/*\n \t * Block devices are only created upon user requests, so we ignore\n \t * existing volumes.\n"
  },
  {
    "path": "target/linux/generic/pending-5.15/492-try-auto-mounting-ubi0-rootfs-in-init-do_mounts.c.patch",
    "content": "From: Daniel Golle <daniel@makrotopia.org>\nSubject: try auto-mounting ubi0:rootfs in init/do_mounts.c\n\nSigned-off-by: Daniel Golle <daniel@makrotopia.org>\n---\n init/do_mounts.c | 26 +++++++++++++++++++++++++-\n 1 file changed, 25 insertions(+), 1 deletion(-)\n\n--- a/init/do_mounts.c\n+++ b/init/do_mounts.c\n@@ -447,7 +447,30 @@ retry:\n out:\n \tput_page(page);\n }\n- \n+\n+#ifdef CONFIG_MTD_ROOTFS_ROOT_DEV\n+static int __init mount_ubi_rootfs(void)\n+{\n+\tint flags = MS_SILENT;\n+\tint err, tried = 0;\n+\n+\twhile (tried < 2) {\n+\t\terr = do_mount_root(\"ubi0:rootfs\", \"ubifs\", flags, \\\n+\t\t\t\t\troot_mount_data);\n+\t\tswitch (err) {\n+\t\t\tcase -EACCES:\n+\t\t\t\tflags |= MS_RDONLY;\n+\t\t\t\ttried++;\n+\t\t\t\tbreak;\n+\t\t\tdefault:\n+\t\t\t\treturn err;\n+\t\t}\n+\t}\n+\n+\treturn -EINVAL;\n+}\n+#endif\n+\n #ifdef CONFIG_ROOT_NFS\n \n #define NFSROOT_TIMEOUT_MIN\t5\n@@ -580,6 +603,10 @@ void __init mount_root(void)\n \t\treturn;\n \t}\n #endif\n+#ifdef CONFIG_MTD_ROOTFS_ROOT_DEV\n+\tif (!mount_ubi_rootfs())\n+\t\treturn;\n+#endif\n \tif (ROOT_DEV == 0 && root_device_name && root_fs_names) {\n \t\tif (mount_nodev_root() == 0)\n \t\t\treturn;\n"
  },
  {
    "path": "target/linux/generic/pending-5.15/493-ubi-set-ROOT_DEV-to-ubiblock-rootfs-if-unset.patch",
    "content": "From: Daniel Golle <daniel@makrotopia.org>\nSubject: ubi: set ROOT_DEV to ubiblock \"rootfs\" if unset\n\nSigned-off-by: Daniel Golle <daniel@makrotopia.org>\n---\n drivers/mtd/ubi/block.c | 10 ++++++++++\n 1 file changed, 10 insertions(+)\n\n--- a/drivers/mtd/ubi/block.c\n+++ b/drivers/mtd/ubi/block.c\n@@ -42,6 +42,7 @@\n #include <linux/scatterlist.h>\n #include <linux/idr.h>\n #include <asm/div64.h>\n+#include <linux/root_dev.h>\n \n #include \"ubi-media.h\"\n #include \"ubi.h\"\n@@ -451,6 +452,15 @@ int ubiblock_create(struct ubi_volume_in\n \tdev_info(disk_to_dev(dev->gd), \"created from ubi%d:%d(%s)\",\n \t\t dev->ubi_num, dev->vol_id, vi->name);\n \tmutex_unlock(&devices_mutex);\n+\n+\tif (!strcmp(vi->name, \"rootfs\") &&\n+\t    IS_ENABLED(CONFIG_MTD_ROOTFS_ROOT_DEV) &&\n+\t    ROOT_DEV == 0) {\n+\t\tpr_notice(\"ubiblock: device ubiblock%d_%d (%s) set to be root filesystem\\n\",\n+\t\t\t  dev->ubi_num, dev->vol_id, vi->name);\n+\t\tROOT_DEV = MKDEV(gd->major, gd->first_minor);\n+\t}\n+\n \treturn 0;\n \n out_remove_minor:\n"
  },
  {
    "path": "target/linux/generic/pending-5.15/494-mtd-ubi-add-EOF-marker-support.patch",
    "content": "From: Gabor Juhos <juhosg@openwrt.org>\nSubject: mtd: add EOF marker support to the UBI layer\n\nSigned-off-by: Gabor Juhos <juhosg@openwrt.org>\n---\n drivers/mtd/ubi/attach.c | 25 ++++++++++++++++++++++---\n drivers/mtd/ubi/ubi.h    |  1 +\n 2 files changed, 23 insertions(+), 3 deletions(-)\n\n--- a/drivers/mtd/ubi/attach.c\n+++ b/drivers/mtd/ubi/attach.c\n@@ -926,6 +926,13 @@ static bool vol_ignored(int vol_id)\n #endif\n }\n \n+static bool ec_hdr_has_eof(struct ubi_ec_hdr *ech)\n+{\n+\treturn ech->padding1[0] == 'E' &&\n+\t       ech->padding1[1] == 'O' &&\n+\t       ech->padding1[2] == 'F';\n+}\n+\n /**\n  * scan_peb - scan and process UBI headers of a PEB.\n  * @ubi: UBI device description object\n@@ -958,9 +965,21 @@ static int scan_peb(struct ubi_device *u\n \t\treturn 0;\n \t}\n \n-\terr = ubi_io_read_ec_hdr(ubi, pnum, ech, 0);\n-\tif (err < 0)\n-\t\treturn err;\n+\tif (!ai->eof_found) {\n+\t\terr = ubi_io_read_ec_hdr(ubi, pnum, ech, 0);\n+\t\tif (err < 0)\n+\t\t\treturn err;\n+\n+\t\tif (ec_hdr_has_eof(ech)) {\n+\t\t\tpr_notice(\"UBI: EOF marker found, PEBs from %d will be erased\\n\",\n+\t\t\t\tpnum);\n+\t\t\tai->eof_found = true;\n+\t\t}\n+\t}\n+\n+\tif (ai->eof_found)\n+\t\terr = UBI_IO_FF_BITFLIPS;\n+\n \tswitch (err) {\n \tcase 0:\n \t\tbreak;\n--- a/drivers/mtd/ubi/ubi.h\n+++ b/drivers/mtd/ubi/ubi.h\n@@ -780,6 +780,7 @@ struct ubi_attach_info {\n \tint mean_ec;\n \tuint64_t ec_sum;\n \tint ec_count;\n+\tbool eof_found;\n \tstruct kmem_cache *aeb_slab_cache;\n \tstruct ubi_ec_hdr *ech;\n \tstruct ubi_vid_io_buf *vidb;\n"
  },
  {
    "path": "target/linux/generic/pending-5.15/495-mtd-core-add-get_mtd_device_by_node.patch",
    "content": "From 1bd1b740f208d1cf4071932cc51860d37266c402 Mon Sep 17 00:00:00 2001\nFrom: Bernhard Frauendienst <kernel@nospam.obeliks.de>\nDate: Sat, 1 Sep 2018 00:30:11 +0200\nSubject: [PATCH 495/497] mtd: core: add get_mtd_device_by_node\n\nAdd function to retrieve a mtd device by its OF node. Since drivers can\nassign arbitrary names to mtd devices in the absence of a label\nproperty, there is no other reliable way to retrieve a mtd device for a\ngiven OF node.\n\nSigned-off-by: Bernhard Frauendienst <kernel@nospam.obeliks.de>\nReviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>\n---\n drivers/mtd/mtdcore.c   | 38 ++++++++++++++++++++++++++++++++++++++\n include/linux/mtd/mtd.h |  2 ++\n 2 files changed, 40 insertions(+)\n\n--- a/drivers/mtd/mtdcore.c\n+++ b/drivers/mtd/mtdcore.c\n@@ -1203,6 +1203,44 @@ out_unlock:\n }\n EXPORT_SYMBOL_GPL(get_mtd_device_nm);\n \n+/**\n+ *\tget_mtd_device_by_node - obtain a validated handle for an MTD device\n+ *\tby of_node\n+ *\t@of_node: OF node of MTD device to open\n+ *\n+ *\tThis function returns MTD device description structure in case of\n+ *\tsuccess and an error code in case of failure.\n+ */\n+struct mtd_info *get_mtd_device_by_node(const struct device_node *of_node)\n+{\n+\tint err = -ENODEV;\n+\tstruct mtd_info *mtd = NULL, *other;\n+\n+\tmutex_lock(&mtd_table_mutex);\n+\n+\tmtd_for_each_device(other) {\n+\t\tif (of_node == other->dev.of_node) {\n+\t\t\tmtd = other;\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\n+\tif (!mtd)\n+\t\tgoto out_unlock;\n+\n+\terr = __get_mtd_device(mtd);\n+\tif (err)\n+\t\tgoto out_unlock;\n+\n+\tmutex_unlock(&mtd_table_mutex);\n+\treturn mtd;\n+\n+out_unlock:\n+\tmutex_unlock(&mtd_table_mutex);\n+\treturn ERR_PTR(err);\n+}\n+EXPORT_SYMBOL_GPL(get_mtd_device_by_node);\n+\n void put_mtd_device(struct mtd_info *mtd)\n {\n \tmutex_lock(&mtd_table_mutex);\n--- a/include/linux/mtd/mtd.h\n+++ b/include/linux/mtd/mtd.h\n@@ -703,6 +703,8 @@ extern struct mtd_info *get_mtd_device(s\n extern int __get_mtd_device(struct mtd_info *mtd);\n extern void __put_mtd_device(struct mtd_info *mtd);\n extern struct mtd_info *get_mtd_device_nm(const char *name);\n+extern struct mtd_info *get_mtd_device_by_node(\n+\t\tconst struct device_node *of_node);\n extern void put_mtd_device(struct mtd_info *mtd);\n \n static inline uint64_t mtdpart_get_offset(const struct mtd_info *mtd)\n"
  },
  {
    "path": "target/linux/generic/pending-5.15/496-dt-bindings-add-bindings-for-mtd-concat-devices.patch",
    "content": "From 5734c6669fba7ddb5ef491ccff7159d15dba0b59 Mon Sep 17 00:00:00 2001\nFrom: Bernhard Frauendienst <kernel@nospam.obeliks.de>\nDate: Wed, 5 Sep 2018 01:32:51 +0200\nSubject: [PATCH 496/497] dt-bindings: add bindings for mtd-concat devices\n\nDocument virtual mtd-concat device bindings.\n\nSigned-off-by: Bernhard Frauendienst <kernel@nospam.obeliks.de>\n---\n .../devicetree/bindings/mtd/mtd-concat.txt    | 36 +++++++++++++++++++\n 1 file changed, 36 insertions(+)\n create mode 100644 Documentation/devicetree/bindings/mtd/mtd-concat.txt\n\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/mtd/mtd-concat.txt\n@@ -0,0 +1,36 @@\n+Virtual MTD concat device\n+\n+Requires properties:\n+- devices: list of phandles to mtd nodes that should be concatenated\n+\n+Example:\n+\n+&spi {\n+\tflash0: flash@0 {\n+\t\t...\n+\t};\n+\tflash1: flash@1 {\n+\t\t...\n+\t};\n+};\n+\n+flash {\n+\tcompatible = \"mtd-concat\";\n+\n+\tdevices = <&flash0 &flash1>;\n+\n+\tpartitions {\n+\t\tcompatible = \"fixed-partitions\";\n+\n+\t\tpartition@0 {\n+\t\t\tlabel = \"boot\";\n+\t\t\treg = <0x0000000 0x0040000>;\n+\t\t\tread-only;\n+\t\t};\n+\n+\t\tpartition@40000 {\n+\t\t\tlabel = \"firmware\";\n+\t\t\treg = <0x0040000 0x1fc0000>;\n+\t\t};\n+\t}\n+}\n"
  },
  {
    "path": "target/linux/generic/pending-5.15/497-mtd-mtdconcat-add-dt-driver-for-concat-devices.patch",
    "content": "From e53f712d8eac71f54399b61038ccf87d2cee99d7 Mon Sep 17 00:00:00 2001\nFrom: Bernhard Frauendienst <kernel@nospam.obeliks.de>\nDate: Sat, 25 Aug 2018 12:35:22 +0200\nSubject: [PATCH 497/497] mtd: mtdconcat: add dt driver for concat devices\n\nSome mtd drivers like physmap variants have support for concatenating\nmultiple mtd devices, but there is no generic way to define such a\nconcat device from within the device tree.\n\nThis is useful for some SoC boards that use multiple flash chips as\nmemory banks of a single mtd device, with partitions spanning chip\nborders.\n\nThis commit adds a driver for creating virtual mtd-concat devices. They\nmust have a compatible = \"mtd-concat\" line, and define a list of devices\nto concat in the 'devices' property, for example:\n\nflash {\n  compatible = \"mtd-concat\";\n\n  devices = <&flash0 &flash1>;\n\n  partitions {\n    ...\n  };\n};\n\nThe driver is added to the very end of the mtd Makefile to increase the\nlikelyhood of all child devices already being loaded at the time of\nprobing, preventing unnecessary deferred probes.\n\nSigned-off-by: Bernhard Frauendienst <kernel@nospam.obeliks.de>\n---\n drivers/mtd/Kconfig                 |   2 +\n drivers/mtd/Makefile                |   3 +\n drivers/mtd/composite/Kconfig       |  12 +++\n drivers/mtd/composite/Makefile      |   6 ++\n drivers/mtd/composite/virt_concat.c | 128 ++++++++++++++++++++++++++++\n 5 files changed, 151 insertions(+)\n create mode 100644 drivers/mtd/composite/Kconfig\n create mode 100644 drivers/mtd/composite/Makefile\n create mode 100644 drivers/mtd/composite/virt_concat.c\n\n--- a/drivers/mtd/Kconfig\n+++ b/drivers/mtd/Kconfig\n@@ -241,4 +241,6 @@ source \"drivers/mtd/ubi/Kconfig\"\n \n source \"drivers/mtd/hyperbus/Kconfig\"\n \n+source \"drivers/mtd/composite/Kconfig\"\n+\n endif # MTD\n--- a/drivers/mtd/Makefile\n+++ b/drivers/mtd/Makefile\n@@ -33,3 +33,6 @@ obj-y\t\t+= chips/ lpddr/ maps/ devices/ n\n obj-$(CONFIG_MTD_SPI_NOR)\t+= spi-nor/\n obj-$(CONFIG_MTD_UBI)\t\t+= ubi/\n obj-$(CONFIG_MTD_HYPERBUS)\t+= hyperbus/\n+\n+# Composite drivers must be loaded last\n+obj-y\t\t\t\t+= composite/\n--- /dev/null\n+++ b/drivers/mtd/composite/Kconfig\n@@ -0,0 +1,12 @@\n+menu \"Composite MTD device drivers\"\n+\tdepends on MTD!=n\n+\n+config MTD_VIRT_CONCAT\n+\ttristate \"Virtual concat MTD device\"\n+\thelp\n+\t  This driver allows creation of a virtual MTD concat device, which\n+\t  concatenates multiple underlying MTD devices to a single device.\n+\t  This is required by some SoC boards where multiple memory banks are\n+\t  used as one device with partitions spanning across device boundaries.\n+\n+endmenu\n--- /dev/null\n+++ b/drivers/mtd/composite/Makefile\n@@ -0,0 +1,6 @@\n+# SPDX-License-Identifier: GPL-2.0\n+#\n+# linux/drivers/mtd/composite/Makefile\n+#\n+\n+obj-$(CONFIG_MTD_VIRT_CONCAT)   += virt_concat.o\n--- /dev/null\n+++ b/drivers/mtd/composite/virt_concat.c\n@@ -0,0 +1,128 @@\n+// SPDX-License-Identifier: GPL-2.0+\n+/*\n+ * Virtual concat MTD device driver\n+ *\n+ * Copyright (C) 2018 Bernhard Frauendienst\n+ * Author: Bernhard Frauendienst, kernel@nospam.obeliks.de\n+ */\n+\n+#include <linux/module.h>\n+#include <linux/device.h>\n+#include <linux/mtd/concat.h>\n+#include <linux/mtd/mtd.h>\n+#include <linux/mtd/partitions.h>\n+#include <linux/of.h>\n+#include <linux/of_platform.h>\n+#include <linux/slab.h>\n+\n+/*\n+ * struct of_virt_concat - platform device driver data.\n+ * @cmtd the final mtd_concat device\n+ * @num_devices the number of devices in @devices\n+ * @devices points to an array of devices already loaded\n+ */\n+struct of_virt_concat {\n+\tstruct mtd_info\t*cmtd;\n+\tint num_devices;\n+\tstruct mtd_info\t**devices;\n+};\n+\n+static int virt_concat_remove(struct platform_device *pdev)\n+{\n+\tstruct of_virt_concat *info;\n+\tint i;\n+\n+\tinfo = platform_get_drvdata(pdev);\n+\tif (!info)\n+\t\treturn 0;\n+\n+\t// unset data for when this is called after a probe error\n+\tplatform_set_drvdata(pdev, NULL);\n+\n+\tif (info->cmtd) {\n+\t\tmtd_device_unregister(info->cmtd);\n+\t\tmtd_concat_destroy(info->cmtd);\n+\t}\n+\n+\tif (info->devices) {\n+\t\tfor (i = 0; i < info->num_devices; i++)\n+\t\t\tput_mtd_device(info->devices[i]);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int virt_concat_probe(struct platform_device *pdev)\n+{\n+\tstruct device_node *node = pdev->dev.of_node;\n+\tstruct of_phandle_iterator it;\n+\tstruct of_virt_concat *info;\n+\tstruct mtd_info *mtd;\n+\tint err = 0, count;\n+\n+\tcount = of_count_phandle_with_args(node, \"devices\", NULL);\n+\tif (count <= 0)\n+\t\treturn -EINVAL;\n+\n+\tinfo = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);\n+\tif (!info)\n+\t\treturn -ENOMEM;\n+\tinfo->devices = devm_kcalloc(&pdev->dev, count,\n+\t\t\t\t     sizeof(*(info->devices)), GFP_KERNEL);\n+\tif (!info->devices) {\n+\t\terr = -ENOMEM;\n+\t\tgoto err_remove;\n+\t}\n+\n+\tplatform_set_drvdata(pdev, info);\n+\n+\tof_for_each_phandle(&it, err, node, \"devices\", NULL, 0) {\n+\t\tmtd = get_mtd_device_by_node(it.node);\n+\t\tif (IS_ERR(mtd)) {\n+\t\t\tof_node_put(it.node);\n+\t\t\terr = -EPROBE_DEFER;\n+\t\t\tgoto err_remove;\n+\t\t}\n+\n+\t\tinfo->devices[info->num_devices++] = mtd;\n+\t}\n+\n+\tinfo->cmtd = mtd_concat_create(info->devices, info->num_devices,\n+\t\t\t\t       dev_name(&pdev->dev));\n+\tif (!info->cmtd) {\n+\t\terr = -ENXIO;\n+\t\tgoto err_remove;\n+\t}\n+\n+\tinfo->cmtd->dev.parent = &pdev->dev;\n+\tmtd_set_of_node(info->cmtd, node);\n+\tmtd_device_register(info->cmtd, NULL, 0);\n+\n+\treturn 0;\n+\n+err_remove:\n+\tvirt_concat_remove(pdev);\n+\n+\treturn err;\n+}\n+\n+static const struct of_device_id virt_concat_of_match[] = {\n+\t{ .compatible = \"mtd-concat\", },\n+\t{ /* sentinel */ }\n+};\n+MODULE_DEVICE_TABLE(of, virt_concat_of_match);\n+\n+static struct platform_driver virt_concat_driver = {\n+\t.probe = virt_concat_probe,\n+\t.remove = virt_concat_remove,\n+\t.driver\t = {\n+\t\t.name   = \"virt-mtdconcat\",\n+\t\t.of_match_table = virt_concat_of_match,\n+\t},\n+};\n+\n+module_platform_driver(virt_concat_driver);\n+\n+MODULE_LICENSE(\"GPL v2\");\n+MODULE_AUTHOR(\"Bernhard Frauendienst <kernel@nospam.obeliks.de>\");\n+MODULE_DESCRIPTION(\"Virtual concat MTD device driver\");\n"
  },
  {
    "path": "target/linux/generic/pending-5.15/498-mtd-spi-nor-locking-support-for-MX25L6405D.patch",
    "content": "From 8bf2ce6ea4ee840b70f55a27f80e1cd308051b13 Mon Sep 17 00:00:00 2001\nFrom: Nick Hainke <vincent@systemli.org>\nDate: Mon, 27 Dec 2021 00:38:13 +0100\nSubject: [PATCH 1/2] mtd: spi-nor: locking support for MX25L6405D\n\nMacronix MX25L6405D supports locking with four block-protection bits.\nCurrently, the driver only sets three bits.  If the bootloader does not\nsustain the flash chip in an unlocked state, the flash might be\nnon-writeable. Add the corresponding flag to enable locking support with\nfour bits in the status register.\n\nTested on Nanostation M2 XM.\n\nSimilar to commit 7ea40b54e83b (\"mtd: spi-nor: enable locking support for\nMX25L12805D\")\n\nSigned-off-by: David Bauer <mail@david-bauer.net>\nSigned-off-by: Nick Hainke <vincent@systemli.org>\n---\n drivers/mtd/spi-nor/macronix.c | 3 ++-\n 1 file changed, 2 insertions(+), 1 deletion(-)\n\n--- a/drivers/mtd/spi-nor/macronix.c\n+++ b/drivers/mtd/spi-nor/macronix.c\n@@ -41,7 +41,8 @@ static const struct flash_info macronix_\n \t{ \"mx25l1606e\",  INFO(0xc22015, 0, 64 * 1024,  32, SECT_4K) },\n \t{ \"mx25l3205d\",  INFO(0xc22016, 0, 64 * 1024,  64, SECT_4K) },\n \t{ \"mx25l3255e\",  INFO(0xc29e16, 0, 64 * 1024,  64, SECT_4K) },\n-\t{ \"mx25l6405d\",  INFO(0xc22017, 0, 64 * 1024, 128, SECT_4K) },\n+\t{ \"mx25l6405d\",  INFO(0xc22017, 0, 64 * 1024, 128, SECT_4K |\n+\t\t\t      SPI_NOR_HAS_LOCK | SPI_NOR_4BIT_BP) },\n \t{ \"mx25u2033e\",  INFO(0xc22532, 0, 64 * 1024,   4, SECT_4K) },\n \t{ \"mx25u3235f\",\t INFO(0xc22536, 0, 64 * 1024,  64,\n \t\t\t      SECT_4K | SPI_NOR_DUAL_READ |\n"
  },
  {
    "path": "target/linux/generic/pending-5.15/499-mtd-spi-nor-disable-16-bit-sr-for-macronix.patch",
    "content": "From 245224608b5368c10407da07557e546743d3c489 Mon Sep 17 00:00:00 2001\nFrom: Nick Hainke <vincent@systemli.org>\nDate: Mon, 27 Dec 2021 09:33:13 +0100\nSubject: [PATCH 2/2] mtd: spi-nor: disable 16-bit-sr for macronix\n\nMacronix flash chips seem to consist of only one status register.\nThese chips will not work with the \"16-bit Write Status (01h) Command\".\nDisable SNOR_F_HAS_16BIT_SR for all Macronix chips.\n\nTested with MX25L6405D.\n\nFixes: 39d1e3340c73 (\"mtd: spi-nor: Fix clearing of QE bit on\nlock()/unlock()\")\n\nSigned-off-by: David Bauer <mail@david-bauer.net>\nSigned-off-by: Nick Hainke <vincent@systemli.org>\n---\n drivers/mtd/spi-nor/macronix.c | 1 +\n 1 file changed, 1 insertion(+)\n\n--- a/drivers/mtd/spi-nor/macronix.c\n+++ b/drivers/mtd/spi-nor/macronix.c\n@@ -94,6 +94,7 @@ static void macronix_default_init(struct\n {\n \tnor->params->quad_enable = spi_nor_sr1_bit6_quad_enable;\n \tnor->params->set_4byte_addr_mode = spi_nor_set_4byte_addr_mode;\n+\tnor->flags &= ~SNOR_F_HAS_16BIT_SR;\n \tnor->flags |= SNOR_F_HAS_LOCK;\n }\n \n"
  },
  {
    "path": "target/linux/generic/pending-5.15/500-fs_cdrom_dependencies.patch",
    "content": "--- a/fs/hfs/Kconfig\n+++ b/fs/hfs/Kconfig\n@@ -2,6 +2,7 @@\n config HFS_FS\n \ttristate \"Apple Macintosh file system support\"\n \tdepends on BLOCK\n+\tselect CDROM\n \tselect NLS\n \thelp\n \t  If you say Y here, you will be able to mount Macintosh-formatted\n--- a/fs/hfsplus/Kconfig\n+++ b/fs/hfsplus/Kconfig\n@@ -2,6 +2,7 @@\n config HFSPLUS_FS\n \ttristate \"Apple Extended HFS file system support\"\n \tdepends on BLOCK\n+\tselect CDROM\n \tselect NLS\n \tselect NLS_UTF8\n \thelp\n--- a/fs/isofs/Kconfig\n+++ b/fs/isofs/Kconfig\n@@ -1,6 +1,7 @@\n # SPDX-License-Identifier: GPL-2.0-only\n config ISO9660_FS\n \ttristate \"ISO 9660 CDROM file system support\"\n+\tselect CDROM\n \thelp\n \t  This is the standard file system used on CD-ROMs.  It was previously\n \t  known as \"High Sierra File System\" and is called \"hsfs\" on other\n--- a/fs/udf/Kconfig\n+++ b/fs/udf/Kconfig\n@@ -1,6 +1,7 @@\n # SPDX-License-Identifier: GPL-2.0-only\n config UDF_FS\n \ttristate \"UDF file system support\"\n+\tselect CDROM\n \tselect CRC_ITU_T\n \tselect NLS\n \thelp\n"
  },
  {
    "path": "target/linux/generic/pending-5.15/530-jffs2_make_lzma_available.patch",
    "content": "From: Alexandros C. Couloumbis <alex@ozo.com>\nSubject: fs: add jffs2/lzma support (not activated by default yet)\n\nlede-commit: c2c88d315fa0e881f8b19da07b62859b915b11b2\nSigned-off-by: Alexandros C. Couloumbis <alex@ozo.com>\n---\n fs/jffs2/Kconfig             |    9 +\n fs/jffs2/Makefile            |    3 +\n fs/jffs2/compr.c             |    6 +\n fs/jffs2/compr.h             |   10 +-\n fs/jffs2/compr_lzma.c        |  128 +++\n fs/jffs2/super.c             |   33 +-\n include/linux/lzma.h         |   62 ++\n include/linux/lzma/LzFind.h  |  115 +++\n include/linux/lzma/LzHash.h  |   54 +\n include/linux/lzma/LzmaDec.h |  231 +++++\n include/linux/lzma/LzmaEnc.h |   80 ++\n include/linux/lzma/Types.h   |  226 +++++\n include/uapi/linux/jffs2.h   |    1 +\n lib/Kconfig                  |    6 +\n lib/Makefile                 |   12 +\n lib/lzma/LzFind.c            |  761 ++++++++++++++\n lib/lzma/LzmaDec.c           |  999 +++++++++++++++++++\n lib/lzma/LzmaEnc.c           | 2271 ++++++++++++++++++++++++++++++++++++++++++\n lib/lzma/Makefile            |    7 +\n 19 files changed, 5008 insertions(+), 6 deletions(-)\n create mode 100644 fs/jffs2/compr_lzma.c\n create mode 100644 include/linux/lzma.h\n create mode 100644 include/linux/lzma/LzFind.h\n create mode 100644 include/linux/lzma/LzHash.h\n create mode 100644 include/linux/lzma/LzmaDec.h\n create mode 100644 include/linux/lzma/LzmaEnc.h\n create mode 100644 include/linux/lzma/Types.h\n create mode 100644 lib/lzma/LzFind.c\n create mode 100644 lib/lzma/LzmaDec.c\n create mode 100644 lib/lzma/LzmaEnc.c\n create mode 100644 lib/lzma/Makefile\n\n--- a/fs/jffs2/Kconfig\n+++ b/fs/jffs2/Kconfig\n@@ -136,6 +136,15 @@ config JFFS2_LZO\n \t  This feature was added in July, 2007. Say 'N' if you need\n \t  compatibility with older bootloaders or kernels.\n \n+config JFFS2_LZMA\n+\tbool \"JFFS2 LZMA compression support\" if JFFS2_COMPRESSION_OPTIONS\n+\tselect LZMA_COMPRESS\n+\tselect LZMA_DECOMPRESS\n+\tdepends on JFFS2_FS\n+\tdefault n\n+\thelp\n+\t  JFFS2 wrapper to the LZMA C SDK\n+\n config JFFS2_RTIME\n \tbool \"JFFS2 RTIME compression support\" if JFFS2_COMPRESSION_OPTIONS\n \tdepends on JFFS2_FS\n--- a/fs/jffs2/Makefile\n+++ b/fs/jffs2/Makefile\n@@ -19,4 +19,7 @@ jffs2-$(CONFIG_JFFS2_RUBIN)\t+= compr_rub\n jffs2-$(CONFIG_JFFS2_RTIME)\t+= compr_rtime.o\n jffs2-$(CONFIG_JFFS2_ZLIB)\t+= compr_zlib.o\n jffs2-$(CONFIG_JFFS2_LZO)\t+= compr_lzo.o\n+jffs2-$(CONFIG_JFFS2_LZMA)\t+= compr_lzma.o\n jffs2-$(CONFIG_JFFS2_SUMMARY)   += summary.o\n+\n+CFLAGS_compr_lzma.o += -Iinclude/linux -Ilib/lzma\n--- a/fs/jffs2/compr.c\n+++ b/fs/jffs2/compr.c\n@@ -378,6 +378,9 @@ int __init jffs2_compressors_init(void)\n #ifdef CONFIG_JFFS2_LZO\n \tjffs2_lzo_init();\n #endif\n+#ifdef CONFIG_JFFS2_LZMA\n+\tjffs2_lzma_init();\n+#endif\n /* Setting default compression mode */\n #ifdef CONFIG_JFFS2_CMODE_NONE\n \tjffs2_compression_mode = JFFS2_COMPR_MODE_NONE;\n@@ -401,6 +404,9 @@ int __init jffs2_compressors_init(void)\n int jffs2_compressors_exit(void)\n {\n /* Unregistering compressors */\n+#ifdef CONFIG_JFFS2_LZMA\n+\tjffs2_lzma_exit();\n+#endif\n #ifdef CONFIG_JFFS2_LZO\n \tjffs2_lzo_exit();\n #endif\n--- a/fs/jffs2/compr.h\n+++ b/fs/jffs2/compr.h\n@@ -29,9 +29,9 @@\n #define JFFS2_DYNRUBIN_PRIORITY  20\n #define JFFS2_LZARI_PRIORITY     30\n #define JFFS2_RTIME_PRIORITY     50\n-#define JFFS2_ZLIB_PRIORITY      60\n-#define JFFS2_LZO_PRIORITY       80\n-\n+#define JFFS2_LZMA_PRIORITY      70\n+#define JFFS2_ZLIB_PRIORITY      80\n+#define JFFS2_LZO_PRIORITY       90\n \n #define JFFS2_RUBINMIPS_DISABLED /* RUBINs will be used only */\n #define JFFS2_DYNRUBIN_DISABLED  /*\t   for decompression */\n@@ -101,5 +101,9 @@ void jffs2_zlib_exit(void);\n int jffs2_lzo_init(void);\n void jffs2_lzo_exit(void);\n #endif\n+#ifdef CONFIG_JFFS2_LZMA\n+int jffs2_lzma_init(void);\n+void jffs2_lzma_exit(void);\n+#endif\n \n #endif /* __JFFS2_COMPR_H__ */\n--- /dev/null\n+++ b/fs/jffs2/compr_lzma.c\n@@ -0,0 +1,128 @@\n+/*\n+ * JFFS2 -- Journalling Flash File System, Version 2.\n+ *\n+ * For licensing information, see the file 'LICENCE' in this directory.\n+ *\n+ * JFFS2 wrapper to the LZMA C SDK\n+ *\n+ */\n+\n+#include <linux/lzma.h>\n+#include \"compr.h\"\n+\n+#ifdef __KERNEL__\n+\tstatic DEFINE_MUTEX(deflate_mutex);\n+#endif\n+\n+CLzmaEncHandle *p;\n+Byte propsEncoded[LZMA_PROPS_SIZE];\n+SizeT propsSize = sizeof(propsEncoded);\n+\n+STATIC void lzma_free_workspace(void)\n+{\n+\tLzmaEnc_Destroy(p, &lzma_alloc, &lzma_alloc);\n+}\n+\n+STATIC int INIT lzma_alloc_workspace(CLzmaEncProps *props)\n+{\n+\tif ((p = (CLzmaEncHandle *)LzmaEnc_Create(&lzma_alloc)) == NULL)\n+\t{\n+\t\tPRINT_ERROR(\"Failed to allocate lzma deflate workspace\\n\");\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\tif (LzmaEnc_SetProps(p, props) != SZ_OK)\n+\t{\n+\t\tlzma_free_workspace();\n+\t\treturn -1;\n+\t}\n+\n+\tif (LzmaEnc_WriteProperties(p, propsEncoded, &propsSize) != SZ_OK)\n+\t{\n+\t\tlzma_free_workspace();\n+\t\treturn -1;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+STATIC int jffs2_lzma_compress(unsigned char *data_in, unsigned char *cpage_out,\n+\t\t\t      uint32_t *sourcelen, uint32_t *dstlen)\n+{\n+\tSizeT compress_size = (SizeT)(*dstlen);\n+\tint ret;\n+\n+\t#ifdef __KERNEL__\n+\t\tmutex_lock(&deflate_mutex);\n+\t#endif\n+\n+\tret = LzmaEnc_MemEncode(p, cpage_out, &compress_size, data_in, *sourcelen,\n+\t\t0, NULL, &lzma_alloc, &lzma_alloc);\n+\n+\t#ifdef __KERNEL__\n+\t\tmutex_unlock(&deflate_mutex);\n+\t#endif\n+\n+\tif (ret != SZ_OK)\n+\t\treturn -1;\n+\n+\t*dstlen = (uint32_t)compress_size;\n+\n+\treturn 0;\n+}\n+\n+STATIC int jffs2_lzma_decompress(unsigned char *data_in, unsigned char *cpage_out,\n+\t\t\t\t uint32_t srclen, uint32_t destlen)\n+{\n+\tint ret;\n+\tSizeT dl = (SizeT)destlen;\n+\tSizeT sl = (SizeT)srclen;\n+\tELzmaStatus status;\n+\n+\tret = LzmaDecode(cpage_out, &dl, data_in, &sl, propsEncoded,\n+\t\tpropsSize, LZMA_FINISH_ANY, &status, &lzma_alloc);\n+\n+\tif (ret != SZ_OK || status == LZMA_STATUS_NOT_FINISHED || dl != (SizeT)destlen)\n+\t\treturn -1;\n+\n+\treturn 0;\n+}\n+\n+static struct jffs2_compressor jffs2_lzma_comp = {\n+\t.priority = JFFS2_LZMA_PRIORITY,\n+\t.name = \"lzma\",\n+\t.compr = JFFS2_COMPR_LZMA,\n+\t.compress = &jffs2_lzma_compress,\n+\t.decompress = &jffs2_lzma_decompress,\n+\t.disabled = 0,\n+};\n+\n+int INIT jffs2_lzma_init(void)\n+{\n+\tint ret;\n+\tCLzmaEncProps props;\n+\tLzmaEncProps_Init(&props);\n+\n+\tprops.dictSize = LZMA_BEST_DICT(0x2000);\n+\tprops.level = LZMA_BEST_LEVEL;\n+\tprops.lc = LZMA_BEST_LC;\n+\tprops.lp = LZMA_BEST_LP;\n+\tprops.pb = LZMA_BEST_PB;\n+\tprops.fb = LZMA_BEST_FB;\n+\n+\tret = lzma_alloc_workspace(&props);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\tret = jffs2_register_compressor(&jffs2_lzma_comp);\n+\tif (ret)\n+\t\tlzma_free_workspace();\n+\n+\treturn ret;\n+}\n+\n+void jffs2_lzma_exit(void)\n+{\n+\tjffs2_unregister_compressor(&jffs2_lzma_comp);\n+\tlzma_free_workspace();\n+}\n--- a/fs/jffs2/super.c\n+++ b/fs/jffs2/super.c\n@@ -374,14 +374,41 @@ static int __init init_jffs2_fs(void)\n \tBUILD_BUG_ON(sizeof(struct jffs2_raw_inode) != 68);\n \tBUILD_BUG_ON(sizeof(struct jffs2_raw_summary) != 32);\n \n-\tpr_info(\"version 2.2.\"\n+\tpr_info(\"version 2.2\"\n #ifdef CONFIG_JFFS2_FS_WRITEBUFFER\n \t       \" (NAND)\"\n #endif\n #ifdef CONFIG_JFFS2_SUMMARY\n-\t       \" (SUMMARY) \"\n+\t       \" (SUMMARY)\"\n #endif\n-\t       \" © 2001-2006 Red Hat, Inc.\\n\");\n+#ifdef CONFIG_JFFS2_ZLIB\n+\t       \" (ZLIB)\"\n+#endif\n+#ifdef CONFIG_JFFS2_LZO\n+\t       \" (LZO)\"\n+#endif\n+#ifdef CONFIG_JFFS2_LZMA\n+\t       \" (LZMA)\"\n+#endif\n+#ifdef CONFIG_JFFS2_RTIME\n+\t       \" (RTIME)\"\n+#endif\n+#ifdef CONFIG_JFFS2_RUBIN\n+\t       \" (RUBIN)\"\n+#endif\n+#ifdef  CONFIG_JFFS2_CMODE_NONE\n+\t       \" (CMODE_NONE)\"\n+#endif\n+#ifdef CONFIG_JFFS2_CMODE_PRIORITY\n+\t       \" (CMODE_PRIORITY)\"\n+#endif\n+#ifdef CONFIG_JFFS2_CMODE_SIZE\n+\t       \" (CMODE_SIZE)\"\n+#endif\n+#ifdef CONFIG_JFFS2_CMODE_FAVOURLZO\n+\t       \" (CMODE_FAVOURLZO)\"\n+#endif\n+\t       \" (c) 2001-2006 Red Hat, Inc.\\n\");\n \n \tjffs2_inode_cachep = kmem_cache_create(\"jffs2_i\",\n \t\t\t\t\t     sizeof(struct jffs2_inode_info),\n--- /dev/null\n+++ b/include/linux/lzma.h\n@@ -0,0 +1,62 @@\n+#ifndef __LZMA_H__\n+#define __LZMA_H__\n+\n+#ifdef __KERNEL__\n+\t#include <linux/kernel.h>\n+\t#include <linux/sched.h>\n+\t#include <linux/slab.h>\n+\t#include <linux/vmalloc.h>\n+\t#include <linux/init.h>\n+\t#define LZMA_MALLOC vmalloc\n+\t#define LZMA_FREE vfree\n+\t#define PRINT_ERROR(msg) printk(KERN_WARNING #msg)\n+\t#define INIT __init\n+\t#define STATIC static\n+#else\n+\t#include <stdint.h>\n+\t#include <stdlib.h>\n+\t#include <stdio.h>\n+\t#include <unistd.h>\n+\t#include <string.h>\n+\t#include <asm/types.h>\n+\t#include <errno.h>\n+\t#include <linux/jffs2.h>\n+\t#ifndef PAGE_SIZE\n+\t\textern int page_size;\n+\t\t#define PAGE_SIZE page_size\n+\t#endif\n+\t#define LZMA_MALLOC malloc\n+\t#define LZMA_FREE free\n+\t#define PRINT_ERROR(msg) fprintf(stderr, msg)\n+\t#define INIT\n+\t#define STATIC\n+#endif\n+\n+#include \"lzma/LzmaDec.h\"\n+#include \"lzma/LzmaEnc.h\"\n+\n+#define LZMA_BEST_LEVEL (9)\n+#define LZMA_BEST_LC    (0)\n+#define LZMA_BEST_LP    (0)\n+#define LZMA_BEST_PB    (0)\n+#define LZMA_BEST_FB  (273)\n+\n+#define LZMA_BEST_DICT(n) (((int)((n) / 2)) * 2)\n+\n+static void *p_lzma_malloc(void *p, size_t size)\n+{\n+\tif (size == 0)\n+\t\treturn NULL;\n+\n+\treturn LZMA_MALLOC(size);\n+}\n+\n+static void p_lzma_free(void *p, void *address)\n+{\n+\tif (address != NULL)\n+\t\tLZMA_FREE(address);\n+}\n+\n+static ISzAlloc lzma_alloc = {p_lzma_malloc, p_lzma_free};\n+\n+#endif\n--- /dev/null\n+++ b/include/linux/lzma/LzFind.h\n@@ -0,0 +1,115 @@\n+/* LzFind.h -- Match finder for LZ algorithms\n+2009-04-22 : Igor Pavlov : Public domain */\n+\n+#ifndef __LZ_FIND_H\n+#define __LZ_FIND_H\n+\n+#include \"Types.h\"\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+typedef UInt32 CLzRef;\n+\n+typedef struct _CMatchFinder\n+{\n+  Byte *buffer;\n+  UInt32 pos;\n+  UInt32 posLimit;\n+  UInt32 streamPos;\n+  UInt32 lenLimit;\n+\n+  UInt32 cyclicBufferPos;\n+  UInt32 cyclicBufferSize; /* it must be = (historySize + 1) */\n+\n+  UInt32 matchMaxLen;\n+  CLzRef *hash;\n+  CLzRef *son;\n+  UInt32 hashMask;\n+  UInt32 cutValue;\n+\n+  Byte *bufferBase;\n+  ISeqInStream *stream;\n+  int streamEndWasReached;\n+\n+  UInt32 blockSize;\n+  UInt32 keepSizeBefore;\n+  UInt32 keepSizeAfter;\n+\n+  UInt32 numHashBytes;\n+  int directInput;\n+  size_t directInputRem;\n+  int btMode;\n+  int bigHash;\n+  UInt32 historySize;\n+  UInt32 fixedHashSize;\n+  UInt32 hashSizeSum;\n+  UInt32 numSons;\n+  SRes result;\n+  UInt32 crc[256];\n+} CMatchFinder;\n+\n+#define Inline_MatchFinder_GetPointerToCurrentPos(p) ((p)->buffer)\n+#define Inline_MatchFinder_GetIndexByte(p, index) ((p)->buffer[(Int32)(index)])\n+\n+#define Inline_MatchFinder_GetNumAvailableBytes(p) ((p)->streamPos - (p)->pos)\n+\n+int MatchFinder_NeedMove(CMatchFinder *p);\n+Byte *MatchFinder_GetPointerToCurrentPos(CMatchFinder *p);\n+void MatchFinder_MoveBlock(CMatchFinder *p);\n+void MatchFinder_ReadIfRequired(CMatchFinder *p);\n+\n+void MatchFinder_Construct(CMatchFinder *p);\n+\n+/* Conditions:\n+     historySize <= 3 GB\n+     keepAddBufferBefore + matchMaxLen + keepAddBufferAfter < 511MB\n+*/\n+int MatchFinder_Create(CMatchFinder *p, UInt32 historySize,\n+    UInt32 keepAddBufferBefore, UInt32 matchMaxLen, UInt32 keepAddBufferAfter,\n+    ISzAlloc *alloc);\n+void MatchFinder_Free(CMatchFinder *p, ISzAlloc *alloc);\n+void MatchFinder_Normalize3(UInt32 subValue, CLzRef *items, UInt32 numItems);\n+void MatchFinder_ReduceOffsets(CMatchFinder *p, UInt32 subValue);\n+\n+UInt32 * GetMatchesSpec1(UInt32 lenLimit, UInt32 curMatch, UInt32 pos, const Byte *buffer, CLzRef *son,\n+    UInt32 _cyclicBufferPos, UInt32 _cyclicBufferSize, UInt32 _cutValue,\n+    UInt32 *distances, UInt32 maxLen);\n+\n+/*\n+Conditions:\n+  Mf_GetNumAvailableBytes_Func must be called before each Mf_GetMatchLen_Func.\n+  Mf_GetPointerToCurrentPos_Func's result must be used only before any other function\n+*/\n+\n+typedef void (*Mf_Init_Func)(void *object);\n+typedef Byte (*Mf_GetIndexByte_Func)(void *object, Int32 index);\n+typedef UInt32 (*Mf_GetNumAvailableBytes_Func)(void *object);\n+typedef const Byte * (*Mf_GetPointerToCurrentPos_Func)(void *object);\n+typedef UInt32 (*Mf_GetMatches_Func)(void *object, UInt32 *distances);\n+typedef void (*Mf_Skip_Func)(void *object, UInt32);\n+\n+typedef struct _IMatchFinder\n+{\n+  Mf_Init_Func Init;\n+  Mf_GetIndexByte_Func GetIndexByte;\n+  Mf_GetNumAvailableBytes_Func GetNumAvailableBytes;\n+  Mf_GetPointerToCurrentPos_Func GetPointerToCurrentPos;\n+  Mf_GetMatches_Func GetMatches;\n+  Mf_Skip_Func Skip;\n+} IMatchFinder;\n+\n+void MatchFinder_CreateVTable(CMatchFinder *p, IMatchFinder *vTable);\n+\n+void MatchFinder_Init(CMatchFinder *p);\n+UInt32 Bt3Zip_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances);\n+UInt32 Hc3Zip_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances);\n+void Bt3Zip_MatchFinder_Skip(CMatchFinder *p, UInt32 num);\n+void Hc3Zip_MatchFinder_Skip(CMatchFinder *p, UInt32 num);\n+\n+#ifdef __cplusplus\n+}\n+#endif\n+\n+#endif\n--- /dev/null\n+++ b/include/linux/lzma/LzHash.h\n@@ -0,0 +1,54 @@\n+/* LzHash.h -- HASH functions for LZ algorithms\n+2009-02-07 : Igor Pavlov : Public domain */\n+\n+#ifndef __LZ_HASH_H\n+#define __LZ_HASH_H\n+\n+#define kHash2Size (1 << 10)\n+#define kHash3Size (1 << 16)\n+#define kHash4Size (1 << 20)\n+\n+#define kFix3HashSize (kHash2Size)\n+#define kFix4HashSize (kHash2Size + kHash3Size)\n+#define kFix5HashSize (kHash2Size + kHash3Size + kHash4Size)\n+\n+#define HASH2_CALC hashValue = cur[0] | ((UInt32)cur[1] << 8);\n+\n+#define HASH3_CALC { \\\n+  UInt32 temp = p->crc[cur[0]] ^ cur[1]; \\\n+  hash2Value = temp & (kHash2Size - 1); \\\n+  hashValue = (temp ^ ((UInt32)cur[2] << 8)) & p->hashMask; }\n+\n+#define HASH4_CALC { \\\n+  UInt32 temp = p->crc[cur[0]] ^ cur[1]; \\\n+  hash2Value = temp & (kHash2Size - 1); \\\n+  hash3Value = (temp ^ ((UInt32)cur[2] << 8)) & (kHash3Size - 1); \\\n+  hashValue = (temp ^ ((UInt32)cur[2] << 8) ^ (p->crc[cur[3]] << 5)) & p->hashMask; }\n+\n+#define HASH5_CALC { \\\n+  UInt32 temp = p->crc[cur[0]] ^ cur[1]; \\\n+  hash2Value = temp & (kHash2Size - 1); \\\n+  hash3Value = (temp ^ ((UInt32)cur[2] << 8)) & (kHash3Size - 1); \\\n+  hash4Value = (temp ^ ((UInt32)cur[2] << 8) ^ (p->crc[cur[3]] << 5)); \\\n+  hashValue = (hash4Value ^ (p->crc[cur[4]] << 3)) & p->hashMask; \\\n+  hash4Value &= (kHash4Size - 1); }\n+\n+/* #define HASH_ZIP_CALC hashValue = ((cur[0] | ((UInt32)cur[1] << 8)) ^ p->crc[cur[2]]) & 0xFFFF; */\n+#define HASH_ZIP_CALC hashValue = ((cur[2] | ((UInt32)cur[0] << 8)) ^ p->crc[cur[1]]) & 0xFFFF;\n+\n+\n+#define MT_HASH2_CALC \\\n+  hash2Value = (p->crc[cur[0]] ^ cur[1]) & (kHash2Size - 1);\n+\n+#define MT_HASH3_CALC { \\\n+  UInt32 temp = p->crc[cur[0]] ^ cur[1]; \\\n+  hash2Value = temp & (kHash2Size - 1); \\\n+  hash3Value = (temp ^ ((UInt32)cur[2] << 8)) & (kHash3Size - 1); }\n+\n+#define MT_HASH4_CALC { \\\n+  UInt32 temp = p->crc[cur[0]] ^ cur[1]; \\\n+  hash2Value = temp & (kHash2Size - 1); \\\n+  hash3Value = (temp ^ ((UInt32)cur[2] << 8)) & (kHash3Size - 1); \\\n+  hash4Value = (temp ^ ((UInt32)cur[2] << 8) ^ (p->crc[cur[3]] << 5)) & (kHash4Size - 1); }\n+\n+#endif\n--- /dev/null\n+++ b/include/linux/lzma/LzmaDec.h\n@@ -0,0 +1,231 @@\n+/* LzmaDec.h -- LZMA Decoder\n+2009-02-07 : Igor Pavlov : Public domain */\n+\n+#ifndef __LZMA_DEC_H\n+#define __LZMA_DEC_H\n+\n+#include \"Types.h\"\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+/* #define _LZMA_PROB32 */\n+/* _LZMA_PROB32 can increase the speed on some CPUs,\n+   but memory usage for CLzmaDec::probs will be doubled in that case */\n+\n+#ifdef _LZMA_PROB32\n+#define CLzmaProb UInt32\n+#else\n+#define CLzmaProb UInt16\n+#endif\n+\n+\n+/* ---------- LZMA Properties ---------- */\n+\n+#define LZMA_PROPS_SIZE 5\n+\n+typedef struct _CLzmaProps\n+{\n+  unsigned lc, lp, pb;\n+  UInt32 dicSize;\n+} CLzmaProps;\n+\n+/* LzmaProps_Decode - decodes properties\n+Returns:\n+  SZ_OK\n+  SZ_ERROR_UNSUPPORTED - Unsupported properties\n+*/\n+\n+SRes LzmaProps_Decode(CLzmaProps *p, const Byte *data, unsigned size);\n+\n+\n+/* ---------- LZMA Decoder state ---------- */\n+\n+/* LZMA_REQUIRED_INPUT_MAX = number of required input bytes for worst case.\n+   Num bits = log2((2^11 / 31) ^ 22) + 26 < 134 + 26 = 160; */\n+\n+#define LZMA_REQUIRED_INPUT_MAX 20\n+\n+typedef struct\n+{\n+  CLzmaProps prop;\n+  CLzmaProb *probs;\n+  Byte *dic;\n+  const Byte *buf;\n+  UInt32 range, code;\n+  SizeT dicPos;\n+  SizeT dicBufSize;\n+  UInt32 processedPos;\n+  UInt32 checkDicSize;\n+  unsigned state;\n+  UInt32 reps[4];\n+  unsigned remainLen;\n+  int needFlush;\n+  int needInitState;\n+  UInt32 numProbs;\n+  unsigned tempBufSize;\n+  Byte tempBuf[LZMA_REQUIRED_INPUT_MAX];\n+} CLzmaDec;\n+\n+#define LzmaDec_Construct(p) { (p)->dic = 0; (p)->probs = 0; }\n+\n+void LzmaDec_Init(CLzmaDec *p);\n+\n+/* There are two types of LZMA streams:\n+     0) Stream with end mark. That end mark adds about 6 bytes to compressed size.\n+     1) Stream without end mark. You must know exact uncompressed size to decompress such stream. */\n+\n+typedef enum\n+{\n+  LZMA_FINISH_ANY,   /* finish at any point */\n+  LZMA_FINISH_END    /* block must be finished at the end */\n+} ELzmaFinishMode;\n+\n+/* ELzmaFinishMode has meaning only if the decoding reaches output limit !!!\n+\n+   You must use LZMA_FINISH_END, when you know that current output buffer\n+   covers last bytes of block. In other cases you must use LZMA_FINISH_ANY.\n+\n+   If LZMA decoder sees end marker before reaching output limit, it returns SZ_OK,\n+   and output value of destLen will be less than output buffer size limit.\n+   You can check status result also.\n+\n+   You can use multiple checks to test data integrity after full decompression:\n+     1) Check Result and \"status\" variable.\n+     2) Check that output(destLen) = uncompressedSize, if you know real uncompressedSize.\n+     3) Check that output(srcLen) = compressedSize, if you know real compressedSize.\n+        You must use correct finish mode in that case. */\n+\n+typedef enum\n+{\n+  LZMA_STATUS_NOT_SPECIFIED,               /* use main error code instead */\n+  LZMA_STATUS_FINISHED_WITH_MARK,          /* stream was finished with end mark. */\n+  LZMA_STATUS_NOT_FINISHED,                /* stream was not finished */\n+  LZMA_STATUS_NEEDS_MORE_INPUT,            /* you must provide more input bytes */\n+  LZMA_STATUS_MAYBE_FINISHED_WITHOUT_MARK  /* there is probability that stream was finished without end mark */\n+} ELzmaStatus;\n+\n+/* ELzmaStatus is used only as output value for function call */\n+\n+\n+/* ---------- Interfaces ---------- */\n+\n+/* There are 3 levels of interfaces:\n+     1) Dictionary Interface\n+     2) Buffer Interface\n+     3) One Call Interface\n+   You can select any of these interfaces, but don't mix functions from different\n+   groups for same object. */\n+\n+\n+/* There are two variants to allocate state for Dictionary Interface:\n+     1) LzmaDec_Allocate / LzmaDec_Free\n+     2) LzmaDec_AllocateProbs / LzmaDec_FreeProbs\n+   You can use variant 2, if you set dictionary buffer manually.\n+   For Buffer Interface you must always use variant 1.\n+\n+LzmaDec_Allocate* can return:\n+  SZ_OK\n+  SZ_ERROR_MEM         - Memory allocation error\n+  SZ_ERROR_UNSUPPORTED - Unsupported properties\n+*/\n+\n+SRes LzmaDec_AllocateProbs(CLzmaDec *p, const Byte *props, unsigned propsSize, ISzAlloc *alloc);\n+void LzmaDec_FreeProbs(CLzmaDec *p, ISzAlloc *alloc);\n+\n+SRes LzmaDec_Allocate(CLzmaDec *state, const Byte *prop, unsigned propsSize, ISzAlloc *alloc);\n+void LzmaDec_Free(CLzmaDec *state, ISzAlloc *alloc);\n+\n+/* ---------- Dictionary Interface ---------- */\n+\n+/* You can use it, if you want to eliminate the overhead for data copying from\n+   dictionary to some other external buffer.\n+   You must work with CLzmaDec variables directly in this interface.\n+\n+   STEPS:\n+     LzmaDec_Constr()\n+     LzmaDec_Allocate()\n+     for (each new stream)\n+     {\n+       LzmaDec_Init()\n+       while (it needs more decompression)\n+       {\n+         LzmaDec_DecodeToDic()\n+         use data from CLzmaDec::dic and update CLzmaDec::dicPos\n+       }\n+     }\n+     LzmaDec_Free()\n+*/\n+\n+/* LzmaDec_DecodeToDic\n+\n+   The decoding to internal dictionary buffer (CLzmaDec::dic).\n+   You must manually update CLzmaDec::dicPos, if it reaches CLzmaDec::dicBufSize !!!\n+\n+finishMode:\n+  It has meaning only if the decoding reaches output limit (dicLimit).\n+  LZMA_FINISH_ANY - Decode just dicLimit bytes.\n+  LZMA_FINISH_END - Stream must be finished after dicLimit.\n+\n+Returns:\n+  SZ_OK\n+    status:\n+      LZMA_STATUS_FINISHED_WITH_MARK\n+      LZMA_STATUS_NOT_FINISHED\n+      LZMA_STATUS_NEEDS_MORE_INPUT\n+      LZMA_STATUS_MAYBE_FINISHED_WITHOUT_MARK\n+  SZ_ERROR_DATA - Data error\n+*/\n+\n+SRes LzmaDec_DecodeToDic(CLzmaDec *p, SizeT dicLimit,\n+    const Byte *src, SizeT *srcLen, ELzmaFinishMode finishMode, ELzmaStatus *status);\n+\n+\n+/* ---------- Buffer Interface ---------- */\n+\n+/* It's zlib-like interface.\n+   See LzmaDec_DecodeToDic description for information about STEPS and return results,\n+   but you must use LzmaDec_DecodeToBuf instead of LzmaDec_DecodeToDic and you don't need\n+   to work with CLzmaDec variables manually.\n+\n+finishMode:\n+  It has meaning only if the decoding reaches output limit (*destLen).\n+  LZMA_FINISH_ANY - Decode just destLen bytes.\n+  LZMA_FINISH_END - Stream must be finished after (*destLen).\n+*/\n+\n+SRes LzmaDec_DecodeToBuf(CLzmaDec *p, Byte *dest, SizeT *destLen,\n+    const Byte *src, SizeT *srcLen, ELzmaFinishMode finishMode, ELzmaStatus *status);\n+\n+\n+/* ---------- One Call Interface ---------- */\n+\n+/* LzmaDecode\n+\n+finishMode:\n+  It has meaning only if the decoding reaches output limit (*destLen).\n+  LZMA_FINISH_ANY - Decode just destLen bytes.\n+  LZMA_FINISH_END - Stream must be finished after (*destLen).\n+\n+Returns:\n+  SZ_OK\n+    status:\n+      LZMA_STATUS_FINISHED_WITH_MARK\n+      LZMA_STATUS_NOT_FINISHED\n+      LZMA_STATUS_MAYBE_FINISHED_WITHOUT_MARK\n+  SZ_ERROR_DATA - Data error\n+  SZ_ERROR_MEM  - Memory allocation error\n+  SZ_ERROR_UNSUPPORTED - Unsupported properties\n+  SZ_ERROR_INPUT_EOF - It needs more bytes in input buffer (src).\n+*/\n+\n+SRes LzmaDecode(Byte *dest, SizeT *destLen, const Byte *src, SizeT *srcLen,\n+    const Byte *propData, unsigned propSize, ELzmaFinishMode finishMode,\n+    ELzmaStatus *status, ISzAlloc *alloc);\n+\n+#ifdef __cplusplus\n+}\n+#endif\n+\n+#endif\n--- /dev/null\n+++ b/include/linux/lzma/LzmaEnc.h\n@@ -0,0 +1,80 @@\n+/*  LzmaEnc.h -- LZMA Encoder\n+2009-02-07 : Igor Pavlov : Public domain */\n+\n+#ifndef __LZMA_ENC_H\n+#define __LZMA_ENC_H\n+\n+#include \"Types.h\"\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+#define LZMA_PROPS_SIZE 5\n+\n+typedef struct _CLzmaEncProps\n+{\n+  int level;       /*  0 <= level <= 9 */\n+  UInt32 dictSize; /* (1 << 12) <= dictSize <= (1 << 27) for 32-bit version\n+                      (1 << 12) <= dictSize <= (1 << 30) for 64-bit version\n+                       default = (1 << 24) */\n+  int lc;          /* 0 <= lc <= 8, default = 3 */\n+  int lp;          /* 0 <= lp <= 4, default = 0 */\n+  int pb;          /* 0 <= pb <= 4, default = 2 */\n+  int algo;        /* 0 - fast, 1 - normal, default = 1 */\n+  int fb;          /* 5 <= fb <= 273, default = 32 */\n+  int btMode;      /* 0 - hashChain Mode, 1 - binTree mode - normal, default = 1 */\n+  int numHashBytes; /* 2, 3 or 4, default = 4 */\n+  UInt32 mc;        /* 1 <= mc <= (1 << 30), default = 32 */\n+  unsigned writeEndMark;  /* 0 - do not write EOPM, 1 - write EOPM, default = 0 */\n+  int numThreads;  /* 1 or 2, default = 2 */\n+} CLzmaEncProps;\n+\n+void LzmaEncProps_Init(CLzmaEncProps *p);\n+void LzmaEncProps_Normalize(CLzmaEncProps *p);\n+UInt32 LzmaEncProps_GetDictSize(const CLzmaEncProps *props2);\n+\n+\n+/* ---------- CLzmaEncHandle Interface ---------- */\n+\n+/* LzmaEnc_* functions can return the following exit codes:\n+Returns:\n+  SZ_OK           - OK\n+  SZ_ERROR_MEM    - Memory allocation error\n+  SZ_ERROR_PARAM  - Incorrect paramater in props\n+  SZ_ERROR_WRITE  - Write callback error.\n+  SZ_ERROR_PROGRESS - some break from progress callback\n+  SZ_ERROR_THREAD - errors in multithreading functions (only for Mt version)\n+*/\n+\n+typedef void * CLzmaEncHandle;\n+\n+CLzmaEncHandle LzmaEnc_Create(ISzAlloc *alloc);\n+void LzmaEnc_Destroy(CLzmaEncHandle p, ISzAlloc *alloc, ISzAlloc *allocBig);\n+SRes LzmaEnc_SetProps(CLzmaEncHandle p, const CLzmaEncProps *props);\n+SRes LzmaEnc_WriteProperties(CLzmaEncHandle p, Byte *properties, SizeT *size);\n+SRes LzmaEnc_Encode(CLzmaEncHandle p, ISeqOutStream *outStream, ISeqInStream *inStream,\n+    ICompressProgress *progress, ISzAlloc *alloc, ISzAlloc *allocBig);\n+SRes LzmaEnc_MemEncode(CLzmaEncHandle p, Byte *dest, SizeT *destLen, const Byte *src, SizeT srcLen,\n+    int writeEndMark, ICompressProgress *progress, ISzAlloc *alloc, ISzAlloc *allocBig);\n+\n+/* ---------- One Call Interface ---------- */\n+\n+/* LzmaEncode\n+Return code:\n+  SZ_OK               - OK\n+  SZ_ERROR_MEM        - Memory allocation error\n+  SZ_ERROR_PARAM      - Incorrect paramater\n+  SZ_ERROR_OUTPUT_EOF - output buffer overflow\n+  SZ_ERROR_THREAD     - errors in multithreading functions (only for Mt version)\n+*/\n+\n+SRes LzmaEncode(Byte *dest, SizeT *destLen, const Byte *src, SizeT srcLen,\n+    const CLzmaEncProps *props, Byte *propsEncoded, SizeT *propsSize, int writeEndMark,\n+    ICompressProgress *progress, ISzAlloc *alloc, ISzAlloc *allocBig);\n+\n+#ifdef __cplusplus\n+}\n+#endif\n+\n+#endif\n--- /dev/null\n+++ b/include/linux/lzma/Types.h\n@@ -0,0 +1,226 @@\n+/* Types.h -- Basic types\n+2009-11-23 : Igor Pavlov : Public domain */\n+\n+#ifndef __7Z_TYPES_H\n+#define __7Z_TYPES_H\n+\n+#include <stddef.h>\n+\n+#ifdef _WIN32\n+#include <windows.h>\n+#endif\n+\n+#ifndef EXTERN_C_BEGIN\n+#ifdef __cplusplus\n+#define EXTERN_C_BEGIN extern \"C\" {\n+#define EXTERN_C_END }\n+#else\n+#define EXTERN_C_BEGIN\n+#define EXTERN_C_END\n+#endif\n+#endif\n+\n+EXTERN_C_BEGIN\n+\n+#define SZ_OK 0\n+\n+#define SZ_ERROR_DATA 1\n+#define SZ_ERROR_MEM 2\n+#define SZ_ERROR_CRC 3\n+#define SZ_ERROR_UNSUPPORTED 4\n+#define SZ_ERROR_PARAM 5\n+#define SZ_ERROR_INPUT_EOF 6\n+#define SZ_ERROR_OUTPUT_EOF 7\n+#define SZ_ERROR_READ 8\n+#define SZ_ERROR_WRITE 9\n+#define SZ_ERROR_PROGRESS 10\n+#define SZ_ERROR_FAIL 11\n+#define SZ_ERROR_THREAD 12\n+\n+#define SZ_ERROR_ARCHIVE 16\n+#define SZ_ERROR_NO_ARCHIVE 17\n+\n+typedef int SRes;\n+\n+#ifdef _WIN32\n+typedef DWORD WRes;\n+#else\n+typedef int WRes;\n+#endif\n+\n+#ifndef RINOK\n+#define RINOK(x) { int __result__ = (x); if (__result__ != 0) return __result__; }\n+#endif\n+\n+typedef unsigned char Byte;\n+typedef short Int16;\n+typedef unsigned short UInt16;\n+\n+#ifdef _LZMA_UINT32_IS_ULONG\n+typedef long Int32;\n+typedef unsigned long UInt32;\n+#else\n+typedef int Int32;\n+typedef unsigned int UInt32;\n+#endif\n+\n+#ifdef _SZ_NO_INT_64\n+\n+/* define _SZ_NO_INT_64, if your compiler doesn't support 64-bit integers.\n+   NOTES: Some code will work incorrectly in that case! */\n+\n+typedef long Int64;\n+typedef unsigned long UInt64;\n+\n+#else\n+\n+#if defined(_MSC_VER) || defined(__BORLANDC__)\n+typedef __int64 Int64;\n+typedef unsigned __int64 UInt64;\n+#else\n+typedef long long int Int64;\n+typedef unsigned long long int UInt64;\n+#endif\n+\n+#endif\n+\n+#ifdef _LZMA_NO_SYSTEM_SIZE_T\n+typedef UInt32 SizeT;\n+#else\n+typedef size_t SizeT;\n+#endif\n+\n+typedef int Bool;\n+#define True 1\n+#define False 0\n+\n+\n+#ifdef _WIN32\n+#define MY_STD_CALL __stdcall\n+#else\n+#define MY_STD_CALL\n+#endif\n+\n+#ifdef _MSC_VER\n+\n+#if _MSC_VER >= 1300\n+#define MY_NO_INLINE __declspec(noinline)\n+#else\n+#define MY_NO_INLINE\n+#endif\n+\n+#define MY_CDECL __cdecl\n+#define MY_FAST_CALL __fastcall\n+\n+#else\n+\n+#define MY_CDECL\n+#define MY_FAST_CALL\n+\n+#endif\n+\n+\n+/* The following interfaces use first parameter as pointer to structure */\n+\n+typedef struct\n+{\n+  SRes (*Read)(void *p, void *buf, size_t *size);\n+    /* if (input(*size) != 0 && output(*size) == 0) means end_of_stream.\n+       (output(*size) < input(*size)) is allowed */\n+} ISeqInStream;\n+\n+/* it can return SZ_ERROR_INPUT_EOF */\n+SRes SeqInStream_Read(ISeqInStream *stream, void *buf, size_t size);\n+SRes SeqInStream_Read2(ISeqInStream *stream, void *buf, size_t size, SRes errorType);\n+SRes SeqInStream_ReadByte(ISeqInStream *stream, Byte *buf);\n+\n+typedef struct\n+{\n+  size_t (*Write)(void *p, const void *buf, size_t size);\n+    /* Returns: result - the number of actually written bytes.\n+       (result < size) means error */\n+} ISeqOutStream;\n+\n+typedef enum\n+{\n+  SZ_SEEK_SET = 0,\n+  SZ_SEEK_CUR = 1,\n+  SZ_SEEK_END = 2\n+} ESzSeek;\n+\n+typedef struct\n+{\n+  SRes (*Read)(void *p, void *buf, size_t *size);  /* same as ISeqInStream::Read */\n+  SRes (*Seek)(void *p, Int64 *pos, ESzSeek origin);\n+} ISeekInStream;\n+\n+typedef struct\n+{\n+  SRes (*Look)(void *p, void **buf, size_t *size);\n+    /* if (input(*size) != 0 && output(*size) == 0) means end_of_stream.\n+       (output(*size) > input(*size)) is not allowed\n+       (output(*size) < input(*size)) is allowed */\n+  SRes (*Skip)(void *p, size_t offset);\n+    /* offset must be <= output(*size) of Look */\n+\n+  SRes (*Read)(void *p, void *buf, size_t *size);\n+    /* reads directly (without buffer). It's same as ISeqInStream::Read */\n+  SRes (*Seek)(void *p, Int64 *pos, ESzSeek origin);\n+} ILookInStream;\n+\n+SRes LookInStream_LookRead(ILookInStream *stream, void *buf, size_t *size);\n+SRes LookInStream_SeekTo(ILookInStream *stream, UInt64 offset);\n+\n+/* reads via ILookInStream::Read */\n+SRes LookInStream_Read2(ILookInStream *stream, void *buf, size_t size, SRes errorType);\n+SRes LookInStream_Read(ILookInStream *stream, void *buf, size_t size);\n+\n+#define LookToRead_BUF_SIZE (1 << 14)\n+\n+typedef struct\n+{\n+  ILookInStream s;\n+  ISeekInStream *realStream;\n+  size_t pos;\n+  size_t size;\n+  Byte buf[LookToRead_BUF_SIZE];\n+} CLookToRead;\n+\n+void LookToRead_CreateVTable(CLookToRead *p, int lookahead);\n+void LookToRead_Init(CLookToRead *p);\n+\n+typedef struct\n+{\n+  ISeqInStream s;\n+  ILookInStream *realStream;\n+} CSecToLook;\n+\n+void SecToLook_CreateVTable(CSecToLook *p);\n+\n+typedef struct\n+{\n+  ISeqInStream s;\n+  ILookInStream *realStream;\n+} CSecToRead;\n+\n+void SecToRead_CreateVTable(CSecToRead *p);\n+\n+typedef struct\n+{\n+  SRes (*Progress)(void *p, UInt64 inSize, UInt64 outSize);\n+    /* Returns: result. (result != SZ_OK) means break.\n+       Value (UInt64)(Int64)-1 for size means unknown value. */\n+} ICompressProgress;\n+\n+typedef struct\n+{\n+  void *(*Alloc)(void *p, size_t size);\n+  void (*Free)(void *p, void *address); /* address can be 0 */\n+} ISzAlloc;\n+\n+#define IAlloc_Alloc(p, size) (p)->Alloc((p), size)\n+#define IAlloc_Free(p, a) (p)->Free((p), a)\n+\n+EXTERN_C_END\n+\n+#endif\n--- a/include/uapi/linux/jffs2.h\n+++ b/include/uapi/linux/jffs2.h\n@@ -46,6 +46,7 @@\n #define JFFS2_COMPR_DYNRUBIN\t0x05\n #define JFFS2_COMPR_ZLIB\t0x06\n #define JFFS2_COMPR_LZO\t\t0x07\n+#define JFFS2_COMPR_LZMA\t0x08\n /* Compatibility flags. */\n #define JFFS2_COMPAT_MASK 0xc000      /* What do to if an unknown nodetype is found */\n #define JFFS2_NODE_ACCURATE 0x2000\n--- a/lib/Kconfig\n+++ b/lib/Kconfig\n@@ -335,6 +335,12 @@ config ZSTD_DECOMPRESS\n \n source \"lib/xz/Kconfig\"\n \n+config LZMA_COMPRESS\n+    tristate\n+\n+config LZMA_DECOMPRESS\n+    tristate\n+\n #\n # These all provide a common interface (hence the apparent duplication with\n # ZLIB_INFLATE; DECOMPRESS_GZIP is just a wrapper.)\n--- a/lib/Makefile\n+++ b/lib/Makefile\n@@ -135,6 +135,16 @@ CFLAGS_kobject.o += -DDEBUG\n CFLAGS_kobject_uevent.o += -DDEBUG\n endif\n \n+ifdef CONFIG_JFFS2_ZLIB\n+  CONFIG_ZLIB_INFLATE:=y\n+  CONFIG_ZLIB_DEFLATE:=y\n+endif\n+\n+ifdef CONFIG_JFFS2_LZMA\n+  CONFIG_LZMA_DECOMPRESS:=y\n+  CONFIG_LZMA_COMPRESS:=y\n+endif\n+\n obj-$(CONFIG_DEBUG_INFO_REDUCED) += debug_info.o\n CFLAGS_debug_info.o += $(call cc-option, -femit-struct-debug-detailed=any)\n \n@@ -192,6 +202,8 @@ obj-$(CONFIG_ZSTD_COMPRESS) += zstd/\n obj-$(CONFIG_ZSTD_DECOMPRESS) += zstd/\n obj-$(CONFIG_XZ_DEC) += xz/\n obj-$(CONFIG_RAID6_PQ) += raid6/\n+obj-$(CONFIG_LZMA_COMPRESS) += lzma/\n+obj-$(CONFIG_LZMA_DECOMPRESS) += lzma/\n \n lib-$(CONFIG_DECOMPRESS_GZIP) += decompress_inflate.o\n lib-$(CONFIG_DECOMPRESS_BZIP2) += decompress_bunzip2.o\n--- /dev/null\n+++ b/lib/lzma/LzFind.c\n@@ -0,0 +1,761 @@\n+/* LzFind.c -- Match finder for LZ algorithms\n+2009-04-22 : Igor Pavlov : Public domain */\n+\n+#include <string.h>\n+\n+#include \"LzFind.h\"\n+#include \"LzHash.h\"\n+\n+#define kEmptyHashValue 0\n+#define kMaxValForNormalize ((UInt32)0xFFFFFFFF)\n+#define kNormalizeStepMin (1 << 10) /* it must be power of 2 */\n+#define kNormalizeMask (~(kNormalizeStepMin - 1))\n+#define kMaxHistorySize ((UInt32)3 << 30)\n+\n+#define kStartMaxLen 3\n+\n+static void LzInWindow_Free(CMatchFinder *p, ISzAlloc *alloc)\n+{\n+  if (!p->directInput)\n+  {\n+    alloc->Free(alloc, p->bufferBase);\n+    p->bufferBase = 0;\n+  }\n+}\n+\n+/* keepSizeBefore + keepSizeAfter + keepSizeReserv must be < 4G) */\n+\n+static int LzInWindow_Create(CMatchFinder *p, UInt32 keepSizeReserv, ISzAlloc *alloc)\n+{\n+  UInt32 blockSize = p->keepSizeBefore + p->keepSizeAfter + keepSizeReserv;\n+  if (p->directInput)\n+  {\n+    p->blockSize = blockSize;\n+    return 1;\n+  }\n+  if (p->bufferBase == 0 || p->blockSize != blockSize)\n+  {\n+    LzInWindow_Free(p, alloc);\n+    p->blockSize = blockSize;\n+    p->bufferBase = (Byte *)alloc->Alloc(alloc, (size_t)blockSize);\n+  }\n+  return (p->bufferBase != 0);\n+}\n+\n+Byte *MatchFinder_GetPointerToCurrentPos(CMatchFinder *p) { return p->buffer; }\n+Byte MatchFinder_GetIndexByte(CMatchFinder *p, Int32 index) { return p->buffer[index]; }\n+\n+UInt32 MatchFinder_GetNumAvailableBytes(CMatchFinder *p) { return p->streamPos - p->pos; }\n+\n+void MatchFinder_ReduceOffsets(CMatchFinder *p, UInt32 subValue)\n+{\n+  p->posLimit -= subValue;\n+  p->pos -= subValue;\n+  p->streamPos -= subValue;\n+}\n+\n+static void MatchFinder_ReadBlock(CMatchFinder *p)\n+{\n+  if (p->streamEndWasReached || p->result != SZ_OK)\n+    return;\n+  if (p->directInput)\n+  {\n+    UInt32 curSize = 0xFFFFFFFF - p->streamPos;\n+    if (curSize > p->directInputRem)\n+      curSize = (UInt32)p->directInputRem;\n+    p->directInputRem -= curSize;\n+    p->streamPos += curSize;\n+    if (p->directInputRem == 0)\n+      p->streamEndWasReached = 1;\n+    return;\n+  }\n+  for (;;)\n+  {\n+    Byte *dest = p->buffer + (p->streamPos - p->pos);\n+    size_t size = (p->bufferBase + p->blockSize - dest);\n+    if (size == 0)\n+      return;\n+    p->result = p->stream->Read(p->stream, dest, &size);\n+    if (p->result != SZ_OK)\n+      return;\n+    if (size == 0)\n+    {\n+      p->streamEndWasReached = 1;\n+      return;\n+    }\n+    p->streamPos += (UInt32)size;\n+    if (p->streamPos - p->pos > p->keepSizeAfter)\n+      return;\n+  }\n+}\n+\n+void MatchFinder_MoveBlock(CMatchFinder *p)\n+{\n+  memmove(p->bufferBase,\n+    p->buffer - p->keepSizeBefore,\n+    (size_t)(p->streamPos - p->pos + p->keepSizeBefore));\n+  p->buffer = p->bufferBase + p->keepSizeBefore;\n+}\n+\n+int MatchFinder_NeedMove(CMatchFinder *p)\n+{\n+  if (p->directInput)\n+    return 0;\n+  /* if (p->streamEndWasReached) return 0; */\n+  return ((size_t)(p->bufferBase + p->blockSize - p->buffer) <= p->keepSizeAfter);\n+}\n+\n+void MatchFinder_ReadIfRequired(CMatchFinder *p)\n+{\n+  if (p->streamEndWasReached)\n+    return;\n+  if (p->keepSizeAfter >= p->streamPos - p->pos)\n+    MatchFinder_ReadBlock(p);\n+}\n+\n+static void MatchFinder_CheckAndMoveAndRead(CMatchFinder *p)\n+{\n+  if (MatchFinder_NeedMove(p))\n+    MatchFinder_MoveBlock(p);\n+  MatchFinder_ReadBlock(p);\n+}\n+\n+static void MatchFinder_SetDefaultSettings(CMatchFinder *p)\n+{\n+  p->cutValue = 32;\n+  p->btMode = 1;\n+  p->numHashBytes = 4;\n+  p->bigHash = 0;\n+}\n+\n+#define kCrcPoly 0xEDB88320\n+\n+void MatchFinder_Construct(CMatchFinder *p)\n+{\n+  UInt32 i;\n+  p->bufferBase = 0;\n+  p->directInput = 0;\n+  p->hash = 0;\n+  MatchFinder_SetDefaultSettings(p);\n+\n+  for (i = 0; i < 256; i++)\n+  {\n+    UInt32 r = i;\n+    int j;\n+    for (j = 0; j < 8; j++)\n+      r = (r >> 1) ^ (kCrcPoly & ~((r & 1) - 1));\n+    p->crc[i] = r;\n+  }\n+}\n+\n+static void MatchFinder_FreeThisClassMemory(CMatchFinder *p, ISzAlloc *alloc)\n+{\n+  alloc->Free(alloc, p->hash);\n+  p->hash = 0;\n+}\n+\n+void MatchFinder_Free(CMatchFinder *p, ISzAlloc *alloc)\n+{\n+  MatchFinder_FreeThisClassMemory(p, alloc);\n+  LzInWindow_Free(p, alloc);\n+}\n+\n+static CLzRef* AllocRefs(UInt32 num, ISzAlloc *alloc)\n+{\n+  size_t sizeInBytes = (size_t)num * sizeof(CLzRef);\n+  if (sizeInBytes / sizeof(CLzRef) != num)\n+    return 0;\n+  return (CLzRef *)alloc->Alloc(alloc, sizeInBytes);\n+}\n+\n+int MatchFinder_Create(CMatchFinder *p, UInt32 historySize,\n+    UInt32 keepAddBufferBefore, UInt32 matchMaxLen, UInt32 keepAddBufferAfter,\n+    ISzAlloc *alloc)\n+{\n+  UInt32 sizeReserv;\n+  if (historySize > kMaxHistorySize)\n+  {\n+    MatchFinder_Free(p, alloc);\n+    return 0;\n+  }\n+  sizeReserv = historySize >> 1;\n+  if (historySize > ((UInt32)2 << 30))\n+    sizeReserv = historySize >> 2;\n+  sizeReserv += (keepAddBufferBefore + matchMaxLen + keepAddBufferAfter) / 2 + (1 << 19);\n+\n+  p->keepSizeBefore = historySize + keepAddBufferBefore + 1;\n+  p->keepSizeAfter = matchMaxLen + keepAddBufferAfter;\n+  /* we need one additional byte, since we use MoveBlock after pos++ and before dictionary using */\n+  if (LzInWindow_Create(p, sizeReserv, alloc))\n+  {\n+    UInt32 newCyclicBufferSize = historySize + 1;\n+    UInt32 hs;\n+    p->matchMaxLen = matchMaxLen;\n+    {\n+      p->fixedHashSize = 0;\n+      if (p->numHashBytes == 2)\n+        hs = (1 << 16) - 1;\n+      else\n+      {\n+        hs = historySize - 1;\n+        hs |= (hs >> 1);\n+        hs |= (hs >> 2);\n+        hs |= (hs >> 4);\n+        hs |= (hs >> 8);\n+        hs >>= 1;\n+        hs |= 0xFFFF; /* don't change it! It's required for Deflate */\n+        if (hs > (1 << 24))\n+        {\n+          if (p->numHashBytes == 3)\n+            hs = (1 << 24) - 1;\n+          else\n+            hs >>= 1;\n+        }\n+      }\n+      p->hashMask = hs;\n+      hs++;\n+      if (p->numHashBytes > 2) p->fixedHashSize += kHash2Size;\n+      if (p->numHashBytes > 3) p->fixedHashSize += kHash3Size;\n+      if (p->numHashBytes > 4) p->fixedHashSize += kHash4Size;\n+      hs += p->fixedHashSize;\n+    }\n+\n+    {\n+      UInt32 prevSize = p->hashSizeSum + p->numSons;\n+      UInt32 newSize;\n+      p->historySize = historySize;\n+      p->hashSizeSum = hs;\n+      p->cyclicBufferSize = newCyclicBufferSize;\n+      p->numSons = (p->btMode ? newCyclicBufferSize * 2 : newCyclicBufferSize);\n+      newSize = p->hashSizeSum + p->numSons;\n+      if (p->hash != 0 && prevSize == newSize)\n+        return 1;\n+      MatchFinder_FreeThisClassMemory(p, alloc);\n+      p->hash = AllocRefs(newSize, alloc);\n+      if (p->hash != 0)\n+      {\n+        p->son = p->hash + p->hashSizeSum;\n+        return 1;\n+      }\n+    }\n+  }\n+  MatchFinder_Free(p, alloc);\n+  return 0;\n+}\n+\n+static void MatchFinder_SetLimits(CMatchFinder *p)\n+{\n+  UInt32 limit = kMaxValForNormalize - p->pos;\n+  UInt32 limit2 = p->cyclicBufferSize - p->cyclicBufferPos;\n+  if (limit2 < limit)\n+    limit = limit2;\n+  limit2 = p->streamPos - p->pos;\n+  if (limit2 <= p->keepSizeAfter)\n+  {\n+    if (limit2 > 0)\n+      limit2 = 1;\n+  }\n+  else\n+    limit2 -= p->keepSizeAfter;\n+  if (limit2 < limit)\n+    limit = limit2;\n+  {\n+    UInt32 lenLimit = p->streamPos - p->pos;\n+    if (lenLimit > p->matchMaxLen)\n+      lenLimit = p->matchMaxLen;\n+    p->lenLimit = lenLimit;\n+  }\n+  p->posLimit = p->pos + limit;\n+}\n+\n+void MatchFinder_Init(CMatchFinder *p)\n+{\n+  UInt32 i;\n+  for (i = 0; i < p->hashSizeSum; i++)\n+    p->hash[i] = kEmptyHashValue;\n+  p->cyclicBufferPos = 0;\n+  p->buffer = p->bufferBase;\n+  p->pos = p->streamPos = p->cyclicBufferSize;\n+  p->result = SZ_OK;\n+  p->streamEndWasReached = 0;\n+  MatchFinder_ReadBlock(p);\n+  MatchFinder_SetLimits(p);\n+}\n+\n+static UInt32 MatchFinder_GetSubValue(CMatchFinder *p)\n+{\n+  return (p->pos - p->historySize - 1) & kNormalizeMask;\n+}\n+\n+void MatchFinder_Normalize3(UInt32 subValue, CLzRef *items, UInt32 numItems)\n+{\n+  UInt32 i;\n+  for (i = 0; i < numItems; i++)\n+  {\n+    UInt32 value = items[i];\n+    if (value <= subValue)\n+      value = kEmptyHashValue;\n+    else\n+      value -= subValue;\n+    items[i] = value;\n+  }\n+}\n+\n+static void MatchFinder_Normalize(CMatchFinder *p)\n+{\n+  UInt32 subValue = MatchFinder_GetSubValue(p);\n+  MatchFinder_Normalize3(subValue, p->hash, p->hashSizeSum + p->numSons);\n+  MatchFinder_ReduceOffsets(p, subValue);\n+}\n+\n+static void MatchFinder_CheckLimits(CMatchFinder *p)\n+{\n+  if (p->pos == kMaxValForNormalize)\n+    MatchFinder_Normalize(p);\n+  if (!p->streamEndWasReached && p->keepSizeAfter == p->streamPos - p->pos)\n+    MatchFinder_CheckAndMoveAndRead(p);\n+  if (p->cyclicBufferPos == p->cyclicBufferSize)\n+    p->cyclicBufferPos = 0;\n+  MatchFinder_SetLimits(p);\n+}\n+\n+static UInt32 * Hc_GetMatchesSpec(UInt32 lenLimit, UInt32 curMatch, UInt32 pos, const Byte *cur, CLzRef *son,\n+    UInt32 _cyclicBufferPos, UInt32 _cyclicBufferSize, UInt32 cutValue,\n+    UInt32 *distances, UInt32 maxLen)\n+{\n+  son[_cyclicBufferPos] = curMatch;\n+  for (;;)\n+  {\n+    UInt32 delta = pos - curMatch;\n+    if (cutValue-- == 0 || delta >= _cyclicBufferSize)\n+      return distances;\n+    {\n+      const Byte *pb = cur - delta;\n+      curMatch = son[_cyclicBufferPos - delta + ((delta > _cyclicBufferPos) ? _cyclicBufferSize : 0)];\n+      if (pb[maxLen] == cur[maxLen] && *pb == *cur)\n+      {\n+        UInt32 len = 0;\n+        while (++len != lenLimit)\n+          if (pb[len] != cur[len])\n+            break;\n+        if (maxLen < len)\n+        {\n+          *distances++ = maxLen = len;\n+          *distances++ = delta - 1;\n+          if (len == lenLimit)\n+            return distances;\n+        }\n+      }\n+    }\n+  }\n+}\n+\n+UInt32 * GetMatchesSpec1(UInt32 lenLimit, UInt32 curMatch, UInt32 pos, const Byte *cur, CLzRef *son,\n+    UInt32 _cyclicBufferPos, UInt32 _cyclicBufferSize, UInt32 cutValue,\n+    UInt32 *distances, UInt32 maxLen)\n+{\n+  CLzRef *ptr0 = son + (_cyclicBufferPos << 1) + 1;\n+  CLzRef *ptr1 = son + (_cyclicBufferPos << 1);\n+  UInt32 len0 = 0, len1 = 0;\n+  for (;;)\n+  {\n+    UInt32 delta = pos - curMatch;\n+    if (cutValue-- == 0 || delta >= _cyclicBufferSize)\n+    {\n+      *ptr0 = *ptr1 = kEmptyHashValue;\n+      return distances;\n+    }\n+    {\n+      CLzRef *pair = son + ((_cyclicBufferPos - delta + ((delta > _cyclicBufferPos) ? _cyclicBufferSize : 0)) << 1);\n+      const Byte *pb = cur - delta;\n+      UInt32 len = (len0 < len1 ? len0 : len1);\n+      if (pb[len] == cur[len])\n+      {\n+        if (++len != lenLimit && pb[len] == cur[len])\n+          while (++len != lenLimit)\n+            if (pb[len] != cur[len])\n+              break;\n+        if (maxLen < len)\n+        {\n+          *distances++ = maxLen = len;\n+          *distances++ = delta - 1;\n+          if (len == lenLimit)\n+          {\n+            *ptr1 = pair[0];\n+            *ptr0 = pair[1];\n+            return distances;\n+          }\n+        }\n+      }\n+      if (pb[len] < cur[len])\n+      {\n+        *ptr1 = curMatch;\n+        ptr1 = pair + 1;\n+        curMatch = *ptr1;\n+        len1 = len;\n+      }\n+      else\n+      {\n+        *ptr0 = curMatch;\n+        ptr0 = pair;\n+        curMatch = *ptr0;\n+        len0 = len;\n+      }\n+    }\n+  }\n+}\n+\n+static void SkipMatchesSpec(UInt32 lenLimit, UInt32 curMatch, UInt32 pos, const Byte *cur, CLzRef *son,\n+    UInt32 _cyclicBufferPos, UInt32 _cyclicBufferSize, UInt32 cutValue)\n+{\n+  CLzRef *ptr0 = son + (_cyclicBufferPos << 1) + 1;\n+  CLzRef *ptr1 = son + (_cyclicBufferPos << 1);\n+  UInt32 len0 = 0, len1 = 0;\n+  for (;;)\n+  {\n+    UInt32 delta = pos - curMatch;\n+    if (cutValue-- == 0 || delta >= _cyclicBufferSize)\n+    {\n+      *ptr0 = *ptr1 = kEmptyHashValue;\n+      return;\n+    }\n+    {\n+      CLzRef *pair = son + ((_cyclicBufferPos - delta + ((delta > _cyclicBufferPos) ? _cyclicBufferSize : 0)) << 1);\n+      const Byte *pb = cur - delta;\n+      UInt32 len = (len0 < len1 ? len0 : len1);\n+      if (pb[len] == cur[len])\n+      {\n+        while (++len != lenLimit)\n+          if (pb[len] != cur[len])\n+            break;\n+        {\n+          if (len == lenLimit)\n+          {\n+            *ptr1 = pair[0];\n+            *ptr0 = pair[1];\n+            return;\n+          }\n+        }\n+      }\n+      if (pb[len] < cur[len])\n+      {\n+        *ptr1 = curMatch;\n+        ptr1 = pair + 1;\n+        curMatch = *ptr1;\n+        len1 = len;\n+      }\n+      else\n+      {\n+        *ptr0 = curMatch;\n+        ptr0 = pair;\n+        curMatch = *ptr0;\n+        len0 = len;\n+      }\n+    }\n+  }\n+}\n+\n+#define MOVE_POS \\\n+  ++p->cyclicBufferPos; \\\n+  p->buffer++; \\\n+  if (++p->pos == p->posLimit) MatchFinder_CheckLimits(p);\n+\n+#define MOVE_POS_RET MOVE_POS return offset;\n+\n+static void MatchFinder_MovePos(CMatchFinder *p) { MOVE_POS; }\n+\n+#define GET_MATCHES_HEADER2(minLen, ret_op) \\\n+  UInt32 lenLimit; UInt32 hashValue; const Byte *cur; UInt32 curMatch; \\\n+  lenLimit = p->lenLimit; { if (lenLimit < minLen) { MatchFinder_MovePos(p); ret_op; }} \\\n+  cur = p->buffer;\n+\n+#define GET_MATCHES_HEADER(minLen) GET_MATCHES_HEADER2(minLen, return 0)\n+#define SKIP_HEADER(minLen)        GET_MATCHES_HEADER2(minLen, continue)\n+\n+#define MF_PARAMS(p) p->pos, p->buffer, p->son, p->cyclicBufferPos, p->cyclicBufferSize, p->cutValue\n+\n+#define GET_MATCHES_FOOTER(offset, maxLen) \\\n+  offset = (UInt32)(GetMatchesSpec1(lenLimit, curMatch, MF_PARAMS(p), \\\n+  distances + offset, maxLen) - distances); MOVE_POS_RET;\n+\n+#define SKIP_FOOTER \\\n+  SkipMatchesSpec(lenLimit, curMatch, MF_PARAMS(p)); MOVE_POS;\n+\n+static UInt32 Bt2_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances)\n+{\n+  UInt32 offset;\n+  GET_MATCHES_HEADER(2)\n+  HASH2_CALC;\n+  curMatch = p->hash[hashValue];\n+  p->hash[hashValue] = p->pos;\n+  offset = 0;\n+  GET_MATCHES_FOOTER(offset, 1)\n+}\n+\n+UInt32 Bt3Zip_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances)\n+{\n+  UInt32 offset;\n+  GET_MATCHES_HEADER(3)\n+  HASH_ZIP_CALC;\n+  curMatch = p->hash[hashValue];\n+  p->hash[hashValue] = p->pos;\n+  offset = 0;\n+  GET_MATCHES_FOOTER(offset, 2)\n+}\n+\n+static UInt32 Bt3_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances)\n+{\n+  UInt32 hash2Value, delta2, maxLen, offset;\n+  GET_MATCHES_HEADER(3)\n+\n+  HASH3_CALC;\n+\n+  delta2 = p->pos - p->hash[hash2Value];\n+  curMatch = p->hash[kFix3HashSize + hashValue];\n+\n+  p->hash[hash2Value] =\n+  p->hash[kFix3HashSize + hashValue] = p->pos;\n+\n+\n+  maxLen = 2;\n+  offset = 0;\n+  if (delta2 < p->cyclicBufferSize && *(cur - delta2) == *cur)\n+  {\n+    for (; maxLen != lenLimit; maxLen++)\n+      if (cur[(ptrdiff_t)maxLen - delta2] != cur[maxLen])\n+        break;\n+    distances[0] = maxLen;\n+    distances[1] = delta2 - 1;\n+    offset = 2;\n+    if (maxLen == lenLimit)\n+    {\n+      SkipMatchesSpec(lenLimit, curMatch, MF_PARAMS(p));\n+      MOVE_POS_RET;\n+    }\n+  }\n+  GET_MATCHES_FOOTER(offset, maxLen)\n+}\n+\n+static UInt32 Bt4_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances)\n+{\n+  UInt32 hash2Value, hash3Value, delta2, delta3, maxLen, offset;\n+  GET_MATCHES_HEADER(4)\n+\n+  HASH4_CALC;\n+\n+  delta2 = p->pos - p->hash[                hash2Value];\n+  delta3 = p->pos - p->hash[kFix3HashSize + hash3Value];\n+  curMatch = p->hash[kFix4HashSize + hashValue];\n+\n+  p->hash[                hash2Value] =\n+  p->hash[kFix3HashSize + hash3Value] =\n+  p->hash[kFix4HashSize + hashValue] = p->pos;\n+\n+  maxLen = 1;\n+  offset = 0;\n+  if (delta2 < p->cyclicBufferSize && *(cur - delta2) == *cur)\n+  {\n+    distances[0] = maxLen = 2;\n+    distances[1] = delta2 - 1;\n+    offset = 2;\n+  }\n+  if (delta2 != delta3 && delta3 < p->cyclicBufferSize && *(cur - delta3) == *cur)\n+  {\n+    maxLen = 3;\n+    distances[offset + 1] = delta3 - 1;\n+    offset += 2;\n+    delta2 = delta3;\n+  }\n+  if (offset != 0)\n+  {\n+    for (; maxLen != lenLimit; maxLen++)\n+      if (cur[(ptrdiff_t)maxLen - delta2] != cur[maxLen])\n+        break;\n+    distances[offset - 2] = maxLen;\n+    if (maxLen == lenLimit)\n+    {\n+      SkipMatchesSpec(lenLimit, curMatch, MF_PARAMS(p));\n+      MOVE_POS_RET;\n+    }\n+  }\n+  if (maxLen < 3)\n+    maxLen = 3;\n+  GET_MATCHES_FOOTER(offset, maxLen)\n+}\n+\n+static UInt32 Hc4_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances)\n+{\n+  UInt32 hash2Value, hash3Value, delta2, delta3, maxLen, offset;\n+  GET_MATCHES_HEADER(4)\n+\n+  HASH4_CALC;\n+\n+  delta2 = p->pos - p->hash[                hash2Value];\n+  delta3 = p->pos - p->hash[kFix3HashSize + hash3Value];\n+  curMatch = p->hash[kFix4HashSize + hashValue];\n+\n+  p->hash[                hash2Value] =\n+  p->hash[kFix3HashSize + hash3Value] =\n+  p->hash[kFix4HashSize + hashValue] = p->pos;\n+\n+  maxLen = 1;\n+  offset = 0;\n+  if (delta2 < p->cyclicBufferSize && *(cur - delta2) == *cur)\n+  {\n+    distances[0] = maxLen = 2;\n+    distances[1] = delta2 - 1;\n+    offset = 2;\n+  }\n+  if (delta2 != delta3 && delta3 < p->cyclicBufferSize && *(cur - delta3) == *cur)\n+  {\n+    maxLen = 3;\n+    distances[offset + 1] = delta3 - 1;\n+    offset += 2;\n+    delta2 = delta3;\n+  }\n+  if (offset != 0)\n+  {\n+    for (; maxLen != lenLimit; maxLen++)\n+      if (cur[(ptrdiff_t)maxLen - delta2] != cur[maxLen])\n+        break;\n+    distances[offset - 2] = maxLen;\n+    if (maxLen == lenLimit)\n+    {\n+      p->son[p->cyclicBufferPos] = curMatch;\n+      MOVE_POS_RET;\n+    }\n+  }\n+  if (maxLen < 3)\n+    maxLen = 3;\n+  offset = (UInt32)(Hc_GetMatchesSpec(lenLimit, curMatch, MF_PARAMS(p),\n+    distances + offset, maxLen) - (distances));\n+  MOVE_POS_RET\n+}\n+\n+UInt32 Hc3Zip_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances)\n+{\n+  UInt32 offset;\n+  GET_MATCHES_HEADER(3)\n+  HASH_ZIP_CALC;\n+  curMatch = p->hash[hashValue];\n+  p->hash[hashValue] = p->pos;\n+  offset = (UInt32)(Hc_GetMatchesSpec(lenLimit, curMatch, MF_PARAMS(p),\n+    distances, 2) - (distances));\n+  MOVE_POS_RET\n+}\n+\n+static void Bt2_MatchFinder_Skip(CMatchFinder *p, UInt32 num)\n+{\n+  do\n+  {\n+    SKIP_HEADER(2)\n+    HASH2_CALC;\n+    curMatch = p->hash[hashValue];\n+    p->hash[hashValue] = p->pos;\n+    SKIP_FOOTER\n+  }\n+  while (--num != 0);\n+}\n+\n+void Bt3Zip_MatchFinder_Skip(CMatchFinder *p, UInt32 num)\n+{\n+  do\n+  {\n+    SKIP_HEADER(3)\n+    HASH_ZIP_CALC;\n+    curMatch = p->hash[hashValue];\n+    p->hash[hashValue] = p->pos;\n+    SKIP_FOOTER\n+  }\n+  while (--num != 0);\n+}\n+\n+static void Bt3_MatchFinder_Skip(CMatchFinder *p, UInt32 num)\n+{\n+  do\n+  {\n+    UInt32 hash2Value;\n+    SKIP_HEADER(3)\n+    HASH3_CALC;\n+    curMatch = p->hash[kFix3HashSize + hashValue];\n+    p->hash[hash2Value] =\n+    p->hash[kFix3HashSize + hashValue] = p->pos;\n+    SKIP_FOOTER\n+  }\n+  while (--num != 0);\n+}\n+\n+static void Bt4_MatchFinder_Skip(CMatchFinder *p, UInt32 num)\n+{\n+  do\n+  {\n+    UInt32 hash2Value, hash3Value;\n+    SKIP_HEADER(4)\n+    HASH4_CALC;\n+    curMatch = p->hash[kFix4HashSize + hashValue];\n+    p->hash[                hash2Value] =\n+    p->hash[kFix3HashSize + hash3Value] = p->pos;\n+    p->hash[kFix4HashSize + hashValue] = p->pos;\n+    SKIP_FOOTER\n+  }\n+  while (--num != 0);\n+}\n+\n+static void Hc4_MatchFinder_Skip(CMatchFinder *p, UInt32 num)\n+{\n+  do\n+  {\n+    UInt32 hash2Value, hash3Value;\n+    SKIP_HEADER(4)\n+    HASH4_CALC;\n+    curMatch = p->hash[kFix4HashSize + hashValue];\n+    p->hash[                hash2Value] =\n+    p->hash[kFix3HashSize + hash3Value] =\n+    p->hash[kFix4HashSize + hashValue] = p->pos;\n+    p->son[p->cyclicBufferPos] = curMatch;\n+    MOVE_POS\n+  }\n+  while (--num != 0);\n+}\n+\n+void Hc3Zip_MatchFinder_Skip(CMatchFinder *p, UInt32 num)\n+{\n+  do\n+  {\n+    SKIP_HEADER(3)\n+    HASH_ZIP_CALC;\n+    curMatch = p->hash[hashValue];\n+    p->hash[hashValue] = p->pos;\n+    p->son[p->cyclicBufferPos] = curMatch;\n+    MOVE_POS\n+  }\n+  while (--num != 0);\n+}\n+\n+void MatchFinder_CreateVTable(CMatchFinder *p, IMatchFinder *vTable)\n+{\n+  vTable->Init = (Mf_Init_Func)MatchFinder_Init;\n+  vTable->GetIndexByte = (Mf_GetIndexByte_Func)MatchFinder_GetIndexByte;\n+  vTable->GetNumAvailableBytes = (Mf_GetNumAvailableBytes_Func)MatchFinder_GetNumAvailableBytes;\n+  vTable->GetPointerToCurrentPos = (Mf_GetPointerToCurrentPos_Func)MatchFinder_GetPointerToCurrentPos;\n+  if (!p->btMode)\n+  {\n+    vTable->GetMatches = (Mf_GetMatches_Func)Hc4_MatchFinder_GetMatches;\n+    vTable->Skip = (Mf_Skip_Func)Hc4_MatchFinder_Skip;\n+  }\n+  else if (p->numHashBytes == 2)\n+  {\n+    vTable->GetMatches = (Mf_GetMatches_Func)Bt2_MatchFinder_GetMatches;\n+    vTable->Skip = (Mf_Skip_Func)Bt2_MatchFinder_Skip;\n+  }\n+  else if (p->numHashBytes == 3)\n+  {\n+    vTable->GetMatches = (Mf_GetMatches_Func)Bt3_MatchFinder_GetMatches;\n+    vTable->Skip = (Mf_Skip_Func)Bt3_MatchFinder_Skip;\n+  }\n+  else\n+  {\n+    vTable->GetMatches = (Mf_GetMatches_Func)Bt4_MatchFinder_GetMatches;\n+    vTable->Skip = (Mf_Skip_Func)Bt4_MatchFinder_Skip;\n+  }\n+}\n--- /dev/null\n+++ b/lib/lzma/LzmaDec.c\n@@ -0,0 +1,999 @@\n+/* LzmaDec.c -- LZMA Decoder\n+2009-09-20 : Igor Pavlov : Public domain */\n+\n+#include \"LzmaDec.h\"\n+\n+#include <string.h>\n+\n+#define kNumTopBits 24\n+#define kTopValue ((UInt32)1 << kNumTopBits)\n+\n+#define kNumBitModelTotalBits 11\n+#define kBitModelTotal (1 << kNumBitModelTotalBits)\n+#define kNumMoveBits 5\n+\n+#define RC_INIT_SIZE 5\n+\n+#define NORMALIZE if (range < kTopValue) { range <<= 8; code = (code << 8) | (*buf++); }\n+\n+#define IF_BIT_0(p) ttt = *(p); NORMALIZE; bound = (range >> kNumBitModelTotalBits) * ttt; if (code < bound)\n+#define UPDATE_0(p) range = bound; *(p) = (CLzmaProb)(ttt + ((kBitModelTotal - ttt) >> kNumMoveBits));\n+#define UPDATE_1(p) range -= bound; code -= bound; *(p) = (CLzmaProb)(ttt - (ttt >> kNumMoveBits));\n+#define GET_BIT2(p, i, A0, A1) IF_BIT_0(p) \\\n+  { UPDATE_0(p); i = (i + i); A0; } else \\\n+  { UPDATE_1(p); i = (i + i) + 1; A1; }\n+#define GET_BIT(p, i) GET_BIT2(p, i, ; , ;)\n+\n+#define TREE_GET_BIT(probs, i) { GET_BIT((probs + i), i); }\n+#define TREE_DECODE(probs, limit, i) \\\n+  { i = 1; do { TREE_GET_BIT(probs, i); } while (i < limit); i -= limit; }\n+\n+/* #define _LZMA_SIZE_OPT */\n+\n+#ifdef _LZMA_SIZE_OPT\n+#define TREE_6_DECODE(probs, i) TREE_DECODE(probs, (1 << 6), i)\n+#else\n+#define TREE_6_DECODE(probs, i) \\\n+  { i = 1; \\\n+  TREE_GET_BIT(probs, i); \\\n+  TREE_GET_BIT(probs, i); \\\n+  TREE_GET_BIT(probs, i); \\\n+  TREE_GET_BIT(probs, i); \\\n+  TREE_GET_BIT(probs, i); \\\n+  TREE_GET_BIT(probs, i); \\\n+  i -= 0x40; }\n+#endif\n+\n+#define NORMALIZE_CHECK if (range < kTopValue) { if (buf >= bufLimit) return DUMMY_ERROR; range <<= 8; code = (code << 8) | (*buf++); }\n+\n+#define IF_BIT_0_CHECK(p) ttt = *(p); NORMALIZE_CHECK; bound = (range >> kNumBitModelTotalBits) * ttt; if (code < bound)\n+#define UPDATE_0_CHECK range = bound;\n+#define UPDATE_1_CHECK range -= bound; code -= bound;\n+#define GET_BIT2_CHECK(p, i, A0, A1) IF_BIT_0_CHECK(p) \\\n+  { UPDATE_0_CHECK; i = (i + i); A0; } else \\\n+  { UPDATE_1_CHECK; i = (i + i) + 1; A1; }\n+#define GET_BIT_CHECK(p, i) GET_BIT2_CHECK(p, i, ; , ;)\n+#define TREE_DECODE_CHECK(probs, limit, i) \\\n+  { i = 1; do { GET_BIT_CHECK(probs + i, i) } while (i < limit); i -= limit; }\n+\n+\n+#define kNumPosBitsMax 4\n+#define kNumPosStatesMax (1 << kNumPosBitsMax)\n+\n+#define kLenNumLowBits 3\n+#define kLenNumLowSymbols (1 << kLenNumLowBits)\n+#define kLenNumMidBits 3\n+#define kLenNumMidSymbols (1 << kLenNumMidBits)\n+#define kLenNumHighBits 8\n+#define kLenNumHighSymbols (1 << kLenNumHighBits)\n+\n+#define LenChoice 0\n+#define LenChoice2 (LenChoice + 1)\n+#define LenLow (LenChoice2 + 1)\n+#define LenMid (LenLow + (kNumPosStatesMax << kLenNumLowBits))\n+#define LenHigh (LenMid + (kNumPosStatesMax << kLenNumMidBits))\n+#define kNumLenProbs (LenHigh + kLenNumHighSymbols)\n+\n+\n+#define kNumStates 12\n+#define kNumLitStates 7\n+\n+#define kStartPosModelIndex 4\n+#define kEndPosModelIndex 14\n+#define kNumFullDistances (1 << (kEndPosModelIndex >> 1))\n+\n+#define kNumPosSlotBits 6\n+#define kNumLenToPosStates 4\n+\n+#define kNumAlignBits 4\n+#define kAlignTableSize (1 << kNumAlignBits)\n+\n+#define kMatchMinLen 2\n+#define kMatchSpecLenStart (kMatchMinLen + kLenNumLowSymbols + kLenNumMidSymbols + kLenNumHighSymbols)\n+\n+#define IsMatch 0\n+#define IsRep (IsMatch + (kNumStates << kNumPosBitsMax))\n+#define IsRepG0 (IsRep + kNumStates)\n+#define IsRepG1 (IsRepG0 + kNumStates)\n+#define IsRepG2 (IsRepG1 + kNumStates)\n+#define IsRep0Long (IsRepG2 + kNumStates)\n+#define PosSlot (IsRep0Long + (kNumStates << kNumPosBitsMax))\n+#define SpecPos (PosSlot + (kNumLenToPosStates << kNumPosSlotBits))\n+#define Align (SpecPos + kNumFullDistances - kEndPosModelIndex)\n+#define LenCoder (Align + kAlignTableSize)\n+#define RepLenCoder (LenCoder + kNumLenProbs)\n+#define Literal (RepLenCoder + kNumLenProbs)\n+\n+#define LZMA_BASE_SIZE 1846\n+#define LZMA_LIT_SIZE 768\n+\n+#define LzmaProps_GetNumProbs(p) ((UInt32)LZMA_BASE_SIZE + (LZMA_LIT_SIZE << ((p)->lc + (p)->lp)))\n+\n+#if Literal != LZMA_BASE_SIZE\n+StopCompilingDueBUG\n+#endif\n+\n+#define LZMA_DIC_MIN (1 << 12)\n+\n+/* First LZMA-symbol is always decoded.\n+And it decodes new LZMA-symbols while (buf < bufLimit), but \"buf\" is without last normalization\n+Out:\n+  Result:\n+    SZ_OK - OK\n+    SZ_ERROR_DATA - Error\n+  p->remainLen:\n+    < kMatchSpecLenStart : normal remain\n+    = kMatchSpecLenStart : finished\n+    = kMatchSpecLenStart + 1 : Flush marker\n+    = kMatchSpecLenStart + 2 : State Init Marker\n+*/\n+\n+static int MY_FAST_CALL LzmaDec_DecodeReal(CLzmaDec *p, SizeT limit, const Byte *bufLimit)\n+{\n+  CLzmaProb *probs = p->probs;\n+\n+  unsigned state = p->state;\n+  UInt32 rep0 = p->reps[0], rep1 = p->reps[1], rep2 = p->reps[2], rep3 = p->reps[3];\n+  unsigned pbMask = ((unsigned)1 << (p->prop.pb)) - 1;\n+  unsigned lpMask = ((unsigned)1 << (p->prop.lp)) - 1;\n+  unsigned lc = p->prop.lc;\n+\n+  Byte *dic = p->dic;\n+  SizeT dicBufSize = p->dicBufSize;\n+  SizeT dicPos = p->dicPos;\n+\n+  UInt32 processedPos = p->processedPos;\n+  UInt32 checkDicSize = p->checkDicSize;\n+  unsigned len = 0;\n+\n+  const Byte *buf = p->buf;\n+  UInt32 range = p->range;\n+  UInt32 code = p->code;\n+\n+  do\n+  {\n+    CLzmaProb *prob;\n+    UInt32 bound;\n+    unsigned ttt;\n+    unsigned posState = processedPos & pbMask;\n+\n+    prob = probs + IsMatch + (state << kNumPosBitsMax) + posState;\n+    IF_BIT_0(prob)\n+    {\n+      unsigned symbol;\n+      UPDATE_0(prob);\n+      prob = probs + Literal;\n+      if (checkDicSize != 0 || processedPos != 0)\n+        prob += (LZMA_LIT_SIZE * (((processedPos & lpMask) << lc) +\n+        (dic[(dicPos == 0 ? dicBufSize : dicPos) - 1] >> (8 - lc))));\n+\n+      if (state < kNumLitStates)\n+      {\n+        state -= (state < 4) ? state : 3;\n+        symbol = 1;\n+        do { GET_BIT(prob + symbol, symbol) } while (symbol < 0x100);\n+      }\n+      else\n+      {\n+        unsigned matchByte = p->dic[(dicPos - rep0) + ((dicPos < rep0) ? dicBufSize : 0)];\n+        unsigned offs = 0x100;\n+        state -= (state < 10) ? 3 : 6;\n+        symbol = 1;\n+        do\n+        {\n+          unsigned bit;\n+          CLzmaProb *probLit;\n+          matchByte <<= 1;\n+          bit = (matchByte & offs);\n+          probLit = prob + offs + bit + symbol;\n+          GET_BIT2(probLit, symbol, offs &= ~bit, offs &= bit)\n+        }\n+        while (symbol < 0x100);\n+      }\n+      dic[dicPos++] = (Byte)symbol;\n+      processedPos++;\n+      continue;\n+    }\n+    else\n+    {\n+      UPDATE_1(prob);\n+      prob = probs + IsRep + state;\n+      IF_BIT_0(prob)\n+      {\n+        UPDATE_0(prob);\n+        state += kNumStates;\n+        prob = probs + LenCoder;\n+      }\n+      else\n+      {\n+        UPDATE_1(prob);\n+        if (checkDicSize == 0 && processedPos == 0)\n+          return SZ_ERROR_DATA;\n+        prob = probs + IsRepG0 + state;\n+        IF_BIT_0(prob)\n+        {\n+          UPDATE_0(prob);\n+          prob = probs + IsRep0Long + (state << kNumPosBitsMax) + posState;\n+          IF_BIT_0(prob)\n+          {\n+            UPDATE_0(prob);\n+            dic[dicPos] = dic[(dicPos - rep0) + ((dicPos < rep0) ? dicBufSize : 0)];\n+            dicPos++;\n+            processedPos++;\n+            state = state < kNumLitStates ? 9 : 11;\n+            continue;\n+          }\n+          UPDATE_1(prob);\n+        }\n+        else\n+        {\n+          UInt32 distance;\n+          UPDATE_1(prob);\n+          prob = probs + IsRepG1 + state;\n+          IF_BIT_0(prob)\n+          {\n+            UPDATE_0(prob);\n+            distance = rep1;\n+          }\n+          else\n+          {\n+            UPDATE_1(prob);\n+            prob = probs + IsRepG2 + state;\n+            IF_BIT_0(prob)\n+            {\n+              UPDATE_0(prob);\n+              distance = rep2;\n+            }\n+            else\n+            {\n+              UPDATE_1(prob);\n+              distance = rep3;\n+              rep3 = rep2;\n+            }\n+            rep2 = rep1;\n+          }\n+          rep1 = rep0;\n+          rep0 = distance;\n+        }\n+        state = state < kNumLitStates ? 8 : 11;\n+        prob = probs + RepLenCoder;\n+      }\n+      {\n+        unsigned limit, offset;\n+        CLzmaProb *probLen = prob + LenChoice;\n+        IF_BIT_0(probLen)\n+        {\n+          UPDATE_0(probLen);\n+          probLen = prob + LenLow + (posState << kLenNumLowBits);\n+          offset = 0;\n+          limit = (1 << kLenNumLowBits);\n+        }\n+        else\n+        {\n+          UPDATE_1(probLen);\n+          probLen = prob + LenChoice2;\n+          IF_BIT_0(probLen)\n+          {\n+            UPDATE_0(probLen);\n+            probLen = prob + LenMid + (posState << kLenNumMidBits);\n+            offset = kLenNumLowSymbols;\n+            limit = (1 << kLenNumMidBits);\n+          }\n+          else\n+          {\n+            UPDATE_1(probLen);\n+            probLen = prob + LenHigh;\n+            offset = kLenNumLowSymbols + kLenNumMidSymbols;\n+            limit = (1 << kLenNumHighBits);\n+          }\n+        }\n+        TREE_DECODE(probLen, limit, len);\n+        len += offset;\n+      }\n+\n+      if (state >= kNumStates)\n+      {\n+        UInt32 distance;\n+        prob = probs + PosSlot +\n+            ((len < kNumLenToPosStates ? len : kNumLenToPosStates - 1) << kNumPosSlotBits);\n+        TREE_6_DECODE(prob, distance);\n+        if (distance >= kStartPosModelIndex)\n+        {\n+          unsigned posSlot = (unsigned)distance;\n+          int numDirectBits = (int)(((distance >> 1) - 1));\n+          distance = (2 | (distance & 1));\n+          if (posSlot < kEndPosModelIndex)\n+          {\n+            distance <<= numDirectBits;\n+            prob = probs + SpecPos + distance - posSlot - 1;\n+            {\n+              UInt32 mask = 1;\n+              unsigned i = 1;\n+              do\n+              {\n+                GET_BIT2(prob + i, i, ; , distance |= mask);\n+                mask <<= 1;\n+              }\n+              while (--numDirectBits != 0);\n+            }\n+          }\n+          else\n+          {\n+            numDirectBits -= kNumAlignBits;\n+            do\n+            {\n+              NORMALIZE\n+              range >>= 1;\n+\n+              {\n+                UInt32 t;\n+                code -= range;\n+                t = (0 - ((UInt32)code >> 31)); /* (UInt32)((Int32)code >> 31) */\n+                distance = (distance << 1) + (t + 1);\n+                code += range & t;\n+              }\n+              /*\n+              distance <<= 1;\n+              if (code >= range)\n+              {\n+                code -= range;\n+                distance |= 1;\n+              }\n+              */\n+            }\n+            while (--numDirectBits != 0);\n+            prob = probs + Align;\n+            distance <<= kNumAlignBits;\n+            {\n+              unsigned i = 1;\n+              GET_BIT2(prob + i, i, ; , distance |= 1);\n+              GET_BIT2(prob + i, i, ; , distance |= 2);\n+              GET_BIT2(prob + i, i, ; , distance |= 4);\n+              GET_BIT2(prob + i, i, ; , distance |= 8);\n+            }\n+            if (distance == (UInt32)0xFFFFFFFF)\n+            {\n+              len += kMatchSpecLenStart;\n+              state -= kNumStates;\n+              break;\n+            }\n+          }\n+        }\n+        rep3 = rep2;\n+        rep2 = rep1;\n+        rep1 = rep0;\n+        rep0 = distance + 1;\n+        if (checkDicSize == 0)\n+        {\n+          if (distance >= processedPos)\n+            return SZ_ERROR_DATA;\n+        }\n+        else if (distance >= checkDicSize)\n+          return SZ_ERROR_DATA;\n+        state = (state < kNumStates + kNumLitStates) ? kNumLitStates : kNumLitStates + 3;\n+      }\n+\n+      len += kMatchMinLen;\n+\n+      if (limit == dicPos)\n+        return SZ_ERROR_DATA;\n+      {\n+        SizeT rem = limit - dicPos;\n+        unsigned curLen = ((rem < len) ? (unsigned)rem : len);\n+        SizeT pos = (dicPos - rep0) + ((dicPos < rep0) ? dicBufSize : 0);\n+\n+        processedPos += curLen;\n+\n+        len -= curLen;\n+        if (pos + curLen <= dicBufSize)\n+        {\n+          Byte *dest = dic + dicPos;\n+          ptrdiff_t src = (ptrdiff_t)pos - (ptrdiff_t)dicPos;\n+          const Byte *lim = dest + curLen;\n+          dicPos += curLen;\n+          do\n+            *(dest) = (Byte)*(dest + src);\n+          while (++dest != lim);\n+        }\n+        else\n+        {\n+          do\n+          {\n+            dic[dicPos++] = dic[pos];\n+            if (++pos == dicBufSize)\n+              pos = 0;\n+          }\n+          while (--curLen != 0);\n+        }\n+      }\n+    }\n+  }\n+  while (dicPos < limit && buf < bufLimit);\n+  NORMALIZE;\n+  p->buf = buf;\n+  p->range = range;\n+  p->code = code;\n+  p->remainLen = len;\n+  p->dicPos = dicPos;\n+  p->processedPos = processedPos;\n+  p->reps[0] = rep0;\n+  p->reps[1] = rep1;\n+  p->reps[2] = rep2;\n+  p->reps[3] = rep3;\n+  p->state = state;\n+\n+  return SZ_OK;\n+}\n+\n+static void MY_FAST_CALL LzmaDec_WriteRem(CLzmaDec *p, SizeT limit)\n+{\n+  if (p->remainLen != 0 && p->remainLen < kMatchSpecLenStart)\n+  {\n+    Byte *dic = p->dic;\n+    SizeT dicPos = p->dicPos;\n+    SizeT dicBufSize = p->dicBufSize;\n+    unsigned len = p->remainLen;\n+    UInt32 rep0 = p->reps[0];\n+    if (limit - dicPos < len)\n+      len = (unsigned)(limit - dicPos);\n+\n+    if (p->checkDicSize == 0 && p->prop.dicSize - p->processedPos <= len)\n+      p->checkDicSize = p->prop.dicSize;\n+\n+    p->processedPos += len;\n+    p->remainLen -= len;\n+    while (len-- != 0)\n+    {\n+      dic[dicPos] = dic[(dicPos - rep0) + ((dicPos < rep0) ? dicBufSize : 0)];\n+      dicPos++;\n+    }\n+    p->dicPos = dicPos;\n+  }\n+}\n+\n+static int MY_FAST_CALL LzmaDec_DecodeReal2(CLzmaDec *p, SizeT limit, const Byte *bufLimit)\n+{\n+  do\n+  {\n+    SizeT limit2 = limit;\n+    if (p->checkDicSize == 0)\n+    {\n+      UInt32 rem = p->prop.dicSize - p->processedPos;\n+      if (limit - p->dicPos > rem)\n+        limit2 = p->dicPos + rem;\n+    }\n+    RINOK(LzmaDec_DecodeReal(p, limit2, bufLimit));\n+    if (p->processedPos >= p->prop.dicSize)\n+      p->checkDicSize = p->prop.dicSize;\n+    LzmaDec_WriteRem(p, limit);\n+  }\n+  while (p->dicPos < limit && p->buf < bufLimit && p->remainLen < kMatchSpecLenStart);\n+\n+  if (p->remainLen > kMatchSpecLenStart)\n+  {\n+    p->remainLen = kMatchSpecLenStart;\n+  }\n+  return 0;\n+}\n+\n+typedef enum\n+{\n+  DUMMY_ERROR, /* unexpected end of input stream */\n+  DUMMY_LIT,\n+  DUMMY_MATCH,\n+  DUMMY_REP\n+} ELzmaDummy;\n+\n+static ELzmaDummy LzmaDec_TryDummy(const CLzmaDec *p, const Byte *buf, SizeT inSize)\n+{\n+  UInt32 range = p->range;\n+  UInt32 code = p->code;\n+  const Byte *bufLimit = buf + inSize;\n+  CLzmaProb *probs = p->probs;\n+  unsigned state = p->state;\n+  ELzmaDummy res;\n+\n+  {\n+    CLzmaProb *prob;\n+    UInt32 bound;\n+    unsigned ttt;\n+    unsigned posState = (p->processedPos) & ((1 << p->prop.pb) - 1);\n+\n+    prob = probs + IsMatch + (state << kNumPosBitsMax) + posState;\n+    IF_BIT_0_CHECK(prob)\n+    {\n+      UPDATE_0_CHECK\n+\n+      /* if (bufLimit - buf >= 7) return DUMMY_LIT; */\n+\n+      prob = probs + Literal;\n+      if (p->checkDicSize != 0 || p->processedPos != 0)\n+        prob += (LZMA_LIT_SIZE *\n+          ((((p->processedPos) & ((1 << (p->prop.lp)) - 1)) << p->prop.lc) +\n+          (p->dic[(p->dicPos == 0 ? p->dicBufSize : p->dicPos) - 1] >> (8 - p->prop.lc))));\n+\n+      if (state < kNumLitStates)\n+      {\n+        unsigned symbol = 1;\n+        do { GET_BIT_CHECK(prob + symbol, symbol) } while (symbol < 0x100);\n+      }\n+      else\n+      {\n+        unsigned matchByte = p->dic[p->dicPos - p->reps[0] +\n+            ((p->dicPos < p->reps[0]) ? p->dicBufSize : 0)];\n+        unsigned offs = 0x100;\n+        unsigned symbol = 1;\n+        do\n+        {\n+          unsigned bit;\n+          CLzmaProb *probLit;\n+          matchByte <<= 1;\n+          bit = (matchByte & offs);\n+          probLit = prob + offs + bit + symbol;\n+          GET_BIT2_CHECK(probLit, symbol, offs &= ~bit, offs &= bit)\n+        }\n+        while (symbol < 0x100);\n+      }\n+      res = DUMMY_LIT;\n+    }\n+    else\n+    {\n+      unsigned len;\n+      UPDATE_1_CHECK;\n+\n+      prob = probs + IsRep + state;\n+      IF_BIT_0_CHECK(prob)\n+      {\n+        UPDATE_0_CHECK;\n+        state = 0;\n+        prob = probs + LenCoder;\n+        res = DUMMY_MATCH;\n+      }\n+      else\n+      {\n+        UPDATE_1_CHECK;\n+        res = DUMMY_REP;\n+        prob = probs + IsRepG0 + state;\n+        IF_BIT_0_CHECK(prob)\n+        {\n+          UPDATE_0_CHECK;\n+          prob = probs + IsRep0Long + (state << kNumPosBitsMax) + posState;\n+          IF_BIT_0_CHECK(prob)\n+          {\n+            UPDATE_0_CHECK;\n+            NORMALIZE_CHECK;\n+            return DUMMY_REP;\n+          }\n+          else\n+          {\n+            UPDATE_1_CHECK;\n+          }\n+        }\n+        else\n+        {\n+          UPDATE_1_CHECK;\n+          prob = probs + IsRepG1 + state;\n+          IF_BIT_0_CHECK(prob)\n+          {\n+            UPDATE_0_CHECK;\n+          }\n+          else\n+          {\n+            UPDATE_1_CHECK;\n+            prob = probs + IsRepG2 + state;\n+            IF_BIT_0_CHECK(prob)\n+            {\n+              UPDATE_0_CHECK;\n+            }\n+            else\n+            {\n+              UPDATE_1_CHECK;\n+            }\n+          }\n+        }\n+        state = kNumStates;\n+        prob = probs + RepLenCoder;\n+      }\n+      {\n+        unsigned limit, offset;\n+        CLzmaProb *probLen = prob + LenChoice;\n+        IF_BIT_0_CHECK(probLen)\n+        {\n+          UPDATE_0_CHECK;\n+          probLen = prob + LenLow + (posState << kLenNumLowBits);\n+          offset = 0;\n+          limit = 1 << kLenNumLowBits;\n+        }\n+        else\n+        {\n+          UPDATE_1_CHECK;\n+          probLen = prob + LenChoice2;\n+          IF_BIT_0_CHECK(probLen)\n+          {\n+            UPDATE_0_CHECK;\n+            probLen = prob + LenMid + (posState << kLenNumMidBits);\n+            offset = kLenNumLowSymbols;\n+            limit = 1 << kLenNumMidBits;\n+          }\n+          else\n+          {\n+            UPDATE_1_CHECK;\n+            probLen = prob + LenHigh;\n+            offset = kLenNumLowSymbols + kLenNumMidSymbols;\n+            limit = 1 << kLenNumHighBits;\n+          }\n+        }\n+        TREE_DECODE_CHECK(probLen, limit, len);\n+        len += offset;\n+      }\n+\n+      if (state < 4)\n+      {\n+        unsigned posSlot;\n+        prob = probs + PosSlot +\n+            ((len < kNumLenToPosStates ? len : kNumLenToPosStates - 1) <<\n+            kNumPosSlotBits);\n+        TREE_DECODE_CHECK(prob, 1 << kNumPosSlotBits, posSlot);\n+        if (posSlot >= kStartPosModelIndex)\n+        {\n+          int numDirectBits = ((posSlot >> 1) - 1);\n+\n+          /* if (bufLimit - buf >= 8) return DUMMY_MATCH; */\n+\n+          if (posSlot < kEndPosModelIndex)\n+          {\n+            prob = probs + SpecPos + ((2 | (posSlot & 1)) << numDirectBits) - posSlot - 1;\n+          }\n+          else\n+          {\n+            numDirectBits -= kNumAlignBits;\n+            do\n+            {\n+              NORMALIZE_CHECK\n+              range >>= 1;\n+              code -= range & (((code - range) >> 31) - 1);\n+              /* if (code >= range) code -= range; */\n+            }\n+            while (--numDirectBits != 0);\n+            prob = probs + Align;\n+            numDirectBits = kNumAlignBits;\n+          }\n+          {\n+            unsigned i = 1;\n+            do\n+            {\n+              GET_BIT_CHECK(prob + i, i);\n+            }\n+            while (--numDirectBits != 0);\n+          }\n+        }\n+      }\n+    }\n+  }\n+  NORMALIZE_CHECK;\n+  return res;\n+}\n+\n+\n+static void LzmaDec_InitRc(CLzmaDec *p, const Byte *data)\n+{\n+  p->code = ((UInt32)data[1] << 24) | ((UInt32)data[2] << 16) | ((UInt32)data[3] << 8) | ((UInt32)data[4]);\n+  p->range = 0xFFFFFFFF;\n+  p->needFlush = 0;\n+}\n+\n+void LzmaDec_InitDicAndState(CLzmaDec *p, Bool initDic, Bool initState)\n+{\n+  p->needFlush = 1;\n+  p->remainLen = 0;\n+  p->tempBufSize = 0;\n+\n+  if (initDic)\n+  {\n+    p->processedPos = 0;\n+    p->checkDicSize = 0;\n+    p->needInitState = 1;\n+  }\n+  if (initState)\n+    p->needInitState = 1;\n+}\n+\n+void LzmaDec_Init(CLzmaDec *p)\n+{\n+  p->dicPos = 0;\n+  LzmaDec_InitDicAndState(p, True, True);\n+}\n+\n+static void LzmaDec_InitStateReal(CLzmaDec *p)\n+{\n+  UInt32 numProbs = Literal + ((UInt32)LZMA_LIT_SIZE << (p->prop.lc + p->prop.lp));\n+  UInt32 i;\n+  CLzmaProb *probs = p->probs;\n+  for (i = 0; i < numProbs; i++)\n+    probs[i] = kBitModelTotal >> 1;\n+  p->reps[0] = p->reps[1] = p->reps[2] = p->reps[3] = 1;\n+  p->state = 0;\n+  p->needInitState = 0;\n+}\n+\n+SRes LzmaDec_DecodeToDic(CLzmaDec *p, SizeT dicLimit, const Byte *src, SizeT *srcLen,\n+    ELzmaFinishMode finishMode, ELzmaStatus *status)\n+{\n+  SizeT inSize = *srcLen;\n+  (*srcLen) = 0;\n+  LzmaDec_WriteRem(p, dicLimit);\n+\n+  *status = LZMA_STATUS_NOT_SPECIFIED;\n+\n+  while (p->remainLen != kMatchSpecLenStart)\n+  {\n+      int checkEndMarkNow;\n+\n+      if (p->needFlush != 0)\n+      {\n+        for (; inSize > 0 && p->tempBufSize < RC_INIT_SIZE; (*srcLen)++, inSize--)\n+          p->tempBuf[p->tempBufSize++] = *src++;\n+        if (p->tempBufSize < RC_INIT_SIZE)\n+        {\n+          *status = LZMA_STATUS_NEEDS_MORE_INPUT;\n+          return SZ_OK;\n+        }\n+        if (p->tempBuf[0] != 0)\n+          return SZ_ERROR_DATA;\n+\n+        LzmaDec_InitRc(p, p->tempBuf);\n+        p->tempBufSize = 0;\n+      }\n+\n+      checkEndMarkNow = 0;\n+      if (p->dicPos >= dicLimit)\n+      {\n+        if (p->remainLen == 0 && p->code == 0)\n+        {\n+          *status = LZMA_STATUS_MAYBE_FINISHED_WITHOUT_MARK;\n+          return SZ_OK;\n+        }\n+        if (finishMode == LZMA_FINISH_ANY)\n+        {\n+          *status = LZMA_STATUS_NOT_FINISHED;\n+          return SZ_OK;\n+        }\n+        if (p->remainLen != 0)\n+        {\n+          *status = LZMA_STATUS_NOT_FINISHED;\n+          return SZ_ERROR_DATA;\n+        }\n+        checkEndMarkNow = 1;\n+      }\n+\n+      if (p->needInitState)\n+        LzmaDec_InitStateReal(p);\n+\n+      if (p->tempBufSize == 0)\n+      {\n+        SizeT processed;\n+        const Byte *bufLimit;\n+        if (inSize < LZMA_REQUIRED_INPUT_MAX || checkEndMarkNow)\n+        {\n+          int dummyRes = LzmaDec_TryDummy(p, src, inSize);\n+          if (dummyRes == DUMMY_ERROR)\n+          {\n+            memcpy(p->tempBuf, src, inSize);\n+            p->tempBufSize = (unsigned)inSize;\n+            (*srcLen) += inSize;\n+            *status = LZMA_STATUS_NEEDS_MORE_INPUT;\n+            return SZ_OK;\n+          }\n+          if (checkEndMarkNow && dummyRes != DUMMY_MATCH)\n+          {\n+            *status = LZMA_STATUS_NOT_FINISHED;\n+            return SZ_ERROR_DATA;\n+          }\n+          bufLimit = src;\n+        }\n+        else\n+          bufLimit = src + inSize - LZMA_REQUIRED_INPUT_MAX;\n+        p->buf = src;\n+        if (LzmaDec_DecodeReal2(p, dicLimit, bufLimit) != 0)\n+          return SZ_ERROR_DATA;\n+        processed = (SizeT)(p->buf - src);\n+        (*srcLen) += processed;\n+        src += processed;\n+        inSize -= processed;\n+      }\n+      else\n+      {\n+        unsigned rem = p->tempBufSize, lookAhead = 0;\n+        while (rem < LZMA_REQUIRED_INPUT_MAX && lookAhead < inSize)\n+          p->tempBuf[rem++] = src[lookAhead++];\n+        p->tempBufSize = rem;\n+        if (rem < LZMA_REQUIRED_INPUT_MAX || checkEndMarkNow)\n+        {\n+          int dummyRes = LzmaDec_TryDummy(p, p->tempBuf, rem);\n+          if (dummyRes == DUMMY_ERROR)\n+          {\n+            (*srcLen) += lookAhead;\n+            *status = LZMA_STATUS_NEEDS_MORE_INPUT;\n+            return SZ_OK;\n+          }\n+          if (checkEndMarkNow && dummyRes != DUMMY_MATCH)\n+          {\n+            *status = LZMA_STATUS_NOT_FINISHED;\n+            return SZ_ERROR_DATA;\n+          }\n+        }\n+        p->buf = p->tempBuf;\n+        if (LzmaDec_DecodeReal2(p, dicLimit, p->buf) != 0)\n+          return SZ_ERROR_DATA;\n+        lookAhead -= (rem - (unsigned)(p->buf - p->tempBuf));\n+        (*srcLen) += lookAhead;\n+        src += lookAhead;\n+        inSize -= lookAhead;\n+        p->tempBufSize = 0;\n+      }\n+  }\n+  if (p->code == 0)\n+    *status = LZMA_STATUS_FINISHED_WITH_MARK;\n+  return (p->code == 0) ? SZ_OK : SZ_ERROR_DATA;\n+}\n+\n+SRes LzmaDec_DecodeToBuf(CLzmaDec *p, Byte *dest, SizeT *destLen, const Byte *src, SizeT *srcLen, ELzmaFinishMode finishMode, ELzmaStatus *status)\n+{\n+  SizeT outSize = *destLen;\n+  SizeT inSize = *srcLen;\n+  *srcLen = *destLen = 0;\n+  for (;;)\n+  {\n+    SizeT inSizeCur = inSize, outSizeCur, dicPos;\n+    ELzmaFinishMode curFinishMode;\n+    SRes res;\n+    if (p->dicPos == p->dicBufSize)\n+      p->dicPos = 0;\n+    dicPos = p->dicPos;\n+    if (outSize > p->dicBufSize - dicPos)\n+    {\n+      outSizeCur = p->dicBufSize;\n+      curFinishMode = LZMA_FINISH_ANY;\n+    }\n+    else\n+    {\n+      outSizeCur = dicPos + outSize;\n+      curFinishMode = finishMode;\n+    }\n+\n+    res = LzmaDec_DecodeToDic(p, outSizeCur, src, &inSizeCur, curFinishMode, status);\n+    src += inSizeCur;\n+    inSize -= inSizeCur;\n+    *srcLen += inSizeCur;\n+    outSizeCur = p->dicPos - dicPos;\n+    memcpy(dest, p->dic + dicPos, outSizeCur);\n+    dest += outSizeCur;\n+    outSize -= outSizeCur;\n+    *destLen += outSizeCur;\n+    if (res != 0)\n+      return res;\n+    if (outSizeCur == 0 || outSize == 0)\n+      return SZ_OK;\n+  }\n+}\n+\n+void LzmaDec_FreeProbs(CLzmaDec *p, ISzAlloc *alloc)\n+{\n+  alloc->Free(alloc, p->probs);\n+  p->probs = 0;\n+}\n+\n+static void LzmaDec_FreeDict(CLzmaDec *p, ISzAlloc *alloc)\n+{\n+  alloc->Free(alloc, p->dic);\n+  p->dic = 0;\n+}\n+\n+void LzmaDec_Free(CLzmaDec *p, ISzAlloc *alloc)\n+{\n+  LzmaDec_FreeProbs(p, alloc);\n+  LzmaDec_FreeDict(p, alloc);\n+}\n+\n+SRes LzmaProps_Decode(CLzmaProps *p, const Byte *data, unsigned size)\n+{\n+  UInt32 dicSize;\n+  Byte d;\n+\n+  if (size < LZMA_PROPS_SIZE)\n+    return SZ_ERROR_UNSUPPORTED;\n+  else\n+    dicSize = data[1] | ((UInt32)data[2] << 8) | ((UInt32)data[3] << 16) | ((UInt32)data[4] << 24);\n+\n+  if (dicSize < LZMA_DIC_MIN)\n+    dicSize = LZMA_DIC_MIN;\n+  p->dicSize = dicSize;\n+\n+  d = data[0];\n+  if (d >= (9 * 5 * 5))\n+    return SZ_ERROR_UNSUPPORTED;\n+\n+  p->lc = d % 9;\n+  d /= 9;\n+  p->pb = d / 5;\n+  p->lp = d % 5;\n+\n+  return SZ_OK;\n+}\n+\n+static SRes LzmaDec_AllocateProbs2(CLzmaDec *p, const CLzmaProps *propNew, ISzAlloc *alloc)\n+{\n+  UInt32 numProbs = LzmaProps_GetNumProbs(propNew);\n+  if (p->probs == 0 || numProbs != p->numProbs)\n+  {\n+    LzmaDec_FreeProbs(p, alloc);\n+    p->probs = (CLzmaProb *)alloc->Alloc(alloc, numProbs * sizeof(CLzmaProb));\n+    p->numProbs = numProbs;\n+    if (p->probs == 0)\n+      return SZ_ERROR_MEM;\n+  }\n+  return SZ_OK;\n+}\n+\n+SRes LzmaDec_AllocateProbs(CLzmaDec *p, const Byte *props, unsigned propsSize, ISzAlloc *alloc)\n+{\n+  CLzmaProps propNew;\n+  RINOK(LzmaProps_Decode(&propNew, props, propsSize));\n+  RINOK(LzmaDec_AllocateProbs2(p, &propNew, alloc));\n+  p->prop = propNew;\n+  return SZ_OK;\n+}\n+\n+SRes LzmaDec_Allocate(CLzmaDec *p, const Byte *props, unsigned propsSize, ISzAlloc *alloc)\n+{\n+  CLzmaProps propNew;\n+  SizeT dicBufSize;\n+  RINOK(LzmaProps_Decode(&propNew, props, propsSize));\n+  RINOK(LzmaDec_AllocateProbs2(p, &propNew, alloc));\n+  dicBufSize = propNew.dicSize;\n+  if (p->dic == 0 || dicBufSize != p->dicBufSize)\n+  {\n+    LzmaDec_FreeDict(p, alloc);\n+    p->dic = (Byte *)alloc->Alloc(alloc, dicBufSize);\n+    if (p->dic == 0)\n+    {\n+      LzmaDec_FreeProbs(p, alloc);\n+      return SZ_ERROR_MEM;\n+    }\n+  }\n+  p->dicBufSize = dicBufSize;\n+  p->prop = propNew;\n+  return SZ_OK;\n+}\n+\n+SRes LzmaDecode(Byte *dest, SizeT *destLen, const Byte *src, SizeT *srcLen,\n+    const Byte *propData, unsigned propSize, ELzmaFinishMode finishMode,\n+    ELzmaStatus *status, ISzAlloc *alloc)\n+{\n+  CLzmaDec p;\n+  SRes res;\n+  SizeT inSize = *srcLen;\n+  SizeT outSize = *destLen;\n+  *srcLen = *destLen = 0;\n+  if (inSize < RC_INIT_SIZE)\n+    return SZ_ERROR_INPUT_EOF;\n+\n+  LzmaDec_Construct(&p);\n+  res = LzmaDec_AllocateProbs(&p, propData, propSize, alloc);\n+  if (res != 0)\n+    return res;\n+  p.dic = dest;\n+  p.dicBufSize = outSize;\n+\n+  LzmaDec_Init(&p);\n+\n+  *srcLen = inSize;\n+  res = LzmaDec_DecodeToDic(&p, outSize, src, srcLen, finishMode, status);\n+\n+  if (res == SZ_OK && *status == LZMA_STATUS_NEEDS_MORE_INPUT)\n+    res = SZ_ERROR_INPUT_EOF;\n+\n+  (*destLen) = p.dicPos;\n+  LzmaDec_FreeProbs(&p, alloc);\n+  return res;\n+}\n--- /dev/null\n+++ b/lib/lzma/LzmaEnc.c\n@@ -0,0 +1,2271 @@\n+/* LzmaEnc.c -- LZMA Encoder\n+2009-11-24 : Igor Pavlov : Public domain */\n+\n+#include <string.h>\n+\n+/* #define SHOW_STAT */\n+/* #define SHOW_STAT2 */\n+\n+#if defined(SHOW_STAT) || defined(SHOW_STAT2)\n+#include <stdio.h>\n+#endif\n+\n+#include \"LzmaEnc.h\"\n+\n+/* disable MT */\n+#define _7ZIP_ST\n+\n+#include \"LzFind.h\"\n+#ifndef _7ZIP_ST\n+#include \"LzFindMt.h\"\n+#endif\n+\n+#ifdef SHOW_STAT\n+static int ttt = 0;\n+#endif\n+\n+#define kBlockSizeMax ((1 << LZMA_NUM_BLOCK_SIZE_BITS) - 1)\n+\n+#define kBlockSize (9 << 10)\n+#define kUnpackBlockSize (1 << 18)\n+#define kMatchArraySize (1 << 21)\n+#define kMatchRecordMaxSize ((LZMA_MATCH_LEN_MAX * 2 + 3) * LZMA_MATCH_LEN_MAX)\n+\n+#define kNumMaxDirectBits (31)\n+\n+#define kNumTopBits 24\n+#define kTopValue ((UInt32)1 << kNumTopBits)\n+\n+#define kNumBitModelTotalBits 11\n+#define kBitModelTotal (1 << kNumBitModelTotalBits)\n+#define kNumMoveBits 5\n+#define kProbInitValue (kBitModelTotal >> 1)\n+\n+#define kNumMoveReducingBits 4\n+#define kNumBitPriceShiftBits 4\n+#define kBitPrice (1 << kNumBitPriceShiftBits)\n+\n+void LzmaEncProps_Init(CLzmaEncProps *p)\n+{\n+  p->level = 5;\n+  p->dictSize = p->mc = 0;\n+  p->lc = p->lp = p->pb = p->algo = p->fb = p->btMode = p->numHashBytes = p->numThreads = -1;\n+  p->writeEndMark = 0;\n+}\n+\n+void LzmaEncProps_Normalize(CLzmaEncProps *p)\n+{\n+  int level = p->level;\n+  if (level < 0) level = 5;\n+  p->level = level;\n+  if (p->dictSize == 0) p->dictSize = (level <= 5 ? (1 << (level * 2 + 14)) : (level == 6 ? (1 << 25) : (1 << 26)));\n+  if (p->lc < 0) p->lc = 3;\n+  if (p->lp < 0) p->lp = 0;\n+  if (p->pb < 0) p->pb = 2;\n+  if (p->algo < 0) p->algo = (level < 5 ? 0 : 1);\n+  if (p->fb < 0) p->fb = (level < 7 ? 32 : 64);\n+  if (p->btMode < 0) p->btMode = (p->algo == 0 ? 0 : 1);\n+  if (p->numHashBytes < 0) p->numHashBytes = 4;\n+  if (p->mc == 0)  p->mc = (16 + (p->fb >> 1)) >> (p->btMode ? 0 : 1);\n+  if (p->numThreads < 0)\n+    p->numThreads =\n+      #ifndef _7ZIP_ST\n+      ((p->btMode && p->algo) ? 2 : 1);\n+      #else\n+      1;\n+      #endif\n+}\n+\n+UInt32 LzmaEncProps_GetDictSize(const CLzmaEncProps *props2)\n+{\n+  CLzmaEncProps props = *props2;\n+  LzmaEncProps_Normalize(&props);\n+  return props.dictSize;\n+}\n+\n+/* #define LZMA_LOG_BSR */\n+/* Define it for Intel's CPU */\n+\n+\n+#ifdef LZMA_LOG_BSR\n+\n+#define kDicLogSizeMaxCompress 30\n+\n+#define BSR2_RET(pos, res) { unsigned long i; _BitScanReverse(&i, (pos)); res = (i + i) + ((pos >> (i - 1)) & 1); }\n+\n+UInt32 GetPosSlot1(UInt32 pos)\n+{\n+  UInt32 res;\n+  BSR2_RET(pos, res);\n+  return res;\n+}\n+#define GetPosSlot2(pos, res) { BSR2_RET(pos, res); }\n+#define GetPosSlot(pos, res) { if (pos < 2) res = pos; else BSR2_RET(pos, res); }\n+\n+#else\n+\n+#define kNumLogBits (9 + (int)sizeof(size_t) / 2)\n+#define kDicLogSizeMaxCompress ((kNumLogBits - 1) * 2 + 7)\n+\n+void LzmaEnc_FastPosInit(Byte *g_FastPos)\n+{\n+  int c = 2, slotFast;\n+  g_FastPos[0] = 0;\n+  g_FastPos[1] = 1;\n+\n+  for (slotFast = 2; slotFast < kNumLogBits * 2; slotFast++)\n+  {\n+    UInt32 k = (1 << ((slotFast >> 1) - 1));\n+    UInt32 j;\n+    for (j = 0; j < k; j++, c++)\n+      g_FastPos[c] = (Byte)slotFast;\n+  }\n+}\n+\n+#define BSR2_RET(pos, res) { UInt32 i = 6 + ((kNumLogBits - 1) & \\\n+  (0 - (((((UInt32)1 << (kNumLogBits + 6)) - 1) - pos) >> 31))); \\\n+  res = p->g_FastPos[pos >> i] + (i * 2); }\n+/*\n+#define BSR2_RET(pos, res) { res = (pos < (1 << (kNumLogBits + 6))) ? \\\n+  p->g_FastPos[pos >> 6] + 12 : \\\n+  p->g_FastPos[pos >> (6 + kNumLogBits - 1)] + (6 + (kNumLogBits - 1)) * 2; }\n+*/\n+\n+#define GetPosSlot1(pos) p->g_FastPos[pos]\n+#define GetPosSlot2(pos, res) { BSR2_RET(pos, res); }\n+#define GetPosSlot(pos, res) { if (pos < kNumFullDistances) res = p->g_FastPos[pos]; else BSR2_RET(pos, res); }\n+\n+#endif\n+\n+\n+#define LZMA_NUM_REPS 4\n+\n+typedef unsigned CState;\n+\n+typedef struct\n+{\n+  UInt32 price;\n+\n+  CState state;\n+  int prev1IsChar;\n+  int prev2;\n+\n+  UInt32 posPrev2;\n+  UInt32 backPrev2;\n+\n+  UInt32 posPrev;\n+  UInt32 backPrev;\n+  UInt32 backs[LZMA_NUM_REPS];\n+} COptimal;\n+\n+#define kNumOpts (1 << 12)\n+\n+#define kNumLenToPosStates 4\n+#define kNumPosSlotBits 6\n+#define kDicLogSizeMin 0\n+#define kDicLogSizeMax 32\n+#define kDistTableSizeMax (kDicLogSizeMax * 2)\n+\n+\n+#define kNumAlignBits 4\n+#define kAlignTableSize (1 << kNumAlignBits)\n+#define kAlignMask (kAlignTableSize - 1)\n+\n+#define kStartPosModelIndex 4\n+#define kEndPosModelIndex 14\n+#define kNumPosModels (kEndPosModelIndex - kStartPosModelIndex)\n+\n+#define kNumFullDistances (1 << (kEndPosModelIndex >> 1))\n+\n+#ifdef _LZMA_PROB32\n+#define CLzmaProb UInt32\n+#else\n+#define CLzmaProb UInt16\n+#endif\n+\n+#define LZMA_PB_MAX 4\n+#define LZMA_LC_MAX 8\n+#define LZMA_LP_MAX 4\n+\n+#define LZMA_NUM_PB_STATES_MAX (1 << LZMA_PB_MAX)\n+\n+\n+#define kLenNumLowBits 3\n+#define kLenNumLowSymbols (1 << kLenNumLowBits)\n+#define kLenNumMidBits 3\n+#define kLenNumMidSymbols (1 << kLenNumMidBits)\n+#define kLenNumHighBits 8\n+#define kLenNumHighSymbols (1 << kLenNumHighBits)\n+\n+#define kLenNumSymbolsTotal (kLenNumLowSymbols + kLenNumMidSymbols + kLenNumHighSymbols)\n+\n+#define LZMA_MATCH_LEN_MIN 2\n+#define LZMA_MATCH_LEN_MAX (LZMA_MATCH_LEN_MIN + kLenNumSymbolsTotal - 1)\n+\n+#define kNumStates 12\n+\n+typedef struct\n+{\n+  CLzmaProb choice;\n+  CLzmaProb choice2;\n+  CLzmaProb low[LZMA_NUM_PB_STATES_MAX << kLenNumLowBits];\n+  CLzmaProb mid[LZMA_NUM_PB_STATES_MAX << kLenNumMidBits];\n+  CLzmaProb high[kLenNumHighSymbols];\n+} CLenEnc;\n+\n+typedef struct\n+{\n+  CLenEnc p;\n+  UInt32 prices[LZMA_NUM_PB_STATES_MAX][kLenNumSymbolsTotal];\n+  UInt32 tableSize;\n+  UInt32 counters[LZMA_NUM_PB_STATES_MAX];\n+} CLenPriceEnc;\n+\n+typedef struct\n+{\n+  UInt32 range;\n+  Byte cache;\n+  UInt64 low;\n+  UInt64 cacheSize;\n+  Byte *buf;\n+  Byte *bufLim;\n+  Byte *bufBase;\n+  ISeqOutStream *outStream;\n+  UInt64 processed;\n+  SRes res;\n+} CRangeEnc;\n+\n+typedef struct\n+{\n+  CLzmaProb *litProbs;\n+\n+  CLzmaProb isMatch[kNumStates][LZMA_NUM_PB_STATES_MAX];\n+  CLzmaProb isRep[kNumStates];\n+  CLzmaProb isRepG0[kNumStates];\n+  CLzmaProb isRepG1[kNumStates];\n+  CLzmaProb isRepG2[kNumStates];\n+  CLzmaProb isRep0Long[kNumStates][LZMA_NUM_PB_STATES_MAX];\n+\n+  CLzmaProb posSlotEncoder[kNumLenToPosStates][1 << kNumPosSlotBits];\n+  CLzmaProb posEncoders[kNumFullDistances - kEndPosModelIndex];\n+  CLzmaProb posAlignEncoder[1 << kNumAlignBits];\n+\n+  CLenPriceEnc lenEnc;\n+  CLenPriceEnc repLenEnc;\n+\n+  UInt32 reps[LZMA_NUM_REPS];\n+  UInt32 state;\n+} CSaveState;\n+\n+typedef struct\n+{\n+  IMatchFinder matchFinder;\n+  void *matchFinderObj;\n+\n+  #ifndef _7ZIP_ST\n+  Bool mtMode;\n+  CMatchFinderMt matchFinderMt;\n+  #endif\n+\n+  CMatchFinder matchFinderBase;\n+\n+  #ifndef _7ZIP_ST\n+  Byte pad[128];\n+  #endif\n+\n+  UInt32 optimumEndIndex;\n+  UInt32 optimumCurrentIndex;\n+\n+  UInt32 longestMatchLength;\n+  UInt32 numPairs;\n+  UInt32 numAvail;\n+  COptimal opt[kNumOpts];\n+\n+  #ifndef LZMA_LOG_BSR\n+  Byte g_FastPos[1 << kNumLogBits];\n+  #endif\n+\n+  UInt32 ProbPrices[kBitModelTotal >> kNumMoveReducingBits];\n+  UInt32 matches[LZMA_MATCH_LEN_MAX * 2 + 2 + 1];\n+  UInt32 numFastBytes;\n+  UInt32 additionalOffset;\n+  UInt32 reps[LZMA_NUM_REPS];\n+  UInt32 state;\n+\n+  UInt32 posSlotPrices[kNumLenToPosStates][kDistTableSizeMax];\n+  UInt32 distancesPrices[kNumLenToPosStates][kNumFullDistances];\n+  UInt32 alignPrices[kAlignTableSize];\n+  UInt32 alignPriceCount;\n+\n+  UInt32 distTableSize;\n+\n+  unsigned lc, lp, pb;\n+  unsigned lpMask, pbMask;\n+\n+  CLzmaProb *litProbs;\n+\n+  CLzmaProb isMatch[kNumStates][LZMA_NUM_PB_STATES_MAX];\n+  CLzmaProb isRep[kNumStates];\n+  CLzmaProb isRepG0[kNumStates];\n+  CLzmaProb isRepG1[kNumStates];\n+  CLzmaProb isRepG2[kNumStates];\n+  CLzmaProb isRep0Long[kNumStates][LZMA_NUM_PB_STATES_MAX];\n+\n+  CLzmaProb posSlotEncoder[kNumLenToPosStates][1 << kNumPosSlotBits];\n+  CLzmaProb posEncoders[kNumFullDistances - kEndPosModelIndex];\n+  CLzmaProb posAlignEncoder[1 << kNumAlignBits];\n+\n+  CLenPriceEnc lenEnc;\n+  CLenPriceEnc repLenEnc;\n+\n+  unsigned lclp;\n+\n+  Bool fastMode;\n+\n+  CRangeEnc rc;\n+\n+  Bool writeEndMark;\n+  UInt64 nowPos64;\n+  UInt32 matchPriceCount;\n+  Bool finished;\n+  Bool multiThread;\n+\n+  SRes result;\n+  UInt32 dictSize;\n+  UInt32 matchFinderCycles;\n+\n+  int needInit;\n+\n+  CSaveState saveState;\n+} CLzmaEnc;\n+\n+void LzmaEnc_SaveState(CLzmaEncHandle pp)\n+{\n+  CLzmaEnc *p = (CLzmaEnc *)pp;\n+  CSaveState *dest = &p->saveState;\n+  int i;\n+  dest->lenEnc = p->lenEnc;\n+  dest->repLenEnc = p->repLenEnc;\n+  dest->state = p->state;\n+\n+  for (i = 0; i < kNumStates; i++)\n+  {\n+    memcpy(dest->isMatch[i], p->isMatch[i], sizeof(p->isMatch[i]));\n+    memcpy(dest->isRep0Long[i], p->isRep0Long[i], sizeof(p->isRep0Long[i]));\n+  }\n+  for (i = 0; i < kNumLenToPosStates; i++)\n+    memcpy(dest->posSlotEncoder[i], p->posSlotEncoder[i], sizeof(p->posSlotEncoder[i]));\n+  memcpy(dest->isRep, p->isRep, sizeof(p->isRep));\n+  memcpy(dest->isRepG0, p->isRepG0, sizeof(p->isRepG0));\n+  memcpy(dest->isRepG1, p->isRepG1, sizeof(p->isRepG1));\n+  memcpy(dest->isRepG2, p->isRepG2, sizeof(p->isRepG2));\n+  memcpy(dest->posEncoders, p->posEncoders, sizeof(p->posEncoders));\n+  memcpy(dest->posAlignEncoder, p->posAlignEncoder, sizeof(p->posAlignEncoder));\n+  memcpy(dest->reps, p->reps, sizeof(p->reps));\n+  memcpy(dest->litProbs, p->litProbs, (0x300 << p->lclp) * sizeof(CLzmaProb));\n+}\n+\n+void LzmaEnc_RestoreState(CLzmaEncHandle pp)\n+{\n+  CLzmaEnc *dest = (CLzmaEnc *)pp;\n+  const CSaveState *p = &dest->saveState;\n+  int i;\n+  dest->lenEnc = p->lenEnc;\n+  dest->repLenEnc = p->repLenEnc;\n+  dest->state = p->state;\n+\n+  for (i = 0; i < kNumStates; i++)\n+  {\n+    memcpy(dest->isMatch[i], p->isMatch[i], sizeof(p->isMatch[i]));\n+    memcpy(dest->isRep0Long[i], p->isRep0Long[i], sizeof(p->isRep0Long[i]));\n+  }\n+  for (i = 0; i < kNumLenToPosStates; i++)\n+    memcpy(dest->posSlotEncoder[i], p->posSlotEncoder[i], sizeof(p->posSlotEncoder[i]));\n+  memcpy(dest->isRep, p->isRep, sizeof(p->isRep));\n+  memcpy(dest->isRepG0, p->isRepG0, sizeof(p->isRepG0));\n+  memcpy(dest->isRepG1, p->isRepG1, sizeof(p->isRepG1));\n+  memcpy(dest->isRepG2, p->isRepG2, sizeof(p->isRepG2));\n+  memcpy(dest->posEncoders, p->posEncoders, sizeof(p->posEncoders));\n+  memcpy(dest->posAlignEncoder, p->posAlignEncoder, sizeof(p->posAlignEncoder));\n+  memcpy(dest->reps, p->reps, sizeof(p->reps));\n+  memcpy(dest->litProbs, p->litProbs, (0x300 << dest->lclp) * sizeof(CLzmaProb));\n+}\n+\n+SRes LzmaEnc_SetProps(CLzmaEncHandle pp, const CLzmaEncProps *props2)\n+{\n+  CLzmaEnc *p = (CLzmaEnc *)pp;\n+  CLzmaEncProps props = *props2;\n+  LzmaEncProps_Normalize(&props);\n+\n+  if (props.lc > LZMA_LC_MAX || props.lp > LZMA_LP_MAX || props.pb > LZMA_PB_MAX ||\n+      props.dictSize > (1 << kDicLogSizeMaxCompress) || props.dictSize > (1 << 30))\n+    return SZ_ERROR_PARAM;\n+  p->dictSize = props.dictSize;\n+  p->matchFinderCycles = props.mc;\n+  {\n+    unsigned fb = props.fb;\n+    if (fb < 5)\n+      fb = 5;\n+    if (fb > LZMA_MATCH_LEN_MAX)\n+      fb = LZMA_MATCH_LEN_MAX;\n+    p->numFastBytes = fb;\n+  }\n+  p->lc = props.lc;\n+  p->lp = props.lp;\n+  p->pb = props.pb;\n+  p->fastMode = (props.algo == 0);\n+  p->matchFinderBase.btMode = props.btMode;\n+  {\n+    UInt32 numHashBytes = 4;\n+    if (props.btMode)\n+    {\n+      if (props.numHashBytes < 2)\n+        numHashBytes = 2;\n+      else if (props.numHashBytes < 4)\n+        numHashBytes = props.numHashBytes;\n+    }\n+    p->matchFinderBase.numHashBytes = numHashBytes;\n+  }\n+\n+  p->matchFinderBase.cutValue = props.mc;\n+\n+  p->writeEndMark = props.writeEndMark;\n+\n+  #ifndef _7ZIP_ST\n+  /*\n+  if (newMultiThread != _multiThread)\n+  {\n+    ReleaseMatchFinder();\n+    _multiThread = newMultiThread;\n+  }\n+  */\n+  p->multiThread = (props.numThreads > 1);\n+  #endif\n+\n+  return SZ_OK;\n+}\n+\n+static const int kLiteralNextStates[kNumStates] = {0, 0, 0, 0, 1, 2, 3, 4,  5,  6,   4, 5};\n+static const int kMatchNextStates[kNumStates]   = {7, 7, 7, 7, 7, 7, 7, 10, 10, 10, 10, 10};\n+static const int kRepNextStates[kNumStates]     = {8, 8, 8, 8, 8, 8, 8, 11, 11, 11, 11, 11};\n+static const int kShortRepNextStates[kNumStates]= {9, 9, 9, 9, 9, 9, 9, 11, 11, 11, 11, 11};\n+\n+#define IsCharState(s) ((s) < 7)\n+\n+#define GetLenToPosState(len) (((len) < kNumLenToPosStates + 1) ? (len) - 2 : kNumLenToPosStates - 1)\n+\n+#define kInfinityPrice (1 << 30)\n+\n+static void RangeEnc_Construct(CRangeEnc *p)\n+{\n+  p->outStream = 0;\n+  p->bufBase = 0;\n+}\n+\n+#define RangeEnc_GetProcessed(p) ((p)->processed + ((p)->buf - (p)->bufBase) + (p)->cacheSize)\n+\n+#define RC_BUF_SIZE (1 << 16)\n+static int RangeEnc_Alloc(CRangeEnc *p, ISzAlloc *alloc)\n+{\n+  if (p->bufBase == 0)\n+  {\n+    p->bufBase = (Byte *)alloc->Alloc(alloc, RC_BUF_SIZE);\n+    if (p->bufBase == 0)\n+      return 0;\n+    p->bufLim = p->bufBase + RC_BUF_SIZE;\n+  }\n+  return 1;\n+}\n+\n+static void RangeEnc_Free(CRangeEnc *p, ISzAlloc *alloc)\n+{\n+  alloc->Free(alloc, p->bufBase);\n+  p->bufBase = 0;\n+}\n+\n+static void RangeEnc_Init(CRangeEnc *p)\n+{\n+  /* Stream.Init(); */\n+  p->low = 0;\n+  p->range = 0xFFFFFFFF;\n+  p->cacheSize = 1;\n+  p->cache = 0;\n+\n+  p->buf = p->bufBase;\n+\n+  p->processed = 0;\n+  p->res = SZ_OK;\n+}\n+\n+static void RangeEnc_FlushStream(CRangeEnc *p)\n+{\n+  size_t num;\n+  if (p->res != SZ_OK)\n+    return;\n+  num = p->buf - p->bufBase;\n+  if (num != p->outStream->Write(p->outStream, p->bufBase, num))\n+    p->res = SZ_ERROR_WRITE;\n+  p->processed += num;\n+  p->buf = p->bufBase;\n+}\n+\n+static void MY_FAST_CALL RangeEnc_ShiftLow(CRangeEnc *p)\n+{\n+  if ((UInt32)p->low < (UInt32)0xFF000000 || (int)(p->low >> 32) != 0)\n+  {\n+    Byte temp = p->cache;\n+    do\n+    {\n+      Byte *buf = p->buf;\n+      *buf++ = (Byte)(temp + (Byte)(p->low >> 32));\n+      p->buf = buf;\n+      if (buf == p->bufLim)\n+        RangeEnc_FlushStream(p);\n+      temp = 0xFF;\n+    }\n+    while (--p->cacheSize != 0);\n+    p->cache = (Byte)((UInt32)p->low >> 24);\n+  }\n+  p->cacheSize++;\n+  p->low = (UInt32)p->low << 8;\n+}\n+\n+static void RangeEnc_FlushData(CRangeEnc *p)\n+{\n+  int i;\n+  for (i = 0; i < 5; i++)\n+    RangeEnc_ShiftLow(p);\n+}\n+\n+static void RangeEnc_EncodeDirectBits(CRangeEnc *p, UInt32 value, int numBits)\n+{\n+  do\n+  {\n+    p->range >>= 1;\n+    p->low += p->range & (0 - ((value >> --numBits) & 1));\n+    if (p->range < kTopValue)\n+    {\n+      p->range <<= 8;\n+      RangeEnc_ShiftLow(p);\n+    }\n+  }\n+  while (numBits != 0);\n+}\n+\n+static void RangeEnc_EncodeBit(CRangeEnc *p, CLzmaProb *prob, UInt32 symbol)\n+{\n+  UInt32 ttt = *prob;\n+  UInt32 newBound = (p->range >> kNumBitModelTotalBits) * ttt;\n+  if (symbol == 0)\n+  {\n+    p->range = newBound;\n+    ttt += (kBitModelTotal - ttt) >> kNumMoveBits;\n+  }\n+  else\n+  {\n+    p->low += newBound;\n+    p->range -= newBound;\n+    ttt -= ttt >> kNumMoveBits;\n+  }\n+  *prob = (CLzmaProb)ttt;\n+  if (p->range < kTopValue)\n+  {\n+    p->range <<= 8;\n+    RangeEnc_ShiftLow(p);\n+  }\n+}\n+\n+static void LitEnc_Encode(CRangeEnc *p, CLzmaProb *probs, UInt32 symbol)\n+{\n+  symbol |= 0x100;\n+  do\n+  {\n+    RangeEnc_EncodeBit(p, probs + (symbol >> 8), (symbol >> 7) & 1);\n+    symbol <<= 1;\n+  }\n+  while (symbol < 0x10000);\n+}\n+\n+static void LitEnc_EncodeMatched(CRangeEnc *p, CLzmaProb *probs, UInt32 symbol, UInt32 matchByte)\n+{\n+  UInt32 offs = 0x100;\n+  symbol |= 0x100;\n+  do\n+  {\n+    matchByte <<= 1;\n+    RangeEnc_EncodeBit(p, probs + (offs + (matchByte & offs) + (symbol >> 8)), (symbol >> 7) & 1);\n+    symbol <<= 1;\n+    offs &= ~(matchByte ^ symbol);\n+  }\n+  while (symbol < 0x10000);\n+}\n+\n+void LzmaEnc_InitPriceTables(UInt32 *ProbPrices)\n+{\n+  UInt32 i;\n+  for (i = (1 << kNumMoveReducingBits) / 2; i < kBitModelTotal; i += (1 << kNumMoveReducingBits))\n+  {\n+    const int kCyclesBits = kNumBitPriceShiftBits;\n+    UInt32 w = i;\n+    UInt32 bitCount = 0;\n+    int j;\n+    for (j = 0; j < kCyclesBits; j++)\n+    {\n+      w = w * w;\n+      bitCount <<= 1;\n+      while (w >= ((UInt32)1 << 16))\n+      {\n+        w >>= 1;\n+        bitCount++;\n+      }\n+    }\n+    ProbPrices[i >> kNumMoveReducingBits] = ((kNumBitModelTotalBits << kCyclesBits) - 15 - bitCount);\n+  }\n+}\n+\n+\n+#define GET_PRICE(prob, symbol) \\\n+  p->ProbPrices[((prob) ^ (((-(int)(symbol))) & (kBitModelTotal - 1))) >> kNumMoveReducingBits];\n+\n+#define GET_PRICEa(prob, symbol) \\\n+  ProbPrices[((prob) ^ ((-((int)(symbol))) & (kBitModelTotal - 1))) >> kNumMoveReducingBits];\n+\n+#define GET_PRICE_0(prob) p->ProbPrices[(prob) >> kNumMoveReducingBits]\n+#define GET_PRICE_1(prob) p->ProbPrices[((prob) ^ (kBitModelTotal - 1)) >> kNumMoveReducingBits]\n+\n+#define GET_PRICE_0a(prob) ProbPrices[(prob) >> kNumMoveReducingBits]\n+#define GET_PRICE_1a(prob) ProbPrices[((prob) ^ (kBitModelTotal - 1)) >> kNumMoveReducingBits]\n+\n+static UInt32 LitEnc_GetPrice(const CLzmaProb *probs, UInt32 symbol, UInt32 *ProbPrices)\n+{\n+  UInt32 price = 0;\n+  symbol |= 0x100;\n+  do\n+  {\n+    price += GET_PRICEa(probs[symbol >> 8], (symbol >> 7) & 1);\n+    symbol <<= 1;\n+  }\n+  while (symbol < 0x10000);\n+  return price;\n+}\n+\n+static UInt32 LitEnc_GetPriceMatched(const CLzmaProb *probs, UInt32 symbol, UInt32 matchByte, UInt32 *ProbPrices)\n+{\n+  UInt32 price = 0;\n+  UInt32 offs = 0x100;\n+  symbol |= 0x100;\n+  do\n+  {\n+    matchByte <<= 1;\n+    price += GET_PRICEa(probs[offs + (matchByte & offs) + (symbol >> 8)], (symbol >> 7) & 1);\n+    symbol <<= 1;\n+    offs &= ~(matchByte ^ symbol);\n+  }\n+  while (symbol < 0x10000);\n+  return price;\n+}\n+\n+\n+static void RcTree_Encode(CRangeEnc *rc, CLzmaProb *probs, int numBitLevels, UInt32 symbol)\n+{\n+  UInt32 m = 1;\n+  int i;\n+  for (i = numBitLevels; i != 0;)\n+  {\n+    UInt32 bit;\n+    i--;\n+    bit = (symbol >> i) & 1;\n+    RangeEnc_EncodeBit(rc, probs + m, bit);\n+    m = (m << 1) | bit;\n+  }\n+}\n+\n+static void RcTree_ReverseEncode(CRangeEnc *rc, CLzmaProb *probs, int numBitLevels, UInt32 symbol)\n+{\n+  UInt32 m = 1;\n+  int i;\n+  for (i = 0; i < numBitLevels; i++)\n+  {\n+    UInt32 bit = symbol & 1;\n+    RangeEnc_EncodeBit(rc, probs + m, bit);\n+    m = (m << 1) | bit;\n+    symbol >>= 1;\n+  }\n+}\n+\n+static UInt32 RcTree_GetPrice(const CLzmaProb *probs, int numBitLevels, UInt32 symbol, UInt32 *ProbPrices)\n+{\n+  UInt32 price = 0;\n+  symbol |= (1 << numBitLevels);\n+  while (symbol != 1)\n+  {\n+    price += GET_PRICEa(probs[symbol >> 1], symbol & 1);\n+    symbol >>= 1;\n+  }\n+  return price;\n+}\n+\n+static UInt32 RcTree_ReverseGetPrice(const CLzmaProb *probs, int numBitLevels, UInt32 symbol, UInt32 *ProbPrices)\n+{\n+  UInt32 price = 0;\n+  UInt32 m = 1;\n+  int i;\n+  for (i = numBitLevels; i != 0; i--)\n+  {\n+    UInt32 bit = symbol & 1;\n+    symbol >>= 1;\n+    price += GET_PRICEa(probs[m], bit);\n+    m = (m << 1) | bit;\n+  }\n+  return price;\n+}\n+\n+\n+static void LenEnc_Init(CLenEnc *p)\n+{\n+  unsigned i;\n+  p->choice = p->choice2 = kProbInitValue;\n+  for (i = 0; i < (LZMA_NUM_PB_STATES_MAX << kLenNumLowBits); i++)\n+    p->low[i] = kProbInitValue;\n+  for (i = 0; i < (LZMA_NUM_PB_STATES_MAX << kLenNumMidBits); i++)\n+    p->mid[i] = kProbInitValue;\n+  for (i = 0; i < kLenNumHighSymbols; i++)\n+    p->high[i] = kProbInitValue;\n+}\n+\n+static void LenEnc_Encode(CLenEnc *p, CRangeEnc *rc, UInt32 symbol, UInt32 posState)\n+{\n+  if (symbol < kLenNumLowSymbols)\n+  {\n+    RangeEnc_EncodeBit(rc, &p->choice, 0);\n+    RcTree_Encode(rc, p->low + (posState << kLenNumLowBits), kLenNumLowBits, symbol);\n+  }\n+  else\n+  {\n+    RangeEnc_EncodeBit(rc, &p->choice, 1);\n+    if (symbol < kLenNumLowSymbols + kLenNumMidSymbols)\n+    {\n+      RangeEnc_EncodeBit(rc, &p->choice2, 0);\n+      RcTree_Encode(rc, p->mid + (posState << kLenNumMidBits), kLenNumMidBits, symbol - kLenNumLowSymbols);\n+    }\n+    else\n+    {\n+      RangeEnc_EncodeBit(rc, &p->choice2, 1);\n+      RcTree_Encode(rc, p->high, kLenNumHighBits, symbol - kLenNumLowSymbols - kLenNumMidSymbols);\n+    }\n+  }\n+}\n+\n+static void LenEnc_SetPrices(CLenEnc *p, UInt32 posState, UInt32 numSymbols, UInt32 *prices, UInt32 *ProbPrices)\n+{\n+  UInt32 a0 = GET_PRICE_0a(p->choice);\n+  UInt32 a1 = GET_PRICE_1a(p->choice);\n+  UInt32 b0 = a1 + GET_PRICE_0a(p->choice2);\n+  UInt32 b1 = a1 + GET_PRICE_1a(p->choice2);\n+  UInt32 i = 0;\n+  for (i = 0; i < kLenNumLowSymbols; i++)\n+  {\n+    if (i >= numSymbols)\n+      return;\n+    prices[i] = a0 + RcTree_GetPrice(p->low + (posState << kLenNumLowBits), kLenNumLowBits, i, ProbPrices);\n+  }\n+  for (; i < kLenNumLowSymbols + kLenNumMidSymbols; i++)\n+  {\n+    if (i >= numSymbols)\n+      return;\n+    prices[i] = b0 + RcTree_GetPrice(p->mid + (posState << kLenNumMidBits), kLenNumMidBits, i - kLenNumLowSymbols, ProbPrices);\n+  }\n+  for (; i < numSymbols; i++)\n+    prices[i] = b1 + RcTree_GetPrice(p->high, kLenNumHighBits, i - kLenNumLowSymbols - kLenNumMidSymbols, ProbPrices);\n+}\n+\n+static void MY_FAST_CALL LenPriceEnc_UpdateTable(CLenPriceEnc *p, UInt32 posState, UInt32 *ProbPrices)\n+{\n+  LenEnc_SetPrices(&p->p, posState, p->tableSize, p->prices[posState], ProbPrices);\n+  p->counters[posState] = p->tableSize;\n+}\n+\n+static void LenPriceEnc_UpdateTables(CLenPriceEnc *p, UInt32 numPosStates, UInt32 *ProbPrices)\n+{\n+  UInt32 posState;\n+  for (posState = 0; posState < numPosStates; posState++)\n+    LenPriceEnc_UpdateTable(p, posState, ProbPrices);\n+}\n+\n+static void LenEnc_Encode2(CLenPriceEnc *p, CRangeEnc *rc, UInt32 symbol, UInt32 posState, Bool updatePrice, UInt32 *ProbPrices)\n+{\n+  LenEnc_Encode(&p->p, rc, symbol, posState);\n+  if (updatePrice)\n+    if (--p->counters[posState] == 0)\n+      LenPriceEnc_UpdateTable(p, posState, ProbPrices);\n+}\n+\n+\n+\n+\n+static void MovePos(CLzmaEnc *p, UInt32 num)\n+{\n+  #ifdef SHOW_STAT\n+  ttt += num;\n+  printf(\"\\n MovePos %d\", num);\n+  #endif\n+  if (num != 0)\n+  {\n+    p->additionalOffset += num;\n+    p->matchFinder.Skip(p->matchFinderObj, num);\n+  }\n+}\n+\n+static UInt32 ReadMatchDistances(CLzmaEnc *p, UInt32 *numDistancePairsRes)\n+{\n+  UInt32 lenRes = 0, numPairs;\n+  p->numAvail = p->matchFinder.GetNumAvailableBytes(p->matchFinderObj);\n+  numPairs = p->matchFinder.GetMatches(p->matchFinderObj, p->matches);\n+  #ifdef SHOW_STAT\n+  printf(\"\\n i = %d numPairs = %d    \", ttt, numPairs / 2);\n+  ttt++;\n+  {\n+    UInt32 i;\n+    for (i = 0; i < numPairs; i += 2)\n+      printf(\"%2d %6d   | \", p->matches[i], p->matches[i + 1]);\n+  }\n+  #endif\n+  if (numPairs > 0)\n+  {\n+    lenRes = p->matches[numPairs - 2];\n+    if (lenRes == p->numFastBytes)\n+    {\n+      const Byte *pby = p->matchFinder.GetPointerToCurrentPos(p->matchFinderObj) - 1;\n+      UInt32 distance = p->matches[numPairs - 1] + 1;\n+      UInt32 numAvail = p->numAvail;\n+      if (numAvail > LZMA_MATCH_LEN_MAX)\n+        numAvail = LZMA_MATCH_LEN_MAX;\n+      {\n+        const Byte *pby2 = pby - distance;\n+        for (; lenRes < numAvail && pby[lenRes] == pby2[lenRes]; lenRes++);\n+      }\n+    }\n+  }\n+  p->additionalOffset++;\n+  *numDistancePairsRes = numPairs;\n+  return lenRes;\n+}\n+\n+\n+#define MakeAsChar(p) (p)->backPrev = (UInt32)(-1); (p)->prev1IsChar = False;\n+#define MakeAsShortRep(p) (p)->backPrev = 0; (p)->prev1IsChar = False;\n+#define IsShortRep(p) ((p)->backPrev == 0)\n+\n+static UInt32 GetRepLen1Price(CLzmaEnc *p, UInt32 state, UInt32 posState)\n+{\n+  return\n+    GET_PRICE_0(p->isRepG0[state]) +\n+    GET_PRICE_0(p->isRep0Long[state][posState]);\n+}\n+\n+static UInt32 GetPureRepPrice(CLzmaEnc *p, UInt32 repIndex, UInt32 state, UInt32 posState)\n+{\n+  UInt32 price;\n+  if (repIndex == 0)\n+  {\n+    price = GET_PRICE_0(p->isRepG0[state]);\n+    price += GET_PRICE_1(p->isRep0Long[state][posState]);\n+  }\n+  else\n+  {\n+    price = GET_PRICE_1(p->isRepG0[state]);\n+    if (repIndex == 1)\n+      price += GET_PRICE_0(p->isRepG1[state]);\n+    else\n+    {\n+      price += GET_PRICE_1(p->isRepG1[state]);\n+      price += GET_PRICE(p->isRepG2[state], repIndex - 2);\n+    }\n+  }\n+  return price;\n+}\n+\n+static UInt32 GetRepPrice(CLzmaEnc *p, UInt32 repIndex, UInt32 len, UInt32 state, UInt32 posState)\n+{\n+  return p->repLenEnc.prices[posState][len - LZMA_MATCH_LEN_MIN] +\n+    GetPureRepPrice(p, repIndex, state, posState);\n+}\n+\n+static UInt32 Backward(CLzmaEnc *p, UInt32 *backRes, UInt32 cur)\n+{\n+  UInt32 posMem = p->opt[cur].posPrev;\n+  UInt32 backMem = p->opt[cur].backPrev;\n+  p->optimumEndIndex = cur;\n+  do\n+  {\n+    if (p->opt[cur].prev1IsChar)\n+    {\n+      MakeAsChar(&p->opt[posMem])\n+      p->opt[posMem].posPrev = posMem - 1;\n+      if (p->opt[cur].prev2)\n+      {\n+        p->opt[posMem - 1].prev1IsChar = False;\n+        p->opt[posMem - 1].posPrev = p->opt[cur].posPrev2;\n+        p->opt[posMem - 1].backPrev = p->opt[cur].backPrev2;\n+      }\n+    }\n+    {\n+      UInt32 posPrev = posMem;\n+      UInt32 backCur = backMem;\n+\n+      backMem = p->opt[posPrev].backPrev;\n+      posMem = p->opt[posPrev].posPrev;\n+\n+      p->opt[posPrev].backPrev = backCur;\n+      p->opt[posPrev].posPrev = cur;\n+      cur = posPrev;\n+    }\n+  }\n+  while (cur != 0);\n+  *backRes = p->opt[0].backPrev;\n+  p->optimumCurrentIndex  = p->opt[0].posPrev;\n+  return p->optimumCurrentIndex;\n+}\n+\n+#define LIT_PROBS(pos, prevByte) (p->litProbs + ((((pos) & p->lpMask) << p->lc) + ((prevByte) >> (8 - p->lc))) * 0x300)\n+\n+static UInt32 GetOptimum(CLzmaEnc *p, UInt32 position, UInt32 *backRes)\n+{\n+  UInt32 numAvail, mainLen, numPairs, repMaxIndex, i, posState, lenEnd, len, cur;\n+  UInt32 matchPrice, repMatchPrice, normalMatchPrice;\n+  UInt32 reps[LZMA_NUM_REPS], repLens[LZMA_NUM_REPS];\n+  UInt32 *matches;\n+  const Byte *data;\n+  Byte curByte, matchByte;\n+  if (p->optimumEndIndex != p->optimumCurrentIndex)\n+  {\n+    const COptimal *opt = &p->opt[p->optimumCurrentIndex];\n+    UInt32 lenRes = opt->posPrev - p->optimumCurrentIndex;\n+    *backRes = opt->backPrev;\n+    p->optimumCurrentIndex = opt->posPrev;\n+    return lenRes;\n+  }\n+  p->optimumCurrentIndex = p->optimumEndIndex = 0;\n+\n+  if (p->additionalOffset == 0)\n+    mainLen = ReadMatchDistances(p, &numPairs);\n+  else\n+  {\n+    mainLen = p->longestMatchLength;\n+    numPairs = p->numPairs;\n+  }\n+\n+  numAvail = p->numAvail;\n+  if (numAvail < 2)\n+  {\n+    *backRes = (UInt32)(-1);\n+    return 1;\n+  }\n+  if (numAvail > LZMA_MATCH_LEN_MAX)\n+    numAvail = LZMA_MATCH_LEN_MAX;\n+\n+  data = p->matchFinder.GetPointerToCurrentPos(p->matchFinderObj) - 1;\n+  repMaxIndex = 0;\n+  for (i = 0; i < LZMA_NUM_REPS; i++)\n+  {\n+    UInt32 lenTest;\n+    const Byte *data2;\n+    reps[i] = p->reps[i];\n+    data2 = data - (reps[i] + 1);\n+    if (data[0] != data2[0] || data[1] != data2[1])\n+    {\n+      repLens[i] = 0;\n+      continue;\n+    }\n+    for (lenTest = 2; lenTest < numAvail && data[lenTest] == data2[lenTest]; lenTest++);\n+    repLens[i] = lenTest;\n+    if (lenTest > repLens[repMaxIndex])\n+      repMaxIndex = i;\n+  }\n+  if (repLens[repMaxIndex] >= p->numFastBytes)\n+  {\n+    UInt32 lenRes;\n+    *backRes = repMaxIndex;\n+    lenRes = repLens[repMaxIndex];\n+    MovePos(p, lenRes - 1);\n+    return lenRes;\n+  }\n+\n+  matches = p->matches;\n+  if (mainLen >= p->numFastBytes)\n+  {\n+    *backRes = matches[numPairs - 1] + LZMA_NUM_REPS;\n+    MovePos(p, mainLen - 1);\n+    return mainLen;\n+  }\n+  curByte = *data;\n+  matchByte = *(data - (reps[0] + 1));\n+\n+  if (mainLen < 2 && curByte != matchByte && repLens[repMaxIndex] < 2)\n+  {\n+    *backRes = (UInt32)-1;\n+    return 1;\n+  }\n+\n+  p->opt[0].state = (CState)p->state;\n+\n+  posState = (position & p->pbMask);\n+\n+  {\n+    const CLzmaProb *probs = LIT_PROBS(position, *(data - 1));\n+    p->opt[1].price = GET_PRICE_0(p->isMatch[p->state][posState]) +\n+        (!IsCharState(p->state) ?\n+          LitEnc_GetPriceMatched(probs, curByte, matchByte, p->ProbPrices) :\n+          LitEnc_GetPrice(probs, curByte, p->ProbPrices));\n+  }\n+\n+  MakeAsChar(&p->opt[1]);\n+\n+  matchPrice = GET_PRICE_1(p->isMatch[p->state][posState]);\n+  repMatchPrice = matchPrice + GET_PRICE_1(p->isRep[p->state]);\n+\n+  if (matchByte == curByte)\n+  {\n+    UInt32 shortRepPrice = repMatchPrice + GetRepLen1Price(p, p->state, posState);\n+    if (shortRepPrice < p->opt[1].price)\n+    {\n+      p->opt[1].price = shortRepPrice;\n+      MakeAsShortRep(&p->opt[1]);\n+    }\n+  }\n+  lenEnd = ((mainLen >= repLens[repMaxIndex]) ? mainLen : repLens[repMaxIndex]);\n+\n+  if (lenEnd < 2)\n+  {\n+    *backRes = p->opt[1].backPrev;\n+    return 1;\n+  }\n+\n+  p->opt[1].posPrev = 0;\n+  for (i = 0; i < LZMA_NUM_REPS; i++)\n+    p->opt[0].backs[i] = reps[i];\n+\n+  len = lenEnd;\n+  do\n+    p->opt[len--].price = kInfinityPrice;\n+  while (len >= 2);\n+\n+  for (i = 0; i < LZMA_NUM_REPS; i++)\n+  {\n+    UInt32 repLen = repLens[i];\n+    UInt32 price;\n+    if (repLen < 2)\n+      continue;\n+    price = repMatchPrice + GetPureRepPrice(p, i, p->state, posState);\n+    do\n+    {\n+      UInt32 curAndLenPrice = price + p->repLenEnc.prices[posState][repLen - 2];\n+      COptimal *opt = &p->opt[repLen];\n+      if (curAndLenPrice < opt->price)\n+      {\n+        opt->price = curAndLenPrice;\n+        opt->posPrev = 0;\n+        opt->backPrev = i;\n+        opt->prev1IsChar = False;\n+      }\n+    }\n+    while (--repLen >= 2);\n+  }\n+\n+  normalMatchPrice = matchPrice + GET_PRICE_0(p->isRep[p->state]);\n+\n+  len = ((repLens[0] >= 2) ? repLens[0] + 1 : 2);\n+  if (len <= mainLen)\n+  {\n+    UInt32 offs = 0;\n+    while (len > matches[offs])\n+      offs += 2;\n+    for (; ; len++)\n+    {\n+      COptimal *opt;\n+      UInt32 distance = matches[offs + 1];\n+\n+      UInt32 curAndLenPrice = normalMatchPrice + p->lenEnc.prices[posState][len - LZMA_MATCH_LEN_MIN];\n+      UInt32 lenToPosState = GetLenToPosState(len);\n+      if (distance < kNumFullDistances)\n+        curAndLenPrice += p->distancesPrices[lenToPosState][distance];\n+      else\n+      {\n+        UInt32 slot;\n+        GetPosSlot2(distance, slot);\n+        curAndLenPrice += p->alignPrices[distance & kAlignMask] + p->posSlotPrices[lenToPosState][slot];\n+      }\n+      opt = &p->opt[len];\n+      if (curAndLenPrice < opt->price)\n+      {\n+        opt->price = curAndLenPrice;\n+        opt->posPrev = 0;\n+        opt->backPrev = distance + LZMA_NUM_REPS;\n+        opt->prev1IsChar = False;\n+      }\n+      if (len == matches[offs])\n+      {\n+        offs += 2;\n+        if (offs == numPairs)\n+          break;\n+      }\n+    }\n+  }\n+\n+  cur = 0;\n+\n+    #ifdef SHOW_STAT2\n+    if (position >= 0)\n+    {\n+      unsigned i;\n+      printf(\"\\n pos = %4X\", position);\n+      for (i = cur; i <= lenEnd; i++)\n+      printf(\"\\nprice[%4X] = %d\", position - cur + i, p->opt[i].price);\n+    }\n+    #endif\n+\n+  for (;;)\n+  {\n+    UInt32 numAvailFull, newLen, numPairs, posPrev, state, posState, startLen;\n+    UInt32 curPrice, curAnd1Price, matchPrice, repMatchPrice;\n+    Bool nextIsChar;\n+    Byte curByte, matchByte;\n+    const Byte *data;\n+    COptimal *curOpt;\n+    COptimal *nextOpt;\n+\n+    cur++;\n+    if (cur == lenEnd)\n+      return Backward(p, backRes, cur);\n+\n+    newLen = ReadMatchDistances(p, &numPairs);\n+    if (newLen >= p->numFastBytes)\n+    {\n+      p->numPairs = numPairs;\n+      p->longestMatchLength = newLen;\n+      return Backward(p, backRes, cur);\n+    }\n+    position++;\n+    curOpt = &p->opt[cur];\n+    posPrev = curOpt->posPrev;\n+    if (curOpt->prev1IsChar)\n+    {\n+      posPrev--;\n+      if (curOpt->prev2)\n+      {\n+        state = p->opt[curOpt->posPrev2].state;\n+        if (curOpt->backPrev2 < LZMA_NUM_REPS)\n+          state = kRepNextStates[state];\n+        else\n+          state = kMatchNextStates[state];\n+      }\n+      else\n+        state = p->opt[posPrev].state;\n+      state = kLiteralNextStates[state];\n+    }\n+    else\n+      state = p->opt[posPrev].state;\n+    if (posPrev == cur - 1)\n+    {\n+      if (IsShortRep(curOpt))\n+        state = kShortRepNextStates[state];\n+      else\n+        state = kLiteralNextStates[state];\n+    }\n+    else\n+    {\n+      UInt32 pos;\n+      const COptimal *prevOpt;\n+      if (curOpt->prev1IsChar && curOpt->prev2)\n+      {\n+        posPrev = curOpt->posPrev2;\n+        pos = curOpt->backPrev2;\n+        state = kRepNextStates[state];\n+      }\n+      else\n+      {\n+        pos = curOpt->backPrev;\n+        if (pos < LZMA_NUM_REPS)\n+          state = kRepNextStates[state];\n+        else\n+          state = kMatchNextStates[state];\n+      }\n+      prevOpt = &p->opt[posPrev];\n+      if (pos < LZMA_NUM_REPS)\n+      {\n+        UInt32 i;\n+        reps[0] = prevOpt->backs[pos];\n+        for (i = 1; i <= pos; i++)\n+          reps[i] = prevOpt->backs[i - 1];\n+        for (; i < LZMA_NUM_REPS; i++)\n+          reps[i] = prevOpt->backs[i];\n+      }\n+      else\n+      {\n+        UInt32 i;\n+        reps[0] = (pos - LZMA_NUM_REPS);\n+        for (i = 1; i < LZMA_NUM_REPS; i++)\n+          reps[i] = prevOpt->backs[i - 1];\n+      }\n+    }\n+    curOpt->state = (CState)state;\n+\n+    curOpt->backs[0] = reps[0];\n+    curOpt->backs[1] = reps[1];\n+    curOpt->backs[2] = reps[2];\n+    curOpt->backs[3] = reps[3];\n+\n+    curPrice = curOpt->price;\n+    nextIsChar = False;\n+    data = p->matchFinder.GetPointerToCurrentPos(p->matchFinderObj) - 1;\n+    curByte = *data;\n+    matchByte = *(data - (reps[0] + 1));\n+\n+    posState = (position & p->pbMask);\n+\n+    curAnd1Price = curPrice + GET_PRICE_0(p->isMatch[state][posState]);\n+    {\n+      const CLzmaProb *probs = LIT_PROBS(position, *(data - 1));\n+      curAnd1Price +=\n+        (!IsCharState(state) ?\n+          LitEnc_GetPriceMatched(probs, curByte, matchByte, p->ProbPrices) :\n+          LitEnc_GetPrice(probs, curByte, p->ProbPrices));\n+    }\n+\n+    nextOpt = &p->opt[cur + 1];\n+\n+    if (curAnd1Price < nextOpt->price)\n+    {\n+      nextOpt->price = curAnd1Price;\n+      nextOpt->posPrev = cur;\n+      MakeAsChar(nextOpt);\n+      nextIsChar = True;\n+    }\n+\n+    matchPrice = curPrice + GET_PRICE_1(p->isMatch[state][posState]);\n+    repMatchPrice = matchPrice + GET_PRICE_1(p->isRep[state]);\n+\n+    if (matchByte == curByte && !(nextOpt->posPrev < cur && nextOpt->backPrev == 0))\n+    {\n+      UInt32 shortRepPrice = repMatchPrice + GetRepLen1Price(p, state, posState);\n+      if (shortRepPrice <= nextOpt->price)\n+      {\n+        nextOpt->price = shortRepPrice;\n+        nextOpt->posPrev = cur;\n+        MakeAsShortRep(nextOpt);\n+        nextIsChar = True;\n+      }\n+    }\n+    numAvailFull = p->numAvail;\n+    {\n+      UInt32 temp = kNumOpts - 1 - cur;\n+      if (temp < numAvailFull)\n+        numAvailFull = temp;\n+    }\n+\n+    if (numAvailFull < 2)\n+      continue;\n+    numAvail = (numAvailFull <= p->numFastBytes ? numAvailFull : p->numFastBytes);\n+\n+    if (!nextIsChar && matchByte != curByte) /* speed optimization */\n+    {\n+      /* try Literal + rep0 */\n+      UInt32 temp;\n+      UInt32 lenTest2;\n+      const Byte *data2 = data - (reps[0] + 1);\n+      UInt32 limit = p->numFastBytes + 1;\n+      if (limit > numAvailFull)\n+        limit = numAvailFull;\n+\n+      for (temp = 1; temp < limit && data[temp] == data2[temp]; temp++);\n+      lenTest2 = temp - 1;\n+      if (lenTest2 >= 2)\n+      {\n+        UInt32 state2 = kLiteralNextStates[state];\n+        UInt32 posStateNext = (position + 1) & p->pbMask;\n+        UInt32 nextRepMatchPrice = curAnd1Price +\n+            GET_PRICE_1(p->isMatch[state2][posStateNext]) +\n+            GET_PRICE_1(p->isRep[state2]);\n+        /* for (; lenTest2 >= 2; lenTest2--) */\n+        {\n+          UInt32 curAndLenPrice;\n+          COptimal *opt;\n+          UInt32 offset = cur + 1 + lenTest2;\n+          while (lenEnd < offset)\n+            p->opt[++lenEnd].price = kInfinityPrice;\n+          curAndLenPrice = nextRepMatchPrice + GetRepPrice(p, 0, lenTest2, state2, posStateNext);\n+          opt = &p->opt[offset];\n+          if (curAndLenPrice < opt->price)\n+          {\n+            opt->price = curAndLenPrice;\n+            opt->posPrev = cur + 1;\n+            opt->backPrev = 0;\n+            opt->prev1IsChar = True;\n+            opt->prev2 = False;\n+          }\n+        }\n+      }\n+    }\n+\n+    startLen = 2; /* speed optimization */\n+    {\n+    UInt32 repIndex;\n+    for (repIndex = 0; repIndex < LZMA_NUM_REPS; repIndex++)\n+    {\n+      UInt32 lenTest;\n+      UInt32 lenTestTemp;\n+      UInt32 price;\n+      const Byte *data2 = data - (reps[repIndex] + 1);\n+      if (data[0] != data2[0] || data[1] != data2[1])\n+        continue;\n+      for (lenTest = 2; lenTest < numAvail && data[lenTest] == data2[lenTest]; lenTest++);\n+      while (lenEnd < cur + lenTest)\n+        p->opt[++lenEnd].price = kInfinityPrice;\n+      lenTestTemp = lenTest;\n+      price = repMatchPrice + GetPureRepPrice(p, repIndex, state, posState);\n+      do\n+      {\n+        UInt32 curAndLenPrice = price + p->repLenEnc.prices[posState][lenTest - 2];\n+        COptimal *opt = &p->opt[cur + lenTest];\n+        if (curAndLenPrice < opt->price)\n+        {\n+          opt->price = curAndLenPrice;\n+          opt->posPrev = cur;\n+          opt->backPrev = repIndex;\n+          opt->prev1IsChar = False;\n+        }\n+      }\n+      while (--lenTest >= 2);\n+      lenTest = lenTestTemp;\n+\n+      if (repIndex == 0)\n+        startLen = lenTest + 1;\n+\n+      /* if (_maxMode) */\n+        {\n+          UInt32 lenTest2 = lenTest + 1;\n+          UInt32 limit = lenTest2 + p->numFastBytes;\n+          UInt32 nextRepMatchPrice;\n+          if (limit > numAvailFull)\n+            limit = numAvailFull;\n+          for (; lenTest2 < limit && data[lenTest2] == data2[lenTest2]; lenTest2++);\n+          lenTest2 -= lenTest + 1;\n+          if (lenTest2 >= 2)\n+          {\n+            UInt32 state2 = kRepNextStates[state];\n+            UInt32 posStateNext = (position + lenTest) & p->pbMask;\n+            UInt32 curAndLenCharPrice =\n+                price + p->repLenEnc.prices[posState][lenTest - 2] +\n+                GET_PRICE_0(p->isMatch[state2][posStateNext]) +\n+                LitEnc_GetPriceMatched(LIT_PROBS(position + lenTest, data[lenTest - 1]),\n+                    data[lenTest], data2[lenTest], p->ProbPrices);\n+            state2 = kLiteralNextStates[state2];\n+            posStateNext = (position + lenTest + 1) & p->pbMask;\n+            nextRepMatchPrice = curAndLenCharPrice +\n+                GET_PRICE_1(p->isMatch[state2][posStateNext]) +\n+                GET_PRICE_1(p->isRep[state2]);\n+\n+            /* for (; lenTest2 >= 2; lenTest2--) */\n+            {\n+              UInt32 curAndLenPrice;\n+              COptimal *opt;\n+              UInt32 offset = cur + lenTest + 1 + lenTest2;\n+              while (lenEnd < offset)\n+                p->opt[++lenEnd].price = kInfinityPrice;\n+              curAndLenPrice = nextRepMatchPrice + GetRepPrice(p, 0, lenTest2, state2, posStateNext);\n+              opt = &p->opt[offset];\n+              if (curAndLenPrice < opt->price)\n+              {\n+                opt->price = curAndLenPrice;\n+                opt->posPrev = cur + lenTest + 1;\n+                opt->backPrev = 0;\n+                opt->prev1IsChar = True;\n+                opt->prev2 = True;\n+                opt->posPrev2 = cur;\n+                opt->backPrev2 = repIndex;\n+              }\n+            }\n+          }\n+        }\n+    }\n+    }\n+    /* for (UInt32 lenTest = 2; lenTest <= newLen; lenTest++) */\n+    if (newLen > numAvail)\n+    {\n+      newLen = numAvail;\n+      for (numPairs = 0; newLen > matches[numPairs]; numPairs += 2);\n+      matches[numPairs] = newLen;\n+      numPairs += 2;\n+    }\n+    if (newLen >= startLen)\n+    {\n+      UInt32 normalMatchPrice = matchPrice + GET_PRICE_0(p->isRep[state]);\n+      UInt32 offs, curBack, posSlot;\n+      UInt32 lenTest;\n+      while (lenEnd < cur + newLen)\n+        p->opt[++lenEnd].price = kInfinityPrice;\n+\n+      offs = 0;\n+      while (startLen > matches[offs])\n+        offs += 2;\n+      curBack = matches[offs + 1];\n+      GetPosSlot2(curBack, posSlot);\n+      for (lenTest = /*2*/ startLen; ; lenTest++)\n+      {\n+        UInt32 curAndLenPrice = normalMatchPrice + p->lenEnc.prices[posState][lenTest - LZMA_MATCH_LEN_MIN];\n+        UInt32 lenToPosState = GetLenToPosState(lenTest);\n+        COptimal *opt;\n+        if (curBack < kNumFullDistances)\n+          curAndLenPrice += p->distancesPrices[lenToPosState][curBack];\n+        else\n+          curAndLenPrice += p->posSlotPrices[lenToPosState][posSlot] + p->alignPrices[curBack & kAlignMask];\n+\n+        opt = &p->opt[cur + lenTest];\n+        if (curAndLenPrice < opt->price)\n+        {\n+          opt->price = curAndLenPrice;\n+          opt->posPrev = cur;\n+          opt->backPrev = curBack + LZMA_NUM_REPS;\n+          opt->prev1IsChar = False;\n+        }\n+\n+        if (/*_maxMode && */lenTest == matches[offs])\n+        {\n+          /* Try Match + Literal + Rep0 */\n+          const Byte *data2 = data - (curBack + 1);\n+          UInt32 lenTest2 = lenTest + 1;\n+          UInt32 limit = lenTest2 + p->numFastBytes;\n+          UInt32 nextRepMatchPrice;\n+          if (limit > numAvailFull)\n+            limit = numAvailFull;\n+          for (; lenTest2 < limit && data[lenTest2] == data2[lenTest2]; lenTest2++);\n+          lenTest2 -= lenTest + 1;\n+          if (lenTest2 >= 2)\n+          {\n+            UInt32 state2 = kMatchNextStates[state];\n+            UInt32 posStateNext = (position + lenTest) & p->pbMask;\n+            UInt32 curAndLenCharPrice = curAndLenPrice +\n+                GET_PRICE_0(p->isMatch[state2][posStateNext]) +\n+                LitEnc_GetPriceMatched(LIT_PROBS(position + lenTest, data[lenTest - 1]),\n+                    data[lenTest], data2[lenTest], p->ProbPrices);\n+            state2 = kLiteralNextStates[state2];\n+            posStateNext = (posStateNext + 1) & p->pbMask;\n+            nextRepMatchPrice = curAndLenCharPrice +\n+                GET_PRICE_1(p->isMatch[state2][posStateNext]) +\n+                GET_PRICE_1(p->isRep[state2]);\n+\n+            /* for (; lenTest2 >= 2; lenTest2--) */\n+            {\n+              UInt32 offset = cur + lenTest + 1 + lenTest2;\n+              UInt32 curAndLenPrice;\n+              COptimal *opt;\n+              while (lenEnd < offset)\n+                p->opt[++lenEnd].price = kInfinityPrice;\n+              curAndLenPrice = nextRepMatchPrice + GetRepPrice(p, 0, lenTest2, state2, posStateNext);\n+              opt = &p->opt[offset];\n+              if (curAndLenPrice < opt->price)\n+              {\n+                opt->price = curAndLenPrice;\n+                opt->posPrev = cur + lenTest + 1;\n+                opt->backPrev = 0;\n+                opt->prev1IsChar = True;\n+                opt->prev2 = True;\n+                opt->posPrev2 = cur;\n+                opt->backPrev2 = curBack + LZMA_NUM_REPS;\n+              }\n+            }\n+          }\n+          offs += 2;\n+          if (offs == numPairs)\n+            break;\n+          curBack = matches[offs + 1];\n+          if (curBack >= kNumFullDistances)\n+            GetPosSlot2(curBack, posSlot);\n+        }\n+      }\n+    }\n+  }\n+}\n+\n+#define ChangePair(smallDist, bigDist) (((bigDist) >> 7) > (smallDist))\n+\n+static UInt32 GetOptimumFast(CLzmaEnc *p, UInt32 *backRes)\n+{\n+  UInt32 numAvail, mainLen, mainDist, numPairs, repIndex, repLen, i;\n+  const Byte *data;\n+  const UInt32 *matches;\n+\n+  if (p->additionalOffset == 0)\n+    mainLen = ReadMatchDistances(p, &numPairs);\n+  else\n+  {\n+    mainLen = p->longestMatchLength;\n+    numPairs = p->numPairs;\n+  }\n+\n+  numAvail = p->numAvail;\n+  *backRes = (UInt32)-1;\n+  if (numAvail < 2)\n+    return 1;\n+  if (numAvail > LZMA_MATCH_LEN_MAX)\n+    numAvail = LZMA_MATCH_LEN_MAX;\n+  data = p->matchFinder.GetPointerToCurrentPos(p->matchFinderObj) - 1;\n+\n+  repLen = repIndex = 0;\n+  for (i = 0; i < LZMA_NUM_REPS; i++)\n+  {\n+    UInt32 len;\n+    const Byte *data2 = data - (p->reps[i] + 1);\n+    if (data[0] != data2[0] || data[1] != data2[1])\n+      continue;\n+    for (len = 2; len < numAvail && data[len] == data2[len]; len++);\n+    if (len >= p->numFastBytes)\n+    {\n+      *backRes = i;\n+      MovePos(p, len - 1);\n+      return len;\n+    }\n+    if (len > repLen)\n+    {\n+      repIndex = i;\n+      repLen = len;\n+    }\n+  }\n+\n+  matches = p->matches;\n+  if (mainLen >= p->numFastBytes)\n+  {\n+    *backRes = matches[numPairs - 1] + LZMA_NUM_REPS;\n+    MovePos(p, mainLen - 1);\n+    return mainLen;\n+  }\n+\n+  mainDist = 0; /* for GCC */\n+  if (mainLen >= 2)\n+  {\n+    mainDist = matches[numPairs - 1];\n+    while (numPairs > 2 && mainLen == matches[numPairs - 4] + 1)\n+    {\n+      if (!ChangePair(matches[numPairs - 3], mainDist))\n+        break;\n+      numPairs -= 2;\n+      mainLen = matches[numPairs - 2];\n+      mainDist = matches[numPairs - 1];\n+    }\n+    if (mainLen == 2 && mainDist >= 0x80)\n+      mainLen = 1;\n+  }\n+\n+  if (repLen >= 2 && (\n+        (repLen + 1 >= mainLen) ||\n+        (repLen + 2 >= mainLen && mainDist >= (1 << 9)) ||\n+        (repLen + 3 >= mainLen && mainDist >= (1 << 15))))\n+  {\n+    *backRes = repIndex;\n+    MovePos(p, repLen - 1);\n+    return repLen;\n+  }\n+\n+  if (mainLen < 2 || numAvail <= 2)\n+    return 1;\n+\n+  p->longestMatchLength = ReadMatchDistances(p, &p->numPairs);\n+  if (p->longestMatchLength >= 2)\n+  {\n+    UInt32 newDistance = matches[p->numPairs - 1];\n+    if ((p->longestMatchLength >= mainLen && newDistance < mainDist) ||\n+        (p->longestMatchLength == mainLen + 1 && !ChangePair(mainDist, newDistance)) ||\n+        (p->longestMatchLength > mainLen + 1) ||\n+        (p->longestMatchLength + 1 >= mainLen && mainLen >= 3 && ChangePair(newDistance, mainDist)))\n+      return 1;\n+  }\n+\n+  data = p->matchFinder.GetPointerToCurrentPos(p->matchFinderObj) - 1;\n+  for (i = 0; i < LZMA_NUM_REPS; i++)\n+  {\n+    UInt32 len, limit;\n+    const Byte *data2 = data - (p->reps[i] + 1);\n+    if (data[0] != data2[0] || data[1] != data2[1])\n+      continue;\n+    limit = mainLen - 1;\n+    for (len = 2; len < limit && data[len] == data2[len]; len++);\n+    if (len >= limit)\n+      return 1;\n+  }\n+  *backRes = mainDist + LZMA_NUM_REPS;\n+  MovePos(p, mainLen - 2);\n+  return mainLen;\n+}\n+\n+static void WriteEndMarker(CLzmaEnc *p, UInt32 posState)\n+{\n+  UInt32 len;\n+  RangeEnc_EncodeBit(&p->rc, &p->isMatch[p->state][posState], 1);\n+  RangeEnc_EncodeBit(&p->rc, &p->isRep[p->state], 0);\n+  p->state = kMatchNextStates[p->state];\n+  len = LZMA_MATCH_LEN_MIN;\n+  LenEnc_Encode2(&p->lenEnc, &p->rc, len - LZMA_MATCH_LEN_MIN, posState, !p->fastMode, p->ProbPrices);\n+  RcTree_Encode(&p->rc, p->posSlotEncoder[GetLenToPosState(len)], kNumPosSlotBits, (1 << kNumPosSlotBits) - 1);\n+  RangeEnc_EncodeDirectBits(&p->rc, (((UInt32)1 << 30) - 1) >> kNumAlignBits, 30 - kNumAlignBits);\n+  RcTree_ReverseEncode(&p->rc, p->posAlignEncoder, kNumAlignBits, kAlignMask);\n+}\n+\n+static SRes CheckErrors(CLzmaEnc *p)\n+{\n+  if (p->result != SZ_OK)\n+    return p->result;\n+  if (p->rc.res != SZ_OK)\n+    p->result = SZ_ERROR_WRITE;\n+  if (p->matchFinderBase.result != SZ_OK)\n+    p->result = SZ_ERROR_READ;\n+  if (p->result != SZ_OK)\n+    p->finished = True;\n+  return p->result;\n+}\n+\n+static SRes Flush(CLzmaEnc *p, UInt32 nowPos)\n+{\n+  /* ReleaseMFStream(); */\n+  p->finished = True;\n+  if (p->writeEndMark)\n+    WriteEndMarker(p, nowPos & p->pbMask);\n+  RangeEnc_FlushData(&p->rc);\n+  RangeEnc_FlushStream(&p->rc);\n+  return CheckErrors(p);\n+}\n+\n+static void FillAlignPrices(CLzmaEnc *p)\n+{\n+  UInt32 i;\n+  for (i = 0; i < kAlignTableSize; i++)\n+    p->alignPrices[i] = RcTree_ReverseGetPrice(p->posAlignEncoder, kNumAlignBits, i, p->ProbPrices);\n+  p->alignPriceCount = 0;\n+}\n+\n+static void FillDistancesPrices(CLzmaEnc *p)\n+{\n+  UInt32 tempPrices[kNumFullDistances];\n+  UInt32 i, lenToPosState;\n+  for (i = kStartPosModelIndex; i < kNumFullDistances; i++)\n+  {\n+    UInt32 posSlot = GetPosSlot1(i);\n+    UInt32 footerBits = ((posSlot >> 1) - 1);\n+    UInt32 base = ((2 | (posSlot & 1)) << footerBits);\n+    tempPrices[i] = RcTree_ReverseGetPrice(p->posEncoders + base - posSlot - 1, footerBits, i - base, p->ProbPrices);\n+  }\n+\n+  for (lenToPosState = 0; lenToPosState < kNumLenToPosStates; lenToPosState++)\n+  {\n+    UInt32 posSlot;\n+    const CLzmaProb *encoder = p->posSlotEncoder[lenToPosState];\n+    UInt32 *posSlotPrices = p->posSlotPrices[lenToPosState];\n+    for (posSlot = 0; posSlot < p->distTableSize; posSlot++)\n+      posSlotPrices[posSlot] = RcTree_GetPrice(encoder, kNumPosSlotBits, posSlot, p->ProbPrices);\n+    for (posSlot = kEndPosModelIndex; posSlot < p->distTableSize; posSlot++)\n+      posSlotPrices[posSlot] += ((((posSlot >> 1) - 1) - kNumAlignBits) << kNumBitPriceShiftBits);\n+\n+    {\n+      UInt32 *distancesPrices = p->distancesPrices[lenToPosState];\n+      UInt32 i;\n+      for (i = 0; i < kStartPosModelIndex; i++)\n+        distancesPrices[i] = posSlotPrices[i];\n+      for (; i < kNumFullDistances; i++)\n+        distancesPrices[i] = posSlotPrices[GetPosSlot1(i)] + tempPrices[i];\n+    }\n+  }\n+  p->matchPriceCount = 0;\n+}\n+\n+void LzmaEnc_Construct(CLzmaEnc *p)\n+{\n+  RangeEnc_Construct(&p->rc);\n+  MatchFinder_Construct(&p->matchFinderBase);\n+  #ifndef _7ZIP_ST\n+  MatchFinderMt_Construct(&p->matchFinderMt);\n+  p->matchFinderMt.MatchFinder = &p->matchFinderBase;\n+  #endif\n+\n+  {\n+    CLzmaEncProps props;\n+    LzmaEncProps_Init(&props);\n+    LzmaEnc_SetProps(p, &props);\n+  }\n+\n+  #ifndef LZMA_LOG_BSR\n+  LzmaEnc_FastPosInit(p->g_FastPos);\n+  #endif\n+\n+  LzmaEnc_InitPriceTables(p->ProbPrices);\n+  p->litProbs = 0;\n+  p->saveState.litProbs = 0;\n+}\n+\n+CLzmaEncHandle LzmaEnc_Create(ISzAlloc *alloc)\n+{\n+  void *p;\n+  p = alloc->Alloc(alloc, sizeof(CLzmaEnc));\n+  if (p != 0)\n+    LzmaEnc_Construct((CLzmaEnc *)p);\n+  return p;\n+}\n+\n+void LzmaEnc_FreeLits(CLzmaEnc *p, ISzAlloc *alloc)\n+{\n+  alloc->Free(alloc, p->litProbs);\n+  alloc->Free(alloc, p->saveState.litProbs);\n+  p->litProbs = 0;\n+  p->saveState.litProbs = 0;\n+}\n+\n+void LzmaEnc_Destruct(CLzmaEnc *p, ISzAlloc *alloc, ISzAlloc *allocBig)\n+{\n+  #ifndef _7ZIP_ST\n+  MatchFinderMt_Destruct(&p->matchFinderMt, allocBig);\n+  #endif\n+  MatchFinder_Free(&p->matchFinderBase, allocBig);\n+  LzmaEnc_FreeLits(p, alloc);\n+  RangeEnc_Free(&p->rc, alloc);\n+}\n+\n+void LzmaEnc_Destroy(CLzmaEncHandle p, ISzAlloc *alloc, ISzAlloc *allocBig)\n+{\n+  LzmaEnc_Destruct((CLzmaEnc *)p, alloc, allocBig);\n+  alloc->Free(alloc, p);\n+}\n+\n+static SRes LzmaEnc_CodeOneBlock(CLzmaEnc *p, Bool useLimits, UInt32 maxPackSize, UInt32 maxUnpackSize)\n+{\n+  UInt32 nowPos32, startPos32;\n+  if (p->needInit)\n+  {\n+    p->matchFinder.Init(p->matchFinderObj);\n+    p->needInit = 0;\n+  }\n+\n+  if (p->finished)\n+    return p->result;\n+  RINOK(CheckErrors(p));\n+\n+  nowPos32 = (UInt32)p->nowPos64;\n+  startPos32 = nowPos32;\n+\n+  if (p->nowPos64 == 0)\n+  {\n+    UInt32 numPairs;\n+    Byte curByte;\n+    if (p->matchFinder.GetNumAvailableBytes(p->matchFinderObj) == 0)\n+      return Flush(p, nowPos32);\n+    ReadMatchDistances(p, &numPairs);\n+    RangeEnc_EncodeBit(&p->rc, &p->isMatch[p->state][0], 0);\n+    p->state = kLiteralNextStates[p->state];\n+    curByte = p->matchFinder.GetIndexByte(p->matchFinderObj, 0 - p->additionalOffset);\n+    LitEnc_Encode(&p->rc, p->litProbs, curByte);\n+    p->additionalOffset--;\n+    nowPos32++;\n+  }\n+\n+  if (p->matchFinder.GetNumAvailableBytes(p->matchFinderObj) != 0)\n+  for (;;)\n+  {\n+    UInt32 pos, len, posState;\n+\n+    if (p->fastMode)\n+      len = GetOptimumFast(p, &pos);\n+    else\n+      len = GetOptimum(p, nowPos32, &pos);\n+\n+    #ifdef SHOW_STAT2\n+    printf(\"\\n pos = %4X,   len = %d   pos = %d\", nowPos32, len, pos);\n+    #endif\n+\n+    posState = nowPos32 & p->pbMask;\n+    if (len == 1 && pos == (UInt32)-1)\n+    {\n+      Byte curByte;\n+      CLzmaProb *probs;\n+      const Byte *data;\n+\n+      RangeEnc_EncodeBit(&p->rc, &p->isMatch[p->state][posState], 0);\n+      data = p->matchFinder.GetPointerToCurrentPos(p->matchFinderObj) - p->additionalOffset;\n+      curByte = *data;\n+      probs = LIT_PROBS(nowPos32, *(data - 1));\n+      if (IsCharState(p->state))\n+        LitEnc_Encode(&p->rc, probs, curByte);\n+      else\n+        LitEnc_EncodeMatched(&p->rc, probs, curByte, *(data - p->reps[0] - 1));\n+      p->state = kLiteralNextStates[p->state];\n+    }\n+    else\n+    {\n+      RangeEnc_EncodeBit(&p->rc, &p->isMatch[p->state][posState], 1);\n+      if (pos < LZMA_NUM_REPS)\n+      {\n+        RangeEnc_EncodeBit(&p->rc, &p->isRep[p->state], 1);\n+        if (pos == 0)\n+        {\n+          RangeEnc_EncodeBit(&p->rc, &p->isRepG0[p->state], 0);\n+          RangeEnc_EncodeBit(&p->rc, &p->isRep0Long[p->state][posState], ((len == 1) ? 0 : 1));\n+        }\n+        else\n+        {\n+          UInt32 distance = p->reps[pos];\n+          RangeEnc_EncodeBit(&p->rc, &p->isRepG0[p->state], 1);\n+          if (pos == 1)\n+            RangeEnc_EncodeBit(&p->rc, &p->isRepG1[p->state], 0);\n+          else\n+          {\n+            RangeEnc_EncodeBit(&p->rc, &p->isRepG1[p->state], 1);\n+            RangeEnc_EncodeBit(&p->rc, &p->isRepG2[p->state], pos - 2);\n+            if (pos == 3)\n+              p->reps[3] = p->reps[2];\n+            p->reps[2] = p->reps[1];\n+          }\n+          p->reps[1] = p->reps[0];\n+          p->reps[0] = distance;\n+        }\n+        if (len == 1)\n+          p->state = kShortRepNextStates[p->state];\n+        else\n+        {\n+          LenEnc_Encode2(&p->repLenEnc, &p->rc, len - LZMA_MATCH_LEN_MIN, posState, !p->fastMode, p->ProbPrices);\n+          p->state = kRepNextStates[p->state];\n+        }\n+      }\n+      else\n+      {\n+        UInt32 posSlot;\n+        RangeEnc_EncodeBit(&p->rc, &p->isRep[p->state], 0);\n+        p->state = kMatchNextStates[p->state];\n+        LenEnc_Encode2(&p->lenEnc, &p->rc, len - LZMA_MATCH_LEN_MIN, posState, !p->fastMode, p->ProbPrices);\n+        pos -= LZMA_NUM_REPS;\n+        GetPosSlot(pos, posSlot);\n+        RcTree_Encode(&p->rc, p->posSlotEncoder[GetLenToPosState(len)], kNumPosSlotBits, posSlot);\n+\n+        if (posSlot >= kStartPosModelIndex)\n+        {\n+          UInt32 footerBits = ((posSlot >> 1) - 1);\n+          UInt32 base = ((2 | (posSlot & 1)) << footerBits);\n+          UInt32 posReduced = pos - base;\n+\n+          if (posSlot < kEndPosModelIndex)\n+            RcTree_ReverseEncode(&p->rc, p->posEncoders + base - posSlot - 1, footerBits, posReduced);\n+          else\n+          {\n+            RangeEnc_EncodeDirectBits(&p->rc, posReduced >> kNumAlignBits, footerBits - kNumAlignBits);\n+            RcTree_ReverseEncode(&p->rc, p->posAlignEncoder, kNumAlignBits, posReduced & kAlignMask);\n+            p->alignPriceCount++;\n+          }\n+        }\n+        p->reps[3] = p->reps[2];\n+        p->reps[2] = p->reps[1];\n+        p->reps[1] = p->reps[0];\n+        p->reps[0] = pos;\n+        p->matchPriceCount++;\n+      }\n+    }\n+    p->additionalOffset -= len;\n+    nowPos32 += len;\n+    if (p->additionalOffset == 0)\n+    {\n+      UInt32 processed;\n+      if (!p->fastMode)\n+      {\n+        if (p->matchPriceCount >= (1 << 7))\n+          FillDistancesPrices(p);\n+        if (p->alignPriceCount >= kAlignTableSize)\n+          FillAlignPrices(p);\n+      }\n+      if (p->matchFinder.GetNumAvailableBytes(p->matchFinderObj) == 0)\n+        break;\n+      processed = nowPos32 - startPos32;\n+      if (useLimits)\n+      {\n+        if (processed + kNumOpts + 300 >= maxUnpackSize ||\n+            RangeEnc_GetProcessed(&p->rc) + kNumOpts * 2 >= maxPackSize)\n+          break;\n+      }\n+      else if (processed >= (1 << 15))\n+      {\n+        p->nowPos64 += nowPos32 - startPos32;\n+        return CheckErrors(p);\n+      }\n+    }\n+  }\n+  p->nowPos64 += nowPos32 - startPos32;\n+  return Flush(p, nowPos32);\n+}\n+\n+#define kBigHashDicLimit ((UInt32)1 << 24)\n+\n+static SRes LzmaEnc_Alloc(CLzmaEnc *p, UInt32 keepWindowSize, ISzAlloc *alloc, ISzAlloc *allocBig)\n+{\n+  UInt32 beforeSize = kNumOpts;\n+  Bool btMode;\n+  if (!RangeEnc_Alloc(&p->rc, alloc))\n+    return SZ_ERROR_MEM;\n+  btMode = (p->matchFinderBase.btMode != 0);\n+  #ifndef _7ZIP_ST\n+  p->mtMode = (p->multiThread && !p->fastMode && btMode);\n+  #endif\n+\n+  {\n+    unsigned lclp = p->lc + p->lp;\n+    if (p->litProbs == 0 || p->saveState.litProbs == 0 || p->lclp != lclp)\n+    {\n+      LzmaEnc_FreeLits(p, alloc);\n+      p->litProbs = (CLzmaProb *)alloc->Alloc(alloc, (0x300 << lclp) * sizeof(CLzmaProb));\n+      p->saveState.litProbs = (CLzmaProb *)alloc->Alloc(alloc, (0x300 << lclp) * sizeof(CLzmaProb));\n+      if (p->litProbs == 0 || p->saveState.litProbs == 0)\n+      {\n+        LzmaEnc_FreeLits(p, alloc);\n+        return SZ_ERROR_MEM;\n+      }\n+      p->lclp = lclp;\n+    }\n+  }\n+\n+  p->matchFinderBase.bigHash = (p->dictSize > kBigHashDicLimit);\n+\n+  if (beforeSize + p->dictSize < keepWindowSize)\n+    beforeSize = keepWindowSize - p->dictSize;\n+\n+  #ifndef _7ZIP_ST\n+  if (p->mtMode)\n+  {\n+    RINOK(MatchFinderMt_Create(&p->matchFinderMt, p->dictSize, beforeSize, p->numFastBytes, LZMA_MATCH_LEN_MAX, allocBig));\n+    p->matchFinderObj = &p->matchFinderMt;\n+    MatchFinderMt_CreateVTable(&p->matchFinderMt, &p->matchFinder);\n+  }\n+  else\n+  #endif\n+  {\n+    if (!MatchFinder_Create(&p->matchFinderBase, p->dictSize, beforeSize, p->numFastBytes, LZMA_MATCH_LEN_MAX, allocBig))\n+      return SZ_ERROR_MEM;\n+    p->matchFinderObj = &p->matchFinderBase;\n+    MatchFinder_CreateVTable(&p->matchFinderBase, &p->matchFinder);\n+  }\n+  return SZ_OK;\n+}\n+\n+void LzmaEnc_Init(CLzmaEnc *p)\n+{\n+  UInt32 i;\n+  p->state = 0;\n+  for (i = 0 ; i < LZMA_NUM_REPS; i++)\n+    p->reps[i] = 0;\n+\n+  RangeEnc_Init(&p->rc);\n+\n+\n+  for (i = 0; i < kNumStates; i++)\n+  {\n+    UInt32 j;\n+    for (j = 0; j < LZMA_NUM_PB_STATES_MAX; j++)\n+    {\n+      p->isMatch[i][j] = kProbInitValue;\n+      p->isRep0Long[i][j] = kProbInitValue;\n+    }\n+    p->isRep[i] = kProbInitValue;\n+    p->isRepG0[i] = kProbInitValue;\n+    p->isRepG1[i] = kProbInitValue;\n+    p->isRepG2[i] = kProbInitValue;\n+  }\n+\n+  {\n+    UInt32 num = 0x300 << (p->lp + p->lc);\n+    for (i = 0; i < num; i++)\n+      p->litProbs[i] = kProbInitValue;\n+  }\n+\n+  {\n+    for (i = 0; i < kNumLenToPosStates; i++)\n+    {\n+      CLzmaProb *probs = p->posSlotEncoder[i];\n+      UInt32 j;\n+      for (j = 0; j < (1 << kNumPosSlotBits); j++)\n+        probs[j] = kProbInitValue;\n+    }\n+  }\n+  {\n+    for (i = 0; i < kNumFullDistances - kEndPosModelIndex; i++)\n+      p->posEncoders[i] = kProbInitValue;\n+  }\n+\n+  LenEnc_Init(&p->lenEnc.p);\n+  LenEnc_Init(&p->repLenEnc.p);\n+\n+  for (i = 0; i < (1 << kNumAlignBits); i++)\n+    p->posAlignEncoder[i] = kProbInitValue;\n+\n+  p->optimumEndIndex = 0;\n+  p->optimumCurrentIndex = 0;\n+  p->additionalOffset = 0;\n+\n+  p->pbMask = (1 << p->pb) - 1;\n+  p->lpMask = (1 << p->lp) - 1;\n+}\n+\n+void LzmaEnc_InitPrices(CLzmaEnc *p)\n+{\n+  if (!p->fastMode)\n+  {\n+    FillDistancesPrices(p);\n+    FillAlignPrices(p);\n+  }\n+\n+  p->lenEnc.tableSize =\n+  p->repLenEnc.tableSize =\n+      p->numFastBytes + 1 - LZMA_MATCH_LEN_MIN;\n+  LenPriceEnc_UpdateTables(&p->lenEnc, 1 << p->pb, p->ProbPrices);\n+  LenPriceEnc_UpdateTables(&p->repLenEnc, 1 << p->pb, p->ProbPrices);\n+}\n+\n+static SRes LzmaEnc_AllocAndInit(CLzmaEnc *p, UInt32 keepWindowSize, ISzAlloc *alloc, ISzAlloc *allocBig)\n+{\n+  UInt32 i;\n+  for (i = 0; i < (UInt32)kDicLogSizeMaxCompress; i++)\n+    if (p->dictSize <= ((UInt32)1 << i))\n+      break;\n+  p->distTableSize = i * 2;\n+\n+  p->finished = False;\n+  p->result = SZ_OK;\n+  RINOK(LzmaEnc_Alloc(p, keepWindowSize, alloc, allocBig));\n+  LzmaEnc_Init(p);\n+  LzmaEnc_InitPrices(p);\n+  p->nowPos64 = 0;\n+  return SZ_OK;\n+}\n+\n+static SRes LzmaEnc_Prepare(CLzmaEncHandle pp, ISeqOutStream *outStream, ISeqInStream *inStream,\n+    ISzAlloc *alloc, ISzAlloc *allocBig)\n+{\n+  CLzmaEnc *p = (CLzmaEnc *)pp;\n+  p->matchFinderBase.stream = inStream;\n+  p->needInit = 1;\n+  p->rc.outStream = outStream;\n+  return LzmaEnc_AllocAndInit(p, 0, alloc, allocBig);\n+}\n+\n+SRes LzmaEnc_PrepareForLzma2(CLzmaEncHandle pp,\n+    ISeqInStream *inStream, UInt32 keepWindowSize,\n+    ISzAlloc *alloc, ISzAlloc *allocBig)\n+{\n+  CLzmaEnc *p = (CLzmaEnc *)pp;\n+  p->matchFinderBase.stream = inStream;\n+  p->needInit = 1;\n+  return LzmaEnc_AllocAndInit(p, keepWindowSize, alloc, allocBig);\n+}\n+\n+static void LzmaEnc_SetInputBuf(CLzmaEnc *p, const Byte *src, SizeT srcLen)\n+{\n+  p->matchFinderBase.directInput = 1;\n+  p->matchFinderBase.bufferBase = (Byte *)src;\n+  p->matchFinderBase.directInputRem = srcLen;\n+}\n+\n+SRes LzmaEnc_MemPrepare(CLzmaEncHandle pp, const Byte *src, SizeT srcLen,\n+    UInt32 keepWindowSize, ISzAlloc *alloc, ISzAlloc *allocBig)\n+{\n+  CLzmaEnc *p = (CLzmaEnc *)pp;\n+  LzmaEnc_SetInputBuf(p, src, srcLen);\n+  p->needInit = 1;\n+\n+  return LzmaEnc_AllocAndInit(p, keepWindowSize, alloc, allocBig);\n+}\n+\n+void LzmaEnc_Finish(CLzmaEncHandle pp)\n+{\n+  #ifndef _7ZIP_ST\n+  CLzmaEnc *p = (CLzmaEnc *)pp;\n+  if (p->mtMode)\n+    MatchFinderMt_ReleaseStream(&p->matchFinderMt);\n+  #else\n+  pp = pp;\n+  #endif\n+}\n+\n+typedef struct\n+{\n+  ISeqOutStream funcTable;\n+  Byte *data;\n+  SizeT rem;\n+  Bool overflow;\n+} CSeqOutStreamBuf;\n+\n+static size_t MyWrite(void *pp, const void *data, size_t size)\n+{\n+  CSeqOutStreamBuf *p = (CSeqOutStreamBuf *)pp;\n+  if (p->rem < size)\n+  {\n+    size = p->rem;\n+    p->overflow = True;\n+  }\n+  memcpy(p->data, data, size);\n+  p->rem -= size;\n+  p->data += size;\n+  return size;\n+}\n+\n+\n+UInt32 LzmaEnc_GetNumAvailableBytes(CLzmaEncHandle pp)\n+{\n+  const CLzmaEnc *p = (CLzmaEnc *)pp;\n+  return p->matchFinder.GetNumAvailableBytes(p->matchFinderObj);\n+}\n+\n+const Byte *LzmaEnc_GetCurBuf(CLzmaEncHandle pp)\n+{\n+  const CLzmaEnc *p = (CLzmaEnc *)pp;\n+  return p->matchFinder.GetPointerToCurrentPos(p->matchFinderObj) - p->additionalOffset;\n+}\n+\n+SRes LzmaEnc_CodeOneMemBlock(CLzmaEncHandle pp, Bool reInit,\n+    Byte *dest, size_t *destLen, UInt32 desiredPackSize, UInt32 *unpackSize)\n+{\n+  CLzmaEnc *p = (CLzmaEnc *)pp;\n+  UInt64 nowPos64;\n+  SRes res;\n+  CSeqOutStreamBuf outStream;\n+\n+  outStream.funcTable.Write = MyWrite;\n+  outStream.data = dest;\n+  outStream.rem = *destLen;\n+  outStream.overflow = False;\n+\n+  p->writeEndMark = False;\n+  p->finished = False;\n+  p->result = SZ_OK;\n+\n+  if (reInit)\n+    LzmaEnc_Init(p);\n+  LzmaEnc_InitPrices(p);\n+  nowPos64 = p->nowPos64;\n+  RangeEnc_Init(&p->rc);\n+  p->rc.outStream = &outStream.funcTable;\n+\n+  res = LzmaEnc_CodeOneBlock(p, True, desiredPackSize, *unpackSize);\n+\n+  *unpackSize = (UInt32)(p->nowPos64 - nowPos64);\n+  *destLen -= outStream.rem;\n+  if (outStream.overflow)\n+    return SZ_ERROR_OUTPUT_EOF;\n+\n+  return res;\n+}\n+\n+static SRes LzmaEnc_Encode2(CLzmaEnc *p, ICompressProgress *progress)\n+{\n+  SRes res = SZ_OK;\n+\n+  #ifndef _7ZIP_ST\n+  Byte allocaDummy[0x300];\n+  int i = 0;\n+  for (i = 0; i < 16; i++)\n+    allocaDummy[i] = (Byte)i;\n+  #endif\n+\n+  for (;;)\n+  {\n+    res = LzmaEnc_CodeOneBlock(p, False, 0, 0);\n+    if (res != SZ_OK || p->finished != 0)\n+      break;\n+    if (progress != 0)\n+    {\n+      res = progress->Progress(progress, p->nowPos64, RangeEnc_GetProcessed(&p->rc));\n+      if (res != SZ_OK)\n+      {\n+        res = SZ_ERROR_PROGRESS;\n+        break;\n+      }\n+    }\n+  }\n+  LzmaEnc_Finish(p);\n+  return res;\n+}\n+\n+SRes LzmaEnc_Encode(CLzmaEncHandle pp, ISeqOutStream *outStream, ISeqInStream *inStream, ICompressProgress *progress,\n+    ISzAlloc *alloc, ISzAlloc *allocBig)\n+{\n+  RINOK(LzmaEnc_Prepare(pp, outStream, inStream, alloc, allocBig));\n+  return LzmaEnc_Encode2((CLzmaEnc *)pp, progress);\n+}\n+\n+SRes LzmaEnc_WriteProperties(CLzmaEncHandle pp, Byte *props, SizeT *size)\n+{\n+  CLzmaEnc *p = (CLzmaEnc *)pp;\n+  int i;\n+  UInt32 dictSize = p->dictSize;\n+  if (*size < LZMA_PROPS_SIZE)\n+    return SZ_ERROR_PARAM;\n+  *size = LZMA_PROPS_SIZE;\n+  props[0] = (Byte)((p->pb * 5 + p->lp) * 9 + p->lc);\n+\n+  for (i = 11; i <= 30; i++)\n+  {\n+    if (dictSize <= ((UInt32)2 << i))\n+    {\n+      dictSize = (2 << i);\n+      break;\n+    }\n+    if (dictSize <= ((UInt32)3 << i))\n+    {\n+      dictSize = (3 << i);\n+      break;\n+    }\n+  }\n+\n+  for (i = 0; i < 4; i++)\n+    props[1 + i] = (Byte)(dictSize >> (8 * i));\n+  return SZ_OK;\n+}\n+\n+SRes LzmaEnc_MemEncode(CLzmaEncHandle pp, Byte *dest, SizeT *destLen, const Byte *src, SizeT srcLen,\n+    int writeEndMark, ICompressProgress *progress, ISzAlloc *alloc, ISzAlloc *allocBig)\n+{\n+  SRes res;\n+  CLzmaEnc *p = (CLzmaEnc *)pp;\n+\n+  CSeqOutStreamBuf outStream;\n+\n+  LzmaEnc_SetInputBuf(p, src, srcLen);\n+\n+  outStream.funcTable.Write = MyWrite;\n+  outStream.data = dest;\n+  outStream.rem = *destLen;\n+  outStream.overflow = False;\n+\n+  p->writeEndMark = writeEndMark;\n+\n+  p->rc.outStream = &outStream.funcTable;\n+  res = LzmaEnc_MemPrepare(pp, src, srcLen, 0, alloc, allocBig);\n+  if (res == SZ_OK)\n+    res = LzmaEnc_Encode2(p, progress);\n+\n+  *destLen -= outStream.rem;\n+  if (outStream.overflow)\n+    return SZ_ERROR_OUTPUT_EOF;\n+  return res;\n+}\n+\n+SRes LzmaEncode(Byte *dest, SizeT *destLen, const Byte *src, SizeT srcLen,\n+    const CLzmaEncProps *props, Byte *propsEncoded, SizeT *propsSize, int writeEndMark,\n+    ICompressProgress *progress, ISzAlloc *alloc, ISzAlloc *allocBig)\n+{\n+  CLzmaEnc *p = (CLzmaEnc *)LzmaEnc_Create(alloc);\n+  SRes res;\n+  if (p == 0)\n+    return SZ_ERROR_MEM;\n+\n+  res = LzmaEnc_SetProps(p, props);\n+  if (res == SZ_OK)\n+  {\n+    res = LzmaEnc_WriteProperties(p, propsEncoded, propsSize);\n+    if (res == SZ_OK)\n+      res = LzmaEnc_MemEncode(p, dest, destLen, src, srcLen,\n+          writeEndMark, progress, alloc, allocBig);\n+  }\n+\n+  LzmaEnc_Destroy(p, alloc, allocBig);\n+  return res;\n+}\n--- /dev/null\n+++ b/lib/lzma/Makefile\n@@ -0,0 +1,7 @@\n+lzma_compress-objs := LzFind.o LzmaEnc.o\n+lzma_decompress-objs := LzmaDec.o\n+\n+obj-$(CONFIG_LZMA_COMPRESS) += lzma_compress.o\n+obj-$(CONFIG_LZMA_DECOMPRESS) += lzma_decompress.o\n+\n+EXTRA_CFLAGS += -Iinclude/linux -Iinclude/linux/lzma -include types.h\n"
  },
  {
    "path": "target/linux/generic/pending-5.15/532-jffs2_eofdetect.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nSubject: fs: jffs2: EOF marker\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n fs/jffs2/build.c | 10 ++++++++++\n fs/jffs2/scan.c  | 21 +++++++++++++++++++--\n 2 files changed, 29 insertions(+), 2 deletions(-)\n\n--- a/fs/jffs2/build.c\n+++ b/fs/jffs2/build.c\n@@ -117,6 +117,16 @@ static int jffs2_build_filesystem(struct\n \tdbg_fsbuild(\"scanned flash completely\\n\");\n \tjffs2_dbg_dump_block_lists_nolock(c);\n \n+\tif (c->flags & (1 << 7)) {\n+\t\tprintk(\"%s(): unlocking the mtd device... \", __func__);\n+\t\tmtd_unlock(c->mtd, 0, c->mtd->size);\n+\t\tprintk(\"done.\\n\");\n+\n+\t\tprintk(\"%s(): erasing all blocks after the end marker... \", __func__);\n+\t\tjffs2_erase_pending_blocks(c, -1);\n+\t\tprintk(\"done.\\n\");\n+\t}\n+\n \tdbg_fsbuild(\"pass 1 starting\\n\");\n \tc->flags |= JFFS2_SB_FLAG_BUILDING;\n \t/* Now scan the directory tree, increasing nlink according to every dirent found. */\n--- a/fs/jffs2/scan.c\n+++ b/fs/jffs2/scan.c\n@@ -148,8 +148,14 @@ int jffs2_scan_medium(struct jffs2_sb_in\n \t\t/* reset summary info for next eraseblock scan */\n \t\tjffs2_sum_reset_collected(s);\n \n-\t\tret = jffs2_scan_eraseblock(c, jeb, buf_size?flashbuf:(flashbuf+jeb->offset),\n-\t\t\t\t\t\tbuf_size, s);\n+\t\tif (c->flags & (1 << 7)) {\n+\t\t\tif (mtd_block_isbad(c->mtd, jeb->offset))\n+\t\t\t\tret = BLK_STATE_BADBLOCK;\n+\t\t\telse\n+\t\t\t\tret = BLK_STATE_ALLFF;\n+\t\t} else\n+\t\t\tret = jffs2_scan_eraseblock(c, jeb, buf_size?flashbuf:(flashbuf+jeb->offset),\n+\t\t\t\t\t\t\tbuf_size, s);\n \n \t\tif (ret < 0)\n \t\t\tgoto out;\n@@ -567,6 +573,17 @@ full_scan:\n \t\t\treturn err;\n \t}\n \n+\tif ((buf[0] == 0xde) &&\n+\t\t(buf[1] == 0xad) &&\n+\t\t(buf[2] == 0xc0) &&\n+\t\t(buf[3] == 0xde)) {\n+\t\t/* end of filesystem. erase everything after this point */\n+\t\tprintk(\"%s(): End of filesystem marker found at 0x%x\\n\", __func__, jeb->offset);\n+\t\tc->flags |= (1 << 7);\n+\n+\t\treturn BLK_STATE_ALLFF;\n+\t}\n+\n \t/* We temporarily use 'ofs' as a pointer into the buffer/jeb */\n \tofs = 0;\n \tmax_ofs = EMPTY_SCAN_SIZE(c->sector_size);\n"
  },
  {
    "path": "target/linux/generic/pending-5.15/600-netfilter_conntrack_flush.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nSubject: netfilter: add support for flushing conntrack via /proc\n\nlede-commit 8193bbe59a74d34d6a26d4a8cb857b1952905314\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n net/netfilter/nf_conntrack_standalone.c | 59 ++++++++++++++++++++++++++++++++-\n 1 file changed, 58 insertions(+), 1 deletion(-)\n\n--- a/net/netfilter/nf_conntrack_standalone.c\n+++ b/net/netfilter/nf_conntrack_standalone.c\n@@ -9,6 +9,7 @@\n #include <linux/percpu.h>\n #include <linux/netdevice.h>\n #include <linux/security.h>\n+#include <linux/inet.h>\n #include <net/net_namespace.h>\n #ifdef CONFIG_SYSCTL\n #include <linux/sysctl.h>\n@@ -462,6 +463,56 @@ static int ct_cpu_seq_show(struct seq_fi\n \treturn 0;\n }\n \n+struct kill_request {\n+\tu16 family;\n+\tunion nf_inet_addr addr;\n+};\n+\n+static int kill_matching(struct nf_conn *i, void *data)\n+{\n+\tstruct kill_request *kr = data;\n+\tstruct nf_conntrack_tuple *t1 = &i->tuplehash[IP_CT_DIR_ORIGINAL].tuple;\n+\tstruct nf_conntrack_tuple *t2 = &i->tuplehash[IP_CT_DIR_REPLY].tuple;\n+\n+\tif (!kr->family)\n+\t\treturn 1;\n+\n+\tif (t1->src.l3num != kr->family)\n+\t\treturn 0;\n+\n+\treturn (nf_inet_addr_cmp(&kr->addr, &t1->src.u3) ||\n+\t        nf_inet_addr_cmp(&kr->addr, &t1->dst.u3) ||\n+\t        nf_inet_addr_cmp(&kr->addr, &t2->src.u3) ||\n+\t        nf_inet_addr_cmp(&kr->addr, &t2->dst.u3));\n+}\n+\n+static int ct_file_write(struct file *file, char *buf, size_t count)\n+{\n+\tstruct seq_file *seq = file->private_data;\n+\tstruct net *net = seq_file_net(seq);\n+\tstruct kill_request kr = { };\n+\n+\tif (count == 0)\n+\t\treturn 0;\n+\n+\tif (count >= INET6_ADDRSTRLEN)\n+\t\tcount = INET6_ADDRSTRLEN - 1;\n+\n+\tif (strnchr(buf, count, ':')) {\n+\t\tkr.family = AF_INET6;\n+\t\tif (!in6_pton(buf, count, (void *)&kr.addr, '\\n', NULL))\n+\t\t\treturn -EINVAL;\n+\t} else if (strnchr(buf, count, '.')) {\n+\t\tkr.family = AF_INET;\n+\t\tif (!in4_pton(buf, count, (void *)&kr.addr, '\\n', NULL))\n+\t\t\treturn -EINVAL;\n+\t}\n+\n+\tnf_ct_iterate_cleanup_net(net, kill_matching, &kr, 0, 0);\n+\n+\treturn 0;\n+}\n+\n static const struct seq_operations ct_cpu_seq_ops = {\n \t.start\t= ct_cpu_seq_start,\n \t.next\t= ct_cpu_seq_next,\n@@ -475,8 +526,9 @@ static int nf_conntrack_standalone_init_\n \tkuid_t root_uid;\n \tkgid_t root_gid;\n \n-\tpde = proc_create_net(\"nf_conntrack\", 0440, net->proc_net, &ct_seq_ops,\n-\t\t\tsizeof(struct ct_iter_state));\n+\tpde = proc_create_net_data_write(\"nf_conntrack\", 0440, net->proc_net,\n+\t\t\t\t\t &ct_seq_ops, &ct_file_write,\n+\t\t\t\t\t sizeof(struct ct_iter_state), NULL);\n \tif (!pde)\n \t\tgoto out_nf_conntrack;\n \n"
  },
  {
    "path": "target/linux/generic/pending-5.15/610-netfilter_match_bypass_default_checks.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nSubject: kernel: add a new version of my netfilter speedup patches for linux 2.6.39 and 3.0\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n include/uapi/linux/netfilter_ipv4/ip_tables.h |  1 +\n net/ipv4/netfilter/ip_tables.c                | 37 +++++++++++++++++++++++++++\n 2 files changed, 38 insertions(+)\n\n--- a/include/uapi/linux/netfilter_ipv4/ip_tables.h\n+++ b/include/uapi/linux/netfilter_ipv4/ip_tables.h\n@@ -89,6 +89,7 @@ struct ipt_ip {\n #define IPT_F_FRAG\t\t0x01\t/* Set if rule is a fragment rule */\n #define IPT_F_GOTO\t\t0x02\t/* Set if jump is a goto */\n #define IPT_F_MASK\t\t0x03\t/* All possible flag bits mask. */\n+#define IPT_F_NO_DEF_MATCH\t0x80\t/* Internal: no default match rules present */\n \n /* Values for \"inv\" field in struct ipt_ip. */\n #define IPT_INV_VIA_IN\t\t0x01\t/* Invert the sense of IN IFACE. */\n--- a/net/ipv4/netfilter/ip_tables.c\n+++ b/net/ipv4/netfilter/ip_tables.c\n@@ -50,6 +50,9 @@ ip_packet_match(const struct iphdr *ip,\n {\n \tunsigned long ret;\n \n+\tif (ipinfo->flags & IPT_F_NO_DEF_MATCH)\n+\t\treturn true;\n+\n \tif (NF_INVF(ipinfo, IPT_INV_SRCIP,\n \t\t    (ip->saddr & ipinfo->smsk.s_addr) != ipinfo->src.s_addr) ||\n \t    NF_INVF(ipinfo, IPT_INV_DSTIP,\n@@ -80,6 +83,29 @@ ip_packet_match(const struct iphdr *ip,\n \treturn true;\n }\n \n+static void\n+ip_checkdefault(struct ipt_ip *ip)\n+{\n+\tstatic const char iface_mask[IFNAMSIZ] = {};\n+\n+\tif (ip->invflags || ip->flags & IPT_F_FRAG)\n+\t\treturn;\n+\n+\tif (memcmp(ip->iniface_mask, iface_mask, IFNAMSIZ) != 0)\n+\t\treturn;\n+\n+\tif (memcmp(ip->outiface_mask, iface_mask, IFNAMSIZ) != 0)\n+\t\treturn;\n+\n+\tif (ip->smsk.s_addr || ip->dmsk.s_addr)\n+\t\treturn;\n+\n+\tif (ip->proto)\n+\t\treturn;\n+\n+\tip->flags |= IPT_F_NO_DEF_MATCH;\n+}\n+\n static bool\n ip_checkentry(const struct ipt_ip *ip)\n {\n@@ -524,6 +550,8 @@ find_check_entry(struct ipt_entry *e, st\n \tstruct xt_mtchk_param mtpar;\n \tstruct xt_entry_match *ematch;\n \n+\tip_checkdefault(&e->ip);\n+\n \tif (!xt_percpu_counter_alloc(alloc_state, &e->counters))\n \t\treturn -ENOMEM;\n \n@@ -818,6 +846,7 @@ copy_entries_to_user(unsigned int total_\n \tconst struct xt_table_info *private = table->private;\n \tint ret = 0;\n \tconst void *loc_cpu_entry;\n+\tu8 flags;\n \n \tcounters = alloc_counters(table);\n \tif (IS_ERR(counters))\n@@ -845,6 +874,14 @@ copy_entries_to_user(unsigned int total_\n \t\t\tgoto free_counters;\n \t\t}\n \n+\t\tflags = e->ip.flags & IPT_F_MASK;\n+\t\tif (copy_to_user(userptr + off\n+\t\t\t\t + offsetof(struct ipt_entry, ip.flags),\n+\t\t\t\t &flags, sizeof(flags)) != 0) {\n+\t\t\tret = -EFAULT;\n+\t\t\tgoto free_counters;\n+\t\t}\n+\n \t\tfor (i = sizeof(struct ipt_entry);\n \t\t     i < e->target_offset;\n \t\t     i += m->u.match_size) {\n@@ -1223,12 +1260,15 @@ compat_copy_entry_to_user(struct ipt_ent\n \tcompat_uint_t origsize;\n \tconst struct xt_entry_match *ematch;\n \tint ret = 0;\n+\tu8 flags = e->ip.flags & IPT_F_MASK;\n \n \torigsize = *size;\n \tce = *dstptr;\n \tif (copy_to_user(ce, e, sizeof(struct ipt_entry)) != 0 ||\n \t    copy_to_user(&ce->counters, &counters[i],\n-\t    sizeof(counters[i])) != 0)\n+\t    sizeof(counters[i])) != 0 ||\n+\t    copy_to_user(&ce->ip.flags, &flags,\n+\t    sizeof(flags)) != 0)\n \t\treturn -EFAULT;\n \n \t*dstptr += sizeof(struct compat_ipt_entry);\n"
  },
  {
    "path": "target/linux/generic/pending-5.15/611-netfilter_match_bypass_default_table.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nSubject: netfilter: match bypass default table\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n net/ipv4/netfilter/ip_tables.c | 79 +++++++++++++++++++++++++++++++-----------\n 1 file changed, 58 insertions(+), 21 deletions(-)\n\n--- a/net/ipv4/netfilter/ip_tables.c\n+++ b/net/ipv4/netfilter/ip_tables.c\n@@ -246,6 +246,33 @@ struct ipt_entry *ipt_next_entry(const s\n \treturn (void *)entry + entry->next_offset;\n }\n \n+static bool\n+ipt_handle_default_rule(struct ipt_entry *e, unsigned int *verdict)\n+{\n+\tstruct xt_entry_target *t;\n+\tstruct xt_standard_target *st;\n+\n+\tif (e->target_offset != sizeof(struct ipt_entry))\n+\t\treturn false;\n+\n+\tif (!(e->ip.flags & IPT_F_NO_DEF_MATCH))\n+\t\treturn false;\n+\n+\tt = ipt_get_target(e);\n+\tif (t->u.kernel.target->target)\n+\t\treturn false;\n+\n+\tst = (struct xt_standard_target *) t;\n+\tif (st->verdict == XT_RETURN)\n+\t\treturn false;\n+\n+\tif (st->verdict >= 0)\n+\t\treturn false;\n+\n+\t*verdict = (unsigned)(-st->verdict) - 1;\n+\treturn true;\n+}\n+\n /* Returns one of the generic firewall policies, like NF_ACCEPT. */\n unsigned int\n ipt_do_table(struct sk_buff *skb,\n@@ -266,27 +293,28 @@ ipt_do_table(struct sk_buff *skb,\n \tunsigned int addend;\n \n \t/* Initialization */\n+\tWARN_ON(!(table->valid_hooks & (1 << hook)));\n+\tlocal_bh_disable();\n+\tprivate = READ_ONCE(table->private); /* Address dependency. */\n+\tcpu        = smp_processor_id();\n+\ttable_base = private->entries;\n+\n+\te = get_entry(table_base, private->hook_entry[hook]);\n+\tif (ipt_handle_default_rule(e, &verdict)) {\n+\t\tstruct xt_counters *counter;\n+\n+\t\tcounter = xt_get_this_cpu_counter(&e->counters);\n+\t\tADD_COUNTER(*counter, skb->len, 1);\n+\t\tlocal_bh_enable();\n+\t\treturn verdict;\n+\t}\n+\n \tstackidx = 0;\n \tip = ip_hdr(skb);\n \tindev = state->in ? state->in->name : nulldevname;\n \toutdev = state->out ? state->out->name : nulldevname;\n-\t/* We handle fragments by dealing with the first fragment as\n-\t * if it was a normal packet.  All other fragments are treated\n-\t * normally, except that they will NEVER match rules that ask\n-\t * things we don't know, ie. tcp syn flag or ports).  If the\n-\t * rule is also a fragment-specific rule, non-fragments won't\n-\t * match it. */\n-\tacpar.fragoff = ntohs(ip->frag_off) & IP_OFFSET;\n-\tacpar.thoff   = ip_hdrlen(skb);\n-\tacpar.hotdrop = false;\n-\tacpar.state   = state;\n \n-\tWARN_ON(!(table->valid_hooks & (1 << hook)));\n-\tlocal_bh_disable();\n \taddend = xt_write_recseq_begin();\n-\tprivate = READ_ONCE(table->private); /* Address dependency. */\n-\tcpu        = smp_processor_id();\n-\ttable_base = private->entries;\n \tjumpstack  = (struct ipt_entry **)private->jumpstack[cpu];\n \n \t/* Switch to alternate jumpstack if we're being invoked via TEE.\n@@ -299,7 +327,16 @@ ipt_do_table(struct sk_buff *skb,\n \tif (static_key_false(&xt_tee_enabled))\n \t\tjumpstack += private->stacksize * __this_cpu_read(nf_skb_duplicated);\n \n-\te = get_entry(table_base, private->hook_entry[hook]);\n+\t/* We handle fragments by dealing with the first fragment as\n+\t * if it was a normal packet.  All other fragments are treated\n+\t * normally, except that they will NEVER match rules that ask\n+\t * things we don't know, ie. tcp syn flag or ports).  If the\n+\t * rule is also a fragment-specific rule, non-fragments won't\n+\t * match it. */\n+\tacpar.fragoff = ntohs(ip->frag_off) & IP_OFFSET;\n+\tacpar.thoff   = ip_hdrlen(skb);\n+\tacpar.hotdrop = false;\n+\tacpar.state   = state;\n \n \tdo {\n \t\tconst struct xt_entry_target *t;\n"
  },
  {
    "path": "target/linux/generic/pending-5.15/612-netfilter_match_reduce_memory_access.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nSubject: netfilter: reduce match memory access\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n net/ipv4/netfilter/ip_tables.c | 4 ++--\n 1 file changed, 2 insertions(+), 2 deletions(-)\n\n--- a/net/ipv4/netfilter/ip_tables.c\n+++ b/net/ipv4/netfilter/ip_tables.c\n@@ -53,9 +53,9 @@ ip_packet_match(const struct iphdr *ip,\n \tif (ipinfo->flags & IPT_F_NO_DEF_MATCH)\n \t\treturn true;\n \n-\tif (NF_INVF(ipinfo, IPT_INV_SRCIP,\n+\tif (NF_INVF(ipinfo, IPT_INV_SRCIP, ipinfo->smsk.s_addr &&\n \t\t    (ip->saddr & ipinfo->smsk.s_addr) != ipinfo->src.s_addr) ||\n-\t    NF_INVF(ipinfo, IPT_INV_DSTIP,\n+\t    NF_INVF(ipinfo, IPT_INV_DSTIP, ipinfo->dmsk.s_addr &&\n \t\t    (ip->daddr & ipinfo->dmsk.s_addr) != ipinfo->dst.s_addr))\n \t\treturn false;\n \n"
  },
  {
    "path": "target/linux/generic/pending-5.15/613-netfilter_optional_tcp_window_check.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nSubject: netfilter: optional tcp window check\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n net/netfilter/nf_conntrack_proto_tcp.c | 13 +++++++++++++\n 1 file changed, 13 insertions(+)\n\n--- a/net/netfilter/nf_conntrack_proto_tcp.c\n+++ b/net/netfilter/nf_conntrack_proto_tcp.c\n@@ -465,6 +465,9 @@ static bool tcp_in_window(struct nf_conn\n \ts32 receiver_offset;\n \tbool res, in_recv_win;\n \n+\tif (net->ct.sysctl_no_window_check)\n+\t\treturn true;\n+\n \t/*\n \t * Get the required data from the packet.\n \t */\n@@ -1160,7 +1163,7 @@ int nf_conntrack_tcp_packet(struct nf_co\n \t\t IP_CT_TCP_FLAG_DATA_UNACKNOWLEDGED &&\n \t\t timeouts[new_state] > timeouts[TCP_CONNTRACK_UNACK])\n \t\ttimeout = timeouts[TCP_CONNTRACK_UNACK];\n-\telse if (ct->proto.tcp.last_win == 0 &&\n+\telse if (!net->ct.sysctl_no_window_check && ct->proto.tcp.last_win == 0 &&\n \t\t timeouts[new_state] > timeouts[TCP_CONNTRACK_RETRANS])\n \t\ttimeout = timeouts[TCP_CONNTRACK_RETRANS];\n \telse\n--- a/net/netfilter/nf_conntrack_standalone.c\n+++ b/net/netfilter/nf_conntrack_standalone.c\n@@ -671,6 +671,7 @@ enum nf_ct_sysctl_index {\n \tNF_SYSCTL_CT_LWTUNNEL,\n #endif\n \n+\tNF_SYSCTL_CT_PROTO_TCP_NO_WINDOW_CHECK,\n \t__NF_SYSCTL_CT_LAST_SYSCTL,\n };\n \n@@ -1026,6 +1027,13 @@ static struct ctl_table nf_ct_sysctl_tab\n \t\t.proc_handler\t= nf_hooks_lwtunnel_sysctl_handler,\n \t},\n #endif\n+\t[NF_SYSCTL_CT_PROTO_TCP_NO_WINDOW_CHECK] = {\n+\t\t.procname       = \"nf_conntrack_tcp_no_window_check\",\n+\t\t.data           = &init_net.ct.sysctl_no_window_check,\n+\t\t.maxlen         = sizeof(unsigned int),\n+\t\t.mode           = 0644,\n+\t\t.proc_handler   = proc_dointvec,\n+\t},\n \t{}\n };\n \n@@ -1153,6 +1161,7 @@ static int nf_conntrack_standalone_init_\n #ifdef CONFIG_NF_CONNTRACK_EVENTS\n \ttable[NF_SYSCTL_CT_EVENTS].data = &net->ct.sysctl_events;\n #endif\n+\ttable[NF_SYSCTL_CT_PROTO_TCP_NO_WINDOW_CHECK].data = &net->ct.sysctl_no_window_check;\n #ifdef CONFIG_NF_CONNTRACK_TIMESTAMP\n \ttable[NF_SYSCTL_CT_TIMESTAMP].data = &net->ct.sysctl_tstamp;\n #endif\n@@ -1222,6 +1231,7 @@ static int nf_conntrack_pernet_init(stru\n \tint ret;\n \n \tnet->ct.sysctl_checksum = 1;\n+\tnet->ct.sysctl_no_window_check = 1;\n \n \tret = nf_conntrack_standalone_init_sysctl(net);\n \tif (ret < 0)\n--- a/include/net/netns/conntrack.h\n+++ b/include/net/netns/conntrack.h\n@@ -109,6 +109,7 @@ struct netns_ct {\n \tu8\t\t\tsysctl_auto_assign_helper;\n \tu8\t\t\tsysctl_tstamp;\n \tu8\t\t\tsysctl_checksum;\n+\tu8\t\t\tsysctl_no_window_check;\n \n \tstruct ct_pcpu __percpu *pcpu_lists;\n \tstruct ip_conntrack_stat __percpu *stat;\n"
  },
  {
    "path": "target/linux/generic/pending-5.15/620-net_sched-codel-do-not-defer-queue-length-update.patch",
    "content": "From: Konstantin Khlebnikov <khlebnikov@yandex-team.ru>\nDate: Mon, 21 Aug 2017 11:14:14 +0300\nSubject: [PATCH] net_sched/codel: do not defer queue length update\n\nWhen codel wants to drop last packet in ->dequeue() it cannot call\nqdisc_tree_reduce_backlog() right away - it will notify parent qdisc\nabout zero qlen and HTB/HFSC will deactivate class. The same class will\nbe deactivated second time by caller of ->dequeue(). Currently codel and\nfq_codel defer update. This triggers warning in HFSC when it's qlen != 0\nbut there is no active classes.\n\nThis patch update parent queue length immediately: just temporary increase\nqlen around qdisc_tree_reduce_backlog() to prevent first class deactivation\nif we have skb to return.\n\nThis might open another problem in HFSC - now operation peek could fail and\ndeactivate parent class.\n\nSigned-off-by: Konstantin Khlebnikov <khlebnikov@yandex-team.ru>\nLink: https://bugzilla.kernel.org/show_bug.cgi?id=109581\n---\n\n--- a/net/sched/sch_codel.c\n+++ b/net/sched/sch_codel.c\n@@ -95,11 +95,17 @@ static struct sk_buff *codel_qdisc_deque\n \t\t\t    &q->stats, qdisc_pkt_len, codel_get_enqueue_time,\n \t\t\t    drop_func, dequeue_func);\n \n-\t/* We cant call qdisc_tree_reduce_backlog() if our qlen is 0,\n-\t * or HTB crashes. Defer it for next round.\n+\t/* If our qlen is 0 qdisc_tree_reduce_backlog() will deactivate\n+\t * parent class, dequeue in parent qdisc will do the same if we\n+\t * return skb. Temporary increment qlen if we have skb.\n \t */\n-\tif (q->stats.drop_count && sch->q.qlen) {\n-\t\tqdisc_tree_reduce_backlog(sch, q->stats.drop_count, q->stats.drop_len);\n+\tif (q->stats.drop_count) {\n+\t\tif (skb)\n+\t\t\tsch->q.qlen++;\n+\t\tqdisc_tree_reduce_backlog(sch, q->stats.drop_count,\n+\t\t\t\t\t  q->stats.drop_len);\n+\t\tif (skb)\n+\t\t\tsch->q.qlen--;\n \t\tq->stats.drop_count = 0;\n \t\tq->stats.drop_len = 0;\n \t}\n--- a/net/sched/sch_fq_codel.c\n+++ b/net/sched/sch_fq_codel.c\n@@ -304,6 +304,21 @@ begin:\n \t\t\t    &flow->cvars, &q->cstats, qdisc_pkt_len,\n \t\t\t    codel_get_enqueue_time, drop_func, dequeue_func);\n \n+\t/* If our qlen is 0 qdisc_tree_reduce_backlog() will deactivate\n+\t * parent class, dequeue in parent qdisc will do the same if we\n+\t * return skb. Temporary increment qlen if we have skb.\n+\t */\n+\tif (q->cstats.drop_count) {\n+\t\tif (skb)\n+\t\t\tsch->q.qlen++;\n+\t\tqdisc_tree_reduce_backlog(sch, q->cstats.drop_count,\n+\t\t\t\t\t  q->cstats.drop_len);\n+\t\tif (skb)\n+\t\t\tsch->q.qlen--;\n+\t\tq->cstats.drop_count = 0;\n+\t\tq->cstats.drop_len = 0;\n+\t}\n+\n \tif (!skb) {\n \t\t/* force a pass through old_flows to prevent starvation */\n \t\tif ((head == &q->new_flows) && !list_empty(&q->old_flows))\n@@ -314,15 +329,6 @@ begin:\n \t}\n \tqdisc_bstats_update(sch, skb);\n \tflow->deficit -= qdisc_pkt_len(skb);\n-\t/* We cant call qdisc_tree_reduce_backlog() if our qlen is 0,\n-\t * or HTB crashes. Defer it for next round.\n-\t */\n-\tif (q->cstats.drop_count && sch->q.qlen) {\n-\t\tqdisc_tree_reduce_backlog(sch, q->cstats.drop_count,\n-\t\t\t\t\t  q->cstats.drop_len);\n-\t\tq->cstats.drop_count = 0;\n-\t\tq->cstats.drop_len = 0;\n-\t}\n \treturn skb;\n }\n \n"
  },
  {
    "path": "target/linux/generic/pending-5.15/630-packet_socket_type.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nSubject: net: add an optimization for dealing with raw sockets\n\nlede-commit: 4898039703d7315f0f3431c860123338ec3be0f6\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n include/uapi/linux/if_packet.h |  3 +++\n net/packet/af_packet.c         | 34 +++++++++++++++++++++++++++-------\n net/packet/internal.h          |  1 +\n 3 files changed, 31 insertions(+), 7 deletions(-)\n\n--- a/include/uapi/linux/if_packet.h\n+++ b/include/uapi/linux/if_packet.h\n@@ -33,6 +33,8 @@ struct sockaddr_ll {\n #define PACKET_KERNEL\t\t7\t\t/* To kernel space\t*/\n /* Unused, PACKET_FASTROUTE and PACKET_LOOPBACK are invisible to user space */\n #define PACKET_FASTROUTE\t6\t\t/* Fastrouted frame\t*/\n+#define PACKET_MASK_ANY\t\t0xffffffff\t/* mask for packet type bits */\n+\n \n /* Packet socket options */\n \n@@ -59,6 +61,7 @@ struct sockaddr_ll {\n #define PACKET_ROLLOVER_STATS\t\t21\n #define PACKET_FANOUT_DATA\t\t22\n #define PACKET_IGNORE_OUTGOING\t\t23\n+#define PACKET_RECV_TYPE\t\t24\n \n #define PACKET_FANOUT_HASH\t\t0\n #define PACKET_FANOUT_LB\t\t1\n--- a/net/packet/af_packet.c\n+++ b/net/packet/af_packet.c\n@@ -1825,6 +1825,7 @@ static int packet_rcv_spkt(struct sk_buf\n {\n \tstruct sock *sk;\n \tstruct sockaddr_pkt *spkt;\n+\tstruct packet_sock *po;\n \n \t/*\n \t *\tWhen we registered the protocol we saved the socket in the data\n@@ -1832,6 +1833,7 @@ static int packet_rcv_spkt(struct sk_buf\n \t */\n \n \tsk = pt->af_packet_priv;\n+\tpo = pkt_sk(sk);\n \n \t/*\n \t *\tYank back the headers [hope the device set this\n@@ -1844,7 +1846,7 @@ static int packet_rcv_spkt(struct sk_buf\n \t *\tso that this procedure is noop.\n \t */\n \n-\tif (skb->pkt_type == PACKET_LOOPBACK)\n+\tif (!(po->pkt_type & (1 << skb->pkt_type)))\n \t\tgoto out;\n \n \tif (!net_eq(dev_net(dev), sock_net(sk)))\n@@ -2082,12 +2084,12 @@ static int packet_rcv(struct sk_buff *sk\n \tunsigned int snaplen, res;\n \tbool is_drop_n_account = false;\n \n-\tif (skb->pkt_type == PACKET_LOOPBACK)\n-\t\tgoto drop;\n-\n \tsk = pt->af_packet_priv;\n \tpo = pkt_sk(sk);\n \n+\tif (!(po->pkt_type & (1 << skb->pkt_type)))\n+\t\tgoto drop;\n+\n \tif (!net_eq(dev_net(dev), sock_net(sk)))\n \t\tgoto drop;\n \n@@ -2213,12 +2215,12 @@ static int tpacket_rcv(struct sk_buff *s\n \tBUILD_BUG_ON(TPACKET_ALIGN(sizeof(*h.h2)) != 32);\n \tBUILD_BUG_ON(TPACKET_ALIGN(sizeof(*h.h3)) != 48);\n \n-\tif (skb->pkt_type == PACKET_LOOPBACK)\n-\t\tgoto drop;\n-\n \tsk = pt->af_packet_priv;\n \tpo = pkt_sk(sk);\n \n+\tif (!(po->pkt_type & (1 << skb->pkt_type)))\n+\t\tgoto drop;\n+\n \tif (!net_eq(dev_net(dev), sock_net(sk)))\n \t\tgoto drop;\n \n@@ -3330,6 +3332,7 @@ static int packet_create(struct net *net\n \tmutex_init(&po->pg_vec_lock);\n \tpo->rollover = NULL;\n \tpo->prot_hook.func = packet_rcv;\n+\tpo->pkt_type = PACKET_MASK_ANY & ~(1 << PACKET_LOOPBACK);\n \n \tif (sock->type == SOCK_PACKET)\n \t\tpo->prot_hook.func = packet_rcv_spkt;\n@@ -3971,6 +3974,16 @@ packet_setsockopt(struct socket *sock, i\n \t\tpo->xmit = val ? packet_direct_xmit : dev_queue_xmit;\n \t\treturn 0;\n \t}\n+\tcase PACKET_RECV_TYPE:\n+\t{\n+\t\tunsigned int val;\n+\t\tif (optlen != sizeof(val))\n+\t\t\treturn -EINVAL;\n+\t\tif (copy_from_sockptr(&val, optval, sizeof(val)))\n+\t\t\treturn -EFAULT;\n+\t\tpo->pkt_type = val & ~BIT(PACKET_LOOPBACK);\n+\t\treturn 0;\n+\t}\n \tdefault:\n \t\treturn -ENOPROTOOPT;\n \t}\n@@ -4027,6 +4040,13 @@ static int packet_getsockopt(struct sock\n \tcase PACKET_VNET_HDR:\n \t\tval = po->has_vnet_hdr;\n \t\tbreak;\n+\tcase PACKET_RECV_TYPE:\n+\t\tif (len > sizeof(unsigned int))\n+\t\t\tlen = sizeof(unsigned int);\n+\t\tval = po->pkt_type;\n+\n+\t\tdata = &val;\n+\t\tbreak;\n \tcase PACKET_VERSION:\n \t\tval = po->tp_version;\n \t\tbreak;\n--- a/net/packet/internal.h\n+++ b/net/packet/internal.h\n@@ -137,6 +137,7 @@ struct packet_sock {\n \tint\t\t\t(*xmit)(struct sk_buff *skb);\n \tstruct packet_type\tprot_hook ____cacheline_aligned_in_smp;\n \tatomic_t\t\ttp_drops ____cacheline_aligned_in_smp;\n+\tunsigned int\t\tpkt_type;\n };\n \n static inline struct packet_sock *pkt_sk(struct sock *sk)\n"
  },
  {
    "path": "target/linux/generic/pending-5.15/655-increase_skb_pad.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nSubject: kernel: add a few patches for avoiding unnecessary skb reallocations - significantly improves ethernet<->wireless performance\n\nlede-commit: 6f89cffc9add6939d44a6b54cf9a5e77849aa7fd\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n include/linux/skbuff.h | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/include/linux/skbuff.h\n+++ b/include/linux/skbuff.h\n@@ -2737,7 +2737,7 @@ static inline int pskb_network_may_pull(\n  * NET_IP_ALIGN(2) + ethernet_header(14) + IP_header(20/40) + ports(8)\n  */\n #ifndef NET_SKB_PAD\n-#define NET_SKB_PAD\tmax(32, L1_CACHE_BYTES)\n+#define NET_SKB_PAD\tmax(64, L1_CACHE_BYTES)\n #endif\n \n int ___pskb_trim(struct sk_buff *skb, unsigned int len);\n"
  },
  {
    "path": "target/linux/generic/pending-5.15/666-Add-support-for-MAP-E-FMRs-mesh-mode.patch",
    "content": "From: Steven Barth <steven@midlink.org>\nSubject: Add support for MAP-E FMRs (mesh mode)\n\nMAP-E FMRs (draft-ietf-softwire-map-10) are rules for IPv4-communication\nbetween MAP CEs (mesh mode) without the need to forward such data to a\nborder relay. This is similar to how 6rd works but for IPv4 over IPv6.\n\nSigned-off-by: Steven Barth <cyrus@openwrt.org>\n---\n include/net/ip6_tunnel.h       |  13 ++\n include/uapi/linux/if_tunnel.h |  13 ++\n net/ipv6/ip6_tunnel.c          | 276 +++++++++++++++++++++++++++++++++++++++--\n 3 files changed, 291 insertions(+), 11 deletions(-)\n\n--- a/include/net/ip6_tunnel.h\n+++ b/include/net/ip6_tunnel.h\n@@ -18,6 +18,18 @@\n /* determine capability on a per-packet basis */\n #define IP6_TNL_F_CAP_PER_PACKET 0x40000\n \n+/* IPv6 tunnel FMR */\n+struct __ip6_tnl_fmr {\n+\tstruct __ip6_tnl_fmr *next; /* next fmr in list */\n+\tstruct in6_addr ip6_prefix;\n+\tstruct in_addr ip4_prefix;\n+\n+\t__u8 ip6_prefix_len;\n+\t__u8 ip4_prefix_len;\n+\t__u8 ea_len;\n+\t__u8 offset;\n+};\n+\n struct __ip6_tnl_parm {\n \tchar name[IFNAMSIZ];\t/* name of tunnel device */\n \tint link;\t\t/* ifindex of underlying L2 interface */\n@@ -29,6 +41,7 @@ struct __ip6_tnl_parm {\n \t__u32 flags;\t\t/* tunnel flags */\n \tstruct in6_addr laddr;\t/* local tunnel end-point address */\n \tstruct in6_addr raddr;\t/* remote tunnel end-point address */\n+\tstruct __ip6_tnl_fmr *fmrs;\t/* FMRs */\n \n \t__be16\t\t\ti_flags;\n \t__be16\t\t\to_flags;\n--- a/include/uapi/linux/if_tunnel.h\n+++ b/include/uapi/linux/if_tunnel.h\n@@ -77,10 +77,23 @@ enum {\n \tIFLA_IPTUN_ENCAP_DPORT,\n \tIFLA_IPTUN_COLLECT_METADATA,\n \tIFLA_IPTUN_FWMARK,\n+\tIFLA_IPTUN_FMRS,\n \t__IFLA_IPTUN_MAX,\n };\n #define IFLA_IPTUN_MAX\t(__IFLA_IPTUN_MAX - 1)\n \n+enum {\n+\tIFLA_IPTUN_FMR_UNSPEC,\n+\tIFLA_IPTUN_FMR_IP6_PREFIX,\n+\tIFLA_IPTUN_FMR_IP4_PREFIX,\n+\tIFLA_IPTUN_FMR_IP6_PREFIX_LEN,\n+\tIFLA_IPTUN_FMR_IP4_PREFIX_LEN,\n+\tIFLA_IPTUN_FMR_EA_LEN,\n+\tIFLA_IPTUN_FMR_OFFSET,\n+\t__IFLA_IPTUN_FMR_MAX,\n+};\n+#define IFLA_IPTUN_FMR_MAX (__IFLA_IPTUN_FMR_MAX - 1)\n+\n enum tunnel_encap_types {\n \tTUNNEL_ENCAP_NONE,\n \tTUNNEL_ENCAP_FOU,\n--- a/net/ipv6/ip6_tunnel.c\n+++ b/net/ipv6/ip6_tunnel.c\n@@ -11,6 +11,9 @@\n  *      linux/net/ipv6/sit.c and linux/net/ipv4/ipip.c\n  *\n  *      RFC 2473\n+ *\n+ *      Changes:\n+ *      Steven Barth <cyrus@openwrt.org>:           MAP-E FMR support\n  */\n \n #define pr_fmt(fmt) KBUILD_MODNAME \": \" fmt\n@@ -67,9 +70,9 @@ static bool log_ecn_error = true;\n module_param(log_ecn_error, bool, 0644);\n MODULE_PARM_DESC(log_ecn_error, \"Log packets received with corrupted ECN\");\n \n-static u32 HASH(const struct in6_addr *addr1, const struct in6_addr *addr2)\n+static u32 HASH(const struct in6_addr *addr)\n {\n-\tu32 hash = ipv6_addr_hash(addr1) ^ ipv6_addr_hash(addr2);\n+\tu32 hash = ipv6_addr_hash(addr);\n \n \treturn hash_32(hash, IP6_TUNNEL_HASH_SIZE_SHIFT);\n }\n@@ -114,17 +117,33 @@ static struct ip6_tnl *\n ip6_tnl_lookup(struct net *net, int link,\n \t       const struct in6_addr *remote, const struct in6_addr *local)\n {\n-\tunsigned int hash = HASH(remote, local);\n+\tunsigned int hash = HASH(local);\n \tstruct ip6_tnl *t, *cand = NULL;\n \tstruct ip6_tnl_net *ip6n = net_generic(net, ip6_tnl_net_id);\n \tstruct in6_addr any;\n \n \tfor_each_ip6_tunnel_rcu(ip6n->tnls_r_l[hash]) {\n \t\tif (!ipv6_addr_equal(local, &t->parms.laddr) ||\n-\t\t    !ipv6_addr_equal(remote, &t->parms.raddr) ||\n \t\t    !(t->dev->flags & IFF_UP))\n \t\t\tcontinue;\n \n+\t\tif (!ipv6_addr_equal(remote, &t->parms.raddr)) {\n+\t\t\tstruct __ip6_tnl_fmr *fmr;\n+\t\t\tbool found = false;\n+\n+\t\t\tfor (fmr = t->parms.fmrs; fmr; fmr = fmr->next) {\n+\t\t\t\tif (!ipv6_prefix_equal(remote, &fmr->ip6_prefix,\n+\t\t\t\t\t\t       fmr->ip6_prefix_len))\n+\t\t\t\t\tcontinue;\n+\n+\t\t\t\tfound = true;\n+\t\t\t\tbreak;\n+\t\t\t}\n+\n+\t\t\tif (!found)\n+\t\t\t\tcontinue;\n+\t\t}\n+\n \t\tif (link == t->parms.link)\n \t\t\treturn t;\n \t\telse\n@@ -132,7 +151,7 @@ ip6_tnl_lookup(struct net *net, int link\n \t}\n \n \tmemset(&any, 0, sizeof(any));\n-\thash = HASH(&any, local);\n+\thash = HASH(local);\n \tfor_each_ip6_tunnel_rcu(ip6n->tnls_r_l[hash]) {\n \t\tif (!ipv6_addr_equal(local, &t->parms.laddr) ||\n \t\t    !ipv6_addr_any(&t->parms.raddr) ||\n@@ -145,7 +164,7 @@ ip6_tnl_lookup(struct net *net, int link\n \t\t\tcand = t;\n \t}\n \n-\thash = HASH(remote, &any);\n+\thash = HASH(&any);\n \tfor_each_ip6_tunnel_rcu(ip6n->tnls_r_l[hash]) {\n \t\tif (!ipv6_addr_equal(remote, &t->parms.raddr) ||\n \t\t    !ipv6_addr_any(&t->parms.laddr) ||\n@@ -194,7 +213,7 @@ ip6_tnl_bucket(struct ip6_tnl_net *ip6n,\n \n \tif (!ipv6_addr_any(remote) || !ipv6_addr_any(local)) {\n \t\tprio = 1;\n-\t\th = HASH(remote, local);\n+\t\th = HASH(local);\n \t}\n \treturn &ip6n->tnls[prio][h];\n }\n@@ -378,6 +397,12 @@ ip6_tnl_dev_uninit(struct net_device *de\n \tstruct net *net = t->net;\n \tstruct ip6_tnl_net *ip6n = net_generic(net, ip6_tnl_net_id);\n \n+\twhile (t->parms.fmrs) {\n+\t\tstruct __ip6_tnl_fmr *next = t->parms.fmrs->next;\n+\t\tkfree(t->parms.fmrs);\n+\t\tt->parms.fmrs = next;\n+\t}\n+\n \tif (dev == ip6n->fb_tnl_dev)\n \t\tRCU_INIT_POINTER(ip6n->tnls_wc[0], NULL);\n \telse\n@@ -790,6 +815,107 @@ int ip6_tnl_rcv_ctl(struct ip6_tnl *t,\n }\n EXPORT_SYMBOL_GPL(ip6_tnl_rcv_ctl);\n \n+/**\n+ * ip4ip6_fmr_calc - calculate target / source IPv6-address based on FMR\n+ *   @dest: destination IPv6 address buffer\n+ *   @skb: received socket buffer\n+ *   @fmr: MAP FMR\n+ *   @xmit: Calculate for xmit or rcv\n+ **/\n+static void ip4ip6_fmr_calc(struct in6_addr *dest,\n+\t\tconst struct iphdr *iph, const uint8_t *end,\n+\t\tconst struct __ip6_tnl_fmr *fmr, bool xmit)\n+{\n+\tint psidlen = fmr->ea_len - (32 - fmr->ip4_prefix_len);\n+\tu8 *portp = NULL;\n+\tbool use_dest_addr;\n+\tconst struct iphdr *dsth = iph;\n+\n+\tif ((u8*)dsth >= end)\n+\t\treturn;\n+\n+\t/* find significant IP header */\n+\tif (iph->protocol == IPPROTO_ICMP) {\n+\t\tstruct icmphdr *ih = (struct icmphdr*)(((u8*)dsth) + dsth->ihl * 4);\n+\t\tif (ih && ((u8*)&ih[1]) <= end && (\n+\t\t\tih->type == ICMP_DEST_UNREACH ||\n+\t\t\tih->type == ICMP_SOURCE_QUENCH ||\n+\t\t\tih->type == ICMP_TIME_EXCEEDED ||\n+\t\t\tih->type == ICMP_PARAMETERPROB ||\n+\t\t\tih->type == ICMP_REDIRECT))\n+\t\t\t\tdsth = (const struct iphdr*)&ih[1];\n+\t}\n+\n+\t/* in xmit-path use dest port by default and source port only if\n+\t\tthis is an ICMP reply to something else; vice versa in rcv-path */\n+\tuse_dest_addr = (xmit && dsth == iph) || (!xmit && dsth != iph);\n+\n+\t/* get dst port */\n+\tif (((u8*)&dsth[1]) <= end && (\n+\t\tdsth->protocol == IPPROTO_UDP ||\n+\t\tdsth->protocol == IPPROTO_TCP ||\n+\t\tdsth->protocol == IPPROTO_SCTP ||\n+\t\tdsth->protocol == IPPROTO_DCCP)) {\n+\t\t\t/* for UDP, TCP, SCTP and DCCP source and dest port\n+\t\t\tfollow IPv4 header directly */\n+\t\t\tportp = ((u8*)dsth) + dsth->ihl * 4;\n+\n+\t\t\tif (use_dest_addr)\n+\t\t\t\tportp += sizeof(u16);\n+\t} else if (iph->protocol == IPPROTO_ICMP) {\n+\t\tstruct icmphdr *ih = (struct icmphdr*)(((u8*)dsth) + dsth->ihl * 4);\n+\n+\t\t/* use icmp identifier as port */\n+\t\tif (((u8*)&ih) <= end && (\n+\t\t    (use_dest_addr && (\n+\t\t    ih->type == ICMP_ECHOREPLY ||\n+\t\t\tih->type == ICMP_TIMESTAMPREPLY ||\n+\t\t\tih->type == ICMP_INFO_REPLY ||\n+\t\t\tih->type == ICMP_ADDRESSREPLY)) ||\n+\t\t\t(!use_dest_addr && (\n+\t\t\tih->type == ICMP_ECHO ||\n+\t\t\tih->type == ICMP_TIMESTAMP ||\n+\t\t\tih->type == ICMP_INFO_REQUEST ||\n+\t\t\tih->type == ICMP_ADDRESS)\n+\t\t\t)))\n+\t\t\t\tportp = (u8*)&ih->un.echo.id;\n+\t}\n+\n+\tif ((portp && &portp[2] <= end) || psidlen == 0) {\n+\t\tint frombyte = fmr->ip6_prefix_len / 8;\n+\t\tint fromrem = fmr->ip6_prefix_len % 8;\n+\t\tint bytes = sizeof(struct in6_addr) - frombyte;\n+\t\tconst u32 *addr = (use_dest_addr) ? &iph->daddr : &iph->saddr;\n+\t\tu64 eabits = ((u64)ntohl(*addr)) << (32 + fmr->ip4_prefix_len);\n+\t\tu64 t = 0;\n+\n+\t\t/* extract PSID from port and add it to eabits */\n+\t\tu16 psidbits = 0;\n+\t\tif (psidlen > 0) {\n+\t\t\tpsidbits = ((u16)portp[0]) << 8 | ((u16)portp[1]);\n+\t\t\tpsidbits >>= 16 - psidlen - fmr->offset;\n+\t\t\tpsidbits = (u16)(psidbits << (16 - psidlen));\n+\t\t\teabits |= ((u64)psidbits) << (48 - (fmr->ea_len - psidlen));\n+\t\t}\n+\n+\t\t/* rewrite destination address */\n+\t\t*dest = fmr->ip6_prefix;\n+\t\tmemcpy(&dest->s6_addr[10], addr, sizeof(*addr));\n+\t\tdest->s6_addr16[7] = htons(psidbits >> (16 - psidlen));\n+\n+\t\tif (bytes > sizeof(u64))\n+\t\t\tbytes = sizeof(u64);\n+\n+\t\t/* insert eabits */\n+\t\tmemcpy(&t, &dest->s6_addr[frombyte], bytes);\n+\t\tt = be64_to_cpu(t) & ~(((((u64)1) << fmr->ea_len) - 1)\n+\t\t\t<< (64 - fmr->ea_len - fromrem));\n+\t\tt = cpu_to_be64(t | (eabits >> fromrem));\n+\t\tmemcpy(&dest->s6_addr[frombyte], &t, bytes);\n+\t}\n+}\n+\n+\n static int __ip6_tnl_rcv(struct ip6_tnl *tunnel, struct sk_buff *skb,\n \t\t\t const struct tnl_ptk_info *tpi,\n \t\t\t struct metadata_dst *tun_dst,\n@@ -843,6 +969,27 @@ static int __ip6_tnl_rcv(struct ip6_tnl\n \tskb_reset_network_header(skb);\n \tmemset(skb->cb, 0, sizeof(struct inet6_skb_parm));\n \n+\tif (tpi->proto == htons(ETH_P_IP) && tunnel->parms.fmrs &&\n+\t\t!ipv6_addr_equal(&ipv6h->saddr, &tunnel->parms.raddr)) {\n+\t\t\t/* Packet didn't come from BR, so lookup FMR */\n+\t\t\tstruct __ip6_tnl_fmr *fmr;\n+\t\t\tstruct in6_addr expected = tunnel->parms.raddr;\n+\t\t\tfor (fmr = tunnel->parms.fmrs; fmr; fmr = fmr->next)\n+\t\t\t\tif (ipv6_prefix_equal(&ipv6h->saddr,\n+\t\t\t\t\t&fmr->ip6_prefix, fmr->ip6_prefix_len))\n+\t\t\t\t\t\tbreak;\n+\n+\t\t\t/* Check that IPv6 matches IPv4 source to prevent spoofing */\n+\t\t\tif (fmr)\n+\t\t\t\tip4ip6_fmr_calc(&expected, ip_hdr(skb),\n+\t\t\t\t\t\tskb_tail_pointer(skb), fmr, false);\n+\n+\t\t\tif (!ipv6_addr_equal(&ipv6h->saddr, &expected)) {\n+\t\t\t\trcu_read_unlock();\n+\t\t\t\tgoto drop;\n+\t\t\t}\n+\t}\n+\n \t__skb_tunnel_rx(skb, tunnel->dev, tunnel->net);\n \n \terr = dscp_ecn_decapsulate(tunnel, ipv6h, skb);\n@@ -994,6 +1141,7 @@ static void init_tel_txopt(struct ipv6_t\n \topt->ops.opt_nflen = 8;\n }\n \n+\n /**\n  * ip6_tnl_addr_conflict - compare packet addresses to tunnel's own\n  *   @t: the outgoing tunnel device\n@@ -1274,6 +1422,7 @@ ipxip6_tnl_xmit(struct sk_buff *skb, str\n \t\tu8 protocol)\n {\n \tstruct ip6_tnl *t = netdev_priv(dev);\n+\tstruct __ip6_tnl_fmr *fmr;\n \tstruct ipv6hdr *ipv6h;\n \tconst struct iphdr  *iph;\n \tint encap_limit = -1;\n@@ -1373,6 +1522,18 @@ ipxip6_tnl_xmit(struct sk_buff *skb, str\n \tfl6.flowi6_uid = sock_net_uid(dev_net(dev), NULL);\n \tdsfield = INET_ECN_encapsulate(dsfield, orig_dsfield);\n \n+\t/* try to find matching FMR */\n+\tfor (fmr = t->parms.fmrs; fmr; fmr = fmr->next) {\n+\t\tunsigned mshift = 32 - fmr->ip4_prefix_len;\n+\t\tif (ntohl(fmr->ip4_prefix.s_addr) >> mshift ==\n+\t\t\t\tntohl(ip_hdr(skb)->daddr) >> mshift)\n+\t\t\tbreak;\n+\t}\n+\n+\t/* change dstaddr according to FMR */\n+\tif (fmr)\n+\t\tip4ip6_fmr_calc(&fl6.daddr, ip_hdr(skb), skb_tail_pointer(skb), fmr, true);\n+\n \tif (iptunnel_handle_offloads(skb, SKB_GSO_IPXIP6))\n \t\treturn -1;\n \n@@ -1525,6 +1686,14 @@ ip6_tnl_change(struct ip6_tnl *t, const\n \tt->parms.link = p->link;\n \tt->parms.proto = p->proto;\n \tt->parms.fwmark = p->fwmark;\n+\n+\twhile (t->parms.fmrs) {\n+\t\tstruct __ip6_tnl_fmr *next = t->parms.fmrs->next;\n+\t\tkfree(t->parms.fmrs);\n+\t\tt->parms.fmrs = next;\n+\t}\n+\tt->parms.fmrs = p->fmrs;\n+\n \tdst_cache_reset(&t->dst_cache);\n \tip6_tnl_link_config(t);\n \treturn 0;\n@@ -1563,6 +1732,7 @@ ip6_tnl_parm_from_user(struct __ip6_tnl_\n \tp->flowinfo = u->flowinfo;\n \tp->link = u->link;\n \tp->proto = u->proto;\n+\tp->fmrs = NULL;\n \tmemcpy(p->name, u->name, sizeof(u->name));\n }\n \n@@ -1949,6 +2119,15 @@ static int ip6_tnl_validate(struct nlatt\n \treturn 0;\n }\n \n+static const struct nla_policy ip6_tnl_fmr_policy[IFLA_IPTUN_FMR_MAX + 1] = {\n+\t[IFLA_IPTUN_FMR_IP6_PREFIX] = { .len = sizeof(struct in6_addr) },\n+\t[IFLA_IPTUN_FMR_IP4_PREFIX] = { .len = sizeof(struct in_addr) },\n+\t[IFLA_IPTUN_FMR_IP6_PREFIX_LEN] = { .type = NLA_U8 },\n+\t[IFLA_IPTUN_FMR_IP4_PREFIX_LEN] = { .type = NLA_U8 },\n+\t[IFLA_IPTUN_FMR_EA_LEN] = { .type = NLA_U8 },\n+\t[IFLA_IPTUN_FMR_OFFSET] = { .type = NLA_U8 }\n+};\n+\n static void ip6_tnl_netlink_parms(struct nlattr *data[],\n \t\t\t\t  struct __ip6_tnl_parm *parms)\n {\n@@ -1986,6 +2165,46 @@ static void ip6_tnl_netlink_parms(struct\n \n \tif (data[IFLA_IPTUN_FWMARK])\n \t\tparms->fwmark = nla_get_u32(data[IFLA_IPTUN_FWMARK]);\n+\n+\tif (data[IFLA_IPTUN_FMRS]) {\n+\t\tunsigned rem;\n+\t\tstruct nlattr *fmr;\n+\t\tnla_for_each_nested(fmr, data[IFLA_IPTUN_FMRS], rem) {\n+\t\t\tstruct nlattr *fmrd[IFLA_IPTUN_FMR_MAX + 1], *c;\n+\t\t\tstruct __ip6_tnl_fmr *nfmr;\n+\n+\t\t\tnla_parse_nested(fmrd, IFLA_IPTUN_FMR_MAX,\n+\t\t\t\tfmr, ip6_tnl_fmr_policy, NULL);\n+\n+\t\t\tif (!(nfmr = kzalloc(sizeof(*nfmr), GFP_KERNEL)))\n+\t\t\t\tcontinue;\n+\n+\t\t\tnfmr->offset = 6;\n+\n+\t\t\tif ((c = fmrd[IFLA_IPTUN_FMR_IP6_PREFIX]))\n+\t\t\t\tnla_memcpy(&nfmr->ip6_prefix, fmrd[IFLA_IPTUN_FMR_IP6_PREFIX],\n+\t\t\t\t\tsizeof(nfmr->ip6_prefix));\n+\n+\t\t\tif ((c = fmrd[IFLA_IPTUN_FMR_IP4_PREFIX]))\n+\t\t\t\tnla_memcpy(&nfmr->ip4_prefix, fmrd[IFLA_IPTUN_FMR_IP4_PREFIX],\n+\t\t\t\t\tsizeof(nfmr->ip4_prefix));\n+\n+\t\t\tif ((c = fmrd[IFLA_IPTUN_FMR_IP6_PREFIX_LEN]))\n+\t\t\t\tnfmr->ip6_prefix_len = nla_get_u8(c);\n+\n+\t\t\tif ((c = fmrd[IFLA_IPTUN_FMR_IP4_PREFIX_LEN]))\n+\t\t\t\tnfmr->ip4_prefix_len = nla_get_u8(c);\n+\n+\t\t\tif ((c = fmrd[IFLA_IPTUN_FMR_EA_LEN]))\n+\t\t\t\tnfmr->ea_len = nla_get_u8(c);\n+\n+\t\t\tif ((c = fmrd[IFLA_IPTUN_FMR_OFFSET]))\n+\t\t\t\tnfmr->offset = nla_get_u8(c);\n+\n+\t\t\tnfmr->next = parms->fmrs;\n+\t\t\tparms->fmrs = nfmr;\n+\t\t}\n+\t}\n }\n \n static bool ip6_tnl_netlink_encap_parms(struct nlattr *data[],\n@@ -2101,6 +2320,12 @@ static void ip6_tnl_dellink(struct net_d\n \n static size_t ip6_tnl_get_size(const struct net_device *dev)\n {\n+\tconst struct ip6_tnl *t = netdev_priv(dev);\n+\tstruct __ip6_tnl_fmr *c;\n+\tint fmrs = 0;\n+\tfor (c = t->parms.fmrs; c; c = c->next)\n+\t\t++fmrs;\n+\n \treturn\n \t\t/* IFLA_IPTUN_LINK */\n \t\tnla_total_size(4) +\n@@ -2130,6 +2355,24 @@ static size_t ip6_tnl_get_size(const str\n \t\tnla_total_size(0) +\n \t\t/* IFLA_IPTUN_FWMARK */\n \t\tnla_total_size(4) +\n+\t\t/* IFLA_IPTUN_FMRS */\n+\t\tnla_total_size(0) +\n+\t\t(\n+\t\t\t/* nest */\n+\t\t\tnla_total_size(0) +\n+\t\t\t/* IFLA_IPTUN_FMR_IP6_PREFIX */\n+\t\t\tnla_total_size(sizeof(struct in6_addr)) +\n+\t\t\t/* IFLA_IPTUN_FMR_IP4_PREFIX */\n+\t\t\tnla_total_size(sizeof(struct in_addr)) +\n+\t\t\t/* IFLA_IPTUN_FMR_EA_LEN */\n+\t\t\tnla_total_size(1) +\n+\t\t\t/* IFLA_IPTUN_FMR_IP6_PREFIX_LEN */\n+\t\t\tnla_total_size(1) +\n+\t\t\t/* IFLA_IPTUN_FMR_IP4_PREFIX_LEN */\n+\t\t\tnla_total_size(1) +\n+\t\t\t/* IFLA_IPTUN_FMR_OFFSET */\n+\t\t\tnla_total_size(1)\n+\t\t) * fmrs +\n \t\t0;\n }\n \n@@ -2137,6 +2380,9 @@ static int ip6_tnl_fill_info(struct sk_b\n {\n \tstruct ip6_tnl *tunnel = netdev_priv(dev);\n \tstruct __ip6_tnl_parm *parm = &tunnel->parms;\n+\tstruct __ip6_tnl_fmr *c;\n+\tint fmrcnt = 0;\n+\tstruct nlattr *fmrs;\n \n \tif (nla_put_u32(skb, IFLA_IPTUN_LINK, parm->link) ||\n \t    nla_put_in6_addr(skb, IFLA_IPTUN_LOCAL, &parm->laddr) ||\n@@ -2146,9 +2392,27 @@ static int ip6_tnl_fill_info(struct sk_b\n \t    nla_put_be32(skb, IFLA_IPTUN_FLOWINFO, parm->flowinfo) ||\n \t    nla_put_u32(skb, IFLA_IPTUN_FLAGS, parm->flags) ||\n \t    nla_put_u8(skb, IFLA_IPTUN_PROTO, parm->proto) ||\n-\t    nla_put_u32(skb, IFLA_IPTUN_FWMARK, parm->fwmark))\n+\t    nla_put_u32(skb, IFLA_IPTUN_FWMARK, parm->fwmark) ||\n+\t    !(fmrs = nla_nest_start(skb, IFLA_IPTUN_FMRS)))\n \t\tgoto nla_put_failure;\n \n+\tfor (c = parm->fmrs; c; c = c->next) {\n+\t\tstruct nlattr *fmr = nla_nest_start(skb, ++fmrcnt);\n+\t\tif (!fmr ||\n+\t\t\tnla_put(skb, IFLA_IPTUN_FMR_IP6_PREFIX,\n+\t\t\t\tsizeof(c->ip6_prefix), &c->ip6_prefix) ||\n+\t\t\tnla_put(skb, IFLA_IPTUN_FMR_IP4_PREFIX,\n+\t\t\t\tsizeof(c->ip4_prefix), &c->ip4_prefix) ||\n+\t\t\tnla_put_u8(skb, IFLA_IPTUN_FMR_IP6_PREFIX_LEN, c->ip6_prefix_len) ||\n+\t\t\tnla_put_u8(skb, IFLA_IPTUN_FMR_IP4_PREFIX_LEN, c->ip4_prefix_len) ||\n+\t\t\tnla_put_u8(skb, IFLA_IPTUN_FMR_EA_LEN, c->ea_len) ||\n+\t\t\tnla_put_u8(skb, IFLA_IPTUN_FMR_OFFSET, c->offset))\n+\t\t\t\tgoto nla_put_failure;\n+\n+\t\tnla_nest_end(skb, fmr);\n+\t}\n+\tnla_nest_end(skb, fmrs);\n+\n \tif (nla_put_u16(skb, IFLA_IPTUN_ENCAP_TYPE, tunnel->encap.type) ||\n \t    nla_put_be16(skb, IFLA_IPTUN_ENCAP_SPORT, tunnel->encap.sport) ||\n \t    nla_put_be16(skb, IFLA_IPTUN_ENCAP_DPORT, tunnel->encap.dport) ||\n@@ -2188,6 +2452,7 @@ static const struct nla_policy ip6_tnl_p\n \t[IFLA_IPTUN_ENCAP_DPORT]\t= { .type = NLA_U16 },\n \t[IFLA_IPTUN_COLLECT_METADATA]\t= { .type = NLA_FLAG },\n \t[IFLA_IPTUN_FWMARK]\t\t= { .type = NLA_U32 },\n+\t[IFLA_IPTUN_FMRS]\t\t= { .type = NLA_NESTED },\n };\n \n static struct rtnl_link_ops ip6_link_ops __read_mostly = {\n"
  },
  {
    "path": "target/linux/generic/pending-5.15/670-ipv6-allow-rejecting-with-source-address-failed-policy.patch",
    "content": "From: Jonas Gorski <jogo@openwrt.org>\nSubject: ipv6: allow rejecting with \"source address failed policy\"\n\nRFC6204 L-14 requires rejecting traffic from invalid addresses with\nICMPv6 Destination Unreachable, Code 5 (Source address failed ingress/\negress policy) on the LAN side, so add an appropriate rule for that.\n\nSigned-off-by: Jonas Gorski <jogo@openwrt.org>\n---\n include/net/netns/ipv6.h       |  1 +\n include/uapi/linux/fib_rules.h |  4 +++\n include/uapi/linux/rtnetlink.h |  1 +\n net/ipv4/fib_semantics.c       |  4 +++\n net/ipv4/fib_trie.c            |  1 +\n net/ipv4/ipmr.c                |  1 +\n net/ipv6/fib6_rules.c          |  4 +++\n net/ipv6/ip6mr.c               |  2 ++\n net/ipv6/route.c               | 58 +++++++++++++++++++++++++++++++++++++++++-\n 9 files changed, 75 insertions(+), 1 deletion(-)\n\n--- a/include/net/netns/ipv6.h\n+++ b/include/net/netns/ipv6.h\n@@ -85,6 +85,7 @@ struct netns_ipv6 {\n \tunsigned int\t\tfib6_routes_require_src;\n #endif\n \tstruct rt6_info         *ip6_prohibit_entry;\n+\tstruct rt6_info\t\t*ip6_policy_failed_entry;\n \tstruct rt6_info         *ip6_blk_hole_entry;\n \tstruct fib6_table       *fib6_local_tbl;\n \tstruct fib_rules_ops    *fib6_rules_ops;\n--- a/include/uapi/linux/fib_rules.h\n+++ b/include/uapi/linux/fib_rules.h\n@@ -82,6 +82,10 @@ enum {\n \tFR_ACT_BLACKHOLE,\t/* Drop without notification */\n \tFR_ACT_UNREACHABLE,\t/* Drop with ENETUNREACH */\n \tFR_ACT_PROHIBIT,\t/* Drop with EACCES */\n+\tFR_ACT_RES9,\n+\tFR_ACT_RES10,\n+\tFR_ACT_RES11,\n+\tFR_ACT_POLICY_FAILED,\t/* Drop with EACCES */\n \t__FR_ACT_MAX,\n };\n \n--- a/include/uapi/linux/rtnetlink.h\n+++ b/include/uapi/linux/rtnetlink.h\n@@ -256,6 +256,7 @@ enum {\n \tRTN_THROW,\t\t/* Not in this table\t\t*/\n \tRTN_NAT,\t\t/* Translate this address\t*/\n \tRTN_XRESOLVE,\t\t/* Use external resolver\t*/\n+\tRTN_POLICY_FAILED,\t/* Failed ingress/egress policy */\n \t__RTN_MAX\n };\n \n--- a/net/ipv4/fib_semantics.c\n+++ b/net/ipv4/fib_semantics.c\n@@ -142,6 +142,10 @@ const struct fib_prop fib_props[RTN_MAX\n \t\t.error\t= -EINVAL,\n \t\t.scope\t= RT_SCOPE_NOWHERE,\n \t},\n+\t[RTN_POLICY_FAILED] = {\n+\t\t.error\t= -EACCES,\n+\t\t.scope\t= RT_SCOPE_UNIVERSE,\n+\t},\n };\n \n static void rt_fibinfo_free(struct rtable __rcu **rtp)\n--- a/net/ipv4/fib_trie.c\n+++ b/net/ipv4/fib_trie.c\n@@ -2767,6 +2767,7 @@ static const char *const rtn_type_names[\n \t[RTN_THROW] = \"THROW\",\n \t[RTN_NAT] = \"NAT\",\n \t[RTN_XRESOLVE] = \"XRESOLVE\",\n+\t[RTN_POLICY_FAILED] = \"POLICY_FAILED\",\n };\n \n static inline const char *rtn_type(char *buf, size_t len, unsigned int t)\n--- a/net/ipv4/ipmr.c\n+++ b/net/ipv4/ipmr.c\n@@ -175,6 +175,7 @@ static int ipmr_rule_action(struct fib_r\n \tcase FR_ACT_UNREACHABLE:\n \t\treturn -ENETUNREACH;\n \tcase FR_ACT_PROHIBIT:\n+\tcase FR_ACT_POLICY_FAILED:\n \t\treturn -EACCES;\n \tcase FR_ACT_BLACKHOLE:\n \tdefault:\n--- a/net/ipv6/fib6_rules.c\n+++ b/net/ipv6/fib6_rules.c\n@@ -220,6 +220,10 @@ static int __fib6_rule_action(struct fib\n \t\terr = -EACCES;\n \t\trt = net->ipv6.ip6_prohibit_entry;\n \t\tgoto discard_pkt;\n+\tcase FR_ACT_POLICY_FAILED:\n+\t\terr = -EACCES;\n+\t\trt = net->ipv6.ip6_policy_failed_entry;\n+\t\tgoto discard_pkt;\n \t}\n \n \ttb_id = fib_rule_get_table(rule, arg);\n--- a/net/ipv6/ip6mr.c\n+++ b/net/ipv6/ip6mr.c\n@@ -163,6 +163,8 @@ static int ip6mr_rule_action(struct fib_\n \t\treturn -ENETUNREACH;\n \tcase FR_ACT_PROHIBIT:\n \t\treturn -EACCES;\n+\tcase FR_ACT_POLICY_FAILED:\n+\t\treturn -EACCES;\n \tcase FR_ACT_BLACKHOLE:\n \tdefault:\n \t\treturn -EINVAL;\n--- a/net/ipv6/route.c\n+++ b/net/ipv6/route.c\n@@ -97,6 +97,8 @@ static int\t\tip6_pkt_discard(struct sk_bu\n static int\t\tip6_pkt_discard_out(struct net *net, struct sock *sk, struct sk_buff *skb);\n static int\t\tip6_pkt_prohibit(struct sk_buff *skb);\n static int\t\tip6_pkt_prohibit_out(struct net *net, struct sock *sk, struct sk_buff *skb);\n+static int\t\tip6_pkt_policy_failed(struct sk_buff *skb);\n+static int\t\tip6_pkt_policy_failed_out(struct net *net, struct sock *sk, struct sk_buff *skb);\n static void\t\tip6_link_failure(struct sk_buff *skb);\n static void\t\tip6_rt_update_pmtu(struct dst_entry *dst, struct sock *sk,\n \t\t\t\t\t   struct sk_buff *skb, u32 mtu,\n@@ -312,6 +314,18 @@ static const struct rt6_info ip6_prohibi\n \t.rt6i_flags\t= (RTF_REJECT | RTF_NONEXTHOP),\n };\n \n+static const struct rt6_info ip6_policy_failed_entry_template = {\n+\t.dst = {\n+\t\t.__refcnt\t= ATOMIC_INIT(1),\n+\t\t.__use\t\t= 1,\n+\t\t.obsolete\t= DST_OBSOLETE_FORCE_CHK,\n+\t\t.error\t\t= -EACCES,\n+\t\t.input\t\t= ip6_pkt_policy_failed,\n+\t\t.output\t\t= ip6_pkt_policy_failed_out,\n+\t},\n+\t.rt6i_flags\t= (RTF_REJECT | RTF_NONEXTHOP),\n+};\n+\n static const struct rt6_info ip6_blk_hole_entry_template = {\n \t.dst = {\n \t\t.__refcnt\t= ATOMIC_INIT(1),\n@@ -1033,6 +1047,7 @@ static const int fib6_prop[RTN_MAX + 1]\n \t[RTN_BLACKHOLE]\t= -EINVAL,\n \t[RTN_UNREACHABLE] = -EHOSTUNREACH,\n \t[RTN_PROHIBIT]\t= -EACCES,\n+\t[RTN_POLICY_FAILED] = -EACCES,\n \t[RTN_THROW]\t= -EAGAIN,\n \t[RTN_NAT]\t= -EINVAL,\n \t[RTN_XRESOLVE]\t= -EINVAL,\n@@ -1068,6 +1083,10 @@ static void ip6_rt_init_dst_reject(struc\n \t\trt->dst.output = ip6_pkt_prohibit_out;\n \t\trt->dst.input = ip6_pkt_prohibit;\n \t\tbreak;\n+\tcase RTN_POLICY_FAILED:\n+\t\trt->dst.output = ip6_pkt_policy_failed_out;\n+\t\trt->dst.input = ip6_pkt_policy_failed;\n+\t\tbreak;\n \tcase RTN_THROW:\n \tcase RTN_UNREACHABLE:\n \tdefault:\n@@ -4560,6 +4579,17 @@ static int ip6_pkt_prohibit_out(struct n\n \treturn ip6_pkt_drop(skb, ICMPV6_ADM_PROHIBITED, IPSTATS_MIB_OUTNOROUTES);\n }\n \n+static int ip6_pkt_policy_failed(struct sk_buff *skb)\n+{\n+\treturn ip6_pkt_drop(skb, ICMPV6_POLICY_FAIL, IPSTATS_MIB_INNOROUTES);\n+}\n+\n+static int ip6_pkt_policy_failed_out(struct net *net, struct sock *sk, struct sk_buff *skb)\n+{\n+\tskb->dev = skb_dst(skb)->dev;\n+\treturn ip6_pkt_drop(skb, ICMPV6_POLICY_FAIL, IPSTATS_MIB_OUTNOROUTES);\n+}\n+\n /*\n  *\tAllocate a dst for local (unicast / anycast) address.\n  */\n@@ -5040,7 +5070,8 @@ static int rtm_to_fib6_config(struct sk_\n \tif (rtm->rtm_type == RTN_UNREACHABLE ||\n \t    rtm->rtm_type == RTN_BLACKHOLE ||\n \t    rtm->rtm_type == RTN_PROHIBIT ||\n-\t    rtm->rtm_type == RTN_THROW)\n+\t    rtm->rtm_type == RTN_THROW ||\n+\t    rtm->rtm_type == RTN_POLICY_FAILED)\n \t\tcfg->fc_flags |= RTF_REJECT;\n \n \tif (rtm->rtm_type == RTN_LOCAL)\n@@ -6293,6 +6324,8 @@ static int ip6_route_dev_notify(struct n\n #ifdef CONFIG_IPV6_MULTIPLE_TABLES\n \t\tnet->ipv6.ip6_prohibit_entry->dst.dev = dev;\n \t\tnet->ipv6.ip6_prohibit_entry->rt6i_idev = in6_dev_get(dev);\n+\t\tnet->ipv6.ip6_policy_failed_entry->dst.dev = dev;\n+\t\tnet->ipv6.ip6_policy_failed_entry->rt6i_idev = in6_dev_get(dev);\n \t\tnet->ipv6.ip6_blk_hole_entry->dst.dev = dev;\n \t\tnet->ipv6.ip6_blk_hole_entry->rt6i_idev = in6_dev_get(dev);\n #endif\n@@ -6304,6 +6337,7 @@ static int ip6_route_dev_notify(struct n\n \t\tin6_dev_put_clear(&net->ipv6.ip6_null_entry->rt6i_idev);\n #ifdef CONFIG_IPV6_MULTIPLE_TABLES\n \t\tin6_dev_put_clear(&net->ipv6.ip6_prohibit_entry->rt6i_idev);\n+\t\tin6_dev_put_clear(&net->ipv6.ip6_policy_failed_entry->rt6i_idev);\n \t\tin6_dev_put_clear(&net->ipv6.ip6_blk_hole_entry->rt6i_idev);\n #endif\n \t}\n@@ -6495,6 +6529,8 @@ static int __net_init ip6_route_net_init\n \n #ifdef CONFIG_IPV6_MULTIPLE_TABLES\n \tnet->ipv6.fib6_has_custom_rules = false;\n+\n+\n \tnet->ipv6.ip6_prohibit_entry = kmemdup(&ip6_prohibit_entry_template,\n \t\t\t\t\t       sizeof(*net->ipv6.ip6_prohibit_entry),\n \t\t\t\t\t       GFP_KERNEL);\n@@ -6505,11 +6541,21 @@ static int __net_init ip6_route_net_init\n \t\t\t ip6_template_metrics, true);\n \tINIT_LIST_HEAD(&net->ipv6.ip6_prohibit_entry->rt6i_uncached);\n \n+\tnet->ipv6.ip6_policy_failed_entry =\n+\t\t\t\tkmemdup(&ip6_policy_failed_entry_template,\n+\t\t\t\tsizeof(*net->ipv6.ip6_policy_failed_entry), GFP_KERNEL);\n+\tif (!net->ipv6.ip6_policy_failed_entry)\n+\t\tgoto out_ip6_prohibit_entry;\n+\tnet->ipv6.ip6_policy_failed_entry->dst.ops = &net->ipv6.ip6_dst_ops;\n+\tdst_init_metrics(&net->ipv6.ip6_policy_failed_entry->dst,\n+\t\t\t ip6_template_metrics, true);\n+\tINIT_LIST_HEAD(&net->ipv6.ip6_policy_failed_entry->rt6i_uncached);\n+\n \tnet->ipv6.ip6_blk_hole_entry = kmemdup(&ip6_blk_hole_entry_template,\n \t\t\t\t\t       sizeof(*net->ipv6.ip6_blk_hole_entry),\n \t\t\t\t\t       GFP_KERNEL);\n \tif (!net->ipv6.ip6_blk_hole_entry)\n-\t\tgoto out_ip6_prohibit_entry;\n+\t\tgoto out_ip6_policy_failed_entry;\n \tnet->ipv6.ip6_blk_hole_entry->dst.ops = &net->ipv6.ip6_dst_ops;\n \tdst_init_metrics(&net->ipv6.ip6_blk_hole_entry->dst,\n \t\t\t ip6_template_metrics, true);\n@@ -6536,6 +6582,8 @@ out:\n \treturn ret;\n \n #ifdef CONFIG_IPV6_MULTIPLE_TABLES\n+out_ip6_policy_failed_entry:\n+\tkfree(net->ipv6.ip6_policy_failed_entry);\n out_ip6_prohibit_entry:\n \tkfree(net->ipv6.ip6_prohibit_entry);\n out_ip6_null_entry:\n@@ -6555,6 +6603,7 @@ static void __net_exit ip6_route_net_exi\n \tkfree(net->ipv6.ip6_null_entry);\n #ifdef CONFIG_IPV6_MULTIPLE_TABLES\n \tkfree(net->ipv6.ip6_prohibit_entry);\n+\tkfree(net->ipv6.ip6_policy_failed_entry);\n \tkfree(net->ipv6.ip6_blk_hole_entry);\n #endif\n \tdst_entries_destroy(&net->ipv6.ip6_dst_ops);\n@@ -6632,6 +6681,9 @@ void __init ip6_route_init_special_entri\n \tinit_net.ipv6.ip6_prohibit_entry->rt6i_idev = in6_dev_get(init_net.loopback_dev);\n \tinit_net.ipv6.ip6_blk_hole_entry->dst.dev = init_net.loopback_dev;\n \tinit_net.ipv6.ip6_blk_hole_entry->rt6i_idev = in6_dev_get(init_net.loopback_dev);\n+\tinit_net.ipv6.ip6_policy_failed_entry->dst.dev = init_net.loopback_dev;\n+\tinit_net.ipv6.ip6_policy_failed_entry->rt6i_idev =\n+\t\tin6_dev_get(init_net.loopback_dev);\n   #endif\n }\n \n"
  },
  {
    "path": "target/linux/generic/pending-5.15/671-net-provide-defines-for-_POLICY_FAILED-until-all-cod.patch",
    "content": "From: Jonas Gorski <jogo@openwrt.org>\nSubject: net: provide defines for _POLICY_FAILED until all code is updated\n\nUpstream introduced ICMPV6_POLICY_FAIL for code 5 of destination\nunreachable, conflicting with our name.\n\nAdd appropriate defines to allow our code to build with the new\nname until we have updated our local patches for older kernels\nand userspace packages.\n\nSigned-off-by: Jonas Gorski <jogo@openwrt.org>\n---\n include/uapi/linux/fib_rules.h | 2 ++\n include/uapi/linux/icmpv6.h    | 2 ++\n include/uapi/linux/rtnetlink.h | 2 ++\n 3 files changed, 6 insertions(+)\n\n--- a/include/uapi/linux/fib_rules.h\n+++ b/include/uapi/linux/fib_rules.h\n@@ -89,6 +89,8 @@ enum {\n \t__FR_ACT_MAX,\n };\n \n+#define FR_ACT_FAILED_POLICY FR_ACT_POLICY_FAILED\n+\n #define FR_ACT_MAX (__FR_ACT_MAX - 1)\n \n #endif\n--- a/include/uapi/linux/icmpv6.h\n+++ b/include/uapi/linux/icmpv6.h\n@@ -126,6 +126,8 @@ struct icmp6hdr {\n #define ICMPV6_POLICY_FAIL\t\t5\n #define ICMPV6_REJECT_ROUTE\t\t6\n \n+#define ICMPV6_FAILED_POLICY\t\tICMPV6_POLICY_FAIL\n+\n /*\n  *\tCodes for Time Exceeded\n  */\n--- a/include/uapi/linux/rtnetlink.h\n+++ b/include/uapi/linux/rtnetlink.h\n@@ -260,6 +260,8 @@ enum {\n \t__RTN_MAX\n };\n \n+#define RTN_FAILED_POLICY RTN_POLICY_FAILED\n+\n #define RTN_MAX (__RTN_MAX - 1)\n \n \n"
  },
  {
    "path": "target/linux/generic/pending-5.15/680-NET-skip-GRO-for-foreign-MAC-addresses.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nSubject: net: replace GRO optimization patch with a new one that supports VLANs/bridges with different MAC addresses\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n include/linux/netdevice.h |  2 ++\n include/linux/skbuff.h    |  3 ++-\n net/core/dev.c            | 48 +++++++++++++++++++++++++++++++++++++++++++++++\n net/ethernet/eth.c        | 18 +++++++++++++++++-\n 4 files changed, 69 insertions(+), 2 deletions(-)\n\n--- a/include/linux/netdevice.h\n+++ b/include/linux/netdevice.h\n@@ -2068,6 +2068,8 @@ struct net_device {\n \tstruct netdev_hw_addr_list\tmc;\n \tstruct netdev_hw_addr_list\tdev_addrs;\n \n+\tunsigned char\t\tlocal_addr_mask[MAX_ADDR_LEN];\n+\n #ifdef CONFIG_SYSFS\n \tstruct kset\t\t*queues_kset;\n #endif\n--- a/include/linux/skbuff.h\n+++ b/include/linux/skbuff.h\n@@ -855,6 +855,7 @@ struct sk_buff {\n #ifdef CONFIG_IPV6_NDISC_NODETYPE\n \t__u8\t\t\tndisc_nodetype:2;\n #endif\n+\t__u8\t\t\tgro_skip:1;\n \n \t__u8\t\t\tipvs_property:1;\n \t__u8\t\t\tinner_protocol_type:1;\n--- a/net/core/dev.c\n+++ b/net/core/dev.c\n@@ -6051,6 +6051,9 @@ static enum gro_result dev_gro_receive(s\n \tint same_flow;\n \tint grow;\n \n+\tif (skb->gro_skip)\n+\t\tgoto normal;\n+\n \tif (netif_elide_gro(skb->dev))\n \t\tgoto normal;\n \n@@ -8065,6 +8068,48 @@ static void __netdev_adjacent_dev_unlink\n \t\t\t\t\t   &upper_dev->adj_list.lower);\n }\n \n+static void __netdev_addr_mask(unsigned char *mask, const unsigned char *addr,\n+\t\t\t       struct net_device *dev)\n+{\n+\tint i;\n+\n+\tfor (i = 0; i < dev->addr_len; i++)\n+\t\tmask[i] |= addr[i] ^ dev->dev_addr[i];\n+}\n+\n+static void __netdev_upper_mask(unsigned char *mask, struct net_device *dev,\n+\t\t\t\tstruct net_device *lower)\n+{\n+\tstruct net_device *cur;\n+\tstruct list_head *iter;\n+\n+\tnetdev_for_each_upper_dev_rcu(dev, cur, iter) {\n+\t\t__netdev_addr_mask(mask, cur->dev_addr, lower);\n+\t\t__netdev_upper_mask(mask, cur, lower);\n+\t}\n+}\n+\n+static void __netdev_update_addr_mask(struct net_device *dev)\n+{\n+\tunsigned char mask[MAX_ADDR_LEN];\n+\tstruct net_device *cur;\n+\tstruct list_head *iter;\n+\n+\tmemset(mask, 0, sizeof(mask));\n+\t__netdev_upper_mask(mask, dev, dev);\n+\tmemcpy(dev->local_addr_mask, mask, dev->addr_len);\n+\n+\tnetdev_for_each_lower_dev(dev, cur, iter)\n+\t\t__netdev_update_addr_mask(cur);\n+}\n+\n+static void netdev_update_addr_mask(struct net_device *dev)\n+{\n+\trcu_read_lock();\n+\t__netdev_update_addr_mask(dev);\n+\trcu_read_unlock();\n+}\n+\n static int __netdev_upper_dev_link(struct net_device *dev,\n \t\t\t\t   struct net_device *upper_dev, bool master,\n \t\t\t\t   void *upper_priv, void *upper_info,\n@@ -8116,6 +8161,7 @@ static int __netdev_upper_dev_link(struc\n \tif (ret)\n \t\treturn ret;\n \n+\tnetdev_update_addr_mask(dev);\n \tret = call_netdevice_notifiers_info(NETDEV_CHANGEUPPER,\n \t\t\t\t\t    &changeupper_info.info);\n \tret = notifier_to_errno(ret);\n@@ -8212,6 +8258,7 @@ static void __netdev_upper_dev_unlink(st\n \n \t__netdev_adjacent_dev_unlink_neighbour(dev, upper_dev);\n \n+\tnetdev_update_addr_mask(dev);\n \tcall_netdevice_notifiers_info(NETDEV_CHANGEUPPER,\n \t\t\t\t      &changeupper_info.info);\n \n@@ -9031,6 +9078,7 @@ int dev_set_mac_address(struct net_devic\n \tif (err)\n \t\treturn err;\n \tdev->addr_assign_type = NET_ADDR_SET;\n+\tnetdev_update_addr_mask(dev);\n \tcall_netdevice_notifiers(NETDEV_CHANGEADDR, dev);\n \tadd_device_randomness(dev->dev_addr, dev->addr_len);\n \treturn 0;\n--- a/net/ethernet/eth.c\n+++ b/net/ethernet/eth.c\n@@ -142,6 +142,18 @@ u32 eth_get_headlen(const struct net_dev\n }\n EXPORT_SYMBOL(eth_get_headlen);\n \n+static inline bool\n+eth_check_local_mask(const void *addr1, const void *addr2, const void *mask)\n+{\n+\tconst u16 *a1 = addr1;\n+\tconst u16 *a2 = addr2;\n+\tconst u16 *m = mask;\n+\n+\treturn (((a1[0] ^ a2[0]) & ~m[0]) |\n+\t\t((a1[1] ^ a2[1]) & ~m[1]) |\n+\t\t((a1[2] ^ a2[2]) & ~m[2]));\n+}\n+\n /**\n  * eth_type_trans - determine the packet's protocol ID.\n  * @skb: received socket data\n@@ -173,6 +185,10 @@ __be16 eth_type_trans(struct sk_buff *sk\n \t\t} else {\n \t\t\tskb->pkt_type = PACKET_OTHERHOST;\n \t\t}\n+\n+\t\tif (eth_check_local_mask(eth->h_dest, dev->dev_addr,\n+\t\t\t\t\t dev->local_addr_mask))\n+\t\t\tskb->gro_skip = 1;\n \t}\n \n \t/*\n"
  },
  {
    "path": "target/linux/generic/pending-5.15/682-of_net-add-mac-address-increment-support.patch",
    "content": "From 844c273286f328acf0dab5fbd5d864366b4904dc Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Tue, 30 Mar 2021 18:21:14 +0200\nSubject: [PATCH] of_net: add mac-address-increment support\n\nLots of embedded devices use the mac-address of other interface\nextracted from nvmem cells and increments it by one or two. Add two\nbindings to integrate this and directly use the right mac-address for\nthe interface. Some example are some routers that use the gmac\nmac-address stored in the art partition and increments it by one for the\nwifi. mac-address-increment-byte bindings is used to tell what byte of\nthe mac-address has to be increased (if not defined the last byte is\nincreased) and mac-address-increment tells how much the byte decided\nearly has to be increased.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\n---\n net/core/of_net.c | 43 +++++++++++++++++++++++++++++++++++++++----\n 1 file changed, 39 insertions(+), 4 deletions(-)\n\n--- a/net/core/of_net.c\n+++ b/net/core/of_net.c\n@@ -119,27 +119,62 @@ static int of_get_mac_addr_nvmem(struct\n  * this case, the real MAC is in 'local-mac-address', and 'mac-address' exists\n  * but is all zeros.\n  *\n+ * DT can tell the system to increment the mac-address after is extracted by\n+ * using:\n+ * - mac-address-increment-byte to decide what byte to increase\n+ *   (if not defined is increased the last byte)\n+ * - mac-address-increment to decide how much to increase. The value WILL\n+ *   overflow to other bytes if the increment is over 255 or the total\n+ *   increment will exceed 255 of the current byte.\n+ *   (example 00:01:02:03:04:ff + 1 == 00:01:02:03:05:00)\n+ *   (example 00:01:02:03:04:fe + 5 == 00:01:02:03:05:03)\n+ *\n  * Return: 0 on success and errno in case of error.\n */\n int of_get_mac_address(struct device_node *np, u8 *addr)\n {\n+\tu32 inc_idx, mac_inc, mac_val;\n \tint ret;\n \n+\t/* Check first if the increment byte is present and valid.\n+\t * If not set assume to increment the last byte if found.\n+\t */\n+\tif (of_property_read_u32(np, \"mac-address-increment-byte\", &inc_idx))\n+\t\tinc_idx = 5;\n+\tif (inc_idx < 3 || inc_idx > 5)\n+\t\treturn -EINVAL;\n+\n \tif (!np)\n \t\treturn -ENODEV;\n \n \tret = of_get_mac_addr(np, \"mac-address\", addr);\n \tif (!ret)\n-\t\treturn 0;\n+\t\tgoto found;\n \n \tret = of_get_mac_addr(np, \"local-mac-address\", addr);\n \tif (!ret)\n-\t\treturn 0;\n+\t\tgoto found;\n \n \tret = of_get_mac_addr(np, \"address\", addr);\n \tif (!ret)\n-\t\treturn 0;\n+\t\tgoto found;\n+\n+\tret = of_get_mac_addr_nvmem(np, addr);\n+\tif (ret)\n+\t\treturn ret;\n+\n+found:\n+\tif (!of_property_read_u32(np, \"mac-address-increment\", &mac_inc)) {\n+\t\t/* Convert to a contiguous value */\n+\t\tmac_val = (addr[3] << 16) + (addr[4] << 8) + addr[5];\n+\t\tmac_val += mac_inc << 8 * (5-inc_idx);\n+\n+\t\t/* Apply the incremented value handling overflow case */\n+\t\taddr[3] = (mac_val >> 16) & 0xff;\n+\t\taddr[4] = (mac_val >> 8) & 0xff;\n+\t\taddr[5] = (mac_val >> 0) & 0xff;\n+\t}\n \n-\treturn of_get_mac_addr_nvmem(np, addr);\n+\treturn ret;\n }\n EXPORT_SYMBOL(of_get_mac_address);\n"
  },
  {
    "path": "target/linux/generic/pending-5.15/683-of_net-add-mac-address-to-of-tree.patch",
    "content": "--- a/net/core/of_net.c\n+++ b/net/core/of_net.c\n@@ -95,6 +95,27 @@ static int of_get_mac_addr_nvmem(struct\n \treturn 0;\n }\n \n+static int of_add_mac_address(struct device_node *np, u8* addr)\n+{\n+\tstruct property *prop;\n+\n+\tprop = kzalloc(sizeof(*prop), GFP_KERNEL);\n+\tif (!prop)\n+\t\treturn -ENOMEM;\n+\n+\tprop->name = \"mac-address\";\n+\tprop->length = ETH_ALEN;\n+\tprop->value = kmemdup(addr, ETH_ALEN, GFP_KERNEL);\n+\tif (!prop->value || of_update_property(np, prop))\n+\t\tgoto free;\n+\n+\treturn 0;\n+free:\n+\tkfree(prop->value);\n+\tkfree(prop);\n+\treturn -ENOMEM;\n+}\n+\n /**\n  * of_get_mac_address()\n  * @np:\t\tCaller's Device Node\n@@ -175,6 +196,7 @@ found:\n \t\taddr[5] = (mac_val >> 0) & 0xff;\n \t}\n \n+\tof_add_mac_address(np, addr);\n \treturn ret;\n }\n EXPORT_SYMBOL(of_get_mac_address);\n"
  },
  {
    "path": "target/linux/generic/pending-5.15/701-00-net-ethernet-mtk_eth_soc-add-support-for-coherent-DM.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nDate: Sat, 5 Feb 2022 17:59:07 +0100\nSubject: [PATCH] net: ethernet: mtk_eth_soc: add support for coherent\n DMA\n\nIt improves performance by eliminating the need for a cache flush on rx and tx\nIn preparation for supporting WED (Wireless Ethernet Dispatch), also add a\nfunction for disabling coherent DMA at runtime.\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n\n--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c\n+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c\n@@ -9,6 +9,7 @@\n #include <linux/of_device.h>\n #include <linux/of_mdio.h>\n #include <linux/of_net.h>\n+#include <linux/of_address.h>\n #include <linux/mfd/syscon.h>\n #include <linux/regmap.h>\n #include <linux/clk.h>\n@@ -828,7 +829,7 @@ static int mtk_init_fq_dma(struct mtk_et\n \tdma_addr_t dma_addr;\n \tint i;\n \n-\teth->scratch_ring = dma_alloc_coherent(eth->dev,\n+\teth->scratch_ring = dma_alloc_coherent(eth->dma_dev,\n \t\t\t\t\t       cnt * sizeof(struct mtk_tx_dma),\n \t\t\t\t\t       &eth->phy_scratch_ring,\n \t\t\t\t\t       GFP_ATOMIC);\n@@ -840,10 +841,10 @@ static int mtk_init_fq_dma(struct mtk_et\n \tif (unlikely(!eth->scratch_head))\n \t\treturn -ENOMEM;\n \n-\tdma_addr = dma_map_single(eth->dev,\n+\tdma_addr = dma_map_single(eth->dma_dev,\n \t\t\t\t  eth->scratch_head, cnt * MTK_QDMA_PAGE_SIZE,\n \t\t\t\t  DMA_FROM_DEVICE);\n-\tif (unlikely(dma_mapping_error(eth->dev, dma_addr)))\n+\tif (unlikely(dma_mapping_error(eth->dma_dev, dma_addr)))\n \t\treturn -ENOMEM;\n \n \tphy_ring_tail = eth->phy_scratch_ring +\n@@ -897,26 +898,26 @@ static void mtk_tx_unmap(struct mtk_eth\n {\n \tif (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {\n \t\tif (tx_buf->flags & MTK_TX_FLAGS_SINGLE0) {\n-\t\t\tdma_unmap_single(eth->dev,\n+\t\t\tdma_unmap_single(eth->dma_dev,\n \t\t\t\t\t dma_unmap_addr(tx_buf, dma_addr0),\n \t\t\t\t\t dma_unmap_len(tx_buf, dma_len0),\n \t\t\t\t\t DMA_TO_DEVICE);\n \t\t} else if (tx_buf->flags & MTK_TX_FLAGS_PAGE0) {\n-\t\t\tdma_unmap_page(eth->dev,\n+\t\t\tdma_unmap_page(eth->dma_dev,\n \t\t\t\t       dma_unmap_addr(tx_buf, dma_addr0),\n \t\t\t\t       dma_unmap_len(tx_buf, dma_len0),\n \t\t\t\t       DMA_TO_DEVICE);\n \t\t}\n \t} else {\n \t\tif (dma_unmap_len(tx_buf, dma_len0)) {\n-\t\t\tdma_unmap_page(eth->dev,\n+\t\t\tdma_unmap_page(eth->dma_dev,\n \t\t\t\t       dma_unmap_addr(tx_buf, dma_addr0),\n \t\t\t\t       dma_unmap_len(tx_buf, dma_len0),\n \t\t\t\t       DMA_TO_DEVICE);\n \t\t}\n \n \t\tif (dma_unmap_len(tx_buf, dma_len1)) {\n-\t\t\tdma_unmap_page(eth->dev,\n+\t\t\tdma_unmap_page(eth->dma_dev,\n \t\t\t\t       dma_unmap_addr(tx_buf, dma_addr1),\n \t\t\t\t       dma_unmap_len(tx_buf, dma_len1),\n \t\t\t\t       DMA_TO_DEVICE);\n@@ -994,9 +995,9 @@ static int mtk_tx_map(struct sk_buff *sk\n \tif (skb_vlan_tag_present(skb))\n \t\ttxd4 |= TX_DMA_INS_VLAN | skb_vlan_tag_get(skb);\n \n-\tmapped_addr = dma_map_single(eth->dev, skb->data,\n+\tmapped_addr = dma_map_single(eth->dma_dev, skb->data,\n \t\t\t\t     skb_headlen(skb), DMA_TO_DEVICE);\n-\tif (unlikely(dma_mapping_error(eth->dev, mapped_addr)))\n+\tif (unlikely(dma_mapping_error(eth->dma_dev, mapped_addr)))\n \t\treturn -ENOMEM;\n \n \tWRITE_ONCE(itxd->txd1, mapped_addr);\n@@ -1035,10 +1036,10 @@ static int mtk_tx_map(struct sk_buff *sk\n \n \n \t\t\tfrag_map_size = min(frag_size, MTK_TX_DMA_BUF_LEN);\n-\t\t\tmapped_addr = skb_frag_dma_map(eth->dev, frag, offset,\n+\t\t\tmapped_addr = skb_frag_dma_map(eth->dma_dev, frag, offset,\n \t\t\t\t\t\t       frag_map_size,\n \t\t\t\t\t\t       DMA_TO_DEVICE);\n-\t\t\tif (unlikely(dma_mapping_error(eth->dev, mapped_addr)))\n+\t\t\tif (unlikely(dma_mapping_error(eth->dma_dev, mapped_addr)))\n \t\t\t\tgoto err_dma;\n \n \t\t\tif (i == nr_frags - 1 &&\n@@ -1316,18 +1317,18 @@ static int mtk_poll_rx(struct napi_struc\n \t\t\tnetdev->stats.rx_dropped++;\n \t\t\tgoto release_desc;\n \t\t}\n-\t\tdma_addr = dma_map_single(eth->dev,\n+\t\tdma_addr = dma_map_single(eth->dma_dev,\n \t\t\t\t\t  new_data + NET_SKB_PAD +\n \t\t\t\t\t  eth->ip_align,\n \t\t\t\t\t  ring->buf_size,\n \t\t\t\t\t  DMA_FROM_DEVICE);\n-\t\tif (unlikely(dma_mapping_error(eth->dev, dma_addr))) {\n+\t\tif (unlikely(dma_mapping_error(eth->dma_dev, dma_addr))) {\n \t\t\tskb_free_frag(new_data);\n \t\t\tnetdev->stats.rx_dropped++;\n \t\t\tgoto release_desc;\n \t\t}\n \n-\t\tdma_unmap_single(eth->dev, trxd.rxd1,\n+\t\tdma_unmap_single(eth->dma_dev, trxd.rxd1,\n \t\t\t\t ring->buf_size, DMA_FROM_DEVICE);\n \n \t\t/* receive data */\n@@ -1600,7 +1601,7 @@ static int mtk_tx_alloc(struct mtk_eth *\n \tif (!ring->buf)\n \t\tgoto no_tx_mem;\n \n-\tring->dma = dma_alloc_coherent(eth->dev, MTK_DMA_SIZE * sz,\n+\tring->dma = dma_alloc_coherent(eth->dma_dev, MTK_DMA_SIZE * sz,\n \t\t\t\t       &ring->phys, GFP_ATOMIC);\n \tif (!ring->dma)\n \t\tgoto no_tx_mem;\n@@ -1618,7 +1619,7 @@ static int mtk_tx_alloc(struct mtk_eth *\n \t * descriptors in ring->dma_pdma.\n \t */\n \tif (!MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {\n-\t\tring->dma_pdma = dma_alloc_coherent(eth->dev, MTK_DMA_SIZE * sz,\n+\t\tring->dma_pdma = dma_alloc_coherent(eth->dma_dev, MTK_DMA_SIZE * sz,\n \t\t\t\t\t\t    &ring->phys_pdma,\n \t\t\t\t\t\t    GFP_ATOMIC);\n \t\tif (!ring->dma_pdma)\n@@ -1677,7 +1678,7 @@ static void mtk_tx_clean(struct mtk_eth\n \t}\n \n \tif (ring->dma) {\n-\t\tdma_free_coherent(eth->dev,\n+\t\tdma_free_coherent(eth->dma_dev,\n \t\t\t\t  MTK_DMA_SIZE * sizeof(*ring->dma),\n \t\t\t\t  ring->dma,\n \t\t\t\t  ring->phys);\n@@ -1685,7 +1686,7 @@ static void mtk_tx_clean(struct mtk_eth\n \t}\n \n \tif (ring->dma_pdma) {\n-\t\tdma_free_coherent(eth->dev,\n+\t\tdma_free_coherent(eth->dma_dev,\n \t\t\t\t  MTK_DMA_SIZE * sizeof(*ring->dma_pdma),\n \t\t\t\t  ring->dma_pdma,\n \t\t\t\t  ring->phys_pdma);\n@@ -1730,18 +1731,18 @@ static int mtk_rx_alloc(struct mtk_eth *\n \t\t\treturn -ENOMEM;\n \t}\n \n-\tring->dma = dma_alloc_coherent(eth->dev,\n+\tring->dma = dma_alloc_coherent(eth->dma_dev,\n \t\t\t\t       rx_dma_size * sizeof(*ring->dma),\n \t\t\t\t       &ring->phys, GFP_ATOMIC);\n \tif (!ring->dma)\n \t\treturn -ENOMEM;\n \n \tfor (i = 0; i < rx_dma_size; i++) {\n-\t\tdma_addr_t dma_addr = dma_map_single(eth->dev,\n+\t\tdma_addr_t dma_addr = dma_map_single(eth->dma_dev,\n \t\t\t\tring->data[i] + NET_SKB_PAD + eth->ip_align,\n \t\t\t\tring->buf_size,\n \t\t\t\tDMA_FROM_DEVICE);\n-\t\tif (unlikely(dma_mapping_error(eth->dev, dma_addr)))\n+\t\tif (unlikely(dma_mapping_error(eth->dma_dev, dma_addr)))\n \t\t\treturn -ENOMEM;\n \t\tring->dma[i].rxd1 = (unsigned int)dma_addr;\n \n@@ -1777,7 +1778,7 @@ static void mtk_rx_clean(struct mtk_eth\n \t\t\t\tcontinue;\n \t\t\tif (!ring->dma[i].rxd1)\n \t\t\t\tcontinue;\n-\t\t\tdma_unmap_single(eth->dev,\n+\t\t\tdma_unmap_single(eth->dma_dev,\n \t\t\t\t\t ring->dma[i].rxd1,\n \t\t\t\t\t ring->buf_size,\n \t\t\t\t\t DMA_FROM_DEVICE);\n@@ -1788,7 +1789,7 @@ static void mtk_rx_clean(struct mtk_eth\n \t}\n \n \tif (ring->dma) {\n-\t\tdma_free_coherent(eth->dev,\n+\t\tdma_free_coherent(eth->dma_dev,\n \t\t\t\t  ring->dma_size * sizeof(*ring->dma),\n \t\t\t\t  ring->dma,\n \t\t\t\t  ring->phys);\n@@ -2141,7 +2142,7 @@ static void mtk_dma_free(struct mtk_eth\n \t\tif (eth->netdev[i])\n \t\t\tnetdev_reset_queue(eth->netdev[i]);\n \tif (eth->scratch_ring) {\n-\t\tdma_free_coherent(eth->dev,\n+\t\tdma_free_coherent(eth->dma_dev,\n \t\t\t\t  MTK_DMA_SIZE * sizeof(struct mtk_tx_dma),\n \t\t\t\t  eth->scratch_ring,\n \t\t\t\t  eth->phy_scratch_ring);\n@@ -2491,6 +2492,8 @@ static void mtk_dim_tx(struct work_struc\n \n static int mtk_hw_init(struct mtk_eth *eth)\n {\n+\tu32 dma_mask = ETHSYS_DMA_AG_MAP_PDMA | ETHSYS_DMA_AG_MAP_QDMA |\n+\t\t       ETHSYS_DMA_AG_MAP_PPE;\n \tint i, val, ret;\n \n \tif (test_and_set_bit(MTK_HW_INIT, &eth->state))\n@@ -2503,6 +2506,10 @@ static int mtk_hw_init(struct mtk_eth *e\n \tif (ret)\n \t\tgoto err_disable_pm;\n \n+\tif (eth->ethsys)\n+\t\tregmap_update_bits(eth->ethsys, ETHSYS_DMA_AG_MAP, dma_mask,\n+\t\t\t\t   of_dma_is_coherent(eth->dma_dev->of_node) * dma_mask);\n+\n \tif (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) {\n \t\tret = device_reset(eth->dev);\n \t\tif (ret) {\n@@ -3056,6 +3063,35 @@ free_netdev:\n \treturn err;\n }\n \n+void mtk_eth_set_dma_device(struct mtk_eth *eth, struct device *dma_dev)\n+{\n+\tstruct net_device *dev, *tmp;\n+\tLIST_HEAD(dev_list);\n+\tint i;\n+\n+\trtnl_lock();\n+\n+\tfor (i = 0; i < MTK_MAC_COUNT; i++) {\n+\t\tdev = eth->netdev[i];\n+\n+\t\tif (!dev || !(dev->flags & IFF_UP))\n+\t\t\tcontinue;\n+\n+\t\tlist_add_tail(&dev->close_list, &dev_list);\n+\t}\n+\n+\tdev_close_many(&dev_list, false);\n+\n+\teth->dma_dev = dma_dev;\n+\n+\tlist_for_each_entry_safe(dev, tmp, &dev_list, close_list) {\n+\t\tlist_del_init(&dev->close_list);\n+\t\tdev_open(dev, NULL);\n+\t}\n+\n+\trtnl_unlock();\n+}\n+\n static int mtk_probe(struct platform_device *pdev)\n {\n \tstruct device_node *mac_np;\n@@ -3069,6 +3105,7 @@ static int mtk_probe(struct platform_dev\n \teth->soc = of_device_get_match_data(&pdev->dev);\n \n \teth->dev = &pdev->dev;\n+\teth->dma_dev = &pdev->dev;\n \teth->base = devm_platform_ioremap_resource(pdev, 0);\n \tif (IS_ERR(eth->base))\n \t\treturn PTR_ERR(eth->base);\n@@ -3117,6 +3154,16 @@ static int mtk_probe(struct platform_dev\n \t\t}\n \t}\n \n+\tif (of_dma_is_coherent(pdev->dev.of_node)) {\n+\t\tstruct regmap *cci;\n+\n+\t\tcci = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,\n+\t\t\t\t\t\t      \"mediatek,cci-control\");\n+\t\t/* enable CPU/bus coherency */\n+\t\tif (!IS_ERR(cci))\n+\t\t\tregmap_write(cci, 0, 3);\n+\t}\n+\n \tif (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) {\n \t\teth->sgmii = devm_kzalloc(eth->dev, sizeof(*eth->sgmii),\n \t\t\t\t\t  GFP_KERNEL);\n--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h\n+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h\n@@ -462,6 +462,12 @@\n #define RSTCTRL_FE\t\tBIT(6)\n #define RSTCTRL_PPE\t\tBIT(31)\n \n+/* ethernet dma channel agent map */\n+#define ETHSYS_DMA_AG_MAP\t0x408\n+#define ETHSYS_DMA_AG_MAP_PDMA\tBIT(0)\n+#define ETHSYS_DMA_AG_MAP_QDMA\tBIT(1)\n+#define ETHSYS_DMA_AG_MAP_PPE\tBIT(2)\n+\n /* SGMII subsystem config registers */\n /* Register to auto-negotiation restart */\n #define SGMSYS_PCS_CONTROL_1\t0x0\n@@ -879,6 +885,7 @@ struct mtk_sgmii {\n /* struct mtk_eth -\tThis is the main datasructure for holding the state\n  *\t\t\tof the driver\n  * @dev:\t\tThe device pointer\n+ * @dev:\t\tThe device pointer used for dma mapping/alloc\n  * @base:\t\tThe mapped register i/o base\n  * @page_lock:\t\tMake sure that register operations are atomic\n  * @tx_irq__lock:\tMake sure that IRQ register operations are atomic\n@@ -922,6 +929,7 @@ struct mtk_sgmii {\n \n struct mtk_eth {\n \tstruct device\t\t\t*dev;\n+\tstruct device\t\t\t*dma_dev;\n \tvoid __iomem\t\t\t*base;\n \tspinlock_t\t\t\tpage_lock;\n \tspinlock_t\t\t\ttx_irq_lock;\n@@ -1020,6 +1028,7 @@ int mtk_gmac_rgmii_path_setup(struct mtk\n int mtk_eth_offload_init(struct mtk_eth *eth);\n int mtk_eth_setup_tc(struct net_device *dev, enum tc_setup_type type,\n \t\t     void *type_data);\n+void mtk_eth_set_dma_device(struct mtk_eth *eth, struct device *dma_dev);\n \n \n #endif /* MTK_ETH_H */\n"
  },
  {
    "path": "target/linux/generic/pending-5.15/701-01-arm64-dts-mediatek-mt7622-add-support-for-coherent-D.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nDate: Mon, 7 Feb 2022 10:27:22 +0100\nSubject: [PATCH] arm64: dts: mediatek: mt7622: add support for coherent\n DMA\n\nIt improves performance by eliminating the need for a cache flush on rx and tx\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n\n--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi\n+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi\n@@ -357,7 +357,7 @@\n \t\t};\n \n \t\tcci_control2: slave-if@5000 {\n-\t\t\tcompatible = \"arm,cci-400-ctrl-if\";\n+\t\t\tcompatible = \"arm,cci-400-ctrl-if\", \"syscon\";\n \t\t\tinterface-type = \"ace\";\n \t\t\treg = <0x5000 0x1000>;\n \t\t};\n@@ -937,6 +937,8 @@\n \t\tpower-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>;\n \t\tmediatek,ethsys = <&ethsys>;\n \t\tmediatek,sgmiisys = <&sgmiisys>;\n+\t\tmediatek,cci-control = <&cci_control2>;\n+\t\tdma-coherent;\n \t\t#address-cells = <1>;\n \t\t#size-cells = <0>;\n \t\tstatus = \"disabled\";\n"
  },
  {
    "path": "target/linux/generic/pending-5.15/701-02-net-ethernet-mtk_eth_soc-add-support-for-Wireless-Et.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nDate: Sat, 5 Feb 2022 17:56:08 +0100\nSubject: [PATCH] net: ethernet: mtk_eth_soc: add support for Wireless\n Ethernet Dispatch (WED)\n\nThe Wireless Ethernet Dispatch subsystem on the MT7622 SoC can be\nconfigured to intercept and handle access to the DMA queues and\nPCIe interrupts for a MT7615/MT7915 wireless card.\nIt can manage the internal WDMA (Wireless DMA) controller, which allows\nethernet packets to be passed from the packet switch engine (PSE) to the\nwireless card, bypassing the CPU entirely.\nThis can be used to implement hardware flow offloading from ethernet to\nWLAN.\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n create mode 100644 drivers/net/ethernet/mediatek/mtk_wed.c\n create mode 100644 drivers/net/ethernet/mediatek/mtk_wed.h\n create mode 100644 drivers/net/ethernet/mediatek/mtk_wed_debugfs.c\n create mode 100644 drivers/net/ethernet/mediatek/mtk_wed_ops.c\n create mode 100644 drivers/net/ethernet/mediatek/mtk_wed_regs.h\n create mode 100644 include/linux/soc/mediatek/mtk_wed.h\n\n--- a/drivers/net/ethernet/mediatek/Kconfig\n+++ b/drivers/net/ethernet/mediatek/Kconfig\n@@ -7,6 +7,10 @@ config NET_VENDOR_MEDIATEK\n \n if NET_VENDOR_MEDIATEK\n \n+config NET_MEDIATEK_SOC_WED\n+\tdepends on ARCH_MEDIATEK || COMPILE_TEST\n+\tdef_bool NET_MEDIATEK_SOC != n\n+\n config NET_MEDIATEK_SOC\n \ttristate \"MediaTek SoC Gigabit Ethernet support\"\n \tdepends on NET_DSA || !NET_DSA\n--- a/drivers/net/ethernet/mediatek/Makefile\n+++ b/drivers/net/ethernet/mediatek/Makefile\n@@ -5,4 +5,9 @@\n \n obj-$(CONFIG_NET_MEDIATEK_SOC) += mtk_eth.o\n mtk_eth-y := mtk_eth_soc.o mtk_sgmii.o mtk_eth_path.o mtk_ppe.o mtk_ppe_debugfs.o mtk_ppe_offload.o\n+mtk_eth-$(CONFIG_NET_MEDIATEK_SOC_WED) += mtk_wed.o\n+ifdef CONFIG_DEBUG_FS\n+mtk_eth-$(CONFIG_NET_MEDIATEK_SOC_WED) += mtk_wed_debugfs.o\n+endif\n+obj-$(CONFIG_NET_MEDIATEK_SOC_WED) += mtk_wed_ops.o\n obj-$(CONFIG_NET_MEDIATEK_STAR_EMAC) += mtk_star_emac.o\n--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c\n+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c\n@@ -24,6 +24,7 @@\n #include <net/dsa.h>\n \n #include \"mtk_eth_soc.h\"\n+#include \"mtk_wed.h\"\n \n static int mtk_msg_level = -1;\n module_param_named(msg_level, mtk_msg_level, int, 0);\n@@ -3186,6 +3187,22 @@ static int mtk_probe(struct platform_dev\n \t\t}\n \t}\n \n+\tfor (i = 0;; i++) {\n+\t\tstruct device_node *np = of_parse_phandle(pdev->dev.of_node,\n+\t\t\t\t\t\t\t  \"mediatek,wed\", i);\n+\t\tstatic const u32 wdma_regs[] = {\n+\t\t\tMTK_WDMA0_BASE,\n+\t\t\tMTK_WDMA1_BASE\n+\t\t};\n+\t\tvoid __iomem *wdma;\n+\n+\t\tif (!np || i >= ARRAY_SIZE(wdma_regs))\n+\t\t\tbreak;\n+\n+\t\twdma = eth->base + wdma_regs[i];\n+\t\tmtk_wed_add_hw(np, eth, wdma, i);\n+\t}\n+\n \tfor (i = 0; i < 3; i++) {\n \t\tif (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT) && i > 0)\n \t\t\teth->irq[i] = eth->irq[0];\n--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h\n+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h\n@@ -295,6 +295,9 @@\n #define MTK_GDM1_TX_GPCNT\t0x2438\n #define MTK_STAT_OFFSET\t\t0x40\n \n+#define MTK_WDMA0_BASE\t\t0x2800\n+#define MTK_WDMA1_BASE\t\t0x2c00\n+\n /* QDMA descriptor txd4 */\n #define TX_DMA_CHKSUM\t\t(0x7 << 29)\n #define TX_DMA_TSO\t\tBIT(28)\n--- /dev/null\n+++ b/drivers/net/ethernet/mediatek/mtk_wed.c\n@@ -0,0 +1,875 @@\n+// SPDX-License-Identifier: GPL-2.0-only\n+/* Copyright (C) 2021 Felix Fietkau <nbd@nbd.name> */\n+\n+#include <linux/kernel.h>\n+#include <linux/slab.h>\n+#include <linux/module.h>\n+#include <linux/bitfield.h>\n+#include <linux/dma-mapping.h>\n+#include <linux/skbuff.h>\n+#include <linux/of_platform.h>\n+#include <linux/of_address.h>\n+#include <linux/mfd/syscon.h>\n+#include <linux/debugfs.h>\n+#include <linux/soc/mediatek/mtk_wed.h>\n+#include \"mtk_eth_soc.h\"\n+#include \"mtk_wed_regs.h\"\n+#include \"mtk_wed.h\"\n+#include \"mtk_ppe.h\"\n+\n+#define MTK_PCIE_BASE(n)\t\t(0x1a143000 + (n) * 0x2000)\n+\n+#define MTK_WED_PKT_SIZE\t\t1900\n+#define MTK_WED_BUF_SIZE\t\t2048\n+#define MTK_WED_BUF_PER_PAGE\t\t(PAGE_SIZE / 2048)\n+\n+#define MTK_WED_TX_RING_SIZE\t\t2048\n+#define MTK_WED_WDMA_RING_SIZE\t\t1024\n+\n+static struct mtk_wed_hw *hw_list[2];\n+static DEFINE_MUTEX(hw_lock);\n+\n+static void\n+wed_m32(struct mtk_wed_device *dev, u32 reg, u32 mask, u32 val)\n+{\n+\tregmap_update_bits(dev->hw->regs, reg, mask | val, val);\n+}\n+\n+static void\n+wed_set(struct mtk_wed_device *dev, u32 reg, u32 mask)\n+{\n+\treturn wed_m32(dev, reg, 0, mask);\n+}\n+\n+static void\n+wed_clr(struct mtk_wed_device *dev, u32 reg, u32 mask)\n+{\n+\treturn wed_m32(dev, reg, mask, 0);\n+}\n+\n+static void\n+wdma_m32(struct mtk_wed_device *dev, u32 reg, u32 mask, u32 val)\n+{\n+\twdma_w32(dev, reg, (wdma_r32(dev, reg) & ~mask) | val);\n+}\n+\n+static void\n+wdma_set(struct mtk_wed_device *dev, u32 reg, u32 mask)\n+{\n+\twdma_m32(dev, reg, 0, mask);\n+}\n+\n+static u32\n+mtk_wed_read_reset(struct mtk_wed_device *dev)\n+{\n+\treturn wed_r32(dev, MTK_WED_RESET);\n+}\n+\n+static void\n+mtk_wed_reset(struct mtk_wed_device *dev, u32 mask)\n+{\n+\tu32 status;\n+\n+\twed_w32(dev, MTK_WED_RESET, mask);\n+\tif (readx_poll_timeout(mtk_wed_read_reset, dev, status,\n+\t\t\t       !(status & mask), 0, 1000))\n+\t\tWARN_ON_ONCE(1);\n+}\n+\n+static struct mtk_wed_hw *\n+mtk_wed_assign(struct mtk_wed_device *dev)\n+{\n+\tstruct mtk_wed_hw *hw;\n+\n+\thw = hw_list[pci_domain_nr(dev->wlan.pci_dev->bus)];\n+\tif (!hw || hw->wed_dev)\n+\t\treturn NULL;\n+\n+\thw->wed_dev = dev;\n+\treturn hw;\n+}\n+\n+static int\n+mtk_wed_buffer_alloc(struct mtk_wed_device *dev)\n+{\n+\tstruct mtk_wdma_desc *desc;\n+\tdma_addr_t desc_phys;\n+\tvoid **page_list;\n+\tint token = dev->wlan.token_start;\n+\tint ring_size;\n+\tint n_pages;\n+\tint i, page_idx;\n+\n+\tring_size = dev->wlan.nbuf & ~(MTK_WED_BUF_PER_PAGE - 1);\n+\tn_pages = ring_size / MTK_WED_BUF_PER_PAGE;\n+\n+\tpage_list = kcalloc(n_pages, sizeof(*page_list), GFP_KERNEL);\n+\tif (!page_list)\n+\t\treturn -ENOMEM;\n+\n+\tdev->buf_ring.size = ring_size;\n+\tdev->buf_ring.pages = page_list;\n+\n+\tdesc = dma_alloc_coherent(dev->hw->dev, ring_size * sizeof(*desc),\n+\t\t\t\t  &desc_phys, GFP_KERNEL);\n+\tif (!desc)\n+\t\treturn -ENOMEM;\n+\n+\tdev->buf_ring.desc = desc;\n+\tdev->buf_ring.desc_phys = desc_phys;\n+\n+\tfor (i = 0, page_idx = 0; i < ring_size; i += MTK_WED_BUF_PER_PAGE) {\n+\t\tdma_addr_t page_phys, buf_phys;\n+\t\tstruct page *page;\n+\t\tvoid *buf;\n+\t\tint s;\n+\n+\t\tpage = __dev_alloc_pages(GFP_KERNEL, 0);\n+\t\tif (!page)\n+\t\t\treturn -ENOMEM;\n+\n+\t\tpage_phys = dma_map_page(dev->hw->dev, page, 0, PAGE_SIZE,\n+\t\t\t\t\t DMA_BIDIRECTIONAL);\n+\t\tif (dma_mapping_error(dev->hw->dev, page_phys)) {\n+\t\t\t__free_page(page);\n+\t\t\treturn -ENOMEM;\n+\t\t}\n+\n+\t\tpage_list[page_idx++] = page;\n+\t\tdma_sync_single_for_cpu(dev->hw->dev, page_phys, PAGE_SIZE,\n+\t\t\t\t\tDMA_BIDIRECTIONAL);\n+\n+\t\tbuf = page_to_virt(page);\n+\t\tbuf_phys = page_phys;\n+\n+\t\tfor (s = 0; s < MTK_WED_BUF_PER_PAGE; s++) {\n+\t\t\tu32 txd_size;\n+\n+\t\t\ttxd_size = dev->wlan.init_buf(buf, buf_phys, token++);\n+\n+\t\t\tdesc->buf0 = buf_phys;\n+\t\t\tdesc->buf1 = buf_phys + txd_size;\n+\t\t\tdesc->ctrl = FIELD_PREP(MTK_WDMA_DESC_CTRL_LEN0,\n+\t\t\t\t\t\ttxd_size) |\n+\t\t\t\t     FIELD_PREP(MTK_WDMA_DESC_CTRL_LEN1,\n+\t\t\t\t\t\tMTK_WED_BUF_SIZE - txd_size) |\n+\t\t\t\t     MTK_WDMA_DESC_CTRL_LAST_SEG1;\n+\t\t\tdesc->info = 0;\n+\t\t\tdesc++;\n+\n+\t\t\tbuf += MTK_WED_BUF_SIZE;\n+\t\t\tbuf_phys += MTK_WED_BUF_SIZE;\n+\t\t}\n+\n+\t\tdma_sync_single_for_device(dev->hw->dev, page_phys, PAGE_SIZE,\n+\t\t\t\t\t   DMA_BIDIRECTIONAL);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static void\n+mtk_wed_free_buffer(struct mtk_wed_device *dev)\n+{\n+\tstruct mtk_wdma_desc *desc = dev->buf_ring.desc;\n+\tvoid **page_list = dev->buf_ring.pages;\n+\tint page_idx;\n+\tint i;\n+\n+\tif (!page_list)\n+\t\treturn;\n+\n+\tif (!desc)\n+\t\tgoto free_pagelist;\n+\n+\tfor (i = 0, page_idx = 0; i < dev->buf_ring.size; i += MTK_WED_BUF_PER_PAGE) {\n+\t\tvoid *page = page_list[page_idx++];\n+\n+\t\tif (!page)\n+\t\t\tbreak;\n+\n+\t\tdma_unmap_page(dev->hw->dev, desc[i].buf0,\n+\t\t\t       PAGE_SIZE, DMA_BIDIRECTIONAL);\n+\t\t__free_page(page);\n+\t}\n+\n+\tdma_free_coherent(dev->hw->dev, dev->buf_ring.size * sizeof(*desc),\n+\t\t\t  desc, dev->buf_ring.desc_phys);\n+\n+free_pagelist:\n+\tkfree(page_list);\n+}\n+\n+static void\n+mtk_wed_free_ring(struct mtk_wed_device *dev, struct mtk_wed_ring *ring)\n+{\n+\tif (!ring->desc)\n+\t\treturn;\n+\n+\tdma_free_coherent(dev->hw->dev, ring->size * sizeof(*ring->desc),\n+\t\t\t  ring->desc, ring->desc_phys);\n+}\n+\n+static void\n+mtk_wed_free_tx_rings(struct mtk_wed_device *dev)\n+{\n+\tint i;\n+\n+\tfor (i = 0; i < ARRAY_SIZE(dev->tx_ring); i++)\n+\t\tmtk_wed_free_ring(dev, &dev->tx_ring[i]);\n+\tfor (i = 0; i < ARRAY_SIZE(dev->tx_wdma); i++)\n+\t\tmtk_wed_free_ring(dev, &dev->tx_wdma[i]);\n+}\n+\n+static void\n+mtk_wed_set_ext_int(struct mtk_wed_device *dev, bool en)\n+{\n+\tu32 mask = MTK_WED_EXT_INT_STATUS_ERROR_MASK;\n+\n+\tif (!dev->hw->num_flows)\n+\t\tmask &= ~MTK_WED_EXT_INT_STATUS_TKID_WO_PYLD;\n+\n+\twed_w32(dev, MTK_WED_EXT_INT_MASK, en ? mask : 0);\n+\twed_r32(dev, MTK_WED_EXT_INT_MASK);\n+}\n+\n+static void\n+mtk_wed_stop(struct mtk_wed_device *dev)\n+{\n+\tregmap_write(dev->hw->mirror, dev->hw->index * 4, 0);\n+\tmtk_wed_set_ext_int(dev, false);\n+\n+\twed_clr(dev, MTK_WED_CTRL,\n+\t\tMTK_WED_CTRL_WDMA_INT_AGENT_EN |\n+\t\tMTK_WED_CTRL_WPDMA_INT_AGENT_EN |\n+\t\tMTK_WED_CTRL_WED_TX_BM_EN |\n+\t\tMTK_WED_CTRL_WED_TX_FREE_AGENT_EN);\n+\twed_w32(dev, MTK_WED_WPDMA_INT_TRIGGER, 0);\n+\twed_w32(dev, MTK_WED_WDMA_INT_TRIGGER, 0);\n+\twdma_w32(dev, MTK_WDMA_INT_MASK, 0);\n+\twdma_w32(dev, MTK_WDMA_INT_GRP2, 0);\n+\twed_w32(dev, MTK_WED_WPDMA_INT_MASK, 0);\n+\n+\twed_clr(dev, MTK_WED_GLO_CFG,\n+\t\tMTK_WED_GLO_CFG_TX_DMA_EN |\n+\t\tMTK_WED_GLO_CFG_RX_DMA_EN);\n+\twed_clr(dev, MTK_WED_WPDMA_GLO_CFG,\n+\t\tMTK_WED_WPDMA_GLO_CFG_TX_DRV_EN |\n+\t\tMTK_WED_WPDMA_GLO_CFG_RX_DRV_EN);\n+\twed_clr(dev, MTK_WED_WDMA_GLO_CFG,\n+\t\tMTK_WED_WDMA_GLO_CFG_RX_DRV_EN);\n+}\n+\n+static void\n+mtk_wed_detach(struct mtk_wed_device *dev)\n+{\n+\tstruct device_node *wlan_node = dev->wlan.pci_dev->dev.of_node;\n+\tstruct mtk_wed_hw *hw = dev->hw;\n+\n+\tmutex_lock(&hw_lock);\n+\n+\tmtk_wed_stop(dev);\n+\n+\twdma_w32(dev, MTK_WDMA_RESET_IDX, MTK_WDMA_RESET_IDX_RX);\n+\twdma_w32(dev, MTK_WDMA_RESET_IDX, 0);\n+\n+\tmtk_wed_reset(dev, MTK_WED_RESET_WED);\n+\n+\tmtk_wed_free_buffer(dev);\n+\tmtk_wed_free_tx_rings(dev);\n+\n+\tif (of_dma_is_coherent(wlan_node))\n+\t\tregmap_update_bits(hw->hifsys, HIFSYS_DMA_AG_MAP,\n+\t\t\t\t   BIT(hw->index), BIT(hw->index));\n+\n+\tif (!hw_list[!hw->index]->wed_dev &&\n+\t    hw->eth->dma_dev != hw->eth->dev)\n+\t\tmtk_eth_set_dma_device(hw->eth, hw->eth->dev);\n+\n+\tmemset(dev, 0, sizeof(*dev));\n+\tmodule_put(THIS_MODULE);\n+\n+\thw->wed_dev = NULL;\n+\tmutex_unlock(&hw_lock);\n+}\n+\n+static void\n+mtk_wed_hw_init_early(struct mtk_wed_device *dev)\n+{\n+\tu32 mask, set;\n+\tu32 offset;\n+\n+\tmtk_wed_stop(dev);\n+\tmtk_wed_reset(dev, MTK_WED_RESET_WED);\n+\n+\tmask = MTK_WED_WDMA_GLO_CFG_BT_SIZE |\n+\t       MTK_WED_WDMA_GLO_CFG_DYNAMIC_DMAD_RECYCLE |\n+\t       MTK_WED_WDMA_GLO_CFG_RX_DIS_FSM_AUTO_IDLE;\n+\tset = FIELD_PREP(MTK_WED_WDMA_GLO_CFG_BT_SIZE, 2) |\n+\t      MTK_WED_WDMA_GLO_CFG_DYNAMIC_SKIP_DMAD_PREP |\n+\t      MTK_WED_WDMA_GLO_CFG_IDLE_DMAD_SUPPLY;\n+\twed_m32(dev, MTK_WED_WDMA_GLO_CFG, mask, set);\n+\n+\twdma_set(dev, MTK_WDMA_GLO_CFG, MTK_WDMA_GLO_CFG_RX_INFO_PRERES);\n+\n+\toffset = dev->hw->index ? 0x04000400 : 0;\n+\twed_w32(dev, MTK_WED_WDMA_OFFSET0, 0x2a042a20 + offset);\n+\twed_w32(dev, MTK_WED_WDMA_OFFSET1, 0x29002800 + offset);\n+\n+\twed_w32(dev, MTK_WED_PCIE_CFG_BASE, MTK_PCIE_BASE(dev->hw->index));\n+\twed_w32(dev, MTK_WED_WPDMA_CFG_BASE, dev->wlan.wpdma_phys);\n+}\n+\n+static void\n+mtk_wed_hw_init(struct mtk_wed_device *dev)\n+{\n+\tif (dev->init_done)\n+\t\treturn;\n+\n+\tdev->init_done = true;\n+\tmtk_wed_set_ext_int(dev, false);\n+\twed_w32(dev, MTK_WED_TX_BM_CTRL,\n+\t\tMTK_WED_TX_BM_CTRL_PAUSE |\n+\t\tFIELD_PREP(MTK_WED_TX_BM_CTRL_VLD_GRP_NUM,\n+\t\t\t   dev->buf_ring.size / 128) |\n+\t\tFIELD_PREP(MTK_WED_TX_BM_CTRL_RSV_GRP_NUM,\n+\t\t\t   MTK_WED_TX_RING_SIZE / 256));\n+\n+\twed_w32(dev, MTK_WED_TX_BM_BASE, dev->buf_ring.desc_phys);\n+\n+\twed_w32(dev, MTK_WED_TX_BM_TKID,\n+\t\tFIELD_PREP(MTK_WED_TX_BM_TKID_START,\n+\t\t\t   dev->wlan.token_start) |\n+\t\tFIELD_PREP(MTK_WED_TX_BM_TKID_END,\n+\t\t\t   dev->wlan.token_start + dev->wlan.nbuf - 1));\n+\n+\twed_w32(dev, MTK_WED_TX_BM_BUF_LEN, MTK_WED_PKT_SIZE);\n+\n+\twed_w32(dev, MTK_WED_TX_BM_DYN_THR,\n+\t\tFIELD_PREP(MTK_WED_TX_BM_DYN_THR_LO, 1) |\n+\t\tMTK_WED_TX_BM_DYN_THR_HI);\n+\n+\tmtk_wed_reset(dev, MTK_WED_RESET_TX_BM);\n+\n+\twed_set(dev, MTK_WED_CTRL,\n+\t\tMTK_WED_CTRL_WED_TX_BM_EN |\n+\t\tMTK_WED_CTRL_WED_TX_FREE_AGENT_EN);\n+\n+\twed_clr(dev, MTK_WED_TX_BM_CTRL, MTK_WED_TX_BM_CTRL_PAUSE);\n+}\n+\n+static void\n+mtk_wed_ring_reset(struct mtk_wdma_desc *desc, int size)\n+{\n+\tint i;\n+\n+\tfor (i = 0; i < size; i++) {\n+\t\tdesc[i].buf0 = 0;\n+\t\tdesc[i].ctrl = cpu_to_le32(MTK_WDMA_DESC_CTRL_DMA_DONE);\n+\t\tdesc[i].buf1 = 0;\n+\t\tdesc[i].info = 0;\n+\t}\n+}\n+\n+static u32\n+mtk_wed_check_busy(struct mtk_wed_device *dev)\n+{\n+\tif (wed_r32(dev, MTK_WED_GLO_CFG) & MTK_WED_GLO_CFG_TX_DMA_BUSY)\n+\t\treturn true;\n+\n+\tif (wed_r32(dev, MTK_WED_WPDMA_GLO_CFG) &\n+\t    MTK_WED_WPDMA_GLO_CFG_TX_DRV_BUSY)\n+\t\treturn true;\n+\n+\tif (wed_r32(dev, MTK_WED_CTRL) & MTK_WED_CTRL_WDMA_INT_AGENT_BUSY)\n+\t\treturn true;\n+\n+\tif (wed_r32(dev, MTK_WED_WDMA_GLO_CFG) &\n+\t    MTK_WED_WDMA_GLO_CFG_RX_DRV_BUSY)\n+\t\treturn true;\n+\n+\tif (wdma_r32(dev, MTK_WDMA_GLO_CFG) &\n+\t    MTK_WED_WDMA_GLO_CFG_RX_DRV_BUSY)\n+\t\treturn true;\n+\n+\tif (wed_r32(dev, MTK_WED_CTRL) &\n+\t    (MTK_WED_CTRL_WED_TX_BM_BUSY | MTK_WED_CTRL_WED_TX_FREE_AGENT_BUSY))\n+\t\treturn true;\n+\n+\treturn false;\n+}\n+\n+static int\n+mtk_wed_poll_busy(struct mtk_wed_device *dev)\n+{\n+\tint sleep = 15000;\n+\tint timeout = 100 * sleep;\n+\tu32 val;\n+\n+\treturn read_poll_timeout(mtk_wed_check_busy, val, !val, sleep,\n+\t\t\t\t timeout, false, dev);\n+}\n+\n+static void\n+mtk_wed_reset_dma(struct mtk_wed_device *dev)\n+{\n+\tbool busy = false;\n+\tu32 val;\n+\tint i;\n+\n+\tfor (i = 0; i < ARRAY_SIZE(dev->tx_ring); i++) {\n+\t\tstruct mtk_wdma_desc *desc = dev->tx_ring[i].desc;\n+\n+\t\tif (!desc)\n+\t\t\tcontinue;\n+\n+\t\tmtk_wed_ring_reset(desc, MTK_WED_TX_RING_SIZE);\n+\t}\n+\n+\tif (mtk_wed_poll_busy(dev))\n+\t\tbusy = mtk_wed_check_busy(dev);\n+\n+\tif (busy) {\n+\t\tmtk_wed_reset(dev, MTK_WED_RESET_WED_TX_DMA);\n+\t} else {\n+\t\twed_w32(dev, MTK_WED_RESET_IDX,\n+\t\t\tMTK_WED_RESET_IDX_TX |\n+\t\t\tMTK_WED_RESET_IDX_RX);\n+\t\twed_w32(dev, MTK_WED_RESET_IDX, 0);\n+\t}\n+\n+\twdma_w32(dev, MTK_WDMA_RESET_IDX, MTK_WDMA_RESET_IDX_RX);\n+\twdma_w32(dev, MTK_WDMA_RESET_IDX, 0);\n+\n+\tif (busy) {\n+\t\tmtk_wed_reset(dev, MTK_WED_RESET_WDMA_INT_AGENT);\n+\t\tmtk_wed_reset(dev, MTK_WED_RESET_WDMA_RX_DRV);\n+\t} else {\n+\t\twed_w32(dev, MTK_WED_WDMA_RESET_IDX,\n+\t\t\tMTK_WED_WDMA_RESET_IDX_RX | MTK_WED_WDMA_RESET_IDX_DRV);\n+\t\twed_w32(dev, MTK_WED_WDMA_RESET_IDX, 0);\n+\n+\t\twed_set(dev, MTK_WED_WDMA_GLO_CFG,\n+\t\t\tMTK_WED_WDMA_GLO_CFG_RST_INIT_COMPLETE);\n+\n+\t\twed_clr(dev, MTK_WED_WDMA_GLO_CFG,\n+\t\t\tMTK_WED_WDMA_GLO_CFG_RST_INIT_COMPLETE);\n+\t}\n+\n+\tfor (i = 0; i < 100; i++) {\n+\t\tval = wed_r32(dev, MTK_WED_TX_BM_INTF);\n+\t\tif (FIELD_GET(MTK_WED_TX_BM_INTF_TKFIFO_FDEP, val) == 0x40)\n+\t\t\tbreak;\n+\t}\n+\n+\tmtk_wed_reset(dev, MTK_WED_RESET_TX_FREE_AGENT);\n+\tmtk_wed_reset(dev, MTK_WED_RESET_TX_BM);\n+\n+\tif (busy) {\n+\t\tmtk_wed_reset(dev, MTK_WED_RESET_WPDMA_INT_AGENT);\n+\t\tmtk_wed_reset(dev, MTK_WED_RESET_WPDMA_TX_DRV);\n+\t\tmtk_wed_reset(dev, MTK_WED_RESET_WPDMA_RX_DRV);\n+\t} else {\n+\t\twed_w32(dev, MTK_WED_WPDMA_RESET_IDX,\n+\t\t\tMTK_WED_WPDMA_RESET_IDX_TX |\n+\t\t\tMTK_WED_WPDMA_RESET_IDX_RX);\n+\t\twed_w32(dev, MTK_WED_WPDMA_RESET_IDX, 0);\n+\t}\n+\n+}\n+\n+static int\n+mtk_wed_ring_alloc(struct mtk_wed_device *dev, struct mtk_wed_ring *ring,\n+\t\t   int size)\n+{\n+\tring->desc = dma_alloc_coherent(dev->hw->dev,\n+\t\t\t\t\tsize * sizeof(*ring->desc),\n+\t\t\t\t\t&ring->desc_phys, GFP_KERNEL);\n+\tif (!ring->desc)\n+\t\treturn -ENOMEM;\n+\n+\tring->size = size;\n+\tmtk_wed_ring_reset(ring->desc, size);\n+\n+\treturn 0;\n+}\n+\n+static int\n+mtk_wed_wdma_ring_setup(struct mtk_wed_device *dev, int idx, int size)\n+{\n+\tstruct mtk_wed_ring *wdma = &dev->tx_wdma[idx];\n+\n+\tif (mtk_wed_ring_alloc(dev, wdma, MTK_WED_WDMA_RING_SIZE))\n+\t\treturn -ENOMEM;\n+\n+\twdma_w32(dev, MTK_WDMA_RING_RX(idx) + MTK_WED_RING_OFS_BASE,\n+\t\t wdma->desc_phys);\n+\twdma_w32(dev, MTK_WDMA_RING_RX(idx) + MTK_WED_RING_OFS_COUNT,\n+\t\t size);\n+\twdma_w32(dev, MTK_WDMA_RING_RX(idx) + MTK_WED_RING_OFS_CPU_IDX, 0);\n+\n+\twed_w32(dev, MTK_WED_WDMA_RING_RX(idx) + MTK_WED_RING_OFS_BASE,\n+\t\twdma->desc_phys);\n+\twed_w32(dev, MTK_WED_WDMA_RING_RX(idx) + MTK_WED_RING_OFS_COUNT,\n+\t\tsize);\n+\n+\treturn 0;\n+}\n+\n+static void\n+mtk_wed_start(struct mtk_wed_device *dev, u32 irq_mask)\n+{\n+\tu32 wdma_mask;\n+\tu32 val;\n+\tint i;\n+\n+\tfor (i = 0; i < ARRAY_SIZE(dev->tx_wdma); i++)\n+\t\tif (!dev->tx_wdma[i].desc)\n+\t\t\tmtk_wed_wdma_ring_setup(dev, i, 16);\n+\n+\twdma_mask = FIELD_PREP(MTK_WDMA_INT_MASK_RX_DONE, GENMASK(1, 0));\n+\n+\tmtk_wed_hw_init(dev);\n+\n+\twed_set(dev, MTK_WED_CTRL,\n+\t\tMTK_WED_CTRL_WDMA_INT_AGENT_EN |\n+\t\tMTK_WED_CTRL_WPDMA_INT_AGENT_EN |\n+\t\tMTK_WED_CTRL_WED_TX_BM_EN |\n+\t\tMTK_WED_CTRL_WED_TX_FREE_AGENT_EN);\n+\n+\twed_w32(dev, MTK_WED_PCIE_INT_TRIGGER, MTK_WED_PCIE_INT_TRIGGER_STATUS);\n+\n+\twed_w32(dev, MTK_WED_WPDMA_INT_TRIGGER,\n+\t\tMTK_WED_WPDMA_INT_TRIGGER_RX_DONE |\n+\t\tMTK_WED_WPDMA_INT_TRIGGER_TX_DONE);\n+\n+\twed_set(dev, MTK_WED_WPDMA_INT_CTRL,\n+\t\tMTK_WED_WPDMA_INT_CTRL_SUBRT_ADV);\n+\n+\twed_w32(dev, MTK_WED_WDMA_INT_TRIGGER, wdma_mask);\n+\twed_clr(dev, MTK_WED_WDMA_INT_CTRL, wdma_mask);\n+\n+\twdma_w32(dev, MTK_WDMA_INT_MASK, wdma_mask);\n+\twdma_w32(dev, MTK_WDMA_INT_GRP2, wdma_mask);\n+\n+\twed_w32(dev, MTK_WED_WPDMA_INT_MASK, irq_mask);\n+\twed_w32(dev, MTK_WED_INT_MASK, irq_mask);\n+\n+\twed_set(dev, MTK_WED_GLO_CFG,\n+\t\tMTK_WED_GLO_CFG_TX_DMA_EN |\n+\t\tMTK_WED_GLO_CFG_RX_DMA_EN);\n+\twed_set(dev, MTK_WED_WPDMA_GLO_CFG,\n+\t\tMTK_WED_WPDMA_GLO_CFG_TX_DRV_EN |\n+\t\tMTK_WED_WPDMA_GLO_CFG_RX_DRV_EN);\n+\twed_set(dev, MTK_WED_WDMA_GLO_CFG,\n+\t\tMTK_WED_WDMA_GLO_CFG_RX_DRV_EN);\n+\n+\tmtk_wed_set_ext_int(dev, true);\n+\tval = dev->wlan.wpdma_phys |\n+\t      MTK_PCIE_MIRROR_MAP_EN |\n+\t      FIELD_PREP(MTK_PCIE_MIRROR_MAP_WED_ID, dev->hw->index);\n+\n+\tif (dev->hw->index)\n+\t\tval |= BIT(1);\n+\tval |= BIT(0);\n+\tregmap_write(dev->hw->mirror, dev->hw->index * 4, val);\n+\n+\tdev->running = true;\n+}\n+\n+static int\n+mtk_wed_attach(struct mtk_wed_device *dev)\n+\t__releases(RCU)\n+{\n+\tstruct mtk_wed_hw *hw;\n+\tint ret = 0;\n+\n+\tRCU_LOCKDEP_WARN(!rcu_read_lock_held(),\n+\t\t\t \"mtk_wed_attach without holding the RCU read lock\");\n+\n+\tif (pci_domain_nr(dev->wlan.pci_dev->bus) > 1 ||\n+\t    !try_module_get(THIS_MODULE))\n+\t\tret = -ENODEV;\n+\n+\trcu_read_unlock();\n+\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tmutex_lock(&hw_lock);\n+\n+\thw = mtk_wed_assign(dev);\n+\tif (!hw) {\n+\t\tmodule_put(THIS_MODULE);\n+\t\tret = -ENODEV;\n+\t\tgoto out;\n+\t}\n+\n+\tdev_info(&dev->wlan.pci_dev->dev, \"attaching wed device %d\\n\", hw->index);\n+\n+\tdev->hw = hw;\n+\tdev->dev = hw->dev;\n+\tdev->irq = hw->irq;\n+\tdev->wdma_idx = hw->index;\n+\n+\tif (hw->eth->dma_dev == hw->eth->dev &&\n+\t    of_dma_is_coherent(hw->eth->dev->of_node))\n+\t\tmtk_eth_set_dma_device(hw->eth, hw->dev);\n+\n+\tret = mtk_wed_buffer_alloc(dev);\n+\tif (ret) {\n+\t\tmtk_wed_detach(dev);\n+\t\tgoto out;\n+\t}\n+\n+\tmtk_wed_hw_init_early(dev);\n+\tregmap_update_bits(hw->hifsys, HIFSYS_DMA_AG_MAP, BIT(hw->index), 0);\n+\n+out:\n+\tmutex_unlock(&hw_lock);\n+\n+\treturn ret;\n+}\n+\n+static int\n+mtk_wed_tx_ring_setup(struct mtk_wed_device *dev, int idx, void __iomem *regs)\n+{\n+\tstruct mtk_wed_ring *ring = &dev->tx_ring[idx];\n+\n+\t/*\n+\t * Tx ring redirection:\n+\t * Instead of configuring the WLAN PDMA TX ring directly, the WLAN\n+\t * driver allocated DMA ring gets configured into WED MTK_WED_RING_TX(n)\n+\t * registers.\n+\t *\n+\t * WED driver posts its own DMA ring as WLAN PDMA TX and configures it\n+\t * into MTK_WED_WPDMA_RING_TX(n) registers.\n+\t * It gets filled with packets picked up from WED TX ring and from\n+\t * WDMA RX.\n+\t */\n+\n+\tBUG_ON(idx > ARRAY_SIZE(dev->tx_ring));\n+\n+\tif (mtk_wed_ring_alloc(dev, ring, MTK_WED_TX_RING_SIZE))\n+\t\treturn -ENOMEM;\n+\n+\tif (mtk_wed_wdma_ring_setup(dev, idx, MTK_WED_WDMA_RING_SIZE))\n+\t\treturn -ENOMEM;\n+\n+\tring->reg_base = MTK_WED_RING_TX(idx);\n+\tring->wpdma = regs;\n+\n+\t/* WED -> WPDMA */\n+\twpdma_tx_w32(dev, idx, MTK_WED_RING_OFS_BASE, ring->desc_phys);\n+\twpdma_tx_w32(dev, idx, MTK_WED_RING_OFS_COUNT, MTK_WED_TX_RING_SIZE);\n+\twpdma_tx_w32(dev, idx, MTK_WED_RING_OFS_CPU_IDX, 0);\n+\n+\twed_w32(dev, MTK_WED_WPDMA_RING_TX(idx) + MTK_WED_RING_OFS_BASE,\n+\t\tring->desc_phys);\n+\twed_w32(dev, MTK_WED_WPDMA_RING_TX(idx) + MTK_WED_RING_OFS_COUNT,\n+\t\tMTK_WED_TX_RING_SIZE);\n+\twed_w32(dev, MTK_WED_WPDMA_RING_TX(idx) + MTK_WED_RING_OFS_CPU_IDX, 0);\n+\n+\treturn 0;\n+}\n+\n+static int\n+mtk_wed_txfree_ring_setup(struct mtk_wed_device *dev, void __iomem *regs)\n+{\n+\tstruct mtk_wed_ring *ring = &dev->txfree_ring;\n+\tint i;\n+\n+\t/*\n+\t * For txfree event handling, the same DMA ring is shared between WED\n+\t * and WLAN. The WLAN driver accesses the ring index registers through\n+\t * WED\n+\t */\n+\tring->reg_base = MTK_WED_RING_RX(1);\n+\tring->wpdma = regs;\n+\n+\tfor (i = 0; i < 12; i += 4) {\n+\t\tu32 val = readl(regs + i);\n+\n+\t\twed_w32(dev, MTK_WED_RING_RX(1) + i, val);\n+\t\twed_w32(dev, MTK_WED_WPDMA_RING_RX(1) + i, val);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static u32\n+mtk_wed_irq_get(struct mtk_wed_device *dev, u32 mask)\n+{\n+\tu32 val;\n+\n+\tval = wed_r32(dev, MTK_WED_EXT_INT_STATUS);\n+\twed_w32(dev, MTK_WED_EXT_INT_STATUS, val);\n+\tval &= MTK_WED_EXT_INT_STATUS_ERROR_MASK;\n+\tif (!dev->hw->num_flows)\n+\t\tval &= ~MTK_WED_EXT_INT_STATUS_TKID_WO_PYLD;\n+\tif (val && net_ratelimit())\n+\t\tpr_err(\"mtk_wed%d: error status=%08x\\n\", dev->hw->index, val);\n+\n+\tval = wed_r32(dev, MTK_WED_INT_STATUS);\n+\tval &= mask;\n+\twed_w32(dev, MTK_WED_INT_STATUS, val); /* ACK */\n+\n+\treturn val;\n+}\n+\n+static void\n+mtk_wed_irq_set_mask(struct mtk_wed_device *dev, u32 mask)\n+{\n+\tif (!dev->running)\n+\t\treturn;\n+\n+\tmtk_wed_set_ext_int(dev, !!mask);\n+\twed_w32(dev, MTK_WED_INT_MASK, mask);\n+}\n+\n+int mtk_wed_flow_add(int index)\n+{\n+\tstruct mtk_wed_hw *hw = hw_list[index];\n+\tint ret;\n+\n+\tif (!hw || !hw->wed_dev)\n+\t\treturn -ENODEV;\n+\n+\tif (hw->num_flows) {\n+\t\thw->num_flows++;\n+\t\treturn 0;\n+\t}\n+\n+\tmutex_lock(&hw_lock);\n+\tif (!hw->wed_dev) {\n+\t\tret = -ENODEV;\n+\t\tgoto out;\n+\t}\n+\n+\tret = hw->wed_dev->wlan.offload_enable(hw->wed_dev);\n+\tif (!ret)\n+\t\thw->num_flows++;\n+\tmtk_wed_set_ext_int(hw->wed_dev, true);\n+\n+out:\n+\tmutex_unlock(&hw_lock);\n+\n+\treturn ret;\n+}\n+\n+void mtk_wed_flow_remove(int index)\n+{\n+\tstruct mtk_wed_hw *hw = hw_list[index];\n+\n+\tif (!hw)\n+\t\treturn;\n+\n+\tif (--hw->num_flows)\n+\t\treturn;\n+\n+\tmutex_lock(&hw_lock);\n+\tif (!hw->wed_dev)\n+\t\tgoto out;\n+\n+\thw->wed_dev->wlan.offload_disable(hw->wed_dev);\n+\tmtk_wed_set_ext_int(hw->wed_dev, true);\n+\n+out:\n+\tmutex_unlock(&hw_lock);\n+}\n+\n+void mtk_wed_add_hw(struct device_node *np, struct mtk_eth *eth,\n+\t\t    void __iomem *wdma, int index)\n+{\n+\tstatic const struct mtk_wed_ops wed_ops = {\n+\t\t.attach = mtk_wed_attach,\n+\t\t.tx_ring_setup = mtk_wed_tx_ring_setup,\n+\t\t.txfree_ring_setup = mtk_wed_txfree_ring_setup,\n+\t\t.start = mtk_wed_start,\n+\t\t.stop = mtk_wed_stop,\n+\t\t.reset_dma = mtk_wed_reset_dma,\n+\t\t.reg_read = wed_r32,\n+\t\t.reg_write = wed_w32,\n+\t\t.irq_get = mtk_wed_irq_get,\n+\t\t.irq_set_mask = mtk_wed_irq_set_mask,\n+\t\t.detach = mtk_wed_detach,\n+\t};\n+\tstruct device_node *eth_np = eth->dev->of_node;\n+\tstruct platform_device *pdev;\n+\tstruct mtk_wed_hw *hw;\n+\tstruct regmap *regs;\n+\tint irq;\n+\n+\tif (!np)\n+\t\treturn;\n+\n+\tpdev = of_find_device_by_node(np);\n+\tif (!pdev)\n+\t\treturn;\n+\n+\tget_device(&pdev->dev);\n+\tirq = platform_get_irq(pdev, 0);\n+\tif (irq < 0)\n+\t\treturn;\n+\n+\tregs = syscon_regmap_lookup_by_phandle(np, NULL);\n+\tif (!regs)\n+\t\treturn;\n+\n+\trcu_assign_pointer(mtk_soc_wed_ops, &wed_ops);\n+\n+\tmutex_lock(&hw_lock);\n+\n+\tif (WARN_ON(hw_list[index]))\n+\t\tgoto unlock;\n+\n+\thw = kzalloc(sizeof(*hw), GFP_KERNEL);\n+\thw->node = np;\n+\thw->regs = regs;\n+\thw->eth = eth;\n+\thw->dev = &pdev->dev;\n+\thw->wdma = wdma;\n+\thw->index = index;\n+\thw->irq = irq;\n+\thw->mirror = syscon_regmap_lookup_by_phandle(eth_np,\n+\t\t\t\t\t\t     \"mediatek,pcie-mirror\");\n+\thw->hifsys = syscon_regmap_lookup_by_phandle(eth_np,\n+\t\t\t\t\t\t     \"mediatek,hifsys\");\n+\tif (IS_ERR(hw->mirror) || IS_ERR(hw->hifsys)) {\n+\t\tkfree(hw);\n+\t\tgoto unlock;\n+\t}\n+\n+\tif (!index) {\n+\t\tregmap_write(hw->mirror, 0, 0);\n+\t\tregmap_write(hw->mirror, 4, 0);\n+\t}\n+\tmtk_wed_hw_add_debugfs(hw);\n+\n+\thw_list[index] = hw;\n+\n+unlock:\n+\tmutex_unlock(&hw_lock);\n+}\n+\n+void mtk_wed_exit(void)\n+{\n+\tint i;\n+\n+\trcu_assign_pointer(mtk_soc_wed_ops, NULL);\n+\n+\tsynchronize_rcu();\n+\n+\tfor (i = 0; i < ARRAY_SIZE(hw_list); i++) {\n+\t\tstruct mtk_wed_hw *hw;\n+\n+\t\thw = hw_list[i];\n+\t\tif (!hw)\n+\t\t\tcontinue;\n+\n+\t\thw_list[i] = NULL;\n+\t\tdebugfs_remove(hw->debugfs_dir);\n+\t\tput_device(hw->dev);\n+\t\tkfree(hw);\n+\t}\n+}\n--- /dev/null\n+++ b/drivers/net/ethernet/mediatek/mtk_wed.h\n@@ -0,0 +1,128 @@\n+// SPDX-License-Identifier: GPL-2.0-only\n+/* Copyright (C) 2021 Felix Fietkau <nbd@nbd.name> */\n+\n+#ifndef __MTK_WED_PRIV_H\n+#define __MTK_WED_PRIV_H\n+\n+#include <linux/soc/mediatek/mtk_wed.h>\n+#include <linux/debugfs.h>\n+#include <linux/regmap.h>\n+\n+struct mtk_eth;\n+\n+struct mtk_wed_hw {\n+\tstruct device_node *node;\n+\tstruct mtk_eth *eth;\n+\tstruct regmap *regs;\n+\tstruct regmap *hifsys;\n+\tstruct device *dev;\n+\tvoid __iomem *wdma;\n+\tstruct regmap *mirror;\n+\tstruct dentry *debugfs_dir;\n+\tstruct mtk_wed_device *wed_dev;\n+\tu32 debugfs_reg;\n+\tu32 num_flows;\n+\tchar dirname[5];\n+\tint irq;\n+\tint index;\n+};\n+\n+\n+#ifdef CONFIG_NET_MEDIATEK_SOC_WED\n+static inline void\n+wed_w32(struct mtk_wed_device *dev, u32 reg, u32 val)\n+{\n+\tregmap_write(dev->hw->regs, reg, val);\n+}\n+\n+static inline u32\n+wed_r32(struct mtk_wed_device *dev, u32 reg)\n+{\n+\tunsigned int val;\n+\n+\tregmap_read(dev->hw->regs, reg, &val);\n+\n+\treturn val;\n+}\n+\n+static inline void\n+wdma_w32(struct mtk_wed_device *dev, u32 reg, u32 val)\n+{\n+\twritel(val, dev->hw->wdma + reg);\n+}\n+\n+static inline u32\n+wdma_r32(struct mtk_wed_device *dev, u32 reg)\n+{\n+\treturn readl(dev->hw->wdma + reg);\n+}\n+\n+static inline u32\n+wpdma_tx_r32(struct mtk_wed_device *dev, int ring, u32 reg)\n+{\n+\tif (!dev->tx_ring[ring].wpdma)\n+\t\treturn 0;\n+\n+\treturn readl(dev->tx_ring[ring].wpdma + reg);\n+}\n+\n+static inline void\n+wpdma_tx_w32(struct mtk_wed_device *dev, int ring, u32 reg, u32 val)\n+{\n+\tif (!dev->tx_ring[ring].wpdma)\n+\t\treturn;\n+\n+\twritel(val, dev->tx_ring[ring].wpdma + reg);\n+}\n+\n+static inline u32\n+wpdma_txfree_r32(struct mtk_wed_device *dev, u32 reg)\n+{\n+\tif (!dev->txfree_ring.wpdma)\n+\t\treturn 0;\n+\n+\treturn readl(dev->txfree_ring.wpdma + reg);\n+}\n+\n+static inline void\n+wpdma_txfree_w32(struct mtk_wed_device *dev, u32 reg, u32 val)\n+{\n+\tif (!dev->txfree_ring.wpdma)\n+\t\treturn;\n+\n+\twritel(val, dev->txfree_ring.wpdma + reg);\n+}\n+\n+void mtk_wed_add_hw(struct device_node *np, struct mtk_eth *eth,\n+\t\t    void __iomem *wdma, int index);\n+void mtk_wed_exit(void);\n+int mtk_wed_flow_add(int index);\n+void mtk_wed_flow_remove(int index);\n+#else\n+static inline void\n+mtk_wed_add_hw(struct device_node *np, struct mtk_eth *eth,\n+\t       void __iomem *wdma, int index)\n+{\n+}\n+static inline void\n+mtk_wed_exit(void)\n+{\n+}\n+static inline int mtk_wed_flow_add(int index)\n+{\n+\treturn -EINVAL;\n+}\n+static inline void mtk_wed_flow_remove(int index)\n+{\n+}\n+#endif\n+\n+#ifdef CONFIG_DEBUG_FS\n+void mtk_wed_hw_add_debugfs(struct mtk_wed_hw *hw);\n+#else\n+static inline void mtk_wed_hw_add_debugfs(struct mtk_wed_hw *hw)\n+{\n+}\n+#endif\n+\n+#endif\n--- /dev/null\n+++ b/drivers/net/ethernet/mediatek/mtk_wed_debugfs.c\n@@ -0,0 +1,175 @@\n+// SPDX-License-Identifier: GPL-2.0-only\n+/* Copyright (C) 2021 Felix Fietkau <nbd@nbd.name> */\n+\n+#include <linux/seq_file.h>\n+#include \"mtk_wed.h\"\n+#include \"mtk_wed_regs.h\"\n+\n+struct reg_dump {\n+\tconst char *name;\n+\tu16 offset;\n+\tu8 type;\n+\tu8 base;\n+};\n+\n+enum {\n+\tDUMP_TYPE_STRING,\n+\tDUMP_TYPE_WED,\n+\tDUMP_TYPE_WDMA,\n+\tDUMP_TYPE_WPDMA_TX,\n+\tDUMP_TYPE_WPDMA_TXFREE,\n+};\n+\n+#define DUMP_STR(_str) { _str, 0, DUMP_TYPE_STRING }\n+#define DUMP_REG(_reg, ...) { #_reg, MTK_##_reg, __VA_ARGS__ }\n+#define DUMP_RING(_prefix, _base, ...)\t\t\t\t\\\n+\t{ _prefix \" BASE\", _base, __VA_ARGS__ },\t\t\\\n+\t{ _prefix \" CNT\",  _base + 0x4, __VA_ARGS__ },\t\\\n+\t{ _prefix \" CIDX\", _base + 0x8, __VA_ARGS__ },\t\\\n+\t{ _prefix \" DIDX\", _base + 0xc, __VA_ARGS__ }\n+\n+#define DUMP_WED(_reg) DUMP_REG(_reg, DUMP_TYPE_WED)\n+#define DUMP_WED_RING(_base) DUMP_RING(#_base, MTK_##_base, DUMP_TYPE_WED)\n+\n+#define DUMP_WDMA(_reg) DUMP_REG(_reg, DUMP_TYPE_WDMA)\n+#define DUMP_WDMA_RING(_base) DUMP_RING(#_base, MTK_##_base, DUMP_TYPE_WDMA)\n+\n+#define DUMP_WPDMA_TX_RING(_n) DUMP_RING(\"WPDMA_TX\" #_n, 0, DUMP_TYPE_WPDMA_TX, _n)\n+#define DUMP_WPDMA_TXFREE_RING DUMP_RING(\"WPDMA_RX1\", 0, DUMP_TYPE_WPDMA_TXFREE)\n+\n+static void\n+print_reg_val(struct seq_file *s, const char *name, u32 val)\n+{\n+\tseq_printf(s, \"%-32s %08x\\n\", name, val);\n+}\n+\n+static void\n+dump_wed_regs(struct seq_file *s, struct mtk_wed_device *dev,\n+\t      const struct reg_dump *regs, int n_regs)\n+{\n+\tconst struct reg_dump *cur;\n+\tu32 val;\n+\n+\tfor (cur = regs; cur < &regs[n_regs]; cur++) {\n+\t\tswitch (cur->type) {\n+\t\tcase DUMP_TYPE_STRING:\n+\t\t\tseq_printf(s, \"%s======== %s:\\n\",\n+\t\t\t\t   cur > regs ? \"\\n\" : \"\",\n+\t\t\t\t   cur->name);\n+\t\t\tcontinue;\n+\t\tcase DUMP_TYPE_WED:\n+\t\t\tval = wed_r32(dev, cur->offset);\n+\t\t\tbreak;\n+\t\tcase DUMP_TYPE_WDMA:\n+\t\t\tval = wdma_r32(dev, cur->offset);\n+\t\t\tbreak;\n+\t\tcase DUMP_TYPE_WPDMA_TX:\n+\t\t\tval = wpdma_tx_r32(dev, cur->base, cur->offset);\n+\t\t\tbreak;\n+\t\tcase DUMP_TYPE_WPDMA_TXFREE:\n+\t\t\tval = wpdma_txfree_r32(dev, cur->offset);\n+\t\t\tbreak;\n+\t\t}\n+\t\tprint_reg_val(s, cur->name, val);\n+\t}\n+}\n+\n+\n+static int\n+wed_txinfo_show(struct seq_file *s, void *data)\n+{\n+\tstatic const struct reg_dump regs[] = {\n+\t\tDUMP_STR(\"WED TX\"),\n+\t\tDUMP_WED(WED_TX_MIB(0)),\n+\t\tDUMP_WED_RING(WED_RING_TX(0)),\n+\n+\t\tDUMP_WED(WED_TX_MIB(1)),\n+\t\tDUMP_WED_RING(WED_RING_TX(1)),\n+\n+\t\tDUMP_STR(\"WPDMA TX\"),\n+\t\tDUMP_WED(WED_WPDMA_TX_MIB(0)),\n+\t\tDUMP_WED_RING(WED_WPDMA_RING_TX(0)),\n+\t\tDUMP_WED(WED_WPDMA_TX_COHERENT_MIB(0)),\n+\n+\t\tDUMP_WED(WED_WPDMA_TX_MIB(1)),\n+\t\tDUMP_WED_RING(WED_WPDMA_RING_TX(1)),\n+\t\tDUMP_WED(WED_WPDMA_TX_COHERENT_MIB(1)),\n+\n+\t\tDUMP_STR(\"WPDMA TX\"),\n+\t\tDUMP_WPDMA_TX_RING(0),\n+\t\tDUMP_WPDMA_TX_RING(1),\n+\n+\t\tDUMP_STR(\"WED WDMA RX\"),\n+\t\tDUMP_WED(WED_WDMA_RX_MIB(0)),\n+\t\tDUMP_WED_RING(WED_WDMA_RING_RX(0)),\n+\t\tDUMP_WED(WED_WDMA_RX_THRES(0)),\n+\t\tDUMP_WED(WED_WDMA_RX_RECYCLE_MIB(0)),\n+\t\tDUMP_WED(WED_WDMA_RX_PROCESSED_MIB(0)),\n+\n+\t\tDUMP_WED(WED_WDMA_RX_MIB(1)),\n+\t\tDUMP_WED_RING(WED_WDMA_RING_RX(1)),\n+\t\tDUMP_WED(WED_WDMA_RX_THRES(1)),\n+\t\tDUMP_WED(WED_WDMA_RX_RECYCLE_MIB(1)),\n+\t\tDUMP_WED(WED_WDMA_RX_PROCESSED_MIB(1)),\n+\n+\t\tDUMP_STR(\"WDMA RX\"),\n+\t\tDUMP_WDMA(WDMA_GLO_CFG),\n+\t\tDUMP_WDMA_RING(WDMA_RING_RX(0)),\n+\t\tDUMP_WDMA_RING(WDMA_RING_RX(1)),\n+\t};\n+\tstruct mtk_wed_hw *hw = s->private;\n+\tstruct mtk_wed_device *dev = hw->wed_dev;\n+\n+\tif (!dev)\n+\t\treturn 0;\n+\n+\tdump_wed_regs(s, dev, regs, ARRAY_SIZE(regs));\n+\n+\treturn 0;\n+}\n+DEFINE_SHOW_ATTRIBUTE(wed_txinfo);\n+\n+\n+static int\n+mtk_wed_reg_set(void *data, u64 val)\n+{\n+\tstruct mtk_wed_hw *hw = data;\n+\n+\tregmap_write(hw->regs, hw->debugfs_reg, val);\n+\n+\treturn 0;\n+}\n+\n+static int\n+mtk_wed_reg_get(void *data, u64 *val)\n+{\n+\tstruct mtk_wed_hw *hw = data;\n+\tunsigned int regval;\n+\tint ret;\n+\n+\tret = regmap_read(hw->regs, hw->debugfs_reg, &regval);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\t*val = regval;\n+\n+\treturn 0;\n+}\n+\n+DEFINE_DEBUGFS_ATTRIBUTE(fops_regval, mtk_wed_reg_get, mtk_wed_reg_set,\n+             \"0x%08llx\\n\");\n+\n+void mtk_wed_hw_add_debugfs(struct mtk_wed_hw *hw)\n+{\n+\tstruct dentry *dir;\n+\n+\tsnprintf(hw->dirname, sizeof(hw->dirname), \"wed%d\", hw->index);\n+\tdir = debugfs_create_dir(hw->dirname, NULL);\n+\tif (!dir)\n+\t\treturn;\n+\n+\thw->debugfs_dir = dir;\n+\tdebugfs_create_u32(\"regidx\", 0600, dir, &hw->debugfs_reg);\n+\tdebugfs_create_file_unsafe(\"regval\", 0600, dir, hw, &fops_regval);\n+\tdebugfs_create_file_unsafe(\"txinfo\", 0400, dir, hw, &wed_txinfo_fops);\n+}\n--- /dev/null\n+++ b/drivers/net/ethernet/mediatek/mtk_wed_ops.c\n@@ -0,0 +1,8 @@\n+// SPDX-License-Identifier: GPL-2.0-only\n+/* Copyright (C) 2020 Felix Fietkau <nbd@nbd.name> */\n+\n+#include <linux/kernel.h>\n+#include <linux/soc/mediatek/mtk_wed.h>\n+\n+const struct mtk_wed_ops __rcu *mtk_soc_wed_ops;\n+EXPORT_SYMBOL_GPL(mtk_soc_wed_ops);\n--- /dev/null\n+++ b/drivers/net/ethernet/mediatek/mtk_wed_regs.h\n@@ -0,0 +1,251 @@\n+// SPDX-License-Identifier: GPL-2.0-only\n+/* Copyright (C) 2020 Felix Fietkau <nbd@nbd.name> */\n+\n+#ifndef __MTK_WED_REGS_H\n+#define __MTK_WED_REGS_H\n+\n+#define MTK_WDMA_DESC_CTRL_LEN1\t\t\tGENMASK(14, 0)\n+#define MTK_WDMA_DESC_CTRL_LAST_SEG1\t\tBIT(15)\n+#define MTK_WDMA_DESC_CTRL_BURST\t\tBIT(16)\n+#define MTK_WDMA_DESC_CTRL_LEN0\t\t\tGENMASK(29, 16)\n+#define MTK_WDMA_DESC_CTRL_LAST_SEG0\t\tBIT(30)\n+#define MTK_WDMA_DESC_CTRL_DMA_DONE\t\tBIT(31)\n+\n+struct mtk_wdma_desc {\n+\t__le32 buf0;\n+\t__le32 ctrl;\n+\t__le32 buf1;\n+\t__le32 info;\n+} __packed __aligned(4);\n+\n+#define MTK_WED_RESET\t\t\t\t\t0x008\n+#define MTK_WED_RESET_TX_BM\t\t\t\tBIT(0)\n+#define MTK_WED_RESET_TX_FREE_AGENT\t\t\tBIT(4)\n+#define MTK_WED_RESET_WPDMA_TX_DRV\t\t\tBIT(8)\n+#define MTK_WED_RESET_WPDMA_RX_DRV\t\t\tBIT(9)\n+#define MTK_WED_RESET_WPDMA_INT_AGENT\t\t\tBIT(11)\n+#define MTK_WED_RESET_WED_TX_DMA\t\t\tBIT(12)\n+#define MTK_WED_RESET_WDMA_RX_DRV\t\t\tBIT(17)\n+#define MTK_WED_RESET_WDMA_INT_AGENT\t\t\tBIT(19)\n+#define MTK_WED_RESET_WED\t\t\t\tBIT(31)\n+\n+#define MTK_WED_CTRL\t\t\t\t\t0x00c\n+#define MTK_WED_CTRL_WPDMA_INT_AGENT_EN\t\t\tBIT(0)\n+#define MTK_WED_CTRL_WPDMA_INT_AGENT_BUSY\t\tBIT(1)\n+#define MTK_WED_CTRL_WDMA_INT_AGENT_EN\t\t\tBIT(2)\n+#define MTK_WED_CTRL_WDMA_INT_AGENT_BUSY\t\tBIT(3)\n+#define MTK_WED_CTRL_WED_TX_BM_EN\t\t\tBIT(8)\n+#define MTK_WED_CTRL_WED_TX_BM_BUSY\t\t\tBIT(9)\n+#define MTK_WED_CTRL_WED_TX_FREE_AGENT_EN\t\tBIT(10)\n+#define MTK_WED_CTRL_WED_TX_FREE_AGENT_BUSY\t\tBIT(11)\n+#define MTK_WED_CTRL_RESERVE_EN\t\t\t\tBIT(12)\n+#define MTK_WED_CTRL_RESERVE_BUSY\t\t\tBIT(13)\n+#define MTK_WED_CTRL_FINAL_DIDX_READ\t\t\tBIT(24)\n+#define MTK_WED_CTRL_MIB_READ_CLEAR\t\t\tBIT(28)\n+\n+#define MTK_WED_EXT_INT_STATUS\t\t\t\t0x020\n+#define MTK_WED_EXT_INT_STATUS_TF_LEN_ERR\t\tBIT(0)\n+#define MTK_WED_EXT_INT_STATUS_TKID_WO_PYLD\t\tBIT(1)\n+#define MTK_WED_EXT_INT_STATUS_TKID_TITO_INVALID\tBIT(4)\n+#define MTK_WED_EXT_INT_STATUS_TX_FBUF_LO_TH\t\tBIT(8)\n+#define MTK_WED_EXT_INT_STATUS_TX_FBUF_HI_TH\t\tBIT(9)\n+#define MTK_WED_EXT_INT_STATUS_RX_FBUF_LO_TH\t\tBIT(12)\n+#define MTK_WED_EXT_INT_STATUS_RX_FBUF_HI_TH\t\tBIT(13)\n+#define MTK_WED_EXT_INT_STATUS_RX_DRV_R_RESP_ERR\tBIT(16)\n+#define MTK_WED_EXT_INT_STATUS_RX_DRV_W_RESP_ERR\tBIT(17)\n+#define MTK_WED_EXT_INT_STATUS_RX_DRV_COHERENT\t\tBIT(18)\n+#define MTK_WED_EXT_INT_STATUS_RX_DRV_INIT_WDMA_EN\tBIT(19)\n+#define MTK_WED_EXT_INT_STATUS_RX_DRV_BM_DMAD_COHERENT\tBIT(20)\n+#define MTK_WED_EXT_INT_STATUS_TX_DRV_R_RESP_ERR\tBIT(21)\n+#define MTK_WED_EXT_INT_STATUS_TX_DRV_W_RESP_ERR\tBIT(22)\n+#define MTK_WED_EXT_INT_STATUS_RX_DRV_DMA_RECYCLE\tBIT(24)\n+#define MTK_WED_EXT_INT_STATUS_ERROR_MASK\t\t(MTK_WED_EXT_INT_STATUS_TF_LEN_ERR | \\\n+\t\t\t\t\t\t\t MTK_WED_EXT_INT_STATUS_TKID_WO_PYLD | \\\n+\t\t\t\t\t\t\t MTK_WED_EXT_INT_STATUS_TKID_TITO_INVALID | \\\n+\t\t\t\t\t\t\t MTK_WED_EXT_INT_STATUS_RX_DRV_R_RESP_ERR | \\\n+\t\t\t\t\t\t\t MTK_WED_EXT_INT_STATUS_RX_DRV_W_RESP_ERR | \\\n+\t\t\t\t\t\t\t MTK_WED_EXT_INT_STATUS_RX_DRV_INIT_WDMA_EN | \\\n+\t\t\t\t\t\t\t MTK_WED_EXT_INT_STATUS_TX_DRV_R_RESP_ERR | \\\n+\t\t\t\t\t\t\t MTK_WED_EXT_INT_STATUS_TX_DRV_W_RESP_ERR)\n+\n+#define MTK_WED_EXT_INT_MASK\t\t\t\t0x028\n+\n+#define MTK_WED_STATUS\t\t\t\t\t0x060\n+#define MTK_WED_STATUS_TX\t\t\t\tGENMASK(15, 8)\n+\n+#define MTK_WED_TX_BM_CTRL\t\t\t\t0x080\n+#define MTK_WED_TX_BM_CTRL_VLD_GRP_NUM\t\t\tGENMASK(6, 0)\n+#define MTK_WED_TX_BM_CTRL_RSV_GRP_NUM\t\t\tGENMASK(22, 16)\n+#define MTK_WED_TX_BM_CTRL_PAUSE\t\t\tBIT(28)\n+\n+#define MTK_WED_TX_BM_BASE\t\t\t\t0x084\n+\n+#define MTK_WED_TX_BM_TKID\t\t\t\t0x088\n+#define MTK_WED_TX_BM_TKID_START\t\t\tGENMASK(15, 0)\n+#define MTK_WED_TX_BM_TKID_END\t\t\t\tGENMASK(31, 16)\n+\n+#define MTK_WED_TX_BM_BUF_LEN\t\t\t\t0x08c\n+\n+#define MTK_WED_TX_BM_INTF\t\t\t\t0x09c\n+#define MTK_WED_TX_BM_INTF_TKID\t\t\t\tGENMASK(15, 0)\n+#define MTK_WED_TX_BM_INTF_TKFIFO_FDEP\t\t\tGENMASK(23, 16)\n+#define MTK_WED_TX_BM_INTF_TKID_VALID\t\t\tBIT(28)\n+#define MTK_WED_TX_BM_INTF_TKID_READ\t\t\tBIT(29)\n+\n+#define MTK_WED_TX_BM_DYN_THR\t\t\t\t0x0a0\n+#define MTK_WED_TX_BM_DYN_THR_LO\t\t\tGENMASK(6, 0)\n+#define MTK_WED_TX_BM_DYN_THR_HI\t\t\tGENMASK(22, 16)\n+\n+#define MTK_WED_INT_STATUS\t\t\t\t0x200\n+#define MTK_WED_INT_MASK\t\t\t\t0x204\n+\n+#define MTK_WED_GLO_CFG\t\t\t\t\t0x208\n+#define MTK_WED_GLO_CFG_TX_DMA_EN\t\t\tBIT(0)\n+#define MTK_WED_GLO_CFG_TX_DMA_BUSY\t\t\tBIT(1)\n+#define MTK_WED_GLO_CFG_RX_DMA_EN\t\t\tBIT(2)\n+#define MTK_WED_GLO_CFG_RX_DMA_BUSY\t\t\tBIT(3)\n+#define MTK_WED_GLO_CFG_RX_BT_SIZE\t\t\tGENMASK(5, 4)\n+#define MTK_WED_GLO_CFG_TX_WB_DDONE\t\t\tBIT(6)\n+#define MTK_WED_GLO_CFG_BIG_ENDIAN\t\t\tBIT(7)\n+#define MTK_WED_GLO_CFG_DIS_BT_SIZE_ALIGN\t\tBIT(8)\n+#define MTK_WED_GLO_CFG_TX_BT_SIZE_LO\t\t\tBIT(9)\n+#define MTK_WED_GLO_CFG_MULTI_DMA_EN\t\t\tGENMASK(11, 10)\n+#define MTK_WED_GLO_CFG_FIFO_LITTLE_ENDIAN\t\tBIT(12)\n+#define MTK_WED_GLO_CFG_MI_DEPTH_RD\t\t\tGENMASK(21, 13)\n+#define MTK_WED_GLO_CFG_TX_BT_SIZE_HI\t\t\tGENMASK(23, 22)\n+#define MTK_WED_GLO_CFG_SW_RESET\t\t\tBIT(24)\n+#define MTK_WED_GLO_CFG_FIRST_TOKEN_ONLY\t\tBIT(26)\n+#define MTK_WED_GLO_CFG_OMIT_RX_INFO\t\t\tBIT(27)\n+#define MTK_WED_GLO_CFG_OMIT_TX_INFO\t\t\tBIT(28)\n+#define MTK_WED_GLO_CFG_BYTE_SWAP\t\t\tBIT(29)\n+#define MTK_WED_GLO_CFG_RX_2B_OFFSET\t\t\tBIT(31)\n+\n+#define MTK_WED_RESET_IDX\t\t\t\t0x20c\n+#define MTK_WED_RESET_IDX_TX\t\t\t\tGENMASK(3, 0)\n+#define MTK_WED_RESET_IDX_RX\t\t\t\tGENMASK(17, 16)\n+\n+#define MTK_WED_TX_MIB(_n)\t\t\t\t(0x2a0 + (_n) * 4)\n+\n+#define MTK_WED_RING_TX(_n)\t\t\t\t(0x300 + (_n) * 0x10)\n+\n+#define MTK_WED_RING_RX(_n)\t\t\t\t(0x400 + (_n) * 0x10)\n+\n+#define MTK_WED_WPDMA_INT_TRIGGER\t\t\t0x504\n+#define MTK_WED_WPDMA_INT_TRIGGER_RX_DONE\t\tBIT(1)\n+#define MTK_WED_WPDMA_INT_TRIGGER_TX_DONE\t\tGENMASK(5, 4)\n+\n+#define MTK_WED_WPDMA_GLO_CFG\t\t\t\t0x508\n+#define MTK_WED_WPDMA_GLO_CFG_TX_DRV_EN\t\t\tBIT(0)\n+#define MTK_WED_WPDMA_GLO_CFG_TX_DRV_BUSY\t\tBIT(1)\n+#define MTK_WED_WPDMA_GLO_CFG_RX_DRV_EN\t\t\tBIT(2)\n+#define MTK_WED_WPDMA_GLO_CFG_RX_DRV_BUSY\t\tBIT(3)\n+#define MTK_WED_WPDMA_GLO_CFG_RX_BT_SIZE\t\tGENMASK(5, 4)\n+#define MTK_WED_WPDMA_GLO_CFG_TX_WB_DDONE\t\tBIT(6)\n+#define MTK_WED_WPDMA_GLO_CFG_BIG_ENDIAN\t\tBIT(7)\n+#define MTK_WED_WPDMA_GLO_CFG_DIS_BT_SIZE_ALIGN\t\tBIT(8)\n+#define MTK_WED_WPDMA_GLO_CFG_TX_BT_SIZE_LO\t\tBIT(9)\n+#define MTK_WED_WPDMA_GLO_CFG_MULTI_DMA_EN\t\tGENMASK(11, 10)\n+#define MTK_WED_WPDMA_GLO_CFG_FIFO_LITTLE_ENDIAN\tBIT(12)\n+#define MTK_WED_WPDMA_GLO_CFG_MI_DEPTH_RD\t\tGENMASK(21, 13)\n+#define MTK_WED_WPDMA_GLO_CFG_TX_BT_SIZE_HI\t\tGENMASK(23, 22)\n+#define MTK_WED_WPDMA_GLO_CFG_SW_RESET\t\t\tBIT(24)\n+#define MTK_WED_WPDMA_GLO_CFG_FIRST_TOKEN_ONLY\t\tBIT(26)\n+#define MTK_WED_WPDMA_GLO_CFG_OMIT_RX_INFO\t\tBIT(27)\n+#define MTK_WED_WPDMA_GLO_CFG_OMIT_TX_INFO\t\tBIT(28)\n+#define MTK_WED_WPDMA_GLO_CFG_BYTE_SWAP\t\t\tBIT(29)\n+#define MTK_WED_WPDMA_GLO_CFG_RX_2B_OFFSET\t\tBIT(31)\n+\n+#define MTK_WED_WPDMA_RESET_IDX\t\t\t\t0x50c\n+#define MTK_WED_WPDMA_RESET_IDX_TX\t\t\tGENMASK(3, 0)\n+#define MTK_WED_WPDMA_RESET_IDX_RX\t\t\tGENMASK(17, 16)\n+\n+#define MTK_WED_WPDMA_INT_CTRL\t\t\t\t0x520\n+#define MTK_WED_WPDMA_INT_CTRL_SUBRT_ADV\t\tBIT(21)\n+\n+#define MTK_WED_WPDMA_INT_MASK\t\t\t\t0x524\n+\n+#define MTK_WED_PCIE_CFG_BASE\t\t\t\t0x560\n+\n+#define MTK_WED_PCIE_INT_TRIGGER\t\t\t0x570\n+#define MTK_WED_PCIE_INT_TRIGGER_STATUS\t\t\tBIT(16)\n+\n+#define MTK_WED_WPDMA_CFG_BASE\t\t\t\t0x580\n+\n+#define MTK_WED_WPDMA_TX_MIB(_n)\t\t\t(0x5a0 + (_n) * 4)\n+#define MTK_WED_WPDMA_TX_COHERENT_MIB(_n)\t\t(0x5d0 + (_n) * 4)\n+\n+#define MTK_WED_WPDMA_RING_TX(_n)\t\t\t(0x600 + (_n) * 0x10)\n+#define MTK_WED_WPDMA_RING_RX(_n)\t\t\t(0x700 + (_n) * 0x10)\n+#define MTK_WED_WDMA_RING_RX(_n)\t\t\t(0x900 + (_n) * 0x10)\n+#define MTK_WED_WDMA_RX_THRES(_n)\t\t\t(0x940 + (_n) * 0x4)\n+\n+#define MTK_WED_WDMA_GLO_CFG\t\t\t\t0xa04\n+#define MTK_WED_WDMA_GLO_CFG_TX_DRV_EN\t\t\tBIT(0)\n+#define MTK_WED_WDMA_GLO_CFG_RX_DRV_EN\t\t\tBIT(2)\n+#define MTK_WED_WDMA_GLO_CFG_RX_DRV_BUSY\t\tBIT(3)\n+#define MTK_WED_WDMA_GLO_CFG_BT_SIZE\t\t\tGENMASK(5, 4)\n+#define MTK_WED_WDMA_GLO_CFG_TX_WB_DDONE\t\tBIT(6)\n+#define MTK_WED_WDMA_GLO_CFG_RX_DIS_FSM_AUTO_IDLE\tBIT(13)\n+#define MTK_WED_WDMA_GLO_CFG_WCOMPLETE_SEL\t\tBIT(16)\n+#define MTK_WED_WDMA_GLO_CFG_INIT_PHASE_RXDMA_BYPASS\tBIT(17)\n+#define MTK_WED_WDMA_GLO_CFG_INIT_PHASE_BYPASS\t\tBIT(18)\n+#define MTK_WED_WDMA_GLO_CFG_FSM_RETURN_IDLE\t\tBIT(19)\n+#define MTK_WED_WDMA_GLO_CFG_WAIT_COHERENT\t\tBIT(20)\n+#define MTK_WED_WDMA_GLO_CFG_AXI_W_AFTER_AW\t\tBIT(21)\n+#define MTK_WED_WDMA_GLO_CFG_IDLE_DMAD_SUPPLY_SINGLE_W\tBIT(22)\n+#define MTK_WED_WDMA_GLO_CFG_IDLE_DMAD_SUPPLY\t\tBIT(23)\n+#define MTK_WED_WDMA_GLO_CFG_DYNAMIC_SKIP_DMAD_PREP\tBIT(24)\n+#define MTK_WED_WDMA_GLO_CFG_DYNAMIC_DMAD_RECYCLE\tBIT(25)\n+#define MTK_WED_WDMA_GLO_CFG_RST_INIT_COMPLETE\t\tBIT(26)\n+#define MTK_WED_WDMA_GLO_CFG_RXDRV_CLKGATE_BYPASS\tBIT(30)\n+\n+#define MTK_WED_WDMA_RESET_IDX\t\t\t\t0xa08\n+#define MTK_WED_WDMA_RESET_IDX_RX\t\t\tGENMASK(17, 16)\n+#define MTK_WED_WDMA_RESET_IDX_DRV\t\t\tGENMASK(25, 24)\n+\n+#define MTK_WED_WDMA_INT_TRIGGER\t\t\t0xa28\n+#define MTK_WED_WDMA_INT_TRIGGER_RX_DONE\t\tGENMASK(17, 16)\n+\n+#define MTK_WED_WDMA_INT_CTRL\t\t\t\t0xa2c\n+#define MTK_WED_WDMA_INT_CTRL_POLL_SRC_SEL\t\tGENMASK(17, 16)\n+\n+#define MTK_WED_WDMA_OFFSET0\t\t\t\t0xaa4\n+#define MTK_WED_WDMA_OFFSET1\t\t\t\t0xaa8\n+\n+#define MTK_WED_WDMA_RX_MIB(_n)\t\t\t\t(0xae0 + (_n) * 4)\n+#define MTK_WED_WDMA_RX_RECYCLE_MIB(_n)\t\t\t(0xae8 + (_n) * 4)\n+#define MTK_WED_WDMA_RX_PROCESSED_MIB(_n)\t\t(0xaf0 + (_n) * 4)\n+\n+#define MTK_WED_RING_OFS_BASE\t\t\t\t0x00\n+#define MTK_WED_RING_OFS_COUNT\t\t\t\t0x04\n+#define MTK_WED_RING_OFS_CPU_IDX\t\t\t0x08\n+#define MTK_WED_RING_OFS_DMA_IDX\t\t\t0x0c\n+\n+#define MTK_WDMA_RING_RX(_n)\t\t\t\t(0x100 + (_n) * 0x10)\n+\n+#define MTK_WDMA_GLO_CFG\t\t\t\t0x204\n+#define MTK_WDMA_GLO_CFG_RX_INFO_PRERES\t\t\tGENMASK(28, 26)\n+\n+#define MTK_WDMA_RESET_IDX\t\t\t\t0x208\n+#define MTK_WDMA_RESET_IDX_TX\t\t\t\tGENMASK(3, 0)\n+#define MTK_WDMA_RESET_IDX_RX\t\t\t\tGENMASK(17, 16)\n+\n+#define MTK_WDMA_INT_MASK\t\t\t\t0x228\n+#define MTK_WDMA_INT_MASK_TX_DONE\t\t\tGENMASK(3, 0)\n+#define MTK_WDMA_INT_MASK_RX_DONE\t\t\tGENMASK(17, 16)\n+#define MTK_WDMA_INT_MASK_TX_DELAY\t\t\tBIT(28)\n+#define MTK_WDMA_INT_MASK_TX_COHERENT\t\t\tBIT(29)\n+#define MTK_WDMA_INT_MASK_RX_DELAY\t\t\tBIT(30)\n+#define MTK_WDMA_INT_MASK_RX_COHERENT\t\t\tBIT(31)\n+\n+#define MTK_WDMA_INT_GRP1\t\t\t\t0x250\n+#define MTK_WDMA_INT_GRP2\t\t\t\t0x254\n+\n+#define MTK_PCIE_MIRROR_MAP(n)\t\t\t\t((n) ? 0x4 : 0x0)\n+#define MTK_PCIE_MIRROR_MAP_EN\t\t\t\tBIT(0)\n+#define MTK_PCIE_MIRROR_MAP_WED_ID\t\t\tBIT(1)\n+\n+/* DMA channel mapping */\n+#define HIFSYS_DMA_AG_MAP\t\t\t\t0x008\n+\n+#endif\n--- /dev/null\n+++ b/include/linux/soc/mediatek/mtk_wed.h\n@@ -0,0 +1,131 @@\n+#ifndef __MTK_WED_H\n+#define __MTK_WED_H\n+\n+#include <linux/kernel.h>\n+#include <linux/rcupdate.h>\n+#include <linux/regmap.h>\n+#include <linux/pci.h>\n+\n+#define MTK_WED_TX_QUEUES\t\t2\n+\n+struct mtk_wed_hw;\n+struct mtk_wdma_desc;\n+\n+struct mtk_wed_ring {\n+\tstruct mtk_wdma_desc *desc;\n+\tdma_addr_t desc_phys;\n+\tint size;\n+\n+\tu32 reg_base;\n+\tvoid __iomem *wpdma;\n+};\n+\n+struct mtk_wed_device {\n+#ifdef CONFIG_NET_MEDIATEK_SOC_WED\n+\tconst struct mtk_wed_ops *ops;\n+\tstruct device *dev;\n+\tstruct mtk_wed_hw *hw;\n+\tbool init_done, running;\n+\tint wdma_idx;\n+\tint irq;\n+\n+\tstruct mtk_wed_ring tx_ring[MTK_WED_TX_QUEUES];\n+\tstruct mtk_wed_ring txfree_ring;\n+\tstruct mtk_wed_ring tx_wdma[MTK_WED_TX_QUEUES];\n+\n+\tstruct {\n+\t\tint size;\n+\t\tvoid **pages;\n+\t\tstruct mtk_wdma_desc *desc;\n+\t\tdma_addr_t desc_phys;\n+\t} buf_ring;\n+\n+\t/* filled by driver: */\n+\tstruct {\n+\t\tstruct pci_dev *pci_dev;\n+\n+\t\tu32 wpdma_phys;\n+\n+\t\tu16 token_start;\n+\t\tunsigned int nbuf;\n+\n+\t\tu32 (*init_buf)(void *ptr, dma_addr_t phys, int token_id);\n+\t\tint (*offload_enable)(struct mtk_wed_device *wed);\n+\t\tvoid (*offload_disable)(struct mtk_wed_device *wed);\n+\t} wlan;\n+#endif\n+};\n+\n+struct mtk_wed_ops {\n+\tint (*attach)(struct mtk_wed_device *dev);\n+\tint (*tx_ring_setup)(struct mtk_wed_device *dev, int ring,\n+\t\t\t     void __iomem *regs);\n+\tint (*txfree_ring_setup)(struct mtk_wed_device *dev,\n+\t\t\t\t void __iomem *regs);\n+\tvoid (*detach)(struct mtk_wed_device *dev);\n+\n+\tvoid (*stop)(struct mtk_wed_device *dev);\n+\tvoid (*start)(struct mtk_wed_device *dev, u32 irq_mask);\n+\tvoid (*reset_dma)(struct mtk_wed_device *dev);\n+\n+\tu32 (*reg_read)(struct mtk_wed_device *dev, u32 reg);\n+\tvoid (*reg_write)(struct mtk_wed_device *dev, u32 reg, u32 val);\n+\n+\tu32 (*irq_get)(struct mtk_wed_device *dev, u32 mask);\n+\tvoid (*irq_set_mask)(struct mtk_wed_device *dev, u32 mask);\n+};\n+\n+extern const struct mtk_wed_ops __rcu *mtk_soc_wed_ops;\n+\n+static inline int\n+mtk_wed_device_attach(struct mtk_wed_device *dev)\n+{\n+\tint ret = -ENODEV;\n+\n+#ifdef CONFIG_NET_MEDIATEK_SOC_WED\n+\trcu_read_lock();\n+\tdev->ops = rcu_dereference(mtk_soc_wed_ops);\n+\tif (dev->ops)\n+\t\tret = dev->ops->attach(dev);\n+\telse\n+\t\trcu_read_unlock();\n+\n+\tif (ret)\n+\t\tdev->ops = NULL;\n+#endif\n+\n+\treturn ret;\n+}\n+\n+#ifdef CONFIG_NET_MEDIATEK_SOC_WED\n+#define mtk_wed_device_active(_dev) !!(_dev)->ops\n+#define mtk_wed_device_detach(_dev) (_dev)->ops->detach(_dev)\n+#define mtk_wed_device_start(_dev, _mask) (_dev)->ops->start(_dev, _mask)\n+#define mtk_wed_device_tx_ring_setup(_dev, _ring, _regs) \\\n+\t(_dev)->ops->tx_ring_setup(_dev, _ring, _regs)\n+#define mtk_wed_device_txfree_ring_setup(_dev, _regs) \\\n+\t(_dev)->ops->txfree_ring_setup(_dev, _regs)\n+#define mtk_wed_device_reg_read(_dev, _reg) \\\n+\t(_dev)->ops->reg_read(_dev, _reg)\n+#define mtk_wed_device_reg_write(_dev, _reg, _val) \\\n+\t(_dev)->ops->reg_write(_dev, _reg, _val)\n+#define mtk_wed_device_irq_get(_dev, _mask) \\\n+\t(_dev)->ops->irq_get(_dev, _mask)\n+#define mtk_wed_device_irq_set_mask(_dev, _mask) \\\n+\t(_dev)->ops->irq_set_mask(_dev, _mask)\n+#else\n+static inline bool mtk_wed_device_active(struct mtk_wed_device *dev)\n+{\n+\treturn false;\n+}\n+#define mtk_wed_device_detach(_dev) do {} while (0)\n+#define mtk_wed_device_start(_dev, _mask) do {} while (0)\n+#define mtk_wed_device_tx_ring_setup(_dev, _ring, _regs) -ENODEV\n+#define mtk_wed_device_txfree_ring_setup(_dev, _ring, _regs) -ENODEV\n+#define mtk_wed_device_reg_read(_dev, _reg) 0\n+#define mtk_wed_device_reg_write(_dev, _reg, _val) do {} while (0)\n+#define mtk_wed_device_irq_get(_dev, _mask) 0\n+#define mtk_wed_device_irq_set_mask(_dev, _mask) do {} while (0)\n+#endif\n+\n+#endif\n"
  },
  {
    "path": "target/linux/generic/pending-5.15/701-03-net-ethernet-mtk_eth_soc-implement-flow-offloading-t.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nDate: Sat, 5 Feb 2022 18:29:22 +0100\nSubject: [PATCH] net: ethernet: mtk_eth_soc: implement flow offloading\n to WED devices\n\nThis allows hardware flow offloading from Ethernet to WLAN on MT7622 SoC\n\nCo-developed-by: Lorenzo Bianconi <lorenzo@kernel.org>\nSigned-off-by: Lorenzo Bianconi <lorenzo@kernel.org>\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n\n--- a/drivers/net/ethernet/mediatek/mtk_ppe.c\n+++ b/drivers/net/ethernet/mediatek/mtk_ppe.c\n@@ -329,6 +329,24 @@ int mtk_foe_entry_set_pppoe(struct mtk_f\n \treturn 0;\n }\n \n+int mtk_foe_entry_set_wdma(struct mtk_foe_entry *entry, int wdma_idx, int txq,\n+\t\t\t   int bss, int wcid)\n+{\n+\tstruct mtk_foe_mac_info *l2 = mtk_foe_entry_l2(entry);\n+\tu32 *ib2 = mtk_foe_entry_ib2(entry);\n+\n+\t*ib2 &= ~MTK_FOE_IB2_PORT_MG;\n+\t*ib2 |= MTK_FOE_IB2_WDMA_WINFO;\n+\tif (wdma_idx)\n+\t\t*ib2 |= MTK_FOE_IB2_WDMA_DEVIDX;\n+\n+\tl2->vlan2 = FIELD_PREP(MTK_FOE_VLAN2_WINFO_BSS, bss) |\n+\t\t    FIELD_PREP(MTK_FOE_VLAN2_WINFO_WCID, wcid) |\n+\t\t    FIELD_PREP(MTK_FOE_VLAN2_WINFO_RING, txq);\n+\n+\treturn 0;\n+}\n+\n static inline bool mtk_foe_entry_usable(struct mtk_foe_entry *entry)\n {\n \treturn !(entry->ib1 & MTK_FOE_IB1_STATIC) &&\n--- a/drivers/net/ethernet/mediatek/mtk_ppe.h\n+++ b/drivers/net/ethernet/mediatek/mtk_ppe.h\n@@ -48,9 +48,9 @@ enum {\n #define MTK_FOE_IB2_DEST_PORT\t\tGENMASK(7, 5)\n #define MTK_FOE_IB2_MULTICAST\t\tBIT(8)\n \n-#define MTK_FOE_IB2_WHNAT_QID2\t\tGENMASK(13, 12)\n-#define MTK_FOE_IB2_WHNAT_DEVIDX\tBIT(16)\n-#define MTK_FOE_IB2_WHNAT_NAT\t\tBIT(17)\n+#define MTK_FOE_IB2_WDMA_QID2\t\tGENMASK(13, 12)\n+#define MTK_FOE_IB2_WDMA_DEVIDX\t\tBIT(16)\n+#define MTK_FOE_IB2_WDMA_WINFO\t\tBIT(17)\n \n #define MTK_FOE_IB2_PORT_MG\t\tGENMASK(17, 12)\n \n@@ -58,9 +58,9 @@ enum {\n \n #define MTK_FOE_IB2_DSCP\t\tGENMASK(31, 24)\n \n-#define MTK_FOE_VLAN2_WHNAT_BSS\t\tGEMMASK(5, 0)\n-#define MTK_FOE_VLAN2_WHNAT_WCID\tGENMASK(13, 6)\n-#define MTK_FOE_VLAN2_WHNAT_RING\tGENMASK(15, 14)\n+#define MTK_FOE_VLAN2_WINFO_BSS\t\tGENMASK(5, 0)\n+#define MTK_FOE_VLAN2_WINFO_WCID\tGENMASK(13, 6)\n+#define MTK_FOE_VLAN2_WINFO_RING\tGENMASK(15, 14)\n \n enum {\n \tMTK_FOE_STATE_INVALID,\n@@ -281,6 +281,8 @@ int mtk_foe_entry_set_ipv6_tuple(struct\n int mtk_foe_entry_set_dsa(struct mtk_foe_entry *entry, int port);\n int mtk_foe_entry_set_vlan(struct mtk_foe_entry *entry, int vid);\n int mtk_foe_entry_set_pppoe(struct mtk_foe_entry *entry, int sid);\n+int mtk_foe_entry_set_wdma(struct mtk_foe_entry *entry, int wdma_idx, int txq,\n+\t\t\t   int bss, int wcid);\n int mtk_foe_entry_commit(struct mtk_ppe *ppe, struct mtk_foe_entry *entry,\n \t\t\t u16 timestamp);\n int mtk_ppe_debugfs_init(struct mtk_ppe *ppe);\n--- a/drivers/net/ethernet/mediatek/mtk_ppe_offload.c\n+++ b/drivers/net/ethernet/mediatek/mtk_ppe_offload.c\n@@ -10,6 +10,7 @@\n #include <net/pkt_cls.h>\n #include <net/dsa.h>\n #include \"mtk_eth_soc.h\"\n+#include \"mtk_wed.h\"\n \n struct mtk_flow_data {\n \tstruct ethhdr eth;\n@@ -39,6 +40,7 @@ struct mtk_flow_entry {\n \tstruct rhash_head node;\n \tunsigned long cookie;\n \tu16 hash;\n+\ts8 wed_index;\n };\n \n static const struct rhashtable_params mtk_flow_ht_params = {\n@@ -80,6 +82,35 @@ mtk_flow_offload_mangle_eth(const struct\n \tmemcpy(dest, src, act->mangle.mask ? 2 : 4);\n }\n \n+static int\n+mtk_flow_get_wdma_info(struct net_device *dev, const u8 *addr, struct mtk_wdma_info *info)\n+{\n+\tstruct net_device_path_ctx ctx = {\n+\t\t.dev = dev,\n+\t\t.daddr = addr,\n+\t};\n+\tstruct net_device_path path = {};\n+\n+\tif (!IS_ENABLED(CONFIG_NET_MEDIATEK_SOC_WED))\n+\t\treturn -1;\n+\n+\tif (!dev->netdev_ops->ndo_fill_forward_path)\n+\t\treturn -1;\n+\n+\tif (dev->netdev_ops->ndo_fill_forward_path(&ctx, &path))\n+\t\treturn -1;\n+\n+\tif (path.type != DEV_PATH_MTK_WDMA)\n+\t\treturn -1;\n+\n+\tinfo->wdma_idx = path.mtk_wdma.wdma_idx;\n+\tinfo->queue = path.mtk_wdma.queue;\n+\tinfo->bss = path.mtk_wdma.bss;\n+\tinfo->wcid = path.mtk_wdma.wcid;\n+\n+\treturn 0;\n+}\n+\n \n static int\n mtk_flow_mangle_ports(const struct flow_action_entry *act,\n@@ -149,10 +180,20 @@ mtk_flow_get_dsa_port(struct net_device\n \n static int\n mtk_flow_set_output_device(struct mtk_eth *eth, struct mtk_foe_entry *foe,\n-\t\t\t   struct net_device *dev)\n+\t\t\t   struct net_device *dev, const u8 *dest_mac,\n+\t\t\t   int *wed_index)\n {\n+\tstruct mtk_wdma_info info = {};\n \tint pse_port, dsa_port;\n \n+\tif (mtk_flow_get_wdma_info(dev, dest_mac, &info) == 0) {\n+\t\tmtk_foe_entry_set_wdma(foe, info.wdma_idx, info.queue, info.bss,\n+\t\t\t\t       info.wcid);\n+\t\tpse_port = 3;\n+\t\t*wed_index = info.wdma_idx;\n+\t\tgoto out;\n+\t}\n+\n \tdsa_port = mtk_flow_get_dsa_port(&dev);\n \tif (dsa_port >= 0)\n \t\tmtk_foe_entry_set_dsa(foe, dsa_port);\n@@ -164,6 +205,7 @@ mtk_flow_set_output_device(struct mtk_et\n \telse\n \t\treturn -EOPNOTSUPP;\n \n+out:\n \tmtk_foe_entry_set_pse_port(foe, pse_port);\n \n \treturn 0;\n@@ -179,6 +221,7 @@ mtk_flow_offload_replace(struct mtk_eth\n \tstruct net_device *odev = NULL;\n \tstruct mtk_flow_entry *entry;\n \tint offload_type = 0;\n+\tint wed_index = -1;\n \tu16 addr_type = 0;\n \tu32 timestamp;\n \tu8 l4proto = 0;\n@@ -326,10 +369,14 @@ mtk_flow_offload_replace(struct mtk_eth\n \tif (data.pppoe.num == 1)\n \t\tmtk_foe_entry_set_pppoe(&foe, data.pppoe.sid);\n \n-\terr = mtk_flow_set_output_device(eth, &foe, odev);\n+\terr = mtk_flow_set_output_device(eth, &foe, odev, data.eth.h_dest,\n+\t\t\t\t\t &wed_index);\n \tif (err)\n \t\treturn err;\n \n+\tif (wed_index >= 0 && (err = mtk_wed_flow_add(wed_index)) < 0)\n+\t\treturn err;\n+\n \tentry = kzalloc(sizeof(*entry), GFP_KERNEL);\n \tif (!entry)\n \t\treturn -ENOMEM;\n@@ -343,6 +390,7 @@ mtk_flow_offload_replace(struct mtk_eth\n \t}\n \n \tentry->hash = hash;\n+\tentry->wed_index = wed_index;\n \terr = rhashtable_insert_fast(&eth->flow_table, &entry->node,\n \t\t\t\t     mtk_flow_ht_params);\n \tif (err < 0)\n@@ -353,6 +401,8 @@ clear_flow:\n \tmtk_foe_entry_clear(&eth->ppe, hash);\n free:\n \tkfree(entry);\n+\tif (wed_index >= 0)\n+\t    mtk_wed_flow_remove(wed_index);\n \treturn err;\n }\n \n@@ -369,6 +419,8 @@ mtk_flow_offload_destroy(struct mtk_eth\n \tmtk_foe_entry_clear(&eth->ppe, entry->hash);\n \trhashtable_remove_fast(&eth->flow_table, &entry->node,\n \t\t\t       mtk_flow_ht_params);\n+\tif (entry->wed_index >= 0)\n+\t\tmtk_wed_flow_remove(entry->wed_index);\n \tkfree(entry);\n \n \treturn 0;\n--- a/drivers/net/ethernet/mediatek/mtk_wed.h\n+++ b/drivers/net/ethernet/mediatek/mtk_wed.h\n@@ -7,6 +7,7 @@\n #include <linux/soc/mediatek/mtk_wed.h>\n #include <linux/debugfs.h>\n #include <linux/regmap.h>\n+#include <linux/netdevice.h>\n \n struct mtk_eth;\n \n@@ -27,6 +28,12 @@ struct mtk_wed_hw {\n \tint index;\n };\n \n+struct mtk_wdma_info {\n+\tu8 wdma_idx;\n+\tu8 queue;\n+\tu16 wcid;\n+\tu8 bss;\n+};\n \n #ifdef CONFIG_NET_MEDIATEK_SOC_WED\n static inline void\n--- a/include/linux/netdevice.h\n+++ b/include/linux/netdevice.h\n@@ -849,6 +849,7 @@ enum net_device_path_type {\n \tDEV_PATH_BRIDGE,\n \tDEV_PATH_PPPOE,\n \tDEV_PATH_DSA,\n+\tDEV_PATH_MTK_WDMA,\n };\n \n struct net_device_path {\n@@ -874,6 +875,12 @@ struct net_device_path {\n \t\t\tint port;\n \t\t\tu16 proto;\n \t\t} dsa;\n+\t\tstruct {\n+\t\t\tu8 wdma_idx;\n+\t\t\tu8 queue;\n+\t\t\tu16 wcid;\n+\t\t\tu8 bss;\n+\t\t} mtk_wdma;\n \t};\n };\n \n--- a/net/core/dev.c\n+++ b/net/core/dev.c\n@@ -761,6 +761,10 @@ int dev_fill_forward_path(const struct n\n \t\tif (WARN_ON_ONCE(last_dev == ctx.dev))\n \t\t\treturn -1;\n \t}\n+\n+\tif (!ctx.dev)\n+\t\treturn ret;\n+\n \tpath = dev_fwd_path(stack);\n \tif (!path)\n \t\treturn -1;\n"
  },
  {
    "path": "target/linux/generic/pending-5.15/701-04-arm64-dts-mediatek-mt7622-introduce-nodes-for-Wirele.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nDate: Sat, 5 Feb 2022 18:36:36 +0100\nSubject: [PATCH] arm64: dts: mediatek: mt7622: introduce nodes for\n Wireless Ethernet Dispatch\n\nIntroduce wed0 and wed1 nodes in order to enable offloading forwarding\nbetween ethernet and wireless devices on the mt7622 chipset.\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n\n--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi\n+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi\n@@ -893,6 +893,11 @@\n \t\t};\n \t};\n \n+\thifsys: syscon@1af00000 {\n+\t\tcompatible = \"mediatek,mt7622-hifsys\", \"syscon\";\n+\t\treg = <0 0x1af00000 0 0x70>;\n+\t};\n+\n \tethsys: syscon@1b000000 {\n \t\tcompatible = \"mediatek,mt7622-ethsys\",\n \t\t\t     \"syscon\";\n@@ -911,6 +916,26 @@\n \t\t#dma-cells = <1>;\n \t};\n \n+\tpcie_mirror: pcie-mirror@10000400 {\n+\t\tcompatible = \"mediatek,mt7622-pcie-mirror\",\n+\t\t\t     \"syscon\";\n+\t\treg = <0 0x10000400 0 0x10>;\n+\t};\n+\n+\twed0: wed@1020a000 {\n+\t\tcompatible = \"mediatek,mt7622-wed\",\n+\t\t\t     \"syscon\";\n+\t\treg = <0 0x1020a000 0 0x1000>;\n+\t\tinterrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_LOW>;\n+\t};\n+\n+\twed1: wed@1020b000 {\n+\t\tcompatible = \"mediatek,mt7622-wed\",\n+\t\t\t     \"syscon\";\n+\t\treg = <0 0x1020b000 0 0x1000>;\n+\t\tinterrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_LOW>;\n+\t};\n+\n \teth: ethernet@1b100000 {\n \t\tcompatible = \"mediatek,mt7622-eth\",\n \t\t\t     \"mediatek,mt2701-eth\",\n@@ -938,6 +963,9 @@\n \t\tmediatek,ethsys = <&ethsys>;\n \t\tmediatek,sgmiisys = <&sgmiisys>;\n \t\tmediatek,cci-control = <&cci_control2>;\n+\t\tmediatek,wed = <&wed0>, <&wed1>;\n+\t\tmediatek,pcie-mirror = <&pcie_mirror>;\n+\t\tmediatek,hifsys = <&hifsys>;\n \t\tdma-coherent;\n \t\t#address-cells = <1>;\n \t\t#size-cells = <0>;\n"
  },
  {
    "path": "target/linux/generic/pending-5.15/701-05-net-ethernet-mtk_eth_soc-add-ipv6-flow-offload-suppo.patch",
    "content": "From: David Bentham <db260179@gmail.com>\nDate: Mon, 21 Feb 2022 15:36:16 +0100\nSubject: [PATCH] net: ethernet: mtk_eth_soc: add ipv6 flow offload\n support\n\nAdd the missing IPv6 flow offloading support for routing only.\nHardware flow offloading is done by the packet processing engine (PPE)\nof the Ethernet MAC and as it doesn't support mangling of IPv6 packets,\nIPv6 NAT cannot be supported.\n\nSigned-off-by: David Bentham <db260179@gmail.com>\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n\n--- a/drivers/net/ethernet/mediatek/mtk_ppe_offload.c\n+++ b/drivers/net/ethernet/mediatek/mtk_ppe_offload.c\n@@ -6,6 +6,7 @@\n #include <linux/if_ether.h>\n #include <linux/rhashtable.h>\n #include <linux/ip.h>\n+#include <linux/ipv6.h>\n #include <net/flow_offload.h>\n #include <net/pkt_cls.h>\n #include <net/dsa.h>\n@@ -20,6 +21,11 @@ struct mtk_flow_data {\n \t\t\t__be32 src_addr;\n \t\t\t__be32 dst_addr;\n \t\t} v4;\n+\n+\t\tstruct {\n+\t\t\tstruct in6_addr src_addr;\n+\t\t\tstruct in6_addr dst_addr;\n+\t\t} v6;\n \t};\n \n \t__be16 src_port;\n@@ -65,6 +71,14 @@ mtk_flow_set_ipv4_addr(struct mtk_foe_en\n \t\t\t\t\t    data->v4.dst_addr, data->dst_port);\n }\n \n+static int\n+mtk_flow_set_ipv6_addr(struct mtk_foe_entry *foe, struct mtk_flow_data *data)\n+{\n+\treturn mtk_foe_entry_set_ipv6_tuple(foe,\n+\t\t\t\t\t    data->v6.src_addr.s6_addr32, data->src_port,\n+\t\t\t\t\t    data->v6.dst_addr.s6_addr32, data->dst_port);\n+}\n+\n static void\n mtk_flow_offload_mangle_eth(const struct flow_action_entry *act, void *eth)\n {\n@@ -296,6 +310,9 @@ mtk_flow_offload_replace(struct mtk_eth\n \tcase FLOW_DISSECTOR_KEY_IPV4_ADDRS:\n \t\toffload_type = MTK_PPE_PKT_TYPE_IPV4_HNAPT;\n \t\tbreak;\n+\tcase FLOW_DISSECTOR_KEY_IPV6_ADDRS:\n+\t\toffload_type = MTK_PPE_PKT_TYPE_IPV6_ROUTE_5T;\n+\t\tbreak;\n \tdefault:\n \t\treturn -EOPNOTSUPP;\n \t}\n@@ -331,6 +348,17 @@ mtk_flow_offload_replace(struct mtk_eth\n \t\tmtk_flow_set_ipv4_addr(&foe, &data, false);\n \t}\n \n+\tif (addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) {\n+\t\tstruct flow_match_ipv6_addrs addrs;\n+\n+\t\tflow_rule_match_ipv6_addrs(rule, &addrs);\n+\n+\t\tdata.v6.src_addr = addrs.key->src;\n+\t\tdata.v6.dst_addr = addrs.key->dst;\n+\n+\t\tmtk_flow_set_ipv6_addr(&foe, &data);\n+\t}\n+\n \tflow_action_for_each(i, act, &rule->action) {\n \t\tif (act->id != FLOW_ACTION_MANGLE)\n \t\t\tcontinue;\n"
  },
  {
    "path": "target/linux/generic/pending-5.15/701-06-net-ethernet-mtk_eth_soc-support-TC_SETUP_BLOCK-for-.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nDate: Mon, 21 Feb 2022 15:37:21 +0100\nSubject: [PATCH] net: ethernet: mtk_eth_soc: support TC_SETUP_BLOCK for\n PPE offload\n\nThis allows offload entries to be created from user space\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n\n--- a/drivers/net/ethernet/mediatek/mtk_ppe_offload.c\n+++ b/drivers/net/ethernet/mediatek/mtk_ppe_offload.c\n@@ -563,10 +563,13 @@ mtk_eth_setup_tc_block(struct net_device\n int mtk_eth_setup_tc(struct net_device *dev, enum tc_setup_type type,\n \t\t     void *type_data)\n {\n-\tif (type == TC_SETUP_FT)\n+\tswitch (type) {\n+\tcase TC_SETUP_BLOCK:\n+\tcase TC_SETUP_FT:\n \t\treturn mtk_eth_setup_tc_block(dev, type_data);\n-\n-\treturn -EOPNOTSUPP;\n+\tdefault:\n+\t\treturn -EOPNOTSUPP;\n+\t}\n }\n \n int mtk_eth_offload_init(struct mtk_eth *eth)\n"
  },
  {
    "path": "target/linux/generic/pending-5.15/701-07-net-ethernet-mtk_eth_soc-allocate-struct-mtk_ppe-sep.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nDate: Mon, 21 Feb 2022 15:38:20 +0100\nSubject: [PATCH] net: ethernet: mtk_eth_soc: allocate struct mtk_ppe\n separately\n\nPreparation for adding more data to it, which will increase its size.\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n\n--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c\n+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c\n@@ -2312,7 +2312,7 @@ static int mtk_open(struct net_device *d\n \t\tif (err)\n \t\t\treturn err;\n \n-\t\tif (eth->soc->offload_version && mtk_ppe_start(&eth->ppe) == 0)\n+\t\tif (eth->soc->offload_version && mtk_ppe_start(eth->ppe) == 0)\n \t\t\tgdm_config = MTK_GDMA_TO_PPE;\n \n \t\tmtk_gdm_config(eth, gdm_config);\n@@ -2386,7 +2386,7 @@ static int mtk_stop(struct net_device *d\n \tmtk_dma_free(eth);\n \n \tif (eth->soc->offload_version)\n-\t\tmtk_ppe_stop(&eth->ppe);\n+\t\tmtk_ppe_stop(eth->ppe);\n \n \treturn 0;\n }\n@@ -3278,10 +3278,11 @@ static int mtk_probe(struct platform_dev\n \t}\n \n \tif (eth->soc->offload_version) {\n-\t\terr = mtk_ppe_init(&eth->ppe, eth->dev,\n-\t\t\t\t   eth->base + MTK_ETH_PPE_BASE, 2);\n-\t\tif (err)\n+\t\teth->ppe = mtk_ppe_init(eth->dev, eth->base + MTK_ETH_PPE_BASE, 2);\n+\t\tif (!eth->ppe) {\n+\t\t\terr = -ENOMEM;\n \t\t\tgoto err_free_dev;\n+\t\t}\n \n \t\terr = mtk_eth_offload_init(eth);\n \t\tif (err)\n--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h\n+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h\n@@ -982,7 +982,7 @@ struct mtk_eth {\n \tu32\t\t\t\trx_dma_l4_valid;\n \tint\t\t\t\tip_align;\n \n-\tstruct mtk_ppe\t\t\tppe;\n+\tstruct mtk_ppe\t\t\t*ppe;\n \tstruct rhashtable\t\tflow_table;\n };\n \n--- a/drivers/net/ethernet/mediatek/mtk_ppe.c\n+++ b/drivers/net/ethernet/mediatek/mtk_ppe.c\n@@ -384,10 +384,15 @@ int mtk_foe_entry_commit(struct mtk_ppe\n \treturn hash;\n }\n \n-int mtk_ppe_init(struct mtk_ppe *ppe, struct device *dev, void __iomem *base,\n+struct mtk_ppe *mtk_ppe_init(struct device *dev, void __iomem *base,\n \t\t int version)\n {\n \tstruct mtk_foe_entry *foe;\n+\tstruct mtk_ppe *ppe;\n+\n+\tppe = devm_kzalloc(dev, sizeof(*ppe), GFP_KERNEL);\n+\tif (!ppe)\n+\t\treturn NULL;\n \n \t/* need to allocate a separate device, since it PPE DMA access is\n \t * not coherent.\n@@ -399,13 +404,13 @@ int mtk_ppe_init(struct mtk_ppe *ppe, st\n \tfoe = dmam_alloc_coherent(ppe->dev, MTK_PPE_ENTRIES * sizeof(*foe),\n \t\t\t\t  &ppe->foe_phys, GFP_KERNEL);\n \tif (!foe)\n-\t\treturn -ENOMEM;\n+\t\treturn NULL;\n \n \tppe->foe_table = foe;\n \n \tmtk_ppe_debugfs_init(ppe);\n \n-\treturn 0;\n+\treturn ppe;\n }\n \n static void mtk_ppe_init_foe_table(struct mtk_ppe *ppe)\n--- a/drivers/net/ethernet/mediatek/mtk_ppe.h\n+++ b/drivers/net/ethernet/mediatek/mtk_ppe.h\n@@ -246,8 +246,7 @@ struct mtk_ppe {\n \tvoid *acct_table;\n };\n \n-int mtk_ppe_init(struct mtk_ppe *ppe, struct device *dev, void __iomem *base,\n-\t\t int version);\n+struct mtk_ppe *mtk_ppe_init(struct device *dev, void __iomem *base, int version);\n int mtk_ppe_start(struct mtk_ppe *ppe);\n int mtk_ppe_stop(struct mtk_ppe *ppe);\n \n--- a/drivers/net/ethernet/mediatek/mtk_ppe_offload.c\n+++ b/drivers/net/ethernet/mediatek/mtk_ppe_offload.c\n@@ -411,7 +411,7 @@ mtk_flow_offload_replace(struct mtk_eth\n \n \tentry->cookie = f->cookie;\n \ttimestamp = mtk_eth_timestamp(eth);\n-\thash = mtk_foe_entry_commit(&eth->ppe, &foe, timestamp);\n+\thash = mtk_foe_entry_commit(eth->ppe, &foe, timestamp);\n \tif (hash < 0) {\n \t\terr = hash;\n \t\tgoto free;\n@@ -426,7 +426,7 @@ mtk_flow_offload_replace(struct mtk_eth\n \n \treturn 0;\n clear_flow:\n-\tmtk_foe_entry_clear(&eth->ppe, hash);\n+\tmtk_foe_entry_clear(eth->ppe, hash);\n free:\n \tkfree(entry);\n \tif (wed_index >= 0)\n@@ -444,7 +444,7 @@ mtk_flow_offload_destroy(struct mtk_eth\n \tif (!entry)\n \t\treturn -ENOENT;\n \n-\tmtk_foe_entry_clear(&eth->ppe, entry->hash);\n+\tmtk_foe_entry_clear(eth->ppe, entry->hash);\n \trhashtable_remove_fast(&eth->flow_table, &entry->node,\n \t\t\t       mtk_flow_ht_params);\n \tif (entry->wed_index >= 0)\n@@ -466,7 +466,7 @@ mtk_flow_offload_stats(struct mtk_eth *e\n \tif (!entry)\n \t\treturn -ENOENT;\n \n-\ttimestamp = mtk_foe_entry_timestamp(&eth->ppe, entry->hash);\n+\ttimestamp = mtk_foe_entry_timestamp(eth->ppe, entry->hash);\n \tif (timestamp < 0)\n \t\treturn -ETIMEDOUT;\n \n@@ -522,7 +522,7 @@ mtk_eth_setup_tc_block(struct net_device\n \tstruct flow_block_cb *block_cb;\n \tflow_setup_cb_t *cb;\n \n-\tif (!eth->ppe.foe_table)\n+\tif (!eth->ppe || !eth->ppe->foe_table)\n \t\treturn -EOPNOTSUPP;\n \n \tif (f->binder_type != FLOW_BLOCK_BINDER_TYPE_CLSACT_INGRESS)\n@@ -574,7 +574,7 @@ int mtk_eth_setup_tc(struct net_device *\n \n int mtk_eth_offload_init(struct mtk_eth *eth)\n {\n-\tif (!eth->ppe.foe_table)\n+\tif (!eth->ppe || !eth->ppe->foe_table)\n \t\treturn 0;\n \n \treturn rhashtable_init(&eth->flow_table, &mtk_flow_ht_params);\n"
  },
  {
    "path": "target/linux/generic/pending-5.15/701-08-net-ethernet-mtk_eth_soc-rework-hardware-flow-table-.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nDate: Mon, 21 Feb 2022 15:39:18 +0100\nSubject: [PATCH] net: ethernet: mtk_eth_soc: rework hardware flow table\n management\n\nThe hardware was designed to handle flow detection and creation of flow entries\nby itself, relying on the software primarily for filling in egress routing\ninformation.\nWhen there is a hash collision between multiple flows, this allows the hardware\nto maintain the entry for the most active flow.\nAdditionally, the hardware only keeps offloading active for entries with at\nleast 30 packets per second.\n\nWith this rework, the code no longer creates a hardware entries directly.\nInstead, the hardware entry is only created when the PPE reports a matching\nunbound flow with the minimum target rate.\nIn order to reduce CPU overhead, looking for flows belonging to a hash entry\nis rate limited to once every 100ms.\n\nThis rework is also used as preparation for emulating bridge offload by\nmanaging L4 offload entries on demand.\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n\n--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c\n+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c\n@@ -21,6 +21,7 @@\n #include <linux/pinctrl/devinfo.h>\n #include <linux/phylink.h>\n #include <linux/jhash.h>\n+#include <linux/bitfield.h>\n #include <net/dsa.h>\n \n #include \"mtk_eth_soc.h\"\n@@ -1281,7 +1282,7 @@ static int mtk_poll_rx(struct napi_struc\n \t\tstruct net_device *netdev;\n \t\tunsigned int pktlen;\n \t\tdma_addr_t dma_addr;\n-\t\tu32 hash;\n+\t\tu32 hash, reason;\n \t\tint mac;\n \n \t\tring = mtk_get_rx_ring(eth);\n@@ -1357,6 +1358,11 @@ static int mtk_poll_rx(struct napi_struc\n \t\t\tskb_set_hash(skb, hash, PKT_HASH_TYPE_L4);\n \t\t}\n \n+\t\treason = FIELD_GET(MTK_RXD4_PPE_CPU_REASON, trxd.rxd4);\n+\t\tif (reason == MTK_PPE_CPU_REASON_HIT_UNBIND_RATE_REACHED)\n+\t\t\tmtk_ppe_check_skb(eth->ppe, skb,\n+\t\t\t\t\t  trxd.rxd4 & MTK_RXD4_FOE_ENTRY);\n+\n \t\tif (netdev->features & NETIF_F_HW_VLAN_CTAG_RX &&\n \t\t    (trxd.rxd2 & RX_DMA_VTAG))\n \t\t\t__vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),\n@@ -3278,7 +3284,7 @@ static int mtk_probe(struct platform_dev\n \t}\n \n \tif (eth->soc->offload_version) {\n-\t\teth->ppe = mtk_ppe_init(eth->dev, eth->base + MTK_ETH_PPE_BASE, 2);\n+\t\teth->ppe = mtk_ppe_init(eth, eth->base + MTK_ETH_PPE_BASE, 2);\n \t\tif (!eth->ppe) {\n \t\t\terr = -ENOMEM;\n \t\t\tgoto err_free_dev;\n--- a/drivers/net/ethernet/mediatek/mtk_ppe.c\n+++ b/drivers/net/ethernet/mediatek/mtk_ppe.c\n@@ -6,9 +6,12 @@\n #include <linux/iopoll.h>\n #include <linux/etherdevice.h>\n #include <linux/platform_device.h>\n+#include \"mtk_eth_soc.h\"\n #include \"mtk_ppe.h\"\n #include \"mtk_ppe_regs.h\"\n \n+static DEFINE_SPINLOCK(ppe_lock);\n+\n static void ppe_w32(struct mtk_ppe *ppe, u32 reg, u32 val)\n {\n \twritel(val, ppe->base + reg);\n@@ -41,6 +44,11 @@ static u32 ppe_clear(struct mtk_ppe *ppe\n \treturn ppe_m32(ppe, reg, val, 0);\n }\n \n+static u32 mtk_eth_timestamp(struct mtk_eth *eth)\n+{\n+\treturn mtk_r32(eth, 0x0010) & MTK_FOE_IB1_BIND_TIMESTAMP;\n+}\n+\n static int mtk_ppe_wait_busy(struct mtk_ppe *ppe)\n {\n \tint ret;\n@@ -353,26 +361,59 @@ static inline bool mtk_foe_entry_usable(\n \t       FIELD_GET(MTK_FOE_IB1_STATE, entry->ib1) != MTK_FOE_STATE_BIND;\n }\n \n-int mtk_foe_entry_commit(struct mtk_ppe *ppe, struct mtk_foe_entry *entry,\n-\t\t\t u16 timestamp)\n+static bool\n+mtk_flow_entry_match(struct mtk_flow_entry *entry, struct mtk_foe_entry *data)\n+{\n+\tint type, len;\n+\n+\tif ((data->ib1 ^ entry->data.ib1) & MTK_FOE_IB1_UDP)\n+\t\treturn false;\n+\n+\ttype = FIELD_GET(MTK_FOE_IB1_PACKET_TYPE, entry->data.ib1);\n+\tif (type > MTK_PPE_PKT_TYPE_IPV4_DSLITE)\n+\t\tlen = offsetof(struct mtk_foe_entry, ipv6._rsv);\n+\telse\n+\t\tlen = offsetof(struct mtk_foe_entry, ipv4.ib2);\n+\n+\treturn !memcmp(&entry->data.data, &data->data, len - 4);\n+}\n+\n+static void\n+mtk_flow_entry_update(struct mtk_ppe *ppe, struct mtk_flow_entry *entry)\n {\n \tstruct mtk_foe_entry *hwe;\n-\tu32 hash;\n+\tstruct mtk_foe_entry foe;\n \n+\tspin_lock_bh(&ppe_lock);\n+\tif (entry->hash == 0xffff)\n+\t\tgoto out;\n+\n+\thwe = &ppe->foe_table[entry->hash];\n+\tmemcpy(&foe, hwe, sizeof(foe));\n+\tif (!mtk_flow_entry_match(entry, &foe)) {\n+\t\tentry->hash = 0xffff;\n+\t\tgoto out;\n+\t}\n+\n+\tentry->data.ib1 = foe.ib1;\n+\n+out:\n+\tspin_unlock_bh(&ppe_lock);\n+}\n+\n+static void\n+__mtk_foe_entry_commit(struct mtk_ppe *ppe, struct mtk_foe_entry *entry,\n+\t\t       u16 hash)\n+{\n+\tstruct mtk_foe_entry *hwe;\n+\tu16 timestamp;\n+\n+\ttimestamp = mtk_eth_timestamp(ppe->eth);\n \ttimestamp &= MTK_FOE_IB1_BIND_TIMESTAMP;\n \tentry->ib1 &= ~MTK_FOE_IB1_BIND_TIMESTAMP;\n \tentry->ib1 |= FIELD_PREP(MTK_FOE_IB1_BIND_TIMESTAMP, timestamp);\n \n-\thash = mtk_ppe_hash_entry(entry);\n \thwe = &ppe->foe_table[hash];\n-\tif (!mtk_foe_entry_usable(hwe)) {\n-\t\thwe++;\n-\t\thash++;\n-\n-\t\tif (!mtk_foe_entry_usable(hwe))\n-\t\t\treturn -ENOSPC;\n-\t}\n-\n \tmemcpy(&hwe->data, &entry->data, sizeof(hwe->data));\n \twmb();\n \thwe->ib1 = entry->ib1;\n@@ -380,13 +421,77 @@ int mtk_foe_entry_commit(struct mtk_ppe\n \tdma_wmb();\n \n \tmtk_ppe_cache_clear(ppe);\n+}\n \n-\treturn hash;\n+void mtk_foe_entry_clear(struct mtk_ppe *ppe, struct mtk_flow_entry *entry)\n+{\n+\tspin_lock_bh(&ppe_lock);\n+\thlist_del_init(&entry->list);\n+\tif (entry->hash != 0xffff) {\n+\t\tppe->foe_table[entry->hash].ib1 &= ~MTK_FOE_IB1_STATE;\n+\t\tppe->foe_table[entry->hash].ib1 |= FIELD_PREP(MTK_FOE_IB1_STATE,\n+\t\t\t\t\t\t\t      MTK_FOE_STATE_BIND);\n+\t\tdma_wmb();\n+\t}\n+\tentry->hash = 0xffff;\n+\tspin_unlock_bh(&ppe_lock);\n+}\n+\n+int mtk_foe_entry_commit(struct mtk_ppe *ppe, struct mtk_flow_entry *entry)\n+{\n+\tu32 hash = mtk_ppe_hash_entry(&entry->data);\n+\n+\tentry->hash = 0xffff;\n+\tspin_lock_bh(&ppe_lock);\n+\thlist_add_head(&entry->list, &ppe->foe_flow[hash / 2]);\n+\tspin_unlock_bh(&ppe_lock);\n+\n+\treturn 0;\n+}\n+\n+void __mtk_ppe_check_skb(struct mtk_ppe *ppe, struct sk_buff *skb, u16 hash)\n+{\n+\tstruct hlist_head *head = &ppe->foe_flow[hash / 2];\n+\tstruct mtk_flow_entry *entry;\n+\tstruct mtk_foe_entry *hwe = &ppe->foe_table[hash];\n+\tbool found = false;\n+\n+\tif (hlist_empty(head))\n+\t\treturn;\n+\n+\tspin_lock_bh(&ppe_lock);\n+\thlist_for_each_entry(entry, head, list) {\n+\t\tif (found || !mtk_flow_entry_match(entry, hwe)) {\n+\t\t\tif (entry->hash != 0xffff)\n+\t\t\t\tentry->hash = 0xffff;\n+\t\t\tcontinue;\n+\t\t}\n+\n+\t\tentry->hash = hash;\n+\t\t__mtk_foe_entry_commit(ppe, &entry->data, hash);\n+\t\tfound = true;\n+\t}\n+\tspin_unlock_bh(&ppe_lock);\n+}\n+\n+int mtk_foe_entry_idle_time(struct mtk_ppe *ppe, struct mtk_flow_entry *entry)\n+{\n+\tu16 now = mtk_eth_timestamp(ppe->eth) & MTK_FOE_IB1_BIND_TIMESTAMP;\n+\tu16 timestamp;\n+\n+\tmtk_flow_entry_update(ppe, entry);\n+\ttimestamp = entry->data.ib1 & MTK_FOE_IB1_BIND_TIMESTAMP;\n+\n+\tif (timestamp > now)\n+\t\treturn MTK_FOE_IB1_BIND_TIMESTAMP + 1 - timestamp + now;\n+\telse\n+\t\treturn now - timestamp;\n }\n \n-struct mtk_ppe *mtk_ppe_init(struct device *dev, void __iomem *base,\n+struct mtk_ppe *mtk_ppe_init(struct mtk_eth *eth, void __iomem *base,\n \t\t int version)\n {\n+\tstruct device *dev = eth->dev;\n \tstruct mtk_foe_entry *foe;\n \tstruct mtk_ppe *ppe;\n \n@@ -398,6 +503,7 @@ struct mtk_ppe *mtk_ppe_init(struct devi\n \t * not coherent.\n \t */\n \tppe->base = base;\n+\tppe->eth = eth;\n \tppe->dev = dev;\n \tppe->version = version;\n \n--- a/drivers/net/ethernet/mediatek/mtk_ppe.h\n+++ b/drivers/net/ethernet/mediatek/mtk_ppe.h\n@@ -235,7 +235,17 @@ enum {\n \tMTK_PPE_CPU_REASON_INVALID\t\t\t= 0x1f,\n };\n \n+struct mtk_flow_entry {\n+\tstruct rhash_head node;\n+\tstruct hlist_node list;\n+\tunsigned long cookie;\n+\tstruct mtk_foe_entry data;\n+\tu16 hash;\n+\ts8 wed_index;\n+};\n+\n struct mtk_ppe {\n+\tstruct mtk_eth *eth;\n \tstruct device *dev;\n \tvoid __iomem *base;\n \tint version;\n@@ -243,18 +253,33 @@ struct mtk_ppe {\n \tstruct mtk_foe_entry *foe_table;\n \tdma_addr_t foe_phys;\n \n+\tu16 foe_check_time[MTK_PPE_ENTRIES];\n+\tstruct hlist_head foe_flow[MTK_PPE_ENTRIES / 2];\n+\n \tvoid *acct_table;\n };\n \n-struct mtk_ppe *mtk_ppe_init(struct device *dev, void __iomem *base, int version);\n+struct mtk_ppe *mtk_ppe_init(struct mtk_eth *eth, void __iomem *base, int version);\n int mtk_ppe_start(struct mtk_ppe *ppe);\n int mtk_ppe_stop(struct mtk_ppe *ppe);\n \n+void __mtk_ppe_check_skb(struct mtk_ppe *ppe, struct sk_buff *skb, u16 hash);\n+\n static inline void\n-mtk_foe_entry_clear(struct mtk_ppe *ppe, u16 hash)\n+mtk_ppe_check_skb(struct mtk_ppe *ppe, struct sk_buff *skb, u16 hash)\n {\n-\tppe->foe_table[hash].ib1 = 0;\n-\tdma_wmb();\n+\tu16 now, diff;\n+\n+\tif (!ppe)\n+\t\treturn;\n+\n+\tnow = (u16)jiffies;\n+\tdiff = now - ppe->foe_check_time[hash];\n+\tif (diff < HZ / 10)\n+\t\treturn;\n+\n+\tppe->foe_check_time[hash] = now;\n+\t__mtk_ppe_check_skb(ppe, skb, hash);\n }\n \n static inline int\n@@ -282,8 +307,9 @@ int mtk_foe_entry_set_vlan(struct mtk_fo\n int mtk_foe_entry_set_pppoe(struct mtk_foe_entry *entry, int sid);\n int mtk_foe_entry_set_wdma(struct mtk_foe_entry *entry, int wdma_idx, int txq,\n \t\t\t   int bss, int wcid);\n-int mtk_foe_entry_commit(struct mtk_ppe *ppe, struct mtk_foe_entry *entry,\n-\t\t\t u16 timestamp);\n+int mtk_foe_entry_commit(struct mtk_ppe *ppe, struct mtk_flow_entry *entry);\n+void mtk_foe_entry_clear(struct mtk_ppe *ppe, struct mtk_flow_entry *entry);\n+int mtk_foe_entry_idle_time(struct mtk_ppe *ppe, struct mtk_flow_entry *entry);\n int mtk_ppe_debugfs_init(struct mtk_ppe *ppe);\n \n #endif\n--- a/drivers/net/ethernet/mediatek/mtk_ppe_offload.c\n+++ b/drivers/net/ethernet/mediatek/mtk_ppe_offload.c\n@@ -42,13 +42,6 @@ struct mtk_flow_data {\n \t} pppoe;\n };\n \n-struct mtk_flow_entry {\n-\tstruct rhash_head node;\n-\tunsigned long cookie;\n-\tu16 hash;\n-\ts8 wed_index;\n-};\n-\n static const struct rhashtable_params mtk_flow_ht_params = {\n \t.head_offset = offsetof(struct mtk_flow_entry, node),\n \t.key_offset = offsetof(struct mtk_flow_entry, cookie),\n@@ -56,12 +49,6 @@ static const struct rhashtable_params mt\n \t.automatic_shrinking = true,\n };\n \n-static u32\n-mtk_eth_timestamp(struct mtk_eth *eth)\n-{\n-\treturn mtk_r32(eth, 0x0010) & MTK_FOE_IB1_BIND_TIMESTAMP;\n-}\n-\n static int\n mtk_flow_set_ipv4_addr(struct mtk_foe_entry *foe, struct mtk_flow_data *data,\n \t\t       bool egress)\n@@ -237,10 +224,8 @@ mtk_flow_offload_replace(struct mtk_eth\n \tint offload_type = 0;\n \tint wed_index = -1;\n \tu16 addr_type = 0;\n-\tu32 timestamp;\n \tu8 l4proto = 0;\n \tint err = 0;\n-\tint hash;\n \tint i;\n \n \tif (rhashtable_lookup(&eth->flow_table, &f->cookie, mtk_flow_ht_params))\n@@ -410,23 +395,21 @@ mtk_flow_offload_replace(struct mtk_eth\n \t\treturn -ENOMEM;\n \n \tentry->cookie = f->cookie;\n-\ttimestamp = mtk_eth_timestamp(eth);\n-\thash = mtk_foe_entry_commit(eth->ppe, &foe, timestamp);\n-\tif (hash < 0) {\n-\t\terr = hash;\n+\tmemcpy(&entry->data, &foe, sizeof(entry->data));\n+\tentry->wed_index = wed_index;\n+\n+\tif (mtk_foe_entry_commit(eth->ppe, entry) < 0)\n \t\tgoto free;\n-\t}\n \n-\tentry->hash = hash;\n-\tentry->wed_index = wed_index;\n \terr = rhashtable_insert_fast(&eth->flow_table, &entry->node,\n \t\t\t\t     mtk_flow_ht_params);\n \tif (err < 0)\n-\t\tgoto clear_flow;\n+\t\tgoto clear;\n \n \treturn 0;\n-clear_flow:\n-\tmtk_foe_entry_clear(eth->ppe, hash);\n+\n+clear:\n+\tmtk_foe_entry_clear(eth->ppe, entry);\n free:\n \tkfree(entry);\n \tif (wed_index >= 0)\n@@ -444,7 +427,7 @@ mtk_flow_offload_destroy(struct mtk_eth\n \tif (!entry)\n \t\treturn -ENOENT;\n \n-\tmtk_foe_entry_clear(eth->ppe, entry->hash);\n+\tmtk_foe_entry_clear(eth->ppe, entry);\n \trhashtable_remove_fast(&eth->flow_table, &entry->node,\n \t\t\t       mtk_flow_ht_params);\n \tif (entry->wed_index >= 0)\n@@ -458,7 +441,6 @@ static int\n mtk_flow_offload_stats(struct mtk_eth *eth, struct flow_cls_offload *f)\n {\n \tstruct mtk_flow_entry *entry;\n-\tint timestamp;\n \tu32 idle;\n \n \tentry = rhashtable_lookup(&eth->flow_table, &f->cookie,\n@@ -466,11 +448,7 @@ mtk_flow_offload_stats(struct mtk_eth *e\n \tif (!entry)\n \t\treturn -ENOENT;\n \n-\ttimestamp = mtk_foe_entry_timestamp(eth->ppe, entry->hash);\n-\tif (timestamp < 0)\n-\t\treturn -ETIMEDOUT;\n-\n-\tidle = mtk_eth_timestamp(eth) - timestamp;\n+\tidle = mtk_foe_entry_idle_time(eth->ppe, entry);\n \tf->stats.lastused = jiffies - idle * HZ;\n \n \treturn 0;\n"
  },
  {
    "path": "target/linux/generic/pending-5.15/701-09-net-ethernet-mtk_eth_soc-remove-bridge-flow-offload-.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nDate: Mon, 21 Feb 2022 15:55:19 +0100\nSubject: [PATCH] net: ethernet: mtk_eth_soc: remove bridge flow offload\n type entry support\n\nAccording to MediaTek, this feature is not supported in current hardware\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n\n--- a/drivers/net/ethernet/mediatek/mtk_ppe.c\n+++ b/drivers/net/ethernet/mediatek/mtk_ppe.c\n@@ -84,13 +84,6 @@ static u32 mtk_ppe_hash_entry(struct mtk\n \tu32 hash;\n \n \tswitch (FIELD_GET(MTK_FOE_IB1_PACKET_TYPE, e->ib1)) {\n-\t\tcase MTK_PPE_PKT_TYPE_BRIDGE:\n-\t\t\thv1 = e->bridge.src_mac_lo;\n-\t\t\thv1 ^= ((e->bridge.src_mac_hi & 0xffff) << 16);\n-\t\t\thv2 = e->bridge.src_mac_hi >> 16;\n-\t\t\thv2 ^= e->bridge.dest_mac_lo;\n-\t\t\thv3 = e->bridge.dest_mac_hi;\n-\t\t\tbreak;\n \t\tcase MTK_PPE_PKT_TYPE_IPV4_ROUTE:\n \t\tcase MTK_PPE_PKT_TYPE_IPV4_HNAPT:\n \t\t\thv1 = e->ipv4.orig.ports;\n@@ -572,7 +565,6 @@ int mtk_ppe_start(struct mtk_ppe *ppe)\n \t      MTK_PPE_FLOW_CFG_IP4_NAT |\n \t      MTK_PPE_FLOW_CFG_IP4_NAPT |\n \t      MTK_PPE_FLOW_CFG_IP4_DSLITE |\n-\t      MTK_PPE_FLOW_CFG_L2_BRIDGE |\n \t      MTK_PPE_FLOW_CFG_IP4_NAT_FRAG;\n \tppe_w32(ppe, MTK_PPE_FLOW_CFG, val);\n \n--- a/drivers/net/ethernet/mediatek/mtk_ppe_debugfs.c\n+++ b/drivers/net/ethernet/mediatek/mtk_ppe_debugfs.c\n@@ -32,7 +32,6 @@ static const char *mtk_foe_pkt_type_str(\n \tstatic const char * const type_str[] = {\n \t\t[MTK_PPE_PKT_TYPE_IPV4_HNAPT] = \"IPv4 5T\",\n \t\t[MTK_PPE_PKT_TYPE_IPV4_ROUTE] = \"IPv4 3T\",\n-\t\t[MTK_PPE_PKT_TYPE_BRIDGE] = \"L2\",\n \t\t[MTK_PPE_PKT_TYPE_IPV4_DSLITE] = \"DS-LITE\",\n \t\t[MTK_PPE_PKT_TYPE_IPV6_ROUTE_3T] = \"IPv6 3T\",\n \t\t[MTK_PPE_PKT_TYPE_IPV6_ROUTE_5T] = \"IPv6 5T\",\n"
  },
  {
    "path": "target/linux/generic/pending-5.15/701-10-net-ethernet-mtk_eth_soc-support-creating-mac-addres.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nDate: Wed, 23 Feb 2022 10:56:34 +0100\nSubject: [PATCH] net: ethernet: mtk_eth_soc: support creating mac\n address based offload entries\n\nThis will be used to implement a limited form of bridge offloading.\nSince the hardware does not support flow table entries with just source\nand destination MAC address, the driver has to emulate it.\n\nThe hardware automatically creates entries entries for incoming flows, even\nwhen they are bridged instead of routed, and reports when packets for these\nflows have reached the minimum PPS rate for offloading.\n\nAfter this happens, we look up the L2 flow offload entry based on the MAC\nheader and fill in the output routing information in the flow table.\nThe dynamically created per-flow entries are automatically removed when\neither the hardware flowtable entry expires, is replaced, or if the offload\nrule they belong to is removed\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n\n--- a/drivers/net/ethernet/mediatek/mtk_ppe.c\n+++ b/drivers/net/ethernet/mediatek/mtk_ppe.c\n@@ -6,12 +6,22 @@\n #include <linux/iopoll.h>\n #include <linux/etherdevice.h>\n #include <linux/platform_device.h>\n+#include <linux/if_ether.h>\n+#include <linux/if_vlan.h>\n+#include <net/dsa.h>\n #include \"mtk_eth_soc.h\"\n #include \"mtk_ppe.h\"\n #include \"mtk_ppe_regs.h\"\n \n static DEFINE_SPINLOCK(ppe_lock);\n \n+static const struct rhashtable_params mtk_flow_l2_ht_params = {\n+\t.head_offset = offsetof(struct mtk_flow_entry, l2_node),\n+\t.key_offset = offsetof(struct mtk_flow_entry, data.bridge),\n+\t.key_len = offsetof(struct mtk_foe_bridge, key_end),\n+\t.automatic_shrinking = true,\n+};\n+\n static void ppe_w32(struct mtk_ppe *ppe, u32 reg, u32 val)\n {\n \twritel(val, ppe->base + reg);\n@@ -123,6 +133,9 @@ mtk_foe_entry_l2(struct mtk_foe_entry *e\n {\n \tint type = FIELD_GET(MTK_FOE_IB1_PACKET_TYPE, entry->ib1);\n \n+\tif (type == MTK_PPE_PKT_TYPE_BRIDGE)\n+\t\treturn &entry->bridge.l2;\n+\n \tif (type >= MTK_PPE_PKT_TYPE_IPV4_DSLITE)\n \t\treturn &entry->ipv6.l2;\n \n@@ -134,6 +147,9 @@ mtk_foe_entry_ib2(struct mtk_foe_entry *\n {\n \tint type = FIELD_GET(MTK_FOE_IB1_PACKET_TYPE, entry->ib1);\n \n+\tif (type == MTK_PPE_PKT_TYPE_BRIDGE)\n+\t\treturn &entry->bridge.ib2;\n+\n \tif (type >= MTK_PPE_PKT_TYPE_IPV4_DSLITE)\n \t\treturn &entry->ipv6.ib2;\n \n@@ -168,7 +184,12 @@ int mtk_foe_entry_prepare(struct mtk_foe\n \tif (type == MTK_PPE_PKT_TYPE_IPV6_ROUTE_3T)\n \t\tentry->ipv6.ports = ports_pad;\n \n-\tif (type >= MTK_PPE_PKT_TYPE_IPV4_DSLITE) {\n+\tif (type == MTK_PPE_PKT_TYPE_BRIDGE) {\n+\t\tether_addr_copy(entry->bridge.src_mac, src_mac);\n+\t\tether_addr_copy(entry->bridge.dest_mac, dest_mac);\n+\t\tentry->bridge.ib2 = val;\n+\t\tl2 = &entry->bridge.l2;\n+\t} else if (type >= MTK_PPE_PKT_TYPE_IPV4_DSLITE) {\n \t\tentry->ipv6.ib2 = val;\n \t\tl2 = &entry->ipv6.l2;\n \t} else {\n@@ -372,12 +393,96 @@ mtk_flow_entry_match(struct mtk_flow_ent\n }\n \n static void\n+__mtk_foe_entry_clear(struct mtk_ppe *ppe, struct mtk_flow_entry *entry)\n+{\n+\tstruct hlist_head *head;\n+\tstruct hlist_node *tmp;\n+\n+\tif (entry->type == MTK_FLOW_TYPE_L2) {\n+\t\trhashtable_remove_fast(&ppe->l2_flows, &entry->l2_node,\n+\t\t\t\t       mtk_flow_l2_ht_params);\n+\n+\t\thead = &entry->l2_flows;\n+\t\thlist_for_each_entry_safe(entry, tmp, head, l2_data.list)\n+\t\t\t__mtk_foe_entry_clear(ppe, entry);\n+\t\treturn;\n+\t}\n+\n+\thlist_del_init(&entry->list);\n+\tif (entry->hash != 0xffff) {\n+\t\tppe->foe_table[entry->hash].ib1 &= ~MTK_FOE_IB1_STATE;\n+\t\tppe->foe_table[entry->hash].ib1 |= FIELD_PREP(MTK_FOE_IB1_STATE,\n+\t\t\t\t\t\t\t      MTK_FOE_STATE_BIND);\n+\t\tdma_wmb();\n+\t}\n+\tentry->hash = 0xffff;\n+\n+\tif (entry->type != MTK_FLOW_TYPE_L2_SUBFLOW)\n+\t\treturn;\n+\n+\thlist_del_init(&entry->l2_data.list);\n+\tkfree(entry);\n+}\n+\n+static int __mtk_foe_entry_idle_time(struct mtk_ppe *ppe, u32 ib1)\n+{\n+\tu16 timestamp;\n+\tu16 now;\n+\n+\tnow = mtk_eth_timestamp(ppe->eth) & MTK_FOE_IB1_BIND_TIMESTAMP;\n+\ttimestamp = ib1 & MTK_FOE_IB1_BIND_TIMESTAMP;\n+\n+\tif (timestamp > now)\n+\t\treturn MTK_FOE_IB1_BIND_TIMESTAMP + 1 - timestamp + now;\n+\telse\n+\t\treturn now - timestamp;\n+}\n+\n+static void\n+mtk_flow_entry_update_l2(struct mtk_ppe *ppe, struct mtk_flow_entry *entry)\n+{\n+\tstruct mtk_flow_entry *cur;\n+\tstruct mtk_foe_entry *hwe;\n+\tstruct hlist_node *tmp;\n+\tint idle;\n+\n+\tidle = __mtk_foe_entry_idle_time(ppe, entry->data.ib1);\n+\thlist_for_each_entry_safe(cur, tmp, &entry->l2_flows, l2_data.list) {\n+\t\tint cur_idle;\n+\t\tu32 ib1;\n+\n+\t\thwe = &ppe->foe_table[cur->hash];\n+\t\tib1 = READ_ONCE(hwe->ib1);\n+\n+\t\tif (FIELD_GET(MTK_FOE_IB1_STATE, ib1) != MTK_FOE_STATE_BIND) {\n+\t\t\tcur->hash = 0xffff;\n+\t\t\t__mtk_foe_entry_clear(ppe, cur);\n+\t\t\tcontinue;\n+\t\t}\n+\n+\t\tcur_idle = __mtk_foe_entry_idle_time(ppe, ib1);\n+\t\tif (cur_idle >= idle)\n+\t\t\tcontinue;\n+\n+\t\tidle = cur_idle;\n+\t\tentry->data.ib1 &= ~MTK_FOE_IB1_BIND_TIMESTAMP;\n+\t\tentry->data.ib1 |= hwe->ib1 & MTK_FOE_IB1_BIND_TIMESTAMP;\n+\t}\n+}\n+\n+static void\n mtk_flow_entry_update(struct mtk_ppe *ppe, struct mtk_flow_entry *entry)\n {\n \tstruct mtk_foe_entry *hwe;\n \tstruct mtk_foe_entry foe;\n \n \tspin_lock_bh(&ppe_lock);\n+\n+\tif (entry->type == MTK_FLOW_TYPE_L2) {\n+\t\tmtk_flow_entry_update_l2(ppe, entry);\n+\t\tgoto out;\n+\t}\n+\n \tif (entry->hash == 0xffff)\n \t\tgoto out;\n \n@@ -419,21 +524,28 @@ __mtk_foe_entry_commit(struct mtk_ppe *p\n void mtk_foe_entry_clear(struct mtk_ppe *ppe, struct mtk_flow_entry *entry)\n {\n \tspin_lock_bh(&ppe_lock);\n-\thlist_del_init(&entry->list);\n-\tif (entry->hash != 0xffff) {\n-\t\tppe->foe_table[entry->hash].ib1 &= ~MTK_FOE_IB1_STATE;\n-\t\tppe->foe_table[entry->hash].ib1 |= FIELD_PREP(MTK_FOE_IB1_STATE,\n-\t\t\t\t\t\t\t      MTK_FOE_STATE_BIND);\n-\t\tdma_wmb();\n-\t}\n-\tentry->hash = 0xffff;\n+\t__mtk_foe_entry_clear(ppe, entry);\n \tspin_unlock_bh(&ppe_lock);\n }\n \n+static int\n+mtk_foe_entry_commit_l2(struct mtk_ppe *ppe, struct mtk_flow_entry *entry)\n+{\n+\tentry->type = MTK_FLOW_TYPE_L2;\n+\n+\treturn rhashtable_insert_fast(&ppe->l2_flows, &entry->l2_node,\n+\t\t\t\t      mtk_flow_l2_ht_params);\n+}\n+\n int mtk_foe_entry_commit(struct mtk_ppe *ppe, struct mtk_flow_entry *entry)\n {\n-\tu32 hash = mtk_ppe_hash_entry(&entry->data);\n+\tint type = FIELD_GET(MTK_FOE_IB1_PACKET_TYPE, entry->data.ib1);\n+\tu32 hash;\n+\n+\tif (type == MTK_PPE_PKT_TYPE_BRIDGE)\n+\t\treturn mtk_foe_entry_commit_l2(ppe, entry);\n \n+\thash = mtk_ppe_hash_entry(&entry->data);\n \tentry->hash = 0xffff;\n \tspin_lock_bh(&ppe_lock);\n \thlist_add_head(&entry->list, &ppe->foe_flow[hash / 2]);\n@@ -442,18 +554,72 @@ int mtk_foe_entry_commit(struct mtk_ppe\n \treturn 0;\n }\n \n+static void\n+mtk_foe_entry_commit_subflow(struct mtk_ppe *ppe, struct mtk_flow_entry *entry,\n+\t\t\t     u16 hash)\n+{\n+\tstruct mtk_flow_entry *flow_info;\n+\tstruct mtk_foe_entry foe, *hwe;\n+\tstruct mtk_foe_mac_info *l2;\n+\tu32 ib1_mask = MTK_FOE_IB1_PACKET_TYPE | MTK_FOE_IB1_UDP;\n+\tint type;\n+\n+\tflow_info = kzalloc(offsetof(struct mtk_flow_entry, l2_data.end),\n+\t\t\t    GFP_ATOMIC);\n+\tif (!flow_info)\n+\t\treturn;\n+\n+\tflow_info->l2_data.base_flow = entry;\n+\tflow_info->type = MTK_FLOW_TYPE_L2_SUBFLOW;\n+\tflow_info->hash = hash;\n+\thlist_add_head(&flow_info->list, &ppe->foe_flow[hash / 2]);\n+\thlist_add_head(&flow_info->l2_data.list, &entry->l2_flows);\n+\n+\thwe = &ppe->foe_table[hash];\n+\tmemcpy(&foe, hwe, sizeof(foe));\n+\tfoe.ib1 &= ib1_mask;\n+\tfoe.ib1 |= entry->data.ib1 & ~ib1_mask;\n+\n+\tl2 = mtk_foe_entry_l2(&foe);\n+\tmemcpy(l2, &entry->data.bridge.l2, sizeof(*l2));\n+\n+\ttype = FIELD_GET(MTK_FOE_IB1_PACKET_TYPE, foe.ib1);\n+\tif (type == MTK_PPE_PKT_TYPE_IPV4_HNAPT)\n+\t\tmemcpy(&foe.ipv4.new, &foe.ipv4.orig, sizeof(foe.ipv4.new));\n+\telse if (type >= MTK_PPE_PKT_TYPE_IPV6_ROUTE_3T && l2->etype == ETH_P_IP)\n+\t\tl2->etype = ETH_P_IPV6;\n+\n+\t*mtk_foe_entry_ib2(&foe) = entry->data.bridge.ib2;\n+\n+\t__mtk_foe_entry_commit(ppe, &foe, hash);\n+}\n+\n void __mtk_ppe_check_skb(struct mtk_ppe *ppe, struct sk_buff *skb, u16 hash)\n {\n \tstruct hlist_head *head = &ppe->foe_flow[hash / 2];\n-\tstruct mtk_flow_entry *entry;\n \tstruct mtk_foe_entry *hwe = &ppe->foe_table[hash];\n+\tstruct mtk_flow_entry *entry;\n+\tstruct mtk_foe_bridge key = {};\n+\tstruct ethhdr *eh;\n \tbool found = false;\n-\n-\tif (hlist_empty(head))\n-\t\treturn;\n+\tu8 *tag;\n \n \tspin_lock_bh(&ppe_lock);\n+\n+\tif (FIELD_GET(MTK_FOE_IB1_STATE, hwe->ib1) == MTK_FOE_STATE_BIND)\n+\t\tgoto out;\n+\n \thlist_for_each_entry(entry, head, list) {\n+\t\tif (entry->type == MTK_FLOW_TYPE_L2_SUBFLOW) {\n+\t\t\tif (unlikely(FIELD_GET(MTK_FOE_IB1_STATE, hwe->ib1) ==\n+\t\t\t\t     MTK_FOE_STATE_BIND))\n+\t\t\t\tcontinue;\n+\n+\t\t\tentry->hash = 0xffff;\n+\t\t\t__mtk_foe_entry_clear(ppe, entry);\n+\t\t\tcontinue;\n+\t\t}\n+\n \t\tif (found || !mtk_flow_entry_match(entry, hwe)) {\n \t\t\tif (entry->hash != 0xffff)\n \t\t\t\tentry->hash = 0xffff;\n@@ -464,21 +630,50 @@ void __mtk_ppe_check_skb(struct mtk_ppe\n \t\t__mtk_foe_entry_commit(ppe, &entry->data, hash);\n \t\tfound = true;\n \t}\n+\n+\tif (found)\n+\t\tgoto out;\n+\n+\teh = eth_hdr(skb);\n+\tether_addr_copy(key.dest_mac, eh->h_dest);\n+\tether_addr_copy(key.src_mac, eh->h_source);\n+\ttag = skb->data - 2;\n+\tkey.vlan = 0;\n+\tswitch (skb->protocol) {\n+#if IS_ENABLED(CONFIG_NET_DSA)\n+\tcase htons(ETH_P_XDSA):\n+\t\tif (!netdev_uses_dsa(skb->dev) ||\n+\t\t    skb->dev->dsa_ptr->tag_ops->proto != DSA_TAG_PROTO_MTK)\n+\t\t\tgoto out;\n+\n+\t\ttag += 4;\n+\t\tif (get_unaligned_be16(tag) != ETH_P_8021Q)\n+\t\t\tbreak;\n+\n+\t\tfallthrough;\n+#endif\n+\tcase htons(ETH_P_8021Q):\n+\t\tkey.vlan = get_unaligned_be16(tag + 2) & VLAN_VID_MASK;\n+\t\tbreak;\n+\tdefault:\n+\t\tbreak;\n+\t}\n+\n+\tentry = rhashtable_lookup_fast(&ppe->l2_flows, &key, mtk_flow_l2_ht_params);\n+\tif (!entry)\n+\t\tgoto out;\n+\n+\tmtk_foe_entry_commit_subflow(ppe, entry, hash);\n+\n+out:\n \tspin_unlock_bh(&ppe_lock);\n }\n \n int mtk_foe_entry_idle_time(struct mtk_ppe *ppe, struct mtk_flow_entry *entry)\n {\n-\tu16 now = mtk_eth_timestamp(ppe->eth) & MTK_FOE_IB1_BIND_TIMESTAMP;\n-\tu16 timestamp;\n-\n \tmtk_flow_entry_update(ppe, entry);\n-\ttimestamp = entry->data.ib1 & MTK_FOE_IB1_BIND_TIMESTAMP;\n \n-\tif (timestamp > now)\n-\t\treturn MTK_FOE_IB1_BIND_TIMESTAMP + 1 - timestamp + now;\n-\telse\n-\t\treturn now - timestamp;\n+\treturn __mtk_foe_entry_idle_time(ppe, entry->data.ib1);\n }\n \n struct mtk_ppe *mtk_ppe_init(struct mtk_eth *eth, void __iomem *base,\n@@ -492,6 +687,8 @@ struct mtk_ppe *mtk_ppe_init(struct mtk_\n \tif (!ppe)\n \t\treturn NULL;\n \n+\trhashtable_init(&ppe->l2_flows, &mtk_flow_l2_ht_params);\n+\n \t/* need to allocate a separate device, since it PPE DMA access is\n \t * not coherent.\n \t */\n--- a/drivers/net/ethernet/mediatek/mtk_ppe.h\n+++ b/drivers/net/ethernet/mediatek/mtk_ppe.h\n@@ -6,6 +6,7 @@\n \n #include <linux/kernel.h>\n #include <linux/bitfield.h>\n+#include <linux/rhashtable.h>\n \n #define MTK_ETH_PPE_BASE\t\t0xc00\n \n@@ -84,19 +85,16 @@ struct mtk_foe_mac_info {\n \tu16 src_mac_lo;\n };\n \n+/* software-only entry type */\n struct mtk_foe_bridge {\n-\tu32 dest_mac_hi;\n-\n-\tu16 src_mac_lo;\n-\tu16 dest_mac_lo;\n+\tu8 dest_mac[ETH_ALEN];\n+\tu8 src_mac[ETH_ALEN];\n+\tu16 vlan;\n \n-\tu32 src_mac_hi;\n+\tstruct {} key_end;\n \n \tu32 ib2;\n \n-\tu32 _rsv[5];\n-\n-\tu32 udf_tsid;\n \tstruct mtk_foe_mac_info l2;\n };\n \n@@ -235,13 +233,33 @@ enum {\n \tMTK_PPE_CPU_REASON_INVALID\t\t\t= 0x1f,\n };\n \n+enum {\n+\tMTK_FLOW_TYPE_L4,\n+\tMTK_FLOW_TYPE_L2,\n+\tMTK_FLOW_TYPE_L2_SUBFLOW,\n+};\n+\n struct mtk_flow_entry {\n+\tunion {\n+\t\tstruct hlist_node list;\n+\t\tstruct {\n+\t\t\tstruct rhash_head l2_node;\n+\t\t\tstruct hlist_head l2_flows;\n+\t\t};\n+\t};\n+\tu8 type;\n+\ts8 wed_index;\n+\tu16 hash;\n+\tunion {\n+\t\tstruct mtk_foe_entry data;\n+\t\tstruct {\n+\t\t\tstruct mtk_flow_entry *base_flow;\n+\t\t\tstruct hlist_node list;\n+\t\t\tstruct {} end;\n+\t\t} l2_data;\n+\t};\n \tstruct rhash_head node;\n-\tstruct hlist_node list;\n \tunsigned long cookie;\n-\tstruct mtk_foe_entry data;\n-\tu16 hash;\n-\ts8 wed_index;\n };\n \n struct mtk_ppe {\n@@ -256,6 +274,8 @@ struct mtk_ppe {\n \tu16 foe_check_time[MTK_PPE_ENTRIES];\n \tstruct hlist_head foe_flow[MTK_PPE_ENTRIES / 2];\n \n+\tstruct rhashtable l2_flows;\n+\n \tvoid *acct_table;\n };\n \n--- a/drivers/net/ethernet/mediatek/mtk_ppe_offload.c\n+++ b/drivers/net/ethernet/mediatek/mtk_ppe_offload.c\n@@ -31,6 +31,8 @@ struct mtk_flow_data {\n \t__be16 src_port;\n \t__be16 dst_port;\n \n+\tu16 vlan_in;\n+\n \tstruct {\n \t\tu16 id;\n \t\t__be16 proto;\n@@ -257,9 +259,45 @@ mtk_flow_offload_replace(struct mtk_eth\n \t\treturn -EOPNOTSUPP;\n \t}\n \n+\tswitch (addr_type) {\n+\tcase 0:\n+\t\toffload_type = MTK_PPE_PKT_TYPE_BRIDGE;\n+\t\tif (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) {\n+\t\t\tstruct flow_match_eth_addrs match;\n+\n+\t\t\tflow_rule_match_eth_addrs(rule, &match);\n+\t\t\tmemcpy(data.eth.h_dest, match.key->dst, ETH_ALEN);\n+\t\t\tmemcpy(data.eth.h_source, match.key->src, ETH_ALEN);\n+\t\t} else {\n+\t\t\treturn -EOPNOTSUPP;\n+\t\t}\n+\n+\t\tif (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN)) {\n+\t\t\tstruct flow_match_vlan match;\n+\n+\t\t\tflow_rule_match_vlan(rule, &match);\n+\n+\t\t\tif (match.key->vlan_tpid != cpu_to_be16(ETH_P_8021Q))\n+\t\t\t\treturn -EOPNOTSUPP;\n+\n+\t\t\tdata.vlan_in = match.key->vlan_id;\n+\t\t}\n+\t\tbreak;\n+\tcase FLOW_DISSECTOR_KEY_IPV4_ADDRS:\n+\t\toffload_type = MTK_PPE_PKT_TYPE_IPV4_HNAPT;\n+\t\tbreak;\n+\tcase FLOW_DISSECTOR_KEY_IPV6_ADDRS:\n+\t\toffload_type = MTK_PPE_PKT_TYPE_IPV6_ROUTE_5T;\n+\t\tbreak;\n+\tdefault:\n+\t\treturn -EOPNOTSUPP;\n+\t}\n+\n \tflow_action_for_each(i, act, &rule->action) {\n \t\tswitch (act->id) {\n \t\tcase FLOW_ACTION_MANGLE:\n+\t\t\tif (offload_type == MTK_PPE_PKT_TYPE_BRIDGE)\n+\t\t\t\treturn -EOPNOTSUPP;\n \t\t\tif (act->mangle.htype == FLOW_ACT_MANGLE_HDR_TYPE_ETH)\n \t\t\t\tmtk_flow_offload_mangle_eth(act, &data.eth);\n \t\t\tbreak;\n@@ -291,17 +329,6 @@ mtk_flow_offload_replace(struct mtk_eth\n \t\t}\n \t}\n \n-\tswitch (addr_type) {\n-\tcase FLOW_DISSECTOR_KEY_IPV4_ADDRS:\n-\t\toffload_type = MTK_PPE_PKT_TYPE_IPV4_HNAPT;\n-\t\tbreak;\n-\tcase FLOW_DISSECTOR_KEY_IPV6_ADDRS:\n-\t\toffload_type = MTK_PPE_PKT_TYPE_IPV6_ROUTE_5T;\n-\t\tbreak;\n-\tdefault:\n-\t\treturn -EOPNOTSUPP;\n-\t}\n-\n \tif (!is_valid_ether_addr(data.eth.h_source) ||\n \t    !is_valid_ether_addr(data.eth.h_dest))\n \t\treturn -EINVAL;\n@@ -315,10 +342,13 @@ mtk_flow_offload_replace(struct mtk_eth\n \tif (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_PORTS)) {\n \t\tstruct flow_match_ports ports;\n \n+\t\tif (offload_type == MTK_PPE_PKT_TYPE_BRIDGE)\n+\t\t\treturn -EOPNOTSUPP;\n+\n \t\tflow_rule_match_ports(rule, &ports);\n \t\tdata.src_port = ports.key->src;\n \t\tdata.dst_port = ports.key->dst;\n-\t} else {\n+\t} else if (offload_type != MTK_PPE_PKT_TYPE_BRIDGE) {\n \t\treturn -EOPNOTSUPP;\n \t}\n \n@@ -348,6 +378,9 @@ mtk_flow_offload_replace(struct mtk_eth\n \t\tif (act->id != FLOW_ACTION_MANGLE)\n \t\t\tcontinue;\n \n+\t\tif (offload_type == MTK_PPE_PKT_TYPE_BRIDGE)\n+\t\t\treturn -EOPNOTSUPP;\n+\n \t\tswitch (act->mangle.htype) {\n \t\tcase FLOW_ACT_MANGLE_HDR_TYPE_TCP:\n \t\tcase FLOW_ACT_MANGLE_HDR_TYPE_UDP:\n@@ -373,6 +406,9 @@ mtk_flow_offload_replace(struct mtk_eth\n \t\t\treturn err;\n \t}\n \n+\tif (offload_type == MTK_PPE_PKT_TYPE_BRIDGE)\n+\t\tfoe.bridge.vlan = data.vlan_in;\n+\n \tif (data.vlan.num == 1) {\n \t\tif (data.vlan.proto != htons(ETH_P_8021Q))\n \t\t\treturn -EOPNOTSUPP;\n"
  },
  {
    "path": "target/linux/generic/pending-5.15/702-net-ethernet-mtk_eth_soc-enable-threaded-NAPI.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nDate: Mon, 21 Mar 2022 20:39:59 +0100\nSubject: [PATCH] net: ethernet: mtk_eth_soc: enable threaded NAPI\n\nThis can improve performance under load by ensuring that NAPI processing is\nnot pinned on CPU 0.\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n\n--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c\n+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c\n@@ -2186,8 +2186,8 @@ static irqreturn_t mtk_handle_irq_rx(int\n \n \teth->rx_events++;\n \tif (likely(napi_schedule_prep(&eth->rx_napi))) {\n-\t\t__napi_schedule(&eth->rx_napi);\n \t\tmtk_rx_irq_disable(eth, MTK_RX_DONE_INT);\n+\t\t__napi_schedule(&eth->rx_napi);\n \t}\n \n \treturn IRQ_HANDLED;\n@@ -2199,8 +2199,8 @@ static irqreturn_t mtk_handle_irq_tx(int\n \n \teth->tx_events++;\n \tif (likely(napi_schedule_prep(&eth->tx_napi))) {\n-\t\t__napi_schedule(&eth->tx_napi);\n \t\tmtk_tx_irq_disable(eth, MTK_TX_DONE_INT);\n+\t\t__napi_schedule(&eth->tx_napi);\n \t}\n \n \treturn IRQ_HANDLED;\n@@ -3313,6 +3313,8 @@ static int mtk_probe(struct platform_dev\n \t * for NAPI to work\n \t */\n \tinit_dummy_netdev(&eth->dummy_dev);\n+\teth->dummy_dev.threaded = 1;\n+\tstrcpy(eth->dummy_dev.name, \"mtk_eth\");\n \tnetif_napi_add(&eth->dummy_dev, &eth->tx_napi, mtk_napi_tx,\n \t\t       MTK_NAPI_WEIGHT);\n \tnetif_napi_add(&eth->dummy_dev, &eth->rx_napi, mtk_napi_rx,\n"
  },
  {
    "path": "target/linux/generic/pending-5.15/703-phy-add-detach-callback-to-struct-phy_driver.patch",
    "content": "From: Gabor Juhos <juhosg@openwrt.org>\nSubject: generic: add detach callback to struct phy_driver\n\nlede-commit: fe61fc2d7d0b3fb348b502f68f98243b3ddf5867\n\nSigned-off-by: Gabor Juhos <juhosg@openwrt.org>\n---\n drivers/net/phy/phy_device.c | 3 +++\n include/linux/phy.h          | 6 ++++++\n 2 files changed, 9 insertions(+)\n\n--- a/drivers/net/phy/phy_device.c\n+++ b/drivers/net/phy/phy_device.c\n@@ -1715,6 +1715,9 @@ void phy_detach(struct phy_device *phyde\n \tstruct module *ndev_owner = NULL;\n \tstruct mii_bus *bus;\n \n+\tif (phydev->drv && phydev->drv->detach)\n+\t\tphydev->drv->detach(phydev);\n+\n \tif (phydev->sysfs_links) {\n \t\tif (dev)\n \t\t\tsysfs_remove_link(&dev->dev.kobj, \"phydev\");\n--- a/include/linux/phy.h\n+++ b/include/linux/phy.h\n@@ -783,6 +783,12 @@ struct phy_driver {\n \t/** @handle_interrupt: Override default interrupt handling */\n \tirqreturn_t (*handle_interrupt)(struct phy_device *phydev);\n \n+\t/*\n+\t * Called before an ethernet device is detached\n+\t * from the PHY.\n+\t */\n+\tvoid (*detach)(struct phy_device *phydev);\n+\n \t/** @remove: Clears up any memory if needed */\n \tvoid (*remove)(struct phy_device *phydev);\n \n"
  },
  {
    "path": "target/linux/generic/pending-5.15/704-00-netfilter-flowtable-fix-excessive-hw-offload-attempt.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nDate: Fri, 6 May 2022 12:37:23 +0200\nSubject: [PATCH] netfilter: flowtable: fix excessive hw offload attempts\n after failure\n\nIf a flow cannot be offloaded, the code currently repeatedly tries again as\nquickly as possible, which can significantly increase system load.\nFix this by limiting flow timeout update and hardware offload retry to once\nper second.\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n\n--- a/net/netfilter/nf_flow_table_core.c\n+++ b/net/netfilter/nf_flow_table_core.c\n@@ -329,8 +329,10 @@ void flow_offload_refresh(struct nf_flow\n \tu32 timeout;\n \n \ttimeout = nf_flowtable_time_stamp + flow_offload_get_timeout(flow);\n-\tif (READ_ONCE(flow->timeout) != timeout)\n+\tif (timeout - READ_ONCE(flow->timeout) > HZ)\n \t\tWRITE_ONCE(flow->timeout, timeout);\n+\telse\n+\t\treturn;\n \n \tif (likely(!nf_flowtable_hw_offload(flow_table)))\n \t\treturn;\n"
  },
  {
    "path": "target/linux/generic/pending-5.15/704-01-netfilter-nft_flow_offload-skip-dst-neigh-lookup-for.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nDate: Fri, 6 May 2022 12:43:58 +0200\nSubject: [PATCH] netfilter: nft_flow_offload: skip dst neigh lookup for\n ppp devices\n\nThe dst entry does not contain a valid hardware address, so skip the lookup\nin order to avoid running into errors here.\nThe proper hardware address is filled in from nft_dev_path_info\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n\n--- a/net/netfilter/nft_flow_offload.c\n+++ b/net/netfilter/nft_flow_offload.c\n@@ -36,6 +36,15 @@ static void nft_default_forward_path(str\n \troute->tuple[dir].xmit_type\t= nft_xmit_type(dst_cache);\n }\n \n+static bool nft_is_valid_ether_device(const struct net_device *dev)\n+{\n+\tif (!dev || (dev->flags & IFF_LOOPBACK) || dev->type != ARPHRD_ETHER ||\n+\t    dev->addr_len != ETH_ALEN || !is_valid_ether_addr(dev->dev_addr))\n+\t\treturn false;\n+\n+\treturn true;\n+}\n+\n static int nft_dev_fill_forward_path(const struct nf_flow_route *route,\n \t\t\t\t     const struct dst_entry *dst_cache,\n \t\t\t\t     const struct nf_conn *ct,\n@@ -47,6 +56,9 @@ static int nft_dev_fill_forward_path(con\n \tstruct neighbour *n;\n \tu8 nud_state;\n \n+\tif (!nft_is_valid_ether_device(dev))\n+\t\tgoto out;\n+\n \tn = dst_neigh_lookup(dst_cache, daddr);\n \tif (!n)\n \t\treturn -1;\n@@ -60,6 +72,7 @@ static int nft_dev_fill_forward_path(con\n \tif (!(nud_state & NUD_VALID))\n \t\treturn -1;\n \n+out:\n \treturn dev_fill_forward_path(dev, ha, stack);\n }\n \n@@ -78,15 +91,6 @@ struct nft_forward_info {\n \tenum flow_offload_xmit_type xmit_type;\n };\n \n-static bool nft_is_valid_ether_device(const struct net_device *dev)\n-{\n-\tif (!dev || (dev->flags & IFF_LOOPBACK) || dev->type != ARPHRD_ETHER ||\n-\t    dev->addr_len != ETH_ALEN || !is_valid_ether_addr(dev->dev_addr))\n-\t\treturn false;\n-\n-\treturn true;\n-}\n-\n static void nft_dev_path_info(const struct net_device_path_stack *stack,\n \t\t\t      struct nft_forward_info *info,\n \t\t\t      unsigned char *ha, struct nf_flowtable *flowtable)\n"
  },
  {
    "path": "target/linux/generic/pending-5.15/704-02-net-fix-dev_fill_forward_path-with-pppoe-bridge.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nDate: Fri, 6 May 2022 13:54:44 +0200\nSubject: [PATCH] net: fix dev_fill_forward_path with pppoe + bridge\n\nWhen calling dev_fill_forward_path on a pppoe device, the provided destination\naddress is invalid. In order for the bridge fdb lookup to succeed, the pppoe\ncode needs to update ctx->daddr to the correct value.\nFix this by storing the address inside struct net_device_path_ctx\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n\n--- a/drivers/net/ethernet/mediatek/mtk_ppe_offload.c\n+++ b/drivers/net/ethernet/mediatek/mtk_ppe_offload.c\n@@ -90,7 +90,6 @@ mtk_flow_get_wdma_info(struct net_device\n {\n \tstruct net_device_path_ctx ctx = {\n \t\t.dev = dev,\n-\t\t.daddr = addr,\n \t};\n \tstruct net_device_path path = {};\n \n@@ -100,6 +99,7 @@ mtk_flow_get_wdma_info(struct net_device\n \tif (!dev->netdev_ops->ndo_fill_forward_path)\n \t\treturn -1;\n \n+\tmemcpy(ctx.daddr, addr, sizeof(ctx.daddr));\n \tif (dev->netdev_ops->ndo_fill_forward_path(&ctx, &path))\n \t\treturn -1;\n \n--- a/drivers/net/ppp/pppoe.c\n+++ b/drivers/net/ppp/pppoe.c\n@@ -988,6 +988,7 @@ static int pppoe_fill_forward_path(struc\n \tpath->encap.proto = htons(ETH_P_PPP_SES);\n \tpath->encap.id = be16_to_cpu(po->num);\n \tmemcpy(path->encap.h_dest, po->pppoe_pa.remote, ETH_ALEN);\n+\tmemcpy(ctx->daddr, po->pppoe_pa.remote, ETH_ALEN);\n \tpath->dev = ctx->dev;\n \tctx->dev = dev;\n \n--- a/include/linux/netdevice.h\n+++ b/include/linux/netdevice.h\n@@ -894,7 +894,7 @@ struct net_device_path_stack {\n \n struct net_device_path_ctx {\n \tconst struct net_device *dev;\n-\tconst u8\t\t*daddr;\n+\tu8\t\t\tdaddr[ETH_ALEN];\n \n \tint\t\t\tnum_vlans;\n \tstruct {\n--- a/net/core/dev.c\n+++ b/net/core/dev.c\n@@ -741,11 +741,11 @@ int dev_fill_forward_path(const struct n\n \tconst struct net_device *last_dev;\n \tstruct net_device_path_ctx ctx = {\n \t\t.dev\t= dev,\n-\t\t.daddr\t= daddr,\n \t};\n \tstruct net_device_path *path;\n \tint ret = 0;\n \n+\tmemcpy(ctx.daddr, daddr, sizeof(ctx.daddr));\n \tstack->num_paths = 0;\n \twhile (ctx.dev && ctx.dev->netdev_ops->ndo_fill_forward_path) {\n \t\tlast_dev = ctx.dev;\n"
  },
  {
    "path": "target/linux/generic/pending-5.15/704-03-netfilter-nft_flow_offload-fix-offload-with-pppoe-vl.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nDate: Fri, 6 May 2022 15:15:06 +0200\nSubject: [PATCH] netfilter: nft_flow_offload: fix offload with pppoe +\n vlan\n\nWhen running a combination of PPPoE on top of a VLAN, we need to set\ninfo->outdev to the PPPoE device, otherwise PPPoE encap is skipped\nduring software offload.\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n\n--- a/net/netfilter/nft_flow_offload.c\n+++ b/net/netfilter/nft_flow_offload.c\n@@ -123,7 +123,8 @@ static void nft_dev_path_info(const stru\n \t\t\t\tinfo->indev = NULL;\n \t\t\t\tbreak;\n \t\t\t}\n-\t\t\tinfo->outdev = path->dev;\n+\t\t\tif (!info->outdev)\n+\t\t\t\tinfo->outdev = path->dev;\n \t\t\tinfo->encap[info->num_encaps].id = path->encap.id;\n \t\t\tinfo->encap[info->num_encaps].proto = path->encap.proto;\n \t\t\tinfo->num_encaps++;\n"
  },
  {
    "path": "target/linux/generic/pending-5.15/705-net-dsa-tag_mtk-add-padding-for-tx-packets.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nDate: Fri, 6 May 2022 21:38:42 +0200\nSubject: [PATCH] net: dsa: tag_mtk: add padding for tx packets\n\nPadding for transmitted packets needs to account for the special tag.\nWith not enough padding, garbage bytes are inserted by the switch at the\nend of small packets.\n\nFixes: 5cd8985a1909 (\"net-next: dsa: add Mediatek tag RX/TX handler\")\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n\n--- a/net/dsa/tag_mtk.c\n+++ b/net/dsa/tag_mtk.c\n@@ -25,6 +25,14 @@ static struct sk_buff *mtk_tag_xmit(stru\n \tu8 xmit_tpid;\n \tu8 *mtk_tag;\n \n+\t/* The Ethernet switch we are interfaced with needs packets to be at\n+\t * least 64 bytes (including FCS) otherwise their padding might be\n+\t * corrupted. With tags enabled, we need to make sure that packets are\n+\t * at least 68 bytes (including FCS and tag).\n+\t */\n+\tif (__skb_put_padto(skb, ETH_ZLEN + MTK_HDR_LEN, false))\n+\t\treturn NULL;\n+\n \t/* Build the special tag after the MAC Source Address. If VLAN header\n \t * is present, it's required that VLAN header and special tag is\n \t * being combined. Only in this way we can allow the switch can parse\n"
  },
  {
    "path": "target/linux/generic/pending-5.15/710-bridge-add-knob-for-filtering-rx-tx-BPDU-pack.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nDate: Fri, 27 Aug 2021 12:22:32 +0200\nSubject: [PATCH] bridge: add knob for filtering rx/tx BPDU packets on a port\n\nSome devices (e.g. wireless APs) can't have devices behind them be part of\na bridge topology with redundant links, due to address limitations.\nAdditionally, broadcast traffic on these devices is somewhat expensive, due to\nthe low data rate and wakeups of clients in powersave mode.\nThis knob can be used to ensure that BPDU packets are never sent or forwarded\nto/from these devices\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n\n--- a/include/linux/if_bridge.h\n+++ b/include/linux/if_bridge.h\n@@ -58,6 +58,7 @@ struct br_ip_list {\n #define BR_MRP_LOST_CONT\tBIT(18)\n #define BR_MRP_LOST_IN_CONT\tBIT(19)\n #define BR_TX_FWD_OFFLOAD\tBIT(20)\n+#define BR_BPDU_FILTER\t\tBIT(21)\n \n #define BR_DEFAULT_AGEING_TIME\t(300 * HZ)\n \n--- a/net/bridge/br_forward.c\n+++ b/net/bridge/br_forward.c\n@@ -199,6 +199,7 @@ out:\n void br_flood(struct net_bridge *br, struct sk_buff *skb,\n \t      enum br_pkt_type pkt_type, bool local_rcv, bool local_orig)\n {\n+\tconst unsigned char *dest = eth_hdr(skb)->h_dest;\n \tstruct net_bridge_port *prev = NULL;\n \tstruct net_bridge_port *p;\n \n@@ -214,6 +215,10 @@ void br_flood(struct net_bridge *br, str\n \t\tcase BR_PKT_MULTICAST:\n \t\t\tif (!(p->flags & BR_MCAST_FLOOD) && skb->dev != br->dev)\n \t\t\t\tcontinue;\n+\t\t\tif ((p->flags & BR_BPDU_FILTER) &&\n+\t\t\t    unlikely(is_link_local_ether_addr(dest) &&\n+\t\t\t\t     dest[5] == 0))\n+\t\t\t\tcontinue;\n \t\t\tbreak;\n \t\tcase BR_PKT_BROADCAST:\n \t\t\tif (!(p->flags & BR_BCAST_FLOOD) && skb->dev != br->dev)\n--- a/net/bridge/br_input.c\n+++ b/net/bridge/br_input.c\n@@ -319,6 +319,8 @@ static rx_handler_result_t br_handle_fra\n \t\tfwd_mask |= p->group_fwd_mask;\n \t\tswitch (dest[5]) {\n \t\tcase 0x00:\t/* Bridge Group Address */\n+\t\t\tif (p->flags & BR_BPDU_FILTER)\n+\t\t\t\tgoto drop;\n \t\t\t/* If STP is turned off,\n \t\t\t   then must forward to keep loop detection */\n \t\t\tif (p->br->stp_enabled == BR_NO_STP ||\n--- a/net/bridge/br_sysfs_if.c\n+++ b/net/bridge/br_sysfs_if.c\n@@ -240,6 +240,7 @@ BRPORT_ATTR_FLAG(multicast_flood, BR_MCA\n BRPORT_ATTR_FLAG(broadcast_flood, BR_BCAST_FLOOD);\n BRPORT_ATTR_FLAG(neigh_suppress, BR_NEIGH_SUPPRESS);\n BRPORT_ATTR_FLAG(isolated, BR_ISOLATED);\n+BRPORT_ATTR_FLAG(bpdu_filter, BR_BPDU_FILTER);\n \n #ifdef CONFIG_BRIDGE_IGMP_SNOOPING\n static ssize_t show_multicast_router(struct net_bridge_port *p, char *buf)\n@@ -292,6 +293,7 @@ static const struct brport_attribute *br\n \t&brport_attr_group_fwd_mask,\n \t&brport_attr_neigh_suppress,\n \t&brport_attr_isolated,\n+\t&brport_attr_bpdu_filter,\n \t&brport_attr_backup_port,\n \tNULL\n };\n--- a/net/bridge/br_stp_bpdu.c\n+++ b/net/bridge/br_stp_bpdu.c\n@@ -80,7 +80,8 @@ void br_send_config_bpdu(struct net_brid\n {\n \tunsigned char buf[35];\n \n-\tif (p->br->stp_enabled != BR_KERNEL_STP)\n+\tif (p->br->stp_enabled != BR_KERNEL_STP ||\n+\t    (p->flags & BR_BPDU_FILTER))\n \t\treturn;\n \n \tbuf[0] = 0;\n@@ -127,7 +128,8 @@ void br_send_tcn_bpdu(struct net_bridge_\n {\n \tunsigned char buf[4];\n \n-\tif (p->br->stp_enabled != BR_KERNEL_STP)\n+\tif (p->br->stp_enabled != BR_KERNEL_STP ||\n+\t    (p->flags & BR_BPDU_FILTER))\n \t\treturn;\n \n \tbuf[0] = 0;\n@@ -172,6 +174,9 @@ void br_stp_rcv(const struct stp_proto *\n \tif (!(br->dev->flags & IFF_UP))\n \t\tgoto out;\n \n+\tif (p->flags & BR_BPDU_FILTER)\n+\t\tgoto out;\n+\n \tif (p->state == BR_STATE_DISABLED)\n \t\tgoto out;\n \n--- a/include/uapi/linux/if_link.h\n+++ b/include/uapi/linux/if_link.h\n@@ -536,6 +536,7 @@ enum {\n \tIFLA_BRPORT_MRP_IN_OPEN,\n \tIFLA_BRPORT_MCAST_EHT_HOSTS_LIMIT,\n \tIFLA_BRPORT_MCAST_EHT_HOSTS_CNT,\n+\tIFLA_BRPORT_BPDU_FILTER,\n \t__IFLA_BRPORT_MAX\n };\n #define IFLA_BRPORT_MAX (__IFLA_BRPORT_MAX - 1)\n--- a/net/bridge/br_netlink.c\n+++ b/net/bridge/br_netlink.c\n@@ -184,6 +184,7 @@ static inline size_t br_port_info_size(v\n \t\t+ nla_total_size(1)\t/* IFLA_BRPORT_VLAN_TUNNEL */\n \t\t+ nla_total_size(1)\t/* IFLA_BRPORT_NEIGH_SUPPRESS */\n \t\t+ nla_total_size(1)\t/* IFLA_BRPORT_ISOLATED */\n+\t\t+ nla_total_size(1)\t/* IFLA_BRPORT_BPDU_FILTER */\n \t\t+ nla_total_size(sizeof(struct ifla_bridge_id))\t/* IFLA_BRPORT_ROOT_ID */\n \t\t+ nla_total_size(sizeof(struct ifla_bridge_id))\t/* IFLA_BRPORT_BRIDGE_ID */\n \t\t+ nla_total_size(sizeof(u16))\t/* IFLA_BRPORT_DESIGNATED_PORT */\n@@ -269,7 +270,8 @@ static int br_port_fill_attrs(struct sk_\n \t\t\t\t\t\t\t  BR_MRP_LOST_CONT)) ||\n \t    nla_put_u8(skb, IFLA_BRPORT_MRP_IN_OPEN,\n \t\t       !!(p->flags & BR_MRP_LOST_IN_CONT)) ||\n-\t    nla_put_u8(skb, IFLA_BRPORT_ISOLATED, !!(p->flags & BR_ISOLATED)))\n+\t    nla_put_u8(skb, IFLA_BRPORT_ISOLATED, !!(p->flags & BR_ISOLATED)) ||\n+\t    nla_put_u8(skb, IFLA_BRPORT_BPDU_FILTER, !!(p->flags & BR_BPDU_FILTER)))\n \t\treturn -EMSGSIZE;\n \n \ttimerval = br_timer_value(&p->message_age_timer);\n@@ -829,6 +831,7 @@ static const struct nla_policy br_port_p\n \t[IFLA_BRPORT_ISOLATED]\t= { .type = NLA_U8 },\n \t[IFLA_BRPORT_BACKUP_PORT] = { .type = NLA_U32 },\n \t[IFLA_BRPORT_MCAST_EHT_HOSTS_LIMIT] = { .type = NLA_U32 },\n+\t[IFLA_BRPORT_BPDU_FILTER] = { .type = NLA_U8 },\n };\n \n /* Change the state of the port and notify spanning tree */\n@@ -893,6 +896,7 @@ static int br_setport(struct net_bridge_\n \tbr_set_port_flag(p, tb, IFLA_BRPORT_VLAN_TUNNEL, BR_VLAN_TUNNEL);\n \tbr_set_port_flag(p, tb, IFLA_BRPORT_NEIGH_SUPPRESS, BR_NEIGH_SUPPRESS);\n \tbr_set_port_flag(p, tb, IFLA_BRPORT_ISOLATED, BR_ISOLATED);\n+\tbr_set_port_flag(p, tb, IFLA_BRPORT_BPDU_FILTER, BR_BPDU_FILTER);\n \n \tchanged_mask = old_flags ^ p->flags;\n \n--- a/net/core/rtnetlink.c\n+++ b/net/core/rtnetlink.c\n@@ -55,7 +55,7 @@\n #include <net/net_namespace.h>\n \n #define RTNL_MAX_TYPE\t\t50\n-#define RTNL_SLAVE_MAX_TYPE\t40\n+#define RTNL_SLAVE_MAX_TYPE\t41\n \n struct rtnl_link {\n \trtnl_doit_func\t\tdoit;\n@@ -4700,7 +4700,9 @@ int ndo_dflt_bridge_getlink(struct sk_bu\n \t    brport_nla_put_flag(skb, flags, mask,\n \t\t\t\tIFLA_BRPORT_MCAST_FLOOD, BR_MCAST_FLOOD) ||\n \t    brport_nla_put_flag(skb, flags, mask,\n-\t\t\t\tIFLA_BRPORT_BCAST_FLOOD, BR_BCAST_FLOOD)) {\n+\t\t\t\tIFLA_BRPORT_BCAST_FLOOD, BR_BCAST_FLOOD) ||\n+\t    brport_nla_put_flag(skb, flags, mask,\n+\t\t\t\tIFLA_BRPORT_BPDU_FILTER, BR_BPDU_FILTER)) {\n \t\tnla_nest_cancel(skb, protinfo);\n \t\tgoto nla_put_failure;\n \t}\n"
  },
  {
    "path": "target/linux/generic/pending-5.15/760-net-dsa-mv88e6xxx-fix-vlan-setup.patch",
    "content": "From a1b291f3f6c80a6c5ccad7283fc472d77a2a4763 Mon Sep 17 00:00:00 2001\nFrom: Russell King <rmk+kernel@armlinux.org.uk>\nDate: Sun, 22 Dec 2019 12:40:11 +0000\nSubject: [PATCH] net: dsa: mv88e6xxx: fix vlan setup\n\nProvide an option that drivers can set to indicate they want to receive\nvlan configuration even when vlan filtering is disabled. This is safe\nfor Marvell DSA bridges, which do not look up ingress traffic in the\nVTU if the port is in 8021Q disabled state. Whether this change is\nsuitable for all DSA bridges is not known.\n\nSigned-off-by: Russell King <rmk+kernel@armlinux.org.uk>\nSigned-off-by: DENG Qingfang <dqfext@gmail.com>\n---\n drivers/net/dsa/mv88e6xxx/chip.c |  1 +\n 1 file changed, 1 insertion(+)\n\n--- a/drivers/net/dsa/mv88e6xxx/chip.c\n+++ b/drivers/net/dsa/mv88e6xxx/chip.c\n@@ -3193,6 +3193,7 @@ static int mv88e6xxx_setup(struct dsa_sw\n \n \tchip->ds = ds;\n \tds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip);\n+\tds->configure_vlan_while_not_filtering = true;\n \n \t/* Since virtual bridges are mapped in the PVT, the number we support\n \t * depends on the physical switch topology. We need to let DSA figure\n"
  },
  {
    "path": "target/linux/generic/pending-5.15/768-net-dsa-mv88e6xxx-Request-assisted-learning-on-CPU-port.patch",
    "content": "From:   Tobias Waldekranz <tobias@waldekranz.com>\nSubject: [RFC net-next 7/7] net: dsa: mv88e6xxx: Request assisted learning on CPU port\nDate:   Sat, 16 Jan 2021 02:25:15 +0100\nArchived-At: <https://lore.kernel.org/netdev/20210116012515.3152-8-tobias@waldekranz.com/>\n\nWhile the hardware is capable of performing learning on the CPU port,\nit requires alot of additions to the bridge's forwarding path in order\nto handle multi-destination traffic correctly.\n\nUntil that is in place, opt for the next best thing and let DSA sync\nthe relevant addresses down to the hardware FDB.\n\nSigned-off-by: Tobias Waldekranz <tobias@waldekranz.com>\n---\n drivers/net/dsa/mv88e6xxx/chip.c | 1 +\n 1 file changed, 1 insertion(+)\n\n--- a/drivers/net/dsa/mv88e6xxx/chip.c\n+++ b/drivers/net/dsa/mv88e6xxx/chip.c\n@@ -6320,6 +6320,7 @@ static int mv88e6xxx_register_switch(str\n \tds->ops = &mv88e6xxx_switch_ops;\n \tds->ageing_time_min = chip->info->age_time_coeff;\n \tds->ageing_time_max = chip->info->age_time_coeff * U8_MAX;\n+\tds->assisted_learning_on_cpu_port = true;\n \n \t/* Some chips support up to 32, but that requires enabling the\n \t * 5-bit port mode, which we do not support. 640k^W16 ought to\n"
  },
  {
    "path": "target/linux/generic/pending-5.15/780-ARM-kirkwood-add-missing-linux-if_ether.h-for-ETH_AL.patch",
    "content": "From patchwork Thu Aug  5 22:23:30 2021\nContent-Type: text/plain; charset=\"utf-8\"\nMIME-Version: 1.0\nContent-Transfer-Encoding: 7bit\nX-Patchwork-Submitter: Daniel Golle <daniel@makrotopia.org>\nX-Patchwork-Id: 12422209\nDate: Thu, 5 Aug 2021 23:23:30 +0100\nFrom: Daniel Golle <daniel@makrotopia.org>\nTo: linux-arm-kernel@lists.infradead.org, netdev@vger.kernel.org,\n linux-kernel@vger.kernel.org\nCc: \"David S. Miller\" <davem@davemloft.net>, Andrew Lunn <andrew@lunn.ch>,\n Michael Walle <michael@walle.cc>\nSubject: [PATCH] ARM: kirkwood: add missing <linux/if_ether.h> for ETH_ALEN\nMessage-ID: <YQxk4jrbm31NM1US@makrotopia.org>\nMIME-Version: 1.0\nContent-Disposition: inline\nX-BeenThere: linux-arm-kernel@lists.infradead.org\nX-Mailman-Version: 2.1.34\nPrecedence: list\nList-Id: <linux-arm-kernel.lists.infradead.org>\nList-Archive: <http://lists.infradead.org/pipermail/linux-arm-kernel/>\nSender: \"linux-arm-kernel\" <linux-arm-kernel-bounces@lists.infradead.org>\n\nAfter commit 83216e3988cd1 (\"of: net: pass the dst buffer to\nof_get_mac_address()\") build fails for kirkwood as ETH_ALEN is not\ndefined.\n\narch/arm/mach-mvebu/kirkwood.c: In function 'kirkwood_dt_eth_fixup':\narch/arm/mach-mvebu/kirkwood.c:87:13: error: 'ETH_ALEN' undeclared (first use in this function); did you mean 'ESTALE'?\n   u8 tmpmac[ETH_ALEN];\n             ^~~~~~~~\n             ESTALE\narch/arm/mach-mvebu/kirkwood.c:87:13: note: each undeclared identifier is reported only once for each function it appears in\narch/arm/mach-mvebu/kirkwood.c:87:6: warning: unused variable 'tmpmac' [-Wunused-variable]\n   u8 tmpmac[ETH_ALEN];\n      ^~~~~~\nmake[5]: *** [scripts/Makefile.build:262: arch/arm/mach-mvebu/kirkwood.o] Error 1\nmake[5]: *** Waiting for unfinished jobs....\n\nAdd missing #include <linux/if_ether.h> to fix this.\n\nCc: David S. Miller <davem@davemloft.net>\nCc: Andrew Lunn <andrew@lunn.ch>\nCc: Michael Walle <michael@walle.cc>\nReported-by: https://buildbot.openwrt.org/master/images/#/builders/56/builds/220/steps/44/logs/stdio\nFixes: 83216e3988cd1 (\"of: net: pass the dst buffer to of_get_mac_address()\")\nSigned-off-by: Daniel Golle <daniel@makrotopia.org>\n---\n arch/arm/mach-mvebu/kirkwood.c | 1 +\n 1 file changed, 1 insertion(+)\n\n--- a/arch/arm/mach-mvebu/kirkwood.c\n+++ b/arch/arm/mach-mvebu/kirkwood.c\n@@ -14,6 +14,7 @@\n #include <linux/kernel.h>\n #include <linux/init.h>\n #include <linux/mbus.h>\n+#include <linux/if_ether.h>\n #include <linux/of.h>\n #include <linux/of_address.h>\n #include <linux/of_net.h>\n"
  },
  {
    "path": "target/linux/generic/pending-5.15/800-bcma-get-SoC-device-struct-copy-its-DMA-params-to-th.patch",
    "content": "From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>\nSubject: [PATCH] bcma: get SoC device struct & copy its DMA params to the\n subdevices\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nFor bus devices to be fully usable it's required to set their DMA\nparameters.\n\nFor years it has been missing and remained unnoticed because of\nmips_dma_alloc_coherent() silently handling the empty coherent_dma_mask.\nKernel 4.19 came with a lot of DMA changes and caused a regression on\nthe bcm47xx. Starting with the commit f8c55dc6e828 (\"MIPS: use generic\ndma noncoherent ops for simple noncoherent platforms\") DMA coherent\nallocations just fail. Example:\n[    1.114914] bgmac_bcma bcma0:2: Allocation of TX ring 0x200 failed\n[    1.121215] bgmac_bcma bcma0:2: Unable to alloc memory for DMA\n[    1.127626] bgmac_bcma: probe of bcma0:2 failed with error -12\n[    1.133838] bgmac_bcma: Broadcom 47xx GBit MAC driver loaded\n\nThis change fixes above regression in addition to the MIPS bcm47xx\ncommit 321c46b91550 (\"MIPS: BCM47XX: Setup struct device for the SoC\").\n\nIt also fixes another *old* GPIO regression caused by a parent pointing\nto the NULL:\n[    0.157054] missing gpiochip .dev parent pointer\n[    0.157287] bcma: bus0: Error registering GPIO driver: -22\nintroduced by the commit 74f4e0cc6108 (\"bcma: switch GPIO portions to\nuse GPIOLIB_IRQCHIP\").\n\nFixes: f8c55dc6e828 (\"MIPS: use generic dma noncoherent ops for simple noncoherent platforms\")\nFixes: 74f4e0cc6108 (\"bcma: switch GPIO portions to use GPIOLIB_IRQCHIP\")\nCc: linux-mips@linux-mips.org\nCc: Christoph Hellwig <hch@lst.de>\nCc: Linus Walleij <linus.walleij@linaro.org>\nSigned-off-by: Rafał Miłecki <rafal@milecki.pl>\n---\n\n--- a/drivers/bcma/host_soc.c\n+++ b/drivers/bcma/host_soc.c\n@@ -191,6 +191,8 @@ int __init bcma_host_soc_init(struct bcm\n \tstruct bcma_bus *bus = &soc->bus;\n \tint err;\n \n+\tbus->dev = soc->dev;\n+\n \t/* Scan bus and initialize it */\n \terr = bcma_bus_early_register(bus);\n \tif (err)\n--- a/drivers/bcma/main.c\n+++ b/drivers/bcma/main.c\n@@ -236,13 +236,17 @@ EXPORT_SYMBOL(bcma_core_irq);\n \n void bcma_prepare_core(struct bcma_bus *bus, struct bcma_device *core)\n {\n-\tdevice_initialize(&core->dev);\n+\tstruct device *dev = &core->dev;\n+\n+\tdevice_initialize(dev);\n \tcore->dev.release = bcma_release_core_dev;\n \tcore->dev.bus = &bcma_bus_type;\n-\tdev_set_name(&core->dev, \"bcma%d:%d\", bus->num, core->core_index);\n+\tdev_set_name(dev, \"bcma%d:%d\", bus->num, core->core_index);\n \tcore->dev.parent = bus->dev;\n-\tif (bus->dev)\n+\tif (bus->dev) {\n \t\tbcma_of_fill_device(bus->dev, core);\n+\t\tdma_coerce_mask_and_coherent(dev, bus->dev->coherent_dma_mask);\n+\t}\n \n \tswitch (bus->hosttype) {\n \tcase BCMA_HOSTTYPE_PCI:\n"
  },
  {
    "path": "target/linux/generic/pending-5.15/801-gpio-gpio-cascade-add-generic-GPIO-cascade.patch",
    "content": "From fc23ea48ba52c24f201fe5ca0132ee1a3de5a70a Mon Sep 17 00:00:00 2001\nFrom: Mauri Sandberg <maukka@ext.kapsi.fi>\nDate: Thu, 25 Mar 2021 11:48:05 +0200\nSubject: [PATCH 2/2] gpio: gpio-cascade: add generic GPIO cascade\n\nAdds support for building cascades of GPIO lines. That is, it allows\nsetups when there is one upstream line and multiple cascaded lines, out\nof which one can be chosen at a time. The status of the upstream line\ncan be conveyed to the selected cascaded line or, vice versa, the status\nof the cascaded line can be conveyed to the upstream line.\n\nA multiplexer is being used to select, which cascaded GPIO line is being\nused at any given time.\n\nAt the moment only input direction is supported. In future it should be\npossible to add support for output direction, too.\n\nSigned-off-by: Mauri Sandberg <maukka@ext.kapsi.fi>\nReviewed-by: Linus Walleij <linus.walleij@linaro.org>\nReviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>\n---\nv7 -> v8:\n - rearrange members in struct gpio_cascade\n - cosmetic changes in file header and in one function declaration\n - added Reviewed-by tags by Linus and Andy\nv6 -> v7:\n - In Kconfig add info about module name\n - adhere to new convention that allows lines longer than 80 chars\n - use dev_probe_err with upstream gpio line too\n - refactor for cleaner exit of probe function.\nv5 -> v6:\n - In Kconfig, remove dependency to OF_GPIO and select only MULTIPLEXER\n - refactor code preferring one-liners\n - clean up prints, removing them from success-path.\n - don't explicitly set gpio_chip.of_node as it's done in the GPIO library\n - use devm_gpiochip_add_data instead of gpiochip_add\nv4 -> v5:\n - renamed gpio-mux-input -> gpio-cascade. refactored code accordingly\n   here and there and changed to use new bindings and compatible string\n   - ambigious and vague 'pin' was rename to 'upstream_line'\n - dropped Tested-by and Reviewed-by due to changes in bindings\n - dropped Reported-by suggested by an automatic bot as it was not really\n   appropriate to begin with\n - functionally it's the same as v4\nv3 -> v4:\n - Changed author email\n - Included Tested-by and Reviewed-by from Drew\nv2 -> v3:\n - use managed device resources\n - update Kconfig description\nv1 -> v2:\n - removed .owner from platform_driver as per test bot's instruction\n - added MODULE_AUTHOR, MODULE_DESCRIPTION, MODULE_LICENSE\n - added gpio_mux_input_get_direction as it's recommended for all chips\n - removed because this is input only chip: gpio_mux_input_set_value\n - removed because they are not needed for input/output only chips:\n     gpio_mux_input_direction_input\n     gpio_mux_input_direction_output\n - fixed typo in an error message\n - added info message about successful registration\n - removed can_sleep flag as this does not sleep while getting GPIO value\n   like I2C or SPI do\n - Updated description in Kconfig\n---\n drivers/gpio/Kconfig        |  15 +++++\n drivers/gpio/Makefile       |   1 +\n drivers/gpio/gpio-cascade.c | 117 ++++++++++++++++++++++++++++++++++++\n 3 files changed, 133 insertions(+)\n create mode 100644 drivers/gpio/gpio-cascade.c\n\n--- a/drivers/gpio/Kconfig\n+++ b/drivers/gpio/Kconfig\n@@ -1683,4 +1683,19 @@ config GPIO_VIRTIO\n \n endmenu\n \n+comment \"Other GPIO expanders\"\n+\n+config GPIO_CASCADE\n+\ttristate \"General GPIO cascade\"\n+\tselect MULTIPLEXER\n+\thelp\n+\t  Say yes here to enable support for generic GPIO cascade.\n+\n+\t  This allows building one-to-many cascades of GPIO lines using\n+\t  different types of multiplexers readily available. At the\n+\t  moment only input lines are supported.\n+\n+\t  To build the driver as a module choose 'm' and the resulting module\n+\t  will be called 'gpio-cascade'.\n+\n endif\n--- a/drivers/gpio/Makefile\n+++ b/drivers/gpio/Makefile\n@@ -45,6 +45,7 @@ obj-$(CONFIG_GPIO_BD9571MWV)\t\t+= gpio-bd\n obj-$(CONFIG_GPIO_BRCMSTB)\t\t+= gpio-brcmstb.o\n obj-$(CONFIG_GPIO_BT8XX)\t\t+= gpio-bt8xx.o\n obj-$(CONFIG_GPIO_CADENCE)\t\t+= gpio-cadence.o\n+obj-$(CONFIG_GPIO_CASCADE)\t\t+= gpio-cascade.o\n obj-$(CONFIG_GPIO_CLPS711X)\t\t+= gpio-clps711x.o\n obj-$(CONFIG_GPIO_SNPS_CREG)\t\t+= gpio-creg-snps.o\n obj-$(CONFIG_GPIO_CRYSTAL_COVE)\t\t+= gpio-crystalcove.o\n--- /dev/null\n+++ b/drivers/gpio/gpio-cascade.c\n@@ -0,0 +1,117 @@\n+// SPDX-License-Identifier: GPL-2.0-only\n+/*\n+ *  A generic GPIO cascade driver\n+ *\n+ *  Copyright (C) 2021 Mauri Sandberg <maukka@ext.kapsi.fi>\n+ *\n+ * This allows building cascades of GPIO lines in a manner illustrated\n+ * below:\n+ *\n+ *                 /|---- Cascaded GPIO line 0\n+ *  Upstream      | |---- Cascaded GPIO line 1\n+ *  GPIO line ----+ | .\n+ *                | | .\n+ *                 \\|---- Cascaded GPIO line n\n+ *\n+ * A multiplexer is being used to select, which cascaded line is being\n+ * addressed at any given time.\n+ *\n+ * At the moment only input mode is supported due to lack of means for\n+ * testing output functionality. At least theoretically output should be\n+ * possible with open drain constructions.\n+ */\n+\n+#include <linux/module.h>\n+#include <linux/slab.h>\n+#include <linux/platform_device.h>\n+#include <linux/mux/consumer.h>\n+\n+#include <linux/gpio/consumer.h>\n+#include <linux/gpio/driver.h>\n+\n+struct gpio_cascade {\n+\tstruct gpio_chip\tgpio_chip;\n+\tstruct device\t\t*parent;\n+\tstruct mux_control\t*mux_control;\n+\tstruct gpio_desc\t*upstream_line;\n+};\n+\n+static struct gpio_cascade *chip_to_cascade(struct gpio_chip *gc)\n+{\n+\treturn container_of(gc, struct gpio_cascade, gpio_chip);\n+}\n+\n+static int gpio_cascade_get_direction(struct gpio_chip *gc, unsigned int offset)\n+{\n+\treturn GPIO_LINE_DIRECTION_IN;\n+}\n+\n+static int gpio_cascade_get_value(struct gpio_chip *gc, unsigned int offset)\n+{\n+\tstruct gpio_cascade *cas = chip_to_cascade(gc);\n+\tint ret;\n+\n+\tret = mux_control_select(cas->mux_control, offset);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = gpiod_get_value(cas->upstream_line);\n+\tmux_control_deselect(cas->mux_control);\n+\treturn ret;\n+}\n+\n+static int gpio_cascade_probe(struct platform_device *pdev)\n+{\n+\tstruct device *dev = &pdev->dev;\n+\tstruct gpio_cascade *cas;\n+\tstruct mux_control *mc;\n+\tstruct gpio_desc *upstream;\n+\tstruct gpio_chip *gc;\n+\n+\tcas = devm_kzalloc(dev, sizeof(*cas), GFP_KERNEL);\n+\tif (!cas)\n+\t\treturn -ENOMEM;\n+\n+\tmc = devm_mux_control_get(dev, NULL);\n+\tif (IS_ERR(mc))\n+\t\treturn dev_err_probe(dev, PTR_ERR(mc), \"unable to get mux-control\\n\");\n+\n+\tcas->mux_control = mc;\n+\tupstream = devm_gpiod_get(dev, \"upstream\",  GPIOD_IN);\n+\tif (IS_ERR(upstream))\n+\t\treturn dev_err_probe(dev, PTR_ERR(upstream), \"unable to claim upstream GPIO line\\n\");\n+\n+\tcas->upstream_line = upstream;\n+\tcas->parent = dev;\n+\n+\tgc = &cas->gpio_chip;\n+\tgc->get = gpio_cascade_get_value;\n+\tgc->get_direction = gpio_cascade_get_direction;\n+\tgc->base = -1;\n+\tgc->ngpio = mux_control_states(mc);\n+\tgc->label = dev_name(cas->parent);\n+\tgc->parent = cas->parent;\n+\tgc->owner = THIS_MODULE;\n+\n+\tplatform_set_drvdata(pdev, cas);\n+\treturn devm_gpiochip_add_data(dev, &cas->gpio_chip, NULL);\n+}\n+\n+static const struct of_device_id gpio_cascade_id[] = {\n+\t{ .compatible = \"gpio-cascade\" },\n+\t{ /* sentinel */ }\n+};\n+MODULE_DEVICE_TABLE(of, gpio_cascade_id);\n+\n+static struct platform_driver gpio_cascade_driver = {\n+\t.driver\t= {\n+\t\t.name\t\t= \"gpio-cascade\",\n+\t\t.of_match_table = gpio_cascade_id,\n+\t},\n+\t.probe\t= gpio_cascade_probe,\n+};\n+module_platform_driver(gpio_cascade_driver);\n+\n+MODULE_AUTHOR(\"Mauri Sandberg <maukka@ext.kapsi.fi>\");\n+MODULE_DESCRIPTION(\"Generic GPIO cascade\");\n+MODULE_LICENSE(\"GPL\");\n"
  },
  {
    "path": "target/linux/generic/pending-5.15/810-pci_disable_common_quirks.patch",
    "content": "From: Gabor Juhos <juhosg@openwrt.org>\nSubject: debloat: add kernel config option to disabling common PCI quirks\n\nSigned-off-by: Gabor Juhos <juhosg@openwrt.org>\n---\n drivers/pci/Kconfig  | 6 ++++++\n drivers/pci/quirks.c | 6 ++++++\n 2 files changed, 12 insertions(+)\n\n--- a/drivers/pci/Kconfig\n+++ b/drivers/pci/Kconfig\n@@ -118,6 +118,13 @@ config XEN_PCIDEV_FRONTEND\n \t  The PCI device frontend driver allows the kernel to import arbitrary\n \t  PCI devices from a PCI backend to support PCI driver domains.\n \n+config PCI_DISABLE_COMMON_QUIRKS\n+\tbool \"PCI disable common quirks\"\n+\tdepends on PCI\n+\thelp\n+\t  If you don't know what to do here, say N.\n+\n+\n config PCI_ATS\n \tbool\n \n--- a/drivers/pci/quirks.c\n+++ b/drivers/pci/quirks.c\n@@ -206,6 +206,7 @@ static void quirk_mmio_always_on(struct\n DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID, PCI_ANY_ID,\n \t\t\t\tPCI_CLASS_BRIDGE_HOST, 8, quirk_mmio_always_on);\n \n+#ifndef CONFIG_PCI_DISABLE_COMMON_QUIRKS\n /*\n  * The Mellanox Tavor device gives false positive parity errors.  Disable\n  * parity error reporting.\n@@ -3363,6 +3364,8 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_I\n DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata);\n DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata);\n \n+#endif /* !CONFIG_PCI_DISABLE_COMMON_QUIRKS */\n+\n /*\n  * Ivytown NTB BAR sizes are misreported by the hardware due to an erratum.\n  * To work around this, query the size it should be configured to by the\n@@ -3388,6 +3391,8 @@ static void quirk_intel_ntb(struct pci_d\n DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e08, quirk_intel_ntb);\n DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e0d, quirk_intel_ntb);\n \n+#ifndef CONFIG_PCI_DISABLE_COMMON_QUIRKS\n+\n /*\n  * Some BIOS implementations leave the Intel GPU interrupts enabled, even\n  * though no one is handling them (e.g., if the i915 driver is never\n@@ -3426,6 +3431,8 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_IN\n DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq);\n DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0152, disable_igfx_irq);\n \n+#endif /* !CONFIG_PCI_DISABLE_COMMON_QUIRKS */\n+\n /*\n  * PCI devices which are on Intel chips can skip the 10ms delay\n  * before entering D3 mode.\n"
  },
  {
    "path": "target/linux/generic/pending-5.15/811-pci_disable_usb_common_quirks.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nSubject: debloat: disable common USB quirks\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n drivers/usb/host/pci-quirks.c | 16 ++++++++++++++++\n drivers/usb/host/pci-quirks.h | 18 +++++++++++++++++-\n include/linux/usb/hcd.h       |  7 +++++++\n 3 files changed, 40 insertions(+), 1 deletion(-)\n\n--- a/drivers/usb/host/pci-quirks.c\n+++ b/drivers/usb/host/pci-quirks.c\n@@ -128,6 +128,8 @@ struct amd_chipset_type {\n \tu8 rev;\n };\n \n+#ifndef CONFIG_PCI_DISABLE_COMMON_QUIRKS\n+\n static struct amd_chipset_info {\n \tstruct pci_dev\t*nb_dev;\n \tstruct pci_dev\t*smbus_dev;\n@@ -633,6 +635,10 @@ bool usb_amd_pt_check_port(struct device\n }\n EXPORT_SYMBOL_GPL(usb_amd_pt_check_port);\n \n+#endif /* CONFIG_PCI_DISABLE_COMMON_QUIRKS */\n+\n+#if IS_ENABLED(CONFIG_USB_UHCI_HCD)\n+\n /*\n  * Make sure the controller is completely inactive, unable to\n  * generate interrupts or do DMA.\n@@ -712,8 +718,17 @@ reset_needed:\n \tuhci_reset_hc(pdev, base);\n \treturn 1;\n }\n+#else\n+int uhci_check_and_reset_hc(struct pci_dev *pdev, unsigned long base)\n+{\n+\treturn 0;\n+}\n+\n+#endif\n EXPORT_SYMBOL_GPL(uhci_check_and_reset_hc);\n \n+#ifndef CONFIG_PCI_DISABLE_COMMON_QUIRKS\n+\n static inline int io_type_enabled(struct pci_dev *pdev, unsigned int mask)\n {\n \tu16 cmd;\n@@ -1285,3 +1300,4 @@ static void quirk_usb_early_handoff(stru\n }\n DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID,\n \t\t\tPCI_CLASS_SERIAL_USB, 8, quirk_usb_early_handoff);\n+#endif\n--- a/drivers/usb/host/pci-quirks.h\n+++ b/drivers/usb/host/pci-quirks.h\n@@ -5,6 +5,9 @@\n #ifdef CONFIG_USB_PCI\n void uhci_reset_hc(struct pci_dev *pdev, unsigned long base);\n int uhci_check_and_reset_hc(struct pci_dev *pdev, unsigned long base);\n+#endif  /* CONFIG_USB_PCI */\n+\n+#if defined(CONFIG_USB_PCI) && !defined(CONFIG_PCI_DISABLE_COMMON_QUIRKS)\n int usb_hcd_amd_remote_wakeup_quirk(struct pci_dev *pdev);\n bool usb_amd_hang_symptom_quirk(void);\n bool usb_amd_prefetch_quirk(void);\n@@ -19,6 +22,18 @@ void sb800_prefetch(struct device *dev,\n bool usb_amd_pt_check_port(struct device *device, int port);\n #else\n struct pci_dev;\n+static inline int usb_amd_quirk_pll_check(void)\n+{\n+\treturn 0;\n+}\n+static inline bool usb_amd_hang_symptom_quirk(void)\n+{\n+\treturn false;\n+}\n+static inline bool usb_amd_prefetch_quirk(void)\n+{\n+\treturn false;\n+}\n static inline void usb_amd_quirk_pll_disable(void) {}\n static inline void usb_amd_quirk_pll_enable(void) {}\n static inline void usb_asmedia_modifyflowcontrol(struct pci_dev *pdev) {}\n@@ -29,6 +44,11 @@ static inline bool usb_amd_pt_check_port\n {\n \treturn false;\n }\n+static inline void usb_enable_intel_xhci_ports(struct pci_dev *xhci_pdev) {}\n+static inline bool usb_xhci_needs_pci_reset(struct pci_dev *pdev)\n+{\n+\treturn false;\n+}\n #endif  /* CONFIG_USB_PCI */\n \n #endif  /*  __LINUX_USB_PCI_QUIRKS_H  */\n--- a/include/linux/usb/hcd.h\n+++ b/include/linux/usb/hcd.h\n@@ -495,7 +495,14 @@ extern int usb_hcd_pci_probe(struct pci_\n extern void usb_hcd_pci_remove(struct pci_dev *dev);\n extern void usb_hcd_pci_shutdown(struct pci_dev *dev);\n \n+#ifndef CONFIG_PCI_DISABLE_COMMON_QUIRKS\n extern int usb_hcd_amd_remote_wakeup_quirk(struct pci_dev *dev);\n+#else\n+static inline int usb_hcd_amd_remote_wakeup_quirk(struct pci_dev *dev)\n+{\n+\treturn 0;\n+}\n+#endif\n \n #ifdef CONFIG_PM\n extern const struct dev_pm_ops usb_hcd_pci_pm_ops;\n"
  },
  {
    "path": "target/linux/generic/pending-5.15/820-w1-gpio-fix-problem-with-platfom-data-in-w1-gpio.patch",
    "content": "From d9c8bc8c1408f3e8529db6e4e04017b4c579c342 Mon Sep 17 00:00:00 2001\nFrom: Pawel Dembicki <paweldembicki@gmail.com>\nDate: Sun, 18 Feb 2018 17:08:04 +0100\nSubject: [PATCH] w1: gpio: fix problem with platfom data in w1-gpio\n\nIn devices, where fdt is used, is impossible to apply platform data\nwithout proper fdt node.\n\nThis patch allow to use platform data in devices with fdt.\n\nSigned-off-by: Pawel Dembicki <paweldembicki@gmail.com>\n---\n drivers/w1/masters/w1-gpio.c | 7 +++----\n 1 file changed, 3 insertions(+), 4 deletions(-)\n\n--- a/drivers/w1/masters/w1-gpio.c\n+++ b/drivers/w1/masters/w1-gpio.c\n@@ -76,7 +76,7 @@ static int w1_gpio_probe(struct platform\n \tenum gpiod_flags gflags = GPIOD_OUT_LOW_OPEN_DRAIN;\n \tint err;\n \n-\tif (of_have_populated_dt()) {\n+\tif (of_have_populated_dt() && !dev_get_platdata(&pdev->dev)) {\n \t\tpdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);\n \t\tif (!pdata)\n \t\t\treturn -ENOMEM;\n"
  },
  {
    "path": "target/linux/generic/pending-5.15/834-ledtrig-libata.patch",
    "content": "From: Daniel Golle <daniel@makrotopia.org>\nSubject: libata: add ledtrig support\n\nThis adds a LED trigger for each ATA port indicating disk activity.\n\nAs this is needed only on specific platforms (NAS SoCs and such),\nthese platforms should define ARCH_WANTS_LIBATA_LEDS if there\nare boards with LED(s) intended to indicate ATA disk activity and\nneed the OS to take care of that.\nIn that way, if not selected, LED trigger support not will be\nincluded in libata-core and both, codepaths and structures remain\nuntouched.\n\nSigned-off-by: Daniel Golle <daniel@makrotopia.org>\n---\n drivers/ata/Kconfig       | 16 ++++++++++++++++\n drivers/ata/libata-core.c | 41 +++++++++++++++++++++++++++++++++++++++++\n include/linux/libata.h    |  9 +++++++++\n 3 files changed, 66 insertions(+)\n\n--- a/drivers/ata/Kconfig\n+++ b/drivers/ata/Kconfig\n@@ -67,6 +67,22 @@ config ATA_FORCE\n \n \t  If unsure, say Y.\n \n+config ARCH_WANT_LIBATA_LEDS\n+\tbool\n+\n+config ATA_LEDS\n+\tbool \"support ATA port LED triggers\"\n+\tdepends on ARCH_WANT_LIBATA_LEDS\n+\tselect NEW_LEDS\n+\tselect LEDS_CLASS\n+\tselect LEDS_TRIGGERS\n+\tdefault y\n+\thelp\n+\t  This option adds a LED trigger for each registered ATA port.\n+\t  It is used to drive disk activity leds connected via GPIO.\n+\n+\t  If unsure, say N.\n+\n config ATA_ACPI\n \tbool \"ATA ACPI Support\"\n \tdepends on ACPI\n--- a/drivers/ata/libata-core.c\n+++ b/drivers/ata/libata-core.c\n@@ -656,6 +656,19 @@ u64 ata_tf_read_block(const struct ata_t\n \treturn block;\n }\n \n+#ifdef CONFIG_ATA_LEDS\n+#define LIBATA_BLINK_DELAY 20 /* ms */\n+static inline void ata_led_act(struct ata_port *ap)\n+{\n+\tunsigned long led_delay = LIBATA_BLINK_DELAY;\n+\n+\tif (unlikely(!ap->ledtrig))\n+\t\treturn;\n+\n+\tled_trigger_blink_oneshot(ap->ledtrig, &led_delay, &led_delay, 0);\n+}\n+#endif\n+\n /**\n  *\tata_build_rw_tf - Build ATA taskfile for given read/write request\n  *\t@tf: Target ATA taskfile\n@@ -4576,6 +4589,9 @@ struct ata_queued_cmd *ata_qc_new_init(s\n \t\tif (tag < 0)\n \t\t\treturn NULL;\n \t}\n+#ifdef CONFIG_ATA_LEDS\n+\tata_led_act(ap);\n+#endif\n \n \tqc = __ata_qc_from_tag(ap, tag);\n \tqc->tag = qc->hw_tag = tag;\n@@ -5354,6 +5370,9 @@ struct ata_port *ata_port_alloc(struct a\n \tap->stats.unhandled_irq = 1;\n \tap->stats.idle_irq = 1;\n #endif\n+#ifdef CONFIG_ATA_LEDS\n+\tap->ledtrig = kzalloc(sizeof(struct led_trigger), GFP_KERNEL);\n+#endif\n \tata_sff_port_init(ap);\n \n \treturn ap;\n@@ -5389,6 +5408,12 @@ static void ata_host_release(struct kref\n \n \t\tkfree(ap->pmp_link);\n \t\tkfree(ap->slave_link);\n+#ifdef CONFIG_ATA_LEDS\n+\t\tif (ap->ledtrig) {\n+\t\t\tled_trigger_unregister(ap->ledtrig);\n+\t\t\tkfree(ap->ledtrig);\n+\t\t};\n+#endif\n \t\tkfree(ap);\n \t\thost->ports[i] = NULL;\n \t}\n@@ -5795,7 +5820,23 @@ int ata_host_register(struct ata_host *h\n \t\thost->ports[i]->print_id = atomic_inc_return(&ata_print_id);\n \t\thost->ports[i]->local_port_no = i + 1;\n \t}\n+#ifdef CONFIG_ATA_LEDS\n+\tfor (i = 0; i < host->n_ports; i++) {\n+\t\tif (unlikely(!host->ports[i]->ledtrig))\n+\t\t\tcontinue;\n \n+\t\tsnprintf(host->ports[i]->ledtrig_name,\n+\t\t\tsizeof(host->ports[i]->ledtrig_name), \"ata%u\",\n+\t\t\thost->ports[i]->print_id);\n+\n+\t\thost->ports[i]->ledtrig->name = host->ports[i]->ledtrig_name;\n+\n+\t\tif (led_trigger_register(host->ports[i]->ledtrig)) {\n+\t\t\tkfree(host->ports[i]->ledtrig);\n+\t\t\thost->ports[i]->ledtrig = NULL;\n+\t\t}\n+\t}\n+#endif\n \t/* Create associated sysfs transport objects  */\n \tfor (i = 0; i < host->n_ports; i++) {\n \t\trc = ata_tport_add(host->dev,host->ports[i]);\n--- a/include/linux/libata.h\n+++ b/include/linux/libata.h\n@@ -23,6 +23,9 @@\n #include <linux/cdrom.h>\n #include <linux/sched.h>\n #include <linux/async.h>\n+#ifdef CONFIG_ATA_LEDS\n+#include <linux/leds.h>\n+#endif\n \n /*\n  * Define if arch has non-standard setup.  This is a _PCI_ standard\n@@ -888,6 +891,12 @@ struct ata_port {\n #ifdef CONFIG_ATA_ACPI\n \tstruct ata_acpi_gtm\t__acpi_init_gtm; /* use ata_acpi_init_gtm() */\n #endif\n+\n+#ifdef CONFIG_ATA_LEDS\n+\tstruct led_trigger\t*ledtrig;\n+\tchar\t\t\tledtrig_name[8];\n+#endif\n+\n \t/* owned by EH */\n \tu8\t\t\tsector_buf[ATA_SECT_SIZE] ____cacheline_aligned;\n };\n"
  },
  {
    "path": "target/linux/generic/pending-5.15/840-hwrng-bcm2835-set-quality-to-1000.patch",
    "content": "From d6988cf1d16faac56899918bb2b1be8d85155e3f Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com>\nDate: Sat, 20 Feb 2021 18:36:38 +0100\nSubject: [PATCH] hwrng: bcm2835: set quality to 1000\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nThis allows devices without a high precission timer to reduce boot from >100s\nto <30s.\n\nSigned-off-by: Álvaro Fernández Rojas <noltari@gmail.com>\n---\n drivers/char/hw_random/bcm2835-rng.c | 1 +\n 1 file changed, 1 insertion(+)\n\n--- a/drivers/char/hw_random/bcm2835-rng.c\n+++ b/drivers/char/hw_random/bcm2835-rng.c\n@@ -170,6 +170,7 @@ static int bcm2835_rng_probe(struct plat\n \tpriv->rng.init = bcm2835_rng_init;\n \tpriv->rng.read = bcm2835_rng_read;\n \tpriv->rng.cleanup = bcm2835_rng_cleanup;\n+\tpriv->rng.quality = 1000;\n \n \tif (dev_of_node(dev)) {\n \t\trng_id = of_match_node(bcm2835_rng_of_match, dev->of_node);\n"
  },
  {
    "path": "target/linux/generic/pending-5.15/842-net-qmi_wwan-add-ZTE-MF286D-modem-19d2-1485.patch",
    "content": "From 078c6a1cbd4cd7496048786beec2e312577bebbf Mon Sep 17 00:00:00 2001\nFrom: Pawel Dembicki <paweldembicki@gmail.com>\nDate: Tue, 11 Jan 2022 23:11:32 +0100\nSubject: [PATCH] net: qmi_wwan: add ZTE MF286D modem 19d2:1485\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nModem from ZTE MF286D is an Qualcomm MDM9250 based 3G/4G modem.\n\nT:  Bus=02 Lev=01 Prnt=01 Port=00 Cnt=01 Dev#=  3 Spd=5000 MxCh= 0\nD:  Ver= 3.00 Cls=00(>ifc ) Sub=00 Prot=00 MxPS= 9 #Cfgs=  1\nP:  Vendor=19d2 ProdID=1485 Rev=52.87\nS:  Manufacturer=ZTE,Incorporated\nS:  Product=ZTE Technologies MSM\nS:  SerialNumber=MF286DZTED000000\nC:* #Ifs= 7 Cfg#= 1 Atr=80 MxPwr=896mA\nA:  FirstIf#= 0 IfCount= 2 Cls=02(comm.) Sub=06 Prot=00\nI:* If#= 0 Alt= 0 #EPs= 1 Cls=02(comm.) Sub=02 Prot=ff Driver=rndis_host\nE:  Ad=82(I) Atr=03(Int.) MxPS=   8 Ivl=32ms\nI:* If#= 1 Alt= 0 #EPs= 2 Cls=0a(data ) Sub=00 Prot=00 Driver=rndis_host\nE:  Ad=81(I) Atr=02(Bulk) MxPS=1024 Ivl=0ms\nE:  Ad=01(O) Atr=02(Bulk) MxPS=1024 Ivl=0ms\nI:* If#= 2 Alt= 0 #EPs= 2 Cls=ff(vend.) Sub=ff Prot=ff Driver=option\nE:  Ad=83(I) Atr=02(Bulk) MxPS=1024 Ivl=0ms\nE:  Ad=02(O) Atr=02(Bulk) MxPS=1024 Ivl=0ms\nI:* If#= 3 Alt= 0 #EPs= 3 Cls=ff(vend.) Sub=ff Prot=ff Driver=option\nE:  Ad=85(I) Atr=03(Int.) MxPS=  10 Ivl=32ms\nE:  Ad=84(I) Atr=02(Bulk) MxPS=1024 Ivl=0ms\nE:  Ad=03(O) Atr=02(Bulk) MxPS=1024 Ivl=0ms\nI:* If#= 4 Alt= 0 #EPs= 3 Cls=ff(vend.) Sub=ff Prot=ff Driver=option\nE:  Ad=87(I) Atr=03(Int.) MxPS=  10 Ivl=32ms\nE:  Ad=86(I) Atr=02(Bulk) MxPS=1024 Ivl=0ms\nE:  Ad=04(O) Atr=02(Bulk) MxPS=1024 Ivl=0ms\nI:* If#= 5 Alt= 0 #EPs= 3 Cls=ff(vend.) Sub=ff Prot=ff Driver=qmi_wwan\nE:  Ad=88(I) Atr=03(Int.) MxPS=   8 Ivl=32ms\nE:  Ad=8e(I) Atr=02(Bulk) MxPS=1024 Ivl=0ms\nE:  Ad=0f(O) Atr=02(Bulk) MxPS=1024 Ivl=0ms\nI:* If#= 6 Alt= 0 #EPs= 2 Cls=ff(vend.) Sub=42 Prot=01 Driver=usbfs\nE:  Ad=05(O) Atr=02(Bulk) MxPS=1024 Ivl=0ms\nE:  Ad=89(I) Atr=02(Bulk) MxPS=1024 Ivl=0ms\n\nSigned-off-by: Pawel Dembicki <paweldembicki@gmail.com>\nAcked-by: Bjørn Mork <bjorn@mork.no>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/usb/qmi_wwan.c | 1 +\n 1 file changed, 1 insertion(+)\n\n--- a/drivers/net/usb/qmi_wwan.c\n+++ b/drivers/net/usb/qmi_wwan.c\n@@ -1313,6 +1313,7 @@ static const struct usb_device_id produc\n \t{QMI_FIXED_INTF(0x19d2, 0x1426, 2)},\t/* ZTE MF91 */\n \t{QMI_FIXED_INTF(0x19d2, 0x1428, 2)},\t/* Telewell TW-LTE 4G v2 */\n \t{QMI_FIXED_INTF(0x19d2, 0x1432, 3)},\t/* ZTE ME3620 */\n+\t{QMI_FIXED_INTF(0x19d2, 0x1485, 5)},\t/* ZTE MF286D */\n \t{QMI_FIXED_INTF(0x19d2, 0x2002, 4)},\t/* ZTE (Vodafone) K3765-Z */\n \t{QMI_FIXED_INTF(0x2001, 0x7e16, 3)},\t/* D-Link DWM-221 */\n \t{QMI_FIXED_INTF(0x2001, 0x7e19, 4)},\t/* D-Link DWM-221 B1 */\n"
  },
  {
    "path": "target/linux/generic/pending-5.15/850-0001-PCI-aardvark-Replace-custom-PCIE_CORE_INT_-macros-wi.patch",
    "content": "From 43f3f187e6f62ca40802afe39495c8a3e20b4bfa Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>\nDate: Mon, 10 Jan 2022 01:50:50 +0100\nSubject: [PATCH] PCI: aardvark: Replace custom PCIE_CORE_INT_* macros with\n PCI_INTERRUPT_*\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nHeader file linux/pci.h defines enum pci_interrupt_pin with corresponding\nPCI_INTERRUPT_* values.\n\nSigned-off-by: Pali Rohár <pali@kernel.org>\nSigned-off-by: Marek Behún <kabel@kernel.org>\n---\n drivers/pci/controller/pci-aardvark.c | 6 +-----\n 1 file changed, 1 insertion(+), 5 deletions(-)\n\n--- a/drivers/pci/controller/pci-aardvark.c\n+++ b/drivers/pci/controller/pci-aardvark.c\n@@ -38,10 +38,6 @@\n #define     PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN\t\t\tBIT(6)\n #define     PCIE_CORE_ERR_CAPCTL_ECRC_CHCK\t\t\tBIT(7)\n #define     PCIE_CORE_ERR_CAPCTL_ECRC_CHCK_RCV\t\t\tBIT(8)\n-#define     PCIE_CORE_INT_A_ASSERT_ENABLE\t\t\t1\n-#define     PCIE_CORE_INT_B_ASSERT_ENABLE\t\t\t2\n-#define     PCIE_CORE_INT_C_ASSERT_ENABLE\t\t\t3\n-#define     PCIE_CORE_INT_D_ASSERT_ENABLE\t\t\t4\n /* PIO registers base address and register offsets */\n #define PIO_BASE_ADDR\t\t\t\t0x4000\n #define PIO_CTRL\t\t\t\t(PIO_BASE_ADDR + 0x0)\n@@ -961,7 +957,7 @@ static int advk_sw_pci_bridge_init(struc\n \tbridge->conf.pref_mem_limit = cpu_to_le16(PCI_PREF_RANGE_TYPE_64);\n \n \t/* Support interrupt A for MSI feature */\n-\tbridge->conf.intpin = PCIE_CORE_INT_A_ASSERT_ENABLE;\n+\tbridge->conf.intpin = PCI_INTERRUPT_INTA;\n \n \t/* Aardvark HW provides PCIe Capability structure in version 2 */\n \tbridge->pcie_conf.cap = cpu_to_le16(2);\n"
  },
  {
    "path": "target/linux/generic/pending-5.15/850-0004-PCI-aardvark-Rewrite-IRQ-code-to-chained-IRQ-handler.patch",
    "content": "From 0cd5141d1866afb23286fe90cd846441fe7aeb39 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>\nDate: Sat, 27 Mar 2021 14:44:11 +0100\nSubject: [PATCH] PCI: aardvark: Rewrite IRQ code to chained IRQ handler\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nRewrite the code to use irq_set_chained_handler_and_data() handler with\nchained_irq_enter() and chained_irq_exit() processing instead of using\ndevm_request_irq().\n\nadvk_pcie_irq_handler() reads IRQ status bits and calls other functions\nbased on which bits are set. These functions then read its own IRQ status\nbits and calls other aardvark functions based on these bits. Finally\ngeneric_handle_domain_irq() with translated linux IRQ numbers are called.\n\nSigned-off-by: Pali Rohár <pali@kernel.org>\nSigned-off-by: Marek Behún <kabel@kernel.org>\n---\n drivers/pci/controller/pci-aardvark.c | 48 +++++++++++++++------------\n 1 file changed, 26 insertions(+), 22 deletions(-)\n\n--- a/drivers/pci/controller/pci-aardvark.c\n+++ b/drivers/pci/controller/pci-aardvark.c\n@@ -268,6 +268,7 @@ struct advk_pcie {\n \t\tu32 actions;\n \t} wins[OB_WIN_COUNT];\n \tu8 wins_count;\n+\tint irq;\n \tstruct irq_domain *irq_domain;\n \tstruct irq_chip irq_chip;\n \traw_spinlock_t irq_lock;\n@@ -1432,21 +1433,26 @@ static void advk_pcie_handle_int(struct\n \t}\n }\n \n-static irqreturn_t advk_pcie_irq_handler(int irq, void *arg)\n+static void advk_pcie_irq_handler(struct irq_desc *desc)\n {\n-\tstruct advk_pcie *pcie = arg;\n-\tu32 status;\n+\tstruct advk_pcie *pcie = irq_desc_get_handler_data(desc);\n+\tstruct irq_chip *chip = irq_desc_get_chip(desc);\n+\tu32 val, mask, status;\n \n-\tstatus = advk_readl(pcie, HOST_CTRL_INT_STATUS_REG);\n-\tif (!(status & PCIE_IRQ_CORE_INT))\n-\t\treturn IRQ_NONE;\n+\tchained_irq_enter(chip, desc);\n \n-\tadvk_pcie_handle_int(pcie);\n+\tval = advk_readl(pcie, HOST_CTRL_INT_STATUS_REG);\n+\tmask = advk_readl(pcie, HOST_CTRL_INT_MASK_REG);\n+\tstatus = val & ((~mask) & PCIE_IRQ_ALL_MASK);\n \n-\t/* Clear interrupt */\n-\tadvk_writel(pcie, PCIE_IRQ_CORE_INT, HOST_CTRL_INT_STATUS_REG);\n+\tif (status & PCIE_IRQ_CORE_INT) {\n+\t\tadvk_pcie_handle_int(pcie);\n \n-\treturn IRQ_HANDLED;\n+\t\t/* Clear interrupt */\n+\t\tadvk_writel(pcie, PCIE_IRQ_CORE_INT, HOST_CTRL_INT_STATUS_REG);\n+\t}\n+\n+\tchained_irq_exit(chip, desc);\n }\n \n static void __maybe_unused advk_pcie_disable_phy(struct advk_pcie *pcie)\n@@ -1513,7 +1519,7 @@ static int advk_pcie_probe(struct platfo\n \tstruct advk_pcie *pcie;\n \tstruct pci_host_bridge *bridge;\n \tstruct resource_entry *entry;\n-\tint ret, irq;\n+\tint ret;\n \n \tbridge = devm_pci_alloc_host_bridge(dev, sizeof(struct advk_pcie));\n \tif (!bridge)\n@@ -1599,17 +1605,9 @@ static int advk_pcie_probe(struct platfo\n \tif (IS_ERR(pcie->base))\n \t\treturn PTR_ERR(pcie->base);\n \n-\tirq = platform_get_irq(pdev, 0);\n-\tif (irq < 0)\n-\t\treturn irq;\n-\n-\tret = devm_request_irq(dev, irq, advk_pcie_irq_handler,\n-\t\t\t       IRQF_SHARED | IRQF_NO_THREAD, \"advk-pcie\",\n-\t\t\t       pcie);\n-\tif (ret) {\n-\t\tdev_err(dev, \"Failed to register interrupt\\n\");\n-\t\treturn ret;\n-\t}\n+\tpcie->irq = platform_get_irq(pdev, 0);\n+\tif (pcie->irq < 0)\n+\t\treturn pcie->irq;\n \n \tpcie->reset_gpio = devm_gpiod_get_from_of_node(dev, dev->of_node,\n \t\t\t\t\t\t       \"reset-gpios\", 0,\n@@ -1658,11 +1656,14 @@ static int advk_pcie_probe(struct platfo\n \t\treturn ret;\n \t}\n \n+\tirq_set_chained_handler_and_data(pcie->irq, advk_pcie_irq_handler, pcie);\n+\n \tbridge->sysdata = pcie;\n \tbridge->ops = &advk_pcie_ops;\n \n \tret = pci_host_probe(bridge);\n \tif (ret < 0) {\n+\t\tirq_set_chained_handler_and_data(pcie->irq, NULL, NULL);\n \t\tadvk_pcie_remove_msi_irq_domain(pcie);\n \t\tadvk_pcie_remove_irq_domain(pcie);\n \t\treturn ret;\n@@ -1710,6 +1711,9 @@ static int advk_pcie_remove(struct platf\n \tadvk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_REG);\n \tadvk_writel(pcie, PCIE_IRQ_ALL_MASK, HOST_CTRL_INT_STATUS_REG);\n \n+\t/* Remove IRQ handler */\n+\tirq_set_chained_handler_and_data(pcie->irq, NULL, NULL);\n+\n \t/* Remove IRQ domains */\n \tadvk_pcie_remove_msi_irq_domain(pcie);\n \tadvk_pcie_remove_irq_domain(pcie);\n"
  },
  {
    "path": "target/linux/generic/pending-5.15/850-0005-PCI-aardvark-Check-return-value-of-generic_handle_do.patch",
    "content": "From 69c1f2c6f45a556361fd8e8d2d4eb20e2c8d3d95 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>\nDate: Thu, 18 Mar 2021 17:04:32 +0100\nSubject: [PATCH] PCI: aardvark: Check return value of\n generic_handle_domain_irq() when processing INTx IRQ\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nIt is possible that we receive spurious INTx interrupt. Check for the\nreturn value of generic_handle_domain_irq() when processing INTx IRQ.\n\nSigned-off-by: Pali Rohár <pali@kernel.org>\nSigned-off-by: Marek Behún <kabel@kernel.org>\n---\n drivers/pci/controller/pci-aardvark.c | 4 +++-\n 1 file changed, 3 insertions(+), 1 deletion(-)\n\n--- a/drivers/pci/controller/pci-aardvark.c\n+++ b/drivers/pci/controller/pci-aardvark.c\n@@ -1429,7 +1429,9 @@ static void advk_pcie_handle_int(struct\n \t\tadvk_writel(pcie, PCIE_ISR1_INTX_ASSERT(i),\n \t\t\t    PCIE_ISR1_REG);\n \n-\t\tgeneric_handle_domain_irq(pcie->irq_domain, i);\n+\t\tif (generic_handle_domain_irq(pcie->irq_domain, i) == -EINVAL)\n+\t\t\tdev_err_ratelimited(&pcie->pdev->dev, \"unexpected INT%c IRQ\\n\",\n+\t\t\t\t\t    (char)i + 'A');\n \t}\n }\n \n"
  },
  {
    "path": "target/linux/generic/pending-5.15/850-0006-PCI-aardvark-Make-MSI-irq_chip-structures-static-dri.patch",
    "content": "From 5eb36a6b9508da442aac80f4df23e3951bbfa7aa Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Marek=20Beh=C3=BAn?= <kabel@kernel.org>\nDate: Mon, 10 Jan 2022 00:03:41 +0100\nSubject: [PATCH] PCI: aardvark: Make MSI irq_chip structures static driver\n structures\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nMarc Zyngier says [1] that we should use struct irq_chip as a global\nstatic struct in the driver. Even though the structure currently\ncontains a dynamic member (parent_device), Marc says [2] that he plans\nto kill it and make the structure completely static.\n\nConvert Aardvark's priv->msi_bottom_irq_chip and priv->msi_irq_chip to\nstatic driver structure.\n\n[1] https://lore.kernel.org/linux-pci/877dbcvngf.wl-maz@kernel.org/\n[2] https://lore.kernel.org/linux-pci/874k6gvkhz.wl-maz@kernel.org/\n\nSigned-off-by: Marek Behún <kabel@kernel.org>\n---\n drivers/pci/controller/pci-aardvark.c | 26 ++++++++++++--------------\n 1 file changed, 12 insertions(+), 14 deletions(-)\n\n--- a/drivers/pci/controller/pci-aardvark.c\n+++ b/drivers/pci/controller/pci-aardvark.c\n@@ -274,8 +274,6 @@ struct advk_pcie {\n \traw_spinlock_t irq_lock;\n \tstruct irq_domain *msi_domain;\n \tstruct irq_domain *msi_inner_domain;\n-\tstruct irq_chip msi_bottom_irq_chip;\n-\tstruct irq_chip msi_irq_chip;\n \tstruct msi_domain_info msi_domain_info;\n \tDECLARE_BITMAP(msi_used, MSI_IRQ_NUM);\n \tstruct mutex msi_used_lock;\n@@ -1194,6 +1192,12 @@ static int advk_msi_set_affinity(struct\n \treturn -EINVAL;\n }\n \n+static struct irq_chip advk_msi_bottom_irq_chip = {\n+\t.name\t\t\t= \"MSI\",\n+\t.irq_compose_msi_msg\t= advk_msi_irq_compose_msi_msg,\n+\t.irq_set_affinity\t= advk_msi_set_affinity,\n+};\n+\n static int advk_msi_irq_domain_alloc(struct irq_domain *domain,\n \t\t\t\t     unsigned int virq,\n \t\t\t\t     unsigned int nr_irqs, void *args)\n@@ -1210,7 +1214,7 @@ static int advk_msi_irq_domain_alloc(str\n \n \tfor (i = 0; i < nr_irqs; i++)\n \t\tirq_domain_set_info(domain, virq + i, hwirq + i,\n-\t\t\t\t    &pcie->msi_bottom_irq_chip,\n+\t\t\t\t    &advk_msi_bottom_irq_chip,\n \t\t\t\t    domain->host_data, handle_simple_irq,\n \t\t\t\t    NULL, NULL);\n \n@@ -1280,29 +1284,23 @@ static const struct irq_domain_ops advk_\n \t.xlate = irq_domain_xlate_onecell,\n };\n \n+static struct irq_chip advk_msi_irq_chip = {\n+\t.name = \"advk-MSI\",\n+};\n+\n static int advk_pcie_init_msi_irq_domain(struct advk_pcie *pcie)\n {\n \tstruct device *dev = &pcie->pdev->dev;\n \tstruct device_node *node = dev->of_node;\n-\tstruct irq_chip *bottom_ic, *msi_ic;\n \tstruct msi_domain_info *msi_di;\n \tphys_addr_t msi_msg_phys;\n \n \tmutex_init(&pcie->msi_used_lock);\n \n-\tbottom_ic = &pcie->msi_bottom_irq_chip;\n-\n-\tbottom_ic->name = \"MSI\";\n-\tbottom_ic->irq_compose_msi_msg = advk_msi_irq_compose_msi_msg;\n-\tbottom_ic->irq_set_affinity = advk_msi_set_affinity;\n-\n-\tmsi_ic = &pcie->msi_irq_chip;\n-\tmsi_ic->name = \"advk-MSI\";\n-\n \tmsi_di = &pcie->msi_domain_info;\n \tmsi_di->flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |\n \t\tMSI_FLAG_MULTI_PCI_MSI;\n-\tmsi_di->chip = msi_ic;\n+\tmsi_di->chip = &advk_msi_irq_chip;\n \n \tmsi_msg_phys = virt_to_phys(&pcie->msi_msg);\n \n"
  },
  {
    "path": "target/linux/generic/pending-5.15/850-0007-PCI-aardvark-Make-msi_domain_info-structure-a-static.patch",
    "content": "From c092ab8994f1f777054c0179a9deb40b87ee606f Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Marek=20Beh=C3=BAn?= <kabel@kernel.org>\nDate: Mon, 10 Jan 2022 00:10:46 +0100\nSubject: [PATCH] PCI: aardvark: Make msi_domain_info structure a static driver\n structure\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nMake Aardvark's msi_domain_info structure into a private driver structure.\nDomain info is same for every potential instatination of a controller.\n\nSigned-off-by: Marek Behún <kabel@kernel.org>\n---\n drivers/pci/controller/pci-aardvark.c | 16 ++++++++--------\n 1 file changed, 8 insertions(+), 8 deletions(-)\n\n--- a/drivers/pci/controller/pci-aardvark.c\n+++ b/drivers/pci/controller/pci-aardvark.c\n@@ -274,7 +274,6 @@ struct advk_pcie {\n \traw_spinlock_t irq_lock;\n \tstruct irq_domain *msi_domain;\n \tstruct irq_domain *msi_inner_domain;\n-\tstruct msi_domain_info msi_domain_info;\n \tDECLARE_BITMAP(msi_used, MSI_IRQ_NUM);\n \tstruct mutex msi_used_lock;\n \tu16 msi_msg;\n@@ -1288,20 +1287,20 @@ static struct irq_chip advk_msi_irq_chip\n \t.name = \"advk-MSI\",\n };\n \n+static struct msi_domain_info advk_msi_domain_info = {\n+\t.flags\t= MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |\n+\t\t  MSI_FLAG_MULTI_PCI_MSI,\n+\t.chip\t= &advk_msi_irq_chip,\n+};\n+\n static int advk_pcie_init_msi_irq_domain(struct advk_pcie *pcie)\n {\n \tstruct device *dev = &pcie->pdev->dev;\n \tstruct device_node *node = dev->of_node;\n-\tstruct msi_domain_info *msi_di;\n \tphys_addr_t msi_msg_phys;\n \n \tmutex_init(&pcie->msi_used_lock);\n \n-\tmsi_di = &pcie->msi_domain_info;\n-\tmsi_di->flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |\n-\t\tMSI_FLAG_MULTI_PCI_MSI;\n-\tmsi_di->chip = &advk_msi_irq_chip;\n-\n \tmsi_msg_phys = virt_to_phys(&pcie->msi_msg);\n \n \tadvk_writel(pcie, lower_32_bits(msi_msg_phys),\n@@ -1317,7 +1316,8 @@ static int advk_pcie_init_msi_irq_domain\n \n \tpcie->msi_domain =\n \t\tpci_msi_create_irq_domain(of_node_to_fwnode(node),\n-\t\t\t\t\t  msi_di, pcie->msi_inner_domain);\n+\t\t\t\t\t  &advk_msi_domain_info,\n+\t\t\t\t\t  pcie->msi_inner_domain);\n \tif (!pcie->msi_domain) {\n \t\tirq_domain_remove(pcie->msi_inner_domain);\n \t\treturn -ENOMEM;\n"
  },
  {
    "path": "target/linux/generic/pending-5.15/850-0008-PCI-aardvark-Use-dev_fwnode-instead-of-of_node_to_fw.patch",
    "content": "From 59029739d42b439628e2f64f3d8f2db9be97deff Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Marek=20Beh=C3=BAn?= <kabel@kernel.org>\nDate: Mon, 10 Jan 2022 00:15:17 +0100\nSubject: [PATCH] PCI: aardvark: Use dev_fwnode() instead of\n of_node_to_fwnode(dev->of_node)\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nUse simple\n  dev_fwnode(dev)\ninstead of\n  struct device_node *node = dev->of_node;\n  of_node_to_fwnode(node)\nespecially since the node variable is not used elsewhere in the function.\n\nSigned-off-by: Marek Behún <kabel@kernel.org>\n---\n drivers/pci/controller/pci-aardvark.c | 3 +--\n 1 file changed, 1 insertion(+), 2 deletions(-)\n\n--- a/drivers/pci/controller/pci-aardvark.c\n+++ b/drivers/pci/controller/pci-aardvark.c\n@@ -1296,7 +1296,6 @@ static struct msi_domain_info advk_msi_d\n static int advk_pcie_init_msi_irq_domain(struct advk_pcie *pcie)\n {\n \tstruct device *dev = &pcie->pdev->dev;\n-\tstruct device_node *node = dev->of_node;\n \tphys_addr_t msi_msg_phys;\n \n \tmutex_init(&pcie->msi_used_lock);\n@@ -1315,7 +1314,7 @@ static int advk_pcie_init_msi_irq_domain\n \t\treturn -ENOMEM;\n \n \tpcie->msi_domain =\n-\t\tpci_msi_create_irq_domain(of_node_to_fwnode(node),\n+\t\tpci_msi_create_irq_domain(dev_fwnode(dev),\n \t\t\t\t\t  &advk_msi_domain_info,\n \t\t\t\t\t  pcie->msi_inner_domain);\n \tif (!pcie->msi_domain) {\n"
  },
  {
    "path": "target/linux/generic/pending-5.15/850-0009-PCI-aardvark-Refactor-unmasking-summary-MSI-interrup.patch",
    "content": "From 98feaf97bc64fc640a6c5b1394cd18fc7cd7dac8 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>\nDate: Sun, 28 Mar 2021 14:34:49 +0200\nSubject: [PATCH] PCI: aardvark: Refactor unmasking summary MSI interrupt\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nRefactor the masking of ISR0/1 Sources and unmasking of summary MSI interrupt\nso that it corresponds to the comments:\n- first mask all ISR0/1\n- then unmask all MSIs\n- then unmask summary MSI interrupt\n\nSigned-off-by: Pali Rohár <pali@kernel.org>\nSigned-off-by: Marek Behún <kabel@kernel.org>\n---\n drivers/pci/controller/pci-aardvark.c | 10 ++++++----\n 1 file changed, 6 insertions(+), 4 deletions(-)\n\n--- a/drivers/pci/controller/pci-aardvark.c\n+++ b/drivers/pci/controller/pci-aardvark.c\n@@ -571,15 +571,17 @@ static void advk_pcie_setup_hw(struct ad\n \tadvk_writel(pcie, PCIE_IRQ_ALL_MASK, HOST_CTRL_INT_STATUS_REG);\n \n \t/* Disable All ISR0/1 Sources */\n-\treg = PCIE_ISR0_ALL_MASK;\n-\treg &= ~PCIE_ISR0_MSI_INT_PENDING;\n-\tadvk_writel(pcie, reg, PCIE_ISR0_MASK_REG);\n-\n+\tadvk_writel(pcie, PCIE_ISR0_ALL_MASK, PCIE_ISR0_MASK_REG);\n \tadvk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_MASK_REG);\n \n \t/* Unmask all MSIs */\n \tadvk_writel(pcie, ~(u32)PCIE_MSI_ALL_MASK, PCIE_MSI_MASK_REG);\n \n+\t/* Unmask summary MSI interrupt */\n+\treg = advk_readl(pcie, PCIE_ISR0_MASK_REG);\n+\treg &= ~PCIE_ISR0_MSI_INT_PENDING;\n+\tadvk_writel(pcie, reg, PCIE_ISR0_MASK_REG);\n+\n \t/* Enable summary interrupt for GIC SPI source */\n \treg = PCIE_IRQ_ALL_MASK & (~PCIE_IRQ_ENABLE_INTS_MASK);\n \tadvk_writel(pcie, reg, HOST_CTRL_INT_MASK_REG);\n"
  },
  {
    "path": "target/linux/generic/pending-5.15/850-0010-PCI-aardvark-Add-support-for-masking-MSI-interrupts.patch",
    "content": "From 7f353accca6e4a3222991c65b1a6801503973bd3 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>\nDate: Fri, 2 Jul 2021 16:44:10 +0200\nSubject: [PATCH] PCI: aardvark: Add support for masking MSI interrupts\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nWe should not unmask MSIs at setup, but only when kernel asks for them\nto be unmasked.\n\nAt setup, mask all MSIs, and implement IRQ chip callbacks for masking\nand unmasking particular MSIs.\n\nSigned-off-by: Pali Rohár <pali@kernel.org>\nSigned-off-by: Marek Behún <kabel@kernel.org>\n---\n drivers/pci/controller/pci-aardvark.c | 54 ++++++++++++++++++++++++---\n 1 file changed, 49 insertions(+), 5 deletions(-)\n\n--- a/drivers/pci/controller/pci-aardvark.c\n+++ b/drivers/pci/controller/pci-aardvark.c\n@@ -274,6 +274,7 @@ struct advk_pcie {\n \traw_spinlock_t irq_lock;\n \tstruct irq_domain *msi_domain;\n \tstruct irq_domain *msi_inner_domain;\n+\traw_spinlock_t msi_irq_lock;\n \tDECLARE_BITMAP(msi_used, MSI_IRQ_NUM);\n \tstruct mutex msi_used_lock;\n \tu16 msi_msg;\n@@ -570,12 +571,10 @@ static void advk_pcie_setup_hw(struct ad\n \tadvk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_REG);\n \tadvk_writel(pcie, PCIE_IRQ_ALL_MASK, HOST_CTRL_INT_STATUS_REG);\n \n-\t/* Disable All ISR0/1 Sources */\n+\t/* Disable All ISR0/1 and MSI Sources */\n \tadvk_writel(pcie, PCIE_ISR0_ALL_MASK, PCIE_ISR0_MASK_REG);\n \tadvk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_MASK_REG);\n-\n-\t/* Unmask all MSIs */\n-\tadvk_writel(pcie, ~(u32)PCIE_MSI_ALL_MASK, PCIE_MSI_MASK_REG);\n+\tadvk_writel(pcie, PCIE_MSI_ALL_MASK, PCIE_MSI_MASK_REG);\n \n \t/* Unmask summary MSI interrupt */\n \treg = advk_readl(pcie, PCIE_ISR0_MASK_REG);\n@@ -1193,10 +1192,52 @@ static int advk_msi_set_affinity(struct\n \treturn -EINVAL;\n }\n \n+static void advk_msi_irq_mask(struct irq_data *d)\n+{\n+\tstruct advk_pcie *pcie = d->domain->host_data;\n+\tirq_hw_number_t hwirq = irqd_to_hwirq(d);\n+\tunsigned long flags;\n+\tu32 mask;\n+\n+\traw_spin_lock_irqsave(&pcie->msi_irq_lock, flags);\n+\tmask = advk_readl(pcie, PCIE_MSI_MASK_REG);\n+\tmask |= BIT(hwirq);\n+\tadvk_writel(pcie, mask, PCIE_MSI_MASK_REG);\n+\traw_spin_unlock_irqrestore(&pcie->msi_irq_lock, flags);\n+}\n+\n+static void advk_msi_irq_unmask(struct irq_data *d)\n+{\n+\tstruct advk_pcie *pcie = d->domain->host_data;\n+\tirq_hw_number_t hwirq = irqd_to_hwirq(d);\n+\tunsigned long flags;\n+\tu32 mask;\n+\n+\traw_spin_lock_irqsave(&pcie->msi_irq_lock, flags);\n+\tmask = advk_readl(pcie, PCIE_MSI_MASK_REG);\n+\tmask &= ~BIT(hwirq);\n+\tadvk_writel(pcie, mask, PCIE_MSI_MASK_REG);\n+\traw_spin_unlock_irqrestore(&pcie->msi_irq_lock, flags);\n+}\n+\n+static void advk_msi_top_irq_mask(struct irq_data *d)\n+{\n+\tpci_msi_mask_irq(d);\n+\tirq_chip_mask_parent(d);\n+}\n+\n+static void advk_msi_top_irq_unmask(struct irq_data *d)\n+{\n+\tpci_msi_unmask_irq(d);\n+\tirq_chip_unmask_parent(d);\n+}\n+\n static struct irq_chip advk_msi_bottom_irq_chip = {\n \t.name\t\t\t= \"MSI\",\n \t.irq_compose_msi_msg\t= advk_msi_irq_compose_msi_msg,\n \t.irq_set_affinity\t= advk_msi_set_affinity,\n+\t.irq_mask\t\t= advk_msi_irq_mask,\n+\t.irq_unmask\t\t= advk_msi_irq_unmask,\n };\n \n static int advk_msi_irq_domain_alloc(struct irq_domain *domain,\n@@ -1286,7 +1327,9 @@ static const struct irq_domain_ops advk_\n };\n \n static struct irq_chip advk_msi_irq_chip = {\n-\t.name = \"advk-MSI\",\n+\t.name\t\t= \"advk-MSI\",\n+\t.irq_mask\t= advk_msi_top_irq_mask,\n+\t.irq_unmask\t= advk_msi_top_irq_unmask,\n };\n \n static struct msi_domain_info advk_msi_domain_info = {\n@@ -1300,6 +1343,7 @@ static int advk_pcie_init_msi_irq_domain\n \tstruct device *dev = &pcie->pdev->dev;\n \tphys_addr_t msi_msg_phys;\n \n+\traw_spin_lock_init(&pcie->msi_irq_lock);\n \tmutex_init(&pcie->msi_used_lock);\n \n \tmsi_msg_phys = virt_to_phys(&pcie->msi_msg);\n"
  },
  {
    "path": "target/linux/generic/pending-5.15/850-0011-PCI-aardvark-Fix-setting-MSI-address.patch",
    "content": "From fa73c200f181436eab859374657c53a73778d8ad Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>\nDate: Fri, 26 Mar 2021 17:35:44 +0100\nSubject: [PATCH] PCI: aardvark: Fix setting MSI address\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nMSI address for receiving MSI interrupts needs to be correctly set before\nenabling processing of MSI interrupts.\n\nMove code for setting PCIE_MSI_ADDR_LOW_REG and PCIE_MSI_ADDR_HIGH_REG\nfrom advk_pcie_init_msi_irq_domain() to advk_pcie_setup_hw(), before\nenabling PCIE_CORE_CTRL2_MSI_ENABLE.\n\nAfter this we can remove the now unused member msi_msg, which was used\nonly for MSI doorbell address. MSI address can be any address which cannot\nbe used to DMA to. So change it to the address of the main struct advk_pcie.\n\nFixes: 8c39d710363c (\"PCI: aardvark: Add Aardvark PCI host controller driver\")\nSigned-off-by: Pali Rohár <pali@kernel.org>\nAcked-by: Marc Zyngier <maz@kernel.org>\nSigned-off-by: Marek Behún <kabel@kernel.org>\nCc: stable@vger.kernel.org # f21a8b1b6837 (\"PCI: aardvark: Move to MSI handling using generic MSI support\")\n---\n drivers/pci/controller/pci-aardvark.c | 21 +++++++++------------\n 1 file changed, 9 insertions(+), 12 deletions(-)\n\n--- a/drivers/pci/controller/pci-aardvark.c\n+++ b/drivers/pci/controller/pci-aardvark.c\n@@ -277,7 +277,6 @@ struct advk_pcie {\n \traw_spinlock_t msi_irq_lock;\n \tDECLARE_BITMAP(msi_used, MSI_IRQ_NUM);\n \tstruct mutex msi_used_lock;\n-\tu16 msi_msg;\n \tint link_gen;\n \tstruct pci_bridge_emul bridge;\n \tstruct gpio_desc *reset_gpio;\n@@ -472,6 +471,7 @@ static void advk_pcie_disable_ob_win(str\n \n static void advk_pcie_setup_hw(struct advk_pcie *pcie)\n {\n+\tphys_addr_t msi_addr;\n \tu32 reg;\n \tint i;\n \n@@ -560,6 +560,11 @@ static void advk_pcie_setup_hw(struct ad\n \treg |= LANE_COUNT_1;\n \tadvk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);\n \n+\t/* Set MSI address */\n+\tmsi_addr = virt_to_phys(pcie);\n+\tadvk_writel(pcie, lower_32_bits(msi_addr), PCIE_MSI_ADDR_LOW_REG);\n+\tadvk_writel(pcie, upper_32_bits(msi_addr), PCIE_MSI_ADDR_HIGH_REG);\n+\n \t/* Enable MSI */\n \treg = advk_readl(pcie, PCIE_CORE_CTRL2_REG);\n \treg |= PCIE_CORE_CTRL2_MSI_ENABLE;\n@@ -1179,10 +1184,10 @@ static void advk_msi_irq_compose_msi_msg\n \t\t\t\t\t struct msi_msg *msg)\n {\n \tstruct advk_pcie *pcie = irq_data_get_irq_chip_data(data);\n-\tphys_addr_t msi_msg = virt_to_phys(&pcie->msi_msg);\n+\tphys_addr_t msi_addr = virt_to_phys(pcie);\n \n-\tmsg->address_lo = lower_32_bits(msi_msg);\n-\tmsg->address_hi = upper_32_bits(msi_msg);\n+\tmsg->address_lo = lower_32_bits(msi_addr);\n+\tmsg->address_hi = upper_32_bits(msi_addr);\n \tmsg->data = data->hwirq;\n }\n \n@@ -1341,18 +1346,10 @@ static struct msi_domain_info advk_msi_d\n static int advk_pcie_init_msi_irq_domain(struct advk_pcie *pcie)\n {\n \tstruct device *dev = &pcie->pdev->dev;\n-\tphys_addr_t msi_msg_phys;\n \n \traw_spin_lock_init(&pcie->msi_irq_lock);\n \tmutex_init(&pcie->msi_used_lock);\n \n-\tmsi_msg_phys = virt_to_phys(&pcie->msi_msg);\n-\n-\tadvk_writel(pcie, lower_32_bits(msi_msg_phys),\n-\t\t    PCIE_MSI_ADDR_LOW_REG);\n-\tadvk_writel(pcie, upper_32_bits(msi_msg_phys),\n-\t\t    PCIE_MSI_ADDR_HIGH_REG);\n-\n \tpcie->msi_inner_domain =\n \t\tirq_domain_add_linear(NULL, MSI_IRQ_NUM,\n \t\t\t\t      &advk_msi_domain_ops, pcie);\n"
  },
  {
    "path": "target/linux/generic/pending-5.15/850-0012-PCI-aardvark-Enable-MSI-X-support.patch",
    "content": "From 735a4ac9782b96fbe1543c578aa8334364f21abd Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>\nDate: Fri, 2 Apr 2021 14:05:24 +0200\nSubject: [PATCH] PCI: aardvark: Enable MSI-X support\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nAccording to PCI 3.0 specification, sending both MSI and MSI-X interrupts\nis done by DWORD memory write operation to doorbell message address. The\nwrite operation for MSI has zero upper 16 bits and the MSI interrupt number\nin the lower 16 bits, while the write operation for MSI-X contains a 32-bit\nvalue from MSI-X table.\n\nSince the driver only uses interrupt numbers from range 0..31, the upper\n16 bits of the DWORD memory write operation to doorbell message address\nare zero even for MSI-X interrupts. Thus we can enable MSI-X interrupts.\n\nTesting proves that kernel can correctly receive MSI-X interrupts from PCIe\ncards which supports both MSI and MSI-X interrupts.\n\nSigned-off-by: Pali Rohár <pali@kernel.org>\nSigned-off-by: Marek Behún <kabel@kernel.org>\n---\n drivers/pci/controller/pci-aardvark.c | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/drivers/pci/controller/pci-aardvark.c\n+++ b/drivers/pci/controller/pci-aardvark.c\n@@ -1339,7 +1339,7 @@ static struct irq_chip advk_msi_irq_chip\n \n static struct msi_domain_info advk_msi_domain_info = {\n \t.flags\t= MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |\n-\t\t  MSI_FLAG_MULTI_PCI_MSI,\n+\t\t  MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX,\n \t.chip\t= &advk_msi_irq_chip,\n };\n \n"
  },
  {
    "path": "target/linux/generic/pending-5.15/850-0013-PCI-aardvark-Add-support-for-ERR-interrupt-on-emulat.patch",
    "content": "From 7f3e55a3890fa26d15e2e4e90213962d1a7f6df9 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>\nDate: Fri, 12 Feb 2021 20:32:55 +0100\nSubject: [PATCH] PCI: aardvark: Add support for ERR interrupt on emulated\n bridge\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nERR interrupt is triggered when corresponding bit is unmasked in both ISR0\nand PCI_EXP_DEVCTL registers. Unmasking ERR bits in PCI_EXP_DEVCTL register\nis not enough. This means that currently the ERR interrupt is never\ntriggered.\n\nUnmask ERR bits in ISR0 register at driver probe time. ERR interrupt is not\ntriggered until ERR bits are unmasked also in PCI_EXP_DEVCTL register,\nwhich is done by AER driver. So it is safe to unconditionally unmask all\nERR bits in aardvark probe.\n\nAardvark HW sets PCI_ERR_ROOT_AER_IRQ to zero and when corresponding bits\nin ISR0 and PCI_EXP_DEVCTL are enabled, the HW triggers a generic interrupt\non GIC. Chain this interrupt to PCIe interrupt 0 with\ngeneric_handle_domain_irq() to allow processing of ERR interrupts.\n\nSigned-off-by: Pali Rohár <pali@kernel.org>\nSigned-off-by: Marek Behún <kabel@kernel.org>\n---\n drivers/pci/controller/pci-aardvark.c | 36 ++++++++++++++++++++++++++-\n 1 file changed, 35 insertions(+), 1 deletion(-)\n\n--- a/drivers/pci/controller/pci-aardvark.c\n+++ b/drivers/pci/controller/pci-aardvark.c\n@@ -98,6 +98,10 @@\n #define PCIE_MSG_PM_PME_MASK\t\t\tBIT(7)\n #define PCIE_ISR0_MASK_REG\t\t\t(CONTROL_BASE_ADDR + 0x44)\n #define     PCIE_ISR0_MSI_INT_PENDING\t\tBIT(24)\n+#define     PCIE_ISR0_CORR_ERR\t\t\tBIT(11)\n+#define     PCIE_ISR0_NFAT_ERR\t\t\tBIT(12)\n+#define     PCIE_ISR0_FAT_ERR\t\t\tBIT(13)\n+#define     PCIE_ISR0_ERR_MASK\t\t\tGENMASK(13, 11)\n #define     PCIE_ISR0_INTX_ASSERT(val)\t\tBIT(16 + (val))\n #define     PCIE_ISR0_INTX_DEASSERT(val)\tBIT(20 + (val))\n #define     PCIE_ISR0_ALL_MASK\t\t\tGENMASK(31, 0)\n@@ -778,11 +782,15 @@ advk_pci_bridge_emul_base_conf_read(stru\n \tcase PCI_INTERRUPT_LINE: {\n \t\t/*\n \t\t * From the whole 32bit register we support reading from HW only\n-\t\t * one bit: PCI_BRIDGE_CTL_BUS_RESET.\n+\t\t * two bits: PCI_BRIDGE_CTL_BUS_RESET and PCI_BRIDGE_CTL_SERR.\n \t\t * Other bits are retrieved only from emulated config buffer.\n \t\t */\n \t\t__le32 *cfgspace = (__le32 *)&bridge->conf;\n \t\tu32 val = le32_to_cpu(cfgspace[PCI_INTERRUPT_LINE / 4]);\n+\t\tif (advk_readl(pcie, PCIE_ISR0_MASK_REG) & PCIE_ISR0_ERR_MASK)\n+\t\t\tval &= ~(PCI_BRIDGE_CTL_SERR << 16);\n+\t\telse\n+\t\t\tval |= PCI_BRIDGE_CTL_SERR << 16;\n \t\tif (advk_readl(pcie, PCIE_CORE_CTRL1_REG) & HOT_RESET_GEN)\n \t\t\tval |= PCI_BRIDGE_CTL_BUS_RESET << 16;\n \t\telse\n@@ -808,6 +816,19 @@ advk_pci_bridge_emul_base_conf_write(str\n \t\tbreak;\n \n \tcase PCI_INTERRUPT_LINE:\n+\t\t/*\n+\t\t * According to Figure 6-3: Pseudo Logic Diagram for Error\n+\t\t * Message Controls in PCIe base specification, SERR# Enable bit\n+\t\t * in Bridge Control register enable receiving of ERR_* messages\n+\t\t */\n+\t\tif (mask & (PCI_BRIDGE_CTL_SERR << 16)) {\n+\t\t\tu32 val = advk_readl(pcie, PCIE_ISR0_MASK_REG);\n+\t\t\tif (new & (PCI_BRIDGE_CTL_SERR << 16))\n+\t\t\t\tval &= ~PCIE_ISR0_ERR_MASK;\n+\t\t\telse\n+\t\t\t\tval |= PCIE_ISR0_ERR_MASK;\n+\t\t\tadvk_writel(pcie, val, PCIE_ISR0_MASK_REG);\n+\t\t}\n \t\tif (mask & (PCI_BRIDGE_CTL_BUS_RESET << 16)) {\n \t\t\tu32 val = advk_readl(pcie, PCIE_CORE_CTRL1_REG);\n \t\t\tif (new & (PCI_BRIDGE_CTL_BUS_RESET << 16))\n@@ -1457,6 +1478,18 @@ static void advk_pcie_handle_int(struct\n \tisr1_mask = advk_readl(pcie, PCIE_ISR1_MASK_REG);\n \tisr1_status = isr1_val & ((~isr1_mask) & PCIE_ISR1_ALL_MASK);\n \n+\t/* Process ERR interrupt */\n+\tif (isr0_status & PCIE_ISR0_ERR_MASK) {\n+\t\tadvk_writel(pcie, PCIE_ISR0_ERR_MASK, PCIE_ISR0_REG);\n+\n+\t\t/*\n+\t\t * Aardvark HW returns zero for PCI_ERR_ROOT_AER_IRQ, so use\n+\t\t * PCIe interrupt 0\n+\t\t */\n+\t\tif (generic_handle_domain_irq(pcie->irq_domain, 0) == -EINVAL)\n+\t\t\tdev_err_ratelimited(&pcie->pdev->dev, \"unhandled ERR IRQ\\n\");\n+\t}\n+\n \t/* Process MSI interrupts */\n \tif (isr0_status & PCIE_ISR0_MSI_INT_PENDING)\n \t\tadvk_pcie_handle_msi(pcie);\n"
  },
  {
    "path": "target/linux/generic/pending-5.15/850-0015-PCI-aardvark-Optimize-writing-PCI_EXP_RTCTL_PMEIE-an.patch",
    "content": "From 3fe0073d116d9902df08761c1cf0d733dd4c38fc Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>\nDate: Wed, 8 Dec 2021 06:03:50 +0100\nSubject: [PATCH] PCI: aardvark: Optimize writing PCI_EXP_RTCTL_PMEIE and\n PCI_EXP_RTSTA_PME on emulated bridge\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nTo optimize advk_pci_bridge_emul_pcie_conf_write() code, touch\nPCIE_ISR0_REG and PCIE_ISR0_MASK_REG registers only when it is really\nneeded, when processing PCI_EXP_RTCTL_PMEIE and PCI_EXP_RTSTA_PME bits.\n\nSigned-off-by: Pali Rohár <pali@kernel.org>\nSigned-off-by: Marek Behún <kabel@kernel.org>\n---\n drivers/pci/controller/pci-aardvark.c | 20 +++++++++++---------\n 1 file changed, 11 insertions(+), 9 deletions(-)\n\n--- a/drivers/pci/controller/pci-aardvark.c\n+++ b/drivers/pci/controller/pci-aardvark.c\n@@ -925,19 +925,21 @@ advk_pci_bridge_emul_pcie_conf_write(str\n \t\t\tadvk_pcie_wait_for_retrain(pcie);\n \t\tbreak;\n \n-\tcase PCI_EXP_RTCTL: {\n+\tcase PCI_EXP_RTCTL:\n \t\t/* Only mask/unmask PME interrupt */\n-\t\tu32 val = advk_readl(pcie, PCIE_ISR0_MASK_REG) &\n-\t\t\t~PCIE_MSG_PM_PME_MASK;\n-\t\tif ((new & PCI_EXP_RTCTL_PMEIE) == 0)\n-\t\t\tval |= PCIE_MSG_PM_PME_MASK;\n-\t\tadvk_writel(pcie, val, PCIE_ISR0_MASK_REG);\n+\t\tif (mask & PCI_EXP_RTCTL_PMEIE) {\n+\t\t\tu32 val = advk_readl(pcie, PCIE_ISR0_MASK_REG);\n+\t\t\tif (new & PCI_EXP_RTCTL_PMEIE)\n+\t\t\t\tval &= ~PCIE_MSG_PM_PME_MASK;\n+\t\t\telse\n+\t\t\t\tval |= PCIE_MSG_PM_PME_MASK;\n+\t\t\tadvk_writel(pcie, val, PCIE_ISR0_MASK_REG);\n+\t\t}\n \t\tbreak;\n-\t}\n \n \tcase PCI_EXP_RTSTA:\n-\t\tnew = (new & PCI_EXP_RTSTA_PME) >> 9;\n-\t\tadvk_writel(pcie, new, PCIE_ISR0_REG);\n+\t\tif (new & PCI_EXP_RTSTA_PME)\n+\t\t\tadvk_writel(pcie, PCIE_MSG_PM_PME_MASK, PCIE_ISR0_REG);\n \t\tbreak;\n \n \tcase PCI_EXP_DEVCTL:\n"
  },
  {
    "path": "target/linux/generic/pending-5.15/850-0016-PCI-aardvark-Add-support-for-PME-interrupts.patch",
    "content": "From 7acd8ef92e8789e10b5d736d73cea3b625087f26 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>\nDate: Wed, 8 Dec 2021 06:07:44 +0100\nSubject: [PATCH] PCI: aardvark: Add support for PME interrupts\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nCurrently enabling PCI_EXP_RTSTA_PME bit in PCI_EXP_RTCTL register does\nnothing. This is because PCIe PME driver expects to receive PCIe interrupt\ndefined in PCI_EXP_FLAGS_IRQ register, but aardvark hardware does not\ntrigger PCIe INTx/MSI interrupt for PME event, rather it triggers custom\naardvark interrupt which this driver is not processing yet.\n\nFix this issue by handling PME interrupt in advk_pcie_handle_int() and\nchaining it to PCIe interrupt 0 with generic_handle_domain_irq() (since\naardvark sets PCI_EXP_FLAGS_IRQ to zero). With this change PCIe PME driver\nfinally starts receiving PME interrupt.\n\nSigned-off-by: Pali Rohár <pali@kernel.org>\nSigned-off-by: Marek Behún <kabel@kernel.org>\n---\n drivers/pci/controller/pci-aardvark.c | 13 +++++++++++++\n 1 file changed, 13 insertions(+)\n\n--- a/drivers/pci/controller/pci-aardvark.c\n+++ b/drivers/pci/controller/pci-aardvark.c\n@@ -1480,6 +1480,18 @@ static void advk_pcie_handle_int(struct\n \tisr1_mask = advk_readl(pcie, PCIE_ISR1_MASK_REG);\n \tisr1_status = isr1_val & ((~isr1_mask) & PCIE_ISR1_ALL_MASK);\n \n+\t/* Process PME interrupt */\n+\tif (isr0_status & PCIE_MSG_PM_PME_MASK) {\n+\t\t/*\n+\t\t * Do not clear PME interrupt bit in ISR0, it is cleared by IRQ\n+\t\t * receiver by writing to the PCI_EXP_RTSTA register of emulated\n+\t\t * root bridge. Aardvark HW returns zero for PCI_EXP_FLAGS_IRQ,\n+\t\t * so use PCIe interrupt 0.\n+\t\t */\n+\t\tif (generic_handle_domain_irq(pcie->irq_domain, 0) == -EINVAL)\n+\t\t\tdev_err_ratelimited(&pcie->pdev->dev, \"unhandled PME IRQ\\n\");\n+\t}\n+\n \t/* Process ERR interrupt */\n \tif (isr0_status & PCIE_ISR0_ERR_MASK) {\n \t\tadvk_writel(pcie, PCIE_ISR0_ERR_MASK, PCIE_ISR0_REG);\n"
  },
  {
    "path": "target/linux/generic/pending-5.15/850-0017-PCI-aardvark-Fix-support-for-PME-requester-on-emulat.patch",
    "content": "From 68727b545332327b4c2f9c0f8d006be8970e7832 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>\nDate: Fri, 19 Feb 2021 14:22:22 +0100\nSubject: [PATCH] PCI: aardvark: Fix support for PME requester on emulated\n bridge\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nEnable aardvark PME interrupt unconditionally by unmasking it and read PME\nrequester ID to emulated bridge config space immediately after receiving\ninterrupt.\n\nPME requester ID is stored in the PCIE_MSG_LOG_REG register, which contains\nthe last inbound message. So when new inbound message is received by HW\n(including non-PM), the content in PCIE_MSG_LOG_REG register is replaced by\na new value.\n\nPCIe specification mandates that subsequent PMEs are kept pending until the\nPME Status Register bit is cleared by software by writing a 1b.\n\nSupport for masking/unmasking PME interrupt on emulated bridge via\nPCI_EXP_RTCTL_PMEIE bit is now implemented only in emulated bridge config\nspace, to ensure that we do not miss any aardvark PME interrupt.\n\nReading of PCI_EXP_RTCAP and PCI_EXP_RTSTA registers is simplified as final\nvalue is now always stored into emulated bridge config space by the\ninterrupt handler, so there is no need to implement support for these\nregisters in read_pcie callback.\n\nClearing of W1C bit PCI_EXP_RTSTA_PME is now also simplified as it is done\nby pci-bridge-emul.c code for emulated bridge config space. So there is no\nneed to implement support for clearing this bit in write_pcie callback.\n\nSigned-off-by: Pali Rohár <pali@kernel.org>\nSigned-off-by: Marek Behún <kabel@kernel.org>\n---\n drivers/pci/controller/pci-aardvark.c | 94 +++++++++++++++------------\n 1 file changed, 52 insertions(+), 42 deletions(-)\n\n--- a/drivers/pci/controller/pci-aardvark.c\n+++ b/drivers/pci/controller/pci-aardvark.c\n@@ -590,6 +590,11 @@ static void advk_pcie_setup_hw(struct ad\n \treg &= ~PCIE_ISR0_MSI_INT_PENDING;\n \tadvk_writel(pcie, reg, PCIE_ISR0_MASK_REG);\n \n+\t/* Unmask PME interrupt for processing of PME requester */\n+\treg = advk_readl(pcie, PCIE_ISR0_MASK_REG);\n+\treg &= ~PCIE_MSG_PM_PME_MASK;\n+\tadvk_writel(pcie, reg, PCIE_ISR0_MASK_REG);\n+\n \t/* Enable summary interrupt for GIC SPI source */\n \treg = PCIE_IRQ_ALL_MASK & (~PCIE_IRQ_ENABLE_INTS_MASK);\n \tadvk_writel(pcie, reg, HOST_CTRL_INT_MASK_REG);\n@@ -856,22 +861,11 @@ advk_pci_bridge_emul_pcie_conf_read(stru\n \t\t*value = PCI_EXP_SLTSTA_PDS << 16;\n \t\treturn PCI_BRIDGE_EMUL_HANDLED;\n \n-\tcase PCI_EXP_RTCTL: {\n-\t\tu32 val = advk_readl(pcie, PCIE_ISR0_MASK_REG);\n-\t\t*value = (val & PCIE_MSG_PM_PME_MASK) ? 0 : PCI_EXP_RTCTL_PMEIE;\n-\t\t*value |= le16_to_cpu(bridge->pcie_conf.rootctl) & PCI_EXP_RTCTL_CRSSVE;\n-\t\t*value |= PCI_EXP_RTCAP_CRSVIS << 16;\n-\t\treturn PCI_BRIDGE_EMUL_HANDLED;\n-\t}\n-\n-\tcase PCI_EXP_RTSTA: {\n-\t\tu32 isr0 = advk_readl(pcie, PCIE_ISR0_REG);\n-\t\tu32 msglog = advk_readl(pcie, PCIE_MSG_LOG_REG);\n-\t\t*value = msglog >> 16;\n-\t\tif (isr0 & PCIE_MSG_PM_PME_MASK)\n-\t\t\t*value |= PCI_EXP_RTSTA_PME;\n-\t\treturn PCI_BRIDGE_EMUL_HANDLED;\n-\t}\n+\t/*\n+\t * PCI_EXP_RTCTL and PCI_EXP_RTSTA are also supported, but do not need\n+\t * to be handled here, because their values are stored in emulated\n+\t * config space buffer, and we read them from there when needed.\n+\t */\n \n \tcase PCI_EXP_LNKCAP: {\n \t\tu32 val = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + reg);\n@@ -925,22 +919,19 @@ advk_pci_bridge_emul_pcie_conf_write(str\n \t\t\tadvk_pcie_wait_for_retrain(pcie);\n \t\tbreak;\n \n-\tcase PCI_EXP_RTCTL:\n-\t\t/* Only mask/unmask PME interrupt */\n-\t\tif (mask & PCI_EXP_RTCTL_PMEIE) {\n-\t\t\tu32 val = advk_readl(pcie, PCIE_ISR0_MASK_REG);\n-\t\t\tif (new & PCI_EXP_RTCTL_PMEIE)\n-\t\t\t\tval &= ~PCIE_MSG_PM_PME_MASK;\n-\t\t\telse\n-\t\t\t\tval |= PCIE_MSG_PM_PME_MASK;\n-\t\t\tadvk_writel(pcie, val, PCIE_ISR0_MASK_REG);\n-\t\t}\n+\tcase PCI_EXP_RTCTL: {\n+\t\tu16 rootctl = le16_to_cpu(bridge->pcie_conf.rootctl);\n+\t\t/* Only emulation of PMEIE and CRSSVE bits is provided */\n+\t\trootctl &= PCI_EXP_RTCTL_PMEIE | PCI_EXP_RTCTL_CRSSVE;\n+\t\tbridge->pcie_conf.rootctl = cpu_to_le16(rootctl);\n \t\tbreak;\n+\t}\n \n-\tcase PCI_EXP_RTSTA:\n-\t\tif (new & PCI_EXP_RTSTA_PME)\n-\t\t\tadvk_writel(pcie, PCIE_MSG_PM_PME_MASK, PCIE_ISR0_REG);\n-\t\tbreak;\n+\t/*\n+\t * PCI_EXP_RTSTA is also supported, but does not need to be handled\n+\t * here, because its value is stored in emulated config space buffer,\n+\t * and we write it there when needed.\n+\t */\n \n \tcase PCI_EXP_DEVCTL:\n \tcase PCI_EXP_DEVCTL2:\n@@ -1445,6 +1436,32 @@ static void advk_pcie_remove_irq_domain(\n \tirq_domain_remove(pcie->irq_domain);\n }\n \n+static void advk_pcie_handle_pme(struct advk_pcie *pcie)\n+{\n+\tu32 requester = advk_readl(pcie, PCIE_MSG_LOG_REG) >> 16;\n+\n+\tadvk_writel(pcie, PCIE_MSG_PM_PME_MASK, PCIE_ISR0_REG);\n+\n+\t/*\n+\t * PCIE_MSG_LOG_REG contains the last inbound message, so store\n+\t * the requester ID only when PME was not asserted yet.\n+\t * Also do not trigger PME interrupt when PME is still asserted.\n+\t */\n+\tif (!(le32_to_cpu(pcie->bridge.pcie_conf.rootsta) & PCI_EXP_RTSTA_PME)) {\n+\t\tpcie->bridge.pcie_conf.rootsta = cpu_to_le32(requester | PCI_EXP_RTSTA_PME);\n+\n+\t\t/*\n+\t\t * Trigger PME interrupt only if PMEIE bit in Root Control is set.\n+\t\t * Aardvark HW returns zero for PCI_EXP_FLAGS_IRQ, so use PCIe interrupt 0.\n+\t\t */\n+\t\tif (!(le16_to_cpu(pcie->bridge.pcie_conf.rootctl) & PCI_EXP_RTCTL_PMEIE))\n+\t\t\treturn;\n+\n+\t\tif (generic_handle_domain_irq(pcie->irq_domain, 0) == -EINVAL)\n+\t\t\tdev_err_ratelimited(&pcie->pdev->dev, \"unhandled PME IRQ\\n\");\n+\t}\n+}\n+\n static void advk_pcie_handle_msi(struct advk_pcie *pcie)\n {\n \tu32 msi_val, msi_mask, msi_status, msi_idx;\n@@ -1480,17 +1497,9 @@ static void advk_pcie_handle_int(struct\n \tisr1_mask = advk_readl(pcie, PCIE_ISR1_MASK_REG);\n \tisr1_status = isr1_val & ((~isr1_mask) & PCIE_ISR1_ALL_MASK);\n \n-\t/* Process PME interrupt */\n-\tif (isr0_status & PCIE_MSG_PM_PME_MASK) {\n-\t\t/*\n-\t\t * Do not clear PME interrupt bit in ISR0, it is cleared by IRQ\n-\t\t * receiver by writing to the PCI_EXP_RTSTA register of emulated\n-\t\t * root bridge. Aardvark HW returns zero for PCI_EXP_FLAGS_IRQ,\n-\t\t * so use PCIe interrupt 0.\n-\t\t */\n-\t\tif (generic_handle_domain_irq(pcie->irq_domain, 0) == -EINVAL)\n-\t\t\tdev_err_ratelimited(&pcie->pdev->dev, \"unhandled PME IRQ\\n\");\n-\t}\n+\t/* Process PME interrupt as the first one to do not miss PME requester id */\n+\tif (isr0_status & PCIE_MSG_PM_PME_MASK)\n+\t\tadvk_pcie_handle_pme(pcie);\n \n \t/* Process ERR interrupt */\n \tif (isr0_status & PCIE_ISR0_ERR_MASK) {\n"
  },
  {
    "path": "target/linux/generic/pending-5.15/850-0018-PCI-aardvark-Use-separate-INTA-interrupt-for-emulate.patch",
    "content": "From db305233136f5aa2444a8287a279384e8458c458 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>\nDate: Thu, 1 Apr 2021 20:12:48 +0200\nSubject: [PATCH] PCI: aardvark: Use separate INTA interrupt for emulated root\n bridge\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nEmulated root bridge currently provides only one Legacy INTA interrupt\nwhich is used for reporting PCIe PME and ERR events and handled by kernel\nPCIe PME and AER drivers.\n\nAardvark HW reports these PME and ERR events separately, so there is no\nneed to mix real INTA interrupt and emulated INTA interrupt for PCIe PME\nand AER drivers.\n\nRegister a new advk-RP (as in Root Port) irq chip and a new irq domain\nfor emulated root bridge and use this new separate irq domain for\nproviding INTA interrupt from emulated root bridge for PME and ERR events.\n\nThe real INTA interrupt from real devices is now separate.\n\nA custom map_irq callback function on PCI host bridge structure is used to\nallocate IRQ mapping for emulated root bridge from new irq domain. Original\ncallback of_irq_parse_and_map_pci() is used for all other devices as before.\n\nSigned-off-by: Pali Rohár <pali@kernel.org>\nSigned-off-by: Marek Behún <kabel@kernel.org>\n---\n drivers/pci/controller/pci-aardvark.c | 69 ++++++++++++++++++++++++++-\n 1 file changed, 67 insertions(+), 2 deletions(-)\n\n--- a/drivers/pci/controller/pci-aardvark.c\n+++ b/drivers/pci/controller/pci-aardvark.c\n@@ -273,6 +273,7 @@ struct advk_pcie {\n \t} wins[OB_WIN_COUNT];\n \tu8 wins_count;\n \tint irq;\n+\tstruct irq_domain *rp_irq_domain;\n \tstruct irq_domain *irq_domain;\n \tstruct irq_chip irq_chip;\n \traw_spinlock_t irq_lock;\n@@ -1436,6 +1437,44 @@ static void advk_pcie_remove_irq_domain(\n \tirq_domain_remove(pcie->irq_domain);\n }\n \n+static struct irq_chip advk_rp_irq_chip = {\n+\t.name = \"advk-RP\",\n+};\n+\n+static int advk_pcie_rp_irq_map(struct irq_domain *h,\n+\t\t\t\tunsigned int virq, irq_hw_number_t hwirq)\n+{\n+\tstruct advk_pcie *pcie = h->host_data;\n+\n+\tirq_set_chip_and_handler(virq, &advk_rp_irq_chip, handle_simple_irq);\n+\tirq_set_chip_data(virq, pcie);\n+\n+\treturn 0;\n+}\n+\n+static const struct irq_domain_ops advk_pcie_rp_irq_domain_ops = {\n+\t.map = advk_pcie_rp_irq_map,\n+\t.xlate = irq_domain_xlate_onecell,\n+};\n+\n+static int advk_pcie_init_rp_irq_domain(struct advk_pcie *pcie)\n+{\n+\tpcie->rp_irq_domain = irq_domain_add_linear(NULL, 1,\n+\t\t\t\t\t\t    &advk_pcie_rp_irq_domain_ops,\n+\t\t\t\t\t\t    pcie);\n+\tif (!pcie->rp_irq_domain) {\n+\t\tdev_err(&pcie->pdev->dev, \"Failed to add Root Port IRQ domain\\n\");\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static void advk_pcie_remove_rp_irq_domain(struct advk_pcie *pcie)\n+{\n+\tirq_domain_remove(pcie->rp_irq_domain);\n+}\n+\n static void advk_pcie_handle_pme(struct advk_pcie *pcie)\n {\n \tu32 requester = advk_readl(pcie, PCIE_MSG_LOG_REG) >> 16;\n@@ -1457,7 +1496,7 @@ static void advk_pcie_handle_pme(struct\n \t\tif (!(le16_to_cpu(pcie->bridge.pcie_conf.rootctl) & PCI_EXP_RTCTL_PMEIE))\n \t\t\treturn;\n \n-\t\tif (generic_handle_domain_irq(pcie->irq_domain, 0) == -EINVAL)\n+\t\tif (generic_handle_domain_irq(pcie->rp_irq_domain, 0) == -EINVAL)\n \t\t\tdev_err_ratelimited(&pcie->pdev->dev, \"unhandled PME IRQ\\n\");\n \t}\n }\n@@ -1509,7 +1548,7 @@ static void advk_pcie_handle_int(struct\n \t\t * Aardvark HW returns zero for PCI_ERR_ROOT_AER_IRQ, so use\n \t\t * PCIe interrupt 0\n \t\t */\n-\t\tif (generic_handle_domain_irq(pcie->irq_domain, 0) == -EINVAL)\n+\t\tif (generic_handle_domain_irq(pcie->rp_irq_domain, 0) == -EINVAL)\n \t\t\tdev_err_ratelimited(&pcie->pdev->dev, \"unhandled ERR IRQ\\n\");\n \t}\n \n@@ -1553,6 +1592,21 @@ static void advk_pcie_irq_handler(struct\n \tchained_irq_exit(chip, desc);\n }\n \n+static int advk_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)\n+{\n+\tstruct advk_pcie *pcie = dev->bus->sysdata;\n+\n+\t/*\n+\t * Emulated root bridge has its own emulated irq chip and irq domain.\n+\t * Argument pin is the INTx pin (1=INTA, 2=INTB, 3=INTC, 4=INTD) and\n+\t * hwirq for irq_create_mapping() is indexed from zero.\n+\t */\n+\tif (pci_is_root_bus(dev->bus))\n+\t\treturn irq_create_mapping(pcie->rp_irq_domain, pin - 1);\n+\telse\n+\t\treturn of_irq_parse_and_map_pci(dev, slot, pin);\n+}\n+\n static void __maybe_unused advk_pcie_disable_phy(struct advk_pcie *pcie)\n {\n \tphy_power_off(pcie->phy);\n@@ -1754,14 +1808,24 @@ static int advk_pcie_probe(struct platfo\n \t\treturn ret;\n \t}\n \n+\tret = advk_pcie_init_rp_irq_domain(pcie);\n+\tif (ret) {\n+\t\tdev_err(dev, \"Failed to initialize irq\\n\");\n+\t\tadvk_pcie_remove_msi_irq_domain(pcie);\n+\t\tadvk_pcie_remove_irq_domain(pcie);\n+\t\treturn ret;\n+\t}\n+\n \tirq_set_chained_handler_and_data(pcie->irq, advk_pcie_irq_handler, pcie);\n \n \tbridge->sysdata = pcie;\n \tbridge->ops = &advk_pcie_ops;\n+\tbridge->map_irq = advk_pcie_map_irq;\n \n \tret = pci_host_probe(bridge);\n \tif (ret < 0) {\n \t\tirq_set_chained_handler_and_data(pcie->irq, NULL, NULL);\n+\t\tadvk_pcie_remove_rp_irq_domain(pcie);\n \t\tadvk_pcie_remove_msi_irq_domain(pcie);\n \t\tadvk_pcie_remove_irq_domain(pcie);\n \t\treturn ret;\n@@ -1813,6 +1877,7 @@ static int advk_pcie_remove(struct platf\n \tirq_set_chained_handler_and_data(pcie->irq, NULL, NULL);\n \n \t/* Remove IRQ domains */\n+\tadvk_pcie_remove_rp_irq_domain(pcie);\n \tadvk_pcie_remove_msi_irq_domain(pcie);\n \tadvk_pcie_remove_irq_domain(pcie);\n \n"
  },
  {
    "path": "target/linux/generic/pending-5.15/850-0019-PCI-aardvark-Remove-irq_mask_ack-callback-for-INTx-i.patch",
    "content": "From 8c9eef96e24f34ff8b62b230700416b822691a37 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>\nDate: Thu, 1 Apr 2021 14:24:12 +0200\nSubject: [PATCH] PCI: aardvark: Remove irq_mask_ack callback for INTx\n interrupts\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nCallback for irq_mask_ack is the same as for irq_mask. As there is no\nspecial handling for irq_ack, there is no need to define irq_mask_ack too.\n\nSigned-off-by: Pali Rohár <pali@kernel.org>\nAcked-by: Marc Zyngier <maz@kernel.org>\nSigned-off-by: Marek Behún <kabel@kernel.org>\n---\n drivers/pci/controller/pci-aardvark.c | 1 -\n 1 file changed, 1 deletion(-)\n\n--- a/drivers/pci/controller/pci-aardvark.c\n+++ b/drivers/pci/controller/pci-aardvark.c\n@@ -1415,7 +1415,6 @@ static int advk_pcie_init_irq_domain(str\n \t}\n \n \tirq_chip->irq_mask = advk_pcie_irq_mask;\n-\tirq_chip->irq_mask_ack = advk_pcie_irq_mask;\n \tirq_chip->irq_unmask = advk_pcie_irq_unmask;\n \n \tpcie->irq_domain =\n"
  },
  {
    "path": "target/linux/generic/pending-5.15/850-0020-PCI-aardvark-Don-t-mask-irq-when-mapping.patch",
    "content": "From dc01fca5a9d9c09ce9a3fb2bc2e7715c37ff3bd9 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>\nDate: Thu, 1 Apr 2021 14:30:06 +0200\nSubject: [PATCH] PCI: aardvark: Don't mask irq when mapping\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nBy default, all Legacy INTx interrupts are masked, so there is no need to\nmask this interrupt during irq_map callback.\n\nSigned-off-by: Pali Rohár <pali@kernel.org>\nSigned-off-by: Marek Behún <kabel@kernel.org>\n---\n drivers/pci/controller/pci-aardvark.c | 1 -\n 1 file changed, 1 deletion(-)\n\n--- a/drivers/pci/controller/pci-aardvark.c\n+++ b/drivers/pci/controller/pci-aardvark.c\n@@ -1332,7 +1332,6 @@ static int advk_pcie_irq_map(struct irq_\n {\n \tstruct advk_pcie *pcie = h->host_data;\n \n-\tadvk_pcie_irq_mask(irq_get_irq_data(virq));\n \tirq_set_status_flags(virq, IRQ_LEVEL);\n \tirq_set_chip_and_handler(virq, &pcie->irq_chip,\n \t\t\t\t handle_level_irq);\n"
  },
  {
    "path": "target/linux/generic/pending-5.15/850-0021-PCI-aardvark-Drop-__maybe_unused-from-advk_pcie_disa.patch",
    "content": "From a511c99262ce19ee06908d27212b39ec4c5aeb17 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Marek=20Beh=C3=BAn?= <kabel@kernel.org>\nDate: Wed, 8 Dec 2021 04:40:29 +0100\nSubject: [PATCH] PCI: aardvark: Drop __maybe_unused from\n advk_pcie_disable_phy()\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nThis function is now always used in driver remove method, drop the\n__maybe_unused attribute.\n\nSigned-off-by: Marek Behún <kabel@kernel.org>\n---\n drivers/pci/controller/pci-aardvark.c | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/drivers/pci/controller/pci-aardvark.c\n+++ b/drivers/pci/controller/pci-aardvark.c\n@@ -1605,7 +1605,7 @@ static int advk_pcie_map_irq(const struc\n \t\treturn of_irq_parse_and_map_pci(dev, slot, pin);\n }\n \n-static void __maybe_unused advk_pcie_disable_phy(struct advk_pcie *pcie)\n+static void advk_pcie_disable_phy(struct advk_pcie *pcie)\n {\n \tphy_power_off(pcie->phy);\n \tphy_exit(pcie->phy);\n"
  },
  {
    "path": "target/linux/generic/pending-5.15/850-0022-PCI-aardvark-Update-comment-about-link-going-down-af.patch",
    "content": "From bafda858364003a70b9cda84282f9761587f8033 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Marek=20Beh=C3=BAn?= <kabel@kernel.org>\nDate: Mon, 10 Jan 2022 00:47:38 +0100\nSubject: [PATCH] PCI: aardvark: Update comment about link going down after\n link-up\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nUpdate the comment about what happens when link goes down after we have\nchecked for link-up. If a PIO request is done while link-down, we have\na serious problem.\n\nSigned-off-by: Marek Behún <kabel@kernel.org>\n---\n drivers/pci/controller/pci-aardvark.c | 8 ++++++--\n 1 file changed, 6 insertions(+), 2 deletions(-)\n\n--- a/drivers/pci/controller/pci-aardvark.c\n+++ b/drivers/pci/controller/pci-aardvark.c\n@@ -998,8 +998,12 @@ static bool advk_pcie_valid_device(struc\n \t\treturn false;\n \n \t/*\n-\t * If the link goes down after we check for link-up, nothing bad\n-\t * happens but the config access times out.\n+\t * If the link goes down after we check for link-up, we have a problem:\n+\t * if a PIO request is executed while link-down, the whole controller\n+\t * gets stuck in a non-functional state, and even after link comes up\n+\t * again, PIO requests won't work anymore, and a reset of the whole PCIe\n+\t * controller is needed. Therefore we need to prevent sending PIO\n+\t * requests while the link is down.\n \t */\n \tif (!pci_is_root_bus(bus) && !advk_pcie_link_up(pcie))\n \t\treturn false;\n"
  },
  {
    "path": "target/linux/generic/pending-5.15/850-0023-PCI-aardvark-Make-main-irq_chip-structure-a-static-d.patch",
    "content": "From 663b9f99bb35dbc0c7b685f71ee3668a60d31320 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Marek=20Beh=C3=BAn?= <kabel@kernel.org>\nDate: Mon, 10 Jan 2022 02:02:00 +0100\nSubject: [PATCH] PCI: aardvark: Make main irq_chip structure a static driver\n structure\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nMarc Zyngier says [1] that we should use struct irq_chip as a global\nstatic struct in the driver. Even though the structure currently\ncontains a dynamic member (parent_device), Marc says [2] that he plans\nto kill it and make the structure completely static.\n\nWe have already converted others irq_chip structures in this driver in\nthis way, but we omitted this one because the .name member is\ndynamically created from device's name, and the name is displayed in\nsysfs, so changing it would break sysfs ABI.\n\nThe rationale for changing the name (to \"advk-INT\") in spite of sysfs\nABI, and thus allowing to convert to a static structure, is that after\nthe other changes we made in this series, the IRQ chip is basically\nsomething different: it no logner generates ERR and PME interrupts (they\nare generated by emulated bridge's rp_irq_chip).\n\n[1] https://lore.kernel.org/linux-pci/877dbcvngf.wl-maz@kernel.org/\n[2] https://lore.kernel.org/linux-pci/874k6gvkhz.wl-maz@kernel.org/\n\nSigned-off-by: Marek Behún <kabel@kernel.org>\n---\n drivers/pci/controller/pci-aardvark.c | 25 +++++++------------------\n 1 file changed, 7 insertions(+), 18 deletions(-)\n\n--- a/drivers/pci/controller/pci-aardvark.c\n+++ b/drivers/pci/controller/pci-aardvark.c\n@@ -275,7 +275,6 @@ struct advk_pcie {\n \tint irq;\n \tstruct irq_domain *rp_irq_domain;\n \tstruct irq_domain *irq_domain;\n-\tstruct irq_chip irq_chip;\n \traw_spinlock_t irq_lock;\n \tstruct irq_domain *msi_domain;\n \tstruct irq_domain *msi_inner_domain;\n@@ -1331,14 +1330,19 @@ static void advk_pcie_irq_unmask(struct\n \traw_spin_unlock_irqrestore(&pcie->irq_lock, flags);\n }\n \n+static struct irq_chip advk_irq_chip = {\n+\t.name\t\t= \"advk-INT\",\n+\t.irq_mask\t= advk_pcie_irq_mask,\n+\t.irq_unmask\t= advk_pcie_irq_unmask,\n+};\n+\n static int advk_pcie_irq_map(struct irq_domain *h,\n \t\t\t     unsigned int virq, irq_hw_number_t hwirq)\n {\n \tstruct advk_pcie *pcie = h->host_data;\n \n \tirq_set_status_flags(virq, IRQ_LEVEL);\n-\tirq_set_chip_and_handler(virq, &pcie->irq_chip,\n-\t\t\t\t handle_level_irq);\n+\tirq_set_chip_and_handler(virq, &advk_irq_chip, handle_level_irq);\n \tirq_set_chip_data(virq, pcie);\n \n \treturn 0;\n@@ -1397,7 +1401,6 @@ static int advk_pcie_init_irq_domain(str\n \tstruct device *dev = &pcie->pdev->dev;\n \tstruct device_node *node = dev->of_node;\n \tstruct device_node *pcie_intc_node;\n-\tstruct irq_chip *irq_chip;\n \tint ret = 0;\n \n \traw_spin_lock_init(&pcie->irq_lock);\n@@ -1408,28 +1411,14 @@ static int advk_pcie_init_irq_domain(str\n \t\treturn -ENODEV;\n \t}\n \n-\tirq_chip = &pcie->irq_chip;\n-\n-\tirq_chip->name = devm_kasprintf(dev, GFP_KERNEL, \"%s-irq\",\n-\t\t\t\t\tdev_name(dev));\n-\tif (!irq_chip->name) {\n-\t\tret = -ENOMEM;\n-\t\tgoto out_put_node;\n-\t}\n-\n-\tirq_chip->irq_mask = advk_pcie_irq_mask;\n-\tirq_chip->irq_unmask = advk_pcie_irq_unmask;\n-\n \tpcie->irq_domain =\n \t\tirq_domain_add_linear(pcie_intc_node, PCI_NUM_INTX,\n \t\t\t\t      &advk_pcie_irq_domain_ops, pcie);\n \tif (!pcie->irq_domain) {\n \t\tdev_err(dev, \"Failed to get a INTx IRQ domain\\n\");\n \t\tret = -ENOMEM;\n-\t\tgoto out_put_node;\n \t}\n \n-out_put_node:\n \tof_node_put(pcie_intc_node);\n \treturn ret;\n }\n"
  },
  {
    "path": "target/linux/generic/pending-5.15/851-0001-phy-marvell-phy-mvebu-a3700-comphy-Remove-port-from-.patch",
    "content": "From a719f7ba7fcba05d85801c6f0267f389a21627c1 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>\nDate: Fri, 24 Sep 2021 13:03:02 +0200\nSubject: [PATCH] phy: marvell: phy-mvebu-a3700-comphy: Remove port from driver\n configuration\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nPort number is encoded into argument for SMC call. It is zero for SATA,\nPCIe and also both USB 3.0 PHYs. It is non-zero only for Ethernet PHY\n(incorrectly called SGMII) on lane 0. Ethernet PHY on lane 1 also uses zero\nport number.\n\nSo construct \"port\" bits for SMC call argument can be constructed directly\nfrom PHY type and lane number.\n\nChange driver code to always pass zero port number for non-ethernet PHYs\nand for ethernet PHYs determinate port number from lane number. This\nsimplifies the driver.\n\nAs port number from DT PHY configuration is not used anymore, remove whole\ndriver code which parses it. This also simplifies the driver.\n\nSigned-off-by: Pali Rohár <pali@kernel.org>\nSigned-off-by: Marek Behún <kabel@kernel.org>\nReviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>\n---\n drivers/phy/marvell/phy-mvebu-a3700-comphy.c | 62 +++++++++-----------\n 1 file changed, 29 insertions(+), 33 deletions(-)\n\n--- a/drivers/phy/marvell/phy-mvebu-a3700-comphy.c\n+++ b/drivers/phy/marvell/phy-mvebu-a3700-comphy.c\n@@ -20,7 +20,6 @@\n #include <linux/platform_device.h>\n \n #define MVEBU_A3700_COMPHY_LANES\t\t3\n-#define MVEBU_A3700_COMPHY_PORTS\t\t2\n \n /* COMPHY Fast SMC function identifiers */\n #define COMPHY_SIP_POWER_ON\t\t\t0x82000001\n@@ -45,51 +44,47 @@\n #define COMPHY_FW_NET(mode, idx, speed)\t\t(COMPHY_FW_MODE(mode) | \\\n \t\t\t\t\t\t ((idx) << 8) |\t\\\n \t\t\t\t\t\t ((speed) << 2))\n-#define COMPHY_FW_PCIE(mode, idx, speed, width)\t(COMPHY_FW_NET(mode, idx, speed) | \\\n+#define COMPHY_FW_PCIE(mode, speed, width)\t(COMPHY_FW_NET(mode, 0, speed) | \\\n \t\t\t\t\t\t ((width) << 18))\n \n struct mvebu_a3700_comphy_conf {\n \tunsigned int lane;\n \tenum phy_mode mode;\n \tint submode;\n-\tunsigned int port;\n \tu32 fw_mode;\n };\n \n-#define MVEBU_A3700_COMPHY_CONF(_lane, _mode, _smode, _port, _fw)\t\\\n+#define MVEBU_A3700_COMPHY_CONF(_lane, _mode, _smode, _fw)\t\t\\\n \t{\t\t\t\t\t\t\t\t\\\n \t\t.lane = _lane,\t\t\t\t\t\t\\\n \t\t.mode = _mode,\t\t\t\t\t\t\\\n \t\t.submode = _smode,\t\t\t\t\t\\\n-\t\t.port = _port,\t\t\t\t\t\t\\\n \t\t.fw_mode = _fw,\t\t\t\t\t\t\\\n \t}\n \n-#define MVEBU_A3700_COMPHY_CONF_GEN(_lane, _mode, _port, _fw) \\\n-\tMVEBU_A3700_COMPHY_CONF(_lane, _mode, PHY_INTERFACE_MODE_NA, _port, _fw)\n+#define MVEBU_A3700_COMPHY_CONF_GEN(_lane, _mode, _fw) \\\n+\tMVEBU_A3700_COMPHY_CONF(_lane, _mode, PHY_INTERFACE_MODE_NA, _fw)\n \n-#define MVEBU_A3700_COMPHY_CONF_ETH(_lane, _smode, _port, _fw) \\\n-\tMVEBU_A3700_COMPHY_CONF(_lane, PHY_MODE_ETHERNET, _smode, _port, _fw)\n+#define MVEBU_A3700_COMPHY_CONF_ETH(_lane, _smode, _fw) \\\n+\tMVEBU_A3700_COMPHY_CONF(_lane, PHY_MODE_ETHERNET, _smode, _fw)\n \n static const struct mvebu_a3700_comphy_conf mvebu_a3700_comphy_modes[] = {\n \t/* lane 0 */\n-\tMVEBU_A3700_COMPHY_CONF_GEN(0, PHY_MODE_USB_HOST_SS, 0,\n+\tMVEBU_A3700_COMPHY_CONF_GEN(0, PHY_MODE_USB_HOST_SS,\n \t\t\t\t    COMPHY_FW_MODE_USB3H),\n-\tMVEBU_A3700_COMPHY_CONF_ETH(0, PHY_INTERFACE_MODE_SGMII, 1,\n+\tMVEBU_A3700_COMPHY_CONF_ETH(0, PHY_INTERFACE_MODE_SGMII,\n \t\t\t\t    COMPHY_FW_MODE_SGMII),\n-\tMVEBU_A3700_COMPHY_CONF_ETH(0, PHY_INTERFACE_MODE_2500BASEX, 1,\n+\tMVEBU_A3700_COMPHY_CONF_ETH(0, PHY_INTERFACE_MODE_2500BASEX,\n \t\t\t\t    COMPHY_FW_MODE_2500BASEX),\n \t/* lane 1 */\n-\tMVEBU_A3700_COMPHY_CONF_GEN(1, PHY_MODE_PCIE, 0,\n-\t\t\t\t    COMPHY_FW_MODE_PCIE),\n-\tMVEBU_A3700_COMPHY_CONF_ETH(1, PHY_INTERFACE_MODE_SGMII, 0,\n+\tMVEBU_A3700_COMPHY_CONF_GEN(1, PHY_MODE_PCIE, COMPHY_FW_MODE_PCIE),\n+\tMVEBU_A3700_COMPHY_CONF_ETH(1, PHY_INTERFACE_MODE_SGMII,\n \t\t\t\t    COMPHY_FW_MODE_SGMII),\n-\tMVEBU_A3700_COMPHY_CONF_ETH(1, PHY_INTERFACE_MODE_2500BASEX, 0,\n+\tMVEBU_A3700_COMPHY_CONF_ETH(1, PHY_INTERFACE_MODE_2500BASEX,\n \t\t\t\t    COMPHY_FW_MODE_2500BASEX),\n \t/* lane 2 */\n-\tMVEBU_A3700_COMPHY_CONF_GEN(2, PHY_MODE_SATA, 0,\n-\t\t\t\t    COMPHY_FW_MODE_SATA),\n-\tMVEBU_A3700_COMPHY_CONF_GEN(2, PHY_MODE_USB_HOST_SS, 0,\n+\tMVEBU_A3700_COMPHY_CONF_GEN(2, PHY_MODE_SATA, COMPHY_FW_MODE_SATA),\n+\tMVEBU_A3700_COMPHY_CONF_GEN(2, PHY_MODE_USB_HOST_SS,\n \t\t\t\t    COMPHY_FW_MODE_USB3H),\n };\n \n@@ -98,7 +93,6 @@ struct mvebu_a3700_comphy_lane {\n \tunsigned int id;\n \tenum phy_mode mode;\n \tint submode;\n-\tint port;\n };\n \n static int mvebu_a3700_comphy_smc(unsigned long function, unsigned long lane,\n@@ -120,7 +114,7 @@ static int mvebu_a3700_comphy_smc(unsign\n \t}\n }\n \n-static int mvebu_a3700_comphy_get_fw_mode(int lane, int port,\n+static int mvebu_a3700_comphy_get_fw_mode(int lane,\n \t\t\t\t\t  enum phy_mode mode,\n \t\t\t\t\t  int submode)\n {\n@@ -132,7 +126,6 @@ static int mvebu_a3700_comphy_get_fw_mod\n \n \tfor (i = 0; i < n; i++) {\n \t\tif (mvebu_a3700_comphy_modes[i].lane == lane &&\n-\t\t    mvebu_a3700_comphy_modes[i].port == port &&\n \t\t    mvebu_a3700_comphy_modes[i].mode == mode &&\n \t\t    mvebu_a3700_comphy_modes[i].submode == submode)\n \t\t\tbreak;\n@@ -153,7 +146,7 @@ static int mvebu_a3700_comphy_set_mode(s\n \tif (submode == PHY_INTERFACE_MODE_1000BASEX)\n \t\tsubmode = PHY_INTERFACE_MODE_SGMII;\n \n-\tfw_mode = mvebu_a3700_comphy_get_fw_mode(lane->id, lane->port, mode,\n+\tfw_mode = mvebu_a3700_comphy_get_fw_mode(lane->id, mode,\n \t\t\t\t\t\t submode);\n \tif (fw_mode < 0) {\n \t\tdev_err(lane->dev, \"invalid COMPHY mode\\n\");\n@@ -172,9 +165,10 @@ static int mvebu_a3700_comphy_power_on(s\n \tstruct mvebu_a3700_comphy_lane *lane = phy_get_drvdata(phy);\n \tu32 fw_param;\n \tint fw_mode;\n+\tint fw_port;\n \tint ret;\n \n-\tfw_mode = mvebu_a3700_comphy_get_fw_mode(lane->id, lane->port,\n+\tfw_mode = mvebu_a3700_comphy_get_fw_mode(lane->id,\n \t\t\t\t\t\t lane->mode, lane->submode);\n \tif (fw_mode < 0) {\n \t\tdev_err(lane->dev, \"invalid COMPHY mode\\n\");\n@@ -191,17 +185,18 @@ static int mvebu_a3700_comphy_power_on(s\n \t\tfw_param = COMPHY_FW_MODE(fw_mode);\n \t\tbreak;\n \tcase PHY_MODE_ETHERNET:\n+\t\tfw_port = (lane->id == 0) ? 1 : 0;\n \t\tswitch (lane->submode) {\n \t\tcase PHY_INTERFACE_MODE_SGMII:\n \t\t\tdev_dbg(lane->dev, \"set lane %d to SGMII mode\\n\",\n \t\t\t\tlane->id);\n-\t\t\tfw_param = COMPHY_FW_NET(fw_mode, lane->port,\n+\t\t\tfw_param = COMPHY_FW_NET(fw_mode, fw_port,\n \t\t\t\t\t\t COMPHY_FW_SPEED_1_25G);\n \t\t\tbreak;\n \t\tcase PHY_INTERFACE_MODE_2500BASEX:\n \t\t\tdev_dbg(lane->dev, \"set lane %d to 2500BASEX mode\\n\",\n \t\t\t\tlane->id);\n-\t\t\tfw_param = COMPHY_FW_NET(fw_mode, lane->port,\n+\t\t\tfw_param = COMPHY_FW_NET(fw_mode, fw_port,\n \t\t\t\t\t\t COMPHY_FW_SPEED_3_125G);\n \t\t\tbreak;\n \t\tdefault:\n@@ -212,8 +207,7 @@ static int mvebu_a3700_comphy_power_on(s\n \t\tbreak;\n \tcase PHY_MODE_PCIE:\n \t\tdev_dbg(lane->dev, \"set lane %d to PCIe mode\\n\", lane->id);\n-\t\tfw_param = COMPHY_FW_PCIE(fw_mode, lane->port,\n-\t\t\t\t\t  COMPHY_FW_SPEED_5G,\n+\t\tfw_param = COMPHY_FW_PCIE(fw_mode, COMPHY_FW_SPEED_5G,\n \t\t\t\t\t  phy->attrs.bus_width);\n \t\tbreak;\n \tdefault:\n@@ -247,17 +241,20 @@ static struct phy *mvebu_a3700_comphy_xl\n \t\t\t\t\t    struct of_phandle_args *args)\n {\n \tstruct mvebu_a3700_comphy_lane *lane;\n+\tunsigned int port;\n \tstruct phy *phy;\n \n-\tif (WARN_ON(args->args[0] >= MVEBU_A3700_COMPHY_PORTS))\n-\t\treturn ERR_PTR(-EINVAL);\n-\n \tphy = of_phy_simple_xlate(dev, args);\n \tif (IS_ERR(phy))\n \t\treturn phy;\n \n \tlane = phy_get_drvdata(phy);\n-\tlane->port = args->args[0];\n+\n+\tport = args->args[0];\n+\tif (port != 0 && (port != 1 || lane->id != 0)) {\n+\t\tdev_err(lane->dev, \"invalid port number %u\\n\", port);\n+\t\treturn ERR_PTR(-EINVAL);\n+\t}\n \n \treturn phy;\n }\n@@ -302,7 +299,6 @@ static int mvebu_a3700_comphy_probe(stru\n \t\tlane->mode = PHY_MODE_INVALID;\n \t\tlane->submode = PHY_INTERFACE_MODE_NA;\n \t\tlane->id = lane_id;\n-\t\tlane->port = -1;\n \t\tphy_set_drvdata(phy, lane);\n \t}\n \n"
  },
  {
    "path": "target/linux/generic/pending-5.15/851-0002-phy-marvell-phy-mvebu-a3700-comphy-Add-native-kernel.patch",
    "content": "From 9d276da259cce20b2ed7a868b6e6a6a205f7bb04 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>\nDate: Thu, 23 Sep 2021 19:20:13 +0200\nSubject: [PATCH] phy: marvell: phy-mvebu-a3700-comphy: Add native kernel\n implementation\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nRemove old RPC implementation and add a new native kernel implementation.\n\nThe old implementation uses ARM SMC API to issue RPC calls to ARM Trusted\nFirmware which provides real implementation of PHY configuration.\n\nBut older versions of ARM Trusted Firmware do not provide this PHY\nconfiguration functionality, simply returning: operation not supported; or\nworse, some versions provide the configuration functionality incorrectly.\n\nFor example the firmware shipped in ESPRESSObin board has this older\nversion of ARM Trusted Firmware and therefore SATA, USB 3.0 and PCIe\nfunctionality do not work with newer versions of Linux kernel.\n\nDue to the above reasons, the following commits were introduced into Linux,\nto workaround these issues by ignoring -EOPNOTSUPP error code from\nphy-mvebu-a3700-comphy driver function phy_power_on():\n\ncommit 45aefe3d2251 (\"ata: ahci: mvebu: Make SATA PHY optional for Armada\n3720\")\ncommit 3241929b67d2 (\"usb: host: xhci: mvebu: make USB 3.0 PHY optional for\nArmada 3720\")\ncommit b0c6ae0f8948 (\"PCI: aardvark: Fix initialization with old Marvell's\nArm Trusted Firmware\")\n\nReplace this RPC implementation with proper native kernel implementation,\nwhich is independent on the firmware. Never return -EOPNOTSUPP for proper\narguments.\n\nThis should solve multiple issues with real-world boards, where it is not\npossible or really inconvenient to change the firmware. Let's eliminate\nthese issues.\n\nThis implementation is ported directly from Armada 3720 comphy driver found\nin newest version of ARM Trusted Firmware source code, but with various\nfixes of register names, some added comments, some refactoring due to the\noriginal code not conforming to kernel standards. Also PCIe mode poweroff\nsupport was added here, and PHY reset support. These changes are also going\nto be sent to ARM Trusted Firmware.\n\nSigned-off-by: Pali Rohár <pali@kernel.org>\nAcked-by: Miquel Raynal <miquel.raynal@bootlin.com>\n[ Pali did the porting from ATF.\n  I (Marek) then fixed some register names, some various other things,\n  added some comments and refactored the code to kernel standards. Also\n  fixed PHY poweroff and added PHY reset. ]\nSigned-off-by: Marek Behún <kabel@kernel.org>\n---\n drivers/phy/marvell/phy-mvebu-a3700-comphy.c | 1351 ++++++++++++++++--\n 1 file changed, 1234 insertions(+), 117 deletions(-)\n\n--- a/drivers/phy/marvell/phy-mvebu-a3700-comphy.c\n+++ b/drivers/phy/marvell/phy-mvebu-a3700-comphy.c\n@@ -5,12 +5,16 @@\n  * Authors:\n  *   Evan Wang <xswang@marvell.com>\n  *   Miquèl Raynal <miquel.raynal@bootlin.com>\n+ *   Pali Rohár <pali@kernel.org>\n+ *   Marek Behún <kabel@kernel.org>\n  *\n  * Structure inspired from phy-mvebu-cp110-comphy.c written by Antoine Tenart.\n- * SMC call initial support done by Grzegorz Jaszczyk.\n+ * Comphy code from ARM Trusted Firmware ported by Pali Rohár <pali@kernel.org>\n+ * and Marek Behún <kabel@kernel.org>.\n  */\n \n-#include <linux/arm-smccc.h>\n+#include <linux/bitfield.h>\n+#include <linux/clk.h>\n #include <linux/io.h>\n #include <linux/iopoll.h>\n #include <linux/mfd/syscon.h>\n@@ -18,103 +22,1147 @@\n #include <linux/phy.h>\n #include <linux/phy/phy.h>\n #include <linux/platform_device.h>\n+#include <linux/spinlock.h>\n \n-#define MVEBU_A3700_COMPHY_LANES\t\t3\n+#define PLL_SET_DELAY_US\t\t600\n+#define COMPHY_PLL_SLEEP\t\t1000\n+#define COMPHY_PLL_TIMEOUT\t\t150000\n+\n+/* Comphy lane2 indirect access register offset */\n+#define COMPHY_LANE2_INDIR_ADDR\t\t0x0\n+#define COMPHY_LANE2_INDIR_DATA\t\t0x4\n+\n+/* SATA and USB3 PHY offset compared to SATA PHY */\n+#define COMPHY_LANE2_REGS_BASE\t\t0x200\n+\n+/*\n+ * When accessing common PHY lane registers directly, we need to shift by 1,\n+ * since the registers are 16-bit.\n+ */\n+#define COMPHY_LANE_REG_DIRECT(reg)\t(((reg) & 0x7FF) << 1)\n+\n+/* COMPHY registers */\n+#define COMPHY_POWER_PLL_CTRL\t\t0x01\n+#define PU_IVREF_BIT\t\t\tBIT(15)\n+#define PU_PLL_BIT\t\t\tBIT(14)\n+#define PU_RX_BIT\t\t\tBIT(13)\n+#define PU_TX_BIT\t\t\tBIT(12)\n+#define PU_TX_INTP_BIT\t\t\tBIT(11)\n+#define PU_DFE_BIT\t\t\tBIT(10)\n+#define RESET_DTL_RX_BIT\t\tBIT(9)\n+#define PLL_LOCK_BIT\t\t\tBIT(8)\n+#define REF_FREF_SEL_MASK\t\tGENMASK(4, 0)\n+#define REF_FREF_SEL_SERDES_25MHZ\tFIELD_PREP(REF_FREF_SEL_MASK, 0x1)\n+#define REF_FREF_SEL_SERDES_40MHZ\tFIELD_PREP(REF_FREF_SEL_MASK, 0x3)\n+#define REF_FREF_SEL_SERDES_50MHZ\tFIELD_PREP(REF_FREF_SEL_MASK, 0x4)\n+#define REF_FREF_SEL_PCIE_USB3_25MHZ\tFIELD_PREP(REF_FREF_SEL_MASK, 0x2)\n+#define REF_FREF_SEL_PCIE_USB3_40MHZ\tFIELD_PREP(REF_FREF_SEL_MASK, 0x3)\n+#define COMPHY_MODE_MASK\t\tGENMASK(7, 5)\n+#define COMPHY_MODE_SATA\t\tFIELD_PREP(COMPHY_MODE_MASK, 0x0)\n+#define COMPHY_MODE_PCIE\t\tFIELD_PREP(COMPHY_MODE_MASK, 0x3)\n+#define COMPHY_MODE_SERDES\t\tFIELD_PREP(COMPHY_MODE_MASK, 0x4)\n+#define COMPHY_MODE_USB3\t\tFIELD_PREP(COMPHY_MODE_MASK, 0x5)\n+\n+#define COMPHY_KVCO_CAL_CTRL\t\t0x02\n+#define USE_MAX_PLL_RATE_BIT\t\tBIT(12)\n+#define SPEED_PLL_MASK\t\t\tGENMASK(7, 2)\n+#define SPEED_PLL_VALUE_16\t\tFIELD_PREP(SPEED_PLL_MASK, 0x10)\n+\n+#define COMPHY_DIG_LOOPBACK_EN\t\t0x23\n+#define SEL_DATA_WIDTH_MASK\t\tGENMASK(11, 10)\n+#define DATA_WIDTH_10BIT\t\tFIELD_PREP(SEL_DATA_WIDTH_MASK, 0x0)\n+#define DATA_WIDTH_20BIT\t\tFIELD_PREP(SEL_DATA_WIDTH_MASK, 0x1)\n+#define DATA_WIDTH_40BIT\t\tFIELD_PREP(SEL_DATA_WIDTH_MASK, 0x2)\n+#define PLL_READY_TX_BIT\t\tBIT(4)\n+\n+#define COMPHY_SYNC_PATTERN\t\t0x24\n+#define TXD_INVERT_BIT\t\t\tBIT(10)\n+#define RXD_INVERT_BIT\t\t\tBIT(11)\n+\n+#define COMPHY_SYNC_MASK_GEN\t\t0x25\n+#define PHY_GEN_MAX_MASK\t\tGENMASK(11, 10)\n+#define PHY_GEN_MAX_USB3_5G\t\tFIELD_PREP(PHY_GEN_MAX_MASK, 0x1)\n+\n+#define COMPHY_ISOLATION_CTRL\t\t0x26\n+#define PHY_ISOLATE_MODE\t\tBIT(15)\n+\n+#define COMPHY_GEN2_SET2\t\t0x3e\n+#define GS2_TX_SSC_AMP_MASK\t\tGENMASK(15, 9)\n+#define GS2_TX_SSC_AMP_4128\t\tFIELD_PREP(GS2_TX_SSC_AMP_MASK, 0x20)\n+#define GS2_VREG_RXTX_MAS_ISET_MASK\tGENMASK(8, 7)\n+#define GS2_VREG_RXTX_MAS_ISET_60U\tFIELD_PREP(GS2_VREG_RXTX_MAS_ISET_MASK,\\\n+\t\t\t\t\t\t   0x0)\n+#define GS2_VREG_RXTX_MAS_ISET_80U\tFIELD_PREP(GS2_VREG_RXTX_MAS_ISET_MASK,\\\n+\t\t\t\t\t\t   0x1)\n+#define GS2_VREG_RXTX_MAS_ISET_100U\tFIELD_PREP(GS2_VREG_RXTX_MAS_ISET_MASK,\\\n+\t\t\t\t\t\t   0x2)\n+#define GS2_VREG_RXTX_MAS_ISET_120U\tFIELD_PREP(GS2_VREG_RXTX_MAS_ISET_MASK,\\\n+\t\t\t\t\t\t   0x3)\n+#define GS2_RSVD_6_0_MASK\t\tGENMASK(6, 0)\n+\n+#define COMPHY_GEN3_SET2\t\t0x3f\n+\n+#define COMPHY_IDLE_SYNC_EN\t\t0x48\n+#define IDLE_SYNC_EN\t\t\tBIT(12)\n+\n+#define COMPHY_MISC_CTRL0\t\t0x4F\n+#define CLK100M_125M_EN\t\t\tBIT(4)\n+#define TXDCLK_2X_SEL\t\t\tBIT(6)\n+#define CLK500M_EN\t\t\tBIT(7)\n+#define PHY_REF_CLK_SEL\t\t\tBIT(10)\n+\n+#define COMPHY_SFT_RESET\t\t0x52\n+#define SFT_RST\t\t\t\tBIT(9)\n+#define SFT_RST_NO_REG\t\t\tBIT(10)\n+\n+#define COMPHY_MISC_CTRL1\t\t0x73\n+#define SEL_BITS_PCIE_FORCE\t\tBIT(15)\n+\n+#define COMPHY_GEN2_SET3\t\t0x112\n+#define GS3_FFE_CAP_SEL_MASK\t\tGENMASK(3, 0)\n+#define GS3_FFE_CAP_SEL_VALUE\t\tFIELD_PREP(GS3_FFE_CAP_SEL_MASK, 0xF)\n+\n+/* PIPE registers */\n+#define COMPHY_PIPE_LANE_CFG0\t\t0x180\n+#define PRD_TXDEEMPH0_MASK\t\tBIT(0)\n+#define PRD_TXMARGIN_MASK\t\tGENMASK(3, 1)\n+#define PRD_TXSWING_MASK\t\tBIT(4)\n+#define CFG_TX_ALIGN_POS_MASK\t\tGENMASK(8, 5)\n+\n+#define COMPHY_PIPE_LANE_CFG1\t\t0x181\n+#define PRD_TXDEEMPH1_MASK\t\tBIT(15)\n+#define USE_MAX_PLL_RATE_EN\t\tBIT(9)\n+#define TX_DET_RX_MODE\t\t\tBIT(6)\n+#define GEN2_TX_DATA_DLY_MASK\t\tGENMASK(4, 3)\n+#define GEN2_TX_DATA_DLY_DEFT\t\tFIELD_PREP(GEN2_TX_DATA_DLY_MASK, 2)\n+#define TX_ELEC_IDLE_MODE_EN\t\tBIT(0)\n+\n+#define COMPHY_PIPE_LANE_STAT1\t\t0x183\n+#define TXDCLK_PCLK_EN\t\t\tBIT(0)\n+\n+#define COMPHY_PIPE_LANE_CFG4\t\t0x188\n+#define SPREAD_SPECTRUM_CLK_EN\t\tBIT(7)\n+\n+#define COMPHY_PIPE_RST_CLK_CTRL\t0x1C1\n+#define PIPE_SOFT_RESET\t\t\tBIT(0)\n+#define PIPE_REG_RESET\t\t\tBIT(1)\n+#define MODE_CORE_CLK_FREQ_SEL\t\tBIT(9)\n+#define MODE_PIPE_WIDTH_32\t\tBIT(3)\n+#define MODE_REFDIV_MASK\t\tGENMASK(5, 4)\n+#define MODE_REFDIV_BY_4\t\tFIELD_PREP(MODE_REFDIV_MASK, 0x2)\n+\n+#define COMPHY_PIPE_TEST_MODE_CTRL\t0x1C2\n+#define MODE_MARGIN_OVERRIDE\t\tBIT(2)\n+\n+#define COMPHY_PIPE_CLK_SRC_LO\t\t0x1C3\n+#define MODE_CLK_SRC\t\t\tBIT(0)\n+#define BUNDLE_PERIOD_SEL\t\tBIT(1)\n+#define BUNDLE_PERIOD_SCALE_MASK\tGENMASK(3, 2)\n+#define BUNDLE_SAMPLE_CTRL\t\tBIT(4)\n+#define PLL_READY_DLY_MASK\t\tGENMASK(7, 5)\n+#define CFG_SEL_20B\t\t\tBIT(15)\n+\n+#define COMPHY_PIPE_PWR_MGM_TIM1\t0x1D0\n+#define CFG_PM_OSCCLK_WAIT_MASK\t\tGENMASK(15, 12)\n+#define CFG_PM_RXDEN_WAIT_MASK\t\tGENMASK(11, 8)\n+#define CFG_PM_RXDEN_WAIT_1_UNIT\tFIELD_PREP(CFG_PM_RXDEN_WAIT_MASK, 0x1)\n+#define CFG_PM_RXDLOZ_WAIT_MASK\t\tGENMASK(7, 0)\n+#define CFG_PM_RXDLOZ_WAIT_7_UNIT\tFIELD_PREP(CFG_PM_RXDLOZ_WAIT_MASK, 0x7)\n+#define CFG_PM_RXDLOZ_WAIT_12_UNIT\tFIELD_PREP(CFG_PM_RXDLOZ_WAIT_MASK, 0xC)\n+\n+/*\n+ * This register is not from PHY lane register space. It only exists in the\n+ * indirect register space, before the actual PHY lane 2 registers. So the\n+ * offset is absolute, not relative to COMPHY_LANE2_REGS_BASE.\n+ * It is used only for SATA PHY initialization.\n+ */\n+#define COMPHY_RESERVED_REG\t\t0x0E\n+#define PHYCTRL_FRM_PIN_BIT\t\tBIT(13)\n \n-/* COMPHY Fast SMC function identifiers */\n-#define COMPHY_SIP_POWER_ON\t\t\t0x82000001\n-#define COMPHY_SIP_POWER_OFF\t\t\t0x82000002\n-#define COMPHY_SIP_PLL_LOCK\t\t\t0x82000003\n-\n-#define COMPHY_FW_MODE_SATA\t\t\t0x1\n-#define COMPHY_FW_MODE_SGMII\t\t\t0x2\n-#define COMPHY_FW_MODE_2500BASEX\t\t0x3\n-#define COMPHY_FW_MODE_USB3H\t\t\t0x4\n-#define COMPHY_FW_MODE_USB3D\t\t\t0x5\n-#define COMPHY_FW_MODE_PCIE\t\t\t0x6\n-#define COMPHY_FW_MODE_USB3\t\t\t0xa\n-\n-#define COMPHY_FW_SPEED_1_25G\t\t\t0 /* SGMII 1G */\n-#define COMPHY_FW_SPEED_2_5G\t\t\t1\n-#define COMPHY_FW_SPEED_3_125G\t\t\t2 /* 2500BASE-X */\n-#define COMPHY_FW_SPEED_5G\t\t\t3\n-#define COMPHY_FW_SPEED_MAX\t\t\t0x3F\n-\n-#define COMPHY_FW_MODE(mode)\t\t\t((mode) << 12)\n-#define COMPHY_FW_NET(mode, idx, speed)\t\t(COMPHY_FW_MODE(mode) | \\\n-\t\t\t\t\t\t ((idx) << 8) |\t\\\n-\t\t\t\t\t\t ((speed) << 2))\n-#define COMPHY_FW_PCIE(mode, speed, width)\t(COMPHY_FW_NET(mode, 0, speed) | \\\n-\t\t\t\t\t\t ((width) << 18))\n+/* South Bridge PHY Configuration Registers */\n+#define COMPHY_PHY_REG(lane, reg)\t(((1 - (lane)) * 0x28) + ((reg) & 0x3f))\n+\n+/*\n+ * lane0: USB3/GbE1 PHY Configuration 1\n+ * lane1: PCIe/GbE0 PHY Configuration 1\n+ * (used only by SGMII code)\n+ */\n+#define COMPHY_PHY_CFG1\t\t\t0x0\n+#define PIN_PU_IVREF_BIT\t\tBIT(1)\n+#define PIN_RESET_CORE_BIT\t\tBIT(11)\n+#define PIN_RESET_COMPHY_BIT\t\tBIT(12)\n+#define PIN_PU_PLL_BIT\t\t\tBIT(16)\n+#define PIN_PU_RX_BIT\t\t\tBIT(17)\n+#define PIN_PU_TX_BIT\t\t\tBIT(18)\n+#define PIN_TX_IDLE_BIT\t\t\tBIT(19)\n+#define GEN_RX_SEL_MASK\t\t\tGENMASK(25, 22)\n+#define GEN_RX_SEL_VALUE(val)\t\tFIELD_PREP(GEN_RX_SEL_MASK, (val))\n+#define GEN_TX_SEL_MASK\t\t\tGENMASK(29, 26)\n+#define GEN_TX_SEL_VALUE(val)\t\tFIELD_PREP(GEN_TX_SEL_MASK, (val))\n+#define SERDES_SPEED_1_25_G\t\t0x6\n+#define SERDES_SPEED_3_125_G\t\t0x8\n+#define PHY_RX_INIT_BIT\t\t\tBIT(30)\n+\n+/*\n+ * lane0: USB3/GbE1 PHY Status 1\n+ * lane1: PCIe/GbE0 PHY Status 1\n+ * (used only by SGMII code)\n+ */\n+#define COMPHY_PHY_STAT1\t\t0x18\n+#define PHY_RX_INIT_DONE_BIT\t\tBIT(0)\n+#define PHY_PLL_READY_RX_BIT\t\tBIT(2)\n+#define PHY_PLL_READY_TX_BIT\t\tBIT(3)\n+\n+/* PHY Selector */\n+#define COMPHY_SELECTOR_PHY_REG\t\t\t0xFC\n+/* bit0: 0: Lane1 is GbE0; 1: Lane1 is PCIe */\n+#define COMPHY_SELECTOR_PCIE_GBE0_SEL_BIT\tBIT(0)\n+/* bit4: 0: Lane0 is GbE1; 1: Lane0 is USB3 */\n+#define COMPHY_SELECTOR_USB3_GBE1_SEL_BIT\tBIT(4)\n+/* bit8: 0: Lane0 is USB3 instead of GbE1, Lane2 is SATA; 1: Lane2 is USB3 */\n+#define COMPHY_SELECTOR_USB3_PHY_SEL_BIT\tBIT(8)\n \n struct mvebu_a3700_comphy_conf {\n \tunsigned int lane;\n \tenum phy_mode mode;\n \tint submode;\n-\tu32 fw_mode;\n };\n \n-#define MVEBU_A3700_COMPHY_CONF(_lane, _mode, _smode, _fw)\t\t\\\n+#define MVEBU_A3700_COMPHY_CONF(_lane, _mode, _smode)\t\t\t\\\n \t{\t\t\t\t\t\t\t\t\\\n \t\t.lane = _lane,\t\t\t\t\t\t\\\n \t\t.mode = _mode,\t\t\t\t\t\t\\\n \t\t.submode = _smode,\t\t\t\t\t\\\n-\t\t.fw_mode = _fw,\t\t\t\t\t\t\\\n \t}\n \n-#define MVEBU_A3700_COMPHY_CONF_GEN(_lane, _mode, _fw) \\\n-\tMVEBU_A3700_COMPHY_CONF(_lane, _mode, PHY_INTERFACE_MODE_NA, _fw)\n+#define MVEBU_A3700_COMPHY_CONF_GEN(_lane, _mode) \\\n+\tMVEBU_A3700_COMPHY_CONF(_lane, _mode, PHY_INTERFACE_MODE_NA)\n \n-#define MVEBU_A3700_COMPHY_CONF_ETH(_lane, _smode, _fw) \\\n-\tMVEBU_A3700_COMPHY_CONF(_lane, PHY_MODE_ETHERNET, _smode, _fw)\n+#define MVEBU_A3700_COMPHY_CONF_ETH(_lane, _smode) \\\n+\tMVEBU_A3700_COMPHY_CONF(_lane, PHY_MODE_ETHERNET, _smode)\n \n static const struct mvebu_a3700_comphy_conf mvebu_a3700_comphy_modes[] = {\n \t/* lane 0 */\n-\tMVEBU_A3700_COMPHY_CONF_GEN(0, PHY_MODE_USB_HOST_SS,\n-\t\t\t\t    COMPHY_FW_MODE_USB3H),\n-\tMVEBU_A3700_COMPHY_CONF_ETH(0, PHY_INTERFACE_MODE_SGMII,\n-\t\t\t\t    COMPHY_FW_MODE_SGMII),\n-\tMVEBU_A3700_COMPHY_CONF_ETH(0, PHY_INTERFACE_MODE_2500BASEX,\n-\t\t\t\t    COMPHY_FW_MODE_2500BASEX),\n+\tMVEBU_A3700_COMPHY_CONF_GEN(0, PHY_MODE_USB_HOST_SS),\n+\tMVEBU_A3700_COMPHY_CONF_ETH(0, PHY_INTERFACE_MODE_SGMII),\n+\tMVEBU_A3700_COMPHY_CONF_ETH(0, PHY_INTERFACE_MODE_1000BASEX),\n+\tMVEBU_A3700_COMPHY_CONF_ETH(0, PHY_INTERFACE_MODE_2500BASEX),\n \t/* lane 1 */\n-\tMVEBU_A3700_COMPHY_CONF_GEN(1, PHY_MODE_PCIE, COMPHY_FW_MODE_PCIE),\n-\tMVEBU_A3700_COMPHY_CONF_ETH(1, PHY_INTERFACE_MODE_SGMII,\n-\t\t\t\t    COMPHY_FW_MODE_SGMII),\n-\tMVEBU_A3700_COMPHY_CONF_ETH(1, PHY_INTERFACE_MODE_2500BASEX,\n-\t\t\t\t    COMPHY_FW_MODE_2500BASEX),\n+\tMVEBU_A3700_COMPHY_CONF_GEN(1, PHY_MODE_PCIE),\n+\tMVEBU_A3700_COMPHY_CONF_ETH(1, PHY_INTERFACE_MODE_SGMII),\n+\tMVEBU_A3700_COMPHY_CONF_ETH(1, PHY_INTERFACE_MODE_1000BASEX),\n+\tMVEBU_A3700_COMPHY_CONF_ETH(1, PHY_INTERFACE_MODE_2500BASEX),\n \t/* lane 2 */\n-\tMVEBU_A3700_COMPHY_CONF_GEN(2, PHY_MODE_SATA, COMPHY_FW_MODE_SATA),\n-\tMVEBU_A3700_COMPHY_CONF_GEN(2, PHY_MODE_USB_HOST_SS,\n-\t\t\t\t    COMPHY_FW_MODE_USB3H),\n+\tMVEBU_A3700_COMPHY_CONF_GEN(2, PHY_MODE_SATA),\n+\tMVEBU_A3700_COMPHY_CONF_GEN(2, PHY_MODE_USB_HOST_SS),\n+};\n+\n+struct mvebu_a3700_comphy_priv {\n+\tvoid __iomem *comphy_regs;\n+\tvoid __iomem *lane0_phy_regs; /* USB3 and GbE1 */\n+\tvoid __iomem *lane1_phy_regs; /* PCIe and GbE0 */\n+\tvoid __iomem *lane2_phy_indirect; /* SATA and USB3 */\n+\tspinlock_t lock; /* for PHY selector access */\n+\tbool xtal_is_40m;\n };\n \n struct mvebu_a3700_comphy_lane {\n+\tstruct mvebu_a3700_comphy_priv *priv;\n \tstruct device *dev;\n \tunsigned int id;\n \tenum phy_mode mode;\n \tint submode;\n+\tbool invert_tx;\n+\tbool invert_rx;\n+\tbool needs_reset;\n+};\n+\n+struct gbe_phy_init_data_fix {\n+\tu16 addr;\n+\tu16 value;\n+};\n+\n+/* Changes to 40M1G25 mode data required for running 40M3G125 init mode */\n+static struct gbe_phy_init_data_fix gbe_phy_init_fix[] = {\n+\t{ 0x005, 0x07CC }, { 0x015, 0x0000 }, { 0x01B, 0x0000 },\n+\t{ 0x01D, 0x0000 }, { 0x01E, 0x0000 }, { 0x01F, 0x0000 },\n+\t{ 0x020, 0x0000 }, { 0x021, 0x0030 }, { 0x026, 0x0888 },\n+\t{ 0x04D, 0x0152 }, { 0x04F, 0xA020 }, { 0x050, 0x07CC },\n+\t{ 0x053, 0xE9CA }, { 0x055, 0xBD97 }, { 0x071, 0x3015 },\n+\t{ 0x076, 0x03AA }, { 0x07C, 0x0FDF }, { 0x0C2, 0x3030 },\n+\t{ 0x0C3, 0x8000 }, { 0x0E2, 0x5550 }, { 0x0E3, 0x12A4 },\n+\t{ 0x0E4, 0x7D00 }, { 0x0E6, 0x0C83 }, { 0x101, 0xFCC0 },\n+\t{ 0x104, 0x0C10 }\n };\n \n-static int mvebu_a3700_comphy_smc(unsigned long function, unsigned long lane,\n-\t\t\t\t  unsigned long mode)\n+/* 40M1G25 mode init data */\n+static u16 gbe_phy_init[512] = {\n+\t/* 0       1       2       3       4       5       6       7 */\n+\t/*-----------------------------------------------------------*/\n+\t/* 8       9       A       B       C       D       E       F */\n+\t0x3110, 0xFD83, 0x6430, 0x412F, 0x82C0, 0x06FA, 0x4500, 0x6D26,\t/* 00 */\n+\t0xAFC0, 0x8000, 0xC000, 0x0000, 0x2000, 0x49CC, 0x0BC9, 0x2A52,\t/* 08 */\n+\t0x0BD2, 0x0CDE, 0x13D2, 0x0CE8, 0x1149, 0x10E0, 0x0000, 0x0000,\t/* 10 */\n+\t0x0000, 0x0000, 0x0000, 0x0001, 0x0000, 0x4134, 0x0D2D, 0xFFFF,\t/* 18 */\n+\t0xFFE0, 0x4030, 0x1016, 0x0030, 0x0000, 0x0800, 0x0866, 0x0000,\t/* 20 */\n+\t0x0000, 0x0000, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,\t/* 28 */\n+\t0xFFFF, 0xFFFF, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\t/* 30 */\n+\t0x0000, 0x0000, 0x000F, 0x6A62, 0x1988, 0x3100, 0x3100, 0x3100,\t/* 38 */\n+\t0x3100, 0xA708, 0x2430, 0x0830, 0x1030, 0x4610, 0xFF00, 0xFF00,\t/* 40 */\n+\t0x0060, 0x1000, 0x0400, 0x0040, 0x00F0, 0x0155, 0x1100, 0xA02A,\t/* 48 */\n+\t0x06FA, 0x0080, 0xB008, 0xE3ED, 0x5002, 0xB592, 0x7A80, 0x0001,\t/* 50 */\n+\t0x020A, 0x8820, 0x6014, 0x8054, 0xACAA, 0xFC88, 0x2A02, 0x45CF,\t/* 58 */\n+\t0x000F, 0x1817, 0x2860, 0x064F, 0x0000, 0x0204, 0x1800, 0x6000,\t/* 60 */\n+\t0x810F, 0x4F23, 0x4000, 0x4498, 0x0850, 0x0000, 0x000E, 0x1002,\t/* 68 */\n+\t0x9D3A, 0x3009, 0xD066, 0x0491, 0x0001, 0x6AB0, 0x0399, 0x3780,\t/* 70 */\n+\t0x0040, 0x5AC0, 0x4A80, 0x0000, 0x01DF, 0x0000, 0x0007, 0x0000,\t/* 78 */\n+\t0x2D54, 0x00A1, 0x4000, 0x0100, 0xA20A, 0x0000, 0x0000, 0x0000,\t/* 80 */\n+\t0x0000, 0x0000, 0x0000, 0x7400, 0x0E81, 0x1000, 0x1242, 0x0210,\t/* 88 */\n+\t0x80DF, 0x0F1F, 0x2F3F, 0x4F5F, 0x6F7F, 0x0F1F, 0x2F3F, 0x4F5F,\t/* 90 */\n+\t0x6F7F, 0x4BAD, 0x0000, 0x0000, 0x0800, 0x0000, 0x2400, 0xB651,\t/* 98 */\n+\t0xC9E0, 0x4247, 0x0A24, 0x0000, 0xAF19, 0x1004, 0x0000, 0x0000,\t/* A0 */\n+\t0x0000, 0x0013, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\t/* A8 */\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\t/* B0 */\n+\t0x0000, 0x0000, 0x0000, 0x0060, 0x0000, 0x0000, 0x0000, 0x0000,\t/* B8 */\n+\t0x0000, 0x0000, 0x3010, 0xFA00, 0x0000, 0x0000, 0x0000, 0x0003,\t/* C0 */\n+\t0x1618, 0x8200, 0x8000, 0x0400, 0x050F, 0x0000, 0x0000, 0x0000,\t/* C8 */\n+\t0x4C93, 0x0000, 0x1000, 0x1120, 0x0010, 0x1242, 0x1242, 0x1E00,\t/* D0 */\n+\t0x0000, 0x0000, 0x0000, 0x00F8, 0x0000, 0x0041, 0x0800, 0x0000,\t/* D8 */\n+\t0x82A0, 0x572E, 0x2490, 0x14A9, 0x4E00, 0x0000, 0x0803, 0x0541,\t/* E0 */\n+\t0x0C15, 0x0000, 0x0000, 0x0400, 0x2626, 0x0000, 0x0000, 0x4200,\t/* E8 */\n+\t0x0000, 0xAA55, 0x1020, 0x0000, 0x0000, 0x5010, 0x0000, 0x0000,\t/* F0 */\n+\t0x0000, 0x0000, 0x5000, 0x0000, 0x0000, 0x0000, 0x02F2, 0x0000,\t/* F8 */\n+\t0x101F, 0xFDC0, 0x4000, 0x8010, 0x0110, 0x0006, 0x0000, 0x0000,\t/*100 */\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\t/*108 */\n+\t0x04CF, 0x0000, 0x04CF, 0x0000, 0x04CF, 0x0000, 0x04C6, 0x0000,\t/*110 */\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\t/*118 */\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\t/*120 */\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\t/*128 */\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\t/*130 */\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\t/*138 */\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\t/*140 */\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\t/*148 */\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\t/*150 */\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\t/*158 */\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\t/*160 */\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\t/*168 */\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\t/*170 */\n+\t0x0000, 0x0000, 0x0000, 0x00F0, 0x08A2, 0x3112, 0x0A14, 0x0000,\t/*178 */\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\t/*180 */\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\t/*188 */\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\t/*190 */\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\t/*198 */\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\t/*1A0 */\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\t/*1A8 */\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\t/*1B0 */\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\t/*1B8 */\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\t/*1C0 */\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\t/*1C8 */\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\t/*1D0 */\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\t/*1D8 */\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\t/*1E0 */\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\t/*1E8 */\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,\t/*1F0 */\n+\t0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000\t/*1F8 */\n+};\n+\n+static inline void comphy_reg_set(void __iomem *addr, u32 data, u32 mask)\n {\n-\tstruct arm_smccc_res res;\n-\ts32 ret;\n+\tu32 val;\n \n-\tarm_smccc_smc(function, lane, mode, 0, 0, 0, 0, 0, &res);\n-\tret = res.a0;\n+\tval = readl(addr);\n+\tval = (val & ~mask) | (data & mask);\n+\twritel(val, addr);\n+}\n \n-\tswitch (ret) {\n-\tcase SMCCC_RET_SUCCESS:\n-\t\treturn 0;\n-\tcase SMCCC_RET_NOT_SUPPORTED:\n-\t\treturn -EOPNOTSUPP;\n+static inline void comphy_reg_set16(void __iomem *addr, u16 data, u16 mask)\n+{\n+\tu16 val;\n+\n+\tval = readw(addr);\n+\tval = (val & ~mask) | (data & mask);\n+\twritew(val, addr);\n+}\n+\n+/* Used for accessing lane 2 registers (SATA/USB3 PHY) */\n+static void comphy_set_indirect(struct mvebu_a3700_comphy_priv *priv,\n+\t\t\t\tu32 offset, u16 data, u16 mask)\n+{\n+\twritel(offset,\n+\t       priv->lane2_phy_indirect + COMPHY_LANE2_INDIR_ADDR);\n+\tcomphy_reg_set(priv->lane2_phy_indirect + COMPHY_LANE2_INDIR_DATA,\n+\t\t       data, mask);\n+}\n+\n+static void comphy_lane_reg_set(struct mvebu_a3700_comphy_lane *lane,\n+\t\t\t\tu16 reg, u16 data, u16 mask)\n+{\n+\tif (lane->id == 2) {\n+\t\t/* lane 2 PHY registers are accessed indirectly */\n+\t\tcomphy_set_indirect(lane->priv,\n+\t\t\t\t    reg + COMPHY_LANE2_REGS_BASE,\n+\t\t\t\t    data, mask);\n+\t} else {\n+\t\tvoid __iomem *base = lane->id == 1 ?\n+\t\t\t\t     lane->priv->lane1_phy_regs :\n+\t\t\t\t     lane->priv->lane0_phy_regs;\n+\n+\t\tcomphy_reg_set16(base + COMPHY_LANE_REG_DIRECT(reg),\n+\t\t\t\t data, mask);\n+\t}\n+}\n+\n+static int comphy_lane_reg_poll(struct mvebu_a3700_comphy_lane *lane,\n+\t\t\t\tu16 reg, u16 bits,\n+\t\t\t\tulong sleep_us, ulong timeout_us)\n+{\n+\tint ret;\n+\n+\tif (lane->id == 2) {\n+\t\tu32 data;\n+\n+\t\t/* lane 2 PHY registers are accessed indirectly */\n+\t\twritel(reg + COMPHY_LANE2_REGS_BASE,\n+\t\t       lane->priv->lane2_phy_indirect +\n+\t\t       COMPHY_LANE2_INDIR_ADDR);\n+\n+\t\tret = readl_poll_timeout(lane->priv->lane2_phy_indirect +\n+\t\t\t\t\t COMPHY_LANE2_INDIR_DATA,\n+\t\t\t\t\t data, (data & bits) == bits,\n+\t\t\t\t\t sleep_us, timeout_us);\n+\t} else {\n+\t\tvoid __iomem *base = lane->id == 1 ?\n+\t\t\t\t     lane->priv->lane1_phy_regs :\n+\t\t\t\t     lane->priv->lane0_phy_regs;\n+\t\tu16 data;\n+\n+\t\tret = readw_poll_timeout(base + COMPHY_LANE_REG_DIRECT(reg),\n+\t\t\t\t\t data, (data & bits) == bits,\n+\t\t\t\t\t sleep_us, timeout_us);\n+\t}\n+\n+\treturn ret;\n+}\n+\n+static void comphy_periph_reg_set(struct mvebu_a3700_comphy_lane *lane,\n+\t\t\t\t  u8 reg, u32 data, u32 mask)\n+{\n+\tcomphy_reg_set(lane->priv->comphy_regs + COMPHY_PHY_REG(lane->id, reg),\n+\t\t       data, mask);\n+}\n+\n+static int comphy_periph_reg_poll(struct mvebu_a3700_comphy_lane *lane,\n+\t\t\t\t  u8 reg, u32 bits,\n+\t\t\t\t  ulong sleep_us, ulong timeout_us)\n+{\n+\tu32 data;\n+\n+\treturn readl_poll_timeout(lane->priv->comphy_regs +\n+\t\t\t\t  COMPHY_PHY_REG(lane->id, reg),\n+\t\t\t\t  data, (data & bits) == bits,\n+\t\t\t\t  sleep_us, timeout_us);\n+}\n+\n+/* PHY selector configures with corresponding modes */\n+static int\n+mvebu_a3700_comphy_set_phy_selector(struct mvebu_a3700_comphy_lane *lane)\n+{\n+\tu32 old, new, clr = 0, set = 0;\n+\tunsigned long flags;\n+\n+\tswitch (lane->mode) {\n+\tcase PHY_MODE_SATA:\n+\t\t/* SATA must be in Lane2 */\n+\t\tif (lane->id == 2)\n+\t\t\tclr = COMPHY_SELECTOR_USB3_PHY_SEL_BIT;\n+\t\telse\n+\t\t\tgoto error;\n+\t\tbreak;\n+\n+\tcase PHY_MODE_ETHERNET:\n+\t\tif (lane->id == 0)\n+\t\t\tclr = COMPHY_SELECTOR_USB3_GBE1_SEL_BIT;\n+\t\telse if (lane->id == 1)\n+\t\t\tclr = COMPHY_SELECTOR_PCIE_GBE0_SEL_BIT;\n+\t\telse\n+\t\t\tgoto error;\n+\t\tbreak;\n+\n+\tcase PHY_MODE_USB_HOST_SS:\n+\t\tif (lane->id == 2)\n+\t\t\tset = COMPHY_SELECTOR_USB3_PHY_SEL_BIT;\n+\t\telse if (lane->id == 0)\n+\t\t\tset = COMPHY_SELECTOR_USB3_GBE1_SEL_BIT;\n+\t\telse\n+\t\t\tgoto error;\n+\t\tbreak;\n+\n+\tcase PHY_MODE_PCIE:\n+\t\t/* PCIE must be in Lane1 */\n+\t\tif (lane->id == 1)\n+\t\t\tset = COMPHY_SELECTOR_PCIE_GBE0_SEL_BIT;\n+\t\telse\n+\t\t\tgoto error;\n+\t\tbreak;\n+\n+\tdefault:\n+\t\tgoto error;\n+\t}\n+\n+\tspin_lock_irqsave(&lane->priv->lock, flags);\n+\n+\told = readl(lane->priv->comphy_regs + COMPHY_SELECTOR_PHY_REG);\n+\tnew = (old & ~clr) | set;\n+\twritel(new, lane->priv->comphy_regs + COMPHY_SELECTOR_PHY_REG);\n+\n+\tspin_unlock_irqrestore(&lane->priv->lock, flags);\n+\n+\tdev_dbg(lane->dev,\n+\t\t\"COMPHY[%d] mode[%d] changed PHY selector 0x%08x -> 0x%08x\\n\",\n+\t\tlane->id, lane->mode, old, new);\n+\n+\treturn 0;\n+error:\n+\tdev_err(lane->dev, \"COMPHY[%d] mode[%d] is invalid\\n\", lane->id,\n+\t\tlane->mode);\n+\treturn -EINVAL;\n+}\n+\n+static int\n+mvebu_a3700_comphy_sata_power_on(struct mvebu_a3700_comphy_lane *lane)\n+{\n+\tu32 mask, data, ref_clk;\n+\tint ret;\n+\n+\t/* Configure phy selector for SATA */\n+\tret = mvebu_a3700_comphy_set_phy_selector(lane);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\t/* Clear phy isolation mode to make it work in normal mode */\n+\tcomphy_lane_reg_set(lane, COMPHY_ISOLATION_CTRL,\n+\t\t\t    0x0, PHY_ISOLATE_MODE);\n+\n+\t/* 0. Check the Polarity invert bits */\n+\tdata = 0x0;\n+\tif (lane->invert_tx)\n+\t\tdata |= TXD_INVERT_BIT;\n+\tif (lane->invert_rx)\n+\t\tdata |= RXD_INVERT_BIT;\n+\tmask = TXD_INVERT_BIT | RXD_INVERT_BIT;\n+\tcomphy_lane_reg_set(lane, COMPHY_SYNC_PATTERN, data, mask);\n+\n+\t/* 1. Select 40-bit data width */\n+\tcomphy_lane_reg_set(lane, COMPHY_DIG_LOOPBACK_EN,\n+\t\t\t    DATA_WIDTH_40BIT, SEL_DATA_WIDTH_MASK);\n+\n+\t/* 2. Select reference clock(25M) and PHY mode (SATA) */\n+\tif (lane->priv->xtal_is_40m)\n+\t\tref_clk = REF_FREF_SEL_SERDES_40MHZ;\n+\telse\n+\t\tref_clk = REF_FREF_SEL_SERDES_25MHZ;\n+\n+\tdata = ref_clk | COMPHY_MODE_SATA;\n+\tmask = REF_FREF_SEL_MASK | COMPHY_MODE_MASK;\n+\tcomphy_lane_reg_set(lane, COMPHY_POWER_PLL_CTRL, data, mask);\n+\n+\t/* 3. Use maximum PLL rate (no power save) */\n+\tcomphy_lane_reg_set(lane, COMPHY_KVCO_CAL_CTRL,\n+\t\t\t    USE_MAX_PLL_RATE_BIT, USE_MAX_PLL_RATE_BIT);\n+\n+\t/* 4. Reset reserved bit */\n+\tcomphy_set_indirect(lane->priv, COMPHY_RESERVED_REG,\n+\t\t\t    0x0, PHYCTRL_FRM_PIN_BIT);\n+\n+\t/* 5. Set vendor-specific configuration (It is done in sata driver) */\n+\t/* XXX: in U-Boot below sequence was executed in this place, in Linux\n+\t * not.  Now it is done only in U-Boot before this comphy\n+\t * initialization - tests shows that it works ok, but in case of any\n+\t * future problem it is left for reference.\n+\t *   reg_set(MVEBU_REGS_BASE + 0xe00a0, 0, 0xffffffff);\n+\t *   reg_set(MVEBU_REGS_BASE + 0xe00a4, BIT(6), BIT(6));\n+\t */\n+\n+\t/* Wait for > 55 us to allow PLL be enabled */\n+\tudelay(PLL_SET_DELAY_US);\n+\n+\t/* Polling status */\n+\tret = comphy_lane_reg_poll(lane, COMPHY_DIG_LOOPBACK_EN,\n+\t\t\t\t   PLL_READY_TX_BIT, COMPHY_PLL_SLEEP,\n+\t\t\t\t   COMPHY_PLL_TIMEOUT);\n+\tif (ret) {\n+\t\tdev_err(lane->dev, \"Failed to lock SATA PLL\\n\");\n+\t\treturn ret;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static void comphy_gbe_phy_init(struct mvebu_a3700_comphy_lane *lane,\n+\t\t\t\tbool is_1gbps)\n+{\n+\tint addr, fix_idx;\n+\tu16 val;\n+\n+\tfix_idx = 0;\n+\tfor (addr = 0; addr < 512; addr++) {\n+\t\t/*\n+\t\t * All PHY register values are defined in full for 3.125Gbps\n+\t\t * SERDES speed. The values required for 1.25 Gbps are almost\n+\t\t * the same and only few registers should be \"fixed\" in\n+\t\t * comparison to 3.125 Gbps values. These register values are\n+\t\t * stored in \"gbe_phy_init_fix\" array.\n+\t\t */\n+\t\tif (!is_1gbps && gbe_phy_init_fix[fix_idx].addr == addr) {\n+\t\t\t/* Use new value */\n+\t\t\tval = gbe_phy_init_fix[fix_idx].value;\n+\t\t\tif (fix_idx < ARRAY_SIZE(gbe_phy_init_fix))\n+\t\t\t\tfix_idx++;\n+\t\t} else {\n+\t\t\tval = gbe_phy_init[addr];\n+\t\t}\n+\n+\t\tcomphy_lane_reg_set(lane, addr, val, 0xFFFF);\n+\t}\n+}\n+\n+static int\n+mvebu_a3700_comphy_ethernet_power_on(struct mvebu_a3700_comphy_lane *lane)\n+{\n+\tu32 mask, data, speed_sel;\n+\tint ret;\n+\n+\t/* Set selector */\n+\tret = mvebu_a3700_comphy_set_phy_selector(lane);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\t/*\n+\t * 1. Reset PHY by setting PHY input port PIN_RESET=1.\n+\t * 2. Set PHY input port PIN_TX_IDLE=1, PIN_PU_IVREF=1 to keep\n+\t *    PHY TXP/TXN output to idle state during PHY initialization\n+\t * 3. Set PHY input port PIN_PU_PLL=0, PIN_PU_RX=0, PIN_PU_TX=0.\n+\t */\n+\tdata = PIN_PU_IVREF_BIT | PIN_TX_IDLE_BIT | PIN_RESET_COMPHY_BIT;\n+\tmask = data | PIN_RESET_CORE_BIT | PIN_PU_PLL_BIT | PIN_PU_RX_BIT |\n+\t       PIN_PU_TX_BIT | PHY_RX_INIT_BIT;\n+\tcomphy_periph_reg_set(lane, COMPHY_PHY_CFG1, data, mask);\n+\n+\t/* 4. Release reset to the PHY by setting PIN_RESET=0. */\n+\tdata = 0x0;\n+\tmask = PIN_RESET_COMPHY_BIT;\n+\tcomphy_periph_reg_set(lane, COMPHY_PHY_CFG1, data, mask);\n+\n+\t/*\n+\t * 5. Set PIN_PHY_GEN_TX[3:0] and PIN_PHY_GEN_RX[3:0] to decide COMPHY\n+\t * bit rate\n+\t */\n+\tswitch (lane->submode) {\n+\tcase PHY_INTERFACE_MODE_SGMII:\n+\tcase PHY_INTERFACE_MODE_1000BASEX:\n+\t\t/* SGMII 1G, SerDes speed 1.25G */\n+\t\tspeed_sel = SERDES_SPEED_1_25_G;\n+\t\tbreak;\n+\tcase PHY_INTERFACE_MODE_2500BASEX:\n+\t\t/* 2500Base-X, SerDes speed 3.125G */\n+\t\tspeed_sel = SERDES_SPEED_3_125_G;\n+\t\tbreak;\n \tdefault:\n+\t\t/* Other rates are not supported */\n+\t\tdev_err(lane->dev,\n+\t\t\t\"unsupported phy speed %d on comphy lane%d\\n\",\n+\t\t\tlane->submode, lane->id);\n \t\treturn -EINVAL;\n \t}\n+\tdata = GEN_RX_SEL_VALUE(speed_sel) | GEN_TX_SEL_VALUE(speed_sel);\n+\tmask = GEN_RX_SEL_MASK | GEN_TX_SEL_MASK;\n+\tcomphy_periph_reg_set(lane, COMPHY_PHY_CFG1, data, mask);\n+\n+\t/*\n+\t * 6. Wait 10mS for bandgap and reference clocks to stabilize; then\n+\t * start SW programming.\n+\t */\n+\tmdelay(10);\n+\n+\t/* 7. Program COMPHY register PHY_MODE */\n+\tdata = COMPHY_MODE_SERDES;\n+\tmask = COMPHY_MODE_MASK;\n+\tcomphy_lane_reg_set(lane, COMPHY_POWER_PLL_CTRL, data, mask);\n+\n+\t/*\n+\t * 8. Set COMPHY register REFCLK_SEL to select the correct REFCLK\n+\t * source\n+\t */\n+\tdata = 0x0;\n+\tmask = PHY_REF_CLK_SEL;\n+\tcomphy_lane_reg_set(lane, COMPHY_MISC_CTRL0, data, mask);\n+\n+\t/*\n+\t * 9. Set correct reference clock frequency in COMPHY register\n+\t * REF_FREF_SEL.\n+\t */\n+\tif (lane->priv->xtal_is_40m)\n+\t\tdata = REF_FREF_SEL_SERDES_50MHZ;\n+\telse\n+\t\tdata = REF_FREF_SEL_SERDES_25MHZ;\n+\n+\tmask = REF_FREF_SEL_MASK;\n+\tcomphy_lane_reg_set(lane, COMPHY_POWER_PLL_CTRL, data, mask);\n+\n+\t/* 10. Program COMPHY register PHY_GEN_MAX[1:0]\n+\t * This step is mentioned in the flow received from verification team.\n+\t * However the PHY_GEN_MAX value is only meaningful for other interfaces\n+\t * (not SERDES). For instance, it selects SATA speed 1.5/3/6 Gbps or\n+\t * PCIe speed 2.5/5 Gbps\n+\t */\n+\n+\t/*\n+\t * 11. Program COMPHY register SEL_BITS to set correct parallel data\n+\t * bus width\n+\t */\n+\tdata = DATA_WIDTH_10BIT;\n+\tmask = SEL_DATA_WIDTH_MASK;\n+\tcomphy_lane_reg_set(lane, COMPHY_DIG_LOOPBACK_EN, data, mask);\n+\n+\t/*\n+\t * 12. As long as DFE function needs to be enabled in any mode,\n+\t * COMPHY register DFE_UPDATE_EN[5:0] shall be programmed to 0x3F\n+\t * for real chip during COMPHY power on.\n+\t * The step 14 exists (and empty) in the original initialization flow\n+\t * obtained from the verification team. According to the functional\n+\t * specification DFE_UPDATE_EN already has the default value 0x3F\n+\t */\n+\n+\t/*\n+\t * 13. Program COMPHY GEN registers.\n+\t * These registers should be programmed based on the lab testing result\n+\t * to achieve optimal performance. Please contact the CEA group to get\n+\t * the related GEN table during real chip bring-up. We only required to\n+\t * run though the entire registers programming flow defined by\n+\t * \"comphy_gbe_phy_init\" when the REF clock is 40 MHz. For REF clock\n+\t * 25 MHz the default values stored in PHY registers are OK.\n+\t */\n+\tdev_dbg(lane->dev, \"Running C-DPI phy init %s mode\\n\",\n+\t\tlane->submode == PHY_INTERFACE_MODE_2500BASEX ? \"2G5\" : \"1G\");\n+\tif (lane->priv->xtal_is_40m)\n+\t\tcomphy_gbe_phy_init(lane,\n+\t\t\t\t    lane->submode != PHY_INTERFACE_MODE_2500BASEX);\n+\n+\t/*\n+\t * 14. [Simulation Only] should not be used for real chip.\n+\t * By pass power up calibration by programming EXT_FORCE_CAL_DONE\n+\t * (R02h[9]) to 1 to shorten COMPHY simulation time.\n+\t */\n+\n+\t/*\n+\t * 15. [Simulation Only: should not be used for real chip]\n+\t * Program COMPHY register FAST_DFE_TIMER_EN=1 to shorten RX training\n+\t * simulation time.\n+\t */\n+\n+\t/*\n+\t * 16. Check the PHY Polarity invert bit\n+\t */\n+\tdata = 0x0;\n+\tif (lane->invert_tx)\n+\t\tdata |= TXD_INVERT_BIT;\n+\tif (lane->invert_rx)\n+\t\tdata |= RXD_INVERT_BIT;\n+\tmask = TXD_INVERT_BIT | RXD_INVERT_BIT;\n+\tcomphy_lane_reg_set(lane, COMPHY_SYNC_PATTERN, data, mask);\n+\n+\t/*\n+\t * 17. Set PHY input ports PIN_PU_PLL, PIN_PU_TX and PIN_PU_RX to 1 to\n+\t * start PHY power up sequence. All the PHY register programming should\n+\t * be done before PIN_PU_PLL=1. There should be no register programming\n+\t * for normal PHY operation from this point.\n+\t */\n+\tdata = PIN_PU_PLL_BIT | PIN_PU_RX_BIT | PIN_PU_TX_BIT;\n+\tmask = data;\n+\tcomphy_periph_reg_set(lane, COMPHY_PHY_CFG1, data, mask);\n+\n+\t/*\n+\t * 18. Wait for PHY power up sequence to finish by checking output ports\n+\t * PIN_PLL_READY_TX=1 and PIN_PLL_READY_RX=1.\n+\t */\n+\tret = comphy_periph_reg_poll(lane, COMPHY_PHY_STAT1,\n+\t\t\t\t     PHY_PLL_READY_TX_BIT |\n+\t\t\t\t     PHY_PLL_READY_RX_BIT,\n+\t\t\t\t     COMPHY_PLL_SLEEP, COMPHY_PLL_TIMEOUT);\n+\tif (ret) {\n+\t\tdev_err(lane->dev, \"Failed to lock PLL for SERDES PHY %d\\n\",\n+\t\t\tlane->id);\n+\t\treturn ret;\n+\t}\n+\n+\t/*\n+\t * 19. Set COMPHY input port PIN_TX_IDLE=0\n+\t */\n+\tcomphy_periph_reg_set(lane, COMPHY_PHY_CFG1, 0x0, PIN_TX_IDLE_BIT);\n+\n+\t/*\n+\t * 20. After valid data appear on PIN_RXDATA bus, set PIN_RX_INIT=1. To\n+\t * start RX initialization. PIN_RX_INIT_DONE will be cleared to 0 by the\n+\t * PHY After RX initialization is done, PIN_RX_INIT_DONE will be set to\n+\t * 1 by COMPHY Set PIN_RX_INIT=0 after PIN_RX_INIT_DONE= 1. Please\n+\t * refer to RX initialization part for details.\n+\t */\n+\tcomphy_periph_reg_set(lane, COMPHY_PHY_CFG1,\n+\t\t\t      PHY_RX_INIT_BIT, PHY_RX_INIT_BIT);\n+\n+\tret = comphy_periph_reg_poll(lane, COMPHY_PHY_STAT1,\n+\t\t\t\t     PHY_PLL_READY_TX_BIT |\n+\t\t\t\t     PHY_PLL_READY_RX_BIT,\n+\t\t\t\t     COMPHY_PLL_SLEEP, COMPHY_PLL_TIMEOUT);\n+\tif (ret) {\n+\t\tdev_err(lane->dev, \"Failed to lock PLL for SERDES PHY %d\\n\",\n+\t\t\tlane->id);\n+\t\treturn ret;\n+\t}\n+\n+\tret = comphy_periph_reg_poll(lane, COMPHY_PHY_STAT1,\n+\t\t\t\t     PHY_RX_INIT_DONE_BIT,\n+\t\t\t\t     COMPHY_PLL_SLEEP, COMPHY_PLL_TIMEOUT);\n+\tif (ret) {\n+\t\tdev_err(lane->dev, \"Failed to init RX of SERDES PHY %d\\n\",\n+\t\t\tlane->id);\n+\t\treturn ret;\n+\t}\n+\n+\treturn 0;\n }\n \n-static int mvebu_a3700_comphy_get_fw_mode(int lane,\n+static int\n+mvebu_a3700_comphy_usb3_power_on(struct mvebu_a3700_comphy_lane *lane)\n+{\n+\tu32 mask, data, cfg, ref_clk;\n+\tint ret;\n+\n+\t/* Set phy seclector */\n+\tret = mvebu_a3700_comphy_set_phy_selector(lane);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\t/*\n+\t * 0. Set PHY OTG Control(0x5d034), bit 4, Power up OTG module The\n+\t * register belong to UTMI module, so it is set in UTMI phy driver.\n+\t */\n+\n+\t/*\n+\t * 1. Set PRD_TXDEEMPH (3.5db de-emph)\n+\t */\n+\tdata = PRD_TXDEEMPH0_MASK;\n+\tmask = PRD_TXDEEMPH0_MASK | PRD_TXMARGIN_MASK | PRD_TXSWING_MASK |\n+\t       CFG_TX_ALIGN_POS_MASK;\n+\tcomphy_lane_reg_set(lane, COMPHY_PIPE_LANE_CFG0, data, mask);\n+\n+\t/*\n+\t * 2. Set BIT0: enable transmitter in high impedance mode\n+\t *    Set BIT[3:4]: delay 2 clock cycles for HiZ off latency\n+\t *    Set BIT6: Tx detect Rx at HiZ mode\n+\t *    Unset BIT15: set to 0 to set USB3 De-emphasize level to -3.5db\n+\t *            together with bit 0 of COMPHY_PIPE_LANE_CFG0 register\n+\t */\n+\tdata = TX_DET_RX_MODE | GEN2_TX_DATA_DLY_DEFT | TX_ELEC_IDLE_MODE_EN;\n+\tmask = PRD_TXDEEMPH1_MASK | TX_DET_RX_MODE | GEN2_TX_DATA_DLY_MASK |\n+\t       TX_ELEC_IDLE_MODE_EN;\n+\tcomphy_lane_reg_set(lane, COMPHY_PIPE_LANE_CFG1, data, mask);\n+\n+\t/*\n+\t * 3. Set Spread Spectrum Clock Enabled\n+\t */\n+\tcomphy_lane_reg_set(lane, COMPHY_PIPE_LANE_CFG4,\n+\t\t\t    SPREAD_SPECTRUM_CLK_EN, SPREAD_SPECTRUM_CLK_EN);\n+\n+\t/*\n+\t * 4. Set Override Margining Controls From the MAC:\n+\t *    Use margining signals from lane configuration\n+\t */\n+\tcomphy_lane_reg_set(lane, COMPHY_PIPE_TEST_MODE_CTRL,\n+\t\t\t    MODE_MARGIN_OVERRIDE, 0xFFFF);\n+\n+\t/*\n+\t * 5. Set Lane-to-Lane Bundle Clock Sampling Period = per PCLK cycles\n+\t *    set Mode Clock Source = PCLK is generated from REFCLK\n+\t */\n+\tdata = 0x0;\n+\tmask = MODE_CLK_SRC | BUNDLE_PERIOD_SEL | BUNDLE_PERIOD_SCALE_MASK |\n+\t       BUNDLE_SAMPLE_CTRL | PLL_READY_DLY_MASK;\n+\tcomphy_lane_reg_set(lane, COMPHY_PIPE_CLK_SRC_LO, data, mask);\n+\n+\t/*\n+\t * 6. Set G2 Spread Spectrum Clock Amplitude at 4K\n+\t */\n+\tcomphy_lane_reg_set(lane, COMPHY_GEN2_SET2,\n+\t\t\t    GS2_TX_SSC_AMP_4128, GS2_TX_SSC_AMP_MASK);\n+\n+\t/*\n+\t * 7. Unset G3 Spread Spectrum Clock Amplitude\n+\t *    set G3 TX and RX Register Master Current Select\n+\t */\n+\tdata = GS2_VREG_RXTX_MAS_ISET_60U;\n+\tmask = GS2_TX_SSC_AMP_MASK | GS2_VREG_RXTX_MAS_ISET_MASK |\n+\t       GS2_RSVD_6_0_MASK;\n+\tcomphy_lane_reg_set(lane, COMPHY_GEN3_SET2, data, mask);\n+\n+\t/*\n+\t * 8. Check crystal jumper setting and program the Power and PLL Control\n+\t * accordingly Change RX wait\n+\t */\n+\tif (lane->priv->xtal_is_40m) {\n+\t\tref_clk = REF_FREF_SEL_PCIE_USB3_40MHZ;\n+\t\tcfg = CFG_PM_RXDLOZ_WAIT_12_UNIT;\n+\t} else {\n+\t\tref_clk = REF_FREF_SEL_PCIE_USB3_25MHZ;\n+\t\tcfg = CFG_PM_RXDLOZ_WAIT_7_UNIT;\n+\t}\n+\n+\tdata = PU_IVREF_BIT | PU_PLL_BIT | PU_RX_BIT | PU_TX_BIT |\n+\t       PU_TX_INTP_BIT | PU_DFE_BIT | COMPHY_MODE_USB3 | ref_clk;\n+\tmask = PU_IVREF_BIT | PU_PLL_BIT | PU_RX_BIT | PU_TX_BIT |\n+\t       PU_TX_INTP_BIT | PU_DFE_BIT | PLL_LOCK_BIT | COMPHY_MODE_MASK |\n+\t       REF_FREF_SEL_MASK;\n+\tcomphy_lane_reg_set(lane, COMPHY_POWER_PLL_CTRL, data, mask);\n+\n+\tdata = CFG_PM_RXDEN_WAIT_1_UNIT | cfg;\n+\tmask = CFG_PM_OSCCLK_WAIT_MASK | CFG_PM_RXDEN_WAIT_MASK |\n+\t       CFG_PM_RXDLOZ_WAIT_MASK;\n+\tcomphy_lane_reg_set(lane, COMPHY_PIPE_PWR_MGM_TIM1, data, mask);\n+\n+\t/*\n+\t * 9. Enable idle sync\n+\t */\n+\tcomphy_lane_reg_set(lane, COMPHY_IDLE_SYNC_EN,\n+\t\t\t    IDLE_SYNC_EN, IDLE_SYNC_EN);\n+\n+\t/*\n+\t * 10. Enable the output of 500M clock\n+\t */\n+\tcomphy_lane_reg_set(lane, COMPHY_MISC_CTRL0, CLK500M_EN, CLK500M_EN);\n+\n+\t/*\n+\t * 11. Set 20-bit data width\n+\t */\n+\tcomphy_lane_reg_set(lane, COMPHY_DIG_LOOPBACK_EN,\n+\t\t\t    DATA_WIDTH_20BIT, 0xFFFF);\n+\n+\t/*\n+\t * 12. Override Speed_PLL value and use MAC PLL\n+\t */\n+\tdata = SPEED_PLL_VALUE_16 | USE_MAX_PLL_RATE_BIT;\n+\tmask = 0xFFFF;\n+\tcomphy_lane_reg_set(lane, COMPHY_KVCO_CAL_CTRL, data, mask);\n+\n+\t/*\n+\t * 13. Check the Polarity invert bit\n+\t */\n+\tdata = 0x0;\n+\tif (lane->invert_tx)\n+\t\tdata |= TXD_INVERT_BIT;\n+\tif (lane->invert_rx)\n+\t\tdata |= RXD_INVERT_BIT;\n+\tmask = TXD_INVERT_BIT | RXD_INVERT_BIT;\n+\tcomphy_lane_reg_set(lane, COMPHY_SYNC_PATTERN, data, mask);\n+\n+\t/*\n+\t * 14. Set max speed generation to USB3.0 5Gbps\n+\t */\n+\tcomphy_lane_reg_set(lane, COMPHY_SYNC_MASK_GEN,\n+\t\t\t    PHY_GEN_MAX_USB3_5G, PHY_GEN_MAX_MASK);\n+\n+\t/*\n+\t * 15. Set capacitor value for FFE gain peaking to 0xF\n+\t */\n+\tcomphy_lane_reg_set(lane, COMPHY_GEN2_SET3,\n+\t\t\t    GS3_FFE_CAP_SEL_VALUE, GS3_FFE_CAP_SEL_MASK);\n+\n+\t/*\n+\t * 16. Release SW reset\n+\t */\n+\tdata = MODE_CORE_CLK_FREQ_SEL | MODE_PIPE_WIDTH_32 | MODE_REFDIV_BY_4;\n+\tmask = 0xFFFF;\n+\tcomphy_lane_reg_set(lane, COMPHY_PIPE_RST_CLK_CTRL, data, mask);\n+\n+\t/* Wait for > 55 us to allow PCLK be enabled */\n+\tudelay(PLL_SET_DELAY_US);\n+\n+\tret = comphy_lane_reg_poll(lane, COMPHY_PIPE_LANE_STAT1, TXDCLK_PCLK_EN,\n+\t\t\t\t   COMPHY_PLL_SLEEP, COMPHY_PLL_TIMEOUT);\n+\tif (ret) {\n+\t\tdev_err(lane->dev, \"Failed to lock USB3 PLL\\n\");\n+\t\treturn ret;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int\n+mvebu_a3700_comphy_pcie_power_on(struct mvebu_a3700_comphy_lane *lane)\n+{\n+\tu32 mask, data, ref_clk;\n+\tint ret;\n+\n+\t/* Configure phy selector for PCIe */\n+\tret = mvebu_a3700_comphy_set_phy_selector(lane);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\t/* 1. Enable max PLL. */\n+\tcomphy_lane_reg_set(lane, COMPHY_PIPE_LANE_CFG1,\n+\t\t\t    USE_MAX_PLL_RATE_EN, USE_MAX_PLL_RATE_EN);\n+\n+\t/* 2. Select 20 bit SERDES interface. */\n+\tcomphy_lane_reg_set(lane, COMPHY_PIPE_CLK_SRC_LO,\n+\t\t\t    CFG_SEL_20B, CFG_SEL_20B);\n+\n+\t/* 3. Force to use reg setting for PCIe mode */\n+\tcomphy_lane_reg_set(lane, COMPHY_MISC_CTRL1,\n+\t\t\t    SEL_BITS_PCIE_FORCE, SEL_BITS_PCIE_FORCE);\n+\n+\t/* 4. Change RX wait */\n+\tdata = CFG_PM_RXDEN_WAIT_1_UNIT | CFG_PM_RXDLOZ_WAIT_12_UNIT;\n+\tmask = CFG_PM_OSCCLK_WAIT_MASK | CFG_PM_RXDEN_WAIT_MASK |\n+\t       CFG_PM_RXDLOZ_WAIT_MASK;\n+\tcomphy_lane_reg_set(lane, COMPHY_PIPE_PWR_MGM_TIM1, data, mask);\n+\n+\t/* 5. Enable idle sync */\n+\tcomphy_lane_reg_set(lane, COMPHY_IDLE_SYNC_EN,\n+\t\t\t    IDLE_SYNC_EN, IDLE_SYNC_EN);\n+\n+\t/* 6. Enable the output of 100M/125M/500M clock */\n+\tdata = CLK500M_EN | TXDCLK_2X_SEL | CLK100M_125M_EN;\n+\tmask = data;\n+\tcomphy_lane_reg_set(lane, COMPHY_MISC_CTRL0, data, mask);\n+\n+\t/*\n+\t * 7. Enable TX, PCIE global register, 0xd0074814, it is done in\n+\t * PCI-E driver\n+\t */\n+\n+\t/*\n+\t * 8. Check crystal jumper setting and program the Power and PLL\n+\t * Control accordingly\n+\t */\n+\n+\tif (lane->priv->xtal_is_40m)\n+\t\tref_clk = REF_FREF_SEL_PCIE_USB3_40MHZ;\n+\telse\n+\t\tref_clk = REF_FREF_SEL_PCIE_USB3_25MHZ;\n+\n+\tdata = PU_IVREF_BIT | PU_PLL_BIT | PU_RX_BIT | PU_TX_BIT |\n+\t       PU_TX_INTP_BIT | PU_DFE_BIT | COMPHY_MODE_PCIE | ref_clk;\n+\tmask = 0xFFFF;\n+\tcomphy_lane_reg_set(lane, COMPHY_POWER_PLL_CTRL, data, mask);\n+\n+\t/* 9. Override Speed_PLL value and use MAC PLL */\n+\tcomphy_lane_reg_set(lane, COMPHY_KVCO_CAL_CTRL,\n+\t\t\t    SPEED_PLL_VALUE_16 | USE_MAX_PLL_RATE_BIT,\n+\t\t\t    0xFFFF);\n+\n+\t/* 10. Check the Polarity invert bit */\n+\tdata = 0x0;\n+\tif (lane->invert_tx)\n+\t\tdata |= TXD_INVERT_BIT;\n+\tif (lane->invert_rx)\n+\t\tdata |= RXD_INVERT_BIT;\n+\tmask = TXD_INVERT_BIT | RXD_INVERT_BIT;\n+\tcomphy_lane_reg_set(lane, COMPHY_SYNC_PATTERN, data, mask);\n+\n+\t/* 11. Release SW reset */\n+\tdata = MODE_CORE_CLK_FREQ_SEL | MODE_PIPE_WIDTH_32;\n+\tmask = data | PIPE_SOFT_RESET | MODE_REFDIV_MASK;\n+\tcomphy_lane_reg_set(lane, COMPHY_PIPE_RST_CLK_CTRL, data, mask);\n+\n+\t/* Wait for > 55 us to allow PCLK be enabled */\n+\tudelay(PLL_SET_DELAY_US);\n+\n+\tret = comphy_lane_reg_poll(lane, COMPHY_PIPE_LANE_STAT1, TXDCLK_PCLK_EN,\n+\t\t\t\t   COMPHY_PLL_SLEEP, COMPHY_PLL_TIMEOUT);\n+\tif (ret) {\n+\t\tdev_err(lane->dev, \"Failed to lock PCIE PLL\\n\");\n+\t\treturn ret;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static void\n+mvebu_a3700_comphy_usb3_power_off(struct mvebu_a3700_comphy_lane *lane)\n+{\n+\t/*\n+\t * Currently the USB3 MAC sets the USB3 PHY to low state, so we do not\n+\t * need to power off USB3 PHY again.\n+\t */\n+}\n+\n+static void\n+mvebu_a3700_comphy_sata_power_off(struct mvebu_a3700_comphy_lane *lane)\n+{\n+\t/* Set phy isolation mode */\n+\tcomphy_lane_reg_set(lane, COMPHY_ISOLATION_CTRL,\n+\t\t\t    PHY_ISOLATE_MODE, PHY_ISOLATE_MODE);\n+\n+\t/* Power off PLL, Tx, Rx */\n+\tcomphy_lane_reg_set(lane, COMPHY_POWER_PLL_CTRL,\n+\t\t\t    0x0, PU_PLL_BIT | PU_RX_BIT | PU_TX_BIT);\n+}\n+\n+static void\n+mvebu_a3700_comphy_ethernet_power_off(struct mvebu_a3700_comphy_lane *lane)\n+{\n+\tu32 mask, data;\n+\n+\tdata = PIN_RESET_CORE_BIT | PIN_RESET_COMPHY_BIT | PIN_PU_IVREF_BIT |\n+\t       PHY_RX_INIT_BIT;\n+\tmask = data;\n+\tcomphy_periph_reg_set(lane, COMPHY_PHY_CFG1, data, mask);\n+}\n+\n+static void\n+mvebu_a3700_comphy_pcie_power_off(struct mvebu_a3700_comphy_lane *lane)\n+{\n+\t/* Power off PLL, Tx, Rx */\n+\tcomphy_lane_reg_set(lane, COMPHY_POWER_PLL_CTRL,\n+\t\t\t    0x0, PU_PLL_BIT | PU_RX_BIT | PU_TX_BIT);\n+}\n+\n+static int mvebu_a3700_comphy_reset(struct phy *phy)\n+{\n+\tstruct mvebu_a3700_comphy_lane *lane = phy_get_drvdata(phy);\n+\tu16 mask, data;\n+\n+\tdev_dbg(lane->dev, \"resetting lane %d\\n\", lane->id);\n+\n+\t/* COMPHY reset for internal logic */\n+\tcomphy_lane_reg_set(lane, COMPHY_SFT_RESET,\n+\t\t\t    SFT_RST_NO_REG, SFT_RST_NO_REG);\n+\n+\t/* COMPHY register reset (cleared automatically) */\n+\tcomphy_lane_reg_set(lane, COMPHY_SFT_RESET, SFT_RST, SFT_RST);\n+\n+\t/* PIPE soft and register reset */\n+\tdata = PIPE_SOFT_RESET | PIPE_REG_RESET;\n+\tmask = data;\n+\tcomphy_lane_reg_set(lane, COMPHY_PIPE_RST_CLK_CTRL, data, mask);\n+\n+\t/* Release PIPE register reset */\n+\tcomphy_lane_reg_set(lane, COMPHY_PIPE_RST_CLK_CTRL,\n+\t\t\t    0x0, PIPE_REG_RESET);\n+\n+\t/* Reset SB configuration register (only for lanes 0 and 1) */\n+\tif (lane->id == 0 || lane->id == 1) {\n+\t\tu32 mask, data;\n+\n+\t\tdata = PIN_RESET_CORE_BIT | PIN_RESET_COMPHY_BIT |\n+\t\t       PIN_PU_PLL_BIT | PIN_PU_RX_BIT | PIN_PU_TX_BIT;\n+\t\tmask = data | PIN_PU_IVREF_BIT | PIN_TX_IDLE_BIT;\n+\t\tcomphy_periph_reg_set(lane, COMPHY_PHY_CFG1, data, mask);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static bool mvebu_a3700_comphy_check_mode(int lane,\n \t\t\t\t\t  enum phy_mode mode,\n \t\t\t\t\t  int submode)\n {\n@@ -122,7 +1170,7 @@ static int mvebu_a3700_comphy_get_fw_mod\n \n \t/* Unused PHY mux value is 0x0 */\n \tif (mode == PHY_MODE_INVALID)\n-\t\treturn -EINVAL;\n+\t\treturn false;\n \n \tfor (i = 0; i < n; i++) {\n \t\tif (mvebu_a3700_comphy_modes[i].lane == lane &&\n@@ -132,27 +1180,30 @@ static int mvebu_a3700_comphy_get_fw_mod\n \t}\n \n \tif (i == n)\n-\t\treturn -EINVAL;\n+\t\treturn false;\n \n-\treturn mvebu_a3700_comphy_modes[i].fw_mode;\n+\treturn true;\n }\n \n static int mvebu_a3700_comphy_set_mode(struct phy *phy, enum phy_mode mode,\n \t\t\t\t       int submode)\n {\n \tstruct mvebu_a3700_comphy_lane *lane = phy_get_drvdata(phy);\n-\tint fw_mode;\n-\n-\tif (submode == PHY_INTERFACE_MODE_1000BASEX)\n-\t\tsubmode = PHY_INTERFACE_MODE_SGMII;\n \n-\tfw_mode = mvebu_a3700_comphy_get_fw_mode(lane->id, mode,\n-\t\t\t\t\t\t submode);\n-\tif (fw_mode < 0) {\n+\tif (!mvebu_a3700_comphy_check_mode(lane->id, mode, submode)) {\n \t\tdev_err(lane->dev, \"invalid COMPHY mode\\n\");\n-\t\treturn fw_mode;\n+\t\treturn -EINVAL;\n \t}\n \n+\t/* Mode cannot be changed while the PHY is powered on */\n+\tif (phy->power_count &&\n+\t    (lane->mode != mode || lane->submode != submode))\n+\t\treturn -EBUSY;\n+\n+\t/* If changing mode, ensure reset is called */\n+\tif (lane->mode != PHY_MODE_INVALID && lane->mode != mode)\n+\t\tlane->needs_reset = true;\n+\n \t/* Just remember the mode, ->power_on() will do the real setup */\n \tlane->mode = mode;\n \tlane->submode = submode;\n@@ -163,76 +1214,68 @@ static int mvebu_a3700_comphy_set_mode(s\n static int mvebu_a3700_comphy_power_on(struct phy *phy)\n {\n \tstruct mvebu_a3700_comphy_lane *lane = phy_get_drvdata(phy);\n-\tu32 fw_param;\n-\tint fw_mode;\n-\tint fw_port;\n \tint ret;\n \n-\tfw_mode = mvebu_a3700_comphy_get_fw_mode(lane->id,\n-\t\t\t\t\t\t lane->mode, lane->submode);\n-\tif (fw_mode < 0) {\n+\tif (!mvebu_a3700_comphy_check_mode(lane->id, lane->mode,\n+\t\t\t\t\t   lane->submode)) {\n \t\tdev_err(lane->dev, \"invalid COMPHY mode\\n\");\n-\t\treturn fw_mode;\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (lane->needs_reset) {\n+\t\tret = mvebu_a3700_comphy_reset(phy);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\n+\t\tlane->needs_reset = false;\n \t}\n \n \tswitch (lane->mode) {\n \tcase PHY_MODE_USB_HOST_SS:\n \t\tdev_dbg(lane->dev, \"set lane %d to USB3 host mode\\n\", lane->id);\n-\t\tfw_param = COMPHY_FW_MODE(fw_mode);\n-\t\tbreak;\n+\t\treturn mvebu_a3700_comphy_usb3_power_on(lane);\n \tcase PHY_MODE_SATA:\n \t\tdev_dbg(lane->dev, \"set lane %d to SATA mode\\n\", lane->id);\n-\t\tfw_param = COMPHY_FW_MODE(fw_mode);\n-\t\tbreak;\n+\t\treturn mvebu_a3700_comphy_sata_power_on(lane);\n \tcase PHY_MODE_ETHERNET:\n-\t\tfw_port = (lane->id == 0) ? 1 : 0;\n-\t\tswitch (lane->submode) {\n-\t\tcase PHY_INTERFACE_MODE_SGMII:\n-\t\t\tdev_dbg(lane->dev, \"set lane %d to SGMII mode\\n\",\n-\t\t\t\tlane->id);\n-\t\t\tfw_param = COMPHY_FW_NET(fw_mode, fw_port,\n-\t\t\t\t\t\t COMPHY_FW_SPEED_1_25G);\n-\t\t\tbreak;\n-\t\tcase PHY_INTERFACE_MODE_2500BASEX:\n-\t\t\tdev_dbg(lane->dev, \"set lane %d to 2500BASEX mode\\n\",\n-\t\t\t\tlane->id);\n-\t\t\tfw_param = COMPHY_FW_NET(fw_mode, fw_port,\n-\t\t\t\t\t\t COMPHY_FW_SPEED_3_125G);\n-\t\t\tbreak;\n-\t\tdefault:\n-\t\t\tdev_err(lane->dev, \"unsupported PHY submode (%d)\\n\",\n-\t\t\t\tlane->submode);\n-\t\t\treturn -ENOTSUPP;\n-\t\t}\n-\t\tbreak;\n+\t\tdev_dbg(lane->dev, \"set lane %d to Ethernet mode\\n\", lane->id);\n+\t\treturn mvebu_a3700_comphy_ethernet_power_on(lane);\n \tcase PHY_MODE_PCIE:\n \t\tdev_dbg(lane->dev, \"set lane %d to PCIe mode\\n\", lane->id);\n-\t\tfw_param = COMPHY_FW_PCIE(fw_mode, COMPHY_FW_SPEED_5G,\n-\t\t\t\t\t  phy->attrs.bus_width);\n-\t\tbreak;\n+\t\treturn mvebu_a3700_comphy_pcie_power_on(lane);\n \tdefault:\n \t\tdev_err(lane->dev, \"unsupported PHY mode (%d)\\n\", lane->mode);\n-\t\treturn -ENOTSUPP;\n+\t\treturn -EOPNOTSUPP;\n \t}\n-\n-\tret = mvebu_a3700_comphy_smc(COMPHY_SIP_POWER_ON, lane->id, fw_param);\n-\tif (ret == -EOPNOTSUPP)\n-\t\tdev_err(lane->dev,\n-\t\t\t\"unsupported SMC call, try updating your firmware\\n\");\n-\n-\treturn ret;\n }\n \n static int mvebu_a3700_comphy_power_off(struct phy *phy)\n {\n \tstruct mvebu_a3700_comphy_lane *lane = phy_get_drvdata(phy);\n \n-\treturn mvebu_a3700_comphy_smc(COMPHY_SIP_POWER_OFF, lane->id, 0);\n+\tswitch (lane->mode) {\n+\tcase PHY_MODE_USB_HOST_SS:\n+\t\tmvebu_a3700_comphy_usb3_power_off(lane);\n+\t\treturn 0;\n+\tcase PHY_MODE_SATA:\n+\t\tmvebu_a3700_comphy_sata_power_off(lane);\n+\t\treturn 0;\n+\tcase PHY_MODE_ETHERNET:\n+\t\tmvebu_a3700_comphy_ethernet_power_off(lane);\n+\t\treturn 0;\n+\tcase PHY_MODE_PCIE:\n+\t\tmvebu_a3700_comphy_pcie_power_off(lane);\n+\t\treturn 0;\n+\tdefault:\n+\t\tdev_err(lane->dev, \"invalid COMPHY mode\\n\");\n+\t\treturn -EINVAL;\n+\t}\n }\n \n static const struct phy_ops mvebu_a3700_comphy_ops = {\n \t.power_on\t= mvebu_a3700_comphy_power_on,\n \t.power_off\t= mvebu_a3700_comphy_power_off,\n+\t.reset\t\t= mvebu_a3700_comphy_reset,\n \t.set_mode\t= mvebu_a3700_comphy_set_mode,\n \t.owner\t\t= THIS_MODULE,\n };\n@@ -256,13 +1299,75 @@ static struct phy *mvebu_a3700_comphy_xl\n \t\treturn ERR_PTR(-EINVAL);\n \t}\n \n+\tlane->invert_tx = args->args[1] & BIT(0);\n+\tlane->invert_rx = args->args[1] & BIT(1);\n+\n \treturn phy;\n }\n \n static int mvebu_a3700_comphy_probe(struct platform_device *pdev)\n {\n+\tstruct mvebu_a3700_comphy_priv *priv;\n \tstruct phy_provider *provider;\n \tstruct device_node *child;\n+\tstruct resource *res;\n+\tstruct clk *clk;\n+\tint ret;\n+\n+\tpriv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);\n+\tif (!priv)\n+\t\treturn -ENOMEM;\n+\n+\tspin_lock_init(&priv->lock);\n+\n+\tres = platform_get_resource_byname(pdev, IORESOURCE_MEM, \"comphy\");\n+\tpriv->comphy_regs = devm_ioremap_resource(&pdev->dev, res);\n+\tif (IS_ERR(priv->comphy_regs))\n+\t\treturn PTR_ERR(priv->comphy_regs);\n+\n+\tres = platform_get_resource_byname(pdev, IORESOURCE_MEM,\n+\t\t\t\t\t   \"lane1_pcie_gbe\");\n+\tpriv->lane1_phy_regs = devm_ioremap_resource(&pdev->dev, res);\n+\tif (IS_ERR(priv->lane1_phy_regs))\n+\t\treturn PTR_ERR(priv->lane1_phy_regs);\n+\n+\tres = platform_get_resource_byname(pdev, IORESOURCE_MEM,\n+\t\t\t\t\t   \"lane0_usb3_gbe\");\n+\tpriv->lane0_phy_regs = devm_ioremap_resource(&pdev->dev, res);\n+\tif (IS_ERR(priv->lane0_phy_regs))\n+\t\treturn PTR_ERR(priv->lane0_phy_regs);\n+\n+\tres = platform_get_resource_byname(pdev, IORESOURCE_MEM,\n+\t\t\t\t\t   \"lane2_sata_usb3\");\n+\tpriv->lane2_phy_indirect = devm_ioremap_resource(&pdev->dev, res);\n+\tif (IS_ERR(priv->lane2_phy_indirect))\n+\t\treturn PTR_ERR(priv->lane2_phy_indirect);\n+\n+\t/*\n+\t * Driver needs to know if reference xtal clock is 40MHz or 25MHz.\n+\t * Old DT bindings do not have xtal clk present. So do not fail here\n+\t * and expects that default 25MHz reference clock is used.\n+\t */\n+\tclk = clk_get(&pdev->dev, \"xtal\");\n+\tif (IS_ERR(clk)) {\n+\t\tif (PTR_ERR(clk) == -EPROBE_DEFER)\n+\t\t\treturn -EPROBE_DEFER;\n+\t\tdev_warn(&pdev->dev, \"missing 'xtal' clk (%ld)\\n\",\n+\t\t\t PTR_ERR(clk));\n+\t} else {\n+\t\tret = clk_prepare_enable(clk);\n+\t\tif (ret) {\n+\t\t\tdev_warn(&pdev->dev, \"enabling xtal clk failed (%d)\\n\",\n+\t\t\t\t ret);\n+\t\t} else {\n+\t\t\tif (clk_get_rate(clk) == 40000000)\n+\t\t\t\tpriv->xtal_is_40m = true;\n+\t\t\tclk_disable_unprepare(clk);\n+\t\t}\n+\t\tclk_put(clk);\n+\t}\n+\n+\tdev_set_drvdata(&pdev->dev, priv);\n \n \tfor_each_available_child_of_node(pdev->dev.of_node, child) {\n \t\tstruct mvebu_a3700_comphy_lane *lane;\n@@ -277,7 +1382,7 @@ static int mvebu_a3700_comphy_probe(stru\n \t\t\tcontinue;\n \t\t}\n \n-\t\tif (lane_id >= MVEBU_A3700_COMPHY_LANES) {\n+\t\tif (lane_id >= 3) {\n \t\t\tdev_err(&pdev->dev, \"invalid 'reg' property\\n\");\n \t\t\tcontinue;\n \t\t}\n@@ -295,11 +1400,21 @@ static int mvebu_a3700_comphy_probe(stru\n \t\t\treturn PTR_ERR(phy);\n \t\t}\n \n+\t\tlane->priv = priv;\n \t\tlane->dev = &pdev->dev;\n \t\tlane->mode = PHY_MODE_INVALID;\n \t\tlane->submode = PHY_INTERFACE_MODE_NA;\n \t\tlane->id = lane_id;\n+\t\tlane->invert_tx = false;\n+\t\tlane->invert_rx = false;\n \t\tphy_set_drvdata(phy, lane);\n+\n+\t\t/*\n+\t\t * To avoid relying on the bootloader/firmware configuration,\n+\t\t * power off all comphys.\n+\t\t */\n+\t\tmvebu_a3700_comphy_reset(phy);\n+\t\tlane->needs_reset = false;\n \t}\n \n \tprovider = devm_of_phy_provider_register(&pdev->dev,\n@@ -323,5 +1438,7 @@ static struct platform_driver mvebu_a370\n module_platform_driver(mvebu_a3700_comphy_driver);\n \n MODULE_AUTHOR(\"Miquèl Raynal <miquel.raynal@bootlin.com>\");\n+MODULE_AUTHOR(\"Pali Rohár <pali@kernel.org>\");\n+MODULE_AUTHOR(\"Marek Behún <kabel@kernel.org>\");\n MODULE_DESCRIPTION(\"Common PHY driver for A3700\");\n MODULE_LICENSE(\"GPL v2\");\n"
  },
  {
    "path": "target/linux/generic/pending-5.15/851-0003-arm64-dts-marvell-armada-37xx-Add-xtal-clock-to-comp.patch",
    "content": "From 66c51c39fd4bf05e99debf0e71de5704231c57dc Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>\nDate: Thu, 23 Sep 2021 19:26:26 +0200\nSubject: [PATCH] arm64: dts: marvell: armada-37xx: Add xtal clock to comphy\n node\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nKernel driver phy-mvebu-a3700-comphy.c needs to know the rate of the\nreference xtal clock. So add missing xtal clock source into comphy device\ntree node. If the property is not present, the driver defaults to 25 MHz\nxtal rate (which, as far as we know, is used by all the existing boards).\n\nSigned-off-by: Pali Rohár <pali@kernel.org>\nSigned-off-by: Marek Behún <kabel@kernel.org>\n---\n arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 2 ++\n 1 file changed, 2 insertions(+)\n\n--- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi\n+++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi\n@@ -265,6 +265,8 @@\n \t\t\t\t\t    \"lane2_sata_usb3\";\n \t\t\t\t#address-cells = <1>;\n \t\t\t\t#size-cells = <0>;\n+\t\t\t\tclocks = <&xtalclk>;\n+\t\t\t\tclock-names = \"xtal\";\n \n \t\t\t\tcomphy0: phy@0 {\n \t\t\t\t\treg = <0>;\n"
  },
  {
    "path": "target/linux/generic/pending-5.15/851-0004-Revert-ata-ahci-mvebu-Make-SATA-PHY-optional-for-Arm.patch",
    "content": "From 750bb44dbbe9dfb4ba3e1f8a746b831b39ba3cd9 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>\nDate: Thu, 23 Sep 2021 19:35:57 +0200\nSubject: [PATCH] Revert \"ata: ahci: mvebu: Make SATA PHY optional for Armada\n 3720\"\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nThis reverts commit 45aefe3d2251e4e229d7662052739f96ad1d08d9.\n\nArmada 3720 PHY driver (phy-mvebu-a3700-comphy.c) does not return\n-EOPNOTSUPP from phy_power_on() callback anymore.\n\nSo remove AHCI_HFLAG_IGN_NOTSUPP_POWER_ON flag from Armada 3720 plat data.\n\nAHCI_HFLAG_IGN_NOTSUPP_POWER_ON is not used by any other ahci driver, so\nremove this flag completely.\n\nSigned-off-by: Pali Rohár <pali@kernel.org>\nSigned-off-by: Marek Behún <kabel@kernel.org>\nAcked-by: Miquel Raynal <miquel.raynal@bootlin.com>\n---\n drivers/ata/ahci.h             | 2 --\n drivers/ata/ahci_mvebu.c       | 2 +-\n drivers/ata/libahci_platform.c | 2 +-\n 3 files changed, 2 insertions(+), 4 deletions(-)\n\n--- a/drivers/ata/ahci.h\n+++ b/drivers/ata/ahci.h\n@@ -240,8 +240,6 @@ enum {\n \t\t\t\t\t\t\tas default lpm_policy */\n \tAHCI_HFLAG_SUSPEND_PHYS\t\t= (1 << 26), /* handle PHYs during\n \t\t\t\t\t\t\tsuspend/resume */\n-\tAHCI_HFLAG_IGN_NOTSUPP_POWER_ON\t= (1 << 27), /* ignore -EOPNOTSUPP\n-\t\t\t\t\t\t\tfrom phy_power_on() */\n \tAHCI_HFLAG_NO_SXS\t\t= (1 << 28), /* SXS not supported */\n \n \t/* ap->flags bits */\n--- a/drivers/ata/ahci_mvebu.c\n+++ b/drivers/ata/ahci_mvebu.c\n@@ -227,7 +227,7 @@ static const struct ahci_mvebu_plat_data\n \n static const struct ahci_mvebu_plat_data ahci_mvebu_armada_3700_plat_data = {\n \t.plat_config = ahci_mvebu_armada_3700_config,\n-\t.flags = AHCI_HFLAG_SUSPEND_PHYS | AHCI_HFLAG_IGN_NOTSUPP_POWER_ON,\n+\t.flags = AHCI_HFLAG_SUSPEND_PHYS,\n };\n \n static const struct of_device_id ahci_mvebu_of_match[] = {\n--- a/drivers/ata/libahci_platform.c\n+++ b/drivers/ata/libahci_platform.c\n@@ -59,7 +59,7 @@ int ahci_platform_enable_phys(struct ahc\n \t\t}\n \n \t\trc = phy_power_on(hpriv->phys[i]);\n-\t\tif (rc && !(rc == -EOPNOTSUPP && (hpriv->flags & AHCI_HFLAG_IGN_NOTSUPP_POWER_ON))) {\n+\t\tif (rc) {\n \t\t\tphy_exit(hpriv->phys[i]);\n \t\t\tgoto disable_phys;\n \t\t}\n"
  },
  {
    "path": "target/linux/generic/pending-5.15/851-0005-Revert-usb-host-xhci-mvebu-make-USB-3.0-PHY-optional.patch",
    "content": "From 9f0dfb279b1dd505d5e10b10e4a78a62030978d8 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>\nDate: Thu, 23 Sep 2021 19:40:06 +0200\nSubject: [PATCH] Revert \"usb: host: xhci: mvebu: make USB 3.0 PHY optional for\n Armada 3720\"\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nThis reverts commit 3241929b67d28c83945d3191c6816a3271fd6b85.\n\nArmada 3720 phy driver (phy-mvebu-a3700-comphy.c) does not return\n-EOPNOTSUPP from phy_power_on() callback anymore.\n\nSo remove XHCI_SKIP_PHY_INIT flag from xhci_mvebu_a3700_plat_setup() and\nthen also whole xhci_mvebu_a3700_plat_setup() function which is there just\nto handle -EOPNOTSUPP for XHCI_SKIP_PHY_INIT.\n\nxhci plat_setup callback is not used by any other xhci plat driver, so\nremove this callback completely.\n\nSigned-off-by: Pali Rohár <pali@kernel.org>\nSigned-off-by: Marek Behún <kabel@kernel.org>\nAcked-by: Miquel Raynal <miquel.raynal@bootlin.com>\n---\n drivers/usb/host/xhci-mvebu.c | 42 -----------------------------------\n drivers/usb/host/xhci-mvebu.h |  6 -----\n drivers/usb/host/xhci-plat.c  | 20 +----------------\n drivers/usb/host/xhci-plat.h  |  1 -\n 4 files changed, 1 insertion(+), 68 deletions(-)\n\n--- a/drivers/usb/host/xhci-mvebu.c\n+++ b/drivers/usb/host/xhci-mvebu.c\n@@ -8,7 +8,6 @@\n #include <linux/mbus.h>\n #include <linux/of.h>\n #include <linux/platform_device.h>\n-#include <linux/phy/phy.h>\n \n #include <linux/usb.h>\n #include <linux/usb/hcd.h>\n@@ -74,47 +73,6 @@ int xhci_mvebu_mbus_init_quirk(struct us\n \n \treturn 0;\n }\n-\n-int xhci_mvebu_a3700_plat_setup(struct usb_hcd *hcd)\n-{\n-\tstruct xhci_hcd *xhci = hcd_to_xhci(hcd);\n-\tstruct device *dev = hcd->self.controller;\n-\tstruct phy *phy;\n-\tint ret;\n-\n-\t/* Old bindings miss the PHY handle */\n-\tphy = of_phy_get(dev->of_node, \"usb3-phy\");\n-\tif (IS_ERR(phy) && PTR_ERR(phy) == -EPROBE_DEFER)\n-\t\treturn -EPROBE_DEFER;\n-\telse if (IS_ERR(phy))\n-\t\tgoto phy_out;\n-\n-\tret = phy_init(phy);\n-\tif (ret)\n-\t\tgoto phy_put;\n-\n-\tret = phy_set_mode(phy, PHY_MODE_USB_HOST_SS);\n-\tif (ret)\n-\t\tgoto phy_exit;\n-\n-\tret = phy_power_on(phy);\n-\tif (ret == -EOPNOTSUPP) {\n-\t\t/* Skip initializatin of XHCI PHY when it is unsupported by firmware */\n-\t\tdev_warn(dev, \"PHY unsupported by firmware\\n\");\n-\t\txhci->quirks |= XHCI_SKIP_PHY_INIT;\n-\t}\n-\tif (ret)\n-\t\tgoto phy_exit;\n-\n-\tphy_power_off(phy);\n-phy_exit:\n-\tphy_exit(phy);\n-phy_put:\n-\tof_phy_put(phy);\n-phy_out:\n-\n-\treturn 0;\n-}\n \n int xhci_mvebu_a3700_init_quirk(struct usb_hcd *hcd)\n {\n--- a/drivers/usb/host/xhci-mvebu.h\n+++ b/drivers/usb/host/xhci-mvebu.h\n@@ -12,18 +12,12 @@ struct usb_hcd;\n \n #if IS_ENABLED(CONFIG_USB_XHCI_MVEBU)\n int xhci_mvebu_mbus_init_quirk(struct usb_hcd *hcd);\n-int xhci_mvebu_a3700_plat_setup(struct usb_hcd *hcd);\n int xhci_mvebu_a3700_init_quirk(struct usb_hcd *hcd);\n #else\n static inline int xhci_mvebu_mbus_init_quirk(struct usb_hcd *hcd)\n {\n \treturn 0;\n }\n-\n-static inline int xhci_mvebu_a3700_plat_setup(struct usb_hcd *hcd)\n-{\n-\treturn 0;\n-}\n \n static inline int xhci_mvebu_a3700_init_quirk(struct usb_hcd *hcd)\n {\n--- a/drivers/usb/host/xhci-plat.c\n+++ b/drivers/usb/host/xhci-plat.c\n@@ -44,16 +44,6 @@ static void xhci_priv_plat_start(struct\n \t\tpriv->plat_start(hcd);\n }\n \n-static int xhci_priv_plat_setup(struct usb_hcd *hcd)\n-{\n-\tstruct xhci_plat_priv *priv = hcd_to_xhci_priv(hcd);\n-\n-\tif (!priv->plat_setup)\n-\t\treturn 0;\n-\n-\treturn priv->plat_setup(hcd);\n-}\n-\n static int xhci_priv_init_quirk(struct usb_hcd *hcd)\n {\n \tstruct xhci_plat_priv *priv = hcd_to_xhci_priv(hcd);\n@@ -121,7 +111,6 @@ static const struct xhci_plat_priv xhci_\n };\n \n static const struct xhci_plat_priv xhci_plat_marvell_armada3700 = {\n-\t.plat_setup = xhci_mvebu_a3700_plat_setup,\n \t.init_quirk = xhci_mvebu_a3700_init_quirk,\n };\n \n@@ -341,14 +330,7 @@ static int xhci_plat_probe(struct platfo\n \n \thcd->tpl_support = of_usb_host_tpl_support(sysdev->of_node);\n \txhci->shared_hcd->tpl_support = hcd->tpl_support;\n-\n-\tif (priv) {\n-\t\tret = xhci_priv_plat_setup(hcd);\n-\t\tif (ret)\n-\t\t\tgoto disable_usb_phy;\n-\t}\n-\n-\tif ((xhci->quirks & XHCI_SKIP_PHY_INIT) || (priv && (priv->quirks & XHCI_SKIP_PHY_INIT)))\n+\tif (priv && (priv->quirks & XHCI_SKIP_PHY_INIT))\n \t\thcd->skip_phy_initialization = 1;\n \n \tif (priv && (priv->quirks & XHCI_SG_TRB_CACHE_SIZE_QUIRK))\n--- a/drivers/usb/host/xhci-plat.h\n+++ b/drivers/usb/host/xhci-plat.h\n@@ -13,7 +13,6 @@\n struct xhci_plat_priv {\n \tconst char *firmware_name;\n \tunsigned long long quirks;\n-\tint (*plat_setup)(struct usb_hcd *);\n \tvoid (*plat_start)(struct usb_hcd *);\n \tint (*init_quirk)(struct usb_hcd *);\n \tint (*suspend_quirk)(struct usb_hcd *);\n"
  },
  {
    "path": "target/linux/generic/pending-5.15/851-0006-Revert-PCI-aardvark-Fix-initialization-with-old-Marv.patch",
    "content": "From 9a352062b7e3857742389dff6f64393481dc755e Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>\nDate: Thu, 23 Sep 2021 19:37:05 +0200\nSubject: [PATCH] Revert \"PCI: aardvark: Fix initialization with old Marvell's\n Arm Trusted Firmware\"\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nThis reverts commit b0c6ae0f8948a2be6bf4e8b4bbab9ca1343289b6.\n\nArmada 3720 phy driver (phy-mvebu-a3700-comphy.c) does not return\n-EOPNOTSUPP from phy_power_on() callback anymore.\n\nSo remove dead code which handles -EOPNOTSUPP return value.\n\nSigned-off-by: Pali Rohár <pali@kernel.org>\nSigned-off-by: Marek Behún <kabel@kernel.org>\nAcked-by: Miquel Raynal <miquel.raynal@bootlin.com>\n---\n drivers/pci/controller/pci-aardvark.c | 4 +---\n 1 file changed, 1 insertion(+), 3 deletions(-)\n\n--- a/drivers/pci/controller/pci-aardvark.c\n+++ b/drivers/pci/controller/pci-aardvark.c\n@@ -1622,9 +1622,7 @@ static int advk_pcie_enable_phy(struct a\n \t}\n \n \tret = phy_power_on(pcie->phy);\n-\tif (ret == -EOPNOTSUPP) {\n-\t\tdev_warn(&pcie->pdev->dev, \"PHY unsupported by firmware\\n\");\n-\t} else if (ret) {\n+\tif (ret) {\n \t\tphy_exit(pcie->phy);\n \t\treturn ret;\n \t}\n"
  },
  {
    "path": "target/linux/generic/pending-5.15/920-mangle_bootargs.patch",
    "content": "From: Imre Kaloz <kaloz@openwrt.org>\nSubject: init: add CONFIG_MANGLE_BOOTARGS and disable it by default\n\nEnabling this option renames the bootloader supplied root=\nand rootfstype= variables, which might have to be know but\nwould break the automatisms OpenWrt uses.\n\nSigned-off-by: Imre Kaloz <kaloz@openwrt.org>\n---\n init/Kconfig |  9 +++++++++\n init/main.c  | 24 ++++++++++++++++++++++++\n 2 files changed, 33 insertions(+)\n\n--- a/init/Kconfig\n+++ b/init/Kconfig\n@@ -1805,6 +1805,15 @@ config EMBEDDED\n \t  an embedded system so certain expert options are available\n \t  for configuration.\n \n+config MANGLE_BOOTARGS\n+\tbool \"Rename offending bootargs\"\n+\tdepends on EXPERT\n+\thelp\n+\t  Sometimes the bootloader passed bogus root= and rootfstype=\n+\t  parameters to the kernel, and while you want to ignore them,\n+\t  you need to know the values f.e. to support dual firmware\n+\t  layouts on the flash.\n+\n config HAVE_PERF_EVENTS\n \tbool\n \thelp\n--- a/init/main.c\n+++ b/init/main.c\n@@ -615,6 +615,29 @@ static inline void setup_nr_cpu_ids(void\n static inline void smp_prepare_cpus(unsigned int maxcpus) { }\n #endif\n \n+#ifdef CONFIG_MANGLE_BOOTARGS\n+static void __init mangle_bootargs(char *command_line)\n+{\n+\tchar *rootdev;\n+\tchar *rootfs;\n+\n+\trootdev = strstr(command_line, \"root=/dev/mtdblock\");\n+\n+\tif (rootdev)\n+\t\tstrncpy(rootdev, \"mangled_rootblock=\", 18);\n+\n+\trootfs = strstr(command_line, \"rootfstype\");\n+\n+\tif (rootfs)\n+\t\tstrncpy(rootfs, \"mangled_fs\", 10);\n+\n+}\n+#else\n+static void __init mangle_bootargs(char *command_line)\n+{\n+}\n+#endif\n+\n /*\n  * We need to store the untouched command line for future reference.\n  * We also need to store the touched command line since the parameter\n@@ -955,6 +978,7 @@ asmlinkage __visible void __init __no_sa\n \tpr_notice(\"%s\", linux_banner);\n \tearly_security_init();\n \tsetup_arch(&command_line);\n+\tmangle_bootargs(command_line);\n \tsetup_boot_config();\n \tsetup_command_line(command_line);\n \tsetup_nr_cpu_ids();\n"
  },
  {
    "path": "target/linux/imx/Makefile",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2013-2014 OpenWrt.org\n\ninclude $(TOPDIR)/rules.mk\n\nARCH:=arm\nBOARD:=imx\nBOARDNAME:=NXP i.MX\nFEATURES:=audio display fpu gpio pcie rtc usb usbgadget squashfs targz nand ubifs boot-part rootfs-part\nSUBTARGETS:=cortexa7 cortexa9\n\nKERNEL_PATCHVER:=5.15\n\ninclude $(INCLUDE_DIR)/target.mk\n\nKERNELNAME:=zImage dtbs\n\nDEFAULT_PACKAGES += uboot-envtools mkf2fs e2fsprogs blkid\n\n$(eval $(call BuildTarget))\n"
  },
  {
    "path": "target/linux/imx/base-files/etc/inittab",
    "content": "::sysinit:/etc/init.d/rcS S boot\n::shutdown:/etc/init.d/rcS K shutdown\n::askconsole:/usr/libexec/login.sh\ntty1::askfirst:/usr/libexec/login.sh\n"
  },
  {
    "path": "target/linux/imx/config-5.15",
    "content": "CONFIG_ALIGNMENT_TRAP=y\nCONFIG_ARCH_32BIT_OFF_T=y\nCONFIG_ARCH_HIBERNATION_POSSIBLE=y\nCONFIG_ARCH_KEEP_MEMBLOCK=y\nCONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y\nCONFIG_ARCH_MMAP_RND_BITS_MAX=15\nCONFIG_ARCH_MULTIPLATFORM=y\nCONFIG_ARCH_MULTI_V6_V7=y\nCONFIG_ARCH_MULTI_V7=y\nCONFIG_ARCH_MXC=y\nCONFIG_ARCH_NR_GPIO=0\nCONFIG_ARCH_OPTIONAL_KERNEL_RWX=y\nCONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y\nCONFIG_ARCH_SELECT_MEMORY_MODEL=y\nCONFIG_ARCH_SPARSEMEM_ENABLE=y\nCONFIG_ARCH_SUSPEND_POSSIBLE=y\nCONFIG_ARM=y\nCONFIG_ARM_ARCH_TIMER_EVTSTREAM=y\nCONFIG_ARM_CRYPTO=y\nCONFIG_ARM_ERRATA_754322=y\nCONFIG_ARM_ERRATA_764369=y\nCONFIG_ARM_ERRATA_775420=y\nCONFIG_ARM_ERRATA_814220=y\nCONFIG_ARM_HAS_SG_CHAIN=y\nCONFIG_ARM_HEAVY_MB=y\n# CONFIG_ARM_IMX_CPUFREQ_DT is not set\nCONFIG_ARM_L1_CACHE_SHIFT=6\nCONFIG_ARM_L1_CACHE_SHIFT_6=y\nCONFIG_ARM_PATCH_IDIV=y\nCONFIG_ARM_PATCH_PHYS_VIRT=y\nCONFIG_ARM_THUMB=y\nCONFIG_ARM_UNWIND=y\nCONFIG_ARM_VIRT_EXT=y\nCONFIG_ASN1=y\nCONFIG_ASSOCIATIVE_ARRAY=y\nCONFIG_ATA=y\nCONFIG_ATAGS=y\n# CONFIG_ATA_SFF is not set\nCONFIG_AUTO_ZRELADDR=y\nCONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y\nCONFIG_BLK_DEV_LOOP=y\nCONFIG_BLK_PM=y\nCONFIG_CACHE_L2X0=y\nCONFIG_CLKSRC_IMX_GPT=y\nCONFIG_CLKSRC_MMIO=y\n# CONFIG_CLK_IMX8MM is not set\n# CONFIG_CLK_IMX8MN is not set\n# CONFIG_CLK_IMX8MP is not set\n# CONFIG_CLK_IMX8MQ is not set\nCONFIG_CLONE_BACKWARDS=y\nCONFIG_CLZ_TAB=y\nCONFIG_COMMON_CLK=y\nCONFIG_COMPAT_32BIT_TIME=y\nCONFIG_CPUFREQ_DT=y\nCONFIG_CPUFREQ_DT_PLATDEV=y\nCONFIG_CPU_32v6K=y\nCONFIG_CPU_32v7=y\nCONFIG_CPU_ABRT_EV7=y\nCONFIG_CPU_CACHE_V7=y\nCONFIG_CPU_CACHE_VIPT=y\nCONFIG_CPU_COPY_V6=y\nCONFIG_CPU_CP15=y\nCONFIG_CPU_CP15_MMU=y\nCONFIG_CPU_FREQ=y\nCONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y\nCONFIG_CPU_FREQ_GOV_ATTR_SET=y\nCONFIG_CPU_FREQ_GOV_COMMON=y\nCONFIG_CPU_FREQ_GOV_CONSERVATIVE=y\nCONFIG_CPU_FREQ_GOV_ONDEMAND=y\nCONFIG_CPU_FREQ_GOV_PERFORMANCE=y\nCONFIG_CPU_FREQ_GOV_POWERSAVE=y\nCONFIG_CPU_FREQ_GOV_SCHEDUTIL=y\nCONFIG_CPU_FREQ_GOV_USERSPACE=y\nCONFIG_CPU_FREQ_STAT=y\nCONFIG_CPU_HAS_ASID=y\nCONFIG_CPU_PABRT_V7=y\nCONFIG_CPU_RMAP=y\nCONFIG_CPU_SPECTRE=y\nCONFIG_CPU_THERMAL=y\nCONFIG_CPU_THUMB_CAPABLE=y\nCONFIG_CPU_TLB_V7=y\nCONFIG_CPU_V7=y\nCONFIG_CRC16=y\nCONFIG_CRYPTO_AES_ARM=y\nCONFIG_CRYPTO_AES_ARM_BS=y\nCONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=y\nCONFIG_CRYPTO_AUTHENC=y\nCONFIG_CRYPTO_CBC=y\nCONFIG_CRYPTO_CHACHA20=y\nCONFIG_CRYPTO_CHACHA20_NEON=y\nCONFIG_CRYPTO_CRC32=y\nCONFIG_CRYPTO_CRC32C=y\nCONFIG_CRYPTO_CRC32_ARM_CE=y\nCONFIG_CRYPTO_CRYPTD=y\nCONFIG_CRYPTO_CTS=y\nCONFIG_CRYPTO_DEFLATE=y\nCONFIG_CRYPTO_DEV_FSL_CAAM=y\nCONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API=y\nCONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API_DESC=y\nCONFIG_CRYPTO_DEV_FSL_CAAM_COMMON=y\nCONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API=y\nCONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API_DESC=y\n# CONFIG_CRYPTO_DEV_FSL_CAAM_DEBUG is not set\n# CONFIG_CRYPTO_DEV_FSL_CAAM_INTC is not set\nCONFIG_CRYPTO_DEV_FSL_CAAM_JR=y\nCONFIG_CRYPTO_DEV_FSL_CAAM_PKC_API=y\nCONFIG_CRYPTO_DEV_FSL_CAAM_RINGSIZE=9\nCONFIG_CRYPTO_DEV_FSL_CAAM_RNG_API=y\nCONFIG_CRYPTO_DRBG=y\nCONFIG_CRYPTO_DRBG_HMAC=y\nCONFIG_CRYPTO_DRBG_MENU=y\nCONFIG_CRYPTO_ECB=y\nCONFIG_CRYPTO_ENGINE=y\nCONFIG_CRYPTO_HASH_INFO=y\nCONFIG_CRYPTO_HMAC=y\nCONFIG_CRYPTO_HW=y\nCONFIG_CRYPTO_JITTERENTROPY=y\nCONFIG_CRYPTO_LIB_CHACHA_GENERIC=y\nCONFIG_CRYPTO_LIB_DES=y\nCONFIG_CRYPTO_LIB_SHA256=y\nCONFIG_CRYPTO_LZO=y\nCONFIG_CRYPTO_RNG=y\nCONFIG_CRYPTO_RNG2=y\nCONFIG_CRYPTO_RNG_DEFAULT=y\nCONFIG_CRYPTO_RSA=y\nCONFIG_CRYPTO_SEQIV=y\nCONFIG_CRYPTO_SHA1=y\nCONFIG_CRYPTO_SHA1_ARM=y\nCONFIG_CRYPTO_SHA1_ARM_NEON=y\nCONFIG_CRYPTO_SHA256=y\nCONFIG_CRYPTO_SHA256_ARM=y\nCONFIG_CRYPTO_SHA512=y\nCONFIG_CRYPTO_SHA512_ARM=y\nCONFIG_CRYPTO_SIMD=y\nCONFIG_CRYPTO_XTS=y\nCONFIG_CRYPTO_ZSTD=y\nCONFIG_DCACHE_WORD_ACCESS=y\nCONFIG_DEBUG_LL_INCLUDE=\"mach/debug-macro.S\"\nCONFIG_DEBUG_MISC=y\nCONFIG_DECOMPRESS_BZIP2=y\nCONFIG_DECOMPRESS_GZIP=y\nCONFIG_DECOMPRESS_LZO=y\nCONFIG_DECOMPRESS_XZ=y\nCONFIG_DMADEVICES=y\nCONFIG_DMA_ENGINE=y\nCONFIG_DMA_OF=y\nCONFIG_DMA_OPS=y\nCONFIG_DMA_REMAP=y\nCONFIG_DMA_VIRTUAL_CHANNELS=y\nCONFIG_DTC=y\nCONFIG_EDAC_ATOMIC_SCRUB=y\nCONFIG_EDAC_SUPPORT=y\nCONFIG_ENCRYPTED_KEYS=y\nCONFIG_EXT4_FS=y\nCONFIG_EXT4_FS_POSIX_ACL=y\nCONFIG_EXT4_FS_SECURITY=y\nCONFIG_EXTCON=y\nCONFIG_EXTRA_FIRMWARE=\"imx/sdma/sdma-imx6q.bin\"\nCONFIG_EXTRA_FIRMWARE_DIR=\"firmware\"\nCONFIG_F2FS_FS=y\n# CONFIG_FEC is not set\nCONFIG_FIXED_PHY=y\nCONFIG_FIX_EARLYCON_MEM=y\n# CONFIG_FSL_DPAA2_SWITCH is not set\n# CONFIG_FSL_ENETC_IERB is not set\n# CONFIG_FSL_IMX8_DDR_PMU is not set\nCONFIG_FS_ENCRYPTION=y\nCONFIG_FS_ENCRYPTION_ALGS=y\nCONFIG_FS_IOMAP=y\nCONFIG_FS_MBCACHE=y\nCONFIG_FS_POSIX_ACL=y\nCONFIG_FWNODE_MDIO=y\nCONFIG_FW_LOADER_PAGED_BUF=y\nCONFIG_GENERIC_ALLOCATOR=y\nCONFIG_GENERIC_ARCH_TOPOLOGY=y\nCONFIG_GENERIC_BUG=y\nCONFIG_GENERIC_CLOCKEVENTS=y\nCONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y\nCONFIG_GENERIC_CPU_AUTOPROBE=y\nCONFIG_GENERIC_CPU_VULNERABILITIES=y\nCONFIG_GENERIC_EARLY_IOREMAP=y\nCONFIG_GENERIC_GETTIMEOFDAY=y\nCONFIG_GENERIC_IDLE_POLL_SETUP=y\nCONFIG_GENERIC_IRQ_CHIP=y\nCONFIG_GENERIC_IRQ_MULTI_HANDLER=y\nCONFIG_GENERIC_IRQ_SHOW=y\nCONFIG_GENERIC_IRQ_SHOW_LEVEL=y\nCONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y\nCONFIG_GENERIC_PCI_IOMAP=y\nCONFIG_GENERIC_PINCONF=y\nCONFIG_GENERIC_PINCTRL_GROUPS=y\nCONFIG_GENERIC_PINMUX_FUNCTIONS=y\nCONFIG_GENERIC_SCHED_CLOCK=y\nCONFIG_GENERIC_SMP_IDLE_THREAD=y\nCONFIG_GENERIC_STRNCPY_FROM_USER=y\nCONFIG_GENERIC_STRNLEN_USER=y\nCONFIG_GENERIC_TIME_VSYSCALL=y\nCONFIG_GENERIC_VDSO_32=y\n# CONFIG_GIANFAR is not set\nCONFIG_GLOB=y\nCONFIG_GPIOLIB=y\nCONFIG_GPIO_CDEV=y\nCONFIG_GPIO_GENERIC=y\nCONFIG_GPIO_MXC=y\nCONFIG_GRO_CELLS=y\nCONFIG_HANDLE_DOMAIN_IRQ=y\nCONFIG_HARDEN_BRANCH_PREDICTOR=y\nCONFIG_HARDIRQS_SW_RESEND=y\nCONFIG_HAS_DMA=y\nCONFIG_HAS_IOMEM=y\nCONFIG_HAS_IOPORT_MAP=y\nCONFIG_HAVE_ARM_ARCH_TIMER=y\nCONFIG_HAVE_SMP=y\nCONFIG_HWMON=y\nCONFIG_HW_RANDOM=y\nCONFIG_HZ_FIXED=0\nCONFIG_HZ_PERIODIC=y\nCONFIG_I2C=y\nCONFIG_I2C_BOARDINFO=y\nCONFIG_I2C_CHARDEV=y\nCONFIG_I2C_IMX=y\n# CONFIG_I2C_IMX_LPI2C is not set\nCONFIG_I2C_SLAVE=y\n# CONFIG_I2C_SLAVE_TESTUNIT is not set\nCONFIG_IMX2_WDT=y\n# CONFIG_IMX7ULP_WDT is not set\n# CONFIG_IMX8MM_THERMAL is not set\nCONFIG_IMX_DMA=y\n# CONFIG_IMX_GPCV2_PM_DOMAINS is not set\nCONFIG_IMX_INTMUX=y\nCONFIG_IMX_IRQSTEER=y\nCONFIG_IMX_SDMA=y\nCONFIG_IMX_THERMAL=y\n# CONFIG_IMX_WEIM is not set\nCONFIG_INITRAMFS_SOURCE=\"\"\nCONFIG_IO_URING=y\nCONFIG_IRQCHIP=y\nCONFIG_IRQ_DOMAIN=y\nCONFIG_IRQ_DOMAIN_HIERARCHY=y\nCONFIG_IRQ_FORCED_THREADING=y\nCONFIG_IRQ_WORK=y\nCONFIG_JBD2=y\n# CONFIG_JFFS2_FS is not set\nCONFIG_KEYS=y\nCONFIG_LIBFDT=y\nCONFIG_LOCK_DEBUGGING_SUPPORT=y\nCONFIG_LOCK_SPIN_ON_OWNER=y\nCONFIG_LZO_COMPRESS=y\nCONFIG_LZO_DECOMPRESS=y\nCONFIG_MDIO_BUS=y\nCONFIG_MDIO_DEVICE=y\nCONFIG_MDIO_DEVRES=y\nCONFIG_MEMFD_CREATE=y\nCONFIG_MFD_SYSCON=y\nCONFIG_MIGHT_HAVE_CACHE_L2X0=y\nCONFIG_MIGRATION=y\nCONFIG_MMC=y\nCONFIG_MMC_BLOCK=y\nCONFIG_MMC_CQHCI=y\n# CONFIG_MMC_MXC is not set\nCONFIG_MMC_SDHCI=y\n# CONFIG_MMC_SDHCI_ESDHC_IMX is not set\nCONFIG_MMC_SDHCI_PLTFM=y\nCONFIG_MODULES_USE_ELF_REL=y\nCONFIG_MPILIB=y\nCONFIG_MTD_NAND_CORE=y\nCONFIG_MTD_NAND_ECC=y\nCONFIG_MTD_NAND_ECC_SW_HAMMING=y\nCONFIG_MTD_NAND_GPMI_NAND=y\nCONFIG_MTD_RAW_NAND=y\nCONFIG_MTD_UBI=y\nCONFIG_MTD_UBI_BEB_LIMIT=20\nCONFIG_MTD_UBI_BLOCK=y\nCONFIG_MTD_UBI_WL_THRESHOLD=4096\nCONFIG_MUTEX_SPIN_ON_OWNER=y\n# CONFIG_MX3_IPU is not set\nCONFIG_MXC_CLK=y\nCONFIG_MXS_DMA=y\nCONFIG_NEED_DMA_MAP_STATE=y\nCONFIG_NEON=y\nCONFIG_NET_DEVLINK=y\nCONFIG_NET_DSA=y\nCONFIG_NET_DSA_TAG_DSA=y\nCONFIG_NET_DSA_TAG_DSA_COMMON=y\nCONFIG_NET_DSA_TAG_EDSA=y\nCONFIG_NET_FLOW_LIMIT=y\nCONFIG_NET_PTP_CLASSIFY=y\nCONFIG_NET_SELFTESTS=y\nCONFIG_NET_SWITCHDEV=y\nCONFIG_NLS=y\nCONFIG_NLS_CODEPAGE_437=y\nCONFIG_NR_CPUS=4\nCONFIG_NVMEM=y\n# CONFIG_NVMEM_IMX_IIM is not set\nCONFIG_NVMEM_IMX_OCOTP=y\n# CONFIG_NVMEM_SNVS_LPGPR is not set\nCONFIG_NVMEM_SYSFS=y\nCONFIG_OF=y\nCONFIG_OF_ADDRESS=y\nCONFIG_OF_EARLY_FLATTREE=y\nCONFIG_OF_FLATTREE=y\nCONFIG_OF_GPIO=y\nCONFIG_OF_IRQ=y\nCONFIG_OF_KOBJ=y\nCONFIG_OF_MDIO=y\nCONFIG_OLD_SIGACTION=y\nCONFIG_OLD_SIGSUSPEND3=y\nCONFIG_OUTER_CACHE=y\nCONFIG_OUTER_CACHE_SYNC=y\nCONFIG_PADATA=y\nCONFIG_PAGE_OFFSET=0x80000000\nCONFIG_PERF_USE_VMALLOC=y\nCONFIG_PGTABLE_LEVELS=2\nCONFIG_PHYLIB=y\nCONFIG_PHYLINK=y\nCONFIG_PINCTRL=y\n# CONFIG_PINCTRL_IMX8MM is not set\n# CONFIG_PINCTRL_IMX8MN is not set\n# CONFIG_PINCTRL_IMX8MP is not set\n# CONFIG_PINCTRL_IMX8MQ is not set\n# CONFIG_PINCTRL_IMX8ULP is not set\nCONFIG_PL310_ERRATA_769419=y\nCONFIG_PM=y\nCONFIG_PM_CLK=y\nCONFIG_PM_OPP=y\nCONFIG_PPS=y\nCONFIG_PTP_1588_CLOCK=y\nCONFIG_PTP_1588_CLOCK_OPTIONAL=y\nCONFIG_PWM=y\n# CONFIG_PWM_IMX1 is not set\nCONFIG_PWM_IMX27=y\n# CONFIG_PWM_IMX_TPM is not set\nCONFIG_PWM_SYSFS=y\nCONFIG_RAS=y\nCONFIG_RATIONAL=y\nCONFIG_RD_BZIP2=y\nCONFIG_RD_GZIP=y\nCONFIG_RD_LZO=y\nCONFIG_RD_XZ=y\nCONFIG_REGMAP=y\nCONFIG_REGMAP_MMIO=y\nCONFIG_REGULATOR=y\nCONFIG_REGULATOR_FIXED_VOLTAGE=y\nCONFIG_RESET_CONTROLLER=y\nCONFIG_RFS_ACCEL=y\nCONFIG_RPS=y\nCONFIG_RTC_CLASS=y\n# CONFIG_RTC_DRV_CMOS is not set\n# CONFIG_RTC_DRV_IMXDI is not set\n# CONFIG_RTC_DRV_MXC is not set\n# CONFIG_RTC_DRV_MXC_V2 is not set\nCONFIG_RTC_I2C_AND_SPI=y\nCONFIG_RWSEM_SPIN_ON_OWNER=y\nCONFIG_SCSI=y\nCONFIG_SCSI_COMMON=y\nCONFIG_SERIAL_8250_FSL=y\nCONFIG_SERIAL_IMX=y\nCONFIG_SERIAL_IMX_CONSOLE=y\nCONFIG_SERIAL_IMX_EARLYCON=y\nCONFIG_SERIAL_MCTRL_GPIO=y\nCONFIG_SGL_ALLOC=y\nCONFIG_SG_POOL=y\nCONFIG_SMP=y\nCONFIG_SMP_ON_UP=y\n# CONFIG_SND_SOC_IMX_CARD is not set\n# CONFIG_SND_SOC_IMX_HDMI is not set\nCONFIG_SOCK_RX_QUEUE_MAPPING=y\nCONFIG_SOC_BUS=y\n# CONFIG_SOC_IMX50 is not set\n# CONFIG_SOC_IMX51 is not set\n# CONFIG_SOC_IMX53 is not set\n# CONFIG_SOC_IMX6Q is not set\n# CONFIG_SOC_IMX6SL is not set\n# CONFIG_SOC_IMX6SLL is not set\n# CONFIG_SOC_IMX6SX is not set\n# CONFIG_SOC_IMX6UL is not set\n# CONFIG_SOC_IMX7D is not set\n# CONFIG_SOC_IMX7ULP is not set\n# CONFIG_SOC_IMX8M is not set\n# CONFIG_SOC_LS1021A is not set\n# CONFIG_SOC_VF610 is not set\nCONFIG_SPARSE_IRQ=y\nCONFIG_SPI=y\nCONFIG_SPI_BITBANG=y\n# CONFIG_SPI_FSL_LPSPI is not set\n# CONFIG_SPI_FSL_QUADSPI is not set\nCONFIG_SPI_IMX=y\nCONFIG_SPI_MASTER=y\nCONFIG_SRAM=y\nCONFIG_SRAM_EXEC=y\nCONFIG_SRCU=y\nCONFIG_STMP_DEVICE=y\nCONFIG_SWPHY=y\nCONFIG_SWP_EMULATE=y\nCONFIG_SYS_SUPPORTS_APM_EMULATION=y\nCONFIG_THERMAL=y\nCONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y\nCONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0\nCONFIG_THERMAL_GOV_STEP_WISE=y\nCONFIG_THERMAL_OF=y\nCONFIG_TICK_CPU_ACCOUNTING=y\nCONFIG_TIMER_OF=y\nCONFIG_TIMER_PROBE=y\nCONFIG_TREE_RCU=y\nCONFIG_TREE_SRCU=y\nCONFIG_UBIFS_FS=y\n# CONFIG_UCLAMP_TASK is not set\nCONFIG_UNCOMPRESS_INCLUDE=\"debug/uncompress.h\"\nCONFIG_UNWINDER_ARM=y\nCONFIG_USB=y\nCONFIG_USB_CHIPIDEA=y\nCONFIG_USB_CHIPIDEA_HOST=y\nCONFIG_USB_CHIPIDEA_IMX=y\nCONFIG_USB_CHIPIDEA_UDC=y\nCONFIG_USB_COMMON=y\nCONFIG_USB_EHCI_HCD=y\n# CONFIG_USB_EHCI_HCD_PLATFORM is not set\nCONFIG_USB_GADGET=y\nCONFIG_USB_MXS_PHY=y\nCONFIG_USB_OTG=y\nCONFIG_USB_PHY=y\nCONFIG_USB_ROLE_SWITCH=y\nCONFIG_USB_SUPPORT=y\nCONFIG_USB_ULPI_BUS=y\nCONFIG_USE_OF=y\nCONFIG_VFP=y\nCONFIG_VFPv3=y\nCONFIG_VMSPLIT_2G=y\n# CONFIG_VMSPLIT_3G is not set\nCONFIG_WATCHDOG_CORE=y\nCONFIG_XPS=y\nCONFIG_XXHASH=y\nCONFIG_XZ_DEC_ARM=y\nCONFIG_XZ_DEC_ARMTHUMB=y\nCONFIG_XZ_DEC_BCJ=y\nCONFIG_ZBOOT_ROM_BSS=0\nCONFIG_ZBOOT_ROM_TEXT=0\nCONFIG_ZLIB_DEFLATE=y\nCONFIG_ZLIB_INFLATE=y\nCONFIG_ZSTD_COMPRESS=y\nCONFIG_ZSTD_DECOMPRESS=y\n"
  },
  {
    "path": "target/linux/imx/cortexa7/base-files/etc/board.d/02_network",
    "content": ". /lib/functions/uci-defaults.sh\n\nboard=$(board_name)\n\nboard_config_update\n\ncase \"$board\" in\n*)\n\tucidef_set_interfaces_lan_wan \"eth0\" \"eth1\"\n\t;;\nesac\n\nboard_config_flush\n\nexit 0\n"
  },
  {
    "path": "target/linux/imx/cortexa7/base-files/lib/upgrade/platform.sh",
    "content": "PART_NAME=firmware\nREQUIRE_IMAGE_METADATA=1\n\nplatform_check_image() {\n\treturn 0\n}\n\nplatform_do_upgrade() {\n\tlocal board=$(board_name)\n\n\tcase \"$board\" in\n\t*)\n\t\tdefault_do_upgrade \"$1\"\n\t\t;;\n\tesac\n}\n"
  },
  {
    "path": "target/linux/imx/cortexa7/config-default",
    "content": "CONFIG_ARM_CPU_SUSPEND=y\nCONFIG_ARM_GIC=y\nCONFIG_CLK_IMX6UL=y\nCONFIG_CMA=y\nCONFIG_CMA_AREAS=7\n# CONFIG_CMA_DEBUG is not set\n# CONFIG_CMA_DEBUGFS is not set\n# CONFIG_CMA_SYSFS is not set\nCONFIG_CONTIG_ALLOC=y\n# CONFIG_DMA_CMA is not set\nCONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y\nCONFIG_HW_RANDOM_IMX_RNGC=y\nCONFIG_JFFS2_FS=y\nCONFIG_LEDS_GPIO=y\nCONFIG_MEMORY_ISOLATION=y\nCONFIG_MTD_SPI_NOR=y\nCONFIG_MTD_SPLIT_FIRMWARE=y\nCONFIG_MTD_SPLIT_FIT_FW=y\nCONFIG_PINCTRL_IMX=y\nCONFIG_PINCTRL_IMX6UL=y\nCONFIG_PM_GENERIC_DOMAINS=y\nCONFIG_PM_GENERIC_DOMAINS_OF=y\nCONFIG_SOC_IMX6=y\nCONFIG_SOC_IMX6UL=y\nCONFIG_SPI_FSL_QUADSPI=y\nCONFIG_SPI_MEM=y\nCONFIG_USB_CHIPIDEA_IMX=y\nCONFIG_USB_EHCI_MXC=y\n"
  },
  {
    "path": "target/linux/imx/cortexa7/target.mk",
    "content": "BOARDNAME:=NXP i.MX with Cortex-A7\nCPU_TYPE:=cortex-a7\nCPU_SUBTYPE:=neon-vfpv4\n\ndefine Target/Description\n\tBuild firmware images for NXP i.MX (Cortex-A7) based boards.\nendef\n"
  },
  {
    "path": "target/linux/imx/cortexa9/base-files/etc/board.d/02_network",
    "content": "#\n# Copyright (C) 2013-2015 OpenWrt.org\n#\n\n. /lib/functions/uci-defaults.sh\n\nboard=$(board_name)\n\nboard_config_update\n\ncase \"$board\" in\ngw,imx6dl-gw51xx|\\\ngw,imx6dl-gw52xx|\\\ngw,imx6dl-gw5904|\\\ngw,imx6dl-gw5907|\\\ngw,imx6dl-gw5910|\\\ngw,imx6dl-gw5912|\\\ngw,imx6dl-gw5913|\\\ngw,imx6q-gw51xx|\\\ngw,imx6q-gw52xx|\\\ngw,imx6q-gw5904|\\\ngw,imx6q-gw5907|\\\ngw,imx6q-gw5910|\\\ngw,imx6q-gw5912|\\\ngw,imx6q-gw5913|\\\nsolidrun,cubox-i/dl|\\\nsolidrun,cubox-i/q)\n\tucidef_set_interface_lan 'eth0'\n\t;;\ngw,imx6dl-gw53xx|\\\ngw,imx6dl-gw54xx|\\\ngw,imx6dl-gw552x|\\\ngw,imx6q-gw53xx|\\\ngw,imx6q-gw5400-a|\\\ngw,imx6q-gw54xx|\\\ngw,imx6q-gw552x)\n\tucidef_set_interfaces_lan_wan 'eth0' 'eth1'\n\t;;\nwand,imx6dl-wandboard)\n\tucidef_set_interface_wan 'eth0'\n\t;;\nesac\n\nboard_config_flush\n\nexit 0\n"
  },
  {
    "path": "target/linux/imx/cortexa9/base-files/lib/imx.sh",
    "content": "#\n# Copyright (C) 2010-2013 OpenWrt.org\n#\n\nrootpartuuid() {\n\tlocal cmdline=$(cat /proc/cmdline)\n\tlocal bootpart=${cmdline##*root=}\n\tbootpart=${bootpart%% *}\n\tlocal uuid=${bootpart#PARTUUID=}\n\techo ${uuid%-02}\n}\n\nbootdev_from_uuid() {\n\tblkid | grep \"PTUUID=\\\"$(rootpartuuid)\\\"\" | cut -d : -f1\n}\n\nbootpart_from_uuid() {\n\tblkid | grep $(rootpartuuid)-01 | cut -d : -f1\n}\n\nrootpart_from_uuid() {\n\tblkid | grep $(rootpartuuid)-02 | cut -d : -f1\n}\n\napalis_mount_boot() {\n\tmkdir -p /boot\n\t[ -f /boot/uImage ] || {\n\t\tmount -o rw,noatime $(bootpart_from_uuid) /boot > /dev/null\n\t}\n}\n"
  },
  {
    "path": "target/linux/imx/cortexa9/base-files/lib/preinit/79_move_config",
    "content": ". /lib/imx.sh\n. /lib/functions.sh\n. /lib/upgrade/common.sh\n\nmove_config() {\n\tlocal board=$(board_name)\n\n\tcase \"$board\" in\n\ttoradex,apalis_imx6q-eval|\\\n\ttoradex,apalis_imx6q-ixora|\\\n\ttoradex,apalis_imx6q-ixora-v1.1)\n\t\tif [ -b $(bootpart_from_uuid) ]; then\n\t\t\tapalis_mount_boot\n\t\t\t[ -f \"/boot/$BACKUP_FILE\" ] && mv -f \"/boot/$BACKUP_FILE\" /\n\t\t\tumount /boot\n\t\tfi\n\t\t;;\n\tesac\n}\n\nboot_hook_add preinit_mount_root move_config\n"
  },
  {
    "path": "target/linux/imx/cortexa9/base-files/lib/upgrade/platform.sh",
    "content": "#\n# Copyright (C) 2010-2015 OpenWrt.org\n#\n\n. /lib/imx.sh\n\nRAMFS_COPY_BIN='blkid jffs2reset'\n\nenable_image_metadata_check() {\n\tcase \"$(board_name)\" in\n\ttoradex,apalis_imx6q-eval|\\\n\ttoradex,apalis_imx6q-ixora|\\\n\ttoradex,apalis_imx6q-ixora-v1.1)\n\t\tREQUIRE_IMAGE_METADATA=1\n\t\t;;\n\tesac\n}\nenable_image_metadata_check\n\napalis_copy_config() {\n\tapalis_mount_boot\n\tcp -af \"$UPGRADE_BACKUP\" \"/boot/$BACKUP_FILE\"\n\tsync\n\tumount /boot\n}\n\napalis_do_upgrade() {\n\tapalis_mount_boot\n\tget_image \"$1\" | tar Oxf - sysupgrade-apalis/kernel > /boot/uImage\n\tget_image \"$1\" | tar Oxf - sysupgrade-apalis/root > $(rootpart_from_uuid)\n\tsync\n\tumount /boot\n}\n\nplatform_check_image() {\n\tlocal board=$(board_name)\n\n\tcase \"$board\" in\n\tgw,imx6dl-gw51xx|\\\n\tgw,imx6dl-gw52xx|\\\n\tgw,imx6dl-gw53xx|\\\n\tgw,imx6dl-gw54xx|\\\n\tgw,imx6dl-gw551x|\\\n\tgw,imx6dl-gw552x|\\\n\tgw,imx6dl-gw553x|\\\n\tgw,imx6dl-gw5904|\\\n\tgw,imx6dl-gw5907|\\\n\tgw,imx6dl-gw5910|\\\n\tgw,imx6dl-gw5912|\\\n\tgw,imx6dl-gw5913|\\\n\tgw,imx6q-gw51xx|\\\n\tgw,imx6q-gw52xx|\\\n\tgw,imx6q-gw53xx|\\\n\tgw,imx6q-gw5400-a|\\\n\tgw,imx6q-gw54xx|\\\n\tgw,imx6q-gw551x|\\\n\tgw,imx6q-gw552x|\\\n\tgw,imx6q-gw553x|\\\n\tgw,imx6q-gw5904|\\\n\tgw,imx6q-gw5907|\\\n\tgw,imx6q-gw5910|\\\n\tgw,imx6q-gw5912|\\\n\tgw,imx6q-gw5913)\n\t\tnand_do_platform_check $board $1\n\t\treturn $?;\n\t\t;;\n\ttoradex,apalis_imx6q-eval|\\\n\ttoradex,apalis_imx6q-ixora|\\\n\ttoradex,apalis_imx6q-ixora-v1.1)\n\t\treturn 0\n\t\t;;\n\tesac\n\n\techo \"Sysupgrade is not yet supported on $board.\"\n\treturn 1\n}\n\nplatform_do_upgrade() {\n\tlocal board=$(board_name)\n\n\tcase \"$board\" in\n\tgw,imx6dl-gw51xx|\\\n\tgw,imx6dl-gw52xx|\\\n\tgw,imx6dl-gw53xx|\\\n\tgw,imx6dl-gw54xx|\\\n\tgw,imx6dl-gw551x|\\\n\tgw,imx6dl-gw552x|\\\n\tgw,imx6dl-gw553x|\\\n\tgw,imx6dl-gw5904|\\\n\tgw,imx6dl-gw5907|\\\n\tgw,imx6dl-gw5910|\\\n\tgw,imx6dl-gw5912|\\\n\tgw,imx6dl-gw5913|\\\n\tgw,imx6q-gw51xx|\\\n\tgw,imx6q-gw52xx|\\\n\tgw,imx6q-gw53xx|\\\n\tgw,imx6q-gw5400-a|\\\n\tgw,imx6q-gw54xx|\\\n\tgw,imx6q-gw551x|\\\n\tgw,imx6q-gw552x|\\\n\tgw,imx6q-gw553x|\\\n\tgw,imx6q-gw5904|\\\n\tgw,imx6q-gw5907|\\\n\tgw,imx6q-gw5910|\\\n\tgw,imx6q-gw5912|\\\n\tgw,imx6q-gw5913)\n\t\tnand_do_upgrade \"$1\"\n\t\t;;\n\ttoradex,apalis_imx6q-eval|\\\n\ttoradex,apalis_imx6q-ixora|\\\n\ttoradex,apalis_imx6q-ixora-v1.1)\n\t\tapalis_do_upgrade \"$1\"\n\t\t;;\n\tesac\n}\n\nplatform_copy_config() {\n\tlocal board=$(board_name)\n\n\tcase \"$board\" in\n\ttoradex,apalis_imx6q-eval|\\\n\ttoradex,apalis_imx6q-ixora|\\\n\ttoradex,apalis_imx6q-ixora-v1.1)\n\t\tapalis_copy_config\n\t\t;;\n\tesac\n}\n\nplatform_pre_upgrade() {\n\tlocal board=$(board_name)\n\n\tcase \"$board\" in\n\ttoradex,apalis_imx6q-eval|\\\n\ttoradex,apalis_imx6q-ixora|\\\n\ttoradex,apalis_imx6q-ixora-v1.1)\n\t\t[ -z \"$UPGRADE_BACKUP\" ] && {\n\t\t\tjffs2reset -y\n\t\t\tumount /overlay\n\t\t}\n\t\t;;\n\tesac\n}\n"
  },
  {
    "path": "target/linux/imx/cortexa9/config-default",
    "content": "CONFIG_AHCI_IMX=y\nCONFIG_ARM_CPU_SUSPEND=y\nCONFIG_ARM_GIC=y\nCONFIG_ARM_IMX6Q_CPUFREQ=y\nCONFIG_ATA_SFF=y\nCONFIG_BLK_MQ_PCI=y\nCONFIG_CLK_IMX6Q=y\nCONFIG_CLK_IMX6SL=y\nCONFIG_CLK_IMX6SX=y\nCONFIG_CMDLINE=\"pci=nomsi\"\nCONFIG_CMDLINE_EXTEND=y\nCONFIG_E1000E=y\nCONFIG_FEC=y\nCONFIG_FSL_GUTS=y\nCONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y\nCONFIG_GENERIC_MSI_IRQ=y\nCONFIG_GENERIC_MSI_IRQ_DOMAIN=y\nCONFIG_GPIOLIB_IRQCHIP=y\nCONFIG_GPIO_PCA953X=y\nCONFIG_GPIO_PCA953X_IRQ=y\nCONFIG_HW_RANDOM_IMX_RNGC=y\n# CONFIG_INITRAMFS_FORCE is not set\nCONFIG_MARVELL_PHY=y\nCONFIG_MICREL_PHY=y\nCONFIG_MMC_SDHCI_ESDHC_IMX=y\nCONFIG_MMC_SDHCI_IO_ACCESSORS=y\nCONFIG_MMC_SDHCI_OF_ESDHC=y\n# CONFIG_MMC_SDHCI_PCI is not set\nCONFIG_NET_DSA_MV88E6XXX=y\nCONFIG_PCI=y\nCONFIG_PCIEAER=y\nCONFIG_PCIEPORTBUS=y\nCONFIG_PCIE_DW=y\nCONFIG_PCIE_DW_HOST=y\nCONFIG_PCIE_PME=y\nCONFIG_PCI_DOMAINS=y\nCONFIG_PCI_DOMAINS_GENERIC=y\nCONFIG_PCI_IMX6=y\nCONFIG_PCI_MSI=y\nCONFIG_PCI_MSI_IRQ_DOMAIN=y\nCONFIG_PINCTRL_IMX=y\nCONFIG_PINCTRL_IMX6Q=y\nCONFIG_PINCTRL_IMX6SL=y\nCONFIG_PINCTRL_IMX6SX=y\nCONFIG_PM_GENERIC_DOMAINS=y\nCONFIG_PM_GENERIC_DOMAINS_OF=y\nCONFIG_REGMAP_I2C=y\nCONFIG_REGULATOR_ANATOP=y\nCONFIG_REGULATOR_LTC3676=y\nCONFIG_REGULATOR_PFUZE100=y\nCONFIG_RTC_DRV_DS1307=y\nCONFIG_RTC_DRV_DS1672=y\nCONFIG_SATA_HOST=y\nCONFIG_SENSORS_AD7418=y\nCONFIG_SOC_IMX6=y\nCONFIG_SOC_IMX6Q=y\nCONFIG_SOC_IMX6SL=y\nCONFIG_SOC_IMX6SX=y\n"
  },
  {
    "path": "target/linux/imx/cortexa9/target.mk",
    "content": "BOARDNAME:=NXP i.MX with Cortex-A9\nCPU_TYPE:=cortex-a9\nCPU_SUBTYPE:=neon\n\ndefine Target/Description\n\tBuild firmware images for NXP i.MX (Cortex-A9) based boards.\nendef\n"
  },
  {
    "path": "target/linux/imx/image/Makefile",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2013 OpenWrt.org\n\ninclude $(TOPDIR)/rules.mk\ninclude $(INCLUDE_DIR)/image.mk\n\ninclude $(SUBTARGET).mk\n\n$(eval $(call BuildImage))\n"
  },
  {
    "path": "target/linux/imx/image/bootscript-solidrun_cubox-i",
    "content": "echo \"CuBox OpenWrt Boot script\"\n\n# Set console variable for both UART and HDMI\nsetenv console console=ttymxc0,115200 video=mxcfb0:dev=hdmi,1920x1080M@60,if=RGB24,bpp=32\n\n# Find correct dtb\nif test ${board_rev} = MX6DL; then\n\tsetenv fdt_soc_type imx6dl;\nelif test ${board_rev} = MX6Q; then\n\tsetenv fdt_soc_type imx6q;\nfi\nif test ${board_name} = CUBOXI; then\n\tsetenv fdt_name ${fdt_soc_type}-cubox-i.dtb;\nelif test ${board_name} = HUMMINGBOARD; then\n\tsetenv fdt_name ${fdt_soc_type}-hummingboard.dtb;\nfi\n\n# Set correct devtype and partition\nif test ${devtype} != mmc; then setenv devtype mmc; fi\nif mmc dev 0; then\n\tsetenv mmcdev 0\nelif mmc dev 1; then\n\tsetenv mmcdev 1\nfi\n\n# Boot from the SD card is supported at the moment\nsetenv bootargs \"${console} root=/dev/mmcblk1p2 rw rootwait\"\nmmc dev ${mmcdev}\nload ${devtype} ${mmcdev}:${devplist} ${kernel_addr_r} /uImage\nload ${devtype} ${mmcdev}:${devplist} ${fdt_addr_r} /${fdt_name}\nbootz ${kernel_addr_r} - ${fdt_addr_r}\n"
  },
  {
    "path": "target/linux/imx/image/bootscript-toradex_apalis",
    "content": "echo \"Toradex Apalis OpenWrt Boot script v1.1\"\n\nsetenv mmcdev 0\nsetenv mmcrootpart 2\npart uuid mmc ${mmcdev}:${mmcrootpart} uuid\n\nsetenv nextcon 0\nsetenv boot_file uImage\nsetenv fdt_file imx6q-apalis-ixora.dtb\nsetenv root root=PARTUUID=${uuid} rootfstype=squashfs rootwait\nsetenv bootargs earlyprintk console=${console},${baudrate}n8 ${root}\nsetenv fsload ext4load mmc ${mmcdev}:${mmcbootpart}\n\nif ${fsload} ${kernel_addr_r} ${boot_file}; then\n\tif ${fsload} ${fdt_addr_r} ${fdt_file}; then\n\t\ttest -n \"$fdt_fixup\" && run fdt_fixup\n\t\tbootm ${kernel_addr_r} - ${fdt_addr_r}\n\telse\n\t\techo \"Error loading device-tree\"\n\tfi\nelse\n\techo \"Error loading kernel image\"\nfi\n"
  },
  {
    "path": "target/linux/imx/image/bootscript-ventana",
    "content": "echo \"Gateworks Ventana OpenWrt Boot script v1.02\"\n\n# set some defaults\n# set some defaults\ntest -n \"$fs\"    || fs=ext2\ntest -n \"$disk\"  || disk=0\nsetenv nextcon 0\nsetenv bootargs console=${console},${baudrate}\nsetenv loadaddr 10800000\nsetenv fdt_addr 18000000\n\n# detect dtype by looking for kernel on media the bootloader\n# has mounted (in order of preference: usb/mmc/sata)\n#\n# This assumes the bootloader has already started the respective subsystem\n# or mounted the filesystem if appropriate to get to this bootscript\n#\n# To Speed up boot set dtype manually\nif test -n \"$dtype\" ; then\n\techo \"Using dtype from env: $dtype\"\nelse\n\techo \"Detecting boot device (dtype)...\"\n\tif ${fs}load usb ${disk}:1 ${loadaddr} ${bootdir}/uImage ; then\n\t\tdtype=usb\n\telif ${fs}load mmc ${disk}:1 ${loadaddr} ${bootdir}/uImage ; then\n\t\tdtype=mmc\n\telif ${fs}load sata ${disk}:1 ${loadaddr} ${bootdir}/uImage ; then\n\t\tdtype=sata\n\telif ubifsload ${loadaddr} ${bootdir}/uImage ; then\n\t\tdtype=nand\n\tfi\n\techo \"detected dtype:$dtype\"\nfi\n\necho \"Booting from ${dtype}...\"\nif itest.s \"x${dtype}\" == \"xnand\" ; then\n\t# fix partition name\n\t#  OpenWrt kernel bug prevents partition name of 'rootfs' from booting\n\t#  instead name the partition ubi which is what is looked for by\n\t#  procd sysupgrade\n\tmtdparts del rootfs && mtdparts add nand0 - ubi\n\techo \"mtdparts:${mtdparts}\"\n\tsetenv fsload ubifsload\n\tsetenv root \"ubi0:ubi ubi.mtd=2 rootfstype=squashfs,ubifs\"\nelse\n\tsetenv fsload \"${fs}load ${dtype} ${disk}:1\"\n\tpart uuid ${dtype} ${disk}:1 uuid\n\tif test -z \"${uuid}\"; then\n\t\t# fallback to bootdev\n\t\tif test -n \"$bootdev\" ; then\n\t\t\techo \"Using bootdev from env: $bootdev\"\n\t\telse\n\t\t\tif itest.s \"x${dtype}\" == \"xmmc\" ; then\n\t\t\t\tbootdev=mmcblk0p1\n\t\t\telse\n\t\t\t\tbootdev=sda1\n\t\t\tfi\n\t\tfi\n\t\tsetenv root \"root=/dev/${bootdev}\"\n\telse\n\t\tsetenv root \"root=PARTUUID=${uuid}\"\n\tfi\n\tsetenv root \"$root rootfstype=${fs} rootwait rw\"\nfi\n\nsetenv bootargs \"${bootargs}\" \"${root}\" \"${video}\" \"${extra}\"\nif ${fsload} ${loadaddr} ${bootdir}/uImage; then\n\tif ${fsload} ${fdt_addr} ${bootdir}/${fdt_file}; then\n\t\techo Loaded DTB from ${bootdir}/${fdt_file}\n\t\ttest -n \"$fixfdt\" && run fixfdt\n\t\tbootm ${loadaddr} - ${fdt_addr}\n\telif ${fsload} ${fdt_addr} ${bootdir}/${fdt_file1}; then\n\t\techo Loaded DTB from ${bootdir}/${fdt_file1}\n\t\ttest -n \"$fixfdt\" && run fixfdt\n\t\tbootm ${loadaddr} - ${fdt_addr}\n\telif ${fsload} ${fdt_addr} ${bootdir}/${fdt_file2}; then\n\t\techo Loaded DTB from ${bootdir}/${fdt_file2}\n\t\ttest -n \"$fixfdt\" && run fixfdt\n\t\tbootm ${loadaddr} - ${fdt_addr}\n\telse\n\t\techo \"Error loading device-tree\"\n\tfi\nelse\n\techo \"Error loading kernel image\"\nfi\n"
  },
  {
    "path": "target/linux/imx/image/cortexa7.mk",
    "content": "define Device/Default\n  PROFILES := Default\n  FILESYSTEMS := squashfs ext4\n  KERNEL_INSTALL := 1\n  KERNEL_SUFFIX := -uImage\n  KERNEL_NAME := zImage\n  KERNEL := kernel-bin | uImage none\n  KERNEL_LOADADDR := 0x80008000\n  IMAGES :=\nendef\n"
  },
  {
    "path": "target/linux/imx/image/cortexa9.mk",
    "content": "DEVICE_VARS += MKUBIFS_OPTS UBOOT\n\ndefine Build/boot-overlay\n\trm -rf $@.boot\n\tmkdir -p $@.boot\n\n\t$(CP) $@ $@.boot/$(IMG_PREFIX)-uImage\n\tln -sf $(IMG_PREFIX)-uImage $@.boot/uImage\n\n\t$(foreach dts,$(DEVICE_DTS), \\\n\t\t$(CP) \\\n\t\t\t$(DTS_DIR)/$(dts).dtb \\\n\t\t\t$@.boot/$(IMG_PREFIX)-$(dts).dtb; \\\n\t\tln -sf \\\n\t\t\t$(IMG_PREFIX)-$(dts).dtb \\\n\t\t\t$@.boot/$(dts).dtb; \\\n\t)\n\tmkimage -A arm -O linux -T script -C none -a 0 -e 0 \\\n\t\t-n '$(DEVICE_ID) OpenWrt bootscript' \\\n\t\t-d ./bootscript-$(DEVICE_NAME) \\\n\t\t$@.boot/6x_bootscript-$(DEVICE_NAME)\n\n\t$(STAGING_DIR_HOST)/bin/mkfs.ubifs \\\n\t\t--space-fixup --compr=zlib --squash-uids \\\n\t\t$(MKUBIFS_OPTS) -c 16248 \\\n\t\t-o $@.boot.ubifs -d $@.boot\n\n\t$(TAR) -C $@.boot -cf $@.boot.tar .\nendef\n\ndefine Build/bootfs.tar.gz\n\trm -rf $@.boot\n\tmkdir -p $@.boot\n\n\t$(TAR) -C $@.boot -xf $(IMAGE_KERNEL).boot.tar\n\t$(TAR) -C $@.boot \\\n\t\t--numeric-owner --owner=0 --group=0 --transform \"s,./,./boot/,\" \\\n\t\t-czvf $@ .\nendef\n\ndefine Build/recovery-scr\n\tmkimage -A arm -O linux -T script -C none -a 0 -e 0 \\\n\t-n '$(DEVICE_ID) OpenWrt recovery bootscript' \\\n\t-d ./recovery-$(DEVICE_NAME) $@\nendef\n\ndefine Build/imx6-combined-image-prepare\n\trm -rf $@.boot\n\tmkdir -p $@.boot\nendef\n\ndefine Build/imx6-combined-image-clean\n\trm -rf $@.boot $@.fs\nendef\n\ndefine Build/imx6-combined-image\n\t$(CP) $(IMAGE_KERNEL) $@.boot/uImage\n\n\t$(foreach dts,$(DEVICE_DTS), \\\n\t\t$(CP) \\\n\t\t\t$(DTS_DIR)/$(dts).dtb \\\n\t\t\t$@.boot/;\n\t)\n\n\tmkimage -A arm -O linux -T script -C none -a 0 -e 0 \\\n\t\t-n '$(DEVICE_ID) OpenWrt bootscript' \\\n\t\t-d bootscript-$(DEVICE_NAME) \\\n\t\t$@.boot/boot.scr\n\n\tcp $@ $@.fs\n\n\t$(SCRIPT_DIR)/gen_image_generic.sh $@ \\\n\t\t$(CONFIG_TARGET_KERNEL_PARTSIZE) \\\n\t\t$@.boot \\\n\t\t$(CONFIG_TARGET_ROOTFS_PARTSIZE) \\\n\t\t$@.fs \\\n\t\t1024\nendef\n\ndefine Build/imx6-sdcard\n\t$(Build/imx6-combined-image-prepare)\n\n\tif [ -f $(STAGING_DIR_IMAGE)/$(UBOOT)-u-boot.img ]; then \\\n\t\t$(CP) $(STAGING_DIR_IMAGE)/$(UBOOT)-u-boot.img \\\n\t\t$@.boot/u-boot.img; \\\n\tfi\n\n\tif [ -f $(STAGING_DIR_IMAGE)/$(UBOOT)-u-boot-dtb.img ]; then \\\n\t\t$(CP) $(STAGING_DIR_IMAGE)/$(UBOOT)-u-boot-dtb.img \\\n\t\t$@.boot/u-boot-dtb.img; \\\n\tfi\n\n\t$(Build/imx6-combined-image)\n\tdd if=$(STAGING_DIR_IMAGE)/$(UBOOT)-SPL of=$@ bs=1024 seek=1 conv=notrunc\n\n\t$(Build/imx6-combined-image-clean)\nendef\n\ndefine Build/apalis-emmc\n\t$(Build/imx6-combined-image-prepare)\n\t$(Build/imx6-combined-image)\n\t$(Build/imx6-combined-image-clean)\nendef\n\n\ndefine Device/Default\n  PROFILES := Default\n  FILESYSTEMS := squashfs ext4\n  KERNEL_INSTALL := 1\n  KERNEL_SUFFIX := -uImage\n  KERNEL_NAME := zImage\n  KERNEL := kernel-bin | uImage none\n  KERNEL_LOADADDR := 0x10008000\n  IMAGES :=\nendef\n\ndefine Device/gateworks_ventana\n  DEVICE_VENDOR := Gateworks\n  DEVICE_MODEL := Ventana family\n  DEVICE_VARIANT := normal NAND flash\n  DEVICE_NAME := ventana\n  DEVICE_DTS:= \\\n\timx6dl-gw51xx \\\n\timx6dl-gw52xx \\\n\timx6dl-gw53xx \\\n\timx6dl-gw54xx \\\n\timx6dl-gw551x \\\n\timx6dl-gw552x \\\n\timx6dl-gw553x \\\n\timx6dl-gw5904 \\\n\timx6dl-gw5907 \\\n\timx6dl-gw5910 \\\n\timx6dl-gw5912 \\\n\timx6dl-gw5913 \\\n\timx6q-gw51xx \\\n\timx6q-gw52xx \\\n\timx6q-gw53xx \\\n\timx6q-gw54xx \\\n\timx6q-gw5400-a \\\n\timx6q-gw551x \\\n\timx6q-gw552x \\\n\timx6q-gw553x \\\n\timx6q-gw5904 \\\n\timx6q-gw5907 \\\n\timx6q-gw5910 \\\n\timx6q-gw5912 \\\n\timx6q-gw5913\n  DEVICE_PACKAGES := kmod-sky2 kmod-sound-core kmod-sound-soc-imx \\\n\tkmod-sound-soc-imx-sgtl5000 kmod-can kmod-can-flexcan kmod-can-raw \\\n\tkmod-hwmon-gsc kmod-leds-gpio kmod-pps-gpio kobs-ng\n  KERNEL += | boot-overlay\n  IMAGES := nand.ubi bootfs.tar.gz dtb\n  IMAGE/nand.ubi := append-ubi\n  IMAGE/bootfs.tar.gz := bootfs.tar.gz\n  IMAGE/dtb := install-dtb\n  UBINIZE_PARTS = boot=$$(KDIR_KERNEL_IMAGE).boot.ubifs=15\n  PAGESIZE := 2048\n  BLOCKSIZE := 128k\n  MKUBIFS_OPTS := -m $$(PAGESIZE) -e 124KiB\nendef\nTARGET_DEVICES += gateworks_ventana\n\ndefine Device/gateworks_ventana-large\n  $(Device/gateworks_ventana)\n  DEVICE_VARIANT := large NAND flash\n  IMAGES := nand.ubi\n  PAGESIZE := 4096\n  BLOCKSIZE := 256k\n  MKUBIFS_OPTS := -m $$(PAGESIZE) -e 248KiB\nendef\nTARGET_DEVICES += gateworks_ventana-large\n\ndefine Device/solidrun_cubox-i\n  DEVICE_VENDOR := SolidRun\n  DEVICE_MODEL := CuBox-i\n  DEVICE_DTS := \\\n\timx6q-cubox-i \\\n\timx6dl-cubox-i \\\n\timx6q-hummingboard \\\n\timx6dl-hummingboard\n  DEVICE_PACKAGES := kmod-drm-imx kmod-drm-imx-hdmi kmod-usb-hid\n  UBOOT := mx6cuboxi\n  KERNEL := kernel-bin\n  KERNEL_SUFFIX := -zImage\n  FILESYSTEMS := squashfs\n  IMAGES := combined.bin dtb\n  IMAGE/combined.bin := append-rootfs | pad-extra 128k | imx6-sdcard\n  IMAGE/dtb := install-dtb\nendef\nTARGET_DEVICES += solidrun_cubox-i\n\ndefine Device/toradex_apalis\n  DEVICE_VENDOR := Toradex\n  DEVICE_MODEL := Apalis family\n  SUPPORTED_DEVICES := apalis,ixora apalis,eval\n  DEVICE_DTS := \\\n\timx6q-apalis-eval \\\n\timx6q-apalis-ixora \\\n\timx6q-apalis-ixora-v1.1\n  DEVICE_PACKAGES := \\\n\tkmod-can kmod-can-flexcan kmod-can-raw \\\n\tkmod-leds-gpio kmod-gpio-button-hotplug \\\n\tkmod-pps-gpio kmod-rtc-ds1307\n  FILESYSTEMS := squashfs\n  IMAGES := combined.bin sysupgrade.bin\n  DEVICE_IMG_NAME = $$(DEVICE_IMG_PREFIX)-$$(1).$$(2)\n  IMAGE/combined.bin := append-rootfs | pad-extra 128k | apalis-emmc\n  IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata\n  ARTIFACTS := recovery.scr\n  ARTIFACT/recovery.scr := recovery-scr\nendef\nTARGET_DEVICES += toradex_apalis\n\ndefine Device/wandboard_dual\n  DEVICE_VENDOR := Wandboard\n  DEVICE_MODEL := Dual\n  DEVICE_DTS := imx6dl-wandboard\nendef\nTARGET_DEVICES += wandboard_dual\n"
  },
  {
    "path": "target/linux/imx/image/recovery-toradex_apalis",
    "content": "# flash u-boot-with-spl.imx\n# using fixed size of 1M for U-Boot + SPL\nmmc dev 0 1\nmmc write 0x12100000 0x2 0x800\n\n# flash openwrt-imx6-apalis-squashfs.combined.bin\nsetenv set_blkcnt 'setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt ${blkcnt} / 0x200'\nrun set_blkcnt\nmmc dev 0 0\nmmc write 0x12500000 0 ${blkcnt}\n\nenv default -f -a\nsaveenv\n\nreset\n"
  },
  {
    "path": "target/linux/imx/patches-5.15/100-bootargs.patch",
    "content": "--- a/arch/arm/boot/dts/imx6dl-wandboard.dts\n+++ b/arch/arm/boot/dts/imx6dl-wandboard.dts\n@@ -16,4 +16,8 @@\n \t\tdevice_type = \"memory\";\n \t\treg = <0x10000000 0x40000000>;\n \t};\n+\n+\tchosen {\n+\t\tbootargs = \"console=ttymxc0,115200\";\n+\t};\n };\n"
  },
  {
    "path": "target/linux/imx/patches-5.15/300-ARM-dts-imx6q-apalis-ixora-add-status-LEDs-aliases.patch",
    "content": "From 68604e89335ccb3e893b5a05b2c0d5cd2eaaf6ec Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Petr=20=C5=A0tetiar?= <ynezz@true.cz>\nDate: Tue, 3 Mar 2020 15:14:40 +0100\nSubject: [PATCH] ARM: dts: imx6q-apalis: ixora: add status LEDs aliases\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nSigned-off-by: Petr Štetiar <ynezz@true.cz>\n---\n arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts | 16 ++++++++++------\n arch/arm/boot/dts/imx6q-apalis-ixora.dts      | 12 ++++++++----\n 2 files changed, 18 insertions(+), 10 deletions(-)\n\n--- a/arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts\n+++ b/arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts\n@@ -25,6 +25,10 @@\n \t\ti2c2 = &i2c2;\n \t\trtc0 = &rtc_i2c;\n \t\trtc1 = &snvs_rtc;\n+\t\tled-boot = &led_boot;\n+\t\tled-failsafe = &led_failsafe;\n+\t\tled-running = &led_running;\n+\t\tled-upgrade = &led_upgrade;\n \t};\n \n \tchosen {\n@@ -92,22 +96,22 @@\n \t\tpinctrl-names = \"default\";\n \t\tpinctrl-0 = <&pinctrl_leds_ixora>;\n \n-\t\tled4-green {\n+\t\tled_running: led4-green {\n \t\t\tlabel = \"LED_4_GREEN\";\n-\t\t\tgpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;\n+\t\t\tgpios = <&gpio1 17 GPIO_ACTIVE_HIGH>;\n \t\t};\n \n-\t\tled4-red {\n+\t\tled_upgrade: led4-red {\n \t\t\tlabel = \"LED_4_RED\";\n-\t\t\tgpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;\n+\t\t\tgpios = <&gpio1 21 GPIO_ACTIVE_HIGH>;\n \t\t};\n \n-\t\tled5-green {\n+\t\tled_boot: led5-green {\n \t\t\tlabel = \"LED_5_GREEN\";\n \t\t\tgpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;\n \t\t};\n \n-\t\tled5-red {\n+\t\tled_failsafe: led5-red {\n \t\t\tlabel = \"LED_5_RED\";\n \t\t\tgpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;\n \t\t};\n--- a/arch/arm/boot/dts/imx6q-apalis-ixora.dts\n+++ b/arch/arm/boot/dts/imx6q-apalis-ixora.dts\n@@ -24,6 +24,10 @@\n \t\ti2c2 = &i2c2;\n \t\trtc0 = &rtc_i2c;\n \t\trtc1 = &snvs_rtc;\n+\t\tled-boot = &led_boot;\n+\t\tled-failsafe = &led_failsafe;\n+\t\tled-running = &led_running;\n+\t\tled-upgrade = &led_upgrade;\n \t};\n \n \tchosen {\n@@ -91,22 +95,22 @@\n \t\tpinctrl-names = \"default\";\n \t\tpinctrl-0 = <&pinctrl_leds_ixora>;\n \n-\t\tled4-green {\n+\t\tled_running: led4-green {\n \t\t\tlabel = \"LED_4_GREEN\";\n \t\t\tgpios = <&gpio1 17 GPIO_ACTIVE_HIGH>;\n \t\t};\n \n-\t\tled4-red {\n+\t\tled_upgrade: led4-red {\n \t\t\tlabel = \"LED_4_RED\";\n \t\t\tgpios = <&gpio1 21 GPIO_ACTIVE_HIGH>;\n \t\t};\n \n-\t\tled5-green {\n+\t\tled_boot: led5-green {\n \t\t\tlabel = \"LED_5_GREEN\";\n \t\t\tgpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;\n \t\t};\n \n-\t\tled5-red {\n+\t\tled_failsafe: led5-red {\n \t\t\tlabel = \"LED_5_RED\";\n \t\t\tgpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;\n \t\t};\n"
  },
  {
    "path": "target/linux/imx/patches-5.15/301-ARM-dts-imx6q-apalis-ixora-make-switch3-reset-button.patch",
    "content": "From b6764bb27c819cdcf854371db485a43d71f579f3 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Petr=20=C5=A0tetiar?= <ynezz@true.cz>\nDate: Tue, 3 Mar 2020 15:15:57 +0100\nSubject: [PATCH] ARM: dts: imx6q-apalis: ixora: make switch3 reset button\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nSigned-off-by: Petr Štetiar <ynezz@true.cz>\n---\n arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts | 15 ++++++++++++++-\n arch/arm/boot/dts/imx6q-apalis-ixora.dts      | 15 ++++++++++++++-\n 2 files changed, 28 insertions(+), 2 deletions(-)\n\n--- a/arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts\n+++ b/arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts\n@@ -38,7 +38,7 @@\n \tgpio-keys {\n \t\tcompatible = \"gpio-keys\";\n \t\tpinctrl-names = \"default\";\n-\t\tpinctrl-0 = <&pinctrl_gpio_keys>;\n+\t\tpinctrl-0 = <&pinctrl_gpio_keys &pinctrl_switch3_ixora>;\n \n \t\twakeup {\n \t\t\tlabel = \"Wake-Up\";\n@@ -47,6 +47,13 @@\n \t\t\tdebounce-interval = <10>;\n \t\t\twakeup-source;\n \t\t};\n+\n+\t\treset {\n+\t\t\tlabel = \"reset\";\n+\t\t\tgpios = <&gpio1 16 GPIO_ACTIVE_LOW>;\n+\t\t\tlinux,code = <KEY_RESTART>;\n+\t\t\tdebounce-interval = <10>;\n+\t\t};\n \t};\n \n \tlcd_display: disp0 {\n@@ -275,4 +282,10 @@\n \t\t\tMX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0\n \t\t>;\n \t};\n+\n+\tpinctrl_switch3_ixora: switch3ixora {\n+\t\tfsl,pins = <\n+\t\t\tMX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b0\n+\t\t>;\n+\t};\n };\n--- a/arch/arm/boot/dts/imx6q-apalis-ixora.dts\n+++ b/arch/arm/boot/dts/imx6q-apalis-ixora.dts\n@@ -37,7 +37,7 @@\n \tgpio-keys {\n \t\tcompatible = \"gpio-keys\";\n \t\tpinctrl-names = \"default\";\n-\t\tpinctrl-0 = <&pinctrl_gpio_keys>;\n+\t\tpinctrl-0 = <&pinctrl_gpio_keys &pinctrl_switch3_ixora>;\n \n \t\twakeup {\n \t\t\tlabel = \"Wake-Up\";\n@@ -46,6 +46,13 @@\n \t\t\tdebounce-interval = <10>;\n \t\t\twakeup-source;\n \t\t};\n+\n+\t\treset {\n+\t\t\tlabel = \"reset\";\n+\t\t\tgpios = <&gpio1 16 GPIO_ACTIVE_LOW>;\n+\t\t\tlinux,code = <KEY_RESTART>;\n+\t\t\tdebounce-interval = <10>;\n+\t\t};\n \t};\n \n \tlcd_display: disp0 {\n@@ -276,4 +283,10 @@\n \t\t\tMX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0\n \t\t>;\n \t};\n+\n+\tpinctrl_switch3_ixora: switch3ixora {\n+\t\tfsl,pins = <\n+\t\t\tMX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b0\n+\t\t>;\n+\t};\n };\n"
  },
  {
    "path": "target/linux/imx/profiles/100-default.mk",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2013 OpenWrt.org\n\ndefine Profile/Default\n  PRIORITY:=1\n  NAME:=Default Profile\nendef\n\ndefine Profile/Default/Description\n Package set compatible with most NXP i.MX based boards.\nendef\n\n$(eval $(call Profile,Default))\n"
  },
  {
    "path": "target/linux/ipq40xx/Makefile",
    "content": "include $(TOPDIR)/rules.mk\n\nARCH:=arm\nBOARD:=ipq40xx\nBOARDNAME:=Qualcomm Atheros IPQ40XX\nFEATURES:=squashfs fpu ramdisk nand\nCPU_TYPE:=cortex-a7\nCPU_SUBTYPE:=neon-vfpv4\nSUBTARGETS:=generic chromium mikrotik\n\nKERNEL_PATCHVER:=5.10\nKERNEL_TESTING_PATCHVER:=5.15\n\nKERNELNAME:=zImage Image dtbs\n\ninclude $(INCLUDE_DIR)/target.mk\nDEFAULT_PACKAGES += \\\n\tkmod-usb-dwc3-qcom \\\n\tkmod-leds-gpio kmod-gpio-button-hotplug swconfig \\\n\tkmod-ath10k-ct wpad-basic-wolfssl \\\n\tkmod-usb3 kmod-usb-dwc3 ath10k-firmware-qca4019-ct \\\n\tath10k-board-qca4019 uboot-envtools\n\n$(eval $(call BuildTarget))\n"
  },
  {
    "path": "target/linux/ipq40xx/base-files/etc/board.d/01_leds",
    "content": "#\n# Copyright (C) 2015 OpenWrt.org\n#\n\n. /lib/functions/uci-defaults.sh\n\nboard_config_update\n\nboard=$(board_name)\n\ncase \"$board\" in\nalfa-network,ap120c-ac)\n\tucidef_set_led_netdev \"wan\" \"WAN\" \"amber:wan\" \"eth1\"\n\t;;\nasus,rt-ac42u)\n\tucidef_set_led_switch \"lan1\" \"LAN1\" \"blue:lan-1\" \"switch0\" \"0x02\"\n\tucidef_set_led_switch \"lan2\" \"LAN2\" \"blue:lan-2\" \"switch0\" \"0x04\"\n\tucidef_set_led_switch \"lan3\" \"LAN3\" \"blue:lan-3\" \"switch0\" \"0x08\"\n\tucidef_set_led_switch \"lan4\" \"LAN4\" \"blue:lan-4\" \"switch0\" \"0x10\"\n\t;;\nasus,rt-ac58u)\n\tucidef_set_led_netdev \"wan\" \"WAN\" \"blue:wan\" \"eth1\"\n\tucidef_set_led_switch \"lan\" \"LAN\" \"blue:lan\" \"switch0\" \"0x1e\"\n\t;;\navm,fritzbox-4040)\n\tucidef_set_led_wlan \"wlan\" \"WLAN\" \"green:wlan\" \"phy0tpt\" \"phy1tpt\"\n\tucidef_set_led_netdev \"wan\" \"WAN\" \"green:wan\" \"eth1\"\n\tucidef_set_led_switch \"lan\" \"LAN\" \"green:lan\" \"switch0\" \"0x1e\"\n\t;;\navm,fritzbox-7530 |\\\nglinet,gl-b1300 |\\\nmikrotik,lhgg-60ad)\n\tucidef_set_led_wlan \"wlan\" \"WLAN\" \"green:wlan\" \"phy0tpt\"\n\t;;\nedgecore,oap100)\n\tucidef_set_led_wlan \"wlan2g\" \"WLAN2G\" \"blue:wlan2g\" \"phy0tpt\"\n\tucidef_set_led_wlan \"wlan5g\" \"WLAN5G\" \"blue:wlan5g\" \"phy1tpt\"\n\t;;\nengenius,eap1300)\n\tucidef_set_led_netdev \"lan\" \"LAN\" \"blue:lan\" \"eth0\"\n\tucidef_set_led_wlan \"wlan2g\" \"WLAN2G\" \"blue:wlan2g\" \"phy0tpt\"\n\tucidef_set_led_wlan \"wlan5g\" \"WLAN5G\" \"yellow:wlan5g\" \"phy1tpt\"\n\tucidef_set_led_default \"mesh\" \"MESH\" \"blue:mesh\" \"0\"\n\t;;\nengenius,eap2200)\n\tucidef_set_led_netdev \"lan1\" \"LAN1\" \"blue:lan1\" \"eth0\"\n\tucidef_set_led_netdev \"lan2\" \"LAN2\" \"blue:lan2\" \"eth1\"\n\t;;\nengenius,ens620ext)\n\tucidef_set_led_wlan \"wlan2g\" \"WLAN2G\" \"green:wlan2g\" \"phy0tpt\"\n\tucidef_set_led_wlan \"wlan5g\" \"WLAN5G\" \"green:wlan5g\" \"phy1tpt\"\n\tucidef_set_led_netdev \"lan1\" \"LAN1\" \"green:lan1\" \"eth0\"\n\tucidef_set_led_netdev \"lan2\" \"LAN2\" \"green:lan2\" \"eth1\"\n\t;;\nmikrotik,cap-ac)\n\tucidef_set_led_default \"power\" \"POWER\" \"blue:power\" \"1\"\n\tucidef_set_led_default \"user\" \"USER\" \"green:user\" \"0\"\n\tucidef_set_led_switch \"eth1\" \"ETH1\" \"green:eth1\" \"switch0\" \"0x20\"\n\tucidef_set_led_switch \"eth2\" \"ETH2\" \"green:eth2\" \"switch0\" \"0x10\"\n\tucidef_set_led_wlan \"wlan2g\" \"WLAN2G\" \"green:wlan2g\" \"phy0tpt\"\n\tucidef_set_led_wlan \"wlan5g\" \"WLAN5G\" \"green:wlan5g\" \"phy1tpt\"\n\t;;\nmikrotik,hap-ac3)\n\tucidef_set_led_netdev \"wan\" \"WAN\" \"green:wan\" \"eth1\"\n\tucidef_set_led_switch \"lan1\" \"LAN1\" \"green:lan1\" \"switch0\" \"0x10\"\n\tucidef_set_led_switch \"lan2\" \"LAN2\" \"green:lan2\" \"switch0\" \"0x08\"\n\tucidef_set_led_switch \"lan3\" \"LAN3\" \"green:lan3\" \"switch0\" \"0x04\"\n\tucidef_set_led_switch \"lan4\" \"LAN4\" \"green:lan4\" \"switch0\" \"0x02\"\n\tucidef_set_led_gpio \"poe\" \"POE\" \"red:poe\" \"452\" \"0\"\n\t;;\nmikrotik,sxtsq-5-ac)\n\tucidef_set_rssimon \"wlan0\" \"200000\" \"1\"\n\tucidef_set_led_rssi \"rssilow\" \"rssilow\" \"green:rssilow\" \"wlan0\" \"1\" \"100\"\n\tucidef_set_led_rssi \"rssimediumlow\" \"rssimediumlow\" \"green:rssimediumlow\" \"wlan0\" \"21\" \"100\"\n\tucidef_set_led_rssi \"rssimedium\" \"rssimedium\" \"green:rssimedium\" \"wlan0\" \"41\" \"100\"\n\tucidef_set_led_rssi \"rssimediumhigh\" \"rssimediumhigh\" \"green:rssimediumhigh\" \"wlan0\" \"61\" \"100\"\n\tucidef_set_led_rssi \"rssihigh\" \"rssihigh\" \"green:rssihigh\" \"wlan0\" \"81\" \"100\"\n\t;;\nmobipromo,cm520-79f)\n\tucidef_set_led_netdev \"wan\" \"WAN\" \"blue:wan\" \"eth1\"\n\tucidef_set_led_switch \"lan1\" \"LAN1\" \"blue:lan1\" \"switch0\" \"0x10\"\n\tucidef_set_led_switch \"lan2\" \"LAN2\" \"blue:lan2\" \"switch0\" \"0x08\"\n\t;;\nnetgear,ex6100v2 |\\\nnetgear,ex6150v2)\n\tucidef_set_led_wlan \"wlan2g\" \"WLAN2G\" \"green:router\" \"phy0tpt\"\n\tucidef_set_led_wlan \"wlan5g\" \"WLAN5G\" \"green:client\" \"phy1tpt\"\n\t;;\nqxwlan,e2600ac-c1 |\\\nqxwlan,e2600ac-c2)\n\tucidef_set_led_wlan \"wlan2g\" \"WLAN0\" \"green:wlan0\" \"phy0tpt\"\n\tucidef_set_led_wlan \"wlan5g\" \"WLAN1\" \"green:wlan1\" \"phy1tpt\"\n\t;;\nzyxel,nbg6617 |\\\nzyxel,wre6606)\n\tucidef_set_led_wlan \"wlan2g\" \"WLAN2G\" \"green:wlan2g\" \"phy0tpt\"\n\tucidef_set_led_wlan \"wlan5g\" \"WLAN5G\" \"green:wlan5g\" \"phy1tpt\"\n\t;;\nesac\n\nboard_config_flush\n\nexit 0\n"
  },
  {
    "path": "target/linux/ipq40xx/base-files/etc/board.d/02_network",
    "content": "#\n# Copyright (c) 2015 The Linux Foundation. All rights reserved.\n# Copyright (c) 2011-2015 OpenWrt.org\n#\n\n. /lib/functions/uci-defaults.sh\n. /lib/functions/system.sh\n\nipq40xx_setup_interfaces()\n{\n\tlocal board=\"$1\"\n\n\tcase \"$board\" in\n\t8dev,habanero-dvk|\\\n\t8dev,jalapeno|\\\n\talfa-network,ap120c-ac|\\\n\tengenius,emr3500|\\\n\tengenius,ens620ext|\\\n\tluma,wrtq-329acn|\\\n\tnetgear,wac510|\\\n\tplasmacloud,pa1200|\\\n\tplasmacloud,pa2200)\n\t\tucidef_set_interfaces_lan_wan \"eth0\" \"eth1\"\n\t\t;;\n\taruba,ap-303|\\\n\taruba,ap-365|\\\n\tavm,fritzrepeater-1200|\\\n\tdlink,dap-2610 |\\\n\tengenius,eap1300|\\\n\tengenius,emd1|\\\n\tmeraki,mr33|\\\n\tmikrotik,lhgg-60ad|\\\n\tmikrotik,sxtsq-5-ac|\\\n\tnetgear,ex6100v2|\\\n\tnetgear,ex6150v2|\\\n\tzyxel,wre6606)\n\t\tucidef_set_interface_lan \"eth0\"\n\t\t;;\n\taruba,ap-303h|\\\n\tteltonika,rutx10)\n\t\tucidef_set_interfaces_lan_wan \"eth0\" \"eth1\"\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0u@eth0\" \"2:lan:1\" \"3:lan:2\" \"4:lan:3\" \"0u@eth1\" \"5:wan\"\n\t\t;;\n\tasus,map-ac2200|\\\n\tcilab,meshpoint-one|\\\n\tedgecore,ecw5211|\\\n\tedgecore,oap100|\\\n\tgoogle,wifi|\\\n\topenmesh,a42|\\\n\topenmesh,a62)\n\t\tucidef_set_interfaces_lan_wan \"eth1\" \"eth0\"\n\t\t;;\n\tmikrotik,cap-ac)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0t@eth0\" \"4:lan\" \"5:wan\"\n\t\t;;\n\tasus,rt-ac42u|\\\n\tasus,rt-ac58u|\\\n\tmikrotik,hap-ac2|\\\n\tmikrotik,hap-ac3|\\\n\tp2w,r619ac-64m|\\\n\tp2w,r619ac-128m|\\\n\tzyxel,nbg6617)\n\t\tucidef_set_interfaces_lan_wan \"eth0\" \"eth1\"\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0u@eth0\" \"1:lan:4\" \"2:lan:3\" \"3:lan:2\" \"4:lan:1\"\n\t\t;;\n\tavm,fritzbox-4040|\\\n\tlinksys,ea6350v3|\\\n\tlinksys,ea8300)\n\t\tucidef_set_interfaces_lan_wan \"eth0\" \"eth1\"\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0u@eth0\" \"1:lan\" \"2:lan\" \"3:lan\" \"4:lan\"\n\t\t;;\n\tlinksys,mr8300)\n\t\tucidef_set_interfaces_lan_wan \"eth0\" \"eth1\"\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0u@eth0\" \"1:lan\" \"2:lan\" \"3:lan\" \"4:lan\" \"0u@eth1\" \"5:wan\"\n\t\t;;\n\tavm,fritzbox-7530)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0u@eth0\" \"1:lan:4\" \"2:lan:3\" \"3:lan:2\" \"4:lan:1\"\n\t\t;;\n\tavm,fritzrepeater-3000)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0u@eth0\" \"4:lan:1\" \"5:lan:2\"\n\t\t;;\n\tcompex,wpj419|\\\n\tcompex,wpj428|\\\n\tengenius,eap2200)\n\t\tucidef_set_interface_lan \"eth0 eth1\"\n\t\t;;\n\tbuffalo,wtr-m2133hp)\n\t\tucidef_set_interfaces_lan_wan \"eth0\" \"eth1\"\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0u@eth0\" \"2:lan:3\" \"3:lan:2\" \"4:lan:1\"\n\t\t;;\n\tcellc,rtl30vw)\n\t\tucidef_set_interface_lan \"eth0\"\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0u@eth0\" \"3:lan\" \"4:lan\"\n\t\t;;\n\tdevolo,magic-2-wifi-next)\n\t\tucidef_set_interface_lan \"eth0 eth1 eth2\"\n\t\t;;\n\tezviz,cs-w3-wd1200g-eup)\n\t\tucidef_set_interfaces_lan_wan \"eth0\" \"eth1\"\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0u@eth0\" \"2:lan:3\" \"3:lan:2\" \"4:lan:1\" \"0u@eth1\" \"5:wan\"\n\t\t;;\n\tglinet,gl-ap1300 |\\\n\tglinet,gl-b1300 |\\\n\tglinet,gl-s1300)\n\t\tucidef_set_interfaces_lan_wan \"eth0\" \"eth1\"\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0u@eth0\" \"3:lan\" \"4:lan\"\n\t\t;;\n\tglinet,gl-b2200)\n\t\tucidef_set_interfaces_lan_wan \"eth0\" \"eth1\"\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0u@eth0\" \"1:lan\" \"2:lan\" \"3:lan\" \"5:lan\" \"0u@eth1\" \"4:wan\"\n\t\t;;\n\tmobipromo,cm520-79f)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0u@eth0\" \"3:lan:2\" \"4:lan:1\"\n\t\tucidef_set_interface_wan \"eth1\"\n\t\t;;\n\tnetgear,rbr50|\\\n\tnetgear,rbs50|\\\n\tnetgear,srr60|\\\n\tnetgear,srs60)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0u@eth0\" \"2:lan\" \"3:lan\" \"4:lan\"\n\t\tucidef_set_interface_wan \"eth1\"\n\t\t;;\n\tqxwlan,e2600ac-c1 |\\\n\tqxwlan,e2600ac-c2)\n\t\tucidef_set_interfaces_lan_wan \"eth0\" \"eth1\"\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0u@eth0\" \"3:lan\" \"4:lan\" \"0u@eth1\" \"5:wan\"\n\t\t;;\n\tunielec,u4019-32m |\\\n\ttel,x1pro)\n\t\tucidef_set_interfaces_lan_wan \"eth0\" \"eth1\"\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0u@eth0\" \"1:lan\" \"2:lan\" \"3:lan\" \"4:lan\" \"0u@eth1\" \"5:wan\"\n\t\t;;\n\tzte,mf286d)\n\t\tucidef_set_interfaces_lan_wan \"eth0\" \"eth1\"\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0u@eth0\" \"2:lan:4\" \"3:lan:3\" \"4:lan:2\" \"0u@eth1\" \"5:wan\"\n\t\t;;\n\t*)\n\t\techo \"Unsupported hardware. Network interfaces not initialized\"\n\t\t;;\n\tesac\n}\n\nipq40xx_setup_macs()\n{\n\tlocal board=\"$1\"\n\tlocal lan_mac=\"\"\n\tlocal wan_mac=\"\"\n\tlocal label_mac=\"\"\n\n\tcase \"$board\" in\n\t8dev,habanero-dvk)\n\t\tlabel_mac=$(mtd_get_mac_binary \"ART\" 0x1006)\n\t\t;;\n\tasus,rt-ac58u)\n\t\twan_mac=$(mtd_get_mac_binary_ubi Factory 0x1006)\n\t\tlan_mac=$(mtd_get_mac_binary_ubi Factory 0x5006)\n\t\tlabel_mac=$wan_mac\n\t\t;;\n\tcilab,meshpoint-one)\n\t\tlabel_mac=$(mtd_get_mac_binary \"ART\" 0x1006)\n\t\t;;\n\tdevolo,magic-2-wifi-next)\n\t\tlan_mac=$(mtd_get_mac_ascii APPSBLENV MacAddress0)\n\t\tlabel_mac=$lan_mac\n\t\t;;\n\tdlink,dap-2610)\n\t\tlan_mac=$(mtd_get_mac_ascii bdcfg lanmac)\n\t\tlabel_mac=$lan_mac\n\t\t;;\n\tengenius,eap2200|\\\n\tengenius,emd1)\n\t\tlan_mac=$(mtd_get_mac_ascii 0:APPSBLENV ethaddr)\n\t\tlabel_mac=$lan_mac\n\t\t;;\n\tengenius,emr3500)\n\t\twan_mac=$(mtd_get_mac_ascii 0:APPSBLENV wanaddr)\n\t\tlan_mac=$(mtd_get_mac_ascii 0:APPSBLENV ethaddr)\n\t\tlabel_mac=$wan_mac\n\t\t;;\n\tengenius,ens620ext)\n\t\twan_mac=$(mtd_get_mac_ascii u-boot-env ethaddr)\n\t\tlan_mac=$(macaddr_add \"$wan_mac\" 1)\n\t\t;;\n\tezviz,cs-w3-wd1200g-eup)\n\t\tlabel_mac=$(mtd_get_mac_binary \"ART\" 0x6)\n\t\t;;\n\tlinksys,ea6350v3)\n\t\twan_mac=$(mtd_get_mac_ascii devinfo hw_mac_addr)\n\t\tlan_mac=$(macaddr_add \"$wan_mac\" 1)\n\t\t;;\n\tmikrotik,cap-ac |\\\n\tmikrotik,hap-ac2|\\\n\tmikrotik,hap-ac3)\n\t\twan_mac=$(cat /sys/firmware/mikrotik/hard_config/mac_base)\n\t\tlan_mac=$(macaddr_add $wan_mac 1)\n\t\tlabel_mac=\"$wan_mac\"\n\t\t;;\n\tmikrotik,lhgg-60ad|\\\n\tmikrotik,sxtsq-5-ac)\n\t\tlan_mac=$(cat /sys/firmware/mikrotik/hard_config/mac_base)\n\t\tlabel_mac=\"$lan_mac\"\n\t\t;;\n\tesac\n\n\t[ -n \"$lan_mac\" ] && ucidef_set_interface_macaddr \"lan\" $lan_mac\n\t[ -n \"$wan_mac\" ] && ucidef_set_interface_macaddr \"wan\" $wan_mac\n\t[ -n \"$label_mac\" ] && ucidef_set_label_macaddr $label_mac\n}\n\nboard_config_update\nboard=$(board_name)\nipq40xx_setup_interfaces $board\nipq40xx_setup_macs $board\nboard_config_flush\n\nexit 0\n"
  },
  {
    "path": "target/linux/ipq40xx/base-files/etc/board.d/03_gpio_switches",
    "content": "\n. /lib/functions/uci-defaults.sh\n\nboard_config_update\n\nboard=$(board_name)\n\ncase \"$board\" in\ncellc,rtl30vw)\n\tucidef_add_gpio_switch \"w_disable\" \"W_DISABLE mPCIE pin\" \"398\" \"1\"\n\tucidef_add_gpio_switch \"pmd_resin_n\" \"PMD_RESIN_N pin\" \"399\" \"1\"\n\tucidef_add_gpio_switch \"mcpie_vcc\" \"LTE power\" \"400\" \"0\"\n\tucidef_add_gpio_switch \"usb_vcc\" \"USB power\" \"401\" \"0\"\n\t;;\ncilab,meshpoint-one)\n\tucidef_add_gpio_switch \"poe_passtrough\" \"POE passtrough enable\" \"413\" \"1\"\n\t;;\ncompex,wpj428)\n\tucidef_add_gpio_switch \"sim_card_select\" \"SIM card select\" \"3\" \"0\"\n\t;;\nmikrotik,cap-ac)\n\tucidef_add_gpio_switch \"poe_passtrough\" \"POE passtrough enable\" \"414\" \"0\"\n\t;;\nmikrotik,hap-ac3)\n\tucidef_add_gpio_switch \"poe_passtrough\" \"PoE Passthrough\" \"452\" \"0\"\n\t;;\nzte,mf286d)\n\tucidef_add_gpio_switch \"power_btn_block\" \"Power button blocker\" \"421\" \"0\"\n\t;;\nesac\n\nboard_config_flush\n\nexit 0\n"
  },
  {
    "path": "target/linux/ipq40xx/base-files/etc/hotplug.d/firmware/11-ath10k-caldata",
    "content": "#!/bin/sh\n\n[ -e /lib/firmware/$FIRMWARE ] && exit 0\n\n. /lib/functions/caldata.sh\n\nboard=$(board_name)\n\ncase \"$FIRMWARE\" in\n\"ath10k/cal-pci-0000:01:00.0.bin\")\n\tcase \"$board\" in\n\tmeraki,mr33)\n\t\tcaldata_extract_ubi \"ART\" 0x9000 0x844\n\t\tcaldata_valid \"4408\" || caldata_extract \"ART\" 0x9000 0x844\n\t\tath10k_patch_mac $(macaddr_add $(get_mac_binary \"/sys/bus/i2c/devices/0-0050/eeprom\" 0x66) 1)\n\t\t;;\n\tesac\n\t;;\n\"ath10k/pre-cal-pci-0000:01:00.0.bin\")\n\tcase \"$board\" in\n\tasus,map-ac2200)\n\t\tcaldata_extract_ubi \"Factory\" 0x9000 0x2f20\n\t\tln -sf /lib/firmware/ath10k/pre-cal-pci-0000\\:00\\:00.0.bin \\\n\t\t\t/lib/firmware/ath10k/QCA9888/hw2.0/board.bin\n\t\t;;\n\tasus,rt-ac42u)\n\t\tcaldata_extract_ubi \"Factory\" 0x9000 0x2f20\n\t\t;;\n\tavm,fritzrepeater-3000)\n\t\t/usr/bin/fritz_cal_extract -i 1 -s 0x3D000 -e 0x212 -l 12064 -o /lib/firmware/$FIRMWARE $(find_mtd_chardev \"urlader0\") || \\\n\t\t/usr/bin/fritz_cal_extract -i 1 -s 0x3C800 -e 0x212 -l 12064 -o /lib/firmware/$FIRMWARE $(find_mtd_chardev \"urlader0\") || \\\n\t\t/usr/bin/fritz_cal_extract -i 1 -s 0x3C000 -e 0x212 -l 12064 -o /lib/firmware/$FIRMWARE $(find_mtd_chardev \"urlader0\") || \\\n\t\t/usr/bin/fritz_cal_extract -i 1 -s 0x3D000 -e 0x212 -l 12064 -o /lib/firmware/$FIRMWARE $(find_mtd_chardev \"urlader1\") || \\\n\t\t/usr/bin/fritz_cal_extract -i 1 -s 0x3C800 -e 0x212 -l 12064 -o /lib/firmware/$FIRMWARE $(find_mtd_chardev \"urlader1\") || \\\n\t\t/usr/bin/fritz_cal_extract -i 1 -s 0x3C000 -e 0x212 -l 12064 -o /lib/firmware/$FIRMWARE $(find_mtd_chardev \"urlader1\")\n\t\t;;\n\topenmesh,a62 |\\\n\tplasmacloud,pa2200)\n\t\tcaldata_extract \"0:ART\" 0x9000 0x2f20\n\t\t;;\n\tlinksys,ea8300 |\\\n\tlinksys,mr8300)\n\t\tcaldata_extract \"ART\" 0x9000 0x2f20\n\t\t# OEM assigns 4 sequential MACs\n\t\tath10k_patch_mac $(macaddr_setbit_la $(macaddr_add \"$(cat /sys/class/net/eth0/address)\" 4))\n\t\t;;\n\tnetgear,rbr50|\\\n\tnetgear,rbs50|\\\n\tnetgear,srr60|\\\n\tnetgear,srs60)\n\t\tcaldata_extract_mmc \"0:ART\" 0x9000 0x2f20\n\t\tath10k_patch_mac $(mmc_get_mac_binary ARTMTD 0x12)\n\t\t;;\n\tesac\n\t;;\n\"ath10k/pre-cal-ahb-a000000.wifi.bin\")\n\tcase \"$board\" in\n\tqcom,ap-dk01.1-c1)\n\t\tcaldata_extract \"ART\" 0x1000 0x2f20\n\t\t;;\n\tasus,map-ac2200|\\\n\tasus,rt-ac42u|\\\n\tasus,rt-ac58u)\n\t\tcaldata_extract_ubi \"Factory\" 0x1000 0x2f20\n\t\t;;\n\tavm,fritzbox-4040)\n\t\t/usr/bin/fritz_cal_extract -i 1 -s 0x400 -e 0x207 -l 12064 -o /lib/firmware/$FIRMWARE $(find_mtd_chardev \"urlader_config\")\n\t\t;;\n\tavm,fritzbox-7530 |\\\n\tavm,fritzrepeater-1200 |\\\n\tavm,fritzrepeater-3000)\n\t\t/usr/bin/fritz_cal_extract -i 1 -s 0x3C000 -e 0x207 -l 12064 -o /lib/firmware/$FIRMWARE $(find_mtd_chardev \"urlader0\") || \\\n\t\t/usr/bin/fritz_cal_extract -i 1 -s 0x3C800 -e 0x207 -l 12064 -o /lib/firmware/$FIRMWARE $(find_mtd_chardev \"urlader0\") || \\\n\t\t/usr/bin/fritz_cal_extract -i 1 -s 0x3D000 -e 0x207 -l 12064 -o /lib/firmware/$FIRMWARE $(find_mtd_chardev \"urlader0\") || \\\n\t\t/usr/bin/fritz_cal_extract -i 1 -s 0x3C000 -e 0x207 -l 12064 -o /lib/firmware/$FIRMWARE $(find_mtd_chardev \"urlader1\") || \\\n\t\t/usr/bin/fritz_cal_extract -i 1 -s 0x3C800 -e 0x207 -l 12064 -o /lib/firmware/$FIRMWARE $(find_mtd_chardev \"urlader1\") || \\\n\t\t/usr/bin/fritz_cal_extract -i 1 -s 0x3D000 -e 0x207 -l 12064 -o /lib/firmware/$FIRMWARE $(find_mtd_chardev \"urlader1\")\n\t\t;;\n\tcellc,rtl30vw |\\\n\topenmesh,a42 |\\\n\topenmesh,a62 |\\\n\tplasmacloud,pa1200 |\\\n\tplasmacloud,pa2200)\n\t\tcaldata_extract \"0:ART\" 0x1000 0x2f20\n\t\t;;\n\tdevolo,magic-2-wifi-next)\n\t\tcaldata_extract \"ART\" 0x1000 0x2f20\n\t\tath10k_patch_mac $(mtd_get_mac_ascii APPSBLENV WiFiMacAddress0)\n\t\t;;\n\tdlink,dap-2610)\n\t\tcaldata_extract \"ART\" 0x1000 0x2f20\n\t\tath10k_patch_mac $(mtd_get_mac_ascii bdcfg wlanmac)\n\t\t;;\n\tengenius,emd1)\n\t\tcaldata_extract \"0:ART\" 0x1000 0x2f20\n\t\tath10k_patch_mac $(mtd_get_mac_ascii 0:APPSBLENV wlanaddr)\n\t\t;;\n\tengenius,emr3500)\n\t\tcaldata_extract \"0:ART\" 0x1000 0x2f20\n\t\tath10k_patch_mac $(mtd_get_mac_ascii 0:APPSBLENV ethaddr)\n\t\t;;\n\tengenius,ens620ext)\n\t\tcaldata_extract \"ART\" 0x1000 0x2f20\n\t\tath10k_patch_mac $(macaddr_add $(mtd_get_mac_ascii u-boot-env ethaddr) 2)\n\t\t;;\n\tlinksys,ea8300 |\\\n\tlinksys,mr8300)\n\t\tcaldata_extract \"ART\" 0x1000 0x2f20\n\t\tath10k_patch_mac $(macaddr_add \"$(cat /sys/class/net/eth0/address)\" 2)\n\t\t;;\n\tmeraki,mr33)\n\t\tcaldata_extract_ubi \"ART\" 0x1000 0x2f20\n\t\tcaldata_valid \"202f\" || caldata_extract \"ART\" 0x1000 0x2f20\n\t\tath10k_patch_mac $(macaddr_add $(get_mac_binary \"/sys/bus/i2c/devices/0-0050/eeprom\" 0x66) 2)\n\t\t;;\n\tmikrotik,cap-ac |\\\n\tmikrotik,hap-ac2 |\\\n\tmikrotik,hap-ac3)\n\t\twlan_data=\"/sys/firmware/mikrotik/hard_config/wlan_data\"\n\t\t( [ -f \"$wlan_data\" ] && caldata_sysfsload_from_file \"$wlan_data\" 0x0 0x2f20 ) || \\\n\t\t( [ -d \"$wlan_data\" ] && caldata_sysfsload_from_file \"$wlan_data/data_0\" 0x0 0x2f20 )\n\t\t;;\n\tnetgear,rbr50|\\\n\tnetgear,rbs50|\\\n\tnetgear,srr60|\\\n\tnetgear,srs60)\n\t\tcaldata_extract_mmc \"0:ART\" 0x1000 0x2f20\n\t\tath10k_patch_mac $(mmc_get_mac_binary ARTMTD 0x0)\n\t\t;;\n\tzyxel,nbg6617 |\\\n\tzyxel,wre6606)\n\t\tcaldata_extract \"ART\" 0x1000 0x2f20\n\t\tath10k_patch_mac $(macaddr_add $(cat /sys/class/net/eth0/address) -2)\n\t\t;;\n\tesac\n\t;;\n\"ath10k/pre-cal-ahb-a800000.wifi.bin\")\n\tcase \"$board\" in\n\tqcom,ap-dk01.1-c1)\n\t\tcaldata_extract \"ART\" 0x5000 0x2f20\n\t\t;;\n\tasus,map-ac2200|\\\n\tasus,rt-ac58u)\n\t\tcaldata_extract_ubi \"Factory\" 0x5000 0x2f20\n\t\t;;\n\tavm,fritzbox-4040)\n\t\t/usr/bin/fritz_cal_extract -i 1 -s 0x400 -e 0x208 -l 12064 -o /lib/firmware/$FIRMWARE $(find_mtd_chardev \"urlader_config\")\n\t\t;;\n\tavm,fritzbox-7530 |\\\n\tavm,fritzrepeater-1200 |\\\n\tavm,fritzrepeater-3000)\n\t\t/usr/bin/fritz_cal_extract -i 1 -s 0x3C800 -e 0x208 -l 12064 -o /lib/firmware/$FIRMWARE $(find_mtd_chardev \"urlader0\") || \\\n\t\t/usr/bin/fritz_cal_extract -i 1 -s 0x3D000 -e 0x208 -l 12064 -o /lib/firmware/$FIRMWARE $(find_mtd_chardev \"urlader0\") || \\\n\t\t/usr/bin/fritz_cal_extract -i 1 -s 0x3C000 -e 0x208 -l 12064 -o /lib/firmware/$FIRMWARE $(find_mtd_chardev \"urlader0\") || \\\n\t\t/usr/bin/fritz_cal_extract -i 1 -s 0x3C800 -e 0x208 -l 12064 -o /lib/firmware/$FIRMWARE $(find_mtd_chardev \"urlader1\") || \\\n\t\t/usr/bin/fritz_cal_extract -i 1 -s 0x3D000 -e 0x208 -l 12064 -o /lib/firmware/$FIRMWARE $(find_mtd_chardev \"urlader1\") || \\\n\t\t/usr/bin/fritz_cal_extract -i 1 -s 0x3C000 -e 0x208 -l 12064 -o /lib/firmware/$FIRMWARE $(find_mtd_chardev \"urlader1\")\n\t\t;;\n\tcellc,rtl30vw |\\\n\topenmesh,a42 |\\\n\topenmesh,a62 |\\\n\tplasmacloud,pa1200 |\\\n\tplasmacloud,pa2200)\n\t\tcaldata_extract \"0:ART\" 0x5000 0x2f20\n\t\t;;\n\tdevolo,magic-2-wifi-next)\n\t\tcaldata_extract \"ART\" 0x5000 0x2f20\n\t\tath10k_patch_mac $(mtd_get_mac_ascii APPSBLENV WiFiMacAddress1)\n\t\t;;\n\tdlink,dap-2610)\n\t\tcaldata_extract \"ART\" 0x5000 0x2f20\n\t\tath10k_patch_mac $(mtd_get_mac_ascii bdcfg wlanmac_a)\n\t\t;;\n\tengenius,emd1)\n\t\tcaldata_extract \"0:ART\" 0x5000 0x2f20\n\t\tath10k_patch_mac $(macaddr_add $(mtd_get_mac_ascii 0:APPSBLENV wlanaddr) 1)\n\t\t;;\n\tengenius,emr3500)\n\t\tcaldata_extract \"0:ART\" 0x5000 0x2f20\n\t\tath10k_patch_mac $(macaddr_add $(mtd_get_mac_ascii 0:APPSBLENV ethaddr) 1)\n\t\t;;\n\tengenius,ens620ext)\n\t\tcaldata_extract \"ART\" 0x5000 0x2f20\n\t\tath10k_patch_mac $(macaddr_add $(mtd_get_mac_ascii u-boot-env ethaddr) 3)\n\t\t;;\n\tlinksys,ea8300 |\\\n\tlinksys,mr8300)\n\t\tcaldata_extract \"ART\" 0x5000 0x2f20\n\t\tath10k_patch_mac $(macaddr_add \"$(cat /sys/class/net/eth0/address)\" 3)\n\t\t;;\n\tmeraki,mr33)\n\t\tcaldata_extract_ubi \"ART\" 0x5000 0x2f20\n\t\tcaldata_valid \"202f\" || caldata_extract \"ART\" 0x5000 0x2f20\n\t\tath10k_patch_mac $(macaddr_add $(get_mac_binary \"/sys/bus/i2c/devices/0-0050/eeprom\" 0x66) 3)\n\t\t;;\n\tmikrotik,cap-ac |\\\n\tmikrotik,hap-ac2 |\\\n\tmikrotik,hap-ac3 |\\\n\tmikrotik,sxtsq-5-ac)\n\t\twlan_data=\"/sys/firmware/mikrotik/hard_config/wlan_data\"\n\t\t( [ -f \"$wlan_data\" ] && caldata_sysfsload_from_file \"$wlan_data\" 0x8000 0x2f20 ) || \\\n\t\t( [ -d \"$wlan_data\" ] && caldata_sysfsload_from_file \"$wlan_data/data_2\" 0x0 0x2f20 )\n\t\t;;\n\tnetgear,rbr50|\\\n\tnetgear,rbs50|\\\n\tnetgear,srr60|\\\n\tnetgear,srs60)\n\t\tcaldata_extract_mmc \"0:ART\" 0x5000 0x2f20\n\t\tath10k_patch_mac $(mmc_get_mac_binary ARTMTD 0xc)\n\t\t;;\n\tzyxel,nbg6617 |\\\n\tzyxel,wre6606)\n\t\tcaldata_extract \"ART\" 0x5000 0x2f20\n\t\tath10k_patch_mac $(macaddr_add $(cat /sys/class/net/eth0/address) -1)\n\t\t;;\n\tesac\n\t;;\n*)\n\texit 1\n\t;;\nesac\n"
  },
  {
    "path": "target/linux/ipq40xx/base-files/etc/init.d/bootcount",
    "content": "#!/bin/sh /etc/rc.common\n\nSTART=99\n\nboot() {\n\tcase $(board_name) in\n\talfa-network,ap120c-ac)\n\t\t[ -n \"$(fw_printenv bootcount changed 2>/dev/null)\" ] &&\\\n\t\t\techo -e \"bootcount\\nchanged\\n\" | /usr/sbin/fw_setenv -s -\n\t\t;;\n\tlinksys,ea6350v3|\\\n\tlinksys,ea8300|\\\n\tlinksys,mr8300)\n\t\tmtd resetbc s_env || true\n\t\t;;\n\tnetgear,wac510)\n\t\tfw_setenv boot_cnt=0\n\t\t;;\n\tesac\n}\n"
  },
  {
    "path": "target/linux/ipq40xx/base-files/etc/inittab",
    "content": "# Copyright (c) 2013 The Linux Foundation. All rights reserved.\n::sysinit:/etc/init.d/rcS S boot\n::shutdown:/etc/init.d/rcS K shutdown\nttyMSM0::askfirst:/usr/libexec/login.sh\nttyMSM1::askfirst:/usr/libexec/login.sh\n"
  },
  {
    "path": "target/linux/ipq40xx/base-files/etc/uci-defaults/04_led_migration",
    "content": ". /lib/functions/migrations.sh\n\nboard=$(board_name)\n\ncase \"$board\" in\nasus,map-ac2200)\n\tmigrate_leds ':chan=-'\n\t;;\nengenius,emr3500)\n\tmigrate_leds \"emr3500:=\"\n\t;;\nengenius,ens620ext|\\\nzyxel,nbg6617)\n\tmigrate_leds \":wlan2G=:wlan2g\" \":wlan5G=:wlan5g\"\n\t;;\nnetgear,wac510)\n\tmigrate_leds \":wlan2g=:wlan-0\" \":wlan5g=:wlan-1\" \":act=:activity\"\n\t;;\nesac\n\nremove_devicename_leds\n\nmigrations_apply system\n\nexit 0\n"
  },
  {
    "path": "target/linux/ipq40xx/base-files/etc/uci-defaults/05_fix-compat-version",
    "content": ". /lib/functions.sh\n\ncase \"$(board_name)\" in\nezviz,cs-w3-wd1200g-eup)\n\tuci set system.@system[0].compat_version=\"2.0\"\n\tuci commit system\n\t;;\nesac\n\nexit 0\n"
  },
  {
    "path": "target/linux/ipq40xx/base-files/lib/preinit/05_set_iface_mac_ipq40xx.sh",
    "content": ". /lib/functions.sh\n\npreinit_set_mac_address() {\n\tcase $(board_name) in\n\tasus,map-ac2200)\n\t\tbase_mac=$(mtd_get_mac_binary_ubi Factory 0x1006)\n\t\tip link set dev eth0 address $(macaddr_add \"$base_mac\" 1)\n\t\tip link set dev eth1 address $(macaddr_add \"$base_mac\" 3)\n\t\t;;\n\tasus,rt-ac42u)\n\t\tip link set dev eth0 address $(mtd_get_mac_binary_ubi Factory 0x1006)\n\t\tip link set dev eth1 address $(mtd_get_mac_binary_ubi Factory 0x9006)\n\t\t;;\n\tengenius,eap2200)\n\t\tbase_mac=$(cat /sys/class/net/eth0/address)\n\t\tip link set dev eth1 address $(macaddr_add \"$base_mac\" 1)\n\t\t;;\n\tlinksys,ea8300|\\\n\tlinksys,mr8300)\n\t\tbase_mac=$(mtd_get_mac_ascii devinfo hw_mac_addr)\n\t\tip link set dev eth0 address \"$base_mac\"\n\t\tip link set dev eth1 address $(macaddr_add \"$base_mac\" 1)\n\t\t;;\n\tmeraki,mr33)\n\t\tmac_lan=$(get_mac_binary \"/sys/bus/i2c/devices/0-0050/eeprom\" 0x66)\n\t\t[ -n \"$mac_lan\" ] && ip link set dev eth0 address \"$mac_lan\"\n\t\t;;\n\tzyxel,nbg6617)\n\t\tbase_mac=$(cat /sys/class/net/eth0/address)\n\t\tip link set dev eth0 address $(macaddr_add \"$base_mac\" 2)\n\t\tip link set dev eth1 address $(macaddr_add \"$base_mac\" 3)\n\t\t;;\n\tesac\n}\n\nboot_hook_add preinit_main preinit_set_mac_address\n"
  },
  {
    "path": "target/linux/ipq40xx/base-files/lib/preinit/06_set_preinit_iface_ipq40xx.sh",
    "content": "set_preinit_iface() {\n\t. /lib/functions.sh\n\n\tcase $(board_name) in\n\taruba,ap-303| \\\n\tasus,rt-ac42u| \\\n\tasus,rt-ac58u| \\\n\tavm,fritzbox-4040| \\\n\tezviz,cs-w3-wd1200g-eup| \\\n\tglinet,gl-b1300| \\\n\tlinksys,ea8300| \\\n\tlinksys,mr8300| \\\n\tmeraki,mr33| \\\n\tzyxel,nbg6617)\n\t\tifname=eth0\n\t\t;;\n\tdevolo,magic-2-wifi-next)\n\t\tifname=eth1\n\t\t;;\n\tesac\n}\n\nboot_hook_add preinit_main set_preinit_iface\n"
  },
  {
    "path": "target/linux/ipq40xx/base-files/lib/upgrade/dualboot_datachk.sh",
    "content": "# The U-Boot loader with the datachk patchset for dualbooting requires image\n# sizes and checksums to be provided in the U-Boot environment.\n# The devices come with 2 main partitions - while one is active\n# sysupgrade will flash the other. The boot order is changed to boot the\n# newly flashed partition. If the new partition can't be booted due to\n# upgrade failures the previously used partition is loaded.\n\nplatform_do_upgrade_dualboot_datachk() {\n\tlocal tar_file=\"$1\"\n\tlocal restore_backup\n\tlocal primary_kernel_mtd\n\n\tlocal setenv_script=\"/tmp/fw_env_upgrade\"\n\n\tlocal kernel_mtd=\"$(find_mtd_index $PART_NAME)\"\n\tlocal kernel_offset=\"$(cat /sys/class/mtd/mtd${kernel_mtd}/offset)\"\n\tlocal total_size=\"$(cat /sys/class/mtd/mtd${kernel_mtd}/size)\"\n\n\t# detect to which flash region the new image is written to.\n\t#\n\t# 1. check what is the mtd index for the first flash region on this\n\t#    device\n\t# 2. check if the target partition (\"inactive\") has the mtd index of\n\t#    the first flash region\n\t#\n\t#    - when it is: the new bootseq will be 1,2 and the first region is\n\t#      modified\n\t#    - when it isnt: bootseq will be 2,1 and the second region is\n\t#      modified\n\t#\n\t# The detection has to be done via the hardcoded mtd partition because\n\t# the current boot might be done with the fallback region. Let us\n\t# assume that the current bootseq is 1,2. The bootloader detected that\n\t# the image in flash region 1 is corrupt and thus switches to flash\n\t# region 2. The bootseq in the u-boot-env is now still the same and\n\t# the sysupgrade code can now only rely on the actual mtd indexes and\n\t# not the bootseq variable to detect the currently booted flash\n\t# region/image.\n\t#\n\t# In the above example, an implementation which uses bootseq (\"1,2\") to\n\t# detect the currently booted image would assume that region 1 is booted\n\t# and then overwrite the variables for the wrong flash region (aka the\n\t# one which isn't modified). This could result in a device which doesn't\n\t# boot anymore to Linux until it was reflashed with ap51-flash.\n\tlocal next_boot_part=\"1\"\n\tcase \"$(board_name)\" in\n\tplasmacloud,pa1200|\\\n\topenmesh,a42)\n\t\tprimary_kernel_mtd=8\n\t\t;;\n\tplasmacloud,pa2200|\\\n\topenmesh,a62)\n\t\tprimary_kernel_mtd=10\n\t\t;;\n\t*)\n\t\techo \"failed to detect primary kernel mtd partition for board\"\n\t\treturn 1\n\t\t;;\n\tesac\n\t[ \"$kernel_mtd\" = \"$primary_kernel_mtd\" ] || next_boot_part=\"2\"\n\n\tlocal board_dir=$(tar tf $tar_file | grep -m 1 '^sysupgrade-.*/$')\n\tboard_dir=${board_dir%/}\n\n\tlocal kernel_length=$(tar xf $tar_file ${board_dir}/kernel -O | wc -c)\n\tlocal rootfs_length=$(tar xf $tar_file ${board_dir}/root -O | wc -c)\n\t# rootfs without EOF marker\n\trootfs_length=$((rootfs_length-4))\n\n\tlocal kernel_md5=$(tar xf $tar_file ${board_dir}/kernel -O | md5sum); kernel_md5=\"${kernel_md5%% *}\"\n\t# md5 checksum of rootfs with EOF marker\n\tlocal rootfs_md5=$(tar xf $tar_file ${board_dir}/root -O | dd bs=1 count=$rootfs_length | md5sum); rootfs_md5=\"${rootfs_md5%% *}\"\n\n\t#\n\t# add tar support to get_image() to use default_do_upgrade() instead?\n\t#\n\n\t# take care of restoring a saved config\n\t[ -n \"$UPGRADE_BACKUP\" ] && restore_backup=\"${MTD_CONFIG_ARGS} -j ${UPGRADE_BACKUP}\"\n\n\tmtd -q erase inactive\n\ttar xf $tar_file ${board_dir}/root -O | mtd -n -p $kernel_length $restore_backup write - $PART_NAME\n\ttar xf $tar_file ${board_dir}/kernel -O | mtd -n write - $PART_NAME\n\n\t# prepare new u-boot env\n\tif [ \"$next_boot_part\" = \"1\" ]; then\n\t\techo \"bootseq 1,2\" > $setenv_script\n\telse\n\t\techo \"bootseq 2,1\" > $setenv_script\n\tfi\n\n\tprintf \"kernel_size_%i 0x%08x\\n\" $next_boot_part $kernel_length >> $setenv_script\n\tprintf \"vmlinux_start_addr 0x%08x\\n\" ${kernel_offset} >> $setenv_script\n\tprintf \"vmlinux_size 0x%08x\\n\" ${kernel_length} >> $setenv_script\n\tprintf \"vmlinux_checksum %s\\n\" ${kernel_md5} >> $setenv_script\n\n\tprintf \"rootfs_size_%i 0x%08x\\n\" $next_boot_part $((total_size-kernel_length)) >> $setenv_script\n\tprintf \"rootfs_start_addr 0x%08x\\n\" $((kernel_offset+kernel_length)) >> $setenv_script\n\tprintf \"rootfs_size 0x%08x\\n\" ${rootfs_length} >> $setenv_script\n\tprintf \"rootfs_checksum %s\\n\" ${rootfs_md5} >> $setenv_script\n\n\t# store u-boot env changes\n\tmkdir -p /var/lock\n\tfw_setenv -s $setenv_script || {\n\t\techo \"failed to update U-Boot environment\"\n\t\treturn 1\n\t}\n}\n"
  },
  {
    "path": "target/linux/ipq40xx/base-files/lib/upgrade/linksys.sh",
    "content": "linksys_get_target_firmware() {\n\tlocal cur_boot_part mtd_ubi0\n\n\tcur_boot_part=\"$(/usr/sbin/fw_printenv -n boot_part)\"\n\tif [ -z \"${cur_boot_part}\" ]; then\n\t\tmtd_ubi0=$(cat /sys/devices/virtual/ubi/ubi0/mtd_num)\n\t\tcase \"$(grep -E \"^mtd${mtd_ubi0}:\" /proc/mtd | cut -d '\"' -f 2)\" in\n\t\tkernel|rootfs)\n\t\t\tcur_boot_part=1\n\t\t\t;;\n\t\talt_kernel|alt_rootfs)\n\t\t\tcur_boot_part=2\n\t\t\t;;\n\t\tesac\n\t\t>&2 printf \"Current boot_part='%s' selected from ubi0/mtd_num='%s'\" \\\n\t\t\t\"${cur_boot_part}\" \"${mtd_ubi0}\"\n\tfi\n\n\t# OEM U-Boot for EA6350v3, EA8300 and MR8300; bootcmd=\n\t#  if test $auto_recovery = no;\n\t#      then bootipq;\n\t#  elif test $boot_part = 1;\n\t#      then run bootpart1;\n\t#      else run bootpart2;\n\t#  fi\n\n\tcase \"$cur_boot_part\" in\n\t1)\n\t\tfw_setenv -s - <<-EOF\n\t\t\tboot_part 2\n\t\t\tauto_recovery yes\n\t\tEOF\n\t\tprintf \"alt_kernel\"\n\t\treturn\n\t\t;;\n\t2)\n\t\tfw_setenv -s - <<-EOF\n\t\t\tboot_part 1\n\t\t\tauto_recovery yes\n\t\tEOF\n\t\tprintf \"kernel\"\n\t\treturn\n\t\t;;\n\t*)\n\t\treturn\n\t\t;;\n\tesac\n}\n\nplatform_do_upgrade_linksys() {\n\tlocal magic_long=\"$(get_magic_long \"$1\")\"\n\n\tlocal rm_oem_fw_vols=\"squashfs ubifs\"\t# from OEM [alt_]rootfs UBI\n\tlocal vol\n\n\tmkdir -p /var/lock\n\tlocal part_label=\"$(linksys_get_target_firmware)\"\n\ttouch /var/lock/fw_printenv.lock\n\n\tif [ -z \"$part_label\" ]; then\n\t\techo \"cannot find target partition\"\n\t\texit 1\n\tfi\n\n\tlocal target_mtd=$(find_mtd_part \"$part_label\")\n\n\t[ \"$magic_long\" = \"73797375\" ] && {\n\t\tCI_KERNPART=\"$part_label\"\n\t\tif [ \"$part_label\" = \"kernel\" ]; then\n\t\t\tCI_UBIPART=\"rootfs\"\n\t\telse\n\t\t\tCI_UBIPART=\"alt_rootfs\"\n\t\tfi\n\n\t\tlocal mtdnum=\"$(find_mtd_index \"$CI_UBIPART\")\"\n\t\tif [ ! \"$mtdnum\" ]; then\n\t\t\techo \"cannot find ubi mtd partition $CI_UBIPART\"\n\t\t\treturn 1\n\t\tfi\n\n\t\tlocal ubidev=\"$(nand_find_ubi \"$CI_UBIPART\")\"\n\t\tif [ ! \"$ubidev\" ]; then\n\t\t\tubiattach -m \"$mtdnum\"\n\t\t\tsync\n\t\t\tubidev=\"$(nand_find_ubi \"$CI_UBIPART\")\"\n\t\tfi\n\n\t\tif [ \"$ubidev\" ]; then\n\t\t\tfor vol in $rm_oem_fw_vols; do\n\t\t\t\tubirmvol \"/dev/$ubidev\" -N \"$vol\" 2>/dev/null\n\t\t\tdone\n\t\tfi\n\n\t\t# complete std upgrade\n\t\tnand_upgrade_tar \"$1\"\n\t}\n\n\t[ \"$magic_long\" = \"27051956\" ] && {\n\t\techo \"writing \\\"$1\\\" image to \\\"$part_label\\\"\"\n\t\tget_image \"$1\" | mtd write - \"$part_label\"\n\t}\n}\n"
  },
  {
    "path": "target/linux/ipq40xx/base-files/lib/upgrade/netgear.sh",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n. /lib/functions.sh\n\nplatform_do_upgrade_netgear_orbi_upgrade() {\n\tcommand -v losetup >/dev/null || {\n\t\tlogger -s \"Upgrade failed: 'losetup' not installed.\"\n\t\treturn 1\n\t}\n\n\tlocal tar_file=$1\n\tlocal kernel=$2\n\tlocal rootfs=$3\n\n\t[ -z \"$kernel\" ] && kernel=$(find_mmc_part \"kernel\")\n\t[ -z \"$rootfs\" ] && rootfs=$(find_mmc_part \"rootfs\")\n\n\t[ -z \"$kernel\" ] && echo \"Upgrade failed: kernel partition not found! Rebooting...\" && reboot -f\n\t[ -z \"$rootfs\" ] && echo \"Upgrade failed: rootfs partition not found! Rebooting...\" && reboot -f\n\n\tnetgear_orbi_do_flash $tar_file $kernel $rootfs\n\n\techo \"sysupgrade successful\"\n\tumount -a\n\treboot -f\n}\n\nnetgear_orbi_do_flash() {\n\tlocal tar_file=$1\n\tlocal kernel=$2\n\tlocal rootfs=$3\n\n\t# keep sure its unbound\n\tlosetup --detach-all || {\n\t\techo \"Failed to detach all loop devices. Skip this try.\"\n\t\treboot -f\n\t}\n\n\t# use the first found directory in the tar archive\n\tlocal board_dir=$(tar tf $tar_file | grep -m 1 '^sysupgrade-.*/$')\n\tboard_dir=${board_dir%/}\n\n\techo \"flashing kernel to $kernel\"\n\ttar xf $tar_file ${board_dir}/kernel -O >$kernel\n\n\techo \"flashing rootfs to ${rootfs}\"\n\ttar xf $tar_file ${board_dir}/root -O >\"${rootfs}\"\n\n\t# a padded rootfs is needed for overlay fs creation\n\tlocal offset=$(tar xf $tar_file ${board_dir}/root -O | wc -c)\n\t[ $offset -lt 65536 ] && {\n\t\techo \"Wrong size for rootfs: $offset\"\n\t\tsleep 10\n\t\treboot -f\n\t}\n\n\t# Mount loop for rootfs_data\n\tlocal loopdev=\"$(losetup -f)\"\n\tlosetup -o $offset $loopdev $rootfs || {\n\t\techo \"Failed to mount looped rootfs_data.\"\n\t\tsleep 10\n\t\treboot -f\n\t}\n\n\techo \"Format new rootfs_data at position ${offset}.\"\n\tmkfs.ext4 -F -L rootfs_data $loopdev\n\tmkdir /tmp/new_root\n\tmount -t ext4 $loopdev /tmp/new_root && {\n\t\techo \"Saving config to rootfs_data at position ${offset}.\"\n\t\tcp -v \"$UPGRADE_BACKUP\" \"/tmp/new_root/$BACKUP_FILE\"\n\t\tumount /tmp/new_root\n\t}\n\n\t# Cleanup\n\tlosetup -d $loopdev >/dev/null 2>&1\n\tsync\n}\n"
  },
  {
    "path": "target/linux/ipq40xx/base-files/lib/upgrade/platform.sh",
    "content": "PART_NAME=firmware\nREQUIRE_IMAGE_METADATA=1\n\nRAMFS_COPY_BIN='fw_printenv fw_setenv'\nRAMFS_COPY_DATA='/etc/fw_env.config /var/lock/fw_printenv.lock'\n\nplatform_check_image() {\n\tcase \"$(board_name)\" in\n\tasus,rt-ac42u |\\\n\tasus,rt-ac58u)\n\t\tlocal ubidev=$(nand_find_ubi $CI_UBIPART)\n\t\tlocal asus_root=$(nand_find_volume $ubidev jffs2)\n\n\t\t[ -n \"$asus_root\" ] || return 0\n\n\t\tcat << EOF\njffs2 partition is still present.\nThere's probably no space left\nto install the filesystem.\n\nYou need to delete the jffs2 partition first:\n# ubirmvol /dev/ubi0 --name=jffs2\n\nOnce this is done. Retry.\nEOF\n\t\treturn 1\n\t\t;;\n\tzte,mf286d)\n\t\tCI_UBIPART=\"rootfs\"\n\t\tlocal mtdnum=\"$( find_mtd_index $CI_UBIPART )\"\n\t\t[ ! \"$mtdnum\" ] && return 1\n\t\tubiattach -m \"$mtdnum\" || true\n\t\tlocal ubidev=\"$( nand_find_ubi $CI_UBIPART )\"\n\t\tlocal ubi_rootfs=$(nand_find_volume $ubidev ubi_rootfs)\n\t\tlocal ubi_rootfs_data=$(nand_find_volume $ubidev ubi_rootfs_data)\n\n\t\t[ -n \"$ubi_rootfs\" ] || [ -n \"$ubi_rootfs_data\" ] || return 0\n\n\t\tcat << EOF\nubi_rootfs partition is still present.\n\nYou need to delete the stock partition first:\n# ubirmvol /dev/ubi0 -N ubi_rootfs\nPlease also delete ubi_rootfs_data, if exist:\n# ubirmvol /dev/ubi0 -N ubi_rootfs_data\n\nOnce this is done. Retry.\nEOF\n\t\treturn 1\n\t\t;;\n\tesac\n\treturn 0;\n}\n\naskey_do_upgrade() {\n\tlocal tar_file=\"$1\"\n\n\tlocal board_dir=$(tar tf $tar_file | grep -m 1 '^sysupgrade-.*/$')\n\tboard_dir=${board_dir%/}\n\n\ttar Oxf $tar_file ${board_dir}/root | mtd write - rootfs\n\n\tnand_do_upgrade \"$1\"\n}\n\nzyxel_do_upgrade() {\n\tlocal tar_file=\"$1\"\n\n\tlocal board_dir=$(tar tf $tar_file | grep -m 1 '^sysupgrade-.*/$')\n\tboard_dir=${board_dir%/}\n\n\ttar Oxf $tar_file ${board_dir}/kernel | mtd write - kernel\n\n\tif [ -n \"$UPGRADE_BACKUP\" ]; then\n\t\ttar Oxf $tar_file ${board_dir}/root | mtd -j \"$UPGRADE_BACKUP\" write - rootfs\n\telse\n\t\ttar Oxf $tar_file ${board_dir}/root | mtd write - rootfs\n\tfi\n}\n\nplatform_do_upgrade_mikrotik_nand() {\n\tlocal fw_mtd=$(find_mtd_part kernel)\n\tfw_mtd=\"${fw_mtd/block/}\"\n\t[ -n \"$fw_mtd\" ] || return\n\n\tlocal board_dir=$(tar tf \"$1\" | grep -m 1 '^sysupgrade-.*/$')\n\tboard_dir=${board_dir%/}\n\t[ -n \"$board_dir\" ] || return\n\n\tlocal kernel_len=$(tar xf \"$1\" ${board_dir}/kernel -O | wc -c)\n\t[ -n \"$kernel_len\" ] || return\n\n\ttar xf \"$1\" ${board_dir}/kernel -O | ubiformat \"$fw_mtd\" -y -S $kernel_len -f -\n\n\tCI_KERNPART=\"none\"\n\tnand_do_upgrade \"$1\"\n}\n\nplatform_do_upgrade() {\n\tcase \"$(board_name)\" in\n\t8dev,jalapeno |\\\n\taruba,ap-303 |\\\n\taruba,ap-303h |\\\n\taruba,ap-365 |\\\n\tavm,fritzbox-7530 |\\\n\tavm,fritzrepeater-1200 |\\\n\tavm,fritzrepeater-3000 |\\\n\tbuffalo,wtr-m2133hp |\\\n\tcilab,meshpoint-one |\\\n\tedgecore,ecw5211 |\\\n\tedgecore,oap100 |\\\n\tengenius,eap2200 |\\\n\tglinet,gl-ap1300 |\\\n\tluma,wrtq-329acn |\\\n\tmobipromo,cm520-79f |\\\n\tnetgear,wac510 |\\\n\tp2w,r619ac-64m |\\\n\tp2w,r619ac-128m |\\\n\tqxwlan,e2600ac-c2)\n\t\tnand_do_upgrade \"$1\"\n\t\t;;\n\tglinet,gl-b2200)\n\t\tCI_KERNPART=\"0:HLOS\"\n\t\tCI_ROOTPART=\"rootfs\"\n\t\tCI_DATAPART=\"rootfs_data\"\n\t\temmc_do_upgrade \"$1\"\n\t\t;;\n\talfa-network,ap120c-ac)\n\t\tpart=\"$(awk -F 'ubi.mtd=' '{printf $2}' /proc/cmdline | sed -e 's/ .*$//')\"\n\t\tif [ \"$part\" = \"rootfs1\" ]; then\n\t\t\tfw_setenv active 2 || exit 1\n\t\t\tCI_UBIPART=\"rootfs2\"\n\t\telse\n\t\t\tfw_setenv active 1 || exit 1\n\t\t\tCI_UBIPART=\"rootfs1\"\n\t\tfi\n\t\tnand_do_upgrade \"$1\"\n\t\t;;\n\tasus,map-ac2200)\n\t\tCI_KERNPART=\"linux\"\n\t\tnand_do_upgrade \"$1\"\n\t\t;;\n\tasus,rt-ac42u |\\\n\tasus,rt-ac58u)\n\t\tCI_KERNPART=\"linux\"\n\t\tnand_do_upgrade \"$1\"\n\t\t;;\n\tcellc,rtl30vw)\n\t\tCI_UBIPART=\"ubifs\"\n\t\taskey_do_upgrade \"$1\"\n\t\t;;\n\tcompex,wpj419)\n\t\tnand_do_upgrade \"$1\"\n\t\t;;\n\tgoogle,wifi)\n\t\texport_bootdevice\n\t\texport_partdevice CI_ROOTDEV 0\n\t\tCI_KERNPART=\"kernel\"\n\t\tCI_ROOTPART=\"rootfs\"\n\t\temmc_do_upgrade \"$1\"\n\t\t;;\n\tlinksys,ea6350v3 |\\\n\tlinksys,ea8300 |\\\n\tlinksys,mr8300)\n\t\tplatform_do_upgrade_linksys \"$1\"\n\t\t;;\n\tmeraki,mr33)\n\t\tCI_KERNPART=\"part.safe\"\n\t\tnand_do_upgrade \"$1\"\n\t\t;;\n\tmikrotik,cap-ac|\\\n\tmikrotik,hap-ac2|\\\n\tmikrotik,lhgg-60ad|\\\n\tmikrotik,sxtsq-5-ac)\n\t\t[ \"$(rootfs_type)\" = \"tmpfs\" ] && mtd erase firmware\n\t\tdefault_do_upgrade \"$1\"\n\t\t;;\n\tmikrotik,hap-ac3)\n\t\tplatform_do_upgrade_mikrotik_nand \"$1\"\n\t\t;;\n\tnetgear,rbr50 |\\\n\tnetgear,rbs50 |\\\n\tnetgear,srr60 |\\\n\tnetgear,srs60)\n\t\tplatform_do_upgrade_netgear_orbi_upgrade \"$1\"\n\t\t;;\n\topenmesh,a42 |\\\n\topenmesh,a62 |\\\n\tplasmacloud,pa1200 |\\\n\tplasmacloud,pa2200)\n\t\tPART_NAME=\"inactive\"\n\t\tplatform_do_upgrade_dualboot_datachk \"$1\"\n\t\t;;\n\tteltonika,rutx10 |\\\n\tzte,mf286d)\n\t\tCI_UBIPART=\"rootfs\"\n\t\tnand_do_upgrade \"$1\"\n\t\t;;\n\tzyxel,nbg6617)\n\t\tzyxel_do_upgrade \"$1\"\n\t\t;;\n\t*)\n\t\tdefault_do_upgrade \"$1\"\n\t\t;;\n\tesac\n}\n\nplatform_copy_config() {\n\tcase \"$(board_name)\" in\n\tglinet,gl-b2200 |\\\n\tgoogle,wifi)\n\t\temmc_copy_config\n\t\t;;\n\tesac\n\treturn 0;\n}\n"
  },
  {
    "path": "target/linux/ipq40xx/chromium/config-default",
    "content": "CONFIG_BLK_DEV_SD=y\nCONFIG_SCSI=y\nCONFIG_SCSI_COMMON=y\nCONFIG_SG_POOL=y\nCONFIG_USB_DWC3=y\nCONFIG_USB_DWC3_HOST=y\nCONFIG_USB_DWC3_QCOM=y\nCONFIG_USB_STORAGE=y\nCONFIG_USB_XHCI_HCD=y\nCONFIG_USB_XHCI_PLATFORM=y\n"
  },
  {
    "path": "target/linux/ipq40xx/chromium/target.mk",
    "content": "BOARDNAME:=Google Chromium\nFEATURES += emmc boot-part rootfs-part\n"
  },
  {
    "path": "target/linux/ipq40xx/config-5.10",
    "content": "CONFIG_ALIGNMENT_TRAP=y\n# CONFIG_APQ_GCC_8084 is not set\n# CONFIG_APQ_MMCC_8084 is not set\nCONFIG_AR40XX_PHY=y\nCONFIG_ARCH_32BIT_OFF_T=y\nCONFIG_ARCH_HIBERNATION_POSSIBLE=y\nCONFIG_ARCH_IPQ40XX=y\nCONFIG_ARCH_KEEP_MEMBLOCK=y\n# CONFIG_ARCH_MDM9615 is not set\nCONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y\n# CONFIG_ARCH_MSM8960 is not set\n# CONFIG_ARCH_MSM8974 is not set\n# CONFIG_ARCH_MSM8X60 is not set\nCONFIG_ARCH_MULTIPLATFORM=y\nCONFIG_ARCH_MULTI_V6_V7=y\nCONFIG_ARCH_MULTI_V7=y\nCONFIG_ARCH_NR_GPIO=0\nCONFIG_ARCH_OPTIONAL_KERNEL_RWX=y\nCONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y\nCONFIG_ARCH_QCOM=y\nCONFIG_ARCH_SELECT_MEMORY_MODEL=y\nCONFIG_ARCH_SPARSEMEM_ENABLE=y\nCONFIG_ARCH_SUSPEND_POSSIBLE=y\nCONFIG_ARM=y\nCONFIG_ARM_AMBA=y\nCONFIG_ARM_APPENDED_DTB=y\nCONFIG_ARM_ARCH_TIMER=y\nCONFIG_ARM_ARCH_TIMER_EVTSTREAM=y\n# CONFIG_ARM_ATAG_DTB_COMPAT is not set\nCONFIG_ARM_CPUIDLE=y\n# CONFIG_ARM_CPU_TOPOLOGY is not set\nCONFIG_ARM_CRYPTO=y\nCONFIG_ARM_GIC=y\nCONFIG_ARM_HAS_SG_CHAIN=y\nCONFIG_ARM_L1_CACHE_SHIFT=6\nCONFIG_ARM_L1_CACHE_SHIFT_6=y\nCONFIG_ARM_PATCH_IDIV=y\nCONFIG_ARM_PATCH_PHYS_VIRT=y\n# CONFIG_ARM_QCOM_CPUFREQ_HW is not set\n# CONFIG_ARM_QCOM_CPUFREQ_NVMEM is not set\n# CONFIG_ARM_QCOM_SPM_CPUIDLE is not set\n# CONFIG_ARM_SMMU is not set\nCONFIG_ARM_THUMB=y\nCONFIG_ARM_UNWIND=y\nCONFIG_ARM_VIRT_EXT=y\nCONFIG_AT803X_PHY=y\nCONFIG_AUTO_ZRELADDR=y\nCONFIG_BCH=y\nCONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y\nCONFIG_BLK_CMDLINE_PARSER=y\nCONFIG_BLK_DEV_LOOP=y\nCONFIG_BLK_MQ_PCI=y\nCONFIG_BOUNCE=y\n# CONFIG_CACHE_L2X0 is not set\nCONFIG_CLKDEV_LOOKUP=y\nCONFIG_CLKSRC_QCOM=y\nCONFIG_CLONE_BACKWARDS=y\nCONFIG_CMDLINE_PARTITION=y\nCONFIG_COMMON_CLK=y\nCONFIG_COMMON_CLK_QCOM=y\nCONFIG_COMPAT_32BIT_TIME=y\nCONFIG_CPUFREQ_DT=y\nCONFIG_CPUFREQ_DT_PLATDEV=y\nCONFIG_CPU_32v6K=y\nCONFIG_CPU_32v7=y\nCONFIG_CPU_ABRT_EV7=y\nCONFIG_CPU_CACHE_V7=y\nCONFIG_CPU_CACHE_VIPT=y\nCONFIG_CPU_COPY_V6=y\nCONFIG_CPU_CP15=y\nCONFIG_CPU_CP15_MMU=y\nCONFIG_CPU_FREQ=y\nCONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y\n# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set\nCONFIG_CPU_FREQ_GOV_ATTR_SET=y\nCONFIG_CPU_FREQ_GOV_COMMON=y\n# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set\nCONFIG_CPU_FREQ_GOV_ONDEMAND=y\nCONFIG_CPU_FREQ_GOV_PERFORMANCE=y\n# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set\n# CONFIG_CPU_FREQ_GOV_USERSPACE is not set\nCONFIG_CPU_FREQ_STAT=y\nCONFIG_CPU_HAS_ASID=y\nCONFIG_CPU_IDLE=y\nCONFIG_CPU_IDLE_GOV_LADDER=y\nCONFIG_CPU_IDLE_GOV_MENU=y\nCONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y\nCONFIG_CPU_PABRT_V7=y\nCONFIG_CPU_PM=y\nCONFIG_CPU_RMAP=y\nCONFIG_CPU_SPECTRE=y\nCONFIG_CPU_THERMAL=y\nCONFIG_CPU_THUMB_CAPABLE=y\nCONFIG_CPU_TLB_V7=y\nCONFIG_CPU_V7=y\nCONFIG_CRC16=y\n# CONFIG_CRC32_SARWATE is not set\nCONFIG_CRC32_SLICEBY8=y\nCONFIG_CRYPTO_AES_ARM=y\nCONFIG_CRYPTO_AES_ARM_BS=y\nCONFIG_CRYPTO_CBC=y\nCONFIG_CRYPTO_CRYPTD=y\nCONFIG_CRYPTO_DEFLATE=y\nCONFIG_CRYPTO_DES=y\nCONFIG_CRYPTO_DEV_QCE=y\n# CONFIG_CRYPTO_DEV_QCE_ENABLE_ALL is not set\n# CONFIG_CRYPTO_DEV_QCE_ENABLE_SHA is not set\nCONFIG_CRYPTO_DEV_QCE_ENABLE_SKCIPHER=y\nCONFIG_CRYPTO_DEV_QCE_SKCIPHER=y\nCONFIG_CRYPTO_DEV_QCE_SW_MAX_LEN=512\nCONFIG_CRYPTO_DEV_QCOM_RNG=y\nCONFIG_CRYPTO_DRBG=y\nCONFIG_CRYPTO_DRBG_HMAC=y\nCONFIG_CRYPTO_DRBG_MENU=y\nCONFIG_CRYPTO_ECB=y\nCONFIG_CRYPTO_HASH_INFO=y\nCONFIG_CRYPTO_HMAC=y\nCONFIG_CRYPTO_HW=y\nCONFIG_CRYPTO_JITTERENTROPY=y\nCONFIG_CRYPTO_LIB_DES=y\nCONFIG_CRYPTO_LIB_SHA256=y\nCONFIG_CRYPTO_LZO=y\nCONFIG_CRYPTO_RNG=y\nCONFIG_CRYPTO_RNG2=y\nCONFIG_CRYPTO_RNG_DEFAULT=y\nCONFIG_CRYPTO_SEQIV=y\nCONFIG_CRYPTO_SHA1=y\nCONFIG_CRYPTO_SHA256=y\nCONFIG_CRYPTO_SHA256_ARM=y\nCONFIG_CRYPTO_SIMD=y\nCONFIG_CRYPTO_XTS=y\nCONFIG_CRYPTO_ZSTD=y\nCONFIG_DCACHE_WORD_ACCESS=y\nCONFIG_DEBUG_LL_INCLUDE=\"mach/debug-macro.S\"\nCONFIG_DEBUG_MISC=y\nCONFIG_DMADEVICES=y\nCONFIG_DMA_ENGINE=y\nCONFIG_DMA_OF=y\nCONFIG_DMA_OPS=y\nCONFIG_DMA_REMAP=y\nCONFIG_DMA_SHARED_BUFFER=y\nCONFIG_DMA_VIRTUAL_CHANNELS=y\nCONFIG_DTC=y\nCONFIG_DT_IDLE_STATES=y\nCONFIG_DYNAMIC_DEBUG=y\nCONFIG_EDAC_ATOMIC_SCRUB=y\nCONFIG_EDAC_SUPPORT=y\nCONFIG_EEPROM_AT24=y\nCONFIG_ESSEDMA=y\nCONFIG_EXTCON=y\nCONFIG_FIXED_PHY=y\nCONFIG_FIX_EARLYCON_MEM=y\nCONFIG_FW_LOADER_PAGED_BUF=y\nCONFIG_GENERIC_ALLOCATOR=y\nCONFIG_GENERIC_BUG=y\nCONFIG_GENERIC_CLOCKEVENTS=y\nCONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y\nCONFIG_GENERIC_CPU_AUTOPROBE=y\nCONFIG_GENERIC_EARLY_IOREMAP=y\nCONFIG_GENERIC_GETTIMEOFDAY=y\nCONFIG_GENERIC_IDLE_POLL_SETUP=y\nCONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y\nCONFIG_GENERIC_IRQ_MULTI_HANDLER=y\nCONFIG_GENERIC_IRQ_SHOW=y\nCONFIG_GENERIC_IRQ_SHOW_LEVEL=y\nCONFIG_GENERIC_MSI_IRQ=y\nCONFIG_GENERIC_MSI_IRQ_DOMAIN=y\nCONFIG_GENERIC_PCI_IOMAP=y\nCONFIG_GENERIC_PHY=y\nCONFIG_GENERIC_PINCONF=y\nCONFIG_GENERIC_PINCTRL_GROUPS=y\nCONFIG_GENERIC_PINMUX_FUNCTIONS=y\nCONFIG_GENERIC_SCHED_CLOCK=y\nCONFIG_GENERIC_SMP_IDLE_THREAD=y\nCONFIG_GENERIC_STRNCPY_FROM_USER=y\nCONFIG_GENERIC_STRNLEN_USER=y\nCONFIG_GENERIC_TIME_VSYSCALL=y\nCONFIG_GENERIC_VDSO_32=y\nCONFIG_GPIOLIB=y\nCONFIG_GPIOLIB_IRQCHIP=y\nCONFIG_GPIO_74X164=y\nCONFIG_GPIO_WATCHDOG=y\nCONFIG_GPIO_WATCHDOG_ARCH_INITCALL=y\nCONFIG_HANDLE_DOMAIN_IRQ=y\nCONFIG_HARDEN_BRANCH_PREDICTOR=y\nCONFIG_HARDIRQS_SW_RESEND=y\nCONFIG_HAS_DMA=y\nCONFIG_HAS_IOMEM=y\nCONFIG_HAS_IOPORT_MAP=y\nCONFIG_HAVE_SMP=y\nCONFIG_HIGHMEM=y\nCONFIG_HIGHPTE=y\nCONFIG_HWSPINLOCK=y\nCONFIG_HWSPINLOCK_QCOM=y\nCONFIG_HW_RANDOM=y\nCONFIG_HW_RANDOM_OPTEE=y\nCONFIG_HZ_FIXED=0\nCONFIG_I2C=y\nCONFIG_I2C_BOARDINFO=y\nCONFIG_I2C_CHARDEV=y\nCONFIG_I2C_HELPER_AUTO=y\n# CONFIG_I2C_QCOM_CCI is not set\nCONFIG_I2C_QUP=y\nCONFIG_INITRAMFS_SOURCE=\"\"\n# CONFIG_IOMMU_DEBUGFS is not set\n# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set\n# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set\nCONFIG_IOMMU_SUPPORT=y\nCONFIG_IO_URING=y\n# CONFIG_IPQ_APSS_PLL is not set\nCONFIG_IPQ_GCC_4019=y\n# CONFIG_IPQ_GCC_6018 is not set\n# CONFIG_IPQ_GCC_806X is not set\n# CONFIG_IPQ_GCC_8074 is not set\n# CONFIG_IPQ_LCC_806X is not set\nCONFIG_IRQCHIP=y\nCONFIG_IRQ_DOMAIN=y\nCONFIG_IRQ_DOMAIN_HIERARCHY=y\nCONFIG_IRQ_FASTEOI_HIERARCHY_HANDLERS=y\nCONFIG_IRQ_FORCED_THREADING=y\nCONFIG_IRQ_WORK=y\n# CONFIG_KPSS_XCC is not set\n# CONFIG_KRAITCC is not set\nCONFIG_LEDS_LP5523=y\nCONFIG_LEDS_LP5562=y\nCONFIG_LEDS_LP55XX_COMMON=y\nCONFIG_LEDS_TLC591XX=y\nCONFIG_LED_TRIGGER_PHY=y\nCONFIG_LIBFDT=y\nCONFIG_LOCK_DEBUGGING_SUPPORT=y\nCONFIG_LOCK_SPIN_ON_OWNER=y\nCONFIG_LZO_COMPRESS=y\nCONFIG_LZO_DECOMPRESS=y\nCONFIG_MDIO_BITBANG=y\nCONFIG_MDIO_BUS=y\nCONFIG_MDIO_DEVICE=y\nCONFIG_MDIO_DEVRES=y\nCONFIG_MDIO_GPIO=y\nCONFIG_MDIO_IPQ4019=y\n# CONFIG_MDM_GCC_9615 is not set\n# CONFIG_MDM_LCC_9615 is not set\nCONFIG_MEMFD_CREATE=y\n# CONFIG_MFD_HI6421_SPMI is not set\n# CONFIG_MFD_QCOM_RPM is not set\n# CONFIG_MFD_SPMI_PMIC is not set\nCONFIG_MFD_SYSCON=y\nCONFIG_MIGHT_HAVE_CACHE_L2X0=y\nCONFIG_MIGRATION=y\nCONFIG_MMC=y\nCONFIG_MMC_BLOCK=y\nCONFIG_MMC_CQHCI=y\nCONFIG_MMC_SDHCI=y\nCONFIG_MMC_SDHCI_IO_ACCESSORS=y\nCONFIG_MMC_SDHCI_MSM=y\n# CONFIG_MMC_SDHCI_PCI is not set\nCONFIG_MMC_SDHCI_PLTFM=y\nCONFIG_MODULES_USE_ELF_REL=y\n# CONFIG_MSM_GCC_8660 is not set\n# CONFIG_MSM_GCC_8916 is not set\n# CONFIG_MSM_GCC_8939 is not set\n# CONFIG_MSM_GCC_8960 is not set\n# CONFIG_MSM_GCC_8974 is not set\n# CONFIG_MSM_GCC_8994 is not set\n# CONFIG_MSM_GCC_8996 is not set\n# CONFIG_MSM_GCC_8998 is not set\n# CONFIG_MSM_GPUCC_8998 is not set\n# CONFIG_MSM_LCC_8960 is not set\n# CONFIG_MSM_MMCC_8960 is not set\n# CONFIG_MSM_MMCC_8974 is not set\n# CONFIG_MSM_MMCC_8996 is not set\n# CONFIG_MSM_MMCC_8998 is not set\nCONFIG_MTD_CMDLINE_PARTS=y\nCONFIG_MTD_NAND_CORE=y\nCONFIG_MTD_NAND_ECC=y\nCONFIG_MTD_NAND_ECC_SW_BCH=y\nCONFIG_MTD_NAND_ECC_SW_HAMMING=y\nCONFIG_MTD_NAND_QCOM=y\nCONFIG_MTD_RAW_NAND=y\nCONFIG_MTD_SPI_NAND=y\nCONFIG_MTD_SPI_NOR=y\nCONFIG_MTD_SPLIT_FIRMWARE=y\nCONFIG_MTD_SPLIT_FIT_FW=y\nCONFIG_MTD_SPLIT_WRGG_FW=y\nCONFIG_MTD_UBI=y\nCONFIG_MTD_UBI_BEB_LIMIT=20\nCONFIG_MTD_UBI_BLOCK=y\nCONFIG_MTD_UBI_WL_THRESHOLD=4096\nCONFIG_MUTEX_SPIN_ON_OWNER=y\nCONFIG_NEED_DMA_MAP_STATE=y\nCONFIG_NEON=y\nCONFIG_NET_FLOW_LIMIT=y\nCONFIG_NET_PTP_CLASSIFY=y\nCONFIG_NLS=y\nCONFIG_NO_HZ=y\nCONFIG_NO_HZ_COMMON=y\nCONFIG_NO_HZ_IDLE=y\nCONFIG_NR_CPUS=4\nCONFIG_NVMEM=y\n# CONFIG_NVMEM_SPMI_SDAM is not set\nCONFIG_NVMEM_SYSFS=y\nCONFIG_OF=y\nCONFIG_OF_ADDRESS=y\nCONFIG_OF_EARLY_FLATTREE=y\nCONFIG_OF_FLATTREE=y\nCONFIG_OF_GPIO=y\nCONFIG_OF_IRQ=y\nCONFIG_OF_KOBJ=y\nCONFIG_OF_MDIO=y\nCONFIG_OF_NET=y\nCONFIG_OLD_SIGACTION=y\nCONFIG_OLD_SIGSUSPEND3=y\nCONFIG_OPTEE=y\nCONFIG_OPTEE_SHM_NUM_PRIV_PAGES=1\nCONFIG_PADATA=y\nCONFIG_PAGE_OFFSET=0xC0000000\nCONFIG_PCI=y\nCONFIG_PCIEAER=y\nCONFIG_PCIEPORTBUS=y\nCONFIG_PCIE_DW=y\nCONFIG_PCIE_DW_HOST=y\nCONFIG_PCIE_QCOM=y\nCONFIG_PCI_DISABLE_COMMON_QUIRKS=y\nCONFIG_PCI_DOMAINS=y\nCONFIG_PCI_DOMAINS_GENERIC=y\nCONFIG_PCI_MSI=y\nCONFIG_PCI_MSI_IRQ_DOMAIN=y\nCONFIG_PERF_USE_VMALLOC=y\nCONFIG_PGTABLE_LEVELS=2\nCONFIG_PHYLIB=y\n# CONFIG_PHY_QCOM_APQ8064_SATA is not set\nCONFIG_PHY_QCOM_IPQ4019_USB=y\n# CONFIG_PHY_QCOM_IPQ806X_SATA is not set\n# CONFIG_PHY_QCOM_IPQ806X_USB is not set\n# CONFIG_PHY_QCOM_PCIE2 is not set\n# CONFIG_PHY_QCOM_QMP is not set\n# CONFIG_PHY_QCOM_QUSB2 is not set\n# CONFIG_PHY_QCOM_USB_HS_28NM is not set\n# CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2 is not set\n# CONFIG_PHY_QCOM_USB_SS is not set\nCONFIG_PINCTRL=y\n# CONFIG_PINCTRL_APQ8064 is not set\n# CONFIG_PINCTRL_APQ8084 is not set\nCONFIG_PINCTRL_IPQ4019=y\n# CONFIG_PINCTRL_IPQ6018 is not set\n# CONFIG_PINCTRL_IPQ8064 is not set\n# CONFIG_PINCTRL_IPQ8074 is not set\n# CONFIG_PINCTRL_MDM9615 is not set\nCONFIG_PINCTRL_MSM=y\n# CONFIG_PINCTRL_MSM8226 is not set\n# CONFIG_PINCTRL_MSM8660 is not set\n# CONFIG_PINCTRL_MSM8916 is not set\n# CONFIG_PINCTRL_MSM8960 is not set\n# CONFIG_PINCTRL_MSM8976 is not set\n# CONFIG_PINCTRL_MSM8994 is not set\n# CONFIG_PINCTRL_MSM8996 is not set\n# CONFIG_PINCTRL_MSM8998 is not set\n# CONFIG_PINCTRL_QCOM_SPMI_PMIC is not set\n# CONFIG_PINCTRL_QCOM_SSBI_PMIC is not set\n# CONFIG_PINCTRL_QCS404 is not set\n# CONFIG_PINCTRL_SC7180 is not set\n# CONFIG_PINCTRL_SDM660 is not set\n# CONFIG_PINCTRL_SDM845 is not set\n# CONFIG_PINCTRL_SM8150 is not set\n# CONFIG_PINCTRL_SM8250 is not set\nCONFIG_PM_OPP=y\nCONFIG_POWER_RESET=y\nCONFIG_POWER_RESET_MSM=y\nCONFIG_POWER_RESET_GPIO_RESTART=y\nCONFIG_POWER_SUPPLY=y\nCONFIG_PPS=y\nCONFIG_PRINTK_TIME=y\nCONFIG_PTP_1588_CLOCK=y\nCONFIG_QCA807X_PHY=y\nCONFIG_QCOM_A53PLL=y\nCONFIG_QCOM_BAM_DMA=y\n# CONFIG_QCOM_COMMAND_DB is not set\n# CONFIG_QCOM_CPR is not set\n# CONFIG_QCOM_EBI2 is not set\n# CONFIG_QCOM_GENI_SE is not set\n# CONFIG_QCOM_GSBI is not set\n# CONFIG_QCOM_HFPLL is not set\n# CONFIG_QCOM_IOMMU is not set\n# CONFIG_QCOM_LLCC is not set\n# CONFIG_QCOM_OCMEM is not set\n# CONFIG_QCOM_PDC is not set\nCONFIG_QCOM_QFPROM=y\n# CONFIG_QCOM_RMTFS_MEM is not set\n# CONFIG_QCOM_RPMH is not set\nCONFIG_QCOM_SCM=y\n# CONFIG_QCOM_SCM_DOWNLOAD_MODE_DEFAULT is not set\nCONFIG_QCOM_SMEM=y\n# CONFIG_QCOM_SMSM is not set\n# CONFIG_QCOM_SOCINFO is not set\nCONFIG_QCOM_TCSR=y\n# CONFIG_QCOM_TSENS is not set\nCONFIG_QCOM_WDT=y\n# CONFIG_QCS_GCC_404 is not set\n# CONFIG_QCS_Q6SSTOP_404 is not set\n# CONFIG_QCS_TURING_404 is not set\nCONFIG_RAS=y\nCONFIG_RATIONAL=y\nCONFIG_REGMAP=y\nCONFIG_REGMAP_I2C=y\nCONFIG_REGMAP_MMIO=y\nCONFIG_REGULATOR=y\nCONFIG_REGULATOR_FIXED_VOLTAGE=y\n# CONFIG_REGULATOR_QCOM_LABIBB is not set\n# CONFIG_REGULATOR_QCOM_SPMI is not set\n# CONFIG_REGULATOR_QCOM_USB_VBUS is not set\nCONFIG_REGULATOR_VCTRL=y\nCONFIG_REGULATOR_VQMMC_IPQ4019=y\nCONFIG_RESET_CONTROLLER=y\n# CONFIG_RESET_QCOM_AOSS is not set\n# CONFIG_RESET_QCOM_PDC is not set\nCONFIG_RFS_ACCEL=y\nCONFIG_RPS=y\nCONFIG_RTC_CLASS=y\nCONFIG_RTC_I2C_AND_SPI=y\nCONFIG_RTC_MC146818_LIB=y\nCONFIG_RWSEM_SPIN_ON_OWNER=y\n# CONFIG_SC_DISPCC_7180 is not set\n# CONFIG_SC_GCC_7180 is not set\n# CONFIG_SC_GPUCC_7180 is not set\n# CONFIG_SC_LPASS_CORECC_7180 is not set\n# CONFIG_SC_MSS_7180 is not set\n# CONFIG_SC_VIDEOCC_7180 is not set\n# CONFIG_SDM_CAMCC_845 is not set\n# CONFIG_SDM_DISPCC_845 is not set\n# CONFIG_SDM_GCC_660 is not set\n# CONFIG_SDM_GCC_845 is not set\n# CONFIG_SDM_GPUCC_845 is not set\n# CONFIG_SDM_LPASSCC_845 is not set\n# CONFIG_SDM_VIDEOCC_845 is not set\nCONFIG_SERIAL_8250_FSL=y\nCONFIG_SERIAL_MCTRL_GPIO=y\nCONFIG_SERIAL_MSM=y\nCONFIG_SERIAL_MSM_CONSOLE=y\nCONFIG_SGL_ALLOC=y\nCONFIG_SMP=y\nCONFIG_SMP_ON_UP=y\n# CONFIG_SM_GCC_8150 is not set\n# CONFIG_SM_GCC_8250 is not set\n# CONFIG_SM_GPUCC_8150 is not set\n# CONFIG_SM_GPUCC_8250 is not set\n# CONFIG_SM_VIDEOCC_8150 is not set\n# CONFIG_SM_VIDEOCC_8250 is not set\nCONFIG_SPARSE_IRQ=y\nCONFIG_SPI=y\nCONFIG_SPI_BITBANG=y\nCONFIG_SPI_GPIO=y\nCONFIG_SPI_MASTER=y\nCONFIG_SPI_MEM=y\nCONFIG_SPI_QUP=y\nCONFIG_SPMI=y\n# CONFIG_SPMI_HISI3670 is not set\nCONFIG_SPMI_MSM_PMIC_ARB=y\n# CONFIG_SPMI_PMIC_CLKDIV is not set\nCONFIG_SRCU=y\nCONFIG_SWCONFIG=y\nCONFIG_SWCONFIG_LEDS=y\nCONFIG_SWPHY=y\nCONFIG_SWP_EMULATE=y\nCONFIG_SYS_SUPPORTS_APM_EMULATION=y\nCONFIG_TEE=y\nCONFIG_THERMAL=y\nCONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y\nCONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0\nCONFIG_THERMAL_GOV_STEP_WISE=y\nCONFIG_THERMAL_OF=y\nCONFIG_TICK_CPU_ACCOUNTING=y\nCONFIG_TIMER_OF=y\nCONFIG_TIMER_PROBE=y\nCONFIG_TREE_RCU=y\nCONFIG_TREE_SRCU=y\nCONFIG_UBIFS_FS=y\nCONFIG_UEVENT_HELPER_PATH=\"\"\nCONFIG_UNCOMPRESS_INCLUDE=\"debug/uncompress.h\"\nCONFIG_UNWINDER_ARM=y\nCONFIG_USB=y\nCONFIG_USB_COMMON=y\nCONFIG_USB_SUPPORT=y\nCONFIG_USE_OF=y\nCONFIG_VFP=y\nCONFIG_VFPv3=y\nCONFIG_WATCHDOG_CORE=y\nCONFIG_XPS=y\nCONFIG_XXHASH=y\nCONFIG_XZ_DEC_ARM=y\nCONFIG_XZ_DEC_BCJ=y\nCONFIG_ZBOOT_ROM_BSS=0\nCONFIG_ZBOOT_ROM_TEXT=0\nCONFIG_ZLIB_DEFLATE=y\nCONFIG_ZLIB_INFLATE=y\nCONFIG_ZSTD_COMPRESS=y\nCONFIG_ZSTD_DECOMPRESS=y\n"
  },
  {
    "path": "target/linux/ipq40xx/config-5.15",
    "content": "CONFIG_ALIGNMENT_TRAP=y\n# CONFIG_APQ_GCC_8084 is not set\n# CONFIG_APQ_MMCC_8084 is not set\nCONFIG_AR40XX_PHY=y\nCONFIG_ARCH_32BIT_OFF_T=y\nCONFIG_ARCH_HIBERNATION_POSSIBLE=y\nCONFIG_ARCH_IPQ40XX=y\nCONFIG_ARCH_KEEP_MEMBLOCK=y\n# CONFIG_ARCH_MDM9615 is not set\nCONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y\n# CONFIG_ARCH_MSM8960 is not set\n# CONFIG_ARCH_MSM8974 is not set\n# CONFIG_ARCH_MSM8X60 is not set\nCONFIG_ARCH_MULTIPLATFORM=y\nCONFIG_ARCH_MULTI_V6_V7=y\nCONFIG_ARCH_MULTI_V7=y\nCONFIG_ARCH_NR_GPIO=0\nCONFIG_ARCH_OPTIONAL_KERNEL_RWX=y\nCONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y\nCONFIG_ARCH_QCOM=y\nCONFIG_ARCH_SELECT_MEMORY_MODEL=y\nCONFIG_ARCH_SPARSEMEM_ENABLE=y\nCONFIG_ARCH_SUSPEND_POSSIBLE=y\nCONFIG_ARM=y\nCONFIG_ARM_AMBA=y\nCONFIG_ARM_APPENDED_DTB=y\nCONFIG_ARM_ARCH_TIMER=y\nCONFIG_ARM_ARCH_TIMER_EVTSTREAM=y\n# CONFIG_ARM_ATAG_DTB_COMPAT is not set\nCONFIG_ARM_CPUIDLE=y\n# CONFIG_ARM_CPU_TOPOLOGY is not set\nCONFIG_ARM_CRYPTO=y\nCONFIG_ARM_GIC=y\nCONFIG_ARM_HAS_SG_CHAIN=y\nCONFIG_ARM_L1_CACHE_SHIFT=6\nCONFIG_ARM_L1_CACHE_SHIFT_6=y\nCONFIG_ARM_PATCH_IDIV=y\nCONFIG_ARM_PATCH_PHYS_VIRT=y\n# CONFIG_ARM_QCOM_CPUFREQ_HW is not set\n# CONFIG_ARM_QCOM_CPUFREQ_NVMEM is not set\n# CONFIG_ARM_QCOM_SPM_CPUIDLE is not set\n# CONFIG_ARM_SMMU is not set\nCONFIG_ARM_THUMB=y\nCONFIG_ARM_UNWIND=y\nCONFIG_ARM_VIRT_EXT=y\nCONFIG_AT803X_PHY=y\nCONFIG_AUTO_ZRELADDR=y\nCONFIG_BCH=y\nCONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y\nCONFIG_BLK_DEV_LOOP=y\nCONFIG_BLK_MQ_PCI=y\nCONFIG_BOUNCE=y\n# CONFIG_CACHE_L2X0 is not set\nCONFIG_CLKSRC_QCOM=y\nCONFIG_CLONE_BACKWARDS=y\nCONFIG_CMDLINE_PARTITION=y\nCONFIG_COMMON_CLK=y\nCONFIG_COMMON_CLK_QCOM=y\nCONFIG_COMPAT_32BIT_TIME=y\nCONFIG_CPUFREQ_DT=y\nCONFIG_CPUFREQ_DT_PLATDEV=y\nCONFIG_CPU_32v6K=y\nCONFIG_CPU_32v7=y\nCONFIG_CPU_ABRT_EV7=y\nCONFIG_CPU_CACHE_V7=y\nCONFIG_CPU_CACHE_VIPT=y\nCONFIG_CPU_COPY_V6=y\nCONFIG_CPU_CP15=y\nCONFIG_CPU_CP15_MMU=y\nCONFIG_CPU_FREQ=y\nCONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y\n# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set\nCONFIG_CPU_FREQ_GOV_ATTR_SET=y\nCONFIG_CPU_FREQ_GOV_COMMON=y\n# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set\nCONFIG_CPU_FREQ_GOV_ONDEMAND=y\nCONFIG_CPU_FREQ_GOV_PERFORMANCE=y\n# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set\n# CONFIG_CPU_FREQ_GOV_USERSPACE is not set\nCONFIG_CPU_FREQ_STAT=y\nCONFIG_CPU_HAS_ASID=y\nCONFIG_CPU_IDLE=y\nCONFIG_CPU_IDLE_GOV_LADDER=y\nCONFIG_CPU_IDLE_GOV_MENU=y\nCONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y\nCONFIG_CPU_PABRT_V7=y\nCONFIG_CPU_PM=y\nCONFIG_CPU_RMAP=y\nCONFIG_CPU_SPECTRE=y\nCONFIG_CPU_THERMAL=y\nCONFIG_CPU_THUMB_CAPABLE=y\nCONFIG_CPU_TLB_V7=y\nCONFIG_CPU_V7=y\nCONFIG_CRC16=y\n# CONFIG_CRC32_SARWATE is not set\nCONFIG_CRC32_SLICEBY8=y\nCONFIG_CRC8=y\nCONFIG_CRYPTO_AES_ARM=y\nCONFIG_CRYPTO_AES_ARM_BS=y\nCONFIG_CRYPTO_CBC=y\nCONFIG_CRYPTO_CRYPTD=y\nCONFIG_CRYPTO_DEFLATE=y\nCONFIG_CRYPTO_DES=y\nCONFIG_CRYPTO_DEV_QCE=y\n# CONFIG_CRYPTO_DEV_QCE_ENABLE_AEAD is not set\n# CONFIG_CRYPTO_DEV_QCE_ENABLE_ALL is not set\n# CONFIG_CRYPTO_DEV_QCE_ENABLE_SHA is not set\nCONFIG_CRYPTO_DEV_QCE_ENABLE_SKCIPHER=y\nCONFIG_CRYPTO_DEV_QCE_SKCIPHER=y\nCONFIG_CRYPTO_DEV_QCE_SW_MAX_LEN=512\nCONFIG_CRYPTO_DEV_QCOM_RNG=y\nCONFIG_CRYPTO_DRBG=y\nCONFIG_CRYPTO_DRBG_HMAC=y\nCONFIG_CRYPTO_DRBG_MENU=y\nCONFIG_CRYPTO_ECB=y\nCONFIG_CRYPTO_HASH_INFO=y\nCONFIG_CRYPTO_HMAC=y\nCONFIG_CRYPTO_HW=y\nCONFIG_CRYPTO_JITTERENTROPY=y\nCONFIG_CRYPTO_LIB_DES=y\nCONFIG_CRYPTO_LIB_SHA256=y\nCONFIG_CRYPTO_LZO=y\nCONFIG_CRYPTO_RNG=y\nCONFIG_CRYPTO_RNG2=y\nCONFIG_CRYPTO_RNG_DEFAULT=y\nCONFIG_CRYPTO_SEQIV=y\nCONFIG_CRYPTO_SHA1=y\nCONFIG_CRYPTO_SHA256=y\nCONFIG_CRYPTO_SHA256_ARM=y\nCONFIG_CRYPTO_SHA512=y\nCONFIG_CRYPTO_SIMD=y\nCONFIG_CRYPTO_XTS=y\nCONFIG_CRYPTO_ZSTD=y\nCONFIG_DCACHE_WORD_ACCESS=y\nCONFIG_DEBUG_LL_INCLUDE=\"mach/debug-macro.S\"\nCONFIG_DEBUG_MISC=y\nCONFIG_DMADEVICES=y\nCONFIG_DMA_ENGINE=y\nCONFIG_DMA_OF=y\nCONFIG_DMA_OPS=y\nCONFIG_DMA_REMAP=y\nCONFIG_DMA_SHARED_BUFFER=y\nCONFIG_DMA_VIRTUAL_CHANNELS=y\nCONFIG_DTC=y\nCONFIG_DT_IDLE_STATES=y\nCONFIG_DYNAMIC_DEBUG=y\nCONFIG_EDAC_ATOMIC_SCRUB=y\nCONFIG_EDAC_SUPPORT=y\nCONFIG_EEPROM_AT24=y\nCONFIG_ESSEDMA=y\nCONFIG_EXTCON=y\nCONFIG_FIXED_PHY=y\nCONFIG_FIX_EARLYCON_MEM=y\nCONFIG_FWNODE_MDIO=y\nCONFIG_FW_LOADER_PAGED_BUF=y\nCONFIG_GENERIC_ALLOCATOR=y\nCONFIG_GENERIC_BUG=y\nCONFIG_GENERIC_CLOCKEVENTS=y\nCONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y\nCONFIG_GENERIC_CPU_AUTOPROBE=y\nCONFIG_GENERIC_CPU_VULNERABILITIES=y\nCONFIG_GENERIC_EARLY_IOREMAP=y\nCONFIG_GENERIC_GETTIMEOFDAY=y\nCONFIG_GENERIC_IDLE_POLL_SETUP=y\nCONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y\nCONFIG_GENERIC_IRQ_MULTI_HANDLER=y\nCONFIG_GENERIC_IRQ_SHOW=y\nCONFIG_GENERIC_IRQ_SHOW_LEVEL=y\nCONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y\nCONFIG_GENERIC_MSI_IRQ=y\nCONFIG_GENERIC_MSI_IRQ_DOMAIN=y\nCONFIG_GENERIC_PCI_IOMAP=y\nCONFIG_GENERIC_PHY=y\nCONFIG_GENERIC_PINCONF=y\nCONFIG_GENERIC_PINCTRL_GROUPS=y\nCONFIG_GENERIC_PINMUX_FUNCTIONS=y\nCONFIG_GENERIC_SCHED_CLOCK=y\nCONFIG_GENERIC_SMP_IDLE_THREAD=y\nCONFIG_GENERIC_STRNCPY_FROM_USER=y\nCONFIG_GENERIC_STRNLEN_USER=y\nCONFIG_GENERIC_TIME_VSYSCALL=y\nCONFIG_GENERIC_VDSO_32=y\nCONFIG_GPIOLIB=y\nCONFIG_GPIOLIB_IRQCHIP=y\nCONFIG_GPIO_74X164=y\nCONFIG_GPIO_CDEV=y\nCONFIG_GPIO_WATCHDOG=y\nCONFIG_GPIO_WATCHDOG_ARCH_INITCALL=y\nCONFIG_HANDLE_DOMAIN_IRQ=y\nCONFIG_HARDEN_BRANCH_PREDICTOR=y\nCONFIG_HARDIRQS_SW_RESEND=y\nCONFIG_HAS_DMA=y\nCONFIG_HAS_IOMEM=y\nCONFIG_HAS_IOPORT_MAP=y\nCONFIG_HAVE_SMP=y\nCONFIG_HIGHMEM=y\n# CONFIG_HIGHPTE is not set\nCONFIG_HWSPINLOCK=y\nCONFIG_HWSPINLOCK_QCOM=y\nCONFIG_HW_RANDOM=y\nCONFIG_HW_RANDOM_OPTEE=y\nCONFIG_HZ_FIXED=0\nCONFIG_I2C=y\nCONFIG_I2C_BOARDINFO=y\nCONFIG_I2C_CHARDEV=y\nCONFIG_I2C_HELPER_AUTO=y\n# CONFIG_I2C_QCOM_CCI is not set\nCONFIG_I2C_QUP=y\nCONFIG_INITRAMFS_SOURCE=\"\"\n# CONFIG_IOMMU_DEBUGFS is not set\n# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set\n# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set\nCONFIG_IOMMU_SUPPORT=y\nCONFIG_IO_URING=y\n# CONFIG_IPQ_APSS_PLL is not set\nCONFIG_IPQ_GCC_4019=y\n# CONFIG_IPQ_GCC_6018 is not set\n# CONFIG_IPQ_GCC_806X is not set\n# CONFIG_IPQ_GCC_8074 is not set\n# CONFIG_IPQ_LCC_806X is not set\nCONFIG_IRQCHIP=y\nCONFIG_IRQ_DOMAIN=y\nCONFIG_IRQ_DOMAIN_HIERARCHY=y\nCONFIG_IRQ_FASTEOI_HIERARCHY_HANDLERS=y\nCONFIG_IRQ_FORCED_THREADING=y\nCONFIG_IRQ_WORK=y\nCONFIG_KMAP_LOCAL=y\nCONFIG_KMAP_LOCAL_NON_LINEAR_PTE_ARRAY=y\n# CONFIG_KPSS_XCC is not set\n# CONFIG_KRAITCC is not set\nCONFIG_LEDS_LP5523=y\nCONFIG_LEDS_LP5562=y\nCONFIG_LEDS_LP55XX_COMMON=y\nCONFIG_LEDS_TLC591XX=y\nCONFIG_LIBFDT=y\nCONFIG_LOCK_DEBUGGING_SUPPORT=y\nCONFIG_LOCK_SPIN_ON_OWNER=y\nCONFIG_LZO_COMPRESS=y\nCONFIG_LZO_DECOMPRESS=y\nCONFIG_MDIO_BITBANG=y\nCONFIG_MDIO_BUS=y\nCONFIG_MDIO_DEVICE=y\nCONFIG_MDIO_DEVRES=y\nCONFIG_MDIO_GPIO=y\nCONFIG_MDIO_IPQ4019=y\n# CONFIG_MDM_GCC_9615 is not set\n# CONFIG_MDM_LCC_9615 is not set\nCONFIG_MEMFD_CREATE=y\n# CONFIG_MFD_HI6421_SPMI is not set\n# CONFIG_MFD_QCOM_RPM is not set\n# CONFIG_MFD_SPMI_PMIC is not set\nCONFIG_MFD_SYSCON=y\nCONFIG_MIGHT_HAVE_CACHE_L2X0=y\nCONFIG_MIGRATION=y\nCONFIG_MMC=y\nCONFIG_MMC_BLOCK=y\nCONFIG_MMC_CQHCI=y\nCONFIG_MMC_SDHCI=y\nCONFIG_MMC_SDHCI_IO_ACCESSORS=y\nCONFIG_MMC_SDHCI_MSM=y\n# CONFIG_MMC_SDHCI_PCI is not set\nCONFIG_MMC_SDHCI_PLTFM=y\nCONFIG_MODULES_USE_ELF_REL=y\n# CONFIG_MSM_GCC_8660 is not set\n# CONFIG_MSM_GCC_8916 is not set\n# CONFIG_MSM_GCC_8939 is not set\n# CONFIG_MSM_GCC_8960 is not set\n# CONFIG_MSM_GCC_8974 is not set\n# CONFIG_MSM_GCC_8994 is not set\n# CONFIG_MSM_GCC_8996 is not set\n# CONFIG_MSM_GCC_8998 is not set\n# CONFIG_MSM_GPUCC_8998 is not set\n# CONFIG_MSM_LCC_8960 is not set\n# CONFIG_MSM_MMCC_8960 is not set\n# CONFIG_MSM_MMCC_8974 is not set\n# CONFIG_MSM_MMCC_8996 is not set\n# CONFIG_MSM_MMCC_8998 is not set\nCONFIG_MTD_CMDLINE_PARTS=y\nCONFIG_MTD_NAND_CORE=y\nCONFIG_MTD_NAND_ECC=y\nCONFIG_MTD_NAND_ECC_SW_BCH=y\nCONFIG_MTD_NAND_ECC_SW_HAMMING=y\nCONFIG_MTD_NAND_QCOM=y\n# CONFIG_MTD_QCOMSMEM_PARTS is not set\nCONFIG_MTD_RAW_NAND=y\nCONFIG_MTD_SPI_NAND=y\nCONFIG_MTD_SPI_NOR=y\nCONFIG_MTD_SPLIT_FIRMWARE=y\nCONFIG_MTD_SPLIT_FIT_FW=y\nCONFIG_MTD_SPLIT_WRGG_FW=y\nCONFIG_MTD_UBI=y\nCONFIG_MTD_UBI_BEB_LIMIT=20\nCONFIG_MTD_UBI_BLOCK=y\nCONFIG_MTD_UBI_WL_THRESHOLD=4096\nCONFIG_MUTEX_SPIN_ON_OWNER=y\nCONFIG_NEED_DMA_MAP_STATE=y\nCONFIG_NEON=y\nCONFIG_NET_FLOW_LIMIT=y\nCONFIG_NET_PTP_CLASSIFY=y\nCONFIG_NET_SELFTESTS=y\nCONFIG_NLS=y\nCONFIG_NO_HZ=y\nCONFIG_NO_HZ_COMMON=y\nCONFIG_NO_HZ_IDLE=y\nCONFIG_NR_CPUS=4\nCONFIG_NVMEM=y\n# CONFIG_NVMEM_SPMI_SDAM is not set\nCONFIG_NVMEM_SYSFS=y\nCONFIG_OF=y\nCONFIG_OF_ADDRESS=y\nCONFIG_OF_EARLY_FLATTREE=y\nCONFIG_OF_FLATTREE=y\nCONFIG_OF_GPIO=y\nCONFIG_OF_IRQ=y\nCONFIG_OF_KOBJ=y\nCONFIG_OF_MDIO=y\nCONFIG_OLD_SIGACTION=y\nCONFIG_OLD_SIGSUSPEND3=y\nCONFIG_OPTEE=y\nCONFIG_OPTEE_SHM_NUM_PRIV_PAGES=1\nCONFIG_PADATA=y\nCONFIG_PAGE_OFFSET=0xC0000000\nCONFIG_PCI=y\nCONFIG_PCIEAER=y\nCONFIG_PCIEPORTBUS=y\nCONFIG_PCIE_DW=y\nCONFIG_PCIE_DW_HOST=y\nCONFIG_PCIE_QCOM=y\nCONFIG_PCI_DISABLE_COMMON_QUIRKS=y\nCONFIG_PCI_DOMAINS=y\nCONFIG_PCI_DOMAINS_GENERIC=y\nCONFIG_PCI_MSI=y\nCONFIG_PCI_MSI_IRQ_DOMAIN=y\nCONFIG_PERF_USE_VMALLOC=y\nCONFIG_PGTABLE_LEVELS=2\nCONFIG_PHYLIB=y\n# CONFIG_PHY_QCOM_APQ8064_SATA is not set\nCONFIG_PHY_QCOM_IPQ4019_USB=y\n# CONFIG_PHY_QCOM_IPQ806X_SATA is not set\n# CONFIG_PHY_QCOM_IPQ806X_USB is not set\n# CONFIG_PHY_QCOM_PCIE2 is not set\n# CONFIG_PHY_QCOM_QMP is not set\n# CONFIG_PHY_QCOM_QUSB2 is not set\n# CONFIG_PHY_QCOM_USB_HS_28NM is not set\n# CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2 is not set\n# CONFIG_PHY_QCOM_USB_SS is not set\nCONFIG_PINCTRL=y\n# CONFIG_PINCTRL_APQ8064 is not set\n# CONFIG_PINCTRL_APQ8084 is not set\nCONFIG_PINCTRL_IPQ4019=y\n# CONFIG_PINCTRL_IPQ6018 is not set\n# CONFIG_PINCTRL_IPQ8064 is not set\n# CONFIG_PINCTRL_IPQ8074 is not set\n# CONFIG_PINCTRL_MDM9615 is not set\nCONFIG_PINCTRL_MSM=y\n# CONFIG_PINCTRL_MSM8226 is not set\n# CONFIG_PINCTRL_MSM8660 is not set\n# CONFIG_PINCTRL_MSM8916 is not set\n# CONFIG_PINCTRL_MSM8960 is not set\n# CONFIG_PINCTRL_MSM8976 is not set\n# CONFIG_PINCTRL_MSM8994 is not set\n# CONFIG_PINCTRL_MSM8996 is not set\n# CONFIG_PINCTRL_MSM8998 is not set\n# CONFIG_PINCTRL_QCOM_SPMI_PMIC is not set\n# CONFIG_PINCTRL_QCOM_SSBI_PMIC is not set\n# CONFIG_PINCTRL_QCS404 is not set\n# CONFIG_PINCTRL_SC7180 is not set\n# CONFIG_PINCTRL_SDM660 is not set\n# CONFIG_PINCTRL_SDM845 is not set\n# CONFIG_PINCTRL_SM8150 is not set\n# CONFIG_PINCTRL_SM8250 is not set\nCONFIG_PM_OPP=y\nCONFIG_POWER_RESET=y\nCONFIG_POWER_RESET_MSM=y\nCONFIG_POWER_SUPPLY=y\nCONFIG_PPS=y\nCONFIG_PRINTK_TIME=y\nCONFIG_PTP_1588_CLOCK=y\nCONFIG_PTP_1588_CLOCK_OPTIONAL=y\nCONFIG_QCA807X_PHY=y\nCONFIG_QCOM_A53PLL=y\n# CONFIG_QCOM_ADM is not set\nCONFIG_QCOM_BAM_DMA=y\n# CONFIG_QCOM_COMMAND_DB is not set\n# CONFIG_QCOM_CPR is not set\n# CONFIG_QCOM_EBI2 is not set\n# CONFIG_QCOM_GENI_SE is not set\n# CONFIG_QCOM_GSBI is not set\n# CONFIG_QCOM_HFPLL is not set\n# CONFIG_QCOM_IOMMU is not set\n# CONFIG_QCOM_LLCC is not set\n# CONFIG_QCOM_OCMEM is not set\n# CONFIG_QCOM_PDC is not set\nCONFIG_QCOM_QFPROM=y\n# CONFIG_QCOM_RMTFS_MEM is not set\n# CONFIG_QCOM_RPMH is not set\nCONFIG_QCOM_SCM=y\n# CONFIG_QCOM_SCM_DOWNLOAD_MODE_DEFAULT is not set\nCONFIG_QCOM_SMEM=y\n# CONFIG_QCOM_SMSM is not set\n# CONFIG_QCOM_SOCINFO is not set\nCONFIG_QCOM_TCSR=y\n# CONFIG_QCOM_TSENS is not set\nCONFIG_QCOM_WDT=y\n# CONFIG_QCS_GCC_404 is not set\n# CONFIG_QCS_Q6SSTOP_404 is not set\n# CONFIG_QCS_TURING_404 is not set\nCONFIG_RAS=y\nCONFIG_RATIONAL=y\nCONFIG_REGMAP=y\nCONFIG_REGMAP_I2C=y\nCONFIG_REGMAP_MMIO=y\nCONFIG_REGULATOR=y\nCONFIG_REGULATOR_FIXED_VOLTAGE=y\n# CONFIG_REGULATOR_QCOM_LABIBB is not set\n# CONFIG_REGULATOR_QCOM_SPMI is not set\n# CONFIG_REGULATOR_QCOM_USB_VBUS is not set\nCONFIG_REGULATOR_VCTRL=y\nCONFIG_REGULATOR_VQMMC_IPQ4019=y\nCONFIG_RESET_CONTROLLER=y\n# CONFIG_RESET_QCOM_AOSS is not set\n# CONFIG_RESET_QCOM_PDC is not set\nCONFIG_RFS_ACCEL=y\nCONFIG_RPS=y\nCONFIG_RTC_CLASS=y\nCONFIG_RTC_I2C_AND_SPI=y\nCONFIG_RTC_MC146818_LIB=y\nCONFIG_RWSEM_SPIN_ON_OWNER=y\n# CONFIG_SC_DISPCC_7180 is not set\n# CONFIG_SC_GCC_7180 is not set\n# CONFIG_SC_GPUCC_7180 is not set\n# CONFIG_SC_LPASS_CORECC_7180 is not set\n# CONFIG_SC_MSS_7180 is not set\n# CONFIG_SC_VIDEOCC_7180 is not set\n# CONFIG_SDM_CAMCC_845 is not set\n# CONFIG_SDM_DISPCC_845 is not set\n# CONFIG_SDM_GCC_660 is not set\n# CONFIG_SDM_GCC_845 is not set\n# CONFIG_SDM_GPUCC_845 is not set\n# CONFIG_SDM_LPASSCC_845 is not set\n# CONFIG_SDM_VIDEOCC_845 is not set\nCONFIG_SERIAL_8250_FSL=y\nCONFIG_SERIAL_MCTRL_GPIO=y\nCONFIG_SERIAL_MSM=y\nCONFIG_SERIAL_MSM_CONSOLE=y\nCONFIG_SGL_ALLOC=y\nCONFIG_SMP=y\nCONFIG_SMP_ON_UP=y\n# CONFIG_SM_GCC_8150 is not set\n# CONFIG_SM_GCC_8250 is not set\n# CONFIG_SM_GPUCC_8150 is not set\n# CONFIG_SM_GPUCC_8250 is not set\n# CONFIG_SM_VIDEOCC_8150 is not set\n# CONFIG_SM_VIDEOCC_8250 is not set\nCONFIG_SOCK_RX_QUEUE_MAPPING=y\nCONFIG_SPARSE_IRQ=y\nCONFIG_SPI=y\nCONFIG_SPI_BITBANG=y\nCONFIG_SPI_GPIO=y\nCONFIG_SPI_MASTER=y\nCONFIG_SPI_MEM=y\nCONFIG_SPI_QUP=y\nCONFIG_SPMI=y\n# CONFIG_SPMI_HISI3670 is not set\nCONFIG_SPMI_MSM_PMIC_ARB=y\n# CONFIG_SPMI_PMIC_CLKDIV is not set\nCONFIG_SRCU=y\nCONFIG_SWCONFIG=y\nCONFIG_SWCONFIG_LEDS=y\nCONFIG_SWPHY=y\nCONFIG_SWP_EMULATE=y\nCONFIG_SYS_SUPPORTS_APM_EMULATION=y\nCONFIG_TEE=y\nCONFIG_THERMAL=y\nCONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y\nCONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0\nCONFIG_THERMAL_GOV_STEP_WISE=y\nCONFIG_THERMAL_OF=y\nCONFIG_TICK_CPU_ACCOUNTING=y\nCONFIG_TIMER_OF=y\nCONFIG_TIMER_PROBE=y\nCONFIG_TREE_RCU=y\nCONFIG_TREE_SRCU=y\nCONFIG_UBIFS_FS=y\nCONFIG_UEVENT_HELPER_PATH=\"\"\nCONFIG_UNCOMPRESS_INCLUDE=\"debug/uncompress.h\"\nCONFIG_UNWINDER_ARM=y\nCONFIG_USB=y\nCONFIG_USB_COMMON=y\nCONFIG_USB_SUPPORT=y\nCONFIG_USE_OF=y\nCONFIG_VFP=y\nCONFIG_VFPv3=y\nCONFIG_WATCHDOG_CORE=y\nCONFIG_XPS=y\nCONFIG_XXHASH=y\nCONFIG_XZ_DEC_ARM=y\nCONFIG_XZ_DEC_BCJ=y\nCONFIG_ZBOOT_ROM_BSS=0\nCONFIG_ZBOOT_ROM_TEXT=0\nCONFIG_ZLIB_DEFLATE=y\nCONFIG_ZLIB_INFLATE=y\nCONFIG_ZSTD_COMPRESS=y\nCONFIG_ZSTD_DECOMPRESS=y\n"
  },
  {
    "path": "target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-a42.dts",
    "content": "// SPDX-License-Identifier: ISC\n/* Copyright (c) 2015, The Linux Foundation. All rights reserved.\n * Copyright (c) 2017, Sven Eckelmann <sven.eckelmann@openmesh.com>\n */\n\n#include \"qcom-ipq4019.dtsi\"\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/soc/qcom,tcsr.h>\n\n/ {\n\tmodel = \"OpenMesh A42\";\n\tcompatible = \"openmesh,a42\";\n\n\tsoc {\n\t\trng@22000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tmdio@90000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tess-psgmii@98000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\ttcsr@194b000 {\n\t\t\t/* select hostmode */\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x194b000 0x100>;\n\t\t\tqcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\ttcsr@1949000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1949000 0x100>;\n\t\t\tqcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;\n\t\t};\n\n\t\tess_tcsr@1953000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1953000 0x1000>;\n\t\t\tqcom,ess-interface-select = <TCSR_ESS_PSGMII>;\n\t\t};\n\n\t\ttcsr@1957000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1957000 0x100>;\n\t\t\tqcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;\n\t\t};\n\n\t\tusb2: usb2@60f8800 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tcrypto@8e3a000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\twatchdog@b017000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tess-switch@c000000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tedma@c080000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&tlmm 59 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\taliases {\n\t\tled-boot = &led_status_green;\n\t\tled-failsafe = &led_status_green;\n\t\tled-running = &led_status_green;\n\t\tled-upgrade = &led_status_green;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tstatus_red {\n\t\t\tlabel = \"red:status\";\n\t\t\tgpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tled_status_green: status_green {\n\t\t\tlabel = \"green:status\";\n\t\t\tgpios = <&tlmm 1 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tstatus_blue {\n\t\t\tlabel = \"blue:status\";\n\t\t\tgpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n\n\twatchdog {\n\t\tcompatible = \"linux,wdt-gpio\";\n\t\tgpios = <&tlmm 5 GPIO_ACTIVE_LOW>;\n\t\thw_algo = \"toggle\";\n\t\t/* hw_margin_ms is actually 300s but driver limits it to 60s */\n\t\thw_margin_ms = <60000>;\n\t\talways-running;\n\t};\n};\n\n&tlmm {\n\tserial_pins: serial_pinmux {\n\t\tmux {\n\t\t\tpins = \"gpio60\", \"gpio61\";\n\t\t\tfunction = \"blsp_uart0\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tspi_0_pins: spi_0_pinmux {\n\t\tpin {\n\t\t\tfunction = \"blsp_spi0\";\n\t\t\tpins = \"gpio55\", \"gpio56\", \"gpio57\";\n\t\t\tdrive-strength = <12>;\n\t\t\tbias-disable;\n\t\t};\n\t\tpin_cs {\n\t\t\tfunction = \"gpio\";\n\t\t\tpins = \"gpio54\";\n\t\t\tdrive-strength = <2>;\n\t\t\tbias-disable;\n\t\t\toutput-high;\n\t\t};\n\t};\n};\n\n&blsp_dma {\n\tstatus = \"okay\";\n};\n\n&blsp1_spi1 {\n\tpinctrl-0 = <&spi_0_pins>;\n\tpinctrl-names = \"default\";\n\tstatus = \"okay\";\n\tcs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;\n\n\tflash@0 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <24000000>;\n\t\t/* partitions are passed via bootloader */\n\t};\n};\n\n&blsp1_uart1 {\n\tpinctrl-0 = <&serial_pins>;\n\tpinctrl-names = \"default\";\n\tstatus = \"okay\";\n};\n\n&cryptobam {\n\tstatus = \"okay\";\n};\n\n&gmac0 {\n\tqcom,phy_mdio_addr = <4>;\n\tqcom,poll_required = <1>;\n\tqcom,forced_speed = <1000>;\n\tqcom,forced_duplex = <1>;\n\tvlan_tag = <2 0x20>;\n};\n\n&gmac1 {\n\tqcom,phy_mdio_addr = <3>;\n\tqcom,poll_required = <1>;\n\tqcom,forced_speed = <1000>;\n\tqcom,forced_duplex = <1>;\n\tvlan_tag = <1 0x10>;\n};\n\n&usb2_hs_phy {\n\tstatus = \"okay\";\n};\n\n&wifi0 {\n\tstatus = \"okay\";\n\tqcom,ath10k-calibration-variant = \"OM-A42\";\n};\n\n&wifi1 {\n\tstatus = \"okay\";\n\tqcom,ath10k-calibration-variant = \"OM-A42\";\n};\n"
  },
  {
    "path": "target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qcom-ipq4019.dtsi\"\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/soc/qcom,tcsr.h>\n\n/ {\n\tmodel = \"ALFA Network AP120C-AC\";\n\tcompatible = \"alfa-network,ap120c-ac\";\n\n\taliases {\n\t\tled-boot = &status;\n\t\tled-failsafe = &status;\n\t\tled-running = &status;\n\t\tled-upgrade = &status;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&tlmm 63 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tstatus: status {\n\t\t\tlabel = \"blue:status\";\n\t\t\tgpios = <&tlmm 5 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"keep\";\n\t\t};\n\n\t\twan {\n\t\t\tlabel = \"amber:wan\";\n\t\t\tgpios = <&ethphy4 1 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\twlan2g {\n\t\t\tlabel = \"green:wlan2g\";\n\t\t\tgpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\twlan5g {\n\t\t\tlabel = \"red:wlan5g\";\n\t\t\tgpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\t};\n\n\tsoc {\n\t\trng@22000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tmdio@90000 {\n\t\t\tstatus = \"okay\";\n\n\t\t\tpinctrl-0 = <&mdio_pins>;\n\t\t\tpinctrl-names = \"default\";\n\t\t};\n\n\t\tess-psgmii@98000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tcounter@4a1000 {\n\t\t\tcompatible = \"qcom,qca-gcnt\";\n\t\t\treg = <0x4a1000 0x4>;\n\t\t};\n\n\t\ttcsr@1949000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1949000 0x100>;\n\t\t\tqcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;\n\t\t};\n\n\t\ttcsr@194b000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x194b000 0x100>;\n\t\t\tqcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;\n\t\t};\n\n\t\tess_tcsr@1953000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1953000 0x1000>;\n\t\t\tqcom,ess-interface-select = <TCSR_ESS_PSGMII>;\n\t\t};\n\n\t\ttcsr@1957000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1957000 0x100>;\n\t\t\tqcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;\n\t\t};\n\n\t\tusb2@60f8800 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tusb3@8af8800 {\n\t\t\tstatus = \"okay\";\n\n\t\t\tdwc3@8a00000 {\n\t\t\t\tphys = <&usb3_hs_phy>;\n\t\t\t\tphy-names = \"usb2-phy\";\n\t\t\t};\n\t\t};\n\n\t\tcrypto@8e3a000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\twatchdog@b017000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tess-switch@c000000 {\n\t\t\tstatus = \"okay\";\n\n\t\t\tswitch_lan_bmp = <0x10>;\n\t\t\tswitch_wan_bmp = <0x20>;\n\t\t};\n\n\t\tedma@c080000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\t};\n};\n\n&blsp_dma {\n\tstatus = \"okay\";\n};\n\n&blsp1_i2c3 {\n\tstatus = \"okay\";\n\n\tpinctrl-0 = <&i2c0_pins>;\n\tpinctrl-names = \"default\";\n\n\ttpm@29 {\n\t\tcompatible = \"atmel,at97sc3204t\";\n\t\treg = <0x29>;\n\t};\n};\n\n&blsp1_spi1 {\n\tstatus = \"okay\";\n\n\tpinctrl-0 = <&spi0_pins>;\n\tpinctrl-names = \"default\";\n\tcs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>,\n\t\t   <&tlmm  4 GPIO_ACTIVE_HIGH>;\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <24000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"SBL1\";\n\t\t\t\treg = <0x00000000 0x00040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"MIBIB\";\n\t\t\t\treg = <0x00040000 0x00020000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@60000 {\n\t\t\t\tlabel = \"QSEE\";\n\t\t\t\treg = <0x00060000 0x00060000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@c0000 {\n\t\t\t\tlabel = \"CDT\";\n\t\t\t\treg = <0x000c0000 0x00010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@d0000 {\n\t\t\t\tlabel = \"DDRPARAMS\";\n\t\t\t\treg = <0x000d0000 0x00010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@e0000 {\n\t\t\t\tlabel = \"APPSBLENV\";\n\t\t\t\treg = <0x000e0000 0x00010000>;\n\t\t\t};\n\n\t\t\tpartition@f0000 {\n\t\t\t\tlabel = \"APPSBL\";\n\t\t\t\treg = <0x000f0000 0x00080000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@170000 {\n\t\t\t\tlabel = \"ART\";\n\t\t\t\treg = <0x00170000 0x00010000>;\n\t\t\t\tread-only;\n\t\t\t\tcompatible = \"nvmem-cells\";\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\n\t\t\t\tprecal_art_1000: precal@1000 {\n\t\t\t\t\treg = <0x1000 0x2f20>;\n\t\t\t\t};\n\n\t\t\t\tprecal_art_5000: precal@5000 {\n\t\t\t\t\treg = <0x5000 0x2f20>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tpartition@180000 {\n\t\t\t\tlabel = \"priv_data1\";\n\t\t\t\treg = <0x00180000 0x00010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@190000 {\n\t\t\t\tlabel = \"priv_data2\";\n\t\t\t\treg = <0x00190000 0x00010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n\n\tnand@1 {\n\t\tcompatible = \"spi-nand\";\n\t\treg = <1>;\n\t\tspi-max-frequency = <24000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"rootfs1\";\n\t\t\t\treg = <0x00000000 0x04000000>;\n\t\t\t};\n\n\t\t\tpartition@4000000 {\n\t\t\t\tlabel = \"rootfs2\";\n\t\t\t\treg = <0x04000000 0x04000000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&blsp1_uart1 {\n\tstatus = \"okay\";\n\n\tpinctrl-0 = <&serial0_pins>;\n\tpinctrl-names = \"default\";\n};\n\n&cryptobam {\n\tstatus = \"okay\";\n};\n\n&ethphy4 {\n\tgpio-controller;\n\t#gpio-cells = <2>;\n};\n\n&gmac0 {\n\tqcom,forced_duplex = <1>;\n\tqcom,forced_speed = <1000>;\n\tqcom,phy_mdio_addr = <3>;\n\tqcom,poll_required = <1>;\n\tvlan_tag = <1 0x10>;\n};\n\n&gmac1 {\n\tqcom,forced_duplex = <1>;\n\tqcom,forced_speed = <1000>;\n\tqcom,phy_mdio_addr = <4>;\n\tqcom,poll_required = <1>;\n\tvlan_tag = <2 0x20>;\n};\n\n&tlmm {\n\ti2c0_pins: i2c0_pinmux {\n\t\tmux_i2c {\n\t\t\tfunction = \"blsp_i2c0\";\n\t\t\tpins = \"gpio58\", \"gpio59\";\n\t\t\tdrive-strength = <16>;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tmdio_pins: mdio_pinmux {\n\t\tmux_mdio {\n\t\t\tpins = \"gpio53\";\n\t\t\tfunction = \"mdio\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tmux_mdc {\n\t\t\tpins = \"gpio52\";\n\t\t\tfunction = \"mdc\";\n\t\t\tbias-pull-up;\n\t\t};\n\t};\n\n\tserial0_pins: serial0_pinmux {\n\t\tmux_uart {\n\t\t\tpins = \"gpio60\", \"gpio61\";\n\t\t\tfunction = \"blsp_uart0\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tspi0_pins: spi0_pinmux {\n\t\tmux_spi {\n\t\t\tfunction = \"blsp_spi0\";\n\t\t\tpins = \"gpio55\", \"gpio56\", \"gpio57\";\n\t\t\tdrive-strength = <12>;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux_cs {\n\t\t\tfunction = \"gpio\";\n\t\t\tpins = \"gpio54\", \"gpio4\";\n\t\t\tdrive-strength = <2>;\n\t\t\tbias-disable;\n\t\t\toutput-high;\n\t\t};\n\t};\n};\n\n&usb2_hs_phy {\n\tstatus = \"okay\";\n};\n\n&usb3_hs_phy {\n\tstatus = \"okay\";\n};\n\n&wifi0 {\n\tstatus = \"okay\";\n\tnvmem-cell-names = \"pre-calibration\";\n\tnvmem-cells = <&precal_art_1000>;\n};\n\n&wifi1 {\n\tstatus = \"okay\";\n\tqcom,ath10k-calibration-variant = \"ALFA-Network-AP120C-AC\";\n\tnvmem-cell-names = \"pre-calibration\";\n\tnvmem-cells = <&precal_art_5000>;\n};\n"
  },
  {
    "path": "target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-cap-ac.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n/* Copyright (c) 2020, Robert Marko <robimarko@gmail.com> */\n\n#include \"qcom-ipq4019.dtsi\"\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/soc/qcom,tcsr.h>\n\n/ {\n\tmodel = \"MikroTik cAP ac\";\n\tcompatible = \"mikrotik,cap-ac\";\n\n\tmemory {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x80000000 0x08000000>;\n\t};\n\n\tchosen {\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\taliases {\n\t\tled-boot = &led_user;\n\t\tled-failsafe = &led_user;\n\t\tled-running = &led_user;\n\t\tled-upgrade = &led_user;\n\t};\n\n\tsoc {\n\t\trng@22000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tcounter@4a1000 {\n\t\t\tcompatible = \"qcom,qca-gcnt\";\n\t\t\treg = <0x4a1000 0x4>;\n\t\t};\n\n\t\ttcsr@1949000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1949000 0x100>;\n\t\t\tqcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;\n\t\t};\n\n\t\tess_tcsr@1953000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1953000 0x1000>;\n\t\t\tqcom,ess-interface-select = <TCSR_ESS_PSGMII>;\n\t\t};\n\n\t\ttcsr@1957000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1957000 0x100>;\n\t\t\tqcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;\n\t\t};\n\n\t\tcrypto@8e3a000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\twatchdog@b017000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tess-switch@c000000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tedma@c080000 {\n\t\t\tstatus = \"okay\";\n\t\t\tqcom,poll_required = <0>;\n\t\t\tqcom,num_gmac = <1>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&tlmm 63 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\tmode {\n\t\t\tlabel = \"mode\";\n\t\t\tgpios = <&tlmm 5 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_LIGHTS_TOGGLE>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tpower {\n\t\t\tlabel = \"blue:power\";\n\t\t\tgpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"keep\";\n\t\t};\n\n\t\tled_user: user {\n\t\t\tlabel = \"green:user\";\n\t\t\tgpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;\n\t\t\tpanic-indicator;\n\t\t};\n\n\t\twlan2g {\n\t\t\tlabel = \"green:wlan2g\";\n\t\t\tgpios = <&tlmm 1 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\twlan5g {\n\t\t\tlabel = \"green:wlan5g\";\n\t\t\tgpios = <&tlmm 58 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\teth1 {\n\t\t\tlabel = \"green:eth1\";\n\t\t\tgpios = <&ethphy4 1 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\teth2 {\n\t\t\tlabel = \"green:eth2\";\n\t\t\tgpios = <&ethphy3 1 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&tlmm {\n\tserial_pins: serial_pinmux {\n\t\tmux {\n\t\t\tpins = \"gpio60\", \"gpio61\";\n\t\t\tfunction = \"blsp_uart0\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tspi_0_pins: spi_0_pinmux {\n\t\tpin {\n\t\t\tfunction = \"blsp_spi0\";\n\t\t\tpins = \"gpio55\", \"gpio56\", \"gpio57\";\n\t\t\tdrive-strength = <2>;\n\t\t\tbias-disable;\n\t\t};\n\t\tpin_cs {\n\t\t\tfunction = \"gpio\";\n\t\t\tpins = \"gpio54\";\n\t\t\tdrive-strength = <2>;\n\t\t\tbias-disable;\n\t\t\toutput-high;\n\t\t};\n\t};\n};\n\n&blsp_dma {\n\tstatus = \"okay\";\n};\n\n&blsp1_spi1 {\n\tstatus = \"okay\";\n\n\tpinctrl-0 = <&spi_0_pins>;\n\tpinctrl-names = \"default\";\n\tcs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;\n\n\tflash@0 {\n\t\treg = <0>;\n\t\tcompatible = \"jedec,spi-nor\";\n\t\tspi-max-frequency = <40000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"Qualcomm\";\n\t\t\t\treg = <0x0 0x80000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@80000 {\n\t\t\t\tcompatible = \"mikrotik,routerboot-partitions\";\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\t\t\t\tlabel = \"RouterBoot\";\n\t\t\t\treg = <0x80000 0x80000>;\n\t\t\t\tread-only;\n\n\t\t\t\thard_config {\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\tdtb_config {\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\tsoft_config {\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tpartition@100000 {\n\t\t\t\tcompatible = \"mikrotik,minor\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x100000 0xf00000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&blsp1_uart1 {\n\tstatus = \"okay\";\n\n\tpinctrl-0 = <&serial_pins>;\n\tpinctrl-names = \"default\";\n};\n\n&cryptobam {\n\tstatus = \"okay\";\n};\n\n&mdio {\n\tstatus = \"okay\";\n};\n\n&gmac0 {\n\tvlan_tag = <0 0x3f>;\n};\n\n&ethphy3 {\n\tgpio-controller;\n\t#gpio-cells = <2>;\n};\n\n&ethphy4 {\n\tgpio-controller;\n\t#gpio-cells = <2>;\n};\n\n&wifi0 {\n\tstatus = \"okay\";\n\n\tqcom,ath10k-calibration-variant = \"MikroTik-cAP-ac\";\n};\n\n&wifi1 {\n\tstatus = \"okay\";\n\n\tqcom,ath10k-calibration-variant = \"MikroTik-cAP-ac\";\n};\n"
  },
  {
    "path": "target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-cs-w3-wd1200g-eup.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-only OR MIT\n\n#include \"qcom-ipq4019.dtsi\"\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/soc/qcom,tcsr.h>\n\n/ {\n\tmodel = \"EZVIZ CS-W3-WD1200G EUP\";\n\tcompatible = \"ezviz,cs-w3-wd1200g-eup\";\n\n\taliases {\n\t\tled-boot = &led_status_green;\n\t\tled-failsafe = &led_status_red;\n\t\tled-running = &led_status_blue;\n\t\tled-upgrade = &led_status_green;\n\t};\n\n\tsoc {\n\t\trng@22000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tmdio@90000 {\n\t\t\tstatus = \"okay\";\n\t\t\tpinctrl-0 = <&mdio_pins>;\n\t\t\tpinctrl-names = \"default\";\n\t\t\treset-gpios = <&tlmm 59 GPIO_ACTIVE_LOW>;\n\t\t\treset-delay-us = <5000>;\n\t\t};\n\n\t\tess-psgmii@98000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\ttcsr@1949000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1949000 0x100>;\n\t\t\tqcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;\n\t\t};\n\n\t\ttcsr@194b000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x194b000 0x100>;\n\t\t\tqcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;\n\t\t};\n\n\t\tess_tcsr@1953000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1953000 0x1000>;\n\t\t\tqcom,ess-interface-select = <TCSR_ESS_PSGMII>;\n\t\t};\n\n\t\ttcsr@1957000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1957000 0x100>;\n\t\t\tqcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;\n\t\t};\n\n\t\tcrypto@8e3a000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\twatchdog@b017000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tess-switch@c000000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tedma@c080000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_status_red: status_red {\n\t\t\tlabel = \"red:status\";\n\t\t\tgpios = <&tlmm 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_status_green: status_green {\n\t\t\tlabel = \"green:status\";\n\t\t\tgpios = <&tlmm 3 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_status_blue: status_blue {\n\t\t\tlabel = \"blue:status\";\n\t\t\tgpios = <&tlmm 58 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&tlmm 63 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n};\n\n&tlmm {\n\tserial_pins: serial_pinmux {\n\t\tmux {\n\t\t\tpins = \"gpio60\", \"gpio61\";\n\t\t\tfunction = \"blsp_uart0\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tmdio_pins: mdio_pinmux {\n\t\tmux_1 {\n\t\t\tpins = \"gpio53\";\n\t\t\tfunction = \"mdio\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tmux_2 {\n\t\t\tpins = \"gpio52\";\n\t\t\tfunction = \"mdc\";\n\t\t\tbias-pull-up;\n\t\t};\n\t};\n\n\tspi_0_pins: spi_0_pinmux {\n\t\tpin {\n\t\t\tfunction = \"blsp_spi0\";\n\t\t\tpins = \"gpio55\", \"gpio56\", \"gpio57\";\n\t\t\tdrive-strength = <12>;\n\t\t\tbias-disable;\n\t\t};\n\t\tpin_cs {\n\t\t\tfunction = \"gpio\";\n\t\t\tpins = \"gpio54\";\n\t\t\tdrive-strength = <2>;\n\t\t\tbias-disable;\n\t\t\toutput-high;\n\t\t};\n\t};\n};\n\n&blsp_dma {\n\tstatus = \"okay\";\n};\n\n&blsp1_spi1 {\n\tpinctrl-0 = <&spi_0_pins>;\n\tpinctrl-names = \"default\";\n\tstatus = \"okay\";\n\tcs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <24000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition0@0 {\n\t\t\t\tlabel = \"SBL1\";\n\t\t\t\treg = <0x00000000 0x00040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition1@40000 {\n\t\t\t\tlabel = \"MIBIB\";\n\t\t\t\treg = <0x00040000 0x00020000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition2@60000 {\n\t\t\t\tlabel = \"QSEE\";\n\t\t\t\treg = <0x00060000 0x00060000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition3@c0000 {\n\t\t\t\tlabel = \"CDT\";\n\t\t\t\treg = <0x000c0000 0x00010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition4@d0000 {\n\t\t\t\tlabel = \"DDRPARAMS\";\n\t\t\t\treg = <0x000d0000 0x00010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition5@E0000 {\n\t\t\t\tlabel = \"APPSBLENV\";\n\t\t\t\treg = <0x000e0000 0x00010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition6@F0000 {\n\t\t\t\tlabel = \"APPSBL\";\n\t\t\t\treg = <0x000f0000 0x00080000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition7@170000 {\n\t\t\t\tlabel = \"ART\";\n\t\t\t\treg = <0x00170000 0x00010000>;\n\t\t\t\tread-only;\n\n\t\t\t\tcompatible = \"nvmem-cells\";\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\n\t\t\t\tmacaddr_art_0: macaddr@0 {\n\t\t\t\t\treg = <0x0 0x6>;\n\t\t\t\t};\n\n\t\t\t\tmacaddr_art_6: macaddr@6 {\n\t\t\t\t\treg = <0x6 0x6>;\n\t\t\t\t};\n\n\t\t\t\tprecal_art_1000: precal@1000 {\n\t\t\t\t\treg = <0x1000 0x2f20>;\n\t\t\t\t};\n\n\t\t\t\tprecal_art_5000: precal@5000 {\n\t\t\t\t\treg = <0x5000 0x2f20>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tpartition9@580000 {\n\t\t\t\tcompatible = \"denx,fit\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x00180000 0x00e80000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&blsp1_uart1 {\n\tpinctrl-0 = <&serial_pins>;\n\tpinctrl-names = \"default\";\n\tstatus = \"okay\";\n};\n\n&cryptobam {\n\tstatus = \"okay\";\n};\n\n&wifi0 {\n\tstatus = \"okay\";\n\tqcom,ath10k-calibration-variant = \"ezviz-cs-w3-wd1200g-eup\";\n\tnvmem-cell-names = \"pre-calibration\";\n\tnvmem-cells = <&precal_art_1000>;\n};\n\n&wifi1 {\n\tstatus = \"okay\";\n\tqcom,ath10k-calibration-variant = \"ezviz-cs-w3-wd1200g-eup\";\n\tnvmem-cell-names = \"pre-calibration\";\n\tnvmem-cells = <&precal_art_5000>;\n};\n\n&gmac0 {\n\tnvmem-cell-names = \"mac-address\";\n\tnvmem-cells = <&macaddr_art_6>;\n};\n\n&gmac1 {\n\tnvmem-cell-names = \"mac-address\";\n\tnvmem-cells = <&macaddr_art_0>;\n};\n"
  },
  {
    "path": "target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-dap-2610.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qcom-ipq4019.dtsi\"\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/soc/qcom,tcsr.h>\n\n/ {\n\tmodel = \"D-Link DAP 2610\";\n\tcompatible = \"dlink,dap-2610\";\n\n\taliases {\n\t\tled-boot = &led_red;\n\t\tled-failsafe = &led_red;\n\t\tled-running = &led_green;\n\t\tled-upgrade = &led_red;\n\t};\n\n\tsoc {\n\t\tedma@c080000 {\n\t\t\tqcom,num_gmac = <1>;\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\ttcsr@1949000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1949000 0x100>;\n\t\t\tqcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;\n\t\t};\n\n\t\tess_tcsr@1953000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1953000 0x1000>;\n\t\t\tqcom,ess-interface-select = <TCSR_ESS_PSGMII>;\n\t\t};\n\n\t\ttcsr@1957000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1957000 0x100>;\n\t\t\tqcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;\n\t\t};\n\n\t\trng@22000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tcrypto@8e3a000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\twatchdog@b017000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tess-switch@c000000 {\n\t\t\tstatus = \"okay\";\n\t\t\tswitch_lan_bmp = <0x20>;\n\t\t\tswitch_wan_bmp = <0x00>;\n\t\t};\n\n\t\tess-psgmii@98000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_red: red {\n\t\t\tlabel = \"red:power\";\n\t\t\tgpios = <&tlmm 4 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_green: green {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&tlmm 5 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&tlmm 63 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n};\n\n&blsp1_spi1 {\n\tpinctrl-0 = <&spi_0_pins>;\n\tpinctrl-names = \"default\";\n\tstatus = \"okay\";\n\tcs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <24000000>;\n\n\t\tpartitions {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\t\t\tcompatible = \"fixed-partitions\";\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"SBL1\";\n\t\t\t\treg = <0x0 0x40000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"MIBIB\";\n\t\t\t\treg = <0x40000 0x20000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@60000 {\n\t\t\t\tlabel = \"QSEE\";\n\t\t\t\treg = <0x60000 0x60000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@c0000 {\n\t\t\t\tlabel = \"CDT\";\n\t\t\t\treg = <0xc0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@d0000 {\n\t\t\t\tlabel = \"DDRPARAMS\";\n\t\t\t\treg = <0xd0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@e0000 {\n\t\t\t\tlabel = \"APPSBLENV\";\n\t\t\t\treg = <0xe0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@f0000 {\n\t\t\t\tlabel = \"APPSBL\";\n\t\t\t\treg = <0xf0000 0x80000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@170000 {\n\t\t\t\tlabel = \"ART\";\n\t\t\t\treg = <0x170000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@180000 {\n\t\t\t\tcompatible = \"wrg\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x180000 0xdc0000>;\n\t\t\t};\n\t\t\tpartition@fb0000 {\n\t\t\t\tlabel = \"rgbd\";\n\t\t\t\treg = <0xfb0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@fc0000 {\n\t\t\t\tlabel = \"bdcfg\";\n\t\t\t\treg = <0xfc0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@fd0000 {\n\t\t\t\tlabel = \"langpack\";\n\t\t\t\treg = <0xfd0000 0x20000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@ff0000 {\n\t\t\t\tlabel = \"certificate\";\n\t\t\t\treg = <0xff0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@f40000 {\n\t\t\t\tlabel = \"captival\";\n\t\t\t\treg = <0xf40000 0x70000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&blsp_dma {\n\tstatus = \"okay\";\n};\n\n&blsp1_uart1 {\n\tpinctrl-0 = <&serial_pins>;\n\tpinctrl-names = \"default\";\n\tstatus = \"okay\";\n};\n\n&cryptobam {\n\tstatus = \"okay\";\n};\n\n&gmac0 {\n\tqcom,phy_mdio_addr = <4>;\n\tqcom,poll_required = <1>;\n\tqcom,forced_speed = <1000>;\n\tqcom,forced_duplex = <1>;\n\tvlan_tag = <1 0x20>;\n};\n\n&mdio {\n\tstatus = \"okay\";\n};\n\n&tlmm {\n\tserial_pins: serial_pinmux {\n\t\tmux {\n\t\t\tpins = \"gpio60\", \"gpio61\";\n\t\t\tfunction = \"blsp_uart0\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tspi_0_pins: spi_0_pinmux {\n\t\tmux {\n\t\t\tfunction = \"blsp_spi0\";\n\t\t\tpins = \"gpio55\", \"gpio56\", \"gpio57\";\n\t\t\tdrive-strength = <12>;\n\t\t\tbias-disable;\n\t\t};\n\t\tmux_cs {\n\t\t\tfunction = \"gpio\";\n\t\t\tpins = \"gpio54\";\n\t\t\tdrive-strength = <2>;\n\t\t\tbias-disable;\n\t\t\toutput-high;\n\t\t};\n\t};\n};\n\n&wifi0 {\n\tstatus = \"okay\";\n\tqcom,ath10k-calibration-variant = \"dlink,dap-2610\";\n};\n\n&wifi1 {\n\tstatus = \"okay\";\n\tqcom,ath10k-calibration-variant = \"dlink,dap-2610\";\n};\n"
  },
  {
    "path": "target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-ea6350v3.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qcom-ipq4019.dtsi\"\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/soc/qcom,tcsr.h>\n\n/ {\n\tmodel = \"Linksys EA6350v3\";\n\tcompatible = \"linksys,ea6350v3\";\n\n\taliases {\n\t\tled-boot = &power;\n\t\tled-failsafe = &power;\n\t\tled-running = &power;\n\t\tled-upgrade = &power;\n\t};\n\n\tsoc {\n\t\trng@22000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tmdio@90000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tess-psgmii@98000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\ttcsr@1949000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1949000 0x100>;\n\t\t\tqcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;\n\t\t};\n\n\t\ttcsr@194b000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x194b000 0x100>;\n\t\t\tqcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;\n\t\t};\n\n\t\tess_tcsr@1953000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1953000 0x1000>;\n\t\t\tqcom,ess-interface-select = <TCSR_ESS_PSGMII>;\n\t\t};\n\n\t\ttcsr@1957000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1957000 0x100>;\n\t\t\tqcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;\n\t\t};\n\n\t\tusb2@60f8800 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tusb3@8af8800 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tcrypto@8e3a000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\twatchdog@b017000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tess-switch@c000000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tedma@c080000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&tlmm 63 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&tlmm 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tpower: status {\n\t\t\tlabel = \"green:status\";\n\t\t\tgpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&blsp1_uart1 {\n\tpinctrl-0 = <&serial_pins>;\n\tpinctrl-names = \"default\";\n\tstatus = \"okay\";\n};\n\n&cryptobam {\n\tstatus = \"okay\";\n};\n\n&wifi0 {\n\tstatus = \"okay\";\n\tnvmem-cell-names = \"pre-calibration\";\n\tnvmem-cells = <&precal_art_1000>;\n\tqcom,ath10k-calibration-variant = \"linksys-ea6350v3\";\n};\n\n&wifi1 {\n\tstatus = \"okay\";\n\tnvmem-cell-names = \"pre-calibration\";\n\tnvmem-cells = <&precal_art_5000>;\n\tqcom,ath10k-calibration-variant = \"linksys-ea6350v3\";\n};\n\n&blsp_dma {\n\tstatus = \"okay\";\n};\n\n&tlmm {\n\tserial_pins: serial_pinmux {\n\t\tmux {\n\t\t\tpins = \"gpio60\", \"gpio61\";\n\t\t\tfunction = \"blsp_uart0\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tspi_0_pins: spi_0_pinmux {\n\t\tmux {\n\t\t\tfunction = \"blsp_spi0\";\n\t\t\tpins = \"gpio55\", \"gpio56\", \"gpio57\";\n\t\t\tdrive-strength = <12>;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux_cs {\n\t\t\tfunction = \"gpio\";\n\t\t\tpins = \"gpio54\", \"gpio59\";\n\t\t\tdrive-strength = <2>;\n\t\t\tbias-disable;\n\t\t\toutput-high;\n\t\t};\n\t};\n};\n\n&blsp1_spi1 { /* BLSP1 QUP1 */\n\tpinctrl-0 = <&spi_0_pins>;\n\tpinctrl-names = \"default\";\n\tstatus = \"okay\";\n\tcs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>,\n\t\t   <&tlmm 59 GPIO_ACTIVE_HIGH>;\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <24000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tSBL1@0 {\n\t\t\t\tlabel = \"SBL1\";\n\t\t\t\treg = <0x00000000 0x00040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tMBIB@40000 {\n\t\t\t\tlabel = \"MIBIB\";\n\t\t\t\treg = <0x00040000 0x00020000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tQSEE@60000 {\n\t\t\t\tlabel = \"QSEE\";\n\t\t\t\treg = <0x00060000 0x00060000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tCDT@c0000 {\n\t\t\t\tlabel = \"CDT\";\n\t\t\t\treg = <0x000c0000 0x00010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tAPPSBLENV@d0000 {\n\t\t\t\tlabel = \"APPSBLENV\";\n\t\t\t\treg = <0x000d0000 0x00010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tAPPSBL@e0000 {\n\t\t\t\tlabel = \"APPSBL\"; /* uboot */\n\t\t\t\treg = <0x000e0000 0x00080000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tART@160000 {\n\t\t\t\tlabel = \"ART\";\n\t\t\t\treg = <0x00160000 0x00010000>;\n\t\t\t\tread-only;\n\t\t\t\tcompatible = \"nvmem-cells\";\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\n\t\t\t\tprecal_art_1000: precal@1000 {\n\t\t\t\t\treg = <0x1000 0x2f20>;\n\t\t\t\t};\n\n\t\t\t\tprecal_art_5000: precal@5000 {\n\t\t\t\t\treg = <0x5000 0x2f20>;\n\t\t\t\t};\n\t\t\t};\n\t\t\tu_env@170000 {\n\t\t\t\tlabel = \"u_env\";\n\t\t\t\treg = <0x00170000 0x00020000>;\n\t\t\t};\n\t\t\ts_env@190000 {\n\t\t\t\tlabel = \"s_env\";\n\t\t\t\treg = <0x00190000 0x00020000>;\n\t\t\t};\n\t\t\tdevinfo@1b0000 {\n\t\t\t\tlabel = \"devinfo\";\n\t\t\t\treg = <0x001b0000 0x00010000>;\n\t\t\t};\n\t\t\t/* 0x001c0000 - 0x00200000 unused */\n\t\t};\n\t};\n\n\tflash@1 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"spi-nand\";\n\t\treg = <1>;\n\t\tspi-max-frequency = <24000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tkernel@0 {\n\t\t\t\tlabel = \"kernel\";\n\t\t\t\treg = <0x00000000 0x02800000>;\n\t\t\t};\n\t\t\trootfs@300000 {\n\t\t\t\tlabel = \"rootfs\";\n\t\t\t\treg = <0x00300000 0x02500000>;\n\t\t\t};\n\t\t\talt_kernel@2800000 {\n\t\t\t\tlabel = \"alt_kernel\";\n\t\t\t\treg = <0x02800000 0x02800000>;\n\t\t\t};\n\t\t\talt_rootfs@2b00000 {\n\t\t\t\tlabel = \"alt_rootfs\";\n\t\t\t\treg = <0x02b00000 0x02500000>;\n\t\t\t};\n\t\t\tsysdiag@5000000 {\n\t\t\t\tlabel = \"sysdiag\";\n\t\t\t\treg = <0x05000000 0x00100000>;\n\t\t\t};\n\t\t\tsyscfg@5100000 {\n\t\t\t\tlabel = \"syscfg\";\n\t\t\t\treg = <0x05100000 0x02F00000>;\n\t\t\t};\n\t\t\t/* 0x00000000 - 0x08000000: 128 MiB */\n\t\t};\n\t};\n};\n\n&usb3_ss_phy {\n\tstatus = \"okay\";\n};\n\n&usb3_hs_phy {\n\tstatus = \"okay\";\n};\n\n&usb2_hs_phy {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-eap1300.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later\n\n#include \"qcom-ipq4019.dtsi\"\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/soc/qcom,tcsr.h>\n\n/ {\n\tmodel = \"EnGenius EAP1300\";\n\tcompatible = \"engenius,eap1300\";\n\n\tsoc {\n\t\trng@22000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tmdio@90000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tess-psgmii@98000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\ttcsr@1949000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1949000 0x100>;\n\t\t\tqcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;\n\t\t};\n\n\t\tess_tcsr@1953000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1953000 0x1000>;\n\t\t\tqcom,ess-interface-select = <TCSR_ESS_PSGMII>;\n\t\t};\n\n\t\ttcsr@1957000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1957000 0x100>;\n\t\t\tqcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;\n\t\t};\n\n\t\tcrypto@8e3a000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\twatchdog@b017000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tess-switch@c000000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tedma@c080000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&tlmm 18 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\taliases {\n\t\tled-boot = &power;\n\t\tled-failsafe = &power;\n\t\tled-running = &power;\n\t\tled-upgrade = &power;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tpower: orange {\n\t\t\tlabel = \"orange:power\";\n\t\t\tgpios = <&tlmm 58 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan {\n\t\t\tlabel = \"blue:lan\";\n\t\t\tgpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tmesh {\n\t\t\tlabel = \"blue:mesh\";\n\t\t\tgpios = <&tlmm 1 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\twlan2g {\n\t\t\tlabel = \"blue:wlan2g\";\n\t\t\tgpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\twlan5g {\n\t\t\tlabel = \"yellow:wlan5g\";\n\t\t\tgpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&tlmm {\n\tserial_pins: serial_pinmux {\n\t\tmux {\n\t\t\tpins = \"gpio60\", \"gpio61\";\n\t\t\tfunction = \"blsp_uart0\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tspi_0_pins: spi_0_pinmux {\n\t\tpin {\n\t\t\tfunction = \"blsp_spi0\";\n\t\t\tpins = \"gpio54\", \"gpio55\", \"gpio56\", \"gpio57\";\n\t\t\tdrive-strength = <12>;\n\t\t\tbias-disable;\n\t\t};\n\t\tpin_cs {\n\t\t\tfunction = \"gpio\";\n\t\t\tpins = \"gpio54\";\n\t\t\tdrive-strength = <2>;\n\t\t\tbias-disable;\n\t\t\toutput-high;\n\t\t};\n\t};\n};\n\n&blsp_dma {\n\tstatus = \"okay\";\n};\n\n&blsp1_spi1 {\n\tpinctrl-0 = <&spi_0_pins>;\n\tpinctrl-names = \"default\";\n\tstatus = \"okay\";\n\tcs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;\n\n\tm25p80@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <24000000>;\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"0:SBL1\";\n\t\t\t\treg = <0x00000000 0x00040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition1@40000 {\n\t\t\t\tlabel = \"0:MIBIB\";\n\t\t\t\treg = <0x00040000 0x00020000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition2@60000 {\n\t\t\t\tlabel = \"0:QSEE\";\n\t\t\t\treg = <0x00060000 0x00060000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition3@c0000 {\n\t\t\t\tlabel = \"0:CDT\";\n\t\t\t\treg = <0x000c0000 0x00010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition4@d0000 {\n\t\t\t\tlabel = \"0:DDRPARAMS\";\n\t\t\t\treg = <0x000d0000 0x00010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition5@e0000 {\n\t\t\t\tlabel = \"0:APPSBLENV\";\n\t\t\t\treg = <0x000e0000 0x00010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition6@f0000 {\n\t\t\t\tlabel = \"0:APPSBL\";\n\t\t\t\treg = <0x000f0000 0x00090000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition7@180000 {\n\t\t\t\tlabel = \"0:ART\";\n\t\t\t\treg = <0x00180000 0x00010000>;\n\t\t\t\tread-only;\n\t\t\t\tcompatible = \"nvmem-cells\";\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\n\t\t\t\tprecal_art_1000: precal@1000 {\n\t\t\t\t\treg = <0x1000 0x2f20>;\n\t\t\t\t};\n\n\t\t\t\tprecal_art_5000: precal@5000 {\n\t\t\t\t\treg = <0x5000 0x2f20>;\n\t\t\t\t};\n\t\t\t};\n\t\t\tpartition8@190000 {\n\t\t\t\tcompatible = \"denx,fit\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x190000 0x1dc0000>;\n\t\t\t};\n\t\t\tpartition9@1f50000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x01f50000 0x00010000>;\n\t\t\t};\n\t\t\tpartition10@1f60000 {\n\t\t\t\tlabel = \"userconfig\";\n\t\t\t\treg = <0x01f60000 0x000a0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&blsp1_uart1 {\n\tpinctrl-0 = <&serial_pins>;\n\tpinctrl-names = \"default\";\n\tstatus = \"okay\";\n};\n\n&cryptobam {\n\tstatus = \"okay\";\n};\n\n&gmac0 {\n\tvlan_tag = <2 0x20>;\n};\n\n&gmac1 {\n\tvlan_tag = <1 0x10>;\n};\n\n&wifi0 {\n\tstatus = \"okay\";\n\tnvmem-cell-names = \"pre-calibration\";\n\tnvmem-cells = <&precal_art_1000>;\n\tqcom,ath10k-calibration-variant = \"EnGenius-EAP1300\";\n};\n\n&wifi1 {\n\tstatus = \"okay\";\n\tnvmem-cell-names = \"pre-calibration\";\n\tnvmem-cells = <&precal_art_5000>;\n\tqcom,ath10k-calibration-variant = \"EnGenius-EAP1300\";\n};\n"
  },
  {
    "path": "target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-ecw5211.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qcom-ipq4019.dtsi\"\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/soc/qcom,tcsr.h>\n\n/ {\n\tmodel = \"Edgecore ECW5211\";\n\tcompatible = \"edgecore,ecw5211\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t\tlabel-mac-device = &gmac0;\n\t};\n\n\tchosen {\n\t\tbootargs-append = \" root=/dev/ubiblock0_1\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&tlmm 63 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"yellow:power\";\n\t\t\tgpios = <&tlmm 5 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan2g {\n\t\t\tlabel = \"green:wlan2g\";\n\t\t\tgpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\twlan5g {\n\t\t\tlabel = \"green:wlan5g\";\n\t\t\tgpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\t};\n\n\tsoc {\n\t\trng@22000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tess-psgmii@98000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tcounter@4a1000 {\n\t\t\tcompatible = \"qcom,qca-gcnt\";\n\t\t\treg = <0x4a1000 0x4>;\n\t\t};\n\n\t\ttcsr@1949000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1949000 0x100>;\n\t\t\tqcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;\n\t\t};\n\n\t\ttcsr@194b000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x194b000 0x100>;\n\t\t\tqcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;\n\t\t};\n\n\t\tess_tcsr@1953000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1953000 0x1000>;\n\t\t\tqcom,ess-interface-select = <TCSR_ESS_PSGMII>;\n\t\t};\n\n\t\ttcsr@1957000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1957000 0x100>;\n\t\t\tqcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;\n\t\t};\n\n\t\tusb2@60f8800 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tusb3@8af8800 {\n\t\t\tstatus = \"okay\";\n\n\t\t\tdwc3@8a00000 {\n\t\t\t\tphys = <&usb3_hs_phy>;\n\t\t\t\tphy-names = \"usb2-phy\";\n\t\t\t};\n\t\t};\n\n\t\tcrypto@8e3a000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\twatchdog@b017000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tess-switch@c000000 {\n\t\t\tstatus = \"okay\";\n\n\t\t\tswitch_lan_bmp = <0x10>;\n\t\t\tswitch_wan_bmp = <0x20>;\n\t\t};\n\n\t\tedma@c080000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\t};\n};\n\n&tlmm {\n\tmdio_pins: mdio_pinmux {\n\t\tmux_mdio {\n\t\t\tpins = \"gpio53\";\n\t\t\tfunction = \"mdio\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tmux_mdc {\n\t\t\tpins = \"gpio52\";\n\t\t\tfunction = \"mdc\";\n\t\t\tbias-pull-up;\n\t\t};\n\t};\n\n\tserial_pins: serial_pinmux {\n\t\tmux {\n\t\t\tpins = \"gpio60\", \"gpio61\";\n\t\t\tfunction = \"blsp_uart0\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tspi0_pins: spi0_pinmux {\n\t\tpin {\n\t\t\tfunction = \"blsp_spi0\";\n\t\t\tpins = \"gpio55\", \"gpio56\", \"gpio57\";\n\t\t\tdrive-strength = <2>;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tpin_cs {\n\t\t\tfunction = \"gpio\";\n\t\t\tpins = \"gpio54\", \"gpio4\";\n\t\t\tdrive-strength = <2>;\n\t\t\tbias-disable;\n\t\t\toutput-high;\n\t\t};\n\t};\n\n\ti2c0_pins: i2c0_pinmux {\n\t\tmux_i2c {\n\t\t\tfunction = \"blsp_i2c0\";\n\t\t\tpins = \"gpio58\", \"gpio59\";\n\t\t\tdrive-strength = <16>;\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&blsp_dma {\n\tstatus = \"okay\";\n};\n\n&blsp1_spi1 {\n\tstatus = \"okay\";\n\n\tpinctrl-0 = <&spi0_pins>;\n\tpinctrl-names = \"default\";\n\tcs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>, <&tlmm 4 GPIO_ACTIVE_HIGH>;\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <24000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"0:SBL1\";\n\t\t\t\treg = <0x00000000 0x00040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"0:MIBIB\";\n\t\t\t\treg = <0x00040000 0x00020000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@60000 {\n\t\t\t\tlabel = \"0:QSEE\";\n\t\t\t\treg = <0x00060000 0x00060000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@c0000 {\n\t\t\t\tlabel = \"0:CDT\";\n\t\t\t\treg = <0x000c0000 0x00010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@d0000 {\n\t\t\t\tlabel = \"0:DDRPARAMS\";\n\t\t\t\treg = <0x000d0000 0x00010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@e0000 {\n\t\t\t\tlabel = \"0:APPSBLENV\"; /* uboot env */\n\t\t\t\treg = <0x000e0000 0x00010000>;\n\t\t\t};\n\n\t\t\tpartition@f0000 {\n\t\t\t\tlabel = \"0:APPSBL\"; /* uboot */\n\t\t\t\treg = <0x000f0000 0x00080000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@170000 {\n\t\t\t\tlabel = \"0:ART\";\n\t\t\t\treg = <0x00170000 0x00010000>;\n\t\t\t\tread-only;\n\t\t\t\tcompatible = \"nvmem-cells\";\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\n\t\t\t\tprecal_art_1000: precal@1000 {\n\t\t\t\t\treg = <0x1000 0x2f20>;\n\t\t\t\t};\n\n\t\t\t\tprecal_art_5000: precal@5000 {\n\t\t\t\t\treg = <0x5000 0x2f20>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t};\n\n\tflash@1 {\n\t\tcompatible = \"spi-nand\";\n\t\treg = <1>;\n\t\tspi-max-frequency = <24000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"rootfs\";\n\t\t\t\treg = <0x00000000 0x04000000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&blsp1_i2c3 {\n\tstatus = \"okay\";\n\n\tpinctrl-0 = <&i2c0_pins>;\n\tpinctrl-names = \"default\";\n\n\ttpm@29 {\n\t\tcompatible = \"atmel,at97sc3204t\";\n\t\treg = <0x29>;\n\t};\n};\n\n&blsp1_uart1 {\n\tstatus = \"okay\";\n\n\tpinctrl-0 = <&serial_pins>;\n\tpinctrl-names = \"default\";\n};\n\n&cryptobam {\n\tstatus = \"okay\";\n};\n\n&mdio {\n\tstatus = \"okay\";\n\n\tpinctrl-0 = <&mdio_pins>;\n\tpinctrl-names = \"default\";\n};\n\n&gmac0 {\n\tqcom,poll_required = <1>;\n\tqcom,phy_mdio_addr = <4>;\n\tvlan_tag = <2 0x20>;\n};\n\n&gmac1 {\n\tqcom,poll_required = <1>;\n\tqcom,phy_mdio_addr = <3>;\n\tvlan_tag = <1 0x10>;\n};\n\n&wifi0 {\n\tstatus = \"okay\";\n\tnvmem-cell-names = \"pre-calibration\";\n\tnvmem-cells = <&precal_art_1000>;\n};\n\n&wifi1 {\n\tstatus = \"okay\";\n\tnvmem-cell-names = \"pre-calibration\";\n\tnvmem-cells = <&precal_art_5000>;\n\tqcom,ath10k-calibration-variant = \"ALFA-Network-AP120C-AC\";\n};\n\n&usb3_hs_phy {\n\tstatus = \"okay\";\n};\n\n&usb2_hs_phy {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-emd1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later\n\n#include \"qcom-ipq4019.dtsi\"\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/soc/qcom,tcsr.h>\n\n/ {\n\tmodel = \"EnGenius EMD1\";\n\tcompatible = \"engenius,emd1\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tsoc {\n\t\trng@22000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tmdio@90000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tess-psgmii@98000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\ttcsr@1949000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1949000 0x100>;\n\t\t\tqcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;\n\t\t};\n\n\t\tess_tcsr@1953000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1953000 0x1000>;\n\t\t\tqcom,ess-interface-select = <TCSR_ESS_PSGMII>;\n\t\t};\n\n\t\ttcsr@1957000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1957000 0x100>;\n\t\t\tqcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;\n\t\t};\n\n\t\tcrypto@8e3a000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\twatchdog@b017000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tess-switch@c000000 {\n\t\t\tstatus = \"okay\";\n\t\t\tswitch_lan_bmp = <0x20>;\n\t\t\tswitch_wan_bmp = <0x00>;\n\t\t};\n\n\t\tedma@c080000 {\n\t\t\tstatus = \"okay\";\n\t\t\tqcom,num_gmac = <1>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&tlmm 63 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"white:power\";\n\t\t\tgpios = <&tlmm 58 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan2g {\n\t\t\tlabel = \"red:wlan2g\";\n\t\t\tgpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\twlan5g {\n\t\t\tlabel = \"blue:wlan5g\";\n\t\t\tgpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\n\t\tmesh {\n\t\t\tlabel = \"orange:mesh\";\n\t\t\tgpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&tlmm {\n\tserial_pins: serial_pinmux {\n\t\tmux {\n\t\t\tpins = \"gpio60\", \"gpio61\";\n\t\t\tfunction = \"blsp_uart0\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tspi_0_pins: spi_0_pinmux {\n\t\tpin {\n\t\t\tfunction = \"blsp_spi0\";\n\t\t\tpins = \"gpio54\", \"gpio55\", \"gpio56\", \"gpio57\";\n\t\t\tdrive-strength = <12>;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tpin_cs {\n\t\t\tfunction = \"gpio\";\n\t\t\tpins = \"gpio54\";\n\t\t\tdrive-strength = <2>;\n\t\t\tbias-disable;\n\t\t\toutput-high;\n\t\t};\n\t};\n};\n\n&blsp_dma {\n\tstatus = \"okay\";\n};\n\n&blsp1_spi1 {\n\tpinctrl-0 = <&spi_0_pins>;\n\tpinctrl-names = \"default\";\n\tstatus = \"okay\";\n\tcs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <24000000>;\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition0@0 {\n\t\t\t\tlabel = \"0:SBL1\";\n\t\t\t\treg = <0x00000000 0x00040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition1@40000 {\n\t\t\t\tlabel = \"0:MIBIB\";\n\t\t\t\treg = <0x00040000 0x00020000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition2@60000 {\n\t\t\t\tlabel = \"0:QSEE\";\n\t\t\t\treg = <0x00060000 0x00060000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition3@c0000 {\n\t\t\t\tlabel = \"0:CDT\";\n\t\t\t\treg = <0x000c0000 0x00010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition4@d0000 {\n\t\t\t\tlabel = \"0:DDRPARAMS\";\n\t\t\t\treg = <0x000d0000 0x00010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition5@e0000 {\n\t\t\t\tlabel = \"0:APPSBLENV\";\n\t\t\t\treg = <0x000e0000 0x00010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition6@f0000 {\n\t\t\t\tlabel = \"0:APPSBL\";\n\t\t\t\treg = <0x000f0000 0x00080000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition7@170000 {\n\t\t\t\tlabel = \"0:ART\";\n\t\t\t\treg = <0x00170000 0x00010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition8@180000 {\n\t\t\t\tlabel = \"userconfig\";\n\t\t\t\treg = <0x00180000 0x00080000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition9@200000 {\n\t\t\t\tcompatible = \"denx,fit\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x200000 0x01e00000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&blsp1_uart1 {\n\tpinctrl-0 = <&serial_pins>;\n\tpinctrl-names = \"default\";\n\tstatus = \"okay\";\n};\n\n&gmac0 {\n\tqcom,phy_mdio_addr = <4>;\n\tqcom,poll_required = <1>;\n\tqcom,forced_speed = <1000>;\n\tqcom,forced_duplex = <1>;\n\tvlan_tag = <1 0x20>;\n};\n\n&cryptobam {\n\tstatus = \"okay\";\n};\n\n&wifi0 {\n\tstatus = \"okay\";\n\tqcom,ath10k-calibration-variant = \"EnGenius-EMD1\";\n};\n\n&wifi1 {\n\tstatus = \"okay\";\n\tqcom,ath10k-calibration-variant = \"EnGenius-EMD1\";\n};\n"
  },
  {
    "path": "target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-emr3500.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later\n\n#include \"qcom-ipq4019.dtsi\"\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/soc/qcom,tcsr.h>\n\n/ {\n\tmodel = \"EnGenius EMR3500\";\n\tcompatible = \"engenius,emr3500\";\n\n\tsoc {\n\t\trng@22000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tmdio@90000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tess-psgmii@98000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\ttcsr@1949000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1949000 0x100>;\n\t\t\tqcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;\n\t\t};\n\n\t\tess_tcsr@1953000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1953000 0x1000>;\n\t\t\tqcom,ess-interface-select = <TCSR_ESS_PSGMII>;\n\t\t};\n\n\t\ttcsr@1957000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1957000 0x100>;\n\t\t\tqcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;\n\t\t};\n\n\t\tusb2_hs_phy: hsphy@a8000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tcrypto@8e3a000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\twatchdog@b017000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tess-switch@c000000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tedma@c080000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&tlmm 59 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\taliases {\n\t\tled-boot = &power;\n\t\tled-failsafe = &power;\n\t\tled-running = &power;\n\t\tled-upgrade = &power;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tpower: white {\n\t\t\tlabel = \"white:power\";\n\t\t\tgpios = <&tlmm 4 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tblue {\n\t\t\tlabel = \"blue\";\n\t\t\tgpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tred {\n\t\t\tlabel = \"red\";\n\t\t\tgpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\torange {\n\t\t\tlabel = \"orange\";\n\t\t\tgpios = <&tlmm 1 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&tlmm {\n\tserial_pins: serial_pinmux {\n\t\tmux {\n\t\t\tpins = \"gpio60\", \"gpio61\";\n\t\t\tfunction = \"blsp_uart0\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tspi_0_pins: spi_0_pinmux {\n\t\tpin {\n\t\t\tfunction = \"blsp_spi0\";\n\t\t\tpins = \"gpio54\", \"gpio55\", \"gpio56\", \"gpio57\";\n\t\t\tdrive-strength = <12>;\n\t\t\tbias-disable;\n\t\t};\n\t\tpin_cs {\n\t\t\tfunction = \"gpio\";\n\t\t\tpins = \"gpio54\";\n\t\t\tdrive-strength = <2>;\n\t\t\tbias-disable;\n\t\t\toutput-high;\n\t\t};\n\t};\n};\n\n&blsp_dma {\n\tstatus = \"okay\";\n};\n\n&blsp1_spi1 {\n\tpinctrl-0 = <&spi_0_pins>;\n\tpinctrl-names = \"default\";\n\tstatus = \"okay\";\n\tcs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;\n\n\tm25p80@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <24000000>;\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"0:SBL1\";\n\t\t\t\treg = <0x00000000 0x00040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"0:MIBIB\";\n\t\t\t\treg = <0x00040000 0x00020000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@60000 {\n\t\t\t\tlabel = \"0:QSEE\";\n\t\t\t\treg = <0x00060000 0x00060000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@c0000 {\n\t\t\t\tlabel = \"0:CDT\";\n\t\t\t\treg = <0x000c0000 0x00010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@d0000 {\n\t\t\t\tlabel = \"0:DDRPARAMS\";\n\t\t\t\treg = <0x000d0000 0x00010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@e0000 {\n\t\t\t\tlabel = \"0:APPSBLENV\";\n\t\t\t\treg = <0x000e0000 0x00010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@f0000 {\n\t\t\t\tlabel = \"0:APPSBL\";\n\t\t\t\treg = <0x000f0000 0x00080000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@170000 {\n\t\t\t\tlabel = \"0:ART\";\n\t\t\t\treg = <0x00170000 0x00010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@180000 {\n\t\t\t\tlabel = \"userconfig\";\n\t\t\t\treg = <0x00180000 0x00080000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@200000 {\n\t\t\t\tcompatible = \"denx,fit\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x200000 0x1e00000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&blsp1_uart1 {\n\tpinctrl-0 = <&serial_pins>;\n\tpinctrl-names = \"default\";\n\tstatus = \"okay\";\n};\n\n&cryptobam {\n\tstatus = \"okay\";\n};\n\n&gmac0 {\n\tvlan_tag = <1 0x10>;\n};\n\n&gmac1 {\n\tvlan_tag = <2 0x20>;\n};\n\n&usb2_hs_phy {\n\tstatus = \"okay\";\n};\n\n&wifi0 {\n\tstatus = \"okay\";\n\tqcom,ath10k-calibration-variant = \"EnGenius-EMR3500\";\n};\n\n&wifi1 {\n\tstatus = \"okay\";\n\tqcom,ath10k-calibration-variant = \"EnGenius-EMR3500\";\n};\n"
  },
  {
    "path": "target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-ens620ext.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qcom-ipq4019.dtsi\"\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/soc/qcom,tcsr.h>\n\n/ {\n\tmodel = \"EnGenius ENS620EXT\";\n\tcompatible = \"engenius,ens620ext\";\n\n\tmemory {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x80000000 0x10000000>;\n\t};\n\n\taliases {\n\t\tled-boot = &power;\n\t\tled-failsafe = &power;\n\t\tled-running = &power;\n\t\tled-upgrade = &power;\n\t};\n\n\tsoc {\n\t\trng@22000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tmdio@90000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tess-psgmii@98000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\ttcsr@1949000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1949000 0x100>;\n\t\t\tqcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;\n\t\t};\n\n\t\tess_tcsr@1953000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1953000 0x1000>;\n\t\t\tqcom,ess-interface-select = <TCSR_ESS_PSGMII>;\n\t\t};\n\n\t\ttcsr@1957000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1957000 0x100>;\n\t\t\tqcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;\n\t\t};\n\n\t\tcrypto@8e3a000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\twatchdog@b017000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tess-switch@c000000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tedma@c080000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\t/*\n\t\t * Disable the broken restart as a workaround for the buggy\n\t\t * 3.0.0/3.0.1 U-boots that ship with the device.\n\t\t * Note: The watchdog is now used to restart this device.\n\t\t */\n\t\trestart@4ab000 {\n\t\t\tstatus = \"disabled\";\n\t\t};\n\t};\n\n\tbuttons {\n\t\tcompatible = \"gpio-keys\";\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&tlmm 63 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tpower: power {\n\t\t\tlabel = \"amber:power\";\n\t\t\tgpios = <&tlmm 58 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan1 {\n\t\t\tlabel = \"green:lan1\";\n\t\t\tgpios = <&tlmm 1 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan2 {\n\t\t\tlabel = \"green:lan2\";\n\t\t\tgpios = <&tlmm 2 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan2g {\n\t\t\tlabel = \"green:wlan2g\";\n\t\t\tgpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\twlan5g {\n\t\t\tlabel = \"green:wlan5g\";\n\t\t\tgpios = <&tlmm 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&cryptobam {\n\tstatus = \"okay\";\n};\n\n&blsp_dma {\n\tstatus = \"okay\";\n};\n\n&tlmm {\n\tserial_pins: serial_pinmux {\n\t\tmux {\n\t\t\tpins = \"gpio60\", \"gpio61\";\n\t\t\tfunction = \"blsp_uart0\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tspi_0_pins: spi_0_pinmux {\n\t\tmux {\n\t\t\tfunction = \"blsp_spi0\";\n\t\t\tpins = \"gpio55\", \"gpio56\", \"gpio57\";\n\t\t\tdrive-strength = <12>;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux_cs {\n\t\t\tfunction = \"gpio\";\n\t\t\tpins = \"gpio54\";\n\t\t\tdrive-strength = <2>;\n\t\t\tbias-disable;\n\t\t\toutput-high;\n\t\t};\n\t};\n};\n\n&blsp1_spi1 { /* BLSP1 QUP1 */\n\tpinctrl-0 = <&spi_0_pins>;\n\tpinctrl-names = \"default\";\n\tstatus = \"okay\";\n\tcs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;\n\n\tflash@0 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <50000000>;\n\t\tm25p,fast-read;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"SBL1\";\n\t\t\t\treg = <0x00000000 0x00040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"MIBIB\";\n\t\t\t\treg = <0x00040000 0x00020000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@60000 {\n\t\t\t\tlabel = \"QSEE\";\n\t\t\t\treg = <0x00060000 0x00060000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@c0000 {\n\t\t\t\tlabel = \"CDT\";\n\t\t\t\treg = <0x000c0000 0x00010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@d0000 {\n\t\t\t\tlabel = \"DDRPARAMS\";\n\t\t\t\treg = <0x000d0000 0x00010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@e0000 {\n\t\t\t\tlabel = \"APPSBLENV\"; /* uboot env*/\n\t\t\t\treg = <0x000e0000 0x00010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@f0000 {\n\t\t\t\tlabel = \"APPSBL\"; /* uboot */\n\t\t\t\treg = <0x000f0000 0x00090000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@180000 {\n\t\t\t\tlabel = \"ART\";\n\t\t\t\treg = <0x00180000 0x00010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@190000 {\n\t\t\t\tcompatible = \"denx,fit\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x00190000 0x14d0000>;\n\t\t\t};\n\t\t\tpartition@1660000 {\n\t\t\t\tlabel = \"failsafe\";\n\t\t\t\treg = <0x01660000 0x008F0000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@1f50000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x01f50000 0x00010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@1f60000 {\n\t\t\t\tlabel = \"userconfig\";\n\t\t\t\treg = <0x01f60000 0x000a0000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&blsp1_uart1 {\n\tpinctrl-0 = <&serial_pins>;\n\tpinctrl-names = \"default\";\n\tstatus = \"okay\";\n};\n\n&usb3_ss_phy {\n\tstatus = \"okay\";\n};\n\n&usb3_hs_phy {\n\tstatus = \"okay\";\n};\n\n&usb2_hs_phy {\n\tstatus = \"okay\";\n};\n\n&wifi0 {\n\tstatus = \"okay\";\n\tqcom,ath10k-calibration-variant = \"EnGenius-ENS620EXT\";\n};\n\n&wifi1 {\n\tstatus = \"okay\";\n\tqcom,ath10k-calibration-variant = \"EnGenius-ENS620EXT\";\n};\n"
  },
  {
    "path": "target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-ex6100v2.dts",
    "content": "/* Copyright (c) 2015, The Linux Foundation. All rights reserved.\n * Copyright (c) 2018, David Bauer <mail@david-bauer.net>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#include \"qcom-ipq4018-ex61x0v2.dtsi\"\n\n/ {\n\tmodel = \"Netgear EX6100v2\";\n\tcompatible = \"netgear,ex6100v2\";\n};\n\n&wifi0 {\n\tqcom,ath10k-calibration-variant = \"Netgear-EX6100v2\";\n};\n\n&wifi1 {\n\tqcom,ath10k-calibration-variant = \"Netgear-EX6100v2\";\n};\n"
  },
  {
    "path": "target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-ex6150v2.dts",
    "content": "/* Copyright (c) 2015, The Linux Foundation. All rights reserved.\n * Copyright (c) 2018, David Bauer <mail@david-bauer.net>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#include \"qcom-ipq4018-ex61x0v2.dtsi\"\n\n/ {\n\tmodel = \"Netgear EX6150v2\";\n\tcompatible = \"netgear,ex6150v2\";\n};\n\n&wifi0 {\n\tqcom,ath10k-calibration-variant = \"Netgear-EX6150v2\";\n};\n\n&wifi1 {\n\tqcom,ath10k-calibration-variant = \"Netgear-EX6150v2\";\n};\n"
  },
  {
    "path": "target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-ex61x0v2.dtsi",
    "content": "/* Copyright (c) 2015, The Linux Foundation. All rights reserved.\n * Copyright (c) 2018, David Bauer <mail@david-bauer.net>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#include \"qcom-ipq4019.dtsi\"\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/soc/qcom,tcsr.h>\n\n/ {\n\tmodel = \"Netgear EX61X0v2\";\n\tcompatible = \"netgear,ex61x0v2\";\n\n\tsoc {\n\t\trng@22000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tmdio@90000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tess-psgmii@98000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\ttcsr@1949000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1949000 0x100>;\n\t\t\tqcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;\n\t\t};\n\n\t\tess_tcsr@1953000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1953000 0x1000>;\n\t\t\tqcom,ess-interface-select = <TCSR_ESS_PSGMII>;\n\t\t};\n\n\t\ttcsr@1957000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1957000 0x100>;\n\t\t\tqcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;\n\t\t};\n\n\t\tcrypto@8e3a000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\twatchdog@b017000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tess-switch@c000000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tedma@c080000 {\n\t\t\tstatus = \"okay\";\n\t\t\tqcom,num_gmac = <1>;\n\t\t};\n\t};\n\n\taliases {\n\t\tled-boot = &power_amber;\n\t\tled-failsafe = &power_amber;\n\t\tled-running = &power_green;\n\t\tled-upgrade = &power_amber;\n\t\tlabel-mac-device = &gmac0;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&tlmm 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&tlmm 63 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tled_spi {\n\t\tcompatible = \"spi-gpio\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tsck-gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>;\n\t\tmosi-gpios = <&tlmm 4 GPIO_ACTIVE_HIGH>;\n\t\tnum-chipselects = <0>;\n\n\t\tled_gpio: led_gpio@0 {\n\t\t\tcompatible = \"fairchild,74hc595\";\n\t\t\treg = <0>;\n\t\t\tgpio-controller;\n\t\t\t#gpio-cells = <2>;\n\t\t\tregisters-number = <1>;\n\t\t\tspi-max-frequency = <1000000>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tpower_amber: power_amber {\n\t\t\tlabel = \"amber:power\";\n\t\t\tgpios = <&led_gpio 7 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tpower_green: power_green {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&led_gpio 6 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tright {\n\t\t\tlabel = \"blue:right\";\n\t\t\tgpios = <&led_gpio 5 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tleft {\n\t\t\tlabel = \"blue:left\";\n\t\t\tgpios = <&led_gpio 4 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tclient_green {\n\t\t\tlabel = \"green:client\";\n\t\t\tgpios = <&led_gpio 3 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tclient_red {\n\t\t\tlabel = \"red:client\";\n\t\t\tgpios = <&led_gpio 2 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\trouter_green {\n\t\t\tlabel = \"green:router\";\n\t\t\tgpios = <&led_gpio 1 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\trouter_red {\n\t\t\tlabel = \"red:router\";\n\t\t\tgpios = <&led_gpio 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&tlmm 1 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&tlmm {\n\tserial_pins: serial_pinmux {\n\t\tmux {\n\t\t\tpins = \"gpio60\", \"gpio61\";\n\t\t\tfunction = \"blsp_uart0\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tspi_0_pins: spi_0_pinmux {\n\t\tpin {\n\t\t\tfunction = \"blsp_spi0\";\n\t\t\tpins = \"gpio55\", \"gpio56\", \"gpio57\";\n\t\t\tdrive-strength = <12>;\n\t\t\tbias-disable;\n\t\t};\n\t\tpin_cs {\n\t\t\tfunction = \"gpio\";\n\t\t\tpins = \"gpio54\";\n\t\t\tdrive-strength = <2>;\n\t\t\tbias-disable;\n\t\t\toutput-high;\n\t\t};\n\t};\n};\n\n&blsp1_spi1 {\n\tpinctrl-0 = <&spi_0_pins>;\n\tpinctrl-names = \"default\";\n\tstatus = \"okay\";\n\tcs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;\n\n\tmx25l12805d@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <45000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition0@0 {\n\t\t\t\tlabel = \"SBL1\";\n\t\t\t\treg = <0x00000000 0x00040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition1@40000 {\n\t\t\t\tlabel = \"MIBIB\";\n\t\t\t\treg = <0x00040000 0x00020000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition2@60000 {\n\t\t\t\tlabel = \"QSEE\";\n\t\t\t\treg = <0x00060000 0x00060000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition3@c0000 {\n\t\t\t\tlabel = \"CDT\";\n\t\t\t\treg = <0x000c0000 0x00010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition4@d0000 {\n\t\t\t\tlabel = \"DDRPARAMS\";\n\t\t\t\treg = <0x000d0000 0x00010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition5@E0000 {\n\t\t\t\tlabel = \"APPSBLENV\";\n\t\t\t\treg = <0x000e0000 0x00010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition6@F0000 {\n\t\t\t\tlabel = \"APPSBL\";\n\t\t\t\treg = <0x000f0000 0x00080000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition7@170000 {\n\t\t\t\tlabel = \"ART\";\n\t\t\t\treg = <0x00170000 0x00010000>;\n\t\t\t\tcompatible = \"nvmem-cells\";\n\t\t\t\tread-only;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\n\t\t\t\tprecal_art_1000: precal@1000 {\n\t\t\t\t\treg = <0x1000 0x2f20>;\n\t\t\t\t};\n\n\t\t\t\tprecal_art_5000: precal@5000 {\n\t\t\t\t\treg = <0x5000 0x2f20>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tpartition8@180000 {\n\t\t\t\tlabel = \"config\";\n\t\t\t\treg = <0x00180000 0x00010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition9@190000 {\n\t\t\t\tlabel = \"pot\";\n\t\t\t\treg = <0x00190000 0x00010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition10@1a0000 {\n\t\t\t\tcompatible = \"nvmem-cells\";\n\t\t\t\tlabel = \"dnidata\";\n\t\t\t\treg = <0x001a0000 0x00010000>;\n\t\t\t\tread-only;\n\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\n\t\t\t\tmacaddr_dnidata_0: macaddr@0 {\n\t\t\t\t\treg = <0x0 0x6>;\n\t\t\t\t};\n\n\t\t\t\tmacaddr_dnidata_c: macaddr@c {\n\t\t\t\t\treg = <0xc 0x6>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tpartition11@1b0000 {\n\t\t\t\tcompatible = \"denx,fit\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x001b0000 0x00e10000>;\n\t\t\t};\n\n\t\t\tpartition12@fc0000 {\n\t\t\t\tlabel = \"language\";\n\t\t\t\treg = <0x00fc0000 0x00040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&blsp1_uart1 {\n\tpinctrl-0 = <&serial_pins>;\n\tpinctrl-names = \"default\";\n\tstatus = \"okay\";\n};\n\n&blsp_dma {\n\tstatus = \"okay\";\n};\n\n&cryptobam {\n\tstatus = \"okay\";\n};\n\n&wifi0 {\n\tstatus = \"okay\";\n\tnvmem-cell-names = \"pre-calibration\", \"mac-address\";\n\tnvmem-cells = <&precal_art_1000>, <&macaddr_dnidata_0>;\n};\n\n&wifi1 {\n\tstatus = \"okay\";\n\tnvmem-cell-names = \"pre-calibration\", \"mac-address\";\n\tnvmem-cells = <&precal_art_5000>, <&macaddr_dnidata_c>;\n};\n"
  },
  {
    "path": "target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-fritzbox-4040.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qcom-ipq4019.dtsi\"\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/soc/qcom,tcsr.h>\n\n/ {\n\tmodel = \"AVM FRITZ!Box 4040\";\n\tcompatible = \"avm,fritzbox-4040\";\n\n\taliases {\n\t\tled-boot = &power;\n\t\tled-failsafe = &flash;\n\t\tled-running = &power;\n\t\tled-upgrade = &flash;\n\t\tlabel-mac-device = &gmac0;\n\t};\n\n\tsoc {\n\t\trng@22000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tmdio@90000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tess-psgmii@98000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\ttcsr@1949000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1949000 0x100>;\n\t\t\tqcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;\n\t\t};\n\n\t\ttcsr@194b000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x194b000 0x100>;\n\t\t\tqcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;\n\t\t};\n\n\t\tess_tcsr@1953000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1953000 0x1000>;\n\t\t\tqcom,ess-interface-select = <TCSR_ESS_PSGMII>;\n\t\t};\n\n\t\ttcsr@1957000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1957000 0x100>;\n\t\t\tqcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;\n\t\t};\n\n\t\tusb2@60f8800 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tusb3@8af8800 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tcrypto@8e3a000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\twatchdog@b017000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tess-switch@c000000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tedma@c080000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\twlan {\n\t\t\tlabel = \"wlan\";\n\t\t\tgpios = <&tlmm 58 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RFKILL>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&tlmm 63 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n\n\tswitch-leds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twlan {\n\t\t\tlabel = \"green:wlan\";\n\t\t\tgpios = <&ethphy0 0 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tpanic: info_red {\n\t\t\tlabel = \"red:info\";\n\t\t\tgpios = <&ethphy0 1 GPIO_ACTIVE_HIGH>;\n\t\t\tpanic-indicator;\n\t\t};\n\n\t\twan {\n\t\t\tlabel = \"green:wan\";\n\t\t\tgpios = <&ethphy1 0 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tpower: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&ethphy2 1 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tlan {\n\t\t\tlabel = \"green:lan\";\n\t\t\tgpios = <&ethphy3 0 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tflash: info_amber {\n\t\t\tlabel = \"amber:info\";\n\t\t\tgpios = <&ethphy3 1 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&tlmm {\n\tserial_pins: serial_pinmux {\n\t\tmux {\n\t\t\tpins = \"gpio60\", \"gpio61\";\n\t\t\tfunction = \"blsp_uart0\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tspi_0_pins: spi_0_pinmux {\n\t\tmux {\n\t\t\tfunction = \"blsp_spi0\";\n\t\t\tpins = \"gpio55\", \"gpio56\", \"gpio57\";\n\t\t\tdrive-strength = <12>;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux_cs {\n\t\t\tfunction = \"gpio\";\n\t\t\tpins = \"gpio54\";\n\t\t\tdrive-strength = <2>;\n\t\t\tbias-disable;\n\t\t\toutput-high;\n\t\t};\n\t};\n};\n\n&cryptobam {\n\tstatus = \"okay\";\n};\n\n&blsp_dma {\n\tstatus = \"okay\";\n};\n\n&blsp1_spi1 { /* BLSP1 QUP1 */\n\tpinctrl-0 = <&spi_0_pins>;\n\tpinctrl-names = \"default\";\n\tstatus = \"okay\";\n\tcs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <24000000>;\n\t\tstatus = \"okay\";\n\t\tm25p,fast-read;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition0@0 {\n\t\t\t\tlabel = \"SBL1\";\n\t\t\t\treg = <0x00000000 0x00040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition1@40000 {\n\t\t\t\tlabel = \"MIBIB\";\n\t\t\t\treg = <0x00040000 0x00020000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition2@60000 {\n\t\t\t\tlabel = \"QSEE\";\n\t\t\t\treg = <0x00060000 0x00060000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition3@c0000 {\n\t\t\t\tlabel = \"CDT\";\n\t\t\t\treg = <0x000c0000 0x00010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition4@d0000 {\n\t\t\t\tlabel = \"DDRPARAMS\";\n\t\t\t\treg = <0x000d0000 0x00010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition5@e0000 {\n\t\t\t\tlabel = \"APPSBLENV\"; /* uboot env - empty */\n\t\t\t\treg = <0x000e0000 0x00010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition6@f0000 {\n\t\t\t\tlabel = \"urlader\"; /* APPSBL */\n\t\t\t\treg = <0x000f0000 0x0002dc000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition7@11dc00 {\n\t\t\t\t/* make a backup of this partition! */\n\t\t\t\tlabel = \"urlader_config\";\n\t\t\t\treg = <0x0011dc00 0x00002400>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition8@120000 {\n\t\t\t\tlabel = \"tffs1\";\n\t\t\t\treg = <0x00120000 0x00080000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition9@1a0000 {\n\t\t\t\tlabel = \"tffs2\";\n\t\t\t\treg = <0x001a0000 0x00080000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition10@220000 {\n\t\t\t\tlabel = \"uboot\";\n\t\t\t\treg = <0x00220000 0x00080000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition11@2A0000 {\n\t\t\t\tcompatible = \"denx,fit\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x002a0000 0x01c60000>;\n\t\t\t};\n\t\t\tpartition12@1f00000 {\n\t\t\t\tlabel = \"jffs2\";\n\t\t\t\treg = <0x01f00000 0x00100000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&blsp1_uart1 {\n\tpinctrl-0 = <&serial_pins>;\n\tpinctrl-names = \"default\";\n\tstatus = \"okay\";\n};\n\n&ethphy0 {\n\tgpio-controller;\n\t#gpio-cells = <2>;\n};\n\n&ethphy1 {\n\tgpio-controller;\n\t#gpio-cells = <2>;\n\n\tenable-usb-power {\n\t\tgpio-hog;\n\t\tline-name = \"enable USB3 power\";\n\t\tgpios = <1 GPIO_ACTIVE_HIGH>;\n\t\toutput-high;\n\t};\n};\n\n&ethphy2 {\n\tgpio-controller;\n\t#gpio-cells = <2>;\n};\n\n&ethphy3 {\n\tgpio-controller;\n\t#gpio-cells = <2>;\n};\n\n&usb3_ss_phy {\n\tstatus = \"okay\";\n};\n\n&usb3_hs_phy {\n\tstatus = \"okay\";\n};\n\n&usb2_hs_phy {\n\tstatus = \"okay\";\n};\n\n&wifi0 {\n\tstatus = \"okay\";\n\tqcom,ath10k-calibration-variant = \"AVM-FRITZBox-4040\";\n};\n\n&wifi1 {\n\tstatus = \"okay\";\n\tqcom,ath10k-calibration-variant = \"AVM-FRITZBox-4040\";\n};\n"
  },
  {
    "path": "target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-gl-ap1300.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qcom-ipq4019.dtsi\"\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/soc/qcom,tcsr.h>\n\n/ {\n\tmodel = \"GL.iNet GL-AP1300\";\n\tcompatible = \"glinet,gl-ap1300\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tmemory {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x80000000 0x10000000>;\n\t};\n\n\tchosen {\n\t\tbootargs-append = \" ubi.mtd=ubi root=/dev/ubiblock0_1\";\n\t};\n\n\tsoc {\n\t\trng@22000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tmdio@90000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tess-psgmii@98000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\ttcsr@1949000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1949000 0x100>;\n\t\t\tqcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;\n\t\t};\n\n\t\ttcsr@194b000 {\n\t\t\t/* select hostmode */\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x194b000 0x100>;\n\t\t\tqcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tess_tcsr@1953000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1953000 0x1000>;\n\t\t\tqcom,ess-interface-select = <TCSR_ESS_PSGMII>;\n\t\t};\n\n\t\ttcsr@1957000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1957000 0x100>;\n\t\t\tqcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;\n\t\t};\n\n\t\tusb2@60f8800 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tusb3@8af8800 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tcrypto@8e3a000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\twatchdog@b017000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tess-switch@c000000 {\n\t\t\tstatus = \"okay\";\n\t\t\tswitch_lan_bmp = <0x18>;\n\t\t\tswitch_wan_bmp = <0x20>;\n\t\t};\n\n\t\tedma@c080000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&tlmm 63 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\twan {\n\t\t\tlabel = \"green:wan\";\n\t\t\tgpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&blsp_dma {\n\tstatus = \"okay\";\n};\n\n&cryptobam {\n\tstatus = \"okay\";\n};\n\n&blsp1_spi1 {\n\tstatus = \"okay\";\n\n\tpinctrl-0 = <&spi0_pins>;\n\tpinctrl-names = \"default\";\n\tcs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>, <&tlmm 5 GPIO_ACTIVE_HIGH>;\n\n\tflash@0 {\n\t\tstatus = \"okay\";\n\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <24000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"SBL1\";\n\t\t\t\treg = <0x00000000 0x00040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"MIBIB\";\n\t\t\t\treg = <0x00040000 0x00020000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@60000 {\n\t\t\t\tlabel = \"QSEE\";\n\t\t\t\treg = <0x00060000 0x00060000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@c0000 {\n\t\t\t\tlabel = \"CDT\";\n\t\t\t\treg = <0x000c0000 0x00010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@d0000 {\n\t\t\t\tlabel = \"DDRPARAMS\";\n\t\t\t\treg = <0x000d0000 0x00010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@e0000 {\n\t\t\t\tlabel = \"APPSBLENV\"; /* uboot env*/\n\t\t\t\treg = <0x000e0000 0x00010000>;\n\t\t\t};\n\n\t\t\tpartition@f0000 {\n\t\t\t\tlabel = \"APPSBL\"; /* uboot */\n\t\t\t\treg = <0x000f0000 0x00080000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@170000 {\n\t\t\t\tlabel = \"ART\";\n\t\t\t\treg = <0x00170000 0x00010000>;\n\t\t\t\tread-only;\n\t\t\t\tcompatible = \"nvmem-cells\";\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\n\t\t\t\tprecal_art_1000: precal@1000 {\n\t\t\t\t\treg = <0x1000 0x2f20>;\n\t\t\t\t};\n\n\t\t\t\tprecal_art_5000: precal@5000 {\n\t\t\t\t\treg = <0x5000 0x2f20>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t};\n\n\tspi-nand@1 {\n\t\tstatus = \"okay\";\n\n\t\tcompatible = \"spi-nand\";\n\t\treg = <1>;\n\t\tspi-max-frequency = <24000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"ubi\";\n\t\t\t\treg = <0x00000000 0x08000000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&blsp1_uart1 {\n\tpinctrl-0 = <&serial_pins>;\n\tpinctrl-names = \"default\";\n\tstatus = \"okay\";\n};\n\n&tlmm {\n\tserial_pins: serial_pinmux {\n\t\tmux {\n\t\t\tpins = \"gpio60\", \"gpio61\";\n\t\t\tfunction = \"blsp_uart0\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tspi0_pins: spi0_pinmux {\n\t\tmux_spi {\n\t\t\tfunction = \"blsp_spi0\";\n\t\t\tpins = \"gpio55\", \"gpio56\", \"gpio57\";\n\t\t\tdrive-strength = <12>;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux_cs {\n\t\t\tfunction = \"gpio\";\n\t\t\tpins = \"gpio54\", \"gpio5\";\n\t\t\tdrive-strength = <2>;\n\t\t\tbias-disable;\n\t\t\toutput-high;\n\t\t};\n\t};\n};\n\n&usb2_hs_phy {\n\tstatus = \"okay\";\n};\n\n&usb3_hs_phy {\n\tstatus = \"okay\";\n};\n\n&usb3_ss_phy {\n\tstatus = \"okay\";\n};\n\n&wifi0 {\n\tstatus = \"okay\";\n\tnvmem-cell-names = \"pre-calibration\";\n\tnvmem-cells = <&precal_art_1000>;\n\tqcom,ath10k-calibration-variant = \"GL-AP1300\";\n};\n\n&wifi1 {\n\tstatus = \"okay\";\n\tnvmem-cell-names = \"pre-calibration\";\n\tnvmem-cells = <&precal_art_5000>;\n\tqcom,ath10k-calibration-variant = \"GL-AP1300\";\n};\n"
  },
  {
    "path": "target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-hap-ac2.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n/* Copyright (c) 2020, Robert Marko <robimarko@gmail.com> */\n\n#include \"qcom-ipq4019.dtsi\"\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/soc/qcom,tcsr.h>\n\n/ {\n\tmodel = \"MikroTik hAP ac2\";\n\tcompatible = \"mikrotik,hap-ac2\";\n\n\tmemory {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x80000000 0x08000000>;\n\t};\n\n\tchosen {\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\taliases {\n\t\tled-boot = &led_user;\n\t\tled-failsafe = &led_user;\n\t\tled-running = &led_user;\n\t\tled-upgrade = &led_user;\n\t};\n\n\tsoc {\n\t\trng@22000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tcounter@4a1000 {\n\t\t\tcompatible = \"qcom,qca-gcnt\";\n\t\t\treg = <0x4a1000 0x4>;\n\t\t};\n\n\t\ttcsr@1949000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1949000 0x100>;\n\t\t\tqcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;\n\t\t};\n\n\t\ttcsr@194b000 {\n\t\t\t/* select hostmode */\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x194b000 0x100>;\n\t\t\tqcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tess_tcsr@1953000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1953000 0x1000>;\n\t\t\tqcom,ess-interface-select = <TCSR_ESS_PSGMII>;\n\t\t};\n\n\t\ttcsr@1957000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1957000 0x100>;\n\t\t\tqcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;\n\t\t};\n\n\t\tusb3@8af8800 {\n\t\t\tstatus = \"okay\";\n\n\t\t\tdwc3@8a00000 {\n\t\t\t\tphys = <&usb3_hs_phy>;\n\t\t\t\tphy-names = \"usb2-phy\";\n\t\t\t};\n\t\t};\n\n\t\tcrypto@8e3a000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\twatchdog@b017000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tess-switch@c000000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tedma@c080000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&tlmm 63 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\tmode {\n\t\t\tlabel = \"mode\";\n\t\t\tgpios = <&tlmm 5 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RFKILL>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tpower {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"keep\";\n\t\t\tpanic-indicator;\n\t\t};\n\n\t\tled_user: user {\n\t\t\tlabel = \"green:user\";\n\t\t\tgpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&tlmm {\n\tserial_pins: serial_pinmux {\n\t\tmux {\n\t\t\tpins = \"gpio60\", \"gpio61\";\n\t\t\tfunction = \"blsp_uart0\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tspi_0_pins: spi_0_pinmux {\n\t\tpin {\n\t\t\tfunction = \"blsp_spi0\";\n\t\t\tpins = \"gpio55\", \"gpio56\", \"gpio57\";\n\t\t\tdrive-strength = <2>;\n\t\t\tbias-disable;\n\t\t};\n\t\tpin_cs {\n\t\t\tfunction = \"gpio\";\n\t\t\tpins = \"gpio54\";\n\t\t\tdrive-strength = <2>;\n\t\t\tbias-disable;\n\t\t\toutput-high;\n\t\t};\n\t};\n\n\tenable-usb-power {\n\t\tgpio-hog;\n\t\tgpios = <2 GPIO_ACTIVE_HIGH>;\n\t\toutput-high;\n\t\tline-name = \"enable USB power\";\n\t};\n};\n\n&blsp_dma {\n\tstatus = \"okay\";\n};\n\n&blsp1_spi1 {\n\tstatus = \"okay\";\n\n\tpinctrl-0 = <&spi_0_pins>;\n\tpinctrl-names = \"default\";\n\tcs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;\n\n\tflash@0 {\n\t\treg = <0>;\n\t\tcompatible = \"jedec,spi-nor\";\n\t\tspi-max-frequency = <40000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"Qualcomm\";\n\t\t\t\treg = <0x0 0x80000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@80000 {\n\t\t\t\tcompatible = \"mikrotik,routerboot-partitions\";\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\t\t\t\tlabel = \"RouterBoot\";\n\t\t\t\treg = <0x80000 0x80000>;\n\t\t\t\tread-only;\n\n\t\t\t\thard_config {\n\t\t\t\t\tread-only;\n\t\t\t\t\tsize = <0x2000>;\n\t\t\t\t};\n\n\t\t\t\tdtb_config {\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\tsoft_config {\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tpartition@100000 {\n\t\t\t\tcompatible = \"mikrotik,minor\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x100000 0xf00000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&blsp1_uart1 {\n\tstatus = \"okay\";\n\n\tpinctrl-0 = <&serial_pins>;\n\tpinctrl-names = \"default\";\n};\n\n&cryptobam {\n\tstatus = \"okay\";\n};\n\n&usb3_hs_phy {\n\tstatus = \"okay\";\n};\n\n&mdio {\n\tstatus = \"okay\";\n};\n\n&ethphy0 {\n\tqcom,single-led-1000;\n\tqcom,single-led-100;\n\tqcom,single-led-10;\n};\n\n&ethphy1 {\n\tqcom,single-led-1000;\n\tqcom,single-led-100;\n\tqcom,single-led-10;\n};\n\n&ethphy2 {\n\tqcom,single-led-1000;\n\tqcom,single-led-100;\n\tqcom,single-led-10;\n};\n\n&ethphy3 {\n\tqcom,single-led-1000;\n\tqcom,single-led-100;\n\tqcom,single-led-10;\n};\n\n&ethphy4 {\n\tqcom,single-led-1000;\n\tqcom,single-led-100;\n\tqcom,single-led-10;\n};\n\n&wifi0 {\n\tstatus = \"okay\";\n\n\tqcom,ath10k-calibration-variant = \"MikroTik-hAP-ac2\";\n};\n\n&wifi1 {\n\tstatus = \"okay\";\n\n\tqcom,ath10k-calibration-variant = \"MikroTik-hAP-ac2\";\n};\n"
  },
  {
    "path": "target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-jalapeno.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n// Copyright (c) 2018, Robert Marko <robimarko@gmail.com>\n\n#include \"qcom-ipq4018-jalapeno.dtsi\"\n\n/ {\n\tmodel = \"8devices Jalapeno\";\n\tcompatible = \"8dev,jalapeno\";\n};\n"
  },
  {
    "path": "target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-jalapeno.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n// Copyright (c) 2018, Robert Marko <robimarko@gmail.com>\n\n#include \"qcom-ipq4019.dtsi\"\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/soc/qcom,tcsr.h>\n\n/ {\n\tsoc {\n\t\trng@22000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tmdio@90000 {\n\t\t\tstatus = \"okay\";\n\n\t\t\tpinctrl-0 = <&mdio_pins>;\n\t\t\tpinctrl-names = \"default\";\n\t\t};\n\n\t\tess-psgmii@98000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tcounter@4a1000 {\n\t\t\tcompatible = \"qcom,qca-gcnt\";\n\t\t\treg = <0x4a1000 0x4>;\n\t\t};\n\n\t\ttcsr@1949000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1949000 0x100>;\n\t\t\tqcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;\n\t\t};\n\n\t\ttcsr@194b000 {\n\t\t\tstatus = \"okay\";\n\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x194b000 0x100>;\n\t\t\tqcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;\n\t\t};\n\n\t\tess_tcsr@1953000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1953000 0x1000>;\n\t\t\tqcom,ess-interface-select = <TCSR_ESS_PSGMII>;\n\t\t};\n\n\t\ttcsr@1957000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1957000 0x100>;\n\t\t\tqcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;\n\t\t};\n\n\t\tusb2: usb2@60f8800 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tusb3: usb3@8af8800 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tcrypto@8e3a000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\twatchdog@b017000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tess-switch@c000000 {\n\t\t\tstatus = \"okay\";\n\n\t\t\tswitch_lan_bmp = <0x10>; /* lan port bitmap */\n\t\t};\n\n\t\tedma@c080000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\t};\n};\n\n&tlmm {\n\tmdio_pins: mdio_pinmux {\n\t\tpinmux_1 {\n\t\t\tpins = \"gpio53\";\n\t\t\tfunction = \"mdio\";\n\t\t};\n\n\t\tpinmux_2 {\n\t\t\tpins = \"gpio52\";\n\t\t\tfunction = \"mdc\";\n\t\t};\n\n\t\tpinconf {\n\t\t\tpins = \"gpio52\", \"gpio53\";\n\t\t\tbias-pull-up;\n\t\t};\n\t};\n\n\tserial_pins: serial_pinmux {\n\t\tmux {\n\t\t\tpins = \"gpio60\", \"gpio61\";\n\t\t\tfunction = \"blsp_uart0\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tspi_0_pins: spi_0_pinmux {\n\t\tpin {\n\t\t\tfunction = \"blsp_spi0\";\n\t\t\tpins = \"gpio55\", \"gpio56\", \"gpio57\";\n\t\t\tdrive-strength = <2>;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tpin_cs {\n\t\t\tfunction = \"gpio\";\n\t\t\tpins = \"gpio54\", \"gpio59\";\n\t\t\tdrive-strength = <2>;\n\t\t\tbias-disable;\n\t\t\toutput-high;\n\t\t};\n\t};\n};\n\n&blsp_dma {\n\tstatus = \"okay\";\n};\n\n&blsp1_spi1 {\n\tstatus = \"okay\";\n\n\tpinctrl-0 = <&spi_0_pins>;\n\tpinctrl-names = \"default\";\n\tcs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>, <&tlmm 59 GPIO_ACTIVE_HIGH>;\n\n\tflash@0 {\n\t\tstatus = \"okay\";\n\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <24000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"SBL1\";\n\t\t\t\treg = <0x00000000 0x00040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"MIBIB\";\n\t\t\t\treg = <0x00040000 0x00020000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@60000 {\n\t\t\t\tlabel = \"QSEE\";\n\t\t\t\treg = <0x00060000 0x00060000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@c0000 {\n\t\t\t\tlabel = \"CDT\";\n\t\t\t\treg = <0x000c0000 0x00010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@d0000 {\n\t\t\t\tlabel = \"DDRPARAMS\";\n\t\t\t\treg = <0x000d0000 0x00010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@e0000 {\n\t\t\t\tlabel = \"APPSBLENV\"; /* uboot env*/\n\t\t\t\treg = <0x000e0000 0x00010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@f0000 {\n\t\t\t\tlabel = \"APPSBL\"; /* uboot */\n\t\t\t\treg = <0x000f0000 0x00080000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@170000 {\n\t\t\t\tlabel = \"ART\";\n\t\t\t\treg = <0x00170000 0x00010000>;\n\t\t\t\tread-only;\n\t\t\t\tcompatible = \"nvmem-cells\";\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\n\t\t\t\tprecal_art_1000: precal@1000 {\n\t\t\t\t\treg = <0x1000 0x2f20>;\n\t\t\t\t};\n\n\t\t\t\tprecal_art_5000: precal@5000 {\n\t\t\t\t\treg = <0x5000 0x2f20>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t};\n\n\tspi-nand@1 {\n\t\tstatus = \"okay\";\n\n\t\tcompatible = \"spi-nand\";\n\t\treg = <1>;\n\t\tspi-max-frequency = <24000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"ubi\";\n\t\t\t\treg = <0x00000000 0x08000000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&blsp1_uart1 {\n\tstatus = \"okay\";\n\n\tpinctrl-0 = <&serial_pins>;\n\tpinctrl-names = \"default\";\n};\n\n&cryptobam {\n\tstatus = \"okay\";\n};\n\n&gmac0 {\n\tqcom,poll_required = <1>;\n\tqcom,poll_required_dynamic = <1>;\n\tqcom,phy_mdio_addr = <3>;\n\tvlan_tag = <1 0x10>;\n};\n\n&gmac1 {\n\tqcom,poll_required = <1>;\n\tqcom,poll_required_dynamic = <1>;\n\tqcom,phy_mdio_addr = <4>;\n\tvlan_tag = <2 0x20>;\n};\n\n&wifi0 {\n\tstatus = \"okay\";\n\tnvmem-cell-names = \"pre-calibration\";\n\tnvmem-cells = <&precal_art_1000>;\n\tqcom,ath10k-calibration-variant = \"8devices-Jalapeno\";\n};\n\n&wifi1 {\n\tstatus = \"okay\";\n\tnvmem-cell-names = \"pre-calibration\";\n\tnvmem-cells = <&precal_art_5000>;\n\tqcom,ath10k-calibration-variant = \"8devices-Jalapeno\";\n};\n\n&usb3_ss_phy {\n\tstatus = \"okay\";\n};\n\n&usb3_hs_phy {\n\tstatus = \"okay\";\n};\n\n&usb2_hs_phy {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-magic-2-wifi-next.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qcom-ipq4019.dtsi\"\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"devolo Magic 2 WiFi next\";\n\tcompatible = \"devolo,magic-2-wifi-next\";\n\n\tmemory {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x80000000 0x10000000>;\n\t};\n\n\tsoc {\n\t\trng@22000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tmdio@90000 {\n\t\t\tstatus = \"okay\";\n\t\t\tpinctrl-0 = <&mdio_pins>;\n\t\t\tpinctrl-names = \"default\";\n\t\t\treset-gpios = <&tlmm 59 GPIO_ACTIVE_LOW>;\n\t\t\treset-delay-us = <2000>;\n\n\t\t\t/delete-node/ ethernet-phy@0;\n\t\t\t/delete-node/ ethernet-phy@1;\n\t\t};\n\n\t\tess-psgmii@98000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tcrypto@8e3a000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\twatchdog@b017000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tess-switch@c000000 {\n\t\t\tstatus = \"okay\";\n\t\t\tswitch_lan_bmp = <0x3e>;\n\t\t\tswitch_wan_bmp = <0x0>;\n\t\t};\n\n\t\tedma@c080000 {\n\t\t\tstatus = \"okay\";\n\t\t\tqcom,num_gmac = <3>;\n\n\t\t\tgmac0 {\n\t\t\t\tqcom,phy_mdio_addr = <3>;\n\t\t\t\tqcom,poll_required = <1>;\n\t\t\t\t/delete-property/ qcom,forced_speed;\n\t\t\t\t/delete-property/ qcom,forced_duplex;\n\t\t\t\tvlan_tag = <1 0x10>;\n\t\t\t};\n\n\t\t\tgmac1 {\n\t\t\t\tqcom,phy_mdio_addr = <2>;\n\t\t\t\tqcom,poll_required = <1>;\n\t\t\t\t/delete-property/ qcom,forced_speed;\n\t\t\t\t/delete-property/ qcom,forced_duplex;\n\t\t\t\tvlan_tag = <1 0x08>;\n\t\t\t};\n\n\t\t\tgmac2 {\n\t\t\t\tlocal-mac-address = [00 00 00 00 00 00];\n\t\t\t\tqcom,phy_mdio_addr = <4>;\n\t\t\t\tqcom,poll_required = <1>;\n\t\t\t\t/delete-property/ qcom,forced_speed;\n\t\t\t\t/delete-property/ qcom,forced_duplex;\n\t\t\t\tvlan_tag = <1 0x20>;\n\t\t\t};\n\t\t};\n\n\t\tgpio_export {\n\t\t\tcompatible = \"gpio-export\";\n\t\t\t#size-cells = <0>;\n\n\t\t\tplc {\n\t\t\t\tgpio-export,name = \"plc-enable\";\n\t\t\t\tgpio-export,output = <1>;\n\t\t\t\tgpios = <&tlmm 63 GPIO_ACTIVE_HIGH>;\n\t\t\t};\n\t\t};\n\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\twlan {\n\t\t\tlabel = \"WLAN\";\n\t\t\tgpios = <&tlmm 5 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"Reset\";\n\t\t\tgpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tstatus_dlan {\n\t\t\tlabel = \"white:dlan\";\n\t\t\tgpios = <&tlmm 4 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"keep\";\n\t\t};\n\n\t\tstatus_wlan {\n\t\t\tlabel = \"white:wlan\";\n\t\t\tgpios = <&tlmm 58 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"keep\";\n\t\t};\n\n\t\terror_dlan {\n\t\t\tlabel = \"red:dlan\";\n\t\t\tgpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"keep\";\n\t\t};\n\t};\n};\n\n&tlmm {\n\tspi_0_pins: spi_0_pinmux {\n\t\tmux {\n\t\t\tfunction = \"blsp_spi0\";\n\t\t\tpins = \"gpio55\", \"gpio56\", \"gpio57\";\n\t\t\tdrive-strength = <12>;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux_cs {\n\t\t\tfunction = \"gpio\";\n\t\t\tpins = \"gpio54\";\n\t\t\tdrive-strength = <2>;\n\t\t\tbias-disable;\n\t\t\toutput-high;\n\t\t};\n\t};\n\n\tmdio_pins: mdio_pinmux {\n\t\tmux_1 {\n\t\t\tpins = \"gpio53\";\n\t\t\tfunction = \"mdio\";\n\t\t\tbias-pull-up;\n\t\t};\n\t\tmux_2 {\n\t\t\tpins = \"gpio52\";\n\t\t\tfunction = \"mdc\";\n\t\t\tbias-pull-up;\n\t\t};\n\t};\n\n\tserial_pins: serial_pinmux {\n\t\tmux {\n\t\t\tpins = \"gpio61\", \"gpio60\";\n\t\t\tfunction = \"blsp_uart0\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tbutton_pins: button_pinmux {\n\t\tmux {\n\t\t\tfunction = \"gpio\";\n\t\t\tpins = \"gpio0\", \"gpio5\";\n\t\t\tbias-disable;\n\t\t\tinput;\n\t\t};\n\t};\n};\n\n&cryptobam {\n\tstatus = \"okay\";\n};\n\n&blsp_dma {\n\tstatus = \"okay\";\n};\n\n&blsp1_uart1 {\n\tpinctrl-0 = <&serial_pins>;\n\tpinctrl-names = \"default\";\n\tstatus = \"okay\";\n};\n\n&wifi0 {\n\tstatus = \"okay\";\n\tqcom,ath10k-calibration-variant = \"devolo,magic-2-wifi-next\";\n};\n\n&wifi1 {\n\tstatus = \"okay\";\n\tqcom,ath10k-calibration-variant = \"devolo,magic-2-wifi-next\";\n};\n\n&blsp1_spi1 {\n\tpinctrl-0 = <&spi_0_pins>;\n\tpinctrl-names = \"default\";\n\tstatus = \"okay\";\n\tcs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tlinux,modalias = \"n25q128a11\";\n\t\tspi-max-frequency = <24000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"SBL1\";\n\t\t\t\treg = <0x00000000 0x00040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"MIBIB\";\n\t\t\t\treg = <0x00040000 0x00020000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@60000 {\n\t\t\t\tlabel = \"QSEE\";\n\t\t\t\treg = <0x00060000 0x00060000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@c0000 {\n\t\t\t\tlabel = \"CDT\";\n\t\t\t\treg = <0x000c0000 0x00010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@d0000 {\n\t\t\t\tlabel = \"DDRPARAMS\";\n\t\t\t\treg = <0x000d0000 0x00010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@e0000 {\n\t\t\t\tlabel = \"APPSBLENV\"; /* uboot env*/\n\t\t\t\treg = <0x000e0000 0x00010000>;\n\t\t\t};\n\t\t\tpartition@f0000 {\n\t\t\t\tlabel = \"APPSBL\"; /* uboot */\n\t\t\t\treg = <0x000f0000 0x00080000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@170000 {\n\t\t\t\tlabel = \"ART\";\n\t\t\t\treg = <0x00170000 0x00010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tfirmware@180000 {\n\t\t\t\tcompatible = \"denx,fit\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x00180000 0x01a80000>;\n\t\t\t};\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-meshpoint-one.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n/* Copyright (c) 2019, CRISIS INNOVATION LAB d.o.o.\n * Author: Robert Marko <robert@meshpoint.me>\n */\n\n#include \"qcom-ipq4018-jalapeno.dtsi\"\n\n/ {\n\tmodel = \"Crisis Innovation Lab MeshPoint.One\";\n\tcompatible = \"cilab,meshpoint-one\";\n\n\taliases {\n\t\tled-boot = &led_status;\n\t\tled-failsafe = &led_status;\n\t\tled-running = &led_status;\n\t\tled-upgrade = &led_status;\n\t};\n\n\tsoc {\n\t\ti2c-gpio {\n\t\t\tstatus = \"okay\";\n\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\n\t\t\tcompatible = \"i2c-gpio\";\n\t\t\tgpios = <&tlmm 0 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN) /* sda */\n\t\t\t\t\t &tlmm 4 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN) /* scl */\n\t\t\t\t\t>;\n\n\t\t\tbme280@76 {\n\t\t\t\tstatus = \"okay\";\n\n\t\t\t\tcompatible = \"bosch,bme280\";\n\t\t\t\treg = <0x76>;\n\t\t\t};\n\n\t\t\tpcf2129@51 {\n\t\t\t\tstatus = \"okay\";\n\n\t\t\t\tcompatible = \"nxp,pcf2129\";\n\t\t\t\treg = <0x51>;\n\t\t\t};\n\n\t\t\tina230@40 {\n\t\t\t\tstatus = \"okay\";\n\n\t\t\t\tcompatible = \"ti,ina230\";\n\t\t\t\treg = <0x40>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\n\t\t\tina230@44 {\n\t\t\t\tstatus = \"okay\";\n\n\t\t\t\tcompatible = \"ti,ina230\";\n\t\t\t\treg = <0x44>;\n\t\t\t\tshunt-resistor = <2000>;\n\t\t\t};\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&tlmm 5 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART >;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_status: status {\n\t\t\tlabel = \"blue:status\";\n\t\t\tgpios = <&tlmm 63 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-nbg6617.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qcom-ipq4019.dtsi\"\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/input/linux-event-codes.h>\n#include <dt-bindings/soc/qcom,tcsr.h>\n\n/ {\n\tmodel = \"ZyXEL NBG6617\";\n\tcompatible = \"zyxel,nbg6617\";\n\n\tchosen {\n\t\t/*\n\t\t * the vendor u-boot adds root and mtdparts cmdline parameters\n\t\t * which we don't want... but we have to overwrite them or else\n\t\t * the kernel will take them at face value.\n\t\t */\n\t\tbootargs-append = \" mtdparts= root=31:13\";\n\t};\n\n\taliases {\n\t\tled-boot = &power;\n\t\tled-failsafe = &power;\n\t\tled-running = &power;\n\t\tled-upgrade = &power;\n\t};\n\n\tsoc {\n\t\trng@22000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tmdio@90000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tess-psgmii@98000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\ttcsr@1949000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1949000 0x100>;\n\t\t\tqcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;\n\t\t};\n\n\t\ttcsr@194b000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x194b000 0x100>;\n\t\t\tqcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;\n\t\t};\n\n\t\tess_tcsr@1953000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1953000 0x1000>;\n\t\t\tqcom,ess-interface-select = <TCSR_ESS_PSGMII>;\n\t\t};\n\n\t\ttcsr@1957000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1957000 0x100>;\n\t\t\tqcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;\n\t\t};\n\n\t\tusb2@60f8800 {\n\t\t\tstatus = \"okay\";\n\n\t\t\tdwc3@6000000 {\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\n\t\t\t\tusb2_port1: port@1 {\n\t\t\t\t\treg = <1>;\n\t\t\t\t\t#trigger-source-cells = <0>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tusb3@8af8800 {\n\t\t\tstatus = \"okay\";\n\n\t\t\tdwc3@8a00000 {\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\n\t\t\t\tusb3_port1: port@1 {\n\t\t\t\t\treg = <1>;\n\t\t\t\t\t#trigger-source-cells = <0>;\n\t\t\t\t};\n\n\t\t\t\tusb3_port2: port@2 {\n\t\t\t\t\treg = <2>;\n\t\t\t\t\t#trigger-source-cells = <0>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tcrypto@8e3a000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\twatchdog@b017000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tess-switch@c000000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tedma@c080000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\twlan {\n\t\t\tlabel = \"wlan\";\n\t\t\tgpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = <KEY_RFKILL>;\n\t\t\tlinux,input-type = <EV_SW>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&tlmm 63 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&tlmm 4 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tpinctrl-0 = <&led_pins>;\n\t\tpinctrl-names = \"default\";\n\n\t\tpower: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tusb {\n\t\t\tlabel = \"green:usb\";\n\t\t\tgpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;\n\t\t\ttrigger-sources = <&usb2_port1>, <&usb3_port1>, <&usb3_port2>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\n\t\twlan2g {\n\t\t\tlabel = \"green:wlan2g\";\n\t\t\tgpios = <&tlmm 58 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\twlan5g {\n\t\t\tlabel = \"green:wlan5g\";\n\t\t\tgpios = <&tlmm 5 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&tlmm 1 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&tlmm {\n\tserial_pins: serial_pinmux {\n\t\tmux {\n\t\t\tpins = \"gpio60\", \"gpio61\";\n\t\t\tfunction = \"blsp_uart0\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\tspi_0_pins: spi_0_pinmux {\n\t\tmux {\n\t\t\tfunction = \"blsp_spi0\";\n\t\t\tpins = \"gpio55\", \"gpio56\", \"gpio57\";\n\t\t\tdrive-strength = <12>;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux_cs {\n\t\t\tfunction = \"gpio\";\n\t\t\tpins = \"gpio54\";\n\t\t\tdrive-strength = <2>;\n\t\t\tbias-disable;\n\t\t\toutput-low;\n\t\t};\n\t};\n\tled_pins: led_pinmux {\n\t\tmux {\n\t\t\tpins = \"gpio0\", \"gpio1\", \"gpio3\", \"gpio5\", \"gpio58\";\n\t\t\tdrive-strength = <0x8>;\n\t\t\tbias-disable;\n\t\t\toutput-low;\n\t\t};\n\t};\n};\n\n&blsp1_spi1 { /* BLSP1 QUP1 */\n\tpinctrl-0 = <&spi_0_pins>;\n\tpinctrl-names = \"default\";\n\tstatus = \"okay\";\n\tcs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <50000000>;\n\t\tstatus = \"okay\";\n\t\tm25p,fast-read;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition0@0 {\n\t\t\t\tlabel = \"SBL1\";\n\t\t\t\treg = <0x00000000 0x00040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition1@40000 {\n\t\t\t\tlabel = \"MIBIB\";\n\t\t\t\treg = <0x00040000 0x00020000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition2@60000 {\n\t\t\t\tlabel = \"QSEE\";\n\t\t\t\treg = <0x00060000 0x00060000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition3@c0000 {\n\t\t\t\tlabel = \"CDT\";\n\t\t\t\treg = <0x000c0000 0x00010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition4@d0000 {\n\t\t\t\tlabel = \"DDRPARAMS\";\n\t\t\t\treg = <0x000d0000 0x00010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition5@e0000 {\n\t\t\t\tlabel = \"APPSBL\"; /* u-boot */\n\t\t\t\treg = <0x000e0000 0x00080000>;\n\t\t\t\t/* U-Boot Standalone App \"zloader\" is located at 0x64000 */\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition6@160000 {\n\t\t\t\tlabel = \"APPSBLENV\"; /* u-boot env */\n\t\t\t\treg = <0x00160000 0x00010000>;\n\t\t\t};\n\t\t\tpartition7@170000 {\n\t\t\t\t/* make a backup of this partition! */\n\t\t\t\tlabel = \"ART\";\n\t\t\t\treg = <0x00170000 0x00010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition8@180000 {\n\t\t\t\tlabel = \"kernel\";\n\t\t\t\treg = <0x00180000 0x00400000>;\n\t\t\t};\n\t\t\tpartition9@580000 {\n\t\t\t\tlabel = \"dualflag\";\n\t\t\t\treg = <0x00580000 0x00010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition10@590000 {\n\t\t\t\tlabel = \"header\";\n\t\t\t\treg = <0x00590000 0x00010000>;\n\t\t\t};\n\t\t\tpartition11@5a0000 {\n\t\t\t\tlabel = \"romd\";\n\t\t\t\treg = <0x005a0000 0x00100000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition12@6a0000 {\n\t\t\t\tlabel = \"not_root_data\";\n\t\t\t\t/*\n\t\t\t\t * for some strange reason, someone at ZyXEL\n\t\t\t\t * had the \"great\" idea to put the rootfs_data\n\t\t\t\t * in front of rootfs... Don't do that!\n\t\t\t\t * As a result this one, full MebiByte remains\n\t\t\t\t * unused.\n\t\t\t\t */\n\t\t\t\treg = <0x006a0000 0x00100000>;\n\t\t\t};\n\t\t\tpartition13@7a0000 {\n\t\t\t\tlabel = \"rootfs\";\n\t\t\t\treg = <0x007a0000 0x01860000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&blsp1_uart1 {\n\tpinctrl-0 = <&serial_pins>;\n\tpinctrl-names = \"default\";\n\tstatus = \"okay\";\n};\n\n&cryptobam {\n\tstatus = \"okay\";\n};\n\n&blsp_dma {\n\tstatus = \"okay\";\n};\n\n&wifi0 {\n\tstatus = \"okay\";\n\tqcom,ath10k-calibration-variant = \"ZyXEL-NBG6617\";\n};\n\n&wifi1 {\n\tstatus = \"okay\";\n\tqcom,ath10k-calibration-variant = \"ZyXEL-NBG6617\";\n};\n\n&usb3_ss_phy {\n\tstatus = \"okay\";\n};\n\n&usb3_hs_phy {\n\tstatus = \"okay\";\n};\n\n&usb2_hs_phy {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-pa1200.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n/* Copyright (c) 2017-2020, Sven Eckelmann <sven@narfation.org>\n * Copyright (c) 2018, Marek Lindner <marek.lindner@kaiwoo.ai>\n */\n\n#include \"qcom-ipq4019.dtsi\"\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/soc/qcom,tcsr.h>\n\n/ {\n\tmodel = \"Plasma Cloud PA1200\";\n\tcompatible = \"plasmacloud,pa1200\";\n\n\tsoc {\n\t\trng@22000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tmdio@90000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tess-psgmii@98000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\ttcsr@194b000 {\n\t\t\t/* select hostmode */\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x194b000 0x100>;\n\t\t\tqcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\ttcsr@1949000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1949000 0x100>;\n\t\t\tqcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;\n\t\t};\n\n\t\tess_tcsr@1953000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1953000 0x1000>;\n\t\t\tqcom,ess-interface-select = <TCSR_ESS_PSGMII>;\n\t\t};\n\n\t\ttcsr@1957000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1957000 0x100>;\n\t\t\tqcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;\n\t\t};\n\n\t\tusb2: usb2@60f8800 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tcrypto@8e3a000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\twatchdog@b017000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tess-switch@c000000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tedma@c080000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&tlmm 59 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\taliases {\n\t\tled-boot = &led_status_purple;\n\t\tled-failsafe = &led_status_yellow;\n\t\tled-running = &led_status_cyan;\n\t\tled-upgrade = &led_status_yellow;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_status_cyan: status_cyan {\n\t\t\tlabel = \"cyan:status\";\n\t\t\tgpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tled_status_purple: status_purple {\n\t\t\tlabel = \"purple:status\";\n\t\t\tgpios = <&tlmm 1 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tled_status_yellow: status_yellow {\n\t\t\tlabel = \"yellow:status\";\n\t\t\tgpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n\n};\n\n&tlmm {\n\tserial_pins: serial_pinmux {\n\t\tmux {\n\t\t\tpins = \"gpio60\", \"gpio61\";\n\t\t\tfunction = \"blsp_uart0\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tspi_0_pins: spi_0_pinmux {\n\t\tpin {\n\t\t\tfunction = \"blsp_spi0\";\n\t\t\tpins = \"gpio55\", \"gpio56\", \"gpio57\";\n\t\t\tdrive-strength = <12>;\n\t\t\tbias-disable;\n\t\t};\n\t\tpin_cs {\n\t\t\tfunction = \"gpio\";\n\t\t\tpins = \"gpio54\";\n\t\t\tdrive-strength = <2>;\n\t\t\tbias-disable;\n\t\t\toutput-high;\n\t\t};\n\t};\n};\n\n&blsp_dma {\n\tstatus = \"okay\";\n};\n\n&blsp1_spi1 {\n\tpinctrl-0 = <&spi_0_pins>;\n\tpinctrl-names = \"default\";\n\tstatus = \"okay\";\n\tcs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;\n\n\tflash@0 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <24000000>;\n\t\t/* partitions are passed via bootloader */\n\t};\n};\n\n&blsp1_uart1 {\n\tpinctrl-0 = <&serial_pins>;\n\tpinctrl-names = \"default\";\n\tstatus = \"okay\";\n};\n\n&cryptobam {\n\tstatus = \"okay\";\n};\n\n&gmac0 {\n\tqcom,phy_mdio_addr = <4>;\n\tqcom,poll_required = <1>;\n\tqcom,forced_speed = <1000>;\n\tqcom,forced_duplex = <1>;\n\tvlan_tag = <2 0x20>;\n};\n\n&gmac1 {\n\tqcom,phy_mdio_addr = <3>;\n\tqcom,poll_required = <1>;\n\tqcom,forced_speed = <1000>;\n\tqcom,forced_duplex = <1>;\n\tvlan_tag = <1 0x10>;\n};\n\n&usb2_hs_phy {\n\tstatus = \"okay\";\n};\n\n&wifi0 {\n\tstatus = \"okay\";\n\tqcom,ath10k-calibration-variant = \"PlasmaCloud-PA1200\";\n};\n\n&wifi1 {\n\tstatus = \"okay\";\n\tqcom,ath10k-calibration-variant = \"PlasmaCloud-PA1200\";\n};\n"
  },
  {
    "path": "target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-rt-ac58u.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qcom-ipq4019.dtsi\"\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/soc/qcom,tcsr.h>\n\n/ {\n\tmodel = \"ASUS RT-AC58U\";\n\tcompatible = \"asus,rt-ac58u\";\n\n\tmemory {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x80000000 0x8000000>;\n\t};\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tsoc {\n\t\trng@22000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tmdio@90000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tess-psgmii@98000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\ttcsr@1949000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1949000 0x100>;\n\t\t\tqcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;\n\t\t};\n\n\t\ttcsr@194b000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x194b000 0x100>;\n\t\t\tqcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;\n\t\t};\n\n\t\tess_tcsr@1953000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1953000 0x1000>;\n\t\t\tqcom,ess-interface-select = <TCSR_ESS_PSGMII>;\n\t\t};\n\n\t\ttcsr@1957000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1957000 0x100>;\n\t\t\tqcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;\n\t\t};\n\n\t\tusb3@8af8800 {\n\t\t\tstatus = \"okay\";\n\n\t\t\tdwc3@8a00000 {\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\n\t\t\t\tusb3_port1: port@1 {\n\t\t\t\t\treg = <1>;\n\t\t\t\t\t#trigger-source-cells = <0>;\n\t\t\t\t};\n\n\t\t\t\tusb3_port2: port@2 {\n\t\t\t\t\treg = <2>;\n\t\t\t\t\t#trigger-source-cells = <0>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tcrypto@8e3a000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\twatchdog@b017000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tess-switch@c000000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tedma@c080000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&tlmm 4 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&tlmm 63 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: status {\n\t\t\tlabel = \"blue:status\";\n\t\t\tgpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\twan {\n\t\t\tlabel = \"blue:wan\";\n\t\t\tgpios = <&tlmm 1 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\twlan2G {\n\t\t\tlabel = \"blue:wlan2G\";\n\t\t\tgpios = <&tlmm 58 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\twlan5G {\n\t\t\tlabel = \"blue:wlan5G\";\n\t\t\tgpios = <&tlmm 5 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\n\t\tusb {\n\t\t\tlabel = \"blue:usb\";\n\t\t\tgpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;\n\t\t\ttrigger-sources = <&usb3_port1>, <&usb3_port2>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\n\t\tlan {\n\t\t\tlabel = \"blue:lan\";\n\t\t\tgpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&cryptobam {\n\tstatus = \"okay\";\n};\n\n&blsp_dma {\n\tstatus = \"okay\";\n};\n\n&tlmm {\n\tserial_pins: serial_pinmux {\n\t\tmux {\n\t\t\tpins = \"gpio60\", \"gpio61\";\n\t\t\tfunction = \"blsp_uart0\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tspi_0_pins: spi_0_pinmux {\n\t\tmux {\n\t\t\tfunction = \"blsp_spi0\";\n\t\t\tpins = \"gpio55\", \"gpio56\", \"gpio57\";\n\t\t\tdrive-strength = <12>;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tmux_cs {\n\t\t\tfunction = \"gpio\";\n\t\t\tpins = \"gpio54\", \"gpio59\";\n\t\t\tdrive-strength = <2>;\n\t\t\tbias-disable;\n\t\t\toutput-high;\n\t\t};\n\t};\n};\n\n&blsp1_spi1 { /* BLSP1 QUP1 */\n\tpinctrl-0 = <&spi_0_pins>;\n\tpinctrl-names = \"default\";\n\tstatus = \"okay\";\n\tcs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>,\n\t\t   <&tlmm 59 GPIO_ACTIVE_HIGH>;\n\n\tflash@0 {\n\t\t/*\n\t\t * U-boot looks for \"n25q128a11\" node,\n\t\t * if we don't have it, it will spit out the following warning:\n\t\t * \"ipq: fdt fixup unable to find compatible node\".\n\t\t */\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tlinux,modalias = \"m25p80\", \"mx25l1606e\", \"n25q128a11\";\n\t\tspi-max-frequency = <30000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"SBL1\";\n\t\t\t\treg = <0x00000000 0x00040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"MIBIB\";\n\t\t\t\treg = <0x00040000 0x00020000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@60000 {\n\t\t\t\tlabel = \"QSEE\";\n\t\t\t\treg = <0x00060000 0x00060000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@c0000 {\n\t\t\t\tlabel = \"CDT\";\n\t\t\t\treg = <0x000c0000 0x00010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@d0000 {\n\t\t\t\tlabel = \"DDRPARAMS\";\n\t\t\t\treg = <0x000d0000 0x00010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@e0000 {\n\t\t\t\tlabel = \"APPSBLENV\"; /* uboot env*/\n\t\t\t\treg = <0x000e0000 0x00010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@f0000 {\n\t\t\t\tlabel = \"APPSBL\"; /* uboot */\n\t\t\t\treg = <0x000f0000 0x00080000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@170000 {\n\t\t\t\tlabel = \"ART\";\n\t\t\t\treg = <0x00170000 0x00010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\t/* 0x00180000 - 0x00200000 unused */\n\t\t};\n\t};\n\n\tspi-nand@1 {\n\t\tcompatible = \"spi-nand\";\n\t\treg = <1>;\n\t\tspi-max-frequency = <30000000>;\n\n\t\t/*\n\t\t * U-boot looks for \"spinand,mt29f\" node,\n\t\t * if we don't have it, it will spit out the following warning:\n\t\t * \"ipq: fdt fixup unable to find compatible node\".\n\t\t */\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"ubi\";\n\t\t\t\treg = <0x00000000 0x08000000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&blsp1_uart1 {\n\tpinctrl-0 = <&serial_pins>;\n\tpinctrl-names = \"default\";\n\tstatus = \"okay\";\n};\n\n&usb3_ss_phy {\n\tstatus = \"okay\";\n};\n\n&usb3_hs_phy {\n\tstatus = \"okay\";\n};\n\n&wifi0 {\n\tstatus = \"okay\";\n\tqcom,ath10k-calibration-variant = \"RT-AC58U\";\n};\n\n&wifi1 {\n\tstatus = \"okay\";\n\tqcom,ath10k-calibration-variant = \"RT-AC58U\";\n};\n"
  },
  {
    "path": "target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-rutx.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qcom-ipq4019-ap.dk01.1.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\taliases {\n\t\tlabel-mac-device = &gmac0;\n\t};\n\n\tmemory {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x80000000 0x10000000>;\n\t};\n\n\tsoc {\n\t\tpinctrl@1000000 {\n\t\t\tmdio_pins: mdio_pinmux {\n\t\t\t\tmux_1 {\n\t\t\t\t\tpins = \"gpio53\";\n\t\t\t\t\tfunction = \"mdio\";\n\t\t\t\t\tbias-pull-up;\n\t\t\t\t};\n\t\t\t\tmux_2 {\n\t\t\t\t\tpins = \"gpio52\";\n\t\t\t\t\tfunction = \"mdc\";\n\t\t\t\t\tbias-pull-up;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\ti2c_0_pins: i2c_0_pinmux {\n\t\t\t\tmux {\n\t\t\t\t\tpins = \"gpio58\", \"gpio59\";\n\t\t\t\t\tfunction = \"blsp_i2c0\";\n\t\t\t\t\tbias-disable;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tkeys {\n\t\t\tcompatible = \"gpio-keys\";\n\n\t\t\treset {\n\t\t\t\tlabel = \"reset\";\n\t\t\t\tgpios = <&tlmm 4 1>;\n\t\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\t};\n\t\t};\n\n\t\tgpio_export {\n\t\t\tcompatible = \"gpio-export\";\n\t\t\t#size-cells = <0>;\n\n\t\t\tgpio_out {\n\t\t\t\tgpio-export,name = \"gpio_out\";\n\t\t\t\tgpio-export,output = <0>;\n\t\t\t\tgpio-export,direction_may_change = <0>;\n\t\t\t\tgpios = <&stm32_io 23 GPIO_ACTIVE_HIGH>;\n\t\t\t};\n\n\t\t\tgpio_in {\n\t\t\t\tgpio-export,name = \"gpio_in\";\n\t\t\t\tgpio-export,input = <0>;\n\t\t\t\tgpio-export,direction_may_change = <0>;\n\t\t\t\tgpios = <&stm32_io 24 GPIO_ACTIVE_LOW>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&blsp1_i2c3 {\n\tstatus = \"okay\";\n\tpinctrl-0 = <&i2c_0_pins>;\n\tpinctrl-names = \"default\";\n\tclock-frequency = <400000>;\n\n\tstm32_io: stm32@74 {\n\t\tcompatible = \"tlt,stm32v1\";\n\t\t#gpio-cells = <2>;\n\t\t#interrupt-cells = <2>;\n\t\tgpio-controller;\n\t\tinterrupt-controller;\n\t\tinterrupt-parent = <&tlmm>;\n\t\tinterrupts = <5 2>;\n\t\treg = <0x74>;\n\t};\n};\n\n&blsp1_spi1 {\n\tcs-gpios = <&tlmm 54 0>, <&tlmm 63 0>;\n\tnum-cs = <2>;\n\n\txt25f128b@0 {\n\t\t/*\n\t\t * Factory U-boot looks in 0:BOOTCONFIG partition for active\n\t\t * partitions settings and mangles the partition config so\n\t\t * 0:QSEE/0:QSEE_1, 0:CDT/0:CDT_1 and  0:APPSBL/0:APPSBL_1 pairs\n\t\t * can be swaped. It isn't a problem but we never can be sure where\n\t\t * OFW put factory images. \"n25q128a11\" is required for proper nor\n\t\t * recognition in u-boot.\n\t\t */\n\t\tcompatible = \"jedec,spi-nor\", \"n25q128a11\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>;\n\t\tspi-max-frequency = <24000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"0:SBL1\";\n\t\t\t\treg = <0x0 0x40000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"0:MIBIB\";\n\t\t\t\treg = <0x40000 0x20000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@60000 {\n\t\t\t\tlabel = \"0:BOOTCONFIG\";\n\t\t\t\treg = <0x60000 0x20000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@80000 {\n\t\t\t\tlabel = \"0:BOOTCONFIG1\";\n\t\t\t\treg = <0x80000 0x20000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@a0000 {\n\t\t\t\tlabel = \"0:QSEE\";\n\t\t\t\treg = <0xa0000 0x60000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@100000 {\n\t\t\t\tlabel = \"0:QSEE_1\";\n\t\t\t\treg = <0x100000 0x60000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@160000 {\n\t\t\t\tlabel = \"0:CDT\";\n\t\t\t\treg = <0x160000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@170000 {\n\t\t\t\tlabel = \"0:CDT_1\";\n\t\t\t\treg = <0x170000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@180000 {\n\t\t\t\tlabel = \"0:DDRPARAMS\";\n\t\t\t\treg = <0x180000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@190000 {\n\t\t\t\tlabel = \"0:APPSBLENV\";\n\t\t\t\treg = <0x190000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@1a0000 {\n\t\t\t\tlabel = \"0:APPSBL\";\n\t\t\t\treg = <0x1a0000 0xa0000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@240000 {\n\t\t\t\tlabel = \"0:APPSBL_1\";\n\t\t\t\treg = <0x240000 0xa0000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@2e0000 {\n\t\t\t\tlabel = \"0:ART\";\n\t\t\t\treg = <0x2e0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t\tcompatible = \"nvmem-cells\";\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\n\t\t\t\tprecal_art_1000: precal@1000 {\n\t\t\t\t\treg = <0x1000 0x2f20>;\n\t\t\t\t};\n\n\t\t\t\tprecal_art_5000: precal@5000 {\n\t\t\t\t\treg = <0x5000 0x2f20>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tconfig: partition@2f0000 {\n\t\t\t\tlabel = \"0:CONFIG\";\n\t\t\t\treg = <0x2f0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t\tcompatible = \"nvmem-cells\";\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\n\t\t\t\tmacaddr_config_0: macaddr@0 {\n\t\t\t\t\treg = <0x0 0x6>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tpartition@300000 {\n\t\t\t\tlabel = \"0:CONFIG_RW\";\n\t\t\t\treg = <0x300000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@310000 {\n\t\t\t\tlabel = \"0:EVENTSLOG\";\n\t\t\t\treg = <0x310000 0x90000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n\n\txt26g02a@1 {\n\t\t/*\n\t\t * Factory U-boot looks in 0:BOOTCONFIG partition for active\n\t\t * partitions settings and mangles the partition config so\n\t\t * rootfs/rootfs_1 pairs can be swaped.\n\t\t * It isn't a problem but we never can be sure where OFW put\n\t\t * factory images. \"spinand,mt29f\" value is required for proper\n\t\t * nand recognition in u-boot.\n\t\t */\n\t\tcompatible = \"spi-nand\", \"spinand,mt29f\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <1>;\n\t\tspi-max-frequency = <24000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"rootfs_1\";\n\t\t\t\treg = <0x00000000 0x08000000>;\n\t\t\t};\n\n\t\t\tpartition@8000000 {\n\t\t\t\tlabel = \"rootfs\";\n\t\t\t\treg = <0x08000000 0x08000000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&mdio {\n\tstatus = \"okay\";\n\tpinctrl-0 = <&mdio_pins>;\n\tpinctrl-names = \"default\";\n\tphy-reset-gpio = <&tlmm 62 0>;\n};\n\n&wifi0 {\n\tnvmem-cell-names = \"pre-calibration\", \"mac-address\";\n\tnvmem-cells = <&precal_art_1000>, <&macaddr_config_0>;\n\tmac-address-increment = <2>;\n};\n\n&wifi1 {\n\tnvmem-cell-names = \"pre-calibration\", \"mac-address\";\n\tnvmem-cells = <&precal_art_5000>, <&macaddr_config_0>;\n\tmac-address-increment = <3>;\n};\n"
  },
  {
    "path": "target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-rutx10.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qcom-ipq4018-rutx.dtsi\"\n\n/ {\n\tmodel = \"Teltonika RUTX10\";\n\tcompatible = \"teltonika,rutx10\";\n\n\tsoc {\n\t\tleds {\n\t\t\tcompatible = \"gpio-leds\";\n\n\t\t\twifi2g {\n\t\t\t\tlabel = \"green:wifi2g\";\n\t\t\t\tgpios = <&stm32_io 19 GPIO_ACTIVE_HIGH>;\n\t\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t\t};\n\n\t\t\twifi5g {\n\t\t\t\tlabel = \"green:wifi5g\";\n\t\t\t\tgpios = <&stm32_io 18 GPIO_ACTIVE_HIGH>;\n\t\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t\t};\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-sxtsq-5-ac.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n/* Copyright (c) 2020, Robert Marko <robimarko@gmail.com> */\n\n#include \"qcom-ipq4019.dtsi\"\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/soc/qcom,tcsr.h>\n\n/ {\n\tmodel = \"MikroTik SXTsq 5 ac (RBSXTsqG-5acD)\";\n\tcompatible = \"mikrotik,sxtsq-5-ac\";\n\n\tmemory {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x80000000 0x10000000>;\n\t};\n\n\tchosen {\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\taliases {\n\t\tled-boot = &led_user;\n\t\tled-failsafe = &led_user;\n\t\tled-running = &led_user;\n\t\tled-upgrade = &led_user;\n\t};\n\n\tsoc {\n\t\trng@22000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tmdio@90000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tcounter@4a1000 {\n\t\t\tcompatible = \"qcom,qca-gcnt\";\n\t\t\treg = <0x4a1000 0x4>;\n\t\t};\n\n\t\ttcsr@1949000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1949000 0x100>;\n\t\t\tqcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;\n\t\t};\n\n\t\tess_tcsr@1953000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1953000 0x1000>;\n\t\t\tqcom,ess-interface-select = <TCSR_ESS_PSGMII>;\n\t\t};\n\n\t\ttcsr@1957000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1957000 0x100>;\n\t\t\tqcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;\n\t\t};\n\n\t\tcrypto@8e3a000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\twatchdog@b017000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tess-psgmii@98000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tedma@c080000 {\n\t\t\tstatus = \"okay\";\n\t\t\tphy-mode = \"rgmii\";\n\t\t\tqcom,num_gmac = <1>;\n\t\t\tqcom,single-phy;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&tlmm 63 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tpower {\n\t\t\tlabel = \"blue:power\";\n\t\t\tgpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"keep\";\n\t\t\tpanic-indicator;\n\t\t};\n\n\t\tled_user: user {\n\t\t\tlabel = \"green:user\";\n\t\t\tgpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\trssilow {\n\t\t\tlabel = \"green:rssilow\";\n\t\t\tgpios = <&tlmm 58 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\trssimediumlow {\n\t\t\tlabel = \"green:rssimediumlow\";\n\t\t\tgpios = <&tlmm 1 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\trssimedium {\n\t\t\tlabel = \"green:rssimedium\";\n\t\t\tgpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\trssimediumhigh {\n\t\t\tlabel = \"green:rssimediumhigh\";\n\t\t\tgpios = <&tlmm 4 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\trssihigh {\n\t\t\tlabel = \"green:rssihigh\";\n\t\t\tgpios = <&tlmm 5 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&tlmm {\n\tserial_pins: serial_pinmux {\n\t\tmux {\n\t\t\tpins = \"gpio60\", \"gpio61\";\n\t\t\tfunction = \"blsp_uart0\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tspi_0_pins: spi_0_pinmux {\n\t\tpin {\n\t\t\tfunction = \"blsp_spi0\";\n\t\t\tpins = \"gpio55\", \"gpio56\", \"gpio57\";\n\t\t\tdrive-strength = <2>;\n\t\t\tbias-disable;\n\t\t};\n\t\tpin_cs {\n\t\t\tfunction = \"gpio\";\n\t\t\tpins = \"gpio54\";\n\t\t\tdrive-strength = <2>;\n\t\t\tbias-disable;\n\t\t\toutput-high;\n\t\t};\n\t};\n};\n\n&blsp_dma {\n\tstatus = \"okay\";\n};\n\n&blsp1_spi1 {\n\tstatus = \"okay\";\n\n\tpinctrl-0 = <&spi_0_pins>;\n\tpinctrl-names = \"default\";\n\tcs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;\n\n\tflash@0 {\n\t\treg = <0>;\n\t\tcompatible = \"jedec,spi-nor\";\n\t\tspi-max-frequency = <40000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"Qualcomm\";\n\t\t\t\treg = <0x0 0x80000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@80000 {\n\t\t\t\tcompatible = \"mikrotik,routerboot-partitions\";\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\t\t\t\tlabel = \"RouterBoot\";\n\t\t\t\treg = <0x80000 0x80000>;\n\t\t\t\tread-only;\n\n\t\t\t\thard_config {\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\tdtb_config {\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\tsoft_config {\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tpartition@100000 {\n\t\t\t\tcompatible = \"mikrotik,minor\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x100000 0xf00000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&blsp1_uart1 {\n\tstatus = \"okay\";\n\n\tpinctrl-0 = <&serial_pins>;\n\tpinctrl-names = \"default\";\n};\n\n&cryptobam {\n\tstatus = \"okay\";\n};\n\n&wifi1 {\n\tstatus = \"okay\";\n\n\tqcom,ath10k-calibration-variant = \"MikroTik-SXTsq-5-ac\";\n};\n\n&gmac0 {\n\tqcom,phy_mdio_addr = <4>;\n\tqcom,poll_required = <1>;\n\tqcom,forced_speed = <1000>;\n\tqcom,forced_duplex = <1>;\n\tvlan_tag = <1 0x20>;\n};\n\n&mdio {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-wac510.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n/* Copyright (c) 2020, Robert Marko <robimarko@gmail.com> */\n\n#include \"qcom-ipq4019.dtsi\"\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/soc/qcom,tcsr.h>\n#include <dt-bindings/leds/common.h>\n\n/ {\n\tmodel = \"Netgear WAC510\";\n\tcompatible = \"netgear,wac510\";\n\n\taliases {\n\t\tled-boot = &led_power_amber;\n\t\tled-failsafe = &led_power_amber;\n\t\tled-running = &led_power_green;\n\t\tled-upgrade = &led_power_amber;\n\t\tlabel-mac-device = &gmac0;\n\t};\n\n\tchosen {\n\t\tbootargs-append = \" root=/dev/ubiblock0_1\";\n\t};\n\n\tsoc {\n\t\trng@22000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tess-psgmii@98000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tcounter@4a1000 {\n\t\t\tcompatible = \"qcom,qca-gcnt\";\n\t\t\treg = <0x4a1000 0x4>;\n\t\t};\n\n\t\ttcsr@1949000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1949000 0x100>;\n\t\t\tqcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;\n\t\t};\n\n\t\tess_tcsr@1953000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1953000 0x1000>;\n\t\t\tqcom,ess-interface-select = <TCSR_ESS_PSGMII>;\n\t\t};\n\n\t\ttcsr@1957000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1957000 0x100>;\n\t\t\tqcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;\n\t\t};\n\n\t\tcrypto@8e3a000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\twatchdog@b017000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tess-switch@c000000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tedma@c080000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&tlmm 63 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tled_spi {\n\t\tcompatible = \"spi-gpio\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tsck-gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>;\n\t\tmosi-gpios = <&tlmm 4 GPIO_ACTIVE_HIGH>;\n\t\tnum-chipselects = <0>;\n\n\t\tssr: ssr@0 {\n\t\t\tcompatible = \"fairchild,74hc595\";\n\t\t\treg = <0>;\n\t\t\tgpio-controller;\n\t\t\t#gpio-cells = <2>;\n\t\t\tregisters-number = <1>;\n\t\t\tspi-max-frequency = <1000000>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power_amber: led-0 {\n\t\t\tlabel = \"amber:power\";\n\t\t\tcolor = <LED_COLOR_ID_AMBER>;\n\t\t\tfunction = LED_FUNCTION_POWER;\n\t\t\tgpios = <&ssr 6 GPIO_ACTIVE_LOW>;\n\t\t\tpanic-indicator;\n\t\t};\n\n\t\tled_power_green: led-1 {\n\t\t\tlabel = \"green:power\";\n\t\t\tcolor = <LED_COLOR_ID_AMBER>;\n\t\t\tfunction = LED_FUNCTION_POWER;\n\t\t\tgpios = <&ssr 5 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled-2 {\n\t\t\t/* 2.4GHz blue - activity */\n\t\t\tcolor = <LED_COLOR_ID_BLUE>;\n\t\t\tfunction = LED_FUNCTION_WLAN;\n\t\t\tfunction-enumerator = <0>;\n\t\t\tgpios = <&ssr 4 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\tled-3 {\n\t\t\t/* 2.4GHz green - link */\n\t\t\tcolor = <LED_COLOR_ID_GREEN>;\n\t\t\tfunction = LED_FUNCTION_WLAN;\n\t\t\tfunction-enumerator = <0>;\n\t\t\tgpios = <&ssr 3 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0radio\";\n\t\t};\n\n\t\tled-4 {\n\t\t\t/* 5GHz blue - activity */\n\t\t\tcolor = <LED_COLOR_ID_BLUE>;\n\t\t\tfunction = LED_FUNCTION_WLAN;\n\t\t\tfunction-enumerator = <1>;\n\t\t\tgpios = <&ssr 2 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\n\t\tled-5 {\n\t\t\t/* 5GHz green - link */\n\t\t\tcolor = <LED_COLOR_ID_GREEN>;\n\t\t\tfunction = LED_FUNCTION_WLAN;\n\t\t\tfunction-enumerator = <1>;\n\t\t\tgpios = <&ssr 1 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1radio\";\n\t\t};\n\n\t\tled-6 {\n\t\t\tcolor = <LED_COLOR_ID_GREEN>;\n\t\t\tfunction = LED_FUNCTION_ACTIVITY;\n\t\t\tgpios = <&ssr 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&qpic_bam {\n\tstatus = \"okay\";\n};\n\n&tlmm {\n\tmdio_pins: mdio_pinmux {\n\t\tmux_1 {\n\t\t\tpins = \"gpio53\";\n\t\t\tfunction = \"mdio\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tmux_2 {\n\t\t\tpins = \"gpio52\";\n\t\t\tfunction = \"mdc\";\n\t\t\tbias-pull-up;\n\t\t};\n\t};\n\n\tserial_pins: serial_pinmux {\n\t\tmux {\n\t\t\tpins = \"gpio60\", \"gpio61\";\n\t\t\tfunction = \"blsp_uart0\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tspi_0_pins: spi_0_pinmux {\n\t\tpinmux {\n\t\t\tfunction = \"blsp_spi0\";\n\t\t\tpins = \"gpio55\", \"gpio56\", \"gpio57\";\n\t\t\tdrive-strength = <12>;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tpinmux_cs {\n\t\t\tfunction = \"gpio\";\n\t\t\tpins = \"gpio54\", \"gpio59\";\n\t\t\tdrive-strength = <2>;\n\t\t\tbias-disable;\n\t\t\toutput-high;\n\t\t};\n\t};\n};\n\n&blsp_dma {\n\tstatus = \"okay\";\n};\n\n&blsp1_spi1 {\n\tstatus = \"okay\";\n\n\tpinctrl-0 = <&spi_0_pins>;\n\tpinctrl-names = \"default\";\n\tcs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>,\n\t\t   <&tlmm 59 GPIO_ACTIVE_HIGH>;\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\tspi-max-frequency = <50000000>;\n\t\treg = <0>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"0:SBL1\";\n\t\t\t\treg = <0x00000000 0x00040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"0:MIBIB\";\n\t\t\t\treg = <0x00040000 0x00020000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@60000 {\n\t\t\t\tlabel = \"0:QSEE\";\n\t\t\t\treg = <0x00060000 0x00060000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@c0000 {\n\t\t\t\tlabel = \"0:CDT\";\n\t\t\t\treg = <0x000c0000 0x00010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@d0000 {\n\t\t\t\tlabel = \"0:DDRPARAMS\";\n\t\t\t\treg = <0x000d0000 0x00010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@e0000 {\n\t\t\t\tlabel = \"0:APPSBLENV\";\n\t\t\t\treg = <0x000e0000 0x00010000>;\n\t\t\t};\n\n\t\t\tpartition@f0000 {\n\t\t\t\tlabel = \"0:APPSBL\";\n\t\t\t\treg = <0x000f0000 0x000f0000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@1e0000 {\n\t\t\t\tlabel = \"0:MANUDATA\";\n\t\t\t\treg = <0x001e0000 0x00010000>;\n\t\t\t\tread-only;\n\t\t\t\tcompatible = \"nvmem-cells\";\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\n\t\t\t\tmacaddr_manudata_6: macaddr@6 {\n\t\t\t\t\treg = <0x6 0x6>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tpartition@1f0000 {\n\t\t\t\tlabel = \"0:ART\";\n\t\t\t\treg = <0x001f0000 0x00010000>;\n\t\t\t\tread-only;\n\t\t\t\tcompatible = \"nvmem-cells\";\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\n\t\t\t\tprecal_art_1000: precal@1000 {\n\t\t\t\t\treg = <0x1000 0x2f20>;\n\t\t\t\t};\n\n\t\t\t\tprecal_art_5000: precal@5000 {\n\t\t\t\t\treg = <0x5000 0x2f20>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t};\n\n\tnand@1 {\n\t\tcompatible = \"spi-nand\";\n\t\treg = <1>;\n\t\tspi-max-frequency = <48000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"rootfs\";\n\t\t\t\treg = <0x00000000 0x03800000>;\n\t\t\t};\n\n\t\t\tpartition@3800000 {\n\t\t\t\tlabel = \"rootfs_1\";\n\t\t\t\treg = <0x03800000 0x03800000>;\n\t\t\t};\n\n\t\t\tpartition@7000000 {\n\t\t\t\tlabel = \"var_config\";\n\t\t\t\treg = <0x07000000 0x00f00000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@7f00000 {\n\t\t\t\tlabel = \"Oops_log\";\n\t\t\t\treg = <0x07f00000 0x000c0000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&blsp1_uart1 {\n\tstatus = \"okay\";\n\n\tpinctrl-0 = <&serial_pins>;\n\tpinctrl-names = \"default\";\n};\n\n&cryptobam {\n\tstatus = \"okay\";\n};\n\n&mdio {\n\tstatus = \"okay\";\n\n\tpinctrl-0 = <&mdio_pins>;\n\tpinctrl-names = \"default\";\n\treset-gpios = <&tlmm 62 GPIO_ACTIVE_LOW>;\n\treset-delay-us = <2000>;\n};\n\n&gmac0 {\n\tqcom,forced_duplex = <1>;\n\tqcom,forced_speed = <1000>;\n\tqcom,phy_mdio_addr = <3>;\n\tqcom,poll_required = <1>;\n\tvlan_tag = <1 0x10>;\n};\n\n&wifi0 {\n\tstatus = \"okay\";\n\tnvmem-cell-names = \"pre-calibration\", \"mac-address\";\n\tnvmem-cells = <&precal_art_1000>, <&macaddr_manudata_6>;\n\tqcom,ath10k-calibration-variant = \"Netgear-WAC510\";\n};\n\n&wifi1 {\n\tstatus = \"okay\";\n\tnvmem-cell-names = \"pre-calibration\", \"mac-address\";\n\tnvmem-cells = <&precal_art_5000>, <&macaddr_manudata_6>;\n\tmac-address-increment = <16>;\n\tqcom,ath10k-calibration-variant = \"Netgear-WAC510\";\n};\n"
  },
  {
    "path": "target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-wre6606.dts",
    "content": "/* Copyright (c) 2015, The Linux Foundation. All rights reserved.\n * Copyright (c) 2018, David Bauer <mail@david-bauer.net>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#include \"qcom-ipq4019.dtsi\"\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/soc/qcom,tcsr.h>\n\n/ {\n\tmodel = \"ZyXEL WRE6606\";\n\tcompatible = \"zyxel,wre6606\";\n\n\taliases {\n\t\tled-boot = &power;\n\t\tled-failsafe = &power;\n\t\tled-running = &power;\n\t\tled-upgrade = &power;\n\t};\n\n\tchosen {\n\t\tbootargs-append = \" mtdparts=\";\n\t};\n\n\tsoc {\n\t\trng@22000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tmdio@90000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tess-psgmii@98000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\ttcsr@1949000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1949000 0x100>;\n\t\t\tqcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;\n\t\t};\n\n\t\tess_tcsr@1953000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1953000 0x1000>;\n\t\t\tqcom,ess-interface-select = <TCSR_ESS_PSGMII>;\n\t\t};\n\n\t\ttcsr@1957000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1957000 0x100>;\n\t\t\tqcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;\n\t\t};\n\n\t\tcrypto@8e3a000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\twatchdog@b017000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tess-switch@c000000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tedma@c080000 {\n\t\t\tstatus = \"okay\";\n\t\t\tqcom,num_gmac = <1>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twps {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&tlmm 1 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\twlan5g_green {\n\t\t\tlabel = \"green:wlan5g\";\n\t\t\tgpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tpower: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&tlmm 4 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\twlan5g_red {\n\t\t\tlabel = \"red:wlan5g\";\n\t\t\tgpios = <&tlmm 5 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\twlan2g_red {\n\t\t\tlabel = \"red:wlan2g\";\n\t\t\tgpios = <&tlmm 58 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\twlan2g_green {\n\t\t\tlabel = \"green:wlan2g\";\n\t\t\tgpios = <&tlmm 59 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&tlmm 63 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n};\n\n&tlmm {\n\tserial_pins: serial_pinmux {\n\t\tmux {\n\t\t\tpins = \"gpio60\", \"gpio61\";\n\t\t\tfunction = \"blsp_uart0\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tspi_0_pins: spi_0_pinmux {\n\t\tpin {\n\t\t\tfunction = \"blsp_spi0\";\n\t\t\tpins = \"gpio55\", \"gpio56\", \"gpio57\";\n\t\t\tdrive-strength = <12>;\n\t\t\tbias-disable;\n\t\t};\n\t\tpin_cs {\n\t\t\tfunction = \"gpio\";\n\t\t\tpins = \"gpio54\";\n\t\t\tdrive-strength = <2>;\n\t\t\tbias-disable;\n\t\t\toutput-high;\n\t\t};\n\t};\n};\n\n&blsp_dma {\n\tstatus = \"okay\";\n};\n\n&blsp1_spi1 {\n\tpinctrl-0 = <&spi_0_pins>;\n\tpinctrl-names = \"default\";\n\tstatus = \"okay\";\n\tcs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;\n\n\tmx25l12805d@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <24000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition0@0 {\n\t\t\t\tlabel = \"SBL1\";\n\t\t\t\treg = <0x00000000 0x00040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition1@40000 {\n\t\t\t\tlabel = \"MIBIB\";\n\t\t\t\treg = <0x00040000 0x00020000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition2@60000 {\n\t\t\t\tlabel = \"QSEE\";\n\t\t\t\treg = <0x00060000 0x00060000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition3@c0000 {\n\t\t\t\tlabel = \"CDT\";\n\t\t\t\treg = <0x000c0000 0x00010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition4@d0000 {\n\t\t\t\tlabel = \"DDRPARAMS\";\n\t\t\t\treg = <0x000d0000 0x00010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition5@E0000 {\n\t\t\t\tlabel = \"APPSBLENV\";\n\t\t\t\treg = <0x000e0000 0x00010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition6@F0000 {\n\t\t\t\tlabel = \"APPSBL\";\n\t\t\t\treg = <0x000f0000 0x00080000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition7@170000 {\n\t\t\t\tlabel = \"ART\";\n\t\t\t\treg = <0x00170000 0x00010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition8@180000 {\n\t\t\t\tcompatible = \"denx,fit\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x00180000 0x00ce0000>;\n\t\t\t};\n\n\t\t\tpartition9@e60000 {\n\t\t\t\tlabel = \"manufacture\";\n\t\t\t\treg = <0x00e60000 0x00050000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition10@eb0000 {\n\t\t\t\tlabel = \"storage\";\n\t\t\t\treg = <0x00eb0000 0x00150000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&blsp1_uart1 {\n\tpinctrl-0 = <&serial_pins>;\n\tpinctrl-names = \"default\";\n\tstatus = \"okay\";\n};\n\n&cryptobam {\n\tstatus = \"okay\";\n};\n\n&wifi0 {\n\tstatus = \"okay\";\n\tqcom,ath10k-calibration-variant = \"ZyXEL-WRE6606\";\n};\n\n&wifi1 {\n\tstatus = \"okay\";\n\tqcom,ath10k-calibration-variant = \"ZyXEL-WRE6606\";\n};\n"
  },
  {
    "path": "target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-wrtq-329acn.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qcom-ipq4019.dtsi\"\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/soc/qcom,tcsr.h>\n\n/ {\n\tmodel = \"Luma Home WRTQ-329ACN\";\n\tcompatible = \"luma,wrtq-329acn\";\n\n\ti2c-gpio {\n\t\tcompatible = \"i2c-gpio\";\n\t\tsda-gpios = <&tlmm 1 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;\n\t\tscl-gpios = <&tlmm 0 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\t/* No driver exists */\n\t\tled_ring@48 {\n\t\t\tcompatible = \"ti,msp430\";\n\t\t\treg = <0x48>;\n\t\t};\n\n\t\teeprom@50 {\n\t\t\tcompatible = \"atmel,24c16\";\n\t\t\treg = <0x50>;\n\t\t\tpagesize = <16>;\n\t\t\tread-only;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&tlmm 63 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tsoc {\n\t\trng@22000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tmdio@90000 {\n\t\t\tstatus = \"okay\";\n\n\t\t\t/delete-node/ ethernet-phy@0;\n\t\t\t/delete-node/ ethernet-phy@1;\n\t\t\t/delete-node/ ethernet-phy@3;\n\t\t};\n\n\t\tess-psgmii@98000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\ttcsr@1949000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1949000 0x100>;\n\t\t\tqcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;\n\t\t};\n\n\t\ttcsr@194b000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x194b000 0x100>;\n\t\t\tqcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;\n\t\t};\n\n\t\tess_tcsr@1953000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1953000 0x1000>;\n\t\t\tqcom,ess-interface-select = <TCSR_ESS_PSGMII>;\n\t\t};\n\n\t\ttcsr@1957000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1957000 0x100>;\n\t\t\tqcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;\n\t\t};\n\n\t\tusb2@60f8800 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tusb3@8af8800 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tcrypto@8e3a000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\twatchdog@b017000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tess-switch@c000000 {\n\t\t\tstatus = \"okay\";\n\n\t\t\tswitch_lan_bmp = <0x1e>;\n\t\t\tswitch_wan_bmp = <0x20>;\n\t\t};\n\n\t\tedma@c080000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\t};\n};\n\n&blsp_dma {\n\tstatus = \"okay\";\n};\n\n\n&blsp1_spi1 {\n\tstatus = \"okay\";\n\n\tcs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>,\n\t\t   <&tlmm 59 GPIO_ACTIVE_HIGH>;\n\tpinctrl-0 = <&spi0_pins>;\n\tpinctrl-names = \"default\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <24000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"0:SBL1\";\n\t\t\t\treg = <0x000000 0x040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"0:MIBIB\";\n\t\t\t\treg = <0x040000 0x020000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@60000 {\n\t\t\t\tlabel = \"0:QSEE\";\n\t\t\t\treg = <0x060000 0x060000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@c0000 {\n\t\t\t\tlabel = \"0:CDT\";\n\t\t\t\treg = <0x0c0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@d0000 {\n\t\t\t\tlabel = \"0:DDRPARAMS\";\n\t\t\t\treg = <0x0d0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@e0000 {\n\t\t\t\tlabel = \"0:APPSBLENV\";\n\t\t\t\treg = <0x0e0000 0x010000>;\n\t\t\t};\n\n\t\t\tpartition@f0000 {\n\t\t\t\tlabel = \"0:APPSBL\";\n\t\t\t\treg = <0x0f0000 0x080000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@170000 {\n\t\t\t\tlabel = \"0:ART\";\n\t\t\t\treg = <0x170000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t\tcompatible = \"nvmem-cells\";\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\n\t\t\t\tprecal_art_1000: precal@1000 {\n\t\t\t\t\treg = <0x1000 0x2f20>;\n\t\t\t\t};\n\n\t\t\t\tprecal_art_5000: precal@5000 {\n\t\t\t\t\treg = <0x5000 0x2f20>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t};\n\n\tflash@1 {\n\t\tstatus = \"okay\";\n\n\t\tcompatible = \"spi-nand\";\n\t\treg = <1>;\n\t\tspi-max-frequency = <24000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"ubi\";\n\t\t\t\treg = <0x0000000 0x8000000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&blsp1_uart1 {\n\tstatus = \"okay\";\n\n\tpinctrl-0 = <&serial0_pins>;\n\tpinctrl-names = \"default\";\n};\n\n&cryptobam {\n\tstatus = \"okay\";\n};\n\n&gmac0 {\n\tqcom,phy_mdio_addr = <2>;\n\tqcom,poll_required = <1>;\n};\n\n&gmac1 {\n\tqcom,phy_mdio_addr = <4>;\n\tqcom,poll_required = <1>;\n};\n\n&tlmm {\n\tserial0_pins: serial0_pinmux {\n\t\tmux {\n\t\t\tfunction = \"blsp_uart0\";\n\t\t\tpins = \"gpio60\", \"gpio61\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tspi0_pins: spi0_pinmux {\n\t\tmux {\n\t\t\tfunction = \"blsp_spi0\";\n\t\t\tpins = \"gpio55\", \"gpio56\", \"gpio57\";\n\t\t\tbias-disable;\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tmux_cs {\n\t\t\tfunction = \"gpio\";\n\t\t\tpins = \"gpio54\", \"gpio59\";\n\t\t\tbias-disable;\n\t\t\tdrive-strength = <2>;\n\t\t\toutput-high;\n\t\t};\n\t};\n};\n\n&usb2_hs_phy {\n\tstatus = \"okay\";\n};\n\n&usb3_hs_phy {\n\tstatus = \"okay\";\n};\n\n&usb3_ss_phy {\n\tstatus = \"okay\";\n};\n\n&wifi0 {\n\tstatus = \"okay\";\n\tnvmem-cell-names = \"pre-calibration\";\n\tnvmem-cells = <&precal_art_1000>;\n\tqcom,ath10k-calibration-variant = \"Luma-WRTQ-329ACN\";\n};\n\n&wifi1 {\n\tstatus = \"okay\";\n\tnvmem-cell-names = \"pre-calibration\";\n\tnvmem-cells = <&precal_art_5000>;\n\tqcom,ath10k-calibration-variant = \"Luma-WRTQ-329ACN\";\n};\n"
  },
  {
    "path": "target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-a62.dts",
    "content": "// SPDX-License-Identifier: ISC\n/* Copyright (c) 2015, The Linux Foundation. All rights reserved.\n * Copyright (c) 2017-2018, Sven Eckelmann <sven.eckelmann@openmesh.com>\n */\n\n#include \"qcom-ipq4019.dtsi\"\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/soc/qcom,tcsr.h>\n\n/ {\n\tmodel = \"OpenMesh A62\";\n\tcompatible = \"openmesh,a62\";\n\n\tsoc {\n\t\trng@22000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tmdio@90000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tess-psgmii@98000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\ttcsr@194b000 {\n\t\t\t/* select hostmode */\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x194b000 0x100>;\n\t\t\tqcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\ttcsr@1949000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1949000 0x100>;\n\t\t\tqcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;\n\t\t};\n\n\t\tess_tcsr@1953000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1953000 0x1000>;\n\t\t\tqcom,ess-interface-select = <TCSR_ESS_PSGMII>;\n\t\t};\n\n\t\ttcsr@1957000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1957000 0x100>;\n\t\t\tqcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;\n\t\t};\n\n\t\tusb2: usb2@60f8800 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tcrypto@8e3a000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\twatchdog@b017000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tess-switch@c000000 {\n\t\t\tswitch_lan_bmp = <0x10>;\n\t\t\tswitch_wan_bmp = <0x20>;\n\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tedma@c080000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&tlmm 18 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART >;\n\t\t};\n\t};\n\n\taliases {\n\t\tled-boot = &led_status_green;\n\t\tled-failsafe = &led_status_green;\n\t\tled-running = &led_status_green;\n\t\tled-upgrade = &led_status_green;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tstatus_red {\n\t\t\tlabel = \"red:status\";\n\t\t\tgpios = <&tlmm 43 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tled_status_green: status_green {\n\t\t\tlabel = \"green:status\";\n\t\t\tgpios = <&tlmm 45 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tstatus_blue {\n\t\t\tlabel = \"blue:status\";\n\t\t\tgpios = <&tlmm 46 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n\n\twatchdog {\n\t\tcompatible = \"linux,wdt-gpio\";\n\t\tgpios = <&tlmm 59 GPIO_ACTIVE_LOW>;\n\t\thw_algo = \"toggle\";\n\t\t/* hw_margin_ms is actually 300s but driver limits it to 60s */\n\t\thw_margin_ms = <60000>;\n\t\talways-running;\n\t};\n};\n\n&tlmm {\n\tserial_pins: serial_pinmux {\n\t\tmux {\n\t\t\tpins = \"gpio16\", \"gpio17\";\n\t\t\tfunction = \"blsp_uart0\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tspi_0_pins: spi_0_pinmux {\n\t\tpin {\n\t\t\tfunction = \"blsp_spi0\";\n\t\t\tpins = \"gpio13\", \"gpio14\", \"gpio15\";\n\t\t\tdrive-strength = <12>;\n\t\t\tbias-disable;\n\t\t};\n\t\tpin_cs {\n\t\t\tfunction = \"gpio\";\n\t\t\tpins = \"gpio12\";\n\t\t\tdrive-strength = <2>;\n\t\t\tbias-disable;\n\t\t\toutput-high;\n\t\t};\n\t};\n\n\tenable-usb-power {\n\t\tgpio-hog;\n\t\tgpios = <58 GPIO_ACTIVE_HIGH>;\n\t\toutput-low;\n\t\tline-name = \"enable USB2 power\";\n\t};\n};\n\n&blsp_dma {\n\tstatus = \"okay\";\n};\n\n&blsp1_spi1 {\n\tpinctrl-0 = <&spi_0_pins>;\n\tpinctrl-names = \"default\";\n\tstatus = \"okay\";\n\tcs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;\n\n\tflash@0 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <24000000>;\n\t\t/* partitions are passed via bootloader */\n\t};\n};\n\n&blsp1_uart1 {\n\tpinctrl-0 = <&serial_pins>;\n\tpinctrl-names = \"default\";\n\tstatus = \"okay\";\n};\n\n&cryptobam {\n\tstatus = \"okay\";\n};\n\n&gmac0 {\n\tqcom,phy_mdio_addr = <3>;\n\tqcom,poll_required = <1>;\n\tqcom,forced_speed = <1000>;\n\tqcom,forced_duplex = <1>;\n\tvlan_tag = <1 0x10>;\n};\n\n&usb2_hs_phy {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\tstatus = \"okay\";\n\tperst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;\n\twake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>;\n\n\tbridge@0,0 {\n\t\treg = <0x00000000 0 0 0 0>;\n\t\t#address-cells = <3>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\twifi2: wifi@1,0 {\n\t\t\tcompatible = \"qcom,ath10k\";\n\t\t\tstatus = \"okay\";\n\t\t\treg = <0x00010000 0 0 0 0>;\n\t\t\tqcom,ath10k-calibration-variant = \"OM-A62\";\n\t\t\tieee80211-freq-limit = <5170000 5350000>;\n\t\t};\n\t};\n};\n\n&wifi0 {\n\tstatus = \"okay\";\n\tqcom,ath10k-calibration-variant = \"OM-A62\";\n};\n\n&wifi1 {\n\tstatus = \"okay\";\n\tqcom,ath10k-calibration-variant = \"OM-A62\";\n\tieee80211-freq-limit = <5470000 5875000>;\n};\n"
  },
  {
    "path": "target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-cm520-79f.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qcom-ipq4019.dtsi\"\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/soc/qcom,tcsr.h>\n\n/ {\n\tmodel = \"MobiPromo CM520-79F\";\n\tcompatible = \"mobipromo,cm520-79f\";\n\n\taliases {\n\t\tled-boot = &led_sys;\n\t\tled-failsafe = &led_sys;\n\t\tled-running = &led_sys;\n\t\tled-upgrade = &led_sys;\n\t};\n\n\tsoc {\n\t\trng@22000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tmdio@90000 {\n\t\t\tstatus = \"okay\";\n\t\t\tpinctrl-0 = <&mdio_pins>;\n\t\t\tpinctrl-names = \"default\";\n\t\t\treset-gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;\n\t\t\treset-delay-us = <1000>;\n\t\t};\n\n\t\tess-psgmii@98000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\ttcsr@1949000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1949000 0x100>;\n\t\t\tqcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;\n\t\t};\n\n\t\ttcsr@194b000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x194b000 0x100>;\n\t\t\tqcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;\n\t\t};\n\n\t\tess_tcsr@1953000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1953000 0x1000>;\n\t\t\tqcom,ess-interface-select = <TCSR_ESS_PSGMII>;\n\t\t};\n\n\t\ttcsr@1957000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1957000 0x100>;\n\t\t\tqcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;\n\t\t};\n\n\t\tusb2@60f8800 {\n\t\t\tstatus = \"okay\";\n\n\t\t\tdwc3@6000000 {\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\n\t\t\t\tusb2_port1: port@1 {\n\t\t\t\t\treg = <1>;\n\t\t\t\t\t#trigger-source-cells = <0>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tusb3@8af8800 {\n\t\t\tstatus = \"okay\";\n\n\t\t\tdwc3@8a00000 {\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\n\t\t\t\tusb3_port1: port@1 {\n\t\t\t\t\treg = <1>;\n\t\t\t\t\t#trigger-source-cells = <0>;\n\t\t\t\t};\n\n\t\t\t\tusb3_port2: port@2 {\n\t\t\t\t\treg = <2>;\n\t\t\t\t\t#trigger-source-cells = <0>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tcrypto@8e3a000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\twatchdog@b017000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tess-switch@c000000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tedma@c080000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\t};\n\n\tled_spi {\n\t\tcompatible = \"spi-gpio\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tsck-gpios = <&tlmm 40 GPIO_ACTIVE_HIGH>;\n\t\tmosi-gpios = <&tlmm 36 GPIO_ACTIVE_HIGH>;\n\t\tnum-chipselects = <0>;\n\n\t\tled_gpio: led_gpio@0 {\n\t\t\tcompatible = \"fairchild,74hc595\";\n\t\t\treg = <0>;\n\t\t\tgpio-controller;\n\t\t\t#gpio-cells = <2>;\n\t\t\tregisters-number = <1>;\n\t\t\tspi-max-frequency = <1000000>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tusb {\n\t\t\tlabel = \"blue:usb\";\n\t\t\tgpios = <&tlmm 10 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t\ttrigger-sources = <&usb3_port1>, <&usb3_port2>, <&usb2_port1>;\n\t\t};\n\n\t\tled_sys: can {\n\t\t\tlabel = \"blue:can\";\n\t\t\tgpios = <&tlmm 11 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\twan {\n\t\t\tlabel = \"blue:wan\";\n\t\t\tgpios = <&led_gpio 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan1 {\n\t\t\tlabel = \"blue:lan1\";\n\t\t\tgpios = <&led_gpio 1 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan2 {\n\t\t\tlabel = \"blue:lan2\";\n\t\t\tgpios = <&led_gpio 2 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan2g {\n\t\t\tlabel = \"blue:wlan2g\";\n\t\t\tgpios = <&led_gpio 5 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\twlan5g {\n\t\t\tlabel = \"blue:wlan5g\";\n\t\t\tgpios = <&led_gpio 6 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&tlmm 18 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n};\n\n&blsp_dma {\n\tstatus = \"okay\";\n};\n\n&blsp1_uart1 {\n\tstatus = \"okay\";\n};\n\n&blsp1_uart2 {\n\tstatus = \"okay\";\n};\n\n&cryptobam {\n\tstatus = \"okay\";\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_art_1006>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&gmac1 {\n\tnvmem-cells = <&macaddr_art_5006>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&nand {\n\tpinctrl-0 = <&nand_pins>;\n\tpinctrl-names = \"default\";\n\tstatus = \"okay\";\n\n\tnand@0 {\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"SBL1\";\n\t\t\t\treg = <0x0 0x100000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@100000 {\n\t\t\t\tlabel = \"MIBIB\";\n\t\t\t\treg = <0x100000 0x100000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@200000 {\n\t\t\t\tlabel = \"BOOTCONFIG\";\n\t\t\t\treg = <0x200000 0x100000>;\n\t\t\t};\n\n\t\t\tpartition@300000 {\n\t\t\t\tlabel = \"QSEE\";\n\t\t\t\treg = <0x300000 0x100000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@400000 {\n\t\t\t\tlabel = \"QSEE_1\";\n\t\t\t\treg = <0x400000 0x100000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@500000 {\n\t\t\t\tlabel = \"CDT\";\n\t\t\t\treg = <0x500000 0x80000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@580000 {\n\t\t\t\tlabel = \"CDT_1\";\n\t\t\t\treg = <0x580000 0x80000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@600000 {\n\t\t\t\tlabel = \"BOOTCONFIG1\";\n\t\t\t\treg = <0x600000 0x80000>;\n\t\t\t};\n\n\t\t\tpartition@680000 {\n\t\t\t\tlabel = \"APPSBLENV\";\n\t\t\t\treg = <0x680000 0x80000>;\n\t\t\t};\n\n\t\t\tpartition@700000 {\n\t\t\t\tlabel = \"APPSBL\";\n\t\t\t\treg = <0x700000 0x200000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@900000 {\n\t\t\t\tlabel = \"APPSBL_1\";\n\t\t\t\treg = <0x900000 0x200000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tart: partition@b00000 {\n\t\t\t\tlabel = \"ART\";\n\t\t\t\treg = <0xb00000 0x80000>;\n\t\t\t\tread-only;\n\t\t\t\tcompatible = \"nvmem-cells\";\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\n\t\t\t\tprecal_art_1000: precal@1000 {\n\t\t\t\t\treg = <0x1000 0x2f20>;\n\t\t\t\t};\n\n\t\t\t\tmacaddr_art_1006: macaddr@1006 {\n\t\t\t\t\treg = <0x1006 0x6>;\n\t\t\t\t};\n\n\t\t\t\tprecal_art_5000: precal@5000 {\n\t\t\t\t\treg = <0x5000 0x2f20>;\n\t\t\t\t};\n\n\t\t\t\tmacaddr_art_5006: macaddr@5006 {\n\t\t\t\t\treg = <0x5006 0x6>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tpartition@b80000 {\n\t\t\t\tlabel = \"ubi\";\n\t\t\t\treg = <0xb80000 0x7480000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&qpic_bam {\n\tstatus = \"okay\";\n};\n\n&tlmm {\n\tmdio_pins: mdio_pinmux {\n\t\tmux_1 {\n\t\t\tpins = \"gpio6\";\n\t\t\tfunction = \"mdio\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tmux_2 {\n\t\t\tpins = \"gpio7\";\n\t\t\tfunction = \"mdc\";\n\t\t\tbias-pull-up;\n\t\t};\n\t};\n\n\tnand_pins: nand_pins {\n\t\tpullups {\n\t\t\tpins =\t\"gpio52\", \"gpio53\", \"gpio58\",\n\t\t\t\t\"gpio59\";\n\t\t\tfunction = \"qpic\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tpulldowns {\n\t\t\tpins =\t\"gpio54\", \"gpio55\", \"gpio56\",\n\t\t\t\t\"gpio57\", \"gpio60\", \"gpio61\",\n\t\t\t\t\"gpio62\", \"gpio63\", \"gpio64\",\n\t\t\t\t\"gpio65\", \"gpio66\", \"gpio67\",\n\t\t\t\t\"gpio68\", \"gpio69\";\n\t\t\tfunction = \"qpic\";\n\t\t\tbias-pull-down;\n\t\t};\n\t};\n};\n\n&usb3_ss_phy {\n\tstatus = \"okay\";\n};\n\n&usb3_hs_phy {\n\tstatus = \"okay\";\n};\n\n&usb2_hs_phy {\n\tstatus = \"okay\";\n};\n\n&wifi0 {\n\tstatus = \"okay\";\n\tnvmem-cell-names = \"pre-calibration\";\n\tnvmem-cells = <&precal_art_1000>;\n\tqcom,ath10k-calibration-variant = \"CM520-79F\";\n};\n\n&wifi1 {\n\tstatus = \"okay\";\n\tnvmem-cell-names = \"pre-calibration\";\n\tnvmem-cells = <&precal_art_5000>;\n\tqcom,ath10k-calibration-variant = \"CM520-79F\";\n};\n"
  },
  {
    "path": "target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-e2600ac-c1.dts",
    "content": "/* SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n *\n * Copyright (c) 2018 Peng Zhang <sd20@qxwlan.com>\n *\n */\n\n#include \"qcom-ipq4019-e2600ac.dtsi\"\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"Qxwlan E2600AC c1\";\n\tcompatible = \"qxwlan,e2600ac-c1\";\n};\n\n&blsp1_spi1 {\n\tpinctrl-0 = <&spi_0_pins>;\n\tpinctrl-names = \"default\";\n\tstatus = \"okay\";\n\tcs-gpios = <&tlmm 12 GPIO_ACTIVE_LOW>;\n\n\tflash@0 {\n\t\treg = <0>;\n\t\tcompatible = \"jedec,spi-nor\";\n\t\tspi-max-frequency = <24000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"0:SBL1\";\n\t\t\t\treg = <0x0 0x40000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"0:MIBIB\";\n\t\t\t\treg = <0x40000 0x20000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@60000 {\n\t\t\t\tlabel = \"0:QSEE\";\n\t\t\t\treg = <0x60000 0x60000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@c0000 {\n\t\t\t\tlabel = \"0:CDT\";\n\t\t\t\treg = <0xc0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@d0000 {\n\t\t\t\tlabel = \"0:DDRPARAMS\";\n\t\t\t\treg = <0xd0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@e0000 {\n\t\t\t\tlabel = \"0:APPSBLENV\";\n\t\t\t\treg = <0xe0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@f0000 {\n\t\t\t\tlabel = \"0:APPSBL\";\n\t\t\t\treg = <0xf0000 0x80000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@170000 {\n\t\t\t\tlabel = \"0:ART\";\n\t\t\t\treg = <0x170000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t\tcompatible = \"nvmem-cells\";\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\n\t\t\t\tprecal_art_1000: precal@1000 {\n\t\t\t\t\treg = <0x1000 0x2f20>;\n\t\t\t\t};\n\n\t\t\t\tprecal_art_5000: precal@5000 {\n\t\t\t\t\treg = <0x5000 0x2f20>;\n\t\t\t\t};\n\t\t\t};\n\t\t\tpartition@180000 {\n\t\t\t\tcompatible = \"denx,fit\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x180000 0x1e80000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&wifi0 {\n\tstatus = \"okay\";\n\tnvmem-cell-names = \"pre-calibration\";\n\tnvmem-cells = <&precal_art_1000>;\n\tqcom,ath10k-calibration-variant = \"Qxwlan-E2600AC-C1\";\n};\n\n&wifi1 {\n\tstatus = \"okay\";\n\tnvmem-cell-names = \"pre-calibration\";\n\tnvmem-cells = <&precal_art_5000>;\n\tqcom,ath10k-calibration-variant = \"Qxwlan-E2600AC-C1\";\n};\n"
  },
  {
    "path": "target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-e2600ac-c2.dts",
    "content": "/* SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n *\n * Copyright (c) 2018 Peng Zhang <sd20@qxwlan.com>\n *\n */\n\n#include \"qcom-ipq4019-e2600ac.dtsi\"\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"Qxwlan E2600AC c2\";\n\tcompatible = \"qxwlan,e2600ac-c2\";\n};\n\n&blsp1_spi1 {\n\tpinctrl-0 = <&spi_0_pins>;\n\tpinctrl-names = \"default\";\n\tstatus = \"okay\";\n\tcs-gpios = <&tlmm 12 GPIO_ACTIVE_LOW>;\n\n\tflash@0 {\n\t\treg = <0>;\n\t\tcompatible = \"jedec,spi-nor\";\n\t\tspi-max-frequency = <24000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"0:SBL1\";\n\t\t\t\treg = <0x0 0x40000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"0:MIBIB\";\n\t\t\t\treg = <0x40000 0x20000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@60000 {\n\t\t\t\tlabel = \"0:QSEE\";\n\t\t\t\treg = <0x60000 0x60000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@c0000 {\n\t\t\t\tlabel = \"0:CDT\";\n\t\t\t\treg = <0xc0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@d0000 {\n\t\t\t\tlabel = \"0:DDRPARAMS\";\n\t\t\t\treg = <0xd0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@e0000 {\n\t\t\t\tlabel = \"0:APPSBLENV\";\n\t\t\t\treg = <0xe0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@f0000 {\n\t\t\t\tlabel = \"0:APPSBL\";\n\t\t\t\treg = <0xf0000 0x80000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@170000 {\n\t\t\t\tlabel = \"0:ART\";\n\t\t\t\treg = <0x170000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t\tcompatible = \"nvmem-cells\";\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\n\t\t\t\tprecal_art_1000: precal@1000 {\n\t\t\t\t\treg = <0x1000 0x2f20>;\n\t\t\t\t};\n\n\t\t\t\tprecal_art_5000: precal@5000 {\n\t\t\t\t\treg = <0x5000 0x2f20>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t};\n};\n\n&nand {\n\tpinctrl-0 = <&nand_pins>;\n\tpinctrl-names = \"default\";\n\tstatus = \"okay\";\n\n\tnand@0 {\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"ubi\";\n\t\t\t\treg = <0x00000000 0x04000000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&tlmm {\n\tnand_pins: nand-pins {\n\n\t\tpullups {\n\t\t\tpins = \"gpio53\", \"gpio58\", \"gpio59\";\n\t\t\tfunction = \"qpic\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tpulldowns {\n\t\t\tpins = \"gpio54\", \"gpio55\", \"gpio56\",\n\t\t\t\t\"gpio57\", \"gpio60\", \"gpio61\",\n\t\t\t\t\"gpio62\", \"gpio63\", \"gpio64\",\n\t\t\t\t\"gpio65\", \"gpio66\", \"gpio67\",\n\t\t\t\t\"gpio68\", \"gpio69\";\n\t\t\tfunction = \"qpic\";\n\t\t\tbias-pull-down;\n\t\t};\n\t};\n};\n\n&wifi0 {\n\tstatus = \"okay\";\n\tnvmem-cell-names = \"pre-calibration\";\n\tnvmem-cells = <&precal_art_1000>;\n\tqcom,ath10k-calibration-variant = \"Qxwlan-E2600AC-C2\";\n};\n\n&wifi1 {\n\tstatus = \"okay\";\n\tnvmem-cell-names = \"pre-calibration\";\n\tnvmem-cells = <&precal_art_5000>;\n\tqcom,ath10k-calibration-variant = \"Qxwlan-E2600AC-C2\";\n};\n"
  },
  {
    "path": "target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-e2600ac.dtsi",
    "content": "/* SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n *\n * Copyright (c) 2018 Peng Zhang <sd20@qxwlan.com>\n *\n */\n\n#include \"qcom-ipq4019.dtsi\"\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/soc/qcom,tcsr.h>\n\n/ {\n\n\tmodel = \"Qxwlan E2600AC\";\n\tcompatible = \"qcom,ipq4019\";\n\n\tmemory {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x80000000 0x10000000>; /* 256MB */\n\t};\n\n\tsoc {\n\t\trng@22000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tmdio@90000 {\n\t\t\tstatus = \"okay\";\n\t\t\tpinctrl-0 = <&mdio_pins>;\n\t\t\tpinctrl-names = \"default\";\n\t\t};\n\n\t\tess-psgmii@98000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\ttcsr@1949000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1949000 0x100>;\n\t\t\tqcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;\n\t\t};\n\n\t\ttcsr@194b000 {\n\t\t\t/* select hostmode */\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x194b000 0x100>;\n\t\t\tqcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tess_tcsr@1953000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1953000 0x1000>;\n\t\t\tqcom,ess-interface-select = <TCSR_ESS_PSGMII>;\n\t\t};\n\n\t\ttcsr@1957000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1957000 0x100>;\n\t\t\tqcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;\n\t\t};\n\n\t\tusb2: usb2@60f8800 {\n\t\t\tstatus = \"okay\";\n\n\t\t\tdwc3@6000000 {\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\n\t\t\t\tusb2_port1: port@1 {\n\t\t\t\t\treg = <1>;\n\t\t\t\t\t#trigger-source-cells = <0>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tserial@78af000 {\n\t\t\tpinctrl-0 = <&serial_0_pins>;\n\t\t\tpinctrl-names = \"default\";\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tserial@78b0000 {\n\t\t\tpinctrl-0 = <&serial_1_pins>;\n\t\t\tpinctrl-names = \"default\";\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\ti2c@78b7000 { /* BLSP1 QUP2 */\n\t\t\tpinctrl-0 = <&i2c_0_pins>;\n\t\t\tpinctrl-names = \"default\";\n\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tusb3: usb3@8af8800 {\n\t\t\tstatus = \"okay\";\n\n\t\t\tdwc3@8a00000 {\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\n\t\t\t\tusb3_port1: port@1 {\n\t\t\t\t\treg = <1>;\n\t\t\t\t\t#trigger-source-cells = <0>;\n\t\t\t\t};\n\n\t\t\t\tusb3_port2: port@2 {\n\t\t\t\t\treg = <2>;\n\t\t\t\t\t#trigger-source-cells = <0>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tcrypto@8e3a000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\twatchdog@b017000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tess-switch@c000000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tedma@c080000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tleds {\n\t\t\tcompatible = \"gpio-leds\";\n\n\t\t\tled1 {\n\t\t\t\tlabel = \"green:wlan0\";\n\t\t\t\tgpios = <&tlmm 50 GPIO_ACTIVE_LOW>;\n\t\t\t};\n\n\t\t\tled2 {\n\t\t\t\tlabel = \"green:wlan1\";\n\t\t\t\tgpios = <&tlmm 36 GPIO_ACTIVE_LOW>;\n\t\t\t};\n\n\t\t\tled3 {\n\t\t\t\tlabel = \"green:usb\";\n\t\t\t\tgpios = <&tlmm 32 GPIO_ACTIVE_LOW>;\n\t\t\t\ttrigger-sources = <&usb2_port1>, <&usb3_port1>, <&usb3_port2>;\n\t\t\t\tlinux,default-trigger = \"usbport\";\n\t\t\t};\n\n\t\t\tled4 {\n\t\t\t\tlabel = \"green:ctrl1\";\n\t\t\t\tgpios = <&tlmm 51 GPIO_ACTIVE_LOW>;\n\t\t\t};\n\n\t\t\tled5 {\n\t\t\t\tlabel = \"green:ctrl2\";\n\t\t\t\tgpios = <&tlmm 30 GPIO_ACTIVE_LOW>;\n\t\t\t};\n\n\t\t\tled6 {\n\t\t\t\tlabel = \"green:ctrl3\";\n\t\t\t\tgpios = <&tlmm 31 GPIO_ACTIVE_LOW>;\n\t\t\t};\n\t\t};\n\n\t\tkeys {\n\t\t\tcompatible = \"gpio-keys\";\n\n\t\t\treset {\n\t\t\t\tlabel = \"reset\";\n\t\t\t\tgpios = <&tlmm 18 GPIO_ACTIVE_LOW>;\n\t\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&blsp_dma {\n\tstatus = \"okay\";\n};\n\n&cryptobam {\n\tstatus = \"okay\";\n};\n\n&qpic_bam {\n\tstatus = \"okay\";\n};\n\n&tlmm {\n\ti2c_0_pins: i2c-0-pinmux {\n\t\tmux {\n\t\t\tpins = \"gpio20\", \"gpio21\";\n\t\t\tfunction = \"blsp_i2c0\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tmdio_pins: mdio_pinmux {\n\t\tmux_1 {\n\t\t\tpins = \"gpio6\";\n\t\t\tfunction = \"mdio\";\n\t\t\tbias-pull-up;\n\t\t};\n\t\tmux_2 {\n\t\t\tpins = \"gpio7\";\n\t\t\tfunction = \"mdc\";\n\t\t\tbias-pull-up;\n\t\t};\n\t};\n\n\tserial_0_pins: serial0-pinmux {\n\t\tmux {\n\t\t\tpins = \"gpio16\", \"gpio17\";\n\t\t\tfunction = \"blsp_uart0\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tserial_1_pins: serial1_pinmux {\n\t\tmux {\n\t\t\tpins = \"gpio8\", \"gpio9\";\n\t\t\tfunction = \"blsp_uart1\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tspi_0_pins: spi_0_pinmux {\n\t\tpinmux {\n\t\t\tfunction = \"blsp_spi0\";\n\t\t\tpins = \"gpio13\", \"gpio14\", \"gpio15\";\n\t\t\tdrive-strength = <12>;\n\t\t\tbias-disable;\n\t\t};\n\t\tpinmux_cs {\n\t\t\tfunction = \"gpio\";\n\t\t\tpins = \"gpio12\";\n\t\t\tdrive-strength = <2>;\n\t\t\tbias-disable;\n\t\t\toutput-high;\n\t\t};\n\t};\n};\n\n&usb3_ss_phy {\n\tstatus = \"okay\";\n};\n\n&usb3_hs_phy {\n\tstatus = \"okay\";\n};\n\n&usb2_hs_phy {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-ea8300.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qcom-ipq4019-xx8300.dtsi\"\n\n/ {\n\tmodel = \"Linksys EA8300 (Dallas)\";\n\tcompatible = \"linksys,ea8300\", \"qcom,ipq4019\";\n\n\n\taliases {\n\t\tled-boot = &led_wps_amber;\n\t\tled-failsafe = &led_wps;\n\t\tled-running = &led_linksys;\n\t\tled-upgrade = &led_world;\n\t\tserial0 = &blsp1_uart1;\n\t};\n\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\t// Retain node names from running OEM on EA8300\n\n\t\t// Front panel LEDs, top to bottom\n\n\t\tled_plug: diag {\n\t\t\tlabel = \"amber:plug\";\n\t\t\tgpios = <&tlmm 47 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tled_world: internet {\n\t\t\tlabel = \"amber:world\";\n\t\t\tgpios = <&tlmm 49 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tled_wps: wps {\n\t\t\tlabel = \"white:wps\";\n\t\t\tgpios = <&tlmm 46 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tled_wps_amber: wps_amber {\n\t\t\tlabel = \"amber:wps\";\n\t\t\tgpios = <&tlmm 22 GPIO_ACTIVE_HIGH>;\n\t\t\tpanic-indicator;\n\t\t};\n\n\t\tled_linksys: pwr {\n\t\t\tlabel = \"white:linksys\";\n\t\t\tgpios = <&tlmm 45 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\t// On back panel, above USB socket\n\n\t\tled_usb: usb {\n\t\t\tlabel = \"green:usb\";\n\t\t\tgpios = <&tlmm 61 GPIO_ACTIVE_LOW>;\n\t\t\ttrigger-sources = <&usb3_port1>, <&usb3_port2>,\n\t\t\t\t\t  <&usb2_port1>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&tlmm 50 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tgpios = <&tlmm 18 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&wifi0 {\n\tstatus = \"okay\";\n\tqcom,ath10k-calibration-variant = \"linksys-ea8300-fcc\";\n};\n\n&wifi1 {\n\tstatus = \"okay\";\n\tieee80211-freq-limit = <5170000 5330000>;\n\tqcom,ath10k-calibration-variant = \"linksys-ea8300-fcc\";\n};\n\n&wifi2 {\n\tstatus = \"okay\";\n\tieee80211-freq-limit = <5490000 5835000>;\n\tqcom,ath10k-calibration-variant = \"linksys-ea8300-fcc\";\n};\n"
  },
  {
    "path": "target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-eap2200.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qcom-ipq4019.dtsi\"\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"EnGenius EAP2200\";\n\tcompatible = \"engenius,eap2200\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&tlmm 18 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"amber:power\";\n\t\t\tgpios = <&tlmm 43 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan1 {\n\t\t\tlabel = \"blue:lan1\";\n\t\t\tgpios = <&tlmm 44 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan2 {\n\t\t\tlabel = \"blue:lan2\";\n\t\t\tgpios = <&tlmm 45 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan2g {\n\t\t\tlabel = \"blue:wlan2g\";\n\t\t\tgpios = <&tlmm 46 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\twlan5g {\n\t\t\tlabel = \"yellow:wlan5g\";\n\t\t\tgpios = <&tlmm 47 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\n\t\twlan5g2 {\n\t\t\tlabel = \"yellow:wlan5g2\";\n\t\t\tgpios = <&tlmm 48 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy2tpt\";\n\t\t};\n\n\t\tmode {\n\t\t\tlabel = \"blue:mode\";\n\t\t\tgpios = <&tlmm 50 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tsoc {\n\t\trng@22000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tmdio@90000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tess-psgmii@98000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tcrypto@8e3a000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\twatchdog@b017000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tess-switch@c000000 {\n\t\t\tstatus = \"okay\";\n\t\t\tswitch_lan_bmp = <0x10>;\n\t\t};\n\n\t\tedma@c080000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\t};\n};\n\n&blsp_dma {\n\tstatus = \"okay\";\n};\n\n&blsp1_spi1 {\n\tpinctrl-0 = <&spi_0_pins>;\n\tpinctrl-names = \"default\";\n\tstatus = \"okay\";\n\tcs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;\n\n\tflash@0 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <24000000>;\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition0@0 {\n\t\t\t\tlabel = \"0:SBL1\";\n\t\t\t\treg = <0x00000000 0x00040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition1@40000 {\n\t\t\t\tlabel = \"0:MIBIB\";\n\t\t\t\treg = <0x00040000 0x00020000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition2@60000 {\n\t\t\t\tlabel = \"0:QSEE\";\n\t\t\t\treg = <0x00060000 0x00060000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition3@c0000 {\n\t\t\t\tlabel = \"0:CDT\";\n\t\t\t\treg = <0x000c0000 0x00010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition4@d0000 {\n\t\t\t\tlabel = \"0:DDRPARAMS\";\n\t\t\t\treg = <0x000d0000 0x00010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition5@e0000 {\n\t\t\t\tlabel = \"0:APPSBLENV\";\n\t\t\t\treg = <0x000e0000 0x00010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition6@f0000 {\n\t\t\t\tlabel = \"0:APPSBL\";\n\t\t\t\treg = <0x000f0000 0x00080000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition7@170000 {\n\t\t\t\tlabel = \"0:ART\";\n\t\t\t\treg = <0x00170000 0x00010000>;\n\t\t\t\tread-only;\n\t\t\t\tcompatible = \"nvmem-cells\";\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\n\t\t\t\tprecal_art_1000: precal@1000 {\n\t\t\t\t\treg = <0x1000 0x2f20>;\n\t\t\t\t};\n\n\t\t\t\tprecal_art_5000: precal@5000 {\n\t\t\t\t\treg = <0x5000 0x2f20>;\n\t\t\t\t};\n\n\t\t\t\tprecal_art_9000: precal@9000 {\n\t\t\t\t\treg = <0x9000 0x2f20>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t};\n};\n\n&blsp1_uart1 {\n\tpinctrl-0 = <&serial_0_pins>;\n\tpinctrl-names = \"default\";\n\tstatus = \"okay\";\n};\n\n&cryptobam {\n\tstatus = \"okay\";\n};\n\n&gmac0 {\n\tvlan_tag = <1 0x10>;\n};\n\n&nand {\n\tpinctrl-0 = <&nand_pins>;\n\tpinctrl-names = \"default\";\n\tstatus = \"okay\";\n\n\tnand@0 {\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"rootfs1\";\n\t\t\t\treg = <0x00000000 0x04000000>;\n\t\t\t};\n\t\t\tpartition@40000000 {\n\t\t\t\tlabel = \"ubi\";\n\t\t\t\treg = <0x04000000 0x04000000>;\n\t\t\t};\n\n\t\t};\n\t};\n};\n\n&pcie0 {\n\tstatus = \"okay\";\n\tperst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;\n\twake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>;\n\n\tbridge@0,0 {\n\t\treg = <0x00000000 0 0 0 0>;\n\t\t#address-cells = <3>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\twifi2: wifi@1,0 {\n\t\t\tcompatible = \"qcom,ath10k\";\n\t\t\treg = <0x00010000 0 0 0 0>;\n\t\t\tnvmem-cell-names = \"pre-calibration\";\n\t\t\tnvmem-cells = <&precal_art_9000>;\n\t\t\tieee80211-freq-limit = <5470000 5875000>;\n\t\t\tqcom,ath10k-calibration-variant = \"EnGenius-EAP2200\";\n\t\t};\n\t};\n};\n\n&qpic_bam {\n\tstatus = \"okay\";\n};\n\n&tlmm {\n\tnand_pins: nand_pins {\n\t\tpullups {\n\t\t\tpins = \"gpio53\", \"gpio58\", \"gpio59\";\n\t\t\tfunction = \"qpic\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tpulldowns {\n\t\t\tpins = \"gpio54\", \"gpio55\", \"gpio56\",\n\t\t\t\t\"gpio57\", \"gpio60\", \"gpio61\",\n\t\t\t\t\"gpio62\", \"gpio63\", \"gpio64\",\n\t\t\t\t\"gpio65\", \"gpio66\", \"gpio67\",\n\t\t\t\t\"gpio68\", \"gpio69\";\n\t\t\tfunction = \"qpic\";\n\t\t\tbias-pull-down;\n\t\t};\n\t};\n\n\tserial_0_pins: serial_pinmux {\n\t\tmux {\n\t\t\tpins = \"gpio16\", \"gpio17\";\n\t\t\tfunction = \"blsp_uart0\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tspi_0_pins: spi_0_pinmux {\n\t\tpinmux {\n\t\t\tfunction = \"blsp_spi0\";\n\t\t\tpins = \"gpio13\", \"gpio14\", \"gpio15\";\n\t\t\tdrive-strength = <12>;\n\t\t\tbias-disable;\n\t\t};\n\t\tpinmux_cs {\n\t\t\tfunction = \"gpio\";\n\t\t\tpins = \"gpio12\";\n\t\t\tdrive-strength = <2>;\n\t\t\tbias-disable;\n\t\t\toutput-high;\n\t\t};\n\t};\n};\n\n&wifi0 {\n\tstatus = \"okay\";\n\tnvmem-cell-names = \"pre-calibration\";\n\tnvmem-cells = <&precal_art_1000>;\n\tqcom,ath10k-calibration-variant = \"EnGenius-EAP2200\";\n};\n\n&wifi1 {\n\tstatus = \"okay\";\n\tieee80211-freq-limit = <5170000 5350000>;\n\tnvmem-cell-names = \"pre-calibration\";\n\tnvmem-cells = <&precal_art_5000>;\n\tqcom,ath10k-calibration-variant = \"EnGenius-EAP2200\";\n};\n"
  },
  {
    "path": "target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-fritzbox-7530.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qcom-ipq4019.dtsi\"\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/soc/qcom,tcsr.h>\n\n/ {\n\tmodel = \"AVM FRITZ!Box 7530\";\n\tcompatible = \"avm,fritzbox-7530\";\n\n\taliases {\n\t\tled-boot = &power_green;\n\t\tled-failsafe = &info_red;\n\t\tled-running = &power_green;\n\t\tled-upgrade = &info_green;\n\t};\n\n\tsoc {\n\t\trng@22000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tmdio@90000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tess-psgmii@98000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\ttcsr@1949000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1949000 0x100>;\n\t\t\tqcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;\n\t\t};\n\n\t\ttcsr@194b000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x194b000 0x100>;\n\t\t\tqcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;\n\t\t};\n\n\t\tess_tcsr@1953000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1953000 0x1000>;\n\t\t\tqcom,ess-interface-select = <TCSR_ESS_PSGMII>;\n\t\t};\n\n\t\ttcsr@1957000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1957000 0x100>;\n\t\t\tqcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;\n\t\t};\n\n\t\tusb3@8af8800 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tcrypto@8e3a000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\twatchdog@b017000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tess-switch@c000000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tedma@c080000 {\n\t\t\tstatus = \"okay\";\n\t\t\tqcom,num_gmac = <1>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\twlan {\n\t\t\tlabel = \"wlan\";\n\t\t\tgpios = <&tlmm 42 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RFKILL>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&tlmm 41 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\n\t\tdect {\n\t\t\tlabel = \"dect\";\n\t\t\tgpios = <&tlmm 43 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_PHONE>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tinfo_red: info_red {\n\t\t\tlabel = \"red:info\";\n\t\t\tgpios = <&tlmm 32 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tinfo_green: info {\n\t\t\tlabel = \"green:info\";\n\t\t\tgpios = <&tlmm 33 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan {\n\t\t\tlabel = \"green:wlan\";\n\t\t\tgpios = <&tlmm 34 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tfon {\n\t\t\tlabel = \"green:fon\";\n\t\t\tgpios = <&tlmm 35 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tpower_green: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&tlmm 39 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&tlmm 45 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&tlmm {\n\tserial_0_pins: serial_pinmux {\n\t\tmux {\n\t\t\tpins = \"gpio16\", \"gpio17\";\n\t\t\tfunction = \"blsp_uart0\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tnand_pins: nand_pins {\n\t\tpullups {\n\t\t\tpins = \"gpio53\", \"gpio58\", \"gpio59\";\n\t\t\tfunction = \"qpic\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tpulldowns {\n\t\t\tpins = \"gpio54\", \"gpio55\", \"gpio56\",\n\t\t\t\t\"gpio57\", \"gpio60\", \"gpio61\",\n\t\t\t\t\"gpio62\", \"gpio63\", \"gpio64\",\n\t\t\t\t\"gpio65\", \"gpio66\", \"gpio67\",\n\t\t\t\t\"gpio68\", \"gpio69\";\n\t\t\tfunction = \"qpic\";\n\t\t\tbias-pull-down;\n\t\t};\n\t};\n\n\tusb-power {\n\t\tline-name = \"enable USB3 power\";\n\t\tgpios = <49 GPIO_ACTIVE_HIGH>;\n\t\tgpio-hog;\n\t\toutput-high;\n\t};\n};\n\n&nand {\n\tpinctrl-0 = <&nand_pins>;\n\tpinctrl-names = \"default\";\n\tstatus = \"okay\";\n\n\tnand@0 {\n\t\t/delete-property/ nand-ecc-strength;\n\t\t/delete-property/ nand-ecc-step-size;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"SBL1\";\n\t\t\t\treg = <0x000000 0x80000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@80000 {\n\t\t\t\tlabel = \"MIBIB\";\n\t\t\t\treg = <0x080000 0x80000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@100000 {\n\t\t\t\tlabel = \"QSEE\";\n\t\t\t\treg = <0x100000 0x80000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@180000 {\n\t\t\t\tlabel = \"CDT\";\n\t\t\t\treg = <0x180000 0x40000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@1c0000 {\n\t\t\t\tlabel = \"QSEE_B\";\n\t\t\t\treg = <0x1c0000 0x80000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@240000 {\n\t\t\t\tlabel = \"urlader0\";\n\t\t\t\treg = <0x240000 0x40000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@280000 {\n\t\t\t\tlabel = \"urlader1\";\n\t\t\t\treg = <0x280000 0x40000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@2c0000 {\n\t\t\t\tlabel = \"nand-tffs\";\n\t\t\t\treg = <0x2c0000 0x840000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@b00000 {\n\t\t\t\t/* 'kernel1' in AVM firmware */\n\t\t\t\tlabel = \"uboot0\";\n\t\t\t\treg = <0xb00000 0x400000>;\n\t\t\t};\n\n\t\t\tpartition@f00000 {\n\t\t\t\t/* 'kernel2' in AVM firmware */\n\t\t\t\tlabel = \"uboot1\";\n\t\t\t\treg = <0xf00000 0x400000>;\n\t\t\t};\n\n\t\t\tpartition@1300000 {\n\t\t\t\tlabel = \"ubi\";\n\t\t\t\treg = <0x1300000 0x6d00000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&cryptobam {\n\tstatus = \"okay\";\n};\n\n&blsp_dma {\n\tstatus = \"okay\";\n};\n\n&blsp1_uart1 {\n\tpinctrl-0 = <&serial_0_pins>;\n\tpinctrl-names = \"default\";\n\tstatus = \"okay\";\n};\n\n&usb3_ss_phy {\n\tstatus = \"okay\";\n};\n\n&usb3_hs_phy {\n\tstatus = \"okay\";\n};\n\n&qpic_bam {\n\tstatus = \"okay\";\n};\n\n&wifi0 {\n\tstatus = \"okay\";\n\tqcom,ath10k-calibration-variant = \"AVM-FRITZBox-7530\";\n};\n\n&wifi1 {\n\tstatus = \"okay\";\n\tqcom,ath10k-calibration-variant = \"AVM-FRITZBox-7530\";\n};\n\n&pcie0 {\n\tstatus = \"okay\";\n\n\tperst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;\n\twake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>;\n\n\tbridge@0,0 {\n\t\treg = <0x00000000 0 0 0 0>;\n\t\t#address-cells = <3>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\tdsl@1,0 {\n\t\t\tcompatible = \"intel,vrx518\";\n\t\t\tstatus = \"okay\";\n\t\t\treg = <0x00010000 0 0 0 0>;\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-fritzrepeater-1200.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qcom-ipq4019.dtsi\"\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/soc/qcom,tcsr.h>\n\n/ {\n\tmodel = \"AVM FRITZ!Repeater 1200\";\n\tcompatible = \"avm,fritzrepeater-1200\";\n\n\taliases {\n\t\tled-boot = &power_green;\n\t\tled-failsafe = &power_red;\n\t\tled-running = &power_green;\n\t\tled-upgrade = &power_red;\n\t\tlabel-mac-device = &wifi0;\n\t};\n\n\tsoc {\n\t\trng@22000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tmdio@90000 {\n\t\t\tstatus = \"okay\";\n\t\t\tpinctrl-0 = <&mdio_pins>;\n\t\t\tpinctrl-names = \"default\";\n\n\t\t\t/delete-node/ ethernet-phy@1;\n\t\t\t/delete-node/ ethernet-phy@2;\n\t\t\t/delete-node/ ethernet-phy@3;\n\t\t\t/delete-node/ ethernet-phy@4;\n\t\t\t/delete-node/ psgmii-phy@5;\n\t\t};\n\n\t\ttcsr@1949000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1949000 0x100>;\n\t\t\tqcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;\n\t\t};\n\n\t\tess_tcsr@1953000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1953000 0x1000>;\n\t\t\tqcom,ess-interface-select = <TCSR_ESS_PSGMII_RGMII5>;\n\t\t};\n\n\t\ttcsr@1957000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1957000 0x100>;\n\t\t\tqcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;\n\t\t};\n\n\t\tcrypto@8e3a000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\twatchdog@b017000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tess-switch@c000000 {\n\t\t\tswitch_mac_mode = <0x3>; /* mac mode for RGMII RMII */\n\t\t\tswitch_lan_bmp = <0x0>; /* lan port bitmap */\n\t\t\tswitch_wan_bmp = <0x10>; /* wan port bitmap */\n\t\t};\n\n\t\tedma@c080000 {\n\t\t\tstatus = \"okay\";\n\t\t\tphy-mode = \"rgmii-id\";\n\t\t\tqcom,num_gmac = <1>;\n\t\t\tqcom,single-phy;\n\t\t};\n\t};\n\n\tkey {\n\t\tcompatible = \"gpio-keys\";\n\n\t\twps {\n\t\t\tlabel = \"WPS button\";\n\t\t\tgpios = <&tlmm 10 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tpower_red: power_red {\n\t\t\tlabel = \"red:power\";\n\t\t\tgpios = <&tlmm 50 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tpower_green: power_green {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&tlmm 45 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tpower_yellow {\n\t\t\tlabel = \"yellow:power\";\n\t\t\tgpios = <&tlmm 49 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&tlmm {\n\tserial_0_pins: serial_pinmux {\n\t\tmux {\n\t\t\tpins = \"gpio16\", \"gpio17\";\n\t\t\tfunction = \"blsp_uart0\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tnand_pins: nand_pins {\n\t\tpullups {\n\t\t\tpins = \"gpio53\", \"gpio58\", \"gpio59\";\n\t\t\tfunction = \"qpic\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tpulldowns {\n\t\t\tpins = \"gpio54\", \"gpio55\", \"gpio56\",\n\t\t\t\t\"gpio57\", \"gpio60\", \"gpio61\",\n\t\t\t\t\"gpio62\", \"gpio63\", \"gpio64\",\n\t\t\t\t\"gpio65\", \"gpio66\", \"gpio67\",\n\t\t\t\t\"gpio68\", \"gpio69\";\n\t\t\tfunction = \"qpic\";\n\t\t\tbias-pull-down;\n\t\t};\n\t};\n\n\tmdio_pins: mdio_pinmux {\n\t\tmux_1 {\n\t\t\tpins = \"gpio6\";\n\t\t\tfunction = \"mdio\";\n\t\t\tbias-pull-up;\n\t\t};\n\t\tmux_2 {\n\t\t\tpins = \"gpio7\";\n\t\t\tfunction = \"mdc\";\n\t\t\tbias-pull-up;\n\t\t};\n\t};\n\n\tphy-reset {\n\t\tline-name = \"PHY-reset\";\n\t\tgpios = <19 GPIO_ACTIVE_HIGH>;\n\t\tgpio-hog;\n\t\toutput-high;\n\t};\n\n\tphy-reset-2 {\n\t\tline-name = \"PHY-reset-2\";\n\t\tgpios = <47 GPIO_ACTIVE_HIGH>;\n\t\tgpio-hog;\n\t\toutput-high;\n\t};\n};\n\n&nand {\n\tpinctrl-0 = <&nand_pins>;\n\tpinctrl-names = \"default\";\n\tstatus = \"okay\";\n\n\tnand@0 {\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"SBL1\";\n\t\t\t\treg = <0x0 0x80000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@80000 {\n\t\t\t\tlabel = \"MIBIB\";\n\t\t\t\treg = <0x80000 0x80000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@100000 {\n\t\t\t\tlabel = \"QSEE\";\n\t\t\t\treg = <0x100000 0x80000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@180000 {\n\t\t\t\tlabel = \"CDT\";\n\t\t\t\treg = <0x180000 0x40000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@1c0000 {\n\t\t\t\tlabel = \"QSEE_B\";\n\t\t\t\treg = <0x1c0000 0x80000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@240000 {\n\t\t\t\tlabel = \"urlader0\";\n\t\t\t\treg = <0x240000 0x40000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@280000 {\n\t\t\t\tlabel = \"urlader1\";\n\t\t\t\treg = <0x280000 0x40000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@2c0000 {\n\t\t\t\tlabel = \"nand-tffs\";\n\t\t\t\treg = <0x2c0000 0x840000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@b00000 {\n\t\t\t\t/* 'kernel1' in AVM firmware */\n\t\t\t\tlabel = \"uboot0\";\n\t\t\t\treg = <0xb00000 0x400000>;\n\t\t\t};\n\n\t\t\tpartition@f00000 {\n\t\t\t\t/* 'kernel2' in AVM firmware */\n\t\t\t\tlabel = \"uboot1\";\n\t\t\t\treg = <0xf00000 0x400000>;\n\t\t\t};\n\n\t\t\tpartition@1300000 {\n\t\t\t\tlabel = \"ubi\";\n\t\t\t\treg = <0x1300000 0x6d00000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&cryptobam {\n\tstatus = \"okay\";\n};\n\n&blsp_dma {\n\tstatus = \"okay\";\n};\n\n&blsp1_uart1 {\n\tpinctrl-0 = <&serial_0_pins>;\n\tpinctrl-names = \"default\";\n\tstatus = \"okay\";\n};\n\n&qpic_bam {\n\tstatus = \"okay\";\n};\n\n&wifi0 {\n\tstatus = \"okay\";\n\tqcom,ath10k-calibration-variant = \"AVM-FRITZRepeater-1200\";\n};\n\n&wifi1 {\n\tstatus = \"okay\";\n\tqcom,ath10k-calibration-variant = \"AVM-FRITZRepeater-1200\";\n};\n\n&gmac0 {\n\tqcom,phy_mdio_addr = <0>;\n\tqcom,poll_required = <1>;\n\tvlan_tag = <0 0x20>;\n};\n"
  },
  {
    "path": "target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-fritzrepeater-3000.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qcom-ipq4019.dtsi\"\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/soc/qcom,tcsr.h>\n\n/ {\n\tmodel = \"AVM FRITZ!Repeater 3000\";\n\tcompatible = \"avm,fritzrepeater-3000\";\n\n\taliases {\n\t\tled-boot = &power_led;\n\t\tled-failsafe = &power_led;\n\t\tled-running = &power_led;\n\t\tled-upgrade = &power_led;\n\t};\n\n\tsoc {\n\t\trng@22000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tmdio@90000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tess-psgmii@98000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\ttcsr@1949000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1949000 0x100>;\n\t\t\tqcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;\n\t\t};\n\n\t\tess_tcsr@1953000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1953000 0x1000>;\n\t\t\tqcom,ess-interface-select = <TCSR_ESS_PSGMII>;\n\t\t};\n\n\t\ttcsr@1957000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1957000 0x100>;\n\t\t\tqcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;\n\t\t};\n\n\t\tcrypto@8e3a000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\twatchdog@b017000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tess-switch@c000000 {\n\t\t\tstatus = \"okay\";\n\n\t\t\tswitch_lan_bmp = <0x30>;\n\t\t\tswitch_wan_bmp = <0x02>;\n\t\t};\n\n\t\tedma@c080000 {\n\t\t\tstatus = \"okay\";\n\t\t\tqcom,num_gmac = <1>;\n\t\t};\n\t};\n\n\tkey {\n\t\tcompatible = \"gpio-keys\";\n\n\t\tconnect {\n\t\t\tlabel = \"Connect\";\n\t\t\tgpios = <&tlmm 10 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tconnect_red {\n\t\t\tlabel = \"red:connect\";\n\t\t\tgpios = <&tlmm 30 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tconnect_green {\n\t\t\tlabel = \"green:connect\";\n\t\t\tgpios = <&tlmm 31 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tconnect_blue {\n\t\t\tlabel = \"blue:connect\";\n\t\t\tgpios = <&tlmm 32 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tpower_led: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&tlmm 33 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&tlmm {\n\tserial_0_pins: serial_pinmux {\n\t\tmux {\n\t\t\tpins = \"gpio16\", \"gpio17\";\n\t\t\tfunction = \"blsp_uart0\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tnand_pins: nand_pins {\n\t\tpullups {\n\t\t\tpins = \"gpio53\", \"gpio58\", \"gpio59\";\n\t\t\tfunction = \"qpic\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tpulldowns {\n\t\t\tpins = \"gpio54\", \"gpio55\", \"gpio56\",\n\t\t\t\t\"gpio57\", \"gpio60\", \"gpio61\",\n\t\t\t\t\"gpio62\", \"gpio63\", \"gpio64\",\n\t\t\t\t\"gpio65\", \"gpio66\", \"gpio67\",\n\t\t\t\t\"gpio68\", \"gpio69\";\n\t\t\tfunction = \"qpic\";\n\t\t\tbias-pull-down;\n\t\t};\n\t};\n};\n\n&nand {\n\tpinctrl-0 = <&nand_pins>;\n\tpinctrl-names = \"default\";\n\tstatus = \"okay\";\n\n\tnand@0 {\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"SBL1\";\n\t\t\t\treg = <0x000000 0x80000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@80000 {\n\t\t\t\tlabel = \"MIBIB\";\n\t\t\t\treg = <0x080000 0x80000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@100000 {\n\t\t\t\tlabel = \"QSEE\";\n\t\t\t\treg = <0x100000 0x80000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@180000 {\n\t\t\t\tlabel = \"CDT\";\n\t\t\t\treg = <0x180000 0x40000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@1c0000 {\n\t\t\t\tlabel = \"QSEE_B\";\n\t\t\t\treg = <0x1c0000 0x80000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@240000 {\n\t\t\t\tlabel = \"urlader0\";\n\t\t\t\treg = <0x240000 0x40000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@280000 {\n\t\t\t\tlabel = \"urlader1\";\n\t\t\t\treg = <0x280000 0x40000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@2c0000 {\n\t\t\t\tlabel = \"nand-tffs\";\n\t\t\t\treg = <0x2c0000 0x840000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@b00000 {\n\t\t\t\t/* 'kernel1' in AVM firmware */\n\t\t\t\tlabel = \"uboot0\";\n\t\t\t\treg = <0xb00000 0x400000>;\n\t\t\t};\n\n\t\t\tpartition@f00000 {\n\t\t\t\t/* 'kernel2' in AVM firmware */\n\t\t\t\tlabel = \"uboot1\";\n\t\t\t\treg = <0xf00000 0x400000>;\n\t\t\t};\n\n\t\t\tpartition@1300000 {\n\t\t\t\tlabel = \"ubi\";\n\t\t\t\treg = <0x1300000 0x6d00000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&gmac0 {\n\tvlan_tag = <1 0x30>;\n};\n\n&cryptobam {\n\tstatus = \"okay\";\n};\n\n&blsp_dma {\n\tstatus = \"okay\";\n};\n\n&blsp1_uart1 {\n\tpinctrl-0 = <&serial_0_pins>;\n\tpinctrl-names = \"default\";\n\tstatus = \"okay\";\n};\n\n&qpic_bam {\n\tstatus = \"okay\";\n};\n\n&wifi0 {\n\tstatus = \"okay\";\n\t/* BDFs are identical for the FRITZ!Box 7530 and the FRITZ!Repeater 3000 */\n\tqcom,ath10k-calibration-variant = \"AVM-FRITZRepeater-3000\";\n};\n\n&wifi1 {\n\tstatus = \"okay\";\n\tieee80211-freq-limit = <5170000 5350000>;\n\t/* BDFs are identical for the FRITZ!Box 7530 and the FRITZ!Repeater 3000 */\n\tqcom,ath10k-calibration-variant = \"AVM-FRITZRepeater-3000\";\n};\n\n&pcie0 {\n\tstatus = \"okay\";\n\n\tperst-gpio = <&tlmm 35 GPIO_ACTIVE_LOW>;\n\twake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>;\n\n\tbridge@0,0 {\n\t\treg = <0x00000000 0 0 0 0>;\n\t\t#address-cells = <3>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\twifi@1,0 {\n\t\t\t/* QCA9984 */\n\t\t\tcompatible = \"qcom,ath10k\";\n\t\t\tstatus = \"okay\";\n\t\t\treg = <0x00010000 0 0 0 0>;\n\t\t\tieee80211-freq-limit = <5470000 5875000>;\n\t\t\t/* Uses the reference BDF */\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-gl-b2200.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-only OR MIT\n\n#include \"qcom-ipq4019.dtsi\"\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/soc/qcom,tcsr.h>\n\n/ {\n\tmodel = \"GL.iNet GL-B2200\";\n\tcompatible = \"glinet,gl-b2200\", \"qcom,ipq4019\";\n\n\tmemory {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x80000000 0x10000000>;\n\t};\n\n\tchosen {\n\t\tbootargs-append = \" root=/dev/mmcblk0p2 rw rootwait clk_ignore_unused\";\n\t};\n\n\tsoc {\n\t\trng@22000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tmdio@90000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tess-psgmii@98000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\ttcsr@1949000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1949000 0x100>;\n\t\t\tqcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;\n\t\t};\n\n\t\ttcsr@194b000 {\n\t\t\t/* select hostmode */\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x194b000 0x100>;\n\t\t\tqcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tess_tcsr@1953000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1953000 0x1000>;\n\t\t\tqcom,ess-interface-select = <TCSR_ESS_PSGMII>;\n\t\t};\n\n\t\ttcsr@1957000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1957000 0x100>;\n\t\t\tqcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;\n\t\t};\n\n\t\tcrypto@8e3a000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tess-switch@c000000 {\n\t\t\tstatus = \"okay\";\n\t\t\tswitch_lan_bmp = <0x2e>;\n\t\t\tswitch_wan_bmp = <0x10>;\n\t\t};\n\n\t\tedma@c080000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&tlmm 18 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tlinux,input-type = <1>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&tlmm 40 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tlinux,input-type = <1>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tpower_blue {\n\t\t\tlabel = \"blue:power\";\n\t\t\tgpios = <&tlmm 57 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t\tinternet_blue {\n\t\t\tlabel = \"blue:internet\";\n\t\t\tgpios = <&tlmm 60 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t\tpower_white {\n\t\t\tlabel = \"white:power\";\n\t\t\tgpios = <&tlmm 61 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tinternet_white {\n\t\t\tlabel = \"white:internet\";\n\t\t\tgpios = <&tlmm 66 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&gmac1 {\n\tqcom,phy_mdio_addr = <3>;\n\tqcom,poll_required = <1>;\n\tqcom,forced_speed = <1000>;\n\tqcom,forced_duplex = <1>;\n\tvlan_tag = <2 0x10>;\n};\n\n&gmac0 {\n\tvlan_tag = <1 0x2e>;\n};\n\n&vqmmc {\n\tstatus = \"okay\";\n};\n\n&sdhci {\n\tstatus = \"okay\";\n\tpinctrl-0 = <&sd_pins>;\n\tpinctrl-names = \"default\";\n\tcd-gpios = <&tlmm 3 GPIO_ACTIVE_LOW>;\n\tvqmmc-supply = <&vqmmc>;\n};\n\n&blsp_dma {\n\tstatus = \"okay\";\n};\n\n&cryptobam {\n\tstatus = \"okay\";\n};\n\n&blsp1_spi1 {\n\tpinctrl-0 = <&spi_0_pins>;\n\tpinctrl-names = \"default\";\n\tstatus = \"okay\";\n\tcs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <24000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"SBL1\";\n\t\t\t\treg = <0x0 0x40000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"MIBIB\";\n\t\t\t\treg = <0x40000 0x20000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@60000 {\n\t\t\t\tlabel = \"QSEE\";\n\t\t\t\treg = <0x60000 0x60000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@c0000 {\n\t\t\t\tlabel = \"CDT\";\n\t\t\t\treg = <0xc0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@d0000 {\n\t\t\t\tlabel = \"DDRPARAMS\";\n\t\t\t\treg = <0xd0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@e0000 {\n\t\t\t\tlabel = \"APPSBLENV\";\n\t\t\t\treg = <0xe0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@f0000 {\n\t\t\t\tlabel = \"APPSBL\";\n\t\t\t\treg = <0xf0000 0x80000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@170000 {\n\t\t\t\tlabel = \"ART\";\n\t\t\t\treg = <0x170000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t\tcompatible = \"nvmem-cells\";\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\n\t\t\t\tprecal_art_1000: precal@1000 {\n\t\t\t\t\treg = <0x1000 0x2f20>;\n\t\t\t\t};\n\n\t\t\t\tprecal_art_5000: precal@5000 {\n\t\t\t\t\treg = <0x5000 0x2f20>;\n\t\t\t\t};\n\n\t\t\t\tprecal_art_9000: precal@9000 {\n\t\t\t\t\treg = <0x9000 0x2f20>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t};\n};\n\n&blsp1_spi2 {\n\tpinctrl-0 = <&spi_1_pins>;\n\tpinctrl-names = \"default\";\n\tstatus = \"okay\";\n\n\tspidev1: spi@0 {\n\t\tcompatible = \"siliconlabs,si3210\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <24000000>;\n\t};\n};\n\n&blsp1_uart1 {\n\tpinctrl-0 = <&serial_pins>;\n\tpinctrl-names = \"default\";\n\tstatus = \"okay\";\n};\n\n&blsp1_uart2 {\n\tpinctrl-0 = <&serial_1_pins>;\n\tpinctrl-names = \"default\";\n\tstatus = \"okay\";\n};\n\n&tlmm {\n\tserial_pins: serial_pinmux {\n\t\tmux {\n\t\t\tpins = \"gpio16\", \"gpio17\";\n\t\t\tfunction = \"blsp_uart0\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tserial_1_pins: serial1_pinmux {\n\t\tmux {\n\t\t\tpins = \"gpio8\", \"gpio9\",\n\t\t\t\t\"gpio10\", \"gpio11\";\n\t\t\tfunction = \"blsp_uart1\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tspi_0_pins: spi_0_pinmux {\n\t\tpinmux {\n\t\t\tfunction = \"blsp_spi0\";\n\t\t\tpins = \"gpio13\", \"gpio14\", \"gpio15\";\n\t\t};\n\t\tpinmux_cs {\n\t\t\tfunction = \"gpio\";\n\t\t\tpins = \"gpio12\";\n\t\t};\n\t\tpinconf {\n\t\t\tpins = \"gpio13\", \"gpio14\", \"gpio15\";\n\t\t\tdrive-strength = <12>;\n\t\t\tbias-disable;\n\t\t};\n\t\tpinconf_cs {\n\t\t\tpins = \"gpio12\";\n\t\t\tdrive-strength = <2>;\n\t\t\tbias-disable;\n\t\t\toutput-high;\n\t\t};\n\t};\n\n\tspi_1_pins: spi_1_pinmux {\n\t\tmux {\n\t\t\tpins = \"gpio44\", \"gpio46\", \"gpio47\";\n\t\t\tfunction = \"blsp_spi1\";\n\t\t\tbias-disable;\n\t\t};\n\t\tcs {\n\t\t\tpins = \"gpio45\";\n\t\t\tfunction = \"gpio\";\n\t\t\tbias-pull-up;\n\t\t};\n\t\treset {\n\t\t\tpins = \"gpio43\";\n\t\t\tfunction = \"gpio\";\n\t\t\toutput-high;\n\t\t};\n\t\tmux_2 {\n\t\t\tpins = \"gpio35\";\n\t\t\tfunction = \"gpio\";\n\t\t\toutput-high;\n\t\t};\n\t\thost_int {\n\t\t\tpins = \"gpio2\";\n\t\t\tfunction = \"gpio\";\n\t\t\tinput;\n\t\t};\n\t\twake {\n\t\t\tpins = \"gpio48\";\n\t\t\tfunction = \"gpio\";\n\t\t\toutput-high;\n\t\t};\n\t};\n\n\tsd_pins: sd_pins {\n\t\tpinmux {\n\t\t\tfunction = \"sdio\";\n\t\t\tpins = \"gpio23\", \"gpio24\", \"gpio25\", \"gpio26\",\n\t\t\t\t\"gpio29\", \"gpio30\", \"gpio31\", \"gpio32\";\n\t\t\tdrive-strength = <10>;\n\t\t};\n\n\t\tpinmux_sd_clk {\n\t\t\tfunction = \"sdio\";\n\t\t\tpins = \"gpio27\";\n\t\t\tdrive-strength = <16>;\n\t\t};\n\n\t\tpinmux_sd7 {\n\t\t\tfunction = \"sdio\";\n\t\t\tpins = \"gpio28\";\n\t\t\tdrive-strength = <10>;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n};\n\n&pcie0 {\n\tstatus = \"okay\";\n\tperst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;\n\twake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>;\n\n\tbridge@0,0 {\n\t\treg = <0x00000000 0 0 0 0>;\n\t\t#address-cells = <3>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\twifi2: wifi@1,0 {\n\t\t\tstatus = \"okay\";\n\t\t\t/* Bootlog shows this is a 168c:0056 - QCA 9888v2 */\n\t\t\tcompatible = \"qcom,ath10k\";\n\t\t\treg = <0x00010000 0 0 0 0>;\n\t\t\tnvmem-cell-names = \"pre-calibration\";\n\t\t\tnvmem-cells = <&precal_art_9000>;\n\t\t\tqcom,ath10k-calibration-variant = \"GL-B2200\";\n\t\t\tieee80211-freq-limit = <5450000 5900000>;\n\t\t};\n\t};\n};\n\n&wifi0 {\n\tstatus = \"okay\";\n\tnvmem-cell-names = \"pre-calibration\";\n\tnvmem-cells = <&precal_art_1000>;\n\tqcom,ath10k-calibration-variant = \"GL-B2200\";\n};\n\n&wifi1 {\n\tstatus = \"okay\";\n\tnvmem-cell-names = \"pre-calibration\";\n\tnvmem-cells = <&precal_art_5000>;\n\tqcom,ath10k-calibration-variant = \"GL-B2200\";\n\tieee80211-freq-limit = <5100000 5400000>;\n};\n"
  },
  {
    "path": "target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-habanero-dvk.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n/* Copyright (c) 2019, Robert Marko <robimarko@gmail.com> */\n\n#include \"qcom-ipq4019.dtsi\"\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/soc/qcom,tcsr.h>\n\n/ {\n\tmodel = \"8devices Habanero DVK\";\n\tcompatible = \"8dev,habanero-dvk\";\n\n\taliases {\n\t\tled-boot = &led_status;\n\t\tled-failsafe = &led_status;\n\t\tled-running = &led_status;\n\t\tled-upgrade = &led_upgrade;\n\t};\n\n\tsoc {\n\t\trng@22000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tmdio@90000 {\n\t\t\tstatus = \"okay\";\n\n\t\t\tpinctrl-0 = <&mdio_pins>;\n\t\t\tpinctrl-names = \"default\";\n\t\t};\n\n\t\tess-psgmii@98000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tcounter@4a1000 {\n\t\t\tcompatible = \"qcom,qca-gcnt\";\n\t\t\treg = <0x4a1000 0x4>;\n\t\t};\n\n\t\ttcsr@1949000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1949000 0x100>;\n\t\t\tqcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;\n\t\t};\n\n\t\ttcsr@194b000 {\n\t\t\tstatus = \"okay\";\n\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x194b000 0x100>;\n\t\t\tqcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;\n\t\t};\n\n\t\tess_tcsr@1953000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1953000 0x1000>;\n\t\t\tqcom,ess-interface-select = <TCSR_ESS_PSGMII>;\n\t\t};\n\n\t\ttcsr@1957000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1957000 0x100>;\n\t\t\tqcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;\n\t\t};\n\n\t\tusb2: usb2@60f8800 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tusb3: usb3@8af8800 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tcrypto@8e3a000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\twatchdog@b017000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tess-switch@c000000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tedma@c080000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&tlmm 8 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_status: status {\n\t\t\tlabel = \"green:status\";\n\t\t\tgpios = <&tlmm 37 GPIO_ACTIVE_HIGH>;\n\t\t\tpanic-indicator;\n\t\t};\n\n\t\tled_upgrade: upgrade {\n\t\t\tlabel = \"green:upgrade\";\n\t\t\tgpios = <&tlmm 40 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\twlan2g {\n\t\t\tlabel = \"green:wlan2g\";\n\t\t\tgpios = <&tlmm 46 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\twlan5g {\n\t\t\tlabel = \"green:wlan5g\";\n\t\t\tgpios = <&tlmm 48 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\t};\n};\n\n&vqmmc {\n\tstatus = \"okay\";\n};\n\n&sdhci {\n\tstatus = \"okay\";\n\n\tpinctrl-0 = <&sd_pins>;\n\tpinctrl-names = \"default\";\n\tcd-gpios = <&tlmm 22 GPIO_ACTIVE_LOW>;\n\tvqmmc-supply = <&vqmmc>;\n};\n\n&qpic_bam {\n\tstatus = \"okay\";\n};\n\n&tlmm {\n\tmdio_pins: mdio_pinmux {\n\t\tmux_1 {\n\t\t\tpins = \"gpio6\";\n\t\t\tfunction = \"mdio\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tmux_2 {\n\t\t\tpins = \"gpio7\";\n\t\t\tfunction = \"mdc\";\n\t\t\tbias-pull-up;\n\t\t};\n\t};\n\n\tserial_pins: serial_pinmux {\n\t\tmux {\n\t\t\tpins = \"gpio16\", \"gpio17\";\n\t\t\tfunction = \"blsp_uart0\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tspi_0_pins: spi_0_pinmux {\n\t\tpinmux {\n\t\t\tfunction = \"blsp_spi0\";\n\t\t\tpins = \"gpio13\", \"gpio14\", \"gpio15\";\n\t\t\tdrive-strength = <12>;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tpinmux_cs {\n\t\t\tfunction = \"gpio\";\n\t\t\tpins = \"gpio12\";\n\t\t\tdrive-strength = <2>;\n\t\t\tbias-disable;\n\t\t\toutput-high;\n\t\t};\n\t};\n\n\tnand_pins: nand_pins {\n\t\tpullups {\n\t\t\tpins =  \"gpio52\", \"gpio53\", \"gpio58\", \"gpio59\";\n\t\t\tfunction = \"qpic\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tpulldowns {\n\t\t\tpins = \"gpio54\", \"gpio55\", \"gpio56\", \"gpio57\",\n\t\t\t\t\"gpio60\", \"gpio62\", \"gpio63\", \"gpio64\",\n\t\t\t\t\"gpio65\", \"gpio66\", \"gpio67\", \"gpio68\",\n\t\t\t\t\"gpio69\";\n\t\t\tfunction = \"qpic\";\n\t\t\tbias-pull-down;\n\t\t};\n\t};\n\n\tsd_pins: sd_pins {\n\t\tpinmux {\n\t\t\tfunction = \"sdio\";\n\t\t\tpins = \"gpio23\", \"gpio24\", \"gpio25\", \"gpio26\",\n\t\t\t\t\"gpio28\", \"gpio29\", \"gpio30\", \"gpio31\";\n\t\t\tdrive-strength = <10>;\n\t\t};\n\n\t\tpinmux_sd_clk {\n\t\t\tfunction = \"sdio\";\n\t\t\tpins = \"gpio27\";\n\t\t\tdrive-strength = <16>;\n\t\t};\n\n\t\tpinmux_sd7 {\n\t\t\tfunction = \"sdio\";\n\t\t\tpins = \"gpio32\";\n\t\t\tdrive-strength = <10>;\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&blsp_dma {\n\tstatus = \"okay\";\n};\n\n&blsp1_spi1 {\n\tstatus = \"okay\";\n\n\tpinctrl-0 = <&spi_0_pins>;\n\tpinctrl-names = \"default\";\n\tcs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\tspi-max-frequency = <24000000>;\n\t\treg = <0>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"SBL1\";\n\t\t\t\treg = <0x00000000 0x00040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"MIBIB\";\n\t\t\t\treg = <0x00040000 0x00020000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@60000 {\n\t\t\t\tlabel = \"QSEE\";\n\t\t\t\treg = <0x00060000 0x00060000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@c0000 {\n\t\t\t\tlabel = \"CDT\";\n\t\t\t\treg = <0x000c0000 0x00010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@d0000 {\n\t\t\t\tlabel = \"DDRPARAMS\";\n\t\t\t\treg = <0x000d0000 0x00010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@e0000 {\n\t\t\t\tlabel = \"APPSBLENV\"; /* uboot env */\n\t\t\t\treg = <0x000e0000 0x00010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@f0000 {\n\t\t\t\tlabel = \"APPSBL\"; /* uboot */\n\t\t\t\treg = <0x000f0000 0x00080000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@170000 {\n\t\t\t\tlabel = \"ART\";\n\t\t\t\treg = <0x00170000 0x00010000>;\n\t\t\t\tread-only;\n\t\t\t\tcompatible = \"nvmem-cells\";\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\n\t\t\t\tprecal_art_1000: precal@1000 {\n\t\t\t\t\treg = <0x1000 0x2f20>;\n\t\t\t\t};\n\n\t\t\t\tprecal_art_5000: precal@5000 {\n\t\t\t\t\treg = <0x5000 0x2f20>;\n\t\t\t\t};\n\t\t\t};\n\t\t\tpartition@180000 {\n\t\t\t\tlabel = \"cfg\";\n\t\t\t\treg = <0x00180000 0x00040000>;\n\t\t\t};\n\t\t\tpartition@1c0000 {\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\tcompatible = \"denx,fit\";\n\t\t\t\treg = <0x001c0000 0x01e40000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n/* Some DVK boards ship without NAND */\n&nand {\n\tstatus = \"okay\";\n\n\tpinctrl-0 = <&nand_pins>;\n\tpinctrl-names = \"default\";\n};\n\n&blsp1_uart1 {\n\tstatus = \"okay\";\n\n\tpinctrl-0 = <&serial_pins>;\n\tpinctrl-names = \"default\";\n};\n\n&cryptobam {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\tstatus = \"okay\";\n\n\tperst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;\n\twake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>;\n\n\t/* Free slot for use */\n\tbridge@0,0 {\n\t\treg = <0x00000000 0 0 0 0>;\n\t\t#address-cells = <3>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\t};\n};\n\n&wifi0 {\n\tstatus = \"okay\";\n\tnvmem-cell-names = \"pre-calibration\";\n\tnvmem-cells = <&precal_art_1000>;\n\tqcom,ath10k-calibration-variant = \"8devices-Habanero\";\n};\n\n&wifi1 {\n\tstatus = \"okay\";\n\tnvmem-cell-names = \"pre-calibration\";\n\tnvmem-cells = <&precal_art_5000>;\n\tqcom,ath10k-calibration-variant = \"8devices-Habanero\";\n};\n\n&usb3_ss_phy {\n\tstatus = \"okay\";\n};\n\n&usb3_hs_phy {\n\tstatus = \"okay\";\n};\n\n&usb2_hs_phy {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-hap-ac3.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n/* Copyright (c) 2021, Robert Marko <robimarko@gmail.com> */\n\n#include \"qcom-ipq4019.dtsi\"\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/soc/qcom,tcsr.h>\n\n/ {\n\tmodel = \"MikroTik hAP ac3\";\n\tcompatible = \"mikrotik,hap-ac3\";\n\n\tmemory {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x80000000 0x10000000>;\n\t};\n\n\tchosen {\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\taliases {\n\t\tled-boot = &led_status_blue;\n\t\tled-failsafe = &led_status_red;\n\t\tled-running = &led_status_blue;\n\t\tled-upgrade = &led_status_red;\n\t};\n\n\tsoc {\n\t\trng@22000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tcounter@4a1000 {\n\t\t\tcompatible = \"qcom,qca-gcnt\";\n\t\t\treg = <0x4a1000 0x4>;\n\t\t};\n\n\t\ttcsr@1949000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1949000 0x100>;\n\t\t\tqcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;\n\t\t};\n\n\t\ttcsr@194b000 {\n\t\t\t/* select hostmode */\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x194b000 0x100>;\n\t\t\tqcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tess_tcsr@1953000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1953000 0x1000>;\n\t\t\tqcom,ess-interface-select = <TCSR_ESS_PSGMII>;\n\t\t};\n\n\t\ttcsr@1957000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1957000 0x100>;\n\t\t\tqcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;\n\t\t};\n\n\t\tusb2: usb2@60f8800 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tcrypto@8e3a000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\twatchdog@b017000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tess-switch@c000000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tedma@c080000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&tlmm 5 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\tmode {\n\t\t\tlabel = \"mode\";\n\t\t\tgpios = <&tlmm 4 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RFKILL>;\n\t\t};\n\n\t\tled {\n\t\t\tlabel = \"led\";\n\t\t\tgpios = <&tlmm 42 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_status_blue: status-blue {\n\t\t\tlabel = \"blue:status\";\n\t\t\tgpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tled_status_red: status-red {\n\t\t\tlabel = \"red:status\";\n\t\t\tgpios = <&tlmm 1 GPIO_ACTIVE_HIGH>;\n\t\t\tpanic-indicator;\n\t\t};\n\n\t\tled_status_green: status-green {\n\t\t\tlabel = \"green:status\";\n\t\t\tgpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\twlan {\n\t\t\tlabel = \"green:wlan\";\n\t\t\tgpios = <&tlmm 23 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tethernet {\n\t\t\tlabel = \"green:ethernet\";\n\t\t\tgpios = <&tlmm 22 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\twan {\n\t\t\tlabel = \"green:wan\";\n\t\t\tgpios = <&tlmm 28 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tlan1 {\n\t\t\tlabel = \"green:lan1\";\n\t\t\tgpios = <&tlmm 29 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tlan2 {\n\t\t\tlabel = \"green:lan2\";\n\t\t\tgpios = <&tlmm 30 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tlan3 {\n\t\t\tlabel = \"green:lan3\";\n\t\t\tgpios = <&tlmm 31 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tlan4 {\n\t\t\tlabel = \"green:lan4\";\n\t\t\tgpios = <&tlmm 32 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tpoe {\n\t\t\tlabel = \"red:poe\";\n\t\t\tgpios = <&tlmm 36 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&tlmm {\n\tserial_pins: serial_pinmux {\n\t\tmux {\n\t\t\tpins = \"gpio16\", \"gpio17\";\n\t\t\tfunction = \"blsp_uart0\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tspi_0_pins: spi_0_pinmux {\n\t\tpin {\n\t\t\tfunction = \"blsp_spi0\";\n\t\t\tpins = \"gpio13\", \"gpio14\", \"gpio15\";\n\t\t\tdrive-strength = <12>;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tpin_cs {\n\t\t\tfunction = \"gpio\";\n\t\t\tpins = \"gpio12\";\n\t\t\tdrive-strength = <2>;\n\t\t\tbias-disable;\n\t\t\toutput-high;\n\t\t};\n\t};\n\n\tnand_pins: nand_pins {\n\t\tpullups {\n\t\t\tpins = \"gpio53\", \"gpio58\", \"gpio59\";\n\t\t\tfunction = \"qpic\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tpulldowns {\n\t\t\tpins = \"gpio55\", \"gpio56\", \"gpio57\", \"gpio60\",\n\t\t\t\t   \"gpio62\", \"gpio63\", \"gpio64\", \"gpio65\",\n\t\t\t\t   \"gpio66\", \"gpio67\", \"gpio68\", \"gpio69\";\n\t\t\tfunction = \"qpic\";\n\t\t\tbias-pull-down;\n\t\t};\n\t};\n\n\tenable-usb-power {\n\t\tgpio-hog;\n\t\tgpios = <44 GPIO_ACTIVE_HIGH>;\n\t\toutput-high;\n\t\tline-name = \"enable USB power\";\n\t};\n};\n\n&blsp_dma {\n\tstatus = \"okay\";\n};\n\n&blsp1_spi1 {\n\tstatus = \"okay\";\n\n\tpinctrl-0 = <&spi_0_pins>;\n\tpinctrl-names = \"default\";\n\tcs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;\n\n\tflash@0 {\n\t\treg = <0>;\n\t\tcompatible = \"jedec,spi-nor\";\n\t\tspi-max-frequency = <40000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"Qualcomm\";\n\t\t\t\treg = <0x0 0x80000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@80000 {\n\t\t\t\tcompatible = \"mikrotik,routerboot-partitions\";\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\t\t\t\tlabel = \"RouterBoot\";\n\t\t\t\treg = <0x80000 0x80000>;\n\t\t\t\tread-only;\n\n\t\t\t\thard_config {\n\t\t\t\t\tread-only;\n\t\t\t\t\tsize = <0x2000>;\n\t\t\t\t};\n\n\t\t\t\tdtb_config {\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\tsoft_config {\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t};\n};\n\n&qpic_bam {\n\tstatus = \"okay\";\n};\n\n&nand {\n\tstatus = \"okay\";\n\n\tpinctrl-0 = <&nand_pins>;\n\tpinctrl-names = \"default\";\n\n\tnand@0 {\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"kernel\";\n\t\t\t\treg = <0x0 0xa00000>;\n\t\t\t};\n\n\t\t\tpartition@a00000 {\n\t\t\t\tlabel = \"ubi\";\n\t\t\t\treg = <0xa00000 0x7600000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&blsp1_uart1 {\n\tstatus = \"okay\";\n\n\tpinctrl-0 = <&serial_pins>;\n\tpinctrl-names = \"default\";\n};\n\n&cryptobam {\n\tstatus = \"okay\";\n};\n\n&usb2_hs_phy {\n\tstatus = \"okay\";\n};\n\n&mdio {\n\tstatus = \"okay\";\n};\n\n&wifi0 {\n\tstatus = \"okay\";\n\n\tqcom,ath10k-calibration-variant = \"MikroTik-hAP-ac3\";\n};\n\n&wifi1 {\n\tstatus = \"okay\";\n\n\tqcom,ath10k-calibration-variant = \"MikroTik-hAP-ac3\";\n};\n"
  },
  {
    "path": "target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-lhgg-60ad.dts",
    "content": "/* Copyright (c) 2015, The Linux Foundation. All rights reserved.\n * Copyright (c) 2019, Robert Marko <robimarko@gmail.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#include \"qcom-ipq4019.dtsi\"\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/soc/qcom,tcsr.h>\n\n/ {\n\tmodel = \"Mikrotik Wireless Wire Dish LHGG-60ad\";\n\tcompatible = \"mikrotik,lhgg-60ad\";\n\n\tmemory {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x80000000 0x10000000>;\n\t};\n\n\tchosen {\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\taliases {\n\t\tled-boot = &user;\n\t\tled-failsafe = &user;\n\t\tled-running = &user;\n\t\tled-upgrade = &user;\n\t};\n\n\tsoc {\n\t\trng@22000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tmdio@90000 {\n\t\t\tstatus = \"okay\";\n\n\t\t\t/delete-node/ ethernet-phy@1;\n\t\t\t/delete-node/ ethernet-phy@2;\n\t\t\t/delete-node/ ethernet-phy@3;\n\t\t\t/delete-node/ ethernet-phy@4;\n\t\t\t/delete-node/ psgmii-phy@5;\n\t\t};\n\n\t\tcounter@4a1000 {\n\t\t\tcompatible = \"qcom,qca-gcnt\";\n\t\t\treg = <0x4a1000 0x4>;\n\t\t};\n\n\t\ttcsr@1949000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1949000 0x100>;\n\t\t\tqcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;\n\t\t};\n\n\t\tess_tcsr@1953000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1953000 0x1000>;\n\t\t\tqcom,ess-interface-select = <TCSR_ESS_PSGMII_RGMII5>;\n\t\t};\n\n\t\ttcsr@1957000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1957000 0x100>;\n\t\t\tqcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;\n\t\t};\n\n\t\tcrypto@8e3a000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\twatchdog@b017000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tess-switch@c000000 {\n\t\t\tswitch_mac_mode = <0x3>; /* mac mode for RGMII RMII */\n\t\t\tswitch_lan_bmp = <0x0>; /* lan port bitmap */\n\t\t\tswitch_wan_bmp = <0x10>; /* wan port bitmap */\n\t\t};\n\n\t\tedma@c080000 {\n\t\t\tstatus = \"okay\";\n\t\t\tphy-mode = \"rgmii-id\";\n\t\t\tqcom,num_gmac = <1>;\n\t\t\tqcom,single-phy;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&tlmm 63 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tpower: power {\n\t\t\tlabel = \"blue:power\";\n\t\t\tgpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"keep\";\n\t\t\tpanic-indicator;\n\t\t};\n\n\t\tuser: user {\n\t\t\tlabel = \"yellow:user\";\n\t\t\tgpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\twlan {\n\t\t\tlabel = \"green:wlan\";\n\t\t\tgpios = <&tlmm 58 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\talign-left {\n\t\t\tlabel = \"green:align-left\";\n\t\t\tgpios = <&tlmm 1 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\talign-right {\n\t\t\tlabel = \"green:align-right\";\n\t\t\tgpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\twlan-rx {\n\t\t\tlabel = \"green:align-down\";\n\t\t\tgpios = <&tlmm 4 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\twlan-tx {\n\t\t\tlabel = \"green:align-up\";\n\t\t\tgpios = <&tlmm 5 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&tlmm {\n\tserial_pins: serial_pinmux {\n\t\tmux {\n\t\t\tpins = \"gpio60\", \"gpio61\";\n\t\t\tfunction = \"blsp_uart0\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tspi_0_pins: spi-0-pinmux {\n\t\tpinmux {\n\t\t\tfunction = \"blsp_spi0\";\n\t\t\tpins = \"gpio13\", \"gpio14\", \"gpio15\";\n\t\t\tbias-disable;\n\t\t};\n\n\t\tpinmux_cs {\n\t\t\tfunction = \"gpio\";\n\t\t\tpins = \"gpio12\";\n\t\t\tbias-disable;\n\t\t\toutput-high;\n\t\t};\n\t};\n};\n\n&blsp_dma {\n\tstatus = \"okay\";\n};\n\n&blsp1_spi1 {\n\tpinctrl-0 = <&spi_0_pins>;\n\tpinctrl-names = \"default\";\n\tcs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;\n\tstatus = \"okay\";\n\n\tm25p80@0 {\n\t\treg = <0>;\n\t\tcompatible = \"jedec,spi-nor\";\n\t\tspi-max-frequency = <24000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"Qualcomm\";\n\t\t\t\treg = <0x0 0x80000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@80000 {\n\t\t\t\tcompatible = \"mikrotik,routerboot-partitions\";\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\t\t\t\tlabel = \"RouterBoot\";\n\t\t\t\treg = <0x80000 0x80000>;\n\t\t\t\tread-only;\n\n\t\t\t\thard_config {\n\t\t\t\t\tread-only;\n\t\t\t\t\tsize = <0x2000>;\n\t\t\t\t};\n\n\t\t\t\tdtb_config {\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\tsoft_config {\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tpartition@100000 {\n\t\t\t\tcompatible = \"mikrotik,minor\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x100000 0xf00000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&blsp1_uart1 {\n\tpinctrl-0 = <&serial_pins>;\n\tpinctrl-names = \"default\";\n\tstatus = \"okay\";\n};\n\n&cryptobam {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\tstatus = \"okay\";\n\tperst-gpio = <&tlmm 42 GPIO_ACTIVE_HIGH>;\n\n\tbridge@0,0 {\n\t\treg = <0x00000000 0 0 0 0>;\n\t\t#address-cells = <3>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\t/* wil6210 802.11ad card */\n\t\twifi: wifi@1,0 {\n\t\t\tstatus = \"okay\";\n\t\t\t/* wil6210 driver has no compatible */\n\t\t\treg = <0x00010000 0 0 0 0>;\n\t\t};\n\t};\n};\n\n&gmac0 {\n\tqcom,phy_mdio_addr = <0>;\n\tqcom,poll_required = <1>;\n\tvlan_tag = <0 0x20>;\n};\n"
  },
  {
    "path": "target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-map-ac2200.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qcom-ipq4019.dtsi\"\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/soc/qcom,tcsr.h>\n#include <dt-bindings/leds/common.h>\n\n/ {\n\tmodel = \"ASUS Lyra MAP-AC2200\";\n\tcompatible = \"asus,map-ac2200\";\n\n\taliases {\n\t\tled-boot = &led_blue0;\n\t\tled-failsafe = &led_red0;\n\t\tled-running = &led_blue0;\n\t\tled-upgrade = &led_red0;\n\t};\n\n\tsoc {\n\t\trng@22000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tmdio@90000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tess-psgmii@98000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\ttcsr@1949000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1949000 0x100>;\n\t\t\tqcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;\n\t\t};\n\n\t\tess_tcsr@1953000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1953000 0x1000>;\n\t\t\tqcom,ess-interface-select = <TCSR_ESS_PSGMII>;\n\t\t};\n\n\t\ttcsr@1957000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1957000 0x100>;\n\t\t\tqcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;\n\t\t};\n\n\t\tusb2@60f8800 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tcrypto@8e3a000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\twatchdog@b017000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tess-switch@c000000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tedma@c080000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&tlmm 34 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&tlmm 18 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n};\n\n&nand {\n\tpinctrl-0 = <&nand_pins>;\n\tpinctrl-names = \"default\";\n\tstatus = \"okay\";\n\n\tnand@0 {\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"SBL1\";\n\t\t\t\treg = <0x0 0x80000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@80000 {\n\t\t\t\tlabel = \"MIBIB\";\n\t\t\t\treg = <0x80000 0x80000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@100000 {\n\t\t\t\tlabel = \"QSEE\";\n\t\t\t\treg = <0x100000 0x100000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@200000 {\n\t\t\t\tlabel = \"CDT\";\n\t\t\t\treg = <0x200000 0x80000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@280000 {\n\t\t\t\tlabel = \"APPSBL\";\n\t\t\t\treg = <0x280000 0x140000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@3c0000 {\n\t\t\t\tlabel = \"APPSBLENV\";\n\t\t\t\treg = <0x3c0000 0x40000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@400000 {\n\t\t\t\tlabel = \"ubi\";\n\t\t\t\treg = <0x400000 0x7c00000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&tlmm {\n\ti2c_0_pins: i2c_0_pinmux {\n\t\tpinmux {\n\t\t\tfunction = \"blsp_i2c0\";\n\t\t\tpins = \"gpio20\", \"gpio21\";\n\t\t\tdrive-strength = <16>;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tserial_pins: serial_pinmux {\n\t\tmux {\n\t\t\tpins = \"gpio16\", \"gpio17\";\n\t\t\tfunction = \"blsp_uart0\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tnand_pins: nand_pins {\n\t\tpullups {\n\t\t\tpins =\t\"gpio52\", \"gpio53\", \"gpio58\",\n\t\t\t\t\"gpio59\";\n\t\t\tfunction = \"qpic\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tpulldowns {\n\t\t\tpins =\t\"gpio54\", \"gpio55\", \"gpio56\",\n\t\t\t\t\"gpio57\", \"gpio60\", \"gpio61\",\n\t\t\t\t\"gpio62\", \"gpio63\", \"gpio64\",\n\t\t\t\t\"gpio65\", \"gpio66\", \"gpio67\",\n\t\t\t\t\"gpio68\", \"gpio69\";\n\t\t\tfunction = \"qpic\";\n\t\t\tbias-pull-down;\n\t\t};\n\t};\n\tenable_ext_pa_high {\n\t\tgpio-hog;\n\t\tgpios = <44 GPIO_ACTIVE_HIGH>,\n\t\t\t<46 GPIO_ACTIVE_HIGH>;\n\t\toutput-high;\n\t\tbias-pull-down;\n\t\tline-name = \"enable external PA output-high\";\n\t};\n\tenable_ext_pa_low {\n\t\tgpio-hog;\n\t\tgpios = <45 GPIO_ACTIVE_HIGH>,\n\t\t\t<47 GPIO_ACTIVE_HIGH>;\n\t\toutput-low;\n\t\tbias-pull-down;\n\t\tline-name = \"enable external PA output-low\";\n\t};\n};\n\n&cryptobam {\n\tstatus = \"okay\";\n};\n\n&blsp_dma {\n\tstatus = \"okay\";\n};\n\n&qpic_bam {\n\tstatus = \"okay\";\n};\n\n&wifi0 {\n\tstatus = \"okay\";\n\tqcom,ath10k-calibration-variant = \"ASUS-MAP-AC2200\";\n};\n\n&wifi1 {\n\tstatus = \"okay\";\n\tqcom,ath10k-calibration-variant = \"ASUS-MAP-AC2200\";\n\tieee80211-freq-limit = <5470000 5875000>;\n};\n\n&pcie0 {\n\tstatus = \"okay\";\n\tperst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;\n\twake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>;\n\n\tbridge@0,0 {\n\t\treg = <0x00000000 0 0 0 0>;\n\t\t#address-cells = <3>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\twifi2: wifi@1,0 {\n\t\t\tcompatible = \"qcom,ath10k\";\n\t\t\tstatus = \"okay\";\n\t\t\treg = <0x00010000 0 0 0 0>;\n\t\t\tqcom,ath10k-calibration-variant = \"ASUS-MAP-AC2200\";\n\t\t\tieee80211-freq-limit = <5170000 5350000>;\n\t\t};\n\t};\n};\n\n&usb2_hs_phy {\n\t/* Bluetooth module attached via USB */\n\tstatus = \"okay\";\n};\n\n&blsp1_i2c3 {\n\tpinctrl-0 = <&i2c_0_pins>;\n\tpinctrl-names = \"default\";\n\tstatus = \"okay\";\n\n\tled-controller@32 {\n\t\t/* 9-channel RGB LED controller */\n\t\tcompatible = \"national,lp5523\";\n\t\treg = <0x32>;\n\t\tclock-mode = /bits/ 8 <1>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\t/*\n\t\t * There is only one single extremely bright RGB-LED.\n\t\t * The RGB-color channels are running in parallel to\n\t\t * increase the current delivery capabilities beyond\n\t\t * what a single PWM-output of the controller can do.\n\t\t */\n\n\t\tled_blue0: led@0 {\n\t\t\tchan-name = \"blue-0\";\n\t\t\tled-cur = /bits/ 8 <0xfa>;\n\t\t\tmax-cur = /bits/ 8 <0xff>;\n\t\t\treg = <0>;\n\t\t\tcolor = <LED_COLOR_ID_BLUE>;\n\t\t\tfunction-enumerator = <0>;\n\t\t};\n\n\t\tled@1 {\n\t\t\tchan-name = \"blue-1\";\n\t\t\tled-cur = /bits/ 8 <0xfa>;\n\t\t\tmax-cur = /bits/ 8 <0xff>;\n\t\t\treg = <1>;\n\t\t\tcolor = <LED_COLOR_ID_BLUE>;\n\t\t\tfunction-enumerator = <1>;\n\t\t};\n\n\t\tled@2 {\n\t\t\tchan-name = \"blue-2\";\n\t\t\tled-cur = /bits/ 8 <0xfa>;\n\t\t\tmax-cur = /bits/ 8 <0xff>;\n\t\t\treg = <2>;\n\t\t\tcolor = <LED_COLOR_ID_BLUE>;\n\t\t\tfunction-enumerator = <2>;\n\t\t};\n\n\t\tled_green0: led@3 {\n\t\t\tchan-name = \"green-0\";\n\t\t\tled-cur = /bits/ 8 <0xfa>;\n\t\t\tmax-cur = /bits/ 8 <0xff>;\n\t\t\treg = <3>;\n\t\t\tcolor = <LED_COLOR_ID_GREEN>;\n\t\t\tfunction-enumerator = <0>;\n\t\t};\n\n\t\tled@4 {\n\t\t\tchan-name = \"green-1\";\n\t\t\tled-cur = /bits/ 8 <0xfa>;\n\t\t\tmax-cur = /bits/ 8 <0xff>;\n\t\t\treg = <4>;\n\t\t\tcolor = <LED_COLOR_ID_GREEN>;\n\t\t\tfunction-enumerator = <1>;\n\t\t};\n\n\t\tled@5 {\n\t\t\tchan-name = \"green-2\";\n\t\t\tled-cur = /bits/ 8 <0xfa>;\n\t\t\tmax-cur = /bits/ 8 <0xff>;\n\t\t\treg = <5>;\n\t\t\tcolor = <LED_COLOR_ID_GREEN>;\n\t\t\tfunction-enumerator = <2>;\n\t\t};\n\n\t\tled_red0: led@6 {\n\t\t\tchan-name = \"red-0\";\n\t\t\tled-cur = /bits/ 8 <0xfa>;\n\t\t\tmax-cur = /bits/ 8 <0xff>;\n\t\t\treg = <6>;\n\t\t\tcolor = <LED_COLOR_ID_RED>;\n\t\t\tfunction-enumerator = <0>;\n\t\t};\n\n\t\tled@7 {\n\t\t\tchan-name = \"red-1\";\n\t\t\tled-cur = /bits/ 8 <0xfa>;\n\t\t\tmax-cur = /bits/ 8 <0xff>;\n\t\t\treg = <7>;\n\t\t\tcolor = <LED_COLOR_ID_RED>;\n\t\t\tfunction-enumerator = <1>;\n\t\t};\n\n\t\tled@8 {\n\t\t\tchan-name = \"red-2\";\n\t\t\tled-cur = /bits/ 8 <0xfa>;\n\t\t\tmax-cur = /bits/ 8 <0xff>;\n\t\t\treg = <8>;\n\t\t\tcolor = <LED_COLOR_ID_RED>;\n\t\t\tfunction-enumerator = <2>;\n\t\t};\n\t};\n};\n\n&blsp1_uart1 {\n\tpinctrl-0 = <&serial_pins>;\n\tpinctrl-names = \"default\";\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-mf286d.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n// Copyright (c) 2022, Pawel Dembicki <paweldembicki@gmail.com>.\n\n#include \"qcom-ipq4019.dtsi\"\n#include <dt-bindings/soc/qcom,tcsr.h>\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/leds/common.h>\n\n/ {\n\tmodel = \"ZTE MF286D\";\n\tcompatible = \"zte,mf286d\";\n\n\taliases {\n\t\tled-boot = &led_internal;\n\t\tled-failsafe = &led_internal;\n\t\tled-running = &led_internal;\n\t\tled-upgrade = &led_internal;\n\t};\n\n\tchosen {\n\t\t/*\n\t\t * bootargs forced by u-boot bootipq command:\n\t\t * 'ubi.mtd=rootfs root=mtd:ubi_rootfs rootfstype=squashfs rootwait'\n\t\t */\n\t\tbootargs-append = \" root=/dev/ubiblock0_1\";\n\t};\n\n\tgpio-restart {\n\t\tcompatible = \"gpio-restart\";\n\t\tgpios = <&tlmm 8 GPIO_ACTIVE_HIGH>;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_internal: led-0 {\n\t\t\tfunction = LED_FUNCTION_STATUS;\n\t\t\tcolor = <LED_COLOR_ID_BLUE>;\n\t\t\tgpios = <&tlmm 10 GPIO_ACTIVE_LOW>;\n\t\t\tlabel = \"blue:internal_led\";\n\t\t\tdefault-state = \"keep\";\n\t\t};\n\n\t\tled-1 {\n\t\t\tfunction = LED_FUNCTION_WLAN;\n\t\t\tcolor = <LED_COLOR_ID_BLUE>;\n\t\t\tgpios = <&tlmm 61 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\twifi {\n\t\t\tlabel = \"wifi\";\n\t\t\tlinux,code = <KEY_RFKILL>;\n\t\t\tgpios = <&tlmm 11 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&tlmm 18 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tgpios = <&tlmm 68 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tsoc {\n\t\trng@22000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tmdio@90000 {\n\t\t\tstatus = \"okay\";\n\t\t\tpinctrl-0 = <&mdio_pins>;\n\t\t\tpinctrl-names = \"default\";\n\t\t\treset-gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;\n\t\t\treset-delay-us = <2000>;\n\t\t};\n\n\t\tess-psgmii@98000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\ttcsr@1949000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1949000 0x100>;\n\t\t\tqcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;\n\t\t};\n\n\t\ttcsr@194b000 {\n\t\t\t/* select hostmode */\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x194b000 0x100>;\n\t\t\tqcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tess_tcsr@1953000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1953000 0x1000>;\n\t\t\tqcom,ess-interface-select = <TCSR_ESS_PSGMII>;\n\t\t};\n\n\t\ttcsr@1957000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1957000 0x100>;\n\t\t\tqcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;\n\t\t};\n\n\t\tusb2@60f8800 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tusb3@8af8800 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tcrypto@8e3a000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\twatchdog@b017000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tess-switch@c000000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tedma@c080000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\t};\n};\n\n&blsp_dma {\n\tstatus = \"okay\";\n};\n\n&blsp1_spi1 {\n\tpinctrl-0 = <&spi_0_pins>;\n\tpinctrl-names = \"default\";\n\tstatus = \"okay\";\n\tcs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;\n\n\tflash@0 {\n\t\t/* u-boot is looking for \"n25q128a11\" property */\n\t\tcompatible = \"jedec,spi-nor\", \"n25q128a11\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>;\n\t\tspi-max-frequency = <24000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"0:SBL1\";\n\t\t\t\treg = <0x0 0x40000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"0:MIBIB\";\n\t\t\t\treg = <0x40000 0x20000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@60000 {\n\t\t\t\tlabel = \"0:QSEE\";\n\t\t\t\treg = <0x60000 0x60000>;\n\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\tpartition@c0000 {\n\t\t\t\tlabel = \"0:CDT\";\n\t\t\t\treg = <0xc0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@d0000 {\n\t\t\t\tlabel = \"0:DDRPARAMS\";\n\t\t\t\treg = <0xd0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@e0000 {\n\t\t\t\tlabel = \"0:APPSBLENV\";\n\t\t\t\treg = <0xe0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@f0000 {\n\t\t\t\tlabel = \"0:APPSBL\";\n\t\t\t\treg = <0xf0000 0xc0000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@1b0000 {\n\t\t\t\tlabel = \"0:reserved1\";\n\t\t\t\treg = <0x1b0000 0x50000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&blsp1_uart1 {\n\tpinctrl-0 = <&serial_pins>;\n\tpinctrl-names = \"default\";\n\tstatus = \"okay\";\n};\n\n&cryptobam {\n\tstatus = \"okay\";\n};\n\n&gmac0 {\n\tnvmem-cell-names = \"mac-address\";\n\tnvmem-cells = <&macaddr_config_0>;\n};\n\n&gmac1 {\n\tnvmem-cell-names = \"mac-address\";\n\tnvmem-cells = <&macaddr_config_0>;\n\tmac-address-increment = <1>;\n};\n\n&nand {\n\tpinctrl-0 = <&nand_pins>;\n\tpinctrl-names = \"default\";\n\tstatus = \"okay\";\n\n\tnand@0 {\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"fota-flag\";\n\t\t\t\treg = <0x0 0xa0000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@a0000 {\n\t\t\t\tlabel = \"ART\";\n\t\t\t\treg = <0xa0000 0x80000>;\n\t\t\t\tread-only;\n\t\t\t\tcompatible = \"nvmem-cells\";\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\n\t\t\t\tprecal_art_1000: precal@1000 {\n\t\t\t\t\treg = <0x1000 0x2f20>;\n\t\t\t\t};\n\n\t\t\t\tprecal_art_5000: precal@5000 {\n\t\t\t\t\treg = <0x5000 0x2f20>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tpartition@120000 {\n\t\t\t\tlabel = \"mac\";\n\t\t\t\treg = <0x120000 0x80000>;\n\t\t\t\tread-only;\n\t\t\t\tcompatible = \"nvmem-cells\";\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\n\t\t\t\tmacaddr_config_0: macaddr@0 {\n\t\t\t\t\treg = <0x0 0x6>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tpartition@1a0000 {\n\t\t\t\tlabel = \"reserved2\";\n\t\t\t\treg = <0x1a0000 0xc0000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@260000 {\n\t\t\t\tlabel = \"cfg-param\";\n\t\t\t\treg = <0x260000 0x400000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@660000 {\n\t\t\t\tlabel = \"log\";\n\t\t\t\treg = <0x660000 0x400000>;\n\t\t\t};\n\n\t\t\tpartition@a60000 {\n\t\t\t\tlabel = \"oops\";\n\t\t\t\treg = <0xa60000 0xa0000>;\n\t\t\t};\n\n\t\t\tpartition@b00000 {\n\t\t\t\tlabel = \"reserved3\";\n\t\t\t\treg = <0xb00000 0x500000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@1000000 {\n\t\t\t\tlabel = \"web\";\n\t\t\t\treg = <0x1000000 0x800000>;\n\t\t\t};\n\n\t\t\tpartition@1800000 {\n\t\t\t\tlabel = \"rootfs\";\n\t\t\t\treg = <0x1800000 0x1d00000>;\n\t\t\t};\n\n\t\t\tpartition@3500000 {\n\t\t\t\tlabel = \"data\";\n\t\t\t\treg = <0x3500000 0x1900000>;\n\t\t\t};\n\n\t\t\tpartition@4e00000 {\n\t\t\t\tlabel = \"fota\";\n\t\t\t\treg = <0x4e00000 0x3200000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&qpic_bam {\n\tstatus = \"okay\";\n};\n\n&tlmm {\n\ti2c_0_pins: i2c_0_pinmux {\n\t\tmux {\n\t\t\tpins = \"gpio20\", \"gpio21\";\n\t\t\tfunction = \"blsp_i2c0\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tmdio_pins: mdio_pinmux {\n\t\tmux_1 {\n\t\t\tpins = \"gpio6\";\n\t\t\tfunction = \"mdio\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tmux_2 {\n\t\t\tpins = \"gpio7\";\n\t\t\tfunction = \"mdc\";\n\t\t\tbias-pull-up;\n\t\t};\n\t};\n\n\tnand_pins: nand_pins {\n\t\tpullups {\n\t\t\tpins =\t\"gpio52\", \"gpio53\", \"gpio58\",\n\t\t\t\t\"gpio59\";\n\t\t\tfunction = \"qpic\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tpulldowns {\n\t\t\tpins =\t\"gpio54\", \"gpio55\", \"gpio56\",\n\t\t\t\t\"gpio57\", \"gpio60\",\n\t\t\t\t\"gpio62\", \"gpio63\", \"gpio64\",\n\t\t\t\t\"gpio65\", \"gpio66\", \"gpio67\",\n\t\t\t\t\"gpio69\";\n\t\t\tfunction = \"qpic\";\n\t\t\tbias-pull-down;\n\t\t};\n\t};\n\n\tserial_pins: serial_pinmux {\n\t\tmux {\n\t\t\tpins = \"gpio16\", \"gpio17\";\n\t\t\tfunction = \"blsp_uart0\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tspi_0_pins: spi_0_pinmux {\n\t\tpinmux {\n\t\t\tfunction = \"blsp_spi0\";\n\t\t\tpins = \"gpio13\", \"gpio14\", \"gpio15\";\n\t\t\tdrive-strength = <12>;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tpinmux_cs {\n\t\t\tfunction = \"gpio\";\n\t\t\tpins = \"gpio12\";\n\t\t\tdrive-strength = <2>;\n\t\t\tbias-disable;\n\t\t\toutput-high;\n\t\t};\n\t};\n};\n\n&usb2_hs_phy {\n\tstatus = \"okay\";\n};\n\n&usb3_ss_phy {\n\tstatus = \"okay\";\n};\n\n&usb3_hs_phy {\n\tstatus = \"okay\";\n};\n\n&wifi0 {\n\tstatus = \"okay\";\n\tnvmem-cell-names = \"pre-calibration\", \"mac-address\";\n\tnvmem-cells = <&precal_art_1000>, <&macaddr_config_0>;\n\tmac-address-increment = <2>;\n\tqcom,ath10k-calibration-variant = \"zte,mf286d\";\n};\n\n&wifi1 {\n\tstatus = \"okay\";\n\tnvmem-cell-names = \"pre-calibration\", \"mac-address\";\n\tnvmem-cells = <&precal_art_5000>, <&macaddr_config_0>;\n\tmac-address-increment = <3>;\n\tqcom,ath10k-calibration-variant = \"zte,mf286d\";\n};\n"
  },
  {
    "path": "target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-mr8300.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qcom-ipq4019-xx8300.dtsi\"\n\n/ {\n\tmodel = \"Linksys MR8300 (Dallas)\";\n\tcompatible = \"linksys,mr8300\", \"qcom,ipq4019\";\n\n\taliases {\n\t\tled-boot = &led_blue;\n\t\tled-failsafe = &led_red;\n\t\tled-running = &led_blue;\n\t\tled-upgrade = &led_amber;\n\t\tserial0 = &blsp1_uart1;\n\t};\n\n\t// Top panel LEDs, above Linksys logo\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_red: red {\n\t\t\tlabel = \"red:alarm\";\n\t\t\tgpios = <&tlmm 47 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tled_amber: amber {\n\t\t\tlabel = \"amber:programming\";\n\t\t\tgpios = <&tlmm 22 GPIO_ACTIVE_HIGH>;\n\t\t\tpanic-indicator;\n\t\t};\n\n\t\tled_blue: blue {\n\t\t\tlabel = \"blue:power\";\n\t\t\tgpios = <&tlmm 46 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\t// On back panel, above USB socket\n\n\t\tled_usb: usb {\n\t\t\tlabel = \"green:usb\";\n\t\t\tgpios = <&tlmm 61 GPIO_ACTIVE_LOW>;\n\t\t\ttrigger-sources = <&usb3_port1>, <&usb3_port2>,\n\t\t\t\t\t  <&usb2_port1>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&tlmm 50 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tgpios = <&tlmm 18 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&wifi0 {\n\tstatus = \"okay\";\n\tqcom,ath10k-calibration-variant = \"linksys-mr8300-v0-fcc\";\n};\n\n&wifi1 {\n\tstatus = \"okay\";\n\tieee80211-freq-limit = <5170000 5330000>;\n\tqcom,ath10k-calibration-variant = \"linksys-mr8300-v0-fcc\";\n};\n\n&wifi2 {\n\tstatus = \"okay\";\n\tieee80211-freq-limit = <5490000 5835000>;\n\tqcom,ath10k-calibration-variant = \"linksys-mr8300-v0-fcc\";\n};\n"
  },
  {
    "path": "target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-oap100.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qcom-ipq4019.dtsi\"\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/soc/qcom,tcsr.h>\n\n/ {\n\tmodel = \"EdgeCore OAP-100\";\n\tcompatible = \"edgecore,oap100\";\n\n\taliases {\n\t\tled-boot = &led_system;\n\t\tled-failsafe = &led_system;\n\t\tled-running = &led_system;\n\t\tled-upgrade = &led_system;\n\t};\n\n\tchosen {\n\t\tbootargs-append = \" root=/dev/ubiblock0_1\";\n\t};\n\n\tsoc {\n\t\tmdio@90000 {\n\t\t\tstatus = \"okay\";\n\t\t\tpinctrl-0 = <&mdio_pins>;\n\t\t\tpinctrl-names = \"default\";\n\t\t};\n\n\t\tess-psgmii@98000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\ttcsr@1949000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1949000 0x100>;\n\t\t\tqcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;\n\t\t};\n\n\t\tess_tcsr@1953000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1953000 0x1000>;\n\t\t\tqcom,ess-interface-select = <TCSR_ESS_PSGMII>;\n\t\t};\n\n\t\ttcsr@1957000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1957000 0x100>;\n\t\t\tqcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;\n\t\t};\n\n\t\ttcsr@194b000 {\n\t\t\t/* select hostmode */\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x194b000 0x100>;\n\t\t\tqcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tusb2@60f8800 {\n\t\t\tstatus = \"okay\";\n\n\t\t\tdwc3@6000000 {\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\n\t\t\t\tusb2_port1: port@1 {\n\t\t\t\t\treg = <1>;\n\t\t\t\t\t#trigger-source-cells = <0>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tusb3@8af8800 {\n\t\t\tstatus = \"okay\";\n\n\t\t\tdwc3@8a00000 {\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\n\t\t\t\tusb3_port1: port@1 {\n\t\t\t\t\treg = <1>;\n\t\t\t\t\t#trigger-source-cells = <0>;\n\t\t\t\t};\n\n\t\t\t\tusb3_port2: port@2 {\n\t\t\t\t\treg = <2>;\n\t\t\t\t\t#trigger-source-cells = <0>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tcrypto@8e3a000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\twatchdog@b017000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tess-switch@c000000 {\n\t\t\tstatus = \"okay\";\n\t\t\tswitch_mac_mode = <0x0>; /* mac mode for RGMII RMII */\n\t\t\tswitch_initvlas = <0x0007c 0x54>; /* port0 status */\n\t\t\tswitch_lan_bmp = <0x10>;\n\t\t};\n\n\t\tedma@c080000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\t};\n\n\tkey {\n\t\tcompatible = \"gpio-keys\";\n\n\t\tbutton@1 {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&tlmm 18 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,input-type = <1>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_system: led_system {\n\t\t\tlabel = \"green:system\";\n\t\t\tgpios = <&tlmm 22 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tled_2g {\n\t\t\tlabel = \"blue:wlan2g\";\n\t\t\tgpios = <&tlmm 34 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tled_5g {\n\t\t\tlabel = \"blue:wlan5g\";\n\t\t\tgpios = <&tlmm 35 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n\n\tgpio_export {\n\t\tcompatible = \"gpio-export\";\n\t\t#size-cells = <0>;\n\n\t\tusb {\n\t\t\tgpio-export,name = \"usb-power\";\n\t\t\tgpio-export,output = <1>;\n\t\t\tgpios = <&tlmm 44 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tpoe {\n\t\t\tgpio-export,name = \"poe-power\";\n\t\t\tgpio-export,output = <0>;\n\t\t\tgpios = <&tlmm 45 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&tlmm {\n\tserial_0_pins: serial_pinmux {\n\t\tmux {\n\t\t\tpins = \"gpio16\", \"gpio17\";\n\t\t\tfunction = \"blsp_uart0\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tspi_0_pins: spi_0_pinmux {\n\t\tpinmux {\n\t\t\tfunction = \"blsp_spi0\";\n\t\t\tpins = \"gpio13\", \"gpio14\", \"gpio15\";\n\t\t\tdrive-strength = <12>;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tpinmux_cs {\n\t\t\tfunction = \"gpio\";\n\t\t\tpins = \"gpio12\";\n\t\t\tdrive-strength = <2>;\n\t\t\tbias-disable;\n\t\t\toutput-high;\n\t\t};\n\t};\n\n\tnand_pins: nand_pins {\n\t\tpullups {\n\t\t\tpins = \"gpio53\", \"gpio58\", \"gpio59\";\n\t\t\tfunction = \"qpic\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tpulldowns {\n\t\t\tpins = \"gpio54\", \"gpio55\", \"gpio56\",\n\t\t\t\t\"gpio57\", \"gpio60\", \"gpio61\",\n\t\t\t\t\"gpio62\", \"gpio63\", \"gpio64\",\n\t\t\t\t\"gpio65\", \"gpio66\", \"gpio67\",\n\t\t\t\t\"gpio68\", \"gpio69\";\n\t\t\tfunction = \"qpic\";\n\t\t\tbias-pull-down;\n\t\t};\n\t};\n\n\tmdio_pins: mdio_pinmux {\n\t\tmux_1 {\n\t\t\tpins = \"gpio6\";\n\t\t\tfunction = \"mdio\";\n\t\t\tbias-pull-up;\n\t\t};\n\t\tmux_2 {\n\t\t\tpins = \"gpio7\";\n\t\t\tfunction = \"mdc\";\n\t\t\tbias-pull-up;\n\t\t};\n\t};\n};\n\n&cryptobam {\n\tstatus = \"okay\";\n};\n\n&blsp1_spi1 {\n\tpinctrl-0 = <&spi_0_pins>;\n\tpinctrl-names = \"default\";\n\tstatus = \"okay\";\n\tcs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;\n\n\tflash@0 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tlinux,modalias = \"m25p80\", \"gd25q256\";\n\t\tspi-max-frequency = <24000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition0@0 {\n\t\t\t\tlabel = \"0:SBL1\";\n\t\t\t\treg = <0x00000000 0x00040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition1@40000 {\n\t\t\t\tlabel = \"0:MIBIB\";\n\t\t\t\treg = <0x00040000 0x00020000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition2@60000 {\n\t\t\t\tlabel = \"0:QSEE\";\n\t\t\t\treg = <0x00060000 0x00060000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition3@c0000 {\n\t\t\t\tlabel = \"0:CDT\";\n\t\t\t\treg = <0x000c0000 0x00010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition4@d0000 {\n\t\t\t\tlabel = \"0:DDRPARAMS\";\n\t\t\t\treg = <0x000d0000 0x00010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition5@e0000 {\n\t\t\t\tlabel = \"0:APPSBLENV\";\n\t\t\t\treg = <0x000e0000 0x00010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition6@f0000 {\n\t\t\t\tlabel = \"0:APPSBL\";\n\t\t\t\treg = <0x000f0000 0x00080000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition7@170000 {\n\t\t\t\tlabel = \"0:ART\";\n\t\t\t\treg = <0x00170000 0x00010000>;\n\t\t\t\tread-only;\n\t\t\t\tcompatible = \"nvmem-cells\";\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\n\t\t\t\tprecal_art_1000: precal@1000 {\n\t\t\t\t\treg = <0x1000 0x2f20>;\n\t\t\t\t};\n\n\t\t\t\tprecal_art_5000: precal@5000 {\n\t\t\t\t\treg = <0x5000 0x2f20>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t};\n};\n\n&nand {\n\tpinctrl-0 = <&nand_pins>;\n\tpinctrl-names = \"default\";\n\tstatus = \"okay\";\n\n\tnand@0 {\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"rootfs\";\n\t\t\t\treg = <0x00000000 0x4000000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&blsp_dma {\n\tstatus = \"okay\";\n};\n\n&blsp1_uart1 {\n\tpinctrl-0 = <&serial_0_pins>;\n\tpinctrl-names = \"default\";\n\tstatus = \"okay\";\n};\n\n&qpic_bam {\n\tstatus = \"okay\";\n};\n\n&wifi0 {\n\tstatus = \"okay\";\n\tnvmem-cell-names = \"pre-calibration\";\n\tnvmem-cells = <&precal_art_1000>;\n\tqcom,ath10k-calibration-variant = \"Edgecore OAP100\";\n};\n\n&wifi1 {\n\tstatus = \"okay\";\n\tnvmem-cell-names = \"pre-calibration\";\n\tnvmem-cells = <&precal_art_5000>;\n\tqcom,ath10k-calibration-variant = \"Edgecore OAP100\";\n};\n\n&usb3_ss_phy {\n\tstatus = \"okay\";\n};\n\n&usb3_hs_phy {\n\tstatus = \"okay\";\n};\n\n&usb2_hs_phy {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-orbi.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qcom-ipq4019.dtsi\"\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/soc/qcom,tcsr.h>\n\n/ {\n\taliases {\n\t\tled-boot = &led_status_white;\n\t\tled-failsafe = &led_status_red;\n\t\tled-running = &led_status_green;\n\t\tled-upgrade = &led_status_blue;\n\t};\n\n\tsoc {\n\t\trng@22000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tmdio@90000 {\n\t\t\tstatus = \"okay\";\n\n\t\t\tpinctrl-0 = <&mdio_pins>;\n\t\t\tpinctrl-names = \"default\";\n\t\t};\n\n\t\tess-psgmii@98000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tcounter@4a1000 {\n\t\t\tcompatible = \"qcom,qca-gcnt\";\n\t\t\treg = <0x4a1000 0x4>;\n\t\t};\n\n\t\ttcsr@1949000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1949000 0x100>;\n\t\t\tqcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;\n\t\t};\n\n\t\ttcsr@194b000 {\n\t\t\tstatus = \"okay\";\n\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x194b000 0x100>;\n\t\t\tqcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;\n\t\t};\n\n\t\tess_tcsr@1953000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1953000 0x1000>;\n\t\t\tqcom,ess-interface-select = <TCSR_ESS_PSGMII>;\n\t\t};\n\n\t\ttcsr@1957000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1957000 0x100>;\n\t\t\tqcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;\n\t\t};\n\n\t\tcrypto@8e3a000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\twatchdog@b017000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tess-switch@c000000 {\n\t\t\tstatus = \"okay\";\n\n\t\t\tswitch_lan_bmp = <0x1c>;\n\t\t\tswitch_wan_bmp = <0x02>;\n\t\t};\n\n\t\tedma@c080000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&tlmm 18 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&tlmm 49 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled-0 {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&tlmm 63 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\tled-1 {\n\t\t\tlabel = \"red:power\";\n\t\t\tgpios = <&tlmm 64 GPIO_ACTIVE_HIGH>;\n\t\t\tpanic-indicator;\n\t\t};\n\n\t\tled_status_green: led-2 {\n\t\t\tlabel = \"green:status\";\n\t\t\tgpios = <&tlmm 53 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tled_status_red: led-3 {\n\t\t\tlabel = \"red:status\";\n\t\t\tgpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tled_status_blue: led-4 {\n\t\t\tlabel = \"blue:status\";\n\t\t\tgpios = <&tlmm 57 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tled_status_white: led-5 {\n\t\t\tlabel = \"white:status\";\n\t\t\tgpios = <&tlmm 60 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&vqmmc {\n\tstatus = \"okay\";\n};\n\n&sdhci {\n\tstatus = \"okay\";\n\n\tpinctrl-0 = <&sd_pins>;\n\tpinctrl-names = \"default\";\n\tcd-gpios = <&tlmm 22 GPIO_ACTIVE_LOW>;\n\tvqmmc-supply = <&vqmmc>;\n};\n\n&qpic_bam {\n\tstatus = \"okay\";\n};\n\n&tlmm {\n\tmdio_pins: mdio_pinmux {\n\t\tmux_1 {\n\t\t\tpins = \"gpio6\";\n\t\t\tfunction = \"mdio\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tmux_2 {\n\t\t\tpins = \"gpio7\";\n\t\t\tfunction = \"mdc\";\n\t\t\tbias-pull-up;\n\t\t};\n\t};\n\n\tserial_pins: serial_pinmux {\n\t\tmux {\n\t\t\tpins = \"gpio16\", \"gpio17\";\n\t\t\tfunction = \"blsp_uart0\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\ti2c_0_pins: i2c_0_pinmux {\n\t\tpinmux {\n\t\t\tfunction = \"blsp_i2c0\";\n\t\t\tpins = \"gpio58\", \"gpio59\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tsd_pins: sd_pins {\n\t\tpinmux {\n\t\t\tfunction = \"sdio\";\n\t\t\tpins = \"gpio23\", \"gpio24\", \"gpio25\", \"gpio26\",\n\t\t\t\t\"gpio28\", \"gpio29\", \"gpio30\", \"gpio31\";\n\t\t\tdrive-strength = <10>;\n\t\t};\n\n\t\tpinmux_sd_clk {\n\t\t\tfunction = \"sdio\";\n\t\t\tpins = \"gpio27\";\n\t\t\tdrive-strength = <16>;\n\t\t};\n\n\t\tpinmux_sd7 {\n\t\t\tfunction = \"sdio\";\n\t\t\tpins = \"gpio32\";\n\t\t\tdrive-strength = <10>;\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&blsp_dma {\n\tstatus = \"okay\";\n};\n\n&blsp1_i2c3 {\n\tpinctrl-0 = <&i2c_0_pins>;\n\tpinctrl-names = \"default\";\n\n\tstatus = \"okay\";\n\n\tled-controller@27 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tcompatible = \"ti,tlc59108\"; /* really is tlc59208f */\n\t\treg = <0x27>;\n\n\t\tled0@0 {\n\t\t\tlabel = \"rgb:led0\";\n\t\t\treg = <0x0>;\n\t\t\tlinux,default-trigger = \"default-on\";\n\t\t};\n\n\t\tled1@1 {\n\t\t\tlabel = \"rgb:led1\";\n\t\t\treg = <0x1>;\n\t\t\tlinux,default-trigger = \"default-on\";\n\t\t};\n\n\t\tled2@2 {\n\t\t\tlabel = \"rgb:led2\";\n\t\t\treg = <0x2>;\n\t\t\tlinux,default-trigger = \"default-on\";\n\t\t};\n\n\t\tled3@3 {\n\t\t\tlabel = \"rgb:led3\";\n\t\t\treg = <0x3>;\n\t\t\tlinux,default-trigger = \"default-on\";\n\t\t};\n\n\t\tled4@4 {\n\t\t\tlabel = \"rgb:led4\";\n\t\t\treg = <0x4>;\n\t\t\tlinux,default-trigger = \"default-on\";\n\t\t};\n\n\t\tled5@5 {\n\t\t\tlabel = \"rgb:led5\";\n\t\t\treg = <0x5>;\n\t\t\tlinux,default-trigger = \"default-on\";\n\t\t};\n\n\t\tled6@6 {\n\t\t\tlabel = \"rgb:led6\";\n\t\t\treg = <0x6>;\n\t\t\tlinux,default-trigger = \"default-on\";\n\t\t};\n\n\t\tled7@7 {\n\t\t\tlabel = \"rgb:led7\";\n\t\t\treg = <0x7>;\n\t\t\tlinux,default-trigger = \"default-on\";\n\t\t};\n\t};\n};\n\n&blsp1_uart1 {\n\tstatus = \"okay\";\n\n\tpinctrl-0 = <&serial_pins>;\n\tpinctrl-names = \"default\";\n};\n\n&cryptobam {\n\tstatus = \"okay\";\n};\n\n&gmac0 {\n\tvlan_tag = <1 0x1c>;\n};\n\n&gmac1 {\n\tqcom,phy_mdio_addr = <0>;\n\tvlan_tag = <2 0x02>;\n};\n\n&pcie0 {\n\tstatus = \"okay\";\n\n\tperst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;\n\twake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>;\n\n\tbridge@0,0 {\n\t\treg = <0x00000000 0 0 0 0>;\n\t\t#address-cells = <3>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\twifi@1,0 {\n\t\t\tcompatible = \"qcom,ath10k\";\n\t\t\tstatus = \"okay\";\n\t\t\treg = <0x00010000 0 0 0 0>;\n\t\t\tieee80211-freq-limit = <5470000 5875000>;\n\t\t\tqcom,ath10k-calibration-variant = \"Netgear-Orbi-Pro-SRK60\";\n\t\t};\n\t};\n};\n\n&wifi0 {\n\tstatus = \"okay\";\n\n\tqcom,ath10k-calibration-variant = \"Netgear-Orbi-Pro-SRK60\";\n};\n\n&wifi1 {\n\tstatus = \"okay\";\n\n\tqcom,ath10k-calibration-variant = \"Netgear-Orbi-Pro-SRK60\";\n};\n"
  },
  {
    "path": "target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-pa2200.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n/* Copyright (c) 2017-2020, Sven Eckelmann <sven@narfation.org>\n * Copyright (c) 2018, Marek Lindner <marek.lindner@kaiwoo.ai>\n */\n\n#include \"qcom-ipq4019.dtsi\"\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/soc/qcom,tcsr.h>\n\n/ {\n\tmodel = \"Plasma Cloud PA2200\";\n\tcompatible = \"plasmacloud,pa2200\";\n\n\tsoc {\n\t\trng@22000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tmdio@90000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tess-psgmii@98000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\ttcsr@1949000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1949000 0x100>;\n\t\t\tqcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;\n\t\t};\n\n\t\tess_tcsr@1953000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1953000 0x1000>;\n\t\t\tqcom,ess-interface-select = <TCSR_ESS_PSGMII>;\n\t\t};\n\n\t\ttcsr@1957000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1957000 0x100>;\n\t\t\tqcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;\n\t\t};\n\n\t\tcrypto@8e3a000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\twatchdog@b017000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tess-switch@c000000 {\n\t\t\tswitch_lan_bmp = <0x10>;\n\t\t\tswitch_wan_bmp = <0x20>;\n\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tedma@c080000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&tlmm 18 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART >;\n\t\t};\n\t};\n\n\taliases {\n\t\tled-boot = &led_power_orange;\n\t\tled-failsafe = &led_status_blue;\n\t\tled-running = &led_power_orange;\n\t\tled-upgrade = &led_status_blue;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power_orange: power_orange {\n\t\t\tlabel = \"orange:power\";\n\t\t\tgpios = <&tlmm 43 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\t2g_blue {\n\t\t\tlabel = \"blue:2g\";\n\t\t\tgpios = <&tlmm 46 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\n\t\t2g_green {\n\t\t\tlabel = \"green:5g1\";\n\t\t\tgpios = <&tlmm 47 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\t5g2_green {\n\t\t\tlabel = \"green:5g2\";\n\t\t\tgpios = <&tlmm 48 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy2tpt\";\n\t\t};\n\n\t\tled_status_blue: status_blue {\n\t\t\tlabel = \"blue:status\";\n\t\t\tgpios = <&tlmm 50 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&tlmm {\n\tserial_pins: serial_pinmux {\n\t\tmux {\n\t\t\tpins = \"gpio16\", \"gpio17\";\n\t\t\tfunction = \"blsp_uart0\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tspi_0_pins: spi_0_pinmux {\n\t\tpin {\n\t\t\tfunction = \"blsp_spi0\";\n\t\t\tpins = \"gpio13\", \"gpio14\", \"gpio15\";\n\t\t\tdrive-strength = <12>;\n\t\t\tbias-disable;\n\t\t};\n\t\tpin_cs {\n\t\t\tfunction = \"gpio\";\n\t\t\tpins = \"gpio12\";\n\t\t\tdrive-strength = <2>;\n\t\t\tbias-disable;\n\t\t\toutput-high;\n\t\t};\n\t};\n};\n\n&blsp_dma {\n\tstatus = \"okay\";\n};\n\n&blsp1_spi1 {\n\tpinctrl-0 = <&spi_0_pins>;\n\tpinctrl-names = \"default\";\n\tstatus = \"okay\";\n\tcs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;\n\n\tflash@0 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <24000000>;\n\t\t/* partitions are passed via bootloader */\n\t};\n};\n\n&blsp1_uart1 {\n\tpinctrl-0 = <&serial_pins>;\n\tpinctrl-names = \"default\";\n\tstatus = \"okay\";\n};\n\n&cryptobam {\n\tstatus = \"okay\";\n};\n\n&gmac0 {\n\tqcom,phy_mdio_addr = <3>;\n\tqcom,poll_required = <1>;\n\tqcom,forced_speed = <1000>;\n\tqcom,forced_duplex = <1>;\n\tvlan_tag = <1 0x10>;\n};\n\n&pcie0 {\n\tstatus = \"okay\";\n\tperst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;\n\twake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>;\n\n\tbridge@0,0 {\n\t\treg = <0x00000000 0 0 0 0>;\n\t\t#address-cells = <3>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\twifi2: wifi@1,0 {\n\t\t\tcompatible = \"qcom,ath10k\";\n\t\t\tstatus = \"okay\";\n\t\t\treg = <0x00010000 0 0 0 0>;\n\t\t\tqcom,ath10k-calibration-variant = \"PlasmaCloud-PA2200\";\n\t\t\tieee80211-freq-limit = <5170000 5350000>;\n\t\t};\n\t};\n};\n\n&wifi0 {\n\tstatus = \"okay\";\n\tqcom,ath10k-calibration-variant = \"PlasmaCloud-PA2200\";\n};\n\n&wifi1 {\n\tstatus = \"okay\";\n\tqcom,ath10k-calibration-variant = \"PlasmaCloud-PA2200\";\n\tieee80211-freq-limit = <5470000 5875000>;\n};\n"
  },
  {
    "path": "target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-r619ac-128m.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qcom-ipq4019-r619ac.dtsi\"\n\n/ {\n\tmodel = \"P&W R619AC 128M\";\n\tcompatible = \"p2w,r619ac-128m\";\n};\n\n&nand_rootfs {\n\t/*\n\t * Watch out: stock MIBIB is set up for a 64MiB chip.\n\t * If a 128MiB flash chip is used, make sure to have\n\t * the right values in MIBIB or the device might not\n\t * boot.\n\t */\n\treg = <0x0 0x8000000>;\n};\n"
  },
  {
    "path": "target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-r619ac-64m.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qcom-ipq4019-r619ac.dtsi\"\n\n/ {\n\tmodel = \"P&W R619AC 64M\";\n\tcompatible = \"p2w,r619ac-64m\";\n};\n\n&nand_rootfs {\n\treg = <0x0 0x4000000>;\n};\n"
  },
  {
    "path": "target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-r619ac.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qcom-ipq4019.dtsi\"\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/soc/qcom,tcsr.h>\n#include <dt-bindings/leds/common.h>\n\n/ {\n\tchosen {\n\t\tbootargs-append = \" ubi.mtd=ubi root=/dev/ubiblock0_1\";\n\t};\n\n\taliases {\n\t\tled-boot = &led_sys;\n\t\tled-failsafe = &led_sys;\n\t\tled-running = &led_sys;\n\t\tled-upgrade = &led_sys;\n\t\tlabel-mac-device = &gmac0;\n\t};\n\n\tsoc {\n\t\trng@22000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tmdio@90000 {\n\t\t\tstatus = \"okay\";\n\t\t\tpinctrl-0 = <&mdio_pins>;\n\t\t\tpinctrl-names = \"default\";\n\t\t};\n\n\t\tess-psgmii@98000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\ttcsr@1949000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1949000 0x100>;\n\t\t\tqcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;\n\t\t};\n\n\t\ttcsr@194b000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x194b000 0x100>;\n\t\t\tqcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;\n\t\t};\n\n\t\tess_tcsr@1953000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1953000 0x1000>;\n\t\t\tqcom,ess-interface-select = <TCSR_ESS_PSGMII>;\n\t\t};\n\n\t\ttcsr@1957000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1957000 0x100>;\n\t\t\tqcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;\n\t\t};\n\n\t\tusb2@60f8800 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tusb3@8af8800 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tcrypto@8e3a000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\twatchdog@b017000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tess-switch@c000000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tedma@c080000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_sys: led-0 {\n\t\t\tlabel = \"blue:sys\";\n\t\t\tgpios = <&tlmm 39 GPIO_ACTIVE_HIGH>;\n\t\t\tcolor = <LED_COLOR_ID_BLUE>;\n\t\t\tfunction = LED_FUNCTION_POWER;\n\t\t};\n\n\t\tled-1 {\n\t\t\tlabel = \"blue:wlan2g\";\n\t\t\tgpios = <&tlmm 32 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t\tcolor = <LED_COLOR_ID_BLUE>;\n\t\t\tfunction = LED_FUNCTION_WLAN;\n\t\t\tfunction-enumerator = <0>;\n\t\t};\n\n\t\tled-2 {\n\t\t\tlabel = \"blue:wlan5g\";\n\t\t\tgpios = <&tlmm 50 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t\tcolor = <LED_COLOR_ID_BLUE>;\n\t\t\tfunction = LED_FUNCTION_WLAN;\n\t\t\tfunction-enumerator = <1>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&tlmm 18 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n};\n\n&blsp_dma {\n\tstatus = \"okay\";\n};\n\n&blsp1_spi1 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\treg = <0>;\n\t\tcompatible = \"jedec,spi-nor\";\n\t\tspi-max-frequency = <24000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"SBL1\";\n\t\t\t\treg = <0x0 0x40000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"MIBIB\";\n\t\t\t\treg = <0x40000 0x20000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@60000 {\n\t\t\t\tlabel = \"QSEE\";\n\t\t\t\treg = <0x60000 0x60000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@c0000 {\n\t\t\t\tlabel = \"CDT\";\n\t\t\t\treg = <0xc0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@d0000 {\n\t\t\t\tlabel = \"DDRPARAMS\";\n\t\t\t\treg = <0xd0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@e0000 {\n\t\t\t\tlabel = \"APPSBLENV\";\n\t\t\t\treg = <0xe0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@f0000 {\n\t\t\t\tlabel = \"APPSBL\";\n\t\t\t\treg = <0xf0000 0x80000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@170000 {\n\t\t\t\tlabel = \"ART\";\n\t\t\t\treg = <0x170000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t\tcompatible = \"nvmem-cells\";\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\n\t\t\t\tprecal_art_1000: precal@1000 {\n\t\t\t\t\treg = <0x1000 0x2f20>;\n\t\t\t\t};\n\n\t\t\t\tprecal_art_5000: precal@5000 {\n\t\t\t\t\treg = <0x5000 0x2f20>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t};\n};\n\n&nand {\n\tstatus = \"okay\";\n\n\tnand@0 {\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tnand_rootfs: partition@0 {\n\t\t\t\tlabel = \"ubi\";\n\t\t\t\t/* reg defined in 64M/128M variant dts. */\n\t\t\t};\n\t\t};\n\t};\n};\n\n&blsp1_uart1 {\n\tpinctrl-0 = <&serial_0_pins>;\n\tpinctrl-names = \"default\";\n\tstatus = \"okay\";\n};\n\n&cryptobam {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\tstatus = \"okay\";\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pcie_pins>;\n\tperst-gpio = <&tlmm 4 GPIO_ACTIVE_LOW>;\n\twake-gpio = <&tlmm 40 GPIO_ACTIVE_HIGH>;\n\n\t/* Free slot for use */\n\tbridge@0,0 {\n\t\treg = <0x00000000 0 0 0 0>;\n\t\t#address-cells = <3>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\t};\n};\n\n&qpic_bam {\n\tstatus = \"okay\";\n};\n\n&sdhci {\n\tpinctrl-0 = <&sd_0_pins>;\n\tpinctrl-names = \"default\";\n\tvqmmc-supply = <&vqmmc>;\n\tstatus = \"okay\";\n};\n\n&tlmm {\n\tpcie_pins: pcie_pinmux {\n\t\tmux {\n\t\t\tpins = \"gpio2\";\n\t\t\tfunction = \"gpio\";\n\t\t\toutput-low;\n\t\t\tbias-pull-down;\n\t\t};\n\t};\n\n\tmdio_pins: mdio_pinmux {\n\t\tmux_1 {\n\t\t\tpins = \"gpio6\";\n\t\t\tfunction = \"mdio\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tmux_2 {\n\t\t\tpins = \"gpio7\";\n\t\t\tfunction = \"mdc\";\n\t\t\tbias-pull-up;\n\t\t};\n\t};\n\n\tsd_0_pins: sd_0_pinmux {\n\t\tmux_1 {\n\t\t\tpins = \"gpio23\", \"gpio24\", \"gpio25\", \"gpio26\", \"gpio28\";\n\t\t\tfunction = \"sdio\";\n\t\t\tdrive-strength = <10>;\n\t\t};\n\n\t\tmux_2 {\n\t\t\tpins = \"gpio27\";\n\t\t\tfunction = \"sdio\";\n\t\t\tdrive-strength = <16>;\n\t\t};\n\t};\n\n\tserial_0_pins: serial0-pinmux {\n\t\tmux {\n\t\t\tpins = \"gpio16\", \"gpio17\";\n\t\t\tfunction = \"blsp_uart0\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&ethphy0 {\n\tqcom,single-led-1000;\n\tqcom,single-led-100;\n\tqcom,single-led-10;\n};\n\n&ethphy1 {\n\tqcom,single-led-1000;\n\tqcom,single-led-100;\n\tqcom,single-led-10;\n};\n\n&ethphy2 {\n\tqcom,single-led-1000;\n\tqcom,single-led-100;\n\tqcom,single-led-10;\n};\n\n&ethphy3 {\n\tqcom,single-led-1000;\n\tqcom,single-led-100;\n\tqcom,single-led-10;\n};\n\n&ethphy4 {\n\tqcom,single-led-1000;\n\tqcom,single-led-100;\n\tqcom,single-led-10;\n};\n\n&usb3_ss_phy {\n\tstatus = \"okay\";\n};\n\n&usb3_hs_phy {\n\tstatus = \"okay\";\n};\n\n&usb2_hs_phy {\n\tstatus = \"okay\";\n};\n\n&vqmmc {\n\tstatus = \"okay\";\n};\n\n&wifi0 {\n\tstatus = \"okay\";\n\tnvmem-cell-names = \"pre-calibration\";\n\tnvmem-cells = <&precal_art_1000>;\n\tqcom,ath10k-calibration-variant = \"P&W R619AC\";\n};\n\n&wifi1 {\n\tstatus = \"okay\";\n\tnvmem-cell-names = \"pre-calibration\";\n\tnvmem-cells = <&precal_art_5000>;\n\tqcom,ath10k-calibration-variant = \"P&W R619AC\";\n};\n"
  },
  {
    "path": "target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-rbr50.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qcom-ipq4019-orbi.dtsi\"\n\n/ {\n\tmodel = \"NETGEAR RBR50\";\n\tcompatible = \"netgear,rbr50\";\n\n\tchosen {\n\t\tbootargs = \"root=/dev/mmcblk0p20 blkdevparts=mmcblk0:512K@17K(0:SBL1)ro,512K(0:BOOTCONFIG)ro,512K(0:QSEE)ro,512K(0:QSEE_ALT)ro,256K(0:CDT)ro,256K(0:CDT_ALT)ro,256K(0:DDRPARAMS)ro,256K(0:APPSBLENV)ro,1M(0:APPSBL)ro,1M(0:APPSBL_ALT)ro,256K(0:ART)ro,256K(ARTMTD)ro,2M(language)ro,256K(config)ro,256K(pot)ro,256K(traffic_meter)ro,256K(pot_bak)ro,256K(traffic_meter.bak)ro,3840K(kernel),31488K(rootfs),35328K@9233K(firmware),256K(mtdoops)ro,1457651200(reserved)ro,-(unallocated) rootfstype=squashfs,ext4 rootwait\";\n\t};\n\n\tsoc {\n\t\tusb2@60f8800 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tusb3@8af8800 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\t};\n};\n\n&usb3_hs_phy {\n\tstatus = \"okay\";\n};\n\n&usb2_hs_phy {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-rbs50.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qcom-ipq4019-orbi.dtsi\"\n\n/ {\n\tmodel = \"NETGEAR RBS50\";\n\tcompatible = \"netgear,rbs50\";\n\n\tchosen {\n\t\tbootargs = \"root=/dev/mmcblk0p20 blkdevparts=mmcblk0:512K@17K(0:SBL1)ro,512K(0:BOOTCONFIG)ro,512K(0:QSEE)ro,512K(0:QSEE_ALT)ro,256K(0:CDT)ro,256K(0:CDT_ALT)ro,256K(0:DDRPARAMS)ro,256K(0:APPSBLENV)ro,1M(0:APPSBL)ro,1M(0:APPSBL_ALT)ro,256K(0:ART)ro,256K(ARTMTD)ro,2M(language)ro,256K(config)ro,256K(pot)ro,256K(traffic_meter)ro,256K(pot_bak)ro,256K(traffic_meter.bak)ro,3840K(kernel),31488K(rootfs),35328K@9233K(firmware),256K(mtdoops)ro,1457651200(reserved)ro,-(unallocated) rootfstype=squashfs,ext4 rootwait\";\n\t};\n\n\tsoc {\n\t\tusb2@60f8800 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tusb3@8af8800 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\t};\n};\n\n&usb3_hs_phy {\n\tstatus = \"okay\";\n};\n\n&usb2_hs_phy {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-rt-ac42u.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qcom-ipq4019.dtsi\"\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/leds/common.h>\n#include <dt-bindings/soc/qcom,tcsr.h>\n\n/ {\n\tmodel = \"ASUS RT-AC42U\";\n\tcompatible = \"asus,rt-ac42u\";\n\n\tmemory {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x80000000 0x10000000>; /* 256MB */\n\t};\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tsoc {\n\t\trng@22000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tmdio@90000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tess-psgmii@98000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\ttcsr@1949000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1949000 0x100>;\n\t\t\tqcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;\n\t\t};\n\n\t\ttcsr@194b000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x194b000 0x100>;\n\t\t\tqcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;\n\t\t};\n\n\t\tess_tcsr@1953000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1953000 0x1000>;\n\t\t\tqcom,ess-interface-select = <TCSR_ESS_PSGMII>;\n\t\t};\n\n\t\ttcsr@1957000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1957000 0x100>;\n\t\t\tqcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;\n\t\t};\n\n\t\tusb3@8af8800 {\n\t\t\tstatus = \"okay\";\n\n\t\t\tdwc3@8a00000 {\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\n\t\t\t\tusb3_port1: port@1 {\n\t\t\t\t\treg = <1>;\n\t\t\t\t\t#trigger-source-cells = <0>;\n\t\t\t\t};\n\n\t\t\t\tusb3_port2: port@2 {\n\t\t\t\t\treg = <2>;\n\t\t\t\t\t#trigger-source-cells = <0>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tcrypto@8e3a000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\twatchdog@b017000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tess-switch@c000000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tedma@c080000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&tlmm 18 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&tlmm 11 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: led-0 {\n\t\t\tcolor = <LED_COLOR_ID_BLUE>;\n\t\t\tfunction = LED_FUNCTION_STATUS;\n\t\t\tgpios = <&tlmm 40 GPIO_ACTIVE_LOW>;\n\t\t\tlabel = \"blue:status\";\n\t\t};\n\n\t\tled-1 {\n\t\t\tcolor = <LED_COLOR_ID_BLUE>;\n\t\t\tfunction = LED_FUNCTION_WAN;\n\t\t\tgpios = <&tlmm 61 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"90000.mdio-1:04:link\";\n\t\t};\n\n\t\tled-2 {\n\t\t\tcolor = <LED_COLOR_ID_RED>;\n\t\t\tfunction = LED_FUNCTION_WAN;\n\t\t\tgpios = <&tlmm 68 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"none\";\n\t\t};\n\n\t\tled-3 {\n\t\t\tcolor = <LED_COLOR_ID_BLUE>;\n\t\t\tfunction = LED_FUNCTION_WLAN;\n\t\t\tfunction-enumerator = <0>;\n\t\t\tgpios = <&tlmm 52 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\n\t\tled-4 {\n\t\t\tcolor = <LED_COLOR_ID_BLUE>;\n\t\t\tfunction = LED_FUNCTION_WLAN;\n\t\t\tfunction-enumerator = <1>;\n\t\t\tgpios = <&tlmm 54 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\tled-5 {\n\t\t\tcolor = <LED_COLOR_ID_BLUE>;\n\t\t\tfunction = LED_FUNCTION_LAN;\n\t\t\tfunction-enumerator = <1>;\n\t\t\tgpios = <&tlmm 45 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled-6 {\n\t\t\tcolor = <LED_COLOR_ID_BLUE>;\n\t\t\tfunction = LED_FUNCTION_LAN;\n\t\t\tfunction-enumerator = <2>;\n\t\t\tgpios = <&tlmm 43 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled-7 {\n\t\t\tcolor = <LED_COLOR_ID_BLUE>;\n\t\t\tfunction = LED_FUNCTION_LAN;\n\t\t\tfunction-enumerator = <3>;\n\t\t\tgpios = <&tlmm 42 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled-8 {\n\t\t\tcolor = <LED_COLOR_ID_BLUE>;\n\t\t\tfunction = LED_FUNCTION_LAN;\n\t\t\tfunction-enumerator = <4>;\n\t\t\tgpios = <&tlmm 49 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&cryptobam {\n\tstatus = \"okay\";\n};\n\n&blsp_dma {\n\tstatus = \"okay\";\n};\n\n&qpic_bam {\n\tstatus = \"okay\";\n};\n\n&tlmm {\n\tserial_0_pins: serial0_pinmux {\n\t\tmux {\n\t\t\tpins = \"gpio16\", \"gpio17\";\n\t\t\tfunction = \"blsp_uart0\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tnand_pins: nand_pins {\n\t\tpullups {\n\t\t\tpins = \"gpio53\", \"gpio58\", \"gpio59\";\n\t\t\tfunction = \"qpic\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tpulldowns {\n\t\t\tpins = \"gpio55\", \"gpio56\", \"gpio57\", \"gpio60\",\n\t\t\t\t\"gpio62\", \"gpio63\", \"gpio64\", \"gpio65\",\n\t\t\t\t\"gpio66\", \"gpio67\", \"gpio69\";\n\t\t\tfunction = \"qpic\";\n\t\t\tbias-pull-down;\n\t\t};\n\t};\n};\n\n&blsp1_uart1 {\n\tpinctrl-0 = <&serial_0_pins>;\n\tpinctrl-names = \"default\";\n\tstatus = \"okay\";\n};\n\n&nand {\n\tpinctrl-0 = <&nand_pins>;\n\tpinctrl-names = \"default\";\n\tstatus = \"okay\";\n\n\tnand@0 {\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"SBL1\";\n\t\t\t\treg = <0x00000000 0x00080000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@80000 {\n\t\t\t\tlabel = \"MIBIB\";\n\t\t\t\treg = <0x00080000 0x00080000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@100000 {\n\t\t\t\tlabel = \"QSEE\";\n\t\t\t\treg = <0x00100000 0x00100000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@200000 {\n\t\t\t\tlabel = \"CDT\";\n\t\t\t\treg = <0x00200000 0x00080000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@280000 {\n\t\t\t\tlabel = \"APPSBL\";\n\t\t\t\treg = <0x00280000 0x00140000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@3C0000 {\n\t\t\t\tlabel = \"APPSBLENV\";\n\t\t\t\treg = <0x003C0000 0x00040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@400000 {\n\t\t\t\tlabel = \"ubi\";\n\t\t\t\treg = <0x00400000 0x07C00000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&usb3_ss_phy {\n\tstatus = \"okay\";\n};\n\n&usb3_hs_phy {\n\tstatus = \"okay\";\n};\n\n&wifi0 {\n\tstatus = \"okay\";\n\tqcom,ath10k-calibration-variant = \"ASUS-RT-AC42U\";\n};\n\n&pcie0 {\n\tstatus = \"okay\";\n\tperst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;\n\twake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>;\n\tclkreq-gpio = <&tlmm 39 GPIO_ACTIVE_LOW>;\n\n\tbridge@0,0 {\n\t\treg = <0x00000000 0 0 0 0>;\n\t\t#address-cells = <3>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\twifi2: wifi@1,0 {\n\t\t\tcompatible = \"qcom,ath10k\";\n\t\t\treg = <0x00010000 0 0 0 0>;\n\n\t\t\tqcom,ath10k-calibration-variant = \"ASUS-RT-AC42U\";\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-rtl30vw.dts",
    "content": "// SPDX-License-Identifier: ISC\n// Copyright (c) 2015, The Linux Foundation. All rights reserved.\n// Copyright (c) 2019, Cezary Jackiewicz <cezary@eko.one.pl>.\n// Copyright (c) 2020, Pawel Dembicki <paweldembicki@gmail.com>.\n\n#include \"qcom-ipq4019.dtsi\"\n#include <dt-bindings/soc/qcom,tcsr.h>\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"Cell C RTL30VW\";\n\tcompatible = \"cellc,rtl30vw\";\n\n\taliases {\n\t\tled-boot = &led_power_blue;\n\t\tled-failsafe = &led_power_red;\n\t\tled-running = &led_power_blue;\n\t\tled-upgrade = &led_power_red;\n\t};\n\n\tchosen {\n\t\tbootargs-append = \"ubi.mtd=ubifs root=/dev/ubiblock0_0 rootfstype=squashfs ro\";\n\t};\n\n\tled_spi {\n\t\tcompatible = \"spi-gpio\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tnum-chipselects = <1>;\n\n\t\tmosi-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;\n\t\tcs-gpios = <&tlmm 4 GPIO_ACTIVE_LOW>;\n\t\tsck-gpios = <&tlmm 58 GPIO_ACTIVE_LOW>;\n\n\t\tled_gpio: led_gpio@0 {\n\t\t\tcompatible = \"fairchild,74hc595\";\n\t\t\treg = <0>;\n\t\t\tgpio-controller;\n\t\t\t#gpio-cells = <2>;\n\t\t\tregisters-number = <2>;\n\t\t\tspi-max-frequency = <1000000>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power_blue: power_blue {\n\t\t\tgpios = <&led_gpio 0 GPIO_ACTIVE_HIGH>;\n\t\t\tlabel = \"blue:power\";\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\tled_power_red: power_red {\n\t\t\tgpios = <&led_gpio 1 GPIO_ACTIVE_HIGH>;\n\t\t\tlabel = \"red:power\";\n\t\t};\n\n\t\ttp28 {\n\t\t\tgpios = <&led_gpio 6 GPIO_ACTIVE_LOW>;\n\t\t\tlabel = \"ext:tp28\";\n\t\t\tdefault-state = \"keep\";\n\t\t};\n\n\t\ttp27 {\n\t\t\tgpios = <&led_gpio 7 GPIO_ACTIVE_LOW>;\n\t\t\tlabel = \"ext:tp27\";\n\t\t\tdefault-state = \"keep\";\n\t\t};\n\n\t\twlan2g {\n\t\t\tgpios = <&led_gpio 8 GPIO_ACTIVE_HIGH>;\n\t\t\tlabel = \"blue:wlan2g\";\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\twlan5g {\n\t\t\tgpios = <&led_gpio 9 GPIO_ACTIVE_HIGH>;\n\t\t\tlabel = \"blue:wlan5g\";\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\n\t\twps {\n\t\t\tgpios = <&led_gpio 10 GPIO_ACTIVE_HIGH>;\n\t\t\tlabel = \"blue:wps\";\n\t\t};\n\n\t\tvoip {\n\t\t\tgpios = <&led_gpio 11 GPIO_ACTIVE_HIGH>;\n\t\t\tlabel = \"blue:voip\";\n\t\t};\n\n\t\ts1 {\n\t\t\tgpios = <&led_gpio 12 GPIO_ACTIVE_HIGH>;\n\t\t\tlabel = \"blue:s1\";\n\t\t};\n\n\t\ts2 {\n\t\t\tgpios = <&led_gpio 13 GPIO_ACTIVE_HIGH>;\n\t\t\tlabel = \"blue:s2\";\n\t\t};\n\n\t\ts3 {\n\t\t\tgpios = <&led_gpio 14 GPIO_ACTIVE_HIGH>;\n\t\t\tlabel = \"blue:s3\";\n\t\t};\n\n\t\ts4 {\n\t\t\tgpios = <&led_gpio 15 GPIO_ACTIVE_HIGH>;\n\t\t\tlabel = \"blue:s4\";\n\t\t};\n\n\t\tsignal {\n\t\t\tgpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;\n\t\t\tlabel = \"red:signal\";\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tgpios = <&tlmm 5 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&tlmm 63 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tsoc {\n\t\trng@22000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tmdio@90000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tess-psgmii@98000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\ttcsr@1949000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1949000 0x100>;\n\t\t\tqcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;\n\t\t};\n\n\t\ttcsr@194b000 {\n\t\t\t/* select hostmode */\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x194b000 0x100>;\n\t\t\tqcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tess_tcsr@1953000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1953000 0x1000>;\n\t\t\tqcom,ess-interface-select = <TCSR_ESS_PSGMII>;\n\t\t};\n\n\t\ttcsr@1957000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1957000 0x100>;\n\t\t\tqcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;\n\t\t};\n\n\t\tusb2@60f8800 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tusb3@8af8800 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tcrypto@8e3a000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\twatchdog@b017000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tess-switch@c000000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tedma@c080000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\t};\n};\n\n&blsp_dma {\n\tstatus = \"okay\";\n};\n\n&blsp1_spi1 {\n\tpinctrl-0 = <&spi_0_pins>;\n\tpinctrl-names = \"default\";\n\tstatus = \"okay\";\n\tcs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>, <&tlmm 59 GPIO_ACTIVE_HIGH>;\n\n\tflash@0 {\n\t\t/*\"n25q128a11\" is required for proper nand recognition in u-boot. */\n\t\tcompatible = \"jedec,spi-nor\", \"n25q128a11\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0>;\n\t\tspi-max-frequency = <24000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"0:SBL1\";\n\t\t\t\treg = <0x0 0x40000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"0:MIBIB\";\n\t\t\t\treg = <0x40000 0x20000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@60000 {\n\t\t\t\tlabel = \"0:QSEE\";\n\t\t\t\treg = <0x60000 0x60000>;\n\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\tpartition@c0000 {\n\t\t\t\tlabel = \"0:CDT\";\n\t\t\t\treg = <0xc0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@d0000 {\n\t\t\t\tlabel = \"0:DDRPARAMS\";\n\t\t\t\treg = <0xd0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@e0000 {\n\t\t\t\tlabel = \"0:APPSBLENV\";\n\t\t\t\treg = <0xe0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@f0000 {\n\t\t\t\tlabel = \"0:APPSBL\";\n\t\t\t\treg = <0xf0000 0x80000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@170000 {\n\t\t\t\tlabel = \"0:ART\";\n\t\t\t\treg = <0x170000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@180000 {\n\t\t\t\tlabel = \"0:BOOTCONFIG\";\n\t\t\t\treg = <0x180000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n\n\tflash@1 {\n\t\t/*\n\t\t * Factory U-boot looks in 0:BOOTCONFIG partition for active\n\t\t * partitions settings and mangle partition config. So kernel\n\t\t * /kernel_1 and rootfs/rootfs_1 pairs can be swaped.\n\t\t * It isn't a problem but we never can be sure where OFW put\n\t\t * factory images. \"spinand,mt29f\" value is required for proper\n\t\t * nand recognition in u-boot.\n\t\t */\n\t\tcompatible = \"spi-nand\",\"spinand,mt29f\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <1>;\n\t\tspi-max-frequency = <24000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"kernel\";\n\t\t\t\treg = <0x0 0x400000>;\n\t\t\t};\n\n\t\t\tpartition@400000 {\n\t\t\t\tlabel = \"rootfs\";\n\t\t\t\treg = <0x400000 0x2000000>;\n\t\t\t};\n\n\t\t\tpartition@2400000 {\n\t\t\t\tlabel = \"kernel_1\";\n\t\t\t\treg = <0x2400000 0x400000>;\n\t\t\t};\n\n\t\t\tpartition@2800000 {\n\t\t\t\tlabel = \"rootfs_1\";\n\t\t\t\treg = <0x2800000 0x2000000>;\n\t\t\t};\n\n\t\t\tpartition@4800000 {\n\t\t\t\tlabel = \"ubifs\";\n\t\t\t\treg = <0x4800000 0x3800000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&blsp1_uart1 {\n\tpinctrl-0 = <&serial_pins>;\n\tpinctrl-names = \"default\";\n\tstatus = \"okay\";\n};\n\n&cryptobam {\n\tstatus = \"okay\";\n};\n\n&tlmm {\n\tserial_pins: serial_pinmux {\n\t\tmux {\n\t\t\tpins = \"gpio60\", \"gpio61\";\n\t\t\tfunction = \"blsp_uart0\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tspi_0_pins: spi_0_pinmux {\n\t\tpinmux {\n\t\t\tfunction = \"blsp_spi0\";\n\t\t\tpins = \"gpio55\", \"gpio56\", \"gpio57\";\n\t\t\tdrive-strength = <12>;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tpinmux_cs {\n\t\t\tfunction = \"gpio\";\n\t\t\tpins = \"gpio54\", \"gpio59\";\n\t\t\tdrive-strength = <2>;\n\t\t\tbias-disable;\n\t\t\toutput-high;\n\t\t};\n\t};\n};\n\n&usb2_hs_phy {\n\tstatus = \"okay\";\n};\n\n&usb3_ss_phy {\n\tstatus = \"okay\";\n};\n\n&usb3_hs_phy {\n\tstatus = \"okay\";\n};\n\n&wifi0 {\n\tstatus = \"okay\";\n\tqcom,ath10k-calibration-variant = \"cellc,rtl30vw\";\n};\n\n&wifi1 {\n\tstatus = \"okay\";\n\tqcom,ath10k-calibration-variant = \"cellc,rtl30vw\";\n};\n"
  },
  {
    "path": "target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-srr60.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qcom-ipq4019-orbi.dtsi\"\n\n/ {\n\tmodel = \"NETGEAR SRR60\";\n\tcompatible = \"netgear,srr60\";\n\n\tchosen {\n\t\tbootargs = \"root=/dev/mmcblk0p20 blkdevparts=mmcblk0:512K@17K(0:SBL1)ro,512K(0:BOOTCONFIG)ro,512K(0:QSEE)ro,512K(0:QSEE_1)ro,256K(0:CDT)ro,256K(0:CDT_1)ro,512K(0:BOOTCONFIG1)ro,256K(0:APPSBLENV)ro,1M(0:APPSBL)ro,1M(0:APPSBL_1)ro,256K(0:ART)ro,256K(ARTMTD)ro,2M(language)ro,256K(config)ro,256K(pot)ro,256K(traffic_meter)ro,256K(pot_bak)ro,256K(traffic_meter.bak)ro,3840K(kernel),31488K(rootfs),35328K@9233K(firmware),256K(mtdoops)ro,64K(cert)ro,3840K(kernel-2)ro,31488K(rootfs-2)ro,35328K@44881K(firmware-2)ro,5M(device_table)ro,17M(cp_file)ro,102737K(reserved)ro,-(unallocated) rootfstype=squashfs,ext4 rootwait\";\n\t};\n};\n"
  },
  {
    "path": "target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-srs60.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qcom-ipq4019-orbi.dtsi\"\n\n/ {\n\tmodel = \"NETGEAR SRS60\";\n\tcompatible = \"netgear,srs60\";\n\n\tchosen {\n\t\tbootargs = \"root=/dev/mmcblk0p20 blkdevparts=mmcblk0:512K@17K(0:SBL1)ro,512K(0:BOOTCONFIG)ro,512K(0:QSEE)ro,512K(0:QSEE_1)ro,256K(0:CDT)ro,256K(0:CDT_1)ro,512K(0:BOOTCONFIG1)ro,256K(0:APPSBLENV)ro,1M(0:APPSBL)ro,1M(0:APPSBL_1)ro,256K(0:ART)ro,256K(ARTMTD)ro,2M(language)ro,256K(config)ro,256K(pot)ro,256K(traffic_meter)ro,256K(pot_bak)ro,256K(traffic_meter.bak)ro,3840K(kernel),31488K(rootfs),35328K@9233K(firmware),256K(mtdoops)ro,64K(cert)ro,3840K(kernel-2)ro,31488K(rootfs-2)ro,35328K@44881K(firmware-2)ro,5M(device_table)ro,17M(cp_file)ro,102737K(reserved)ro,-(unallocated) rootfstype=squashfs,ext4 rootwait\";\n\t};\n};\n"
  },
  {
    "path": "target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-u4019-32m.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qcom-ipq4019-u4019.dtsi\"\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"Unielec U4019 (32M)\";\n\tcompatible = \"unielec,u4019-32m\",\"unielec,u4019\",\"qcom,ipq4019\";\n};\n\n&blsp1_spi1 {\n\tpinctrl-0 = <&spi_0_pins>;\n\tpinctrl-names = \"default\";\n\tstatus = \"okay\";\n\tcs-gpios = <&tlmm 12 GPIO_ACTIVE_LOW>;\n\n\tflash@0 {\n\t\treg = <0>;\n\t\tcompatible = \"jedec,spi-nor\";\n\t\tspi-max-frequency = <24000000>;\n\t\tbroken-flash-reset;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"0:SBL1\";\n\t\t\t\treg = <0x0 0x40000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"0:MIBIB\";\n\t\t\t\treg = <0x40000 0x20000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@60000 {\n\t\t\t\tlabel = \"0:QSEE\";\n\t\t\t\treg = <0x60000 0x60000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@c0000 {\n\t\t\t\tlabel = \"0:CDT\";\n\t\t\t\treg = <0xc0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@d0000 {\n\t\t\t\tlabel = \"0:DDRPARAMS\";\n\t\t\t\treg = <0xd0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@e0000 {\n\t\t\t\tlabel = \"0:APPSBLENV\";\n\t\t\t\treg = <0xe0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@f0000 {\n\t\t\t\tlabel = \"0:APPSBL\";\n\t\t\t\treg = <0xf0000 0x80000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@170000 {\n\t\t\t\tlabel = \"0:ART\";\n\t\t\t\treg = <0x170000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t\tcompatible = \"nvmem-cells\";\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\n\t\t\t\tprecal_art_1000: precal@1000 {\n\t\t\t\t\treg = <0x1000 0x2f20>;\n\t\t\t\t};\n\n\t\t\t\tprecal_art_5000: precal@5000 {\n\t\t\t\t\treg = <0x5000 0x2f20>;\n\t\t\t\t};\n\t\t\t};\n\t\t\tpartition@180000 {\n\t\t\t\tcompatible = \"denx,fit\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x180000 0x1e80000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n"
  },
  {
    "path": "target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-u4019.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qcom-ipq4019.dtsi\"\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/soc/qcom,tcsr.h>\n\n/ {\n\tcompatible = \"unielec,u4019\",\"qcom,ipq4019\";\n\n\tsoc {\n\t\trng@22000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tmdio@90000 {\n\t\t\tstatus = \"okay\";\n\t\t\tpinctrl-0 = <&mdio_pins>;\n\t\t\tpinctrl-names = \"default\";\n\t\t\treset-gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;\n\t\t\treset-delay-us = <2000>;\n\t\t};\n\n\t\tess-psgmii@98000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\ttcsr@1949000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1949000 0x100>;\n\t\t\tqcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;\n\t\t};\n\n\t\ttcsr@194b000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x194b000 0x100>;\n\t\t\tqcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tess_tcsr@1953000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1953000 0x1000>;\n\t\t\tqcom,ess-interface-select = <TCSR_ESS_PSGMII>;\n\t\t};\n\n\t\ttcsr@1957000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1957000 0x100>;\n\t\t\tqcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;\n\t\t};\n\n\t\tusb2@60f8800 {\n\t\t\tstatus = \"okay\";\n\n\t\t\tdwc3@6000000 {\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\n\t\t\t\tport@1 {\n\t\t\t\t\treg = <1>;\n\t\t\t\t\t#trigger-source-cells = <0>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tusb3@8af8800 {\n\t\t\tstatus = \"okay\";\n\n\t\t\tdwc3@8a00000 {\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\n\t\t\t\tport@1 {\n\t\t\t\t\treg = <1>;\n\t\t\t\t\t#trigger-source-cells = <0>;\n\t\t\t\t};\n\n\t\t\t\tport@2 {\n\t\t\t\t\treg = <2>;\n\t\t\t\t\t#trigger-source-cells = <0>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\twatchdog@b017000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tess-switch@c000000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tedma@c080000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\taliases {\n\t\t\tled-boot = &led_status;\n\t\t\tled-failsafe = &led_status;\n\t\t\tled-running = &led_status;\n\t\t\tled-upgrade = &led_status;\n\t\t\tserial0 = &blsp1_uart1;\n\t\t\tserial1 = &blsp1_uart2;\n\t\t};\n\n\t\tleds {\n\t\t\tcompatible = \"gpio-leds\";\n\t\t\tpinctrl-0 = <&led_pins>;\n\t\t\tpinctrl-names = \"default\";\n\n\t\t\tled_status: led2 {\n\t\t\t\tlabel = \"green:led2\";\n\t\t\t\tgpios = <&tlmm 68 GPIO_ACTIVE_LOW>;\n\t\t\t};\n\t\t};\n\n\t\tkeys {\n\t\t\tcompatible = \"gpio-keys\";\n\n\t\t\treset {\n\t\t\t\tlabel = \"reset\";\n\t\t\t\tgpios = <&tlmm 18 GPIO_ACTIVE_LOW>;\n\t\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&blsp_dma {\n\tstatus = \"okay\";\n};\n\n&blsp1_uart1 {\n\tpinctrl-0 = <&serial_0_pins>;\n\tpinctrl-names = \"default\";\n\tstatus = \"okay\";\n};\n\n&blsp1_uart2 {\n\tpinctrl-0 = <&serial_1_pins>;\n\tpinctrl-names = \"default\";\n\tstatus = \"okay\";\n};\n\n&qpic_bam {\n\tstatus = \"okay\";\n};\n\n&tlmm {\n\tmdio_pins: mdio_pinmux {\n\t\tmux_1 {\n\t\t\tpins = \"gpio6\";\n\t\t\tfunction = \"mdio\";\n\t\t\tbias-pull-up;\n\t\t};\n\t\tmux_2 {\n\t\t\tpins = \"gpio7\";\n\t\t\tfunction = \"mdc\";\n\t\t\tbias-pull-up;\n\t\t};\n\t};\n\n\tserial_0_pins: serial0-pinmux {\n\t\tmux {\n\t\t\tpins = \"gpio16\", \"gpio17\";\n\t\t\tfunction = \"blsp_uart0\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\tserial_1_pins: serial1_pinmux {\n\t\tmux {\n\t\t\tpins = \"gpio8\", \"gpio9\";\n\t\t\tfunction = \"blsp_uart1\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tspi_0_pins: spi_0_pinmux {\n\t\tpinmux {\n\t\t\tfunction = \"blsp_spi0\";\n\t\t\tpins = \"gpio13\", \"gpio14\", \"gpio15\";\n\t\t\tdrive-strength = <12>;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tpinmux_cs {\n\t\t\tfunction = \"gpio\";\n\t\t\tpins = \"gpio12\";\n\t\t\tdrive-strength = <2>;\n\t\t\tbias-disable;\n\t\t\toutput-high;\n\t\t};\n\t};\n\n\tled_pins: led_pinmux {\n\t\tmux {\n\t\t\tfunction = \"gpio\";\n\t\t\tpins = \"gpio68\";\n\t\t\tbias-disabled;\n\t\t\toutput-low;\n\t\t};\n\t};\n};\n\n&usb3_ss_phy {\n\tstatus = \"okay\";\n};\n\n&usb3_hs_phy {\n\tstatus = \"okay\";\n};\n\n&usb2_hs_phy {\n\tstatus = \"okay\";\n};\n\n&wifi0 {\n\tstatus = \"okay\";\n\tnvmem-cell-names = \"pre-calibration\";\n\tnvmem-cells = <&precal_art_1000>;\n};\n\n&wifi1 {\n\tstatus = \"okay\";\n\tnvmem-cell-names = \"pre-calibration\";\n\tnvmem-cells = <&precal_art_5000>;\n};\n"
  },
  {
    "path": "target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-wifi.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * Copyright (c) 2016, 2018 The Linux Foundation. All rights reserved.\n * Copyright (c) 2016 Google, Inc\n */\n\n#include \"qcom-ipq4019.dtsi\"\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/leds/common.h>\n\n/ {\n\tmodel = \"Google WiFi (Gale)\";\n\tcompatible = \"google,wifi\", \"google,gale-v2\", \"qcom,ipq4019\";\n\n\tchosen {\n\t\t/*\n\t\t * rootwait: in case we're booting from slow/async USB storage.\n\t\t */\n\t\tbootargs-append = \" rootwait\";\n\t\tstdout-path = &blsp1_uart1;\n\t};\n\n\tmemory {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x80000000 0x20000000>; /* 512MB */\n\t};\n\n\tsoc {\n\t\tess-switch@c000000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tedma@c080000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tess-psgmii@98000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\t};\n};\n\n&tlmm {\n\tfw_pinmux {\n\t\twp {\n\t\t\tpins = \"gpio53\";\n\t\t\toutput-low;\n\t\t};\n\t\trecovery {\n\t\t\tpins = \"gpio57\";\n\t\t\tbias-none;\n\t\t};\n\t\tdeveloper {\n\t\t\tpins = \"gpio41\";\n\t\t\tbias-none;\n\t\t};\n\t};\n\n\treset802_15_4 {\n\t\tpins = \"gpio60\";\n\t};\n\n\tled_reset {\n\t\tpins = \"gpio22\";\n\t\toutput-high;\n\t};\n\n\tsys_reset {\n\t\tpins = \"gpio19\";\n\t\toutput-high;\n\t};\n\n\trx_active {\n\t\tpins = \"gpio43\";\n\t\tbias-pull,down;\n\t};\n\n\tspi_0_pins: spi_0_pinmux {\n\t\tpinmux {\n\t\t\tfunction = \"blsp_spi0\";\n\t\t\tpins = \"gpio13\", \"gpio14\",\"gpio15\";\n\t\t};\n\t\tpinmux_cs {\n\t\t\tfunction = \"gpio\";\n\t\t\tpins = \"gpio12\";\n\t\t};\n\t\tpinconf {\n\t\t\tpins = \"gpio13\", \"gpio14\",\"gpio15\";\n\t\t\tdrive-strength = <12>;\n\t\t\tbias-disable;\n\t\t};\n\t\tpinconf_cs {\n\t\t\tpins = \"gpio12\";\n\t\t\tdrive-strength = <2>;\n\t\t\tbias-disable;\n\t\t\toutput-high;\n\t\t};\n\t};\n\n\tspi_1_pins: spi_1_pinmux {\n\t\tpinmux {\n\t\t\tfunction = \"blsp_spi1\";\n\t\t\tpins = \"gpio44\", \"gpio46\",\"gpio47\";\n\t\t};\n\t\tpinmux_cs {\n\t\t\tfunction = \"gpio\";\n\t\t\tpins = \"gpio45\";\n\t\t};\n\t\tpinconf {\n\t\t\tpins = \"gpio44\", \"gpio46\",\"gpio47\";\n\t\t\tdrive-strength = <12>;\n\t\t\tbias-disable;\n\t\t};\n\t\tpinconf_cs {\n\t\t\tpins = \"gpio45\";\n\t\t\tdrive-strength = <2>;\n\t\t\tbias-disable;\n\t\t\toutput-high;\n\t\t};\n\t};\n\n\tserial_0_pins: serial0_pinmux {\n\t\tmux {\n\t\t\tpins = \"gpio16\", \"gpio17\";\n\t\t\tfunction = \"blsp_uart0\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tserial_1_pins: serial1_pinmux {\n\t\tmux {\n\t\t\tpins = \"gpio8\", \"gpio9\", \"gpio10\", \"gpio11\";\n\t\t\tfunction = \"blsp_uart1\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\ti2c_0_pins: i2c_0_pinmux {\n\t\tmux {\n\t\t\tpins = \"gpio20\", \"gpio21\";\n\t\t\tfunction = \"blsp_i2c0\";\n\t\t\tdrive-open-drain;\n\t\t};\n\t};\n\n\ti2c_1_pins: i2c_1_pinmux {\n\t\tmux {\n\t\t\tpins = \"gpio34\", \"gpio35\";\n\t\t\tfunction = \"blsp_i2c1\";\n\t\t\tdrive-open-drain;\n\t\t};\n\t};\n\n\tsd_0_pins: sd_0_pinmux {\n\t\tsd0 {\n\t\t\tpins = \"gpio23\", \"gpio24\", \"gpio25\", \"gpio26\", \"gpio29\", \"gpio30\", \"gpio31\", \"gpio32\";\n\t\t\tfunction = \"sdio\";\n\t\t\tdrive-strength = <10>;\n\t\t\tbias-pull-up;\n\t\t\tpull-up-res = <0>;\n\t\t};\n\t\tsdclk {\n\t\t\tpins = \"gpio27\";\n\t\t\tfunction = \"sdio\";\n\t\t\tdrive-strength = <2>;\n\t\t\tbias-pull-up;\n\t\t\tpull-up-res = <0>;\n\t\t};\n\t\tsdcmd {\n\t\t\tpins = \"gpio28\";\n\t\t\tfunction = \"sdio\";\n\t\t\tdrive-strength = <10>;\n\t\t\tbias-pull-up;\n\t\t\tpull-up-res = <0>;\n\t\t};\n\t};\n\n\tmdio_pins: mdio_pinmux {\n\t\tmux_1 {\n\t\t\tpins = \"gpio6\";\n\t\t\tfunction = \"mdio\";\n\t\t\tbias-disable;\n\t\t};\n\t\tmux_2 {\n\t\t\tpins = \"gpio7\";\n\t\t\tfunction = \"mdc\";\n\t\t\tbias-disable;\n\t\t};\n\t\tmux_3 {\n\t\t\tpins = \"gpio40\";\n\t\t\tfunction = \"gpio\";\n\t\t\tbias-disable;\n\t\t\toutput-high;\n\t\t};\n\t};\n\n\twifi1_1_pins: wifi2_pinmux {\n\t\tmux {\n\t\t\tpins = \"gpio58\";\n\t\t\toutput-low;\n\t\t};\n\t};\n};\n\n&blsp_dma {\n\tstatus = \"okay\";\n};\n\n&blsp1_i2c3 {\n\tpinctrl-0 = <&i2c_0_pins>;\n\tpinctrl-names = \"default\";\n\tstatus = \"okay\";\n\n\ttpm@20 {\n\t\tcompatible = \"infineon,slb9645tt\";\n\t\treg = <0x20>;\n\t\tpowered-while-suspended;\n\t};\n};\n\n&blsp1_i2c4 {\n\tpinctrl-0 = <&i2c_1_pins>;\n\tpinctrl-names = \"default\";\n\tstatus = \"okay\";\n\n\tled-controller@32 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tcompatible = \"national,lp5523\";\n\t\treg = <0x32>;\n\t\tclock-mode = /bits/ 8 <1>;\n\n#if 1\n\t\tled@0 {\n\t\t\treg = <0>;\n\t\t\tchan-name = \"LED0_Red\";\n\t\t\tled-cur = /bits/ 8 <0x64>;\n\t\t\tmax-cur = /bits/ 8 <0x78>;\n\t\t\tcolor = <LED_COLOR_ID_RED>;\n\t\t};\n\n\t\tled@1 {\n\t\t\treg = <1>;\n\t\t\tchan-name = \"LED0_Green\";\n\t\t\tled-cur = /bits/ 8 <0x64>;\n\t\t\tmax-cur = /bits/ 8 <0x78>;\n\t\t\tcolor = <LED_COLOR_ID_GREEN>;\n\t\t};\n\n\t\tled@2 {\n\t\t\treg = <2>;\n\t\t\tchan-name = \"LED0_Blue\";\n\t\t\tled-cur = /bits/ 8 <0x64>;\n\t\t\tmax-cur = /bits/ 8 <0x78>;\n\t\t\tcolor = <LED_COLOR_ID_BLUE>;\n\t\t};\n#else\n\t\t/*\n\t\t * openwrt isn't ready to handle multi-intensity leds yet\n\t\t * # echo 255 255 255 > /sys/class/leds/tricolor/multi_intensity\n\t\t * # echo 255 > /sys/class/leds/tricolor/brightness\n\t\t */\n\t\tmulti-led@2 {\n\t\t\treg = <2>;\n\t\t\tcolor = <LED_COLOR_ID_RGB>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\n\t\t\tled@0 {\n\t\t\t\treg = <0>;\n\t\t\t\tchan-name = \"tricolor\";\n\t\t\t\tled-cur = /bits/ 8 <0x64>;\n\t\t\t\tmax-cur = /bits/ 8 <0x78>;\n\t\t\t\tcolor = <LED_COLOR_ID_RED>;\n\t\t\t};\n\n\t\t\tled@1 {\n\t\t\t\treg = <1>;\n\t\t\t\tchan-name = \"tricolor\";\n\t\t\t\tled-cur = /bits/ 8 <0x64>;\n\t\t\t\tmax-cur = /bits/ 8 <0x78>;\n\t\t\t\tcolor = <LED_COLOR_ID_GREEN>;\n\t\t\t};\n\n\t\t\tled@2 {\n\t\t\t\treg = <2>;\n\t\t\t\tchan-name = \"tricolor\";\n\t\t\t\tled-cur = /bits/ 8 <0x64>;\n\t\t\t\tmax-cur = /bits/ 8 <0x78>;\n\t\t\t\tcolor = <LED_COLOR_ID_BLUE>;\n\t\t\t};\n\t\t};\n#endif\n\t};\n};\n\n&blsp1_spi1 {\n\tpinctrl-0 = <&spi_0_pins>;\n\tpinctrl-names = \"default\";\n\tstatus = \"okay\";\n\tcs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <24000000>;\n\t};\n};\n\n&blsp1_spi2 {\n\tpinctrl-0 = <&spi_1_pins>;\n\tpinctrl-names = \"default\";\n\tstatus = \"okay\";\n\tcs-gpios = <&tlmm 45 GPIO_ACTIVE_HIGH>;\n\n\t/*\n\t * This \"spidev\" was included in the manufacturer device tree. I\n\t * suspect it's the (unused; and removed from later HW spins) Zigbee\n\t * radio -- SiliconLabs EM3581 Zigbee? There's no driver or binding for\n\t * this at the moment.\n\t */\n\tspidev@0 {\n\t\tcompatible = \"spidev\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <24000000>;\n\t};\n};\n\n&blsp1_uart1 {\n\tpinctrl-0 = <&serial_0_pins>;\n\tpinctrl-names = \"default\";\n\tstatus = \"okay\";\n};\n\n&blsp1_uart2 {\n\tpinctrl-0 = <&serial_1_pins>;\n\tpinctrl-names = \"default\";\n\tstatus = \"okay\";\n};\n\n&gmac0 {\n\tqcom,phy_mdio_addr = <4>;\n\tqcom,poll_required = <1>;\n\tqcom,forced_speed = <1000>;\n\tqcom,forced_duplex = <1>;\n\tvlan_tag = <2 0x20>;\n};\n\n&gmac1 {\n\tqcom,phy_mdio_addr = <3>;\n\tqcom,forced_duplex = <1>;\n\tvlan_tag = <1 0x10>;\n};\n\n&mdio {\n\tstatus = \"okay\";\n\tpinctrl-0 = <&mdio_pins>;\n\tpinctrl-names = \"default\";\n};\n\n&prng {\n\tstatus = \"okay\";\n};\n\n&sdhci {\n\tstatus = \"okay\";\n\tpinctrl-0 = <&sd_0_pins>;\n\tpinctrl-names = \"default\";\n\tclock-frequency = <192000000>;\n\tvqmmc-supply = <&vqmmc>;\n\tnon-removable;\n};\n\n&usb2 {\n\tstatus = \"okay\";\n};\n\n&usb2_hs_phy {\n\tstatus = \"okay\";\n};\n\n&usb3 {\n\tstatus = \"okay\";\n};\n\n&usb3_ss_phy {\n\tstatus = \"okay\";\n};\n\n&usb3_hs_phy {\n\tstatus = \"okay\";\n};\n\n&vqmmc {\n\tstatus = \"okay\";\n};\n\n&watchdog {\n\tstatus = \"okay\";\n};\n\n&wifi0 {\n\tstatus = \"okay\";\n\tqcom,ath10k-calibration-variant = \"GO_GALE\";\n};\n\n&wifi1 {\n\tstatus = \"okay\";\n\tpinctrl-0 = <&wifi1_1_pins>;\n\tpinctrl-names = \"default\";\n\tqcom,ath10k-calibration-variant = \"GO_GALE\";\n};\n"
  },
  {
    "path": "target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-wpj419.dts",
    "content": "/* Copyright (c) 2015, The Linux Foundation. All rights reserved.\n * Copyright (c) 2019, Nguyen Dinh Phi <phi_nguyen@compex.com.sg>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#include \"qcom-ipq4019.dtsi\"\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/soc/qcom,tcsr.h>\n\n/ {\n\tmodel = \"Compex WPJ419\";\n\tcompatible = \"compex,wpj419\", \"qcom,ipq4019\";\n\n\tmemory {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x80000000 0x10000000>;\n\t};\n\n\treserved-memory {\n\t\tranges;\n\t\trsvd1@87000000 {\n\t\t\t/* Reserved for other subsystem */\n\t\t\treg = <0x87000000 0x500000>;\n\t\t\tno-map;\n\t\t};\n\t\twifi_dump@87500000 {\n\t\t\treg = <0x87500000 0x600000>;\n\t\t\tno-map;\n\t\t};\n\n\t\trsvd2@87B00000 {\n\t\t\t/* Reserved for other subsystem */\n\t\t\treg = <0x87B00000 0x500000>;\n\t\t\tno-map;\n\t\t};\n\t};\n\n\tchosen {\n\t\tbootargs-append = \" ubi.mtd=ubi root=/dev/ubiblock0_1\";\n\t};\n\n\tsoc {\n\t\tpinctrl@1000000 {\n\t\t\tmdio_pins: mdio_pinmux {\n\t\t\t\tmux_1 {\n\t\t\t\t\tpins = \"gpio6\";\n\t\t\t\t\tfunction = \"mdio\";\n\t\t\t\t\tbias-pull-up;\n\t\t\t\t};\n\n\t\t\t\tmux_2 {\n\t\t\t\t\tpins = \"gpio7\";\n\t\t\t\t\tfunction = \"mdc\";\n\t\t\t\t\tbias-pull-up;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tserial_0_pins: serial_pinmux {\n\t\t\t\tmux {\n\t\t\t\t\tpins = \"gpio16\", \"gpio17\";\n\t\t\t\t\tfunction = \"blsp_uart0\";\n\t\t\t\t\tbias-disable;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tserial_1_pins: serial1_pinmux {\n\t\t\t\tmux {\n\t\t\t\t\tpins = \"gpio8\", \"gpio9\", \"gpio10\", \"gpio11\";\n\t\t\t\t\tfunction = \"blsp_uart1\";\n\t\t\t\t\tbias-disable;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tspi_0_pins: spi_0_pinmux {\n\t\t\t\tpinmux {\n\t\t\t\t\tfunction = \"blsp_spi0\";\n\t\t\t\t\tpins = \"gpio13\", \"gpio14\", \"gpio15\";\n\t\t\t\t\tbias-disable;\n\t\t\t\t};\n\n\t\t\t\tpinmux_cs {\n\t\t\t\t\tfunction = \"gpio\";\n\t\t\t\t\tpins = \"gpio12\";\n\t\t\t\t\tbias-disable;\n\t\t\t\t\toutput-high;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\ti2c_0_pins: i2c_0_pinmux {\n\t\t\t\tmux {\n\t\t\t\t\tpins = \"gpio20\", \"gpio21\";\n\t\t\t\t\tfunction = \"blsp_i2c0\";\n\t\t\t\t\tbias-disable;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tnand_pins: nand_pins {\n\t\t\t\tpullups {\n\t\t\t\t\tpins = \"gpio52\", \"gpio53\", \"gpio58\", \"gpio59\";\n\t\t\t\t\tfunction = \"qpic\";\n\t\t\t\t\tbias-pull-up;\n\t\t\t\t};\n\n\t\t\t\tpulldowns {\n\t\t\t\t\tpins = \"gpio54\", \"gpio55\", \"gpio56\",\n\t\t\t\t\t\"gpio57\", \"gpio60\", \"gpio61\",\n\t\t\t\t\t\"gpio62\", \"gpio63\", \"gpio64\",\n\t\t\t\t\t\"gpio65\", \"gpio66\", \"gpio67\",\n\t\t\t\t\t\"gpio68\", \"gpio69\";\n\t\t\t\t\tfunction = \"qpic\";\n\t\t\t\t\tbias-pull-down;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tled_0_pins: led0_pinmux {\n\t\t\t\tmux_1 {\n\t\t\t\t\tpins = \"gpio36\";\n\t\t\t\t\tfunction = \"led0\";\n\t\t\t\t\tbias-pull-down;\n\t\t\t\t};\n\t\t\t\tmux_2 {\n\t\t\t\t\tpins = \"gpio40\";\n\t\t\t\t\tfunction = \"led4\";\n\t\t\t\t\tbias-pull-down;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tblsp_dma: dma@7884000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tspi_0: spi@78b5000 {\n\t\t\tpinctrl-0 = <&spi_0_pins>;\n\t\t\tpinctrl-names = \"default\";\n\t\t\tstatus = \"okay\";\n\t\t\tcs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>, <&tlmm 41 GPIO_ACTIVE_HIGH>;\n\t\t\tnum-cs = <2>;\n\n\t\t\tflash0@0 {\n\t\t\t\treg = <0>;\n\t\t\t\tcompatible = \"jedec,spi-nor\";\n\t\t\t\tspi-max-frequency = <24000000>;\n\t\t\t\tbroken-flash-reset;\n\n\t\t\t\tpartitions {\n\t\t\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t\t\t#address-cells = <1>;\n\t\t\t\t\t#size-cells = <1>;\n\n\t\t\t\t\tpartition@0 {\n\t\t\t\t\t\tlabel = \"0:SBL1\";\n\t\t\t\t\t\treg = <0x000000 0x040000>;\n\t\t\t\t\t\tread-only;\n\t\t\t\t\t};\n\n\t\t\t\t\tpartition@40000 {\n\t\t\t\t\t\tlabel = \"0:MIBIB\";\n\t\t\t\t\t\treg = <0x040000 0x020000>;\n\t\t\t\t\t\tread-only;\n\t\t\t\t\t};\n\n\t\t\t\t\tpartition@60000 {\n\t\t\t\t\t\tlabel = \"0:QSEE\";\n\t\t\t\t\t\treg = <0x060000 0x060000>;\n\t\t\t\t\t\tread-only;\n\t\t\t\t\t};\n\n\t\t\t\t\tpartition@c0000 {\n\t\t\t\t\t\tlabel = \"0:CDT\";\n\t\t\t\t\t\treg = <0x0c0000 0x010000>;\n\t\t\t\t\t\tread-only;\n\t\t\t\t\t};\n\n\t\t\t\t\tpartition@d0000 {\n\t\t\t\t\t\tlabel = \"0:DDRPARAMS\";\n\t\t\t\t\t\treg = <0x0d0000 0x010000>;\n\t\t\t\t\t\tread-only;\n\t\t\t\t\t};\n\n\t\t\t\t\tpartition@e0000 {\n\t\t\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\t\t\treg = <0x0e0000 0x010000>;\n\t\t\t\t\t};\n\n\t\t\t\t\tpartition@f0000 {\n\t\t\t\t\t\tlabel = \"u-boot\";\n\t\t\t\t\t\treg = <0x0f0000 0x080000>;\n\t\t\t\t\t\tread-only;\n\t\t\t\t\t};\n\n\t\t\t\t\tpartition@170000 {\n\t\t\t\t\t\tlabel = \"0:ART\";\n\t\t\t\t\t\treg = <0x170000 0x010000>;\n\t\t\t\t\t\tread-only;\n\t\t\t\t\t\tcompatible = \"nvmem-cells\";\n\t\t\t\t\t\t#address-cells = <1>;\n\t\t\t\t\t\t#size-cells = <1>;\n\n\t\t\t\t\t\tprecal_art_1000: precal@1000 {\n\t\t\t\t\t\t\treg = <0x1000 0x2f20>;\n\t\t\t\t\t\t};\n\n\t\t\t\t\t\tprecal_art_5000: precal@5000 {\n\t\t\t\t\t\t\treg = <0x5000 0x2f20>;\n\t\t\t\t\t\t};\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tnand@1 {\n\t\t\t\treg = <1>;\n\t\t\t\tstatus = \"okay\";\n\t\t\t\tcompatible = \"spi-nand\";\n\t\t\t\tspi-max-frequency = <24000000>;\n\n\t\t\t\tpartitions {\n\t\t\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t\t\t#address-cells = <1>;\n\t\t\t\t\t#size-cells = <1>;\n\n\t\t\t\t\t/* The device has 128MB, but we can only address\n\t\t\t\t\t * 64MB because of the bootloader's default settings.\n\t\t\t\t\t * This is due to the old mt29f driver,\n\t\t\t\t\t * which detected the deivce with only 64MB\n\t\t\t\t\t */\n\t\t\t\t\tpartition@0 {\n\t\t\t\t\t\tlabel = \"ubi\";\n\t\t\t\t\t\treg = <0x0000000 0x4000000>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tmdio@90000 {\n\t\t\tstatus = \"okay\";\n\t\t\tpinctrl-0 = <&mdio_pins>;\n\t\t\tpinctrl-names = \"default\";\n\t\t\treset-gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;\n\t\t\treset-delay-us = <5000>;\n\t\t};\n\n\t\tess-psgmii@98000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\ttcsr@194b000 {\n\t\t\t/* select hostmode */\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x194b000 0x100>;\n\t\t\tqcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\ttcsr@1949000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1949000 0x100>;\n\t\t\tqcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;\n\t\t};\n\n\t\tess_tcsr@1953000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1953000 0x1000>;\n\t\t\tqcom,ess-interface-select = <TCSR_ESS_PSGMII>;\n\t\t};\n\n\t\ttcsr@1957000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1957000 0x100>;\n\t\t\tqcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;\n\t\t};\n\n\t\ti2c_0: i2c@78b7000 {\n\t\t\tpinctrl-0 = <&i2c_0_pins>;\n\t\t\tpinctrl-names = \"default\";\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tserial@78af000 {\n\t\t\tpinctrl-0 = <&serial_0_pins>;\n\t\t\tpinctrl-names = \"default\";\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tserial@78b0000 {\n\t\t\tpinctrl-0 = <&serial_1_pins>;\n\t\t\tpinctrl-names = \"default\";\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tusb3_ss_phy: ssphy@9a000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tusb3_hs_phy: hsphy@a6000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tusb3: usb3@8af8800 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tusb2_hs_phy: hsphy@a8000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tusb2: usb2@60f8800 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tcryptobam: dma@8e04000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tcrypto@8e3a000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\twatchdog@b017000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tess-switch@c000000 {\n\t\t\tswitch_lan_bmp = <0x1e>;\n\t\t\tswitch_wan_bmp = <0x20>;\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tedma@c080000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tqpic_bam: dma@7984000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tpcie0: pci@40000000 {\n\t\t\tstatus = \"okay\";\n\t\t\tperst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;\n\t\t\twake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&tlmm 18 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n};\n\n&nand {\n\tpinctrl-0 = <&nand_pins>;\n\tpinctrl-names = \"default\";\n\tstatus = \"okay\";\n};\n\n&gmac0 {\n\tqcom,phy_mdio_addr = <4>;\n\tqcom,poll_required = <1>;\n\tqcom,forced_speed = <1000>;\n\tqcom,forced_duplex = <1>;\n\tvlan_tag = <2 0x20>;\n};\n\n&gmac1 {\n\tqcom,phy_mdio_addr = <3>;\n\tqcom,poll_required = <1>;\n\tqcom,forced_speed = <1000>;\n\tqcom,forced_duplex = <1>;\n\tvlan_tag = <1 0x10>;\n};\n\n&wifi0 {\n\tstatus = \"okay\";\n\tnvmem-cell-names = \"pre-calibration\";\n\tnvmem-cells = <&precal_art_1000>;\n};\n\n&wifi1 {\n\tstatus = \"okay\";\n\tnvmem-cell-names = \"pre-calibration\";\n\tnvmem-cells = <&precal_art_5000>;\n};\n"
  },
  {
    "path": "target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-wtr-m2133hp.dts",
    "content": "// SPDX-License-Identifier: ISC\n/*\n * Copyright (c) 2015 - 2016, The Linux Foundation. All rights reserved.\n * Copyright (c) 2020 Yanase Yuki <dev@zpc.sakura.ne.jp>\n */\n\n#include \"qcom-ipq4019.dtsi\"\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/soc/qcom,tcsr.h>\n\n/ {\n\tmodel = \"Buffalo WTR-M2133HP\";\n\tcompatible = \"buffalo,wtr-m2133hp\", \"qcom,ipq4019\";\n\n\tmemory {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x80000000 0x20000000>;\n\t};\n\n\tchosen {\n\t\t/*\n\t\t * U-Boot adds \"ubi.mtd=rootfs root=mtd:ubi_rootfs\" to\n\t\t * kernel command line. But we use different partition names,\n\t\t * so we have to set correct parameters.\n\t\t */\n\t\tbootargs-append = \" ubi.mtd=ubi root=/dev/ubiblock0_1\";\n\t};\n\n\taliases {\n\t\tled-boot = &led_power_blue;\n\t\tled-failsafe = &led_power_orange;\n\t\tled-running = &led_power_white;\n\t\tled-upgrade = &led_power_blue;\n\t\tlabel-mac-device = &gmac0;\n\t};\n\n\tsoc {\n\t\trng@22000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\ttcsr@1949000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1949000 0x100>;\n\t\t\tqcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;\n\t\t};\n\n\t\ttcsr@194b000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x194b000 0x100>;\n\t\t\tqcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tess_tcsr@1953000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1953000 0x1000>;\n\t\t\tqcom,ess-interface-select = <TCSR_ESS_PSGMII>;\n\t\t};\n\n\t\ttcsr@1957000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1957000 0x100>;\n\t\t\tqcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;\n\t\t};\n\n\t\tcrypto@8e3a000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\twatchdog@b017000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tess-switch@c000000 {\n\t\t\tstatus = \"okay\";\n\t\t\tswitch_lan_bmp = <0x1c>;\n\t\t};\n\n\t\tess-psgmii@98000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tedma@c080000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tusb3@8af8800 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power_white: power_white {\n\t\t\tlabel = \"white:power\";\n\t\t\tgpios = <&tlmm 40 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tled_power_orange: power_orange {\n\t\t\tlabel = \"orange:power\";\n\t\t\tgpios = <&tlmm 25 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tled_power_blue: power_blue {\n\t\t\tlabel = \"blue:power\";\n\t\t\tgpios = <&tlmm 43 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\trouter_white {\n\t\t\tlabel = \"white:router\";\n\t\t\tgpios = <&tlmm 28 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\trouter_orange {\n\t\t\tlabel = \"orange:router\";\n\t\t\tgpios = <&tlmm 46 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tinternet_white {\n\t\t\tlabel = \"white:internet\";\n\t\t\tgpios = <&tlmm 27 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tinternet_orange {\n\t\t\tlabel = \"orange:internet\";\n\t\t\tgpios = <&tlmm 45 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\twireless_white {\n\t\t\tlabel = \"white:wireless\";\n\t\t\tgpios = <&tlmm 24 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\twireless_orange {\n\t\t\tlabel = \"orange:wireless\";\n\t\t\tgpios = <&tlmm 44 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\tauto_mode {\n\t\t\tlabel = \"auto_mode\";\n\t\t\tgpios = <&tlmm 9 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_0>;\n\t\t\tlinux,input-type = <EV_SW>;\n\t\t};\n\n\t\trouter_mode {\n\t\t\tlabel = \"router_mode\";\n\t\t\tgpios = <&tlmm 10 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_1>;\n\t\t\tlinux,input-type = <EV_SW>;\n\t\t};\n\n\t\tap_mode {\n\t\t\tlabel = \"ap_mode\";\n\t\t\tgpios = <&tlmm 11 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_2>;\n\t\t\tlinux,input-type = <EV_SW>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&tlmm 18 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"AOSS Button\";\n\t\t\tgpios = <&tlmm 32 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n};\n\n&tlmm {\n\tserial_0_pins: serial0_pinmux {\n\t\tmux {\n\t\t\tpins = \"gpio16\", \"gpio17\";\n\t\t\tfunction = \"blsp_uart0\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tmdio_pins: mdio_pinmux {\n\t\tmux_1 {\n\t\t\tpins = \"gpio6\";\n\t\t\tfunction = \"mdio\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tmux_2 {\n\t\t\tpins = \"gpio7\";\n\t\t\tfunction = \"mdc\";\n\t\t\tbias-pull-up;\n\t\t};\n\t};\n\n\tnand_pins: nand_pins {\n\t\tpullups {\n\t\t\tpins = \"gpio52\", \"gpio53\", \"gpio58\",\n\t\t\t\t\"gpio59\";\n\t\t\tfunction = \"qpic\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tpulldowns {\n\t\t\tpins = \"gpio54\", \"gpio55\", \"gpio56\",\n\t\t\t\t\"gpio57\", \"gpio60\", \"gpio61\",\n\t\t\t\t\"gpio62\", \"gpio63\", \"gpio64\",\n\t\t\t\t\"gpio65\", \"gpio66\", \"gpio67\",\n\t\t\t\t\"gpio68\", \"gpio69\";\n\t\t\tfunction = \"qpic\";\n\t\t\tbias-pull-down;\n\t\t};\n\t};\n\n\tusb_power {\n\t\tline-name = \"USB power\";\n\t\tgpios = <34 GPIO_ACTIVE_HIGH>;\n\t\tgpio-hog;\n\t\toutput-high;\n\t};\n};\n\n&blsp_dma {\n\tstatus = \"okay\";\n};\n\n&blsp1_uart1 {\n\tpinctrl-0 = <&serial_0_pins>;\n\tpinctrl-names = \"default\";\n\tstatus = \"okay\";\n};\n\n&cryptobam {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\tstatus = \"okay\";\n\n\tbridge@0,0 {\n\t\treg = <0x00000000 0 0 0 0>;\n\t\t#address-cells = <3>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\twifi@0,0 {\n\t\t\tcompatible = \"qcom,ath10k\";\n\t\t\treg = <0 0 0 0 0>;\n\t\t\tnvmem-cell-names = \"pre-calibration\", \"mac-address\";\n\t\t\tnvmem-cells = <&precal_art_9000>, <&macaddr_orgdata_32>;\n\t\t\tqcom,ath10k-calibration-variant = \"Buffalo-WTR-M2133HP\";\n\t\t};\n\t};\n};\n\n&qpic_bam {\n\tstatus = \"okay\";\n};\n\n&nand {\n\tpinctrl-0 = <&nand_pins>;\n\tpinctrl-names = \"default\";\n\tstatus = \"okay\";\n\n\tnand@0 {\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"SBL1\";\n\t\t\t\treg = <0x0000000 0x0100000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@100000 {\n\t\t\t\tlabel = \"MIBIB\";\n\t\t\t\treg = <0x0100000 0x0100000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@200000 {\n\t\t\t\tlabel = \"BOOTCONFIG\";\n\t\t\t\treg = <0x0200000 0x0100000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@300000 {\n\t\t\t\tlabel = \"QSEE\";\n\t\t\t\treg = <0x0300000 0x0100000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@400000 {\n\t\t\t\tlabel = \"QSEE_1\";\n\t\t\t\treg = <0x0400000 0x0100000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@500000 {\n\t\t\t\tlabel = \"CDT\";\n\t\t\t\treg = <0x0500000 0x0080000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@580000 {\n\t\t\t\tlabel = \"CDT_1\";\n\t\t\t\treg = <0x0580000 0x0080000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@600000 {\n\t\t\t\tlabel = \"BOOTCONFIG1\";\n\t\t\t\treg = <0x0600000 0x0080000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@680000 {\n\t\t\t\tlabel = \"APPSBLENV\";\n\t\t\t\treg = <0x0680000 0x0080000>;\n\t\t\t};\n\n\t\t\tpartition@700000 {\n\t\t\t\tlabel = \"APPSBL\";\n\t\t\t\treg = <0x0700000 0x0200000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@900000 {\n\t\t\t\tlabel = \"APPSBL_1\";\n\t\t\t\treg = <0x0900000 0x0200000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@b00000 {\n\t\t\t\tlabel = \"ART\";\n\t\t\t\treg = <0x0b00000 0x0080000>;\n\t\t\t\tread-only;\n\t\t\t\tcompatible = \"nvmem-cells\";\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\n\t\t\t\tprecal_art_1000: precal@1000 {\n\t\t\t\t\treg = <0x1000 0x2f20>;\n\t\t\t\t};\n\n\t\t\t\tprecal_art_5000: precal@5000 {\n\t\t\t\t\treg = <0x5000 0x2f20>;\n\t\t\t\t};\n\n\t\t\t\tprecal_art_9000: precal@9000 {\n\t\t\t\t\treg = <0x5000 0x2f20>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tpartition@b80000 {\n\t\t\t\tlabel = \"ART_1\";\n\t\t\t\treg = <0x0b80000 0x0080000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\torgdata: partition@c00000 {\n\t\t\t\tlabel = \"ORGDATA\";\n\t\t\t\treg = <0x0c00000 0x0080000>;\n\t\t\t\tread-only;\n\t\t\t\tcompatible = \"nvmem-cells\";\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\n\t\t\t\tmacaddr_orgdata_20: macaddr@20 {\n\t\t\t\t\treg = <0x20 0x6>;\n\t\t\t\t};\n\t\t\t\tmacaddr_orgdata_26: macaddr@26 {\n\t\t\t\t\treg = <0x26 0x6>;\n\t\t\t\t};\n\t\t\t\tmacaddr_orgdata_2c: macaddr@2c {\n\t\t\t\t\treg = <0x2c 0x6>;\n\t\t\t\t};\n\t\t\t\tmacaddr_orgdata_32: macaddr@32 {\n\t\t\t\t\treg = <0x32 0x6>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tpartition@c80000 {\n\t\t\t\tlabel = \"ORGDATA_1\";\n\t\t\t\treg = <0x0c80000 0x0080000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@d00000 {\n\t\t\t\tlabel = \"ubi\";\n\t\t\t\treg = <0x0d00000 0x2900000>;\n\t\t\t};\n\n\t\t\tpartition@3600000 {\n\t\t\t\tlabel = \"rootfs_recover\";\n\t\t\t\treg = <0x3600000 0x2900000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@5f00000 {\n\t\t\t\tlabel = \"user_property\";\n\t\t\t\treg = <0x5f00000 0x1a20000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&wifi0 {\n\tstatus = \"okay\";\n\tnvmem-cell-names = \"pre-calibration\", \"mac-address\";\n\tnvmem-cells = <&precal_art_1000>, <&macaddr_orgdata_26>;\n\tqcom,ath10k-calibration-variant = \"Buffalo-WTR-M2133HP\";\n\tieee80211-freq-limit = <2400000 2483000>;\n};\n\n&wifi1 {\n\tstatus = \"okay\";\n\tnvmem-cell-names = \"pre-calibration\", \"mac-address\";\n\tnvmem-cells = <&precal_art_5000>, <&macaddr_orgdata_2c>;\n\tqcom,ath10k-calibration-variant = \"Buffalo-WTR-M2133HP\";\n};\n\n&mdio {\n\tstatus = \"okay\";\n\tpinctrl-0 = <&mdio_pins>;\n\tpinctrl-names = \"default\";\n\treset-gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_orgdata_20>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&gmac1 {\n\tnvmem-cells = <&macaddr_orgdata_20>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&usb3_ss_phy {\n\tstatus = \"okay\";\n};\n\n&usb3_hs_phy {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-x1pro.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n/dts-v1/;\n\n#include \"qcom-ipq4019-x1pro.dtsi\"\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"Telco X1 Pro\";\n\tcompatible = \"tel,x1pro\",\"qcom,ipq4019\";\n};\n\n&blsp1_spi1 {\n\tpinctrl-0 = <&spi_0_pins>;\n\tpinctrl-names = \"default\";\n\tstatus = \"okay\";\n\tcs-gpios = <&tlmm 12 GPIO_ACTIVE_LOW>;\n\n\tflash@0 {\n\t\treg = <0>;\n\t\tcompatible = \"jedec,spi-nor\";\n\t\tspi-max-frequency = <24000000>;\n\t\tbroken-flash-reset;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"0:SBL1\";\n\t\t\t\treg = <0x0 0x40000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"0:MIBIB\";\n\t\t\t\treg = <0x40000 0x20000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@60000 {\n\t\t\t\tlabel = \"0:QSEE\";\n\t\t\t\treg = <0x60000 0x60000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@c0000 {\n\t\t\t\tlabel = \"0:CDT\";\n\t\t\t\treg = <0xc0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@d0000 {\n\t\t\t\tlabel = \"0:DDRPARAMS\";\n\t\t\t\treg = <0xd0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@e0000 {\n\t\t\t\tlabel = \"0:APPSBLENV\";\n\t\t\t\treg = <0xe0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@f0000 {\n\t\t\t\tlabel = \"0:APPSBL\";\n\t\t\t\treg = <0xf0000 0x80000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tart: partition@170000 {\n\t\t\t\tlabel = \"0:ART\";\n\t\t\t\treg = <0x170000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t\tcompatible = \"nvmem-cells\";\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\n\t\t\t\tprecal_art_1000: precal@1000 {\n\t\t\t\t\treg = <0x1000 0x2f20>;\n\t\t\t\t};\n\n\t\t\t\tprecal_art_5000: precal@5000 {\n\t\t\t\t\treg = <0x5000 0x2f20>;\n\t\t\t\t};\n\t\t\t};\n\t\t\tpartition@180000 {\n\t\t\t\tcompatible = \"denx,fit\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x180000 0x1e80000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&gmac0 {\n\tstatus = \"okay\";\n\n\tmtd-mac-address = <&art 0x5006>;\n\tmtd-mac-address-increment = <2>;\n};\n\n&gmac1 {\n\tstatus = \"okay\";\n\n\tmtd-mac-address = <&art 0x5006>;\n\tmtd-mac-address-increment = <3>;\n};\n"
  },
  {
    "path": "target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-x1pro.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qcom-ipq4019.dtsi\"\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/soc/qcom,tcsr.h>\n\n/ {\n\tcompatible = \"tel,x1pro\",\"qcom,ipq4019\";\n\taliases {\n\t\tled-boot = &led_status;\n\t\tled-failsafe = &led_status;\n\t\tled-running = &led_status;\n\t\tled-upgrade = &led_status;\n\t\tserial0 = &blsp1_uart1;\n\t\tserial1 = &blsp1_uart2;\n\t};\n\t\n\tsoc {\n\n\t\trng@22000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tmdio@90000 {\n\t\t\tstatus = \"okay\";\n\t\t\tpinctrl-0 = <&mdio_pins>;\n\t\t\tpinctrl-names = \"default\";\n\t\t\treset-gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;\n\t\t\treset-delay-us = <2000>;\n\t\t};\n\n\t\tess-psgmii@98000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\ttcsr@1949000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1949000 0x100>;\n\t\t\tqcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;\n\t\t};\n\n\t\ttcsr@194b000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x194b000 0x100>;\n\t\t\tqcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tess_tcsr@1953000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1953000 0x1000>;\n\t\t\tqcom,ess-interface-select = <TCSR_ESS_PSGMII>;\n\t\t};\n\n\t\ttcsr@1957000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1957000 0x100>;\n\t\t\tqcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;\n\t\t};\n\n\t\tusb2@60f8800 {\n\t\t\tstatus = \"okay\";\n\n\t\t\tdwc3@6000000 {\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\n\t\t\t\tport@1 {\n\t\t\t\t\treg = <1>;\n\t\t\t\t\t#trigger-source-cells = <0>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tusb3@8af8800 {\n\t\t\tstatus = \"okay\";\n\n\t\t\tdwc3@8a00000 {\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\n\t\t\t\tport@1 {\n\t\t\t\t\treg = <1>;\n\t\t\t\t\t#trigger-source-cells = <0>;\n\t\t\t\t};\n\n\t\t\t\tport@2 {\n\t\t\t\t\treg = <2>;\n\t\t\t\t\t#trigger-source-cells = <0>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\twatchdog@b017000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tess-switch@c000000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tedma@c080000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tleds {\n\t\t\tcompatible = \"gpio-leds\";\n\t\t\tpinctrl-0 = <&led_pins>;\n\t\t\tpinctrl-names = \"default\";\n\n\t\t\tled_status: status {\n\t\t\t\tlabel = \"green:status\";\n\t\t\t\tgpios = <&tlmm 68 GPIO_ACTIVE_LOW>;\n\t\t\t};\n\t\t};\n\n\t\tkeys {\n\t\t\tcompatible = \"gpio-keys\";\n\n\t\t\treset {\n\t\t\t\tlabel = \"reset\";\n\t\t\t\tgpios = <&tlmm 18 GPIO_ACTIVE_LOW>;\n\t\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&blsp_dma {\n\tstatus = \"okay\";\n};\n\n&blsp1_uart1 {\n\tpinctrl-0 = <&serial_0_pins>;\n\tpinctrl-names = \"default\";\n\tstatus = \"okay\";\n};\n\n&blsp1_uart2 {\n\tpinctrl-0 = <&serial_1_pins>;\n\tpinctrl-names = \"default\";\n\tstatus = \"okay\";\n};\n\n&qpic_bam {\n\tstatus = \"okay\";\n};\n\n&tlmm {\n\tmdio_pins: mdio_pinmux {\n\t\tmux_1 {\n\t\t\tpins = \"gpio6\";\n\t\t\tfunction = \"mdio\";\n\t\t\tbias-pull-up;\n\t\t};\n\t\tmux_2 {\n\t\t\tpins = \"gpio7\";\n\t\t\tfunction = \"mdc\";\n\t\t\tbias-pull-up;\n\t\t};\n\t};\n\n\tserial_0_pins: serial0-pinmux {\n\t\tmux {\n\t\t\tpins = \"gpio16\", \"gpio17\";\n\t\t\tfunction = \"blsp_uart0\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\tserial_1_pins: serial1_pinmux {\n\t\tmux {\n\t\t\tpins = \"gpio8\", \"gpio9\";\n\t\t\tfunction = \"blsp_uart1\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tspi_0_pins: spi_0_pinmux {\n\t\tpinmux {\n\t\t\tfunction = \"blsp_spi0\";\n\t\t\tpins = \"gpio13\", \"gpio14\", \"gpio15\";\n\t\t\tdrive-strength = <12>;\n\t\t\tbias-disable;\n\t\t};\n\n\t\tpinmux_cs {\n\t\t\tfunction = \"gpio\";\n\t\t\tpins = \"gpio12\";\n\t\t\tdrive-strength = <2>;\n\t\t\tbias-disable;\n\t\t\toutput-high;\n\t\t};\n\t};\n\n\tled_pins: led_pinmux {\n\t\tmux {\n\t\t\tfunction = \"gpio\";\n\t\t\tpins = \"gpio68\";\n\t\t\tbias-disabled;\n\t\t\toutput-low;\n\t\t};\n\t};\n};\n\n&usb3_ss_phy {\n\tstatus = \"okay\";\n};\n\n&usb3_hs_phy {\n\tstatus = \"okay\";\n};\n\n&usb2_hs_phy {\n\tstatus = \"okay\";\n};\n\n&wifi0 {\n\tstatus = \"okay\";\n\tnvmem-cell-names = \"pre-calibration\";\n\tnvmem-cells = <&precal_art_1000>;\n};\n\n&wifi1 {\n\tstatus = \"okay\";\n\tnvmem-cell-names = \"pre-calibration\";\n\tnvmem-cells = <&precal_art_5000>;\n};\n"
  },
  {
    "path": "target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-xx8300.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n/*\n * Device Tree Source for Linksys xx8300 (Dallas)\n *\n * Copyright (C) 2019 Jeff Kletsky\n * Updated 2020 Hans Geiblinger\n *\n */\n\n#include \"qcom-ipq4019.dtsi\"\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/soc/qcom,tcsr.h>\n\n\t//\n\t// OEM U-Boot provides either\n\t// init=/sbin/init rootfstype=ubifs ubi.mtd=11,2048 \\\n\t//                 root=ubi0:ubifs rootwait rw\n\t// or the same with ubi.mtd=13,2048\n\t//\n\n/ {\n\tchosen {\n\t\tbootargs-append = \" root=/dev/ubiblock0_0 rootfstype=squashfs ro\";\n\t};\n\n\n\tsoc {\n\t\trng@22000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tmdio@90000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tess-psgmii@98000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\ttcsr@1949000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1949000 0x100>;\n\t\t\tqcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;\n\t\t};\n\n\t\ttcsr@194b000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x194b000 0x100>;\n\t\t\tqcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;\n\t\t};\n\n\t\tess_tcsr@1953000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1953000 0x1000>;\n\t\t\tqcom,ess-interface-select = <TCSR_ESS_PSGMII>;\n\t\t};\n\n\t\ttcsr@1957000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1957000 0x100>;\n\t\t\tqcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;\n\t\t};\n\n\t\tusb2@60f8800 {\n\t\t\tstatus = \"okay\";\n\n\t\t\tdwc3@6000000 {\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\n\t\t\t\tusb2_port1: port@1 {\n\t\t\t\t\treg = <1>;\n\t\t\t\t\t#trigger-source-cells = <0>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tusb3@8af8800 {\n\t\t\tstatus = \"okay\";\n\n\t\t\tdwc3@8a00000 {\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\n\t\t\t\tusb3_port1: port@1 {\n\t\t\t\t\treg = <1>;\n\t\t\t\t\t#trigger-source-cells = <0>;\n\t\t\t\t};\n\n\t\t\t\tusb3_port2: port@2 {\n\t\t\t\t\treg = <2>;\n\t\t\t\t\t#trigger-source-cells = <0>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tcrypto@8e3a000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\twatchdog@b017000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tess-switch@c000000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tedma@c080000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\t};\n};\n\n\n&blsp_dma {\n\tstatus = \"okay\";\n};\n\n&blsp1_uart1 {\n\tstatus = \"okay\";\n\tpinctrl-0 = <&serial_0_pins>;\n\tpinctrl-names = \"default\";\n\n};\n\n&cryptobam {\n\tstatus = \"okay\";\n};\n\n&nand {\n\tstatus = \"okay\";\n\n\tpinctrl-0 = <&nand_pins>;\n\tpinctrl-names = \"default\";\n\n\tnand@0 {\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"sbl1\";\n\t\t\t\treg = <0x0 0x100000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@100000 {\n\t\t\t\tlabel = \"mibib\";\n\t\t\t\treg = <0x100000 0x100000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@200000 {\n\t\t\t\tlabel = \"qsee\";\n\t\t\t\treg = <0x200000 0x100000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@300000 {\n\t\t\t\tlabel = \"cdt\";\n\t\t\t\treg = <0x300000 0x80000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@380000 {\n\t\t\t\tlabel = \"appsblenv\";\n\t\t\t\treg = <0x380000 0x80000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@400000 {\n\t\t\t\tlabel = \"ART\";\n\t\t\t\treg = <0x400000 0x80000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@480000 {\n\t\t\t\tlabel = \"appsbl\";\n\t\t\t\treg = <0x480000 0x200000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@680000 {\n\t\t\t\tlabel = \"u_env\";\n\t\t\t\treg = <0x680000 0x80000>;\n\t\t\t\t// writable -- U-Boot environment\n\t\t\t};\n\n\t\t\tpartition@700000 {\n\t\t\t\tlabel = \"s_env\";\n\t\t\t\treg = <0x700000 0x40000>;\n\t\t\t\t// writable -- Boot counter records\n\t\t\t};\n\n\t\t\tpartition@740000 {\n\t\t\t\tlabel = \"devinfo\";\n\t\t\t\treg = <0x740000 0x40000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@780000 {\n\t\t\t\tlabel = \"kernel\";\n\t\t\t\treg = <0x780000 0x5800000>;\n\t\t\t};\n\n\t\t\tpartition@a80000 {\n\t\t\t\tlabel = \"rootfs\";\n\t\t\t\treg = <0xa80000 0x5500000>;\n\t\t\t};\n\n\t\t\tpartition@5f80000 {\n\t\t\t\tlabel = \"alt_kernel\";\n\t\t\t\treg = <0x5f80000 0x5800000>;\n\t\t\t};\n\n\t\t\tpartition@6280000 {\n\t\t\t\tlabel = \"alt_rootfs\";\n\t\t\t\treg = <0x6280000 0x5500000>;\n\t\t\t};\n\n\t\t\tpartition@b780000 {\n\t\t\t\tlabel = \"sysdiag\";\n\t\t\t\treg = <0xb780000 0x100000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@b880000 {\n\t\t\t\tlabel = \"syscfg\";\n\t\t\t\treg = <0xb880000 0x4680000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pcie0 {\n\tstatus = \"okay\";\n\n\tperst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;\n\twake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>;\n\n\tbridge@0,0 {\n\t\treg = <0x00000000 0 0 0 0>;\n\t\t#address-cells = <3>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\twifi2: wifi@1,0 {\n\t\t\tcompatible = \"qcom,ath10k\";\n\t\t\treg = <0x00010000 0 0 0 0>;\n\t\t};\n\t};\n};\n\n&qpic_bam {\n\tstatus = \"okay\";\n};\n\n&tlmm {\n\tserial_0_pins: serial0-pinmux {\n\t\tpins = \"gpio16\", \"gpio17\";\n\t\tfunction = \"blsp_uart0\";\n\t\tbias-disable;\n\t};\n\n\tnand_pins: nand_pins {\n\t\tpullups {\n\t\t\tpins = \"gpio53\", \"gpio58\", \"gpio59\";\n\t\t\tfunction = \"qpic\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\t// gpio61 controls led_usb\n\n\t\tpulldowns {\n\t\t\tpins =  \"gpio55\", \"gpio56\", \"gpio57\",\n\t\t\t\t\"gpio60\", \"gpio62\", \"gpio63\",\n\t\t\t\t\"gpio64\", \"gpio65\", \"gpio66\",\n\t\t\t\t\"gpio67\", \"gpio68\", \"gpio69\";\n\t\t\tfunction = \"qpic\";\n\t\t\tbias-pull-down;\n\t\t};\n\t};\n};\n\n&usb2_hs_phy {\n\tstatus = \"okay\";\n};\n\n&usb3_hs_phy {\n\tstatus = \"okay\";\n};\n\n&usb3_ss_phy {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4028-wpj428.dts",
    "content": "/* Copyright (c) 2015, The Linux Foundation. All rights reserved.\n * Copyright (c) 2017, Christian Mehlis <christian@m3hlis.de>\n * Copyright (c) 2017-2018, Sven Eckelmann <sven.eckelmann@openmesh.com>\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#include \"qcom-ipq4019.dtsi\"\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/soc/qcom,tcsr.h>\n\n/ {\n\tmodel = \"Compex WPJ428\";\n\tcompatible = \"compex,wpj428\";\n\n\tsoc {\n\t\trng@22000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tmdio@90000 {\n\t\t\tstatus = \"okay\";\n\t\t\tpinctrl-0 = <&mdio_pins>;\n\t\t\tpinctrl-names = \"default\";\n\t\t\treset-gpios = <&tlmm 59 GPIO_ACTIVE_LOW>;\n\t\t\treset-delay-us = <2000>;\n\t\t};\n\n\t\tess-psgmii@98000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\ttcsr@194b000 {\n\t\t\t/* select hostmode */\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x194b000 0x100>;\n\t\t\tqcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\ttcsr@1949000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1949000 0x100>;\n\t\t\tqcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;\n\t\t};\n\n\t\tess_tcsr@1953000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1953000 0x1000>;\n\t\t\tqcom,ess-interface-select = <TCSR_ESS_PSGMII>;\n\t\t};\n\n\t\ttcsr@1957000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1957000 0x100>;\n\t\t\tqcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;\n\t\t};\n\n\t\tusb2: usb2@60f8800 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tusb3: usb3@8af8800 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tcrypto@8e3a000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\twatchdog@b017000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tess-switch@c000000 {\n\t\t\tswitch_lan_bmp = <0x10>;\n\t\t\tswitch_wan_bmp = <0x20>;\n\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tedma@c080000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&tlmm 63 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\taliases {\n\t\tled-boot = &status;\n\t\tled-failsafe = &status;\n\t\tled-upgrade = &status;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tstatus: rss4 {\n\t\t\tlabel = \"green:rss4\";\n\t\t\tgpios = <&tlmm 5 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\trss3 {\n\t\t\tlabel = \"green:rss3\";\n\t\t\tgpios = <&tlmm 4 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n\n\tbeeper: beeper {\n\t\tcompatible = \"gpio-beeper\";\n\t\tgpios = <&tlmm 58 GPIO_ACTIVE_HIGH>;\n\t};\n};\n\n&tlmm {\n\tmdio_pins: mdio_pinmux {\n\t\tmux_1 {\n\t\t\tpins = \"gpio53\";\n\t\t\tfunction = \"mdio\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tmux_2 {\n\t\t\tpins = \"gpio52\";\n\t\t\tfunction = \"mdc\";\n\t\t\tbias-pull-up;\n\t\t};\n\t};\n\n\tserial_pins: serial_pinmux {\n\t\tmux {\n\t\t\tpins = \"gpio60\", \"gpio61\";\n\t\t\tfunction = \"blsp_uart0\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tspi_0_pins: spi_0_pinmux {\n\t\tpin {\n\t\t\tfunction = \"blsp_spi0\";\n\t\t\tpins = \"gpio55\", \"gpio56\", \"gpio57\";\n\t\t\tdrive-strength = <12>;\n\t\t\tbias-disable;\n\t\t};\n\t\tpin_cs {\n\t\t\tfunction = \"gpio\";\n\t\t\tpins = \"gpio54\";\n\t\t\tdrive-strength = <2>;\n\t\t\tbias-disable;\n\t\t\toutput-high;\n\t\t};\n\t};\n};\n\n&blsp_dma {\n\tstatus = \"okay\";\n};\n\n&blsp1_spi1 {\n\tpinctrl-0 = <&spi_0_pins>;\n\tpinctrl-names = \"default\";\n\tstatus = \"okay\";\n\tcs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;\n\n\tm25p80@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <24000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition0@0 {\n\t\t\t\tlabel = \"0:SBL1\";\n\t\t\t\treg = <0x00000000 0x00040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition1@40000 {\n\t\t\t\tlabel = \"0:MIBIB\";\n\t\t\t\treg = <0x00040000 0x00020000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition2@60000 {\n\t\t\t\tlabel = \"0:QSEE\";\n\t\t\t\treg = <0x00060000 0x00060000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition3@c0000 {\n\t\t\t\tlabel = \"0:CDT\";\n\t\t\t\treg = <0x000c0000 0x00010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition4@d0000 {\n\t\t\t\tlabel = \"0:DDRPARAMS\";\n\t\t\t\treg = <0x000d0000 0x00010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition5@e0000 {\n\t\t\t\tlabel = \"0:APPSBLENV\"; /* uboot env*/\n\t\t\t\treg = <0x000e0000 0x00010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition5@f0000 {\n\t\t\t\tlabel = \"0:APPSBL\"; /* uboot */\n\t\t\t\treg = <0x000f0000 0x00080000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition5@170000 {\n\t\t\t\tlabel = \"0:ART\";\n\t\t\t\treg = <0x00170000 0x00010000>;\n\t\t\t\tread-only;\n\t\t\t\tcompatible = \"nvmem-cells\";\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\n\t\t\t\tprecal_art_1000: precal@1000 {\n\t\t\t\t\treg = <0x1000 0x2f20>;\n\t\t\t\t};\n\n\t\t\t\tprecal_art_5000: precal@5000 {\n\t\t\t\t\treg = <0x5000 0x2f20>;\n\t\t\t\t};\n\t\t\t};\n\t\t\tpartition6@180000 {\n\t\t\t\tcompatible = \"denx,fit\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x00180000 0x01e80000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&blsp1_uart1 {\n\tpinctrl-0 = <&serial_pins>;\n\tpinctrl-names = \"default\";\n\tstatus = \"okay\";\n};\n\n&cryptobam {\n\tstatus = \"okay\";\n};\n\n&gmac0 {\n\tqcom,phy_mdio_addr = <4>;\n\tqcom,poll_required = <1>;\n\tqcom,forced_speed = <1000>;\n\tqcom,forced_duplex = <1>;\n\tvlan_tag = <2 0x20>;\n};\n\n&gmac1 {\n\tqcom,phy_mdio_addr = <3>;\n\tqcom,poll_required = <1>;\n\tqcom,forced_speed = <1000>;\n\tqcom,forced_duplex = <1>;\n\tvlan_tag = <1 0x10>;\n};\n\n&usb3_ss_phy {\n\tstatus = \"okay\";\n};\n\n&usb3_hs_phy {\n\tstatus = \"okay\";\n};\n\n&usb2_hs_phy {\n\tstatus = \"okay\";\n};\n\n&wifi0 {\n\tstatus = \"okay\";\n\tnvmem-cell-names = \"pre-calibration\";\n\tnvmem-cells = <&precal_art_1000>;\n};\n\n&wifi1 {\n\tstatus = \"okay\";\n\tnvmem-cell-names = \"pre-calibration\";\n\tnvmem-cells = <&precal_art_5000>;\n};\n"
  },
  {
    "path": "target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4029-ap-303.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-only OR MIT\n\n#include \"qcom-ipq4029-aruba-glenmorangie.dtsi\"\n#include <dt-bindings/gpio/gpio.h>\n\n/ {\n\tmodel = \"Aruba AP-303\";\n\tcompatible = \"aruba,ap-303\";\n\n\taliases {\n\t\tled-boot = &led_system_green;\n\t\tled-failsafe = &led_system_red;\n\t\tled-running = &led_system_green;\n\t\tled-upgrade = &led_system_red;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twifi_green {\n\t\t\tlabel = \"green:wifi\";\n\t\t\tgpios = <&tlmm 39 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\twifi_amber {\n\t\t\tlabel = \"amber:wifi\";\n\t\t\tgpios = <&tlmm 40 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\n\t\tled_system_red: system_red {\n\t\t\tlabel = \"red:system\";\n\t\t\tgpios = <&tlmm 46 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tled_system_green: system_green {\n\t\t\tlabel = \"green:system\";\n\t\t\tgpios = <&tlmm 47 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&tlmm {\n\t/*\n\t * In addition to the Pins listed below,\n\t * the following GPIOs have \"features\":\n\t * 54 - out - active low to force HW reset\n\t * 41 - out - active low to reset TPM\n\t * 43 - out - active low to reset BLE radio\n\t * 19 - in  - active high when DC powered\n\t */\n\n\tphy-reset {\n\t\tline-name = \"PHY-reset\";\n\t\tgpios = <42 GPIO_ACTIVE_HIGH>;\n\t\tgpio-hog;\n\t\toutput-high;\n\t};\n};\n\n&blsp1_spi1 {\n\tpinctrl-0 = <&spi_0_pins>;\n\tpinctrl-names = \"default\";\n\tstatus = \"okay\";\n\tcs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <24000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\t/*\n\t\t\t * There is no partition map for the NOR flash\n\t\t\t * in the stock firmware.\n\t\t\t *\n\t\t\t * All partitions here are based on offsets\n\t\t\t * found in the U-Boot GPL code and information\n\t\t\t * from smem.\n\t\t\t */\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"sbl1\";\n\t\t\t\treg = <0x0 0x40000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"mibib\";\n\t\t\t\treg = <0x40000 0x20000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@60000 {\n\t\t\t\tlabel = \"qsee\";\n\t\t\t\treg = <0x60000 0x60000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@c0000 {\n\t\t\t\tlabel = \"cdt\";\n\t\t\t\treg = <0xc0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@d0000 {\n\t\t\t\tlabel = \"ddrparams\";\n\t\t\t\treg = <0xd0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@e0000 {\n\t\t\t\tlabel = \"ART\";\n\t\t\t\treg = <0xe0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t\tcompatible = \"nvmem-cells\";\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\n\t\t\t\tprecal_art_1000: precal@1000 {\n\t\t\t\t\treg = <0x1000 0x2f20>;\n\t\t\t\t};\n\n\t\t\t\tprecal_art_5000: precal@5000 {\n\t\t\t\t\treg = <0x5000 0x2f20>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tpartition@f0000 {\n\t\t\t\tlabel = \"appsbl\";\n\t\t\t\treg = <0xf0000 0xf0000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@1e0000 {\n\t\t\t\tlabel = \"mfginfo\";\n\t\t\t\treg = <0x1e0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t\tcompatible = \"nvmem-cells\";\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\n\t\t\t\tmacaddr_mfginfo_1d: macaddr@1d {\n\t\t\t\t\treg = <0x1d 0x6>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tpartition@1f0000 {\n\t\t\t\tlabel = \"apcd\";\n\t\t\t\treg = <0x1f0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@200000 {\n\t\t\t\tlabel = \"osss\";\n\t\t\t\treg = <0x200000 0x180000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@380000 {\n\t\t\t\tlabel = \"appsblenv\";\n\t\t\t\treg = <0x380000 0x10000>;\n\t\t\t};\n\n\t\t\tpartition@390000 {\n\t\t\t\tlabel = \"pds\";\n\t\t\t\treg = <0x390000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@3a0000 {\n\t\t\t\tlabel = \"fcache\";\n\t\t\t\treg = <0x3a0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@3b0000 {\n\t\t\t\t/* Called osss1 in smem */\n\t\t\t\tlabel = \"u-boot-env-bak\";\n\t\t\t\treg = <0x3b0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@3f0000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x3f0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4029-ap-303h.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-only OR MIT\n\n#include \"qcom-ipq4019.dtsi\"\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/soc/qcom,tcsr.h>\n\n/ {\n\tmodel = \"Aruba AP-303H\";\n\tcompatible = \"aruba,ap-303h\";\n\n\taliases {\n\t\tled-boot = &led_system_green;\n\t\tled-failsafe = &led_system_red;\n\t\tled-running = &led_system_green;\n\t\tled-upgrade = &led_system_amber;\n\t};\n\n\tmemory {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x80000000 0x10000000>;\n\t};\n\n\tsoc {\n\t\trng@22000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tmdio@90000 {\n\t\t\tstatus = \"okay\";\n\t\t\tpinctrl-0 = <&mdio_pins>;\n\t\t\tpinctrl-names = \"default\";\n\n\t\t\treset-gpios = <&tlmm 19 GPIO_ACTIVE_LOW>;\n\t\t\treset-delay-us = <2000>;\n\t\t};\n\n\t\tcounter@4a1000 {\n\t\t\tcompatible = \"qcom,qca-gcnt\";\n\t\t\treg = <0x4a1000 0x4>;\n\t\t};\n\n\t\tess_tcsr@1953000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1953000 0x1000>;\n\t\t\tqcom,ess-interface-select = <TCSR_ESS_PSGMII>;\n\t\t};\n\n\t\ttcsr@1949000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1949000 0x100>;\n\t\t\tqcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;\n\t\t};\n\n\t\ttcsr@194b000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x194b000 0x100>;\n\t\t\tqcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;\n\t\t};\n\n\t\ttcsr@1957000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1957000 0x100>;\n\t\t\tqcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;\n\t\t};\n\n\t\tusb2@60f8800 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tcrypto@8e3a000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\twatchdog@b017000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tess-switch@c000000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tedma@c080000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\ti2c_0: i2c@78b7000 {\n\t\t\tpinctrl-0 = <&i2c_0_pins>;\n\t\t\tpinctrl-names = \"default\";\n\t\t\tstatus = \"okay\";\n\n\t\t\ttpm@29 {\n\t\t\t\t/* No Driver */\n\t\t\t\tcompatible = \"atmel,at97sc3203\";\n\t\t\t\treg = <0x29>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpower-monitor@40 {\n\t\t\t\t/* No driver */\n\t\t\t\tcompatible = \"isl,isl28022\";\n\t\t\t\treg = <0x40>;\n\t\t    };\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twifi_green {\n\t\t\tlabel = \"green:wifi\";\n\t\t\tgpios = <&tlmm 27 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\twifi_amber {\n\t\t\tlabel = \"amber:wifi\";\n\t\t\tgpios = <&tlmm 28 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\n\t\tpse {\n\t\t\tlabel = \"green:pse\";\n\t\t\tgpios = <&tlmm 42 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tled_system_red: system_red {\n\t\t\tlabel = \"red:system\";\n\t\t\tgpios = <&tlmm 25 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tled_system_green: system_green {\n\t\t\tlabel = \"green:system\";\n\t\t\tgpios = <&tlmm 24 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tled_system_amber: system_amber {\n\t\t\tlabel = \"amber:system\";\n\t\t\tgpios = <&tlmm 26 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"Reset button\";\n\t\t\tgpios = <&tlmm 18 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n};\n\n&blsp_dma {\n\tstatus = \"okay\";\n};\n\n&blsp1_uart1 {\n\tpinctrl-0 = <&serial_0_pins>;\n\tpinctrl-names = \"default\";\n\tstatus = \"okay\";\n};\n\n&blsp1_uart2 {\n\t/* Texas Instruments CC2540T BLE radio */\n\tpinctrl-0 = <&serial_1_pins>;\n\tpinctrl-names = \"default\";\n\tstatus = \"okay\";\n};\n\n&cryptobam {\n\tstatus = \"okay\";\n};\n\n&qpic_bam {\n\tstatus = \"okay\";\n};\n\n&tlmm {\n\t/*\n\t * In addition to the Pins listed below,\n\t * the following GPIOs have \"features\":\n\t * 39 - out - active low to force HW reset\n\t * 32 - out - active low to reset TPM\n\t * 43 - out - active low to reset BLE radio\n\t * 41 - out - pulse to set warm reset status\n\t * 34 - out - active low to enable PSE port\n\t * 22 - in  - active low when 802.3at powered\n\t * 29 - in  - active high when DC powered\n\t * 40 - in  - active low when reset due to cold HW reset\n\t * 30 - in  - active low when USB overcurrent detected\n\t * 35 - in  - interrupt line for power monitor chip\n\t * 31 - in  - active low when PSE port active\n\t */\n\tmdio_pins: mdio_pinmux {\n\t\tmux_1 {\n\t\t\tpins = \"gpio6\";\n\t\t\tfunction = \"mdio\";\n\t\t\tbias-pull-up;\n\t\t};\n\t\tmux_2 {\n\t\t\tpins = \"gpio7\";\n\t\t\tfunction = \"mdc\";\n\t\t\tbias-pull-up;\n\t\t};\n\t};\n\n\tspi_0_pins: spi_0_pinmux {\n\t\tpin {\n\t\t\tfunction = \"blsp_spi0\";\n\t\t\tpins = \"gpio13\", \"gpio14\", \"gpio15\";\n\t\t\tdrive-strength = <12>;\n\t\t\tbias-disable;\n\t\t};\n\t\tpin_cs {\n\t\t\tfunction = \"gpio\";\n\t\t\tpins = \"gpio12\", \"gpio59\";\n\t\t\tdrive-strength = <2>;\n\t\t\tbias-disable;\n\t\t\toutput-high;\n\t\t};\n\t};\n\n\ti2c_0_pins: i2c_0_pinmux {\n\t\tmux {\n\t\t\tpins = \"gpio20\", \"gpio21\";\n\t\t\tfunction = \"blsp_i2c0\";\n\t\t\tdrive-strength = <4>;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tserial_0_pins: serial_0_pinmux {\n\t\tmux {\n\t\t\tpins = \"gpio16\", \"gpio17\";\n\t\t\tfunction = \"blsp_uart0\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tserial_1_pins: serial_1_pinmux {\n\t\tmux {\n\t\t\tpins = \"gpio8\", \"gpio9\";\n\t\t\tfunction = \"blsp_uart1\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tusb-power {\n\t\tline-name = \"USB-power\";\n\t\tgpios = <23 GPIO_ACTIVE_HIGH>;\n\t\tgpio-hog;\n\t\toutput-high;\n\t};\n};\n\n&blsp1_spi1 {\n\tpinctrl-0 = <&spi_0_pins>;\n\tpinctrl-names = \"default\";\n\tstatus = \"okay\";\n\tcs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>, <&tlmm 59 GPIO_ACTIVE_HIGH>;\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <24000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\t/*\n\t\t\t * There is no partition map for the NOR flash\n\t\t\t * in the stock firmware.\n\t\t\t *\n\t\t\t * All partitions here are based on offsets\n\t\t\t * found in the U-Boot GPL code and information\n\t\t\t * from smem.\n\t\t\t */\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"sbl1\";\n\t\t\t\treg = <0x0 0x40000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"mibib\";\n\t\t\t\treg = <0x40000 0x20000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@60000 {\n\t\t\t\tlabel = \"qsee\";\n\t\t\t\treg = <0x60000 0x60000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@c0000 {\n\t\t\t\tlabel = \"cdt\";\n\t\t\t\treg = <0xc0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@d0000 {\n\t\t\t\tlabel = \"ddrparams\";\n\t\t\t\treg = <0xd0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@e0000 {\n\t\t\t\tlabel = \"appsblenv\";\n\t\t\t\treg = <0xe0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@f0000 {\n\t\t\t\tlabel = \"appsbl\";\n\t\t\t\treg = <0xf0000 0x100000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@1e0000 {\n\t\t\t\tlabel = \"ART\";\n\t\t\t\treg = <0x1f0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t\tcompatible = \"nvmem-cells\";\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\n\t\t\t\tprecal_art_1000: precal@1000 {\n\t\t\t\t\treg = <0x1000 0x2f20>;\n\t\t\t\t};\n\n\t\t\t\tprecal_art_5000: precal@5000 {\n\t\t\t\t\treg = <0x5000 0x2f20>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tpartition@1f0000 {\n\t\t\t\tlabel = \"osss\";\n\t\t\t\treg = <0x200000 0x170000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@200000 {\n\t\t\t\tlabel = \"pds\";\n\t\t\t\treg = <0x370000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@380000 {\n\t\t\t\tlabel = \"apcd\";\n\t\t\t\treg = <0x380000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@390000 {\n\t\t\t\tlabel = \"mfginfo\";\n\t\t\t\treg = <0x390000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t\tcompatible = \"nvmem-cells\";\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\n\t\t\t\tmacaddr_mfginfo_1d: macaddr@1d {\n\t\t\t\t\treg = <0x1d 0x6>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tpartition@3a0000 {\n\t\t\t\tlabel = \"fcache\";\n\t\t\t\treg = <0x3a0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@3b0000 {\n\t\t\t\t/* Called osss1 in smem */\n\t\t\t\tlabel = \"u-boot-env-bak\";\n\t\t\t\treg = <0x3b0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@3f0000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x3c0000 0x40000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n\n\tflash@1 {\n\t\tstatus = \"okay\";\n\n\t\tcompatible = \"spi-nand\";\n\t\treg = <1>;\n\t\tspi-max-frequency = <24000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\t/* 'aos0' in Aruba firmware */\n\t\t\t\tlabel = \"aos0\";\n\t\t\t\treg = <0x0 0x2000000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@2000000 {\n\t\t\t\t/* 'aos1' in Aruba firmware */\n\t\t\t\tlabel = \"ubi\";\n\t\t\t\treg = <0x2000000 0x2000000>;\n\t\t\t};\n\n\t\t\tpartition@4000000 {\n\t\t\t\tlabel = \"aruba-ubifs\";\n\t\t\t\treg = <0x4000000 0x4000000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&usb2_hs_phy {\n\tstatus = \"okay\";\n};\n\n&wifi0 {\n\tstatus = \"okay\";\n\tqcom,ath10k-calibration-variant = \"Aruba-AP-303\";\n\tnvmem-cell-names = \"pre-calibration\", \"mac-address\";\n\tnvmem-cells = <&precal_art_1000>, <&macaddr_mfginfo_1d>;\n\tqcom,ath10k-calibration-variant = \"Aruba-AP-303\";\n};\n\n&wifi1 {\n\tstatus = \"okay\";\n\tqcom,ath10k-calibration-variant = \"Aruba-AP-303\";\n\tnvmem-cell-names = \"pre-calibration\", \"mac-address\";\n\tnvmem-cells = <&precal_art_5000>, <&macaddr_mfginfo_1d>;\n\tmac-address-increment = <1>;\n\tqcom,ath10k-calibration-variant = \"Aruba-AP-303\";\n};\n"
  },
  {
    "path": "target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4029-ap-365.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-only OR MIT\n\n#include \"qcom-ipq4029-aruba-glenmorangie.dtsi\"\n#include <dt-bindings/gpio/gpio.h>\n\n/ {\n\tmodel = \"Aruba AP-365\";\n\tcompatible = \"aruba,ap-365\";\n\n\taliases {\n\t\tled-boot = &led_system_green;\n\t\tled-failsafe = &led_system_red;\n\t\tled-running = &led_system_green;\n\t\tled-upgrade = &led_system_red;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_system_red: system_red {\n\t\t\tlabel = \"red:system\";\n\t\t\tgpios = <&tlmm 46 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_system_green: system_green {\n\t\t\tlabel = \"green:system\";\n\t\t\tgpios = <&tlmm 61 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tsystem_amber {\n\t\t\tlabel = \"amber:system\";\n\t\t\tgpios = <&tlmm 49 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\twatchdog {\n\t\tcompatible = \"linux,wdt-gpio\";\n\t\tgpios = <&tlmm 41 GPIO_ACTIVE_LOW>;\n\t\thw_algo = \"toggle\";\n\t\thw_margin_ms = <1000>;\n\t\talways-running;\n\t};\n};\n\n&tlmm {\n\t/*\n\t * In addition to the Pins listed below,\n\t * the following GPIOs have \"features\":\n\t * 39 - out - pulse low to reset watchdog status flipflop\n\t * 40 - out - active high to enable watchdog\n\t * 41 - out - watchdog poke\n\t * 42 - out - active low to reset BLE radio\n\t * 43 - out - active low to reset TPM\n\t * 47 - out - pulse low to reset warm reset status\n\t * 54 - out - active low to force HW reset\n\t * 18 - in  - PHY interrupt line\n\t * 45 - in  - power monitor interrupt\n\t * 48 - in  - active low when cold reset\n\t * 52 - in  - active high when watchdog reset\n\t */\n\n\tphy-reset {\n\t\tline-name = \"PHY-reset\";\n\t\tgpios = <42 GPIO_ACTIVE_HIGH>;\n\t\tgpio-hog;\n\t\toutput-high;\n\t};\n};\n\n&i2c_0 {\n\tpower-monitor@40 {\n\t\t/* No driver */\n\t\tcompatible = \"isl,isl28022\";\n\t\treg = <0x40>;\n\t};\n\n\ttemperature-sensor@48 {\n\t\tcompatible = \"adi,ad7416\";\n\t\treg = <0x48>;\n\t};\n};\n\n&blsp1_spi1 {\n\tpinctrl-0 = <&spi_0_pins>;\n\tpinctrl-names = \"default\";\n\tstatus = \"okay\";\n\tcs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <24000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\t/*\n\t\t\t * There is no partition map for the NOR flash\n\t\t\t * in the stock firmware.\n\t\t\t *\n\t\t\t * All partitions here are based on offsets\n\t\t\t * found in the U-Boot GPL code and information\n\t\t\t * from smem.\n\t\t\t */\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"sbl1\";\n\t\t\t\treg = <0x0 0x40000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"mibib\";\n\t\t\t\treg = <0x40000 0x20000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@60000 {\n\t\t\t\tlabel = \"qsee\";\n\t\t\t\treg = <0x60000 0x60000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@c0000 {\n\t\t\t\tlabel = \"cdt\";\n\t\t\t\treg = <0xc0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@d0000 {\n\t\t\t\tlabel = \"ddrparams\";\n\t\t\t\treg = <0xd0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@e0000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0xe0000 0x10000>;\n\t\t\t};\n\n\t\t\tpartition@f0000 {\n\t\t\t\tlabel = \"appsbl\";\n\t\t\t\treg = <0xf0000 0x100000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@1f0000 {\n\t\t\t\tlabel = \"ART\";\n\t\t\t\treg = <0x1f0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t\tcompatible = \"nvmem-cells\";\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\n\t\t\t\tprecal_art_1000: precal@1000 {\n\t\t\t\t\treg = <0x1000 0x2f20>;\n\t\t\t\t};\n\n\t\t\t\tprecal_art_5000: precal@5000 {\n\t\t\t\t\treg = <0x5000 0x2f20>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tpartition@200000 {\n\t\t\t\tlabel = \"osss\";\n\t\t\t\treg = <0x200000 0x170000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@370000 {\n\t\t\t\tlabel = \"pds\";\n\t\t\t\treg = <0x370000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@380000 {\n\t\t\t\tlabel = \"apcd\";\n\t\t\t\treg = <0x380000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@390000 {\n\t\t\t\tlabel = \"mfginfo\";\n\t\t\t\treg = <0x390000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t\tcompatible = \"nvmem-cells\";\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\n\t\t\t\tmacaddr_mfginfo_1d: macaddr@1d {\n\t\t\t\t\treg = <0x1d 0x6>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tpartition@3a0000 {\n\t\t\t\tlabel = \"fcache\";\n\t\t\t\treg = <0x3a0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@3b0000 {\n\t\t\t\tlabel = \"osss1\";\n\t\t\t\treg = <0x3b0000 0x50000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4029-aruba-glenmorangie.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-only OR MIT\n\n#include \"qcom-ipq4019.dtsi\"\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/soc/qcom,tcsr.h>\n\n/ {\n\tmemory {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x80000000 0x10000000>;\n\t};\n\n\tsoc {\n\t\trng@22000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tmdio@90000 {\n\t\t\tstatus = \"okay\";\n\t\t\tpinctrl-0 = <&mdio_pins>;\n\t\t\tpinctrl-names = \"default\";\n\n\t\t\t/delete-node/ ethernet-phy@0;\n\t\t\t/delete-node/ ethernet-phy@1;\n\t\t\t/delete-node/ ethernet-phy@2;\n\t\t\t/delete-node/ ethernet-phy@3;\n\t\t\t/delete-node/ ethernet-phy@4;\n\t\t\t/delete-node/ psgmii-phy@5;\n\n\t\t\tethernet-phy@5 {\n\t\t\t\treg = <0x5>;\n\t\t\t};\n\t\t};\n\n\t\tcounter@4a1000 {\n\t\t\tcompatible = \"qcom,qca-gcnt\";\n\t\t\treg = <0x4a1000 0x4>;\n\t\t};\n\n\t\tess_tcsr@1953000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1953000 0x1000>;\n\t\t\tqcom,ess-interface-select = <TCSR_ESS_PSGMII_RGMII5>;\n\t\t};\n\n\t\ttcsr@1949000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1949000 0x100>;\n\t\t\tqcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;\n\t\t};\n\n\t\ttcsr@1957000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1957000 0x100>;\n\t\t\tqcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;\n\t\t};\n\n\t\tcrypto@8e3a000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\twatchdog@b017000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tess-switch@c000000 {\n\t\t\tswitch_mac_mode = <0x3>; /* mac mode for RGMII RMII */\n\t\t\tswitch_lan_bmp = <0x0>; /* lan port bitmap */\n\t\t\tswitch_wan_bmp = <0x10>; /* wan port bitmap */\n\t\t};\n\n\t\tedma@c080000 {\n\t\t\tqcom,single-phy;\n\t\t\tqcom,num_gmac = <1>;\n\t\t\tphy-mode = \"rgmii-id\";\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\ti2c_0: i2c@78b7000 {\n\t\t\tpinctrl-0 = <&i2c_0_pins>;\n\t\t\tpinctrl-names = \"default\";\n\t\t\tstatus = \"okay\";\n\n\t\t\ttpm@29 {\n\t\t\t\t/* No Driver */\n\t\t\t\tcompatible = \"atmel,at97sc3203\";\n\t\t\t\treg = <0x29>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"Reset button\";\n\t\t\tgpios = <&tlmm 50 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n};\n\n&blsp_dma {\n\tstatus = \"okay\";\n};\n\n&blsp1_uart1 {\n\t/* Texas Instruments CC2540T BLE radio */\n\tpinctrl-0 = <&serial_0_pins>;\n\tpinctrl-names = \"default\";\n\tstatus = \"okay\";\n};\n\n&blsp1_uart2 {\n\tpinctrl-0 = <&serial_1_pins>;\n\tpinctrl-names = \"default\";\n\tstatus = \"okay\";\n};\n\n&cryptobam {\n\tstatus = \"okay\";\n};\n\n&gmac0 {\n\tqcom,phy_mdio_addr = <5>;\n\tqcom,poll_required = <1>;\n\tvlan_tag = <0 0x20>;\n};\n\n&qpic_bam {\n\tstatus = \"okay\";\n};\n\n&tlmm {\n\tmdio_pins: mdio_pinmux {\n\t\tmux_1 {\n\t\t\tpins = \"gpio6\";\n\t\t\tfunction = \"mdio\";\n\t\t\tbias-pull-up;\n\t\t};\n\t\tmux_2 {\n\t\t\tpins = \"gpio7\";\n\t\t\tfunction = \"mdc\";\n\t\t\tbias-pull-up;\n\t\t};\n\t};\n\n\tnand_pins: nand_pins {\n\t\tpullups {\n\t\t\tpins = \"gpio53\", \"gpio58\", \"gpio59\";\n\t\t\tfunction = \"qpic\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tpulldowns {\n\t\t\tpins = \"gpio54\", \"gpio55\", \"gpio56\",\n\t\t\t\t\"gpio57\", \"gpio60\", \"gpio61\",\n\t\t\t\t\"gpio62\", \"gpio63\", \"gpio64\",\n\t\t\t\t\"gpio65\", \"gpio66\", \"gpio67\",\n\t\t\t\t\"gpio68\", \"gpio69\";\n\t\t\tfunction = \"qpic\";\n\t\t\tbias-pull-down;\n\t\t};\n\t};\n\n\tspi_0_pins: spi_0_pinmux {\n\t\tpin {\n\t\t\tfunction = \"blsp_spi0\";\n\t\t\tpins = \"gpio13\", \"gpio14\", \"gpio15\";\n\t\t\tdrive-strength = <12>;\n\t\t\tbias-disable;\n\t\t};\n\t\tpin_cs {\n\t\t\tfunction = \"gpio\";\n\t\t\tpins = \"gpio12\";\n\t\t\tdrive-strength = <2>;\n\t\t\tbias-disable;\n\t\t\toutput-high;\n\t\t};\n\t};\n\n\ti2c_0_pins: i2c_0_pinmux {\n\t\tmux {\n\t\t\tpins = \"gpio10\", \"gpio11\";\n\t\t\tfunction = \"blsp_i2c0\";\n\t\t\tdrive-strength = <4>;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tserial_0_pins: serial_0_pinmux {\n\t\tmux {\n\t\t\tpins = \"gpio16\", \"gpio17\";\n\t\t\tfunction = \"blsp_uart0\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tserial_1_pins: serial_1_pinmux {\n\t\tmux {\n\t\t\tpins = \"gpio8\", \"gpio9\";\n\t\t\tfunction = \"blsp_uart1\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&nand {\n\tpinctrl-0 = <&nand_pins>;\n\tpinctrl-names = \"default\";\n\tstatus = \"okay\";\n\n\tnand@0 {\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\t/* 'aos0' in Aruba firmware */\n\t\t\t\tlabel = \"aos0\";\n\t\t\t\treg = <0x0 0x2000000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@2000000 {\n\t\t\t\t/* 'aos1' in Aruba firmware */\n\t\t\t\tlabel = \"ubi\";\n\t\t\t\treg = <0x2000000 0x2000000>;\n\t\t\t};\n\n\t\t\tpartition@4000000 {\n\t\t\t\tlabel = \"aruba-ubifs\";\n\t\t\t\treg = <0x4000000 0x4000000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&wifi0 {\n\tstatus = \"okay\";\n\tnvmem-cell-names = \"pre-calibration\", \"mac-address\";\n\tnvmem-cells = <&precal_art_1000>, <&macaddr_mfginfo_1d>;\n\tqcom,ath10k-calibration-variant = \"Aruba-AP-303\";\n};\n\n&wifi1 {\n\tstatus = \"okay\";\n\tnvmem-cell-names = \"pre-calibration\", \"mac-address\";\n\tnvmem-cells = <&precal_art_5000>, <&macaddr_mfginfo_1d>;\n\tmac-address-increment = <1>;\n\tqcom,ath10k-calibration-variant = \"Aruba-AP-303\";\n};\n"
  },
  {
    "path": "target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4029-gl-b1300.dts",
    "content": "/* Copyright (c) 2015, The Linux Foundation. All rights reserved.\n *\n * Permission to use, copy, modify, and/or distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n *\n */\n\n#include \"qcom-ipq4019.dtsi\"\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/soc/qcom,tcsr.h>\n\n/ {\n\tmodel = \"GL.iNet GL-B1300\";\n\tcompatible = \"glinet,gl-b1300\";\n\n\taliases {\n\t\tled-boot = &power;\n\t\tled-failsafe = &power;\n\t\tled-running = &power;\n\t\tled-upgrade = &power;\n\t};\n\n\tmemory {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x80000000 0x10000000>;\n\t};\n\n\tsoc {\n\t\trng@22000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tmdio@90000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tess-psgmii@98000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\ttcsr@1949000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1949000 0x100>;\n\t\t\tqcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;\n\t\t};\n\n\t\ttcsr@194b000 {\n\t\t\t/* select hostmode */\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x194b000 0x100>;\n\t\t\tqcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tess_tcsr@1953000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1953000 0x1000>;\n\t\t\tqcom,ess-interface-select = <TCSR_ESS_PSGMII>;\n\t\t};\n\n\t\ttcsr@1957000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1957000 0x100>;\n\t\t\tqcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;\n\t\t};\n\n\t\tusb2@60f8800 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tusb3@8af8800 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tcrypto@8e3a000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\twatchdog@b017000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tess-switch@c000000 {\n\t\t\tstatus = \"okay\";\n\t\t\tswitch_lan_bmp = <0x18>;\n\t\t\tswitch_wan_bmp = <0x20>;\n\t\t};\n\n\t\tedma@c080000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&tlmm 5 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&tlmm 63 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tpower: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&tlmm 4 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\tmesh {\n\t\t\tlabel = \"green:mesh\";\n\t\t\tgpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\twlan {\n\t\t\tlabel = \"green:wlan\";\n\t\t\tgpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&blsp_dma {\n\tstatus = \"okay\";\n};\n\n&cryptobam {\n\tstatus = \"okay\";\n};\n\n&blsp1_spi1 {\n\tpinctrl-0 = <&spi_0_pins>;\n\tpinctrl-names = \"default\";\n\tstatus = \"okay\";\n\tcs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;\n\n\tmx25l25635f@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <24000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tSBL1@0 {\n\t\t\t\tlabel = \"SBL1\";\n\t\t\t\treg = <0x0 0x40000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tMIBIB@40000 {\n\t\t\t\tlabel = \"MIBIB\";\n\t\t\t\treg = <0x40000 0x20000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tQSEE@60000 {\n\t\t\t\tlabel = \"QSEE\";\n\t\t\t\treg = <0x60000 0x60000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tCDT@c0000 {\n\t\t\t\tlabel = \"CDT\";\n\t\t\t\treg = <0xc0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tDDRPARAMS@d0000 {\n\t\t\t\tlabel = \"DDRPARAMS\";\n\t\t\t\treg = <0xd0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tAPPSBLENV@e0000 {\n\t\t\t\tlabel = \"APPSBLENV\";\n\t\t\t\treg = <0xe0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tAPPSBL@f0000 {\n\t\t\t\tlabel = \"APPSBL\";\n\t\t\t\treg = <0xf0000 0x80000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tART@170000 {\n\t\t\t\tlabel = \"ART\";\n\t\t\t\treg = <0x170000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t\tcompatible = \"nvmem-cells\";\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\n\t\t\t\tprecal_art_1000: precal@1000 {\n\t\t\t\t\treg = <0x1000 0x2f20>;\n\t\t\t\t};\n\n\t\t\t\tprecal_art_5000: precal@5000 {\n\t\t\t\t\treg = <0x5000 0x2f20>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tfirmware@180000 {\n\t\t\t\tcompatible = \"denx,fit\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x180000 0x1e80000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&blsp1_uart1 {\n\tpinctrl-0 = <&serial_pins>;\n\tpinctrl-names = \"default\";\n\tstatus = \"okay\";\n};\n\n&tlmm {\n\tserial_pins: serial_pinmux {\n\t\tmux {\n\t\t\tpins = \"gpio60\", \"gpio61\";\n\t\t\tfunction = \"blsp_uart0\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tspi_0_pins: spi_0_pinmux {\n\t\tpinmux {\n\t\t\tfunction = \"blsp_spi0\";\n\t\t\tpins = \"gpio55\", \"gpio56\", \"gpio57\";\n\t\t};\n\t\tpinmux_cs {\n\t\t\tfunction = \"gpio\";\n\t\t\tpins = \"gpio54\";\n\t\t};\n\t\tpinconf {\n\t\t\tpins = \"gpio55\", \"gpio56\", \"gpio57\";\n\t\t\tdrive-strength = <12>;\n\t\t\tbias-disable;\n\t\t};\n\t\tpinconf_cs {\n\t\t\tpins = \"gpio54\";\n\t\t\tdrive-strength = <2>;\n\t\t\tbias-disable;\n\t\t\toutput-high;\n\t\t};\n\t};\n};\n\n&usb2_hs_phy {\n\tstatus = \"okay\";\n};\n\n&usb3_hs_phy {\n\tstatus = \"okay\";\n};\n\n&usb3_ss_phy {\n\tstatus = \"okay\";\n};\n\n&wifi0 {\n\tstatus = \"okay\";\n\tnvmem-cell-names = \"pre-calibration\";\n\tnvmem-cells = <&precal_art_1000>;\n\tqcom,ath10k-calibration-variant = \"GL-B1300\";\n};\n\n&wifi1 {\n\tstatus = \"okay\";\n\tnvmem-cell-names = \"pre-calibration\";\n\tnvmem-cells = <&precal_art_5000>;\n\tqcom,ath10k-calibration-variant = \"GL-B1300\";\n};\n"
  },
  {
    "path": "target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4029-gl-s1300.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-only OR MIT\n\n#include \"qcom-ipq4019.dtsi\"\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/soc/qcom,tcsr.h>\n\n/ {\n\tmodel = \"GL.iNet GL-S1300\";\n\tcompatible = \"glinet,gl-s1300\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tmemory {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x80000000 0x10000000>;\n\t};\n\n\tsoc {\n\t\trng@22000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tmdio@90000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tess-psgmii@98000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\ttcsr@1949000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1949000 0x100>;\n\t\t\tqcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;\n\t\t};\n\n\t\ttcsr@194b000 {\n\t\t\t/* select hostmode */\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x194b000 0x100>;\n\t\t\tqcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tess_tcsr@1953000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1953000 0x1000>;\n\t\t\tqcom,ess-interface-select = <TCSR_ESS_PSGMII>;\n\t\t};\n\n\t\ttcsr@1957000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1957000 0x100>;\n\t\t\tqcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;\n\t\t};\n\n\t\tusb2@60f8800 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tusb3@8af8800 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tcrypto@8e3a000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\twatchdog@b017000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tess-switch@c000000 {\n\t\t\tstatus = \"okay\";\n\t\t\tswitch_lan_bmp = <0x18>;\n\t\t\tswitch_wan_bmp = <0x20>;\n\t\t};\n\n\t\tedma@c080000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&tlmm 53 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&tlmm 18 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&tlmm 57 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\tmesh {\n\t\t\tlabel = \"green:mesh\";\n\t\t\tgpios = <&tlmm 59 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\twlan {\n\t\t\tlabel = \"green:wlan\";\n\t\t\tgpios = <&tlmm 60 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\t};\n};\n\n&vqmmc {\n\tstatus = \"okay\";\n};\n\n&sdhci {\n\tstatus = \"okay\";\n\tpinctrl-0 = <&sd_pins>;\n\tpinctrl-names = \"default\";\n\tcd-gpios = <&tlmm 22 GPIO_ACTIVE_LOW>;\n\tvqmmc-supply = <&vqmmc>;\n};\n\n&blsp_dma {\n\tstatus = \"okay\";\n};\n\n&cryptobam {\n\tstatus = \"okay\";\n};\n\n&blsp1_spi1 {\n\tpinctrl-0 = <&spi_0_pins>;\n\tpinctrl-names = \"default\";\n\tstatus = \"okay\";\n\tcs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <24000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tSBL1@0 {\n\t\t\t\tlabel = \"SBL1\";\n\t\t\t\treg = <0x0 0x40000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tMIBIB@40000 {\n\t\t\t\tlabel = \"MIBIB\";\n\t\t\t\treg = <0x40000 0x20000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tQSEE@60000 {\n\t\t\t\tlabel = \"QSEE\";\n\t\t\t\treg = <0x60000 0x60000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tCDT@c0000 {\n\t\t\t\tlabel = \"CDT\";\n\t\t\t\treg = <0xc0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tDDRPARAMS@d0000 {\n\t\t\t\tlabel = \"DDRPARAMS\";\n\t\t\t\treg = <0xd0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tAPPSBLENV@e0000 {\n\t\t\t\tlabel = \"APPSBLENV\";\n\t\t\t\treg = <0xe0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tAPPSBL@f0000 {\n\t\t\t\tlabel = \"APPSBL\";\n\t\t\t\treg = <0xf0000 0x80000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tART@170000 {\n\t\t\t\tlabel = \"ART\";\n\t\t\t\treg = <0x170000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t\tcompatible = \"nvmem-cells\";\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\n\t\t\t\tprecal_art_1000: precal@1000 {\n\t\t\t\t\treg = <0x1000 0x2f20>;\n\t\t\t\t};\n\n\t\t\t\tprecal_art_5000: precal@5000 {\n\t\t\t\t\treg = <0x5000 0x2f20>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tfirmware@180000 {\n\t\t\t\tcompatible = \"denx,fit\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x180000 0xe80000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&blsp1_spi2 {\n\tpinctrl-0 = <&spi_1_pins>;\n\tpinctrl-names = \"default\";\n\tstatus = \"okay\";\n\n\tspidev1: spi@0 {\n\t\tcompatible = \"siliconlabs,si3210\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <24000000>;\n\t};\n};\n\n&blsp1_uart1 {\n\tpinctrl-0 = <&serial_pins>;\n\tpinctrl-names = \"default\";\n\tstatus = \"okay\";\n};\n\n&blsp1_uart2 {\n\tpinctrl-0 = <&serial_1_pins>;\n\tpinctrl-names = \"default\";\n\tstatus = \"okay\";\n};\n\n&tlmm {\n\tserial_pins: serial_pinmux {\n\t\tmux {\n\t\t\tpins = \"gpio16\", \"gpio17\";\n\t\t\tfunction = \"blsp_uart0\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tserial_1_pins: serial1_pinmux {\n\t\tmux {\n\t\t\tpins = \"gpio8\", \"gpio9\",\n\t\t\t\t\"gpio10\", \"gpio11\";\n\t\t\tfunction = \"blsp_uart1\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tspi_0_pins: spi_0_pinmux {\n\t\tpinmux {\n\t\t\tfunction = \"blsp_spi0\";\n\t\t\tpins = \"gpio13\", \"gpio14\", \"gpio15\";\n\t\t};\n\t\tpinmux_cs {\n\t\t\tfunction = \"gpio\";\n\t\t\tpins = \"gpio12\";\n\t\t};\n\t\tpinconf {\n\t\t\tpins = \"gpio13\", \"gpio14\", \"gpio15\";\n\t\t\tdrive-strength = <12>;\n\t\t\tbias-disable;\n\t\t};\n\t\tpinconf_cs {\n\t\t\tpins = \"gpio12\";\n\t\t\tdrive-strength = <2>;\n\t\t\tbias-disable;\n\t\t\toutput-high;\n\t\t};\n\t};\n\n\tspi_1_pins: spi_1_pinmux {\n\t\tmux {\n\t\t\tpins = \"gpio44\", \"gpio46\", \"gpio47\";\n\t\t\tfunction = \"blsp_spi1\";\n\t\t\tbias-disable;\n\t\t};\n\t\thost_int {\n\t\t\tpins = \"gpio42\";\n\t\t\tfunction = \"gpio\";\n\t\t\tinput;\n\t\t};\n\t\tcs {\n\t\t\tpins = \"gpio45\";\n\t\t\tfunction = \"gpio\";\n\t\t\tbias-pull-up;\n\t\t};\n\t\twake {\n\t\t\tpins = \"gpio40\";\n\t\t\tfunction = \"gpio\";\n\t\t\toutput-high;\n\t\t};\n\t\treset {\n\t\t\tpins = \"gpio49\";\n\t\t\tfunction = \"gpio\";\n\t\t\toutput-high;\n\t\t};\n\t};\n\n\tsd_pins: sd_pins {\n\t\tpinmux {\n\t\t\tfunction = \"sdio\";\n\t\t\tpins = \"gpio23\", \"gpio24\", \"gpio25\", \"gpio26\",\n\t\t\t\t\"gpio28\", \"gpio29\", \"gpio30\", \"gpio31\";\n\t\t\tdrive-strength = <10>;\n\t\t};\n\n\t\tpinmux_sd_clk {\n\t\t\tfunction = \"sdio\";\n\t\t\tpins = \"gpio27\";\n\t\t\tdrive-strength = <16>;\n\t\t};\n\n\t\tpinmux_sd7 {\n\t\t\tfunction = \"sdio\";\n\t\t\tpins = \"gpio32\";\n\t\t\tdrive-strength = <10>;\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&usb2_hs_phy {\n\tstatus = \"okay\";\n};\n\n&usb3_hs_phy {\n\tstatus = \"okay\";\n};\n\n&usb3_ss_phy {\n\tstatus = \"okay\";\n};\n\n&wifi0 {\n\tstatus = \"okay\";\n\tnvmem-cell-names = \"pre-calibration\";\n\tnvmem-cells = <&precal_art_1000>;\n\tqcom,ath10k-calibration-variant = \"GL-S1300\";\n};\n\n&wifi1 {\n\tstatus = \"okay\";\n\tnvmem-cell-names = \"pre-calibration\";\n\tnvmem-cells = <&precal_art_5000>;\n\tqcom,ath10k-calibration-variant = \"GL-S1300\";\n};\n"
  },
  {
    "path": "target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4029-mr33.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-only\n/*\n * Device Tree Source for Meraki MR33 (Stinkbug)\n *\n * Copyright (C) 2017 Chris Blake <chrisrblake93@gmail.com>\n * Copyright (C) 2017 Christian Lamparter <chunkeey@googlemail.com>\n *\n * Based on Cisco Meraki DTS from GPL release r25-linux-3.14-20170427\n *\n * This file is licensed under the terms of the GNU General Public\n * License version 2.  This program is licensed \"as is\" without\n * any warranty of any kind, whether express or implied.\n */\n\n#include \"qcom-ipq4019.dtsi\"\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/soc/qcom,tcsr.h>\n#include <dt-bindings/leds/common.h>\n\n/ {\n\tmodel = \"Meraki MR33 Access Point\";\n\tcompatible = \"meraki,mr33\";\n\n\taliases {\n\t\tled-boot = &status_green;\n\t\tled-failsafe = &status_red;\n\t\tled-running = &status_green;\n\t\tled-upgrade = &power_orange;\n\t};\n\n\t/* Do we really need this defined? */\n\tmemory {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x80000000 0x10000000>;\n\t};\n\n\tsoc {\n\t\trng@22000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tmdio@90000 {\n\t\t\tstatus = \"okay\";\n\t\t\tpinctrl-0 = <&mdio_pins>;\n\t\t\tpinctrl-names = \"default\";\n\t\t};\n\n\t\t/* It is a 56-bit counter that supplies the count to the ARM arch\n\t\t   timers and without upstream driver */\n\t\tcounter@4a1000 {\n\t\t\tcompatible = \"qcom,qca-gcnt\";\n\t\t\treg = <0x4a1000 0x4>;\n\t\t};\n\n\t\tess_tcsr@1953000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1953000 0x1000>;\n\t\t\tqcom,ess-interface-select = <TCSR_ESS_PSGMII_RGMII5>;\n\t\t};\n\n\t\ttcsr@1949000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1949000 0x100>;\n\t\t\tqcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;\n\t\t};\n\n\t\ttcsr@1957000 {\n\t\t\tcompatible = \"qcom,tcsr\";\n\t\t\treg = <0x1957000 0x100>;\n\t\t\tqcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;\n\t\t};\n\n\t\tserial@78b0000 {\n\t\t\tpinctrl-0 = <&serial_1_pins>;\n\t\t\tpinctrl-names = \"default\";\n\t\t\tstatus = \"okay\";\n\n\t\t\tbluetooth {\n\t\t\t\tcompatible = \"ti,cc2650\";\n\t\t\t\tenable-gpios = <&tlmm 12 GPIO_ACTIVE_LOW>;\n\t\t\t};\n\t\t};\n\n\t\tcrypto@8e3a000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\twatchdog@b017000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tess-switch@c000000 {\n\t\t\tswitch_mac_mode = <0x3>; /* mac mode for RGMII RMII */\n\t\t\tswitch_lan_bmp = <0x0>; /* lan port bitmap */\n\t\t\tswitch_wan_bmp = <0x10>; /* wan port bitmap */\n\t\t};\n\n\t\tedma@c080000 {\n\t\t\tqcom,single-phy;\n\t\t\tqcom,num_gmac = <1>;\n\t\t\tphy-mode = \"rgmii-rxid\";\n\t\t\tstatus = \"okay\";\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&tlmm 18 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tpower_orange: power {\n\t\t\tlabel = \"orange:power\";\n\t\t\tgpios = <&tlmm 49 GPIO_ACTIVE_LOW>;\n\t\t\tpanic-indicator;\n\t\t};\n\t};\n};\n\n&blsp_dma {\n\tstatus = \"okay\";\n};\n\n&blsp1_uart1 {\n\tpinctrl-0 = <&serial_0_pins>;\n\tpinctrl-names = \"default\";\n\tstatus = \"okay\";\n};\n\n&cryptobam {\n\tstatus = \"okay\";\n};\n\n&gmac0 {\n\tqcom,phy_mdio_addr = <1>;\n\tqcom,poll_required = <1>;\n\tvlan_tag = <0 0x20>;\n};\n\n&blsp1_i2c3 {\n\tpinctrl-0 = <&i2c_0_pins>;\n\tpinctrl-names = \"default\";\n\tstatus = \"okay\";\n\tat24@50 {\n\t\tcompatible = \"atmel,24c64\";\n\t\tpagesize = <32>;\n\t\treg = <0x50>;\n\t\tread-only; /* This holds our MAC & Meraki board-data */\n\t};\n};\n\n&blsp1_i2c4 {\n\tpinctrl-0 = <&i2c_1_pins>;\n\tpinctrl-names = \"default\";\n\tstatus = \"okay\";\n\n\tled-controller@30 {\n\t\tcompatible = \"ti,lp5562\";\n\t\treg = <0x30>;\n\t\tclock-mode = /bits/8 <2>;\n\t\tenable-gpio = <&tlmm 48 GPIO_ACTIVE_HIGH>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\t/* RGB led */\n\t\tstatus_red: chan@0 {\n\t\t\tchan-name = \"red:status\";\n\t\t\tled-cur = /bits/ 8 <0x20>;\n\t\t\tmax-cur = /bits/ 8 <0x60>;\n\t\t\treg = <0>;\n\t\t\tcolor = <LED_COLOR_ID_RED>;\n\t\t};\n\n\t\tstatus_green: chan@1 {\n\t\t\tchan-name = \"green:status\";\n\t\t\tled-cur = /bits/ 8 <0x20>;\n\t\t\tmax-cur = /bits/ 8 <0x60>;\n\t\t\treg = <1>;\n\t\t\tcolor = <LED_COLOR_ID_GREEN>;\n\t\t};\n\n\t\tchan@2 {\n\t\t\tchan-name = \"blue:status\";\n\t\t\tled-cur = /bits/ 8 <0x20>;\n\t\t\tmax-cur = /bits/ 8 <0x60>;\n\t\t\treg = <2>;\n\t\t\tcolor = <LED_COLOR_ID_BLUE>;\n\t\t};\n\n\t\tchan@3 {\n\t\t\tchan-name = \"white:status\";\n\t\t\tled-cur = /bits/ 8 <0x20>;\n\t\t\tmax-cur = /bits/ 8 <0x60>;\n\t\t\treg = <3>;\n\t\t\tcolor = <LED_COLOR_ID_WHITE>;\n\t\t};\n\t};\n};\n\n&nand {\n\tpinctrl-0 = <&nand_pins>;\n\tpinctrl-names = \"default\";\n\tstatus = \"okay\";\n\n\tnand@0 {\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"sbl1\";\n\t\t\t\treg = <0x00000000 0x00100000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@100000 {\n\t\t\t\tlabel = \"mibib\";\n\t\t\t\treg = <0x00100000 0x00100000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@200000 {\n\t\t\t\tlabel = \"bootconfig\";\n\t\t\t\treg = <0x00200000 0x00100000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@300000 {\n\t\t\t\tlabel = \"qsee\";\n\t\t\t\treg = <0x00300000 0x00100000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@400000 {\n\t\t\t\tlabel = \"qsee_alt\";\n\t\t\t\treg = <0x00400000 0x00100000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@500000 {\n\t\t\t\tlabel = \"cdt\";\n\t\t\t\treg = <0x00500000 0x00080000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@580000 {\n\t\t\t\tlabel = \"cdt_alt\";\n\t\t\t\treg = <0x00580000 0x00080000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@600000 {\n\t\t\t\tlabel = \"ddrparams\";\n\t\t\t\treg = <0x00600000 0x00080000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@700000 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x00700000 0x00200000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@900000 {\n\t\t\t\tlabel = \"u-boot-backup\";\n\t\t\t\treg = <0x00900000 0x00200000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@b00000 {\n\t\t\t\tlabel = \"ART\";\n\t\t\t\treg = <0x00b00000 0x00080000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@c00000 {\n\t\t\t\tlabel = \"ubi\";\n\t\t\t\treg = <0x00c00000 0x07000000>;\n\t\t\t\t/*\n\t\t\t\t * Do not try to allocate the remaining\n\t\t\t\t * 4 MiB to this ubi partition. It will\n\t\t\t\t * confuse the u-boot and it might not\n\t\t\t\t * find the kernel partition anymore.\n\t\t\t\t */\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pcie0 {\n\tstatus = \"okay\";\n\tperst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;\n\twake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>;\n\n\tbridge@0,0 {\n\t\treg = <0x00000000 0 0 0 0>;\n\t\t#address-cells = <3>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\twifi2: wifi@1,0 {\n\t\t\tcompatible = \"qcom,ath10k\";\n\t\t\tstatus = \"okay\";\n\t\t\treg = <0x00010000 0 0 0 0>;\n\t\t};\n\t};\n};\n\n&qpic_bam {\n\tstatus = \"okay\";\n};\n\n&tlmm {\n\t/*\n\t * GPIO43 should be 0/1 whenever the unit is\n\t * powered through PoE or AC-Adapter.\n\t * That said, playing with this seems to\n\t * reset the AP.\n\t */\n\n\tmdio_pins: mdio_pinmux {\n\t\tmux_1 {\n\t\t\tpins = \"gpio6\";\n\t\t\tfunction = \"mdio\";\n\t\t\tbias-pull-up;\n\t\t};\n\t\tmux_2 {\n\t\t\tpins = \"gpio7\";\n\t\t\tfunction = \"mdc\";\n\t\t\tbias-pull-up;\n\t\t};\n\t};\n\n\tserial_0_pins: serial_pinmux {\n\t\tmux {\n\t\t\tpins = \"gpio16\", \"gpio17\";\n\t\t\tfunction = \"blsp_uart0\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tserial_1_pins: serial1_pinmux {\n\t\tmux {\n\t\t\t/* We use the i2c-0 pins for serial_1 */\n\t\t\tpins = \"gpio8\", \"gpio9\";\n\t\t\tfunction = \"blsp_uart1\";\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\ti2c_0_pins: i2c_0_pinmux {\n\t\tpinmux {\n\t\t\tfunction = \"blsp_i2c0\";\n\t\t\tpins = \"gpio20\", \"gpio21\";\n\t\t};\n\t\tpinconf {\n\t\t\tpins = \"gpio20\", \"gpio21\";\n\t\t\tdrive-strength = <16>;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\ti2c_1_pins: i2c_1_pinmux {\n\t\tpinmux {\n\t\t\tfunction = \"blsp_i2c1\";\n\t\t\tpins = \"gpio34\", \"gpio35\";\n\t\t};\n\t\tpinconf {\n\t\t\tpins = \"gpio34\", \"gpio35\";\n\t\t\tdrive-strength = <16>;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tnand_pins: nand_pins {\n\t\t/*\n\t\t * There are 18 pins. 15 pins are common between LCD and NAND.\n\t\t * The QPIC controller arbitrates between LCD and NAND. Of the\n\t\t * remaining 4, 2 are for NAND and 2 are for LCD exclusively.\n\t\t *\n\t\t * The meraki source hints that the bluetooth module claims\n\t\t * pin 52 as well. But sadly, there's no data whenever this\n\t\t * is a NAND or LCD exclusive pin or not.\n\t\t */\n\n\t\tpullups {\n\t\t\tpins = \"gpio52\", \"gpio53\", \"gpio58\",\n\t\t\t\t\"gpio59\";\n\t\t\tfunction = \"qpic\";\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tpulldowns {\n\t\t\tpins = \"gpio54\", \"gpio55\", \"gpio56\",\n\t\t\t\t\"gpio57\", \"gpio60\", \"gpio61\",\n\t\t\t\t\"gpio62\", \"gpio63\", \"gpio64\",\n\t\t\t\t\"gpio65\", \"gpio66\", \"gpio67\",\n\t\t\t\t\"gpio68\", \"gpio69\";\n\t\t\tfunction = \"qpic\";\n\t\t\tbias-pull-down;\n\t\t};\n\t};\n};\n\n&wifi0 {\n\tstatus = \"okay\";\n\tqcom,ath10k-calibration-variant = \"Meraki-MR33\";\n};\n\n&wifi1 {\n\tstatus = \"okay\";\n\tqcom,ath10k-calibration-variant = \"Meraki-MR33\";\n};\n"
  },
  {
    "path": "target/linux/ipq40xx/files/drivers/net/ethernet/qualcomm/essedma/Makefile",
    "content": "#\n## Makefile for the Qualcomm Atheros ethernet edma driver\n#\n\n\nobj-$(CONFIG_ESSEDMA) += essedma.o\n\nessedma-objs := edma_axi.o edma.o edma_ethtool.o\n\n"
  },
  {
    "path": "target/linux/ipq40xx/files/drivers/net/ethernet/qualcomm/essedma/edma.c",
    "content": "/*\n * Copyright (c) 2014 - 2016, The Linux Foundation. All rights reserved.\n *\n * Permission to use, copy, modify, and/or distribute this software for\n * any purpose with or without fee is hereby granted, provided that the\n * above copyright notice and this permission notice appear in all copies.\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT\n * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n */\n\n#include <linux/platform_device.h>\n#include <linux/if_vlan.h>\n#include \"ess_edma.h\"\n#include \"edma.h\"\n\nextern struct net_device *edma_netdev[EDMA_MAX_PORTID_SUPPORTED];\nbool edma_stp_rstp;\nu16 edma_ath_eth_type;\n\n/* edma_skb_priority_offset()\n * \tget edma skb priority\n */\nstatic unsigned int edma_skb_priority_offset(struct sk_buff *skb)\n{\n\treturn (skb->priority >> 2) & 1;\n}\n\n/* edma_alloc_tx_ring()\n *\tAllocate Tx descriptors ring\n */\nstatic int edma_alloc_tx_ring(struct edma_common_info *edma_cinfo,\n\t\t\t      struct edma_tx_desc_ring *etdr)\n{\n\tstruct platform_device *pdev = edma_cinfo->pdev;\n\n\t/* Initialize ring */\n\tetdr->size = sizeof(struct edma_sw_desc) * etdr->count;\n\tetdr->sw_next_to_fill = 0;\n\tetdr->sw_next_to_clean = 0;\n\n\t/* Allocate SW descriptors */\n\tetdr->sw_desc = vzalloc(etdr->size);\n\tif (!etdr->sw_desc) {\n\t\tdev_err(&pdev->dev, \"buffer alloc of tx ring failed=%p\", etdr);\n\t\treturn -ENOMEM;\n\t}\n\n\t/* Allocate HW descriptors */\n\tetdr->hw_desc = dma_alloc_coherent(&pdev->dev, etdr->size, &etdr->dma,\n\t\t\t\t\t  GFP_KERNEL);\n\tif (!etdr->hw_desc) {\n\t\tdev_err(&pdev->dev, \"descriptor allocation for tx ring failed\");\n\t\tvfree(etdr->sw_desc);\n\t\treturn -ENOMEM;\n\t}\n\n\treturn 0;\n}\n\n/* edma_free_tx_ring()\n *\tFree tx rings allocated by edma_alloc_tx_rings\n */\nstatic void edma_free_tx_ring(struct edma_common_info *edma_cinfo,\n\t\t\t      struct edma_tx_desc_ring *etdr)\n{\n\tstruct platform_device *pdev = edma_cinfo->pdev;\n\n\tif (likely(etdr->dma))\n\t\tdma_free_coherent(&pdev->dev, etdr->size, etdr->hw_desc,\n\t\t\t\t etdr->dma);\n\n\tvfree(etdr->sw_desc);\n\tetdr->sw_desc = NULL;\n}\n\n/* edma_alloc_rx_ring()\n *\tallocate rx descriptor ring\n */\nstatic int edma_alloc_rx_ring(struct edma_common_info *edma_cinfo,\n\t\t\t     struct edma_rfd_desc_ring *erxd)\n{\n\tstruct platform_device *pdev = edma_cinfo->pdev;\n\n\terxd->size = sizeof(struct edma_sw_desc) * erxd->count;\n\terxd->sw_next_to_fill = 0;\n\terxd->sw_next_to_clean = 0;\n\n\t/* Allocate SW descriptors */\n\terxd->sw_desc = vzalloc(erxd->size);\n\tif (!erxd->sw_desc)\n\t\treturn -ENOMEM;\n\n\t/* Alloc HW descriptors */\n\terxd->hw_desc = dma_alloc_coherent(&pdev->dev, erxd->size, &erxd->dma,\n\t\t\tGFP_KERNEL);\n\tif (!erxd->hw_desc) {\n\t\tvfree(erxd->sw_desc);\n\t\treturn -ENOMEM;\n\t}\n\n\t/* Initialize pending_fill */\n\terxd->pending_fill = 0;\n\n\treturn 0;\n}\n\n/* edma_free_rx_ring()\n *\tFree rx ring allocated by alloc_rx_ring\n */\nstatic void edma_free_rx_ring(struct edma_common_info *edma_cinfo,\n\t\t\t     struct edma_rfd_desc_ring *rxdr)\n{\n\tstruct platform_device *pdev = edma_cinfo->pdev;\n\n\tif (likely(rxdr->dma))\n\t\tdma_free_coherent(&pdev->dev, rxdr->size, rxdr->hw_desc,\n\t\t\t\t rxdr->dma);\n\n\tvfree(rxdr->sw_desc);\n\trxdr->sw_desc = NULL;\n}\n\n/* edma_configure_tx()\n *\tConfigure transmission control data\n */\nstatic void edma_configure_tx(struct edma_common_info *edma_cinfo)\n{\n\tu32 txq_ctrl_data;\n\n\ttxq_ctrl_data = (EDMA_TPD_BURST << EDMA_TXQ_NUM_TPD_BURST_SHIFT);\n\ttxq_ctrl_data |= EDMA_TXQ_CTRL_TPD_BURST_EN;\n\ttxq_ctrl_data |= (EDMA_TXF_BURST << EDMA_TXQ_TXF_BURST_NUM_SHIFT);\n\tedma_write_reg(EDMA_REG_TXQ_CTRL, txq_ctrl_data);\n}\n\n\n/* edma_configure_rx()\n *\tconfigure reception control data\n */\nstatic void edma_configure_rx(struct edma_common_info *edma_cinfo)\n{\n\tstruct edma_hw *hw = &edma_cinfo->hw;\n\tu32 rss_type, rx_desc1, rxq_ctrl_data;\n\n\t/* Set RSS type */\n\trss_type = hw->rss_type;\n\tedma_write_reg(EDMA_REG_RSS_TYPE, rss_type);\n\n\t/* Set RFD burst number */\n\trx_desc1 = (EDMA_RFD_BURST << EDMA_RXQ_RFD_BURST_NUM_SHIFT);\n\n\t/* Set RFD prefetch threshold */\n\trx_desc1 |= (EDMA_RFD_THR << EDMA_RXQ_RFD_PF_THRESH_SHIFT);\n\n\t/* Set RFD in host ring low threshold to generte interrupt */\n\trx_desc1 |= (EDMA_RFD_LTHR << EDMA_RXQ_RFD_LOW_THRESH_SHIFT);\n\tedma_write_reg(EDMA_REG_RX_DESC1, rx_desc1);\n\n\t/* Set Rx FIFO threshold to start to DMA data to host */\n\trxq_ctrl_data = EDMA_FIFO_THRESH_128_BYTE;\n\n\t/* Set RX remove vlan bit */\n\trxq_ctrl_data |= EDMA_RXQ_CTRL_RMV_VLAN;\n\n\tedma_write_reg(EDMA_REG_RXQ_CTRL, rxq_ctrl_data);\n}\n\n/* edma_alloc_rx_buf()\n *\tdoes skb allocation for the received packets.\n */\nstatic int edma_alloc_rx_buf(struct edma_common_info\n\t\t\t     *edma_cinfo,\n\t\t\t     struct edma_rfd_desc_ring *erdr,\n\t\t\t     int cleaned_count, int queue_id)\n{\n\tstruct platform_device *pdev = edma_cinfo->pdev;\n\tstruct edma_rx_free_desc *rx_desc;\n\tstruct edma_sw_desc *sw_desc;\n\tstruct sk_buff *skb;\n\tunsigned int i;\n\tu16 prod_idx, length;\n\tu32 reg_data;\n\n\tif (cleaned_count > erdr->count)\n\t\tcleaned_count = erdr->count - 1;\n\n\ti = erdr->sw_next_to_fill;\n\n\twhile (cleaned_count) {\n\t\tsw_desc = &erdr->sw_desc[i];\n\t\tlength = edma_cinfo->rx_head_buffer_len;\n\n\t\tif (sw_desc->flags & EDMA_SW_DESC_FLAG_SKB_REUSE) {\n\t\t\tskb = sw_desc->skb;\n\n\t\t\t/* Clear REUSE Flag */\n\t\t\tsw_desc->flags &= ~EDMA_SW_DESC_FLAG_SKB_REUSE;\n\t\t} else {\n\t\t\t/* alloc skb */\n\t\t\tskb = netdev_alloc_skb_ip_align(edma_netdev[0], length);\n\t\t\tif (!skb) {\n\t\t\t\t/* Better luck next round */\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\n\t\tif (edma_cinfo->page_mode) {\n\t\t\tstruct page *pg = alloc_page(GFP_ATOMIC);\n\n\t\t\tif (!pg) {\n\t\t\t\tdev_kfree_skb_any(skb);\n\t\t\t\tbreak;\n\t\t\t}\n\n\t\t\tsw_desc->dma = dma_map_page(&pdev->dev, pg, 0,\n\t\t\t\t\t\t   edma_cinfo->rx_page_buffer_len,\n\t\t\t\t\t\t   DMA_FROM_DEVICE);\n\t\t\tif (dma_mapping_error(&pdev->dev,\n\t\t\t\t    sw_desc->dma)) {\n\t\t\t\t__free_page(pg);\n\t\t\t\tdev_kfree_skb_any(skb);\n\t\t\t\tbreak;\n\t\t\t}\n\n\t\t\tskb_fill_page_desc(skb, 0, pg, 0,\n\t\t\t\t\t   edma_cinfo->rx_page_buffer_len);\n\t\t\tsw_desc->flags = EDMA_SW_DESC_FLAG_SKB_FRAG;\n\t\t\tsw_desc->length = edma_cinfo->rx_page_buffer_len;\n\t\t} else {\n\t\t\tsw_desc->dma = dma_map_single(&pdev->dev, skb->data,\n\t\t\t\t\t\t     length, DMA_FROM_DEVICE);\n\t\t\tif (dma_mapping_error(&pdev->dev,\n\t\t\t   sw_desc->dma)) {\n\t\t\t\tdev_kfree_skb_any(skb);\n\t\t\t\tbreak;\n\t\t\t}\n\n\t\t\tsw_desc->flags = EDMA_SW_DESC_FLAG_SKB_HEAD;\n\t\t\tsw_desc->length = length;\n\t\t}\n\n\t\t/* Update the buffer info */\n\t\tsw_desc->skb = skb;\n\t\trx_desc = (&((struct edma_rx_free_desc *)(erdr->hw_desc))[i]);\n\t\trx_desc->buffer_addr = cpu_to_le64(sw_desc->dma);\n\t\tif (++i == erdr->count)\n\t\t\ti = 0;\n\t\tcleaned_count--;\n\t}\n\n\terdr->sw_next_to_fill = i;\n\n\tif (i == 0)\n\t\tprod_idx = erdr->count - 1;\n\telse\n\t\tprod_idx = i - 1;\n\n\t/* Update the producer index */\n\tedma_read_reg(EDMA_REG_RFD_IDX_Q(queue_id), &reg_data);\n\treg_data &= ~EDMA_RFD_PROD_IDX_BITS;\n\treg_data |= prod_idx;\n\tedma_write_reg(EDMA_REG_RFD_IDX_Q(queue_id), reg_data);\n\n\t/* If we couldn't allocate all the buffers\n\t * we increment the alloc failure counters\n\t */\n\tif (cleaned_count)\n\t\tedma_cinfo->edma_ethstats.rx_alloc_fail_ctr++;\n\n\treturn cleaned_count;\n}\n\n/* edma_init_desc()\n *\tupdate descriptor ring size, buffer and producer/consumer index\n */\nstatic void edma_init_desc(struct edma_common_info *edma_cinfo)\n{\n\tstruct edma_rfd_desc_ring *rfd_ring;\n\tstruct edma_tx_desc_ring *etdr;\n\tint i = 0, j = 0;\n\tu32 data = 0;\n\tu16 hw_cons_idx = 0;\n\n\t/* Set the base address of every TPD ring. */\n\tfor (i = 0; i < edma_cinfo->num_tx_queues; i++) {\n\t\tetdr = edma_cinfo->tpd_ring[i];\n\n\t\t/* Update descriptor ring base address */\n\t\tedma_write_reg(EDMA_REG_TPD_BASE_ADDR_Q(i), (u32)etdr->dma);\n\t\tedma_read_reg(EDMA_REG_TPD_IDX_Q(i), &data);\n\n\t\t/* Calculate hardware consumer index */\n\t\thw_cons_idx = (data >> EDMA_TPD_CONS_IDX_SHIFT) & 0xffff;\n\t\tetdr->sw_next_to_fill = hw_cons_idx;\n\t\tetdr->sw_next_to_clean = hw_cons_idx;\n\t\tdata &= ~(EDMA_TPD_PROD_IDX_MASK << EDMA_TPD_PROD_IDX_SHIFT);\n\t\tdata |= hw_cons_idx;\n\n\t\t/* update producer index */\n\t\tedma_write_reg(EDMA_REG_TPD_IDX_Q(i), data);\n\n\t\t/* update SW consumer index register */\n\t\tedma_write_reg(EDMA_REG_TX_SW_CONS_IDX_Q(i), hw_cons_idx);\n\n\t\t/* Set TPD ring size */\n\t\tedma_write_reg(EDMA_REG_TPD_RING_SIZE,\n\t\t\t       edma_cinfo->tx_ring_count &\n\t\t\t\t    EDMA_TPD_RING_SIZE_MASK);\n\t}\n\n\tfor (i = 0, j = 0; i < edma_cinfo->num_rx_queues; i++) {\n\t\trfd_ring = edma_cinfo->rfd_ring[j];\n\t\t/* Update Receive Free descriptor ring base address */\n\t\tedma_write_reg(EDMA_REG_RFD_BASE_ADDR_Q(j),\n\t\t\t(u32)(rfd_ring->dma));\n\t\tj += ((edma_cinfo->num_rx_queues == 4) ? 2 : 1);\n\t}\n\n\tdata = edma_cinfo->rx_head_buffer_len;\n\tif (edma_cinfo->page_mode)\n\t\tdata = edma_cinfo->rx_page_buffer_len;\n\n\tdata &= EDMA_RX_BUF_SIZE_MASK;\n\tdata <<= EDMA_RX_BUF_SIZE_SHIFT;\n\n\t/* Update RFD ring size and RX buffer size */\n\tdata |= (edma_cinfo->rx_ring_count & EDMA_RFD_RING_SIZE_MASK)\n\t\t<< EDMA_RFD_RING_SIZE_SHIFT;\n\n\tedma_write_reg(EDMA_REG_RX_DESC0, data);\n\n\t/* Disable TX FIFO low watermark and high watermark */\n\tedma_write_reg(EDMA_REG_TXF_WATER_MARK, 0);\n\n\t/* Load all of base address above */\n\tedma_read_reg(EDMA_REG_TX_SRAM_PART, &data);\n\tdata |= 1 << EDMA_LOAD_PTR_SHIFT;\n\tedma_write_reg(EDMA_REG_TX_SRAM_PART, data);\n}\n\n/* edma_receive_checksum\n *\tApi to check checksum on receive packets\n */\nstatic void edma_receive_checksum(struct edma_rx_return_desc *rd,\n\t\t\t\t\t\t struct sk_buff *skb)\n{\n\tskb_checksum_none_assert(skb);\n\n\t/* check the RRD IP/L4 checksum bit to see if\n\t * its set, which in turn indicates checksum\n\t * failure.\n\t */\n\tif (rd->rrd6 & EDMA_RRD_CSUM_FAIL_MASK)\n\t\treturn;\n\n\tskb->ip_summed = CHECKSUM_UNNECESSARY;\n}\n\n/* edma_clean_rfd()\n *\tclean up rx resourcers on error\n */\nstatic void edma_clean_rfd(struct edma_rfd_desc_ring *erdr, u16 index)\n{\n\tstruct edma_rx_free_desc *rx_desc;\n\tstruct edma_sw_desc *sw_desc;\n\n\trx_desc = (&((struct edma_rx_free_desc *)(erdr->hw_desc))[index]);\n\tsw_desc = &erdr->sw_desc[index];\n\tif (sw_desc->skb) {\n\t\tdev_kfree_skb_any(sw_desc->skb);\n\t\tsw_desc->skb = NULL;\n\t}\n\n\tmemset(rx_desc, 0, sizeof(struct edma_rx_free_desc));\n}\n\n/* edma_rx_complete_fraglist()\n *\tComplete Rx processing for fraglist skbs\n */\nstatic void edma_rx_complete_stp_rstp(struct sk_buff *skb, int port_id, struct edma_rx_return_desc *rd)\n{\n\tint i;\n\tu32 priority;\n\tu16 port_type;\n\tu8 mac_addr[EDMA_ETH_HDR_LEN];\n\n\tport_type = (rd->rrd1 >> EDMA_RRD_PORT_TYPE_SHIFT)\n\t\t                & EDMA_RRD_PORT_TYPE_MASK;\n\t/* if port type is 0x4, then only proceed with\n\t * other stp/rstp calculation\n\t */\n\tif (port_type == EDMA_RX_ATH_HDR_RSTP_PORT_TYPE) {\n\t\tu8 bpdu_mac[6] = {0x01, 0x80, 0xc2, 0x00, 0x00, 0x00};\n\n\t\t/* calculate the frame priority */\n\t\tpriority = (rd->rrd1 >> EDMA_RRD_PRIORITY_SHIFT)\n\t\t\t& EDMA_RRD_PRIORITY_MASK;\n\n\t\tfor (i = 0; i < EDMA_ETH_HDR_LEN; i++)\n\t\t\tmac_addr[i] = skb->data[i];\n\n\t\t/* Check if destination mac addr is bpdu addr */\n\t\tif (!memcmp(mac_addr, bpdu_mac, 6)) {\n\t\t\t/* destination mac address is BPDU\n\t\t\t * destination mac address, then add\n\t\t\t * atheros header to the packet.\n\t\t\t */\n\t\t\tu16 athr_hdr = (EDMA_RX_ATH_HDR_VERSION << EDMA_RX_ATH_HDR_VERSION_SHIFT) |\n\t\t\t\t(priority << EDMA_RX_ATH_HDR_PRIORITY_SHIFT) |\n\t\t\t\t(EDMA_RX_ATH_HDR_RSTP_PORT_TYPE << EDMA_RX_ATH_PORT_TYPE_SHIFT) | port_id;\n\t\t\tskb_push(skb, 4);\n\t\t\tmemcpy(skb->data, mac_addr, EDMA_ETH_HDR_LEN);\n\t\t\t*(uint16_t *)&skb->data[12] = htons(edma_ath_eth_type);\n\t\t\t*(uint16_t *)&skb->data[14] = htons(athr_hdr);\n\t\t}\n\t}\n}\n\n/*\n * edma_rx_complete_fraglist()\n *\tComplete Rx processing for fraglist skbs\n */\nstatic int edma_rx_complete_fraglist(struct sk_buff *skb, u16 num_rfds, u16 length, u32 sw_next_to_clean,\n\t\t\t\t\tu16 *cleaned_count, struct edma_rfd_desc_ring *erdr, struct edma_common_info *edma_cinfo)\n{\n\tstruct platform_device *pdev = edma_cinfo->pdev;\n\tstruct edma_hw *hw = &edma_cinfo->hw;\n\tstruct sk_buff *skb_temp;\n\tstruct edma_sw_desc *sw_desc;\n\tint i;\n\tu16 size_remaining;\n\n\tskb->data_len = 0;\n\tskb->tail += (hw->rx_head_buff_size - 16);\n\tskb->len = skb->truesize = length;\n\tsize_remaining = length - (hw->rx_head_buff_size - 16);\n\n\t/* clean-up all related sw_descs */\n\tfor (i = 1; i < num_rfds; i++) {\n\t\tstruct sk_buff *skb_prev;\n\t\tsw_desc = &erdr->sw_desc[sw_next_to_clean];\n\t\tskb_temp = sw_desc->skb;\n\n\t\tdma_unmap_single(&pdev->dev, sw_desc->dma,\n\t\t\tsw_desc->length, DMA_FROM_DEVICE);\n\n\t\tif (size_remaining < hw->rx_head_buff_size)\n\t\t\tskb_put(skb_temp, size_remaining);\n\t\telse\n\t\t\tskb_put(skb_temp, hw->rx_head_buff_size);\n\n\t\t/*\n\t\t * If we are processing the first rfd, we link\n\t\t * skb->frag_list to the skb corresponding to the\n\t\t * first RFD\n\t\t */\n\t\tif (i == 1)\n\t\t\tskb_shinfo(skb)->frag_list = skb_temp;\n\t\telse\n\t\t\tskb_prev->next = skb_temp;\n\t\tskb_prev = skb_temp;\n\t\tskb_temp->next = NULL;\n\n\t\tskb->data_len += skb_temp->len;\n\t\tsize_remaining -= skb_temp->len;\n\n\t\t/* Increment SW index */\n\t\tsw_next_to_clean = (sw_next_to_clean + 1) & (erdr->count - 1);\n\t\t(*cleaned_count)++;\n\t}\n\n\treturn sw_next_to_clean;\n}\n\n/* edma_rx_complete_paged()\n *\tComplete Rx processing for paged skbs\n */\nstatic int edma_rx_complete_paged(struct sk_buff *skb, u16 num_rfds, u16 length, u32 sw_next_to_clean,\n\t\t\t\t\tu16 *cleaned_count, struct edma_rfd_desc_ring *erdr, struct edma_common_info *edma_cinfo)\n{\n\tstruct platform_device *pdev = edma_cinfo->pdev;\n\tstruct sk_buff *skb_temp;\n\tstruct edma_sw_desc *sw_desc;\n\tint i;\n\tu16 size_remaining;\n\n\tskb_frag_t *frag = &skb_shinfo(skb)->frags[0];\n\n\t/* Setup skbuff fields */\n\tskb->len = length;\n\n\tif (likely(num_rfds <= 1)) {\n\t\tskb->data_len = length;\n\t\tskb->truesize += edma_cinfo->rx_page_buffer_len;\n\t\tskb_fill_page_desc(skb, 0, skb_frag_page(frag),\n\t\t\t\t16, length);\n\t} else {\n\t\tskb_frag_size_sub(frag, 16);\n\t\tskb->data_len = skb_frag_size(frag);\n\t\tskb->truesize += edma_cinfo->rx_page_buffer_len;\n\t\tsize_remaining = length - skb_frag_size(frag);\n\n\t\tskb_fill_page_desc(skb, 0, skb_frag_page(frag),\n\t\t\t\t16, skb_frag_size(frag));\n\n\t\t/* clean-up all related sw_descs */\n\t\tfor (i = 1; i < num_rfds; i++) {\n\t\t\tsw_desc = &erdr->sw_desc[sw_next_to_clean];\n\t\t\tskb_temp = sw_desc->skb;\n\t\t\tfrag = &skb_shinfo(skb_temp)->frags[0];\n\t\t\tdma_unmap_page(&pdev->dev, sw_desc->dma,\n\t\t\t\tsw_desc->length, DMA_FROM_DEVICE);\n\n\t\t\tif (size_remaining < edma_cinfo->rx_page_buffer_len)\n\t\t\t\tskb_frag_size_set(frag, size_remaining);\n\n\t\t\tskb_fill_page_desc(skb, i, skb_frag_page(frag),\n\t\t\t\t\t0, skb_frag_size(frag));\n\n\t\t\tskb_shinfo(skb_temp)->nr_frags = 0;\n\t\t\tdev_kfree_skb_any(skb_temp);\n\n\t\t\tskb->data_len += skb_frag_size(frag);\n\t\t\tskb->truesize += edma_cinfo->rx_page_buffer_len;\n\t\t\tsize_remaining -= skb_frag_size(frag);\n\n\t\t\t/* Increment SW index */\n\t\t\tsw_next_to_clean = (sw_next_to_clean + 1) & (erdr->count - 1);\n\t\t\t(*cleaned_count)++;\n\t\t}\n\t}\n\n\treturn sw_next_to_clean;\n}\n\n/*\n * edma_rx_complete()\n *\tMain api called from the poll function to process rx packets.\n */\nstatic u16 edma_rx_complete(struct edma_common_info *edma_cinfo,\n\t\t\t    int *work_done, int work_to_do, int queue_id,\n\t\t\t    struct napi_struct *napi)\n{\n\tstruct platform_device *pdev = edma_cinfo->pdev;\n\tstruct edma_rfd_desc_ring *erdr = edma_cinfo->rfd_ring[queue_id];\n\tstruct net_device *netdev;\n\tstruct edma_adapter *adapter;\n\tstruct edma_sw_desc *sw_desc;\n\tstruct sk_buff *skb;\n\tstruct edma_rx_return_desc *rd;\n\tu16 hash_type, rrd[8], cleaned_count = 0, length = 0, num_rfds = 1,\n\t    sw_next_to_clean, hw_next_to_clean = 0, vlan = 0, ret_count = 0;\n\tu32 data = 0;\n\tu8 *vaddr;\n\tint port_id, i, drop_count = 0;\n\tu32 priority;\n\tu16 count = erdr->count, rfd_avail;\n\tu8 queue_to_rxid[8] = {0, 0, 1, 1, 2, 2, 3, 3};\n\n\tcleaned_count = erdr->pending_fill;\n\tsw_next_to_clean = erdr->sw_next_to_clean;\n\n\tedma_read_reg(EDMA_REG_RFD_IDX_Q(queue_id), &data);\n\thw_next_to_clean = (data >> EDMA_RFD_CONS_IDX_SHIFT) &\n\t\t\t   EDMA_RFD_CONS_IDX_MASK;\n\n\tdo {\n\t\twhile (sw_next_to_clean != hw_next_to_clean) {\n\t\t\tif (!work_to_do)\n\t\t\t\tbreak;\n\n\t\t\tsw_desc = &erdr->sw_desc[sw_next_to_clean];\n\t\t\tskb = sw_desc->skb;\n\n\t\t\t/* Unmap the allocated buffer */\n\t\t\tif (likely(sw_desc->flags & EDMA_SW_DESC_FLAG_SKB_HEAD))\n\t\t\t\tdma_unmap_single(&pdev->dev, sw_desc->dma,\n\t\t\t\t\t        sw_desc->length, DMA_FROM_DEVICE);\n\t\t\telse\n\t\t\t\tdma_unmap_page(&pdev->dev, sw_desc->dma,\n\t\t\t\t\t      sw_desc->length, DMA_FROM_DEVICE);\n\n\t\t\t/* Get RRD */\n\t\t\tif (edma_cinfo->page_mode) {\n\t\t\t\tvaddr = kmap_atomic(skb_frag_page(&skb_shinfo(skb)->frags[0]));\n\t\t\t\tmemcpy((uint8_t *)&rrd[0], vaddr, 16);\n\t\t\t\trd = (struct edma_rx_return_desc *)rrd;\n\t\t\t\tkunmap_atomic(vaddr);\n\t\t\t} else {\n\t\t\t\trd = (struct edma_rx_return_desc *)skb->data;\n\t\t\t}\n\n\t\t\t/* Check if RRD is valid */\n\t\t\tif (!(rd->rrd7 & EDMA_RRD_DESC_VALID)) {\n\t\t\t\tedma_clean_rfd(erdr, sw_next_to_clean);\n\t\t\t\tsw_next_to_clean = (sw_next_to_clean + 1) &\n\t\t\t\t\t\t   (erdr->count - 1);\n\t\t\t\tcleaned_count++;\n\t\t\t\tcontinue;\n\t\t\t}\n\n\t\t\t/* Get the number of RFDs from RRD */\n\t\t\tnum_rfds = rd->rrd1 & EDMA_RRD_NUM_RFD_MASK;\n\n\t\t\t/* Get Rx port ID from switch */\n\t\t\tport_id = (rd->rrd1 >> EDMA_PORT_ID_SHIFT) & EDMA_PORT_ID_MASK;\n\t\t\tif ((!port_id) || (port_id > EDMA_MAX_PORTID_SUPPORTED)) {\n\t\t\t\tdev_err(&pdev->dev, \"Invalid RRD source port bit set\");\n\t\t\t\tfor (i = 0; i < num_rfds; i++) {\n\t\t\t\t\tedma_clean_rfd(erdr, sw_next_to_clean);\n\t\t\t\t\tsw_next_to_clean = (sw_next_to_clean + 1) & (erdr->count - 1);\n\t\t\t\t\tcleaned_count++;\n\t\t\t\t}\n\t\t\t\tcontinue;\n\t\t\t}\n\n\t\t\t/* check if we have a sink for the data we receive.\n\t\t\t * If the interface isn't setup, we have to drop the\n\t\t\t * incoming data for now.\n\t\t\t */\n\t\t\tnetdev = edma_cinfo->portid_netdev_lookup_tbl[port_id];\n\t\t\tif (!netdev) {\n\t\t\t\tedma_clean_rfd(erdr, sw_next_to_clean);\n\t\t\t\tsw_next_to_clean = (sw_next_to_clean + 1) &\n\t\t\t\t\t\t   (erdr->count - 1);\n\t\t\t\tcleaned_count++;\n\t\t\t\tcontinue;\n\t\t\t}\n\t\t\tadapter = netdev_priv(netdev);\n\n\t\t\t/* This code is added to handle a usecase where high\n\t\t\t * priority stream and a low priority stream are\n\t\t\t * received simultaneously on DUT. The problem occurs\n\t\t\t * if one of the  Rx rings is full and the corresponding\n\t\t\t * core is busy with other stuff. This causes ESS CPU\n\t\t\t * port to backpressure all incoming traffic including\n\t\t\t * high priority one. We monitor free descriptor count\n\t\t\t * on each CPU and whenever it reaches threshold (< 80),\n\t\t\t * we drop all low priority traffic and let only high\n\t\t\t * priotiy traffic pass through. We can hence avoid\n\t\t\t * ESS CPU port to send backpressure on high priroity\n\t\t\t * stream.\n\t\t\t */\n\t\t\tpriority = (rd->rrd1 >> EDMA_RRD_PRIORITY_SHIFT)\n\t\t\t\t& EDMA_RRD_PRIORITY_MASK;\n\t\t\tif (likely(!priority && !edma_cinfo->page_mode && (num_rfds <= 1))) {\n\t\t\t\trfd_avail = (count + sw_next_to_clean - hw_next_to_clean - 1) & (count - 1);\n\t\t\t\tif (rfd_avail < EDMA_RFD_AVAIL_THR) {\n\t\t\t\t\tsw_desc->flags = EDMA_SW_DESC_FLAG_SKB_REUSE;\n\t\t\t\t\tsw_next_to_clean = (sw_next_to_clean + 1) & (erdr->count - 1);\n\t\t\t\t\tadapter->stats.rx_dropped++;\n\t\t\t\t\tcleaned_count++;\n\t\t\t\t\tdrop_count++;\n\t\t\t\t\tif (drop_count == 3) {\n\t\t\t\t\t\twork_to_do--;\n\t\t\t\t\t\t(*work_done)++;\n\t\t\t\t\t\tdrop_count = 0;\n\t\t\t\t\t}\n\t\t\t\t\tif (cleaned_count >= EDMA_RX_BUFFER_WRITE) {\n\t\t\t\t\t\t/* If buffer clean count reaches 16, we replenish HW buffers. */\n\t\t\t\t\t\tret_count = edma_alloc_rx_buf(edma_cinfo, erdr, cleaned_count, queue_id);\n\t\t\t\t\t\tedma_write_reg(EDMA_REG_RX_SW_CONS_IDX_Q(queue_id),\n\t\t\t\t\t\t\t      sw_next_to_clean);\n\t\t\t\t\t\tcleaned_count = ret_count;\n\t\t\t\t\t\terdr->pending_fill = ret_count;\n\t\t\t\t\t}\n\t\t\t\t\tcontinue;\n\t\t\t\t}\n\t\t\t}\n\n\t\t\twork_to_do--;\n\t\t\t(*work_done)++;\n\n\t\t\t/* Increment SW index */\n\t\t\tsw_next_to_clean = (sw_next_to_clean + 1) &\n\t\t\t\t\t   (erdr->count - 1);\n\n\t\t\tcleaned_count++;\n\n\t\t\t/* Get the packet size and allocate buffer */\n\t\t\tlength = rd->rrd6 & EDMA_RRD_PKT_SIZE_MASK;\n\n\t\t\tif (edma_cinfo->page_mode) {\n\t\t\t\t/* paged skb */\n\t\t\t\tsw_next_to_clean = edma_rx_complete_paged(skb, num_rfds, length, sw_next_to_clean, &cleaned_count, erdr, edma_cinfo);\n\t\t\t\tif (!pskb_may_pull(skb, ETH_HLEN)) {\n\t\t\t\t\tdev_kfree_skb_any(skb);\n\t\t\t\t\tcontinue;\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\t/* single or fraglist skb */\n\n\t\t\t\t/* Addition of 16 bytes is required, as in the packet\n\t\t\t\t * first 16 bytes are rrd descriptors, so actual data\n\t\t\t\t * starts from an offset of 16.\n\t\t\t\t */\n\t\t\t\tskb_reserve(skb, 16);\n\t\t\t\tif (likely((num_rfds <= 1) || !edma_cinfo->fraglist_mode)) {\n\t\t\t\t\tskb_put(skb, length);\n\t\t\t\t} else {\n\t\t\t\t\tsw_next_to_clean = edma_rx_complete_fraglist(skb, num_rfds, length, sw_next_to_clean, &cleaned_count, erdr, edma_cinfo);\n\t\t\t\t}\n\t\t\t}\n\n\t\t\tif (edma_stp_rstp) {\n\t\t\t\tedma_rx_complete_stp_rstp(skb, port_id, rd);\n\t\t\t}\n\n\t\t\tskb->protocol = eth_type_trans(skb, netdev);\n\n\t\t\t/* Record Rx queue for RFS/RPS and fill flow hash from HW */\n\t\t\tskb_record_rx_queue(skb, queue_to_rxid[queue_id]);\n\t\t\tif (netdev->features & NETIF_F_RXHASH) {\n\t\t\t\thash_type = (rd->rrd5 >> EDMA_HASH_TYPE_SHIFT);\n\t\t\t\tif ((hash_type > EDMA_HASH_TYPE_START) && (hash_type < EDMA_HASH_TYPE_END))\n\t\t\t\t\tskb_set_hash(skb, rd->rrd2, PKT_HASH_TYPE_L4);\n\t\t\t}\n\n#ifdef CONFIG_NF_FLOW_COOKIE\n\t\t\tskb->flow_cookie = rd->rrd3 & EDMA_RRD_FLOW_COOKIE_MASK;\n#endif\n\t\t\tedma_receive_checksum(rd, skb);\n\n\t\t\t/* Process VLAN HW acceleration indication provided by HW */\n\t\t\tif (unlikely(adapter->default_vlan_tag != rd->rrd4)) {\n\t\t\t\tvlan = rd->rrd4;\n\t\t\t\tif (likely(rd->rrd7 & EDMA_RRD_CVLAN))\n\t\t\t\t\t__vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan);\n\t\t\t\telse if (rd->rrd1 & EDMA_RRD_SVLAN)\n\t\t\t\t\t__vlan_hwaccel_put_tag(skb, htons(ETH_P_8021AD), vlan);\n\t\t\t}\n\n\t\t\t/* Update rx statistics */\n\t\t\tadapter->stats.rx_packets++;\n\t\t\tadapter->stats.rx_bytes += length;\n\n\t\t\t/* Check if we reached refill threshold */\n\t\t\tif (cleaned_count >= EDMA_RX_BUFFER_WRITE) {\n\t\t\t\tret_count = edma_alloc_rx_buf(edma_cinfo, erdr, cleaned_count, queue_id);\n\t\t\t\tedma_write_reg(EDMA_REG_RX_SW_CONS_IDX_Q(queue_id),\n\t\t\t\t\t      sw_next_to_clean);\n\t\t\t\tcleaned_count = ret_count;\n\t\t\t\terdr->pending_fill = ret_count;\n\t\t\t}\n\n\t\t\t/* At this point skb should go to stack */\n\t\t\tnapi_gro_receive(napi, skb);\n\t\t}\n\n\t\t/* Check if we still have NAPI budget */\n\t\tif (!work_to_do)\n\t\t\tbreak;\n\n\t\t/* Read index once again since we still have NAPI budget */\n\t\tedma_read_reg(EDMA_REG_RFD_IDX_Q(queue_id), &data);\n\t\thw_next_to_clean = (data >> EDMA_RFD_CONS_IDX_SHIFT) &\n\t\t\tEDMA_RFD_CONS_IDX_MASK;\n\t} while (hw_next_to_clean != sw_next_to_clean);\n\n\terdr->sw_next_to_clean = sw_next_to_clean;\n\n\t/* Refill here in case refill threshold wasn't reached */\n\tif (likely(cleaned_count)) {\n\t\tret_count = edma_alloc_rx_buf(edma_cinfo, erdr, cleaned_count, queue_id);\n\t\terdr->pending_fill = ret_count;\n\t\tif (ret_count) {\n\t\t\tif (net_ratelimit())\n\t\t\t\tdev_dbg(&pdev->dev, \"Not all buffers was reallocated\");\n\t\t}\n\n\t\tedma_write_reg(EDMA_REG_RX_SW_CONS_IDX_Q(queue_id),\n\t\t\t      erdr->sw_next_to_clean);\n\t}\n\n\treturn erdr->pending_fill;\n}\n\n/* edma_delete_rfs_filter()\n *\tRemove RFS filter from switch\n */\nstatic int edma_delete_rfs_filter(struct edma_adapter *adapter,\n\t\t\t\t struct edma_rfs_filter_node *filter_node)\n{\n\tint res = -1;\n\n\tstruct flow_keys *keys = &filter_node->keys;\n\n\tif (likely(adapter->set_rfs_rule))\n\t\tres = (*adapter->set_rfs_rule)(adapter->netdev,\n\t\t\tflow_get_u32_src(keys), flow_get_u32_dst(keys),\n\t\t\tkeys->ports.src, keys->ports.dst,\n\t\t\tkeys->basic.ip_proto, filter_node->rq_id, 0);\n\n\treturn res;\n}\n\n/* edma_add_rfs_filter()\n *\tAdd RFS filter to switch\n */\nstatic int edma_add_rfs_filter(struct edma_adapter *adapter,\n\t\t\t       struct flow_keys *keys, u16 rq,\n\t\t\t       struct edma_rfs_filter_node *filter_node)\n{\n\tint res = -1;\n\n\tstruct flow_keys *dest_keys = &filter_node->keys;\n\n\tmemcpy(dest_keys, &filter_node->keys, sizeof(*dest_keys));\n/*\n\tdest_keys->control = keys->control;\n\tdest_keys->basic = keys->basic;\n\tdest_keys->addrs = keys->addrs;\n\tdest_keys->ports = keys->ports;\n\tdest_keys.ip_proto = keys->ip_proto;\n*/\n\t/* Call callback registered by ESS driver */\n\tif (likely(adapter->set_rfs_rule))\n\t\tres = (*adapter->set_rfs_rule)(adapter->netdev, flow_get_u32_src(keys),\n\t\t      flow_get_u32_dst(keys), keys->ports.src, keys->ports.dst,\n\t\t      keys->basic.ip_proto, rq, 1);\n\n\treturn res;\n}\n\n/* edma_rfs_key_search()\n *\tLook for existing RFS entry\n */\nstatic struct edma_rfs_filter_node *edma_rfs_key_search(struct hlist_head *h,\n\t\t\t\t\t\t       struct flow_keys *key)\n{\n\tstruct edma_rfs_filter_node *p;\n\n\thlist_for_each_entry(p, h, node)\n\t\tif (flow_get_u32_src(&p->keys) == flow_get_u32_src(key) &&\n\t\t    flow_get_u32_dst(&p->keys) == flow_get_u32_dst(key) &&\n\t\t    p->keys.ports.src == key->ports.src &&\n\t\t    p->keys.ports.dst == key->ports.dst &&\n\t\t    p->keys.basic.ip_proto == key->basic.ip_proto)\n\t\t\treturn p;\n\treturn NULL;\n}\n\n/* edma_initialise_rfs_flow_table()\n * \tInitialise EDMA RFS flow table\n */\nstatic void edma_initialise_rfs_flow_table(struct edma_adapter *adapter)\n{\n\tint i;\n\n\tspin_lock_init(&adapter->rfs.rfs_ftab_lock);\n\n\t/* Initialize EDMA flow hash table */\n\tfor (i = 0; i < EDMA_RFS_FLOW_ENTRIES; i++)\n\t\tINIT_HLIST_HEAD(&adapter->rfs.hlist_head[i]);\n\n\tadapter->rfs.max_num_filter = EDMA_RFS_FLOW_ENTRIES;\n\tadapter->rfs.filter_available = adapter->rfs.max_num_filter;\n\tadapter->rfs.hashtoclean = 0;\n\n\t/* Add timer to get periodic RFS updates from OS */\n\ttimer_setup(&adapter->rfs.expire_rfs, edma_flow_may_expire, 0);\n\tmod_timer(&adapter->rfs.expire_rfs, jiffies + HZ / 4);\n}\n\n/* edma_free_rfs_flow_table()\n * \tFree EDMA RFS flow table\n */\nstatic void edma_free_rfs_flow_table(struct edma_adapter *adapter)\n{\n\tint i;\n\n\t/* Remove sync timer */\n\tdel_timer_sync(&adapter->rfs.expire_rfs);\n\tspin_lock_bh(&adapter->rfs.rfs_ftab_lock);\n\n\t/* Free EDMA RFS table entries */\n\tadapter->rfs.filter_available = 0;\n\n\t/* Clean-up EDMA flow hash table */\n\tfor (i = 0; i < EDMA_RFS_FLOW_ENTRIES; i++) {\n\t\tstruct hlist_head *hhead;\n\t\tstruct hlist_node *tmp;\n\t\tstruct edma_rfs_filter_node *filter_node;\n\t\tint res;\n\n\t\thhead = &adapter->rfs.hlist_head[i];\n\t\thlist_for_each_entry_safe(filter_node, tmp, hhead, node) {\n\t\t\tres  = edma_delete_rfs_filter(adapter, filter_node);\n\t\t\tif (res < 0)\n\t\t\t\tdev_warn(&adapter->netdev->dev,\n\t\t\t\t\t\"EDMA going down but RFS entry %d not allowed to be flushed by Switch\",\n\t\t\t\t        filter_node->flow_id);\n\t\t\thlist_del(&filter_node->node);\n\t\t\tkfree(filter_node);\n\t\t}\n\t}\n\tspin_unlock_bh(&adapter->rfs.rfs_ftab_lock);\n}\n\n/* edma_tx_unmap_and_free()\n *\tclean TX buffer\n */\nstatic inline void edma_tx_unmap_and_free(struct platform_device *pdev,\n\t\t\t\t\t struct edma_sw_desc *sw_desc)\n{\n\tstruct sk_buff *skb = sw_desc->skb;\n\n\tif (likely((sw_desc->flags & EDMA_SW_DESC_FLAG_SKB_HEAD) ||\n\t\t\t(sw_desc->flags & EDMA_SW_DESC_FLAG_SKB_FRAGLIST)))\n\t\t/* unmap_single for skb head area */\n\t\tdma_unmap_single(&pdev->dev, sw_desc->dma,\n\t\t\t\tsw_desc->length, DMA_TO_DEVICE);\n\telse if (sw_desc->flags & EDMA_SW_DESC_FLAG_SKB_FRAG)\n\t\t/* unmap page for paged fragments */\n\t\tdma_unmap_page(&pdev->dev, sw_desc->dma,\n\t\t  \t      sw_desc->length, DMA_TO_DEVICE);\n\n\tif (likely(sw_desc->flags & EDMA_SW_DESC_FLAG_LAST))\n\t\tdev_kfree_skb_any(skb);\n\n\tsw_desc->flags = 0;\n}\n\n/* edma_tx_complete()\n *\tUsed to clean tx queues and update hardware and consumer index\n */\nstatic void edma_tx_complete(struct edma_common_info *edma_cinfo, int queue_id)\n{\n\tstruct edma_tx_desc_ring *etdr = edma_cinfo->tpd_ring[queue_id];\n\tstruct edma_sw_desc *sw_desc;\n\tstruct platform_device *pdev = edma_cinfo->pdev;\n\tint i;\n\n\tu16 sw_next_to_clean = etdr->sw_next_to_clean;\n\tu16 hw_next_to_clean;\n\tu32 data = 0;\n\n\tedma_read_reg(EDMA_REG_TPD_IDX_Q(queue_id), &data);\n\thw_next_to_clean = (data >> EDMA_TPD_CONS_IDX_SHIFT) & EDMA_TPD_CONS_IDX_MASK;\n\n\t/* clean the buffer here */\n\twhile (sw_next_to_clean != hw_next_to_clean) {\n\t\tsw_desc = &etdr->sw_desc[sw_next_to_clean];\n\t\tedma_tx_unmap_and_free(pdev, sw_desc);\n\t\tsw_next_to_clean = (sw_next_to_clean + 1) & (etdr->count - 1);\n\t}\n\n\tetdr->sw_next_to_clean = sw_next_to_clean;\n\n\t/* update the TPD consumer index register */\n\tedma_write_reg(EDMA_REG_TX_SW_CONS_IDX_Q(queue_id), sw_next_to_clean);\n\n\t/* Wake the queue if queue is stopped and netdev link is up */\n\tfor (i = 0; i < EDMA_MAX_NETDEV_PER_QUEUE && etdr->nq[i] ; i++) {\n\t\tif (netif_tx_queue_stopped(etdr->nq[i])) {\n\t\t\tif ((etdr->netdev[i]) && netif_carrier_ok(etdr->netdev[i]))\n\t\t\t\tnetif_tx_wake_queue(etdr->nq[i]);\n\t\t}\n\t}\n}\n\n/* edma_get_tx_buffer()\n *\tGet sw_desc corresponding to the TPD\n */\nstatic struct edma_sw_desc *edma_get_tx_buffer(struct edma_common_info *edma_cinfo,\n\t\t\t\t\t       struct edma_tx_desc *tpd, int queue_id)\n{\n\tstruct edma_tx_desc_ring *etdr = edma_cinfo->tpd_ring[queue_id];\n\treturn &etdr->sw_desc[tpd - (struct edma_tx_desc *)etdr->hw_desc];\n}\n\n/* edma_get_next_tpd()\n *\tReturn a TPD descriptor for transfer\n */\nstatic struct edma_tx_desc *edma_get_next_tpd(struct edma_common_info *edma_cinfo,\n\t\t\t\t\t     int queue_id)\n{\n\tstruct edma_tx_desc_ring *etdr = edma_cinfo->tpd_ring[queue_id];\n\tu16 sw_next_to_fill = etdr->sw_next_to_fill;\n\tstruct edma_tx_desc *tpd_desc =\n\t\t(&((struct edma_tx_desc *)(etdr->hw_desc))[sw_next_to_fill]);\n\n\tetdr->sw_next_to_fill = (etdr->sw_next_to_fill + 1) & (etdr->count - 1);\n\n\treturn tpd_desc;\n}\n\n/* edma_tpd_available()\n *\tCheck number of free TPDs\n */\nstatic inline u16 edma_tpd_available(struct edma_common_info *edma_cinfo,\n\t\t\t\t    int queue_id)\n{\n\tstruct edma_tx_desc_ring *etdr = edma_cinfo->tpd_ring[queue_id];\n\n\tu16 sw_next_to_fill;\n\tu16 sw_next_to_clean;\n\tu16 count = 0;\n\n\tsw_next_to_clean = etdr->sw_next_to_clean;\n\tsw_next_to_fill = etdr->sw_next_to_fill;\n\n\tif (likely(sw_next_to_clean <= sw_next_to_fill))\n\t\tcount = etdr->count;\n\n\treturn count + sw_next_to_clean - sw_next_to_fill - 1;\n}\n\n/* edma_tx_queue_get()\n *\tGet the starting number of  the queue\n */\nstatic inline int edma_tx_queue_get(struct edma_adapter *adapter,\n\t\t\t\t   struct sk_buff *skb, int txq_id)\n{\n\t/* skb->priority is used as an index to skb priority table\n\t * and based on packet priority, correspong queue is assigned.\n\t */\n\treturn adapter->tx_start_offset[txq_id] + edma_skb_priority_offset(skb);\n}\n\n/* edma_tx_update_hw_idx()\n *\tupdate the producer index for the ring transmitted\n */\nstatic void edma_tx_update_hw_idx(struct edma_common_info *edma_cinfo,\n\t\t\t         struct sk_buff *skb, int queue_id)\n{\n\tstruct edma_tx_desc_ring *etdr = edma_cinfo->tpd_ring[queue_id];\n\tu32 tpd_idx_data;\n\n\t/* Read and update the producer index */\n\tedma_read_reg(EDMA_REG_TPD_IDX_Q(queue_id), &tpd_idx_data);\n\ttpd_idx_data &= ~EDMA_TPD_PROD_IDX_BITS;\n\ttpd_idx_data |= (etdr->sw_next_to_fill & EDMA_TPD_PROD_IDX_MASK)\n\t\t<< EDMA_TPD_PROD_IDX_SHIFT;\n\n\tedma_write_reg(EDMA_REG_TPD_IDX_Q(queue_id), tpd_idx_data);\n}\n\n/* edma_rollback_tx()\n *\tFunction to retrieve tx resources in case of error\n */\nstatic void edma_rollback_tx(struct edma_adapter *adapter,\n\t\t\t    struct edma_tx_desc *start_tpd, int queue_id)\n{\n\tstruct edma_tx_desc_ring *etdr = adapter->edma_cinfo->tpd_ring[queue_id];\n\tstruct edma_sw_desc *sw_desc;\n\tstruct edma_tx_desc *tpd = NULL;\n\tu16 start_index, index;\n\n\tstart_index = start_tpd - (struct edma_tx_desc *)(etdr->hw_desc);\n\n\tindex = start_index;\n\twhile (index != etdr->sw_next_to_fill) {\n\t\ttpd = (&((struct edma_tx_desc *)(etdr->hw_desc))[index]);\n\t\tsw_desc = &etdr->sw_desc[index];\n\t\tedma_tx_unmap_and_free(adapter->pdev, sw_desc);\n\t\tmemset(tpd, 0, sizeof(struct edma_tx_desc));\n\t\tif (++index == etdr->count)\n\t\t\tindex = 0;\n\t}\n\tetdr->sw_next_to_fill = start_index;\n}\n\n/* edma_tx_map_and_fill()\n *\tgets called from edma_xmit_frame\n *\n * This is where the dma of the buffer to be transmitted\n * gets mapped\n */\nstatic int edma_tx_map_and_fill(struct edma_common_info *edma_cinfo,\n\t\t\t       struct edma_adapter *adapter, struct sk_buff *skb, int queue_id,\n\t\t\t       unsigned int flags_transmit, u16 from_cpu, u16 dp_bitmap,\n\t\t\t       bool packet_is_rstp, int nr_frags)\n{\n\tstruct edma_sw_desc *sw_desc = NULL;\n\tstruct platform_device *pdev = edma_cinfo->pdev;\n\tstruct edma_tx_desc *tpd = NULL, *start_tpd = NULL;\n\tstruct sk_buff *iter_skb;\n\tint i = 0;\n\tu32 word1 = 0, word3 = 0, lso_word1 = 0, svlan_tag = 0;\n\tu16 buf_len, lso_desc_len = 0;\n\n\t/* It should either be a nr_frags skb or fraglist skb but not both */\n\tBUG_ON(nr_frags && skb_has_frag_list(skb));\n\n\tif (skb_is_gso(skb)) {\n\t\t/* TODO: What additional checks need to be performed here */\n\t\tif (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV4) {\n\t\t\tlso_word1 |= EDMA_TPD_IPV4_EN;\n\t\t\tip_hdr(skb)->check = 0;\n\t\t\ttcp_hdr(skb)->check = ~csum_tcpudp_magic(ip_hdr(skb)->saddr,\n\t\t\t\tip_hdr(skb)->daddr, 0, IPPROTO_TCP, 0);\n\t\t} else if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6) {\n\t\t\tlso_word1 |= EDMA_TPD_LSO_V2_EN;\n\t\t\tipv6_hdr(skb)->payload_len = 0;\n\t\t\ttcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,\n\t\t\t\t&ipv6_hdr(skb)->daddr, 0, IPPROTO_TCP, 0);\n\t\t} else\n\t\t\treturn -EINVAL;\n\n\t\tlso_word1 |= EDMA_TPD_LSO_EN | ((skb_shinfo(skb)->gso_size & EDMA_TPD_MSS_MASK) << EDMA_TPD_MSS_SHIFT) |\n\t\t\t\t(skb_transport_offset(skb) << EDMA_TPD_HDR_SHIFT);\n\t} else if (flags_transmit & EDMA_HW_CHECKSUM) {\n\t\t\tu8 css, cso;\n\t\t\tcso = skb_checksum_start_offset(skb);\n\t\t\tcss = cso  + skb->csum_offset;\n\n\t\t\tword1 |= (EDMA_TPD_CUSTOM_CSUM_EN);\n\t\t\tword1 |= (cso >> 1) << EDMA_TPD_HDR_SHIFT;\n\t\t\tword1 |= ((css >> 1) << EDMA_TPD_CUSTOM_CSUM_SHIFT);\n\t}\n\n\tif (skb->protocol == htons(ETH_P_PPP_SES))\n\t\tword1 |= EDMA_TPD_PPPOE_EN;\n\n\tif (flags_transmit & EDMA_VLAN_TX_TAG_INSERT_FLAG) {\n\t\tswitch(skb->vlan_proto) {\n\t\tcase htons(ETH_P_8021Q):\n\t\t\tword3 |= (1 << EDMA_TX_INS_CVLAN);\n\t\t\tword3 |= skb_vlan_tag_get(skb) << EDMA_TX_CVLAN_TAG_SHIFT;\n\t\t\tbreak;\n\t\tcase htons(ETH_P_8021AD):\n\t\t\tword1 |= (1 << EDMA_TX_INS_SVLAN);\n\t\t\tsvlan_tag = skb_vlan_tag_get(skb) << EDMA_TX_SVLAN_TAG_SHIFT;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tdev_err(&pdev->dev, \"no ctag or stag present\\n\");\n\t\t\tgoto vlan_tag_error;\n\t\t}\n\t} else if (flags_transmit & EDMA_VLAN_TX_TAG_INSERT_DEFAULT_FLAG) {\n\t\tword3 |= (1 << EDMA_TX_INS_CVLAN);\n\t\tword3 |= (adapter->default_vlan_tag) << EDMA_TX_CVLAN_TAG_SHIFT;\n\t}\n\n\tif (packet_is_rstp) {\n\t\tword3 |= dp_bitmap << EDMA_TPD_PORT_BITMAP_SHIFT;\n\t\tword3 |= from_cpu << EDMA_TPD_FROM_CPU_SHIFT;\n\t} else {\n\t\tword3 |= adapter->dp_bitmap << EDMA_TPD_PORT_BITMAP_SHIFT;\n\t}\n\n\tbuf_len = skb_headlen(skb);\n\n\tif (lso_word1) {\n\t\tif (lso_word1 & EDMA_TPD_LSO_V2_EN) {\n\n\t\t\t/* IPv6 LSOv2 descriptor */\n\t\t\tstart_tpd = tpd = edma_get_next_tpd(edma_cinfo, queue_id);\n\t\t\tsw_desc = edma_get_tx_buffer(edma_cinfo, tpd, queue_id);\n\t\t\tsw_desc->flags |= EDMA_SW_DESC_FLAG_SKB_NONE;\n\n\t\t\t/* LSOv2 descriptor overrides addr field to pass length */\n\t\t\ttpd->addr = cpu_to_le16(skb->len);\n\t\t\ttpd->svlan_tag = svlan_tag;\n\t\t\ttpd->word1 = word1 | lso_word1;\n\t\t\ttpd->word3 = word3;\n\t\t}\n\n\t\ttpd = edma_get_next_tpd(edma_cinfo, queue_id);\n\t\tif (!start_tpd)\n\t\t\tstart_tpd = tpd;\n\t\tsw_desc = edma_get_tx_buffer(edma_cinfo, tpd, queue_id);\n\n\t\t/* The last buffer info contain the skb address,\n\t\t * so skb will be freed after unmap\n\t\t */\n\t\tsw_desc->length = lso_desc_len;\n\t\tsw_desc->flags |= EDMA_SW_DESC_FLAG_SKB_HEAD;\n\n\t\tsw_desc->dma = dma_map_single(&adapter->pdev->dev,\n\t\t\t\t\tskb->data, buf_len, DMA_TO_DEVICE);\n\t\tif (dma_mapping_error(&pdev->dev, sw_desc->dma))\n\t\t\tgoto dma_error;\n\n\t\ttpd->addr = cpu_to_le32(sw_desc->dma);\n\t\ttpd->len  = cpu_to_le16(buf_len);\n\n\t\ttpd->svlan_tag = svlan_tag;\n\t\ttpd->word1 = word1 | lso_word1;\n\t\ttpd->word3 = word3;\n\n\t\t/* The last buffer info contain the skb address,\n\t\t * so it will be freed after unmap\n\t\t */\n\t\tsw_desc->length = lso_desc_len;\n\t\tsw_desc->flags |= EDMA_SW_DESC_FLAG_SKB_HEAD;\n\n\t\tbuf_len = 0;\n\t}\n\n\tif (likely(buf_len)) {\n\n\t\t/* TODO Do not dequeue descriptor if there is a potential error */\n\t\ttpd = edma_get_next_tpd(edma_cinfo, queue_id);\n\n\t\tif (!start_tpd)\n\t\t\tstart_tpd = tpd;\n\n\t\tsw_desc = edma_get_tx_buffer(edma_cinfo, tpd, queue_id);\n\n\t\t/* The last buffer info contain the skb address,\n\t\t * so it will be free after unmap\n\t\t */\n\t\tsw_desc->length = buf_len;\n\t\tsw_desc->flags |= EDMA_SW_DESC_FLAG_SKB_HEAD;\n\t\tsw_desc->dma = dma_map_single(&adapter->pdev->dev,\n\t\t\tskb->data, buf_len, DMA_TO_DEVICE);\n\t\tif (dma_mapping_error(&pdev->dev, sw_desc->dma))\n\t\t\tgoto dma_error;\n\n\t\ttpd->addr = cpu_to_le32(sw_desc->dma);\n\t\ttpd->len  = cpu_to_le16(buf_len);\n\n\t\ttpd->svlan_tag = svlan_tag;\n\t\ttpd->word1 = word1 | lso_word1;\n\t\ttpd->word3 = word3;\n\t}\n\n\t/* Walk through all paged fragments */\n\twhile (nr_frags--) {\n\t\tskb_frag_t *frag = &skb_shinfo(skb)->frags[i];\n\t\tbuf_len = skb_frag_size(frag);\n\t\ttpd = edma_get_next_tpd(edma_cinfo, queue_id);\n\t\tsw_desc = edma_get_tx_buffer(edma_cinfo, tpd, queue_id);\n\t\tsw_desc->length = buf_len;\n\t\tsw_desc->flags |= EDMA_SW_DESC_FLAG_SKB_FRAG;\n\n\t\tsw_desc->dma = skb_frag_dma_map(&pdev->dev, frag, 0, buf_len, DMA_TO_DEVICE);\n\n\t\tif (dma_mapping_error(NULL, sw_desc->dma))\n\t\t\tgoto dma_error;\n\n\t\ttpd->addr = cpu_to_le32(sw_desc->dma);\n\t\ttpd->len  = cpu_to_le16(buf_len);\n\n\t\ttpd->svlan_tag = svlan_tag;\n\t\ttpd->word1 = word1 | lso_word1;\n\t\ttpd->word3 = word3;\n\t\ti++;\n\t}\n\n\t/* Walk through all fraglist skbs */\n\tskb_walk_frags(skb, iter_skb) {\n\t\tbuf_len = iter_skb->len;\n\t\ttpd = edma_get_next_tpd(edma_cinfo, queue_id);\n\t\tsw_desc = edma_get_tx_buffer(edma_cinfo, tpd, queue_id);\n\t\tsw_desc->length = buf_len;\n\t\tsw_desc->dma =  dma_map_single(&adapter->pdev->dev,\n\t\t\t\titer_skb->data, buf_len, DMA_TO_DEVICE);\n\n\t\tif (dma_mapping_error(NULL, sw_desc->dma))\n\t\t\tgoto dma_error;\n\n\t\ttpd->addr = cpu_to_le32(sw_desc->dma);\n\t\ttpd->len  = cpu_to_le16(buf_len);\n\t\ttpd->svlan_tag = svlan_tag;\n\t\ttpd->word1 = word1 | lso_word1;\n\t\ttpd->word3 = word3;\n\t\tsw_desc->flags |= EDMA_SW_DESC_FLAG_SKB_FRAGLIST;\n\t}\n\n\tif (tpd)\n\t\ttpd->word1 |= 1 << EDMA_TPD_EOP_SHIFT;\n\n\tsw_desc->skb = skb;\n\tsw_desc->flags |= EDMA_SW_DESC_FLAG_LAST;\n\n\treturn 0;\n\ndma_error:\n\tedma_rollback_tx(adapter, start_tpd, queue_id);\n\tdev_err(&pdev->dev, \"TX DMA map failed\\n\");\nvlan_tag_error:\n\treturn -ENOMEM;\n}\n\n/* edma_check_link()\n *\tcheck Link status\n */\nstatic int edma_check_link(struct edma_adapter *adapter)\n{\n\tstruct phy_device *phydev = adapter->phydev;\n\n\tif (!(adapter->poll_required))\n\t\treturn __EDMA_LINKUP;\n\n\tif (phydev->link)\n\t\treturn __EDMA_LINKUP;\n\n\treturn __EDMA_LINKDOWN;\n}\n\n/* edma_adjust_link()\n *\tcheck for edma link status\n */\nvoid edma_adjust_link(struct net_device *netdev)\n{\n\tint status;\n\tstruct edma_adapter *adapter = netdev_priv(netdev);\n\tstruct phy_device *phydev = adapter->phydev;\n\n\tif (!test_bit(__EDMA_UP, &adapter->state_flags))\n\t\treturn;\n\n\tstatus = edma_check_link(adapter);\n\n\tif (status == __EDMA_LINKUP && adapter->link_state == __EDMA_LINKDOWN) {\n\t\tphy_print_status(phydev);\n\t\tadapter->link_state = __EDMA_LINKUP;\n\t\tif (adapter->edma_cinfo->is_single_phy) {\n\t\t\tess_set_port_status_speed(adapter->edma_cinfo, phydev,\n\t\t\t\t\t\t  ffs(adapter->dp_bitmap) - 1);\n\t\t}\n\t\tnetif_carrier_on(netdev);\n\t\tif (netif_running(netdev))\n\t\t\tnetif_tx_wake_all_queues(netdev);\n\t} else if (status == __EDMA_LINKDOWN && adapter->link_state == __EDMA_LINKUP) {\n\t\tphy_print_status(phydev);\n\t\tadapter->link_state = __EDMA_LINKDOWN;\n\t\tnetif_carrier_off(netdev);\n\t\tnetif_tx_stop_all_queues(netdev);\n\t}\n}\n\n/* edma_get_stats()\n *\tStatistics api used to retreive the tx/rx statistics\n */\nstruct net_device_stats *edma_get_stats(struct net_device *netdev)\n{\n\tstruct edma_adapter *adapter = netdev_priv(netdev);\n\n\treturn &adapter->stats;\n}\n\n/* edma_xmit()\n *\tMain api to be called by the core for packet transmission\n */\nnetdev_tx_t edma_xmit(struct sk_buff *skb,\n\t\t     struct net_device *net_dev)\n{\n\tstruct edma_adapter *adapter = netdev_priv(net_dev);\n\tstruct edma_common_info *edma_cinfo = adapter->edma_cinfo;\n\tstruct edma_tx_desc_ring *etdr;\n\tu16 from_cpu, dp_bitmap, txq_id;\n\tint ret, nr_frags = 0, num_tpds_needed = 1, queue_id;\n\tunsigned int flags_transmit = 0;\n\tbool packet_is_rstp = false;\n\tstruct netdev_queue *nq = NULL;\n\n\tif (skb_shinfo(skb)->nr_frags) {\n\t\tnr_frags = skb_shinfo(skb)->nr_frags;\n\t\tnum_tpds_needed += nr_frags;\n\t} else if (skb_has_frag_list(skb)) {\n\t\tstruct sk_buff *iter_skb;\n\n\t\tskb_walk_frags(skb, iter_skb)\n\t\t\tnum_tpds_needed++;\n\t}\n\n\tif (num_tpds_needed > EDMA_MAX_SKB_FRAGS) {\n\t\tdev_err(&net_dev->dev,\n\t\t\t\"skb received with fragments %d which is more than %lu\",\n\t\t\tnum_tpds_needed, EDMA_MAX_SKB_FRAGS);\n\t\tdev_kfree_skb_any(skb);\n\t\tadapter->stats.tx_errors++;\n\t\treturn NETDEV_TX_OK;\n\t}\n\n\tif (edma_stp_rstp) {\n\t\tu16 ath_hdr, ath_eth_type;\n\t\tu8 mac_addr[EDMA_ETH_HDR_LEN];\n\t\tath_eth_type = ntohs(*(uint16_t *)&skb->data[12]);\n\t\tif (ath_eth_type == edma_ath_eth_type) {\n\t\t\tpacket_is_rstp = true;\n\t\t\tath_hdr = htons(*(uint16_t *)&skb->data[14]);\n\t\t\tdp_bitmap = ath_hdr & EDMA_TX_ATH_HDR_PORT_BITMAP_MASK;\n\t\t\tfrom_cpu = (ath_hdr & EDMA_TX_ATH_HDR_FROM_CPU_MASK) >> EDMA_TX_ATH_HDR_FROM_CPU_SHIFT;\n\t\t\tmemcpy(mac_addr, skb->data, EDMA_ETH_HDR_LEN);\n\n\t\t\tskb_pull(skb, 4);\n\n\t\t\tmemcpy(skb->data, mac_addr, EDMA_ETH_HDR_LEN);\n\t\t}\n\t}\n\n\t/* this will be one of the 4 TX queues exposed to linux kernel */\n\ttxq_id = skb_get_queue_mapping(skb);\n\tqueue_id = edma_tx_queue_get(adapter, skb, txq_id);\n\tetdr = edma_cinfo->tpd_ring[queue_id];\n\tnq = netdev_get_tx_queue(net_dev, txq_id);\n\n\tlocal_bh_disable();\n\t/* Tx is not handled in bottom half context. Hence, we need to protect\n\t * Tx from tasks and bottom half\n\t */\n\n\tif (num_tpds_needed > edma_tpd_available(edma_cinfo, queue_id)) {\n\t\t/* not enough descriptor, just stop queue */\n\t\tnetif_tx_stop_queue(nq);\n\t\tlocal_bh_enable();\n\t\tdev_dbg(&net_dev->dev, \"Not enough descriptors available\");\n\t\tedma_cinfo->edma_ethstats.tx_desc_error++;\n\t\treturn NETDEV_TX_BUSY;\n\t}\n\n\t/* Check and mark VLAN tag offload */\n\tif (unlikely(skb_vlan_tag_present(skb)))\n\t\tflags_transmit |= EDMA_VLAN_TX_TAG_INSERT_FLAG;\n\telse if (!adapter->edma_cinfo->is_single_phy && adapter->default_vlan_tag)\n\t\tflags_transmit |= EDMA_VLAN_TX_TAG_INSERT_DEFAULT_FLAG;\n\n\t/* Check and mark checksum offload */\n\tif (likely(skb->ip_summed == CHECKSUM_PARTIAL))\n\t\tflags_transmit |= EDMA_HW_CHECKSUM;\n\n\t/* Map and fill descriptor for Tx */\n\tret = edma_tx_map_and_fill(edma_cinfo, adapter, skb, queue_id,\n\t\tflags_transmit, from_cpu, dp_bitmap, packet_is_rstp, nr_frags);\n\tif (ret) {\n\t\tdev_kfree_skb_any(skb);\n\t\tadapter->stats.tx_errors++;\n\t\tgoto netdev_okay;\n\t}\n\n\t/* Update SW producer index */\n\tedma_tx_update_hw_idx(edma_cinfo, skb, queue_id);\n\n\t/* update tx statistics */\n\tadapter->stats.tx_packets++;\n\tadapter->stats.tx_bytes += skb->len;\n\nnetdev_okay:\n\tlocal_bh_enable();\n\treturn NETDEV_TX_OK;\n}\n\n/*\n * edma_flow_may_expire()\n * \tTimer function called periodically to delete the node\n */\nvoid edma_flow_may_expire(struct timer_list *t)\n{\n\tstruct edma_rfs_flow_table *table = from_timer(table, t, expire_rfs);\n\tstruct edma_adapter *adapter =\n\t\tcontainer_of(table, typeof(*adapter), rfs);\n\tint j;\n\n\tspin_lock_bh(&adapter->rfs.rfs_ftab_lock);\n\tfor (j = 0; j < EDMA_RFS_EXPIRE_COUNT_PER_CALL; j++) {\n\t\tstruct hlist_head *hhead;\n\t\tstruct hlist_node *tmp;\n\t\tstruct edma_rfs_filter_node *n;\n\t\tbool res;\n\n\t\thhead = &adapter->rfs.hlist_head[adapter->rfs.hashtoclean++];\n\t\thlist_for_each_entry_safe(n, tmp, hhead, node) {\n\t\t\tres = rps_may_expire_flow(adapter->netdev, n->rq_id,\n\t\t\t\t\tn->flow_id, n->filter_id);\n\t\t\tif (res) {\n\t\t\t\tint ret;\n\t\t\t\tret = edma_delete_rfs_filter(adapter, n);\n\t\t\t\tif (ret < 0)\n\t\t\t\t\tdev_dbg(&adapter->netdev->dev,\n\t\t\t\t\t\t\t\"RFS entry %d not allowed to be flushed by Switch\",\n\t\t\t\t\t\t\tn->flow_id);\n\t\t\t\telse {\n\t\t\t\t\thlist_del(&n->node);\n\t\t\t\t\tkfree(n);\n\t\t\t\t\tadapter->rfs.filter_available++;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n\n\tadapter->rfs.hashtoclean = adapter->rfs.hashtoclean & (EDMA_RFS_FLOW_ENTRIES - 1);\n\tspin_unlock_bh(&adapter->rfs.rfs_ftab_lock);\n\tmod_timer(&adapter->rfs.expire_rfs, jiffies + HZ / 4);\n}\n\n/* edma_rx_flow_steer()\n *\tCalled by core to to steer the flow to CPU\n */\nint edma_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,\n\t\t       u16 rxq, u32 flow_id)\n{\n\tstruct flow_keys keys;\n\tstruct edma_rfs_filter_node *filter_node;\n\tstruct edma_adapter *adapter = netdev_priv(dev);\n\tu16 hash_tblid;\n\tint res;\n\n\tif (skb->protocol == htons(ETH_P_IPV6)) {\n\t\tdev_err(&adapter->pdev->dev, \"IPv6 not supported\\n\");\n\t\tres = -EINVAL;\n\t\tgoto no_protocol_err;\n\t}\n\n\t/* Dissect flow parameters\n\t * We only support IPv4 + TCP/UDP\n\t */\n\tres = skb_flow_dissect_flow_keys(skb, &keys, 0);\n\tif (!((keys.basic.ip_proto == IPPROTO_TCP) || (keys.basic.ip_proto == IPPROTO_UDP))) {\n\t\tres = -EPROTONOSUPPORT;\n\t\tgoto no_protocol_err;\n\t}\n\n\t/* Check if table entry exists */\n\thash_tblid = skb_get_hash_raw(skb) & EDMA_RFS_FLOW_ENTRIES_MASK;\n\n\tspin_lock_bh(&adapter->rfs.rfs_ftab_lock);\n\tfilter_node = edma_rfs_key_search(&adapter->rfs.hlist_head[hash_tblid], &keys);\n\n\tif (filter_node) {\n\t\tif (rxq == filter_node->rq_id) {\n\t\t\tres = -EEXIST;\n\t\t\tgoto out;\n\t\t} else {\n\t\t\tres = edma_delete_rfs_filter(adapter, filter_node);\n\t\t\tif (res < 0)\n\t\t\t\tdev_warn(&adapter->netdev->dev,\n\t\t\t\t\t\t\"Cannot steer flow %d to different queue\",\n\t\t\t\t\t\tfilter_node->flow_id);\n\t\t\telse {\n\t\t\t\tadapter->rfs.filter_available++;\n\t\t\t\tres = edma_add_rfs_filter(adapter, &keys, rxq, filter_node);\n\t\t\t\tif (res < 0) {\n\t\t\t\t\tdev_warn(&adapter->netdev->dev,\n\t\t\t\t\t\t\t\"Cannot steer flow %d to different queue\",\n\t\t\t\t\t\t\tfilter_node->flow_id);\n\t\t\t\t} else {\n\t\t\t\t\tadapter->rfs.filter_available--;\n\t\t\t\t\tfilter_node->rq_id = rxq;\n\t\t\t\t\tfilter_node->filter_id = res;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t} else {\n\t\tif (adapter->rfs.filter_available == 0) {\n\t\t\tres = -EBUSY;\n\t\t\tgoto out;\n\t\t}\n\n\t\tfilter_node = kmalloc(sizeof(*filter_node), GFP_ATOMIC);\n\t\tif (!filter_node) {\n\t\t\tres = -ENOMEM;\n\t\t\tgoto out;\n\t\t}\n\n\t\tres = edma_add_rfs_filter(adapter, &keys, rxq, filter_node);\n\t\tif (res < 0) {\n\t\t\tkfree(filter_node);\n\t\t\tgoto out;\n\t\t}\n\n\t\tadapter->rfs.filter_available--;\n\t\tfilter_node->rq_id = rxq;\n\t\tfilter_node->filter_id = res;\n\t\tfilter_node->flow_id = flow_id;\n\t\tfilter_node->keys = keys;\n\t\tINIT_HLIST_NODE(&filter_node->node);\n\t\thlist_add_head(&filter_node->node, &adapter->rfs.hlist_head[hash_tblid]);\n\t}\n\nout:\n\tspin_unlock_bh(&adapter->rfs.rfs_ftab_lock);\nno_protocol_err:\n\treturn res;\n}\n\n/* edma_register_rfs_filter()\n *\tAdd RFS filter callback\n */\nint edma_register_rfs_filter(struct net_device *netdev,\n\t\t\t    set_rfs_filter_callback_t set_filter)\n{\n\tstruct edma_adapter *adapter = netdev_priv(netdev);\n\n\tspin_lock_bh(&adapter->rfs.rfs_ftab_lock);\n\n\tif (adapter->set_rfs_rule) {\n\t\tspin_unlock_bh(&adapter->rfs.rfs_ftab_lock);\n\t\treturn -1;\n\t}\n\n\tadapter->set_rfs_rule = set_filter;\n\tspin_unlock_bh(&adapter->rfs.rfs_ftab_lock);\n\n\treturn 0;\n}\n\n/* edma_alloc_tx_rings()\n *\tAllocate rx rings\n */\nint edma_alloc_tx_rings(struct edma_common_info *edma_cinfo)\n{\n\tstruct platform_device *pdev = edma_cinfo->pdev;\n\tint i, err = 0;\n\n\tfor (i = 0; i < edma_cinfo->num_tx_queues; i++) {\n\t\terr = edma_alloc_tx_ring(edma_cinfo, edma_cinfo->tpd_ring[i]);\n\t\tif (err) {\n\t\t\tdev_err(&pdev->dev, \"Tx Queue alloc %u failed\\n\", i);\n\t\t\treturn err;\n\t\t}\n\t}\n\n\treturn 0;\n}\n\n/* edma_free_tx_rings()\n *\tFree tx rings\n */\nvoid edma_free_tx_rings(struct edma_common_info *edma_cinfo)\n{\n\tint i;\n\n\tfor (i = 0; i < edma_cinfo->num_tx_queues; i++)\n\t\tedma_free_tx_ring(edma_cinfo, edma_cinfo->tpd_ring[i]);\n}\n\n/* edma_free_tx_resources()\n *\tFree buffers associated with tx rings\n */\nvoid edma_free_tx_resources(struct edma_common_info *edma_cinfo)\n{\n\tstruct edma_tx_desc_ring *etdr;\n\tstruct edma_sw_desc *sw_desc;\n\tstruct platform_device *pdev = edma_cinfo->pdev;\n\tint i, j;\n\n\tfor (i = 0; i < edma_cinfo->num_tx_queues; i++) {\n\t\tetdr = edma_cinfo->tpd_ring[i];\n\t\tfor (j = 0; j < EDMA_TX_RING_SIZE; j++) {\n\t\t\tsw_desc = &etdr->sw_desc[j];\n\t\t\tif (sw_desc->flags & (EDMA_SW_DESC_FLAG_SKB_HEAD |\n\t\t\t\tEDMA_SW_DESC_FLAG_SKB_FRAG | EDMA_SW_DESC_FLAG_SKB_FRAGLIST))\n\t\t\t\tedma_tx_unmap_and_free(pdev, sw_desc);\n\t\t}\n\t}\n}\n\n/* edma_alloc_rx_rings()\n *\tAllocate rx rings\n */\nint edma_alloc_rx_rings(struct edma_common_info *edma_cinfo)\n{\n\tstruct platform_device *pdev = edma_cinfo->pdev;\n\tint i, j, err = 0;\n\n\tfor (i = 0, j = 0; i < edma_cinfo->num_rx_queues; i++) {\n\t\terr = edma_alloc_rx_ring(edma_cinfo, edma_cinfo->rfd_ring[j]);\n\t\tif (err) {\n\t\t\tdev_err(&pdev->dev, \"Rx Queue alloc%u failed\\n\", i);\n\t\t\treturn err;\n\t\t}\n\t\tj += ((edma_cinfo->num_rx_queues == 4) ? 2 : 1);\n\t}\n\n\treturn 0;\n}\n\n/* edma_free_rx_rings()\n *\tfree rx rings\n */\nvoid edma_free_rx_rings(struct edma_common_info *edma_cinfo)\n{\n\tint i, j;\n\n\tfor (i = 0, j = 0; i < edma_cinfo->num_rx_queues; i++) {\n\t\tedma_free_rx_ring(edma_cinfo, edma_cinfo->rfd_ring[j]);\n\t\tj += ((edma_cinfo->num_rx_queues == 4) ? 2 : 1);\n\t}\n}\n\n/* edma_free_queues()\n *\tFree the queues allocaated\n */\nvoid edma_free_queues(struct edma_common_info *edma_cinfo)\n{\n\tint i , j;\n\n\tfor (i = 0; i < edma_cinfo->num_tx_queues; i++) {\n\t\tif (edma_cinfo->tpd_ring[i])\n\t\t\tkfree(edma_cinfo->tpd_ring[i]);\n\t\tedma_cinfo->tpd_ring[i] = NULL;\n\t}\n\n\tfor (i = 0, j = 0; i < edma_cinfo->num_rx_queues; i++) {\n\t\tif (edma_cinfo->rfd_ring[j])\n\t\t\tkfree(edma_cinfo->rfd_ring[j]);\n\t\tedma_cinfo->rfd_ring[j] = NULL;\n\t\tj += ((edma_cinfo->num_rx_queues == 4) ? 2 : 1);\n\t}\n\n\tedma_cinfo->num_rx_queues = 0;\n\tedma_cinfo->num_tx_queues = 0;\n\n\treturn;\n}\n\n/* edma_free_rx_resources()\n *\tFree buffers associated with tx rings\n */\nvoid edma_free_rx_resources(struct edma_common_info *edma_cinfo)\n{\n        struct edma_rfd_desc_ring *erdr;\n\tstruct edma_sw_desc *sw_desc;\n\tstruct platform_device *pdev = edma_cinfo->pdev;\n\tint i, j, k;\n\n\tfor (i = 0, k = 0; i < edma_cinfo->num_rx_queues; i++) {\n\t\terdr = edma_cinfo->rfd_ring[k];\n\t\tfor (j = 0; j < EDMA_RX_RING_SIZE; j++) {\n\t\t\tsw_desc = &erdr->sw_desc[j];\n\t\t\tif (likely(sw_desc->flags & EDMA_SW_DESC_FLAG_SKB_HEAD)) {\n\t\t\t\tdma_unmap_single(&pdev->dev, sw_desc->dma,\n\t\t\t\t\tsw_desc->length, DMA_FROM_DEVICE);\n\t\t\t\tedma_clean_rfd(erdr, j);\n\t\t\t} else if ((sw_desc->flags & EDMA_SW_DESC_FLAG_SKB_FRAG)) {\n\t\t\t\tdma_unmap_page(&pdev->dev, sw_desc->dma,\n\t\t\t\t\tsw_desc->length, DMA_FROM_DEVICE);\n\t\t\t\tedma_clean_rfd(erdr, j);\n\t\t\t}\n\t\t}\n\t\tk += ((edma_cinfo->num_rx_queues == 4) ? 2 : 1);\n\n\t}\n}\n\n/* edma_alloc_queues_tx()\n *\tAllocate memory for all rings\n */\nint edma_alloc_queues_tx(struct edma_common_info *edma_cinfo)\n{\n\tint i;\n\n\tfor (i = 0; i < edma_cinfo->num_tx_queues; i++) {\n\t\tstruct edma_tx_desc_ring *etdr;\n\t\tetdr = kzalloc(sizeof(struct edma_tx_desc_ring), GFP_KERNEL);\n\t\tif (!etdr)\n\t\t\tgoto err;\n\t\tetdr->count = edma_cinfo->tx_ring_count;\n\t\tedma_cinfo->tpd_ring[i] = etdr;\n\t}\n\n\treturn 0;\nerr:\n\tedma_free_queues(edma_cinfo);\n\treturn -1;\n}\n\n/* edma_alloc_queues_rx()\n *\tAllocate memory for all rings\n */\nint edma_alloc_queues_rx(struct edma_common_info *edma_cinfo)\n{\n\tint i, j;\n\n\tfor (i = 0, j = 0; i < edma_cinfo->num_rx_queues; i++) {\n\t\tstruct edma_rfd_desc_ring *rfd_ring;\n\t\trfd_ring = kzalloc(sizeof(struct edma_rfd_desc_ring),\n\t\t\t\tGFP_KERNEL);\n\t\tif (!rfd_ring)\n\t\t\tgoto err;\n\t\trfd_ring->count = edma_cinfo->rx_ring_count;\n\t\tedma_cinfo->rfd_ring[j] = rfd_ring;\n\t\tj += ((edma_cinfo->num_rx_queues == 4) ? 2 : 1);\n\t}\n\treturn 0;\nerr:\n\tedma_free_queues(edma_cinfo);\n\treturn -1;\n}\n\n/* edma_clear_irq_status()\n *\tClear interrupt status\n */\nvoid edma_clear_irq_status()\n{\n\tedma_write_reg(EDMA_REG_RX_ISR, 0xff);\n\tedma_write_reg(EDMA_REG_TX_ISR, 0xffff);\n\tedma_write_reg(EDMA_REG_MISC_ISR, 0x1fff);\n\tedma_write_reg(EDMA_REG_WOL_ISR, 0x1);\n};\n\n/* edma_configure()\n *\tConfigure skb, edma interrupts and control register.\n */\nint edma_configure(struct edma_common_info *edma_cinfo)\n{\n\tstruct edma_hw *hw = &edma_cinfo->hw;\n\tu32 intr_modrt_data;\n\tu32 intr_ctrl_data = 0;\n\tint i, j, ret_count;\n\n\tedma_read_reg(EDMA_REG_INTR_CTRL, &intr_ctrl_data);\n\tintr_ctrl_data &= ~(1 << EDMA_INTR_SW_IDX_W_TYP_SHIFT);\n\tintr_ctrl_data |= hw->intr_sw_idx_w << EDMA_INTR_SW_IDX_W_TYP_SHIFT;\n\tedma_write_reg(EDMA_REG_INTR_CTRL, intr_ctrl_data);\n\n\tedma_clear_irq_status();\n\n\t/* Clear any WOL status */\n\tedma_write_reg(EDMA_REG_WOL_CTRL, 0);\n\tintr_modrt_data = (EDMA_TX_IMT << EDMA_IRQ_MODRT_TX_TIMER_SHIFT);\n\tintr_modrt_data |= (EDMA_RX_IMT << EDMA_IRQ_MODRT_RX_TIMER_SHIFT);\n\tedma_write_reg(EDMA_REG_IRQ_MODRT_TIMER_INIT, intr_modrt_data);\n\tedma_configure_tx(edma_cinfo);\n\tedma_configure_rx(edma_cinfo);\n\n\t/* Allocate the RX buffer */\n\tfor (i = 0, j = 0; i < edma_cinfo->num_rx_queues; i++) {\n\t\tstruct edma_rfd_desc_ring *ring = edma_cinfo->rfd_ring[j];\n\t\tret_count = edma_alloc_rx_buf(edma_cinfo, ring, ring->count, j);\n\t\tif (ret_count) {\n\t\t\tdev_dbg(&edma_cinfo->pdev->dev, \"not all rx buffers allocated\\n\");\n\t\t}\n\t\tj += ((edma_cinfo->num_rx_queues == 4) ? 2 : 1);\n\t}\n\n\t/* Configure descriptor Ring */\n\tedma_init_desc(edma_cinfo);\n\treturn 0;\n}\n\n/* edma_irq_enable()\n *\tEnable default interrupt generation settings\n */\nvoid edma_irq_enable(struct edma_common_info *edma_cinfo)\n{\n\tstruct edma_hw *hw = &edma_cinfo->hw;\n\tint i, j;\n\n\tedma_write_reg(EDMA_REG_RX_ISR, 0xff);\n\tfor (i = 0, j = 0; i < edma_cinfo->num_rx_queues; i++) {\n\t\tedma_write_reg(EDMA_REG_RX_INT_MASK_Q(j), hw->rx_intr_mask);\n\t\tj += ((edma_cinfo->num_rx_queues == 4) ? 2 : 1);\n\t}\n\tedma_write_reg(EDMA_REG_TX_ISR, 0xffff);\n\tfor (i = 0; i < edma_cinfo->num_tx_queues; i++)\n\t\tedma_write_reg(EDMA_REG_TX_INT_MASK_Q(i), hw->tx_intr_mask);\n}\n\n/* edma_irq_disable()\n *\tDisable Interrupt\n */\nvoid edma_irq_disable(struct edma_common_info *edma_cinfo)\n{\n\tint i;\n\n\tfor (i = 0; i < EDMA_MAX_RECEIVE_QUEUE; i++)\n\t\tedma_write_reg(EDMA_REG_RX_INT_MASK_Q(i), 0x0);\n\n\tfor (i = 0; i < EDMA_MAX_TRANSMIT_QUEUE; i++)\n\t\tedma_write_reg(EDMA_REG_TX_INT_MASK_Q(i), 0x0);\n\tedma_write_reg(EDMA_REG_MISC_IMR, 0);\n\tedma_write_reg(EDMA_REG_WOL_IMR, 0);\n}\n\n/* edma_free_irqs()\n *\tFree All IRQs\n */\nvoid edma_free_irqs(struct edma_adapter *adapter)\n{\n\tstruct edma_common_info *edma_cinfo = adapter->edma_cinfo;\n\tint i, j;\n\tint k = ((edma_cinfo->num_rx_queues == 4) ? 1 : 2);\n\n\tfor (i = 0; i < CONFIG_NR_CPUS; i++) {\n\t\tfor (j = edma_cinfo->edma_percpu_info[i].tx_start; j < (edma_cinfo->edma_percpu_info[i].tx_start + 4); j++)\n\t\t\tfree_irq(edma_cinfo->tx_irq[j], &edma_cinfo->edma_percpu_info[i]);\n\n\t\tfor (j = edma_cinfo->edma_percpu_info[i].rx_start; j < (edma_cinfo->edma_percpu_info[i].rx_start + k); j++)\n\t\t\tfree_irq(edma_cinfo->rx_irq[j], &edma_cinfo->edma_percpu_info[i]);\n\t}\n}\n\n/* edma_enable_rx_ctrl()\n *\tEnable RX queue control\n */\nvoid edma_enable_rx_ctrl(struct edma_hw *hw)\n{\n\tu32 data;\n\n\tedma_read_reg(EDMA_REG_RXQ_CTRL, &data);\n\tdata |= EDMA_RXQ_CTRL_EN;\n\tedma_write_reg(EDMA_REG_RXQ_CTRL, data);\n}\n\n\n/* edma_enable_tx_ctrl()\n *\tEnable TX queue control\n */\nvoid edma_enable_tx_ctrl(struct edma_hw *hw)\n{\n\tu32 data;\n\n\tedma_read_reg(EDMA_REG_TXQ_CTRL, &data);\n\tdata |= EDMA_TXQ_CTRL_TXQ_EN;\n\tedma_write_reg(EDMA_REG_TXQ_CTRL, data);\n}\n\n/* edma_stop_rx_tx()\n *\tDisable RX/TQ Queue control\n */\nvoid edma_stop_rx_tx(struct edma_hw *hw)\n{\n\tu32 data;\n\n\tedma_read_reg(EDMA_REG_RXQ_CTRL, &data);\n\tdata &= ~EDMA_RXQ_CTRL_EN;\n\tedma_write_reg(EDMA_REG_RXQ_CTRL, data);\n\tedma_read_reg(EDMA_REG_TXQ_CTRL, &data);\n\tdata &= ~EDMA_TXQ_CTRL_TXQ_EN;\n\tedma_write_reg(EDMA_REG_TXQ_CTRL, data);\n}\n\n/* edma_reset()\n *\tReset the EDMA\n */\nint edma_reset(struct edma_common_info *edma_cinfo)\n{\n\tstruct edma_hw *hw = &edma_cinfo->hw;\n\n\tedma_irq_disable(edma_cinfo);\n\n\tedma_clear_irq_status();\n\n\tedma_stop_rx_tx(hw);\n\n\treturn 0;\n}\n\n/* edma_fill_netdev()\n * \tFill netdev for each etdr\n */\nint edma_fill_netdev(struct edma_common_info *edma_cinfo, int queue_id,\n\t\t    int dev, int txq_id)\n{\n\tstruct edma_tx_desc_ring *etdr;\n\tint i = 0;\n\n\tetdr = edma_cinfo->tpd_ring[queue_id];\n\n\twhile (etdr->netdev[i])\n\t\ti++;\n\n\tif (i >= EDMA_MAX_NETDEV_PER_QUEUE)\n\t\treturn -1;\n\n\t/* Populate the netdev associated with the tpd ring */\n\tetdr->netdev[i] = edma_netdev[dev];\n\tetdr->nq[i] = netdev_get_tx_queue(edma_netdev[dev], txq_id);\n\n\treturn 0;\n}\n\n/* edma_set_mac()\n *\tChange the Ethernet Address of the NIC\n */\nint edma_set_mac_addr(struct net_device *netdev, void *p)\n{\n\tstruct sockaddr *addr = p;\n\n\tif (!is_valid_ether_addr(addr->sa_data))\n\t\treturn -EINVAL;\n\n\tif (netif_running(netdev))\n\t\treturn -EBUSY;\n\n\tmemcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);\n\treturn 0;\n}\n\n/* edma_set_stp_rstp()\n *\tset stp/rstp\n */\nvoid edma_set_stp_rstp(bool rstp)\n{\n\tedma_stp_rstp = rstp;\n}\n\n/* edma_assign_ath_hdr_type()\n *\tassign atheros header eth type\n */\nvoid edma_assign_ath_hdr_type(int eth_type)\n{\n\tedma_ath_eth_type = eth_type & EDMA_ETH_TYPE_MASK;\n}\n\n/* edma_get_default_vlan_tag()\n *\tUsed by other modules to get the default vlan tag\n */\nint edma_get_default_vlan_tag(struct net_device *netdev)\n{\n\tstruct edma_adapter *adapter = netdev_priv(netdev);\n\n\tif (adapter->default_vlan_tag)\n\t\treturn adapter->default_vlan_tag;\n\n\treturn 0;\n}\n\n/* edma_open()\n *\tgets called when netdevice is up, start the queue.\n */\nint edma_open(struct net_device *netdev)\n{\n\tstruct edma_adapter *adapter = netdev_priv(netdev);\n\tstruct platform_device *pdev = adapter->edma_cinfo->pdev;\n\n\tnetif_tx_start_all_queues(netdev);\n\tedma_initialise_rfs_flow_table(adapter);\n\tset_bit(__EDMA_UP, &adapter->state_flags);\n\n\t/* if Link polling is enabled, in our case enabled for WAN, then\n\t * do a phy start, else always set link as UP\n\t */\n\tif (adapter->poll_required) {\n\t\tif (!IS_ERR(adapter->phydev)) {\n\t\t\t/* AR40xx calibration will leave the PHY in unwanted state,\n\t\t\t * so a soft reset is required before phy_start()\n\t\t\t */\n\t\t\tgenphy_soft_reset(adapter->phydev);\n\t\t\tphy_start(adapter->phydev);\n\t\t\tphy_start_aneg(adapter->phydev);\n\t\t\tadapter->link_state = __EDMA_LINKDOWN;\n\t\t} else {\n\t\t\tdev_dbg(&pdev->dev, \"Invalid PHY device for a link polled interface\\n\");\n\t\t}\n\t} else {\n\t\tadapter->link_state = __EDMA_LINKUP;\n\t\tnetif_carrier_on(netdev);\n\t}\n\n\treturn 0;\n}\n\n\n/* edma_close()\n *\tgets called when netdevice is down, stops the queue.\n */\nint edma_close(struct net_device *netdev)\n{\n\tstruct edma_adapter *adapter = netdev_priv(netdev);\n\n\tedma_free_rfs_flow_table(adapter);\n\tnetif_carrier_off(netdev);\n\tnetif_tx_stop_all_queues(netdev);\n\n\tif (adapter->poll_required) {\n\t\tif (!IS_ERR(adapter->phydev))\n\t\t\tphy_stop(adapter->phydev);\n\t}\n\n\tadapter->link_state = __EDMA_LINKDOWN;\n\n\t/* Set GMAC state to UP before link state is checked\n\t */\n\tclear_bit(__EDMA_UP, &adapter->state_flags);\n\n\treturn 0;\n}\n\n/* edma_poll\n *\tpolling function that gets called when the napi gets scheduled.\n *\n * Main sequence of task performed in this api\n * is clear irq status -> clear_tx_irq -> clean_rx_irq->\n * enable interrupts.\n */\nint edma_poll(struct napi_struct *napi, int budget)\n{\n\tstruct edma_per_cpu_queues_info *edma_percpu_info = container_of(napi,\n\t\tstruct edma_per_cpu_queues_info, napi);\n\tstruct edma_common_info *edma_cinfo = edma_percpu_info->edma_cinfo;\n\tu32 reg_data;\n\tu32 shadow_rx_status, shadow_tx_status;\n\tint queue_id;\n\tint i, work_done = 0;\n\tu16 rx_pending_fill;\n\n\t/* Store the Rx/Tx status by ANDing it with\n\t * appropriate CPU RX?TX mask\n\t */\n\tedma_read_reg(EDMA_REG_RX_ISR, &reg_data);\n\tedma_percpu_info->rx_status |= reg_data & edma_percpu_info->rx_mask;\n\tshadow_rx_status = edma_percpu_info->rx_status;\n\tedma_read_reg(EDMA_REG_TX_ISR, &reg_data);\n\tedma_percpu_info->tx_status |= reg_data & edma_percpu_info->tx_mask;\n\tshadow_tx_status = edma_percpu_info->tx_status;\n\n\t/* Every core will have a start, which will be computed\n\t * in probe and stored in edma_percpu_info->tx_start variable.\n\t * We will shift the status bit by tx_start to obtain\n\t * status bits for the core on which the current processing\n\t * is happening. Since, there are 4 tx queues per core,\n\t * we will run the loop till we get the correct queue to clear.\n\t */\n\twhile (edma_percpu_info->tx_status) {\n\t\tqueue_id = ffs(edma_percpu_info->tx_status) - 1;\n\t\tedma_tx_complete(edma_cinfo, queue_id);\n\t\tedma_percpu_info->tx_status &= ~(1 << queue_id);\n\t}\n\n\t/* Every core will have a start, which will be computed\n\t * in probe and stored in edma_percpu_info->tx_start variable.\n\t * We will shift the status bit by tx_start to obtain\n\t * status bits for the core on which the current processing\n\t * is happening. Since, there are 4 tx queues per core, we\n\t * will run the loop till we get the correct queue to clear.\n\t */\n\twhile (edma_percpu_info->rx_status) {\n\t\tqueue_id = ffs(edma_percpu_info->rx_status) - 1;\n\t\trx_pending_fill = edma_rx_complete(edma_cinfo, &work_done,\n\t\t\t\t\t\t   budget, queue_id, napi);\n\n\t\tif (likely(work_done < budget)) {\n\t\t\tif (rx_pending_fill) {\n                          \t/* reschedule poll() to refill rx buffer deficit */\n\t\t\t\twork_done = budget;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\tedma_percpu_info->rx_status &= ~(1 << queue_id);\n\t\t} else {\n\t\t\tbreak;\n\t\t}\n\t}\n\n\t/* Clear the status register, to avoid the interrupts to\n\t * reoccur.This clearing of interrupt status register is\n\t * done here as writing to status register only takes place\n\t * once the  producer/consumer index has been updated to\n\t * reflect that the packet transmission/reception went fine.\n\t */\n\tedma_write_reg(EDMA_REG_RX_ISR, shadow_rx_status);\n\tedma_write_reg(EDMA_REG_TX_ISR, shadow_tx_status);\n\n\t/* If budget not fully consumed, exit the polling mode */\n\tif (likely(work_done < budget)) {\n\t\tnapi_complete(napi);\n\n\t\t/* re-enable the interrupts */\n\t\tfor (i = 0; i < edma_cinfo->num_rxq_per_core; i++)\n\t\t\tedma_write_reg(EDMA_REG_RX_INT_MASK_Q(edma_percpu_info->rx_start + i), 0x1);\n\t\tfor (i = 0; i < edma_cinfo->num_txq_per_core; i++)\n\t\t\tedma_write_reg(EDMA_REG_TX_INT_MASK_Q(edma_percpu_info->tx_start + i), 0x1);\n\t}\n\n\treturn work_done;\n}\n\n/* edma interrupt()\n *\tinterrupt handler\n */\nirqreturn_t edma_interrupt(int irq, void *dev)\n{\n\tstruct edma_per_cpu_queues_info *edma_percpu_info = (struct edma_per_cpu_queues_info *) dev;\n\tstruct edma_common_info *edma_cinfo = edma_percpu_info->edma_cinfo;\n\tint i;\n\n\t/* Unmask the TX/RX interrupt register */\n\tfor (i = 0; i < edma_cinfo->num_rxq_per_core; i++)\n\t\tedma_write_reg(EDMA_REG_RX_INT_MASK_Q(edma_percpu_info->rx_start + i), 0x0);\n\n\tfor (i = 0; i < edma_cinfo->num_txq_per_core; i++)\n\t\tedma_write_reg(EDMA_REG_TX_INT_MASK_Q(edma_percpu_info->tx_start + i), 0x0);\n\n\tnapi_schedule(&edma_percpu_info->napi);\n\n\treturn IRQ_HANDLED;\n}\n"
  },
  {
    "path": "target/linux/ipq40xx/files/drivers/net/ethernet/qualcomm/essedma/edma.h",
    "content": "/*\n * Copyright (c) 2014 - 2016, The Linux Foundation. All rights reserved.\n *\n * Permission to use, copy, modify, and/or distribute this software for\n * any purpose with or without fee is hereby granted, provided that the\n * above copyright notice and this permission notice appear in all copies.\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT\n * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n */\n\n#ifndef _EDMA_H_\n#define _EDMA_H_\n\n#include <linux/init.h>\n#include <linux/interrupt.h>\n#include <linux/types.h>\n#include <linux/errno.h>\n#include <linux/module.h>\n#include <linux/netdevice.h>\n#include <linux/etherdevice.h>\n#include <linux/skbuff.h>\n#include <linux/io.h>\n#include <linux/vmalloc.h>\n#include <linux/pagemap.h>\n#include <linux/smp.h>\n#include <linux/platform_device.h>\n#include <linux/of.h>\n#include <linux/of_device.h>\n#include <linux/clk.h>\n#include <linux/kernel.h>\n#include <linux/device.h>\n#include <linux/sysctl.h>\n#include <linux/phy.h>\n#include <linux/of_net.h>\n#include <net/checksum.h>\n#include <net/ip6_checksum.h>\n#include <asm-generic/bug.h>\n#include \"ess_edma.h\"\n\n#define EDMA_CPU_CORES_SUPPORTED 4\n#define EDMA_MAX_PORTID_SUPPORTED 5\n#define EDMA_MAX_VLAN_SUPPORTED  EDMA_MAX_PORTID_SUPPORTED\n#define EDMA_MAX_PORTID_BITMAP_INDEX (EDMA_MAX_PORTID_SUPPORTED + 1)\n#define EDMA_MAX_PORTID_BITMAP_SUPPORTED 0x1f\t/* 0001_1111 = 0x1f */\n#define EDMA_MAX_NETDEV_PER_QUEUE 4 /* 3 Netdev per queue, 1 space for indexing */\n\n#define EDMA_MAX_RECEIVE_QUEUE 8\n#define EDMA_MAX_TRANSMIT_QUEUE 16\n\n/* WAN/LAN adapter number */\n#define EDMA_WAN 0\n#define EDMA_LAN 1\n\n/* VLAN tag */\n#define EDMA_LAN_DEFAULT_VLAN 1\n#define EDMA_WAN_DEFAULT_VLAN 2\n\n#define EDMA_DEFAULT_GROUP1_VLAN 1\n#define EDMA_DEFAULT_GROUP2_VLAN 2\n#define EDMA_DEFAULT_GROUP3_VLAN 3\n#define EDMA_DEFAULT_GROUP4_VLAN 4\n#define EDMA_DEFAULT_GROUP5_VLAN 5\n\n/* Queues exposed to linux kernel */\n#define EDMA_NETDEV_TX_QUEUE 4\n#define EDMA_NETDEV_RX_QUEUE 4\n\n/* Number of queues per core */\n#define EDMA_NUM_TXQ_PER_CORE 4\n#define EDMA_NUM_RXQ_PER_CORE 2\n\n#define EDMA_TPD_EOP_SHIFT 31\n\n#define EDMA_PORT_ID_SHIFT 12\n#define EDMA_PORT_ID_MASK 0x7\n\n/* tpd word 3 bit 18-28 */\n#define EDMA_TPD_PORT_BITMAP_SHIFT 18\n\n#define EDMA_TPD_FROM_CPU_SHIFT 25\n\n#define EDMA_FROM_CPU_MASK 0x80\n#define EDMA_SKB_PRIORITY_MASK 0x38\n\n/* TX/RX descriptor ring count */\n/* should be a power of 2 */\n#define EDMA_RX_RING_SIZE 128\n#define EDMA_TX_RING_SIZE 128\n\n/* Flags used in paged/non paged mode */\n#define EDMA_RX_HEAD_BUFF_SIZE_JUMBO 256\n#define EDMA_RX_HEAD_BUFF_SIZE 1540\n\n/* MAX frame size supported by switch */\n#define EDMA_MAX_JUMBO_FRAME_SIZE 9216\n\n/* Configurations */\n#define EDMA_INTR_CLEAR_TYPE 0\n#define EDMA_INTR_SW_IDX_W_TYPE 0\n#define EDMA_FIFO_THRESH_TYPE 0\n#define EDMA_RSS_TYPE 0\n#define EDMA_RX_IMT 0x0020\n#define EDMA_TX_IMT 0x0050\n#define EDMA_TPD_BURST 5\n#define EDMA_TXF_BURST 0x100\n#define EDMA_RFD_BURST 8\n#define EDMA_RFD_THR 16\n#define EDMA_RFD_LTHR 0\n\n/* RX/TX per CPU based mask/shift */\n#define EDMA_TX_PER_CPU_MASK 0xF\n#define EDMA_RX_PER_CPU_MASK 0x3\n#define EDMA_TX_PER_CPU_MASK_SHIFT 0x2\n#define EDMA_RX_PER_CPU_MASK_SHIFT 0x1\n#define EDMA_TX_CPU_START_SHIFT 0x2\n#define EDMA_RX_CPU_START_SHIFT 0x1\n\n/* FLags used in transmit direction */\n#define EDMA_HW_CHECKSUM 0x00000001\n#define EDMA_VLAN_TX_TAG_INSERT_FLAG 0x00000002\n#define EDMA_VLAN_TX_TAG_INSERT_DEFAULT_FLAG 0x00000004\n\n#define EDMA_SW_DESC_FLAG_LAST 0x1\n#define EDMA_SW_DESC_FLAG_SKB_HEAD 0x2\n#define EDMA_SW_DESC_FLAG_SKB_FRAG 0x4\n#define EDMA_SW_DESC_FLAG_SKB_FRAGLIST 0x8\n#define EDMA_SW_DESC_FLAG_SKB_NONE 0x10\n#define EDMA_SW_DESC_FLAG_SKB_REUSE 0x20\n\n\n#define EDMA_MAX_SKB_FRAGS (MAX_SKB_FRAGS + 1)\n\n/* Ethtool specific list of EDMA supported features */\n#define EDMA_SUPPORTED_FEATURES (SUPPORTED_10baseT_Half \\\n\t\t\t\t\t| SUPPORTED_10baseT_Full \\\n\t\t\t\t\t| SUPPORTED_100baseT_Half \\\n\t\t\t\t\t| SUPPORTED_100baseT_Full \\\n\t\t\t\t\t| SUPPORTED_1000baseT_Full)\n\n/* Recevie side atheros Header */\n#define EDMA_RX_ATH_HDR_VERSION 0x2\n#define EDMA_RX_ATH_HDR_VERSION_SHIFT 14\n#define EDMA_RX_ATH_HDR_PRIORITY_SHIFT 11\n#define EDMA_RX_ATH_PORT_TYPE_SHIFT 6\n#define EDMA_RX_ATH_HDR_RSTP_PORT_TYPE 0x4\n\n/* Transmit side atheros Header */\n#define EDMA_TX_ATH_HDR_PORT_BITMAP_MASK 0x7F\n#define EDMA_TX_ATH_HDR_FROM_CPU_MASK 0x80\n#define EDMA_TX_ATH_HDR_FROM_CPU_SHIFT 7\n\n#define EDMA_TXQ_START_CORE0 8\n#define EDMA_TXQ_START_CORE1 12\n#define EDMA_TXQ_START_CORE2 0\n#define EDMA_TXQ_START_CORE3 4\n\n#define EDMA_TXQ_IRQ_MASK_CORE0 0x0F00\n#define EDMA_TXQ_IRQ_MASK_CORE1 0xF000\n#define EDMA_TXQ_IRQ_MASK_CORE2 0x000F\n#define EDMA_TXQ_IRQ_MASK_CORE3 0x00F0\n\n#define EDMA_ETH_HDR_LEN 12\n#define EDMA_ETH_TYPE_MASK 0xFFFF\n\n#define EDMA_RX_BUFFER_WRITE 16\n#define EDMA_RFD_AVAIL_THR 80\n\n#define EDMA_GMAC_NO_MDIO_PHY\tPHY_MAX_ADDR\n\nextern int ssdk_rfs_ipct_rule_set(__be32 ip_src, __be32 ip_dst,\n\t\t\t\t  __be16 sport, __be16 dport,\n\t\t\t\t  uint8_t proto, u16 loadbalance, bool action);\nstruct edma_ethtool_statistics {\n\tu32 tx_q0_pkt;\n\tu32 tx_q1_pkt;\n\tu32 tx_q2_pkt;\n\tu32 tx_q3_pkt;\n\tu32 tx_q4_pkt;\n\tu32 tx_q5_pkt;\n\tu32 tx_q6_pkt;\n\tu32 tx_q7_pkt;\n\tu32 tx_q8_pkt;\n\tu32 tx_q9_pkt;\n\tu32 tx_q10_pkt;\n\tu32 tx_q11_pkt;\n\tu32 tx_q12_pkt;\n\tu32 tx_q13_pkt;\n\tu32 tx_q14_pkt;\n\tu32 tx_q15_pkt;\n\tu32 tx_q0_byte;\n\tu32 tx_q1_byte;\n\tu32 tx_q2_byte;\n\tu32 tx_q3_byte;\n\tu32 tx_q4_byte;\n\tu32 tx_q5_byte;\n\tu32 tx_q6_byte;\n\tu32 tx_q7_byte;\n\tu32 tx_q8_byte;\n\tu32 tx_q9_byte;\n\tu32 tx_q10_byte;\n\tu32 tx_q11_byte;\n\tu32 tx_q12_byte;\n\tu32 tx_q13_byte;\n\tu32 tx_q14_byte;\n\tu32 tx_q15_byte;\n\tu32 rx_q0_pkt;\n\tu32 rx_q1_pkt;\n\tu32 rx_q2_pkt;\n\tu32 rx_q3_pkt;\n\tu32 rx_q4_pkt;\n\tu32 rx_q5_pkt;\n\tu32 rx_q6_pkt;\n\tu32 rx_q7_pkt;\n\tu32 rx_q0_byte;\n\tu32 rx_q1_byte;\n\tu32 rx_q2_byte;\n\tu32 rx_q3_byte;\n\tu32 rx_q4_byte;\n\tu32 rx_q5_byte;\n\tu32 rx_q6_byte;\n\tu32 rx_q7_byte;\n\tu32 tx_desc_error;\n\tu32 rx_alloc_fail_ctr;\n};\n\nstruct edma_mdio_data {\n\tstruct mii_bus\t*mii_bus;\n\tvoid __iomem\t*membase;\n\tint phy_irq[PHY_MAX_ADDR];\n};\n\n/* EDMA LINK state */\nenum edma_link_state {\n\t__EDMA_LINKUP, /* Indicate link is UP */\n\t__EDMA_LINKDOWN /* Indicate link is down */\n};\n\n/* EDMA GMAC state */\nenum edma_gmac_state {\n\t__EDMA_UP /* use to indicate GMAC is up */\n};\n\n/* edma transmit descriptor */\nstruct edma_tx_desc {\n\t__le16  len; /* full packet including CRC */\n\t__le16  svlan_tag; /* vlan tag */\n\t__le32  word1; /* byte 4-7 */\n\t__le32  addr; /* address of buffer */\n\t__le32  word3; /* byte 12 */\n};\n\n/* edma receive return descriptor */\nstruct edma_rx_return_desc {\n\tu16 rrd0;\n\tu16 rrd1;\n\tu16 rrd2;\n\tu16 rrd3;\n\tu16 rrd4;\n\tu16 rrd5;\n\tu16 rrd6;\n\tu16 rrd7;\n};\n\n/* RFD descriptor */\nstruct edma_rx_free_desc {\n\t__le32  buffer_addr; /* buffer address */\n};\n\n/* edma hw specific data */\nstruct edma_hw {\n\tu32  __iomem *hw_addr; /* inner register address */\n\tstruct edma_adapter *adapter; /* netdevice adapter */\n\tu32 rx_intr_mask; /*rx interrupt mask */\n\tu32 tx_intr_mask; /* tx interrupt nask */\n\tu32 misc_intr_mask; /* misc interrupt mask */\n\tu32 wol_intr_mask; /* wake on lan interrupt mask */\n\tbool intr_clear_type; /* interrupt clear */\n\tbool intr_sw_idx_w; /* interrupt software index */\n\tu32 rx_head_buff_size; /* Rx buffer size */\n\tu8 rss_type; /* rss protocol type */\n};\n\n/* edma_sw_desc stores software descriptor\n * SW descriptor has 1:1 map with HW descriptor\n */\nstruct edma_sw_desc {\n\tstruct sk_buff *skb;\n\tdma_addr_t dma; /* dma address */\n\tu16 length; /* Tx/Rx buffer length */\n\tu32 flags;\n};\n\n/* per core related information */\nstruct edma_per_cpu_queues_info {\n\tstruct napi_struct napi; /* napi associated with the core */\n\tu32 tx_mask; /* tx interrupt mask */\n\tu32 rx_mask; /* rx interrupt mask */\n\tu32 tx_status; /* tx interrupt status */\n\tu32 rx_status; /* rx interrupt status */\n\tu32 tx_start; /* tx queue start */\n\tu32 rx_start; /* rx queue start */\n\tstruct edma_common_info *edma_cinfo; /* edma common info */\n};\n\n/* edma specific common info */\nstruct edma_common_info {\n\tstruct edma_tx_desc_ring *tpd_ring[16]; /* 16 Tx queues */\n\tstruct edma_rfd_desc_ring *rfd_ring[8]; /* 8 Rx queues */\n\tstruct platform_device *pdev; /* device structure */\n\tstruct net_device *netdev[EDMA_MAX_PORTID_SUPPORTED];\n\tstruct net_device *portid_netdev_lookup_tbl[EDMA_MAX_PORTID_BITMAP_INDEX];\n\tstruct ctl_table_header *edma_ctl_table_hdr;\n\tint num_gmac;\n\tstruct edma_ethtool_statistics edma_ethstats; /* ethtool stats */\n\tint num_rx_queues; /* number of rx queue */\n\tu32 num_tx_queues; /* number of tx queue */\n\tu32 tx_irq[16]; /* number of tx irq */\n\tu32 rx_irq[8]; /* number of rx irq */\n\tu32 from_cpu; /* from CPU TPD field */\n\tu32 num_rxq_per_core; /* Rx queues per core */\n\tu32 num_txq_per_core; /* Tx queues per core */\n\tu16 tx_ring_count; /* Tx ring count */\n\tu16 rx_ring_count; /* Rx ring*/\n\tu16 rx_head_buffer_len; /* rx buffer length */\n\tu16 rx_page_buffer_len; /* rx buffer length */\n\tu32 page_mode; /* Jumbo frame supported flag */\n\tu32 fraglist_mode; /* fraglist supported flag */\n\tstruct edma_hw hw; /* edma hw specific structure */\n\tstruct edma_per_cpu_queues_info edma_percpu_info[CONFIG_NR_CPUS]; /* per cpu information */\n\tspinlock_t stats_lock; /* protect edma stats area for updation */\n\tstruct timer_list edma_stats_timer;\n\tbool is_single_phy;\n\tvoid __iomem *ess_hw_addr;\n\tstruct clk *ess_clk;\n};\n\n/* transimit packet descriptor (tpd) ring */\nstruct edma_tx_desc_ring {\n\tstruct netdev_queue *nq[EDMA_MAX_NETDEV_PER_QUEUE]; /* Linux queue index */\n\tstruct net_device *netdev[EDMA_MAX_NETDEV_PER_QUEUE];\n\t\t\t/* Array of netdevs associated with the tpd ring */\n\tvoid *hw_desc; /* descriptor ring virtual address */\n\tstruct edma_sw_desc *sw_desc; /* buffer associated with ring */\n\tint netdev_bmp; /* Bitmap for per-ring netdevs */\n\tu32 size; /* descriptor ring length in bytes */\n\tu16 count; /* number of descriptors in the ring */\n\tdma_addr_t dma; /* descriptor ring physical address */\n\tu16 sw_next_to_fill; /* next Tx descriptor to fill */\n\tu16 sw_next_to_clean; /* next Tx descriptor to clean */\n};\n\n/* receive free descriptor (rfd) ring */\nstruct edma_rfd_desc_ring {\n\tvoid *hw_desc; /* descriptor ring virtual address */\n\tstruct edma_sw_desc *sw_desc; /* buffer associated with ring */\n\tu16 size; /* bytes allocated to sw_desc */\n\tu16 count; /* number of descriptors in the ring */\n\tdma_addr_t dma; /* descriptor ring physical address */\n\tu16 sw_next_to_fill; /* next descriptor to fill */\n\tu16 sw_next_to_clean; /* next descriptor to clean */\n\tu16 pending_fill; /* fill pending from previous iteration */\n};\n\n/* edma_rfs_flter_node - rfs filter node in hash table */\nstruct edma_rfs_filter_node {\n\tstruct flow_keys keys;\n\tu32 flow_id; /* flow_id of filter provided by kernel */\n\tu16 filter_id; /* filter id of filter returned by adaptor */\n\tu16 rq_id; /* desired rq index */\n\tstruct hlist_node node; /* edma rfs list node */\n};\n\n/* edma_rfs_flow_tbl - rfs flow table */\nstruct edma_rfs_flow_table {\n\tu16 max_num_filter; /* Maximum number of filters edma supports */\n\tu16 hashtoclean; /* hash table index to clean next */\n\tint filter_available; /* Number of free filters available */\n\tstruct hlist_head hlist_head[EDMA_RFS_FLOW_ENTRIES];\n\tspinlock_t rfs_ftab_lock;\n\tstruct timer_list expire_rfs; /* timer function for edma_rps_may_expire_flow */\n};\n\n/* EDMA net device structure */\nstruct edma_adapter {\n\tstruct net_device *netdev; /* netdevice */\n\tstruct platform_device *pdev; /* platform device */\n\tstruct edma_common_info *edma_cinfo; /* edma common info */\n\tstruct phy_device *phydev; /* Phy device */\n\tstruct edma_rfs_flow_table rfs; /* edma rfs flow table */\n\tstruct net_device_stats stats; /* netdev statistics */\n\tset_rfs_filter_callback_t set_rfs_rule;\n\tu32 flags;/* status flags */\n\tunsigned long state_flags; /* GMAC up/down flags */\n\tu32 forced_speed; /* link force speed */\n\tu32 forced_duplex; /* link force duplex */\n\tu32 link_state; /* phy link state */\n\tu32 phy_mdio_addr; /* PHY device address on MII interface */\n\tu32 poll_required; /* check if link polling is required */\n\tu32 tx_start_offset[CONFIG_NR_CPUS]; /* tx queue start */\n\tu32 default_vlan_tag; /* vlan tag */\n\tu32 dp_bitmap;\n\tuint8_t phy_id[MII_BUS_ID_SIZE + 3];\n};\n\nint edma_alloc_queues_tx(struct edma_common_info *edma_cinfo);\nint edma_alloc_queues_rx(struct edma_common_info *edma_cinfo);\nint edma_open(struct net_device *netdev);\nint edma_close(struct net_device *netdev);\nvoid edma_free_tx_resources(struct edma_common_info *edma_c_info);\nvoid edma_free_rx_resources(struct edma_common_info *edma_c_info);\nint edma_alloc_tx_rings(struct edma_common_info *edma_cinfo);\nint edma_alloc_rx_rings(struct edma_common_info *edma_cinfo);\nvoid edma_free_tx_rings(struct edma_common_info *edma_cinfo);\nvoid edma_free_rx_rings(struct edma_common_info *edma_cinfo);\nvoid edma_free_queues(struct edma_common_info *edma_cinfo);\nvoid edma_irq_disable(struct edma_common_info *edma_cinfo);\nint edma_reset(struct edma_common_info *edma_cinfo);\nint edma_poll(struct napi_struct *napi, int budget);\nnetdev_tx_t edma_xmit(struct sk_buff *skb,\n\t\tstruct net_device *netdev);\nint edma_configure(struct edma_common_info *edma_cinfo);\nvoid edma_irq_enable(struct edma_common_info *edma_cinfo);\nvoid edma_enable_tx_ctrl(struct edma_hw *hw);\nvoid edma_enable_rx_ctrl(struct edma_hw *hw);\nvoid edma_stop_rx_tx(struct edma_hw *hw);\nvoid edma_free_irqs(struct edma_adapter *adapter);\nirqreturn_t edma_interrupt(int irq, void *dev);\nvoid edma_write_reg(u16 reg_addr, u32 reg_value);\nvoid edma_read_reg(u16 reg_addr, volatile u32 *reg_value);\nstruct net_device_stats *edma_get_stats(struct net_device *netdev);\nint edma_set_mac_addr(struct net_device *netdev, void *p);\nint edma_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,\n\t\tu16 rxq, u32 flow_id);\nint edma_register_rfs_filter(struct net_device *netdev,\n\t\tset_rfs_filter_callback_t set_filter);\nvoid edma_flow_may_expire(struct timer_list *t);\nvoid edma_set_ethtool_ops(struct net_device *netdev);\nvoid edma_set_stp_rstp(bool tag);\nvoid edma_assign_ath_hdr_type(int tag);\nint edma_get_default_vlan_tag(struct net_device *netdev);\nvoid edma_adjust_link(struct net_device *netdev);\nint edma_fill_netdev(struct edma_common_info *edma_cinfo, int qid, int num, int txq_id);\nvoid edma_read_append_stats(struct edma_common_info *edma_cinfo);\nvoid edma_change_tx_coalesce(int usecs);\nvoid edma_change_rx_coalesce(int usecs);\nvoid edma_get_tx_rx_coalesce(u32 *reg_val);\nvoid edma_clear_irq_status(void);\nvoid ess_set_port_status_speed(struct edma_common_info *edma_cinfo,\n                               struct phy_device *phydev, uint8_t port_id);\n#endif /* _EDMA_H_ */\n"
  },
  {
    "path": "target/linux/ipq40xx/files/drivers/net/ethernet/qualcomm/essedma/edma_axi.c",
    "content": "/*\n * Copyright (c) 2014 - 2016, The Linux Foundation. All rights reserved.\n *\n * Permission to use, copy, modify, and/or distribute this software for\n * any purpose with or without fee is hereby granted, provided that the\n * above copyright notice and this permission notice appear in all copies.\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT\n * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n */\n\n#include <linux/cpu_rmap.h>\n#include <linux/of.h>\n#include <linux/of_net.h>\n#include <linux/timer.h>\n#include <linux/of_platform.h>\n#include <linux/of_address.h>\n#include <linux/of_mdio.h>\n#include <linux/clk.h>\n#include <linux/string.h>\n#include <linux/reset.h>\n#include <linux/version.h>\n#include \"edma.h\"\n#include \"ess_edma.h\"\n\n/* Weight round robin and virtual QID mask */\n#define EDMA_WRR_VID_SCTL_MASK 0xffff\n\n/* Weight round robin and virtual QID shift */\n#define EDMA_WRR_VID_SCTL_SHIFT 16\n\nchar edma_axi_driver_name[] = \"ess_edma\";\nstatic const u32 default_msg = NETIF_MSG_DRV | NETIF_MSG_PROBE |\n\tNETIF_MSG_LINK | NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP;\n\nstatic u32 edma_hw_addr;\n\nchar edma_tx_irq[16][64];\nchar edma_rx_irq[8][64];\nstruct net_device *edma_netdev[EDMA_MAX_PORTID_SUPPORTED];\nstatic u16 tx_start[4] = {EDMA_TXQ_START_CORE0, EDMA_TXQ_START_CORE1,\n\t\t\tEDMA_TXQ_START_CORE2, EDMA_TXQ_START_CORE3};\nstatic u32 tx_mask[4] = {EDMA_TXQ_IRQ_MASK_CORE0, EDMA_TXQ_IRQ_MASK_CORE1,\n\t\t\tEDMA_TXQ_IRQ_MASK_CORE2, EDMA_TXQ_IRQ_MASK_CORE3};\n\nstatic u32 edma_default_ltag  __read_mostly = EDMA_LAN_DEFAULT_VLAN;\nstatic u32 edma_default_wtag  __read_mostly = EDMA_WAN_DEFAULT_VLAN;\nstatic u32 edma_default_group1_vtag  __read_mostly = EDMA_DEFAULT_GROUP1_VLAN;\nstatic u32 edma_default_group2_vtag  __read_mostly = EDMA_DEFAULT_GROUP2_VLAN;\nstatic u32 edma_default_group3_vtag  __read_mostly = EDMA_DEFAULT_GROUP3_VLAN;\nstatic u32 edma_default_group4_vtag  __read_mostly = EDMA_DEFAULT_GROUP4_VLAN;\nstatic u32 edma_default_group5_vtag  __read_mostly = EDMA_DEFAULT_GROUP5_VLAN;\nstatic u32 edma_rss_idt_val = EDMA_RSS_IDT_VALUE;\nstatic u32 edma_rss_idt_idx;\n\nstatic int edma_weight_assigned_to_q __read_mostly;\nstatic int edma_queue_to_virtual_q __read_mostly;\nstatic bool edma_enable_rstp  __read_mostly;\nstatic int edma_athr_hdr_eth_type __read_mostly;\n\nstatic int page_mode;\nmodule_param(page_mode, int, 0);\nMODULE_PARM_DESC(page_mode, \"enable page mode\");\n\nstatic int overwrite_mode;\nmodule_param(overwrite_mode, int, 0);\nMODULE_PARM_DESC(overwrite_mode, \"overwrite default page_mode setting\");\n\nstatic int jumbo_mru = EDMA_RX_HEAD_BUFF_SIZE;\nmodule_param(jumbo_mru, int, 0);\nMODULE_PARM_DESC(jumbo_mru, \"enable fraglist support\");\n\nstatic int num_rxq = 4;\nmodule_param(num_rxq, int, 0);\nMODULE_PARM_DESC(num_rxq, \"change the number of rx queues\");\n\nvoid edma_write_reg(u16 reg_addr, u32 reg_value)\n{\n\twritel(reg_value, ((void __iomem *)(edma_hw_addr + reg_addr)));\n}\n\nvoid edma_read_reg(u16 reg_addr, volatile u32 *reg_value)\n{\n\t*reg_value = readl((void __iomem *)(edma_hw_addr + reg_addr));\n}\n\nstatic void ess_write_reg(struct edma_common_info *edma, u16 reg_addr, u32 reg_value)\n{\n\twritel(reg_value, ((void __iomem *)\n\t\t((unsigned long)edma->ess_hw_addr + reg_addr)));\n}\n\nstatic void ess_read_reg(struct edma_common_info *edma, u16 reg_addr,\n\t\t  volatile u32 *reg_value)\n{\n\t*reg_value = readl((void __iomem *)\n\t\t((unsigned long)edma->ess_hw_addr + reg_addr));\n}\n\nstatic int ess_reset(struct edma_common_info *edma)\n{\n\tstruct device_node *switch_node = NULL;\n\tstruct reset_control *ess_rst;\n\tu32 regval;\n\n\tswitch_node = of_find_node_by_name(NULL, \"ess-switch\");\n\tif (!switch_node) {\n\t\tpr_err(\"switch-node not found\\n\");\n\t\treturn -EINVAL;\n\t}\n\n\tess_rst = of_reset_control_get(switch_node, \"ess_rst\");\n\tof_node_put(switch_node);\n\n\tif (IS_ERR(ess_rst)) {\n\t\tpr_err(\"failed to find ess_rst!\\n\");\n\t\treturn -ENOENT;\n\t}\n\n\treset_control_assert(ess_rst);\n\tmsleep(10);\n\treset_control_deassert(ess_rst);\n\tmsleep(100);\n\treset_control_put(ess_rst);\n\n\t/* Enable only port 5 <--> port 0\n\t * bits 0:6 bitmap of ports it can fwd to */\n#define SET_PORT_BMP(r,v) \\\n\t\tess_read_reg(edma, r, &regval); \\\n\t\tess_write_reg(edma, r, ((regval & ~0x3F) | v));\n\n\tSET_PORT_BMP(ESS_PORT0_LOOKUP_CTRL,0x20);\n\tSET_PORT_BMP(ESS_PORT1_LOOKUP_CTRL,0x00);\n\tSET_PORT_BMP(ESS_PORT2_LOOKUP_CTRL,0x00);\n\tSET_PORT_BMP(ESS_PORT3_LOOKUP_CTRL,0x00);\n\tSET_PORT_BMP(ESS_PORT4_LOOKUP_CTRL,0x00);\n\tSET_PORT_BMP(ESS_PORT5_LOOKUP_CTRL,0x01);\n\tess_write_reg(edma, ESS_RGMII_CTRL, 0x400);\n\tess_write_reg(edma, ESS_PORT0_STATUS, ESS_PORT_1G_FDX);\n\tess_write_reg(edma, ESS_PORT5_STATUS, ESS_PORT_1G_FDX);\n\tess_write_reg(edma, ESS_PORT0_HEADER_CTRL, 0);\n#undef SET_PORT_BMP\n\n\t/* forward multicast and broadcast frames to CPU */\n\tess_write_reg(edma, ESS_FWD_CTRL1,\n\t\t(ESS_PORTS_ALL << ESS_FWD_CTRL1_UC_FLOOD_S) |\n\t\t(ESS_PORTS_ALL << ESS_FWD_CTRL1_MC_FLOOD_S) |\n\t\t(ESS_PORTS_ALL << ESS_FWD_CTRL1_BC_FLOOD_S));\n\n\treturn 0;\n}\n\nvoid ess_set_port_status_speed(struct edma_common_info *edma,\n\t\t\t       struct phy_device *phydev, uint8_t port_id)\n{\n\tuint16_t reg_off = ESS_PORT0_STATUS + (4 * port_id);\n\tuint32_t reg_val = 0;\n\n\tess_read_reg(edma, reg_off, &reg_val);\n\n\t/* reset the speed bits [0:1] */\n\treg_val &= ~ESS_PORT_STATUS_SPEED_INV;\n\n\t/* set the new speed */\n\tswitch(phydev->speed) {\n\t\tcase SPEED_1000:  reg_val |= ESS_PORT_STATUS_SPEED_1000; break;\n\t\tcase SPEED_100:   reg_val |= ESS_PORT_STATUS_SPEED_100;  break;\n\t\tcase SPEED_10:    reg_val |= ESS_PORT_STATUS_SPEED_10;   break;\n\t\tdefault:          reg_val |= ESS_PORT_STATUS_SPEED_INV;  break;\n\t}\n\n\t/* check full/half duplex */\n\tif (phydev->duplex) {\n\t\treg_val |= ESS_PORT_STATUS_DUPLEX_MODE;\n\t} else {\n\t\treg_val &= ~ESS_PORT_STATUS_DUPLEX_MODE;\n\t}\n\n\tess_write_reg(edma, reg_off, reg_val);\n}\n\n/* edma_change_tx_coalesce()\n *\tchange tx interrupt moderation timer\n */\nvoid edma_change_tx_coalesce(int usecs)\n{\n\tu32 reg_value;\n\n\t/* Here, we right shift the value from the user by 1, this is\n\t * done because IMT resolution timer is 2usecs. 1 count\n\t * of this register corresponds to 2 usecs.\n\t */\n\tedma_read_reg(EDMA_REG_IRQ_MODRT_TIMER_INIT, &reg_value);\n\treg_value = ((reg_value & 0xffff) | ((usecs >> 1) << 16));\n\tedma_write_reg(EDMA_REG_IRQ_MODRT_TIMER_INIT, reg_value);\n}\n\n/* edma_change_rx_coalesce()\n *\tchange rx interrupt moderation timer\n */\nvoid edma_change_rx_coalesce(int usecs)\n{\n\tu32 reg_value;\n\n\t/* Here, we right shift the value from the user by 1, this is\n\t * done because IMT resolution timer is 2usecs. 1 count\n\t * of this register corresponds to 2 usecs.\n\t */\n\tedma_read_reg(EDMA_REG_IRQ_MODRT_TIMER_INIT, &reg_value);\n\treg_value = ((reg_value & 0xffff0000) | (usecs >> 1));\n\tedma_write_reg(EDMA_REG_IRQ_MODRT_TIMER_INIT, reg_value);\n}\n\n/* edma_get_tx_rx_coalesce()\n *\tGet tx/rx interrupt moderation value\n */\nvoid edma_get_tx_rx_coalesce(u32 *reg_val)\n{\n\tedma_read_reg(EDMA_REG_IRQ_MODRT_TIMER_INIT, reg_val);\n}\n\nvoid edma_read_append_stats(struct edma_common_info *edma_cinfo)\n{\n\tuint32_t *p;\n\tint i;\n\tu32 stat;\n\n\tspin_lock_bh(&edma_cinfo->stats_lock);\n\tp = (uint32_t *)&(edma_cinfo->edma_ethstats);\n\n\tfor (i = 0; i < EDMA_MAX_TRANSMIT_QUEUE; i++) {\n\t\tedma_read_reg(EDMA_REG_TX_STAT_PKT_Q(i), &stat);\n\t\t*p += stat;\n\t\tp++;\n\t}\n\n\tfor (i = 0; i < EDMA_MAX_TRANSMIT_QUEUE; i++) {\n\t\tedma_read_reg(EDMA_REG_TX_STAT_BYTE_Q(i), &stat);\n\t\t*p += stat;\n\t\tp++;\n\t}\n\n\tfor (i = 0; i < EDMA_MAX_RECEIVE_QUEUE; i++) {\n\t\tedma_read_reg(EDMA_REG_RX_STAT_PKT_Q(i), &stat);\n\t\t*p += stat;\n\t\tp++;\n\t}\n\n\tfor (i = 0; i < EDMA_MAX_RECEIVE_QUEUE; i++) {\n\t\tedma_read_reg(EDMA_REG_RX_STAT_BYTE_Q(i), &stat);\n\t\t*p += stat;\n\t\tp++;\n\t}\n\n\tspin_unlock_bh(&edma_cinfo->stats_lock);\n}\n\nstatic void edma_statistics_timer(struct timer_list *t)\n{\n\tstruct edma_common_info *edma_cinfo =\n\t\tfrom_timer(edma_cinfo, t, edma_stats_timer);\n\n\tedma_read_append_stats(edma_cinfo);\n\n\tmod_timer(&edma_cinfo->edma_stats_timer, jiffies + 1*HZ);\n}\n\nstatic int edma_enable_stp_rstp(struct ctl_table *table, int write,\n\t\t\t\tvoid __user *buffer, size_t *lenp,\n\t\t\t\tloff_t *ppos)\n{\n\tint ret;\n\n\tret = proc_dointvec(table, write, buffer, lenp, ppos);\n\tif (write)\n\t\tedma_set_stp_rstp(edma_enable_rstp);\n\n\treturn ret;\n}\n\nstatic int edma_ath_hdr_eth_type(struct ctl_table *table, int write,\n\t\t\t\t void __user *buffer, size_t *lenp,\n\t\t\t\t loff_t *ppos)\n{\n\tint ret;\n\n\tret = proc_dointvec(table, write, buffer, lenp, ppos);\n\tif (write)\n\t\tedma_assign_ath_hdr_type(edma_athr_hdr_eth_type);\n\n\treturn ret;\n}\n\nstatic int edma_change_default_lan_vlan(struct ctl_table *table, int write,\n\t\t\t\t\tvoid __user *buffer, size_t *lenp,\n\t\t\t\t\tloff_t *ppos)\n{\n\tstruct edma_adapter *adapter;\n\tint ret;\n\n\tif (!edma_netdev[1]) {\n\t\tpr_err(\"Netdevice for default_lan does not exist\\n\");\n\t\treturn -1;\n\t}\n\n\tadapter = netdev_priv(edma_netdev[1]);\n\n\tret = proc_dointvec(table, write, buffer, lenp, ppos);\n\n\tif (write)\n\t\tadapter->default_vlan_tag = edma_default_ltag;\n\n\treturn ret;\n}\n\nstatic int edma_change_default_wan_vlan(struct ctl_table *table, int write,\n\t\t\t\t\tvoid __user *buffer, size_t *lenp,\n\t\t\t\t\tloff_t *ppos)\n{\n\tstruct edma_adapter *adapter;\n\tint ret;\n\n\tif (!edma_netdev[0]) {\n\t\tpr_err(\"Netdevice for default_wan does not exist\\n\");\n\t\treturn -1;\n\t}\n\n\tadapter = netdev_priv(edma_netdev[0]);\n\n\tret = proc_dointvec(table, write, buffer, lenp, ppos);\n\n\tif (write)\n\t\tadapter->default_vlan_tag = edma_default_wtag;\n\n\treturn ret;\n}\n\nstatic int edma_change_group1_vtag(struct ctl_table *table, int write,\n\t\t\t\t   void __user *buffer, size_t *lenp,\n\t\t\t\t   loff_t *ppos)\n{\n\tstruct edma_adapter *adapter;\n\tstruct edma_common_info *edma_cinfo;\n\tint ret;\n\n\tif (!edma_netdev[0]) {\n\t\tpr_err(\"Netdevice for Group 1 does not exist\\n\");\n\t\treturn -1;\n\t}\n\n\tadapter = netdev_priv(edma_netdev[0]);\n\tedma_cinfo = adapter->edma_cinfo;\n\n\tret = proc_dointvec(table, write, buffer, lenp, ppos);\n\n\tif (write)\n\t\tadapter->default_vlan_tag = edma_default_group1_vtag;\n\n\treturn ret;\n}\n\nstatic int edma_change_group2_vtag(struct ctl_table *table, int write,\n\t\t\t\t   void __user *buffer, size_t *lenp,\n\t\t\t\t   loff_t *ppos)\n{\n\tstruct edma_adapter *adapter;\n\tstruct edma_common_info *edma_cinfo;\n\tint ret;\n\n\tif (!edma_netdev[1]) {\n\t\tpr_err(\"Netdevice for Group 2 does not exist\\n\");\n\t\treturn -1;\n\t}\n\n\tadapter = netdev_priv(edma_netdev[1]);\n\tedma_cinfo = adapter->edma_cinfo;\n\n\tret = proc_dointvec(table, write, buffer, lenp, ppos);\n\n\tif (write)\n\t\tadapter->default_vlan_tag = edma_default_group2_vtag;\n\n\treturn ret;\n}\n\nstatic int edma_change_group3_vtag(struct ctl_table *table, int write,\n\t\t\t\t   void __user *buffer, size_t *lenp,\n\t\t\t\t   loff_t *ppos)\n{\n\tstruct edma_adapter *adapter;\n\tstruct edma_common_info *edma_cinfo;\n\tint ret;\n\n\tif (!edma_netdev[2]) {\n\t\tpr_err(\"Netdevice for Group 3 does not exist\\n\");\n\t\treturn -1;\n\t}\n\n\tadapter = netdev_priv(edma_netdev[2]);\n\tedma_cinfo = adapter->edma_cinfo;\n\n\tret = proc_dointvec(table, write, buffer, lenp, ppos);\n\n\tif (write)\n\t\tadapter->default_vlan_tag = edma_default_group3_vtag;\n\n\treturn ret;\n}\n\nstatic int edma_change_group4_vtag(struct ctl_table *table, int write,\n\t\t\t\t   void __user *buffer, size_t *lenp,\n\t\t\t\t   loff_t *ppos)\n{\n\tstruct edma_adapter *adapter;\n\tstruct edma_common_info *edma_cinfo;\n\tint ret;\n\n\tif (!edma_netdev[3]) {\n\t\tpr_err(\"Netdevice for Group 4 does not exist\\n\");\n\t\treturn -1;\n\t}\n\n\tadapter = netdev_priv(edma_netdev[3]);\n\tedma_cinfo = adapter->edma_cinfo;\n\n\tret = proc_dointvec(table, write, buffer, lenp, ppos);\n\n\tif (write)\n\t\tadapter->default_vlan_tag = edma_default_group4_vtag;\n\n\treturn ret;\n}\n\nstatic int edma_change_group5_vtag(struct ctl_table *table, int write,\n\t\t\t\t   void __user *buffer, size_t *lenp,\n\t\t\t\t   loff_t *ppos)\n{\n\tstruct edma_adapter *adapter;\n\tstruct edma_common_info *edma_cinfo;\n\tint ret;\n\n\tif (!edma_netdev[4]) {\n\t\tpr_err(\"Netdevice for Group 5 does not exist\\n\");\n\t\treturn -1;\n\t}\n\n\tadapter = netdev_priv(edma_netdev[4]);\n\tedma_cinfo = adapter->edma_cinfo;\n\n\tret = proc_dointvec(table, write, buffer, lenp, ppos);\n\n\tif (write)\n\t\tadapter->default_vlan_tag = edma_default_group5_vtag;\n\n\treturn ret;\n}\n\nstatic int edma_set_rss_idt_value(struct ctl_table *table, int write,\n\t\t\t\t  void __user *buffer, size_t *lenp,\n\t\t\t\t  loff_t *ppos)\n{\n\tint ret;\n\n\tret = proc_dointvec(table, write, buffer, lenp, ppos);\n\tif (write && !ret)\n\t\tedma_write_reg(EDMA_REG_RSS_IDT(edma_rss_idt_idx),\n\t\t\t       edma_rss_idt_val);\n\treturn ret;\n}\n\nstatic int edma_set_rss_idt_idx(struct ctl_table *table, int write,\n\t\t\t\tvoid __user *buffer, size_t *lenp,\n\t\t\t\tloff_t *ppos)\n{\n\tint ret;\n\tu32 old_value = edma_rss_idt_idx;\n\n\tret = proc_dointvec(table, write, buffer, lenp, ppos);\n\tif (!write || ret)\n\t\treturn ret;\n\n\tif (edma_rss_idt_idx >= EDMA_NUM_IDT) {\n\t\tpr_err(\"Invalid RSS indirection table index %d\\n\",\n\t\t       edma_rss_idt_idx);\n\t\tedma_rss_idt_idx = old_value;\n\t\treturn -EINVAL;\n\t}\n\treturn ret;\n}\n\nstatic int edma_weight_assigned_to_queues(struct ctl_table *table, int write,\n\t\t\t\t\t  void __user *buffer, size_t *lenp,\n\t\t\t\t\t  loff_t *ppos)\n{\n\tint ret, queue_id, weight;\n\tu32 reg_data, data, reg_addr;\n\n\tret = proc_dointvec(table, write, buffer, lenp, ppos);\n\tif (write) {\n\t\tqueue_id = edma_weight_assigned_to_q & EDMA_WRR_VID_SCTL_MASK;\n\t\tif (queue_id < 0 || queue_id > 15) {\n\t\t\tpr_err(\"queue_id not within desired range\\n\");\n\t\t\treturn -EINVAL;\n\t\t}\n\n\t\tweight = edma_weight_assigned_to_q >> EDMA_WRR_VID_SCTL_SHIFT;\n\t\tif (weight < 0 || weight > 0xF) {\n\t\t\tpr_err(\"queue_id not within desired range\\n\");\n\t\t\treturn -EINVAL;\n\t\t}\n\n\t\tdata = weight << EDMA_WRR_SHIFT(queue_id);\n\n\t\treg_addr = EDMA_REG_WRR_CTRL_Q0_Q3 + (queue_id & ~0x3);\n\t\tedma_read_reg(reg_addr, &reg_data);\n\t\treg_data &= ~(1 << EDMA_WRR_SHIFT(queue_id));\n\t\tedma_write_reg(reg_addr, data | reg_data);\n\t}\n\n\treturn ret;\n}\n\nstatic int edma_queue_to_virtual_queue_map(struct ctl_table *table, int write,\n\t\t\t\t\t   void __user *buffer, size_t *lenp,\n\t\t\t\t\t   loff_t *ppos)\n{\n\tint ret, queue_id, virtual_qid;\n\tu32 reg_data, data, reg_addr;\n\n\tret = proc_dointvec(table, write, buffer, lenp, ppos);\n\tif (write) {\n\t\tqueue_id = edma_queue_to_virtual_q & EDMA_WRR_VID_SCTL_MASK;\n\t\tif (queue_id < 0 || queue_id > 15) {\n\t\t\tpr_err(\"queue_id not within desired range\\n\");\n\t\t\treturn -EINVAL;\n\t\t}\n\n\t\tvirtual_qid = edma_queue_to_virtual_q >>\n\t\t\tEDMA_WRR_VID_SCTL_SHIFT;\n\t\tif (virtual_qid < 0 || virtual_qid > 8) {\n\t\t\tpr_err(\"queue_id not within desired range\\n\");\n\t\t\treturn -EINVAL;\n\t\t}\n\n\t\tdata = virtual_qid << EDMA_VQ_ID_SHIFT(queue_id);\n\n\t\treg_addr = EDMA_REG_VQ_CTRL0 + (queue_id & ~0x3);\n\t\tedma_read_reg(reg_addr, &reg_data);\n\t\treg_data &= ~(1 << EDMA_VQ_ID_SHIFT(queue_id));\n\t\tedma_write_reg(reg_addr, data | reg_data);\n\t}\n\n\treturn ret;\n}\n\nstatic struct ctl_table edma_table[] = {\n\t{\n\t\t.procname       = \"default_lan_tag\",\n\t\t.data           = &edma_default_ltag,\n\t\t.maxlen         = sizeof(int),\n\t\t.mode           = 0644,\n\t\t.proc_handler   = edma_change_default_lan_vlan\n\t},\n\t{\n\t\t.procname       = \"default_wan_tag\",\n\t\t.data           = &edma_default_wtag,\n\t\t.maxlen         = sizeof(int),\n\t\t.mode           = 0644,\n\t\t.proc_handler   = edma_change_default_wan_vlan\n\t},\n\t{\n\t\t.procname       = \"weight_assigned_to_queues\",\n\t\t.data           = &edma_weight_assigned_to_q,\n\t\t.maxlen         = sizeof(int),\n\t\t.mode           = 0644,\n\t\t.proc_handler   = edma_weight_assigned_to_queues\n\t},\n\t{\n\t\t.procname       = \"queue_to_virtual_queue_map\",\n\t\t.data           = &edma_queue_to_virtual_q,\n\t\t.maxlen         = sizeof(int),\n\t\t.mode           = 0644,\n\t\t.proc_handler   = edma_queue_to_virtual_queue_map\n\t},\n\t{\n\t\t.procname       = \"enable_stp_rstp\",\n\t\t.data           = &edma_enable_rstp,\n\t\t.maxlen         = sizeof(int),\n\t\t.mode           = 0644,\n\t\t.proc_handler   = edma_enable_stp_rstp\n\t},\n\t{\n\t\t.procname       = \"athr_hdr_eth_type\",\n\t\t.data           = &edma_athr_hdr_eth_type,\n\t\t.maxlen         = sizeof(int),\n\t\t.mode           = 0644,\n\t\t.proc_handler   = edma_ath_hdr_eth_type\n\t},\n\t{\n\t\t.procname       = \"default_group1_vlan_tag\",\n\t\t.data           = &edma_default_group1_vtag,\n\t\t.maxlen         = sizeof(int),\n\t\t.mode           = 0644,\n\t\t.proc_handler   = edma_change_group1_vtag\n\t},\n\t{\n\t\t.procname       = \"default_group2_vlan_tag\",\n\t\t.data           = &edma_default_group2_vtag,\n\t\t.maxlen         = sizeof(int),\n\t\t.mode           = 0644,\n\t\t.proc_handler   = edma_change_group2_vtag\n\t},\n\t{\n\t\t.procname       = \"default_group3_vlan_tag\",\n\t\t.data           = &edma_default_group3_vtag,\n\t\t.maxlen         = sizeof(int),\n\t\t.mode           = 0644,\n\t\t.proc_handler   = edma_change_group3_vtag\n\t},\n\t{\n\t\t.procname       = \"default_group4_vlan_tag\",\n\t\t.data           = &edma_default_group4_vtag,\n\t\t.maxlen         = sizeof(int),\n\t\t.mode           = 0644,\n\t\t.proc_handler   = edma_change_group4_vtag\n\t},\n\t{\n\t\t.procname       = \"default_group5_vlan_tag\",\n\t\t.data           = &edma_default_group5_vtag,\n\t\t.maxlen         = sizeof(int),\n\t\t.mode           = 0644,\n\t\t.proc_handler   = edma_change_group5_vtag\n\t},\n\t{\n\t\t.procname       = \"edma_rss_idt_value\",\n\t\t.data           = &edma_rss_idt_val,\n\t\t.maxlen         = sizeof(int),\n\t\t.mode           = 0644,\n\t\t.proc_handler   = edma_set_rss_idt_value\n\t},\n\t{\n\t\t.procname       = \"edma_rss_idt_idx\",\n\t\t.data           = &edma_rss_idt_idx,\n\t\t.maxlen         = sizeof(int),\n\t\t.mode           = 0644,\n\t\t.proc_handler   = edma_set_rss_idt_idx\n\t},\n\t{}\n};\n\nstatic int ess_parse(struct edma_common_info *edma)\n{\n\tstruct device_node *switch_node;\n\tint ret = -EINVAL;\n\n\tswitch_node = of_find_node_by_name(NULL, \"ess-switch\");\n\tif (!switch_node) {\n\t\tpr_err(\"cannot find ess-switch node\\n\");\n\t\tgoto out;\n\t}\n\n\tedma->ess_hw_addr = of_io_request_and_map(switch_node,\n\t\t\t\t\t\t  0, KBUILD_MODNAME);\n\tif (!edma->ess_hw_addr) {\n\t\tpr_err(\"%s ioremap fail.\", __func__);\n\t\tgoto out;\n\t}\n\n\tedma->ess_clk = of_clk_get_by_name(switch_node, \"ess_clk\");\n\tret = clk_prepare_enable(edma->ess_clk);\nout:\n\tof_node_put(switch_node);\n\treturn ret;\n}\n\n/* edma_axi_netdev_ops\n *\tDescribe the operations supported by registered netdevices\n *\n * static const struct net_device_ops edma_axi_netdev_ops = {\n *\t.ndo_open               = edma_open,\n *\t.ndo_stop               = edma_close,\n *\t.ndo_start_xmit         = edma_xmit_frame,\n *\t.ndo_set_mac_address    = edma_set_mac_addr,\n * }\n */\nstatic const struct net_device_ops edma_axi_netdev_ops = {\n\t.ndo_open               = edma_open,\n\t.ndo_stop               = edma_close,\n\t.ndo_start_xmit         = edma_xmit,\n\t.ndo_set_mac_address    = edma_set_mac_addr,\n#ifdef CONFIG_RFS_ACCEL\n\t.ndo_rx_flow_steer      = edma_rx_flow_steer,\n\t.ndo_register_rfs_filter = edma_register_rfs_filter,\n\t.ndo_get_default_vlan_tag = edma_get_default_vlan_tag,\n#endif\n\t.ndo_get_stats          = edma_get_stats,\n};\n\n/* edma_axi_probe()\n *\tInitialise an adapter identified by a platform_device structure.\n *\n * The OS initialization, configuring of the adapter private structure,\n * and a hardware reset occur in the probe.\n */\nstatic int edma_axi_probe(struct platform_device *pdev)\n{\n\tstruct edma_common_info *edma_cinfo;\n\tstruct edma_hw *hw;\n\tstruct edma_adapter *adapter[EDMA_MAX_PORTID_SUPPORTED];\n\tstruct resource *res;\n\tstruct device_node *np = pdev->dev.of_node;\n\tstruct device_node *pnp;\n\tstruct device_node *mdio_node = NULL;\n\tstruct mii_bus *miibus = NULL;\n\tint i, j, k, err = 0;\n\tint portid_bmp;\n\tint idx = 0, idx_mac = 0;\n\n\tif (CONFIG_NR_CPUS != EDMA_CPU_CORES_SUPPORTED) {\n\t\tdev_err(&pdev->dev, \"Invalid CPU Cores\\n\");\n\t\treturn -EINVAL;\n\t}\n\n\tif ((num_rxq != 4) && (num_rxq != 8)) {\n\t\tdev_err(&pdev->dev, \"Invalid RX queue, edma probe failed\\n\");\n\t\treturn -EINVAL;\n\t}\n\tedma_cinfo = kzalloc(sizeof(struct edma_common_info), GFP_KERNEL);\n\tif (!edma_cinfo) {\n\t\terr = -ENOMEM;\n\t\tgoto err_alloc;\n\t}\n\n\tedma_cinfo->pdev = pdev;\n\n\tof_property_read_u32(np, \"qcom,num_gmac\", &edma_cinfo->num_gmac);\n\tif (edma_cinfo->num_gmac > EDMA_MAX_PORTID_SUPPORTED) {\n\t\tpr_err(\"Invalid DTSI Entry for qcom,num_gmac\\n\");\n\t\terr = -EINVAL;\n\t\tgoto err_cinfo;\n\t}\n\n\t/* Initialize the netdev array before allocation\n\t * to avoid double free\n\t */\n\tfor (i = 0 ; i < edma_cinfo->num_gmac ; i++)\n\t\tedma_netdev[i] = NULL;\n\n\tfor (i = 0 ; i < edma_cinfo->num_gmac ; i++) {\n\t\tedma_netdev[i] = alloc_etherdev_mqs(sizeof(struct edma_adapter),\n\t\t\tEDMA_NETDEV_TX_QUEUE, EDMA_NETDEV_RX_QUEUE);\n\n\t\tif (!edma_netdev[i]) {\n\t\t\tdev_err(&pdev->dev,\n\t\t\t\t\"net device alloc fails for index=%d\\n\", i);\n\t\t\terr = -ENODEV;\n\t\t\tgoto err_ioremap;\n\t\t}\n\n\t\tSET_NETDEV_DEV(edma_netdev[i], &pdev->dev);\n\t\tplatform_set_drvdata(pdev, edma_netdev[i]);\n\t\tedma_cinfo->netdev[i] = edma_netdev[i];\n\t}\n\n\t/* Fill ring details */\n\tedma_cinfo->num_tx_queues = EDMA_MAX_TRANSMIT_QUEUE;\n\tedma_cinfo->num_txq_per_core = (EDMA_MAX_TRANSMIT_QUEUE / 4);\n\tedma_cinfo->tx_ring_count = EDMA_TX_RING_SIZE;\n\n\t/* Update num rx queues based on module parameter */\n\tedma_cinfo->num_rx_queues = num_rxq;\n\tedma_cinfo->num_rxq_per_core = ((num_rxq == 4) ? 1 : 2);\n\n\tedma_cinfo->rx_ring_count = EDMA_RX_RING_SIZE;\n\n\thw = &edma_cinfo->hw;\n\n\t/* Fill HW defaults */\n\thw->tx_intr_mask = EDMA_TX_IMR_NORMAL_MASK;\n\thw->rx_intr_mask = EDMA_RX_IMR_NORMAL_MASK;\n\n\tof_property_read_u32(np, \"qcom,page-mode\", &edma_cinfo->page_mode);\n\tof_property_read_u32(np, \"qcom,rx_head_buf_size\",\n\t\t\t     &hw->rx_head_buff_size);\n\n\tif (overwrite_mode) {\n\t\tdev_info(&pdev->dev, \"page mode overwritten\");\n\t\tedma_cinfo->page_mode = page_mode;\n\t}\n\n\tif (jumbo_mru)\n\t\tedma_cinfo->fraglist_mode = 1;\n\n\tif (edma_cinfo->page_mode)\n\t\thw->rx_head_buff_size = EDMA_RX_HEAD_BUFF_SIZE_JUMBO;\n\telse if (edma_cinfo->fraglist_mode)\n\t\thw->rx_head_buff_size = jumbo_mru;\n\telse if (!hw->rx_head_buff_size)\n\t\thw->rx_head_buff_size = EDMA_RX_HEAD_BUFF_SIZE;\n\n\thw->misc_intr_mask = 0;\n\thw->wol_intr_mask = 0;\n\n\thw->intr_clear_type = EDMA_INTR_CLEAR_TYPE;\n\thw->intr_sw_idx_w = EDMA_INTR_SW_IDX_W_TYPE;\n\n\t/* configure RSS type to the different protocol that can be\n\t * supported\n\t */\n\thw->rss_type = EDMA_RSS_TYPE_IPV4TCP | EDMA_RSS_TYPE_IPV6_TCP |\n\t\tEDMA_RSS_TYPE_IPV4_UDP | EDMA_RSS_TYPE_IPV6UDP |\n\t\tEDMA_RSS_TYPE_IPV4 | EDMA_RSS_TYPE_IPV6;\n\n\tres = platform_get_resource(pdev, IORESOURCE_MEM, 0);\n\n\tedma_cinfo->hw.hw_addr = devm_ioremap_resource(&pdev->dev, res);\n\tif (IS_ERR(edma_cinfo->hw.hw_addr)) {\n\t\terr = PTR_ERR(edma_cinfo->hw.hw_addr);\n\t\tgoto err_ioremap;\n\t}\n\n\tedma_hw_addr = (u32)edma_cinfo->hw.hw_addr;\n\n\t/* Parse tx queue interrupt number from device tree */\n\tfor (i = 0; i < edma_cinfo->num_tx_queues; i++)\n\t\tedma_cinfo->tx_irq[i] = platform_get_irq(pdev, i);\n\n\t/* Parse rx queue interrupt number from device tree\n\t * Here we are setting j to point to the point where we\n\t * left tx interrupt parsing(i.e 16) and run run the loop\n\t * from 0 to 7 to parse rx interrupt number.\n\t */\n\tfor (i = 0, j = edma_cinfo->num_tx_queues, k = 0;\n\t\t\ti < edma_cinfo->num_rx_queues; i++) {\n\t\tedma_cinfo->rx_irq[k] = platform_get_irq(pdev, j);\n\t\tk += ((num_rxq == 4) ?  2 : 1);\n\t\tj += ((num_rxq == 4) ?  2 : 1);\n\t}\n\n\tedma_cinfo->rx_head_buffer_len = edma_cinfo->hw.rx_head_buff_size;\n\tedma_cinfo->rx_page_buffer_len = PAGE_SIZE;\n\n\terr = edma_alloc_queues_tx(edma_cinfo);\n\tif (err) {\n\t\tdev_err(&pdev->dev, \"Allocation of TX queue failed\\n\");\n\t\tgoto err_tx_qinit;\n\t}\n\n\terr = edma_alloc_queues_rx(edma_cinfo);\n\tif (err) {\n\t\tdev_err(&pdev->dev, \"Allocation of RX queue failed\\n\");\n\t\tgoto err_rx_qinit;\n\t}\n\n\terr = edma_alloc_tx_rings(edma_cinfo);\n\tif (err) {\n\t\tdev_err(&pdev->dev, \"Allocation of TX resources failed\\n\");\n\t\tgoto err_tx_rinit;\n\t}\n\n\terr = edma_alloc_rx_rings(edma_cinfo);\n\tif (err) {\n\t\tdev_err(&pdev->dev, \"Allocation of RX resources failed\\n\");\n\t\tgoto err_rx_rinit;\n\t}\n\n\t/* Initialize netdev and netdev bitmap for transmit descriptor rings */\n\tfor (i = 0; i < edma_cinfo->num_tx_queues; i++) {\n\t\tstruct edma_tx_desc_ring *etdr =  edma_cinfo->tpd_ring[i];\n\t\tint j;\n\n\t\tetdr->netdev_bmp = 0;\n\t\tfor (j = 0; j < EDMA_MAX_NETDEV_PER_QUEUE; j++) {\n\t\t\tetdr->netdev[j] = NULL;\n\t\t\tetdr->nq[j] = NULL;\n\t\t}\n\t}\n\n\tif (of_property_read_bool(np, \"qcom,mdio_supported\")) {\n\t\tmdio_node = of_find_compatible_node(NULL, NULL,\n\t\t\t\t\t\t    \"qcom,ipq4019-mdio\");\n\t\tif (!mdio_node) {\n\t\t\tdev_err(&pdev->dev, \"cannot find mdio node by phandle\");\n\t\t\terr = -EIO;\n\t\t\tgoto err_mdiobus_init_fail;\n\t\t}\n\n\t\tmiibus = of_mdio_find_bus(mdio_node);\n\t\tif (!miibus)\n\t\t\treturn -EINVAL;\n\t}\n\n\tif (of_property_read_bool(np, \"qcom,single-phy\") &&\n\t    edma_cinfo->num_gmac == 1) {\n\t\terr = ess_parse(edma_cinfo);\n\t\tif (!err)\n\t\t\terr = ess_reset(edma_cinfo);\n\t\tif (err)\n\t\t\tgoto err_single_phy_init;\n\t\telse\n\t\t\tedma_cinfo->is_single_phy = true;\n\t}\n\n\tfor_each_available_child_of_node(np, pnp) {\n\t\t/* this check is needed if parent and daughter dts have\n\t\t * different number of gmac nodes\n\t\t */\n\t\tif (idx_mac == edma_cinfo->num_gmac) {\n\t\t\tof_node_put(np);\n\t\t\tbreak;\n\t\t}\n\n\t\tof_get_mac_address(pnp, edma_netdev[idx_mac]->dev_addr);\n\n\t\tidx_mac++;\n\t}\n\n\t/* Populate the adapter structure register the netdevice */\n\tfor (i = 0; i < edma_cinfo->num_gmac; i++) {\n\t\tint k, m;\n\n\t\tadapter[i] = netdev_priv(edma_netdev[i]);\n\t\tadapter[i]->netdev = edma_netdev[i];\n\t\tadapter[i]->pdev = pdev;\n\t\tfor (j = 0; j < CONFIG_NR_CPUS; j++) {\n\t\t\tm = i % 2;\n\t\t\tadapter[i]->tx_start_offset[j] =\n\t\t\t\t((j << EDMA_TX_CPU_START_SHIFT) + (m << 1));\n\t\t\t/* Share the queues with available net-devices.\n\t\t\t * For instance , with 5 net-devices\n\t\t\t * eth0/eth2/eth4 will share q0,q1,q4,q5,q8,q9,q12,q13\n\t\t\t * and eth1/eth3 will get the remaining.\n\t\t\t */\n\t\t\tfor (k = adapter[i]->tx_start_offset[j]; k <\n\t\t\t     (adapter[i]->tx_start_offset[j] + 2); k++) {\n\t\t\t\tif (edma_fill_netdev(edma_cinfo, k, i, j)) {\n\t\t\t\t\tpr_err(\"Netdev overflow Error\\n\");\n\t\t\t\t\tgoto err_register;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n\t\tadapter[i]->edma_cinfo = edma_cinfo;\n\t\tedma_netdev[i]->netdev_ops = &edma_axi_netdev_ops;\n\t\tedma_netdev[i]->max_mtu = 9000;\n\t\tedma_netdev[i]->features = NETIF_F_HW_CSUM | NETIF_F_RXCSUM\n\t\t\t\t      | NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_SG |\n\t\t\t\t      NETIF_F_TSO | NETIF_F_GRO | NETIF_F_HW_VLAN_CTAG_TX;\n\t\tedma_netdev[i]->hw_features = NETIF_F_HW_CSUM | NETIF_F_RXCSUM |\n\t\t\t\tNETIF_F_HW_VLAN_CTAG_RX\n\t\t\t\t| NETIF_F_SG | NETIF_F_TSO | NETIF_F_GRO;\n\t\tedma_netdev[i]->vlan_features = NETIF_F_HW_CSUM | NETIF_F_SG |\n\t\t\t\t\t   NETIF_F_TSO | NETIF_F_GRO;\n\t\tedma_netdev[i]->wanted_features = NETIF_F_HW_CSUM | NETIF_F_SG |\n\t\t\t\t\t     NETIF_F_TSO | NETIF_F_GRO;\n\n#ifdef CONFIG_RFS_ACCEL\n\t\tedma_netdev[i]->features |=  NETIF_F_NTUPLE | NETIF_F_RXHASH;\n\t\tedma_netdev[i]->hw_features |=  NETIF_F_NTUPLE | NETIF_F_RXHASH;\n\t\tedma_netdev[i]->vlan_features |= NETIF_F_NTUPLE | NETIF_F_RXHASH;\n\t\tedma_netdev[i]->wanted_features |= NETIF_F_NTUPLE | NETIF_F_RXHASH;\n#endif\n\t\tedma_set_ethtool_ops(edma_netdev[i]);\n\n\t\t/* This just fill in some default MAC address\n\t\t */\n\t\tif (!is_valid_ether_addr(edma_netdev[i]->dev_addr)) {\n\t\t\trandom_ether_addr(edma_netdev[i]->dev_addr);\n\t\t\tpr_info(\"EDMA using MAC@ - using\");\n\t\t\tpr_info(\"%02x:%02x:%02x:%02x:%02x:%02x\\n\",\n\t\t\t*(edma_netdev[i]->dev_addr),\n\t\t\t*(edma_netdev[i]->dev_addr + 1),\n\t\t\t*(edma_netdev[i]->dev_addr + 2),\n\t\t\t*(edma_netdev[i]->dev_addr + 3),\n\t\t\t*(edma_netdev[i]->dev_addr + 4),\n\t\t\t*(edma_netdev[i]->dev_addr + 5));\n\t\t}\n\n\t\terr = register_netdev(edma_netdev[i]);\n\t\tif (err)\n\t\t\tgoto err_register;\n\n\t\t/* carrier off reporting is important to\n\t\t * ethtool even BEFORE open\n\t\t */\n\t\tnetif_carrier_off(edma_netdev[i]);\n\n\t\t/* Allocate reverse irq cpu mapping structure for\n\t\t* receive queues\n\t\t*/\n#ifdef CONFIG_RFS_ACCEL\n\t\tedma_netdev[i]->rx_cpu_rmap =\n\t\t\talloc_irq_cpu_rmap(EDMA_NETDEV_RX_QUEUE);\n\t\tif (!edma_netdev[i]->rx_cpu_rmap) {\n\t\t\terr = -ENOMEM;\n\t\t\tgoto err_rmap_alloc_fail;\n\t\t}\n#endif\n\t}\n\n\tfor (i = 0; i < EDMA_MAX_PORTID_BITMAP_INDEX; i++)\n\t\tedma_cinfo->portid_netdev_lookup_tbl[i] = NULL;\n\n\tfor_each_available_child_of_node(np, pnp) {\n\t\tconst uint32_t *vlan_tag = NULL;\n\t\tint len;\n\n\t\t/* this check is needed if parent and daughter dts have\n\t\t * different number of gmac nodes\n\t\t */\n\t\tif (idx == edma_cinfo->num_gmac)\n\t\t\tbreak;\n\n\t\t/* Populate port-id to netdev lookup table */\n\t\tvlan_tag = of_get_property(pnp, \"vlan_tag\", &len);\n\t\tif (!vlan_tag) {\n\t\t\tpr_err(\"Vlan tag parsing Failed.\\n\");\n\t\t\tgoto err_rmap_alloc_fail;\n\t\t}\n\n\t\tadapter[idx]->default_vlan_tag = of_read_number(vlan_tag, 1);\n\t\tvlan_tag++;\n\t\tportid_bmp = of_read_number(vlan_tag, 1);\n\t\tadapter[idx]->dp_bitmap = portid_bmp;\n\n\t\tportid_bmp = portid_bmp >> 1; /* We ignore CPU Port bit 0 */\n\t\twhile (portid_bmp) {\n\t\t\tint port_bit = ffs(portid_bmp);\n\n\t\t\tif (port_bit > EDMA_MAX_PORTID_SUPPORTED)\n\t\t\t\tgoto err_rmap_alloc_fail;\n\t\t\tedma_cinfo->portid_netdev_lookup_tbl[port_bit] =\n\t\t\t\tedma_netdev[idx];\n\t\t\tportid_bmp &= ~(1 << (port_bit - 1));\n\t\t}\n\n\t\tif (!of_property_read_u32(pnp, \"qcom,poll_required\",\n\t\t\t\t\t  &adapter[idx]->poll_required)) {\n\t\t\tif (adapter[idx]->poll_required) {\n\t\t\t\tof_property_read_u32(pnp, \"qcom,phy_mdio_addr\",\n\t\t\t\t\t\t     &adapter[idx]->phy_mdio_addr);\n\t\t\t\tof_property_read_u32(pnp, \"qcom,forced_speed\",\n\t\t\t\t\t\t     &adapter[idx]->forced_speed);\n\t\t\t\tof_property_read_u32(pnp, \"qcom,forced_duplex\",\n\t\t\t\t\t\t     &adapter[idx]->forced_duplex);\n\n\t\t\t\t/* create a phyid using MDIO bus id\n\t\t\t\t * and MDIO bus address\n\t\t\t\t */\n\t\t\t\tsnprintf(adapter[idx]->phy_id,\n\t\t\t\t\t MII_BUS_ID_SIZE + 3, PHY_ID_FMT,\n\t\t\t\t\t miibus->id,\n\t\t\t\t\t adapter[idx]->phy_mdio_addr);\n\t\t\t}\n\t\t} else {\n\t\t\tadapter[idx]->poll_required = 0;\n\t\t\tadapter[idx]->forced_speed = SPEED_1000;\n\t\t\tadapter[idx]->forced_duplex = DUPLEX_FULL;\n\t\t}\n\n\t\tidx++;\n\t}\n\n\tedma_cinfo->edma_ctl_table_hdr = register_net_sysctl(&init_net,\n\t\t\t\t\t\t\t     \"net/edma\",\n\t\t\t\t\t\t\t     edma_table);\n\tif (!edma_cinfo->edma_ctl_table_hdr) {\n\t\tdev_err(&pdev->dev, \"edma sysctl table hdr not registered\\n\");\n\t\tgoto err_unregister_sysctl_tbl;\n\t}\n\n\t/* Disable all 16 Tx and 8 rx irqs */\n\tedma_irq_disable(edma_cinfo);\n\n\terr = edma_reset(edma_cinfo);\n\tif (err) {\n\t\terr = -EIO;\n\t\tgoto err_reset;\n\t}\n\n\t/* populate per_core_info, do a napi_Add, request 16 TX irqs,\n\t * 8 RX irqs, do a napi enable\n\t */\n\tfor (i = 0; i < CONFIG_NR_CPUS; i++) {\n\t\tu8 rx_start;\n\n\t\tedma_cinfo->edma_percpu_info[i].napi.state = 0;\n\n\t\tnetif_napi_add(edma_netdev[0],\n\t\t\t       &edma_cinfo->edma_percpu_info[i].napi,\n\t\t\t       edma_poll, 64);\n\t\tnapi_enable(&edma_cinfo->edma_percpu_info[i].napi);\n\t\tedma_cinfo->edma_percpu_info[i].tx_mask = tx_mask[i];\n\t\tedma_cinfo->edma_percpu_info[i].rx_mask = EDMA_RX_PER_CPU_MASK\n\t\t\t\t<< (i << EDMA_RX_PER_CPU_MASK_SHIFT);\n\t\tedma_cinfo->edma_percpu_info[i].tx_start = tx_start[i];\n\t\tedma_cinfo->edma_percpu_info[i].rx_start =\n\t\t\ti << EDMA_RX_CPU_START_SHIFT;\n\t\trx_start = i << EDMA_RX_CPU_START_SHIFT;\n\t\tedma_cinfo->edma_percpu_info[i].tx_status = 0;\n\t\tedma_cinfo->edma_percpu_info[i].rx_status = 0;\n\t\tedma_cinfo->edma_percpu_info[i].edma_cinfo = edma_cinfo;\n\n\t\t/* Request irq per core */\n\t\tfor (j = edma_cinfo->edma_percpu_info[i].tx_start;\n\t\t     j < tx_start[i] + 4; j++) {\n\t\t\tsprintf(&edma_tx_irq[j][0], \"edma_eth_tx%d\", j);\n\t\t\terr = request_irq(edma_cinfo->tx_irq[j],\n\t\t\t\t\t  edma_interrupt,\n\t\t\t\t\t  0,\n\t\t\t\t\t  &edma_tx_irq[j][0],\n\t\t\t\t\t  &edma_cinfo->edma_percpu_info[i]);\n\t\t\tif (err)\n\t\t\t\tgoto err_reset;\n\t\t}\n\n\t\tfor (j = edma_cinfo->edma_percpu_info[i].rx_start;\n\t\t     j < (rx_start +\n\t\t     ((edma_cinfo->num_rx_queues == 4) ? 1 : 2));\n\t\t     j++) {\n\t\t\tsprintf(&edma_rx_irq[j][0], \"edma_eth_rx%d\", j);\n\t\t\terr = request_irq(edma_cinfo->rx_irq[j],\n\t\t\t\t\t  edma_interrupt,\n\t\t\t\t\t  0,\n\t\t\t\t\t  &edma_rx_irq[j][0],\n\t\t\t\t\t  &edma_cinfo->edma_percpu_info[i]);\n\t\t\tif (err)\n\t\t\t\tgoto err_reset;\n\t\t}\n\n#ifdef CONFIG_RFS_ACCEL\n\t\tfor (j = edma_cinfo->edma_percpu_info[i].rx_start;\n\t\t     j < rx_start + 2; j += 2) {\n\t\t\terr = irq_cpu_rmap_add(edma_netdev[0]->rx_cpu_rmap,\n\t\t\t\t\t       edma_cinfo->rx_irq[j]);\n\t\t\tif (err)\n\t\t\t\tgoto err_rmap_add_fail;\n\t\t}\n#endif\n\t}\n\n\t/* Used to clear interrupt status, allocate rx buffer,\n\t * configure edma descriptors registers\n\t */\n\terr = edma_configure(edma_cinfo);\n\tif (err) {\n\t\terr = -EIO;\n\t\tgoto err_configure;\n\t}\n\n\t/* Configure RSS indirection table.\n\t * 128 hash will be configured in the following\n\t * pattern: hash{0,1,2,3} = {Q0,Q2,Q4,Q6} respectively\n\t * and so on\n\t */\n\tfor (i = 0; i < EDMA_NUM_IDT; i++)\n\t\tedma_write_reg(EDMA_REG_RSS_IDT(i), EDMA_RSS_IDT_VALUE);\n\n\t/* Configure load balance mapping table.\n\t * 4 table entry will be configured according to the\n\t * following pattern: load_balance{0,1,2,3} = {Q0,Q1,Q3,Q4}\n\t * respectively.\n\t */\n\tedma_write_reg(EDMA_REG_LB_RING, EDMA_LB_REG_VALUE);\n\n\t/* Configure Virtual queue for Tx rings\n\t * User can also change this value runtime through\n\t * a sysctl\n\t */\n\tedma_write_reg(EDMA_REG_VQ_CTRL0, EDMA_VQ_REG_VALUE);\n\tedma_write_reg(EDMA_REG_VQ_CTRL1, EDMA_VQ_REG_VALUE);\n\n\t/* Configure Max AXI Burst write size to 128 bytes*/\n\tedma_write_reg(EDMA_REG_AXIW_CTRL_MAXWRSIZE,\n\t\t       EDMA_AXIW_MAXWRSIZE_VALUE);\n\n\t/* Enable All 16 tx and 8 rx irq mask */\n\tedma_irq_enable(edma_cinfo);\n\tedma_enable_tx_ctrl(&edma_cinfo->hw);\n\tedma_enable_rx_ctrl(&edma_cinfo->hw);\n\n\tfor (i = 0; i < edma_cinfo->num_gmac; i++) {\n\t\tif (adapter[i]->poll_required) {\n#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,5,0)\n\t\t\tphy_interface_t phy_mode;\n\n\t\t\terr = of_get_phy_mode(np, &phy_mode);\n\t\t\tif (err)\n\t\t\t\tphy_mode = PHY_INTERFACE_MODE_SGMII;\n#else\n\t\t\tint phy_mode = of_get_phy_mode(np);\n\t\t\tif (phy_mode < 0)\n\t\t\t\tphy_mode = PHY_INTERFACE_MODE_SGMII;\n#endif\n\t\t\tadapter[i]->phydev =\n\t\t\t\tphy_connect(edma_netdev[i],\n\t\t\t\t\t    (const char *)adapter[i]->phy_id,\n\t\t\t\t\t    &edma_adjust_link,\n\t\t\t\t\t    phy_mode);\n\t\t\tif (IS_ERR(adapter[i]->phydev)) {\n\t\t\t\tdev_dbg(&pdev->dev, \"PHY attach FAIL\");\n\t\t\t\terr = -EIO;\n\t\t\t\tgoto edma_phy_attach_fail;\n\t\t\t} else {\n\t\t\t\tlinkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT,\n\t\t\t\t\t\t adapter[i]->phydev->advertising);\n\t\t\t\tlinkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT,\n\t\t\t\t\t\t adapter[i]->phydev->advertising);\n\t\t\t\tlinkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT,\n\t\t\t\t\t\t adapter[i]->phydev->supported);\n\t\t\t\tlinkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT,\n\t\t\t\t\t\t adapter[i]->phydev->supported);\n\t\t\t}\n\t\t} else {\n\t\t\tadapter[i]->phydev = NULL;\n\t\t}\n\t}\n\n\tspin_lock_init(&edma_cinfo->stats_lock);\n\n\ttimer_setup(&edma_cinfo->edma_stats_timer, edma_statistics_timer, 0);\n\tmod_timer(&edma_cinfo->edma_stats_timer, jiffies + 1*HZ);\n\n\treturn 0;\n\nedma_phy_attach_fail:\n\tmiibus = NULL;\nerr_configure:\n#ifdef CONFIG_RFS_ACCEL\n\tfor (i = 0; i < edma_cinfo->num_gmac; i++) {\n\t\tfree_irq_cpu_rmap(adapter[i]->netdev->rx_cpu_rmap);\n\t\tadapter[i]->netdev->rx_cpu_rmap = NULL;\n\t}\n#endif\nerr_rmap_add_fail:\n\tedma_free_irqs(adapter[0]);\n\tfor (i = 0; i < CONFIG_NR_CPUS; i++)\n\t\tnapi_disable(&edma_cinfo->edma_percpu_info[i].napi);\nerr_reset:\nerr_unregister_sysctl_tbl:\nerr_rmap_alloc_fail:\n\tfor (i = 0; i < edma_cinfo->num_gmac; i++)\n\t\tunregister_netdev(edma_netdev[i]);\nerr_register:\nerr_single_phy_init:\n\tiounmap(edma_cinfo->ess_hw_addr);\n\tclk_disable_unprepare(edma_cinfo->ess_clk);\nerr_mdiobus_init_fail:\n\tedma_free_rx_rings(edma_cinfo);\nerr_rx_rinit:\n\tedma_free_tx_rings(edma_cinfo);\nerr_tx_rinit:\n\tedma_free_queues(edma_cinfo);\nerr_rx_qinit:\nerr_tx_qinit:\n\tiounmap(edma_cinfo->hw.hw_addr);\nerr_ioremap:\n\tfor (i = 0; i < edma_cinfo->num_gmac; i++) {\n\t\tif (edma_netdev[i])\n\t\t\tfree_netdev(edma_netdev[i]);\n\t}\nerr_cinfo:\n\tkfree(edma_cinfo);\nerr_alloc:\n\treturn err;\n}\n\n/* edma_axi_remove()\n *\tDevice Removal Routine\n *\n * edma_axi_remove is called by the platform subsystem to alert the driver\n * that it should release a platform device.\n */\nstatic int edma_axi_remove(struct platform_device *pdev)\n{\n\tstruct edma_adapter *adapter = netdev_priv(edma_netdev[0]);\n\tstruct edma_common_info *edma_cinfo = adapter->edma_cinfo;\n\tstruct edma_hw *hw = &edma_cinfo->hw;\n\tint i;\n\n\tfor (i = 0; i < edma_cinfo->num_gmac; i++)\n\t\tunregister_netdev(edma_netdev[i]);\n\n\tedma_stop_rx_tx(hw);\n\tfor (i = 0; i < CONFIG_NR_CPUS; i++)\n\t\tnapi_disable(&edma_cinfo->edma_percpu_info[i].napi);\n\n\tedma_irq_disable(edma_cinfo);\n\tedma_write_reg(EDMA_REG_RX_ISR, 0xff);\n\tedma_write_reg(EDMA_REG_TX_ISR, 0xffff);\n#ifdef CONFIG_RFS_ACCEL\n\tfor (i = 0; i < edma_cinfo->num_gmac; i++) {\n\t\tfree_irq_cpu_rmap(edma_netdev[i]->rx_cpu_rmap);\n\t\tedma_netdev[i]->rx_cpu_rmap = NULL;\n\t}\n#endif\n\n\tfor (i = 0; i < edma_cinfo->num_gmac; i++) {\n\t\tstruct edma_adapter *adapter = netdev_priv(edma_netdev[i]);\n\n\t\tif (adapter->phydev)\n\t\t\tphy_disconnect(adapter->phydev);\n\t}\n\n\tdel_timer_sync(&edma_cinfo->edma_stats_timer);\n\tedma_free_irqs(adapter);\n\tunregister_net_sysctl_table(edma_cinfo->edma_ctl_table_hdr);\n\tiounmap(edma_cinfo->ess_hw_addr);\n\tclk_disable_unprepare(edma_cinfo->ess_clk);\n\tedma_free_tx_resources(edma_cinfo);\n\tedma_free_rx_resources(edma_cinfo);\n\tedma_free_tx_rings(edma_cinfo);\n\tedma_free_rx_rings(edma_cinfo);\n\tedma_free_queues(edma_cinfo);\n\tfor (i = 0; i < edma_cinfo->num_gmac; i++)\n\t\tfree_netdev(edma_netdev[i]);\n\n\tkfree(edma_cinfo);\n\n\treturn 0;\n}\n\nstatic const struct of_device_id edma_of_mtable[] = {\n\t{.compatible = \"qcom,ess-edma\" },\n\t{}\n};\nMODULE_DEVICE_TABLE(of, edma_of_mtable);\n\nstatic struct platform_driver edma_axi_driver = {\n\t.driver = {\n\t\t.name    = edma_axi_driver_name,\n\t\t.of_match_table = edma_of_mtable,\n\t},\n\t.probe    = edma_axi_probe,\n\t.remove   = edma_axi_remove,\n};\n\nmodule_platform_driver(edma_axi_driver);\n\nMODULE_AUTHOR(\"Qualcomm Atheros Inc\");\nMODULE_DESCRIPTION(\"QCA ESS EDMA driver\");\nMODULE_LICENSE(\"GPL\");\n"
  },
  {
    "path": "target/linux/ipq40xx/files/drivers/net/ethernet/qualcomm/essedma/edma_ethtool.c",
    "content": "/*\n * Copyright (c) 2015 - 2016, The Linux Foundation. All rights reserved.\n *\n * Permission to use, copy, modify, and/or distribute this software for\n * any purpose with or without fee is hereby granted, provided that the\n * above copyright notice and this permission notice appear in all copies.\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT\n * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n */\n\n#include <linux/ethtool.h>\n#include <linux/netdevice.h>\n#include <linux/string.h>\n#include <linux/version.h>\n#include \"edma.h\"\n\nstruct edma_ethtool_stats {\n\tuint8_t stat_string[ETH_GSTRING_LEN];\n\tuint32_t stat_offset;\n};\n\n#define EDMA_STAT(m)    offsetof(struct edma_ethtool_statistics, m)\n#define DRVINFO_LEN\t32\n\n/* Array of strings describing statistics\n */\nstatic const struct edma_ethtool_stats edma_gstrings_stats[] = {\n\t{\"tx_q0_pkt\", EDMA_STAT(tx_q0_pkt)},\n\t{\"tx_q1_pkt\", EDMA_STAT(tx_q1_pkt)},\n\t{\"tx_q2_pkt\", EDMA_STAT(tx_q2_pkt)},\n\t{\"tx_q3_pkt\", EDMA_STAT(tx_q3_pkt)},\n\t{\"tx_q4_pkt\", EDMA_STAT(tx_q4_pkt)},\n\t{\"tx_q5_pkt\", EDMA_STAT(tx_q5_pkt)},\n\t{\"tx_q6_pkt\", EDMA_STAT(tx_q6_pkt)},\n\t{\"tx_q7_pkt\", EDMA_STAT(tx_q7_pkt)},\n\t{\"tx_q8_pkt\", EDMA_STAT(tx_q8_pkt)},\n\t{\"tx_q9_pkt\", EDMA_STAT(tx_q9_pkt)},\n\t{\"tx_q10_pkt\", EDMA_STAT(tx_q10_pkt)},\n\t{\"tx_q11_pkt\", EDMA_STAT(tx_q11_pkt)},\n\t{\"tx_q12_pkt\", EDMA_STAT(tx_q12_pkt)},\n\t{\"tx_q13_pkt\", EDMA_STAT(tx_q13_pkt)},\n\t{\"tx_q14_pkt\", EDMA_STAT(tx_q14_pkt)},\n\t{\"tx_q15_pkt\", EDMA_STAT(tx_q15_pkt)},\n\t{\"tx_q0_byte\", EDMA_STAT(tx_q0_byte)},\n\t{\"tx_q1_byte\", EDMA_STAT(tx_q1_byte)},\n\t{\"tx_q2_byte\", EDMA_STAT(tx_q2_byte)},\n\t{\"tx_q3_byte\", EDMA_STAT(tx_q3_byte)},\n\t{\"tx_q4_byte\", EDMA_STAT(tx_q4_byte)},\n\t{\"tx_q5_byte\", EDMA_STAT(tx_q5_byte)},\n\t{\"tx_q6_byte\", EDMA_STAT(tx_q6_byte)},\n\t{\"tx_q7_byte\", EDMA_STAT(tx_q7_byte)},\n\t{\"tx_q8_byte\", EDMA_STAT(tx_q8_byte)},\n\t{\"tx_q9_byte\", EDMA_STAT(tx_q9_byte)},\n\t{\"tx_q10_byte\", EDMA_STAT(tx_q10_byte)},\n\t{\"tx_q11_byte\", EDMA_STAT(tx_q11_byte)},\n\t{\"tx_q12_byte\", EDMA_STAT(tx_q12_byte)},\n\t{\"tx_q13_byte\", EDMA_STAT(tx_q13_byte)},\n\t{\"tx_q14_byte\", EDMA_STAT(tx_q14_byte)},\n\t{\"tx_q15_byte\", EDMA_STAT(tx_q15_byte)},\n\t{\"rx_q0_pkt\", EDMA_STAT(rx_q0_pkt)},\n\t{\"rx_q1_pkt\", EDMA_STAT(rx_q1_pkt)},\n\t{\"rx_q2_pkt\", EDMA_STAT(rx_q2_pkt)},\n\t{\"rx_q3_pkt\", EDMA_STAT(rx_q3_pkt)},\n\t{\"rx_q4_pkt\", EDMA_STAT(rx_q4_pkt)},\n\t{\"rx_q5_pkt\", EDMA_STAT(rx_q5_pkt)},\n\t{\"rx_q6_pkt\", EDMA_STAT(rx_q6_pkt)},\n\t{\"rx_q7_pkt\", EDMA_STAT(rx_q7_pkt)},\n\t{\"rx_q0_byte\", EDMA_STAT(rx_q0_byte)},\n\t{\"rx_q1_byte\", EDMA_STAT(rx_q1_byte)},\n\t{\"rx_q2_byte\", EDMA_STAT(rx_q2_byte)},\n\t{\"rx_q3_byte\", EDMA_STAT(rx_q3_byte)},\n\t{\"rx_q4_byte\", EDMA_STAT(rx_q4_byte)},\n\t{\"rx_q5_byte\", EDMA_STAT(rx_q5_byte)},\n\t{\"rx_q6_byte\", EDMA_STAT(rx_q6_byte)},\n\t{\"rx_q7_byte\", EDMA_STAT(rx_q7_byte)},\n\t{\"tx_desc_error\", EDMA_STAT(tx_desc_error)},\n\t{\"rx_alloc_fail_ctr\", EDMA_STAT(rx_alloc_fail_ctr)},\n};\n\n#define EDMA_STATS_LEN ARRAY_SIZE(edma_gstrings_stats)\n\n/* edma_get_strset_count()\n *\tGet strset count\n */\nstatic int edma_get_strset_count(struct net_device *netdev,\n\t\t\t\t int sset)\n{\n\tswitch (sset) {\n\tcase ETH_SS_STATS:\n\t\treturn EDMA_STATS_LEN;\n\tdefault:\n\t\tnetdev_dbg(netdev, \"%s: Invalid string set\", __func__);\n\t\treturn -EOPNOTSUPP;\n\t}\n}\n\n\n/* edma_get_strings()\n *\tget stats string\n */\nstatic void edma_get_strings(struct net_device *netdev, uint32_t stringset,\n\t\t\t     uint8_t *data)\n{\n\tuint8_t *p = data;\n\tuint32_t i;\n\n\tswitch (stringset) {\n\tcase ETH_SS_STATS:\n\t\tfor (i = 0; i < EDMA_STATS_LEN; i++) {\n\t\t\tmemcpy(p, edma_gstrings_stats[i].stat_string,\n\t\t\t\tmin((size_t)ETH_GSTRING_LEN,\n\t\t\t\t    strlen(edma_gstrings_stats[i].stat_string)\n\t\t\t\t    + 1));\n\t\t\tp += ETH_GSTRING_LEN;\n\t\t}\n\t\tbreak;\n\t}\n}\n\n/* edma_get_ethtool_stats()\n *\tGet ethtool statistics\n */\nstatic void edma_get_ethtool_stats(struct net_device *netdev,\n\t\t\t\t   struct ethtool_stats *stats, uint64_t *data)\n{\n\tstruct edma_adapter *adapter = netdev_priv(netdev);\n\tstruct edma_common_info *edma_cinfo = adapter->edma_cinfo;\n\tint i;\n\tuint8_t *p = NULL;\n\n\tedma_read_append_stats(edma_cinfo);\n\n\tfor(i = 0; i < EDMA_STATS_LEN; i++) {\n\t\tp = (uint8_t *)&(edma_cinfo->edma_ethstats) +\n\t\t\tedma_gstrings_stats[i].stat_offset;\n\t\tdata[i] = *(uint32_t *)p;\n\t}\n}\n\n/* edma_get_drvinfo()\n *\tget edma driver info\n */\nstatic void edma_get_drvinfo(struct net_device *dev,\n\t\t\t     struct ethtool_drvinfo *info)\n{\n\tstrlcpy(info->driver, \"ess_edma\", DRVINFO_LEN);\n\tstrlcpy(info->bus_info, \"axi\", ETHTOOL_BUSINFO_LEN);\n}\n\n/* edma_nway_reset()\n *\tReset the phy, if available.\n */\nstatic int edma_nway_reset(struct net_device *netdev)\n{\n\treturn -EINVAL;\n}\n\n/* edma_get_wol()\n *\tget wake on lan info\n */\nstatic void edma_get_wol(struct net_device *netdev,\n\t\t\t struct ethtool_wolinfo *wol)\n{\n\twol->supported = 0;\n\twol->wolopts = 0;\n}\n\n/* edma_get_msglevel()\n *\tget message level.\n */\nstatic uint32_t edma_get_msglevel(struct net_device *netdev)\n{\n\treturn 0;\n}\n\n/* edma_get_settings()\n *\tGet edma settings\n */\nstatic int edma_get_settings(struct net_device *netdev,\n\t\t\t     struct ethtool_link_ksettings *cmd)\n{\n\tstruct edma_adapter *adapter = netdev_priv(netdev);\n\n\tif (adapter->poll_required) {\n\t\tif ((adapter->forced_speed != SPEED_UNKNOWN)\n\t\t\t&& !(adapter->poll_required))\n\t\t\treturn -EPERM;\n\n\t\tphy_ethtool_ksettings_get(adapter->phydev, cmd);\n\t\tif (linkmode_test_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, adapter->phydev->advertising))\n\t\t\tcmd->base.port = PORT_FIBRE;\n\t\telse\n\t\t\tcmd->base.port = PORT_TP;\n\t} else {\n\t\t/* If the speed/duplex for this GMAC is forced and we\n\t\t * are not polling for link state changes, return the\n\t\t * values as specified by platform. This will be true\n\t\t * for GMACs connected to switch, and interfaces that\n\t\t * do not use a PHY.\n\t\t */\n\t\tif (!(adapter->poll_required)) {\n\t\t\tif (adapter->forced_speed != SPEED_UNKNOWN) {\n\t\t\t\t/* set speed and duplex */\n\t\t\t\tcmd->base.speed = SPEED_1000;\n\t\t\t\tcmd->base.duplex = DUPLEX_FULL;\n\n\t\t\t\t/* Populate capabilities advertised by self */\n\t\t\t\tlinkmode_zero(cmd->link_modes.advertising);\n\t\t\t\tcmd->base.autoneg = 0;\n\t\t\t\tcmd->base.port = PORT_TP;\n\t\t\t\tcmd->base.transceiver = XCVR_EXTERNAL;\n\t\t\t} else {\n\t\t\t\t/* non link polled and non\n\t\t\t\t * forced speed/duplex interface\n\t\t\t\t */\n\t\t\t\treturn -EIO;\n\t\t\t}\n\t\t}\n\t}\n\n\treturn 0;\n}\n\n/* edma_set_settings()\n *\tSet EDMA settings\n */\nstatic int edma_set_settings(struct net_device *netdev,\n\t\t\t    const struct ethtool_link_ksettings *cmd)\n{\n\tstruct edma_adapter *adapter = netdev_priv(netdev);\n\n\tif ((adapter->forced_speed != SPEED_UNKNOWN) &&\n\t     !adapter->poll_required)\n\t\treturn -EPERM;\n\n\treturn phy_ethtool_ksettings_set(adapter->phydev, cmd);\n}\n\n/* edma_get_coalesce\n *\tget interrupt mitigation\n */\n#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,15,0)\nstatic int edma_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec,\n\t\t\t     struct kernel_ethtool_coalesce *kernel_coal,\n\t\t\t     struct netlink_ext_ack *extack)\n#else\nstatic int edma_get_coalesce(struct net_device *netdev,\n\t\t\t     struct ethtool_coalesce *ec)\n#endif\n{\n\tu32 reg_val;\n\n\tedma_get_tx_rx_coalesce(&reg_val);\n\n\t/* We read the Interrupt Moderation Timer(IMT) register value,\n\t * use lower 16 bit for rx and higher 16 bit for Tx. We do a\n\t * left shift by 1, because IMT resolution timer is 2usecs.\n\t * Hence the value given by the register is multiplied by 2 to\n\t * get the actual time in usecs.\n\t */\n\tec->tx_coalesce_usecs = (((reg_val >> 16) & 0xffff) << 1);\n\tec->rx_coalesce_usecs = ((reg_val & 0xffff) << 1);\n\n\treturn 0;\n}\n\n/* edma_set_coalesce\n *\tset interrupt mitigation\n */\n#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,15,0)\nstatic int edma_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec,\n\t\t\t     struct kernel_ethtool_coalesce *kernel_coal,\n\t\t\t     struct netlink_ext_ack *extack)\n#else\nstatic int edma_set_coalesce(struct net_device *netdev,\n\t\t\t     struct ethtool_coalesce *ec)\n#endif\n{\n\tif (ec->tx_coalesce_usecs)\n\t\tedma_change_tx_coalesce(ec->tx_coalesce_usecs);\n\tif (ec->rx_coalesce_usecs)\n\t\tedma_change_rx_coalesce(ec->rx_coalesce_usecs);\n\n\treturn 0;\n}\n\n/* edma_set_priv_flags()\n *\tSet EDMA private flags\n */\nstatic int edma_set_priv_flags(struct net_device *netdev, u32 flags)\n{\n\treturn 0;\n}\n\n/* edma_get_priv_flags()\n *\tget edma driver flags\n */\nstatic u32 edma_get_priv_flags(struct net_device *netdev)\n{\n\treturn 0;\n}\n\n/* edma_get_ringparam()\n *\tget ring size\n */\nstatic void edma_get_ringparam(struct net_device *netdev,\n\t\t\t       struct ethtool_ringparam *ring)\n{\n\tstruct edma_adapter *adapter = netdev_priv(netdev);\n\tstruct edma_common_info *edma_cinfo = adapter->edma_cinfo;\n\n\tring->tx_max_pending = edma_cinfo->tx_ring_count;\n\tring->rx_max_pending = edma_cinfo->rx_ring_count;\n}\n\n/* Ethtool operations\n */\nstatic const struct ethtool_ops edma_ethtool_ops = {\n#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,7,0)\n\t.supported_coalesce_params = ETHTOOL_COALESCE_USECS,\n#endif\n\t.get_drvinfo = &edma_get_drvinfo,\n\t.get_link = &ethtool_op_get_link,\n\t.get_msglevel = &edma_get_msglevel,\n\t.nway_reset = &edma_nway_reset,\n\t.get_wol = &edma_get_wol,\n\t.get_link_ksettings = &edma_get_settings,\n\t.set_link_ksettings = &edma_set_settings,\n\t.get_strings = &edma_get_strings,\n\t.get_sset_count = &edma_get_strset_count,\n\t.get_ethtool_stats = &edma_get_ethtool_stats,\n\t.get_coalesce = &edma_get_coalesce,\n\t.set_coalesce = &edma_set_coalesce,\n\t.get_priv_flags = edma_get_priv_flags,\n\t.set_priv_flags = edma_set_priv_flags,\n\t.get_ringparam = edma_get_ringparam,\n};\n\n/* edma_set_ethtool_ops\n *\tSet ethtool operations\n */\nvoid edma_set_ethtool_ops(struct net_device *netdev)\n{\n\tnetdev->ethtool_ops = &edma_ethtool_ops;\n}\n"
  },
  {
    "path": "target/linux/ipq40xx/files/drivers/net/ethernet/qualcomm/essedma/ess_edma.h",
    "content": "/*\n * Copyright (c) 2014 - 2016, The Linux Foundation. All rights reserved.\n *\n * Permission to use, copy, modify, and/or distribute this software for\n * any purpose with or without fee is hereby granted, provided that the\n * above copyright notice and this permission notice appear in all copies.\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT\n * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n */\n\n#ifndef _ESS_EDMA_H_\n#define _ESS_EDMA_H_\n\n#include <linux/types.h>\n\nstruct edma_adapter;\nstruct edma_hw;\n\n/* register definition */\n#define EDMA_REG_MAS_CTRL 0x0\n#define EDMA_REG_TIMEOUT_CTRL 0x004\n#define EDMA_REG_DBG0 0x008\n#define EDMA_REG_DBG1 0x00C\n#define EDMA_REG_SW_CTRL0 0x100\n#define EDMA_REG_SW_CTRL1 0x104\n\n/* Interrupt Status Register */\n#define EDMA_REG_RX_ISR 0x200\n#define EDMA_REG_TX_ISR 0x208\n#define EDMA_REG_MISC_ISR 0x210\n#define EDMA_REG_WOL_ISR 0x218\n\n#define EDMA_MISC_ISR_RX_URG_Q(x) (1 << x)\n\n#define EDMA_MISC_ISR_AXIR_TIMEOUT 0x00000100\n#define EDMA_MISC_ISR_AXIR_ERR 0x00000200\n#define EDMA_MISC_ISR_TXF_DEAD 0x00000400\n#define EDMA_MISC_ISR_AXIW_ERR 0x00000800\n#define EDMA_MISC_ISR_AXIW_TIMEOUT 0x00001000\n\n#define EDMA_WOL_ISR 0x00000001\n\n/* Interrupt Mask Register */\n#define EDMA_REG_MISC_IMR 0x214\n#define EDMA_REG_WOL_IMR 0x218\n\n#define EDMA_RX_IMR_NORMAL_MASK 0x1\n#define EDMA_TX_IMR_NORMAL_MASK 0x1\n#define EDMA_MISC_IMR_NORMAL_MASK 0x80001FFF\n#define EDMA_WOL_IMR_NORMAL_MASK 0x1\n\n/* Edma receive consumer index */\n#define EDMA_REG_RX_SW_CONS_IDX_Q(x) (0x220 + ((x) << 2)) /* x is the queue id */\n/* Edma transmit consumer index */\n#define EDMA_REG_TX_SW_CONS_IDX_Q(x) (0x240 + ((x) << 2)) /* x is the queue id */\n\n/* IRQ Moderator Initial Timer Register */\n#define EDMA_REG_IRQ_MODRT_TIMER_INIT 0x280\n#define EDMA_IRQ_MODRT_TIMER_MASK 0xFFFF\n#define EDMA_IRQ_MODRT_RX_TIMER_SHIFT 0\n#define EDMA_IRQ_MODRT_TX_TIMER_SHIFT 16\n\n/* Interrupt Control Register */\n#define EDMA_REG_INTR_CTRL 0x284\n#define EDMA_INTR_CLR_TYP_SHIFT 0\n#define EDMA_INTR_SW_IDX_W_TYP_SHIFT 1\n#define EDMA_INTR_CLEAR_TYPE_W1 0\n#define EDMA_INTR_CLEAR_TYPE_R 1\n\n/* RX Interrupt Mask Register */\n#define EDMA_REG_RX_INT_MASK_Q(x) (0x300 + ((x) << 2)) /* x = queue id */\n\n/* TX Interrupt mask register */\n#define EDMA_REG_TX_INT_MASK_Q(x) (0x340 + ((x) << 2)) /* x = queue id */\n\n/* Load Ptr Register\n * Software sets this bit after the initialization of the head and tail\n */\n#define EDMA_REG_TX_SRAM_PART 0x400\n#define EDMA_LOAD_PTR_SHIFT 16\n\n/* TXQ Control Register */\n#define EDMA_REG_TXQ_CTRL 0x404\n#define EDMA_TXQ_CTRL_IP_OPTION_EN 0x10\n#define EDMA_TXQ_CTRL_TXQ_EN 0x20\n#define EDMA_TXQ_CTRL_ENH_MODE 0x40\n#define EDMA_TXQ_CTRL_LS_8023_EN 0x80\n#define EDMA_TXQ_CTRL_TPD_BURST_EN 0x100\n#define EDMA_TXQ_CTRL_LSO_BREAK_EN 0x200\n#define EDMA_TXQ_NUM_TPD_BURST_MASK 0xF\n#define EDMA_TXQ_TXF_BURST_NUM_MASK 0xFFFF\n#define EDMA_TXQ_NUM_TPD_BURST_SHIFT 0\n#define EDMA_TXQ_TXF_BURST_NUM_SHIFT 16\n\n#define\tEDMA_REG_TXF_WATER_MARK 0x408 /* In 8-bytes */\n#define EDMA_TXF_WATER_MARK_MASK 0x0FFF\n#define EDMA_TXF_LOW_WATER_MARK_SHIFT 0\n#define EDMA_TXF_HIGH_WATER_MARK_SHIFT 16\n#define EDMA_TXQ_CTRL_BURST_MODE_EN 0x80000000\n\n/* WRR Control Register */\n#define EDMA_REG_WRR_CTRL_Q0_Q3 0x40c\n#define EDMA_REG_WRR_CTRL_Q4_Q7 0x410\n#define EDMA_REG_WRR_CTRL_Q8_Q11 0x414\n#define EDMA_REG_WRR_CTRL_Q12_Q15 0x418\n\n/* Weight round robin(WRR), it takes queue as input, and computes\n * starting bits where we need to write the weight for a particular\n * queue\n */\n#define EDMA_WRR_SHIFT(x) (((x) * 5) % 20)\n\n/* Tx Descriptor Control Register */\n#define EDMA_REG_TPD_RING_SIZE 0x41C\n#define EDMA_TPD_RING_SIZE_SHIFT 0\n#define EDMA_TPD_RING_SIZE_MASK 0xFFFF\n\n/* Transmit descriptor base address */\n#define EDMA_REG_TPD_BASE_ADDR_Q(x) (0x420 + ((x) << 2)) /* x = queue id */\n\n/* TPD Index Register */\n#define EDMA_REG_TPD_IDX_Q(x) (0x460 + ((x) << 2)) /* x = queue id */\n\n#define EDMA_TPD_PROD_IDX_BITS 0x0000FFFF\n#define EDMA_TPD_CONS_IDX_BITS 0xFFFF0000\n#define EDMA_TPD_PROD_IDX_MASK 0xFFFF\n#define EDMA_TPD_CONS_IDX_MASK 0xFFFF\n#define EDMA_TPD_PROD_IDX_SHIFT 0\n#define EDMA_TPD_CONS_IDX_SHIFT 16\n\n/* TX Virtual Queue Mapping Control Register */\n#define EDMA_REG_VQ_CTRL0 0x4A0\n#define EDMA_REG_VQ_CTRL1 0x4A4\n\n/* Virtual QID shift, it takes queue as input, and computes\n * Virtual QID position in virtual qid control register\n */\n#define EDMA_VQ_ID_SHIFT(i) (((i) * 3) % 24)\n\n/* Virtual Queue Default Value */\n#define EDMA_VQ_REG_VALUE 0x240240\n\n/* Tx side Port Interface Control Register */\n#define EDMA_REG_PORT_CTRL 0x4A8\n#define EDMA_PAD_EN_SHIFT 15\n\n/* Tx side VLAN Configuration Register */\n#define EDMA_REG_VLAN_CFG 0x4AC\n\n#define EDMA_TX_CVLAN 16\n#define EDMA_TX_INS_CVLAN 17\n#define EDMA_TX_CVLAN_TAG_SHIFT 0\n\n#define EDMA_TX_SVLAN 14\n#define EDMA_TX_INS_SVLAN 15\n#define EDMA_TX_SVLAN_TAG_SHIFT 16\n\n/* Tx Queue Packet Statistic Register */\n#define EDMA_REG_TX_STAT_PKT_Q(x) (0x700 + ((x) << 3)) /* x = queue id */\n\n#define EDMA_TX_STAT_PKT_MASK 0xFFFFFF\n\n/* Tx Queue Byte Statistic Register */\n#define EDMA_REG_TX_STAT_BYTE_Q(x) (0x704 + ((x) << 3)) /* x = queue id */\n\n/* Load Balance Based Ring Offset Register */\n#define EDMA_REG_LB_RING 0x800\n#define EDMA_LB_RING_ENTRY_MASK 0xff\n#define EDMA_LB_RING_ID_MASK 0x7\n#define EDMA_LB_RING_PROFILE_ID_MASK 0x3\n#define EDMA_LB_RING_ENTRY_BIT_OFFSET 8\n#define EDMA_LB_RING_ID_OFFSET 0\n#define EDMA_LB_RING_PROFILE_ID_OFFSET 3\n#define EDMA_LB_REG_VALUE 0x6040200\n\n/* Load Balance Priority Mapping Register */\n#define EDMA_REG_LB_PRI_START 0x804\n#define EDMA_REG_LB_PRI_END 0x810\n#define EDMA_LB_PRI_REG_INC 4\n#define EDMA_LB_PRI_ENTRY_BIT_OFFSET 4\n#define EDMA_LB_PRI_ENTRY_MASK 0xf\n\n/* RSS Priority Mapping Register */\n#define EDMA_REG_RSS_PRI 0x820\n#define EDMA_RSS_PRI_ENTRY_MASK 0xf\n#define EDMA_RSS_RING_ID_MASK 0x7\n#define EDMA_RSS_PRI_ENTRY_BIT_OFFSET 4\n\n/* RSS Indirection Register */\n#define EDMA_REG_RSS_IDT(x) (0x840 + ((x) << 2)) /* x = No. of indirection table */\n#define EDMA_NUM_IDT 16\n#define EDMA_RSS_IDT_VALUE 0x64206420\n\n/* Default RSS Ring Register */\n#define EDMA_REG_DEF_RSS 0x890\n#define EDMA_DEF_RSS_MASK 0x7\n\n/* RSS Hash Function Type Register */\n#define EDMA_REG_RSS_TYPE 0x894\n#define EDMA_RSS_TYPE_NONE 0x01\n#define EDMA_RSS_TYPE_IPV4TCP 0x02\n#define EDMA_RSS_TYPE_IPV6_TCP 0x04\n#define EDMA_RSS_TYPE_IPV4_UDP 0x08\n#define EDMA_RSS_TYPE_IPV6UDP 0x10\n#define EDMA_RSS_TYPE_IPV4 0x20\n#define EDMA_RSS_TYPE_IPV6 0x40\n#define EDMA_RSS_HASH_MODE_MASK 0x7f\n\n#define EDMA_REG_RSS_HASH_VALUE 0x8C0\n\n#define EDMA_REG_RSS_TYPE_RESULT 0x8C4\n\n#define EDMA_HASH_TYPE_START 0\n#define EDMA_HASH_TYPE_END 5\n#define EDMA_HASH_TYPE_SHIFT 12\n\n#define EDMA_RFS_FLOW_ENTRIES 1024\n#define EDMA_RFS_FLOW_ENTRIES_MASK (EDMA_RFS_FLOW_ENTRIES - 1)\n#define EDMA_RFS_EXPIRE_COUNT_PER_CALL 128\n\n/* RFD Base Address Register */\n#define EDMA_REG_RFD_BASE_ADDR_Q(x) (0x950 + ((x) << 2)) /* x = queue id */\n\n/* RFD Index Register */\n#define EDMA_REG_RFD_IDX_Q(x) (0x9B0 + ((x) << 2))\n\n#define EDMA_RFD_PROD_IDX_BITS 0x00000FFF\n#define EDMA_RFD_CONS_IDX_BITS 0x0FFF0000\n#define EDMA_RFD_PROD_IDX_MASK 0xFFF\n#define EDMA_RFD_CONS_IDX_MASK 0xFFF\n#define EDMA_RFD_PROD_IDX_SHIFT 0\n#define EDMA_RFD_CONS_IDX_SHIFT 16\n\n/* Rx Descriptor Control Register */\n#define EDMA_REG_RX_DESC0 0xA10\n#define EDMA_RFD_RING_SIZE_MASK 0xFFF\n#define EDMA_RX_BUF_SIZE_MASK 0xFFFF\n#define EDMA_RFD_RING_SIZE_SHIFT 0\n#define EDMA_RX_BUF_SIZE_SHIFT 16\n\n#define EDMA_REG_RX_DESC1 0xA14\n#define EDMA_RXQ_RFD_BURST_NUM_MASK 0x3F\n#define EDMA_RXQ_RFD_PF_THRESH_MASK 0x1F\n#define EDMA_RXQ_RFD_LOW_THRESH_MASK 0xFFF\n#define EDMA_RXQ_RFD_BURST_NUM_SHIFT 0\n#define EDMA_RXQ_RFD_PF_THRESH_SHIFT 8\n#define EDMA_RXQ_RFD_LOW_THRESH_SHIFT 16\n\n/* RXQ Control Register */\n#define EDMA_REG_RXQ_CTRL 0xA18\n#define EDMA_FIFO_THRESH_TYPE_SHIF 0\n#define EDMA_FIFO_THRESH_128_BYTE 0x0\n#define EDMA_FIFO_THRESH_64_BYTE 0x1\n#define EDMA_RXQ_CTRL_RMV_VLAN 0x00000002\n#define EDMA_RXQ_CTRL_EN 0x0000FF00\n\n/* AXI Burst Size Config */\n#define EDMA_REG_AXIW_CTRL_MAXWRSIZE 0xA1C\n#define EDMA_AXIW_MAXWRSIZE_VALUE 0x0\n\n/* Rx Statistics Register */\n#define EDMA_REG_RX_STAT_BYTE_Q(x) (0xA30 + ((x) << 2)) /* x = queue id */\n#define EDMA_REG_RX_STAT_PKT_Q(x) (0xA50 + ((x) << 2)) /* x = queue id */\n\n/* WoL Pattern Length Register */\n#define EDMA_REG_WOL_PATTERN_LEN0 0xC00\n#define EDMA_WOL_PT_LEN_MASK 0xFF\n#define EDMA_WOL_PT0_LEN_SHIFT 0\n#define EDMA_WOL_PT1_LEN_SHIFT 8\n#define EDMA_WOL_PT2_LEN_SHIFT 16\n#define EDMA_WOL_PT3_LEN_SHIFT 24\n\n#define EDMA_REG_WOL_PATTERN_LEN1 0xC04\n#define EDMA_WOL_PT4_LEN_SHIFT 0\n#define EDMA_WOL_PT5_LEN_SHIFT 8\n#define EDMA_WOL_PT6_LEN_SHIFT 16\n\n/* WoL Control Register */\n#define EDMA_REG_WOL_CTRL 0xC08\n#define EDMA_WOL_WK_EN 0x00000001\n#define EDMA_WOL_MG_EN 0x00000002\n#define EDMA_WOL_PT0_EN 0x00000004\n#define EDMA_WOL_PT1_EN 0x00000008\n#define EDMA_WOL_PT2_EN 0x00000010\n#define EDMA_WOL_PT3_EN 0x00000020\n#define EDMA_WOL_PT4_EN 0x00000040\n#define EDMA_WOL_PT5_EN 0x00000080\n#define EDMA_WOL_PT6_EN 0x00000100\n\n/* MAC Control Register */\n#define EDMA_REG_MAC_CTRL0 0xC20\n#define EDMA_REG_MAC_CTRL1 0xC24\n\n/* WoL Pattern Register */\n#define EDMA_REG_WOL_PATTERN_START 0x5000\n#define EDMA_PATTERN_PART_REG_OFFSET 0x40\n\n\n/* TX descriptor fields */\n#define EDMA_TPD_HDR_SHIFT 0\n#define EDMA_TPD_PPPOE_EN 0x00000100\n#define EDMA_TPD_IP_CSUM_EN 0x00000200\n#define EDMA_TPD_TCP_CSUM_EN 0x0000400\n#define EDMA_TPD_UDP_CSUM_EN 0x00000800\n#define EDMA_TPD_CUSTOM_CSUM_EN 0x00000C00\n#define EDMA_TPD_LSO_EN 0x00001000\n#define EDMA_TPD_LSO_V2_EN 0x00002000\n#define EDMA_TPD_IPV4_EN 0x00010000\n#define EDMA_TPD_MSS_MASK 0x1FFF\n#define EDMA_TPD_MSS_SHIFT 18\n#define EDMA_TPD_CUSTOM_CSUM_SHIFT 18\n\n/* RRD descriptor fields */\n#define EDMA_RRD_NUM_RFD_MASK 0x000F\n#define EDMA_RRD_SVLAN 0x8000\n#define EDMA_RRD_FLOW_COOKIE_MASK 0x07FF;\n\n#define EDMA_RRD_PKT_SIZE_MASK 0x3FFF\n#define EDMA_RRD_CSUM_FAIL_MASK 0xC000\n#define EDMA_RRD_CVLAN 0x0001\n#define EDMA_RRD_DESC_VALID 0x8000\n\n#define EDMA_RRD_PRIORITY_SHIFT 4\n#define EDMA_RRD_PRIORITY_MASK 0x7\n#define EDMA_RRD_PORT_TYPE_SHIFT 7\n#define EDMA_RRD_PORT_TYPE_MASK 0x1F\n\n#define ESS_RGMII_CTRL\t\t0x0004\n\n/* Port status registers */\n#define ESS_PORT0_STATUS\t0x007C\n#define ESS_PORT1_STATUS\t0x0080\n#define ESS_PORT2_STATUS\t0x0084\n#define ESS_PORT3_STATUS\t0x0088\n#define ESS_PORT4_STATUS\t0x008C\n#define ESS_PORT5_STATUS\t0x0090\n\n#define ESS_PORT_STATUS_HDX_FLOW_CTL\t0x80\n#define ESS_PORT_STATUS_DUPLEX_MODE\t0x40\n#define ESS_PORT_STATUS_RX_FLOW_EN\t0x20\n#define ESS_PORT_STATUS_TX_FLOW_EN\t0x10\n#define ESS_PORT_STATUS_RX_MAC_EN\t0x08\n#define ESS_PORT_STATUS_TX_MAC_EN\t0x04\n#define ESS_PORT_STATUS_SPEED_INV\t0x03\n#define ESS_PORT_STATUS_SPEED_1000\t0x02\n#define ESS_PORT_STATUS_SPEED_100\t0x01\n#define ESS_PORT_STATUS_SPEED_10\t0x00\n\n#define ESS_PORT_1G_FDX      (ESS_PORT_STATUS_DUPLEX_MODE | ESS_PORT_STATUS_RX_FLOW_EN | \\\n\t\t\t       ESS_PORT_STATUS_TX_FLOW_EN  | ESS_PORT_STATUS_RX_MAC_EN  | \\\n\t\t\t       ESS_PORT_STATUS_TX_MAC_EN   | ESS_PORT_STATUS_SPEED_1000)\n\n#define PHY_STATUS_REG\t\t\t0x11\n#define PHY_STATUS_SPEED\t\t0xC000\n#define PHY_STATUS_SPEED_SHIFT\t\t14\n#define PHY_STATUS_DUPLEX\t\t0x2000\n#define PHY_STATUS_DUPLEX_SHIFT\t13\n#define PHY_STATUS_SPEED_DUPLEX_RESOLVED 0x0800\n#define PHY_STATUS_CARRIER\t\t0x0400\n#define PHY_STATUS_CARRIER_SHIFT\t10\n\n/* Port lookup control registers */\n#define ESS_PORT0_LOOKUP_CTRL\t0x0660\n#define ESS_PORT1_LOOKUP_CTRL\t0x066C\n#define ESS_PORT2_LOOKUP_CTRL\t0x0678\n#define ESS_PORT3_LOOKUP_CTRL\t0x0684\n#define ESS_PORT4_LOOKUP_CTRL\t0x0690\n#define ESS_PORT5_LOOKUP_CTRL\t0x069C\n\n#define ESS_PORT0_HEADER_CTRL\t0x009C\n\n#define ESS_PORTS_ALL\t\t0x3f\n\n#define ESS_FWD_CTRL1\t\t0x0624\n#define   ESS_FWD_CTRL1_UC_FLOOD\t\tBITS(0, 7)\n#define   ESS_FWD_CTRL1_UC_FLOOD_S\t\t0\n#define   ESS_FWD_CTRL1_MC_FLOOD\t\tBITS(8, 7)\n#define   ESS_FWD_CTRL1_MC_FLOOD_S\t\t8\n#define   ESS_FWD_CTRL1_BC_FLOOD\t\tBITS(16, 7)\n#define   ESS_FWD_CTRL1_BC_FLOOD_S\t\t16\n#define   ESS_FWD_CTRL1_IGMP\t\t\tBITS(24, 7)\n#define   ESS_FWD_CTRL1_IGMP_S\t\t\t24\n\n#endif /* _ESS_EDMA_H_ */\n"
  },
  {
    "path": "target/linux/ipq40xx/files/drivers/net/mdio/ar40xx.c",
    "content": "/*\n * Copyright (c) 2016, The Linux Foundation. All rights reserved.\n *\n * Permission to use, copy, modify, and/or distribute this software for\n * any purpose with or without fee is hereby granted, provided that the\n * above copyright notice and this permission notice appear in all copies.\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT\n * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n */\n\n#include <linux/bitfield.h>\n#include <linux/module.h>\n#include <linux/list.h>\n#include <linux/bitops.h>\n#include <linux/switch.h>\n#include <linux/delay.h>\n#include <linux/phy.h>\n#include <linux/clk.h>\n#include <linux/reset.h>\n#include <linux/lockdep.h>\n#include <linux/workqueue.h>\n#include <linux/of_device.h>\n#include <linux/of_address.h>\n#include <linux/of_mdio.h>\n#include <linux/mdio.h>\n#include <linux/gpio.h>\n\n#include \"ar40xx.h\"\n\nstatic struct ar40xx_priv *ar40xx_priv;\n\n#define MIB_DESC(_s , _o, _n)\t\\\n\t{\t\t\t\\\n\t\t.size = (_s),\t\\\n\t\t.offset = (_o),\t\\\n\t\t.name = (_n),\t\\\n\t}\n\nstatic const struct ar40xx_mib_desc ar40xx_mibs[] = {\n\tMIB_DESC(1, AR40XX_STATS_RXBROAD, \"RxBroad\"),\n\tMIB_DESC(1, AR40XX_STATS_RXPAUSE, \"RxPause\"),\n\tMIB_DESC(1, AR40XX_STATS_RXMULTI, \"RxMulti\"),\n\tMIB_DESC(1, AR40XX_STATS_RXFCSERR, \"RxFcsErr\"),\n\tMIB_DESC(1, AR40XX_STATS_RXALIGNERR, \"RxAlignErr\"),\n\tMIB_DESC(1, AR40XX_STATS_RXRUNT, \"RxRunt\"),\n\tMIB_DESC(1, AR40XX_STATS_RXFRAGMENT, \"RxFragment\"),\n\tMIB_DESC(1, AR40XX_STATS_RX64BYTE, \"Rx64Byte\"),\n\tMIB_DESC(1, AR40XX_STATS_RX128BYTE, \"Rx128Byte\"),\n\tMIB_DESC(1, AR40XX_STATS_RX256BYTE, \"Rx256Byte\"),\n\tMIB_DESC(1, AR40XX_STATS_RX512BYTE, \"Rx512Byte\"),\n\tMIB_DESC(1, AR40XX_STATS_RX1024BYTE, \"Rx1024Byte\"),\n\tMIB_DESC(1, AR40XX_STATS_RX1518BYTE, \"Rx1518Byte\"),\n\tMIB_DESC(1, AR40XX_STATS_RXMAXBYTE, \"RxMaxByte\"),\n\tMIB_DESC(1, AR40XX_STATS_RXTOOLONG, \"RxTooLong\"),\n\tMIB_DESC(2, AR40XX_STATS_RXGOODBYTE, \"RxGoodByte\"),\n\tMIB_DESC(2, AR40XX_STATS_RXBADBYTE, \"RxBadByte\"),\n\tMIB_DESC(1, AR40XX_STATS_RXOVERFLOW, \"RxOverFlow\"),\n\tMIB_DESC(1, AR40XX_STATS_FILTERED, \"Filtered\"),\n\tMIB_DESC(1, AR40XX_STATS_TXBROAD, \"TxBroad\"),\n\tMIB_DESC(1, AR40XX_STATS_TXPAUSE, \"TxPause\"),\n\tMIB_DESC(1, AR40XX_STATS_TXMULTI, \"TxMulti\"),\n\tMIB_DESC(1, AR40XX_STATS_TXUNDERRUN, \"TxUnderRun\"),\n\tMIB_DESC(1, AR40XX_STATS_TX64BYTE, \"Tx64Byte\"),\n\tMIB_DESC(1, AR40XX_STATS_TX128BYTE, \"Tx128Byte\"),\n\tMIB_DESC(1, AR40XX_STATS_TX256BYTE, \"Tx256Byte\"),\n\tMIB_DESC(1, AR40XX_STATS_TX512BYTE, \"Tx512Byte\"),\n\tMIB_DESC(1, AR40XX_STATS_TX1024BYTE, \"Tx1024Byte\"),\n\tMIB_DESC(1, AR40XX_STATS_TX1518BYTE, \"Tx1518Byte\"),\n\tMIB_DESC(1, AR40XX_STATS_TXMAXBYTE, \"TxMaxByte\"),\n\tMIB_DESC(1, AR40XX_STATS_TXOVERSIZE, \"TxOverSize\"),\n\tMIB_DESC(2, AR40XX_STATS_TXBYTE, \"TxByte\"),\n\tMIB_DESC(1, AR40XX_STATS_TXCOLLISION, \"TxCollision\"),\n\tMIB_DESC(1, AR40XX_STATS_TXABORTCOL, \"TxAbortCol\"),\n\tMIB_DESC(1, AR40XX_STATS_TXMULTICOL, \"TxMultiCol\"),\n\tMIB_DESC(1, AR40XX_STATS_TXSINGLECOL, \"TxSingleCol\"),\n\tMIB_DESC(1, AR40XX_STATS_TXEXCDEFER, \"TxExcDefer\"),\n\tMIB_DESC(1, AR40XX_STATS_TXDEFER, \"TxDefer\"),\n\tMIB_DESC(1, AR40XX_STATS_TXLATECOL, \"TxLateCol\"),\n};\n\nstatic u32\nar40xx_read(struct ar40xx_priv *priv, int reg)\n{\n\treturn readl(priv->hw_addr + reg);\n}\n\nstatic u32\nar40xx_psgmii_read(struct ar40xx_priv *priv, int reg)\n{\n\treturn readl(priv->psgmii_hw_addr + reg);\n}\n\nstatic void\nar40xx_write(struct ar40xx_priv *priv, int reg, u32 val)\n{\n\twritel(val, priv->hw_addr + reg);\n}\n\nstatic u32\nar40xx_rmw(struct ar40xx_priv *priv, int reg, u32 mask, u32 val)\n{\n\tu32 ret;\n\n\tret = ar40xx_read(priv, reg);\n\tret &= ~mask;\n\tret |= val;\n\tar40xx_write(priv, reg, ret);\n\treturn ret;\n}\n\nstatic void\nar40xx_psgmii_write(struct ar40xx_priv *priv, int reg, u32 val)\n{\n\twritel(val, priv->psgmii_hw_addr + reg);\n}\n\nstatic void\nar40xx_phy_dbg_write(struct ar40xx_priv *priv, int phy_addr,\n\t\t     u16 dbg_addr, u16 dbg_data)\n{\n\tstruct mii_bus *bus = priv->mii_bus;\n\n\tmutex_lock(&bus->mdio_lock);\n\tbus->write(bus, phy_addr, AR40XX_MII_ATH_DBG_ADDR, dbg_addr);\n\tbus->write(bus, phy_addr, AR40XX_MII_ATH_DBG_DATA, dbg_data);\n\tmutex_unlock(&bus->mdio_lock);\n}\n\nstatic void\nar40xx_phy_dbg_read(struct ar40xx_priv *priv, int phy_addr,\n\t\t    u16 dbg_addr, u16 *dbg_data)\n{\n\tstruct mii_bus *bus = priv->mii_bus;\n\n\tmutex_lock(&bus->mdio_lock);\n\tbus->write(bus, phy_addr, AR40XX_MII_ATH_DBG_ADDR, dbg_addr);\n\t*dbg_data = bus->read(bus, phy_addr, AR40XX_MII_ATH_DBG_DATA);\n\tmutex_unlock(&bus->mdio_lock);\n}\n\nstatic void\nar40xx_phy_mmd_write(struct ar40xx_priv *priv, u32 phy_id,\n\t\t     u16 mmd_num, u16 reg_id, u16 reg_val)\n{\n\tstruct mii_bus *bus = priv->mii_bus;\n\n\tmutex_lock(&bus->mdio_lock);\n\tbus->write(bus, phy_id,\n\t\t\tAR40XX_MII_ATH_MMD_ADDR, mmd_num);\n\tbus->write(bus, phy_id,\n\t\t\tAR40XX_MII_ATH_MMD_DATA, reg_id);\n\tbus->write(bus, phy_id,\n\t\t\tAR40XX_MII_ATH_MMD_ADDR,\n\t\t\t0x4000 | mmd_num);\n\tbus->write(bus, phy_id,\n\t\tAR40XX_MII_ATH_MMD_DATA, reg_val);\n\tmutex_unlock(&bus->mdio_lock);\n}\n\nstatic u16\nar40xx_phy_mmd_read(struct ar40xx_priv *priv, u32 phy_id,\n\t\t    u16 mmd_num, u16 reg_id)\n{\n\tu16 value;\n\tstruct mii_bus *bus = priv->mii_bus;\n\n\tmutex_lock(&bus->mdio_lock);\n\tbus->write(bus, phy_id,\n\t\t\tAR40XX_MII_ATH_MMD_ADDR, mmd_num);\n\tbus->write(bus, phy_id,\n\t\t\tAR40XX_MII_ATH_MMD_DATA, reg_id);\n\tbus->write(bus, phy_id,\n\t\t\tAR40XX_MII_ATH_MMD_ADDR,\n\t\t\t0x4000 | mmd_num);\n\tvalue = bus->read(bus, phy_id, AR40XX_MII_ATH_MMD_DATA);\n\tmutex_unlock(&bus->mdio_lock);\n\treturn value;\n}\n\n/* Start of swconfig support */\n\nstatic void\nar40xx_phy_poll_reset(struct ar40xx_priv *priv)\n{\n\tu32 i, in_reset, retries = 500;\n\tstruct mii_bus *bus = priv->mii_bus;\n\n\t/* Assume RESET was recently issued to some or all of the phys */\n\tin_reset = GENMASK(AR40XX_NUM_PHYS - 1, 0);\n\n\twhile (retries--) {\n\t\t/* 1ms should be plenty of time.\n\t\t * 802.3 spec allows for a max wait time of 500ms\n\t\t */\n\t\tusleep_range(1000, 2000);\n\n\t\tfor (i = 0; i < AR40XX_NUM_PHYS; i++) {\n\t\t\tint val;\n\n\t\t\t/* skip devices which have completed reset */\n\t\t\tif (!(in_reset & BIT(i)))\n\t\t\t\tcontinue;\n\n\t\t\tval = mdiobus_read(bus, i, MII_BMCR);\n\t\t\tif (val < 0)\n\t\t\t\tcontinue;\n\n\t\t\t/* mark when phy is no longer in reset state */\n\t\t\tif (!(val & BMCR_RESET))\n\t\t\t\tin_reset &= ~BIT(i);\n\t\t}\n\n\t\tif (!in_reset)\n\t\t\treturn;\n\t}\n\n\tdev_warn(&bus->dev, \"Failed to reset all phys! (in_reset: 0x%x)\\n\",\n\t\t in_reset);\n}\n\nstatic void\nar40xx_phy_init(struct ar40xx_priv *priv)\n{\n\tint i;\n\tstruct mii_bus *bus;\n\tu16 val;\n\n\tbus = priv->mii_bus;\n\tfor (i = 0; i < AR40XX_NUM_PORTS - 1; i++) {\n\t\tar40xx_phy_dbg_read(priv, i, AR40XX_PHY_DEBUG_0, &val);\n\t\tval &= ~AR40XX_PHY_MANU_CTRL_EN;\n\t\tar40xx_phy_dbg_write(priv, i, AR40XX_PHY_DEBUG_0, val);\n\t\tmdiobus_write(bus, i,\n\t\t\t      MII_ADVERTISE, ADVERTISE_ALL |\n\t\t\t      ADVERTISE_PAUSE_CAP |\n\t\t\t      ADVERTISE_PAUSE_ASYM);\n\t\tmdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);\n\t\tmdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);\n\t}\n\n\tar40xx_phy_poll_reset(priv);\n}\n\nstatic void\nar40xx_port_phy_linkdown(struct ar40xx_priv *priv)\n{\n\tstruct mii_bus *bus;\n\tint i;\n\tu16 val;\n\n\tbus = priv->mii_bus;\n\tfor (i = 0; i < AR40XX_NUM_PORTS - 1; i++) {\n\t\tmdiobus_write(bus, i, MII_CTRL1000, 0);\n\t\tmdiobus_write(bus, i, MII_ADVERTISE, 0);\n\t\tmdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);\n\t\tar40xx_phy_dbg_read(priv, i, AR40XX_PHY_DEBUG_0, &val);\n\t\tval |= AR40XX_PHY_MANU_CTRL_EN;\n\t\tar40xx_phy_dbg_write(priv, i, AR40XX_PHY_DEBUG_0, val);\n\t\t/* disable transmit */\n\t\tar40xx_phy_dbg_read(priv, i, AR40XX_PHY_DEBUG_2, &val);\n\t\tval &= 0xf00f;\n\t\tar40xx_phy_dbg_write(priv, i, AR40XX_PHY_DEBUG_2, val);\n\t}\n}\n\nstatic void\nar40xx_set_mirror_regs(struct ar40xx_priv *priv)\n{\n\tint port;\n\n\t/* reset all mirror registers */\n\tar40xx_rmw(priv, AR40XX_REG_FWD_CTRL0,\n\t\t   AR40XX_FWD_CTRL0_MIRROR_PORT,\n\t\t   (0xF << AR40XX_FWD_CTRL0_MIRROR_PORT_S));\n\tfor (port = 0; port < AR40XX_NUM_PORTS; port++) {\n\t\tar40xx_rmw(priv, AR40XX_REG_PORT_LOOKUP(port),\n\t\t\t   AR40XX_PORT_LOOKUP_ING_MIRROR_EN, 0);\n\n\t\tar40xx_rmw(priv, AR40XX_REG_PORT_HOL_CTRL1(port),\n\t\t\t   AR40XX_PORT_HOL_CTRL1_EG_MIRROR_EN, 0);\n\t}\n\n\t/* now enable mirroring if necessary */\n\tif (priv->source_port >= AR40XX_NUM_PORTS ||\n\t    priv->monitor_port >= AR40XX_NUM_PORTS ||\n\t    priv->source_port == priv->monitor_port) {\n\t\treturn;\n\t}\n\n\tar40xx_rmw(priv, AR40XX_REG_FWD_CTRL0,\n\t\t   AR40XX_FWD_CTRL0_MIRROR_PORT,\n\t\t   (priv->monitor_port << AR40XX_FWD_CTRL0_MIRROR_PORT_S));\n\n\tif (priv->mirror_rx)\n\t\tar40xx_rmw(priv, AR40XX_REG_PORT_LOOKUP(priv->source_port), 0,\n\t\t\t   AR40XX_PORT_LOOKUP_ING_MIRROR_EN);\n\n\tif (priv->mirror_tx)\n\t\tar40xx_rmw(priv, AR40XX_REG_PORT_HOL_CTRL1(priv->source_port),\n\t\t\t   0, AR40XX_PORT_HOL_CTRL1_EG_MIRROR_EN);\n}\n\nstatic int\nar40xx_sw_get_ports(struct switch_dev *dev, struct switch_val *val)\n{\n\tstruct ar40xx_priv *priv = swdev_to_ar40xx(dev);\n\tu8 ports = priv->vlan_table[val->port_vlan];\n\tint i;\n\n\tval->len = 0;\n\tfor (i = 0; i < dev->ports; i++) {\n\t\tstruct switch_port *p;\n\n\t\tif (!(ports & BIT(i)))\n\t\t\tcontinue;\n\n\t\tp = &val->value.ports[val->len++];\n\t\tp->id = i;\n\t\tif ((priv->vlan_tagged & BIT(i)) ||\n\t\t    (priv->pvid[i] != val->port_vlan))\n\t\t\tp->flags = BIT(SWITCH_PORT_FLAG_TAGGED);\n\t\telse\n\t\t\tp->flags = 0;\n\t}\n\treturn 0;\n}\n\nstatic int\nar40xx_sw_set_ports(struct switch_dev *dev, struct switch_val *val)\n{\n\tstruct ar40xx_priv *priv = swdev_to_ar40xx(dev);\n\tu8 *vt = &priv->vlan_table[val->port_vlan];\n\tint i;\n\n\t*vt = 0;\n\tfor (i = 0; i < val->len; i++) {\n\t\tstruct switch_port *p = &val->value.ports[i];\n\n\t\tif (p->flags & BIT(SWITCH_PORT_FLAG_TAGGED)) {\n\t\t\tif (val->port_vlan == priv->pvid[p->id])\n\t\t\t\tpriv->vlan_tagged |= BIT(p->id);\n\t\t} else {\n\t\t\tpriv->vlan_tagged &= ~BIT(p->id);\n\t\t\tpriv->pvid[p->id] = val->port_vlan;\n\t\t}\n\n\t\t*vt |= BIT(p->id);\n\t}\n\treturn 0;\n}\n\nstatic int\nar40xx_reg_wait(struct ar40xx_priv *priv, u32 reg, u32 mask, u32 val,\n\t\tunsigned timeout)\n{\n\tint i;\n\n\tfor (i = 0; i < timeout; i++) {\n\t\tu32 t;\n\n\t\tt = ar40xx_read(priv, reg);\n\t\tif ((t & mask) == val)\n\t\t\treturn 0;\n\n\t\tusleep_range(1000, 2000);\n\t}\n\n\treturn -ETIMEDOUT;\n}\n\nstatic int\nar40xx_mib_op(struct ar40xx_priv *priv, u32 op)\n{\n\tint ret;\n\n\tlockdep_assert_held(&priv->mib_lock);\n\n\t/* Capture the hardware statistics for all ports */\n\tar40xx_rmw(priv, AR40XX_REG_MIB_FUNC,\n\t\t   AR40XX_MIB_FUNC, (op << AR40XX_MIB_FUNC_S));\n\n\t/* Wait for the capturing to complete. */\n\tret = ar40xx_reg_wait(priv, AR40XX_REG_MIB_FUNC,\n\t\t\t      AR40XX_MIB_BUSY, 0, 10);\n\n\treturn ret;\n}\n\nstatic void\nar40xx_mib_fetch_port_stat(struct ar40xx_priv *priv, int port, bool flush)\n{\n\tunsigned int base;\n\tu64 *mib_stats;\n\tint i;\n\tu32 num_mibs = ARRAY_SIZE(ar40xx_mibs);\n\n\tWARN_ON(port >= priv->dev.ports);\n\n\tlockdep_assert_held(&priv->mib_lock);\n\n\tbase = AR40XX_REG_PORT_STATS_START +\n\t       AR40XX_REG_PORT_STATS_LEN * port;\n\n\tmib_stats = &priv->mib_stats[port * num_mibs];\n\tif (flush) {\n\t\tu32 len;\n\n\t\tlen = num_mibs * sizeof(*mib_stats);\n\t\tmemset(mib_stats, 0, len);\n\t\treturn;\n\t}\n\tfor (i = 0; i < num_mibs; i++) {\n\t\tconst struct ar40xx_mib_desc *mib;\n\t\tu64 t;\n\n\t\tmib = &ar40xx_mibs[i];\n\t\tt = ar40xx_read(priv, base + mib->offset);\n\t\tif (mib->size == 2) {\n\t\t\tu64 hi;\n\n\t\t\thi = ar40xx_read(priv, base + mib->offset + 4);\n\t\t\tt |= hi << 32;\n\t\t}\n\n\t\tmib_stats[i] += t;\n\t}\n}\n\nstatic int\nar40xx_mib_capture(struct ar40xx_priv *priv)\n{\n\treturn ar40xx_mib_op(priv, AR40XX_MIB_FUNC_CAPTURE);\n}\n\nstatic int\nar40xx_mib_flush(struct ar40xx_priv *priv)\n{\n\treturn ar40xx_mib_op(priv, AR40XX_MIB_FUNC_FLUSH);\n}\n\nstatic int\nar40xx_sw_set_reset_mibs(struct switch_dev *dev,\n\t\t\t const struct switch_attr *attr,\n\t\t\t struct switch_val *val)\n{\n\tstruct ar40xx_priv *priv = swdev_to_ar40xx(dev);\n\tunsigned int len;\n\tint ret;\n\tu32 num_mibs = ARRAY_SIZE(ar40xx_mibs);\n\n\tmutex_lock(&priv->mib_lock);\n\n\tlen = priv->dev.ports * num_mibs * sizeof(*priv->mib_stats);\n\tmemset(priv->mib_stats, 0, len);\n\tret = ar40xx_mib_flush(priv);\n\n\tmutex_unlock(&priv->mib_lock);\n\treturn ret;\n}\n\nstatic int\nar40xx_sw_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,\n\t\t   struct switch_val *val)\n{\n\tstruct ar40xx_priv *priv = swdev_to_ar40xx(dev);\n\n\tpriv->vlan = !!val->value.i;\n\treturn 0;\n}\n\nstatic int\nar40xx_sw_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,\n\t\t   struct switch_val *val)\n{\n\tstruct ar40xx_priv *priv = swdev_to_ar40xx(dev);\n\n\tval->value.i = priv->vlan;\n\treturn 0;\n}\n\nstatic int\nar40xx_sw_set_mirror_rx_enable(struct switch_dev *dev,\n\t\t\t       const struct switch_attr *attr,\n\t\t\t       struct switch_val *val)\n{\n\tstruct ar40xx_priv *priv = swdev_to_ar40xx(dev);\n\n\tmutex_lock(&priv->reg_mutex);\n\tpriv->mirror_rx = !!val->value.i;\n\tar40xx_set_mirror_regs(priv);\n\tmutex_unlock(&priv->reg_mutex);\n\n\treturn 0;\n}\n\nstatic int\nar40xx_sw_get_mirror_rx_enable(struct switch_dev *dev,\n\t\t\t       const struct switch_attr *attr,\n\t\t\t       struct switch_val *val)\n{\n\tstruct ar40xx_priv *priv = swdev_to_ar40xx(dev);\n\n\tmutex_lock(&priv->reg_mutex);\n\tval->value.i = priv->mirror_rx;\n\tmutex_unlock(&priv->reg_mutex);\n\treturn 0;\n}\n\nstatic int\nar40xx_sw_set_mirror_tx_enable(struct switch_dev *dev,\n\t\t\t       const struct switch_attr *attr,\n\t\t\t       struct switch_val *val)\n{\n\tstruct ar40xx_priv *priv = swdev_to_ar40xx(dev);\n\n\tmutex_lock(&priv->reg_mutex);\n\tpriv->mirror_tx = !!val->value.i;\n\tar40xx_set_mirror_regs(priv);\n\tmutex_unlock(&priv->reg_mutex);\n\n\treturn 0;\n}\n\nstatic int\nar40xx_sw_get_mirror_tx_enable(struct switch_dev *dev,\n\t\t\t       const struct switch_attr *attr,\n\t\t\t       struct switch_val *val)\n{\n\tstruct ar40xx_priv *priv = swdev_to_ar40xx(dev);\n\n\tmutex_lock(&priv->reg_mutex);\n\tval->value.i = priv->mirror_tx;\n\tmutex_unlock(&priv->reg_mutex);\n\treturn 0;\n}\n\nstatic int\nar40xx_sw_set_mirror_monitor_port(struct switch_dev *dev,\n\t\t\t\t  const struct switch_attr *attr,\n\t\t\t\t  struct switch_val *val)\n{\n\tstruct ar40xx_priv *priv = swdev_to_ar40xx(dev);\n\n\tmutex_lock(&priv->reg_mutex);\n\tpriv->monitor_port = val->value.i;\n\tar40xx_set_mirror_regs(priv);\n\tmutex_unlock(&priv->reg_mutex);\n\n\treturn 0;\n}\n\nstatic int\nar40xx_sw_get_mirror_monitor_port(struct switch_dev *dev,\n\t\t\t\t  const struct switch_attr *attr,\n\t\t\t\t  struct switch_val *val)\n{\n\tstruct ar40xx_priv *priv = swdev_to_ar40xx(dev);\n\n\tmutex_lock(&priv->reg_mutex);\n\tval->value.i = priv->monitor_port;\n\tmutex_unlock(&priv->reg_mutex);\n\treturn 0;\n}\n\nstatic int\nar40xx_sw_set_mirror_source_port(struct switch_dev *dev,\n\t\t\t\t const struct switch_attr *attr,\n\t\t\t\t struct switch_val *val)\n{\n\tstruct ar40xx_priv *priv = swdev_to_ar40xx(dev);\n\n\tmutex_lock(&priv->reg_mutex);\n\tpriv->source_port = val->value.i;\n\tar40xx_set_mirror_regs(priv);\n\tmutex_unlock(&priv->reg_mutex);\n\n\treturn 0;\n}\n\nstatic int\nar40xx_sw_get_mirror_source_port(struct switch_dev *dev,\n\t\t\t\t const struct switch_attr *attr,\n\t\t\t\t struct switch_val *val)\n{\n\tstruct ar40xx_priv *priv = swdev_to_ar40xx(dev);\n\n\tmutex_lock(&priv->reg_mutex);\n\tval->value.i = priv->source_port;\n\tmutex_unlock(&priv->reg_mutex);\n\treturn 0;\n}\n\nstatic int\nar40xx_sw_set_linkdown(struct switch_dev *dev,\n\t\t       const struct switch_attr *attr,\n\t\t       struct switch_val *val)\n{\n\tstruct ar40xx_priv *priv = swdev_to_ar40xx(dev);\n\n\tif (val->value.i == 1)\n\t\tar40xx_port_phy_linkdown(priv);\n\telse\n\t\tar40xx_phy_init(priv);\n\n\treturn 0;\n}\n\nstatic int\nar40xx_sw_set_port_reset_mib(struct switch_dev *dev,\n\t\t\t     const struct switch_attr *attr,\n\t\t\t     struct switch_val *val)\n{\n\tstruct ar40xx_priv *priv = swdev_to_ar40xx(dev);\n\tint port;\n\tint ret;\n\n\tport = val->port_vlan;\n\tif (port >= dev->ports)\n\t\treturn -EINVAL;\n\n\tmutex_lock(&priv->mib_lock);\n\tret = ar40xx_mib_capture(priv);\n\tif (ret)\n\t\tgoto unlock;\n\n\tar40xx_mib_fetch_port_stat(priv, port, true);\n\nunlock:\n\tmutex_unlock(&priv->mib_lock);\n\treturn ret;\n}\n\nstatic int\nar40xx_sw_get_port_mib(struct switch_dev *dev,\n\t\t       const struct switch_attr *attr,\n\t\t       struct switch_val *val)\n{\n\tstruct ar40xx_priv *priv = swdev_to_ar40xx(dev);\n\tu64 *mib_stats;\n\tint port;\n\tint ret;\n\tchar *buf = priv->buf;\n\tint i, len = 0;\n\tu32 num_mibs = ARRAY_SIZE(ar40xx_mibs);\n\n\tport = val->port_vlan;\n\tif (port >= dev->ports)\n\t\treturn -EINVAL;\n\n\tmutex_lock(&priv->mib_lock);\n\tret = ar40xx_mib_capture(priv);\n\tif (ret)\n\t\tgoto unlock;\n\n\tar40xx_mib_fetch_port_stat(priv, port, false);\n\n\tlen += snprintf(buf + len, sizeof(priv->buf) - len,\n\t\t\t\"Port %d MIB counters\\n\",\n\t\t\tport);\n\n\tmib_stats = &priv->mib_stats[port * num_mibs];\n\tfor (i = 0; i < num_mibs; i++)\n\t\tlen += snprintf(buf + len, sizeof(priv->buf) - len,\n\t\t\t\t\"%-12s: %llu\\n\",\n\t\t\t\tar40xx_mibs[i].name,\n\t\t\t\tmib_stats[i]);\n\n\tval->value.s = buf;\n\tval->len = len;\n\nunlock:\n\tmutex_unlock(&priv->mib_lock);\n\treturn ret;\n}\n\nstatic int\nar40xx_sw_set_vid(struct switch_dev *dev, const struct switch_attr *attr,\n\t\t  struct switch_val *val)\n{\n\tstruct ar40xx_priv *priv = swdev_to_ar40xx(dev);\n\n\tpriv->vlan_id[val->port_vlan] = val->value.i;\n\treturn 0;\n}\n\nstatic int\nar40xx_sw_get_vid(struct switch_dev *dev, const struct switch_attr *attr,\n\t\t  struct switch_val *val)\n{\n\tstruct ar40xx_priv *priv = swdev_to_ar40xx(dev);\n\n\tval->value.i = priv->vlan_id[val->port_vlan];\n\treturn 0;\n}\n\nstatic int\nar40xx_sw_get_pvid(struct switch_dev *dev, int port, int *vlan)\n{\n\tstruct ar40xx_priv *priv = swdev_to_ar40xx(dev);\n\t*vlan = priv->pvid[port];\n\treturn 0;\n}\n\nstatic int\nar40xx_sw_set_pvid(struct switch_dev *dev, int port, int vlan)\n{\n\tstruct ar40xx_priv *priv = swdev_to_ar40xx(dev);\n\n\t/* make sure no invalid PVIDs get set */\n\tif (vlan >= dev->vlans)\n\t\treturn -EINVAL;\n\n\tpriv->pvid[port] = vlan;\n\treturn 0;\n}\n\nstatic void\nar40xx_read_port_link(struct ar40xx_priv *priv, int port,\n\t\t      struct switch_port_link *link)\n{\n\tu32 status;\n\tu32 speed;\n\n\tmemset(link, 0, sizeof(*link));\n\n\tstatus = ar40xx_read(priv, AR40XX_REG_PORT_STATUS(port));\n\n\tlink->aneg = !!(status & AR40XX_PORT_AUTO_LINK_EN);\n\tif (link->aneg || (port != AR40XX_PORT_CPU))\n\t\tlink->link = !!(status & AR40XX_PORT_STATUS_LINK_UP);\n\telse\n\t\tlink->link = true;\n\n\tif (!link->link)\n\t\treturn;\n\n\tlink->duplex = !!(status & AR40XX_PORT_DUPLEX);\n\tlink->tx_flow = !!(status & AR40XX_PORT_STATUS_TXFLOW);\n\tlink->rx_flow = !!(status & AR40XX_PORT_STATUS_RXFLOW);\n\n\tspeed = (status & AR40XX_PORT_SPEED) >>\n\t\t AR40XX_PORT_STATUS_SPEED_S;\n\n\tswitch (speed) {\n\tcase AR40XX_PORT_SPEED_10M:\n\t\tlink->speed = SWITCH_PORT_SPEED_10;\n\t\tbreak;\n\tcase AR40XX_PORT_SPEED_100M:\n\t\tlink->speed = SWITCH_PORT_SPEED_100;\n\t\tbreak;\n\tcase AR40XX_PORT_SPEED_1000M:\n\t\tlink->speed = SWITCH_PORT_SPEED_1000;\n\t\tbreak;\n\tdefault:\n\t\tlink->speed = SWITCH_PORT_SPEED_UNKNOWN;\n\t\tbreak;\n\t}\n}\n\nstatic int\nar40xx_sw_get_port_link(struct switch_dev *dev, int port,\n\t\t\tstruct switch_port_link *link)\n{\n\tstruct ar40xx_priv *priv = swdev_to_ar40xx(dev);\n\n\tar40xx_read_port_link(priv, port, link);\n\treturn 0;\n}\n\nstatic const struct switch_attr ar40xx_sw_attr_globals[] = {\n\t{\n\t\t.type = SWITCH_TYPE_INT,\n\t\t.name = \"enable_vlan\",\n\t\t.description = \"Enable VLAN mode\",\n\t\t.set = ar40xx_sw_set_vlan,\n\t\t.get = ar40xx_sw_get_vlan,\n\t\t.max = 1\n\t},\n\t{\n\t\t.type = SWITCH_TYPE_NOVAL,\n\t\t.name = \"reset_mibs\",\n\t\t.description = \"Reset all MIB counters\",\n\t\t.set = ar40xx_sw_set_reset_mibs,\n\t},\n\t{\n\t\t.type = SWITCH_TYPE_INT,\n\t\t.name = \"enable_mirror_rx\",\n\t\t.description = \"Enable mirroring of RX packets\",\n\t\t.set = ar40xx_sw_set_mirror_rx_enable,\n\t\t.get = ar40xx_sw_get_mirror_rx_enable,\n\t\t.max = 1\n\t},\n\t{\n\t\t.type = SWITCH_TYPE_INT,\n\t\t.name = \"enable_mirror_tx\",\n\t\t.description = \"Enable mirroring of TX packets\",\n\t\t.set = ar40xx_sw_set_mirror_tx_enable,\n\t\t.get = ar40xx_sw_get_mirror_tx_enable,\n\t\t.max = 1\n\t},\n\t{\n\t\t.type = SWITCH_TYPE_INT,\n\t\t.name = \"mirror_monitor_port\",\n\t\t.description = \"Mirror monitor port\",\n\t\t.set = ar40xx_sw_set_mirror_monitor_port,\n\t\t.get = ar40xx_sw_get_mirror_monitor_port,\n\t\t.max = AR40XX_NUM_PORTS - 1\n\t},\n\t{\n\t\t.type = SWITCH_TYPE_INT,\n\t\t.name = \"mirror_source_port\",\n\t\t.description = \"Mirror source port\",\n\t\t.set = ar40xx_sw_set_mirror_source_port,\n\t\t.get = ar40xx_sw_get_mirror_source_port,\n\t\t.max = AR40XX_NUM_PORTS - 1\n\t},\n\t{\n\t\t.type = SWITCH_TYPE_INT,\n\t\t.name = \"linkdown\",\n\t\t.description = \"Link down all the PHYs\",\n\t\t.set = ar40xx_sw_set_linkdown,\n\t\t.max = 1\n\t},\n};\n\nstatic const struct switch_attr ar40xx_sw_attr_port[] = {\n\t{\n\t\t.type = SWITCH_TYPE_NOVAL,\n\t\t.name = \"reset_mib\",\n\t\t.description = \"Reset single port MIB counters\",\n\t\t.set = ar40xx_sw_set_port_reset_mib,\n\t},\n\t{\n\t\t.type = SWITCH_TYPE_STRING,\n\t\t.name = \"mib\",\n\t\t.description = \"Get port's MIB counters\",\n\t\t.set = NULL,\n\t\t.get = ar40xx_sw_get_port_mib,\n\t},\n};\n\nconst struct switch_attr ar40xx_sw_attr_vlan[] = {\n\t{\n\t\t.type = SWITCH_TYPE_INT,\n\t\t.name = \"vid\",\n\t\t.description = \"VLAN ID (0-4094)\",\n\t\t.set = ar40xx_sw_set_vid,\n\t\t.get = ar40xx_sw_get_vid,\n\t\t.max = 4094,\n\t},\n};\n\n/* End of swconfig support */\n\nstatic int\nar40xx_wait_bit(struct ar40xx_priv *priv, int reg, u32 mask, u32 val)\n{\n\tint timeout = 20;\n\tu32 t;\n\n\twhile (1) {\n\t\tt = ar40xx_read(priv, reg);\n\t\tif ((t & mask) == val)\n\t\t\treturn 0;\n\n\t\tif (timeout-- <= 0)\n\t\t\tbreak;\n\n\t\tusleep_range(10, 20);\n\t}\n\n\tpr_err(\"ar40xx: timeout for reg %08x: %08x & %08x != %08x\\n\",\n\t       (unsigned int)reg, t, mask, val);\n\treturn -ETIMEDOUT;\n}\n\nstatic int\nar40xx_atu_flush(struct ar40xx_priv *priv)\n{\n\tint ret;\n\n\tret = ar40xx_wait_bit(priv, AR40XX_REG_ATU_FUNC,\n\t\t\t      AR40XX_ATU_FUNC_BUSY, 0);\n\tif (!ret)\n\t\tar40xx_write(priv, AR40XX_REG_ATU_FUNC,\n\t\t\t     AR40XX_ATU_FUNC_OP_FLUSH |\n\t\t\t     AR40XX_ATU_FUNC_BUSY);\n\n\treturn ret;\n}\n\nstatic void\nar40xx_ess_reset(struct ar40xx_priv *priv)\n{\n\treset_control_assert(priv->ess_rst);\n\tmdelay(10);\n\treset_control_deassert(priv->ess_rst);\n\t/* Waiting for all inner tables init done.\n\t  * It cost 5~10ms.\n\t  */\n\tmdelay(10);\n\n\tpr_info(\"ESS reset ok!\\n\");\n}\n\n/* Start of psgmii self test */\n\nstatic void\nar40xx_malibu_psgmii_ess_reset(struct ar40xx_priv *priv)\n{\n\tu32 n;\n\tstruct mii_bus *bus = priv->mii_bus;\n\t/* reset phy psgmii */\n\t/* fix phy psgmii RX 20bit */\n\tmdiobus_write(bus, 5, 0x0, 0x005b);\n\t/* reset phy psgmii */\n\tmdiobus_write(bus, 5, 0x0, 0x001b);\n\t/* release reset phy psgmii */\n\tmdiobus_write(bus, 5, 0x0, 0x005b);\n\n\tfor (n = 0; n < AR40XX_PSGMII_CALB_NUM; n++) {\n\t\tu16 status;\n\n\t\tstatus = ar40xx_phy_mmd_read(priv, 5, 1, 0x28);\n\t\tif (status & BIT(0))\n\t\t\tbreak;\n\t\t/* Polling interval to check PSGMII PLL in malibu is ready\n\t\t  * the worst time is 8.67ms\n\t\t  * for 25MHz reference clock\n\t\t  * [512+(128+2048)*49]*80ns+100us\n\t\t  */\n\t\tmdelay(2);\n\t}\n\tmdelay(50);\n\n\t/*check malibu psgmii calibration done end..*/\n\n\t/*freeze phy psgmii RX CDR*/\n\tmdiobus_write(bus, 5, 0x1a, 0x2230);\n\n\tar40xx_ess_reset(priv);\n\n\t/*check psgmii calibration done start*/\n\tfor (n = 0; n < AR40XX_PSGMII_CALB_NUM; n++) {\n\t\tu32 status;\n\n\t\tstatus = ar40xx_psgmii_read(priv, 0xa0);\n\t\tif (status & BIT(0))\n\t\t\tbreak;\n\t\t/* Polling interval to check PSGMII PLL in ESS is ready */\n\t\tmdelay(2);\n\t}\n\tmdelay(50);\n\n\t/* check dakota psgmii calibration done end..*/\n\n\t/* relesae phy psgmii RX CDR */\n\tmdiobus_write(bus, 5, 0x1a, 0x3230);\n\t/* release phy psgmii RX 20bit */\n\tmdiobus_write(bus, 5, 0x0, 0x005f);\n\tmdelay(200);\n}\n\nstatic void\nar40xx_psgmii_single_phy_testing(struct ar40xx_priv *priv, int phy)\n{\n\tint j;\n\tu32 tx_ok, tx_error;\n\tu32 rx_ok, rx_error;\n\tu32 tx_ok_high16;\n\tu32 rx_ok_high16;\n\tu32 tx_all_ok, rx_all_ok;\n\tstruct mii_bus *bus = priv->mii_bus;\n\n\tmdiobus_write(bus, phy, 0x0, 0x9000);\n\tmdiobus_write(bus, phy, 0x0, 0x4140);\n\n\tfor (j = 0; j < AR40XX_PSGMII_CALB_NUM; j++) {\n\t\tu16 status;\n\n\t\tstatus = mdiobus_read(bus, phy, 0x11);\n\t\tif (status & AR40XX_PHY_SPEC_STATUS_LINK)\n\t\t\tbreak;\n\t\t/* the polling interval to check if the PHY link up or not\n\t\t  * maxwait_timer: 750 ms +/-10 ms\n\t\t  * minwait_timer : 1 us +/- 0.1us\n\t\t  * time resides in minwait_timer ~ maxwait_timer\n\t\t  * see IEEE 802.3 section 40.4.5.2\n\t\t  */\n\t\tmdelay(8);\n\t}\n\n\t/* enable check */\n\tar40xx_phy_mmd_write(priv, phy, 7, 0x8029, 0x0000);\n\tar40xx_phy_mmd_write(priv, phy, 7, 0x8029, 0x0003);\n\n\t/* start traffic */\n\tar40xx_phy_mmd_write(priv, phy, 7, 0x8020, 0xa000);\n\t/* wait for all traffic end\n\t  * 4096(pkt num)*1524(size)*8ns(125MHz)=49.9ms\n\t  */\n\tmdelay(50);\n\n\t/* check counter */\n\ttx_ok = ar40xx_phy_mmd_read(priv, phy, 7, 0x802e);\n\ttx_ok_high16 = ar40xx_phy_mmd_read(priv, phy, 7, 0x802d);\n\ttx_error = ar40xx_phy_mmd_read(priv, phy, 7, 0x802f);\n\trx_ok = ar40xx_phy_mmd_read(priv, phy, 7, 0x802b);\n\trx_ok_high16 = ar40xx_phy_mmd_read(priv, phy, 7, 0x802a);\n\trx_error = ar40xx_phy_mmd_read(priv, phy, 7, 0x802c);\n\ttx_all_ok = tx_ok + (tx_ok_high16 << 16);\n\trx_all_ok = rx_ok + (rx_ok_high16 << 16);\n\tif (tx_all_ok == 0x1000 && tx_error == 0) {\n\t\t/* success */\n\t\tpriv->phy_t_status &= (~BIT(phy));\n\t} else {\n\t\tpr_info(\"PHY %d single test PSGMII issue happen!\\n\", phy);\n\t\tpriv->phy_t_status |= BIT(phy);\n\t}\n\n\tmdiobus_write(bus, phy, 0x0, 0x1840);\n}\n\nstatic void\nar40xx_psgmii_all_phy_testing(struct ar40xx_priv *priv)\n{\n\tint phy, j;\n\tstruct mii_bus *bus = priv->mii_bus;\n\n\tmdiobus_write(bus, 0x1f, 0x0, 0x9000);\n\tmdiobus_write(bus, 0x1f, 0x0, 0x4140);\n\n\tfor (j = 0; j < AR40XX_PSGMII_CALB_NUM; j++) {\n\t\tfor (phy = 0; phy < AR40XX_NUM_PORTS - 1; phy++) {\n\t\t\tu16 status;\n\n\t\t\tstatus = mdiobus_read(bus, phy, 0x11);\n\t\t\tif (!(status & BIT(10)))\n\t\t\t\tbreak;\n\t\t}\n\n\t\tif (phy >= (AR40XX_NUM_PORTS - 1))\n\t\t\tbreak;\n\t\t/* The polling interva to check if the PHY link up or not */\n\t\tmdelay(8);\n\t}\n\t/* enable check */\n\tar40xx_phy_mmd_write(priv, 0x1f, 7, 0x8029, 0x0000);\n\tar40xx_phy_mmd_write(priv, 0x1f, 7, 0x8029, 0x0003);\n\n\t/* start traffic */\n\tar40xx_phy_mmd_write(priv, 0x1f, 7, 0x8020, 0xa000);\n\t/* wait for all traffic end\n\t  * 4096(pkt num)*1524(size)*8ns(125MHz)=49.9ms\n\t  */\n\tmdelay(50);\n\n\tfor (phy = 0; phy < AR40XX_NUM_PORTS - 1; phy++) {\n\t\tu32 tx_ok, tx_error;\n\t\tu32 rx_ok, rx_error;\n\t\tu32 tx_ok_high16;\n\t\tu32 rx_ok_high16;\n\t\tu32 tx_all_ok, rx_all_ok;\n\n\t\t/* check counter */\n\t\ttx_ok = ar40xx_phy_mmd_read(priv, phy, 7, 0x802e);\n\t\ttx_ok_high16 = ar40xx_phy_mmd_read(priv, phy, 7, 0x802d);\n\t\ttx_error = ar40xx_phy_mmd_read(priv, phy, 7, 0x802f);\n\t\trx_ok = ar40xx_phy_mmd_read(priv, phy, 7, 0x802b);\n\t\trx_ok_high16 = ar40xx_phy_mmd_read(priv, phy, 7, 0x802a);\n\t\trx_error = ar40xx_phy_mmd_read(priv, phy, 7, 0x802c);\n\t\ttx_all_ok = tx_ok + (tx_ok_high16<<16);\n\t\trx_all_ok = rx_ok + (rx_ok_high16<<16);\n\t\tif (tx_all_ok == 0x1000 && tx_error == 0) {\n\t\t\t/* success */\n\t\t\tpriv->phy_t_status &= ~BIT(phy + 8);\n\t\t} else {\n\t\t\tpr_info(\"PHY%d test see issue!\\n\", phy);\n\t\t\tpriv->phy_t_status |= BIT(phy + 8);\n\t\t}\n\t}\n\n\tpr_debug(\"PHY all test 0x%x \\r\\n\", priv->phy_t_status);\n}\n\nvoid\nar40xx_psgmii_self_test(struct ar40xx_priv *priv)\n{\n\tu32 i, phy;\n\tstruct mii_bus *bus = priv->mii_bus;\n\n\tar40xx_malibu_psgmii_ess_reset(priv);\n\n\t/* switch to access MII reg for copper */\n\tmdiobus_write(bus, 4, 0x1f, 0x8500);\n\tfor (phy = 0; phy < AR40XX_NUM_PORTS - 1; phy++) {\n\t\t/*enable phy mdio broadcast write*/\n\t\tar40xx_phy_mmd_write(priv, phy, 7, 0x8028, 0x801f);\n\t}\n\t/* force no link by power down */\n\tmdiobus_write(bus, 0x1f, 0x0, 0x1840);\n\t/*packet number*/\n\tar40xx_phy_mmd_write(priv, 0x1f, 7, 0x8021, 0x1000);\n\tar40xx_phy_mmd_write(priv, 0x1f, 7, 0x8062, 0x05e0);\n\n\t/*fix mdi status */\n\tmdiobus_write(bus, 0x1f, 0x10, 0x6800);\n\tfor (i = 0; i < AR40XX_PSGMII_CALB_NUM; i++) {\n\t\tpriv->phy_t_status = 0;\n\n\t\tfor (phy = 0; phy < AR40XX_NUM_PORTS - 1; phy++) {\n\t\t\tar40xx_rmw(priv, AR40XX_REG_PORT_LOOKUP(phy + 1),\n\t\t\t\tAR40XX_PORT_LOOKUP_LOOPBACK,\n\t\t\t\tAR40XX_PORT_LOOKUP_LOOPBACK);\n\t\t}\n\n\t\tfor (phy = 0; phy < AR40XX_NUM_PORTS - 1; phy++)\n\t\t\tar40xx_psgmii_single_phy_testing(priv, phy);\n\n\t\tar40xx_psgmii_all_phy_testing(priv);\n\n\t\tif (priv->phy_t_status)\n\t\t\tar40xx_malibu_psgmii_ess_reset(priv);\n\t\telse\n\t\t\tbreak;\n\t}\n\n\tif (i >= AR40XX_PSGMII_CALB_NUM)\n\t\tpr_info(\"PSGMII cannot recover\\n\");\n\telse\n\t\tpr_debug(\"PSGMII recovered after %d times reset\\n\", i);\n\n\t/* configuration recover */\n\t/* packet number */\n\tar40xx_phy_mmd_write(priv, 0x1f, 7, 0x8021, 0x0);\n\t/* disable check */\n\tar40xx_phy_mmd_write(priv, 0x1f, 7, 0x8029, 0x0);\n\t/* disable traffic */\n\tar40xx_phy_mmd_write(priv, 0x1f, 7, 0x8020, 0x0);\n}\n\nvoid\nar40xx_psgmii_self_test_clean(struct ar40xx_priv *priv)\n{\n\tint phy;\n\tstruct mii_bus *bus = priv->mii_bus;\n\n\t/* disable phy internal loopback */\n\tmdiobus_write(bus, 0x1f, 0x10, 0x6860);\n\tmdiobus_write(bus, 0x1f, 0x0, 0x9040);\n\n\tfor (phy = 0; phy < AR40XX_NUM_PORTS - 1; phy++) {\n\t\t/* disable mac loop back */\n\t\tar40xx_rmw(priv, AR40XX_REG_PORT_LOOKUP(phy + 1),\n\t\t\t\tAR40XX_PORT_LOOKUP_LOOPBACK, 0);\n\t\t/* disable phy mdio broadcast write */\n\t\tar40xx_phy_mmd_write(priv, phy, 7, 0x8028, 0x001f);\n\t}\n\n\t/* clear fdb entry */\n\tar40xx_atu_flush(priv);\n}\n\n/* End of psgmii self test */\n\nstatic void\nar40xx_mac_mode_init(struct ar40xx_priv *priv, u32 mode)\n{\n\tif (mode == PORT_WRAPPER_PSGMII) {\n\t\tar40xx_psgmii_write(priv, AR40XX_PSGMII_MODE_CONTROL, 0x2200);\n\t\tar40xx_psgmii_write(priv, AR40XX_PSGMIIPHY_TX_CONTROL, 0x8380);\n\t}\n}\n\nstatic\nint ar40xx_cpuport_setup(struct ar40xx_priv *priv)\n{\n\tu32 t;\n\n\tt = AR40XX_PORT_STATUS_TXFLOW |\n\t     AR40XX_PORT_STATUS_RXFLOW |\n\t     AR40XX_PORT_TXHALF_FLOW |\n\t     AR40XX_PORT_DUPLEX |\n\t     AR40XX_PORT_SPEED_1000M;\n\tar40xx_write(priv, AR40XX_REG_PORT_STATUS(0), t);\n\tusleep_range(10, 20);\n\n\tt |= AR40XX_PORT_TX_EN |\n\t       AR40XX_PORT_RX_EN;\n\tar40xx_write(priv, AR40XX_REG_PORT_STATUS(0), t);\n\n\treturn 0;\n}\n\nstatic void\nar40xx_init_port(struct ar40xx_priv *priv, int port)\n{\n\tu32 t;\n\n\tar40xx_write(priv, AR40XX_REG_PORT_STATUS(port), 0);\n\n\tar40xx_write(priv, AR40XX_REG_PORT_HEADER(port), 0);\n\n\tar40xx_write(priv, AR40XX_REG_PORT_VLAN0(port), 0);\n\n\tt = AR40XX_PORT_VLAN1_OUT_MODE_UNTOUCH << AR40XX_PORT_VLAN1_OUT_MODE_S;\n\tar40xx_write(priv, AR40XX_REG_PORT_VLAN1(port), t);\n\n\tt = AR40XX_PORT_LOOKUP_LEARN;\n\tt |= AR40XX_PORT_STATE_FORWARD << AR40XX_PORT_LOOKUP_STATE_S;\n\tar40xx_write(priv, AR40XX_REG_PORT_LOOKUP(port), t);\n}\n\nvoid\nar40xx_init_globals(struct ar40xx_priv *priv)\n{\n\tu32 t;\n\n\t/* enable CPU port and disable mirror port */\n\tt = AR40XX_FWD_CTRL0_CPU_PORT_EN |\n\t    AR40XX_FWD_CTRL0_MIRROR_PORT;\n\tar40xx_write(priv, AR40XX_REG_FWD_CTRL0, t);\n\n\t/* forward multicast and broadcast frames to CPU */\n\tt = (AR40XX_PORTS_ALL << AR40XX_FWD_CTRL1_UC_FLOOD_S) |\n\t    (AR40XX_PORTS_ALL << AR40XX_FWD_CTRL1_MC_FLOOD_S) |\n\t    (AR40XX_PORTS_ALL << AR40XX_FWD_CTRL1_BC_FLOOD_S);\n\tar40xx_write(priv, AR40XX_REG_FWD_CTRL1, t);\n\n\t/* enable jumbo frames */\n\tar40xx_rmw(priv, AR40XX_REG_MAX_FRAME_SIZE,\n\t\t   AR40XX_MAX_FRAME_SIZE_MTU, 9018 + 8 + 2);\n\n\t/* Enable MIB counters */\n\tar40xx_rmw(priv, AR40XX_REG_MODULE_EN, 0,\n\t\t   AR40XX_MODULE_EN_MIB);\n\n\t/* Disable AZ */\n\tar40xx_write(priv, AR40XX_REG_EEE_CTRL, 0);\n\n\t/* set flowctrl thershold for cpu port */\n\tt = (AR40XX_PORT0_FC_THRESH_ON_DFLT << 16) |\n\t      AR40XX_PORT0_FC_THRESH_OFF_DFLT;\n\tar40xx_write(priv, AR40XX_REG_PORT_FLOWCTRL_THRESH(0), t);\n}\n\nstatic int\nar40xx_hw_init(struct ar40xx_priv *priv)\n{\n\tu32 i;\n\n\tar40xx_ess_reset(priv);\n\n\tif (!priv->mii_bus)\n\t\treturn -1;\n\n\tar40xx_psgmii_self_test(priv);\n\tar40xx_psgmii_self_test_clean(priv);\n\n\tar40xx_mac_mode_init(priv, priv->mac_mode);\n\n\tfor (i = 0; i < priv->dev.ports; i++)\n\t\tar40xx_init_port(priv, i);\n\n\tar40xx_init_globals(priv);\n\n\treturn 0;\n}\n\n/* Start of qm error WAR */\n\nstatic\nint ar40xx_force_1g_full(struct ar40xx_priv *priv, u32 port_id)\n{\n\tu32 reg;\n\n\tif (port_id < 0 || port_id > 6)\n\t\treturn -1;\n\n\treg = AR40XX_REG_PORT_STATUS(port_id);\n\treturn ar40xx_rmw(priv, reg, AR40XX_PORT_SPEED,\n\t\t\t(AR40XX_PORT_SPEED_1000M | AR40XX_PORT_DUPLEX));\n}\n\nstatic\nint ar40xx_get_qm_status(struct ar40xx_priv *priv,\n\t\t\t u32 port_id, u32 *qm_buffer_err)\n{\n\tu32 reg;\n\tu32 qm_val;\n\n\tif (port_id < 1 || port_id > 5) {\n\t\t*qm_buffer_err = 0;\n\t\treturn -1;\n\t}\n\n\tif (port_id < 4) {\n\t\treg = AR40XX_REG_QM_PORT0_3_QNUM;\n\t\tar40xx_write(priv, AR40XX_REG_QM_DEBUG_ADDR, reg);\n\t\tqm_val = ar40xx_read(priv, AR40XX_REG_QM_DEBUG_VALUE);\n\t\t/* every 8 bits for each port */\n\t\t*qm_buffer_err = (qm_val >> (port_id * 8)) & 0xFF;\n\t} else {\n\t\treg = AR40XX_REG_QM_PORT4_6_QNUM;\n\t\tar40xx_write(priv, AR40XX_REG_QM_DEBUG_ADDR, reg);\n\t\tqm_val = ar40xx_read(priv, AR40XX_REG_QM_DEBUG_VALUE);\n\t\t/* every 8 bits for each port */\n\t\t*qm_buffer_err = (qm_val >> ((port_id-4) * 8)) & 0xFF;\n\t}\n\n\treturn 0;\n}\n\nstatic void\nar40xx_sw_mac_polling_task(struct ar40xx_priv *priv)\n{\n\tstatic int task_count;\n\tu32 i;\n\tu32 reg, value;\n\tu32 link, speed, duplex;\n\tu32 qm_buffer_err;\n\tu16 port_phy_status[AR40XX_NUM_PORTS];\n\tstatic u32 qm_err_cnt[AR40XX_NUM_PORTS] = {0, 0, 0, 0, 0, 0};\n\tstatic u32 link_cnt[AR40XX_NUM_PORTS] = {0, 0, 0, 0, 0, 0};\n\tstruct mii_bus *bus = NULL;\n\n\tif (!priv || !priv->mii_bus)\n\t\treturn;\n\n\tbus = priv->mii_bus;\n\n\t++task_count;\n\n\tfor (i = 1; i < AR40XX_NUM_PORTS; ++i) {\n\t\tport_phy_status[i] =\n\t\t\tmdiobus_read(bus, i-1, AR40XX_PHY_SPEC_STATUS);\n\n\t\tspeed = FIELD_GET(AR40XX_PHY_SPEC_STATUS_SPEED,\n\t\t\t\t  port_phy_status[i]);\n\t\tlink = FIELD_GET(AR40XX_PHY_SPEC_STATUS_LINK,\n\t\t\t\t port_phy_status[i]);\n\t\tduplex = FIELD_GET(AR40XX_PHY_SPEC_STATUS_DUPLEX,\n\t\t\t\t   port_phy_status[i]);\n\n\t\tif (link != priv->ar40xx_port_old_link[i]) {\n\t\t\t++link_cnt[i];\n\t\t\t/* Up --> Down */\n\t\t\tif ((priv->ar40xx_port_old_link[i] ==\n\t\t\t\t\tAR40XX_PORT_LINK_UP) &&\n\t\t\t    (link == AR40XX_PORT_LINK_DOWN)) {\n\t\t\t\t/* LINK_EN disable(MAC force mode)*/\n\t\t\t\treg = AR40XX_REG_PORT_STATUS(i);\n\t\t\t\tar40xx_rmw(priv, reg,\n\t\t\t\t\t\tAR40XX_PORT_AUTO_LINK_EN, 0);\n\n\t\t\t\t/* Check queue buffer */\n\t\t\t\tqm_err_cnt[i] = 0;\n\t\t\t\tar40xx_get_qm_status(priv, i, &qm_buffer_err);\n\t\t\t\tif (qm_buffer_err) {\n\t\t\t\t\tpriv->ar40xx_port_qm_buf[i] =\n\t\t\t\t\t\tAR40XX_QM_NOT_EMPTY;\n\t\t\t\t} else {\n\t\t\t\t\tu16 phy_val = 0;\n\n\t\t\t\t\tpriv->ar40xx_port_qm_buf[i] =\n\t\t\t\t\t\tAR40XX_QM_EMPTY;\n\t\t\t\t\tar40xx_force_1g_full(priv, i);\n\t\t\t\t\t/* Ref:QCA8337 Datasheet,Clearing\n\t\t\t\t\t * MENU_CTRL_EN prevents phy to\n\t\t\t\t\t * stuck in 100BT mode when\n\t\t\t\t\t * bringing up the link\n\t\t\t\t\t */\n\t\t\t\t\tar40xx_phy_dbg_read(priv, i-1,\n\t\t\t\t\t\t\t    AR40XX_PHY_DEBUG_0,\n\t\t\t\t\t\t\t    &phy_val);\n\t\t\t\t\tphy_val &= (~AR40XX_PHY_MANU_CTRL_EN);\n\t\t\t\t\tar40xx_phy_dbg_write(priv, i-1,\n\t\t\t\t\t\t\t     AR40XX_PHY_DEBUG_0,\n\t\t\t\t\t\t\t     phy_val);\n\t\t\t\t}\n\t\t\t\tpriv->ar40xx_port_old_link[i] = link;\n\t\t\t} else if ((priv->ar40xx_port_old_link[i] ==\n\t\t\t\t\t\tAR40XX_PORT_LINK_DOWN) &&\n\t\t\t\t\t(link == AR40XX_PORT_LINK_UP)) {\n\t\t\t\t/* Down --> Up */\n\t\t\t\tif (priv->port_link_up[i] < 1) {\n\t\t\t\t\t++priv->port_link_up[i];\n\t\t\t\t} else {\n\t\t\t\t\t/* Change port status */\n\t\t\t\t\treg = AR40XX_REG_PORT_STATUS(i);\n\t\t\t\t\tvalue = ar40xx_read(priv, reg);\n\t\t\t\t\tpriv->port_link_up[i] = 0;\n\n\t\t\t\t\tvalue &= ~(AR40XX_PORT_DUPLEX |\n\t\t\t\t\t\t   AR40XX_PORT_SPEED);\n\t\t\t\t\tvalue |= speed | (duplex ? BIT(6) : 0);\n\t\t\t\t\tar40xx_write(priv, reg, value);\n\t\t\t\t\t/* clock switch need such time\n\t\t\t\t\t * to avoid glitch\n\t\t\t\t\t */\n\t\t\t\t\tusleep_range(100, 200);\n\n\t\t\t\t\tvalue |= AR40XX_PORT_AUTO_LINK_EN;\n\t\t\t\t\tar40xx_write(priv, reg, value);\n\t\t\t\t\t/* HW need such time to make sure link\n\t\t\t\t\t * stable before enable MAC\n\t\t\t\t\t */\n\t\t\t\t\tusleep_range(100, 200);\n\n\t\t\t\t\tif (speed == AR40XX_PORT_SPEED_100M) {\n\t\t\t\t\t\tu16 phy_val = 0;\n\t\t\t\t\t\t/* Enable @100M, if down to 10M\n\t\t\t\t\t\t * clock will change smoothly\n\t\t\t\t\t\t */\n\t\t\t\t\t\tar40xx_phy_dbg_read(priv, i-1,\n\t\t\t\t\t\t\t\t    0,\n\t\t\t\t\t\t\t\t    &phy_val);\n\t\t\t\t\t\tphy_val |=\n\t\t\t\t\t\t\tAR40XX_PHY_MANU_CTRL_EN;\n\t\t\t\t\t\tar40xx_phy_dbg_write(priv, i-1,\n\t\t\t\t\t\t\t\t     0,\n\t\t\t\t\t\t\t\t     phy_val);\n\t\t\t\t\t}\n\t\t\t\t\tpriv->ar40xx_port_old_link[i] = link;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n\t\tif (priv->ar40xx_port_qm_buf[i] == AR40XX_QM_NOT_EMPTY) {\n\t\t\t/* Check QM */\n\t\t\tar40xx_get_qm_status(priv, i, &qm_buffer_err);\n\t\t\tif (qm_buffer_err) {\n\t\t\t\t++qm_err_cnt[i];\n\t\t\t} else {\n\t\t\t\tpriv->ar40xx_port_qm_buf[i] =\n\t\t\t\t\t\tAR40XX_QM_EMPTY;\n\t\t\t\tqm_err_cnt[i] = 0;\n\t\t\t\tar40xx_force_1g_full(priv, i);\n\t\t\t}\n\t\t}\n\t}\n}\n\nstatic void\nar40xx_qm_err_check_work_task(struct work_struct *work)\n{\n\tstruct ar40xx_priv *priv = container_of(work, struct ar40xx_priv,\n\t\t\t\t\tqm_dwork.work);\n\n\tmutex_lock(&priv->qm_lock);\n\n\tar40xx_sw_mac_polling_task(priv);\n\n\tmutex_unlock(&priv->qm_lock);\n\n\tschedule_delayed_work(&priv->qm_dwork,\n\t\t\t      msecs_to_jiffies(AR40XX_QM_WORK_DELAY));\n}\n\nstatic int\nar40xx_qm_err_check_work_start(struct ar40xx_priv *priv)\n{\n\tmutex_init(&priv->qm_lock);\n\n\tINIT_DELAYED_WORK(&priv->qm_dwork, ar40xx_qm_err_check_work_task);\n\n\tschedule_delayed_work(&priv->qm_dwork,\n\t\t\t      msecs_to_jiffies(AR40XX_QM_WORK_DELAY));\n\n\treturn 0;\n}\n\n/* End of qm error WAR */\n\nstatic int\nar40xx_vlan_init(struct ar40xx_priv *priv)\n{\n\tint port;\n\tunsigned long bmp;\n\n\t/* By default Enable VLAN */\n\tpriv->vlan = 1;\n\tpriv->vlan_table[AR40XX_LAN_VLAN] = priv->cpu_bmp | priv->lan_bmp;\n\tpriv->vlan_table[AR40XX_WAN_VLAN] = priv->cpu_bmp | priv->wan_bmp;\n\tpriv->vlan_tagged = priv->cpu_bmp;\n\tbmp = priv->lan_bmp;\n\tfor_each_set_bit(port, &bmp, AR40XX_NUM_PORTS)\n\t\t\tpriv->pvid[port] = AR40XX_LAN_VLAN;\n\n\tbmp = priv->wan_bmp;\n\tfor_each_set_bit(port, &bmp, AR40XX_NUM_PORTS)\n\t\t\tpriv->pvid[port] = AR40XX_WAN_VLAN;\n\n\treturn 0;\n}\n\nstatic void\nar40xx_mib_work_func(struct work_struct *work)\n{\n\tstruct ar40xx_priv *priv;\n\tint err;\n\n\tpriv = container_of(work, struct ar40xx_priv, mib_work.work);\n\n\tmutex_lock(&priv->mib_lock);\n\n\terr = ar40xx_mib_capture(priv);\n\tif (err)\n\t\tgoto next_port;\n\n\tar40xx_mib_fetch_port_stat(priv, priv->mib_next_port, false);\n\nnext_port:\n\tpriv->mib_next_port++;\n\tif (priv->mib_next_port >= priv->dev.ports)\n\t\tpriv->mib_next_port = 0;\n\n\tmutex_unlock(&priv->mib_lock);\n\n\tschedule_delayed_work(&priv->mib_work,\n\t\t\t      msecs_to_jiffies(AR40XX_MIB_WORK_DELAY));\n}\n\nstatic void\nar40xx_setup_port(struct ar40xx_priv *priv, int port, u32 members)\n{\n\tu32 t;\n\tu32 egress, ingress;\n\tu32 pvid = priv->vlan_id[priv->pvid[port]];\n\n\tif (priv->vlan) {\n\t\tegress = AR40XX_PORT_VLAN1_OUT_MODE_UNMOD;\n\n\t\tingress = AR40XX_IN_SECURE;\n\t} else {\n\t\tegress = AR40XX_PORT_VLAN1_OUT_MODE_UNTOUCH;\n\t\tingress = AR40XX_IN_PORT_ONLY;\n\t}\n\n\tt = pvid << AR40XX_PORT_VLAN0_DEF_SVID_S;\n\tt |= pvid << AR40XX_PORT_VLAN0_DEF_CVID_S;\n\tar40xx_write(priv, AR40XX_REG_PORT_VLAN0(port), t);\n\n\tt = AR40XX_PORT_VLAN1_PORT_VLAN_PROP;\n\tt |= egress << AR40XX_PORT_VLAN1_OUT_MODE_S;\n\n\tar40xx_write(priv, AR40XX_REG_PORT_VLAN1(port), t);\n\n\tt = members;\n\tt |= AR40XX_PORT_LOOKUP_LEARN;\n\tt |= ingress << AR40XX_PORT_LOOKUP_IN_MODE_S;\n\tt |= AR40XX_PORT_STATE_FORWARD << AR40XX_PORT_LOOKUP_STATE_S;\n\tar40xx_write(priv, AR40XX_REG_PORT_LOOKUP(port), t);\n}\n\nstatic void\nar40xx_vtu_op(struct ar40xx_priv *priv, u32 op, u32 val)\n{\n\tif (ar40xx_wait_bit(priv, AR40XX_REG_VTU_FUNC1,\n\t\t\t    AR40XX_VTU_FUNC1_BUSY, 0))\n\t\treturn;\n\n\tif ((op & AR40XX_VTU_FUNC1_OP) == AR40XX_VTU_FUNC1_OP_LOAD)\n\t\tar40xx_write(priv, AR40XX_REG_VTU_FUNC0, val);\n\n\top |= AR40XX_VTU_FUNC1_BUSY;\n\tar40xx_write(priv, AR40XX_REG_VTU_FUNC1, op);\n}\n\nstatic void\nar40xx_vtu_load_vlan(struct ar40xx_priv *priv, u32 vid, u32 port_mask)\n{\n\tu32 op;\n\tu32 val;\n\tint i;\n\n\top = AR40XX_VTU_FUNC1_OP_LOAD | (vid << AR40XX_VTU_FUNC1_VID_S);\n\tval = AR40XX_VTU_FUNC0_VALID | AR40XX_VTU_FUNC0_IVL;\n\tfor (i = 0; i < AR40XX_NUM_PORTS; i++) {\n\t\tu32 mode;\n\n\t\tif ((port_mask & BIT(i)) == 0)\n\t\t\tmode = AR40XX_VTU_FUNC0_EG_MODE_NOT;\n\t\telse if (priv->vlan == 0)\n\t\t\tmode = AR40XX_VTU_FUNC0_EG_MODE_KEEP;\n\t\telse if ((priv->vlan_tagged & BIT(i)) ||\n\t\t\t (priv->vlan_id[priv->pvid[i]] != vid))\n\t\t\tmode = AR40XX_VTU_FUNC0_EG_MODE_TAG;\n\t\telse\n\t\t\tmode = AR40XX_VTU_FUNC0_EG_MODE_UNTAG;\n\n\t\tval |= mode << AR40XX_VTU_FUNC0_EG_MODE_S(i);\n\t}\n\tar40xx_vtu_op(priv, op, val);\n}\n\nstatic void\nar40xx_vtu_flush(struct ar40xx_priv *priv)\n{\n\tar40xx_vtu_op(priv, AR40XX_VTU_FUNC1_OP_FLUSH, 0);\n}\n\nstatic int\nar40xx_sw_hw_apply(struct switch_dev *dev)\n{\n\tstruct ar40xx_priv *priv = swdev_to_ar40xx(dev);\n\tu8 portmask[AR40XX_NUM_PORTS];\n\tint i, j;\n\n\tmutex_lock(&priv->reg_mutex);\n\t/* flush all vlan entries */\n\tar40xx_vtu_flush(priv);\n\n\tmemset(portmask, 0, sizeof(portmask));\n\tif (priv->vlan) {\n\t\tfor (j = 0; j < AR40XX_MAX_VLANS; j++) {\n\t\t\tu8 vp = priv->vlan_table[j];\n\n\t\t\tif (!vp)\n\t\t\t\tcontinue;\n\n\t\t\tfor (i = 0; i < dev->ports; i++) {\n\t\t\t\tu8 mask = BIT(i);\n\n\t\t\t\tif (vp & mask)\n\t\t\t\t\tportmask[i] |= vp & ~mask;\n\t\t\t}\n\n\t\t\tar40xx_vtu_load_vlan(priv, priv->vlan_id[j],\n\t\t\t\t\t     priv->vlan_table[j]);\n\t\t}\n\t} else {\n\t\t/* 8021q vlan disabled */\n\t\tfor (i = 0; i < dev->ports; i++) {\n\t\t\tif (i == AR40XX_PORT_CPU)\n\t\t\t\tcontinue;\n\n\t\t\tportmask[i] = BIT(AR40XX_PORT_CPU);\n\t\t\tportmask[AR40XX_PORT_CPU] |= BIT(i);\n\t\t}\n\t}\n\n\t/* update the port destination mask registers and tag settings */\n\tfor (i = 0; i < dev->ports; i++)\n\t\tar40xx_setup_port(priv, i, portmask[i]);\n\n\tar40xx_set_mirror_regs(priv);\n\n\tmutex_unlock(&priv->reg_mutex);\n\treturn 0;\n}\n\nstatic int\nar40xx_sw_reset_switch(struct switch_dev *dev)\n{\n\tstruct ar40xx_priv *priv = swdev_to_ar40xx(dev);\n\tint i, rv;\n\n\tmutex_lock(&priv->reg_mutex);\n\tmemset(&priv->vlan, 0, sizeof(struct ar40xx_priv) -\n\t\toffsetof(struct ar40xx_priv, vlan));\n\n\tfor (i = 0; i < AR40XX_MAX_VLANS; i++)\n\t\tpriv->vlan_id[i] = i;\n\n\tar40xx_vlan_init(priv);\n\n\tpriv->mirror_rx = false;\n\tpriv->mirror_tx = false;\n\tpriv->source_port = 0;\n\tpriv->monitor_port = 0;\n\n\tmutex_unlock(&priv->reg_mutex);\n\n\trv = ar40xx_sw_hw_apply(dev);\n\treturn rv;\n}\n\nstatic int\nar40xx_start(struct ar40xx_priv *priv)\n{\n\tint ret;\n\n\tret = ar40xx_hw_init(priv);\n\tif (ret)\n\t\treturn ret;\n\n\tret = ar40xx_sw_reset_switch(&priv->dev);\n\tif (ret)\n\t\treturn ret;\n\n\t/* at last, setup cpu port */\n\tret = ar40xx_cpuport_setup(priv);\n\tif (ret)\n\t\treturn ret;\n\n\tschedule_delayed_work(&priv->mib_work,\n\t\t\t      msecs_to_jiffies(AR40XX_MIB_WORK_DELAY));\n\n\tar40xx_qm_err_check_work_start(priv);\n\n\treturn 0;\n}\n\nstatic const struct switch_dev_ops ar40xx_sw_ops = {\n\t.attr_global = {\n\t\t.attr = ar40xx_sw_attr_globals,\n\t\t.n_attr = ARRAY_SIZE(ar40xx_sw_attr_globals),\n\t},\n\t.attr_port = {\n\t\t.attr = ar40xx_sw_attr_port,\n\t\t.n_attr = ARRAY_SIZE(ar40xx_sw_attr_port),\n\t},\n\t.attr_vlan = {\n\t\t.attr = ar40xx_sw_attr_vlan,\n\t\t.n_attr = ARRAY_SIZE(ar40xx_sw_attr_vlan),\n\t},\n\t.get_port_pvid = ar40xx_sw_get_pvid,\n\t.set_port_pvid = ar40xx_sw_set_pvid,\n\t.get_vlan_ports = ar40xx_sw_get_ports,\n\t.set_vlan_ports = ar40xx_sw_set_ports,\n\t.apply_config = ar40xx_sw_hw_apply,\n\t.reset_switch = ar40xx_sw_reset_switch,\n\t.get_port_link = ar40xx_sw_get_port_link,\n};\n\n/* Platform driver probe function */\n\nstatic int ar40xx_probe(struct platform_device *pdev)\n{\n\tstruct device_node *switch_node;\n\tstruct device_node *psgmii_node;\n\tstruct device_node *mdio_node;\n\tconst __be32 *mac_mode;\n\tstruct clk *ess_clk;\n\tstruct switch_dev *swdev;\n\tstruct ar40xx_priv *priv;\n\tu32 len;\n\tu32 num_mibs;\n\tstruct resource psgmii_base = {0};\n\tstruct resource switch_base = {0};\n\tint ret;\n\n\tpriv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);\n\tif (!priv)\n\t\treturn -ENOMEM;\n\n\tplatform_set_drvdata(pdev, priv);\n\tar40xx_priv = priv;\n\n\tswitch_node = of_node_get(pdev->dev.of_node);\n\tif (of_address_to_resource(switch_node, 0, &switch_base) != 0)\n\t\treturn -EIO;\n\n\tpriv->hw_addr = devm_ioremap_resource(&pdev->dev, &switch_base);\n\tif (IS_ERR(priv->hw_addr)) {\n\t\tdev_err(&pdev->dev, \"Failed to ioremap switch_base!\\n\");\n\t\treturn PTR_ERR(priv->hw_addr);\n\t}\n\n\t/*psgmii dts get*/\n\tpsgmii_node = of_find_node_by_name(NULL, \"ess-psgmii\");\n\tif (!psgmii_node) {\n\t\tdev_err(&pdev->dev, \"Failed to find ess-psgmii node!\\n\");\n\t\treturn -EINVAL;\n\t}\n\n\tif (of_address_to_resource(psgmii_node, 0, &psgmii_base) != 0)\n\t\treturn -EIO;\n\n\tpriv->psgmii_hw_addr = devm_ioremap_resource(&pdev->dev, &psgmii_base);\n\tif (IS_ERR(priv->psgmii_hw_addr)) {\n\t\tdev_err(&pdev->dev, \"psgmii ioremap fail!\\n\");\n\t\treturn PTR_ERR(priv->psgmii_hw_addr);\n\t}\n\n\tmac_mode = of_get_property(switch_node, \"switch_mac_mode\", &len);\n\tif (!mac_mode) {\n\t\tdev_err(&pdev->dev, \"Failed to read switch_mac_mode\\n\");\n\t\treturn -EINVAL;\n\t}\n\tpriv->mac_mode = be32_to_cpup(mac_mode);\n\n\tess_clk = of_clk_get_by_name(switch_node, \"ess_clk\");\n\tif (ess_clk)\n\t\tclk_prepare_enable(ess_clk);\n\n\tpriv->ess_rst = devm_reset_control_get(&pdev->dev, \"ess_rst\");\n\tif (IS_ERR(priv->ess_rst)) {\n\t\tdev_err(&pdev->dev, \"Failed to get ess_rst control!\\n\");\n\t\treturn PTR_ERR(priv->ess_rst);\n\t}\n\n\tif (of_property_read_u32(switch_node, \"switch_cpu_bmp\",\n\t\t\t\t &priv->cpu_bmp) ||\n\t    of_property_read_u32(switch_node, \"switch_lan_bmp\",\n\t\t\t\t &priv->lan_bmp) ||\n\t    of_property_read_u32(switch_node, \"switch_wan_bmp\",\n\t\t\t\t &priv->wan_bmp)) {\n\t\tdev_err(&pdev->dev, \"Failed to read port properties\\n\");\n\t\treturn -EIO;\n\t}\n\n\tmutex_init(&priv->reg_mutex);\n\tmutex_init(&priv->mib_lock);\n\tINIT_DELAYED_WORK(&priv->mib_work, ar40xx_mib_work_func);\n\n\t/* register switch */\n\tswdev = &priv->dev;\n\n\tmdio_node = of_find_compatible_node(NULL, NULL, \"qcom,ipq4019-mdio\");\n\tif (!mdio_node) {\n\t\tdev_err(&pdev->dev, \"Probe failed - Cannot find mdio node by phandle!\\n\");\n\t\tret = -ENODEV;\n\t\tgoto err_missing_phy;\n\t}\n\n\tpriv->mii_bus = of_mdio_find_bus(mdio_node);\n\n\tif (priv->mii_bus == NULL) {\n\t\tdev_err(&pdev->dev, \"Probe failed - Missing PHYs!\\n\");\n\t\tret = -ENODEV;\n\t\tgoto err_missing_phy;\n\t}\n\n\tswdev->alias = dev_name(&priv->mii_bus->dev);\n\n\tswdev->cpu_port = AR40XX_PORT_CPU;\n\tswdev->name = \"QCA AR40xx\";\n\tswdev->vlans = AR40XX_MAX_VLANS;\n\tswdev->ports = AR40XX_NUM_PORTS;\n\tswdev->ops = &ar40xx_sw_ops;\n\tret = register_switch(swdev, NULL);\n\tif (ret < 0) {\n\t\tdev_err(&pdev->dev, \"Switch registration failed!\\n\");\n\t\treturn ret;\n\t}\n\n\tnum_mibs = ARRAY_SIZE(ar40xx_mibs);\n\tlen = priv->dev.ports * num_mibs *\n\t      sizeof(*priv->mib_stats);\n\tpriv->mib_stats = devm_kzalloc(&pdev->dev, len, GFP_KERNEL);\n\tif (!priv->mib_stats) {\n\t\tret = -ENOMEM;\n\t\tgoto err_unregister_switch;\n\t}\n\n\tar40xx_start(priv);\n\n\treturn 0;\n\nerr_unregister_switch:\n\tunregister_switch(&priv->dev);\nerr_missing_phy:\n\tplatform_set_drvdata(pdev, NULL);\n\treturn ret;\n}\n\nstatic int ar40xx_remove(struct platform_device *pdev)\n{\n\tstruct ar40xx_priv *priv = platform_get_drvdata(pdev);\n\n\tcancel_delayed_work_sync(&priv->qm_dwork);\n\tcancel_delayed_work_sync(&priv->mib_work);\n\n\tunregister_switch(&priv->dev);\n\n\treturn 0;\n}\n\nstatic const struct of_device_id ar40xx_of_mtable[] = {\n\t{.compatible = \"qcom,ess-switch\" },\n\t{}\n};\n\nstruct platform_driver ar40xx_drv = {\n\t.probe = ar40xx_probe,\n\t.remove = ar40xx_remove,\n\t.driver = {\n\t\t.name    = \"ar40xx\",\n\t\t.of_match_table = ar40xx_of_mtable,\n\t},\n};\n\nmodule_platform_driver(ar40xx_drv);\n\nMODULE_DESCRIPTION(\"IPQ40XX ESS driver\");\nMODULE_LICENSE(\"Dual BSD/GPL\");\n"
  },
  {
    "path": "target/linux/ipq40xx/files/drivers/net/mdio/ar40xx.h",
    "content": "/*\n * Copyright (c) 2016, The Linux Foundation. All rights reserved.\n *\n * Permission to use, copy, modify, and/or distribute this software for\n * any purpose with or without fee is hereby granted, provided that the\n * above copyright notice and this permission notice appear in all copies.\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT\n * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n */\n\n #ifndef __AR40XX_H\n#define __AR40XX_H\n\n#define AR40XX_MAX_VLANS\t128\n#define AR40XX_NUM_PORTS\t6\n#define AR40XX_NUM_PHYS\t5\n\n#define BITS(_s, _n)\t(((1UL << (_n)) - 1) << _s)\n\nstruct ar40xx_priv {\n\tstruct switch_dev dev;\n\n\tu8  __iomem      *hw_addr;\n\tu8  __iomem      *psgmii_hw_addr;\n\tu32 mac_mode;\n\tstruct reset_control *ess_rst;\n\tu32 cpu_bmp;\n\tu32 lan_bmp;\n\tu32 wan_bmp;\n\n\tstruct mii_bus *mii_bus;\n\tstruct phy_device *phy;\n\n\t/* mutex for qm task */\n\tstruct mutex qm_lock;\n\tstruct delayed_work qm_dwork;\n\tu32 port_link_up[AR40XX_NUM_PORTS];\n\tu32 ar40xx_port_old_link[AR40XX_NUM_PORTS];\n\tu32 ar40xx_port_qm_buf[AR40XX_NUM_PORTS];\n\n\tu32 phy_t_status;\n\n\t/* mutex for switch reg access */\n\tstruct mutex reg_mutex;\n\n\t/* mutex for mib task */\n\tstruct mutex mib_lock;\n\tstruct delayed_work mib_work;\n\tint mib_next_port;\n\tu64 *mib_stats;\n\n\tchar buf[2048];\n\n\t/* all fields below will be cleared on reset */\n\tbool vlan;\n\tu16 vlan_id[AR40XX_MAX_VLANS];\n\tu8 vlan_table[AR40XX_MAX_VLANS];\n\tu8 vlan_tagged;\n\tu16 pvid[AR40XX_NUM_PORTS];\n\n\t/* mirror */\n\tbool mirror_rx;\n\tbool mirror_tx;\n\tint source_port;\n\tint monitor_port;\n};\n\n#define AR40XX_PORT_LINK_UP 1\n#define AR40XX_PORT_LINK_DOWN 0\n#define AR40XX_QM_NOT_EMPTY  1\n#define AR40XX_QM_EMPTY  0\n\n#define AR40XX_LAN_VLAN\t1\n#define AR40XX_WAN_VLAN\t2\n\nenum ar40xx_port_wrapper_cfg {\n\tPORT_WRAPPER_PSGMII = 0,\n};\n\nstruct ar40xx_mib_desc {\n\tu32 size;\n\tu32 offset;\n\tconst char *name;\n};\n\n#define AR40XX_PORT_CPU\t0\n\n#define AR40XX_PSGMII_MODE_CONTROL\t0x1b4\n#define   AR40XX_PSGMII_ATHR_CSCO_MODE_25M\tBIT(0)\n\n#define AR40XX_PSGMIIPHY_TX_CONTROL\t 0x288\n\n#define AR40XX_MII_ATH_MMD_ADDR\t\t0x0d\n#define AR40XX_MII_ATH_MMD_DATA\t\t0x0e\n#define AR40XX_MII_ATH_DBG_ADDR\t\t0x1d\n#define AR40XX_MII_ATH_DBG_DATA\t\t0x1e\n\n#define AR40XX_STATS_RXBROAD\t\t0x00\n#define AR40XX_STATS_RXPAUSE\t\t0x04\n#define AR40XX_STATS_RXMULTI\t\t0x08\n#define AR40XX_STATS_RXFCSERR\t\t0x0c\n#define AR40XX_STATS_RXALIGNERR\t\t0x10\n#define AR40XX_STATS_RXRUNT\t\t0x14\n#define AR40XX_STATS_RXFRAGMENT\t\t0x18\n#define AR40XX_STATS_RX64BYTE\t\t0x1c\n#define AR40XX_STATS_RX128BYTE\t\t0x20\n#define AR40XX_STATS_RX256BYTE\t\t0x24\n#define AR40XX_STATS_RX512BYTE\t\t0x28\n#define AR40XX_STATS_RX1024BYTE\t\t0x2c\n#define AR40XX_STATS_RX1518BYTE\t\t0x30\n#define AR40XX_STATS_RXMAXBYTE\t\t0x34\n#define AR40XX_STATS_RXTOOLONG\t\t0x38\n#define AR40XX_STATS_RXGOODBYTE\t\t0x3c\n#define AR40XX_STATS_RXBADBYTE\t\t0x44\n#define AR40XX_STATS_RXOVERFLOW\t\t0x4c\n#define AR40XX_STATS_FILTERED\t\t0x50\n#define AR40XX_STATS_TXBROAD\t\t0x54\n#define AR40XX_STATS_TXPAUSE\t\t0x58\n#define AR40XX_STATS_TXMULTI\t\t0x5c\n#define AR40XX_STATS_TXUNDERRUN\t\t0x60\n#define AR40XX_STATS_TX64BYTE\t\t0x64\n#define AR40XX_STATS_TX128BYTE\t\t0x68\n#define AR40XX_STATS_TX256BYTE\t\t0x6c\n#define AR40XX_STATS_TX512BYTE\t\t0x70\n#define AR40XX_STATS_TX1024BYTE\t\t0x74\n#define AR40XX_STATS_TX1518BYTE\t\t0x78\n#define AR40XX_STATS_TXMAXBYTE\t\t0x7c\n#define AR40XX_STATS_TXOVERSIZE\t\t0x80\n#define AR40XX_STATS_TXBYTE\t\t0x84\n#define AR40XX_STATS_TXCOLLISION\t0x8c\n#define AR40XX_STATS_TXABORTCOL\t\t0x90\n#define AR40XX_STATS_TXMULTICOL\t\t0x94\n#define AR40XX_STATS_TXSINGLECOL\t0x98\n#define AR40XX_STATS_TXEXCDEFER\t\t0x9c\n#define AR40XX_STATS_TXDEFER\t\t0xa0\n#define AR40XX_STATS_TXLATECOL\t\t0xa4\n\n#define AR40XX_REG_MODULE_EN\t\t\t0x030\n#define   AR40XX_MODULE_EN_MIB\t\t\tBIT(0)\n\n#define AR40XX_REG_MIB_FUNC\t\t\t0x034\n#define   AR40XX_MIB_BUSY\t\tBIT(17)\n#define   AR40XX_MIB_CPU_KEEP\t\t\tBIT(20)\n#define   AR40XX_MIB_FUNC\t\tBITS(24, 3)\n#define   AR40XX_MIB_FUNC_S\t\t24\n#define   AR40XX_MIB_FUNC_NO_OP\t\t0x0\n#define   AR40XX_MIB_FUNC_FLUSH\t\t0x1\n\n#define AR40XX_ESS_SERVICE_TAG\t\t0x48\n#define AR40XX_ESS_SERVICE_TAG_STAG\tBIT(17)\n\n#define AR40XX_REG_PORT_STATUS(_i)\t\t(0x07c + (_i) * 4)\n#define   AR40XX_PORT_SPEED\t\t\tBITS(0, 2)\n#define   AR40XX_PORT_STATUS_SPEED_S\t0\n#define   AR40XX_PORT_TX_EN\t\t\tBIT(2)\n#define   AR40XX_PORT_RX_EN\t\t\tBIT(3)\n#define   AR40XX_PORT_STATUS_TXFLOW\tBIT(4)\n#define   AR40XX_PORT_STATUS_RXFLOW\tBIT(5)\n#define   AR40XX_PORT_DUPLEX\t\t\tBIT(6)\n#define   AR40XX_PORT_TXHALF_FLOW\t\tBIT(7)\n#define   AR40XX_PORT_STATUS_LINK_UP\tBIT(8)\n#define   AR40XX_PORT_AUTO_LINK_EN\t\tBIT(9)\n#define   AR40XX_PORT_STATUS_FLOW_CONTROL  BIT(12)\n\n#define AR40XX_REG_MAX_FRAME_SIZE\t\t0x078\n#define   AR40XX_MAX_FRAME_SIZE_MTU\t\tBITS(0, 14)\n\n#define AR40XX_REG_PORT_HEADER(_i)\t\t(0x09c + (_i) * 4)\n\n#define AR40XX_REG_EEE_CTRL\t\t\t0x100\n#define   AR40XX_EEE_CTRL_DISABLE_PHY(_i)\tBIT(4 + (_i) * 2)\n\n#define AR40XX_REG_PORT_VLAN0(_i)\t\t(0x420 + (_i) * 0x8)\n#define   AR40XX_PORT_VLAN0_DEF_SVID\t\tBITS(0, 12)\n#define   AR40XX_PORT_VLAN0_DEF_SVID_S\t\t0\n#define   AR40XX_PORT_VLAN0_DEF_CVID\t\tBITS(16, 12)\n#define   AR40XX_PORT_VLAN0_DEF_CVID_S\t\t16\n\n#define AR40XX_REG_PORT_VLAN1(_i)\t\t(0x424 + (_i) * 0x8)\n#define   AR40XX_PORT_VLAN1_CORE_PORT\t\tBIT(9)\n#define   AR40XX_PORT_VLAN1_PORT_TLS_MODE\tBIT(7)\n#define   AR40XX_PORT_VLAN1_PORT_VLAN_PROP\tBIT(6)\n#define   AR40XX_PORT_VLAN1_OUT_MODE\t\tBITS(12, 2)\n#define   AR40XX_PORT_VLAN1_OUT_MODE_S\t\t12\n#define   AR40XX_PORT_VLAN1_OUT_MODE_UNMOD\t0\n#define   AR40XX_PORT_VLAN1_OUT_MODE_UNTAG\t1\n#define   AR40XX_PORT_VLAN1_OUT_MODE_TAG\t\t2\n#define   AR40XX_PORT_VLAN1_OUT_MODE_UNTOUCH\t3\n\n#define AR40XX_REG_VTU_FUNC0\t\t\t0x0610\n#define   AR40XX_VTU_FUNC0_EG_MODE\t\tBITS(4, 14)\n#define   AR40XX_VTU_FUNC0_EG_MODE_S(_i)\t(4 + (_i) * 2)\n#define   AR40XX_VTU_FUNC0_EG_MODE_KEEP\t\t0\n#define   AR40XX_VTU_FUNC0_EG_MODE_UNTAG\t1\n#define   AR40XX_VTU_FUNC0_EG_MODE_TAG\t\t2\n#define   AR40XX_VTU_FUNC0_EG_MODE_NOT\t\t3\n#define   AR40XX_VTU_FUNC0_IVL\t\t\tBIT(19)\n#define   AR40XX_VTU_FUNC0_VALID\t\tBIT(20)\n\n#define AR40XX_REG_VTU_FUNC1\t\t\t0x0614\n#define   AR40XX_VTU_FUNC1_OP\t\t\tBITS(0, 3)\n#define   AR40XX_VTU_FUNC1_OP_NOOP\t\t0\n#define   AR40XX_VTU_FUNC1_OP_FLUSH\t\t1\n#define   AR40XX_VTU_FUNC1_OP_LOAD\t\t2\n#define   AR40XX_VTU_FUNC1_OP_PURGE\t\t3\n#define   AR40XX_VTU_FUNC1_OP_REMOVE_PORT\t4\n#define   AR40XX_VTU_FUNC1_OP_GET_NEXT\t\t5\n#define   AR40XX7_VTU_FUNC1_OP_GET_ONE\t\t6\n#define   AR40XX_VTU_FUNC1_FULL\t\t\tBIT(4)\n#define   AR40XX_VTU_FUNC1_PORT\t\t\tBIT(8, 4)\n#define   AR40XX_VTU_FUNC1_PORT_S\t\t8\n#define   AR40XX_VTU_FUNC1_VID\t\t\tBIT(16, 12)\n#define   AR40XX_VTU_FUNC1_VID_S\t\t16\n#define   AR40XX_VTU_FUNC1_BUSY\t\t\tBIT(31)\n\n#define AR40XX_REG_FWD_CTRL0\t\t\t0x620\n#define   AR40XX_FWD_CTRL0_CPU_PORT_EN\t\tBIT(10)\n#define   AR40XX_FWD_CTRL0_MIRROR_PORT\t\tBITS(4, 4)\n#define   AR40XX_FWD_CTRL0_MIRROR_PORT_S\t4\n\n#define AR40XX_REG_FWD_CTRL1\t\t\t0x624\n#define   AR40XX_FWD_CTRL1_UC_FLOOD\t\tBITS(0, 7)\n#define   AR40XX_FWD_CTRL1_UC_FLOOD_S\t\t0\n#define   AR40XX_FWD_CTRL1_MC_FLOOD\t\tBITS(8, 7)\n#define   AR40XX_FWD_CTRL1_MC_FLOOD_S\t\t8\n#define   AR40XX_FWD_CTRL1_BC_FLOOD\t\tBITS(16, 7)\n#define   AR40XX_FWD_CTRL1_BC_FLOOD_S\t\t16\n#define   AR40XX_FWD_CTRL1_IGMP\t\t\tBITS(24, 7)\n#define   AR40XX_FWD_CTRL1_IGMP_S\t\t24\n\n#define AR40XX_REG_PORT_LOOKUP(_i)\t\t(0x660 + (_i) * 0xc)\n#define   AR40XX_PORT_LOOKUP_MEMBER\t\tBITS(0, 7)\n#define   AR40XX_PORT_LOOKUP_IN_MODE\t\tBITS(8, 2)\n#define   AR40XX_PORT_LOOKUP_IN_MODE_S\t\t8\n#define   AR40XX_PORT_LOOKUP_STATE\t\tBITS(16, 3)\n#define   AR40XX_PORT_LOOKUP_STATE_S\t\t16\n#define   AR40XX_PORT_LOOKUP_LEARN\t\tBIT(20)\n#define   AR40XX_PORT_LOOKUP_LOOPBACK\t\tBIT(21)\n#define   AR40XX_PORT_LOOKUP_ING_MIRROR_EN\tBIT(25)\n\n#define AR40XX_REG_ATU_FUNC\t\t\t0x60c\n#define   AR40XX_ATU_FUNC_OP\t\t\tBITS(0, 4)\n#define   AR40XX_ATU_FUNC_OP_NOOP\t\t0x0\n#define   AR40XX_ATU_FUNC_OP_FLUSH\t\t0x1\n#define   AR40XX_ATU_FUNC_OP_LOAD\t\t0x2\n#define   AR40XX_ATU_FUNC_OP_PURGE\t\t0x3\n#define   AR40XX_ATU_FUNC_OP_FLUSH_LOCKED\t0x4\n#define   AR40XX_ATU_FUNC_OP_FLUSH_UNICAST\t0x5\n#define   AR40XX_ATU_FUNC_OP_GET_NEXT\t\t0x6\n#define   AR40XX_ATU_FUNC_OP_SEARCH_MAC\t\t0x7\n#define   AR40XX_ATU_FUNC_OP_CHANGE_TRUNK\t0x8\n#define   AR40XX_ATU_FUNC_BUSY\t\t\tBIT(31)\n\n#define AR40XX_REG_QM_DEBUG_ADDR\t\t0x820\n#define AR40XX_REG_QM_DEBUG_VALUE\t\t0x824\n#define   AR40XX_REG_QM_PORT0_3_QNUM\t\t0x1d\n#define   AR40XX_REG_QM_PORT4_6_QNUM\t\t0x1e\n\n#define AR40XX_REG_PORT_HOL_CTRL1(_i)\t\t(0x974 + (_i) * 0x8)\n#define   AR40XX_PORT_HOL_CTRL1_EG_MIRROR_EN\tBIT(16)\n\n#define AR40XX_REG_PORT_FLOWCTRL_THRESH(_i)\t(0x9b0 + (_i) * 0x4)\n#define   AR40XX_PORT0_FC_THRESH_ON_DFLT\t0x60\n#define   AR40XX_PORT0_FC_THRESH_OFF_DFLT\t0x90\n\n#define AR40XX_PHY_DEBUG_0   0\n#define AR40XX_PHY_MANU_CTRL_EN  BIT(12)\n\n#define AR40XX_PHY_DEBUG_2   2\n\n#define AR40XX_PHY_SPEC_STATUS 0x11\n#define   AR40XX_PHY_SPEC_STATUS_LINK\t\tBIT(10)\n#define   AR40XX_PHY_SPEC_STATUS_DUPLEX\t\tBIT(13)\n#define   AR40XX_PHY_SPEC_STATUS_SPEED\t\tBITS(14, 2)\n\n/* port forwarding state */\nenum {\n\tAR40XX_PORT_STATE_DISABLED = 0,\n\tAR40XX_PORT_STATE_BLOCK = 1,\n\tAR40XX_PORT_STATE_LISTEN = 2,\n\tAR40XX_PORT_STATE_LEARN = 3,\n\tAR40XX_PORT_STATE_FORWARD = 4\n};\n\n/* ingress 802.1q mode */\nenum {\n\tAR40XX_IN_PORT_ONLY = 0,\n\tAR40XX_IN_PORT_FALLBACK = 1,\n\tAR40XX_IN_VLAN_ONLY = 2,\n\tAR40XX_IN_SECURE = 3\n};\n\n/* egress 802.1q mode */\nenum {\n\tAR40XX_OUT_KEEP = 0,\n\tAR40XX_OUT_STRIP_VLAN = 1,\n\tAR40XX_OUT_ADD_VLAN = 2\n};\n\n/* port speed */\nenum {\n\tAR40XX_PORT_SPEED_10M = 0,\n\tAR40XX_PORT_SPEED_100M = 1,\n\tAR40XX_PORT_SPEED_1000M = 2,\n\tAR40XX_PORT_SPEED_ERR = 3,\n};\n\n#define AR40XX_MIB_WORK_DELAY\t2000 /* msecs */\n\n#define AR40XX_QM_WORK_DELAY    100\n\n#define   AR40XX_MIB_FUNC_CAPTURE\t0x3\n\n#define AR40XX_REG_PORT_STATS_START\t0x1000\n#define AR40XX_REG_PORT_STATS_LEN\t\t0x100\n\n#define AR40XX_PORTS_ALL\t0x3f\n\n#define AR40XX_PSGMII_ID\t5\n#define AR40XX_PSGMII_CALB_NUM\t100\n#define AR40XX_MALIBU_PSGMII_MODE_CTRL\t0x6d\n#define AR40XX_MALIBU_PHY_PSGMII_MODE_CTRL_ADJUST_VAL\t0x220c\n#define AR40XX_MALIBU_PHY_MMD7_DAC_CTRL\t0x801a\n#define AR40XX_MALIBU_DAC_CTRL_MASK\t0x380\n#define AR40XX_MALIBU_DAC_CTRL_VALUE\t0x280\n#define AR40XX_MALIBU_PHY_RLP_CTRL       0x805a\n#define AR40XX_PSGMII_TX_DRIVER_1_CTRL\t0xb\n#define AR40XX_MALIBU_PHY_PSGMII_REDUCE_SERDES_TX_AMP\t0x8a\n#define AR40XX_MALIBU_PHY_LAST_ADDR\t4\n\nstatic inline struct ar40xx_priv *\nswdev_to_ar40xx(struct switch_dev *swdev)\n{\n\treturn container_of(swdev, struct ar40xx_priv, dev);\n}\n\n#endif\n"
  },
  {
    "path": "target/linux/ipq40xx/files/drivers/net/phy/qca807x.c",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later\n/*\n * Copyright (c) 2020 Sartura Ltd.\n *\n * Author: Robert Marko <robert.marko@sartura.hr>\n *\n * Qualcomm QCA8072 and QCA8075 PHY driver\n */\n\n#include <linux/version.h>\n#include <linux/module.h>\n#include <linux/of.h>\n#include <linux/phy.h>\n#include <linux/bitfield.h>\n#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,8,0)\n#include <linux/ethtool_netlink.h>\n#endif\n#include <linux/gpio.h>\n#include <linux/sfp.h>\n\n#include <dt-bindings/net/qcom-qca807x.h>\n\n#define PHY_ID_QCA8072\t\t0x004dd0b2\n#define PHY_ID_QCA8075\t\t0x004dd0b1\n#define PHY_ID_QCA807X_PSGMII\t0x06820805\n\n/* Downshift */\n#define QCA807X_SMARTSPEED_EN\t\t\tBIT(5)\n#define QCA807X_SMARTSPEED_RETRY_LIMIT_MASK\tGENMASK(4, 2)\n#define QCA807X_SMARTSPEED_RETRY_LIMIT_DEFAULT\t5\n#define QCA807X_SMARTSPEED_RETRY_LIMIT_MIN\t2\n#define QCA807X_SMARTSPEED_RETRY_LIMIT_MAX\t9\n\n/* Cable diagnostic test (CDT) */\n#define QCA807X_CDT\t\t\t\t\t\t0x16\n#define QCA807X_CDT_ENABLE\t\t\t\t\tBIT(15)\n#define QCA807X_CDT_ENABLE_INTER_PAIR_SHORT\t\t\tBIT(13)\n#define QCA807X_CDT_STATUS\t\t\t\t\tBIT(11)\n#define QCA807X_CDT_MMD3_STATUS\t\t\t\t\t0x8064\n#define QCA807X_CDT_MDI0_STATUS_MASK\t\t\t\tGENMASK(15, 12)\n#define QCA807X_CDT_MDI1_STATUS_MASK\t\t\t\tGENMASK(11, 8)\n#define QCA807X_CDT_MDI2_STATUS_MASK\t\t\t\tGENMASK(7, 4)\n#define QCA807X_CDT_MDI3_STATUS_MASK\t\t\t\tGENMASK(3, 0)\n#define QCA807X_CDT_RESULTS_INVALID\t\t\t\t0x0\n#define QCA807X_CDT_RESULTS_OK\t\t\t\t\t0x1\n#define QCA807X_CDT_RESULTS_OPEN\t\t\t\t0x2\n#define QCA807X_CDT_RESULTS_SAME_SHORT\t\t\t\t0x3\n#define QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI1_SAME_OK\t0x4\n#define QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI2_SAME_OK\t0x8\n#define QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI3_SAME_OK\t0xc\n#define QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI1_SAME_OPEN\t0x6\n#define QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI2_SAME_OPEN\t0xa\n#define QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI3_SAME_OPEN\t0xe\n#define QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI1_SAME_SHORT\t0x7\n#define QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI2_SAME_SHORT\t0xb\n#define QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI3_SAME_SHORT\t0xf\n#define QCA807X_CDT_RESULTS_BUSY\t\t\t\t0x9\n#define QCA807X_CDT_MMD3_MDI0_LENGTH\t\t\t\t0x8065\n#define QCA807X_CDT_MMD3_MDI1_LENGTH\t\t\t\t0x8066\n#define QCA807X_CDT_MMD3_MDI2_LENGTH\t\t\t\t0x8067\n#define QCA807X_CDT_MMD3_MDI3_LENGTH\t\t\t\t0x8068\n#define QCA807X_CDT_SAME_SHORT_LENGTH_MASK\t\t\tGENMASK(15, 8)\n#define QCA807X_CDT_CROSS_SHORT_LENGTH_MASK\t\t\tGENMASK(7, 0)\n\n#define QCA807X_CHIP_CONFIGURATION\t\t\t\t0x1f\n#define QCA807X_BT_BX_REG_SEL\t\t\t\t\tBIT(15)\n#define QCA807X_CHIP_CONFIGURATION_MODE_CFG_MASK\t\tGENMASK(3, 0)\n#define QCA807X_CHIP_CONFIGURATION_MODE_QSGMII_SGMII\t\t4\n#define QCA807X_CHIP_CONFIGURATION_MODE_PSGMII_FIBER\t\t3\n#define QCA807X_CHIP_CONFIGURATION_MODE_PSGMII_ALL_COPPER\t0\n\n#define QCA807X_MEDIA_SELECT_STATUS\t\t\t\t0x1a\n#define QCA807X_MEDIA_DETECTED_COPPER\t\t\t\tBIT(5)\n#define QCA807X_MEDIA_DETECTED_1000_BASE_X\t\t\tBIT(4)\n#define QCA807X_MEDIA_DETECTED_100_BASE_FX\t\t\tBIT(3)\n\n#define QCA807X_MMD7_FIBER_MODE_AUTO_DETECTION\t\t\t0x807e\n#define QCA807X_MMD7_FIBER_MODE_AUTO_DETECTION_EN\t\tBIT(0)\n\n#define QCA807X_MMD7_1000BASE_T_POWER_SAVE_PER_CABLE_LENGTH\t0x801a\n#define QCA807X_CONTROL_DAC_MASK\t\t\t\tGENMASK(2, 0)\n\n#define QCA807X_MMD7_LED_100N_1\t\t\t\t0x8074\n#define QCA807X_MMD7_LED_100N_2\t\t\t\t0x8075\n#define QCA807X_MMD7_LED_1000N_1\t\t\t0x8076\n#define QCA807X_MMD7_LED_1000N_2\t\t\t0x8077\n#define QCA807X_LED_TXACT_BLK_EN_2\t\t\tBIT(10)\n#define QCA807X_LED_RXACT_BLK_EN_2\t\t\tBIT(9)\n#define QCA807X_LED_GT_ON_EN_2\t\t\t\tBIT(6)\n#define QCA807X_LED_HT_ON_EN_2\t\t\t\tBIT(5)\n#define QCA807X_LED_BT_ON_EN_2\t\t\t\tBIT(4)\n#define QCA807X_GPIO_FORCE_EN\t\t\t\tBIT(15)\n#define QCA807X_GPIO_FORCE_MODE_MASK\t\t\tGENMASK(14, 13)\n\n#define QCA807X_INTR_ENABLE\t\t\t\t0x12\n#define QCA807X_INTR_STATUS\t\t\t\t0x13\n#define QCA807X_INTR_ENABLE_AUTONEG_ERR\t\t\tBIT(15)\n#define QCA807X_INTR_ENABLE_SPEED_CHANGED\t\tBIT(14)\n#define QCA807X_INTR_ENABLE_DUPLEX_CHANGED\t\tBIT(13)\n#define QCA807X_INTR_ENABLE_LINK_FAIL\t\t\tBIT(11)\n#define QCA807X_INTR_ENABLE_LINK_SUCCESS\t\tBIT(10)\n\n#define QCA807X_FUNCTION_CONTROL\t\t\t0x10\n#define QCA807X_FC_MDI_CROSSOVER_MODE_MASK\t\tGENMASK(6, 5)\n#define QCA807X_FC_MDI_CROSSOVER_AUTO\t\t\t3\n#define QCA807X_FC_MDI_CROSSOVER_MANUAL_MDIX\t\t1\n#define QCA807X_FC_MDI_CROSSOVER_MANUAL_MDI\t\t0\n\n#define QCA807X_PHY_SPECIFIC_STATUS\t\t\t0x11\n#define QCA807X_SS_SPEED_AND_DUPLEX_RESOLVED\t\tBIT(11)\n#define QCA807X_SS_SPEED_MASK\t\t\t\tGENMASK(15, 14)\n#define QCA807X_SS_SPEED_1000\t\t\t\t2\n#define QCA807X_SS_SPEED_100\t\t\t\t1\n#define QCA807X_SS_SPEED_10\t\t\t\t0\n#define QCA807X_SS_DUPLEX\t\t\t\tBIT(13)\n#define QCA807X_SS_MDIX\t\t\t\t\tBIT(6)\n\n/* PSGMII PHY specific */\n#define PSGMII_QSGMII_DRIVE_CONTROL_1\t\t\t0xb\n#define PSGMII_QSGMII_TX_DRIVER_MASK\t\t\tGENMASK(7, 4)\n#define PSGMII_MODE_CTRL\t\t\t\t0x6d\n#define PSGMII_MODE_CTRL_AZ_WORKAROUND_MASK\t\tGENMASK(3, 0)\n#define PSGMII_MMD3_SERDES_CONTROL\t\t\t0x805a\n\nstruct qca807x_gpio_priv {\n\tstruct phy_device *phy;\n};\n\nstatic int qca807x_get_downshift(struct phy_device *phydev, u8 *data)\n{\n\tint val, cnt, enable;\n\n\tval = phy_read(phydev, MII_NWAYTEST);\n\tif (val < 0)\n\t\treturn val;\n\n\tenable = FIELD_GET(QCA807X_SMARTSPEED_EN, val);\n\tcnt = FIELD_GET(QCA807X_SMARTSPEED_RETRY_LIMIT_MASK, val) + 2;\n\n\t*data = enable ? cnt : DOWNSHIFT_DEV_DISABLE;\n\n\treturn 0;\n}\n\nstatic int qca807x_set_downshift(struct phy_device *phydev, u8 cnt)\n{\n\tint ret, val;\n\n\tif (cnt > QCA807X_SMARTSPEED_RETRY_LIMIT_MAX ||\n\t    (cnt < QCA807X_SMARTSPEED_RETRY_LIMIT_MIN && cnt != DOWNSHIFT_DEV_DISABLE))\n\t\treturn -EINVAL;\n\n\tif (!cnt) {\n\t\tret = phy_clear_bits(phydev, MII_NWAYTEST, QCA807X_SMARTSPEED_EN);\n\t} else {\n\t\tval = QCA807X_SMARTSPEED_EN;\n\t\tval |= FIELD_PREP(QCA807X_SMARTSPEED_RETRY_LIMIT_MASK, cnt - 2);\n\n\t\tphy_modify(phydev, MII_NWAYTEST,\n\t\t\t   QCA807X_SMARTSPEED_EN |\n\t\t\t   QCA807X_SMARTSPEED_RETRY_LIMIT_MASK,\n\t\t\t   val);\n\t}\n\n\tret = genphy_soft_reset(phydev);\n\n\treturn ret;\n}\n\nstatic int qca807x_get_tunable(struct phy_device *phydev,\n\t\t\t       struct ethtool_tunable *tuna, void *data)\n{\n\tswitch (tuna->id) {\n\tcase ETHTOOL_PHY_DOWNSHIFT:\n\t\treturn qca807x_get_downshift(phydev, data);\n\tdefault:\n\t\treturn -EOPNOTSUPP;\n\t}\n}\n\nstatic int qca807x_set_tunable(struct phy_device *phydev,\n\t\t\t       struct ethtool_tunable *tuna, const void *data)\n{\n\tswitch (tuna->id) {\n\tcase ETHTOOL_PHY_DOWNSHIFT:\n\t\treturn qca807x_set_downshift(phydev, *(const u8 *)data);\n\tdefault:\n\t\treturn -EOPNOTSUPP;\n\t}\n}\n\n#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,8,0)\nstatic bool qca807x_distance_valid(int result)\n{\n\tswitch (result) {\n\tcase QCA807X_CDT_RESULTS_OPEN:\n\tcase QCA807X_CDT_RESULTS_SAME_SHORT:\n\tcase QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI1_SAME_OK:\n\tcase QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI2_SAME_OK:\n\tcase QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI3_SAME_OK:\n\tcase QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI1_SAME_OPEN:\n\tcase QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI2_SAME_OPEN:\n\tcase QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI3_SAME_OPEN:\n\tcase QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI1_SAME_SHORT:\n\tcase QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI2_SAME_SHORT:\n\tcase QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI3_SAME_SHORT:\n\t\treturn true;\n\t}\n\treturn false;\n}\n\nstatic int qca807x_report_length(struct phy_device *phydev,\n\t\t\t\t int pair, int result)\n{\n\tint length;\n\tint ret;\n\n\tret = phy_read_mmd(phydev, MDIO_MMD_PCS, QCA807X_CDT_MMD3_MDI0_LENGTH + pair);\n\tif (ret < 0)\n\t\treturn ret;\n\n\tswitch (result) {\n\tcase ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT:\n\t\tlength = (FIELD_GET(QCA807X_CDT_SAME_SHORT_LENGTH_MASK, ret) * 800) / 10;\n\t\tbreak;\n\tcase ETHTOOL_A_CABLE_RESULT_CODE_OPEN:\n\tcase ETHTOOL_A_CABLE_RESULT_CODE_CROSS_SHORT:\n\t\tlength = (FIELD_GET(QCA807X_CDT_CROSS_SHORT_LENGTH_MASK, ret) * 800) / 10;\n\t\tbreak;\n\t}\n\n\tethnl_cable_test_fault_length(phydev, pair, length);\n\n\treturn 0;\n}\n\nstatic int qca807x_cable_test_report_trans(int result)\n{\n\tswitch (result) {\n\tcase QCA807X_CDT_RESULTS_OK:\n\t\treturn ETHTOOL_A_CABLE_RESULT_CODE_OK;\n\tcase QCA807X_CDT_RESULTS_OPEN:\n\t\treturn ETHTOOL_A_CABLE_RESULT_CODE_OPEN;\n\tcase QCA807X_CDT_RESULTS_SAME_SHORT:\n\t\treturn ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;\n\tcase QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI1_SAME_OK:\n\tcase QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI2_SAME_OK:\n\tcase QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI3_SAME_OK:\n\tcase QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI1_SAME_OPEN:\n\tcase QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI2_SAME_OPEN:\n\tcase QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI3_SAME_OPEN:\n\tcase QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI1_SAME_SHORT:\n\tcase QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI2_SAME_SHORT:\n\tcase QCA807X_CDT_RESULTS_CROSS_SHORT_WITH_MDI3_SAME_SHORT:\n\t\treturn ETHTOOL_A_CABLE_RESULT_CODE_CROSS_SHORT;\n\tdefault:\n\t\treturn ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;\n\t}\n}\n\nstatic int qca807x_cable_test_report(struct phy_device *phydev)\n{\n\tint pair0, pair1, pair2, pair3;\n\tint ret;\n\n\tret = phy_read_mmd(phydev, MDIO_MMD_PCS, QCA807X_CDT_MMD3_STATUS);\n\tif (ret < 0)\n\t\treturn ret;\n\n\tpair0 = FIELD_GET(QCA807X_CDT_MDI0_STATUS_MASK, ret);\n\tpair1 = FIELD_GET(QCA807X_CDT_MDI1_STATUS_MASK, ret);\n\tpair2 = FIELD_GET(QCA807X_CDT_MDI2_STATUS_MASK, ret);\n\tpair3 = FIELD_GET(QCA807X_CDT_MDI3_STATUS_MASK, ret);\n\n\tethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_A,\n\t\t\t\tqca807x_cable_test_report_trans(pair0));\n\tethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_B,\n\t\t\t\tqca807x_cable_test_report_trans(pair1));\n\tethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_C,\n\t\t\t\tqca807x_cable_test_report_trans(pair2));\n\tethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_D,\n\t\t\t\tqca807x_cable_test_report_trans(pair3));\n\n\tif (qca807x_distance_valid(pair0))\n\t\tqca807x_report_length(phydev, 0, qca807x_cable_test_report_trans(pair0));\n\tif (qca807x_distance_valid(pair1))\n\t\tqca807x_report_length(phydev, 1, qca807x_cable_test_report_trans(pair1));\n\tif (qca807x_distance_valid(pair2))\n\t\tqca807x_report_length(phydev, 2, qca807x_cable_test_report_trans(pair2));\n\tif (qca807x_distance_valid(pair3))\n\t\tqca807x_report_length(phydev, 3, qca807x_cable_test_report_trans(pair3));\n\n\treturn 0;\n}\n\nstatic int qca807x_cable_test_get_status(struct phy_device *phydev,\n\t\t\t\t\t bool *finished)\n{\n\tint val;\n\n\t*finished = false;\n\n\tval = phy_read(phydev, QCA807X_CDT);\n\tif (!((val & QCA807X_CDT_ENABLE) && (val & QCA807X_CDT_STATUS))) {\n\t\t*finished = true;\n\n\t\treturn qca807x_cable_test_report(phydev);\n\t}\n\n\treturn 0;\n}\n\nstatic int qca807x_cable_test_start(struct phy_device *phydev)\n{\n\tint val, ret;\n\n\tval = phy_read(phydev, QCA807X_CDT);\n\t/* Enable inter-pair short check as well */\n\tval &= ~QCA807X_CDT_ENABLE_INTER_PAIR_SHORT;\n\tval |= QCA807X_CDT_ENABLE;\n\tret = phy_write(phydev, QCA807X_CDT, val);\n\n\treturn ret;\n}\n#endif\n\n#ifdef CONFIG_GPIOLIB\nstatic int qca807x_gpio_get_direction(struct gpio_chip *gc, unsigned int offset)\n{\n#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,5,0)\n\treturn GPIO_LINE_DIRECTION_OUT;\n#else\n\treturn GPIOF_DIR_OUT;\n#endif\n}\n\nstatic int qca807x_gpio_get_reg(unsigned int offset)\n{\n\treturn QCA807X_MMD7_LED_100N_2 + (offset % 2) * 2;\n}\n\nstatic int qca807x_gpio_get(struct gpio_chip *gc, unsigned int offset)\n{\n\tstruct qca807x_gpio_priv *priv = gpiochip_get_data(gc);\n\tint val;\n\n\tval = phy_read_mmd(priv->phy, MDIO_MMD_AN, qca807x_gpio_get_reg(offset));\n\n\treturn FIELD_GET(QCA807X_GPIO_FORCE_MODE_MASK, val);\n}\n\nstatic void qca807x_gpio_set(struct gpio_chip *gc, unsigned int offset, int value)\n{\n\tstruct qca807x_gpio_priv *priv = gpiochip_get_data(gc);\n\tint val;\n\n\tval = phy_read_mmd(priv->phy, MDIO_MMD_AN, qca807x_gpio_get_reg(offset));\n\tval &= ~QCA807X_GPIO_FORCE_MODE_MASK;\n\tval |= QCA807X_GPIO_FORCE_EN;\n\tval |= FIELD_PREP(QCA807X_GPIO_FORCE_MODE_MASK, value);\n\n\tphy_write_mmd(priv->phy, MDIO_MMD_AN, qca807x_gpio_get_reg(offset), val);\n}\n\nstatic int qca807x_gpio_dir_out(struct gpio_chip *gc, unsigned int offset, int value)\n{\n\tqca807x_gpio_set(gc, offset, value);\n\n\treturn 0;\n}\n\nstatic int qca807x_gpio(struct phy_device *phydev)\n{\n\tstruct device *dev = &phydev->mdio.dev;\n\tstruct qca807x_gpio_priv *priv;\n\tstruct gpio_chip *gc;\n\n\tpriv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);\n\tif (!priv)\n\t\treturn -ENOMEM;\n\n\tpriv->phy = phydev;\n\n\tgc = devm_kzalloc(dev, sizeof(*gc), GFP_KERNEL);\n\tif (!gc)\n\t\treturn -ENOMEM;\n\n\tgc->label = dev_name(dev);\n\tgc->base = -1;\n\tgc->ngpio = 2;\n\tgc->parent = dev;\n\tgc->owner = THIS_MODULE;\n\tgc->can_sleep = true;\n\tgc->get_direction = qca807x_gpio_get_direction;\n\tgc->direction_output = qca807x_gpio_dir_out;\n\tgc->get = qca807x_gpio_get;\n\tgc->set = qca807x_gpio_set;\n\n\treturn devm_gpiochip_add_data(dev, gc, priv);\n}\n#endif\n\nstatic int qca807x_read_copper_status(struct phy_device *phydev, bool combo_port)\n{\n\tint ss, err, page, old_link = phydev->link;\n\n\t/* Only combo port has dual pages */\n\tif (combo_port) {\n\t\t/* Check whether copper page is set and set if needed */\n\t\tpage = phy_read(phydev, QCA807X_CHIP_CONFIGURATION);\n\t\tif (!(page & QCA807X_BT_BX_REG_SEL)) {\n\t\t\tpage |= QCA807X_BT_BX_REG_SEL;\n\t\t\tphy_write(phydev, QCA807X_CHIP_CONFIGURATION, page);\n\t\t}\n\t}\n\n\t/* Update the link, but return if there was an error */\n\terr = genphy_update_link(phydev);\n\tif (err)\n\t\treturn err;\n\n\t/* why bother the PHY if nothing can have changed */\n\tif (phydev->autoneg == AUTONEG_ENABLE && old_link && phydev->link)\n\t\treturn 0;\n\n\tphydev->speed = SPEED_UNKNOWN;\n\tphydev->duplex = DUPLEX_UNKNOWN;\n\tphydev->pause = 0;\n\tphydev->asym_pause = 0;\n\n\terr = genphy_read_lpa(phydev);\n\tif (err < 0)\n\t\treturn err;\n\n\t/* Read the QCA807x PHY-Specific Status register copper page,\n\t * which indicates the speed and duplex that the PHY is actually\n\t * using, irrespective of whether we are in autoneg mode or not.\n\t */\n\tss = phy_read(phydev, QCA807X_PHY_SPECIFIC_STATUS);\n\tif (ss < 0)\n\t\treturn ss;\n\n\tif (ss & QCA807X_SS_SPEED_AND_DUPLEX_RESOLVED) {\n\t\tint sfc;\n\n\t\tsfc = phy_read(phydev, QCA807X_FUNCTION_CONTROL);\n\t\tif (sfc < 0)\n\t\t\treturn sfc;\n\n\t\tswitch (FIELD_GET(QCA807X_SS_SPEED_MASK, ss)) {\n\t\tcase QCA807X_SS_SPEED_10:\n\t\t\tphydev->speed = SPEED_10;\n\t\t\tbreak;\n\t\tcase QCA807X_SS_SPEED_100:\n\t\t\tphydev->speed = SPEED_100;\n\t\t\tbreak;\n\t\tcase QCA807X_SS_SPEED_1000:\n\t\t\tphydev->speed = SPEED_1000;\n\t\t\tbreak;\n\t\t}\n\t\tif (ss & QCA807X_SS_DUPLEX)\n\t\t\tphydev->duplex = DUPLEX_FULL;\n\t\telse\n\t\t\tphydev->duplex = DUPLEX_HALF;\n\n\t\tif (ss & QCA807X_SS_MDIX)\n\t\t\tphydev->mdix = ETH_TP_MDI_X;\n\t\telse\n\t\t\tphydev->mdix = ETH_TP_MDI;\n\n\t\tswitch (FIELD_GET(QCA807X_FC_MDI_CROSSOVER_MODE_MASK, sfc)) {\n\t\tcase QCA807X_FC_MDI_CROSSOVER_MANUAL_MDI:\n\t\t\tphydev->mdix_ctrl = ETH_TP_MDI;\n\t\t\tbreak;\n\t\tcase QCA807X_FC_MDI_CROSSOVER_MANUAL_MDIX:\n\t\t\tphydev->mdix_ctrl = ETH_TP_MDI_X;\n\t\t\tbreak;\n\t\tcase QCA807X_FC_MDI_CROSSOVER_AUTO:\n\t\t\tphydev->mdix_ctrl = ETH_TP_MDI_AUTO;\n\t\t\tbreak;\n\t\t}\n\t}\n\n\tif (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete)\n\t\tphy_resolve_aneg_pause(phydev);\n\n\treturn 0;\n}\n\nstatic int qca807x_read_fiber_status(struct phy_device *phydev, bool combo_port)\n{\n\tint ss, err, page, lpa, old_link = phydev->link;\n\n\t/* Check whether fiber page is set and set if needed */\n\tpage = phy_read(phydev, QCA807X_CHIP_CONFIGURATION);\n\tif (page & QCA807X_BT_BX_REG_SEL) {\n\t\tpage &= ~QCA807X_BT_BX_REG_SEL;\n\t\tphy_write(phydev, QCA807X_CHIP_CONFIGURATION, page);\n\t}\n\n\t/* Update the link, but return if there was an error */\n\terr = genphy_update_link(phydev);\n\tif (err)\n\t\treturn err;\n\n\t/* why bother the PHY if nothing can have changed */\n\tif (phydev->autoneg == AUTONEG_ENABLE && old_link && phydev->link)\n\t\treturn 0;\n\n\tphydev->speed = SPEED_UNKNOWN;\n\tphydev->duplex = DUPLEX_UNKNOWN;\n\tphydev->pause = 0;\n\tphydev->asym_pause = 0;\n\n\tif (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete) {\n\t\tlpa = phy_read(phydev, MII_LPA);\n\t\tif (lpa < 0)\n\t\t\treturn lpa;\n\n\t\tlinkmode_mod_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,\n\t\t\t\t phydev->lp_advertising, lpa & LPA_LPACK);\n\t\tlinkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT,\n\t\t\t\t phydev->lp_advertising, lpa & LPA_1000XFULL);\n\t\tlinkmode_mod_bit(ETHTOOL_LINK_MODE_Pause_BIT,\n\t\t\t\t phydev->lp_advertising, lpa & LPA_1000XPAUSE);\n\t\tlinkmode_mod_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT,\n\t\t\t\t phydev->lp_advertising,\n\t\t\t\t lpa & LPA_1000XPAUSE_ASYM);\n\n\t\tphy_resolve_aneg_linkmode(phydev);\n\t}\n\n\t/* Read the QCA807x PHY-Specific Status register fiber page,\n\t * which indicates the speed and duplex that the PHY is actually\n\t * using, irrespective of whether we are in autoneg mode or not.\n\t */\n\tss = phy_read(phydev, QCA807X_PHY_SPECIFIC_STATUS);\n\tif (ss < 0)\n\t\treturn ss;\n\n\tif (ss & QCA807X_SS_SPEED_AND_DUPLEX_RESOLVED) {\n\t\tswitch (FIELD_GET(QCA807X_SS_SPEED_MASK, ss)) {\n\t\tcase QCA807X_SS_SPEED_100:\n\t\t\tphydev->speed = SPEED_100;\n\t\t\tbreak;\n\t\tcase QCA807X_SS_SPEED_1000:\n\t\t\tphydev->speed = SPEED_1000;\n\t\t\tbreak;\n\t\t}\n\n\t\tif (ss & QCA807X_SS_DUPLEX)\n\t\t\tphydev->duplex = DUPLEX_FULL;\n\t\telse\n\t\t\tphydev->duplex = DUPLEX_HALF;\n\t}\n\n\treturn 0;\n}\n\nstatic int qca807x_read_status(struct phy_device *phydev)\n{\n\tint val;\n\n\t/* Check for Combo port */\n\tif (phy_read(phydev, QCA807X_CHIP_CONFIGURATION)) {\n\t\t/* Check for fiber mode first */\n\t\tif (linkmode_test_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, phydev->supported)) {\n\t\t\t/* Check for actual detected media */\n\t\t\tval = phy_read(phydev, QCA807X_MEDIA_SELECT_STATUS);\n\t\t\tif (val & QCA807X_MEDIA_DETECTED_COPPER) {\n\t\t\t\tqca807x_read_copper_status(phydev, true);\n\t\t\t} else if ((val & QCA807X_MEDIA_DETECTED_1000_BASE_X) ||\n\t\t\t\t   (val & QCA807X_MEDIA_DETECTED_100_BASE_FX)) {\n\t\t\t\tqca807x_read_fiber_status(phydev, true);\n\t\t\t}\n\t\t} else {\n\t\t\tqca807x_read_copper_status(phydev, true);\n\t\t}\n\t} else {\n\t\tqca807x_read_copper_status(phydev, false);\n\t}\n\n\treturn 0;\n}\n\nstatic int qca807x_config_intr(struct phy_device *phydev)\n{\n\tint ret, val;\n\n\tval = phy_read(phydev, QCA807X_INTR_ENABLE);\n\n\tif (phydev->interrupts == PHY_INTERRUPT_ENABLED) {\n\t\t/* Check for combo port as it has fewer interrupts */\n\t\tif (phy_read(phydev, QCA807X_CHIP_CONFIGURATION)) {\n\t\t\tval |= QCA807X_INTR_ENABLE_SPEED_CHANGED;\n\t\t\tval |= QCA807X_INTR_ENABLE_LINK_FAIL;\n\t\t\tval |= QCA807X_INTR_ENABLE_LINK_SUCCESS;\n\t\t} else {\n\t\t\tval |= QCA807X_INTR_ENABLE_AUTONEG_ERR;\n\t\t\tval |= QCA807X_INTR_ENABLE_SPEED_CHANGED;\n\t\t\tval |= QCA807X_INTR_ENABLE_DUPLEX_CHANGED;\n\t\t\tval |= QCA807X_INTR_ENABLE_LINK_FAIL;\n\t\t\tval |= QCA807X_INTR_ENABLE_LINK_SUCCESS;\n\t\t}\n\t\tret = phy_write(phydev, QCA807X_INTR_ENABLE, val);\n\t} else {\n\t\tret = phy_write(phydev, QCA807X_INTR_ENABLE, 0);\n\t}\n\n\treturn ret;\n}\n\n#if LINUX_VERSION_CODE < KERNEL_VERSION(5,12,0)\nstatic int qca807x_ack_intr(struct phy_device *phydev)\n{\n\tint ret;\n\n\tret = phy_read(phydev, QCA807X_INTR_STATUS);\n\n\treturn (ret < 0) ? ret : 0;\n}\n#else\nstatic irqreturn_t qca807x_handle_interrupt(struct phy_device *phydev)\n{\n\tint irq_status, int_enabled;\n\n\tirq_status = phy_read(phydev, QCA807X_INTR_STATUS);\n\tif (irq_status < 0) {\n\t\tphy_error(phydev);\n\t\treturn IRQ_NONE;\n\t}\n\n\t/* Read the current enabled interrupts */\n\tint_enabled = phy_read(phydev, QCA807X_INTR_ENABLE);\n\tif (int_enabled < 0) {\n\t\tphy_error(phydev);\n\t\treturn IRQ_NONE;\n\t}\n\n\t/* See if this was one of our enabled interrupts */\n\tif (!(irq_status & int_enabled))\n\t\treturn IRQ_NONE;\n\n\tphy_trigger_machine(phydev);\n\n\treturn IRQ_HANDLED;\n}\n#endif\n\nstatic int qca807x_led_config(struct phy_device *phydev)\n{\n\tstruct device_node *node = phydev->mdio.dev.of_node;\n\tbool led_config = false;\n\tint val;\n\n\tval = phy_read_mmd(phydev, MDIO_MMD_AN, QCA807X_MMD7_LED_1000N_1);\n\tif (val < 0)\n\t\treturn val;\n\n\tif (of_property_read_bool(node, \"qcom,single-led-1000\")) {\n\t\tval |= QCA807X_LED_TXACT_BLK_EN_2;\n\t\tval |= QCA807X_LED_RXACT_BLK_EN_2;\n\t\tval |= QCA807X_LED_GT_ON_EN_2;\n\n\t\tled_config = true;\n\t}\n\n\tif (of_property_read_bool(node, \"qcom,single-led-100\")) {\n\t\tval |= QCA807X_LED_HT_ON_EN_2;\n\n\t\tled_config = true;\n\t}\n\n\tif (of_property_read_bool(node, \"qcom,single-led-10\")) {\n\t\tval |= QCA807X_LED_BT_ON_EN_2;\n\n\t\tled_config = true;\n\t}\n\n\tif (led_config)\n\t\treturn phy_write_mmd(phydev, MDIO_MMD_AN, QCA807X_MMD7_LED_1000N_1, val);\n\telse\n\t\treturn 0;\n}\n\nstatic const struct sfp_upstream_ops qca807x_sfp_ops = {\n\t.attach = phy_sfp_attach,\n\t.detach = phy_sfp_detach,\n};\n\nstatic int qca807x_config(struct phy_device *phydev)\n{\n\tstruct device_node *node = phydev->mdio.dev.of_node;\n\tint control_dac, ret = 0;\n\tu32 of_control_dac;\n\n\t/* Check for Combo port */\n\tif (phy_read(phydev, QCA807X_CHIP_CONFIGURATION)) {\n\t\tint fiber_mode_autodect;\n\t\tint psgmii_serdes;\n\t\tint chip_config;\n\n\t\tif (of_property_read_bool(node, \"qcom,fiber-enable\")) {\n\t\t\t/* Enable fiber mode autodection (1000Base-X or 100Base-FX) */\n\t\t\tfiber_mode_autodect = phy_read_mmd(phydev, MDIO_MMD_AN,\n\t\t\t\t\t\t\t   QCA807X_MMD7_FIBER_MODE_AUTO_DETECTION);\n\t\t\tfiber_mode_autodect |= QCA807X_MMD7_FIBER_MODE_AUTO_DETECTION_EN;\n\t\t\tphy_write_mmd(phydev, MDIO_MMD_AN, QCA807X_MMD7_FIBER_MODE_AUTO_DETECTION,\n\t\t\t\t      fiber_mode_autodect);\n\n\t\t\t/* Enable 4 copper + combo port mode */\n\t\t\tchip_config = phy_read(phydev, QCA807X_CHIP_CONFIGURATION);\n\t\t\tchip_config &= ~QCA807X_CHIP_CONFIGURATION_MODE_CFG_MASK;\n\t\t\tchip_config |= FIELD_PREP(QCA807X_CHIP_CONFIGURATION_MODE_CFG_MASK,\n\t\t\t\t\t\t  QCA807X_CHIP_CONFIGURATION_MODE_PSGMII_FIBER);\n\t\t\tphy_write(phydev, QCA807X_CHIP_CONFIGURATION, chip_config);\n\n\t\t\tlinkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, phydev->supported);\n\t\t\tlinkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, phydev->advertising);\n\t\t}\n\n\t\t/* Prevent PSGMII going into hibernation via PSGMII self test */\n\t\tpsgmii_serdes = phy_read_mmd(phydev, MDIO_MMD_PCS, PSGMII_MMD3_SERDES_CONTROL);\n\t\tpsgmii_serdes &= ~BIT(1);\n\t\tret = phy_write_mmd(phydev, MDIO_MMD_PCS,\n\t\t\t\t    PSGMII_MMD3_SERDES_CONTROL,\n\t\t\t\t    psgmii_serdes);\n\t}\n\n\tif (!of_property_read_u32(node, \"qcom,control-dac\", &of_control_dac)) {\n\t\tcontrol_dac = phy_read_mmd(phydev, MDIO_MMD_AN,\n\t\t\t\t\t   QCA807X_MMD7_1000BASE_T_POWER_SAVE_PER_CABLE_LENGTH);\n\t\tcontrol_dac &= ~QCA807X_CONTROL_DAC_MASK;\n\t\tcontrol_dac |= FIELD_PREP(QCA807X_CONTROL_DAC_MASK, of_control_dac);\n\t\tret = phy_write_mmd(phydev, MDIO_MMD_AN,\n\t\t\t\t    QCA807X_MMD7_1000BASE_T_POWER_SAVE_PER_CABLE_LENGTH,\n\t\t\t\t    control_dac);\n\t}\n\n\t/* Optionally configure LED-s */\n\tif (IS_ENABLED(CONFIG_GPIOLIB)) {\n\t\t/* Check whether PHY-s pins are used as GPIO-s */\n\t\tif (!of_property_read_bool(node, \"gpio-controller\"))\n\t\t\tret = qca807x_led_config(phydev);\n\t} else {\n\t\tret = qca807x_led_config(phydev);\n\t}\n\n\treturn ret;\n}\n\nstatic int qca807x_probe(struct phy_device *phydev)\n{\n\tstruct device_node *node = phydev->mdio.dev.of_node;\n\tint ret = 0;\n\n\tif (IS_ENABLED(CONFIG_GPIOLIB)) {\n\t\t/* Do not register a GPIO controller unless flagged for it */\n\t\tif (of_property_read_bool(node, \"gpio-controller\"))\n\t\t\tret = qca807x_gpio(phydev);\n\t}\n\n\t/* Attach SFP bus on combo port*/\n\tif (of_property_read_bool(node, \"qcom,fiber-enable\")) {\n\t\tif (phy_read(phydev, QCA807X_CHIP_CONFIGURATION))\n\t\t\tret = phy_sfp_probe(phydev, &qca807x_sfp_ops);\n\t}\n\n\treturn ret;\n}\n\nstatic int qca807x_psgmii_config(struct phy_device *phydev)\n{\n\tstruct device_node *node = phydev->mdio.dev.of_node;\n\tint psgmii_az, tx_amp, ret = 0;\n\tu32 tx_driver_strength;\n\n\t/* Workaround to enable AZ transmitting ability */\n\tif (of_property_read_bool(node, \"qcom,psgmii-az\")) {\n\t\tpsgmii_az = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, PSGMII_MODE_CTRL);\n\t\tpsgmii_az &= ~PSGMII_MODE_CTRL_AZ_WORKAROUND_MASK;\n\t\tpsgmii_az |= FIELD_PREP(PSGMII_MODE_CTRL_AZ_WORKAROUND_MASK, 0xc);\n\t\tret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, PSGMII_MODE_CTRL, psgmii_az);\n\t\tpsgmii_az = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, PSGMII_MODE_CTRL);\n\t}\n\n\t/* PSGMII/QSGMII TX amp set to DT defined value instead of default 600mV */\n\tif (!of_property_read_u32(node, \"qcom,tx-driver-strength\", &tx_driver_strength)) {\n\t\ttx_amp = phy_read(phydev, PSGMII_QSGMII_DRIVE_CONTROL_1);\n\t\ttx_amp &= ~PSGMII_QSGMII_TX_DRIVER_MASK;\n\t\ttx_amp |= FIELD_PREP(PSGMII_QSGMII_TX_DRIVER_MASK, tx_driver_strength);\n\t\tret = phy_write(phydev, PSGMII_QSGMII_DRIVE_CONTROL_1, tx_amp);\n\t}\n\n\treturn ret;\n}\n\nstatic struct phy_driver qca807x_drivers[] = {\n\t{\n\t\tPHY_ID_MATCH_EXACT(PHY_ID_QCA8072),\n\t\t.name           = \"Qualcomm QCA8072\",\n#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,8,0)\n\t\t.flags\t\t= PHY_POLL_CABLE_TEST,\n#endif\n\t\t/* PHY_GBIT_FEATURES */\n\t\t.probe\t\t= qca807x_probe,\n\t\t.config_init\t= qca807x_config,\n\t\t.read_status\t= qca807x_read_status,\n\t\t.config_intr\t= qca807x_config_intr,\n#if LINUX_VERSION_CODE < KERNEL_VERSION(5,12,0)\n\t\t.ack_interrupt\t= qca807x_ack_intr,\n#else\n\t\t.handle_interrupt = qca807x_handle_interrupt,\n#endif\n\t\t.soft_reset\t= genphy_soft_reset,\n\t\t.get_tunable\t= qca807x_get_tunable,\n\t\t.set_tunable\t= qca807x_set_tunable,\n#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,8,0)\n\t\t.cable_test_start\t= qca807x_cable_test_start,\n\t\t.cable_test_get_status\t= qca807x_cable_test_get_status,\n#endif\n\t},\n\t{\n\t\tPHY_ID_MATCH_EXACT(PHY_ID_QCA8075),\n\t\t.name           = \"Qualcomm QCA8075\",\n#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,8,0)\n\t\t.flags\t\t= PHY_POLL_CABLE_TEST,\n#endif\n\t\t/* PHY_GBIT_FEATURES */\n\t\t.probe\t\t= qca807x_probe,\n\t\t.config_init\t= qca807x_config,\n\t\t.read_status\t= qca807x_read_status,\n\t\t.config_intr\t= qca807x_config_intr,\n#if LINUX_VERSION_CODE < KERNEL_VERSION(5,12,0)\n\t\t.ack_interrupt\t= qca807x_ack_intr,\n#else\n\t\t.handle_interrupt = qca807x_handle_interrupt,\n#endif\n\t\t.soft_reset\t= genphy_soft_reset,\n\t\t.get_tunable\t= qca807x_get_tunable,\n\t\t.set_tunable\t= qca807x_set_tunable,\n#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,8,0)\n\t\t.cable_test_start\t= qca807x_cable_test_start,\n\t\t.cable_test_get_status\t= qca807x_cable_test_get_status,\n#endif\n\t},\n\t{\n\t\tPHY_ID_MATCH_EXACT(PHY_ID_QCA807X_PSGMII),\n\t\t.name           = \"Qualcomm QCA807x PSGMII\",\n\t\t.probe\t\t= qca807x_psgmii_config,\n\t},\n};\nmodule_phy_driver(qca807x_drivers);\n\nstatic struct mdio_device_id __maybe_unused qca807x_tbl[] = {\n\t{ PHY_ID_MATCH_EXACT(PHY_ID_QCA8072) },\n\t{ PHY_ID_MATCH_EXACT(PHY_ID_QCA8075) },\n\t{ PHY_ID_MATCH_MODEL(PHY_ID_QCA807X_PSGMII) },\n\t{ }\n};\n\nMODULE_AUTHOR(\"Robert Marko\");\nMODULE_DESCRIPTION(\"Qualcomm QCA807x PHY driver\");\nMODULE_DEVICE_TABLE(mdio, qca807x_tbl);\nMODULE_LICENSE(\"GPL\");\n"
  },
  {
    "path": "target/linux/ipq40xx/generic/target.mk",
    "content": "BOARDNAME:=Generic\nFEATURES+=emmc\n"
  },
  {
    "path": "target/linux/ipq40xx/image/Makefile",
    "content": "include $(TOPDIR)/rules.mk\ninclude $(INCLUDE_DIR)/image.mk\n\ndefine Device/Default\n\tPROFILES := Default\n\tKERNEL_DEPENDS = $$(wildcard $(DTS_DIR)/$$(DEVICE_DTS).dts)\n\tKERNEL_LOADADDR := 0x80208000\n\tDEVICE_DTS = $$(SOC)-$(lastword $(subst _, ,$(1)))\n\tDEVICE_DTS_CONFIG := config@1\n\tIMAGES := sysupgrade.bin\n\tIMAGE/sysupgrade.bin = sysupgrade-tar | append-metadata\n\tIMAGE/sysupgrade.bin/squashfs :=\nendef\n\ninclude $(SUBTARGET).mk\n\n$(eval $(call BuildImage))\n"
  },
  {
    "path": "target/linux/ipq40xx/image/chromium.mk",
    "content": "define Build/cros-gpt\n\tcp $@ $@.tmp 2>/dev/null || true\n\tptgen -o $@.tmp -g \\\n\t\t-T cros_kernel\t-N kernel -p $(CONFIG_TARGET_KERNEL_PARTSIZE)m \\\n\t\t\t\t-N rootfs -p $(CONFIG_TARGET_ROOTFS_PARTSIZE)m\n\tcat $@.tmp >> $@\n\trm $@.tmp\nendef\n\ndefine Build/append-kernel-part\n\tdd if=$(IMAGE_KERNEL) bs=$(CONFIG_TARGET_KERNEL_PARTSIZE)M conv=sync >> $@\nendef\n\n# NB: Chrome OS bootloaders replace the '%U' in command lines with the UUID of\n# the kernel partition it chooses to boot from. This gives a flexible way to\n# consistently build and sign kernels that always use the subsequent\n# (PARTNROFF=1) partition as their rootfs.\ndefine Build/cros-vboot\n\t$(STAGING_DIR_HOST)/bin/cros-vbutil \\\n\t\t-k $@ -c \"root=PARTUUID=%U/PARTNROFF=1\" -o $@.new\n\t@mv $@.new $@\nendef\n\ndefine Device/google_wifi\n\tDEVICE_VENDOR := Google\n\tDEVICE_MODEL := WiFi (Gale)\n\tSOC := qcom-ipq4019\n\tKERNEL_SUFFIX := -fit-zImage.itb.vboot\n\tKERNEL = kernel-bin | fit none $$(DTS_DIR)/$$(DEVICE_DTS).dtb | cros-vboot\n\tKERNEL_NAME := zImage\n\tIMAGES += factory.bin\n\tIMAGE/factory.bin := cros-gpt | append-kernel-part | append-rootfs\n\tDEVICE_PACKAGES := partx-utils mkf2fs e2fsprogs \\\n\t\t\t   kmod-fs-ext4 kmod-fs-f2fs kmod-google-firmware\nendef\nTARGET_DEVICES += google_wifi\n"
  },
  {
    "path": "target/linux/ipq40xx/image/generic.mk",
    "content": "\nDEVICE_VARS += NETGEAR_BOARD_ID NETGEAR_HW_ID\nDEVICE_VARS += RAS_BOARD RAS_ROOTFS_SIZE RAS_VERSION\nDEVICE_VARS += WRGG_DEVNAME WRGG_SIGNATURE\n\ndefine Device/FitImage\n\tKERNEL_SUFFIX := -fit-uImage.itb\n\tKERNEL = kernel-bin | gzip | fit gzip $$(DTS_DIR)/$$(DEVICE_DTS).dtb\n\tKERNEL_NAME := Image\nendef\n\ndefine Device/FitImageLzma\n\tKERNEL_SUFFIX := -fit-uImage.itb\n\tKERNEL = kernel-bin | lzma | fit lzma $$(DTS_DIR)/$$(DEVICE_DTS).dtb\n\tKERNEL_NAME := Image\nendef\n\ndefine Device/FitzImage\n\tKERNEL_SUFFIX := -fit-zImage.itb\n\tKERNEL = kernel-bin | fit none $$(DTS_DIR)/$$(DEVICE_DTS).dtb\n\tKERNEL_NAME := zImage\nendef\n\ndefine Device/UbiFit\n\tKERNEL_IN_UBI := 1\n\tIMAGES := nand-factory.ubi nand-sysupgrade.bin\n\tIMAGE/nand-factory.ubi := append-ubi\n\tIMAGE/nand-sysupgrade.bin := sysupgrade-tar | append-metadata\nendef\n\ndefine Device/DniImage\n\t$(call Device/FitzImage)\n\tNETGEAR_BOARD_ID :=\n\tNETGEAR_HW_ID :=\n\tIMAGES += factory.img\n\tIMAGE/factory.img := append-kernel | pad-offset 64k 64 | append-uImage-fakehdr filesystem | append-rootfs | pad-rootfs | netgear-dni\n\tIMAGE/sysupgrade.bin := append-kernel | pad-offset 64k 64 | append-uImage-fakehdr filesystem | \\\n\t\tappend-rootfs | pad-rootfs | check-size | append-metadata\nendef\n\ndefine Build/append-rootfshdr\n\tmkimage -A $(LINUX_KARCH) \\\n\t\t-O linux -T filesystem \\\n\t\t-C lzma -a $(KERNEL_LOADADDR) -e $(if $(KERNEL_ENTRY),$(KERNEL_ENTRY),$(KERNEL_LOADADDR)) \\\n\t\t-n root.squashfs -d $(IMAGE_ROOTFS) $@.new\n\tdd if=$@.new bs=64 count=1 >> $(IMAGE_KERNEL)\nendef\n\ndefine Build/append-rutx-metadata\n\techo \\\n\t\t'{ \\\n\t\t\t\"device_code\": [\".*\"], \\\n\t\t\t\"hwver\": [\".*\"], \\\n\t\t\t\"batch\": [\".*\"], \\\n\t\t\t\"serial\": [\".*\"], \\\n\t\t\t\"supported_devices\":[\"teltonika,rutx\"] \\\n\t\t}' | fwtool -I - $@\nendef\n\ndefine Build/copy-file\n\tcat \"$(1)\" > \"$@\"\nendef\n\ndefine Build/mkmylofw_32m\n\t$(eval device_id=$(word 1,$(1)))\n\t$(eval revision=$(word 2,$(1)))\n\n\tlet \\\n\t\tsize=\"$$(stat -c%s $@)\" \\\n\t\tpad=\"$(subst k,* 1024,$(BLOCKSIZE))\" \\\n\t\tpad=\"(pad - (size % pad)) % pad\" \\\n\t\tnewsize='size + pad'; \\\n\t\t$(STAGING_DIR_HOST)/bin/mkmylofw \\\n\t\t-B WPE72 -i 0x11f6:$(device_id):0x11f6:$(device_id) -r $(revision) \\\n\t\t-s 0x2000000 -p0x180000:$$newsize:al:0x80208000:\"OpenWrt\":$@ \\\n\t\t$@.new\n\t@mv $@.new $@\nendef\n\ndefine Build/wac5xx-netgear-tar\n\tmkdir $@.tmp\n\tmv $@ $@.tmp/wac5xx-ubifs-root.img\n\tmd5sum $@.tmp/wac5xx-ubifs-root.img > $@.tmp/wac5xx-ubifs-root.md5sum\n\techo \"WAC505 WAC510\" > $@.tmp/metadata.txt\n\techo \"WAC505_V9.9.9.9\" > $@.tmp/version\n\ttar -C $@.tmp/ -cf $@ .\n\trm -rf $@.tmp\nendef\n\ndefine Build/qsdk-ipq-factory-nand-askey\n\t$(TOPDIR)/scripts/mkits-qsdk-ipq-image.sh $@.its\\\n\t\taskey_kernel $(IMAGE_KERNEL) \\\n\t\taskey_fs $(IMAGE_ROOTFS) \\\n\t\tubifs $@\n\tPATH=$(LINUX_DIR)/scripts/dtc:$(PATH) mkimage -f $@.its $@.new\n\t@mv $@.new $@\nendef\n\ndefine Build/qsdk-ipq-app-gpt\n\tcp $@ $@.tmp 2>/dev/null || true\n\tptgen -g -o $@.tmp -a 1 -l 1024 \\\n\t\t\t-t 0x2e -N 0:HLOS -r -p 32M \\\n\t\t\t-t 0x83 -N rootfs -r -p 128M \\\n\t\t\t\t-N rootfs_data -p 512M\n\tcat $@.tmp >> $@\n\trm $@.tmp\nendef\n\ndefine Build/SenaoFW\n\t-$(STAGING_DIR_HOST)/bin/mksenaofw \\\n\t\t-n $(BOARD_NAME) -r $(VENDOR_ID) -p $(1) \\\n\t\t-c $(DATECODE) -w $(2) -x $(CW_VER) -t 0 \\\n\t\t-e $@ \\\n\t\t-o $@.new\n\t@cp $@.new $@\nendef\n\ndefine Build/wrgg-image\n\tmkwrggimg -i $@ \\\n\t-o $@.new \\\n\t-d \"$(WRGG_DEVNAME)\" \\\n\t-s \"$(WRGG_SIGNATURE)\" \\\n\t-v \"\" -m \"\" -B \"\"\n\tmv $@.new $@\nendef\n\ndefine Device/8dev_habanero-dvk\n\t$(call Device/FitImageLzma)\n\tDEVICE_VENDOR := 8devices\n\tDEVICE_MODEL := Habanero DVK\n\tIMAGE_SIZE := 30976k\n\tSOC := qcom-ipq4019\n\tIMAGE/sysupgrade.bin := append-kernel | pad-to 64k | append-rootfs | pad-rootfs | check-size | append-metadata\nendef\nTARGET_DEVICES += 8dev_habanero-dvk\n\ndefine Device/8dev_jalapeno-common\n\t$(call Device/FitImage)\n\t$(call Device/UbiFit)\n\tBLOCKSIZE := 128k\n\tPAGESIZE := 2048\n\tSOC := qcom-ipq4018\nendef\n\ndefine Device/8dev_jalapeno\n\t$(call Device/8dev_jalapeno-common)\n\tDEVICE_VENDOR := 8devices\n\tDEVICE_MODEL := Jalapeno\nendef\nTARGET_DEVICES += 8dev_jalapeno\n\ndefine Device/alfa-network_ap120c-ac\n\t$(call Device/FitImage)\n\t$(call Device/UbiFit)\n\tDEVICE_VENDOR := ALFA Network\n\tDEVICE_MODEL := AP120C-AC\n\tSOC := qcom-ipq4018\n\tDEVICE_PACKAGES := kmod-usb-acm kmod-tpm-i2c-atmel\n\tBLOCKSIZE := 128k\n\tPAGESIZE := 2048\n\tIMAGE_SIZE := 65536k\n\tIMAGES := nand-factory.bin nand-sysupgrade.bin\n\tIMAGE/nand-factory.bin := append-ubi | qsdk-ipq-factory-nand\nendef\nTARGET_DEVICES += alfa-network_ap120c-ac\n\ndefine Device/aruba_glenmorangie\n\t$(call Device/FitImageLzma)\n\tDEVICE_VENDOR := Aruba\n\tSOC := qcom-ipq4029\nendef\n\ndefine Device/aruba_ap-303\n\t$(call Device/aruba_glenmorangie)\n\tDEVICE_MODEL := AP-303\nendef\nTARGET_DEVICES += aruba_ap-303\n\ndefine Device/aruba_ap-303h\n\t$(call Device/aruba_glenmorangie)\n\tDEVICE_MODEL := AP-303H\nendef\nTARGET_DEVICES += aruba_ap-303h\n\ndefine Device/aruba_ap-365\n\t$(call Device/aruba_glenmorangie)\n\tDEVICE_MODEL := AP-365\n\tDEVICE_PACKAGES += kmod-hwmon-ad7418\nendef\nTARGET_DEVICES += aruba_ap-365\n\ndefine Device/asus_map-ac2200\n\t$(call Device/FitImageLzma)\n\tDEVICE_VENDOR := ASUS\n\tDEVICE_MODEL := Lyra (MAP-AC2200)\n\tSOC := qcom-ipq4019\n\tDEVICE_PACKAGES := ath10k-firmware-qca9888-ct kmod-ath3k\nendef\nTARGET_DEVICES += asus_map-ac2200\n\n# WARNING: this is an initramfs image that gets you half of the way there\n#          you need to delete the jffs2 ubi volume and sysupgrade to the final image\n# to get a \"trx\" you can flash via web UI for ac42u/ac58u:\n# - change call Device/FitImageLzma to Device/FitImage\n# - add the following below UIMAGE_NAME\n#   UIMAGE_MAGIC := 0x27051956\n#   IMAGES += factory.trx\n#   IMAGE/factory.trx := copy-file $(KDIR)/tmp/$$(KERNEL_INITRAMFS_IMAGE) | uImage none\ndefine Device/asus_rt-ac42u\n\t$(call Device/FitImageLzma)\n\tDEVICE_VENDOR := ASUS\n\tDEVICE_MODEL := RT-AC42U\n\tDEVICE_ALT0_VENDOR := ASUS\n\tDEVICE_ALT0_MODEL := RT-ACRH17\n\tDEVICE_ALT1_VENDOR := ASUS\n\tDEVICE_ALT1_MODEL := RT-AC2200\n\tSOC := qcom-ipq4019\n\tBLOCKSIZE := 128k\n\tPAGESIZE := 2048\n\tIMAGE_SIZE := 20439364\n\tFILESYSTEMS := squashfs\n#\tRT-AC82U is nowhere to be found online\n#\tRather, this device is a/k/a RT-AC42U\n#\tBut we'll go with what the vendor firmware has...\n\tUIMAGE_NAME:=$(shell echo -e '\\03\\01\\01\\01RT-AC82U')\n\tDEVICE_PACKAGES := ath10k-firmware-qca9984-ct kmod-usb-ledtrig-usbport\nendef\nTARGET_DEVICES += asus_rt-ac42u\n\ndefine Device/asus_rt-ac58u\n\t$(call Device/FitImageLzma)\n\tDEVICE_VENDOR := ASUS\n\tDEVICE_MODEL := RT-AC58U\n\tDEVICE_ALT0_VENDOR := ASUS\n\tDEVICE_ALT0_MODEL := RT-ACRH13\n\tSOC := qcom-ipq4018\n\tBLOCKSIZE := 128k\n\tPAGESIZE := 2048\n\tIMAGE_SIZE := 20439364\n\tFILESYSTEMS := squashfs\n#\tSomeone - in their infinite wisdom - decided to put the firmware\n#\tversion in front of the image name \\03\\00\\00\\04 => Version 3.0.0.4\n#\tSince u-boot works with strings we either need another fixup step\n#\tto add a version... or we are very careful not to add '\\0' into that\n#\tstring and call it a day.... Yeah, we do the latter!\n\tUIMAGE_NAME:=$(shell echo -e '\\03\\01\\01\\01RT-AC58U')\n\tDEVICE_PACKAGES := -kmod-ath10k-ct kmod-ath10k-ct-smallbuffers \\\n\t\tkmod-usb-ledtrig-usbport\nendef\nTARGET_DEVICES += asus_rt-ac58u\n\ndefine Device/avm_fritzbox-4040\n\t$(call Device/FitImageLzma)\n\tDEVICE_VENDOR := AVM\n\tDEVICE_MODEL := FRITZ!Box 4040\n\tSOC := qcom-ipq4018\n\tBOARD_NAME := fritz4040\n\tIMAGE_SIZE := 29056k\n\tUBOOT_PATH := $(STAGING_DIR_IMAGE)/uboot-fritz4040.bin\n\tUBOOT_PARTITION_SIZE := 524288\n\tIMAGES += eva.bin\n\tIMAGE/eva.bin := append-uboot | pad-to $$$$(UBOOT_PARTITION_SIZE) | append-kernel | append-rootfs | pad-rootfs\n\tIMAGE/sysupgrade.bin := append-kernel | append-rootfs | pad-rootfs | check-size | append-metadata\n\tDEVICE_PACKAGES := fritz-tffs fritz-caldata\nendef\nTARGET_DEVICES += avm_fritzbox-4040\n\ndefine Device/avm_fritzbox-7530\n\t$(call Device/FitImageLzma)\n\tDEVICE_VENDOR := AVM\n\tDEVICE_MODEL := FRITZ!Box 7530\n\tDEVICE_ALT0_VENDOR := AVM\n\tDEVICE_ALT0_MODEL := FRITZ!Box 7520\n\tSOC := qcom-ipq4019\n\tDEVICE_PACKAGES := fritz-caldata fritz-tffs-nand\nendef\nTARGET_DEVICES += avm_fritzbox-7530\n\ndefine Device/avm_fritzrepeater-1200\n\t$(call Device/FitImageLzma)\n\tDEVICE_VENDOR := AVM\n\tDEVICE_MODEL := FRITZ!Repeater 1200\n\tSOC := qcom-ipq4019\n\tDEVICE_PACKAGES := fritz-caldata fritz-tffs-nand\nendef\nTARGET_DEVICES += avm_fritzrepeater-1200\n\ndefine Device/avm_fritzrepeater-3000\n\t$(call Device/FitImageLzma)\n\tDEVICE_VENDOR := AVM\n\tDEVICE_MODEL := FRITZ!Repeater 3000\n\tSOC := qcom-ipq4019\n\tDEVICE_PACKAGES := ath10k-firmware-qca9984-ct fritz-caldata fritz-tffs-nand\nendef\nTARGET_DEVICES += avm_fritzrepeater-3000\n\ndefine Device/buffalo_wtr-m2133hp\n\t$(call Device/FitImage)\n\t$(call Device/UbiFit)\n\tDEVICE_VENDOR := Buffalo\n\tDEVICE_MODEL := WTR-M2133HP\n\tSOC := qcom-ipq4019\n\tDEVICE_PACKAGES := ath10k-firmware-qca9984-ct\n\tBLOCKSIZE := 128k\n\tPAGESIZE := 2048\nendef\nTARGET_DEVICES += buffalo_wtr-m2133hp\n\ndefine Device/cellc_rtl30vw\n\tKERNEL_SUFFIX := -fit-zImage.itb\n\tKERNEL_INITRAMFS = kernel-bin | gzip | fit gzip $$(DTS_DIR)/$$(DEVICE_DTS).dtb\n\tKERNEL = kernel-bin | fit none $$(DTS_DIR)/$$(DEVICE_DTS).dtb | uImage lzma | pad-to 2048\n\tKERNEL_NAME := zImage\n\tKERNEL_IN_UBI :=\n\tIMAGES := nand-factory.bin nand-sysupgrade.bin\n\tIMAGE/nand-factory.bin := append-rootfshdr | append-ubi | qsdk-ipq-factory-nand-askey\n\tIMAGE/nand-sysupgrade.bin := append-rootfshdr | sysupgrade-tar | append-metadata\n\tDEVICE_VENDOR := Cell C\n\tDEVICE_MODEL := RTL30VW\n\tSOC := qcom-ipq4019\n\tDEVICE_DTS_CONFIG := config@5\n\tKERNEL_INSTALL := 1\n\tKERNEL_SIZE := 4096k\n\tIMAGE_SIZE := 57344k\n\tBLOCKSIZE := 128k\n\tPAGESIZE := 2048\n\tDEVICE_PACKAGES := kmod-usb-net-qmi-wwan kmod-usb-serial-option uqmi\nendef\nTARGET_DEVICES += cellc_rtl30vw\n\ndefine Device/cilab_meshpoint-one\n\t$(call Device/8dev_jalapeno-common)\n\tDEVICE_VENDOR := Crisis Innovation Lab\n\tDEVICE_MODEL := MeshPoint.One\n\tDEVICE_PACKAGES := kmod-i2c-gpio kmod-iio-bmp280-i2c kmod-hwmon-ina2xx kmod-rtc-pcf2127\nendef\nTARGET_DEVICES += cilab_meshpoint-one\n\ndefine Device/compex_wpj419\n\t$(call Device/FitImage)\n\t$(call Device/UbiFit)\n\tDEVICE_VENDOR := Compex\n\tDEVICE_MODEL := WPJ419\n\tSOC := qcom-ipq4019\n\tDEVICE_DTS_CONFIG := config@12\n\tKERNEL_INSTALL := 1\n\tBLOCKSIZE := 128k\n\tPAGESIZE := 2048\n\tFILESYSTEMS := squashfs\nendef\nTARGET_DEVICES += compex_wpj419\n\ndefine Device/compex_wpj428\n\t$(call Device/FitImage)\n\tDEVICE_VENDOR := Compex\n\tDEVICE_MODEL := WPJ428\n\tSOC := qcom-ipq4028\n\tDEVICE_DTS_CONFIG := config@4\n\tBLOCKSIZE := 64k\n\tIMAGE_SIZE := 31232k\n\tKERNEL_SIZE := 4096k\n\tIMAGES += cpximg-6a04.bin\n\tIMAGE/sysupgrade.bin := append-kernel | append-rootfs | pad-rootfs | append-metadata\n\tIMAGE/cpximg-6a04.bin := append-kernel | append-rootfs | pad-rootfs | mkmylofw_32m 0x8A2 3\n\tDEVICE_PACKAGES := kmod-gpio-beeper\n\tDEFAULT := n\nendef\nTARGET_DEVICES += compex_wpj428\n\ndefine Device/devolo_magic-2-wifi-next\n\t$(call Device/FitImage)\n\tDEVICE_VENDOR := devolo\n\tDEVICE_MODEL := Magic 2 WiFi next\n\tSOC := qcom-ipq4018\n\tKERNEL_SIZE := 4096k\n\n\t# If the bootloader sees 0xDEADC0DE and this trailer at the 64k boundary of a TFTP image\n\t# it will bootm it, just like we want for the initramfs.\n\tKERNEL_INITRAMFS := kernel-bin | gzip | fit gzip $$(DTS_DIR)/$$(DEVICE_DTS).dtb | pad-to 64k |\\\n\t\tappend-string -e '\\xDE\\xAD\\xC0\\xDE{\"fl_initramfs\":\"\"}\\x00'\n\n\tIMAGE_SIZE := 26624k\n\tIMAGES := sysupgrade.bin\n\tIMAGE/sysupgrade.bin := append-kernel | append-rootfs | pad-rootfs | append-metadata\n\tDEVICE_PACKAGES := ipq-wifi-devolo_magic-2-wifi-next\n\tDEFAULT := n\nendef\nTARGET_DEVICES += devolo_magic-2-wifi-next\n\ndefine Device/dlink_dap-2610\n\t$(call Device/FitImageLzma)\n\tDEVICE_VENDOR := D-Link\n\tDEVICE_MODEL := DAP-2610\n\tSOC := qcom-ipq4018\n\tDEVICE_DTS_CONFIG := config@ap.dk01.1-c1\n\tBLOCKSIZE := 64k\n\tWRGG_DEVNAME := /dev/mtdblock/8\n\tWRGG_SIGNATURE := wapac30_dkbs_dap2610\n\tIMAGE_SIZE := 14080k\n\tIMAGES += factory.bin\n\t# Bootloader expects a special 160 byte header which is added by\n\t# wrgg-image.\n\t# Factory image size must be larger than 6MB, and size in wrgg header must\n\t# match actual factory image size to be flashable from D-Link http server.\n\t# Bootloader verifies checksum of wrgg image before booting, thus jffs2\n\t# cannot be part of the wrgg image. This is solved in the factory image by\n\t# having the rootfs at the end of the image (without pad-rootfs). And in\n\t# the sysupgrade image only the kernel is included in the wrgg checksum,\n\t# but this is not flashable from the D-link http server.\n\t# append-rootfs must start on an erase block boundary.\n\tIMAGE/factory.bin    := append-kernel | pad-offset 6144k 160 | append-rootfs | wrgg-image | check-size\n\tIMAGE/sysupgrade.bin := append-kernel | wrgg-image | pad-to $$$$(BLOCKSIZE) | append-rootfs | pad-rootfs | check-size | append-metadata\nendef\nTARGET_DEVICES += dlink_dap-2610\n\ndefine Device/edgecore_ecw5211\n\t$(call Device/FitImage)\n\t$(call Device/UbiFit)\n\tDEVICE_VENDOR := Edgecore\n\tDEVICE_MODEL := ECW5211\n\tSOC := qcom-ipq4018\n\tBLOCKSIZE := 128k\n\tPAGESIZE := 2048\n\tDEVICE_DTS_CONFIG := config@ap.dk01.1-c2\n\tDEVICE_PACKAGES := kmod-tpm-i2c-atmel kmod-usb-acm\nendef\nTARGET_DEVICES += edgecore_ecw5211\n\ndefine Device/edgecore_oap100\n\t$(call Device/FitImage)\n\t$(call Device/UbiFit)\n\tDEVICE_VENDOR := Edgecore\n\tDEVICE_MODEL := OAP100\n\tSOC := qcom-ipq4019\n\tBLOCKSIZE := 128k\n\tPAGESIZE := 2048\n\tIMAGES := nand-sysupgrade.bin\n\tDEVICE_DTS_CONFIG := config@ap.dk07.1-c1\n\tDEVICE_PACKAGES := ipq-wifi-edgecore_oap100 kmod-usb-acm kmod-usb-net kmod-usb-net-cdc-qmi uqmi\nendef\nTARGET_DEVICES += edgecore_oap100\n\ndefine Device/engenius_eap1300\n\t$(call Device/FitImage)\n\tDEVICE_VENDOR := EnGenius\n\tDEVICE_MODEL := EAP1300\n\tDEVICE_DTS_CONFIG := config@4\n\tBOARD_NAME := eap1300\n\tSOC := qcom-ipq4018\n\tKERNEL_SIZE := 5120k\n\tIMAGE_SIZE := 25344k\n\tIMAGE/sysupgrade.bin := append-kernel | append-rootfs | pad-rootfs | append-metadata\nendef\nTARGET_DEVICES += engenius_eap1300\n\ndefine Device/engenius_eap2200\n\t$(call Device/FitImage)\n\t$(call Device/UbiFit)\n\tDEVICE_VENDOR := EnGenius\n\tDEVICE_MODEL := EAP2200\n\tSOC := qcom-ipq4019\n\tBLOCKSIZE := 128k\n\tPAGESIZE := 2048\n\tDEVICE_PACKAGES := ath10k-firmware-qca9888-ct -kmod-ath10k-ct kmod-ath10k-ct-smallbuffers\nendef\nTARGET_DEVICES += engenius_eap2200\n\ndefine Device/engenius_emd1\n\t$(call Device/FitImage)\n\tDEVICE_VENDOR := EnGenius\n\tDEVICE_MODEL := EMD1\n\tDEVICE_DTS_CONFIG := config@4\n\tSOC := qcom-ipq4018\n\tIMAGE_SIZE := 30720k\n\tIMAGES += factory.bin\n\tIMAGE/sysupgrade.bin := append-kernel | append-rootfs | pad-rootfs | append-metadata\n\tIMAGE/factory.bin := qsdk-ipq-factory-nor | check-size\nendef\nTARGET_DEVICES += engenius_emd1\n\ndefine Device/engenius_emr3500\n\t$(call Device/FitImage)\n\tDEVICE_VENDOR := EnGenius\n\tDEVICE_MODEL := EMR3500\n\tDEVICE_DTS_CONFIG := config@4\n\tSOC := qcom-ipq4018\n\tKERNEL_SIZE := 4096k\n\tIMAGE_SIZE := 30720k\n\tIMAGES += factory.bin\n\tIMAGE/sysupgrade.bin := append-kernel | append-rootfs | pad-rootfs | append-metadata\n\tIMAGE/factory.bin := qsdk-ipq-factory-nor | check-size\n\tDEFAULT := n\nendef\nTARGET_DEVICES += engenius_emr3500\n\ndefine Device/engenius_ens620ext\n\t$(call Device/FitImage)\n\tDEVICE_VENDOR := EnGenius\n\tDEVICE_MODEL := ENS620EXT\n\tSOC := qcom-ipq4018\n\tDEVICE_DTS_CONFIG := config@4\n\tBLOCKSIZE := 64k\n\tPAGESIZE := 256\n\tBOARD_NAME := ENS620EXT\n\tVENDOR_ID := 0x0101\n\tPRODUCT_ID := 0x79\n\tPRODUCT_ID_NEW := 0xA4\n\tDATECODE := 190507\n\tFW_VER := 3.1.2\n\tFW_VER_NEW := 3.5.6\n\tCW_VER := 1.8.99\n\tIMAGE_SIZE := 21312k\n\tKERNEL_SIZE := 5120k\n\tFILESYSTEMS := squashfs\n\tIMAGES += factory_30.bin factory_35.bin\n\tIMAGE/sysupgrade.bin := append-kernel | append-rootfs | pad-rootfs | check-size | append-metadata\n\tIMAGE/factory_30.bin := append-kernel | pad-to $$$$(KERNEL_SIZE) | append-rootfs | pad-rootfs | check-size | SenaoFW $$$$(PRODUCT_ID) $$$$(FW_VER)\n\tIMAGE/factory_35.bin := qsdk-ipq-factory-nor | check-size | SenaoFW $$$$(PRODUCT_ID_NEW) $$$$(FW_VER_NEW)\nendef\nTARGET_DEVICES += engenius_ens620ext\n\ndefine Device/ezviz_cs-w3-wd1200g-eup\n\t$(call Device/FitImage)\n\tDEVICE_VENDOR := EZVIZ\n\tDEVICE_MODEL := CS-W3-WD1200G\n\tDEVICE_VARIANT := EUP\n\tIMAGE_SIZE := 14848k\n\tKERNEL_SIZE = 6m\n\tSOC := qcom-ipq4018\n\tIMAGE/sysupgrade.bin := append-kernel | append-rootfs | pad-rootfs | \\\n\t\tappend-metadata\n\tDEVICE_PACKAGES := -kmod-ath10k-ct kmod-ath10k-ct-smallbuffers\n\tDEVICE_COMPAT_VERSION := 2.0\n\tDEVICE_COMPAT_MESSAGE := uboot's bootcmd has to be updated (see wiki). \\\n\t\tUpgrade via sysupgrade mechanism is not possible.\nendef\nTARGET_DEVICES += ezviz_cs-w3-wd1200g-eup\n\ndefine Device/glinet_gl-ap1300\n\t$(call Device/FitImage)\n\t$(call Device/UbiFit)\n\tDEVICE_VENDOR := GL.iNet\n\tDEVICE_MODEL := GL-AP1300\n\tSOC := qcom-ipq4018\n\tDEVICE_DTS_CONFIG := config@ap.dk01.1-c2\n\tBLOCKSIZE := 128k\n\tPAGESIZE := 2048\n\tIMAGE_SIZE := 131072k\n\tKERNEL_INSTALL := 1\n\tDEVICE_PACKAGES := ipq-wifi-glinet_gl-ap1300\nendef\nTARGET_DEVICES += glinet_gl-ap1300\n\ndefine Device/glinet_gl-b1300\n\t$(call Device/FitzImage)\n\tDEVICE_VENDOR := GL.iNet\n\tDEVICE_MODEL := GL-B1300\n\tBOARD_NAME := gl-b1300\n\tSOC := qcom-ipq4029\n\tKERNEL_SIZE := 4096k\n\tIMAGE_SIZE := 26624k\n\tIMAGE/sysupgrade.bin := append-kernel |append-rootfs | pad-rootfs | append-metadata\nendef\nTARGET_DEVICES += glinet_gl-b1300\n\ndefine Device/glinet_gl-b2200\n\t$(call Device/FitzImage)\n\tDEVICE_VENDOR := GL.iNet\n\tDEVICE_MODEL := GL-B2200\n\tSOC := qcom-ipq4019\n\tDEVICE_DTS_CONFIG := config@ap.dk04.1-c3\n\tKERNEL_INITRAMFS_SUFFIX := -recovery.itb\n\tIMAGES := emmc.img.gz sysupgrade.bin\n\tIMAGE/emmc.img.gz := qsdk-ipq-app-gpt |\\\n\t\tpad-to 1024k | append-kernel |\\\n\t\tpad-to 33792k | append-rootfs |\\\n\t\tappend-metadata | gzip\n\tIMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata\n\tDEVICE_PACKAGES := ath10k-firmware-qca9888-ct ipq-wifi-glinet_gl-b2200 \\\n\t\tkmod-fs-ext4 kmod-mmc kmod-spi-dev mkf2fs e2fsprogs kmod-fs-f2fs\nendef\nTARGET_DEVICES += glinet_gl-b2200\n\ndefine Device/glinet_gl-s1300\n\t$(call Device/FitzImage)\n\tDEVICE_VENDOR := GL.iNet\n\tDEVICE_MODEL := GL-S1300\n\tSOC := qcom-ipq4029\n\tKERNEL_SIZE := 4096k\n\tIMAGE_SIZE := 26624k\n\tIMAGES := sysupgrade.bin\n\tIMAGE/sysupgrade.bin := append-kernel | append-rootfs | pad-rootfs | append-metadata\n\tDEVICE_PACKAGES := ipq-wifi-glinet_gl-s1300 kmod-fs-ext4 kmod-mmc kmod-spi-dev\nendef\nTARGET_DEVICES += glinet_gl-s1300\n\ndefine Device/linksys_ea6350v3\n\t# The Linksys EA6350v3 has a uboot bootloader that does not\n\t# support either booting lzma kernel images nor booting UBI\n\t# partitions. This uboot, however, supports raw kernel images and\n\t# gzipped images.\n\t#\n\t# As for the time of writing this, the device will boot the kernel\n\t# from a fixed address with a fixed length of 3MiB. Also, the\n\t# device has a hard-coded kernel command line that requieres the\n\t# rootfs and alt_rootfs to be in mtd11 and mtd13 respectively.\n\t# Oh... and the kernel partition overlaps with the rootfs\n\t# partition (the same for alt_kernel and alt_rootfs).\n\t#\n\t# If you are planing re-partitioning the device, you may want to\n\t# keep those details in mind:\n\t# 1. The kernel adresses you should honor are 0x00000000 and\n\t#    0x02800000 respectively.\n\t# 2. The kernel size (plus the dtb) cannot exceed 3.00MiB in size.\n\t# 3. You can use 'zImage', but not a raw 'Image' packed with lzma.\n\t# 4. The kernel command line from uboot is harcoded to boot with\n\t#    rootfs either in mtd11 or mtd13.\n\t$(call Device/FitzImage)\n\tDEVICE_VENDOR := Linksys\n\tDEVICE_MODEL := EA6350\n\tDEVICE_VARIANT := v3\n\tSOC := qcom-ipq4018\n\tBLOCKSIZE := 128k\n\tPAGESIZE := 2048\n\tKERNEL_SIZE := 3072k\n\tIMAGE_SIZE := 37888k\n\tUBINIZE_OPTS := -E 5\n\tIMAGES += factory.bin\n\tIMAGE/factory.bin := append-kernel | append-uImage-fakehdr filesystem | pad-to $$$$(KERNEL_SIZE) | append-ubi | linksys-image type=EA6350v3\nendef\nTARGET_DEVICES += linksys_ea6350v3\n\ndefine Device/linksys_ea8300\n\t$(call Device/FitzImage)\n\tDEVICE_VENDOR := Linksys\n\tDEVICE_MODEL := EA8300\n\tSOC := qcom-ipq4019\n\tKERNEL_SIZE := 3072k\n\tIMAGE_SIZE := 87040k\n\tBLOCKSIZE := 128k\n\tPAGESIZE := 2048\n\tUBINIZE_OPTS := -E 5    # EOD marks to \"hide\" factory sig at EOF\n\tIMAGES += factory.bin\n\tIMAGE/factory.bin  := append-kernel | pad-to $$$$(KERNEL_SIZE) | append-ubi | linksys-image type=EA8300\n\tDEVICE_PACKAGES := ath10k-firmware-qca9888-ct ipq-wifi-linksys_ea8300 kmod-usb-ledtrig-usbport\nendef\nTARGET_DEVICES += linksys_ea8300\n\ndefine Device/linksys_mr8300\n\t$(call Device/FitzImage)\n\tDEVICE_VENDOR := Linksys\n\tDEVICE_MODEL := MR8300\n\tSOC := qcom-ipq4019\n\tKERNEL_SIZE := 3072k\n\tIMAGE_SIZE := 87040k\n\tBLOCKSIZE := 128k\n\tPAGESIZE := 2048\n\tUBINIZE_OPTS := -E 5    # EOD marks to \"hide\" factory sig at EOF\n\tIMAGES += factory.bin\n\tIMAGE/factory.bin  := append-kernel | pad-to $$$$(KERNEL_SIZE) | append-ubi | linksys-image type=MR8300\n\tDEVICE_PACKAGES := ath10k-firmware-qca9888-ct kmod-usb-ledtrig-usbport\nendef\nTARGET_DEVICES += linksys_mr8300\n\ndefine Device/luma_wrtq-329acn\n\t$(call Device/FitImage)\n\tDEVICE_VENDOR := Luma Home\n\tDEVICE_MODEL := WRTQ-329ACN\n\tSOC := qcom-ipq4018\n\tDEVICE_PACKAGES := kmod-ath3k kmod-eeprom-at24 kmod-i2c-gpio\n\tIMAGE_SIZE := 76632k\n\tBLOCKSIZE := 128k\n\tPAGESIZE := 2048\nendef\nTARGET_DEVICES += luma_wrtq-329acn\n\ndefine Device/meraki_mr33\n\t$(call Device/FitImage)\n\tDEVICE_VENDOR := Cisco Meraki\n\tDEVICE_MODEL := MR33\n\tSOC := qcom-ipq4029\n\tBLOCKSIZE := 128k\n\tPAGESIZE := 2048\n\tDEVICE_PACKAGES := -swconfig ath10k-firmware-qca9887-ct\nendef\nTARGET_DEVICES += meraki_mr33\n\ndefine Device/mobipromo_cm520-79f\n\t$(call Device/FitzImage)\n\t$(call Device/UbiFit)\n\tDEVICE_VENDOR := MobiPromo\n\tDEVICE_MODEL := CM520-79F\n\tSOC := qcom-ipq4019\n\tBLOCKSIZE := 128k\n\tPAGESIZE := 2048\n\tDEVICE_PACKAGES := kmod-usb-ledtrig-usbport\nendef\nTARGET_DEVICES += mobipromo_cm520-79f\n\ndefine Device/netgear_ex61x0v2\n\t$(call Device/DniImage)\n\tDEVICE_VENDOR := NETGEAR\n\tDEVICE_DTS_CONFIG := config@4\n\tNETGEAR_BOARD_ID := EX6150v2series\n\tNETGEAR_HW_ID := 29765285+16+0+128+2x2\n\tIMAGE_SIZE := 14400k\n\tSOC := qcom-ipq4018\nendef\n\ndefine Device/netgear_ex6100v2\n\t$(call Device/netgear_ex61x0v2)\n\tDEVICE_MODEL := EX6100\n\tDEVICE_VARIANT := v2\nendef\nTARGET_DEVICES += netgear_ex6100v2\n\ndefine Device/netgear_ex6150v2\n\t$(call Device/netgear_ex61x0v2)\n\tDEVICE_MODEL := EX6150\n\tDEVICE_VARIANT := v2\nendef\nTARGET_DEVICES += netgear_ex6150v2\n\ndefine Device/netgear_orbi\n\t$(call Device/DniImage)\n\tSOC := qcom-ipq4019\n\tDEVICE_VENDOR := NETGEAR\n\tIMAGE/factory.img := append-kernel | pad-offset 128k 64 | \\\n\t\tappend-uImage-fakehdr filesystem | pad-to $$$$(KERNEL_SIZE) | \\\n\t\tappend-rootfs | pad-rootfs | netgear-dni\n\tIMAGE/sysupgrade.bin/squashfs := append-rootfs | pad-to 64k | \\\n\t\tsysupgrade-tar rootfs=$$$$@ | append-metadata\n\tDEVICE_PACKAGES := ath10k-firmware-qca9984-ct e2fsprogs kmod-fs-ext4 losetup\nendef\n\ndefine Device/netgear_rbx50\n\t$(call Device/netgear_orbi)\n\tNETGEAR_HW_ID := 29765352+0+4000+512+2x2+2x2+4x4\n\tKERNEL_SIZE := 3932160\n\tROOTFS_SIZE := 32243712\n\tIMAGE_SIZE := 36175872\nendef\n\ndefine Device/netgear_rbr50\n\t$(call Device/netgear_rbx50)\n\tDEVICE_MODEL := RBR50\n\tDEVICE_VARIANT := v1\n\tNETGEAR_BOARD_ID := RBR50\nendef\nTARGET_DEVICES += netgear_rbr50\n\ndefine Device/netgear_rbs50\n\t$(call Device/netgear_rbx50)\n\tDEVICE_MODEL := RBS50\n\tDEVICE_VARIANT := v1\n\tNETGEAR_BOARD_ID := RBS50\nendef\nTARGET_DEVICES += netgear_rbs50\n\ndefine Device/netgear_srx60\n\t$(call Device/netgear_orbi)\n\tNETGEAR_HW_ID := 29765352+0+4096+512+2x2+2x2+4x4\n\tKERNEL_SIZE := 3932160\n\tROOTFS_SIZE := 32243712\n\tIMAGE_SIZE := 36175872\nendef\n\ndefine Device/netgear_srr60\n\t$(call Device/netgear_srx60)\n\tDEVICE_MODEL := SRR60\n\tNETGEAR_BOARD_ID := SRR60\nendef\nTARGET_DEVICES += netgear_srr60\n\ndefine Device/netgear_srs60\n\t$(call Device/netgear_srx60)\n\tDEVICE_MODEL := SRS60\n\tNETGEAR_BOARD_ID := SRS60\nendef\nTARGET_DEVICES += netgear_srs60\n\ndefine Device/netgear_wac510\n\t$(call Device/FitImage)\n\t$(call Device/UbiFit)\n\tDEVICE_VENDOR := Netgear\n\tDEVICE_MODEL := WAC510\n\tSOC := qcom-ipq4018\n\tDEVICE_DTS_CONFIG := config@5\n\tBLOCKSIZE := 128k\n\tPAGESIZE := 2048\n\tIMAGES += nand-factory.tar\n\tIMAGE/nand-factory.tar := append-ubi | wac5xx-netgear-tar\n\tDEVICE_PACKAGES := uboot-envtools\nendef\nTARGET_DEVICES += netgear_wac510\n\ndefine Device/openmesh_a42\n\t$(call Device/FitImageLzma)\n\tDEVICE_VENDOR := OpenMesh\n\tDEVICE_MODEL := A42\n\tSOC := qcom-ipq4018\n\tDEVICE_DTS_CONFIG := config@om.a42\n\tBLOCKSIZE := 64k\n\tKERNEL = kernel-bin | lzma | fit lzma $$(DTS_DIR)/$$(DEVICE_DTS).dtb | pad-to $$(BLOCKSIZE)\n\tIMAGE_SIZE := 15616k\n\tIMAGES += factory.bin\n\tIMAGE/factory.bin := append-rootfs | pad-rootfs | openmesh-image ce_type=A42\n\tIMAGE/sysupgrade.bin/squashfs := append-rootfs | pad-rootfs | sysupgrade-tar rootfs=$$$$@ | append-metadata\nendef\nTARGET_DEVICES += openmesh_a42\n\ndefine Device/openmesh_a62\n\t$(call Device/FitImageLzma)\n\tDEVICE_VENDOR := OpenMesh\n\tDEVICE_MODEL := A62\n\tSOC := qcom-ipq4019\n\tDEVICE_DTS_CONFIG := config@om.a62\n\tBLOCKSIZE := 64k\n\tKERNEL = kernel-bin | lzma | fit lzma $$(DTS_DIR)/$$(DEVICE_DTS).dtb | pad-to $$(BLOCKSIZE)\n\tIMAGE_SIZE := 15552k\n\tIMAGES += factory.bin\n\tIMAGE/factory.bin := append-rootfs | pad-rootfs | openmesh-image ce_type=A62\n\tIMAGE/sysupgrade.bin/squashfs := append-rootfs | pad-rootfs | sysupgrade-tar rootfs=$$$$@ | append-metadata\n\tDEVICE_PACKAGES := ath10k-firmware-qca9888-ct\nendef\nTARGET_DEVICES += openmesh_a62\n\ndefine Device/p2w_r619ac\n\t$(call Device/FitzImage)\n\t$(call Device/UbiFit)\n\tDEVICE_VENDOR := P&W\n\tDEVICE_MODEL := R619AC\n\tSOC := qcom-ipq4019\n\tDEVICE_DTS_CONFIG := config@10\n\tBLOCKSIZE := 128k\n\tPAGESIZE := 2048\n\tDEVICE_PACKAGES := ipq-wifi-p2w_r619ac\nendef\n\ndefine Device/p2w_r619ac-64m\n\t$(call Device/p2w_r619ac)\n\tDEVICE_VARIANT := 64M NAND\n\tIMAGES += nand-factory.bin\n\tIMAGE/nand-factory.bin := append-ubi | qsdk-ipq-factory-nand\nendef\nTARGET_DEVICES += p2w_r619ac-64m\n\ndefine Device/p2w_r619ac-128m\n\t$(call Device/p2w_r619ac)\n\tDEVICE_VARIANT := 128M NAND\nendef\nTARGET_DEVICES += p2w_r619ac-128m\n\ndefine Device/plasmacloud_pa1200\n\t$(call Device/FitImageLzma)\n\tDEVICE_VENDOR := Plasma Cloud\n\tDEVICE_MODEL := PA1200\n\tSOC := qcom-ipq4018\n\tDEVICE_DTS_CONFIG := config@pc.pa1200\n\tBLOCKSIZE := 64k\n\tKERNEL = kernel-bin | lzma | fit lzma $$(DTS_DIR)/$$(DEVICE_DTS).dtb | pad-to $$(BLOCKSIZE)\n\tIMAGE_SIZE := 15616k\n\tIMAGES += factory.bin\n\tIMAGE/factory.bin := append-rootfs | pad-rootfs | openmesh-image ce_type=PA1200\n\tIMAGE/sysupgrade.bin/squashfs := append-rootfs | pad-rootfs | sysupgrade-tar rootfs=$$$$@ | append-metadata\nendef\nTARGET_DEVICES += plasmacloud_pa1200\n\ndefine Device/plasmacloud_pa2200\n\t$(call Device/FitImageLzma)\n\tDEVICE_VENDOR := Plasma Cloud\n\tDEVICE_MODEL := PA2200\n\tSOC := qcom-ipq4019\n\tDEVICE_DTS_CONFIG := config@pc.pa2200\n\tBLOCKSIZE := 64k\n\tKERNEL = kernel-bin | lzma | fit lzma $$(DTS_DIR)/$$(DEVICE_DTS).dtb | pad-to $$(BLOCKSIZE)\n\tIMAGE_SIZE := 15552k\n\tIMAGES += factory.bin\n\tIMAGE/factory.bin := append-rootfs | pad-rootfs | openmesh-image ce_type=PA2200\n\tIMAGE/sysupgrade.bin/squashfs := append-rootfs | pad-rootfs | sysupgrade-tar rootfs=$$$$@ | append-metadata\n\tDEVICE_PACKAGES := ath10k-firmware-qca9888-ct\nendef\nTARGET_DEVICES += plasmacloud_pa2200\n\ndefine Device/qcom_ap-dk01.1-c1\n\tDEVICE_VENDOR := Qualcomm Atheros\n\tDEVICE_MODEL := AP-DK01.1\n\tDEVICE_VARIANT := C1\n\tBOARD_NAME := ap-dk01.1-c1\n\tSOC := qcom-ipq4019\n\tDEVICE_DTS := qcom-ipq4019-ap.dk01.1-c1\n\tKERNEL_INSTALL := 1\n\tKERNEL_SIZE := 4096k\n\tIMAGE_SIZE := 26624k\n\t$(call Device/FitImage)\n\tIMAGE/sysupgrade.bin := append-kernel | pad-to $$$$(KERNEL_SIZE) | append-rootfs | pad-rootfs | append-metadata\n\tDEFAULT := n\nendef\nTARGET_DEVICES += qcom_ap-dk01.1-c1\n\ndefine Device/qcom_ap-dk04.1-c1\n\t$(call Device/FitImage)\n\t$(call Device/UbiFit)\n\tDEVICE_VENDOR := Qualcomm Atheros\n\tDEVICE_MODEL := AP-DK04.1\n\tDEVICE_VARIANT := C1\n\tSOC := qcom-ipq4019\n\tDEVICE_DTS := qcom-ipq4019-ap.dk04.1-c1\n\tKERNEL_INSTALL := 1\n\tKERNEL_SIZE := 4048k\n\tBLOCKSIZE := 128k\n\tPAGESIZE := 2048\n\tBOARD_NAME := ap-dk04.1-c1\n\tDEFAULT := n\nendef\nTARGET_DEVICES += qcom_ap-dk04.1-c1\n\ndefine Device/qxwlan_e2600ac-c1\n\t$(call Device/FitImage)\n\tDEVICE_VENDOR := Qxwlan\n\tDEVICE_MODEL := E2600AC\n\tDEVICE_VARIANT := C1\n\tBOARD_NAME := e2600ac-c1\n\tSOC := qcom-ipq4019\n\tKERNEL_SIZE := 4096k\n\tIMAGE_SIZE := 31232k\n\tIMAGE/sysupgrade.bin := append-kernel | append-rootfs | pad-rootfs | append-metadata\n\tDEVICE_PACKAGES := ipq-wifi-qxwlan_e2600ac-c1\n\tDEFAULT := n\nendef\nTARGET_DEVICES += qxwlan_e2600ac-c1\n\ndefine Device/qxwlan_e2600ac-c2\n\t$(call Device/FitImage)\n\t$(call Device/UbiFit)\n\tDEVICE_VENDOR := Qxwlan\n\tDEVICE_MODEL := E2600AC\n\tDEVICE_VARIANT := C2\n\tSOC := qcom-ipq4019\n\tKERNEL_INSTALL := 1\n\tBLOCKSIZE := 128k\n\tPAGESIZE := 2048\n\tDEVICE_PACKAGES := ipq-wifi-qxwlan_e2600ac-c2\nendef\nTARGET_DEVICES += qxwlan_e2600ac-c2\n\ndefine Device/teltonika_rutx10\n\t$(call Device/FitImage)\n\t$(call Device/UbiFit)\n\tDEVICE_VENDOR := Teltonika\n\tDEVICE_MODEL := RUTX10\n\tSOC := qcom-ipq4018\n\tDEVICE_DTS_CONFIG := config@5\n\tKERNEL_INSTALL := 1\n\tBLOCKSIZE := 128k\n\tPAGESIZE := 2048\n\tFILESYSTEMS := squashfs\n\tIMAGE/nand-factory.ubi := append-ubi | qsdk-ipq-factory-nand | append-rutx-metadata\n\tDEVICE_PACKAGES := ipq-wifi-teltonika_rutx kmod-bluetooth\nendef\nTARGET_DEVICES += teltonika_rutx10\n\ndefine Device/tel_x1pro\n\t$(call Device/FitImage)\n\tDEVICE_VENDOR := Telco\n\tDEVICE_MODEL := X1 Pro\n\tSOC := qcom-ipq4019\n\tKERNEL_SIZE := 4096k\n\tIMAGE_SIZE := 31232k\n\tIMAGE/sysupgrade.bin := append-kernel | append-rootfs | pad-rootfs | append-metadata\n\tDEVICE_PACKAGES := kmod-usb-net-qmi-wwan kmod-usb-serial-option uqmi\n\tDEFAULT := n\nendef\nTARGET_DEVICES += tel_x1pro\n\ndefine Device/unielec_u4019-32m\n\t$(call Device/FitImage)\n\tDEVICE_VENDOR := Unielec\n\tDEVICE_MODEL := U4019\n\tDEVICE_VARIANT := 32M\n\tBOARD_NAME := u4019-32m\n\tSOC := qcom-ipq4019\n\tKERNEL_SIZE := 4096k\n\tIMAGE_SIZE := 31232k\n\tIMAGE/sysupgrade.bin := append-kernel | append-rootfs | pad-rootfs | append-metadata\n\tDEFAULT := n\nendef\nTARGET_DEVICES += unielec_u4019-32m\n\ndefine Device/zte_mf286d\n\t$(call Device/FitzImage)\n\tDEVICE_VENDOR := ZTE\n\tDEVICE_MODEL := MF286D\n\tSOC := qcom-ipq4019\n\tDEVICE_DTS_CONFIG := config@ap.dk04.1-c1\n\tBLOCKSIZE := 128k\n\tPAGESIZE := 2048\n\tKERNEL_IN_UBI := 1\n\tDEVICE_PACKAGES := kmod-usb-net-qmi-wwan kmod-usb-serial-option uqmi\nendef\nTARGET_DEVICES += zte_mf286d\n\ndefine Device/zyxel_nbg6617\n\t$(call Device/FitImageLzma)\n\tDEVICE_VENDOR := ZyXEL\n\tDEVICE_MODEL := NBG6617\n\tSOC := qcom-ipq4018\n\tKERNEL_SIZE := 4096k\n\tROOTFS_SIZE := 24960k\n\tRAS_BOARD := NBG6617\n\tRAS_ROOTFS_SIZE := 19840k\n\tRAS_VERSION := \"$(VERSION_DIST) $(REVISION)\"\n\tIMAGE/sysupgrade.bin := append-kernel | append-rootfs | pad-rootfs | append-metadata\n\tIMAGES += factory.bin\n#\tThe ZyXEL firmware allows flashing thru the web-gui only when the rootfs is\n#\tat least as large as the one of the initial firmware image (not the current\n#\tone on the device). This only applies to the Web-UI, the bootlaoder ignores\n#\tthis minimum-size. However, the larger image can be flashed both ways.\n\tIMAGE/factory.bin := append-rootfs | pad-rootfs | pad-to 64k | check-size $$$$(ROOTFS_SIZE) | zyxel-ras-image separate-kernel\n\tIMAGE/sysupgrade.bin/squashfs := append-rootfs | pad-rootfs | check-size $$$$(ROOTFS_SIZE) | sysupgrade-tar rootfs=$$$$@ | append-metadata\n\tDEVICE_PACKAGES := kmod-usb-ledtrig-usbport\nendef\nTARGET_DEVICES += zyxel_nbg6617\n\ndefine Device/zyxel_wre6606\n\t$(call Device/FitImage)\n\tDEVICE_VENDOR := ZyXEL\n\tDEVICE_MODEL := WRE6606\n\tDEVICE_DTS_CONFIG := config@4\n\tSOC := qcom-ipq4018\n\tIMAGE_SIZE := 13184k\n\tIMAGE/sysupgrade.bin := append-kernel | append-rootfs | pad-rootfs | check-size | append-metadata\n\tDEVICE_PACKAGES := -kmod-ath10k-ct kmod-ath10k-ct-smallbuffers\nendef\nTARGET_DEVICES += zyxel_wre6606\n"
  },
  {
    "path": "target/linux/ipq40xx/image/mikrotik.mk",
    "content": "define Device/mikrotik_nor\n\tDEVICE_VENDOR := MikroTik\n\tBLOCKSIZE := 64k\n\tIMAGE_SIZE := 16128k\n\tKERNEL_NAME := vmlinux\n\tKERNEL := kernel-bin | append-dtb-elf\n\tIMAGES = sysupgrade.bin\n\tIMAGE/sysupgrade.bin := append-kernel | kernel2minor -s 1024 | \\\n\t\tpad-to $$$$(BLOCKSIZE) | append-rootfs | pad-rootfs | \\\n\t\tcheck-size | append-metadata\nendef\n\ndefine Device/mikrotik_nand\n\tDEVICE_VENDOR := MikroTik\n\tKERNEL_NAME := vmlinux\n\tKERNEL_INITRAMFS := kernel-bin | append-dtb-elf\n\tKERNEL := kernel-bin | append-dtb-elf | package-kernel-ubifs | \\\n\t\tubinize-kernel\n\tIMAGES := nand-sysupgrade.bin\n\tIMAGE/nand-sysupgrade.bin := sysupgrade-tar | append-metadata\nendef\n\ndefine Device/mikrotik_cap-ac\n\t$(call Device/mikrotik_nor)\n\tDEVICE_MODEL := cAP ac\n\tSOC := qcom-ipq4018\n\tDEVICE_PACKAGES := ipq-wifi-mikrotik_cap-ac -kmod-ath10k-ct \\\n\t\tkmod-ath10k-ct-smallbuffers\nendef\nTARGET_DEVICES += mikrotik_cap-ac\n\ndefine Device/mikrotik_hap-ac2\n\t$(call Device/mikrotik_nor)\n\tDEVICE_MODEL := hAP ac2\n\tSOC := qcom-ipq4018\n\tDEVICE_PACKAGES := ipq-wifi-mikrotik_hap-ac2 -kmod-ath10k-ct \\\n\t\tkmod-ath10k-ct-smallbuffers\nendef\nTARGET_DEVICES += mikrotik_hap-ac2\n\ndefine Device/mikrotik_hap-ac3\n\t$(call Device/mikrotik_nand)\n\tDEVICE_MODEL := hAP ac3\n\tSOC := qcom-ipq4019\n\tBLOCKSIZE := 128k\n\tPAGESIZE := 2048\n\tKERNEL_UBIFS_OPTS = -m $$(PAGESIZE) -e 124KiB -c $$(PAGESIZE) -x none\n\tDEVICE_PACKAGES := kmod-ledtrig-gpio ipq-wifi-mikrotik_hap-ac3\nendef\nTARGET_DEVICES += mikrotik_hap-ac3\n\ndefine Device/mikrotik_lhgg-60ad\n\t$(call Device/mikrotik_nor)\n\tDEVICE_MODEL := Wireless Wire Dish LHGG-60ad\n\tDEVICE_DTS := qcom-ipq4019-lhgg-60ad\n\tDEVICE_PACKAGES += -kmod-ath10k-ct -ath10k-firmware-qca4019-ct kmod-wil6210\nendef\nTARGET_DEVICES += mikrotik_lhgg-60ad\n\ndefine Device/mikrotik_sxtsq-5-ac\n\t$(call Device/mikrotik_nor)\n\tDEVICE_MODEL := SXTsq 5 ac (RBSXTsqG-5acD)\n\tSOC := qcom-ipq4018\n\tDEVICE_PACKAGES := ipq-wifi-mikrotik_sxtsq-5-ac rssileds\nendef\nTARGET_DEVICES += mikrotik_sxtsq-5-ac\n"
  },
  {
    "path": "target/linux/ipq40xx/mikrotik/config-default",
    "content": "CONFIG_MIKROTIK=y\nCONFIG_MIKROTIK_RB_SYSFS=y\nCONFIG_MTD_ROUTERBOOT_PARTS=y\nCONFIG_MTD_SPI_NOR_USE_VARIABLE_ERASE=y\nCONFIG_MTD_SPLIT_MINOR_FW=y\n"
  },
  {
    "path": "target/linux/ipq40xx/mikrotik/target.mk",
    "content": "BOARDNAME:=MikroTik\nFEATURES += minor\nKERNEL_IMAGES:=vmlinux\nIMAGES_DIR:=compressed\n"
  },
  {
    "path": "target/linux/ipq40xx/patches-5.10/0001-v5.12-ARM-dts-qcom-ipq4019-add-USB-devicetree-nodes.patch",
    "content": "From b8afc254b40167fd37b4d4263e750dab1f9ef157 Mon Sep 17 00:00:00 2001\nFrom: John Crispin <john@phrozen.org>\nDate: Wed, 9 Sep 2020 18:38:31 +0200\nSubject: [PATCH] ARM: dts: qcom: ipq4019: add USB devicetree nodes\n\nSince we now have driver for the USB PHY, and USB controller is already supported by the DWC3 driver lets add the necessary nodes to DTSI.\n\nSigned-off-by: John Crispin <john@phrozen.org>\nSigned-off-by: Robert Marko <robert.marko@sartura.hr>\nCc: Luka Perkov <luka.perkov@sartura.hr>\nReviewed-by: Vinod Koul <vkoul@kernel.org>\nLink: https://lore.kernel.org/r/20200909163831.1894142-1-robert.marko@sartura.hr\nSigned-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>\n---\n arch/arm/boot/dts/qcom-ipq4019.dtsi | 74 +++++++++++++++++++++++++++++\n 1 file changed, 74 insertions(+)\n\n--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi\n+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi\n@@ -606,5 +606,79 @@\n \t\t\t\treg = <4>;\n \t\t\t};\n \t\t};\n+\n+\t\tusb3_ss_phy: ssphy@9a000 {\n+\t\t\tcompatible = \"qcom,usb-ss-ipq4019-phy\";\n+\t\t\t#phy-cells = <0>;\n+\t\t\treg = <0x9a000 0x800>;\n+\t\t\treg-names = \"phy_base\";\n+\t\t\tresets = <&gcc USB3_UNIPHY_PHY_ARES>;\n+\t\t\treset-names = \"por_rst\";\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tusb3_hs_phy: hsphy@a6000 {\n+\t\t\tcompatible = \"qcom,usb-hs-ipq4019-phy\";\n+\t\t\t#phy-cells = <0>;\n+\t\t\treg = <0xa6000 0x40>;\n+\t\t\treg-names = \"phy_base\";\n+\t\t\tresets = <&gcc USB3_HSPHY_POR_ARES>, <&gcc USB3_HSPHY_S_ARES>;\n+\t\t\treset-names = \"por_rst\", \"srif_rst\";\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tusb3: usb3@8af8800 {\n+\t\t\tcompatible = \"qcom,dwc3\";\n+\t\t\treg = <0x8af8800 0x100>;\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <1>;\n+\t\t\tclocks = <&gcc GCC_USB3_MASTER_CLK>,\n+\t\t\t\t <&gcc GCC_USB3_SLEEP_CLK>,\n+\t\t\t\t <&gcc GCC_USB3_MOCK_UTMI_CLK>;\n+\t\t\tclock-names = \"master\", \"sleep\", \"mock_utmi\";\n+\t\t\tranges;\n+\t\t\tstatus = \"disabled\";\n+\n+\t\t\tdwc3@8a00000 {\n+\t\t\t\tcompatible = \"snps,dwc3\";\n+\t\t\t\treg = <0x8a00000 0xf8000>;\n+\t\t\t\tinterrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\t\tphys = <&usb3_hs_phy>, <&usb3_ss_phy>;\n+\t\t\t\tphy-names = \"usb2-phy\", \"usb3-phy\";\n+\t\t\t\tdr_mode = \"host\";\n+\t\t\t};\n+\t\t};\n+\n+\t\tusb2_hs_phy: hsphy@a8000 {\n+\t\t\tcompatible = \"qcom,usb-hs-ipq4019-phy\";\n+\t\t\t#phy-cells = <0>;\n+\t\t\treg = <0xa8000 0x40>;\n+\t\t\treg-names = \"phy_base\";\n+\t\t\tresets = <&gcc USB2_HSPHY_POR_ARES>, <&gcc USB2_HSPHY_S_ARES>;\n+\t\t\treset-names = \"por_rst\", \"srif_rst\";\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tusb2: usb2@60f8800 {\n+\t\t\tcompatible = \"qcom,dwc3\";\n+\t\t\treg = <0x60f8800 0x100>;\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <1>;\n+\t\t\tclocks = <&gcc GCC_USB2_MASTER_CLK>,\n+\t\t\t\t <&gcc GCC_USB2_SLEEP_CLK>,\n+\t\t\t\t <&gcc GCC_USB2_MOCK_UTMI_CLK>;\n+\t\t\tclock-names = \"master\", \"sleep\", \"mock_utmi\";\n+\t\t\tranges;\n+\t\t\tstatus = \"disabled\";\n+\n+\t\t\tdwc3@6000000 {\n+\t\t\t\tcompatible = \"snps,dwc3\";\n+\t\t\t\treg = <0x6000000 0xf8000>;\n+\t\t\t\tinterrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\t\tphys = <&usb2_hs_phy>;\n+\t\t\t\tphy-names = \"usb2-phy\";\n+\t\t\t\tdr_mode = \"host\";\n+\t\t\t};\n+\t\t};\n \t};\n };\n"
  },
  {
    "path": "target/linux/ipq40xx/patches-5.10/0002-v5.12-ARM-dts-qcom-ipq4019-add-more-labels.patch",
    "content": "From d1ae4c808e7802008225078d93fbadd4aeea1e2d Mon Sep 17 00:00:00 2001\nFrom: Robert Marko <robert.marko@sartura.hr>\nDate: Wed, 9 Sep 2020 21:56:37 +0200\nSubject: [PATCH] ARM: dts: qcom: ipq4019: add more labels\n\nLets add labels to more commonly used nodes for easier modification in board DTS files.\n\nSigned-off-by: Robert Marko <robert.marko@sartura.hr>\nCc: Luka Perkov <luka.perkov@sartura.hr>\nLink: https://lore.kernel.org/r/20200909195640.3127341-2-robert.marko@sartura.hr\nSigned-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>\n---\n arch/arm/boot/dts/qcom-ipq4019.dtsi | 6 +++---\n 1 file changed, 3 insertions(+), 3 deletions(-)\n\n--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi\n+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi\n@@ -191,7 +191,7 @@\n \t\t\treg = <0x1800000 0x60000>;\n \t\t};\n \n-\t\trng@22000 {\n+\t\tprng: rng@22000 {\n \t\t\tcompatible = \"qcom,prng\";\n \t\t\treg = <0x22000 0x140>;\n \t\t\tclocks = <&gcc GCC_PRNG_AHB_CLK>;\n@@ -301,7 +301,7 @@\n \t\t\tstatus = \"disabled\";\n \t\t};\n \n-\t\tcrypto@8e3a000 {\n+\t\tcrypto: crypto@8e3a000 {\n \t\t\tcompatible = \"qcom,crypto-v5.1\";\n \t\t\treg = <0x08e3a000 0x6000>;\n \t\t\tclocks = <&gcc GCC_CRYPTO_AHB_CLK>,\n@@ -387,7 +387,7 @@\n \t\t\tdma-names = \"rx\", \"tx\";\n \t\t};\n \n-\t\twatchdog@b017000 {\n+\t\twatchdog: watchdog@b017000 {\n \t\t\tcompatible = \"qcom,kpss-wdt\", \"qcom,kpss-wdt-ipq4019\";\n \t\t\treg = <0xb017000 0x40>;\n \t\t\tclocks = <&sleep_clk>;\n"
  },
  {
    "path": "target/linux/ipq40xx/patches-5.10/0003-v5.12-ARM-dts-qcom-ipq4019-add-SDHCI-VQMMC-LDO-node.patch",
    "content": "From e14775aa2feac18e7378cb8009b55c13d4236b50 Mon Sep 17 00:00:00 2001\nFrom: Robert Marko <robert.marko@sartura.hr>\nDate: Mon, 7 Sep 2020 12:19:37 +0200\nSubject: [PATCH] ARM: dts: qcom: ipq4019: add SDHCI VQMMC LDO node\n\nSince we now have driver for the SDHCI VQMMC LDO needed\nfor I/0 voltage levels lets introduce the necessary node for it.\n\nSigned-off-by: Robert Marko <robert.marko@sartura.hr>\nCc: Luka Perkov <luka.perkov@sartura.hr>\nLink: https://lore.kernel.org/r/20200907101937.10155-1-robert.marko@sartura.hr\nSigned-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>\n---\n arch/arm/boot/dts/qcom-ipq4019.dtsi | 10 ++++++++++\n 1 file changed, 10 insertions(+)\n\n--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi\n+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi\n@@ -210,6 +210,16 @@\n \t\t\tinterrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;\n \t\t};\n \n+\t\tvqmmc: regulator@1948000 {\n+\t\t\tcompatible = \"qcom,vqmmc-ipq4019-regulator\";\n+\t\t\treg = <0x01948000 0x4>;\n+\t\t\tregulator-name = \"vqmmc\";\n+\t\t\tregulator-min-microvolt = <1500000>;\n+\t\t\tregulator-max-microvolt = <3000000>;\n+\t\t\tregulator-always-on;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n \t\tsdhci: sdhci@7824900 {\n \t\t\tcompatible = \"qcom,sdhci-msm-v4\";\n \t\t\treg = <0x7824900 0x11c>, <0x7824000 0x800>;\n"
  },
  {
    "path": "target/linux/ipq40xx/patches-5.10/104-clk-fix-apss-cpu-overclocking.patch",
    "content": "From f2b87dc1028b710ec8ce25808b9d21f92b376184 Mon Sep 17 00:00:00 2001\nFrom: Christian Lamparter <chunkeey@googlemail.com>\nDate: Sun, 11 Mar 2018 14:41:31 +0100\nSubject: [PATCH 2/2] clk: fix apss cpu overclocking\n\nThere's an interaction issue between the clk changes:\"\nclk: qcom: ipq4019: Add the apss cpu pll divider clock node\nclk: qcom: ipq4019: remove fixed clocks and add pll clocks\n\" and the cpufreq-dt.\n\ncpufreq-dt is now spamming the kernel-log with the following:\n\n[ 1099.190658] cpu cpu0: dev_pm_opp_set_rate: failed to find current OPP\nfor freq 761142857 (-34)\n\nThis only happens on certain devices like the Compex WPJ428\nand AVM FritzBox!4040. However, other devices like the Asus\nRT-AC58U and Meraki MR33 work just fine.\n\nThe issue stem from the fact that all higher CPU-Clocks\nare achieved by switching the clock-parent to the P_DDRPLLAPSS\n(ddrpllapss). Which is set by Qualcomm's proprietary bootcode\nas part of the DDR calibration.\n\nFor example, the FB4040 uses 256 MiB Nanya NT5CC128M16IP clocked\nat round 533 MHz (ddrpllsdcc = 190285714 Hz).\n\nwhereas the 128 MiB Nanya NT5CC64M16GP-DI in the ASUS RT-AC58U is\nclocked at a slightly higher 537 MHz ( ddrpllsdcc = 192000000 Hz).\n\nThis patch attempts to fix the issue by modifying\nclk_cpu_div_round_rate(), clk_cpu_div_set_rate(), clk_cpu_div_recalc_rate()\nto use a new qcom_find_freq_close() function, which returns the closest\nmatching frequency, instead of the next higher. This way, the SoC in\nthe FB4040 (with its max clock speed of 710.4 MHz) will no longer\ntry to overclock to 761 MHz.\n\nFixes: d83dcacea18 (\"clk: qcom: ipq4019: Add the apss cpu pll divider clock node\")\nSigned-off-by: Christian Lamparter <chunkeey@gmail.com>\nSigned-off-by: John Crispin <john@phrozen.org>\n---\n drivers/clk/qcom/gcc-ipq4019.c | 34 +++++++++++++++++++++++++++++++---\n 1 file changed, 31 insertions(+), 3 deletions(-)\n\n--- a/drivers/clk/qcom/gcc-ipq4019.c\n+++ b/drivers/clk/qcom/gcc-ipq4019.c\n@@ -1243,6 +1243,29 @@ static const struct clk_fepll_vco gcc_fe\n \t.reg = 0x2f020,\n };\n \n+\n+const struct freq_tbl *qcom_find_freq_close(const struct freq_tbl *f,\n+\t\t\t\t\t     unsigned long rate)\n+{\n+\tconst struct freq_tbl *last = NULL;\n+\n+\tfor ( ; f->freq; f++) {\n+\t\tif (rate == f->freq)\n+\t\t\treturn f;\n+\n+\t\tif (f->freq > rate) {\n+\t\t\tif (!last ||\n+\t\t\t   (f->freq - rate) < (rate - last->freq))\n+\t\t\t\treturn f;\n+\t\t\telse\n+\t\t\t\treturn last;\n+\t\t}\n+\t\tlast = f;\n+\t}\n+\n+\treturn last;\n+}\n+\n /*\n  * Round rate function for APSS CPU PLL Clock divider.\n  * It looks up the frequency table and returns the next higher frequency\n@@ -1255,7 +1278,7 @@ static long clk_cpu_div_round_rate(struc\n \tstruct clk_hw *p_hw;\n \tconst struct freq_tbl *f;\n \n-\tf = qcom_find_freq(pll->freq_tbl, rate);\n+\tf = qcom_find_freq_close(pll->freq_tbl, rate);\n \tif (!f)\n \t\treturn -EINVAL;\n \n@@ -1278,7 +1301,7 @@ static int clk_cpu_div_set_rate(struct c\n \tu32 mask;\n \tint ret;\n \n-\tf = qcom_find_freq(pll->freq_tbl, rate);\n+\tf = qcom_find_freq_close(pll->freq_tbl, rate);\n \tif (!f)\n \t\treturn -EINVAL;\n \n@@ -1305,6 +1328,7 @@ static unsigned long\n clk_cpu_div_recalc_rate(struct clk_hw *hw,\n \t\t\tunsigned long parent_rate)\n {\n+\tconst struct freq_tbl *f;\n \tstruct clk_fepll *pll = to_clk_fepll(hw);\n \tu32 cdiv, pre_div;\n \tu64 rate;\n@@ -1325,7 +1349,11 @@ clk_cpu_div_recalc_rate(struct clk_hw *h\n \trate = clk_fepll_vco_calc_rate(pll, parent_rate) * 2;\n \tdo_div(rate, pre_div);\n \n-\treturn rate;\n+\tf = qcom_find_freq_close(pll->freq_tbl, rate);\n+\tif (!f)\n+\t\treturn rate;\n+\n+\treturn f->freq;\n };\n \n static const struct clk_ops clk_regmap_cpu_div_ops = {\n"
  },
  {
    "path": "target/linux/ipq40xx/patches-5.10/300-clk-qcom-ipq4019-add-ess-reset.patch",
    "content": "From 480c1f7648fc586db12d6003c717c23667a4fcf0 Mon Sep 17 00:00:00 2001\nFrom: Ram Chandra Jangir <rjangir@codeaurora.org>\nDate: Tue, 28 Mar 2017 22:35:33 +0530\nSubject: [PATCH] clk: qcom: ipq4019: add ess reset\n\nAdded the ESS reset in IPQ4019 GCC.\n\nSigned-off-by: Ram Chandra Jangir <rjangir@codeaurora.org>\n---\n drivers/clk/qcom/gcc-ipq4019.c               | 11 +++++++++++\n include/dt-bindings/clock/qcom,gcc-ipq4019.h | 11 +++++++++++\n 2 files changed, 22 insertions(+)\n\n--- a/drivers/clk/qcom/gcc-ipq4019.c\n+++ b/drivers/clk/qcom/gcc-ipq4019.c\n@@ -1736,6 +1736,17 @@ static const struct qcom_reset_map gcc_i\n \t[GCC_TCSR_BCR] = {0x22000, 0},\n \t[GCC_MPM_BCR] = {0x24000, 0},\n \t[GCC_SPDM_BCR] = {0x25000, 0},\n+\t[ESS_MAC1_ARES] = {0x1200C, 0},\n+\t[ESS_MAC2_ARES] = {0x1200C, 1},\n+\t[ESS_MAC3_ARES] = {0x1200C, 2},\n+\t[ESS_MAC4_ARES] = {0x1200C, 3},\n+\t[ESS_MAC5_ARES] = {0x1200C, 4},\n+\t[ESS_PSGMII_ARES] = {0x1200C, 5},\n+\t[ESS_MAC1_CLK_DIS] = {0x1200C, 8},\n+\t[ESS_MAC2_CLK_DIS] = {0x1200C, 9},\n+\t[ESS_MAC3_CLK_DIS] = {0x1200C, 10},\n+\t[ESS_MAC4_CLK_DIS] = {0x1200C, 11},\n+\t[ESS_MAC5_CLK_DIS] = {0x1200C, 12},\n };\n \n static const struct regmap_config gcc_ipq4019_regmap_config = {\n--- a/include/dt-bindings/clock/qcom,gcc-ipq4019.h\n+++ b/include/dt-bindings/clock/qcom,gcc-ipq4019.h\n@@ -165,5 +165,16 @@\n #define GCC_QDSS_BCR\t\t\t\t\t69\n #define GCC_MPM_BCR\t\t\t\t\t70\n #define GCC_SPDM_BCR\t\t\t\t\t71\n+#define ESS_MAC1_ARES\t\t\t\t\t72\n+#define ESS_MAC2_ARES\t\t\t\t\t73\n+#define ESS_MAC3_ARES\t\t\t\t\t74\n+#define ESS_MAC4_ARES\t\t\t\t\t75\n+#define ESS_MAC5_ARES\t\t\t\t\t76\n+#define ESS_PSGMII_ARES\t\t\t\t\t77\n+#define ESS_MAC1_CLK_DIS\t\t\t\t78\n+#define ESS_MAC2_CLK_DIS\t\t\t\t79\n+#define ESS_MAC3_CLK_DIS\t\t\t\t80\n+#define ESS_MAC4_CLK_DIS\t\t\t\t81\n+#define ESS_MAC5_CLK_DIS\t\t\t\t82\n \n #endif\n"
  },
  {
    "path": "target/linux/ipq40xx/patches-5.10/301-arm-compressed-add-appended-DTB-section.patch",
    "content": "From 0843a61d6913bdac8889eb048ed89f7903059787 Mon Sep 17 00:00:00 2001\nFrom: Robert Marko <robimarko@gmail.com>\nDate: Fri, 30 Oct 2020 13:36:31 +0100\nSubject: [PATCH] arm: compressed: add appended DTB section\n\nThis adds a appended_dtb section to the ARM decompressor\nlinker script.\n\nThis allows using the existing ARM zImage appended DTB support for\nappending a DTB to the raw ELF kernel.\n\nIts size is set to 1MB max to match the zImage appended DTB size limit.\n\nTo use it to pass the DTB to the kernel, objcopy is used:\n\nobjcopy --set-section-flags=.appended_dtb=alloc,contents \\\n\t--update-section=.appended_dtb=<target>.dtb vmlinux\n\nThis is based off the following patch:\nhttps://github.com/openwrt/openwrt/commit/c063e27e02a9dcac0e7f5877fb154e58fa3e1a69\n\nSigned-off-by: Robert Marko <robimarko@gmail.com>\n---\n arch/arm/boot/compressed/vmlinux.lds.S | 9 ++++++++-\n 1 file changed, 8 insertions(+), 1 deletion(-)\n\n--- a/arch/arm/boot/compressed/vmlinux.lds.S\n+++ b/arch/arm/boot/compressed/vmlinux.lds.S\n@@ -101,6 +101,13 @@ SECTIONS\n \n   _edata = .;\n \n+  .appended_dtb : {\n+    /* leave space for appended DTB */\n+    . += 0x100000;\n+  }\n+\n+  _edata_dtb = .;\n+\n   /*\n    * The image_end section appears after any additional loadable sections\n    * that the linker may decide to insert in the binary image.  Having\n@@ -138,4 +145,4 @@ SECTIONS\n \n   ARM_ASSERTS\n }\n-ASSERT(_edata_real == _edata, \"error: zImage file size is incorrect\");\n+ASSERT(_edata_real == _edata_dtb, \"error: zImage file size is incorrect\");\n"
  },
  {
    "path": "target/linux/ipq40xx/patches-5.10/302-arm-compressed-set-ipq40xx-watchdog-to-allow-boot.patch",
    "content": "From 11d6a6128a5a07c429941afc202b6e62a19771be Mon Sep 17 00:00:00 2001\nFrom: John Thomson <git@johnthomson.fastmail.com.au>\nDate: Fri, 23 Oct 2020 19:42:36 +1000\nSubject: [PATCH 2/2] arm: compressed: set ipq40xx watchdog to allow boot\n\nFor IPQ40XX systems where the SoC watchdog is activated before linux,\nthe watchdog timer may be too small for linux to finish uncompress,\nboot, and watchdog management start.\nIf the watchdog is enabled, set the timeout for it to 30 seconds.\nThe functionality and offsets were copied from:\ndrivers/watchdog/qcom-wdt.c qcom_wdt_set_timeout & qcom_wdt_start\nThe watchdog memory address was taken from:\narch/arm/boot/dts/qcom-ipq4019.dtsi\n\nThis was required on Mikrotik IPQ40XX consumer hardware using Mikrotik's\nRouterBoot bootloader.\n\nSigned-off-by: John Thomson <git@johnthomson.fastmail.com.au>\n---\n arch/arm/boot/compressed/head.S | 35 +++++++++++++++++++++++++++++++++\n 1 file changed, 35 insertions(+)\n\n--- a/arch/arm/boot/compressed/head.S\n+++ b/arch/arm/boot/compressed/head.S\n@@ -602,6 +602,41 @@ not_relocated:\tmov\tr0, #0\n \t\tbic\tr4, r4, #1\n \t\tblne\tcache_on\n \n+/* Set the Qualcom IPQ40xx watchdog timeout to 30 seconds\n+ * if it is enabled, so that there is time for kernel\n+ * to decompress, boot, and take over the watchdog.\n+ * data and functionality from drivers/watchdog/qcom-wdt.c\n+ * address from arch/arm/boot/dts/qcom-ipq4019.dtsi\n+ */\n+#ifdef CONFIG_ARCH_IPQ40XX\n+watchdog_set:\n+\t\t/* offsets:\n+\t\t * 0x04 reset\t(=1 resets countdown)\n+\t\t * 0x08 enable\t(=0 disables)\n+\t\t * 0x0c status\t(=1 when SoC was reset by watchdog)\n+\t\t * 0x10 bark\t(=timeout warning in ticks)\n+\t\t * 0x14 bite\t(=timeout reset in ticks)\n+\t\t * clock rate is 1<<15 hertz\n+\t\t */\n+\t\t.equ watchdog, 0x0b017000\t@Store watchdog base address\n+\t\tmovw r0, #:lower16:watchdog\n+\t\tmovt r0, #:upper16:watchdog\n+\t\tldr r1, [r0, #0x08]\t@Get enabled?\n+\t\tcmp r1, #1\t\t@If not enabled, do not change\n+\t\tbne watchdog_finished\n+\t\tmov r1, #0\n+\t\tstr r1, [r0, #0x08]\t@Disable the watchdog\n+\t\tmov r1, #1\n+\t\tstr r1, [r0, #0x04]\t@Pet the watchdog\n+\t\tmov r1, #30\t\t@30 seconds timeout\n+\t\tlsl r1, r1, #15\t\t@converted to ticks\n+\t\tstr r1, [r0, #0x10]\t@Set the bark timeout\n+\t\tstr r1, [r0, #0x14]\t@Set the bite timeout\n+\t\tmov r1, #1\n+\t\tstr r1, [r0, #0x08]\t@Enable the watchdog\n+watchdog_finished:\n+#endif /* CONFIG_ARCH_IPQ40XX */\n+\n /*\n  * The C runtime environment should now be setup sufficiently.\n  * Set up some pointers, and start decompressing.\n"
  },
  {
    "path": "target/linux/ipq40xx/patches-5.10/400-mmc-sdhci-sdhci-msm-use-sdhci_set_clock-instead-of-s.patch",
    "content": "From f63ea127643a605da97090ce585fdd7c2d17fa42 Mon Sep 17 00:00:00 2001\nFrom: Robert Marko <robert.marko@sartura.hr>\nDate: Mon, 14 Dec 2020 13:35:35 +0100\nSubject: [PATCH] mmc: sdhci-msm: use sdhci_set_clock\n\nWhen using sdhci_msm_set_clock clock setting will fail, so lets\nuse the generic sdhci_set_clock.\n\nSigned-off-by: Robert Marko <robert.marko@sartura.hr>\n---\n drivers/mmc/host/sdhci-msm.c | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/drivers/mmc/host/sdhci-msm.c\n+++ b/drivers/mmc/host/sdhci-msm.c\n@@ -2191,7 +2191,7 @@ MODULE_DEVICE_TABLE(of, sdhci_msm_dt_mat\n \n static const struct sdhci_ops sdhci_msm_ops = {\n \t.reset = sdhci_msm_reset,\n-\t.set_clock = sdhci_msm_set_clock,\n+\t.set_clock = sdhci_set_clock,\n \t.get_min_clock = sdhci_msm_get_min_clock,\n \t.get_max_clock = sdhci_msm_get_max_clock,\n \t.set_bus_width = sdhci_set_bus_width,\n"
  },
  {
    "path": "target/linux/ipq40xx/patches-5.10/420-firmware-qcom-scm-disable-SDI.patch",
    "content": "--- a/drivers/firmware/qcom_scm.c\n+++ b/drivers/firmware/qcom_scm.c\n@@ -404,6 +404,20 @@ static int __qcom_scm_set_dload_mode(str\n \treturn qcom_scm_call_atomic(__scm->dev, &desc, NULL);\n }\n \n+static int __qcom_scm_disable_sdi(struct device *dev)\n+{\n+\tstruct qcom_scm_desc desc = {\n+\t\t.svc = QCOM_SCM_SVC_BOOT,\n+\t\t.cmd = QCOM_SCM_BOOT_CONFIG_SDI,\n+\t\t.arginfo = QCOM_SCM_ARGS(2),\n+\t\t.args[0] = 1  /* 1: disable watchdog debug */,\n+\t\t.args[1] = 0  /* 0: disable SDI */,\n+\t\t.owner = ARM_SMCCC_OWNER_SIP,\n+\t};\n+\n+\treturn qcom_scm_call(__scm->dev, &desc, NULL);\n+}\n+\n static void qcom_scm_set_download_mode(bool enable)\n {\n \tbool avail;\n@@ -1250,6 +1264,13 @@ static int qcom_scm_probe(struct platfor\n \tif (download_mode)\n \t\tqcom_scm_set_download_mode(true);\n \n+\t/*\n+\t * Factory firmware leaves SDI (a debug interface), which prevents\n+\t * clean reboot.\n+\t */\n+\tif (of_machine_is_compatible(\"google,wifi\"))\n+\t\t__qcom_scm_disable_sdi(__scm->dev);\n+\n \treturn 0;\n }\n \n--- a/drivers/firmware/qcom_scm.h\n+++ b/drivers/firmware/qcom_scm.h\n@@ -77,6 +77,7 @@ extern int scm_legacy_call(struct device\n #define QCOM_SCM_SVC_BOOT\t\t0x01\n #define QCOM_SCM_BOOT_SET_ADDR\t\t0x01\n #define QCOM_SCM_BOOT_TERMINATE_PC\t0x02\n+#define QCOM_SCM_BOOT_CONFIG_SDI\t0x09\n #define QCOM_SCM_BOOT_SET_DLOAD_MODE\t0x10\n #define QCOM_SCM_BOOT_SET_REMOTE_STATE\t0x0a\n #define QCOM_SCM_FLUSH_FLAG_MASK\t0x3\n"
  },
  {
    "path": "target/linux/ipq40xx/patches-5.10/421-firmware-qcom-scm-cold-boot-address.patch",
    "content": "--- a/drivers/firmware/qcom_scm-legacy.c\n+++ b/drivers/firmware/qcom_scm-legacy.c\n@@ -13,6 +13,9 @@\n #include <linux/arm-smccc.h>\n #include <linux/dma-mapping.h>\n \n+#include <asm/cacheflush.h>\n+#include <asm/outercache.h>\n+\n #include \"qcom_scm.h\"\n \n static DEFINE_MUTEX(qcom_scm_lock);\n@@ -117,6 +120,25 @@ static void __scm_legacy_do(const struct\n \t} while (res->a0 == QCOM_SCM_INTERRUPTED);\n }\n \n+static void qcom_scm_inv_range(unsigned long start, unsigned long end)\n+{\n+\tu32 cacheline_size, ctr;\n+\n+\tasm volatile(\"mrc p15, 0, %0, c0, c0, 1\" : \"=r\" (ctr));\n+\tcacheline_size = 4 << ((ctr >> 16) & 0xf);\n+\n+\tstart = round_down(start, cacheline_size);\n+\tend = round_up(end, cacheline_size);\n+\touter_inv_range(start, end);\n+\twhile (start < end) {\n+\t\tasm (\"mcr p15, 0, %0, c7, c6, 1\" : : \"r\" (start)\n+\t\t     : \"memory\");\n+\t\tstart += cacheline_size;\n+\t}\n+\tdsb();\n+\tisb();\n+}\n+\n /**\n  * qcom_scm_call() - Sends a command to the SCM and waits for the command to\n  * finish processing.\n@@ -160,10 +182,16 @@ int scm_legacy_call(struct device *dev,\n \n \trsp = scm_legacy_command_to_response(cmd);\n \n-\tcmd_phys = dma_map_single(dev, cmd, alloc_len, DMA_TO_DEVICE);\n-\tif (dma_mapping_error(dev, cmd_phys)) {\n-\t\tkfree(cmd);\n-\t\treturn -ENOMEM;\n+\tif (dev) {\n+\t\tcmd_phys = dma_map_single(dev, cmd, alloc_len, DMA_TO_DEVICE);\n+\t\tif (dma_mapping_error(dev, cmd_phys)) {\n+\t\t\tkfree(cmd);\n+\t\t\treturn -ENOMEM;\n+\t\t}\n+\t} else {\n+\t\tcmd_phys = virt_to_phys(cmd);\n+\t\t__cpuc_flush_dcache_area(cmd, alloc_len);\n+\t\touter_flush_range(cmd_phys, cmd_phys + alloc_len);\n \t}\n \n \tsmc.args[0] = 1;\n@@ -179,13 +207,26 @@ int scm_legacy_call(struct device *dev,\n \t\tgoto out;\n \n \tdo {\n-\t\tdma_sync_single_for_cpu(dev, cmd_phys + sizeof(*cmd) + cmd_len,\n-\t\t\t\t\tsizeof(*rsp), DMA_FROM_DEVICE);\n+\t\tif (dev) {\n+\t\t\tdma_sync_single_for_cpu(dev, cmd_phys + sizeof(*cmd) +\n+\t\t\t\t\t\tcmd_len, sizeof(*rsp),\n+\t\t\t\t\t\tDMA_FROM_DEVICE);\n+\t\t} else {\n+\t\t\tunsigned long start = (uintptr_t)cmd + sizeof(*cmd) +\n+\t\t\t\t\t      cmd_len;\n+\t\t\tqcom_scm_inv_range(start, start + sizeof(*rsp));\n+\t\t}\n \t} while (!rsp->is_complete);\n \n-\tdma_sync_single_for_cpu(dev, cmd_phys + sizeof(*cmd) + cmd_len +\n-\t\t\t\tle32_to_cpu(rsp->buf_offset),\n-\t\t\t\tresp_len, DMA_FROM_DEVICE);\n+\tif (dev) {\n+\t\tdma_sync_single_for_cpu(dev, cmd_phys + sizeof(*cmd) + cmd_len +\n+\t\t\t\t\tle32_to_cpu(rsp->buf_offset),\n+\t\t\t\t\tresp_len, DMA_FROM_DEVICE);\n+\t} else {\n+\t\tunsigned long start = (uintptr_t)cmd + sizeof(*cmd) + cmd_len +\n+\t\t\t\t      le32_to_cpu(rsp->buf_offset);\n+\t\tqcom_scm_inv_range(start, start + resp_len);\n+\t}\n \n \tif (res) {\n \t\tres_buf = scm_legacy_get_response_buffer(rsp);\n@@ -193,7 +234,8 @@ int scm_legacy_call(struct device *dev,\n \t\t\tres->result[i] = le32_to_cpu(res_buf[i]);\n \t}\n out:\n-\tdma_unmap_single(dev, cmd_phys, alloc_len, DMA_TO_DEVICE);\n+\tif (dev)\n+\t\tdma_unmap_single(dev, cmd_phys, alloc_len, DMA_TO_DEVICE);\n \tkfree(cmd);\n \treturn ret;\n }\n--- a/drivers/firmware/qcom_scm.c\n+++ b/drivers/firmware/qcom_scm.c\n@@ -344,6 +344,17 @@ int qcom_scm_set_cold_boot_addr(void *en\n \tdesc.args[0] = flags;\n \tdesc.args[1] = virt_to_phys(entry);\n \n+\t/*\n+\t * Factory firmware doesn't support the atomic variant. Non-atomic SCMs\n+\t * require ugly DMA invalidation support that was dropped upstream a\n+\t * while ago. For more info, see:\n+\t *\n+\t *  [RFC] qcom_scm: IPQ4019 firmware does not support atomic API?\n+\t *  https://lore.kernel.org/linux-arm-msm/20200913201608.GA3162100@bDebian/\n+\t */\n+\tif (of_machine_is_compatible(\"google,wifi\"))\n+\t\treturn qcom_scm_call(__scm ? __scm->dev : NULL, &desc, NULL);\n+\n \treturn qcom_scm_call_atomic(__scm ? __scm->dev : NULL, &desc, NULL);\n }\n EXPORT_SYMBOL(qcom_scm_set_cold_boot_addr);\n"
  },
  {
    "path": "target/linux/ipq40xx/patches-5.10/702-dts-ipq4019-add-PHY-switch-nodes.patch",
    "content": "From 9deeec35dd3b628b95624e41d4e04acf728991ba Mon Sep 17 00:00:00 2001\nFrom: Christian Lamparter <chunkeey@gmail.com>\nDate: Sun, 20 Nov 2016 02:20:54 +0100\nSubject: [PATCH] dts: ipq4019: add PHY/switch nodes\n\nThis patch adds both the \"qcom,ess-switch\" and \"qcom,ess-psgmii\"\nnodes which are needed for the ar40xx.c driver to initialize the\nswitch.\n\nSigned-off-by: Christian Lamparter <chunkeey@gmail.com>\n---\n arch/arm/boot/dts/qcom-ipq4019.dtsi | 23 +++++++++++++++++++++++\n 1 file changed, 23 insertions(+)\n\n--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi\n+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi\n@@ -617,6 +617,29 @@\n \t\t\t};\n \t\t};\n \n+\t\tess-switch@c000000 {\n+\t\t\tcompatible = \"qcom,ess-switch\";\n+\t\t\treg = <0xc000000 0x80000>;\n+\t\t\tswitch_access_mode = \"local bus\";\n+\t\t\tresets = <&gcc ESS_RESET>;\n+\t\t\treset-names = \"ess_rst\";\n+\t\t\tclocks = <&gcc GCC_ESS_CLK>;\n+\t\t\tclock-names = \"ess_clk\";\n+\t\t\tswitch_cpu_bmp = <0x1>;\n+\t\t\tswitch_lan_bmp = <0x1e>;\n+\t\t\tswitch_wan_bmp = <0x20>;\n+\t\t\tswitch_mac_mode = <0>; /* PORT_WRAPPER_PSGMII */\n+\t\t\tswitch_initvlas = <0x7c 0x54>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tess-psgmii@98000 {\n+\t\t\tcompatible = \"qcom,ess-psgmii\";\n+\t\t\treg = <0x98000 0x800>;\n+\t\t\tpsgmii_access_mode = \"local bus\";\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n \t\tusb3_ss_phy: ssphy@9a000 {\n \t\t\tcompatible = \"qcom,usb-ss-ipq4019-phy\";\n \t\t\t#phy-cells = <0>;\n"
  },
  {
    "path": "target/linux/ipq40xx/patches-5.10/703-net-IPQ4019-needs-rfs-vlan_tag-callbacks-in.patch",
    "content": "From 7c129254adb1093d10a62ed7bf7b956fcc6ffe34 Mon Sep 17 00:00:00 2001\nFrom: Rakesh Nair <ranair@codeaurora.org>\nDate: Wed, 20 Jul 2016 15:02:01 +0530\nSubject: [PATCH] net: IPQ4019 needs rfs/vlan_tag callbacks in\n netdev_ops\n\nAdd callback support to get default vlan tag and register\nreceive flow steering filter.\n\nUsed by IPQ4019 ess-edma driver.\n\nBUG=chrome-os-partner:33096\nTEST=none\n\nChange-Id: I266070e4a0fbe4a0d9966fe79a71e50ec4f26c75\nSigned-off-by: Rakesh Nair <ranair@codeaurora.org>\nReviewed-on: https://chromium-review.googlesource.com/362203\nCommit-Ready: Grant Grundler <grundler@chromium.org>\nTested-by: Grant Grundler <grundler@chromium.org>\nReviewed-by: Grant Grundler <grundler@chromium.org>\n---\n include/linux/netdevice.h | 13 +++++++++++++\n 1 file changed, 13 insertions(+)\n\n--- a/include/linux/netdevice.h\n+++ b/include/linux/netdevice.h\n@@ -765,6 +765,16 @@ struct xps_map {\n #define XPS_MIN_MAP_ALLOC ((L1_CACHE_ALIGN(offsetof(struct xps_map, queues[1])) \\\n        - sizeof(struct xps_map)) / sizeof(u16))\n \n+#ifdef CONFIG_RFS_ACCEL\n+typedef int (*set_rfs_filter_callback_t)(struct net_device *dev,\n+                                     __be32 src,\n+                                     __be32 dst,\n+                                     __be16 sport,\n+                                     __be16 dport,\n+                                     u8 proto,\n+                                     u16 rxq_index,\n+                                     u32 action);\n+#endif\n /*\n  * This structure holds all XPS maps for device.  Maps are indexed by CPU.\n  */\n@@ -1452,6 +1462,9 @@ struct net_device_ops {\n \t\t\t\t\t\t     const struct sk_buff *skb,\n \t\t\t\t\t\t     u16 rxq_index,\n \t\t\t\t\t\t     u32 flow_id);\n+        int                     (*ndo_register_rfs_filter)(struct net_device *dev,\n+                                                              set_rfs_filter_callback_t set_filter);\n+        int                     (*ndo_get_default_vlan_tag)(struct net_device *net);\n #endif\n \tint\t\t\t(*ndo_add_slave)(struct net_device *dev,\n \t\t\t\t\t\t struct net_device *slave_dev,\n"
  },
  {
    "path": "target/linux/ipq40xx/patches-5.10/705-net-add-qualcomm-ar40xx-phy.patch",
    "content": "--- a/drivers/net/mdio/Kconfig\n+++ b/drivers/net/mdio/Kconfig\n@@ -27,6 +27,13 @@ config OF_MDIO\n \thelp\n \t  OpenFirmware MDIO bus (Ethernet PHY) accessors\n \n+config AR40XX_PHY\n+   tristate \"Driver for Qualcomm Atheros IPQ40XX switches\"\n+   depends on HAS_IOMEM && OF && OF_MDIO\n+   select SWCONFIG\n+   help\n+      This is the driver for Qualcomm Atheros IPQ40XX ESS switches.\n+\n if MDIO_BUS\n \n config MDIO_DEVRES\n--- a/drivers/net/mdio/Makefile\n+++ b/drivers/net/mdio/Makefile\n@@ -21,6 +21,8 @@ obj-$(CONFIG_MDIO_SUN4I)\t\t+= mdio-sun4i.\n obj-$(CONFIG_MDIO_THUNDER)\t\t+= mdio-thunder.o\n obj-$(CONFIG_MDIO_XGENE)\t\t+= mdio-xgene.o\n \n+obj-$(CONFIG_AR40XX_PHY)\t\t+= ar40xx.o\n+\n obj-$(CONFIG_MDIO_BUS_MUX)\t\t+= mdio-mux.o\n obj-$(CONFIG_MDIO_BUS_MUX_BCM_IPROC)\t+= mdio-mux-bcm-iproc.o\n obj-$(CONFIG_MDIO_BUS_MUX_GPIO)\t\t+= mdio-mux-gpio.o\n"
  },
  {
    "path": "target/linux/ipq40xx/patches-5.10/706-dt-bindings-net-add-QCA807x-PHY.patch",
    "content": "From c66863c1ba8995b61e6d727d78a241c734f5bb57 Mon Sep 17 00:00:00 2001\nFrom: Robert Marko <robert.marko@sartura.hr>\nDate: Thu, 1 Oct 2020 15:05:35 +0200\nSubject: [PATCH] dt-bindings: net: add QCA807x PHY\n\nAdd DT bindings for Qualcomm QCA807x PHY series.\n\nSigned-off-by: Robert Marko <robert.marko@sartura.hr>\n---\n include/dt-bindings/net/qcom-qca807x.h | 45 ++++++++++++++++++++++++++\n 1 file changed, 45 insertions(+)\n create mode 100644 include/dt-bindings/net/qcom-qca807x.h\n\n--- /dev/null\n+++ b/include/dt-bindings/net/qcom-qca807x.h\n@@ -0,0 +1,45 @@\n+/* SPDX-License-Identifier: GPL-2.0-or-later */\n+/*\n+ * Device Tree constants for the Qualcomm QCA807X PHYs\n+ */\n+\n+#ifndef _DT_BINDINGS_QCOM_QCA807X_H\n+#define _DT_BINDINGS_QCOM_QCA807X_H\n+\n+#define PSGMII_QSGMII_TX_DRIVER_140MV\t0\n+#define PSGMII_QSGMII_TX_DRIVER_160MV\t1\n+#define PSGMII_QSGMII_TX_DRIVER_180MV\t2\n+#define PSGMII_QSGMII_TX_DRIVER_200MV\t3\n+#define PSGMII_QSGMII_TX_DRIVER_220MV\t4\n+#define PSGMII_QSGMII_TX_DRIVER_240MV\t5\n+#define PSGMII_QSGMII_TX_DRIVER_260MV\t6\n+#define PSGMII_QSGMII_TX_DRIVER_280MV\t7\n+#define PSGMII_QSGMII_TX_DRIVER_300MV\t8\n+#define PSGMII_QSGMII_TX_DRIVER_320MV\t9\n+#define PSGMII_QSGMII_TX_DRIVER_400MV\t10\n+#define PSGMII_QSGMII_TX_DRIVER_500MV\t11\n+/* Default value */\n+#define PSGMII_QSGMII_TX_DRIVER_600MV\t12\n+\n+/* Full amplitude, full bias current */\n+#define QCA807X_CONTROL_DAC_FULL_VOLT_BIAS\t\t0\n+/* Amplitude follow DSP (amplitude is adjusted based on cable length), half bias current */\n+#define QCA807X_CONTROL_DAC_DSP_VOLT_HALF_BIAS\t\t1\n+/* Full amplitude, bias current follow DSP (bias current is adjusted based on cable length) */\n+#define QCA807X_CONTROL_DAC_FULL_VOLT_DSP_BIAS\t\t2\n+/* Both amplitude and bias current follow DSP */\n+#define QCA807X_CONTROL_DAC_DSP_VOLT_BIAS\t\t3\n+/* Full amplitude, half bias current */\n+#define QCA807X_CONTROL_DAC_FULL_VOLT_HALF_BIAS\t\t4\n+/* Amplitude follow DSP setting; 1/4 bias current when cable<10m,\n+ * otherwise half bias current\n+ */\n+#define QCA807X_CONTROL_DAC_DSP_VOLT_QUARTER_BIAS\t5\n+/* Full amplitude; same bias current setting with “010” and “011”,\n+ * but half more bias is reduced when cable <10m\n+ */\n+#define QCA807X_CONTROL_DAC_FULL_VOLT_HALF_BIAS_SHORT\t6\n+/* Amplitude follow DSP; same bias current setting with “110”, default value */\n+#define QCA807X_CONTROL_DAC_DSP_VOLT_HALF_BIAS_SHORT\t7\n+\n+#endif\n"
  },
  {
    "path": "target/linux/ipq40xx/patches-5.10/707-net-phy-Add-Qualcom-QCA807x-driver.patch",
    "content": "From f825cdc8bfde7616a14e2163f16303a8973031d2 Mon Sep 17 00:00:00 2001\nFrom: Robert Marko <robert.marko@sartura.hr>\nDate: Wed, 7 Oct 2020 17:38:48 +0200\nSubject: [PATCH] net: phy: Add Qualcom QCA807x driver\n\nThis adds driver for the Qualcomm QCA8072 and QCA8075 PHY-s.\n\nThey are 2 or 5 port IEEE 802.3 clause 22 compliant 10BASE-Te, 100BASE-TX and 1000BASE-T PHY-s.\n\nThey feature 2 SerDes, one for PSGMII or QSGMII connection with MAC, while second one is SGMII for connection to MAC or fiber.\n\nBoth models have a combo port that supports 1000BASE-X and 100BASE-FX fiber.\n\nEach PHY inside of QCA807x series has 4 digitally controlled output only pins that natively drive LED-s.\nBut some vendors used these to driver generic LED-s controlled by userspace,\nso lets enable registering each PHY as GPIO controller and add driver for it.\n\nThese are commonly used in Qualcomm IPQ40xx, IPQ60xx and IPQ807x boards.\n\nSigned-off-by: Robert Marko <robert.marko@sartura.hr>\n---\n drivers/net/phy/Kconfig  | 6 ++++++\n drivers/net/phy/Makefile | 1 +\n 2 files changed, 7 insertions(+)\n\n--- a/drivers/net/phy/Kconfig\n+++ b/drivers/net/phy/Kconfig\n@@ -320,6 +320,12 @@ config AT803X_PHY\n \t  Currently supports the AR8030, AR8031, AR8033, AR8035 and internal\n \t  QCA8337(Internal qca8k PHY) model\n \n+config QCA807X_PHY\n+\ttristate \"Qualcomm QCA807X PHYs\"\n+\tdepends on OF_MDIO\n+\thelp\n+\t  Currently supports the QCA8072 and QCA8075 models.\n+\n config QSEMI_PHY\n \ttristate \"Quality Semiconductor PHYs\"\n \thelp\n--- a/drivers/net/phy/Makefile\n+++ b/drivers/net/phy/Makefile\n@@ -86,6 +86,7 @@ obj-$(CONFIG_MICROSEMI_PHY)\t+= mscc/\n obj-$(CONFIG_NATIONAL_PHY)\t+= national.o\n obj-$(CONFIG_NXP_TJA11XX_PHY)\t+= nxp-tja11xx.o\n obj-$(CONFIG_QSEMI_PHY)\t\t+= qsemi.o\n+obj-$(CONFIG_QCA807X_PHY)\t\t+= qca807x.o\n obj-$(CONFIG_REALTEK_PHY)\t+= realtek.o\n obj-$(CONFIG_RENESAS_PHY)\t+= uPD60620.o\n obj-$(CONFIG_ROCKCHIP_PHY)\t+= rockchip.o\n"
  },
  {
    "path": "target/linux/ipq40xx/patches-5.10/708-arm-dts-ipq4019-QCA807x-properties.patch",
    "content": "From e0fa88eaa3c176b71e563da68949ac2ab45aaa61 Mon Sep 17 00:00:00 2001\nFrom: Robert Marko <robert.marko@sartura.hr>\nDate: Fri, 2 Oct 2020 10:43:26 +0200\nSubject: [PATCH] arm: dts: ipq4019: QCA807x properties\n\nThis adds necessary DT properties for QCA807x PHY-s to IPQ4019 DTSI.\n\nSigned-off-by: Robert Marko <robert.marko@sartura.hr>\n---\n arch/arm/boot/dts/qcom-ipq4019.dtsi | 18 ++++++++++++++++++\n 1 file changed, 18 insertions(+)\n\n--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi\n+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi\n@@ -8,6 +8,7 @@\n #include <dt-bindings/clock/qcom,gcc-ipq4019.h>\n #include <dt-bindings/interrupt-controller/arm-gic.h>\n #include <dt-bindings/interrupt-controller/irq.h>\n+#include <dt-bindings/net/qcom-qca807x.h>\n \n / {\n \t#address-cells = <1>;\n@@ -598,22 +599,39 @@\n \n \t\t\tethphy0: ethernet-phy@0 {\n \t\t\t\treg = <0>;\n+\n+\t\t\t\tqcom,control-dac = <QCA807X_CONTROL_DAC_DSP_VOLT_QUARTER_BIAS>;\n \t\t\t};\n \n \t\t\tethphy1: ethernet-phy@1 {\n \t\t\t\treg = <1>;\n+\n+\t\t\t\tqcom,control-dac = <QCA807X_CONTROL_DAC_DSP_VOLT_QUARTER_BIAS>;\n \t\t\t};\n \n \t\t\tethphy2: ethernet-phy@2 {\n \t\t\t\treg = <2>;\n+\n+\t\t\t\tqcom,control-dac = <QCA807X_CONTROL_DAC_DSP_VOLT_QUARTER_BIAS>;\n \t\t\t};\n \n \t\t\tethphy3: ethernet-phy@3 {\n \t\t\t\treg = <3>;\n+\n+\t\t\t\tqcom,control-dac = <QCA807X_CONTROL_DAC_DSP_VOLT_QUARTER_BIAS>;\n \t\t\t};\n \n \t\t\tethphy4: ethernet-phy@4 {\n \t\t\t\treg = <4>;\n+\n+\t\t\t\tqcom,control-dac = <QCA807X_CONTROL_DAC_DSP_VOLT_QUARTER_BIAS>;\n+\t\t\t};\n+\n+\t\t\tpsgmiiphy: psgmii-phy@5 {\n+\t\t\t\treg = <5>;\n+\n+\t\t\t\tqcom,tx-driver-strength = <PSGMII_QSGMII_TX_DRIVER_300MV>;\n+\t\t\t\tqcom,psgmii-az;\n \t\t\t};\n \t\t};\n \n"
  },
  {
    "path": "target/linux/ipq40xx/patches-5.10/710-net-add-qualcomm-essedma-ethernet-driver.patch",
    "content": "From 12e9319da1adacac92930c899c99f0e1970cac11 Mon Sep 17 00:00:00 2001\nFrom: Christian Lamparter <chunkeey@googlemail.com>\nDate: Thu, 19 Jan 2017 02:01:31 +0100\nSubject: [PATCH 33/38] NET: add qualcomm essedma ethernet driver\n\nSigned-off-by: Christian Lamparter <chunkeey@gmail.com>\n---\n drivers/net/ethernet/qualcomm/Kconfig  | 9 +++++++++\n drivers/net/ethernet/qualcomm/Makefile | 1 +\n 2 files changed, 10 insertions(+)\n\n--- a/drivers/net/ethernet/qualcomm/Kconfig\n+++ b/drivers/net/ethernet/qualcomm/Kconfig\n@@ -62,4 +62,14 @@ config QCOM_EMAC\n \n source \"drivers/net/ethernet/qualcomm/rmnet/Kconfig\"\n \n+config ESSEDMA\n+\ttristate \"Qualcomm Atheros ESS Edma support\"\n+\tdepends on OF_MDIO\n+\thelp\n+\t  This driver supports ethernet edma adapter.\n+\t  Say Y to build this driver.\n+\n+\t  To compile this driver as a module, choose M here. The module\n+\t  will be called essedma.ko.\n+\n endif # NET_VENDOR_QUALCOMM\n--- a/drivers/net/ethernet/qualcomm/Makefile\n+++ b/drivers/net/ethernet/qualcomm/Makefile\n@@ -10,5 +10,6 @@ obj-$(CONFIG_QCA7000_UART) += qcauart.o\n qcauart-objs := qca_uart.o\n \n obj-y += emac/\n+obj-$(CONFIG_ESSEDMA) += essedma/\n \n obj-$(CONFIG_RMNET) += rmnet/\n"
  },
  {
    "path": "target/linux/ipq40xx/patches-5.10/711-dts-ipq4019-add-ethernet-essedma-node.patch",
    "content": "From c611d3780fa101662a822d10acf8feb04ca97409 Mon Sep 17 00:00:00 2001\nFrom: Christian Lamparter <chunkeey@gmail.com>\nDate: Sun, 20 Nov 2016 01:01:10 +0100\nSubject: [PATCH] dts: ipq4019: add ethernet essedma node\n\nThis patch adds the device-tree node for the ethernet\ninterfaces.\n\nNote: The driver isn't anywhere close to be upstream,\nso the info might change.\n\nSigned-off-by: Christian Lamparter <chunkeey@gmail.com>\n---\n arch/arm/boot/dts/qcom-ipq4019.dtsi | 60 +++++++++++++++++++++++++++++++++++++\n 1 file changed, 60 insertions(+)\n\n--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi\n+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi\n@@ -39,6 +39,8 @@\n \t\tspi1 = &blsp1_spi2;\n \t\ti2c0 = &blsp1_i2c3;\n \t\ti2c1 = &blsp1_i2c4;\n+\t\tethernet0 = &gmac0;\n+\t\tethernet1 = &gmac1;\n \t};\n \n \tcpus {\n@@ -658,6 +660,64 @@\n \t\t\tstatus = \"disabled\";\n \t\t};\n \n+\t\tedma@c080000 {\n+\t\t\tcompatible = \"qcom,ess-edma\";\n+\t\t\treg = <0xc080000 0x8000>;\n+\t\t\tqcom,page-mode = <0>;\n+\t\t\tqcom,rx_head_buf_size = <1540>;\n+\t\t\tqcom,mdio_supported;\n+\t\t\tqcom,poll_required = <1>;\n+\t\t\tqcom,num_gmac = <2>;\n+\t\t\tinterrupts = <0  65 IRQ_TYPE_EDGE_RISING\n+\t\t\t\t      0  66 IRQ_TYPE_EDGE_RISING\n+\t\t\t\t      0  67 IRQ_TYPE_EDGE_RISING\n+\t\t\t\t      0  68 IRQ_TYPE_EDGE_RISING\n+\t\t\t\t      0  69 IRQ_TYPE_EDGE_RISING\n+\t\t\t\t      0  70 IRQ_TYPE_EDGE_RISING\n+\t\t\t\t      0  71 IRQ_TYPE_EDGE_RISING\n+\t\t\t\t      0  72 IRQ_TYPE_EDGE_RISING\n+\t\t\t\t      0  73 IRQ_TYPE_EDGE_RISING\n+\t\t\t\t      0  74 IRQ_TYPE_EDGE_RISING\n+\t\t\t\t      0  75 IRQ_TYPE_EDGE_RISING\n+\t\t\t\t      0  76 IRQ_TYPE_EDGE_RISING\n+\t\t\t\t      0  77 IRQ_TYPE_EDGE_RISING\n+\t\t\t\t      0  78 IRQ_TYPE_EDGE_RISING\n+\t\t\t\t      0  79 IRQ_TYPE_EDGE_RISING\n+\t\t\t\t      0  80 IRQ_TYPE_EDGE_RISING\n+\t\t\t\t      0 240 IRQ_TYPE_EDGE_RISING\n+\t\t\t\t      0 241 IRQ_TYPE_EDGE_RISING\n+\t\t\t\t      0 242 IRQ_TYPE_EDGE_RISING\n+\t\t\t\t      0 243 IRQ_TYPE_EDGE_RISING\n+\t\t\t\t      0 244 IRQ_TYPE_EDGE_RISING\n+\t\t\t\t      0 245 IRQ_TYPE_EDGE_RISING\n+\t\t\t\t      0 246 IRQ_TYPE_EDGE_RISING\n+\t\t\t\t      0 247 IRQ_TYPE_EDGE_RISING\n+\t\t\t\t      0 248 IRQ_TYPE_EDGE_RISING\n+\t\t\t\t      0 249 IRQ_TYPE_EDGE_RISING\n+\t\t\t\t      0 250 IRQ_TYPE_EDGE_RISING\n+\t\t\t\t      0 251 IRQ_TYPE_EDGE_RISING\n+\t\t\t\t      0 252 IRQ_TYPE_EDGE_RISING\n+\t\t\t\t      0 253 IRQ_TYPE_EDGE_RISING\n+\t\t\t\t      0 254 IRQ_TYPE_EDGE_RISING\n+\t\t\t\t      0 255 IRQ_TYPE_EDGE_RISING>;\n+\n+\t\t\tstatus = \"disabled\";\n+\n+\t\t\tgmac0: gmac0 {\n+\t\t\t\tlocal-mac-address = [00 00 00 00 00 00];\n+\t\t\t\tvlan_tag = <1 0x1f>;\n+\t\t\t};\n+\n+\t\t\tgmac1: gmac1 {\n+\t\t\t\tlocal-mac-address = [00 00 00 00 00 00];\n+\t\t\t\tqcom,phy_mdio_addr = <4>;\n+\t\t\t\tqcom,poll_required = <1>;\n+\t\t\t\tqcom,forced_speed = <1000>;\n+\t\t\t\tqcom,forced_duplex = <1>;\n+\t\t\t\tvlan_tag = <2 0x20>;\n+\t\t\t};\n+\t\t};\n+\n \t\tusb3_ss_phy: ssphy@9a000 {\n \t\t\tcompatible = \"qcom,usb-ss-ipq4019-phy\";\n \t\t\t#phy-cells = <0>;\n"
  },
  {
    "path": "target/linux/ipq40xx/patches-5.10/850-soc-add-qualcomm-syscon.patch",
    "content": "From: Christian Lamparter <chunkeey@googlemail.com>\nSubject: SoC: add qualcomm syscon\n--- a/drivers/soc/qcom/Makefile\n+++ b/drivers/soc/qcom/Makefile\n@@ -21,6 +21,7 @@ obj-$(CONFIG_QCOM_SMP2P)\t+= smp2p.o\n obj-$(CONFIG_QCOM_SMSM)\t+= smsm.o\n obj-$(CONFIG_QCOM_SOCINFO)\t+= socinfo.o\n obj-$(CONFIG_QCOM_WCNSS_CTRL) += wcnss_ctrl.o\n+obj-$(CONFIG_QCOM_TCSR)\t += qcom_tcsr.o\n obj-$(CONFIG_QCOM_APR) += apr.o\n obj-$(CONFIG_QCOM_LLCC) += llcc-qcom.o\n obj-$(CONFIG_QCOM_RPMHPD) += rpmhpd.o\n--- a/drivers/soc/qcom/Kconfig\n+++ b/drivers/soc/qcom/Kconfig\n@@ -189,6 +189,13 @@ config QCOM_SOCINFO\n \t Say yes here to support the Qualcomm socinfo driver, providing\n \t information about the SoC to user space.\n \n+config QCOM_TCSR\n+\ttristate \"QCOM Top Control and Status Registers\"\n+\tdepends on ARCH_QCOM\n+\thelp\n+\t  Say y here to enable TCSR support.  The TCSR provides control\n+\t  functions for various peripherals.\n+\n config QCOM_WCNSS_CTRL\n \ttristate \"Qualcomm WCNSS control driver\"\n \tdepends on ARCH_QCOM || COMPILE_TEST\n--- /dev/null\n+++ b/drivers/soc/qcom/qcom_tcsr.c\n@@ -0,0 +1,98 @@\n+/*\n+ * Copyright (c) 2014, The Linux foundation. All rights reserved.\n+ *\n+ * This program is free software; you can redistribute it and/or modify\n+ * it under the terms of the GNU General Public License rev 2 and\n+ * only rev 2 as published by the free Software foundation.\n+ *\n+ * This program is distributed in the hope that it will be useful,\n+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\n+ * MERCHANTABILITY or fITNESS fOR A PARTICULAR PURPOSE.  See the\n+ * GNU General Public License for more details.\n+ */\n+\n+#include <linux/clk.h>\n+#include <linux/err.h>\n+#include <linux/io.h>\n+#include <linux/module.h>\n+#include <linux/of.h>\n+#include <linux/of_platform.h>\n+#include <linux/platform_device.h>\n+\n+#define TCSR_USB_PORT_SEL\t0xb0\n+#define TCSR_USB_HSPHY_CONFIG\t0xC\n+\n+#define TCSR_ESS_INTERFACE_SEL_OFFSET   0x0\n+#define TCSR_ESS_INTERFACE_SEL_MASK     0xf\n+\n+#define TCSR_WIFI0_GLB_CFG_OFFSET\t0x0\n+#define TCSR_WIFI1_GLB_CFG_OFFSET\t0x4\n+#define TCSR_PNOC_SNOC_MEMTYPE_M0_M2\t0x4\n+\n+static int tcsr_probe(struct platform_device *pdev)\n+{\n+\tstruct resource *res;\n+\tconst struct device_node *node = pdev->dev.of_node;\n+\tvoid __iomem *base;\n+\tu32 val;\n+\n+\tres = platform_get_resource(pdev, IORESOURCE_MEM, 0);\n+\tbase = devm_ioremap_resource(&pdev->dev, res);\n+\tif (IS_ERR(base))\n+\t\treturn PTR_ERR(base);\n+\n+\tif (!of_property_read_u32(node, \"qcom,usb-ctrl-select\", &val)) {\n+\t\tdev_err(&pdev->dev, \"setting usb port select = %d\\n\", val);\n+\t\twritel(val, base + TCSR_USB_PORT_SEL);\n+\t}\n+\n+\tif (!of_property_read_u32(node, \"qcom,usb-hsphy-mode-select\", &val)) {\n+\t\tdev_info(&pdev->dev, \"setting usb hs phy mode select = %x\\n\", val);\n+\t\twritel(val, base + TCSR_USB_HSPHY_CONFIG);\n+\t}\n+\n+\tif (!of_property_read_u32(node, \"qcom,ess-interface-select\", &val)) {\n+\t\tu32 tmp = 0;\n+\t\tdev_info(&pdev->dev, \"setting ess interface select = %x\\n\", val);\n+\t\ttmp = readl(base + TCSR_ESS_INTERFACE_SEL_OFFSET);\n+\t\ttmp = tmp & (~TCSR_ESS_INTERFACE_SEL_MASK);\n+\t\ttmp = tmp | (val&TCSR_ESS_INTERFACE_SEL_MASK);\n+\t\twritel(tmp, base + TCSR_ESS_INTERFACE_SEL_OFFSET);\n+        }\n+\n+\tif (!of_property_read_u32(node, \"qcom,wifi_glb_cfg\", &val)) {\n+\t\tdev_info(&pdev->dev, \"setting wifi_glb_cfg = %x\\n\", val);\n+\t\twritel(val, base + TCSR_WIFI0_GLB_CFG_OFFSET);\n+\t\twritel(val, base + TCSR_WIFI1_GLB_CFG_OFFSET);\n+\t}\n+\n+\tif (!of_property_read_u32(node, \"qcom,wifi_noc_memtype_m0_m2\", &val)) {\n+\t\tdev_info(&pdev->dev,\n+\t\t\t\"setting wifi_noc_memtype_m0_m2 = %x\\n\", val);\n+\t\twritel(val, base + TCSR_PNOC_SNOC_MEMTYPE_M0_M2);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static const struct of_device_id tcsr_dt_match[] = {\n+\t{ .compatible = \"qcom,tcsr\", },\n+\t{ },\n+};\n+\n+MODULE_DEVICE_TABLE(of, tcsr_dt_match);\n+\n+static struct platform_driver tcsr_driver = {\n+\t.driver = {\n+\t\t.name\t\t= \"tcsr\",\n+\t\t.owner\t\t= THIS_MODULE,\n+\t\t.of_match_table\t= tcsr_dt_match,\n+\t},\n+\t.probe = tcsr_probe,\n+};\n+\n+module_platform_driver(tcsr_driver);\n+\n+MODULE_AUTHOR(\"Andy Gross <agross@codeaurora.org>\");\n+MODULE_DESCRIPTION(\"QCOM TCSR driver\");\n+MODULE_LICENSE(\"GPL v2\");\n--- /dev/null\n+++ b/include/dt-bindings/soc/qcom,tcsr.h\n@@ -0,0 +1,48 @@\n+/* Copyright (c) 2014, The Linux Foundation. All rights reserved.\n+ *\n+ * This program is free software; you can redistribute it and/or modify\n+ * it under the terms of the GNU General Public License version 2 and\n+ * only version 2 as published by the Free Software Foundation.\n+ *\n+ * This program is distributed in the hope that it will be useful,\n+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\n+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n+ * GNU General Public License for more details.\n+ */\n+#ifndef __DT_BINDINGS_QCOM_TCSR_H\n+#define __DT_BINDINGS_QCOM_TCSR_H\n+\n+#define TCSR_USB_SELECT_USB3_P0\t\t0x1\n+#define TCSR_USB_SELECT_USB3_P1\t\t0x2\n+#define TCSR_USB_SELECT_USB3_DUAL\t0x3\n+\n+/* IPQ40xx HS PHY Mode Select */\n+#define TCSR_USB_HSPHY_HOST_MODE\t0x00E700E7\n+#define TCSR_USB_HSPHY_DEVICE_MODE\t0x00C700E7\n+\n+/* IPQ40xx ess interface mode select */\n+#define TCSR_ESS_PSGMII              0\n+#define TCSR_ESS_PSGMII_RGMII5       1\n+#define TCSR_ESS_PSGMII_RMII0        2\n+#define TCSR_ESS_PSGMII_RMII1        4\n+#define TCSR_ESS_PSGMII_RMII0_RMII1  6\n+#define TCSR_ESS_PSGMII_RGMII4       9\n+\n+/*\n+ * IPQ40xx WiFi Global Config\n+ * Bit 30:AXID_EN\n+ * Enable AXI master bus Axid translating to confirm all txn submitted by order\n+ * Bit 24: Use locally generated socslv_wxi_bvalid\n+ * 1:  use locally generate socslv_wxi_bvalid for performance.\n+ * 0:  use SNOC socslv_wxi_bvalid.\n+ */\n+#define TCSR_WIFI_GLB_CFG\t\t0x41000000\n+\n+/* IPQ40xx MEM_TYPE_SEL_M0_M2 Select Bit 26:24 - 2 NORMAL */\n+#define TCSR_WIFI_NOC_MEMTYPE_M0_M2\t0x02222222\n+\n+/* TCSR A/B REG */\n+#define IPQ806X_TCSR_REG_A_ADM_CRCI_MUX_SEL     0\n+#define IPQ806X_TCSR_REG_B_ADM_CRCI_MUX_SEL     1\n+\n+#endif\n"
  },
  {
    "path": "target/linux/ipq40xx/patches-5.10/900-dts-ipq4019-ap-dk01.1.patch",
    "content": "--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi\n+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi\n@@ -15,6 +15,7 @@\n  */\n \n #include \"qcom-ipq4019.dtsi\"\n+#include <dt-bindings/soc/qcom,tcsr.h>\n \n / {\n \tmodel = \"Qualcomm Technologies, Inc. IPQ4019/AP-DK01.1\";\n@@ -29,6 +30,32 @@\n \t};\n \n \tsoc {\n+\t\ttcsr@194b000 {\n+\t\t\t/* select hostmode */\n+\t\t\tcompatible = \"qcom,tcsr\";\n+\t\t\treg = <0x194b000 0x100>;\n+\t\t\tqcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\n+\t\tess_tcsr@1953000 {\n+\t\t\tcompatible = \"qcom,tcsr\";\n+\t\t\treg = <0x1953000 0x1000>;\n+\t\t\tqcom,ess-interface-select = <TCSR_ESS_PSGMII>;\n+\t\t};\n+\n+\t\ttcsr@1949000 {\n+\t\t\tcompatible = \"qcom,tcsr\";\n+\t\t\treg = <0x1949000 0x100>;\n+\t\t\tqcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;\n+\t\t};\n+\n+\t\ttcsr@1957000 {\n+\t\t\tcompatible = \"qcom,tcsr\";\n+\t\t\treg = <0x1957000 0x100>;\n+\t\t\tqcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;\n+\t\t};\n+\n \t\trng@22000 {\n \t\t\tstatus = \"ok\";\n \t\t};\n@@ -74,14 +101,6 @@\n \t\t\tpinctrl-names = \"default\";\n \t\t\tstatus = \"ok\";\n \t\t\tcs-gpios = <&tlmm 54 0>;\n-\n-\t\t\tmx25l25635e@0 {\n-\t\t\t\t#address-cells = <1>;\n-\t\t\t\t#size-cells = <1>;\n-\t\t\t\treg = <0>;\n-\t\t\t\tcompatible = \"mx25l25635e\";\n-\t\t\t\tspi-max-frequency = <24000000>;\n-\t\t\t};\n \t\t};\n \n \t\tserial@78af000 {\n@@ -109,5 +128,41 @@\n \t\twifi@a800000 {\n \t\t\tstatus = \"ok\";\n \t\t};\n+\n+\t\tmdio@90000 {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\n+\t\tess-switch@c000000 {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\n+\t\tess-psgmii@98000 {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\n+\t\tedma@c080000 {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\n+\t\tusb3_ss_phy: ssphy@9a000 {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\n+\t\tusb3_hs_phy: hsphy@a6000 {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\n+\t\tusb3: usb3@8af8800 {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\n+\t\tusb2_hs_phy: hsphy@a8000 {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\n+\t\tusb2: usb2@60f8800 {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n \t};\n };\n--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts\n+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts\n@@ -18,5 +18,73 @@\n \n / {\n \tmodel = \"Qualcomm Technologies, Inc. IPQ40xx/AP-DK01.1-C1\";\n+\tcompatible = \"qcom,ap-dk01.1-c1\", \"qcom,ap-dk01.2-c1\";\n \n+\tmemory {\n+\t\tdevice_type = \"memory\";\n+\t\treg = <0x80000000 0x10000000>;\n+\t};\n+};\n+\n+&blsp1_spi1 {\n+\tmx25l25635f@0 {\n+\t\tcompatible = \"mx25l25635f\", \"jedec,spi-nor\";\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <1>;\n+\t\treg = <0>;\n+\t\tspi-max-frequency = <24000000>;\n+\n+\t\tSBL1@0 {\n+\t\t\tlabel = \"SBL1\";\n+\t\t\treg = <0x0 0x40000>;\n+\t\t\tread-only;\n+\t\t};\n+\t\tMIBIB@40000 {\n+\t\t\tlabel = \"MIBIB\";\n+\t\t\treg = <0x40000 0x20000>;\n+\t\t\tread-only;\n+\t\t};\n+\t\tQSEE@60000 {\n+\t\t\tlabel = \"QSEE\";\n+\t\t\treg = <0x60000 0x60000>;\n+\t\t\tread-only;\n+\t\t};\n+\t\tCDT@c0000 {\n+\t\t\tlabel = \"CDT\";\n+\t\t\treg = <0xc0000 0x10000>;\n+\t\t\tread-only;\n+\t\t};\n+\t\tDDRPARAMS@d0000 {\n+\t\t\tlabel = \"DDRPARAMS\";\n+\t\t\treg = <0xd0000 0x10000>;\n+\t\t\tread-only;\n+\t\t};\n+\t\tAPPSBLENV@e0000 {\n+\t\t\tlabel = \"APPSBLENV\";\n+\t\t\treg = <0xe0000 0x10000>;\n+\t\t\tread-only;\n+\t\t};\n+\t\tAPPSBL@f0000 {\n+\t\t\tlabel = \"APPSBL\";\n+\t\t\treg = <0xf0000 0x80000>;\n+\t\t\tread-only;\n+\t\t};\n+\t\tART@170000 {\n+\t\t\tlabel = \"ART\";\n+\t\t\treg = <0x170000 0x10000>;\n+\t\t\tread-only;\n+\t\t};\n+\t\tkernel@180000 {\n+\t\t\tlabel = \"kernel\";\n+\t\t\treg = <0x180000 0x400000>;\n+\t\t};\n+\t\trootfs@580000 {\n+\t\t\tlabel = \"rootfs\";\n+\t\t\treg = <0x580000 0x1600000>;\n+\t\t};\n+\t\tfirmware@180000 {\n+\t\t\tlabel = \"firmware\";\n+\t\t\treg = <0x180000 0x1a00000>;\n+\t\t};\n+\t};\n };\n"
  },
  {
    "path": "target/linux/ipq40xx/patches-5.10/901-arm-boot-add-dts-files.patch",
    "content": "From a10fab12a927e60b7141a602e740d70cb4d09e4a Mon Sep 17 00:00:00 2001\nFrom: John Crispin <john@phrozen.org>\nDate: Thu, 9 Mar 2017 11:03:18 +0100\nSubject: [PATCH] arm: boot: add dts files\n\nSigned-off-by: John Crispin <john@phrozen.org>\n---\n arch/arm/boot/dts/Makefile | 23 +++++++++++++++++++++++\n 1 file changed, 23 insertions(+)\n\n--- a/arch/arm/boot/dts/Makefile\n+++ b/arch/arm/boot/dts/Makefile\n@@ -903,11 +903,76 @@ dtb-$(CONFIG_ARCH_QCOM) += \\\n \tqcom-apq8074-dragonboard.dtb \\\n \tqcom-apq8084-ifc6540.dtb \\\n \tqcom-apq8084-mtp.dtb \\\n+\tqcom-ipq4018-a42.dtb \\\n+\tqcom-ipq4018-ap120c-ac.dtb \\\n+\tqcom-ipq4018-dap-2610.dtb \\\n+\tqcom-ipq4018-cs-w3-wd1200g-eup.dtb \\\n+\tqcom-ipq4018-magic-2-wifi-next.dtb \\\n+\tqcom-ipq4018-ea6350v3.dtb \\\n+\tqcom-ipq4018-eap1300.dtb \\\n+\tqcom-ipq4018-ecw5211.dtb \\\n+\tqcom-ipq4018-emd1.dtb \\\n+\tqcom-ipq4018-emr3500.dtb \\\n+\tqcom-ipq4018-ens620ext.dtb \\\n+\tqcom-ipq4018-ex6100v2.dtb \\\n+\tqcom-ipq4018-ex6150v2.dtb \\\n+\tqcom-ipq4018-fritzbox-4040.dtb \\\n+\tqcom-ipq4018-gl-ap1300.dtb \\\n+\tqcom-ipq4018-jalapeno.dtb \\\n+\tqcom-ipq4018-meshpoint-one.dtb \\\n+\tqcom-ipq4018-cap-ac.dtb \\\n+\tqcom-ipq4018-hap-ac2.dtb \\\n+\tqcom-ipq4018-sxtsq-5-ac.dtb \\\n+\tqcom-ipq4018-nbg6617.dtb \\\n+\tqcom-ipq4019-oap100.dtb \\\n+\tqcom-ipq4018-pa1200.dtb \\\n+\tqcom-ipq4018-rt-ac58u.dtb \\\n+\tqcom-ipq4018-rutx10.dtb \\\n+\tqcom-ipq4018-wac510.dtb \\\n+\tqcom-ipq4018-wre6606.dtb \\\n+\tqcom-ipq4018-wrtq-329acn.dtb \\\n \tqcom-ipq4019-ap.dk01.1-c1.dtb \\\n \tqcom-ipq4019-ap.dk04.1-c1.dtb \\\n \tqcom-ipq4019-ap.dk04.1-c3.dtb \\\n \tqcom-ipq4019-ap.dk07.1-c1.dtb \\\n \tqcom-ipq4019-ap.dk07.1-c2.dtb \\\n+\tqcom-ipq4019-a62.dtb \\\n+\tqcom-ipq4019-cm520-79f.dtb \\\n+\tqcom-ipq4019-e2600ac-c1.dtb \\\n+\tqcom-ipq4019-e2600ac-c2.dtb \\\n+\tqcom-ipq4019-ea8300.dtb \\\n+\tqcom-ipq4019-eap2200.dtb \\\n+\tqcom-ipq4019-fritzbox-7530.dtb \\\n+\tqcom-ipq4019-fritzrepeater-1200.dtb \\\n+\tqcom-ipq4019-fritzrepeater-3000.dtb \\\n+\tqcom-ipq4019-habanero-dvk.dtb \\\n+\tqcom-ipq4019-hap-ac3.dtb \\\n+\tqcom-ipq4019-map-ac2200.dtb \\\n+\tqcom-ipq4019-lhgg-60ad.dtb \\\n+\tqcom-ipq4019-mf286d.dtb \\\n+\tqcom-ipq4019-mr8300.dtb \\\n+\tqcom-ipq4019-pa2200.dtb \\\n+\tqcom-ipq4019-r619ac-64m.dtb \\\n+\tqcom-ipq4019-r619ac-128m.dtb \\\n+\tqcom-ipq4019-rbr50.dtb \\\n+\tqcom-ipq4019-rbs50.dtb \\\n+\tqcom-ipq4019-rt-ac42u.dtb \\\n+\tqcom-ipq4019-rtl30vw.dtb \\\n+\tqcom-ipq4019-srr60.dtb \\\n+\tqcom-ipq4019-srs60.dtb \\\n+\tqcom-ipq4019-u4019-32m.dtb \\\n+\tqcom-ipq4019-wifi.dtb \\\n+\tqcom-ipq4019-wpj419.dtb \\\n+\tqcom-ipq4019-wtr-m2133hp.dtb \\\n+\tqcom-ipq4019-x1pro.dtb \\\n+\tqcom-ipq4028-wpj428.dtb \\\n+\tqcom-ipq4029-ap-303.dtb \\\n+\tqcom-ipq4029-ap-303h.dtb \\\n+\tqcom-ipq4029-ap-365.dtb \\\n+\tqcom-ipq4029-gl-b1300.dtb \\\n+\tqcom-ipq4019-gl-b2200.dtb \\\n+\tqcom-ipq4029-gl-s1300.dtb \\\n+\tqcom-ipq4029-mr33.dtb \\\n \tqcom-ipq8064-ap148.dtb \\\n \tqcom-ipq8064-rb3011.dtb \\\n \tqcom-msm8660-surf.dtb \\\n"
  },
  {
    "path": "target/linux/ipq40xx/patches-5.10/902-dts-ipq4019-ap-dk04.1.patch",
    "content": "--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi\n+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi\n@@ -17,53 +17,79 @@\n \t\tstdout-path = \"serial0:115200n8\";\n \t};\n \n-\tmemory {\n-\t\tdevice_type = \"memory\";\n-\t\treg = <0x80000000 0x10000000>; /* 256MB */\n-\t};\n-\n \tsoc {\n+\t\trng@22000 {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\n \t\tpinctrl@1000000 {\n \t\t\tserial_0_pins: serial0-pinmux {\n-\t\t\t\tpins = \"gpio16\", \"gpio17\";\n-\t\t\t\tfunction = \"blsp_uart0\";\n-\t\t\t\tbias-disable;\n+\t\t\t\tmux {\n+\t\t\t\t\tpins = \"gpio16\", \"gpio17\";\n+\t\t\t\t\tfunction = \"blsp_uart0\";\n+\t\t\t\t\tbias-disable;\n+\t\t\t\t};\n \t\t\t};\n \n \t\t\tserial_1_pins: serial1-pinmux {\n-\t\t\t\tpins = \"gpio8\", \"gpio9\",\n-\t\t\t\t\t\"gpio10\", \"gpio11\";\n-\t\t\t\tfunction = \"blsp_uart1\";\n-\t\t\t\tbias-disable;\n+\t\t\t\tmux {\n+\t\t\t\t\tpins = \"gpio8\", \"gpio9\";\n+\t\t\t\t\tfunction = \"blsp_uart1\";\n+\t\t\t\t\tbias-disable;\n+\t\t\t\t};\n \t\t\t};\n \n \t\t\tspi_0_pins: spi-0-pinmux {\n \t\t\t\tpinmux {\n \t\t\t\t\tfunction = \"blsp_spi0\";\n \t\t\t\t\tpins = \"gpio13\", \"gpio14\", \"gpio15\";\n-\t\t\t\t\tbias-disable;\n \t\t\t\t};\n \t\t\t\tpinmux_cs {\n \t\t\t\t\tfunction = \"gpio\";\n \t\t\t\t\tpins = \"gpio12\";\n+\t\t\t\t};\n+\t\t\t\tpinconf {\n+\t\t\t\t\tpins = \"gpio13\", \"gpio14\", \"gpio15\";\n+\t\t\t\t\tdrive-strength = <12>;\n+\t\t\t\t\tbias-disable;\n+\t\t\t\t};\n+\t\t\t\tpinconf_cs {\n+\t\t\t\t\tpins = \"gpio12\";\n+\t\t\t\t\tdrive-strength = <2>;\n \t\t\t\t\tbias-disable;\n \t\t\t\t\toutput-high;\n \t\t\t\t};\n \t\t\t};\n \n \t\t\ti2c_0_pins: i2c-0-pinmux {\n-\t\t\t\tpins = \"gpio20\", \"gpio21\";\n-\t\t\t\tfunction = \"blsp_i2c0\";\n-\t\t\t\tbias-disable;\n+\t\t\t\tpinmux {\n+\t\t\t\t\tfunction = \"blsp_i2c0\";\n+\t\t\t\t\tpins = \"gpio10\", \"gpio11\";\n+\t\t\t\t};\n+\t\t\t\tpinconf {\n+\t\t\t\t\tpins = \"gpio10\", \"gpio11\";\n+\t\t\t\t\tdrive-strength = <16>;\n+\t\t\t\t\tbias-disable;\n+\t\t\t\t};\n \t\t\t};\n \n \t\t\tnand_pins: nand-pins {\n-\t\t\t\tpins = \"gpio53\", \"gpio55\", \"gpio56\",\n-\t\t\t\t\t\"gpio57\", \"gpio58\", \"gpio59\",\n-\t\t\t\t\t\"gpio60\", \"gpio62\", \"gpio63\",\n-\t\t\t\t\t\"gpio64\", \"gpio65\", \"gpio66\",\n-\t\t\t\t\t\"gpio67\", \"gpio68\", \"gpio69\";\n-\t\t\t\tfunction = \"qpic\";\n+\t\t\t\tpullups {\n+\t\t\t\t\tpins = \"gpio52\", \"gpio53\", \"gpio58\",\n+\t\t\t\t\t\t\"gpio59\";\n+\t\t\t\t\tfunction = \"qpic\";\n+\t\t\t\t\tbias-pull-up;\n+\t\t\t\t};\n+\n+\t\t\t\tpulldowns {\n+\t\t\t\t\tpins = \"gpio54\", \"gpio55\", \"gpio56\",\n+\t\t\t\t\t\t\"gpio57\", \"gpio60\", \"gpio61\",\n+\t\t\t\t\t\t\"gpio62\", \"gpio63\", \"gpio64\",\n+\t\t\t\t\t\t\"gpio65\", \"gpio66\", \"gpio67\",\n+\t\t\t\t\t\t\"gpio68\", \"gpio69\";\n+\t\t\t\t\tfunction = \"qpic\";\n+\t\t\t\t\tbias-pull-down;\n+\t\t\t\t};\n \t\t\t};\n \t\t};\n \n@@ -89,11 +115,11 @@\n \t\t\tstatus = \"ok\";\n \t\t\tcs-gpios = <&tlmm 12 0>;\n \n-\t\t\tm25p80@0 {\n+\t\t\tmx25l25635e@0 {\n \t\t\t\t#address-cells = <1>;\n \t\t\t\t#size-cells = <1>;\n \t\t\t\treg = <0>;\n-\t\t\t\tcompatible = \"n25q128a11\";\n+\t\t\t\tcompatible = \"mx25l25635e\";\n \t\t\t\tspi-max-frequency = <24000000>;\n \t\t\t};\n \t\t};\n@@ -103,9 +129,48 @@\n \t\t\tperst-gpio = <&tlmm 38 0x1>;\n \t\t};\n \n+\t\ti2c0: i2c@78b7000 { /* BLSP1 QUP2 */\n+\t\t\tpinctrl-0 = <&i2c_0_pins>;\n+\t\t\tpinctrl-names = \"default\";\n+\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\n \t\tqpic-nand@79b0000 {\n \t\t\tpinctrl-0 = <&nand_pins>;\n \t\t\tpinctrl-names = \"default\";\n \t\t};\n+\n+\t\tusb3_ss_phy: ssphy@9a000 {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\n+\t\tusb3_hs_phy: hsphy@a6000 {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\n+\t\tusb3: usb3@8af8800 {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\n+\t\tusb2_hs_phy: hsphy@a8000 {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\n+\t\tusb2: usb2@60f8800 {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\n+\t\tcryptobam: dma@8e04000 {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\n+\t\tcrypto@8e3a000 {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\n+\t\twatchdog@b017000 {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n \t};\n };\n"
  },
  {
    "path": "target/linux/ipq40xx/patches-5.15/104-clk-fix-apss-cpu-overclocking.patch",
    "content": "From f2b87dc1028b710ec8ce25808b9d21f92b376184 Mon Sep 17 00:00:00 2001\nFrom: Christian Lamparter <chunkeey@googlemail.com>\nDate: Sun, 11 Mar 2018 14:41:31 +0100\nSubject: [PATCH 2/2] clk: fix apss cpu overclocking\n\nThere's an interaction issue between the clk changes:\"\nclk: qcom: ipq4019: Add the apss cpu pll divider clock node\nclk: qcom: ipq4019: remove fixed clocks and add pll clocks\n\" and the cpufreq-dt.\n\ncpufreq-dt is now spamming the kernel-log with the following:\n\n[ 1099.190658] cpu cpu0: dev_pm_opp_set_rate: failed to find current OPP\nfor freq 761142857 (-34)\n\nThis only happens on certain devices like the Compex WPJ428\nand AVM FritzBox!4040. However, other devices like the Asus\nRT-AC58U and Meraki MR33 work just fine.\n\nThe issue stem from the fact that all higher CPU-Clocks\nare achieved by switching the clock-parent to the P_DDRPLLAPSS\n(ddrpllapss). Which is set by Qualcomm's proprietary bootcode\nas part of the DDR calibration.\n\nFor example, the FB4040 uses 256 MiB Nanya NT5CC128M16IP clocked\nat round 533 MHz (ddrpllsdcc = 190285714 Hz).\n\nwhereas the 128 MiB Nanya NT5CC64M16GP-DI in the ASUS RT-AC58U is\nclocked at a slightly higher 537 MHz ( ddrpllsdcc = 192000000 Hz).\n\nThis patch attempts to fix the issue by modifying\nclk_cpu_div_round_rate(), clk_cpu_div_set_rate(), clk_cpu_div_recalc_rate()\nto use a new qcom_find_freq_close() function, which returns the closest\nmatching frequency, instead of the next higher. This way, the SoC in\nthe FB4040 (with its max clock speed of 710.4 MHz) will no longer\ntry to overclock to 761 MHz.\n\nFixes: d83dcacea18 (\"clk: qcom: ipq4019: Add the apss cpu pll divider clock node\")\nSigned-off-by: Christian Lamparter <chunkeey@gmail.com>\nSigned-off-by: John Crispin <john@phrozen.org>\n---\n drivers/clk/qcom/gcc-ipq4019.c | 34 +++++++++++++++++++++++++++++++---\n 1 file changed, 31 insertions(+), 3 deletions(-)\n\n--- a/drivers/clk/qcom/gcc-ipq4019.c\n+++ b/drivers/clk/qcom/gcc-ipq4019.c\n@@ -1243,6 +1243,29 @@ static const struct clk_fepll_vco gcc_fe\n \t.reg = 0x2f020,\n };\n \n+\n+const struct freq_tbl *qcom_find_freq_close(const struct freq_tbl *f,\n+\t\t\t\t\t     unsigned long rate)\n+{\n+\tconst struct freq_tbl *last = NULL;\n+\n+\tfor ( ; f->freq; f++) {\n+\t\tif (rate == f->freq)\n+\t\t\treturn f;\n+\n+\t\tif (f->freq > rate) {\n+\t\t\tif (!last ||\n+\t\t\t   (f->freq - rate) < (rate - last->freq))\n+\t\t\t\treturn f;\n+\t\t\telse\n+\t\t\t\treturn last;\n+\t\t}\n+\t\tlast = f;\n+\t}\n+\n+\treturn last;\n+}\n+\n /*\n  * Round rate function for APSS CPU PLL Clock divider.\n  * It looks up the frequency table and returns the next higher frequency\n@@ -1255,7 +1278,7 @@ static long clk_cpu_div_round_rate(struc\n \tstruct clk_hw *p_hw;\n \tconst struct freq_tbl *f;\n \n-\tf = qcom_find_freq(pll->freq_tbl, rate);\n+\tf = qcom_find_freq_close(pll->freq_tbl, rate);\n \tif (!f)\n \t\treturn -EINVAL;\n \n@@ -1277,7 +1300,7 @@ static int clk_cpu_div_set_rate(struct c\n \tconst struct freq_tbl *f;\n \tu32 mask;\n \n-\tf = qcom_find_freq(pll->freq_tbl, rate);\n+\tf = qcom_find_freq_close(pll->freq_tbl, rate);\n \tif (!f)\n \t\treturn -EINVAL;\n \n@@ -1304,6 +1327,7 @@ static unsigned long\n clk_cpu_div_recalc_rate(struct clk_hw *hw,\n \t\t\tunsigned long parent_rate)\n {\n+\tconst struct freq_tbl *f;\n \tstruct clk_fepll *pll = to_clk_fepll(hw);\n \tu32 cdiv, pre_div;\n \tu64 rate;\n@@ -1324,7 +1348,11 @@ clk_cpu_div_recalc_rate(struct clk_hw *h\n \trate = clk_fepll_vco_calc_rate(pll, parent_rate) * 2;\n \tdo_div(rate, pre_div);\n \n-\treturn rate;\n+\tf = qcom_find_freq_close(pll->freq_tbl, rate);\n+\tif (!f)\n+\t\treturn rate;\n+\n+\treturn f->freq;\n };\n \n static const struct clk_ops clk_regmap_cpu_div_ops = {\n"
  },
  {
    "path": "target/linux/ipq40xx/patches-5.15/300-clk-qcom-ipq4019-add-ess-reset.patch",
    "content": "From 480c1f7648fc586db12d6003c717c23667a4fcf0 Mon Sep 17 00:00:00 2001\nFrom: Ram Chandra Jangir <rjangir@codeaurora.org>\nDate: Tue, 28 Mar 2017 22:35:33 +0530\nSubject: [PATCH] clk: qcom: ipq4019: add ess reset\n\nAdded the ESS reset in IPQ4019 GCC.\n\nSigned-off-by: Ram Chandra Jangir <rjangir@codeaurora.org>\n---\n drivers/clk/qcom/gcc-ipq4019.c               | 11 +++++++++++\n include/dt-bindings/clock/qcom,gcc-ipq4019.h | 11 +++++++++++\n 2 files changed, 22 insertions(+)\n\n--- a/drivers/clk/qcom/gcc-ipq4019.c\n+++ b/drivers/clk/qcom/gcc-ipq4019.c\n@@ -1735,6 +1735,17 @@ static const struct qcom_reset_map gcc_i\n \t[GCC_TCSR_BCR] = {0x22000, 0},\n \t[GCC_MPM_BCR] = {0x24000, 0},\n \t[GCC_SPDM_BCR] = {0x25000, 0},\n+\t[ESS_MAC1_ARES] = {0x1200C, 0},\n+\t[ESS_MAC2_ARES] = {0x1200C, 1},\n+\t[ESS_MAC3_ARES] = {0x1200C, 2},\n+\t[ESS_MAC4_ARES] = {0x1200C, 3},\n+\t[ESS_MAC5_ARES] = {0x1200C, 4},\n+\t[ESS_PSGMII_ARES] = {0x1200C, 5},\n+\t[ESS_MAC1_CLK_DIS] = {0x1200C, 8},\n+\t[ESS_MAC2_CLK_DIS] = {0x1200C, 9},\n+\t[ESS_MAC3_CLK_DIS] = {0x1200C, 10},\n+\t[ESS_MAC4_CLK_DIS] = {0x1200C, 11},\n+\t[ESS_MAC5_CLK_DIS] = {0x1200C, 12},\n };\n \n static const struct regmap_config gcc_ipq4019_regmap_config = {\n--- a/include/dt-bindings/clock/qcom,gcc-ipq4019.h\n+++ b/include/dt-bindings/clock/qcom,gcc-ipq4019.h\n@@ -165,5 +165,16 @@\n #define GCC_QDSS_BCR\t\t\t\t\t69\n #define GCC_MPM_BCR\t\t\t\t\t70\n #define GCC_SPDM_BCR\t\t\t\t\t71\n+#define ESS_MAC1_ARES\t\t\t\t\t72\n+#define ESS_MAC2_ARES\t\t\t\t\t73\n+#define ESS_MAC3_ARES\t\t\t\t\t74\n+#define ESS_MAC4_ARES\t\t\t\t\t75\n+#define ESS_MAC5_ARES\t\t\t\t\t76\n+#define ESS_PSGMII_ARES\t\t\t\t\t77\n+#define ESS_MAC1_CLK_DIS\t\t\t\t78\n+#define ESS_MAC2_CLK_DIS\t\t\t\t79\n+#define ESS_MAC3_CLK_DIS\t\t\t\t80\n+#define ESS_MAC4_CLK_DIS\t\t\t\t81\n+#define ESS_MAC5_CLK_DIS\t\t\t\t82\n \n #endif\n"
  },
  {
    "path": "target/linux/ipq40xx/patches-5.15/301-arm-compressed-add-appended-DTB-section.patch",
    "content": "From 0843a61d6913bdac8889eb048ed89f7903059787 Mon Sep 17 00:00:00 2001\nFrom: Robert Marko <robimarko@gmail.com>\nDate: Fri, 30 Oct 2020 13:36:31 +0100\nSubject: [PATCH] arm: compressed: add appended DTB section\n\nThis adds a appended_dtb section to the ARM decompressor\nlinker script.\n\nThis allows using the existing ARM zImage appended DTB support for\nappending a DTB to the raw ELF kernel.\n\nIts size is set to 1MB max to match the zImage appended DTB size limit.\n\nTo use it to pass the DTB to the kernel, objcopy is used:\n\nobjcopy --set-section-flags=.appended_dtb=alloc,contents \\\n\t--update-section=.appended_dtb=<target>.dtb vmlinux\n\nThis is based off the following patch:\nhttps://github.com/openwrt/openwrt/commit/c063e27e02a9dcac0e7f5877fb154e58fa3e1a69\n\nSigned-off-by: Robert Marko <robimarko@gmail.com>\n---\n arch/arm/boot/compressed/vmlinux.lds.S | 9 ++++++++-\n 1 file changed, 8 insertions(+), 1 deletion(-)\n\n--- a/arch/arm/boot/compressed/vmlinux.lds.S\n+++ b/arch/arm/boot/compressed/vmlinux.lds.S\n@@ -101,6 +101,13 @@ SECTIONS\n \n   _edata = .;\n \n+  .appended_dtb : {\n+    /* leave space for appended DTB */\n+    . += 0x100000;\n+  }\n+\n+  _edata_dtb = .;\n+\n   /*\n    * The image_end section appears after any additional loadable sections\n    * that the linker may decide to insert in the binary image.  Having\n@@ -138,4 +145,4 @@ SECTIONS\n \n   ARM_ASSERTS\n }\n-ASSERT(_edata_real == _edata, \"error: zImage file size is incorrect\");\n+ASSERT(_edata_real == _edata_dtb, \"error: zImage file size is incorrect\");\n"
  },
  {
    "path": "target/linux/ipq40xx/patches-5.15/302-arm-compressed-set-ipq40xx-watchdog-to-allow-boot.patch",
    "content": "From 11d6a6128a5a07c429941afc202b6e62a19771be Mon Sep 17 00:00:00 2001\nFrom: John Thomson <git@johnthomson.fastmail.com.au>\nDate: Fri, 23 Oct 2020 19:42:36 +1000\nSubject: [PATCH 2/2] arm: compressed: set ipq40xx watchdog to allow boot\n\nFor IPQ40XX systems where the SoC watchdog is activated before linux,\nthe watchdog timer may be too small for linux to finish uncompress,\nboot, and watchdog management start.\nIf the watchdog is enabled, set the timeout for it to 30 seconds.\nThe functionality and offsets were copied from:\ndrivers/watchdog/qcom-wdt.c qcom_wdt_set_timeout & qcom_wdt_start\nThe watchdog memory address was taken from:\narch/arm/boot/dts/qcom-ipq4019.dtsi\n\nThis was required on Mikrotik IPQ40XX consumer hardware using Mikrotik's\nRouterBoot bootloader.\n\nSigned-off-by: John Thomson <git@johnthomson.fastmail.com.au>\n---\n arch/arm/boot/compressed/head.S | 35 +++++++++++++++++++++++++++++++++\n 1 file changed, 35 insertions(+)\n\n--- a/arch/arm/boot/compressed/head.S\n+++ b/arch/arm/boot/compressed/head.S\n@@ -624,6 +624,41 @@ not_relocated:\tmov\tr0, #0\n \t\tbic\tr4, r4, #1\n \t\tblne\tcache_on\n \n+/* Set the Qualcom IPQ40xx watchdog timeout to 30 seconds\n+ * if it is enabled, so that there is time for kernel\n+ * to decompress, boot, and take over the watchdog.\n+ * data and functionality from drivers/watchdog/qcom-wdt.c\n+ * address from arch/arm/boot/dts/qcom-ipq4019.dtsi\n+ */\n+#ifdef CONFIG_ARCH_IPQ40XX\n+watchdog_set:\n+\t\t/* offsets:\n+\t\t * 0x04 reset\t(=1 resets countdown)\n+\t\t * 0x08 enable\t(=0 disables)\n+\t\t * 0x0c status\t(=1 when SoC was reset by watchdog)\n+\t\t * 0x10 bark\t(=timeout warning in ticks)\n+\t\t * 0x14 bite\t(=timeout reset in ticks)\n+\t\t * clock rate is 1<<15 hertz\n+\t\t */\n+\t\t.equ watchdog, 0x0b017000\t@Store watchdog base address\n+\t\tmovw r0, #:lower16:watchdog\n+\t\tmovt r0, #:upper16:watchdog\n+\t\tldr r1, [r0, #0x08]\t@Get enabled?\n+\t\tcmp r1, #1\t\t@If not enabled, do not change\n+\t\tbne watchdog_finished\n+\t\tmov r1, #0\n+\t\tstr r1, [r0, #0x08]\t@Disable the watchdog\n+\t\tmov r1, #1\n+\t\tstr r1, [r0, #0x04]\t@Pet the watchdog\n+\t\tmov r1, #30\t\t@30 seconds timeout\n+\t\tlsl r1, r1, #15\t\t@converted to ticks\n+\t\tstr r1, [r0, #0x10]\t@Set the bark timeout\n+\t\tstr r1, [r0, #0x14]\t@Set the bite timeout\n+\t\tmov r1, #1\n+\t\tstr r1, [r0, #0x08]\t@Enable the watchdog\n+watchdog_finished:\n+#endif /* CONFIG_ARCH_IPQ40XX */\n+\n /*\n  * The C runtime environment should now be setup sufficiently.\n  * Set up some pointers, and start decompressing.\n"
  },
  {
    "path": "target/linux/ipq40xx/patches-5.15/400-mmc-sdhci-sdhci-msm-use-sdhci_set_clock-instead-of-s.patch",
    "content": "From f63ea127643a605da97090ce585fdd7c2d17fa42 Mon Sep 17 00:00:00 2001\nFrom: Robert Marko <robert.marko@sartura.hr>\nDate: Mon, 14 Dec 2020 13:35:35 +0100\nSubject: [PATCH] mmc: sdhci-msm: use sdhci_set_clock\n\nWhen using sdhci_msm_set_clock clock setting will fail, so lets\nuse the generic sdhci_set_clock.\n\nSigned-off-by: Robert Marko <robert.marko@sartura.hr>\n---\n drivers/mmc/host/sdhci-msm.c | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/drivers/mmc/host/sdhci-msm.c\n+++ b/drivers/mmc/host/sdhci-msm.c\n@@ -2445,7 +2445,7 @@ MODULE_DEVICE_TABLE(of, sdhci_msm_dt_mat\n \n static const struct sdhci_ops sdhci_msm_ops = {\n \t.reset = sdhci_msm_reset,\n-\t.set_clock = sdhci_msm_set_clock,\n+\t.set_clock = sdhci_set_clock,\n \t.get_min_clock = sdhci_msm_get_min_clock,\n \t.get_max_clock = sdhci_msm_get_max_clock,\n \t.set_bus_width = sdhci_set_bus_width,\n"
  },
  {
    "path": "target/linux/ipq40xx/patches-5.15/420-firmware-qcom-scm-disable-SDI.patch",
    "content": "--- a/drivers/firmware/qcom_scm.c\n+++ b/drivers/firmware/qcom_scm.c\n@@ -404,6 +404,20 @@ static int __qcom_scm_set_dload_mode(str\n \treturn qcom_scm_call_atomic(__scm->dev, &desc, NULL);\n }\n \n+static int __qcom_scm_disable_sdi(struct device *dev)\n+{\n+\tstruct qcom_scm_desc desc = {\n+\t\t.svc = QCOM_SCM_SVC_BOOT,\n+\t\t.cmd = QCOM_SCM_BOOT_CONFIG_SDI,\n+\t\t.arginfo = QCOM_SCM_ARGS(2),\n+\t\t.args[0] = 1  /* 1: disable watchdog debug */,\n+\t\t.args[1] = 0  /* 0: disable SDI */,\n+\t\t.owner = ARM_SMCCC_OWNER_SIP,\n+\t};\n+\n+\treturn qcom_scm_call(__scm->dev, &desc, NULL);\n+}\n+\n static void qcom_scm_set_download_mode(bool enable)\n {\n \tbool avail;\n@@ -1314,6 +1328,13 @@ static int qcom_scm_probe(struct platfor\n \tif (download_mode)\n \t\tqcom_scm_set_download_mode(true);\n \n+\t/*\n+\t * Factory firmware leaves SDI (a debug interface), which prevents\n+\t * clean reboot.\n+\t */\n+\tif (of_machine_is_compatible(\"google,wifi\"))\n+\t\t__qcom_scm_disable_sdi(__scm->dev);\n+\n \treturn 0;\n }\n \n--- a/drivers/firmware/qcom_scm.h\n+++ b/drivers/firmware/qcom_scm.h\n@@ -77,6 +77,7 @@ extern int scm_legacy_call(struct device\n #define QCOM_SCM_SVC_BOOT\t\t0x01\n #define QCOM_SCM_BOOT_SET_ADDR\t\t0x01\n #define QCOM_SCM_BOOT_TERMINATE_PC\t0x02\n+#define QCOM_SCM_BOOT_CONFIG_SDI\t0x09\n #define QCOM_SCM_BOOT_SET_DLOAD_MODE\t0x10\n #define QCOM_SCM_BOOT_SET_REMOTE_STATE\t0x0a\n #define QCOM_SCM_FLUSH_FLAG_MASK\t0x3\n"
  },
  {
    "path": "target/linux/ipq40xx/patches-5.15/421-firmware-qcom-scm-cold-boot-address.patch",
    "content": "--- a/drivers/firmware/qcom_scm-legacy.c\n+++ b/drivers/firmware/qcom_scm-legacy.c\n@@ -13,6 +13,9 @@\n #include <linux/arm-smccc.h>\n #include <linux/dma-mapping.h>\n \n+#include <asm/cacheflush.h>\n+#include <asm/outercache.h>\n+\n #include \"qcom_scm.h\"\n \n static DEFINE_MUTEX(qcom_scm_lock);\n@@ -117,6 +120,25 @@ static void __scm_legacy_do(const struct\n \t} while (res->a0 == QCOM_SCM_INTERRUPTED);\n }\n \n+static void qcom_scm_inv_range(unsigned long start, unsigned long end)\n+{\n+\tu32 cacheline_size, ctr;\n+\n+\tasm volatile(\"mrc p15, 0, %0, c0, c0, 1\" : \"=r\" (ctr));\n+\tcacheline_size = 4 << ((ctr >> 16) & 0xf);\n+\n+\tstart = round_down(start, cacheline_size);\n+\tend = round_up(end, cacheline_size);\n+\touter_inv_range(start, end);\n+\twhile (start < end) {\n+\t\tasm (\"mcr p15, 0, %0, c7, c6, 1\" : : \"r\" (start)\n+\t\t     : \"memory\");\n+\t\tstart += cacheline_size;\n+\t}\n+\tdsb();\n+\tisb();\n+}\n+\n /**\n  * scm_legacy_call() - Sends a command to the SCM and waits for the command to\n  * finish processing.\n@@ -160,10 +182,16 @@ int scm_legacy_call(struct device *dev,\n \n \trsp = scm_legacy_command_to_response(cmd);\n \n-\tcmd_phys = dma_map_single(dev, cmd, alloc_len, DMA_TO_DEVICE);\n-\tif (dma_mapping_error(dev, cmd_phys)) {\n-\t\tkfree(cmd);\n-\t\treturn -ENOMEM;\n+\tif (dev) {\n+\t\tcmd_phys = dma_map_single(dev, cmd, alloc_len, DMA_TO_DEVICE);\n+\t\tif (dma_mapping_error(dev, cmd_phys)) {\n+\t\t\tkfree(cmd);\n+\t\t\treturn -ENOMEM;\n+\t\t}\n+\t} else {\n+\t\tcmd_phys = virt_to_phys(cmd);\n+\t\t__cpuc_flush_dcache_area(cmd, alloc_len);\n+\t\touter_flush_range(cmd_phys, cmd_phys + alloc_len);\n \t}\n \n \tsmc.args[0] = 1;\n@@ -179,13 +207,26 @@ int scm_legacy_call(struct device *dev,\n \t\tgoto out;\n \n \tdo {\n-\t\tdma_sync_single_for_cpu(dev, cmd_phys + sizeof(*cmd) + cmd_len,\n-\t\t\t\t\tsizeof(*rsp), DMA_FROM_DEVICE);\n+\t\tif (dev) {\n+\t\t\tdma_sync_single_for_cpu(dev, cmd_phys + sizeof(*cmd) +\n+\t\t\t\t\t\tcmd_len, sizeof(*rsp),\n+\t\t\t\t\t\tDMA_FROM_DEVICE);\n+\t\t} else {\n+\t\t\tunsigned long start = (uintptr_t)cmd + sizeof(*cmd) +\n+\t\t\t\t\t      cmd_len;\n+\t\t\tqcom_scm_inv_range(start, start + sizeof(*rsp));\n+\t\t}\n \t} while (!rsp->is_complete);\n \n-\tdma_sync_single_for_cpu(dev, cmd_phys + sizeof(*cmd) + cmd_len +\n-\t\t\t\tle32_to_cpu(rsp->buf_offset),\n-\t\t\t\tresp_len, DMA_FROM_DEVICE);\n+\tif (dev) {\n+\t\tdma_sync_single_for_cpu(dev, cmd_phys + sizeof(*cmd) + cmd_len +\n+\t\t\t\t\tle32_to_cpu(rsp->buf_offset),\n+\t\t\t\t\tresp_len, DMA_FROM_DEVICE);\n+\t} else {\n+\t\tunsigned long start = (uintptr_t)cmd + sizeof(*cmd) + cmd_len +\n+\t\t\t\t      le32_to_cpu(rsp->buf_offset);\n+\t\tqcom_scm_inv_range(start, start + resp_len);\n+\t}\n \n \tif (res) {\n \t\tres_buf = scm_legacy_get_response_buffer(rsp);\n@@ -193,7 +234,8 @@ int scm_legacy_call(struct device *dev,\n \t\t\tres->result[i] = le32_to_cpu(res_buf[i]);\n \t}\n out:\n-\tdma_unmap_single(dev, cmd_phys, alloc_len, DMA_TO_DEVICE);\n+\tif (dev)\n+\t\tdma_unmap_single(dev, cmd_phys, alloc_len, DMA_TO_DEVICE);\n \tkfree(cmd);\n \treturn ret;\n }\n--- a/drivers/firmware/qcom_scm.c\n+++ b/drivers/firmware/qcom_scm.c\n@@ -344,6 +344,17 @@ int qcom_scm_set_cold_boot_addr(void *en\n \tdesc.args[0] = flags;\n \tdesc.args[1] = virt_to_phys(entry);\n \n+\t/*\n+\t * Factory firmware doesn't support the atomic variant. Non-atomic SCMs\n+\t * require ugly DMA invalidation support that was dropped upstream a\n+\t * while ago. For more info, see:\n+\t *\n+\t *  [RFC] qcom_scm: IPQ4019 firmware does not support atomic API?\n+\t *  https://lore.kernel.org/linux-arm-msm/20200913201608.GA3162100@bDebian/\n+\t */\n+\tif (of_machine_is_compatible(\"google,wifi\"))\n+\t\treturn qcom_scm_call(__scm ? __scm->dev : NULL, &desc, NULL);\n+\n \treturn qcom_scm_call_atomic(__scm ? __scm->dev : NULL, &desc, NULL);\n }\n EXPORT_SYMBOL(qcom_scm_set_cold_boot_addr);\n"
  },
  {
    "path": "target/linux/ipq40xx/patches-5.15/702-dts-ipq4019-add-PHY-switch-nodes.patch",
    "content": "From 9deeec35dd3b628b95624e41d4e04acf728991ba Mon Sep 17 00:00:00 2001\nFrom: Christian Lamparter <chunkeey@gmail.com>\nDate: Sun, 20 Nov 2016 02:20:54 +0100\nSubject: [PATCH] dts: ipq4019: add PHY/switch nodes\n\nThis patch adds both the \"qcom,ess-switch\" and \"qcom,ess-psgmii\"\nnodes which are needed for the ar40xx.c driver to initialize the\nswitch.\n\nSigned-off-by: Christian Lamparter <chunkeey@gmail.com>\n---\n arch/arm/boot/dts/qcom-ipq4019.dtsi | 23 +++++++++++++++++++++++\n 1 file changed, 23 insertions(+)\n\n--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi\n+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi\n@@ -617,6 +617,29 @@\n \t\t\t};\n \t\t};\n \n+\t\tess-switch@c000000 {\n+\t\t\tcompatible = \"qcom,ess-switch\";\n+\t\t\treg = <0xc000000 0x80000>;\n+\t\t\tswitch_access_mode = \"local bus\";\n+\t\t\tresets = <&gcc ESS_RESET>;\n+\t\t\treset-names = \"ess_rst\";\n+\t\t\tclocks = <&gcc GCC_ESS_CLK>;\n+\t\t\tclock-names = \"ess_clk\";\n+\t\t\tswitch_cpu_bmp = <0x1>;\n+\t\t\tswitch_lan_bmp = <0x1e>;\n+\t\t\tswitch_wan_bmp = <0x20>;\n+\t\t\tswitch_mac_mode = <0>; /* PORT_WRAPPER_PSGMII */\n+\t\t\tswitch_initvlas = <0x7c 0x54>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tess-psgmii@98000 {\n+\t\t\tcompatible = \"qcom,ess-psgmii\";\n+\t\t\treg = <0x98000 0x800>;\n+\t\t\tpsgmii_access_mode = \"local bus\";\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n \t\tusb3_ss_phy: ssphy@9a000 {\n \t\t\tcompatible = \"qcom,usb-ss-ipq4019-phy\";\n \t\t\t#phy-cells = <0>;\n"
  },
  {
    "path": "target/linux/ipq40xx/patches-5.15/703-net-IPQ4019-needs-rfs-vlan_tag-callbacks-in.patch",
    "content": "From 7c129254adb1093d10a62ed7bf7b956fcc6ffe34 Mon Sep 17 00:00:00 2001\nFrom: Rakesh Nair <ranair@codeaurora.org>\nDate: Wed, 20 Jul 2016 15:02:01 +0530\nSubject: [PATCH] net: IPQ4019 needs rfs/vlan_tag callbacks in\n netdev_ops\n\nAdd callback support to get default vlan tag and register\nreceive flow steering filter.\n\nUsed by IPQ4019 ess-edma driver.\n\nBUG=chrome-os-partner:33096\nTEST=none\n\nChange-Id: I266070e4a0fbe4a0d9966fe79a71e50ec4f26c75\nSigned-off-by: Rakesh Nair <ranair@codeaurora.org>\nReviewed-on: https://chromium-review.googlesource.com/362203\nCommit-Ready: Grant Grundler <grundler@chromium.org>\nTested-by: Grant Grundler <grundler@chromium.org>\nReviewed-by: Grant Grundler <grundler@chromium.org>\n---\n include/linux/netdevice.h | 13 +++++++++++++\n 1 file changed, 13 insertions(+)\n\n--- a/include/linux/netdevice.h\n+++ b/include/linux/netdevice.h\n@@ -771,6 +771,16 @@ struct xps_map {\n #define XPS_MIN_MAP_ALLOC ((L1_CACHE_ALIGN(offsetof(struct xps_map, queues[1])) \\\n        - sizeof(struct xps_map)) / sizeof(u16))\n \n+#ifdef CONFIG_RFS_ACCEL\n+typedef int (*set_rfs_filter_callback_t)(struct net_device *dev,\n+                                     __be32 src,\n+                                     __be32 dst,\n+                                     __be16 sport,\n+                                     __be16 dport,\n+                                     u8 proto,\n+                                     u16 rxq_index,\n+                                     u32 action);\n+#endif\n /*\n  * This structure holds all XPS maps for device.  Maps are indexed by CPU.\n  *\n@@ -1477,6 +1487,9 @@ struct net_device_ops {\n \t\t\t\t\t\t     const struct sk_buff *skb,\n \t\t\t\t\t\t     u16 rxq_index,\n \t\t\t\t\t\t     u32 flow_id);\n+        int                     (*ndo_register_rfs_filter)(struct net_device *dev,\n+                                                              set_rfs_filter_callback_t set_filter);\n+        int                     (*ndo_get_default_vlan_tag)(struct net_device *net);\n #endif\n \tint\t\t\t(*ndo_add_slave)(struct net_device *dev,\n \t\t\t\t\t\t struct net_device *slave_dev,\n"
  },
  {
    "path": "target/linux/ipq40xx/patches-5.15/705-net-add-qualcomm-ar40xx-phy.patch",
    "content": "--- a/drivers/net/mdio/Kconfig\n+++ b/drivers/net/mdio/Kconfig\n@@ -41,6 +41,13 @@ config ACPI_MDIO\n \thelp\n \t  ACPI MDIO bus (Ethernet PHY) accessors\n \n+config AR40XX_PHY\n+   tristate \"Driver for Qualcomm Atheros IPQ40XX switches\"\n+   depends on HAS_IOMEM && OF && OF_MDIO\n+   select SWCONFIG\n+   help\n+      This is the driver for Qualcomm Atheros IPQ40XX ESS switches.\n+\n if MDIO_BUS\n \n config MDIO_DEVRES\n--- a/drivers/net/mdio/Makefile\n+++ b/drivers/net/mdio/Makefile\n@@ -23,6 +23,8 @@ obj-$(CONFIG_MDIO_SUN4I)\t\t+= mdio-sun4i.\n obj-$(CONFIG_MDIO_THUNDER)\t\t+= mdio-thunder.o\n obj-$(CONFIG_MDIO_XGENE)\t\t+= mdio-xgene.o\n \n+obj-$(CONFIG_AR40XX_PHY)\t\t+= ar40xx.o\n+\n obj-$(CONFIG_MDIO_BUS_MUX)\t\t+= mdio-mux.o\n obj-$(CONFIG_MDIO_BUS_MUX_BCM6368)\t+= mdio-mux-bcm6368.o\n obj-$(CONFIG_MDIO_BUS_MUX_BCM_IPROC)\t+= mdio-mux-bcm-iproc.o\n"
  },
  {
    "path": "target/linux/ipq40xx/patches-5.15/706-dt-bindings-net-add-QCA807x-PHY.patch",
    "content": "From c66863c1ba8995b61e6d727d78a241c734f5bb57 Mon Sep 17 00:00:00 2001\nFrom: Robert Marko <robert.marko@sartura.hr>\nDate: Thu, 1 Oct 2020 15:05:35 +0200\nSubject: [PATCH] dt-bindings: net: add QCA807x PHY\n\nAdd DT bindings for Qualcomm QCA807x PHY series.\n\nSigned-off-by: Robert Marko <robert.marko@sartura.hr>\n---\n include/dt-bindings/net/qcom-qca807x.h | 45 ++++++++++++++++++++++++++\n 1 file changed, 45 insertions(+)\n create mode 100644 include/dt-bindings/net/qcom-qca807x.h\n\n--- /dev/null\n+++ b/include/dt-bindings/net/qcom-qca807x.h\n@@ -0,0 +1,45 @@\n+/* SPDX-License-Identifier: GPL-2.0-or-later */\n+/*\n+ * Device Tree constants for the Qualcomm QCA807X PHYs\n+ */\n+\n+#ifndef _DT_BINDINGS_QCOM_QCA807X_H\n+#define _DT_BINDINGS_QCOM_QCA807X_H\n+\n+#define PSGMII_QSGMII_TX_DRIVER_140MV\t0\n+#define PSGMII_QSGMII_TX_DRIVER_160MV\t1\n+#define PSGMII_QSGMII_TX_DRIVER_180MV\t2\n+#define PSGMII_QSGMII_TX_DRIVER_200MV\t3\n+#define PSGMII_QSGMII_TX_DRIVER_220MV\t4\n+#define PSGMII_QSGMII_TX_DRIVER_240MV\t5\n+#define PSGMII_QSGMII_TX_DRIVER_260MV\t6\n+#define PSGMII_QSGMII_TX_DRIVER_280MV\t7\n+#define PSGMII_QSGMII_TX_DRIVER_300MV\t8\n+#define PSGMII_QSGMII_TX_DRIVER_320MV\t9\n+#define PSGMII_QSGMII_TX_DRIVER_400MV\t10\n+#define PSGMII_QSGMII_TX_DRIVER_500MV\t11\n+/* Default value */\n+#define PSGMII_QSGMII_TX_DRIVER_600MV\t12\n+\n+/* Full amplitude, full bias current */\n+#define QCA807X_CONTROL_DAC_FULL_VOLT_BIAS\t\t0\n+/* Amplitude follow DSP (amplitude is adjusted based on cable length), half bias current */\n+#define QCA807X_CONTROL_DAC_DSP_VOLT_HALF_BIAS\t\t1\n+/* Full amplitude, bias current follow DSP (bias current is adjusted based on cable length) */\n+#define QCA807X_CONTROL_DAC_FULL_VOLT_DSP_BIAS\t\t2\n+/* Both amplitude and bias current follow DSP */\n+#define QCA807X_CONTROL_DAC_DSP_VOLT_BIAS\t\t3\n+/* Full amplitude, half bias current */\n+#define QCA807X_CONTROL_DAC_FULL_VOLT_HALF_BIAS\t\t4\n+/* Amplitude follow DSP setting; 1/4 bias current when cable<10m,\n+ * otherwise half bias current\n+ */\n+#define QCA807X_CONTROL_DAC_DSP_VOLT_QUARTER_BIAS\t5\n+/* Full amplitude; same bias current setting with “010” and “011”,\n+ * but half more bias is reduced when cable <10m\n+ */\n+#define QCA807X_CONTROL_DAC_FULL_VOLT_HALF_BIAS_SHORT\t6\n+/* Amplitude follow DSP; same bias current setting with “110”, default value */\n+#define QCA807X_CONTROL_DAC_DSP_VOLT_HALF_BIAS_SHORT\t7\n+\n+#endif\n"
  },
  {
    "path": "target/linux/ipq40xx/patches-5.15/707-net-phy-Add-Qualcom-QCA807x-driver.patch",
    "content": "From f825cdc8bfde7616a14e2163f16303a8973031d2 Mon Sep 17 00:00:00 2001\nFrom: Robert Marko <robert.marko@sartura.hr>\nDate: Wed, 7 Oct 2020 17:38:48 +0200\nSubject: [PATCH] net: phy: Add Qualcom QCA807x driver\n\nThis adds driver for the Qualcomm QCA8072 and QCA8075 PHY-s.\n\nThey are 2 or 5 port IEEE 802.3 clause 22 compliant 10BASE-Te, 100BASE-TX and 1000BASE-T PHY-s.\n\nThey feature 2 SerDes, one for PSGMII or QSGMII connection with MAC, while second one is SGMII for connection to MAC or fiber.\n\nBoth models have a combo port that supports 1000BASE-X and 100BASE-FX fiber.\n\nEach PHY inside of QCA807x series has 4 digitally controlled output only pins that natively drive LED-s.\nBut some vendors used these to driver generic LED-s controlled by userspace,\nso lets enable registering each PHY as GPIO controller and add driver for it.\n\nThese are commonly used in Qualcomm IPQ40xx, IPQ60xx and IPQ807x boards.\n\nSigned-off-by: Robert Marko <robert.marko@sartura.hr>\n---\n drivers/net/phy/Kconfig  | 6 ++++++\n drivers/net/phy/Makefile | 1 +\n 2 files changed, 7 insertions(+)\n\n--- a/drivers/net/phy/Kconfig\n+++ b/drivers/net/phy/Kconfig\n@@ -346,6 +346,12 @@ config AT803X_PHY\n \t  Currently supports the AR8030, AR8031, AR8033, AR8035 and internal\n \t  QCA8337(Internal qca8k PHY) model\n \n+config QCA807X_PHY\n+\ttristate \"Qualcomm QCA807X PHYs\"\n+\tdepends on OF_MDIO\n+\thelp\n+\t  Currently supports the QCA8072 and QCA8075 models.\n+\n config QSEMI_PHY\n \ttristate \"Quality Semiconductor PHYs\"\n \thelp\n--- a/drivers/net/phy/Makefile\n+++ b/drivers/net/phy/Makefile\n@@ -90,6 +90,7 @@ obj-$(CONFIG_NATIONAL_PHY)\t+= national.o\n obj-$(CONFIG_NXP_C45_TJA11XX_PHY)\t+= nxp-c45-tja11xx.o\n obj-$(CONFIG_NXP_TJA11XX_PHY)\t+= nxp-tja11xx.o\n obj-$(CONFIG_QSEMI_PHY)\t\t+= qsemi.o\n+obj-$(CONFIG_QCA807X_PHY)\t\t+= qca807x.o\n obj-$(CONFIG_REALTEK_PHY)\t+= realtek.o\n obj-$(CONFIG_RENESAS_PHY)\t+= uPD60620.o\n obj-$(CONFIG_ROCKCHIP_PHY)\t+= rockchip.o\n"
  },
  {
    "path": "target/linux/ipq40xx/patches-5.15/708-arm-dts-ipq4019-QCA807x-properties.patch",
    "content": "From e0fa88eaa3c176b71e563da68949ac2ab45aaa61 Mon Sep 17 00:00:00 2001\nFrom: Robert Marko <robert.marko@sartura.hr>\nDate: Fri, 2 Oct 2020 10:43:26 +0200\nSubject: [PATCH] arm: dts: ipq4019: QCA807x properties\n\nThis adds necessary DT properties for QCA807x PHY-s to IPQ4019 DTSI.\n\nSigned-off-by: Robert Marko <robert.marko@sartura.hr>\n---\n arch/arm/boot/dts/qcom-ipq4019.dtsi | 18 ++++++++++++++++++\n 1 file changed, 18 insertions(+)\n\n--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi\n+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi\n@@ -8,6 +8,7 @@\n #include <dt-bindings/clock/qcom,gcc-ipq4019.h>\n #include <dt-bindings/interrupt-controller/arm-gic.h>\n #include <dt-bindings/interrupt-controller/irq.h>\n+#include <dt-bindings/net/qcom-qca807x.h>\n \n / {\n \t#address-cells = <1>;\n@@ -598,22 +599,39 @@\n \n \t\t\tethphy0: ethernet-phy@0 {\n \t\t\t\treg = <0>;\n+\n+\t\t\t\tqcom,control-dac = <QCA807X_CONTROL_DAC_DSP_VOLT_QUARTER_BIAS>;\n \t\t\t};\n \n \t\t\tethphy1: ethernet-phy@1 {\n \t\t\t\treg = <1>;\n+\n+\t\t\t\tqcom,control-dac = <QCA807X_CONTROL_DAC_DSP_VOLT_QUARTER_BIAS>;\n \t\t\t};\n \n \t\t\tethphy2: ethernet-phy@2 {\n \t\t\t\treg = <2>;\n+\n+\t\t\t\tqcom,control-dac = <QCA807X_CONTROL_DAC_DSP_VOLT_QUARTER_BIAS>;\n \t\t\t};\n \n \t\t\tethphy3: ethernet-phy@3 {\n \t\t\t\treg = <3>;\n+\n+\t\t\t\tqcom,control-dac = <QCA807X_CONTROL_DAC_DSP_VOLT_QUARTER_BIAS>;\n \t\t\t};\n \n \t\t\tethphy4: ethernet-phy@4 {\n \t\t\t\treg = <4>;\n+\n+\t\t\t\tqcom,control-dac = <QCA807X_CONTROL_DAC_DSP_VOLT_QUARTER_BIAS>;\n+\t\t\t};\n+\n+\t\t\tpsgmiiphy: psgmii-phy@5 {\n+\t\t\t\treg = <5>;\n+\n+\t\t\t\tqcom,tx-driver-strength = <PSGMII_QSGMII_TX_DRIVER_300MV>;\n+\t\t\t\tqcom,psgmii-az;\n \t\t\t};\n \t\t};\n \n"
  },
  {
    "path": "target/linux/ipq40xx/patches-5.15/710-net-add-qualcomm-essedma-ethernet-driver.patch",
    "content": "From 12e9319da1adacac92930c899c99f0e1970cac11 Mon Sep 17 00:00:00 2001\nFrom: Christian Lamparter <chunkeey@googlemail.com>\nDate: Thu, 19 Jan 2017 02:01:31 +0100\nSubject: [PATCH 33/38] NET: add qualcomm essedma ethernet driver\n\nSigned-off-by: Christian Lamparter <chunkeey@gmail.com>\n---\n drivers/net/ethernet/qualcomm/Kconfig  | 9 +++++++++\n drivers/net/ethernet/qualcomm/Makefile | 1 +\n 2 files changed, 10 insertions(+)\n\n--- a/drivers/net/ethernet/qualcomm/Kconfig\n+++ b/drivers/net/ethernet/qualcomm/Kconfig\n@@ -62,4 +62,14 @@ config QCOM_EMAC\n \n source \"drivers/net/ethernet/qualcomm/rmnet/Kconfig\"\n \n+config ESSEDMA\n+\ttristate \"Qualcomm Atheros ESS Edma support\"\n+\tdepends on OF_MDIO\n+\thelp\n+\t  This driver supports ethernet edma adapter.\n+\t  Say Y to build this driver.\n+\n+\t  To compile this driver as a module, choose M here. The module\n+\t  will be called essedma.ko.\n+\n endif # NET_VENDOR_QUALCOMM\n--- a/drivers/net/ethernet/qualcomm/Makefile\n+++ b/drivers/net/ethernet/qualcomm/Makefile\n@@ -10,5 +10,6 @@ obj-$(CONFIG_QCA7000_UART) += qcauart.o\n qcauart-objs := qca_uart.o\n \n obj-y += emac/\n+obj-$(CONFIG_ESSEDMA) += essedma/\n \n obj-$(CONFIG_RMNET) += rmnet/\n"
  },
  {
    "path": "target/linux/ipq40xx/patches-5.15/711-dts-ipq4019-add-ethernet-essedma-node.patch",
    "content": "From c611d3780fa101662a822d10acf8feb04ca97409 Mon Sep 17 00:00:00 2001\nFrom: Christian Lamparter <chunkeey@gmail.com>\nDate: Sun, 20 Nov 2016 01:01:10 +0100\nSubject: [PATCH] dts: ipq4019: add ethernet essedma node\n\nThis patch adds the device-tree node for the ethernet\ninterfaces.\n\nNote: The driver isn't anywhere close to be upstream,\nso the info might change.\n\nSigned-off-by: Christian Lamparter <chunkeey@gmail.com>\n---\n arch/arm/boot/dts/qcom-ipq4019.dtsi | 60 +++++++++++++++++++++++++++++++++++++\n 1 file changed, 60 insertions(+)\n\n--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi\n+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi\n@@ -39,6 +39,8 @@\n \t\tspi1 = &blsp1_spi2;\n \t\ti2c0 = &blsp1_i2c3;\n \t\ti2c1 = &blsp1_i2c4;\n+\t\tethernet0 = &gmac0;\n+\t\tethernet1 = &gmac1;\n \t};\n \n \tcpus {\n@@ -658,6 +660,64 @@\n \t\t\tstatus = \"disabled\";\n \t\t};\n \n+\t\tedma@c080000 {\n+\t\t\tcompatible = \"qcom,ess-edma\";\n+\t\t\treg = <0xc080000 0x8000>;\n+\t\t\tqcom,page-mode = <0>;\n+\t\t\tqcom,rx_head_buf_size = <1540>;\n+\t\t\tqcom,mdio_supported;\n+\t\t\tqcom,poll_required = <1>;\n+\t\t\tqcom,num_gmac = <2>;\n+\t\t\tinterrupts = <0  65 IRQ_TYPE_EDGE_RISING\n+\t\t\t\t      0  66 IRQ_TYPE_EDGE_RISING\n+\t\t\t\t      0  67 IRQ_TYPE_EDGE_RISING\n+\t\t\t\t      0  68 IRQ_TYPE_EDGE_RISING\n+\t\t\t\t      0  69 IRQ_TYPE_EDGE_RISING\n+\t\t\t\t      0  70 IRQ_TYPE_EDGE_RISING\n+\t\t\t\t      0  71 IRQ_TYPE_EDGE_RISING\n+\t\t\t\t      0  72 IRQ_TYPE_EDGE_RISING\n+\t\t\t\t      0  73 IRQ_TYPE_EDGE_RISING\n+\t\t\t\t      0  74 IRQ_TYPE_EDGE_RISING\n+\t\t\t\t      0  75 IRQ_TYPE_EDGE_RISING\n+\t\t\t\t      0  76 IRQ_TYPE_EDGE_RISING\n+\t\t\t\t      0  77 IRQ_TYPE_EDGE_RISING\n+\t\t\t\t      0  78 IRQ_TYPE_EDGE_RISING\n+\t\t\t\t      0  79 IRQ_TYPE_EDGE_RISING\n+\t\t\t\t      0  80 IRQ_TYPE_EDGE_RISING\n+\t\t\t\t      0 240 IRQ_TYPE_EDGE_RISING\n+\t\t\t\t      0 241 IRQ_TYPE_EDGE_RISING\n+\t\t\t\t      0 242 IRQ_TYPE_EDGE_RISING\n+\t\t\t\t      0 243 IRQ_TYPE_EDGE_RISING\n+\t\t\t\t      0 244 IRQ_TYPE_EDGE_RISING\n+\t\t\t\t      0 245 IRQ_TYPE_EDGE_RISING\n+\t\t\t\t      0 246 IRQ_TYPE_EDGE_RISING\n+\t\t\t\t      0 247 IRQ_TYPE_EDGE_RISING\n+\t\t\t\t      0 248 IRQ_TYPE_EDGE_RISING\n+\t\t\t\t      0 249 IRQ_TYPE_EDGE_RISING\n+\t\t\t\t      0 250 IRQ_TYPE_EDGE_RISING\n+\t\t\t\t      0 251 IRQ_TYPE_EDGE_RISING\n+\t\t\t\t      0 252 IRQ_TYPE_EDGE_RISING\n+\t\t\t\t      0 253 IRQ_TYPE_EDGE_RISING\n+\t\t\t\t      0 254 IRQ_TYPE_EDGE_RISING\n+\t\t\t\t      0 255 IRQ_TYPE_EDGE_RISING>;\n+\n+\t\t\tstatus = \"disabled\";\n+\n+\t\t\tgmac0: gmac0 {\n+\t\t\t\tlocal-mac-address = [00 00 00 00 00 00];\n+\t\t\t\tvlan_tag = <1 0x1f>;\n+\t\t\t};\n+\n+\t\t\tgmac1: gmac1 {\n+\t\t\t\tlocal-mac-address = [00 00 00 00 00 00];\n+\t\t\t\tqcom,phy_mdio_addr = <4>;\n+\t\t\t\tqcom,poll_required = <1>;\n+\t\t\t\tqcom,forced_speed = <1000>;\n+\t\t\t\tqcom,forced_duplex = <1>;\n+\t\t\t\tvlan_tag = <2 0x20>;\n+\t\t\t};\n+\t\t};\n+\n \t\tusb3_ss_phy: ssphy@9a000 {\n \t\t\tcompatible = \"qcom,usb-ss-ipq4019-phy\";\n \t\t\t#phy-cells = <0>;\n"
  },
  {
    "path": "target/linux/ipq40xx/patches-5.15/850-soc-add-qualcomm-syscon.patch",
    "content": "From: Christian Lamparter <chunkeey@googlemail.com>\nSubject: SoC: add qualcomm syscon\n--- a/drivers/soc/qcom/Makefile\n+++ b/drivers/soc/qcom/Makefile\n@@ -21,6 +21,7 @@ obj-$(CONFIG_QCOM_SMP2P)\t+= smp2p.o\n obj-$(CONFIG_QCOM_SMSM)\t+= smsm.o\n obj-$(CONFIG_QCOM_SOCINFO)\t+= socinfo.o\n obj-$(CONFIG_QCOM_WCNSS_CTRL) += wcnss_ctrl.o\n+obj-$(CONFIG_QCOM_TCSR)\t += qcom_tcsr.o\n obj-$(CONFIG_QCOM_APR) += apr.o\n obj-$(CONFIG_QCOM_LLCC) += llcc-qcom.o\n obj-$(CONFIG_QCOM_RPMHPD) += rpmhpd.o\n--- a/drivers/soc/qcom/Kconfig\n+++ b/drivers/soc/qcom/Kconfig\n@@ -190,6 +190,13 @@ config QCOM_SOCINFO\n \t Say yes here to support the Qualcomm socinfo driver, providing\n \t information about the SoC to user space.\n \n+config QCOM_TCSR\n+\ttristate \"QCOM Top Control and Status Registers\"\n+\tdepends on ARCH_QCOM\n+\thelp\n+\t  Say y here to enable TCSR support.  The TCSR provides control\n+\t  functions for various peripherals.\n+\n config QCOM_WCNSS_CTRL\n \ttristate \"Qualcomm WCNSS control driver\"\n \tdepends on ARCH_QCOM || COMPILE_TEST\n--- /dev/null\n+++ b/drivers/soc/qcom/qcom_tcsr.c\n@@ -0,0 +1,98 @@\n+/*\n+ * Copyright (c) 2014, The Linux foundation. All rights reserved.\n+ *\n+ * This program is free software; you can redistribute it and/or modify\n+ * it under the terms of the GNU General Public License rev 2 and\n+ * only rev 2 as published by the free Software foundation.\n+ *\n+ * This program is distributed in the hope that it will be useful,\n+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\n+ * MERCHANTABILITY or fITNESS fOR A PARTICULAR PURPOSE.  See the\n+ * GNU General Public License for more details.\n+ */\n+\n+#include <linux/clk.h>\n+#include <linux/err.h>\n+#include <linux/io.h>\n+#include <linux/module.h>\n+#include <linux/of.h>\n+#include <linux/of_platform.h>\n+#include <linux/platform_device.h>\n+\n+#define TCSR_USB_PORT_SEL\t0xb0\n+#define TCSR_USB_HSPHY_CONFIG\t0xC\n+\n+#define TCSR_ESS_INTERFACE_SEL_OFFSET   0x0\n+#define TCSR_ESS_INTERFACE_SEL_MASK     0xf\n+\n+#define TCSR_WIFI0_GLB_CFG_OFFSET\t0x0\n+#define TCSR_WIFI1_GLB_CFG_OFFSET\t0x4\n+#define TCSR_PNOC_SNOC_MEMTYPE_M0_M2\t0x4\n+\n+static int tcsr_probe(struct platform_device *pdev)\n+{\n+\tstruct resource *res;\n+\tconst struct device_node *node = pdev->dev.of_node;\n+\tvoid __iomem *base;\n+\tu32 val;\n+\n+\tres = platform_get_resource(pdev, IORESOURCE_MEM, 0);\n+\tbase = devm_ioremap_resource(&pdev->dev, res);\n+\tif (IS_ERR(base))\n+\t\treturn PTR_ERR(base);\n+\n+\tif (!of_property_read_u32(node, \"qcom,usb-ctrl-select\", &val)) {\n+\t\tdev_err(&pdev->dev, \"setting usb port select = %d\\n\", val);\n+\t\twritel(val, base + TCSR_USB_PORT_SEL);\n+\t}\n+\n+\tif (!of_property_read_u32(node, \"qcom,usb-hsphy-mode-select\", &val)) {\n+\t\tdev_info(&pdev->dev, \"setting usb hs phy mode select = %x\\n\", val);\n+\t\twritel(val, base + TCSR_USB_HSPHY_CONFIG);\n+\t}\n+\n+\tif (!of_property_read_u32(node, \"qcom,ess-interface-select\", &val)) {\n+\t\tu32 tmp = 0;\n+\t\tdev_info(&pdev->dev, \"setting ess interface select = %x\\n\", val);\n+\t\ttmp = readl(base + TCSR_ESS_INTERFACE_SEL_OFFSET);\n+\t\ttmp = tmp & (~TCSR_ESS_INTERFACE_SEL_MASK);\n+\t\ttmp = tmp | (val&TCSR_ESS_INTERFACE_SEL_MASK);\n+\t\twritel(tmp, base + TCSR_ESS_INTERFACE_SEL_OFFSET);\n+        }\n+\n+\tif (!of_property_read_u32(node, \"qcom,wifi_glb_cfg\", &val)) {\n+\t\tdev_info(&pdev->dev, \"setting wifi_glb_cfg = %x\\n\", val);\n+\t\twritel(val, base + TCSR_WIFI0_GLB_CFG_OFFSET);\n+\t\twritel(val, base + TCSR_WIFI1_GLB_CFG_OFFSET);\n+\t}\n+\n+\tif (!of_property_read_u32(node, \"qcom,wifi_noc_memtype_m0_m2\", &val)) {\n+\t\tdev_info(&pdev->dev,\n+\t\t\t\"setting wifi_noc_memtype_m0_m2 = %x\\n\", val);\n+\t\twritel(val, base + TCSR_PNOC_SNOC_MEMTYPE_M0_M2);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static const struct of_device_id tcsr_dt_match[] = {\n+\t{ .compatible = \"qcom,tcsr\", },\n+\t{ },\n+};\n+\n+MODULE_DEVICE_TABLE(of, tcsr_dt_match);\n+\n+static struct platform_driver tcsr_driver = {\n+\t.driver = {\n+\t\t.name\t\t= \"tcsr\",\n+\t\t.owner\t\t= THIS_MODULE,\n+\t\t.of_match_table\t= tcsr_dt_match,\n+\t},\n+\t.probe = tcsr_probe,\n+};\n+\n+module_platform_driver(tcsr_driver);\n+\n+MODULE_AUTHOR(\"Andy Gross <agross@codeaurora.org>\");\n+MODULE_DESCRIPTION(\"QCOM TCSR driver\");\n+MODULE_LICENSE(\"GPL v2\");\n--- /dev/null\n+++ b/include/dt-bindings/soc/qcom,tcsr.h\n@@ -0,0 +1,48 @@\n+/* Copyright (c) 2014, The Linux Foundation. All rights reserved.\n+ *\n+ * This program is free software; you can redistribute it and/or modify\n+ * it under the terms of the GNU General Public License version 2 and\n+ * only version 2 as published by the Free Software Foundation.\n+ *\n+ * This program is distributed in the hope that it will be useful,\n+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\n+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n+ * GNU General Public License for more details.\n+ */\n+#ifndef __DT_BINDINGS_QCOM_TCSR_H\n+#define __DT_BINDINGS_QCOM_TCSR_H\n+\n+#define TCSR_USB_SELECT_USB3_P0\t\t0x1\n+#define TCSR_USB_SELECT_USB3_P1\t\t0x2\n+#define TCSR_USB_SELECT_USB3_DUAL\t0x3\n+\n+/* IPQ40xx HS PHY Mode Select */\n+#define TCSR_USB_HSPHY_HOST_MODE\t0x00E700E7\n+#define TCSR_USB_HSPHY_DEVICE_MODE\t0x00C700E7\n+\n+/* IPQ40xx ess interface mode select */\n+#define TCSR_ESS_PSGMII              0\n+#define TCSR_ESS_PSGMII_RGMII5       1\n+#define TCSR_ESS_PSGMII_RMII0        2\n+#define TCSR_ESS_PSGMII_RMII1        4\n+#define TCSR_ESS_PSGMII_RMII0_RMII1  6\n+#define TCSR_ESS_PSGMII_RGMII4       9\n+\n+/*\n+ * IPQ40xx WiFi Global Config\n+ * Bit 30:AXID_EN\n+ * Enable AXI master bus Axid translating to confirm all txn submitted by order\n+ * Bit 24: Use locally generated socslv_wxi_bvalid\n+ * 1:  use locally generate socslv_wxi_bvalid for performance.\n+ * 0:  use SNOC socslv_wxi_bvalid.\n+ */\n+#define TCSR_WIFI_GLB_CFG\t\t0x41000000\n+\n+/* IPQ40xx MEM_TYPE_SEL_M0_M2 Select Bit 26:24 - 2 NORMAL */\n+#define TCSR_WIFI_NOC_MEMTYPE_M0_M2\t0x02222222\n+\n+/* TCSR A/B REG */\n+#define IPQ806X_TCSR_REG_A_ADM_CRCI_MUX_SEL     0\n+#define IPQ806X_TCSR_REG_B_ADM_CRCI_MUX_SEL     1\n+\n+#endif\n"
  },
  {
    "path": "target/linux/ipq40xx/patches-5.15/900-dts-ipq4019-ap-dk01.1.patch",
    "content": "--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi\n+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi\n@@ -15,6 +15,7 @@\n  */\n \n #include \"qcom-ipq4019.dtsi\"\n+#include <dt-bindings/soc/qcom,tcsr.h>\n \n / {\n \tmodel = \"Qualcomm Technologies, Inc. IPQ4019/AP-DK01.1\";\n@@ -29,6 +30,32 @@\n \t};\n \n \tsoc {\n+\t\ttcsr@194b000 {\n+\t\t\t/* select hostmode */\n+\t\t\tcompatible = \"qcom,tcsr\";\n+\t\t\treg = <0x194b000 0x100>;\n+\t\t\tqcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\n+\t\tess_tcsr@1953000 {\n+\t\t\tcompatible = \"qcom,tcsr\";\n+\t\t\treg = <0x1953000 0x1000>;\n+\t\t\tqcom,ess-interface-select = <TCSR_ESS_PSGMII>;\n+\t\t};\n+\n+\t\ttcsr@1949000 {\n+\t\t\tcompatible = \"qcom,tcsr\";\n+\t\t\treg = <0x1949000 0x100>;\n+\t\t\tqcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;\n+\t\t};\n+\n+\t\ttcsr@1957000 {\n+\t\t\tcompatible = \"qcom,tcsr\";\n+\t\t\treg = <0x1957000 0x100>;\n+\t\t\tqcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;\n+\t\t};\n+\n \t\trng@22000 {\n \t\t\tstatus = \"okay\";\n \t\t};\n@@ -74,14 +101,6 @@\n \t\t\tpinctrl-names = \"default\";\n \t\t\tstatus = \"okay\";\n \t\t\tcs-gpios = <&tlmm 54 0>;\n-\n-\t\t\tmx25l25635e@0 {\n-\t\t\t\t#address-cells = <1>;\n-\t\t\t\t#size-cells = <1>;\n-\t\t\t\treg = <0>;\n-\t\t\t\tcompatible = \"mx25l25635e\";\n-\t\t\t\tspi-max-frequency = <24000000>;\n-\t\t\t};\n \t\t};\n \n \t\tserial@78af000 {\n@@ -109,5 +128,41 @@\n \t\twifi@a800000 {\n \t\t\tstatus = \"okay\";\n \t\t};\n+\n+\t\tmdio@90000 {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\n+\t\tess-switch@c000000 {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\n+\t\tess-psgmii@98000 {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\n+\t\tedma@c080000 {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\n+\t\tusb3_ss_phy: ssphy@9a000 {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\n+\t\tusb3_hs_phy: hsphy@a6000 {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\n+\t\tusb3: usb3@8af8800 {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\n+\t\tusb2_hs_phy: hsphy@a8000 {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\n+\t\tusb2: usb2@60f8800 {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n \t};\n };\n--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts\n+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts\n@@ -18,5 +18,73 @@\n \n / {\n \tmodel = \"Qualcomm Technologies, Inc. IPQ40xx/AP-DK01.1-C1\";\n+\tcompatible = \"qcom,ap-dk01.1-c1\", \"qcom,ap-dk01.2-c1\";\n \n+\tmemory {\n+\t\tdevice_type = \"memory\";\n+\t\treg = <0x80000000 0x10000000>;\n+\t};\n+};\n+\n+&blsp1_spi1 {\n+\tmx25l25635f@0 {\n+\t\tcompatible = \"mx25l25635f\", \"jedec,spi-nor\";\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <1>;\n+\t\treg = <0>;\n+\t\tspi-max-frequency = <24000000>;\n+\n+\t\tSBL1@0 {\n+\t\t\tlabel = \"SBL1\";\n+\t\t\treg = <0x0 0x40000>;\n+\t\t\tread-only;\n+\t\t};\n+\t\tMIBIB@40000 {\n+\t\t\tlabel = \"MIBIB\";\n+\t\t\treg = <0x40000 0x20000>;\n+\t\t\tread-only;\n+\t\t};\n+\t\tQSEE@60000 {\n+\t\t\tlabel = \"QSEE\";\n+\t\t\treg = <0x60000 0x60000>;\n+\t\t\tread-only;\n+\t\t};\n+\t\tCDT@c0000 {\n+\t\t\tlabel = \"CDT\";\n+\t\t\treg = <0xc0000 0x10000>;\n+\t\t\tread-only;\n+\t\t};\n+\t\tDDRPARAMS@d0000 {\n+\t\t\tlabel = \"DDRPARAMS\";\n+\t\t\treg = <0xd0000 0x10000>;\n+\t\t\tread-only;\n+\t\t};\n+\t\tAPPSBLENV@e0000 {\n+\t\t\tlabel = \"APPSBLENV\";\n+\t\t\treg = <0xe0000 0x10000>;\n+\t\t\tread-only;\n+\t\t};\n+\t\tAPPSBL@f0000 {\n+\t\t\tlabel = \"APPSBL\";\n+\t\t\treg = <0xf0000 0x80000>;\n+\t\t\tread-only;\n+\t\t};\n+\t\tART@170000 {\n+\t\t\tlabel = \"ART\";\n+\t\t\treg = <0x170000 0x10000>;\n+\t\t\tread-only;\n+\t\t};\n+\t\tkernel@180000 {\n+\t\t\tlabel = \"kernel\";\n+\t\t\treg = <0x180000 0x400000>;\n+\t\t};\n+\t\trootfs@580000 {\n+\t\t\tlabel = \"rootfs\";\n+\t\t\treg = <0x580000 0x1600000>;\n+\t\t};\n+\t\tfirmware@180000 {\n+\t\t\tlabel = \"firmware\";\n+\t\t\treg = <0x180000 0x1a00000>;\n+\t\t};\n+\t};\n };\n"
  },
  {
    "path": "target/linux/ipq40xx/patches-5.15/901-arm-boot-add-dts-files.patch",
    "content": "From a10fab12a927e60b7141a602e740d70cb4d09e4a Mon Sep 17 00:00:00 2001\nFrom: John Crispin <john@phrozen.org>\nDate: Thu, 9 Mar 2017 11:03:18 +0100\nSubject: [PATCH] arm: boot: add dts files\n\nSigned-off-by: John Crispin <john@phrozen.org>\n---\n arch/arm/boot/dts/Makefile | 23 +++++++++++++++++++++++\n 1 file changed, 23 insertions(+)\n\n--- a/arch/arm/boot/dts/Makefile\n+++ b/arch/arm/boot/dts/Makefile\n@@ -951,11 +951,75 @@ dtb-$(CONFIG_ARCH_QCOM) += \\\n \tqcom-ipq4018-ap120c-ac.dtb \\\n \tqcom-ipq4018-ap120c-ac-bit.dtb \\\n \tqcom-ipq4018-jalapeno.dtb \\\n+\tqcom-ipq4018-a42.dtb \\\n+\tqcom-ipq4018-ap120c-ac.dtb \\\n+\tqcom-ipq4018-dap-2610.dtb \\\n+\tqcom-ipq4018-cs-w3-wd1200g-eup.dtb \\\n+\tqcom-ipq4018-magic-2-wifi-next.dtb \\\n+\tqcom-ipq4018-ea6350v3.dtb \\\n+\tqcom-ipq4018-eap1300.dtb \\\n+\tqcom-ipq4018-ecw5211.dtb \\\n+\tqcom-ipq4018-emd1.dtb \\\n+\tqcom-ipq4018-emr3500.dtb \\\n+\tqcom-ipq4018-ens620ext.dtb \\\n+\tqcom-ipq4018-ex6100v2.dtb \\\n+\tqcom-ipq4018-ex6150v2.dtb \\\n+\tqcom-ipq4018-fritzbox-4040.dtb \\\n+\tqcom-ipq4018-gl-ap1300.dtb \\\n+\tqcom-ipq4018-meshpoint-one.dtb \\\n+\tqcom-ipq4018-cap-ac.dtb \\\n+\tqcom-ipq4018-hap-ac2.dtb \\\n+\tqcom-ipq4018-sxtsq-5-ac.dtb \\\n+\tqcom-ipq4018-nbg6617.dtb \\\n+\tqcom-ipq4019-oap100.dtb \\\n+\tqcom-ipq4018-pa1200.dtb \\\n+\tqcom-ipq4018-rt-ac58u.dtb \\\n+\tqcom-ipq4018-rutx10.dtb \\\n+\tqcom-ipq4018-wac510.dtb \\\n+\tqcom-ipq4018-wre6606.dtb \\\n+\tqcom-ipq4018-wrtq-329acn.dtb \\\n \tqcom-ipq4019-ap.dk01.1-c1.dtb \\\n \tqcom-ipq4019-ap.dk04.1-c1.dtb \\\n \tqcom-ipq4019-ap.dk04.1-c3.dtb \\\n \tqcom-ipq4019-ap.dk07.1-c1.dtb \\\n \tqcom-ipq4019-ap.dk07.1-c2.dtb \\\n+\tqcom-ipq4019-a62.dtb \\\n+\tqcom-ipq4019-cm520-79f.dtb \\\n+\tqcom-ipq4019-e2600ac-c1.dtb \\\n+\tqcom-ipq4019-e2600ac-c2.dtb \\\n+\tqcom-ipq4019-ea8300.dtb \\\n+\tqcom-ipq4019-eap2200.dtb \\\n+\tqcom-ipq4019-fritzbox-7530.dtb \\\n+\tqcom-ipq4019-fritzrepeater-1200.dtb \\\n+\tqcom-ipq4019-fritzrepeater-3000.dtb \\\n+\tqcom-ipq4019-habanero-dvk.dtb \\\n+\tqcom-ipq4019-hap-ac3.dtb \\\n+\tqcom-ipq4019-map-ac2200.dtb \\\n+\tqcom-ipq4019-lhgg-60ad.dtb \\\n+\tqcom-ipq4019-mf286d.dtb \\\n+\tqcom-ipq4019-mr8300.dtb \\\n+\tqcom-ipq4019-pa2200.dtb \\\n+\tqcom-ipq4019-r619ac-64m.dtb \\\n+\tqcom-ipq4019-r619ac-128m.dtb \\\n+\tqcom-ipq4019-rbr50.dtb \\\n+\tqcom-ipq4019-rbs50.dtb \\\n+\tqcom-ipq4019-rt-ac42u.dtb \\\n+\tqcom-ipq4019-rtl30vw.dtb \\\n+\tqcom-ipq4019-srr60.dtb \\\n+\tqcom-ipq4019-srs60.dtb \\\n+\tqcom-ipq4019-u4019-32m.dtb \\\n+\tqcom-ipq4019-wifi.dtb \\\n+\tqcom-ipq4019-wpj419.dtb \\\n+\tqcom-ipq4019-wtr-m2133hp.dtb \\\n+\tqcom-ipq4019-x1pro.dtb \\\n+\tqcom-ipq4028-wpj428.dtb \\\n+\tqcom-ipq4029-ap-303.dtb \\\n+\tqcom-ipq4029-ap-303h.dtb \\\n+\tqcom-ipq4029-ap-365.dtb \\\n+\tqcom-ipq4029-gl-b1300.dtb \\\n+\tqcom-ipq4019-gl-b2200.dtb \\\n+\tqcom-ipq4029-gl-s1300.dtb \\\n+\tqcom-ipq4029-mr33.dtb \\\n \tqcom-ipq8064-ap148.dtb \\\n \tqcom-ipq8064-rb3011.dtb \\\n \tqcom-msm8226-samsung-s3ve3g.dtb \\\n"
  },
  {
    "path": "target/linux/ipq40xx/patches-5.15/902-dts-ipq4019-ap-dk04.1.patch",
    "content": "--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi\n+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi\n@@ -17,53 +17,79 @@\n \t\tstdout-path = \"serial0:115200n8\";\n \t};\n \n-\tmemory {\n-\t\tdevice_type = \"memory\";\n-\t\treg = <0x80000000 0x10000000>; /* 256MB */\n-\t};\n-\n \tsoc {\n+\t\trng@22000 {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\n \t\tpinctrl@1000000 {\n \t\t\tserial_0_pins: serial0-pinmux {\n-\t\t\t\tpins = \"gpio16\", \"gpio17\";\n-\t\t\t\tfunction = \"blsp_uart0\";\n-\t\t\t\tbias-disable;\n+\t\t\t\tmux {\n+\t\t\t\t\tpins = \"gpio16\", \"gpio17\";\n+\t\t\t\t\tfunction = \"blsp_uart0\";\n+\t\t\t\t\tbias-disable;\n+\t\t\t\t};\n \t\t\t};\n \n \t\t\tserial_1_pins: serial1-pinmux {\n-\t\t\t\tpins = \"gpio8\", \"gpio9\",\n-\t\t\t\t\t\"gpio10\", \"gpio11\";\n-\t\t\t\tfunction = \"blsp_uart1\";\n-\t\t\t\tbias-disable;\n+\t\t\t\tmux {\n+\t\t\t\t\tpins = \"gpio8\", \"gpio9\";\n+\t\t\t\t\tfunction = \"blsp_uart1\";\n+\t\t\t\t\tbias-disable;\n+\t\t\t\t};\n \t\t\t};\n \n \t\t\tspi_0_pins: spi-0-pinmux {\n \t\t\t\tpinmux {\n \t\t\t\t\tfunction = \"blsp_spi0\";\n \t\t\t\t\tpins = \"gpio13\", \"gpio14\", \"gpio15\";\n-\t\t\t\t\tbias-disable;\n \t\t\t\t};\n \t\t\t\tpinmux_cs {\n \t\t\t\t\tfunction = \"gpio\";\n \t\t\t\t\tpins = \"gpio12\";\n+\t\t\t\t};\n+\t\t\t\tpinconf {\n+\t\t\t\t\tpins = \"gpio13\", \"gpio14\", \"gpio15\";\n+\t\t\t\t\tdrive-strength = <12>;\n+\t\t\t\t\tbias-disable;\n+\t\t\t\t};\n+\t\t\t\tpinconf_cs {\n+\t\t\t\t\tpins = \"gpio12\";\n+\t\t\t\t\tdrive-strength = <2>;\n \t\t\t\t\tbias-disable;\n \t\t\t\t\toutput-high;\n \t\t\t\t};\n \t\t\t};\n \n \t\t\ti2c_0_pins: i2c-0-pinmux {\n-\t\t\t\tpins = \"gpio20\", \"gpio21\";\n-\t\t\t\tfunction = \"blsp_i2c0\";\n-\t\t\t\tbias-disable;\n+\t\t\t\tpinmux {\n+\t\t\t\t\tfunction = \"blsp_i2c0\";\n+\t\t\t\t\tpins = \"gpio10\", \"gpio11\";\n+\t\t\t\t};\n+\t\t\t\tpinconf {\n+\t\t\t\t\tpins = \"gpio10\", \"gpio11\";\n+\t\t\t\t\tdrive-strength = <16>;\n+\t\t\t\t\tbias-disable;\n+\t\t\t\t};\n \t\t\t};\n \n \t\t\tnand_pins: nand-pins {\n-\t\t\t\tpins = \"gpio53\", \"gpio55\", \"gpio56\",\n-\t\t\t\t\t\"gpio57\", \"gpio58\", \"gpio59\",\n-\t\t\t\t\t\"gpio60\", \"gpio62\", \"gpio63\",\n-\t\t\t\t\t\"gpio64\", \"gpio65\", \"gpio66\",\n-\t\t\t\t\t\"gpio67\", \"gpio68\", \"gpio69\";\n-\t\t\t\tfunction = \"qpic\";\n+\t\t\t\tpullups {\n+\t\t\t\t\tpins = \"gpio52\", \"gpio53\", \"gpio58\",\n+\t\t\t\t\t\t\"gpio59\";\n+\t\t\t\t\tfunction = \"qpic\";\n+\t\t\t\t\tbias-pull-up;\n+\t\t\t\t};\n+\n+\t\t\t\tpulldowns {\n+\t\t\t\t\tpins = \"gpio54\", \"gpio55\", \"gpio56\",\n+\t\t\t\t\t\t\"gpio57\", \"gpio60\", \"gpio61\",\n+\t\t\t\t\t\t\"gpio62\", \"gpio63\", \"gpio64\",\n+\t\t\t\t\t\t\"gpio65\", \"gpio66\", \"gpio67\",\n+\t\t\t\t\t\t\"gpio68\", \"gpio69\";\n+\t\t\t\t\tfunction = \"qpic\";\n+\t\t\t\t\tbias-pull-down;\n+\t\t\t\t};\n \t\t\t};\n \t\t};\n \n@@ -89,11 +115,11 @@\n \t\t\tstatus = \"okay\";\n \t\t\tcs-gpios = <&tlmm 12 0>;\n \n-\t\t\tm25p80@0 {\n+\t\t\tmx25l25635e@0 {\n \t\t\t\t#address-cells = <1>;\n \t\t\t\t#size-cells = <1>;\n \t\t\t\treg = <0>;\n-\t\t\t\tcompatible = \"n25q128a11\";\n+\t\t\t\tcompatible = \"mx25l25635e\";\n \t\t\t\tspi-max-frequency = <24000000>;\n \t\t\t};\n \t\t};\n@@ -103,9 +129,48 @@\n \t\t\tperst-gpio = <&tlmm 38 0x1>;\n \t\t};\n \n+\t\ti2c0: i2c@78b7000 { /* BLSP1 QUP2 */\n+\t\t\tpinctrl-0 = <&i2c_0_pins>;\n+\t\t\tpinctrl-names = \"default\";\n+\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\n \t\tqpic-nand@79b0000 {\n \t\t\tpinctrl-0 = <&nand_pins>;\n \t\t\tpinctrl-names = \"default\";\n \t\t};\n+\n+\t\tusb3_ss_phy: ssphy@9a000 {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\n+\t\tusb3_hs_phy: hsphy@a6000 {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\n+\t\tusb3: usb3@8af8800 {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\n+\t\tusb2_hs_phy: hsphy@a8000 {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\n+\t\tusb2: usb2@60f8800 {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\n+\t\tcryptobam: dma@8e04000 {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\n+\t\tcrypto@8e3a000 {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\n+\t\twatchdog@b017000 {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n \t};\n };\n"
  },
  {
    "path": "target/linux/ipq806x/Makefile",
    "content": "# Copyright (c) 2013 The Linux Foundation. All rights reserved.\n#\ninclude $(TOPDIR)/rules.mk\n\nARCH:=arm\nBOARD:=ipq806x\nBOARDNAME:=Qualcomm Atheros IPQ806X\nFEATURES:=squashfs nand fpu ramdisk\nCPU_TYPE:=cortex-a15\nCPU_SUBTYPE:=neon-vfpv4\nSUBTARGETS:=generic\n\nKERNEL_PATCHVER:=5.10\nKERNEL_TESTING_PATCHVER:=5.15\n\nKERNELNAME:=zImage Image dtbs\n\ninclude $(INCLUDE_DIR)/target.mk\nDEFAULT_PACKAGES += \\\n\tkmod-leds-gpio kmod-gpio-button-hotplug swconfig \\\n\tkmod-ata-ahci kmod-ata-ahci-platform \\\n\tkmod-usb-ohci kmod-usb2 kmod-usb-ledtrig-usbport \\\n\tkmod-phy-qcom-ipq806x-usb kmod-usb3 kmod-usb-dwc3-qcom \\\n\tkmod-ath10k-ct wpad-basic-wolfssl \\\n\tuboot-envtools\n\n$(eval $(call BuildTarget))\n"
  },
  {
    "path": "target/linux/ipq806x/base-files/etc/board.d/01_leds",
    "content": "#\n# Copyright (C) 2015 OpenWrt.org\n#\n\n. /lib/functions/uci-defaults.sh\n\nboard_config_update\n\nboard=$(board_name)\n\ncase \"$board\" in\nbuffalo,wxr-2533dhp)\n\tucidef_set_led_wlan \"wlan\" \"WLAN\" \"white:wireless\" \"phy0tpt\"\n\tucidef_set_led_switch \"wan\" \"WAN\" \"white:internet\" \"switch0\" \"0x20\"\n\t;;\ncompex,wpq864)\n\tucidef_set_led_usbport \"usb\" \"USB\" \"green:usb\" \"usb1-port1\" \"usb2-port1\"\n\tucidef_set_led_usbport \"pcie-usb\" \"PCIe USB\" \"green:usb-pcie\" \"usb3-port1\"\n\t;;\nedgecore,ecw5410)\n\tucidef_set_led_wlan \"wlan2g\" \"WLAN2G\" \"green:wlan2g\" \"phy1tpt\"\n\tucidef_set_led_wlan \"wlan5g\" \"WLAN5G\" \"green:wlan5g\" \"phy0tpt\"\n\t;;\nmeraki,mr52)\n\tucidef_set_led_netdev \"eth0\" \"eth0\" \"green:lan1\" \"eth0\"\n\tucidef_set_led_netdev \"eth1\" \"eth1\" \"green:lan2\" \"eth1\"\n\t;;\nnec,wg2600hp)\n\tucidef_set_led_wlan \"wlan2g\" \"WLAN2G\" \"green:wlan2g\" \"phy1tpt\"\n\tucidef_set_led_wlan \"wlan5g\" \"WLAN5G\" \"green:wlan5g\" \"phy0tpt\"\n\tucidef_set_led_switch \"wan\" \"WAN\" \"green:active\" \"switch0\" \"0x2\"\n\t;;\nnec,wg2600hp3)\n\tucidef_set_led_switch \"wan\" \"WAN\" \"green:active\" \"switch0\" \"0x2\"\n\t;;\nnetgear,d7800 |\\\nnetgear,r7500 |\\\nnetgear,r7500v2 |\\\nnetgear,r7800 |\\\nnetgear,xr500)\n\tucidef_set_led_usbport \"usb1\" \"USB 1\" \"white:usb1\" \"usb1-port1\" \"usb2-port1\"\n\tucidef_set_led_usbport \"usb2\" \"USB 2\" \"white:usb2\" \"usb3-port1\" \"usb4-port1\"\n\tucidef_set_led_switch \"wan\" \"WAN\" \"white:wan\" \"switch0\" \"0x20\"\n\tucidef_set_led_ide \"esata\" \"eSATA\" \"white:esata\"\n\t;;\ntplink,ad7200)\n\tucidef_set_led_usbport \"usb1\" \"USB 1\" \"blue:usb1\" \"usb1-port1\" \"usb2-port1\"\n\tucidef_set_led_usbport \"usb2\" \"USB 2\" \"blue:usb3\" \"usb3-port1\" \"usb4-port1\"\n\tucidef_set_led_switch \"wan\" \"wan\" \"blue:wan\" \"switch0\" \"0x02\"\n\tucidef_set_led_switch \"lan\" \"lan\" \"blue:lan\" \"switch0\" \"0x3c\"\n\tucidef_set_led_wlan \"wlan2g\" \"wlan2g\" \"blue:wlan2g\" \"phy2tpt\"\n\tucidef_set_led_wlan \"wlan5g\" \"wlan5g\" \"blue:wlan5g\" \"phy1tpt\"\n\tucidef_set_led_netdev \"wlan60g\" \"wlan60g\" \"blue:wlan60g\" \"wlan0\"\n\t;;\ntplink,c2600)\n\tucidef_set_led_usbport \"usb1\" \"USB 1\" \"white:usb_2\" \"usb1-port1\" \"usb2-port1\"\n\tucidef_set_led_usbport \"usb2\" \"USB 2\" \"white:usb_4\" \"usb3-port1\" \"usb4-port1\"\n\tucidef_set_led_switch \"wan\" \"wan\" \"white:wan\" \"switch0\" \"0x20\"\n\tucidef_set_led_switch \"lan\" \"lan\" \"white:lan\" \"switch0\" \"0x1e\"\n\t;;\ntplink,vr2600v)\n\tucidef_set_led_usbport \"usb\" \"USB\" \"white:usb\" \"usb1-port1\" \"usb2-port1\" \"usb3-port1\" \"usb4-port1\"\n\tucidef_set_led_switch \"lan\" \"lan\" \"white:lan\" \"switch0\" \"0x1e\"\n\tucidef_set_led_wlan \"wlan2g\" \"WLAN2G\" \"white:wlan2g\" \"phy0tpt\"\n\tucidef_set_led_wlan \"wlan5g\" \"WLAN5G\" \"white:wlan5g\" \"phy1tpt\"\n\tucidef_set_led_switch \"wan\" \"wan\" \"white:wan\" \"switch0\" \"0x20\"\n\t;;\nzyxel,nbg6817)\n\tucidef_set_led_netdev \"wan\" \"WAN\" \"white:internet\" \"eth1\"\n\t;;\nesac\n\nboard_config_flush\n\nexit 0\n"
  },
  {
    "path": "target/linux/ipq806x/base-files/etc/board.d/02_network",
    "content": "#\n# Copyright (c) 2015 The Linux Foundation. All rights reserved.\n# Copyright (c) 2011-2015 OpenWrt.org\n#\n\n. /lib/functions/uci-defaults.sh\n. /lib/functions/system.sh\n\nboard_config_update\n\nboard=$(board_name)\n\ncase \"$board\" in\narris,tr4400-v2)\n\tucidef_set_interfaces_lan_wan \"eth1\" \"eth2\"\n\tucidef_add_switch \"switch0\" \\\n\t\t\"1:lan\" \"2:lan\" \"3:lan\" \"4:lan\" \"6u@eth1\" \"0u@eth0\"\n\t;;\naskey,rt4230w-rev6 |\\\nasrock,g10 |\\\nnec,wg2600hp)\n\tucidef_add_switch \"switch0\" \\\n\t\t\"2:lan\" \"3:lan\" \"4:lan\" \"5:lan\" \"6@eth1\" \"1:wan\" \"0@eth0\"\n\t;;\nbuffalo,wxr-2533dhp |\\\ncompex,wpq864 |\\\nnetgear,d7800 |\\\nnetgear,r7500 |\\\nnetgear,r7500v2 |\\\nqcom,ipq8064-ap148 |\\\ntplink,vr2600v)\n\tucidef_add_switch \"switch0\" \\\n\t\t\"1:lan\" \"2:lan\" \"3:lan\" \"4:lan\" \"6@eth1\" \"5:wan\" \"0@eth0\"\n\t;;\nedgecore,ecw5410)\n\tucidef_set_interfaces_lan_wan \"eth1\" \"eth0\"\n\t;;\nlinksys,ea7500-v1)\n\thw_mac_addr=$(mtd_get_mac_ascii devinfo hw_mac_addr)\n\tucidef_add_switch \"switch0\" \\\n\t\t\"2:lan:1\" \"3:lan:2\" \"4:lan:3\" \"5:lan:4\" \"6@eth1\" \"1:wan\" \"0@eth0\"\n\tucidef_set_interface_macaddr \"lan\" \"$hw_mac_addr\"\n\tucidef_set_interface_macaddr \"wan\" \"$hw_mac_addr\"\n\t;;\nlinksys,ea8500)\n\thw_mac_addr=$(mtd_get_mac_ascii devinfo hw_mac_addr)\n\tucidef_add_switch \"switch0\" \\\n\t\t\"1:lan\" \"2:lan\" \"3:lan\" \"4:lan\" \"6@eth1\" \"5:wan\" \"0@eth0\"\n\tucidef_set_interface_macaddr \"lan\" \"$hw_mac_addr\"\n\tucidef_set_interface_macaddr \"wan\" \"$hw_mac_addr\"\n\t;;\nmeraki,mr42)\n\tucidef_set_interface_lan \"eth0\"\n\t;;\nmeraki,mr52)\n\tucidef_set_interfaces_lan_wan \"eth0\" \"eth1\"\n\t;;\nnec,wg2600hp3)\n\tucidef_add_switch \"switch0\" \\\n\t\t\"2:lan\" \"3:lan\" \"4:lan\" \"5:lan\" \"0@eth1\" \"1:wan\" \"6@eth0\"\n\t;;\nnetgear,r7800 |\\\nnetgear,xr500 |\\\ntplink,c2600)\n\tucidef_add_switch \"switch0\" \\\n\t\t\"1:lan:4\" \"2:lan:3\" \"3:lan:2\" \"4:lan:1\" \"6@eth1\" \"5:wan\" \"0@eth0\"\n\t;;\nqcom,ipq8064-ap161)\n\tucidef_set_interface_lan \"eth1 eth2\"\n\tucidef_add_switch \"switch0\" \\\n\t\t\"0:lan\" \"1:lan\" \"2:lan\" \"3u@eth1\" \"6:wan\" \"4u@eth0\"\n\t;;\nqcom,ipq8064-db149)\n\tucidef_set_interface_lan \"eth1 eth2 eth3\"\n\tucidef_add_switch \"switch0\" \\\n\t\t\"1:lan\" \"2:lan\" \"3:lan\" \"4:lan\" \"6u@eth1\" \"5:wan\" \"0u@eth0\"\n\t;;\ntplink,ad7200)\n\tucidef_add_switch \"switch0\" \\\n\t\t\"2:lan:1\" \"3:lan:2\" \"4:lan:3\" \"5:lan:4\" \"6@eth1\" \"1:wan\" \"0@eth0\"\n\t;;\nubnt,unifi-ac-hd)\n\tucidef_set_interface_lan \"eth0 eth1\"\n\t;;\nzyxel,nbg6817)\n\thw_mac_addr=$(mtd_get_mac_ascii 0:appsblenv ethaddr)\n\tucidef_add_switch \"switch0\" \\\n\t\t\"1:lan\" \"2:lan\" \"3:lan\" \"4:lan\" \"6@eth1\" \"5:wan\" \"0@eth0\"\n\tucidef_set_interface_macaddr \"lan\" \"$(macaddr_add $hw_mac_addr 2)\"\n\tucidef_set_interface_macaddr \"wan\" \"$(macaddr_add $hw_mac_addr 3)\"\n\t;;\n*)\n\techo \"Unsupported hardware. Network interfaces not intialized\"\n\t;;\nesac\n\nboard_config_flush\n\nexit 0\n"
  },
  {
    "path": "target/linux/ipq806x/base-files/etc/hotplug.d/firmware/11-ath10k-caldata",
    "content": "#!/bin/sh\n\n[ -e /lib/firmware/$FIRMWARE ] && exit 0\n\n. /lib/functions/caldata.sh\n\nboard=$(board_name)\n\ncase \"$FIRMWARE\" in\n\"ath10k/cal-pci-0000:01:00.0.bin\")\n\tcase \"$board\" in\n\tmeraki,mr52)\n\t\tCI_UBIPART=art\n\t\tcaldata_extract_ubi \"ART\" 0x1000 0x844\n\t\t;;\n\tesac\n\t;;\n\"ath10k/pre-cal-pci-0000:01:00.0.bin\")\n\tcase $board in\n\tasrock,g10)\n\t\tcaldata_extract \"0:art\" 0x1000 0x2f20\n\t\t;;\n\tlinksys,ea7500-v1 |\\\n\tlinksys,ea8500)\n\t\tcaldata_extract \"art\" 0x1000 0x2f20\n\t\tath10k_patch_mac $(macaddr_add $(mtd_get_mac_ascii devinfo hw_mac_addr) 1)\n\t\t;;\n\tmeraki,mr42)\n\t\tCI_UBIPART=art\n\t\tcaldata_extract_ubi \"ART\" 0x1000 0x2f20\n\t\t;;\n\tzyxel,nbg6817)\n\t\tcaldata_extract \"0:art\" 0x1000 0x2f20\n\t\tath10k_patch_mac $(macaddr_add $(mtd_get_mac_ascii 0:appsblenv ethaddr) 1)\n\t\t;;\n\tesac\n\t;;\n\"ath10k/pre-cal-pci-0001:01:00.0.bin\")\n\tcase $board in\n\tasrock,g10)\n\t\tcaldata_extract \"0:art\" 0x5000 0x2f20\n\t\t;;\n\tedgecore,ecw5410)\n\t\tcaldata_extract \"0:art\" 0x1000 0x2f20\n\t\t;;\n\tlinksys,ea7500-v1 |\\\n\tlinksys,ea8500)\n\t\tcaldata_extract \"art\" 0x5000 0x2f20\n\t\tath10k_patch_mac $(macaddr_add $(mtd_get_mac_ascii devinfo hw_mac_addr) 2)\n\t\t;;\n\tmeraki,mr42 |\\\n\tmeraki,mr52)\n\t\tCI_UBIPART=art\n\t\tcaldata_extract_ubi \"ART\" 0x5000 0x2f20\n\t\t;;\n\tzyxel,nbg6817)\n\t\tcaldata_extract \"0:art\" 0x5000 0x2f20\n\t\tath10k_patch_mac $(mtd_get_mac_ascii 0:appsblenv ethaddr)\n\t\t;;\n\tesac\n\t;;\n\"ath10k/cal-pci-0002:01:00.0.bin\")\n\tcase \"$board\" in\n\tmeraki,mr42)\n\t\tCI_UBIPART=art\n\t\tcaldata_extract_ubi \"ART\" 0x9000 0x844\n\t\t;;\n\tesac\n\t;;\n\"ath10k/pre-cal-pci-0002:01:00.0.bin\")\n\tcase $board in\n\tedgecore,ecw5410)\n\t\tcaldata_extract \"0:art\" 0x5000 0x2f20\n\t\t;;\n\tmeraki,mr52)\n\t\tCI_UBIPART=art\n\t\tcaldata_extract_ubi \"ART\" 0x9000 0x2f20\n\t\t;;\n\tesac\n\t;;\n*)\n\texit 1\n\t;;\nesac\n"
  },
  {
    "path": "target/linux/ipq806x/base-files/etc/hotplug.d/ieee80211/10_fix_wifi_mac",
    "content": "#!/bin/ash\n\n[ \"$ACTION\" == \"add\" ] || exit 0\n\nPHYNBR=${DEVPATH##*/phy}\n\n[ -n $PHYNBR ] || exit 0\n\n. /lib/functions.sh\n. /lib/functions/system.sh\n\nboard=$(board_name)\n\ncase \"$board\" in\n\tubnt,unifi-ac-hd)\n\t\tmacaddr_add $(mtd_get_mac_binary EEPROM 0x6) $(($PHYNBR + 1)) > /sys${DEVPATH}/macaddress\n\t\t;;\nesac\n\nOPATH=${DEVPATH##/devices/platform/}\nOPATH=${OPATH%%/ieee*}\n\n# 10 radios is enough for anyone!\nfor i in $(seq 0 9);\n  do\n  BUS=$(uci get wireless.@wifi-device[$i].path)\n  if [ \"$BUS \" == \"$OPATH \" ]\n      then\n      PHYNAME=${DEVPATH##*ieee80211/}\n      NPHYNAME=$(uci get wireless.@wifi-device[$i].phyname)\n      if [ \"$NPHYNAME \" != \" \" ]\n          then\n          if [ \"$PHYNAME \" != \"$NPHYNAME \" ]\n              then\n              iw $PHYNAME set name $NPHYNAME\n          fi\n      fi\n  fi\ndone\n"
  },
  {
    "path": "target/linux/ipq806x/base-files/etc/init.d/bootcount",
    "content": "#!/bin/sh /etc/rc.common\n\nSTART=99\n\n. \"$IPKG_INSTROOT/lib/upgrade/asrock.sh\"\n\nboot() {\n\tcase $(board_name) in\n\tasrock,g10)\n\t\tasrock_bootconfig_mangle \"bootcheck\" && reboot\n\t\t;;\n\tedgecore,ecw5410)\n\t\tfw_setenv bootcount 0\n\t\t;;\n\tlinksys,ea7500-v1 |\\\n\tlinksys,ea8500)\n\t\tmtd resetbc s_env || true\n\t\t;;\n\tesac\n}\n"
  },
  {
    "path": "target/linux/ipq806x/base-files/etc/init.d/cpufreq",
    "content": "#!/bin/sh /etc/rc.common\n\nSTART=15\n\nboot() {\n  local governor\n\n  governor=$(cat /sys/devices/system/cpu/cpufreq/policy0/scaling_governor)\n\n  if [ \"$governor\" = \"ondemand\" ]; then\n    # Effective only with ondemand\n    echo 600000 > /sys/devices/system/cpu/cpufreq/policy0/scaling_min_freq\n    echo 600000 > /sys/devices/system/cpu/cpufreq/policy1/scaling_min_freq\n    echo 10 > /sys/devices/system/cpu/cpufreq/ondemand/sampling_down_factor\n    echo 50 > /sys/devices/system/cpu/cpufreq/ondemand/up_threshold\n  fi\n}\n"
  },
  {
    "path": "target/linux/ipq806x/base-files/etc/inittab",
    "content": "# Copyright (c) 2013 The Linux Foundation. All rights reserved.\n::sysinit:/etc/init.d/rcS S boot\n::shutdown:/etc/init.d/rcS K shutdown\nttyMSM0::askfirst:/usr/libexec/login.sh\n"
  },
  {
    "path": "target/linux/ipq806x/base-files/etc/uci-defaults/04_led_migration",
    "content": ". /lib/functions/migrations.sh\n\nremove_devicename_leds\n\nmigrations_apply system\n\nexit 0\n"
  },
  {
    "path": "target/linux/ipq806x/base-files/etc/uci-defaults/05_fix-compat-version",
    "content": ". /lib/functions.sh\n\ncase \"$(board_name)\" in\n\tlinksys,ea7500-v1|\\\n\tlinksys,ea8500)\n\t\tuci set system.@system[0].compat_version=\"2.0\"\n\t\tuci commit system\n\t;;\nesac\n\nexit 0\n"
  },
  {
    "path": "target/linux/ipq806x/base-files/lib/preinit/04_reorder_eth",
    "content": ". /lib/functions.sh\n\npreinit_reorder_eth() {\n\tcase $(board_name) in\n\tubnt,unifi-ac-hd)\n\t\tip link set eth0 name ethtmp\n\t\tip link set eth1 name eth0\n\t\tip link set ethtmp name eth1\n\t\t;;\n\tesac\n}\n\nboot_hook_add preinit_main preinit_reorder_eth\n"
  },
  {
    "path": "target/linux/ipq806x/base-files/lib/preinit/05_set_iface_mac_ipq806x.sh",
    "content": ". /lib/functions.sh\n\npreinit_set_mac_address() {\n\tcase $(board_name) in\n\tasrock,g10)\n\t\tlan_mac=$(mtd_get_mac_ascii hwconfig HW.LAN.MAC.Address)\n\t\twan_mac=$(mtd_get_mac_ascii hwconfig HW.WAN.MAC.Address)\n\t\tip link set dev eth0 address \"${lan_mac}\"\n\t\tip link set dev eth1 address \"${wan_mac}\"\n\t\t;;\n\tesac\n}\n\nboot_hook_add preinit_main preinit_set_mac_address\n"
  },
  {
    "path": "target/linux/ipq806x/base-files/lib/upgrade/asrock.sh",
    "content": ". \"$IPKG_INSTROOT/lib/functions.sh\"\n\nasrock_bootconfig_mangle() {\n\tlocal mtdnum=\"$(find_mtd_index 0:bootconfig)\"\n\n\tif [ -z \"$mtdnum\" ]; then\n\t\techo \"cannot find bootconfig mtd partition\"\n\t\treturn 1\n\tfi\n\tdd if=/dev/mtd$mtdnum of=/tmp/mtd$mtdnum bs=1k\n\n\tlocal partition_byte=\"$(dd if=/tmp/mtd$mtdnum bs=1 skip=52 count=1)\"\n\tlocal upgrade_byte=\"$(dd if=/tmp/mtd$mtdnum bs=1 skip=4 count=1)\"\n\n\tif [ $1 = \"bootcheck\" ]; then\n\t\tif [ ! -s $upgrade_byte ]; then\n\t\t\tdd if=/dev/mtd$mtdnum of=/tmp/mtd$mtdnum bs=1k\n\t\t\tprintf '\\x00' | dd of=/tmp/mtd$mtdnum conv=notrunc bs=1 seek=4\n\t\t\tprintf '\\x00' | dd of=/tmp/mtd$mtdnum conv=notrunc bs=1 seek=56\n\t\telse\n\t\t\treturn 1\n\t\tfi\n\telif [ $1 = \"sysupgrade\" ]; then\n\t\tprintf '\\x01' | dd of=/tmp/mtd$mtdnum conv=notrunc bs=1 seek=4\n\t\tprintf '\\x01' | dd of=/tmp/mtd$mtdnum conv=notrunc bs=1 seek=56\n\tfi\n\n\tif [ -s $partition_byte ]; then\n\t\tprintf '\\x01' | dd of=/tmp/mtd$mtdnum conv=notrunc bs=1 seek=52\n\telse\n\t\tprintf '\\x00' | dd of=/tmp/mtd$mtdnum conv=notrunc bs=1 seek=52\n\tfi\n\n\tmtd write /tmp/mtd$mtdnum /dev/mtd$mtdnum\n\treturn 0\n}\n\nasrock_upgrade_prepare() {\n\tlocal ubidev=\"$( nand_find_ubi ubi )\"\n\n\t#Set upgrade flag. If something goes wrong, router will boot with\n\t#factory firmware.\n\tasrock_bootconfig_mangle 'sysupgrade'\n\n\tif [ $? -ne 0 ]; then\n\t\techo \"cannot find bootconfig mtd partition\"\n\t\texit 1\n\tfi\n\n\t# Just delete these partitions if present and use\n\t# OpenWrt's standard names for those.\n\tubirmvol /dev/$ubidev -N ubi_rootfs &> /dev/null || true\n\tubirmvol /dev/$ubidev -N ubi_rootfs_data &> /dev/null || true\n}\n"
  },
  {
    "path": "target/linux/ipq806x/base-files/lib/upgrade/buffalo.sh",
    "content": "# Copyright (C) 2018 OpenWrt.org\n#\n\n. /lib/functions.sh\n\n# The mtd partition 'ubi' and 'rootfs_1' on NAND flash are os-image\n# partitions. These partitions are called as \"Bank1/Bank2\" in U-Boot\n# on WXR-2533DHP, and they are checked conditions when booting.\n# Then, U-Boot checks kernel and rootfs volumes in ubi, but U-Boot\n# needs \"ubi_rootfs\" as rootfs volume name. And, U-Boot checks the\n# checksum at the end of rootfs (ubi_rootfs).\n# When U-Boot writes os-image into the Bank, only kernel, rootfs\n# (ubi_rootfs) and rootfs_data (ubi_rootfs_data) volumes are wrote\n# into the Bank. (not full ubi image)\n#\n# == U-Boot Behaviors ==\n# - Bank1/Bank2 images are good, images are different\n#   -> writes os-image to Bank1 from Bank2\n#      (this behavior is used to firmware upgrade in stock firmware)\n# - Bank1 image is broken (or checksum error)\n#   -> writes os-image to Bank1 from Bank2\n# - Bank2 image is broken (or checksum error)\n#   -> writes os-image to Bank2 from Bank1\n# - Bank1/Bank2 images are broken (or checksum error)\n#   -> start tftp\n\nbuffalo_upgrade_prepare_ubi() {\n\tlocal ubidev=\"$( nand_find_ubi ubi )\"\n\tlocal mtdnum2=\"$( find_mtd_index rootfs_1 )\"\n\n\tif [ ! \"$mtdnum2\" ]; then\n\t\techo \"cannot find second ubi mtd partition rootfs_1\"\n\t\treturn 1\n\tfi\n\n\tlocal ubidev2=\"$( nand_find_ubi rootfs_1 )\"\n\tif [ ! \"$ubidev2\" ] && [ -n \"$mtdnum2\" ]; then\n\t\tubiattach -m \"$mtdnum2\"\n\t\tubidev2=\"$( nand_find_ubi rootfs_1 )\"\n\tfi\n\n\tubirmvol /dev/$ubidev -N ubi_rootfs_data &> /dev/null || true\n\tubirmvol /dev/$ubidev2 -N kernel &> /dev/null || true\n}\n"
  },
  {
    "path": "target/linux/ipq806x/base-files/lib/upgrade/linksys.sh",
    "content": "#\n# Copyright (C) 2014-2015 OpenWrt.org\n#\n\nlinksys_get_target_firmware() {\n\n\tlocal cur_boot_part mtd_ubi0\n\n\tcur_boot_part=$(/usr/sbin/fw_printenv -n boot_part)\n\tif [ -z \"${cur_boot_part}\" ] ; then\n\t\tmtd_ubi0=$(cat /sys/devices/virtual/ubi/ubi0/mtd_num)\n\t\tcase $(grep -E ^mtd${mtd_ubi0}: /proc/mtd | cut -d '\"' -f 2) in\n\t\tkernel1|rootfs1)\n\t\t\tcur_boot_part=1\n\t\t\t;;\n\t\tkernel2|rootfs2)\n\t\t\tcur_boot_part=2\n\t\t\t;;\n\t\tesac\n\t\t>&2 printf \"Current boot_part='%s' selected from ubi0/mtd_num='%s'\" \\\n\t\t\t\"${cur_boot_part}\" \"${mtd_ubi0}\"\n\tfi\n\n\tcase $cur_boot_part in\n\t1)\n\t\tfw_setenv -s - <<-EOF\n\t\t\tboot_part 2\n\t\t\tauto_recovery yes\n\t\tEOF\n\t\tprintf \"kernel2\"\n\t\treturn\n\t\t;;\n\t2)\n\t\tfw_setenv -s - <<-EOF\n\t\t\tboot_part 1\n\t\t\tauto_recovery yes\n\t\tEOF\n\t\tprintf \"kernel1\"\n\t\treturn\n\t\t;;\n\t*)\n\t\treturn\n\t\t;;\n\tesac\n}\n\nplatform_do_upgrade_linksys() {\n\tlocal magic_long=\"$(get_magic_long \"$1\")\"\n\n\tmkdir -p /var/lock\n\tlocal part_label=\"$(linksys_get_target_firmware)\"\n\ttouch /var/lock/fw_printenv.lock\n\n\tif [ ! -n \"$part_label\" ]\n\tthen\n\t\techo \"cannot find target partition\"\n\t\texit 1\n\tfi\n\n\tlocal target_mtd=$(find_mtd_part $part_label)\n\n\t[ \"$magic_long\" = \"73797375\" ] && {\n\t\tCI_KERNPART=\"$part_label\"\n\t\tif [ \"$part_label\" = \"kernel1\" ]\n\t\tthen\n\t\t\tCI_UBIPART=\"rootfs1\"\n\t\telse\n\t\t\tCI_UBIPART=\"rootfs2\"\n\t\tfi\n\n\n\t\t# remove \"squashfs\" vol (in case we are flashing over a stock image, which is also UBI)\n\n\t\tlocal mtdnum=\"$( find_mtd_index \"$CI_UBIPART\" )\"\n\t\tif [ ! \"$mtdnum\" ]; then\n\t\t\techo \"cannot find ubi mtd partition $CI_UBIPART\"\n\t\t\treturn 1\n\t\tfi\n\n\t\tlocal ubidev=\"$( nand_find_ubi \"$CI_UBIPART\" )\"\n\t\tif [ ! \"$ubidev\" ]; then\n\t\t\tubiattach -m \"$mtdnum\"\n\t\t\tsync\n\t\t\tubidev=\"$( nand_find_ubi \"$CI_UBIPART\" )\"\n\t\tfi\n\n\t\tif [ \"$ubidev\" ]; then\n\n\t\t\tlocal squash_ubivol=\"$( nand_find_volume $ubidev squashfs )\"\n\n\t\t\t# kill volume\n\t\t\t[ \"$squash_ubivol\" ] && ubirmvol /dev/$ubidev -N squashfs || true\n\t\tfi\n\n\n\t\t# complete std upgrade\n\t\tnand_upgrade_tar \"$1\"\n\t}\n\t[ \"$magic_long\" = \"27051956\" ] && {\n\t\tget_image \"$1\" | mtd write - $part_label\n\t}\n}\n"
  },
  {
    "path": "target/linux/ipq806x/base-files/lib/upgrade/platform.sh",
    "content": "PART_NAME=firmware\nREQUIRE_IMAGE_METADATA=1\n\nRAMFS_COPY_BIN='fw_printenv fw_setenv'\nRAMFS_COPY_DATA='/etc/fw_env.config /var/lock/fw_printenv.lock'\n\nplatform_check_image() {\n\treturn 0;\n}\n\nplatform_do_upgrade() {\n\tcase \"$(board_name)\" in\n\tarris,tr4400-v2 |\\\n\taskey,rt4230w-rev6 |\\\n\tcompex,wpq864|\\\n\tnetgear,d7800 |\\\n\tnetgear,r7500 |\\\n\tnetgear,r7500v2 |\\\n\tnetgear,r7800 |\\\n\tnetgear,xr500 |\\\n\tqcom,ipq8064-ap148 |\\\n\tqcom,ipq8064-ap161)\n\t\tnand_do_upgrade \"$1\"\n\t\t;;\n\tasrock,g10)\n\t\tasrock_upgrade_prepare\n\t\tnand_do_upgrade \"$1\"\n\t\t;;\n\tbuffalo,wxr-2533dhp)\n\t\tbuffalo_upgrade_prepare_ubi\n\t\tCI_ROOTPART=\"ubi_rootfs\"\n\t\tnand_do_upgrade \"$1\"\n\t\t;;\n\tedgecore,ecw5410)\n\t\tpart=\"$(awk -F 'ubi.mtd=' '{printf $2}' /proc/cmdline | sed -e 's/ .*$//')\"\n\t\tif [ \"$part\" = \"rootfs1\" ]; then\n\t\t\tfw_setenv active 2 || exit 1\n\t\t\tCI_UBIPART=\"rootfs2\"\n\t\telse\n\t\t\tfw_setenv active 1 || exit 1\n\t\t\tCI_UBIPART=\"rootfs1\"\n\t\tfi\n\t\tnand_do_upgrade \"$1\"\n\t\t;;\n\tlinksys,ea7500-v1 |\\\n\tlinksys,ea8500)\n\t\tplatform_do_upgrade_linksys \"$1\"\n\t\t;;\n\tmeraki,mr42 |\\\n\tmeraki,mr52)\n\t\tCI_KERNPART=\"bootkernel2\"\n\t\tnand_do_upgrade \"$1\"\n\t\t;;\n\ttplink,ad7200 |\\\n\ttplink,c2600)\n\t\tPART_NAME=\"os-image:rootfs\"\n\t\tMTD_CONFIG_ARGS=\"-s 0x200000\"\n\t\tdefault_do_upgrade \"$1\"\n\t\t;;\n\ttplink,vr2600v)\n\t\tMTD_CONFIG_ARGS=\"-s 0x200000\"\n\t\tdefault_do_upgrade \"$1\"\n\t\t;;\n\tzyxel,nbg6817)\n\t\tzyxel_do_upgrade \"$1\"\n\t\t;;\n\t*)\n\t\tdefault_do_upgrade \"$1\"\n\t\t;;\n\tesac\n}\n"
  },
  {
    "path": "target/linux/ipq806x/base-files/lib/upgrade/zyxel.sh",
    "content": "#\n# Copyright (C) 2016 lede-project.org\n#\n\nzyxel_get_rootfs() {\n\tlocal rootfsdev\n\n\tif read cmdline < /proc/cmdline; then\n\t\tcase \"$cmdline\" in\n\t\t\t*root=*)\n\t\t\t\trootfsdev=\"${cmdline##*root=}\"\n\t\t\t\trootfsdev=\"${rootfsdev%% *}\"\n\t\t\t;;\n\t\tesac\n\n\t\techo \"${rootfsdev}\"\n\tfi\n}\n\nzyxel_do_flash() {\n\tlocal tar_file=$1\n\tlocal kernel=$2\n\tlocal rootfs=$3\n\tlocal dualflagmtd=$4\n\n\t# keep sure its unbound\n\tlosetup --detach-all || {\n\t\techo Failed to detach all loop devices. Skip this try.\n\t\treboot -f\n\t}\n\n\t# use the first found directory in the tar archive\n\tlocal board_dir=$(tar tf $tar_file | grep -m 1 '^sysupgrade-.*/$')\n\tboard_dir=${board_dir%/}\n\n\techo \"flashing kernel to $kernel\"\n\ttar xf $tar_file ${board_dir}/kernel -O >$kernel\n\n\techo \"flashing rootfs to ${rootfs}\"\n\ttar xf $tar_file ${board_dir}/root -O >\"${rootfs}\"\n\n\t# a padded rootfs is needed for overlay fs creation\n\tlocal offset=$(tar xf $tar_file ${board_dir}/root -O | wc -c)\n\t[ $offset -lt 65536 ] && {\n\t\techo Wrong size for rootfs: $offset\n\t\tsleep 10\n\t\treboot -f\n\t}\n\n\t# Mount loop for rootfs_data\n\tlocal loopdev=\"$(losetup -f)\"\n\tlosetup -o $offset $loopdev $rootfs || {\n\t\techo \"Failed to mount looped rootfs_data.\"\n\t\tsleep 10\n\t\treboot -f\n\t}\n\n\techo \"Format new rootfs_data at position ${offset}.\"\n\tmkfs.ext4 -F -L rootfs_data $loopdev\n\tmkdir /tmp/new_root\n\tmount -t ext4 $loopdev /tmp/new_root && {\n\t\techo \"Saving config to rootfs_data at position ${offset}.\"\n\t\tcp -v \"$UPGRADE_BACKUP\" \"/tmp/new_root/$BACKUP_FILE\"\n\t\tumount /tmp/new_root\n\t}\n\n\t# flashing successful, toggle the dualflag\n\tcase \"$rootfs\" in\n\t\t\"/dev/mmcblk0p5\")\n\t\t\tprintf \"\\xff\" >$dualflagmtd\n\t\t\t;;\n\t\t\"/dev/mmcblk0p8\")\n\t\t\tprintf \"\\x01\" >$dualflagmtd\n\t\t\t;;\n\tesac\n\n\t# Cleanup\n\tlosetup -d $loopdev >/dev/null 2>&1\n\tsync\n\tumount -a\n\treboot -f\n}\n\nzyxel_do_upgrade() {\n\tlocal tar_file=\"$1\"\n\tlocal board=$(board_name)\n\tlocal rootfs=\"$(zyxel_get_rootfs)\"\n\tlocal kernel=\n\n\t[ -b \"${rootfs}\" ] || return 1\n\tcase \"$board\" in\n\tzyxel,nbg6817)\n\t\tlocal dualflagmtd=\"$(find_mtd_part 0:dual_flag)\"\n\t\t[ -b $dualflagmtd ] || return 1\n\n\t\tcase \"$rootfs\" in\n\t\t\t\"/dev/mmcblk0p5\")\n\t\t\t\t# booted from the primary partition set\n\t\t\t\t# write to the alternative set\n\t\t\t\tkernel=\"/dev/mmcblk0p7\"\n\t\t\t\trootfs=\"/dev/mmcblk0p8\"\n\t\t\t;;\n\t\t\t\"/dev/mmcblk0p8\")\n\t\t\t\t# booted from the alternative partition set\n\t\t\t\t# write to the primary set\n\t\t\t\tkernel=\"/dev/mmcblk0p4\"\n\t\t\t\trootfs=\"/dev/mmcblk0p5\"\n\t\t\t;;\n\t\t\t*)\n\t\t\t\treturn 1\n\t\t\t;;\n\t\tesac\n\t\t;;\n\t*)\n\t\treturn 1\n\t\t;;\n\tesac\n\n\tzyxel_do_flash $tar_file $kernel $rootfs $dualflagmtd\n\n\tnand_do_upgrade \"$1\"\n\n\treturn 0\n}\n"
  },
  {
    "path": "target/linux/ipq806x/base-files/sbin/asrock_g10_back_to_factory",
    "content": "#!/bin/sh\n\n. /lib/upgrade/asrock.sh\n\ncase $(board_name) in\nasrock,g10)\n\tasrock_bootconfig_mangle \"factory\"\n\tif [ $? -eq 0 ]; then\n\t\treboot\n\tfi\n\t;;\n*)\n\techo \"Unsupported hardware.\"\n\t;;\nesac\n"
  },
  {
    "path": "target/linux/ipq806x/config-5.10",
    "content": "CONFIG_ALIGNMENT_TRAP=y\n# CONFIG_APQ_GCC_8084 is not set\n# CONFIG_APQ_MMCC_8084 is not set\nCONFIG_AR8216_PHY=y\nCONFIG_ARCH_32BIT_OFF_T=y\nCONFIG_ARCH_HIBERNATION_POSSIBLE=y\n# CONFIG_ARCH_IPQ40XX is not set\nCONFIG_ARCH_KEEP_MEMBLOCK=y\n# CONFIG_ARCH_MDM9615 is not set\nCONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y\nCONFIG_ARCH_MSM8960=y\nCONFIG_ARCH_MSM8974=y\nCONFIG_ARCH_MSM8X60=y\nCONFIG_ARCH_MULTIPLATFORM=y\nCONFIG_ARCH_MULTI_V6_V7=y\nCONFIG_ARCH_MULTI_V7=y\nCONFIG_ARCH_NR_GPIO=0\nCONFIG_ARCH_OPTIONAL_KERNEL_RWX=y\nCONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y\nCONFIG_ARCH_QCOM=y\nCONFIG_ARCH_SELECT_MEMORY_MODEL=y\nCONFIG_ARCH_SPARSEMEM_ENABLE=y\nCONFIG_ARCH_SUSPEND_POSSIBLE=y\nCONFIG_ARM=y\nCONFIG_ARM_AMBA=y\nCONFIG_ARM_APPENDED_DTB=y\nCONFIG_ARM_ARCH_TIMER=y\nCONFIG_ARM_ARCH_TIMER_EVTSTREAM=y\nCONFIG_ARM_ATAG_DTB_COMPAT=y\n# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER is not set\nCONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE=y\nCONFIG_ARM_CPUIDLE=y\nCONFIG_ARM_CPU_SUSPEND=y\n# CONFIG_ARM_CPU_TOPOLOGY is not set\nCONFIG_ARM_GIC=y\nCONFIG_ARM_HAS_SG_CHAIN=y\nCONFIG_ARM_L1_CACHE_SHIFT=6\nCONFIG_ARM_L1_CACHE_SHIFT_6=y\nCONFIG_ARM_MODULE_PLTS=y\nCONFIG_ARM_PATCH_IDIV=y\nCONFIG_ARM_PATCH_PHYS_VIRT=y\n# CONFIG_ARM_QCOM_CPUFREQ_HW is not set\nCONFIG_ARM_QCOM_CPUFREQ_KRAIT=y\nCONFIG_ARM_QCOM_CPUFREQ_NVMEM=y\nCONFIG_ARM_QCOM_SPM_CPUIDLE=y\n# CONFIG_ARM_SMMU is not set\nCONFIG_ARM_THUMB=y\nCONFIG_ARM_UNWIND=y\nCONFIG_ARM_VIRT_EXT=y\nCONFIG_AT803X_PHY=y\nCONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y\nCONFIG_BLK_DEV_LOOP=y\nCONFIG_BLK_MQ_PCI=y\nCONFIG_BOUNCE=y\n# CONFIG_CACHE_L2X0 is not set\nCONFIG_CLKDEV_LOOKUP=y\nCONFIG_CLKSRC_QCOM=y\nCONFIG_CLONE_BACKWARDS=y\nCONFIG_CMDLINE_OVERRIDE=y\nCONFIG_COMMON_CLK=y\nCONFIG_COMMON_CLK_QCOM=y\nCONFIG_COMPAT_32BIT_TIME=y\nCONFIG_CPUFREQ_DT=y\nCONFIG_CPUFREQ_DT_PLATDEV=y\nCONFIG_CPU_32v6K=y\nCONFIG_CPU_32v7=y\nCONFIG_CPU_ABRT_EV7=y\nCONFIG_CPU_CACHE_V7=y\nCONFIG_CPU_CACHE_VIPT=y\nCONFIG_CPU_COPY_V6=y\nCONFIG_CPU_CP15=y\nCONFIG_CPU_CP15_MMU=y\nCONFIG_CPU_FREQ=y\nCONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y\n# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set\nCONFIG_CPU_FREQ_GOV_ATTR_SET=y\nCONFIG_CPU_FREQ_GOV_COMMON=y\n# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set\nCONFIG_CPU_FREQ_GOV_ONDEMAND=y\nCONFIG_CPU_FREQ_GOV_PERFORMANCE=y\n# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set\nCONFIG_CPU_FREQ_GOV_SCHEDUTIL=y\n# CONFIG_CPU_FREQ_GOV_USERSPACE is not set\nCONFIG_CPU_FREQ_STAT=y\nCONFIG_CPU_HAS_ASID=y\nCONFIG_CPU_IDLE=y\nCONFIG_CPU_IDLE_GOV_LADDER=y\nCONFIG_CPU_IDLE_GOV_MENU=y\nCONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y\nCONFIG_CPU_PABRT_V7=y\nCONFIG_CPU_PM=y\nCONFIG_CPU_RMAP=y\nCONFIG_CPU_SPECTRE=y\nCONFIG_CPU_THERMAL=y\nCONFIG_CPU_THUMB_CAPABLE=y\nCONFIG_CPU_TLB_V7=y\nCONFIG_CPU_V7=y\nCONFIG_CRC16=y\n# CONFIG_CRC32_SARWATE is not set\nCONFIG_CRC32_SLICEBY8=y\nCONFIG_CRYPTO_DEFLATE=y\nCONFIG_CRYPTO_DEV_QCOM_RNG=y\nCONFIG_CRYPTO_DRBG=y\nCONFIG_CRYPTO_DRBG_HMAC=y\nCONFIG_CRYPTO_DRBG_MENU=y\nCONFIG_CRYPTO_HASH_INFO=y\nCONFIG_CRYPTO_HMAC=y\nCONFIG_CRYPTO_HW=y\nCONFIG_CRYPTO_JITTERENTROPY=y\nCONFIG_CRYPTO_LIB_SHA256=y\nCONFIG_CRYPTO_LZO=y\nCONFIG_CRYPTO_RNG=y\nCONFIG_CRYPTO_RNG2=y\nCONFIG_CRYPTO_SHA256=y\nCONFIG_CRYPTO_ZSTD=y\nCONFIG_DCACHE_WORD_ACCESS=y\nCONFIG_DEBUG_GPIO=y\nCONFIG_DEBUG_LL_INCLUDE=\"mach/debug-macro.S\"\n# CONFIG_DEVFREQ_GOV_PASSIVE is not set\n# CONFIG_DEVFREQ_GOV_PERFORMANCE is not set\n# CONFIG_DEVFREQ_GOV_POWERSAVE is not set\n# CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND is not set\n# CONFIG_DEVFREQ_GOV_USERSPACE is not set\n# CONFIG_DEVFREQ_THERMAL is not set\nCONFIG_DMADEVICES=y\nCONFIG_DMA_ENGINE=y\nCONFIG_DMA_OF=y\nCONFIG_DMA_OPS=y\nCONFIG_DMA_REMAP=y\nCONFIG_DMA_VIRTUAL_CHANNELS=y\nCONFIG_DTC=y\nCONFIG_DT_IDLE_STATES=y\n# CONFIG_DWMAC_GENERIC is not set\nCONFIG_DWMAC_IPQ806X=y\n# CONFIG_DWMAC_QCOM_ETHQOS is not set\nCONFIG_DYNAMIC_DEBUG=y\nCONFIG_EDAC_ATOMIC_SCRUB=y\nCONFIG_EDAC_SUPPORT=y\nCONFIG_ETHERNET_PACKET_MANGLE=y\nCONFIG_FIXED_PHY=y\nCONFIG_FIX_EARLYCON_MEM=y\nCONFIG_FW_LOADER_PAGED_BUF=y\nCONFIG_GENERIC_ALLOCATOR=y\nCONFIG_GENERIC_BUG=y\nCONFIG_GENERIC_CLOCKEVENTS=y\nCONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y\nCONFIG_GENERIC_CPU_AUTOPROBE=y\nCONFIG_GENERIC_EARLY_IOREMAP=y\nCONFIG_GENERIC_GETTIMEOFDAY=y\nCONFIG_GENERIC_IDLE_POLL_SETUP=y\nCONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y\nCONFIG_GENERIC_IRQ_MULTI_HANDLER=y\nCONFIG_GENERIC_IRQ_SHOW=y\nCONFIG_GENERIC_IRQ_SHOW_LEVEL=y\nCONFIG_GENERIC_MSI_IRQ=y\nCONFIG_GENERIC_MSI_IRQ_DOMAIN=y\nCONFIG_GENERIC_PCI_IOMAP=y\nCONFIG_GENERIC_PHY=y\nCONFIG_GENERIC_PINCONF=y\nCONFIG_GENERIC_PINCTRL_GROUPS=y\nCONFIG_GENERIC_PINMUX_FUNCTIONS=y\nCONFIG_GENERIC_SCHED_CLOCK=y\nCONFIG_GENERIC_SMP_IDLE_THREAD=y\nCONFIG_GENERIC_STRNCPY_FROM_USER=y\nCONFIG_GENERIC_STRNLEN_USER=y\nCONFIG_GENERIC_TIME_VSYSCALL=y\nCONFIG_GENERIC_VDSO_32=y\nCONFIG_GPIOLIB=y\nCONFIG_GPIOLIB_IRQCHIP=y\nCONFIG_GRO_CELLS=y\nCONFIG_HANDLE_DOMAIN_IRQ=y\nCONFIG_HARDEN_BRANCH_PREDICTOR=y\nCONFIG_HARDIRQS_SW_RESEND=y\nCONFIG_HAS_DMA=y\nCONFIG_HAS_IOMEM=y\nCONFIG_HAS_IOPORT_MAP=y\nCONFIG_HAVE_SMP=y\nCONFIG_HIGHMEM=y\nCONFIG_HIGHPTE=y\nCONFIG_HWMON=y\nCONFIG_HWSPINLOCK=y\nCONFIG_HWSPINLOCK_QCOM=y\nCONFIG_HW_RANDOM=y\nCONFIG_HZ_FIXED=0\nCONFIG_I2C=y\nCONFIG_I2C_BOARDINFO=y\nCONFIG_I2C_CHARDEV=y\nCONFIG_I2C_HELPER_AUTO=y\n# CONFIG_I2C_QCOM_CCI is not set\nCONFIG_I2C_QUP=y\nCONFIG_INITRAMFS_SOURCE=\"\"\n# CONFIG_IOMMU_DEBUGFS is not set\n# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set\n# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set\nCONFIG_IOMMU_SUPPORT=y\n# CONFIG_IPQ_APSS_PLL is not set\n# CONFIG_IPQ_GCC_4019 is not set\n# CONFIG_IPQ_GCC_6018 is not set\nCONFIG_IPQ_GCC_806X=y\n# CONFIG_IPQ_GCC_8074 is not set\n# CONFIG_IPQ_LCC_806X is not set\nCONFIG_IRQCHIP=y\nCONFIG_IRQ_DOMAIN=y\nCONFIG_IRQ_DOMAIN_HIERARCHY=y\nCONFIG_IRQ_FASTEOI_HIERARCHY_HANDLERS=y\nCONFIG_IRQ_FORCED_THREADING=y\nCONFIG_IRQ_WORK=y\nCONFIG_KPSS_XCC=y\nCONFIG_KRAITCC=y\nCONFIG_KRAIT_CLOCKS=y\nCONFIG_KRAIT_L2_ACCESSORS=y\nCONFIG_LIBFDT=y\nCONFIG_LOCK_DEBUGGING_SUPPORT=y\nCONFIG_LOCK_SPIN_ON_OWNER=y\nCONFIG_LZO_COMPRESS=y\nCONFIG_LZO_DECOMPRESS=y\nCONFIG_MDIO_BITBANG=y\nCONFIG_MDIO_BUS=y\nCONFIG_MDIO_DEVICE=y\nCONFIG_MDIO_DEVRES=y\nCONFIG_MDIO_GPIO=y\nCONFIG_MDIO_IPQ8064=y\n# CONFIG_MDM_GCC_9615 is not set\n# CONFIG_MDM_LCC_9615 is not set\nCONFIG_MEMFD_CREATE=y\n# CONFIG_MFD_HI6421_SPMI is not set\nCONFIG_MFD_QCOM_RPM=y\n# CONFIG_MFD_SPMI_PMIC is not set\nCONFIG_MFD_SYSCON=y\nCONFIG_MIGHT_HAVE_CACHE_L2X0=y\nCONFIG_MIGRATION=y\nCONFIG_MMC=y\nCONFIG_MMC_ARMMMCI=y\nCONFIG_MMC_BLOCK=y\nCONFIG_MMC_BLOCK_MINORS=16\nCONFIG_MMC_CQHCI=y\nCONFIG_MMC_QCOM_DML=y\nCONFIG_MMC_SDHCI=y\nCONFIG_MMC_SDHCI_IO_ACCESSORS=y\nCONFIG_MMC_SDHCI_MSM=y\n# CONFIG_MMC_SDHCI_PCI is not set\nCONFIG_MMC_SDHCI_PLTFM=y\nCONFIG_MODULES_USE_ELF_REL=y\nCONFIG_MSM_GCC_8660=y\n# CONFIG_MSM_GCC_8916 is not set\n# CONFIG_MSM_GCC_8939 is not set\n# CONFIG_MSM_GCC_8960 is not set\n# CONFIG_MSM_GCC_8974 is not set\n# CONFIG_MSM_GCC_8994 is not set\n# CONFIG_MSM_GCC_8996 is not set\n# CONFIG_MSM_GCC_8998 is not set\n# CONFIG_MSM_GPUCC_8998 is not set\n# CONFIG_MSM_IOMMU is not set\n# CONFIG_MSM_LCC_8960 is not set\n# CONFIG_MSM_MMCC_8960 is not set\n# CONFIG_MSM_MMCC_8974 is not set\n# CONFIG_MSM_MMCC_8996 is not set\n# CONFIG_MSM_MMCC_8998 is not set\nCONFIG_MTD_CMDLINE_PARTS=y\nCONFIG_MTD_NAND_CORE=y\nCONFIG_MTD_NAND_ECC=y\nCONFIG_MTD_NAND_ECC_SW_HAMMING=y\nCONFIG_MTD_NAND_QCOM=y\nCONFIG_MTD_QCOMSMEM_PARTS=y\nCONFIG_MTD_RAW_NAND=y\nCONFIG_MTD_SPI_NOR=y\nCONFIG_MTD_SPLIT_FIRMWARE=y\nCONFIG_MTD_SPLIT_FIT_FW=y\nCONFIG_MTD_SPLIT_UIMAGE_FW=y\nCONFIG_MTD_UBI=y\nCONFIG_MTD_UBI_BEB_LIMIT=20\nCONFIG_MTD_UBI_BLOCK=y\nCONFIG_MTD_UBI_WL_THRESHOLD=4096\nCONFIG_MUTEX_SPIN_ON_OWNER=y\nCONFIG_NEED_DMA_MAP_STATE=y\nCONFIG_NEON=y\nCONFIG_NET_DEVLINK=y\nCONFIG_NET_DSA=y\nCONFIG_NET_DSA_QCA8K=y\nCONFIG_NET_DSA_TAG_QCA=y\nCONFIG_NET_FLOW_LIMIT=y\nCONFIG_NET_PTP_CLASSIFY=y\nCONFIG_NET_SWITCHDEV=y\nCONFIG_NLS=y\nCONFIG_NO_HZ=y\nCONFIG_NO_HZ_COMMON=y\nCONFIG_NO_HZ_IDLE=y\nCONFIG_NR_CPUS=2\nCONFIG_NVMEM=y\n# CONFIG_NVMEM_SPMI_SDAM is not set\nCONFIG_OF=y\nCONFIG_OF_ADDRESS=y\nCONFIG_OF_EARLY_FLATTREE=y\nCONFIG_OF_FLATTREE=y\nCONFIG_OF_GPIO=y\nCONFIG_OF_IRQ=y\nCONFIG_OF_KOBJ=y\nCONFIG_OF_MDIO=y\nCONFIG_OF_NET=y\nCONFIG_OLD_SIGACTION=y\nCONFIG_OLD_SIGSUSPEND3=y\nCONFIG_PADATA=y\nCONFIG_PAGE_OFFSET=0xC0000000\nCONFIG_PAGE_POOL=y\nCONFIG_PCI=y\nCONFIG_PCIEAER=y\nCONFIG_PCIEPORTBUS=y\nCONFIG_PCIE_DW=y\nCONFIG_PCIE_DW_HOST=y\nCONFIG_PCIE_QCOM=y\nCONFIG_PCI_DEBUG=y\nCONFIG_PCI_DISABLE_COMMON_QUIRKS=y\nCONFIG_PCI_DOMAINS=y\nCONFIG_PCI_DOMAINS_GENERIC=y\nCONFIG_PCI_MSI=y\nCONFIG_PCI_MSI_IRQ_DOMAIN=y\nCONFIG_PCS_XPCS=y\nCONFIG_PERF_USE_VMALLOC=y\nCONFIG_PGTABLE_LEVELS=2\nCONFIG_PHYLIB=y\nCONFIG_PHYLINK=y\n# CONFIG_PHY_QCOM_APQ8064_SATA is not set\n# CONFIG_PHY_QCOM_IPQ4019_USB is not set\nCONFIG_PHY_QCOM_IPQ806X_SATA=y\n# CONFIG_PHY_QCOM_IPQ806X_USB is not set\n# CONFIG_PHY_QCOM_PCIE2 is not set\n# CONFIG_PHY_QCOM_QMP is not set\n# CONFIG_PHY_QCOM_QUSB2 is not set\n# CONFIG_PHY_QCOM_USB_HS_28NM is not set\n# CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2 is not set\n# CONFIG_PHY_QCOM_USB_SS is not set\nCONFIG_PINCTRL=y\n# CONFIG_PINCTRL_APQ8064 is not set\n# CONFIG_PINCTRL_APQ8084 is not set\n# CONFIG_PINCTRL_IPQ4019 is not set\n# CONFIG_PINCTRL_IPQ6018 is not set\nCONFIG_PINCTRL_IPQ8064=y\n# CONFIG_PINCTRL_IPQ8074 is not set\n# CONFIG_PINCTRL_MDM9615 is not set\nCONFIG_PINCTRL_MSM=y\n# CONFIG_PINCTRL_MSM8226 is not set\n# CONFIG_PINCTRL_MSM8660 is not set\n# CONFIG_PINCTRL_MSM8916 is not set\n# CONFIG_PINCTRL_MSM8960 is not set\n# CONFIG_PINCTRL_MSM8976 is not set\n# CONFIG_PINCTRL_MSM8994 is not set\n# CONFIG_PINCTRL_MSM8996 is not set\n# CONFIG_PINCTRL_MSM8998 is not set\n# CONFIG_PINCTRL_QCOM_SPMI_PMIC is not set\n# CONFIG_PINCTRL_QCOM_SSBI_PMIC is not set\n# CONFIG_PINCTRL_QCS404 is not set\n# CONFIG_PINCTRL_SC7180 is not set\n# CONFIG_PINCTRL_SDM660 is not set\n# CONFIG_PINCTRL_SDM845 is not set\n# CONFIG_PINCTRL_SM8150 is not set\n# CONFIG_PINCTRL_SM8250 is not set\nCONFIG_PM_DEVFREQ=y\n# CONFIG_PM_DEVFREQ_EVENT is not set\nCONFIG_PM_OPP=y\nCONFIG_POWER_RESET=y\nCONFIG_POWER_RESET_MSM=y\nCONFIG_POWER_SUPPLY=y\nCONFIG_PPS=y\nCONFIG_PRINTK_TIME=y\nCONFIG_PTP_1588_CLOCK=y\n# CONFIG_QCOM_A53PLL is not set\nCONFIG_QCOM_ADM=y\nCONFIG_QCOM_BAM_DMA=y\nCONFIG_QCOM_CLK_RPM=y\n# CONFIG_QCOM_COMMAND_DB is not set\n# CONFIG_QCOM_CPR is not set\n# CONFIG_QCOM_EBI2 is not set\n# CONFIG_QCOM_GENI_SE is not set\nCONFIG_QCOM_GSBI=y\nCONFIG_QCOM_HFPLL=y\n# CONFIG_QCOM_IOMMU is not set\n# CONFIG_QCOM_LLCC is not set\n# CONFIG_QCOM_OCMEM is not set\n# CONFIG_QCOM_PDC is not set\nCONFIG_QCOM_QFPROM=y\n# CONFIG_QCOM_RMTFS_MEM is not set\nCONFIG_QCOM_RPMCC=y\n# CONFIG_QCOM_RPMH is not set\nCONFIG_QCOM_SCM=y\n# CONFIG_QCOM_SCM_DOWNLOAD_MODE_DEFAULT is not set\nCONFIG_QCOM_SMEM=y\n# CONFIG_QCOM_SMSM is not set\n# CONFIG_QCOM_SOCINFO is not set\nCONFIG_QCOM_TCSR=y\nCONFIG_QCOM_TSENS=y\nCONFIG_QCOM_WDT=y\n# CONFIG_QCS_GCC_404 is not set\n# CONFIG_QCS_Q6SSTOP_404 is not set\n# CONFIG_QCS_TURING_404 is not set\nCONFIG_RAS=y\nCONFIG_RATIONAL=y\nCONFIG_REGMAP=y\nCONFIG_REGMAP_MMIO=y\nCONFIG_REGULATOR=y\nCONFIG_REGULATOR_FIXED_VOLTAGE=y\n# CONFIG_REGULATOR_QCOM_LABIBB is not set\nCONFIG_REGULATOR_QCOM_RPM=y\n# CONFIG_REGULATOR_QCOM_SPMI is not set\n# CONFIG_REGULATOR_QCOM_USB_VBUS is not set\n# CONFIG_REGULATOR_VQMMC_IPQ4019 is not set\nCONFIG_RESET_CONTROLLER=y\n# CONFIG_RESET_QCOM_AOSS is not set\n# CONFIG_RESET_QCOM_PDC is not set\nCONFIG_RFS_ACCEL=y\nCONFIG_RPS=y\nCONFIG_RTC_CLASS=y\nCONFIG_RTC_I2C_AND_SPI=y\nCONFIG_RTC_MC146818_LIB=y\nCONFIG_RWSEM_SPIN_ON_OWNER=y\n# CONFIG_SC_DISPCC_7180 is not set\n# CONFIG_SC_GCC_7180 is not set\n# CONFIG_SC_GPUCC_7180 is not set\n# CONFIG_SC_LPASS_CORECC_7180 is not set\n# CONFIG_SC_MSS_7180 is not set\n# CONFIG_SC_VIDEOCC_7180 is not set\n# CONFIG_SDM_CAMCC_845 is not set\n# CONFIG_SDM_DISPCC_845 is not set\n# CONFIG_SDM_GCC_660 is not set\n# CONFIG_SDM_GCC_845 is not set\n# CONFIG_SDM_GPUCC_845 is not set\n# CONFIG_SDM_LPASSCC_845 is not set\n# CONFIG_SDM_VIDEOCC_845 is not set\nCONFIG_SERIAL_8250_FSL=y\nCONFIG_SERIAL_MCTRL_GPIO=y\nCONFIG_SERIAL_MSM=y\nCONFIG_SERIAL_MSM_CONSOLE=y\nCONFIG_SGL_ALLOC=y\nCONFIG_SMP=y\nCONFIG_SMP_ON_UP=y\n# CONFIG_SM_GCC_8150 is not set\n# CONFIG_SM_GCC_8250 is not set\n# CONFIG_SM_GPUCC_8150 is not set\n# CONFIG_SM_GPUCC_8250 is not set\n# CONFIG_SM_VIDEOCC_8150 is not set\n# CONFIG_SM_VIDEOCC_8250 is not set\nCONFIG_SPARSE_IRQ=y\nCONFIG_SPI=y\nCONFIG_SPI_MASTER=y\nCONFIG_SPI_MEM=y\nCONFIG_SPI_QUP=y\nCONFIG_SPMI=y\n# CONFIG_SPMI_HISI3670 is not set\nCONFIG_SPMI_MSM_PMIC_ARB=y\n# CONFIG_SPMI_PMIC_CLKDIV is not set\nCONFIG_SRCU=y\nCONFIG_STMMAC_ETH=y\nCONFIG_STMMAC_PLATFORM=y\n# CONFIG_STMMAC_SELFTESTS is not set\nCONFIG_SWCONFIG=y\nCONFIG_SWCONFIG_LEDS=y\nCONFIG_SWPHY=y\nCONFIG_SWP_EMULATE=y\nCONFIG_SYS_SUPPORTS_APM_EMULATION=y\nCONFIG_THERMAL=y\nCONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y\nCONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0\nCONFIG_THERMAL_GOV_STEP_WISE=y\nCONFIG_THERMAL_HWMON=y\nCONFIG_THERMAL_OF=y\nCONFIG_TICK_CPU_ACCOUNTING=y\nCONFIG_TIMER_OF=y\nCONFIG_TIMER_PROBE=y\nCONFIG_TREE_RCU=y\nCONFIG_TREE_SRCU=y\nCONFIG_UBIFS_FS=y\nCONFIG_UBIFS_FS_ADVANCED_COMPR=y\n# CONFIG_UCLAMP_TASK is not set\nCONFIG_UEVENT_HELPER_PATH=\"\"\nCONFIG_UNCOMPRESS_INCLUDE=\"debug/uncompress.h\"\nCONFIG_UNWINDER_ARM=y\nCONFIG_USB=y\nCONFIG_USB_COMMON=y\nCONFIG_USB_SUPPORT=y\nCONFIG_USE_OF=y\nCONFIG_VFP=y\nCONFIG_VFPv3=y\nCONFIG_WATCHDOG_CORE=y\nCONFIG_XPS=y\nCONFIG_XXHASH=y\nCONFIG_XZ_DEC_ARM=y\nCONFIG_XZ_DEC_BCJ=y\nCONFIG_ZBOOT_ROM_BSS=0\nCONFIG_ZBOOT_ROM_TEXT=0\nCONFIG_ZLIB_DEFLATE=y\nCONFIG_ZLIB_INFLATE=y\nCONFIG_ZSTD_COMPRESS=y\nCONFIG_ZSTD_DECOMPRESS=y\n"
  },
  {
    "path": "target/linux/ipq806x/config-5.15",
    "content": "CONFIG_ALIGNMENT_TRAP=y\n# CONFIG_APQ_GCC_8084 is not set\n# CONFIG_APQ_MMCC_8084 is not set\nCONFIG_AR8216_PHY=y\nCONFIG_ARCH_32BIT_OFF_T=y\nCONFIG_ARCH_HIBERNATION_POSSIBLE=y\n# CONFIG_ARCH_IPQ40XX is not set\nCONFIG_ARCH_KEEP_MEMBLOCK=y\n# CONFIG_ARCH_MDM9615 is not set\nCONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y\nCONFIG_ARCH_MSM8960=y\nCONFIG_ARCH_MSM8974=y\nCONFIG_ARCH_MSM8X60=y\nCONFIG_ARCH_MULTIPLATFORM=y\nCONFIG_ARCH_MULTI_V6_V7=y\nCONFIG_ARCH_MULTI_V7=y\nCONFIG_ARCH_NR_GPIO=0\nCONFIG_ARCH_OPTIONAL_KERNEL_RWX=y\nCONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y\nCONFIG_ARCH_QCOM=y\nCONFIG_ARCH_SELECT_MEMORY_MODEL=y\nCONFIG_ARCH_SPARSEMEM_ENABLE=y\nCONFIG_ARCH_SUSPEND_POSSIBLE=y\nCONFIG_ARM=y\nCONFIG_ARM_AMBA=y\nCONFIG_ARM_APPENDED_DTB=y\nCONFIG_ARM_ARCH_TIMER=y\nCONFIG_ARM_ARCH_TIMER_EVTSTREAM=y\nCONFIG_ARM_ATAG_DTB_COMPAT=y\n# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER is not set\nCONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE=y\nCONFIG_ARM_CPUIDLE=y\nCONFIG_ARM_CPU_SUSPEND=y\n# CONFIG_ARM_CPU_TOPOLOGY is not set\nCONFIG_ARM_GIC=y\nCONFIG_ARM_HAS_SG_CHAIN=y\nCONFIG_ARM_L1_CACHE_SHIFT=6\nCONFIG_ARM_L1_CACHE_SHIFT_6=y\nCONFIG_ARM_MODULE_PLTS=y\nCONFIG_ARM_PATCH_IDIV=y\nCONFIG_ARM_PATCH_PHYS_VIRT=y\n# CONFIG_ARM_QCOM_CPUFREQ_HW is not set\nCONFIG_ARM_QCOM_CPUFREQ_KRAIT=y\nCONFIG_ARM_QCOM_CPUFREQ_NVMEM=y\nCONFIG_ARM_QCOM_SPM_CPUIDLE=y\n# CONFIG_ARM_SMMU is not set\nCONFIG_ARM_THUMB=y\nCONFIG_ARM_UNWIND=y\nCONFIG_ARM_VIRT_EXT=y\nCONFIG_AT803X_PHY=y\nCONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y\nCONFIG_BLK_DEV_LOOP=y\nCONFIG_BLK_MQ_PCI=y\nCONFIG_BOUNCE=y\n# CONFIG_CACHE_L2X0 is not set\nCONFIG_CLKSRC_QCOM=y\nCONFIG_CLONE_BACKWARDS=y\nCONFIG_CMDLINE_OVERRIDE=y\nCONFIG_COMMON_CLK=y\nCONFIG_COMMON_CLK_QCOM=y\nCONFIG_COMPAT_32BIT_TIME=y\nCONFIG_CPUFREQ_DT=y\nCONFIG_CPUFREQ_DT_PLATDEV=y\nCONFIG_CPU_32v6K=y\nCONFIG_CPU_32v7=y\nCONFIG_CPU_ABRT_EV7=y\nCONFIG_CPU_CACHE_V7=y\nCONFIG_CPU_CACHE_VIPT=y\nCONFIG_CPU_COPY_V6=y\nCONFIG_CPU_CP15=y\nCONFIG_CPU_CP15_MMU=y\nCONFIG_CPU_FREQ=y\nCONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y\n# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set\nCONFIG_CPU_FREQ_GOV_ATTR_SET=y\nCONFIG_CPU_FREQ_GOV_COMMON=y\n# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set\nCONFIG_CPU_FREQ_GOV_ONDEMAND=y\nCONFIG_CPU_FREQ_GOV_PERFORMANCE=y\n# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set\nCONFIG_CPU_FREQ_GOV_SCHEDUTIL=y\n# CONFIG_CPU_FREQ_GOV_USERSPACE is not set\nCONFIG_CPU_FREQ_STAT=y\nCONFIG_CPU_HAS_ASID=y\nCONFIG_CPU_IDLE=y\nCONFIG_CPU_IDLE_GOV_LADDER=y\nCONFIG_CPU_IDLE_GOV_MENU=y\nCONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y\nCONFIG_CPU_PABRT_V7=y\nCONFIG_CPU_PM=y\nCONFIG_CPU_RMAP=y\nCONFIG_CPU_SPECTRE=y\nCONFIG_CPU_THERMAL=y\nCONFIG_CPU_THUMB_CAPABLE=y\nCONFIG_CPU_TLB_V7=y\nCONFIG_CPU_V7=y\nCONFIG_CRC16=y\n# CONFIG_CRC32_SARWATE is not set\nCONFIG_CRC32_SLICEBY8=y\nCONFIG_CRC8=y\nCONFIG_CRYPTO_DEFLATE=y\nCONFIG_CRYPTO_DEV_QCOM_RNG=y\nCONFIG_CRYPTO_DRBG=y\nCONFIG_CRYPTO_DRBG_HMAC=y\nCONFIG_CRYPTO_DRBG_MENU=y\nCONFIG_CRYPTO_GF128MUL=y\nCONFIG_CRYPTO_HASH_INFO=y\nCONFIG_CRYPTO_HMAC=y\nCONFIG_CRYPTO_HW=y\nCONFIG_CRYPTO_JITTERENTROPY=y\nCONFIG_CRYPTO_LIB_SHA256=y\nCONFIG_CRYPTO_LZO=y\nCONFIG_CRYPTO_NULL2=y\nCONFIG_CRYPTO_RNG=y\nCONFIG_CRYPTO_RNG2=y\nCONFIG_CRYPTO_SHA256=y\nCONFIG_CRYPTO_SHA512=y\nCONFIG_CRYPTO_ZSTD=y\nCONFIG_DCACHE_WORD_ACCESS=y\nCONFIG_DEBUG_GPIO=y\nCONFIG_DEBUG_LL_INCLUDE=\"mach/debug-macro.S\"\n# CONFIG_DEVFREQ_GOV_PASSIVE is not set\n# CONFIG_DEVFREQ_GOV_PERFORMANCE is not set\n# CONFIG_DEVFREQ_GOV_POWERSAVE is not set\n# CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND is not set\n# CONFIG_DEVFREQ_GOV_USERSPACE is not set\n# CONFIG_DEVFREQ_THERMAL is not set\nCONFIG_DMADEVICES=y\nCONFIG_DMA_ENGINE=y\nCONFIG_DMA_OF=y\nCONFIG_DMA_OPS=y\nCONFIG_DMA_REMAP=y\nCONFIG_DMA_VIRTUAL_CHANNELS=y\nCONFIG_DTC=y\nCONFIG_DT_IDLE_STATES=y\n# CONFIG_DWMAC_GENERIC is not set\nCONFIG_DWMAC_IPQ806X=y\n# CONFIG_DWMAC_QCOM_ETHQOS is not set\nCONFIG_DYNAMIC_DEBUG=y\nCONFIG_EDAC_ATOMIC_SCRUB=y\nCONFIG_EDAC_SUPPORT=y\nCONFIG_FIXED_PHY=y\nCONFIG_FIX_EARLYCON_MEM=y\nCONFIG_FWNODE_MDIO=y\nCONFIG_FW_LOADER_PAGED_BUF=y\nCONFIG_GENERIC_ALLOCATOR=y\nCONFIG_GENERIC_BUG=y\nCONFIG_GENERIC_CLOCKEVENTS=y\nCONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y\nCONFIG_GENERIC_CPU_AUTOPROBE=y\nCONFIG_GENERIC_EARLY_IOREMAP=y\nCONFIG_GENERIC_GETTIMEOFDAY=y\nCONFIG_GENERIC_IDLE_POLL_SETUP=y\nCONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y\nCONFIG_GENERIC_IRQ_MULTI_HANDLER=y\nCONFIG_GENERIC_IRQ_SHOW=y\nCONFIG_GENERIC_IRQ_SHOW_LEVEL=y\nCONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y\nCONFIG_GENERIC_MSI_IRQ=y\nCONFIG_GENERIC_MSI_IRQ_DOMAIN=y\nCONFIG_GENERIC_PCI_IOMAP=y\nCONFIG_GENERIC_PHY=y\nCONFIG_GENERIC_PINCONF=y\nCONFIG_GENERIC_PINCTRL_GROUPS=y\nCONFIG_GENERIC_PINMUX_FUNCTIONS=y\nCONFIG_GENERIC_SCHED_CLOCK=y\nCONFIG_GENERIC_SMP_IDLE_THREAD=y\nCONFIG_GENERIC_STRNCPY_FROM_USER=y\nCONFIG_GENERIC_STRNLEN_USER=y\nCONFIG_GENERIC_TIME_VSYSCALL=y\nCONFIG_GENERIC_VDSO_32=y\nCONFIG_GPIOLIB=y\nCONFIG_GPIOLIB_IRQCHIP=y\nCONFIG_GPIO_CDEV=y\nCONFIG_GRO_CELLS=y\nCONFIG_HANDLE_DOMAIN_IRQ=y\nCONFIG_HARDEN_BRANCH_PREDICTOR=y\nCONFIG_HARDIRQS_SW_RESEND=y\nCONFIG_HAS_DMA=y\nCONFIG_HAS_IOMEM=y\nCONFIG_HAS_IOPORT_MAP=y\nCONFIG_HAVE_SMP=y\nCONFIG_HIGHMEM=y\n# CONFIG_HIGHPTE is not set\nCONFIG_HWMON=y\nCONFIG_HWSPINLOCK=y\nCONFIG_HWSPINLOCK_QCOM=y\nCONFIG_HW_RANDOM=y\nCONFIG_HZ_FIXED=0\nCONFIG_I2C=y\nCONFIG_I2C_BOARDINFO=y\nCONFIG_I2C_CHARDEV=y\nCONFIG_I2C_HELPER_AUTO=y\n# CONFIG_I2C_QCOM_CCI is not set\nCONFIG_I2C_QUP=y\nCONFIG_INITRAMFS_SOURCE=\"\"\n# CONFIG_IOMMU_DEBUGFS is not set\n# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set\n# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set\nCONFIG_IOMMU_SUPPORT=y\n# CONFIG_IPQ_APSS_PLL is not set\n# CONFIG_IPQ_GCC_4019 is not set\n# CONFIG_IPQ_GCC_6018 is not set\nCONFIG_IPQ_GCC_806X=y\n# CONFIG_IPQ_GCC_8074 is not set\n# CONFIG_IPQ_LCC_806X is not set\nCONFIG_IRQCHIP=y\nCONFIG_IRQ_DOMAIN=y\nCONFIG_IRQ_DOMAIN_HIERARCHY=y\nCONFIG_IRQ_FASTEOI_HIERARCHY_HANDLERS=y\nCONFIG_IRQ_FORCED_THREADING=y\nCONFIG_IRQ_WORK=y\nCONFIG_KMAP_LOCAL=y\nCONFIG_KPSS_XCC=y\nCONFIG_KRAITCC=y\nCONFIG_KRAIT_CLOCKS=y\nCONFIG_KRAIT_L2_ACCESSORS=y\nCONFIG_LIBFDT=y\nCONFIG_LLD_VERSION=0\nCONFIG_LOCK_DEBUGGING_SUPPORT=y\nCONFIG_LOCK_SPIN_ON_OWNER=y\nCONFIG_LZO_COMPRESS=y\nCONFIG_LZO_DECOMPRESS=y\nCONFIG_MDIO_BITBANG=y\nCONFIG_MDIO_BUS=y\nCONFIG_MDIO_DEVICE=y\nCONFIG_MDIO_DEVRES=y\nCONFIG_MDIO_GPIO=y\nCONFIG_MDIO_IPQ8064=y\n# CONFIG_MDM_GCC_9615 is not set\n# CONFIG_MDM_LCC_9615 is not set\nCONFIG_MEMFD_CREATE=y\n# CONFIG_MFD_HI6421_SPMI is not set\nCONFIG_MFD_QCOM_RPM=y\n# CONFIG_MFD_SPMI_PMIC is not set\nCONFIG_MFD_SYSCON=y\nCONFIG_MIGHT_HAVE_CACHE_L2X0=y\nCONFIG_MIGRATION=y\nCONFIG_MMC=y\nCONFIG_MMC_ARMMMCI=y\nCONFIG_MMC_BLOCK=y\nCONFIG_MMC_BLOCK_MINORS=16\nCONFIG_MMC_CQHCI=y\nCONFIG_MMC_QCOM_DML=y\nCONFIG_MMC_SDHCI=y\nCONFIG_MMC_SDHCI_IO_ACCESSORS=y\nCONFIG_MMC_SDHCI_MSM=y\n# CONFIG_MMC_SDHCI_PCI is not set\nCONFIG_MMC_SDHCI_PLTFM=y\nCONFIG_MODULES_USE_ELF_REL=y\nCONFIG_MSM_GCC_8660=y\n# CONFIG_MSM_GCC_8916 is not set\n# CONFIG_MSM_GCC_8939 is not set\n# CONFIG_MSM_GCC_8960 is not set\n# CONFIG_MSM_GCC_8974 is not set\n# CONFIG_MSM_GCC_8994 is not set\n# CONFIG_MSM_GCC_8996 is not set\n# CONFIG_MSM_GCC_8998 is not set\n# CONFIG_MSM_GPUCC_8998 is not set\n# CONFIG_MSM_IOMMU is not set\n# CONFIG_MSM_LCC_8960 is not set\n# CONFIG_MSM_MMCC_8960 is not set\n# CONFIG_MSM_MMCC_8974 is not set\n# CONFIG_MSM_MMCC_8996 is not set\n# CONFIG_MSM_MMCC_8998 is not set\nCONFIG_MTD_CMDLINE_PARTS=y\nCONFIG_MTD_NAND_CORE=y\nCONFIG_MTD_NAND_ECC=y\nCONFIG_MTD_NAND_ECC_SW_HAMMING=y\nCONFIG_MTD_NAND_QCOM=y\nCONFIG_MTD_QCOMSMEM_PARTS=y\nCONFIG_MTD_RAW_NAND=y\nCONFIG_MTD_SPI_NOR=y\nCONFIG_MTD_SPLIT_FIRMWARE=y\nCONFIG_MTD_SPLIT_FIT_FW=y\nCONFIG_MTD_SPLIT_UIMAGE_FW=y\nCONFIG_MTD_UBI=y\nCONFIG_MTD_UBI_BEB_LIMIT=20\nCONFIG_MTD_UBI_BLOCK=y\nCONFIG_MTD_UBI_WL_THRESHOLD=4096\nCONFIG_MUTEX_SPIN_ON_OWNER=y\nCONFIG_NEED_DMA_MAP_STATE=y\nCONFIG_NEON=y\nCONFIG_NET_DEVLINK=y\nCONFIG_NET_DSA=y\nCONFIG_NET_DSA_QCA8K=y\nCONFIG_NET_DSA_TAG_QCA=y\nCONFIG_NET_FLOW_LIMIT=y\nCONFIG_NET_PTP_CLASSIFY=y\nCONFIG_NET_SELFTESTS=y\nCONFIG_NET_SWITCHDEV=y\nCONFIG_NLS=y\nCONFIG_NO_HZ=y\nCONFIG_NO_HZ_COMMON=y\nCONFIG_NO_HZ_IDLE=y\nCONFIG_NR_CPUS=2\nCONFIG_NVMEM=y\n# CONFIG_NVMEM_SPMI_SDAM is not set\nCONFIG_OF=y\nCONFIG_OF_ADDRESS=y\nCONFIG_OF_EARLY_FLATTREE=y\nCONFIG_OF_FLATTREE=y\nCONFIG_OF_GPIO=y\nCONFIG_OF_IRQ=y\nCONFIG_OF_KOBJ=y\nCONFIG_OF_MDIO=y\nCONFIG_OF_NET=y\nCONFIG_OLD_SIGACTION=y\nCONFIG_OLD_SIGSUSPEND3=y\nCONFIG_PADATA=y\nCONFIG_PAGE_OFFSET=0xC0000000\nCONFIG_PAGE_POOL=y\nCONFIG_PCI=y\nCONFIG_PCIEAER=y\nCONFIG_PCIEPORTBUS=y\nCONFIG_PCIE_DW=y\nCONFIG_PCIE_DW_HOST=y\nCONFIG_PCIE_QCOM=y\nCONFIG_PCI_DEBUG=y\nCONFIG_PCI_DISABLE_COMMON_QUIRKS=y\nCONFIG_PCI_DOMAINS=y\nCONFIG_PCI_DOMAINS_GENERIC=y\nCONFIG_PCI_MSI=y\nCONFIG_PCI_MSI_IRQ_DOMAIN=y\nCONFIG_PCS_XPCS=y\nCONFIG_PERF_USE_VMALLOC=y\nCONFIG_PGTABLE_LEVELS=2\nCONFIG_PHYLIB=y\nCONFIG_PHYLINK=y\n# CONFIG_PHY_QCOM_APQ8064_SATA is not set\n# CONFIG_PHY_QCOM_IPQ4019_USB is not set\nCONFIG_PHY_QCOM_IPQ806X_SATA=y\n# CONFIG_PHY_QCOM_IPQ806X_USB is not set\n# CONFIG_PHY_QCOM_PCIE2 is not set\n# CONFIG_PHY_QCOM_QMP is not set\n# CONFIG_PHY_QCOM_QUSB2 is not set\n# CONFIG_PHY_QCOM_USB_HS_28NM is not set\n# CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2 is not set\n# CONFIG_PHY_QCOM_USB_SS is not set\nCONFIG_PINCTRL=y\n# CONFIG_PINCTRL_APQ8064 is not set\n# CONFIG_PINCTRL_APQ8084 is not set\n# CONFIG_PINCTRL_IPQ4019 is not set\n# CONFIG_PINCTRL_IPQ6018 is not set\nCONFIG_PINCTRL_IPQ8064=y\n# CONFIG_PINCTRL_IPQ8074 is not set\n# CONFIG_PINCTRL_MDM9615 is not set\nCONFIG_PINCTRL_MSM=y\n# CONFIG_PINCTRL_MSM8226 is not set\n# CONFIG_PINCTRL_MSM8660 is not set\n# CONFIG_PINCTRL_MSM8916 is not set\n# CONFIG_PINCTRL_MSM8960 is not set\n# CONFIG_PINCTRL_MSM8976 is not set\n# CONFIG_PINCTRL_MSM8994 is not set\n# CONFIG_PINCTRL_MSM8996 is not set\n# CONFIG_PINCTRL_MSM8998 is not set\n# CONFIG_PINCTRL_QCOM_SPMI_PMIC is not set\n# CONFIG_PINCTRL_QCOM_SSBI_PMIC is not set\n# CONFIG_PINCTRL_QCS404 is not set\n# CONFIG_PINCTRL_SC7180 is not set\n# CONFIG_PINCTRL_SDM660 is not set\n# CONFIG_PINCTRL_SDM845 is not set\n# CONFIG_PINCTRL_SM8150 is not set\n# CONFIG_PINCTRL_SM8250 is not set\nCONFIG_PM_DEVFREQ=y\n# CONFIG_PM_DEVFREQ_EVENT is not set\nCONFIG_PM_OPP=y\nCONFIG_POWER_RESET=y\nCONFIG_POWER_RESET_MSM=y\nCONFIG_POWER_SUPPLY=y\nCONFIG_PPS=y\nCONFIG_PRINTK_TIME=y\nCONFIG_PTP_1588_CLOCK=y\nCONFIG_PTP_1588_CLOCK_OPTIONAL=y\n# CONFIG_QCOM_A53PLL is not set\nCONFIG_QCOM_ADM=y\nCONFIG_QCOM_BAM_DMA=y\nCONFIG_QCOM_CLK_RPM=y\n# CONFIG_QCOM_COMMAND_DB is not set\n# CONFIG_QCOM_CPR is not set\n# CONFIG_QCOM_EBI2 is not set\n# CONFIG_QCOM_GENI_SE is not set\nCONFIG_QCOM_GSBI=y\nCONFIG_QCOM_HFPLL=y\n# CONFIG_QCOM_IOMMU is not set\n# CONFIG_QCOM_LLCC is not set\n# CONFIG_QCOM_OCMEM is not set\n# CONFIG_QCOM_PDC is not set\nCONFIG_QCOM_QFPROM=y\n# CONFIG_QCOM_RMTFS_MEM is not set\nCONFIG_QCOM_RPMCC=y\n# CONFIG_QCOM_RPMH is not set\nCONFIG_QCOM_SCM=y\n# CONFIG_QCOM_SCM_DOWNLOAD_MODE_DEFAULT is not set\nCONFIG_QCOM_SMEM=y\n# CONFIG_QCOM_SMSM is not set\n# CONFIG_QCOM_SOCINFO is not set\nCONFIG_QCOM_TCSR=y\nCONFIG_QCOM_TSENS=y\nCONFIG_QCOM_WDT=y\n# CONFIG_QCS_GCC_404 is not set\n# CONFIG_QCS_Q6SSTOP_404 is not set\n# CONFIG_QCS_TURING_404 is not set\nCONFIG_RAS=y\nCONFIG_RATIONAL=y\nCONFIG_RCU_CPU_STALL_TIMEOUT=21\nCONFIG_REGMAP=y\nCONFIG_REGMAP_MMIO=y\nCONFIG_REGULATOR=y\nCONFIG_REGULATOR_FIXED_VOLTAGE=y\n# CONFIG_REGULATOR_QCOM_LABIBB is not set\nCONFIG_REGULATOR_QCOM_RPM=y\n# CONFIG_REGULATOR_QCOM_SPMI is not set\n# CONFIG_REGULATOR_QCOM_USB_VBUS is not set\n# CONFIG_REGULATOR_VQMMC_IPQ4019 is not set\nCONFIG_RESET_CONTROLLER=y\n# CONFIG_RESET_QCOM_AOSS is not set\n# CONFIG_RESET_QCOM_PDC is not set\nCONFIG_RFS_ACCEL=y\nCONFIG_RPS=y\nCONFIG_RTC_CLASS=y\nCONFIG_RTC_I2C_AND_SPI=y\nCONFIG_RTC_MC146818_LIB=y\nCONFIG_RWSEM_SPIN_ON_OWNER=y\n# CONFIG_SC_DISPCC_7180 is not set\n# CONFIG_SC_GCC_7180 is not set\n# CONFIG_SC_GPUCC_7180 is not set\n# CONFIG_SC_LPASS_CORECC_7180 is not set\n# CONFIG_SC_MSS_7180 is not set\n# CONFIG_SC_VIDEOCC_7180 is not set\n# CONFIG_SDM_CAMCC_845 is not set\n# CONFIG_SDM_DISPCC_845 is not set\n# CONFIG_SDM_GCC_660 is not set\n# CONFIG_SDM_GCC_845 is not set\n# CONFIG_SDM_GPUCC_845 is not set\n# CONFIG_SDM_LPASSCC_845 is not set\n# CONFIG_SDM_VIDEOCC_845 is not set\nCONFIG_SERIAL_8250_FSL=y\nCONFIG_SERIAL_MCTRL_GPIO=y\nCONFIG_SERIAL_MSM=y\nCONFIG_SERIAL_MSM_CONSOLE=y\nCONFIG_SGL_ALLOC=y\nCONFIG_SMP=y\nCONFIG_SMP_ON_UP=y\n# CONFIG_SM_GCC_8150 is not set\n# CONFIG_SM_GCC_8250 is not set\n# CONFIG_SM_GPUCC_8150 is not set\n# CONFIG_SM_GPUCC_8250 is not set\n# CONFIG_SM_VIDEOCC_8150 is not set\n# CONFIG_SM_VIDEOCC_8250 is not set\nCONFIG_SOCK_RX_QUEUE_MAPPING=y\nCONFIG_SPARSE_IRQ=y\nCONFIG_SPI=y\nCONFIG_SPI_MASTER=y\nCONFIG_SPI_MEM=y\nCONFIG_SPI_QUP=y\nCONFIG_SPMI=y\n# CONFIG_SPMI_HISI3670 is not set\nCONFIG_SPMI_MSM_PMIC_ARB=y\n# CONFIG_SPMI_PMIC_CLKDIV is not set\nCONFIG_SRCU=y\nCONFIG_STMMAC_ETH=y\nCONFIG_STMMAC_PLATFORM=y\nCONFIG_SWCONFIG=y\nCONFIG_SWCONFIG_LEDS=y\nCONFIG_SWPHY=y\nCONFIG_SWP_EMULATE=y\nCONFIG_SYS_SUPPORTS_APM_EMULATION=y\nCONFIG_THERMAL=y\nCONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y\nCONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0\nCONFIG_THERMAL_GOV_STEP_WISE=y\nCONFIG_THERMAL_HWMON=y\nCONFIG_THERMAL_OF=y\nCONFIG_TICK_CPU_ACCOUNTING=y\nCONFIG_TIMER_OF=y\nCONFIG_TIMER_PROBE=y\nCONFIG_TREE_RCU=y\nCONFIG_TREE_SRCU=y\nCONFIG_UBIFS_FS=y\nCONFIG_UBIFS_FS_ADVANCED_COMPR=y\n# CONFIG_UCLAMP_TASK is not set\nCONFIG_UEVENT_HELPER_PATH=\"\"\nCONFIG_UNCOMPRESS_INCLUDE=\"debug/uncompress.h\"\nCONFIG_UNWINDER_ARM=y\nCONFIG_USB=y\nCONFIG_USB_COMMON=y\nCONFIG_USB_SUPPORT=y\nCONFIG_USE_OF=y\nCONFIG_VFP=y\nCONFIG_VFPv3=y\nCONFIG_WATCHDOG_CORE=y\nCONFIG_XPS=y\nCONFIG_XXHASH=y\nCONFIG_XZ_DEC_ARM=y\nCONFIG_XZ_DEC_BCJ=y\nCONFIG_ZBOOT_ROM_BSS=0\nCONFIG_ZBOOT_ROM_TEXT=0\nCONFIG_ZLIB_DEFLATE=y\nCONFIG_ZLIB_INFLATE=y\nCONFIG_ZSTD_COMPRESS=y\nCONFIG_ZSTD_DECOMPRESS=y\n"
  },
  {
    "path": "target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8062-wg2600hp3.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qcom-ipq8062.dtsi\"\n#include <dt-bindings/input/input.h>\n\n/delete-node/ &nand_pins;\n\n/ {\n\tmodel = \"NEC Platforms Aterm WG2600HP3\";\n\tcompatible = \"nec,wg2600hp3\", \"qcom,ipq8062\", \"qcom,ipq8064\";\n\n\tmemory {\n\t\tdevice_type = \"memory\";\n\t\treg =  <0x42000000 0x1e000000>;\n\t};\n\n\taliases {\n\t\tlabel-mac-device = &gmac2;\n\n\t\tled-boot = &led_power_green;\n\t\tled-failsafe = &led_power_red;\n\t\tled-running = &led_power_green;\n\t\tled-upgrade = &led_power_red;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\tpinctrl-0 = <&buttons_pins>;\n\t\tpinctrl-names = \"default\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&qcom_pinmux 24 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tdebounce-interval = <60>;\n\t\t\twakeup-source;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&qcom_pinmux 22 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tdebounce-interval = <60>;\n\t\t\twakeup-source;\n\t\t};\n\n\t\tmode0 {\n\t\t\tlabel = \"mode0\";\n\t\t\tgpios = <&qcom_pinmux 40 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_0>;\n\t\t\tlinux,input-type = <EV_SW>;\n\t\t\tdebounce-interval = <60>;\n\t\t\twakeup-source;\n\t\t};\n\n\t\tmode1 {\n\t\t\tlabel = \"mode1\";\n\t\t\tgpios = <&qcom_pinmux 41 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_1>;\n\t\t\tlinux,input-type = <EV_SW>;\n\t\t\tdebounce-interval = <60>;\n\t\t\twakeup-source;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tpinctrl-0 = <&leds_pins>;\n\t\tpinctrl-names = \"default\";\n\n\t\tled_power_green: power_green {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&qcom_pinmux 14 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tled_power_red: power_red {\n\t\t\tlabel = \"red:power\";\n\t\t\tgpios = <&qcom_pinmux 35 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tactive_green {\n\t\t\tlabel = \"green:active\";\n\t\t\tgpios = <&qcom_pinmux 42 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tactive_red {\n\t\t\tlabel = \"red:active\";\n\t\t\tgpios = <&qcom_pinmux 38 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\twlan2g_green {\n\t\t\tlabel = \"green:wlan2g\";\n\t\t\tgpios = <&qcom_pinmux 55 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\n\t\twlan2g_red {\n\t\t\tlabel = \"red:wlan2g\";\n\t\t\tgpios = <&qcom_pinmux 56 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\twlan5g_green {\n\t\t\tlabel = \"green:wlan5g\";\n\t\t\tgpios = <&qcom_pinmux 57 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\twlan5g_red {\n\t\t\tlabel = \"red:wlan5g\";\n\t\t\tgpios = <&qcom_pinmux 58 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\ttv_green {\n\t\t\tlabel = \"green:tv\";\n\t\t\tgpios = <&qcom_pinmux 46 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\ttv_red {\n\t\t\tlabel = \"red:tv\";\n\t\t\tgpios = <&qcom_pinmux 36 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tconverter_green {\n\t\t\tlabel = \"green:converter\";\n\t\t\tgpios = <&qcom_pinmux 43 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tconverter_red {\n\t\t\tlabel = \"red:converter\";\n\t\t\tgpios = <&qcom_pinmux 15 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&qcom_pinmux {\n\tpinctrl-0 = <&akro_pins>;\n\tpinctrl-names = \"default\";\n\n\tspi_pins: spi_pins {\n\t\tmux {\n\t\t\tpins = \"gpio18\", \"gpio19\", \"gpio21\";\n\t\t\tfunction = \"gsbi5\";\n\t\t\tbias-pull-down;\n\t\t};\n\n\t\tdata {\n\t\t\tpins = \"gpio18\", \"gpio19\";\n\t\t\tdrive-strength = <10>;\n\t\t};\n\n\t\tcs {\n\t\t\tpins = \"gpio20\";\n\t\t\tdrive-strength = <10>;\n\t\t};\n\n\t\tclk {\n\t\t\tpins = \"gpio21\";\n\t\t\tdrive-strength = <12>;\n\t\t};\n\t};\n\n\tbuttons_pins: buttons_pins {\n\t\tmux {\n\t\t\tpins = \"gpio22\", \"gpio24\", \"gpio40\",\n\t\t\t\t\"gpio41\";\n\t\t\tfunction = \"gpio\";\n\t\t\tdrive-strength = <2>;\n\t\t\tbias-pull-up;\n\t\t};\n\t};\n\n\tleds_pins: leds_pins {\n\t\tmux {\n\t\t\tpins = \"gpio14\", \"gpio15\", \"gpio35\",\n\t\t\t\t\"gpio36\", \"gpio38\", \"gpio42\",\n\t\t\t\t\"gpio43\", \"gpio46\", \"gpio55\",\n\t\t\t\t\"gpio56\", \"gpio57\", \"gpio58\";\n\t\t\tfunction = \"gpio\";\n\t\t\tbias-pull-down;\n\t\t};\n\n\t\takro2 {\n\t\t\tpins = \"gpio15\", \"gpio35\", \"gpio38\",\n\t\t\t\t\"gpio42\", \"gpio43\", \"gpio46\",\n\t\t\t\t\"gpio55\", \"gpio56\", \"gpio57\",\n\t\t\t\t\"gpio58\";\n\t\t\tdrive-strength = <2>;\n\t\t};\n\n\t\takro4 {\n\t\t\tpins = \"gpio14\", \"gpio36\";\n\t\t\tdrive-strength = <4>;\n\t\t};\n\t};\n\n\t/*\n\t * Stock firmware has the following settings, so let's do the same.\n\t * I don't sure why these are required.\n\t */\n\takro_pins: akro_pinmux {\n\t\takro {\n\t\t\tpins = \"gpio17\", \"gpio26\", \"gpio47\";\n\t\t\tfunction = \"gpio\";\n\t\t\tdrive-strength = <2>;\n\t\t\tbias-pull-down;\n\t\t};\n\n\t\treset {\n\t\t\tpins = \"gpio45\";\n\t\t\tfunction = \"gpio\";\n\t\t\tdrive-strength = <2>;\n\t\t\tbias-disable;\n\t\t\toutput-low;\n\t\t};\n\n\t\tgmac0_rgmii {\n\t\t\tpins = \"gpio25\";\n\t\t\tfunction = \"gpio\";\n\t\t\tdrive-strength = <8>;\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&gsbi5 {\n\tstatus = \"okay\";\n\tqcom,mode = <GSBI_PROT_SPI>;\n\n\tspi@1a280000 {\n\t\tstatus = \"okay\";\n\n\t\tpinctrl-0 = <&spi_pins>;\n\t\tpinctrl-names = \"default\";\n\n\t\tcs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>;\n\n\t\tflash@0 {\n\t\t\tcompatible = \"jedec,spi-nor\";\n\t\t\treg = <0>;\n\t\t\tspi-max-frequency = <50000000>;\n\t\t\tm25p,fast-read;\n\n\t\t\tpartitions {\n\t\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\n\t\t\t\tpartition@0 {\n\t\t\t\t\tlabel = \"SBL1\";\n\t\t\t\t\treg = <0x0000000 0x0020000>;\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\tpartition@20000 {\n\t\t\t\t\tlabel = \"MIBIB\";\n\t\t\t\t\treg = <0x0020000 0x0020000>;\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\tpartition@40000 {\n\t\t\t\t\tlabel = \"SBL2\";\n\t\t\t\t\treg = <0x0040000 0x0040000>;\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\tpartition@80000 {\n\t\t\t\t\tlabel = \"SBL3\";\n\t\t\t\t\treg = <0x0080000 0x0080000>;\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\tpartition@100000 {\n\t\t\t\t\tlabel = \"DDRCONFIG\";\n\t\t\t\t\treg = <0x0100000 0x0010000>;\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\tpartition@110000 {\n\t\t\t\t\tlabel = \"SSD\";\n\t\t\t\t\treg = <0x0110000 0x0010000>;\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\tpartition@120000 {\n\t\t\t\t\tlabel = \"TZ\";\n\t\t\t\t\treg = <0x0120000 0x0080000>;\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\tpartition@1a0000 {\n\t\t\t\t\tlabel = \"RPM\";\n\t\t\t\t\treg = <0x01a0000 0x0080000>;\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\tpartition@220000 {\n\t\t\t\t\tlabel = \"APPSBL\";\n\t\t\t\t\treg = <0x0220000 0x0080000>;\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\tpartition@2a0000 {\n\t\t\t\t\tlabel = \"APPSBLENV\";\n\t\t\t\t\treg = <0x02a0000 0x0010000>;\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\tfactory: partition@2b0000 {\n\t\t\t\t\tlabel = \"PRODUCTDATA\";\n\t\t\t\t\treg = <0x02b0000 0x0030000>;\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\tpartition@2e0000 {\n\t\t\t\t\tlabel = \"ART\";\n\t\t\t\t\treg = <0x02e0000 0x0040000>;\n\t\t\t\t\tread-only;\n\t\t\t\t\tcompatible = \"nvmem-cells\";\n\t\t\t\t\t#address-cells = <1>;\n\t\t\t\t\t#size-cells = <1>;\n\n\t\t\t\t\tprecal_ART_1000: precal@1000 {\n\t\t\t\t\t\treg = <0x1000 0x2f20>;\n\t\t\t\t\t};\n\n\t\t\t\t\tprecal_ART_5000: precal@5000 {\n\t\t\t\t\t\treg = <0x5000 0x2f20>;\n\t\t\t\t\t};\n\t\t\t\t};\n\n\t\t\t\tpartition@320000 {\n\t\t\t\t\tlabel = \"TP\";\n\t\t\t\t\treg = <0x0320000 0x0040000>;\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\tpartition@360000 {\n\t\t\t\t\tlabel = \"TINY\";\n\t\t\t\t\treg = <0x0360000 0x0500000>;\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\tpartition@860000 {\n\t\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\t\tlabel = \"firmware\";\n\t\t\t\t\treg = <0x0860000 0x17a0000>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t};\n};\n\n&adm_dma {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\tstatus = \"okay\";\n\n\tbridge@0,0 {\n\t\treg = <0x00000000 0 0 0 0>;\n\t\t#address-cells = <3>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\twifi@1,0 {\n\t\t\tcompatible = \"qcom,ath10k\";\n\t\t\treg = <0x00010000 0 0 0 0>;\n\n\t\t\tqcom,ath10k-calibration-variant = \"NEC-Platforms-WG2600HP3\";\n\n\t\t\tnvmem-cells = <&macaddr_PRODUCTDATA_12>, <&precal_ART_1000>;\n\t\t\tnvmem-cell-names = \"mac-address\", \"pre-calibration\";\n\t\t};\n\t};\n};\n\n&pcie1 {\n\tstatus = \"okay\";\n\tforce_gen1 = <1>;\n\n\tbridge@0,0 {\n\t\treg = <0x00000000 0 0 0 0>;\n\t\t#address-cells = <3>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\twifi@1,0 {\n\t\t\tcompatible = \"qcom,ath10k\";\n\t\t\treg = <0x00010000 0 0 0 0>;\n\n\t\t\tieee80211-freq-limit = <2400000 2483000>;\n\t\t\tqcom,ath10k-calibration-variant = \"NEC-Platforms-WG2600HP3\";\n\n\t\t\tnvmem-cells = <&macaddr_PRODUCTDATA_c>, <&precal_ART_5000>;\n\t\t\tnvmem-cell-names = \"mac-address\", \"pre-calibration\";\n\t\t};\n\t};\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tpinctrl-0 = <&mdio0_pins>;\n\tpinctrl-names = \"default\";\n\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t\tqca,ar8327-initvals = <\n\t\t\t0x04 0x80080080  /* PAD0_MODE */\n\t\t\t0x0c 0x06000000  /* PAD6_MODE */\n\t\t\t0x10 0x002613a0  /* PWS_REG */\n\t\t\t0x50 0xcc36cc36  /* LED_CTRL0 */\n\t\t\t0x54 0xca36ca36  /* LED_CTRL1 */\n\t\t\t0x58 0xc936c936  /* LED_CTRL2 */\n\t\t\t0x5c 0x03ffff00  /* LED_CTRL3 */\n\t\t\t0x7c 0x0000004e  /* PORT0_STATUS */\n\t\t\t0x94 0x0000004e  /* PORT6_STATUS */\n\t\t\t0xe0 0xc74164de  /* SGMII_CTRL */\n\t\t\t0xe4 0x0006a545  /* MAC_PWR_SEL */\n\t\t\t>;\n\t};\n};\n\n&gmac1 {\n\tstatus = \"okay\";\n\n\tpinctrl-0 = <&rgmii2_pins>;\n\tpinctrl-names = \"default\";\n\n\tphy-mode = \"rgmii\";\n\tqcom,id = <1>;\n\tmdiobus = <&mdio0>;\n\tnvmem-cells = <&macaddr_factory_0>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tfixed-link {\n\t\tspeed = <1000>;\n\t\tfull-duplex;\n\t};\n};\n\n&gmac2 {\n\tstatus = \"okay\";\n\tphy-mode = \"sgmii\";\n\tqcom,id = <2>;\n\tmdiobus = <&mdio0>;\n\tnvmem-cells = <&macaddr_factory_6>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tfixed-link {\n\t\tspeed = <1000>;\n\t\tfull-duplex;\n\t};\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n\n\tmacaddr_factory_6: macaddr@6 {\n\t\treg = <0x6 0x6>;\n\t};\n\n\tmacaddr_PRODUCTDATA_c: macaddr@c {\n\t\treg = <0xc 0x6>;\n\t};\n\n\tmacaddr_PRODUCTDATA_12: macaddr@12 {\n\t\treg = <0x12 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8062.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-only\n\n#include \"qcom-ipq8064.dtsi\"\n\n/ {\n\tmodel = \"Qualcomm IPQ8062\";\n\tcompatible = \"qcom,ipq8062\", \"qcom,ipq8064\";\n\n\taliases {\n\t\tserial0 = &gsbi4_serial;\n\t};\n\n\tchosen {\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\treserved-memory {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tranges;\n\n\t\trsvd@41200000 {\n\t\t\treg = <0x41200000 0x300000>;\n\t\t\tno-map;\n\t\t};\n\t};\n};\n\n&gsbi4 {\n\tqcom,mode = <GSBI_PROT_I2C_UART>;\n\tstatus = \"okay\";\n\n\tserial@16340000 {\n\t\tstatus = \"okay\";\n\t};\n\t/*\n\t* The i2c device on gsbi4 should not be enabled.\n\t* On ipq806x designs gsbi4 i2c is meant for exclusive\n\t* RPM usage. Turning this on in kernel manifests as\n\t* i2c failure for the RPM.\n\t*/\n};\n\n&opp_table0 {\n\t/delete-node/opp-1200000000;\n\t/delete-node/opp-1400000000;\n\n\t/*\n\t * Voltage thresholds are <target min max>\n\t */\n\topp-384000000 {\n\t\topp-microvolt-speed0-pvs0-v0 = <1000000 950000 1050000>;\n\t\topp-microvolt-speed0-pvs1-v0 = < 925000 878750  971250>;\n\t\topp-microvolt-speed0-pvs2-v0 = < 875000 831250  918750>;\n\t\topp-microvolt-speed0-pvs3-v0 = < 800000 760000  840000>;\n\t};\n\n\topp-600000000 {\n\t\topp-microvolt-speed0-pvs0-v0 = <1050000 997500 1102500>;\n\t\topp-microvolt-speed0-pvs1-v0 = < 975000 926250 1023750>;\n\t\topp-microvolt-speed0-pvs2-v0 = < 925000 878750  971250>;\n\t\topp-microvolt-speed0-pvs3-v0 = < 850000 807500  892500>;\n\t};\n\n\topp-800000000 {\n\t\topp-microvolt-speed0-pvs0-v0 = <1100000 1045000 1155000>;\n\t\topp-microvolt-speed0-pvs1-v0 = <1025000  973750 1076250>;\n\t\topp-microvolt-speed0-pvs2-v0 = < 995000  945250 1044750>;\n\t\topp-microvolt-speed0-pvs3-v0 = < 900000  855000  945000>;\n\t};\n\n\topp-1000000000 {\n\t\topp-microvolt-speed0-pvs0-v0 = <1150000 1092500 1207500>;\n\t\topp-microvolt-speed0-pvs1-v0 = <1075000 1021250 1128750>;\n\t\topp-microvolt-speed0-pvs2-v0 = <1025000  973750 1076250>;\n\t\topp-microvolt-speed0-pvs3-v0 = < 950000  902500  997500>;\n\t};\n};\n\n&pcie0 {\n\tcompatible = \"qcom,pcie-ipq8064-v2\";\n};\n\n&pcie1 {\n\tcompatible = \"qcom,pcie-ipq8064-v2\";\n};\n\n&pcie2 {\n\tcompatible = \"qcom,pcie-ipq8064-v2\";\n};\n\n&smb208_s2a {\n\tregulator-max-microvolt = <1150000>;\n};\n\n&smb208_s2b {\n\tregulator-max-microvolt = <1150000>;\n};\n"
  },
  {
    "path": "target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-ad7200-c2600.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qcom-ipq8064-v2.0.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmemory@0 {\n\t\treg = <0x42000000 0x1e000000>;\n\t\tdevice_type = \"memory\";\n\t};\n\n\taliases {\n\t\tmdio-gpio0 = &mdio0;\n\t\tlabel-mac-device = &gmac2;\n\t};\n};\n\n&qcom_pinmux {\n\tspi_pins: spi_pins {\n\t\tmux {\n\t\t\tpins = \"gpio18\", \"gpio19\", \"gpio21\";\n\t\t\tfunction = \"gsbi5\";\n\t\t\tbias-pull-down;\n\t\t};\n\n\t\tdata {\n\t\t\tpins = \"gpio18\", \"gpio19\";\n\t\t\tdrive-strength = <10>;\n\t\t};\n\n\t\tcs {\n\t\t\tpins = \"gpio20\";\n\t\t\tfunction = \"gpio\";\n\t\t\tdrive-strength = <10>;\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tclk {\n\t\t\tpins = \"gpio21\";\n\t\t\tdrive-strength = <12>;\n\t\t};\n\t};\n\n\tusb0_pwr_en_pin: usb0_pwr_en_pin {\n\t\tmux {\n\t\t\tpins = \"gpio25\";\n\t\t\tfunction = \"gpio\";\n\t\t\tdrive-strength = <10>;\n\t\t\tbias-pull-up;\n\t\t\toutput-high;\n\t\t};\n\t};\n\n\tusb1_pwr_en_pin: usb1_pwr_en_pin {\n\t\tmux {\n\t\t\tpins = \"gpio23\";\n\t\t\tfunction = \"gpio\";\n\t\t\tdrive-strength = <10>;\n\t\t\tbias-pull-up;\n\t\t\toutput-high;\n\t\t};\n\t};\n};\n\n&gsbi5 {\n\tqcom,mode = <GSBI_PROT_SPI>;\n\tstatus = \"okay\";\n\n\tspi@1a280000 {\n\t\tstatus = \"okay\";\n\n\t\tpinctrl-0 = <&spi_pins>;\n\t\tpinctrl-names = \"default\";\n\n\t\tcs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>;\n\n\t\tflash@0 {\n\t\t\tcompatible = \"jedec,spi-nor\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\t\t\tspi-max-frequency = <50000000>;\n\t\t\treg = <0>;\n\n\t\t\tpartitions {\n\t\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\n\t\t\t\tpartition@0 {\n\t\t\t\t\tlabel = \"SBL1\";\n\t\t\t\t\treg = <0x0 0x20000>;\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\tpartition@20000 {\n\t\t\t\t\tlabel = \"MIBIB\";\n\t\t\t\t\treg = <0x20000 0x20000>;\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\tpartition@40000 {\n\t\t\t\t\tlabel = \"SBL2\";\n\t\t\t\t\treg = <0x40000 0x20000>;\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\tpartition@60000 {\n\t\t\t\t\tlabel = \"SBL3\";\n\t\t\t\t\treg = <0x60000 0x30000>;\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\tpartition@90000 {\n\t\t\t\t\tlabel = \"DDRCONFIG\";\n\t\t\t\t\treg = <0x90000 0x10000>;\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\tpartition@a0000 {\n\t\t\t\t\tlabel = \"SSD\";\n\t\t\t\t\treg = <0xa0000 0x10000>;\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\tpartition@b0000 {\n\t\t\t\t\tlabel = \"TZ\";\n\t\t\t\t\treg = <0xb0000 0x30000>;\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\tpartition@e0000 {\n\t\t\t\t\tlabel = \"RPM\";\n\t\t\t\t\treg = <0xe0000 0x20000>;\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\tpartition@100000 {\n\t\t\t\t\tlabel = \"fs-uboot\";\n\t\t\t\t\treg = <0x100000 0x70000>;\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\tpartition@170000 {\n\t\t\t\t\tlabel = \"uboot-env\";\n\t\t\t\t\treg = <0x170000 0x40000>;\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\tpartition@1b0000 {\n\t\t\t\t\tlabel = \"radio\";\n\t\t\t\t\treg = <0x1b0000 0x40000>;\n\t\t\t\t\tread-only;\n\t\t\t\t\tcompatible = \"nvmem-cells\";\n\t\t\t\t\t#address-cells = <1>;\n\t\t\t\t\t#size-cells = <1>;\n\n\t\t\t\t\tprecal_radio_1000: precal@1000 {\n\t\t\t\t\t\treg = <0x1000 0x2f20>;\n\t\t\t\t\t};\n\n\t\t\t\t\tprecal_radio_5000: precal@5000 {\n\t\t\t\t\t\treg = <0x5000 0x2f20>;\n\t\t\t\t\t};\n\t\t\t\t};\n\n\t\t\t\tpartition@1f0000 {\n\t\t\t\t\tlabel = \"os-image\";\n\t\t\t\t\treg = <0x1f0000 0x400000>;\n\t\t\t\t};\n\n\t\t\t\tpartition@5f0000 {\n\t\t\t\t\tlabel = \"rootfs\";\n\t\t\t\t\treg = <0x5f0000 0x1900000>;\n\t\t\t\t};\n\n\t\t\t\tdefaultmac: partition@1ef0000 {\n\t\t\t\t\tlabel = \"default-mac\";\n\t\t\t\t\treg = <0x1ef0000 0x00200>;\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\tpartition@1ef0200 {\n\t\t\t\t\tlabel = \"pin\";\n\t\t\t\t\treg = <0x1ef0200 0x00200>;\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\tpartition@1ef0400 {\n\t\t\t\t\tlabel = \"product-info\";\n\t\t\t\t\treg = <0x1ef0400 0x0fc00>;\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\tpartition@1f00000 {\n\t\t\t\t\tlabel = \"partition-table\";\n\t\t\t\t\treg = <0x1f00000 0x10000>;\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\tpartition@1f10000 {\n\t\t\t\t\tlabel = \"soft-version\";\n\t\t\t\t\treg = <0x1f10000 0x10000>;\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\tpartition@1f20000 {\n\t\t\t\t\tlabel = \"support-list\";\n\t\t\t\t\treg = <0x1f20000 0x10000>;\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\tpartition@1f30000 {\n\t\t\t\t\tlabel = \"profile\";\n\t\t\t\t\treg = <0x1f30000 0x10000>;\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\tpartition@1f40000 {\n\t\t\t\t\tlabel = \"default-config\";\n\t\t\t\t\treg = <0x1f40000 0x10000>;\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\tpartition@1f50000 {\n\t\t\t\t\tlabel = \"user-config\";\n\t\t\t\t\treg = <0x1f50000 0x40000>;\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\tpartition@1f90000 {\n\t\t\t\t\tlabel = \"qos-db\";\n\t\t\t\t\treg = <0x1f90000 0x40000>;\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\tpartition@1fd0000 {\n\t\t\t\t\tlabel = \"usb-config\";\n\t\t\t\t\treg = <0x1fd0000 0x10000>;\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\tpartition@1fe0000 {\n\t\t\t\t\tlabel = \"log\";\n\t\t\t\t\treg = <0x1fe0000 0x20000>;\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t};\n};\n\n&usb3_0 {\n\tstatus = \"okay\";\n\n\tpinctrl-0 = <&usb0_pwr_en_pin>;\n\tpinctrl-names = \"default\";\n};\n\n&usb3_1 {\n\tstatus = \"okay\";\n\n\tpinctrl-0 = <&usb1_pwr_en_pin>;\n\tpinctrl-names = \"default\";\n};\n\n&pcie0 {\n\tstatus = \"okay\";\n\n\tbridge@0,0 {\n\t\treg = <0x00000000 0 0 0 0>;\n\t\t#address-cells = <3>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\twifi@1,0 {\n\t\t\tcompatible = \"pci168c,0040\";\n\t\t\treg = <0x00010000 0 0 0 0>;\n\n\t\t\tnvmem-cells = <&macaddr_defaultmac_8>, <&precal_radio_1000>;\n\t\t\tnvmem-cell-names = \"mac-address\", \"pre-calibration\";\n\t\t\tmac-address-increment = <(-1)>;\n\t\t};\n\t};\n};\n\n&pcie1 {\n\tstatus = \"okay\";\n\tmax-link-speed = <1>;\n\n\tbridge@0,0 {\n\t\treg = <0x00000000 0 0 0 0>;\n\t\t#address-cells = <3>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\twifi@1,0 {\n\t\t\tcompatible = \"pci168c,0040\";\n\t\t\treg = <0x00010000 0 0 0 0>;\n\n\t\t\tnvmem-cells = <&macaddr_defaultmac_8>, <&precal_radio_5000>;\n\t\t\tnvmem-cell-names = \"mac-address\", \"pre-calibration\";\n\t\t};\n\t};\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tpinctrl-0 = <&mdio0_pins>;\n\tpinctrl-names = \"default\";\n\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t\tqca,ar8327-initvals = <\n\t\t\t0x00004 0x7600000   /* PAD0_MODE */\n\t\t\t0x00008 0x1000000   /* PAD5_MODE */\n\t\t\t0x0000c 0x80        /* PAD6_MODE */\n\t\t\t0x000e4 0x6a545     /* MAC_POWER_SEL */\n\t\t\t0x000e0 0xc74164de  /* SGMII_CTRL */\n\t\t\t0x0007c 0x4e        /* PORT0_STATUS */\n\t\t\t0x00094 0x4e        /* PORT6_STATUS */\n\t\t\t>;\n\t};\n\n\tphy4: ethernet-phy@4 {\n\t\treg = <4>;\n\t};\n};\n\n&gmac1 {\n\tstatus = \"okay\";\n\tphy-mode = \"rgmii\";\n\tqcom,id = <1>;\n\n\tpinctrl-0 = <&rgmii2_pins>;\n\tpinctrl-names = \"default\";\n\n\tnvmem-cells = <&macaddr_defaultmac_8>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <1>;\n\n\tfixed-link {\n\t\tspeed = <1000>;\n\t\tfull-duplex;\n\t};\n};\n\n&gmac2 {\n\tstatus = \"okay\";\n\tphy-mode = \"sgmii\";\n\tqcom,id = <2>;\n\n\tnvmem-cells = <&macaddr_defaultmac_8>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tfixed-link {\n\t\tspeed = <1000>;\n\t\tfull-duplex;\n\t};\n};\n\n&adm_dma {\n\tstatus = \"okay\";\n};\n\n&defaultmac {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_defaultmac_8: macaddr@8 {\n\t\treg = <0x8 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-ad7200.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qcom-ipq8064-ad7200-c2600.dtsi\"\n\n/ {\n\tmodel = \"TP-Link Talon AD7200\";\n\tcompatible = \"tplink,ad7200\", \"qcom,ipq8064\";\n\n\taliases {\n\t\tled-boot = &led_status;\n\t\tled-failsafe = &led_status;\n\t\tled-running = &led_status;\n\t\tled-upgrade = &led_status;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\t\tpinctrl-0 = <&button_pins>;\n\t\tpinctrl-names = \"default\";\n\n\t\twifi {\n\t\t\tlabel = \"wifi\";\n\t\t\tgpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RFKILL>;\n\t\t\tdebounce-interval = <60>;\n\t\t\twakeup-source;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&qcom_pinmux 7 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tdebounce-interval = <60>;\n\t\t\twakeup-source;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&qcom_pinmux 67 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tdebounce-interval = <60>;\n\t\t\twakeup-source;\n\t\t};\n\n\t\tled_enable {\n\t\t\tlabel = \"led-enable\";\n\t\t\tgpios = <&qcom_pinmux 53 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_LIGHTS_TOGGLE>;\n\t\t\tdebounce-interval = <60>;\n\t\t\twakeup-source;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tpinctrl-0 = <&led_pins>;\n\t\tpinctrl-names = \"default\";\n\n\t\tlan {\n\t\t\tlabel = \"blue:lan\";\n\t\t\tgpios = <&qcom_pinmux 2 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tusb1 {\n\t\t\tlabel = \"blue:usb1\";\n\t\t\tgpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\twlan5g {\n\t\t\tlabel = \"blue:wlan5g\";\n\t\t\tgpios = <&qcom_pinmux 15 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tusb3 {\n\t\t\tlabel = \"blue:usb3\";\n\t\t\tgpios = <&qcom_pinmux 16 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\twlan2g {\n\t\t\tlabel = \"blue:wlan2g\";\n\t\t\tgpios = <&qcom_pinmux 17 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\twan_orange {\n\t\t\tlabel = \"orange:wan\";\n\t\t\tgpios = <&qcom_pinmux 26 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twan_blue {\n\t\t\tlabel = \"blue:wan\";\n\t\t\tgpios = <&qcom_pinmux 33 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"blue:wps\";\n\t\t\tgpios = <&qcom_pinmux 55 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\twlan60g {\n\t\t\tlabel = \"blue:wlan60g\";\n\t\t\tgpios = <&qcom_pinmux 56 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tled_status: status {\n\t\t\tlabel = \"blue:status\";\n\t\t\tgpios = <&qcom_pinmux 66 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&qcom_pinmux {\n\tbutton_pins: button_pins {\n\t\tmux {\n\t\t\tpins = \"gpio53\", \"gpio54\", \"gpio67\";\n\t\t\tfunction = \"gpio\";\n\t\t\tdrive-strength = <2>;\n\t\t\tbias-pull-up;\n\t\t};\n\t};\n\n\tled_pins: led_pins {\n\t\tmux {\n\t\t\tpins = \"gpio2\", \"gpio8\", \"gpio15\", \"gpio16\", \"gpio17\", \"gpio26\",\n\t\t\t\t\t\"gpio33\", \"gpio55\", \"gpio56\", \"gpio66\";\n\t\t\tfunction = \"gpio\";\n\t\t\tdrive-strength = <2>;\n\t\t\tbias-pull-up;\n\t\t};\n\t};\n};\n\n&pcie2 {\n\tstatus = \"okay\";\n\tmax-link-speed = <1>;\n};\n"
  },
  {
    "path": "target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-ap148.dts",
    "content": "#include \"qcom-ipq8064-v1.0.dtsi\"\n\n/ {\n\tmodel = \"Qualcomm Technologies, Inc. IPQ8064/AP-148\";\n\tcompatible = \"qcom,ipq8064-ap148\", \"qcom,ipq8064\";\n\n\tmemory@0 {\n\t\treg = <0x42000000 0x1e000000>;\n\t\tdevice_type = \"memory\";\n\t};\n\n\treserved-memory {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tranges;\n\t\trsvd@41200000 {\n\t\t\treg = <0x41200000 0x300000>;\n\t\t\tno-map;\n\t\t};\n\t};\n\n\taliases {\n\t\tmdio-gpio0 = &mdio0;\n\t};\n};\n\n&adm_dma {\n\tstatus = \"okay\";\n};\n\n&flash {\n\tpartitions {\n\t\tcompatible = \"qcom,smem-part\";\n\t};\n};\n\n&usb3_0 {\n\tstatus = \"okay\";\n};\n\n&usb3_1 {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\tstatus = \"okay\";\n};\n\n&pcie1 {\n\tstatus = \"okay\";\n\tmax-link-speed = <1>;\n};\n\n&nand {\n\tstatus = \"okay\";\n\n\tpinctrl-0 = <&nand_pins>;\n\tpinctrl-names = \"default\";\n\n\tnand@0 {\n\t\treg = <0>;\n\t\tcompatible = \"qcom,nandcs\";\n\n\t\tnand-ecc-strength = <4>;\n\t\tnand-bus-width = <8>;\n\t\tnand-ecc-step-size = <512>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"qcom,smem-part\";\n\t\t};\n\t};\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tpinctrl-0 = <&mdio0_pins>;\n\tpinctrl-names = \"default\";\n\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t\tqca,ar8327-initvals = <\n\t\t\t0x00004 0x7600000   /* PAD0_MODE */\n\t\t\t0x00008 0x1000000   /* PAD5_MODE */\n\t\t\t0x0000c 0x80        /* PAD6_MODE */\n\t\t\t0x000e4 0x6a545     /* MAC_POWER_SEL */\n\t\t\t0x000e0 0xc74164de  /* SGMII_CTRL */\n\t\t\t0x0007c 0x4e        /* PORT0_STATUS */\n\t\t\t0x00094 0x4e        /* PORT6_STATUS */\n\t\t\t>;\n\t};\n\n\tphy4: ethernet-phy@4 {\n\t\treg = <4>;\n\t};\n};\n\n&gmac1 {\n\tstatus = \"okay\";\n\tphy-mode = \"rgmii\";\n\tqcom,id = <1>;\n\n\tpinctrl-0 = <&rgmii2_pins>;\n\tpinctrl-names = \"default\";\n\n\tfixed-link {\n\t\tspeed = <1000>;\n\t\tfull-duplex;\n\t};\n};\n\n&gmac2 {\n\tstatus = \"okay\";\n\tphy-mode = \"sgmii\";\n\tqcom,id = <2>;\n\n\tfixed-link {\n\t\tspeed = <1000>;\n\t\tfull-duplex;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-ap161.dts",
    "content": "#include \"qcom-ipq8064-v1.0.dtsi\"\n\n/ {\n\tmodel = \"Qualcomm IPQ8064/AP161\";\n\tcompatible = \"qcom,ipq8064-ap161\", \"qcom,ipq8064\";\n\n\tmemory@0 {\n\t\treg = <0x42000000 0x1e000000>;\n\t\tdevice_type = \"memory\";\n\t};\n\n\treserved-memory {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tranges;\n\t\trsvd@41200000 {\n\t\t\treg = <0x41200000 0x300000>;\n\t\t\tno-map;\n\t\t};\n\t};\n\n\taliases {\n\t\tmdio-gpio0 = &mdio0;\n\t};\n};\n\n&qcom_pinmux {\n\trgmii2_pins: rgmii2_pins {\n\t\tmux {\n\t\t\tpins = \"gpio27\", \"gpio28\", \"gpio29\",\n\t\t\t       \"gpio30\", \"gpio31\", \"gpio32\",\n\t\t\t       \"gpio51\", \"gpio52\", \"gpio59\",\n\t\t\t       \"gpio60\", \"gpio61\", \"gpio62\",\n\t\t\t       \"gpio2\", \"gpio66\";\n\t\t};\n\t};\n};\n\n&flash {\n\tpartitions {\n\t\tcompatible = \"qcom,smem-part\";\n\t};\n};\n\n&usb3_0 {\n\tstatus = \"okay\";\n};\n\n&usb3_1 {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\tstatus = \"okay\";\n};\n\n&pcie1 {\n\tstatus = \"okay\";\n\tmax-link-speed = <1>;\n};\n\n&pcie2 {\n\tstatus = \"okay\";\n};\n\n&nand {\n\tstatus = \"okay\";\n\n\tpinctrl-0 = <&nand_pins>;\n\tpinctrl-names = \"default\";\n\n\tnand@0 {\n\t\treg = <0>;\n\t\tcompatible = \"qcom,nandcs\";\n\n\t\tnand-ecc-strength = <4>;\n\t\tnand-bus-width = <8>;\n\t\tnand-ecc-step-size = <512>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"qcom,smem-part\";\n\t\t};\n\t};\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tpinctrl-0 = <&mdio0_pins>;\n\tpinctrl-names = \"default\";\n\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t\tqca,ar8327-initvals = <\n\t\t\t0x00004 0x7600000   /* PAD0_MODE */\n\t\t\t0x00008 0x1000000   /* PAD5_MODE */\n\t\t\t0x0000c 0x20080     /* PAD6_MODE */\n\t\t\t0x000e4 0x6a545     /* MAC_POWER_SEL */\n\t\t\t0x000e0 0xc74164de  /* SGMII_CTRL */\n\t\t\t0x0007c 0x4e        /* PORT0_STATUS */\n\t\t\t0x00094 0x4e        /* PORT6_STATUS */\n\t\t\t>;\n\t};\n\n\tphy4: ethernet-phy@4 {\n\t\treg = <4>;\n\t\tqca,phy-rgmii-en;\n\t\tqca,txclk-delay-en;\n\t\tqca,rxclk-delay-en;\n\t};\n\n\tphy3: ethernet-phy@3 {\n\t\tdevice_type = \"ethernet-phy\";\n\t\treg = <3>;\n\t};\n};\n\n&gmac0 {\n\tstatus = \"okay\";\n\tphy-mode = \"rgmii\";\n\tqcom,id = <0>;\n\n\tpinctrl-0 = <&rgmii2_pins>;\n\tpinctrl-names = \"default\";\n\tmdiobus = <&mdio0>;\n\n\tfixed-link {\n\t\tspeed = <1000>;\n\t\tfull-duplex;\n\t};\n};\n\n&gmac1 {\n\tstatus = \"okay\";\n\tphy-mode = \"rgmii\";\n\tqcom,id = <1>;\n\tmdiobus = <&mdio0>;\n\n\tfixed-link {\n\t\tspeed = <1000>;\n\t\tfull-duplex;\n\t};\n};\n\n&gmac2 {\n\tstatus = \"okay\";\n\tphy-mode = \"sgmii\";\n\tqcom,id = <2>;\n\tmdiobus = <&mdio0>;\n\n\tfixed-link {\n\t\tspeed = <1000>;\n\t\tfull-duplex;\n\t};\n};\n\n&adm_dma {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-c2600.dts",
    "content": "#include \"qcom-ipq8064-ad7200-c2600.dtsi\"\n\n/ {\n\tmodel = \"TP-Link Archer C2600\";\n\tcompatible = \"tplink,c2600\", \"qcom,ipq8064\";\n\n\taliases {\n\t\tled-boot = &power;\n\t\tled-failsafe = &general;\n\t\tled-running = &power;\n\t\tled-upgrade = &general;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\t\tpinctrl-0 = <&button_pins>;\n\t\tpinctrl-names = \"default\";\n\n\t\twifi {\n\t\t\tlabel = \"wifi\";\n\t\t\tgpios = <&qcom_pinmux 49 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RFKILL>;\n\t\t\tdebounce-interval = <60>;\n\t\t\twakeup-source;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&qcom_pinmux 64 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tdebounce-interval = <60>;\n\t\t\twakeup-source;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tdebounce-interval = <60>;\n\t\t\twakeup-source;\n\t\t};\n\n\t\tledswitch {\n\t\t\tlabel = \"ledswitch\";\n\t\t\tgpios = <&qcom_pinmux 16 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_LIGHTS_TOGGLE>;\n\t\t\tdebounce-interval = <60>;\n\t\t\twakeup-source;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tpinctrl-0 = <&led_pins>;\n\t\tpinctrl-names = \"default\";\n\n\t\tlan {\n\t\t\tlabel = \"white:lan\";\n\t\t\tgpios = <&qcom_pinmux 6 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tusb4 {\n\t\t\tlabel = \"white:usb_4\";\n\t\t\tgpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tusb2 {\n\t\t\tlabel = \"white:usb_2\";\n\t\t\tgpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"white:wps\";\n\t\t\tgpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\twan_amber {\n\t\t\tlabel = \"amber:wan\";\n\t\t\tgpios = <&qcom_pinmux 26 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twan_white {\n\t\t\tlabel = \"white:wan\";\n\t\t\tgpios = <&qcom_pinmux 33 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tpower: power {\n\t\t\tlabel = \"white:power\";\n\t\t\tgpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"keep\";\n\t\t};\n\n\t\tgeneral: general {\n\t\t\tlabel = \"white:general\";\n\t\t\tgpios = <&qcom_pinmux 66 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&qcom_pinmux {\n\tbutton_pins: button_pins {\n\t\tmux {\n\t\t\tpins = \"gpio16\", \"gpio54\", \"gpio65\";\n\t\t\tfunction = \"gpio\";\n\t\t\tdrive-strength = <2>;\n\t\t\tbias-pull-up;\n\t\t};\n\t};\n\n\tled_pins: led_pins {\n\t\tmux {\n\t\t\tpins = \"gpio6\", \"gpio7\", \"gpio8\", \"gpio9\", \"gpio26\", \"gpio33\",\n\t\t\t\t\t\"gpio53\", \"gpio66\";\n\t\t\tfunction = \"gpio\";\n\t\t\tdrive-strength = <2>;\n\t\t\tbias-pull-up;\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-d7800.dts",
    "content": "#include \"qcom-ipq8064-v2.0.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"Netgear Nighthawk X4 D7800\";\n\tcompatible = \"netgear,d7800\", \"qcom,ipq8064\";\n\n\tmemory@0 {\n\t\treg = <0x42000000 0x1e000000>;\n\t\tdevice_type = \"memory\";\n\t};\n\n\treserved-memory {\n\t\trsvd@5fe00000 {\n\t\t\treg = <0x5fe00000 0x200000>;\n\t\t\treusable;\n\t\t};\n\t};\n\n\taliases {\n\t\tmdio-gpio0 = &mdio0;\n\n\t\tled-boot = &power_white;\n\t\tled-failsafe = &power_amber;\n\t\tled-running = &power_white;\n\t\tled-upgrade = &power_amber;\n\t};\n\n\tchosen {\n\t\tbootargs = \"rootfstype=squashfs noinitrd\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\t\tpinctrl-0 = <&button_pins>;\n\t\tpinctrl-names = \"default\";\n\n\t\twifi {\n\t\t\tlabel = \"wifi\";\n\t\t\tgpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RFKILL>;\n\t\t\tdebounce-interval = <60>;\n\t\t\twakeup-source;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tdebounce-interval = <60>;\n\t\t\twakeup-source;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tdebounce-interval = <60>;\n\t\t\twakeup-source;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tpinctrl-0 = <&led_pins>;\n\t\tpinctrl-names = \"default\";\n\n\t\tusb1 {\n\t\t\tlabel = \"white:usb1\";\n\t\t\tgpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tusb2 {\n\t\t\tlabel = \"white:usb2\";\n\t\t\tgpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tpower_amber: power_amber {\n\t\t\tlabel = \"amber:power\";\n\t\t\tgpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\twan_white {\n\t\t\tlabel = \"white:wan\";\n\t\t\tgpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\twan_amber {\n\t\t\tlabel = \"amber:wan\";\n\t\t\tgpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"white:wps\";\n\t\t\tgpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tesata {\n\t\t\tlabel = \"white:esata\";\n\t\t\tgpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tpower_white: power_white {\n\t\t\tlabel = \"white:power\";\n\t\t\tgpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"keep\";\n\t\t};\n\n\t\twifi {\n\t\t\tlabel = \"white:wifi\";\n\t\t\tgpios = <&qcom_pinmux 64 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&qcom_pinmux {\n\tbutton_pins: button_pins {\n\t\tmux {\n\t\t\tpins = \"gpio6\", \"gpio54\", \"gpio65\";\n\t\t\tfunction = \"gpio\";\n\t\t\tdrive-strength = <2>;\n\t\t\tbias-pull-up;\n\t\t};\n\t};\n\n\tled_pins: led_pins {\n\t\tmux {\n\t\t\tpins = \"gpio7\", \"gpio8\", \"gpio9\", \"gpio22\", \"gpio23\",\n\t\t\t\t\"gpio24\",\"gpio26\", \"gpio53\", \"gpio64\";\n\t\t\tfunction = \"gpio\";\n\t\t\tdrive-strength = <2>;\n\t\t\tbias-pull-up;\n\t\t};\n\t};\n\n\tusb0_pwr_en_pins: usb0_pwr_en_pins {\n\t\tmux {\n\t\t\tpins = \"gpio15\";\n\t\t\tfunction = \"gpio\";\n\t\t\tdrive-strength = <12>;\n\t\t\tbias-pull-down;\n\t\t\toutput-high;\n\t\t};\n\t};\n\n\tusb1_pwr_en_pins: usb1_pwr_en_pins {\n\t\tmux {\n\t\t\tpins = \"gpio16\", \"gpio68\";\n\t\t\tfunction = \"gpio\";\n\t\t\tdrive-strength = <12>;\n\t\t\tbias-pull-down;\n\t\t\toutput-high;\n\t\t};\n\t};\n};\n\n&sata_phy {\n\tstatus = \"okay\";\n};\n\n&sata {\n\tstatus = \"okay\";\n};\n\n&usb3_0 {\n\tstatus = \"okay\";\n\n\tpinctrl-0 = <&usb0_pwr_en_pins>;\n\tpinctrl-names = \"default\";\n};\n\n&usb3_1 {\n\tstatus = \"okay\";\n\n\tpinctrl-0 = <&usb1_pwr_en_pins>;\n\tpinctrl-names = \"default\";\n};\n\n&pcie0 {\n\tstatus = \"okay\";\n\treset-gpio = <&qcom_pinmux 3 GPIO_ACTIVE_HIGH>;\n\tpinctrl-0 = <&pcie0_pins>;\n\tpinctrl-names = \"default\";\n\n\tbridge@0,0 {\n\t\treg = <0x00000000 0 0 0 0>;\n\t\t#address-cells = <3>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\twifi@1,0 {\n\t\t\tcompatible = \"pci168c,0040\";\n\t\t\treg = <0x00010000 0 0 0 0>;\n\n\t\t\tnvmem-cells = <&macaddr_art_6>, <&precal_art_1000>;\n\t\t\tnvmem-cell-names = \"mac-address\", \"pre-calibration\";\n\t\t\tmac-address-increment = <(1)>;\n\t\t};\n\t};\n};\n\n&pcie1 {\n\tstatus = \"okay\";\n\treset-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_HIGH>;\n\tpinctrl-0 = <&pcie1_pins>;\n\tpinctrl-names = \"default\";\n\tmax-link-speed = <1>;\n\n\tbridge@0,0 {\n\t\treg = <0x00000000 0 0 0 0>;\n\t\t#address-cells = <3>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\twifi@1,0 {\n\t\t\tcompatible = \"pci168c,0040\";\n\t\t\treg = <0x00010000 0 0 0 0>;\n\n\t\t\tnvmem-cells = <&macaddr_art_6>, <&precal_art_5000>;\n\t\t\tnvmem-cell-names = \"mac-address\", \"pre-calibration\";\n\t\t\tmac-address-increment = <(2)>;\n\t\t};\n\t};\n};\n\n&pcie2 {\n\tstatus = \"okay\";\n\treset-gpio = <&qcom_pinmux 63 GPIO_ACTIVE_HIGH>;\n\tpinctrl-0 = <&pcie2_pins>;\n\tpinctrl-names = \"default\";\n};\n\n&nand {\n\tstatus = \"okay\";\n\n\tpinctrl-0 = <&nand_pins>;\n\tpinctrl-names = \"default\";\n\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\n\tnand@0 {\n\t\treg = <0>;\n\t\tcompatible = \"qcom,nandcs\";\n\n\t\tnand-ecc-strength = <4>;\n\t\tnand-bus-width = <8>;\n\t\tnand-ecc-step-size = <512>;\n\n\t\tnand-is-boot-medium;\n\t\tqcom,boot_pages_size = <0x1180000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tqcadata@0 {\n\t\t\t\tlabel = \"qcadata\";\n\t\t\t\treg = <0x0000000 0x0c80000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tAPPSBL@c80000 {\n\t\t\t\tlabel = \"APPSBL\";\n\t\t\t\treg = <0x0c80000 0x0500000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tAPPSBLENV@1180000 {\n\t\t\t\tlabel = \"APPSBLENV\";\n\t\t\t\treg = <0x1180000 0x0080000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tart@1200000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0x1200000 0x0140000>;\n\t\t\t\tread-only;\n\t\t\t\tcompatible = \"nvmem-cells\";\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\n\t\t\t\tmacaddr_art_0: macaddr@0 {\n\t\t\t\t\treg = <0x0 0x6>;\n\t\t\t\t};\n\n\t\t\t\tmacaddr_art_6: macaddr@6 {\n\t\t\t\t\treg = <0x6 0x6>;\n\t\t\t\t};\n\n\t\t\t\tprecal_art_1000: precal@1000 {\n\t\t\t\t\treg = <0x1000 0x2f20>;\n\t\t\t\t};\n\n\t\t\t\tprecal_art_5000: precal@5000 {\n\t\t\t\t\treg = <0x5000 0x2f20>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tartbak: art@1340000 {\n\t\t\t\tlabel = \"artbak\";\n\t\t\t\treg = <0x1340000 0x0140000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tkernel@1480000 {\n\t\t\t\tlabel = \"kernel\";\n\t\t\t\treg = <0x1480000 0x0400000>;\n\t\t\t};\n\n\t\t\tubi@1880000 {\n\t\t\t\tlabel = \"ubi\";\n\t\t\t\treg = <0x1880000 0x6080000>;\n\t\t\t};\n\n\t\t\treserve@7900000 {\n\t\t\t\tlabel = \"reserve\";\n\t\t\t\treg = <0x7900000 0x0700000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tpinctrl-0 = <&mdio0_pins>;\n\tpinctrl-names = \"default\";\n\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t\tqca,ar8327-initvals = <\n\t\t\t0x00004 0x7600000   /* PAD0_MODE */\n\t\t\t0x00008 0x1000000   /* PAD5_MODE */\n\t\t\t0x0000c 0x80        /* PAD6_MODE */\n\t\t\t0x000e4 0x6a545     /* MAC_POWER_SEL */\n\t\t\t0x000e0 0xc74164de  /* SGMII_CTRL */\n\t\t\t0x0007c 0x4e        /* PORT0_STATUS */\n\t\t\t0x00094 0x4e        /* PORT6_STATUS */\n\t\t\t>;\n\t};\n\n\tphy4: ethernet-phy@4 {\n\t\treg = <4>;\n\t};\n};\n\n&gmac1 {\n\tstatus = \"okay\";\n\tphy-mode = \"rgmii\";\n\tqcom,id = <1>;\n\n\tpinctrl-0 = <&rgmii2_pins>;\n\tpinctrl-names = \"default\";\n\n\tnvmem-cells = <&macaddr_art_6>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tfixed-link {\n\t\tspeed = <1000>;\n\t\tfull-duplex;\n\t};\n};\n\n&gmac2 {\n\tstatus = \"okay\";\n\tphy-mode = \"sgmii\";\n\tqcom,id = <2>;\n\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tfixed-link {\n\t\tspeed = <1000>;\n\t\tfull-duplex;\n\t};\n};\n\n&adm_dma {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-db149.dts",
    "content": "#include \"qcom-ipq8064-v1.0.dtsi\"\n\n/ {\n\tmodel = \"Qualcomm IPQ8064/DB149\";\n\tcompatible = \"qcom,ipq8064-db149\", \"qcom,ipq8064\";\n\n\taliases {\n\t\tserial0 = &gsbi2_serial;\n\t};\n\n\treserved-memory {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tranges;\n\t\trsvd@41200000 {\n\t\t\treg = <0x41200000 0x300000>;\n\t\t\tno-map;\n\t\t};\n\t};\n};\n\n&qcom_pinmux {\n\trgmii0_pins: rgmii0_pins {\n\t\tmux {\n\t\t\tpins = \"gpio2\", \"gpio66\";\n\t\t\tdrive-strength = <8>;\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&gsbi2 {\n\tqcom,mode = <GSBI_PROT_I2C_UART>;\n\tstatus = \"okay\";\n\n\tgsbi2_serial: serial@12490000 {\n\t\tstatus = \"okay\";\n\t};\n};\n\n&gsbi4 {\n\tstatus = \"disabled\";\n};\n\n&gsbi4_serial {\n\tstatus = \"disabled\";\n};\n\n&flash {\n\tm25p,fast-read;\n\n\tpartition@0 {\n\t\tlabel = \"lowlevel_init\";\n\t\treg = <0x0 0x1b0000>;\n\t};\n\n\tpartition@1 {\n\t\tlabel = \"u-boot\";\n\t\treg = <0x1b0000 0x80000>;\n\t};\n\n\tpartition@2 {\n\t\tlabel = \"u-boot-env\";\n\t\treg = <0x230000 0x40000>;\n\t};\n\n\tpartition@3 {\n\t\tlabel = \"caldata\";\n\t\treg = <0x270000 0x40000>;\n\t};\n\n\tpartition@4 {\n\t\tlabel = \"firmware\";\n\t\treg = <0x2b0000 0x1d50000>;\n\t};\n};\n\n&usb3_0 {\n\tstatus = \"okay\";\n};\n\n&usb3_1 {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\tstatus = \"okay\";\n};\n\n&pcie1 {\n\tstatus = \"okay\";\n};\n\n&pcie2 {\n\tstatus = \"okay\";\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tpinctrl-0 = <&mdio0_pins>;\n\tpinctrl-names = \"default\";\n\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t\tqca,ar8327-initvals = <\n\t\t\t0x00004 0x7600000   /* PAD0_MODE */\n\t\t\t0x00008 0x1000000   /* PAD5_MODE */\n\t\t\t0x0000c 0x80        /* PAD6_MODE */\n\t\t\t0x000e4 0x6a545     /* MAC_POWER_SEL */\n\t\t\t0x000e0 0xc74164de  /* SGMII_CTRL */\n\t\t\t0x0007c 0x4e        /* PORT0_STATUS */\n\t\t\t0x00094 0x4e        /* PORT6_STATUS */\n\t\t>;\n\t};\n\n\tphy4: ethernet-phy@4 {\n\t\treg = <4>;\n\t};\n\n\tphy6: ethernet-phy@6 {\n\t\treg = <6>;\n\t};\n\n\tphy7: ethernet-phy@7 {\n\t\treg = <7>;\n\t};\n};\n\n&gmac0 {\n\tstatus = \"okay\";\n\tphy-mode = \"rgmii\";\n\tqcom,id = <0>;\n\tphy-handle = <&phy4>;\n\n\tpinctrl-0 = <&rgmii0_pins>;\n\tpinctrl-names = \"default\";\n};\n\n&gmac1 {\n\tstatus = \"okay\";\n\tphy-mode = \"sgmii\";\n\tqcom,id = <1>;\n\n\tfixed-link {\n\t\tspeed = <1000>;\n\t\tfull-duplex;\n\t};\n};\n\n&gmac2 {\n\tstatus = \"okay\";\n\tphy-mode = \"sgmii\";\n\tqcom,id = <2>;\n\tphy-handle = <&phy6>;\n};\n\n&gmac3 {\n\tstatus = \"okay\";\n\tphy-mode = \"sgmii\";\n\tqcom,id = <3>;\n\tphy-handle = <&phy7>;\n};\n"
  },
  {
    "path": "target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-ea7500-v1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qcom-ipq8064-eax500.dtsi\"\n\n/ {\n\tmodel = \"Linksys EA7500 V1 WiFi Router\";\n\tcompatible = \"linksys,ea7500-v1\", \"qcom,ipq8064\";\n\n\tmemory@0 {\n\t\treg = <0x42000000 0xe000000>;\n\t\tdevice_type = \"memory\";\n\t};\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tchosen {\n\t\t/* look for root deviceblock nbr in this bootarg */\n\t\tfind-rootblock = \"ubi.mtd=\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\t\tpinctrl-0 = <&button_pins>;\n\t\tpinctrl-names = \"default\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&qcom_pinmux 68 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tdebounce-interval = <60>;\n\t\t\twakeup-source;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tdebounce-interval = <60>;\n\t\t\twakeup-source;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tpinctrl-0 = <&led_pins>;\n\t\tpinctrl-names = \"default\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"white:power\";\n\t\t\tgpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"keep\";\n\t\t};\n\t};\n};\n\n&qcom_pinmux {\n\tbutton_pins: button_pins {\n\t\tmux {\n\t\t\tpins = \"gpio65\", \"gpio68\";\n\t\t\tfunction = \"gpio\";\n\t\t\tdrive-strength = <2>;\n\t\t\tbias-pull-up;\n\t\t};\n\t};\n\n\tled_pins: led_pins {\n\t\tmux {\n\t\t\tpins = \"gpio6\";\n\t\t\tfunction = \"gpio\";\n\t\t\tdrive-strength = <2>;\n\t\t\tbias-pull-up;\n\t\t};\n\t};\n};\n\n&partitions {\n\tpartition@5f80000 {\n\t\tlabel = \"sysdiag\";\n\t\treg = <0x5f80000 0x100000>;\n\t};\n\n\tpartition@6080000 {\n\t\tlabel = \"syscfg\";\n\t\treg = <0x6080000 0x1f80000>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-ea8500.dts",
    "content": "#include \"qcom-ipq8064-eax500.dtsi\"\n\n/ {\n\tmodel = \"Linksys EA8500 WiFi Router\";\n\tcompatible = \"linksys,ea8500\", \"qcom,ipq8064\";\n\n\tmemory@0 {\n\t\treg = <0x42000000 0x1e000000>;\n\t\tdevice_type = \"memory\";\n\t};\n\n\taliases {\n\t\tmdio-gpio0 = &mdio0;\n\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\t\tpinctrl-0 = <&button_pins>;\n\t\tpinctrl-names = \"default\";\n\n\t\twifi {\n\t\t\tlabel = \"wifi\";\n\t\t\tgpios = <&qcom_pinmux 67 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RFKILL>;\n\t\t\tdebounce-interval = <60>;\n\t\t\twakeup-source;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&qcom_pinmux 68 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tdebounce-interval = <60>;\n\t\t\twakeup-source;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tdebounce-interval = <60>;\n\t\t\twakeup-source;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tpinctrl-0 = <&led_pins>;\n\t\tpinctrl-names = \"default\";\n\n\t\twps {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tled_power: power {\n\t\t\tlabel = \"white:power\";\n\t\t\tgpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"keep\";\n\t\t};\n\n\t\twifi {\n\t\t\tlabel = \"green:wifi\";\n\t\t\tgpios = <&qcom_pinmux 54 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&qcom_pinmux {\n\tbutton_pins: button_pins {\n\t\tmux {\n\t\t\tpins = \"gpio65\", \"gpio67\", \"gpio68\";\n\t\t\tfunction = \"gpio\";\n\t\t\tdrive-strength = <2>;\n\t\t\tbias-pull-up;\n\t\t};\n\t};\n\n\tled_pins: led_pins {\n\t\tmux {\n\t\t\tpins = \"gpio6\", \"gpio53\", \"gpio54\";\n\t\t\tfunction = \"gpio\";\n\t\t\tdrive-strength = <2>;\n\t\t\tbias-pull-up;\n\t\t};\n\t};\n};\n\n&sata_phy {\n\tstatus = \"okay\";\n};\n\n&sata {\n\tstatus = \"okay\";\n};\n\n&partitions {\n\tpartition@5f80000 {\n\t\tlabel = \"syscfg\";\n\t\treg = <0x5f80000 0x2080000>;\n\t};\n};\n\n&mdio0 {\n\tphy4: ethernet-phy@4 {\n\t\treg = <4>;\n\t};\n};\n\n&gmac1 {\n\tqcom,phy_mdio_addr = <4>;\n\tqcom,poll_required = <1>;\n\tqcom,rgmii_delay = <0>;\n\tqcom,emulation = <0>;\n};\n\n/* LAN */\n&gmac2 {\n\tqcom,phy_mdio_addr = <0>;\t/* none */\n\tqcom,poll_required = <0>;\t/* no polling */\n\tqcom,rgmii_delay = <0>;\n\tqcom,emulation = <0>;\n};\n"
  },
  {
    "path": "target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-eax500.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qcom-ipq8064-v2.0.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tchosen {\n\t\tbootargs = \"console=ttyMSM0,115200n8\";\n\t\t/* append to bootargs adding the root deviceblock nbr from bootloader */\n\t\tappend-rootblock = \"ubi.mtd=\";\n\t};\n};\n\n&usb3_0 {\n\tstatus = \"okay\";\n};\n\n&usb3_1 {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\tstatus = \"okay\";\n\n\tmax-link-speed = <1>;\n};\n\n&pcie1 {\n\tstatus = \"okay\";\n};\n\n&pcie2 {\n\tstatus = \"okay\";\n};\n\n&nand {\n\tstatus = \"okay\";\n\n\tpinctrl-0 = <&nand_pins>;\n\tpinctrl-names = \"default\";\n\n\tnand@0 {\n\t\treg = <0>;\n\t\tcompatible = \"qcom,nandcs\";\n\n\t\tnand-ecc-strength = <4>;\n\t\tnand-bus-width = <8>;\n\t\tnand-ecc-step-size = <512>;\n\n\t\tnand-is-boot-medium;\n\t\tqcom,boot_pages_size = <0x0c80000>;\n\n\t\tpartitions: partitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"SBL1\";\n\t\t\t\treg = <0x0000000 0x0040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"MIBIB\";\n\t\t\t\treg = <0x0040000 0x0140000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@180000 {\n\t\t\t\tlabel = \"SBL2\";\n\t\t\t\treg = <0x0180000 0x0140000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@2c0000 {\n\t\t\t\tlabel = \"SBL3\";\n\t\t\t\treg = <0x02c0000 0x0280000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@540000 {\n\t\t\t\tlabel = \"DDRCONFIG\";\n\t\t\t\treg = <0x0540000 0x0120000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@660000 {\n\t\t\t\tlabel = \"SSD\";\n\t\t\t\treg = <0x0660000 0x0120000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@780000 {\n\t\t\t\tlabel = \"TZ\";\n\t\t\t\treg = <0x0780000 0x0280000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@a00000 {\n\t\t\t\tlabel = \"RPM\";\n\t\t\t\treg = <0x0a00000 0x0280000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tart: partition@c80000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0x0c80000 0x0140000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@dc0000 {\n\t\t\t\tlabel = \"APPSBL\";\n\t\t\t\treg = <0x0dc0000 0x0100000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@ec0000 {\n\t\t\t\tlabel = \"u_env\";\n\t\t\t\treg = <0x0ec0000 0x0040000>;\n\t\t\t};\n\n\t\t\tpartition@f00000 {\n\t\t\t\tlabel = \"s_env\";\n\t\t\t\treg = <0x0f00000 0x0040000>;\n\t\t\t};\n\n\t\t\tpartition@f40000 {\n\t\t\t\tlabel = \"devinfo\";\n\t\t\t\treg = <0x0f40000 0x0040000>;\n\t\t\t};\n\n\t\t\tpartition@f80000 {\n\t\t\t\tlabel = \"kernel1\";\n\t\t\t\treg = <0x0f80000 0x2800000>;  /* 4 MB, spill to rootfs */\n\t\t\t};\n\n\t\t\tpartition@1380000 {\n\t\t\t\tlabel = \"rootfs1\";\n\t\t\t\treg = <0x1380000 0x2400000>;\n\t\t\t};\n\n\t\t\tpartition@3780000 {\n\t\t\t\tlabel = \"kernel2\";\n\t\t\t\treg = <0x3780000 0x2800000>;\n\t\t\t};\n\n\t\t\tpartition@3b80000 {\n\t\t\t\tlabel = \"rootfs2\";\n\t\t\t\treg = <0x3b80000 0x2400000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tpinctrl-0 = <&mdio0_pins>;\n\tpinctrl-names = \"default\";\n\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t\tqca,ar8327-initvals = <\n\t\t\t0x00004 0x7600000   /* PAD0_MODE */\n\t\t\t0x00008 0x1000000   /* PAD5_MODE */\n\t\t\t0x0000c 0x80        /* PAD6_MODE */\n\t\t\t0x00010 0x2613a0    /* PWS_REG */\n\t\t\t0x000e4 0x6a545     /* MAC_POWER_SEL */\n\t\t\t0x000e0 0xc74164de  /* SGMII_CTRL */\n\t\t\t0x0007c 0x4e        /* PORT0_STATUS */\n\t\t\t0x00094 0x4e        /* PORT6_STATUS */\n\t\t\t>;\n\t};\n};\n\n&gmac1 {\n\tstatus = \"okay\";\n\n\tphy-mode = \"rgmii\";\n\tqcom,id = <1>;\n\n\tpinctrl-0 = <&rgmii2_pins>;\n\tpinctrl-names = \"default\";\n\n\tfixed-link {\n\t\tspeed = <1000>;\n\t\tfull-duplex;\n\t};\n};\n\n&gmac2 {\n\tstatus = \"okay\";\n\n\tphy-mode = \"sgmii\";\n\tqcom,id = <2>;\n\n\tfixed-link {\n\t\tspeed = <1000>;\n\t\tfull-duplex;\n\t};\n};\n\n&adm_dma {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-g10.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0\n#include \"qcom-ipq8064-v2.0.dtsi\"\n\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/soc/qcom,tcsr.h>\n\n/ {\n\tcompatible = \"asrock,g10\", \"qcom,ipq8064\";\n\tmodel = \"ASRock G10\";\n\n\taliases {\n\t\tethernet0 = &gmac1;\n\t\tethernet1 = &gmac0;\n\n\t\tled-boot = &led_status_blue;\n\t\tled-failsafe = &led_status_amber;\n\t\tled-running = &led_status_blue;\n\t\tled-upgrade = &led_status_amber;\n\t};\n\n\tchosen {\n\t\tbootargs-override = \"console=ttyMSM0,115200n8\";\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tpinctrl-0 = <&led_pins>;\n\t\tpinctrl-names = \"default\";\n\n\t\t/*\n\t\t * this is a bit misleading. Because there are about seven\n\t\t * multicolor LEDs connected all wired together in parallel.\n\t\t */\n\n\t\tstatus_yellow {\n\t\t\tlabel = \"yellow:status\";\n\t\t\tgpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tled_status_amber: status_amber {\n\t\t\tlabel = \"amber:status\";\n\t\t\tgpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tled_status_blue: status_blue {\n\t\t\tlabel = \"blue:status\";\n\t\t\tgpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\t/*\n\t\t * LED is declared in vendors boardfile but it's not\n\t\t * working and the manual doesn't mention anything\n\t\t * about the LED being white.\n\n\t\tstatus_white {\n\t\t\tlabel = \"white:status\";\n\t\t\tgpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t\t*/\n\t};\n\n\ti2c-gpio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcompatible = \"i2c-gpio\";\n\t\tgpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>, /* sda */\n\t\t\t<&qcom_pinmux 54 GPIO_ACTIVE_HIGH>; /* scl */\n\t\ti2c-gpio,delay-us = <5>;\n\t\ti2c-gpio,scl-output-only;\n\n\t\tmcu@50 {\n\t\t\treg = <0x50>;\n\t\t\tcompatible = \"sonix,sn8f25e21\";\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\tpinctrl-0 = <&button_pins>;\n\t\tpinctrl-names = \"default\";\n\n\t\tir-remote {\n\t\t\tlabel = \"ir-remote\";\n\t\t\tgpios = <&qcom_pinmux 15 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_0>;\n\t\t\tdebounce-interval = <60>;\n\t\t\twakeup-source;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&qcom_pinmux 16 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tdebounce-interval = <60>;\n\t\t\twakeup-source;\n\t\t};\n\n\t\twps5g {\n\t\t\tlabel = \"wps5g\";\n\t\t\tgpios = <&qcom_pinmux 64 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tdebounce-interval = <60>;\n\t\t\twakeup-source;\n\t\t};\n\n\t\twps2g {\n\t\t\tlabel = \"wps2g\";\n\t\t\tgpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tdebounce-interval = <60>;\n\t\t\twakeup-source;\n\t\t};\n\t};\n};\n\n&adm_dma {\n\tstatus = \"okay\";\n};\n\n&gmac1 {\n\tstatus = \"okay\";\n\n\tpinctrl-0 = <&rgmii2_pins>;\n\tpinctrl-names = \"default\";\n\n\tphy-mode = \"rgmii\";\n\tqcom,id = <1>;\n\n\tfixed-link {\n\t\tspeed = <1000>;\n\t\tfull-duplex;\n\t};\n};\n\n&gmac2 {\n\tstatus = \"okay\";\n\n\tphy-mode = \"sgmii\";\n\tqcom,id = <2>;\n\n\tfixed-link {\n\t\tspeed = <1000>;\n\t\tfull-duplex;\n\t};\n};\n\n&gsbi4_serial {\n\tpinctrl-0 = <&uart0_pins>;\n\tpinctrl-names = \"default\";\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tpinctrl-0 = <&mdio0_pins>;\n\tpinctrl-names = \"default\";\n\n\tethernet-phy@0 {\n\t\treg = <0>;\n\t\tqca,ar8327-initvals = <\n\t\t\t0x00004 0x7600000   /* PAD0_MODE */\n\t\t\t0x00008 0x1000000   /* PAD5_MODE */\n\t\t\t0x0000c 0x80        /* PAD6_MODE */\n\t\t\t0x000e4 0x6a545     /* MAC_POWER_SEL */\n\t\t\t0x000e0 0xc74164de  /* SGMII_CTRL */\n\t\t\t0x0007c 0x4e        /* PORT0_STATUS */\n\t\t\t0x00094 0x4e        /* PORT6_STATUS */\n\t\t\t>;\n\t};\n};\n\n&nand {\n\tstatus = \"okay\";\n\n\tpinctrl-0 = <&nand_pins>;\n\tpinctrl-names = \"default\";\n\n\tnand@0 {\n\t\treg = <0>;\n\t\tcompatible = \"qcom,nandcs\";\n\n\t\tnand-ecc-strength = <4>;\n\t\tnand-bus-width = <8>;\n\t\tnand-ecc-step-size = <512>;\n\n\t\tnand-is-boot-medium;\n\t\tqcom,boot_pages_size = <0x1200000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"qcom,smem-part\";\n\t\t};\n\t};\n};\n\n&pcie0 {\n\tstatus = \"okay\";\n\n\tbridge@0,0 {\n\t\treg = <0x00000000 0 0 0 0>;\n\t\t#address-cells = <3>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\twifi5g: wifi@1,0 {\n\t\t\treg = <0x00010000 0 0 0 0>;\n\t\t\tcompatible = \"qcom,ath10k\";\n\t\t\tqcom,ath10k-calibration-variant = \"ASRock-G10\";\n\t\t};\n\t};\n};\n\n&pcie1 {\n\tstatus = \"okay\";\n\n\tbridge@0,0 {\n\t\treg = <0x00000000 0 0 0 0>;\n\t\t#address-cells = <3>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\twifi2g: wifi@1,0 {\n\t\t\treg = <0x00010000 0 0 0 0>;\n\t\t\tcompatible = \"qcom,ath10k\";\n\t\t\tqcom,ath10k-calibration-variant = \"ASRock-G10\";\n\t\t};\n\t};\n};\n\n&qcom_pinmux {\n\tled_pins: led_pins {\n\t\tmux {\n\t\t\tpins = \"gpio7\", \"gpio8\", \"gpio9\", \"gpio26\";\n\t\t\tfunction = \"gpio\";\n\t\t\tdrive-strength = <2>;\n\t\t\tbias-pull-up;\n\t\t};\n\t};\n\n\tbutton_pins: button_pins {\n\t\tmux {\n\t\t\tpins = \"gpio15\", \"gpio16\", \"gpio64\", \"gpio65\";\n\t\t\tfunction = \"gpio\";\n\t\t\tdrive-strength = <2>;\n\t\t\tbias-pull-up;\n\t\t};\n\t};\n\n\tuart0_pins: uart0_pins {\n\t\tmux {\n\t\t\tpins = \"gpio10\", \"gpio11\";\n\t\t\tfunction = \"gsbi4\";\n\t\t\tdrive-strength = <10>;\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&rpm {\n\tpinctrl-0 = <&i2c4_pins>;\n\tpinctrl-names = \"default\";\n};\n\n&usb3_0 {\n\tstatus = \"okay\";\n};\n\n&usb3_1 {\n\tstatus = \"okay\";\n};\n\n&tcsr {\n\tqcom,usb-ctrl-select = <TCSR_USB_SELECT_USB3_DUAL>;\n};\n\n/delete-node/ &pcie2_pins;\n/delete-node/ &pcie2;\n"
  },
  {
    "path": "target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-r7500.dts",
    "content": "#include \"qcom-ipq8064-v1.0.dtsi\"\n\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/soc/qcom,tcsr.h>\n\n/ {\n\tmodel = \"Netgear Nighthawk X4 R7500\";\n\tcompatible = \"netgear,r7500\", \"qcom,ipq8064\";\n\n\tmemory@0 {\n\t\treg = <0x42000000 0xe000000>;\n\t\tdevice_type = \"memory\";\n\t};\n\n\treserved-memory {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tranges;\n\t\trsvd@41200000 {\n\t\t\treg = <0x41200000 0x300000>;\n\t\t\tno-map;\n\t\t};\n\t};\n\n\taliases {\n\t\tmdio-gpio0 = &mdio0;\n\n\t\tled-boot = &power_white;\n\t\tled-failsafe = &power_amber;\n\t\tled-running = &power_white;\n\t\tled-upgrade = &power_amber;\n\t};\n\n\tchosen {\n\t\tbootargs = \"rootfstype=squashfs noinitrd\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\t\tpinctrl-0 = <&button_pins>;\n\t\tpinctrl-names = \"default\";\n\n\t\twifi {\n\t\t\tlabel = \"wifi\";\n\t\t\tgpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RFKILL>;\n\t\t\tdebounce-interval = <60>;\n\t\t\twakeup-source;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tdebounce-interval = <60>;\n\t\t\twakeup-source;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tdebounce-interval = <60>;\n\t\t\twakeup-source;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tpinctrl-0 = <&led_pins>;\n\t\tpinctrl-names = \"default\";\n\n\t\tusb1 {\n\t\t\tlabel = \"white:usb1\";\n\t\t\tgpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tusb2 {\n\t\t\tlabel = \"white:usb2\";\n\t\t\tgpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tpower_amber: power_amber {\n\t\t\tlabel = \"amber:power\";\n\t\t\tgpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\twan_white {\n\t\t\tlabel = \"white:wan\";\n\t\t\tgpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\twan_amber {\n\t\t\tlabel = \"amber:wan\";\n\t\t\tgpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"white:wps\";\n\t\t\tgpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tesata {\n\t\t\tlabel = \"white:esata\";\n\t\t\tgpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tpower_white: power_white {\n\t\t\tlabel = \"white:power\";\n\t\t\tgpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"keep\";\n\t\t};\n\n\t\twifi {\n\t\t\tlabel = \"white:wifi\";\n\t\t\tgpios = <&qcom_pinmux 64 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&qcom_pinmux {\n\tbutton_pins: button_pins {\n\t\tmux {\n\t\t\tpins = \"gpio6\", \"gpio54\", \"gpio65\";\n\t\t\tfunction = \"gpio\";\n\t\t\tdrive-strength = <2>;\n\t\t\tbias-pull-up;\n\t\t};\n\t};\n\n\tled_pins: led_pins {\n\t\tmux {\n\t\t\tpins = \"gpio7\", \"gpio8\", \"gpio9\", \"gpio22\", \"gpio23\",\n\t\t\t\t\"gpio24\",\"gpio26\", \"gpio53\", \"gpio64\";\n\t\t\tfunction = \"gpio\";\n\t\t\tdrive-strength = <2>;\n\t\t\tbias-pull-up;\n\t\t};\n\t};\n};\n\n&gsbi5 {\n\tstatus = \"disabled\";\n\n\tspi@1a280000 {\n\t\tstatus = \"disabled\";\n\t};\n};\n\n&usb3_0 {\n\tstatus = \"okay\";\n};\n\n&usb3_1 {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\tstatus = \"okay\";\n};\n\n&pcie1 {\n\tstatus = \"okay\";\n\tmax-link-speed = <1>;\n};\n\n&nand {\n\tstatus = \"okay\";\n\n\tpinctrl-0 = <&nand_pins>;\n\tpinctrl-names = \"default\";\n\n\tnand@0 {\n\t\treg = <0>;\n\t\tcompatible = \"qcom,nandcs\";\n\n\t\tnand-ecc-strength = <4>;\n\t\tnand-bus-width = <8>;\n\t\tnand-ecc-step-size = <512>;\n\n\t\tnand-is-boot-medium;\n\t\tqcom,boot_pages_size = <0x1180000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tqcadata@0 {\n\t\t\t\tlabel = \"qcadata\";\n\t\t\t\treg = <0x0000000 0x0c80000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tAPPSBL@c80000 {\n\t\t\t\tlabel = \"APPSBL\";\n\t\t\t\treg = <0x0c80000 0x0500000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tAPPSBLENV@1180000 {\n\t\t\t\tlabel = \"APPSBLENV\";\n\t\t\t\treg = <0x1180000 0x0080000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tart: art@1200000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0x1200000 0x0140000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tkernel@1340000 {\n\t\t\t\tlabel = \"kernel\";\n\t\t\t\treg = <0x1340000 0x0400000>;\n\t\t\t};\n\n\t\t\tubi@1740000 {\n\t\t\t\tlabel = \"ubi\";\n\t\t\t\treg = <0x1740000 0x1600000>;\n\t\t\t};\n\n\t\t\tnetgear@2d40000 {\n\t\t\t\tlabel = \"netgear\";\n\t\t\t\treg = <0x2d40000 0x0c00000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\treserve@3940000 {\n\t\t\t\tlabel = \"reserve\";\n\t\t\t\treg = <0x3940000 0x46c0000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tpinctrl-0 = <&mdio0_pins>;\n\tpinctrl-names = \"default\";\n\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t\tqca,ar8327-initvals = <\n\t\t\t0x00004 0x7600000   /* PAD0_MODE */\n\t\t\t0x00008 0x1000000   /* PAD5_MODE */\n\t\t\t0x0000c 0x80        /* PAD6_MODE */\n\t\t\t0x000e4 0x6a545     /* MAC_POWER_SEL */\n\t\t\t0x000e0 0xc74164de  /* SGMII_CTRL */\n\t\t\t0x0007c 0x4e        /* PORT0_STATUS */\n\t\t\t0x00094 0x4e        /* PORT6_STATUS */\n\t\t\t>;\n\t};\n\n\tphy4: ethernet-phy@4 {\n\t\treg = <4>;\n\t};\n};\n\n&gmac1 {\n\tstatus = \"okay\";\n\tphy-mode = \"rgmii\";\n\tqcom,id = <1>;\n\n\tpinctrl-0 = <&rgmii2_pins>;\n\tpinctrl-names = \"default\";\n\n\tnvmem-cells = <&macaddr_art_6>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tfixed-link {\n\t\tspeed = <1000>;\n\t\tfull-duplex;\n\t};\n};\n\n&gmac2 {\n\tstatus = \"okay\";\n\tphy-mode = \"sgmii\";\n\tqcom,id = <2>;\n\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tfixed-link {\n\t\tspeed = <1000>;\n\t\tfull-duplex;\n\t};\n};\n\n&tcsr {\n\tqcom,usb-ctrl-select = <TCSR_USB_SELECT_USB3_DUAL>;\n\tcompatible = \"qcom,tcsr\";\n};\n\n&adm_dma {\n\tstatus = \"okay\";\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n\n\tmacaddr_art_6: macaddr@6 {\n\t\treg = <0x6 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-r7500v2.dts",
    "content": "#include \"qcom-ipq8064-v2.0.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"Netgear Nighthawk X4 R7500v2\";\n\tcompatible = \"netgear,r7500v2\", \"qcom,ipq8064\";\n\n\tmemory@0 {\n\t\treg = <0x42000000 0x1e000000>;\n\t\tdevice_type = \"memory\";\n\t};\n\n\treserved-memory {\n\t\trsvd@5fe00000 {\n\t\t\treg = <0x5fe00000 0x200000>;\n\t\t\treusable;\n\t\t};\n\t};\n\n\taliases {\n\t\tmdio-gpio0 = &mdio0;\n\n\t\tled-boot = &power;\n\t\tled-failsafe = &power;\n\t\tled-running = &power;\n\t\tled-upgrade = &power;\n\t};\n\n\tchosen {\n\t\tbootargs = \"rootfstype=squashfs noinitrd\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\t\tpinctrl-0 = <&button_pins>;\n\t\tpinctrl-names = \"default\";\n\n\t\twifi {\n\t\t\tlabel = \"wifi\";\n\t\t\tgpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RFKILL>;\n\t\t\tdebounce-interval = <60>;\n\t\t\twakeup-source;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tdebounce-interval = <60>;\n\t\t\twakeup-source;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tdebounce-interval = <60>;\n\t\t\twakeup-source;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tpinctrl-0 = <&led_pins>;\n\t\tpinctrl-names = \"default\";\n\n\t\tusb1 {\n\t\t\tlabel = \"amber:usb1\";\n\t\t\tgpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tusb3 {\n\t\t\tlabel = \"amber:usb3\";\n\t\t\tgpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tstatus {\n\t\t\tlabel = \"amber:status\";\n\t\t\tgpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tinternet {\n\t\t\tlabel = \"white:internet\";\n\t\t\tgpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\twan {\n\t\t\tlabel = \"white:wan\";\n\t\t\tgpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"white:wps\";\n\t\t\tgpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tesata {\n\t\t\tlabel = \"white:esata\";\n\t\t\tgpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tpower: power {\n\t\t\tlabel = \"white:power\";\n\t\t\tgpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"keep\";\n\t\t};\n\n\t\twifi {\n\t\t\tlabel = \"white:wifi\";\n\t\t\tgpios = <&qcom_pinmux 64 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&adm_dma {\n\tstatus = \"okay\";\n};\n\n&qcom_pinmux {\n\tbutton_pins: button_pins {\n\t\tmux {\n\t\t\tpins = \"gpio6\", \"gpio54\", \"gpio65\";\n\t\t\tfunction = \"gpio\";\n\t\t\tdrive-strength = <2>;\n\t\t\tbias-pull-up;\n\t\t};\n\t};\n\n\tled_pins: led_pins {\n\t\tmux {\n\t\t\tpins = \"gpio7\", \"gpio8\", \"gpio9\", \"gpio22\", \"gpio23\",\n\t\t\t\t\"gpio24\",\"gpio26\", \"gpio53\", \"gpio64\";\n\t\t\tfunction = \"gpio\";\n\t\t\tdrive-strength = <2>;\n\t\t\tbias-pull-up;\n\t\t};\n\t};\n\n\tusb0_pwr_en_pins: usb0_pwr_en_pins {\n\t\tmux {\n\t\t\tpins = \"gpio15\";\n\t\t\tfunction = \"gpio\";\n\t\t\tdrive-strength = <12>;\n\t\t\tbias-pull-down;\n\t\t\toutput-high;\n\t\t};\n\t};\n\n\tusb1_pwr_en_pins: usb1_pwr_en_pins {\n\t\tmux {\n\t\t\tpins = \"gpio16\", \"gpio68\";\n\t\t\tfunction = \"gpio\";\n\t\t\tdrive-strength = <12>;\n\t\t\tbias-pull-down;\n\t\t\toutput-high;\n\t\t};\n\t};\n};\n\n&sata_phy {\n\tstatus = \"okay\";\n};\n\n&sata {\n\tstatus = \"okay\";\n};\n\n&usb3_0 {\n\tstatus = \"okay\";\n\n\tpinctrl-0 = <&usb0_pwr_en_pins>;\n\tpinctrl-names = \"default\";\n};\n\n&usb3_1 {\n\tstatus = \"okay\";\n\n\tpinctrl-0 = <&usb1_pwr_en_pins>;\n\tpinctrl-names = \"default\";\n};\n\n&pcie0 {\n\tstatus = \"okay\";\n\treset-gpio = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>;\n\tpinctrl-0 = <&pcie0_pins>;\n\tpinctrl-names = \"default\";\n\n\tbridge@0,0 {\n\t\treg = <0x00000000 0 0 0 0>;\n\t\t#address-cells = <3>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\twifi@1,0 {\n\t\t\tcompatible = \"pci168c,0040\";\n\t\t\treg = <0x00010000 0 0 0 0>;\n\n\t\t\tnvmem-cells = <&macaddr_art_6>, <&precal_art_1000>;\n\t\t\tnvmem-cell-names = \"mac-address\", \"pre-calibration\";\n\t\t\tmac-address-increment = <(1)>;\n\t\t};\n\t};\n};\n\n&pcie1 {\n\tstatus = \"okay\";\n\treset-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;\n\tpinctrl-0 = <&pcie1_pins>;\n\tpinctrl-names = \"default\";\n\tmax-link-speed = <1>;\n\n\tbridge@0,0 {\n\t\treg = <0x00000000 0 0 0 0>;\n\t\t#address-cells = <3>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\twifi@1,0 {\n\t\t\tcompatible = \"pci168c,0040\";\n\t\t\treg = <0x00010000 0 0 0 0>;\n\n\t\t\tnvmem-cells = <&macaddr_art_6>, <&precal_art_5000>;\n\t\t\tnvmem-cell-names = \"mac-address\", \"pre-calibration\";\n\t\t\tmac-address-increment = <(2)>;\n\t\t};\n\t};\n};\n\n&nand {\n\tstatus = \"okay\";\n\n\tpinctrl-0 = <&nand_pins>;\n\tpinctrl-names = \"default\";\n\n\tnand@0 {\n\t\treg = <0>;\n\t\tcompatible = \"qcom,nandcs\";\n\n\t\tnand-ecc-strength = <4>;\n\t\tnand-bus-width = <8>;\n\t\tnand-ecc-step-size = <512>;\n\n\t\tnand-is-boot-medium;\n\t\tqcom,boot_pages_size = <0x1180000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tqcadata@0 {\n\t\t\t\tlabel = \"qcadata\";\n\t\t\t\treg = <0x0000000 0x0c80000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tAPPSBL@c80000 {\n\t\t\t\tlabel = \"APPSBL\";\n\t\t\t\treg = <0x0c80000 0x0500000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tAPPSBLENV@1180000 {\n\t\t\t\tlabel = \"APPSBLENV\";\n\t\t\t\treg = <0x1180000 0x0080000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tart@1200000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0x1200000 0x0140000>;\n\t\t\t\tread-only;\n\t\t\t\tcompatible = \"nvmem-cells\";\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\n\t\t\t\tmacaddr_art_0: macaddr@0 {\n\t\t\t\t\treg = <0x0 0x6>;\n\t\t\t\t};\n\n\t\t\t\tmacaddr_art_6: macaddr@6 {\n\t\t\t\t\treg = <0x6 0x6>;\n\t\t\t\t};\n\n\t\t\t\tprecal_art_1000: precal@1000 {\n\t\t\t\t\treg = <0x1000 0x2f20>;\n\t\t\t\t};\n\n\t\t\t\tprecal_art_5000: precal@5000 {\n\t\t\t\t\treg = <0x5000 0x2f20>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tartbak: art@1340000 {\n\t\t\t\tlabel = \"artbak\";\n\t\t\t\treg = <0x1340000 0x0140000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tkernel@1480000 {\n\t\t\t\tlabel = \"kernel\";\n\t\t\t\treg = <0x1480000 0x0400000>;\n\t\t\t};\n\n\t\t\tubi@1880000 {\n\t\t\t\tlabel = \"ubi\";\n\t\t\t\treg = <0x1880000 0x6080000>;\n\t\t\t};\n\n\t\t\treserve@7900000 {\n\t\t\t\tlabel = \"reserve\";\n\t\t\t\treg = <0x7900000 0x0700000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tpinctrl-0 = <&mdio0_pins>;\n\tpinctrl-names = \"default\";\n\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t\tqca,ar8327-initvals = <\n\t\t\t0x00004 0x7600000   /* PAD0_MODE */\n\t\t\t0x00008 0x1000000   /* PAD5_MODE */\n\t\t\t0x0000c 0x80        /* PAD6_MODE */\n\t\t\t0x000e4 0xaa545     /* MAC_POWER_SEL */\n\t\t\t0x000e0 0xc74164de  /* SGMII_CTRL */\n\t\t\t0x0007c 0x4e        /* PORT0_STATUS */\n\t\t\t0x00094 0x4e        /* PORT6_STATUS */\n\t\t\t>;\n\t};\n\n\tphy4: ethernet-phy@4 {\n\t\treg = <4>;\n\t};\n};\n\n&gmac1 {\n\tstatus = \"okay\";\n\tphy-mode = \"rgmii\";\n\tqcom,id = <1>;\n\n\tpinctrl-0 = <&rgmii2_pins>;\n\tpinctrl-names = \"default\";\n\n\tnvmem-cells = <&macaddr_art_6>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tfixed-link {\n\t\tspeed = <1000>;\n\t\tfull-duplex;\n\t};\n};\n\n&gmac2 {\n\tstatus = \"okay\";\n\tphy-mode = \"sgmii\";\n\tqcom,id = <2>;\n\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tfixed-link {\n\t\tspeed = <1000>;\n\t\tfull-duplex;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-unifi-ac-hd.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qcom-ipq8064-v2.0.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"Ubiquiti UniFi AC HD\";\n\tcompatible = \"ubnt,unifi-ac-hd\", \"qcom,ipq8064\";\n\n\taliases {\n\t\tlabel-mac-device = &gmac2;\n\t\tled-boot = &led_dome_white;\n\t\tled-failsafe = &led_dome_white;\n\t\tled-running = &led_dome_blue;\n\t\tled-upgrade = &led_dome_blue;\n\t\tmdio-gpio0 = &mdio0;\n\t\tethernet0 = &gmac2;\n\t\tethernet1 = &gmac1;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tpinctrl-0 = <&led_pins>;\n\t\tpinctrl-names = \"default\";\n\n\t\tled_dome_blue: dome_blue {\n\t\t\tlabel = \"blue:dome\";\n\t\t\tgpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tled_dome_white: dome_white {\n\t\t\tlabel = \"white:dome\";\n\t\t\tgpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\t\tpinctrl-0 = <&button_pins>;\n\t\tpinctrl-names = \"default\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&qcom_pinmux 68 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tdebounce-interval = <60>;\n\t\t\twakeup-source;\n\t\t};\n\t};\n};\n\n&qcom_pinmux {\n\tbutton_pins: button_pins {\n\t\tmux {\n\t\t\tpins = \"gpio68\";\n\t\t\tfunction = \"gpio\";\n\t\t\tdrive-strength = <2>;\n\t\t\tbias-pull-up;\n\t\t};\n\t};\n\n\tled_pins: led_pins {\n\t\tmux {\n\t\t\tpins = \"gpio9\", \"gpio53\";\n\t\t\tfunction = \"gpio\";\n\t\t\tdrive-strength = <2>;\n\t\t\tbias-pull-down;\n\t\t\toutput-low;\n\t\t};\n\t};\n\n\tspi_pins: spi_pins {\n\t\tmux {\n\t\t\tpins = \"gpio18\", \"gpio19\", \"gpio21\";\n\t\t\tfunction = \"gsbi5\";\n\t\t\tdrive-strength = <10>;\n\t\t\tbias-none;\n\t\t};\n\n\t\tcs {\n\t\t\tpins = \"gpio20\";\n\t\t\tdrive-strength = <12>;\n\t\t};\n\t};\n};\n\n&CPU_SPC {\n\tstatus = \"disabled\";\n};\n\n&gsbi5 {\n\tstatus = \"okay\";\n\n\tqcom,mode = <GSBI_PROT_SPI>;\n\n\tspi@1a280000 {\n\t\tstatus = \"okay\";\n\n\t\tpinctrl-0 = <&spi_pins>;\n\t\tpinctrl-names = \"default\";\n\t\tcs-gpios = <&qcom_pinmux 20 0>;\n\n\t\tflash@0 {\n\t\t\tcompatible = \"mx25u25635f\", \"jedec,spi-nor\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\t\t\tspi-max-frequency = <50000000>;\n\t\t\treg = <0>;\n\t\t\tm25p,fast-read;\n\n\t\t\tpartitions {\n\t\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\n\t\t\t\tpartition@0 {\n\t\t\t\t\tlabel = \"SBL1\";\n\t\t\t\t\treg = <0x0 0x20000>;\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\tpartition@20000 {\n\t\t\t\t\tlabel = \"MIBIB\";\n\t\t\t\t\treg = <0x20000 0x10000>;\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\tpartition@30000 {\n\t\t\t\t\tlabel = \"SBL2\";\n\t\t\t\t\treg = <0x30000 0x20000>;\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\tpartition@50000 {\n\t\t\t\t\tlabel = \"SBL3\";\n\t\t\t\t\treg = <0x50000 0x30000>;\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\tpartition@80000 {\n\t\t\t\t\tlabel = \"DDRCONFIG\";\n\t\t\t\t\treg = <0x80000 0x10000>;\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\tpartition@90000 {\n\t\t\t\t\tlabel = \"SSD\";\n\t\t\t\t\treg = <0x90000 0x10000>;\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\tpartition@a0000 {\n\t\t\t\t\tlabel = \"TZ\";\n\t\t\t\t\treg = <0xa0000 0x30000>;\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\tpartition@d0000 {\n\t\t\t\t\tlabel = \"RPM\";\n\t\t\t\t\treg = <0xd0000 0x20000>;\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\tpartition@f0000 {\n\t\t\t\t\tlabel = \"APPSBL\";\n\t\t\t\t\treg = <0xf0000 0xc0000>;\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\tpartition@1b0000 {\n\t\t\t\t\tlabel = \"APPSBLENV\";\n\t\t\t\t\treg = <0x1b0000 0x10000>;\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\teeprom: partition@1c0000 {\n\t\t\t\t\tlabel = \"EEPROM\";\n\t\t\t\t\treg = <0x1c0000 0x10000>;\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\tpartition@1d0000 {\n\t\t\t\t\tlabel = \"bootselect\";\n\t\t\t\t\treg = <0x1d0000 0x10000>;\n\t\t\t\t};\n\n\t\t\t\tpartition@1e0000 {\n\t\t\t\t\tcompatible = \"denx,fit\";\n\t\t\t\t\tlabel = \"firmware\";\n\t\t\t\t\treg = <0x1e0000 0xe70000>;\n\t\t\t\t};\n\n\t\t\t\tpartition@1050000 {\n\t\t\t\t\tlabel = \"kernel1\";\n\t\t\t\t\treg = <0x1050000 0xe70000>;\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\tpartition@1ec0000 {\n\t\t\t\t\tlabel = \"debug\";\n\t\t\t\t\treg = <0x1ec0000 0x100000>;\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\tpartition@1fc0000 {\n\t\t\t\t\tlabel = \"cfg\";\n\t\t\t\t\treg = <0x1fc0000 0x40000>;\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t};\n};\n\n&adm_dma {\n\tstatus = \"okay\";\n};\n\n&nand {\n\tstatus = \"okay\";\n\n\tpinctrl-0 = <&nand_pins>;\n\tpinctrl-names = \"default\";\n\tnand-ecc-strength = <4>;\n\tnand-bus-width = <8>;\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tpinctrl-0 = <&mdio0_pins>;\n\tpinctrl-names = \"default\";\n\n\tphy4: ethernet-phy@4 {\n\t\treg = <4>;\n\t};\n\n\tphy5: ethernet-phy@5 {\n\t\treg = <5>;\n\t};\n};\n\n&gmac1 {\n\tstatus = \"okay\";\n\n\tmdiobus = <&mdio0>;\n\tphy-handle = <&phy5>;\n\tphy-mode = \"sgmii\";\n\tqcom,id = <1>;\n\n\tnvmem-cells = <&macaddr_eeprom_6>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&gmac2 {\n\tstatus = \"okay\";\n\n\tmdiobus = <&mdio0>;\n\tphy-handle = <&phy4>;\n\tphy-mode = \"sgmii\";\n\tqcom,id = <2>;\n\n\tnvmem-cells = <&macaddr_eeprom_0>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&pcie0 {\n\tstatus = \"okay\";\n};\n\n&pcie1 {\n\tstatus = \"okay\";\n};\n\n&tcsr {\n\tstatus = \"okay\";\n};\n\n&hs_phy_0 {\n\tstatus = \"okay\";\n};\n\n&ss_phy_0 {\n\tstatus = \"okay\";\n};\n\n&usb3_0 {\n\tstatus = \"okay\";\n};\n\n&hs_phy_1 {\n\tstatus = \"okay\";\n};\n\n&ss_phy_1 {\n\tstatus = \"okay\";\n};\n\n&usb3_1 {\n\tstatus = \"okay\";\n};\n\n&eeprom {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_eeprom_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n\n\tmacaddr_eeprom_6: macaddr@6 {\n\t\treg = <0x6 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi",
    "content": "#include \"qcom-ipq8064.dtsi\"\n\n/ {\n\taliases {\n\t\tserial0 = &gsbi4_serial;\n\t};\n\n\tchosen {\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\treserved-memory {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tranges;\n\n\t\trsvd@41200000 {\n\t\t\treg = <0x41200000 0x300000>;\n\t\t\tno-map;\n\t\t};\n\t};\n};\n\n&gsbi4 {\n\tqcom,mode = <GSBI_PROT_I2C_UART>;\n\tstatus = \"okay\";\n\n\tserial@16340000 {\n\t\tstatus = \"okay\";\n\t};\n\t/*\n\t* The i2c device on gsbi4 should not be enabled.\n\t* On ipq806x designs gsbi4 i2c is meant for exclusive\n\t* RPM usage. Turning this on in kernel manifests as\n\t* i2c failure for the RPM.\n\t*/\n};\n\n&CPU_SPC {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\tcompatible = \"qcom,pcie-ipq8064-v2\";\n};\n\n&pcie1 {\n\tcompatible = \"qcom,pcie-ipq8064-v2\";\n};\n\n&pcie2 {\n\tcompatible = \"qcom,pcie-ipq8064-v2\";\n};\n\n&sata {\n\tports-implemented = <0x1>;\n};\n\n&ss_phy_0 {\n\tqcom,rx-eq = <2>;\n\tqcom,tx-deamp_3_5db = <32>;\n\tqcom,mpll = <5>;\n};\n\n&ss_phy_1 {\n\tqcom,rx-eq = <2>;\n\tqcom,tx-deamp_3_5db = <32>;\n\tqcom,mpll = <5>;\n};\n"
  },
  {
    "path": "target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-vr2600v.dts",
    "content": "#include \"qcom-ipq8064-v2.0.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"TP-Link Archer VR2600v\";\n\tcompatible = \"tplink,vr2600v\", \"qcom,ipq8064\";\n\n\tmemory@0 {\n\t\treg = <0x42000000 0x1e000000>;\n\t\tdevice_type = \"memory\";\n\t};\n\n\taliases {\n\t\tmdio-gpio0 = &mdio0;\n\n\t\tled-boot = &power;\n\t\tled-failsafe = &general;\n\t\tled-running = &power;\n\t\tled-upgrade = &general;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\t\tpinctrl-0 = <&button_pins>;\n\t\tpinctrl-names = \"default\";\n\n\t\twifi {\n\t\t\tlabel = \"wifi\";\n\t\t\tgpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RFKILL>;\n\t\t\tdebounce-interval = <60>;\n\t\t\twakeup-source;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&qcom_pinmux 64 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tdebounce-interval = <60>;\n\t\t\twakeup-source;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tdebounce-interval = <60>;\n\t\t\twakeup-source;\n\t\t};\n\n\t\tdect {\n\t\t\tlabel = \"dect\";\n\t\t\tgpios = <&qcom_pinmux 67 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_PHONE>;\n\t\t\tdebounce-interval = <60>;\n\t\t\twakeup-source;\n\t\t};\n\n\t\tledswitch {\n\t\t\tlabel = \"ledswitch\";\n\t\t\tgpios = <&qcom_pinmux 68 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_LIGHTS_TOGGLE>;\n\t\t\tdebounce-interval = <60>;\n\t\t\twakeup-source;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tpinctrl-0 = <&led_pins>;\n\t\tpinctrl-names = \"default\";\n\n\t\tdsl {\n\t\t\tlabel = \"white:dsl\";\n\t\t\tgpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tusb {\n\t\t\tlabel = \"white:usb\";\n\t\t\tgpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tlan {\n\t\t\tlabel = \"white:lan\";\n\t\t\tgpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\twlan2g {\n\t\t\tlabel = \"white:wlan2g\";\n\t\t\tgpios = <&qcom_pinmux 16 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\twlan5g {\n\t\t\tlabel = \"white:wlan5g\";\n\t\t\tgpios = <&qcom_pinmux 17 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tpower: power {\n\t\t\tlabel = \"white:power\";\n\t\t\tgpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"keep\";\n\t\t};\n\n\t\tphone {\n\t\t\tlabel = \"white:phone\";\n\t\t\tgpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\twan {\n\t\t\tlabel = \"white:wan\";\n\t\t\tgpios = <&qcom_pinmux 56 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tgeneral: general {\n\t\t\tlabel = \"white:general\";\n\t\t\tgpios = <&qcom_pinmux 66 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&qcom_pinmux {\n\tled_pins: led_pins {\n\t\tmux {\n\t\t\tpins = \"gpio7\", \"gpio8\", \"gpio9\", \"gpio16\", \"gpio17\",\n\t\t\t\t\"gpio26\", \"gpio53\", \"gpio56\", \"gpio66\";\n\t\t\tfunction = \"gpio\";\n\t\t\tdrive-strength = <2>;\n\t\t\tbias-pull-up;\n\t\t};\n\t};\n\n\tbutton_pins: button_pins {\n\t\tmux {\n\t\t\tpins = \"gpio54\", \"gpio64\", \"gpio65\", \"gpio67\", \"gpio68\";\n\t\t\tfunction = \"gpio\";\n\t\t\tdrive-strength = <2>;\n\t\t\tbias-pull-up;\n\t\t};\n\t};\n\n\tspi_pins: spi_pins {\n\t\tmux {\n\t\t\tpins = \"gpio18\", \"gpio19\", \"gpio21\";\n\t\t\tfunction = \"gsbi5\";\n\t\t\tbias-pull-down;\n\t\t};\n\n\t\tdata {\n\t\t\tpins = \"gpio18\", \"gpio19\";\n\t\t\tdrive-strength = <10>;\n\t\t};\n\n\t\tcs {\n\t\t\tpins = \"gpio20\";\n\t\t\tdrive-strength = <10>;\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tclk {\n\t\t\tpins = \"gpio21\";\n\t\t\tdrive-strength = <12>;\n\t\t};\n\t};\n};\n\n&gsbi5 {\n\tqcom,mode = <GSBI_PROT_SPI>;\n\tstatus = \"okay\";\n\n\tspi4: spi@1a280000 {\n\t\tstatus = \"okay\";\n\n\t\tpinctrl-0 = <&spi_pins>;\n\t\tpinctrl-names = \"default\";\n\n\t\tcs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>;\n\n\t\tflash@0 {\n\t\t\tcompatible = \"jedec,spi-nor\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\t\t\tspi-max-frequency = <50000000>;\n\t\t\treg = <0>;\n\n\t\t\tpartitions {\n\t\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\n\t\t\t\tpartition@0 {\n\t\t\t\t\tlabel = \"SBL1\";\n\t\t\t\t\treg = <0x0 0x20000>;\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\tpartition@20000 {\n\t\t\t\t\tlabel = \"MIBIB\";\n\t\t\t\t\treg = <0x20000 0x20000>;\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\tpartition@40000 {\n\t\t\t\t\tlabel = \"SBL2\";\n\t\t\t\t\treg = <0x40000 0x40000>;\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\tpartition@80000 {\n\t\t\t\t\tlabel = \"SBL3\";\n\t\t\t\t\treg = <0x80000 0x80000>;\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\tpartition@100000 {\n\t\t\t\t\tlabel = \"DDRCONFIG\";\n\t\t\t\t\treg = <0x100000 0x10000>;\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\tpartition@110000 {\n\t\t\t\t\tlabel = \"SSD\";\n\t\t\t\t\treg = <0x110000 0x10000>;\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\tpartition@120000 {\n\t\t\t\t\tlabel = \"TZ\";\n\t\t\t\t\treg = <0x120000 0x80000>;\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\tpartition@1a0000 {\n\t\t\t\t\tlabel = \"RPM\";\n\t\t\t\t\treg = <0x1a0000 0x80000>;\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\tpartition@220000 {\n\t\t\t\t\tlabel = \"APPSBL\";\n\t\t\t\t\treg = <0x220000 0x80000>;\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\tpartition@2a0000 {\n\t\t\t\t\tlabel = \"APPSBLENV\";\n\t\t\t\t\treg = <0x2a0000 0x40000>;\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\tpartition@2e0000 {\n\t\t\t\t\tlabel = \"OLDART\";\n\t\t\t\t\treg = <0x2e0000 0x40000>;\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\tpartition@320000 {\n\t\t\t\t\tlabel = \"firmware\";\n\t\t\t\t\treg = <0x320000 0xc60000>;\n\t\t\t\t\tcompatible = \"openwrt,uimage\";\n\t\t\t\t\topenwrt,offset = <512>; /* account for pad-extra 512 */\n\t\t\t\t};\n\n\t\t\t\t/* hole 0xf80000 - 0xfaf100 */\n\n\t\t\t\tpartition@faf100 {\n\t\t\t\t\tlabel = \"default-mac\";\n\t\t\t\t\treg = <0xfaf100 0x00200>;\n\t\t\t\t\tread-only;\n\n\t\t\t\t\tcompatible = \"nvmem-cells\";\n\t\t\t\t\t#address-cells = <1>;\n\t\t\t\t\t#size-cells = <1>;\n\n\t\t\t\t\tmacaddr_defaultmac_0: macaddr@0 {\n\t\t\t\t\t\treg = <0x0 0x6>;\n\t\t\t\t\t};\n\t\t\t\t};\n\n\t\t\t\tpartition@fc0000 {\n\t\t\t\t\tlabel = \"ART\";\n\t\t\t\t\treg = <0xfc0000 0x40000>;\n\t\t\t\t\tread-only;\n\n\t\t\t\t\tcompatible = \"nvmem-cells\";\n\t\t\t\t\t#address-cells = <1>;\n\t\t\t\t\t#size-cells = <1>;\n\n\t\t\t\t\tprecal_ART_1000: precal@1000 {\n\t\t\t\t\t\treg = <0x1000 0x2f20>;\n\t\t\t\t\t};\n\n\t\t\t\t\tprecal_ART_5000: precal@5000 {\n\t\t\t\t\t\treg = <0x5000 0x2f20>;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t};\n};\n\n&usb3_0 {\n\tstatus = \"okay\";\n};\n\n&usb3_1 {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\tstatus = \"okay\";\n\n\tbridge@0,0 {\n\t\treg = <0x00000000 0 0 0 0>;\n\t\t#address-cells = <3>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\twifi@1,0 {\n\t\t\tcompatible = \"pci168c,0040\";\n\t\t\treg = <0x00010000 0 0 0 0>;\n\n\t\t\tnvmem-cells = <&macaddr_defaultmac_0>, <&precal_ART_1000>;\n\t\t\tnvmem-cell-names = \"mac-address\", \"pre-calibration\";\n\t\t\tmac-address-increment = <(-1)>;\n\t\t};\n\t};\n};\n\n&pcie1 {\n\tstatus = \"okay\";\n\tmax-link-speed = <1>;\n\n\tbridge@0,0 {\n\t\treg = <0x00000000 0 0 0 0>;\n\t\t#address-cells = <3>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\twifi@1,0 {\n\t\t\tcompatible = \"pci168c,0040\";\n\t\t\treg = <0x00010000 0 0 0 0>;\n\n\t\t\tnvmem-cells = <&macaddr_defaultmac_0>, <&precal_ART_5000>;\n\t\t\tnvmem-cell-names = \"mac-address\", \"pre-calibration\";\n\t\t};\n\t};\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tpinctrl-0 = <&mdio0_pins>;\n\tpinctrl-names = \"default\";\n\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t\tqca,ar8327-initvals = <\n\t\t\t0x00004 0x7600000   /* PAD0_MODE */\n\t\t\t0x00008 0x1000000   /* PAD5_MODE */\n\t\t\t0x0000c 0x80        /* PAD6_MODE */\n\t\t\t0x000e4 0x6a545     /* MAC_POWER_SEL */\n\t\t\t0x000e0 0xc74164de  /* SGMII_CTRL */\n\t\t\t0x0007c 0x4e        /* PORT0_STATUS */\n\t\t\t0x00094 0x4e        /* PORT6_STATUS */\n\t\t\t>;\n\t};\n\n\tphy4: ethernet-phy@4 {\n\t\treg = <4>;\n\t};\n};\n\n&gmac1 {\n\tstatus = \"okay\";\n\tphy-mode = \"rgmii\";\n\tqcom,id = <1>;\n\n\tpinctrl-0 = <&rgmii2_pins>;\n\tpinctrl-names = \"default\";\n\n\tnvmem-cells = <&macaddr_defaultmac_0>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <1>;\n\n\tfixed-link {\n\t\tspeed = <1000>;\n\t\tfull-duplex;\n\t};\n};\n\n&gmac2 {\n\tstatus = \"okay\";\n\tphy-mode = \"sgmii\";\n\tqcom,id = <2>;\n\n\tnvmem-cells = <&macaddr_defaultmac_0>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tfixed-link {\n\t\tspeed = <1000>;\n\t\tfull-duplex;\n\t};\n};\n\n&adm_dma {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-wg2600hp.dts",
    "content": "#include \"qcom-ipq8064-v2.0.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"NEC Aterm WG2600HP\";\n\tcompatible = \"nec,wg2600hp\", \"qcom,ipq8064\";\n\n\tmemory@0 {\n\t\treg = <0x42000000 0x1e000000>;\n\t\tdevice_type = \"memory\";\n\t};\n\n\taliases {\n\t\tmdio-gpio0 = &mdio0;\n\n\t\tled-boot = &power_green;\n\t\tled-failsafe = &power_red;\n\t\tled-running = &power_green;\n\t\tled-upgrade = &power_green;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\t\tpinctrl-0 = <&button_pins>;\n\t\tpinctrl-names = \"default\";\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&qcom_pinmux 16 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tdebounce-interval = <60>;\n\t\t\twakeup-source;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tdebounce-interval = <60>;\n\t\t\twakeup-source;\n\t\t};\n\n\t\tbridge {\n\t\t\tlabel = \"bridge\";\n\t\t\tgpios = <&qcom_pinmux 24 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_0>;\n\t\t\tlinux,input-type = <EV_SW>;\n\t\t\tdebounce-interval = <60>;\n\t\t\twakeup-source;\n\t\t};\n\n\t\tconverter {\n\t\t\tlabel = \"converter\";\n\t\t\tgpios = <&qcom_pinmux 25 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_0>;\n\t\t\tlinux,input-type = <EV_SW>;\n\t\t\tdebounce-interval = <60>;\n\t\t\twakeup-source;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tpinctrl-0 = <&led_pins>;\n\t\tpinctrl-names = \"default\";\n\n\t\tconverter_green {\n\t\t\tlabel = \"green:converter\";\n\t\t\tgpios = <&qcom_pinmux 6 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tpower_red: power_red {\n\t\t\tlabel = \"red:power\";\n\t\t\tgpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tactive_green {\n\t\t\tlabel = \"green:active\";\n\t\t\tgpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tactive_red {\n\t\t\tlabel = \"red:active\";\n\t\t\tgpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tpower_green: power_green {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&qcom_pinmux 14 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tconverter_red {\n\t\t\tlabel = \"red:converter\";\n\t\t\tgpios = <&qcom_pinmux 15 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\twlan2g_green {\n\t\t\tlabel = \"green:wlan2g\";\n\t\t\tgpios = <&qcom_pinmux 55 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\twlan2g_red {\n\t\t\tlabel = \"red:wlan2g\";\n\t\t\tgpios = <&qcom_pinmux 56 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\twlan5g_green {\n\t\t\tlabel = \"green:wlan5g\";\n\t\t\tgpios = <&qcom_pinmux 57 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\twlan5g_red {\n\t\t\tlabel = \"red:wlan5g\";\n\t\t\tgpios = <&qcom_pinmux 58 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\ttv_green {\n\t\t\tlabel = \"green:tv\";\n\t\t\tgpios = <&qcom_pinmux 64 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\ttv_red {\n\t\t\tlabel = \"red:tv\";\n\t\t\tgpios = <&qcom_pinmux 65 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&CPU_SPC {\n\tstatus = \"disabled\";\n};\n\n&adm_dma {\n\tstatus = \"okay\";\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tpinctrl-0 = <&mdio0_pins>;\n\tpinctrl-names = \"default\";\n\n\tethernet-phy@0 {\n\t\treg = <0>;\n\t\tqca,ar8327-initvals = <\n\t\t\t0x00004 0x06000000  /* PAD0_MODE */\n\t\t\t0x0000c 0x00080080  /* PAD6_MODE */\n\t\t\t0x000e4 0x0006a545  /* MAC_POWER_SEL */\n\t\t\t0x000e0 0xc74164de  /* SGMII_CTRL */\n\t\t\t0x0007c 0x0000004e  /* PORT0_STATUS */\n\t\t\t0x00094 0x0000004e  /* PORT6_STATUS */\n\t\t\t>;\n\t};\n\n\tethernet-phy@4 {\n\t\treg = <4>;\n\t};\n};\n\n&gmac1 {\n\tstatus = \"okay\";\n\n\tphy-mode = \"rgmii\";\n\tqcom,id = <1>;\n\n\tpinctrl-0 = <&rgmii2_pins>;\n\tpinctrl-names = \"default\";\n\n\tnvmem-cells = <&macaddr_PRODUCTDATA_6>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tfixed-link {\n\t\tspeed = <1000>;\n\t\tfull-duplex;\n\t};\n};\n\n&gmac2 {\n\tstatus = \"okay\";\n\n\tphy-mode = \"sgmii\";\n\tqcom,id = <2>;\n\n\tnvmem-cells = <&macaddr_PRODUCTDATA_0>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tfixed-link {\n\t\tspeed = <1000>;\n\t\tfull-duplex;\n\t};\n};\n\n&gsbi5 {\n\tstatus = \"okay\";\n\n\tqcom,mode = <GSBI_PROT_SPI>;\n\n\tspi@1a280000 {\n\t\tstatus = \"okay\";\n\n\t\tpinctrl-0 = <&spi_pins>;\n\t\tpinctrl-names = \"default\";\n\n\t\tcs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>;\n\n\t\tflash@0 {\n\t\t\tcompatible = \"jedec,spi-nor\";\n\t\t\tspi-max-frequency = <50000000>;\n\t\t\treg = <0>;\n\n\t\t\tpartitions {\n\t\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\n\t\t\t\tSBL1@0 {\n\t\t\t\t\tlabel = \"SBL1\";\n\t\t\t\t\treg = <0x0 0x20000>;\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\tMIBIB@20000 {\n\t\t\t\t\tlabel = \"MIBIB\";\n\t\t\t\t\treg = <0x20000 0x20000>;\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\tSBL2@40000 {\n\t\t\t\t\tlabel = \"SBL2\";\n\t\t\t\t\treg = <0x40000 0x40000>;\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\tSBL3@80000 {\n\t\t\t\t\tlabel = \"SBL3\";\n\t\t\t\t\treg = <0x80000 0x80000>;\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\tDDRCONFIG@100000 {\n\t\t\t\t\tlabel = \"DDRCONFIG\";\n\t\t\t\t\treg = <0x100000 0x10000>;\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\tSSD@110000 {\n\t\t\t\t\tlabel = \"SSD\";\n\t\t\t\t\treg = <0x110000 0x10000>;\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\tTZ@120000 {\n\t\t\t\t\tlabel = \"TZ\";\n\t\t\t\t\treg = <0x120000 0x80000>;\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\tRPM@1a0000 {\n\t\t\t\t\tlabel = \"RPM\";\n\t\t\t\t\treg = <0x1a0000 0x80000>;\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\tAPPSBL@220000 {\n\t\t\t\t\tlabel = \"APPSBL\";\n\t\t\t\t\treg = <0x220000 0x80000>;\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\tAPPSBLENV@2a0000 {\n\t\t\t\t\tlabel = \"APPSBLENV\";\n\t\t\t\t\treg = <0x2a0000 0x10000>;\n\t\t\t\t};\n\n\t\t\t\tPRODUCTDATA: PRODUCTDATA@2b0000 {\n\t\t\t\t\tlabel = \"PRODUCTDATA\";\n\t\t\t\t\treg = <0x2b0000 0x30000>;\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\tART@2e0000 {\n\t\t\t\t\tlabel = \"ART\";\n\t\t\t\t\treg = <0x2e0000 0x40000>;\n\t\t\t\t\tread-only;\n\t\t\t\t\tcompatible = \"nvmem-cells\";\n\t\t\t\t\t#address-cells = <1>;\n\t\t\t\t\t#size-cells = <1>;\n\n\t\t\t\t\tprecal_ART_1000: precal@1000 {\n\t\t\t\t\t\treg = <0x1000 0x2f20>;\n\t\t\t\t\t};\n\n\t\t\t\t\tprecal_ART_5000: precal@5000 {\n\t\t\t\t\t\treg = <0x5000 0x2f20>;\n\t\t\t\t\t};\n\t\t\t\t};\n\n\t\t\t\tTP@320000 {\n\t\t\t\t\tlabel = \"TP\";\n\t\t\t\t\treg = <0x320000 0x40000>;\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\tTINY@360000 {\n\t\t\t\t\tlabel = \"TINY\";\n\t\t\t\t\treg = <0x360000 0x500000>;\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\tfirmware@860000 {\n\t\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\t\tlabel = \"firmware\";\n\t\t\t\t\treg = <0x860000 0x17a0000>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t};\n};\n\n&usb3_0 {\n\tstatus = \"okay\";\n\n\tpinctrl-0 = <&usb_pwr_en_pins>;\n\tpinctrl-names = \"default\";\n};\n\n&usb3_1 {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\tstatus = \"okay\";\n\n\tbridge@0,0 {\n\t\treg = <0x00000000 0 0 0 0>;\n\t\t#address-cells = <3>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\twifi@1,0 {\n\t\t\tcompatible = \"pci168c,0040\";\n\t\t\treg = <0x00010000 0 0 0 0>;\n\n\t\t\tnvmem-cells = <&macaddr_PRODUCTDATA_12>, <&precal_ART_1000>;\n\t\t\tnvmem-cell-names = \"mac-address\", \"pre-calibration\";\n\t\t};\n\t};\n};\n\n&pcie1 {\n\tstatus = \"okay\";\n\tmax-link-speed = <1>;\n\n\tbridge@0,0 {\n\t\treg = <0x00000000 0 0 0 0>;\n\t\t#address-cells = <3>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\twifi@1,0 {\n\t\t\tcompatible = \"pci168c,0040\";\n\t\t\treg = <0x00010000 0 0 0 0>;\n\n\t\t\tnvmem-cells = <&macaddr_PRODUCTDATA_c>, <&precal_ART_5000>;\n\t\t\tnvmem-cell-names = \"mac-address\", \"pre-calibration\";\n\t\t};\n\t};\n};\n\n&qcom_pinmux {\n\tbutton_pins: button_pins {\n\t\tmux {\n\t\t\tpins = \"gpio16\", \"gpio54\", \"gpio24\", \"gpio25\";\n\t\t\tfunction = \"gpio\";\n\t\t\tdrive-strength = <2>;\n\t\t\tbias-pull-up;\n\t\t};\n\t};\n\n\tled_pins: led_pins {\n\t\tmux {\n\t\t\tpins = \"gpio6\", \"gpio7\", \"gpio8\", \"gpio9\", \"gpio14\",\n\t\t\t\t\"gpio15\", \"gpio55\", \"gpio56\", \"gpio57\", \"gpio58\",\n\t\t\t\t\"gpio64\", \"gpio65\";\n\t\t\tfunction = \"gpio\";\n\t\t\tdrive-strength = <2>;\n\t\t\tbias-pull-down;\n\t\t};\n\t};\n\n\tspi_pins: spi_pins {\n\t\tmux {\n\t\t\tpins = \"gpio18\", \"gpio19\", \"gpio21\";\n\t\t\tfunction = \"gsbi5\";\n\t\t\tbias-pull-down;\n\t\t};\n\n\t\tdata {\n\t\t\tpins = \"gpio18\", \"gpio19\";\n\t\t\tdrive-strength = <10>;\n\t\t};\n\n\t\tcs {\n\t\t\tpins = \"gpio20\";\n\t\t\tdrive-strength = <10>;\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tclk {\n\t\t\tpins = \"gpio21\";\n\t\t\tdrive-strength = <12>;\n\t\t};\n\t};\n\n\tusb_pwr_en_pins: usb_pwr_en_pins {\n\t\tmux {\n\t\t\tpins = \"gpio22\";\n\t\t\tfunction = \"gpio\";\n\t\t\tdrive-strength = <2>;\n\t\t\tbias-pull-down;\n\t\t\toutput-high;\n\t\t};\n\t};\n};\n\n&PRODUCTDATA {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_PRODUCTDATA_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n\n\tmacaddr_PRODUCTDATA_6: macaddr@6 {\n\t\treg = <0x6 0x6>;\n\t};\n\n\tmacaddr_PRODUCTDATA_c: macaddr@c {\n\t\treg = <0xc 0x6>;\n\t};\n\n\tmacaddr_PRODUCTDATA_12: macaddr@12 {\n\t\treg = <0x12 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-wpq864.dts",
    "content": "// SPDX-License-Identifier: BSD-3-Clause\n/*\n *  Copyright (C) 2017 Christian Mehlis <christian@m3hlis.de>\n *  Copyright (C) 2018 Mathias Kresin <dev@kresin.me>\n *  All rights reserved.\n */\n\n#include \"qcom-ipq8064-v1.0.dtsi\"\n\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/soc/qcom,tcsr.h>\n\n/ {\n\tcompatible = \"compex,wpq864\", \"qcom,ipq8064\";\n\tmodel = \"Compex WPQ864\";\n\n\taliases {\n\t\tmdio-gpio0 = &mdio0;\n\t\tethernet0 = &gmac1;\n\t\tethernet1 = &gmac0;\n\n\t\tled-boot = &led_pass;\n\t\tled-failsafe = &led_fail;\n\t\tled-running = &led_pass;\n\t\tled-upgrade = &led_pass;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tpinctrl-0 = <&led_pins>;\n\t\tpinctrl-names = \"default\";\n\n\t\trss4 {\n\t\t\tlabel = \"green:rss4\";\n\t\t\tgpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\trss3 {\n\t\t\tlabel = \"green:rss3\";\n\t\t\tgpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"keep\";\n\t\t};\n\n\t\trss2 {\n\t\t\tlabel = \"orange:rss2\";\n\t\t\tgpios = <&qcom_pinmux 25 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\trss1 {\n\t\t\tlabel = \"red:rss1\";\n\t\t\tgpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tled_pass: pass {\n\t\t\tlabel = \"green:pass\";\n\t\t\tgpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tled_fail: fail {\n\t\t\tlabel = \"green:fail\";\n\t\t\tgpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tusb {\n\t\t\tlabel = \"green:usb\";\n\t\t\tgpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tusb-pcie {\n\t\t\tlabel = \"green:usb-pcie\";\n\t\t\tgpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\tpinctrl-0 = <&button_pins>;\n\t\tpinctrl-names = \"default\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tdebounce-interval = <60>;\n\t\t\twakeup-source;\n\t\t};\n\t};\n\n\tbeeper {\n\t\tcompatible = \"gpio-beeper\";\n\n\t\tpinctrl-0 = <&beeper_pins>;\n\t\tpinctrl-names = \"default\";\n\n\t\tgpios = <&qcom_pinmux 55 GPIO_ACTIVE_HIGH>;\n\t};\n};\n\n&rpm {\n\tpinctrl-0 = <&rpm_pins>;\n\tpinctrl-names = \"default\";\n};\n\n&nand {\n\tstatus = \"okay\";\n\n\tpinctrl-0 = <&nand_pins>;\n\tpinctrl-names = \"default\";\n\n\tmt29f2g08abbeah4@0 {\n\t\tcompatible = \"qcom,nandcs\";\n\n\t\treg = <0>;\n\n\t\tnand-ecc-strength = <4>;\n\t\tnand-bus-width = <8>;\n\t\tnand-ecc-step-size = <512>;\n\n\t\tnand-is-boot-medium;\n\t\tqcom,boot_pages_size = <0x1180000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tSBL1@0 {\n\t\t\t\tlabel = \"SBL1\";\n\t\t\t\treg = <0x0000000 0x0040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tMIBIB@40000 {\n\t\t\t\tlabel = \"MIBIB\";\n\t\t\t\treg = <0x0040000 0x0140000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tSBL2@180000 {\n\t\t\t\tlabel = \"SBL2\";\n\t\t\t\treg = <0x0180000 0x0140000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tSBL3@2c0000 {\n\t\t\t\tlabel = \"SBL3\";\n\t\t\t\treg = <0x02c0000 0x0280000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tDDRCONFIG@540000 {\n\t\t\t\tlabel = \"DDRCONFIG\";\n\t\t\t\treg = <0x0540000 0x0120000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tSSD@660000 {\n\t\t\t\tlabel = \"SSD\";\n\t\t\t\treg = <0x0660000 0x0120000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tTZ@780000 {\n\t\t\t\tlabel = \"TZ\";\n\t\t\t\treg = <0x0780000 0x0280000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tRPM@a00000 {\n\t\t\t\tlabel = \"RPM\";\n\t\t\t\treg = <0x0a00000 0x0280000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tAPPSBL@c80000 {\n\t\t\t\tlabel = \"APPSBL\";\n\t\t\t\treg = <0x0c80000 0x0500000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tAPPSBLENV@1180000 {\n\t\t\t\tlabel = \"APPSBLENV\";\n\t\t\t\treg = <0x1180000 0x0080000>;\n\t\t\t};\n\n\t\t\tART@1200000 {\n\t\t\t\tlabel = \"ART\";\n\t\t\t\treg = <0x1200000 0x0140000>;\n\t\t\t};\n\n\t\t\tubi@1340000 {\n\t\t\t\tlabel = \"ubi\";\n\t\t\t\treg = <0x1340000 0x4000000>;\n\t\t\t};\n\n\t\t\tBOOTCONFIG@5340000 {\n\t\t\t\tlabel = \"BOOTCONFIG\";\n\t\t\t\treg = <0x5340000 0x0060000>;\n\t\t\t};\n\n\t\t\tSBL2-1@53a0000- {\n\t\t\t\tlabel = \"SBL2_1\";\n\t\t\t\treg = <0x53a0000 0x0140000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tSBL3-1@54e0000 {\n\t\t\t\tlabel = \"SBL3_1\";\n\t\t\t\treg = <0x54e0000 0x0280000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tDDRCONFIG-1@5760000 {\n\t\t\t\tlabel = \"DDRCONFIG_1\";\n\t\t\t\treg = <0x5760000 0x0120000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tSSD-1@5880000 {\n\t\t\t\tlabel = \"SSD_1\";\n\t\t\t\treg = <0x5880000 0x0120000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tTZ-1@59a0000 {\n\t\t\t\tlabel = \"TZ_1\";\n\t\t\t\treg = <0x59a0000 0x0280000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tRPM-1@5c20000 {\n\t\t\t\tlabel = \"RPM_1\";\n\t\t\t\treg = <0x5c20000 0x0280000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tBOOTCONFIG1@5ea0000 {\n\t\t\t\tlabel = \"BOOTCONFIG1\";\n\t\t\t\treg = <0x5ea0000 0x0060000>;\n\t\t\t};\n\n\t\t\tAPPSBL-1@5f00000 {\n\t\t\t\tlabel = \"APPSBL_1\";\n\t\t\t\treg = <0x5f00000 0x0500000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tubi-1@6400000 {\n\t\t\t\tlabel = \"ubi_1\";\n\t\t\t\treg = <0x6400000 0x4000000>;\n\t\t\t};\n\n\t\t\tunused@a400000 {\n\t\t\t\tlabel = \"unused\";\n\t\t\t\treg = <0xa400000 0x5c00000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&adm_dma {\n\tstatus = \"okay\";\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tpinctrl-0 = <&mdio0_pins>;\n\tpinctrl-names = \"default\";\n\n\tethernet-phy@0 {\n\t\treg = <0>;\n\t\tqca,ar8327-initvals = <\n\t\t\t0x00004 0x7600000   /* PAD0_MODE */\n\t\t\t0x00008 0x1000000   /* PAD5_MODE */\n\t\t\t0x0000c 0x80        /* PAD6_MODE */\n\t\t\t0x000e4 0x6a545     /* MAC_POWER_SEL */\n\t\t\t0x000e0 0xc74164de  /* SGMII_CTRL */\n\t\t\t0x0007c 0x4e        /* PORT0_STATUS */\n\t\t\t0x00094 0x4e        /* PORT6_STATUS */\n\t\t\t>;\n\t};\n\n\tethernet-phy@4 {\n\t\treg = <4>;\n\t};\n};\n\n&gmac1 {\n\tstatus = \"okay\";\n\n\tpinctrl-0 = <&rgmii2_pins>;\n\tpinctrl-names = \"default\";\n\n\tphy-mode = \"rgmii\";\n\tqcom,id = <1>;\n\n\tfixed-link {\n\t\tspeed = <1000>;\n\t\tfull-duplex;\n\t};\n};\n\n&gmac2 {\n\tstatus = \"okay\";\n\n\tphy-mode = \"sgmii\";\n\tqcom,id = <2>;\n\n\tfixed-link {\n\t\tspeed = <1000>;\n\t\tfull-duplex;\n\t};\n};\n\n&gsbi4_serial {\n\tpinctrl-0 = <&uart0_pins>;\n\tpinctrl-names = \"default\";\n};\n\n&flash {\n\tcompatible = \"jedec,spi-nor\";\n};\n\n&sata_phy {\n\tstatus = \"disabled\";\n};\n\n&sata {\n\tstatus = \"disabled\";\n};\n\n&ss_phy_0 {\t\t/* USB3 port 0 SS phy */\n\tstatus = \"okay\";\n\n\trx_eq = <2>;\n\ttx_deamp_3_5db = <32>;\n\tmpll = <160>;\n};\n\n&ss_phy_1 {\t\t/* USB3 port 1 SS phy */\n\tstatus = \"okay\";\n\n\trx_eq = <2>;\n\ttx_deamp_3_5db = <32>;\n\tmpll = <160>;\n};\n\n&pcie0 {\n\tstatus = \"okay\";\n\n\t/delete-property/ pinctrl-0;\n\t/delete-property/ pinctrl-names;\n\t/delete-property/ perst-gpios;\n};\n\n&pcie1 {\n\tstatus = \"okay\";\n};\n\n&pcie2 {\n\tstatus = \"okay\";\n\n\t/delete-property/ pinctrl-0;\n\t/delete-property/ pinctrl-names;\n\t/delete-property/ perst-gpios;\n};\n\n&qcom_pinmux {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&state_default>;\n\n\tstate_default: pinctrl0 {\n\t\tpcie0_pcie2_perst {\n\t\t\tpins = \"gpio3\";\n\t\t\tfunction = \"gpio\";\n\t\t\tdrive-strength = <2>;\n\t\t\tbias-disable;\n\t\t\toutput-high;\n\t\t};\n\t};\n\n\tled_pins: led_pins {\n\t\tmux {\n\t\t\tpins = \"gpio7\", \"gpio8\", \"gpio9\", \"gpio22\",\n\t\t\t       \"gpio23\", \"gpio24\", \"gpio25\", \"gpio53\";\n\t\t\tfunction = \"gpio\";\n\t\t\tdrive-strength = <2>;\n\t\t\tbias-pull-up;\n\t\t};\n\t};\n\n\tbutton_pins: button_pins {\n\t\tmux {\n\t\t\tpins = \"gpio54\";\n\t\t\tfunction = \"gpio\";\n\t\t\tdrive-strength = <2>;\n\t\t\tbias-pull-up;\n\t\t};\n\t};\n\n\tbeeper_pins: beeper_pins {\n\t\tmux {\n\t\t\tpins = \"gpio55\";\n\t\t\tfunction = \"gpio\";\n\t\t\tdrive-strength = <2>;\n\t\t\tbias-pull-up;\n\t\t};\n\t};\n\n\trpm_pins: rpm_pins {\n\t\tmux {\n\t\t\tpins = \"gpio12\", \"gpio13\";\n\t\t\tfunction = \"gsbi4\";\n\t\t\tdrive-strength = <10>;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tuart0_pins: uart0_pins {\n\t\tmux {\n\t\t\tpins = \"gpio10\", \"gpio11\";\n\t\t\tfunction = \"gsbi4\";\n\t\t\tdrive-strength = <10>;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tspi_pins: spi_pins {\n\t\tmux {\n\t\t\tpins = \"gpio18\", \"gpio19\";\n\t\t\tfunction = \"gsbi5\";\n\t\t\tdrive-strength = <10>;\n\t\t\tbias-pull-down;\n\t\t};\n\n\t\tclk {\n\t\t\tpins = \"gpio21\";\n\t\t\tfunction = \"gsbi5\";\n\t\t\tdrive-strength = <12>;\n\t\t\tbias-pull-down;\n\t\t};\n\n\t\tcs {\n\t\t\tpins = \"gpio20\";\n\t\t\tfunction = \"gpio\";\n\t\t\tdrive-strength = <10>;\n\t\t\tbias-pull-up;\n\t\t};\n\t};\n};\n\n&usb3_0 {\n\tstatus = \"okay\";\n};\n\n&usb3_1 {\n\tstatus = \"okay\";\n};\n\n&tcsr {\n\tqcom,usb-ctrl-select = <TCSR_USB_SELECT_USB3_DUAL>;\n};\n"
  },
  {
    "path": "target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-wxr-2533dhp.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n#include \"qcom-ipq8064-v2.0.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"Buffalo WXR-2533DHP\";\n\tcompatible = \"buffalo,wxr-2533dhp\", \"qcom,ipq8064\";\n\n\tmemory@42000000 {\n\t\treg = <0x42000000 0x1e000000>;\n\t\tdevice_type = \"memory\";\n\t};\n\n\taliases {\n\t\tled-boot = &power;\n\t\tled-failsafe = &diag;\n\t\tled-running = &power;\n\t\tled-upgrade = &power;\n\t};\n\n\tchosen {\n\t\t/* use \"ubi_rootfs\" volume in \"ubi\" partition as rootfs */\n\t\tbootargs = \"ubi.block=0,1 root=/dev/ubiblock0_1 rootfstype=squashfs\";\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tpinctrl-0 = <&led_pins>;\n\t\tpinctrl-names = \"default\";\n\n\t\tusb {\n\t\t\tlabel = \"green:usb\";\n\t\t\tgpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t\ttrigger-sources = <&hub_port0 &hub_port1>;\n\t\t};\n\n\t\tguestport {\n\t\t\tlabel = \"green:guestport\";\n\t\t\tgpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tdiag: diag {\n\t\t\tlabel = \"orange:diag\";\n\t\t\tgpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tinternet_orange {\n\t\t\tlabel = \"orange:internet\";\n\t\t\tgpios = <&qcom_pinmux 16 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tinternet_white {\n\t\t\tlabel = \"white:internet\";\n\t\t\tgpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\twireless_orange {\n\t\t\tlabel = \"orange:wireless\";\n\t\t\tgpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\twireless_white {\n\t\t\tlabel = \"white:wireless\";\n\t\t\tgpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\trouter_orange {\n\t\t\tlabel = \"orange:router\";\n\t\t\tgpios = <&qcom_pinmux 25 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\trouter_white {\n\t\t\tlabel = \"white:router\";\n\t\t\tgpios = <&qcom_pinmux 26 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tpower: power {\n\t\t\tlabel = \"white:power\";\n\t\t\tgpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\t\tpinctrl-0 = <&button_pins>;\n\t\tpinctrl-names = \"default\";\n\n\t\tpower {\n\t\t\tlabel = \"power\";\n\t\t\tgpios = <&qcom_pinmux 58 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_POWER>;\n\t\t\tdebounce-interval = <60>;\n\t\t\twakeup-source;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tdebounce-interval = <60>;\n\t\t\twakeup-source;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tdebounce-interval = <60>;\n\t\t\twakeup-source;\n\t\t};\n\n\t\teject {\n\t\t\tlabel = \"eject\";\n\t\t\tgpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_EJECTCD>;\n\t\t\tdebounce-interval = <60>;\n\t\t\twakeup-source;\n\t\t};\n\n\t\tguest {\n\t\t\tlabel = \"guest\";\n\t\t\tgpios = <&qcom_pinmux 64 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_0>;\n\t\t\tdebounce-interval = <60>;\n\t\t\twakeup-source;\n\t\t};\n\n\t\tap {\n\t\t\tlabel = \"ap\";\n\t\t\tgpios = <&qcom_pinmux 55 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_1>;\n\t\t\tlinux,input-type = <EV_SW>;\n\t\t\tdebounce-interval = <60>;\n\t\t\twakeup-source;\n\t\t};\n\n\t\trouter {\n\t\t\tlabel = \"router\";\n\t\t\tgpios = <&qcom_pinmux 56 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_1>;\n\t\t\tlinux,input-type = <EV_SW>;\n\t\t\tdebounce-interval = <60>;\n\t\t\twakeup-source;\n\t\t};\n\n\t\tauto {\n\t\t\tlabel = \"auto\";\n\t\t\tgpios = <&qcom_pinmux 57 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_1>;\n\t\t\tlinux,input-type = <EV_SW>;\n\t\t\tdebounce-interval = <60>;\n\t\t\twakeup-source;\n\t\t};\n\t};\n};\n\n&nand {\n\tstatus = \"okay\";\n\n\tpinctrl-0 = <&nand_pins>;\n\tpinctrl-names = \"default\";\n\n\tcs@0 {\n\t\treg = <0>;\n\t\tcompatible = \"qcom,nandcs\";\n\n\t\tnand-ecc-strength = <4>;\n\t\tnand-bus-width = <8>;\n\t\tnand-ecc-step-size = <512>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tubi@0 {\n\t\t\t\tlabel = \"ubi\";\n\t\t\t\treg = <0x0000000 0x4000000>;\n\t\t\t};\n\n\t\t\trootfs_1@4000000 {\n\t\t\t\tlabel = \"rootfs_1\";\n\t\t\t\treg = <0x4000000 0x4000000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&adm_dma {\n\tstatus = \"okay\";\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tpinctrl-0 = <&mdio0_pins>;\n\tpinctrl-names = \"default\";\n\n\tethernet-phy@0 {\n\t\treg = <0>;\n\t\tqca,ar8327-initvals = <\n\t\t\t0x00004 0x07600000  /* PAD0_MODE */\n\t\t\t0x00008 0x01000000  /* PAD5_MODE */\n\t\t\t0x0000c 0x00000080  /* PAD6_MODE */\n\t\t\t0x00050 0xcc35cc35  /* LED_CTRL0 */\n\t\t\t0x00054 0xca35ca35  /* LED_CTRL1 */\n\t\t\t0x00058 0xc935c935  /* LED_CTRL2 */\n\t\t\t0x0005c 0x03ffff00  /* LED_CTRL3 */\n\t\t\t0x000e4 0x0006a545  /* MAC_POWER_SEL */\n\t\t\t0x000e0 0xc74164de  /* SGMII_CTRL */\n\t\t\t0x0007c 0x0000007e  /* PORT0_STATUS */\n\t\t\t0x00094 0x0000007e  /* PORT6_STATUS */\n\t\t\t>;\n\t};\n\n\tethernet-phy@4 {\n\t\treg = <4>;\n\t};\n};\n\n&gmac1 {\n\tstatus = \"okay\";\n\n\tphy-mode = \"rgmii\";\n\tqcom,id = <1>;\n\n\tpinctrl-0 = <&rgmii2_pins>;\n\tpinctrl-names = \"default\";\n\n\tnvmem-cells = <&macaddr_ART_6>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tfixed-link {\n\t\tspeed = <1000>;\n\t\tfull-duplex;\n\t};\n};\n\n&gmac2 {\n\tstatus = \"okay\";\n\n\tphy-mode = \"sgmii\";\n\tqcom,id = <2>;\n\n\tnvmem-cells = <&macaddr_ART_0>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tfixed-link {\n\t\tspeed = <1000>;\n\t\tfull-duplex;\n\t};\n};\n\n&gsbi4_serial {\n\tpinctrl-0 = <&uart0_pins>;\n\tpinctrl-names = \"default\";\n};\n\n&gsbi5 {\n\tstatus = \"okay\";\n\tqcom,mode = <GSBI_PROT_SPI>;\n\n\tspi@1a280000 {\n\t\tstatus = \"okay\";\n\n\t\tpinctrl-0 = <&spi_pins>;\n\t\tpinctrl-names = \"default\";\n\n\t\tcs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>;\n\n\t\tflash@0 {\n\t\t\tcompatible = \"jedec,spi-nor\";\n\t\t\tspi-max-frequency = <50000000>;\n\t\t\treg = <0>;\n\n\t\t\tpartitions {\n\t\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\n\t\t\t\tSBL1@0 {\n\t\t\t\t\tlabel = \"SBL1\";\n\t\t\t\t\treg = <0x0 0x10000>;\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\tMIBIB@10000 {\n\t\t\t\t\tlabel = \"MIBIB\";\n\t\t\t\t\treg = <0x10000 0x20000>;\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\tSBL2@30000 {\n\t\t\t\t\tlabel = \"SBL2\";\n\t\t\t\t\treg = <0x30000 0x30000>;\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\tSBL3@60000 {\n\t\t\t\t\tlabel = \"SBL3\";\n\t\t\t\t\treg = <0x60000 0x30000>;\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\tDDRCONFIG@90000 {\n\t\t\t\t\tlabel = \"DDRCONFIG\";\n\t\t\t\t\treg = <0x90000 0x10000>;\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\tSSD@a0000 {\n\t\t\t\t\tlabel = \"SSD\";\n\t\t\t\t\treg = <0xa0000 0x10000>;\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\tTZ@b0000 {\n\t\t\t\t\tlabel = \"TZ\";\n\t\t\t\t\treg = <0xb0000 0x30000>;\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\tRPM@e0000 {\n\t\t\t\t\tlabel = \"RPM\";\n\t\t\t\t\treg = <0xe0000 0x20000>;\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\tAPPSBL@100000 {\n\t\t\t\t\tlabel = \"APPSBL\";\n\t\t\t\t\treg = <0x100000 0x70000>;\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\tAPPSBLENV@170000 {\n\t\t\t\t\tlabel = \"APPSBLENV\";\n\t\t\t\t\treg = <0x170000 0x10000>;\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\tART@180000 {\n\t\t\t\t\tlabel = \"ART\";\n\t\t\t\t\treg = <0x180000 0x40000>;\n\t\t\t\t\tread-only;\n\n\t\t\t\t\tcompatible = \"nvmem-cells\";\n\t\t\t\t\t#address-cells = <1>;\n\t\t\t\t\t#size-cells = <1>;\n\n\t\t\t\t\tmacaddr_ART_0: macaddr@0 {\n\t\t\t\t\t\treg = <0x0 0x6>;\n\t\t\t\t\t};\n\n\t\t\t\t\tmacaddr_ART_6: macaddr@6 {\n\t\t\t\t\t\treg = <0x6 0x6>;\n\t\t\t\t\t};\n\n\t\t\t\t\tmacaddr_ART_18: macaddr@18 {\n\t\t\t\t\t\treg = <0x18 0x6>;\n\t\t\t\t\t};\n\n\t\t\t\t\tmacaddr_ART_1e: macaddr@1e {\n\t\t\t\t\t\treg = <0x1e 0x6>;\n\t\t\t\t\t};\n\n\t\t\t\t\tprecal_ART_1000: precal@1000 {\n\t\t\t\t\t\treg = <0x1000 0x2f20>;\n\t\t\t\t\t};\n\n\t\t\t\t\tprecal_ART_5000: precal@5000 {\n\t\t\t\t\t\treg = <0x5000 0x2f20>;\n\t\t\t\t\t};\n\t\t\t\t};\n\n\t\t\t\tBOOTCONFIG@1c0000 {\n\t\t\t\t\tlabel = \"BOOTCONFIG\";\n\t\t\t\t\treg = <0x1c0000 0x10000>;\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\tAPPSBL_1@1d0000 {\n\t\t\t\t\tlabel = \"APPSBL_1\";\n\t\t\t\t\treg = <0x1d0000 0x70000>;\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t};\n};\n\n&usb3_0 {\n\tstatus = \"okay\";\n\n\tpinctrl-0 = <&usb_pwr_en_pins>;\n\tpinctrl-names = \"default\";\n};\n\n&usb3_1 {\n\tstatus = \"okay\";\n};\n\n&dwc3_0 {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\n\thub_port0: port@1 {\n\t\treg = <1>;\n\t\t#trigger-source-cells = <0>;\n\t};\n};\n\n&dwc3_1 {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\n\thub_port1: port@1 {\n\t\treg = <1>;\n\t\t#trigger-source-cells = <0>;\n\t};\n};\n\n&pcie0 {\n\tstatus = \"okay\";\n\n\tbridge@0,0 {\n\t\treg = <0x00000000 0 0 0 0>;\n\t\t#address-cells = <3>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\twifi@1,0 {\n\t\t\tcompatible = \"pci168c,0040\";\n\t\t\treg = <0x00010000 0 0 0 0>;\n\n\t\t\tnvmem-cells = <&macaddr_ART_1e>, <&precal_ART_1000>;\n\t\t\tnvmem-cell-names = \"mac-address\", \"pre-calibration\";\n\t\t};\n\t};\n};\n\n&pcie1 {\n\tstatus = \"okay\";\n\tmax-link-speed = <1>;\n\n\tbridge@0,0 {\n\t\treg = <0x00000000 0 0 0 0>;\n\t\t#address-cells = <3>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\twifi@1,0 {\n\t\t\tcompatible = \"pci168c,0040\";\n\t\t\treg = <0x00010000 0 0 0 0>;\n\n\t\t\tnvmem-cells = <&macaddr_ART_18>, <&precal_ART_5000>;\n\t\t\tnvmem-cell-names = \"mac-address\", \"pre-calibration\";\n\t\t};\n\t};\n};\n\n&qcom_pinmux {\n\tbutton_pins: button_pins {\n\t\tmux {\n\t\t\tpins = \"gpio6\", \"gpio54\", \"gpio55\", \"gpio56\", \"gpio57\",\n\t\t\t\t\"gpio58\", \"gpio64\", \"gpio65\";\n\t\t\tfunction = \"gpio\";\n\t\t\tdrive-strength = <2>;\n\t\t\tbias-pull-up;\n\t\t};\n\t};\n\n\tled_pins: led_pins {\n\t\tmux {\n\t\t\tpins = \"gpio7\", \"gpio8\", \"gpio9\", \"gpio16\", \"gpio22\",\n\t\t\t\t\"gpio23\", \"gpio24\", \"gpio25\", \"gpio26\", \"gpio53\";\n\t\t\tfunction = \"gpio\";\n\t\t\tdrive-strength = <2>;\n\t\t\tbias-pull-up;\n\t\t};\n\t};\n\n\tuart0_pins: uart0_pins {\n\t\tmux {\n\t\t\tpins = \"gpio10\", \"gpio11\";\n\t\t\tfunction = \"gsbi4\";\n\t\t\tdrive-strength = <12>;\n\t\t\tbias-disable;\n\t\t};\n\t};\n\n\tspi_pins: spi_pins {\n\t\tmux {\n\t\t\tpins = \"gpio18\", \"gpio19\", \"gpio21\";\n\t\t\tfunction = \"gsbi5\";\n\t\t\tbias-pull-down;\n\t\t};\n\n\t\tdata {\n\t\t\tpins = \"gpio18\", \"gpio19\";\n\t\t\tdrive-strength = <10>;\n\t\t};\n\n\t\tcs{\n\t\t\tpins = \"gpio20\";\n\t\t\tdrive-strength = <10>;\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tclk {\n\t\t\tpins = \"gpio21\";\n\t\t\tdrive-strength = <12>;\n\t\t};\n\t};\n\n\tusb_pwr_en_pins: usb_pwr_en_pins {\n\t\tmux{\n\t\t\tpins = \"gpio68\";\n\t\t\tfunction = \"gpio\";\n\t\t\tdrive-strength = <2>;\n\t\t\tbias-pull-up;\n\t\t\toutput-high;\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-nbg6817.dts",
    "content": "#include \"qcom-ipq8065.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"ZyXEL NBG6817\";\n\tcompatible = \"zyxel,nbg6817\", \"qcom,ipq8065\", \"qcom,ipq8064\";\n\n\tmemory@0 {\n\t\treg = <0x42000000 0x1e000000>;\n\t\tdevice_type = \"memory\";\n\t};\n\n\taliases {\n\t\tmdio-gpio0 = &mdio0;\n\t\tsdcc1 = &sdcc1;\n\n\t\tled-boot = &power;\n\t\tled-failsafe = &power;\n\t\tled-running = &power;\n\t\tled-upgrade = &power;\n\t};\n\n\tchosen {\n\t\tbootargs = \"rootfstype=squashfs,ext4 rootwait noinitrd fstools_ignore_partname=1\";\n\t\tappend-rootblock = \"root=/dev/mmcblk0p\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\t\tpinctrl-0 = <&button_pins>;\n\t\tpinctrl-names = \"default\";\n\n\t\twifi {\n\t\t\tlabel = \"wifi\";\n\t\t\tgpios = <&qcom_pinmux 53 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RFKILL>;\n\t\t\tlinux,input-type = <EV_SW>;\n\t\t\tdebounce-interval = <60>;\n\t\t\twakeup-source;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tdebounce-interval = <60>;\n\t\t\twakeup-source;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tdebounce-interval = <60>;\n\t\t\twakeup-source;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tpinctrl-0 = <&led_pins>;\n\t\tpinctrl-names = \"default\";\n\n\t\tinternet {\n\t\t\tlabel = \"white:internet\";\n\t\t\tgpios = <&qcom_pinmux 64 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tpower: power {\n\t\t\tlabel = \"white:power\";\n\t\t\tgpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"keep\";\n\t\t};\n\n\t\twifi2g {\n\t\t\tlabel = \"amber:wifi2g\";\n\t\t\tgpios = <&qcom_pinmux 33 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\t/* wifi2g amber from the manual is missing */\n\n\t\twifi5g {\n\t\t\tlabel = \"amber:wifi5g\";\n\t\t\tgpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\t/* wifi5g amber from the manual is missing */\n\t};\n};\n\n&qcom_pinmux {\n\tbutton_pins: button_pins {\n\t\tmux {\n\t\t\tpins = \"gpio53\", \"gpio54\", \"gpio65\";\n\t\t\tfunction = \"gpio\";\n\t\t\tdrive-strength = <2>;\n\t\t\tbias-pull-up;\n\t\t};\n\t};\n\n\tled_pins: led_pins {\n\t\tmux {\n\t\t\tpins = \"gpio9\", \"gpio26\", \"gpio33\", \"gpio64\";\n\t\t\tfunction = \"gpio\";\n\t\t\tdrive-strength = <2>;\n\t\t\tbias-pull-down;\n\t\t};\n\t};\n\n\tmdio0_pins: mdio0_pins {\n\t\tclk {\n\t\t\tpins = \"gpio1\";\n\t\t\tinput-disable;\n\t\t};\n\t};\n\n\trgmii2_pins: rgmii2_pins {\n\t\ttx {\n\t\t\tpins = \"gpio27\", \"gpio28\", \"gpio29\", \"gpio30\", \"gpio31\", \"gpio32\" ;\n\t\t\tinput-disable;\n\t\t};\n\t};\n\n\tspi_pins: spi_pins {\n\t\tcs {\n\t\t\tpins = \"gpio20\";\n\t\t\tdrive-strength = <12>;\n\t\t};\n\t};\n\n\tusb0_pwr_en_pins: usb0_pwr_en_pins {\n\t\tmux {\n\t\t\tpins = \"gpio16\", \"gpio17\";\n\t\t\tfunction = \"gpio\";\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tpwr {\n\t\t\tpins = \"gpio17\";\n\t\t\tbias-pull-down;\n\t\t\toutput-high;\n\t\t};\n\n\t\tovc {\n\t\t\tpins = \"gpio16\";\n\t\t\tbias-pull-up;\n\t\t};\n\t};\n\n\tusb1_pwr_en_pins: usb1_pwr_en_pins {\n\t\tmux {\n\t\t\tpins = \"gpio14\", \"gpio15\";\n\t\t\tfunction = \"gpio\";\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tpwr {\n\t\t\tpins = \"gpio14\";\n\t\t\tbias-pull-down;\n\t\t\toutput-high;\n\t\t};\n\n\t\tovc {\n\t\t\tpins = \"gpio15\";\n\t\t\tbias-pull-up;\n\t\t};\n\t};\n};\n\n&gsbi5 {\n\tqcom,mode = <GSBI_PROT_SPI>;\n\tstatus = \"okay\";\n\n\tspi4: spi@1a280000 {\n\t\tstatus = \"okay\";\n\n\t\tpinctrl-0 = <&spi_pins>;\n\t\tpinctrl-names = \"default\";\n\n\t\tcs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>;\n\n\t\tm25p80@0 {\n\t\t\tcompatible = \"jedec,spi-nor\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\t\t\tspi-max-frequency = <51200000>;\n\t\t\treg = <0>;\n\n\t\t\tpartitions {\n\t\t\t\tcompatible = \"qcom,smem-part\";\n\t\t\t};\n\t\t};\n\t};\n};\n\n&usb3_0 {\n\tstatus = \"okay\";\n\n\tpinctrl-0 = <&usb0_pwr_en_pins>;\n\tpinctrl-names = \"default\";\n};\n\n&usb3_1 {\n\tstatus = \"okay\";\n\n\tpinctrl-0 = <&usb1_pwr_en_pins>;\n\tpinctrl-names = \"default\";\n};\n\n&pcie0 {\n\tstatus = \"okay\";\n\treset-gpio = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>;\n\tpinctrl-0 = <&pcie0_pins>;\n\tpinctrl-names = \"default\";\n};\n\n&pcie1 {\n\tstatus = \"okay\";\n\treset-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;\n\tpinctrl-0 = <&pcie1_pins>;\n\tpinctrl-names = \"default\";\n\tmax-link-speed = <1>;\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tpinctrl-0 = <&mdio0_pins>;\n\tpinctrl-names = \"default\";\n\n\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t\tqca,ar8327-initvals = <\n\t\t\t0x00004 0x7600000   /* PAD0_MODE */\n\t\t\t0x00008 0x1000000   /* PAD5_MODE */\n\t\t\t0x0000c 0x80        /* PAD6_MODE */\n\t\t\t0x000e4 0xaa545     /* MAC_POWER_SEL */\n\t\t\t0x000e0 0xc74164de  /* SGMII_CTRL */\n\t\t\t0x0007c 0x4e        /* PORT0_STATUS */\n\t\t\t0x00094 0x4e        /* PORT6_STATUS */\n\t\t\t0x00970 0x1e864443  /* QM_PORT0_CTRL0 */\n\t\t\t0x00974 0x000001c6  /* QM_PORT0_CTRL1 */\n\t\t\t0x00978 0x19008643  /* QM_PORT1_CTRL0 */\n\t\t\t0x0097c 0x000001c6  /* QM_PORT1_CTRL1 */\n\t\t\t0x00980 0x19008643  /* QM_PORT2_CTRL0 */\n\t\t\t0x00984 0x000001c6  /* QM_PORT2_CTRL1 */\n\t\t\t0x00988 0x19008643  /* QM_PORT3_CTRL0 */\n\t\t\t0x0098c 0x000001c6  /* QM_PORT3_CTRL1 */\n\t\t\t0x00990 0x19008643  /* QM_PORT4_CTRL0 */\n\t\t\t0x00994 0x000001c6  /* QM_PORT4_CTRL1 */\n\t\t\t0x00998 0x1e864443  /* QM_PORT5_CTRL0 */\n\t\t\t0x0099c 0x000001c6  /* QM_PORT5_CTRL1 */\n\t\t\t0x009a0 0x1e864443  /* QM_PORT6_CTRL0 */\n\t\t\t0x009a4 0x000001c6  /* QM_PORT6_CTRL1 */\n\t\t\t>;\n\t};\n\n\tphy4: ethernet-phy@4 {\n\t\treg = <4>;\n\t\tqca,ar8327-initvals = <\n\t\t\t0x000e4 0x6a545     /* MAC_POWER_SEL */\n\t\t\t0x0000c 0x80        /* PAD6_MODE */\n\t\t\t>;\n\t};\n};\n\n&gmac1 {\n\tstatus = \"okay\";\n\tphy-mode = \"rgmii\";\n\tqcom,id = <1>;\n\tqcom,phy_mdio_addr = <4>;\n\tqcom,poll_required = <0>;\n\tqcom,rgmii_delay = <1>;\n\tqcom,phy_mii_type = <0>;\n\tqcom,emulation = <0>;\n\tqcom,irq = <255>;\n\tmdiobus = <&mdio0>;\n\n\tpinctrl-0 = <&rgmii2_pins>;\n\tpinctrl-names = \"default\";\n\n\tfixed-link {\n\t\tspeed = <1000>;\n\t\tfull-duplex;\n\t};\n};\n\n&gmac2 {\n\tstatus = \"okay\";\n\tphy-mode = \"sgmii\";\n\tqcom,id = <2>;\n\tqcom,phy_mdio_addr = <0>;\t/* none */\n\tqcom,poll_required = <0>;\t/* no polling */\n\tqcom,rgmii_delay = <0>;\n\tqcom,phy_mii_type = <1>;\n\tqcom,emulation = <0>;\n\tqcom,irq = <258>;\n\tmdiobus = <&mdio0>;\n\n\tfixed-link {\n\t\tspeed = <1000>;\n\t\tfull-duplex;\n\t};\n};\n\n&amba {\n\tsdcc1: sdcc@12400000 {\n\t\tstatus = \"okay\";\n\t};\n};\n\n&adm_dma {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-nighthawk.dtsi",
    "content": "#include \"qcom-ipq8065.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmemory@0 {\n\t\treg = <0x42000000 0x1e000000>;\n\t\tdevice_type = \"memory\";\n\t};\n\n\treserved-memory {\n\t\trsvd@5fe00000 {\n\t\t\treg = <0x5fe00000 0x200000>;\n\t\t\treusable;\n\t\t};\n\n\t\tramoops@42100000 {\n\t\t\tcompatible = \"ramoops\";\n\t\t\treg = <0x42100000 0x40000>;\n\t\t\trecord-size = <0x4000>;\n\t\t\tconsole-size = <0x4000>;\n\t\t\tftrace-size = <0x4000>;\n\t\t\tpmsg-size = <0x4000>;\n\t\t};\n\t};\n\n\taliases {\n\t\tlabel-mac-device = &gmac2;\n\n\t\tled-boot = &power_white;\n\t\tled-failsafe = &power_amber;\n\t\tled-running = &power_white;\n\t\tled-upgrade = &power_amber;\n\n\t\tmdio-gpio0 = &mdio0;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\t\tpinctrl-0 = <&button_pins>;\n\t\tpinctrl-names = \"default\";\n\n\t\twifi {\n\t\t\tlabel = \"wifi\";\n\t\t\tgpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RFKILL>;\n\t\t\tdebounce-interval = <60>;\n\t\t\twakeup-source;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tdebounce-interval = <60>;\n\t\t\twakeup-source;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tdebounce-interval = <60>;\n\t\t\twakeup-source;\n\t\t};\n\t};\n\n\tleds: leds {\n\t\tcompatible = \"gpio-leds\";\n\t\tpinctrl-0 = <&led_pins>;\n\t\tpinctrl-names = \"default\";\n\n\t\tpower_white: power_white {\n\t\t\tlabel = \"white:power\";\n\t\t\tgpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"keep\";\n\t\t};\n\n\t\tpower_amber: power_amber {\n\t\t\tlabel = \"amber:power\";\n\t\t\tgpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\twan_white {\n\t\t\tlabel = \"white:wan\";\n\t\t\tgpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\twan_amber {\n\t\t\tlabel = \"amber:wan\";\n\t\t\tgpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\twifi {\n\t\t\tlabel = \"white:wifi\";\n\t\t\tgpios = <&qcom_pinmux 64 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"white:wps\";\n\t\t\tgpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&qcom_pinmux {\n\tbutton_pins: button_pins {\n\t\tmux {\n\t\t\tpins = \"gpio6\", \"gpio54\", \"gpio65\";\n\t\t\tfunction = \"gpio\";\n\t\t\tdrive-strength = <2>;\n\t\t\tbias-pull-up;\n\t\t};\n\t};\n\n\tled_pins: led_pins {\n\t\tmux {\n\t\t\tpins = \"gpio7\", \"gpio8\", \"gpio9\",\n\t\t\t\t\"gpio22\", \"gpio23\", \"gpio24\",\n\t\t\t\t\"gpio26\", \"gpio53\", \"gpio64\";\n\t\t\tfunction = \"gpio\";\n\t\t\tdrive-strength = <2>;\n\t\t\tbias-pull-down;\n\t\t};\n\t};\n\n\tmdio0_pins: mdio0_pins {\n\t\tclk {\n\t\t\tpins = \"gpio1\";\n\t\t\tinput-disable;\n\t\t};\n\t};\n\n\trgmii2_pins: rgmii2_pins {\n\t\ttx {\n\t\t\tpins = \"gpio27\", \"gpio28\", \"gpio29\",\n\t\t\t\t\"gpio30\", \"gpio31\", \"gpio32\";\n\t\t\tinput-disable;\n\t\t};\n\t};\n\n\tspi_pins: spi_pins {\n\t\tmux {\n\t\t\tpins = \"gpio18\", \"gpio19\", \"gpio21\";\n\t\t\tfunction = \"gsbi5\";\n\t\t\tbias-pull-down;\n\t\t};\n\n\t\tdata {\n\t\t\tpins = \"gpio18\", \"gpio19\";\n\t\t\tdrive-strength = <10>;\n\t\t};\n\n\t\tcs {\n\t\t\tpins = \"gpio20\";\n\t\t\tdrive-strength = <10>;\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tclk {\n\t\t\tpins = \"gpio21\";\n\t\t\tdrive-strength = <12>;\n\t\t};\n\t};\n\n\tspi6_pins: spi6_pins {\n\t\tmux {\n\t\t\tpins = \"gpio55\", \"gpio56\", \"gpio58\";\n\t\t\tfunction = \"gsbi6\";\n\t\t\tbias-pull-down;\n\t\t};\n\n\t\tmosi {\n\t\t\tpins = \"gpio55\";\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\tmiso {\n\t\t\tpins = \"gpio56\";\n\t\t\tdrive-strength = <14>;\n\t\t};\n\n\t\tcs {\n\t\t\tpins = \"gpio57\";\n\t\t\tdrive-strength = <12>;\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tclk {\n\t\t\tpins = \"gpio58\";\n\t\t\tdrive-strength = <12>;\n\t\t};\n\n\t\treset {\n\t\t\tpins = \"gpio33\";\n\t\t\tdrive-strength = <10>;\n\t\t\tbias-pull-down;\n\t\t\toutput-high;\n\t\t};\n\t};\n\n\tusb0_pwr_en_pins: usb0_pwr_en_pins {\n\t\tmux {\n\t\t\tpins = \"gpio15\";\n\t\t\tfunction = \"gpio\";\n\t\t\tdrive-strength = <12>;\n\t\t\tbias-pull-down;\n\t\t\toutput-high;\n\t\t};\n\t};\n\n\tusb1_pwr_en_pins: usb1_pwr_en_pins {\n\t\tmux {\n\t\t\tpins = \"gpio16\", \"gpio68\";\n\t\t\tfunction = \"gpio\";\n\t\t\tdrive-strength = <12>;\n\t\t\tbias-pull-down;\n\t\t\toutput-high;\n\t\t};\n\t};\n};\n\n&nand {\n\tstatus = \"okay\";\n\n\tpinctrl-0 = <&nand_pins>;\n\tpinctrl-names = \"default\";\n\n\tnand@0 {\n\t\treg = <0>;\n\t\tcompatible = \"qcom,nandcs\";\n\n\t\tnand-ecc-strength = <4>;\n\t\tnand-bus-width = <8>;\n\t\tnand-ecc-step-size = <512>;\n\n\t\tnand-is-boot-medium;\n\t\tqcom,boot_pages_size = <0x1180000>;\n\n\t\tpartitions: partitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"qcadata\";\n\t\t\t\treg = <0x0000000 0x0c80000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@c80000 {\n\t\t\t\tlabel = \"APPSBL\";\n\t\t\t\treg = <0x0c80000 0x0500000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@1180000 {\n\t\t\t\tlabel = \"APPSBLENV\";\n\t\t\t\treg = <0x1180000 0x0080000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tart: partition@1200000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0x1200000 0x0140000>;\n\t\t\t\tread-only;\n\t\t\t\tcompatible = \"nvmem-cells\";\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\n\t\t\t\tmacaddr_art_0: macaddr@0 {\n\t\t\t\t\treg = <0x0 0x6>;\n\t\t\t\t};\n\n\t\t\t\tmacaddr_art_6: macaddr@6 {\n\t\t\t\t\treg = <0x6 0x6>;\n\t\t\t\t};\n\n\t\t\t\tprecal_art_1000: precal@1000 {\n\t\t\t\t\treg = <0x1000 0x2f20>;\n\t\t\t\t};\n\n\t\t\t\tprecal_art_5000: precal@5000 {\n\t\t\t\t\treg = <0x5000 0x2f20>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tpartition@1340000 {\n\t\t\t\tlabel = \"artbak\";\n\t\t\t\treg = <0x1340000 0x0140000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@1480000 {\n\t\t\t\tlabel = \"kernel\";\n\t\t\t\treg = <0x1480000 0x0400000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tpinctrl-0 = <&mdio0_pins>;\n\tpinctrl-names = \"default\";\n\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t\tqca,ar8327-initvals = <\n\t\t\t0x00004 0x7600000   /* PAD0_MODE */\n\t\t\t0x00008 0x1000000   /* PAD5_MODE */\n\t\t\t0x0000c 0x80        /* PAD6_MODE */\n\t\t\t0x000e4 0xaa545     /* MAC_POWER_SEL */\n\t\t\t0x000e0 0xc74164de  /* SGMII_CTRL */\n\t\t\t0x0007c 0x4e        /* PORT0_STATUS */\n\t\t\t0x00094 0x4e        /* PORT6_STATUS */\n\t\t\t0x00970 0x1e864443  /* QM_PORT0_CTRL0 */\n\t\t\t0x00974 0x000001c6  /* QM_PORT0_CTRL1 */\n\t\t\t0x00978 0x19008643  /* QM_PORT1_CTRL0 */\n\t\t\t0x0097c 0x000001c6  /* QM_PORT1_CTRL1 */\n\t\t\t0x00980 0x19008643  /* QM_PORT2_CTRL0 */\n\t\t\t0x00984 0x000001c6  /* QM_PORT2_CTRL1 */\n\t\t\t0x00988 0x19008643  /* QM_PORT3_CTRL0 */\n\t\t\t0x0098c 0x000001c6  /* QM_PORT3_CTRL1 */\n\t\t\t0x00990 0x19008643  /* QM_PORT4_CTRL0 */\n\t\t\t0x00994 0x000001c6  /* QM_PORT4_CTRL1 */\n\t\t\t0x00998 0x1e864443  /* QM_PORT5_CTRL0 */\n\t\t\t0x0099c 0x000001c6  /* QM_PORT5_CTRL1 */\n\t\t\t0x009a0 0x1e864443  /* QM_PORT6_CTRL0 */\n\t\t\t0x009a4 0x000001c6  /* QM_PORT6_CTRL1 */\n\t\t\t>;\n\t\tqca,ar8327-vlans = <\n\t\t\t0x1\t0x5e\t    /* VLAN1 Ports 1/2/3/4/6 */\n\t\t\t0x2\t0x21\t    /* VLAN2 Ports 0/5 */\n\t\t>;\n\t};\n\n\tphy4: ethernet-phy@4 {\n\t\treg = <4>;\n\t\tqca,ar8327-initvals = <\n\t\t\t0x000e4 0x6a545     /* MAC_POWER_SEL */\n\t\t\t0x0000c 0x80        /* PAD6_MODE */\n\t\t\t>;\n\t};\n};\n\n&gmac1 {\n\tstatus = \"okay\";\n\n\tphy-mode = \"rgmii\";\n\tqcom,id = <1>;\n\tqcom,phy_mdio_addr = <4>;\n\tqcom,poll_required = <0>;\n\tqcom,rgmii_delay = <1>;\n\tqcom,phy_mii_type = <0>;\n\tqcom,emulation = <0>;\n\tqcom,irq = <255>;\n\tmdiobus = <&mdio0>;\n\n\tpinctrl-0 = <&rgmii2_pins>;\n\tpinctrl-names = \"default\";\n\n\tnvmem-cells = <&macaddr_art_6>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tfixed-link {\n\t\tspeed = <1000>;\n\t\tfull-duplex;\n\t};\n};\n\n&gmac2 {\n\tstatus = \"okay\";\n\n\tphy-mode = \"sgmii\";\n\tqcom,id = <2>;\n\tqcom,phy_mdio_addr = <0>;\t/* none */\n\tqcom,poll_required = <0>;\t/* no polling */\n\tqcom,rgmii_delay = <0>;\n\tqcom,phy_mii_type = <1>;\n\tqcom,emulation = <0>;\n\tqcom,irq = <258>;\n\tmdiobus = <&mdio0>;\n\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tfixed-link {\n\t\tspeed = <1000>;\n\t\tfull-duplex;\n\t};\n};\n\n&adm_dma {\n\tstatus = \"okay\";\n};\n\n&sata_phy {\n\tstatus = \"okay\";\n};\n\n&sata {\n\tstatus = \"okay\";\n};\n\n&usb3_0 {\n\tstatus = \"okay\";\n\n\tpinctrl-0 = <&usb0_pwr_en_pins>;\n\tpinctrl-names = \"default\";\n};\n\n&usb3_1 {\n\tstatus = \"okay\";\n\n\tpinctrl-0 = <&usb1_pwr_en_pins>;\n\tpinctrl-names = \"default\";\n};\n\n&pcie0 {\n\tstatus = \"okay\";\n\n\tbridge@0,0 {\n\t\treg = <0x00000000 0 0 0 0>;\n\t\t#address-cells = <3>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\twifi0: wifi@1,0 {\n\t\t\tcompatible = \"pci168c,0046\";\n\t\t\treg = <0x00010000 0 0 0 0>;\n\t\t};\n\t};\n};\n\n&pcie1 {\n\tstatus = \"okay\";\n\n\tmax-link-speed = <1>;\n\n\tbridge@0,0 {\n\t\treg = <0x00000000 0 0 0 0>;\n\t\t#address-cells = <3>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\twifi1: wifi@1,0 {\n\t\t\tcompatible = \"pci168c,0046\";\n\t\t\treg = <0x00010000 0 0 0 0>;\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-r7800.dts",
    "content": "#include \"qcom-ipq8065-nighthawk.dtsi\"\n\n/ {\n\tmodel = \"Netgear Nighthawk X4S R7800\";\n\tcompatible = \"netgear,r7800\", \"qcom,ipq8065\", \"qcom,ipq8064\";\n};\n\n&leds {\n\tusb1 {\n\t\tlabel = \"white:usb1\";\n\t\tgpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>;\n\t};\n\n\tusb2 {\n\t\tlabel = \"white:usb2\";\n\t\tgpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;\n\t};\n\n\tesata {\n\t\tlabel = \"white:esata\";\n\t\tgpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>;\n\t};\n};\n\n&partitions {\n\tpartition@1880000 {\n\t\tlabel = \"ubi\";\n\t\treg = <0x1880000 0x6080000>;\n\t};\n\n\tpartition@7900000 {\n\t\tlabel = \"reserve\";\n\t\treg = <0x7900000 0x0700000>;\n\t\tread-only;\n\t};\n};\n\n&wifi0 {\n\tnvmem-cells = <&macaddr_art_6>, <&precal_art_1000>;\n\tnvmem-cell-names = \"mac-address\", \"pre-calibration\";\n\tmac-address-increment = <(1)>;\n};\n\n&wifi1 {\n\tnvmem-cells = <&macaddr_art_6>, <&precal_art_5000>;\n\tnvmem-cell-names = \"mac-address\", \"pre-calibration\";\n\tmac-address-increment = <(2)>;\n};\n"
  },
  {
    "path": "target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-rt4230w-rev6.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later\n\n#include \"qcom-ipq8065.dtsi\"\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"Askey RT4230W REV6\";\n\tcompatible = \"askey,rt4230w-rev6\", \"qcom,ipq8065\", \"qcom,ipq8064\";\n\n\tmemory@0 {\n\t\treg = <0x42000000 0x3e000000>;\n\t\tdevice_type = \"memory\";\n\t};\n\n\taliases {\n\t\tled-boot = &ledctrl3;\n\t\tled-failsafe = &ledctrl1;\n\t\tled-running = &ledctrl2;\n\t\tled-upgrade = &ledctrl3;\n\t};\n\n\tchosen {\n\t\tbootargs = \"rootfstype=squashfs noinitrd\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\t\tpinctrl-0 = <&button_pins>;\n\t\tpinctrl-names = \"default\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&qcom_pinmux 68 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tpinctrl-0 = <&led_pins>;\n\t\tpinctrl-names = \"default\";\n\n\t\tledctrl1: ledctrl1 {\n\t\t\tlabel = \"ledctrl1\";\n\t\t\tgpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tledctrl2: ledctrl2 {\n\t\t\tlabel = \"ledctrl2\";\n\t\t\tgpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tledctrl3: ledctrl3 {\n\t\t\tlabel = \"ledctrl3\";\n\t\t\tgpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&qcom_pinmux {\n\tbutton_pins: button_pins {\n\t\tmux {\n\t\t\tpins = \"gpio54\", \"gpio68\";\n\t\t\tfunction = \"gpio\";\n\t\t\tdrive-strength = <2>;\n\t\t\tbias-pull-up;\n\t\t};\n\t};\n\n\tled_pins: led_pins {\n\t\tmux {\n\t\t\tpins = \"gpio22\", \"gpio23\", \"gpio24\";\n\t\t\tfunction = \"gpio\";\n\t\t\tdrive-strength = <2>;\n\t\t\tbias-pull-down;\n\t\t};\n\t};\n\n\trgmii2_pins: rgmii2_pins {\n\t\tmux {\n\t\t\tpins = \"gpio27\", \"gpio28\", \"gpio29\", \"gpio30\", \"gpio31\",\n\t\t\t\t\"gpio51\", \"gpio52\", \"gpio59\", \"gpio60\", \"gpio61\", \"gpio62\";\n\t\t\tfunction = \"rgmii2\";\n\t\t\tdrive-strength = <8>;\n\t\t\tbias-disable;\n\t\t};\n\n\t\ttx {\n\t\t\tpins = \"gpio27\", \"gpio28\", \"gpio29\", \"gpio30\", \"gpio31\", \"gpio32\";\n\t\t\tinput-disable;\n\t\t};\n\t};\n\n\tspi_pins: spi_pins {\n\t\tcs {\n\t\t\tpins = \"gpio20\";\n\t\t\tdrive-strength = <12>;\n\t\t};\n\t};\n};\n\n&gsbi5 {\n\tqcom,mode = <GSBI_PROT_SPI>;\n\tstatus = \"okay\";\n\n\tspi@1a280000 {\n\t\tstatus = \"okay\";\n\n\t\tpinctrl-0 = <&spi_pins>;\n\t\tpinctrl-names = \"default\";\n\n\t\tcs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>;\n\n\t\tflash@0 {\n\t\t\tcompatible = \"everspin,mr25h256\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\t\t\tspi-max-frequency = <40000000>;\n\t\t\treg = <0>;\n\t\t};\n\t};\n};\n\n&nand {\n\tstatus = \"okay\";\n\n\tpinctrl-0 = <&nand_pins>;\n\tpinctrl-names = \"default\";\n\n\tnand@0 {\n\t\treg = <0>;\n\t\tcompatible = \"qcom,nandcs\";\n\n\t\tnand-ecc-strength = <4>;\n\t\tnand-bus-width = <8>;\n\t\tnand-ecc-step-size = <512>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"0:SBL1\";\n\t\t\t\treg = <0x0000000 0x0040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"0:MIBIB\";\n\t\t\t\treg = <0x0040000 0x0140000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@180000 {\n\t\t\t\tlabel = \"0:SBL2\";\n\t\t\t\treg = <0x0180000 0x0140000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@2c0000 {\n\t\t\t\tlabel = \"0:SBL3\";\n\t\t\t\treg = <0x02c0000 0x0280000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@540000 {\n\t\t\t\tlabel = \"0:DDRCONFIG\";\n\t\t\t\treg = <0x0540000 0x0120000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@660000 {\n\t\t\t\tlabel = \"0:SSD\";\n\t\t\t\treg = <0x0660000 0x0120000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@780000 {\n\t\t\t\tlabel = \"0:TZ\";\n\t\t\t\treg = <0x0780000 0x0280000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@a00000 {\n\t\t\t\tlabel = \"0:RPM\";\n\t\t\t\treg = <0x0a00000 0x0280000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@c80000 {\n\t\t\t\tlabel = \"0:APPSBL\";\n\t\t\t\treg = <0x0c80000 0x0500000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@1180000 {\n\t\t\t\tlabel = \"0:APPSBLENV\";\n\t\t\t\treg = <0x1180000 0x0080000>;\n\t\t\t};\n\n\t\t\tpartition@1200000 {\n\t\t\t\tlabel = \"0:ART\";\n\t\t\t\treg = <0x1200000 0x0140000>;\n\t\t\t\tread-only;\n\t\t\t\tcompatible = \"nvmem-cells\";\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\n\t\t\t\tmacaddr_ART_0: macaddr@0 {\n\t\t\t\t\treg = <0x0 0x6>;\n\t\t\t\t};\n\n\t\t\t\tmacaddr_ART_6: macaddr@6 {\n\t\t\t\t\treg = <0x6 0x6>;\n\t\t\t\t};\n\n\t\t\t\tprecal_ART_1000: precal@1000 {\n\t\t\t\t\treg = <0x1000 0x2f20>;\n\t\t\t\t};\n\n\t\t\t\tprecal_ART_5000: precal@5000 {\n\t\t\t\t\treg = <0x5000 0x2f20>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tpartition@1340000 {\n\t\t\t\tlabel = \"0:BOOTCONFIG\";\n\t\t\t\treg = <0x1340000 0x0060000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@13a0000 {\n\t\t\t\tlabel = \"0:SBL2_1\";\n\t\t\t\treg = <0x13a0000 0x0140000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@14e0000 {\n\t\t\t\tlabel = \"0:SBL3_1\";\n\t\t\t\treg = <0x14e0000 0x0280000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@1760000 {\n\t\t\t\tlabel = \"0:DDRCONFIG_1\";\n\t\t\t\treg = <0x1760000 0x0120000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@1880000 {\n\t\t\t\tlabel = \"0:SSD_1\";\n\t\t\t\treg = <0x1880000 0x0120000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@19a0000 {\n\t\t\t\tlabel = \"0:TZ_1\";\n\t\t\t\treg = <0x19a0000 0x0280000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@1c20000 {\n\t\t\t\tlabel = \"0:RPM_1\";\n\t\t\t\treg = <0x1c20000 0x0280000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@1ea0000 {\n\t\t\t\tlabel = \"0:BOOTCONFIG1\";\n\t\t\t\treg = <0x1ea0000 0x0060000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@1f00000 {\n\t\t\t\tlabel = \"0:APPSBL_1\";\n\t\t\t\treg = <0x1f00000 0x0500000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@2400000 {\n\t\t\t\tlabel = \"ubi\";\n\t\t\t\treg = <0x2400000 0x1a000000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tpinctrl-0 = <&mdio0_pins>;\n\tpinctrl-names = \"default\";\n\n\tphy0: ethernet-phy@0 {\n\t\treg = <0x0>;\n\t\tqca,ar8327-initvals = <\n\t\t\t0x00004 0x7600000   /* PAD0_MODE */\n\t\t\t0x00008 0x1000000   /* PAD5_MODE */\n\t\t\t0x0000c 0x80        /* PAD6_MODE */\n\t\t\t0x000e4 0xaa545     /* MAC_POWER_SEL */\n\t\t\t0x000e0 0xc74164de  /* SGMII_CTRL */\n\t\t\t0x0007c 0x4e        /* PORT0_STATUS */\n\t\t\t0x00094 0x4e        /* PORT6_STATUS */\n\t\t\t0x00050 0xcf02cf02  /* LED_CTRL_0 */\n\t\t\t0x00054 0xc832c832  /* LED_CTRL_1 */\n\t\t\t>;\n\t};\n};\n\n&gmac0 {\n\tstatus = \"okay\";\n\tphy-mode = \"rgmii\";\n\tqcom,id = <0>;\n\n\tnvmem-cells = <&macaddr_ART_0>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tpinctrl-0 = <&rgmii2_pins>;\n\tpinctrl-names = \"default\";\n\n\tfixed-link {\n\t\tspeed = <1000>;\n\t\tfull-duplex;\n\t};\n};\n\n&gmac1 {\n\tstatus = \"okay\";\n\tphy-mode = \"sgmii\";\n\tqcom,id = <1>;\n\n\tnvmem-cells = <&macaddr_ART_6>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tfixed-link {\n\t\tspeed = <1000>;\n\t\tfull-duplex;\n\t};\n};\n\n&adm_dma {\n\tstatus = \"okay\";\n};\n\n&usb3_0 {\n\tstatus = \"okay\";\n};\n\n&usb3_1 {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\tstatus = \"okay\";\n\treset-gpio = <&qcom_pinmux 3 GPIO_ACTIVE_HIGH>;\n\tpinctrl-0 = <&pcie0_pins>;\n\tpinctrl-names = \"default\";\n\n\tbridge@0,0 {\n\t\treg = <0x00000000 0 0 0 0>;\n\t\t#address-cells = <3>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\twifi0: wifi@1,0 {\n\t\t\tcompatible = \"pci168c,0046\";\n\t\t\treg = <0x00010000 0 0 0 0>;\n\n\t\t\tnvmem-cells = <&precal_ART_1000>;\n\t\t\tnvmem-cell-names = \"pre-calibration\";\n\t\t};\n\t};\n};\n\n&pcie1 {\n\tstatus = \"okay\";\n\treset-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_HIGH>;\n\tpinctrl-0 = <&pcie1_pins>;\n\tpinctrl-names = \"default\";\n\tmax-link-speed = <1>;\n\n\tbridge@0,0 {\n\t\treg = <0x00000000 0 0 0 0>;\n\t\t#address-cells = <3>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\twifi1: wifi@1,0 {\n\t\t\tcompatible = \"pci168c,0046\";\n\t\t\treg = <0x00010000 0 0 0 0>;\n\n\t\t\tnvmem-cells = <&precal_ART_5000>;\n\t\t\tnvmem-cell-names = \"pre-calibration\";\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-tr4400-v2.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later\n\n#include \"qcom-ipq8065.dtsi\"\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"Arris TR4400 v2\";\n\tcompatible = \"arris,tr4400-v2\", \"qcom,ipq8065\", \"qcom,ipq8064\";\n\n\tmemory@0 {\n\t\treg = <0x42000000 0x1e000000>;\n\t\tdevice_type = \"memory\";\n\t};\n\n\taliases {\n\t\tled-boot = &led_status_blue;\n\t\tled-failsafe = &led_status_red;\n\t\tled-running = &led_status_blue;\n\t\tled-upgrade = &led_status_red;\n\t};\n\n\tchosen {\n\t\tbootargs = \"rootfstype=squashfs noinitrd\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\t\tpinctrl-0 = <&button_pins>;\n\t\tpinctrl-names = \"default\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tdebounce-interval = <60>;\n\t\t\twakeup-source;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tdebounce-interval = <60>;\n\t\t\twakeup-source;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tpinctrl-0 = <&led_pins>;\n\t\tpinctrl-names = \"default\";\n\n\t\tled_status_red: status_red {\n\t\t\tlabel = \"red:status\";\n\t\t\tgpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tled_status_blue: status_blue {\n\t\t\tlabel = \"blue:status\";\n\t\t\tgpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&qcom_pinmux {\n\tbutton_pins: button_pins {\n\t\tmux {\n\t\t\tpins = \"gpio6\", \"gpio54\";\n\t\t\tfunction = \"gpio\";\n\t\t\tdrive-strength = <2>;\n\t\t\tbias-pull-up;\n\t\t};\n\t};\n\n\tled_pins: led_pins {\n\t\tmux {\n\t\t\tpins = \"gpio7\", \"gpio8\";\n\t\t\tfunction = \"gpio\";\n\t\t\tdrive-strength = <2>;\n\t\t\tbias-pull-down;\n\t\t};\n\t};\n\n\trgmii2_pins: rgmii2_pins {\n\t\ttx {\n\t\t\tpins = \"gpio27\", \"gpio28\", \"gpio29\", \"gpio30\", \"gpio31\", \"gpio32\";\n\t\t\tinput-disable;\n\t\t};\n\t};\n\n\tspi_pins: spi_pins {\n\t\tcs {\n\t\t\tpins = \"gpio20\";\n\t\t\tdrive-strength = <12>;\n\t\t};\n\t};\n};\n\n&gsbi5 {\n\tqcom,mode = <GSBI_PROT_SPI>;\n\tstatus = \"okay\";\n\n\tspi@1a280000 {\n\t\tstatus = \"okay\";\n\n\t\tpinctrl-0 = <&spi_pins>;\n\t\tpinctrl-names = \"default\";\n\n\t\tcs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>;\n\n\t\tflash@0 {\n\t\t\tcompatible = \"everspin,mr25h256\";\n\t\t\tspi-max-frequency = <40000000>;\n\t\t\treg = <0>;\n\t\t};\n\t};\n};\n\n&nand {\n\tstatus = \"okay\";\n\n\tpinctrl-0 = <&nand_pins>;\n\tpinctrl-names = \"default\";\n\n\tnand@0 {\n\t\treg = <0>;\n\t\tcompatible = \"qcom,nandcs\";\n\n\t\tnand-ecc-strength = <4>;\n\t\tnand-bus-width = <8>;\n\t\tnand-ecc-step-size = <512>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"0:SBL1\";\n\t\t\t\treg = <0x0000000 0x0040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"0:MIBIB\";\n\t\t\t\treg = <0x0040000 0x0140000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@180000 {\n\t\t\t\tlabel = \"0:SBL2\";\n\t\t\t\treg = <0x0180000 0x0140000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@2c0000 {\n\t\t\t\tlabel = \"0:SBL3\";\n\t\t\t\treg = <0x02c0000 0x0280000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@540000 {\n\t\t\t\tlabel = \"0:DDRCONFIG\";\n\t\t\t\treg = <0x0540000 0x0120000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@660000 {\n\t\t\t\tlabel = \"0:SSD\";\n\t\t\t\treg = <0x0660000 0x0120000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@780000 {\n\t\t\t\tlabel = \"0:TZ\";\n\t\t\t\treg = <0x0780000 0x0280000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@a00000 {\n\t\t\t\tlabel = \"0:RPM\";\n\t\t\t\treg = <0x0a00000 0x0280000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@c80000 {\n\t\t\t\tlabel = \"0:APPSBL\";\n\t\t\t\treg = <0x0c80000 0x0500000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@1180000 {\n\t\t\t\tlabel = \"0:APPSBLENV\";\n\t\t\t\treg = <0x1180000 0x0080000>;\n\t\t\t};\n\t\t\tpartition@1200000 {\n\t\t\t\tlabel = \"0:ART\";\n\t\t\t\treg = <0x1200000 0x0140000>;\n\t\t\t\tread-only;\n\n\t\t\t\tcompatible = \"nvmem-cells\";\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\n\t\t\t\tprecal_ART_1000: precal@1000 {\n\t\t\t\t\treg = <0x1000 0x2f20>;\n\t\t\t\t};\n\t\t\t\tprecal_ART_5000: precal@5000 {\n\t\t\t\t\treg = <0x5000 0x2f20>;\n\t\t\t\t};\n\t\t\t};\n\t\t\tstock_partition@1340000 {\n\t\t\t\tlabel = \"stock_rootfs\";\n\t\t\t\treg = <0x1340000 0x4000000>;\n\t\t\t};\n\t\t\tpartition@5340000 {\n\t\t\t\tlabel = \"0:BOOTCONFIG\";\n\t\t\t\treg = <0x5340000 0x0060000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@53a0000 {\n\t\t\t\tlabel = \"0:SBL2_1\";\n\t\t\t\treg = <0x53a0000 0x0140000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@54e0000 {\n\t\t\t\tlabel = \"0:SBL3_1\";\n\t\t\t\treg = <0x54e0000 0x0280000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@5760000 {\n\t\t\t\tlabel = \"0:DDRCONFIG_1\";\n\t\t\t\treg = <0x5760000 0x0120000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@5880000 {\n\t\t\t\tlabel = \"0:SSD_1\";\n\t\t\t\treg = <0x5880000 0x0120000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@59a0000 {\n\t\t\t\tlabel = \"0:TZ_1\";\n\t\t\t\treg = <0x59a0000 0x0280000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@5c20000 {\n\t\t\t\tlabel = \"0:RPM_1\";\n\t\t\t\treg = <0x5c20000 0x0280000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@5ea0000 {\n\t\t\t\tlabel = \"0:BOOTCONFIG1\";\n\t\t\t\treg = <0x5ea0000 0x0060000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@5f00000 {\n\t\t\t\tlabel = \"0:APPSBL_1\";\n\t\t\t\treg = <0x5f00000 0x0500000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tstock_partition@6400000 {\n\t\t\t\tlabel = \"stock_rootfs_1\";\n\t\t\t\treg = <0x6400000 0x4000000>;\n\t\t\t};\n\t\t\tstock_partition@a400000 {\n\t\t\t\tlabel = \"stock_fw_env\";\n\t\t\t\treg = <0xa400000 0x0100000>;\n\t\t\t};\n\t\t\tstock_partition@a500000 {\n\t\t\t\tlabel = \"stock_config\";\n\t\t\t\treg = <0xa500000 0x0800000>;\n\t\t\t};\n\t\t\tstock_partition@ad00000 {\n\t\t\t\tlabel = \"stock_PKI\";\n\t\t\t\treg = <0xad00000 0x0200000>;\n\t\t\t};\n\t\t\tstock_partition@af00000 {\n\t\t\t\tlabel = \"stock_scfgmgr\";\n\t\t\t\treg = <0xaf00000 0x0100000>;\n\t\t\t};\n\n\t\t\tpartition@6400000 {\n\t\t\t\tlabel = \"fw_env\";\n\t\t\t\treg = <0x6400000 0x0100000>;\n\n\t\t\t\tcompatible = \"nvmem-cells\";\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\n\t\t\t\tmacaddr_fw_env_0: macaddr@0 {\n\t\t\t\t\treg = <0x00 0x6>;\n\t\t\t\t};\n\t\t\t\tmacaddr_fw_env_6: macaddr@6 {\n\t\t\t\t\treg = <0x06 0x6>;\n\t\t\t\t};\n\t\t\t\tmacaddr_fw_env_c: macaddr@c {\n\t\t\t\t\treg = <0x0c 0x6>;\n\t\t\t\t};\n\t\t\t\tmacaddr_fw_env_12: macaddr@12 {\n\t\t\t\t\treg = <0x12 0x6>;\n\t\t\t\t};\n\t\t\t\tmacaddr_fw_env_18: macaddr@18 {\n\t\t\t\t\treg = <0x18 0x6>;\n\t\t\t\t};\n\t\t\t};\n\t\t\tpartition@6500000 {\n\t\t\t\tlabel = \"ubi\";\n\t\t\t\treg = <0x6500000 0x9b00000>;\n\t\t\t};\n\t\t\tpartition@1340000 {\n\t\t\t\tlabel = \"extra\";\n\t\t\t\treg = <0x1340000 0x4000000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tpinctrl-0 = <&mdio0_pins>;\n\tpinctrl-names = \"default\";\n\n\tethernet-phy@0 {\n\t\treg = <0x0>;\n\t\tqca,ar8327-initvals = <\n\t\t\t0x00004 0x7600000   /* PAD0_MODE */\n\t\t\t0x00008 0x1000000   /* PAD5_MODE */\n\t\t\t0x0000c 0x80        /* PAD6_MODE */\n\t\t\t0x000e4 0xaa545     /* MAC_POWER_SEL */\n\t\t\t0x000e0 0xc74164de  /* SGMII_CTRL */\n\t\t\t0x0007c 0x4e        /* PORT0_STATUS */\n\t\t\t0x00094 0x4e        /* PORT6_STATUS */\n\t\t\t>;\n\t};\n\n\tphy7: ethernet-phy@7 {\n\t\treg = <7>;\n\t};\n};\n\n&gmac0 {\n\tstatus = \"okay\";\n\tphy-mode = \"rgmii\";\n\tqcom,id = <0>;\n\n\tnvmem-cells = <&macaddr_fw_env_18>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tpinctrl-0 = <&rgmii2_pins>;\n\tpinctrl-names = \"default\";\n\n\tfixed-link {\n\t\tspeed = <1000>;\n\t\tfull-duplex;\n\t};\n};\n\n&gmac1 {\n\tstatus = \"okay\";\n\tphy-mode = \"sgmii\";\n\tqcom,id = <1>;\n\n\tnvmem-cells = <&macaddr_fw_env_0>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tfixed-link {\n\t\tspeed = <1000>;\n\t\tfull-duplex;\n\t};\n};\n\n&gmac3 {\n\tstatus = \"okay\";\n\tphy-mode = \"sgmii\";\n\tqcom,id = <3>;\n\tphy-handle = <&phy7>;\n\n\tnvmem-cells = <&macaddr_fw_env_6>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&adm_dma {\n\tstatus = \"okay\";\n};\n\n&usb3_1 {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\tstatus = \"okay\";\n\treset-gpio = <&qcom_pinmux 3 GPIO_ACTIVE_HIGH>;\n\tpinctrl-0 = <&pcie0_pins>;\n\tpinctrl-names = \"default\";\n\n\tbridge@0,0 {\n\t\treg = <0x00000000 0 0 0 0>;\n\t\t#address-cells = <3>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\twifi0: wifi@1,0 {\n\t\t\tcompatible = \"pci168c,0046\";\n\t\t\treg = <0x00010000 0 0 0 0>;\n\n\t\t\tnvmem-cells = <&precal_ART_1000>, <&macaddr_fw_env_12>;\n\t\t\tnvmem-cell-names = \"pre-calibration\", \"mac-address\";\n\t\t};\n\t};\n};\n\n&pcie1 {\n\tstatus = \"okay\";\n\treset-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_HIGH>;\n\tpinctrl-0 = <&pcie1_pins>;\n\tpinctrl-names = \"default\";\n\tmax-link-speed = <1>;\n\n\tbridge@0,0 {\n\t\treg = <0x00000000 0 0 0 0>;\n\t\t#address-cells = <3>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\twifi1: wifi@1,0 {\n\t\t\tcompatible = \"pci168c,0040\";\n\t\t\treg = <0x00010000 0 0 0 0>;\n\n\t\t\tnvmem-cells = <&precal_ART_5000>, <&macaddr_fw_env_c>;\n\t\t\tnvmem-cell-names = \"pre-calibration\", \"mac-address\";\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-xr500.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"qcom-ipq8065-nighthawk.dtsi\"\n\n/ {\n\tmodel = \"Netgear Nighthawk XR500\";\n\tcompatible = \"netgear,xr500\", \"qcom,ipq8065\", \"qcom,ipq8064\";\n\n};\n\n&leds {\n\tusb1 {\n\t\tlabel = \"white:usb1\";\n\t\tgpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;\n\t};\n\n\tusb2 {\n\t\tlabel = \"white:usb2\";\n\t\tgpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>;\n\t};\n};\n\n&partitions {\n\tpartition@1880000 {\n\t\tlabel = \"ubi\";\n\t\treg = <0x1880000 0xce00000>;\n\t};\n\n\tpartition@e680000 {\n\t\tlabel = \"reserve\";\n\t\treg = <0xe680000 0x0780000>;\n\t\tread-only;\n\t};\n};\n\n&wifi0 {\n\tnvmem-cells = <&macaddr_art_c>, <&precal_art_1000>;\n\tnvmem-cell-names = \"mac-address\", \"pre-calibration\";\n};\n\n&wifi1 {\n\tnvmem-cells = <&macaddr_art_0>, <&precal_art_5000>;\n\tnvmem-cell-names = \"mac-address\", \"pre-calibration\";\n};\n\n&art {\n\tmacaddr_art_c: macaddr@c {\n\t\treg = <0xc 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065.dtsi",
    "content": "#include \"qcom-ipq8064.dtsi\"\n\n/ {\n\tmodel = \"Qualcomm IPQ8065\";\n\tcompatible = \"qcom,ipq8065\", \"qcom,ipq8064\";\n\n\taliases {\n\t\tserial0 = &gsbi4_serial;\n\t};\n\n\tchosen {\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\treserved-memory {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tranges;\n\n\t\trsvd@41200000 {\n\t\t\treg = <0x41200000 0x300000>;\n\t\t\tno-map;\n\t\t};\n\t};\n};\n\n&gsbi4 {\n\tqcom,mode = <GSBI_PROT_I2C_UART>;\n\tstatus = \"okay\";\n\n\tserial@16340000 {\n\t\tstatus = \"okay\";\n\t};\n\t/*\n\t* The i2c device on gsbi4 should not be enabled.\n\t* On ipq806x designs gsbi4 i2c is meant for exclusive\n\t* RPM usage. Turning this on in kernel manifests as\n\t* i2c failure for the RPM.\n\t*/\n};\n\n&pcie0 {\n\tcompatible = \"qcom,pcie-ipq8064-v2\";\n};\n\n&pcie1 {\n\tcompatible = \"qcom,pcie-ipq8064-v2\";\n};\n\n&pcie2 {\n\tcompatible = \"qcom,pcie-ipq8064-v2\";\n};\n\n&sata {\n\tports-implemented = <0x1>;\n};\n\n&smb208_s2a {\n\tregulator-min-microvolt = <775000>;\n\tregulator-max-microvolt = <1275000>;\n};\n\n&smb208_s2b {\n\tregulator-min-microvolt = <775000>;\n\tregulator-max-microvolt = <1275000>;\n};\n\n&ss_phy_0 {\n\tqcom,rx-eq = <2>;\n\tqcom,tx-deamp_3_5db = <32>;\n\tqcom,mpll = <5>;\n};\n\n&ss_phy_1 {\n\tqcom,rx-eq = <2>;\n\tqcom,tx-deamp_3_5db = <32>;\n\tqcom,mpll = <5>;\n};\n\n&opp_table_l2 {\n\t/delete-node/opp-1200000000;\n\n\topp-1400000000 {\n\t\topp-hz = /bits/ 64 <1400000000>;\n\t\topp-microvolt = <1150000>;\n\t\tclock-latency-ns = <100000>;\n\t\topp-level = <2>;\n\t};\n};\n\n&opp_table0 {\n\t/* \n\t * On ipq8065 1.2 ghz freq is not present\n\t * Remove it to make cpufreq work and not\n\t * complain for missing definition\n\t */\n\n\t/delete-node/opp-1200000000;\n\n\t/*\n\t * Voltage thresholds are <target min max>\n\t */\n\topp-384000000 {\n\t\topp-microvolt-speed0-pvs0-v0 = <975000 926250 1023750>;\n\t\topp-microvolt-speed0-pvs1-v0 = <950000 902500 997500>;\n\t\topp-microvolt-speed0-pvs2-v0 = <925000 878750 971250>;\n\t\topp-microvolt-speed0-pvs3-v0 = <900000 855000 945000>;\n\t\topp-microvolt-speed0-pvs4-v0 = <875000 831250 918750>;\n\t\topp-microvolt-speed0-pvs5-v0 = <825000 783750 866250>;\n\t\topp-microvolt-speed0-pvs6-v0 = <775000 736250 813750>;\n\t};\n\n\topp-600000000 {\n\t\topp-microvolt-speed0-pvs0-v0 = <1000000 950000 1050000>;\n\t\topp-microvolt-speed0-pvs1-v0 = <975000 926250 1023750>;\n\t\topp-microvolt-speed0-pvs2-v0 = <950000 902500 997500>;\n\t\topp-microvolt-speed0-pvs3-v0 = <925000 878750 971250>;\n\t\topp-microvolt-speed0-pvs4-v0 = <900000 855000 945000>;\n\t\topp-microvolt-speed0-pvs5-v0 = <850000 807500 892500>;\n\t\topp-microvolt-speed0-pvs6-v0 = <800000 760000 840000>;\n\t};\n\n\topp-800000000 {\n\t\topp-microvolt-speed0-pvs0-v0 = <1050000 997500 1102500>;\n\t\topp-microvolt-speed0-pvs1-v0 = <1025000 973750 1076250>;\n\t\topp-microvolt-speed0-pvs2-v0 = <1000000 950000 1050000>;\n\t\topp-microvolt-speed0-pvs3-v0 = <975000 926250 1023750>;\n\t\topp-microvolt-speed0-pvs4-v0 = <950000 902500 997500>;\n\t\topp-microvolt-speed0-pvs5-v0 = <900000 855000 945000>;\n\t\topp-microvolt-speed0-pvs6-v0 = <850000 807500 892500>;\n\t};\n\n\topp-1000000000 {\n\t\topp-microvolt-speed0-pvs0-v0 = <1100000 1045000 1155000>;\n\t\topp-microvolt-speed0-pvs1-v0 = <1075000 1021250 1128750>;\n\t\topp-microvolt-speed0-pvs2-v0 = <1050000 997500 1102500>;\n\t\topp-microvolt-speed0-pvs3-v0 = <1025000 973750 1076250>;\n\t\topp-microvolt-speed0-pvs4-v0 = <1000000 950000 1050000>;\n\t\topp-microvolt-speed0-pvs5-v0 = <950000 902500 997500>;\n\t\topp-microvolt-speed0-pvs6-v0 = <900000 855000 945000>;\n\t};\n\n\topp-1400000000 {\n\t\topp-microvolt-speed0-pvs0-v0 = <1175000 1116250 1233750>;\n\t\topp-microvolt-speed0-pvs1-v0 = <1150000 1092500 1207500>;\n\t\topp-microvolt-speed0-pvs2-v0 = <1125000 1068750 1181250>;\n\t\topp-microvolt-speed0-pvs3-v0 = <1100000 1045000 1155000>;\n\t\topp-microvolt-speed0-pvs4-v0 = <1075000 1021250 1128750>;\n\t\topp-microvolt-speed0-pvs5-v0 = <1025000 973750 1076250>;\n\t\topp-microvolt-speed0-pvs6-v0 = <975000 926250 1023750>;\n\t\topp-level = <1>;\n\t};\n\n\topp-1725000000 {\n\t\topp-hz = /bits/ 64 <1725000000>;\n\t\topp-microvolt-speed0-pvs0-v0 = <1262500 1199375 1325625>;\n\t\topp-microvolt-speed0-pvs1-v0 = <1225000 1163750 1286250>;\n\t\topp-microvolt-speed0-pvs2-v0 = <1200000 1140000 1260000>;\n\t\topp-microvolt-speed0-pvs3-v0 = <1175000 1116250 1233750>;\n\t\topp-microvolt-speed0-pvs4-v0 = <1150000 1092500 1207500>;\n\t\topp-microvolt-speed0-pvs5-v0 = <1100000 1045000 1155000>;\n\t\topp-microvolt-speed0-pvs6-v0 = <1050000 997500 1102500>;\n\t\topp-supported-hw = <0x1>;\n\t\tclock-latency-ns = <100000>;\n\t\topp-level = <2>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8068-cryptid-common.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0 OR MIT\n\n#include \"qcom-ipq8064-v2.0.dtsi\"\n\n/ {\n\tmemory {\n\t\tdevice_type = \"memory\";\n\t\tlinux,usable-memory = <0x41500000 0x1ea00000>;\n\t\treg = <0x40000000 0x20000000>;\n\t};\n\n\tcpus {\n\t\tidle-states {\n\t\t\tCPU_SPC: spc {\n\t\t\t\tstatus = \"disabled\";\n\t\t\t};\n\t\t};\n\t};\n\n\tchosen {\n\t\tbootargs-append = \" console=ttyMSM0,115200n8 ubi.mtd=ubi ubi.mtd=art\";\n\t};\n};\n\n&qcom_pinmux {\n\tmdio0_pins_active: mdio0_pins_active {\n\t\tmux {\n\t\t\tpins = \"gpio0\", \"gpio1\";\n\t\t\tfunction = \"mdio\";\n\t\t\tdrive-strength = <2>;\n\t\t\tbias-pull-down;\n\t\t\toutput-low;\n\t\t};\n\n\t\tclk {\n\t\t\tpins = \"gpio1\";\n\t\t\tinput-disable;\n\t\t};\n\t};\n\n\tphy_active: phy_active {\n\t\tphy {\n\t\t\tpins = \"gpio6\", \"gpio7\";\n\t\t\tfunction = \"gpio\";\n\t\t\tdrive-strength = <2>;\n\t\t\tbias-pull-down;\n\t\t\toutput-high;\n\t\t};\n\t};\n\n\tuart1_pins: uart1_pins {\n\t\tmux {\n\t\t\tpins = \"gpio51\", \"gpio52\";\n\t\t\tfunction = \"gsbi1\";\n\t\t\tdrive-strength = <4>;\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&gsbi1 {\n\tstatus = \"okay\";\n\tqcom,mode = <GSBI_PROT_UART_W_FC>;\n\n\tserial@12450000 {\n\t\tstatus = \"okay\";\n\n\t\tpinctrl-0 = <&uart1_pins>;\n\t\tpinctrl-names = \"default\";\n\t};\n};\n\n&pcie0 {\n\tstatus = \"okay\";\n\n\t/delete-property/ pinctrl-0;\n\t/delete-property/ pinctrl-names;\n\t/delete-property/ perst-gpios;\n\n\tbridge@0,0 {\n\t\treg = <0x0 0 0 0 0>;\n\t\t#address-cells = <3>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\twifi0: wifi@1,0 {\n\t\t\tcompatible = \"qcom,ath10k\";\n\t\t\tstatus = \"okay\";\n\t\t\treg = <0x10000 0 0 0 0>;\n\t\t};\n\t};\n};\n\n&pcie1 {\n\tstatus = \"okay\";\n\n\t/delete-property/ pinctrl-0;\n\t/delete-property/ pinctrl-names;\n\t/delete-property/ perst-gpios;\n\n\tbridge@0,0 {\n\t\treg = <0x0 0 0 0 0>;\n\t\t#address-cells = <3>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\twifi1: wifi@1,0 {\n\t\t\tcompatible = \"qcom,ath10k\";\n\t\t\tstatus = \"okay\";\n\t\t\treg = <0x10000 0 0 0 0>;\n\t\t};\n\t};\n};\n\n&pcie2 {\n\tstatus = \"okay\";\n\n\t/delete-property/ pinctrl-0;\n\t/delete-property/ pinctrl-names;\n\t/delete-property/ perst-gpios;\n\n\tbridge@0,0 {\n\t\treg = <0x0 0 0 0 0>;\n\t\t#address-cells = <3>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\twifi2: wifi@1,0 {\n\t\t\tcompatible = \"qcom,ath10k\";\n\t\t\tstatus = \"okay\";\n\t\t\treg = <0x10000 0 0 0 0>;\n\t\t};\n\t};\n};\n\n&adm_dma {\n\tstatus = \"okay\";\n};\n\n&nand {\n\tstatus = \"okay\";\n\n\tpinctrl-0 = <&nand_pins>;\n\tpinctrl-names = \"default\";\n\n\tnand@0 {\n\t\tcompatible = \"qcom,nandcs\";\n\n\t\treg = <0>;\n\n\t\tnand-ecc-strength = <4>;\n\t\tnand-bus-width = <8>;\n\t\tnand-ecc-step-size = <512>;\n\n\t\tnand-is-boot-medium;\n\t\tqcom,boot_pages_size = <0x2140000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"sbl1\";\n\t\t\t\treg = <0x0 0x40000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"mibib\";\n\t\t\t\treg = <0x40000 0x140000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@180000 {\n\t\t\t\tlabel = \"sbl2\";\n\t\t\t\treg = <0x180000 0x140000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@2c0000 {\n\t\t\t\tlabel = \"sbl3\";\n\t\t\t\treg = <0x2c0000 0x280000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@540000 {\n\t\t\t\tlabel = \"ddrconfig\";\n\t\t\t\treg = <0x540000 0x120000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@660000 {\n\t\t\t\tlabel = \"ssd\";\n\t\t\t\treg = <0x660000 0x120000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@780000 {\n\t\t\t\tlabel = \"tz\";\n\t\t\t\treg = <0x780000 0x280000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@a00000 {\n\t\t\t\tlabel = \"rpm\";\n\t\t\t\treg = <0xa00000 0x280000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@1fc0000 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x1fc0000 0x180000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@21c0000 {\n\t\t\t\tlabel = \"bootkernel1\";\n\t\t\t\treg = <0x21c0000 0xa80000>;\n\t\t\t};\n\n\t\t\tpartition@2c40000 {\n\t\t\t\tlabel = \"bootkernel2\";\n\t\t\t\treg = <0x2c40000 0xa80000>;\n\t\t\t};\n\n\t\t\tpartition@36c0000 {\n\t\t\t\tlabel = \"ubi\";\n\t\t\t\treg = <0x36c0000 0x46c0000>;\n\t\t\t};\n\n\t\t\tpartition@7d80000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0x7d80000 0x200000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8068-ecw5410.dts",
    "content": "#include \"qcom-ipq8064-v2.0.dtsi\"\n\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/soc/qcom,tcsr.h>\n\n/ {\n\tmodel = \"Edgecore ECW5410\";\n\tcompatible = \"edgecore,ecw5410\", \"qcom,ipq8064\";\n\n\treserved-memory {\n\t\tnss@40000000 {\n\t\t\treg = <0x40000000 0x1000000>;\n\t\t\tno-map;\n\t\t};\n\n\t\tsmem: smem@41000000 {\n\t\t\treg = <0x41000000 0x200000>;\n\t\t\tno-map;\n\t\t};\n\n\t\twifi_dump@44000000 {\n\t\t\treg = <0x44000000 0x600000>;\n\t\t\tno-map;\n\t\t};\n\t};\n\n\tcpus {\n\t\tidle-states {\n\t\t\tCPU_SPC: spc {\n\t\t\t\tstatus = \"disabled\";\n\t\t\t};\n\t\t};\n\t};\n\n\taliases {\n\t\tserial1 = &gsbi1_serial;\n\t\tethernet0 = &gmac2;\n\t\tethernet1 = &gmac3;\n\n\t\tled-boot = &led_power_green;\n\t\tled-failsafe = &led_power_red;\n\t\tled-running = &led_power_green;\n\t\tled-upgrade = &led_power_green;\n\t};\n\n\tchosen {\n\t\tbootargs-append = \" console=ttyMSM0,115200n8 root=/dev/ubiblock0_1\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\t\tpinctrl-0 = <&button_pins>;\n\t\tpinctrl-names = \"default\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&qcom_pinmux 25 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tdebounce-interval = <60>;\n\t\t\twakeup-source;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tpinctrl-0 = <&led_pins>;\n\t\tpinctrl-names = \"default\";\n\n\t\tled_power_green: power_green {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&qcom_pinmux 16 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\twlan2g_green {\n\t\t\tlabel = \"green:wlan2g\";\n\t\t\tgpios = <&qcom_pinmux 23 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan2g_yellow {\n\t\t\tlabel = \"yellow:wlan2g\";\n\t\t\tgpios = <&qcom_pinmux 24 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan5g_green {\n\t\t\tlabel = \"green:wlan5g\";\n\t\t\tgpios = <&qcom_pinmux 26 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_power_red: power_red {\n\t\t\tlabel = \"red:power\";\n\t\t\tgpios = <&qcom_pinmux 28 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan5g_yellow {\n\t\t\tlabel = \"yellow:wlan5g\";\n\t\t\tgpios = <&qcom_pinmux 59 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n\n&qcom_pinmux {\n\tspi_pins: spi_pins {\n\t\tmux {\n\t\t\tpins = \"gpio18\", \"gpio19\";\n\t\t\tfunction = \"gsbi5\";\n\t\t\tdrive-strength = <10>;\n\t\t\tbias-pull-down;\n\t\t};\n\n\t\tclk {\n\t\t\tpins = \"gpio21\";\n\t\t\tfunction = \"gsbi5\";\n\t\t\tdrive-strength = <12>;\n\t\t\tbias-pull-down;\n\t\t};\n\n\t\tcs {\n\t\t\tpins = \"gpio20\";\n\t\t\tfunction = \"gpio\";\n\t\t\tdrive-strength = <10>;\n\t\t\tbias-pull-up;\n\t\t};\n\t};\n\n\tled_pins: led_pins {\n\t\tmux {\n\t\t\tpins = \"gpio16\", \"gpio23\", \"gpio24\", \"gpio26\",\n\t\t\t\t   \"gpio28\", \"gpio59\";\n\t\t\tfunction = \"gpio\";\n\t\t\tdrive-strength = <2>;\n\t\t\tbias-pull-up;\n\t\t};\n\t};\n\n\tbutton_pins: button_pins {\n\t\tmux {\n\t\t\tpins = \"gpio25\";\n\t\t\tfunction = \"gpio\";\n\t\t\tdrive-strength = <2>;\n\t\t\tbias-pull-up;\n\t\t};\n\t};\n\n\tuart1_pins: uart1_pins {\n\t\tmux {\n\t\t\tpins = \"gpio51\", \"gpio52\", \"gpio53\", \"gpio54\";\n\t\t\tfunction = \"gsbi1\";\n\t\t\tdrive-strength = <12>;\n\t\t\tbias-none;\n\t\t};\n\t};\n};\n\n&gsbi1 {\n\tqcom,mode = <GSBI_PROT_UART_W_FC>;\n\tstatus = \"okay\";\n\n\tserial@12450000 {\n\t\tstatus = \"okay\";\n\n\t\tpinctrl-0 = <&uart1_pins>;\n\t\tpinctrl-names = \"default\";\n\t};\n};\n\n&gsbi5 {\n\tqcom,mode = <GSBI_PROT_SPI>;\n\tstatus = \"okay\";\n\n\tspi4: spi@1a280000 {\n\t\tstatus = \"okay\";\n\t\tspi-max-frequency = <50000000>;\n\n\t\tpinctrl-0 = <&spi_pins>;\n\t\tpinctrl-names = \"default\";\n\n\t\tcs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>;\n\n\t\tm25p80@0 {\n\t\t\tcompatible = \"jedec,spi-nor\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\t\t\tspi-max-frequency = <50000000>;\n\t\t\treg = <0>;\n\n\t\t\tpartitions {\n\t\t\t\tcompatible = \"qcom,smem-part\";\n\t\t\t};\n\t\t};\n\t};\n};\n\n&hs_phy_0 {\t\t/* USB3 port 0 HS phy */\n\tstatus = \"okay\";\n};\n\n&hs_phy_1 {\t\t/* USB3 port 1 HS phy */\n\tstatus = \"okay\";\n};\n\n&ss_phy_0 {\t\t/* USB3 port 0 SS phy */\n\tstatus = \"okay\";\n};\n\n&ss_phy_1 {\t\t/* USB3 port 1 SS phy */\n\tstatus = \"okay\";\n};\n\n&usb3_0 {\n\tstatus = \"okay\";\n};\n\n&usb3_1 {\n\tstatus = \"okay\";\n};\n\n&pcie1 {\n\tstatus = \"okay\";\n\n\t/delete-property/ pinctrl-0;\n\t/delete-property/ pinctrl-names;\n\t/delete-property/ perst-gpios;\n\n\tbridge@0,0 {\n\t\treg = <0x00000000 0 0 0 0>;\n\t\t#address-cells = <3>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\twifi@1,0 {\n\t\t\tcompatible = \"qcom,ath10k\";\n\t\t\tstatus = \"okay\";\n\t\t\treg = <0x00010000 0 0 0 0>;\n\t\t\tqcom,ath10k-calibration-variant = \"Edgecore-ECW5410-L\";\n\t\t};\n\t};\n};\n\n&pcie2 {\n\tstatus = \"okay\";\n\n\t/delete-property/ pinctrl-0;\n\t/delete-property/ pinctrl-names;\n\t/delete-property/ perst-gpios;\n\n\tbridge@0,0 {\n\t\treg = <0x00000000 0 0 0 0>;\n\t\t#address-cells = <3>;\n\t\t#size-cells = <2>;\n\t\tranges;\n\n\t\twifi@1,0 {\n\t\t\tcompatible = \"qcom,ath10k\";\n\t\t\tstatus = \"okay\";\n\t\t\treg = <0x00010000 0 0 0 0>;\n\t\t\tqcom,ath10k-calibration-variant = \"Edgecore-ECW5410-L\";\n\t\t};\n\t};\n};\n\n&nand {\n\tstatus = \"okay\";\n\n\tpinctrl-0 = <&nand_pins>;\n\tpinctrl-names = \"default\";\n\n\tnand@0 {\n\t\tcompatible = \"qcom,nandcs\";\n\n\t\treg = <0>;\n\n\t\tnand-ecc-strength = <4>;\n\t\tnand-bus-width = <8>;\n\t\tnand-ecc-step-size = <512>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\trootfs1@0 {\n\t\t\t\tlabel = \"rootfs1\";\n\t\t\t\treg = <0x0000000 0x4000000>;\n\t\t\t};\n\n\t\t\trootfs2@4000000 {\n\t\t\t\tlabel = \"rootfs2\";\n\t\t\t\treg = <0x4000000 0x4000000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tpinctrl-0 = <&mdio0_pins>;\n\tpinctrl-names = \"default\";\n\n\tphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t};\n\n\tphy1: ethernet-phy@1 {\n\t\treg = <1>;\n\t};\n};\n\n&gmac2 {\n\tstatus = \"okay\";\n\n\tqcom,id = <2>;\n\tmdiobus = <&mdio0>;\n\n\tphy-mode = \"sgmii\";\n\tphy-handle = <&phy1>;\n};\n\n&gmac3 {\n\tstatus = \"okay\";\n\n\tqcom,id = <3>;\n\tmdiobus = <&mdio0>;\n\n\tphy-mode = \"sgmii\";\n\tphy-handle = <&phy0>;\n};\n\n&adm_dma {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8068-mr42.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0 OR MIT\n\n#include \"qcom-ipq8068-cryptid-common.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"Meraki MR42\";\n\tcompatible = \"meraki,mr42\", \"qcom,ipq8064\";\n\n\taliases {\n\t\tserial1 = &gsbi1_serial;\n\t\tethernet0 = &gmac3;\n\n\t\tled-boot = &led_active;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_active;\n\t\tled-upgrade = &led_active;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\t\tpinctrl-0 = <&button_pins>;\n\t\tpinctrl-names = \"default\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&qcom_pinmux 26 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tdebounce-interval = <60>;\n\t\t\twakeup-source;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tpinctrl-0 = <&led_pins>;\n\t\tpinctrl-names = \"default\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"orange:power\";\n\t\t\tgpios = <&qcom_pinmux 31 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tled_active: active {\n\t\t\tlabel = \"white:active\";\n\t\t\tgpios = <&qcom_pinmux 32 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&gmac3 {\n\tstatus = \"okay\";\n\n\tqcom,id = <3>;\n\tmdiobus = <&mdio0>;\n\n\tphy-mode = \"sgmii\";\n\tphy-handle = <&phy2>;\n\n\tnvmem-cells = <&mac_address>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&gsbi2 {\n\tstatus = \"okay\";\n\tqcom,mode = <GSBI_PROT_I2C>;\n};\n\n&gsbi2_i2c {\n\tstatus = \"okay\";\n\n\tpinctrl-0 = <&i2c0_pins>;\n\tpinctrl-names = \"default\";\n\n\tina2xx@40 {\n\t\tcompatible = \"ina219\";\n\t\tshunt-resistor = <40000>;\n\t\treg = <0x40>;\n\t};\n\n\teeprom@56 {\n\t\tcompatible = \"atmel,24c64\";\n\t\tpagesize = <32>;\n\t\treg = <0x56>;\n\t\tread-only;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tmac_address: mac-address@66 {\n\t\t\treg = <0x66 0x6>;\n\t\t};\n\t};\n};\n\n&gsbi6 {\n\tqcom,mode = <GSBI_PROT_I2C>;\n\tstatus = \"okay\";\n};\n\n&gsbi6_i2c {\n\tstatus = \"okay\";\n\n\tpinctrl-0 = <&i2c1_pins>;\n\tpinctrl-names = \"default\";\n\n\ttlc591xx@40 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tcompatible = \"ti,tlc59108\";\n\t\treg = <0x40>;\n\n\t\tred@0 {\n\t\t\tlabel = \"red:user\";\n\t\t\treg = <0x0>;\n\t\t};\n\n\t\tgreen@1 {\n\t\t\tlabel = \"green:user\";\n\t\t\treg = <0x1>;\n\t\t};\n\n\t\tblue@2 {\n\t\t\tlabel = \"blue:user\";\n\t\t\treg = <0x2>;\n\t\t};\n\t};\n};\n\n&mdio0 {\n\tstatus = \"okay\";\n\n\tpinctrl-0 = <&mdio0_pins_active>, <&phy_active>;\n\tpinctrl-names = \"default\";\n\n\tphy2: ethernet-phy2 {\n\t\treg = <2>;\n\n\t\treset-gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>;\n\t\treset-assert-us = <24000>;\n\n\t\teee-broken-100tx;\n\t\teee-broken-1000t;\n\t};\n};\n\n&qcom_pinmux {\n\ti2c0_pins: i2c0_pins {\n\t\tmux {\n\t\t\tpins = \"gpio24\", \"gpio25\";\n\t\t\tfunction = \"gsbi2\";\n\t\t\tdrive-strength = <2>;\n\t\t\tbias-pull-up;\n\t\t\tinput;\n\t\t};\n\t};\n\n\tbutton_pins: button_pins {\n\t\tmux {\n\t\t\tpins = \"gpio26\";\n\t\t\tfunction = \"gpio\";\n\t\t\tdrive-strength = <2>;\n\t\t\tbias-pull-up;\n\t\t};\n\t};\n\n\ti2c1_pins: i2c1_pins {\n\t\tmux {\n\t\t\tpins = \"gpio29\", \"gpio30\";\n\t\t\tfunction = \"gsbi6\";\n\t\t\tdrive-strength = <2>;\n\t\t\tbias-pull-up;\n\t\t\tinput;\n\t\t};\n\t};\n\n\tled_pins: led_pins {\n\t\tmux {\n\t\t\tpins = \"gpio31\", \"gpio32\";\n\t\t\tfunction = \"gpio\";\n\t\t\tdrive-strength = <12>;\n\t\t\tbias-pull-down;\n\t\t\toutput-low;\n\t\t};\n\t};\n};\n\n&wifi0 {\n\tnvmem-cells = <&mac_address>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <1>;\n};\n\n&wifi1 {\n\tnvmem-cells = <&mac_address>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <2>;\n};\n\n&wifi2 {\n\tnvmem-cells = <&mac_address>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <3>;\n};\n"
  },
  {
    "path": "target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8068-mr52.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0 OR MIT\n\n#include \"qcom-ipq8068-cryptid-common.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"Meraki MR52\";\n\tcompatible = \"meraki,mr52\", \"qcom,ipq8064\";\n\n\taliases {\n\t\tserial1 = &gsbi1_serial;\n\t\tmdio-gpio0 = &mdio_gpio0;\n\t\tethernet0 = &gmac2;\n\t\tethernet1 = &gmac3;\n\n\t\tled-boot = &led_active;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_active;\n\t\tled-upgrade = &led_active;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\t\tpinctrl-0 = <&button_pins>;\n\t\tpinctrl-names = \"default\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&qcom_pinmux 25 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tdebounce-interval = <60>;\n\t\t\twakeup-source;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tpinctrl-0 = <&led_pins>;\n\t\tpinctrl-names = \"default\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"orange:power\";\n\t\t\tgpios = <&qcom_pinmux 19 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tlan2_green {\n\t\t\tlabel = \"green:lan2\";\n\t\t\tgpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tlan1_green {\n\t\t\tlabel = \"green:lan1\";\n\t\t\tgpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tled_active: active {\n\t\t\tlabel = \"white:active\";\n\t\t\tgpios = <&qcom_pinmux 26 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan2_orange {\n\t\t\tlabel = \"orange:lan2\";\n\t\t\tgpios = <&qcom_pinmux 60 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tlan1_orange {\n\t\t\tlabel = \"orange:lan1\";\n\t\t\tgpios = <&qcom_pinmux 62 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&gmac2 {\n\tstatus = \"okay\";\n\n\tqcom,id = <2>;\n\tmdiobus = <&mdio0>;\n\n\tphy-mode = \"sgmii\";\n\tphy-handle = <&phy0>;\n\n\tnvmem-cells = <&mac_address>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&gmac3 {\n\tstatus = \"okay\";\n\n\tqcom,id = <3>;\n\tmdiobus = <&mdio_gpio0>;\n\n\tphy-mode = \"sgmii\";\n\tphy-handle = <&phy4>;\n\n\tnvmem-cells = <&mac_address>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <1>;\n};\n\n&gsbi7 {\n\tstatus = \"okay\";\n\tqcom,mode = <GSBI_PROT_I2C>;\n};\n\n&gsbi7_i2c {\n\tstatus = \"okay\";\n\n\tpinctrl-0 = <&i2c_pins>;\n\tpinctrl-names = \"default\";\n\n\tina2xx@45 {\n\t\tcompatible = \"ina219\";\n\t\tshunt-resistor = <80000>;\n\t\treg = <0x45>;\n\t};\n\n\ttlc591xx@49 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tcompatible = \"ti,tlc59108\";\n\t\treg = <0x49>;\n\n\t\tred@0 {\n\t\t\tlabel = \"red:user\";\n\t\t\treg = <0x0>;\n\t\t};\n\n\t\tgreen@1 {\n\t\t\tlabel = \"green:user\";\n\t\t\treg = <0x1>;\n\t\t};\n\n\t\tblue@2 {\n\t\t\tlabel = \"blue:user\";\n\t\t\treg = <0x2>;\n\t\t};\n\t};\n\n\teeprom@52 {\n\t\tcompatible = \"atmel,24c64\";\n\t\tpagesize = <32>;\n\t\treg = <0x52>;\n\t\tread-only;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tmac_address: mac-address@66 {\n\t\t\treg = <0x66 0x6>;\n\t\t};\n\t};\n};\n\n&qcom_pinmux {\n\ti2c_pins: i2c_pins {\n\t\tmux {\n\t\t\tpins = \"gpio8\", \"gpio9\";\n\t\t\tfunction = \"gsbi7\";\n\t\t\tdrive-strength = <2>;\n\t\t\tbias-pull-up;\n\t\t\tinput;\n\t\t};\n\t};\n\n\tled_pins: led_pins {\n\t\tmux {\n\t\t\tpins = \"gpio19\", \"gpio26\";\n\t\t\tfunction = \"gpio\";\n\t\t\tdrive-strength = <12>;\n\t\t\tbias-pull-down;\n\t\t\toutput-low;\n\t\t};\n\t};\n\n\tbutton_pins: button_pins {\n\t\tmux {\n\t\t\tpins = \"gpio25\";\n\t\t\tfunction = \"gpio\";\n\t\t\tdrive-strength = <2>;\n\t\t\tbias-pull-up;\n\t\t\tinput;\n\t\t};\n\t};\n};\n\n&soc {\n\tmdio_gpio0: mdio {\n\t\tcompatible = \"virtual,mdio-gpio\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tstatus = \"okay\";\n\n\t\tpinctrl-0 = <&mdio0_pins_active>, <&phy_active>;\n\t\tpinctrl-names = \"default\";\n\n\t\tgpios = <&qcom_pinmux 1 GPIO_ACTIVE_HIGH\n\t\t\t &qcom_pinmux 0 GPIO_ACTIVE_HIGH>;\n\n\t\tphy0: ethernet-phy0 {\n\t\t\treg = <0>;\n\t\t\treset-gpios = <&qcom_pinmux 7 GPIO_ACTIVE_LOW>;\n\t\t\treset-assert-us = <24000>;\n\t\t};\n\n\t\tphy4: ethernet-phy4 {\n\t\t\treg = <4>;\n\t\t\treset-gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>;\n\t\t\treset-assert-us = <24000>;\n\t\t};\n\t};\n};\n\n&wifi0 {\n\tnvmem-cells = <&mac_address>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <4>;\n};\n\n&wifi1 {\n\tnvmem-cells = <&mac_address>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <3>;\n};\n\n&wifi2 {\n\tnvmem-cells = <&mac_address>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <2>;\n};\n"
  },
  {
    "path": "target/linux/ipq806x/generic/target.mk",
    "content": "BOARDNAME:=Generic\n"
  },
  {
    "path": "target/linux/ipq806x/image/Makefile",
    "content": "# Copyright (c) 2014 The Linux Foundation. All rights reserved.\n#\ninclude $(TOPDIR)/rules.mk\ninclude $(INCLUDE_DIR)/image.mk\n\ndefine Device/Default\n\tPROFILES := Default\n\tKERNEL_DEPENDS = $$(wildcard $(DTS_DIR)/$$(DEVICE_DTS).dts)\n\tKERNEL_LOADADDR = 0x42208000\n\tDEVICE_DTS = $$(SOC)-$(lastword $(subst _, ,$(1)))\n\tDEVICE_DTS_CONFIG := config@1\n\tIMAGES := sysupgrade.bin\n\tIMAGE/sysupgrade.bin = sysupgrade-tar | append-metadata\n\tIMAGE/sysupgrade.bin/squashfs :=\nendef\n\ndefine Device/LegacyImage\n\tKERNEL_SUFFIX := -uImage\n\tKERNEL = kernel-bin | append-dtb | uImage none\n\tKERNEL_NAME := zImage\nendef\n\ndefine Device/FitImage\n\tKERNEL_SUFFIX := -fit-uImage.itb\n\tKERNEL = kernel-bin | gzip | fit gzip $$(DTS_DIR)/$$(DEVICE_DTS).dtb\n\tKERNEL_NAME := Image\nendef\n\ndefine Device/FitImageLzma\n\tKERNEL_SUFFIX := -fit-uImage.itb\n\tKERNEL = kernel-bin | lzma | fit lzma $$(DTS_DIR)/$$(DEVICE_DTS).dtb\n\tKERNEL_NAME := Image\nendef\n\ndefine Device/UbiFit\n\tKERNEL_IN_UBI := 1\n\tIMAGES := nand-factory.bin nand-sysupgrade.bin\n\tIMAGE/nand-factory.bin := append-ubi\n\tIMAGE/nand-sysupgrade.bin := sysupgrade-tar | append-metadata\nendef\n\ninclude $(SUBTARGET).mk\n\n$(eval $(call BuildImage))\n"
  },
  {
    "path": "target/linux/ipq806x/image/generic.mk",
    "content": "DEVICE_VARS += NETGEAR_BOARD_ID NETGEAR_HW_ID\nDEVICE_VARS += TPLINK_BOARD_ID\n\ndefine Device/kernel-size-migration\n  DEVICE_COMPAT_VERSION := 2.0\n  DEVICE_COMPAT_MESSAGE := *** Kernel partition size has changed from earlier \\\n\tversions. You need to sysupgrade with the OpenWrt factory image and \\\n\tuse the force flag when image check fails. Settings will be lost. ***\nendef\n\ndefine Build/buffalo-rootfs-cksum\n\t( \\\n\t\techo -ne \"\\x$$(od -A n -t u1 $@ | tr -s ' ' '\\n' | \\\n\t\t\t$(STAGING_DIR_HOST)/bin/awk '{s+=$$0}END{printf \"%x\", 255-s%256}')\"; \\\n\t) >> $@\nendef\n\ndefine Build/edimax-header\n\t$(eval edimax_model=$(word 1,$(1)))\n\n\t$(STAGING_DIR_HOST)/bin/mkedimaximg \\\n\t-b -s CSYS -m $(edimax_model) \\\n\t-f 0x70000 -S 0x1200000 \\\n\t-i $@ -o $@.new\n\t@mv $@.new $@\nendef\n\ndefine Device/DniImage\n\tKERNEL_SUFFIX := -uImage\n\tKERNEL = kernel-bin | append-dtb | uImage none\n\tKERNEL_NAME := zImage\n\tNETGEAR_BOARD_ID :=\n\tNETGEAR_HW_ID :=\n\tUBINIZE_OPTS := -E 5\n\tIMAGES += factory.img\n\tIMAGE/factory.img := append-kernel | pad-offset $$$$(BLOCKSIZE) 64 | \\\n\t\tappend-uImage-fakehdr filesystem | pad-to $$$$(KERNEL_SIZE) | \\\n\t\tappend-ubi | netgear-dni\n\tIMAGE/sysupgrade.bin := append-kernel | pad-offset $$$$(BLOCKSIZE) 64 | \\\n\t\tappend-uImage-fakehdr filesystem | sysupgrade-tar kernel=$$$$@ | \\\n\t\tappend-metadata\nendef\n\ndefine Device/TpSafeImage\n\tKERNEL_SUFFIX := -uImage\n\tKERNEL = kernel-bin | append-dtb | uImage none\n\tKERNEL_NAME := zImage\n\tTPLINK_BOARD_ID :=\n\tIMAGES += factory.bin\n\tIMAGE/factory.bin := append-rootfs | tplink-safeloader factory\n\tIMAGE/sysupgrade.bin := append-rootfs | \\\n\t\ttplink-safeloader sysupgrade | append-metadata\nendef\n\ndefine Device/ZyXELImage\n\tKERNEL_SUFFIX := -uImage\n\tKERNEL = kernel-bin | append-dtb | uImage none | \\\n\t\tpad-to $$(KERNEL_SIZE)\n\tKERNEL_NAME := zImage\n\tIMAGES += factory.bin\n\tIMAGE/factory.bin := append-rootfs | pad-rootfs | \\\n\t\tpad-to $$$$(BLOCKSIZE) | zyxel-ras-image separate-kernel\n\tIMAGE/sysupgrade.bin/squashfs := append-rootfs | \\\n\t\tpad-to $$$$(BLOCKSIZE) | sysupgrade-tar rootfs=$$$$@ | \\\n\t\tappend-metadata\nendef\n\ndefine Device/arris_tr4400-v2\n\t$(call Device/LegacyImage)\n\tDEVICE_VENDOR := Arris\n\tDEVICE_MODEL := TR4400\n\tDEVICE_VARIANT := v2\n\tSOC := qcom-ipq8065\n\tBLOCKSIZE := 128k\n\tPAGESIZE := 2048\n\tDEVICE_PACKAGES := ath10k-firmware-qca9984-ct ath10k-firmware-qca99x0-ct\n\tKERNEL_IN_UBI := 1\nendef\nTARGET_DEVICES += arris_tr4400-v2\n\ndefine Device/askey_rt4230w-rev6\n\t$(call Device/LegacyImage)\n\tDEVICE_VENDOR := Askey\n\tDEVICE_MODEL := RT4230W\n\tDEVICE_VARIANT := REV6\n\tSOC := qcom-ipq8065\n\tBLOCKSIZE := 128k\n\tPAGESIZE := 2048\n\tDEVICE_PACKAGES := ath10k-firmware-qca9984-ct\n\tKERNEL_IN_UBI := 1\nendef\nTARGET_DEVICES += askey_rt4230w-rev6\n\ndefine Device/asrock_g10\n\t$(call Device/FitImage)\n\t$(call Device/UbiFit)\n\tSOC := qcom-ipq8064\n\tDEVICE_VENDOR := ASRock\n\tDEVICE_MODEL := G10\n\tBLOCKSIZE := 128k\n\tPAGESIZE := 2048\n\tKERNEL_SIZE := 5332k\n\tDEVICE_PACKAGES := kmod-i2c-gpio ath10k-firmware-qca99x0-ct\n\tIMAGE/nand-factory.bin := append-ubi | edimax-header RN67\nendef\nTARGET_DEVICES += asrock_g10\n\ndefine Device/buffalo_wxr-2533dhp\n\t$(call Device/LegacyImage)\n\tSOC := qcom-ipq8064\n\tDEVICE_VENDOR := Buffalo\n\tDEVICE_MODEL := WXR-2533DHP\n\tBLOCKSIZE := 128k\n\tPAGESIZE := 2048\n\tIMAGE_SIZE := 65536k\n\tKERNEL_IN_UBI := 1\n\tIMAGE/sysupgrade.bin := append-rootfs | buffalo-rootfs-cksum | \\\n\t\tsysupgrade-tar rootfs=$$$$@ | append-metadata\n\tDEVICE_PACKAGES := ath10k-firmware-qca99x0-ct\nendef\nTARGET_DEVICES += buffalo_wxr-2533dhp\n\ndefine Device/compex_wpq864\n\t$(call Device/FitImage)\n\t$(call Device/UbiFit)\n\tDEVICE_VENDOR := Compex\n\tDEVICE_MODEL := WPQ864\n\tBLOCKSIZE := 128k\n\tPAGESIZE := 2048\n\tSOC := qcom-ipq8064\n\tDEVICE_PACKAGES := kmod-gpio-beeper\nendef\nTARGET_DEVICES += compex_wpq864\n\ndefine Device/edgecore_ecw5410\n\t$(call Device/FitImage)\n\t$(call Device/UbiFit)\n\tDEVICE_VENDOR := Edgecore\n\tDEVICE_MODEL := ECW5410\n\tSOC := qcom-ipq8068\n\tBLOCKSIZE := 128k\n\tPAGESIZE := 2048\n\tDEVICE_DTS_CONFIG := config@v2.0-ap160\n\tDEVICE_PACKAGES := ath10k-firmware-qca9984-ct \\\n\t\tipq-wifi-edgecore_ecw5410\nendef\nTARGET_DEVICES += edgecore_ecw5410\n\ndefine Device/linksys_ea7500-v1\n\t$(call Device/LegacyImage)\n\t$(Device/kernel-size-migration)\n\tDEVICE_VENDOR := Linksys\n\tDEVICE_MODEL := EA7500\n\tDEVICE_VARIANT := v1\n\tSOC := qcom-ipq8064\n\tPAGESIZE := 2048\n\tBLOCKSIZE := 128k\n\tKERNEL_SIZE := 4096k\n\tKERNEL = kernel-bin | append-dtb | uImage none | \\\n\t\tappend-uImage-fakehdr filesystem\n\tUBINIZE_OPTS := -E 5\n\tIMAGES := factory.bin sysupgrade.bin\n\tIMAGE/factory.bin := append-kernel | pad-to $$$$(KERNEL_SIZE) | \\\n\t\tappend-ubi | pad-to $$$$(PAGESIZE)\n\tDEVICE_PACKAGES := ath10k-firmware-qca99x0-ct\nendef\nTARGET_DEVICES += linksys_ea7500-v1\n\ndefine Device/linksys_ea8500\n\t$(call Device/LegacyImage)\n\t$(Device/kernel-size-migration)\n\tDEVICE_VENDOR := Linksys\n\tDEVICE_MODEL := EA8500\n\tSOC := qcom-ipq8064\n\tPAGESIZE := 2048\n\tBLOCKSIZE := 128k\n\tKERNEL_SIZE := 4096k\n\tKERNEL = kernel-bin | append-dtb | uImage none | \\\n\t\tappend-uImage-fakehdr filesystem\n\tBOARD_NAME := ea8500\n\tSUPPORTED_DEVICES += ea8500\n\tUBINIZE_OPTS := -E 5\n\tIMAGES += factory.bin\n\tIMAGE/factory.bin := append-kernel | pad-to $$$$(KERNEL_SIZE) | \\\n\t\tappend-ubi\n\tDEVICE_PACKAGES := ath10k-firmware-qca99x0-ct\nendef\nTARGET_DEVICES += linksys_ea8500\n\ndefine Device/meraki_mr42\n\t$(call Device/FitImage)\n\tDEVICE_VENDOR := Cisco Meraki\n\tDEVICE_MODEL := MR42\n\tSOC := qcom-ipq8068\n\tBLOCKSIZE := 128k\n\tPAGESIZE := 2048\n\tKERNEL_LOADADDR = 0x44208000\n\tDEVICE_PACKAGES := -swconfig -kmod-ata-ahci -kmod-ata-ahci-platform \\\n\t\t-kmod-usb-ohci -kmod-usb2 -kmod-usb-ledtrig-usbport \\\n\t\t-kmod-phy-qcom-ipq806x-usb -kmod-usb3 -kmod-usb-dwc3-qcom \\\n\t\t-uboot-envtools ath10k-firmware-qca9887-ct \\\n\t\tath10k-firmware-qca99x0-ct kmod-eeprom-at24 kmod-hwmon-ina2xx \\\n\t\tkmod-leds-tlc591xx\nendef\nTARGET_DEVICES += meraki_mr42\n\ndefine Device/meraki_mr52\n\t$(call Device/FitImage)\n\tDEVICE_VENDOR := Cisco Meraki\n\tDEVICE_MODEL := MR52\n\tSOC := qcom-ipq8068\n\tBLOCKSIZE := 128k\n\tPAGESIZE := 2048\n\tKERNEL_LOADADDR = 0x44208000\n\tDEVICE_DTS_CONFIG := config@2\n\tDEVICE_PACKAGES := -swconfig -kmod-ata-ahci -kmod-ata-ahci-platform \\\n\t\t-kmod-usb-ohci -kmod-usb2 -kmod-usb-ledtrig-usbport \\\n\t\t-kmod-phy-qcom-ipq806x-usb -kmod-usb3 -kmod-usb-dwc3-qcom \\\n\t\t-uboot-envtools ath10k-firmware-qca9887-ct \\\n\t\tath10k-firmware-qca9984-ct kmod-eeprom-at24 kmod-hwmon-ina2xx \\\n\t\tkmod-leds-tlc591xx\nendef\nTARGET_DEVICES += meraki_mr52\n\ndefine Device/nec_wg2600hp\n\t$(call Device/LegacyImage)\n\tDEVICE_VENDOR := NEC\n\tDEVICE_MODEL := Aterm WG2600HP\n\tSOC := qcom-ipq8064\n\tBLOCKSIZE := 64k\n\tBOARD_NAME := wg2600hp\n\tIMAGE/sysupgrade.bin := append-kernel | append-rootfs | \\\n\t\tpad-rootfs | append-metadata\n\tDEVICE_PACKAGES := ath10k-firmware-qca99x0-ct\nendef\nTARGET_DEVICES += nec_wg2600hp\n\ndefine Device/nec_wg2600hp3\n\t$(call Device/LegacyImage)\n\tDEVICE_VENDOR := NEC Platforms\n\tDEVICE_MODEL := Aterm WG2600HP3\n\tSOC := qcom-ipq8062\n\tBLOCKSIZE := 64k\n\tIMAGES := sysupgrade.bin\n\tIMAGE/sysupgrade.bin := append-kernel | append-rootfs | \\\n\t\tpad-rootfs | append-metadata\n\tDEVICE_PACKAGES := -kmod-ata-ahci -kmod-ata-ahci-platform \\\n\t\t-kmod-usb-ohci -kmod-usb2 -kmod-usb-ledtrig-usbport \\\n\t\t-kmod-usb-phy-qcom-dwc3 -kmod-usb3 -kmod-usb-dwc3-qcom \\\n\t\tath10k-firmware-qca9984-ct\nendef\nTARGET_DEVICES += nec_wg2600hp3\n\ndefine Device/netgear_d7800\n\t$(call Device/DniImage)\n\tDEVICE_VENDOR := NETGEAR\n\tDEVICE_MODEL := Nighthawk X4 D7800\n\tSOC := qcom-ipq8064\n\tKERNEL_SIZE := 4096k\n\tNETGEAR_BOARD_ID := D7800\n\tNETGEAR_HW_ID := 29764958+0+128+512+4x4+4x4\n\tBLOCKSIZE := 128k\n\tPAGESIZE := 2048\n\tBOARD_NAME := d7800\n\tSUPPORTED_DEVICES += d7800\n\tDEVICE_PACKAGES := ath10k-firmware-qca99x0-ct\n\tDEVICE_COMPAT_VERSION := 2.0\n\tDEVICE_COMPAT_MESSAGE := Sysupgrade does not work due to rootfs ubi partition size change. \\\n\t\tUse factory image with the TFTP recovery flash routine.\nendef\nTARGET_DEVICES += netgear_d7800\n\ndefine Device/netgear_r7500\n\t$(call Device/DniImage)\n\tDEVICE_VENDOR := NETGEAR\n\tDEVICE_MODEL := Nighthawk X4 R7500\n\tDEVICE_VARIANT := v1\n\tSOC := qcom-ipq8064\n\tKERNEL_SIZE := 4096k\n\tNETGEAR_BOARD_ID := R7500\n\tNETGEAR_HW_ID := 29764841+0+128+256+3x3+4x4\n\tBLOCKSIZE := 128k\n\tPAGESIZE := 2048\n\tBOARD_NAME := r7500\n\tSUPPORTED_DEVICES += r7500\n\tDEVICE_PACKAGES := ath10k-firmware-qca988x-ct\nendef\nTARGET_DEVICES += netgear_r7500\n\ndefine Device/netgear_r7500v2\n\t$(call Device/DniImage)\n\tDEVICE_VENDOR := NETGEAR\n\tDEVICE_MODEL := Nighthawk X4 R7500\n\tDEVICE_VARIANT := v2\n\tSOC := qcom-ipq8064\n\tKERNEL_SIZE := 4096k\n\tNETGEAR_BOARD_ID := R7500v2\n\tNETGEAR_HW_ID := 29764958+0+128+512+3x3+4x4\n\tBLOCKSIZE := 128k\n\tPAGESIZE := 2048\n\tBOARD_NAME := r7500v2\n\tSUPPORTED_DEVICES += r7500v2\n\tDEVICE_PACKAGES := ath10k-firmware-qca99x0-ct \\\n\t\tath10k-firmware-qca988x-ct\nendef\nTARGET_DEVICES += netgear_r7500v2\n\ndefine Device/netgear_r7800\n\t$(call Device/DniImage)\n\tDEVICE_VENDOR := NETGEAR\n\tDEVICE_MODEL := Nighthawk X4S R7800\n\tSOC := qcom-ipq8065\n\tKERNEL_SIZE := 4096k\n\tNETGEAR_BOARD_ID := R7800\n\tNETGEAR_HW_ID := 29764958+0+128+512+4x4+4x4+cascade\n\tBLOCKSIZE := 128k\n\tPAGESIZE := 2048\n\tBOARD_NAME := r7800\n\tSUPPORTED_DEVICES += r7800\n\tDEVICE_PACKAGES := ath10k-firmware-qca9984-ct kmod-ramoops\nendef\nTARGET_DEVICES += netgear_r7800\n\ndefine Device/netgear_xr500\n\t$(call Device/DniImage)\n\tDEVICE_VENDOR := NETGEAR\n\tDEVICE_MODEL := Nighthawk XR500\n\tSOC := qcom-ipq8065\n\tKERNEL_SIZE := 4096k\n\tNETGEAR_BOARD_ID := XR500\n\tNETGEAR_HW_ID := 29764958+0+256+512+4x4+4x4+cascade\n\tBLOCKSIZE := 128k\n\tPAGESIZE := 2048\n\tDEVICE_PACKAGES := ath10k-firmware-qca9984-ct kmod-ramoops\nendef\nTARGET_DEVICES += netgear_xr500\n\ndefine Device/qcom_ipq8064-ap148\n\t$(call Device/FitImage)\n\t$(call Device/UbiFit)\n\tDEVICE_VENDOR := Qualcomm\n\tDEVICE_MODEL := AP148\n\tDEVICE_VARIANT := standard\n\tSOC := qcom-ipq8064\n\tDEVICE_DTS := qcom-ipq8064-ap148\n\tKERNEL_INSTALL := 1\n\tBLOCKSIZE := 128k\n\tPAGESIZE := 2048\n\tBOARD_NAME := ap148\n\tSUPPORTED_DEVICES += ap148\n\tDEVICE_PACKAGES := ath10k-firmware-qca99x0-ct\nendef\nTARGET_DEVICES += qcom_ipq8064-ap148\n\ndefine Device/qcom_ipq8064-ap148-legacy\n\t$(call Device/LegacyImage)\n\t$(call Device/UbiFit)\n\tDEVICE_VENDOR := Qualcomm\n\tDEVICE_MODEL := AP148\n\tDEVICE_VARIANT := legacy\n\tSOC := qcom-ipq8064\n\tDEVICE_DTS := qcom-ipq8064-ap148\n\tBLOCKSIZE := 128k\n\tPAGESIZE := 2048\n\tBOARD_NAME := ap148\n\tSUPPORTED_DEVICES := qcom,ipq8064-ap148 ap148\n\tDEVICE_PACKAGES := ath10k-firmware-qca99x0-ct\nendef\nTARGET_DEVICES += qcom_ipq8064-ap148-legacy\n\ndefine Device/qcom_ipq8064-ap161\n\t$(call Device/FitImage)\n\t$(call Device/UbiFit)\n\tDEVICE_VENDOR := Qualcomm\n\tDEVICE_MODEL := AP161\n\tSOC := qcom-ipq8064\n\tDEVICE_DTS := qcom-ipq8064-ap161\n\tKERNEL_INSTALL := 1\n\tBLOCKSIZE := 128k\n\tPAGESIZE := 2048\n\tBOARD_NAME := ap161\n\tDEVICE_PACKAGES := ath10k-firmware-qca99x0-ct\nendef\nTARGET_DEVICES += qcom_ipq8064-ap161\n\ndefine Device/qcom_ipq8064-db149\n\t$(call Device/FitImage)\n\tDEVICE_VENDOR := Qualcomm\n\tDEVICE_MODEL := DB149\n\tSOC := qcom-ipq8064\n\tDEVICE_DTS := qcom-ipq8064-db149\n\tKERNEL_INSTALL := 1\n\tBOARD_NAME := db149\n\tDEVICE_PACKAGES := ath10k-firmware-qca99x0-ct\nendef\nTARGET_DEVICES += qcom_ipq8064-db149\n\ndefine Device/tplink_ad7200\n\t$(call Device/TpSafeImage)\n\tDEVICE_VENDOR := TP-Link\n\tDEVICE_MODEL := AD7200\n\tDEVICE_VARIANT := v1/v2\n\tDEVICE_ALT0_VENDOR := TP-Link\n\tDEVICE_ALT0_MODEL := Talon AD7200\n\tDEVICE_ALT0_VARIANT := v1/v2\n\tSOC := qcom-ipq8064\n\tBLOCKSIZE := 128k\n\tPAGESIZE := 2048\n\tTPLINK_BOARD_ID := AD7200\n\tDEVICE_PACKAGES := ath10k-firmware-qca99x0-ct kmod-wil6210\nendef\nTARGET_DEVICES += tplink_ad7200\n\ndefine Device/tplink_c2600\n\t$(call Device/TpSafeImage)\n\tDEVICE_VENDOR := TP-Link\n\tDEVICE_MODEL := Archer C2600\n\tDEVICE_VARIANT := v1\n\tSOC := qcom-ipq8064\n\tBLOCKSIZE := 128k\n\tPAGESIZE := 2048\n\tBOARD_NAME := c2600\n\tSUPPORTED_DEVICES += c2600\n\tTPLINK_BOARD_ID := C2600\n\tDEVICE_PACKAGES := ath10k-firmware-qca99x0-ct\nendef\nTARGET_DEVICES += tplink_c2600\n\ndefine Device/tplink_vr2600v\n\tDEVICE_VENDOR := TP-Link\n\tDEVICE_MODEL := Archer VR2600v\n\tDEVICE_VARIANT := v1\n\tKERNEL_SUFFIX := -uImage\n\tKERNEL = kernel-bin | append-dtb | uImage none\n\tKERNEL_NAME := zImage\n\tIMAGE_SIZE := 12672k\n\tSOC := qcom-ipq8064\n\tBLOCKSIZE := 128k\n\tPAGESIZE := 2048\n\tBOARD_NAME := vr2600v\n\tSUPPORTED_DEVICES += vr2600v\n\tDEVICE_PACKAGES := ath10k-firmware-qca99x0-ct\n\tIMAGE/sysupgrade.bin := pad-extra 512 | append-kernel | \\\n\t\tappend-rootfs | pad-rootfs | append-metadata\nendef\nTARGET_DEVICES += tplink_vr2600v\n\ndefine Device/ubnt_unifi-ac-hd\n\t$(call Device/FitImageLzma)\n\tDEVICE_VENDOR := Ubiquiti\n\tDEVICE_MODEL := UniFi AC HD\n\tSOC := qcom-ipq8064\n\tBLOCKSIZE := 64k\n\tIMAGE_SIZE := 14784k\n\tDEVICE_PACKAGES := ath10k-firmware-qca9984-ct\n\tIMAGE/sysupgrade.bin := append-kernel | pad-to $$$$(BLOCKSIZE) | \\\n\t\tappend-rootfs | pad-rootfs | check-size | append-metadata\nendef\nTARGET_DEVICES += ubnt_unifi-ac-hd\n\ndefine Device/zyxel_nbg6817\n\tDEVICE_VENDOR := ZyXEL\n\tDEVICE_MODEL := NBG6817\n\tSOC := qcom-ipq8065\n\tKERNEL_SIZE := 4096k\n\tBLOCKSIZE := 64k\n\tBOARD_NAME := nbg6817\n\tRAS_BOARD := NBG6817\n\tRAS_ROOTFS_SIZE := 20934k\n\tRAS_VERSION := \"V1.99(OWRT.9999)C0\"\n\tSUPPORTED_DEVICES += nbg6817\n\tDEVICE_PACKAGES := ath10k-firmware-qca9984-ct e2fsprogs \\\n\t\tkmod-fs-ext4 losetup\n\t$(call Device/ZyXELImage)\nendef\nTARGET_DEVICES += zyxel_nbg6817\n"
  },
  {
    "path": "target/linux/ipq806x/modules.mk",
    "content": "define KernelPackage/phy-qcom-ipq806x-usb\n  TITLE:=Qualcomm IPQ806x DWC3 USB PHY driver\n  DEPENDS:=@TARGET_ipq806x\n  KCONFIG:= CONFIG_PHY_QCOM_IPQ806X_USB\n  FILES:= \\\n    $(LINUX_DIR)/drivers/phy/qualcomm/phy-qcom-ipq806x-usb.ko\n  AUTOLOAD:=$(call AutoLoad,45,phy-qcom-ipq806x-usb,1)\n  $(call AddDepends/usb)\nendef\n\ndefine KernelPackage/phy-qcom-ipq806x-usb/description\n This driver provides support for the integrated DesignWare\n USB3 IP Core within the QCOM SoCs.\nendef\n\n$(eval $(call KernelPackage,phy-qcom-ipq806x-usb))\n"
  },
  {
    "path": "target/linux/ipq806x/patches-5.10/0001-dtbindings-qcom_adm-Fix-channel-specifiers.patch",
    "content": "From 28d0ed88f536dd639adf1b0c7c08e04be3c8f294 Mon Sep 17 00:00:00 2001\nFrom: Thomas Pedersen <twp@codeaurora.org>\nDate: Mon, 16 May 2016 17:58:50 -0700\nSubject: [PATCH 01/69] dtbindings: qcom_adm: Fix channel specifiers\n\nOriginal patch from Andy Gross.\n\nThis patch removes the crci information from the dma\nchannel property.  At least one client device requires\nusing more than one CRCI value for a channel.  This does\nnot match the current binding and the crci information\nneeds to be removed.\n\nInstead, the client device will provide this information\nvia other means.\n\nSigned-off-by: Andy Gross <agross@codeaurora.org>\nSigned-off-by: Thomas Pedersen <twp@codeaurora.org>\n---\n Documentation/devicetree/bindings/dma/qcom_adm.txt | 16 ++++++----------\n 1 file changed, 6 insertions(+), 10 deletions(-)\n\n--- a/Documentation/devicetree/bindings/dma/qcom_adm.txt\n+++ b/Documentation/devicetree/bindings/dma/qcom_adm.txt\n@@ -4,8 +4,7 @@ Required properties:\n - compatible: must contain \"qcom,adm\" for IPQ/APQ8064 and MSM8960\n - reg: Address range for DMA registers\n - interrupts: Should contain one interrupt shared by all channels\n-- #dma-cells: must be <2>.  First cell denotes the channel number.  Second cell\n-  denotes CRCI (client rate control interface) flow control assignment.\n+- #dma-cells: must be <1>.  First cell denotes the channel number.\n - clocks: Should contain the core clock and interface clock.\n - clock-names: Must contain \"core\" for the core clock and \"iface\" for the\n   interface clock.\n@@ -22,7 +21,7 @@ Example:\n \t\t\tcompatible = \"qcom,adm\";\n \t\t\treg = <0x18300000 0x100000>;\n \t\t\tinterrupts = <0 170 0>;\n-\t\t\t#dma-cells = <2>;\n+\t\t\t#dma-cells = <1>;\n \n \t\t\tclocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>;\n \t\t\tclock-names = \"core\", \"iface\";\n@@ -35,15 +34,12 @@ Example:\n \t\t\tqcom,ee = <0>;\n \t\t};\n \n-DMA clients must use the format descripted in the dma.txt file, using a three\n+DMA clients must use the format descripted in the dma.txt file, using a two\n cell specifier for each channel.\n \n-Each dmas request consists of 3 cells:\n+Each dmas request consists of two cells:\n  1. phandle pointing to the DMA controller\n  2. channel number\n- 3. CRCI assignment, if applicable.  If no CRCI flow control is required, use 0.\n-    The CRCI is used for flow control.  It identifies the peripheral device that\n-    is the source/destination for the transferred data.\n \n Example:\n \n@@ -55,7 +51,7 @@ Example:\n \n \t\tcs-gpios = <&qcom_pinmux 20 0>;\n \n-\t\tdmas = <&adm_dma 6 9>,\n-\t\t\t<&adm_dma 5 10>;\n+\t\tdmas = <&adm_dma 6>,\n+\t\t\t<&adm_dma 5>;\n \t\tdma-names = \"rx\", \"tx\";\n \t};\n"
  },
  {
    "path": "target/linux/ipq806x/patches-5.10/0033-ARM-qcom-automatically-select-PCI_DOMAINS-if-PCI-is-.patch",
    "content": "From 48051ece78136e4235a2415a52797db56f8a4478 Mon Sep 17 00:00:00 2001\nFrom: Mathieu Olivari <mathieu@codeaurora.org>\nDate: Tue, 21 Apr 2015 19:09:07 -0700\nSubject: [PATCH 33/69] ARM: qcom: automatically select PCI_DOMAINS if PCI is\n enabled\n\nIf multiple PCIe devices are present in the system, the kernel will\npanic at boot time when trying to scan the PCI buses. This happens on\nIPQ806x based platforms, which has 3 PCIe ports.\n\nEnabling this option allows the kernel to assign the pci-domains\naccording to the device-tree content. This allows multiple PCIe\ncontrollers to coexist in the system.\n\nSigned-off-by: Mathieu Olivari <mathieu@codeaurora.org>\n---\n arch/arm/mach-qcom/Kconfig | 1 +\n 1 file changed, 1 insertion(+)\n\n--- a/arch/arm/mach-qcom/Kconfig\n+++ b/arch/arm/mach-qcom/Kconfig\n@@ -7,6 +7,7 @@ menuconfig ARCH_QCOM\n \tselect ARM_AMBA\n \tselect PINCTRL\n \tselect QCOM_SCM if SMP\n+\tselect PCI_DOMAINS if PCI\n \thelp\n \t  Support for Qualcomm's devicetree based systems.\n \n"
  },
  {
    "path": "target/linux/ipq806x/patches-5.10/0060-HACK-arch-arm-force-ZRELADDR-on-arch-qcom.patch",
    "content": "From fa71139b55e114aa8c3c4823ff8ee7d49ee810d4 Mon Sep 17 00:00:00 2001\nFrom: Mathieu Olivari <mathieu@codeaurora.org>\nDate: Wed, 29 Apr 2015 15:21:46 -0700\nSubject: [PATCH 60/69] HACK: arch: arm: force ZRELADDR on arch-qcom\n\nARCH_QCOM is using the ARCH_MULTIPLATFORM option, as now recommended\non most ARM architectures. This automatically calculate ZRELADDR by\nmasking PHYS_OFFSET with 0xf8000000.\n\nHowever, on IPQ806x, the first ~20MB of RAM is reserved for the hardware\nnetwork accelerators, and the bootloader removes this section from the\nlayout passed from the ATAGS (when used).\n\nFor newer bootloader, when DT is used, this is not a problem, we just\nreserve this memory in the device tree. But if the bootloader doesn't\nhave DT support, then ATAGS have to be used. In this case, the ARM\ndecompressor will position the kernel in this low mem, which will not be\nin the RAM section mapped by the bootloader, which means the kernel will\nfreeze in the middle of the boot process trying to map the memory.\n\nAs a work around, this patch allows disabling AUTO_ZRELADDR when\nARCH_QCOM is selected. It makes the zImage usage possible on bootloaders\nwhich don't support device-tree, which is the case on certain early\nIPQ806x based designs.\n\nSigned-off-by: Mathieu Olivari <mathieu@codeaurora.org>\n---\n arch/arm/Kconfig                 | 2 +-\n arch/arm/Makefile                | 2 ++\n arch/arm/mach-qcom/Makefile.boot | 1 +\n 3 files changed, 4 insertions(+), 1 deletion(-)\n create mode 100644 arch/arm/mach-qcom/Makefile.boot\n\n--- a/arch/arm/Kconfig\n+++ b/arch/arm/Kconfig\n@@ -322,7 +322,7 @@ config ARCH_MULTIPLATFORM\n \tselect ARCH_SELECT_MEMORY_MODEL\n \tselect ARM_HAS_SG_CHAIN\n \tselect ARM_PATCH_PHYS_VIRT\n-\tselect AUTO_ZRELADDR\n+\tselect AUTO_ZRELADDR if !ARCH_QCOM\n \tselect TIMER_OF\n \tselect COMMON_CLK\n \tselect GENERIC_CLOCKEVENTS\n--- a/arch/arm/Makefile\n+++ b/arch/arm/Makefile\n@@ -251,9 +251,11 @@ MACHINE  := arch/arm/mach-$(word 1,$(mac\n else\n MACHINE  :=\n endif\n+ifeq ($(CONFIG_ARCH_QCOM),)\n ifeq ($(CONFIG_ARCH_MULTIPLATFORM),y)\n MACHINE  :=\n endif\n+endif\n \n machdirs := $(patsubst %,arch/arm/mach-%/,$(machine-y))\n platdirs := $(patsubst %,arch/arm/plat-%/,$(sort $(plat-y)))\n--- /dev/null\n+++ b/arch/arm/mach-qcom/Makefile.boot\n@@ -0,0 +1 @@\n+zreladdr-y+= 0x42208000\n"
  },
  {
    "path": "target/linux/ipq806x/patches-5.10/0065-arm-override-compiler-flags.patch",
    "content": "From 4d8e29642661397a339ac3485f212c6360445421 Mon Sep 17 00:00:00 2001\nFrom: John Crispin <john@phrozen.org>\nDate: Thu, 9 Mar 2017 09:33:32 +0100\nSubject: [PATCH 65/69] arm: override compiler flags\n\nSigned-off-by: John Crispin <john@phrozen.org>\n---\n arch/arm/Makefile | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/arch/arm/Makefile\n+++ b/arch/arm/Makefile\n@@ -61,7 +61,7 @@ KBUILD_CFLAGS\t+= $(call cc-option,-fno-i\n # macro, but instead defines a whole series of macros which makes\n # testing for a specific architecture or later rather impossible.\n arch-$(CONFIG_CPU_32v7M)\t=-D__LINUX_ARM_ARCH__=7 -march=armv7-m\n-arch-$(CONFIG_CPU_32v7)\t\t=-D__LINUX_ARM_ARCH__=7 -march=armv7-a\n+arch-$(CONFIG_CPU_32v7)\t\t=-D__LINUX_ARM_ARCH__=7 -mcpu=cortex-a15\n arch-$(CONFIG_CPU_32v6)\t\t=-D__LINUX_ARM_ARCH__=6 -march=armv6\n # Only override the compiler option if ARMv6. The ARMv6K extensions are\n # always available in ARMv7\n"
  },
  {
    "path": "target/linux/ipq806x/patches-5.10/0067-generic-Mangle-bootloader-s-kernel-arguments.patch",
    "content": "From 71270226b14733a4b1f2cde58ea9265caa50b38d Mon Sep 17 00:00:00 2001\nFrom: Adrian Panella <ianchi74@outlook.com>\nDate: Thu, 9 Mar 2017 09:37:17 +0100\nSubject: [PATCH 67/69] generic: Mangle bootloader's kernel arguments\n\nThe command-line arguments provided by the boot loader will be\nappended to a new device tree property: bootloader-args.\nIf there is a property \"append-rootblock\" in DT under /chosen\nand a root= option in bootloaders command line it will be parsed\nand added to DT bootargs with the form: <append-rootblock>XX.\nOnly command line ATAG will be processed, the rest of the ATAGs\nsent by bootloader will be ignored.\nThis is usefull in dual boot systems, to get the current root partition\nwithout afecting the rest of the system.\n\nSigned-off-by: Adrian Panella <ianchi74@outlook.com>\n---\n arch/arm/Kconfig                        | 11 +++++\n arch/arm/boot/compressed/atags_to_fdt.c | 72 ++++++++++++++++++++++++++++++++-\n init/main.c                             | 16 ++++++++\n 3 files changed, 98 insertions(+), 1 deletion(-)\n\n--- a/arch/arm/Kconfig\n+++ b/arch/arm/Kconfig\n@@ -1781,6 +1781,17 @@ config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEN\n \t  The command-line arguments provided by the boot loader will be\n \t  appended to the the device tree bootargs property.\n \n+config ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE\n+\tbool \"Append rootblock parsing bootloader's kernel arguments\"\n+\thelp\n+\t  The command-line arguments provided by the boot loader will be\n+\t  appended to a new device tree property: bootloader-args.\n+\t  If there is a property \"append-rootblock\" in DT under /chosen\n+\t  and a root= option in bootloaders command line it will be parsed\n+\t  and added to DT bootargs with the form: <append-rootblock>XX.\n+\t  Only command line ATAG will be processed, the rest of the ATAGs\n+\t  sent by bootloader will be ignored.\n+\n endchoice\n \n config CMDLINE\n--- a/arch/arm/boot/compressed/atags_to_fdt.c\n+++ b/arch/arm/boot/compressed/atags_to_fdt.c\n@@ -5,6 +5,8 @@\n \n #if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND)\n #define do_extend_cmdline 1\n+#elif defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)\n+#define do_extend_cmdline 1\n #else\n #define do_extend_cmdline 0\n #endif\n@@ -69,6 +71,80 @@ static uint32_t get_cell_size(const void\n \treturn cell_size;\n }\n \n+#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)\n+/**\n+ * taken from arch/x86/boot/string.c\n+ * local_strstr - Find the first substring in a %NUL terminated string\n+ * @s1: The string to be searched\n+ * @s2: The string to search for\n+ */\n+static char *local_strstr(const char *s1, const char *s2)\n+{\n+\tsize_t l1, l2;\n+\n+\tl2 = strlen(s2);\n+\tif (!l2)\n+\t\treturn (char *)s1;\n+\tl1 = strlen(s1);\n+\twhile (l1 >= l2) {\n+\t\tl1--;\n+\t\tif (!memcmp(s1, s2, l2))\n+\t\t\treturn (char *)s1;\n+\t\ts1++;\n+\t}\n+\treturn NULL;\n+}\n+\n+static char *append_rootblock(char *dest, const char *str, int len, void *fdt)\n+{\n+\tchar *ptr, *end, *tmp;\n+\tchar *root=\"root=\";\n+\tchar *find_rootblock;\n+\tint i, l;\n+\tconst char *rootblock;\n+\n+\tfind_rootblock = getprop(fdt, \"/chosen\", \"find-rootblock\", &l);\n+\tif(!find_rootblock)\n+\t\tfind_rootblock = root;\n+\n+\t//ARM doesn't have __HAVE_ARCH_STRSTR, so it was copied from x86\n+\tptr = local_strstr(str, find_rootblock);\n+\n+\tif(!ptr)\n+\t\treturn dest;\n+\n+\tend = strchr(ptr, ' ');\n+\tend = end ? (end - 1) : (strchr(ptr, 0) - 1);\n+\n+\t// Some boards ubi.mtd=XX,ZZZZ, so let's check for ',\" too.\n+\ttmp = strchr(ptr, ',');\n+\n+\tif(tmp)\n+\t\tend = end < tmp ? end : tmp - 1;\n+\n+\t//find partition number (assumes format root=/dev/mtdXX | /dev/mtdblockXX | yy:XX | ubi.mtd=XX,ZZZZ )\n+\tfor( i = 0; end >= ptr && *end >= '0' && *end <= '9'; end--, i++);\n+\tptr = end + 1;\n+\n+\t/* if append-rootblock property is set use it to append to command line */\n+\trootblock = getprop(fdt, \"/chosen\", \"append-rootblock\", &l);\n+\tif(rootblock != NULL) {\n+\t\tif(*dest != ' ') {\n+\t\t\t*dest = ' ';\n+\t\t\tdest++;\n+\t\t\tlen++;\n+\t\t}\n+\t\tif (len + l + i <= COMMAND_LINE_SIZE) {\n+\t\t\tmemcpy(dest, rootblock, l);\n+\t\t\tdest += l - 1;\n+\t\t\tmemcpy(dest, ptr, i);\n+\t\t\tdest += i;\n+\t\t}\n+\t}\n+\treturn dest;\n+}\n+#endif\n+\n static void merge_fdt_bootargs(void *fdt, const char *fdt_cmdline)\n {\n \tchar cmdline[COMMAND_LINE_SIZE];\n@@ -88,12 +164,21 @@ static void merge_fdt_bootargs(void *fdt\n \n \t/* and append the ATAG_CMDLINE */\n \tif (fdt_cmdline) {\n+\n+#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)\n+\t\t//save original bootloader args\n+\t\t//and append ubi.mtd with root partition number to current cmdline\n+\t\tsetprop_string(fdt, \"/chosen\", \"bootloader-args\", fdt_cmdline);\n+\t\tptr = append_rootblock(ptr, fdt_cmdline, len, fdt);\n+\n+#else\n \t\tlen = strlen(fdt_cmdline);\n \t\tif (ptr - cmdline + len + 2 < COMMAND_LINE_SIZE) {\n \t\t\t*ptr++ = ' ';\n \t\t\tmemcpy(ptr, fdt_cmdline, len);\n \t\t\tptr += len;\n \t\t}\n+#endif\n \t}\n \t*ptr = '\\0';\n \n@@ -168,7 +253,9 @@ int atags_to_fdt(void *atag_list, void *\n \t\t\telse\n \t\t\t\tsetprop_string(fdt, \"/chosen\", \"bootargs\",\n \t\t\t\t\t       atag->u.cmdline.cmdline);\n-\t\t} else if (atag->hdr.tag == ATAG_MEM) {\n+\t\t}\n+#ifndef CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE\n+\t\telse if (atag->hdr.tag == ATAG_MEM) {\n \t\t\tif (memcount >= sizeof(mem_reg_property)/4)\n \t\t\t\tcontinue;\n \t\t\tif (!atag->u.mem.size)\n@@ -212,6 +299,10 @@ int atags_to_fdt(void *atag_list, void *\n \t\tsetprop(fdt, \"/memory\", \"reg\", mem_reg_property,\n \t\t\t4 * memcount * memsize);\n \t}\n+#else\n+\n+\t}\n+#endif\n \n \treturn fdt_pack(fdt);\n }\n--- a/init/main.c\n+++ b/init/main.c\n@@ -110,6 +110,10 @@\n \n #include <kunit/test.h>\n \n+#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)\n+#include <linux/of.h>\n+#endif\n+\n static int kernel_init(void *);\n \n extern void init_IRQ(void);\n@@ -906,6 +910,18 @@ asmlinkage __visible void __init __no_sa\n \tpr_notice(\"Kernel command line: %s\\n\", saved_command_line);\n \t/* parameters may set static keys */\n \tjump_label_init();\n+\n+#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)\n+\t//Show bootloader's original command line for reference\n+\tif(of_chosen) {\n+\t\tconst char *prop = of_get_property(of_chosen, \"bootloader-args\", NULL);\n+\t\tif(prop)\n+\t\t\tpr_notice(\"Bootloader command line (ignored): %s\\n\", prop);\n+\t\telse\n+\t\t\tpr_notice(\"Bootloader command line not present\\n\");\n+\t}\n+#endif\n+\n \tparse_early_param();\n \tafter_dashes = parse_args(\"Booting kernel\",\n \t\t\t\t  static_command_line, __start___param,\n"
  },
  {
    "path": "target/linux/ipq806x/patches-5.10/0069-arm-boot-add-dts-files.patch",
    "content": "From 8f68331e14dff9a101f2d0e1d6bec84a031f27ee Mon Sep 17 00:00:00 2001\nFrom: John Crispin <john@phrozen.org>\nDate: Thu, 9 Mar 2017 11:03:18 +0100\nSubject: [PATCH 69/69] arm: boot: add dts files\n\nSigned-off-by: John Crispin <john@phrozen.org>\n---\n arch/arm/boot/dts/Makefile | 8 ++++++++\n 1 file changed, 8 insertions(+)\n\n--- a/arch/arm/boot/dts/Makefile\n+++ b/arch/arm/boot/dts/Makefile\n@@ -908,8 +908,30 @@ dtb-$(CONFIG_ARCH_QCOM) += \\\n \tqcom-ipq4019-ap.dk04.1-c3.dtb \\\n \tqcom-ipq4019-ap.dk07.1-c1.dtb \\\n \tqcom-ipq4019-ap.dk07.1-c2.dtb \\\n+\tqcom-ipq8062-wg2600hp3.dtb \\\n \tqcom-ipq8064-ap148.dtb \\\n \tqcom-ipq8064-rb3011.dtb \\\n+\tqcom-ipq8064-c2600.dtb \\\n+\tqcom-ipq8064-d7800.dtb \\\n+\tqcom-ipq8064-db149.dtb \\\n+\tqcom-ipq8064-ap161.dtb \\\n+\tqcom-ipq8064-ea7500-v1.dtb \\\n+\tqcom-ipq8064-ea8500.dtb \\\n+\tqcom-ipq8064-g10.dtb \\\n+\tqcom-ipq8064-r7500.dtb \\\n+\tqcom-ipq8064-r7500v2.dtb \\\n+\tqcom-ipq8064-unifi-ac-hd.dtb \\\n+\tqcom-ipq8064-wg2600hp.dtb \\\n+\tqcom-ipq8064-wpq864.dtb \\\n+\tqcom-ipq8064-wxr-2533dhp.dtb \\\n+\tqcom-ipq8065-nbg6817.dtb \\\n+\tqcom-ipq8065-r7800.dtb \\\n+\tqcom-ipq8065-rt4230w-rev6.dtb \\\n+\tqcom-ipq8065-tr4400-v2.dtb \\\n+\tqcom-ipq8065-xr500.dtb \\\n+\tqcom-ipq8068-ecw5410.dtb \\\n+\tqcom-ipq8068-mr42.dtb \\\n+\tqcom-ipq8068-mr52.dtb \\\n \tqcom-msm8660-surf.dtb \\\n \tqcom-msm8960-cdp.dtb \\\n \tqcom-msm8974-fairphone-fp2.dtb \\\n"
  },
  {
    "path": "target/linux/ipq806x/patches-5.10/0072-add-ipq806x-with-no-clocks.patch",
    "content": "--- a/drivers/firmware/qcom_scm.c\n+++ b/drivers/firmware/qcom_scm.c\n@@ -1269,6 +1269,7 @@ static const struct of_device_id qcom_sc\n \t\t\t\t\t\t\t     SCM_HAS_BUS_CLK)\n \t},\n \t{ .compatible = \"qcom,scm-ipq4019\" },\n+\t{ .compatible = \"qcom,scm-ipq806x\" },\n \t{ .compatible = \"qcom,scm-msm8660\", .data = (void *) SCM_HAS_CORE_CLK },\n \t{ .compatible = \"qcom,scm-msm8960\", .data = (void *) SCM_HAS_CORE_CLK },\n \t{ .compatible = \"qcom,scm-msm8916\", .data = (void *)(SCM_HAS_CORE_CLK |\n"
  },
  {
    "path": "target/linux/ipq806x/patches-5.10/082-ipq8064-dtsi-tweaks.patch",
    "content": "--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi\n+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi\n@@ -20,7 +20,7 @@\n \t\t#address-cells = <1>;\n \t\t#size-cells = <0>;\n \n-\t\tcpu@0 {\n+\t\tcpu0: cpu@0 {\n \t\t\tcompatible = \"qcom,krait\";\n \t\t\tenable-method = \"qcom,kpss-acc-v1\";\n \t\t\tdevice_type = \"cpu\";\n@@ -30,7 +30,7 @@\n \t\t\tqcom,saw = <&saw0>;\n \t\t};\n \n-\t\tcpu@1 {\n+\t\tcpu1: cpu@1 {\n \t\t\tcompatible = \"qcom,krait\";\n \t\t\tenable-method = \"qcom,kpss-acc-v1\";\n \t\t\tdevice_type = \"cpu\";\n@@ -67,7 +67,7 @@\n \t\t\tno-map;\n \t\t};\n \n-\t\tsmem@41000000 {\n+\t\tsmem: smem@41000000 {\n \t\t\treg = <0x41000000 0x200000>;\n \t\t\tno-map;\n \t\t};\n@@ -128,6 +128,7 @@\n \t\t\tgpio-ranges = <&qcom_pinmux 0 0 69>;\n \t\t\t#gpio-cells = <2>;\n \t\t\tinterrupt-controller;\n+\t\t\t#address-cells = <0>;\n \t\t\t#interrupt-cells = <2>;\n \t\t\tinterrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;\n \n@@ -155,6 +156,7 @@\n \t\t\t\t\tfunction = \"pcie3_rst\";\n \t\t\t\t\tdrive-strength = <12>;\n \t\t\t\t\tbias-disable;\n+\t\t\t\t\toutput-low;\n \t\t\t\t};\n \t\t\t};\n \n@@ -190,6 +192,7 @@\n \t\tintc: interrupt-controller@2000000 {\n \t\t\tcompatible = \"qcom,msm-qgic2\";\n \t\t\tinterrupt-controller;\n+\t\t\t#address-cells = <0>;\n \t\t\t#interrupt-cells = <3>;\n \t\t\treg = <0x02000000 0x1000>,\n \t\t\t      <0x02002000 0x1000>;\n@@ -219,21 +222,23 @@\n \t\tacc0: clock-controller@2088000 {\n \t\t\tcompatible = \"qcom,kpss-acc-v1\";\n \t\t\treg = <0x02088000 0x1000>, <0x02008000 0x1000>;\n+\t\t\tclock-output-names = \"acpu0_aux\";\n \t\t};\n \n \t\tacc1: clock-controller@2098000 {\n \t\t\tcompatible = \"qcom,kpss-acc-v1\";\n \t\t\treg = <0x02098000 0x1000>, <0x02008000 0x1000>;\n+\t\t\tclock-output-names = \"acpu1_aux\";\n \t\t};\n \n \t\tsaw0: regulator@2089000 {\n-\t\t\tcompatible = \"qcom,saw2\";\n+\t\t\tcompatible = \"qcom,saw2\", \"qcom,apq8064-saw2-v1.1-cpu\", \"syscon\";\n \t\t\treg = <0x02089000 0x1000>, <0x02009000 0x1000>;\n \t\t\tregulator;\n \t\t};\n \n \t\tsaw1: regulator@2099000 {\n-\t\t\tcompatible = \"qcom,saw2\";\n+\t\t\tcompatible = \"qcom,saw2\", \"qcom,apq8064-saw2-v1.1-cpu\", \"syscon\";\n \t\t\treg = <0x02099000 0x1000>, <0x02009000 0x1000>;\n \t\t\tregulator;\n \t\t};\n@@ -251,7 +256,7 @@\n \n \t\t\tsyscon-tcsr = <&tcsr>;\n \n-\t\t\tserial@12490000 {\n+\t\t\tgsbi2_serial: serial@12490000 {\n \t\t\t\tcompatible = \"qcom,msm-uartdm-v1.3\", \"qcom,msm-uartdm\";\n \t\t\t\treg = <0x12490000 0x1000>,\n \t\t\t\t      <0x12480000 0x1000>;\n@@ -261,7 +266,7 @@\n \t\t\t\tstatus = \"disabled\";\n \t\t\t};\n \n-\t\t\ti2c@124a0000 {\n+\t\t\tgsbi2_i2c: i2c@124a0000 {\n \t\t\t\tcompatible = \"qcom,i2c-qup-v1.1.1\";\n \t\t\t\treg = <0x124a0000 0x1000>;\n \t\t\t\tinterrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;\n@@ -326,7 +331,7 @@\n \n \t\t\tsyscon-tcsr = <&tcsr>;\n \n-\t\t\tserial@1a240000 {\n+\t\t\tgsbi5_serial: serial@1a240000 {\n \t\t\t\tcompatible = \"qcom,msm-uartdm-v1.3\", \"qcom,msm-uartdm\";\n \t\t\t\treg = <0x1a240000 0x1000>,\n \t\t\t\t      <0x1a200000 0x1000>;\n@@ -397,7 +402,7 @@\n \t\t\tstatus = \"disabled\";\n \t\t};\n \n-\t\tsata@29000000 {\n+\t\tsata: sata@29000000 {\n \t\t\tcompatible = \"qcom,ipq806x-ahci\", \"generic-ahci\";\n \t\t\treg = <0x29000000 0x180>;\n \n@@ -430,13 +435,35 @@\n \t\t\treg = <0x00700000 0x1000>;\n \t\t\t#address-cells = <1>;\n \t\t\t#size-cells = <1>;\n+\n+\t\t\ttsens_calib: calib@400 {\n+\t\t\t\treg = <0x400 0xb>;\n+\t\t\t};\n+\t\t\ttsens_backup: backup@410 {\n+\t\t\t\treg = <0x410 0xb>;\n+\t\t\t};\n+\t\t\tspeedbin_efuse: speedbin@0c0 {\n+\t\t\t\treg = <0x0c0 0x4>;\n+\t\t\t};\n \t\t};\n \n \t\tgcc: clock-controller@900000 {\n-\t\t\tcompatible = \"qcom,gcc-ipq8064\";\n+\t\t\tcompatible = \"qcom,gcc-ipq8064\", \"syscon\";\n \t\t\treg = <0x00900000 0x4000>;\n \t\t\t#clock-cells = <1>;\n \t\t\t#reset-cells = <1>;\n+\t\t\t#power-domain-cells = <1>;\n+\n+\t\t\ttsens: thermal-sensor@900000 {\n+\t\t\t\tcompatible = \"qcom,ipq8064-tsens\";\n+\n+\t\t\t\tnvmem-cells = <&tsens_calib>, <&tsens_backup>;\n+\t\t\t\tnvmem-cell-names = \"calib\", \"calib_backup\";\n+\t\t\t\tinterrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\t\tinterrupt-names = \"uplow\";\n+\t\t\t\t#thermal-sensor-cells = <1>;\n+\t\t\t\t#qcom,sensors = <11>;\n+\t\t\t};\n \t\t};\n \n \t\ttcsr: syscon@1a400000 {\n@@ -622,7 +649,7 @@\n \n \t\tgmac0: ethernet@37000000 {\n \t\t\tdevice_type = \"network\";\n-\t\t\tcompatible = \"qcom,ipq806x-gmac\";\n+\t\t\tcompatible = \"qcom,ipq806x-gmac\", \"snps,dwmac\";\n \t\t\treg = <0x37000000 0x200000>;\n \t\t\tinterrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;\n \t\t\tinterrupt-names = \"macirq\";\n@@ -645,7 +672,7 @@\n \n \t\tgmac1: ethernet@37200000 {\n \t\t\tdevice_type = \"network\";\n-\t\t\tcompatible = \"qcom,ipq806x-gmac\";\n+\t\t\tcompatible = \"qcom,ipq806x-gmac\", \"snps,dwmac\";\n \t\t\treg = <0x37200000 0x200000>;\n \t\t\tinterrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;\n \t\t\tinterrupt-names = \"macirq\";\n@@ -668,7 +695,7 @@\n \n \t\tgmac2: ethernet@37400000 {\n \t\t\tdevice_type = \"network\";\n-\t\t\tcompatible = \"qcom,ipq806x-gmac\";\n+\t\t\tcompatible = \"qcom,ipq806x-gmac\", \"snps,dwmac\";\n \t\t\treg = <0x37400000 0x200000>;\n \t\t\tinterrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;\n \t\t\tinterrupt-names = \"macirq\";\n@@ -691,7 +718,7 @@\n \n \t\tgmac3: ethernet@37600000 {\n \t\t\tdevice_type = \"network\";\n-\t\t\tcompatible = \"qcom,ipq806x-gmac\";\n+\t\t\tcompatible = \"qcom,ipq806x-gmac\", \"snps,dwmac\";\n \t\t\treg = <0x37600000 0x200000>;\n \t\t\tinterrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;\n \t\t\tinterrupt-names = \"macirq\";\n@@ -740,13 +767,13 @@\n \t\t\tqcom,ee = <0>;\n \t\t};\n \n-\t\tamba {\n-\t\t\tcompatible = \"simple-bus\";\n+\t\tamba: amba {\n+\t\t\tcompatible = \"arm,amba-bus\";\n \t\t\t#address-cells = <1>;\n \t\t\t#size-cells = <1>;\n \t\t\tranges;\n \n-\t\t\tsdcc@12400000 {\n+\t\t\tsdcc1: sdcc@12400000 {\n \t\t\t\tstatus          = \"disabled\";\n \t\t\t\tcompatible      = \"arm,pl18x\", \"arm,primecell\";\n \t\t\t\tarm,primecell-periphid = <0x00051180>;\n@@ -760,13 +787,12 @@\n \t\t\t\tnon-removable;\n \t\t\t\tcap-sd-highspeed;\n \t\t\t\tcap-mmc-highspeed;\n-\t\t\t\tmmc-ddr-1_8v;\n \t\t\t\tvmmc-supply = <&vsdcc_fixed>;\n \t\t\t\tdmas = <&sdcc1bam 2>, <&sdcc1bam 1>;\n \t\t\t\tdma-names = \"tx\", \"rx\";\n \t\t\t};\n \n-\t\t\tsdcc@12180000 {\n+\t\t\tsdcc3: sdcc@12180000 {\n \t\t\t\tcompatible      = \"arm,pl18x\", \"arm,primecell\";\n \t\t\t\tarm,primecell-periphid = <0x00051180>;\n \t\t\t\tstatus          = \"disabled\";\n"
  },
  {
    "path": "target/linux/ipq806x/patches-5.10/083-ipq8064-dtsi-additions.patch",
    "content": "--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi\n+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi\n@@ -8,6 +8,8 @@\n #include <dt-bindings/reset/qcom,gcc-ipq806x.h>\n #include <dt-bindings/soc/qcom,gsbi.h>\n #include <dt-bindings/interrupt-controller/arm-gic.h>\n+#include <dt-bindings/mfd/qcom-rpm.h>\n+#include <dt-bindings/clock/qcom,rpmcc.h>\n \n / {\n \t#address-cells = <1>;\n@@ -28,6 +30,16 @@\n \t\t\tnext-level-cache = <&L2>;\n \t\t\tqcom,acc = <&acc0>;\n \t\t\tqcom,saw = <&saw0>;\n+\t\t\tclocks = <&kraitcc 0>, <&kraitcc 4>;\n+\t\t\tclock-names = \"cpu\", \"l2\";\n+\t\t\tclock-latency = <100000>;\n+\t\t\tcpu-supply = <&smb208_s2a>;\n+\t\t\toperating-points-v2 = <&opp_table0>;\n+\t\t\tvoltage-tolerance = <5>;\n+\t\t\tcooling-min-state = <0>;\n+\t\t\tcooling-max-state = <10>;\n+\t\t\t#cooling-cells = <2>;\n+\t\t\tcpu-idle-states = <&CPU_SPC>;\n \t\t};\n \n \t\tcpu1: cpu@1 {\n@@ -38,14 +50,350 @@\n \t\t\tnext-level-cache = <&L2>;\n \t\t\tqcom,acc = <&acc1>;\n \t\t\tqcom,saw = <&saw1>;\n+\t\t\tclocks = <&kraitcc 1>, <&kraitcc 4>;\n+\t\t\tclock-names = \"cpu\", \"l2\";\n+\t\t\tclock-latency = <100000>;\n+\t\t\tcpu-supply = <&smb208_s2b>;\n+\t\t\toperating-points-v2 = <&opp_table0>;\n+\t\t\tvoltage-tolerance = <5>;\n+\t\t\tcooling-min-state = <0>;\n+\t\t\tcooling-max-state = <10>;\n+\t\t\t#cooling-cells = <2>;\n+\t\t\tcpu-idle-states = <&CPU_SPC>;\n+ \t\t};\n+\n+\t\tidle-states {\n+\t\t\tCPU_SPC: spc {\n+\t\t\t\tcompatible = \"qcom,idle-state-spc\";\n+\t\t\t\tstatus = \"disabled\";\n+\t\t\t\tentry-latency-us = <400>;\n+\t\t\t\texit-latency-us = <900>;\n+\t\t\t\tmin-residency-us = <3000>;\n+\t\t\t};\n \t\t};\n+\t};\n \n-\t\tL2: l2-cache {\n-\t\t\tcompatible = \"cache\";\n-\t\t\tcache-level = <2>;\n+\topp_table_l2: opp_table_l2 {\n+\t\tcompatible = \"operating-points-v2\";\n+\n+\t\topp-384000000 {\n+\t\t\topp-hz = /bits/ 64 <384000000>;\n+\t\t\topp-microvolt = <1100000>;\n+\t\t\tclock-latency-ns = <100000>;\n+\t\t\topp-level = <0>;\n+\t\t};\n+\n+\t\topp-1000000000 {\n+\t\t\topp-hz = /bits/ 64 <1000000000>;\n+\t\t\topp-microvolt = <1100000>;\n+\t\t\tclock-latency-ns = <100000>;\n+\t\t\topp-level = <1>;\n+\t\t};\n+\n+\t\topp-1200000000 {\n+\t\t\topp-hz = /bits/ 64 <1200000000>;\n+\t\t\topp-microvolt = <1150000>;\n+\t\t\tclock-latency-ns = <100000>;\n+\t\t\topp-level = <2>;\n+\t\t};\n+\t};\n+\n+\topp_table0: opp_table0 {\n+\t\tcompatible = \"operating-points-v2-kryo-cpu\";\n+\t\tnvmem-cells = <&speedbin_efuse>;\n+\n+\t\t/*\n+\t\t * Voltage thresholds are <target min max>\n+\t\t */\n+\t\topp-384000000 {\n+\t\t\topp-hz = /bits/ 64 <384000000>;\n+\t\t\topp-microvolt-speed0-pvs0-v0 = <1000000 950000 1050000>;\n+\t\t\topp-microvolt-speed0-pvs1-v0 = <925000 878750 971250>;\n+\t\t\topp-microvolt-speed0-pvs2-v0 = <875000 831250 918750>;\n+\t\t\topp-microvolt-speed0-pvs3-v0 = <800000 760000 840000>;\n+\t\t\topp-supported-hw = <0x1>;\n+\t\t\tclock-latency-ns = <100000>;\n+\t\t\topp-level = <0>;\n+\t\t};\n+\n+\t\topp-600000000 {\n+\t\t\topp-hz = /bits/ 64 <600000000>;\n+\t\t\topp-microvolt-speed0-pvs0-v0 = <1050000 997500 1102500>;\n+\t\t\topp-microvolt-speed0-pvs1-v0 = <975000 926250 1023750>;\n+\t\t\topp-microvolt-speed0-pvs2-v0 = <925000 878750 971250>;\n+\t\t\topp-microvolt-speed0-pvs3-v0 = <850000 807500 892500>;\n+\t\t\topp-supported-hw = <0x1>;\n+\t\t\tclock-latency-ns = <100000>;\n+\t\t\topp-level = <1>;\n+\t\t};\n+\n+\t\topp-800000000 {\n+\t\t\topp-hz = /bits/ 64 <800000000>;\n+\t\t\topp-microvolt-speed0-pvs0-v0 = <1100000 1045000 1155000>;\n+\t\t\topp-microvolt-speed0-pvs1-v0 = <1025000 973750 1076250>;\n+\t\t\topp-microvolt-speed0-pvs2-v0 = <995000 945250 1044750>;\n+\t\t\topp-microvolt-speed0-pvs3-v0 = <900000 855000 945000>;\n+\t\t\topp-supported-hw = <0x1>;\n+\t\t\tclock-latency-ns = <100000>;\n+\t\t\topp-level = <1>;\n+\t\t};\n+\n+\t\topp-1000000000 {\n+\t\t\topp-hz = /bits/ 64 <1000000000>;\n+\t\t\topp-microvolt-speed0-pvs0-v0 = <1150000 1092500 1207500>;\n+\t\t\topp-microvolt-speed0-pvs1-v0 = <1075000 1021250 1128750>;\n+\t\t\topp-microvolt-speed0-pvs2-v0 = <1025000 973750 1076250>;\n+\t\t\topp-microvolt-speed0-pvs3-v0 = <950000 902500 997500>;\n+\t\t\topp-supported-hw = <0x1>;\n+\t\t\tclock-latency-ns = <100000>;\n+\t\t\topp-level = <1>;\n+\t\t};\n+\n+\t\topp-1200000000 {\n+\t\t\topp-hz = /bits/ 64 <1200000000>;\n+\t\t\topp-microvolt-speed0-pvs0-v0 = <1200000 1140000 1260000>;\n+\t\t\topp-microvolt-speed0-pvs1-v0 = <1125000 1068750 1181250>;\n+\t\t\topp-microvolt-speed0-pvs2-v0 = <1075000 1021250 1128750>;\n+\t\t\topp-microvolt-speed0-pvs3-v0 = <1000000 950000 1050000>;\n+\t\t\topp-supported-hw = <0x1>;\n+\t\t\tclock-latency-ns = <100000>;\n+\t\t\topp-level = <2>;\n+\t\t};\n+\n+\t\topp-1400000000 {\n+\t\t\topp-hz = /bits/ 64 <1400000000>;\n+\t\t\topp-microvolt-speed0-pvs0-v0 = <1250000 1187500 1312500>;\n+\t\t\topp-microvolt-speed0-pvs1-v0 = <1175000 1116250 1233750>;\n+\t\t\topp-microvolt-speed0-pvs2-v0 = <1125000 1068750 1181250>;\n+\t\t\topp-microvolt-speed0-pvs3-v0 = <1050000 997500 1102500>;\n+\t\t\topp-supported-hw = <0x1>;\n+\t\t\tclock-latency-ns = <100000>;\n+\t\t\topp-level = <2>;\n \t\t};\n \t};\n \n+\tthermal-zones {\n+\t\ttsens_tz_sensor0 {\n+\t\t\tpolling-delay-passive = <0>;\n+\t\t\tpolling-delay = <0>;\n+\t\t\tthermal-sensors = <&tsens 0>;\n+\n+\t\t\ttrips {\n+\t\t\t\tcpu-critical {\n+\t\t\t\t\ttemperature = <105000>;\n+\t\t\t\t\thysteresis = <2000>;\n+\t\t\t\t\ttype = \"critical\";\n+\t\t\t\t};\n+\n+\t\t\t\tcpu-hot {\n+\t\t\t\t\ttemperature = <95000>;\n+\t\t\t\t\thysteresis = <2000>;\n+\t\t\t\t\ttype = \"hot\";\n+\t\t\t\t};\n+\t\t\t};\n+\t\t};\n+\n+\t\ttsens_tz_sensor1 {\n+\t\t\tpolling-delay-passive = <0>;\n+\t\t\tpolling-delay = <0>;\n+\t\t\tthermal-sensors = <&tsens 1>;\n+\n+\t\t\ttrips {\n+\t\t\t\tcpu-critical {\n+\t\t\t\t\ttemperature = <105000>;\n+\t\t\t\t\thysteresis = <2000>;\n+\t\t\t\t\ttype = \"critical\";\n+\t\t\t\t};\n+\n+\t\t\t\tcpu-hot {\n+\t\t\t\t\ttemperature = <95000>;\n+\t\t\t\t\thysteresis = <2000>;\n+\t\t\t\t\ttype = \"hot\";\n+\t\t\t\t};\n+\t\t\t};\n+\t\t};\n+\n+\t\ttsens_tz_sensor2 {\n+\t\t\tpolling-delay-passive = <0>;\n+\t\t\tpolling-delay = <0>;\n+\t\t\tthermal-sensors = <&tsens 2>;\n+\n+\t\t\ttrips {\n+\t\t\t\tcpu-critical {\n+\t\t\t\t\ttemperature = <105000>;\n+\t\t\t\t\thysteresis = <2000>;\n+\t\t\t\t\ttype = \"critical\";\n+\t\t\t\t};\n+\n+\t\t\t\tcpu-hot {\n+\t\t\t\t\ttemperature = <95000>;\n+\t\t\t\t\thysteresis = <2000>;\n+\t\t\t\t\ttype = \"hot\";\n+\t\t\t\t};\n+\t\t\t};\n+\t\t};\n+\n+\t\ttsens_tz_sensor3 {\n+\t\t\tpolling-delay-passive = <0>;\n+\t\t\tpolling-delay = <0>;\n+\t\t\tthermal-sensors = <&tsens 3>;\n+\n+\t\t\ttrips {\n+\t\t\t\tcpu-critical {\n+\t\t\t\t\ttemperature = <105000>;\n+\t\t\t\t\thysteresis = <2000>;\n+\t\t\t\t\ttype = \"critical\";\n+\t\t\t\t};\n+\n+\t\t\t\tcpu-hot {\n+\t\t\t\t\ttemperature = <95000>;\n+\t\t\t\t\thysteresis = <2000>;\n+\t\t\t\t\ttype = \"hot\";\n+\t\t\t\t};\n+\t\t\t};\n+\t\t};\n+\n+\t\ttsens_tz_sensor4 {\n+\t\t\tpolling-delay-passive = <0>;\n+\t\t\tpolling-delay = <0>;\n+\t\t\tthermal-sensors = <&tsens 4>;\n+\n+\t\t\ttrips {\n+\t\t\t\tcpu-critical {\n+\t\t\t\t\ttemperature = <105000>;\n+\t\t\t\t\thysteresis = <2000>;\n+\t\t\t\t\ttype = \"critical\";\n+\t\t\t\t};\n+\n+\t\t\t\tcpu-hot {\n+\t\t\t\t\ttemperature = <95000>;\n+\t\t\t\t\thysteresis = <2000>;\n+\t\t\t\t\ttype = \"hot\";\n+\t\t\t\t};\n+\t\t\t};\n+\t\t};\n+\n+\t\ttsens_tz_sensor5 {\n+\t\t\tpolling-delay-passive = <0>;\n+\t\t\tpolling-delay = <0>;\n+\t\t\tthermal-sensors = <&tsens 5>;\n+\n+\t\t\ttrips {\n+\t\t\t\tcpu-critical {\n+\t\t\t\t\ttemperature = <105000>;\n+\t\t\t\t\thysteresis = <2000>;\n+\t\t\t\t\ttype = \"critical\";\n+\t\t\t\t};\n+\n+\t\t\t\tcpu-hot {\n+\t\t\t\t\ttemperature = <95000>;\n+\t\t\t\t\thysteresis = <2000>;\n+\t\t\t\t\ttype = \"hot\";\n+\t\t\t\t};\n+\t\t\t};\n+\t\t};\n+\n+\t\ttsens_tz_sensor6 {\n+\t\t\tpolling-delay-passive = <0>;\n+\t\t\tpolling-delay = <0>;\n+\t\t\tthermal-sensors = <&tsens 6>;\n+\n+\t\t\ttrips {\n+\t\t\t\tcpu-critical {\n+\t\t\t\t\ttemperature = <105000>;\n+\t\t\t\t\thysteresis = <2000>;\n+\t\t\t\t\ttype = \"critical\";\n+\t\t\t\t};\n+\n+\t\t\t\tcpu-hot {\n+\t\t\t\t\ttemperature = <95000>;\n+\t\t\t\t\thysteresis = <2000>;\n+\t\t\t\t\ttype = \"hot\";\n+\t\t\t\t};\n+\t\t\t};\n+\t\t};\n+\n+\t\ttsens_tz_sensor7 {\n+\t\t\tpolling-delay-passive = <0>;\n+\t\t\tpolling-delay = <0>;\n+\t\t\tthermal-sensors = <&tsens 7>;\n+\n+\t\t\ttrips {\n+\t\t\t\tcpu-critical {\n+\t\t\t\t\ttemperature = <105000>;\n+\t\t\t\t\thysteresis = <2000>;\n+\t\t\t\t\ttype = \"critical\";\n+\t\t\t\t};\n+\n+\t\t\t\tcpu-hot {\n+\t\t\t\t\ttemperature = <95000>;\n+\t\t\t\t\thysteresis = <2000>;\n+\t\t\t\t\ttype = \"hot\";\n+\t\t\t\t};\n+\t\t\t};\n+\t\t};\n+\n+\t\ttsens_tz_sensor8 {\n+\t\t\tpolling-delay-passive = <0>;\n+\t\t\tpolling-delay = <0>;\n+\t\t\tthermal-sensors = <&tsens 8>;\n+\n+\t\t\ttrips {\n+\t\t\t\tcpu-critical {\n+\t\t\t\t\ttemperature = <105000>;\n+\t\t\t\t\thysteresis = <2000>;\n+\t\t\t\t\ttype = \"critical\";\n+\t\t\t\t};\n+\n+\t\t\t\tcpu-hot {\n+\t\t\t\t\ttemperature = <95000>;\n+\t\t\t\t\thysteresis = <2000>;\n+\t\t\t\t\ttype = \"hot\";\n+\t\t\t\t};\n+\t\t\t};\n+\t\t};\n+\n+\t\ttsens_tz_sensor9 {\n+\t\t\tpolling-delay-passive = <0>;\n+\t\t\tpolling-delay = <0>;\n+\t\t\tthermal-sensors = <&tsens 9>;\n+\n+\t\t\ttrips {\n+\t\t\t\tcpu-critical {\n+\t\t\t\t\ttemperature = <105000>;\n+\t\t\t\t\thysteresis = <2000>;\n+\t\t\t\t\ttype = \"critical\";\n+\t\t\t\t};\n+\n+\t\t\t\tcpu-hot {\n+\t\t\t\t\ttemperature = <95000>;\n+\t\t\t\t\thysteresis = <2000>;\n+\t\t\t\t\ttype = \"hot\";\n+\t\t\t\t};\n+\t\t\t};\n+\t\t};\n+\n+\t\ttsens_tz_sensor10 {\n+\t\t\tpolling-delay-passive = <0>;\n+\t\t\tpolling-delay = <0>;\n+\t\t\tthermal-sensors = <&tsens 10>;\n+\n+\t\t\ttrips {\n+\t\t\t\tcpu-critical {\n+\t\t\t\t\ttemperature = <105000>;\n+\t\t\t\t\thysteresis = <2000>;\n+\t\t\t\t\ttype = \"critical\";\n+\t\t\t\t};\n+\n+\t\t\t\tcpu-hot {\n+\t\t\t\t\ttemperature = <95000>;\n+\t\t\t\t\thysteresis = <2000>;\n+\t\t\t\t\ttype = \"hot\";\n+\t\t\t\t};\n+\t\t\t};\n+ \t\t};\n+ \t};\n+\n \tmemory {\n \t\tdevice_type = \"memory\";\n \t\treg = <0x0 0x0>;\n@@ -93,6 +441,15 @@\n \t\t};\n \t};\n \n+\tfab-scaling {\n+\t\tcompatible = \"qcom,fab-scaling\";\n+\t\tclocks = <&rpmcc RPM_APPS_FABRIC_A_CLK>, <&rpmcc RPM_EBI1_A_CLK>;\n+\t\tclock-names = \"apps-fab-clk\", \"ddr-fab-clk\";\n+\t\tfab_freq_high = <533000000>;\n+\t\tfab_freq_nominal = <400000000>;\n+\t\tcpu_freq_threshold = <1000000000>;\n+\t};\n+\n \tfirmware {\n \t\tscm {\n \t\t\tcompatible = \"qcom,scm-ipq806x\", \"qcom,scm\";\n@@ -120,6 +477,78 @@\n \t\t\treg-names = \"lpass-lpaif\";\n \t\t};\n \n+\t\tL2: l2-cache {\n+\t\t\tcompatible = \"qcom,krait-cache\", \"cache\";\n+\t\t\tcache-level = <2>;\n+\t\t\tqcom,saw = <&saw_l2>;\n+\n+\t\t\tclocks = <&kraitcc 4>;\n+\t\t\tclock-names = \"l2\";\n+\t\t\tl2-supply = <&smb208_s1a>;\n+\t\t\toperating-points-v2 = <&opp_table_l2>;\n+\t\t};\n+\n+\t\trpm: rpm@108000 {\n+\t\t\tcompatible = \"qcom,rpm-ipq8064\";\n+\t\t\treg = <0x108000 0x1000>;\n+\t\t\tqcom,ipc = <&l2cc 0x8 2>;\n+\n+\t\t\tinterrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t\t\t <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t\t\t <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tinterrupt-names = \"ack\", \"err\", \"wakeup\";\n+\n+\t\t\tclocks = <&gcc RPM_MSG_RAM_H_CLK>;\n+\t\t\tclock-names = \"ram\";\n+\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\trpmcc: clock-controller {\n+\t\t\t\tcompatible = \"qcom,rpmcc-ipq806x\", \"qcom,rpmcc\";\n+\t\t\t\t#clock-cells = <1>;\n+\t\t\t};\n+\n+\t\t\tregulators {\n+\t\t\t\tcompatible = \"qcom,rpm-smb208-regulators\";\n+\n+\t\t\t\tsmb208_s1a: s1a {\n+\t\t\t\t\tregulator-min-microvolt = <1050000>;\n+\t\t\t\t\tregulator-max-microvolt = <1150000>;\n+\n+\t\t\t\t\tqcom,switch-mode-frequency = <1200000>;\n+\t\t\t\t};\n+\n+\t\t\t\tsmb208_s1b: s1b {\n+\t\t\t\t\tregulator-min-microvolt = <1050000>;\n+\t\t\t\t\tregulator-max-microvolt = <1150000>;\n+\n+\t\t\t\t\tqcom,switch-mode-frequency = <1200000>;\n+\t\t\t\t};\n+\n+\t\t\t\tsmb208_s2a: s2a {\n+\t\t\t\t\tregulator-min-microvolt = < 800000>;\n+\t\t\t\t\tregulator-max-microvolt = <1250000>;\n+\n+\t\t\t\t\tqcom,switch-mode-frequency = <1200000>;\n+\t\t\t\t};\n+\n+\t\t\t\tsmb208_s2b: s2b {\n+\t\t\t\t\tregulator-min-microvolt = < 800000>;\n+\t\t\t\t\tregulator-max-microvolt = <1250000>;\n+\n+\t\t\t\t\tqcom,switch-mode-frequency = <1200000>;\n+\t\t\t\t};\n+\t\t\t};\n+\t\t};\n+\n+\t\trng@1a500000 {\n+\t\t\tcompatible = \"qcom,prng\";\n+\t\t\treg = <0x1a500000 0x200>;\n+\t\t\tclocks = <&gcc PRNG_CLK>;\n+\t\t\tclock-names = \"core\";\n+\t\t};\n+\n \t\tqcom_pinmux: pinmux@800000 {\n \t\t\tcompatible = \"qcom,ipq8064-pinctrl\";\n \t\t\treg = <0x800000 0x4000>;\n@@ -160,6 +589,15 @@\n \t\t\t\t};\n \t\t\t};\n \n+\t\t\ti2c4_pins: i2c4_pinmux {\n+\t\t\t\tmux {\n+\t\t\t\t\tpins = \"gpio12\", \"gpio13\";\n+\t\t\t\t\tfunction = \"gsbi4\";\n+\t\t\t\t\tdrive-strength = <12>;\n+\t\t\t\t\tbias-disable;\n+\t\t\t\t};\n+\t\t\t};\n+\n \t\t\tspi_pins: spi_pins {\n \t\t\t\tmux {\n \t\t\t\t\tpins = \"gpio18\", \"gpio19\", \"gpio21\";\n@@ -169,6 +607,53 @@\n \t\t\t\t};\n \t\t\t};\n \n+\t\t\tnand_pins: nand_pins {\n+\t\t\t\tdisable {\n+\t\t\t\t\tpins = \"gpio34\", \"gpio35\", \"gpio36\",\n+\t\t\t\t\t       \"gpio37\", \"gpio38\";\n+\t\t\t\t\tfunction = \"nand\";\n+\t\t\t\t\tdrive-strength = <10>;\n+\t\t\t\t\tbias-disable;\n+\t\t\t\t};\n+\n+\t\t\t\tpullups {\n+\t\t\t\t\tpins = \"gpio39\";\n+\t\t\t\t\tfunction = \"nand\";\n+\t\t\t\t\tdrive-strength = <10>;\n+\t\t\t\t\tbias-pull-up;\n+\t\t\t\t};\n+\n+\t\t\t\thold {\n+\t\t\t\t\tpins = \"gpio40\", \"gpio41\", \"gpio42\",\n+\t\t\t\t\t       \"gpio43\", \"gpio44\", \"gpio45\",\n+\t\t\t\t\t       \"gpio46\", \"gpio47\";\n+\t\t\t\t\tfunction = \"nand\";\n+\t\t\t\t\tdrive-strength = <10>;\n+\t\t\t\t\tbias-bus-hold;\n+\t\t\t\t};\n+\t\t\t};\n+\n+\t\t\tmdio0_pins: mdio0_pins {\n+\t\t\t\tmux {\n+\t\t\t\t\tpins = \"gpio0\", \"gpio1\";\n+\t\t\t\t\tfunction = \"mdio\";\n+\t\t\t\t\tdrive-strength = <8>;\n+\t\t\t\t\tbias-disable;\n+\t\t\t\t};\n+\t\t\t};\n+\n+\t\t\trgmii2_pins: rgmii2_pins {\n+\t\t\t\tmux {\n+\t\t\t\t\tpins = \"gpio27\", \"gpio28\", \"gpio29\",\n+\t\t\t\t\t       \"gpio30\", \"gpio31\", \"gpio32\",\n+\t\t\t\t\t       \"gpio51\", \"gpio52\", \"gpio59\",\n+\t\t\t\t\t       \"gpio60\", \"gpio61\", \"gpio62\";\n+\t\t\t\t\tfunction = \"rgmii2\";\n+\t\t\t\t\tdrive-strength = <8>;\n+\t\t\t\t\tbias-disable;\n+\t\t\t\t};\n+\t\t\t};\n+\n \t\t\tleds_pins: leds_pins {\n \t\t\t\tmux {\n \t\t\t\t\tpins = \"gpio7\", \"gpio8\", \"gpio9\",\n@@ -231,6 +716,17 @@\n \t\t\tclock-output-names = \"acpu1_aux\";\n \t\t};\n \n+\t\tl2cc: clock-controller@2011000 {\n+\t\t\tcompatible = \"qcom,kpss-gcc\", \"syscon\";\n+\t\t\treg = <0x2011000 0x1000>;\n+\t\t\tclock-output-names = \"acpu_l2_aux\";\n+\t\t};\n+\n+\t\tkraitcc: clock-controller {\n+\t\t\tcompatible = \"qcom,krait-cc-v1\";\n+\t\t\t#clock-cells = <1>;\n+\t\t};\n+\n \t\tsaw0: regulator@2089000 {\n \t\t\tcompatible = \"qcom,saw2\", \"qcom,apq8064-saw2-v1.1-cpu\", \"syscon\";\n \t\t\treg = <0x02089000 0x1000>, <0x02009000 0x1000>;\n@@ -243,6 +739,52 @@\n \t\t\tregulator;\n \t\t};\n \n+\t\tsaw_l2: regulator@02012000 {\n+\t\t\tcompatible = \"qcom,saw2\", \"syscon\";\n+\t\t\treg = <0x02012000 0x1000>;\n+\t\t\tregulator;\n+\t\t};\n+\n+\t\tsic_non_secure: sic-non-secure@12100000 {\n+\t\t\tcompatible = \"syscon\";\n+\t\t\treg = <0x12100000 0x10000>;\n+\t\t};\n+\n+\t\tgsbi1: gsbi@12440000 {\n+\t\t\tcompatible = \"qcom,gsbi-v1.0.0\";\n+\t\t\tcell-index = <1>;\n+\t\t\treg = <0x12440000 0x100>;\n+\t\t\tclocks = <&gcc GSBI1_H_CLK>;\n+\t\t\tclock-names = \"iface\";\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <1>;\n+\t\t\tranges;\n+\t\t\tstatus = \"disabled\";\n+\n+\t\t\tsyscon-tcsr = <&tcsr>;\n+\n+\t\t\tgsbi1_serial: serial@12450000 {\n+\t\t\t\tcompatible = \"qcom,msm-uartdm-v1.3\", \"qcom,msm-uartdm\";\n+\t\t\t\treg = <0x12450000 0x100>,\n+\t\t\t\t      <0x12400000 0x03>;\n+\t\t\t\tinterrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\t\tclocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>;\n+\t\t\t\tclock-names = \"core\", \"iface\";\n+\t\t\t\tstatus = \"disabled\";\n+\t\t\t};\n+\n+\t\t\tgsbi1_i2c: i2c@12460000 {\n+\t\t\t\tcompatible = \"qcom,i2c-qup-v1.1.1\";\n+\t\t\t\treg = <0x12460000 0x1000>;\n+\t\t\t\tinterrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\t\tclocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;\n+\t\t\t\tclock-names = \"core\", \"iface\";\n+\t\t\t\t#address-cells = <1>;\n+\t\t\t\t#size-cells = <0>;\n+\t\t\t\tstatus = \"disabled\";\n+\t\t\t};\n+\t\t};\n+\n \t\tgsbi2: gsbi@12480000 {\n \t\t\tcompatible = \"qcom,gsbi-v1.0.0\";\n \t\t\tcell-index = <2>;\n@@ -368,6 +910,33 @@\n \t\t\t};\n \t\t};\n \n+\t\tgsbi6: gsbi@16500000 {\n+\t\t\tstatus = \"disabled\";\n+\t\t\tcompatible = \"qcom,gsbi-v1.0.0\";\n+\t\t\tcell-index = <6>;\n+\t\t\treg = <0x16500000 0x100>;\n+\t\t\tclocks = <&gcc GSBI6_H_CLK>;\n+\t\t\tclock-names = \"iface\";\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <1>;\n+\t\t\tranges;\n+\n+\t\t\tsyscon-tcsr = <&tcsr>;\n+\n+\t\t\tgsbi6_i2c: i2c@16580000 {\n+\t\t\t\tcompatible = \"qcom,i2c-qup-v1.1.1\";\n+\t\t\t\treg = <0x16580000 0x1000>;\n+\t\t\t\tinterrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;\n+\n+\t\t\t\tclocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>;\n+\t\t\t\tclock-names = \"core\", \"iface\";\n+\t\t\t\tstatus = \"disabled\";\n+\n+\t\t\t\t#address-cells = <1>;\n+\t\t\t\t#size-cells = <0>;\n+\t\t\t};\n+\t\t};\n+\n \t\tgsbi7: gsbi@16600000 {\n \t\t\tstatus = \"disabled\";\n \t\t\tcompatible = \"qcom,gsbi-v1.0.0\";\n@@ -389,6 +958,19 @@\n \t\t\t\tclock-names = \"core\", \"iface\";\n \t\t\t\tstatus = \"disabled\";\n \t\t\t};\n+\n+\t\t\tgsbi7_i2c: i2c@16680000 {\n+ \t\t\t\tcompatible = \"qcom,i2c-qup-v1.1.1\";\n+ \t\t\t\treg = <0x16680000 0x1000>;\n+\t\t\t\tinterrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;\n+\n+ \t\t\t\tclocks = <&gcc GSBI7_QUP_CLK>, <&gcc GSBI7_H_CLK>;\n+ \t\t\t\tclock-names = \"core\", \"iface\";\n+\t\t\t\tstatus = \"disabled\";\n+\n+ \t\t\t\t#address-cells = <1>;\n+\t\t\t\t#size-cells = <0>;\n+\t\t\t};\n \t\t};\n \n \t\tsata_phy: sata-phy@1b400000 {\n@@ -478,6 +1060,95 @@\n \t\t\t#reset-cells = <1>;\n \t\t};\n \n+\t\tsfpb_mutex_block: syscon@1200600 {\n+\t\t\tcompatible = \"syscon\";\n+\t\t\treg = <0x01200600 0x100>;\n+\t\t};\n+\n+\t\ths_phy_0: hs_phy_0 {\n+\t\t\tcompatible = \"qcom,ipq806x-usb-phy-hs\";\n+\t\t\treg = <0x100f8800 0x30>;\n+\t\t\tclocks = <&gcc USB30_0_UTMI_CLK>;\n+\t\t\tclock-names = \"ref\";\n+\t\t\t#phy-cells = <0>;\n+\t\t};\n+\n+\t\tss_phy_0: ss_phy_0 {\n+\t\t\tcompatible = \"qcom,ipq806x-usb-phy-ss\";\n+\t\t\treg = <0x100f8830 0x30>;\n+\t\t\tclocks = <&gcc USB30_0_MASTER_CLK>;\n+\t\t\tclock-names = \"ref\";\n+\t\t\t#phy-cells = <0>;\n+\t\t};\n+\n+\t\tusb3_0: usb3@100f8800 {\n+\t\t\tcompatible = \"qcom,dwc3\", \"syscon\";\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <1>;\n+\t\t\treg = <0x100f8800 0x8000>;\n+\t\t\tclocks = <&gcc USB30_0_MASTER_CLK>;\n+\t\t\tclock-names = \"core\";\n+\n+\t\t\tranges;\n+\n+\t\t\tresets = <&gcc USB30_0_MASTER_RESET>;\n+\t\t\treset-names = \"master\";\n+\n+\t\t\tstatus = \"disabled\";\n+\n+\t\t\tdwc3_0: dwc3@10000000 {\n+\t\t\t\tcompatible = \"snps,dwc3\";\n+\t\t\t\treg = <0x10000000 0xcd00>;\n+\t\t\t\tinterrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\t\tphys = <&hs_phy_0>, <&ss_phy_0>;\n+\t\t\t\tphy-names = \"usb2-phy\", \"usb3-phy\";\n+\t\t\t\tdr_mode = \"host\";\n+\t\t\t\tsnps,dis_u3_susphy_quirk;\n+\t\t\t};\n+\t\t};\n+\n+\t\ths_phy_1: hs_phy_1 {\n+\t\t\tcompatible = \"qcom,ipq806x-usb-phy-hs\";\n+\t\t\treg = <0x110f8800 0x30>;\n+\t\t\tclocks = <&gcc USB30_1_UTMI_CLK>;\n+\t\t\tclock-names = \"ref\";\n+\t\t\t#phy-cells = <0>;\n+\t\t};\n+\n+\t\tss_phy_1: ss_phy_1 {\n+\t\t\tcompatible = \"qcom,ipq806x-usb-phy-ss\";\n+\t\t\treg = <0x110f8830 0x30>;\n+\t\t\tclocks = <&gcc USB30_1_MASTER_CLK>;\n+\t\t\tclock-names = \"ref\";\n+\t\t\t#phy-cells = <0>;\n+\t\t};\n+\n+\t\tusb3_1: usb3@110f8800 {\n+\t\t\tcompatible = \"qcom,dwc3\", \"syscon\";\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <1>;\n+\t\t\treg = <0x110f8800 0x8000>;\n+\t\t\tclocks = <&gcc USB30_1_MASTER_CLK>;\n+\t\t\tclock-names = \"core\";\n+\n+\t\t\tranges;\n+\n+\t\t\tresets = <&gcc USB30_1_MASTER_RESET>;\n+\t\t\treset-names = \"master\";\n+\n+\t\t\tstatus = \"disabled\";\n+\n+\t\t\tdwc3_1: dwc3@11000000 {\n+\t\t\t\tcompatible = \"snps,dwc3\";\n+\t\t\t\treg = <0x11000000 0xcd00>;\n+\t\t\t\tinterrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\t\tphys = <&hs_phy_1>, <&ss_phy_1>;\n+\t\t\t\tphy-names = \"usb2-phy\", \"usb3-phy\";\n+\t\t\t\tdr_mode = \"host\";\n+\t\t\t\tsnps,dis_u3_susphy_quirk;\n+\t\t\t};\n+\t\t};\n+\n \t\tpcie0: pci@1b500000 {\n \t\t\tcompatible = \"qcom,pcie-ipq8064\";\n \t\t\treg = <0x1b500000 0x1000\n@@ -739,6 +1410,59 @@\n \t\t\tstatus = \"disabled\";\n \t\t};\n \n+\t\tadm_dma: dma@18300000 {\n+\t\t\tcompatible = \"qcom,adm\";\n+\t\t\treg = <0x18300000 0x100000>;\n+\t\t\tinterrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\t#dma-cells = <1>;\n+\n+\t\t\tclocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>;\n+\t\t\tclock-names = \"core\", \"iface\";\n+\n+\t\t\tresets = <&gcc ADM0_RESET>,\n+\t\t\t\t <&gcc ADM0_PBUS_RESET>,\n+\t\t\t\t <&gcc ADM0_C0_RESET>,\n+\t\t\t\t <&gcc ADM0_C1_RESET>,\n+\t\t\t\t <&gcc ADM0_C2_RESET>;\n+\t\t\treset-names = \"clk\", \"pbus\", \"c0\", \"c1\", \"c2\";\n+\t\t\tqcom,ee = <0>;\n+\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tnand: nand-controller@1ac00000 {\n+\t\t\tcompatible = \"qcom,ipq806x-nand\";\n+\t\t\treg = <0x1ac00000 0x800>;\n+\n+\t\t\tclocks = <&gcc EBI2_CLK>,\n+\t\t\t\t <&gcc EBI2_AON_CLK>;\n+\t\t\tclock-names = \"core\", \"aon\";\n+\n+\t\t\tdmas = <&adm_dma 3>;\n+\t\t\tdma-names = \"rxtx\";\n+\t\t\tqcom,cmd-crci = <15>;\n+\t\t\tqcom,data-crci = <3>;\n+\n+\t\t\tstatus = \"disabled\";\n+\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t};\n+\n+\t\tmdio0: mdio@37000000 {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tcompatible = \"qcom,ipq8064-mdio\", \"syscon\";\n+\t\t\treg = <0x37000000 0x200000>;\n+\t\t\tresets = <&gcc GMAC_CORE1_RESET>;\n+\t\t\treset-names = \"stmmaceth\";\n+\t\t\tclocks = <&gcc GMAC_CORE1_CLK>;\n+\t\t\tclock-names = \"stmmaceth\";\n+\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n \t\tvsdcc_fixed: vsdcc-regulator {\n \t\t\tcompatible = \"regulator-fixed\";\n \t\t\tregulator-name = \"SDCC Power\";\n@@ -814,4 +1538,17 @@\n \t\t\t};\n \t\t};\n \t};\n+\n+\tsfpb_mutex: sfpb-mutex {\n+\t\tcompatible = \"qcom,sfpb-mutex\";\n+\t\tsyscon = <&sfpb_mutex_block 4 4>;\n+\n+\t\t#hwlock-cells = <1>;\n+\t};\n+\n+\tsmem {\n+\t\tcompatible = \"qcom,smem\";\n+\t\tmemory-region = <&smem>;\n+\t\thwlocks = <&sfpb_mutex 3>;\n+\t};\n };\n"
  },
  {
    "path": "target/linux/ipq806x/patches-5.10/084-ipq8064-v1.0-dtsi-cleanup.patch",
    "content": "This uses upstream qcom-ipq8064-v1.0.dtsi and modifies it by patches\ninstead of keeping a local version.\nWe drop partitions, LEDs and keys from the file as we will implement\nthem differently anyway.\n\n--- a/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi\n+++ b/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi\n@@ -42,16 +42,6 @@\n \t\t\t\t\t#size-cells = <1>;\n \t\t\t\t\tspi-max-frequency = <50000000>;\n \t\t\t\t\treg = <0>;\n-\n-\t\t\t\t\tpartition@0 {\n-\t\t\t\t\t\tlabel = \"rootfs\";\n-\t\t\t\t\t\treg = <0x0 0x1000000>;\n-\t\t\t\t\t};\n-\n-\t\t\t\t\tpartition@1 {\n-\t\t\t\t\t\tlabel = \"scratch\";\n-\t\t\t\t\t\treg = <0x1000000 0x1000000>;\n-\t\t\t\t\t};\n \t\t\t\t};\n \t\t\t};\n \t\t};\n@@ -64,64 +54,5 @@\n \t\t\tports-implemented = <0x1>;\n \t\t\tstatus = \"ok\";\n \t\t};\n-\n-\t\tgpio_keys {\n-\t\t\tcompatible = \"gpio-keys\";\n-\t\t\tpinctrl-0 = <&buttons_pins>;\n-\t\t\tpinctrl-names = \"default\";\n-\n-\t\t\tbutton@1 {\n-\t\t\t\tlabel = \"reset\";\n-\t\t\t\tlinux,code = <KEY_RESTART>;\n-\t\t\t\tgpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;\n-\t\t\t\tlinux,input-type = <1>;\n-\t\t\t\tdebounce-interval = <60>;\n-\t\t\t};\n-\t\t\tbutton@2 {\n-\t\t\t\tlabel = \"wps\";\n-\t\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n-\t\t\t\tgpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>;\n-\t\t\t\tlinux,input-type = <1>;\n-\t\t\t\tdebounce-interval = <60>;\n-\t\t\t};\n-\t\t};\n-\n-\t\tleds {\n-\t\t\tcompatible = \"gpio-leds\";\n-\t\t\tpinctrl-0 = <&leds_pins>;\n-\t\t\tpinctrl-names = \"default\";\n-\n-\t\t\tled@7 {\n-\t\t\t\tlabel = \"led_usb1\";\n-\t\t\t\tgpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>;\n-\t\t\t\tlinux,default-trigger = \"usbdev\";\n-\t\t\t\tdefault-state = \"off\";\n-\t\t\t};\n-\n-\t\t\tled@8 {\n-\t\t\t\tlabel = \"led_usb3\";\n-\t\t\t\tgpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;\n-\t\t\t\tlinux,default-trigger = \"usbdev\";\n-\t\t\t\tdefault-state = \"off\";\n-\t\t\t};\n-\n-\t\t\tled@9 {\n-\t\t\t\tlabel = \"status_led_fail\";\n-\t\t\t\tgpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;\n-\t\t\t\tdefault-state = \"off\";\n-\t\t\t};\n-\n-\t\t\tled@26 {\n-\t\t\t\tlabel = \"sata_led\";\n-\t\t\t\tgpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>;\n-\t\t\t\tdefault-state = \"off\";\n-\t\t\t};\n-\n-\t\t\tled@53 {\n-\t\t\t\tlabel = \"status_led_pass\";\n-\t\t\t\tgpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>;\n-\t\t\t\tdefault-state = \"off\";\n-\t\t\t};\n-\t\t};\n \t};\n };\n"
  },
  {
    "path": "target/linux/ipq806x/patches-5.10/085-ipq8064-v1.0-dtsi-additions.patch",
    "content": "This uses upstream qcom-ipq8064-v1.0.dtsi and modifies it by patches\ninstead of keeping a local version. This patch adds our local adjustments\nfor the (local) additional contents of qcom-ipq8064.dtsi\n\n--- a/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi\n+++ b/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi\n@@ -56,3 +56,7 @@\n \t\t};\n \t};\n };\n+\n+&CPU_SPC {\n+\tstatus = \"okay\";\n+};\n"
  },
  {
    "path": "target/linux/ipq806x/patches-5.10/086-ipq8064-fix-duplicate-node.patch",
    "content": "--- a/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts\n+++ b/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts\n@@ -24,73 +24,6 @@\n \t\tdevice_type = \"memory\";\n \t};\n \n-\tmdio0: mdio-0 {\n-\t\tstatus = \"okay\";\n-\t\tcompatible = \"virtual,mdio-gpio\";\n-\t\tgpios = <&qcom_pinmux 1 GPIO_ACTIVE_HIGH>,\n-\t\t\t<&qcom_pinmux 0 GPIO_ACTIVE_HIGH>;\n-\t\t#address-cells = <1>;\n-\t\t#size-cells = <0>;\n-\n-\t\tpinctrl-0 = <&mdio0_pins>;\n-\t\tpinctrl-names = \"default\";\n-\n-\t\tswitch0: switch@10 {\n-\t\t\tcompatible = \"qca,qca8337\";\n-\t\t\t#address-cells = <1>;\n-\t\t\t#size-cells = <0>;\n-\n-\t\t\tdsa,member = <0 0>;\n-\n-\t\t\tpinctrl-0 = <&sw0_reset_pin>;\n-\t\t\tpinctrl-names = \"default\";\n-\n-\t\t\treset-gpios = <&qcom_pinmux 16 GPIO_ACTIVE_LOW>;\n-\t\t\treg = <0x10>;\n-\n-\t\t\tports {\n-\t\t\t\t#address-cells = <1>;\n-\t\t\t\t#size-cells = <0>;\n-\n-\t\t\t\tswitch0cpu: port@0 {\n-\t\t\t\t\treg = <0>;\n-\t\t\t\t\tlabel = \"cpu\";\n-\t\t\t\t\tethernet = <&gmac0>;\n-\t\t\t\t\tphy-mode = \"rgmii-id\";\n-\t\t\t\t\tfixed-link {\n-\t\t\t\t\t\tspeed = <1000>;\n-\t\t\t\t\t\tfull-duplex;\n-\t\t\t\t\t};\n-\t\t\t\t};\n-\n-\t\t\t\tport@1 {\n-\t\t\t\t\treg = <1>;\n-\t\t\t\t\tlabel = \"sw1\";\n-\t\t\t\t};\n-\n-\t\t\t\tport@2 {\n-\t\t\t\t\treg = <2>;\n-\t\t\t\t\tlabel = \"sw2\";\n-\t\t\t\t};\n-\n-\t\t\t\tport@3 {\n-\t\t\t\t\treg = <3>;\n-\t\t\t\t\tlabel = \"sw3\";\n-\t\t\t\t};\n-\n-\t\t\t\tport@4 {\n-\t\t\t\t\treg = <4>;\n-\t\t\t\t\tlabel = \"sw4\";\n-\t\t\t\t};\n-\n-\t\t\t\tport@5 {\n-\t\t\t\t\treg = <5>;\n-\t\t\t\t\tlabel = \"sw5\";\n-\t\t\t\t};\n-\t\t\t};\n-\t\t};\n-\t};\n-\n \tmdio1: mdio-1 {\n \t\tstatus = \"okay\";\n \t\tcompatible = \"virtual,mdio-gpio\";\n@@ -216,6 +149,68 @@\n \t};\n };\n \n+&mdio0 {\n+\tstatus = \"okay\";\n+\n+\tpinctrl-0 = <&mdio0_pins>;\n+\tpinctrl-names = \"default\";\n+\n+\tswitch0: switch@10 {\n+\t\tcompatible = \"qca,qca8337\";\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\n+\t\tdsa,member = <0 0>;\n+\n+\t\tpinctrl-0 = <&sw0_reset_pin>;\n+\t\tpinctrl-names = \"default\";\n+\n+\t\treset-gpios = <&qcom_pinmux 16 GPIO_ACTIVE_LOW>;\n+\t\treg = <0x10>;\n+\n+\t\tports {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tswitch0cpu: port@0 {\n+\t\t\t\treg = <0>;\n+\t\t\t\tlabel = \"cpu\";\n+\t\t\t\tethernet = <&gmac0>;\n+\t\t\t\tphy-mode = \"rgmii-id\";\n+\t\t\t\tfixed-link {\n+\t\t\t\t\tspeed = <1000>;\n+\t\t\t\t\tfull-duplex;\n+\t\t\t\t};\n+\t\t\t};\n+\n+\t\t\tport@1 {\n+\t\t\t\treg = <1>;\n+\t\t\t\tlabel = \"sw1\";\n+\t\t\t};\n+\n+\t\t\tport@2 {\n+\t\t\t\treg = <2>;\n+\t\t\t\tlabel = \"sw2\";\n+\t\t\t};\n+\n+\t\t\tport@3 {\n+\t\t\t\treg = <3>;\n+\t\t\t\tlabel = \"sw3\";\n+\t\t\t};\n+\n+\t\t\tport@4 {\n+\t\t\t\treg = <4>;\n+\t\t\t\tlabel = \"sw4\";\n+\t\t\t};\n+\n+\t\t\tport@5 {\n+\t\t\t\treg = <5>;\n+\t\t\t\tlabel = \"sw5\";\n+\t\t\t};\n+\t\t};\n+\t};\n+};\n+\n &gmac0 {\n \tstatus = \"okay\";\n \n"
  },
  {
    "path": "target/linux/ipq806x/patches-5.10/093-drivers-cpufreq-qcom-cpufreq-nvmem-support-specific-.patch",
    "content": "From a206d4061f1cc2c5cd17ee45c53a0ba711e48e6d Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Sun, 7 Feb 2021 16:42:52 +0100\nSubject: [PATCH 3/3] drivers: cpufreq: qcom-cpufreq-nvmem: support specific\n cpufreq driver\n\nAdd support for specific cpufreq driver for qcom-cpufreq-nvmem driver.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\n---\n drivers/cpufreq/qcom-cpufreq-nvmem.c | 15 +++++++++++++++\n 1 file changed, 15 insertions(+)\n\n--- a/drivers/cpufreq/qcom-cpufreq-nvmem.c\n+++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c\n@@ -52,6 +52,7 @@ struct qcom_cpufreq_match_data {\n \t\t\t   char **pvs_name,\n \t\t\t   struct qcom_cpufreq_drv *drv);\n \tconst char **genpd_names;\n+\tconst char *cpufreq_driver;\n };\n \n struct qcom_cpufreq_drv {\n@@ -250,6 +251,7 @@ static const struct qcom_cpufreq_match_d\n \n static const struct qcom_cpufreq_match_data match_data_krait = {\n \t.get_version = qcom_cpufreq_krait_name_version,\n+\t.cpufreq_driver = \"krait-cpufreq\",\n };\n \n static const char *qcs404_genpd_names[] = { \"cpr\", NULL };\n@@ -385,6 +387,19 @@ static int qcom_cpufreq_probe(struct pla\n \t\t}\n \t}\n \n+\tif (drv->data->cpufreq_driver) {\n+\t\tcpufreq_dt_pdev = platform_device_register_simple(\n+\t\t\tdrv->data->cpufreq_driver, -1, NULL, 0);\n+\t\tif (!IS_ERR(cpufreq_dt_pdev)) {\n+\t\t\tplatform_set_drvdata(pdev, drv);\n+\t\t\treturn 0;\n+\t\t} else {\n+\t\t\tdev_err(cpu_dev,\n+\t\t\t\t\"Failed to register dedicated %s cpufreq\\n\",\n+\t\t\t\tdrv->data->cpufreq_driver);\n+\t\t}\n+\t}\n+\n \tcpufreq_dt_pdev = platform_device_register_simple(\"cpufreq-dt\", -1,\n \t\t\t\t\t\t\t  NULL, 0);\n \tif (!IS_ERR(cpufreq_dt_pdev)) {\n"
  },
  {
    "path": "target/linux/ipq806x/patches-5.10/097-1-ipq806x-gcc-add-missing-clk-flag.patch",
    "content": "From 0af44917941cbfecdc86bb9bf05ff01d22a88973 Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Sun, 7 Feb 2021 16:52:56 +0100\nSubject: [PATCH 1/4] ipq806x: gcc: add missing clk flag\n\nSome flag are missing from the original code.\nThese clk can't be set using the protected-clock proprities as they\ncause the malfunction of the serial interface.\nThese clks are needed for the rpm interface to work proprely or the\ncpu regulators starts to fail as soon as they are disabled by the\nkernel.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\n---\n drivers/clk/qcom/gcc-ipq806x.c | 19 +++++++++++++------\n 1 file changed, 13 insertions(+), 6 deletions(-)\n\n--- a/drivers/clk/qcom/gcc-ipq806x.c\n+++ b/drivers/clk/qcom/gcc-ipq806x.c\n@@ -65,6 +65,7 @@ static struct clk_pll pll3 = {\n \t\t.parent_names = (const char *[]){ \"pxo\" },\n \t\t.num_parents = 1,\n \t\t.ops = &clk_pll_ops,\n+\t\t.flags = CLK_IS_CRITICAL,\n \t},\n };\n \n@@ -782,7 +783,7 @@ static struct clk_rcg gsbi4_qup_src = {\n \t\t\t.parent_names = gcc_pxo_pll8,\n \t\t\t.num_parents = 2,\n \t\t\t.ops = &clk_rcg_ops,\n-\t\t\t.flags = CLK_SET_PARENT_GATE,\n+\t\t\t.flags = CLK_SET_PARENT_GATE | CLK_IGNORE_UNUSED,\n \t\t},\n \t},\n };\n@@ -798,7 +799,7 @@ static struct clk_branch gsbi4_qup_clk =\n \t\t\t.parent_names = (const char *[]){ \"gsbi4_qup_src\" },\n \t\t\t.num_parents = 1,\n \t\t\t.ops = &clk_branch_ops,\n-\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,\n \t\t},\n \t},\n };\n@@ -880,7 +881,7 @@ static struct clk_rcg gsbi6_qup_src = {\n \t\t\t.parent_names = gcc_pxo_pll8,\n \t\t\t.num_parents = 2,\n \t\t\t.ops = &clk_rcg_ops,\n-\t\t\t.flags = CLK_SET_PARENT_GATE,\n+\t\t\t.flags = CLK_SET_PARENT_GATE | CLK_IGNORE_UNUSED,\n \t\t},\n \t},\n };\n@@ -945,7 +946,7 @@ static struct clk_branch gsbi7_qup_clk =\n \t\t\t.parent_names = (const char *[]){ \"gsbi7_qup_src\" },\n \t\t\t.num_parents = 1,\n \t\t\t.ops = &clk_branch_ops,\n-\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,\n \t\t},\n \t},\n };\n@@ -991,6 +992,7 @@ static struct clk_branch gsbi4_h_clk = {\n \t\t.hw.init = &(struct clk_init_data){\n \t\t\t.name = \"gsbi4_h_clk\",\n \t\t\t.ops = &clk_branch_ops,\n+\t\t\t.flags = CLK_IGNORE_UNUSED,\n \t\t},\n \t},\n };\n@@ -1424,6 +1426,7 @@ static struct clk_rcg tsif_ref_src = {\n \t\t\t.parent_names = gcc_pxo_pll8,\n \t\t\t.num_parents = 2,\n \t\t\t.ops = &clk_rcg_ops,\n+\t\t\t.flags = CLK_SET_RATE_GATE,\n \t\t},\n \t}\n };\n@@ -2694,7 +2697,8 @@ static struct clk_dyn_rcg ubi32_core1_sr\n \t\t\t.parent_names = gcc_pxo_pll8_pll14_pll18_pll0,\n \t\t\t.num_parents = 5,\n \t\t\t.ops = &clk_dyn_rcg_ops,\n-\t\t\t.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,\n+\t\t\t.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE |\n+\t\t\t\t CLK_IGNORE_UNUSED,\n \t\t},\n \t},\n };\n@@ -2747,7 +2751,8 @@ static struct clk_dyn_rcg ubi32_core2_sr\n \t\t\t.parent_names = gcc_pxo_pll8_pll14_pll18_pll0,\n \t\t\t.num_parents = 5,\n \t\t\t.ops = &clk_dyn_rcg_ops,\n-\t\t\t.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,\n+\t\t\t.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE |\n+\t\t\t\t CLK_IGNORE_UNUSED,\n \t\t},\n \t},\n };\n"
  },
  {
    "path": "target/linux/ipq806x/patches-5.10/097-2-ipq806x-lcc-add-missing-reset.patch",
    "content": "From 3a5f1793c0bf4a6b536751886b0a44589fe05f35 Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Sun, 7 Feb 2021 17:00:07 +0100\nSubject: [PATCH 2/4] ipq806x: lcc: add missing reset\n\nAdd missing reset for ipq806x lcc clk\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\n---\n drivers/clk/qcom/lcc-ipq806x.c               | 8 ++++++++\n include/dt-bindings/clock/qcom,lcc-ipq806x.h | 1 +\n 2 files changed, 9 insertions(+)\n\n--- a/drivers/clk/qcom/lcc-ipq806x.c\n+++ b/drivers/clk/qcom/lcc-ipq806x.c\n@@ -12,6 +12,7 @@\n #include <linux/of_device.h>\n #include <linux/clk-provider.h>\n #include <linux/regmap.h>\n+#include <linux/reset-controller.h>\n \n #include <dt-bindings/clock/qcom,lcc-ipq806x.h>\n \n@@ -22,6 +23,7 @@\n #include \"clk-branch.h\"\n #include \"clk-regmap-divider.h\"\n #include \"clk-regmap-mux.h\"\n+#include \"reset.h\"\n \n static struct clk_pll pll4 = {\n \t.l_reg = 0x4,\n@@ -39,6 +41,10 @@ static struct clk_pll pll4 = {\n \t},\n };\n \n+static const struct qcom_reset_map lcc_ipq806x_resets[] = {\n+\t[LCC_PCM_RESET] = { 0x54, 13 },\n+};\n+\n static const struct pll_config pll4_config = {\n \t.l = 0xf,\n \t.m = 0x91,\n@@ -417,6 +423,8 @@ static const struct qcom_cc_desc lcc_ipq\n \t.config = &lcc_ipq806x_regmap_config,\n \t.clks = lcc_ipq806x_clks,\n \t.num_clks = ARRAY_SIZE(lcc_ipq806x_clks),\n+\t.resets = lcc_ipq806x_resets,\n+\t.num_resets = ARRAY_SIZE(lcc_ipq806x_resets),\n };\n \n static const struct of_device_id lcc_ipq806x_match_table[] = {\n--- a/include/dt-bindings/clock/qcom,lcc-ipq806x.h\n+++ b/include/dt-bindings/clock/qcom,lcc-ipq806x.h\n@@ -19,4 +19,5 @@\n #define SPDIF_CLK\t\t\t10\n #define AHBIX_CLK\t\t\t11\n \n+#define LCC_PCM_RESET\t\t\t0\n #endif\n"
  },
  {
    "path": "target/linux/ipq806x/patches-5.10/097-3-clk-qcom-krait-add-missing-enable-disable.patch",
    "content": "From f8fdbecdaca97f0f2eebd77256e2eca4a8da6c39 Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Sun, 7 Feb 2021 17:08:16 +0100\nSubject: [PATCH 3/4] clk: qcom: krait: add missing enable disable\n\nAdd missing enable disable mux function. Add extra check to\ndiv2_round_rate.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\n---\n drivers/clk/qcom/clk-krait.c | 27 +++++++++++++++++++++++++--\n 1 file changed, 25 insertions(+), 2 deletions(-)\n\n--- a/drivers/clk/qcom/clk-krait.c\n+++ b/drivers/clk/qcom/clk-krait.c\n@@ -68,7 +68,25 @@ static u8 krait_mux_get_parent(struct cl\n \treturn clk_mux_val_to_index(hw, mux->parent_map, 0, sel);\n }\n \n+static int krait_mux_enable(struct clk_hw *hw)\n+{\n+\tstruct krait_mux_clk *mux = to_krait_mux_clk(hw);\n+\n+\t__krait_mux_set_sel(mux, mux->en_mask);\n+\n+\treturn 0;\n+}\n+\n+static void krait_mux_disable(struct clk_hw *hw)\n+{\n+\tstruct krait_mux_clk *mux = to_krait_mux_clk(hw);\n+\n+\t__krait_mux_set_sel(mux, mux->safe_sel);\n+}\n+\n const struct clk_ops krait_mux_clk_ops = {\n+\t.enable = krait_mux_enable,\n+\t.disable = krait_mux_disable,\n \t.set_parent = krait_mux_set_parent,\n \t.get_parent = krait_mux_get_parent,\n \t.determine_rate = __clk_mux_determine_rate_closest,\n@@ -79,8 +97,13 @@ EXPORT_SYMBOL_GPL(krait_mux_clk_ops);\n static long krait_div2_round_rate(struct clk_hw *hw, unsigned long rate,\n \t\t\t\t  unsigned long *parent_rate)\n {\n-\t*parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw), rate * 2);\n-\treturn DIV_ROUND_UP(*parent_rate, 2);\n+\tstruct clk_hw *hw_parent = clk_hw_get_parent(hw);\n+\n+\tif (hw_parent) {\n+\t\t*parent_rate = clk_hw_round_rate(hw_parent, rate * 2);\n+\t\treturn DIV_ROUND_UP(*parent_rate, 2);\n+\t} else\n+\t\treturn -1;\n }\n \n static int krait_div2_set_rate(struct clk_hw *hw, unsigned long rate,\n"
  },
  {
    "path": "target/linux/ipq806x/patches-5.10/097-4-ipq806x-gcc-add-missing-clk-and-reset-for-crypto-eng.patch",
    "content": "From 22a0f55b0e505fbbbb680e451a62878bc97f7ff1 Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Sun, 7 Feb 2021 17:23:38 +0100\nSubject: [PATCH 4/4] ipq806x: gcc: add missing clk and reset for crypto engine\n\nAdd missing clk and reset needed for nss additional core and crypto\nengine.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\n---\n drivers/clk/qcom/gcc-ipq806x.c               | 250 +++++++++++++++++++\n include/dt-bindings/clock/qcom,gcc-ipq806x.h |   5 +-\n include/dt-bindings/reset/qcom,gcc-ipq806x.h |   5 +\n 3 files changed, 259 insertions(+), 1 deletion(-)\n\n--- a/drivers/clk/qcom/gcc-ipq806x.c\n+++ b/drivers/clk/qcom/gcc-ipq806x.c\n@@ -223,7 +223,9 @@ static struct clk_regmap pll14_vote = {\n \n static struct pll_freq_tbl pll18_freq_tbl[] = {\n \tNSS_PLL_RATE(550000000, 44, 0, 1, 0x01495625),\n+\tNSS_PLL_RATE(600000000, 48, 0, 1, 0x01495625),\n \tNSS_PLL_RATE(733000000, 58, 16, 25, 0x014b5625),\n+\tNSS_PLL_RATE(800000000, 64, 0, 1, 0x01495625),\n };\n \n static struct clk_pll pll18 = {\n@@ -245,6 +247,22 @@ static struct clk_pll pll18 = {\n \t},\n };\n \n+static struct clk_pll pll11 = {\n+\t.l_reg = 0x3184,\n+\t.m_reg = 0x3188,\n+\t.n_reg = 0x318c,\n+\t.config_reg = 0x3194,\n+\t.mode_reg = 0x3180,\n+\t.status_reg = 0x3198,\n+\t.status_bit = 16,\n+\t.clkr.hw.init = &(struct clk_init_data){\n+\t\t.name = \"pll11\",\n+\t\t.parent_names = (const char *[]){ \"pxo\" },\n+\t\t.num_parents = 1,\n+\t\t.ops = &clk_pll_ops,\n+\t},\n+};\n+\n enum {\n \tP_PXO,\n \tP_PLL8,\n@@ -253,6 +271,7 @@ enum {\n \tP_CXO,\n \tP_PLL14,\n \tP_PLL18,\n+\tP_PLL11,\n };\n \n static const struct parent_map gcc_pxo_pll8_map[] = {\n@@ -320,6 +339,42 @@ static const char * const gcc_pxo_pll8_p\n \t\"pll18\",\n };\n \n+static const struct parent_map gcc_pxo_pll8_pll0_pll14_pll18_pll11_map[] = {\n+\t{ P_PXO, 0 },\n+\t{ P_PLL8, 4 },\n+\t{ P_PLL0, 2 },\n+\t{ P_PLL14, 5 },\n+\t{ P_PLL18, 1 },\n+\t{ P_PLL11, 3 },\n+};\n+\n+static const char *gcc_pxo_pll8_pll0_pll14_pll18_pll11[] = {\n+\t\"pxo\",\n+\t\"pll8_vote\",\n+\t\"pll0_vote\",\n+\t\"pll14\",\n+\t\"pll18\",\n+\t\"pll11\"\n+};\n+\n+static const struct parent_map gcc_pxo_pll3_pll0_pll14_pll18_pll11_map[] = {\n+\t{ P_PXO, 0 },\n+\t{ P_PLL3, 6 },\n+\t{ P_PLL0, 2 },\n+\t{ P_PLL14, 5 },\n+\t{ P_PLL18, 1 },\n+\t{ P_PLL11, 3 },\n+};\n+\n+static const char *gcc_pxo_pll3_pll0_pll14_pll18_pll11[] = {\n+\t\"pxo\",\n+\t\"pll3\",\n+\t\"pll0_vote\",\n+\t\"pll14\",\n+\t\"pll18\",\n+\t\"pll11\"\n+};\n+\n static struct freq_tbl clk_tbl_gsbi_uart[] = {\n \t{  1843200, P_PLL8, 2,  6, 625 },\n \t{  3686400, P_PLL8, 2, 12, 625 },\n@@ -1261,6 +1316,7 @@ static const struct freq_tbl clk_tbl_sdc\n \t{  20210000, P_PLL8,  1, 1,  19 },\n \t{  24000000, P_PLL8,  4, 1,   4 },\n \t{  48000000, P_PLL8,  4, 1,   2 },\n+\t{  52000000, P_PLL8,  1, 2,  15 }, /* 51.2 Mhz */\n \t{  64000000, P_PLL8,  3, 1,   2 },\n \t{  96000000, P_PLL8,  4, 0,   0 },\n \t{ 192000000, P_PLL8,  2, 0,   0 },\n@@ -2645,7 +2701,9 @@ static const struct freq_tbl clk_tbl_nss\n \t{ 110000000, P_PLL18, 1, 1, 5 },\n \t{ 275000000, P_PLL18, 2, 0, 0 },\n \t{ 550000000, P_PLL18, 1, 0, 0 },\n+\t{ 600000000, P_PLL18, 1, 0, 0 },\n \t{ 733000000, P_PLL18, 1, 0, 0 },\n+\t{ 800000000, P_PLL18, 1, 0, 0 },\n \t{ }\n };\n \n@@ -2757,6 +2815,186 @@ static struct clk_dyn_rcg ubi32_core2_sr\n \t},\n };\n \n+static const struct freq_tbl clk_tbl_ce5_core[] = {\n+\t{ 150000000, P_PLL3, 8, 1, 1 },\n+\t{ 213200000, P_PLL11, 5, 1, 1 },\n+\t{ }\n+};\n+\n+static struct clk_dyn_rcg ce5_core_src = {\n+\t.ns_reg[0] = 0x36C4,\n+\t.ns_reg[1] = 0x36C8,\n+\t.bank_reg = 0x36C0,\n+\t.s[0] = {\n+\t\t.src_sel_shift = 0,\n+\t\t.parent_map = gcc_pxo_pll3_pll0_pll14_pll18_pll11_map,\n+\t},\n+\t.s[1] = {\n+\t\t.src_sel_shift = 0,\n+\t\t.parent_map = gcc_pxo_pll3_pll0_pll14_pll18_pll11_map,\n+\t},\n+\t.p[0] = {\n+\t\t.pre_div_shift = 3,\n+\t\t.pre_div_width = 4,\n+\t},\n+\t.p[1] = {\n+\t\t.pre_div_shift = 3,\n+\t\t.pre_div_width = 4,\n+\t},\n+\t.mux_sel_bit = 0,\n+\t.freq_tbl = clk_tbl_ce5_core,\n+\t.clkr = {\n+\t\t.enable_reg = 0x36C0,\n+\t\t.enable_mask = BIT(1),\n+\t\t.hw.init = &(struct clk_init_data){\n+\t\t\t.name = \"ce5_core_src\",\n+\t\t\t.parent_names = gcc_pxo_pll3_pll0_pll14_pll18_pll11,\n+\t\t\t.num_parents = 6,\n+\t\t\t.ops = &clk_dyn_rcg_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch ce5_core_clk = {\n+\t.halt_reg = 0x2FDC,\n+\t.halt_bit = 5,\n+\t.hwcg_reg = 0x36CC,\n+\t.hwcg_bit = 6,\n+\t.clkr = {\n+\t\t.enable_reg = 0x36CC,\n+\t\t.enable_mask = BIT(4),\n+\t\t.hw.init = &(struct clk_init_data){\n+\t\t\t.name = \"ce5_core_clk\",\n+\t\t\t.parent_names = (const char *[]){\n+\t\t\t\t\"ce5_core_src\",\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.ops = &clk_branch_ops,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t},\n+\t},\n+};\n+\n+static const struct freq_tbl clk_tbl_ce5_a_clk[] = {\n+\t{ 160000000, P_PLL0, 5, 1, 1 },\n+\t{ 213200000, P_PLL11, 5, 1, 1 },\n+\t{ }\n+};\n+\n+static struct clk_dyn_rcg ce5_a_clk_src = {\n+\t.ns_reg[0] = 0x3d84,\n+\t.ns_reg[1] = 0x3d88,\n+\t.bank_reg = 0x3d80,\n+\t.s[0] = {\n+\t\t.src_sel_shift = 0,\n+\t\t.parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map,\n+\t},\n+\t.s[1] = {\n+\t\t.src_sel_shift = 0,\n+\t\t.parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map,\n+\t},\n+\t.p[0] = {\n+\t\t.pre_div_shift = 3,\n+\t\t.pre_div_width = 4,\n+\t},\n+\t.p[1] = {\n+\t\t.pre_div_shift = 3,\n+\t\t.pre_div_width = 4,\n+\t},\n+\t.mux_sel_bit = 0,\n+\t.freq_tbl = clk_tbl_ce5_a_clk,\n+\t.clkr = {\n+\t\t.enable_reg = 0x3d80,\n+\t\t.enable_mask = BIT(1),\n+\t\t.hw.init = &(struct clk_init_data){\n+\t\t\t.name = \"ce5_a_clk_src\",\n+\t\t\t.parent_names = gcc_pxo_pll8_pll0_pll14_pll18_pll11,\n+\t\t\t.num_parents = 6,\n+\t\t\t.ops = &clk_dyn_rcg_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch ce5_a_clk = {\n+\t.halt_reg = 0x3c20,\n+\t.halt_bit = 12,\n+\t.hwcg_reg = 0x3d8c,\n+\t.hwcg_bit = 6,\n+\t.clkr = {\n+\t\t.enable_reg = 0x3d8c,\n+\t\t.enable_mask = BIT(4),\n+\t\t.hw.init = &(struct clk_init_data){\n+\t\t\t.name = \"ce5_a_clk\",\n+\t\t\t.parent_names = (const char *[]){\n+\t\t\t\t\"ce5_a_clk_src\",\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.ops = &clk_branch_ops,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t},\n+\t},\n+};\n+\n+static const struct freq_tbl clk_tbl_ce5_h_clk[] = {\n+\t{ 160000000, P_PLL0, 5, 1, 1 },\n+\t{ 213200000, P_PLL11, 5, 1, 1 },\n+\t{ }\n+};\n+\n+static struct clk_dyn_rcg ce5_h_clk_src = {\n+\t.ns_reg[0] = 0x3c64,\n+\t.ns_reg[1] = 0x3c68,\n+\t.bank_reg = 0x3c60,\n+\t.s[0] = {\n+\t\t.src_sel_shift = 0,\n+\t\t.parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map,\n+\t},\n+\t.s[1] = {\n+\t\t.src_sel_shift = 0,\n+\t\t.parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map,\n+\t},\n+\t.p[0] = {\n+\t\t.pre_div_shift = 3,\n+\t\t.pre_div_width = 4,\n+\t},\n+\t.p[1] = {\n+\t\t.pre_div_shift = 3,\n+\t\t.pre_div_width = 4,\n+\t},\n+\t.mux_sel_bit = 0,\n+\t.freq_tbl = clk_tbl_ce5_h_clk,\n+\t.clkr = {\n+\t\t.enable_reg = 0x3c60,\n+\t\t.enable_mask = BIT(1),\n+\t\t.hw.init = &(struct clk_init_data){\n+\t\t\t.name = \"ce5_h_clk_src\",\n+\t\t\t.parent_names = gcc_pxo_pll8_pll0_pll14_pll18_pll11,\n+\t\t\t.num_parents = 6,\n+\t\t\t.ops = &clk_dyn_rcg_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch ce5_h_clk = {\n+\t.halt_reg = 0x3c20,\n+\t.halt_bit = 11,\n+\t.hwcg_reg = 0x3c6c,\n+\t.hwcg_bit = 6,\n+\t.clkr = {\n+\t\t.enable_reg = 0x3c6c,\n+\t\t.enable_mask = BIT(4),\n+\t\t.hw.init = &(struct clk_init_data){\n+\t\t\t.name = \"ce5_h_clk\",\n+\t\t\t.parent_names = (const char *[]){\n+\t\t\t\t\"ce5_h_clk_src\",\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.ops = &clk_branch_ops,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t},\n+\t},\n+};\n+\n static struct clk_regmap *gcc_ipq806x_clks[] = {\n \t[PLL0] = &pll0.clkr,\n \t[PLL0_VOTE] = &pll0_vote,\n@@ -2764,6 +3002,7 @@ static struct clk_regmap *gcc_ipq806x_cl\n \t[PLL4_VOTE] = &pll4_vote,\n \t[PLL8] = &pll8.clkr,\n \t[PLL8_VOTE] = &pll8_vote,\n+\t[PLL11] = &pll11.clkr,\n \t[PLL14] = &pll14.clkr,\n \t[PLL14_VOTE] = &pll14_vote,\n \t[PLL18] = &pll18.clkr,\n@@ -2878,6 +3117,12 @@ static struct clk_regmap *gcc_ipq806x_cl\n \t[PLL9] = &hfpll0.clkr,\n \t[PLL10] = &hfpll1.clkr,\n \t[PLL12] = &hfpll_l2.clkr,\n+\t[CE5_A_CLK_SRC] = &ce5_a_clk_src.clkr,\n+\t[CE5_A_CLK] = &ce5_a_clk.clkr,\n+\t[CE5_H_CLK_SRC] = &ce5_h_clk_src.clkr,\n+\t[CE5_H_CLK] = &ce5_h_clk.clkr,\n+\t[CE5_CORE_CLK_SRC] = &ce5_core_src.clkr,\n+\t[CE5_CORE_CLK] = &ce5_core_clk.clkr,\n };\n \n static const struct qcom_reset_map gcc_ipq806x_resets[] = {\n@@ -3009,6 +3254,11 @@ static const struct qcom_reset_map gcc_i\n \t[GMAC_CORE3_RESET] = { 0x3cfc, 0 },\n \t[GMAC_CORE4_RESET] = { 0x3d1c, 0 },\n \t[GMAC_AHB_RESET] = { 0x3e24, 0 },\n+\t[CRYPTO_ENG1_RESET] = { 0x3e00, 0},\n+\t[CRYPTO_ENG2_RESET] = { 0x3e04, 0},\n+\t[CRYPTO_ENG3_RESET] = { 0x3e08, 0},\n+\t[CRYPTO_ENG4_RESET] = { 0x3e0c, 0},\n+\t[CRYPTO_AHB_RESET] = { 0x3e10, 0},\n \t[NSS_CH0_RST_RX_CLK_N_RESET] = { 0x3b60, 0 },\n \t[NSS_CH0_RST_TX_CLK_N_RESET] = { 0x3b60, 1 },\n \t[NSS_CH0_RST_RX_125M_N_RESET] = { 0x3b60, 2 },\n--- a/include/dt-bindings/clock/qcom,gcc-ipq806x.h\n+++ b/include/dt-bindings/clock/qcom,gcc-ipq806x.h\n@@ -240,7 +240,7 @@\n #define PLL14\t\t\t\t\t232\n #define PLL14_VOTE\t\t\t\t233\n #define PLL18\t\t\t\t\t234\n-#define CE5_SRC\t\t\t\t\t235\n+#define CE5_A_CLK\t\t\t\t235\n #define CE5_H_CLK\t\t\t\t236\n #define CE5_CORE_CLK\t\t\t\t237\n #define CE3_SLEEP_CLK\t\t\t\t238\n@@ -283,5 +283,8 @@\n #define EBI2_AON_CLK\t\t\t\t281\n #define NSSTCM_CLK_SRC\t\t\t\t282\n #define NSSTCM_CLK\t\t\t\t283\n+#define CE5_A_CLK_SRC\t\t\t\t285\n+#define CE5_H_CLK_SRC\t\t\t\t286\n+#define CE5_CORE_CLK_SRC\t\t\t287\n \n #endif\n--- a/include/dt-bindings/reset/qcom,gcc-ipq806x.h\n+++ b/include/dt-bindings/reset/qcom,gcc-ipq806x.h\n@@ -163,5 +163,10 @@\n #define NSS_CAL_PRBS_RST_N_RESET\t\t\t154\n #define NSS_LCKDT_RST_N_RESET\t\t\t\t155\n #define NSS_SRDS_N_RESET\t\t\t\t156\n+#define CRYPTO_ENG1_RESET\t\t\t\t157\n+#define CRYPTO_ENG2_RESET\t\t\t\t158\n+#define CRYPTO_ENG3_RESET\t\t\t\t159\n+#define CRYPTO_ENG4_RESET\t\t\t\t160\n+#define CRYPTO_AHB_RESET\t\t\t\t161\n \n #endif\n"
  },
  {
    "path": "target/linux/ipq806x/patches-5.10/098-1-cpufreq-add-Krait-dedicated-scaling-driver.patch",
    "content": "From cc41a266280cad0b55319e614167c88dff344248 Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Sat, 22 Feb 2020 16:33:10 +0100\nSubject: [PATCH 1/8] cpufreq: add Krait dedicated scaling driver\n\nThis new driver is based on generic cpufreq-dt driver.\nKrait SoCs have 2-4 cpu and one shared L2 cache that can\noperate at different frequency based on the maximum cpu clk\nacross all core.\nL2 frequency and voltage are scaled on every frequency change\nif needed. On Krait SoCs is present a bug that can cause\ntransition problem between frequency bin, to workaround this\non more than one transition, the L2 frequency is first set to the\nbase rate and then to the target rate.\nThe L2 frequency use the OPP framework and use the opp-level\nbindings to link the l2 freq to different cpu freq. This is needed\nas the Krait l2 clk are note mapped 1:1 to the core clks and some\nof the l2 clk is set based on a range of the cpu clks. If the driver\nfind a broken config (for example no opp-level set) the l2 scaling is\nskipped.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\n---\n drivers/cpufreq/Kconfig.arm          |  14 +-\n drivers/cpufreq/Makefile             |   2 +\n drivers/cpufreq/qcom-cpufreq-krait.c | 589 +++++++++++++++++++++++++++\n 3 files changed, 604 insertions(+), 1 deletion(-)\n create mode 100644 drivers/cpufreq/qcom-cpufreq-krait.c\n\n--- a/drivers/cpufreq/Kconfig.arm\n+++ b/drivers/cpufreq/Kconfig.arm\n@@ -150,6 +150,18 @@ config ARM_QCOM_CPUFREQ_HW\n \t  The driver implements the cpufreq interface for this HW engine.\n \t  Say Y if you want to support CPUFreq HW.\n \n+config ARM_QCOM_CPUFREQ_KRAIT\n+\ttristate \"CPU Frequency scaling support for Krait SoCs\"\n+\tdepends on ARCH_QCOM || COMPILE_TEST\n+\tselect PM_OPP\n+\tselect ARM_QCOM_CPUFREQ_NVMEM\n+\thelp\n+\t  This adds the CPUFreq driver for Qualcomm Krait SoC based boards.\n+\t  This scale the cache clk and regulator based on the different cpu\n+\t  clks when scaling the different cores clk.\n+\n+\t  If in doubt, say N.\n+\n config ARM_RASPBERRYPI_CPUFREQ\n \ttristate \"Raspberry Pi cpufreq support\"\n \tdepends on CLK_RASPBERRYPI || COMPILE_TEST\n@@ -339,4 +351,4 @@ config ARM_PXA2xx_CPUFREQ\n \thelp\n \t  This add the CPUFreq driver support for Intel PXA2xx SOCs.\n \n-\t  If in doubt, say N.\n+\t  If in doubt, say N.\n\\ No newline at end of file\n--- a/drivers/cpufreq/Makefile\n+++ b/drivers/cpufreq/Makefile\n@@ -63,6 +63,7 @@ obj-$(CONFIG_ARM_PXA2xx_CPUFREQ)\t+= pxa2\n obj-$(CONFIG_PXA3xx)\t\t\t+= pxa3xx-cpufreq.o\n obj-$(CONFIG_ARM_QCOM_CPUFREQ_HW)\t+= qcom-cpufreq-hw.o\n obj-$(CONFIG_ARM_QCOM_CPUFREQ_NVMEM)\t+= qcom-cpufreq-nvmem.o\n+obj-$(CONFIG_ARM_QCOM_CPUFREQ_KRAIT)\t+= qcom-cpufreq-krait.o\n obj-$(CONFIG_ARM_RASPBERRYPI_CPUFREQ) \t+= raspberrypi-cpufreq.o\n obj-$(CONFIG_ARM_S3C2410_CPUFREQ)\t+= s3c2410-cpufreq.o\n obj-$(CONFIG_ARM_S3C2412_CPUFREQ)\t+= s3c2412-cpufreq.o\n@@ -86,6 +87,7 @@ obj-$(CONFIG_ARM_TEGRA186_CPUFREQ)\t+= te\n obj-$(CONFIG_ARM_TEGRA194_CPUFREQ)\t+= tegra194-cpufreq.o\n obj-$(CONFIG_ARM_TI_CPUFREQ)\t\t+= ti-cpufreq.o\n obj-$(CONFIG_ARM_VEXPRESS_SPC_CPUFREQ)\t+= vexpress-spc-cpufreq.o\n+obj-$(CONFIG_ARM_KRAIT_CPUFREQ)\t\t+= krait-cpufreq.o\n \n \n ##################################################################################\n--- /dev/null\n+++ b/drivers/cpufreq/qcom-cpufreq-krait.c\n@@ -0,0 +1,603 @@\n+// SPDX-License-Identifier: GPL-2.0\n+\n+#define pr_fmt(fmt) KBUILD_MODNAME \": \" fmt\n+\n+#include <linux/clk.h>\n+#include <linux/cpu.h>\n+#include <linux/cpufreq.h>\n+#include <linux/cpumask.h>\n+#include <linux/err.h>\n+#include <linux/module.h>\n+#include <linux/of.h>\n+#include <linux/of_device.h>\n+#include <linux/pm_opp.h>\n+#include <linux/platform_device.h>\n+#include <linux/regulator/consumer.h>\n+#include <linux/slab.h>\n+#include <linux/thermal.h>\n+\n+#include \"cpufreq-dt.h\"\n+\n+static struct platform_device *l2_pdev;\n+\n+struct private_data {\n+\tstruct opp_table *opp_table;\n+\tstruct device *cpu_dev;\n+\tconst char *reg_name;\n+\tbool have_static_opps;\n+};\n+\n+static int set_target(struct cpufreq_policy *policy, unsigned int index)\n+{\n+\tstruct private_data *priv = policy->driver_data;\n+\tunsigned long freq = policy->freq_table[index].frequency;\n+\tunsigned long target_freq = freq * 1000;\n+\tstruct dev_pm_opp *opp;\n+\tunsigned int level;\n+\tint cpu, ret;\n+\n+\tif (l2_pdev) {\n+\t\tint policy_cpu = policy->cpu;\n+\n+\t\t/* find the max freq across all core */\n+\t\tfor_each_present_cpu(cpu)\n+\t\t\tif (cpu != policy_cpu)\n+\t\t\t\ttarget_freq = max(\n+\t\t\t\t\ttarget_freq,\n+\t\t\t\t\t(unsigned long)cpufreq_quick_get(cpu));\n+\n+\t\topp = dev_pm_opp_find_freq_exact(priv->cpu_dev, target_freq,\n+\t\t\t\t\t\t true);\n+\t\tif (IS_ERR(opp)) {\n+\t\t\tdev_err(&l2_pdev->dev, \"failed to find OPP for %ld\\n\",\n+\t\t\t\ttarget_freq);\n+\t\t\treturn PTR_ERR(opp);\n+\t\t}\n+\t\tlevel = dev_pm_opp_get_level(opp);\n+\t\tdev_pm_opp_put(opp);\n+\n+\t\t/*\n+\t\t * Hardware constraint:\n+\t\t * Krait CPU cannot operate at 384MHz with L2 at 1Ghz.\n+\t\t * Assume index 0 with the idle freq and level > 0 as \n+\t\t * any L2 freq > 384MHz.\n+\t\t * Skip CPU freq change in this corner case.\n+\t\t */\n+\t\tif (unlikely(index == 0 && level != 0)) {\n+\t\t\tdev_err(priv->cpu_dev, \"Krait CPU can't operate at idle freq with L2 at 1GHz\");\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\n+\t\topp = dev_pm_opp_find_level_exact(&l2_pdev->dev, level);\n+\t\tif (IS_ERR(opp)) {\n+\t\t\tdev_err(&l2_pdev->dev,\n+\t\t\t\t\"failed to find level OPP for %d\\n\", level);\n+\t\t\treturn PTR_ERR(opp);\n+\t\t}\n+\t\ttarget_freq = dev_pm_opp_get_freq(opp);\n+\t\tdev_pm_opp_put(opp);\n+\n+\t\tret = dev_pm_opp_set_rate(&l2_pdev->dev, target_freq);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\t}\n+\n+\tret = dev_pm_opp_set_rate(priv->cpu_dev, freq * 1000);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tarch_set_freq_scale(policy->related_cpus, freq,\n+\t\t\t    policy->cpuinfo.max_freq);\n+\n+\treturn 0;\n+}\n+\n+/*\n+ * An earlier version of opp-v1 bindings used to name the regulator\n+ * \"cpu0-supply\", we still need to handle that for backwards compatibility.\n+ */\n+static const char *find_supply_name(struct device *dev)\n+{\n+\tstruct device_node *np;\n+\tstruct property *pp;\n+\tint cpu = dev->id;\n+\tconst char *name = NULL;\n+\n+\tnp = of_node_get(dev->of_node);\n+\n+\t/* This must be valid for sure */\n+\tif (WARN_ON(!np))\n+\t\treturn NULL;\n+\n+\t/* Try \"cpu0\" for older DTs */\n+\tif (!cpu) {\n+\t\tpp = of_find_property(np, \"cpu0-supply\", NULL);\n+\t\tif (pp) {\n+\t\t\tname = \"cpu0\";\n+\t\t\tgoto node_put;\n+\t\t}\n+\t}\n+\n+\tpp = of_find_property(np, \"cpu-supply\", NULL);\n+\tif (pp) {\n+\t\tname = \"cpu\";\n+\t\tgoto node_put;\n+\t}\n+\n+\tdev_dbg(dev, \"no regulator for cpu%d\\n\", cpu);\n+node_put:\n+\tof_node_put(np);\n+\treturn name;\n+}\n+\n+static int resources_available(void)\n+{\n+\tstruct device *cpu_dev;\n+\tstruct regulator *cpu_reg;\n+\tstruct clk *cpu_clk;\n+\tint ret = 0;\n+\tconst char *name;\n+\n+\tcpu_dev = get_cpu_device(0);\n+\tif (!cpu_dev) {\n+\t\tpr_err(\"failed to get cpu0 device\\n\");\n+\t\treturn -ENODEV;\n+\t}\n+\n+\tcpu_clk = clk_get(cpu_dev, NULL);\n+\tret = PTR_ERR_OR_ZERO(cpu_clk);\n+\tif (ret) {\n+\t\t/*\n+\t\t * If cpu's clk node is present, but clock is not yet\n+\t\t * registered, we should try defering probe.\n+\t\t */\n+\t\tif (ret == -EPROBE_DEFER)\n+\t\t\tdev_dbg(cpu_dev, \"clock not ready, retry\\n\");\n+\t\telse\n+\t\t\tdev_err(cpu_dev, \"failed to get clock: %d\\n\", ret);\n+\n+\t\treturn ret;\n+\t}\n+\n+\tclk_put(cpu_clk);\n+\n+\tname = find_supply_name(cpu_dev);\n+\t/* Platform doesn't require regulator */\n+\tif (!name)\n+\t\treturn 0;\n+\n+\tcpu_reg = regulator_get_optional(cpu_dev, name);\n+\tret = PTR_ERR_OR_ZERO(cpu_reg);\n+\tif (ret) {\n+\t\t/*\n+\t\t * If cpu's regulator supply node is present, but regulator is\n+\t\t * not yet registered, we should try defering probe.\n+\t\t */\n+\t\tif (ret == -EPROBE_DEFER)\n+\t\t\tdev_dbg(cpu_dev, \"cpu0 regulator not ready, retry\\n\");\n+\t\telse\n+\t\t\tdev_dbg(cpu_dev, \"no regulator for cpu0: %d\\n\", ret);\n+\n+\t\treturn ret;\n+\t}\n+\n+\tregulator_put(cpu_reg);\n+\treturn 0;\n+}\n+\n+static int cpufreq_init(struct cpufreq_policy *policy)\n+{\n+\tstruct cpufreq_frequency_table *freq_table;\n+\tstruct opp_table *opp_table = NULL;\n+\tunsigned int transition_latency;\n+\tstruct private_data *priv;\n+\tstruct device *cpu_dev;\n+\tbool fallback = false;\n+\tstruct clk *cpu_clk;\n+\tconst char *name;\n+\tint ret;\n+\n+\tcpu_dev = get_cpu_device(policy->cpu);\n+\tif (!cpu_dev) {\n+\t\tpr_err(\"failed to get cpu%d device\\n\", policy->cpu);\n+\t\treturn -ENODEV;\n+\t}\n+\n+\tcpu_clk = clk_get(cpu_dev, NULL);\n+\tif (IS_ERR(cpu_clk)) {\n+\t\tret = PTR_ERR(cpu_clk);\n+\t\tdev_err(cpu_dev, \"%s: failed to get clk: %d\\n\", __func__, ret);\n+\t\treturn ret;\n+\t}\n+\n+\t/* Get OPP-sharing information from \"operating-points-v2\" bindings */\n+\tret = dev_pm_opp_of_get_sharing_cpus(cpu_dev, policy->cpus);\n+\tif (ret) {\n+\t\tif (ret != -ENOENT)\n+\t\t\tgoto out_put_clk;\n+\n+\t\t/*\n+\t\t * operating-points-v2 not supported, fallback to old method of\n+\t\t * finding shared-OPPs for backward compatibility if the\n+\t\t * platform hasn't set sharing CPUs.\n+\t\t */\n+\t\tif (dev_pm_opp_get_sharing_cpus(cpu_dev, policy->cpus))\n+\t\t\tfallback = true;\n+\t}\n+\n+\t/*\n+\t * OPP layer will be taking care of regulators now, but it needs to know\n+\t * the name of the regulator first.\n+\t */\n+\tname = find_supply_name(cpu_dev);\n+\tif (name) {\n+\t\topp_table = dev_pm_opp_set_regulators(cpu_dev, &name, 1);\n+\t\tif (IS_ERR(opp_table)) {\n+\t\t\tret = PTR_ERR(opp_table);\n+\t\t\tdev_err(cpu_dev,\n+\t\t\t\t\"Failed to set regulator for cpu%d: %d\\n\",\n+\t\t\t\tpolicy->cpu, ret);\n+\t\t\tgoto out_put_clk;\n+\t\t}\n+\t}\n+\n+\tpriv = kzalloc(sizeof(*priv), GFP_KERNEL);\n+\tif (!priv) {\n+\t\tret = -ENOMEM;\n+\t\tgoto out_put_regulator;\n+\t}\n+\n+\tpriv->reg_name = name;\n+\tpriv->opp_table = opp_table;\n+\n+\t/*\n+\t * Initialize OPP tables for all policy->cpus. They will be shared by\n+\t * all CPUs which have marked their CPUs shared with OPP bindings.\n+\t *\n+\t * For platforms not using operating-points-v2 bindings, we do this\n+\t * before updating policy->cpus. Otherwise, we will end up creating\n+\t * duplicate OPPs for policy->cpus.\n+\t *\n+\t * OPPs might be populated at runtime, don't check for error here\n+\t */\n+\tif (!dev_pm_opp_of_cpumask_add_table(policy->cpus))\n+\t\tpriv->have_static_opps = true;\n+\n+\t/*\n+\t * But we need OPP table to function so if it is not there let's\n+\t * give platform code chance to provide it for us.\n+\t */\n+\tret = dev_pm_opp_get_opp_count(cpu_dev);\n+\tif (ret <= 0) {\n+\t\tdev_dbg(cpu_dev, \"OPP table is not ready, deferring probe\\n\");\n+\t\tret = -EPROBE_DEFER;\n+\t\tgoto out_free_opp;\n+\t}\n+\n+\tif (fallback) {\n+\t\tcpumask_setall(policy->cpus);\n+\n+\t\t/*\n+\t\t * OPP tables are initialized only for policy->cpu, do it for\n+\t\t * others as well.\n+\t\t */\n+\t\tret = dev_pm_opp_set_sharing_cpus(cpu_dev, policy->cpus);\n+\t\tif (ret)\n+\t\t\tdev_err(cpu_dev,\n+\t\t\t\t\"%s: failed to mark OPPs as shared: %d\\n\",\n+\t\t\t\t__func__, ret);\n+\t}\n+\n+\tret = dev_pm_opp_init_cpufreq_table(cpu_dev, &freq_table);\n+\tif (ret) {\n+\t\tdev_err(cpu_dev, \"failed to init cpufreq table: %d\\n\", ret);\n+\t\tgoto out_free_opp;\n+\t}\n+\n+\tpriv->cpu_dev = cpu_dev;\n+\n+\tpolicy->driver_data = priv;\n+\tpolicy->clk = cpu_clk;\n+\tpolicy->freq_table = freq_table;\n+\n+\tpolicy->suspend_freq = dev_pm_opp_get_suspend_opp_freq(cpu_dev) / 1000;\n+\n+\ttransition_latency = dev_pm_opp_get_max_transition_latency(cpu_dev);\n+\tif (!transition_latency)\n+\t\ttransition_latency = CPUFREQ_ETERNAL;\n+\n+\tpolicy->cpuinfo.transition_latency = transition_latency;\n+\tpolicy->dvfs_possible_from_any_cpu = true;\n+\n+\tdev_pm_opp_of_register_em(cpu_dev, policy->cpus);\n+\n+\treturn 0;\n+\n+out_free_opp:\n+\tif (priv->have_static_opps)\n+\t\tdev_pm_opp_of_cpumask_remove_table(policy->cpus);\n+\tkfree(priv);\n+out_put_regulator:\n+\tif (name)\n+\t\tdev_pm_opp_put_regulators(opp_table);\n+out_put_clk:\n+\tclk_put(cpu_clk);\n+\n+\treturn ret;\n+}\n+\n+static int cpufreq_online(struct cpufreq_policy *policy)\n+{\n+\t/* We did light-weight tear down earlier, nothing to do here */\n+\treturn 0;\n+}\n+\n+static int cpufreq_offline(struct cpufreq_policy *policy)\n+{\n+\t/*\n+\t * Preserve policy->driver_data and don't free resources on light-weight\n+\t * tear down.\n+\t */\n+\treturn 0;\n+}\n+\n+static int cpufreq_exit(struct cpufreq_policy *policy)\n+{\n+\tstruct private_data *priv = policy->driver_data;\n+\n+\tdev_pm_opp_free_cpufreq_table(priv->cpu_dev, &policy->freq_table);\n+\tif (priv->have_static_opps)\n+\t\tdev_pm_opp_of_cpumask_remove_table(policy->related_cpus);\n+\tif (priv->reg_name)\n+\t\tdev_pm_opp_put_regulators(priv->opp_table);\n+\n+\tclk_put(policy->clk);\n+\tkfree(priv);\n+\n+\treturn 0;\n+}\n+\n+static struct cpufreq_driver krait_cpufreq_driver = {\n+\t.flags = CPUFREQ_STICKY | CPUFREQ_NEED_INITIAL_FREQ_CHECK |\n+\t\t CPUFREQ_IS_COOLING_DEV,\n+\t.verify = cpufreq_generic_frequency_table_verify,\n+\t.target_index = set_target,\n+\t.get = cpufreq_generic_get,\n+\t.init = cpufreq_init,\n+\t.exit = cpufreq_exit,\n+\t.online = cpufreq_online,\n+\t.offline = cpufreq_offline,\n+\t.name = \"krait-cpufreq\",\n+\t.suspend = cpufreq_generic_suspend,\n+};\n+\n+struct krait_data {\n+\tunsigned long idle_freq;\n+\tbool regulator_enabled;\n+};\n+\n+static int krait_cache_set_opp(struct dev_pm_set_opp_data *data)\n+{\n+\tunsigned long old_freq = data->old_opp.rate, freq = data->new_opp.rate;\n+\tstruct dev_pm_opp_supply *supply = &data->new_opp.supplies[0];\n+\tstruct regulator *reg = data->regulators[0];\n+\tstruct clk *clk = data->clk;\n+\tstruct krait_data *kdata;\n+\tunsigned long idle_freq;\n+\tint ret;\n+\n+\tkdata = (struct krait_data *)dev_get_drvdata(data->dev);\n+\tidle_freq = kdata->idle_freq;\n+\n+\t/* Scaling up? Scale voltage before frequency */\n+\tif (freq >= old_freq) {\n+\t\tret = regulator_set_voltage_triplet(reg, supply->u_volt_min,\n+\t\t\t\t\t\t    supply->u_volt,\n+\t\t\t\t\t\t    supply->u_volt_max);\n+\t\tif (ret)\n+\t\t\tgoto exit;\n+\t}\n+\n+\t/*\n+\t * Set to idle bin if switching from normal to high bin\n+\t * or vice versa. It has been notice that a bug is triggered\n+\t * in cache scaling when more than one bin is scaled, to fix\n+\t * this we first need to transition to the base rate and then\n+\t * to target rate\n+\t */\n+\tif (likely(freq != idle_freq && old_freq != idle_freq)) {\n+\t\tret = clk_set_rate(clk, idle_freq);\n+\t\tif (ret)\n+\t\t\tgoto exit;\n+\t}\n+\n+\tret = clk_set_rate(clk, freq);\n+\tif (ret)\n+\t\tgoto exit;\n+\n+\t/* Scaling down? Scale voltage after frequency */\n+\tif (freq < old_freq) {\n+\t\tret = regulator_set_voltage_triplet(reg, supply->u_volt_min,\n+\t\t\t\t\t\t    supply->u_volt,\n+\t\t\t\t\t\t    supply->u_volt_max);\n+\t}\n+\n+\tif (unlikely(!kdata->regulator_enabled)) {\n+\t\tret = regulator_enable(reg);\n+\t\tif (ret < 0)\n+\t\t\tdev_warn(data->dev, \"Failed to enable regulator: %d\", ret);\n+\t\telse\n+\t\t\tkdata->regulator_enabled = true;\n+\t}\n+\n+exit:\n+\treturn ret;\n+};\n+\n+static int krait_cache_probe(struct platform_device *pdev)\n+{\n+\tstruct device *dev = &pdev->dev;\n+\tstruct krait_data *data;\n+\tstruct opp_table *table;\n+\tstruct dev_pm_opp *opp;\n+\tstruct device *cpu_dev;\n+\tint ret;\n+\n+\tdata = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);\n+\tif (!data)\n+\t\treturn -ENOMEM;\n+\n+\ttable = dev_pm_opp_set_regulators(dev, (const char *[]){ \"l2\" }, 1);\n+\tif (IS_ERR(table)) {\n+\t\tret = PTR_ERR(table);\n+\t\tif (ret != -EPROBE_DEFER)\n+\t\t\tdev_err(dev, \"failed to set regulators %d\\n\", ret);\n+\n+\t\treturn ret;\n+\t}\n+\n+\tret = PTR_ERR_OR_ZERO(\n+\t\tdev_pm_opp_register_set_opp_helper(dev, krait_cache_set_opp));\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = dev_pm_opp_of_add_table(dev);\n+\tif (ret) {\n+\t\tdev_err(dev, \"failed to parse L2 freq thresholds\\n\");\n+\t\treturn ret;\n+\t}\n+\n+\topp = dev_pm_opp_find_freq_ceil(dev, &data->idle_freq);\n+\tdev_pm_opp_put(opp);\n+\n+\t/*\n+\t * Check opp-level configuration\n+\t * At least 2 level must be set or the cache will always be scaled\n+\t * the idle freq causing some performance problem\n+\t *\n+\t * In case of invalid configuration, the l2 scaling is skipped\n+\t */\n+\tcpu_dev = get_cpu_device(0);\n+\tif (!cpu_dev) {\n+\t\tpr_err(\"failed to get cpu0 device\\n\");\n+\t\treturn -ENODEV;\n+\t}\n+\n+\t/*\n+\t * Check if we have at least opp-level 1, 0 should always be set to\n+\t * the idle freq\n+\t */\n+\topp = dev_pm_opp_find_level_exact(dev, 1);\n+\tif (IS_ERR(opp)) {\n+\t\tdev_err(dev,\n+\t\t\t\"Invalid configuration found of l2 opp. Can't find opp-level 1\");\n+\t\tgoto invalid_conf;\n+\t}\n+\tdev_pm_opp_put(opp);\n+\n+\t/*\n+\t * Check if we have at least opp-level 1 in the cpu opp, 0 should always\n+\t * be set to the idle freq\n+\t */\n+\topp = dev_pm_opp_find_level_exact(cpu_dev, 1);\n+\tif (IS_ERR(opp)) {\n+\t\tdev_err(dev,\n+\t\t\t\"Invalid configuration found of cpu opp. Can't find opp-level 1\");\n+\t\tgoto invalid_conf;\n+\t}\n+\tdev_pm_opp_put(opp);\n+\n+\tplatform_set_drvdata(pdev, data);\n+\n+\t/* The l2 scaling is enabled by linking the cpufreq driver */\n+\tl2_pdev = pdev;\n+\n+\treturn 0;\n+\n+invalid_conf:\n+\tdev_pm_opp_remove_table(dev);\n+\tdev_pm_opp_put_regulators(table);\n+\tdev_pm_opp_unregister_set_opp_helper(table);\n+\n+\treturn -EINVAL;\n+};\n+\n+static int krait_cache_remove(struct platform_device *pdev)\n+{\n+\tstruct device *dev = &pdev->dev;\n+\tstruct opp_table *table = dev_pm_opp_get_opp_table(dev);\n+\n+\tdev_pm_opp_remove_table(dev);\n+\tdev_pm_opp_put_regulators(table);\n+\tdev_pm_opp_unregister_set_opp_helper(table);\n+\n+\treturn 0;\n+};\n+\n+static const struct of_device_id krait_cache_match_table[] = {\n+\t{ .compatible = \"qcom,krait-cache\" },\n+\t{}\n+};\n+\n+static struct platform_driver krait_cache_driver = {\n+\t.driver = {\n+\t\t.name\t= \"krait-cache\",\n+\t\t.of_match_table = krait_cache_match_table,\n+\t},\n+\t.probe\t\t= krait_cache_probe,\n+\t.remove\t\t= krait_cache_remove,\n+};\n+module_platform_driver(krait_cache_driver);\n+\n+static int krait_cpufreq_probe(struct platform_device *pdev)\n+{\n+\tstruct cpufreq_dt_platform_data *data = dev_get_platdata(&pdev->dev);\n+\tint ret;\n+\n+\t/*\n+\t * All per-cluster (CPUs sharing clock/voltages) initialization is done\n+\t * from ->init(). In probe(), we just need to make sure that clk and\n+\t * regulators are available. Else defer probe and retry.\n+\t *\n+\t * FIXME: Is checking this only for CPU0 sufficient ?\n+\t */\n+\tret = resources_available();\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tif (data) {\n+\t\tif (data->have_governor_per_policy)\n+\t\t\tkrait_cpufreq_driver.flags |=\n+\t\t\t\tCPUFREQ_HAVE_GOVERNOR_PER_POLICY;\n+\n+\t\tkrait_cpufreq_driver.resume = data->resume;\n+\t\tif (data->suspend)\n+\t\t\tkrait_cpufreq_driver.suspend = data->suspend;\n+\t}\n+\n+\tret = cpufreq_register_driver(&krait_cpufreq_driver);\n+\tif (ret)\n+\t\tdev_err(&pdev->dev, \"failed register driver: %d\\n\", ret);\n+\n+\treturn ret;\n+}\n+\n+static int krait_cpufreq_remove(struct platform_device *pdev)\n+{\n+\tcpufreq_unregister_driver(&krait_cpufreq_driver);\n+\treturn 0;\n+}\n+\n+static struct platform_driver krait_cpufreq_platdrv = {\n+\t.driver = {\n+\t\t.name\t= \"krait-cpufreq\",\n+\t},\n+\t.probe\t\t= krait_cpufreq_probe,\n+\t.remove\t\t= krait_cpufreq_remove,\n+};\n+module_platform_driver(krait_cpufreq_platdrv);\n+\n+MODULE_ALIAS(\"platform:krait-cpufreq\");\n+MODULE_AUTHOR(\"Ansuel Smith <ansuelsmth@gmail.com>\");\n+MODULE_DESCRIPTION(\"Dedicated Krait SoC cpufreq driver\");\n+MODULE_LICENSE(\"GPL\");\n"
  },
  {
    "path": "target/linux/ipq806x/patches-5.10/098-2-Documentation-cpufreq-add-qcom-krait-cpufreq-binding.patch",
    "content": "From c9ecd920324a647bf1f2b47f771c8f599cc7b551 Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Sat, 22 Feb 2020 18:02:17 +0100\nSubject: [PATCH 2/8] Documentation: cpufreq: add qcom,krait-cache bindings\n\nDocument dedicated cpufreq for Krait CPUs.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\n---\n .../bindings/cpufreq/qcom-cpufreq-krait.yaml  | 221 ++++++++++++++++++\n 1 file changed, 221 insertions(+)\n create mode 100644 Documentation/devicetree/bindings/cpufreq/qcom-cpufreq-krait.yaml\n\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/cpufreq/qcom-cpufreq-krait.yaml\n@@ -0,0 +1,221 @@\n+# SPDX-License-Identifier: GPL-2.0\n+%YAML 1.2\n+---\n+$id: http://devicetree.org/schemas/cpufreq/qcom-cpufreq-krait.yaml#\n+$schema: http://devicetree.org/meta-schemas/core.yaml#\n+\n+title: CPU Frequency scaling driver for Krait SoCs\n+\n+maintainers:\n+  - Ansuel Smith <ansuelsmth@gmail.com>\n+\n+description: |\n+  The krait cpufreq driver is a dedicated frequency scaling driver\n+  based on cpufreq-dt generic driver that scale L2 cache and the\n+  cores. TEST\n+\n+  The L2 cache is scaled based on the max clk across all cores and\n+  the clock is decided based on the opp-level set in the device tree.\n+\n+  Different core freq can be linked to a specific l2 freq and the driver\n+  on frequency change will scale the core and the l2 clk based of the \n+  linked freq.\n+\n+  On Krait SoC is present a bug and on every L2 clk change the driver\n+  needs to set the clk to the idle freq before changing it to the new value.\n+\n+  This requires the qcom cpufreq nvmem driver to parse the different opp\n+  core clk and an additional opp table for the l2 scaling.\n+\n+  If the driver detect broken config (for example missing opp-level) the\n+  cpufreq driver skips the l2 scaling\n+\n+  Referring to this example opp-level can be used to link a range of cpu freq\n+  to a specific l2 freq:\n+    cpu opp freq 384000000 has opp-level 0\n+    l2 opp freq 384000000 has opp-level 0\n+    The driver will scale l2 to 384000000\n+\n+    cpu opp freq 600000000-1000000000 has opp-level 1\n+    l2 opp freq 1000000000 has opp-level 1\n+    The driver will scale l2 to 1000000000\n+\n+allOf:\n+  - $ref: /schemas/cache-controller.yaml#\n+\n+select:\n+  properties:\n+    compatible:\n+      items:\n+        - enum:\n+            - qcom,krait-cache\n+\n+  required:\n+    - compatible\n+\n+properties:\n+  compatible:\n+    items:\n+      - const: qcom,krait-cache\n+      - const: cache\n+\n+  cache-level:\n+    const: 2\n+\n+  clocks:\n+    maxItems: 1\n+\n+  clock-names:\n+    const: l2\n+\n+  l2-supply: true\n+\n+  operating-points-v2: true\n+\n+required:\n+  - compatible\n+  - cache-level\n+  - clocks\n+  - clock-names\n+  - l2-supply\n+  - operating-points-v2\n+\n+additionalProperties: false\n+\n+examples:\n+  - |\n+    cpus {\n+      #address-cells = <1>;\n+      #size-cells = <0>;\n+\n+      cpu0: cpu@0 {\n+        compatible = \"qcom,krait\";\n+        enable-method = \"qcom,kpss-acc-v1\";\n+        device_type = \"cpu\";\n+        reg = <0>;\n+        next-level-cache = <&L2>;\n+        qcom,acc = <&acc0>;\n+        qcom,saw = <&saw0>;\n+        clocks = <&kraitcc 0>, <&kraitcc 4>;\n+        clock-names = \"cpu\", \"l2\";\n+        clock-latency = <100000>;\n+        cpu-supply = <&smb208_s2a>;\n+        operating-points-v2 = <&opp_table0>;\n+        voltage-tolerance = <5>;\n+        cooling-min-state = <0>;\n+        cooling-max-state = <10>;\n+        #cooling-cells = <2>;\n+        cpu-idle-states = <&CPU_SPC>;\n+      };\n+\n+      /* ... */\n+\n+    };\n+\n+    opp_table0: opp_table0 {\n+      compatible = \"operating-points-v2-kryo-cpu\";\n+      nvmem-cells = <&speedbin_efuse>;\n+\n+      opp-384000000 {\n+        opp-hz = /bits/ 64 <384000000>;\n+        opp-microvolt-speed0-pvs0-v0 = <1000000>;\n+        opp-microvolt-speed0-pvs1-v0 = <925000>;\n+        opp-microvolt-speed0-pvs2-v0 = <875000>;\n+        opp-microvolt-speed0-pvs3-v0 = <800000>;\n+        opp-supported-hw = <0x1>;\n+        clock-latency-ns = <100000>;\n+        opp-level = <0>;\n+      };\n+\n+      opp-600000000 {\n+        opp-hz = /bits/ 64 <600000000>;\n+        opp-microvolt-speed0-pvs0-v0 = <1050000>;\n+        opp-microvolt-speed0-pvs1-v0 = <975000>;\n+        opp-microvolt-speed0-pvs2-v0 = <925000>;\n+        opp-microvolt-speed0-pvs3-v0 = <850000>;\n+        opp-supported-hw = <0x1>;\n+        clock-latency-ns = <100000>;\n+        opp-level = <1>;\n+      };\n+\n+      opp-800000000 {\n+        opp-hz = /bits/ 64 <800000000>;\n+        opp-microvolt-speed0-pvs0-v0 = <1100000>;\n+        opp-microvolt-speed0-pvs1-v0 = <1025000>;\n+        opp-microvolt-speed0-pvs2-v0 = <995000>;\n+        opp-microvolt-speed0-pvs3-v0 = <900000>;\n+        opp-supported-hw = <0x1>;\n+        clock-latency-ns = <100000>;\n+        opp-level = <1>;\n+      };\n+\n+      opp-1000000000 {\n+        opp-hz = /bits/ 64 <1000000000>;\n+        opp-microvolt-speed0-pvs0-v0 = <1150000>;\n+        opp-microvolt-speed0-pvs1-v0 = <1075000>;\n+        opp-microvolt-speed0-pvs2-v0 = <1025000>;\n+        opp-microvolt-speed0-pvs3-v0 = <950000>;\n+        opp-supported-hw = <0x1>;\n+        clock-latency-ns = <100000>;\n+        opp-level = <1>;\n+      };\n+\n+      opp-1200000000 {\n+        opp-hz = /bits/ 64 <1200000000>;\n+        opp-microvolt-speed0-pvs0-v0 = <1200000>;\n+        opp-microvolt-speed0-pvs1-v0 = <1125000>;\n+        opp-microvolt-speed0-pvs2-v0 = <1075000>;\n+        opp-microvolt-speed0-pvs3-v0 = <1000000>;\n+        opp-supported-hw = <0x1>;\n+        clock-latency-ns = <100000>;\n+        opp-level = <2>;\n+      };\n+\n+      opp-1400000000 {\n+        opp-hz = /bits/ 64 <1400000000>;\n+        opp-microvolt-speed0-pvs0-v0 = <1250000>;\n+        opp-microvolt-speed0-pvs1-v0 = <1175000>;\n+        opp-microvolt-speed0-pvs2-v0 = <1125000>;\n+        opp-microvolt-speed0-pvs3-v0 = <1050000>;\n+        opp-supported-hw = <0x1>;\n+        clock-latency-ns = <100000>;\n+        opp-level = <2>;\n+      };\n+    };\n+\n+    opp_table_l2: opp_table_l2 {\n+      compatible = \"operating-points-v2\";\n+\n+      opp-384000000 {\n+        opp-hz = /bits/ 64 <384000000>;\n+        opp-microvolt = <1100000>;\n+        clock-latency-ns = <100000>;\n+        opp-level = <0>;\n+      };\n+      opp-1000000000 {\n+        opp-hz = /bits/ 64 <1000000000>;\n+        opp-microvolt = <1100000>;\n+        clock-latency-ns = <100000>;\n+        opp-level = <1>;\n+      };\n+      opp-1200000000 {\n+        opp-hz = /bits/ 64 <1200000000>;\n+        opp-microvolt = <1150000>;\n+        clock-latency-ns = <100000>;\n+        opp-level = <2>;\n+      };\n+    };\n+\n+    soc {\n+      L2: l2-cache {\n+        compatible = \"qcom,krait-cache\", \"cache\";\n+        cache-level = <2>;\n+\n+        clocks = <&kraitcc 4>;\n+        clock-names = \"l2\";\n+        l2-supply = <&smb208_s1a>;\n+        operating-points-v2 = <&opp_table_l2>;\n+      };\n+    };\n+\n+...\n"
  },
  {
    "path": "target/linux/ipq806x/patches-5.10/098-3-add-fab-scaling-support-with-cpufreq.patch",
    "content": "--- a/drivers/clk/qcom/Makefile\n+++ b/drivers/clk/qcom/Makefile\n@@ -15,6 +15,7 @@ clk-qcom-$(CONFIG_KRAIT_CLOCKS) += clk-k\n clk-qcom-y += clk-hfpll.o\n clk-qcom-y += reset.o\n clk-qcom-$(CONFIG_QCOM_GDSC) += gdsc.o\n+clk-qcom-y += fab_scaling.o\n \n # Keep alphabetically sorted by config\n obj-$(CONFIG_APQ_GCC_8084) += gcc-apq8084.o\n--- /dev/null\n+++ b/drivers/clk/qcom/fab_scaling.c\n@@ -0,0 +1,172 @@\n+/*\n+ * Copyright (c) 2015, The Linux Foundation. All rights reserved.\n+ *\n+ * Permission to use, copy, modify, and/or distribute this software for any\n+ * purpose with or without fee is hereby granted, provided that the above\n+ * copyright notice and this permission notice appear in all copies.\n+ *\n+ * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n+ */\n+\n+#include <linux/kernel.h>\n+#include <linux/init.h>\n+#include <linux/module.h>\n+#include <linux/platform_device.h>\n+#include <linux/err.h>\n+#include <linux/io.h>\n+#include <linux/of.h>\n+#include <linux/of_device.h>\n+#include <linux/clk.h>\n+#include <linux/clk-provider.h>\n+#include <linux/slab.h>\n+#include <linux/fab_scaling.h>\n+\n+struct qcom_fab_scaling_data {\n+\tu32 fab_freq_high;\n+\tu32 fab_freq_nominal;\n+\tu32 cpu_freq_threshold;\n+\tstruct clk *apps_fab_clk;\n+\tstruct clk *ddr_fab_clk;\n+};\n+\n+static struct qcom_fab_scaling_data *drv_data;\n+\n+int scale_fabrics(unsigned long max_cpu_freq)\n+{\t\n+\tstruct clk *apps_fab_clk = drv_data->apps_fab_clk,\n+\t           *ddr_fab_clk = drv_data->ddr_fab_clk;\n+\tunsigned long target_freq, cur_freq;\n+\tint ret;\n+\n+\t/* Skip fab scaling if the driver is not ready */\n+\tif (!apps_fab_clk || !ddr_fab_clk)\n+\t\treturn 0;\n+\n+\tif (max_cpu_freq > drv_data->cpu_freq_threshold)\n+\t\ttarget_freq = drv_data->fab_freq_high;\n+\telse\n+\t\ttarget_freq = drv_data->fab_freq_nominal;\n+\n+\tcur_freq = clk_get_rate(ddr_fab_clk);\n+\n+\tif (target_freq != cur_freq) {\n+\t\tret = clk_set_rate(apps_fab_clk, target_freq);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\t\tret = clk_set_rate(ddr_fab_clk, target_freq);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\t}\n+\n+\treturn 0;\n+}\n+EXPORT_SYMBOL(scale_fabrics);\n+\n+static int ipq806x_fab_scaling_probe(struct platform_device *pdev)\n+{\n+\tstruct device_node *np = pdev->dev.of_node;\n+\tstruct clk *apps_fab_clk, *ddr_fab_clk;\n+\tint ret;\n+\n+\tif (!np)\n+\t\treturn -ENODEV;\n+\t\n+\tdrv_data = kzalloc(sizeof(*drv_data), GFP_KERNEL);\n+\tif (!drv_data)\n+\t\treturn -ENOMEM;\n+\n+\tif (of_property_read_u32(np, \"fab_freq_high\", &drv_data->fab_freq_high)) {\n+\t\tpr_err(\"FABRICS turbo freq not found. Using defaults...\\n\");\n+\t\tdrv_data->fab_freq_high = 533000000;\n+\t}\n+\n+\tif (of_property_read_u32(np, \"fab_freq_nominal\", &drv_data->fab_freq_nominal)) {\n+\t\tpr_err(\"FABRICS nominal freq not found. Using defaults...\\n\");\n+\t\tdrv_data->fab_freq_nominal = 400000000;\n+\t}\n+\n+\tif (of_property_read_u32(np, \"cpu_freq_threshold\", &drv_data->cpu_freq_threshold)) {\n+\t\tpr_err(\"FABRICS cpu freq threshold not found. Using defaults...\\n\");\n+\t\tdrv_data->cpu_freq_threshold = 1000000000;\n+\t}\n+\n+\tapps_fab_clk = devm_clk_get(&pdev->dev, \"apps-fab-clk\");\n+\tret = PTR_ERR_OR_ZERO(apps_fab_clk);\n+\tif (ret) {\n+\t\t/*\n+\t\t * If apps fab clk node is present, but clock is not yet\n+\t\t * registered, we should try defering probe.\n+\t\t */\n+\t\tif (ret != -EPROBE_DEFER) {\n+\t\t\tpr_err(\"Failed to get APPS FABRIC clock: %d\\n\", ret);\n+\t\t\tret = -ENODEV;\n+\t\t}\n+\t\tgoto err;\n+\t}\n+\n+\tclk_prepare_enable(apps_fab_clk);\n+\tclk_set_rate(apps_fab_clk, drv_data->fab_freq_high);\n+\tdrv_data->apps_fab_clk = apps_fab_clk;\n+\n+\tddr_fab_clk = devm_clk_get(&pdev->dev, \"ddr-fab-clk\");\n+\tret = PTR_ERR_OR_ZERO(ddr_fab_clk);\n+\tif (ret) {\n+\t\t/*\n+\t\t * If ddr fab clk node is present, but clock is not yet\n+\t\t * registered, we should try defering probe.\n+\t\t */\n+\t\tif (ret != -EPROBE_DEFER) {\n+\t\t\tpr_err(\"Failed to get DDR FABRIC clock: %d\\n\", ret);\n+\t\t\tddr_fab_clk = NULL;\n+\t\t\tret = -ENODEV;\n+\t\t}\n+\t\tgoto err;\n+\t}\n+\n+\tclk_prepare_enable(ddr_fab_clk);\n+\tclk_set_rate(ddr_fab_clk, drv_data->fab_freq_high);\n+\tdrv_data->ddr_fab_clk = ddr_fab_clk;\n+\n+\treturn 0;\n+err:\n+\tkfree(drv_data);\n+\treturn ret;\n+}\n+\n+static int ipq806x_fab_scaling_remove(struct platform_device *pdev)\n+{\n+\tkfree(drv_data);\n+\treturn 0;\n+}\n+\n+static const struct of_device_id fab_scaling_ipq806x_match_table[] = {\n+\t{ .compatible = \"qcom,fab-scaling\" },\n+\t{ }\n+};\n+\n+static struct platform_driver fab_scaling_ipq806x_driver = {\n+\t.probe\t\t= ipq806x_fab_scaling_probe,\n+\t.remove\t\t= ipq806x_fab_scaling_remove,\n+\t.driver\t\t= {\n+\t\t.name   = \"fab-scaling\",\n+\t\t.of_match_table = fab_scaling_ipq806x_match_table,\n+\t},\n+};\n+\n+static int __init fab_scaling_ipq806x_init(void)\n+{\n+\treturn platform_driver_register(&fab_scaling_ipq806x_driver);\n+}\n+late_initcall(fab_scaling_ipq806x_init);\n+\n+static void __exit fab_scaling_ipq806x_exit(void)\n+{\n+\tplatform_driver_unregister(&fab_scaling_ipq806x_driver);\n+}\n+module_exit(fab_scaling_ipq806x_exit);\n--- /dev/null\n+++ b/include/linux/fab_scaling.h\n@@ -0,0 +1,31 @@\n+/*\n+ * Copyright (c) 2015, The Linux Foundation. All rights reserved.\n+ *\n+ * Permission to use, copy, modify, and/or distribute this software for any\n+ * purpose with or without fee is hereby granted, provided that the above\n+ * copyright notice and this permission notice appear in all copies.\n+ *\n+ * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n+ */\n+\n+\n+#ifndef __FAB_SCALING_H\n+#define __FAB_SCALING_H\n+\n+/**\n+ * scale_fabrics - Scale DDR and APPS FABRICS\n+ *\n+ * This function monitors all the registered clocks and does APPS\n+ * and DDR FABRIC scaling based on the idle frequencies with which\n+ * it was registered.\n+ *\n+ */\n+int scale_fabrics(unsigned long max_cpu_freq);\n+\n+#endif\n--- a/drivers/cpufreq/qcom-cpufreq-krait.c\n+++ b/drivers/cpufreq/qcom-cpufreq-krait.c\n@@ -15,6 +15,7 @@\n #include <linux/regulator/consumer.h>\n #include <linux/slab.h>\n #include <linux/thermal.h>\n+#include <linux/fab_scaling.h>\n \n #include \"cpufreq-dt.h\"\n \n@@ -68,6 +69,13 @@ static int set_target(struct cpufreq_pol\n \t\t\treturn -EINVAL;\n \t\t}\n \n+\t\t/*\n+\t\t * Scale fabrics with max freq across all cores\n+\t\t */\n+\t\tret = scale_fabrics(target_freq);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\n \t\topp = dev_pm_opp_find_level_exact(&l2_pdev->dev, level);\n \t\tif (IS_ERR(opp)) {\n \t\t\tdev_err(&l2_pdev->dev,\n"
  },
  {
    "path": "target/linux/ipq806x/patches-5.10/099-1-mtd-nand-raw-qcom_nandc-add-boot_layout_mode-support.patch",
    "content": "From 6949d651e3be3ebbfedb6bbd5b541cfda6ee58a9 Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Wed, 10 Feb 2021 10:40:17 +0100\nSubject: [PATCH 1/2] mtd: nand: raw: qcom_nandc: add boot_layout_mode support\n\nipq806x nand have a special ecc configuration for the boot pages. The\nuse of the non-boot pages configuration on boot pages cause I/O error\nand can cause broken data written to the nand. Add support for this\nspecial configuration if the page to be read/write is in the size of the\nboot pages set by the dts.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\n---\n drivers/mtd/nand/raw/qcom_nandc.c | 82 +++++++++++++++++++++++++++++--\n 1 file changed, 77 insertions(+), 5 deletions(-)\n\n--- a/drivers/mtd/nand/raw/qcom_nandc.c\n+++ b/drivers/mtd/nand/raw/qcom_nandc.c\n@@ -158,6 +158,11 @@\n /* NAND_CTRL bits */\n #define\tBAM_MODE_EN\t\t\tBIT(0)\n \n+\n+#define UD_SIZE_BYTES_MASK\t(0x3ff << UD_SIZE_BYTES)\n+#define SPARE_SIZE_BYTES_MASK\t(0xf << SPARE_SIZE_BYTES)\n+#define ECC_NUM_DATA_BYTES_MASK\t(0x3ff << ECC_NUM_DATA_BYTES)\n+\n /*\n  * the NAND controller performs reads/writes with ECC in 516 byte chunks.\n  * the driver calls the chunks 'step' or 'codeword' interchangeably\n@@ -429,6 +434,13 @@ struct qcom_nand_controller {\n  * @cfg0, cfg1, cfg0_raw..:\tNANDc register configurations needed for\n  *\t\t\t\tecc/non-ecc mode for the current nand flash\n  *\t\t\t\tdevice\n+ *\n+ * @boot_pages_conf:\t\tkeep track of the current ecc configuration used by\n+ * \t\t\t\tthe driver for read/write operation. (boot pages\n+ * \t\t\t\thave different configuration than normal page)\n+ * @boot_pages:\t\t\tnumber of pages starting from 0 used as boot pages\n+ * \t\t\t\twhere the driver will use the boot pages ecc\n+ * \t\t\t\tconfiguration for read/write operation\n  */\n struct qcom_nand_host {\n \tstruct nand_chip chip;\n@@ -451,6 +463,9 @@ struct qcom_nand_host {\n \tu32 ecc_bch_cfg;\n \tu32 clrflashstatus;\n \tu32 clrreadstatus;\n+\n+\tbool boot_pages_conf;\n+\tu32 boot_pages;\n };\n \n /*\n@@ -459,12 +474,14 @@ struct qcom_nand_host {\n  * @ecc_modes - ecc mode for NAND\n  * @is_bam - whether NAND controller is using BAM\n  * @is_qpic - whether NAND CTRL is part of qpic IP\n+ * @has_boot_pages - whether NAND has different ecc settings for boot pages\n  * @dev_cmd_reg_start - NAND_DEV_CMD_* registers starting offset\n  */\n struct qcom_nandc_props {\n \tu32 ecc_modes;\n \tbool is_bam;\n \tbool is_qpic;\n+\tbool has_boot_pages;\n \tu32 dev_cmd_reg_start;\n };\n \n@@ -1603,7 +1620,7 @@ qcom_nandc_read_cw_raw(struct mtd_info *\n \tdata_size1 = mtd->writesize - host->cw_size * (ecc->steps - 1);\n \toob_size1 = host->bbm_size;\n \n-\tif (cw == (ecc->steps - 1)) {\n+\tif (cw == (ecc->steps - 1) && !host->boot_pages_conf) {\n \t\tdata_size2 = ecc->size - data_size1 -\n \t\t\t     ((ecc->steps - 1) * 4);\n \t\toob_size2 = (ecc->steps * 4) + host->ecc_bytes_hw +\n@@ -1684,7 +1701,7 @@ check_for_erased_page(struct qcom_nand_h\n \t}\n \n \tfor_each_set_bit(cw, &uncorrectable_cws, ecc->steps) {\n-\t\tif (cw == (ecc->steps - 1)) {\n+\t\tif (cw == (ecc->steps - 1) && !host->boot_pages_conf) {\n \t\t\tdata_size = ecc->size - ((ecc->steps - 1) * 4);\n \t\t\toob_size = (ecc->steps * 4) + host->ecc_bytes_hw;\n \t\t} else {\n@@ -1843,7 +1860,7 @@ static int read_page_ecc(struct qcom_nan\n \tfor (i = 0; i < ecc->steps; i++) {\n \t\tint data_size, oob_size;\n \n-\t\tif (i == (ecc->steps - 1)) {\n+\t\tif (i == (ecc->steps - 1) && !host->boot_pages_conf) {\n \t\t\tdata_size = ecc->size - ((ecc->steps - 1) << 2);\n \t\t\toob_size = (ecc->steps << 2) + host->ecc_bytes_hw +\n \t\t\t\t   host->spare_bytes;\n@@ -1940,6 +1957,30 @@ static int copy_last_cw(struct qcom_nand\n \treturn ret;\n }\n \n+static void\n+check_boot_pages_conf(struct qcom_nand_host *host, int page)\n+{\n+\tbool boot_pages_conf = page < host->boot_pages;\n+\n+\t/* Skip conf write if we are already in the correct mode */\n+\tif (boot_pages_conf != host->boot_pages_conf) {\n+\t\thost->boot_pages_conf = boot_pages_conf;\n+\n+\t\thost->cw_data = boot_pages_conf ? 512 : 516;\n+\t\thost->spare_bytes = host->cw_size - host->ecc_bytes_hw -\n+\t\t\t\t    host->bbm_size - host->cw_data;\n+\n+\t\thost->cfg0 &= ~(SPARE_SIZE_BYTES_MASK | UD_SIZE_BYTES_MASK);\n+\t\thost->cfg0 |= host->spare_bytes << SPARE_SIZE_BYTES |\n+\t\t\t      host->cw_data << UD_SIZE_BYTES;\n+\n+\t\thost->ecc_bch_cfg &= ~ECC_NUM_DATA_BYTES_MASK;\n+\t\thost->ecc_bch_cfg |= host->cw_data << ECC_NUM_DATA_BYTES;\n+\t\thost->ecc_buf_cfg = (boot_pages_conf ? 0x1ff : 0x203) <<\n+\t\t\t\t     NUM_STEPS;\n+\t}\n+}\n+\n /* implements ecc->read_page() */\n static int qcom_nandc_read_page(struct nand_chip *chip, uint8_t *buf,\n \t\t\t\tint oob_required, int page)\n@@ -1948,6 +1989,9 @@ static int qcom_nandc_read_page(struct n\n \tstruct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);\n \tu8 *data_buf, *oob_buf = NULL;\n \n+\tif (host->boot_pages)\n+\t\tcheck_boot_pages_conf(host, page);\n+\n \tnand_read_page_op(chip, page, 0, NULL, 0);\n \tdata_buf = buf;\n \toob_buf = oob_required ? chip->oob_poi : NULL;\n@@ -1967,6 +2011,9 @@ static int qcom_nandc_read_page_raw(stru\n \tint cw, ret;\n \tu8 *data_buf = buf, *oob_buf = chip->oob_poi;\n \n+\tif (host->boot_pages)\n+\t\tcheck_boot_pages_conf(host, page);\n+\n \tfor (cw = 0; cw < ecc->steps; cw++) {\n \t\tret = qcom_nandc_read_cw_raw(mtd, chip, data_buf, oob_buf,\n \t\t\t\t\t     page, cw);\n@@ -1987,6 +2034,9 @@ static int qcom_nandc_read_oob(struct na\n \tstruct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);\n \tstruct nand_ecc_ctrl *ecc = &chip->ecc;\n \n+\tif (host->boot_pages)\n+\t\tcheck_boot_pages_conf(host, page);\n+\n \tclear_read_regs(nandc);\n \tclear_bam_transaction(nandc);\n \n@@ -2007,6 +2057,9 @@ static int qcom_nandc_write_page(struct\n \tu8 *data_buf, *oob_buf;\n \tint i, ret;\n \n+\tif (host->boot_pages)\n+\t\tcheck_boot_pages_conf(host, page);\n+\n \tnand_prog_page_begin_op(chip, page, 0, NULL, 0);\n \n \tclear_read_regs(nandc);\n@@ -2022,7 +2075,7 @@ static int qcom_nandc_write_page(struct\n \tfor (i = 0; i < ecc->steps; i++) {\n \t\tint data_size, oob_size;\n \n-\t\tif (i == (ecc->steps - 1)) {\n+\t\tif (i == (ecc->steps - 1) && !host->boot_pages_conf) {\n \t\t\tdata_size = ecc->size - ((ecc->steps - 1) << 2);\n \t\t\toob_size = (ecc->steps << 2) + host->ecc_bytes_hw +\n \t\t\t\t   host->spare_bytes;\n@@ -2079,6 +2132,9 @@ static int qcom_nandc_write_page_raw(str\n \tu8 *data_buf, *oob_buf;\n \tint i, ret;\n \n+\tif (host->boot_pages)\n+\t\tcheck_boot_pages_conf(host, page);\n+\n \tnand_prog_page_begin_op(chip, page, 0, NULL, 0);\n \tclear_read_regs(nandc);\n \tclear_bam_transaction(nandc);\n@@ -2097,7 +2153,7 @@ static int qcom_nandc_write_page_raw(str\n \t\tdata_size1 = mtd->writesize - host->cw_size * (ecc->steps - 1);\n \t\toob_size1 = host->bbm_size;\n \n-\t\tif (i == (ecc->steps - 1)) {\n+\t\tif (i == (ecc->steps - 1) && !host->boot_pages_conf) {\n \t\t\tdata_size2 = ecc->size - data_size1 -\n \t\t\t\t     ((ecc->steps - 1) << 2);\n \t\t\toob_size2 = (ecc->steps << 2) + host->ecc_bytes_hw +\n@@ -2157,6 +2213,9 @@ static int qcom_nandc_write_oob(struct n\n \tint data_size, oob_size;\n \tint ret;\n \n+\tif (host->boot_pages)\n+\t\tcheck_boot_pages_conf(host, page);\n+\n \thost->use_ecc = true;\n \tclear_bam_transaction(nandc);\n \n@@ -2805,6 +2864,7 @@ static int qcom_nand_host_init_and_regis\n \tstruct nand_chip *chip = &host->chip;\n \tstruct mtd_info *mtd = nand_to_mtd(chip);\n \tstruct device *dev = nandc->dev;\n+\tu32 boot_pages_size;\n \tint ret;\n \n \tret = of_property_read_u32(dn, \"reg\", &host->cs);\n@@ -2865,6 +2925,17 @@ static int qcom_nand_host_init_and_regis\n \tif (ret)\n \t\tnand_cleanup(chip);\n \n+\tif (nandc->props->has_boot_pages &&\n+\t    of_property_read_bool(dn, \"nand-is-boot-medium\")) {\n+\t\tret = of_property_read_u32(dn, \"qcom,boot_pages_size\",\n+\t\t\t\t\t   &boot_pages_size);\n+\t\tif (ret)\n+\t\t\tdev_warn(dev, \"can't get boot pages size\");\n+\t\telse\n+\t\t\t/* Convert size to nand pages */\n+\t\t\thost->boot_pages = boot_pages_size / mtd->writesize;\n+\t}\n+\n \treturn ret;\n }\n \n@@ -3030,6 +3101,7 @@ static int qcom_nandc_remove(struct plat\n static const struct qcom_nandc_props ipq806x_nandc_props = {\n \t.ecc_modes = (ECC_RS_4BIT | ECC_BCH_8BIT),\n \t.is_bam = false,\n+\t.has_boot_pages = true,\n \t.dev_cmd_reg_start = 0x0,\n };\n \n"
  },
  {
    "path": "target/linux/ipq806x/patches-5.10/099-2-Documentation-devicetree-mtd-qcom_nandc-document-qco.patch",
    "content": "From 6fb003a7a117f97a35b078ba726c84adeae29c4c Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Wed, 10 Feb 2021 10:54:19 +0100\nSubject: [PATCH 2/2] Documentation: devicetree: mtd: qcom_nandc: document\n qcom,boot_layout_size binding\n\nDocument new qcom,boot_layout_size binding used to apply special\nread/write confituation to boots partitions.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\n---\n Documentation/devicetree/bindings/mtd/qcom_nandc.txt | 11 +++++++++++\n 1 file changed, 11 insertions(+)\n\n--- a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt\n+++ b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt\n@@ -52,6 +52,15 @@ Optional properties:\n \t\t\tbe used according to chip requirement and available\n \t\t\tOOB size.\n \n+EBI2 specific properties:\n+- nand-is-boot-medium:\tnand contains boot partitions and different ecc configuration\n+\t\t\tshould be used for these partitions.\n+- qcom,boot_pages_size:\tshould contain the size of the total boot partitions\n+\t\t\twhere the boot layout read/write specific configuration\n+\t\t\tshould be used. The boot layout is considered from the\n+\t\t\tstart of the nand to the value set in this binding.\n+\t\t\tOnly used in combination with 'nand-is-boot-medium'.\n+\n Each nandcs device node may optionally contain a 'partitions' sub-node, which\n further contains sub-nodes describing the flash partition mapping. See\n partition.txt for more detail.\n@@ -80,6 +89,9 @@ nand-controller@1ac00000 {\n \t\tnand-ecc-strength = <4>;\n \t\tnand-bus-width = <8>;\n \n+\t\tnand-is-boot-medium;\n+\t\tqcom,boot_pages_size: <0x58a0000>;\n+\n \t\tpartitions {\n \t\t\tcompatible = \"fixed-partitions\";\n \t\t\t#address-cells = <1>;\n"
  },
  {
    "path": "target/linux/ipq806x/patches-5.10/100-v5.11-dmaengine-qcom-add_ADM_driver.patch",
    "content": "From 5c9f8c2dbdbe53818bcde6aa6695e1331e5f841f Mon Sep 17 00:00:00 2001\nFrom: Jonathan McDowell <noodles@earth.li>\nDate: Sat, 14 Nov 2020 14:02:33 +0000\nSubject: dmaengine: qcom: Add ADM driver\n\nAdd the DMA engine driver for the QCOM Application Data Mover (ADM) DMA\ncontroller found in the MSM8x60 and IPQ/APQ8064 platforms.\n\nThe ADM supports both memory to memory transactions and memory\nto/from peripheral device transactions.  The controller also provides\nflow control capabilities for transactions to/from peripheral devices.\n\nThe initial release of this driver supports slave transfers to/from\nperipherals and also incorporates CRCI (client rate control interface)\nflow control.\n\nThe hardware only supports a 32 bit physical address, so specifying\n!PHYS_ADDR_T_64BIT gives maximum COMPILE_TEST coverage without having to\nspend effort on kludging things in the code that will never actually be\nneeded on real hardware.\n\nSigned-off-by: Andy Gross <agross@codeaurora.org>\nSigned-off-by: Thomas Pedersen <twp@codeaurora.org>\nSigned-off-by: Jonathan McDowell <noodles@earth.li>\nLink: https://lore.kernel.org/r/20201114140233.GM32650@earth.li\nSigned-off-by: Vinod Koul <vkoul@kernel.org>\n---\n drivers/dma/qcom/Kconfig    |  11 +\n drivers/dma/qcom/Makefile   |   1 +\n drivers/dma/qcom/qcom_adm.c | 903 ++++++++++++++++++++++++++++++++++++++++++++\n 3 files changed, 915 insertions(+)\n create mode 100644 drivers/dma/qcom/qcom_adm.c\n\n--- a/drivers/dma/qcom/Kconfig\n+++ b/drivers/dma/qcom/Kconfig\n@@ -1,4 +1,15 @@\n # SPDX-License-Identifier: GPL-2.0-only\n+config QCOM_ADM\n+\ttristate \"Qualcomm ADM support\"\n+\tdepends on (ARCH_QCOM || COMPILE_TEST) && !PHYS_ADDR_T_64BIT\n+\tselect DMA_ENGINE\n+\tselect DMA_VIRTUAL_CHANNELS\n+\thelp\n+\t  Enable support for the Qualcomm Application Data Mover (ADM) DMA\n+\t  controller, as present on MSM8x60, APQ8064, and IPQ8064 devices.\n+\t  This controller provides DMA capabilities for both general purpose\n+\t  and on-chip peripheral devices.\n+\n config QCOM_BAM_DMA\n \ttristate \"QCOM BAM DMA support\"\n \tdepends on ARCH_QCOM || (COMPILE_TEST && OF && ARM)\n--- a/drivers/dma/qcom/Makefile\n+++ b/drivers/dma/qcom/Makefile\n@@ -1,4 +1,5 @@\n # SPDX-License-Identifier: GPL-2.0\n+obj-$(CONFIG_QCOM_ADM) += qcom_adm.o\n obj-$(CONFIG_QCOM_BAM_DMA) += bam_dma.o\n obj-$(CONFIG_QCOM_HIDMA_MGMT) += hdma_mgmt.o\n hdma_mgmt-objs\t := hidma_mgmt.o hidma_mgmt_sys.o\n--- /dev/null\n+++ b/drivers/dma/qcom/qcom_adm.c\n@@ -0,0 +1,903 @@\n+// SPDX-License-Identifier: GPL-2.0-only\n+/*\n+ * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.\n+ */\n+\n+#include <linux/clk.h>\n+#include <linux/delay.h>\n+#include <linux/device.h>\n+#include <linux/dmaengine.h>\n+#include <linux/dma-mapping.h>\n+#include <linux/init.h>\n+#include <linux/interrupt.h>\n+#include <linux/io.h>\n+#include <linux/kernel.h>\n+#include <linux/module.h>\n+#include <linux/of.h>\n+#include <linux/of_address.h>\n+#include <linux/of_irq.h>\n+#include <linux/of_dma.h>\n+#include <linux/platform_device.h>\n+#include <linux/reset.h>\n+#include <linux/scatterlist.h>\n+#include <linux/slab.h>\n+\n+#include \"../dmaengine.h\"\n+#include \"../virt-dma.h\"\n+\n+/* ADM registers - calculated from channel number and security domain */\n+#define ADM_CHAN_MULTI\t\t\t0x4\n+#define ADM_CI_MULTI\t\t\t0x4\n+#define ADM_CRCI_MULTI\t\t\t0x4\n+#define ADM_EE_MULTI\t\t\t0x800\n+#define ADM_CHAN_OFFS(chan)\t\t(ADM_CHAN_MULTI * (chan))\n+#define ADM_EE_OFFS(ee)\t\t\t(ADM_EE_MULTI * (ee))\n+#define ADM_CHAN_EE_OFFS(chan, ee)\t(ADM_CHAN_OFFS(chan) + ADM_EE_OFFS(ee))\n+#define ADM_CHAN_OFFS(chan)\t\t(ADM_CHAN_MULTI * (chan))\n+#define ADM_CI_OFFS(ci)\t\t\t(ADM_CHAN_OFF(ci))\n+#define ADM_CH_CMD_PTR(chan, ee)\t(ADM_CHAN_EE_OFFS(chan, ee))\n+#define ADM_CH_RSLT(chan, ee)\t\t(0x40 + ADM_CHAN_EE_OFFS(chan, ee))\n+#define ADM_CH_FLUSH_STATE0(chan, ee)\t(0x80 + ADM_CHAN_EE_OFFS(chan, ee))\n+#define ADM_CH_STATUS_SD(chan, ee)\t(0x200 + ADM_CHAN_EE_OFFS(chan, ee))\n+#define ADM_CH_CONF(chan)\t\t(0x240 + ADM_CHAN_OFFS(chan))\n+#define ADM_CH_RSLT_CONF(chan, ee)\t(0x300 + ADM_CHAN_EE_OFFS(chan, ee))\n+#define ADM_SEC_DOMAIN_IRQ_STATUS(ee)\t(0x380 + ADM_EE_OFFS(ee))\n+#define ADM_CI_CONF(ci)\t\t\t(0x390 + (ci) * ADM_CI_MULTI)\n+#define ADM_GP_CTL\t\t\t0x3d8\n+#define ADM_CRCI_CTL(crci, ee)\t\t(0x400 + (crci) * ADM_CRCI_MULTI + \\\n+\t\t\t\t\t\tADM_EE_OFFS(ee))\n+\n+/* channel status */\n+#define ADM_CH_STATUS_VALID\t\tBIT(1)\n+\n+/* channel result */\n+#define ADM_CH_RSLT_VALID\t\tBIT(31)\n+#define ADM_CH_RSLT_ERR\t\t\tBIT(3)\n+#define ADM_CH_RSLT_FLUSH\t\tBIT(2)\n+#define ADM_CH_RSLT_TPD\t\t\tBIT(1)\n+\n+/* channel conf */\n+#define ADM_CH_CONF_SHADOW_EN\t\tBIT(12)\n+#define ADM_CH_CONF_MPU_DISABLE\t\tBIT(11)\n+#define ADM_CH_CONF_PERM_MPU_CONF\tBIT(9)\n+#define ADM_CH_CONF_FORCE_RSLT_EN\tBIT(7)\n+#define ADM_CH_CONF_SEC_DOMAIN(ee)\t((((ee) & 0x3) << 4) | (((ee) & 0x4) << 11))\n+\n+/* channel result conf */\n+#define ADM_CH_RSLT_CONF_FLUSH_EN\tBIT(1)\n+#define ADM_CH_RSLT_CONF_IRQ_EN\t\tBIT(0)\n+\n+/* CRCI CTL */\n+#define ADM_CRCI_CTL_MUX_SEL\t\tBIT(18)\n+#define ADM_CRCI_CTL_RST\t\tBIT(17)\n+\n+/* CI configuration */\n+#define ADM_CI_RANGE_END(x)\t\t((x) << 24)\n+#define ADM_CI_RANGE_START(x)\t\t((x) << 16)\n+#define ADM_CI_BURST_4_WORDS\t\tBIT(2)\n+#define ADM_CI_BURST_8_WORDS\t\tBIT(3)\n+\n+/* GP CTL */\n+#define ADM_GP_CTL_LP_EN\t\tBIT(12)\n+#define ADM_GP_CTL_LP_CNT(x)\t\t((x) << 8)\n+\n+/* Command pointer list entry */\n+#define ADM_CPLE_LP\t\t\tBIT(31)\n+#define ADM_CPLE_CMD_PTR_LIST\t\tBIT(29)\n+\n+/* Command list entry */\n+#define ADM_CMD_LC\t\t\tBIT(31)\n+#define ADM_CMD_DST_CRCI(n)\t\t(((n) & 0xf) << 7)\n+#define ADM_CMD_SRC_CRCI(n)\t\t(((n) & 0xf) << 3)\n+\n+#define ADM_CMD_TYPE_SINGLE\t\t0x0\n+#define ADM_CMD_TYPE_BOX\t\t0x3\n+\n+#define ADM_CRCI_MUX_SEL\t\tBIT(4)\n+#define ADM_DESC_ALIGN\t\t\t8\n+#define ADM_MAX_XFER\t\t\t(SZ_64K - 1)\n+#define ADM_MAX_ROWS\t\t\t(SZ_64K - 1)\n+#define ADM_MAX_CHANNELS\t\t16\n+\n+struct adm_desc_hw_box {\n+\tu32 cmd;\n+\tu32 src_addr;\n+\tu32 dst_addr;\n+\tu32 row_len;\n+\tu32 num_rows;\n+\tu32 row_offset;\n+};\n+\n+struct adm_desc_hw_single {\n+\tu32 cmd;\n+\tu32 src_addr;\n+\tu32 dst_addr;\n+\tu32 len;\n+};\n+\n+struct adm_async_desc {\n+\tstruct virt_dma_desc vd;\n+\tstruct adm_device *adev;\n+\n+\tsize_t length;\n+\tenum dma_transfer_direction dir;\n+\tdma_addr_t dma_addr;\n+\tsize_t dma_len;\n+\n+\tvoid *cpl;\n+\tdma_addr_t cp_addr;\n+\tu32 crci;\n+\tu32 mux;\n+\tu32 blk_size;\n+};\n+\n+struct adm_chan {\n+\tstruct virt_dma_chan vc;\n+\tstruct adm_device *adev;\n+\n+\t/* parsed from DT */\n+\tu32 id;\t\t\t/* channel id */\n+\n+\tstruct adm_async_desc *curr_txd;\n+\tstruct dma_slave_config slave;\n+\tstruct list_head node;\n+\n+\tint error;\n+\tint initialized;\n+};\n+\n+static inline struct adm_chan *to_adm_chan(struct dma_chan *common)\n+{\n+\treturn container_of(common, struct adm_chan, vc.chan);\n+}\n+\n+struct adm_device {\n+\tvoid __iomem *regs;\n+\tstruct device *dev;\n+\tstruct dma_device common;\n+\tstruct device_dma_parameters dma_parms;\n+\tstruct adm_chan *channels;\n+\n+\tu32 ee;\n+\n+\tstruct clk *core_clk;\n+\tstruct clk *iface_clk;\n+\n+\tstruct reset_control *clk_reset;\n+\tstruct reset_control *c0_reset;\n+\tstruct reset_control *c1_reset;\n+\tstruct reset_control *c2_reset;\n+\tint irq;\n+};\n+\n+/**\n+ * adm_free_chan - Frees dma resources associated with the specific channel\n+ *\n+ * Free all allocated descriptors associated with this channel\n+ *\n+ */\n+static void adm_free_chan(struct dma_chan *chan)\n+{\n+\t/* free all queued descriptors */\n+\tvchan_free_chan_resources(to_virt_chan(chan));\n+}\n+\n+/**\n+ * adm_get_blksize - Get block size from burst value\n+ *\n+ */\n+static int adm_get_blksize(unsigned int burst)\n+{\n+\tint ret;\n+\n+\tswitch (burst) {\n+\tcase 16:\n+\tcase 32:\n+\tcase 64:\n+\tcase 128:\n+\t\tret = ffs(burst >> 4) - 1;\n+\t\tbreak;\n+\tcase 192:\n+\t\tret = 4;\n+\t\tbreak;\n+\tcase 256:\n+\t\tret = 5;\n+\t\tbreak;\n+\tdefault:\n+\t\tret = -EINVAL;\n+\t\tbreak;\n+\t}\n+\n+\treturn ret;\n+}\n+\n+/**\n+ * adm_process_fc_descriptors - Process descriptors for flow controlled xfers\n+ *\n+ * @achan: ADM channel\n+ * @desc: Descriptor memory pointer\n+ * @sg: Scatterlist entry\n+ * @crci: CRCI value\n+ * @burst: Burst size of transaction\n+ * @direction: DMA transfer direction\n+ */\n+static void *adm_process_fc_descriptors(struct adm_chan *achan, void *desc,\n+\t\t\t\t\tstruct scatterlist *sg, u32 crci,\n+\t\t\t\t\tu32 burst,\n+\t\t\t\t\tenum dma_transfer_direction direction)\n+{\n+\tstruct adm_desc_hw_box *box_desc = NULL;\n+\tstruct adm_desc_hw_single *single_desc;\n+\tu32 remainder = sg_dma_len(sg);\n+\tu32 rows, row_offset, crci_cmd;\n+\tu32 mem_addr = sg_dma_address(sg);\n+\tu32 *incr_addr = &mem_addr;\n+\tu32 *src, *dst;\n+\n+\tif (direction == DMA_DEV_TO_MEM) {\n+\t\tcrci_cmd = ADM_CMD_SRC_CRCI(crci);\n+\t\trow_offset = burst;\n+\t\tsrc = &achan->slave.src_addr;\n+\t\tdst = &mem_addr;\n+\t} else {\n+\t\tcrci_cmd = ADM_CMD_DST_CRCI(crci);\n+\t\trow_offset = burst << 16;\n+\t\tsrc = &mem_addr;\n+\t\tdst = &achan->slave.dst_addr;\n+\t}\n+\n+\twhile (remainder >= burst) {\n+\t\tbox_desc = desc;\n+\t\tbox_desc->cmd = ADM_CMD_TYPE_BOX | crci_cmd;\n+\t\tbox_desc->row_offset = row_offset;\n+\t\tbox_desc->src_addr = *src;\n+\t\tbox_desc->dst_addr = *dst;\n+\n+\t\trows = remainder / burst;\n+\t\trows = min_t(u32, rows, ADM_MAX_ROWS);\n+\t\tbox_desc->num_rows = rows << 16 | rows;\n+\t\tbox_desc->row_len = burst << 16 | burst;\n+\n+\t\t*incr_addr += burst * rows;\n+\t\tremainder -= burst * rows;\n+\t\tdesc += sizeof(*box_desc);\n+\t}\n+\n+\t/* if leftover bytes, do one single descriptor */\n+\tif (remainder) {\n+\t\tsingle_desc = desc;\n+\t\tsingle_desc->cmd = ADM_CMD_TYPE_SINGLE | crci_cmd;\n+\t\tsingle_desc->len = remainder;\n+\t\tsingle_desc->src_addr = *src;\n+\t\tsingle_desc->dst_addr = *dst;\n+\t\tdesc += sizeof(*single_desc);\n+\n+\t\tif (sg_is_last(sg))\n+\t\t\tsingle_desc->cmd |= ADM_CMD_LC;\n+\t} else {\n+\t\tif (box_desc && sg_is_last(sg))\n+\t\t\tbox_desc->cmd |= ADM_CMD_LC;\n+\t}\n+\n+\treturn desc;\n+}\n+\n+/**\n+ * adm_process_non_fc_descriptors - Process descriptors for non-fc xfers\n+ *\n+ * @achan: ADM channel\n+ * @desc: Descriptor memory pointer\n+ * @sg: Scatterlist entry\n+ * @direction: DMA transfer direction\n+ */\n+static void *adm_process_non_fc_descriptors(struct adm_chan *achan, void *desc,\n+\t\t\t\t\t    struct scatterlist *sg,\n+\t\t\t\t\t    enum dma_transfer_direction direction)\n+{\n+\tstruct adm_desc_hw_single *single_desc;\n+\tu32 remainder = sg_dma_len(sg);\n+\tu32 mem_addr = sg_dma_address(sg);\n+\tu32 *incr_addr = &mem_addr;\n+\tu32 *src, *dst;\n+\n+\tif (direction == DMA_DEV_TO_MEM) {\n+\t\tsrc = &achan->slave.src_addr;\n+\t\tdst = &mem_addr;\n+\t} else {\n+\t\tsrc = &mem_addr;\n+\t\tdst = &achan->slave.dst_addr;\n+\t}\n+\n+\tdo {\n+\t\tsingle_desc = desc;\n+\t\tsingle_desc->cmd = ADM_CMD_TYPE_SINGLE;\n+\t\tsingle_desc->src_addr = *src;\n+\t\tsingle_desc->dst_addr = *dst;\n+\t\tsingle_desc->len = (remainder > ADM_MAX_XFER) ?\n+\t\t\t\tADM_MAX_XFER : remainder;\n+\n+\t\tremainder -= single_desc->len;\n+\t\t*incr_addr += single_desc->len;\n+\t\tdesc += sizeof(*single_desc);\n+\t} while (remainder);\n+\n+\t/* set last command if this is the end of the whole transaction */\n+\tif (sg_is_last(sg))\n+\t\tsingle_desc->cmd |= ADM_CMD_LC;\n+\n+\treturn desc;\n+}\n+\n+/**\n+ * adm_prep_slave_sg - Prep slave sg transaction\n+ *\n+ * @chan: dma channel\n+ * @sgl: scatter gather list\n+ * @sg_len: length of sg\n+ * @direction: DMA transfer direction\n+ * @flags: DMA flags\n+ * @context: transfer context (unused)\n+ */\n+static struct dma_async_tx_descriptor *adm_prep_slave_sg(struct dma_chan *chan,\n+\t\t\t\t\t\t\t struct scatterlist *sgl,\n+\t\t\t\t\t\t\t unsigned int sg_len,\n+\t\t\t\t\t\t\t enum dma_transfer_direction direction,\n+\t\t\t\t\t\t\t unsigned long flags,\n+\t\t\t\t\t\t\t void *context)\n+{\n+\tstruct adm_chan *achan = to_adm_chan(chan);\n+\tstruct adm_device *adev = achan->adev;\n+\tstruct adm_async_desc *async_desc;\n+\tstruct scatterlist *sg;\n+\tdma_addr_t cple_addr;\n+\tu32 i, burst;\n+\tu32 single_count = 0, box_count = 0, crci = 0;\n+\tvoid *desc;\n+\tu32 *cple;\n+\tint blk_size = 0;\n+\n+\tif (!is_slave_direction(direction)) {\n+\t\tdev_err(adev->dev, \"invalid dma direction\\n\");\n+\t\treturn NULL;\n+\t}\n+\n+\t/*\n+\t * get burst value from slave configuration\n+\t */\n+\tburst = (direction == DMA_MEM_TO_DEV) ?\n+\t\tachan->slave.dst_maxburst :\n+\t\tachan->slave.src_maxburst;\n+\n+\t/* if using flow control, validate burst and crci values */\n+\tif (achan->slave.device_fc) {\n+\t\tblk_size = adm_get_blksize(burst);\n+\t\tif (blk_size < 0) {\n+\t\t\tdev_err(adev->dev, \"invalid burst value: %d\\n\",\n+\t\t\t\tburst);\n+\t\t\treturn ERR_PTR(-EINVAL);\n+\t\t}\n+\n+\t\tcrci = achan->slave.slave_id & 0xf;\n+\t\tif (!crci || achan->slave.slave_id > 0x1f) {\n+\t\t\tdev_err(adev->dev, \"invalid crci value\\n\");\n+\t\t\treturn ERR_PTR(-EINVAL);\n+\t\t}\n+\t}\n+\n+\t/* iterate through sgs and compute allocation size of structures */\n+\tfor_each_sg(sgl, sg, sg_len, i) {\n+\t\tif (achan->slave.device_fc) {\n+\t\t\tbox_count += DIV_ROUND_UP(sg_dma_len(sg) / burst,\n+\t\t\t\t\t\t  ADM_MAX_ROWS);\n+\t\t\tif (sg_dma_len(sg) % burst)\n+\t\t\t\tsingle_count++;\n+\t\t} else {\n+\t\t\tsingle_count += DIV_ROUND_UP(sg_dma_len(sg),\n+\t\t\t\t\t\t     ADM_MAX_XFER);\n+\t\t}\n+\t}\n+\n+\tasync_desc = kzalloc(sizeof(*async_desc), GFP_NOWAIT);\n+\tif (!async_desc)\n+\t\treturn ERR_PTR(-ENOMEM);\n+\n+\tif (crci)\n+\t\tasync_desc->mux = achan->slave.slave_id & ADM_CRCI_MUX_SEL ?\n+\t\t\t\t\tADM_CRCI_CTL_MUX_SEL : 0;\n+\tasync_desc->crci = crci;\n+\tasync_desc->blk_size = blk_size;\n+\tasync_desc->dma_len = single_count * sizeof(struct adm_desc_hw_single) +\n+\t\t\t\tbox_count * sizeof(struct adm_desc_hw_box) +\n+\t\t\t\tsizeof(*cple) + 2 * ADM_DESC_ALIGN;\n+\n+\tasync_desc->cpl = kzalloc(async_desc->dma_len, GFP_NOWAIT);\n+\tif (!async_desc->cpl)\n+\t\tgoto free;\n+\n+\tasync_desc->adev = adev;\n+\n+\t/* both command list entry and descriptors must be 8 byte aligned */\n+\tcple = PTR_ALIGN(async_desc->cpl, ADM_DESC_ALIGN);\n+\tdesc = PTR_ALIGN(cple + 1, ADM_DESC_ALIGN);\n+\n+\tfor_each_sg(sgl, sg, sg_len, i) {\n+\t\tasync_desc->length += sg_dma_len(sg);\n+\n+\t\tif (achan->slave.device_fc)\n+\t\t\tdesc = adm_process_fc_descriptors(achan, desc, sg, crci,\n+\t\t\t\t\t\t\t  burst, direction);\n+\t\telse\n+\t\t\tdesc = adm_process_non_fc_descriptors(achan, desc, sg,\n+\t\t\t\t\t\t\t      direction);\n+\t}\n+\n+\tasync_desc->dma_addr = dma_map_single(adev->dev, async_desc->cpl,\n+\t\t\t\t\t      async_desc->dma_len,\n+\t\t\t\t\t      DMA_TO_DEVICE);\n+\tif (dma_mapping_error(adev->dev, async_desc->dma_addr))\n+\t\tgoto free;\n+\n+\tcple_addr = async_desc->dma_addr + ((void *)cple - async_desc->cpl);\n+\n+\t/* init cmd list */\n+\tdma_sync_single_for_cpu(adev->dev, cple_addr, sizeof(*cple),\n+\t\t\t\tDMA_TO_DEVICE);\n+\t*cple = ADM_CPLE_LP;\n+\t*cple |= (async_desc->dma_addr + ADM_DESC_ALIGN) >> 3;\n+\tdma_sync_single_for_device(adev->dev, cple_addr, sizeof(*cple),\n+\t\t\t\t   DMA_TO_DEVICE);\n+\n+\treturn vchan_tx_prep(&achan->vc, &async_desc->vd, flags);\n+\n+free:\n+\tkfree(async_desc);\n+\treturn ERR_PTR(-ENOMEM);\n+}\n+\n+/**\n+ * adm_terminate_all - terminate all transactions on a channel\n+ * @achan: adm dma channel\n+ *\n+ * Dequeues and frees all transactions, aborts current transaction\n+ * No callbacks are done\n+ *\n+ */\n+static int adm_terminate_all(struct dma_chan *chan)\n+{\n+\tstruct adm_chan *achan = to_adm_chan(chan);\n+\tstruct adm_device *adev = achan->adev;\n+\tunsigned long flags;\n+\tLIST_HEAD(head);\n+\n+\tspin_lock_irqsave(&achan->vc.lock, flags);\n+\tvchan_get_all_descriptors(&achan->vc, &head);\n+\n+\t/* send flush command to terminate current transaction */\n+\twritel_relaxed(0x0,\n+\t\t       adev->regs + ADM_CH_FLUSH_STATE0(achan->id, adev->ee));\n+\n+\tspin_unlock_irqrestore(&achan->vc.lock, flags);\n+\n+\tvchan_dma_desc_free_list(&achan->vc, &head);\n+\n+\treturn 0;\n+}\n+\n+static int adm_slave_config(struct dma_chan *chan, struct dma_slave_config *cfg)\n+{\n+\tstruct adm_chan *achan = to_adm_chan(chan);\n+\tunsigned long flag;\n+\n+\tspin_lock_irqsave(&achan->vc.lock, flag);\n+\tmemcpy(&achan->slave, cfg, sizeof(struct dma_slave_config));\n+\tspin_unlock_irqrestore(&achan->vc.lock, flag);\n+\n+\treturn 0;\n+}\n+\n+/**\n+ * adm_start_dma - start next transaction\n+ * @achan - ADM dma channel\n+ */\n+static void adm_start_dma(struct adm_chan *achan)\n+{\n+\tstruct virt_dma_desc *vd = vchan_next_desc(&achan->vc);\n+\tstruct adm_device *adev = achan->adev;\n+\tstruct adm_async_desc *async_desc;\n+\n+\tlockdep_assert_held(&achan->vc.lock);\n+\n+\tif (!vd)\n+\t\treturn;\n+\n+\tlist_del(&vd->node);\n+\n+\t/* write next command list out to the CMD FIFO */\n+\tasync_desc = container_of(vd, struct adm_async_desc, vd);\n+\tachan->curr_txd = async_desc;\n+\n+\t/* reset channel error */\n+\tachan->error = 0;\n+\n+\tif (!achan->initialized) {\n+\t\t/* enable interrupts */\n+\t\twritel(ADM_CH_CONF_SHADOW_EN |\n+\t\t       ADM_CH_CONF_PERM_MPU_CONF |\n+\t\t       ADM_CH_CONF_MPU_DISABLE |\n+\t\t       ADM_CH_CONF_SEC_DOMAIN(adev->ee),\n+\t\t       adev->regs + ADM_CH_CONF(achan->id));\n+\n+\t\twritel(ADM_CH_RSLT_CONF_IRQ_EN | ADM_CH_RSLT_CONF_FLUSH_EN,\n+\t\t       adev->regs + ADM_CH_RSLT_CONF(achan->id, adev->ee));\n+\n+\t\tachan->initialized = 1;\n+\t}\n+\n+\t/* set the crci block size if this transaction requires CRCI */\n+\tif (async_desc->crci) {\n+\t\twritel(async_desc->mux | async_desc->blk_size,\n+\t\t       adev->regs + ADM_CRCI_CTL(async_desc->crci, adev->ee));\n+\t}\n+\n+\t/* make sure IRQ enable doesn't get reordered */\n+\twmb();\n+\n+\t/* write next command list out to the CMD FIFO */\n+\twritel(ALIGN(async_desc->dma_addr, ADM_DESC_ALIGN) >> 3,\n+\t       adev->regs + ADM_CH_CMD_PTR(achan->id, adev->ee));\n+}\n+\n+/**\n+ * adm_dma_irq - irq handler for ADM controller\n+ * @irq: IRQ of interrupt\n+ * @data: callback data\n+ *\n+ * IRQ handler for the bam controller\n+ */\n+static irqreturn_t adm_dma_irq(int irq, void *data)\n+{\n+\tstruct adm_device *adev = data;\n+\tu32 srcs, i;\n+\tstruct adm_async_desc *async_desc;\n+\tunsigned long flags;\n+\n+\tsrcs = readl_relaxed(adev->regs +\n+\t\t\tADM_SEC_DOMAIN_IRQ_STATUS(adev->ee));\n+\n+\tfor (i = 0; i < ADM_MAX_CHANNELS; i++) {\n+\t\tstruct adm_chan *achan = &adev->channels[i];\n+\t\tu32 status, result;\n+\n+\t\tif (srcs & BIT(i)) {\n+\t\t\tstatus = readl_relaxed(adev->regs +\n+\t\t\t\t\t       ADM_CH_STATUS_SD(i, adev->ee));\n+\n+\t\t\t/* if no result present, skip */\n+\t\t\tif (!(status & ADM_CH_STATUS_VALID))\n+\t\t\t\tcontinue;\n+\n+\t\t\tresult = readl_relaxed(adev->regs +\n+\t\t\t\tADM_CH_RSLT(i, adev->ee));\n+\n+\t\t\t/* no valid results, skip */\n+\t\t\tif (!(result & ADM_CH_RSLT_VALID))\n+\t\t\t\tcontinue;\n+\n+\t\t\t/* flag error if transaction was flushed or failed */\n+\t\t\tif (result & (ADM_CH_RSLT_ERR | ADM_CH_RSLT_FLUSH))\n+\t\t\t\tachan->error = 1;\n+\n+\t\t\tspin_lock_irqsave(&achan->vc.lock, flags);\n+\t\t\tasync_desc = achan->curr_txd;\n+\n+\t\t\tachan->curr_txd = NULL;\n+\n+\t\t\tif (async_desc) {\n+\t\t\t\tvchan_cookie_complete(&async_desc->vd);\n+\n+\t\t\t\t/* kick off next DMA */\n+\t\t\t\tadm_start_dma(achan);\n+\t\t\t}\n+\n+\t\t\tspin_unlock_irqrestore(&achan->vc.lock, flags);\n+\t\t}\n+\t}\n+\n+\treturn IRQ_HANDLED;\n+}\n+\n+/**\n+ * adm_tx_status - returns status of transaction\n+ * @chan: dma channel\n+ * @cookie: transaction cookie\n+ * @txstate: DMA transaction state\n+ *\n+ * Return status of dma transaction\n+ */\n+static enum dma_status adm_tx_status(struct dma_chan *chan, dma_cookie_t cookie,\n+\t\t\t\t     struct dma_tx_state *txstate)\n+{\n+\tstruct adm_chan *achan = to_adm_chan(chan);\n+\tstruct virt_dma_desc *vd;\n+\tenum dma_status ret;\n+\tunsigned long flags;\n+\tsize_t residue = 0;\n+\n+\tret = dma_cookie_status(chan, cookie, txstate);\n+\tif (ret == DMA_COMPLETE || !txstate)\n+\t\treturn ret;\n+\n+\tspin_lock_irqsave(&achan->vc.lock, flags);\n+\n+\tvd = vchan_find_desc(&achan->vc, cookie);\n+\tif (vd)\n+\t\tresidue = container_of(vd, struct adm_async_desc, vd)->length;\n+\n+\tspin_unlock_irqrestore(&achan->vc.lock, flags);\n+\n+\t/*\n+\t * residue is either the full length if it is in the issued list, or 0\n+\t * if it is in progress.  We have no reliable way of determining\n+\t * anything inbetween\n+\t */\n+\tdma_set_residue(txstate, residue);\n+\n+\tif (achan->error)\n+\t\treturn DMA_ERROR;\n+\n+\treturn ret;\n+}\n+\n+/**\n+ * adm_issue_pending - starts pending transactions\n+ * @chan: dma channel\n+ *\n+ * Issues all pending transactions and starts DMA\n+ */\n+static void adm_issue_pending(struct dma_chan *chan)\n+{\n+\tstruct adm_chan *achan = to_adm_chan(chan);\n+\tunsigned long flags;\n+\n+\tspin_lock_irqsave(&achan->vc.lock, flags);\n+\n+\tif (vchan_issue_pending(&achan->vc) && !achan->curr_txd)\n+\t\tadm_start_dma(achan);\n+\tspin_unlock_irqrestore(&achan->vc.lock, flags);\n+}\n+\n+/**\n+ * adm_dma_free_desc - free descriptor memory\n+ * @vd: virtual descriptor\n+ *\n+ */\n+static void adm_dma_free_desc(struct virt_dma_desc *vd)\n+{\n+\tstruct adm_async_desc *async_desc = container_of(vd,\n+\t\t\tstruct adm_async_desc, vd);\n+\n+\tdma_unmap_single(async_desc->adev->dev, async_desc->dma_addr,\n+\t\t\t async_desc->dma_len, DMA_TO_DEVICE);\n+\tkfree(async_desc->cpl);\n+\tkfree(async_desc);\n+}\n+\n+static void adm_channel_init(struct adm_device *adev, struct adm_chan *achan,\n+\t\t\t     u32 index)\n+{\n+\tachan->id = index;\n+\tachan->adev = adev;\n+\n+\tvchan_init(&achan->vc, &adev->common);\n+\tachan->vc.desc_free = adm_dma_free_desc;\n+}\n+\n+static int adm_dma_probe(struct platform_device *pdev)\n+{\n+\tstruct adm_device *adev;\n+\tint ret;\n+\tu32 i;\n+\n+\tadev = devm_kzalloc(&pdev->dev, sizeof(*adev), GFP_KERNEL);\n+\tif (!adev)\n+\t\treturn -ENOMEM;\n+\n+\tadev->dev = &pdev->dev;\n+\n+\tadev->regs = devm_platform_ioremap_resource(pdev, 0);\n+\tif (IS_ERR(adev->regs))\n+\t\treturn PTR_ERR(adev->regs);\n+\n+\tadev->irq = platform_get_irq(pdev, 0);\n+\tif (adev->irq < 0)\n+\t\treturn adev->irq;\n+\n+\tret = of_property_read_u32(pdev->dev.of_node, \"qcom,ee\", &adev->ee);\n+\tif (ret) {\n+\t\tdev_err(adev->dev, \"Execution environment unspecified\\n\");\n+\t\treturn ret;\n+\t}\n+\n+\tadev->core_clk = devm_clk_get(adev->dev, \"core\");\n+\tif (IS_ERR(adev->core_clk))\n+\t\treturn PTR_ERR(adev->core_clk);\n+\n+\tadev->iface_clk = devm_clk_get(adev->dev, \"iface\");\n+\tif (IS_ERR(adev->iface_clk))\n+\t\treturn PTR_ERR(adev->iface_clk);\n+\n+\tadev->clk_reset = devm_reset_control_get_exclusive(&pdev->dev, \"clk\");\n+\tif (IS_ERR(adev->clk_reset)) {\n+\t\tdev_err(adev->dev, \"failed to get ADM0 reset\\n\");\n+\t\treturn PTR_ERR(adev->clk_reset);\n+\t}\n+\n+\tadev->c0_reset = devm_reset_control_get_exclusive(&pdev->dev, \"c0\");\n+\tif (IS_ERR(adev->c0_reset)) {\n+\t\tdev_err(adev->dev, \"failed to get ADM0 C0 reset\\n\");\n+\t\treturn PTR_ERR(adev->c0_reset);\n+\t}\n+\n+\tadev->c1_reset = devm_reset_control_get_exclusive(&pdev->dev, \"c1\");\n+\tif (IS_ERR(adev->c1_reset)) {\n+\t\tdev_err(adev->dev, \"failed to get ADM0 C1 reset\\n\");\n+\t\treturn PTR_ERR(adev->c1_reset);\n+\t}\n+\n+\tadev->c2_reset = devm_reset_control_get_exclusive(&pdev->dev, \"c2\");\n+\tif (IS_ERR(adev->c2_reset)) {\n+\t\tdev_err(adev->dev, \"failed to get ADM0 C2 reset\\n\");\n+\t\treturn PTR_ERR(adev->c2_reset);\n+\t}\n+\n+\tret = clk_prepare_enable(adev->core_clk);\n+\tif (ret) {\n+\t\tdev_err(adev->dev, \"failed to prepare/enable core clock\\n\");\n+\t\treturn ret;\n+\t}\n+\n+\tret = clk_prepare_enable(adev->iface_clk);\n+\tif (ret) {\n+\t\tdev_err(adev->dev, \"failed to prepare/enable iface clock\\n\");\n+\t\tgoto err_disable_core_clk;\n+\t}\n+\n+\treset_control_assert(adev->clk_reset);\n+\treset_control_assert(adev->c0_reset);\n+\treset_control_assert(adev->c1_reset);\n+\treset_control_assert(adev->c2_reset);\n+\n+\tudelay(2);\n+\n+\treset_control_deassert(adev->clk_reset);\n+\treset_control_deassert(adev->c0_reset);\n+\treset_control_deassert(adev->c1_reset);\n+\treset_control_deassert(adev->c2_reset);\n+\n+\tadev->channels = devm_kcalloc(adev->dev, ADM_MAX_CHANNELS,\n+\t\t\t\t      sizeof(*adev->channels), GFP_KERNEL);\n+\n+\tif (!adev->channels) {\n+\t\tret = -ENOMEM;\n+\t\tgoto err_disable_clks;\n+\t}\n+\n+\t/* allocate and initialize channels */\n+\tINIT_LIST_HEAD(&adev->common.channels);\n+\n+\tfor (i = 0; i < ADM_MAX_CHANNELS; i++)\n+\t\tadm_channel_init(adev, &adev->channels[i], i);\n+\n+\t/* reset CRCIs */\n+\tfor (i = 0; i < 16; i++)\n+\t\twritel(ADM_CRCI_CTL_RST, adev->regs +\n+\t\t\tADM_CRCI_CTL(i, adev->ee));\n+\n+\t/* configure client interfaces */\n+\twritel(ADM_CI_RANGE_START(0x40) | ADM_CI_RANGE_END(0xb0) |\n+\t       ADM_CI_BURST_8_WORDS, adev->regs + ADM_CI_CONF(0));\n+\twritel(ADM_CI_RANGE_START(0x2a) | ADM_CI_RANGE_END(0x2c) |\n+\t       ADM_CI_BURST_8_WORDS, adev->regs + ADM_CI_CONF(1));\n+\twritel(ADM_CI_RANGE_START(0x12) | ADM_CI_RANGE_END(0x28) |\n+\t       ADM_CI_BURST_8_WORDS, adev->regs + ADM_CI_CONF(2));\n+\twritel(ADM_GP_CTL_LP_EN | ADM_GP_CTL_LP_CNT(0xf),\n+\t       adev->regs + ADM_GP_CTL);\n+\n+\tret = devm_request_irq(adev->dev, adev->irq, adm_dma_irq,\n+\t\t\t       0, \"adm_dma\", adev);\n+\tif (ret)\n+\t\tgoto err_disable_clks;\n+\n+\tplatform_set_drvdata(pdev, adev);\n+\n+\tadev->common.dev = adev->dev;\n+\tadev->common.dev->dma_parms = &adev->dma_parms;\n+\n+\t/* set capabilities */\n+\tdma_cap_zero(adev->common.cap_mask);\n+\tdma_cap_set(DMA_SLAVE, adev->common.cap_mask);\n+\tdma_cap_set(DMA_PRIVATE, adev->common.cap_mask);\n+\n+\t/* initialize dmaengine apis */\n+\tadev->common.directions = BIT(DMA_DEV_TO_MEM | DMA_MEM_TO_DEV);\n+\tadev->common.residue_granularity = DMA_RESIDUE_GRANULARITY_DESCRIPTOR;\n+\tadev->common.src_addr_widths = DMA_SLAVE_BUSWIDTH_4_BYTES;\n+\tadev->common.dst_addr_widths = DMA_SLAVE_BUSWIDTH_4_BYTES;\n+\tadev->common.device_free_chan_resources = adm_free_chan;\n+\tadev->common.device_prep_slave_sg = adm_prep_slave_sg;\n+\tadev->common.device_issue_pending = adm_issue_pending;\n+\tadev->common.device_tx_status = adm_tx_status;\n+\tadev->common.device_terminate_all = adm_terminate_all;\n+\tadev->common.device_config = adm_slave_config;\n+\n+\tret = dma_async_device_register(&adev->common);\n+\tif (ret) {\n+\t\tdev_err(adev->dev, \"failed to register dma async device\\n\");\n+\t\tgoto err_disable_clks;\n+\t}\n+\n+\tret = of_dma_controller_register(pdev->dev.of_node,\n+\t\t\t\t\t of_dma_xlate_by_chan_id,\n+\t\t\t\t\t &adev->common);\n+\tif (ret)\n+\t\tgoto err_unregister_dma;\n+\n+\treturn 0;\n+\n+err_unregister_dma:\n+\tdma_async_device_unregister(&adev->common);\n+err_disable_clks:\n+\tclk_disable_unprepare(adev->iface_clk);\n+err_disable_core_clk:\n+\tclk_disable_unprepare(adev->core_clk);\n+\n+\treturn ret;\n+}\n+\n+static int adm_dma_remove(struct platform_device *pdev)\n+{\n+\tstruct adm_device *adev = platform_get_drvdata(pdev);\n+\tstruct adm_chan *achan;\n+\tu32 i;\n+\n+\tof_dma_controller_free(pdev->dev.of_node);\n+\tdma_async_device_unregister(&adev->common);\n+\n+\tfor (i = 0; i < ADM_MAX_CHANNELS; i++) {\n+\t\tachan = &adev->channels[i];\n+\n+\t\t/* mask IRQs for this channel/EE pair */\n+\t\twritel(0, adev->regs + ADM_CH_RSLT_CONF(achan->id, adev->ee));\n+\n+\t\ttasklet_kill(&adev->channels[i].vc.task);\n+\t\tadm_terminate_all(&adev->channels[i].vc.chan);\n+\t}\n+\n+\tdevm_free_irq(adev->dev, adev->irq, adev);\n+\n+\tclk_disable_unprepare(adev->core_clk);\n+\tclk_disable_unprepare(adev->iface_clk);\n+\n+\treturn 0;\n+}\n+\n+static const struct of_device_id adm_of_match[] = {\n+\t{ .compatible = \"qcom,adm\", },\n+\t{}\n+};\n+MODULE_DEVICE_TABLE(of, adm_of_match);\n+\n+static struct platform_driver adm_dma_driver = {\n+\t.probe = adm_dma_probe,\n+\t.remove = adm_dma_remove,\n+\t.driver = {\n+\t\t.name = \"adm-dma-engine\",\n+\t\t.of_match_table = adm_of_match,\n+\t},\n+};\n+\n+module_platform_driver(adm_dma_driver);\n+\n+MODULE_AUTHOR(\"Andy Gross <agross@codeaurora.org>\");\n+MODULE_DESCRIPTION(\"QCOM ADM DMA engine driver\");\n+MODULE_LICENSE(\"GPL v2\");\n"
  },
  {
    "path": "target/linux/ipq806x/patches-5.10/101-5.12-mtd-parsers-Add-Qcom-SMEM-parser.patch",
    "content": "From 803eb124e1a64e42888542c3444bfe6dac412c7f Mon Sep 17 00:00:00 2001\nFrom: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>\nDate: Mon, 4 Jan 2021 09:41:35 +0530\nSubject: mtd: parsers: Add Qcom SMEM parser\n\nNAND based Qualcomm platforms have the partition table populated in the\nShared Memory (SMEM). Hence, add a parser for parsing the partitions\nfrom it.\n\nSigned-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>\nSigned-off-by: Miquel Raynal <miquel.raynal@bootlin.com>\nLink: https://lore.kernel.org/linux-mtd/20210104041137.113075-3-manivannan.sadhasivam@linaro.org\n---\n drivers/mtd/parsers/Kconfig        |   8 ++\n drivers/mtd/parsers/Makefile       |   1 +\n drivers/mtd/parsers/qcomsmempart.c | 170 +++++++++++++++++++++++++++++++++++++\n 3 files changed, 179 insertions(+)\n create mode 100644 drivers/mtd/parsers/qcomsmempart.c\n\n--- a/drivers/mtd/parsers/Kconfig\n+++ b/drivers/mtd/parsers/Kconfig\n@@ -196,6 +196,14 @@ config MTD_REDBOOT_PARTS_READONLY\n \n endif # MTD_REDBOOT_PARTS\n \n+config MTD_QCOMSMEM_PARTS\n+\ttristate \"Qualcomm SMEM NAND flash partition parser\"\n+\tdepends on MTD_NAND_QCOM || COMPILE_TEST\n+\tdepends on QCOM_SMEM\n+\thelp\n+\t  This provides support for parsing partitions from Shared Memory (SMEM)\n+\t  for NAND flash on Qualcomm platforms.\n+\n config MTD_ROUTERBOOT_PARTS\n \ttristate \"RouterBoot flash partition parser\"\n \tdepends on MTD && OF\n--- a/drivers/mtd/parsers/Makefile\n+++ b/drivers/mtd/parsers/Makefile\n@@ -13,4 +13,5 @@ obj-$(CONFIG_MTD_AFS_PARTS)\t\t+= afs.o\n obj-$(CONFIG_MTD_PARSER_TRX)\t\t+= parser_trx.o\n obj-$(CONFIG_MTD_SHARPSL_PARTS)\t\t+= sharpslpart.o\n obj-$(CONFIG_MTD_REDBOOT_PARTS)\t\t+= redboot.o\n+obj-$(CONFIG_MTD_QCOMSMEM_PARTS)\t+= qcomsmempart.o\n obj-$(CONFIG_MTD_ROUTERBOOT_PARTS)\t\t+= routerbootpart.o\n--- /dev/null\n+++ b/drivers/mtd/parsers/qcomsmempart.c\n@@ -0,0 +1,170 @@\n+// SPDX-License-Identifier: GPL-2.0-only\n+/*\n+ * Qualcomm SMEM NAND flash partition parser\n+ *\n+ * Copyright (C) 2020, Linaro Ltd.\n+ */\n+\n+#include <linux/ctype.h>\n+#include <linux/module.h>\n+#include <linux/mtd/mtd.h>\n+#include <linux/mtd/partitions.h>\n+#include <linux/slab.h>\n+#include <linux/soc/qcom/smem.h>\n+\n+#define SMEM_AARM_PARTITION_TABLE\t9\n+#define SMEM_APPS\t\t\t0\n+\n+#define SMEM_FLASH_PART_MAGIC1\t\t0x55ee73aa\n+#define SMEM_FLASH_PART_MAGIC2\t\t0xe35ebddb\n+#define SMEM_FLASH_PTABLE_V3\t\t3\n+#define SMEM_FLASH_PTABLE_V4\t\t4\n+#define SMEM_FLASH_PTABLE_MAX_PARTS_V3\t16\n+#define SMEM_FLASH_PTABLE_MAX_PARTS_V4\t48\n+#define SMEM_FLASH_PTABLE_HDR_LEN\t(4 * sizeof(u32))\n+#define SMEM_FLASH_PTABLE_NAME_SIZE\t16\n+\n+/**\n+ * struct smem_flash_pentry - SMEM Flash partition entry\n+ * @name: Name of the partition\n+ * @offset: Offset in blocks\n+ * @length: Length of the partition in blocks\n+ * @attr: Flags for this partition\n+ */\n+struct smem_flash_pentry {\n+\tchar name[SMEM_FLASH_PTABLE_NAME_SIZE];\n+\t__le32 offset;\n+\t__le32 length;\n+\tu8 attr;\n+} __packed __aligned(4);\n+\n+/**\n+ * struct smem_flash_ptable - SMEM Flash partition table\n+ * @magic1: Partition table Magic 1\n+ * @magic2: Partition table Magic 2\n+ * @version: Partition table version\n+ * @numparts: Number of partitions in this ptable\n+ * @pentry: Flash partition entries belonging to this ptable\n+ */\n+struct smem_flash_ptable {\n+\t__le32 magic1;\n+\t__le32 magic2;\n+\t__le32 version;\n+\t__le32 numparts;\n+\tstruct smem_flash_pentry pentry[SMEM_FLASH_PTABLE_MAX_PARTS_V4];\n+} __packed __aligned(4);\n+\n+static int parse_qcomsmem_part(struct mtd_info *mtd,\n+\t\t\t       const struct mtd_partition **pparts,\n+\t\t\t       struct mtd_part_parser_data *data)\n+{\n+\tstruct smem_flash_pentry *pentry;\n+\tstruct smem_flash_ptable *ptable;\n+\tsize_t len = SMEM_FLASH_PTABLE_HDR_LEN;\n+\tstruct mtd_partition *parts;\n+\tint ret, i, numparts;\n+\tchar *name, *c;\n+\n+\tpr_debug(\"Parsing partition table info from SMEM\\n\");\n+\tptable = qcom_smem_get(SMEM_APPS, SMEM_AARM_PARTITION_TABLE, &len);\n+\tif (IS_ERR(ptable)) {\n+\t\tpr_err(\"Error reading partition table header\\n\");\n+\t\treturn PTR_ERR(ptable);\n+\t}\n+\n+\t/* Verify ptable magic */\n+\tif (le32_to_cpu(ptable->magic1) != SMEM_FLASH_PART_MAGIC1 ||\n+\t    le32_to_cpu(ptable->magic2) != SMEM_FLASH_PART_MAGIC2) {\n+\t\tpr_err(\"Partition table magic verification failed\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\t/* Ensure that # of partitions is less than the max we have allocated */\n+\tnumparts = le32_to_cpu(ptable->numparts);\n+\tif (numparts > SMEM_FLASH_PTABLE_MAX_PARTS_V4) {\n+\t\tpr_err(\"Partition numbers exceed the max limit\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\t/* Find out length of partition data based on table version */\n+\tif (le32_to_cpu(ptable->version) <= SMEM_FLASH_PTABLE_V3) {\n+\t\tlen = SMEM_FLASH_PTABLE_HDR_LEN + SMEM_FLASH_PTABLE_MAX_PARTS_V3 *\n+\t\t\tsizeof(struct smem_flash_pentry);\n+\t} else if (le32_to_cpu(ptable->version) == SMEM_FLASH_PTABLE_V4) {\n+\t\tlen = SMEM_FLASH_PTABLE_HDR_LEN + SMEM_FLASH_PTABLE_MAX_PARTS_V4 *\n+\t\t\tsizeof(struct smem_flash_pentry);\n+\t} else {\n+\t\tpr_err(\"Unknown ptable version (%d)\", le32_to_cpu(ptable->version));\n+\t\treturn -EINVAL;\n+\t}\n+\n+\t/*\n+\t * Now that the partition table header has been parsed, verified\n+\t * and the length of the partition table calculated, read the\n+\t * complete partition table\n+\t */\n+\tptable = qcom_smem_get(SMEM_APPS, SMEM_AARM_PARTITION_TABLE, &len);\n+\tif (IS_ERR_OR_NULL(ptable)) {\n+\t\tpr_err(\"Error reading partition table\\n\");\n+\t\treturn PTR_ERR(ptable);\n+\t}\n+\n+\tparts = kcalloc(numparts, sizeof(*parts), GFP_KERNEL);\n+\tif (!parts)\n+\t\treturn -ENOMEM;\n+\n+\tfor (i = 0; i < numparts; i++) {\n+\t\tpentry = &ptable->pentry[i];\n+\t\tif (pentry->name[0] == '\\0')\n+\t\t\tcontinue;\n+\n+\t\tname = kstrdup(pentry->name, GFP_KERNEL);\n+\t\tif (!name) {\n+\t\t\tret = -ENOMEM;\n+\t\t\tgoto out_free_parts;\n+\t\t}\n+\n+\t\t/* Convert name to lower case */\n+\t\tfor (c = name; *c != '\\0'; c++)\n+\t\t\t*c = tolower(*c);\n+\n+\t\tparts[i].name = name;\n+\t\tparts[i].offset = le32_to_cpu(pentry->offset) * mtd->erasesize;\n+\t\tparts[i].mask_flags = pentry->attr;\n+\t\tparts[i].size = le32_to_cpu(pentry->length) * mtd->erasesize;\n+\t\tpr_debug(\"%d: %s offs=0x%08x size=0x%08x attr:0x%08x\\n\",\n+\t\t\t i, pentry->name, le32_to_cpu(pentry->offset),\n+\t\t\t le32_to_cpu(pentry->length), pentry->attr);\n+\t}\n+\n+\tpr_debug(\"SMEM partition table found: ver: %d len: %d\\n\",\n+\t\t le32_to_cpu(ptable->version), numparts);\n+\t*pparts = parts;\n+\n+\treturn numparts;\n+\n+out_free_parts:\n+\twhile (--i >= 0)\n+\t\tkfree(parts[i].name);\n+\tkfree(parts);\n+\t*pparts = NULL;\n+\n+\treturn ret;\n+}\n+\n+static const struct of_device_id qcomsmem_of_match_table[] = {\n+\t{ .compatible = \"qcom,smem-part\" },\n+\t{},\n+};\n+MODULE_DEVICE_TABLE(of, qcomsmem_of_match_table);\n+\n+static struct mtd_part_parser mtd_parser_qcomsmem = {\n+\t.parse_fn = parse_qcomsmem_part,\n+\t.name = \"qcomsmem\",\n+\t.of_match_table = qcomsmem_of_match_table,\n+};\n+module_mtd_part_parser(mtd_parser_qcomsmem);\n+\n+MODULE_LICENSE(\"GPL v2\");\n+MODULE_AUTHOR(\"Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>\");\n+MODULE_DESCRIPTION(\"Qualcomm SMEM NAND flash partition parser\");\n"
  },
  {
    "path": "target/linux/ipq806x/patches-5.10/101-dwmac-ipq806x-qsgmii-pcs-all-ch-ctl.patch",
    "content": "--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c\n+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c\n@@ -64,6 +64,17 @@\n #define NSS_COMMON_CLK_DIV_SGMII_100\t\t4\n #define NSS_COMMON_CLK_DIV_SGMII_10\t\t49\n \n+#define QSGMII_PCS_ALL_CH_CTL\t\t\t0x80\n+#define QSGMII_PCS_CH_SPEED_FORCE\t\t0x2\n+#define QSGMII_PCS_CH_SPEED_10\t\t\t0x0\n+#define QSGMII_PCS_CH_SPEED_100\t\t\t0x4\n+#define QSGMII_PCS_CH_SPEED_1000\t\t0x8\n+#define QSGMII_PCS_CH_SPEED_MASK\t\t(QSGMII_PCS_CH_SPEED_FORCE | \\\n+\t\t\t\t\t\t QSGMII_PCS_CH_SPEED_10 | \\\n+\t\t\t\t\t\t QSGMII_PCS_CH_SPEED_100 | \\\n+\t\t\t\t\t\t QSGMII_PCS_CH_SPEED_1000)\n+#define QSGMII_PCS_CH_SPEED_SHIFT(x)\t\t(x * 4)\n+\n #define QSGMII_PCS_CAL_LCKDT_CTL\t\t0x120\n #define QSGMII_PCS_CAL_LCKDT_CTL_RST\t\tBIT(19)\n \n@@ -242,6 +253,36 @@ static void ipq806x_gmac_fix_mac_speed(v\n \tipq806x_gmac_set_speed(gmac, speed);\n }\n \n+static int\n+ipq806x_gmac_get_qsgmii_pcs_speed_val(struct platform_device *pdev) {\n+\tstruct device_node *fixed_link_node;\n+\tint rv;\n+\tint fixed_link_speed;\n+\n+\tif (!of_phy_is_fixed_link(pdev->dev.of_node))\n+\t\treturn 0;\n+\n+\tfixed_link_node = of_get_child_by_name(pdev->dev.of_node, \"fixed-link\");\n+\tif (!fixed_link_node)\n+\t\treturn -1;\n+\n+\trv = of_property_read_u32(fixed_link_node, \"speed\", &fixed_link_speed);\n+\tof_node_put(fixed_link_node);\n+\tif (rv)\n+\t\treturn -1;\n+\n+\tswitch (fixed_link_speed) {\n+\tcase SPEED_1000:\n+\t\treturn QSGMII_PCS_CH_SPEED_FORCE | QSGMII_PCS_CH_SPEED_1000;\n+\tcase SPEED_100:\n+\t\treturn QSGMII_PCS_CH_SPEED_FORCE | QSGMII_PCS_CH_SPEED_100;\n+\tcase SPEED_10:\n+\t\treturn QSGMII_PCS_CH_SPEED_FORCE | QSGMII_PCS_CH_SPEED_10;\n+\t}\n+\n+\treturn -1;\n+}\n+\n static int ipq806x_gmac_probe(struct platform_device *pdev)\n {\n \tstruct plat_stmmacenet_data *plat_dat;\n@@ -250,6 +291,7 @@ static int ipq806x_gmac_probe(struct pla\n \tstruct ipq806x_gmac *gmac;\n \tint val;\n \tint err;\n+\tint qsgmii_pcs_speed;\n \n \tval = stmmac_get_platform_resources(pdev, &stmmac_res);\n \tif (val)\n@@ -339,6 +381,17 @@ static int ipq806x_gmac_probe(struct pla\n \t\t\t     0x1ul << QSGMII_PHY_RX_INPUT_EQU_OFFSET |\n \t\t\t     0x2ul << QSGMII_PHY_CDR_PI_SLEW_OFFSET |\n \t\t\t     0xCul << QSGMII_PHY_TX_DRV_AMP_OFFSET);\n+\n+\t\tqsgmii_pcs_speed = ipq806x_gmac_get_qsgmii_pcs_speed_val(pdev);\n+\t\tif (qsgmii_pcs_speed != -1) {\n+\t\t\tregmap_update_bits(\n+\t\t\t    gmac->qsgmii_csr,\n+\t\t\t    QSGMII_PCS_ALL_CH_CTL,\n+\t\t\t    QSGMII_PCS_CH_SPEED_MASK <<\n+\t\t\t\tQSGMII_PCS_CH_SPEED_SHIFT(gmac->id),\n+\t\t\t    qsgmii_pcs_speed <<\n+\t\t\t\tQSGMII_PCS_CH_SPEED_SHIFT(gmac->id));\n+\t\t}\n \t}\n \n \tplat_dat->has_gmac = true;\n"
  },
  {
    "path": "target/linux/ipq806x/patches-5.10/102-mtd-rootfs-conflicts-with-OpenWrt-auto-mounting.patch",
    "content": "From 5001f2e1a325b68dbf225bd17f69a4d3d975cca5 Mon Sep 17 00:00:00 2001\nFrom: John Crispin <john@phrozen.org>\nDate: Thu, 9 Mar 2017 09:31:44 +0100\nSubject: [PATCH 61/69] mtd: \"rootfs\" conflicts with OpenWrt auto mounting\n\nSigned-off-by: John Crispin <john@phrozen.org>\n---\n drivers/mtd/parsers/qcomsmempart.c | 4 ++++\n 1 file changed, 4 insertions(+)\n\n--- a/drivers/mtd/parsers/qcomsmempart.c\n+++ b/drivers/mtd/parsers/qcomsmempart.c\n@@ -132,6 +132,11 @@ static int parse_qcomsmem_part(struct mt\n \t\tparts[i].offset = le32_to_cpu(pentry->offset) * mtd->erasesize;\n \t\tparts[i].mask_flags = pentry->attr;\n \t\tparts[i].size = le32_to_cpu(pentry->length) * mtd->erasesize;\n+\n+\t\t/* \"rootfs\" conflicts with OpenWrt auto mounting */\n+\t\tif (mtd_type_is_nand(mtd) && !strcmp(name, \"rootfs\"))\n+\t\t\tparts[i].name = \"ubi\";\n+\n \t\tpr_debug(\"%d: %s offs=0x%08x size=0x%08x attr:0x%08x\\n\",\n \t\t\t i, pentry->name, le32_to_cpu(pentry->offset),\n \t\t\t le32_to_cpu(pentry->length), pentry->attr);\n"
  },
  {
    "path": "target/linux/ipq806x/patches-5.10/103-ARM-dts-qcom-reduce-pci-IO-size-to-64K.patch",
    "content": "From 84909e85881d67244240c9f40974ce12a51e3886 Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Tue, 11 May 2021 23:09:45 +0200\nSubject: [PATCH] ARM: dts: qcom: reduce pci IO size to 64K\n\nThe current value is probably a typo and is actually uncommon to find\n1MB IO space even on a x86 arch. Also with recent changes to the pci\ndriver, pci1 and pci2 now fails to function as any connected device\nfails any reg read/write. Reduce this to 64K as it should be more than\nenough and 3 * 64K of total IO space doesn't exceed the IO_SPACE_LIMIT\nhardcoded for the ARM arch.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\n---\n arch/arm/boot/dts/qcom-ipq8064.dtsi | 6 +++---\n 1 file changed, 3 insertions(+), 3 deletions(-)\n\n--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi\n+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi\n@@ -1163,7 +1163,7 @@\n \t\t\t#address-cells = <3>;\n \t\t\t#size-cells = <2>;\n \n-\t\t\tranges = <0x81000000 0 0x0fe00000 0x0fe00000 0 0x00100000   /* downstream I/O */\n+\t\t\tranges = <0x81000000 0 0x0fe00000 0x0fe00000 0 0x00010000   /* downstream I/O */\n \t\t\t\t  0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* non-prefetchable memory */\n \n \t\t\tinterrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;\n@@ -1214,7 +1214,7 @@\n \t\t\t#address-cells = <3>;\n \t\t\t#size-cells = <2>;\n \n-\t\t\tranges = <0x81000000 0 0x31e00000 0x31e00000 0 0x00100000   /* downstream I/O */\n+\t\t\tranges = <0x81000000 0 0x31e00000 0x31e00000 0 0x00010000   /* downstream I/O */\n \t\t\t\t  0x82000000 0 0x2e000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */\n \n \t\t\tinterrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;\n@@ -1265,7 +1265,7 @@\n \t\t\t#address-cells = <3>;\n \t\t\t#size-cells = <2>;\n \n-\t\t\tranges = <0x81000000 0 0x35e00000 0x35e00000 0 0x00100000   /* downstream I/O */\n+\t\t\tranges = <0x81000000 0 0x35e00000 0x35e00000 0 0x00010000   /* downstream I/O */\n \t\t\t\t  0x82000000 0 0x32000000 0x32000000 0 0x03e00000>; /* non-prefetchable memory */\n \n \t\t\tinterrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;\n"
  },
  {
    "path": "target/linux/ipq806x/patches-5.10/104-1-drivers-thermal-tsens-Add-VER_0-tsens-version.patch",
    "content": "From 5c7d1181056feef0b58fb2f556f55e170ba5b479 Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Sat, 25 Jul 2020 19:14:59 +0200\nSubject: [PATCH 01/10] drivers: thermal: tsens: Add VER_0 tsens version\n\nVER_0 is used to describe device based on tsens version before v0.1.\nThese device are devices based on msm8960 for example apq8064 or\nipq806x.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nReviewed-by: Thara Gopinath <thara.gopinath@linaro.org>\nReported-by: kernel test robot <lkp@intel.com>\nReported-by: Dan Carpenter <dan.carpenter@oracle.com>\n---\n drivers/thermal/qcom/tsens.c | 150 ++++++++++++++++++++++++++++-------\n drivers/thermal/qcom/tsens.h |   4 +-\n 2 files changed, 124 insertions(+), 30 deletions(-)\n\n--- a/drivers/thermal/qcom/tsens.c\n+++ b/drivers/thermal/qcom/tsens.c\n@@ -12,6 +12,7 @@\n #include <linux/of.h>\n #include <linux/of_address.h>\n #include <linux/of_platform.h>\n+#include <linux/mfd/syscon.h>\n #include <linux/platform_device.h>\n #include <linux/pm.h>\n #include <linux/regmap.h>\n@@ -515,6 +516,15 @@ static irqreturn_t tsens_irq_thread(int\n \t\t\tdev_dbg(priv->dev, \"[%u] %s: no violation:  %d\\n\",\n \t\t\t\thw_id, __func__, temp);\n \t\t}\n+\n+\t\tif (tsens_version(priv) < VER_0_1) {\n+\t\t\t/* Constraint: There is only 1 interrupt control register for all\n+\t\t\t * 11 temperature sensor. So monitoring more than 1 sensor based\n+\t\t\t * on interrupts will yield inconsistent result. To overcome this\n+\t\t\t * issue we will monitor only sensor 0 which is the master sensor.\n+\t\t\t */\n+\t\t\tbreak;\n+\t\t}\n \t}\n \n \treturn IRQ_HANDLED;\n@@ -530,6 +540,13 @@ static int tsens_set_trips(void *_sensor\n \tint high_val, low_val, cl_high, cl_low;\n \tu32 hw_id = s->hw_id;\n \n+\tif (tsens_version(priv) < VER_0_1) {\n+\t\t/* Pre v0.1 IP had a single register for each type of interrupt\n+\t\t * and thresholds\n+\t\t */\n+\t\thw_id = 0;\n+\t}\n+\n \tdev_dbg(dev, \"[%u] %s: proposed thresholds: (%d:%d)\\n\",\n \t\thw_id, __func__, low, high);\n \n@@ -584,18 +601,21 @@ int get_temp_tsens_valid(const struct ts\n \tu32 valid;\n \tint ret;\n \n-\tret = regmap_field_read(priv->rf[valid_idx], &valid);\n-\tif (ret)\n-\t\treturn ret;\n-\twhile (!valid) {\n-\t\t/* Valid bit is 0 for 6 AHB clock cycles.\n-\t\t * At 19.2MHz, 1 AHB clock is ~60ns.\n-\t\t * We should enter this loop very, very rarely.\n-\t\t */\n-\t\tndelay(400);\n+\t/* VER_0 doesn't have VALID bit */\n+\tif (tsens_version(priv) >= VER_0_1) {\n \t\tret = regmap_field_read(priv->rf[valid_idx], &valid);\n \t\tif (ret)\n \t\t\treturn ret;\n+\t\twhile (!valid) {\n+\t\t\t/* Valid bit is 0 for 6 AHB clock cycles.\n+\t\t\t * At 19.2MHz, 1 AHB clock is ~60ns.\n+\t\t\t * We should enter this loop very, very rarely.\n+\t\t\t */\n+\t\t\tndelay(400);\n+\t\t\tret = regmap_field_read(priv->rf[valid_idx], &valid);\n+\t\t\tif (ret)\n+\t\t\t\treturn ret;\n+\t\t}\n \t}\n \n \t/* Valid bit is set, OK to read the temperature */\n@@ -608,15 +628,29 @@ int get_temp_common(const struct tsens_s\n {\n \tstruct tsens_priv *priv = s->priv;\n \tint hw_id = s->hw_id;\n-\tint last_temp = 0, ret;\n+\tint last_temp = 0, ret, trdy;\n+\tunsigned long timeout;\n \n-\tret = regmap_field_read(priv->rf[LAST_TEMP_0 + hw_id], &last_temp);\n-\tif (ret)\n-\t\treturn ret;\n+\ttimeout = jiffies + usecs_to_jiffies(TIMEOUT_US);\n+\tdo {\n+\t\tif (tsens_version(priv) == VER_0) {\n+\t\t\tret = regmap_field_read(priv->rf[TRDY], &trdy);\n+\t\t\tif (ret)\n+\t\t\t\treturn ret;\n+\t\t\tif (!trdy)\n+\t\t\t\tcontinue;\n+\t\t}\n \n-\t*temp = code_to_degc(last_temp, s) * 1000;\n+\t\tret = regmap_field_read(priv->rf[LAST_TEMP_0 + hw_id], &last_temp);\n+\t\tif (ret)\n+\t\t\treturn ret;\n \n-\treturn 0;\n+\t\t*temp = code_to_degc(last_temp, s) * 1000;\n+\n+\t\treturn 0;\n+\t} while (time_before(jiffies, timeout));\n+\n+\treturn -ETIMEDOUT;\n }\n \n #ifdef CONFIG_DEBUG_FS\n@@ -738,19 +772,34 @@ int __init init_common(struct tsens_priv\n \t\tpriv->tm_offset = 0x1000;\n \t}\n \n-\tres = platform_get_resource(op, IORESOURCE_MEM, 0);\n-\ttm_base = devm_ioremap_resource(dev, res);\n-\tif (IS_ERR(tm_base)) {\n-\t\tret = PTR_ERR(tm_base);\n-\t\tgoto err_put_device;\n+\tif (tsens_version(priv) >= VER_0_1) {\n+\t\tres = platform_get_resource(op, IORESOURCE_MEM, 0);\n+\t\ttm_base = devm_ioremap_resource(dev, res);\n+\t\tif (IS_ERR(tm_base)) {\n+\t\t\tret = PTR_ERR(tm_base);\n+\t\t\tgoto err_put_device;\n+\t\t}\n+\n+\t\tpriv->tm_map = devm_regmap_init_mmio(dev, tm_base, &tsens_config);\n+\t} else { /* VER_0 share the same gcc regs using a syscon */\n+\t\tstruct device *parent = priv->dev->parent;\n+\n+\t\tif (parent)\n+\t\t\tpriv->tm_map = syscon_node_to_regmap(parent->of_node);\n \t}\n \n-\tpriv->tm_map = devm_regmap_init_mmio(dev, tm_base, &tsens_config);\n-\tif (IS_ERR(priv->tm_map)) {\n-\t\tret = PTR_ERR(priv->tm_map);\n+\tif (IS_ERR_OR_NULL(priv->tm_map)) {\n+\t\tif (!priv->tm_map)\n+\t\t\tret = -ENODEV;\n+\t\telse\n+\t\t\tret = PTR_ERR(priv->tm_map);\n \t\tgoto err_put_device;\n \t}\n \n+\t/* VER_0 have only tm_map */\n+\tif (!priv->srot_map)\n+\t\tpriv->srot_map = priv->tm_map;\n+\n \tif (tsens_version(priv) > VER_0_1) {\n \t\tfor (i = VER_MAJOR; i <= VER_STEP; i++) {\n \t\t\tpriv->rf[i] = devm_regmap_field_alloc(dev, priv->srot_map,\n@@ -771,6 +820,10 @@ int __init init_common(struct tsens_priv\n \t\tret = PTR_ERR(priv->rf[TSENS_EN]);\n \t\tgoto err_put_device;\n \t}\n+\t/* in VER_0 TSENS need to be explicitly enabled */\n+\tif (tsens_version(priv) == VER_0)\n+\t\tregmap_field_write(priv->rf[TSENS_EN], 1);\n+\n \tret = regmap_field_read(priv->rf[TSENS_EN], &enabled);\n \tif (ret)\n \t\tgoto err_put_device;\n@@ -793,6 +846,19 @@ int __init init_common(struct tsens_priv\n \t\tgoto err_put_device;\n \t}\n \n+\tpriv->rf[TSENS_SW_RST] =\n+\t\tdevm_regmap_field_alloc(dev, priv->srot_map, priv->fields[TSENS_SW_RST]);\n+\tif (IS_ERR(priv->rf[TSENS_SW_RST])) {\n+\t\tret = PTR_ERR(priv->rf[TSENS_SW_RST]);\n+\t\tgoto err_put_device;\n+\t}\n+\n+\tpriv->rf[TRDY] = devm_regmap_field_alloc(dev, priv->tm_map, priv->fields[TRDY]);\n+\tif (IS_ERR(priv->rf[TRDY])) {\n+\t\tret = PTR_ERR(priv->rf[TRDY]);\n+\t\tgoto err_put_device;\n+\t}\n+\n \t/* This loop might need changes if enum regfield_ids is reordered */\n \tfor (j = LAST_TEMP_0; j <= UP_THRESH_15; j += 16) {\n \t\tfor (i = 0; i < priv->feat->max_sensors; i++) {\n@@ -808,7 +874,7 @@ int __init init_common(struct tsens_priv\n \t\t}\n \t}\n \n-\tif (priv->feat->crit_int) {\n+\tif (priv->feat->crit_int || tsens_version(priv) < VER_0_1) {\n \t\t/* Loop might need changes if enum regfield_ids is reordered */\n \t\tfor (j = CRITICAL_STATUS_0; j <= CRIT_THRESH_15; j += 16) {\n \t\t\tfor (i = 0; i < priv->feat->max_sensors; i++) {\n@@ -846,7 +912,11 @@ int __init init_common(struct tsens_priv\n \t}\n \n \tspin_lock_init(&priv->ul_lock);\n-\ttsens_enable_irq(priv);\n+\n+\t/* VER_0 interrupt doesn't need to be enabled */\n+\tif (tsens_version(priv) >= VER_0_1)\n+\t\ttsens_enable_irq(priv);\n+\n \ttsens_debug_init(op);\n \n err_put_device:\n@@ -945,10 +1015,19 @@ static int tsens_register_irq(struct tse\n \t\tif (irq == -ENXIO)\n \t\t\tret = 0;\n \t} else {\n-\t\tret = devm_request_threaded_irq(&pdev->dev, irq,\n-\t\t\t\t\t\tNULL, thread_fn,\n-\t\t\t\t\t\tIRQF_ONESHOT,\n-\t\t\t\t\t\tdev_name(&pdev->dev), priv);\n+\t\t/* VER_0 interrupt is TRIGGER_RISING, VER_0_1 and up is ONESHOT */\n+\t\tif (tsens_version(priv) == VER_0)\n+\t\t\tret = devm_request_threaded_irq(&pdev->dev, irq,\n+\t\t\t\t\t\t\tthread_fn, NULL,\n+\t\t\t\t\t\t\tIRQF_TRIGGER_RISING,\n+\t\t\t\t\t\t\tdev_name(&pdev->dev),\n+\t\t\t\t\t\t\tpriv);\n+\t\telse\n+\t\t\tret = devm_request_threaded_irq(&pdev->dev, irq, NULL,\n+\t\t\t\t\t\t\tthread_fn, IRQF_ONESHOT,\n+\t\t\t\t\t\t\tdev_name(&pdev->dev),\n+\t\t\t\t\t\t\tpriv);\n+\n \t\tif (ret)\n \t\t\tdev_err(&pdev->dev, \"%s: failed to get irq\\n\",\n \t\t\t\t__func__);\n@@ -977,6 +1056,19 @@ static int tsens_register(struct tsens_p\n \t\t\tpriv->ops->enable(priv, i);\n \t}\n \n+\t/* VER_0 require to set MIN and MAX THRESH\n+\t * These 2 regs are set using the:\n+\t * - CRIT_THRESH_0 for MAX THRESH hardcoded to 120°C\n+\t * - CRIT_THRESH_1 for MIN THRESH hardcoded to   0°C\n+\t */\n+\tif (tsens_version(priv) < VER_0_1) {\n+\t\tregmap_field_write(priv->rf[CRIT_THRESH_0],\n+\t\t\t\t   tsens_mC_to_hw(priv->sensor, 120000));\n+\n+\t\tregmap_field_write(priv->rf[CRIT_THRESH_1],\n+\t\t\t\t   tsens_mC_to_hw(priv->sensor, 0));\n+\t}\n+\n \tret = tsens_register_irq(priv, \"uplow\", tsens_irq_thread);\n \tif (ret < 0)\n \t\treturn ret;\n--- a/drivers/thermal/qcom/tsens.h\n+++ b/drivers/thermal/qcom/tsens.h\n@@ -13,6 +13,7 @@\n #define CAL_DEGC_PT2\t\t120\n #define SLOPE_FACTOR\t\t1000\n #define SLOPE_DEFAULT\t\t3200\n+#define TIMEOUT_US\t\t100\n #define THRESHOLD_MAX_ADC_CODE\t0x3ff\n #define THRESHOLD_MIN_ADC_CODE\t0x0\n \n@@ -25,7 +26,8 @@ struct tsens_priv;\n \n /* IP version numbers in ascending order */\n enum tsens_ver {\n-\tVER_0_1 = 0,\n+\tVER_0 = 0,\n+\tVER_0_1,\n \tVER_1_X,\n \tVER_2_X,\n };\n"
  },
  {
    "path": "target/linux/ipq806x/patches-5.10/104-2-drivers-thermal-tsens-Don-t-hardcode-sensor-slope.patch",
    "content": "From efa0d50a6c5ec7619371dfe4d3e6ca54b73787d5 Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Wed, 25 Nov 2020 16:47:21 +0100\nSubject: [PATCH 02/10] drivers: thermal: tsens: Don't hardcode sensor slope\n\nFunction compute_intercept_slope hardcode the sensor slope to\nSLOPE_DEFAULT. Change this and use the default value only if a slope is\nnot defined. This is needed for tsens VER_0 that has a hardcoded slope\ntable.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nReviewed-by: Thara Gopinath <thara.gopinath@linaro.org>\n---\n drivers/thermal/qcom/tsens.c | 3 ++-\n 1 file changed, 2 insertions(+), 1 deletion(-)\n\n--- a/drivers/thermal/qcom/tsens.c\n+++ b/drivers/thermal/qcom/tsens.c\n@@ -86,7 +86,8 @@ void compute_intercept_slope(struct tsen\n \t\t\t\"%s: sensor%d - data_point1:%#x data_point2:%#x\\n\",\n \t\t\t__func__, i, p1[i], p2[i]);\n \n-\t\tpriv->sensor[i].slope = SLOPE_DEFAULT;\n+\t\tif (!priv->sensor[i].slope)\n+\t\t\tpriv->sensor[i].slope = SLOPE_DEFAULT;\n \t\tif (mode == TWO_PT_CALIB) {\n \t\t\t/*\n \t\t\t * slope (m) = adc_code2 - adc_code1 (y2 - y1)/\n"
  },
  {
    "path": "target/linux/ipq806x/patches-5.10/104-3-drivers-thermal-tsens-Convert-msm8960-to-reg_field.patch",
    "content": "From 6bac2e2fa36c2d7c304768a689d8b73155b90aa2 Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Wed, 25 Nov 2020 17:15:51 +0100\nSubject: [PATCH 03/10] drivers: thermal: tsens: Convert msm8960 to reg_field\n\nConvert msm9860 driver to reg_field to use the init_common\nfunction.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nAcked-by: Thara Gopinath <thara.gopinath@linaro.org>\n---\n drivers/thermal/qcom/tsens-8960.c | 80 ++++++++++++++++++++++++++++++-\n 1 file changed, 79 insertions(+), 1 deletion(-)\n\n--- a/drivers/thermal/qcom/tsens-8960.c\n+++ b/drivers/thermal/qcom/tsens-8960.c\n@@ -51,11 +51,22 @@\n #define MIN_LIMIT_TH\t\t0x0\n #define MAX_LIMIT_TH\t\t0xff\n \n-#define S0_STATUS_ADDR\t\t0x3628\n #define INT_STATUS_ADDR\t\t0x363c\n #define TRDY_MASK\t\tBIT(7)\n #define TIMEOUT_US\t\t100\n \n+#define S0_STATUS_OFF\t\t0x3628\n+#define S1_STATUS_OFF\t\t0x362c\n+#define S2_STATUS_OFF\t\t0x3630\n+#define S3_STATUS_OFF\t\t0x3634\n+#define S4_STATUS_OFF\t\t0x3638\n+#define S5_STATUS_OFF\t\t0x3664  /* Sensors 5-10 found on apq8064/msm8960 */\n+#define S6_STATUS_OFF\t\t0x3668\n+#define S7_STATUS_OFF\t\t0x366c\n+#define S8_STATUS_OFF\t\t0x3670\n+#define S9_STATUS_OFF\t\t0x3674\n+#define S10_STATUS_OFF\t\t0x3678\n+\n static int suspend_8960(struct tsens_priv *priv)\n {\n \tint ret;\n@@ -269,6 +280,71 @@ static int get_temp_8960(const struct ts\n \treturn -ETIMEDOUT;\n }\n \n+static struct tsens_features tsens_8960_feat = {\n+\t.ver_major\t= VER_0,\n+\t.crit_int\t= 0,\n+\t.adc\t\t= 1,\n+\t.srot_split\t= 0,\n+\t.max_sensors\t= 11,\n+};\n+\n+static const struct reg_field tsens_8960_regfields[MAX_REGFIELDS] = {\n+\t/* ----- SROT ------ */\n+\t/* No VERSION information */\n+\n+\t/* CNTL */\n+\t[TSENS_EN]     = REG_FIELD(CNTL_ADDR,  0, 0),\n+\t[TSENS_SW_RST] = REG_FIELD(CNTL_ADDR,  1, 1),\n+\t/* 8960 has 5 sensors, 8660 has 11, we only handle 5 */\n+\t[SENSOR_EN]    = REG_FIELD(CNTL_ADDR,  3, 7),\n+\n+\t/* ----- TM ------ */\n+\t/* INTERRUPT ENABLE */\n+\t/* NO INTERRUPT ENABLE */\n+\n+\t/* Single UPPER/LOWER TEMPERATURE THRESHOLD for all sensors */\n+\t[LOW_THRESH_0]   = REG_FIELD(THRESHOLD_ADDR,  0,  7),\n+\t[UP_THRESH_0]    = REG_FIELD(THRESHOLD_ADDR,  8, 15),\n+\t/* MIN_THRESH_0 and MAX_THRESH_0 are not present in the regfield\n+\t * Recycle CRIT_THRESH_0 and 1 to set the required regs to hardcoded temp\n+\t * MIN_THRESH_0 -> CRIT_THRESH_1\n+\t * MAX_THRESH_0 -> CRIT_THRESH_0\n+\t */\n+\t[CRIT_THRESH_1]   = REG_FIELD(THRESHOLD_ADDR, 16, 23),\n+\t[CRIT_THRESH_0]   = REG_FIELD(THRESHOLD_ADDR, 24, 31),\n+\n+\t/* UPPER/LOWER INTERRUPT [CLEAR/STATUS] */\n+\t/* 1 == clear, 0 == normal operation */\n+\t[LOW_INT_CLEAR_0]   = REG_FIELD(CNTL_ADDR,  9,  9),\n+\t[UP_INT_CLEAR_0]    = REG_FIELD(CNTL_ADDR, 10, 10),\n+\n+\t/* NO CRITICAL INTERRUPT SUPPORT on 8960 */\n+\n+\t/* Sn_STATUS */\n+\t[LAST_TEMP_0]  = REG_FIELD(S0_STATUS_OFF,  0,  7),\n+\t[LAST_TEMP_1]  = REG_FIELD(S1_STATUS_OFF,  0,  7),\n+\t[LAST_TEMP_2]  = REG_FIELD(S2_STATUS_OFF,  0,  7),\n+\t[LAST_TEMP_3]  = REG_FIELD(S3_STATUS_OFF,  0,  7),\n+\t[LAST_TEMP_4]  = REG_FIELD(S4_STATUS_OFF,  0,  7),\n+\t[LAST_TEMP_5]  = REG_FIELD(S5_STATUS_OFF,  0,  7),\n+\t[LAST_TEMP_6]  = REG_FIELD(S6_STATUS_OFF,  0,  7),\n+\t[LAST_TEMP_7]  = REG_FIELD(S7_STATUS_OFF,  0,  7),\n+\t[LAST_TEMP_8]  = REG_FIELD(S8_STATUS_OFF,  0,  7),\n+\t[LAST_TEMP_9]  = REG_FIELD(S9_STATUS_OFF,  0,  7),\n+\t[LAST_TEMP_10] = REG_FIELD(S10_STATUS_OFF, 0,  7),\n+\n+\t/* No VALID field on 8960 */\n+\t/* TSENS_INT_STATUS bits: 1 == threshold violated */\n+\t[MIN_STATUS_0] = REG_FIELD(INT_STATUS_ADDR, 0, 0),\n+\t[LOWER_STATUS_0] = REG_FIELD(INT_STATUS_ADDR, 1, 1),\n+\t[UPPER_STATUS_0] = REG_FIELD(INT_STATUS_ADDR, 2, 2),\n+\t/* No CRITICAL field on 8960 */\n+\t[MAX_STATUS_0] = REG_FIELD(INT_STATUS_ADDR, 3, 3),\n+\n+\t/* TRDY: 1=ready, 0=in progress */\n+\t[TRDY] = REG_FIELD(INT_STATUS_ADDR, 7, 7),\n+};\n+\n static const struct tsens_ops ops_8960 = {\n \t.init\t\t= init_8960,\n \t.calibrate\t= calibrate_8960,\n@@ -282,4 +358,6 @@ static const struct tsens_ops ops_8960 =\n struct tsens_plat_data data_8960 = {\n \t.num_sensors\t= 11,\n \t.ops\t\t= &ops_8960,\n+\t.feat\t\t= &tsens_8960_feat,\n+\t.fields\t\t= tsens_8960_regfields,\n };\n"
  },
  {
    "path": "target/linux/ipq806x/patches-5.10/104-4-drivers-thermal-tsens-Use-init_common-for-msm8960.patch",
    "content": "From c04f98a496929f75d75c65115d5717423c3d0634 Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Wed, 25 Nov 2020 17:16:36 +0100\nSubject: [PATCH 04/10] drivers: thermal: tsens: Use init_common for msm8960\n\nUse init_common and drop custom init for msm8960.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nReviewed-by: Thara Gopinath <thara.gopinath@linaro.org>\n---\n drivers/thermal/qcom/tsens-8960.c | 52 +------------------------------\n 1 file changed, 1 insertion(+), 51 deletions(-)\n\n--- a/drivers/thermal/qcom/tsens-8960.c\n+++ b/drivers/thermal/qcom/tsens-8960.c\n@@ -173,56 +173,6 @@ static void disable_8960(struct tsens_pr\n \tregmap_write(priv->tm_map, CNTL_ADDR, reg_cntl);\n }\n \n-static int init_8960(struct tsens_priv *priv)\n-{\n-\tint ret, i;\n-\tu32 reg_cntl;\n-\n-\tpriv->tm_map = dev_get_regmap(priv->dev, NULL);\n-\tif (!priv->tm_map)\n-\t\treturn -ENODEV;\n-\n-\t/*\n-\t * The status registers for each sensor are discontiguous\n-\t * because some SoCs have 5 sensors while others have more\n-\t * but the control registers stay in the same place, i.e\n-\t * directly after the first 5 status registers.\n-\t */\n-\tfor (i = 0; i < priv->num_sensors; i++) {\n-\t\tif (i >= 5)\n-\t\t\tpriv->sensor[i].status = S0_STATUS_ADDR + 40;\n-\t\tpriv->sensor[i].status += i * 4;\n-\t}\n-\n-\treg_cntl = SW_RST;\n-\tret = regmap_update_bits(priv->tm_map, CNTL_ADDR, SW_RST, reg_cntl);\n-\tif (ret)\n-\t\treturn ret;\n-\n-\tif (priv->num_sensors > 1) {\n-\t\treg_cntl |= SLP_CLK_ENA | (MEASURE_PERIOD << 18);\n-\t\treg_cntl &= ~SW_RST;\n-\t\tret = regmap_update_bits(priv->tm_map, CONFIG_ADDR,\n-\t\t\t\t\t CONFIG_MASK, CONFIG);\n-\t} else {\n-\t\treg_cntl |= SLP_CLK_ENA_8660 | (MEASURE_PERIOD << 16);\n-\t\treg_cntl &= ~CONFIG_MASK_8660;\n-\t\treg_cntl |= CONFIG_8660 << CONFIG_SHIFT_8660;\n-\t}\n-\n-\treg_cntl |= GENMASK(priv->num_sensors - 1, 0) << SENSOR0_SHIFT;\n-\tret = regmap_write(priv->tm_map, CNTL_ADDR, reg_cntl);\n-\tif (ret)\n-\t\treturn ret;\n-\n-\treg_cntl |= EN;\n-\tret = regmap_write(priv->tm_map, CNTL_ADDR, reg_cntl);\n-\tif (ret)\n-\t\treturn ret;\n-\n-\treturn 0;\n-}\n-\n static int calibrate_8960(struct tsens_priv *priv)\n {\n \tint i;\n@@ -346,7 +296,7 @@ static const struct reg_field tsens_8960\n };\n \n static const struct tsens_ops ops_8960 = {\n-\t.init\t\t= init_8960,\n+\t.init\t\t= init_common,\n \t.calibrate\t= calibrate_8960,\n \t.get_temp\t= get_temp_8960,\n \t.enable\t\t= enable_8960,\n"
  },
  {
    "path": "target/linux/ipq806x/patches-5.10/104-5-drivers-thermal-tsens-Fix-bug-in-sensor-enable-for-m.patch",
    "content": "From b3e8bd33b84a6b6c863bd1733bd15b5f1483b8ab Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Wed, 25 Nov 2020 17:06:55 +0100\nSubject: [PATCH 05/10] drivers: thermal: tsens: Fix bug in sensor enable for\n msm8960\n\nDevice based on tsens VER_0 contains a hardware bug that results in some\nproblem with sensor enablement. Sensor id 6-11 can't be enabled\nselectively and all of them must be enabled in one step.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nAcked-by: Thara Gopinath <thara.gopinath@linaro.org>\n---\n drivers/thermal/qcom/tsens-8960.c | 23 ++++++++++++++++++++---\n 1 file changed, 20 insertions(+), 3 deletions(-)\n\n--- a/drivers/thermal/qcom/tsens-8960.c\n+++ b/drivers/thermal/qcom/tsens-8960.c\n@@ -27,9 +27,9 @@\n #define EN\t\t\tBIT(0)\n #define SW_RST\t\t\tBIT(1)\n #define SENSOR0_EN\t\tBIT(3)\n+#define MEASURE_PERIOD\t\tBIT(18)\n #define SLP_CLK_ENA\t\tBIT(26)\n #define SLP_CLK_ENA_8660\tBIT(24)\n-#define MEASURE_PERIOD\t\t1\n #define SENSOR0_SHIFT\t\t3\n \n /* INT_STATUS_ADDR bitmasks */\n@@ -126,17 +126,34 @@ static int resume_8960(struct tsens_priv\n static int enable_8960(struct tsens_priv *priv, int id)\n {\n \tint ret;\n-\tu32 reg, mask;\n+\tu32 reg, mask = BIT(id);\n \n \tret = regmap_read(priv->tm_map, CNTL_ADDR, &reg);\n \tif (ret)\n \t\treturn ret;\n \n-\tmask = BIT(id + SENSOR0_SHIFT);\n+\t/* HARDWARE BUG:\n+\t * On platforms with more than 6 sensors, all remaining sensors\n+\t * must be enabled together, otherwise undefined results are expected.\n+\t * (Sensor 6-7 disabled, Sensor 3 disabled...) In the original driver,\n+\t * all the sensors are enabled in one step hence this bug is not\n+\t * triggered.\n+\t */\n+\tif (id > 5)\n+\t\tmask = GENMASK(10, 6);\n+\n+\tmask <<= SENSOR0_SHIFT;\n+\n+\t/* Sensors already enabled. Skip. */\n+\tif ((reg & mask) == mask)\n+\t\treturn 0;\n+\n \tret = regmap_write(priv->tm_map, CNTL_ADDR, reg | SW_RST);\n \tif (ret)\n \t\treturn ret;\n \n+\treg |= MEASURE_PERIOD;\n+\n \tif (priv->num_sensors > 1)\n \t\treg |= mask | SLP_CLK_ENA | EN;\n \telse\n"
  },
  {
    "path": "target/linux/ipq806x/patches-5.10/104-6-drivers-thermal-tsens-Replace-custom-8960-apis-with-.patch",
    "content": "From 1ff9f982051759e0387e8c7e793b49c48eae291d Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Wed, 25 Nov 2020 17:11:05 +0100\nSubject: [PATCH 06/10] drivers: thermal: tsens: Replace custom 8960 apis with\n generic apis\n\nRework calibrate function to use common function. Derive the offset from\na missing hardcoded slope table and the data from the nvmem calib\nefuses.\nDrop custom get_temp function and use generic api.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nAcked-by: Thara Gopinath <thara.gopinath@linaro.org>\n---\n drivers/thermal/qcom/tsens-8960.c | 56 +++++++++----------------------\n 1 file changed, 15 insertions(+), 41 deletions(-)\n\n--- a/drivers/thermal/qcom/tsens-8960.c\n+++ b/drivers/thermal/qcom/tsens-8960.c\n@@ -67,6 +67,13 @@\n #define S9_STATUS_OFF\t\t0x3674\n #define S10_STATUS_OFF\t\t0x3678\n \n+/* Original slope - 200 to compensate mC to C inaccuracy */\n+static u32 tsens_msm8960_slope[] = {\n+\t\t\t976, 976, 954, 976,\n+\t\t\t911, 932, 932, 999,\n+\t\t\t932, 999, 932\n+\t\t\t};\n+\n static int suspend_8960(struct tsens_priv *priv)\n {\n \tint ret;\n@@ -194,9 +201,7 @@ static int calibrate_8960(struct tsens_p\n {\n \tint i;\n \tchar *data;\n-\n-\tssize_t num_read = priv->num_sensors;\n-\tstruct tsens_sensor *s = priv->sensor;\n+\tu32 p1[11];\n \n \tdata = qfprom_read(priv->dev, \"calib\");\n \tif (IS_ERR(data))\n@@ -204,49 +209,18 @@ static int calibrate_8960(struct tsens_p\n \tif (IS_ERR(data))\n \t\treturn PTR_ERR(data);\n \n-\tfor (i = 0; i < num_read; i++, s++)\n-\t\ts->offset = data[i];\n+\tfor (i = 0; i < priv->num_sensors; i++) {\n+\t\tp1[i] = data[i];\n+\t\tpriv->sensor[i].slope = tsens_msm8960_slope[i];\n+\t}\n+\n+\tcompute_intercept_slope(priv, p1, NULL, ONE_PT_CALIB);\n \n \tkfree(data);\n \n \treturn 0;\n }\n \n-/* Temperature on y axis and ADC-code on x-axis */\n-static inline int code_to_mdegC(u32 adc_code, const struct tsens_sensor *s)\n-{\n-\tint slope, offset;\n-\n-\tslope = thermal_zone_get_slope(s->tzd);\n-\toffset = CAL_MDEGC - slope * s->offset;\n-\n-\treturn adc_code * slope + offset;\n-}\n-\n-static int get_temp_8960(const struct tsens_sensor *s, int *temp)\n-{\n-\tint ret;\n-\tu32 code, trdy;\n-\tstruct tsens_priv *priv = s->priv;\n-\tunsigned long timeout;\n-\n-\ttimeout = jiffies + usecs_to_jiffies(TIMEOUT_US);\n-\tdo {\n-\t\tret = regmap_read(priv->tm_map, INT_STATUS_ADDR, &trdy);\n-\t\tif (ret)\n-\t\t\treturn ret;\n-\t\tif (!(trdy & TRDY_MASK))\n-\t\t\tcontinue;\n-\t\tret = regmap_read(priv->tm_map, s->status, &code);\n-\t\tif (ret)\n-\t\t\treturn ret;\n-\t\t*temp = code_to_mdegC(code, s);\n-\t\treturn 0;\n-\t} while (time_before(jiffies, timeout));\n-\n-\treturn -ETIMEDOUT;\n-}\n-\n static struct tsens_features tsens_8960_feat = {\n \t.ver_major\t= VER_0,\n \t.crit_int\t= 0,\n@@ -315,7 +289,7 @@ static const struct reg_field tsens_8960\n static const struct tsens_ops ops_8960 = {\n \t.init\t\t= init_common,\n \t.calibrate\t= calibrate_8960,\n-\t.get_temp\t= get_temp_8960,\n+\t.get_temp\t= get_temp_common,\n \t.enable\t\t= enable_8960,\n \t.disable\t= disable_8960,\n \t.suspend\t= suspend_8960,\n"
  },
  {
    "path": "target/linux/ipq806x/patches-5.10/104-7-drivers-thermal-tsens-Drop-unused-define-for-msm8960.patch",
    "content": "From 5716a61239c6ac9ceb137e825e93c3aea06c4634 Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Fri, 19 Mar 2021 00:48:23 +0100\nSubject: [PATCH 07/10] drivers: thermal: tsens: Drop unused define for msm8960\n\nDrop unused define for msm8960 replaced by generic api and reg_field.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nReviewed-by: Thara Gopinath <thara.gopinath@linaro.org>\n---\n drivers/thermal/qcom/tsens-8960.c | 24 +-----------------------\n 1 file changed, 1 insertion(+), 23 deletions(-)\n\n--- a/drivers/thermal/qcom/tsens-8960.c\n+++ b/drivers/thermal/qcom/tsens-8960.c\n@@ -10,8 +10,6 @@\n #include <linux/thermal.h>\n #include \"tsens.h\"\n \n-#define CAL_MDEGC\t\t30000\n-\n #define CONFIG_ADDR\t\t0x3640\n #define CONFIG_ADDR_8660\t0x3620\n /* CONFIG_ADDR bitmasks */\n@@ -21,39 +19,19 @@\n #define CONFIG_SHIFT_8660\t28\n #define CONFIG_MASK_8660\t(3 << CONFIG_SHIFT_8660)\n \n-#define STATUS_CNTL_ADDR_8064\t0x3660\n #define CNTL_ADDR\t\t0x3620\n /* CNTL_ADDR bitmasks */\n #define EN\t\t\tBIT(0)\n #define SW_RST\t\t\tBIT(1)\n-#define SENSOR0_EN\t\tBIT(3)\n+\n #define MEASURE_PERIOD\t\tBIT(18)\n #define SLP_CLK_ENA\t\tBIT(26)\n #define SLP_CLK_ENA_8660\tBIT(24)\n #define SENSOR0_SHIFT\t\t3\n \n-/* INT_STATUS_ADDR bitmasks */\n-#define MIN_STATUS_MASK\t\tBIT(0)\n-#define LOWER_STATUS_CLR\tBIT(1)\n-#define UPPER_STATUS_CLR\tBIT(2)\n-#define MAX_STATUS_MASK\t\tBIT(3)\n-\n #define THRESHOLD_ADDR\t\t0x3624\n-/* THRESHOLD_ADDR bitmasks */\n-#define THRESHOLD_MAX_LIMIT_SHIFT\t24\n-#define THRESHOLD_MIN_LIMIT_SHIFT\t16\n-#define THRESHOLD_UPPER_LIMIT_SHIFT\t8\n-#define THRESHOLD_LOWER_LIMIT_SHIFT\t0\n-\n-/* Initial temperature threshold values */\n-#define LOWER_LIMIT_TH\t\t0x50\n-#define UPPER_LIMIT_TH\t\t0xdf\n-#define MIN_LIMIT_TH\t\t0x0\n-#define MAX_LIMIT_TH\t\t0xff\n \n #define INT_STATUS_ADDR\t\t0x363c\n-#define TRDY_MASK\t\tBIT(7)\n-#define TIMEOUT_US\t\t100\n \n #define S0_STATUS_OFF\t\t0x3628\n #define S1_STATUS_OFF\t\t0x362c\n"
  },
  {
    "path": "target/linux/ipq806x/patches-5.10/104-8-drivers-thermal-tsens-Add-support-for-ipq8064-tsens.patch",
    "content": "From 0d0c22a59bf2672b57e23da9a9ea743e91b71f54 Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Sat, 25 Jul 2020 19:55:57 +0200\nSubject: [PATCH 08/10] drivers: thermal: tsens: Add support for ipq8064-tsens\n\nAdd support for tsens present in ipq806x SoCs based on generic msm8960\ntsens driver.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nReviewed-by: Thara Gopinath <thara.gopinath@linaro.org>\n---\n drivers/thermal/qcom/tsens.c | 3 +++\n 1 file changed, 3 insertions(+)\n\n--- a/drivers/thermal/qcom/tsens.c\n+++ b/drivers/thermal/qcom/tsens.c\n@@ -968,6 +968,9 @@ static SIMPLE_DEV_PM_OPS(tsens_pm_ops, t\n \n static const struct of_device_id tsens_table[] = {\n \t{\n+\t\t.compatible = \"qcom,ipq8064-tsens\",\n+\t\t.data = &data_8960,\n+\t}, {\n \t\t.compatible = \"qcom,msm8916-tsens\",\n \t\t.data = &data_8916,\n \t}, {\n"
  },
  {
    "path": "target/linux/ipq806x/patches-5.10/104-9-dt-bindings-thermal-tsens-Document-ipq8064-bindings.patch",
    "content": "From ac369071920d427dd484cf74cddba2774bba45f5 Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Thu, 9 Jul 2020 22:35:54 +0200\nSubject: [PATCH 09/10] dt-bindings: thermal: tsens: Document ipq8064 bindings\n\nDocument the use of bindings used for msm8960 tsens based devices.\nmsm8960 use the same gcc regs and is set as a child of the qcom gcc.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nReviewed-by: Rob Herring <robh@kernel.org>\n---\n .../bindings/thermal/qcom-tsens.yaml          | 56 ++++++++++++++++---\n 1 file changed, 48 insertions(+), 8 deletions(-)\n\n--- a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml\n+++ b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml\n@@ -19,6 +19,11 @@ description: |\n properties:\n   compatible:\n     oneOf:\n+      - description: msm9860 TSENS based\n+        items:\n+          - enum:\n+              - qcom,ipq8064-tsens\n+\n       - description: v0.1 of TSENS\n         items:\n           - enum:\n@@ -73,7 +78,9 @@ properties:\n     maxItems: 2\n     items:\n       - const: calib\n-      - const: calib_sel\n+      - enum:\n+          - calib_backup\n+          - calib_sel\n \n   \"#qcom,sensors\":\n     description:\n@@ -88,12 +95,20 @@ properties:\n       Number of cells required to uniquely identify the thermal sensors. Since\n       we have multiple sensors this is set to 1\n \n+required:\n+  - compatible\n+  - interrupts\n+  - interrupt-names\n+  - \"#thermal-sensor-cells\"\n+  - \"#qcom,sensors\"\n+\n allOf:\n   - if:\n       properties:\n         compatible:\n           contains:\n             enum:\n+              - qcom,ipq8064-tsens\n               - qcom,msm8916-tsens\n               - qcom,msm8974-tsens\n               - qcom,msm8976-tsens\n@@ -114,19 +129,44 @@ allOf:\n         interrupt-names:\n           minItems: 2\n \n-required:\n-  - compatible\n-  - reg\n-  - \"#qcom,sensors\"\n-  - interrupts\n-  - interrupt-names\n-  - \"#thermal-sensor-cells\"\n+  - if:\n+      properties:\n+        compatible:\n+          contains:\n+            enum:\n+              - qcom,tsens-v0_1\n+              - qcom,tsens-v1\n+              - qcom,tsens-v2\n+\n+    then:\n+      required:\n+        - reg\n \n additionalProperties: false\n \n examples:\n   - |\n     #include <dt-bindings/interrupt-controller/arm-gic.h>\n+    // Example msm9860 based SoC (ipq8064):\n+    gcc: clock-controller {\n+\n+           /* ... */\n+\n+           tsens: thermal-sensor {\n+                compatible = \"qcom,ipq8064-tsens\";\n+\n+                 nvmem-cells = <&tsens_calib>, <&tsens_calib_backup>;\n+                 nvmem-cell-names = \"calib\", \"calib_backup\";\n+                 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;\n+                 interrupt-names = \"uplow\";\n+\n+                 #qcom,sensors = <11>;\n+                 #thermal-sensor-cells = <1>;\n+          };\n+    };\n+\n+  - |\n+    #include <dt-bindings/interrupt-controller/arm-gic.h>\n     // Example 1 (legacy: for pre v1 IP):\n     tsens1: thermal-sensor@900000 {\n            compatible = \"qcom,msm8916-tsens\", \"qcom,tsens-v0_1\";\n"
  },
  {
    "path": "target/linux/ipq806x/patches-5.10/105-10-drivers-thermal-tsens-Fix-wrong-slope-on-msm-8960.patch",
    "content": "From 68e720ed73c8f038c8c500e4c49c1e65a993a448 Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Tue, 6 Apr 2021 04:45:31 +0200\nSubject: [PATCH 10/10] drivers: thermal: tsens: Fix wrong slope on msm-8960\n\nSome user using some stats with the old legacy implementation and the\nnew implementation using the compute_intercept_slope reported an offset\nof 3C. Fix the slope table to reflect the original temp.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\n---\n drivers/thermal/qcom/tsens-8960.c | 8 ++++----\n 1 file changed, 4 insertions(+), 4 deletions(-)\n\n--- a/drivers/thermal/qcom/tsens-8960.c\n+++ b/drivers/thermal/qcom/tsens-8960.c\n@@ -45,11 +45,11 @@\n #define S9_STATUS_OFF\t\t0x3674\n #define S10_STATUS_OFF\t\t0x3678\n \n-/* Original slope - 200 to compensate mC to C inaccuracy */\n+/* Original slope - 350 to compensate mC to C inaccuracy */\n static u32 tsens_msm8960_slope[] = {\n-\t\t\t976, 976, 954, 976,\n-\t\t\t911, 932, 932, 999,\n-\t\t\t932, 999, 932\n+\t\t\t826, 826, 804, 826,\n+\t\t\t761, 782, 782, 849,\n+\t\t\t782, 849, 782\n \t\t\t};\n \n static int suspend_8960(struct tsens_priv *priv)\n"
  },
  {
    "path": "target/linux/ipq806x/patches-5.10/107-1-thermal-qcom-tsens-init-debugfs-only-with-successful.patch",
    "content": "From 8f32d48a309246a80bdca505968085a484d54408 Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Mon, 19 Apr 2021 03:01:53 +0200\nSubject: [thermal-next PATCH v2 1/2] thermal: qcom: tsens: init debugfs only with\n successful probe\n\ncalibrate and tsens_register can fail or PROBE_DEFER. This will cause a\ndouble or a wrong init of the debugfs information. Init debugfs only\nwith successful probe fixing warning about directory already present.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nAcked-by: Thara Gopinath <thara.gopinath@linaro.org>\n---\n drivers/thermal/qcom/tsens.c | 9 ++++++---\n 1 file changed, 6 insertions(+), 3 deletions(-)\n\n--- a/drivers/thermal/qcom/tsens.c\n+++ b/drivers/thermal/qcom/tsens.c\n@@ -918,8 +918,6 @@ int __init init_common(struct tsens_priv\n \tif (tsens_version(priv) >= VER_0_1)\n \t\ttsens_enable_irq(priv);\n \n-\ttsens_debug_init(op);\n-\n err_put_device:\n \tput_device(&op->dev);\n \treturn ret;\n@@ -1155,7 +1153,12 @@ static int tsens_probe(struct platform_d\n \t\t}\n \t}\n \n-\treturn tsens_register(priv);\n+\tret = tsens_register(priv);\n+\n+\tif (!ret)\n+\t\ttsens_debug_init(pdev);\n+\n+\treturn ret;\n }\n \n static int tsens_remove(struct platform_device *pdev)\n"
  },
  {
    "path": "target/linux/ipq806x/patches-5.10/107-2-thermal-qcom-tsens-simplify-debugfs-init-function.patch",
    "content": "From 4204f22060f7a5d42c6ccb4d4c25a6a875571099 Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Mon, 19 Apr 2021 03:08:37 +0200\nSubject: [thermal-next PATCH v2 2/2] thermal: qcom: tsens: simplify debugfs init\n function\n\nSimplify debugfs init function.\n- Add check for existing dev directory.\n- Fix wrong version in dbg_version_show (with version 0.0.0, 0.1.0 was\n  incorrectly reported)\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nReviewed-by: Thara Gopinath <thara.gopinath@linaro.org>\n---\n drivers/thermal/qcom/tsens.c | 16 +++++++---------\n 1 file changed, 7 insertions(+), 9 deletions(-)\n\n--- a/drivers/thermal/qcom/tsens.c\n+++ b/drivers/thermal/qcom/tsens.c\n@@ -692,7 +692,7 @@ static int dbg_version_show(struct seq_f\n \t\t\treturn ret;\n \t\tseq_printf(s, \"%d.%d.%d\\n\", maj_ver, min_ver, step_ver);\n \t} else {\n-\t\tseq_puts(s, \"0.1.0\\n\");\n+\t\tseq_printf(s, \"0.%d.0\\n\", priv->feat->ver_major);\n \t}\n \n \treturn 0;\n@@ -704,21 +704,17 @@ DEFINE_SHOW_ATTRIBUTE(dbg_sensors);\n static void tsens_debug_init(struct platform_device *pdev)\n {\n \tstruct tsens_priv *priv = platform_get_drvdata(pdev);\n-\tstruct dentry *root, *file;\n \n-\troot = debugfs_lookup(\"tsens\", NULL);\n-\tif (!root)\n+\tpriv->debug_root = debugfs_lookup(\"tsens\", NULL);\n+\tif (!priv->debug_root)\n \t\tpriv->debug_root = debugfs_create_dir(\"tsens\", NULL);\n-\telse\n-\t\tpriv->debug_root = root;\n \n-\tfile = debugfs_lookup(\"version\", priv->debug_root);\n-\tif (!file)\n+\tif (!debugfs_lookup(\"version\", priv->debug_root))\n \t\tdebugfs_create_file(\"version\", 0444, priv->debug_root,\n \t\t\t\t    pdev, &dbg_version_fops);\n \n \t/* A directory for each instance of the TSENS IP */\n-\tpriv->debug = debugfs_create_dir(dev_name(&pdev->dev), priv->debug_root);\n+\tpriv->debug = debugfs_lookup(dev_name(&pdev->dev), priv->debug_root);\n \tdebugfs_create_file(\"sensors\", 0444, priv->debug, pdev, &dbg_sensors_fops);\n }\n #else\n"
  },
  {
    "path": "target/linux/ipq806x/patches-5.10/108-v5.14-net-stmmac-explicitly-deassert-gmac-ahb-reset.patch",
    "content": "From e67f325e9cd67562b761e884680c0fec03a6f404 Mon Sep 17 00:00:00 2001\nFrom: Matthew Hagan <mnhagan88@gmail.com>\nDate: Tue, 8 Jun 2021 19:59:06 +0100\nSubject: net: stmmac: explicitly deassert GMAC_AHB_RESET\n\nWe are currently assuming that GMAC_AHB_RESET will already be deasserted\nby the bootloader. However if this has not been done, probing of the GMAC\nwill fail. To remedy this we must ensure GMAC_AHB_RESET has been deasserted\nprior to probing.\n\nv2 changes:\n - remove NULL condition check for stmmac_ahb_rst in stmmac_main.c\n - unwrap dev_err() message in stmmac_main.c\n - add PTR_ERR() around plat->stmmac_ahb_rst in stmmac_platform.c\n\nv3 changes:\n - add error pointer to dev_err() output\n - add reset_control_assert(stmmac_ahb_rst) in stmmac_dvr_remove\n - revert PTR_ERR() around plat->stmmac_ahb_rst since this is performed\n   on the returned value of ret by the calling function\n\nSigned-off-by: Matthew Hagan <mnhagan88@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/ethernet/stmicro/stmmac/stmmac_main.c     | 5 +++++\n drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c | 6 ++++++\n include/linux/stmmac.h                                | 1 +\n 3 files changed, 12 insertions(+)\n\n--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c\n+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c\n@@ -5021,6 +5021,10 @@ int stmmac_dvr_probe(struct device *devi\n \t\t\treset_control_reset(priv->plat->stmmac_rst);\n \t}\n \n+\tret = reset_control_deassert(priv->plat->stmmac_ahb_rst);\n+\tif (ret == -ENOTSUPP)\n+\t\tdev_err(priv->device, \"unable to bring out of ahb reset\\n\");\n+\n \t/* Init MAC and get the capabilities */\n \tret = stmmac_hw_init(priv);\n \tif (ret)\n@@ -5245,6 +5249,7 @@ int stmmac_dvr_remove(struct device *dev\n \tphylink_destroy(priv->phylink);\n \tif (priv->plat->stmmac_rst)\n \t\treset_control_assert(priv->plat->stmmac_rst);\n+\treset_control_assert(priv->plat->stmmac_ahb_rst);\n \tpm_runtime_put(dev);\n \tpm_runtime_disable(dev);\n \tif (priv->hw->pcs != STMMAC_PCS_TBI &&\n--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c\n+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c\n@@ -616,6 +616,12 @@ stmmac_probe_config_dt(struct platform_d\n \t\tplat->stmmac_rst = NULL;\n \t}\n \n+\tplat->stmmac_ahb_rst = devm_reset_control_get_optional_shared(\n+\t\t\t\t\t\t\t&pdev->dev, \"ahb\");\n+\tif (IS_ERR(plat->stmmac_ahb_rst))\n+\t\tif (PTR_ERR(plat->stmmac_ahb_rst) == -EPROBE_DEFER)\n+\t\t\tgoto error_hw_init;\n+\n \treturn plat;\n \n error_hw_init:\n--- a/include/linux/stmmac.h\n+++ b/include/linux/stmmac.h\n@@ -192,6 +192,7 @@ struct plat_stmmacenet_data {\n \tunsigned int clk_ref_rate;\n \ts32 ptp_max_adj;\n \tstruct reset_control *stmmac_rst;\n+\tstruct reset_control *stmmac_ahb_rst;\n \tstruct stmmac_axi *axi;\n \tint has_gmac4;\n \tbool has_sun8i;\n"
  },
  {
    "path": "target/linux/ipq806x/patches-5.10/109-v5.15-arm-dts-qcom-add-ahb-reset-to-ipq806x-gmac.patch",
    "content": "From f95c4c56d65225a537a2d88735fde7ec4d37641d Mon Sep 17 00:00:00 2001\nFrom: Matthew Hagan <mnhagan88@gmail.com>\nDate: Sat, 5 Jun 2021 18:35:38 +0100\nSubject: ARM: dts: qcom: add ahb reset to ipq806x-gmac\n\nAdd GMAC_AHB_RESET to the resets property of each gmac node.\n\nSigned-off-by: Matthew Hagan <mnhagan88@gmail.com>\nLink: https://lore.kernel.org/r/20210605173546.4102455-2-mnhagan88@gmail.com\nSigned-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>\n---\n arch/arm/boot/dts/qcom-ipq8064.dtsi | 20 ++++++++++++--------\n 1 file changed, 12 insertions(+), 8 deletions(-)\n\n--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi\n+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi\n@@ -1335,8 +1335,9 @@\n \t\t\tclocks = <&gcc GMAC_CORE1_CLK>;\n \t\t\tclock-names = \"stmmaceth\";\n \n-\t\t\tresets = <&gcc GMAC_CORE1_RESET>;\n-\t\t\treset-names = \"stmmaceth\";\n+\t\t\tresets = <&gcc GMAC_CORE1_RESET>,\n+\t\t\t\t <&gcc GMAC_AHB_RESET>;\n+\t\t\treset-names = \"stmmaceth\", \"ahb\";\n \n \t\t\tstatus = \"disabled\";\n \t\t};\n@@ -1358,8 +1359,9 @@\n \t\t\tclocks = <&gcc GMAC_CORE2_CLK>;\n \t\t\tclock-names = \"stmmaceth\";\n \n-\t\t\tresets = <&gcc GMAC_CORE2_RESET>;\n-\t\t\treset-names = \"stmmaceth\";\n+\t\t\tresets = <&gcc GMAC_CORE2_RESET>,\n+\t\t\t\t <&gcc GMAC_AHB_RESET>;\n+\t\t\treset-names = \"stmmaceth\", \"ahb\";\n \n \t\t\tstatus = \"disabled\";\n \t\t};\n@@ -1381,8 +1383,9 @@\n \t\t\tclocks = <&gcc GMAC_CORE3_CLK>;\n \t\t\tclock-names = \"stmmaceth\";\n \n-\t\t\tresets = <&gcc GMAC_CORE3_RESET>;\n-\t\t\treset-names = \"stmmaceth\";\n+\t\t\tresets = <&gcc GMAC_CORE3_RESET>,\n+\t\t\t\t <&gcc GMAC_AHB_RESET>;\n+\t\t\treset-names = \"stmmaceth\", \"ahb\";\n \n \t\t\tstatus = \"disabled\";\n \t\t};\n@@ -1404,8 +1407,9 @@\n \t\t\tclocks = <&gcc GMAC_CORE4_CLK>;\n \t\t\tclock-names = \"stmmaceth\";\n \n-\t\t\tresets = <&gcc GMAC_CORE4_RESET>;\n-\t\t\treset-names = \"stmmaceth\";\n+\t\t\tresets = <&gcc GMAC_CORE4_RESET>,\n+\t\t\t\t <&gcc GMAC_AHB_RESET>;\n+\t\t\treset-names = \"stmmaceth\", \"ahb\";\n \n \t\t\tstatus = \"disabled\";\n \t\t};\n"
  },
  {
    "path": "target/linux/ipq806x/patches-5.10/850-soc-add-qualcomm-syscon.patch",
    "content": "From: Christian Lamparter <chunkeey@googlemail.com>\nSubject: SoC: add qualcomm syscon\n--- a/drivers/soc/qcom/Makefile\n+++ b/drivers/soc/qcom/Makefile\n@@ -21,6 +21,7 @@ obj-$(CONFIG_QCOM_SMP2P)\t+= smp2p.o\n obj-$(CONFIG_QCOM_SMSM)\t+= smsm.o\n obj-$(CONFIG_QCOM_SOCINFO)\t+= socinfo.o\n obj-$(CONFIG_QCOM_WCNSS_CTRL) += wcnss_ctrl.o\n+obj-$(CONFIG_QCOM_TCSR)\t += qcom_tcsr.o\n obj-$(CONFIG_QCOM_APR) += apr.o\n obj-$(CONFIG_QCOM_LLCC) += llcc-qcom.o\n obj-$(CONFIG_QCOM_RPMHPD) += rpmhpd.o\n--- a/drivers/soc/qcom/Kconfig\n+++ b/drivers/soc/qcom/Kconfig\n@@ -189,6 +189,13 @@ config QCOM_SOCINFO\n \t Say yes here to support the Qualcomm socinfo driver, providing\n \t information about the SoC to user space.\n \n+config QCOM_TCSR\n+\ttristate \"QCOM Top Control and Status Registers\"\n+\tdepends on ARCH_QCOM\n+\thelp\n+\t  Say y here to enable TCSR support.  The TCSR provides control\n+\t  functions for various peripherals.\n+\n config QCOM_WCNSS_CTRL\n \ttristate \"Qualcomm WCNSS control driver\"\n \tdepends on ARCH_QCOM || COMPILE_TEST\n--- /dev/null\n+++ b/drivers/soc/qcom/qcom_tcsr.c\n@@ -0,0 +1,64 @@\n+/*\n+ * Copyright (c) 2014, The Linux foundation. All rights reserved.\n+ *\n+ * This program is free software; you can redistribute it and/or modify\n+ * it under the terms of the GNU General Public License rev 2 and\n+ * only rev 2 as published by the free Software foundation.\n+ *\n+ * This program is distributed in the hope that it will be useful,\n+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\n+ * MERCHANTABILITY or fITNESS fOR A PARTICULAR PURPOSE.  See the\n+ * GNU General Public License for more details.\n+ */\n+\n+#include <linux/clk.h>\n+#include <linux/err.h>\n+#include <linux/io.h>\n+#include <linux/module.h>\n+#include <linux/of.h>\n+#include <linux/of_platform.h>\n+#include <linux/platform_device.h>\n+\n+#define TCSR_USB_PORT_SEL\t0xb0\n+\n+static int tcsr_probe(struct platform_device *pdev)\n+{\n+\tstruct resource *res;\n+\tconst struct device_node *node = pdev->dev.of_node;\n+\tvoid __iomem *base;\n+\tu32 val;\n+\n+\tres = platform_get_resource(pdev, IORESOURCE_MEM, 0);\n+\tbase = devm_ioremap_resource(&pdev->dev, res);\n+\tif (IS_ERR(base))\n+\t\treturn PTR_ERR(base);\n+\n+\tif (!of_property_read_u32(node, \"qcom,usb-ctrl-select\", &val)) {\n+\t\tdev_err(&pdev->dev, \"setting usb port select = %d\\n\", val);\n+\t\twritel(val, base + TCSR_USB_PORT_SEL);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static const struct of_device_id tcsr_dt_match[] = {\n+\t{ .compatible = \"qcom,tcsr\", },\n+\t{ },\n+};\n+\n+MODULE_DEVICE_TABLE(of, tcsr_dt_match);\n+\n+static struct platform_driver tcsr_driver = {\n+\t.driver = {\n+\t\t.name\t\t= \"tcsr\",\n+\t\t.owner\t\t= THIS_MODULE,\n+\t\t.of_match_table\t= tcsr_dt_match,\n+\t},\n+\t.probe = tcsr_probe,\n+};\n+\n+module_platform_driver(tcsr_driver);\n+\n+MODULE_AUTHOR(\"Andy Gross <agross@codeaurora.org>\");\n+MODULE_DESCRIPTION(\"QCOM TCSR driver\");\n+MODULE_LICENSE(\"GPL v2\");\n--- /dev/null\n+++ b/include/dt-bindings/soc/qcom,tcsr.h\n@@ -0,0 +1,23 @@\n+/* Copyright (c) 2014, The Linux Foundation. All rights reserved.\n+ *\n+ * This program is free software; you can redistribute it and/or modify\n+ * it under the terms of the GNU General Public License version 2 and\n+ * only version 2 as published by the Free Software Foundation.\n+ *\n+ * This program is distributed in the hope that it will be useful,\n+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\n+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n+ * GNU General Public License for more details.\n+ */\n+#ifndef __DT_BINDINGS_QCOM_TCSR_H\n+#define __DT_BINDINGS_QCOM_TCSR_H\n+\n+#define TCSR_USB_SELECT_USB3_P0\t\t0x1\n+#define TCSR_USB_SELECT_USB3_P1\t\t0x2\n+#define TCSR_USB_SELECT_USB3_DUAL\t0x3\n+\n+/* TCSR A/B REG */\n+#define IPQ806X_TCSR_REG_A_ADM_CRCI_MUX_SEL     0\n+#define IPQ806X_TCSR_REG_B_ADM_CRCI_MUX_SEL     1\n+\n+#endif\n"
  },
  {
    "path": "target/linux/ipq806x/patches-5.10/900-arm-add-cmdline-override.patch",
    "content": "--- a/arch/arm/Kconfig\n+++ b/arch/arm/Kconfig\n@@ -1794,6 +1794,14 @@ config ARM_ATAG_DTB_COMPAT_CMDLINE_MANGL\n \n endchoice\n \n+config CMDLINE_OVERRIDE\n+\tbool \"Use alternative cmdline from device tree\"\n+\thelp\n+\t  Some bootloaders may have uneditable bootargs. While CMDLINE_FORCE can\n+\t  be used, this is not a good option for kernels that are shared across\n+\t  devices. This setting enables using \"chosen/cmdline-override\" as the\n+\t  cmdline if it exists in the device tree.\n+\n config CMDLINE\n \tstring \"Default kernel command string\"\n \tdefault \"\"\n--- a/drivers/of/fdt.c\n+++ b/drivers/of/fdt.c\n@@ -1059,6 +1059,17 @@ int __init early_init_dt_scan_chosen(uns\n \tif (p != NULL && l > 0)\n \t\tstrlcat(data, p, min_t(int, strlen(data) + (int)l, COMMAND_LINE_SIZE));\n \n+    /* CONFIG_CMDLINE_OVERRIDE is used to fallback to a different\n+     * device tree option of chosen/bootargs-override. This is\n+     * helpful on boards where u-boot sets bootargs, and is unable\n+     * to be modified.\n+     */\n+#ifdef CONFIG_CMDLINE_OVERRIDE\n+\tp = of_get_flat_dt_prop(node, \"bootargs-override\", &l);\n+\tif (p != NULL && l > 0)\n+\t\tstrlcpy(data, p, min((int)l, COMMAND_LINE_SIZE));\n+#endif\n+\n \t/*\n \t * CONFIG_CMDLINE is meant to be a default in case nothing else\n \t * managed to set the command line, unless CONFIG_CMDLINE_FORCE\n"
  },
  {
    "path": "target/linux/ipq806x/patches-5.15/0001-dtbindings-qcom_adm-Fix-channel-specifiers.patch",
    "content": "From 28d0ed88f536dd639adf1b0c7c08e04be3c8f294 Mon Sep 17 00:00:00 2001\nFrom: Thomas Pedersen <twp@codeaurora.org>\nDate: Mon, 16 May 2016 17:58:50 -0700\nSubject: [PATCH 01/69] dtbindings: qcom_adm: Fix channel specifiers\n\nOriginal patch from Andy Gross.\n\nThis patch removes the crci information from the dma\nchannel property.  At least one client device requires\nusing more than one CRCI value for a channel.  This does\nnot match the current binding and the crci information\nneeds to be removed.\n\nInstead, the client device will provide this information\nvia other means.\n\nSigned-off-by: Andy Gross <agross@codeaurora.org>\nSigned-off-by: Thomas Pedersen <twp@codeaurora.org>\n---\n Documentation/devicetree/bindings/dma/qcom_adm.txt | 16 ++++++----------\n 1 file changed, 6 insertions(+), 10 deletions(-)\n\n--- a/Documentation/devicetree/bindings/dma/qcom_adm.txt\n+++ b/Documentation/devicetree/bindings/dma/qcom_adm.txt\n@@ -4,8 +4,7 @@ Required properties:\n - compatible: must contain \"qcom,adm\" for IPQ/APQ8064 and MSM8960\n - reg: Address range for DMA registers\n - interrupts: Should contain one interrupt shared by all channels\n-- #dma-cells: must be <2>.  First cell denotes the channel number.  Second cell\n-  denotes CRCI (client rate control interface) flow control assignment.\n+- #dma-cells: must be <1>.  First cell denotes the channel number.\n - clocks: Should contain the core clock and interface clock.\n - clock-names: Must contain \"core\" for the core clock and \"iface\" for the\n   interface clock.\n@@ -22,7 +21,7 @@ Example:\n \t\t\tcompatible = \"qcom,adm\";\n \t\t\treg = <0x18300000 0x100000>;\n \t\t\tinterrupts = <0 170 0>;\n-\t\t\t#dma-cells = <2>;\n+\t\t\t#dma-cells = <1>;\n \n \t\t\tclocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>;\n \t\t\tclock-names = \"core\", \"iface\";\n@@ -35,15 +34,12 @@ Example:\n \t\t\tqcom,ee = <0>;\n \t\t};\n \n-DMA clients must use the format descripted in the dma.txt file, using a three\n+DMA clients must use the format descripted in the dma.txt file, using a two\n cell specifier for each channel.\n \n-Each dmas request consists of 3 cells:\n+Each dmas request consists of two cells:\n  1. phandle pointing to the DMA controller\n  2. channel number\n- 3. CRCI assignment, if applicable.  If no CRCI flow control is required, use 0.\n-    The CRCI is used for flow control.  It identifies the peripheral device that\n-    is the source/destination for the transferred data.\n \n Example:\n \n@@ -55,7 +51,7 @@ Example:\n \n \t\tcs-gpios = <&qcom_pinmux 20 0>;\n \n-\t\tdmas = <&adm_dma 6 9>,\n-\t\t\t<&adm_dma 5 10>;\n+\t\tdmas = <&adm_dma 6>,\n+\t\t\t<&adm_dma 5>;\n \t\tdma-names = \"rx\", \"tx\";\n \t};\n"
  },
  {
    "path": "target/linux/ipq806x/patches-5.15/0033-ARM-qcom-automatically-select-PCI_DOMAINS-if-PCI-is-.patch",
    "content": "From 48051ece78136e4235a2415a52797db56f8a4478 Mon Sep 17 00:00:00 2001\nFrom: Mathieu Olivari <mathieu@codeaurora.org>\nDate: Tue, 21 Apr 2015 19:09:07 -0700\nSubject: [PATCH 33/69] ARM: qcom: automatically select PCI_DOMAINS if PCI is\n enabled\n\nIf multiple PCIe devices are present in the system, the kernel will\npanic at boot time when trying to scan the PCI buses. This happens on\nIPQ806x based platforms, which has 3 PCIe ports.\n\nEnabling this option allows the kernel to assign the pci-domains\naccording to the device-tree content. This allows multiple PCIe\ncontrollers to coexist in the system.\n\nSigned-off-by: Mathieu Olivari <mathieu@codeaurora.org>\n---\n arch/arm/mach-qcom/Kconfig | 1 +\n 1 file changed, 1 insertion(+)\n\n--- a/arch/arm/mach-qcom/Kconfig\n+++ b/arch/arm/mach-qcom/Kconfig\n@@ -7,6 +7,7 @@ menuconfig ARCH_QCOM\n \tselect ARM_AMBA\n \tselect PINCTRL\n \tselect QCOM_SCM if SMP\n+\tselect PCI_DOMAINS if PCI\n \thelp\n \t  Support for Qualcomm's devicetree based systems.\n \n"
  },
  {
    "path": "target/linux/ipq806x/patches-5.15/0060-HACK-arch-arm-force-ZRELADDR-on-arch-qcom.patch",
    "content": "From fa71139b55e114aa8c3c4823ff8ee7d49ee810d4 Mon Sep 17 00:00:00 2001\nFrom: Mathieu Olivari <mathieu@codeaurora.org>\nDate: Wed, 29 Apr 2015 15:21:46 -0700\nSubject: [PATCH 60/69] HACK: arch: arm: force ZRELADDR on arch-qcom\n\nARCH_QCOM is using the ARCH_MULTIPLATFORM option, as now recommended\non most ARM architectures. This automatically calculate ZRELADDR by\nmasking PHYS_OFFSET with 0xf8000000.\n\nHowever, on IPQ806x, the first ~20MB of RAM is reserved for the hardware\nnetwork accelerators, and the bootloader removes this section from the\nlayout passed from the ATAGS (when used).\n\nFor newer bootloader, when DT is used, this is not a problem, we just\nreserve this memory in the device tree. But if the bootloader doesn't\nhave DT support, then ATAGS have to be used. In this case, the ARM\ndecompressor will position the kernel in this low mem, which will not be\nin the RAM section mapped by the bootloader, which means the kernel will\nfreeze in the middle of the boot process trying to map the memory.\n\nAs a work around, this patch allows disabling AUTO_ZRELADDR when\nARCH_QCOM is selected. It makes the zImage usage possible on bootloaders\nwhich don't support device-tree, which is the case on certain early\nIPQ806x based designs.\n\nSigned-off-by: Mathieu Olivari <mathieu@codeaurora.org>\n---\n arch/arm/Kconfig                 | 2 +-\n arch/arm/Makefile                | 2 ++\n arch/arm/mach-qcom/Makefile.boot | 1 +\n 3 files changed, 4 insertions(+), 1 deletion(-)\n create mode 100644 arch/arm/mach-qcom/Makefile.boot\n\n--- a/arch/arm/Kconfig\n+++ b/arch/arm/Kconfig\n@@ -317,7 +317,7 @@ config ARCH_MULTIPLATFORM\n \tselect ARCH_SELECT_MEMORY_MODEL\n \tselect ARM_HAS_SG_CHAIN\n \tselect ARM_PATCH_PHYS_VIRT\n-\tselect AUTO_ZRELADDR\n+\tselect AUTO_ZRELADDR if !ARCH_QCOM\n \tselect TIMER_OF\n \tselect COMMON_CLK\n \tselect GENERIC_IRQ_MULTI_HANDLER\n--- a/arch/arm/Makefile\n+++ b/arch/arm/Makefile\n@@ -237,9 +237,11 @@ MACHINE  := arch/arm/mach-$(word 1,$(mac\n else\n MACHINE  :=\n endif\n+ifeq ($(CONFIG_ARCH_QCOM),)\n ifeq ($(CONFIG_ARCH_MULTIPLATFORM),y)\n MACHINE  :=\n endif\n+endif\n \n machdirs := $(patsubst %,arch/arm/mach-%/,$(machine-y))\n platdirs := $(patsubst %,arch/arm/plat-%/,$(sort $(plat-y)))\n--- /dev/null\n+++ b/arch/arm/mach-qcom/Makefile.boot\n@@ -0,0 +1 @@\n+zreladdr-y+= 0x42208000\n"
  },
  {
    "path": "target/linux/ipq806x/patches-5.15/0065-arm-override-compiler-flags.patch",
    "content": "From 4d8e29642661397a339ac3485f212c6360445421 Mon Sep 17 00:00:00 2001\nFrom: John Crispin <john@phrozen.org>\nDate: Thu, 9 Mar 2017 09:33:32 +0100\nSubject: [PATCH 65/69] arm: override compiler flags\n\nSigned-off-by: John Crispin <john@phrozen.org>\n---\n arch/arm/Makefile | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/arch/arm/Makefile\n+++ b/arch/arm/Makefile\n@@ -61,7 +61,7 @@ KBUILD_CFLAGS\t+= $(call cc-option,-fno-i\n # macro, but instead defines a whole series of macros which makes\n # testing for a specific architecture or later rather impossible.\n arch-$(CONFIG_CPU_32v7M)\t=-D__LINUX_ARM_ARCH__=7 -march=armv7-m\n-arch-$(CONFIG_CPU_32v7)\t\t=-D__LINUX_ARM_ARCH__=7 -march=armv7-a\n+arch-$(CONFIG_CPU_32v7)\t\t=-D__LINUX_ARM_ARCH__=7 -mcpu=cortex-a15\n arch-$(CONFIG_CPU_32v6)\t\t=-D__LINUX_ARM_ARCH__=6 -march=armv6\n # Only override the compiler option if ARMv6. The ARMv6K extensions are\n # always available in ARMv7\n"
  },
  {
    "path": "target/linux/ipq806x/patches-5.15/0067-generic-Mangle-bootloader-s-kernel-arguments.patch",
    "content": "From 71270226b14733a4b1f2cde58ea9265caa50b38d Mon Sep 17 00:00:00 2001\nFrom: Adrian Panella <ianchi74@outlook.com>\nDate: Thu, 9 Mar 2017 09:37:17 +0100\nSubject: [PATCH 67/69] generic: Mangle bootloader's kernel arguments\n\nThe command-line arguments provided by the boot loader will be\nappended to a new device tree property: bootloader-args.\nIf there is a property \"append-rootblock\" in DT under /chosen\nand a root= option in bootloaders command line it will be parsed\nand added to DT bootargs with the form: <append-rootblock>XX.\nOnly command line ATAG will be processed, the rest of the ATAGs\nsent by bootloader will be ignored.\nThis is usefull in dual boot systems, to get the current root partition\nwithout afecting the rest of the system.\n\nSigned-off-by: Adrian Panella <ianchi74@outlook.com>\n---\n arch/arm/Kconfig                        | 11 +++++\n arch/arm/boot/compressed/atags_to_fdt.c | 72 ++++++++++++++++++++++++++++++++-\n init/main.c                             | 16 ++++++++\n 3 files changed, 98 insertions(+), 1 deletion(-)\n\n--- a/arch/arm/Kconfig\n+++ b/arch/arm/Kconfig\n@@ -1727,6 +1727,17 @@ config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEN\n \t  The command-line arguments provided by the boot loader will be\n \t  appended to the the device tree bootargs property.\n \n+config ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE\n+\tbool \"Append rootblock parsing bootloader's kernel arguments\"\n+\thelp\n+\t  The command-line arguments provided by the boot loader will be\n+\t  appended to a new device tree property: bootloader-args.\n+\t  If there is a property \"append-rootblock\" in DT under /chosen\n+\t  and a root= option in bootloaders command line it will be parsed\n+\t  and added to DT bootargs with the form: <append-rootblock>XX.\n+\t  Only command line ATAG will be processed, the rest of the ATAGs\n+\t  sent by bootloader will be ignored.\n+\n endchoice\n \n config CMDLINE\n--- a/arch/arm/boot/compressed/atags_to_fdt.c\n+++ b/arch/arm/boot/compressed/atags_to_fdt.c\n@@ -5,6 +5,8 @@\n \n #if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND)\n #define do_extend_cmdline 1\n+#elif defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)\n+#define do_extend_cmdline 1\n #else\n #define do_extend_cmdline 0\n #endif\n@@ -69,6 +71,80 @@ static uint32_t get_cell_size(const void\n \treturn cell_size;\n }\n \n+#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)\n+/**\n+ * taken from arch/x86/boot/string.c\n+ * local_strstr - Find the first substring in a %NUL terminated string\n+ * @s1: The string to be searched\n+ * @s2: The string to search for\n+ */\n+static char *local_strstr(const char *s1, const char *s2)\n+{\n+\tsize_t l1, l2;\n+\n+\tl2 = strlen(s2);\n+\tif (!l2)\n+\t\treturn (char *)s1;\n+\tl1 = strlen(s1);\n+\twhile (l1 >= l2) {\n+\t\tl1--;\n+\t\tif (!memcmp(s1, s2, l2))\n+\t\t\treturn (char *)s1;\n+\t\ts1++;\n+\t}\n+\treturn NULL;\n+}\n+\n+static char *append_rootblock(char *dest, const char *str, int len, void *fdt)\n+{\n+\tchar *ptr, *end, *tmp;\n+\tchar *root=\"root=\";\n+\tchar *find_rootblock;\n+\tint i, l;\n+\tconst char *rootblock;\n+\n+\tfind_rootblock = getprop(fdt, \"/chosen\", \"find-rootblock\", &l);\n+\tif(!find_rootblock)\n+\t\tfind_rootblock = root;\n+\n+\t//ARM doesn't have __HAVE_ARCH_STRSTR, so it was copied from x86\n+\tptr = local_strstr(str, find_rootblock);\n+\n+\tif(!ptr)\n+\t\treturn dest;\n+\n+\tend = strchr(ptr, ' ');\n+\tend = end ? (end - 1) : (strchr(ptr, 0) - 1);\n+\n+\t// Some boards ubi.mtd=XX,ZZZZ, so let's check for ',\" too.\n+\ttmp = strchr(ptr, ',');\n+\n+\tif(tmp)\n+\t\tend = end < tmp ? end : tmp - 1;\n+\n+\t//find partition number (assumes format root=/dev/mtdXX | /dev/mtdblockXX | yy:XX | ubi.mtd=XX,ZZZZ )\n+\tfor( i = 0; end >= ptr && *end >= '0' && *end <= '9'; end--, i++);\n+\tptr = end + 1;\n+\n+\t/* if append-rootblock property is set use it to append to command line */\n+\trootblock = getprop(fdt, \"/chosen\", \"append-rootblock\", &l);\n+\tif(rootblock != NULL) {\n+\t\tif(*dest != ' ') {\n+\t\t\t*dest = ' ';\n+\t\t\tdest++;\n+\t\t\tlen++;\n+\t\t}\n+\t\tif (len + l + i <= COMMAND_LINE_SIZE) {\n+\t\t\tmemcpy(dest, rootblock, l);\n+\t\t\tdest += l - 1;\n+\t\t\tmemcpy(dest, ptr, i);\n+\t\t\tdest += i;\n+\t\t}\n+\t}\n+\treturn dest;\n+}\n+#endif\n+\n static void merge_fdt_bootargs(void *fdt, const char *fdt_cmdline)\n {\n \tchar cmdline[COMMAND_LINE_SIZE];\n@@ -88,12 +164,21 @@ static void merge_fdt_bootargs(void *fdt\n \n \t/* and append the ATAG_CMDLINE */\n \tif (fdt_cmdline) {\n+\n+#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)\n+\t\t//save original bootloader args\n+\t\t//and append ubi.mtd with root partition number to current cmdline\n+\t\tsetprop_string(fdt, \"/chosen\", \"bootloader-args\", fdt_cmdline);\n+\t\tptr = append_rootblock(ptr, fdt_cmdline, len, fdt);\n+\n+#else\n \t\tlen = strlen(fdt_cmdline);\n \t\tif (ptr - cmdline + len + 2 < COMMAND_LINE_SIZE) {\n \t\t\t*ptr++ = ' ';\n \t\t\tmemcpy(ptr, fdt_cmdline, len);\n \t\t\tptr += len;\n \t\t}\n+#endif\n \t}\n \t*ptr = '\\0';\n \n@@ -168,7 +253,9 @@ int atags_to_fdt(void *atag_list, void *\n \t\t\telse\n \t\t\t\tsetprop_string(fdt, \"/chosen\", \"bootargs\",\n \t\t\t\t\t       atag->u.cmdline.cmdline);\n-\t\t} else if (atag->hdr.tag == ATAG_MEM) {\n+\t\t}\n+#ifndef CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE\n+\t\telse if (atag->hdr.tag == ATAG_MEM) {\n \t\t\tif (memcount >= sizeof(mem_reg_property)/4)\n \t\t\t\tcontinue;\n \t\t\tif (!atag->u.mem.size)\n@@ -212,6 +299,10 @@ int atags_to_fdt(void *atag_list, void *\n \t\tsetprop(fdt, \"/memory\", \"reg\", mem_reg_property,\n \t\t\t4 * memcount * memsize);\n \t}\n+#else\n+\n+\t}\n+#endif\n \n \treturn fdt_pack(fdt);\n }\n--- a/init/main.c\n+++ b/init/main.c\n@@ -113,6 +113,10 @@\n \n #include <kunit/test.h>\n \n+#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)\n+#include <linux/of.h>\n+#endif\n+\n static int kernel_init(void *);\n \n extern void init_IRQ(void);\n@@ -992,6 +996,18 @@ asmlinkage __visible void __init __no_sa\n \tpr_notice(\"Kernel command line: %s\\n\", saved_command_line);\n \t/* parameters may set static keys */\n \tjump_label_init();\n+\n+#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)\n+\t//Show bootloader's original command line for reference\n+\tif(of_chosen) {\n+\t\tconst char *prop = of_get_property(of_chosen, \"bootloader-args\", NULL);\n+\t\tif(prop)\n+\t\t\tpr_notice(\"Bootloader command line (ignored): %s\\n\", prop);\n+\t\telse\n+\t\t\tpr_notice(\"Bootloader command line not present\\n\");\n+\t}\n+#endif\n+\n \tparse_early_param();\n \tafter_dashes = parse_args(\"Booting kernel\",\n \t\t\t\t  static_command_line, __start___param,\n"
  },
  {
    "path": "target/linux/ipq806x/patches-5.15/0069-arm-boot-add-dts-files.patch",
    "content": "From 8f68331e14dff9a101f2d0e1d6bec84a031f27ee Mon Sep 17 00:00:00 2001\nFrom: John Crispin <john@phrozen.org>\nDate: Thu, 9 Mar 2017 11:03:18 +0100\nSubject: [PATCH 69/69] arm: boot: add dts files\n\nSigned-off-by: John Crispin <john@phrozen.org>\n---\n arch/arm/boot/dts/Makefile | 8 ++++++++\n 1 file changed, 8 insertions(+)\n\n--- a/arch/arm/boot/dts/Makefile\n+++ b/arch/arm/boot/dts/Makefile\n@@ -956,8 +956,30 @@ dtb-$(CONFIG_ARCH_QCOM) += \\\n \tqcom-ipq4019-ap.dk04.1-c3.dtb \\\n \tqcom-ipq4019-ap.dk07.1-c1.dtb \\\n \tqcom-ipq4019-ap.dk07.1-c2.dtb \\\n+\tqcom-ipq8062-wg2600hp3.dtb \\\n \tqcom-ipq8064-ap148.dtb \\\n \tqcom-ipq8064-rb3011.dtb \\\n+\tqcom-ipq8064-c2600.dtb \\\n+\tqcom-ipq8064-d7800.dtb \\\n+\tqcom-ipq8064-db149.dtb \\\n+\tqcom-ipq8064-ap161.dtb \\\n+\tqcom-ipq8064-ea7500-v1.dtb \\\n+\tqcom-ipq8064-ea8500.dtb \\\n+\tqcom-ipq8064-g10.dtb \\\n+\tqcom-ipq8064-r7500.dtb \\\n+\tqcom-ipq8064-r7500v2.dtb \\\n+\tqcom-ipq8064-unifi-ac-hd.dtb \\\n+\tqcom-ipq8064-wg2600hp.dtb \\\n+\tqcom-ipq8064-wpq864.dtb \\\n+\tqcom-ipq8064-wxr-2533dhp.dtb \\\n+\tqcom-ipq8065-nbg6817.dtb \\\n+\tqcom-ipq8065-r7800.dtb \\\n+\tqcom-ipq8065-rt4230w-rev6.dtb \\\n+\tqcom-ipq8065-tr4400-v2.dtb \\\n+\tqcom-ipq8065-xr500.dtb \\\n+\tqcom-ipq8068-ecw5410.dtb \\\n+\tqcom-ipq8068-mr42.dtb \\\n+\tqcom-ipq8068-mr52.dtb \\\n \tqcom-msm8226-samsung-s3ve3g.dtb \\\n \tqcom-msm8660-surf.dtb \\\n \tqcom-msm8960-cdp.dtb \\\n"
  },
  {
    "path": "target/linux/ipq806x/patches-5.15/0072-add-ipq806x-with-no-clocks.patch",
    "content": "--- a/drivers/firmware/qcom_scm.c\n+++ b/drivers/firmware/qcom_scm.c\n@@ -1333,6 +1333,7 @@ static const struct of_device_id qcom_sc\n \t\t\t\t\t\t\t     SCM_HAS_BUS_CLK)\n \t},\n \t{ .compatible = \"qcom,scm-ipq4019\" },\n+\t{ .compatible = \"qcom,scm-ipq806x\" },\n \t{ .compatible = \"qcom,scm-mdm9607\", .data = (void *)(SCM_HAS_CORE_CLK |\n \t\t\t\t\t\t\t     SCM_HAS_IFACE_CLK |\n \t\t\t\t\t\t\t     SCM_HAS_BUS_CLK) },\n"
  },
  {
    "path": "target/linux/ipq806x/patches-5.15/082-ipq8064-dtsi-tweaks.patch",
    "content": "--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi\n+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi\n@@ -352,6 +352,7 @@\n \t\t\tgpio-ranges = <&qcom_pinmux 0 0 69>;\n \t\t\t#gpio-cells = <2>;\n \t\t\tinterrupt-controller;\n+\t\t\t#address-cells = <0>;\n \t\t\t#interrupt-cells = <2>;\n \t\t\tinterrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;\n \n@@ -379,6 +380,7 @@\n \t\t\t\t\tfunction = \"pcie3_rst\";\n \t\t\t\t\tdrive-strength = <12>;\n \t\t\t\t\tbias-disable;\n+\t\t\t\t\toutput-low;\n \t\t\t\t};\n \t\t\t};\n \n@@ -411,12 +413,9 @@\n \t\t\t};\n \n \t\t\tnand_pins: nand_pins {\n-\t\t\t\tmux {\n+\t\t\t\tdisable {\n \t\t\t\t\tpins = \"gpio34\", \"gpio35\", \"gpio36\",\n-\t\t\t\t\t       \"gpio37\", \"gpio38\", \"gpio39\",\n-\t\t\t\t\t       \"gpio40\", \"gpio41\", \"gpio42\",\n-\t\t\t\t\t       \"gpio43\", \"gpio44\", \"gpio45\",\n-\t\t\t\t\t       \"gpio46\", \"gpio47\";\n+\t\t\t\t\t       \"gpio37\", \"gpio38\";\n \t\t\t\t\tfunction = \"nand\";\n \t\t\t\t\tdrive-strength = <10>;\n \t\t\t\t\tbias-disable;\n@@ -424,6 +423,8 @@\n \n \t\t\t\tpullups {\n \t\t\t\t\tpins = \"gpio39\";\n+\t\t\t\t\tfunction = \"nand\";\n+\t\t\t\t\tdrive-strength = <10>;\n \t\t\t\t\tbias-pull-up;\n \t\t\t\t};\n \n@@ -431,6 +432,8 @@\n \t\t\t\t\tpins = \"gpio40\", \"gpio41\", \"gpio42\",\n \t\t\t\t\t       \"gpio43\", \"gpio44\", \"gpio45\",\n \t\t\t\t\t       \"gpio46\", \"gpio47\";\n+\t\t\t\t\tfunction = \"nand\";\n+\t\t\t\t\tdrive-strength = <10>;\n \t\t\t\t\tbias-bus-hold;\n \t\t\t\t};\n \t\t\t};\n@@ -439,6 +442,7 @@\n \t\tintc: interrupt-controller@2000000 {\n \t\t\tcompatible = \"qcom,msm-qgic2\";\n \t\t\tinterrupt-controller;\n+\t\t\t#address-cells = <0>;\n \t\t\t#interrupt-cells = <3>;\n \t\t\treg = <0x02000000 0x1000>,\n \t\t\t      <0x02002000 0x1000>;\n@@ -468,11 +472,13 @@\n \t\tacc0: clock-controller@2088000 {\n \t\t\tcompatible = \"qcom,kpss-acc-v1\";\n \t\t\treg = <0x02088000 0x1000>, <0x02008000 0x1000>;\n+\t\t\tclock-output-names = \"acpu0_aux\";\n \t\t};\n \n \t\tacc1: clock-controller@2098000 {\n \t\t\tcompatible = \"qcom,kpss-acc-v1\";\n \t\t\treg = <0x02098000 0x1000>, <0x02008000 0x1000>;\n+\t\t\tclock-output-names = \"acpu1_aux\";\n \t\t};\n \n \t\tadm_dma: dma-controller@18300000 {\n@@ -496,13 +502,13 @@\n \t\t};\n \n \t\tsaw0: regulator@2089000 {\n-\t\t\tcompatible = \"qcom,saw2\";\n+\t\t\tcompatible = \"qcom,saw2\", \"qcom,apq8064-saw2-v1.1-cpu\", \"syscon\";\n \t\t\treg = <0x02089000 0x1000>, <0x02009000 0x1000>;\n \t\t\tregulator;\n \t\t};\n \n \t\tsaw1: regulator@2099000 {\n-\t\t\tcompatible = \"qcom,saw2\";\n+\t\t\tcompatible = \"qcom,saw2\", \"qcom,apq8064-saw2-v1.1-cpu\", \"syscon\";\n \t\t\treg = <0x02099000 0x1000>, <0x02009000 0x1000>;\n \t\t\tregulator;\n \t\t};\n@@ -530,7 +536,7 @@\n \t\t\t\tstatus = \"disabled\";\n \t\t\t};\n \n-\t\t\ti2c@124a0000 {\n+\t\t\tgsbi2_i2c: i2c@124a0000 {\n \t\t\t\tcompatible = \"qcom,i2c-qup-v1.1.1\";\n \t\t\t\treg = <0x124a0000 0x1000>;\n \t\t\t\tinterrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;\n@@ -676,9 +682,6 @@\n \t\t\tcompatible = \"qcom,ipq806x-nand\";\n \t\t\treg = <0x1ac00000 0x800>;\n \n-\t\t\tpinctrl-0 = <&nand_pins>;\n-\t\t\tpinctrl-names = \"default\";\n-\n \t\t\tclocks = <&gcc EBI2_CLK>,\n \t\t\t\t <&gcc EBI2_AON_CLK>;\n \t\t\tclock-names = \"core\", \"aon\";\n@@ -733,10 +736,13 @@\n \t\t\ttsens_calib_backup: calib_backup@410 {\n \t\t\t\treg = <0x410 0xb>;\n \t\t\t};\n+\t\t\tspeedbin_efuse: speedbin@0c0 {\n+\t\t\t\treg = <0x0c0 0x4>;\n+\t\t\t};\n \t\t};\n \n \t\tgcc: clock-controller@900000 {\n-\t\t\tcompatible = \"qcom,gcc-ipq8064\";\n+\t\t\tcompatible = \"qcom,gcc-ipq8064\", \"syscon\";\n \t\t\treg = <0x00900000 0x4000>;\n \t\t\t#clock-cells = <1>;\n \t\t\t#reset-cells = <1>;\n@@ -768,10 +774,45 @@\n \t\t\tclocks = <&gcc RPM_MSG_RAM_H_CLK>;\n \t\t\tclock-names = \"ram\";\n \n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n \t\t\trpmcc: clock-controller {\n \t\t\t\tcompatible = \"qcom,rpmcc-ipq806x\", \"qcom,rpmcc\";\n \t\t\t\t#clock-cells = <1>;\n \t\t\t};\n+\n+\t\t\tregulators {\n+\t\t\t\tcompatible = \"qcom,rpm-smb208-regulators\";\n+\n+\t\t\t\tsmb208_s1a: s1a {\n+\t\t\t\t\tregulator-min-microvolt = <1050000>;\n+\t\t\t\t\tregulator-max-microvolt = <1150000>;\n+\n+\t\t\t\t\tqcom,switch-mode-frequency = <1200000>;\n+\t\t\t\t};\n+\n+\t\t\t\tsmb208_s1b: s1b {\n+\t\t\t\t\tregulator-min-microvolt = <1050000>;\n+\t\t\t\t\tregulator-max-microvolt = <1150000>;\n+\n+\t\t\t\t\tqcom,switch-mode-frequency = <1200000>;\n+\t\t\t\t};\n+\n+\t\t\t\tsmb208_s2a: s2a {\n+\t\t\t\t\tregulator-min-microvolt = < 800000>;\n+\t\t\t\t\tregulator-max-microvolt = <1250000>;\n+\n+\t\t\t\t\tqcom,switch-mode-frequency = <1200000>;\n+\t\t\t\t};\n+\n+\t\t\t\tsmb208_s2b: s2b {\n+\t\t\t\t\tregulator-min-microvolt = < 800000>;\n+\t\t\t\t\tregulator-max-microvolt = <1250000>;\n+\n+\t\t\t\t\tqcom,switch-mode-frequency = <1200000>;\n+\t\t\t\t};\n+\t\t\t};\n \t\t};\n \n \t\ttcsr: syscon@1a400000 {\n@@ -965,7 +1006,7 @@\n \n \t\tgmac0: ethernet@37000000 {\n \t\t\tdevice_type = \"network\";\n-\t\t\tcompatible = \"qcom,ipq806x-gmac\";\n+\t\t\tcompatible = \"qcom,ipq806x-gmac\", \"snps,dwmac\";\n \t\t\treg = <0x37000000 0x200000>;\n \t\t\tinterrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;\n \t\t\tinterrupt-names = \"macirq\";\n@@ -989,7 +1030,7 @@\n \n \t\tgmac1: ethernet@37200000 {\n \t\t\tdevice_type = \"network\";\n-\t\t\tcompatible = \"qcom,ipq806x-gmac\";\n+\t\t\tcompatible = \"qcom,ipq806x-gmac\", \"snps,dwmac\";\n \t\t\treg = <0x37200000 0x200000>;\n \t\t\tinterrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;\n \t\t\tinterrupt-names = \"macirq\";\n@@ -1013,7 +1054,7 @@\n \n \t\tgmac2: ethernet@37400000 {\n \t\t\tdevice_type = \"network\";\n-\t\t\tcompatible = \"qcom,ipq806x-gmac\";\n+\t\t\tcompatible = \"qcom,ipq806x-gmac\", \"snps,dwmac\";\n \t\t\treg = <0x37400000 0x200000>;\n \t\t\tinterrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;\n \t\t\tinterrupt-names = \"macirq\";\n@@ -1037,7 +1078,7 @@\n \n \t\tgmac3: ethernet@37600000 {\n \t\t\tdevice_type = \"network\";\n-\t\t\tcompatible = \"qcom,ipq806x-gmac\";\n+\t\t\tcompatible = \"qcom,ipq806x-gmac\", \"snps,dwmac\";\n \t\t\treg = <0x37600000 0x200000>;\n \t\t\tinterrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;\n \t\t\tinterrupt-names = \"macirq\";\n@@ -1065,8 +1106,6 @@\n \t\t\tclocks = <&gcc USB30_0_UTMI_CLK>;\n \t\t\tclock-names = \"ref\";\n \t\t\t#phy-cells = <0>;\n-\n-\t\t\tstatus = \"disabled\";\n \t\t};\n \n \t\tss_phy_0: phy@100f8830 {\n@@ -1075,8 +1114,6 @@\n \t\t\tclocks = <&gcc USB30_0_MASTER_CLK>;\n \t\t\tclock-names = \"ref\";\n \t\t\t#phy-cells = <0>;\n-\n-\t\t\tstatus = \"disabled\";\n \t\t};\n \n \t\tusb3_0: usb3@100f8800 {\n@@ -1176,7 +1213,7 @@\n \t\t};\n \n \t\tamba: amba {\n-\t\t\tcompatible = \"simple-bus\";\n+\t\t\tcompatible = \"arm,amba-bus\";\n \t\t\t#address-cells = <1>;\n \t\t\t#size-cells = <1>;\n \t\t\tranges;\n@@ -1195,7 +1232,6 @@\n \t\t\t\tnon-removable;\n \t\t\t\tcap-sd-highspeed;\n \t\t\t\tcap-mmc-highspeed;\n-\t\t\t\tmmc-ddr-1_8v;\n \t\t\t\tvmmc-supply = <&vsdcc_fixed>;\n \t\t\t\tdmas = <&sdcc1bam 2>, <&sdcc1bam 1>;\n \t\t\t\tdma-names = \"tx\", \"rx\";\n"
  },
  {
    "path": "target/linux/ipq806x/patches-5.15/083-ipq8064-dtsi-additions.patch",
    "content": "--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi\n+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi\n@@ -10,6 +10,8 @@\n #include <dt-bindings/reset/qcom,gcc-ipq806x.h>\n #include <dt-bindings/soc/qcom,gsbi.h>\n #include <dt-bindings/interrupt-controller/arm-gic.h>\n+#include <dt-bindings/mfd/qcom-rpm.h>\n+#include <dt-bindings/clock/qcom,rpmcc.h>\n \n / {\n \t#address-cells = <1>;\n@@ -30,6 +32,16 @@\n \t\t\tnext-level-cache = <&L2>;\n \t\t\tqcom,acc = <&acc0>;\n \t\t\tqcom,saw = <&saw0>;\n+\t\t\tclocks = <&kraitcc 0>, <&kraitcc 4>;\n+\t\t\tclock-names = \"cpu\", \"l2\";\n+\t\t\tclock-latency = <100000>;\n+\t\t\tcpu-supply = <&smb208_s2a>;\n+\t\t\toperating-points-v2 = <&opp_table0>;\n+\t\t\tvoltage-tolerance = <5>;\n+\t\t\tcooling-min-state = <0>;\n+\t\t\tcooling-max-state = <10>;\n+\t\t\t#cooling-cells = <2>;\n+\t\t\tcpu-idle-states = <&CPU_SPC>;\n \t\t};\n \n \t\tcpu1: cpu@1 {\n@@ -40,11 +52,125 @@\n \t\t\tnext-level-cache = <&L2>;\n \t\t\tqcom,acc = <&acc1>;\n \t\t\tqcom,saw = <&saw1>;\n+\t\t\tclocks = <&kraitcc 1>, <&kraitcc 4>;\n+\t\t\tclock-names = \"cpu\", \"l2\";\n+\t\t\tclock-latency = <100000>;\n+\t\t\tcpu-supply = <&smb208_s2b>;\n+\t\t\toperating-points-v2 = <&opp_table0>;\n+\t\t\tvoltage-tolerance = <5>;\n+\t\t\tcooling-min-state = <0>;\n+\t\t\tcooling-max-state = <10>;\n+\t\t\t#cooling-cells = <2>;\n+\t\t\tcpu-idle-states = <&CPU_SPC>;\n+ \t\t};\n+\n+\t\tidle-states {\n+\t\t\tCPU_SPC: spc {\n+\t\t\t\tcompatible = \"qcom,idle-state-spc\";\n+\t\t\t\tstatus = \"disabled\";\n+\t\t\t\tentry-latency-us = <400>;\n+\t\t\t\texit-latency-us = <900>;\n+\t\t\t\tmin-residency-us = <3000>;\n+\t\t\t};\n \t\t};\n+\t};\n \n-\t\tL2: l2-cache {\n-\t\t\tcompatible = \"cache\";\n-\t\t\tcache-level = <2>;\n+\topp_table_l2: opp_table_l2 {\n+\t\tcompatible = \"operating-points-v2\";\n+\n+\t\topp-384000000 {\n+\t\t\topp-hz = /bits/ 64 <384000000>;\n+\t\t\topp-microvolt = <1100000>;\n+\t\t\tclock-latency-ns = <100000>;\n+\t\t\topp-level = <0>;\n+\t\t};\n+\n+\t\topp-1000000000 {\n+\t\t\topp-hz = /bits/ 64 <1000000000>;\n+\t\t\topp-microvolt = <1100000>;\n+\t\t\tclock-latency-ns = <100000>;\n+\t\t\topp-level = <1>;\n+\t\t};\n+\n+\t\topp-1200000000 {\n+\t\t\topp-hz = /bits/ 64 <1200000000>;\n+\t\t\topp-microvolt = <1150000>;\n+\t\t\tclock-latency-ns = <100000>;\n+\t\t\topp-level = <2>;\n+\t\t};\n+\t};\n+\n+\topp_table0: opp_table0 {\n+\t\tcompatible = \"operating-points-v2-kryo-cpu\";\n+\t\tnvmem-cells = <&speedbin_efuse>;\n+\n+\t\t/*\n+\t\t * Voltage thresholds are <target min max>\n+\t\t */\n+\t\topp-384000000 {\n+\t\t\topp-hz = /bits/ 64 <384000000>;\n+\t\t\topp-microvolt-speed0-pvs0-v0 = <1000000 950000 1050000>;\n+\t\t\topp-microvolt-speed0-pvs1-v0 = <925000 878750 971250>;\n+\t\t\topp-microvolt-speed0-pvs2-v0 = <875000 831250 918750>;\n+\t\t\topp-microvolt-speed0-pvs3-v0 = <800000 760000 840000>;\n+\t\t\topp-supported-hw = <0x1>;\n+\t\t\tclock-latency-ns = <100000>;\n+\t\t\topp-level = <0>;\n+\t\t};\n+\n+\t\topp-600000000 {\n+\t\t\topp-hz = /bits/ 64 <600000000>;\n+\t\t\topp-microvolt-speed0-pvs0-v0 = <1050000 997500 1102500>;\n+\t\t\topp-microvolt-speed0-pvs1-v0 = <975000 926250 1023750>;\n+\t\t\topp-microvolt-speed0-pvs2-v0 = <925000 878750 971250>;\n+\t\t\topp-microvolt-speed0-pvs3-v0 = <850000 807500 892500>;\n+\t\t\topp-supported-hw = <0x1>;\n+\t\t\tclock-latency-ns = <100000>;\n+\t\t\topp-level = <1>;\n+\t\t};\n+\n+\t\topp-800000000 {\n+\t\t\topp-hz = /bits/ 64 <800000000>;\n+\t\t\topp-microvolt-speed0-pvs0-v0 = <1100000 1045000 1155000>;\n+\t\t\topp-microvolt-speed0-pvs1-v0 = <1025000 973750 1076250>;\n+\t\t\topp-microvolt-speed0-pvs2-v0 = <995000 945250 1044750>;\n+\t\t\topp-microvolt-speed0-pvs3-v0 = <900000 855000 945000>;\n+\t\t\topp-supported-hw = <0x1>;\n+\t\t\tclock-latency-ns = <100000>;\n+\t\t\topp-level = <1>;\n+\t\t};\n+\n+\t\topp-1000000000 {\n+\t\t\topp-hz = /bits/ 64 <1000000000>;\n+\t\t\topp-microvolt-speed0-pvs0-v0 = <1150000 1092500 1207500>;\n+\t\t\topp-microvolt-speed0-pvs1-v0 = <1075000 1021250 1128750>;\n+\t\t\topp-microvolt-speed0-pvs2-v0 = <1025000 973750 1076250>;\n+\t\t\topp-microvolt-speed0-pvs3-v0 = <950000 902500 997500>;\n+\t\t\topp-supported-hw = <0x1>;\n+\t\t\tclock-latency-ns = <100000>;\n+\t\t\topp-level = <1>;\n+\t\t};\n+\n+\t\topp-1200000000 {\n+\t\t\topp-hz = /bits/ 64 <1200000000>;\n+\t\t\topp-microvolt-speed0-pvs0-v0 = <1200000 1140000 1260000>;\n+\t\t\topp-microvolt-speed0-pvs1-v0 = <1125000 1068750 1181250>;\n+\t\t\topp-microvolt-speed0-pvs2-v0 = <1075000 1021250 1128750>;\n+\t\t\topp-microvolt-speed0-pvs3-v0 = <1000000 950000 1050000>;\n+\t\t\topp-supported-hw = <0x1>;\n+\t\t\tclock-latency-ns = <100000>;\n+\t\t\topp-level = <2>;\n+\t\t};\n+\n+\t\topp-1400000000 {\n+\t\t\topp-hz = /bits/ 64 <1400000000>;\n+\t\t\topp-microvolt-speed0-pvs0-v0 = <1250000 1187500 1312500>;\n+\t\t\topp-microvolt-speed0-pvs1-v0 = <1175000 1116250 1233750>;\n+\t\t\topp-microvolt-speed0-pvs2-v0 = <1125000 1068750 1181250>;\n+\t\t\topp-microvolt-speed0-pvs3-v0 = <1050000 997500 1102500>;\n+\t\t\topp-supported-hw = <0x1>;\n+\t\t\tclock-latency-ns = <100000>;\n+\t\t\topp-level = <2>;\n \t\t};\n \t};\n \n@@ -317,6 +443,15 @@\n \t\t};\n \t};\n \n+\tfab-scaling {\n+\t\tcompatible = \"qcom,fab-scaling\";\n+\t\tclocks = <&rpmcc RPM_APPS_FABRIC_A_CLK>, <&rpmcc RPM_EBI1_A_CLK>;\n+\t\tclock-names = \"apps-fab-clk\", \"ddr-fab-clk\";\n+\t\tfab_freq_high = <533000000>;\n+\t\tfab_freq_nominal = <400000000>;\n+\t\tcpu_freq_threshold = <1000000000>;\n+\t};\n+\n \tfirmware {\n \t\tscm {\n \t\t\tcompatible = \"qcom,scm-ipq806x\", \"qcom,scm\";\n@@ -384,6 +519,15 @@\n \t\t\t\t};\n \t\t\t};\n \n+\t\t\ti2c4_pins: i2c4_pinmux {\n+\t\t\t\tmux {\n+\t\t\t\t\tpins = \"gpio12\", \"gpio13\";\n+\t\t\t\t\tfunction = \"gsbi4\";\n+\t\t\t\t\tdrive-strength = <12>;\n+\t\t\t\t\tbias-disable;\n+\t\t\t\t};\n+\t\t\t};\n+\n \t\t\tspi_pins: spi_pins {\n \t\t\t\tmux {\n \t\t\t\t\tpins = \"gpio18\", \"gpio19\", \"gpio21\";\n@@ -437,6 +581,27 @@\n \t\t\t\t\tbias-bus-hold;\n \t\t\t\t};\n \t\t\t};\n+\n+\t\t\tmdio0_pins: mdio0_pins {\n+\t\t\t\tmux {\n+\t\t\t\t\tpins = \"gpio0\", \"gpio1\";\n+\t\t\t\t\tfunction = \"mdio\";\n+\t\t\t\t\tdrive-strength = <8>;\n+\t\t\t\t\tbias-disable;\n+\t\t\t\t};\n+\t\t\t};\n+\n+\t\t\trgmii2_pins: rgmii2_pins {\n+\t\t\t\tmux {\n+\t\t\t\t\tpins = \"gpio27\", \"gpio28\", \"gpio29\",\n+\t\t\t\t\t       \"gpio30\", \"gpio31\", \"gpio32\",\n+\t\t\t\t\t       \"gpio51\", \"gpio52\", \"gpio59\",\n+\t\t\t\t\t       \"gpio60\", \"gpio61\", \"gpio62\";\n+\t\t\t\t\tfunction = \"rgmii2\";\n+\t\t\t\t\tdrive-strength = <8>;\n+\t\t\t\t\tbias-disable;\n+\t\t\t\t};\n+\t\t\t};\n \t\t};\n \n \t\tintc: interrupt-controller@2000000 {\n@@ -513,6 +678,17 @@\n \t\t\tregulator;\n \t\t};\n \n+\t\tsaw_l2: regulator@02012000 {\n+\t\t\tcompatible = \"qcom,saw2\", \"syscon\";\n+\t\t\treg = <0x02012000 0x1000>;\n+\t\t\tregulator;\n+\t\t};\n+\n+\t\tsic_non_secure: sic-non-secure@12100000 {\n+\t\t\tcompatible = \"syscon\";\n+\t\t\treg = <0x12100000 0x10000>;\n+\t\t};\n+\n \t\tgsbi2: gsbi@12480000 {\n \t\t\tcompatible = \"qcom,gsbi-v1.0.0\";\n \t\t\tcell-index = <2>;\n@@ -637,6 +813,33 @@\n \t\t\t};\n \t\t};\n \n+\t\tgsbi6: gsbi@16500000 {\n+\t\t\tstatus = \"disabled\";\n+\t\t\tcompatible = \"qcom,gsbi-v1.0.0\";\n+\t\t\tcell-index = <6>;\n+\t\t\treg = <0x16500000 0x100>;\n+\t\t\tclocks = <&gcc GSBI6_H_CLK>;\n+\t\t\tclock-names = \"iface\";\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <1>;\n+\t\t\tranges;\n+\n+\t\t\tsyscon-tcsr = <&tcsr>;\n+\n+\t\t\tgsbi6_i2c: i2c@16580000 {\n+\t\t\t\tcompatible = \"qcom,i2c-qup-v1.1.1\";\n+\t\t\t\treg = <0x16580000 0x1000>;\n+\t\t\t\tinterrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;\n+\n+\t\t\t\tclocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>;\n+\t\t\t\tclock-names = \"core\", \"iface\";\n+\t\t\t\tstatus = \"disabled\";\n+\n+\t\t\t\t#address-cells = <1>;\n+\t\t\t\t#size-cells = <0>;\n+\t\t\t};\n+\t\t};\n+\n \t\tgsbi7: gsbi@16600000 {\n \t\t\tstatus = \"disabled\";\n \t\t\tcompatible = \"qcom,gsbi-v1.0.0\";\n@@ -658,6 +861,19 @@\n \t\t\t\tclock-names = \"core\", \"iface\";\n \t\t\t\tstatus = \"disabled\";\n \t\t\t};\n+\n+\t\t\tgsbi7_i2c: i2c@16680000 {\n+ \t\t\t\tcompatible = \"qcom,i2c-qup-v1.1.1\";\n+ \t\t\t\treg = <0x16680000 0x1000>;\n+\t\t\t\tinterrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;\n+\n+ \t\t\t\tclocks = <&gcc GSBI7_QUP_CLK>, <&gcc GSBI7_H_CLK>;\n+ \t\t\t\tclock-names = \"core\", \"iface\";\n+\t\t\t\tstatus = \"disabled\";\n+\n+ \t\t\t\t#address-cells = <1>;\n+\t\t\t\t#size-cells = <0>;\n+\t\t\t};\n \t\t};\n \n \t\trng@1a500000 {\n@@ -761,6 +977,17 @@\n \t\t\t};\n \t\t};\n \n+\t\tL2: l2-cache {\n+\t\t\tcompatible = \"qcom,krait-cache\", \"cache\";\n+\t\t\tcache-level = <2>;\n+\t\t\tqcom,saw = <&saw_l2>;\n+\n+\t\t\tclocks = <&kraitcc 4>;\n+\t\t\tclock-names = \"l2\";\n+\t\t\tl2-supply = <&smb208_s1a>;\n+\t\t\toperating-points-v2 = <&opp_table_l2>;\n+\t\t};\n+\n \t\trpm: rpm@108000 {\n \t\t\tcompatible = \"qcom,rpm-ipq8064\";\n \t\t\treg = <0x108000 0x1000>;\n@@ -828,6 +1055,11 @@\n \t\t\tclock-output-names = \"acpu_l2_aux\";\n \t\t};\n \n+\t\tkraitcc: clock-controller {\n+\t\t\tcompatible = \"qcom,krait-cc-v1\";\n+\t\t\t#clock-cells = <1>;\n+\t\t};\n+\n \t\tlcc: clock-controller@28000000 {\n \t\t\tcompatible = \"qcom,lcc-ipq8064\";\n \t\t\treg = <0x28000000 0x1000>;\n@@ -835,6 +1067,11 @@\n \t\t\t#reset-cells = <1>;\n \t\t};\n \n+\t\tsfpb_mutex_block: syscon@1200600 {\n+\t\t\tcompatible = \"syscon\";\n+\t\t\treg = <0x01200600 0x100>;\n+\t\t};\n+\n \t\tpcie0: pci@1b500000 {\n \t\t\tcompatible = \"qcom,pcie-ipq8064\";\n \t\t\treg = <0x1b500000 0x1000\n@@ -1184,6 +1421,21 @@\n \t\t\t};\n \t\t};\n \n+\n+\t\tmdio0: mdio@37000000 {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tcompatible = \"qcom,ipq8064-mdio\", \"syscon\";\n+\t\t\treg = <0x37000000 0x200000>;\n+\t\t\tresets = <&gcc GMAC_CORE1_RESET>;\n+\t\t\treset-names = \"stmmaceth\";\n+\t\t\tclocks = <&gcc GMAC_CORE1_CLK>;\n+\t\t\tclock-names = \"stmmaceth\";\n+\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n \t\tvsdcc_fixed: vsdcc-regulator {\n \t\t\tcompatible = \"regulator-fixed\";\n \t\t\tregulator-name = \"SDCC Power\";\n@@ -1258,4 +1510,17 @@\n \t\t\t};\n \t\t};\n \t};\n+\n+\tsfpb_mutex: sfpb-mutex {\n+\t\tcompatible = \"qcom,sfpb-mutex\";\n+\t\tsyscon = <&sfpb_mutex_block 4 4>;\n+\n+\t\t#hwlock-cells = <1>;\n+\t};\n+\n+\tsmem {\n+\t\tcompatible = \"qcom,smem\";\n+\t\tmemory-region = <&smem>;\n+\t\thwlocks = <&sfpb_mutex 3>;\n+\t};\n };\n"
  },
  {
    "path": "target/linux/ipq806x/patches-5.15/084-ipq8064-v1.0-dtsi-cleanup.patch",
    "content": "This uses upstream qcom-ipq8064-v1.0.dtsi and modifies it by patches\ninstead of keeping a local version.\nWe drop partitions, LEDs and keys from the file as we will implement\nthem differently anyway.\n\n--- a/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi\n+++ b/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi\n@@ -42,16 +42,6 @@\n \t\t\t\t\t#size-cells = <1>;\n \t\t\t\t\tspi-max-frequency = <50000000>;\n \t\t\t\t\treg = <0>;\n-\n-\t\t\t\t\tpartition@0 {\n-\t\t\t\t\t\tlabel = \"rootfs\";\n-\t\t\t\t\t\treg = <0x0 0x1000000>;\n-\t\t\t\t\t};\n-\n-\t\t\t\t\tpartition@1 {\n-\t\t\t\t\t\tlabel = \"scratch\";\n-\t\t\t\t\t\treg = <0x1000000 0x1000000>;\n-\t\t\t\t\t};\n \t\t\t\t};\n \t\t\t};\n \t\t};\n@@ -64,64 +54,5 @@\n \t\t\tports-implemented = <0x1>;\n \t\t\tstatus = \"okay\";\n \t\t};\n-\n-\t\tgpio_keys {\n-\t\t\tcompatible = \"gpio-keys\";\n-\t\t\tpinctrl-0 = <&buttons_pins>;\n-\t\t\tpinctrl-names = \"default\";\n-\n-\t\t\tbutton@1 {\n-\t\t\t\tlabel = \"reset\";\n-\t\t\t\tlinux,code = <KEY_RESTART>;\n-\t\t\t\tgpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;\n-\t\t\t\tlinux,input-type = <1>;\n-\t\t\t\tdebounce-interval = <60>;\n-\t\t\t};\n-\t\t\tbutton@2 {\n-\t\t\t\tlabel = \"wps\";\n-\t\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n-\t\t\t\tgpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>;\n-\t\t\t\tlinux,input-type = <1>;\n-\t\t\t\tdebounce-interval = <60>;\n-\t\t\t};\n-\t\t};\n-\n-\t\tleds {\n-\t\t\tcompatible = \"gpio-leds\";\n-\t\t\tpinctrl-0 = <&leds_pins>;\n-\t\t\tpinctrl-names = \"default\";\n-\n-\t\t\tled@7 {\n-\t\t\t\tlabel = \"led_usb1\";\n-\t\t\t\tgpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>;\n-\t\t\t\tlinux,default-trigger = \"usbdev\";\n-\t\t\t\tdefault-state = \"off\";\n-\t\t\t};\n-\n-\t\t\tled@8 {\n-\t\t\t\tlabel = \"led_usb3\";\n-\t\t\t\tgpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;\n-\t\t\t\tlinux,default-trigger = \"usbdev\";\n-\t\t\t\tdefault-state = \"off\";\n-\t\t\t};\n-\n-\t\t\tled@9 {\n-\t\t\t\tlabel = \"status_led_fail\";\n-\t\t\t\tgpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;\n-\t\t\t\tdefault-state = \"off\";\n-\t\t\t};\n-\n-\t\t\tled@26 {\n-\t\t\t\tlabel = \"sata_led\";\n-\t\t\t\tgpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>;\n-\t\t\t\tdefault-state = \"off\";\n-\t\t\t};\n-\n-\t\t\tled@53 {\n-\t\t\t\tlabel = \"status_led_pass\";\n-\t\t\t\tgpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>;\n-\t\t\t\tdefault-state = \"off\";\n-\t\t\t};\n-\t\t};\n \t};\n };\n"
  },
  {
    "path": "target/linux/ipq806x/patches-5.15/085-ipq8064-v1.0-dtsi-additions.patch",
    "content": "This uses upstream qcom-ipq8064-v1.0.dtsi and modifies it by patches\ninstead of keeping a local version. This patch adds our local adjustments\nfor the (local) additional contents of qcom-ipq8064.dtsi\n\n--- a/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi\n+++ b/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi\n@@ -56,3 +56,7 @@\n \t\t};\n \t};\n };\n+\n+&CPU_SPC {\n+\tstatus = \"okay\";\n+};\n"
  },
  {
    "path": "target/linux/ipq806x/patches-5.15/086-ipq8064-fix-duplicate-node.patch",
    "content": "--- a/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts\n+++ b/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts\n@@ -24,73 +24,6 @@\n \t\tdevice_type = \"memory\";\n \t};\n \n-\tmdio0: mdio-0 {\n-\t\tstatus = \"okay\";\n-\t\tcompatible = \"virtual,mdio-gpio\";\n-\t\tgpios = <&qcom_pinmux 1 GPIO_ACTIVE_HIGH>,\n-\t\t\t<&qcom_pinmux 0 GPIO_ACTIVE_HIGH>;\n-\t\t#address-cells = <1>;\n-\t\t#size-cells = <0>;\n-\n-\t\tpinctrl-0 = <&mdio0_pins>;\n-\t\tpinctrl-names = \"default\";\n-\n-\t\tswitch0: switch@10 {\n-\t\t\tcompatible = \"qca,qca8337\";\n-\t\t\t#address-cells = <1>;\n-\t\t\t#size-cells = <0>;\n-\n-\t\t\tdsa,member = <0 0>;\n-\n-\t\t\tpinctrl-0 = <&sw0_reset_pin>;\n-\t\t\tpinctrl-names = \"default\";\n-\n-\t\t\treset-gpios = <&qcom_pinmux 16 GPIO_ACTIVE_LOW>;\n-\t\t\treg = <0x10>;\n-\n-\t\t\tports {\n-\t\t\t\t#address-cells = <1>;\n-\t\t\t\t#size-cells = <0>;\n-\n-\t\t\t\tswitch0cpu: port@0 {\n-\t\t\t\t\treg = <0>;\n-\t\t\t\t\tlabel = \"cpu\";\n-\t\t\t\t\tethernet = <&gmac0>;\n-\t\t\t\t\tphy-mode = \"rgmii-id\";\n-\t\t\t\t\tfixed-link {\n-\t\t\t\t\t\tspeed = <1000>;\n-\t\t\t\t\t\tfull-duplex;\n-\t\t\t\t\t};\n-\t\t\t\t};\n-\n-\t\t\t\tport@1 {\n-\t\t\t\t\treg = <1>;\n-\t\t\t\t\tlabel = \"sw1\";\n-\t\t\t\t};\n-\n-\t\t\t\tport@2 {\n-\t\t\t\t\treg = <2>;\n-\t\t\t\t\tlabel = \"sw2\";\n-\t\t\t\t};\n-\n-\t\t\t\tport@3 {\n-\t\t\t\t\treg = <3>;\n-\t\t\t\t\tlabel = \"sw3\";\n-\t\t\t\t};\n-\n-\t\t\t\tport@4 {\n-\t\t\t\t\treg = <4>;\n-\t\t\t\t\tlabel = \"sw4\";\n-\t\t\t\t};\n-\n-\t\t\t\tport@5 {\n-\t\t\t\t\treg = <5>;\n-\t\t\t\t\tlabel = \"sw5\";\n-\t\t\t\t};\n-\t\t\t};\n-\t\t};\n-\t};\n-\n \tmdio1: mdio-1 {\n \t\tstatus = \"okay\";\n \t\tcompatible = \"virtual,mdio-gpio\";\n@@ -220,6 +153,68 @@\n \tstatus = \"okay\";\n };\n \n+&mdio0 {\n+\tstatus = \"okay\";\n+\n+\tpinctrl-0 = <&mdio0_pins>;\n+\tpinctrl-names = \"default\";\n+\n+\tswitch0: switch@10 {\n+\t\tcompatible = \"qca,qca8337\";\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\n+\t\tdsa,member = <0 0>;\n+\n+\t\tpinctrl-0 = <&sw0_reset_pin>;\n+\t\tpinctrl-names = \"default\";\n+\n+\t\treset-gpios = <&qcom_pinmux 16 GPIO_ACTIVE_LOW>;\n+\t\treg = <0x10>;\n+\n+\t\tports {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tswitch0cpu: port@0 {\n+\t\t\t\treg = <0>;\n+\t\t\t\tlabel = \"cpu\";\n+\t\t\t\tethernet = <&gmac0>;\n+\t\t\t\tphy-mode = \"rgmii-id\";\n+\t\t\t\tfixed-link {\n+\t\t\t\t\tspeed = <1000>;\n+\t\t\t\t\tfull-duplex;\n+\t\t\t\t};\n+\t\t\t};\n+\n+\t\t\tport@1 {\n+\t\t\t\treg = <1>;\n+\t\t\t\tlabel = \"sw1\";\n+\t\t\t};\n+\n+\t\t\tport@2 {\n+\t\t\t\treg = <2>;\n+\t\t\t\tlabel = \"sw2\";\n+\t\t\t};\n+\n+\t\t\tport@3 {\n+\t\t\t\treg = <3>;\n+\t\t\t\tlabel = \"sw3\";\n+\t\t\t};\n+\n+\t\t\tport@4 {\n+\t\t\t\treg = <4>;\n+\t\t\t\tlabel = \"sw4\";\n+\t\t\t};\n+\n+\t\t\tport@5 {\n+\t\t\t\treg = <5>;\n+\t\t\t\tlabel = \"sw5\";\n+\t\t\t};\n+\t\t};\n+\t};\n+};\n+\n &gmac0 {\n \tstatus = \"okay\";\n \n"
  },
  {
    "path": "target/linux/ipq806x/patches-5.15/093-drivers-cpufreq-qcom-cpufreq-nvmem-support-specific-.patch",
    "content": "From a206d4061f1cc2c5cd17ee45c53a0ba711e48e6d Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Sun, 7 Feb 2021 16:42:52 +0100\nSubject: [PATCH 3/3] drivers: cpufreq: qcom-cpufreq-nvmem: support specific\n cpufreq driver\n\nAdd support for specific cpufreq driver for qcom-cpufreq-nvmem driver.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\n---\n drivers/cpufreq/qcom-cpufreq-nvmem.c | 15 +++++++++++++++\n 1 file changed, 15 insertions(+)\n\n--- a/drivers/cpufreq/qcom-cpufreq-nvmem.c\n+++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c\n@@ -52,6 +52,7 @@ struct qcom_cpufreq_match_data {\n \t\t\t   char **pvs_name,\n \t\t\t   struct qcom_cpufreq_drv *drv);\n \tconst char **genpd_names;\n+\tconst char *cpufreq_driver;\n };\n \n struct qcom_cpufreq_drv {\n@@ -250,6 +251,7 @@ static const struct qcom_cpufreq_match_d\n \n static const struct qcom_cpufreq_match_data match_data_krait = {\n \t.get_version = qcom_cpufreq_krait_name_version,\n+\t.cpufreq_driver = \"krait-cpufreq\",\n };\n \n static const char *qcs404_genpd_names[] = { \"cpr\", NULL };\n@@ -385,6 +387,19 @@ static int qcom_cpufreq_probe(struct pla\n \t\t}\n \t}\n \n+\tif (drv->data->cpufreq_driver) {\n+\t\tcpufreq_dt_pdev = platform_device_register_simple(\n+\t\t\tdrv->data->cpufreq_driver, -1, NULL, 0);\n+\t\tif (!IS_ERR(cpufreq_dt_pdev)) {\n+\t\t\tplatform_set_drvdata(pdev, drv);\n+\t\t\treturn 0;\n+\t\t} else {\n+\t\t\tdev_err(cpu_dev,\n+\t\t\t\t\"Failed to register dedicated %s cpufreq\\n\",\n+\t\t\t\tdrv->data->cpufreq_driver);\n+\t\t}\n+\t}\n+\n \tcpufreq_dt_pdev = platform_device_register_simple(\"cpufreq-dt\", -1,\n \t\t\t\t\t\t\t  NULL, 0);\n \tif (!IS_ERR(cpufreq_dt_pdev)) {\n"
  },
  {
    "path": "target/linux/ipq806x/patches-5.15/097-1-ipq806x-gcc-add-missing-clk-flag.patch",
    "content": "From 0af44917941cbfecdc86bb9bf05ff01d22a88973 Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Sun, 7 Feb 2021 16:52:56 +0100\nSubject: [PATCH 1/4] ipq806x: gcc: add missing clk flag\n\nSome flag are missing from the original code.\nThese clk can't be set using the protected-clock proprities as they\ncause the malfunction of the serial interface.\nThese clks are needed for the rpm interface to work proprely or the\ncpu regulators starts to fail as soon as they are disabled by the\nkernel.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\n---\n drivers/clk/qcom/gcc-ipq806x.c | 19 +++++++++++++------\n 1 file changed, 13 insertions(+), 6 deletions(-)\n\n--- a/drivers/clk/qcom/gcc-ipq806x.c\n+++ b/drivers/clk/qcom/gcc-ipq806x.c\n@@ -65,6 +65,7 @@ static struct clk_pll pll3 = {\n \t\t.parent_names = (const char *[]){ \"pxo\" },\n \t\t.num_parents = 1,\n \t\t.ops = &clk_pll_ops,\n+\t\t.flags = CLK_IS_CRITICAL,\n \t},\n };\n \n@@ -782,7 +783,7 @@ static struct clk_rcg gsbi4_qup_src = {\n \t\t\t.parent_names = gcc_pxo_pll8,\n \t\t\t.num_parents = 2,\n \t\t\t.ops = &clk_rcg_ops,\n-\t\t\t.flags = CLK_SET_PARENT_GATE,\n+\t\t\t.flags = CLK_SET_PARENT_GATE | CLK_IGNORE_UNUSED,\n \t\t},\n \t},\n };\n@@ -798,7 +799,7 @@ static struct clk_branch gsbi4_qup_clk =\n \t\t\t.parent_names = (const char *[]){ \"gsbi4_qup_src\" },\n \t\t\t.num_parents = 1,\n \t\t\t.ops = &clk_branch_ops,\n-\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,\n \t\t},\n \t},\n };\n@@ -880,7 +881,7 @@ static struct clk_rcg gsbi6_qup_src = {\n \t\t\t.parent_names = gcc_pxo_pll8,\n \t\t\t.num_parents = 2,\n \t\t\t.ops = &clk_rcg_ops,\n-\t\t\t.flags = CLK_SET_PARENT_GATE,\n+\t\t\t.flags = CLK_SET_PARENT_GATE | CLK_IGNORE_UNUSED,\n \t\t},\n \t},\n };\n@@ -945,7 +946,7 @@ static struct clk_branch gsbi7_qup_clk =\n \t\t\t.parent_names = (const char *[]){ \"gsbi7_qup_src\" },\n \t\t\t.num_parents = 1,\n \t\t\t.ops = &clk_branch_ops,\n-\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,\n \t\t},\n \t},\n };\n@@ -991,6 +992,7 @@ static struct clk_branch gsbi4_h_clk = {\n \t\t.hw.init = &(struct clk_init_data){\n \t\t\t.name = \"gsbi4_h_clk\",\n \t\t\t.ops = &clk_branch_ops,\n+\t\t\t.flags = CLK_IGNORE_UNUSED,\n \t\t},\n \t},\n };\n@@ -1424,6 +1426,7 @@ static struct clk_rcg tsif_ref_src = {\n \t\t\t.parent_names = gcc_pxo_pll8,\n \t\t\t.num_parents = 2,\n \t\t\t.ops = &clk_rcg_ops,\n+\t\t\t.flags = CLK_SET_RATE_GATE,\n \t\t},\n \t}\n };\n@@ -2694,7 +2697,8 @@ static struct clk_dyn_rcg ubi32_core1_sr\n \t\t\t.parent_names = gcc_pxo_pll8_pll14_pll18_pll0,\n \t\t\t.num_parents = 5,\n \t\t\t.ops = &clk_dyn_rcg_ops,\n-\t\t\t.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,\n+\t\t\t.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE |\n+\t\t\t\t CLK_IGNORE_UNUSED,\n \t\t},\n \t},\n };\n@@ -2747,7 +2751,8 @@ static struct clk_dyn_rcg ubi32_core2_sr\n \t\t\t.parent_names = gcc_pxo_pll8_pll14_pll18_pll0,\n \t\t\t.num_parents = 5,\n \t\t\t.ops = &clk_dyn_rcg_ops,\n-\t\t\t.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,\n+\t\t\t.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE |\n+\t\t\t\t CLK_IGNORE_UNUSED,\n \t\t},\n \t},\n };\n"
  },
  {
    "path": "target/linux/ipq806x/patches-5.15/097-2-ipq806x-lcc-add-missing-reset.patch",
    "content": "From 3a5f1793c0bf4a6b536751886b0a44589fe05f35 Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Sun, 7 Feb 2021 17:00:07 +0100\nSubject: [PATCH 2/4] ipq806x: lcc: add missing reset\n\nAdd missing reset for ipq806x lcc clk\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\n---\n drivers/clk/qcom/lcc-ipq806x.c               | 8 ++++++++\n include/dt-bindings/clock/qcom,lcc-ipq806x.h | 1 +\n 2 files changed, 9 insertions(+)\n\n--- a/drivers/clk/qcom/lcc-ipq806x.c\n+++ b/drivers/clk/qcom/lcc-ipq806x.c\n@@ -12,6 +12,7 @@\n #include <linux/of_device.h>\n #include <linux/clk-provider.h>\n #include <linux/regmap.h>\n+#include <linux/reset-controller.h>\n \n #include <dt-bindings/clock/qcom,lcc-ipq806x.h>\n \n@@ -22,6 +23,7 @@\n #include \"clk-branch.h\"\n #include \"clk-regmap-divider.h\"\n #include \"clk-regmap-mux.h\"\n+#include \"reset.h\"\n \n static struct clk_pll pll4 = {\n \t.l_reg = 0x4,\n@@ -39,6 +41,10 @@ static struct clk_pll pll4 = {\n \t},\n };\n \n+static const struct qcom_reset_map lcc_ipq806x_resets[] = {\n+\t[LCC_PCM_RESET] = { 0x54, 13 },\n+};\n+\n static const struct pll_config pll4_config = {\n \t.l = 0xf,\n \t.m = 0x91,\n@@ -417,6 +423,8 @@ static const struct qcom_cc_desc lcc_ipq\n \t.config = &lcc_ipq806x_regmap_config,\n \t.clks = lcc_ipq806x_clks,\n \t.num_clks = ARRAY_SIZE(lcc_ipq806x_clks),\n+\t.resets = lcc_ipq806x_resets,\n+\t.num_resets = ARRAY_SIZE(lcc_ipq806x_resets),\n };\n \n static const struct of_device_id lcc_ipq806x_match_table[] = {\n--- a/include/dt-bindings/clock/qcom,lcc-ipq806x.h\n+++ b/include/dt-bindings/clock/qcom,lcc-ipq806x.h\n@@ -19,4 +19,5 @@\n #define SPDIF_CLK\t\t\t10\n #define AHBIX_CLK\t\t\t11\n \n+#define LCC_PCM_RESET\t\t\t0\n #endif\n"
  },
  {
    "path": "target/linux/ipq806x/patches-5.15/097-3-clk-qcom-krait-add-missing-enable-disable.patch",
    "content": "From f8fdbecdaca97f0f2eebd77256e2eca4a8da6c39 Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Sun, 7 Feb 2021 17:08:16 +0100\nSubject: [PATCH 3/4] clk: qcom: krait: add missing enable disable\n\nAdd missing enable disable mux function. Add extra check to\ndiv2_round_rate.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\n---\n drivers/clk/qcom/clk-krait.c | 27 +++++++++++++++++++++++++--\n 1 file changed, 25 insertions(+), 2 deletions(-)\n\n--- a/drivers/clk/qcom/clk-krait.c\n+++ b/drivers/clk/qcom/clk-krait.c\n@@ -68,7 +68,25 @@ static u8 krait_mux_get_parent(struct cl\n \treturn clk_mux_val_to_index(hw, mux->parent_map, 0, sel);\n }\n \n+static int krait_mux_enable(struct clk_hw *hw)\n+{\n+\tstruct krait_mux_clk *mux = to_krait_mux_clk(hw);\n+\n+\t__krait_mux_set_sel(mux, mux->en_mask);\n+\n+\treturn 0;\n+}\n+\n+static void krait_mux_disable(struct clk_hw *hw)\n+{\n+\tstruct krait_mux_clk *mux = to_krait_mux_clk(hw);\n+\n+\t__krait_mux_set_sel(mux, mux->safe_sel);\n+}\n+\n const struct clk_ops krait_mux_clk_ops = {\n+\t.enable = krait_mux_enable,\n+\t.disable = krait_mux_disable,\n \t.set_parent = krait_mux_set_parent,\n \t.get_parent = krait_mux_get_parent,\n \t.determine_rate = __clk_mux_determine_rate_closest,\n@@ -79,8 +97,13 @@ EXPORT_SYMBOL_GPL(krait_mux_clk_ops);\n static long krait_div2_round_rate(struct clk_hw *hw, unsigned long rate,\n \t\t\t\t  unsigned long *parent_rate)\n {\n-\t*parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw), rate * 2);\n-\treturn DIV_ROUND_UP(*parent_rate, 2);\n+\tstruct clk_hw *hw_parent = clk_hw_get_parent(hw);\n+\n+\tif (hw_parent) {\n+\t\t*parent_rate = clk_hw_round_rate(hw_parent, rate * 2);\n+\t\treturn DIV_ROUND_UP(*parent_rate, 2);\n+\t} else\n+\t\treturn -1;\n }\n \n static int krait_div2_set_rate(struct clk_hw *hw, unsigned long rate,\n"
  },
  {
    "path": "target/linux/ipq806x/patches-5.15/097-4-ipq806x-gcc-add-missing-clk-and-reset-for-crypto-eng.patch",
    "content": "From 22a0f55b0e505fbbbb680e451a62878bc97f7ff1 Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Sun, 7 Feb 2021 17:23:38 +0100\nSubject: [PATCH 4/4] ipq806x: gcc: add missing clk and reset for crypto engine\n\nAdd missing clk and reset needed for nss additional core and crypto\nengine.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\n---\n drivers/clk/qcom/gcc-ipq806x.c               | 250 +++++++++++++++++++\n include/dt-bindings/clock/qcom,gcc-ipq806x.h |   5 +-\n include/dt-bindings/reset/qcom,gcc-ipq806x.h |   5 +\n 3 files changed, 259 insertions(+), 1 deletion(-)\n\n--- a/drivers/clk/qcom/gcc-ipq806x.c\n+++ b/drivers/clk/qcom/gcc-ipq806x.c\n@@ -223,7 +223,9 @@ static struct clk_regmap pll14_vote = {\n \n static struct pll_freq_tbl pll18_freq_tbl[] = {\n \tNSS_PLL_RATE(550000000, 44, 0, 1, 0x01495625),\n+\tNSS_PLL_RATE(600000000, 48, 0, 1, 0x01495625),\n \tNSS_PLL_RATE(733000000, 58, 16, 25, 0x014b5625),\n+\tNSS_PLL_RATE(800000000, 64, 0, 1, 0x01495625),\n };\n \n static struct clk_pll pll18 = {\n@@ -245,6 +247,22 @@ static struct clk_pll pll18 = {\n \t},\n };\n \n+static struct clk_pll pll11 = {\n+\t.l_reg = 0x3184,\n+\t.m_reg = 0x3188,\n+\t.n_reg = 0x318c,\n+\t.config_reg = 0x3194,\n+\t.mode_reg = 0x3180,\n+\t.status_reg = 0x3198,\n+\t.status_bit = 16,\n+\t.clkr.hw.init = &(struct clk_init_data){\n+\t\t.name = \"pll11\",\n+\t\t.parent_names = (const char *[]){ \"pxo\" },\n+\t\t.num_parents = 1,\n+\t\t.ops = &clk_pll_ops,\n+\t},\n+};\n+\n enum {\n \tP_PXO,\n \tP_PLL8,\n@@ -253,6 +271,7 @@ enum {\n \tP_CXO,\n \tP_PLL14,\n \tP_PLL18,\n+\tP_PLL11,\n };\n \n static const struct parent_map gcc_pxo_pll8_map[] = {\n@@ -320,6 +339,42 @@ static const char * const gcc_pxo_pll8_p\n \t\"pll18\",\n };\n \n+static const struct parent_map gcc_pxo_pll8_pll0_pll14_pll18_pll11_map[] = {\n+\t{ P_PXO, 0 },\n+\t{ P_PLL8, 4 },\n+\t{ P_PLL0, 2 },\n+\t{ P_PLL14, 5 },\n+\t{ P_PLL18, 1 },\n+\t{ P_PLL11, 3 },\n+};\n+\n+static const char *gcc_pxo_pll8_pll0_pll14_pll18_pll11[] = {\n+\t\"pxo\",\n+\t\"pll8_vote\",\n+\t\"pll0_vote\",\n+\t\"pll14\",\n+\t\"pll18\",\n+\t\"pll11\"\n+};\n+\n+static const struct parent_map gcc_pxo_pll3_pll0_pll14_pll18_pll11_map[] = {\n+\t{ P_PXO, 0 },\n+\t{ P_PLL3, 6 },\n+\t{ P_PLL0, 2 },\n+\t{ P_PLL14, 5 },\n+\t{ P_PLL18, 1 },\n+\t{ P_PLL11, 3 },\n+};\n+\n+static const char *gcc_pxo_pll3_pll0_pll14_pll18_pll11[] = {\n+\t\"pxo\",\n+\t\"pll3\",\n+\t\"pll0_vote\",\n+\t\"pll14\",\n+\t\"pll18\",\n+\t\"pll11\"\n+};\n+\n static struct freq_tbl clk_tbl_gsbi_uart[] = {\n \t{  1843200, P_PLL8, 2,  6, 625 },\n \t{  3686400, P_PLL8, 2, 12, 625 },\n@@ -1261,6 +1316,7 @@ static const struct freq_tbl clk_tbl_sdc\n \t{  20210000, P_PLL8,  1, 1,  19 },\n \t{  24000000, P_PLL8,  4, 1,   4 },\n \t{  48000000, P_PLL8,  4, 1,   2 },\n+\t{  52000000, P_PLL8,  1, 2,  15 }, /* 51.2 Mhz */\n \t{  64000000, P_PLL8,  3, 1,   2 },\n \t{  96000000, P_PLL8,  4, 0,   0 },\n \t{ 192000000, P_PLL8,  2, 0,   0 },\n@@ -2645,7 +2701,9 @@ static const struct freq_tbl clk_tbl_nss\n \t{ 110000000, P_PLL18, 1, 1, 5 },\n \t{ 275000000, P_PLL18, 2, 0, 0 },\n \t{ 550000000, P_PLL18, 1, 0, 0 },\n+\t{ 600000000, P_PLL18, 1, 0, 0 },\n \t{ 733000000, P_PLL18, 1, 0, 0 },\n+\t{ 800000000, P_PLL18, 1, 0, 0 },\n \t{ }\n };\n \n@@ -2757,6 +2815,186 @@ static struct clk_dyn_rcg ubi32_core2_sr\n \t},\n };\n \n+static const struct freq_tbl clk_tbl_ce5_core[] = {\n+\t{ 150000000, P_PLL3, 8, 1, 1 },\n+\t{ 213200000, P_PLL11, 5, 1, 1 },\n+\t{ }\n+};\n+\n+static struct clk_dyn_rcg ce5_core_src = {\n+\t.ns_reg[0] = 0x36C4,\n+\t.ns_reg[1] = 0x36C8,\n+\t.bank_reg = 0x36C0,\n+\t.s[0] = {\n+\t\t.src_sel_shift = 0,\n+\t\t.parent_map = gcc_pxo_pll3_pll0_pll14_pll18_pll11_map,\n+\t},\n+\t.s[1] = {\n+\t\t.src_sel_shift = 0,\n+\t\t.parent_map = gcc_pxo_pll3_pll0_pll14_pll18_pll11_map,\n+\t},\n+\t.p[0] = {\n+\t\t.pre_div_shift = 3,\n+\t\t.pre_div_width = 4,\n+\t},\n+\t.p[1] = {\n+\t\t.pre_div_shift = 3,\n+\t\t.pre_div_width = 4,\n+\t},\n+\t.mux_sel_bit = 0,\n+\t.freq_tbl = clk_tbl_ce5_core,\n+\t.clkr = {\n+\t\t.enable_reg = 0x36C0,\n+\t\t.enable_mask = BIT(1),\n+\t\t.hw.init = &(struct clk_init_data){\n+\t\t\t.name = \"ce5_core_src\",\n+\t\t\t.parent_names = gcc_pxo_pll3_pll0_pll14_pll18_pll11,\n+\t\t\t.num_parents = 6,\n+\t\t\t.ops = &clk_dyn_rcg_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch ce5_core_clk = {\n+\t.halt_reg = 0x2FDC,\n+\t.halt_bit = 5,\n+\t.hwcg_reg = 0x36CC,\n+\t.hwcg_bit = 6,\n+\t.clkr = {\n+\t\t.enable_reg = 0x36CC,\n+\t\t.enable_mask = BIT(4),\n+\t\t.hw.init = &(struct clk_init_data){\n+\t\t\t.name = \"ce5_core_clk\",\n+\t\t\t.parent_names = (const char *[]){\n+\t\t\t\t\"ce5_core_src\",\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.ops = &clk_branch_ops,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t},\n+\t},\n+};\n+\n+static const struct freq_tbl clk_tbl_ce5_a_clk[] = {\n+\t{ 160000000, P_PLL0, 5, 1, 1 },\n+\t{ 213200000, P_PLL11, 5, 1, 1 },\n+\t{ }\n+};\n+\n+static struct clk_dyn_rcg ce5_a_clk_src = {\n+\t.ns_reg[0] = 0x3d84,\n+\t.ns_reg[1] = 0x3d88,\n+\t.bank_reg = 0x3d80,\n+\t.s[0] = {\n+\t\t.src_sel_shift = 0,\n+\t\t.parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map,\n+\t},\n+\t.s[1] = {\n+\t\t.src_sel_shift = 0,\n+\t\t.parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map,\n+\t},\n+\t.p[0] = {\n+\t\t.pre_div_shift = 3,\n+\t\t.pre_div_width = 4,\n+\t},\n+\t.p[1] = {\n+\t\t.pre_div_shift = 3,\n+\t\t.pre_div_width = 4,\n+\t},\n+\t.mux_sel_bit = 0,\n+\t.freq_tbl = clk_tbl_ce5_a_clk,\n+\t.clkr = {\n+\t\t.enable_reg = 0x3d80,\n+\t\t.enable_mask = BIT(1),\n+\t\t.hw.init = &(struct clk_init_data){\n+\t\t\t.name = \"ce5_a_clk_src\",\n+\t\t\t.parent_names = gcc_pxo_pll8_pll0_pll14_pll18_pll11,\n+\t\t\t.num_parents = 6,\n+\t\t\t.ops = &clk_dyn_rcg_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch ce5_a_clk = {\n+\t.halt_reg = 0x3c20,\n+\t.halt_bit = 12,\n+\t.hwcg_reg = 0x3d8c,\n+\t.hwcg_bit = 6,\n+\t.clkr = {\n+\t\t.enable_reg = 0x3d8c,\n+\t\t.enable_mask = BIT(4),\n+\t\t.hw.init = &(struct clk_init_data){\n+\t\t\t.name = \"ce5_a_clk\",\n+\t\t\t.parent_names = (const char *[]){\n+\t\t\t\t\"ce5_a_clk_src\",\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.ops = &clk_branch_ops,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t},\n+\t},\n+};\n+\n+static const struct freq_tbl clk_tbl_ce5_h_clk[] = {\n+\t{ 160000000, P_PLL0, 5, 1, 1 },\n+\t{ 213200000, P_PLL11, 5, 1, 1 },\n+\t{ }\n+};\n+\n+static struct clk_dyn_rcg ce5_h_clk_src = {\n+\t.ns_reg[0] = 0x3c64,\n+\t.ns_reg[1] = 0x3c68,\n+\t.bank_reg = 0x3c60,\n+\t.s[0] = {\n+\t\t.src_sel_shift = 0,\n+\t\t.parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map,\n+\t},\n+\t.s[1] = {\n+\t\t.src_sel_shift = 0,\n+\t\t.parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map,\n+\t},\n+\t.p[0] = {\n+\t\t.pre_div_shift = 3,\n+\t\t.pre_div_width = 4,\n+\t},\n+\t.p[1] = {\n+\t\t.pre_div_shift = 3,\n+\t\t.pre_div_width = 4,\n+\t},\n+\t.mux_sel_bit = 0,\n+\t.freq_tbl = clk_tbl_ce5_h_clk,\n+\t.clkr = {\n+\t\t.enable_reg = 0x3c60,\n+\t\t.enable_mask = BIT(1),\n+\t\t.hw.init = &(struct clk_init_data){\n+\t\t\t.name = \"ce5_h_clk_src\",\n+\t\t\t.parent_names = gcc_pxo_pll8_pll0_pll14_pll18_pll11,\n+\t\t\t.num_parents = 6,\n+\t\t\t.ops = &clk_dyn_rcg_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch ce5_h_clk = {\n+\t.halt_reg = 0x3c20,\n+\t.halt_bit = 11,\n+\t.hwcg_reg = 0x3c6c,\n+\t.hwcg_bit = 6,\n+\t.clkr = {\n+\t\t.enable_reg = 0x3c6c,\n+\t\t.enable_mask = BIT(4),\n+\t\t.hw.init = &(struct clk_init_data){\n+\t\t\t.name = \"ce5_h_clk\",\n+\t\t\t.parent_names = (const char *[]){\n+\t\t\t\t\"ce5_h_clk_src\",\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.ops = &clk_branch_ops,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t},\n+\t},\n+};\n+\n static struct clk_regmap *gcc_ipq806x_clks[] = {\n \t[PLL0] = &pll0.clkr,\n \t[PLL0_VOTE] = &pll0_vote,\n@@ -2764,6 +3002,7 @@ static struct clk_regmap *gcc_ipq806x_cl\n \t[PLL4_VOTE] = &pll4_vote,\n \t[PLL8] = &pll8.clkr,\n \t[PLL8_VOTE] = &pll8_vote,\n+\t[PLL11] = &pll11.clkr,\n \t[PLL14] = &pll14.clkr,\n \t[PLL14_VOTE] = &pll14_vote,\n \t[PLL18] = &pll18.clkr,\n@@ -2878,6 +3117,12 @@ static struct clk_regmap *gcc_ipq806x_cl\n \t[PLL9] = &hfpll0.clkr,\n \t[PLL10] = &hfpll1.clkr,\n \t[PLL12] = &hfpll_l2.clkr,\n+\t[CE5_A_CLK_SRC] = &ce5_a_clk_src.clkr,\n+\t[CE5_A_CLK] = &ce5_a_clk.clkr,\n+\t[CE5_H_CLK_SRC] = &ce5_h_clk_src.clkr,\n+\t[CE5_H_CLK] = &ce5_h_clk.clkr,\n+\t[CE5_CORE_CLK_SRC] = &ce5_core_src.clkr,\n+\t[CE5_CORE_CLK] = &ce5_core_clk.clkr,\n };\n \n static const struct qcom_reset_map gcc_ipq806x_resets[] = {\n@@ -3009,6 +3254,11 @@ static const struct qcom_reset_map gcc_i\n \t[GMAC_CORE3_RESET] = { 0x3cfc, 0 },\n \t[GMAC_CORE4_RESET] = { 0x3d1c, 0 },\n \t[GMAC_AHB_RESET] = { 0x3e24, 0 },\n+\t[CRYPTO_ENG1_RESET] = { 0x3e00, 0},\n+\t[CRYPTO_ENG2_RESET] = { 0x3e04, 0},\n+\t[CRYPTO_ENG3_RESET] = { 0x3e08, 0},\n+\t[CRYPTO_ENG4_RESET] = { 0x3e0c, 0},\n+\t[CRYPTO_AHB_RESET] = { 0x3e10, 0},\n \t[NSS_CH0_RST_RX_CLK_N_RESET] = { 0x3b60, 0 },\n \t[NSS_CH0_RST_TX_CLK_N_RESET] = { 0x3b60, 1 },\n \t[NSS_CH0_RST_RX_125M_N_RESET] = { 0x3b60, 2 },\n--- a/include/dt-bindings/clock/qcom,gcc-ipq806x.h\n+++ b/include/dt-bindings/clock/qcom,gcc-ipq806x.h\n@@ -240,7 +240,7 @@\n #define PLL14\t\t\t\t\t232\n #define PLL14_VOTE\t\t\t\t233\n #define PLL18\t\t\t\t\t234\n-#define CE5_SRC\t\t\t\t\t235\n+#define CE5_A_CLK\t\t\t\t235\n #define CE5_H_CLK\t\t\t\t236\n #define CE5_CORE_CLK\t\t\t\t237\n #define CE3_SLEEP_CLK\t\t\t\t238\n@@ -283,5 +283,8 @@\n #define EBI2_AON_CLK\t\t\t\t281\n #define NSSTCM_CLK_SRC\t\t\t\t282\n #define NSSTCM_CLK\t\t\t\t283\n+#define CE5_A_CLK_SRC\t\t\t\t285\n+#define CE5_H_CLK_SRC\t\t\t\t286\n+#define CE5_CORE_CLK_SRC\t\t\t287\n \n #endif\n--- a/include/dt-bindings/reset/qcom,gcc-ipq806x.h\n+++ b/include/dt-bindings/reset/qcom,gcc-ipq806x.h\n@@ -163,5 +163,10 @@\n #define NSS_CAL_PRBS_RST_N_RESET\t\t\t154\n #define NSS_LCKDT_RST_N_RESET\t\t\t\t155\n #define NSS_SRDS_N_RESET\t\t\t\t156\n+#define CRYPTO_ENG1_RESET\t\t\t\t157\n+#define CRYPTO_ENG2_RESET\t\t\t\t158\n+#define CRYPTO_ENG3_RESET\t\t\t\t159\n+#define CRYPTO_ENG4_RESET\t\t\t\t160\n+#define CRYPTO_AHB_RESET\t\t\t\t161\n \n #endif\n"
  },
  {
    "path": "target/linux/ipq806x/patches-5.15/098-1-cpufreq-add-Krait-dedicated-scaling-driver.patch",
    "content": "From cc41a266280cad0b55319e614167c88dff344248 Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Sat, 22 Feb 2020 16:33:10 +0100\nSubject: [PATCH 1/8] cpufreq: add Krait dedicated scaling driver\n\nThis new driver is based on generic cpufreq-dt driver.\nKrait SoCs have 2-4 cpu and one shared L2 cache that can\noperate at different frequency based on the maximum cpu clk\nacross all core.\nL2 frequency and voltage are scaled on every frequency change\nif needed. On Krait SoCs is present a bug that can cause\ntransition problem between frequency bin, to workaround this\non more than one transition, the L2 frequency is first set to the\nbase rate and then to the target rate.\nThe L2 frequency use the OPP framework and use the opp-level\nbindings to link the l2 freq to different cpu freq. This is needed\nas the Krait l2 clk are note mapped 1:1 to the core clks and some\nof the l2 clk is set based on a range of the cpu clks. If the driver\nfind a broken config (for example no opp-level set) the l2 scaling is\nskipped.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\n---\n drivers/cpufreq/Kconfig.arm          |  14 +-\n drivers/cpufreq/Makefile             |   2 +\n drivers/cpufreq/qcom-cpufreq-krait.c | 589 +++++++++++++++++++++++++++\n 3 files changed, 604 insertions(+), 1 deletion(-)\n create mode 100644 drivers/cpufreq/qcom-cpufreq-krait.c\n\n--- a/drivers/cpufreq/Kconfig.arm\n+++ b/drivers/cpufreq/Kconfig.arm\n@@ -172,6 +172,18 @@ config ARM_QCOM_CPUFREQ_HW\n \t  The driver implements the cpufreq interface for this HW engine.\n \t  Say Y if you want to support CPUFreq HW.\n \n+config ARM_QCOM_CPUFREQ_KRAIT\n+\ttristate \"CPU Frequency scaling support for Krait SoCs\"\n+\tdepends on ARCH_QCOM || COMPILE_TEST\n+\tselect PM_OPP\n+\tselect ARM_QCOM_CPUFREQ_NVMEM\n+\thelp\n+\t  This adds the CPUFreq driver for Qualcomm Krait SoC based boards.\n+\t  This scale the cache clk and regulator based on the different cpu\n+\t  clks when scaling the different cores clk.\n+\n+\t  If in doubt, say N.\n+\n config ARM_RASPBERRYPI_CPUFREQ\n \ttristate \"Raspberry Pi cpufreq support\"\n \tdepends on CLK_RASPBERRYPI || COMPILE_TEST\n@@ -356,4 +368,4 @@ config ARM_PXA2xx_CPUFREQ\n \thelp\n \t  This add the CPUFreq driver support for Intel PXA2xx SOCs.\n \n-\t  If in doubt, say N.\n+\t  If in doubt, say N.\n\\ No newline at end of file\n--- a/drivers/cpufreq/Makefile\n+++ b/drivers/cpufreq/Makefile\n@@ -63,6 +63,7 @@ obj-$(CONFIG_ARM_PXA2xx_CPUFREQ)\t+= pxa2\n obj-$(CONFIG_PXA3xx)\t\t\t+= pxa3xx-cpufreq.o\n obj-$(CONFIG_ARM_QCOM_CPUFREQ_HW)\t+= qcom-cpufreq-hw.o\n obj-$(CONFIG_ARM_QCOM_CPUFREQ_NVMEM)\t+= qcom-cpufreq-nvmem.o\n+obj-$(CONFIG_ARM_QCOM_CPUFREQ_KRAIT)\t+= qcom-cpufreq-krait.o\n obj-$(CONFIG_ARM_RASPBERRYPI_CPUFREQ) \t+= raspberrypi-cpufreq.o\n obj-$(CONFIG_ARM_S3C2410_CPUFREQ)\t+= s3c2410-cpufreq.o\n obj-$(CONFIG_ARM_S3C2412_CPUFREQ)\t+= s3c2412-cpufreq.o\n@@ -85,6 +86,7 @@ obj-$(CONFIG_ARM_TEGRA186_CPUFREQ)\t+= te\n obj-$(CONFIG_ARM_TEGRA194_CPUFREQ)\t+= tegra194-cpufreq.o\n obj-$(CONFIG_ARM_TI_CPUFREQ)\t\t+= ti-cpufreq.o\n obj-$(CONFIG_ARM_VEXPRESS_SPC_CPUFREQ)\t+= vexpress-spc-cpufreq.o\n+obj-$(CONFIG_ARM_KRAIT_CPUFREQ)\t\t+= krait-cpufreq.o\n \n \n ##################################################################################\n--- /dev/null\n+++ b/drivers/cpufreq/qcom-cpufreq-krait.c\n@@ -0,0 +1,629 @@\n+// SPDX-License-Identifier: GPL-2.0\n+\n+#define pr_fmt(fmt) KBUILD_MODNAME \": \" fmt\n+\n+#include <linux/clk.h>\n+#include <linux/cpu.h>\n+#include <linux/cpufreq.h>\n+#include <linux/cpumask.h>\n+#include <linux/err.h>\n+#include <linux/module.h>\n+#include <linux/of.h>\n+#include <linux/of_device.h>\n+#include <linux/pm_opp.h>\n+#include <linux/platform_device.h>\n+#include <linux/regulator/consumer.h>\n+#include <linux/slab.h>\n+#include <linux/thermal.h>\n+\n+#include \"cpufreq-dt.h\"\n+\n+static struct device *l2_dev;\n+static struct mutex lock;\n+\n+struct private_data {\n+\tstruct opp_table *opp_table;\n+\tstruct device *cpu_dev;\n+\tstruct device *l2_dev;\n+\tconst char *reg_name;\n+\tbool have_static_opps;\n+};\n+\n+static int set_target(struct cpufreq_policy *policy, unsigned int index)\n+{\n+\tstruct private_data *priv = policy->driver_data;\n+\tunsigned long freq = policy->freq_table[index].frequency;\n+\tunsigned long target_freq = freq * 1000;\n+\tstruct dev_pm_opp *opp;\n+\tunsigned int level;\n+\tint cpu, ret;\n+\n+\tif (l2_dev) {\n+\t\tint policy_cpu = policy->cpu;\n+\n+\t\tmutex_lock(&lock);\n+\n+\t\t/* find the max freq across all core */\n+\t\tfor_each_present_cpu(cpu)\n+\t\t\tif (cpu != policy_cpu)\n+\t\t\t\ttarget_freq = max(\n+\t\t\t\t\ttarget_freq,\n+\t\t\t\t\t(unsigned long)cpufreq_quick_get(cpu));\n+\n+\t\topp = dev_pm_opp_find_freq_exact(priv->cpu_dev, target_freq,\n+\t\t\t\t\t\t true);\n+\t\tif (IS_ERR(opp)) {\n+\t\t\tdev_err(l2_dev, \"failed to find OPP for %ld\\n\",\n+\t\t\t\ttarget_freq);\n+\t\t\tret = PTR_ERR(opp);\n+\t\t\tgoto l2_scale_fail;\n+\t\t}\n+\t\tlevel = dev_pm_opp_get_level(opp);\n+\t\tdev_pm_opp_put(opp);\n+\n+\t\t/*\n+\t\t * Hardware constraint:\n+\t\t * Krait CPU cannot operate at 384MHz with L2 at 1Ghz.\n+\t\t * Assume index 0 with the idle freq and level > 0 as \n+\t\t * any L2 freq > 384MHz.\n+\t\t * Skip CPU freq change in this corner case.\n+\t\t */\n+\t\tif (unlikely(index == 0 && level != 0)) {\n+\t\t\tdev_err(priv->cpu_dev, \"Krait CPU can't operate at idle freq with L2 at 1GHz\");\n+\t\t\tret = -EINVAL;\n+\t\t\tgoto l2_scale_fail;\n+\t\t}\n+\n+\t\topp = dev_pm_opp_find_level_exact(l2_dev, level);\n+\t\tif (IS_ERR(opp)) {\n+\t\t\tdev_err(l2_dev,\n+\t\t\t\t\"failed to find level OPP for %d\\n\", level);\n+\t\t\tret = PTR_ERR(opp);\n+\t\t\tgoto l2_scale_fail;\n+\t\t}\n+\t\ttarget_freq = dev_pm_opp_get_freq(opp);\n+\t\tdev_pm_opp_put(opp);\n+\n+\t\tret = dev_pm_opp_set_rate(l2_dev, target_freq);\n+\t\tif (ret)\n+\t\t\tgoto l2_scale_fail;\n+\n+\t\tmutex_unlock(&lock);\n+\t}\n+\n+\tret = dev_pm_opp_set_rate(priv->cpu_dev, freq * 1000);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tarch_set_freq_scale(policy->related_cpus, freq,\n+\t\t\t    policy->cpuinfo.max_freq);\n+\n+\treturn 0;\n+l2_scale_fail:\n+\tmutex_unlock(&lock);\n+\n+\treturn ret;\n+}\n+\n+/*\n+ * An earlier version of opp-v1 bindings used to name the regulator\n+ * \"cpu0-supply\", we still need to handle that for backwards compatibility.\n+ */\n+static const char *find_supply_name(struct device *dev)\n+{\n+\tstruct device_node *np;\n+\tstruct property *pp;\n+\tint cpu = dev->id;\n+\tconst char *name = NULL;\n+\n+\tnp = of_node_get(dev->of_node);\n+\n+\t/* This must be valid for sure */\n+\tif (WARN_ON(!np))\n+\t\treturn NULL;\n+\n+\t/* Try \"cpu0\" for older DTs */\n+\tif (!cpu) {\n+\t\tpp = of_find_property(np, \"cpu0-supply\", NULL);\n+\t\tif (pp) {\n+\t\t\tname = \"cpu0\";\n+\t\t\tgoto node_put;\n+\t\t}\n+\t}\n+\n+\tpp = of_find_property(np, \"cpu-supply\", NULL);\n+\tif (pp) {\n+\t\tname = \"cpu\";\n+\t\tgoto node_put;\n+\t}\n+\n+\tdev_dbg(dev, \"no regulator for cpu%d\\n\", cpu);\n+node_put:\n+\tof_node_put(np);\n+\treturn name;\n+}\n+\n+static int resources_available(void)\n+{\n+\tstruct device *cpu_dev;\n+\tstruct regulator *cpu_reg;\n+\tstruct clk *cpu_clk;\n+\tint ret = 0;\n+\tconst char *name;\n+\n+\tcpu_dev = get_cpu_device(0);\n+\tif (!cpu_dev) {\n+\t\tpr_err(\"failed to get cpu0 device\\n\");\n+\t\treturn -ENODEV;\n+\t}\n+\n+\tcpu_clk = clk_get(cpu_dev, NULL);\n+\tret = PTR_ERR_OR_ZERO(cpu_clk);\n+\tif (ret) {\n+\t\t/*\n+\t\t * If cpu's clk node is present, but clock is not yet\n+\t\t * registered, we should try defering probe.\n+\t\t */\n+\t\tif (ret == -EPROBE_DEFER)\n+\t\t\tdev_dbg(cpu_dev, \"clock not ready, retry\\n\");\n+\t\telse\n+\t\t\tdev_err(cpu_dev, \"failed to get clock: %d\\n\", ret);\n+\n+\t\treturn ret;\n+\t}\n+\n+\tclk_put(cpu_clk);\n+\n+\tname = find_supply_name(cpu_dev);\n+\t/* Platform doesn't require regulator */\n+\tif (!name)\n+\t\treturn 0;\n+\n+\tcpu_reg = regulator_get_optional(cpu_dev, name);\n+\tret = PTR_ERR_OR_ZERO(cpu_reg);\n+\tif (ret) {\n+\t\t/*\n+\t\t * If cpu's regulator supply node is present, but regulator is\n+\t\t * not yet registered, we should try defering probe.\n+\t\t */\n+\t\tif (ret == -EPROBE_DEFER)\n+\t\t\tdev_dbg(cpu_dev, \"cpu0 regulator not ready, retry\\n\");\n+\t\telse\n+\t\t\tdev_dbg(cpu_dev, \"no regulator for cpu0: %d\\n\", ret);\n+\n+\t\treturn ret;\n+\t}\n+\n+\tregulator_put(cpu_reg);\n+\treturn 0;\n+}\n+\n+static int cpufreq_init(struct cpufreq_policy *policy)\n+{\n+\tstruct cpufreq_frequency_table *freq_table;\n+\tstruct opp_table *opp_table = NULL;\n+\tunsigned int transition_latency;\n+\tstruct private_data *priv;\n+\tstruct device *cpu_dev;\n+\tbool fallback = false;\n+\tstruct clk *cpu_clk;\n+\tconst char *name;\n+\tint ret;\n+\n+\tcpu_dev = get_cpu_device(policy->cpu);\n+\tif (!cpu_dev) {\n+\t\tpr_err(\"failed to get cpu%d device\\n\", policy->cpu);\n+\t\treturn -ENODEV;\n+\t}\n+\n+\tcpu_clk = clk_get(cpu_dev, NULL);\n+\tif (IS_ERR(cpu_clk)) {\n+\t\tret = PTR_ERR(cpu_clk);\n+\t\tdev_err(cpu_dev, \"%s: failed to get clk: %d\\n\", __func__, ret);\n+\t\treturn ret;\n+\t}\n+\n+\t/* Get OPP-sharing information from \"operating-points-v2\" bindings */\n+\tret = dev_pm_opp_of_get_sharing_cpus(cpu_dev, policy->cpus);\n+\tif (ret) {\n+\t\tif (ret != -ENOENT)\n+\t\t\tgoto out_put_clk;\n+\n+\t\t/*\n+\t\t * operating-points-v2 not supported, fallback to old method of\n+\t\t * finding shared-OPPs for backward compatibility if the\n+\t\t * platform hasn't set sharing CPUs.\n+\t\t */\n+\t\tif (dev_pm_opp_get_sharing_cpus(cpu_dev, policy->cpus))\n+\t\t\tfallback = true;\n+\t}\n+\n+\t/*\n+\t * OPP layer will be taking care of regulators now, but it needs to know\n+\t * the name of the regulator first.\n+\t */\n+\tname = find_supply_name(cpu_dev);\n+\tif (name) {\n+\t\topp_table = dev_pm_opp_set_regulators(cpu_dev, &name, 1);\n+\t\tif (IS_ERR(opp_table)) {\n+\t\t\tret = PTR_ERR(opp_table);\n+\t\t\tdev_err(cpu_dev,\n+\t\t\t\t\"Failed to set regulator for cpu%d: %d\\n\",\n+\t\t\t\tpolicy->cpu, ret);\n+\t\t\tgoto out_put_clk;\n+\t\t}\n+\t}\n+\n+\tpriv = kzalloc(sizeof(*priv), GFP_KERNEL);\n+\tif (!priv) {\n+\t\tret = -ENOMEM;\n+\t\tgoto out_put_regulator;\n+\t}\n+\n+\tpriv->reg_name = name;\n+\tpriv->opp_table = opp_table;\n+\n+\t/*\n+\t * Initialize OPP tables for all policy->cpus. They will be shared by\n+\t * all CPUs which have marked their CPUs shared with OPP bindings.\n+\t *\n+\t * For platforms not using operating-points-v2 bindings, we do this\n+\t * before updating policy->cpus. Otherwise, we will end up creating\n+\t * duplicate OPPs for policy->cpus.\n+\t *\n+\t * OPPs might be populated at runtime, don't check for error here\n+\t */\n+\tif (!dev_pm_opp_of_cpumask_add_table(policy->cpus))\n+\t\tpriv->have_static_opps = true;\n+\n+\t/*\n+\t * But we need OPP table to function so if it is not there let's\n+\t * give platform code chance to provide it for us.\n+\t */\n+\tret = dev_pm_opp_get_opp_count(cpu_dev);\n+\tif (ret < 0) {\n+\t\tdev_dbg(cpu_dev, \"OPP table is not ready, deferring probe\\n\");\n+\t\tret = -EPROBE_DEFER;\n+\t\tgoto out_free_opp;\n+\t}\n+\n+\tif (fallback) {\n+\t\tcpumask_setall(policy->cpus);\n+\n+\t\t/*\n+\t\t * OPP tables are initialized only for policy->cpu, do it for\n+\t\t * others as well.\n+\t\t */\n+\t\tret = dev_pm_opp_set_sharing_cpus(cpu_dev, policy->cpus);\n+\t\tif (ret)\n+\t\t\tdev_err(cpu_dev,\n+\t\t\t\t\"%s: failed to mark OPPs as shared: %d\\n\",\n+\t\t\t\t__func__, ret);\n+\t}\n+\n+\tret = dev_pm_opp_init_cpufreq_table(cpu_dev, &freq_table);\n+\tif (ret) {\n+\t\tdev_err(cpu_dev, \"failed to init cpufreq table: %d\\n\", ret);\n+\t\tgoto out_free_opp;\n+\t}\n+\n+\tpriv->cpu_dev = cpu_dev;\n+\n+\tpolicy->driver_data = priv;\n+\tpolicy->clk = cpu_clk;\n+\tpolicy->freq_table = freq_table;\n+\n+\tpolicy->suspend_freq = dev_pm_opp_get_suspend_opp_freq(cpu_dev) / 1000;\n+\n+\ttransition_latency = dev_pm_opp_get_max_transition_latency(cpu_dev);\n+\tif (!transition_latency)\n+\t\ttransition_latency = CPUFREQ_ETERNAL;\n+\n+\tpolicy->cpuinfo.transition_latency = transition_latency;\n+\tpolicy->dvfs_possible_from_any_cpu = true;\n+\n+\tdev_pm_opp_of_register_em(cpu_dev, policy->cpus);\n+\n+\treturn 0;\n+\n+out_free_opp:\n+\tif (priv->have_static_opps)\n+\t\tdev_pm_opp_of_cpumask_remove_table(policy->cpus);\n+\tkfree(priv);\n+out_put_regulator:\n+\tif (name)\n+\t\tdev_pm_opp_put_regulators(opp_table);\n+out_put_clk:\n+\tclk_put(cpu_clk);\n+\n+\treturn ret;\n+}\n+\n+static int cpufreq_online(struct cpufreq_policy *policy)\n+{\n+\t/* We did light-weight tear down earlier, nothing to do here */\n+\treturn 0;\n+}\n+\n+static int cpufreq_offline(struct cpufreq_policy *policy)\n+{\n+\t/*\n+\t * Preserve policy->driver_data and don't free resources on light-weight\n+\t * tear down.\n+\t */\n+\treturn 0;\n+}\n+\n+static int cpufreq_exit(struct cpufreq_policy *policy)\n+{\n+\tstruct private_data *priv = policy->driver_data;\n+\n+\tdev_pm_opp_free_cpufreq_table(priv->cpu_dev, &policy->freq_table);\n+\tif (priv->have_static_opps)\n+\t\tdev_pm_opp_of_cpumask_remove_table(policy->related_cpus);\n+\tif (priv->reg_name)\n+\t\tdev_pm_opp_put_regulators(priv->opp_table);\n+\n+\tclk_put(policy->clk);\n+\tkfree(priv);\n+\n+\treturn 0;\n+}\n+\n+static struct cpufreq_driver krait_cpufreq_driver = {\n+\t.flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK |\n+\t\t CPUFREQ_IS_COOLING_DEV,\n+\t.verify = cpufreq_generic_frequency_table_verify,\n+\t.target_index = set_target,\n+\t.get = cpufreq_generic_get,\n+\t.init = cpufreq_init,\n+\t.exit = cpufreq_exit,\n+\t.online = cpufreq_online,\n+\t.offline = cpufreq_offline,\n+\t.name = \"krait-cpufreq\",\n+\t.suspend = cpufreq_generic_suspend,\n+};\n+\n+struct krait_data {\n+\tunsigned long idle_freq;\n+\tbool regulator_enabled;\n+};\n+\n+static int krait_cache_set_opp(struct dev_pm_set_opp_data *data)\n+{\n+\tunsigned long old_freq = data->old_opp.rate, freq = data->new_opp.rate;\n+\tstruct dev_pm_opp_supply *supply = &data->new_opp.supplies[0];\n+\tstruct regulator *reg = data->regulators[0];\n+\tstruct clk *clk = data->clk;\n+\tstruct krait_data *kdata;\n+\tunsigned long idle_freq;\n+\tint ret;\n+\n+\tkdata = (struct krait_data *)dev_get_drvdata(data->dev);\n+\tidle_freq = kdata->idle_freq;\n+\n+\t/* Scaling up? Scale voltage before frequency */\n+\tif (freq >= old_freq) {\n+\t\tret = regulator_set_voltage_triplet(reg, supply->u_volt_min,\n+\t\t\t\t\t\t    supply->u_volt,\n+\t\t\t\t\t\t    supply->u_volt_max);\n+\t\tif (ret)\n+\t\t\tgoto exit;\n+\t}\n+\n+\t/*\n+\t * Set to idle bin if switching from normal to high bin\n+\t * or vice versa. It has been notice that a bug is triggered\n+\t * in cache scaling when more than one bin is scaled, to fix\n+\t * this we first need to transition to the base rate and then\n+\t * to target rate\n+\t */\n+\tif (likely(freq != idle_freq && old_freq != idle_freq)) {\n+\t\tret = clk_set_rate(clk, idle_freq);\n+\t\tif (ret)\n+\t\t\tgoto exit;\n+\t}\n+\n+\tret = clk_set_rate(clk, freq);\n+\tif (ret)\n+\t\tgoto exit;\n+\n+\t/* Scaling down? Scale voltage after frequency */\n+\tif (freq < old_freq) {\n+\t\tret = regulator_set_voltage_triplet(reg, supply->u_volt_min,\n+\t\t\t\t\t\t    supply->u_volt,\n+\t\t\t\t\t\t    supply->u_volt_max);\n+\t}\n+\n+\tif (unlikely(!kdata->regulator_enabled)) {\n+\t\tret = regulator_enable(reg);\n+\t\tif (ret < 0)\n+\t\t\tdev_warn(data->dev, \"Failed to enable regulator: %d\", ret);\n+\t\telse\n+\t\t\tkdata->regulator_enabled = true;\n+\t}\n+\n+exit:\n+\treturn ret;\n+};\n+\n+static int krait_cache_probe(struct platform_device *pdev)\n+{\n+\tstruct device *dev = &pdev->dev;\n+\tstruct krait_data *data;\n+\tstruct opp_table *table;\n+\tstruct dev_pm_opp *opp;\n+\tstruct device *cpu_dev;\n+\tint ret;\n+\n+\tdata = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);\n+\tif (!data)\n+\t\treturn -ENOMEM;\n+\n+\ttable = dev_pm_opp_set_regulators(dev, (const char *[]){ \"l2\" }, 1);\n+\tif (IS_ERR(table)) {\n+\t\tret = PTR_ERR(table);\n+\t\tif (ret != -EPROBE_DEFER)\n+\t\t\tdev_err(dev, \"failed to set regulators %d\\n\", ret);\n+\n+\t\treturn ret;\n+\t}\n+\n+\tret = PTR_ERR_OR_ZERO(\n+\t\tdev_pm_opp_register_set_opp_helper(dev, krait_cache_set_opp));\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = dev_pm_opp_of_add_table(dev);\n+\tif (ret) {\n+\t\tdev_err(dev, \"failed to parse L2 freq thresholds\\n\");\n+\t\treturn ret;\n+\t}\n+\n+\topp = dev_pm_opp_find_freq_ceil(dev, &data->idle_freq);\n+\tdev_pm_opp_put(opp);\n+\n+\t/*\n+\t * Check if we have at least opp-level 1, 0 should always be set to\n+\t * the idle freq\n+\t */\n+\topp = dev_pm_opp_find_level_exact(dev, 1);\n+\tif (IS_ERR(opp)) {\n+\t\tret = PTR_ERR(opp);\n+\t\tdev_err(dev,\n+\t\t\t\"Invalid configuration found of l2 opp. Can't find opp-level 1\");\n+\t\tgoto invalid_conf;\n+\t}\n+\tdev_pm_opp_put(opp);\n+\n+\t/*\n+\t * Check opp-level configuration\n+\t * At least 2 level must be set or the cache will always be scaled\n+\t * the idle freq causing some performance problem\n+\t *\n+\t * In case of invalid configuration, the l2 scaling is skipped\n+\t */\n+\tcpu_dev = get_cpu_device(0);\n+\tif (!cpu_dev) {\n+\t\tpr_err(\"failed to get cpu0 device\\n\");\n+\t\treturn -ENODEV;\n+\t}\n+\n+\t/* With opp error assume cpufreq still has to be registred. Defer probe. */\n+\tret = dev_pm_opp_get_opp_count(cpu_dev);\n+\tif (ret < 0) {\n+\t\tret = -EPROBE_DEFER;\n+\t\tgoto invalid_conf;\n+\t}\n+\n+\t/*\n+\t * Check if we have at least opp-level 1 in the cpu opp, 0 should always\n+\t * be set to the idle freq\n+\t */\n+\topp = dev_pm_opp_find_level_exact(cpu_dev, 1);\n+\tif (IS_ERR(opp)) {\n+\t\tret = PTR_ERR(opp);\n+\t\tif (ret != -EPROBE_DEFER)\n+\t\t\tdev_err(dev,\n+\t\t\t\t\"Invalid configuration found of cpu opp. Can't find opp-level 1\");\n+\t\tgoto invalid_conf;\n+\t}\n+\tdev_pm_opp_put(opp);\n+\n+\tplatform_set_drvdata(pdev, data);\n+\n+\tmutex_init(&lock);\n+\n+\t/* The l2 scaling is enabled by linking the cpufreq driver */\n+\tl2_dev = dev;\n+\n+\treturn 0;\n+\n+invalid_conf:\n+\tdev_pm_opp_remove_table(dev);\n+\tdev_pm_opp_put_regulators(table);\n+\tdev_pm_opp_unregister_set_opp_helper(table);\n+\n+\treturn ret;\n+};\n+\n+static int krait_cache_remove(struct platform_device *pdev)\n+{\n+\tstruct device *dev = &pdev->dev;\n+\tstruct opp_table *table = dev_pm_opp_get_opp_table(dev);\n+\n+\tdev_pm_opp_remove_table(dev);\n+\tdev_pm_opp_put_regulators(table);\n+\tdev_pm_opp_unregister_set_opp_helper(table);\n+\n+\treturn 0;\n+};\n+\n+static const struct of_device_id krait_cache_match_table[] = {\n+\t{ .compatible = \"qcom,krait-cache\" },\n+\t{}\n+};\n+\n+static struct platform_driver krait_cache_driver = {\n+\t.driver = {\n+\t\t.name\t= \"krait-cache\",\n+\t\t.of_match_table = krait_cache_match_table,\n+\t},\n+\t.probe\t\t= krait_cache_probe,\n+\t.remove\t\t= krait_cache_remove,\n+};\n+module_platform_driver(krait_cache_driver);\n+\n+static int krait_cpufreq_probe(struct platform_device *pdev)\n+{\n+\tstruct cpufreq_dt_platform_data *data = dev_get_platdata(&pdev->dev);\n+\tint ret;\n+\n+\t/*\n+\t * All per-cluster (CPUs sharing clock/voltages) initialization is done\n+\t * from ->init(). In probe(), we just need to make sure that clk and\n+\t * regulators are available. Else defer probe and retry.\n+\t *\n+\t * FIXME: Is checking this only for CPU0 sufficient ?\n+\t */\n+\tret = resources_available();\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tif (data) {\n+\t\tif (data->have_governor_per_policy)\n+\t\t\tkrait_cpufreq_driver.flags |=\n+\t\t\t\tCPUFREQ_HAVE_GOVERNOR_PER_POLICY;\n+\n+\t\tkrait_cpufreq_driver.resume = data->resume;\n+\t\tif (data->suspend)\n+\t\t\tkrait_cpufreq_driver.suspend = data->suspend;\n+\t}\n+\n+\tret = cpufreq_register_driver(&krait_cpufreq_driver);\n+\tif (ret)\n+\t\tdev_err(&pdev->dev, \"failed register driver: %d\\n\", ret);\n+\n+\treturn ret;\n+}\n+\n+static int krait_cpufreq_remove(struct platform_device *pdev)\n+{\n+\tcpufreq_unregister_driver(&krait_cpufreq_driver);\n+\treturn 0;\n+}\n+\n+static struct platform_driver krait_cpufreq_platdrv = {\n+\t.driver = {\n+\t\t.name\t= \"krait-cpufreq\",\n+\t},\n+\t.probe\t\t= krait_cpufreq_probe,\n+\t.remove\t\t= krait_cpufreq_remove,\n+};\n+\n+module_platform_driver(krait_cpufreq_platdrv);\n+\n+MODULE_ALIAS(\"platform:krait-cpufreq\");\n+MODULE_AUTHOR(\"Ansuel Smith <ansuelsmth@gmail.com>\");\n+MODULE_DESCRIPTION(\"Dedicated Krait SoC cpufreq driver\");\n+MODULE_LICENSE(\"GPL\");\n"
  },
  {
    "path": "target/linux/ipq806x/patches-5.15/098-2-Documentation-cpufreq-add-qcom-krait-cpufreq-binding.patch",
    "content": "From c9ecd920324a647bf1f2b47f771c8f599cc7b551 Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Sat, 22 Feb 2020 18:02:17 +0100\nSubject: [PATCH 2/8] Documentation: cpufreq: add qcom,krait-cache bindings\n\nDocument dedicated cpufreq for Krait CPUs.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\n---\n .../bindings/cpufreq/qcom-cpufreq-krait.yaml  | 221 ++++++++++++++++++\n 1 file changed, 221 insertions(+)\n create mode 100644 Documentation/devicetree/bindings/cpufreq/qcom-cpufreq-krait.yaml\n\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/cpufreq/qcom-cpufreq-krait.yaml\n@@ -0,0 +1,221 @@\n+# SPDX-License-Identifier: GPL-2.0\n+%YAML 1.2\n+---\n+$id: http://devicetree.org/schemas/cpufreq/qcom-cpufreq-krait.yaml#\n+$schema: http://devicetree.org/meta-schemas/core.yaml#\n+\n+title: CPU Frequency scaling driver for Krait SoCs\n+\n+maintainers:\n+  - Ansuel Smith <ansuelsmth@gmail.com>\n+\n+description: |\n+  The krait cpufreq driver is a dedicated frequency scaling driver\n+  based on cpufreq-dt generic driver that scale L2 cache and the\n+  cores. TEST\n+\n+  The L2 cache is scaled based on the max clk across all cores and\n+  the clock is decided based on the opp-level set in the device tree.\n+\n+  Different core freq can be linked to a specific l2 freq and the driver\n+  on frequency change will scale the core and the l2 clk based of the \n+  linked freq.\n+\n+  On Krait SoC is present a bug and on every L2 clk change the driver\n+  needs to set the clk to the idle freq before changing it to the new value.\n+\n+  This requires the qcom cpufreq nvmem driver to parse the different opp\n+  core clk and an additional opp table for the l2 scaling.\n+\n+  If the driver detect broken config (for example missing opp-level) the\n+  cpufreq driver skips the l2 scaling\n+\n+  Referring to this example opp-level can be used to link a range of cpu freq\n+  to a specific l2 freq:\n+    cpu opp freq 384000000 has opp-level 0\n+    l2 opp freq 384000000 has opp-level 0\n+    The driver will scale l2 to 384000000\n+\n+    cpu opp freq 600000000-1000000000 has opp-level 1\n+    l2 opp freq 1000000000 has opp-level 1\n+    The driver will scale l2 to 1000000000\n+\n+allOf:\n+  - $ref: /schemas/cache-controller.yaml#\n+\n+select:\n+  properties:\n+    compatible:\n+      items:\n+        - enum:\n+            - qcom,krait-cache\n+\n+  required:\n+    - compatible\n+\n+properties:\n+  compatible:\n+    items:\n+      - const: qcom,krait-cache\n+      - const: cache\n+\n+  cache-level:\n+    const: 2\n+\n+  clocks:\n+    maxItems: 1\n+\n+  clock-names:\n+    const: l2\n+\n+  l2-supply: true\n+\n+  operating-points-v2: true\n+\n+required:\n+  - compatible\n+  - cache-level\n+  - clocks\n+  - clock-names\n+  - l2-supply\n+  - operating-points-v2\n+\n+additionalProperties: false\n+\n+examples:\n+  - |\n+    cpus {\n+      #address-cells = <1>;\n+      #size-cells = <0>;\n+\n+      cpu0: cpu@0 {\n+        compatible = \"qcom,krait\";\n+        enable-method = \"qcom,kpss-acc-v1\";\n+        device_type = \"cpu\";\n+        reg = <0>;\n+        next-level-cache = <&L2>;\n+        qcom,acc = <&acc0>;\n+        qcom,saw = <&saw0>;\n+        clocks = <&kraitcc 0>, <&kraitcc 4>;\n+        clock-names = \"cpu\", \"l2\";\n+        clock-latency = <100000>;\n+        cpu-supply = <&smb208_s2a>;\n+        operating-points-v2 = <&opp_table0>;\n+        voltage-tolerance = <5>;\n+        cooling-min-state = <0>;\n+        cooling-max-state = <10>;\n+        #cooling-cells = <2>;\n+        cpu-idle-states = <&CPU_SPC>;\n+      };\n+\n+      /* ... */\n+\n+    };\n+\n+    opp_table0: opp_table0 {\n+      compatible = \"operating-points-v2-kryo-cpu\";\n+      nvmem-cells = <&speedbin_efuse>;\n+\n+      opp-384000000 {\n+        opp-hz = /bits/ 64 <384000000>;\n+        opp-microvolt-speed0-pvs0-v0 = <1000000>;\n+        opp-microvolt-speed0-pvs1-v0 = <925000>;\n+        opp-microvolt-speed0-pvs2-v0 = <875000>;\n+        opp-microvolt-speed0-pvs3-v0 = <800000>;\n+        opp-supported-hw = <0x1>;\n+        clock-latency-ns = <100000>;\n+        opp-level = <0>;\n+      };\n+\n+      opp-600000000 {\n+        opp-hz = /bits/ 64 <600000000>;\n+        opp-microvolt-speed0-pvs0-v0 = <1050000>;\n+        opp-microvolt-speed0-pvs1-v0 = <975000>;\n+        opp-microvolt-speed0-pvs2-v0 = <925000>;\n+        opp-microvolt-speed0-pvs3-v0 = <850000>;\n+        opp-supported-hw = <0x1>;\n+        clock-latency-ns = <100000>;\n+        opp-level = <1>;\n+      };\n+\n+      opp-800000000 {\n+        opp-hz = /bits/ 64 <800000000>;\n+        opp-microvolt-speed0-pvs0-v0 = <1100000>;\n+        opp-microvolt-speed0-pvs1-v0 = <1025000>;\n+        opp-microvolt-speed0-pvs2-v0 = <995000>;\n+        opp-microvolt-speed0-pvs3-v0 = <900000>;\n+        opp-supported-hw = <0x1>;\n+        clock-latency-ns = <100000>;\n+        opp-level = <1>;\n+      };\n+\n+      opp-1000000000 {\n+        opp-hz = /bits/ 64 <1000000000>;\n+        opp-microvolt-speed0-pvs0-v0 = <1150000>;\n+        opp-microvolt-speed0-pvs1-v0 = <1075000>;\n+        opp-microvolt-speed0-pvs2-v0 = <1025000>;\n+        opp-microvolt-speed0-pvs3-v0 = <950000>;\n+        opp-supported-hw = <0x1>;\n+        clock-latency-ns = <100000>;\n+        opp-level = <1>;\n+      };\n+\n+      opp-1200000000 {\n+        opp-hz = /bits/ 64 <1200000000>;\n+        opp-microvolt-speed0-pvs0-v0 = <1200000>;\n+        opp-microvolt-speed0-pvs1-v0 = <1125000>;\n+        opp-microvolt-speed0-pvs2-v0 = <1075000>;\n+        opp-microvolt-speed0-pvs3-v0 = <1000000>;\n+        opp-supported-hw = <0x1>;\n+        clock-latency-ns = <100000>;\n+        opp-level = <2>;\n+      };\n+\n+      opp-1400000000 {\n+        opp-hz = /bits/ 64 <1400000000>;\n+        opp-microvolt-speed0-pvs0-v0 = <1250000>;\n+        opp-microvolt-speed0-pvs1-v0 = <1175000>;\n+        opp-microvolt-speed0-pvs2-v0 = <1125000>;\n+        opp-microvolt-speed0-pvs3-v0 = <1050000>;\n+        opp-supported-hw = <0x1>;\n+        clock-latency-ns = <100000>;\n+        opp-level = <2>;\n+      };\n+    };\n+\n+    opp_table_l2: opp_table_l2 {\n+      compatible = \"operating-points-v2\";\n+\n+      opp-384000000 {\n+        opp-hz = /bits/ 64 <384000000>;\n+        opp-microvolt = <1100000>;\n+        clock-latency-ns = <100000>;\n+        opp-level = <0>;\n+      };\n+      opp-1000000000 {\n+        opp-hz = /bits/ 64 <1000000000>;\n+        opp-microvolt = <1100000>;\n+        clock-latency-ns = <100000>;\n+        opp-level = <1>;\n+      };\n+      opp-1200000000 {\n+        opp-hz = /bits/ 64 <1200000000>;\n+        opp-microvolt = <1150000>;\n+        clock-latency-ns = <100000>;\n+        opp-level = <2>;\n+      };\n+    };\n+\n+    soc {\n+      L2: l2-cache {\n+        compatible = \"qcom,krait-cache\", \"cache\";\n+        cache-level = <2>;\n+\n+        clocks = <&kraitcc 4>;\n+        clock-names = \"l2\";\n+        l2-supply = <&smb208_s1a>;\n+        operating-points-v2 = <&opp_table_l2>;\n+      };\n+    };\n+\n+...\n"
  },
  {
    "path": "target/linux/ipq806x/patches-5.15/098-3-add-fab-scaling-support-with-cpufreq.patch",
    "content": "--- a/drivers/clk/qcom/Makefile\n+++ b/drivers/clk/qcom/Makefile\n@@ -15,6 +15,7 @@ clk-qcom-$(CONFIG_KRAIT_CLOCKS) += clk-k\n clk-qcom-y += clk-hfpll.o\n clk-qcom-y += reset.o\n clk-qcom-$(CONFIG_QCOM_GDSC) += gdsc.o\n+clk-qcom-y += fab_scaling.o\n \n # Keep alphabetically sorted by config\n obj-$(CONFIG_APQ_GCC_8084) += gcc-apq8084.o\n--- /dev/null\n+++ b/drivers/clk/qcom/fab_scaling.c\n@@ -0,0 +1,172 @@\n+/*\n+ * Copyright (c) 2015, The Linux Foundation. All rights reserved.\n+ *\n+ * Permission to use, copy, modify, and/or distribute this software for any\n+ * purpose with or without fee is hereby granted, provided that the above\n+ * copyright notice and this permission notice appear in all copies.\n+ *\n+ * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n+ */\n+\n+#include <linux/kernel.h>\n+#include <linux/init.h>\n+#include <linux/module.h>\n+#include <linux/platform_device.h>\n+#include <linux/err.h>\n+#include <linux/io.h>\n+#include <linux/of.h>\n+#include <linux/of_device.h>\n+#include <linux/clk.h>\n+#include <linux/clk-provider.h>\n+#include <linux/slab.h>\n+#include <linux/fab_scaling.h>\n+\n+struct qcom_fab_scaling_data {\n+\tu32 fab_freq_high;\n+\tu32 fab_freq_nominal;\n+\tu32 cpu_freq_threshold;\n+\tstruct clk *apps_fab_clk;\n+\tstruct clk *ddr_fab_clk;\n+};\n+\n+static struct qcom_fab_scaling_data *drv_data;\n+\n+int scale_fabrics(unsigned long max_cpu_freq)\n+{\t\n+\tstruct clk *apps_fab_clk = drv_data->apps_fab_clk,\n+\t           *ddr_fab_clk = drv_data->ddr_fab_clk;\n+\tunsigned long target_freq, cur_freq;\n+\tint ret;\n+\n+\t/* Skip fab scaling if the driver is not ready */\n+\tif (!apps_fab_clk || !ddr_fab_clk)\n+\t\treturn 0;\n+\n+\tif (max_cpu_freq > drv_data->cpu_freq_threshold)\n+\t\ttarget_freq = drv_data->fab_freq_high;\n+\telse\n+\t\ttarget_freq = drv_data->fab_freq_nominal;\n+\n+\tcur_freq = clk_get_rate(ddr_fab_clk);\n+\n+\tif (target_freq != cur_freq) {\n+\t\tret = clk_set_rate(apps_fab_clk, target_freq);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\t\tret = clk_set_rate(ddr_fab_clk, target_freq);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\t}\n+\n+\treturn 0;\n+}\n+EXPORT_SYMBOL(scale_fabrics);\n+\n+static int ipq806x_fab_scaling_probe(struct platform_device *pdev)\n+{\n+\tstruct device_node *np = pdev->dev.of_node;\n+\tstruct clk *apps_fab_clk, *ddr_fab_clk;\n+\tint ret;\n+\n+\tif (!np)\n+\t\treturn -ENODEV;\n+\t\n+\tdrv_data = kzalloc(sizeof(*drv_data), GFP_KERNEL);\n+\tif (!drv_data)\n+\t\treturn -ENOMEM;\n+\n+\tif (of_property_read_u32(np, \"fab_freq_high\", &drv_data->fab_freq_high)) {\n+\t\tpr_err(\"FABRICS turbo freq not found. Using defaults...\\n\");\n+\t\tdrv_data->fab_freq_high = 533000000;\n+\t}\n+\n+\tif (of_property_read_u32(np, \"fab_freq_nominal\", &drv_data->fab_freq_nominal)) {\n+\t\tpr_err(\"FABRICS nominal freq not found. Using defaults...\\n\");\n+\t\tdrv_data->fab_freq_nominal = 400000000;\n+\t}\n+\n+\tif (of_property_read_u32(np, \"cpu_freq_threshold\", &drv_data->cpu_freq_threshold)) {\n+\t\tpr_err(\"FABRICS cpu freq threshold not found. Using defaults...\\n\");\n+\t\tdrv_data->cpu_freq_threshold = 1000000000;\n+\t}\n+\n+\tapps_fab_clk = devm_clk_get(&pdev->dev, \"apps-fab-clk\");\n+\tret = PTR_ERR_OR_ZERO(apps_fab_clk);\n+\tif (ret) {\n+\t\t/*\n+\t\t * If apps fab clk node is present, but clock is not yet\n+\t\t * registered, we should try defering probe.\n+\t\t */\n+\t\tif (ret != -EPROBE_DEFER) {\n+\t\t\tpr_err(\"Failed to get APPS FABRIC clock: %d\\n\", ret);\n+\t\t\tret = -ENODEV;\n+\t\t}\n+\t\tgoto err;\n+\t}\n+\n+\tclk_prepare_enable(apps_fab_clk);\n+\tclk_set_rate(apps_fab_clk, drv_data->fab_freq_high);\n+\tdrv_data->apps_fab_clk = apps_fab_clk;\n+\n+\tddr_fab_clk = devm_clk_get(&pdev->dev, \"ddr-fab-clk\");\n+\tret = PTR_ERR_OR_ZERO(ddr_fab_clk);\n+\tif (ret) {\n+\t\t/*\n+\t\t * If ddr fab clk node is present, but clock is not yet\n+\t\t * registered, we should try defering probe.\n+\t\t */\n+\t\tif (ret != -EPROBE_DEFER) {\n+\t\t\tpr_err(\"Failed to get DDR FABRIC clock: %d\\n\", ret);\n+\t\t\tddr_fab_clk = NULL;\n+\t\t\tret = -ENODEV;\n+\t\t}\n+\t\tgoto err;\n+\t}\n+\n+\tclk_prepare_enable(ddr_fab_clk);\n+\tclk_set_rate(ddr_fab_clk, drv_data->fab_freq_high);\n+\tdrv_data->ddr_fab_clk = ddr_fab_clk;\n+\n+\treturn 0;\n+err:\n+\tkfree(drv_data);\n+\treturn ret;\n+}\n+\n+static int ipq806x_fab_scaling_remove(struct platform_device *pdev)\n+{\n+\tkfree(drv_data);\n+\treturn 0;\n+}\n+\n+static const struct of_device_id fab_scaling_ipq806x_match_table[] = {\n+\t{ .compatible = \"qcom,fab-scaling\" },\n+\t{ }\n+};\n+\n+static struct platform_driver fab_scaling_ipq806x_driver = {\n+\t.probe\t\t= ipq806x_fab_scaling_probe,\n+\t.remove\t\t= ipq806x_fab_scaling_remove,\n+\t.driver\t\t= {\n+\t\t.name   = \"fab-scaling\",\n+\t\t.of_match_table = fab_scaling_ipq806x_match_table,\n+\t},\n+};\n+\n+static int __init fab_scaling_ipq806x_init(void)\n+{\n+\treturn platform_driver_register(&fab_scaling_ipq806x_driver);\n+}\n+late_initcall(fab_scaling_ipq806x_init);\n+\n+static void __exit fab_scaling_ipq806x_exit(void)\n+{\n+\tplatform_driver_unregister(&fab_scaling_ipq806x_driver);\n+}\n+module_exit(fab_scaling_ipq806x_exit);\n--- /dev/null\n+++ b/include/linux/fab_scaling.h\n@@ -0,0 +1,31 @@\n+/*\n+ * Copyright (c) 2015, The Linux Foundation. All rights reserved.\n+ *\n+ * Permission to use, copy, modify, and/or distribute this software for any\n+ * purpose with or without fee is hereby granted, provided that the above\n+ * copyright notice and this permission notice appear in all copies.\n+ *\n+ * THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES\n+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF\n+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR\n+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES\n+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN\n+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF\n+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.\n+ */\n+\n+\n+#ifndef __FAB_SCALING_H\n+#define __FAB_SCALING_H\n+\n+/**\n+ * scale_fabrics - Scale DDR and APPS FABRICS\n+ *\n+ * This function monitors all the registered clocks and does APPS\n+ * and DDR FABRIC scaling based on the idle frequencies with which\n+ * it was registered.\n+ *\n+ */\n+int scale_fabrics(unsigned long max_cpu_freq);\n+\n+#endif\n--- a/drivers/cpufreq/qcom-cpufreq-krait.c\n+++ b/drivers/cpufreq/qcom-cpufreq-krait.c\n@@ -15,6 +15,7 @@\n #include <linux/regulator/consumer.h>\n #include <linux/slab.h>\n #include <linux/thermal.h>\n+#include <linux/fab_scaling.h>\n \n #include \"cpufreq-dt.h\"\n \n@@ -74,6 +75,13 @@ static int set_target(struct cpufreq_pol\n \t\t\tgoto l2_scale_fail;\n \t\t}\n \n+\t\t/*\n+\t\t * Scale fabrics with max freq across all cores\n+\t\t */\n+\t\tret = scale_fabrics(target_freq);\n+\t\tif (ret)\n+\t\t\tgoto l2_scale_fail;\n+\n \t\topp = dev_pm_opp_find_level_exact(l2_dev, level);\n \t\tif (IS_ERR(opp)) {\n \t\t\tdev_err(l2_dev,\n"
  },
  {
    "path": "target/linux/ipq806x/patches-5.15/099-1-mtd-nand-raw-qcom_nandc-add-boot_layout_mode-support.patch",
    "content": "From 6949d651e3be3ebbfedb6bbd5b541cfda6ee58a9 Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Wed, 10 Feb 2021 10:40:17 +0100\nSubject: [PATCH 1/2] mtd: nand: raw: qcom_nandc: add boot_layout_mode support\n\nipq806x nand have a special ecc configuration for the boot pages. The\nuse of the non-boot pages configuration on boot pages cause I/O error\nand can cause broken data written to the nand. Add support for this\nspecial configuration if the page to be read/write is in the size of the\nboot pages set by the dts.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\n---\n drivers/mtd/nand/raw/qcom_nandc.c | 82 +++++++++++++++++++++++++++++--\n 1 file changed, 77 insertions(+), 5 deletions(-)\n\n--- a/drivers/mtd/nand/raw/qcom_nandc.c\n+++ b/drivers/mtd/nand/raw/qcom_nandc.c\n@@ -163,6 +163,11 @@\n /* NAND_CTRL bits */\n #define\tBAM_MODE_EN\t\t\tBIT(0)\n \n+\n+#define UD_SIZE_BYTES_MASK\t(0x3ff << UD_SIZE_BYTES)\n+#define SPARE_SIZE_BYTES_MASK\t(0xf << SPARE_SIZE_BYTES)\n+#define ECC_NUM_DATA_BYTES_MASK\t(0x3ff << ECC_NUM_DATA_BYTES)\n+\n /*\n  * the NAND controller performs reads/writes with ECC in 516 byte chunks.\n  * the driver calls the chunks 'step' or 'codeword' interchangeably\n@@ -443,6 +448,13 @@ struct qcom_nand_controller {\n  * @cfg0, cfg1, cfg0_raw..:\tNANDc register configurations needed for\n  *\t\t\t\tecc/non-ecc mode for the current nand flash\n  *\t\t\t\tdevice\n+ *\n+ * @boot_pages_conf:\t\tkeep track of the current ecc configuration used by\n+ * \t\t\t\tthe driver for read/write operation. (boot pages\n+ * \t\t\t\thave different configuration than normal page)\n+ * @boot_pages:\t\t\tnumber of pages starting from 0 used as boot pages\n+ * \t\t\t\twhere the driver will use the boot pages ecc\n+ * \t\t\t\tconfiguration for read/write operation\n  */\n struct qcom_nand_host {\n \tstruct nand_chip chip;\n@@ -465,6 +477,9 @@ struct qcom_nand_host {\n \tu32 ecc_bch_cfg;\n \tu32 clrflashstatus;\n \tu32 clrreadstatus;\n+\n+\tbool boot_pages_conf;\n+\tu32 boot_pages;\n };\n \n /*\n@@ -474,6 +489,7 @@ struct qcom_nand_host {\n  * @is_bam - whether NAND controller is using BAM\n  * @is_qpic - whether NAND CTRL is part of qpic IP\n  * @qpic_v2 - flag to indicate QPIC IP version 2\n+ * @has_boot_pages - whether NAND has different ecc settings for boot pages\n  * @dev_cmd_reg_start - NAND_DEV_CMD_* registers starting offset\n  */\n struct qcom_nandc_props {\n@@ -481,6 +497,7 @@ struct qcom_nandc_props {\n \tbool is_bam;\n \tbool is_qpic;\n \tbool qpic_v2;\n+\tbool has_boot_pages;\n \tu32 dev_cmd_reg_start;\n };\n \n@@ -1691,7 +1708,7 @@ qcom_nandc_read_cw_raw(struct mtd_info *\n \tdata_size1 = mtd->writesize - host->cw_size * (ecc->steps - 1);\n \toob_size1 = host->bbm_size;\n \n-\tif (qcom_nandc_is_last_cw(ecc, cw)) {\n+\tif (qcom_nandc_is_last_cw(ecc, cw) && !host->boot_pages_conf) {\n \t\tdata_size2 = ecc->size - data_size1 -\n \t\t\t     ((ecc->steps - 1) * 4);\n \t\toob_size2 = (ecc->steps * 4) + host->ecc_bytes_hw +\n@@ -1772,7 +1789,7 @@ check_for_erased_page(struct qcom_nand_h\n \t}\n \n \tfor_each_set_bit(cw, &uncorrectable_cws, ecc->steps) {\n-\t\tif (qcom_nandc_is_last_cw(ecc, cw)) {\n+\t\tif (qcom_nandc_is_last_cw(ecc, cw) && !host->boot_pages_conf) {\n \t\t\tdata_size = ecc->size - ((ecc->steps - 1) * 4);\n \t\t\toob_size = (ecc->steps * 4) + host->ecc_bytes_hw;\n \t\t} else {\n@@ -1930,7 +1947,7 @@ static int read_page_ecc(struct qcom_nan\n \tfor (i = 0; i < ecc->steps; i++) {\n \t\tint data_size, oob_size;\n \n-\t\tif (qcom_nandc_is_last_cw(ecc, i)) {\n+\t\tif (qcom_nandc_is_last_cw(ecc, i) && !host->boot_pages_conf) {\n \t\t\tdata_size = ecc->size - ((ecc->steps - 1) << 2);\n \t\t\toob_size = (ecc->steps << 2) + host->ecc_bytes_hw +\n \t\t\t\t   host->spare_bytes;\n@@ -2027,6 +2044,30 @@ static int copy_last_cw(struct qcom_nand\n \treturn ret;\n }\n \n+static void\n+check_boot_pages_conf(struct qcom_nand_host *host, int page)\n+{\n+\tbool boot_pages_conf = page < host->boot_pages;\n+\n+\t/* Skip conf write if we are already in the correct mode */\n+\tif (boot_pages_conf != host->boot_pages_conf) {\n+\t\thost->boot_pages_conf = boot_pages_conf;\n+\n+\t\thost->cw_data = boot_pages_conf ? 512 : 516;\n+\t\thost->spare_bytes = host->cw_size - host->ecc_bytes_hw -\n+\t\t\t\t    host->bbm_size - host->cw_data;\n+\n+\t\thost->cfg0 &= ~(SPARE_SIZE_BYTES_MASK | UD_SIZE_BYTES_MASK);\n+\t\thost->cfg0 |= host->spare_bytes << SPARE_SIZE_BYTES |\n+\t\t\t      host->cw_data << UD_SIZE_BYTES;\n+\n+\t\thost->ecc_bch_cfg &= ~ECC_NUM_DATA_BYTES_MASK;\n+\t\thost->ecc_bch_cfg |= host->cw_data << ECC_NUM_DATA_BYTES;\n+\t\thost->ecc_buf_cfg = (boot_pages_conf ? 0x1ff : 0x203) <<\n+\t\t\t\t     NUM_STEPS;\n+\t}\n+}\n+\n /* implements ecc->read_page() */\n static int qcom_nandc_read_page(struct nand_chip *chip, uint8_t *buf,\n \t\t\t\tint oob_required, int page)\n@@ -2035,6 +2076,9 @@ static int qcom_nandc_read_page(struct n\n \tstruct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);\n \tu8 *data_buf, *oob_buf = NULL;\n \n+\tif (host->boot_pages)\n+\t\tcheck_boot_pages_conf(host, page);\n+\n \tnand_read_page_op(chip, page, 0, NULL, 0);\n \tdata_buf = buf;\n \toob_buf = oob_required ? chip->oob_poi : NULL;\n@@ -2054,6 +2098,9 @@ static int qcom_nandc_read_page_raw(stru\n \tint cw, ret;\n \tu8 *data_buf = buf, *oob_buf = chip->oob_poi;\n \n+\tif (host->boot_pages)\n+\t\tcheck_boot_pages_conf(host, page);\n+\n \tfor (cw = 0; cw < ecc->steps; cw++) {\n \t\tret = qcom_nandc_read_cw_raw(mtd, chip, data_buf, oob_buf,\n \t\t\t\t\t     page, cw);\n@@ -2074,6 +2121,9 @@ static int qcom_nandc_read_oob(struct na\n \tstruct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);\n \tstruct nand_ecc_ctrl *ecc = &chip->ecc;\n \n+\tif (host->boot_pages)\n+\t\tcheck_boot_pages_conf(host, page);\n+\n \tclear_read_regs(nandc);\n \tclear_bam_transaction(nandc);\n \n@@ -2094,6 +2144,9 @@ static int qcom_nandc_write_page(struct\n \tu8 *data_buf, *oob_buf;\n \tint i, ret;\n \n+\tif (host->boot_pages)\n+\t\tcheck_boot_pages_conf(host, page);\n+\n \tnand_prog_page_begin_op(chip, page, 0, NULL, 0);\n \n \tclear_read_regs(nandc);\n@@ -2109,7 +2162,7 @@ static int qcom_nandc_write_page(struct\n \tfor (i = 0; i < ecc->steps; i++) {\n \t\tint data_size, oob_size;\n \n-\t\tif (qcom_nandc_is_last_cw(ecc, i)) {\n+\t\tif (qcom_nandc_is_last_cw(ecc, i) && !host->boot_pages_conf) {\n \t\t\tdata_size = ecc->size - ((ecc->steps - 1) << 2);\n \t\t\toob_size = (ecc->steps << 2) + host->ecc_bytes_hw +\n \t\t\t\t   host->spare_bytes;\n@@ -2166,6 +2219,9 @@ static int qcom_nandc_write_page_raw(str\n \tu8 *data_buf, *oob_buf;\n \tint i, ret;\n \n+\tif (host->boot_pages)\n+\t\tcheck_boot_pages_conf(host, page);\n+\n \tnand_prog_page_begin_op(chip, page, 0, NULL, 0);\n \tclear_read_regs(nandc);\n \tclear_bam_transaction(nandc);\n@@ -2184,7 +2240,7 @@ static int qcom_nandc_write_page_raw(str\n \t\tdata_size1 = mtd->writesize - host->cw_size * (ecc->steps - 1);\n \t\toob_size1 = host->bbm_size;\n \n-\t\tif (qcom_nandc_is_last_cw(ecc, i)) {\n+\t\tif (qcom_nandc_is_last_cw(ecc, i) && !host->boot_pages_conf) {\n \t\t\tdata_size2 = ecc->size - data_size1 -\n \t\t\t\t     ((ecc->steps - 1) << 2);\n \t\t\toob_size2 = (ecc->steps << 2) + host->ecc_bytes_hw +\n@@ -2244,6 +2300,9 @@ static int qcom_nandc_write_oob(struct n\n \tint data_size, oob_size;\n \tint ret;\n \n+\tif (host->boot_pages)\n+\t\tcheck_boot_pages_conf(host, page);\n+\n \thost->use_ecc = true;\n \tclear_bam_transaction(nandc);\n \n@@ -2912,6 +2971,7 @@ static int qcom_nand_host_init_and_regis\n \tstruct nand_chip *chip = &host->chip;\n \tstruct mtd_info *mtd = nand_to_mtd(chip);\n \tstruct device *dev = nandc->dev;\n+\tu32 boot_pages_size;\n \tint ret;\n \n \tret = of_property_read_u32(dn, \"reg\", &host->cs);\n@@ -2962,6 +3022,17 @@ static int qcom_nand_host_init_and_regis\n \tif (ret)\n \t\tnand_cleanup(chip);\n \n+\tif (nandc->props->has_boot_pages &&\n+\t    of_property_read_bool(dn, \"nand-is-boot-medium\")) {\n+\t\tret = of_property_read_u32(dn, \"qcom,boot_pages_size\",\n+\t\t\t\t\t   &boot_pages_size);\n+\t\tif (ret)\n+\t\t\tdev_warn(dev, \"can't get boot pages size\");\n+\t\telse\n+\t\t\t/* Convert size to nand pages */\n+\t\t\thost->boot_pages = boot_pages_size / mtd->writesize;\n+\t}\n+\n \treturn ret;\n }\n \n@@ -3127,6 +3198,7 @@ static int qcom_nandc_remove(struct plat\n static const struct qcom_nandc_props ipq806x_nandc_props = {\n \t.ecc_modes = (ECC_RS_4BIT | ECC_BCH_8BIT),\n \t.is_bam = false,\n+\t.has_boot_pages = true,\n \t.dev_cmd_reg_start = 0x0,\n };\n \n"
  },
  {
    "path": "target/linux/ipq806x/patches-5.15/099-2-Documentation-devicetree-mtd-qcom_nandc-document-qco.patch",
    "content": "From 6fb003a7a117f97a35b078ba726c84adeae29c4c Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Wed, 10 Feb 2021 10:54:19 +0100\nSubject: [PATCH 2/2] Documentation: devicetree: mtd: qcom_nandc: document\n qcom,boot_layout_size binding\n\nDocument new qcom,boot_layout_size binding used to apply special\nread/write confituation to boots partitions.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\n---\n Documentation/devicetree/bindings/mtd/qcom,nandc.yaml | 11 +++++++++++\n 1 file changed, 11 insertions(+)\n\n--- a/Documentation/devicetree/bindings/mtd/qcom,nandc.yaml\n+++ b/Documentation/devicetree/bindings/mtd/qcom,nandc.yaml\n@@ -78,6 +78,14 @@ allOf:\n             Must contain the ADM data type CRCI block instance number\n             specified for the NAND controller on the given platform\n \n+        qcom,boot_pages_size:\n+          description:\n+            Should contain the size of the total boot partitions\n+            where the boot layout read/write specific configuration\n+            should be used. The boot layout is considered from the\n+            start of the nand to the value set in this binding.\n+            Only used in combination with 'nand-is-boot-medium'.\n+\n   - if:\n       properties:\n         compatible:\n@@ -135,6 +143,9 @@ examples:\n         nand-ecc-strength = <4>;\n         nand-bus-width = <8>;\n \n+        nand-is-boot-medium;\n+        qcom,boot_pages_size: <0x58a0000>;\n+\n         partitions {\n           compatible = \"fixed-partitions\";\n           #address-cells = <1>;\n"
  },
  {
    "path": "target/linux/ipq806x/patches-5.15/101-dwmac-ipq806x-qsgmii-pcs-all-ch-ctl.patch",
    "content": "--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c\n+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c\n@@ -64,6 +64,17 @@\n #define NSS_COMMON_CLK_DIV_SGMII_100\t\t4\n #define NSS_COMMON_CLK_DIV_SGMII_10\t\t49\n \n+#define QSGMII_PCS_ALL_CH_CTL\t\t\t0x80\n+#define QSGMII_PCS_CH_SPEED_FORCE\t\t0x2\n+#define QSGMII_PCS_CH_SPEED_10\t\t\t0x0\n+#define QSGMII_PCS_CH_SPEED_100\t\t\t0x4\n+#define QSGMII_PCS_CH_SPEED_1000\t\t0x8\n+#define QSGMII_PCS_CH_SPEED_MASK\t\t(QSGMII_PCS_CH_SPEED_FORCE | \\\n+\t\t\t\t\t\t QSGMII_PCS_CH_SPEED_10 | \\\n+\t\t\t\t\t\t QSGMII_PCS_CH_SPEED_100 | \\\n+\t\t\t\t\t\t QSGMII_PCS_CH_SPEED_1000)\n+#define QSGMII_PCS_CH_SPEED_SHIFT(x)\t\t(x * 4)\n+\n #define QSGMII_PCS_CAL_LCKDT_CTL\t\t0x120\n #define QSGMII_PCS_CAL_LCKDT_CTL_RST\t\tBIT(19)\n \n@@ -242,6 +253,36 @@ static void ipq806x_gmac_fix_mac_speed(v\n \tipq806x_gmac_set_speed(gmac, speed);\n }\n \n+static int\n+ipq806x_gmac_get_qsgmii_pcs_speed_val(struct platform_device *pdev) {\n+\tstruct device_node *fixed_link_node;\n+\tint rv;\n+\tint fixed_link_speed;\n+\n+\tif (!of_phy_is_fixed_link(pdev->dev.of_node))\n+\t\treturn 0;\n+\n+\tfixed_link_node = of_get_child_by_name(pdev->dev.of_node, \"fixed-link\");\n+\tif (!fixed_link_node)\n+\t\treturn -1;\n+\n+\trv = of_property_read_u32(fixed_link_node, \"speed\", &fixed_link_speed);\n+\tof_node_put(fixed_link_node);\n+\tif (rv)\n+\t\treturn -1;\n+\n+\tswitch (fixed_link_speed) {\n+\tcase SPEED_1000:\n+\t\treturn QSGMII_PCS_CH_SPEED_FORCE | QSGMII_PCS_CH_SPEED_1000;\n+\tcase SPEED_100:\n+\t\treturn QSGMII_PCS_CH_SPEED_FORCE | QSGMII_PCS_CH_SPEED_100;\n+\tcase SPEED_10:\n+\t\treturn QSGMII_PCS_CH_SPEED_FORCE | QSGMII_PCS_CH_SPEED_10;\n+\t}\n+\n+\treturn -1;\n+}\n+\n static int ipq806x_gmac_probe(struct platform_device *pdev)\n {\n \tstruct plat_stmmacenet_data *plat_dat;\n@@ -250,6 +291,7 @@ static int ipq806x_gmac_probe(struct pla\n \tstruct ipq806x_gmac *gmac;\n \tint val;\n \tint err;\n+\tint qsgmii_pcs_speed;\n \n \tval = stmmac_get_platform_resources(pdev, &stmmac_res);\n \tif (val)\n@@ -339,6 +381,17 @@ static int ipq806x_gmac_probe(struct pla\n \t\t\t     0x1ul << QSGMII_PHY_RX_INPUT_EQU_OFFSET |\n \t\t\t     0x2ul << QSGMII_PHY_CDR_PI_SLEW_OFFSET |\n \t\t\t     0xCul << QSGMII_PHY_TX_DRV_AMP_OFFSET);\n+\n+\t\tqsgmii_pcs_speed = ipq806x_gmac_get_qsgmii_pcs_speed_val(pdev);\n+\t\tif (qsgmii_pcs_speed != -1) {\n+\t\t\tregmap_update_bits(\n+\t\t\t    gmac->qsgmii_csr,\n+\t\t\t    QSGMII_PCS_ALL_CH_CTL,\n+\t\t\t    QSGMII_PCS_CH_SPEED_MASK <<\n+\t\t\t\tQSGMII_PCS_CH_SPEED_SHIFT(gmac->id),\n+\t\t\t    qsgmii_pcs_speed <<\n+\t\t\t\tQSGMII_PCS_CH_SPEED_SHIFT(gmac->id));\n+\t\t}\n \t}\n \n \tplat_dat->has_gmac = true;\n"
  },
  {
    "path": "target/linux/ipq806x/patches-5.15/102-mtd-rootfs-conflicts-with-OpenWrt-auto-mounting.patch",
    "content": "From 5001f2e1a325b68dbf225bd17f69a4d3d975cca5 Mon Sep 17 00:00:00 2001\nFrom: John Crispin <john@phrozen.org>\nDate: Thu, 9 Mar 2017 09:31:44 +0100\nSubject: [PATCH 61/69] mtd: \"rootfs\" conflicts with OpenWrt auto mounting\n\nSigned-off-by: John Crispin <john@phrozen.org>\n---\n drivers/mtd/mtdpart.c | 4 ++++\n 1 file changed, 4 insertions(+)\n\n--- a/drivers/mtd/mtdpart.c\n+++ b/drivers/mtd/mtdpart.c\n@@ -50,7 +50,11 @@ static struct mtd_info *allocate_partiti\n \n \t/* allocate the partition structure */\n \tchild = kzalloc(sizeof(*child), GFP_KERNEL);\n-\tname = kstrdup(part->name, GFP_KERNEL);\n+\t/* \"rootfs\" conflicts with OpenWrt auto mounting */\n+\tif (mtd_type_is_nand(parent) && !strcmp(part->name, \"rootfs\"))\n+\t\tname = \"ubi\";\n+\telse\n+\t\tname = kstrdup(part->name, GFP_KERNEL);\n \tif (!name || !child) {\n \t\tprintk(KERN_ERR\"memory allocation error while creating partitions for \\\"%s\\\"\\n\",\n \t\t       parent->name);\n"
  },
  {
    "path": "target/linux/ipq806x/patches-5.15/103-ARM-dts-qcom-reduce-pci-IO-size-to-64K.patch",
    "content": "From 84909e85881d67244240c9f40974ce12a51e3886 Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Tue, 11 May 2021 23:09:45 +0200\nSubject: [PATCH] ARM: dts: qcom: reduce pci IO size to 64K\n\nThe current value is probably a typo and is actually uncommon to find\n1MB IO space even on a x86 arch. Also with recent changes to the pci\ndriver, pci1 and pci2 now fails to function as any connected device\nfails any reg read/write. Reduce this to 64K as it should be more than\nenough and 3 * 64K of total IO space doesn't exceed the IO_SPACE_LIMIT\nhardcoded for the ARM arch.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\n---\n arch/arm/boot/dts/qcom-ipq8064.dtsi | 6 +++---\n 1 file changed, 3 insertions(+), 3 deletions(-)\n\n--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi\n+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi\n@@ -1086,7 +1086,7 @@\n \t\t\t#address-cells = <3>;\n \t\t\t#size-cells = <2>;\n \n-\t\t\tranges = <0x81000000 0 0x0fe00000 0x0fe00000 0 0x00100000   /* downstream I/O */\n+\t\t\tranges = <0x81000000 0 0x0fe00000 0x0fe00000 0 0x00010000   /* downstream I/O */\n \t\t\t\t  0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* non-prefetchable memory */\n \n \t\t\tinterrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;\n@@ -1137,7 +1137,7 @@\n \t\t\t#address-cells = <3>;\n \t\t\t#size-cells = <2>;\n \n-\t\t\tranges = <0x81000000 0 0x31e00000 0x31e00000 0 0x00100000   /* downstream I/O */\n+\t\t\tranges = <0x81000000 0 0x31e00000 0x31e00000 0 0x00010000   /* downstream I/O */\n \t\t\t\t  0x82000000 0 0x2e000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */\n \n \t\t\tinterrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;\n@@ -1188,7 +1188,7 @@\n \t\t\t#address-cells = <3>;\n \t\t\t#size-cells = <2>;\n \n-\t\t\tranges = <0x81000000 0 0x35e00000 0x35e00000 0 0x00100000   /* downstream I/O */\n+\t\t\tranges = <0x81000000 0 0x35e00000 0x35e00000 0 0x00010000   /* downstream I/O */\n \t\t\t\t  0x82000000 0 0x32000000 0x32000000 0 0x03e00000>; /* non-prefetchable memory */\n \n \t\t\tinterrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;\n"
  },
  {
    "path": "target/linux/ipq806x/patches-5.15/107-1-thermal-qcom-tsens-init-debugfs-only-with-successful.patch",
    "content": "From 8f32d48a309246a80bdca505968085a484d54408 Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Mon, 19 Apr 2021 03:01:53 +0200\nSubject: [thermal-next PATCH v2 1/2] thermal: qcom: tsens: init debugfs only with\n successful probe\n\ncalibrate and tsens_register can fail or PROBE_DEFER. This will cause a\ndouble or a wrong init of the debugfs information. Init debugfs only\nwith successful probe fixing warning about directory already present.\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nAcked-by: Thara Gopinath <thara.gopinath@linaro.org>\n---\n drivers/thermal/qcom/tsens.c | 9 ++++++---\n 1 file changed, 6 insertions(+), 3 deletions(-)\n\n--- a/drivers/thermal/qcom/tsens.c\n+++ b/drivers/thermal/qcom/tsens.c\n@@ -917,8 +917,6 @@ int __init init_common(struct tsens_priv\n \tif (tsens_version(priv) >= VER_0_1)\n \t\ttsens_enable_irq(priv);\n \n-\ttsens_debug_init(op);\n-\n err_put_device:\n \tput_device(&op->dev);\n \treturn ret;\n@@ -1157,7 +1155,12 @@ static int tsens_probe(struct platform_d\n \t\t}\n \t}\n \n-\treturn tsens_register(priv);\n+\tret = tsens_register(priv);\n+\n+\tif (!ret)\n+\t\ttsens_debug_init(pdev);\n+\n+\treturn ret;\n }\n \n static int tsens_remove(struct platform_device *pdev)\n"
  },
  {
    "path": "target/linux/ipq806x/patches-5.15/107-2-thermal-qcom-tsens-simplify-debugfs-init-function.patch",
    "content": "From 4204f22060f7a5d42c6ccb4d4c25a6a875571099 Mon Sep 17 00:00:00 2001\nFrom: Ansuel Smith <ansuelsmth@gmail.com>\nDate: Mon, 19 Apr 2021 03:08:37 +0200\nSubject: [thermal-next PATCH v2 2/2] thermal: qcom: tsens: simplify debugfs init\n function\n\nSimplify debugfs init function.\n- Add check for existing dev directory.\n- Fix wrong version in dbg_version_show (with version 0.0.0, 0.1.0 was\n  incorrectly reported)\n\nSigned-off-by: Ansuel Smith <ansuelsmth@gmail.com>\nReviewed-by: Thara Gopinath <thara.gopinath@linaro.org>\n---\n drivers/thermal/qcom/tsens.c | 16 +++++++---------\n 1 file changed, 7 insertions(+), 9 deletions(-)\n\n--- a/drivers/thermal/qcom/tsens.c\n+++ b/drivers/thermal/qcom/tsens.c\n@@ -691,7 +691,7 @@ static int dbg_version_show(struct seq_f\n \t\t\treturn ret;\n \t\tseq_printf(s, \"%d.%d.%d\\n\", maj_ver, min_ver, step_ver);\n \t} else {\n-\t\tseq_puts(s, \"0.1.0\\n\");\n+\t\tseq_printf(s, \"0.%d.0\\n\", priv->feat->ver_major);\n \t}\n \n \treturn 0;\n@@ -703,21 +703,17 @@ DEFINE_SHOW_ATTRIBUTE(dbg_sensors);\n static void tsens_debug_init(struct platform_device *pdev)\n {\n \tstruct tsens_priv *priv = platform_get_drvdata(pdev);\n-\tstruct dentry *root, *file;\n \n-\troot = debugfs_lookup(\"tsens\", NULL);\n-\tif (!root)\n+\tpriv->debug_root = debugfs_lookup(\"tsens\", NULL);\n+\tif (!priv->debug_root)\n \t\tpriv->debug_root = debugfs_create_dir(\"tsens\", NULL);\n-\telse\n-\t\tpriv->debug_root = root;\n \n-\tfile = debugfs_lookup(\"version\", priv->debug_root);\n-\tif (!file)\n+\tif (!debugfs_lookup(\"version\", priv->debug_root))\n \t\tdebugfs_create_file(\"version\", 0444, priv->debug_root,\n \t\t\t\t    pdev, &dbg_version_fops);\n \n \t/* A directory for each instance of the TSENS IP */\n-\tpriv->debug = debugfs_create_dir(dev_name(&pdev->dev), priv->debug_root);\n+\tpriv->debug = debugfs_lookup(dev_name(&pdev->dev), priv->debug_root);\n \tdebugfs_create_file(\"sensors\", 0444, priv->debug, pdev, &dbg_sensors_fops);\n }\n #else\n"
  },
  {
    "path": "target/linux/ipq806x/patches-5.15/850-soc-add-qualcomm-syscon.patch",
    "content": "From: Christian Lamparter <chunkeey@googlemail.com>\nSubject: SoC: add qualcomm syscon\n--- a/drivers/soc/qcom/Makefile\n+++ b/drivers/soc/qcom/Makefile\n@@ -21,6 +21,7 @@ obj-$(CONFIG_QCOM_SMP2P)\t+= smp2p.o\n obj-$(CONFIG_QCOM_SMSM)\t+= smsm.o\n obj-$(CONFIG_QCOM_SOCINFO)\t+= socinfo.o\n obj-$(CONFIG_QCOM_WCNSS_CTRL) += wcnss_ctrl.o\n+obj-$(CONFIG_QCOM_TCSR)\t += qcom_tcsr.o\n obj-$(CONFIG_QCOM_APR) += apr.o\n obj-$(CONFIG_QCOM_LLCC) += llcc-qcom.o\n obj-$(CONFIG_QCOM_RPMHPD) += rpmhpd.o\n--- a/drivers/soc/qcom/Kconfig\n+++ b/drivers/soc/qcom/Kconfig\n@@ -190,6 +190,13 @@ config QCOM_SOCINFO\n \t Say yes here to support the Qualcomm socinfo driver, providing\n \t information about the SoC to user space.\n \n+config QCOM_TCSR\n+\ttristate \"QCOM Top Control and Status Registers\"\n+\tdepends on ARCH_QCOM\n+\thelp\n+\t  Say y here to enable TCSR support.  The TCSR provides control\n+\t  functions for various peripherals.\n+\n config QCOM_WCNSS_CTRL\n \ttristate \"Qualcomm WCNSS control driver\"\n \tdepends on ARCH_QCOM || COMPILE_TEST\n--- /dev/null\n+++ b/drivers/soc/qcom/qcom_tcsr.c\n@@ -0,0 +1,64 @@\n+/*\n+ * Copyright (c) 2014, The Linux foundation. All rights reserved.\n+ *\n+ * This program is free software; you can redistribute it and/or modify\n+ * it under the terms of the GNU General Public License rev 2 and\n+ * only rev 2 as published by the free Software foundation.\n+ *\n+ * This program is distributed in the hope that it will be useful,\n+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\n+ * MERCHANTABILITY or fITNESS fOR A PARTICULAR PURPOSE.  See the\n+ * GNU General Public License for more details.\n+ */\n+\n+#include <linux/clk.h>\n+#include <linux/err.h>\n+#include <linux/io.h>\n+#include <linux/module.h>\n+#include <linux/of.h>\n+#include <linux/of_platform.h>\n+#include <linux/platform_device.h>\n+\n+#define TCSR_USB_PORT_SEL\t0xb0\n+\n+static int tcsr_probe(struct platform_device *pdev)\n+{\n+\tstruct resource *res;\n+\tconst struct device_node *node = pdev->dev.of_node;\n+\tvoid __iomem *base;\n+\tu32 val;\n+\n+\tres = platform_get_resource(pdev, IORESOURCE_MEM, 0);\n+\tbase = devm_ioremap_resource(&pdev->dev, res);\n+\tif (IS_ERR(base))\n+\t\treturn PTR_ERR(base);\n+\n+\tif (!of_property_read_u32(node, \"qcom,usb-ctrl-select\", &val)) {\n+\t\tdev_err(&pdev->dev, \"setting usb port select = %d\\n\", val);\n+\t\twritel(val, base + TCSR_USB_PORT_SEL);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static const struct of_device_id tcsr_dt_match[] = {\n+\t{ .compatible = \"qcom,tcsr\", },\n+\t{ },\n+};\n+\n+MODULE_DEVICE_TABLE(of, tcsr_dt_match);\n+\n+static struct platform_driver tcsr_driver = {\n+\t.driver = {\n+\t\t.name\t\t= \"tcsr\",\n+\t\t.owner\t\t= THIS_MODULE,\n+\t\t.of_match_table\t= tcsr_dt_match,\n+\t},\n+\t.probe = tcsr_probe,\n+};\n+\n+module_platform_driver(tcsr_driver);\n+\n+MODULE_AUTHOR(\"Andy Gross <agross@codeaurora.org>\");\n+MODULE_DESCRIPTION(\"QCOM TCSR driver\");\n+MODULE_LICENSE(\"GPL v2\");\n--- /dev/null\n+++ b/include/dt-bindings/soc/qcom,tcsr.h\n@@ -0,0 +1,23 @@\n+/* Copyright (c) 2014, The Linux Foundation. All rights reserved.\n+ *\n+ * This program is free software; you can redistribute it and/or modify\n+ * it under the terms of the GNU General Public License version 2 and\n+ * only version 2 as published by the Free Software Foundation.\n+ *\n+ * This program is distributed in the hope that it will be useful,\n+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\n+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n+ * GNU General Public License for more details.\n+ */\n+#ifndef __DT_BINDINGS_QCOM_TCSR_H\n+#define __DT_BINDINGS_QCOM_TCSR_H\n+\n+#define TCSR_USB_SELECT_USB3_P0\t\t0x1\n+#define TCSR_USB_SELECT_USB3_P1\t\t0x2\n+#define TCSR_USB_SELECT_USB3_DUAL\t0x3\n+\n+/* TCSR A/B REG */\n+#define IPQ806X_TCSR_REG_A_ADM_CRCI_MUX_SEL     0\n+#define IPQ806X_TCSR_REG_B_ADM_CRCI_MUX_SEL     1\n+\n+#endif\n"
  },
  {
    "path": "target/linux/ipq806x/patches-5.15/851-add-gsbi1-dts.patch",
    "content": "--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi\n+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi\n@@ -689,6 +689,41 @@\n \t\t\treg = <0x12100000 0x10000>;\n \t\t};\n \n+\t\tgsbi1: gsbi@12440000 {\n+\t\t\tcompatible = \"qcom,gsbi-v1.0.0\";\n+\t\t\tcell-index = <1>;\n+\t\t\treg = <0x12440000 0x100>;\n+\t\t\tclocks = <&gcc GSBI1_H_CLK>;\n+\t\t\tclock-names = \"iface\";\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <1>;\n+\t\t\tranges;\n+\t\t\tstatus = \"disabled\";\n+\n+\t\t\tsyscon-tcsr = <&tcsr>;\n+\n+\t\t\tgsbi1_serial: serial@12450000 {\n+\t\t\t\tcompatible = \"qcom,msm-uartdm-v1.3\", \"qcom,msm-uartdm\";\n+\t\t\t\treg = <0x12450000 0x100>,\n+\t\t\t\t      <0x12400000 0x03>;\n+\t\t\t\tinterrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\t\tclocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>;\n+\t\t\t\tclock-names = \"core\", \"iface\";\n+\t\t\t\tstatus = \"disabled\";\n+\t\t\t};\n+\n+\t\t\tgsbi1_i2c: i2c@12460000 {\n+\t\t\t\tcompatible = \"qcom,i2c-qup-v1.1.1\";\n+\t\t\t\treg = <0x12460000 0x1000>;\n+\t\t\t\tinterrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\t\tclocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;\n+\t\t\t\tclock-names = \"core\", \"iface\";\n+\t\t\t\t#address-cells = <1>;\n+\t\t\t\t#size-cells = <0>;\n+\t\t\t\tstatus = \"disabled\";\n+\t\t\t};\n+\t\t};\n+\n \t\tgsbi2: gsbi@12480000 {\n \t\t\tcompatible = \"qcom,gsbi-v1.0.0\";\n \t\t\tcell-index = <2>;\n"
  },
  {
    "path": "target/linux/kirkwood/Makefile",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2009-2015 OpenWrt.org\n\ninclude $(TOPDIR)/rules.mk\n\nARCH:=arm\nBOARD:=kirkwood\nBOARDNAME:=Marvell Kirkwood\nFEATURES:=usb nand squashfs ramdisk\nCPU_TYPE:=xscale\n\nKERNEL_PATCHVER:=5.10\nKERNEL_TESTING_PATCHVER:=5.15\n\ninclude $(INCLUDE_DIR)/target.mk\n\nKERNELNAME:=zImage dtbs\n\nDEFAULT_PACKAGES += uboot-envtools kmod-usb2\n\n$(eval $(call BuildTarget))\n"
  },
  {
    "path": "target/linux/kirkwood/base-files/etc/board.d/01_leds",
    "content": "#\n# Copyright (C) 2012-2015 OpenWrt.org\n#\n\n. /lib/functions/uci-defaults.sh\n\nboard_config_update\n\nboard=$(board_name)\n\ncase \"$board\" in\niom,ix2-200)\n\tucidef_set_led_timer \"health\" \"health\" \"status:white:rebuild_led\" \"200\" \"800\"\n\t;;\nlinksys,e4200-v2|\\\nlinksys,ea4500)\n\tucidef_set_led_default \"pulse\" \"pulse\" \"viper:white:pulse\" \"1\"\n\t;;\nesac\n\nboard_config_flush\n\nexit 0\n"
  },
  {
    "path": "target/linux/kirkwood/base-files/etc/board.d/02_network",
    "content": "#\n# Copyright (C) 2012-2015 OpenWrt.org\n#\n\n. /lib/functions/uci-defaults.sh\n. /lib/functions/system.sh\n\nkirkwood_setup_interfaces()\n{\n\tlocal board=\"$1\"\n\n\tcase \"$board\" in\n\tcheckpoint,l-50)\n\t\tucidef_set_interfaces_lan_wan \"lan1 lan2 lan3 lan4 lan5 lan6 lan7 lan8 dmz\" \"eth0\"\n\t\t;;\n\tcisco,on100)\n\t\tucidef_set_interface_lan \"eth0 eth1\"\n\t\t;;\n\tcloudengines,pogoe02|\\\n\tcloudengines,pogoplugv4|\\\n\tctera,c200-v1|\\\n\tglobalscale,sheevaplug|\\\n\tiom,iconnect-1.1|\\\n\tiom,ix2-200|\\\n\tiptime,nas1|\\\n\tnetgear,readynas-duo-v2|\\\n\traidsonic,ib-nas62x0|\\\n\tseagate,blackarmor-nas220|\\\n\tseagate,dockstar|\\\n\tseagate,goflexhome|\\\n\tseagate,goflexnet|\\\n\tzyxel,nsa310b|\\\n\tzyxel,nsa310s|\\\n\tzyxel,nsa325)\n\t\tucidef_set_interface_lan \"eth0\" \"dhcp\"\n\t\t;;\n\tendian,4i-edge-200)\n\t\tucidef_set_interface_lan \"port1 port2 port3 port4 eth1\"\n\t\t;;\n\tlinksys,e4200-v2|\\\n\tlinksys,ea3500|\\\n\tlinksys,ea4500)\n\t\tucidef_set_interfaces_lan_wan \"ethernet1 ethernet2 ethernet3 ethernet4\" \"internet\"\n\t\t;;\n\t*)\n\t\tucidef_set_interface_lan \"eth0\"\n\t\t;;\n\tesac\n}\n\nkirkwood_setup_macs()\n{\n\tlocal board=\"$1\"\n\tlocal lan_mac=\"\"\n\tlocal wan_mac=\"\"\n\tlocal label_mac=\"\"\n\n\tcase \"$board\" in\n\tiptime,nas1)\n\t\tlan_mac=$(mtd_get_mac_binary u-boot 0x3ffa8)\n\t\tlabel_mac=$lan_mac\n\t\t;;\n\tlinksys,e4200-v2|\\\n\tlinksys,ea3500|\\\n\tlinksys,ea4500)\n\t\twan_mac=$(mtd_get_mac_ascii u_env eth1addr)\n\t\t;;\n\tzyxel,nsa310b|\\\n\tzyxel,nsa325)\n\t\tlan_mac=$(mtd_get_mac_ascii uboot_env ethaddr)\n\t\t;;\n\tesac\n\n\t[ -n \"$lan_mac\" ] && ucidef_set_interface_macaddr \"lan\" $lan_mac\n\t[ -n \"$wan_mac\" ] && ucidef_set_interface_macaddr \"wan\" $wan_mac\n\t[ -n \"$label_mac\" ] && ucidef_set_label_macaddr $label_mac\n}\n\nboard_config_update\nboard=$(board_name)\nkirkwood_setup_interfaces $board\nkirkwood_setup_macs $board\nboard_config_flush\n\nexit 0\n"
  },
  {
    "path": "target/linux/kirkwood/base-files/etc/board.d/03_gpio_switches",
    "content": "\n. /lib/functions/uci-defaults.sh\n\nboard_config_update\n\nboard=$(board_name)\n\ncase \"$board\" in\ncheckpoint,l-50)\n\tucidef_add_gpio_switch \"mpcie-rst\" \"mPCIE Card reset\" \"502\" \"1\"\n\tucidef_add_gpio_switch \"exp-card-rst\" \"Express Card reset\" \"497\" \"1\"\n\t;;\nesac\n\nboard_config_flush\n\nexit 0\n"
  },
  {
    "path": "target/linux/kirkwood/base-files/etc/board.d/05_compat-version",
    "content": "#\n# Copyright (C) 2020 OpenWrt.org\n#\n\n. /lib/functions.sh\n. /lib/functions/uci-defaults.sh\n\nboard_config_update\n\ncase \"$(board_name)\" in\n\tlinksys,e4200-v2|\\\n\tlinksys,ea3500|\\\n\tlinksys,ea4500)\n\t\tucidef_set_compat_version \"2.0\"\n\t\t;;\nesac\n\nboard_config_flush\n\nexit 0\n"
  },
  {
    "path": "target/linux/kirkwood/base-files/etc/init.d/bootcount",
    "content": "#!/bin/sh /etc/rc.common\n\nSTART=99\n\nboot() {\n\tcase $(board_name) in\n\tlinksys,e4200-v2|\\\n\tlinksys,ea3500|\\\n\tlinksys,ea4500)\n\t\tmtd resetbc s_env || true\n\t\t;;\n\tesac\n}\n"
  },
  {
    "path": "target/linux/kirkwood/base-files/etc/init.d/hwmon_fancontrol",
    "content": "#!/bin/sh /etc/rc.common\n\nSTART=98\n\nboot() {\n\t# configuring onboard temp/fan controller to run the fan on its own\n\t# for more information, please read https://www.kernel.org/doc/Documentation/hwmon/sysfs-interface\n\n\tcase $(board_name) in\n\tctera,c200-v1)\n\t\tpath_to_hwmon='/sys/devices/platform/ocp@f1000000/f1011000.i2c/i2c-0/0-004c/hwmon/hwmon0'\n\n\t\t# It should be related to hdd temerature instead lm63 temp\n\t\techo 1 > \"$path_to_hwmon/pwm1_enable\"\n\t\techo 128 > \"$path_to_hwmon/pwm1\"\n\t\t;;\n\tiom,ix2-200)\n\t\tpath_to_hwmon='/sys/class/hwmon/hwmon0'\n\t\techo 2 > \"$path_to_hwmon/pwm1_enable\" # fan is on pwm1\n\t\t;;\n\tnetgear,readynas-duo-v2)\n\t\tpath_to_hwmon='/sys/class/hwmon/hwmon0'\n\t\techo 1200 > \"$path_to_hwmon/fan1_target\" # set target rpm\n\t\t;;\n\tseagate,blackarmor-nas220)\n\t\tpath_to_hwmon='/sys/devices/platform/ocp@f1000000/f1011000.i2c/i2c-0/0-002e/hwmon/hwmon0'\n\t\t# adt7476 fan control chip. 3 temp sensors. Set to 1/4 speed at 35C and max speed at 48C.\n\t\techo 7 > \"$path_to_hwmon/pwm1_auto_channels_temp\"\n\t\techo 64 > \"$path_to_hwmon/pwm1_auto_point1_pwm\"\n\t\techo 255 > \"$path_to_hwmon/pwm1_auto_point2_pwm\"\n\t\techo 35000 > \"$path_to_hwmon/temp1_auto_point1_temp\"\n\t\techo 48000 > \"$path_to_hwmon/temp1_auto_point2_temp\"\n\t\techo 35000 > \"$path_to_hwmon/temp2_auto_point1_temp\"\n\t\techo 48000 > \"$path_to_hwmon/temp2_auto_point2_temp\"\n\t\techo 35000 > \"$path_to_hwmon/temp3_auto_point1_temp\"\n\t\techo 48000 > \"$path_to_hwmon/temp3_auto_point2_temp\"\n\t\techo 2 > \"$path_to_hwmon/pwm1_enable\"\n\t\t;;\n\tzyxel,nsa310b)\n\t\tpath_to_hwmon='/sys/devices/platform/ocp@f1000000/f1011000.i2c/i2c-0/0-002e/hwmon/hwmon0'\n\t\t# use the max. value of (temp1) OR (temp2) OR (temp3) as an input\n\t\t# for the PWM of the cooling fan\n\t\techo 123 > \"$path_to_hwmon/pwm1_auto_channels\"\n\t\t# Temperature sensor #1 placed on mainboard\n\t\techo 30000 > \"$path_to_hwmon/temp1_auto_temp_min\"\n\t\techo 49600 > \"$path_to_hwmon/temp1_auto_temp_max\"\n\t\t# Temperature sensor #2 placed on mainboard\n\t\t# range: 0 to 127000 in steps of 1000 [millicelsius]\n\t\techo 30000 > \"$path_to_hwmon/temp2_auto_temp_min\"\n\t\t# range: 0 to 127000 in steps of ???? [millicelsius]\n\t\techo 49600 > \"$path_to_hwmon/temp2_auto_temp_max\"\n\t\t# Temperature sensor #3 placed close to a chipset\n\t\t# range: 0 to 60000 in steps of 1000 [millicelsius]\n\t\techo 23000 > \"$path_to_hwmon/temp3_auto_temp_min\"\n\t\t# pre-defined steps: 103000, 122000, 143300, 170000 in [millicelsius]\n\t\techo 103000 > \"$path_to_hwmon/temp3_auto_temp_max\"\n\t\t;;\n\tesac\n}\n"
  },
  {
    "path": "target/linux/kirkwood/base-files/lib/preinit/07_set_iface_mac",
    "content": ". /lib/functions.sh\n. /lib/functions/system.sh\n\npreinit_set_mac_address() {\n\tlocal mac\n\n\tcase $(board_name) in\n\tcheckpoint,l-50)\n\t\tmac=$(mtd_get_mac_ascii bootldr-env lan1_mac_addr)\n\n\t\tip link set dev lan1 address $mac 2>/dev/null\n\t\tip link set dev lan2 address $(macaddr_add $mac 1) 2>/dev/null\n\t\tip link set dev lan3 address $(macaddr_add $mac 2) 2>/dev/null\n\t\tip link set dev lan4 address $(macaddr_add $mac 3) 2>/dev/null\n\t\tip link set dev lan5 address $(macaddr_add $mac 4) 2>/dev/null\n\t\tip link set dev lan6 address $(macaddr_add $mac 5) 2>/dev/null\n\t\tip link set dev lan7 address $(macaddr_add $mac 6) 2>/dev/null\n\t\tip link set dev lan8 address $(macaddr_add $mac 7) 2>/dev/null\n\t\tip link set dev dmz address $(macaddr_add $mac 8) 2>/dev/null\n\t\tip link set dev dsl address $(macaddr_add $mac 9) 2>/dev/null\n\t\t;;\n\tendian,4i-edge-200)\n\t\tmac=$(cat /sys/class/net/eth0/address)\n\n\t\tip link set dev port1 address $mac 2>/dev/null\n\t\tip link set dev port2 address $(macaddr_add $mac 1) 2>/dev/null\n\t\tip link set dev port3 address $(macaddr_add $mac 2) 2>/dev/null\n\t\tip link set dev port4 address $(macaddr_add $mac 3) 2>/dev/null\n\t\t;;\n\tiptime,nas1)\n\t\tmac=$(mtd_get_mac_binary u-boot 0x3ffa8)\n\t\tip link set dev eth0 address $mac 2>/dev/null\n\t\t;;\n\tesac\n}\n\nboot_hook_add preinit_main preinit_set_mac_address\n"
  },
  {
    "path": "target/linux/kirkwood/base-files/lib/upgrade/linksys.sh",
    "content": "#\n# Copyright (C) 2014 OpenWrt.org\n#\n\nlinksys_get_target_firmware() {\n\n\tlocal cur_boot_part mtd_ubi0\n\n\tcur_boot_part=$(/usr/sbin/fw_printenv -n boot_part)\n\tif [ -z \"${cur_boot_part}\" ] ; then\n\t\tmtd_ubi0=$(cat /sys/devices/virtual/ubi/ubi0/mtd_num)\n\t\tcase $(grep -E ^mtd${mtd_ubi0}: /proc/mtd | cut -d '\"' -f 2) in\n\t\tkernel|rootfs)\n\t\t\tcur_boot_part=1\n\t\t\t;;\n\t\talt_kernel|alt_rootfs)\n\t\t\tcur_boot_part=2\n\t\t\t;;\n\t\tesac\n\t\t>&2 printf \"Current boot_part='%s' selected from ubi0/mtd_num='%s'\" \\\n\t\t\t\"${cur_boot_part}\" \"${mtd_ubi0}\"\n\tfi\n\n\tcase $cur_boot_part in\n\t1)\n\t\tfw_setenv -s - <<-EOF\n\t\t\tboot_part 2\n\t\t\tbootcmd \"run altnandboot\"\n\t\tEOF\n\t\tprintf \"kernel2\"\n\t\treturn\n\t\t;;\n\t2)\n\t\tfw_setenv -s - <<-EOF\n\t\t\tboot_part 1\n\t\t\tbootcmd \"run nandboot\"\n\t\tEOF\n\t\tprintf \"kernel1\"\n\t\treturn\n\t\t;;\n\t*)\n\t\treturn\n\t\t;;\n\tesac\n}\n\nplatform_do_upgrade_linksys() {\n\tlocal magic_long=\"$(get_magic_long \"$1\")\"\n\n\tmkdir -p /var/lock\n\tlocal part_label=\"$(linksys_get_target_firmware)\"\n\ttouch /var/lock/fw_printenv.lock\n\n\tif [ ! -n \"$part_label\" ]\n\tthen\n\t\techo \"cannot find target partition\"\n\t\texit 1\n\tfi\n\n\tlocal target_mtd=$(find_mtd_part $part_label)\n\n\t[ \"$magic_long\" = \"73797375\" ] && {\n\t\tCI_KERNPART=\"$part_label\"\n\t\tif [ \"$part_label\" = \"kernel1\" ]\n\t\tthen\n\t\t\tCI_UBIPART=\"rootfs1\"\n\t\telse\n\t\t\tCI_UBIPART=\"rootfs2\"\n\t\tfi\n\n\t\tnand_upgrade_tar \"$1\"\n\t}\n\t[ \"$magic_long\" = \"27051956\" ] && {\n\t\tget_image \"$1\" | mtd write - $part_label\n\t}\n}\n"
  },
  {
    "path": "target/linux/kirkwood/base-files/lib/upgrade/platform.sh",
    "content": "RAMFS_COPY_BIN='fw_printenv fw_setenv strings'\nRAMFS_COPY_DATA='/etc/fw_env.config /var/lock/fw_printenv.lock'\n\nPART_NAME=firmware\nREQUIRE_IMAGE_METADATA=1\n\nplatform_check_image() {\n\tlocal board=\"$(board_name)\"\n\n\tcase \"$board\" in\n\tnetgear,readynas-duo-v2)\n\t\t# let's store how rootfs is mounted\n\t\tcp /proc/mounts /tmp/mounts\n\t\treturn 0\n\t\t;;\n\t*)\n\t\treturn 0\n\t\t;;\n\tesac\n}\n\nplatform_do_upgrade() {\n\tlocal board=\"$(board_name)\"\n\n\tcase \"$board\" in\n\tctera,c200-v1)\n\t\tpart=$(find_mtd_part \"active_bank\")\n\n\t\tif [ -n \"$part\" ]; then\n\t\t\tCI_KERNPART=\"$(strings $part | grep bank)\"\n\t\t\tnand_do_upgrade \"$1\"\n\t\telse\n\t\t\techo \"active_bank partition missed!\"\n\t\t\treturn 1\n\t\tfi\n\t\t;;\n\tiptime,nas1)\n\t\tdefault_do_upgrade \"$1\"\n\t\t;;\n\tlinksys,e4200-v2|\\\n\tlinksys,ea3500|\\\n\tlinksys,ea4500)\n\t\tplatform_do_upgrade_linksys \"$1\"\n\t\t;;\n\t*)\n\t\tnand_do_upgrade \"$1\"\n\t\t;;\n\tesac\n}\n"
  },
  {
    "path": "target/linux/kirkwood/base-files/sbin/ctera_c200-v1_back_to_factory",
    "content": "#!/bin/sh\n\n. /lib/functions.sh\n\ncase $(board_name) in\nctera,c200-v1)\n\tpart=$(find_mtd_part \"active_bank\")\n\n\tif [ -n \"$part\" ]; then\n\t\tactive_bank=\"$(strings $part | grep bank)\"\n\n\t\tif [ $active_bank = \"bank1\" ]; then\n\t\t\techo \"bank2\" > /tmp/change_bank\n\t\telse\n\t\t\techo \"bank1\" > /tmp/change_bank\n\t\tfi\n\n\t\tmtd write /tmp/change_bank active_bank\n\t\treboot\n\telse\n\t\techo \"active_bank partition missed!\"\n\t\treturn 1\n\tfi\n\t;;\n*)\n\techo \"Unsupported hardware.\"\n\t;;\nesac\n"
  },
  {
    "path": "target/linux/kirkwood/config-5.10",
    "content": "CONFIG_ALIGNMENT_TRAP=y\nCONFIG_ARCH_32BIT_OFF_T=y\nCONFIG_ARCH_HIBERNATION_POSSIBLE=y\nCONFIG_ARCH_KEEP_MEMBLOCK=y\nCONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y\nCONFIG_ARCH_MULTIPLATFORM=y\nCONFIG_ARCH_MULTI_CPU_AUTO=y\n# CONFIG_ARCH_MULTI_V4 is not set\n# CONFIG_ARCH_MULTI_V4T is not set\nCONFIG_ARCH_MULTI_V4_V5=y\nCONFIG_ARCH_MULTI_V5=y\nCONFIG_ARCH_MVEBU=y\nCONFIG_ARCH_NR_GPIO=0\nCONFIG_ARCH_OPTIONAL_KERNEL_RWX=y\nCONFIG_ARCH_SELECT_MEMORY_MODEL=y\nCONFIG_ARCH_SPARSEMEM_ENABLE=y\nCONFIG_ARCH_SUSPEND_POSSIBLE=y\nCONFIG_ARM=y\n# CONFIG_ARMADA_37XX_WATCHDOG is not set\n# CONFIG_ARMADA_THERMAL is not set\nCONFIG_ARM_APPENDED_DTB=y\nCONFIG_ARM_ATAG_DTB_COMPAT=y\nCONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y\nCONFIG_ARM_HAS_SG_CHAIN=y\n# CONFIG_ARM_KIRKWOOD_CPUIDLE is not set\nCONFIG_ARM_L1_CACHE_SHIFT=5\n# CONFIG_ARM_MVEBU_V7_CPUIDLE is not set\nCONFIG_ARM_PATCH_PHYS_VIRT=y\n# CONFIG_ARM_THUMB is not set\nCONFIG_ARM_UNWIND=y\nCONFIG_ATA=y\nCONFIG_ATAGS=y\nCONFIG_ATA_LEDS=y\nCONFIG_AUTO_ZRELADDR=y\nCONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y\nCONFIG_BLK_DEV_SD=y\nCONFIG_BLK_MQ_PCI=y\nCONFIG_BLK_SCSI_REQUEST=y\nCONFIG_CACHE_FEROCEON_L2=y\n# CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH is not set\nCONFIG_CLKDEV_LOOKUP=y\nCONFIG_CLKSRC_MMIO=y\nCONFIG_CLONE_BACKWARDS=y\nCONFIG_COMMON_CLK=y\nCONFIG_COMPAT_32BIT_TIME=y\nCONFIG_CPU_32v5=y\nCONFIG_CPU_ABRT_EV5T=y\nCONFIG_CPU_CACHE_VIVT=y\nCONFIG_CPU_COPY_FEROCEON=y\nCONFIG_CPU_CP15=y\nCONFIG_CPU_CP15_MMU=y\nCONFIG_CPU_FEROCEON=y\n# CONFIG_CPU_FEROCEON_OLD_ID is not set\nCONFIG_CPU_IDLE=y\nCONFIG_CPU_IDLE_GOV_LADDER=y\nCONFIG_CPU_PABRT_LEGACY=y\nCONFIG_CPU_PM=y\nCONFIG_CPU_THERMAL=y\nCONFIG_CPU_THUMB_CAPABLE=y\nCONFIG_CPU_TLB_FEROCEON=y\nCONFIG_CPU_USE_DOMAINS=y\nCONFIG_CRC16=y\n# CONFIG_CRC32_SARWATE is not set\nCONFIG_CRC32_SLICEBY8=y\nCONFIG_CRYPTO_CRC32C=y\nCONFIG_CRYPTO_DEFLATE=y\nCONFIG_CRYPTO_DES=y\nCONFIG_CRYPTO_DEV_MARVELL=y\nCONFIG_CRYPTO_DEV_MARVELL_CESA=y\nCONFIG_CRYPTO_HASH_INFO=y\nCONFIG_CRYPTO_HW=y\nCONFIG_CRYPTO_LIB_DES=y\nCONFIG_CRYPTO_LZO=y\nCONFIG_CRYPTO_RNG2=y\nCONFIG_CRYPTO_ZSTD=y\nCONFIG_DEBUG_LL=y\nCONFIG_DEBUG_LL_INCLUDE=\"debug/8250.S\"\nCONFIG_DEBUG_MVEBU_UART0_ALTERNATE=y\n# CONFIG_DEBUG_MVEBU_UART1_ALTERNATE is not set\nCONFIG_DEBUG_UART_8250=y\nCONFIG_DEBUG_UART_8250_SHIFT=2\nCONFIG_DEBUG_UART_PHYS=0xf1012000\nCONFIG_DEBUG_UART_VIRT=0xfed12000\nCONFIG_DEBUG_UNCOMPRESS=y\n# CONFIG_DLCI is not set\nCONFIG_DMA_OPS=y\nCONFIG_DMA_REMAP=y\nCONFIG_DNOTIFY=y\nCONFIG_DTC=y\n# CONFIG_EARLY_PRINTK is not set\nCONFIG_EDAC_ATOMIC_SCRUB=y\nCONFIG_EDAC_SUPPORT=y\nCONFIG_FIXED_PHY=y\nCONFIG_FIX_EARLYCON_MEM=y\nCONFIG_FORCE_PCI=y\nCONFIG_FW_LOADER_PAGED_BUF=y\nCONFIG_GENERIC_ALLOCATOR=y\nCONFIG_GENERIC_ATOMIC64=y\nCONFIG_GENERIC_BUG=y\nCONFIG_GENERIC_CLOCKEVENTS=y\nCONFIG_GENERIC_CPU_AUTOPROBE=y\nCONFIG_GENERIC_EARLY_IOREMAP=y\nCONFIG_GENERIC_IDLE_POLL_SETUP=y\nCONFIG_GENERIC_IRQ_CHIP=y\nCONFIG_GENERIC_IRQ_MULTI_HANDLER=y\nCONFIG_GENERIC_IRQ_SHOW=y\nCONFIG_GENERIC_IRQ_SHOW_LEVEL=y\nCONFIG_GENERIC_PCI_IOMAP=y\nCONFIG_GENERIC_PHY=y\nCONFIG_GENERIC_PINCONF=y\nCONFIG_GENERIC_SCHED_CLOCK=y\nCONFIG_GENERIC_SMP_IDLE_THREAD=y\nCONFIG_GENERIC_STRNCPY_FROM_USER=y\nCONFIG_GENERIC_STRNLEN_USER=y\nCONFIG_GLOB=y\nCONFIG_GPIOLIB=y\nCONFIG_GPIOLIB_IRQCHIP=y\nCONFIG_GPIO_MVEBU=y\nCONFIG_GRO_CELLS=y\nCONFIG_HANDLE_DOMAIN_IRQ=y\nCONFIG_HARDIRQS_SW_RESEND=y\nCONFIG_HAS_DMA=y\nCONFIG_HAS_IOMEM=y\nCONFIG_HAS_IOPORT_MAP=y\nCONFIG_HWMON=y\nCONFIG_HW_RANDOM=y\nCONFIG_HW_RANDOM_OMAP=y\nCONFIG_HZ_FIXED=0\nCONFIG_HZ_PERIODIC=y\nCONFIG_I2C=y\nCONFIG_I2C_BOARDINFO=y\nCONFIG_I2C_CHARDEV=y\nCONFIG_I2C_MV64XXX=y\n# CONFIG_I2C_PXA is not set\nCONFIG_INITRAMFS_SOURCE=\"\"\nCONFIG_IRQCHIP=y\nCONFIG_IRQ_DOMAIN=y\nCONFIG_IRQ_FORCED_THREADING=y\nCONFIG_IRQ_WORK=y\nCONFIG_KIRKWOOD_CLK=y\nCONFIG_KIRKWOOD_THERMAL=y\nCONFIG_LEDS_GPIO=y\nCONFIG_LEDS_NETXBIG=y\nCONFIG_LEDS_NS2=y\nCONFIG_LIBFDT=y\nCONFIG_LOCK_DEBUGGING_SUPPORT=y\nCONFIG_LZO_COMPRESS=y\nCONFIG_LZO_DECOMPRESS=y\nCONFIG_MACH_KIRKWOOD=y\nCONFIG_MACH_MVEBU_ANY=y\nCONFIG_MANGLE_BOOTARGS=y\nCONFIG_MARVELL_PHY=y\nCONFIG_MDIO_BUS=y\nCONFIG_MDIO_DEVICE=y\nCONFIG_MDIO_DEVRES=y\nCONFIG_MEMFD_CREATE=y\nCONFIG_MIGRATION=y\nCONFIG_MODULES_USE_ELF_REL=y\n# CONFIG_MTD_CFI is not set\nCONFIG_MTD_CMDLINE_PARTS=y\nCONFIG_MTD_NAND_CORE=y\nCONFIG_MTD_NAND_ECC=y\nCONFIG_MTD_NAND_ECC_SW_HAMMING=y\n# CONFIG_MTD_NAND_MARVELL is not set\nCONFIG_MTD_NAND_ORION=y\nCONFIG_MTD_RAW_NAND=y\nCONFIG_MTD_SPI_NOR=y\nCONFIG_MTD_SPLIT_FIRMWARE=y\nCONFIG_MTD_SPLIT_UIMAGE_FW=y\nCONFIG_MTD_UBI=y\nCONFIG_MTD_UBI_BEB_LIMIT=20\nCONFIG_MTD_UBI_BLOCK=y\nCONFIG_MTD_UBI_WL_THRESHOLD=4096\nCONFIG_MV643XX_ETH=y\nCONFIG_MVEBU_CLK_COMMON=y\nCONFIG_MVEBU_MBUS=y\nCONFIG_MVMDIO=y\n# CONFIG_MVNETA is not set\n# CONFIG_MVPP2 is not set\nCONFIG_NEED_DMA_MAP_STATE=y\nCONFIG_NEED_KUSER_HELPERS=y\nCONFIG_NEED_PER_CPU_KM=y\nCONFIG_NET_DEVLINK=y\nCONFIG_NET_DSA=y\nCONFIG_NET_DSA_MV88E6XXX=y\nCONFIG_NET_DSA_MV88E6XXX_GLOBAL2=y\nCONFIG_NET_DSA_TAG_DSA=y\nCONFIG_NET_DSA_TAG_EDSA=y\nCONFIG_NET_SWITCHDEV=y\nCONFIG_NLS=y\nCONFIG_NVMEM=y\nCONFIG_OF=y\nCONFIG_OF_ADDRESS=y\nCONFIG_OF_EARLY_FLATTREE=y\nCONFIG_OF_FLATTREE=y\nCONFIG_OF_GPIO=y\nCONFIG_OF_IRQ=y\nCONFIG_OF_KOBJ=y\nCONFIG_OF_MDIO=y\nCONFIG_OF_NET=y\nCONFIG_OLD_SIGACTION=y\nCONFIG_OLD_SIGSUSPEND3=y\nCONFIG_ORION_IRQCHIP=y\nCONFIG_ORION_TIMER=y\nCONFIG_ORION_WATCHDOG=y\nCONFIG_OUTER_CACHE=y\nCONFIG_PAGE_OFFSET=0xC0000000\nCONFIG_PCI=y\nCONFIG_PCI_BRIDGE_EMUL=y\nCONFIG_PCI_DOMAINS=y\nCONFIG_PCI_DOMAINS_GENERIC=y\nCONFIG_PCI_MVEBU=y\nCONFIG_PERF_USE_VMALLOC=y\nCONFIG_PGTABLE_LEVELS=2\nCONFIG_PHYLIB=y\nCONFIG_PHYLINK=y\n# CONFIG_PHY_MVEBU_A3700_UTMI is not set\n# CONFIG_PHY_MVEBU_A38X_COMPHY is not set\nCONFIG_PHY_MVEBU_SATA=y\nCONFIG_PINCTRL=y\nCONFIG_PINCTRL_KIRKWOOD=y\nCONFIG_PINCTRL_MVEBU=y\n# CONFIG_PINCTRL_SINGLE is not set\nCONFIG_PINCTRL_SX150X=y\nCONFIG_PLAT_ORION=y\nCONFIG_POWER_RESET=y\nCONFIG_POWER_RESET_GPIO=y\nCONFIG_POWER_RESET_LINKSTATION=y\nCONFIG_POWER_SUPPLY=y\nCONFIG_RATIONAL=y\nCONFIG_REGMAP=y\nCONFIG_REGMAP_MMIO=y\nCONFIG_REGULATOR=y\nCONFIG_REGULATOR_FIXED_VOLTAGE=y\nCONFIG_RTC_CLASS=y\nCONFIG_RTC_DRV_MV=y\nCONFIG_RTC_I2C_AND_SPI=y\nCONFIG_RTC_MC146818_LIB=y\nCONFIG_SATA_HOST=y\nCONFIG_SATA_PMP=y\nCONFIG_SCSI=y\nCONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y\nCONFIG_SERIAL_8250_FSL=y\nCONFIG_SERIAL_MCTRL_GPIO=y\n# CONFIG_SERIAL_MVEBU_UART is not set\nCONFIG_SERIAL_OF_PLATFORM=y\nCONFIG_SGL_ALLOC=y\nCONFIG_SG_POOL=y\nCONFIG_SOC_BUS=y\nCONFIG_SPARSE_IRQ=y\nCONFIG_SPI=y\n# CONFIG_SPI_ARMADA_3700 is not set\nCONFIG_SPI_MASTER=y\nCONFIG_SPI_MEM=y\nCONFIG_SPI_ORION=y\nCONFIG_SPLIT_PTLOCK_CPUS=999999\nCONFIG_SRAM=y\nCONFIG_SRAM_EXEC=y\nCONFIG_SRCU=y\nCONFIG_SWPHY=y\nCONFIG_SYS_SUPPORTS_APM_EMULATION=y\nCONFIG_THERMAL=y\nCONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y\nCONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0\nCONFIG_THERMAL_GOV_STEP_WISE=y\nCONFIG_THERMAL_HWMON=y\nCONFIG_THERMAL_OF=y\nCONFIG_TICK_CPU_ACCOUNTING=y\nCONFIG_TIMER_OF=y\nCONFIG_TIMER_PROBE=y\nCONFIG_TINY_SRCU=y\nCONFIG_UBIFS_FS=y\nCONFIG_UNCOMPRESS_INCLUDE=\"debug/uncompress.h\"\nCONFIG_UNWINDER_ARM=y\nCONFIG_USB=y\nCONFIG_USB_COMMON=y\nCONFIG_USB_LED_TRIG=y\nCONFIG_USB_SUPPORT=y\nCONFIG_USE_OF=y\n# CONFIG_VFP is not set\nCONFIG_VM_EVENT_COUNTERS=y\nCONFIG_WAN=y\nCONFIG_WATCHDOG_CORE=y\nCONFIG_XXHASH=y\nCONFIG_XZ_DEC_ARM=y\nCONFIG_XZ_DEC_BCJ=y\nCONFIG_ZBOOT_ROM_BSS=0x0\nCONFIG_ZBOOT_ROM_TEXT=0x0\nCONFIG_ZLIB_DEFLATE=y\nCONFIG_ZLIB_INFLATE=y\nCONFIG_ZSTD_COMPRESS=y\nCONFIG_ZSTD_DECOMPRESS=y\n"
  },
  {
    "path": "target/linux/kirkwood/config-5.15",
    "content": "CONFIG_ALIGNMENT_TRAP=y\nCONFIG_ARCH_32BIT_OFF_T=y\nCONFIG_ARCH_HIBERNATION_POSSIBLE=y\nCONFIG_ARCH_KEEP_MEMBLOCK=y\nCONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y\nCONFIG_ARCH_MULTIPLATFORM=y\nCONFIG_ARCH_MULTI_CPU_AUTO=y\n# CONFIG_ARCH_MULTI_V4 is not set\n# CONFIG_ARCH_MULTI_V4T is not set\nCONFIG_ARCH_MULTI_V4_V5=y\nCONFIG_ARCH_MULTI_V5=y\nCONFIG_ARCH_MVEBU=y\nCONFIG_ARCH_NR_GPIO=0\nCONFIG_ARCH_OPTIONAL_KERNEL_RWX=y\nCONFIG_ARCH_SELECT_MEMORY_MODEL=y\nCONFIG_ARCH_SPARSEMEM_ENABLE=y\nCONFIG_ARCH_SUSPEND_POSSIBLE=y\nCONFIG_ARM=y\n# CONFIG_ARMADA_37XX_WATCHDOG is not set\n# CONFIG_ARMADA_THERMAL is not set\nCONFIG_ARM_APPENDED_DTB=y\nCONFIG_ARM_ATAG_DTB_COMPAT=y\nCONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y\nCONFIG_ARM_HAS_SG_CHAIN=y\n# CONFIG_ARM_KIRKWOOD_CPUIDLE is not set\nCONFIG_ARM_L1_CACHE_SHIFT=5\n# CONFIG_ARM_MVEBU_V7_CPUIDLE is not set\nCONFIG_ARM_PATCH_PHYS_VIRT=y\n# CONFIG_ARM_THUMB is not set\nCONFIG_ARM_UNWIND=y\nCONFIG_ATA=y\nCONFIG_ATAGS=y\nCONFIG_ATA_LEDS=y\nCONFIG_AUTO_ZRELADDR=y\nCONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y\nCONFIG_BLK_DEV_SD=y\nCONFIG_BLK_MQ_PCI=y\nCONFIG_CACHE_FEROCEON_L2=y\n# CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH is not set\nCONFIG_CLKSRC_MMIO=y\nCONFIG_CLONE_BACKWARDS=y\nCONFIG_COMMON_CLK=y\nCONFIG_COMPAT_32BIT_TIME=y\nCONFIG_CPU_32v5=y\nCONFIG_CPU_ABRT_EV5T=y\nCONFIG_CPU_CACHE_VIVT=y\nCONFIG_CPU_COPY_FEROCEON=y\nCONFIG_CPU_CP15=y\nCONFIG_CPU_CP15_MMU=y\nCONFIG_CPU_FEROCEON=y\n# CONFIG_CPU_FEROCEON_OLD_ID is not set\nCONFIG_CPU_IDLE=y\nCONFIG_CPU_IDLE_GOV_LADDER=y\nCONFIG_CPU_PABRT_LEGACY=y\nCONFIG_CPU_PM=y\nCONFIG_CPU_THERMAL=y\nCONFIG_CPU_THUMB_CAPABLE=y\nCONFIG_CPU_TLB_FEROCEON=y\nCONFIG_CPU_USE_DOMAINS=y\nCONFIG_CRC16=y\n# CONFIG_CRC32_SARWATE is not set\nCONFIG_CRC32_SLICEBY8=y\nCONFIG_CRYPTO_CRC32C=y\nCONFIG_CRYPTO_DEFLATE=y\nCONFIG_CRYPTO_DES=y\nCONFIG_CRYPTO_DEV_MARVELL=y\nCONFIG_CRYPTO_DEV_MARVELL_CESA=y\nCONFIG_CRYPTO_HASH_INFO=y\nCONFIG_CRYPTO_HW=y\nCONFIG_CRYPTO_LIB_DES=y\nCONFIG_CRYPTO_LZO=y\nCONFIG_CRYPTO_RNG2=y\nCONFIG_CRYPTO_ZSTD=y\nCONFIG_DEBUG_LL=y\nCONFIG_DEBUG_LL_INCLUDE=\"debug/8250.S\"\nCONFIG_DEBUG_MVEBU_UART0_ALTERNATE=y\n# CONFIG_DEBUG_MVEBU_UART1_ALTERNATE is not set\nCONFIG_DEBUG_UART_8250=y\nCONFIG_DEBUG_UART_8250_SHIFT=2\nCONFIG_DEBUG_UART_PHYS=0xf1012000\nCONFIG_DEBUG_UART_VIRT=0xfed12000\nCONFIG_DEBUG_UNCOMPRESS=y\nCONFIG_DMA_OPS=y\nCONFIG_DMA_REMAP=y\nCONFIG_DNOTIFY=y\nCONFIG_DTC=y\n# CONFIG_EARLY_PRINTK is not set\nCONFIG_EDAC_ATOMIC_SCRUB=y\nCONFIG_EDAC_SUPPORT=y\nCONFIG_FIXED_PHY=y\nCONFIG_FIX_EARLYCON_MEM=y\nCONFIG_FORCE_PCI=y\nCONFIG_FWNODE_MDIO=y\nCONFIG_FW_LOADER_PAGED_BUF=y\nCONFIG_GENERIC_ALLOCATOR=y\nCONFIG_GENERIC_ATOMIC64=y\nCONFIG_GENERIC_BUG=y\nCONFIG_GENERIC_CLOCKEVENTS=y\nCONFIG_GENERIC_CPU_AUTOPROBE=y\nCONFIG_GENERIC_EARLY_IOREMAP=y\nCONFIG_GENERIC_IDLE_POLL_SETUP=y\nCONFIG_GENERIC_IRQ_CHIP=y\nCONFIG_GENERIC_IRQ_MULTI_HANDLER=y\nCONFIG_GENERIC_IRQ_SHOW=y\nCONFIG_GENERIC_IRQ_SHOW_LEVEL=y\nCONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y\nCONFIG_GENERIC_PCI_IOMAP=y\nCONFIG_GENERIC_PHY=y\nCONFIG_GENERIC_PINCONF=y\nCONFIG_GENERIC_SCHED_CLOCK=y\nCONFIG_GENERIC_SMP_IDLE_THREAD=y\nCONFIG_GENERIC_STRNCPY_FROM_USER=y\nCONFIG_GENERIC_STRNLEN_USER=y\nCONFIG_GLOB=y\nCONFIG_GPIOLIB=y\nCONFIG_GPIOLIB_IRQCHIP=y\nCONFIG_GPIO_CDEV=y\nCONFIG_GPIO_MVEBU=y\nCONFIG_GRO_CELLS=y\nCONFIG_HANDLE_DOMAIN_IRQ=y\nCONFIG_HARDIRQS_SW_RESEND=y\nCONFIG_HAS_DMA=y\nCONFIG_HAS_IOMEM=y\nCONFIG_HAS_IOPORT_MAP=y\nCONFIG_HWMON=y\nCONFIG_HW_RANDOM=y\nCONFIG_HW_RANDOM_OMAP=y\nCONFIG_HZ_FIXED=0\nCONFIG_HZ_PERIODIC=y\nCONFIG_I2C=y\nCONFIG_I2C_BOARDINFO=y\nCONFIG_I2C_CHARDEV=y\nCONFIG_I2C_MV64XXX=y\n# CONFIG_I2C_PXA is not set\nCONFIG_INITRAMFS_SOURCE=\"\"\nCONFIG_IRQCHIP=y\nCONFIG_IRQ_DOMAIN=y\nCONFIG_IRQ_FORCED_THREADING=y\nCONFIG_IRQ_WORK=y\nCONFIG_KIRKWOOD_CLK=y\nCONFIG_KIRKWOOD_THERMAL=y\nCONFIG_LEDS_GPIO=y\nCONFIG_LEDS_NETXBIG=y\nCONFIG_LEDS_NS2=y\nCONFIG_LIBFDT=y\nCONFIG_LOCK_DEBUGGING_SUPPORT=y\nCONFIG_LZO_COMPRESS=y\nCONFIG_LZO_DECOMPRESS=y\nCONFIG_MACH_KIRKWOOD=y\nCONFIG_MACH_MVEBU_ANY=y\nCONFIG_MANGLE_BOOTARGS=y\nCONFIG_MARVELL_PHY=y\nCONFIG_MDIO_BUS=y\nCONFIG_MDIO_DEVICE=y\nCONFIG_MDIO_DEVRES=y\nCONFIG_MEMFD_CREATE=y\nCONFIG_MIGRATION=y\nCONFIG_MODULES_USE_ELF_REL=y\n# CONFIG_MTD_CFI is not set\nCONFIG_MTD_CMDLINE_PARTS=y\nCONFIG_MTD_NAND_CORE=y\nCONFIG_MTD_NAND_ECC=y\nCONFIG_MTD_NAND_ECC_SW_HAMMING=y\n# CONFIG_MTD_NAND_MARVELL is not set\nCONFIG_MTD_NAND_ORION=y\nCONFIG_MTD_RAW_NAND=y\nCONFIG_MTD_SPI_NOR=y\nCONFIG_MTD_SPLIT_FIRMWARE=y\nCONFIG_MTD_SPLIT_UIMAGE_FW=y\nCONFIG_MTD_UBI=y\nCONFIG_MTD_UBI_BEB_LIMIT=20\nCONFIG_MTD_UBI_BLOCK=y\nCONFIG_MTD_UBI_WL_THRESHOLD=4096\nCONFIG_MV643XX_ETH=y\nCONFIG_MVEBU_CLK_COMMON=y\nCONFIG_MVEBU_MBUS=y\nCONFIG_MVMDIO=y\n# CONFIG_MVNETA is not set\n# CONFIG_MVPP2 is not set\nCONFIG_NEED_DMA_MAP_STATE=y\nCONFIG_NEED_KUSER_HELPERS=y\nCONFIG_NEED_PER_CPU_KM=y\nCONFIG_NET_DEVLINK=y\nCONFIG_NET_DSA=y\nCONFIG_NET_DSA_MV88E6XXX=y\nCONFIG_NET_DSA_TAG_DSA=y\nCONFIG_NET_DSA_TAG_DSA_COMMON=y\nCONFIG_NET_DSA_TAG_EDSA=y\nCONFIG_NET_SELFTESTS=y\nCONFIG_NET_SWITCHDEV=y\nCONFIG_NLS=y\nCONFIG_NVMEM=y\nCONFIG_OF=y\nCONFIG_OF_ADDRESS=y\nCONFIG_OF_EARLY_FLATTREE=y\nCONFIG_OF_FLATTREE=y\nCONFIG_OF_GPIO=y\nCONFIG_OF_IRQ=y\nCONFIG_OF_KOBJ=y\nCONFIG_OF_MDIO=y\nCONFIG_OLD_SIGACTION=y\nCONFIG_OLD_SIGSUSPEND3=y\nCONFIG_ORION_IRQCHIP=y\nCONFIG_ORION_TIMER=y\nCONFIG_ORION_WATCHDOG=y\nCONFIG_OUTER_CACHE=y\nCONFIG_PAGE_OFFSET=0xC0000000\nCONFIG_PCI=y\nCONFIG_PCI_BRIDGE_EMUL=y\nCONFIG_PCI_DOMAINS=y\nCONFIG_PCI_DOMAINS_GENERIC=y\nCONFIG_PCI_MVEBU=y\nCONFIG_PERF_USE_VMALLOC=y\nCONFIG_PGTABLE_LEVELS=2\nCONFIG_PHYLIB=y\nCONFIG_PHYLINK=y\n# CONFIG_PHY_MVEBU_A3700_UTMI is not set\n# CONFIG_PHY_MVEBU_A38X_COMPHY is not set\nCONFIG_PHY_MVEBU_SATA=y\nCONFIG_PINCTRL=y\nCONFIG_PINCTRL_KIRKWOOD=y\nCONFIG_PINCTRL_MVEBU=y\n# CONFIG_PINCTRL_SINGLE is not set\nCONFIG_PINCTRL_SX150X=y\nCONFIG_PLAT_ORION=y\nCONFIG_POWER_RESET=y\nCONFIG_POWER_RESET_GPIO=y\nCONFIG_POWER_RESET_LINKSTATION=y\nCONFIG_POWER_SUPPLY=y\nCONFIG_PTP_1588_CLOCK_OPTIONAL=y\nCONFIG_RATIONAL=y\nCONFIG_REGMAP=y\nCONFIG_REGMAP_MMIO=y\nCONFIG_REGULATOR=y\nCONFIG_REGULATOR_FIXED_VOLTAGE=y\nCONFIG_RTC_CLASS=y\nCONFIG_RTC_DRV_MV=y\nCONFIG_RTC_I2C_AND_SPI=y\nCONFIG_RTC_MC146818_LIB=y\nCONFIG_SATA_HOST=y\nCONFIG_SATA_PMP=y\nCONFIG_SCSI=y\nCONFIG_SCSI_COMMON=y\nCONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y\nCONFIG_SERIAL_8250_FSL=y\nCONFIG_SERIAL_MCTRL_GPIO=y\n# CONFIG_SERIAL_MVEBU_UART is not set\nCONFIG_SERIAL_OF_PLATFORM=y\nCONFIG_SGL_ALLOC=y\nCONFIG_SG_POOL=y\nCONFIG_SOC_BUS=y\nCONFIG_SPARSE_IRQ=y\nCONFIG_SPI=y\n# CONFIG_SPI_ARMADA_3700 is not set\nCONFIG_SPI_MASTER=y\nCONFIG_SPI_MEM=y\nCONFIG_SPI_ORION=y\nCONFIG_SPLIT_PTLOCK_CPUS=999999\nCONFIG_SRAM=y\nCONFIG_SRAM_EXEC=y\nCONFIG_SRCU=y\nCONFIG_SWPHY=y\nCONFIG_SYS_SUPPORTS_APM_EMULATION=y\nCONFIG_THERMAL=y\nCONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y\nCONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0\nCONFIG_THERMAL_GOV_STEP_WISE=y\nCONFIG_THERMAL_HWMON=y\nCONFIG_THERMAL_OF=y\nCONFIG_TICK_CPU_ACCOUNTING=y\nCONFIG_TIMER_OF=y\nCONFIG_TIMER_PROBE=y\nCONFIG_TINY_SRCU=y\nCONFIG_UBIFS_FS=y\nCONFIG_UNCOMPRESS_INCLUDE=\"debug/uncompress.h\"\nCONFIG_UNWINDER_ARM=y\nCONFIG_USB=y\nCONFIG_USB_COMMON=y\nCONFIG_USB_LED_TRIG=y\nCONFIG_USB_SUPPORT=y\nCONFIG_USE_OF=y\n# CONFIG_VFP is not set\nCONFIG_VM_EVENT_COUNTERS=y\nCONFIG_WAN=y\nCONFIG_WATCHDOG_CORE=y\nCONFIG_XXHASH=y\nCONFIG_XZ_DEC_ARM=y\nCONFIG_XZ_DEC_BCJ=y\nCONFIG_ZBOOT_ROM_BSS=0x0\nCONFIG_ZBOOT_ROM_TEXT=0x0\nCONFIG_ZLIB_DEFLATE=y\nCONFIG_ZLIB_INFLATE=y\nCONFIG_ZSTD_COMPRESS=y\nCONFIG_ZSTD_DECOMPRESS=y\n"
  },
  {
    "path": "target/linux/kirkwood/files/arch/arm/boot/dts/kirkwood-4i-edge-200.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later\n/*\n * Endian 4i Edge 200 Board Description\n * Note: Endian UTM Mini is hardware clone of Endian Edge 200\n * Copyright 2021 Pawel Dembicki <paweldembicki@gmail.com>\n */\n\n/dts-v1/;\n\n#include \"kirkwood.dtsi\"\n#include \"kirkwood-6281.dtsi\"\n\n/ {\n\tmodel = \"Endian 4i Edge 200\";\n\tcompatible = \"endian,4i-edge-200\", \"marvell,kirkwood-88f6281\", \"marvell,kirkwood\";\n\n\tmemory {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x00000000 0x20000000>;\n\t};\n\n\taliases {\n\t\tled-boot = &led_status_green;\n\t\tled-failsafe = &led_status_orange;\n\t\tled-running = &led_status_green;\n\t\tled-upgrade = &led_status_orange;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200n8\";\n\t\tstdout-path = &uart0;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tpinctrl-0 = <&pmx_led49 &pmx_led35 &pmx_led34>;\n\t\tpinctrl-names = \"default\";\n\n\t\tled_status_green: status_green {\n\t\t\tlabel = \"green:status\";\n\t\t\tgpios = <&gpio1 17 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tled_status_orange: status_orange {\n\t\t\tlabel = \"orange:status\";\n\t\t\tgpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tsdcard {\n\t\t\tlabel = \"orange:sdcard\";\n\t\t\tgpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"mmc0\";\n\t\t};\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n};\n\n&eth0port {\n\tspeed = <1000>;\n\tduplex = <1>;\n};\n\n&eth1 {\n\tstatus = \"okay\";\n};\n\n&eth1port {\n\tphy-handle = <&ethphyb>;\n};\n\n&mdio {\n\tstatus = \"okay\";\n\n\tethphyb: ethernet-phy@b {\n\t\treg = <0x0b>;\n\n\t\tmarvell,reg-init =\n\t\t\t/* link-activity, bi-color mode 4 */\n\t\t\t<3 0x10 0xfff0 0xf>; /* Reg 3,16 <- 0xzzzf */\n\t};\n\n\tswitch0: switch@11 {\n\t\tcompatible = \"marvell,mv88e6085\";\n\t\treg = <0x11>;\n\n\t\tports {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\n\t\t\tport@0 {\n\t\t\t\treg = <0>;\n\t\t\t\tlabel = \"port1\";\n\t\t\t};\n\n\t\t\tport@1 {\n\t\t\t\treg = <1>;\n\t\t\t\tlabel = \"port2\";\n\t\t\t};\n\n\t\t\tport@2 {\n\t\t\t\treg = <2>;\n\t\t\t\tlabel = \"port3\";\n\t\t\t};\n\n\t\t\tport@3 {\n\t\t\t\treg = <3>;\n\t\t\t\tlabel = \"port4\";\n\t\t\t};\n\n\t\t\tport@5 {\n\t\t\t\treg = <5>;\n\t\t\t\tlabel = \"cpu\";\n\t\t\t\tphy-mode = \"rgmii-id\";\n\t\t\t\tethernet = <&eth0port>;\n\n\t\t\t\tfixed-link {\n\t\t\t\t\tspeed = <1000>;\n\t\t\t\t\tfull-duplex;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t};\n};\n\n&nand {\n\tstatus = \"okay\";\n\tpinctrl-0 = <&pmx_nand>;\n\tpinctrl-names = \"default\";\n\n\tpartition@0 {\n\t\tlabel = \"u-boot\";\n\t\treg = <0x00000000 0x000a0000>;\n\t\tread-only;\n\t};\n\n\tpartition@a0000 {\n\t\tlabel = \"u-boot-env\";\n\t\treg = <0x000a0000 0x00060000>;\n\t\tread-only;\n\t};\n\n\tpartition@100000 {\n\t\tlabel = \"kernel\";\n\t\treg = <0x00100000 0x00400000>;\n\t};\n\n\tpartition@500000 {\n\t\tlabel = \"ubi\";\n\t\treg = <0x00500000 0x1fb00000>;\n\t};\n};\n\n&pciec {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\tstatus = \"okay\";\n};\n\n&pinctrl {\n\tpinctrl-0 = <&pmx_sysrst>;\n\tpinctrl-names = \"default\";\n\n\tpmx_sysrst: pmx-sysrst {\n\t\tmarvell,pins = \"mpp6\";\n\t\tmarvell,function = \"sysrst\";\n\t};\n\n\tpmx_sdio_cd: pmx-sdio-cd {\n\t\tmarvell,pins = \"mpp28\";\n\t\tmarvell,function = \"gpio\";\n\t};\n\n\tpmx_led34: pmx_led34 {\n\t\tmarvell,pins = \"mpp34\";\n\t\tmarvell,function = \"gpio\";\n\t};\n\n\tpmx_led35: pmx_led35 {\n\t\tmarvell,pins = \"mpp35\";\n\t\tmarvell,function = \"gpio\";\n\t};\n\n\tpmx_led49: pmx_led49 {\n\t\tmarvell,pins = \"mpp49\";\n\t\tmarvell,function = \"gpio\";\n\t};\n};\n\n&rtc {\n\tstatus = \"okay\";\n};\n\n&sata_phy0 {\n\tstatus = \"disabled\";\n};\n\n&sata_phy1 {\n\tstatus = \"disabled\";\n};\n\n&sdio {\n\tpinctrl-0 = <&pmx_sdio_cd>;\n\tpinctrl-names = \"default\";\n\tstatus = \"okay\";\n\tcd-gpios = <&gpio0 28 9>;\n};\n\n&uart0 {\n\tstatus = \"okay\";\n};\n\n&usb0 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/kirkwood/files/arch/arm/boot/dts/kirkwood-c200-v1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later\n/*\n * Ctera C200 V1 Board Description\n * Copyright 2021 Pawel Dembicki <paweldembicki@gmail.com>\n */\n\n/dts-v1/;\n\n#include \"kirkwood.dtsi\"\n#include \"kirkwood-6281.dtsi\"\n\n/ {\n\tmodel = \"Ctera C200 V1\";\n\tcompatible = \"ctera,c200-v1\", \"marvell,kirkwood-88f6281\", \"marvell,kirkwood\";\n\n\taliases {\n\t\tled-boot = &led_status_green;\n\t\tled-failsafe = &led_status_red;\n\t\tled-running = &led_status_green;\n\t\tled-upgrade = &led_status_red;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200\";\n\t\tstdout-path = &uart0;\n\t};\n\n\tmemory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x00000000 0x20000000>;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\t\tpinctrl-0 = <&pmx_buttons>;\n\t\tpinctrl-names = \"default\";\n\n\t\tpower {\n\t\t\tlabel = \"Power Button\";\n\t\t\tlinux,code = <KEY_POWER>;\n\t\t\tgpios = <&gpio1 16 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"Reset Button\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio1 17 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tusb1 {\n\t\t\tlabel = \"USB1 Button\";\n\t\t\tlinux,code = <BTN_0>;\n\t\t\tgpios = <&gpio0 28 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tusb2 {\n\t\t\tlabel = \"USB2 Button\";\n\t\t\tlinux,code = <BTN_1>;\n\t\t\tgpios = <&gpio0 29 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tgpio-poweroff {\n\t\tcompatible = \"gpio-poweroff\";\n\t\tpinctrl-0 = <&pmx_poweroff>;\n\t\tpinctrl-names = \"default\";\n\t\tgpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tpinctrl-0 = <&pmx_leds>;\n\t\tpinctrl-names = \"default\";\n\n\t\tled_status_green: status-green {\n\t\t\tlabel = \"green:status\";\n\t\t\tgpios = <&gpio1 7 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_status_red: status-red {\n\t\t\tlabel = \"red:status\";\n\t\t\tgpios = <&gpio1 6 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tcloud-blue {\n\t\t\tlabel = \"blue:cloud\";\n\t\t\tgpios = <&gpio1 8 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tdisk1-green {\n\t\t\tlabel = \"green:disk1\";\n\t\t\tgpios = <&gpio0 15 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"ata1\";\n\t\t};\n\n\t\tdisk1-red {\n\t\t\tlabel = \"red:disk1\";\n\t\t\tgpios = <&gpio0 17 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tdisk2-green {\n\t\t\tlabel = \"green:disk2\";\n\t\t\tgpios = <&gpio0 16 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"ata2\";\n\t\t};\n\n\t\tdisk2-red {\n\t\t\tlabel = \"red:disk2\";\n\t\t\tgpios = <&gpio0 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tdisk-fail-green {\n\t\t\tlabel = \"green:disk-fail\";\n\t\t\tgpios = <&gpio1 11 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tdisk-fail-red {\n\t\t\tlabel = \"red:disk-fail\";\n\t\t\tgpios = <&gpio1 10 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tusb1-green {\n\t\t\tlabel = \"green:usb1\";\n\t\t\tgpios = <&gpio1 13 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t\ttrigger-sources = <&hub_port2>;\n\t\t};\n\n\t\tusb1-red {\n\t\t\tlabel = \"red:usb1\";\n\t\t\tgpios = <&gpio1 12 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tusb2-green {\n\t\t\tlabel = \"green:usb2\";\n\t\t\tgpios = <&gpio1 15 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t\ttrigger-sources = <&hub_port1>;\n\t\t};\n\n\t\tusb2-red {\n\t\t\tlabel = \"red:usb2\";\n\t\t\tgpios = <&gpio1 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n};\n\n&eth0port {\n\tphy-handle = <&ethphy9>;\n};\n\n&i2c0 {\n\tstatus = \"okay\";\n\n\trtc@30 {\n\t\tcompatible = \"s35390a\";\n\t\treg = <0x30>;\n\t};\n\n\tlm63@4c {\n\t\tcompatible = \"national,lm63\";\n\t\treg = <0x4c>;\n\t};\n};\n\n&mdio {\n\tstatus = \"okay\";\n\n\tethphy9: ethernet-phy@9 {\n\t\treg = <9>;\n\t};\n};\n\n&nand {\n\tstatus = \"okay\";\n\tchip-delay = <40>;\n\n\tpartition@0 {\n\t\tlabel = \"uboot\";\n\t\treg = <0x0000000 0x200000>;\n\t};\n\n\tpartition@200000 {\n\t\tlabel = \"certificate\";\n\t\treg = <0x0200000 0x100000>;\n\t};\n\n\tpartition@300000 {\n\t\tlabel = \"preset_cfg\";\n\t\treg = <0x0300000 0x100000>;\n\t};\n\n\tpartition@400000 {\n\t\tlabel = \"dev_params\";\n\t\treg = <0x0400000 0x100000>;\n\t};\n\tpartition@500000 {\n\t\tlabel = \"active_bank\";\n\t\treg = <0x0500000 0x0100000>;\n\t};\n\n\tpartition@600000 {\n\t\tlabel = \"magic\";\n\t\treg = <0x0600000 0x0100000>;\n\t};\n\n\tpartition@700000 {\n\t\tlabel = \"bank1\";\n\t\treg = <0x0700000 0x2800000>;\n\t};\n\n\tpartition@2f00000 {\n\t\tlabel = \"bank2\";\n\t\treg = <0x2f00000 0x2800000>;\n\t};\n\n\t/* 0x5700000-0x5a00000 undefined in vendor firmware */\n\n\tpartition@5a00000 {\n\t\tlabel = \"reserved\";\n\t\treg = <0x5a00000 0x2000000>;\n\t};\n\n\tpartition@7a00000 {\n\t\tlabel = \"ubi\";\n\t\treg = <0x7a00000 0x8600000>;\n\t};\n};\n\n&pciec {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\tstatus = \"okay\";\n};\n\n&pinctrl {\n\t/* buzzer gpios are connected to two pins of buzzer\n\t * leave it as is due lack of proper driver\n\t */\n\tpmx_buzzer: pmx-buzzer {\n\t\tmarvell,pins = \"mpp12\", \"mpp13\";\n\t\tmarvell,function = \"gpio\";\n\t};\n\n\tpmx_leds: pmx-leds {\n\t\tmarvell,pins = \"mpp14\", \"mpp15\", \"mpp16\", \"mpp17\", \"mpp38\",\n\t\t\t       \"mpp39\", \"mpp40\", \"mpp42\", \"mpp43\", \"mpp44\",\n\t\t\t       \"mpp45\", \"mpp46\", \"mpp47\";\n\t\tmarvell,function = \"gpio\";\n\t};\n\n\tpmx_buttons: pmx-buttons {\n\t\tmarvell,pins = \"mpp28\", \"mpp29\", \"mpp48\", \"mpp49\";\n\t\tmarvell,function = \"gpio\";\n\t};\n\n\tpmx_poweroff: pmx-poweroff {\n\t\tmarvell,pins = \"mpp34\";\n\t\tmarvell,function = \"gpio\";\n\t};\n};\n\n&rtc {\n\tstatus = \"disabled\";\n};\n\n&sata {\n\tstatus = \"okay\";\n\tnr-ports = <2>;\n};\n\n&uart0 {\n\tstatus = \"okay\";\n};\n\n&usb0 {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\tstatus = \"okay\";\n\n\tport@1 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <1>;\n\t\t#trigger-source-cells = <0>;\n\n\t\thub_port1: port@1 {\n\t\t\treg = <1>;\n\t\t\t#trigger-source-cells = <0>;\n\t\t};\n\n\t\thub_port2: port@2 {\n\t\t\treg = <2>;\n\t\t\t#trigger-source-cells = <0>;\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/kirkwood/files/arch/arm/boot/dts/kirkwood-e4200-v2.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"kirkwood-linksys-viper.dts\"\n\n/ {\n\tmodel = \"Linksys E4200 v2 (Viper)\";\n\tcompatible = \"linksys,e4200-v2\", \"linksys,viper\", \"marvell,kirkwood-88f6282\", \"marvell,kirkwood\";\n};\n"
  },
  {
    "path": "target/linux/kirkwood/files/arch/arm/boot/dts/kirkwood-ea3500.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-only\n/*\n * kirkwood-linksys-audi.dts - Device Tree file for Linksys EA3500\n *\n * (c) 2013 Jonas Gorski <jogo@openwrt.org>\n * (c) 2013 Deutsche Telekom Innovation Laboratories\n * (c) 2014 Luka Perkov <luka@openwrt.org>\n * (c) 2014 Dan Walters <dan@walters.io>\n *\n */\n\n/dts-v1/;\n\n#include \"kirkwood.dtsi\"\n#include \"kirkwood-6282.dtsi\"\n\n/ {\n\tmodel = \"Linksys EA3500 (Audi)\";\n\tcompatible = \"linksys,ea3500\", \"linksys,audi\", \"marvell,kirkwood-88f6282\", \"marvell,kirkwood\";\n\n\tmemory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x00000000 0x4000000>;\n\t};\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t\tserial0 = &uart0;\n\t};\n\n\tchosen {\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\tpinctrl-0 = <&pmx_btn_wps &pmx_btn_reset>;\n\t\tpinctrl-names = \"default\";\n\n\t\twps {\n\t\t\tlabel = \"WPS Button\";\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tgpios = <&gpio1 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"Reset Button\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio1 16 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tgpio-leds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tpinctrl-0 = <&pmx_led_green_power>;\n\t\tpinctrl-names = \"default\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"audi:green:power\";\n\t\t\tgpios = <&gpio0 7 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n};\n\n&pinctrl {\n\tpmx_led_green_power: pmx-led-green-power {\n\t\tmarvell,pins = \"mpp7\";\n\t\tmarvell,function = \"gpo\";\n\t};\n\n\tpmx_btn_wps: pmx-btn-wps {\n\t\tmarvell,pins = \"mpp47\";\n\t\tmarvell,function = \"gpio\";\n\t};\n\n\tpmx_btn_reset: pmx-btn-reset {\n\t\tmarvell,pins = \"mpp48\";\n\t\tmarvell,function = \"gpio\";\n\t};\n};\n\n&mdio {\n\tstatus = \"okay\";\n\n\tswitch@10 {\n\t\tcompatible = \"marvell,mv88e6085\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <16>;\n\n\t\tports {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\n\t\t\tport@0 {\n\t\t\t\treg = <0>;\n\t\t\t\tlabel = \"ethernet1\";\n\t\t\t};\n\n\t\t\tport@1 {\n\t\t\t\treg = <1>;\n\t\t\t\tlabel = \"ethernet2\";\n\t\t\t};\n\n\t\t\tport@2 {\n\t\t\t\treg = <2>;\n\t\t\t\tlabel = \"ethernet3\";\n\t\t\t};\n\n\t\t\tport@3 {\n\t\t\t\treg = <3>;\n\t\t\t\tlabel = \"ethernet4\";\n\t\t\t};\n\n\t\t\tport@4 {\n\t\t\t\treg = <4>;\n\t\t\t\tlabel = \"internet\";\n\t\t\t};\n\n\t\t\tport@5 {\n\t\t\t\treg = <5>;\n\t\t\t\tlabel = \"cpu\";\n\t\t\t\tethernet = <&eth0port>;\n\t\t\t\tfixed-link {\n\t\t\t\t\tspeed = <1000>;\n\t\t\t\t\tfull-duplex;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t};\n};\n\n&nand {\n\tstatus = \"okay\";\n\n\tpinctrl-0 = <&pmx_nand>;\n\tpinctrl-names = \"default\";\n\n\tpartitions {\n\t\tcompatible = \"fixed-partitions\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"u-boot\";\n\t\t\treg = <0x0 0x80000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@80000 {\n\t\t\tlabel = \"u_env\";\n\t\t\treg = <0x80000 0x4000>;\n\t\t};\n\n\t\tpartition@84000 {\n\t\t\tlabel = \"s_env\";\n\t\t\treg = <0x84000 0x4000>;\n\t\t};\n\n\t\tpartition@200000 {\n\t\t\tlabel = \"kernel1\";\n\t\t\treg = <0x200000 0x1400000>;\n\t\t};\n\n\t\tpartition@500000 {\n\t\t\tlabel = \"rootfs1\";\n\t\t\treg = <0x500000 0x1100000>;\n\t\t};\n\n\t\tpartition@1600000 {\n\t\t\tlabel = \"kernel2\";\n\t\t\treg = <0x1600000 0x1400000>;\n\t\t};\n\n\t\tpartition@1900000 {\n\t\t\tlabel = \"rootfs2\";\n\t\t\treg = <0x1900000 0x1100000>;\n\t\t};\n\n\t\tpartition@2a00000 {\n\t\t\tlabel = \"syscfg\";\n\t\t\treg = <0x2a00000  0x1600000>;\n\t\t};\n\n\t\tpartition@88000 {\n\t\t\tlabel = \"unused\";\n\t\t\treg = <0x88000 0x178000>;\n\t\t};\n\t};\n};\n\n&pciec {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\tstatus = \"okay\";\n};\n\n&pcie1 {\n\tstatus = \"okay\";\n};\n\n&mdio {\n\tstatus = \"okay\";\n};\n\n&uart0 {\n\tstatus = \"okay\";\n};\n\n/* eth0 is connected to a Marvell 88E6171 switch, without a PHY. So set\n * fixed speed and duplex.\n */\n&eth0 {\n\tstatus = \"okay\";\n\n\tethernet0-port@0 {\n\t\tspeed = <1000>;\n\t\tduplex = <1>;\n\t};\n};\n\n/* eth1 is connected to the switch at port 6. However DSA only supports a\n * single CPU port. This port is disabled to avoid confusion.\n */\n&eth1 {\n\tstatus = \"disabled\";\n};\n\n/* There is no battery on the board, so the RTC does not keep\n * time when there is no power, making it useless.\n */\n&rtc {\n\tstatus = \"disabled\";\n};\n"
  },
  {
    "path": "target/linux/kirkwood/files/arch/arm/boot/dts/kirkwood-ea4500.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"kirkwood-linksys-viper.dts\"\n\n/ {\n\tmodel = \"Linksys EA4500 (Viper)\";\n\tcompatible = \"linksys,ea4500\", \"linksys,viper\", \"marvell,kirkwood-88f6282\", \"marvell,kirkwood\";\n};\n"
  },
  {
    "path": "target/linux/kirkwood/files/arch/arm/boot/dts/kirkwood-goflexhome.dts",
    "content": "/dts-v1/;\n\n#include \"kirkwood.dtsi\"\n#include \"kirkwood-6281.dtsi\"\n\n/ {\n\tmodel = \"Seagate GoFlex Home\";\n\tcompatible = \"seagate,goflexhome\", \"marvell,kirkwood-88f6281\", \"marvell,kirkwood\";\n\n\taliases {\n\t\tled-boot = &led_health;\n\t\tled-failsafe = &led_fault;\n\t\tled-running = &led_health;\n\t\tled-upgrade = &led_fault;\n\t};\n\n\tmemory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x00000000 0x8000000>;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200n8 earlyprintk root=/dev/sda1 rootdelay=10\";\n\t\tstdout-path = &uart0;\n\t};\n\n\tocp@f1000000 {\n\t\tpinctrl: pin-controller@10000 {\n\t\t\tpmx_usb_power_enable: pmx-usb-power-enable {\n\t\t\t\tmarvell,pins = \"mpp29\";\n\t\t\t\tmarvell,function = \"gpio\";\n\t\t\t};\n\n\t\t\tpmx_led_white: pmx-led-white {\n\t\t\t\tmarvell,pins = \"mpp40\";\n\t\t\t\tmarvell,function = \"gpio\";\n\t\t\t};\n\n\t\t\tpmx_led_green: pmx-led_green {\n\t\t\t\tmarvell,pins = \"mpp46\";\n\t\t\t\tmarvell,function = \"gpio\";\n\t\t\t};\n\n\t\t\tpmx_led_orange: pmx-led-orange {\n\t\t\t\tmarvell,pins = \"mpp47\";\n\t\t\t\tmarvell,function = \"gpio\";\n\t\t\t};\n\t\t};\n\n\t\tserial@12000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tsata@80000 {\n\t\t\tstatus = \"okay\";\n\t\t\tnr-ports = <2>;\n\t\t};\n\t};\n\n\tgpio-leds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_health: health {\n\t\t\tlabel = \"status:green:health\";\n\t\t\tgpios = <&gpio1 14 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\tled_fault: fault {\n\t\t\tlabel = \"status:orange:fault\";\n\t\t\tgpios = <&gpio1 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tmisc {\n\t\t\tlabel = \"status:white:misc\";\n\t\t\tgpios = <&gpio1 8 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"disk-activity\";\n\t\t};\n\t};\n\n\tregulators {\n\t\tcompatible = \"simple-bus\";\n\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tpinctrl-0 = <&pmx_usb_power_enable>;\n\t\tpinctrl-names = \"default\";\n\n\t\tusb_power: regulator@1 {\n\t\t\tcompatible = \"regulator-fixed\";\n\t\t\treg = <1>;\n\t\t\tregulator-name = \"USB Power\";\n\t\t\tregulator-min-microvolt = <5000000>;\n\t\t\tregulator-max-microvolt = <5000000>;\n\t\t\tenable-active-high;\n\t\t\tregulator-always-on;\n\t\t\tregulator-boot-on;\n\t\t\tgpio = <&gpio0 29 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&nand {\n\tstatus = \"okay\";\n\n\tchip-delay = <40>;\n\n\tpartition@0 {\n\t\tlabel = \"u-boot\";\n\t\treg = <0x0000000 0x0100000>;\n\t\tread-only;\n\t};\n\n\tpartition@100000 {\n\t\tlabel = \"ubi\";\n\t\treg = <0x0100000 0xff00000>;\n\t};\n};\n\n&mdio {\n\tstatus = \"okay\";\n\n\tethphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tethernet0-port@0 {\n\t\tphy-handle = <&ethphy0>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/kirkwood/files/arch/arm/boot/dts/kirkwood-nas1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n/dts-v1/;\n\n#include \"kirkwood.dtsi\"\n#include \"kirkwood-6281.dtsi\"\n\n/ {\n\tmodel = \"ipTIME NAS1\";\n\tcompatible = \"iptime,nas1\", \"marvell,kirkwood-88f6281\", \"marvell,kirkwood\";\n\n\taliases {\n\t\tserial0 = &uart0;\n\t\tled-boot = &led_ready;\n\t\tled-failsafe = &led_ready;\n\t\tled-running = &led_ready;\n\t\tled-upgrade = &led_ready;\n\t};\n\n\tchosen {\n\t\t/*\n\t\t * \"root\" argument from the stock bootloader should be ignored\n\t\t * as it'll prevent the kernel from finding the correct rootfs.\n\t\t */\n\t\tbootargs-append = \" console=ttyS0,115200 root=\";\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\tmemory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x00000000 0x10000000>;\n\t};\n\n\tgpio-leds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tpinctrl-0 = <&pmx_led>;\n\t\tpinctrl-names = \"default\";\n\n\t\thdd {\n\t\t\tlabel = \"blue:hdd\";\n\t\t\tgpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"ata1\";\n\t\t};\n\n\t\tusb {\n\t\t\tlabel = \"blue:usb\";\n\t\t\tgpios = <&gpio1 13 GPIO_ACTIVE_LOW>;\n\t\t\ttrigger-sources = <&ehci_port1>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\n\t\tled_ready: ready {\n\t\t\tlabel = \"blue:ready\";\n\t\t\tgpios = <&gpio1 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\tpinctrl-0 = <&pmx_button>;\n\t\tpinctrl-names = \"default\";\n\n\t\treset-copy {\n\t\t\tlabel = \"Reset/Copy Button\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio1 12 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tpower {\n\t\t\tlabel = \"Power Button\";\n\t\t\tlinux,code = <KEY_POWER>;\n\t\t\tgpios = <&gpio1 16 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n\n\tgpio-fan {\n\t\tcompatible = \"gpio-fan\";\n\n\t\tpinctrl-0 = <&pmx_fan>;\n\t\tpinctrl-names = \"default\";\n\t\tgpios = <&gpio1  9 GPIO_ACTIVE_HIGH>,\n\t\t        <&gpio1 10 GPIO_ACTIVE_HIGH>;\n\t\t/* We don't know the exact rpm, just use dummy values here. */\n\t\tgpio-fan,speed-map = <0 0>, <1 1>, <2 2>;\n\t\t#cooling-cells = <2>;\n\t};\n\n\tgpio-poweroff {\n\t\tcompatible = \"gpio-poweroff\";\n\t\tgpios = <&pca9536 0 GPIO_ACTIVE_LOW>;\n\t};\n\n\tregulators {\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tpinctrl-0 = <&pmx_usb_vbus>;\n\t\tpinctrl-names = \"default\";\n\n\t\tregulator@1 {\n\t\t\tcompatible = \"regulator-fixed\";\n\t\t\treg = <1>;\n\t\t\tregulator-name = \"USB Power\";\n\t\t\tregulator-min-microvolt = <5000000>;\n\t\t\tregulator-max-microvolt = <5000000>;\n\t\t\tenable-active-high;\n\t\t\tregulator-always-on;\n\t\t\tgpio = <&gpio1 11 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&pinctrl {\n\tpmx_led: pmx-led {\n\t\tmarvell,pins = \"mpp35\", \"mpp45\", \"mpp46\";\n\t\tmarvell,function = \"gpio\";\n\t};\n\n\tpmx_fan: pmx-fan {\n\t\tmarvell,pins = \"mpp41\", \"mpp42\";\n\t\tmarvell,function = \"gpio\";\n\t};\n\n\tpmx_usb_vbus: pmx-usb-vbus {\n\t\tmarvell,pins = \"mpp43\";\n\t\tmarvell,function = \"gpio\";\n\t};\n\n\tpmx_button: pmx-button {\n\t\tmarvell,pins = \"mpp44\", \"mpp48\";\n\t\tmarvell,function = \"gpio\";\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <20000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x40000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tcompatible = \"openwrt,uimage\", \"denx,uimage\";\n\t\t\t\topenwrt,offset = <0x400>;\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x40000 0xf80000>;\n\t\t\t};\n\n\t\t\tpartition@fc0000 {\n\t\t\t\tlabel = \"config\";\n\t\t\t\treg = <0xfc0000 0x40000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&rtc {\n\tstatus = \"disabled\";\n};\n\n&i2c0 {\n\tstatus = \"okay\";\n\n\tpca9536: gpio@41 {\n\t\tcompatible = \"nxp,pca9536\";\n\t\treg = <0x41>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t};\n};\n\n&uart0 {\n\tstatus = \"okay\";\n};\n\n&usb0 {\n\tstatus = \"okay\";\n\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\n\tehci_port1: port@1 {\n\t\treg = <1>;\n\t\t#trigger-source-cells = <0>;\n\t};\n};\n\n&mdio {\n\tstatus = \"okay\";\n\n\tethphyb: ethernet-phy@b {\n\t\treg = <0x0b>;\n\t};\n};\n\n&eth1 {\n\tstatus = \"okay\";\n};\n\n&eth1port {\n\tphy-handle = <&ethphyb>;\n\tphy-connection-type = \"rgmii-id\";\n};\n\n&sata {\n\tstatus = \"okay\";\n\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\tnr-ports = <1>;\n\n\tsata-port@0 {\n\t\treg = <0>;\n\t\t#thermal-sensor-cells = <0>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/kirkwood/files/arch/arm/boot/dts/kirkwood-nsa310b.dts",
    "content": "/dts-v1/;\n\n#include \"kirkwood-nsa3x0-common.dtsi\"\n\n/*\n * There are at least two different NSA310 designs. This variant has\n * a red/green USB Led (same as nsa310) and a lm85 temp/fan controller.\n */\n\n/ {\n\tmodel = \"ZyXEL NSA310b\";\n\tcompatible = \"zyxel,nsa310b\", \"zyxel,nsa310\", \"marvell,kirkwood-88f6281\", \"marvell,kirkwood\";\n\n\taliases {\n\t\tled-boot = &led_green_sys;\n\t\tled-failsafe = &led_red_sys;\n\t\tled-running = &led_green_sys;\n\t\tled-upgrade = &led_red_sys;\n\t};\n\n\tmemory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x00000000 0x10000000>;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200\";\n\t\tstdout-path = &uart0;\n\t};\n\n\tocp@f1000000 {\n\t\tpinctrl: pin-controller@10000 {\n\t\t\tpinctrl-names = \"default\";\n\n\t\t\tpmx_led_esata_green: pmx-led-esata-green {\n\t\t\t\tmarvell,pins = \"mpp12\";\n\t\t\t\tmarvell,function = \"gpio\";\n\t\t\t};\n\n\t\t\tpmx_led_esata_red: pmx-led-esata-red {\n\t\t\t\tmarvell,pins = \"mpp13\";\n\t\t\t\tmarvell,function = \"gpio\";\n\t\t\t};\n\n\t\t\tpmx_led_usb_green: pmx-led-usb-green {\n\t\t\t\tmarvell,pins = \"mpp15\";\n\t\t\t\tmarvell,function = \"gpio\";\n\t\t\t};\n\n\t\t\tpmx_led_usb_red: pmx-led-usb-red {\n\t\t\t\tmarvell,pins = \"mpp16\";\n\t\t\t\tmarvell,function = \"gpio\";\n\t\t\t};\n\n\t\t\tpmx_led_sys_green: pmx-led-sys-green {\n\t\t\t\tmarvell,pins = \"mpp28\";\n\t\t\t\tmarvell,function = \"gpio\";\n\t\t\t};\n\n\t\t\tpmx_led_sys_red: pmx-led-sys-red {\n\t\t\t\tmarvell,pins = \"mpp29\";\n\t\t\t\tmarvell,function = \"gpio\";\n\t\t\t};\n\n\t\t\tpmx_led_hdd_green: pmx-led-hdd-green {\n\t\t\t\tmarvell,pins = \"mpp41\";\n\t\t\t\tmarvell,function = \"gpio\";\n\t\t\t};\n\n\t\t\tpmx_led_hdd_red: pmx-led-hdd-red {\n\t\t\t\tmarvell,pins = \"mpp42\";\n\t\t\t\tmarvell,function = \"gpio\";\n\t\t\t};\n\n\t\t};\n\n\t\ti2c@11000 {\n\t\t\tstatus = \"okay\";\n\n\t\t\tlm85: lm85@2e {\n\t\t\t\tcompatible = \"national,lm85\";\n\t\t\t\treg = <0x2e>;\n\t\t\t};\n\t\t};\n\t};\n\n\tgpio-leds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_green_sys: green-sys {\n\t\t\tlabel = \"nsa310:green:sys\";\n\t\t\tgpios = <&gpio0 28 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\tled_red_sys: red-sys {\n\t\t\tlabel = \"nsa310:red:sys\";\n\t\t\tgpios = <&gpio0 29 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tgreen-hdd {\n\t\t\tlabel = \"nsa310:green:hdd\";\n\t\t\tgpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"ata1\";\n\t\t};\n\n\t\tred-hdd {\n\t\t\tlabel = \"nsa310:red:hdd\";\n\t\t\tgpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tgreen-esata {\n\t\t\tlabel = \"nsa310:green:esata\";\n\t\t\tgpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"ata2\";\n\t\t};\n\n\t\tred-esata {\n\t\t\tlabel = \"nsa310:red:esata\";\n\t\t\tgpios = <&gpio0 13 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tgreen-usb {\n\t\t\tlabel = \"nsa310:green:usb\";\n\t\t\tgpios = <&gpio0 15 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"usb-host\";\n\t\t};\n\n\t\tred-usb {\n\t\t\tlabel = \"nsa310:red:usb\";\n\t\t\tgpios = <&gpio0 16 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tgreen-copy {\n\t\t\tlabel = \"nsa310:green:copy\";\n\t\t\tgpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tred-copy {\n\t\t\tlabel = \"nsa310:red:copy\";\n\t\t\tgpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/kirkwood/files/arch/arm/boot/dts/kirkwood-nsa310s.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-only\n/dts-v1/;\n\n#include \"kirkwood.dtsi\"\n#include \"kirkwood-6281.dtsi\"\n\n/ {\n\tmodel = \"ZyXEL NSA310S\";\n\tcompatible = \"zyxel,nsa310s\", \"marvell,kirkwood-88f6702\", \"marvell,kirkwood\";\n\n\taliases {\n\t\tled-boot = &led_green_sys;\n\t\tled-failsafe = &led_red_sys;\n\t\tled-running = &led_green_sys;\n\t\tled-upgrade = &led_red_sys;\n\t};\n\n\tmemory {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x00000000 0x10000000>;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200n8 earlyprintk\";\n\t\tstdout-path = &uart0;\n\t};\n\n\tocp@f1000000 {\n\t\tpinctrl: pin-controller@10000 {\n\t\t\tpinctrl-names = \"default\";\n\n\t\t\tpmx_usb_power: pmx-usb-power {\n\t\t\t\tmarvell,pins = \"mpp21\";\n\t\t\t\tmarvell,function = \"gpio\";\n\t\t\t};\n\n\t\t\tpmx_pwr_off: pmx-pwr-off {\n\t\t\t\tmarvell,pins = \"mpp27\";\n\t\t\t\tmarvell,function = \"gpio\";\n\t\t\t};\n\n\t\t\tpmx_btn_reset: pmx-btn-reset {\n\t\t\t\tmarvell,pins = \"mpp24\";\n\t\t\t\tmarvell,function = \"gpio\";\n\t\t\t};\n\n\t\t\tpmx_btn_copy: pmx-btn-copy {\n\t\t\t\tmarvell,pins = \"mpp25\";\n\t\t\t\tmarvell,function = \"gpio\";\n\t\t\t};\n\n\t\t\tpmx_btn_power: pmx-btn-power {\n\t\t\t\tmarvell,pins = \"mpp26\";\n\t\t\t\tmarvell,function = \"gpio\";\n\t\t\t};\n\n\t\t\tpmx_led_usb_green: pmx-led-usb-green {\n\t\t\t\tmarvell,pins = \"mpp15\";\n\t\t\t\tmarvell,function = \"gpio\";\n\t\t\t};\n\n\t\t\tpmx_led_copy_green: pmx-led-copy-green {\n\t\t\t\tmarvell,pins = \"mpp22\";\n\t\t\t\tmarvell,function = \"gpio\";\n\t\t\t};\n\n\t\t\tpmx_led_copy_red: pmx-led-copy-red {\n\t\t\t\tmarvell,pins = \"mpp23\";\n\t\t\t\tmarvell,function = \"gpio\";\n\t\t\t};\n\n\t\t\tpmx_led_sys_green: pmx-led-sys-green {\n\t\t\t\tmarvell,pins = \"mpp28\";\n\t\t\t\tmarvell,function = \"gpio\";\n\t\t\t};\n\n\t\t\tpmx_led_sys_red: pmx-led-sys-red {\n\t\t\t\tmarvell,pins = \"mpp29\";\n\t\t\t\tmarvell,function = \"gpio\";\n\t\t\t};\n\n\t\t\tpmx_led_hdd1_green: pmx-led-hdd1-green {\n\t\t\t\tmarvell,pins = \"mpp16\";\n\t\t\t\tmarvell,function = \"gpio\";\n\t\t\t};\n\n\t\t\tpmx_led_hdd1_red: pmx-led-hdd1-red {\n\t\t\t\tmarvell,pins = \"mpp13\";\n\t\t\t\tmarvell,function = \"gpio\";\n\t\t\t};\n\n\t\t\tpmx_pwr_sata1: pmx-pwr-sata1 {\n\t\t\t\tmarvell,pins = \"mpp33\";\n\t\t\t\tmarvell,function = \"gpio\";\n\t\t\t};\n\n\t\t};\n\n\t\ti2c@11000 {\n\t\t\tstatus = \"okay\";\n\n\t\t\trtc@68 {\n\t\t\t\tcompatible = \"htk,ht1382\";\n\t\t\t\treg = <0x68>;\n\t\t\t};\n\t\t};\n\n\t\tserial@12000 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\t};\n\n\tregulators {\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tpinctrl-0 = <&pmx_usb_power &pmx_pwr_sata1>;\n\t\tpinctrl-names = \"default\";\n\n\t\tusb0_power: regulator@1 {\n\t\t\tcompatible = \"regulator-fixed\";\n\t\t\treg = <1>;\n\t\t\tregulator-name = \"USB Power\";\n\t\t\tregulator-min-microvolt = <5000000>;\n\t\t\tregulator-max-microvolt = <5000000>;\n\t\t\tregulator-always-on;\n\t\t\tregulator-boot-on;\n\t\t\tgpio = <&gpio0 21 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tsata1_power: regulator@2 {\n\t\t\tcompatible = \"regulator-fixed\";\n\t\t\treg = <2>;\n\t\t\tregulator-name = \"SATA1 Power\";\n\t\t\tregulator-min-microvolt = <5000000>;\n\t\t\tregulator-max-microvolt = <5000000>;\n\t\t\tregulator-always-on;\n\t\t\tregulator-boot-on;\n\t\t\tgpio = <&gpio1 1 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tpinctrl-0 = <&pmx_btn_reset &pmx_btn_copy &pmx_btn_power>;\n\t\tpinctrl-names = \"default\";\n\n\t\tpower {\n\t\t\tlabel = \"Power Button\";\n\t\t\tlinux,code = <KEY_POWER>;\n\t\t\tgpios = <&gpio0 26 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tcopy {\n\t\t\tlabel = \"Copy Button\";\n\t\t\tlinux,code = <KEY_COPY>;\n\t\t\tgpios = <&gpio0 25 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"Reset Button\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio0 24 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_green_sys: green-sys {\n\t\t\tlabel = \"nsa310s:green:sys\";\n\t\t\tgpios = <&gpio0 28 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"default-on\";\n\t\t};\n\n\t\tled_red_sys: red-sys {\n\t\t\tlabel = \"nsa310s:red:sys\";\n\t\t\tgpios = <&gpio0 29 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tgreen-hdd1 {\n\t\t\tlabel = \"nsa310s:green:hdd1\";\n\t\t\tgpios = <&gpio0 16 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"ata1\";\n\t\t};\n\n\t\tred-hdd1 {\n\t\t\tlabel = \"nsa310s:red:hdd1\";\n\t\t\tgpios = <&gpio0 13 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tgreen-usb {\n\t\t\tlabel = \"nsa310s:green:usb\";\n\t\t\tgpios = <&gpio0 15 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"usb-host\";\n\t\t};\n\n\t\tgreen-copy {\n\t\t\tlabel = \"nsa310s:green:copy\";\n\t\t\tgpios = <&gpio0 22 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tred-copy {\n\t\t\tlabel = \"nsa310s:red:copy\";\n\t\t\tgpios = <&gpio0 23 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n\n\tgpio_poweroff {\n\t\tcompatible = \"gpio-poweroff\";\n\t\tpinctrl-0 = <&pmx_pwr_off>;\n\t\tpinctrl-names = \"default\";\n\t\tgpios = <&gpio0 27 GPIO_ACTIVE_HIGH>;\n\t};\n};\n\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tethernet0-port@0 {\n\t\tphy-handle = <&ethphy0>;\n\t};\n};\n\n&mdio {\n\tstatus = \"okay\";\n\n\tethphy0: ethernet-phy@1 {\n\t\treg = <1>;\n\t\tphy-mode = \"rgmii-id\";\n\t\tmarvell,reg-init = <0x1 0x16 0x0 0x3>,\n\t\t\t\t   <0x1 0x10 0x0 0x1017>,\n\t\t\t\t   <0x1 0x11 0x0 0x4408>,\n\t\t\t\t   <0x1 0x16 0x0 0x0>;\n\t};\n};\n\n&nand {\n\tstatus = \"okay\";\n\tchip-delay = <35>;\n\n\tpartition@0 {\n\t\tlabel = \"uboot\";\n\t\treg = <0x0000000 0x00c0000>;\n\t\tread-only;\n\t};\n\tpartition@c0000 {\n\t\tlabel = \"uboot_env\";\n\t\treg = <0x00c0000 0x0080000>;\n\t};\n\tpartition@140000 {\n\t\tlabel = \"ubi\";\n\t\treg = <0x0140000 0x7ec0000>;\n\t};\n};\n\n&pciec {\n        status = \"okay\";\n};\n\n&pcie0 {\n\tstatus = \"okay\";\n};\n\n&sata {\n\tstatus = \"okay\";\n\tnr-ports = <1>;\n};\n"
  },
  {
    "path": "target/linux/kirkwood/files/arch/arm/boot/dts/kirkwood-on100.dts",
    "content": "/dts-v1/;\n\n#include \"kirkwood.dtsi\"\n#include \"kirkwood-6282.dtsi\"\n\n/ {\n\tmodel = \"Cisco Systems ON100\";\n\tcompatible = \"cisco,on100\", \"marvell,kirkwood-88f6282\", \"marvell,kirkwood\";\n\n\tmemory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x00000000 0x20000000>;\n\t};\n\n\taliases {\n\t\tled-boot = &led_health_green;\n\t\tled-failsafe = &led_health_red;\n\t\tled-running = &led_health_green;\n\t\tled-upgrade = &led_health_red;\n\t\tserial0 = &uart0;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200n8 earlyprintk\";\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\tpinctrl-0 = <&pmx_btn_reset>;\n\t\tpinctrl-names = \"default\";\n\n\t\treset {\n\t\t\tlabel = \"Reset Button\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio1 9 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tgpio-leds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tpinctrl-0 = <&pmx_led_health_red &pmx_led_health_green>;\n\t\tpinctrl-names = \"default\";\n\n\t\tled_health_green: health-green {\n\t\t\tlabel = \"on100:green:health\";\n\t\t\tgpios = <&gpio1 12 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\tled_health_red: health-red {\n\t\t\tlabel = \"on100:red:health\";\n\t\t\tgpios = <&gpio1 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\thealth2-green {\n\t\t\tlabel = \"on100:green:health2\";\n\t\t\tgpios = <&gpio1 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\thealth2-red {\n\t\t\tlabel = \"on100:red:health2\";\n\t\t\tgpios = <&gpio1 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\n\tethernet0-port@0 {\n\t\tphy-handle = <&ethphy0>;\n\t\tphy-connection-type = \"rgmii-id\";\n\t};\n};\n\n&eth1 {\n\tstatus = \"okay\";\n\n\tethernet1-port@0 {\n\t\tphy-handle = <&ethphy1>;\n\t\tphy-connection-type = \"rgmii-id\";\n\t};\n};\n\n&mdio {\n\tstatus = \"okay\";\n\n\tethphy0: ethernet-phy@0 {\n\t\t/* Marvell 88E1121R */\n\t\tcompatible = \"ethernet-phy-id0141.0cb0\",\n\t\t\t     \"ethernet-phy-ieee802.3-c22\";\n\t\treg = <0>;\n\t};\n\n\tethphy1: ethernet-phy@1 {\n\t\t/* Marvell 88E1121R */\n\t\tcompatible = \"ethernet-phy-id0141.0cb0\",\n\t\t\t     \"ethernet-phy-ieee802.3-c22\";\n\t\treg = <1>;\n\t};\n};\n\n&nand {\n\tstatus = \"okay\";\n\n\tpartition@0 {\n\t\tlabel = \"u-boot\";\n\t\treg = <0x00000000 0x000a0000>;\n\t\tread-only;\n\t};\n\n\tpartition@a0000 {\n\t\tlabel = \"u-boot environment\";\n\t\treg = <0x000a0000 0x00020000>;\n\t\tread-only;\n\t};\n\n\tpartition@c0000 {\n\t\tlabel = \"kernel\";\n\t\treg = <0x000c0000 0x00540000>;\n\t};\n\n\tpartition@600000 {\n\t\tlabel = \"ubi\";\n\t\treg = <0x00600000 0x1fa00000>;\n\t};\n};\n\n&pinctrl {\n\tpmx_led_health_red: pmx-led-health-red {\n\t\tmarvell,pins = \"mpp45\";\n\t\tmarvell,function = \"gpio\";\n\t};\n\n\tpmx_led_health_green: pmx-led-health-green {\n\t\tmarvell,pins = \"mpp44\";\n\t\tmarvell,function = \"gpio\";\n\t};\n\n\tpmx_led_health2_red: pmx-led-health2-red {\n\t\tmarvell,pins = \"mpp47\";\n\t\tmarvell,function = \"gpio\";\n\t};\n\n\tpmx_led_health2_green: pmx-led-health2-green {\n\t\tmarvell,pins = \"mpp46\";\n\t\tmarvell,function = \"gpio\";\n\t};\n\n\tpmx_btn_reset: pmx-btn-reset {\n\t\tmarvell,pins = \"mpp31\";\n\t\tmarvell,function = \"gpio\";\n\t};\n};\n\n&sdio {\n\tstatus = \"okay\";\n};\n\n&uart0 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/kirkwood/image/Makefile",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2009-2013 OpenWrt.org\n\ninclude $(TOPDIR)/rules.mk\ninclude $(INCLUDE_DIR)/image.mk\n\nKERNEL_LOADADDR:=0x8000\n\n# Some info about Ctera firmware:\n# 1. It's simple tar file (GNU standard), but it must have \".firm\" suffix.\n# 2. It contains two images: kernel and romdisk. Both are required.\n# 3. Every image has header and trailer file.\n# 4. The struct of tar firmware is: header kernel trailer header romdisk trailer\n# 5. In header file are some strings used to describe image. It was decoded from\n#    factory image.\n# 6. Version format in header file is restricted by Original FW.\n# 7. Trailer file contains MD5 sum string of header and image file.\n# 8. Firmware file must have <=24MB size.\n\ndefine Build/ctera-firmware\n\tmkdir -p $@.tmp\n\n\t# Prepare header and trailer file for kernel\n\techo \"# CTera firmware information file\" > $@.tmp/header\n\techo \"image_type=kernel\" >> $@.tmp/header\n\techo \"arch=Kirkwood\" >> $@.tmp/header\n\techo \"board=Any\" >> $@.tmp/header\n\techo \"version=3.1.22.30669\" >> $@.tmp/header\n\techo \"kernel_cmd=console=ttyS0,115200 earlyprintk\" >> $@.tmp/header\n\techo \"date=$$(date $(if $(SOURCE_DATE_EPOCH),-d@$(SOURCE_DATE_EPOCH)))\" \\\n\t\t>> $@.tmp/header\n\n\tcp $@ $@.tmp/kernel\n\n\techo \"MD5=$$(cat $@.tmp/header $@.tmp/kernel | $(MKHASH) md5)\" \\\n\t\t> $@.tmp/trailer\n\n\ttar $(if $(SOURCE_DATE_EPOCH),--mtime=\"@$(SOURCE_DATE_EPOCH)\") \\\n\t\t-H gnu -C $@.tmp -cf $@.tar header kernel trailer\n\n\t# Prepare header and trailer file for fake romdisk\n\techo \"# CTera firmware information file\" > $@.tmp/header\n\techo \"image_type=romdisk\" >> $@.tmp/header\n\techo \"initrd=yes\" >> $@.tmp/header\n\techo \"arch=Kirkwood\" >> $@.tmp/header\n\techo \"board=Any\" >> $@.tmp/header\n\techo \"version=3.1.22.30669\" >> $@.tmp/header\n\techo \"date=$$(date $(if $(SOURCE_DATE_EPOCH),-d@$(SOURCE_DATE_EPOCH)))\" \\\n\t\t>> $@.tmp/header\n\n\trm -f $@\n\ttouch $@\n\t$(call Build/append-uImage-fakehdr, ramdisk)\n\tcp $@ $@.tmp/romdisk\n\n\techo \"MD5=$$(cat $@.tmp/header $@.tmp/romdisk | $(MKHASH) md5)\" \\\n\t\t> $@.tmp/trailer\n\n\ttar $(if $(SOURCE_DATE_EPOCH),--mtime=\"@$(SOURCE_DATE_EPOCH)\") \\\n\t\t-H gnu -C $@.tmp -rf $@.tar header romdisk trailer\n\n\tmv $@.tar $@\n\trm -rf $@.tmp\nendef\n\ndefine Device/kernel-size-migration\n  DEVICE_COMPAT_VERSION := 2.0\n  DEVICE_COMPAT_MESSAGE := Partition design has changed compared to \\\n\tolder versions (up to 21.02) due to kernel size restrictions. \\\n\tUpgrade via sysupgrade mechanism is not possible, so new \\\n\tinstallation via factory style image is required.\nendef\n\ndefine Device/Default\n  PROFILES := Default\n  DEVICE_DTS = kirkwood-$(lastword $(subst _, ,$(1)))\n  KERNEL_DEPENDS = $$(wildcard $(DTS_DIR)/$$(DEVICE_DTS).dts)\n  KERNEL := kernel-bin | append-dtb | uImage none\n  KERNEL_NAME := zImage\n  KERNEL_SUFFIX  := -uImage\n  KERNEL_IN_UBI := 1\n\n  PAGESIZE := 2048\n  SUBPAGESIZE := 512\n  BLOCKSIZE := 128k\n  IMAGES := sysupgrade.bin factory.bin\n  IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata\n  IMAGE/factory.bin := append-ubi\nendef\n\ndefine Device/checkpoint_l-50\n  DEVICE_VENDOR := Check Point\n  DEVICE_MODEL := L-50\n  DEVICE_PACKAGES := kmod-ath9k kmod-gpio-button-hotplug kmod-mvsdio \\\n\tkmod-rtc-s35390a kmod-usb-ledtrig-usbport wpad-basic-wolfssl\n  IMAGES := sysupgrade.bin\nendef\nTARGET_DEVICES += checkpoint_l-50\n\ndefine Device/cisco_on100\n  DEVICE_VENDOR := Cisco Systems\n  DEVICE_MODEL := ON100\n  KERNEL_SIZE := 5376k\n  KERNEL_IN_UBI :=\n  UBINIZE_OPTS := -E 5\n  IMAGE/factory.bin := append-kernel | pad-to $$$$(KERNEL_SIZE) | append-ubi\n  DEVICE_PACKAGES := kmod-mvsdio\n  SUPPORTED_DEVICES += on100\nendef\nTARGET_DEVICES += cisco_on100\n\ndefine Device/cloudengines_pogoe02\n  DEVICE_VENDOR := Cloud Engines\n  DEVICE_MODEL := Pogoplug E02\n  DEVICE_DTS := kirkwood-pogo_e02\n  SUPPORTED_DEVICES += pogo_e02\nendef\nTARGET_DEVICES += cloudengines_pogoe02\n\ndefine Device/cloudengines_pogoplugv4\n  DEVICE_VENDOR := Cloud Engines\n  DEVICE_MODEL := Pogoplug V4\n  DEVICE_DTS := kirkwood-pogoplug-series-4\n  DEVICE_PACKAGES := kmod-ata-marvell-sata kmod-fs-ext4 kmod-mvsdio kmod-usb3 \\\n\tkmod-gpio-button-hotplug\nendef\nTARGET_DEVICES += cloudengines_pogoplugv4\n\ndefine Device/ctera_c200-v1\n  DEVICE_VENDOR := Ctera\n  DEVICE_MODEL := C200\n  DEVICE_VARIANT := V1\n  DEVICE_PACKAGES := kmod-ata-marvell-sata kmod-gpio-button-hotplug \\\n\tkmod-hwmon-lm63 kmod-rtc-s35390a kmod-usb-ledtrig-usbport\n  KERNEL := kernel-bin | append-dtb | uImage none | ctera-firmware\n  KERNEL_IN_UBI :=\n  KERNEL_SUFFIX := -factory.firm\n  IMAGES := sysupgrade.bin\nendef\nTARGET_DEVICES += ctera_c200-v1\n\ndefine Device/endian_4i-edge-200\n  DEVICE_VENDOR := Endian\n  DEVICE_MODEL := 4i Edge 200\n  DEVICE_ALT0_VENDOR := Endian\n  DEVICE_ALT0_MODEL := UTM Mini Firewall\n  DEVICE_PACKAGES := kmod-ath9k kmod-mvsdio wpad-basic-wolfssl\n  KERNEL_SIZE := 4096k\n  IMAGES := sysupgrade.bin\nendef\nTARGET_DEVICES += endian_4i-edge-200\n\ndefine Device/globalscale_sheevaplug\n  DEVICE_VENDOR := Globalscale\n  DEVICE_MODEL := Sheevaplug\n  DEVICE_PACKAGES := kmod-mvsdio\nendef\nTARGET_DEVICES += globalscale_sheevaplug\n\ndefine Device/iom_iconnect-1.1\n  DEVICE_VENDOR := Iomega\n  DEVICE_MODEL := Iconnect\n  DEVICE_DTS := kirkwood-iconnect\n  SUPPORTED_DEVICES += iconnect\nendef\nTARGET_DEVICES += iom_iconnect-1.1\n\ndefine Device/iom_ix2-200\n  DEVICE_VENDOR := Iomega\n  DEVICE_MODEL := StorCenter ix2-200\n  DEVICE_DTS := kirkwood-iomega_ix2_200\n  DEVICE_PACKAGES := kmod-ata-marvell-sata kmod-fs-ext4 \\\n\tkmod-gpio-button-hotplug kmod-hwmon-lm63\n  PAGESIZE := 512\n  SUBPAGESIZE := 256\n  BLOCKSIZE := 16k\n  KERNEL_SIZE := 3072k\n  KERNEL_IN_UBI :=\n  UBINIZE_OPTS := -E 5\n  IMAGE_SIZE := 31744k\n  IMAGE/factory.bin := append-kernel | pad-to $$$$(KERNEL_SIZE) | append-ubi | \\\n\tcheck-size\nendef\nTARGET_DEVICES += iom_ix2-200\n\ndefine Device/iptime_nas1\n  DEVICE_VENDOR := ipTIME\n  DEVICE_MODEL := NAS1\n  DEVICE_PACKAGES := kmod-ata-marvell-sata kmod-fs-ext4 \\\n\tkmod-gpio-button-hotplug kmod-gpio-pca953x kmod-hwmon-drivetemp \\\n\tkmod-hwmon-gpiofan kmod-usb-ledtrig-usbport -uboot-envtools\n  KERNEL := $$(KERNEL) | iptime-naspkg nas1\n  BLOCKSIZE := 256k\n  IMAGE_SIZE := 15872k\n  IMAGES := sysupgrade.bin\n  IMAGE/sysupgrade.bin := append-kernel | append-rootfs | pad-rootfs | \\\n\tcheck-size | append-metadata\nendef\nTARGET_DEVICES += iptime_nas1\n\ndefine Device/linksys\n  DEVICE_VENDOR := Linksys\n  DEVICE_PACKAGES := kmod-mwl8k wpad-basic-wolfssl kmod-gpio-button-hotplug\n  KERNEL_IN_UBI :=\n  UBINIZE_OPTS := -E 5\n  IMAGE/factory.bin := append-kernel | pad-to $$$$(KERNEL_SIZE) | append-ubi\nendef\n\ndefine Device/linksys_e4200-v2\n  $(Device/linksys)\n  $(Device/kernel-size-migration)\n  DEVICE_MODEL := E4200\n  DEVICE_VARIANT := v2\n  KERNEL_SIZE := 3072k\n  SUPPORTED_DEVICES += linksys,viper linksys-viper\nendef\nTARGET_DEVICES += linksys_e4200-v2\n\ndefine Device/linksys_ea3500\n  $(Device/linksys)\n  $(Device/kernel-size-migration)\n  DEVICE_MODEL := EA3500\n  PAGESIZE := 512\n  SUBPAGESIZE := 256\n  BLOCKSIZE := 16k\n  KERNEL_SIZE := 3072k\n  SUPPORTED_DEVICES += linksys,audi linksys-audi\nendef\nTARGET_DEVICES += linksys_ea3500\n\ndefine Device/linksys_ea4500\n  $(Device/linksys)\n  $(Device/kernel-size-migration)\n  DEVICE_MODEL := EA4500\n  KERNEL_SIZE := 3072k\n  SUPPORTED_DEVICES += linksys,viper linksys-viper\nendef\nTARGET_DEVICES += linksys_ea4500\n\ndefine Device/netgear_readynas-duo-v2\n  DEVICE_VENDOR := NETGEAR\n  DEVICE_MODEL := ReadyNAS Duo\n  DEVICE_VARIANT := v2\n  DEVICE_DTS := kirkwood-netgear_readynas_duo_v2\n  KERNEL_IN_UBI :=\n  IMAGES := sysupgrade.bin\n  DEVICE_PACKAGES := kmod-ata-marvell-sata kmod-fs-ext4 \\\n\tkmod-gpio-button-hotplug kmod-hwmon-g762 kmod-rtc-rs5c372a kmod-usb3\nendef\nTARGET_DEVICES += netgear_readynas-duo-v2\n\ndefine Device/raidsonic_ib-nas62x0\n  DEVICE_VENDOR := RaidSonic\n  DEVICE_MODEL := ICY BOX IB-NAS62x0\n  DEVICE_DTS := kirkwood-ib62x0\n  DEVICE_PACKAGES := kmod-ata-marvell-sata kmod-fs-ext4\n  SUPPORTED_DEVICES += ib62x0\nendef\nTARGET_DEVICES += raidsonic_ib-nas62x0\n\ndefine Device/seagate_blackarmor-nas220\n  DEVICE_VENDOR := Seagate\n  DEVICE_MODEL := Blackarmor NAS220\n  DEVICE_PACKAGES := kmod-hwmon-adt7475 kmod-fs-ext4 kmod-ata-marvell-sata \\\n\tmdadm kmod-gpio-button-hotplug\n  PAGESIZE := 512\n  SUBPAGESIZE := 256\n  BLOCKSIZE := 16k\n  UBINIZE_OPTS := -e 1\nendef\nTARGET_DEVICES += seagate_blackarmor-nas220\n\ndefine Device/seagate_dockstar\n  DEVICE_VENDOR := Seagate\n  DEVICE_MODEL := FreeAgent Dockstar\n  SUPPORTED_DEVICES += dockstar\nendef\nTARGET_DEVICES += seagate_dockstar\n\ndefine Device/seagate_goflexnet\n  DEVICE_VENDOR := Seagate\n  DEVICE_MODEL := GoFlexNet\n  DEVICE_PACKAGES := kmod-ata-marvell-sata kmod-fs-ext4\n  SUPPORTED_DEVICES += goflexnet\nendef\nTARGET_DEVICES += seagate_goflexnet\n\ndefine Device/seagate_goflexhome\n  DEVICE_VENDOR := Seagate\n  DEVICE_MODEL := GoFlexHome\n  DEVICE_PACKAGES := kmod-ata-marvell-sata kmod-fs-ext4\n  SUPPORTED_DEVICES += goflexhome\nendef\nTARGET_DEVICES += seagate_goflexhome\n\ndefine Device/zyxel_nsa310b\n  DEVICE_VENDOR := ZyXEL\n  DEVICE_MODEL := NSA310b\n  DEVICE_PACKAGES := kmod-ata-marvell-sata kmod-r8169 kmod-fs-ext4 \\\n\tkmod-gpio-button-hotplug kmod-hwmon-lm85\n  SUPPORTED_DEVICES += nsa310b\nendef\nTARGET_DEVICES += zyxel_nsa310b\n\ndefine Device/zyxel_nsa310s\n  DEVICE_VENDOR := ZyXEL\n  DEVICE_MODEL := NSA310S\n  DEVICE_PACKAGES := kmod-ata-marvell-sata kmod-fs-ext4 kmod-gpio-button-hotplug\nendef\nTARGET_DEVICES += zyxel_nsa310s\n\ndefine Device/zyxel_nsa325\n  DEVICE_VENDOR := ZyXEL\n  DEVICE_MODEL := NSA325\n  DEVICE_VARIANT := v1/v2\n  DEVICE_PACKAGES := kmod-ata-marvell-sata kmod-fs-ext4 \\\n\tkmod-gpio-button-hotplug kmod-rtc-pcf8563 kmod-usb3\n  SUPPORTED_DEVICES += nsa325\nendef\nTARGET_DEVICES += zyxel_nsa325\n\n$(eval $(call BuildImage))\n"
  },
  {
    "path": "target/linux/kirkwood/patches-5.10/100-ib62x0.patch",
    "content": "--- a/arch/arm/boot/dts/kirkwood-ib62x0.dts\n+++ b/arch/arm/boot/dts/kirkwood-ib62x0.dts\n@@ -6,7 +6,14 @@\n \n / {\n \tmodel = \"RaidSonic ICY BOX IB-NAS62x0 (Rev B)\";\n-\tcompatible = \"raidsonic,ib-nas6210-b\", \"raidsonic,ib-nas6220-b\", \"raidsonic,ib-nas6210\", \"raidsonic,ib-nas6220\", \"raidsonic,ib-nas62x0\", \"marvell,kirkwood-88f6281\", \"marvell,kirkwood\";\n+\tcompatible = \"raidsonic,ib-nas62x0\", \"marvell,kirkwood-88f6281\", \"marvell,kirkwood\";\n+\n+\taliases {\n+\t\tled-boot = &led_green_os;\n+\t\tled-failsafe = &led_red_os;\n+\t\tled-running = &led_green_os;\n+\t\tled-upgrade = &led_red_os;\n+\t};\n \n \tmemory {\n \t\tdevice_type = \"memory\";\n@@ -81,12 +88,12 @@\n \t\t\t     &pmx_led_usb_transfer>;\n \t\tpinctrl-names = \"default\";\n \n-\t\tgreen-os {\n+\t\tled_green_os: green-os {\n \t\t\tlabel = \"ib62x0:green:os\";\n \t\t\tgpios = <&gpio0 25 GPIO_ACTIVE_HIGH>;\n-\t\t\tdefault-state = \"keep\";\n+\t\t\tdefault-state = \"on\";\n \t\t};\n-\t\tred-os {\n+\t\tled_red_os: red-os {\n \t\t\tlabel = \"ib62x0:red:os\";\n \t\t\tgpios = <&gpio0 22 GPIO_ACTIVE_HIGH>;\n \t\t};\n@@ -118,13 +125,13 @@\n \t};\n \n \tpartition@100000 {\n-\t\tlabel = \"uImage\";\n-\t\treg = <0x0100000 0x600000>;\n+\t\tlabel = \"second stage u-boot\";\n+\t\treg = <0x100000 0x200000>;\n \t};\n \n-\tpartition@700000 {\n-\t\tlabel = \"root\";\n-\t\treg = <0x0700000 0xf900000>;\n+\tpartition@200000 {\n+\t\tlabel = \"ubi\";\n+\t\treg = <0x200000 0xfe00000>;\n \t};\n \n };\n"
  },
  {
    "path": "target/linux/kirkwood/patches-5.10/101-iconnect.patch",
    "content": "--- a/arch/arm/boot/dts/kirkwood-iconnect.dts\n+++ b/arch/arm/boot/dts/kirkwood-iconnect.dts\n@@ -8,6 +8,13 @@\n \tmodel = \"Iomega Iconnect\";\n \tcompatible = \"iom,iconnect-1.1\", \"iom,iconnect\", \"marvell,kirkwood-88f6281\", \"marvell,kirkwood\";\n \n+\taliases {\n+\t\tled-boot = &led_power_blue;\n+\t\tled-failsafe = &led_power_red;\n+\t\tled-running = &led_power_blue;\n+\t\tled-upgrade = &led_power_red;\n+\t};\n+\n \tmemory {\n \t\tdevice_type = \"memory\";\n \t\treg = <0x00000000 0x10000000>;\n@@ -16,8 +23,6 @@\n \tchosen {\n \t\tbootargs = \"console=ttyS0,115200n8 earlyprintk\";\n \t\tstdout-path = &uart0;\n-\t\tlinux,initrd-start = <0x4500040>;\n-\t\tlinux,initrd-end   = <0x4800000>;\n \t};\n \n \tocp@f1000000 {\n@@ -89,12 +94,12 @@\n \t\t\tgpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;\n \t\t\tdefault-state = \"on\";\n \t\t};\n-\t\tpower-blue {\n+\t\tled_power_blue: power-blue {\n \t\t\tlabel = \"power:blue\";\n \t\t\tgpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;\n-\t\t\tdefault-state = \"keep\";\n+\t\t\tdefault-state = \"on\";\n \t\t};\n-\t\tpower-red {\n+\t\tled_power_red: power-red {\n \t\t\tlabel = \"power:red\";\n \t\t\tgpios = <&gpio1 11 GPIO_ACTIVE_HIGH>;\n \t\t};\n@@ -146,28 +151,23 @@\n \tstatus = \"okay\";\n \n \tpartition@0 {\n-\t\tlabel = \"uboot\";\n-\t\treg = <0x0000000 0xc0000>;\n+\t\tlabel = \"u-boot\";\n+\t\treg = <0x0000000 0xe0000>;\n \t};\n \n-\tpartition@a0000 {\n-\t\tlabel = \"env\";\n-\t\treg = <0xa0000 0x20000>;\n+\tpartition@e0000 {\n+\t\tlabel = \"u-boot environment\";\n+\t\treg = <0xe0000 0x100000>;\n \t};\n \n \tpartition@100000 {\n-\t\tlabel = \"zImage\";\n-\t\treg = <0x100000 0x300000>;\n-\t};\n-\n-\tpartition@540000 {\n-\t\tlabel = \"initrd\";\n-\t\treg = <0x540000 0x300000>;\n+\t\tlabel = \"second stage u-boot\";\n+\t\treg = <0x100000 0x200000>;\n \t};\n \n-\tpartition@980000 {\n-\t\tlabel = \"boot\";\n-\t\treg = <0x980000 0x1f400000>;\n+\tpartition@200000 {\n+\t\tlabel = \"ubi\";\n+\t\treg = <0x200000 0x1fe00000>;\n \t};\n };\n \n"
  },
  {
    "path": "target/linux/kirkwood/patches-5.10/102-dockstar.patch",
    "content": "--- a/arch/arm/boot/dts/kirkwood-dockstar.dts\n+++ b/arch/arm/boot/dts/kirkwood-dockstar.dts\n@@ -8,6 +8,13 @@\n \tmodel = \"Seagate FreeAgent Dockstar\";\n \tcompatible = \"seagate,dockstar\", \"marvell,kirkwood-88f6281\", \"marvell,kirkwood\";\n \n+\taliases {\n+\t\tled-boot = &led_health;\n+\t\tled-failsafe = &led_fault;\n+\t\tled-running = &led_health;\n+\t\tled-upgrade = &led_fault;\n+\t};\n+\n \tmemory {\n \t\tdevice_type = \"memory\";\n \t\treg = <0x00000000 0x8000000>;\n@@ -42,12 +49,12 @@\n \t\tpinctrl-0 = <&pmx_led_green &pmx_led_orange>;\n \t\tpinctrl-names = \"default\";\n \n-\t\thealth {\n+\t\tled_health: health {\n \t\t\tlabel = \"status:green:health\";\n \t\t\tgpios = <&gpio1 14 GPIO_ACTIVE_LOW>;\n-\t\t\tdefault-state = \"keep\";\n+\t\t\tdefault-state = \"on\";\n \t\t};\n-\t\tfault {\n+\t\tled_fault: fault {\n \t\t\tlabel = \"status:orange:fault\";\n \t\t\tgpios = <&gpio1 15 GPIO_ACTIVE_LOW>;\n \t\t};\n@@ -78,18 +85,22 @@\n \n \tpartition@0 {\n \t\tlabel = \"u-boot\";\n-\t\treg = <0x0000000 0x100000>;\n-\t\tread-only;\n+\t\treg = <0x0000000 0xe0000>;\n+\t};\n+\n+\tpartition@e0000 {\n+\t\tlabel = \"u-boot environment\";\n+\t\treg = <0xe0000 0x100000>;\n \t};\n \n \tpartition@100000 {\n-\t\tlabel = \"uImage\";\n-\t\treg = <0x0100000 0x400000>;\n+\t\tlabel = \"second stage u-boot\";\n+\t\treg = <0x100000 0x200000>;\n \t};\n \n-\tpartition@500000 {\n-\t\tlabel = \"data\";\n-\t\treg = <0x0500000 0xfb00000>;\n+\tpartition@200000 {\n+\t\tlabel = \"ubi\";\n+\t\treg = <0x200000 0xfe00000>;\n \t};\n };\n \n"
  },
  {
    "path": "target/linux/kirkwood/patches-5.10/103-iomega-ix2-200.patch",
    "content": "--- a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts\n+++ b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts\n@@ -8,6 +8,13 @@\n \tmodel = \"Iomega StorCenter ix2-200\";\n \tcompatible = \"iom,ix2-200\", \"marvell,kirkwood-88f6281\", \"marvell,kirkwood\";\n \n+\taliases {\n+\t\tled-boot = &led_power;\n+\t\tled-failsafe = &led_health;\n+\t\tled-running = &led_power;\n+\t\tled-upgrade = &led_health;\n+\t};\n+\n \tmemory {\n \t\tdevice_type = \"memory\";\n \t\treg = <0x00000000 0x10000000>;\n@@ -127,16 +134,16 @@\n \t\t\t      &pmx_led_rebuild &pmx_led_health >;\n \t\tpinctrl-names = \"default\";\n \n-\t\tpower_led {\n+\t\tled_power: power_led {\n \t\t\tlabel = \"status:white:power_led\";\n \t\t\tgpios = <&gpio0 16 GPIO_ACTIVE_HIGH>;\n-\t\t\tdefault-state = \"keep\";\n+\t\t\tdefault-state = \"on\";\n \t\t};\n \t\trebuild_led {\n \t\t\tlabel = \"status:white:rebuild_led\";\n \t\t\tgpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;\n \t\t};\n-\t\thealth_led {\n+\t\tled_health: health_led {\n \t\t\tlabel = \"status:red:health_led\";\n \t\t\tgpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;\n \t\t};\n@@ -186,18 +193,18 @@\n \t};\n \n \tpartition@a0000 {\n-\t\tlabel = \"env\";\n+\t\tlabel = \"u-boot environment\";\n \t\treg = <0xa0000 0x20000>;\n \t\tread-only;\n \t};\n \n \tpartition@100000 {\n-\t\tlabel = \"uImage\";\n+\t\tlabel = \"kernel\";\n \t\treg = <0x100000 0x300000>;\n \t};\n \n \tpartition@400000 {\n-\t\tlabel = \"rootfs\";\n+\t\tlabel = \"ubi\";\n \t\treg = <0x400000 0x1C00000>;\n \t};\n };\n@@ -211,7 +218,7 @@\n };\n \n &eth0 {\n-\tstatus = \"okay\";\n+\tstatus = \"disabled\";\n \tethernet0-port@0 {\n \t\tspeed = <1000>;\n \t\tduplex = <1>;\n"
  },
  {
    "path": "target/linux/kirkwood/patches-5.10/105-linksys-viper-dts.patch",
    "content": "--- a/arch/arm/boot/dts/kirkwood-linksys-viper.dts\n+++ b/arch/arm/boot/dts/kirkwood-linksys-viper.dts\n@@ -24,6 +24,10 @@\n \t};\n \n \taliases {\n+\t\tled-boot = &led_white_health;\n+\t\tled-failsafe = &led_white_health;\n+\t\tled-running = &led_white_health;\n+\t\tled-upgrade = &led_white_health;\n \t\tserial0 = &uart0;\n \t};\n \n@@ -56,9 +60,10 @@\n \t\tpinctrl-0 = < &pmx_led_white_health &pmx_led_white_pulse >;\n \t\tpinctrl-names = \"default\";\n \n-\t\twhite-health {\n+\t\tled_white_health: white-health {\n \t\t\tlabel = \"viper:white:health\";\n \t\t\tgpios = <&gpio0 7 GPIO_ACTIVE_HIGH>;\n+\t\t\tdefault-state = \"on\";\n \t\t};\n \n \t\twhite-pulse {\n@@ -114,23 +119,23 @@\n \t\t};\n \n \t\tpartition@200000 {\n-\t\t\tlabel = \"kernel\";\n-\t\t\treg = <0x200000 0x2A0000>;\n+\t\t\tlabel = \"kernel1\";\n+\t\t\treg = <0x200000 0x1A00000>;\n \t\t};\n \n-\t\tpartition@4a0000 {\n-\t\t\tlabel = \"rootfs\";\n-\t\t\treg = <0x4A0000 0x1760000>;\n+\t\tpartition@500000 {\n+\t\t\tlabel = \"rootfs1\";\n+\t\t\treg = <0x500000 0x1700000>;\n \t\t};\n \n \t\tpartition@1c00000 {\n-\t\t\tlabel = \"alt_kernel\";\n-\t\t\treg = <0x1C00000 0x2A0000>;\n+\t\t\tlabel = \"kernel2\";\n+\t\t\treg = <0x1C00000 0x1A00000>;\n \t\t};\n \n-\t\tpartition@1ea0000 {\n-\t\t\tlabel = \"alt_rootfs\";\n-\t\t\treg = <0x1EA0000 0x1760000>;\n+\t\tpartition@1f00000 {\n+\t\t\tlabel = \"rootfs2\";\n+\t\t\treg = <0x1F00000 0x1700000>;\n \t\t};\n \n \t\tpartition@3600000 {\n"
  },
  {
    "path": "target/linux/kirkwood/patches-5.10/106-goflexnet.patch",
    "content": "--- a/arch/arm/boot/dts/kirkwood-goflexnet.dts\n+++ b/arch/arm/boot/dts/kirkwood-goflexnet.dts\n@@ -8,6 +8,13 @@\n \tmodel = \"Seagate GoFlex Net\";\n \tcompatible = \"seagate,goflexnet\", \"marvell,kirkwood-88f6281\", \"marvell,kirkwood\";\n \n+\taliases {\n+\t\tled-boot = &led_health;\n+\t\tled-failsafe = &led_fault;\n+\t\tled-running = &led_health;\n+\t\tled-upgrade = &led_fault;\n+\t};\n+\n \tmemory {\n \t\tdevice_type = \"memory\";\n \t\treg = <0x00000000 0x8000000>;\n@@ -85,12 +92,12 @@\n \t\t\t    >;\n \t\tpinctrl-names = \"default\";\n \n-\t\thealth {\n+\t\tled_health: health {\n \t\t\tlabel = \"status:green:health\";\n \t\t\tgpios = <&gpio1 14 GPIO_ACTIVE_LOW>;\n-\t\t\tdefault-state = \"keep\";\n+\t\t\tdefault-state = \"on\";\n \t\t};\n-\t\tfault {\n+\t\tled_fault: fault {\n \t\t\tlabel = \"status:orange:fault\";\n \t\t\tgpios = <&gpio1 15 GPIO_ACTIVE_LOW>;\n \t\t};\n@@ -159,18 +166,8 @@\n \t};\n \n \tpartition@100000 {\n-\t\tlabel = \"uImage\";\n-\t\treg = <0x0100000 0x400000>;\n-\t};\n-\n-\tpartition@500000 {\n-\t\tlabel = \"pogoplug\";\n-\t\treg = <0x0500000 0x2000000>;\n-\t};\n-\n-\tpartition@2500000 {\n-\t\tlabel = \"root\";\n-\t\treg = <0x02500000 0xd800000>;\n+\t\tlabel = \"ubi\";\n+\t\treg = <0x0100000 0x0ff00000>;\n \t};\n };\n \n"
  },
  {
    "path": "target/linux/kirkwood/patches-5.10/107-01-zyxel-nsa3x0-common-nand-partitions.patch",
    "content": "--- a/arch/arm/boot/dts/kirkwood-nsa3x0-common.dtsi\n+++ b/arch/arm/boot/dts/kirkwood-nsa3x0-common.dtsi\n@@ -112,40 +112,16 @@\n \n \tpartition@0 {\n \t\tlabel = \"uboot\";\n-\t\treg = <0x0000000 0x0100000>;\n+\t\treg = <0x0000000 0x00c0000>;\n \t\tread-only;\n \t};\n \tpartition@100000 {\n \t\tlabel = \"uboot_env\";\n-\t\treg = <0x0100000 0x0080000>;\n+\t\treg = <0x00c0000 0x0080000>;\n \t};\n-\tpartition@180000 {\n-\t\tlabel = \"key_store\";\n-\t\treg = <0x0180000 0x0080000>;\n-\t};\n-\tpartition@200000 {\n-\t\tlabel = \"info\";\n-\t\treg = <0x0200000 0x0080000>;\n-\t};\n-\tpartition@280000 {\n-\t\tlabel = \"etc\";\n-\t\treg = <0x0280000 0x0a00000>;\n-\t};\n-\tpartition@c80000 {\n-\t\tlabel = \"kernel_1\";\n-\t\treg = <0x0c80000 0x0a00000>;\n-\t};\n-\tpartition@1680000 {\n-\t\tlabel = \"rootfs1\";\n-\t\treg = <0x1680000 0x2fc0000>;\n-\t};\n-\tpartition@4640000 {\n-\t\tlabel = \"kernel_2\";\n-\t\treg = <0x4640000 0x0a00000>;\n-\t};\n-\tpartition@5040000 {\n-\t\tlabel = \"rootfs2\";\n-\t\treg = <0x5040000 0x2fc0000>;\n+\tpartition@140000 {\n+\t\tlabel = \"ubi\";\n+\t\treg = <0x0140000 0x7ec0000>;\n \t};\n };\n \n"
  },
  {
    "path": "target/linux/kirkwood/patches-5.10/107-03-nsa325.patch",
    "content": "--- a/arch/arm/boot/dts/kirkwood-nsa325.dts\n+++ b/arch/arm/boot/dts/kirkwood-nsa325.dts\n@@ -15,6 +15,13 @@\n \tmodel = \"ZyXEL NSA325\";\n \tcompatible = \"zyxel,nsa325\", \"marvell,kirkwood-88f6282\", \"marvell,kirkwood\";\n \n+\taliases {\n+\t\tled-boot = &led_green_sys;\n+\t\tled-failsafe = &led_orange_sys;\n+\t\tled-running = &led_green_sys;\n+\t\tled-upgrade = &led_orange_sys;\n+\t};\n+\n \tmemory {\n \t\tdevice_type = \"memory\";\n \t\treg = <0x00000000 0x20000000>;\n@@ -162,17 +169,19 @@\n \t\t\t     &pmx_led_hdd1_green &pmx_led_hdd1_red>;\n \t\tpinctrl-names = \"default\";\n \n-\t\tgreen-sys {\n+\t\tled_green_sys: green-sys {\n \t\t\tlabel = \"nsa325:green:sys\";\n \t\t\tgpios = <&gpio0 28 GPIO_ACTIVE_HIGH>;\n+\t\t\tdefault-state = \"on\";\n \t\t};\n-\t\torange-sys {\n+\t\tled_orange_sys: orange-sys {\n \t\t\tlabel = \"nsa325:orange:sys\";\n \t\t\tgpios = <&gpio0 29 GPIO_ACTIVE_HIGH>;\n \t\t};\n \t\tgreen-hdd1 {\n \t\t\tlabel = \"nsa325:green:hdd1\";\n \t\t\tgpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;\n+\t\t\tlinux,default-trigger = \"ata1\";\n \t\t};\n \t\tred-hdd1 {\n \t\t\tlabel = \"nsa325:red:hdd1\";\n@@ -181,6 +190,7 @@\n \t\tgreen-hdd2 {\n \t\t\tlabel = \"nsa325:green:hdd2\";\n \t\t\tgpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;\n+\t\t\tlinux,default-trigger = \"ata2\";\n \t\t};\n \t\tred-hdd2 {\n \t\t\tlabel = \"nsa325:red:hdd2\";\n@@ -189,6 +199,7 @@\n \t\tgreen-usb {\n \t\t\tlabel = \"nsa325:green:usb\";\n \t\t\tgpios = <&gpio0 15 GPIO_ACTIVE_HIGH>;\n+\t\t\tlinux,default-trigger = \"usb-host\";\n \t\t};\n \t\tgreen-copy {\n \t\t\tlabel = \"nsa325:green:copy\";\n"
  },
  {
    "path": "target/linux/kirkwood/patches-5.10/109-pogoplug_v4.patch",
    "content": "--- a/arch/arm/boot/dts/kirkwood-pogoplug-series-4.dts\n+++ b/arch/arm/boot/dts/kirkwood-pogoplug-series-4.dts\n@@ -18,12 +18,20 @@\n \tcompatible = \"cloudengines,pogoplugv4\", \"marvell,kirkwood-88f6192\",\n \t\t     \"marvell,kirkwood\";\n \n+\taliases {\n+\t\tled-boot = &led_health;\n+\t\tled-failsafe = &led_fault;\n+\t\tled-running = &led_health;\n+\t\tled-upgrade = &led_fault;\n+\t};\n+\n \tmemory {\n \t\tdevice_type = \"memory\";\n \t\treg = <0x00000000 0x08000000>;\n \t};\n \n \tchosen {\n+\t\tbootargs = \"console=ttyS0,115200\";\n \t\tstdout-path = \"uart0:115200n8\";\n \t};\n \n@@ -37,8 +45,8 @@\n \t\teject {\n \t\t\tdebounce-interval = <50>;\n \t\t\twakeup-source;\n-\t\t\tlinux,code = <KEY_EJECTCD>;\n-\t\t\tlabel = \"Eject Button\";\n+\t\t\tlinux,code = <KEY_RESTART>;\n+\t\t\tlabel = \"Reset\";\n \t\t\tgpios = <&gpio0 29 GPIO_ACTIVE_LOW>;\n \t\t};\n \t};\n@@ -48,12 +56,12 @@\n \t\tpinctrl-0 = <&pmx_led_green &pmx_led_red>;\n \t\tpinctrl-names = \"default\";\n \n-\t\thealth {\n+\t\tled_health: health {\n \t\t\tlabel = \"pogoplugv4:green:health\";\n \t\t\tgpios = <&gpio0 22 GPIO_ACTIVE_LOW>;\n \t\t\tdefault-state = \"on\";\n \t\t};\n-\t\tfault {\n+\t\tled_fault: fault {\n \t\t\tlabel = \"pogoplugv4:red:fault\";\n \t\t\tgpios = <&gpio0 24 GPIO_ACTIVE_LOW>;\n \t\t};\n@@ -137,29 +145,19 @@\n \t\t#size-cells = <1>;\n \n \t\tpartition@0 {\n-\t\t\tlabel = \"u-boot\";\n-\t\t\treg = <0x00000000 0x200000>;\n+\t\t\tlabel = \"uboot\";\n+\t\t\treg = <0x00000000 0x1c0000>;\n \t\t\tread-only;\n \t\t};\n \n-\t\tpartition@200000 {\n-\t\t\tlabel = \"uImage\";\n-\t\t\treg = <0x00200000 0x300000>;\n-\t\t};\n-\n-\t\tpartition@500000 {\n-\t\t\tlabel = \"uImage2\";\n-\t\t\treg = <0x00500000 0x300000>;\n-\t\t};\n-\n-\t\tpartition@800000 {\n-\t\t\tlabel = \"failsafe\";\n-\t\t\treg = <0x00800000 0x800000>;\n+\t\tpartition@1c0000 {\n+\t\t\tlabel = \"uboot_env\";\n+\t\t\treg = <0x001c0000 0x40000>;\n \t\t};\n \n-\t\tpartition@1000000 {\n-\t\t\tlabel = \"root\";\n-\t\t\treg = <0x01000000 0x7000000>;\n+\t\tpartition@200000 {\n+\t\t\tlabel = \"ubi\";\n+\t\t\treg = <0x00200000 0x7e00000>;\n \t\t};\n \t};\n };\n"
  },
  {
    "path": "target/linux/kirkwood/patches-5.10/110-pogo_e02.patch",
    "content": "--- a/arch/arm/boot/dts/kirkwood-pogo_e02.dts\n+++ b/arch/arm/boot/dts/kirkwood-pogo_e02.dts\n@@ -20,6 +20,13 @@\n \tcompatible = \"cloudengines,pogoe02\", \"marvell,kirkwood-88f6281\",\n \t\t     \"marvell,kirkwood\";\n \n+\taliases {\n+\t\tled-boot = &led_health;\n+\t\tled-failsafe = &led_fault;\n+\t\tled-running = &led_health;\n+\t\tled-upgrade = &led_fault;\n+\t};\n+\n \tmemory {\n \t\tdevice_type = \"memory\";\n \t\treg = <0x00000000 0x10000000>;\n@@ -33,12 +40,12 @@\n \tgpio-leds {\n \t\tcompatible = \"gpio-leds\";\n \n-\t\thealth {\n+\t\tled_health: health {\n \t\t\tlabel = \"pogo_e02:green:health\";\n \t\t\tgpios = <&gpio1 16 GPIO_ACTIVE_LOW>;\n-\t\t\tdefault-state = \"keep\";\n+\t\t\tdefault-state = \"on\";\n \t\t};\n-\t\tfault {\n+\t\tled_fault: fault {\n \t\t\tlabel = \"pogo_e02:orange:fault\";\n \t\t\tgpios = <&gpio1 17 GPIO_ACTIVE_LOW>;\n \t\t};\n@@ -95,24 +102,24 @@\n \tstatus = \"okay\";\n \n \tpartition@0 {\n-\t\tlabel = \"u-boot\";\n-\t\treg = <0x0000000 0x100000>;\n+\t\tlabel = \"uboot\";\n+\t\treg = <0x0 0xe0000>;\n \t\tread-only;\n \t};\n \n-\tpartition@100000 {\n-\t\tlabel = \"uImage\";\n-\t\treg = <0x0100000 0x400000>;\n+\tpartition@e0000 {\n+\t\tlabel = \"uboot_env\";\n+\t\treg = <0xe0000 0x20000>;\n \t};\n \n-\tpartition@500000 {\n-\t\tlabel = \"pogoplug\";\n-\t\treg = <0x0500000 0x2000000>;\n+\tpartition@100000 {\n+\t\tlabel = \"second_stage_uboot\";\n+\t\treg = <0x100000 0x100000>;\n \t};\n \n-\tpartition@2500000 {\n-\t\tlabel = \"root\";\n-\t\treg = <0x02500000 0x5b00000>;\n+\tpartition@200000 {\n+\t\tlabel = \"ubi\";\n+\t\treg = <0x200000 0x7e00000>;\n \t};\n };\n \n"
  },
  {
    "path": "target/linux/kirkwood/patches-5.10/111-l-50.patch",
    "content": "--- a/arch/arm/boot/dts/kirkwood-l-50.dts\n+++ b/arch/arm/boot/dts/kirkwood-l-50.dts\n@@ -18,6 +18,13 @@\n \t\treg = <0x00000000 0x20000000>;\n \t};\n \n+\taliases {\n+\t\tled-boot = &led_status_green;\n+\t\tled-failsafe = &led_status_red;\n+\t\tled-running = &led_status_green;\n+\t\tled-upgrade = &led_status_red;\n+\t};\n+\n \tchosen {\n \t\tbootargs = \"console=ttyS0,115200n8\";\n \t\tstdout-path = &uart0;\n@@ -95,12 +102,12 @@\n \tleds {\n \t\tcompatible = \"gpio-leds\";\n \n-\t\tstatus_green {\n+\t\tled_status_green: status_green {\n \t\t\tlabel = \"l-50:green:status\";\n \t\t\tgpios = <&gpio1 6 GPIO_ACTIVE_LOW>;\n \t\t};\n \n-\t\tstatus_red {\n+\t\tled_status_red: status_red {\n \t\t\tlabel = \"l-50:red:status\";\n \t\t\tgpios = <&gpio3 2 GPIO_ACTIVE_LOW>;\n \t\t};\n@@ -349,13 +356,8 @@\n \t};\n \n \tpartition@100000 {\n-\t\tlabel = \"kernel-1\";\n-\t\treg = <0x00100000 0x00800000>;\n-\t};\n-\n-\tpartition@900000 {\n-\t\tlabel = \"rootfs-1\";\n-\t\treg = <0x00900000 0x07100000>;\n+\t\tlabel = \"ubi\";\n+\t\treg = <0x00100000 0x07900000>;\n \t};\n \n \tpartition@7a00000 {\n"
  },
  {
    "path": "target/linux/kirkwood/patches-5.10/112-sheevaplug.patch",
    "content": "--- a/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi\n+++ b/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi\n@@ -78,13 +78,8 @@\n \t};\n \n \tpartition@100000 {\n-\t\tlabel = \"uImage\";\n-\t\treg = <0x0100000 0x400000>;\n-\t};\n-\n-\tpartition@500000 {\n-\t\tlabel = \"root\";\n-\t\treg = <0x0500000 0x1fb00000>;\n+\t\tlabel = \"ubi\";\n+\t\treg = <0x0100000 0x1ff00000>;\n \t};\n };\n \n--- a/arch/arm/boot/dts/kirkwood-sheevaplug.dts\n+++ b/arch/arm/boot/dts/kirkwood-sheevaplug.dts\n@@ -13,6 +13,13 @@\n \tmodel = \"Globalscale Technologies SheevaPlug\";\n \tcompatible = \"globalscale,sheevaplug\", \"marvell,kirkwood-88f6281\", \"marvell,kirkwood\";\n \n+\taliases {\n+\t\tled-boot = &led_health;\n+\t\tled-failsafe = &led_health;\n+\t\tled-running = &led_health;\n+\t\tled-upgrade = &led_health;\n+\t};\n+\n \tocp@f1000000 {\n \t\tmvsdio@90000 {\n \t\t\tpinctrl-0 = <&pmx_sdio>;\n@@ -28,10 +35,10 @@\n \t\tpinctrl-0 = <&pmx_led_blue &pmx_led_red>;\n \t\tpinctrl-names = \"default\";\n \n-\t\thealth {\n+\t\tled_health: health {\n \t\t\tlabel = \"sheevaplug:blue:health\";\n \t\t\tgpios = <&gpio1 17 GPIO_ACTIVE_LOW>;\n-\t\t\tdefault-state = \"keep\";\n+\t\t\tdefault-state = \"on\";\n \t\t};\n \n \t\tmisc {\n"
  },
  {
    "path": "target/linux/kirkwood/patches-5.10/113-readynas_duo_v2.patch",
    "content": "--- a/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts\n+++ b/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts\n@@ -19,6 +19,13 @@\n \t\treg = <0x00000000 0x10000000>;\n \t};\n \n+\taliases {\n+\t\tled-boot = &led_power;\n+\t\tled-failsafe = &led_power;\n+\t\tled-running = &led_power;\n+\t\tled-upgrade = &led_power;\n+\t};\n+\n \tchosen {\n \t\tbootargs = \"console=ttyS0,115200n8 earlyprintk\";\n \t\tstdout-path = &uart0;\n@@ -115,7 +122,7 @@\n \t\t\t      &pmx_led_blue_backup >;\n \t\tpinctrl-names = \"default\";\n \n-\t\tpower_led {\n+\t\tled_power: power_led {\n \t\t\tlabel = \"status:blue:power_led\";\n \t\t\tgpios = <&gpio0 31 GPIO_ACTIVE_LOW>;\n \t\t\tdefault-state = \"keep\";\n@@ -129,11 +136,13 @@\n \t\tdisk1_led {\n \t\t\tlabel = \"status:blue:disk1_led\";\n \t\t\tgpios = <&gpio0 23 GPIO_ACTIVE_LOW>;\n+\t\t\tlinux,default-trigger = \"ata1\";\n \t\t};\n \n \t\tdisk2_led {\n \t\t\tlabel = \"status:blue:disk2_led\";\n \t\t\tgpios = <&gpio0 22 GPIO_ACTIVE_LOW>;\n+\t\t\tlinux,default-trigger = \"ata2\";\n \t\t};\n \n \t\tbackup_led {\n@@ -150,7 +159,13 @@\n \n \t\tpower-button {\n \t\t\tlabel = \"Power Button\";\n-\t\t\tlinux,code = <KEY_POWER>;\n+\t\t\t/* Power button and INT pin from PHY are both connected\n+\t\t\t * to this GPIO. Every network restart causes PHY restart\n+\t\t\t * and button is pressed. It's difficult to use it as\n+\t\t\t * KEY_POWER without changes in kernel (or netifd) so\n+\t\t\t * the button is configured as regular one.\n+\t\t\t */\n+\t\t\tlinux,code = <BTN_1>;\n \t\t\tgpios = <&gpio1 15 GPIO_ACTIVE_LOW>;\n \t\t};\n \n@@ -208,18 +223,13 @@\n \t};\n \n \tpartition@200000 {\n-\t\tlabel = \"uImage\";\n+\t\tlabel = \"kernel\";\n \t\treg = <0x0200000 0x600000>;\n \t};\n \n \tpartition@800000 {\n-\t\tlabel = \"minirootfs\";\n-\t\treg = <0x0800000 0x1000000>;\n-\t};\n-\n-\tpartition@1800000 {\n-\t\tlabel = \"jffs2\";\n-\t\treg = <0x1800000 0x6800000>;\n+\t\tlabel = \"ubi\";\n+\t\treg = <0x0800000 0x7800000>;\n \t};\n };\n \n"
  },
  {
    "path": "target/linux/kirkwood/patches-5.10/201-enable-sata-port-specific-led-triggers.patch",
    "content": "--- a/arch/arm/mach-mvebu/Kconfig\n+++ b/arch/arm/mach-mvebu/Kconfig\n@@ -116,6 +116,7 @@ config MACH_DOVE\n config MACH_KIRKWOOD\n \tbool \"Marvell Kirkwood boards\"\n \tdepends on ARCH_MULTI_V5\n+\tselect ARCH_WANT_LIBATA_LEDS\n \tselect CPU_FEROCEON\n \tselect GPIOLIB\n \tselect KIRKWOOD_CLK\n"
  },
  {
    "path": "target/linux/kirkwood/patches-5.10/202-linksys-find-active-root.patch",
    "content": "The WRT1900AC among other Linksys routers uses a dual-firmware layout.\nDynamically rename the active partition to \"ubi\".\n\nSigned-off-by: Imre Kaloz <kaloz@openwrt.org>\n---\n--- a/drivers/mtd/parsers/ofpart_core.c\n+++ b/drivers/mtd/parsers/ofpart_core.c\n@@ -38,6 +38,8 @@ static bool node_has_compatible(struct d\n \treturn of_get_property(pp, \"compatible\", NULL);\n }\n \n+static int mangled_rootblock;\n+\n static int parse_fixed_partitions(struct mtd_info *master,\n \t\t\t\t  const struct mtd_partition **pparts,\n \t\t\t\t  struct mtd_part_parser_data *data)\n@@ -47,6 +49,7 @@ static int parse_fixed_partitions(struct\n \tstruct mtd_partition *parts;\n \tstruct device_node *mtd_node;\n \tstruct device_node *ofpart_node;\n+\tconst char *owrtpart = \"ubi\";\n \tconst char *partname;\n \tstruct device_node *pp;\n \tint nr_parts, i, ret = 0;\n@@ -133,9 +136,15 @@ static int parse_fixed_partitions(struct\n \t\tparts[i].size = of_read_number(reg + a_cells, s_cells);\n \t\tparts[i].of_node = pp;\n \n-\t\tpartname = of_get_property(pp, \"label\", &len);\n-\t\tif (!partname)\n-\t\t\tpartname = of_get_property(pp, \"name\", &len);\n+\t\tif (mangled_rootblock && (i == mangled_rootblock)) {\n+\t\t\tpartname = owrtpart;\n+\t\t} else {\n+\t\t\tpartname = of_get_property(pp, \"label\", &len);\n+\n+\t\t\tif (!partname)\n+\t\t\t\tpartname = of_get_property(pp, \"name\", &len);\n+\t\t}\n+\n \t\tparts[i].name = partname;\n \n \t\tif (of_get_property(pp, \"read-only\", &len))\n@@ -252,6 +261,18 @@ static int __init ofpart_parser_init(voi\n \treturn 0;\n }\n \n+static int __init active_root(char *str)\n+{\n+\tget_option(&str, &mangled_rootblock);\n+\n+\tif (!mangled_rootblock)\n+\t\treturn 1;\n+\n+\treturn 1;\n+}\n+\n+__setup(\"mangled_rootblock=\", active_root);\n+\n static void __exit ofpart_parser_exit(void)\n {\n \tderegister_mtd_parser(&ofpart_parser);\n"
  },
  {
    "path": "target/linux/kirkwood/patches-5.10/203-blackarmor-nas220.patch",
    "content": "--- a/arch/arm/boot/dts/kirkwood-blackarmor-nas220.dts\n+++ b/arch/arm/boot/dts/kirkwood-blackarmor-nas220.dts\n@@ -17,6 +17,13 @@\n \tcompatible = \"seagate,blackarmor-nas220\",\"marvell,kirkwood-88f6192\",\n \t\t     \"marvell,kirkwood\";\n \n+\taliases {\n+\t\tled-boot = &led_status_amber;\n+\t\tled-failsafe = &led_status_amber;\n+\t\tled-running = &led_status_blue;\n+\t\tled-upgrade = &led_status_amber;\n+\t};\n+\n \tmemory { /* 128 MB */\n \t\tdevice_type = \"memory\";\n \t\treg = <0x00000000 0x8000000>;\n@@ -36,14 +43,14 @@\n \t\tcompatible = \"gpio-keys\";\n \n \t\treset {\n-\t\t\tlabel = \"Reset\";\n-\t\t\tlinux,code = <KEY_POWER>;\n+\t\t\tlabel = \"Reset Button\";\n+\t\t\tlinux,code = <KEY_RESTART>;\n \t\t\tgpios = <&gpio0 29 GPIO_ACTIVE_HIGH>;\n \t\t};\n \n-\t\tbutton {\n-\t\t\tlabel = \"Power\";\n-\t\t\tlinux,code = <KEY_SLEEP>;\n+\t\tpower {\n+\t\t\tlabel = \"Power Button\";\n+\t\t\tlinux,code = <KEY_POWER>;\n \t\t\tgpios = <&gpio0 26 GPIO_ACTIVE_LOW>;\n \t\t};\n \t};\n@@ -51,11 +58,27 @@\n \tgpio-leds {\n \t\tcompatible = \"gpio-leds\";\n \n-\t\tblue-power {\n+\t\tled_power_blue: power_blue {\n \t\t\tlabel = \"nas220:blue:power\";\n \t\t\tgpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;\n \t\t\tlinux,default-trigger = \"default-on\";\n \t\t};\n+\n+\t\tdisk_blue {\n+\t\t\tlabel = \"nas220:blue:disk\";\n+\t\t\tgpios = <&gpio0 16 GPIO_ACTIVE_LOW>;\n+\t\t\tlinux,default-trigger = \"disk-activity\";\n+\t\t};\n+\n+\t\tled_status_blue: status_blue {\n+\t\t\tlabel = \"nas220:blue:status\";\n+\t\t\tgpios = <&gpio0 23 GPIO_ACTIVE_HIGH>;\n+\t\t};\n+\n+\t\tled_status_amber: status_amber {\n+\t\t\tlabel = \"nas220:amber:status\";\n+\t\t\tgpios = <&gpio0 22 GPIO_ACTIVE_HIGH>;\n+\t\t};\n \t};\n \n \tregulators {\n@@ -153,6 +176,33 @@\n \n &nand {\n \tstatus = \"okay\";\n+\n+\tpartitions {\n+\t\tcompatible = \"fixed-partitions\";\n+\n+\t\tpartition@0 {\n+\t\t\tlabel = \"uboot\";\n+\t\t\treg = <0x0 0xa0000>;\n+\t\t\tread-only;\n+\t\t};\n+\n+\t\tpartition@a0000 {\n+\t\t\tlabel = \"uboot-env\";\n+\t\t\treg = <0xa0000 0x10000>;\n+\t\t\tread-only;\n+\t\t};\n+\n+\t\tpartition@b0000 {\n+\t\t\tlabel = \"reserved\";\n+\t\t\treg = <0xb0000 0x10000>;\n+\t\t\tread-only;\n+\t\t};\n+\n+\t\tpartition@c0000 {\n+\t\t\tlabel = \"ubi\";\n+\t\t\treg = <0xc0000 0x1e80000>;\n+\t\t};\n+\t};\n };\n \n &mdio {\n"
  },
  {
    "path": "target/linux/kirkwood/patches-5.10/800-power-reset-linkstation-poweroff-prepare-for-new-dev.patch",
    "content": "From 11cab9f5cd9390cd83747e579957c8f5b807c09c Mon Sep 17 00:00:00 2001\nFrom: Pawel Dembicki <paweldembicki@gmail.com>\nDate: Fri, 18 Jun 2021 12:37:27 +0200\nSubject: [PATCH 1/2] power: reset: linkstation-poweroff: prepare for new\n devices\n\nThis commit prepare driver for another device support.\n\nNew power_off_cfg structure describes two most important things: name of\nmdio bus and pointer to register setting function. It allow to add new\ndevice with different mdio bus node and other phy register config.\n\nSigned-off-by: Pawel Dembicki <paweldembicki@gmail.com>\n---\n drivers/power/reset/linkstation-poweroff.c | 35 ++++++++++++++++++----\n 1 file changed, 29 insertions(+), 6 deletions(-)\n\n--- a/drivers/power/reset/linkstation-poweroff.c\n+++ b/drivers/power/reset/linkstation-poweroff.c\n@@ -29,11 +29,21 @@\n #define LED2_FORCE_ON\t\t\t\t\t(0x8 << 8)\n #define LEDMASK\t\t\t\t\t\tGENMASK(11,8)\n \n+struct power_off_cfg {\n+\tchar *mdio_node_name;\n+\tvoid (*phy_set_reg)(bool restart);\n+};\n+\n static struct phy_device *phydev;\n+static const struct power_off_cfg *cfg;\n \n-static void mvphy_reg_intn(u16 data)\n+static void linkstation_mvphy_reg_intn(bool restart)\n {\n \tint rc = 0, saved_page;\n+\tu16 data = 0;\n+\n+\tif(restart)\n+\t\tdata = MII_88E1318S_PHY_LED_TCR_FORCE_INT;\n \n \tsaved_page = phy_select_page(phydev, MII_MARVELL_LED_PAGE);\n \tif (saved_page < 0)\n@@ -66,11 +76,16 @@ err:\n \t\tdev_err(&phydev->mdio.dev, \"Write register failed, %d\\n\", rc);\n }\n \n+static const struct power_off_cfg linkstation_power_off_cfg = {\n+\t.mdio_node_name = \"mdio\",\n+\t.phy_set_reg = linkstation_mvphy_reg_intn,\n+};\n+\n static int linkstation_reboot_notifier(struct notifier_block *nb,\n \t\t\t\t       unsigned long action, void *unused)\n {\n \tif (action == SYS_RESTART)\n-\t\tmvphy_reg_intn(MII_88E1318S_PHY_LED_TCR_FORCE_INT);\n+\t\tcfg->phy_set_reg(true);\n \n \treturn NOTIFY_DONE;\n }\n@@ -82,14 +97,18 @@ static struct notifier_block linkstation\n static void linkstation_poweroff(void)\n {\n \tunregister_reboot_notifier(&linkstation_reboot_nb);\n-\tmvphy_reg_intn(0);\n+\tcfg->phy_set_reg(false);\n \n \tkernel_restart(\"Power off\");\n }\n \n static const struct of_device_id ls_poweroff_of_match[] = {\n-\t{ .compatible = \"buffalo,ls421d\" },\n-\t{ .compatible = \"buffalo,ls421de\" },\n+\t{ .compatible = \"buffalo,ls421d\",\n+\t  .data = &linkstation_power_off_cfg,\n+\t},\n+\t{ .compatible = \"buffalo,ls421de\",\n+\t  .data = &linkstation_power_off_cfg,\n+\t},\n \t{ },\n };\n \n@@ -97,13 +116,17 @@ static int __init linkstation_poweroff_i\n {\n \tstruct mii_bus *bus;\n \tstruct device_node *dn;\n+\tconst struct of_device_id *match;\n \n \tdn = of_find_matching_node(NULL, ls_poweroff_of_match);\n \tif (!dn)\n \t\treturn -ENODEV;\n \tof_node_put(dn);\n \n-\tdn = of_find_node_by_name(NULL, \"mdio\");\n+\tmatch = of_match_node(ls_poweroff_of_match, dn);\n+\tcfg = match->data;\n+\n+\tdn = of_find_node_by_name(NULL, cfg->mdio_node_name);\n \tif (!dn)\n \t\treturn -ENODEV;\n \n"
  },
  {
    "path": "target/linux/kirkwood/patches-5.10/801-power-reset-linkstation-poweroff-add-new-device.patch",
    "content": "From a2d9c86df8d12646f5bf66920e4f1e6d940cfc62 Mon Sep 17 00:00:00 2001\nFrom: Pawel Dembicki <paweldembicki@gmail.com>\nDate: Fri, 18 Jun 2021 13:25:33 +0200\nSubject: [PATCH 2/2] power: reset: linkstation-poweroff: add new device\n\nThis commit introduces support for NETGEAR ReadyNAS Duo v2.\nThis device use bit 4 of LED[2:0] Polarity Control Register to indicate\nAC Power loss.\n\nFor more details about AC loss detection in NETGEAR ReadyNAS Duo v2,\nplease look at the file:\nRND_5.3.13_WW.src/u-boot/board/mv_feroceon/mv_hal/usibootup/usibootup.c\nfrom Netgear GPL sources.\n\nSigned-off-by: Pawel Dembicki <paweldembicki@gmail.com>\n---\n drivers/power/reset/linkstation-poweroff.c | 43 ++++++++++++++++++++++\n 1 file changed, 43 insertions(+)\n\n--- a/drivers/power/reset/linkstation-poweroff.c\n+++ b/drivers/power/reset/linkstation-poweroff.c\n@@ -19,6 +19,7 @@\n #define MII_MARVELL_PHY_PAGE\t\t22\n \n #define MII_PHY_LED_CTRL\t\t16\n+#define MII_PHY_LED_POL_CTRL\t\t17\n #define MII_88E1318S_PHY_LED_TCR\t18\n #define MII_88E1318S_PHY_WOL_CTRL\t16\n #define MII_M1011_IEVENT\t\t19\n@@ -29,6 +30,8 @@\n #define LED2_FORCE_ON\t\t\t\t\t(0x8 << 8)\n #define LEDMASK\t\t\t\t\t\tGENMASK(11,8)\n \n+#define MII_88E1318S_PHY_LED_POL_LED2\t\tBIT(4)\n+\n struct power_off_cfg {\n \tchar *mdio_node_name;\n \tvoid (*phy_set_reg)(bool restart);\n@@ -76,11 +79,48 @@ err:\n \t\tdev_err(&phydev->mdio.dev, \"Write register failed, %d\\n\", rc);\n }\n \n+static void readynas_mvphy_set_reg(bool restart)\n+{\n+\tint rc = 0, saved_page;\n+\tu16 data = 0;\n+\n+\tif(restart)\n+\t\tdata = MII_88E1318S_PHY_LED_POL_LED2;\n+\n+\tsaved_page = phy_select_page(phydev, MII_MARVELL_LED_PAGE);\n+\tif (saved_page < 0)\n+\t\tgoto err;\n+\n+\t/* Set the LED[2].0 Polarity bit to the required state */\n+\t__phy_modify(phydev, MII_PHY_LED_POL_CTRL,\n+\t\t     MII_88E1318S_PHY_LED_POL_LED2, data);\n+\n+\tif (!data) {\n+\n+\t\t/* If WOL was enabled and a magic packet was received before powering\n+\t\t * off, we won't be able to wake up by sending another magic packet.\n+\t\t * Clear WOL status.\n+\t\t */\n+\t\t__phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_MARVELL_WOL_PAGE);\n+\t\t__phy_set_bits(phydev, MII_88E1318S_PHY_WOL_CTRL,\n+\t\t\t       MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS);\n+\t}\n+err:\n+\trc = phy_restore_page(phydev, saved_page, rc);\n+\tif (rc < 0)\n+\t\tdev_err(&phydev->mdio.dev, \"Write register failed, %d\\n\", rc);\n+}\n+\n static const struct power_off_cfg linkstation_power_off_cfg = {\n \t.mdio_node_name = \"mdio\",\n \t.phy_set_reg = linkstation_mvphy_reg_intn,\n };\n \n+static const struct power_off_cfg readynas_power_off_cfg = {\n+\t.mdio_node_name = \"mdio-bus\",\n+\t.phy_set_reg = readynas_mvphy_set_reg,\n+};\n+\n static int linkstation_reboot_notifier(struct notifier_block *nb,\n \t\t\t\t       unsigned long action, void *unused)\n {\n@@ -109,6 +149,9 @@ static const struct of_device_id ls_powe\n \t{ .compatible = \"buffalo,ls421de\",\n \t  .data = &linkstation_power_off_cfg,\n \t},\n+\t{ .compatible = \"netgear,readynas-duo-v2\",\n+\t  .data = &readynas_power_off_cfg,\n+\t},\n \t{ },\n };\n \n"
  },
  {
    "path": "target/linux/kirkwood/patches-5.15/100-ib62x0.patch",
    "content": "--- a/arch/arm/boot/dts/kirkwood-ib62x0.dts\n+++ b/arch/arm/boot/dts/kirkwood-ib62x0.dts\n@@ -6,7 +6,14 @@\n \n / {\n \tmodel = \"RaidSonic ICY BOX IB-NAS62x0 (Rev B)\";\n-\tcompatible = \"raidsonic,ib-nas6210-b\", \"raidsonic,ib-nas6220-b\", \"raidsonic,ib-nas6210\", \"raidsonic,ib-nas6220\", \"raidsonic,ib-nas62x0\", \"marvell,kirkwood-88f6281\", \"marvell,kirkwood\";\n+\tcompatible = \"raidsonic,ib-nas62x0\", \"marvell,kirkwood-88f6281\", \"marvell,kirkwood\";\n+\n+\taliases {\n+\t\tled-boot = &led_green_os;\n+\t\tled-failsafe = &led_red_os;\n+\t\tled-running = &led_green_os;\n+\t\tled-upgrade = &led_red_os;\n+\t};\n \n \tmemory {\n \t\tdevice_type = \"memory\";\n@@ -81,12 +88,12 @@\n \t\t\t     &pmx_led_usb_transfer>;\n \t\tpinctrl-names = \"default\";\n \n-\t\tgreen-os {\n+\t\tled_green_os: green-os {\n \t\t\tlabel = \"ib62x0:green:os\";\n \t\t\tgpios = <&gpio0 25 GPIO_ACTIVE_HIGH>;\n-\t\t\tdefault-state = \"keep\";\n+\t\t\tdefault-state = \"on\";\n \t\t};\n-\t\tred-os {\n+\t\tled_red_os: red-os {\n \t\t\tlabel = \"ib62x0:red:os\";\n \t\t\tgpios = <&gpio0 22 GPIO_ACTIVE_HIGH>;\n \t\t};\n@@ -118,13 +125,13 @@\n \t};\n \n \tpartition@100000 {\n-\t\tlabel = \"uImage\";\n-\t\treg = <0x0100000 0x600000>;\n+\t\tlabel = \"second stage u-boot\";\n+\t\treg = <0x100000 0x200000>;\n \t};\n \n-\tpartition@700000 {\n-\t\tlabel = \"root\";\n-\t\treg = <0x0700000 0xf900000>;\n+\tpartition@200000 {\n+\t\tlabel = \"ubi\";\n+\t\treg = <0x200000 0xfe00000>;\n \t};\n \n };\n"
  },
  {
    "path": "target/linux/kirkwood/patches-5.15/101-iconnect.patch",
    "content": "--- a/arch/arm/boot/dts/kirkwood-iconnect.dts\n+++ b/arch/arm/boot/dts/kirkwood-iconnect.dts\n@@ -8,6 +8,13 @@\n \tmodel = \"Iomega Iconnect\";\n \tcompatible = \"iom,iconnect-1.1\", \"iom,iconnect\", \"marvell,kirkwood-88f6281\", \"marvell,kirkwood\";\n \n+\taliases {\n+\t\tled-boot = &led_power_blue;\n+\t\tled-failsafe = &led_power_red;\n+\t\tled-running = &led_power_blue;\n+\t\tled-upgrade = &led_power_red;\n+\t};\n+\n \tmemory {\n \t\tdevice_type = \"memory\";\n \t\treg = <0x00000000 0x10000000>;\n@@ -16,8 +23,6 @@\n \tchosen {\n \t\tbootargs = \"console=ttyS0,115200n8 earlyprintk\";\n \t\tstdout-path = &uart0;\n-\t\tlinux,initrd-start = <0x4500040>;\n-\t\tlinux,initrd-end   = <0x4800000>;\n \t};\n \n \tocp@f1000000 {\n@@ -89,12 +94,12 @@\n \t\t\tgpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;\n \t\t\tdefault-state = \"on\";\n \t\t};\n-\t\tpower-blue {\n+\t\tled_power_blue: power-blue {\n \t\t\tlabel = \"power:blue\";\n \t\t\tgpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;\n-\t\t\tdefault-state = \"keep\";\n+\t\t\tdefault-state = \"on\";\n \t\t};\n-\t\tpower-red {\n+\t\tled_power_red: power-red {\n \t\t\tlabel = \"power:red\";\n \t\t\tgpios = <&gpio1 11 GPIO_ACTIVE_HIGH>;\n \t\t};\n@@ -146,28 +151,23 @@\n \tstatus = \"okay\";\n \n \tpartition@0 {\n-\t\tlabel = \"uboot\";\n-\t\treg = <0x0000000 0xc0000>;\n+\t\tlabel = \"u-boot\";\n+\t\treg = <0x0000000 0xe0000>;\n \t};\n \n-\tpartition@a0000 {\n-\t\tlabel = \"env\";\n-\t\treg = <0xa0000 0x20000>;\n+\tpartition@e0000 {\n+\t\tlabel = \"u-boot environment\";\n+\t\treg = <0xe0000 0x100000>;\n \t};\n \n \tpartition@100000 {\n-\t\tlabel = \"zImage\";\n-\t\treg = <0x100000 0x300000>;\n-\t};\n-\n-\tpartition@540000 {\n-\t\tlabel = \"initrd\";\n-\t\treg = <0x540000 0x300000>;\n+\t\tlabel = \"second stage u-boot\";\n+\t\treg = <0x100000 0x200000>;\n \t};\n \n-\tpartition@980000 {\n-\t\tlabel = \"boot\";\n-\t\treg = <0x980000 0x1f400000>;\n+\tpartition@200000 {\n+\t\tlabel = \"ubi\";\n+\t\treg = <0x200000 0x1fe00000>;\n \t};\n };\n \n"
  },
  {
    "path": "target/linux/kirkwood/patches-5.15/102-dockstar.patch",
    "content": "--- a/arch/arm/boot/dts/kirkwood-dockstar.dts\n+++ b/arch/arm/boot/dts/kirkwood-dockstar.dts\n@@ -8,6 +8,13 @@\n \tmodel = \"Seagate FreeAgent Dockstar\";\n \tcompatible = \"seagate,dockstar\", \"marvell,kirkwood-88f6281\", \"marvell,kirkwood\";\n \n+\taliases {\n+\t\tled-boot = &led_health;\n+\t\tled-failsafe = &led_fault;\n+\t\tled-running = &led_health;\n+\t\tled-upgrade = &led_fault;\n+\t};\n+\n \tmemory {\n \t\tdevice_type = \"memory\";\n \t\treg = <0x00000000 0x8000000>;\n@@ -42,12 +49,12 @@\n \t\tpinctrl-0 = <&pmx_led_green &pmx_led_orange>;\n \t\tpinctrl-names = \"default\";\n \n-\t\thealth {\n+\t\tled_health: health {\n \t\t\tlabel = \"status:green:health\";\n \t\t\tgpios = <&gpio1 14 GPIO_ACTIVE_LOW>;\n-\t\t\tdefault-state = \"keep\";\n+\t\t\tdefault-state = \"on\";\n \t\t};\n-\t\tfault {\n+\t\tled_fault: fault {\n \t\t\tlabel = \"status:orange:fault\";\n \t\t\tgpios = <&gpio1 15 GPIO_ACTIVE_LOW>;\n \t\t};\n@@ -78,18 +85,22 @@\n \n \tpartition@0 {\n \t\tlabel = \"u-boot\";\n-\t\treg = <0x0000000 0x100000>;\n-\t\tread-only;\n+\t\treg = <0x0000000 0xe0000>;\n+\t};\n+\n+\tpartition@e0000 {\n+\t\tlabel = \"u-boot environment\";\n+\t\treg = <0xe0000 0x100000>;\n \t};\n \n \tpartition@100000 {\n-\t\tlabel = \"uImage\";\n-\t\treg = <0x0100000 0x400000>;\n+\t\tlabel = \"second stage u-boot\";\n+\t\treg = <0x100000 0x200000>;\n \t};\n \n-\tpartition@500000 {\n-\t\tlabel = \"data\";\n-\t\treg = <0x0500000 0xfb00000>;\n+\tpartition@200000 {\n+\t\tlabel = \"ubi\";\n+\t\treg = <0x200000 0xfe00000>;\n \t};\n };\n \n"
  },
  {
    "path": "target/linux/kirkwood/patches-5.15/103-iomega-ix2-200.patch",
    "content": "--- a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts\n+++ b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts\n@@ -8,6 +8,13 @@\n \tmodel = \"Iomega StorCenter ix2-200\";\n \tcompatible = \"iom,ix2-200\", \"marvell,kirkwood-88f6281\", \"marvell,kirkwood\";\n \n+\taliases {\n+\t\tled-boot = &led_power;\n+\t\tled-failsafe = &led_health;\n+\t\tled-running = &led_power;\n+\t\tled-upgrade = &led_health;\n+\t};\n+\n \tmemory {\n \t\tdevice_type = \"memory\";\n \t\treg = <0x00000000 0x10000000>;\n@@ -127,16 +134,16 @@\n \t\t\t      &pmx_led_rebuild &pmx_led_health >;\n \t\tpinctrl-names = \"default\";\n \n-\t\tpower_led {\n+\t\tled_power: power_led {\n \t\t\tlabel = \"status:white:power_led\";\n \t\t\tgpios = <&gpio0 16 GPIO_ACTIVE_HIGH>;\n-\t\t\tdefault-state = \"keep\";\n+\t\t\tdefault-state = \"on\";\n \t\t};\n \t\trebuild_led {\n \t\t\tlabel = \"status:white:rebuild_led\";\n \t\t\tgpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;\n \t\t};\n-\t\thealth_led {\n+\t\tled_health: health_led {\n \t\t\tlabel = \"status:red:health_led\";\n \t\t\tgpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;\n \t\t};\n@@ -186,18 +193,18 @@\n \t};\n \n \tpartition@a0000 {\n-\t\tlabel = \"env\";\n+\t\tlabel = \"u-boot environment\";\n \t\treg = <0xa0000 0x20000>;\n \t\tread-only;\n \t};\n \n \tpartition@100000 {\n-\t\tlabel = \"uImage\";\n+\t\tlabel = \"kernel\";\n \t\treg = <0x100000 0x300000>;\n \t};\n \n \tpartition@400000 {\n-\t\tlabel = \"rootfs\";\n+\t\tlabel = \"ubi\";\n \t\treg = <0x400000 0x1C00000>;\n \t};\n };\n@@ -211,7 +218,7 @@\n };\n \n &eth0 {\n-\tstatus = \"okay\";\n+\tstatus = \"disabled\";\n \tethernet0-port@0 {\n \t\tspeed = <1000>;\n \t\tduplex = <1>;\n"
  },
  {
    "path": "target/linux/kirkwood/patches-5.15/105-linksys-viper-dts.patch",
    "content": "--- a/arch/arm/boot/dts/kirkwood-linksys-viper.dts\n+++ b/arch/arm/boot/dts/kirkwood-linksys-viper.dts\n@@ -24,6 +24,10 @@\n \t};\n \n \taliases {\n+\t\tled-boot = &led_white_health;\n+\t\tled-failsafe = &led_white_health;\n+\t\tled-running = &led_white_health;\n+\t\tled-upgrade = &led_white_health;\n \t\tserial0 = &uart0;\n \t};\n \n@@ -56,9 +60,10 @@\n \t\tpinctrl-0 = < &pmx_led_white_health &pmx_led_white_pulse >;\n \t\tpinctrl-names = \"default\";\n \n-\t\twhite-health {\n+\t\tled_white_health: white-health {\n \t\t\tlabel = \"viper:white:health\";\n \t\t\tgpios = <&gpio0 7 GPIO_ACTIVE_HIGH>;\n+\t\t\tdefault-state = \"on\";\n \t\t};\n \n \t\twhite-pulse {\n@@ -114,23 +119,23 @@\n \t\t};\n \n \t\tpartition@200000 {\n-\t\t\tlabel = \"kernel\";\n-\t\t\treg = <0x200000 0x2A0000>;\n+\t\t\tlabel = \"kernel1\";\n+\t\t\treg = <0x200000 0x1A00000>;\n \t\t};\n \n-\t\tpartition@4a0000 {\n-\t\t\tlabel = \"rootfs\";\n-\t\t\treg = <0x4A0000 0x1760000>;\n+\t\tpartition@500000 {\n+\t\t\tlabel = \"rootfs1\";\n+\t\t\treg = <0x500000 0x1700000>;\n \t\t};\n \n \t\tpartition@1c00000 {\n-\t\t\tlabel = \"alt_kernel\";\n-\t\t\treg = <0x1C00000 0x2A0000>;\n+\t\t\tlabel = \"kernel2\";\n+\t\t\treg = <0x1C00000 0x1A00000>;\n \t\t};\n \n-\t\tpartition@1ea0000 {\n-\t\t\tlabel = \"alt_rootfs\";\n-\t\t\treg = <0x1EA0000 0x1760000>;\n+\t\tpartition@1f00000 {\n+\t\t\tlabel = \"rootfs2\";\n+\t\t\treg = <0x1F00000 0x1700000>;\n \t\t};\n \n \t\tpartition@3600000 {\n"
  },
  {
    "path": "target/linux/kirkwood/patches-5.15/106-goflexnet.patch",
    "content": "--- a/arch/arm/boot/dts/kirkwood-goflexnet.dts\n+++ b/arch/arm/boot/dts/kirkwood-goflexnet.dts\n@@ -8,6 +8,13 @@\n \tmodel = \"Seagate GoFlex Net\";\n \tcompatible = \"seagate,goflexnet\", \"marvell,kirkwood-88f6281\", \"marvell,kirkwood\";\n \n+\taliases {\n+\t\tled-boot = &led_health;\n+\t\tled-failsafe = &led_fault;\n+\t\tled-running = &led_health;\n+\t\tled-upgrade = &led_fault;\n+\t};\n+\n \tmemory {\n \t\tdevice_type = \"memory\";\n \t\treg = <0x00000000 0x8000000>;\n@@ -85,12 +92,12 @@\n \t\t\t    >;\n \t\tpinctrl-names = \"default\";\n \n-\t\thealth {\n+\t\tled_health: health {\n \t\t\tlabel = \"status:green:health\";\n \t\t\tgpios = <&gpio1 14 GPIO_ACTIVE_LOW>;\n-\t\t\tdefault-state = \"keep\";\n+\t\t\tdefault-state = \"on\";\n \t\t};\n-\t\tfault {\n+\t\tled_fault: fault {\n \t\t\tlabel = \"status:orange:fault\";\n \t\t\tgpios = <&gpio1 15 GPIO_ACTIVE_LOW>;\n \t\t};\n@@ -159,18 +166,8 @@\n \t};\n \n \tpartition@100000 {\n-\t\tlabel = \"uImage\";\n-\t\treg = <0x0100000 0x400000>;\n-\t};\n-\n-\tpartition@500000 {\n-\t\tlabel = \"pogoplug\";\n-\t\treg = <0x0500000 0x2000000>;\n-\t};\n-\n-\tpartition@2500000 {\n-\t\tlabel = \"root\";\n-\t\treg = <0x02500000 0xd800000>;\n+\t\tlabel = \"ubi\";\n+\t\treg = <0x0100000 0x0ff00000>;\n \t};\n };\n \n"
  },
  {
    "path": "target/linux/kirkwood/patches-5.15/107-01-zyxel-nsa3x0-common-nand-partitions.patch",
    "content": "--- a/arch/arm/boot/dts/kirkwood-nsa3x0-common.dtsi\n+++ b/arch/arm/boot/dts/kirkwood-nsa3x0-common.dtsi\n@@ -112,40 +112,16 @@\n \n \tpartition@0 {\n \t\tlabel = \"uboot\";\n-\t\treg = <0x0000000 0x0100000>;\n+\t\treg = <0x0000000 0x00c0000>;\n \t\tread-only;\n \t};\n \tpartition@100000 {\n \t\tlabel = \"uboot_env\";\n-\t\treg = <0x0100000 0x0080000>;\n+\t\treg = <0x00c0000 0x0080000>;\n \t};\n-\tpartition@180000 {\n-\t\tlabel = \"key_store\";\n-\t\treg = <0x0180000 0x0080000>;\n-\t};\n-\tpartition@200000 {\n-\t\tlabel = \"info\";\n-\t\treg = <0x0200000 0x0080000>;\n-\t};\n-\tpartition@280000 {\n-\t\tlabel = \"etc\";\n-\t\treg = <0x0280000 0x0a00000>;\n-\t};\n-\tpartition@c80000 {\n-\t\tlabel = \"kernel_1\";\n-\t\treg = <0x0c80000 0x0a00000>;\n-\t};\n-\tpartition@1680000 {\n-\t\tlabel = \"rootfs1\";\n-\t\treg = <0x1680000 0x2fc0000>;\n-\t};\n-\tpartition@4640000 {\n-\t\tlabel = \"kernel_2\";\n-\t\treg = <0x4640000 0x0a00000>;\n-\t};\n-\tpartition@5040000 {\n-\t\tlabel = \"rootfs2\";\n-\t\treg = <0x5040000 0x2fc0000>;\n+\tpartition@140000 {\n+\t\tlabel = \"ubi\";\n+\t\treg = <0x0140000 0x7ec0000>;\n \t};\n };\n \n"
  },
  {
    "path": "target/linux/kirkwood/patches-5.15/107-03-nsa325.patch",
    "content": "--- a/arch/arm/boot/dts/kirkwood-nsa325.dts\n+++ b/arch/arm/boot/dts/kirkwood-nsa325.dts\n@@ -15,6 +15,13 @@\n \tmodel = \"ZyXEL NSA325\";\n \tcompatible = \"zyxel,nsa325\", \"marvell,kirkwood-88f6282\", \"marvell,kirkwood\";\n \n+\taliases {\n+\t\tled-boot = &led_green_sys;\n+\t\tled-failsafe = &led_orange_sys;\n+\t\tled-running = &led_green_sys;\n+\t\tled-upgrade = &led_orange_sys;\n+\t};\n+\n \tmemory {\n \t\tdevice_type = \"memory\";\n \t\treg = <0x00000000 0x20000000>;\n@@ -162,17 +169,19 @@\n \t\t\t     &pmx_led_hdd1_green &pmx_led_hdd1_red>;\n \t\tpinctrl-names = \"default\";\n \n-\t\tgreen-sys {\n+\t\tled_green_sys: green-sys {\n \t\t\tlabel = \"nsa325:green:sys\";\n \t\t\tgpios = <&gpio0 28 GPIO_ACTIVE_HIGH>;\n+\t\t\tdefault-state = \"on\";\n \t\t};\n-\t\torange-sys {\n+\t\tled_orange_sys: orange-sys {\n \t\t\tlabel = \"nsa325:orange:sys\";\n \t\t\tgpios = <&gpio0 29 GPIO_ACTIVE_HIGH>;\n \t\t};\n \t\tgreen-hdd1 {\n \t\t\tlabel = \"nsa325:green:hdd1\";\n \t\t\tgpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;\n+\t\t\tlinux,default-trigger = \"ata1\";\n \t\t};\n \t\tred-hdd1 {\n \t\t\tlabel = \"nsa325:red:hdd1\";\n@@ -181,6 +190,7 @@\n \t\tgreen-hdd2 {\n \t\t\tlabel = \"nsa325:green:hdd2\";\n \t\t\tgpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;\n+\t\t\tlinux,default-trigger = \"ata2\";\n \t\t};\n \t\tred-hdd2 {\n \t\t\tlabel = \"nsa325:red:hdd2\";\n@@ -189,6 +199,7 @@\n \t\tgreen-usb {\n \t\t\tlabel = \"nsa325:green:usb\";\n \t\t\tgpios = <&gpio0 15 GPIO_ACTIVE_HIGH>;\n+\t\t\tlinux,default-trigger = \"usb-host\";\n \t\t};\n \t\tgreen-copy {\n \t\t\tlabel = \"nsa325:green:copy\";\n"
  },
  {
    "path": "target/linux/kirkwood/patches-5.15/109-pogoplug_v4.patch",
    "content": "--- a/arch/arm/boot/dts/kirkwood-pogoplug-series-4.dts\n+++ b/arch/arm/boot/dts/kirkwood-pogoplug-series-4.dts\n@@ -18,12 +18,20 @@\n \tcompatible = \"cloudengines,pogoplugv4\", \"marvell,kirkwood-88f6192\",\n \t\t     \"marvell,kirkwood\";\n \n+\taliases {\n+\t\tled-boot = &led_health;\n+\t\tled-failsafe = &led_fault;\n+\t\tled-running = &led_health;\n+\t\tled-upgrade = &led_fault;\n+\t};\n+\n \tmemory {\n \t\tdevice_type = \"memory\";\n \t\treg = <0x00000000 0x08000000>;\n \t};\n \n \tchosen {\n+\t\tbootargs = \"console=ttyS0,115200\";\n \t\tstdout-path = \"uart0:115200n8\";\n \t};\n \n@@ -37,8 +45,8 @@\n \t\teject {\n \t\t\tdebounce-interval = <50>;\n \t\t\twakeup-source;\n-\t\t\tlinux,code = <KEY_EJECTCD>;\n-\t\t\tlabel = \"Eject Button\";\n+\t\t\tlinux,code = <KEY_RESTART>;\n+\t\t\tlabel = \"Reset\";\n \t\t\tgpios = <&gpio0 29 GPIO_ACTIVE_LOW>;\n \t\t};\n \t};\n@@ -48,12 +56,12 @@\n \t\tpinctrl-0 = <&pmx_led_green &pmx_led_red>;\n \t\tpinctrl-names = \"default\";\n \n-\t\thealth {\n+\t\tled_health: health {\n \t\t\tlabel = \"pogoplugv4:green:health\";\n \t\t\tgpios = <&gpio0 22 GPIO_ACTIVE_LOW>;\n \t\t\tdefault-state = \"on\";\n \t\t};\n-\t\tfault {\n+\t\tled_fault: fault {\n \t\t\tlabel = \"pogoplugv4:red:fault\";\n \t\t\tgpios = <&gpio0 24 GPIO_ACTIVE_LOW>;\n \t\t};\n@@ -137,29 +145,19 @@\n \t\t#size-cells = <1>;\n \n \t\tpartition@0 {\n-\t\t\tlabel = \"u-boot\";\n-\t\t\treg = <0x00000000 0x200000>;\n+\t\t\tlabel = \"uboot\";\n+\t\t\treg = <0x00000000 0x1c0000>;\n \t\t\tread-only;\n \t\t};\n \n-\t\tpartition@200000 {\n-\t\t\tlabel = \"uImage\";\n-\t\t\treg = <0x00200000 0x300000>;\n-\t\t};\n-\n-\t\tpartition@500000 {\n-\t\t\tlabel = \"uImage2\";\n-\t\t\treg = <0x00500000 0x300000>;\n-\t\t};\n-\n-\t\tpartition@800000 {\n-\t\t\tlabel = \"failsafe\";\n-\t\t\treg = <0x00800000 0x800000>;\n+\t\tpartition@1c0000 {\n+\t\t\tlabel = \"uboot_env\";\n+\t\t\treg = <0x001c0000 0x40000>;\n \t\t};\n \n-\t\tpartition@1000000 {\n-\t\t\tlabel = \"root\";\n-\t\t\treg = <0x01000000 0x7000000>;\n+\t\tpartition@200000 {\n+\t\t\tlabel = \"ubi\";\n+\t\t\treg = <0x00200000 0x7e00000>;\n \t\t};\n \t};\n };\n"
  },
  {
    "path": "target/linux/kirkwood/patches-5.15/110-pogo_e02.patch",
    "content": "--- a/arch/arm/boot/dts/kirkwood-pogo_e02.dts\n+++ b/arch/arm/boot/dts/kirkwood-pogo_e02.dts\n@@ -20,6 +20,13 @@\n \tcompatible = \"cloudengines,pogoe02\", \"marvell,kirkwood-88f6281\",\n \t\t     \"marvell,kirkwood\";\n \n+\taliases {\n+\t\tled-boot = &led_health;\n+\t\tled-failsafe = &led_fault;\n+\t\tled-running = &led_health;\n+\t\tled-upgrade = &led_fault;\n+\t};\n+\n \tmemory {\n \t\tdevice_type = \"memory\";\n \t\treg = <0x00000000 0x10000000>;\n@@ -33,12 +40,12 @@\n \tgpio-leds {\n \t\tcompatible = \"gpio-leds\";\n \n-\t\thealth {\n+\t\tled_health: health {\n \t\t\tlabel = \"pogo_e02:green:health\";\n \t\t\tgpios = <&gpio1 16 GPIO_ACTIVE_LOW>;\n-\t\t\tdefault-state = \"keep\";\n+\t\t\tdefault-state = \"on\";\n \t\t};\n-\t\tfault {\n+\t\tled_fault: fault {\n \t\t\tlabel = \"pogo_e02:orange:fault\";\n \t\t\tgpios = <&gpio1 17 GPIO_ACTIVE_LOW>;\n \t\t};\n@@ -95,24 +102,24 @@\n \tstatus = \"okay\";\n \n \tpartition@0 {\n-\t\tlabel = \"u-boot\";\n-\t\treg = <0x0000000 0x100000>;\n+\t\tlabel = \"uboot\";\n+\t\treg = <0x0 0xe0000>;\n \t\tread-only;\n \t};\n \n-\tpartition@100000 {\n-\t\tlabel = \"uImage\";\n-\t\treg = <0x0100000 0x400000>;\n+\tpartition@e0000 {\n+\t\tlabel = \"uboot_env\";\n+\t\treg = <0xe0000 0x20000>;\n \t};\n \n-\tpartition@500000 {\n-\t\tlabel = \"pogoplug\";\n-\t\treg = <0x0500000 0x2000000>;\n+\tpartition@100000 {\n+\t\tlabel = \"second_stage_uboot\";\n+\t\treg = <0x100000 0x100000>;\n \t};\n \n-\tpartition@2500000 {\n-\t\tlabel = \"root\";\n-\t\treg = <0x02500000 0x5b00000>;\n+\tpartition@200000 {\n+\t\tlabel = \"ubi\";\n+\t\treg = <0x200000 0x7e00000>;\n \t};\n };\n \n"
  },
  {
    "path": "target/linux/kirkwood/patches-5.15/111-l-50.patch",
    "content": "--- a/arch/arm/boot/dts/kirkwood-l-50.dts\n+++ b/arch/arm/boot/dts/kirkwood-l-50.dts\n@@ -18,6 +18,13 @@\n \t\treg = <0x00000000 0x20000000>;\n \t};\n \n+\taliases {\n+\t\tled-boot = &led_status_green;\n+\t\tled-failsafe = &led_status_red;\n+\t\tled-running = &led_status_green;\n+\t\tled-upgrade = &led_status_red;\n+\t};\n+\n \tchosen {\n \t\tbootargs = \"console=ttyS0,115200n8\";\n \t\tstdout-path = &uart0;\n@@ -95,12 +102,12 @@\n \tleds {\n \t\tcompatible = \"gpio-leds\";\n \n-\t\tstatus_green {\n+\t\tled_status_green: status_green {\n \t\t\tlabel = \"l-50:green:status\";\n \t\t\tgpios = <&gpio1 6 GPIO_ACTIVE_LOW>;\n \t\t};\n \n-\t\tstatus_red {\n+\t\tled_status_red: status_red {\n \t\t\tlabel = \"l-50:red:status\";\n \t\t\tgpios = <&gpio3 2 GPIO_ACTIVE_LOW>;\n \t\t};\n@@ -349,13 +356,8 @@\n \t};\n \n \tpartition@100000 {\n-\t\tlabel = \"kernel-1\";\n-\t\treg = <0x00100000 0x00800000>;\n-\t};\n-\n-\tpartition@900000 {\n-\t\tlabel = \"rootfs-1\";\n-\t\treg = <0x00900000 0x07100000>;\n+\t\tlabel = \"ubi\";\n+\t\treg = <0x00100000 0x07900000>;\n \t};\n \n \tpartition@7a00000 {\n"
  },
  {
    "path": "target/linux/kirkwood/patches-5.15/112-sheevaplug.patch",
    "content": "--- a/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi\n+++ b/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi\n@@ -78,13 +78,8 @@\n \t};\n \n \tpartition@100000 {\n-\t\tlabel = \"uImage\";\n-\t\treg = <0x0100000 0x400000>;\n-\t};\n-\n-\tpartition@500000 {\n-\t\tlabel = \"root\";\n-\t\treg = <0x0500000 0x1fb00000>;\n+\t\tlabel = \"ubi\";\n+\t\treg = <0x0100000 0x1ff00000>;\n \t};\n };\n \n--- a/arch/arm/boot/dts/kirkwood-sheevaplug.dts\n+++ b/arch/arm/boot/dts/kirkwood-sheevaplug.dts\n@@ -13,6 +13,13 @@\n \tmodel = \"Globalscale Technologies SheevaPlug\";\n \tcompatible = \"globalscale,sheevaplug\", \"marvell,kirkwood-88f6281\", \"marvell,kirkwood\";\n \n+\taliases {\n+\t\tled-boot = &led_health;\n+\t\tled-failsafe = &led_health;\n+\t\tled-running = &led_health;\n+\t\tled-upgrade = &led_health;\n+\t};\n+\n \tocp@f1000000 {\n \t\tmvsdio@90000 {\n \t\t\tpinctrl-0 = <&pmx_sdio>;\n@@ -28,10 +35,10 @@\n \t\tpinctrl-0 = <&pmx_led_blue &pmx_led_red>;\n \t\tpinctrl-names = \"default\";\n \n-\t\thealth {\n+\t\tled_health: health {\n \t\t\tlabel = \"sheevaplug:blue:health\";\n \t\t\tgpios = <&gpio1 17 GPIO_ACTIVE_LOW>;\n-\t\t\tdefault-state = \"keep\";\n+\t\t\tdefault-state = \"on\";\n \t\t};\n \n \t\tmisc {\n"
  },
  {
    "path": "target/linux/kirkwood/patches-5.15/113-readynas_duo_v2.patch",
    "content": "--- a/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts\n+++ b/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts\n@@ -19,6 +19,13 @@\n \t\treg = <0x00000000 0x10000000>;\n \t};\n \n+\taliases {\n+\t\tled-boot = &led_power;\n+\t\tled-failsafe = &led_power;\n+\t\tled-running = &led_power;\n+\t\tled-upgrade = &led_power;\n+\t};\n+\n \tchosen {\n \t\tbootargs = \"console=ttyS0,115200n8 earlyprintk\";\n \t\tstdout-path = &uart0;\n@@ -115,7 +122,7 @@\n \t\t\t      &pmx_led_blue_backup >;\n \t\tpinctrl-names = \"default\";\n \n-\t\tpower_led {\n+\t\tled_power: power_led {\n \t\t\tlabel = \"status:blue:power_led\";\n \t\t\tgpios = <&gpio0 31 GPIO_ACTIVE_LOW>;\n \t\t\tdefault-state = \"keep\";\n@@ -129,11 +136,13 @@\n \t\tdisk1_led {\n \t\t\tlabel = \"status:blue:disk1_led\";\n \t\t\tgpios = <&gpio0 23 GPIO_ACTIVE_LOW>;\n+\t\t\tlinux,default-trigger = \"ata1\";\n \t\t};\n \n \t\tdisk2_led {\n \t\t\tlabel = \"status:blue:disk2_led\";\n \t\t\tgpios = <&gpio0 22 GPIO_ACTIVE_LOW>;\n+\t\t\tlinux,default-trigger = \"ata2\";\n \t\t};\n \n \t\tbackup_led {\n@@ -150,7 +159,13 @@\n \n \t\tpower-button {\n \t\t\tlabel = \"Power Button\";\n-\t\t\tlinux,code = <KEY_POWER>;\n+\t\t\t/* Power button and INT pin from PHY are both connected\n+\t\t\t * to this GPIO. Every network restart causes PHY restart\n+\t\t\t * and button is pressed. It's difficult to use it as\n+\t\t\t * KEY_POWER without changes in kernel (or netifd) so\n+\t\t\t * the button is configured as regular one.\n+\t\t\t */\n+\t\t\tlinux,code = <BTN_1>;\n \t\t\tgpios = <&gpio1 15 GPIO_ACTIVE_LOW>;\n \t\t};\n \n@@ -208,18 +223,13 @@\n \t};\n \n \tpartition@200000 {\n-\t\tlabel = \"uImage\";\n+\t\tlabel = \"kernel\";\n \t\treg = <0x0200000 0x600000>;\n \t};\n \n \tpartition@800000 {\n-\t\tlabel = \"minirootfs\";\n-\t\treg = <0x0800000 0x1000000>;\n-\t};\n-\n-\tpartition@1800000 {\n-\t\tlabel = \"jffs2\";\n-\t\treg = <0x1800000 0x6800000>;\n+\t\tlabel = \"ubi\";\n+\t\treg = <0x0800000 0x7800000>;\n \t};\n };\n \n"
  },
  {
    "path": "target/linux/kirkwood/patches-5.15/201-enable-sata-port-specific-led-triggers.patch",
    "content": "--- a/arch/arm/mach-mvebu/Kconfig\n+++ b/arch/arm/mach-mvebu/Kconfig\n@@ -116,6 +116,7 @@ config MACH_DOVE\n config MACH_KIRKWOOD\n \tbool \"Marvell Kirkwood boards\"\n \tdepends on ARCH_MULTI_V5\n+\tselect ARCH_WANT_LIBATA_LEDS\n \tselect CPU_FEROCEON\n \tselect GPIOLIB\n \tselect KIRKWOOD_CLK\n"
  },
  {
    "path": "target/linux/kirkwood/patches-5.15/202-linksys-find-active-root.patch",
    "content": "The WRT1900AC among other Linksys routers uses a dual-firmware layout.\nDynamically rename the active partition to \"ubi\".\n\nSigned-off-by: Imre Kaloz <kaloz@openwrt.org>\n---\n--- a/drivers/mtd/parsers/ofpart_core.c\n+++ b/drivers/mtd/parsers/ofpart_core.c\n@@ -38,6 +38,8 @@ static bool node_has_compatible(struct d\n \treturn of_get_property(pp, \"compatible\", NULL);\n }\n \n+static int mangled_rootblock;\n+\n static int parse_fixed_partitions(struct mtd_info *master,\n \t\t\t\t  const struct mtd_partition **pparts,\n \t\t\t\t  struct mtd_part_parser_data *data)\n@@ -47,6 +49,7 @@ static int parse_fixed_partitions(struct\n \tstruct mtd_partition *parts;\n \tstruct device_node *mtd_node;\n \tstruct device_node *ofpart_node;\n+\tconst char *owrtpart = \"ubi\";\n \tconst char *partname;\n \tstruct device_node *pp;\n \tint nr_parts, i, ret = 0;\n@@ -133,9 +136,15 @@ static int parse_fixed_partitions(struct\n \t\tparts[i].size = of_read_number(reg + a_cells, s_cells);\n \t\tparts[i].of_node = pp;\n \n-\t\tpartname = of_get_property(pp, \"label\", &len);\n-\t\tif (!partname)\n-\t\t\tpartname = of_get_property(pp, \"name\", &len);\n+\t\tif (mangled_rootblock && (i == mangled_rootblock)) {\n+\t\t\tpartname = owrtpart;\n+\t\t} else {\n+\t\t\tpartname = of_get_property(pp, \"label\", &len);\n+\n+\t\t\tif (!partname)\n+\t\t\t\tpartname = of_get_property(pp, \"name\", &len);\n+\t\t}\n+\n \t\tparts[i].name = partname;\n \n \t\tif (of_get_property(pp, \"read-only\", &len))\n@@ -252,6 +261,18 @@ static int __init ofpart_parser_init(voi\n \treturn 0;\n }\n \n+static int __init active_root(char *str)\n+{\n+\tget_option(&str, &mangled_rootblock);\n+\n+\tif (!mangled_rootblock)\n+\t\treturn 1;\n+\n+\treturn 1;\n+}\n+\n+__setup(\"mangled_rootblock=\", active_root);\n+\n static void __exit ofpart_parser_exit(void)\n {\n \tderegister_mtd_parser(&ofpart_parser);\n"
  },
  {
    "path": "target/linux/kirkwood/patches-5.15/203-blackarmor-nas220.patch",
    "content": "--- a/arch/arm/boot/dts/kirkwood-blackarmor-nas220.dts\n+++ b/arch/arm/boot/dts/kirkwood-blackarmor-nas220.dts\n@@ -17,6 +17,13 @@\n \tcompatible = \"seagate,blackarmor-nas220\",\"marvell,kirkwood-88f6192\",\n \t\t     \"marvell,kirkwood\";\n \n+\taliases {\n+\t\tled-boot = &led_status_amber;\n+\t\tled-failsafe = &led_status_amber;\n+\t\tled-running = &led_status_blue;\n+\t\tled-upgrade = &led_status_amber;\n+\t};\n+\n \tmemory { /* 128 MB */\n \t\tdevice_type = \"memory\";\n \t\treg = <0x00000000 0x8000000>;\n@@ -36,14 +43,14 @@\n \t\tcompatible = \"gpio-keys\";\n \n \t\treset {\n-\t\t\tlabel = \"Reset\";\n-\t\t\tlinux,code = <KEY_POWER>;\n+\t\t\tlabel = \"Reset Button\";\n+\t\t\tlinux,code = <KEY_RESTART>;\n \t\t\tgpios = <&gpio0 29 GPIO_ACTIVE_HIGH>;\n \t\t};\n \n-\t\tbutton {\n-\t\t\tlabel = \"Power\";\n-\t\t\tlinux,code = <KEY_SLEEP>;\n+\t\tpower {\n+\t\t\tlabel = \"Power Button\";\n+\t\t\tlinux,code = <KEY_POWER>;\n \t\t\tgpios = <&gpio0 26 GPIO_ACTIVE_LOW>;\n \t\t};\n \t};\n@@ -51,11 +58,27 @@\n \tgpio-leds {\n \t\tcompatible = \"gpio-leds\";\n \n-\t\tblue-power {\n+\t\tled_power_blue: power_blue {\n \t\t\tlabel = \"nas220:blue:power\";\n \t\t\tgpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;\n \t\t\tlinux,default-trigger = \"default-on\";\n \t\t};\n+\n+\t\tdisk_blue {\n+\t\t\tlabel = \"nas220:blue:disk\";\n+\t\t\tgpios = <&gpio0 16 GPIO_ACTIVE_LOW>;\n+\t\t\tlinux,default-trigger = \"disk-activity\";\n+\t\t};\n+\n+\t\tled_status_blue: status_blue {\n+\t\t\tlabel = \"nas220:blue:status\";\n+\t\t\tgpios = <&gpio0 23 GPIO_ACTIVE_HIGH>;\n+\t\t};\n+\n+\t\tled_status_amber: status_amber {\n+\t\t\tlabel = \"nas220:amber:status\";\n+\t\t\tgpios = <&gpio0 22 GPIO_ACTIVE_HIGH>;\n+\t\t};\n \t};\n \n \tregulators {\n@@ -153,6 +176,33 @@\n \n &nand {\n \tstatus = \"okay\";\n+\n+\tpartitions {\n+\t\tcompatible = \"fixed-partitions\";\n+\n+\t\tpartition@0 {\n+\t\t\tlabel = \"uboot\";\n+\t\t\treg = <0x0 0xa0000>;\n+\t\t\tread-only;\n+\t\t};\n+\n+\t\tpartition@a0000 {\n+\t\t\tlabel = \"uboot-env\";\n+\t\t\treg = <0xa0000 0x10000>;\n+\t\t\tread-only;\n+\t\t};\n+\n+\t\tpartition@b0000 {\n+\t\t\tlabel = \"reserved\";\n+\t\t\treg = <0xb0000 0x10000>;\n+\t\t\tread-only;\n+\t\t};\n+\n+\t\tpartition@c0000 {\n+\t\t\tlabel = \"ubi\";\n+\t\t\treg = <0xc0000 0x1e80000>;\n+\t\t};\n+\t};\n };\n \n &mdio {\n"
  },
  {
    "path": "target/linux/lantiq/Makefile",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2007-2011 OpenWrt.org\n\ninclude $(TOPDIR)/rules.mk\n\nBOARD:=lantiq\nBOARDNAME:=Lantiq\nFEATURES:=squashfs\nSUBTARGETS:=xrx200 xway xway_legacy falcon ase\n\nKERNEL_PATCHVER:=5.10\nKERNEL_TESTING_PATCHVER:=5.10\n\ndefine Target/Description\n\tBuild firmware images for Lantiq SoC\nendef\n\ninclude $(INCLUDE_DIR)/target.mk\n\n$(eval $(call BuildTarget))\n"
  },
  {
    "path": "target/linux/lantiq/ase/base-files/etc/board.d/01_leds",
    "content": "#\n# Copyright (C) 2011-2015 OpenWrt.org\n#\n\n. /lib/functions/leds.sh\n. /lib/functions/uci-defaults.sh\n\nboard_config_update\n\nled_dsl=\"$(get_dt_led dsl)\"\n[ -n \"$led_dsl\" ] && {\n\tled_internet=\"$(get_dt_led internet)\"\n\tif [ -n \"$led_internet\" ]; then\n\t\tucidef_set_led_default \"dsl\" \"dsl\" \"$led_dsl\" \"0\"\n\t\tucidef_set_led_netdev \"internet\" \"internet\" \"$led_internet\" \"pppoe-wan\"\n\telse\n\t\tucidef_set_led_netdev \"dsl\" \"dsl\" \"$led_dsl\" \"dsl0\"\n\tfi\n}\n\nboard=$(board_name)\n\ncase \"$board\" in\nallnet,all0333cj)\n\tucidef_set_led_netdev \"lan\" \"lan\" \"green:lan\" \"eth0.1\"\n\t;;\nesac\n\nboard_config_flush\n\nexit 0\n"
  },
  {
    "path": "target/linux/lantiq/ase/base-files/etc/board.d/02_network",
    "content": "#\n# Copyright (C) 2011-2015 OpenWrt.org\n#\n\n. /lib/functions/uci-defaults.sh\n. /lib/functions/system.sh\n. /lib/functions/lantiq.sh\n\nlantiq_setup_interfaces()\n{\n\tlocal board=\"$1\"\n\n\tcase \"$board\" in\n\t*)\n\t\tucidef_set_interface_lan 'eth0'\n\t\t;;\n\tesac\n}\n\nlantiq_setup_dsl()\n{\n\tlocal board=\"$1\"\n\tlocal annex=\"b\"\n\n\tcase \"$board\" in\n\tesac\n\n\tlantiq_setup_dsl_helper \"$annex\"\n}\n\nlantiq_setup_macs()\n{\n\tlocal board=\"$1\"\n\tlocal lan_mac=\"\"\n\tlocal wan_mac=\"\"\n\n\tcase \"$board\" in\n\tallnet,all0333cj)\n\t\tlan_mac=$(mtd_get_mac_ascii u-boot-env ethaddr)\n\t\twan_mac=$(macaddr_add \"$lan_mac\" 1)\n\t\t;;\n\tesac\n\n\t[ -n \"$lan_mac\" ] && ucidef_set_interface_macaddr \"lan\" \"$lan_mac\"\n\t[ -n \"$wan_mac\" ] && ucidef_set_interface_macaddr \"wan\" \"$wan_mac\"\n}\n\nboard_config_update\nboard=$(board_name)\nlantiq_setup_interfaces $board\nlantiq_setup_dsl $board\nlantiq_setup_macs $board\nboard_config_flush\n\nexit 0\n"
  },
  {
    "path": "target/linux/lantiq/ase/base-files/etc/uci-defaults/01_led_migration",
    "content": "#\n# Copyright (C) 2020 OpenWrt.org\n#\n\n. /lib/functions/migrations.sh\n\nremove_devicename_leds\n\nmigrations_apply system\n\nexit 0\n"
  },
  {
    "path": "target/linux/lantiq/ase/base-files/lib/preinit/05_set_preinit_iface_lantiq",
    "content": "set_preinit_iface() {\n\tifname=eth0\n}\n\nboot_hook_add preinit_main set_preinit_iface\n"
  },
  {
    "path": "target/linux/lantiq/ase/base-files/lib/upgrade/platform.sh",
    "content": "PART_NAME=firmware\nREQUIRE_IMAGE_METADATA=1\n\nplatform_check_image() {\n\treturn 0\n}\n\nplatform_do_upgrade() {\n\tdefault_do_upgrade \"$1\"\n}\n"
  },
  {
    "path": "target/linux/lantiq/ase/config-5.10",
    "content": "CONFIG_ADM6996_PHY=y\nCONFIG_CPU_MIPS32_R1=y\n# CONFIG_CPU_MIPS32_R2 is not set\nCONFIG_CPU_MIPSR1=y\nCONFIG_CRC16=y\nCONFIG_CRYPTO_ACOMP2=y\nCONFIG_CRYPTO_DEFLATE=y\nCONFIG_FIRMWARE_MEMMAP=y\nCONFIG_GENERIC_ALLOCATOR=y\nCONFIG_GPIO_GENERIC=y\nCONFIG_GPIO_GENERIC_PLATFORM=y\nCONFIG_HW_RANDOM=y\n# CONFIG_ISDN is not set\nCONFIG_LANTIQ_ETOP=y\nCONFIG_NLS=y\nCONFIG_SGL_ALLOC=y\nCONFIG_SOC_AMAZON_SE=y\nCONFIG_SOC_TYPE_XWAY=y\nCONFIG_SWCONFIG=y\nCONFIG_TARGET_ISA_REV=1\nCONFIG_USB=y\nCONFIG_USB_COMMON=y\nCONFIG_USB_SUPPORT=y\nCONFIG_ZLIB_DEFLATE=y\nCONFIG_ZLIB_INFLATE=y\n"
  },
  {
    "path": "target/linux/lantiq/ase/profiles/00-default.mk",
    "content": "define Profile/Default\n\tNAME:=Default Profile\n\tPRIORITY:=1\nendef\n\ndefine Profile/Default/Description\n\tDefault package set compatible with most boards.\nendef\n$(eval $(call Profile,Default))\n"
  },
  {
    "path": "target/linux/lantiq/ase/target.mk",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2016 LEDE Project\n\nARCH:=mips\nSUBTARGET:=ase\nBOARDNAME:=Amazon-SE\nFEATURES+=atm mips16 small_flash\nCPU_TYPE:=mips32\n\nDEFAULT_PACKAGES+=kmod-leds-gpio kmod-gpio-button-hotplug \\\n\tkmod-ltq-adsl-ase kmod-ltq-adsl-ase-mei \\\n\tkmod-ltq-adsl-ase-fw-b kmod-ltq-atm-ase \\\n\tltq-adsl-app ppp-mod-pppoe\n\ndefine Target/Description\n\tLantiq Amazon-SE Boards\nendef\n"
  },
  {
    "path": "target/linux/lantiq/base-files/etc/inittab",
    "content": "::sysinit:/etc/init.d/rcS S boot\n::shutdown:/etc/init.d/rcS K shutdown\nttyLTQ0::askfirst:/usr/libexec/login.sh\n"
  },
  {
    "path": "target/linux/lantiq/base-files/etc/uci-defaults/02_migrate_xdsl_iface",
    "content": ". /lib/functions.sh\n\nIFNAME_CHANGED=0\n\nrename_xdsl_ifname()\n{\n\tlocal cfg=\"$1\"\n\tlocal section=\"$2\"\n\tlocal option=\"$3\"\n\tlocal name\n\n\tconfig_get name ${section} $option\n\tcase $name in\n\t\tnas0*)\n\t\t\tname=${name/nas0/dsl0}\n\t\t\t;;\n\t\tptm0*)\n\t\t\tname=${name/ptm0/dsl0}\n\t\t\t;;\n\t\t*)\n\t\t\treturn\n\t\t\t;;\n\tesac\n\n\tuci set ${cfg}.${section}.$option=$name\n\tIFNAME_CHANGED=1\n}\n\nadd_atm_bridge_nameprefix()\n{\n\tlocal cfg=\"$1\"\n\n\tconfig_get nameprefix \"$cfg\" nameprefix\n\t[ -z \"$nameprefix\" ] || return\n\n\tuci set network.${cfg}.nameprefix=\"dsl\"\n\tIFNAME_CHANGED=1\n}\n\nmigrate_network_xdsl_ifname()\n{\n\trename_xdsl_ifname network \"$1\" ifname\n\trename_xdsl_ifname network \"$1\" name\n}\n\nmigrate_led_xdsl_ifname()\n{\n\trename_xdsl_ifname system \"$1\" dev\n}\n\nconfig_load network\nconfig_foreach migrate_network_xdsl_ifname\nconfig_foreach add_atm_bridge_nameprefix atm-bridge\n\n[ \"$IFNAME_CHANGED\" = \"1\" ] && uci commit network\n\nIFNAME_CHANGED=0\n\nconfig_load system\nconfig_foreach migrate_led_xdsl_ifname led\n\n[ \"$IFNAME_CHANGED\" = \"1\" ] && uci commit system\n\nexit 0\n"
  },
  {
    "path": "target/linux/lantiq/base-files/lib/functions/lantiq.sh",
    "content": "lantiq_is_vdsl_system() {\n\tgrep -qE \"system type.*: (VR9|xRX200)\" /proc/cpuinfo\n}\n\nlantiq_setup_dsl_helper() {\n\tlocal annex=\"$1\"\n\n\tls /lib/modules/$(uname -r)/ltq_atm* 1> /dev/null 2>&1 && \\\n\t\tucidef_add_atm_bridge \"1\" \"32\" \"llc\" \"bridged\" \"dsl\"\n\n\tif lantiq_is_vdsl_system; then\n\t\tucidef_add_vdsl_modem \"$annex\" \"av\"\n\telse\n\t\tucidef_add_adsl_modem \"$annex\" \"/lib/firmware/adsl.bin\"\n\tfi\n\n\tucidef_set_interface_wan \"dsl0\" \"pppoe\"\n}\n"
  },
  {
    "path": "target/linux/lantiq/config-5.10",
    "content": "CONFIG_ARCH_32BIT_OFF_T=y\nCONFIG_ARCH_CLOCKSOURCE_DATA=y\nCONFIG_ARCH_HAS_DMA_COHERENT_TO_PFN=y\nCONFIG_ARCH_HAS_DMA_PREP_COHERENT=y\nCONFIG_ARCH_HAS_DMA_WRITE_COMBINE=y\nCONFIG_ARCH_HAS_ELF_RANDOMIZE=y\nCONFIG_ARCH_HAS_RESET_CONTROLLER=y\nCONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y\nCONFIG_ARCH_HAS_UNCACHED_SEGMENT=y\nCONFIG_ARCH_HIBERNATION_POSSIBLE=y\nCONFIG_ARCH_MMAP_RND_BITS_MAX=15\nCONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15\nCONFIG_ARCH_SUPPORTS_UPROBES=y\nCONFIG_ARCH_SUSPEND_POSSIBLE=y\nCONFIG_ARCH_USE_BUILTIN_BSWAP=y\nCONFIG_ARCH_USE_MEMREMAP_PROT=y\nCONFIG_ARCH_USE_QUEUED_RWLOCKS=y\nCONFIG_ARCH_USE_QUEUED_SPINLOCKS=y\nCONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y\nCONFIG_ARCH_WANT_IPC_PARSE_VERSION=y\nCONFIG_CEVT_R4K=y\nCONFIG_CLKDEV_LOOKUP=y\nCONFIG_CLONE_BACKWARDS=y\nCONFIG_COMPAT_32BIT_TIME=y\nCONFIG_CPU_BIG_ENDIAN=y\nCONFIG_CPU_GENERIC_DUMP_TLB=y\nCONFIG_CPU_HAS_LOAD_STORE_LR=y\nCONFIG_CPU_HAS_PREFETCH=y\nCONFIG_CPU_HAS_RIXI=y\nCONFIG_CPU_HAS_SYNC=y\nCONFIG_CPU_MIPS32=y\n# CONFIG_CPU_MIPS32_R1 is not set\nCONFIG_CPU_MIPS32_R2=y\nCONFIG_CPU_MIPSR2=y\nCONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y\nCONFIG_CPU_R4K_CACHE_TLB=y\nCONFIG_CPU_SUPPORTS_32BIT_KERNEL=y\nCONFIG_CPU_SUPPORTS_HIGHMEM=y\nCONFIG_CPU_SUPPORTS_MSA=y\nCONFIG_CRYPTO_LIB_POLY1305_RSIZE=2\nCONFIG_CRYPTO_RNG2=y\nCONFIG_CSRC_R4K=y\nCONFIG_DMA_NONCOHERENT=y\nCONFIG_DMA_NONCOHERENT_CACHE_SYNC=y\nCONFIG_DTC=y\n# CONFIG_DT_EASY50712 is not set\nCONFIG_EARLY_PRINTK=y\nCONFIG_EFI_EARLYCON=y\nCONFIG_FIXED_PHY=y\nCONFIG_FONT_8x16=y\nCONFIG_FONT_AUTOSELECT=y\nCONFIG_FONT_SUPPORT=y\nCONFIG_FW_LOADER_PAGED_BUF=y\nCONFIG_GENERIC_ATOMIC64=y\nCONFIG_GENERIC_CLOCKEVENTS=y\nCONFIG_GENERIC_CMOS_UPDATE=y\nCONFIG_GENERIC_CPU_AUTOPROBE=y\nCONFIG_GENERIC_GETTIMEOFDAY=y\nCONFIG_GENERIC_IOMAP=y\nCONFIG_GENERIC_IRQ_CHIP=y\nCONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y\nCONFIG_GENERIC_IRQ_SHOW=y\nCONFIG_GENERIC_LIB_ASHLDI3=y\nCONFIG_GENERIC_LIB_ASHRDI3=y\nCONFIG_GENERIC_LIB_CMPDI2=y\nCONFIG_GENERIC_LIB_LSHRDI3=y\nCONFIG_GENERIC_LIB_UCMPDI2=y\nCONFIG_GENERIC_PCI_IOMAP=y\nCONFIG_GENERIC_PHY=y\nCONFIG_GENERIC_SCHED_CLOCK=y\nCONFIG_GENERIC_SMP_IDLE_THREAD=y\nCONFIG_GENERIC_TIME_VSYSCALL=y\nCONFIG_GPIOLIB=y\nCONFIG_GPIO_MM_LANTIQ=y\nCONFIG_GPIO_STP_XWAY=y\nCONFIG_HANDLE_DOMAIN_IRQ=y\nCONFIG_HARDWARE_WATCHPOINTS=y\nCONFIG_HAS_DMA=y\nCONFIG_HAS_IOMEM=y\nCONFIG_HAS_IOPORT_MAP=y\nCONFIG_HAVE_ARCH_COMPILER_H=y\nCONFIG_HAVE_ARCH_JUMP_LABEL=y\nCONFIG_HAVE_ARCH_KGDB=y\nCONFIG_HAVE_ARCH_SECCOMP_FILTER=y\nCONFIG_HAVE_ARCH_TRACEHOOK=y\nCONFIG_HAVE_ASM_MODVERSIONS=y\nCONFIG_HAVE_CLK=y\nCONFIG_HAVE_CONTEXT_TRACKING=y\nCONFIG_HAVE_COPY_THREAD_TLS=y\nCONFIG_HAVE_C_RECORDMCOUNT=y\nCONFIG_HAVE_DEBUG_KMEMLEAK=y\nCONFIG_HAVE_DEBUG_STACKOVERFLOW=y\nCONFIG_HAVE_DMA_CONTIGUOUS=y\nCONFIG_HAVE_DYNAMIC_FTRACE=y\nCONFIG_HAVE_FAST_GUP=y\nCONFIG_HAVE_FTRACE_MCOUNT_RECORD=y\nCONFIG_HAVE_FUNCTION_GRAPH_TRACER=y\nCONFIG_HAVE_FUNCTION_TRACER=y\nCONFIG_HAVE_GENERIC_VDSO=y\nCONFIG_HAVE_IDE=y\nCONFIG_HAVE_IOREMAP_PROT=y\nCONFIG_HAVE_IRQ_EXIT_ON_IRQ_STACK=y\nCONFIG_HAVE_IRQ_TIME_ACCOUNTING=y\nCONFIG_HAVE_KVM=y\nCONFIG_HAVE_LD_DEAD_CODE_DATA_ELIMINATION=y\nCONFIG_HAVE_MEMBLOCK_NODE_MAP=y\nCONFIG_HAVE_MOD_ARCH_SPECIFIC=y\nCONFIG_HAVE_NET_DSA=y\nCONFIG_HAVE_OPROFILE=y\nCONFIG_HAVE_PCI=y\nCONFIG_HAVE_PERF_EVENTS=y\nCONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y\nCONFIG_HAVE_RSEQ=y\nCONFIG_HAVE_SYSCALL_TRACEPOINTS=y\nCONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y\nCONFIG_HZ_PERIODIC=y\nCONFIG_INITRAMFS_SOURCE=\"\"\nCONFIG_IRQCHIP=y\nCONFIG_IRQ_DOMAIN=y\nCONFIG_IRQ_DOMAIN_HIERARCHY=y\nCONFIG_IRQ_FORCED_THREADING=y\nCONFIG_IRQ_MIPS_CPU=y\nCONFIG_IRQ_WORK=y\nCONFIG_LANTIQ=y\nCONFIG_LANTIQ_DT_NONE=y\n# CONFIG_LANTIQ_ETOP is not set\nCONFIG_LANTIQ_WDT=y\n# CONFIG_LANTIQ_XRX200 is not set\nCONFIG_LEDS_GPIO=y\nCONFIG_LIBFDT=y\nCONFIG_LOCK_DEBUGGING_SUPPORT=y\nCONFIG_MDIO_BUS=y\nCONFIG_MDIO_DEVICE=y\nCONFIG_MDIO_DEVRES=y\nCONFIG_MEMFD_CREATE=y\nCONFIG_MFD_CORE=y\nCONFIG_MFD_SYSCON=y\nCONFIG_MIGRATION=y\nCONFIG_MIPS=y\nCONFIG_MIPS_ASID_BITS=8\nCONFIG_MIPS_ASID_SHIFT=0\nCONFIG_MIPS_CBPF_JIT=y\nCONFIG_MIPS_CLOCK_VSYSCALL=y\n# CONFIG_MIPS_CMDLINE_DTB_EXTEND is not set\n# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set\nCONFIG_MIPS_CMDLINE_FROM_DTB=y\n# CONFIG_MIPS_ELF_APPENDED_DTB is not set\nCONFIG_MIPS_L1_CACHE_SHIFT=5\nCONFIG_MIPS_LD_CAN_LINK_VDSO=y\n# CONFIG_MIPS_MT_SMP is not set\n# CONFIG_MIPS_NO_APPENDED_DTB is not set\nCONFIG_MIPS_RAW_APPENDED_DTB=y\nCONFIG_MIPS_SPRAM=y\n# CONFIG_MIPS_VPE_LOADER is not set\nCONFIG_MODULES_USE_ELF_REL=y\nCONFIG_MTD_CFI_ADV_OPTIONS=y\nCONFIG_MTD_CFI_GEOMETRY=y\nCONFIG_MTD_CMDLINE_PARTS=y\nCONFIG_MTD_JEDECPROBE=y\nCONFIG_MTD_LANTIQ=y\nCONFIG_MTD_SPI_NOR=y\nCONFIG_MTD_SPLIT_BRNIMAGE_FW=y\nCONFIG_MTD_SPLIT_EVA_FW=y\nCONFIG_MTD_SPLIT_FIRMWARE=y\nCONFIG_MTD_SPLIT_TPLINK_FW=y\nCONFIG_MTD_SPLIT_UIMAGE_FW=y\nCONFIG_NEED_DMA_MAP_STATE=y\nCONFIG_NEED_PER_CPU_KM=y\nCONFIG_NO_GENERIC_PCI_IOPORT_MAP=y\nCONFIG_NVMEM=y\nCONFIG_OF=y\nCONFIG_OF_ADDRESS=y\nCONFIG_OF_EARLY_FLATTREE=y\nCONFIG_OF_FLATTREE=y\nCONFIG_OF_GPIO=y\nCONFIG_OF_IRQ=y\nCONFIG_OF_KOBJ=y\nCONFIG_OF_MDIO=y\nCONFIG_OF_NET=y\n# CONFIG_PCIE_LANTIQ is not set\nCONFIG_PCI_DRIVERS_LEGACY=y\nCONFIG_PERF_USE_VMALLOC=y\nCONFIG_PGTABLE_LEVELS=2\nCONFIG_PHYLIB=y\nCONFIG_PHY_LANTIQ_RCU_USB2=y\n# CONFIG_PHY_LANTIQ_VRX200_PCIE is not set\nCONFIG_PINCTRL=y\nCONFIG_PINCTRL_LANTIQ=y\n# CONFIG_PINCTRL_SINGLE is not set\nCONFIG_PINCTRL_XWAY=y\nCONFIG_POWER_RESET=y\nCONFIG_POWER_RESET_SYSCON=y\nCONFIG_REGMAP=y\nCONFIG_REGMAP_MMIO=y\nCONFIG_RESET_CONTROLLER=y\nCONFIG_RESET_LANTIQ=y\n# CONFIG_SERIAL_8250 is not set\nCONFIG_SERIAL_LANTIQ=y\nCONFIG_SERIAL_LANTIQ_CONSOLE=y\n# CONFIG_SOC_AMAZON_SE is not set\n# CONFIG_SOC_FALCON is not set\n# CONFIG_SOC_XWAY is not set\nCONFIG_SPI=y\nCONFIG_SPI_LANTIQ_SSC=y\nCONFIG_SPI_MASTER=y\nCONFIG_SPI_MEM=y\nCONFIG_SRCU=y\nCONFIG_SWAP_IO_SPACE=y\nCONFIG_SWPHY=y\nCONFIG_SYSCTL_EXCEPTION_TRACE=y\nCONFIG_SYS_HAS_CPU_MIPS32_R1=y\nCONFIG_SYS_HAS_CPU_MIPS32_R2=y\nCONFIG_SYS_HAS_EARLY_PRINTK=y\nCONFIG_SYS_SUPPORTS_32BIT_KERNEL=y\nCONFIG_SYS_SUPPORTS_ARBIT_HZ=y\nCONFIG_SYS_SUPPORTS_BIG_ENDIAN=y\nCONFIG_SYS_SUPPORTS_MIPS16=y\nCONFIG_SYS_SUPPORTS_MULTITHREADING=y\nCONFIG_SYS_SUPPORTS_VPE_LOADER=y\nCONFIG_TARGET_ISA_REV=2\nCONFIG_TICK_CPU_ACCOUNTING=y\nCONFIG_TINY_SRCU=y\nCONFIG_USE_OF=y\nCONFIG_WATCHDOG_CORE=y\n"
  },
  {
    "path": "target/linux/lantiq/falcon/base-files/etc/board.d/02_network",
    "content": "#\n# Copyright (C) 2011-2015 OpenWrt.org\n#\n\n. /lib/functions/uci-defaults.sh\n. /lib/functions/system.sh\n. /lib/functions/lantiq.sh\n\nlantiq_setup_interfaces()\n{\n\tlocal board=\"$1\"\n\n\tcase \"$board\" in\n\t*)\n\t\tucidef_set_interface_lan 'eth0'\n\t\t;;\n\tesac\n}\n\nlantiq_setup_dsl()\n{\n\tlocal board=\"$1\"\n\tlocal annex=\"a\"\n\n\tcase \"$board\" in\n\tesac\n\n\tlantiq_setup_dsl_helper \"$annex\"\n}\n\nlantiq_setup_macs()\n{\n\tlocal board=\"$1\"\n\tlocal lan_mac=\"\"\n\tlocal wan_mac=\"\"\n\n\tcase \"$board\" in\n\tesac\n\n\t[ -n \"$lan_mac\" ] && ucidef_set_interface_macaddr \"lan\" \"$lan_mac\"\n\t[ -n \"$wan_mac\" ] && ucidef_set_interface_macaddr \"wan\" \"$wan_mac\"\n}\n\nboard_config_update\nboard=$(board_name)\nlantiq_setup_interfaces $board\nlantiq_setup_dsl $board\nlantiq_setup_macs $board\nboard_config_flush\n\nexit 0\n"
  },
  {
    "path": "target/linux/lantiq/falcon/base-files/etc/uci-defaults/01_led_migration",
    "content": "#\n# Copyright (C) 2020 OpenWrt.org\n#\n\n. /lib/functions/migrations.sh\n\nboard=$(board_name)\n\ncase \"$board\" in\nlantiq,easy98020)\n\tmigrate_leds \"easy98020:=\"\n\t;;\nesac\n\nremove_devicename_leds\n\nmigrations_apply system\n\nexit 0\n"
  },
  {
    "path": "target/linux/lantiq/falcon/base-files/lib/upgrade/platform.sh",
    "content": "PART_NAME=firmware\nREQUIRE_IMAGE_METADATA=1\n\nplatform_check_image() {\n\treturn 0\n}\n\nplatform_do_upgrade() {\n\tdefault_do_upgrade \"$1\"\n}\n"
  },
  {
    "path": "target/linux/lantiq/falcon/config-5.10",
    "content": "CONFIG_CPU_HAS_DIEI=y\nCONFIG_MTD_NAND_CORE=y\nCONFIG_MTD_NAND_ECC=y\nCONFIG_MTD_NAND_ECC_SW_HAMMING=y\nCONFIG_MTD_RAW_NAND=y\nCONFIG_MTD_SPLIT_FIRMWARE_NAME=\"linux\"\nCONFIG_PINCTRL_FALCON=y\nCONFIG_SOC_FALCON=y\nCONFIG_SPI_FALCON=y\n"
  },
  {
    "path": "target/linux/lantiq/falcon/profiles/00-default.mk",
    "content": "define Profile/Default\n\tNAME:=Default Profile\n\tPRIORITY:=1\nendef\n\ndefine Profile/Default/Description\n\tDefault package set compatible with most boards.\nendef\n$(eval $(call Profile,Default))\n"
  },
  {
    "path": "target/linux/lantiq/falcon/target.mk",
    "content": "ARCH:=mips\nSUBTARGET:=falcon\nBOARDNAME:=Falcon\nFEATURES+=nand source-only\nCPU_TYPE:=24kc\n\nDEFAULT_PACKAGES+= kmod-leds-gpio \\\n\tkmod-gpio-button-hotplug\n\ndefine Target/Description\n\tLantiq Falcon\nendef\n"
  },
  {
    "path": "target/linux/lantiq/files/arch/mips/boot/dts/lantiq/amazonse.dtsi",
    "content": "/dts-v1/;\n\n#include <dt-bindings/gpio/gpio.h>\n\n/ {\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\tcompatible = \"lantiq,xway\", \"lantiq,ase\";\n\n\taliases {\n\t\tserial0 = &asc1;\n\t};\n\n\tchosen {\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu@0 {\n\t\t\tcompatible = \"mips,mips4Kc\";\n\t\t\treg = <0>;\n\t\t};\n\t};\n\n\treboot {\n\t\tcompatible = \"syscon-reboot\";\n\n\t\tregmap = <&rcu0>;\n\t\toffset = <0x10>;\n\t\tmask = <0x40000000>;\n\t};\n\n\tbiu@1f800000 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"lantiq,biu\", \"simple-bus\";\n\t\treg = <0x1f800000 0x800000>;\n\t\tranges = <0x0 0x1f800000 0x7fffff>;\n\n\t\ticu0: icu@80200 {\n\t\t\t#interrupt-cells = <1>;\n\t\t\tinterrupt-controller;\n\t\t\tcompatible = \"lantiq,icu\";\n\t\t\treg = <0x80200 0xc8>;\n\t\t};\n\n\t\twatchdog@803f0 {\n\t\t\tcompatible = \"lantiq,wdt\";\n\t\t\treg = <0x803f0 0x10>;\n\t\t};\n\t};\n\n\tsram@1f000000 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"lantiq,sram\", \"simple-bus\";\n\t\treg = <0x1f000000 0x800000>;\n\t\tranges = <0x0 0x1f000000 0x7fffff>;\n\n\t\teiu0: eiu@101000 {\n\t\t\t#interrupt-cells = <1>;\n\t\t\tinterrupt-controller;\n\t\t\tcompatible = \"lantiq,eiu-xway\";\n\t\t\treg = <0x101000 0x1000>;\n\t\t\tinterrupt-parent = <&icu0>;\n\t\t\tlantiq,eiu-irqs = <29 30 31>;\n\t\t};\n\n\t\tpmu0: pmu@102000 {\n\t\t\tcompatible = \"lantiq,pmu-xway\";\n\t\t\treg = <0x102000 0x1000>;\n\t\t};\n\n\t\tcgu0: cgu@103000 {\n\t\t\tcompatible = \"lantiq,cgu-xway\";\n\t\t\treg = <0x103000 0x1000>;\n\t\t\t#clock-cells = <1>;\n\t\t};\n\n\t\trcu0: rcu@203000 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\t\t\tcompatible = \"lantiq,ase-rcu\", \"simple-mfd\", \"syscon\";\n\t\t\treg = <0x203000 0x1000>;\n\t\t\tranges = <0x0 0x203000 0x100>;\n\t\t\tbig-endian;\n\n\t\t\treset: reset-controller@10 {\n\t\t\t\tcompatible = \"lantiq,danube-reset\";\n\t\t\t\treg = <0x10 4>, <0x14 4>;\n\n\t\t\t\t#reset-cells = <2>;\n\t\t\t};\n\n\t\t\tusb_phy: usb2-phy@18 {\n\t\t\t\tcompatible = \"lantiq,ase-usb2-phy\";\n\t\t\t\treg = <0x18 4>;\n\t\t\t\tstatus = \"disabled\";\n\n\t\t\t\tresets = <&reset 4 4>;\n\t\t\t\treset-names = \"ctrl\";\n\t\t\t\t#phy-cells = <0>;\n\t\t\t};\n\t\t};\n\t};\n\n\tfpi@10000000 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"lantiq,fpi\", \"simple-bus\";\n\t\tranges = <0x0 0x10000000 0xeefffff>;\n\t\treg = <0x10000000 0xef00000>;\n\n\t\tlocalbus: localbus@0 {\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <1>;\n\t\t\tranges = <0 0 0x0 0x3ffffff /* addrsel0 */\n\t\t\t\t1 0 0x4000000 0x4000010>; /* addsel1 */\n\t\t\tcompatible = \"lantiq,localbus\", \"simple-bus\";\n\t\t};\n\n\t\tspi: spi@e100800 {\n\t\t\tcompatible = \"lantiq,ase-spi\";\n\t\t\treg = <0xe100800 0x100>;\n\t\t\tinterrupt-parent = <&icu0>;\n\t\t\tinterrupts = <24 25 26>;\n\t\t\tinterrupt-names = \"spi_rx\", \"spi_tx\", \"spi_err\",\n\t\t\t\t\t\"spi_frm\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tpinctrl-names = \"default\";\n\t\t\tpinctrl-0 = <&spi_pins>, <&spi_cs4_pins>;\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tgptu@e100a00 {\n\t\t\tcompatible = \"lantiq,gptu-xway\";\n\t\t\treg = <0xe100a00 0x100>;\n\t\t\tinterrupt-parent = <&icu0>;\n\t\t\tinterrupts = <33 34 35 36 37 38>;\n\t\t};\n\n\t\tgpio: pinmux@e100b10 {\n\t\t\tcompatible = \"lantiq,ase-pinctrl\";\n\t\t\t#gpio-cells = <2>;\n\t\t\tgpio-controller;\n\t\t\treg = <0xe100b10 0xa0>;\n\n\t\t\tasc_pins: asc-pins {\n\t\t\t\tmux {\n\t\t\t\t\tlantiq,groups = \"asc\";\n\t\t\t\t\tlantiq,function = \"asc\";\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tmdio_pins: mdio {\n\t\t\t\tmux {\n\t\t\t\t\tlantiq,groups = \"mdio\";\n\t\t\t\t\tlantiq,function = \"mdio\";\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tspi_pins: spi {\n\t\t\t\tmux-0 {\n\t\t\t\t\tlantiq,groups = \"spi_di\";\n\t\t\t\t\tlantiq,function = \"spi\";\n\t\t\t\t};\n\t\t\t\tmux-1 {\n\t\t\t\t\tlantiq,groups = \"spi_do\", \"spi_clk\";\n\t\t\t\t\tlantiq,function = \"spi\";\n\t\t\t\t\tlantiq,output = <1>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tspi_cs4_pins: spi-cs4 {\n\t\t\t\tmux {\n\t\t\t\t\tlantiq,groups = \"spi_cs4\";\n\t\t\t\t\tlantiq,function = \"spi\";\n\t\t\t\t\tlantiq,output = <1>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tasc1: serial@e100c00 {\n\t\t\tcompatible = \"lantiq,asc\";\n\t\t\treg = <0xe100c00 0x400>;\n\t\t\tinterrupt-parent = <&icu0>;\n\t\t\tinterrupts = <72 74 75>;\n\t\t\tpinctrl-0 = <&asc_pins>;\n\t\t\tpinctrl-names = \"default\";\n\t\t};\n\n\t\tmei@e116000 {\n\t\t\tcompatible = \"lantiq,mei-xway\";\n\t\t\treg = <0xe116000 0x400>;\n\t\t\tinterrupt-parent = <&icu0>;\n\t\t\tinterrupts = <81>;\n\t\t};\n\n\t\tusb: usb@e101000 {\n\t\t\tcompatible = \"lantiq,ase-usb\";\n\t\t\treg = <0xe101000 0x1000\n\t\t\t\t0xe120000 0x3f000>;\n\t\t\tinterrupt-parent = <&icu0>;\n\t\t\tinterrupts = <39>;\n\t\t\tdr_mode = \"host\";\n\t\t\tphys = <&usb_phy>;\n\t\t\tphy-names = \"usb2-phy\";\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tdma0: dma@e104100 {\n\t\t\tcompatible = \"lantiq,dma-xway\";\n\t\t\treg = <0xe104100 0x800>;\n\t\t};\n\n\t\tebu0: ebu@e105300 {\n\t\t\tcompatible = \"lantiq,ebu-xway\";\n\t\t\treg = <0xe105300 0x100>;\n\t\t};\n\n\t\tppe@e234000 {\n\t\t\tcompatible = \"lantiq,ppe-ase\";\n\t\t\treg = <0xe234000 0x40000>;\n\t\t\tinterrupt-parent = <&icu0>;\n\t\t\tinterrupts = <85>;\n\t\t};\n\n\t\tgsw: etop@e180000 {\n\t\t\tcompatible = \"lantiq,etop-xway\";\n\t\t\treg = <0xe180000 0x40000>;\n\t\t\tinterrupt-parent = <&icu0>;\n\t\t\tinterrupts = <105 109>;\n\t\t\tpinctrl-0 = <&mdio_pins>;\n\t\t\tpinctrl-names = \"default\";\n\t\t\tlantiq,tx-burst-length = <4>;\n\t\t\tlantiq,rx-burst-length = <4>;\n\t\t};\n\t};\n\n\tadsl {\n\t\tcompatible = \"lantiq,adsl-ase\";\n\t};\n};\n"
  },
  {
    "path": "target/linux/lantiq/files/arch/mips/boot/dts/lantiq/amazonse_allnet_all0333cj.dts",
    "content": "#include \"amazonse.dtsi\"\n\n/ {\n\tcompatible = \"allnet,all0333cj\", \"lantiq,xway\", \"lantiq,ase\";\n\tmodel = \"Allnet ALL0333CJ DSL Modem\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyLTQ0,115200\";\n\n\t\taliases {\n\t\t\tled-boot = &power;\n\t\t\tled-failsafe = &power;\n\t\t\tled-running = &power;\n\t\t\tled-upgrade = &power;\n\n\t\t\tled-dsl = &dsl;\n\t\t\tled-internet = &online_green;\n\t\t};\n\t};\n\n\tmemory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x0 0x1000000>;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\t/* power led: red=off, green=on */\n\t\tpower: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"keep\";\n\t\t};\n\n\t\tlan: lan {\n\t\t\tlabel = \"green:lan\";\n\t\t\tgpios = <&gpio 3 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tdsl: dsl {\n\t\t\tlabel = \"green:dsl\";\n\t\t\tgpios = <&gpio 1 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tonline_green: online {\n\t\t\tlabel = \"green:online\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tonline_red {\n\t\t\tlabel = \"red:online\";\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&state_default>;\n\n\tstate_default: pinmux {\n\t\tkeys_in {\n\t\t\tlantiq,pins = \"io0\",/* \"io25\", */\"io29\";\n\t\t\tlantiq,pull = <2>;\n\t\t\tlantiq,open-drain = <1>;\n\t\t};\n\t};\n};\n\n&gsw {\n\tphy-mode = \"mii\";\n};\n\n&localbus {\n\tflash@0 {\n\t\tcompatible = \"lantiq,nor\";\n\t\tbank-width = <2>;\n\t\treg = <0 0x0 0x400000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"uboot\";\n\t\t\t\treg = <0x00000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@10000 {\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x10000 0x3ef200>;\n\t\t\t};\n\n\t\t\tpartition@3ff200 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x3ff200 0xc00>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@3ffe00 {\n\t\t\t\tlabel = \"dummy_bits\";\n\t\t\t\treg = <0x3ffe00 0x200>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/lantiq/files/arch/mips/boot/dts/lantiq/amazonse_netgear_dgn1000b.dts",
    "content": "#include \"amazonse.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"netgear,dgn1000b\", \"lantiq,xway\", \"lantiq,ase\";\n\tmodel = \"Netgear DGN1000B\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyLTQ0,115200\";\n\t};\n\n\taliases {\n\t\tled-boot = &power;\n\t\tled-failsafe = &power;\n\t\tled-running = &power;\n\t\tled-upgrade = &power;\n\n\t\tled-dsl = &dsl;\n\t\tled-internet = &online_green;\n\t};\n\n\tmemory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x0 0x1000000>;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <100>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t\trfkill {\n\t\t\tlabel = \"rfkill\";\n\t\t\tgpios = <&gpio 25 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RFKILL>;\n\t\t};\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio 29 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tdsl: dsl {\n\t\t\tlabel = \"green:dsl\";\n\t\t\tgpios = <&gpio 1 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t\tonline_green: online {\n\t\t\tlabel = \"green:online\";\n\t\t\tgpios = <&gpio 2 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t\tonline2 {\n\t\t\tlabel = \"red:online\";\n\t\t\tgpios = <&gpio 3 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t\twps {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t\tpower: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"keep\";\n\t\t};\n\t\t/*\n\t\t\tpower red is missing\n\t\t*/\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&state_default>;\n\n\tstate_default: pinmux {\n\t\tkeys_in {\n\t\t\tlantiq,pins = \"io0\",/* \"io25\", */\"io29\";\n\t\t\tlantiq,pull = <2>;\n\t\t\tlantiq,open-drain = <1>;\n\t\t};\n\t};\n};\n\n&gsw {\n\tphy-mode = \"mii\";\n\tmac-address = [ 00 11 22 33 44 55 ];\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@1 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <1>;\n\t\tspi-max-frequency = <5000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\treg = <0x0 0x20000>;\n\t\t\t\tlabel = \"SPI (RO) U-Boot Image\";\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\treg = <0x20000 0x10000>;\n\t\t\t\tlabel = \"ENV_MAC\";\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tlabel = \"DPF\";\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tlabel = \"NVRAM\";\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\treg = <0x50000 0x3a0000>;\n\t\t\t\tlabel = \"kernel\";\n\t\t\t};\n\t\t};\n\t};\n};\n\n&usb_phy {\n\tstatus = \"okay\";\n};\n\n&usb {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/lantiq/files/arch/mips/boot/dts/lantiq/ar9.dtsi",
    "content": "/dts-v1/;\n\n#include <dt-bindings/gpio/gpio.h>\n\n/ {\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\tcompatible = \"lantiq,xway\", \"lantiq,ar9\";\n\n\taliases {\n\t\tserial0 = &asc1;\n\t};\n\n\tchosen {\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu@0 {\n\t\t\tcompatible = \"mips,mips34K\";\n\t\t\treg = <0>;\n\t\t};\n\t};\n\n\treboot {\n\t\tcompatible = \"syscon-reboot\";\n\n\t\tregmap = <&rcu0>;\n\t\toffset = <0x10>;\n\t\tmask = <0x40000000>;\n\t};\n\n\tbiu@1f800000 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"lantiq,biu\", \"simple-bus\";\n\t\treg = <0x1f800000 0x800000>;\n\t\tranges = <0x0 0x1f800000 0x7fffff>;\n\n\t\ticu0: icu@80200 {\n\t\t\t#interrupt-cells = <1>;\n\t\t\tinterrupt-controller;\n\t\t\tcompatible = \"lantiq,icu\";\n\t\t\t/* TODO: AR9 should have ICU1 (like VR9) too */\n\t\t\treg = <0x80200 0xc8>;\n\t\t};\n\n\t\twatchdog@803f0 {\n\t\t\tcompatible = \"lantiq,xrx100-wdt\", \"lantiq,xrx100-wdt\";\n\t\t\treg = <0x803f0 0x10>;\n\n\t\t\tregmap = <&rcu0>;\n\t\t};\n\t};\n\n\tsram@1f000000 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"lantiq,sram\", \"simple-bus\";\n\t\treg = <0x1f000000 0x800000>;\n\t\tranges = <0x0 0x1f000000 0x7fffff>;\n\n\t\teiu0: eiu@101000 {\n\t\t\t#interrupt-cells = <1>;\n\t\t\tinterrupt-controller;\n\t\t\tcompatible = \"lantiq,eiu-xway\";\n\t\t\treg = <0x101000 0x1000>;\n\t\t\tinterrupt-parent = <&icu0>;\n\t\t\tlantiq,eiu-irqs = <166 135 66 40 41 42>;\n\t\t};\n\n\t\tpmu0: pmu@102000 {\n\t\t\tcompatible = \"lantiq,pmu-xway\";\n\t\t\treg = <0x102000 0x1000>;\n\t\t};\n\n\t\tcgu0: cgu@103000 {\n\t\t\tcompatible = \"lantiq,cgu-xway\";\n\t\t\treg = <0x103000 0x1000>;\n\t\t\t#clock-cells = <1>;\n\t\t};\n\n\t\trcu0: rcu@203000 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\t\t\tcompatible = \"lantiq,xrx100-rcu\", \"simple-mfd\", \"syscon\";\n\t\t\treg = <0x203000 0x1000>;\n\t\t\tranges = <0x0 0x203000 0x100>;\n\t\t\tbig-endian;\n\n\t\t\treset: reset-controller@10 {\n\t\t\t\tcompatible = \"lantiq,xrx100-reset\", \"lantiq,danube-reset\";\n\t\t\t\treg = <0x10 4>, <0x14 4>;\n\n\t\t\t\t#reset-cells = <2>;\n\t\t\t};\n\n\t\t\tusb_phy0: usb2-phy@18 {\n\t\t\t\tcompatible = \"lantiq,xrx100-usb2-phy\";\n\t\t\t\treg = <0x18 4>;\n\t\t\t\tstatus = \"disabled\";\n\n\t\t\t\tresets = <&reset 4 4>;\n\t\t\t\treset-names = \"ctrl\";\n\t\t\t\t#phy-cells = <0>;\n\t\t\t};\n\n\t\t\tusb_phy1: usb2-phy@34 {\n\t\t\t\tcompatible = \"lantiq,xrx100-usb2-phy\";\n\t\t\t\treg = <0x34 4>;\n\t\t\t\tstatus = \"disabled\";\n\n\t\t\t\tresets = <&reset 28 28>;\n\t\t\t\treset-names = \"ctrl\";\n\t\t\t\t#phy-cells = <0>;\n\t\t\t};\n\t\t};\n\t};\n\n\tfpi@10000000 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"lantiq,fpi\", \"simple-bus\";\n\t\tranges = <0x0 0x10000000 0xeefffff>;\n\t\treg = <0x10000000 0xef00000>;\n\n\t\tlocalbus: localbus@0 {\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <1>;\n\t\t\tranges = <0 0 0x0 0x3ffffff /* addrsel0 */\n\t\t\t\t1 0 0x4000000 0x4000010>; /* addsel1 */\n\t\t\tcompatible = \"lantiq,localbus\", \"simple-bus\";\n\t\t};\n\n\t\tgptu@e100a00 {\n\t\t\tcompatible = \"lantiq,gptu-xway\";\n\t\t\treg = <0xe100a00 0x100>;\n\t\t\tinterrupt-parent = <&icu0>;\n\t\t\tinterrupts = <126 127 128 129 130 131>;\n\t\t};\n\n\t\tasc0: serial@e100400 {\n\t\t\tcompatible = \"lantiq,asc\";\n\t\t\treg = <0xe100400 0x400>;\n\t\t\tinterrupt-parent = <&icu0>;\n\t\t\tinterrupts = <104 105 106>;\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tspi: spi@e100800 {\n\t\t\tcompatible = \"lantiq,xrx100-spi\";\n\t\t\treg = <0xe100800 0x100>;\n\t\t\tinterrupt-parent = <&icu0>;\n\t\t\tinterrupts = <22 23 24>;\n\t\t\tinterrupt-names = \"spi_rx\", \"spi_tx\", \"spi_err\",\n\t\t\t\t\t\"spi_frm\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tpinctrl-names = \"default\";\n\t\t\tpinctrl-0 = <&spi_pins>, <&spi_cs4_pins>;\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tgpio: pinmux@e100b10 {\n\t\t\tcompatible = \"lantiq,xrx100-pinctrl\";\n\t\t\t#gpio-cells = <2>;\n\t\t\tgpio-controller;\n\t\t\treg = <0xe100b10 0xa0>;\n\n\t\t\tmdio_pins: mdio {\n\t\t\t\tmux {\n\t\t\t\t\tlantiq,groups = \"mdio\";\n\t\t\t\t\tlantiq,function = \"mdio\";\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tnand_pins: nand {\n\t\t\t\tmux-0 {\n\t\t\t\t\tlantiq,groups = \"nand cle\", \"nand ale\",\n\t\t\t\t\t\t\t\"nand rd\";\n\t\t\t\t\tlantiq,function = \"ebu\";\n\t\t\t\t\tlantiq,output = <1>;\n\t\t\t\t\tlantiq,open-drain = <0>;\n\t\t\t\t\tlantiq,pull = <0>;\n\t\t\t\t};\n\t\t\t\tmux-1 {\n\t\t\t\t\tlantiq,groups = \"nand rdy\";\n\t\t\t\t\tlantiq,function = \"ebu\";\n\t\t\t\t\tlantiq,output = <0>;\n\t\t\t\t\tlantiq,pull = <2>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tnand_cs1_pins: nand-cs1 {\n\t\t\t\tmux {\n\t\t\t\t\tlantiq,groups = \"nand cs1\";\n\t\t\t\t\tlantiq,function = \"ebu\";\n\t\t\t\t\tlantiq,open-drain = <0>;\n\t\t\t\t\tlantiq,pull = <0>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tpci_gnt1_pins: pci-gnt1 {\n\t\t\t\tmux {\n\t\t\t\t\tlantiq,groups = \"gnt1\";\n\t\t\t\t\tlantiq,function = \"pci\";\n\t\t\t\t\tlantiq,output = <1>;\n\t\t\t\t\tlantiq,open-drain = <0>;\n\t\t\t\t\tlantiq,pull = <0>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tpci_gnt2_pins: pci-gnt2 {\n\t\t\t\tmux {\n\t\t\t\t\tlantiq,groups = \"gnt2\";\n\t\t\t\t\tlantiq,function = \"pci\";\n\t\t\t\t\tlantiq,output = <1>;\n\t\t\t\t\tlantiq,open-drain = <0>;\n\t\t\t\t\tlantiq,pull = <0>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tpci_gnt3_pins: pci-gnt3 {\n\t\t\t\tmux {\n\t\t\t\t\tlantiq,groups = \"gnt3\";\n\t\t\t\t\tlantiq,function = \"pci\";\n\t\t\t\t\tlantiq,output = <1>;\n\t\t\t\t\tlantiq,open-drain = <0>;\n\t\t\t\t\tlantiq,pull = <0>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tpci_gnt4_pins: pci-gnt4 {\n\t\t\t\tmux {\n\t\t\t\t\tlantiq,groups = \"gnt4\";\n\t\t\t\t\tlantiq,function = \"pci\";\n\t\t\t\t\tlantiq,output = <1>;\n\t\t\t\t\tlantiq,open-drain = <0>;\n\t\t\t\t\tlantiq,pull = <0>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tpci_req1_pins: pci-req1 {\n\t\t\t\tmux {\n\t\t\t\t\tlantiq,groups = \"req1\";\n\t\t\t\t\tlantiq,function = \"pci\";\n\t\t\t\t\tlantiq,output = <0>;\n\t\t\t\t\tlantiq,open-drain = <1>;\n\t\t\t\t\tlantiq,pull = <2>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tpci_req2_pins: pci-req2 {\n\t\t\t\tmux {\n\t\t\t\t\tlantiq,groups = \"req2\";\n\t\t\t\t\tlantiq,function = \"pci\";\n\t\t\t\t\tlantiq,output = <0>;\n\t\t\t\t\tlantiq,open-drain = <1>;\n\t\t\t\t\tlantiq,pull = <2>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tpci_req3_pins: pci-req3 {\n\t\t\t\tmux {\n\t\t\t\t\tlantiq,groups = \"req3\";\n\t\t\t\t\tlantiq,function = \"pci\";\n\t\t\t\t\tlantiq,output = <0>;\n\t\t\t\t\tlantiq,open-drain = <1>;\n\t\t\t\t\tlantiq,pull = <2>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tpci_req4_pins: pci-req4 {\n\t\t\t\tmux {\n\t\t\t\t\tlantiq,groups = \"req4\";\n\t\t\t\t\tlantiq,function = \"pci\";\n\t\t\t\t\tlantiq,output = <0>;\n\t\t\t\t\tlantiq,open-drain = <1>;\n\t\t\t\t\tlantiq,pull = <2>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tspi_pins: spi {\n\t\t\t\tmux-0 {\n\t\t\t\t\tlantiq,groups = \"spi_di\";\n\t\t\t\t\tlantiq,function = \"spi\";\n\t\t\t\t};\n\t\t\t\tmux-1 {\n\t\t\t\t\tlantiq,groups = \"spi_do\", \"spi_clk\";\n\t\t\t\t\tlantiq,function = \"spi\";\n\t\t\t\t\tlantiq,output = <1>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tspi_cs4_pins: spi-cs4 {\n\t\t\t\tmux {\n\t\t\t\t\tlantiq,groups = \"spi_cs4\";\n\t\t\t\t\tlantiq,function = \"spi\";\n\t\t\t\t\tlantiq,output = <1>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tstp_pins: stp {\n\t\t\t\tmux {\n\t\t\t\t\tlantiq,groups = \"stp\";\n\t\t\t\t\tlantiq,function = \"stp\";\n\t\t\t\t\tlantiq,pull = <0>;\n\t\t\t\t\tlantiq,open-drain = <0>;\n\t\t\t\t\tlantiq,output = <1>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tstp: stp@e100bb0 {\n\t\t\t#gpio-cells = <2>;\n\t\t\tcompatible = \"lantiq,gpio-stp-xway\";\n\t\t\tgpio-controller;\n\t\t\treg = <0xe100bb0 0x40>;\n\n\t\t\tpinctrl-0 = <&stp_pins>;\n\t\t\tpinctrl-names = \"default\";\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tasc1: serial@e100c00 {\n\t\t\tcompatible = \"lantiq,asc\";\n\t\t\treg = <0xe100c00 0x400>;\n\t\t\tinterrupt-parent = <&icu0>;\n\t\t\tinterrupts = <112 113 114>;\n\t\t};\n\n\t\tusb0: usb@e101000 {\n\t\t\tcompatible = \"lantiq,arx100-usb\";\n\t\t\treg = <0xe101000 0x1000\n\t\t\t\t0xe120000 0x3f000>;\n\t\t\tinterrupt-parent = <&icu0>;\n\t\t\tinterrupts = <62 91>;\n\t\t\tdr_mode = \"host\";\n\t\t\tphys = <&usb_phy0>;\n\t\t\tphy-names = \"usb2-phy\";\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tusb1: usb@e106000 {\n\t\t\tcompatible = \"lantiq,arx100-usb\";\n\t\t\treg = <0xe106000 0x1000\n\t\t\t\t0xe1e0000 0x3f000>;\n\t\t\tinterrupt-parent = <&icu0>;\n\t\t\tinterrupts = <91>;\n\t\t\tdr_mode = \"host\";\n\t\t\tphys = <&usb_phy1>;\n\t\t\tphy-names = \"usb2-phy\";\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tdeu@e103100 {\n\t\t\tcompatible = \"lantiq,deu-arx100\";\n\t\t\treg = <0xe103100 0xf00>;\n\t\t};\n\n\t\tdma0: dma@e104100 {\n\t\t\tcompatible = \"lantiq,dma-xway\";\n\t\t\treg = <0xe104100 0x800>;\n\t\t};\n\n\t\tebu0: ebu@e105300 {\n\t\t\tcompatible = \"lantiq,ebu-xway\";\n\t\t\treg = <0xe105300 0x100>;\n\t\t};\n\n\t\tmei@e116000 {\n\t\t\tcompatible = \"lantiq,mei-xway\";\n\t\t\treg = <0xe116000 0x9c>;\n\t\t\tinterrupt-parent = <&icu0>;\n\t\t\tinterrupts = <63>;\n\t\t};\n\n\t\tgsw: etop@e180000 {\n\t\t\tcompatible = \"lantiq,etop-xway\";\n\t\t\treg = <0xe180000 0x40000\n\t\t\t\t0xe108000 0x200>;\n\t\t\tinterrupt-parent = <&icu0>;\n\t\t\tinterrupts = <73 72>;\n\t\t\tpinctrl-0 = <&mdio_pins>;\n\t\t\tpinctrl-names = \"default\";\n\t\t\tlantiq,tx-burst-length = <8>;\n\t\t\tlantiq,rx-burst-length = <8>;\n\t\t};\n\n\t\tppe@e234000 {\n\t\t\tcompatible = \"lantiq,ppe-arx100\";\n\t\t\treg = <0xe234000 0x3ffd>;\n\t\t\tinterrupt-parent = <&icu0>;\n\t\t\tinterrupts = <96>;\n\t\t};\n\n\t\tpci0: pci@e105400 {\n\t\t\tstatus = \"disabled\";\n\t\t\t#address-cells = <3>;\n\t\t\t#size-cells = <2>;\n\t\t\t#interrupt-cells = <1>;\n\t\t\tcompatible = \"lantiq,pci-xway\";\n\t\t\tbus-range = <0x0 0x0>;\n\t\t\tranges = <0x2000000 0 0x8000000 0x8000000 0 0x2000000\t/* pci memory */\n\t\t\t\t  0x1000000 0 0x00000000 0xae00000 0 0x200000>;\t/* io space */\n\t\t\treg = <0x7000000 0x8000\t\t/* config space */\n\t\t\t\t0xe105400 0x400>;\t/* pci bridge */\n\t\t\tlantiq,bus-clock = <33333333>;\n\t\t\tinterrupt-map-mask = <0xf800 0x0 0x0 0x7>;\n\t\t\tinterrupt-map = <0x7000 0 0 1 &icu0 30 1>;\n\t\t\treq-mask = <0x1>;\n\n\t\t\tdevice_type = \"pci\";\n\t\t};\n\t};\n\n\tadsl {\n\t\tcompatible = \"lantiq,adsl-arx100\";\n\t};\n};\n"
  },
  {
    "path": "target/linux/lantiq/files/arch/mips/boot/dts/lantiq/ar9_avm_fritz7312.dts",
    "content": "#include \"ar9.dtsi\"\n\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/mtd/partitions/uimage.h>\n\n/ {\n\tcompatible = \"avm,fritz7312\", \"lantiq,xway\", \"lantiq,ar9\";\n\tmodel = \"AVM FRITZ!Box 7312\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyLTQ0,115200\";\n\t};\n\n\taliases {\n\t\tled-boot = &power;\n\t\tled-failsafe = &power;\n\t\tled-running = &power;\n\t\tled-upgrade = &power;\n\n\t\tled-dsl = &info_green;\n\t\tled-wifi = &wlan;\n\t};\n\n\tmemory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x0 0x4000000>;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <100>;\n\n\t\twlan {\n\t\t\tlabel = \"wlan\";\n\t\t\tgpios = <&gpio 1 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RFKILL>;\n\t\t};\n\t\tdect {\n\t\t\tlabel = \"dect\";\n\t\t\tgpios = <&gpio 2 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_PHONE>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tpower: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 44 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"keep\";\n\t\t};\n\t\tvoice {\n\t\t\tlabel = \"green:fon\";\n\t\t\tgpios = <&gpio 47 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tdect {\n\t\t\tlabel = \"green:dect\";\n\t\t\tgpios = <&gpio 38 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\twlan: wlan {\n\t\t\tlabel = \"green:wlan\";\n\t\t\tgpios = <&gpio 37 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tinfo_green: info_green {\n\t\t\tlabel = \"green:info\";\n\t\t\tgpios = <&gpio 35 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&state_default>;\n\n\tstate_default: pinmux {\n\t\tar8030-intr {\n\t\t\tlantiq,groups = \"exin3\";\n\t\t\tlantiq,function = \"exin\";\n\t\t\tlantiq,pull = <2>;\n\t\t\tlantiq,output = <0>;\n\t\t};\n\t\tar8030-clk {\n\t\t\tlantiq,groups = \"clkout2\";\n\t\t\tlantiq,output = <1>;\n\t\t\tlantiq,open-drain;\n\t\t};\n\t\tar8030-rst {\n\t\t\tlantiq,pins = \"io34\";\n\t\t\tlantiq,output = <1>;\n\t\t\tlantiq,pull = <2>;\n\t\t\tlantiq,open-drain;\n\t\t};\n\t};\n};\n\n&gsw {\n\tphy-mode = \"rmii\";\n\tphy-handle = <&phy0>;\n\tnvmem-cells = <&macaddr_ath9k_cal_a91>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <(-2)>;\n\n\tmdio-bus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tphy0: ethernet-phy@0 {\n\t\t\treg = <0>;\n\t\t\treset-gpios = <&gpio 34 GPIO_ACTIVE_LOW>;\n\t\t\tmax-speed = <100>;\n\t\t};\n\t};\n};\n\n&localbus {\n\tflash@0 {\n\t\tcompatible = \"lantiq,nor\";\n\t\tbank-width = <2>;\n\t\treg = <0 0x0 0x1000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tath9k_cal: partition@0 {\n\t\t\t\tlabel = \"urlader\";\n\t\t\t\treg = <0x00000 0x20000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\tcompatible = \"openwrt,uimage\", \"denx,uimage\";\n\t\t\t\treg = <0x20000 0xf60000>;\n\t\t\t\topenwrt,ih-magic = <IH_MAGIC_OKLI>;\n\t\t\t\topenwrt,offset = <0x11000>;\n\t\t\t};\n\n\t\t\tpartition@f80000 {\n\t\t\t\tlabel = \"tffs (1)\";\n\t\t\t\treg = <0xf80000 0x40000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@fc0000 {\n\t\t\t\tlabel = \"tffs (2)\";\n\t\t\t\treg = <0xfc0000 0x40000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pci0 {\n\tstatus = \"okay\";\n\n\tpinctrl-0 = <&pci_gnt1_pins>, <&pci_gnt2_pins>,\n\t\t    <&pci_gnt3_pins>, <&pci_gnt4_pins>,\n\t\t    <&pci_req1_pins>, <&pci_req2_pins>,\n\t\t    <&pci_req4_pins>;\n\tpinctrl-names = \"default\";\n\n\treq-mask = <0xf>;\n\tgpio-reset = <&gpio 21 GPIO_ACTIVE_LOW>;\n\n\twifi@0,0 {\n\t\tcompatible = \"pci0,0\";\n\t\treg = <0x7000 0 0 0 0>;\n\t\tqca,no-eeprom; /* load from ath9k-eeprom-pci-0000:00:0e.0.bin */\n\t};\n};\n\n&ath9k_cal {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_ath9k_cal_a91: macaddr@a91 {\n\t\treg = <0xa91 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/lantiq/files/arch/mips/boot/dts/lantiq/ar9_avm_fritz7320.dts",
    "content": "#include \"ar9.dtsi\"\n\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/mtd/partitions/uimage.h>\n\n/ {\n\tcompatible = \"avm,fritz7320\", \"lantiq,xway\", \"lantiq,ar9\";\n\tmodel = \"AVM FRITZ!Box 7320\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyLTQ0,115200\";\n\t};\n\n\taliases {\n\t\tled-boot = &power;\n\t\tled-failsafe = &power;\n\t\tled-running = &power;\n\t\tled-upgrade = &power;\n\n\t\tled-dsl = &info_green;\n\t\tled-wifi = &wlan;\n\t};\n\n\tmemory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x0 0x4000000>;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <100>;\n\n\t\trfkill {\n\t\t\tlabel = \"rfkill\";\n\t\t\tgpios = <&gpio 1 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RFKILL>;\n\t\t};\n\t\tdect {\n\t\t\tlabel = \"dect\";\n\t\t\tgpios = <&gpio 2 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_PHONE>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tpower: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 44 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"keep\";\n\t\t};\n\t\tvoice {\n\t\t\tlabel = \"green:fon\";\n\t\t\tgpios = <&gpio 47 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tdect {\n\t\t\tlabel = \"green:dect\";\n\t\t\tgpios = <&gpio 38 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\twlan: wlan {\n\t\t\tlabel = \"green:wlan\";\n\t\t\tgpios = <&gpio 37 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tinfo_green: info_green {\n\t\t\tlabel = \"green:info\";\n\t\t\tgpios = <&gpio 35 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tinfo_red {\n\t\t\tlabel = \"red:info\";\n\t\t\tgpios = <&gpio 45 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tusb0_vbus: regulator-usb0-vbus {\n\t\tcompatible = \"regulator-fixed\";\n\n\t\tregulator-name = \"USB0_VBUS\";\n\n\t\tregulator-min-microvolt = <5000000>;\n\t\tregulator-max-microvolt = <5000000>;\n\n\t\tgpio = <&gpio 50 GPIO_ACTIVE_HIGH>;\n\t\tenable-active-high;\n\t};\n\n\tusb1_vbus: regulator-usb1-vbus {\n\t\tcompatible = \"regulator-fixed\";\n\n\t\tregulator-name = \"USB1_VBUS\";\n\n\t\tregulator-min-microvolt = <5000000>;\n\t\tregulator-max-microvolt = <5000000>;\n\n\t\tgpio = <&gpio 51 GPIO_ACTIVE_HIGH>;\n\t\tenable-active-high;\n\t};\n};\n\n&gsw {\n\tphy-mode = \"mii\";\n\tnvmem-cells = <&macaddr_ath9k_cal_a91>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <(-2)>;\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&state_default>;\n\n\tstate_default: pinmux {\n\t\tusb0_vbus {\n\t\t\tlantiq,pins = \"io50\";\n\t\t\tlantiq,pull = <0>;\n\t\t\tlantiq,open-drain = <0>;\n\t\t\tlantiq,output = <1>;\n\t\t};\n\t\tusb1_vbus {\n\t\t\tlantiq,pins = \"io51\";\n\t\t\tlantiq,pull = <0>;\n\t\t\tlantiq,open-drain = <0>;\n\t\t\tlantiq,output = <1>;\n\t\t};\n\t};\n};\n\n&localbus {\n\tflash@0 {\n\t\tcompatible = \"lantiq,nor\";\n\t\tbank-width = <2>;\n\t\treg = <0 0x0 0x1000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tath9k_cal: partition@0 {\n\t\t\t\tlabel = \"urlader\";\n\t\t\t\treg = <0x00000 0x20000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tcompatible = \"openwrt,uimage\", \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x20000 0xf60000>;\n\t\t\t\topenwrt,ih-magic = <IH_MAGIC_OKLI>;\n\t\t\t\topenwrt,offset = <0x11000>;\n\t\t\t};\n\n\t\t\tpartition@f80000 {\n\t\t\t\tlabel = \"tffs (1)\";\n\t\t\t\treg = <0xf80000 0x40000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@fc0000 {\n\t\t\t\tlabel = \"tffs (2)\";\n\t\t\t\treg = <0xfc0000 0x40000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pci0 {\n\tstatus = \"okay\";\n\n\tpinctrl-0 = <&pci_gnt1_pins>, <&pci_gnt2_pins>,\n\t\t    <&pci_gnt3_pins>, <&pci_gnt4_pins>,\n\t\t    <&pci_req1_pins>, <&pci_req2_pins>,\n\t\t    <&pci_req3_pins>, <&pci_req4_pins>;\n\n\treq-mask = <0xf>;\n\tgpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>;\n\n\twifi@0,0 {\n\t\tcompatible = \"pci0,0\";\n\t\treg = <0x7000 0 0 0 0>;\n\t\tqca,no-eeprom; /* load from ath9k-eeprom-pci-0000:00:0e.0.bin */\n\t};\n};\n\n&usb_phy0 {\n\tstatus = \"okay\";\n};\n\n&usb_phy1 {\n\tstatus = \"okay\";\n};\n\n&usb0 {\n\tstatus = \"okay\";\n\tvbus-supply = <&usb0_vbus>;\n};\n\n&usb1 {\n\tstatus = \"okay\";\n\tvbus-supply = <&usb1_vbus>;\n};\n\n&ath9k_cal {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_ath9k_cal_a91: macaddr@a91 {\n\t\treg = <0xa91 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/lantiq/files/arch/mips/boot/dts/lantiq/ar9_bt_homehub-v3a.dts",
    "content": "#include \"ar9.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"bt,homehub-v3a\", \"lantiq,xway\", \"lantiq,ar9\";\n\tmodel = \"BT Home Hub 3A\";  /* SoC: Lantiq ar9 @ 333MHz */\n\n\tchosen {\n\t\tbootargs = \"console=ttyLTQ0,115200\";\n\t};\n\n\taliases {\n\t\tled-boot = &power_orange;\n\t\tled-failsafe = &power_red;\n\t\tled-running = &power_blue;\n\t\tled-upgrade = &power_blue;\n\n\t\tled-dsl = &broadband_blue;\n\t\tled-wifi = &wireless_blue;\n\t};\n\n\tmemory@0 {\t\t\t\t  /* RAM: Samsung K4H511638F-LC 64MB */\n\t\tdevice_type = \"memory\";\n\t\treg = <0x0 0x4000000>;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <100>;\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 54 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t\trestart {\n\t\t\tlabel = \"restart\";\n\t\t\tgpios = <&gpio 52 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_POWER>;\n\t\t};\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio 53 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twireless-red {\n\t\t\tlabel = \"red:wireless\";\n\t\t\tgpios = <&gpio 2 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\twireless-orange {\n\t\t\tlabel = \"orange:wireless\";\n\t\t\tgpios = <&gpio 6 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\twireless_blue: wireless-blue {\n\t\t\tlabel = \"blue:wireless\";\n\t\t\tgpios = <&gpio 9 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tbroadband-red {\n\t\t\tlabel = \"red:broadband\";\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tbroadband-orange {\n\t\t\tlabel = \"orange:broadband\";\n\t\t\tgpios = <&gpio 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tbroadband_blue: broadband-blue {\n\t\t\tlabel = \"blue:broadband\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tpower_red: power-red {\n\t\t\tlabel = \"red:power\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tpower_orange: power-orange {\n\t\t\tlabel = \"orange:power\";\n\t\t\tgpios = <&gpio 5 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"keep\";\n\t\t};\n\t\tpower_blue: power-blue {\n\t\t\tlabel = \"blue:power\";\n\t\t\tgpios = <&gpio 1 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tusb_vbus: regulator-usb-vbus {\n\t\tcompatible = \"regulator-fixed\";\n\n\t\tregulator-name = \"USB_VBUS\";\n\n\t\tregulator-min-microvolt = <5000000>;\n\t\tregulator-max-microvolt = <5000000>;\n\n\t\tgpio = <&gpio 33 GPIO_ACTIVE_HIGH>;\n\t\tenable-active-high;\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&state_default>;\n\n\tstate_default: pinmux {\n\t\tpci_rst {\n\t\t\tlantiq,pins = \"io21\";\n\t\t\tlantiq,output = <1>;\n\t\t\tlantiq,open-drain = <0>;\n\t\t};\n\t};\n};\n\n&gsw {\n\tphy-mode = \"rgmii\";\n};\n\n&localbus {\n\tflash@1 {\t\t  /* NAND Flash: Samsung K9F5608U0D-JIB0 32MB */\n\t\tcompatible = \"lantiq,nand-xway\";\n\t\tlantiq,cs = <1>;\n\t\tbank-width = <2>;\n\t\treg = <1 0x0 0x2000000 >;\n\t\treq-mask = <0x1>;  /* PCI request lines to mask during NAND access */\n\n\t\tpinctrl-0 = <&nand_pins>, <&nand_cs1_pins>;\n\t\tpinctrl-names = \"default\";\n\n\t\tnand-use-soft-ecc-engine;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"preboot\";\n\t\t\t\treg = <0x00000 0x8000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@8000 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x8000 0x05c000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@64000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x64000 0x004000>;\n\t\t\t};\n\t\t\tath9k_cal: partition@68000 {\n\t\t\t\tlabel = \"art-copy\";\n\t\t\t\treg = <0x68000 0x004000>;\n\t\t\t};\n\t\t\tpartition@6c000 {\n\t\t\t\tlabel = \"kernel\";\n\t\t\t\treg = <0x6c000 0x200000>;\n\t\t\t};\n\t\t\tpartition@26c000 {\n\t\t\t\tlabel = \"ubi\";\n\t\t\t\treg = <0x26c000 0x1d94000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pci0 {\n\tstatus = \"okay\";\n\n\tpinctrl-0 = <&pci_gnt1_pins>, <&pci_req1_pins>;\n\tpinctrl-names = \"default\";\n\n\tgpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>;\n\n\twifi@7000 {\n\t\treg = <0x7000 0 0 0 0>;\n\t\tqca,no-eeprom; /* load from ath9k-eeprom-pci-0000:00:0e.0.bin */\n\t};\n};\n\n&usb_phy0 {\n\tstatus = \"okay\";\n};\n\n&usb0 {\n\tstatus = \"okay\";\n\tvbus-supply = <&usb_vbus>;\n};\n"
  },
  {
    "path": "target/linux/lantiq/files/arch/mips/boot/dts/lantiq/ar9_buffalo_wbmr-hp-g300h.dts",
    "content": "#include \"ar9.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"buffalo,wbmr-hp-g300h\", \"lantiq,xway\", \"lantiq,ar9\";\n\tmodel = \"Buffalo WBMR-HP-G300H\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyLTQ0,115200\";\n\t};\n\n\taliases {\n\t\tled-boot = &power_green;\n\t\tled-failsafe = &power_red;\n\t\tled-running = &power_green;\n\t\tled-upgrade = &power_green;\n\n\t\tled-dsl = &dsl;\n\t\tled-internet = &online_green;\n\t\tled-usb = &led_usb;\n\t\tled-wifi = &wifi;\n\t};\n\n\tmemory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x0 0x4000000>;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <100>;\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 37 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t\teject {\n\t\t\tlabel = \"eject\";\n\t\t\tgpios = <&gpio 34 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_EJECTCD>;\n\t\t};\n\t\tmovie {\n\t\t\tlabel = \"movie\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_VIDEO>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tpower_green: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 1 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"keep\";\n\t\t};\n\t\tpower_red: power2 {\n\t\t\tlabel = \"red:power\";\n\t\t\tgpios = <&gpio 5 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tsecurity {\n\t\t\tlabel = \"yellow:security\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\twifi: wifi {\n\t\t\tlabel = \"green:wireless\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tdsl: dsl {\n\t\t\tlabel = \"green:dsl\";\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tonline_green: online {\n\t\t\tlabel = \"green:internet\";\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tonline2 {\n\t\t\tlabel = \"red:internet\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tmovie {\n\t\t\tlabel = \"blue:movie\";\n\t\t\tgpios = <&gpio 20 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tled_usb: usb {\n\t\t\tlabel = \"green:usb\";\n\t\t\tgpios = <&gpio 28 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\tusb_vbus: regulator-usb-vbus {\n\t\tcompatible = \"regulator-fixed\";\n\n\t\tregulator-name = \"USB_VBUS\";\n\n\t\tregulator-min-microvolt = <5000000>;\n\t\tregulator-max-microvolt = <5000000>;\n\n\t\tgpio = <&gpio 36 GPIO_ACTIVE_HIGH>;\n\t\tenable-active-high;\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&state_default>;\n\n\tstate_default: pinmux {\n\t\tpci-in {\n\t\t\tlantiq,groups = \"req1\";\n\t\t\tlantiq,output = <0>;\n\t\t\tlantiq,open-drain = <1>;\n\t\t\tlantiq,pull = <2>;\n\t\t};\n\t\tpci-out {\n\t\t\tlantiq,groups = \"gnt1\";\n\t\t\tlantiq,output = <1>;\n\t\t\tlantiq,pull = <0>;\n\t\t};\n\t\tpci_rst {\n\t\t\tlantiq,pins = \"io21\";\n\t\t\tlantiq,pull = <0>;\n\t\t\tlantiq,output = <1>;\n\t\t};\n\t};\n};\n\n&gsw {\n\tphy-mode = \"rgmii\";\n\tnvmem-cells = <&macaddr_boardconfig_10024>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&pci0 {\n\tstatus = \"okay\";\n};\n\n&localbus {\n\tflash@0 {\n\t\tcompatible = \"lantiq,nor\";\n\t\tbank-width = <2>;\n\t\treg = <0 0x0 0x2000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"uboot\";\n\t\t\t\treg = <0x00000 0x40000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x40000 0x20000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x60000 0x1f20000>;\n\t\t\t};\n\n\t\t\tboardconfig: partition@1fc0000 {\n\t\t\t\tlabel = \"board\";\n\t\t\t\treg = <0x1fc0000 0x20000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@1fe0000 {\n\t\t\t\tlabel = \"calibration\";\n\t\t\t\treg = <0x1fe0000 0x20000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&usb_phy0 {\n\tstatus = \"okay\";\n};\n\n&usb0 {\n\tstatus = \"okay\";\n\tvbus-supply = <&usb_vbus>;\n};\n\n&boardconfig {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_boardconfig_10024: macaddr@10024 {\n\t\treg = <0x10024 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/lantiq/files/arch/mips/boot/dts/lantiq/ar9_netgear_dgn3500.dts",
    "content": "#include \"ar9_netgear_dgn3500.dtsi\"\n\n/ {\n\tcompatible = \"netgear,dgn3500\", \"lantiq,xway\", \"lantiq,ar9\";\n\tmodel = \"Netgear DGN3500\";\n};\n"
  },
  {
    "path": "target/linux/lantiq/files/arch/mips/boot/dts/lantiq/ar9_netgear_dgn3500.dtsi",
    "content": "#include \"ar9.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tchosen {\n\t\tbootargs = \"root= console=ttyLTQ0,115200\";\n\t};\n\n\taliases {\n\t\tled-boot = &power_green;\n\t\tled-failsafe = &power_red;\n\t\tled-running = &power_green;\n\t\tled-upgrade = &power_green;\n\n\t\tled-dsl = &dsl;\n\t\tled-internet = &internet;\n\t\tled-usb = &led_usb;\n\t\tled-wifi = &wifi_green;\n\t};\n\n\tmemory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x0 0x4000000>;\n\t};\n\n\trtl8366rb {\n\t\tcompatible = \"realtek,rtl8366rb\";\n\t\tgpio-sda = <&gpio 35 GPIO_ACTIVE_HIGH>;\n\t\tgpio-sck = <&gpio 37 GPIO_ACTIVE_HIGH>;\n\n\t\trealtek,initvals = <\n\t\t\t0x0000 0x0830\n\t\t\t0x0400 0x8130\n\t\t\t0x000a 0x83ed\n\t\t\t0x0f51 0x0017\n\t\t\t0x02f5 0x0048\n\t\t\t0x02fa 0xffdf\n\t\t\t0x02fb 0xffe0\n\t\t\t0x0450 0x0000\n\t\t\t0x0401 0x0000\n\t\t\t0x0431 0x0960\n\t\t>;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <100>;\n\n\t\trfkill {\n\t\t\tlabel = \"rfkill\";\n\t\t\tgpios = <&gpio 36 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RFKILL>;\n\t\t};\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio 54 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 53 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tinternet: internet {\n\t\t\tlabel = \"green:internet\";\n\t\t\tgpios = <&gpio 2 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tinternet2 {\n\t\t\tlabel = \"red:internet\";\n\t\t\tgpios = <&gpio 30 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tdsl: dsl {\n\t\t\tlabel = \"green:dsl\";\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tled_usb: usb {\n\t\t\tlabel = \"green:usb\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tpower_green: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 34 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"keep\";\n\t\t};\n\t\tpower_red: power2 {\n\t\t\tlabel = \"red:power\";\n\t\t\tgpios = <&gpio 39 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\twifi_green: wifi {\n\t\t\tlabel = \"green:wireless\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\twifi2 {\n\t\t\tlabel = \"amber:wireless\";\n\t\t\tgpios = <&gpio 51 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\twps {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&gpio 52 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&state_default>;\n\n\tstate_default: pinmux {\n\t\texin {\n\t\t\tlantiq,groups = \"exin1\";\n\t\t\tlantiq,function = \"exin\";\n\t\t};\n\t};\n};\n\n&gsw {\n\tphy-mode = \"mii\";\n};\n\n&pci0 {\n\tstatus = \"okay\";\n\n\tpinctrl-0 = <&pci_gnt1_pins>, <&pci_req1_pins>;\n\tpinctrl-names = \"default\";\n\n\tgpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>;\n\n\twifi@168c,0029 {\n\t\tcompatible = \"pci168c,0029\";\n\t\treg = <0x7000 0 0 0 0>;\n\t\tqca,no-eeprom; /* load from ath9k-eeprom-pci-0000:00:0e.0.bin */\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@4 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <4>;\n\t\tspi-max-frequency = <20000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\treg = <0x0 0x10000>;\n\t\t\t\tlabel = \"uboot\";\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@10000 {\n\t\t\t\treg = <0x10000 0x10000>;\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tath9k_cal: partition@20000 {\n\t\t\t\treg = <0x20000 0x10000>;\n\t\t\t\tlabel = \"calibration\";\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\treg = <0x50000 0xfa0000>;\n\t\t\t\tlabel = \"firmware\";\n\t\t\t};\n\t\t};\n\t};\n};\n\n&usb_phy0 {\n\tstatus = \"okay\";\n};\n\n&usb0 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/lantiq/files/arch/mips/boot/dts/lantiq/ar9_netgear_dgn3500b.dts",
    "content": "#include \"ar9_netgear_dgn3500.dtsi\"\n\n/ {\n\tcompatible = \"netgear,dgn3500b\", \"lantiq,xway\", \"lantiq,ar9\";\n\tmodel = \"Netgear DGN3500B\";\n};\n"
  },
  {
    "path": "target/linux/lantiq/files/arch/mips/boot/dts/lantiq/ar9_zte_h201l.dts",
    "content": "#include \"ar9.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"zte,h201l\", \"lantiq,xway\", \"lantiq,ar9\";\n\tmodel = \"ZTE H210L\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyLTQ0,115200\";\n\t};\n\n\taliases {\n\t\tled-boot = &power_green;\n\t\tled-failsafe = &power_green;\n\t\tled-running = &power_green;\n\t\tled-upgrade = &power_green;\n\n\t\tled-dsl = &dsl;\n\t\tled-internet = &online;\n\t\tled-usb = &led_usb;\n\t\tled-wifi = &wifi;\n\t};\n\n\tmemory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x0 0x2000000>;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <100>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 53 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio 54 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t\trfkill {\n\t\t\tlabel = \"rfkill\";\n\t\t\tgpios = <&gpio 55 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RFKILL>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tpower_green: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 19 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"keep\";\n\t\t};\n\t\tonline: online {\n\t\t\tlabel = \"green:internet\";\n\t\t\tgpios = <&gpio 37 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tdsl: dsl {\n\t\t\tlabel = \"green:dsl\";\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tphone {\n\t\t\tlabel = \"green:phone\";\n\t\t\tgpios = <&gpio 39 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\twps {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\twifi: wifi {\n\t\t\tlabel = \"green:wlan\";\n\t\t\tgpios = <&gpio 6 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tled_usb: usb {\n\t\t\tlabel = \"green:usb\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tgpio_export {\n\t\tcompatible = \"gpio-export\";\n\t\t#size-cells = <0>;\n\n\t\tswitch {\n\t\t\tgpio-export,name = \"switch\";\n\t\t\tgpio-export,output = <1>;\n\t\t\tgpios = <&gpio 38 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t\tusb {\n\t\t\tgpio-export,name = \"usb\";\n\t\t\tgpio-export,output = <1>;\n\t\t\tgpios = <&gpio 28 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t\twifi {\n\t\t\tgpio-export,name = \"wifi\";\n\t\t\tgpio-export,output = <1>;\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n\n\tusb_vbus: regulator-usb-vbus {\n\t\tcompatible = \"regulator-fixed\";\n\n\t\tregulator-name = \"USB_VBUS\";\n\n\t\tregulator-min-microvolt = <5000000>;\n\t\tregulator-max-microvolt = <5000000>;\n\n\t\tgpio = <&gpio 36 GPIO_ACTIVE_HIGH>;\n\t\tenable-active-high;\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&state_default>;\n\n\tstate_default: pinmux {\n\t};\n};\n\n&gsw {\n\tphy-mode = \"rgmii\";\n};\n\n&localbus {\n\tflash@0 {\n\t\tcompatible = \"lantiq,nor\";\n\t\tbank-width = <2>;\n\t\treg = <0 0x0 0x2000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"uboot\";\n\t\t\t\treg = <0x00000 0x20000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x20000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x30000 0x7d0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&usb_phy0 {\n\tstatus = \"okay\";\n};\n\n\n&usb0 {\n\tstatus = \"okay\";\n\tvbus-supply = <&usb_vbus>;\n};\n"
  },
  {
    "path": "target/linux/lantiq/files/arch/mips/boot/dts/lantiq/ar9_zyxel_p-2601hn.dts",
    "content": "#include \"ar9.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"zyxel,p-2601hn\", \"lantiq,xway\", \"lantiq,ar9\";\n\tmodel = \"ZyXEL P-2601HN-Fx\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyLTQ0,115200\";\n\t};\n\n\taliases {\n\t\tled-boot = &power_green;\n\t\tled-failsafe = &power_red;\n\t\tled-running = &power_green;\n\t\tled-upgrade = &power_green;\n\n\t\tled-dsl = &dsl;\n\t\tled-internet = &online;\n\t\tled-wifi = &wifi;\n\t};\n\n\tmemory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x0 0x4000000>;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <100>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 53 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t\trfkill {\n\t\t\tlabel = \"rfkill\";\n\t\t\tgpios = <&gpio 54 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RFKILL>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tpower_green: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&stp 11 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"keep\";\n\t\t};\n\t\tpower_red: power2 {\n\t\t\tlabel = \"red:power\";\n\t\t\tgpios = <&gpio 29 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tonline: online {\n\t\t\tlabel = \"green:internet\";\n\t\t\tgpios = <&stp 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tonline2 {\n\t\t\tlabel = \"red:internet\";\n\t\t\tgpios = <&stp 12 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tdsl: dsl {\n\t\t\tlabel = \"green:dsl\";\n\t\t\tgpios = <&stp 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tphone {\n\t\t\tlabel = \"green:phone\";\n\t\t\tgpios = <&stp 9 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tphone2 {\n\t\t\tlabel = \"orange:phone\";\n\t\t\tgpios = <&stp 8 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\twifi: wifi {\n\t\t\tlabel = \"green:wireless\";\n\t\t\tgpios = <&stp 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\twifi2 {\n\t\t\tlabel = \"orange:wireless\";\n\t\t\tgpios = <&stp 10 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tgpio_export {\n\t\tcompatible = \"gpio-export\";\n\t\t#size-cells = <0>;\n\n\t\tswitch {\n\t\t\tgpio-export,name = \"switch\";\n\t\t\tgpio-export,output = <1>;\n\t\t\tgpios = <&gpio 50 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n\n\tusb_vbus: regulator-usb-vbus {\n\t\tcompatible = \"regulator-fixed\";\n\n\t\tregulator-name = \"USB_VBUS\";\n\n\t\tregulator-min-microvolt = <5000000>;\n\t\tregulator-max-microvolt = <5000000>;\n\n\t\tgpio = <&gpio 9 GPIO_ACTIVE_HIGH>;\n\t\tenable-active-high;\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&state_default>;\n\n\tstate_default: pinmux {\n\t\texin {\n\t\t\tlantiq,groups = \"exin1\";\n\t\t\tlantiq,function = \"exin\";\n\t\t};\n\t};\n};\n\n&gsw {\n\tphy-mode = \"rmii\";\n};\n\n&localbus {\n\tflash@0 {\n\t\tcompatible = \"lantiq,nor\";\n\t\tbank-width = <2>;\n\t\treg = <0 0x0 0x2000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"uboot\";\n\t\t\t\treg = <0x00000 0x40000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x40000 0x20000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@60000 {\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x60000 0xfa0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pci0 {\n\tpinctrl-0 = <&pci_gnt1_pins>, <&pci_req1_pins>;\n\tpinctrl-names = \"default\";\n};\n\n&stp {\n\tstatus = \"okay\";\n\tlantiq,shadow = <0xfff>;\n\tlantiq,groups = <0x3>;\n};\n\n&usb_phy0 {\n\tstatus = \"okay\";\n};\n\n&usb0 {\n\tstatus = \"okay\";\n\tvbus-supply = <&usb_vbus>;\n};\n"
  },
  {
    "path": "target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube.dtsi",
    "content": "/dts-v1/;\n\n#include <dt-bindings/gpio/gpio.h>\n\n/ {\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\tcompatible = \"lantiq,xway\", \"lantiq,danube\";\n\n\taliases {\n\t\tserial0 = &asc1;\n\t};\n\n\tchosen {\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu@0 {\n\t\t\tcompatible = \"mips,mips24Kc\";\n\t\t\treg = <0>;\n\t\t};\n\t};\n\n\treboot {\n\t\tcompatible = \"syscon-reboot\";\n\n\t\tregmap = <&rcu0>;\n\t\toffset = <0x10>;\n\t\tmask = <0x40000000>;\n\t};\n\n\tbiu@1f800000 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"lantiq,biu\", \"simple-bus\";\n\t\treg = <0x1f800000 0x800000>;\n\t\tranges = <0x0 0x1f800000 0x7fffff>;\n\n\t\ticu0: icu@80200 {\n\t\t\t#interrupt-cells = <1>;\n\t\t\tinterrupt-controller;\n\t\t\tcompatible = \"lantiq,icu\";\n\t\t\t/*\n\t\t\t * There is a second ICU, but the SoC is not SMP\n\t\t\t * capable.\n\t\t\t */\n\t\t\treg = <0x80200 0xc8>;\n\t\t};\n\n\t\twatchdog@803f0 {\n\t\t\tcompatible = \"lantiq,wdt\";\n\t\t\treg = <0x803f0 0x10>;\n\t\t};\n\t};\n\n\tsram@1f000000 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"lantiq,sram\", \"simple-bus\";\n\t\treg = <0x1f000000 0x800000>;\n\t\tranges = <0x0 0x1f000000 0x7fffff>;\n\n\t\teiu0: eiu@101000 {\n\t\t\t#interrupt-cells = <1>;\n\t\t\tinterrupt-controller;\n\t\t\tcompatible = \"lantiq,eiu-xway\";\n\t\t\treg = <0x101000 0x1000>;\n\t\t\tinterrupt-parent = <&icu0>;\n\t\t\tlantiq,eiu-irqs = <166 135 66>;\n\t\t};\n\n\t\tpmu0: pmu@102000 {\n\t\t\tcompatible = \"lantiq,pmu-xway\";\n\t\t\treg = <0x102000 0x1000>;\n\t\t};\n\n\t\tcgu0: cgu@103000 {\n\t\t\tcompatible = \"lantiq,cgu-xway\";\n\t\t\treg = <0x103000 0x1000>;\n\t\t\t#clock-cells = <1>;\n\t\t};\n\n\t\tvmmc: vmmc@107000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"lantiq,vmmc-xway\";\n\t\t\treg = <0x107000 0x400>;\n\t\t\tinterrupt-parent = <&icu0>;\n\t\t\tinterrupts = <150 151 152 153 154 155>;\n\t\t};\n\n\t\trcu0: rcu@203000 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\t\t\tcompatible = \"lantiq,danube-rcu\", \"simple-mfd\", \"syscon\";\n\t\t\treg = <0x203000 0x1000>;\n\t\t\tranges = <0x0 0x203000 0x100>;\n\t\t\tbig-endian;\n\n\t\t\treset: reset-controller@10 {\n\t\t\t\tcompatible = \"lantiq,danube-reset\";\n\t\t\t\treg = <0x10 4>, <0x14 4>;\n\n\t\t\t\t#reset-cells = <2>;\n\t\t\t};\n\n\t\t\tusb_phy: usb2-phy@18 {\n\t\t\t\tcompatible = \"lantiq,danube-usb2-phy\";\n\t\t\t\treg = <0x18 4>;\n\t\t\t\tstatus = \"disabled\";\n\n\t\t\t\tresets = <&reset 4 4>;\n\t\t\t\treset-names = \"ctrl\";\n\t\t\t\t#phy-cells = <0>;\n\t\t\t};\n\t\t};\n\t};\n\n\tfpi@10000000 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"lantiq,fpi\", \"simple-bus\";\n\t\tranges = <0x0 0x10000000 0xeefffff>;\n\t\treg = <0x10000000 0xef00000>;\n\n\t\tlocalbus: localbus@0 {\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <1>;\n\t\t\tranges = <0 0 0x0 0x3ffffff /* addrsel0 */\n\t\t\t\t1 0 0x4000000 0x4000010>; /* addsel1 */\n\t\t\tcompatible = \"lantiq,localbus\", \"simple-bus\";\n\t\t};\n\n\t\tgptu@e100a00 {\n\t\t\tcompatible = \"lantiq,gptu-xway\";\n\t\t\treg = <0xe100a00 0x100>;\n\t\t\tinterrupt-parent = <&icu0>;\n\t\t\tinterrupts = <126 127 128 129 130 131>;\n\t\t};\n\n\t\tgpios: stp@e100bb0 {\n\t\t\t#gpio-cells = <2>;\n\t\t\tcompatible = \"lantiq,gpio-stp-xway\";\n\t\t\tgpio-controller;\n\t\t\treg = <0xe100bb0 0x40>;\n\n\t\t\tpinctrl-0 = <&stp_pins>;\n\t\t\tpinctrl-names = \"default\";\n\n\t\t\tlantiq,shadow = <0xfff>;\n\t\t\tlantiq,groups = <0x3>;\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tasc0: serial@e100400 {\n\t\t\tcompatible = \"lantiq,asc\";\n\t\t\treg = <0xe100400 0x400>;\n\t\t\tinterrupt-parent = <&icu0>;\n\t\t\tinterrupts = <104 105 106>;\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tgpio: pinmux@e100b10 {\n\t\t\tcompatible = \"lantiq,danube-pinctrl\";\n\t\t\t#gpio-cells = <2>;\n\t\t\tgpio-controller;\n\t\t\treg = <0xe100b10 0xa0>;\n\n\t\t\tnand_pins: nand {\n\t\t\t\tmux-0 {\n\t\t\t\t\tlantiq,groups = \"nand cle\", \"nand ale\",\n\t\t\t\t\t\t\t\"nand rd\";\n\t\t\t\t\tlantiq,function = \"ebu\";\n\t\t\t\t\tlantiq,output = <1>;\n\t\t\t\t\tlantiq,open-drain = <0>;\n\t\t\t\t\tlantiq,pull = <0>;\n\t\t\t\t};\n\t\t\t\tmux-1 {\n\t\t\t\t\tlantiq,groups = \"nand rdy\";\n\t\t\t\t\tlantiq,function = \"ebu\";\n\t\t\t\t\tlantiq,output = <0>;\n\t\t\t\t\tlantiq,pull = <2>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tnand_cs1_pins: nand-cs1 {\n\t\t\t\tmux {\n\t\t\t\t\tlantiq,groups = \"nand cs1\";\n\t\t\t\t\tlantiq,function = \"ebu\";\n\t\t\t\t\tlantiq,open-drain = <0>;\n\t\t\t\t\tlantiq,pull = <0>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tpci_gnt1_pins: pci-gnt1 {\n\t\t\t\tmux {\n\t\t\t\t\tlantiq,groups = \"gnt1\";\n\t\t\t\t\tlantiq,function = \"pci\";\n\t\t\t\t\tlantiq,output = <1>;\n\t\t\t\t\tlantiq,open-drain = <0>;\n\t\t\t\t\tlantiq,pull = <0>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tpci_gnt2_pins: pci-gnt2 {\n\t\t\t\tmux {\n\t\t\t\t\tlantiq,groups = \"gnt2\";\n\t\t\t\t\tlantiq,function = \"pci\";\n\t\t\t\t\tlantiq,output = <1>;\n\t\t\t\t\tlantiq,open-drain = <0>;\n\t\t\t\t\tlantiq,pull = <0>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tpci_req1_pins: pci-req1 {\n\t\t\t\tmux {\n\t\t\t\t\tlantiq,groups = \"req1\";\n\t\t\t\t\tlantiq,function = \"pci\";\n\t\t\t\t\tlantiq,output = <0>;\n\t\t\t\t\tlantiq,open-drain = <1>;\n\t\t\t\t\tlantiq,pull = <2>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tpci_req2_pins: pci-req2 {\n\t\t\t\tmux {\n\t\t\t\t\tlantiq,groups = \"req2\";\n\t\t\t\t\tlantiq,function = \"pci\";\n\t\t\t\t\tlantiq,output = <0>;\n\t\t\t\t\tlantiq,open-drain = <1>;\n\t\t\t\t\tlantiq,pull = <2>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tstp_pins: stp {\n\t\t\t\tmux {\n\t\t\t\t\tlantiq,groups = \"stp\";\n\t\t\t\t\tlantiq,function = \"stp\";\n\t\t\t\t\tlantiq,pull = <0>;\n\t\t\t\t\tlantiq,open-drain = <0>;\n\t\t\t\t\tlantiq,output = <1>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tasc1: serial@e100c00 {\n\t\t\tcompatible = \"lantiq,asc\";\n\t\t\treg = <0xe100c00 0x400>;\n\t\t\tinterrupt-parent = <&icu0>;\n\t\t\tinterrupts = <112 113 114>;\n\t\t};\n\n\t\tusb: usb@e101000 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tcompatible = \"lantiq,danube-usb\";\n\t\t\treg = <0xe101000 0x1000\n\t\t\t\t0xe120000 0x3f000>;\n\t\t\tinterrupt-parent = <&icu0>;\n\t\t\tinterrupts = <62>;\n\t\t\tdr_mode = \"host\";\n\t\t\tphys = <&usb_phy>;\n\t\t\tphy-names = \"usb2-phy\";\n\t\t\tstatus = \"disabled\";\n\n\t\t\tehci_port1: port@1 {\n\t\t\t\treg = <1>;\n\t\t\t\t#trigger-source-cells = <0>;\n\t\t\t};\n\t\t};\n\n\t\tdeu@e103100 {\n\t\t\tcompatible = \"lantiq,deu-danube\";\n\t\t\treg = <0xe103100 0xf00>;\n\t\t};\n\n\t\tdma0: dma@e104100 {\n\t\t\tcompatible = \"lantiq,dma-xway\";\n\t\t\treg = <0xe104100 0x800>;\n\t\t};\n\n\t\tebu0: ebu@e105300 {\n\t\t\tcompatible = \"lantiq,ebu-xway\";\n\t\t\treg = <0xe105300 0x100>;\n\t\t};\n\n\t\tmei@e116000 {\n\t\t\tcompatible = \"lantiq,mei-xway\";\n\t\t\treg = <0xe116000 0x400>;\n\t\t\tinterrupt-parent = <&icu0>;\n\t\t\tinterrupts = <63>;\n\t\t};\n\n\t\tgsw: etop@e180000 {\n\t\t\tcompatible = \"lantiq,etop-xway\";\n\t\t\treg = <0xe180000 0x40000>;\n\t\t\tinterrupt-parent = <&icu0>;\n\t\t\tinterrupts = <73 78>;\n\t\t\tlantiq,tx-burst-length = <4>;\n\t\t\tlantiq,rx-burst-length = <4>;\n\t\t};\n\n\t\tppe@e234000 {\n\t\t\tcompatible = \"lantiq,ppe-danube\";\n\t\t\treg = <0xe234000 0x40000>;\n\t\t\tinterrupt-parent = <&icu0>;\n\t\t\tinterrupts = <96>;\n\t\t};\n\n\t\tpci0: pci@e105400 {\n\t\t\tstatus = \"disabled\";\n\n\t\t\t#address-cells = <3>;\n\t\t\t#size-cells = <2>;\n\t\t\t#interrupt-cells = <1>;\n\t\t\tcompatible = \"lantiq,pci-xway\";\n\t\t\tbus-range = <0x0 0x0>;\n\t\t\tranges = <0x2000000 0 0x8000000 0x8000000 0 0x2000000\t/* pci memory */\n\t\t\t\t  0x1000000 0 0x00000000 0xae00000 0 0x200000>;\t/* io space */\n\t\t\treg = <0x7000000 0x8000\t\t/* config space */\n\t\t\t\t0xe105400 0x400>;\t/* pci bridge */\n\t\t\tlantiq,bus-clock = <33333333>;\n\t\t\tinterrupt-map-mask = <0xf800 0x0 0x0 0x7>;\n\t\t\tinterrupt-map = <0x7000 0 0 1 &icu0 30 1>; /* slot 14, irq 30 */\n\t\t\treq-mask = <0x1>; /* GNT1 */\n\n\t\t\tdevice_type = \"pci\";\n\t\t};\n\t};\n\n\tadsl {\n\t\tcompatible = \"lantiq,adsl-danube\";\n\t};\n};\n"
  },
  {
    "path": "target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4510pw.dts",
    "content": "#include \"danube.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"arcadyan,arv4510pw\", \"lantiq,xway\", \"lantiq,danube\";\n\tmodel = \"Wippies, Elisa\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyLTQ0,115200\";\n\t};\n\n\taliases {\n\t\tled-boot = &power;\n\t\tled-failsafe = &power2;\n\t\tled-running = &power;\n\t\tled-upgrade = &power;\n\n\t\tled-dsl = &adsl;\n\t\tled-internet = &internet;\n\t\tled-usb = &led_usb;\n\t\tled-usb2 = &led_usb2;\n\t\tled-wifi = &wifi;\n\t};\n\n\tmemory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x0 0x2000000>;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <100>;\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 3 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tpower: power {\n\t\t\tlabel = \"power\";\n\t\t\tgpios = <&gpios 21 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"keep\";\n\t\t};\n\t\tpower2: power2 {\n\t\t\tlabel = \"power2\";\n\t\t\tgpios = <&gpios 20 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t\tlan1 {\n\t\t\tlabel = \"lan1\";\n\t\t\tgpios = <&gpios 19 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t\tlan2 {\n\t\t\tlabel = \"lan2\";\n\t\t\tgpios = <&gpios 18 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t\tlan3 {\n\t\t\tlabel = \"lan3\";\n\t\t\tgpios = <&gpios 17 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t\tlan4 {\n\t\t\tlabel = \"lan4\";\n\t\t\tgpios = <&gpios 16 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t\twifi: wifi {\n\t\t\tlabel = \"wifi\";\n\t\t\tgpios = <&gpios 15 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t\tadsl: adsl {\n\t\t\tlabel = \"adsl\";\n\t\t\tgpios = <&gpios 14 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t\tinternet: internet {\n\t\t\tlabel = \"internet\";\n\t\t\tgpios = <&gpios 13 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t\tinternet2 {\n\t\t\tlabel = \"internet2\";\n\t\t\tgpios = <&gpios 12 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t\tvoip {\n\t\t\tlabel = \"voip\";\n\t\t\tgpios = <&gpios 11 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t\tphone {\n\t\t\tlabel = \"phone\";\n\t\t\tgpios = <&gpios 10 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t\tphone2 {\n\t\t\tlabel = \"phone2\";\n\t\t\tgpios = <&gpios 9 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t\tled_usb: usb {\n\t\t\tlabel = \"usb\";\n\t\t\tgpios = <&gpios 8 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t\tled_usb2: usb2 {\n\t\t\tlabel = \"usb2\";\n\t\t\tgpios = <&gpios 7 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t\tusb3 {\n\t\t\tlabel = \"usb3\";\n\t\t\tgpios = <&gpios 6 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t\tunlabeled {\n\t\t\tlabel = \"unlabeled\";\n\t\t\tgpios = <&gpios 5 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&state_default>;\n\n\tstate_default: pinmux {\n\t\tebu {\n\t\t\tlantiq,groups = \"ebu a23\";\n\t\t\tlantiq,function = \"ebu\";\n\t\t\tlantiq,open-drain = <0>;\n\t\t\tlantiq,output = <1>;\n\t\t};\n\t\texin {\n\t\t\tlantiq,groups = \"exin1\", \"exin2\";\n\t\t\tlantiq,function = \"exin\";\n\t\t\tlantiq,output = <0>;\n\t\t};\n\t\tpci_rst {\n\t\t\tlantiq,pins = \"io21\";\n\t\t\tlantiq,open-drain = <0>;\n\t\t\tlantiq,output = <1>;\n\t\t};\n\t\tbuttons {\n\t\t\tlantiq,pins = \"io3\", \"io14\";\n\t\t\tlantiq,pull = <2>;\n\t\t\tlantiq,output = <0>;\n\t\t};\n\t};\n};\n\n&gpios {\n\tstatus = \"okay\";\n\tlantiq,groups = <0x7>;\n};\n\n&gsw {\n\tphy-mode = \"rmii\";\n};\n\n&localbus {\n\tflash@0 {\n\t\tcompatible = \"lantiq,nor\";\n\t\tbank-width = <2>;\n\t\treg = <0 0x0 0x1000000>;\n\n\t\tlantiq,noxip;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"uboot\";\n\t\t\t\treg = <0x00000 0x40000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x40000 0x20000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@60000 {\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x60000 0xfa0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pci0 {\n\tstatus = \"okay\";\n\n\tpinctrl-0 = <&pci_gnt1_pins>, <&pci_gnt2_pins>,\n\t\t    <&pci_req1_pins>, <&pci_req2_pins>;\n\tpinctrl-names = \"default\";\n\n\tlantiq,external-clock;\n\tinterrupt-map = <\n\t\t0x6000 0 0 1 &icu0 135\n\t\t0x7800 0 0 1 &icu0 66\n\t\t0x7800 0 0 2 &icu0 66\n\t\t0x7800 0 0 3 &icu0 66\n\t>;\n\tgpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>;\n\treq-mask = <0x7>;\n};\n\n&vmmc {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4518pwr01.dts",
    "content": "#include \"danube_arcadyan_arv4518pwr01.dtsi\"\n\n/ {\n\tcompatible = \"arcadyan,arv4518pwr01\", \"lantiq,xway\", \"lantiq,danube\";\n\tmodel = \"SMC7908A-ISP\";\n};\n"
  },
  {
    "path": "target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4518pwr01.dtsi",
    "content": "#include \"danube.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tchosen {\n\t\tbootargs = \"console=ttyLTQ0,115200\";\n\t};\n\n\taliases {\n\t\tled-boot = &power;\n\t\tled-failsafe = &power;\n\t\tled-running = &power;\n\t\tled-upgrade = &power;\n\n\t\tled-dsl = &dsl;\n\t\tled-internet = &online;\n\t\tled-usb = &led_usb;\n\t\tled-wifi = &wifi;\n\t};\n\n\tmemory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x0 0x4000000>;\n\t};\n\n\tath5k_eep {\n\t\tcompatible = \"ath5k,eeprom\";\n\t\tath,eep-flash = <&boardconfig 0x400>;\n\t\tath,mac-offset = <0x16>;\n\t\tath,mac-increment = <1>;\n\t\tath,eep-swap;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <100>;\n\n\t\trfkill {\n\t\t\tlabel = \"rfkill\";\n\t\t\tgpios = <&gpio 28 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RFKILL>;\n\t\t};\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 30 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tpower: power {\n\t\t\tlabel = \"power\";\n\t\t\tgpios = <&gpio 3 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"keep\";\n\t\t};\n\t\tdsl: dsl {\n\t\t\tlabel = \"dsl\";\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tonline: online {\n\t\t\tlabel = \"online\";\n\t\t\tgpios = <&gpio 5 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\twifi: wifi {\n\t\t\tlabel = \"wifi\";\n\t\t\tgpios = <&gpio 6 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tdsl2 {\n\t\t\tlabel = \"dsl2\";\n\t\t\tgpios = <&gpio 8 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tled_usb: usb {\n\t\t\tlabel = \"usb\";\n\t\t\tgpios = <&gpio 19 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tvoice {\n\t\t\tlabel = \"voice\";\n\t\t\tgpios = <&gpiomm 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tfxs1 {\n\t\t\tlabel = \"fxs1\";\n\t\t\tgpios = <&gpiomm 1 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tfxs2 {\n\t\t\tlabel = \"fxs2\";\n\t\t\tgpios = <&gpiomm 2 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tfxo {\n\t\t\tlabel = \"fxo\";\n\t\t\tgpios = <&gpiomm 3 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tusb_vbus: regulator-usb-vbus {\n\t\tcompatible = \"regulator-fixed\";\n\n\t\tregulator-name = \"USB_VBUS\";\n\n\t\tregulator-min-microvolt = <5000000>;\n\t\tregulator-max-microvolt = <5000000>;\n\n\t\tgpio = <&gpio 14 GPIO_ACTIVE_HIGH>;\n\t\tenable-active-high;\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&state_default>;\n\n\tstate_default: pinmux {\n\t\tebu {\n\t\t\tlantiq,groups = \"ebu cs1\";\n\t\t\tlantiq,function = \"ebu\";\n\t\t};\n\t};\n};\n\n&gsw {\n\tphy-mode = \"mii\";\n\tnvmem-cells = <&macaddr_boardconfig_16>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&localbus {\n\tflash@0 {\n\t\tcompatible = \"lantiq,nor\";\n\t\tbank-width = <2>;\n\t\treg = <0 0x0 0x2000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"uboot\";\n\t\t\t\treg = <0x00000 0x10000>; /* 64 KB */\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@10000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x10000 0x10000>; /* 64 KB */\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x20000 0x3d0000>;\n\t\t\t};\n\n\t\t\tboardconfig: partition@3f0000 {\n\t\t\t\tlabel = \"boardconfig\";\n\t\t\t\treg = <0x3f0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n\n\tgpiomm: gpio@1 {\n\t\tcompatible = \"lantiq,gpio-mm\";\n\t\treg = <1 0x0 0x10 >;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\t#gpio-cells = <2>;\n\t\tgpio-controller;\n\t\tlantiq,shadow = <0x0>;\n\t};\n};\n\n&pci0 {\n\tstatus = \"okay\";\n\n\tpinctrl-0 = <&pci_gnt1_pins>, <&pci_gnt2_pins>,\n\t\t    <&pci_req1_pins>, <&pci_req2_pins>;\n\tpinctrl-names = \"default\";\n\n\tgpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>;\n\treq-mask = <0xf>;\n};\n\n&usb_phy {\n\tstatus = \"okay\";\n};\n\n&usb {\n\tstatus = \"okay\";\n\tvbus-supply = <&usb_vbus>;\n};\n\n&vmmc {\n\tstatus = \"okay\";\n\tgpios = <&gpio 31 GPIO_ACTIVE_HIGH>;\n};\n\n&boardconfig {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_boardconfig_16: macaddr@16 {\n\t\treg = <0x16 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4518pwr01a.dts",
    "content": "#include \"danube_arcadyan_arv4518pwr01.dtsi\"\n\n/ {\n\tcompatible = \"arcadyan,arv4518pwr01a\", \"lantiq,xway\", \"lantiq,danube\";\n\tmodel = \"SMC7908A-ISP, Airties WAV-221\";\n};\n\n&pci0 {\n\tlantiq,external-clock;\n};\n"
  },
  {
    "path": "target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4519pw.dts",
    "content": "#include \"danube.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"arcadyan,arv4519pw\", \"lantiq,xway\", \"lantiq,danube\";\n\tmodel = \"Vodafone Netfaster IAD 2, Pirelli P.RG A4201G\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyLTQ0,115200\";\n\t};\n\n\taliases {\n\t\tled-boot = &power_green;\n\t\tled-failsafe = &power_red;\n\t\tled-running = &power_green;\n\t\tled-upgrade = &power_green;\n\n\t\tled-dsl = &dsl;\n\t\tled-internet = &internet_green;\n\t\tled-usb = &led_usb;\n\t\tled-wifi = &wifi;\n\t};\n\n\tmemory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x0 0x2000000>;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <100>;\n\n\t\trfkill {\n\t\t\tlabel = \"rfkill\";\n\t\t\tgpios = <&gpio 28 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RFKILL>;\n\t\t};\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 30 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tpower_green: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 2 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"keep\";\n\t\t};\n\t\tpower_red: power2 {\n\t\t\tlabel = \"red:power\";\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\twifi: wifi {\n\t\t\tlabel = \"green:wlan\";\n\t\t\tgpios = <&gpio 6 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tdsl: dsl {\n\t\t\tlabel = \"green:dsl\";\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tinternet_green: online {\n\t\t\tlabel = \"green:internet\";\n\t\t\tgpios = <&gpio 5 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tonline2 {\n\t\t\tlabel = \"red:internet\";\n\t\t\tgpios = <&gpio 8 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tled_usb: usb {\n\t\t\tlabel = \"green:usb\";\n\t\t\tgpios = <&gpio 19 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tvoip {\n\t\t\tlabel = \"green:voip\";\n\t\t\tgpios = <&gpiomm 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tfxs1 {\n\t\t\tlabel = \"green:phone1\";\n\t\t\tgpios = <&gpiomm 1 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tfxs2 {\n\t\t\tlabel = \"green:phone2\";\n\t\t\tgpios = <&gpiomm 2 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tfxo {\n\t\t\tlabel = \"green:line\";\n\t\t\tgpios = <&gpiomm 3 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\twps2 {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&gpiomm 4 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\twps {\n\t\t\tlabel = \"orange:wps\";\n\t\t\tgpios = <&gpiomm 5 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\twps3 {\n\t\t\tlabel = \"red:wps\";\n\t\t\tgpios = <&gpiomm 6 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tusb_vbus: regulator-usb-vbus {\n\t\tcompatible = \"regulator-fixed\";\n\n\t\tregulator-name = \"USB_VBUS\";\n\n\t\tregulator-min-microvolt = <5000000>;\n\t\tregulator-max-microvolt = <5000000>;\n\n\t\tgpio = <&gpio 14 GPIO_ACTIVE_HIGH>;\n\t\tenable-active-high;\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&state_default>;\n\n\tstate_default: pinmux {\n\t\tebu {\n\t\t\tlantiq,groups = \"ebu cs1\";\n\t\t\tlantiq,function = \"ebu\";\n\t\t};\n\t};\n};\n\n&gsw {\n\tphy-mode = \"mii\";\n\tnvmem-cells = <&macaddr_boardconfig_16>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&localbus {\n\tflash@0 {\n\t\tcompatible = \"lantiq,nor\";\n\t\tbank-width = <2>;\n\t\treg = <0 0x0 0x2000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"uboot\";\n\t\t\t\treg = <0x00000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@10000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x10000 0x10000>;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x20000 0x3d0000>;\n\t\t\t};\n\n\t\t\tboardconfig: partition@3f0000 {\n\t\t\t\tlabel = \"boardconfig\";\n\t\t\t\treg = <0x3f0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n\n\tgpiomm: gpio@1 {\n\t\tcompatible = \"lantiq,gpio-mm\";\n\t\treg = <1 0x0 0x10 >;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\t#gpio-cells = <2>;\n\t\tgpio-controller;\n\t\tlantiq,shadow = <0x400>;\n\t};\n};\n\n&pci0 {\n\tstatus = \"okay\";\n\tlantiq,external-clock;\n\tgpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>;\n\treq-mask = <0xf>;\n};\n\n&usb_phy {\n\tstatus = \"okay\";\n};\n\n&usb {\n\tstatus = \"okay\";\n\tvbus-supply = <&usb_vbus>;\n};\n\n&vmmc {\n\tstatus = \"okay\";\n\tgpios = <&gpio 31 GPIO_ACTIVE_HIGH>;\n};\n\n&boardconfig {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_boardconfig_16: macaddr@16 {\n\t\treg = <0x16 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4520pw.dts",
    "content": "#include \"danube.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"arcadyan,arv4520pw\", \"lantiq,xway\", \"lantiq,danube\";\n\tmodel = \"Easybox 800, WAV-281\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyLTQ0,115200\";\n\t};\n\n\taliases {\n\t\tled-boot = &power_blue;\n\t\tled-failsafe = &power_red;\n\t\tled-running = &power_blue;\n\t\tled-upgrade = &power_blue;\n\n\t\tled-dsl = &dsl;\n\t\tled-internet = &internet_blue;\n\t\tled-usb = &led_usb;\n\t\tled-wifi = &wifi;\n\t};\n\n\tmemory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x0 0x2000000>;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <100>;\n\n\t\trfkill {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio 29 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 30 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tpower_blue: power {\n\t\t\tlabel = \"blue:power\";\n\t\t\tgpios = <&gpio 3 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"keep\";\n\t\t};\n\t\tdsl: dsl {\n\t\t\tlabel = \"blue:dsl\";\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tinternet_blue: internet {\n\t\t\tlabel = \"blue:internet\";\n\t\t\tgpios = <&gpio 5 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tpower_red: power2 {\n\t\t\tlabel = \"red:power\";\n\t\t\tgpios = <&gpio 6 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\twps {\n\t\t\tlabel = \"yellow:wps\";\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\twps2 {\n\t\t\tlabel = \"red:wps\";\n\t\t\tgpios = <&gpio 9 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\t/*\n\t\t\twps green is missing\n\t\t*/\n\t\tfxs1 {\n\t\t\tlabel = \"blue:telefon1\";\n\t\t\tgpios = <&gpiomm 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tfxs2 {\n\t\t\tlabel = \"blue:telefon2\";\n\t\t\tgpios = <&gpiomm 1 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tisdn {\n\t\t\tlabel = \"blue:isdn\";\n\t\t\tgpios = <&gpiomm 2 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tfxo {\n\t\t\tlabel = \"blue:line\";\n\t\t\tgpios = <&gpiomm 3 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tvoice {\n\t\t\tlabel = \"blue:sprache\";\n\t\t\tgpios = <&gpiomm 4 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tled_usb: usb {\n\t\t\tlabel = \"blue:usb\";\n\t\t\tgpios = <&gpiomm 5 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\twifi: wifi {\n\t\t\tlabel = \"blue:wifi\";\n\t\t\tgpios = <&gpiomm 6 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tinternet2 {\n\t\t\tlabel = \"red:internet\";\n\t\t\tgpios = <&gpiomm 9 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\t/*\n\t\t\tinfo is missing\n\t\t*/\n\t};\n\n\tusb_vbus: regulator-usb-vbus {\n\t\tcompatible = \"regulator-fixed\";\n\n\t\tregulator-name = \"USB_VBUS\";\n\n\t\tregulator-min-microvolt = <5000000>;\n\t\tregulator-max-microvolt = <5000000>;\n\n\t\tgpio = <&gpio 28 GPIO_ACTIVE_HIGH>;\n\t\tenable-active-high;\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&state_default>;\n\n\tstate_default: pinmux {\n\t\tebu {\n\t\t\tlantiq,groups = \"ebu cs1\";\n\t\t\tlantiq,function = \"ebu\";\n\t\t};\n\t\tpci_rst {\n\t\t\tlantiq,pins = \"io21\";\n\t\t\tlantiq,open-drain = <0>;\n\t\t\tlantiq,pull = <0>;\n\t\t};\n\t};\n};\n\n&gsw {\n\t/* gpiomm 10 - switch */\n\tphy-mode = \"rmii\";\n\tnvmem-cells = <&macaddr_boardconfig_16>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&localbus {\n\tflash@0 {\n\t\tcompatible = \"lantiq,nor\";\n\t\tbank-width = <2>;\n\t\treg = <0 0x0 0x800000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"uboot\";\n\t\t\t\treg = <0x00000 0x20000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x20000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x30000 0x3c0000>;\n\t\t\t};\n\n\t\t\tboardconfig: partition@7f0000 {\n\t\t\t\tlabel = \"boardconfig\";\n\t\t\t\treg = <0x3f0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n\n\tgpiomm: gpio@1 {\n\t\tcompatible = \"lantiq,gpio-mm\";\n\t\treg = <1 0x0 0x10 >;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\t#gpio-cells = <2>;\n\t\tgpio-controller;\n\t\tlantiq,shadow = <0x400>;\n\t};\n};\n\n&pci0 {\n\tstatus = \"okay\";\n\n\tpinctrl-0 = <&pci_gnt1_pins>, <&pci_req1_pins>;\n\tpinctrl-names = \"default\";\n\n\tlantiq,external-clock;\n\tgpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>;\n};\n\n&usb_phy {\n\tstatus = \"okay\";\n};\n\n&usb {\n\tstatus = \"okay\";\n\tvbus-supply = <&usb_vbus>;\n};\n\n&vmmc {\n\tstatus = \"okay\";\n\tgpios = <&gpio 31 GPIO_ACTIVE_HIGH\n\t\t&gpiomm 7 GPIO_ACTIVE_HIGH>;\n};\n\n&boardconfig {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_boardconfig_16: macaddr@16 {\n\t\treg = <0x16 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_arcadyan_arv4525pw.dts",
    "content": "#include \"danube.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"arcadyan,arv4525pw\", \"lantiq,xway\", \"lantiq,danube\";\n\tmodel = \"Speedport W501V Typ A\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyLTQ0,115200\";\n\t};\n\n\taliases {\n\t\t/* we dont have a power led, lets use the online led */\n\t\tled-boot = &online;\n\t\tled-failsafe = &online;\n\n\t\tled-dsl = &dsl;\n\t\tled-internet = &online;\n\t\tled-wifi = &wifi;\n\t};\n\n\tmemory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x0 0x2000000>;\n\t};\n\n\tath5k_eep {\n\t\tcompatible = \"ath5k,eeprom\";\n\t\tath,eep-flash = <&boardconfig 0x400>;\n\t\tath,mac-offset = <0x0>;\n\t\tath,eep-swap;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <100>;\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio 29 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 30 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tfxo {\n\t\t\tlabel = \"green:festnetz\";\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tfxs {\n\t\t\tlabel = \"green:internet\";\n\t\t\tgpios = <&gpio 5 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tdsl: dsl {\n\t\t\tlabel = \"green:t-dsl\";\n\t\t\tgpios = <&gpio 6 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\twifi: wifi {\n\t\t\tlabel = \"green:wlan\";\n\t\t\tgpios = <&gpio 8 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tonline: online {\n\t\t\tlabel = \"green:online\";\n\t\t\tgpios = <&gpio 9 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&state_default>;\n\n\tstate_default: pinmux {\n\t\tpci_rst {\n\t\t\tlantiq,pins = \"io21\";\n\t\t\tlantiq,pull = <2>;\n\t\t\tlantiq,output = <1>;\n\t\t};\n\t\trelay {\n\t\t\tlantiq,pins = \"io31\";\n\t\t\tlantiq,output = <1>;\n\t\t};\n\t};\n};\n\n/* #define ARV4525PW_PHYRESET\t13 */\n&gsw {\n\tphy-mode = \"mii\";\n\tnvmem-cells = <&macaddr_boardconfig_16>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&localbus {\n\tflash@0 {\n\t\tcompatible = \"lantiq,nor\";\n\t\tbank-width = <2>;\n\t\treg = <0 0x0 0x2000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"uboot\";\n\t\t\t\treg = <0x00000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@10000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x10000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x20000 0x3d0000>;\n\t\t\t};\n\n\t\t\tboardconfig: partition@3f0000 {\n\t\t\t\tlabel = \"boardconfig\";\n\t\t\t\treg = <0x3f0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pci0 {\n\tstatus = \"okay\";\n\n\tpinctrl-0 = <&pci_gnt1_pins>, <&pci_req1_pins>;\n\tpinctrl-names = \"default\";\n\n\tgpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>;\n};\n\n/* #define ARV4525PW_RELAY\t\t31 */\n&vmmc {\n\tstatus = \"okay\";\n\tgpios = <&gpio 31 GPIO_ACTIVE_HIGH>;\n};\n\n&boardconfig {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_boardconfig_16: macaddr@16 {\n\t\treg = <0x16 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_arcadyan_arv452cqw.dts",
    "content": "#include \"danube.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"arcadyan,arv452cqw\", \"lantiq,xway\", \"lantiq,danube\";\n\tmodel = \"Arcor 801\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyLTQ0,115200\";\n\t};\n\n\taliases {\n\t\tled-boot = &power_blue;\n\t\tled-failsafe = &power_red;\n\t\tled-running = &power_blue;\n\t\tled-upgrade = &power_blue;\n\n\t\tled-dsl = &dsl_blue;\n\t\tled-usb = &led_usb;\n\t\tled-wifi = &wifi;\n\t};\n\n\tmemory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x0 0x2000000>;\n\t};\n\n\tath5k_eep {\n\t\tcompatible = \"ath5k,eeprom\";\n\t\tath,eep-flash = <&boardconfig 0x400>;\n\t\tath,mac-offset = <0x0>;\n\t\tath,eep-swap;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <100>;\n\n\t\trfkill {\n\t\t\tlabel = \"rfkill\";\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RFKILL>;\n\t\t};\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio 29 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 30 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tpower_blue: power0 {\n\t\t\tlabel = \"blue:power\";\n\t\t\tgpios = <&gpio 3 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"keep\";\n\t\t};\n\t\tdsl_blue: dsl {\n\t\t\tlabel = \"blue:dsl\";\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tisdn {\n\t\t\tlabel = \"blue:isdn\";\n\t\t\tgpios = <&gpio 5 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tpower_red: power1 {\n\t\t\tlabel = \"red:power\";\n\t\t\tgpios = <&gpio 6 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\twps {\n\t\t\tlabel = \"blue:wps\";\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\twps1 {\n\t\t\tlabel = \"yellow:wps\";\n\t\t\tgpios = <&gpio 9 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tfxs1 {\n\t\t\tlabel = \"blue:telefon1\";\n\t\t\tgpios = <&gpiomm 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tfxs2 {\n\t\t\tlabel = \"blue:telefon2\";\n\t\t\tgpios = <&gpiomm 1 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\twps2 {\n\t\t\tlabel = \"red:wps\";\n\t\t\tgpios = <&gpiomm 2 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tfxo {\n\t\t\tlabel = \"blue:line\";\n\t\t\tgpios = <&gpiomm 3 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tvoice {\n\t\t\tlabel = \"blue:sprache\";\n\t\t\tgpios = <&gpiomm 4 1>;\n\t\t};\n\t\tled_usb: usb {\n\t\t\tlabel = \"blue:usb\";\n\t\t\tgpios = <&gpiomm 5 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\twifi: wifi {\n\t\t\tlabel = \"blue:wlan\";\n\t\t\tgpios = <&gpiomm 6 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\t/*\n\t\t\tinternet blue and internet red are missing\n\t\t\tdsl2 and dsl3 are not referenced in manual\n\t\t*/\n\t\tdsl2 {\n\t\t\tlabel = \"yellow:dsl\";\n\t\t\tgpios = <&gpiomm 8 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tdsl3 {\n\t\t\tlabel = \"red:dsl\";\n\t\t\tgpios = <&gpiomm 9 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tusb_vbus: regulator-usb-vbus {\n\t\tcompatible = \"regulator-fixed\";\n\n\t\tregulator-name = \"USB_VBUS\";\n\n\t\tregulator-min-microvolt = <5000000>;\n\t\tregulator-max-microvolt = <5000000>;\n\n\t\tgpio = <&gpio 28 GPIO_ACTIVE_HIGH>;\n\t\tenable-active-high;\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&state_default>;\n\n\tstate_default: pinmux {\n\t\tebu {\n\t\t\tlantiq,groups = \"ebu cs1\";\n\t\t\tlantiq,function = \"ebu\";\n\t\t};\n\t\tpci_rst {\n\t\t\tlantiq,pins = \"io21\";\n\t\t\tlantiq,pull = <0>;\n\t\t\tlantiq,output = <1>;\n\t\t};\n\t\tleds {\n\t\t\tlantiq,pins = \"io3\", \"io5\", \"io6\", \"io7\", \"io9\";\n\t\t\tlantiq,output = <1>;\n\t\t};\n\t};\n};\n\n/*\n#define ARV452CPW_SWITCH_RESET          110\n*/\n&gsw {\n\tphy-mode = \"rmii\";\n\tnvmem-cells = <&macaddr_boardconfig_16>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&localbus {\n\tflash@0 {\n\t\tcompatible = \"lantiq,nor\";\n\t\tbank-width = <2>;\n\t\treg = <0 0x0 0x400000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"uboot\";\n\t\t\t\treg = <0x00000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@10000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x10000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x20000 0x3d0000>;\n\t\t\t};\n\n\t\t\tboardconfig: partition@3f0000 {\n\t\t\t\tlabel = \"boardconfig\";\n\t\t\t\treg = <0x3f0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n\n\tgpiomm: gpio@1 {\n\t\tcompatible = \"lantiq,gpio-mm\";\n\t\treg = <1 0x0 0x10 >;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\t#gpio-cells = <2>;\n\t\tgpio-controller;\n\t\tlantiq,shadow = <0x77f>;\n\t};\n};\n\n&pci0 {\n\tstatus = \"okay\";\n\n\tpinctrl-0 = <&pci_gnt1_pins>, <&pci_req1_pins>;\n\tpinctrl-names = \"default\";\n\n\tlantiq,external-clock;\n\tgpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>;\n};\n\n&usb_phy {\n\tstatus = \"okay\";\n};\n\n&usb {\n\tstatus = \"okay\";\n\tvbus-supply = <&usb_vbus>;\n};\n\n&vmmc {\n\tstatus = \"okay\";\n\tgpios = <&gpio 31 GPIO_ACTIVE_HIGH\n\t\t&gpiomm 7 GPIO_ACTIVE_HIGH>;\n};\n\n&boardconfig {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_boardconfig_16: macaddr@16 {\n\t\treg = <0x16 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_arcadyan_arv7506pw11.dts",
    "content": "#include \"danube.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"arcadyan,arv7506pw11\", \"lantiq,xway\", \"lantiq,danube\";\n\tmodel = \"Alice/O2 IAD 4421\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyLTQ0,115200\";\n\t};\n\n\taliases {\n\t\tled-boot = &power;\n\t\tled-failsafe = &power_red;\n\t\tled-running = &power;\n\t\tled-upgrade = &power;\n\n\t\tled-dsl = &dsl;\n\t\tled-internet = &internet;\n\t\tled-wifi = &wlan;\n\t};\n\n\tmemory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x0 0x4000000>;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <100>;\n\n\t\trfkill {\n\t\t\tlabel = \"rfkill\";\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RFKILL>;\n\t\t};\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 30 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\twlan: wlan {\n\t\t\tlabel = \"green:wlan\";\n\t\t\tgpios = <&gpio 2 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tpower: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 3 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"keep\";\n\t\t};\n\t\tdsl: dsl {\n\t\t\tlabel = \"green:dsl\";\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tinternet: internet {\n\t\t\tlabel = \"green:internet\";\n\t\t\tgpios = <&gpio 5 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tpower_red: power_red {\n\t\t\tlabel = \"red:power\";\n\t\t\tgpios = <&gpio 6 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tinternet_red {\n\t\t\tlabel = \"red:internet\";\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tinfo {\n\t\t\tlabel = \"green:info\";\n\t\t\tgpios = <&gpio 8 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\ttelefon {\n\t\t\tlabel = \"green:telefon\";\n\t\t\tgpios = <&gpio 9 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tinfo_red {\n\t\t\tlabel = \"red:info\";\n\t\t\tgpios = <&gpio 20 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&state_default>;\n\n\tstate_default: pinmux {\n\t\tpci_rst {\n\t\t\tlantiq,pins = \"io21\";\n\t\t\tlantiq,pull = <2>;\n\t\t\tlantiq,output = <1>;\n\t\t};\n\t};\n};\n\n/* GPIO 19: switch reset */\n&gsw {\n\tphy-mode = \"rmii\";\n\tnvmem-cells = <&macaddr_boardconfig_16>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&localbus {\n\tflash@0 {\n\t\tcompatible = \"lantiq,nor\";\n\t\tbank-width = <2>;\n\t\treg = <0 0x0 0x800000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"uboot\";\n\t\t\t\treg = <0x00000 0x40000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x7a0000>;\n\t\t\t};\n\n\t\t\tboardconfig: partition@7f0000 {\n\t\t\t\tlabel = \"board_config\";\n\t\t\t\treg = <0x7f0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pci0 {\n\tstatus = \"okay\";\n\n\tpinctrl-0 = <&pci_gnt1_pins>, <&pci_req1_pins>;\n\tpinctrl-names = \"default\";\n\n\tlantiq,external-clock;\n\tgpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>;\n\n\twifi@1814,3592 {\n\t\tcompatible = \"pci1814,3592\";\n\t\treg = <0x7000 0 0 0 0>;\n\t\tralink,mtd-eeprom = <&boardconfig 0x410>;\n\t\tralink,mtd-eeprom-swap;\n\t\tnvmem-cells = <&macaddr_boardconfig_16>;\n\t\tnvmem-cell-names = \"mac-address\";\n\t\tmac-address-increment = <1>;\n\t};\n};\n\n&boardconfig {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_boardconfig_16: macaddr@16 {\n\t\treg = <0x16 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_arcadyan_arv7510pw22.dts",
    "content": "#include \"danube.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"arcadyan,arv7510pw22\", \"lantiq,xway\", \"lantiq,danube\";\n\tmodel = \"Astoria Networks ARV7510PW22\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyLTQ0,115200\";\n\t};\n\n\taliases {\n\t\tled-boot = &power;\n\t\tled-failsafe = &power;\n\t\tled-running = &power;\n\t\tled-upgrade = &power;\n\n\t\tled-dsl = &internet;\n\t\tled-usb = &umts;\n\t\tled-wifi = &wlan;\n\t};\n\n\tmemory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x0 0x4000000>;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <100>;\n\n\t\trfkill {\n\t\t\tlabel = \"rfkill\";\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RFKILL>;\n\t\t};\n\t\trestart {\n\t\t\tlabel = \"restart\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_POWER>;\n\t\t};\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 28 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tpower: power {\n\t\t\tlabel = \"power\";\n\t\t\tgpios = <&gpio 2 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"keep\";\n\t\t};\n\t\tinternet: internet {\n\t\t\tlabel = \"internet\";\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\twlan: wlan {\n\t\t\tlabel = \"wlan\";\n\t\t\tgpios = <&gpio 10 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tumts: 3g {\n\t\t\tlabel = \"3g\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tmessage {\n\t\t\tlabel = \"message\";\n\t\t\tgpios = <&gpio 20 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tusb_vbus: regulator-usb-vbus {\n\t\tcompatible = \"regulator-fixed\";\n\n\t\tregulator-name = \"USB_VBUS\";\n\n\t\tregulator-min-microvolt = <5000000>;\n\t\tregulator-max-microvolt = <5000000>;\n\n\t\tgpio = <&gpio 8 GPIO_ACTIVE_HIGH>;\n\t\tenable-active-high;\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&state_default>;\n\n\tstate_default: pinmux {\n\t\texin {\n\t\t\tlantiq,groups = \"exin1\";\n\t\t\tlantiq,function = \"exin\";\n\t\t\tlantiq,pull = <2>;\n\t\t\tlantiq,output = <0>;\n\t\t};\n\t\tpci_rst {\n\t\t\tlantiq,pins = \"io21\";\n\t\t\tlantiq,pull = <2>;\n\t\t\tlantiq,output = <1>;\n\t\t};\n\t\tpins_out {\n\t\t\tlantiq,pins = \"io2\", \"io4\", \"io8\", \"io9\", \"io10\", \"io15\", \"io20\";\n\t\t\tlantiq,output = <1>;\n\t\t};\n\t\tpins_in {\n\t\t\tlantiq,pins = \"io11\", \"io12\", \"io28\";\n\t\t\tlantiq,open-drain = <1>;\n\t\t\tlantiq,pull = <2>;\n\t\t\tlantiq,output = <0>;\n\t\t};\n\t};\n};\n\n&gsw {\n\t/* Switch reset 19 */\n\tphy-mode = \"mii\";\n\tnvmem-cells = <&macaddr_boardconfig_16>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&localbus {\n\tflash@0 {\n\t\tcompatible = \"lantiq,nor\";\n\t\tbank-width = <2>;\n\t\treg = <0 0x0 0x1000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"uboot\";\n\t\t\t\treg = <0x00000 0x40000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x40000 0x20000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@60000 {\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x60000 0xf80000>;\n\t\t\t};\n\n\t\t\tboardconfig: partition@fe0000 {\n\t\t\t\tlabel = \"board_config\";\n\t\t\t\treg = <0xfe0000 0x20000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pci0 {\n\tstatus = \"okay\";\n\n\tpinctrl-0 = <&pci_gnt1_pins>, <&pci_req1_pins>, <&pci_req2_pins>;\n\tpinctrl-names = \"default\";\n\n\tlantiq,external-clock;\n\tinterrupt-map = <\n\t\t0x7000 0 0 1 &icu0 30\n\t\t0x7800 0 0 1 &icu0 135\n\t\t0x7800 0 0 2 &icu0 135\n\t\t0x7800 0 0 3 &icu0 135\n\t>;\n\tgpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>;\n\treq-mask = <0x3>;\n\n\twifi@1814,3592 {\n\t\tcompatible = \"pci1814,3592\";\n\t\treg = <0x7000 0 0 0 0>;\n\t\tralink,mtd-eeprom = <&boardconfig 0x410>;\n\t\tralink,mtd-eeprom-swap;\n\t};\n};\n\n&usb_phy {\n\tstatus = \"okay\";\n};\n\n&usb {\n\tstatus = \"okay\";\n\tvbus-supply = <&usb_vbus>;\n};\n\n&vmmc {\n\tstatus = \"okay\";\n\tgpios = <&gpio 9 GPIO_ACTIVE_HIGH>;\n};\n\n&boardconfig {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_boardconfig_16: macaddr@16 {\n\t\treg = <0x16 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_arcadyan_arv7518pw.dts",
    "content": "#include \"danube.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"arcadyan,arv7518pw\", \"lantiq,xway\", \"lantiq,danube\";\n\tmodel = \"Astoria Networks ARV7518PW\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyLTQ0,115200\";\n\t};\n\n\taliases {\n\t\tled-boot = &power_green;\n\t\tled-failsafe = &power_red;\n\t\tled-running = &power_green;\n\t\tled-upgrade = &power_green;\n\n\t\tled-dsl = &dsl;\n\t\tled-internet = &online_green;\n\t\tled-usb = &led_usb;\n\t\tled-wifi = &wifi;\n\t};\n\n\tmemory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x0 0x4000000>;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <100>;\n\n\t\trfkill {\n\t\t\tlabel = \"rfkill\";\n\t\t\tgpios = <&gpio 28 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RFKILL>;\n\t\t};\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 30 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tpower_green: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 2 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"keep\";\n\t\t};\n\t\tdsl: dsl {\n\t\t\tlabel = \"green:dsl\";\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tonline_green: online {\n\t\t\tlabel = \"green:internet\";\n\t\t\tgpios = <&gpio 5 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\twifi: wifi {\n\t\t\tlabel = \"green:wlan\";\n\t\t\tgpios = <&gpio 6 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tpower_red: power2 {\n\t\t\tlabel = \"red:power\";\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tonline2 {\n\t\t\tlabel = \"red:internet\";\n\t\t\tgpios = <&gpio 8 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tled_usb: usb {\n\t\t\tlabel = \"green:usb\";\n\t\t\tgpios = <&gpio 19 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tvoice {\n\t\t\tlabel = \"green:voip\";\n\t\t\tgpios = <&gpiomm 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tfxs1 {\n\t\t\tlabel = \"green:phone1\";\n\t\t\tgpios = <&gpiomm 1 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tfxs2 {\n\t\t\tlabel = \"green:phone2\";\n\t\t\tgpios = <&gpiomm 2 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tunlabeled {\n\t\t\tlabel = \"amber:unlabeled\";\n\t\t\tgpios = <&gpiomm 3 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\twps {\n\t\t\tlabel = \"amber:wps\";\n\t\t\tgpios = <&gpiomm 4 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\twps2 {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&gpiomm 5 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\twps3 {\n\t\t\tlabel = \"red:wps\";\n\t\t\tgpios = <&gpiomm 6 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tusb_vbus: regulator-usb-vbus {\n\t\tcompatible = \"regulator-fixed\";\n\n\t\tregulator-name = \"USB_VBUS\";\n\n\t\tregulator-min-microvolt = <5000000>;\n\t\tregulator-max-microvolt = <5000000>;\n\n\t\tgpio = <&gpio 14 GPIO_ACTIVE_HIGH>;\n\t\tenable-active-high;\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&state_default>;\n\n\tstate_default: pinmux {\n\t\tebu {\n\t\t\tlantiq,groups = \"ebu cs1\";\n\t\t\tlantiq,function = \"ebu\";\n\t\t};\n\t\tpci_rst {\n\t\t\tlantiq,pins = \"io21\";\n\t\t\tlantiq,pull = <2>;\n\t\t\tlantiq,output = <1>;\n\t\t};\n\t\tleds {\n\t\t\tlantiq,pins = \"io2\", \"io4\", \"io5\", \"io6\", \"io7\", \"io8\", \"io19\";\n\t\t\tlantiq,output = <1>;\n\t\t};\n\t\tkeys {\n\t\t\tlantiq,pins = \"io28\", \"io30\";\n\t\t\tlantiq,output = <0>;\n\t\t\tlantiq,pull = <2>;\n\t\t\tlantiq,open-drain = <1>;\n\t\t};\n\t};\n};\n\n/*\n#define SWITCH_RESET          13\n*/\n&gsw {\n\tphy-mode = \"mii\";\n\tnvmem-cells = <&macaddr_boardconfig_16>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&localbus {\n\tflash@0 {\n\t\tcompatible = \"lantiq,nor\";\n\t\tbank-width = <2>;\n\t\treg = <0 0x0 0x2000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"uboot\";\n\t\t\t\treg = <0x00000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@10000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x10000 0x10000>;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x20000 0x7d0000>;\n\t\t\t};\n\n\t\t\tboardconfig: partition@7f0000 {\n\t\t\t\tlabel = \"boardconfig\";\n\t\t\t\treg = <0x7f0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n\n\tgpiomm: gpio@1 {\n\t\tcompatible = \"lantiq,gpio-mm\";\n\t\treg = <1 0x0 0x10 >;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\t#gpio-cells = <2>;\n\t\tgpio-controller;\n\t\tlantiq,shadow = <0x0>;\n\t};\n};\n\n&pci0 {\n\tstatus = \"okay\";\n\n\tpinctrl-0 = <&pci_gnt1_pins>, <&pci_req1_pins>;\n\tpinctrl-names = \"default\";\n\n\tgpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>;\n\tlantiq,external-clock;\n\treq-mask = <0xf>;\n\n\twifi@168c,0029 {\n\t\tcompatible = \"pci168c,0029\";\n\t\treg = <0x7000 0 0 0 0>;\n\t\tqca,no-eeprom; /* load from ath9k-eeprom-pci-0000:00:0e.0.bin */\n\t\tnvmem-cells = <&macaddr_boardconfig_16>;\n\t\tnvmem-cell-names = \"mac-address\";\n\t\tmac-address-increment = <1>;\n\t};\n};\n\n&usb_phy {\n\tstatus = \"okay\";\n};\n\n&usb {\n\tstatus = \"okay\";\n\tvbus-supply = <&usb_vbus>;\n};\n\n&vmmc {\n\tstatus = \"okay\";\n};\n\n&boardconfig {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_boardconfig_16: macaddr@16 {\n\t\treg = <0x16 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_arcadyan_arv7519pw.dts",
    "content": "#include \"danube.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"arcadyan,arv7519pw\", \"lantiq,xway\", \"lantiq,danube\";\n\tmodel = \"Astoria Networks ARV7519PW\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyLTQ0,115200\";\n\t};\n\n\taliases {\n\t\tled-boot = &power;\n\t\tled-failsafe = &power2;\n\t\tled-running = &power;\n\t\tled-upgrade = &power;\n\n\t\tled-dsl = &dsl;\n\t\tled-internet = &online;\n\t\tled-wifi = &wifi;\n\t};\n\n\tmemory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x0 0x4000000>;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <100>;\n\n\t\trfkill {\n\t\t\tlabel = \"rfkill\";\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RFKILL>;\n\t\t};\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 28 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tpower: power {\n\t\t\tlabel = \"power\";\n\t\t\tgpios = <&gpio 2 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"keep\";\n\t\t};\n\t\tpower2: power2 {\n\t\t\tlabel = \"power2\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tonline: online {\n\t\t\tlabel = \"online\";\n\t\t\tgpios = <&gpio 3 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tonline2 {\n\t\t\tlabel = \"online2\";\n\t\t\tgpios = <&gpio 30 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\twifi: wifi {\n\t\t\tlabel = \"wifi\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\twifi2 {\n\t\t\tlabel = \"wifi2\";\n\t\t\tgpios = <&gpio 10 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\twifi3 {\n\t\t\tlabel = \"wifi3\";\n\t\t\tgpios = <&gpio 6 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tvoice {\n\t\t\tlabel = \"voice\";\n\t\t\tgpios = <&gpio 31 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\twps2 {\n\t\t\tlabel = \"wps2\";\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\twps3 {\n\t\t\tlabel = \"wps3\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tdsl: dsl {\n\t\t\tlabel = \"dsl\";\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tlan {\n\t\t\tlabel = \"lan\";\n\t\t\tgpios = <&gpio 1 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\ttv {\n\t\t\tlabel = \"tv\";\n\t\t\tgpios = <&gpio 20 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tupgrade {\n\t\t\tlabel = \"upgrade\";\n\t\t\tgpios = <&gpio 29 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\t/* is there another way to \"reserve\" the GPIO? */\n\tgpio_export {\n\t\tcompatible = \"gpio-export\";\n\t\t#size-cells = <0>;\n\n\t\tswitch {\n\t\t\tgpio-export,name = \"switch\";\n\t\t\tgpio-export,output = <1>;\n\t\t\tgpios = <&gpio 19 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&state_default>;\n\n\tstate_default: pinmux {\n\t\tebu {\n\t\t\tlantiq,groups = \"ebu cs1\";\n\t\t\tlantiq,function = \"ebu\";\n\t\t};\n\t\tpci_rst {\n\t\t\tlantiq,pins = \"io21\";\n\t\t\tlantiq,pull = <2>;\n\t\t\tlantiq,output = <1>;\n\t\t};\n\t\tswitch_rst {\n\t\t\tlantiq,pins = \"io19\";\n\t\t\tlantiq,pull = <2>;\n\t\t\tlantiq,output = <1>;\n\t\t};\n\t};\n};\n\n&gsw {\n\tphy-mode = \"mii\";\n\tnvmem-cells = <&macaddr_boardconfig_16>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&localbus {\n\tflash@0 {\n\t\tcompatible = \"lantiq,nor\";\n\t\tbank-width = <2>;\n\t\treg = <0 0x0 0x2000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"uboot\";\n\t\t\t\treg = <0x00000 0x40000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x40000 0x20000>;\n\t\t\t};\n\n\t\t\tpartition@60000 {\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x60000 0xf80000>;\n\t\t\t};\n\n\t\t\tboardconfig: partition@fe0000 {\n\t\t\t\tlabel = \"board_config\";\n\t\t\t\treg = <0xfe0000 0x20000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pci0 {\n\tstatus = \"okay\";\n\n\tpinctrl-0 = <&pci_gnt1_pins>, <&pci_req1_pins>;\n\tpinctrl-names = \"default\";\n\n\tlantiq,external-clock;\n\tgpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>;\n\treq-mask = <0xf>;\n\n\twifi@0,0 {\n\t\tcompatible = \"pci0,0\";\n\t\treg = <0x7000 0 0 0 0>;\n\t\tralink,mtd-eeprom = <&boardconfig 0x410>;\n\t\tralink,mtd-eeprom-swap;\n\t};\n};\n\n&usb_phy {\n\tstatus = \"okay\";\n};\n\n/* warning: passive port only works with active devices */\n&usb {\n\tstatus = \"okay\";\n};\n\n&vmmc {\n\tstatus = \"okay\";\n};\n\n&boardconfig {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_boardconfig_16: macaddr@16 {\n\t\treg = <0x16 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_arcadyan_arv7525pw.dts",
    "content": "#include \"danube.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"arcadyan,arv7525pw\", \"lantiq,xway\", \"lantiq,danube\";\n\tmodel = \"Speedport W303V Typ A\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyLTQ0,115200\";\n\t};\n\n\taliases {\n\t\tled-boot = &power_green;\n\t\tled-failsafe = &power_red;\n\t\tled-running = &power_green;\n\t\tled-upgrade = &power_green;\n\n\t\tled-dsl = &power_green;\n\t\tled-internet = &online;\n\t\tled-wifi = &wifi;\n\t};\n\n\tmemory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x0 0x2000000>;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <100>;\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio 29 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 30 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tpower_green: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 3 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"keep\";\n\t\t};\n\t\tpower_red: power1 {\n\t\t\tlabel = \"red:power\";\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tonline: online {\n\t\t\tlabel = \"green:online\";\n\t\t\tgpios = <&gpio 5 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tvoice {\n\t\t\tlabel = \"green:telefonie\";\n\t\t\tgpios = <&gpio 6 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tvoice2 {\n\t\t\tlabel = \"red:telefonie\";\n\t\t\tgpios = <&gpio 8 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\twifi: wifi {\n\t\t\tlabel = \"green:wlan\";\n\t\t\tgpios = <&gpio 9 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&state_default>;\n\n\tstate_default: pinmux {\n\t\texin {\n\t\t\tlantiq,groups = \"exin1\";\n\t\t\tlantiq,function = \"exin\";\n\t\t};\n\t};\n};\n\n&gsw {\n\tphy-mode = \"mii\";\n\tnvmem-cells = <&macaddr_boardconfig_16>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&localbus {\n\tflash@0 {\n\t\tcompatible = \"lantiq,nor\";\n\t\tbank-width = <2>;\n\t\treg = <0 0x0 0x2000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"uboot\";\n\t\t\t\treg = <0x00000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@10000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x10000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x20000 0x3d0000>;\n\t\t\t};\n\n\t\t\tboardconfig: partition@3f0000 {\n\t\t\t\tlabel = \"board_config\";\n\t\t\t\treg = <0x3f0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pci0 {\n\tstatus = \"okay\";\n\n\tpinctrl-0 = <&pci_gnt1_pins>, <&pci_req1_pins>;\n\tpinctrl-names = \"default\";\n\n\tinterrupt-map = <0x7000 0 0 1 &icu0 135 1>;\n\n\twifi@0,0 {\n\t\tcompatible = \"pci0,0\";\n\t\treg = <0x7000 0 0 0 0>;\n\t\tralink,mtd-eeprom = <&boardconfig 0x410>;\n\t};\n};\n\n&vmmc {\n\tstatus = \"okay\";\n\tgpios = <&gpio 31 GPIO_ACTIVE_HIGH>;\n};\n\n&boardconfig {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_boardconfig_16: macaddr@16 {\n\t\treg = <0x16 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_arcadyan_arv752dpw.dts",
    "content": "#include \"danube.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"arcadyan,arv752dpw\", \"lantiq,xway\", \"lantiq,danube\";\n\tmodel = \"Arcor 802\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyLTQ0,115200\";\n\t};\n\n\taliases {\n\t\tled-boot = &power_red;\n\t\tled-failsafe = &power_blue;\n\t\tled-running = &power_red;\n\t\tled-upgrade = &power_red;\n\n\t\tled-dsl = &internet_red;\n\t\tled-usb = &umts;\n\t\tled-wifi = &wifi;\n\n\t\tlabel-mac-device = &wifi0;\n\t};\n\n\tmemory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x0 0x4000000>;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <100>;\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t\trestart {\n\t\t\tlabel = \"restart\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_POWER>;\n\t\t};\n\t\tdsl {\n\t\t\tlabel = \"dsl\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_0>;\n\t\t};\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 30 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tpower_blue: power1 {\n\t\t\tlabel = \"blue:power\";\n\t\t\tgpios = <&gpio 3 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tinternet_red: internet {\n\t\t\tlabel = \"red:internet\";\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tmessage {\n\t\t\tlabel = \"red:message\";\n\t\t\tgpios = <&gpio 5 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tpower_red: power {\n\t\t\tlabel = \"red:power\";\n\t\t\tgpios = <&gpio 6 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"keep\";\n\t\t};\n\t\tvoice1 {\n\t\t\tlabel = \"red:voice\";\n\t\t\tgpios = <&gpio 8 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tumts: umts {\n\t\t\tlabel = \"red:umts\";\n\t\t\tgpios = <&gpiomm 3 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\twifi: wifi {\n\t\t\tlabel = \"red:wifi\";\n\t\t\tgpios = <&gpiomm 4 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tfxs1 {\n\t\t\tlabel = \"green:tae-n\";\n\t\t\tgpios = <&gpiomm 5 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tfxs2 {\n\t\t\tlabel = \"green:tae-u\";\n\t\t\tgpios = <&gpiomm 6 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tfxo {\n\t\t\tlabel = \"green:isdn\";\n\t\t\tgpios = <&gpiomm 7 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tinternet2 {\n\t\t\tlabel = \"blue:internet\";\n\t\t\tgpios = <&gpiomm 8 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tvoice2 {\n\t\t\tlabel = \"blue:voice\";\n\t\t\tgpios = <&gpiomm 9 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tusb_vbus: regulator-usb-vbus {\n\t\tcompatible = \"regulator-fixed\";\n\n\t\tregulator-name = \"USB_VBUS\";\n\n\t\tregulator-min-microvolt = <5000000>;\n\t\tregulator-max-microvolt = <5000000>;\n\n\t\tgpio = <&gpiomm 0 GPIO_ACTIVE_HIGH>;\n\t\tenable-active-high;\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&state_default>;\n\n\tstate_default: pinmux {\n\t\tebu {\n\t\t\tlantiq,groups = \"ebu cs1\";\n\t\t\tlantiq,function = \"ebu\";\n\t\t};\n\t\texin {\n\t\t\tlantiq,groups = \"exin1\";\n\t\t\tlantiq,function = \"exin\";\n\t\t\tlantiq,pull = <2>;\n\t\t\tlantiq,output = <0>;\n\t\t};\n\t\tpci_rst {\n\t\t\tlantiq,pins = \"io21\";\n\t\t\tlantiq,pull = <2>;\n\t\t\tlantiq,output = <1>;\n\t\t};\n\t\tleds {\n\t\t\tlantiq,pins = \"io3\", \"io5\", \"io6\", \"io8\";\n\t\t\tlantiq,output = <1>;\n\t\t\tlantiq,pull = <0>;\n\t\t};\n\t\tkeys {\n\t\t\tlantiq,pins = \"io11\", \"io12\", \"io13\", \"io28\";\n\t\t\tlantiq,output = <0>;\n\t\t\tlantiq,pull = <2>;\n\t\t\tlantiq,open-drain = <1>;\n\t\t};\n\t};\n};\n\n&gsw {\n\tphy-mode = \"rmii\";\n\tnvmem-cells = <&macaddr_boardconfig_16>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&localbus {\n\tflash@0 {\n\t\tcompatible = \"lantiq,nor\";\n\t\tbank-width = <2>;\n\t\treg = <0 0x0 0x800000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"uboot\";\n\t\t\t\treg = <0x00000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@10000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x10000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x20000 0x7d0000>;\n\t\t\t};\n\n\t\t\tboardconfig: partition@7f0000 {\n\t\t\t\tlabel = \"board_config\";\n\t\t\t\treg = <0x7f0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n\n\tgpiomm: gpio@1 {\n\t\tcompatible = \"lantiq,gpio-mm\";\n\t\treg = <1 0x0 0x10 >;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\t#gpio-cells = <2>;\n\t\tgpio-controller;\n\t\tlantiq,shadow = <0x3>;\n\t};\n};\n\n&pci0 {\n\tstatus = \"okay\";\n\n\tpinctrl-0 = <&pci_gnt1_pins>, <&pci_req1_pins>, <&pci_req2_pins>;\n\tpinctrl-names = \"default\";\n\n\tlantiq,external-clock;\n\tgpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>;\n\tinterrupt-map = <0x7000 0 0 1 &icu0 135>;\n\treq-mask = <0x3>;\n\n\twifi0: wifi@1814,0601 {\n\t\tcompatible = \"pci1814,0601\";\n\t\treg = <0x7000 0 0 0 0>;\n\t\tnvmem-cells = <&macaddr_boardconfig_16>;\n\t\tnvmem-cell-names = \"mac-address\";\n\t\tralink,mtd-eeprom = <&boardconfig 0x410>;\n\t\tralink,mtd-eeprom-swap;\n\t};\n};\n\n&usb_phy {\n\tstatus = \"okay\";\n};\n\n&usb {\n\tstatus = \"okay\";\n\tvbus-supply = <&usb_vbus>;\n};\n\n&vmmc {\n\tstatus = \"okay\";\n\tgpios = <&gpiomm 1 GPIO_ACTIVE_HIGH>;\n};\n\n&boardconfig {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_boardconfig_16: macaddr@16 {\n\t\treg = <0x16 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_arcadyan_arv752dpw22.dts",
    "content": "#include \"danube.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"arcadyan,arv752dpw22\", \"lantiq,xway\", \"lantiq,danube\";\n\tmodel = \"Arcor 803\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyLTQ0,115200\";\n\t};\n\n\taliases {\n\t\tled-boot = &power_red;\n\t\tled-failsafe = &power_blue;\n\t\tled-running = &power_red;\n\t\tled-upgrade = &power_red;\n\n\t\tled-dsl = &internet_red;\n\t\tled-wifi = &wifi;\n\t};\n\n\tmemory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x0 0x4000000>;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <100>;\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t\trestart {\n\t\t\tlabel = \"restart\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_POWER>;\n\t\t};\n\t\tdsl {\n\t\t\tlabel = \"dsl\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_0>;\n\t\t};\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 28 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tpower_blue: power1 {\n\t\t\tlabel = \"blue:power\";\n\t\t\tgpios = <&gpio 3 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tinternet_red: internet {\n\t\t\tlabel = \"red:internet\";\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tmessage {\n\t\t\tlabel = \"red:message\";\n\t\t\tgpios = <&gpio 5 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tpower_red: power {\n\t\t\tlabel = \"red:power\";\n\t\t\tgpios = <&gpio 6 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"keep\";\n\t\t};\n\t\tvoice1 {\n\t\t\tlabel = \"red:voice\";\n\t\t\tgpios = <&gpio 8 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tumts: umts {\n\t\t\tlabel = \"red:umts\";\n\t\t\tgpios = <&gpiomm 3 GPIO_ACTIVE_LOW>;\n\t\t\ttrigger-sources = <&ehci_port1>,\n\t\t\t\t\t  <&ehci_port2>, <&uhci_port2>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\t\twifi: wifi {\n\t\t\tlabel = \"red:wifi\";\n\t\t\tgpios = <&gpiomm 4 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tfxs1 {\n\t\t\tlabel = \"green:tae-n\";\n\t\t\tgpios = <&gpiomm 5 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tfxs2 {\n\t\t\tlabel = \"green:tae-u\";\n\t\t\tgpios = <&gpiomm 6 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tfxo {\n\t\t\tlabel = \"green:isdn\";\n\t\t\tgpios = <&gpiomm 7 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tinternet2 {\n\t\t\tlabel = \"blue:internet\";\n\t\t\tgpios = <&gpiomm 8 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tvoice2 {\n\t\t\tlabel = \"blue:voice\";\n\t\t\tgpios = <&gpiomm 9 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\teth1 {\n\t\t\t label = \"green:lan1\";\n\t\t\t gpios = <&gpiomm 11 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\teth2 {\n\t\t\tlabel = \"green:lan2\";\n\t\t\tgpios = <&gpiomm 12 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\teth3 {\n\t\t\tlabel = \"green:lan3\";\n\t\t\tgpios = <&gpiomm 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\teth4 {\n\t\t\tlabel = \"green:lan4\";\n\t\t\tgpios = <&gpiomm 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tusb_vbus: regulator-usb-vbus {\n\t\tcompatible = \"regulator-fixed\";\n\n\t\tregulator-name = \"USB_VBUS\";\n\n\t\tregulator-min-microvolt = <5000000>;\n\t\tregulator-max-microvolt = <5000000>;\n\n\t\tgpio = <&gpiomm 0 GPIO_ACTIVE_HIGH>;\n\t\tenable-active-high;\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&state_default>;\n\n\tstate_default: pinmux {\n\t\tebu {\n\t\t\tlantiq,groups = \"ebu cs1\";\n\t\t\tlantiq,function = \"ebu\";\n\t\t};\n\t\texin {\n\t\t\tlantiq,groups = \"exin1\";\n\t\t\tlantiq,function = \"exin\";\n\t\t\tlantiq,pull = <2>;\n\t\t\tlantiq,output = <0>;\n\t\t};\n\t\tpci_rst {\n\t\t\tlantiq,pins = \"io21\";\n\t\t\tlantiq,open-drain = <1>;\n\t\t\tlantiq,output = <1>;\n\t\t};\n\t\tleds {\n\t\t\tlantiq,pins = \"io3\", \"io5\", \"io6\", \"io8\";\n\t\t\tlantiq,open-drain = <1>;\n\t\t\tlantiq,output = <1>;\n\t\t};\n\t\tbuttons {\n\t\t\tlantiq,pins = \"io11\", \"io12\", \"io13\", \"io28\";\n\t\t\tlantiq,pull = <2>;\n\t\t\tlantiq,output = <0>;\n\t\t};\n\t};\n};\n\n&gsw {\n\tphy-mode = \"mii\";\n\tnvmem-cells = <&macaddr_boardconfig_16>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&localbus {\n\tflash@0 {\n\t\tcompatible = \"lantiq,nor\";\n\t\tbank-width = <2>;\n\t\treg = <0 0x0 0x800000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"uboot\";\n\t\t\t\treg = <0x00000 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@10000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x40000 0x7b0000>;\n\t\t\t};\n\n\t\t\tboardconfig: partition@7f0000 {\n\t\t\t\tlabel = \"board_config\";\n\t\t\t\treg = <0x7f0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n\n\tgpiomm: gpio@1 {\n\t\tcompatible = \"lantiq,gpio-mm\";\n\t\treg = <1 0x0 0x10 >;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\t#gpio-cells = <2>;\n\t\tgpio-controller;\n\t\tlantiq,shadow = <3>;\n\t};\n};\n\n&pci0 {\n\tstatus = \"okay\";\n\n\tpinctrl-0 = <&pci_gnt1_pins>, <&pci_req1_pins>;\n\tpinctrl-names = \"default\";\n\n\tlantiq,external-clock;\n\tinterrupt-map = <\n\t\t0x7000 0 0 1 &icu0 30\n\t\t0x7800 0 0 1 &icu0 135\n\t\t0x7800 0 0 2 &icu0 135\n\t\t0x7800 0 0 3 &icu0 135\n\t>;\n\tgpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>;\n\treq-mask = <0x3>;\n\n\twifi@1814,3592 {\n\t\tcompatible = \"pci1814,3592\";\n\t\treg = <0x7000 0 0 0 0>;\n\t\tralink,mtd-eeprom = <&boardconfig 0x410>;\n\t\tralink,mtd-eeprom-swap;\n\t\tnvmem-cells = <&macaddr_boardconfig_16>;\n\t\tnvmem-cell-names = \"mac-address\";\n\t};\n\n\tusb@0f,0 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tcompatible = \"pci1106,3038\";\n\t\treg = <0x7800 0 0 0 0>; /* 0000:00:0f.0: UHCI Host Controller */\n\n\t\tuhci_port2: port@2 {\n\t\t\treg = <2>;\n\t\t\t#trigger-source-cells = <0>;\n\t\t};\n\t};\n\n\tusb@0f,2 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tcompatible = \"pci1106,3038\";\n\t\treg = <0x7a00 0 0 0 0>; /* 0000:00:0f.2: EHCI Host Controller*/\n\n\t\tehci_port2: port@2 {\n\t\t\treg = <2>;\n\t\t\t#trigger-source-cells = <0>;\n\t\t};\n\t};\n};\n\n&usb_phy {\n\tstatus = \"okay\";\n};\n\n&usb {\n\tstatus = \"okay\";\n\tvbus-supply = <&usb_vbus>;\n};\n\n&vmmc {\n\tstatus = \"okay\";\n\tgpios = <&gpiomm 1 GPIO_ACTIVE_HIGH>;\n};\n\n&boardconfig {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_boardconfig_16: macaddr@16 {\n\t\treg = <0x16 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_arcadyan_arv8539pw22.dts",
    "content": "#include \"danube.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"arcadyan,arv8539pw22\", \"lantiq,xway\", \"lantiq,danube\";\n\tmodel = \"Speedport W 504V Typ A\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyLTQ0,115200\";\n\t};\n\n\taliases {\n\t\tled-boot = &power_green;\n\t\tled-failsafe = &power_red;\n\t\tled-running = &power_green;\n\t\tled-upgrade = &power_green;\n\n\t\tled-dsl = &dsl_green;\n\t\tled-internet = &online_green;\n\t\tled-wifi = &wireless_green;\n\t};\n\n\tmemory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x0 0x4000000>;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <100>;\n\n\t\twlan {\n\t\t\tlabel = \"wlan\";\n\t\t\tgpios = <&gpio 29 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 30 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t\t/* key DECT is missing */\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tpower_green: power-green {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 24 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"keep\";\n\t\t};\n\t\tpower_red: power-red {\n\t\t\tlabel = \"red:power\";\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tdsl_green: dsl-green {\n\t\t\tlabel = \"green:dsl\";\n\t\t\tgpios = <&gpio 5 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tonline_green: online-green {\n\t\t\tlabel = \"green:online\";\n\t\t\tgpios = <&gpio 6 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twireless_green: wireless-green {\n\t\t\tlabel = \"green:wlan\";\n\t\t\tgpios = <&gpio 8 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\t/*\n\t\t\ttelefonie green is missing\n\t\t*/\n\t};\n\n\tusb_vbus: regulator-usb-vbus {\n\t\tcompatible = \"regulator-fixed\";\n\n\t\tregulator-name = \"USB_VBUS\";\n\n\t\tregulator-min-microvolt = <5000000>;\n\t\tregulator-max-microvolt = <5000000>;\n\n\t\tgpio = <&gpio 14 GPIO_ACTIVE_HIGH>;\n\t\tenable-active-high;\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&state_default>;\n\n\tstate_default: pinmux {\n\t\tpci_rst {\n\t\t\tlantiq,pins = \"io21\";\n\t\t\tlantiq,pull = <2>;\n\t\t\tlantiq,output = <1>;\n\t\t};\n\t\trelay {\n\t\t\tlantiq,pins = \"io31\";\n\t\t\tlantiq,output = <1>;\n\t\t};\n\t};\n};\n\n&gsw {\n\tphy-mode = \"mii\";\n\tnvmem-cells = <&macaddr_art_16>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&localbus {\n\tflash@0 {\n\t\tcompatible = \"lantiq,nor\";\n\t\tbank-width = <2>;\n\t\treg = <0 0x0 0x800000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"uboot\";\n\t\t\t\treg = <0x00000 0x30000>;\t/* 192 KiB */\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"uboot\";\n\t\t\t\treg = <0x30000 0x10000>;\t/* 64 KiB */\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x40000 0x7b0000>;       /* 7872 KiB */\n\t\t\t};\n\n\t\t\tart: partition@7f0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0x7f0000 0x10000>;       /* 64 KiB*/\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pci0 {\n\tstatus = \"okay\";\n\n\tpinctrl-0 = <&pci_gnt1_pins>, <&pci_req1_pins>;\n\tpinctrl-names = \"default\";\n\n\tgpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>;\n\n\twifi@168c,0029 {\n\t\tcompatible = \"pci168c,0029\";\n\t\treg = <0x7000 0 0 0 0>;\n\t\tqca,no-eeprom; /* load from ath9k-eeprom-pci-0000:00:0e.0.bin */\n\t\tnvmem-cells = <&macaddr_art_16>;\n\t\tnvmem-cell-names = \"mac-address\";\n\t\tmac-address-increment = <1>;\n\t};\n};\n\n&usb_phy {\n\tstatus = \"okay\";\n};\n\n&usb {\n\tstatus = \"okay\";\n\tvbus-supply = <&usb_vbus>;\n};\n\n&vmmc {\n\tstatus = \"okay\";\n\tgpios = <&gpio 31 GPIO_ACTIVE_HIGH>;\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_16: macaddr@16 {\n\t\treg = <0x16 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_audiocodes_mp-252.dts",
    "content": "#include \"danube.dtsi\"\n\n/ {\n\tcompatible = \"audiocodes,mp-252\", \"lantiq,xway\", \"lantiq,danube\";\n\tmodel = \"AudioCodes MediaPack MP-252\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyLTQ0,115200\";\n\t};\n\n\tmemory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x0 0x4000000>;\n\t};\n\n\tusb_vbus: regulator-usb-vbus {\n\t\tcompatible = \"regulator-fixed\";\n\n\t\tregulator-name = \"USB_VBUS\";\n\n\t\tregulator-min-microvolt = <5000000>;\n\t\tregulator-max-microvolt = <5000000>;\n\n\t\tgpio = <&gpio 3 GPIO_ACTIVE_HIGH>;\n\t\tenable-active-high;\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&state_default>;\n\n\tstate_default: pinmux {\n\t\texin {\n\t\t\tlantiq,groups = \"exin1\";\n\t\t\tlantiq,function = \"exin\";\n\t\t};\n\t};\n};\n\n&gsw {\n\tphy-mode = \"rmii\";\n};\n\n&localbus {\n\tflash@0 {\n\t\tcompatible = \"lantiq,nor\";\n\t\tbank-width = <2>;\n\t\treg = <0 0x0 0x2000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"uboot\";\n\t\t\t\treg = <0x0 0x20000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x20000 0x20000>;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"boardconfig\";\n\t\t\t\treg = <0x40000 0x60000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@a0000 {\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0xa0000 0xf20000>;\n\t\t\t};\n\n\t\t\tpartition@fc0000 {\n\t\t\t\tlabel = \"sysconfig\";\n\t\t\t\treg = <0xfc0000 0x40000>;\n\t\t\t};\n\n\t\t\tpartition@1000000 {\n\t\t\t\tlabel = \"rootfs_data\";\n\t\t\t\treg = <0x1000000 0x1000000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pci0 {\n\tstatus = \"okay\";\n\n\tpinctrl-0 = <&pci_gnt1_pins>, <&pci_req1_pins>;\n\tpinctrl-names = \"default\";\n};\n\n&usb_phy {\n\tstatus = \"okay\";\n};\n\n&usb {\n\tstatus = \"okay\";\n\tvbus-supply = <&usb_vbus>;\n};\n\n&vmmc {\n\tstatus = \"okay\";\n\tgpios = <&gpio 31 GPIO_ACTIVE_HIGH>;\n};\n"
  },
  {
    "path": "target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_bt_homehub-v2b.dts",
    "content": "#include \"danube.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"bt,homehub-v2b\", \"lantiq,xway\", \"lantiq,danube\";\n\tmodel = \"BT Home Hub 2B\";  /* SoC: Lantiq Danube-S PSB 50712 @ 333MHz V1.3/1.5 */\n\n\tchosen {\n\t\tbootargs = \"console=ttyLTQ0,115200\";\n\t};\n\n\taliases {\n\t\tled-boot = &power_orange;\n\t\tled-failsafe = &power_red;\n\t\tled-running = &power_blue;\n\t\tled-upgrade = &power_blue;\n\n\t\tled-dsl = &broadband_blue;\n\t\tled-wifi = &wireless_blue;\n\t};\n\n\tmemory@0 {\t\t\t\t  /* RAM: Samsung K4H511638F-LC 64MB */\n\t\tdevice_type = \"memory\";\n\t\treg = <0x0 0x4000000>;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <100>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 2 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t\tfindhandset {\n\t\t\tlabel = \"findhandset\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_PHONE>;\n\t\t};\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tupgrading-orange {\n\t\t\tlabel = \"orange:upgrading\";\n\t\t\tgpios = <&gpios 5 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tphone-orange {\n\t\t\tlabel = \"orange:phone\";\n\t\t\tgpios = <&gpios 6 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t\tphone-blue {\n\t\t\tlabel = \"blue:phone\";\n\t\t\tgpios = <&gpios 7 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\twireless-orange {\n\t\t\tlabel = \"orange:wireless\";\n\t\t\tgpios = <&gpios 8 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t\twireless_blue: wireless-blue {\n\t\t\tlabel = \"blue:wireless\";\n\t\t\tgpios = <&gpios 9 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tbroadband-red {\n\t\t\tlabel = \"red:broadband\";\n\t\t\tgpios = <&gpios 10 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t\tbroadband-orange {\n\t\t\tlabel = \"orange:broadband\";\n\t\t\tgpios = <&gpios 11 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t\tbroadband_blue: broadband-blue {\n\t\t\tlabel = \"blue:broadband\";\n\t\t\tgpios = <&gpios 12 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tpower_red: power-red {\n\t\t\tlabel = \"red:power\";\n\t\t\tgpios = <&gpios 13 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t\tpower_orange: power-orange {\n\t\t\tlabel = \"orange:power\";\n\t\t\tgpios = <&gpios 14 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"keep\";\n\t\t};\n\t\tpower_blue: power-blue {\n\t\t\tlabel = \"blue:power\";\n\t\t\tgpios = <&gpios 15 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&state_default>;\n\n\tstate_default: pinmux {\n\t\texin {\n\t\t\tlantiq,groups = \"exin1\";\n\t\t\tlantiq,function = \"exin\";\n\t\t};\n\n\t\tpci_rst {\n\t\t\tlantiq,pins = \"io21\";\n\t\t\tlantiq,output = <1>;\n\t\t\tlantiq,open-drain = <0>;\n\t\t};\n\n\t\tbtn_in {\n\t\t\tlantiq,pins = \"io2\", \"io15\", \"io22\";\n\t\t\tlantiq,output = <0>;\n\t\t\tlantiq,open-drain = <1>;\n\t\t\tlantiq,pull = <2>;\n\t\t};\n\t};\n};\n\n&gpios {\n\tstatus = \"okay\";\n};\n\n&gsw {\n\tphy-mode = \"rmii\";\n};\n\n&localbus {\n\tflash@0 {\t\t\t\t/* NOR Flash: Spansion S29AL004D 512KB */\n\t\tcompatible = \"lantiq,nor\";\t/* \"AMD AM29LV400BB\" compatible on 3.3.8 */\n\t\tlantiq,cs = <0>;\n\t\tbank-width = <2>;\n\t\treg = <0 0x0 0x80000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"uboot\";\n\t\t\t\treg = <0x00000 0x40000>; /* 256KB */\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x40000 0x10000>; /* 64KB */\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tlabel = \"rg_conf_1\";\n\t\t\t\treg = <0x50000 0x10000>;\n\t\t\t};\n\n\t\t\tpartition@60000 {\n\t\t\t\tlabel = \"rg_conf_2\";\n\t\t\t\treg = <0x60000 0x10000>;\n\t\t\t};\n\n\t\t\tpartition@70000 {\n\t\t\t\tlabel = \"rg_conf_factory\";\n\t\t\t\treg = <0x70000 0x10000>;\n\t\t\t};\n\t\t};\n\t};\n\n\tflash@1 {\t\t  /* NAND Flash: Samsung K9F5608U0D-JIB0 32MB */\n\t\tcompatible = \"lantiq,nand-xway\";\n\t\tlantiq,cs = <1>;\n\t\tbank-width = <2>;\n\t\treg = <1 0x0 0x2000000 >;\n\t\treq-mask = <0x1>;  /* PCI request lines to mask during NAND access */\n\n\t\tpinctrl-0 = <&nand_pins>, <&nand_cs1_pins>;\n\t\tpinctrl-names = \"default\";\n\n\t\tnand-use-soft-ecc-engine;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tath9k_cal: partition@0 {\n\t\t\t\tlabel = \"art\";\t   /* Atheros 9160 wifi b/g/n radio EEPROM */\n\t\t\t\treg = <0x00000 0x4000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@4000 {\n\t\t\t\tlabel = \"kernel\";\n\t\t\t\treg = <0x4000 0x200000>;\n\t\t\t};\n\n\t\t\tpartition@164000 {\n\t\t\t\tlabel = \"ubi\";\n\t\t\t\treg = <0x204000 0x1dfc000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pci0 {\n\tstatus = \"okay\";\n\n\tpinctrl-0 = <&pci_gnt1_pins>, <&pci_req1_pins>;\n\tpinctrl-names = \"default\";\n\n\tgpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>;\n\n\twifi@168c,0027 {\n\t\tcompatible = \"pci168c,0027\";\n\t\treg = <0x7000 0 0 0 0>;\n\t\tqca,no-eeprom; /* load from ath9k-eeprom-pci-0000:00:0e.0.bin */\n\t};\n};\n\n&usb_phy {\n\tstatus = \"okay\";\n};\n\n&usb {\n\tstatus = \"okay\";\n};\n\n&vmmc {\n\tstatus = \"okay\";\n\tgpios = <&gpio 31 GPIO_ACTIVE_HIGH>;\n};\n"
  },
  {
    "path": "target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_lantiq_easy50712.dts",
    "content": "#include \"danube.dtsi\"\n\n/ {\n\tcompatible = \"lantiq,easy50712\", \"lantiq,xway\", \"lantiq,danube\";\n\tmodel = \"Intel EASY50712 Nand\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyLTQ0,115200\";\n\t};\n\n\tmemory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x0 0x2000000>;\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&state_default>;\n\n\tstate_default: pinmux {\n\t\texin {\n\t\t\tlantiq,groups = \"exin1\";\n\t\t\tlantiq,function = \"exin\";\n\t\t};\n\t};\n};\n\n&gsw {\n\tphy-mode = \"rmii\";\n};\n\n&localbus {\n\tflash@0 {\n\t\tcompatible = \"lantiq,nor\";\n\t\tbank-width = <2>;\n\t\treg = <0 0x0 0x2000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"uboot\";\n\t\t\t\treg = <0x00000 0x10000>; /* 64 KB */\n\t\t\t};\n\n\t\t\tpartition@10000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x10000 0x10000>; /* 64 KB */\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x20000 0x3d0000>;\n\t\t\t};\n\n\t\t\tpartition@400000 {\n\t\t\t\tlabel = \"rootfs\";\n\t\t\t\treg = <0x400000 0x400000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pci0 {\n\tpinctrl-0 = <&pci_gnt1_pins>, <&pci_req1_pins>;\n\tpinctrl-names = \"default\";\n};\n"
  },
  {
    "path": "target/linux/lantiq/files/arch/mips/boot/dts/lantiq/danube_siemens_gigaset-sx76x.dts",
    "content": "#include \"danube.dtsi\"\n\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"siemens,gigaset-sx76x\", \"lantiq,xway\", \"lantiq,danube\";\n\tmodel = \"Gigaset SX761,SX762,SX763\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyLTQ0,115200\";\n\t};\n\n\tmemory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x0 0x2000000>;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <100>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tgpio_export {\n\t\tcompatible = \"gpio-export\";\n\t\t#size-cells = <0>;\n\n\t\tswitch {\n\t\t\tgpio-export,name = \"switch\";\n\t\t\tgpio-export,output = <1>;\n\t\t\tgpios = <&gpio 19 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n\n\tusb_vbus: regulator-usb-vbus {\n\t\tcompatible = \"regulator-fixed\";\n\n\t\tregulator-name = \"USB_VBUS\";\n\n\t\tregulator-min-microvolt = <5000000>;\n\t\tregulator-max-microvolt = <5000000>;\n\n\t\tgpio = <&gpio 29 GPIO_ACTIVE_HIGH>;\n\t\tenable-active-high;\n\t};\n};\n\n&gpios {\n\tstatus = \"okay\";\n};\n\n&gsw {\n\tphy-mode = \"rmii\";\n};\n\n&localbus {\n\tflash@0 {\n\t\tcompatible = \"lantiq,nor\";\n\t\tbank-width = <2>;\n\t\treg = <0 0x0 0x2000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"uboot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t};\n\n\t\t\tpartition@10000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x40000 0x7c0000>;\n\t\t\t};\n\t\t};\n\t};\n\n\tgpiomm: gpio@1 {\n\t\tcompatible = \"lantiq,gpio-mm\";\n\t\treg = <1 0x0 0x10 >;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\t#gpio-cells = <2>;\n\t\tgpio-controller;\n\t\tlantiq,shadow = <0x3>;\n\t};\n};\n\n&pci0 {\n\tstatus = \"okay\";\n\tgpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>;\n};\n\n&usb_phy {\n\tstatus = \"okay\";\n};\n\n&usb {\n\tstatus = \"okay\";\n\tvbus-supply = <&usb_vbus>;\n};\n\n&vmmc {\n\tstatus = \"okay\";\n\tgpios = <&gpiomm 1 GPIO_ACTIVE_HIGH>;\n};\n"
  },
  {
    "path": "target/linux/lantiq/files/arch/mips/boot/dts/lantiq/falcon.dtsi",
    "content": "/dts-v1/;\n\n/ {\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\tcompatible = \"lantiq,falcon\";\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu@0 {\n\t\t\tcompatible = \"mips,mips34kc\";\n\t\t\treg = <0>;\n\t\t};\n\t};\n\n\taliases {\n\t\tserial0 = &serial0;\n\t\tserial1 = &serial1;\n\t\tgpio0 = &gpio0;\n\t\tgpio1 = &gpio1;\n\t\tgpio2 = &gpio2;\n\t\tgpio3 = &gpio3;\n\t\tgpio4 = &gpio4;\n\t};\n\n\tchosen {\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\tebu_cs0: localbus@10000000 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"lantiq,localbus\", \"simple-bus\";\n\t\treg = <0x10000000 0x4000000>;\n\t\tranges = <0x0 0x10000000 0x4000000>;\n\t};\n\tebu_cs1: localbus@14000000 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"lantiq,localbus\", \"simple-bus\";\n\t\treg = <0x14000000 0x4000000>;\n\t\tranges = <0x0 0x14000000 0x4000000>;\n\t};\n\n\tebu@18000000 {\n\t\tcompatible = \"lantiq,ebu-falcon\";\n\t\treg = <0x18000000 0x100>;\n\t};\n\n\tsbs2@1d000000 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"lantiq,sysb2\", \"simple-bus\";\n\t\treg = <0x1d000000 0x1000000>;\n\t\tranges = <0x0 0x1d000000 0x1000000>;\n\n\t\tclock_sysgpe: clock-controller@700000 {\n\t\t\tcompatible = \"lantiq,sysgpe-falcon\";\n\t\t\treg = <0x700000 0x100>;\n\t\t\t#clock-cells = <1>;\n\t\t};\n\n\t\tmps@4000 {\n\t\t\tcompatible = \"lantiq,mps-falcon\", \"lantiq,mps-xrx100\";\n\t\t\treg = <0x4000 0x1000>;\n\t\t\tinterrupt-parent = <&icu0>;\n\t\t\tinterrupts = <154 155>;\n\t\t\tlantiq,mbx = <&mpsmbx>;\n\t\t};\n\n\t\tgpio0: gpio@810000 {\n\t\t\tcompatible = \"lantiq,falcon-gpio\";\n\t\t\tgpio-controller;\n\t\t\t#gpio-cells = <2>;\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\tinterrupt-parent = <&icu0>;\n\t\t\tinterrupts = <44>;\n\t\t\treg = <0x810000 0x80>;\n\t\t\tclocks = <&clock_syseth 16>;\n\t\t};\n\n\t\tgpio2: gpio@810100 {\n\t\t\tcompatible = \"lantiq,falcon-gpio\";\n\t\t\tgpio-controller;\n\t\t\t#gpio-cells = <2>;\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\tinterrupt-parent = <&icu0>;\n\t\t\tinterrupts = <46>;\n\t\t\treg = <0x810100 0x80>;\n\t\t\tclocks = <&clock_syseth 17>;\n\t\t};\n\n\t\tclock_syseth: clock-controller@b00000 {\n\t\t\tcompatible = \"lantiq,syseth-falcon\";\n\t\t\treg = <0xb00000 0x100>;\n\t\t\t#clock-cells = <1>;\n\t\t};\n\n\t\tpad@b01000 {\n\t\t\tcompatible = \"lantiq,pad-falcon\";\n\t\t\treg = <0xb01000 0x100>;\n\t\t\tlantiq,bank = <0>;\n\t\t\tclocks = <&clock_syseth 20>;\n\t\t};\n\n\t\tpad@b02000 {\n\t\t\tcompatible = \"lantiq,pad-falcon\";\n\t\t\treg = <0xb02000 0x100>;\n\t\t\tlantiq,bank = <2>;\n\t\t\tclocks = <&clock_syseth 21>;\n\t\t};\n\t};\n\n\tfpi@1e000000 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"lantiq,fpi\", \"simple-bus\";\n\t\treg = <0x1e000000 0x1000000>;\n\t\tranges = <0x0 0x1e000000 0x1000000>;\n\n\t\tserial1: serial@100b00 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"lantiq,asc\";\n\t\t\treg = <0x100b00 0x100>;\n\t\t\tinterrupt-parent = <&icu0>;\n\t\t\tinterrupts = <112 113 114>;\n\t\t\tline = <1>;\n\t\t\tpinctrl-names = \"default\";\n\t\t\tpinctrl-0 = <&asc1_pins>;\n\t\t\tclocks = <&clock_sys1 11>;\n\t\t};\n\n\t\tserial0: serial@100c00 {\n\t\t\tcompatible = \"lantiq,asc\";\n\t\t\treg = <0x100c00 0x100>;\n\t\t\tinterrupt-parent = <&icu0>;\n\t\t\tinterrupts = <104 105 106>;\n\t\t\tline = <0>;\n\t\t\tpinctrl-names = \"default\";\n\t\t\tpinctrl-0 = <&asc0_pins>;\n\t\t\tclocks = <&clock_sys1 12>;\n\t\t};\n\n\t\tspi: spi@100d00 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"lantiq,falcon-spi\", \"lantiq,xrx100-spi\", \"lantiq,spi-lantiq-ssc\";\n\t\t\tinterrupts = <22 23 24 25>;\n\t\t\tinterrupt-names = \"spi_tx\", \"spi_rx\", \"spi_err\", \"spi_frm\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0x100d00 0x100>;\n\t\t\tinterrupt-parent = <&icu0>;\n\t\t\tclocks = <&clock_sys1 13>;\n\t\t\tbase_cs = <1>;\n\t\t\tnum_cs = <2>;\n\t\t};\n\n\t\tgptc@100e00 {\n\t\t\tcompatible = \"lantiq,gptc-falcon\";\n\t\t\treg = <0x100e00 0x100>;\n\t\t};\n\n\t\ti2c: i2c@200000 {\n\t\t\tstatus = \"disabled\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tcompatible = \"lantiq,lantiq-i2c\";\n\t\t\treg = <0x200000 0x10000>;\n\t\t\tinterrupt-parent = <&icu0>;\n\t\t\tinterrupts = <18 19 20 21>;\n\t\t\tgpios = <&gpio1 7 0 &gpio1 8 0>;\n\t\t\tpinctrl-names = \"default\";\n\t\t\tpinctrl-0 = <&i2c_pins>;\n\t\t\tclocks = <&clock_sys1 14>;\n\t\t};\n\n\t\tgpio1: gpio@800100 {\n\t\t\tcompatible = \"lantiq,falcon-gpio\";\n\t\t\tgpio-controller;\n\t\t\t#gpio-cells = <2>;\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\tinterrupt-parent = <&icu0>;\n\t\t\tinterrupts = <45>;\n\t\t\treg = <0x800100 0x100>;\n\t\t\tclocks = <&clock_sys1 16>;\n\t\t};\n\n\t\tgpio3: gpio@800200 {\n\t\t\tcompatible = \"lantiq,falcon-gpio\";\n\t\t\tgpio-controller;\n\t\t\t#gpio-cells = <2>;\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\tinterrupt-parent = <&icu0>;\n\t\t\tinterrupts = <47>;\n\t\t\treg = <0x800200 0x100>;\n\t\t\tclocks = <&clock_sys1 17>;\n\t\t};\n\n\t\tgpio4: gpio@800300 {\n\t\t\tcompatible = \"lantiq,falcon-gpio\";\n\t\t\tgpio-controller;\n\t\t\t#gpio-cells = <2>;\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\tinterrupt-parent = <&icu0>;\n\t\t\tinterrupts = <48>;\n\t\t\treg = <0x800300 0x100>;\n\t\t\tclocks = <&clock_sys1 18>;\n\t\t};\n\n\t\tpad@800400 {\n\t\t\tcompatible = \"lantiq,pad-falcon\";\n\t\t\treg = <0x800400 0x100>;\n\t\t\tlantiq,bank = <1>;\n\t\t\tclocks = <&clock_sys1 20>;\n\t\t};\n\n\t\tpad@800500 {\n\t\t\tcompatible = \"lantiq,pad-falcon\";\n\t\t\treg = <0x800500 0x100>;\n\t\t\tlantiq,bank = <3>;\n\t\t\tclocks = <&clock_sys1 21>;\n\t\t};\n\n\t\tpad@800600 {\n\t\t\tcompatible = \"lantiq,pad-falcon\";\n\t\t\treg = <0x800600 0x100>;\n\t\t\tlantiq,bank = <4>;\n\t\t\tclocks = <&clock_sys1 22>;\n\t\t};\n\n\t\tstatus@802000 {\n\t\t\tcompatible = \"lantiq,status-falcon\";\n\t\t\treg = <0x802000 0x80>;\n\t\t};\n\n\t\tclock_sys1: clock-controller@f00000 {\n\t\t\tcompatible = \"lantiq,sys1-falcon\";\n\t\t\treg = <0xf00000 0x100>;\n\t\t\t#clock-cells = <1>;\n\t\t};\n\t};\n\n\tsbs0@1f000000 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"simple-bus\";\n\t\treg = <0x1f000000 0x400000>;\n\t\tranges = <0x0 0x1f000000 0x400000>;\n\n\t\tmpsmbx: mpsmbx@200000 {\n\t\t\treg = <0x200000 0x200>;\n\t\t};\n\t};\n\n\tbiu@1f800000 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"lantiq,biu\", \"simple-bus\";\n\t\treg = <0x1f800000 0x800000>;\n\t\tranges = <0x0 0x1f800000 0x800000>;\n\n\t\ticu0: icu@80200 {\n\t\t\t#interrupt-cells = <1>;\n\t\t\tinterrupt-controller;\n\t\t\tcompatible = \"lantiq,icu\";\n\t\t\t/* TODO: Number of ICUs isn't known */\n\t\t\treg = <0x80200 0xc8>;\n\t\t};\n\n\t\twatchdog@803f0 {\n\t\t\tcompatible = \"lantiq,wdt\";\n\t\t\treg = <0x803f0 0x10>;\n\t\t};\n\t};\n\n\tpinctrl {\n\t\tcompatible = \"lantiq,pinctrl-falcon\";\n\t\tpinctrl-names = \"default\";\n\t\tpinctrl-0 = <&state_default>;\n\n\t\tstate_default: pinctrl0 {\n\t\t\t/*ntr {\n\t\t\t\tlantiq,groups = \"ntr8k\";\n\t\t\t\tlantiq,function = \"ntr\";\n\t\t\t};*/\n\t\t\thrst {\n\t\t\t\tlantiq,groups = \"hrst\";\n\t\t\t\tlantiq,function = \"rst\";\n\t\t\t};\n\t\t};\n\n\t\tasc0_pins: asc0 {\n\t\t\tasc0 {\n\t\t\t\tlantiq,groups = \"asc0\";\n\t\t\t\tlantiq,function = \"asc\";\n\t\t\t};\n\t\t};\n\t\tasc1_pins: asc1 {\n\t\t\tasc1 {\n\t\t\t\tlantiq,groups = \"asc1\";\n\t\t\t\tlantiq,function = \"asc\";\n\t\t\t};\n\t\t};\n\t\ti2c_pins: i2c_pins {\n\t\t\ti2c_pins {\n\t\t\t\tlantiq,groups = \"i2c\";\n\t\t\t\tlantiq,function = \"i2c\";\n\t\t\t};\n\t\t};\n\t\tbootled_pins: bootled {\n\t\t\tbootled {\n\t\t\t\tlantiq,groups = \"bootled\";\n\t\t\t\tlantiq,function = \"led\";\n\t\t\t};\n\t\t};\n\t\tntr_ntr8k: ntr8k {\n\t\t\tntr8k {\n\t\t\t\tlantiq,groups = \"ntr8k\";\n\t\t\t\tlantiq,function = \"ntr\";\n\t\t\t};\n\t\t};\n\t\tntr_pps: pps {\n\t\t\tpps {\n\t\t\t\tlantiq,groups = \"pps\";\n\t\t\t\tlantiq,function = \"ntr\";\n\t\t\t};\n\t\t};\n\t\tntr_gpio: gpio {\n\t\t\tgpio {\n\t\t\t\tlantiq,pins = \"io5\";\n\t\t\t\tlantiq,mux = <1>;\n\t\t\t\tlantiq,output = <0>;\n\t\t\t};\n\t\t};\n\t\tslic_pins: slic {\n\t\t\tslic {\n\t\t\t\tlantiq,groups = \"slic\";\n\t\t\t\tlantiq,function = \"slic\";\n\t\t\t};\n\t\t};\n\t};\n\n\tpinselect-ntr {\n\t\tcompatible = \"lantiq,onu-ntr\",\"lantiq,pinselect-ntr\";\n\t\tpinctrl-names = \"ntr8k\", \"pps\", \"gpio\";\n\t\tpinctrl-0 = <&ntr_ntr8k>;\n\t\tpinctrl-1 = <&ntr_pps>;\n\t\tpinctrl-2 = <&ntr_gpio>;\n\t};\n\n\tpinselect-asc1 {\n\t\tcompatible = \"lantiq,onu-asc1\",\"lantiq,pinselect-asc1\";\n\t\tpinctrl-names = \"default\", \"asc1\";\n\t\tpinctrl-0 = <&slic_pins>;\n\t\tpinctrl-1 = <&asc1_pins>;\n\t};\n\n};\n"
  },
  {
    "path": "target/linux/lantiq/files/arch/mips/boot/dts/lantiq/falcon_lantiq_easy88388.dts",
    "content": "#include \"falcon.dtsi\"\n#include \"falcon_sflash-16m.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n\n/ {\n\tmodel = \"Lantiq Falcon FTTDP8 Reference Board\";\n\tcompatible = \"lantiq,easy88388\", \"lantiq,falcon\";\n\n\taliases {\n\t\tspi0 = &ebu_cs0;\n\t};\n\n\tmemory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x0 0x4000000>;  // 64M at 0x0\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 1 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <0x198>;\n\t\t};\n\t};\n\n\tpinctrl {\n\t\tled_pins: led-pins {\n\t\t\tlantiq,pins = \"io34\", \"io35\", \"io36\", \"io37\", \"io38\",\n\t\t\t\t\t\"io39\", \"io40\", \"io41\";\n\t\t\tlantiq,function = \"gpio\";\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tpinctrl-names = \"default\";\n\t\tpinctrl-0 = <&led_pins &bootled_pins>;\n\n\t\tGPON {\n\t\t\tlabel = \"green:gpon\";\n\t\t\tgpios = <&gpio0 11 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t\tTEST {\n\t\t\tlabel = \"green:test\";\n\t\t\tgpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t\tSTATUS {\n\t\t\tlabel = \"green:status\";\n\t\t\tgpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t\tERROR {\n\t\t\tlabel = \"red:error\";\n\t\t\tgpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tDSL1 {\n\t\t\tlabel = \"dsl:1\";\n\t\t\tgpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t\tDSL2 {\n\t\t\tlabel = \"dsl:2\";\n\t\t\tgpios = <&gpio0 13 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t\tDSL3 {\n\t\t\tlabel = \"dsl:3\";\n\t\t\tgpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t\tDSL4 {\n\t\t\tlabel = \"dsl:4\";\n\t\t\tgpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t\tDSL5 {\n\t\t\tlabel = \"dsl:5\";\n\t\t\tgpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t\tDSL6 {\n\t\t\tlabel = \"dsl:6\";\n\t\t\tgpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t\tDSL7 {\n\t\t\tlabel = \"dsl:7\";\n\t\t\tgpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t\tDSL8 {\n\t\t\tlabel = \"dsl:8\";\n\t\t\tgpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n"
  },
  {
    "path": "target/linux/lantiq/files/arch/mips/boot/dts/lantiq/falcon_lantiq_easy88444.dts",
    "content": "#include \"falcon.dtsi\"\n#include \"falcon_sflash-16m.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n\n/ {\n\tmodel = \"Lantiq Falcon FTTdp G.FAST Reference Board\";\n\tcompatible = \"lantiq,easy88444\", \"lantiq,falcon\";\n\n\taliases {\n\t\tspi0 = &ebu_cs0;\n\t};\n\n\tmemory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x0 0x4000000>;\t// 64M at 0x0\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 1 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <0x198>;\n\t\t};\n\t};\n\n\tpinctrl {\n\t\tled_pins: led-pins {\n\t\t\tlantiq,pins = \"io34\", \"io35\", \"io37\";\n\t\t\tlantiq,function = \"gpio\";\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tpinctrl-names = \"default\";\n\t\tpinctrl-0 = <&led_pins &bootled_pins>;\n\n\t\tGPON {\n\t\t\tlabel = \"green:gpon\";\n\t\t\tgpios = <&gpio0 11 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t\tTEST {\n\t\t\tlabel = \"green:test\";\n\t\t\tgpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t\tSTATUS {\n\t\t\tlabel = \"green:status\";\n\t\t\tgpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tGFAST1 {\n\t\t\tlabel = \"gfast:1\";\n\t\t\tgpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t\tGFAST2 {\n\t\t\tlabel = \"gfast:2\";\n\t\t\tgpios = <&gpio0 13 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t\tGFAST3 {\n\t\t\tlabel = \"gfast:3\";\n\t\t\tgpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t\tGFAST4 {\n\t\t\tlabel = \"gfast:4\";\n\t\t\tgpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n"
  },
  {
    "path": "target/linux/lantiq/files/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98000-nand.dts",
    "content": "#include \"falcon_lantiq_easy98000.dtsi\"\n\n/ {\n\tmodel = \"Lantiq Falcon (NAND)\";\n\tcompatible = \"lantiq,easy98000-nand\", \"lantiq,easy98000\", \"lantiq,falcon\";\n\n\taliases {\n\t\tspi0 = &spi;\n\t};\n};\n\n&ebu_cs0 {\n\tflash@0 {\n\t\tcompatible = \"gen_nand\", \"lantiq,nand-falcon\";\n\t\tbank-width = <1>;\n\t\treg = <0x0 0x40000>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tbbt-use-flash;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"uboot\";\n\t\t\treg = <0x00000 0x40000>;\n\t\t};\n\n\t\tpartition@10000 {\n\t\t\tlabel = \"u-boot-env\";\n\t\t\treg = <0x40000 0x40000>;\n\t\t};\n\n\t\tpartition@20000 {\n\t\t\tlabel = \"linux\";\n\t\t\treg = <0x80000 0x3d0000>;\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/lantiq/files/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98000-nor.dts",
    "content": "#include \"falcon_lantiq_easy98000.dtsi\"\n\n/ {\n\tmodel = \"Lantiq Falcon (NOR)\";\n\tcompatible = \"lantiq,easy98000-nor\", \"lantiq,easy98000\", \"lantiq,falcon\";\n\n\taliases {\n\t\tspi0 = &spi;\n\t};\n};\n\n&ebu_cs0 {\n\tflash@0 {\n\t\tcompatible = \"lantiq,nor\";\n\t\tbank-width = <2>;\n\t\treg = <0x0 0x4000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"uboot\";\n\t\t\t\treg = <0x00000 0x40000>;\n\t\t\t};\n\n\t\t\tpartition@10000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x40000 0x40000>;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tlabel = \"linux\";\n\t\t\t\treg = <0x80000 0x3d0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/lantiq/files/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98000-sflash.dts",
    "content": "#include \"falcon_lantiq_easy98000.dtsi\"\n#include \"falcon_sflash-16m.dtsi\"\n\n/ {\n\tmodel = \"Lantiq Falcon (SFLASH)\";\n\tcompatible = \"lantiq,easy98000-sflash\", \"lantiq,easy98000\", \"lantiq,falcon\";\n\n\taliases {\n\t\tspi0 = &ebu_cs0;\n\t\tspi1 = &spi;\n\t};\n};\n"
  },
  {
    "path": "target/linux/lantiq/files/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98000.dtsi",
    "content": "#include \"falcon.dtsi\"\n\n#include <dt-bindings/interrupt-controller/irq.h>\n#include <dt-bindings/gpio/gpio.h>\n\n/ {\n\tcompatible = \"lantiq,easy98000\", \"lantiq,falcon\";\n\n\tmemory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x0 0x4000000>;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tpinctrl-names = \"default\";\n\t\tpinctrl-0 = <&bootled_pins>;\n\n\t\tLED_0 {\n\t\t\tlabel = \"green:gpon\";\n\t\t\tgpios = <&gpio0 9 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"keep\";\n\t\t};\n\t\tLED_1 {\n\t\t\tlabel = \"red:gpon\";\n\t\t\tgpios = <&gpio0 10 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"keep\";\n\t\t};\n\t\tLED_2 {\n\t\t\tlabel = \"green:gpon_tx\";\n\t\t\tgpios = <&gpio0 11 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"keep\";\n\t\t};\n\t\tLED_3 {\n\t\t\tlabel = \"green:gpon_rx\";\n\t\t\tgpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"keep\";\n\t\t};\n\t\tLED_4 {\n\t\t\tlabel = \"green:voice\";\n\t\t\tgpios = <&gpio0 13 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"keep\";\n\t\t};\n\t\tLED_5 {\n\t\t\tlabel = \"green:status\";\n\t\t\tgpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"keep\";\n\t\t};\n\t};\n};\n\n&ebu_cs1 {\n\teth0: ethernet@3 {\n\t\tcompatible = \"davicom,dm9000\";\n\t\tdevice_type = \"network\";\n\t\treg = <0x0000003 0x1>, <0x0000001 0x1>;\n\t\treg-names = \"addr\", \"data\";\n\t\tinterrupt-parent = <&gpio1>;\n\t\t#interrupt-cells = <2>;\n\t\tinterrupts = <10 IRQ_TYPE_LEVEL_LOW>;\n\t\tlocal-mac-address = [ 00 00 00 00 00 00 ];\n\t};\n\n\tcpld@3c00000 {\n\t\tcompatible = \"lantiq,easy98000_addon\";\n\t\treg = <0x3c00000 0x2>;\n\t};\n\n\tcpld@3c0000c {\n\t\tcompatible = \"lantiq,easy98000_cpld_led\";\n\t\treg = <0x3c0000c 0x2>,  <0x3c00012 0x2>;\n\t};\n};\n\n/* // enable this for second uart:\n&serial1 {\n\tstatus = \"okay\";\n};*/\n\n&spi {\n\tstatus = \"okay\";\n\n\teeprom@2 {\n\t\tcompatible = \"atmel,at25\", \"atmel,at25160n\";\n\t\treg = <2>;\n\t\tspi-max-frequency = <1000000>;\n\t\tspi-cpha;\n\t\tspi-cpol;\n\n\t\tpagesize = <32>;\n\t\tsize = <2048>;\n\t\taddress-width = <16>;\n\t};\n};\n\n&i2c {\n\tstatus = \"okay\";\n\n\tclock-frequency = <100000>;\n\n\t/* eeprom-emulation by OMU */\n\teeprom@50 {\n\t\tcompatible = \"at,24c02\";\n\t\treg = <0x50>;\n\t};\n\teeprom@51 {\n\t\tcompatible = \"at,24c02\";\n\t\treg = <0x51>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/lantiq/files/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98020-v18.dts",
    "content": "#include \"falcon.dtsi\"\n#include \"falcon_sflash-16m.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n\n/ {\n\tmodel = \"Lantiq Falcon Reference Board V1.8\";\n\tcompatible = \"lantiq,easy98020-v18\", \"lantiq,easy98020\", \"lantiq,falcon\";\n\n\taliases {\n\t\tspi0 = &ebu_cs0;\n\t};\n\n\tmemory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x0 0x4000000>;  // 64M at 0x0\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 1 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <0x198>;\n\t\t};\n\t};\n\n\tpinctrl {\n\t\tled_pins: led-pins {\n\t\t\tlantiq,pins = \"io11\", \"io14\", \"io36\", \"io37\", \"io38\";\n\t\t\tlantiq,function = \"gpio\";\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tpinctrl-names = \"default\";\n\t\tpinctrl-0 = <&led_pins &bootled_pins>;\n\n\t\tGPON {\n\t\t\tlabel = \"green:gpon\";\n\t\t\tgpios = <&gpio0 11 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"keep\";\n\t\t};\n\t\tTEST {\n\t\t\tlabel = \"green:test\";\n\t\t\tgpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"keep\";\n\t\t};\n\t\tETH {\n\t\t\tlabel = \"green:status\";\n\t\t\tgpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"keep\";\n\t\t};\n\t\tVOICE {\n\t\t\tlabel = \"green:voice\";\n\t\t\tgpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"keep\";\n\t\t};\n\t\tVIDEO {\n\t\t\tlabel = \"green:video\";\n\t\t\tgpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"keep\";\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/lantiq/files/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98020.dts",
    "content": "#include \"falcon.dtsi\"\n#include \"falcon_sflash-16m.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n\n/ {\n\tmodel = \"Lantiq Falcon Reference Board\";\n\tcompatible = \"lantiq,easy98020\", \"lantiq,falcon\";\n\n\taliases {\n\t\tspi0 = &ebu_cs0;\n\t};\n\n\tmemory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x0 0x4000000>;  // 64M at 0x0\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 1 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <0x198>;\n\t\t};\n\t};\n\n\tpinctrl {\n\t\tled_pins: phy-led-pins {\n\t\t\tlantiq,pins = \"io42\", \"io41\", \"io38\", \"io37\";\n\t\t\tlantiq,function = \"gpio\";\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tpinctrl-names = \"default\";\n\t\tpinctrl-0 = <&bootled_pins>, <&led_pins>;\n\n\t\tGPON {\n\t\t\tlabel = \"green:gpon\";\n\t\t\tgpios = <&gpio0 9 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"keep\";\n\t\t};\n\t\tTEST {\n\t\t\tlabel = \"green:test\";\n\t\t\tgpios = <&gpio0 10 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"keep\";\n\t\t};\n\t\tETH {\n\t\t\tlabel = \"green:status\";\n\t\t\tgpios = <&gpio0 11 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"keep\";\n\t\t};\n\t\tVOICE {\n\t\t\tlabel = \"green:voice\";\n\t\t\tgpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"keep\";\n\t\t};\n\t\tVIDEO {\n\t\t\tlabel = \"green:video\";\n\t\t\tgpios = <&gpio0 13 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"keep\";\n\t\t};\n\n\t\tGE0_ACT {\n\t\t\tlabel = \"ge0_act\";\n\t\t\tgpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t\tGE0_LINK {\n\t\t\tlabel = \"ge0_link\";\n\t\t\tgpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t\tGE1_ACT {\n\t\t\tlabel = \"ge1_act\";\n\t\t\tgpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t\tGE1_LINK {\n\t\t\tlabel = \"ge1_link\";\n\t\t\tgpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/lantiq/files/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98021.dts",
    "content": "#include \"falcon.dtsi\"\n#include \"falcon_sflash-16m.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n\n/ {\n\tmodel = \"Lantiq Falcon HGU Reference Board\";\n\tcompatible = \"lantiq,easy98021\", \"lantiq,easy98020\", \"lantiq,falcon\";\n\n\taliases {\n\t\tspi0 = &ebu_cs0;\n\t};\n\n\tmemory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x0 0x4000000>;\t// 64M at 0x0\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 1 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <0x198>;\n\t\t};\n\t};\n\n\tgpio-mmc {\n\t\t/* Place-holder for SIM-Card connector,\n\t\t   to list the used GPIOs, no official binding */\n\t\tcompatible = \"gpio-mmc\";\n\t\tgpios = <&gpio0 3 GPIO_ACTIVE_HIGH>,\n\t\t\t<&gpio0 3 GPIO_ACTIVE_HIGH>,\n\t\t\t<&gpio0 2 GPIO_ACTIVE_HIGH>,\n\t\t\t<0>; /* no CS */\n\t\tgpio-names = \"di\", \"do\", \"clk\", \"cs\";\n\t\treset-gpio = <&gpio3 24 GPIO_ACTIVE_HIGH>;\n\t};\n\n\tpinctrl {\n\t\tled_pins: led-pins {\n\t\t\tlantiq,pins = \"io11\", \"io14\", \"io36\", \"io37\", \"io38\";\n\t\t\tlantiq,function = \"gpio\";\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tpinctrl-names = \"default\";\n\t\tpinctrl-0 = <&led_pins &bootled_pins>;\n\n\t\tGPON {\n\t\t\tlabel = \"green:gpon\";\n\t\t\tgpios = <&gpio0 11 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"keep\";\n\t\t};\n\t\tTEST {\n\t\t\tlabel = \"red:test\";\n\t\t\tgpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"keep\";\n\t\t};\n\t\tETH {\n\t\t\tlabel = \"green:status\";\n\t\t\tgpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"keep\";\n\t\t};\n\t\tVOICE {\n\t\t\tlabel = \"green:voice\";\n\t\t\tgpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"keep\";\n\t\t};\n\t\tSIMCARD {\n\t\t\tlabel = \"green:simcard\";\n\t\t\tgpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"keep\";\n\t\t};\n\t};\n};\n\n"
  },
  {
    "path": "target/linux/lantiq/files/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98035synce.dts",
    "content": "#include \"falcon.dtsi\"\n#include \"falcon_sflash-16m.dtsi\"\n\n/ {\n\tmodel = \"Lantiq Falcon SFP Stick with SyncE\";\n\tcompatible = \"lantiq,easy98035synce\", \"lantiq,falcon-sfp\", \"lantiq,falcon\";\n\n\taliases {\n\t\tspi0 = &ebu_cs0;\n\t};\n\n\tmemory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x0 0x4000000>;  // 64M at 0x0\n\t};\n\n\tpinctrl {\n\t\tcompatible = \"lantiq,pinctrl-falcon\";\n\n\t\tasc0_func1: func1 {\n\t\t\tfunc1_tx {\n\t\t\t\tlantiq,pins = \"io32\";\n\t\t\t\tlantiq,mux = <1>;\n\t\t\t\tlantiq,input = <0>;\n\t\t\t};\n\t\t\tfunc1_rx {\n\t\t\t\tlantiq,pins = \"io33\";\n\t\t\t\tlantiq,mux = <0>;\n\t\t\t};\n\t\t};\n\t\tasc0_func2: func2 {\n\t\t\tfunc2_tx {\n\t\t\t\tlantiq,pins = \"io32\";\n\t\t\t\tlantiq,mux = <0>;\n\t\t\t};\n\t\t\tfunc2_rx {\n\t\t\t\tlantiq,pins = \"io33\";\n\t\t\t\tlantiq,mux = <1>;\n\t\t\t\tlantiq,input = <0>;\n\t\t\t};\n\t\t};\n\t\tasc0_func3: func3 {\n\t\t\tfunc3_tx {\n\t\t\t\tlantiq,pins = \"io32\";\n\t\t\t\tlantiq,mux = <1>;\n\t\t\t\tlantiq,input = <0>;\n\t\t\t};\n\t\t\tfunc3_rx {\n\t\t\t\tlantiq,pins = \"io33\";\n\t\t\t\tlantiq,mux = <1>;\n\t\t\t\tlantiq,input = <0>;\n\t\t\t};\n\t\t};\n\t};\n\n\tpinselect-asc0 {\n\t\tcompatible = \"lantiq,pinselect-asc0\";\n\t\tpinctrl-names = \"asc0\", \"func1\", \"func2\", \"func3\";\n\t\tpinctrl-0 = <&asc0_pins>;\n\t\tpinctrl-1 = <&asc0_func1>;\n\t\tpinctrl-2 = <&asc0_func2>;\n\t\tpinctrl-3 = <&asc0_func3>;\n\t};\n};\n\n&serial0 {\n\tpinctrl-names = \"default\";\n\t/* use \"empty\" pinctrl to leave setting from u-boot enabled */\n\tpinctrl-0 = < >;\n};\n\n&i2c {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/lantiq/files/arch/mips/boot/dts/lantiq/falcon_lantiq_easy98035synce1588.dts",
    "content": "#include \"falcon.dtsi\"\n#include \"falcon_sflash-16m.dtsi\"\n\n/ {\n\tmodel = \"Lantiq Falcon SFP Stick with SyncE/1588\";\n\tcompatible = \"lantiq,easy98035synce1588\", \"lantiq,falcon-sfp\", \"lantiq,falcon\";\n\n\taliases {\n\t\tspi0 = &ebu_cs0;\n\t};\n\n\tmemory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x0 0x4000000>;  // 64M at 0x0\n\t};\n\n\tpinctrl {\n\t\tcompatible = \"lantiq,pinctrl-falcon\";\n\n\t\tasc0_func1: func1 {\n\t\t\tfunc1_tx {\n\t\t\t\tlantiq,pins = \"io32\";\n\t\t\t\tlantiq,mux = <1>;\n\t\t\t\tlantiq,input = <0>;\n\t\t\t};\n\t\t\tfunc1_rx {\n\t\t\t\tlantiq,pins = \"io33\";\n\t\t\t\tlantiq,mux = <0>;\n\t\t\t};\n\t\t};\n\t\tasc0_func2: func2 {\n\t\t\tfunc2_tx {\n\t\t\t\tlantiq,pins = \"io32\";\n\t\t\t\tlantiq,mux = <0>;\n\t\t\t};\n\t\t\tfunc2_rx {\n\t\t\t\tlantiq,pins = \"io33\";\n\t\t\t\tlantiq,mux = <1>;\n\t\t\t\tlantiq,input = <0>;\n\t\t\t};\n\t\t};\n\t\tasc0_func3: func3 {\n\t\t\tfunc3_tx {\n\t\t\t\tlantiq,pins = \"io32\";\n\t\t\t\tlantiq,mux = <1>;\n\t\t\t\tlantiq,input = <0>;\n\t\t\t};\n\t\t\tfunc3_rx {\n\t\t\t\tlantiq,pins = \"io33\";\n\t\t\t\tlantiq,mux = <1>;\n\t\t\t\tlantiq,input = <0>;\n\t\t\t};\n\t\t};\n\t};\n\n\tpinselect-asc0 {\n\t\tcompatible = \"lantiq,pinselect-asc0\";\n\t\tpinctrl-names = \"asc0\", \"func1\", \"func2\", \"func3\";\n\t\tpinctrl-0 = <&asc0_pins>;\n\t\tpinctrl-1 = <&asc0_func1>;\n\t\tpinctrl-2 = <&asc0_func2>;\n\t\tpinctrl-3 = <&asc0_func3>;\n\t};\n};\n\n&serial0 {\n\tpinctrl-names = \"default\";\n\t/* use \"empty\" pinctrl to leave setting from u-boot enabled */\n\tpinctrl-0 = < >;\n};\n\n&i2c {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/lantiq/files/arch/mips/boot/dts/lantiq/falcon_lantiq_falcon-mdu.dts",
    "content": "#include \"falcon.dtsi\"\n#include \"falcon_sflash-16m.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n\n/ {\n\tmodel = \"Lantiq Falcon / Vinax MDU Board\";\n\tcompatible = \"lantiq,falcon-mdu\", \"lantiq,falcon\";\n\n\taliases {\n\t\tspi0 = &ebu_cs0;\n\t};\n\n\tmemory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x0 0x4000000>;  // 64M at 0x0\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tpinctrl-names = \"default\";\n\t\tpinctrl-0 = <&bootled_pins>;\n\n\t\tLED_0 {\n\t\t\tlabel = \"green:gpon\";\n\t\t\tgpios = <&gpio0 9 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"keep\";\n\t\t};\n\t\tLED_1 {\n\t\t\tlabel = \"green:status\";\n\t\t\tgpios = <&gpio0 10 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"keep\";\n\t\t};\n\t\tLED_2 {\n\t\t\tlabel = \"green:2\";\n\t\t\tgpios = <&gpio0 11 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"keep\";\n\t\t};\n\t\tLED_3 {\n\t\t\tlabel = \"green:3\";\n\t\t\tgpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"keep\";\n\t\t};\n\t\tLED_4 {\n\t\t\tlabel = \"green:4\";\n\t\t\tgpios = <&gpio0 13 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"keep\";\n\t\t};\n\t};\n};\n\n"
  },
  {
    "path": "target/linux/lantiq/files/arch/mips/boot/dts/lantiq/falcon_lantiq_falcon-sfp.dts",
    "content": "#include \"falcon.dtsi\"\n#include \"falcon_sflash-16m.dtsi\"\n\n/ {\n\tmodel = \"Lantiq Falcon SFP Stick\";\n\tcompatible = \"lantiq,falcon-sfp\", \"lantiq,falcon\";\n\n\taliases {\n\t\tspi0 = &ebu_cs0;\n\t};\n\n\tmemory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x0 0x4000000>;  // 64M at 0x0\n\t};\n\n\tpinctrl {\n\t\tcompatible = \"lantiq,pinctrl-falcon\";\n\n\t\tasc0_func1: func1 {\n\t\t\tfunc1_tx {\n\t\t\t\tlantiq,pins = \"io32\";\n\t\t\t\tlantiq,mux = <1>;\n\t\t\t\tlantiq,output = <0>;\n\t\t\t};\n\t\t\tfunc1_rx {\n\t\t\t\tlantiq,pins = \"io33\";\n\t\t\t\tlantiq,mux = <0>;\n\t\t\t};\n\t\t};\n\t\tasc0_func2: func2 {\n\t\t\tfunc2_tx {\n\t\t\t\tlantiq,pins = \"io32\";\n\t\t\t\tlantiq,mux = <0>;\n\t\t\t};\n\t\t\tfunc2_rx {\n\t\t\t\tlantiq,pins = \"io33\";\n\t\t\t\tlantiq,mux = <1>;\n\t\t\t\tlantiq,input = <0>;\n\t\t\t};\n\t\t};\n\t\tasc0_func3: func3 {\n\t\t\tfunc3_tx {\n\t\t\t\tlantiq,pins = \"io32\";\n\t\t\t\tlantiq,mux = <1>;\n\t\t\t\tlantiq,output = <0>;\n\t\t\t};\n\t\t\tfunc3_rx {\n\t\t\t\tlantiq,pins = \"io33\";\n\t\t\t\tlantiq,mux = <1>;\n\t\t\t\tlantiq,input = <0>;\n\t\t\t};\n\t\t};\n\t};\n\n\tpinselect-asc0 {\n\t\tcompatible = \"lantiq,pinselect-asc0\";\n\t\tpinctrl-names = \"asc0\", \"func1\", \"func2\", \"func3\";\n\t\tpinctrl-0 = <&asc0_pins>;\n\t\tpinctrl-1 = <&asc0_func1>;\n\t\tpinctrl-2 = <&asc0_func2>;\n\t\tpinctrl-3 = <&asc0_func3>;\n\t};\n};\n\n&serial0 {\n\tpinctrl-names = \"default\";\n\t/* use \"empty\" pinctrl to leave setting from u-boot enabled */\n\tpinctrl-0 = < >;\n};\n\n&i2c {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/lantiq/files/arch/mips/boot/dts/lantiq/falcon_sflash-16m.dtsi",
    "content": "\n&ebu_cs0 {\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\tcompatible = \"lantiq,sflash-falcon\", \"simple-bus\";\n\n\tflash@0 {\n\t\tcompatible = \"spansion,s25fl129p0\", \"spansion,s25fl129p1\";\n\t\treg = <0 0>;\n\t\tspi-max-frequency = <80000000>;\n\t\tm25p,fast-read;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\treg = <0x0 0x40000>;\n\t\t\t\tlabel = \"uboot\";\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\treg = <0x40000 0x80000>;\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t};\n\n\t\t\tpartition@c0000 {\n\t\t\t\treg = <0xc0000 0x740000>;\n\t\t\t\tlabel = \"image0\";\n\t\t\t};\n\n\t\t\tpartition@800000 {\n\t\t\t\treg = <0x800000 0x800000>;\n\t\t\t\tlabel = \"image1\";\n\t\t\t};\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9.dtsi",
    "content": "/dts-v1/;\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/phy/phy-lantiq-vrx200-pcie.h>\n\n/ {\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\tcompatible = \"lantiq,xway\", \"lantiq,vr9\";\n\n\taliases {\n\t\tserial0 = &asc1;\n\t};\n\n\tchosen {\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu@0 {\n\t\t\tcompatible = \"mips,mips34Kc\";\n\t\t\treg = <0>;\n\t\t};\n\t};\n\n\tcputemp {\n\t\tcompatible = \"lantiq,cputemp\";\n\t};\n\n\treboot {\n\t\tcompatible = \"syscon-reboot\";\n\n\t\tregmap = <&rcu0>;\n\t\toffset = <0x10>;\n\t\tmask = <0xe0000000>;\n\t};\n\n\tbiu@1f800000 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"lantiq,biu\", \"simple-bus\";\n\t\treg = <0x1f800000 0x800000>;\n\t\tranges = <0x0 0x1f800000 0x7fffff>;\n\n\t\ticu0: icu@80200 {\n\t\t\t#interrupt-cells = <1>;\n\t\t\tinterrupt-controller;\n\t\t\tcompatible = \"lantiq,icu\";\n\t\t\treg = <0x80200 0xc8\t/* icu0 */\n\t\t\t       0x80300 0xc8>;\t/* icu1 */\n\t\t};\n\n\t\twatchdog@803f0 {\n\t\t\tcompatible = \"lantiq,xrx100-wdt\", \"lantiq,xrx100-wdt\";\n\t\t\treg = <0x803f0 0x10>;\n\n\t\t\tregmap = <&rcu0>;\n\t\t};\n\t};\n\n\tsram@1f000000 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"lantiq,sram\", \"simple-bus\";\n\t\treg = <0x1f000000 0x800000>;\n\t\tranges = <0x0 0x1f000000 0x7fffff>;\n\n\t\teiu0: eiu@101000 {\n\t\t\t#interrupt-cells = <1>;\n\t\t\tinterrupt-controller;\n\t\t\tcompatible = \"lantiq,eiu-xway\";\n\t\t\treg = <0x101000 0x1000>;\n\t\t\tinterrupt-parent = <&icu0>;\n\t\t\tlantiq,eiu-irqs = <166 135 66 40 41 42>;\n\t\t};\n\n\t\tpmu0: pmu@102000 {\n\t\t\tcompatible = \"lantiq,pmu-xway\";\n\t\t\treg = <0x102000 0x1000>;\n\t\t};\n\n\t\tcgu0: cgu@103000 {\n\t\t\tcompatible = \"lantiq,cgu-xway\";\n\t\t\treg = <0x103000 0x1000>;\n\t\t};\n\n\t\tdcdc@106a00 {\n\t\t\tcompatible = \"lantiq,dcdc-xrx200\";\n\t\t\treg = <0x106a00 0x200>;\n\t\t};\n\n\t\tvmmc: vmmc@107000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"lantiq,vmmc-xway\";\n\t\t\treg = <0x107000 0x300>;\n\t\t\tinterrupt-parent = <&icu0>;\n\t\t\tinterrupts = <150 151 152 153 154 155>;\n\t\t};\n\n\t\tpcie0_phy: phy@106800 {\n\t\t\tcompatible = \"lantiq,vrx200-pcie-phy\";\n\t\t\treg = <0x106800 0x100>;\n\t\t\tlantiq,rcu = <&rcu0>;\n\t\t\tlantiq,rcu-endian-offset = <0x4c>;\n\t\t\tlantiq,rcu-big-endian-mask = <0x80>; /* bit 7 */\n\t\t\tbig-endian;\n\t\t\tresets = <&reset0 12 24>, <&reset0 22 22>;\n\t\t\treset-names = \"phy\", \"pcie\";\n\t\t\t#phy-cells = <1>;\n\t\t};\n\n\t\trcu0: rcu@203000 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\t\t\tcompatible = \"lantiq,xrx200-rcu\", \"simple-mfd\", \"syscon\";\n\t\t\treg = <0x203000 0x100>;\n\t\t\tranges = <0x0 0x203000 0x100>;\n\t\t\tbig-endian;\n\n\t\t\treset0: reset-controller@10 {\n\t\t\t\tcompatible = \"lantiq,xrx200-reset\";\n\t\t\t\treg = <0x10 4>, <0x14 4>;\n\n\t\t\t\t#reset-cells = <2>;\n\t\t\t};\n\n\t\t\treset1: reset-controller@48 {\n\t\t\t\tcompatible = \"lantiq,xrx200-reset\";\n\t\t\t\treg = <0x48 4>, <0x24 4>;\n\n\t\t\t\t#reset-cells = <2>;\n\t\t\t};\n\n\t\t\tusb_phy0: usb2-phy@18 {\n\t\t\t\tcompatible = \"lantiq,xrx200-usb2-phy\";\n\t\t\t\treg = <0x18 4>, <0x38 4>;\n\t\t\t\tstatus = \"disabled\";\n\n\t\t\t\tresets = <&reset1 4 4>, <&reset0 4 4>;\n\t\t\t\treset-names = \"phy\", \"ctrl\";\n\t\t\t\t#phy-cells = <0>;\n\t\t\t};\n\n\t\t\tusb_phy1: usb2-phy@34 {\n\t\t\t\tcompatible = \"lantiq,xrx200-usb2-phy\";\n\t\t\t\treg = <0x34 4>, <0x3c 4>;\n\t\t\t\tstatus = \"disabled\";\n\n\t\t\t\tresets = <&reset1 5 5>, <&reset0 4 4>;\n\t\t\t\treset-names = \"phy\", \"ctrl\";\n\t\t\t\t#phy-cells = <0>;\n\t\t\t};\n\t\t};\n\t};\n\n\tfpi@10000000 {\n\t\tcompatible = \"lantiq,xrx200-fpi\", \"simple-bus\";\n\t\tranges = <0x0 0x10000000 0xf000000>;\n\t\treg =\t<0x1f400000 0x1000>,\n\t\t\t<0x10000000 0xf000000>;\n\t\tregmap = <&rcu0>;\n\t\toffset-endianness = <0x4c>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tlocalbus: localbus@0 {\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <1>;\n\t\t\tranges = <0 0 0x0 0x3ffffff /* addrsel0 */\n\t\t\t\t1 0 0x4000000 0x4000010>; /* addsel1 */\n\t\t\tcompatible = \"lantiq,localbus\", \"simple-bus\";\n\t\t};\n\n\t\tgptu@e100a00 {\n\t\t\tcompatible = \"lantiq,gptu-xway\";\n\t\t\treg = <0xe100a00 0x100>;\n\t\t\tinterrupt-parent = <&icu0>;\n\t\t\tinterrupts = <126 127 128 129 130 131>;\n\t\t};\n\n\t\tusif: usif@da00000 {\n\t\t\tcompatible = \"lantiq,usif\";\n\t\t\treg = <0xda00000 0x1000000>;\n\t\t\tinterrupt-parent = <&icu0>;\n\t\t\tinterrupts = <29 125 107 108 109 110>;\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tspi: spi@e100800 {\n\t\t\tcompatible = \"lantiq,xrx200-spi\", \"lantiq,xrx100-spi\";\n\t\t\treg = <0xe100800 0x100>;\n\t\t\tinterrupt-parent = <&icu0>;\n\t\t\tinterrupts = <22 23 24>;\n\t\t\tinterrupt-names = \"spi_rx\", \"spi_tx\", \"spi_err\",\n\t\t\t\t\t\"spi_frm\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tpinctrl-names = \"default\";\n\t\t\tpinctrl-0 = <&spi_pins>, <&spi_cs4_pins>;\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tgpio: pinmux@e100b10 {\n\t\t\tcompatible = \"lantiq,xrx200-pinctrl\";\n\t\t\t#gpio-cells = <2>;\n\t\t\tgpio-controller;\n\t\t\tgpio-ranges = <&gpio 0 0 50>;\n\t\t\treg = <0xe100b10 0xa0>;\n\n\t\t\tgphy0_led0_pins: gphy0-led0 {\n\t\t\t\tmux {\n\t\t\t\t\tlantiq,groups = \"gphy0 led0\";\n\t\t\t\t\tlantiq,function = \"gphy\";\n\t\t\t\t\tlantiq,open-drain = <0>;\n\t\t\t\t\tlantiq,pull = <2>;\n\t\t\t\t\tlantiq,output = <1>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tgphy0_led1_pins: gphy0-led1 {\n\t\t\t\tmux {\n\t\t\t\t\tlantiq,groups = \"gphy0 led1\";\n\t\t\t\t\tlantiq,function = \"gphy\";\n\t\t\t\t\tlantiq,open-drain = <0>;\n\t\t\t\t\tlantiq,pull = <2>;\n\t\t\t\t\tlantiq,output = <1>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tgphy0_led2_pins: gphy0-led2 {\n\t\t\t\tmux {\n\t\t\t\t\tlantiq,groups = \"gphy0 led2\";\n\t\t\t\t\tlantiq,function = \"gphy\";\n\t\t\t\t\tlantiq,open-drain = <0>;\n\t\t\t\t\tlantiq,pull = <2>;\n\t\t\t\t\tlantiq,output = <1>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tgphy1_led0_pins: gphy1-led0 {\n\t\t\t\tmux {\n\t\t\t\t\tlantiq,groups = \"gphy1 led0\";\n\t\t\t\t\tlantiq,function = \"gphy\";\n\t\t\t\t\tlantiq,open-drain = <0>;\n\t\t\t\t\tlantiq,pull = <2>;\n\t\t\t\t\tlantiq,output = <1>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tgphy1_led1_pins: gphy1-led1 {\n\t\t\t\tmux {\n\t\t\t\t\tlantiq,groups = \"gphy1 led1\";\n\t\t\t\t\tlantiq,function = \"gphy\";\n\t\t\t\t\tlantiq,open-drain = <0>;\n\t\t\t\t\tlantiq,pull = <2>;\n\t\t\t\t\tlantiq,output = <1>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tgphy1_led2_pins: gphy1-led2 {\n\t\t\t\tmux {\n\t\t\t\t\tlantiq,groups = \"gphy1 led2\";\n\t\t\t\t\tlantiq,function = \"gphy\";\n\t\t\t\t\tlantiq,open-drain = <0>;\n\t\t\t\t\tlantiq,pull = <2>;\n\t\t\t\t\tlantiq,output = <1>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tmdio_pins: mdio {\n\t\t\t\tmux {\n\t\t\t\t\tlantiq,groups = \"mdio\";\n\t\t\t\t\tlantiq,function = \"mdio\";\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tnand_pins: nand {\n\t\t\t\tmux-0 {\n\t\t\t\t\tlantiq,groups = \"nand cle\", \"nand ale\",\n\t\t\t\t\t\t\t\"nand rd\";\n\t\t\t\t\tlantiq,function = \"ebu\";\n\t\t\t\t\tlantiq,output = <1>;\n\t\t\t\t\tlantiq,open-drain = <0>;\n\t\t\t\t\tlantiq,pull = <0>;\n\t\t\t\t};\n\t\t\t\tmux-1 {\n\t\t\t\t\tlantiq,groups = \"nand rdy\";\n\t\t\t\t\tlantiq,function = \"ebu\";\n\t\t\t\t\tlantiq,output = <0>;\n\t\t\t\t\tlantiq,pull = <2>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tnand_cs1_pins: nand-cs1 {\n\t\t\t\tmux {\n\t\t\t\t\tlantiq,groups = \"nand cs1\";\n\t\t\t\t\tlantiq,function = \"ebu\";\n\t\t\t\t\tlantiq,open-drain = <0>;\n\t\t\t\t\tlantiq,pull = <0>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tpci_gnt1_pins: pci-gnt1 {\n\t\t\t\tmux {\n\t\t\t\t\tlantiq,groups = \"gnt1\";\n\t\t\t\t\tlantiq,function = \"pci\";\n\t\t\t\t\tlantiq,output = <1>;\n\t\t\t\t\tlantiq,open-drain = <0>;\n\t\t\t\t\tlantiq,pull = <0>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tpci_req1_pins: pci-req1 {\n\t\t\t\tmux {\n\t\t\t\t\tlantiq,groups = \"req1\";\n\t\t\t\t\tlantiq,function = \"pci\";\n\t\t\t\t\tlantiq,output = <0>;\n\t\t\t\t\tlantiq,open-drain = <1>;\n\t\t\t\t\tlantiq,pull = <2>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tspi_pins: spi {\n\t\t\t\tmux-0 {\n\t\t\t\t\tlantiq,groups = \"spi_di\";\n\t\t\t\t\tlantiq,function = \"spi\";\n\t\t\t\t};\n\t\t\t\tmux-1 {\n\t\t\t\t\tlantiq,groups = \"spi_do\", \"spi_clk\";\n\t\t\t\t\tlantiq,function = \"spi\";\n\t\t\t\t\tlantiq,output = <1>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tspi_cs4_pins: spi-cs4 {\n\t\t\t\tmux {\n\t\t\t\t\tlantiq,groups = \"spi_cs4\";\n\t\t\t\t\tlantiq,function = \"spi\";\n\t\t\t\t\tlantiq,output = <1>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tstp_pins: stp {\n\t\t\t\tmux {\n\t\t\t\t\tlantiq,groups = \"stp\";\n\t\t\t\t\tlantiq,function = \"stp\";\n\t\t\t\t\tlantiq,pull = <0>;\n\t\t\t\t\tlantiq,open-drain = <0>;\n\t\t\t\t\tlantiq,output = <1>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tstp: stp@e100bb0 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"lantiq,gpio-stp-xway\";\n\t\t\treg = <0xe100bb0 0x40>;\n\t\t\t#gpio-cells = <2>;\n\t\t\tgpio-controller;\n\n\t\t\tpinctrl-0 = <&stp_pins>;\n\t\t\tpinctrl-names = \"default\";\n\n\t\t\tlantiq,shadow = <0xffffff>;\n\t\t\tlantiq,groups = <0x7>;\n\t\t\tlantiq,dsl = <0x0>;\n\t\t\tlantiq,phy1 = <0x0>;\n\t\t\tlantiq,phy2 = <0x0>;\n\t\t};\n\n\t\tasc1: serial@e100c00 {\n\t\t\tcompatible = \"lantiq,asc\";\n\t\t\treg = <0xe100c00 0x400>;\n\t\t\tinterrupt-parent = <&icu0>;\n\t\t\tinterrupts = <112 113 114>;\n\t\t};\n\n\t\tdeu@e103100 {\n\t\t\tcompatible = \"lantiq,deu-xrx200\";\n\t\t\treg = <0xe103100 0xf00>;\n\t\t};\n\n\t\tdma0: dma@e104100 {\n\t\t\tcompatible = \"lantiq,dma-xway\";\n\t\t\treg = <0xe104100 0x800>;\n\t\t};\n\n\t\tebu0: ebu@e105300 {\n\t\t\tcompatible = \"lantiq,ebu-xway\";\n\t\t\treg = <0xe105300 0x100>;\n\t\t};\n\n\t\tusb0: usb@e101000 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"lantiq,xrx200-usb\";\n\t\t\treg = <0xe101000 0x1000\n\t\t\t\t0xe120000 0x3f000>;\n\t\t\tinterrupt-parent = <&icu0>;\n\t\t\tinterrupts = <62 91>;\n\t\t\tdr_mode = \"host\";\n\t\t\tphys = <&usb_phy0>;\n\t\t\tphy-names = \"usb2-phy\";\n\n\t\t\tehci_port1: port@1 {\n\t\t\t\treg = <1>;\n\t\t\t\t#trigger-source-cells = <0>;\n\t\t\t};\n\t\t};\n\n\t\tusb1: usb@e106000 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"lantiq,xrx200-usb\";\n\t\t\treg = <0xe106000 0x1000>;\n\t\t\tinterrupt-parent = <&icu0>;\n\t\t\tinterrupts = <91>;\n\t\t\tdr_mode = \"host\";\n\t\t\tphys = <&usb_phy1>;\n\t\t\tphy-names = \"usb2-phy\";\n\n\t\t\tehci_port2: port@1 {\n\t\t\t\treg = <1>;\n\t\t\t\t#trigger-source-cells = <0>;\n\t\t\t};\n\t\t};\n\n\t\tgswip: switch@e108000 {\n\t\t\tcompatible = \"lantiq,xrx200-gswip\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = < 0xe108000 0x3000 /* switch */\n\t\t\t\t0xe10b100 0x70   /* mdio */\n\t\t\t\t0xe10b1d8 0x30   /* mii */\n\t\t\t\t>;\n\n\t\t\tdsa,member = <0 0>;\n\n\t\t\tgswip_ports: ports {\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\n\t\t\t\tport@6 {\n\t\t\t\t\treg = <0x6>;\n\t\t\t\t\tlabel = \"cpu\";\n\t\t\t\t\tethernet = <&eth0>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tgswip_mdio: mdio {\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\t\t\t\tcompatible = \"lantiq,xrx200-mdio\";\n\t\t\t};\n\n\t\t\tgphy-fw {\n\t\t\t\tcompatible = \"lantiq,xrx200-gphy-fw\", \"lantiq,gphy-fw\";\n\t\t\t\tlantiq,rcu = <&rcu0>;\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\n\t\t\t\tgphy0: gphy@20 {\n\t\t\t\t\treg = <0x20>;\n\n\t\t\t\t\tresets = <&reset0 31 30>;\n\t\t\t\t\treset-names = \"gphy\";\n\t\t\t\t};\n\n\t\t\t\tgphy1: gphy@68 {\n\t\t\t\t\treg = <0x68>;\n\n\t\t\t\t\tresets = <&reset0 29 28>;\n\t\t\t\t\treset-names = \"gphy\";\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\teth0: eth@e10b308 {\n\t\t\tcompatible = \"lantiq,xrx200-net\";\n\t\t\treg = <0xe10b308 0x30>; /* pmac */\n\t\t\tinterrupt-parent = <&icu0>;\n\t\t\tinterrupts = <73>, <72>;\n\t\t\tinterrupt-names = \"tx\", \"rx\";\n\t\t\tresets = <&reset0 21 16>, <&reset0 8 8>, <&reset0 3 3>;\n\t\t\treset-names = \"switch\", \"ppe\", \"ppe_dsp\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\n\t\t\tfixed-link {\n\t\t\t\tspeed = <1000>;\n\t\t\t\tfull-duplex;\n\t\t\t};\n\t\t};\n\n\t\tmei@e116000 {\n\t\t\tcompatible = \"lantiq,mei-xrx200\";\n\t\t\treg = <0xe116000 0x9c>;\n\t\t\tinterrupt-parent = <&icu0>;\n\t\t\tinterrupts = <63>;\n\t\t};\n\n\t\tppe@e234000 {\n\t\t\tcompatible = \"lantiq,ppe-xrx200\";\n\t\t\treg = <0xe234000 0x3ffd>;\n\t\t\tinterrupt-parent = <&icu0>;\n\t\t\tinterrupts = <96>;\n\t\t\tresets = <&reset0 3 3>, <&reset0 11 11>, <&reset0 23 23>;\n\t\t\treset-names = \"dsp\", \"dfe\", \"tc\";\n\t\t};\n\n\t\tpcie0: pcie@d900000 {\n\t\t\tcompatible = \"lantiq,pcie-xrx200\";\n\n\t\t\t#interrupt-cells = <1>;\n\t\t\t#size-cells = <2>;\n\t\t\t#address-cells = <3>;\n\n\t\t\treg = <0xd900000 0x1000>;\n\n\t\t\tinterrupt-parent = <&icu0>;\n\t\t\tinterrupts = <161 144>;\n\n\t\t\tphys = <&pcie0_phy LANTIQ_PCIE_PHY_MODE_36MHZ>;\n\t\t\tphy-names = \"pcie\";\n\n\t\t\tresets = <&reset0 22 22>;\n\n\t\t\tlantiq,rcu = <&rcu0>;\n\n\t\t\tdevice_type = \"pci\";\n\n\t\t\tgpio-reset = <&gpio 38 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tpci0: pci@e105400 {\n\t\t\tstatus = \"disabled\";\n\n\t\t\t#address-cells = <3>;\n\t\t\t#size-cells = <2>;\n\t\t\t#interrupt-cells = <1>;\n\t\t\tcompatible = \"lantiq,pci-xway\";\n\t\t\tbus-range = <0x0 0x0>;\n\t\t\tranges = <0x2000000 0 0x8000000 0x8000000 0 0x2000000   /* pci memory */\n\t\t\t\t0x1000000 0 0x00000000 0xae00000 0 0x200000>; /* io space */\n\t\t\treg = <0x7000000 0x8000         /* config space */\n\t\t\t\t0xe105400 0x400>;       /* pci bridge */\n\t\t\tlantiq,bus-clock = <33333333>;\n\t\t\tinterrupt-map-mask = <0xf800 0x0 0x0 0x7>;\n\t\t\tinterrupt-map = <0x7000 0 0 1 &icu0 30 1>; /* slot 14, irq 30 */\n\t\t\treq-mask = <0x1>; /* GNT1 */\n\n\t\t\tdevice_type = \"pci\";\n\t\t};\n\t};\n\n\tvdsl {\n\t\tcompatible = \"lantiq,vdsl-vrx200\";\n\t};\n};\n"
  },
  {
    "path": "target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_alphanetworks_asl56026.dts",
    "content": "#include \"vr9.dtsi\"\n\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/mips/lantiq_rcu_gphy.h>\n\n/ {\n\tcompatible = \"alphanetworks,asl56026\", \"lantiq,xway\", \"lantiq,vr9\";\n\tmodel = \"BT OpenReach VDSL Modem\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyLTQ0,115200\";\n\t};\n\n\taliases {\n\t\tled-boot = &power_green;\n\t\tled-failsafe = &power_red;\n\t\tled-running = &power_green;\n\t\tled-upgrade = &power_green;\n\n\t\tled-dsl = &dsl;\n\t};\n\n\tmemory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x0 0x2000000>;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <100>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 40 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tdsl: dsl {\n\t\t\tlabel = \"green:dsl\";\n\t\t\tgpios = <&gpio 6 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\t/* power-* is a bicolour led */\n\t\tpower_green: power_green {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"keep\";\n\t\t};\n\n\t\tpower_red: power_red {\n\t\t\tlabel = \"red:power\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n\n\tgpio_export {\n\t\tcompatible = \"gpio-export\";\n\t\t#size-cells = <0>;\n\n\t\tpower_led_blink {\n\t\t\tgpio-export,name = \"power_led_blink\";\n\t\t\tgpio-export,output = <0>;\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&gphy0 {\n\tlantiq,gphy-mode = <GPHY_MODE_FE>;\n};\n\n&gphy1 {\n\tlantiq,gphy-mode = <GPHY_MODE_FE>;\n};\n\n&gswip_mdio {\n\tphy11: ethernet-phy@11 {\n\t\treg = <0x11>;\n\t};\n\n\tphy14: ethernet-phy@14 {\n\t\treg = <0x14>;\n\t};\n};\n\n&gswip_ports {\n\tport@2 {\n\t\treg = <2>;\n\t\tlabel = \"lan1\";\n\t\tphy-mode = \"internal\";\n\t\tphy-handle = <&phy11>;\n\t};\n\n\tport@3 {\n\t\treg = <3>;\n\t\tlabel = \"lan2\";\n\t\tphy-mode = \"internal\";\n\t\tphy-handle = <&phy14>;\n\t};\n};\n\n&localbus {\n\tflash@0 {\n\t\tcompatible = \"lantiq,nor\";\n\t\tbank-width = <2>;\n\t\treg = <0 0x0 0x0800000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"uboot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x40000 0x750000>;\n\t\t\t};\n\n\t\t\tpartition@790000 {\n\t\t\t\tlabel = \"ddrconfig\";\n\t\t\t\treg = <0x790000 0x70000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_arcadyan_arv7519rw22.dts",
    "content": "#include \"vr9.dtsi\"\n\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/mips/lantiq_rcu_gphy.h>\n\n/ {\n\tcompatible = \"arcadyan,arv7519rw22\", \"lantiq,xway\", \"lantiq,vr9\";\n\tmodel = \"Orange Livebox 2.1\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyLTQ0,115200\";\n\t};\n\n\taliases {\n\t\tled-boot = &power_green;\n\t\tled-failsafe = &power_green;\n\t\tled-running = &power_green;\n\t\tled-upgrade = &power_green;\n\n\t\tled-dsl = &internet_green;\n\t};\n\n\tmemory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x0 0x8000000>;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <100>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 6 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t\trfkill {\n\t\t\tlabel = \"rfkill\";\n\t\t\tgpios = <&gpio 33 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RFKILL>;\n\t\t};\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio 37 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tlan_green {\n\t\t\tlabel = \"green:lan\";\n\t\t\tgpios = <&gpio 2 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tinternet_red {\n\t\t\tlabel = \"red:internet\";\n\t\t\tgpios = <&gpio 10 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tpower_green: power_green {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"keep\";\n\t\t};\n\t\talarm_blue {\n\t\t\tlabel = \"blue:alarm\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tinternet_orange {\n\t\t\tlabel = \"orange:internet\";\n\t\t\tgpios = <&gpio 19 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tinternet_green: internet_green {\n\t\t\tlabel = \"green:internet\";\n\t\t\tgpios = <&gpio 28 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tvoice_green {\n\t\t\tlabel = \"green:voice\";\n\t\t\tgpios = <&gpio 29 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tusb_vbus: regulator-usb-vbus {\n\t\tcompatible = \"regulator-fixed\";\n\n\t\tregulator-name = \"USB_VBUS\";\n\n\t\tregulator-min-microvolt = <5000000>;\n\t\tregulator-max-microvolt = <5000000>;\n\n\t\tgpio = <&gpio 32 GPIO_ACTIVE_HIGH>;\n\t\tenable-active-high;\n\t};\n};\n\n&eth0 {\n\tnvmem-cells = <&macaddr_boardconfig_16>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&gphy0 {\n\tlantiq,gphy-mode = <GPHY_MODE_FE>;\n};\n\n&gphy1 {\n\tlantiq,gphy-mode = <GPHY_MODE_FE>;\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&state_default>;\n\n\tstate_default: pinmux {\n\t\tpcie-rst {\n\t\t\tlantiq,pins = \"io21\";\n\t\t\tlantiq,pull = <0>;\n\t\t\tlantiq,output = <1>;\n\t\t};\n\t};\n};\n\n&gswip {\n\tpinctrl-0 = <&mdio_pins>;\n\tpinctrl-names = \"default\";\n};\n\n&gswip_mdio {\n\tphy0: ethernet-phy@0 {\n\t\treg = <0x0>;\n\t};\n\tphy11: ethernet-phy@11 {\n\t\treg = <0x11>;\n\t};\n\tphy12: ethernet-phy@12 {\n\t\treg = <0x12>;\n\t};\n\tphy13: ethernet-phy@13 {\n\t\treg = <0x13>;\n\t};\n\tphy14: ethernet-phy@14 {\n\t\treg = <0x14>;\n\t};\n};\n\n&gswip_ports {\n\tport@0 {\n\t\treg = <0>;\n\t\tlabel = \"lan5\";\n\t\tphy-mode = \"rgmii\";\n\t\tphy-handle = <&phy0>;\n\t};\n\tport@2 {\n\t\treg = <2>;\n\t\tlabel = \"lan3\";\n\t\tphy-mode = \"internal\";\n\t\tphy-handle = <&phy11>;\n\t};\n\tport@3 {\n\t\treg = <3>;\n\t\tlabel = \"lan4\";\n\t\tphy-mode = \"internal\";\n\t\tphy-handle = <&phy12>;\n\t};\n\tport@4 {\n\t\treg = <4>;\n\t\tlabel = \"lan1\";\n\t\tphy-mode = \"internal\";\n\t\tphy-handle = <&phy13>;\n\t};\n\tport@5 {\n\t\treg = <5>;\n\t\tlabel = \"lan2\";\n\t\tphy-mode = \"internal\";\n\t\tphy-handle = <&phy14>;\n\t};\n};\n\n&localbus {\n\tflash@0 {\n\t\tcompatible = \"lantiq,nor\";\n\t\tbank-width = <2>;\n\t\treg = <0 0x0 0x2000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"uboot\";\n\t\t\t\treg = <0x0 0x60000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@60000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x60000 0x20000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@80000 {\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x80000 0x1f00000>;\n\t\t\t};\n\n\t\t\tboardconfig: partition@1f80000 {\n\t\t\t\tlabel = \"boardconfig\";\n\t\t\t\treg = <0x1f80000 0x80000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pcie0 {\n\tstatus = \"okay\";\n\tgpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>;\n};\n\n&usb_phy0 {\n\tstatus = \"okay\";\n};\n\n&usb_phy1 {\n\tstatus = \"okay\";\n};\n\n&usb0 {\n\tstatus = \"okay\";\n\tvbus-supply = <&usb_vbus>;\n};\n\n&usb1 {\n\tstatus = \"okay\";\n\tvbus-supply = <&usb_vbus>;\n};\n\n&boardconfig {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_boardconfig_16: macaddr@16 {\n\t\treg = <0x16 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_arcadyan_vg3503j.dts",
    "content": "#include \"vr9.dtsi\"\n\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/mips/lantiq_rcu_gphy.h>\n\n/ {\n\tcompatible = \"arcadyan,vg3503j\", \"lantiq,xway\", \"lantiq,vr9\";\n\tmodel = \"BT OpenReach VDSL Modem\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyLTQ0,115200\";\n\t};\n\n\taliases {\n\t\tled-boot = &power_green;\n\t\tled-failsafe = &power_red;\n\t\tled-running = &power_green;\n\t\tled-upgrade = &power_green;\n\n\t\tled-dsl = &dsl;\n\t};\n\n\tmemory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x0 0x2000000>;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <100>;\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 6 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tpower_red: power2 {\n\t\t\tlabel = \"red:power\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tdsl: dsl {\n\t\t\tlabel = \"green:dsl\";\n\t\t\tgpios = <&gpio 19 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tpower_green: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 28 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"keep\";\n\t\t};\n\t};\n};\n\n&gphy0 {\n\tlantiq,gphy-mode = <GPHY_MODE_GE>;\n};\n\n&gphy1 {\n\tlantiq,gphy-mode = <GPHY_MODE_GE>;\n};\n\n&gswip {\n\tpinctrl-0 = <&gphy0_led0_pins>, <&gphy0_led1_pins>, <&gphy0_led2_pins>,\n\t\t    <&gphy1_led0_pins>, <&gphy1_led1_pins>, <&gphy1_led2_pins>;\n\tpinctrl-names = \"default\";\n};\n\n&gswip_mdio {\n\tphy11: ethernet-phy@11 {\n\t\treg = <0x11>;\n\t\tlantiq,led1h = <0x70>;\n\t\tlantiq,led1l = <0x00>;\n\t\tlantiq,led2h = <0x00>;\n\t\tlantiq,led2l = <0x03>;\n\t};\n\tphy13: ethernet-phy@13 {\n\t\treg = <0x13>;\n\t\tlantiq,led1h = <0x70>;\n\t\tlantiq,led1l = <0x00>;\n\t\tlantiq,led2h = <0x00>;\n\t\tlantiq,led2l = <0x03>;\n\t};\n};\n\n&gswip_ports {\n\tport@2 {\n\t\treg = <2>;\n\t\tlabel = \"lan2\";\n\t\tphy-mode = \"internal\";\n\t\tphy-handle = <&phy11>;\n\t};\n\tport@4 {\n\t\treg = <4>;\n\t\tlabel = \"lan1\";\n\t\tphy-mode = \"internal\";\n\t\tphy-handle = <&phy13>;\n\t};\n};\n\n&localbus {\n\tflash@0 {\n\t\tcompatible = \"lantiq,nor\";\n\t\tbank-width = <2>;\n\t\treg = <0 0x0 0x2000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"uboot\";\n\t\t\t\treg = <0x00000 0x20000>;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x20000 0x7d0000>;\n\t\t\t};\n\n\t\t\tpartition@7f0000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x7f0000 0x10000>;\n\t\t\t};\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_arcadyan_vgv7510kw22-brn.dts",
    "content": "#include \"vr9_arcadyan_vgv7510kw22.dtsi\"\n\n/ {\n\tcompatible = \"arcadyan,vgv7510kw22-brn\", \"arcadyan,vgv7510kw22\", \"lantiq,xway\", \"lantiq,vr9\";\n\tmodel = \"o2 Box 6431\";\n\n\tsram@1f000000 {\n\t\tcgu@103000 {\n\t\t\tlantiq,phy-clk-src = <0x2>;\n\t\t};\n\t};\n};\n\n&localbus {\n\tflash@0 {\n\t\tpartitions {\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"Boot\";\n\t\t\t\treg = <0x00000 0x40000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"Configuration\";\n\t\t\t\treg = <0x40000 0x40000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@80000 {\n\t\t\t\tlabel = \"Certificate\";\n\t\t\t\treg = <0x80000 0x20000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@a0000 {\n\t\t\t\tlabel = \"Special_Area\";\n\t\t\t\treg = <0xa0000 0x20000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@c0000 {\n\t\t\t\tcompatible = \"brnboot,root-selector\";\n\t\t\t\tlabel = \"Primary_Setting\";\n\t\t\t\treg = <0xc0000 0x20000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@e0000 {\n\t\t\t\tlabel = \"Code_Image_0\";\n\t\t\t\treg = <0xe0000 0x780000>;\n\t\t\t\tbrnboot,root-id = <0x00>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@860000 {\n\t\t\t\tlabel = \"Code_Image_1\";\n\t\t\t\treg = <0x860000 0x780000>;\n\t\t\t\tbrnboot,root-id = <0x01>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_arcadyan_vgv7510kw22-nor.dts",
    "content": "#include \"vr9_arcadyan_vgv7510kw22.dtsi\"\n\n/ {\n\tcompatible = \"arcadyan,vgv7510kw22-nor\", \"arcadyan,vgv7510kw22\", \"lantiq,xway\", \"lantiq,vr9\";\n\tmodel = \"o2 Box 6431\";\n};\n\n&localbus {\n\tflash@0 {\n\t\tpartitions {\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"uboot\";\n\t\t\t\treg = <0x0 0x60000>; /* 384 KiB */\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@60000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x60000 0x20000>; /* 128 KiB */\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@80000 {\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x80000 0xf60000>; /* 15744 KiB */\n\t\t\t};\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_arcadyan_vgv7510kw22.dtsi",
    "content": "#include \"vr9.dtsi\"\n\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/mips/lantiq_rcu_gphy.h>\n\n/ {\n\tcompatible = \"arcadyan,vgv7510kw22\", \"lantiq,xway\", \"lantiq,vr9\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyLTQ0,115200 mem=62M vpe1_load_addr=0x83e00000 vpe1_mem=2M maxvpes=1 maxtcs=1 nosmp\";\n\t};\n\n\taliases {\n\t\tled-boot = &power_green;\n\t\tled-failsafe = &power_red;\n\t\tled-running = &power_green;\n\t\tled-upgrade = &power_green;\n\n\t\tled-dsl = &dsl;\n\t\tled-internet = &internet_green;\n\t\tled-wifi = &wifi;\n\t};\n\n\tmemory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x0 0x4000000>;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <100>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 6 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio 9 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tdsl: dsl {\n\t\t\tlabel = \"green:dsl\";\n\t\t\tgpios = <&gpio 2 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tinternet_red {\n\t\t\tlabel = \"red:internet\";\n\t\t\tgpios = <&gpio 10 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tinfo_red {\n\t\t\tlabel = \"red:info\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tpower_green: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"keep\";\n\t\t};\n\n\t\tinfo_green {\n\t\t\tlabel = \"green:info\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tinternet_green: internet_green {\n\t\t\tlabel = \"green:internet\";\n\t\t\tgpios = <&gpio 19 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twifi: wifi {\n\t\t\tlabel = \"green:wlan\";\n\t\t\tgpios = <&gpio 20 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tpower_red: power2 {\n\t\t\tlabel = \"red:power\";\n\t\t\tgpios = <&gpio 28 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tphone {\n\t\t\tlabel = \"green:telefon\";\n\t\t\tgpios = <&gpio 29 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tusb_vbus: regulator-usb-vbus {\n\t\tcompatible = \"regulator-fixed\";\n\n\t\tregulator-name = \"USB_VBUS\";\n\n\t\tregulator-min-microvolt = <5000000>;\n\t\tregulator-max-microvolt = <5000000>;\n\n\t\tgpio = <&gpio 47 GPIO_ACTIVE_HIGH>;\n\t\tenable-active-high;\n\t};\n};\n\n&eth0 {\n\tnvmem-cells = <&macaddr_boardconfig_16>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&gphy0 {\n\tlantiq,gphy-mode = <GPHY_MODE_FE>;\n};\n\n&gphy1 {\n\tlantiq,gphy-mode = <GPHY_MODE_FE>;\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&state_default>, <&gphy0_led1_pins>;\n\n\tstate_default: pinmux {\n\t\tpci-rst {\n\t\t\tlantiq,pins = \"io21\";\n\t\t\tlantiq,open-drain = <0>;\n\t\t\tlantiq,pull = <0>;\n\t\t\tlantiq,output = <1>;\n\t\t};\n\t};\n};\n\n&gswip {\n\tpinctrl-0 = <&mdio_pins>,\n\t\t    <&gphy0_led0_pins>,\n\t\t    <&gphy1_led0_pins>, <&gphy1_led1_pins>;\n\tpinctrl-names = \"default\";\n};\n\n&gswip_mdio {\n\tphy1: ethernet-phy@1 {\n\t\treg = <0x1>;\n\t};\n\tphy11: ethernet-phy@11 {\n\t\treg = <0x11>;\n\t};\n\tphy12: ethernet-phy@12 {\n\t\treg = <0x12>;\n\t};\n\tphy13: ethernet-phy@13 {\n\t\treg = <0x13>;\n\t};\n\tphy14: ethernet-phy@14 {\n\t\treg = <0x14>;\n\t};\n};\n\n&gswip_ports {\n\tport@0 {\n\t\treg = <0>;\n\t\tlabel = \"wan\";\n\t\tphy-mode = \"mii\";\n\t\tphy-handle = <&phy1>;\n\t};\n\tport@2 {\n\t\treg = <2>;\n\t\tlabel = \"lan2\";\n\t\tphy-mode = \"internal\";\n\t\tphy-handle = <&phy11>;\n\t};\n\tport@3 {\n\t\treg = <3>;\n\t\tlabel = \"lan1\";\n\t\tphy-mode = \"internal\";\n\t\tphy-handle = <&phy12>;\n\t};\n\tport@4 {\n\t\treg = <4>;\n\t\tlabel = \"lan4\";\n\t\tphy-mode = \"internal\";\n\t\tphy-handle = <&phy13>;\n\t};\n\tport@5 {\n\t\treg = <5>;\n\t\tlabel = \"lan3\";\n\t\tphy-mode = \"internal\";\n\t\tphy-handle = <&phy14>;\n\t};\n};\n\n&localbus {\n\tflash@0 {\n\t\tcompatible = \"lantiq,nor\";\n\t\tbank-width = <2>;\n\t\treg = <0 0x0 0x1000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tboardconfig: partition@fe0000 {\n\t\t\t\tlabel = \"board_config\";\n\t\t\t\treg = <0xfe0000 0x20000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pci0 {\n\tstatus = \"okay\";\n\tgpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>;\n\n\twifi@1814,3592 {\n\t\tcompatible = \"pci1814,3592\";\n\t\treg = <0x7000 0 0 0 0>;\n\t\tralink,mtd-eeprom = <&boardconfig 0x410>;\n\t\tralink,mtd-eeprom-swap;\n\t\tnvmem-cells = <&macaddr_boardconfig_16>;\n\t\tnvmem-cell-names = \"mac-address\";\n\t\tmac-address-increment = <1>;\n\t};\n};\n\n&pcie0 {\n\tstatus = \"disabled\";\n};\n\n&usb_phy0 {\n\tstatus = \"okay\";\n};\n\n&usb0 {\n\tstatus = \"okay\";\n\tvbus-supply = <&usb_vbus>;\n};\n\n&vmmc {\n\tstatus = \"okay\";\n\tgpios = <&gpio 30 GPIO_ACTIVE_HIGH  //fxs relay\n\t\t\t &gpio 31 GPIO_ACTIVE_HIGH  //still unknown\n\t\t\t &gpio 3  GPIO_ACTIVE_HIGH>; //reset_slic?\n};\n\n&boardconfig {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_boardconfig_16: macaddr@16 {\n\t\treg = <0x16 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_arcadyan_vgv7519-brn.dts",
    "content": "#include \"vr9_arcadyan_vgv7519.dtsi\"\n\n/ {\n\tcompatible = \"arcadyan,vgv7519-brn\", \"arcadyan,vgv7519\", \"lantiq,xway\", \"lantiq,vr9\";\n\tmodel = \"KPN Experiabox V8\";\n};\n\n&localbus {\n\tflash@0 {\n\t\tpartitions {\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"Boot\";\n\t\t\t\treg = <0x00000 0x40000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tlabel = \"Certificate\";\n\t\t\t\treg = <0x50000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@60000 {\n\t\t\t\tlabel = \"Special_Area\";\n\t\t\t\treg = <0x60000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@70000 {\n\t\t\t\tlabel = \" Reserve_0\";\n\t\t\t\treg = <0x70000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@80000 {\n\t\t\t\tlabel = \"Code_Image_0\";\n\t\t\t\treg = <0x80000 0x780000>;\n\t\t\t\tbrnboot,root-id = <0x00>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@4000000 {\n\t\t\t\tcompatible = \"brnboot,root-selector\";\n\t\t\t\tlabel = \"Primary_Setting\";\n\t\t\t\treg = <0x4000000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@4010000 {\n\t\t\t\tlabel = \"Configuration\";\n\t\t\t\treg = <0x4010000 0x60000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@4070000 {\n\t\t\t\tlabel = \" Reserve_1\";\n\t\t\t\treg = <0x4070000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@4080000 {\n\t\t\t\tlabel = \"Code_Image_1\";\n\t\t\t\treg = <0x4080000 0x780000>;\n\t\t\t\tbrnboot,root-id = <0x01>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_arcadyan_vgv7519-nor.dts",
    "content": "#include \"vr9_arcadyan_vgv7519.dtsi\"\n\n/ {\n\tcompatible = \"arcadyan,vgv7519-nor\", \"arcadyan,vgv7519\", \"lantiq,xway\", \"lantiq,vr9\";\n\tmodel = \"KPN Experiabox V8\";\n};\n\n&localbus {\n\tflash@0 {\n\t\tpartitions {\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"uboot\";\n\t\t\t\treg = <0x00000 0x40000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@60000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x60000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@80000 {\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x80000 0xf80000>;\n\t\t\t};\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_arcadyan_vgv7519.dtsi",
    "content": "#include \"vr9.dtsi\"\n\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/mips/lantiq_rcu_gphy.h>\n\n/ {\n\tcompatible = \"arcadyan,vgv7519\", \"lantiq,xway\", \"lantiq,vr9\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyLTQ0,115200 mem=62M vpe1_load_addr=0x83e00000 vpe1_mem=2M maxvpes=1 maxtcs=1 nosmp\";\n\t};\n\n\taliases {\n\t\tled-boot = &power_green;\n\t\tled-failsafe = &power_red;\n\t\tled-running = &power_green;\n\t\tled-upgrade = &power_green;\n\n\t\tled-dsl = &broadband_green;\n\t\tled-internet = &internet_green;\n\t\tled-wifi = &wireless_green;\n\t};\n\n\tmemory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x0 0x4000000>;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <100>;\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 9 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t\teco {\n\t\t\tlabel = \"eco\";\n\t\t\tgpios = <&gpio 41 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_0>;\n\t\t};\n\t\trfkill {\n\t\t\tlabel = \"rfkill\";\n\t\t\tgpios = <&gpio 45 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RFKILL>;\n\t\t};\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio 10 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\teco {\n\t\t\tlabel = \"blue:eco\";\n\t\t\tgpios = <&stp 2 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\twps_red {\n\t\t\tlabel = \"red:wps\";\n\t\t\tgpios = <&stp 3 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\twps_green {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&stp 4 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tupgrade {\n\t\t\tlabel = \"blue:upgrade\";\n\t\t\tgpios = <&stp 5 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\ttv {\n\t\t\tlabel = \"green:tv\";\n\t\t\tgpios = <&stp 6 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tinternet_green: internet_green {\n\t\t\tlabel = \"green:internet\";\n\t\t\tgpios = <&stp 7 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tinternet_red {\n\t\t\tlabel = \"red:internet\";\n\t\t\tgpios = <&stp 8 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tbroadband_red {\n\t\t\tlabel = \"red:broadband\";\n\t\t\tgpios = <&stp 9 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tbroadband_green: broadband_green {\n\t\t\tlabel = \"green:broadband\";\n\t\t\tgpios = <&stp 10 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tvoice {\n\t\t\tlabel = \"green:voice\";\n\t\t\tgpios = <&stp 11 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\twireless_red {\n\t\t\tlabel = \"red:wireless\";\n\t\t\tgpios = <&stp 12 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\twireless_green: wireless_green {\n\t\t\tlabel = \"green:wireless\";\n\t\t\tgpios = <&stp 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tpower_green: power2 {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&stp 14 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"keep\";\n\t\t};\n\t\tpower_red: power {\n\t\t\tlabel = \"red:power\";\n\t\t\tgpios = <&stp 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tusb_vbus: regulator-usb-vbus {\n\t\tcompatible = \"regulator-fixed\";\n\n\t\tregulator-name = \"USB_VBUS\";\n\n\t\tregulator-min-microvolt = <5000000>;\n\t\tregulator-max-microvolt = <5000000>;\n\n\t\tgpio = <&gpio 32 GPIO_ACTIVE_HIGH>;\n\t\tenable-active-high;\n\t};\n};\n\n&eth0 {\n\tnvmem-cells = <&macaddr_boardconfig_16>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <1>;\n};\n\n&gphy0 {\n\tlantiq,gphy-mode = <GPHY_MODE_GE>;\n};\n\n&gphy1 {\n\tlantiq,gphy-mode = <GPHY_MODE_GE>;\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&state_default>;\n\n\tstate_default: pinmux {\n\t\tpci-rst {\n\t\t\tlantiq,pins = \"io21\";\n\t\t\tlantiq,open-drain = <0>;\n\t\t\tlantiq,pull = <0>;\n\t\t\tlantiq,output = <1>;\n\t\t};\n\t};\n};\n\n&gswip {\n\tpinctrl-0 = <&mdio_pins>, <&gphy0_led1_pins>, <&gphy1_led0_pins>;\n\tpinctrl-names = \"default\";\n};\n\n&gswip_mdio {\n\tphy0: ethernet-phy@0 {\n\t\treg = <0x0>;\n\t};\n\tphy1: ethernet-phy@1 {\n\t\treg = <0x1>;\n\t};\n\tphy5: ethernet-phy@5 {\n\t\treg = <0x5>;\n\t};\n\tphy11: ethernet-phy@11 {\n\t\treg = <0x11>;\n\t};\n\tphy13: ethernet-phy@13 {\n\t\treg = <0x13>;\n\t};\n};\n\n&gswip_ports {\n\tport@0 {\n\t\treg = <0>;\n\t\tlabel = \"lan4\";\n\t\tphy-mode = \"rgmii\";\n\t\tphy-handle = <&phy0>;\n\t};\n\tport@1 {\n\t\treg = <1>;\n\t\tlabel = \"lan3\";\n\t\tphy-mode = \"rgmii\";\n\t\tphy-handle = <&phy1>;\n\t};\n\tport@2 {\n\t\treg = <2>;\n\t\tlabel = \"lan2\";\n\t\tphy-mode = \"internal\";\n\t\tphy-handle = <&phy11>;\n\t};\n\tport@4 {\n\t\treg = <4>;\n\t\tlabel = \"lan1\";\n\t\tphy-mode = \"internal\";\n\t\tphy-handle = <&phy13>;\n\t};\n\tport@5 {\n\t\treg = <5>;\n\t\tlabel = \"wan\";\n\t\tphy-mode = \"rgmii\";\n\t\tphy-handle = <&phy5>;\n\t};\n};\n\n&localbus {\n\tflash@0 {\n\t\tcompatible = \"lantiq,nor\";\n\t\tbank-width = <2>;\n\t\treg = <0 0x0 0x800000>, <1 0x800000 0x800000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tboardconfig: partition@40000 {\n\t\t\t\tlabel = \"board_config\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pci0 {\n\tstatus = \"okay\";\n\tgpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>;\n\n\twifi@1814,3091 {\n\t\tcompatible = \"pci1814,3091\";\n\t\treg = <0x7000 0 0 0 0>;\n\t\tralink,mtd-eeprom = <&boardconfig 0x410>;\n\t\tralink,mtd-eeprom-swap;\n\t\tnvmem-cells = <&macaddr_boardconfig_16>;\n\t\tnvmem-cell-names = \"mac-address\";\n\t\tmac-address-increment = <1>;\n\t};\n};\n\n&pcie0 {\n\tstatus = \"disabled\";\n};\n\n&stp {\n\tstatus = \"okay\";\n\tlantiq,shadow = <0xffff>;\n\tlantiq,groups = <0x3>;\n\t/* lantiq,rising; */\n};\n\n&usb_phy0 {\n\tstatus = \"okay\";\n};\n\n&usb_phy1 {\n\tstatus = \"okay\";\n};\n\n&usb0 {\n\tstatus = \"okay\";\n\tvbus-supply = <&usb_vbus>;\n};\n\n&usb1 {\n\tstatus = \"okay\";\n\tvbus-supply = <&usb_vbus>;\n};\n\n&vmmc {\n\tstatus = \"okay\";\n\tgpios = <&gpio 30 GPIO_ACTIVE_HIGH  //fxs relay\n\t\t &gpio 31 GPIO_ACTIVE_HIGH  //still unknown\n\t\t &gpio 3  GPIO_ACTIVE_HIGH>; //reset_slic?\n};\n\n&boardconfig {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_boardconfig_16: macaddr@16 {\n\t\treg = <0x16 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_avm_fritz3370-rev2-hynix.dts",
    "content": "#include \"vr9_avm_fritz3370-rev2.dtsi\"\n\n/ {\n\tcompatible = \"avm,fritz3370-rev2-hynix\", \"avm,fritz3370-rev2\", \"lantiq,xway\", \"lantiq,vr9\";\n\tmodel = \"AVM FRITZ!Box 3370 Rev. 2 (Hynix NAND)\";\n};\n\n&localbus {\n\tflash@1 {\n\t\tcompatible = \"lantiq,nand-xway\";\n\t\tbank-width = <2>;\n\t\treg = <1 0x0 0x2000000>;\n\n\t\tpinctrl-0 = <&nand_pins>, <&nand_cs1_pins>;\n\t\tpinctrl-names = \"default\";\n\n\t\tnand-use-soft-ecc-engine;\n\t\tnand-ecc-strength = <3>;\n\t\tnand-ecc-step-size = <256>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"kernel\";\n\t\t\t\treg = <0x0 0x400000>;\n\t\t\t};\n\n\t\t\tpartition@400000 {\n\t\t\t\tlabel = \"ubi\";\n\t\t\t\treg = <0x400000 0x7c00000>;\n\t\t\t};\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_avm_fritz3370-rev2-micron.dts",
    "content": "#include \"vr9_avm_fritz3370-rev2.dtsi\"\n\n/ {\n\tcompatible = \"avm,fritz3370-rev2-micron\", \"avm,fritz3370-rev2\", \"lantiq,xway\", \"lantiq,vr9\";\n\tmodel = \"AVM FRITZ!Box 3370 Rev. 2 (Micron NAND)\";\n};\n\n&localbus {\n\tflash1: flash@1 {\n\t\tcompatible = \"lantiq,nand-xway\";\n\t\tbank-width = <2>;\n\t\treg = <1 0x0 0x2000000>;\n\n\t\tpinctrl-0 = <&nand_pins>, <&nand_cs1_pins>;\n\t\tpinctrl-names = \"default\";\n\n\t\tnand-ecc-engine = <&flash1>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"kernel\";\n\t\t\t\treg = <0x0 0x400000>;\n\t\t\t};\n\n\t\t\tpartition@400000 {\n\t\t\t\tlabel = \"ubi\";\n\t\t\t\treg = <0x400000 0x7c00000>;\n\t\t\t};\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_avm_fritz3370-rev2.dtsi",
    "content": "#include \"vr9.dtsi\"\n\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/mips/lantiq_rcu_gphy.h>\n\n/ {\n\tcompatible = \"avm,fritz3370-rev2\", \"lantiq,xway\", \"lantiq,vr9\";\n\tmodel = \"AVM FRITZ!Box 3370 Rev. 2\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyLTQ0,115200\";\n\t};\n\n\taliases {\n\t\tled-boot = &power_green;\n\t\tled-failsafe = &power_red;\n\t\tled-running = &power_green;\n\t\tled-upgrade = &power_red;\n\n\t\tled-dsl = &dsl;\n\t\tled-internet = &info_green;\n\t\tled-wifi = &wifi;\n\t};\n\n\tmemory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x0 0x8000000>;\n\t};\n\n\tgpio-poweroff {\n\t\tcompatible = \"gpio-poweroff\";\n\t\tgpios = <&gpio 45 GPIO_ACTIVE_HIGH>;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <100>;\n\n\t\tpower {\n\t\t\tlabel = \"power\";\n\t\t\tgpios = <&gpio 1 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = <KEY_POWER>;\n\t\t};\n\n\t\twifi {\n\t\t\tlabel = \"wlan\";\n\t\t\tgpios = <&gpio 29 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RFKILL>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tpower_green: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 32 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"keep\";\n\t\t};\n\n\t\tpower_red: power2 {\n\t\t\tlabel = \"red:power\";\n\t\t\tgpios = <&gpio 33 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tinfo_red {\n\t\t\tlabel = \"red:info\";\n\t\t\tgpios = <&gpio 34 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twifi: wifi {\n\t\t\tlabel = \"green:wlan\";\n\t\t\tgpios = <&gpio 35 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tdsl: dsl {\n\t\t\tlabel = \"green:dsl\";\n\t\t\tgpios = <&gpio 36 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan {\n\t\t\tlabel = \"green:lan\";\n\t\t\tgpios = <&gpio 38 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tinfo_green: info_green {\n\t\t\tlabel = \"green:info\";\n\t\t\tgpios = <&gpio 47 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tusb0_vbus: regulator-usb0-vbus {\n\t\tcompatible = \"regulator-fixed\";\n\n\t\tregulator-name = \"USB0_VBUS\";\n\n\t\tregulator-min-microvolt = <5000000>;\n\t\tregulator-max-microvolt = <5000000>;\n\n\t\tgpio = <&gpio 14 GPIO_ACTIVE_HIGH>;\n\t\tenable-active-high;\n\t};\n\n\tusb1_vbus: regulator-usb1-vbus {\n\t\tcompatible = \"regulator-fixed\";\n\n\t\tregulator-name = \"USB1_VBUS\";\n\n\t\tregulator-min-microvolt = <5000000>;\n\t\tregulator-max-microvolt = <5000000>;\n\n\t\tgpio = <&gpio 5 GPIO_ACTIVE_HIGH>;\n\t\tenable-active-high;\n\t};\n};\n\n&gphy0 {\n\tlantiq,gphy-mode = <GPHY_MODE_GE>;\n};\n\n&gphy1 {\n\tlantiq,gphy-mode = <GPHY_MODE_GE>;\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&state_default>;\n\n\tstate_default: pinmux {\n\t\tphy-rst {\n\t\t\tlantiq,pins = \"io37\", \"io44\";\n\t\t\tlantiq,pull = <0>;\n\t\t\tlantiq,open-drain = <0>;\n\t\t\tlantiq,output = <1>;\n\t\t};\n\n\t\tpcie-rst {\n\t\t\tlantiq,pins = \"io21\";\n\t\t\tlantiq,pull = <0>;\n\t\t\tlantiq,output = <1>;\n\t\t};\n\t};\n};\n\n&gswip {\n\tpinctrl-0 = <&mdio_pins>;\n\tpinctrl-names = \"default\";\n};\n\n&gswip_mdio {\n\tphy0: ethernet-phy@0 {\n\t\treg = <0x0>;\n\t\tgpios = <&gpio 37 GPIO_ACTIVE_HIGH>;\n\t};\n\n\tphy1: ethernet-phy@1 {\n\t\treg = <0x1>;\n\t\tgpios = <&gpio 44 GPIO_ACTIVE_HIGH>;\n\t};\n\n\tphy11: ethernet-phy@11 {\n\t\treg = <0x11>;\n\t};\n\n\tphy13: ethernet-phy@13 {\n\t\treg = <0x13>;\n\t};\n};\n\n&gswip_ports {\n\tport@0 {\n\t\treg = <0>;\n\t\tlabel = \"lan3\";\n\t\tphy-mode = \"rgmii\";\n\t\tphy-handle = <&phy0>;\n\t};\n\n\tport@1 {\n\t\treg = <1>;\n\t\tlabel = \"lan4\";\n\t\tphy-mode = \"rgmii\";\n\t\tphy-handle = <&phy1>;\n\t};\n\n\tport@2 {\n\t\treg = <2>;\n\t\tlabel = \"lan2\";\n\t\tphy-mode = \"internal\";\n\t\tphy-handle = <&phy11>;\n\t};\n\n\tport@4 {\n\t\treg = <4>;\n\t\tlabel = \"lan1\";\n\t\tphy-mode = \"internal\";\n\t\tphy-handle = <&phy13>;\n\t};\n};\n\n&pcie0 {\n\tgpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>;\n\n\tpcie@0 {\n\t\treg = <0 0 0 0 0>;\n\t\t#interrupt-cells = <1>;\n\t\t#size-cells = <2>;\n\t\t#address-cells = <3>;\n\t\tdevice_type = \"pci\";\n\n\t\twifi@0,0 {\n\t\t\tcompatible = \"pci0,0\";\n\t\t\treg = <0 0 0 0 0>;\n\t\t\tqca,no-eeprom; /* load from ath9k-eeprom-pci-0000:01:00.0.bin */\n\t\t};\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@4 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <4>;\n\t\tspi-max-frequency = <1000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\turlader: partition@0 {\n\t\t\t\treg = <0x0 0x20000>;\n\t\t\t\tlabel = \"urlader\";\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\treg = <0x20000 0x10000>;\n\t\t\t\tlabel = \"tffs (1)\";\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tlabel = \"tffs (2)\";\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&usb_phy0 {\n\tstatus = \"okay\";\n};\n\n&usb_phy1 {\n\tstatus = \"okay\";\n};\n\n&usb0 {\n\tstatus = \"okay\";\n\tvbus-supply = <&usb0_vbus>;\n};\n\n&usb1 {\n\tstatus = \"okay\";\n\tvbus-supply = <&usb1_vbus>;\n};\n"
  },
  {
    "path": "target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_avm_fritz3390.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"vr9.dtsi\"\n\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/mips/lantiq_rcu_gphy.h>\n\n/ {\n\tcompatible = \"avm,fritz3390\", \"lantiq,xway\", \"lantiq,vr9\";\n\tmodel = \"AVM FRITZ!Box 3390\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyLTQ0,115200\";\n\t};\n\n\taliases {\n\t\tled-boot = &led_power_green;\n\t\tled-failsafe = &led_power_red;\n\t\tled-running = &led_power_green;\n\t\tled-upgrade = &led_power_red;\n\n\t\tled-dsl = &led_dsl;\n\t\tled-internet = &led_info;\n\t\tled-wifi = &led_wifi;\n\t};\n\n\tmemory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x0 0x8000000>;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <100>;\n\n\t\tpower {\n\t\t\tlabel = \"power\";\n\t\t\tgpios = <&gpio 1 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = <KEY_POWER>;\n\t\t};\n\n\t\twifi {\n\t\t\tlabel = \"wifi\";\n\t\t\tgpios = <&gpio 29 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = <KEY_RFKILL>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power_green: power_green {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 45 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"keep\";\n\t\t};\n\n\t\tled_power_red: power_red {\n\t\t\tlabel = \"red:power\";\n\t\t\tgpios = <&gpio 46 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_wifi: wifi {\n\t\t\tlabel = \"green:wifi\";\n\t\t\tgpios = <&gpio 36 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_dsl: dsl {\n\t\t\tlabel = \"green:dsl\";\n\t\t\tgpios = <&gpio 35 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_lan {\n\t\t\tlabel = \"green:lan\";\n\t\t\tgpios = <&gpio 47 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_info: info {\n\t\t\tlabel = \"green:info\";\n\t\t\tgpios = <&gpio 33 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tusb0_vbus: regulator-usb0-vbus {\n\t\tcompatible = \"regulator-fixed\";\n\n\t\tregulator-name = \"USB0_VBUS\";\n\n\t\tregulator-min-microvolt = <5000000>;\n\t\tregulator-max-microvolt = <5000000>;\n\n\t\tgpio = <&gpio 14 GPIO_ACTIVE_HIGH>;\n\t\tenable-active-high;\n\t};\n\n\tusb1_vbus: regulator-usb1-vbus {\n\t\tcompatible = \"regulator-fixed\";\n\n\t\tregulator-name = \"USB1_VBUS\";\n\n\t\tregulator-min-microvolt = <5000000>;\n\t\tregulator-max-microvolt = <5000000>;\n\n\t\tgpio = <&gpio 5 GPIO_ACTIVE_HIGH>;\n\t\tenable-active-high;\n\t};\n};\n\n&gphy0 {\n\tlantiq,gphy-mode = <GPHY_MODE_GE>;\n};\n\n&gphy1 {\n\tlantiq,gphy-mode = <GPHY_MODE_GE>;\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&state_default>;\n\n\tstate_default: pinmux {\n\t\tphy-rst {\n\t\t\tlantiq,pins = \"io32\", \"io44\";\n\t\t\tlantiq,pull = <0>;\n\t\t\tlantiq,open-drain;\n\t\t\tlantiq,output = <1>;\n\t\t};\n\n\t\tpcie-rst {\n\t\t\tlantiq,pins = \"io21\";\n\t\t\tlantiq,open-drain;\n\t\t\tlantiq,output = <1>;\n\t\t};\n\t};\n\n\tpcie-rst-dev {\n\t\tgpio-hog;\n\t\tline-name = \"pcie-rst-dev\";\n\t\tgpios = <22 GPIO_ACTIVE_LOW>;\n\t\toutput-low;\n\t};\n};\n\n&gswip {\n\tpinctrl-0 = <&mdio_pins>;\n\tpinctrl-names = \"default\";\n};\n\n&gswip_mdio {\n\tphy0: ethernet-phy@0 {\n\t\treg = <0x0>;\n\t\tgpios = <&gpio 32 GPIO_ACTIVE_HIGH>;\n\t};\n\n\tphy1: ethernet-phy@1 {\n\t\treg = <0x1>;\n\t\tgpios = <&gpio 44 GPIO_ACTIVE_HIGH>;\n\t};\n\n\tphy11: ethernet-phy@11 {\n\t\treg = <0x11>;\n\t};\n\n\tphy13: ethernet-phy@13 {\n\t\treg = <0x13>;\n\t};\n};\n\n&gswip_ports {\n\tport@0 {\n\t\treg = <0>;\n\t\tlabel = \"lan3\";\n\t\tphy-mode = \"rgmii\";\n\t\tphy-handle = <&phy0>;\n\t};\n\n\tport@1 {\n\t\treg = <1>;\n\t\tlabel = \"lan4\";\n\t\tphy-mode = \"rgmii\";\n\t\tphy-handle = <&phy1>;\n\t};\n\n\tport@2 {\n\t\treg = <2>;\n\t\tlabel = \"lan2\";\n\t\tphy-mode = \"internal\";\n\t\tphy-handle = <&phy11>;\n\t};\n\n\tport@4 {\n\t\treg = <4>;\n\t\tlabel = \"lan1\";\n\t\tphy-mode = \"internal\";\n\t\tphy-handle = <&phy13>;\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@4 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <4>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\treg = <0x0 0x20000>;\n\t\t\t\tlabel = \"urlader\";\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\treg = <0x20000 0x10000>;\n\t\t\t\tlabel = \"tffs (1)\";\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tlabel = \"tffs (2)\";\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&localbus {\n\tflash1: flash@1 {\n\t\tcompatible = \"lantiq,nand-xway\";\n\t\tbank-width = <1>;\n\t\treg = <1 0x0 0x2000000>;\n\n\t\tpinctrl-0 = <&nand_pins>;\n\t\tpinctrl-names = \"default\";\n\n\t\tnand-ecc-engine = <&flash1>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"kernel\";\n\t\t\t\treg = <0x0 0x400000>;\n\t\t\t};\n\n\t\t\tpartition@400000 {\n\t\t\t\tlabel = \"ubi\";\n\t\t\t\treg = <0x400000 0x7c00000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&usb_phy0 {\n\tstatus = \"okay\";\n};\n\n&usb_phy1 {\n\tstatus = \"okay\";\n};\n\n&usb0 {\n\tstatus = \"okay\";\n\tvbus-supply = <&usb0_vbus>;\n};\n\n&usb1 {\n\tstatus = \"okay\";\n\tvbus-supply = <&usb1_vbus>;\n};\n\n&pcie0 {\n\tstatus = \"okay\";\n\tgpio-reset = <&gpio 21 GPIO_ACTIVE_LOW>;\n\n\tpcie@0 {\n\t\treg = <0 0 0 0 0>;\n\t\t#interrupt-cells = <1>;\n\t\t#size-cells = <1>;\n\t\t#address-cells = <2>;\n\t\tdevice_type = \"pci\";\n\n\t\twifi@0,0 {\n\t\t\tcompatible = \"pci168c,0033\";\n\t\t\treg = <0 0 0 0 0>;\n\t\t\tqca,no-eeprom; /* load from ath9k-eeprom-pci-0000:01:00.0.bin */\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_avm_fritz7360-v2.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"vr9_avm_fritz736x.dtsi\"\n\n/ {\n\tcompatible = \"avm,fritz7360-v2\", \"avm,fritz736x\", \"lantiq,xway\", \"lantiq,vr9\";\n\tmodel = \"AVM FRITZ!Box 7360 V2\";\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&state_default>;\n\n\tstate_default: pinmux {\n\t\tpcie-rst {\n\t\t\tlantiq,pins = \"io21\";\n\t\t\tlantiq,pull = <0>;\n\t\t\tlantiq,output = <1>;\n\t\t};\n\n\t\tphy-rst {\n\t\t\tlantiq,pins = \"io37\", \"io44\";\n\t\t\tlantiq,pull = <0>;\n\t\t\tlantiq,open-drain;\n\t\t\tlantiq,output = <1>;\n\t\t};\n\t};\n};\n\n&localbus {\n\tflash@0 {\n\t\tcompatible = \"lantiq,nor\";\n\t\tbank-width = <2>;\n\t\treg = <0 0x0 0x2000000>;\n\n\t\tpartitions {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\t\t\tcompatible = \"fixed-partitions\";\n\n\t\t\turlader: partition@0 {\n\t\t\t\tlabel = \"urlader\";\n\t\t\t\treg = <0x00000 0x20000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x20000 0x1f60000>;\n\t\t\t};\n\n\t\t\tpartition@1f80000 {\n\t\t\t\tlabel = \"tffs (1)\";\n\t\t\t\treg = <0x1f80000 0x40000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@1fc0000 {\n\t\t\t\tlabel = \"tffs (2)\";\n\t\t\t\treg = <0x1fc0000 0x40000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&eth0 {\n\tnvmem-cells = <&macaddr_urlader_a91>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <(-2)>;\n};\n\n&phy0 {\n\treset-gpios = <&gpio 37 GPIO_ACTIVE_LOW>;\n};\n\n&phy1 {\n\treset-gpios = <&gpio 44 GPIO_ACTIVE_LOW>;\n};\n\n&urlader {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_urlader_a91: macaddr@a91 {\n\t\treg = <0xa91 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_avm_fritz7360sl.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"vr9_avm_fritz736x.dtsi\"\n\n/ {\n\tcompatible = \"avm,fritz7360sl\", \"avm,fritz736x\", \"lantiq,xway\", \"lantiq,vr9\";\n\tmodel = \"AVM FRITZ!Box 7360 SL\";\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&state_default>;\n\n\tstate_default: pinmux {\n\t\tpcie-rst {\n\t\t\tlantiq,pins = \"io21\";\n\t\t\tlantiq,pull = <0>;\n\t\t\tlantiq,output = <1>;\n\t\t};\n\n\t\tphy-rst {\n\t\t\tlantiq,pins = \"io37\", \"io44\";\n\t\t\tlantiq,pull = <0>;\n\t\t\tlantiq,open-drain;\n\t\t\tlantiq,output = <1>;\n\t\t};\n\t};\n\n};\n\n&localbus {\n\tflash@0 {\n\t\tcompatible = \"lantiq,nor\";\n\t\tbank-width = <2>;\n\t\treg = <0 0x0 0x1000000>;\n\n\t\tpartitions {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\t\t\tcompatible = \"fixed-partitions\";\n\n\t\t\turlader: partition@0 {\n\t\t\t\tlabel = \"urlader\";\n\t\t\t\treg = <0x00000 0x20000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x20000 0xf60000>;\n\t\t\t};\n\n\t\t\tpartition@f80000 {\n\t\t\t\tlabel = \"tffs (1)\";\n\t\t\t\treg = <0xf80000 0x40000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@fc0000 {\n\t\t\t\tlabel = \"tffs (2)\";\n\t\t\t\treg = <0xfc0000 0x40000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&eth0 {\n\tnvmem-cells = <&macaddr_urlader_a91>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <(-2)>;\n};\n\n&phy0 {\n\treset-gpios = <&gpio 37 GPIO_ACTIVE_LOW>;\n};\n\n&phy1 {\n\treset-gpios = <&gpio 44 GPIO_ACTIVE_LOW>;\n};\n\n&urlader {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_urlader_a91: macaddr@a91 {\n\t\treg = <0xa91 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_avm_fritz7362sl.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"vr9_avm_fritz736x.dtsi\"\n\n/ {\n\tcompatible = \"avm,fritz7362sl\", \"avm,fritz736x\", \"lantiq,xway\", \"lantiq,vr9\";\n\tmodel = \"AVM FRITZ!Box 7362 SL\";\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&state_default>;\n\n\tstate_default: pinmux {\n\t\tpcie-rst {\n\t\t\tlantiq,pins = \"io21\";\n\t\t\tlantiq,pull = <0>;\n\t\t\tlantiq,output = <1>;\n\t\t};\n\n\t\tphy-rst {\n\t\t\tlantiq,pins = \"io44\", \"io45\";\n\t\t\tlantiq,pull = <0>;\n\t\t\tlantiq,open-drain;\n\t\t\tlantiq,output = <1>;\n\t\t};\n\t};\n\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@4 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <4>;\n\t\tspi-max-frequency = <1000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\turlader: partition@0 {\n\t\t\t\treg = <0x0 0x40000>;\n\t\t\t\tlabel = \"urlader\";\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\treg = <0x40000 0x60000>;\n\t\t\t\tlabel = \"tffs (1)\";\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@A0000 {\n\t\t\t\treg = <0xA0000 0x60000>;\n\t\t\t\tlabel = \"tffs (2)\";\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&localbus {\n\tflash1: flash@1 {\n\t\tcompatible = \"lantiq,nand-xway\";\n\t\tlantiq,cs1 = <1>;\n\t\tbank-width = <1>;\n\t\treg = <1 0x0 0x2000000>;\n\n\t\tpinctrl-0 = <&nand_pins>, <&nand_cs1_pins>;\n\t\tpinctrl-names = \"default\";\n\n\t\tnand-ecc-engine = <&flash1>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"kernel\";\n\t\t\t\treg = <0x0 0x400000>;\n\t\t\t};\n\n\t\t\tpartition@400000 {\n\t\t\t\tlabel = \"ubi\";\n\t\t\t\treg = <0x400000 0x7c00000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pcie0 {\n\tgpio-reset = <&gpio 21 GPIO_ACTIVE_LOW>;\n\n\tpcie@0 {\n\t\t#size-cells = <1>;\n\t\t#address-cells = <2>;\n\t};\n};\n\n&eth0 {\n\tnvmem-cells = <&macaddr_urlader_a91>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <(-2)>;\n};\n\n&phy0 {\n\treset-gpios = <&gpio 45 GPIO_ACTIVE_LOW>;\n};\n\n&phy1 {\n\treset-gpios = <&gpio 44 GPIO_ACTIVE_LOW>;\n};\n\n&urlader {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_urlader_a91: macaddr@a91 {\n\t\treg = <0xa91 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_avm_fritz736x.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"vr9.dtsi\"\n\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/mips/lantiq_rcu_gphy.h>\n\n/ {\n\tcompatible = \"avm,fritz736x\", \"lantiq,xway\", \"lantiq,vr9\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyLTQ0,115200\";\n\t};\n\n\taliases {\n\t\tled-boot = &led_power_green;\n\t\tled-failsafe = &led_power_red;\n\t\tled-running = &led_power_green;\n\t\tled-upgrade = &led_power_red;\n\n\t\tled-dsl = &led_info_green;\n\t\tled-wifi = &led_wifi;\n\t};\n\n\tmemory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x0 0x8000000>;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <100>;\n\n\t\tdect {\n\t\t\tlabel = \"dect\";\n\t\t\tgpios = <&gpio 1 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_PHONE>;\n\t\t};\n\n\t\twifi {\n\t\t\tlabel = \"wifi\";\n\t\t\tgpios = <&gpio 29 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RFKILL>;\n\t\t};\n\t};\n\n\tleds: leds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power_green: power_green {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 32 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"keep\";\n\t\t};\n\n\t\tled_power_red: power_red {\n\t\t\tlabel = \"red:power\";\n\t\t\tgpios = <&gpio 33 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_info_green: info_green {\n\t\t\tlabel = \"green:info\";\n\t\t\tgpios = <&gpio 47 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_wifi: wifi {\n\t\t\tlabel = \"green:wlan\";\n\t\t\tgpios = <&gpio 36 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tinfo_red {\n\t\t\tlabel = \"red:info\";\n\t\t\tgpios = <&gpio 34 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tdect {\n\t\t\tlabel = \"green:dect\";\n\t\t\tgpios = <&gpio 35 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&gphy0 {\n\tlantiq,gphy-mode = <GPHY_MODE_GE>;\n};\n\n&gphy1 {\n\tlantiq,gphy-mode = <GPHY_MODE_GE>;\n};\n\n&gswip {\n\tpinctrl-0 = <&mdio_pins>;\n\tpinctrl-names = \"default\";\n};\n\n&gswip_mdio {\n\tphy0: ethernet-phy@0 {\n\t\treg = <0x00>;\n\t};\n\n\tphy1: ethernet-phy@1 {\n\t\treg = <0x01>;\n\t};\n\n\tphy11: ethernet-phy@11 {\n\t\treg = <0x11>;\n\t};\n\n\tphy13: ethernet-phy@13 {\n\t\treg = <0x13>;\n\t};\n};\n\n&gswip_ports {\n\tport@0 {\n\t\treg = <0>;\n\t\tlabel = \"lan3\";\n\t\tphy-mode = \"rmii\";\n\t\tphy-handle = <&phy0>;\n\t};\n\n\tport@1 {\n\t\treg = <1>;\n\t\tlabel = \"lan4\";\n\t\tphy-mode = \"rmii\";\n\t\tphy-handle = <&phy1>;\n\t};\n\n\tport@2 {\n\t\treg = <2>;\n\t\tlabel = \"lan2\";\n\t\tphy-mode = \"internal\";\n\t\tphy-handle = <&phy11>;\n\t};\n\n\tport@4 {\n\t\treg = <4>;\n\t\tlabel = \"lan1\";\n\t\tphy-mode = \"internal\";\n\t\tphy-handle = <&phy13>;\n\t};\n};\n\n&pcie0 {\n\tstatus = \"okay\";\n\n\tpcie@0 {\n\t\treg = <0 0 0 0 0>;\n\t\t#interrupt-cells = <1>;\n\t\t#size-cells = <1>;\n\t\t#address-cells = <2>;\n\t\tdevice_type = \"pci\";\n\n\t\twifi@168c,002e {\n\t\t\tcompatible = \"pci168c,002e\";\n\t\t\treg = <0 0 0 0 0>;\n\t\t\tqca,no-eeprom; /* load from ath9k-eeprom-pci-0000:01:00.0.bin */\n\t\t};\n\t};\n};\n\n&usb_phy0 {\n\tstatus = \"okay\";\n};\n\n&usb_phy1 {\n\tstatus = \"okay\";\n};\n\n&usb0 {\n\tstatus = \"okay\";\n};\n\n&usb1 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_avm_fritz7412.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"vr9.dtsi\"\n\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/mips/lantiq_rcu_gphy.h>\n\n/ {\n\tcompatible = \"avm,fritz7412\", \"lantiq,xway\", \"lantiq,vr9\";\n\tmodel = \"AVM FRITZ!Box 7412\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyLTQ0,115200\";\n\t};\n\n\taliases {\n\t\tled-boot = &power_green;\n\t\tled-failsafe = &power_red;\n\t\tled-running = &power_green;\n\t\tled-upgrade = &power_red;\n\n\t\tled-dsl = &info;\n\t\tled-wifi = &wifi;\n\t};\n\n\tmemory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x0 0x8000000>;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <100>;\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio 1 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\n\t\tdect {\n\t\t\tlabel = \"dect\";\n\t\t\tgpios = <&gpio 2 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_PHONE>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tpower_green: power_green {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 6 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"keep\";\n\t\t};\n\n\t\tpower_red: power_red {\n\t\t\tlabel = \"red:power\";\n\t\t\tgpios = <&gpio 5 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tfon {\n\t\t\tlabel = \"green:fon\";\n\t\t\tgpios = <&gpio 34 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tdect {\n\t\t\tlabel = \"green:dect\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twifi: wifi {\n\t\t\tlabel = \"green:wifi\";\n\t\t\tgpios = <&gpio 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tinfo: info {\n\t\t\tlabel = \"green:info\";\n\t\t\tgpios = <&gpio 35 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&localbus {\n\tflash@0 {\n\t\tcompatible = \"lantiq,nand-xway\";\n\t\tbank-width = <2>;\n\t\treg = <0 0x0 0x2000000>;\n\t\tlantiq,cs = <1>;\n\n\t\tpinctrl-0 = <&nand_pins>, <&nand_cs1_pins>;\n\t\tpinctrl-names = \"default\";\n\n\t\tnand-use-soft-ecc-engine;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"urlader\";\n\t\t\t\treg = <0x0 0x40000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"nand-tffs\";\n\t\t\t\treg = <0x40000 0x400000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@440000 {\n\t\t\t\tlabel = \"kernel\";\n\t\t\t\treg = <0x440000 0x400000>;\n\t\t\t};\n\n\t\t\tpartition@840000 {\n\t\t\t\tlabel = \"ubi\";\n\t\t\t\treg = <0x840000 0x3000000>;\n\t\t\t};\n\n\t\t\tpartition@3840000 {\n\t\t\t\tlabel = \"reserved-kernel\";\n\t\t\t\treg = <0x3840000 0x400000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@3c40000 {\n\t\t\t\tlabel = \"reserved-filesystem\";\n\t\t\t\treg = <0x3c40000 0x3000000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@6c40000 {\n\t\t\t\tlabel = \"config\";\n\t\t\t\treg = <0x6c40000 0x400000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@6e40000 {\n\t\t\t\tlabel = \"nand-filesystem\";\n\t\t\t\treg = <0x6e40000 0x400000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pcie0 {\n\tstatus = \"okay\";\n\tgpio-reset = <&gpio 11 GPIO_ACTIVE_HIGH>;\n\n\tpcie@0 {\n\t\treg = <0 0 0 0 0>;\n\t\t#interrupt-cells = <1>;\n\t\t#size-cells = <2>;\n\t\t#address-cells = <3>;\n\t\tdevice_type = \"pci\";\n\n\t\twifi@168c,002e {\n\t\t\tcompatible = \"pci168c,002e\";\n\t\t\treg = <0 0 0 0 0>;\n\t\t\tqca,no-eeprom; /* load from ath9k-eeprom-pci-0000:01:00.0.bin */\n\t\t};\n\t};\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&state_default>;\n\n\tstate_default: pinmux {\n\t\tpcie-rst {\n\t\t\tlantiq,pins = \"io11\";\n\t\t\tlantiq,open-drain = <1>;\n\t\t\tlantiq,output = <1>;\n\t\t};\n\t};\n};\n\n&gphy0 {\n\tlantiq,gphy-mode = <GPHY_MODE_FE>;\n};\n\n&gswip_mdio {\n\tphy11: ethernet-phy@11 {\n\t\treg = <0x11>;\n\t};\n};\n\n&gswip_ports {\n\tport@2 {\n\t\treg = <2>;\n\t\tlabel = \"lan\";\n\t\tphy-mode = \"internal\";\n\t\tphy-handle = <&phy11>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_avm_fritz7430.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"vr9.dtsi\"\n\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/mips/lantiq_rcu_gphy.h>\n\n/ {\n\tcompatible = \"avm,fritz7430\", \"lantiq,xway\", \"lantiq,vr9\";\n\tmodel = \"AVM FRITZ!Box 7430\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyLTQ0,115200\";\n\t};\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_info_red;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_info_green;\n\n\t\tled-dsl = &led_info_green;\n\t\tled-wifi = &led_wifi;\n\t};\n\n\tmemory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x0 0x8000000>;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <100>;\n\n\t\tdect {\n\t\t\tlabel = \"dect\";\n\t\t\tgpios = <&gpio 1 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_PHONE>;\n\t\t};\n\n\t\twifi {\n\t\t\tlabel = \"wifi\";\n\t\t\tgpios = <&gpio 2 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RFKILL>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 31 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"keep\";\n\t\t};\n\n\t\tled_info_green: info_green {\n\t\t\tlabel = \"green:info\";\n\t\t\tgpios = <&gpio 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_info_red: info_red {\n\t\t\tlabel = \"red:info\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_wifi: wifi {\n\t\t\tlabel = \"green:wifi\";\n\t\t\tgpios = <&gpio 34 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tdect {\n\t\t\tlabel = \"green:dect\";\n\t\t\tgpios = <&gpio 35 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tfon {\n\t\t\tlabel = \"green:fon\";\n\t\t\tgpios = <&gpio 36 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tusb0_vbus: regulator-usb0-vbus {\n\t\tcompatible = \"regulator-fixed\";\n\n\t\tregulator-name = \"USB0_VBUS\";\n\n\t\tregulator-min-microvolt = <5000000>;\n\t\tregulator-max-microvolt = <5000000>;\n\n\t\tgpio = <&gpio 5 GPIO_ACTIVE_HIGH>;\n\t\tenable-active-high;\n\t};\n};\n\n&localbus {\n\tflash@0 {\n\t\tcompatible = \"lantiq,nand-xway\";\n\t\tbank-width = <2>;\n\t\treg = <0 0x0 0x8000000>;\n\t\tlantiq,cs = <1>;\n\n\t\tpinctrl-0 = <&nand_pins>, <&nand_cs1_pins>;\n\t\tpinctrl-names = \"default\";\n\n\t\tnand-use-soft-ecc-engine;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"urlader\";\n\t\t\t\treg = <0x0 0x40000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"nand-tffs\";\n\t\t\t\treg = <0x40000 0x400000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@440000 {\n\t\t\t\tlabel = \"kernel\";\n\t\t\t\treg = <0x440000 0x400000>;\n\t\t\t};\n\n\t\t\tpartition@840000 {\n\t\t\t\tlabel = \"ubi\";\n\t\t\t\treg = <0x840000 0x3000000>;\n\t\t\t};\n\n\t\t\tpartition@3840000 {\n\t\t\t\tlabel = \"reserved-kernel\";\n\t\t\t\treg = <0x3840000 0x400000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@3c40000 {\n\t\t\t\tlabel = \"reserved-filesystem\";\n\t\t\t\treg = <0x3c40000 0x3000000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@6c40000 {\n\t\t\t\tlabel = \"config\";\n\t\t\t\treg = <0x6c40000 0x200000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@6e40000 {\n\t\t\t\tlabel = \"nand-filesystem\";\n\t\t\t\treg = <0x6e40000 0x11c0000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pcie0 {\n\tstatus = \"okay\";\n\n\tgpio-reset = <&gpio 11 GPIO_ACTIVE_LOW>;\n\n\tpcie@0 {\n\t\treg = <0 0 0 0 0>;\n\t\t#interrupt-cells = <1>;\n\t\t#size-cells = <2>;\n\t\t#address-cells = <3>;\n\t\tdevice_type = \"pci\";\n\n\t\twifi@168c,abcd {\n\t\t\tcompatible = \"pci168c,abcd\";\n\t\t\treg = <0 0 0 0 0>;\n\t\t\tqca,no-eeprom; /* load from ath9k-eeprom-pci-0000:01:00.0.bin */\n\t\t};\n\t};\n};\n\n&gphy0 {\n\tlantiq,gphy-mode = <GPHY_MODE_FE>;\n};\n\n&gphy1 {\n\tlantiq,gphy-mode = <GPHY_MODE_FE>;\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&state_default>;\n\n\tstate_default: pinmux {\n\t\tpcie-rst {\n\t\t\tlantiq,pins = \"io11\";\n\t\t\tlantiq,open-drain = <1>;\n\t\t\tlantiq,output = <1>;\n\t\t};\n\t};\n};\n\n&gswip_mdio {\n\tphy11: ethernet-phy@11 {\n\t\treg = <0x11>;\n\t};\n\tphy12: ethernet-phy@12 {\n\t\treg = <0x12>;\n\t};\n\tphy13: ethernet-phy@13 {\n\t\treg = <0x13>;\n\t};\n\tphy14: ethernet-phy@14 {\n\t\treg = <0x14>;\n\t};\n};\n\n&gswip_ports {\n\tport@2 {\n\t\treg = <2>;\n\t\tlabel = \"lan3\";\n\t\tphy-mode = \"internal\";\n\t\tphy-handle = <&phy11>;\n\t};\n\tport@3 {\n\t\treg = <3>;\n\t\tlabel = \"lan4\";\n\t\tphy-mode = \"internal\";\n\t\tphy-handle = <&phy12>;\n\t};\n\tport@4 {\n\t\treg = <4>;\n\t\tlabel = \"lan1\";\n\t\tphy-mode = \"internal\";\n\t\tphy-handle = <&phy13>;\n\t};\n\tport@5 {\n\t\treg = <5>;\n\t\tlabel = \"lan2\";\n\t\tphy-mode = \"internal\";\n\t\tphy-handle = <&phy14>;\n\t};\n};\n\n&usb_phy0 {\n\tstatus = \"okay\";\n};\n\n&usb0 {\n\tstatus = \"okay\";\n\n\tvbus-supply = <&usb0_vbus>;\n};\n"
  },
  {
    "path": "target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_bt_homehub-v5a.dts",
    "content": "#include \"vr9.dtsi\"\n\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/mips/lantiq_rcu_gphy.h>\n\n/ {\n\tcompatible = \"bt,homehub-v5a\", \"lantiq,xway\", \"lantiq,vr9\";\n\tmodel = \"BT Home Hub 5A\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyLTQ0,115200\";\n\t};\n\n\taliases {\n\t\tled-boot = &power_green;\n\t\tled-failsafe = &power_red;\n\t\tled-running = &power_blue;\n\t\tled-upgrade = &power_blue;\n\n\t\tled-dsl = &broadband_blue;\n\t\tled-wifi = &wireless_blue;\n\t};\n\n\tmemory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x0 0x8000000>;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <100>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 2 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio 25 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\n\t\trestart {\n\t\t\tlabel = \"restart\";\n\t\t\tgpios = <&gpio 39 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_POWER2>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\t/* broadband-* is a single RGB led */\n\t\tbroadband-red {\n\t\t\tlabel = \"red:broadband\";\n\t\t\tgpios = <&gpio 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tbroadband-green {\n\t\t\tlabel = \"green:broadband\";\n\t\t\tgpios = <&gpio 3 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tbroadband_blue: broadband-blue {\n\t\t\tlabel = \"blue:broadband\";\n\t\t\tgpios = <&gpio 8 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\t/* wireless-* is a single RGB led */\n\t\twireless-red {\n\t\t\tlabel = \"red:wireless\";\n\t\t\tgpios = <&gpio 9 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\twireless-green {\n\t\t\tlabel = \"green:wireless\";\n\t\t\tgpios = <&gpio 10 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\twireless_blue: wireless-blue {\n\t\t\tlabel = \"blue:wireless\";\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\t/* power-* is a single RGB led */\n\t\tpower_red: power-red {\n\t\t\tlabel = \"red:power\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tpower_green: power-green {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"keep\";\n\t\t};\n\t\tpower_blue: power-blue {\n\t\t\tlabel = \"blue:power\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tdimmed {\n\t\t\tlabel = \"dimmed\";\n\t\t\tgpios = <&gpio 19 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n\n\tusb_vbus: regulator-usb-vbus {\n\t\tcompatible = \"regulator-fixed\";\n\n\t\tregulator-name = \"USB_VBUS\";\n\n\t\tregulator-min-microvolt = <5000000>;\n\t\tregulator-max-microvolt = <5000000>;\n\n\t\tgpio = <&gpio 33 GPIO_ACTIVE_HIGH>;\n\t\tenable-active-high;\n\t};\n};\n\n&gphy0 {\n\tlantiq,gphy-mode = <GPHY_MODE_GE>;\n};\n\n&gphy1 {\n\tlantiq,gphy-mode = <GPHY_MODE_GE>;\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&state_default>;\n\n\tstate_default: pinmux {\n\t\tpci_rst {\n\t\t\tlantiq,pins = \"io21\";\n\t\t\tlantiq,output = <1>;\n\t\t\tlantiq,open-drain;\n\t\t};\n\t\tpcie_rst {\n\t\t\tlantiq,pins = \"io38\";\n\t\t\tlantiq,pull = <0>;\n\t\t\tlantiq,output = <1>;\n\t\t\tlantiq,open-drain;\n\t\t};\n\t\tusb_vbus {\n\t\t\tlantiq,pins = \"io33\";\n\t\t\tlantiq,pull = <0>;\n\t\t\tlantiq,open-drain = <0>;\n\t\t\tlantiq,output = <1>;\n\t\t};\n\t};\n};\n\n&gswip {\n\tpinctrl-0 = <&mdio_pins>;\n\tpinctrl-names = \"default\";\n};\n\n&gswip_mdio {\n\tphy0: ethernet-phy@0 {\n\t\treg = <0x0>;\n\t};\n\tphy1: ethernet-phy@1 {\n\t\treg = <0x1>;\n\t};\n\tphy5: ethernet-phy@5 {\n\t\treg = <0x5>;\n\t};\n\tphy11: ethernet-phy@11 {\n\t\treg = <0x11>;\n\t};\n\tphy13: ethernet-phy@13 {\n\t\treg = <0x13>;\n\t};\n};\n\n&gswip_ports {\n\tport@0 {\n\t\treg = <0>;\n\t\tlabel = \"lan3\";\n\t\tphy-mode = \"rgmii\";\n\t\tphy-handle = <&phy0>;\n\t};\n\tport@1 {\n\t\treg = <1>;\n\t\tlabel = \"lan4\";\n\t\tphy-mode = \"rgmii\";\n\t\tphy-handle = <&phy1>;\n\t};\n\tport@2 {\n\t\treg = <2>;\n\t\tlabel = \"lan2\";\n\t\tphy-mode = \"internal\";\n\t\tphy-handle = <&phy11>;\n\t};\n\tport@4 {\n\t\treg = <4>;\n\t\tlabel = \"lan1\";\n\t\tphy-mode = \"internal\";\n\t\tphy-handle = <&phy13>;\n\t};\n\tport@5 {\n\t\treg = <5>;\n\t\tlabel = \"wan\";\n\t\tphy-mode = \"rgmii\";\n\t\tphy-handle = <&phy5>;\n\t};\n};\n\n&localbus {\n\tflash@1 {\n\t\tcompatible = \"lantiq,nand-xway\";\n\t\tlantiq,cs = <1>;\n\t\tbank-width = <2>;\n\t\treg = <0x1 0x0 0x2000000>;\n\n\t\tpinctrl-0 = <&nand_pins>, <&nand_cs1_pins>;\n\t\tpinctrl-names = \"default\";\n\n\t\tnand-on-flash-bbt;\n\t\tnand-ecc-strength = <3>;\n\t\tnand-ecc-step-size = <256>;\n\t\tnand-use-soft-ecc-engine;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0xa0000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@a0000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0xa0000 0x20000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@c0000 {\n\t\t\t\tlabel = \"unused\";\n\t\t\t\treg = <0xc0000 0x40000>;\n\t\t\t};\n\t\t\tpartition@100000 {\n\t\t\t\tlabel = \"ubi\";\n\t\t\t\treg = <0x100000 0x7e80000>;\n\t\t\t};\n\t\t\t/*\n\t\t\t * last 512 KiB are for the bad block table, not writable\n\t\t\t */\n\t\t};\n\t};\n};\n\n&pci0 {\n\tstatus = \"okay\";\n\tgpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>;\n\n\twifi@168c,002d {\n\t\tcompatible = \"pci168c,002d\";\n\t\treg = <0x7000 0 0 0 0>;\n\t\tqca,no-eeprom; /* load from ath9k-eeprom-pci-0000:00:0e.0.bin */\n\t\tieee80211-freq-limit = <2402000 2482000>;\n\t};\n};\n\n&usb_phy0 {\n\tstatus = \"okay\";\n};\n\n&usb0 {\n\tstatus = \"okay\";\n\tvbus-supply = <&usb_vbus>;\n};\n"
  },
  {
    "path": "target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_buffalo_wbmr-300hpd.dts",
    "content": "#include \"vr9.dtsi\"\n\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/mips/lantiq_rcu_gphy.h>\n\n/ {\n\tcompatible = \"buffalo,wbmr-300hpd\", \"lantiq,xway\", \"lantiq,vr9\";\n\tmodel = \"Buffalo WBMR-300HPD\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyLTQ0,115200\";\n\t};\n\n\taliases {\n\t\tled-boot = &power_g;\n\t\tled-failsafe = &diag_r;\n\t\tled-running = &power_g;\n\t\tled-upgrade = &power_g;\n\n\t\tled-dsl = &dsl;\n\t\tled-internet = &router_g;\n\t\tled-wifi = &wifi_g;\n\t};\n\n\tmemory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x0 0x4000000>;\n\t};\n\n\tgpio_poweroff {\n\t\tcompatible = \"gpio-poweroff\";\n\t\tgpios = <&gpio 6 GPIO_ACTIVE_LOW>;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <100>;\n\n\t\tpower {\n\t\t\tlabel = \"power\";\n\t\t\tgpios = <&gpio 5 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_POWER>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio 31 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\n\t\tauto {\n\t\t\tlabel = \"auto\";\n\t\t\tgpios = <&gpio 48 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = <BTN_0>;\n\t\t\tlinux,input-type = <EV_SW>;\n\t\t};\n\n\t\trouter {\n\t\t\tlabel = \"router\";\n\t\t\tgpios = <&gpio 2 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = <BTN_1>;\n\t\t\tlinux,input-type = <EV_SW>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tdiag_r: diag_r {\n\t\t\tlabel = \"red:diag\";\n\t\t\tgpios = <&gpio 0 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault_state = \"off\";\n\t\t};\n\n\t\twifi_g: wifi_g {\n\t\t\tlabel = \"green:wifi\";\n\t\t\tgpios = <&gpio 1 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tdsl: dsl {\n\t\t\tlabel = \"dsl\";\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\trouter_y: router_y {\n\t\t\tlabel = \"yellow:router\";\n\t\t\tgpios = <&gpio 8 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\twifi_y: wifi_y {\n\t\t\tlabel = \"yellow:wifi\";\n\t\t\tgpios = <&gpio 9 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tlan1: lan1 {\n\t\t\tlabel = \"green:lan1\";\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\twan: wan {\n\t\t\tlabel = \"green:wan\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tlan3: lan3 {\n\t\t\tlabel = \"green:lan3\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tlan2: lan2 {\n\t\t\tlabel = \"green:lan2\";\n\t\t\tgpios = <&gpio 33 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tinternet_g: internet_g {\n\t\t\tlabel = \"green:internet\";\n\t\t\tgpios = <&gpio 34 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tinternet_y: internet_y {\n\t\t\tlabel = \"yellow:internet\";\n\t\t\tgpios = <&gpio 35 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\trouter_g: router_g {\n\t\t\tlabel = \"green:router\";\n\t\t\tgpios = <&gpio 36 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tpower_g: power_g {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 49 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n\n\tusb_vbus: regulator-usb-vbus {\n\t\tcompatible = \"regulator-fixed\";\n\n\t\tregulator-name = \"USB_VBUS\";\n\n\t\tregulator-min-microvolt = <5000000>;\n\t\tregulator-max-microvolt = <5000000>;\n\n\t\tgpio = <&gpio 33 GPIO_ACTIVE_HIGH>;\n\t\tenable-active-high;\n\t};\n};\n\n&gphy0 {\n\tlantiq,gphy-mode = <GPHY_MODE_FE>;\n};\n\n&gphy1 {\n\tlantiq,gphy-mode = <GPHY_MODE_FE>;\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&state_default>;\n\n\tstate_default: pinmux {\n\t\tphy-rst {\n\t\t\tlantiq,pins = \"io42\";\n\t\t\tlantiq,pull = <0>;\n\t\t\tlantiq,open-drain = <0>;\n\t\t\tlantiq,output = <1>;\n\t\t};\n\t\tpcie-rst {\n\t\t\tlantiq,pins = \"io38\";\n\t\t\tlantiq,pull = <0>;\n\t\t\tlantiq,output = <1>;\n\t\t};\n\t};\n};\n\n&gswip_mdio {\n\tphy11: ethernet-phy@11 {\n\t\treg = <0x11>;\n\t};\n\tphy12: ethernet-phy@12 {\n\t\treg = <0x12>;\n\t};\n\tphy13: ethernet-phy@13 {\n\t\treg = <0x13>;\n\t};\n\tphy14: ethernet-phy@14 {\n\t\treg = <0x14>;\n\t};\n};\n\n&gswip_ports {\n\tport@2 {\n\t\treg = <2>;\n\t\tlabel = \"lan3\";\n\t\tphy-mode = \"internal\";\n\t\tphy-handle = <&phy11>;\n\t};\n\tport@3 {\n\t\treg = <3>;\n\t\tlabel = \"lan4\";\n\t\tphy-mode = \"internal\";\n\t\tphy-handle = <&phy12>;\n\t};\n\tport@4 {\n\t\treg = <4>;\n\t\tlabel = \"lan1\";\n\t\tphy-mode = \"internal\";\n\t\tphy-handle = <&phy13>;\n\t};\n\tport@5 {\n\t\treg = <5>;\n\t\tlabel = \"lan2\";\n\t\tphy-mode = \"internal\";\n\t\tphy-handle = <&phy14>;\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@4 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <4>;\n\t\tspi-max-frequency = <20000000>;\n\n\t\tpartitions {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\treg = <0x0 0x10000>;\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@10000 {\n\t\t\t\treg = <0x10000 0x10000>;\n\t\t\t\tlabel = \"gphyfirmware\";\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\treg = <0x20000 0x80000>;\n\t\t\t\tlabel = \"dsl_fw\";\n\t\t\t};\n\n\t\t\tpartition@de0000 {\n\t\t\t\treg = <0xa0000 0xf40000>;\n\t\t\t\tlabel = \"firmware\";\n\t\t\t};\n\n\t\t\tpartition@fe0000 {\n\t\t\t\treg = <0xfe0000 0x10000>;\n\t\t\t\tlabel = \"sysconfig\";\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@ff0000 {\n\t\t\t\treg = <0xff0000 0x2000>;\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t};\n\n\t\t\tpartition@ff3000 {\n\t\t\t\treg = <0xff3000 0x2000>;\n\t\t\t\tlabel = \"board_config\";\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&usb_phy0 {\n\tstatus = \"okay\";\n};\n\n&usb_phy1 {\n\tstatus = \"okay\";\n};\n\n&usb0 {\n\tstatus = \"okay\";\n\tvbus-supply = <&usb_vbus>;\n};\n\n&usb1 {\n\tstatus = \"okay\";\n\tvbus-supply = <&usb_vbus>;\n};\n"
  },
  {
    "path": "target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_lantiq_easy80920-nand.dts",
    "content": "#include \"vr9_lantiq_easy80920.dtsi\"\n\n/ {\n\tcompatible = \"lantiq,easy80920-nand\", \"lantiq,easy80920\", \"lantiq,xway\", \"lantiq,vr9\";\n\tmodel = \"Intel EASY80920 Nand\";\n\n\tchosen {\n\t\tbootargs = \"ubi.mtd=ubi ubi.block=0,rootfsA root=/dev/ubiblock0_1\";\n\t};\n};\n\n&localbus {\n\tflash@0 {\n\t\tcompatible = \"lantiq,nand-xway\";\n\t\tlantiq,cs = <1>;\n\t\tbank-width = <2>;\n\t\treg = <0 0x0 0x2000000>;\n\n\t\tpinctrl-0 = <&nand_pins>;\n\t\tpinctrl-names = \"default\";\n\n\t\tnand-use-soft-ecc-engine;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"uboot\";\n\t\t\t\treg = <0x00000 0x100000>; /* 1024 KB */\n\t\t\t};\n\n\t\t\tpartition@100000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x100000 0x40000>; /* 256 KB */\n\t\t\t};\n\n\t\t\tpartition@140000 {\n\t\t\t\tlabel = \"ubootconfigB\";\n\t\t\t\treg = <0x140000 0x40000>; /* 256 KB */\n\t\t\t};\n\n\t\t\tpartition@180000 {\n\t\t\t\tlabel = \"gphyfirmware\";\n\t\t\t\treg = <0x180000 0x40000>; /* 256 KB */\n\t\t\t};\n\n\t\t\tpartition@1c0000 {\n\t\t\t\tlabel = \"ubi\";\n\t\t\t\treg = <0x1c0000 0xc800000>;\n\t\t\t};\n\n\t\t\tpartition@c9c0000 {\n\t\t\t\tlabel = \"calibration\";\n\t\t\t\treg = <0xc9c0000 0x100000>;\n\t\t\t};\n\n\t\t\tpartition@cac0000 {\n\t\t\t\tlabel = \"res\";\n\t\t\t\treg = <0xcac0000 0x13540000>;\n\t\t\t};\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_lantiq_easy80920-nor.dts",
    "content": "#include \"vr9_lantiq_easy80920.dtsi\"\n\n/ {\n\tcompatible = \"lantiq,easy80920-nor\", \"lantiq,easy80920\", \"lantiq,xway\", \"lantiq,vr9\";\n\tmodel = \"Intel EASY80920 Nor\";\n};\n\n&localbus {\n\tflash@0 {\n\t\tcompatible = \"lantiq,nor\";\n\t\tbank-width = <2>;\n\t\treg = <0 0x0 0x2000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"uboot\";\n\t\t\t\treg = <0x00000 0x10000>;\n\t\t\t};\n\n\t\t\tpartition@10000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x10000 0x10000>;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x20000 0x7e0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_lantiq_easy80920.dtsi",
    "content": "#include \"vr9.dtsi\"\n\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/mips/lantiq_rcu_gphy.h>\n\n/ {\n\tcompatible = \"lantiq,easy80920\", \"lantiq,xway\", \"lantiq,vr9\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyLTQ0,115200\";\n\t};\n\n\taliases {\n\t\tled-boot = &power;\n\t\tled-failsafe = &power;\n\t\tled-running = &power;\n\t\tled-upgrade = &power;\n\t};\n\n\tmemory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x0 0x4000000>;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <100>;\n/*\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};*/\n\t\tpaging {\n\t\t\tlabel = \"paging\";\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_PHONE>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tpower: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&stp 9 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"keep\";\n\t\t};\n\t\twarning {\n\t\t\tlabel = \"green:warning\";\n\t\t\tgpios = <&stp 22 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t\tfxs1 {\n\t\t\tlabel = \"green:fxs1\";\n\t\t\tgpios = <&stp 21 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t\tfxs2 {\n\t\t\tlabel = \"green:fxs2\";\n\t\t\tgpios = <&stp 20 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t\tfxo {\n\t\t\tlabel = \"green:fxo\";\n\t\t\tgpios = <&stp 19 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t\tusb1 {\n\t\t\tlabel = \"green:usb1\";\n\t\t\tgpios = <&stp 18 GPIO_ACTIVE_HIGH>;\n\t\t\ttrigger-sources = <&ehci_port1>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\n\t\tusb2 {\n\t\t\tlabel = \"green:usb2\";\n\t\t\tgpios = <&stp 15 GPIO_ACTIVE_HIGH>;\n\t\t\ttrigger-sources = <&ehci_port2>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\t\tsd {\n\t\t\tlabel = \"green:sd\";\n\t\t\tgpios = <&stp 14 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t\twps {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&stp 12 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n\n\tusb_vbus: regulator-usb-vbus {\n\t\tcompatible = \"regulator-fixed\";\n\n\t\tregulator-name = \"USB_VBUS\";\n\n\t\tregulator-min-microvolt = <5000000>;\n\t\tregulator-max-microvolt = <5000000>;\n\n\t\tgpio = <&gpio 33 GPIO_ACTIVE_HIGH>;\n\t\tenable-active-high;\n\t};\n};\n\n&gphy0 {\n\tlantiq,gphy-mode = <GPHY_MODE_GE>;\n};\n\n&gphy1 {\n\tlantiq,gphy-mode = <GPHY_MODE_GE>;\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&state_default>;\n\n\tstate_default: pinmux {\n\t\texin3 {\n\t\t\tlantiq,groups = \"exin3\";\n\t\t\tlantiq,function = \"exin\";\n\t\t};\n\t\tconf_out {\n\t\t\tlantiq,pins = \"io21\",\n\t\t\t\t\t\"io33\";\n\t\t\tlantiq,open-drain;\n\t\t\tlantiq,pull = <0>;\n\t\t\tlantiq,output = <1>;\n\t\t};\n\t\tpcie-rst {\n\t\t\tlantiq,pins = \"io38\";\n\t\t\tlantiq,pull = <0>;\n\t\t\tlantiq,output = <1>;\n\t\t};\n\t\tconf_in {\n\t\t\tlantiq,pins = \"io39\"; /* exin3 */\n\t\t\tlantiq,pull = <2>;\n\t\t};\n\t};\n};\n\n&gswip {\n\tpinctrl-0 = <&mdio_pins>;\n\tpinctrl-names = \"default\";\n};\n\n&gswip_mdio {\n\tphy0: ethernet-phy@0 {\n\t\treg = <0x0>;\n\t};\n\tphy1: ethernet-phy@1 {\n\t\treg = <0x1>;\n\t};\n\tphy5: ethernet-phy@5 {\n\t\treg = <0x5>;\n\t};\n\tphy11: ethernet-phy@11 {\n\t\treg = <0x11>;\n\t};\n\tphy13: ethernet-phy@13 {\n\t\treg = <0x13>;\n\t};\n};\n\n&gswip_ports {\n\tport@0 {\n\t\treg = <0>;\n\t\tlabel = \"lan4\";\n\t\tphy-mode = \"rgmii\";\n\t\tphy-handle = <&phy0>;\n\t};\n\tport@1 {\n\t\treg = <1>;\n\t\tlabel = \"lan3\";\n\t\tphy-mode = \"rgmii\";\n\t\tphy-handle = <&phy1>;\n\t};\n\tport@2 {\n\t\treg = <2>;\n\t\tlabel = \"lan2\";\n\t\tphy-mode = \"internal\";\n\t\tphy-handle = <&phy11>;\n\t};\n\tport@4 {\n\t\treg = <4>;\n\t\tlabel = \"lan1\";\n\t\tphy-mode = \"internal\";\n\t\tphy-handle = <&phy13>;\n\t};\n\tport@5 {\n\t\treg = <5>;\n\t\tlabel = \"wan\";\n\t\tphy-mode = \"rgmii\";\n\t\tphy-handle = <&phy5>;\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@4 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <4>;\n\t\tspi-max-frequency = <1000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\treg = <0x0 0x20000>;\n\t\t\t\tlabel = \"SPI (RO) U-Boot Image\";\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\treg = <0x20000 0x10000>;\n\t\t\t\tlabel = \"ENV_MAC\";\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tlabel = \"DPF\";\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tlabel = \"NVRAM\";\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\treg = <0x50000 0x3a0000>;\n\t\t\t\tlabel = \"kernel\";\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pci0 {\n\tpinctrl-0 = <&pci_gnt1_pins>, <&pci_req1_pins>;\n\tpinctrl-names = \"default\";\n};\n\n&stp {\n\tstatus = \"okay\";\n\n\tlantiq,shadow = <0xffff>;\n\tlantiq,dsl = <0x3>;\n\tlantiq,phy1 = <0x7>;\n\tlantiq,phy2 = <0x7>;\n\t/* lantiq,rising; */\n};\n\n&usb_phy0 {\n\tstatus = \"okay\";\n};\n\n&usb0 {\n\tstatus = \"okay\";\n\tvbus-supply = <&usb_vbus>;\n};\n"
  },
  {
    "path": "target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_netgear_dm200.dts",
    "content": "#include \"vr9.dtsi\"\n\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/mips/lantiq_rcu_gphy.h>\n\n/ {\n\tcompatible = \"netgear,dm200\", \"lantiq,xway\", \"lantiq,vr9\";\n\tmodel = \"Netgear DM200\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyLTQ0,115200\";\n\t};\n\n\taliases {\n\t\tled-boot = &power_green;\n\t\tled-failsafe = &power_amber;\n\t\tled-running = &power_green;\n\t\tled-upgrade = &power_green;\n\n\t\tled-dsl = &dsl_green;\n\t};\n\n\tmemory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x0 0x4000000>;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <100>;\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tgpio_export {\n\t\tcompatible = \"gpio-export\";\n\t\t#size-cells = <0>;\n\n\t\tannexa {\n\t\t\tgpio-export,name = \"annexa\";\n\t\t\tgpio-export,output = <0>;\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t\tannexb {\n\t\t\tgpio-export,name = \"annexb\";\n\t\t\tgpio-export,output = <0>;\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tpower_amber: power_amber {\n\t\t\tlabel = \"amber:power\";\n\t\t\tgpios = <&gpio 0 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t\tpower_green: power_green {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 1 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tlan_amber {\n\t\t\tlabel = \"amber:lan\";\n\t\t\tgpios = <&gpio 33 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t\tlan_green {\n\t\t\tlabel = \"green:lan\";\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tdsl_amber {\n\t\t\tlabel = \"amber:dsl\";\n\t\t\tgpios = <&gpio 8 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t\tdsl_green: dsl_green {\n\t\t\tlabel = \"green:dsl\";\n\t\t\tgpios = <&gpio 36 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&gphy1 {\n\tlantiq,gphy-mode = <GPHY_MODE_FE>;\n};\n\n&gswip_mdio {\n\tphy13: ethernet-phy@13 {\n\t\treg = <0x13>;\n\t};\n};\n\n&gswip_ports {\n\tport@4 {\n\t\treg = <4>;\n\t\tlabel = \"lan\";\n\t\tphy-mode = \"internal\";\n\t\tphy-handle = <&phy13>;\n\t};\n};\n\n&pcie0 {\n\tstatus = \"disabled\";\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@4 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <4>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\t\t\tcompatible = \"fixed-partitions\";\n\n\t\t\tpartition@0 {\n\t\t\t\treg = <0x0 0x20000>;\n\t\t\t\tlabel = \"uboot\";\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\treg = <0x20000 0x10000>;\n\t\t\t\tlabel = \"gphyfirmware\";\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\treg = <0x30000 0x7b0000>;\n\t\t\t\tlabel = \"firmware\";\n\t\t\t};\n\n\t\t\tpartition@7e0000 {\n\t\t\t\treg = <0x7e0000 0x10000>;\n\t\t\t\tlabel = \"sysconfig\";\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@7f0000 {\n\t\t\t\treg = <0x7f0000 0x2000>;\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@7f2000 {\n\t\t\t\treg = <0x7f2000 0x1000>;\n\t\t\t\tlabel = \"ART\";\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@7f3000 {\n\t\t\t\treg = <0x7f3000 0x1000>;\n\t\t\t\tlabel = \"pot\";\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@7f4000 {\n\t\t\t\treg = <0x7f4000 0xc000>;\n\t\t\t\tlabel = \"ret\";\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_tplink_tdw8970.dts",
    "content": "#include \"vr9_tplink_tdw89x0.dtsi\"\n\n/ {\n\tcompatible = \"tplink,tdw8970\", \"tplink,tdw89x0\", \"lantiq,xway\", \"lantiq,vr9\";\n\tmodel = \"TP-LINK TD-W8970\";\n};\n"
  },
  {
    "path": "target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_tplink_tdw8980.dts",
    "content": "#include \"vr9_tplink_tdw89x0.dtsi\"\n\n/ {\n\tcompatible = \"tplink,tdw8980\", \"tplink,tdw89x0\", \"lantiq,xway\", \"lantiq,vr9\";\n\tmodel = \"TP-LINK TD-W8980\";\n};\n\n&leds {\n\twifi2 {\n\t\tlabel = \"green:wlan5ghz\";\n\t\tgpios = <&gpio 24 GPIO_ACTIVE_LOW>;\n\t};\n};\n\n&gpio {\n\tstate_default: pinmux {\n\t\tpci_rst {\n\t\t\tlantiq,pins = \"io21\";\n\t\t\tlantiq,output = <1>;\n\t\t\tlantiq,open-drain;\n\t\t};\n\t};\n};\n\n&pci0 {\n\tstatus = \"okay\";\n\tlantiq,bus-clock = <33333333>;\n\tinterrupt-map-mask = <0xf800 0x0 0x0 0x7>;\n\tinterrupt-map = <0x7000 0 0 1 &icu0 30 1>;\n\tgpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>;\n};\n"
  },
  {
    "path": "target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_tplink_tdw89x0.dtsi",
    "content": "#include \"vr9.dtsi\"\n\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/mips/lantiq_rcu_gphy.h>\n\n/ {\n\tcompatible = \"tplink,tdw89x0\", \"lantiq,xway\", \"lantiq,vr9\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyLTQ0,115200\";\n\t};\n\n\taliases {\n\t\t/* the power led can't be controlled, use the wps led instead */\n\t\tled-boot = &led_wps;\n\t\tled-failsafe = &led_wps;\n\n\t\tled-dsl = &led_dsl;\n\t\tled-internet = &led_internet;\n\t\tled-wifi = &led_wifi;\n\t};\n\n\tmemory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x0 0x4000000>;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <100>;\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twifi {\n\t\t\tlabel = \"wifi\";\n\t\t\tgpios = <&gpio 9 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = <KEY_RFKILL>;\n\t\t\tlinux,input-type = <EV_SW>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio 39 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n\n\tleds: leds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\t/*\n\t\t\tpower is not controllable via gpio\n\t\t*/\n\n\t\tled_dsl: dsl {\n\t\t\tlabel = \"green:dsl\";\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tled_internet: internet {\n\t\t\tlabel = \"green:internet\";\n\t\t\tgpios = <&gpio 5 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tusb0 {\n\t\t\tlabel = \"green:usb\";\n\t\t\tgpios = <&gpio 19 GPIO_ACTIVE_HIGH>;\n\t\t\ttrigger-sources = <&ehci_port1>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\n\t\tusb2 {\n\t\t\tlabel = \"green:usb2\";\n\t\t\tgpios = <&gpio 20 GPIO_ACTIVE_HIGH>;\n\t\t\ttrigger-sources = <&ehci_port2>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\n\t\tled_wps: wps {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&gpio 37 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n\n\tath9k-leds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_wifi: wifi {\n\t\t\tlabel = \"green:wifi\";\n\t\t\tgpios = <&ath9k 0 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\t};\n\n\n\tusb_vbus: regulator-usb-vbus {\n\t\tcompatible = \"regulator-fixed\";\n\n\t\tregulator-name = \"USB_VBUS\";\n\n\t\tregulator-min-microvolt = <5000000>;\n\t\tregulator-max-microvolt = <5000000>;\n\n\t\tgpio = <&gpio 33 GPIO_ACTIVE_HIGH>;\n\t\tenable-active-high;\n\t};\n};\n\n&eth0 {\n\tnvmem-cells = <&macaddr_ath9k_cal_f100>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&gphy0 {\n\tlantiq,gphy-mode = <GPHY_MODE_GE>;\n};\n\n&gphy1 {\n\tlantiq,gphy-mode = <GPHY_MODE_GE>;\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&state_default>;\n\n\tstate_default: pinmux {\n\t\tphy-rst {\n\t\t\tlantiq,pins = \"io42\";\n\t\t\tlantiq,pull = <0>;\n\t\t\tlantiq,open-drain = <0>;\n\t\t\tlantiq,output = <1>;\n\t\t};\n\t\tpcie-rst {\n\t\t\tlantiq,pins = \"io38\";\n\t\t\tlantiq,pull = <0>;\n\t\t\tlantiq,output = <1>;\n\t\t};\n\t};\n};\n\n&gswip {\n\tpinctrl-0 = <&mdio_pins>, <&gphy0_led1_pins>, <&gphy1_led1_pins>;\n\tpinctrl-names = \"default\";\n};\n\n&gswip_mdio {\n\tphy0: ethernet-phy@0 {\n\t\treg = <0x0>;\n\t\t// reset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>;\n\t};\n\tphy5: ethernet-phy@5 {\n\t\treg = <0x5>;\n\t};\n\tphy11: ethernet-phy@11 {\n\t\treg = <0x11>;\n\t};\n\tphy13: ethernet-phy@13 {\n\t\treg = <0x13>;\n\t};\n};\n\n&gswip_ports {\n\tport@0 {\n\t\treg = <0>;\n\t\tlabel = \"lan2\";\n\t\tphy-mode = \"rgmii\";\n\t\tphy-handle = <&phy0>;\n\t};\n\tport@2 {\n\t\treg = <2>;\n\t\tlabel = \"lan3\";\n\t\tphy-mode = \"internal\";\n\t\tphy-handle = <&phy11>;\n\t};\n\tport@4 {\n\t\treg = <4>;\n\t\tlabel = \"lan4\";\n\t\tphy-mode = \"internal\";\n\t\tphy-handle = <&phy13>;\n\t};\n\tport@5 {\n\t\treg = <5>;\n\t\tlabel = \"lan1\";\n\t\tphy-mode = \"rgmii\";\n\t\tphy-handle = <&phy5>;\n\t};\n};\n\n&pcie0 {\n\tpcie@0 {\n\t\treg = <0 0 0 0 0>;\n\t\t#interrupt-cells = <1>;\n\t\t#size-cells = <2>;\n\t\t#address-cells = <3>;\n\t\tdevice_type = \"pci\";\n\n\t\tath9k: wifi@168c,002e {\n\t\t\tcompatible = \"pci168c,002e\";\n\t\t\treg = <0 0 0 0 0>;\n\t\t\t#gpio-cells = <2>;\n\t\t\tgpio-controller;\n\t\t\tqca,no-eeprom;\n\t\t\tieee80211-freq-limit = <2402000 2482000>;\n\t\t\tnvmem-cells = <&macaddr_ath9k_cal_f100>;\n\t\t\tnvmem-cell-names = \"mac-address\";\n\t\t\tmac-address-increment = <2>;\n\t\t};\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@4 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <4>;\n\t\tspi-max-frequency = <33250000>;\n\t\tm25p,fast-read;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\treg = <0x0 0x20000>;\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\treg = <0x20000 0x7a0000>;\n\t\t\t\tlabel = \"firmware\";\n\t\t\t};\n\n\t\t\tpartition@7c0000 {\n\t\t\t\treg = <0x7c0000 0x10000>;\n\t\t\t\tlabel = \"config\";\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tath9k_cal: partition@7d0000 {\n\t\t\t\treg = <0x7d0000 0x30000>;\n\t\t\t\tlabel = \"boardconfig\";\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&usb_phy0 {\n\tstatus = \"okay\";\n};\n\n&usb_phy1 {\n\tstatus = \"okay\";\n};\n\n&usb0 {\n\tstatus = \"okay\";\n\tvbus-supply = <&usb_vbus>;\n};\n\n&usb1 {\n\tstatus = \"okay\";\n\tvbus-supply = <&usb_vbus>;\n};\n\n&ath9k_cal {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_ath9k_cal_f100: macaddr@f100 {\n\t\treg = <0xf100 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_tplink_vr200.dts",
    "content": "#include \"vr9_tplink_vr200.dtsi\"\n\n/ {\n\tcompatible = \"tplink,vr200\", \"lantiq,xway\", \"lantiq,vr9\";\n\tmodel = \"TP-LINK Archer VR200\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyLTQ0,115200\";\n\t};\n};\n\n&keys {\n\tled {\n\t\tlabel = \"led\";\n\t\tgpios = <&gpio 39 GPIO_ACTIVE_LOW>;\n\t\tlinux,code = <KEY_LIGHTS_TOGGLE>;\n\t};\n};\n\n&leds {\n\twps {\n\t\tlabel = \"blue:wps\";\n\t\tgpios = <&gpio 44 GPIO_ACTIVE_LOW>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_tplink_vr200.dtsi",
    "content": "#include \"vr9.dtsi\"\n\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/mips/lantiq_rcu_gphy.h>\n\n/ {\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\n\t\tled-dsl = &led_dsl;\n\t\tled-internet = &led_internet;\n\t\tled-wifi = &led_wlan5g;\n\t};\n\n\tmemory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x0 0x7f00000>;\n\t};\n\n\tkeys: keys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <100>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twifi {\n\t\t\tlabel = \"wifi\";\n\t\t\tgpios = <&gpio 0 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = <KEY_RFKILL>;\n\t\t\tlinux,input-type = <EV_SW>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio 2 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n\n\tleds: leds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"blue:power\";\n\t\t\tgpios = <&gpio 46 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"keep\";\n\t\t};\n\n\t\tled_dsl: dsl {\n\t\t\tlabel = \"blue:dsl\";\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_internet: internet {\n\t\t\tlabel = \"blue:internet\";\n\t\t\tgpios = <&gpio 5 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tusb {\n\t\t\tlabel = \"blue:usb\";\n\t\t\tgpios = <&gpio 25 GPIO_ACTIVE_LOW>;\n\t\t\ttrigger-sources = <&ehci_port1>, <&ehci_port2>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\n\t\teth {\n\t\t\tlabel = \"blue:lan\";\n\t\t\tgpios = <&gpio 40 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan {\n\t\t\tlabel = \"blue:wlan\";\n\t\t\tgpios = <&gpio 24 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_wlan5g: wifi {\n\t\t\tlabel = \"blue:wlan5g\";\n\t\t\tgpios = <&gpio 20 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tusb_vbus: regulator-usb-vbus {\n\t\tcompatible = \"regulator-fixed\";\n\n\t\tregulator-name = \"USB_VBUS\";\n\n\t\tregulator-min-microvolt = <5000000>;\n\t\tregulator-max-microvolt = <5000000>;\n\n\t\tgpio = <&gpio 33 GPIO_ACTIVE_HIGH>;\n\t\tenable-active-high;\n\t};\n};\n\n&eth0 {\n\tnvmem-cells = <&macaddr_romfile_f100>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&gphy0 {\n\tlantiq,gphy-mode = <GPHY_MODE_GE>;\n};\n\n&gphy1 {\n\tlantiq,gphy-mode = <GPHY_MODE_GE>;\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&state_default>;\n\n\tstate_default: pinmux {\n\t\tphy-rst {\n\t\t\tlantiq,pins = \"io42\";\n\t\t\tlantiq,pull = <0>;\n\t\t\tlantiq,open-drain = <0>;\n\t\t\tlantiq,output = <1>;\n\t\t};\n\t\tpcie-rst {\n\t\t\tlantiq,pins = \"io38\";\n\t\t\tlantiq,pull = <0>;\n\t\t\tlantiq,output = <1>;\n\t\t};\n\t};\n};\n\n&gswip {\n\tpinctrl-0 = <&mdio_pins>, <&gphy0_led1_pins>, <&gphy1_led1_pins>;\n\tpinctrl-names = \"default\";\n};\n\n&gswip_mdio {\n\tphy0: ethernet-phy@0 {\n\t\treg = <0x0>;\n\t\t// reset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>;\n\t};\n\tphy5: ethernet-phy@5 {\n\t\treg = <0x5>;\n\t};\n\tphy11: ethernet-phy@11 {\n\t\treg = <0x11>;\n\t};\n\tphy13: ethernet-phy@13 {\n\t\treg = <0x13>;\n\t};\n};\n\n&gswip_ports {\n\tport@0 {\n\t\treg = <0>;\n\t\tlabel = \"lan3\";\n\t\tphy-mode = \"rgmii\";\n\t\tphy-handle = <&phy0>;\n\t};\n\tport@2 {\n\t\treg = <2>;\n\t\tlabel = \"lan2\";\n\t\tphy-mode = \"internal\";\n\t\tphy-handle = <&phy11>;\n\t};\n\tport@4 {\n\t\treg = <4>;\n\t\tlabel = \"lan1\";\n\t\tphy-mode = \"internal\";\n\t\tphy-handle = <&phy13>;\n\t};\n\tport@5 {\n\t\treg = <5>;\n\t\tlabel = \"lan4\";\n\t\tphy-mode = \"rgmii\";\n\t\tphy-handle = <&phy5>;\n\t};\n};\n\n&pcie0 {\n\tpcie@0 {\n\t\treg = <0 0 0 0 0>;\n\t\t#interrupt-cells = <1>;\n\t\t#size-cells = <2>;\n\t\t#address-cells = <3>;\n\t\tdevice_type = \"pci\";\n\n\t\twifi@0,0 {\n\t\t\treg = <0 0 0 0 0>;\n\t\t\tmediatek,mtd-eeprom = <&radio 0x0000>;\n\t\t\tbig-endian;\n\t\t\tieee80211-freq-limit = <5000000 6000000>;\n\t\t\tnvmem-cells = <&macaddr_romfile_f100>;\n\t\t\tnvmem-cell-names = \"mac-address\";\n\t\t\tmac-address-increment = <2>;\n\t\t};\n\t};\n};\n\n&pci0 {\n\tstatus = \"okay\";\n\tgpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>;\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@4 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <4>;\n\t\tspi-max-frequency = <33250000>;\n\t\tm25p,fast-read;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\treg = <0x0 0x20000>;\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\treg = <0x20000 0xf90000>;\n\t\t\t\tlabel = \"firmware\";\n\t\t\t};\n\n\t\t\tpartition@fb0000 {\n\t\t\t\treg = <0xfb0000 0x10000>;\n\t\t\t\tlabel = \"radioDECT\";\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@fc0000 {\n\t\t\t\treg = <0xfc0000 0x10000>;\n\t\t\t\tlabel = \"config\";\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tromfile: partition@fd0000 {\n\t\t\t\treg = <0xfd0000 0x10000>;\n\t\t\t\tlabel = \"romfile\";\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@fe0000 {\n\t\t\t\treg = <0xfe0000 0x10000>;\n\t\t\t\tlabel = \"rom\";\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tradio: partition@ff0000 {\n\t\t\t\treg = <0xff0000 0x10000>;\n\t\t\t\tlabel = \"radio\";\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&usb_phy0 {\n\tstatus = \"okay\";\n};\n\n&usb_phy1 {\n\tstatus = \"okay\";\n};\n\n&usb0 {\n\tstatus = \"okay\";\n\tvbus-supply = <&usb_vbus>;\n};\n\n&usb1 {\n\tstatus = \"okay\";\n\tvbus-supply = <&usb_vbus>;\n};\n\n&romfile {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_romfile_f100: macaddr@f100 {\n\t\treg = <0xf100 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_tplink_vr200v.dts",
    "content": "#include \"vr9_tplink_vr200.dtsi\"\n\n/ {\n\tcompatible = \"tplink,vr200v\", \"lantiq,xway\", \"lantiq,vr9\";\n\tmodel = \"TP-LINK Archer VR200v\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyLTQ0,115200 mem=126M vpe1_load_addr=0x87e00000 vpe1_mem=2M maxvpes=1 maxtcs=1 nosmp\";\n\t};\n};\n\n&keys {\n\tdect_paging {\n\t\tlabel = \"dect_paging\";\n\t\tgpios = <&gpio 39 GPIO_ACTIVE_LOW>;\n\t\tlinux,code = <KEY_PHONE>;\n\t};\n};\n\n&leds {\n\tphone {\n\t\tlabel = \"blue:phone\";\n\t\tgpios = <&gpio 44 GPIO_ACTIVE_LOW>;\n\t};\n};\n\n&vmmc {\n\tstatus = \"okay\";\n\tgpios = <&gpio 30 GPIO_ACTIVE_HIGH  //fxs relay\n\t\t\t &gpio 31 GPIO_ACTIVE_HIGH  //still unknown\n\t\t\t &gpio 3  GPIO_ACTIVE_HIGH>; //reset_slic?\n};\n"
  },
  {
    "path": "target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_zyxel_p-2812hnu-f1.dts",
    "content": "#include \"vr9_zyxel_p-2812hnu-fx.dtsi\"\n\n/ {\n\tcompatible = \"zyxel,p-2812hnu-f1\", \"zyxel,p-2812hnu\", \"lantiq,xway\", \"lantiq,vr9\";\n\tmodel = \"ZyXEL P-2812HNU-F1\";\n\n\tleds {\n\t\tusb1 {\n\t\t\tlabel = \"green:usb1\";\n\t\t\tgpios = <&gpio 38 GPIO_ACTIVE_LOW>;\n\t\t\ttrigger-sources = <&ehci_port1>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\t\tusb2 {\n\t\t\tlabel = \"green:usb2\";\n\t\t\tgpios = <&gpio 44 GPIO_ACTIVE_LOW>;\n\t\t\ttrigger-sources = <&ehci_port2>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\t};\n};\n\n&localbus {\n\tflash@0 {\n\t\tcompatible = \"lantiq,nand-xway\";\n\t\tlantiq,cs = <1>;\n\t\tbank-width = <2>;\n\t\treg = <0 0x0 0x2000000>;\n\n\t\tpinctrl-0 = <&nand_pins>, <&nand_cs1_pins>;\n\t\tpinctrl-names = \"default\";\n\n\t\tnand-use-soft-ecc-engine;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"uboot\";\n\t\t\t\treg = <0x00000 0x40000>;\n\t\t\t};\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x40000 0x20000>;\n\t\t\t};\n\t\t\tpartition@60000 {\n\t\t\t\tlabel = \"kernel\";\n\t\t\t\treg = <0x60000 0x300000>;\n\t\t\t};\n\t\t\tpartition@360000 {\n\t\t\t\tlabel = \"ubi\";\n\t\t\t\treg = <0x360000 0x7ca0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pci0 {\n\twifi@1814,3062 {\n\t\tcompatible = \"pci1814,3062\";\n\t\treg = <0x7000 0 0 0 0>;\n\t\tralink,eeprom = \"RT3062.eeprom\";\n\t};\n};\n\n&pcie0 {\n\tstatus = \"disabled\";\n};\n"
  },
  {
    "path": "target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_zyxel_p-2812hnu-f3.dts",
    "content": "#include \"vr9_zyxel_p-2812hnu-fx.dtsi\"\n\n/ {\n\tcompatible = \"zyxel,p-2812hnu-f3\", \"zyxel,p-2812hnu\", \"lantiq,xway\", \"lantiq,vr9\";\n\tmodel = \"ZyXEL P-2812HNU-F3\";\n};\n\n&pci0 {\n\twifi@1814,3092 {\n\t\tcompatible = \"pci1814,3092\";\n\t\treg = <0x7000 0 0 0 0>;\n\t\tralink,eeprom = \"RT3092.eeprom\";\n\t};\n};\n\n&localbus {\n\tflash@0 {\n\t\tcompatible = \"lantiq,nor\";\n\t\tbank-width = <2>;\n\t\treg = <0 0x0 0x800000>;\n\n\t\tpinctrl-0 = <&nand_pins>, <&nand_cs1_pins>;\n\t\tpinctrl-names = \"default\";\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"uboot\";\n\t\t\t\treg = <0x0 0x50000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@50000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x50000 0x10000>;\n\t\t\t};\n\t\t\tpartition@60000 {\n\t\t\t\tlabel = \"unused\";\n\t\t\t\treg = <0x60000 0x7a0000>;\n\t\t\t};\n\t\t};\n\t};\n\n\tflash@1 {\n\t\tcompatible = \"lantiq,nand-xway\";\n\t\tlantiq,cs = <1>;\n\t\tbank-width = <2>;\n\t\treg = <1 0x0 0x2000000>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tnand-use-soft-ecc-engine;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"kernel\";\n\t\t\treg = <0x0 0x200000>;\n\t\t};\n\t\tpartition@200000 {\n\t\t\tlabel = \"ubi\";\n\t\t\treg = <0x200000 0x7e00000>;\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_zyxel_p-2812hnu-fx.dtsi",
    "content": "#include \"vr9.dtsi\"\n\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/mips/lantiq_rcu_gphy.h>\n\n/ {\n\tcompatible = \"zyxel,p-2812hnu\", \"lantiq,xway\", \"lantiq,vr9\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyLTQ0,115200\";\n\t};\n\n\taliases {\n\t\tled-boot = &power_green;\n\t\tled-failsafe = &power_red;\n\t\tled-running = &power_green;\n\t\tled-upgrade = &power_green;\n\n\t\tled-dsl = &dsl_green;\n\t\tled-internet = &internet_green;\n\t\tled-wifi = &wireless_green;\n\t};\n\n\tmemory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x0 0x8000000>;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <100>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 39 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\trfkill {\n\t\t\tlabel = \"rfkill\";\n\t\t\tgpios = <&gpio 1 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RFKILL>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tinternet_red {\n\t\t\tlabel = \"red:internet\";\n\t\t\tgpios = <&stp 16 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tinternet_green: internet_green {\n\t\t\tlabel = \"green:internet\";\n\t\t\tgpios = <&stp 17 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tdsl_green: dsl_green {\n\t\t\tlabel = \"green:dsl\";\n\t\t\tgpios = <&stp 18 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tdsl_orange {\n\t\t\tlabel = \"orange:dsl\";\n\t\t\tgpios = <&stp 19 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\twireless_orange {\n\t\t\tlabel = \"orange:wlan\";\n\t\t\tgpios = <&stp 20 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\twireless_green: wireless_green {\n\t\t\tlabel = \"green:wlan\";\n\t\t\tgpios = <&stp 21 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tpower_red: power {\n\t\t\tlabel = \"red:power\";\n\t\t\tgpios = <&stp 22 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tpower_green: power2 {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&stp 23 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"keep\";\n\t\t};\n\t\tphone1 {\n\t\t\tlabel = \"green:phone\";\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tphone1warn {\n\t\t\tlabel = \"orange:phone\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tphone2warn {\n\t\t\tlabel = \"orange:phone2\";\n\t\t\tgpios = <&gpio 26 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tphone2 {\n\t\t\tlabel = \"green:phone2\";\n\t\t\tgpios = <&gpio 28 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tusb_vbus: regulator-usb-vbus {\n\t\tcompatible = \"regulator-fixed\";\n\n\t\tregulator-name = \"USB_VBUS\";\n\n\t\tregulator-min-microvolt = <5000000>;\n\t\tregulator-max-microvolt = <5000000>;\n\n\t\tgpio = <&gpio 33 GPIO_ACTIVE_HIGH>;\n\t\tenable-active-high;\n\t};\n};\n\n&gphy0 {\n\tlantiq,gphy-mode = <GPHY_MODE_GE>;\n};\n\n&gphy1 {\n\tlantiq,gphy-mode = <GPHY_MODE_GE>;\n};\n\n&gpio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&state_default>;\n\n\tstate_default: pinmux {\n\t\texin3 {\n\t\t\tlantiq,groups = \"exin3\";\n\t\t\tlantiq,function = \"exin\";\n\t\t};\n\t\tpci_rst {\n\t\t\tlantiq,pins = \"io21\";\n\t\t\tlantiq,output = <1>;\n\t\t\tlantiq,open-drain = <0>;\n\t\t\tlantiq,pull = <2>;\n\t\t};\n\t\tpcie-rst {\n\t\t\tlantiq,pins = \"io38\";\n\t\t\tlantiq,pull = <0>;\n\t\t\tlantiq,output = <1>;\n\t\t};\n\t\tifxhcd-rst {\n\t\t\tlantiq,pins = \"io33\";\n\t\t\tlantiq,pull = <0>;\n\t\t\tlantiq,open-drain = <0>;\n\t\t\tlantiq,output = <1>;\n\t\t};\n\t};\n};\n\n&gswip {\n\tpinctrl-0 = <&mdio_pins>,\n\t\t    <&gphy0_led1_pins>, <&gphy0_led2_pins>,\n\t\t    <&gphy1_led1_pins>, <&gphy1_led2_pins>;\n\tpinctrl-names = \"default\";\n};\n\n&gswip_mdio {\n\tphy0: ethernet-phy@0 {\n\t\treg = <0x0>;\n\t};\n\tphy1: ethernet-phy@1 {\n\t\treg = <0x1>;\n\t};\n\tphy5: ethernet-phy@5 {\n\t\treg = <0x5>;\n\t};\n\tphy11: ethernet-phy@11 {\n\t\treg = <0x11>;\n\t};\n\tphy13: ethernet-phy@13 {\n\t\treg = <0x13>;\n\t};\n};\n\n&gswip_ports {\n\tport@0 {\n\t\treg = <0>;\n\t\tlabel = \"lan1\";\n\t\tphy-mode = \"rgmii\";\n\t\tphy-handle = <&phy0>;\n\t};\n\tport@1 {\n\t\treg = <1>;\n\t\tlabel = \"lan2\";\n\t\tphy-mode = \"rgmii\";\n\t\tphy-handle = <&phy1>;\n\t};\n\tport@2 {\n\t\treg = <2>;\n\t\tlabel = \"lan3\";\n\t\tphy-mode = \"internal\";\n\t\tphy-handle = <&phy11>;\n\t};\n\tport@4 {\n\t\treg = <4>;\n\t\tlabel = \"lan4\";\n\t\tphy-mode = \"internal\";\n\t\tphy-handle = <&phy13>;\n\t};\n\tport@5 {\n\t\treg = <5>;\n\t\tlabel = \"wan\";\n\t\tphy-mode = \"rgmii\";\n\t\tphy-handle = <&phy5>;\n\t};\n};\n\n&pci0 {\n\tstatus = \"okay\";\n\n\tpinctrl-0 = <&pci_gnt1_pins>, <&pci_req1_pins>;\n\tpinctrl-names = \"default\";\n\n\tgpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>;\n};\n\n&stp {\n\tstatus = \"okay\";\n};\n\n&usb_phy0 {\n\tstatus = \"okay\";\n};\n\n&usb_phy1 {\n\tstatus = \"okay\";\n};\n\n&usb0 {\n\tstatus = \"okay\";\n\tvbus-supply = <&usb_vbus>;\n};\n\n&usb1 {\n\tstatus = \"okay\";\n\tvbus-supply = <&usb_vbus>;\n};\n"
  },
  {
    "path": "target/linux/lantiq/image/Makefile",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2010-2016 OpenWrt.org\n\n# boards missing since devicetree update\n#EASY50712 ARV3527P\n\nKERNEL_LOADADDR = 0x80002000\nKERNEL_ENTRY = 0x80002000\n\ninclude $(TOPDIR)/rules.mk\ninclude $(INCLUDE_DIR)/image.mk\n\nifeq ($(SUBTARGET),xway)\n\tUBIFS_OPTS := -m 512 -e 15872 -c 1959\nelse\n\tUBIFS_OPTS := -m 2048 -e 126KiB -c 4096\nendif\n\ndefine Build/append-avm-fakeroot\n\tcat ./eva.dummy.squashfs >> $@\nendef\n\ndefine Build/dgn3500-sercom-footer\n\t$(STAGING_DIR_HOST)/bin/dgn3500sum $@ $(1) $(2)\nendef\n\ndefine Build/mkbrncmdline\n\tmkbrncmdline -i $@ -o $@.new BRN-BOOT\n\tmv $@.new $@\nendef\n\ndefine Build/mkbrnimg\n\tmkbrnimg -s $(SIGNATURE) -m $(MAGIC) -p $(CRC32_POLY) -o $@ $(IMAGE_KERNEL) $(IMAGE_ROOTFS)\nendef\n\ndefine Build/fullimage\n\tmkimage -A mips -O linux -C lzma -T filesystem -a 0x00  \\\n\t\t-e 0x00 -n '$(VERSION_DIST) RootFS' \\\n\t\t-d $(IMAGE_ROOTFS) $(IMAGE_ROOTFS).new\n\n\tcat $(IMAGE_KERNEL) $(IMAGE_ROOTFS).new > $@.tmp\n\n\tmkimage -A mips -O linux -T multi -a 0x00 -C none \\\n\t\t-e 0x00 -n 'OpenWrt fullimage' \\\n\t\t-d $@.tmp $@\n\n\trm $(IMAGE_ROOTFS).new\n\trm $@.tmp\nendef\n\ndefine Build/loader-okli-compile\n\trm -rf $@.src\n\t$(MAKE) -C lzma-loader \\\n\t\tPKG_BUILD_DIR=\"$@.src\" \\\n\t\tTARGET_DIR=\"$(dir $@)\" LOADER_NAME=\"$(notdir $@)\" \\\n\t\tPLATFORM=\"lantiq\" \\\n\t\tLZMA_TEXT_START=0x82000000 \\\n\t\tLOADADDR=0x80002000 \\\n\t\tFLASH_START=0x10000000 \\\n\t\tFLASH_OFFS=$(LOADER_FLASH_OFFS) \\\n\t\tFLASH_MAX=0x0 \\\n\t\t$(1) compile loader.bin\n\tmv \"$@.bin\" \"$@\"\n\trm -rf $@.src\nendef\n\ndefine Build/prepend-loader-okli\n\tcat \"$(KDIR)/loader-$(word 1,$(1)).bin\" \"$@\" >> \"$@.new\"\n\tmv \"$@.new\" \"$@\"\nendef\n\nDEVICE_VARS += SIGNATURE MAGIC CRC32_POLY LOADER_FLASH_OFFS\n\nDTS_DIR := $(DTS_DIR)/lantiq\n\n# Shared device definition: applies to every defined device\ndefine Device/Default\n  PROFILES = Default\n  COMPILE :=\n  KERNEL_DEPENDS = $$(wildcard $(DTS_DIR)/$$(DEVICE_DTS).dts)\n  KERNEL_INITRAMFS_NAME = $$(KERNEL_NAME)-initramfs\n  KERNEL := kernel-bin | append-dtb | lzma | uImage lzma\n  KERNEL_INITRAMFS := kernel-bin | append-dtb | lzma | uImage lzma\n  FILESYSTEMS := squashfs\n  SOC := $(DEFAULT_SOC)\n  DEVICE_DTS = $$(SOC)_$(1)\n  IMAGES := sysupgrade.bin\n  IMAGE/sysupgrade.bin := append-kernel | append-rootfs | pad-rootfs | check-size | append-metadata\nendef\n\ndefine Device/NAND/xway\n  BLOCKSIZE := 16k\n  PAGESIZE := 512\n  SUBPAGESIZE := 256\n  FILESYSTEMS += ubifs\nendef\n\ndefine Device/NAND/xrx200\n  BLOCKSIZE := 128k\n  PAGESIZE := 2048\n  SUBPAGESIZE := 512\n  FILESYSTEMS += ubifs\nendef\n\ndefine Device/NAND\n  $(Device/NAND/$(SUBTARGET))\n  IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata\nendef\n\ndefine Device/lantiqBrnImage\n  KERNEL := kernel-bin | append-dtb | mkbrncmdline | lzma-no-dict\n  IMAGES := factory.bin\n  IMAGE/factory.bin := mkbrnimg | check-size\nendef\n\ndefine Device/lantiqFullImage\n  KERNEL := kernel-bin | append-dtb | lzma | uImage lzma | pad-offset 4 0\n  IMAGES := sysupgrade.bin fullimage.bin\n  IMAGE/fullimage.bin := fullimage | check-size\nendef\n\ndefine Device/AVM\n  DEVICE_VENDOR := AVM\n  KERNEL := kernel-bin | append-dtb | lzma | eva-image\n  KERNEL_INITRAMFS := $$(KERNEL)\n  IMAGE/sysupgrade.bin := append-kernel | pad-to 64k | append-avm-fakeroot | \\\n\tappend-rootfs | pad-rootfs | check-size | append-metadata\nendef\n\ndefine Device/AVM_preloader\n  DEVICE_VENDOR := AVM\n  COMPILE := loader-$(1).bin\n  COMPILE/loader-$(1).bin := loader-okli-compile | lzma | eva-image | \\\n\tpad-to 64k | append-avm-fakeroot | pad-to 4k\n  KERNEL := kernel-bin | append-dtb | lzma | uImage lzma -M 0x4f4b4c49 | \\\n\tprepend-loader-okli $(1)\n  KERNEL_INITRAMFS := kernel-bin | append-dtb | lzma | eva-image\nendef\n\nifeq ($(SUBTARGET),ase)\nDEFAULT_SOC := amazonse\ninclude amazonse.mk\nendif\n\nifeq ($(SUBTARGET),xway_legacy)\nDEFAULT_SOC := danube\ninclude xway_legacy.mk\nendif\n\nifeq ($(SUBTARGET),xway)\ninclude danube.mk\ninclude ar9.mk\nendif\n\nifeq ($(SUBTARGET),xrx200)\nDEFAULT_SOC := vr9\ninclude tp-link.mk\ninclude vr9.mk\nendif\n\nifeq ($(SUBTARGET),falcon)\nDEFAULT_SOC := falcon\ninclude falcon.mk\nendif\n\n$(eval $(call BuildImage))\n"
  },
  {
    "path": "target/linux/lantiq/image/amazonse.mk",
    "content": "define Device/allnet_all0333cj\n  DEVICE_VENDOR := Allnet\n  DEVICE_MODEL := ALL0333CJ\n  IMAGE_SIZE := 3700k\n  DEVICE_PACKAGES := kmod-ltq-adsl-ase kmod-ltq-adsl-ase-mei \\\n\tkmod-ltq-adsl-ase-fw-b kmod-ltq-atm-ase \\\n\tltq-adsl-app ppp-mod-pppoe\n  DEFAULT := n\nendef\nTARGET_DEVICES += allnet_all0333cj\n\ndefine Device/netgear_dgn1000b\n  DEVICE_VENDOR := NETGEAR\n  DEVICE_MODEL := DGN1000B\n  IMAGE_SIZE := 3712k\n  DEVICE_PACKAGES := kmod-ltq-adsl-ase kmod-ltq-adsl-ase-mei \\\n\tkmod-ltq-adsl-ase-fw-b kmod-ltq-atm-ase \\\n\tltq-adsl-app ppp-mod-pppoe\n  SUPPORTED_DEVICES += DGN1000B\n  DEFAULT := n\nendef\nTARGET_DEVICES += netgear_dgn1000b\n"
  },
  {
    "path": "target/linux/lantiq/image/ar9.mk",
    "content": "define Device/avm_fritz7312\n  $(Device/AVM_preloader)\n  DEVICE_MODEL := FRITZ!Box 7312\n  SOC := ar9\n  IMAGE_SIZE := 15744k\n  LOADER_FLASH_OFFS := 0x31000\n  DEVICE_PACKAGES := kmod-ath9k kmod-owl-loader wpad-basic-wolfssl \\\n\tkmod-ltq-adsl-ar9-mei kmod-ltq-adsl-ar9 \\\n\tkmod-ltq-adsl-ar9-fw-b kmod-ltq-atm-ar9 \\\n\tltq-adsl-app ppp-mod-pppoa \\\n\tkmod-ltq-deu-ar9 -swconfig\nendef\nTARGET_DEVICES += avm_fritz7312\n\ndefine Device/avm_fritz7320\n  $(Device/AVM_preloader)\n  DEVICE_MODEL := FRITZ!Box 7320\n  DEVICE_ALT0_VENDOR := 1&1\n  DEVICE_ALT0_MODEL := HomeServer\n  SOC := ar9\n  IMAGE_SIZE := 15744k\n  LOADER_FLASH_OFFS := 0x31000\n  DEVICE_PACKAGES := kmod-ath9k kmod-owl-loader wpad-basic-wolfssl \\\n\tkmod-ltq-adsl-ar9-mei kmod-ltq-adsl-ar9 \\\n\tkmod-ltq-adsl-ar9-fw-b kmod-ltq-atm-ar9 \\\n\tltq-adsl-app ppp-mod-pppoa \\\n\tkmod-ltq-deu-ar9 kmod-usb-dwc2 -swconfig\n  SUPPORTED_DEVICES += FRITZ7320\nendef\nTARGET_DEVICES += avm_fritz7320\n\ndefine Device/bt_homehub-v3a\n  $(Device/NAND)\n  DEVICE_VENDOR := British Telecom (BT)\n  DEVICE_MODEL := Home Hub 3\n  DEVICE_VARIANT := Type A\n  BOARD_NAME := BTHOMEHUBV3A\n  SOC := ar9\n  KERNEL_SIZE := 2048k\n  DEVICE_PACKAGES := kmod-usb-dwc2 \\\n\tkmod-ltq-adsl-ar9-mei kmod-ltq-adsl-ar9 \\\n\tkmod-ltq-adsl-ar9-fw-a kmod-ltq-atm-ar9 \\\n\tkmod-ltq-deu-ar9 \\\n\tltq-adsl-app ppp-mod-pppoa \\\n\tkmod-ath9k kmod-owl-loader wpad-basic-wolfssl \\\n\tuboot-envtools\n  SUPPORTED_DEVICES += BTHOMEHUBV3A\n  DEFAULT := n\nendef\nTARGET_DEVICES += bt_homehub-v3a\n\ndefine Device/buffalo_wbmr-hp-g300h-a\n  DEVICE_VENDOR := Buffalo\n  DEVICE_MODEL := WBMR-HP-G300H\n  DEVICE_VARIANT := A\n  IMAGE_SIZE := 31488k\n  SOC := ar9\n  DEVICE_DTS := ar9_buffalo_wbmr-hp-g300h\n  DEVICE_PACKAGES := kmod-usb-dwc2 kmod-usb-ledtrig-usbport \\\n\tkmod-ltq-adsl-ar9-mei kmod-ltq-adsl-ar9 \\\n\tkmod-ltq-adsl-ar9-fw-a kmod-ltq-atm-ar9 \\\n\tltq-adsl-app ppp-mod-pppoa \\\n\tkmod-ath9k kmod-owl-loader wpad-basic-wolfssl\n  SUPPORTED_DEVICES := WBMR buffalo,wbmr-hp-g300h\nendef\nTARGET_DEVICES += buffalo_wbmr-hp-g300h-a\n\ndefine Device/buffalo_wbmr-hp-g300h-b\n  DEVICE_VENDOR := Buffalo\n  DEVICE_MODEL := WBMR-HP-G300H\n  DEVICE_VARIANT := B\n  IMAGE_SIZE := 31488k\n  SOC := ar9\n  DEVICE_DTS := ar9_buffalo_wbmr-hp-g300h\n  DEVICE_PACKAGES := kmod-usb-dwc2 kmod-usb-ledtrig-usbport \\\n\tkmod-ltq-adsl-ar9-mei kmod-ltq-adsl-ar9 \\\n\tkmod-ltq-adsl-ar9-fw-b kmod-ltq-atm-ar9 \\\n\tltq-adsl-app ppp-mod-pppoa \\\n\tkmod-ath9k kmod-owl-loader wpad-basic-wolfssl\n  SUPPORTED_DEVICES := WBMR buffalo,wbmr-hp-g300h\nendef\nTARGET_DEVICES += buffalo_wbmr-hp-g300h-b\n\nDGN3500_KERNEL_OFFSET_HEX=0x50000\nDGN3500_KERNEL_OFFSET_DEC=327680\ndefine Device/netgear_dgn3500\n  DEVICE_VENDOR := NETGEAR\n  DEVICE_MODEL := DGN3500\n  SOC := ar9\n  IMAGE_SIZE := 16000k\n  IMAGES := \\\n\tsysupgrade-na.bin sysupgrade.bin \\\n\tfactory-na.img factory.img\n  IMAGE/sysupgrade-na.bin := \\\n\tappend-kernel | append-rootfs | dgn3500-sercom-footer 0x0 \"NA\" | \\\n\tpad-rootfs | check-size | append-metadata\n  IMAGE/sysupgrade.bin := \\\n\tappend-kernel | append-rootfs | dgn3500-sercom-footer 0x0 \"WW\" | \\\n\tpad-rootfs | check-size | append-metadata\n  IMAGE/factory-na.img := \\\n\tpad-extra $(DGN3500_KERNEL_OFFSET_DEC) | append-kernel | append-rootfs | \\\n\tdgn3500-sercom-footer $(DGN3500_KERNEL_OFFSET_HEX) \"NA\" | pad-rootfs | \\\n\tcheck-size 16320k | pad-to 16384k\n  IMAGE/factory.img := \\\n\tpad-extra $(DGN3500_KERNEL_OFFSET_DEC) | append-kernel | append-rootfs | \\\n\tdgn3500-sercom-footer $(DGN3500_KERNEL_OFFSET_HEX) \"WW\" | pad-rootfs | \\\n\tcheck-size 16320k | pad-to 16384k\n  DEVICE_PACKAGES := kmod-usb-dwc2 kmod-usb-ledtrig-usbport \\\n\tkmod-ath9k kmod-owl-loader wpad-basic-wolfssl \\\n\tkmod-ltq-adsl-ar9-mei kmod-ltq-adsl-ar9 \\\n\tkmod-ltq-adsl-ar9-fw-a kmod-ltq-atm-ar9 \\\n\tkmod-ltq-deu-ar9 ltq-adsl-app ppp-mod-pppoa\n  SUPPORTED_DEVICES += DGN3500\nendef\nTARGET_DEVICES += netgear_dgn3500\n\ndefine Device/netgear_dgn3500b\n  DEVICE_VENDOR := NETGEAR\n  DEVICE_MODEL := DGN3500B\n  SOC := ar9\n  IMAGE_SIZE := 16000k\n  IMAGES += factory.img\n  IMAGE/sysupgrade.bin := \\\n\tappend-kernel | append-rootfs | dgn3500-sercom-footer 0x0 \"DE\" | \\\n\tpad-rootfs | check-size | append-metadata\n  IMAGE/factory.img := \\\n\tpad-extra $(DGN3500_KERNEL_OFFSET_DEC) | append-kernel | append-rootfs | \\\n\tdgn3500-sercom-footer $(DGN3500_KERNEL_OFFSET_HEX) \"DE\" | pad-rootfs | \\\n\tcheck-size 16320k | pad-to 16384k\n  DEVICE_PACKAGES := kmod-usb-dwc2 kmod-usb-ledtrig-usbport \\\n\tkmod-ath9k kmod-owl-loader wpad-basic-wolfssl \\\n\tkmod-ltq-adsl-ar9-mei kmod-ltq-adsl-ar9 \\\n\tkmod-ltq-adsl-ar9-fw-b kmod-ltq-atm-ar9 \\\n\tkmod-ltq-deu-ar9 ltq-adsl-app ppp-mod-pppoa\n  SUPPORTED_DEVICES += DGN3500B\nendef\nTARGET_DEVICES += netgear_dgn3500b\n\ndefine Device/zte_h201l\n  DEVICE_VENDOR := ZTE\n  DEVICE_MODEL := H201L\n  IMAGE_SIZE := 7808k\n  SOC := ar9\n  DEVICE_PACKAGES := kmod-ath9k-htc wpad-basic-wolfssl \\\n\tkmod-ltq-adsl-ar9-mei kmod-ltq-adsl-ar9 \\\n\tkmod-ltq-adsl-ar9-fw-b kmod-ltq-atm-ar9 \\\n\tkmod-ltq-deu-ar9 ltq-adsl-app ppp-mod-pppoe \\\n\tkmod-usb-dwc2 kmod-usb-ledtrig-usbport \\\n\tkmod-ltq-tapi kmod-ltq-vmmc\n  SUPPORTED_DEVICES += H201L\nendef\nTARGET_DEVICES += zte_h201l\n\ndefine Device/zyxel_p-2601hn\n  DEVICE_VENDOR := ZyXEL\n  DEVICE_MODEL := P-2601HN\n  DEVICE_VARIANT := F1/F3\n  IMAGE_SIZE := 15616k\n  SOC := ar9\n  DEVICE_PACKAGES := kmod-rt2800-usb wpad-basic-wolfssl \\\n\tkmod-ltq-adsl-ar9-mei kmod-ltq-adsl-ar9 \\\n\tkmod-ltq-adsl-ar9-fw-b kmod-ltq-atm-ar9 \\\n\tkmod-ltq-deu-ar9 ltq-adsl-app ppp-mod-pppoe \\\n\tkmod-usb-dwc2\n  SUPPORTED_DEVICES += P2601HNFX\nendef\nTARGET_DEVICES += zyxel_p-2601hn\n"
  },
  {
    "path": "target/linux/lantiq/image/danube.mk",
    "content": "define Device/arcadyan_arv4510pw\n  DEVICE_VENDOR := Arcadyan\n  DEVICE_MODEL := ARV4510PW\n  DEVICE_ALT0_VENDOR := Wippies\n  DEVICE_ALT0_MODEL := BeWan iBox v1.0\n  IMAGE_SIZE := 15616k\n  SOC := danube\n  DEVICE_PACKAGES := kmod-usb-ledtrig-usbport kmod-usb2-pci kmod-usb-uhci \\\n\tkmod-ltq-adsl-danube-mei kmod-ltq-adsl-danube \\\n\tkmod-ltq-adsl-danube-fw-a kmod-ltq-atm-danube \\\n\tltq-adsl-app ppp-mod-pppoa \\\n\tkmod-ltq-tapi kmod-ltq-vmmc \\\n\tkmod-rt2800-pci kmod-ath5k wpad-basic-wolfssl\n  SUPPORTED_DEVICES += ARV4510PW\nendef\nTARGET_DEVICES += arcadyan_arv4510pw\n\ndefine Device/arcadyan_arv4519pw\n  DEVICE_VENDOR := Arcadyan\n  DEVICE_MODEL := ARV4519PW\n  DEVICE_ALT0_VENDOR := Vodafone\n  DEVICE_ALT0_MODEL := NetFasteR IAD 2\n  DEVICE_ALT1_VENDOR := Pirelli\n  DEVICE_ALT1_MODEL := P.RG A4201G\n  IMAGE_SIZE := 3776k\n  SOC := danube\n  DEVICE_PACKAGES := kmod-usb-dwc2 kmod-usb-ledtrig-usbport \\\n\tkmod-ltq-adsl-danube-mei kmod-ltq-adsl-danube \\\n\tkmod-ltq-adsl-danube-fw-a kmod-ltq-atm-danube \\\n\tltq-adsl-app ppp-mod-pppoa\n  SUPPORTED_DEVICES += ARV4519PW\n  DEFAULT := n\nendef\nTARGET_DEVICES += arcadyan_arv4519pw\n\ndefine Device/arcadyan_arv7506pw11\n  DEVICE_VENDOR := Arcadyan\n  DEVICE_MODEL := ARV7506PW11\n  DEVICE_ALT0_VENDOR := Alice/O2\n  DEVICE_ALT0_MODEL := IAD 4421\n  IMAGE_SIZE := 7808k\n  SOC := danube\n  DEVICE_PACKAGES := kmod-ltq-adsl-danube-mei kmod-ltq-adsl-danube \\\n\tkmod-ltq-adsl-danube-fw-b kmod-ltq-atm-danube \\\n\tltq-adsl-app ppp-mod-pppoa \\\n\tkmod-rt2800-pci wpad-basic-wolfssl\n  SUPPORTED_DEVICES += ARV7506PW11\nendef\nTARGET_DEVICES += arcadyan_arv7506pw11\n\ndefine Device/arcadyan_arv7510pw22\n  DEVICE_VENDOR := Arcadyan\n  DEVICE_MODEL := ARV7510PW22\n  DEVICE_ALT0_VENDOR := Astoria Networks\n  DEVICE_ALT0_MODEL := ARV7510PW22\n  IMAGE_SIZE := 31232k\n  SOC := danube\n  DEVICE_PACKAGES := kmod-usb-dwc2 kmod-usb-ledtrig-usbport \\\n\tkmod-ltq-adsl-danube-mei kmod-ltq-adsl-danube \\\n\tkmod-ltq-adsl-danube-fw-a kmod-ltq-atm-danube \\\n\tltq-adsl-app ppp-mod-pppoa \\\n\tkmod-ltq-tapi kmod-ltq-vmmc \\\n\tkmod-rt2800-pci wpad-basic-wolfssl \\\n\tkmod-usb-uhci kmod-usb2 kmod-usb2-pci\n  SUPPORTED_DEVICES += ARV7510PW22\nendef\nTARGET_DEVICES += arcadyan_arv7510pw22\n\ndefine Device/arcadyan_arv7518pw\n  DEVICE_VENDOR := Arcadyan\n  DEVICE_MODEL := ARV7518PW\n  DEVICE_ALT0_VENDOR := Astoria Networks\n  DEVICE_ALT0_MODEL := ARV7518PW\n  IMAGE_SIZE := 7872k\n  SOC := danube\n  DEVICE_PACKAGES := kmod-usb-dwc2 kmod-usb-ledtrig-usbport \\\n\tkmod-ltq-adsl-danube-mei kmod-ltq-adsl-danube \\\n\tkmod-ltq-adsl-danube-fw-a kmod-ltq-atm-danube \\\n\tltq-adsl-app ppp-mod-pppoa \\\n\tkmod-ath9k kmod-owl-loader wpad-basic-wolfssl\n  SUPPORTED_DEVICES += ARV7518PW\nendef\nTARGET_DEVICES += arcadyan_arv7518pw\n\ndefine Device/arcadyan_arv7519pw\n  DEVICE_VENDOR := Arcadyan\n  DEVICE_MODEL := ARV7519PW\n  DEVICE_ALT0_VENDOR := Astoria Networks\n  DEVICE_ALT0_MODEL := ARV7519PW\n  IMAGE_SIZE := 15488k\n  SOC := danube\n  DEVICE_PACKAGES := kmod-usb-dwc2 \\\n\tkmod-ltq-adsl-danube-mei kmod-ltq-adsl-danube \\\n\tkmod-ltq-adsl-danube-fw-a kmod-ltq-atm-danube \\\n\tltq-adsl-app ppp-mod-pppoa \\\n\tkmod-rt2800-pci wpad-basic-wolfssl\n  SUPPORTED_DEVICES += ARV7519PW\nendef\nTARGET_DEVICES += arcadyan_arv7519pw\n\ndefine Device/arcadyan_arv7525pw\n  DEVICE_VENDOR := Arcadyan\n  DEVICE_MODEL := ARV7525PW\n  DEVICE_ALT0_VENDOR := Telekom\n  DEVICE_ALT0_MODEL := Speedport W303V\n  DEVICE_ALT0_VARIANT := Typ A\n  IMAGE_SIZE := 3776k\n  SOC := danube\n  DEVICE_PACKAGES := kmod-rt2800-pci wpad-basic-wolfssl \\\n\tkmod-ltq-adsl-danube-mei kmod-ltq-adsl-danube \\\n\tkmod-ltq-adsl-danube-fw-b kmod-ltq-atm-danube \\\n\tltq-adsl-app ppp-mod-pppoa -swconfig\n  SUPPORTED_DEVICES += ARV4510PW\n  DEFAULT := n\nendef\nTARGET_DEVICES += arcadyan_arv7525pw\n\ndefine Device/arcadyan_arv752dpw\n  DEVICE_VENDOR := Arcadyan\n  DEVICE_MODEL := ARV752DPW\n  DEVICE_ALT0_VENDOR := Vodafone\n  DEVICE_ALT0_MODEL := Easybox 802\n  IMAGE_SIZE := 7872k\n  SOC := danube\n  DEVICE_PACKAGES := kmod-usb-dwc2 kmod-usb-ledtrig-usbport \\\n\tkmod-ltq-adsl-danube-mei kmod-ltq-adsl-danube \\\n\tkmod-ltq-adsl-danube-fw-b kmod-ltq-atm-danube \\\n\tltq-adsl-app ppp-mod-pppoa \\\n\tkmod-ltq-tapi kmod-ltq-vmmc \\\n\tkmod-rt2800-pci wpad-basic-wolfssl\n  SUPPORTED_DEVICES += ARV752DPW\nendef\nTARGET_DEVICES += arcadyan_arv752dpw\n\ndefine Device/arcadyan_arv752dpw22\n  DEVICE_VENDOR := Arcadyan\n  DEVICE_MODEL := ARV752DPW22\n  DEVICE_ALT0_VENDOR := Vodafone\n  DEVICE_ALT0_MODEL := Easybox 803\n  IMAGE_SIZE := 7616k\n  SOC := danube\n  DEVICE_PACKAGES := kmod-usb2-pci kmod-usb-uhci kmod-usb-dwc2 kmod-usb-ledtrig-usbport \\\n\tkmod-ltq-adsl-danube-mei kmod-ltq-adsl-danube \\\n\tkmod-ltq-adsl-danube-fw-b kmod-ltq-atm-danube \\\n\tltq-adsl-app ppp-mod-pppoa \\\n\tkmod-ltq-tapi kmod-ltq-vmmc \\\n\tkmod-rt2800-pci wpad-basic-wolfssl\n  SUPPORTED_DEVICES += ARV752DPW22\nendef\nTARGET_DEVICES += arcadyan_arv752dpw22\n\ndefine Device/arcadyan_arv8539pw22\n  DEVICE_VENDOR := Arcadyan\n  DEVICE_MODEL := ARV8539PW22\n  DEVICE_ALT0_VENDOR := Telekom\n  DEVICE_ALT0_MODEL := Speedport W504V Typ A\n  IMAGE_SIZE := 7616k\n  SOC := danube\n  DEVICE_PACKAGES := kmod-usb-dwc2 \\\n\tkmod-ltq-adsl-danube-mei kmod-ltq-adsl-danube \\\n\tkmod-ltq-adsl-danube-fw-b kmod-ltq-atm-danube \\\n\tltq-adsl-app ppp-mod-pppoa \\\n\tkmod-ath9k kmod-owl-loader wpad-basic-wolfssl\n  SUPPORTED_DEVICES += ARV8539PW22\nendef\nTARGET_DEVICES += arcadyan_arv8539pw22\n\ndefine Device/audiocodes_mp-252\n  DEVICE_VENDOR := AudioCodes\n  DEVICE_MODEL := MediaPack MP-252\n  IMAGE_SIZE := 14848k\n  SOC := danube\n  DEVICE_PACKAGES :=  kmod-ltq-adsl-danube-mei kmod-ltq-adsl-danube \\\n\tkmod-ltq-adsl-danube-fw-a kmod-ltq-atm-danube \\\n\tkmod-ltq-tapi kmod-ltq-vmmc \\\n\tkmod-usb-ledtrig-usbport kmod-usb-dwc2 \\\n\tkmod-rt2800-pci \\\n\tltq-adsl-app ppp-mod-pppoa \\\n\twpad-basic-wolfssl\n  SUPPORTED_DEVICES += ACMP252\nendef\nTARGET_DEVICES += audiocodes_mp-252\n\ndefine Device/bt_homehub-v2b\n  $(Device/NAND)\n  DEVICE_VENDOR := British Telecom (BT)\n  DEVICE_MODEL := Home Hub 2\n  DEVICE_VARIANT := Type B\n  BOARD_NAME := BTHOMEHUBV2B\n  SOC := danube\n  KERNEL_SIZE := 2048k\n  DEVICE_PACKAGES := kmod-usb-dwc2 \\\n\tkmod-ltq-adsl-danube-mei kmod-ltq-adsl-danube \\\n\tkmod-ltq-adsl-danube-fw-a kmod-ltq-atm-danube \\\n\tkmod-ltq-deu-danube ltq-adsl-app ppp-mod-pppoa \\\n\tkmod-ath9k kmod-owl-loader wpad-basic-wolfssl\n  SUPPORTED_DEVICES += BTHOMEHUBV2B\n  DEFAULT := n\nendef\nTARGET_DEVICES += bt_homehub-v2b\n\ndefine Device/lantiq_easy50712\n  DEVICE_VENDOR := Lantiq\n  DEVICE_MODEL := Danube (EASY50712)\n  SOC := danube\n  IMAGE_SIZE := 3776k\n  DEFAULT := n\nendef\nTARGET_DEVICES += lantiq_easy50712\n\ndefine Device/siemens_gigaset-sx76x\n  DEVICE_VENDOR := Siemens\n  DEVICE_MODEL := Gigaset sx76x\n  IMAGE_SIZE := 7680k\n  SOC := danube\n  DEVICE_PACKAGES := kmod-usb-dwc2 \\\n\tkmod-ltq-adsl-danube-mei kmod-ltq-adsl-danube \\\n\tkmod-ltq-adsl-danube-fw-b kmod-ltq-atm-danube \\\n\tltq-adsl-app ppp-mod-pppoe \\\n\tkmod-ath5k wpad-basic-wolfssl\n  SUPPORTED_DEVICES += GIGASX76X\nendef\nTARGET_DEVICES += siemens_gigaset-sx76x\n"
  },
  {
    "path": "target/linux/lantiq/image/falcon.mk",
    "content": "define Device/lantiq_easy88388\n  DEVICE_VENDOR := Lantiq\n  DEVICE_MODEL := EASY88388 Falcon FTTDP8 Reference Board\n  IMAGE_SIZE := 7424k\nendef\nTARGET_DEVICES += lantiq_easy88388\n\ndefine Device/lantiq_easy88444\n  DEVICE_VENDOR := Lantiq\n  DEVICE_MODEL := EASY88444 Falcon FTTdp G.FAST Reference Board\n  IMAGE_SIZE := 7424k\nendef\nTARGET_DEVICES += lantiq_easy88444\n\ndefine Device/lantiq_easy98020\n  DEVICE_VENDOR := Lantiq\n  DEVICE_MODEL := Falcon SFU Reference Board (EASY98020)\n  DEVICE_VARIANT := v1.0-v1.7\n  IMAGE_SIZE := 7424k\nendef\nTARGET_DEVICES += lantiq_easy98020\n\ndefine Device/lantiq_easy98020-v18\n  DEVICE_VENDOR := Lantiq\n  DEVICE_MODEL := Falcon SFU Reference Board (EASY98020)\n  DEVICE_VARIANT := v1.8\n  IMAGE_SIZE := 7424k\nendef\nTARGET_DEVICES += lantiq_easy98020-v18\n\ndefine Device/lantiq_easy98021\n  DEVICE_VENDOR := Lantiq\n  DEVICE_MODEL := Falcon HGU Reference Board (EASY98021)\n  IMAGE_SIZE := 7424k\nendef\nTARGET_DEVICES += lantiq_easy98021\n\ndefine Device/lantiq_easy98035synce\n  DEVICE_VENDOR := Lantiq\n  DEVICE_MODEL := Falcon SFP Stick (EASY98035SYNCE)\n  DEVICE_VARIANT := with Synchronous Ethernet\n  IMAGE_SIZE := 7424k\nendef\nTARGET_DEVICES += lantiq_easy98035synce\n\ndefine Device/lantiq_easy98035synce1588\n  DEVICE_VENDOR := Lantiq\n  DEVICE_MODEL := Falcon SFP Stick (EASY98035SYNCE1588)\n  DEVICE_VARIANT := with SyncE and IEEE1588\n  IMAGE_SIZE := 7424k\nendef\nTARGET_DEVICES += lantiq_easy98035synce1588\n\ndefine Device/lantiq_easy98000-nand\n  DEVICE_VENDOR := Lantiq\n  DEVICE_MODEL := EASY98000 Falcon Eval Board\n  DEVICE_VARIANT := NAND\n  IMAGE_SIZE := 3904k\n  DEVICE_PACKAGES := kmod-dm9000 kmod-i2c-lantiq kmod-eeprom-at24\n  DEFAULT := n\nendef\nTARGET_DEVICES += lantiq_easy98000-nand\n\ndefine Device/lantiq_easy98000-nor\n  DEVICE_VENDOR := Lantiq\n  DEVICE_MODEL := EASY98000 Falcon Eval Board\n  DEVICE_VARIANT := NOR\n  IMAGE_SIZE := 3904k\n  DEVICE_PACKAGES := kmod-dm9000 kmod-i2c-lantiq kmod-eeprom-at24\n  DEFAULT := n\nendef\nTARGET_DEVICES += lantiq_easy98000-nor\n\ndefine Device/lantiq_easy98000-sflash\n  DEVICE_VENDOR := Lantiq\n  DEVICE_MODEL := EASY98000 Falcon Eval Board\n  DEVICE_VARIANT := SFLASH\n  IMAGE_SIZE := 7424k\n  DEVICE_PACKAGES := kmod-dm9000 kmod-i2c-lantiq kmod-eeprom-at24\nendef\nTARGET_DEVICES += lantiq_easy98000-sflash\n\ndefine Device/lantiq_falcon-mdu\n  DEVICE_VENDOR := Lantiq\n  DEVICE_MODEL := Falcon / VINAXdp MDU Board\n  IMAGE_SIZE := 7424k\nendef\nTARGET_DEVICES += lantiq_falcon-mdu\n\ndefine Device/lantiq_falcon-sfp\n  DEVICE_VENDOR := Lantiq\n  DEVICE_MODEL := Falcon SFP Stick\n  IMAGE_SIZE := 7424k\nendef\nTARGET_DEVICES += lantiq_falcon-sfp\n"
  },
  {
    "path": "target/linux/lantiq/image/lzma-loader/Makefile",
    "content": "#\n# Copyright (C) 2011 OpenWrt.org\n# Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nLZMA_TEXT_START\t:=\nLOADADDR\t:=\nLOADER\t\t:= loader.bin\nLOADER_NAME\t:= $(basename $(notdir $(LOADER)))\nLOADER_DATA \t:=\nKERNEL_MAGIC\t:=\nTARGET_DIR\t:=\nFLASH_START\t:=\nFLASH_OFFS\t:=\nFLASH_MAX\t:=\nBOARD\t\t:=\nPLATFORM\t:=\n\nifeq ($(TARGET_DIR),)\nTARGET_DIR\t:= $(KDIR)\nendif\n\nLOADER_BIN\t:= $(TARGET_DIR)/$(LOADER_NAME).bin\nLOADER_GZ\t:= $(TARGET_DIR)/$(LOADER_NAME).gz\nLOADER_ELF\t:= $(TARGET_DIR)/$(LOADER_NAME).elf\n\nPKG_NAME := lzma-loader\nPKG_BUILD_DIR := $(KDIR)/$(PKG_NAME)\n\n.PHONY : loader-compile loader.bin loader.elf loader.gz\n\n$(PKG_BUILD_DIR)/.prepared:\n\tmkdir $(PKG_BUILD_DIR)\n\t$(CP) ./src/* $(PKG_BUILD_DIR)/\n\ttouch $@\n\nloader-compile: $(PKG_BUILD_DIR)/.prepared\n\t$(MAKE) -C $(PKG_BUILD_DIR) CROSS_COMPILE=\"$(TARGET_CROSS)\" \\\n\t\tLZMA_TEXT_START=$(LZMA_TEXT_START) \\\n\t\tLOADADDR=$(LOADADDR) \\\n\t\tLOADER_DATA=$(LOADER_DATA) \\\n\t\tKERNEL_MAGIC=$(KERNEL_MAGIC) \\\n\t\tFLASH_START=$(FLASH_START) \\\n\t\tFLASH_OFFS=$(FLASH_OFFS) \\\n\t\tFLASH_MAX=$(FLASH_MAX) \\\n\t\tBOARD=\"$(BOARD)\" \\\n\t\tPLATFORM=\"$(PLATFORM)\" \\\n\t\tclean all\n\nloader.gz: $(PKG_BUILD_DIR)/loader.bin\n\tgzip -nc9 $< > $(LOADER_GZ)\n\nloader.elf: $(PKG_BUILD_DIR)/loader.elf\n\t$(CP) $< $(LOADER_ELF)\n\nloader.bin: $(PKG_BUILD_DIR)/loader.bin\n\t$(CP) $< $(LOADER_BIN)\n\ndownload:\nprepare: $(PKG_BUILD_DIR)/.prepared\ncompile: loader-compile\n\ninstall:\n\nclean:\n\trm -rf $(PKG_BUILD_DIR)\n\n"
  },
  {
    "path": "target/linux/lantiq/image/lzma-loader/src/LzmaDecode.c",
    "content": "/*\n  LzmaDecode.c\n  LZMA Decoder (optimized for Speed version)\n  \n  LZMA SDK 4.40 Copyright (c) 1999-2006 Igor Pavlov (2006-05-01)\n  http://www.7-zip.org/\n\n  LZMA SDK is licensed under two licenses:\n  1) GNU Lesser General Public License (GNU LGPL)\n  2) Common Public License (CPL)\n  It means that you can select one of these two licenses and \n  follow rules of that license.\n\n  SPECIAL EXCEPTION:\n  Igor Pavlov, as the author of this Code, expressly permits you to \n  statically or dynamically link your Code (or bind by name) to the \n  interfaces of this file without subjecting your linked Code to the \n  terms of the CPL or GNU LGPL. Any modifications or additions \n  to this file, however, are subject to the LGPL or CPL terms.\n*/\n\n#include \"LzmaDecode.h\"\n\n#define kNumTopBits 24\n#define kTopValue ((UInt32)1 << kNumTopBits)\n\n#define kNumBitModelTotalBits 11\n#define kBitModelTotal (1 << kNumBitModelTotalBits)\n#define kNumMoveBits 5\n\n#define RC_READ_BYTE (*Buffer++)\n\n#define RC_INIT2 Code = 0; Range = 0xFFFFFFFF; \\\n  { int i; for(i = 0; i < 5; i++) { RC_TEST; Code = (Code << 8) | RC_READ_BYTE; }}\n\n#ifdef _LZMA_IN_CB\n\n#define RC_TEST { if (Buffer == BufferLim) \\\n  { SizeT size; int result = InCallback->Read(InCallback, &Buffer, &size); if (result != LZMA_RESULT_OK) return result; \\\n  BufferLim = Buffer + size; if (size == 0) return LZMA_RESULT_DATA_ERROR; }}\n\n#define RC_INIT Buffer = BufferLim = 0; RC_INIT2\n\n#else\n\n#define RC_TEST { if (Buffer == BufferLim) return LZMA_RESULT_DATA_ERROR; }\n\n#define RC_INIT(buffer, bufferSize) Buffer = buffer; BufferLim = buffer + bufferSize; RC_INIT2\n \n#endif\n\n#define RC_NORMALIZE if (Range < kTopValue) { RC_TEST; Range <<= 8; Code = (Code << 8) | RC_READ_BYTE; }\n\n#define IfBit0(p) RC_NORMALIZE; bound = (Range >> kNumBitModelTotalBits) * *(p); if (Code < bound)\n#define UpdateBit0(p) Range = bound; *(p) += (kBitModelTotal - *(p)) >> kNumMoveBits;\n#define UpdateBit1(p) Range -= bound; Code -= bound; *(p) -= (*(p)) >> kNumMoveBits;\n\n#define RC_GET_BIT2(p, mi, A0, A1) IfBit0(p) \\\n  { UpdateBit0(p); mi <<= 1; A0; } else \\\n  { UpdateBit1(p); mi = (mi + mi) + 1; A1; } \n  \n#define RC_GET_BIT(p, mi) RC_GET_BIT2(p, mi, ; , ;)               \n\n#define RangeDecoderBitTreeDecode(probs, numLevels, res) \\\n  { int i = numLevels; res = 1; \\\n  do { CProb *p = probs + res; RC_GET_BIT(p, res) } while(--i != 0); \\\n  res -= (1 << numLevels); }\n\n\n#define kNumPosBitsMax 4\n#define kNumPosStatesMax (1 << kNumPosBitsMax)\n\n#define kLenNumLowBits 3\n#define kLenNumLowSymbols (1 << kLenNumLowBits)\n#define kLenNumMidBits 3\n#define kLenNumMidSymbols (1 << kLenNumMidBits)\n#define kLenNumHighBits 8\n#define kLenNumHighSymbols (1 << kLenNumHighBits)\n\n#define LenChoice 0\n#define LenChoice2 (LenChoice + 1)\n#define LenLow (LenChoice2 + 1)\n#define LenMid (LenLow + (kNumPosStatesMax << kLenNumLowBits))\n#define LenHigh (LenMid + (kNumPosStatesMax << kLenNumMidBits))\n#define kNumLenProbs (LenHigh + kLenNumHighSymbols) \n\n\n#define kNumStates 12\n#define kNumLitStates 7\n\n#define kStartPosModelIndex 4\n#define kEndPosModelIndex 14\n#define kNumFullDistances (1 << (kEndPosModelIndex >> 1))\n\n#define kNumPosSlotBits 6\n#define kNumLenToPosStates 4\n\n#define kNumAlignBits 4\n#define kAlignTableSize (1 << kNumAlignBits)\n\n#define kMatchMinLen 2\n\n#define IsMatch 0\n#define IsRep (IsMatch + (kNumStates << kNumPosBitsMax))\n#define IsRepG0 (IsRep + kNumStates)\n#define IsRepG1 (IsRepG0 + kNumStates)\n#define IsRepG2 (IsRepG1 + kNumStates)\n#define IsRep0Long (IsRepG2 + kNumStates)\n#define PosSlot (IsRep0Long + (kNumStates << kNumPosBitsMax))\n#define SpecPos (PosSlot + (kNumLenToPosStates << kNumPosSlotBits))\n#define Align (SpecPos + kNumFullDistances - kEndPosModelIndex)\n#define LenCoder (Align + kAlignTableSize)\n#define RepLenCoder (LenCoder + kNumLenProbs)\n#define Literal (RepLenCoder + kNumLenProbs)\n\n#if Literal != LZMA_BASE_SIZE\nStopCompilingDueBUG\n#endif\n\nint LzmaDecodeProperties(CLzmaProperties *propsRes, const unsigned char *propsData, int size)\n{\n  unsigned char prop0;\n  if (size < LZMA_PROPERTIES_SIZE)\n    return LZMA_RESULT_DATA_ERROR;\n  prop0 = propsData[0];\n  if (prop0 >= (9 * 5 * 5))\n    return LZMA_RESULT_DATA_ERROR;\n  {\n    for (propsRes->pb = 0; prop0 >= (9 * 5); propsRes->pb++, prop0 -= (9 * 5));\n    for (propsRes->lp = 0; prop0 >= 9; propsRes->lp++, prop0 -= 9);\n    propsRes->lc = prop0;\n    /*\n    unsigned char remainder = (unsigned char)(prop0 / 9);\n    propsRes->lc = prop0 % 9;\n    propsRes->pb = remainder / 5;\n    propsRes->lp = remainder % 5;\n    */\n  }\n\n  #ifdef _LZMA_OUT_READ\n  {\n    int i;\n    propsRes->DictionarySize = 0;\n    for (i = 0; i < 4; i++)\n      propsRes->DictionarySize += (UInt32)(propsData[1 + i]) << (i * 8);\n    if (propsRes->DictionarySize == 0)\n      propsRes->DictionarySize = 1;\n  }\n  #endif\n  return LZMA_RESULT_OK;\n}\n\n#define kLzmaStreamWasFinishedId (-1)\n\nint LzmaDecode(CLzmaDecoderState *vs,\n    #ifdef _LZMA_IN_CB\n    ILzmaInCallback *InCallback,\n    #else\n    const unsigned char *inStream, SizeT inSize, SizeT *inSizeProcessed,\n    #endif\n    unsigned char *outStream, SizeT outSize, SizeT *outSizeProcessed)\n{\n  CProb *p = vs->Probs;\n  SizeT nowPos = 0;\n  Byte previousByte = 0;\n  UInt32 posStateMask = (1 << (vs->Properties.pb)) - 1;\n  UInt32 literalPosMask = (1 << (vs->Properties.lp)) - 1;\n  int lc = vs->Properties.lc;\n\n  #ifdef _LZMA_OUT_READ\n  \n  UInt32 Range = vs->Range;\n  UInt32 Code = vs->Code;\n  #ifdef _LZMA_IN_CB\n  const Byte *Buffer = vs->Buffer;\n  const Byte *BufferLim = vs->BufferLim;\n  #else\n  const Byte *Buffer = inStream;\n  const Byte *BufferLim = inStream + inSize;\n  #endif\n  int state = vs->State;\n  UInt32 rep0 = vs->Reps[0], rep1 = vs->Reps[1], rep2 = vs->Reps[2], rep3 = vs->Reps[3];\n  int len = vs->RemainLen;\n  UInt32 globalPos = vs->GlobalPos;\n  UInt32 distanceLimit = vs->DistanceLimit;\n\n  Byte *dictionary = vs->Dictionary;\n  UInt32 dictionarySize = vs->Properties.DictionarySize;\n  UInt32 dictionaryPos = vs->DictionaryPos;\n\n  Byte tempDictionary[4];\n\n  #ifndef _LZMA_IN_CB\n  *inSizeProcessed = 0;\n  #endif\n  *outSizeProcessed = 0;\n  if (len == kLzmaStreamWasFinishedId)\n    return LZMA_RESULT_OK;\n\n  if (dictionarySize == 0)\n  {\n    dictionary = tempDictionary;\n    dictionarySize = 1;\n    tempDictionary[0] = vs->TempDictionary[0];\n  }\n\n  if (len == kLzmaNeedInitId)\n  {\n    {\n      UInt32 numProbs = Literal + ((UInt32)LZMA_LIT_SIZE << (lc + vs->Properties.lp));\n      UInt32 i;\n      for (i = 0; i < numProbs; i++)\n        p[i] = kBitModelTotal >> 1; \n      rep0 = rep1 = rep2 = rep3 = 1;\n      state = 0;\n      globalPos = 0;\n      distanceLimit = 0;\n      dictionaryPos = 0;\n      dictionary[dictionarySize - 1] = 0;\n      #ifdef _LZMA_IN_CB\n      RC_INIT;\n      #else\n      RC_INIT(inStream, inSize);\n      #endif\n    }\n    len = 0;\n  }\n  while(len != 0 && nowPos < outSize)\n  {\n    UInt32 pos = dictionaryPos - rep0;\n    if (pos >= dictionarySize)\n      pos += dictionarySize;\n    outStream[nowPos++] = dictionary[dictionaryPos] = dictionary[pos];\n    if (++dictionaryPos == dictionarySize)\n      dictionaryPos = 0;\n    len--;\n  }\n  if (dictionaryPos == 0)\n    previousByte = dictionary[dictionarySize - 1];\n  else\n    previousByte = dictionary[dictionaryPos - 1];\n\n  #else /* if !_LZMA_OUT_READ */\n\n  int state = 0;\n  UInt32 rep0 = 1, rep1 = 1, rep2 = 1, rep3 = 1;\n  int len = 0;\n  const Byte *Buffer;\n  const Byte *BufferLim;\n  UInt32 Range;\n  UInt32 Code;\n\n  #ifndef _LZMA_IN_CB\n  *inSizeProcessed = 0;\n  #endif\n  *outSizeProcessed = 0;\n\n  {\n    UInt32 i;\n    UInt32 numProbs = Literal + ((UInt32)LZMA_LIT_SIZE << (lc + vs->Properties.lp));\n    for (i = 0; i < numProbs; i++)\n      p[i] = kBitModelTotal >> 1;\n  }\n  \n  #ifdef _LZMA_IN_CB\n  RC_INIT;\n  #else\n  RC_INIT(inStream, inSize);\n  #endif\n\n  #endif /* _LZMA_OUT_READ */\n\n  while(nowPos < outSize)\n  {\n    CProb *prob;\n    UInt32 bound;\n    int posState = (int)(\n        (nowPos \n        #ifdef _LZMA_OUT_READ\n        + globalPos\n        #endif\n        )\n        & posStateMask);\n\n    prob = p + IsMatch + (state << kNumPosBitsMax) + posState;\n    IfBit0(prob)\n    {\n      int symbol = 1;\n      UpdateBit0(prob)\n      prob = p + Literal + (LZMA_LIT_SIZE * \n        (((\n        (nowPos \n        #ifdef _LZMA_OUT_READ\n        + globalPos\n        #endif\n        )\n        & literalPosMask) << lc) + (previousByte >> (8 - lc))));\n\n      if (state >= kNumLitStates)\n      {\n        int matchByte;\n        #ifdef _LZMA_OUT_READ\n        UInt32 pos = dictionaryPos - rep0;\n        if (pos >= dictionarySize)\n          pos += dictionarySize;\n        matchByte = dictionary[pos];\n        #else\n        matchByte = outStream[nowPos - rep0];\n        #endif\n        do\n        {\n          int bit;\n          CProb *probLit;\n          matchByte <<= 1;\n          bit = (matchByte & 0x100);\n          probLit = prob + 0x100 + bit + symbol;\n          RC_GET_BIT2(probLit, symbol, if (bit != 0) break, if (bit == 0) break)\n        }\n        while (symbol < 0x100);\n      }\n      while (symbol < 0x100)\n      {\n        CProb *probLit = prob + symbol;\n        RC_GET_BIT(probLit, symbol)\n      }\n      previousByte = (Byte)symbol;\n\n      outStream[nowPos++] = previousByte;\n      #ifdef _LZMA_OUT_READ\n      if (distanceLimit < dictionarySize)\n        distanceLimit++;\n\n      dictionary[dictionaryPos] = previousByte;\n      if (++dictionaryPos == dictionarySize)\n        dictionaryPos = 0;\n      #endif\n      if (state < 4) state = 0;\n      else if (state < 10) state -= 3;\n      else state -= 6;\n    }\n    else             \n    {\n      UpdateBit1(prob);\n      prob = p + IsRep + state;\n      IfBit0(prob)\n      {\n        UpdateBit0(prob);\n        rep3 = rep2;\n        rep2 = rep1;\n        rep1 = rep0;\n        state = state < kNumLitStates ? 0 : 3;\n        prob = p + LenCoder;\n      }\n      else\n      {\n        UpdateBit1(prob);\n        prob = p + IsRepG0 + state;\n        IfBit0(prob)\n        {\n          UpdateBit0(prob);\n          prob = p + IsRep0Long + (state << kNumPosBitsMax) + posState;\n          IfBit0(prob)\n          {\n            #ifdef _LZMA_OUT_READ\n            UInt32 pos;\n            #endif\n            UpdateBit0(prob);\n            \n            #ifdef _LZMA_OUT_READ\n            if (distanceLimit == 0)\n            #else\n            if (nowPos == 0)\n            #endif\n              return LZMA_RESULT_DATA_ERROR;\n            \n            state = state < kNumLitStates ? 9 : 11;\n            #ifdef _LZMA_OUT_READ\n            pos = dictionaryPos - rep0;\n            if (pos >= dictionarySize)\n              pos += dictionarySize;\n            previousByte = dictionary[pos];\n            dictionary[dictionaryPos] = previousByte;\n            if (++dictionaryPos == dictionarySize)\n              dictionaryPos = 0;\n            #else\n            previousByte = outStream[nowPos - rep0];\n            #endif\n            outStream[nowPos++] = previousByte;\n            #ifdef _LZMA_OUT_READ\n            if (distanceLimit < dictionarySize)\n              distanceLimit++;\n            #endif\n\n            continue;\n          }\n          else\n          {\n            UpdateBit1(prob);\n          }\n        }\n        else\n        {\n          UInt32 distance;\n          UpdateBit1(prob);\n          prob = p + IsRepG1 + state;\n          IfBit0(prob)\n          {\n            UpdateBit0(prob);\n            distance = rep1;\n          }\n          else \n          {\n            UpdateBit1(prob);\n            prob = p + IsRepG2 + state;\n            IfBit0(prob)\n            {\n              UpdateBit0(prob);\n              distance = rep2;\n            }\n            else\n            {\n              UpdateBit1(prob);\n              distance = rep3;\n              rep3 = rep2;\n            }\n            rep2 = rep1;\n          }\n          rep1 = rep0;\n          rep0 = distance;\n        }\n        state = state < kNumLitStates ? 8 : 11;\n        prob = p + RepLenCoder;\n      }\n      {\n        int numBits, offset;\n        CProb *probLen = prob + LenChoice;\n        IfBit0(probLen)\n        {\n          UpdateBit0(probLen);\n          probLen = prob + LenLow + (posState << kLenNumLowBits);\n          offset = 0;\n          numBits = kLenNumLowBits;\n        }\n        else\n        {\n          UpdateBit1(probLen);\n          probLen = prob + LenChoice2;\n          IfBit0(probLen)\n          {\n            UpdateBit0(probLen);\n            probLen = prob + LenMid + (posState << kLenNumMidBits);\n            offset = kLenNumLowSymbols;\n            numBits = kLenNumMidBits;\n          }\n          else\n          {\n            UpdateBit1(probLen);\n            probLen = prob + LenHigh;\n            offset = kLenNumLowSymbols + kLenNumMidSymbols;\n            numBits = kLenNumHighBits;\n          }\n        }\n        RangeDecoderBitTreeDecode(probLen, numBits, len);\n        len += offset;\n      }\n\n      if (state < 4)\n      {\n        int posSlot;\n        state += kNumLitStates;\n        prob = p + PosSlot +\n            ((len < kNumLenToPosStates ? len : kNumLenToPosStates - 1) << \n            kNumPosSlotBits);\n        RangeDecoderBitTreeDecode(prob, kNumPosSlotBits, posSlot);\n        if (posSlot >= kStartPosModelIndex)\n        {\n          int numDirectBits = ((posSlot >> 1) - 1);\n          rep0 = (2 | ((UInt32)posSlot & 1));\n          if (posSlot < kEndPosModelIndex)\n          {\n            rep0 <<= numDirectBits;\n            prob = p + SpecPos + rep0 - posSlot - 1;\n          }\n          else\n          {\n            numDirectBits -= kNumAlignBits;\n            do\n            {\n              RC_NORMALIZE\n              Range >>= 1;\n              rep0 <<= 1;\n              if (Code >= Range)\n              {\n                Code -= Range;\n                rep0 |= 1;\n              }\n            }\n            while (--numDirectBits != 0);\n            prob = p + Align;\n            rep0 <<= kNumAlignBits;\n            numDirectBits = kNumAlignBits;\n          }\n          {\n            int i = 1;\n            int mi = 1;\n            do\n            {\n              CProb *prob3 = prob + mi;\n              RC_GET_BIT2(prob3, mi, ; , rep0 |= i);\n              i <<= 1;\n            }\n            while(--numDirectBits != 0);\n          }\n        }\n        else\n          rep0 = posSlot;\n        if (++rep0 == (UInt32)(0))\n        {\n          /* it's for stream version */\n          len = kLzmaStreamWasFinishedId;\n          break;\n        }\n      }\n\n      len += kMatchMinLen;\n      #ifdef _LZMA_OUT_READ\n      if (rep0 > distanceLimit) \n      #else\n      if (rep0 > nowPos)\n      #endif\n        return LZMA_RESULT_DATA_ERROR;\n\n      #ifdef _LZMA_OUT_READ\n      if (dictionarySize - distanceLimit > (UInt32)len)\n        distanceLimit += len;\n      else\n        distanceLimit = dictionarySize;\n      #endif\n\n      do\n      {\n        #ifdef _LZMA_OUT_READ\n        UInt32 pos = dictionaryPos - rep0;\n        if (pos >= dictionarySize)\n          pos += dictionarySize;\n        previousByte = dictionary[pos];\n        dictionary[dictionaryPos] = previousByte;\n        if (++dictionaryPos == dictionarySize)\n          dictionaryPos = 0;\n        #else\n        previousByte = outStream[nowPos - rep0];\n        #endif\n        len--;\n        outStream[nowPos++] = previousByte;\n      }\n      while(len != 0 && nowPos < outSize);\n    }\n  }\n  RC_NORMALIZE;\n\n  #ifdef _LZMA_OUT_READ\n  vs->Range = Range;\n  vs->Code = Code;\n  vs->DictionaryPos = dictionaryPos;\n  vs->GlobalPos = globalPos + (UInt32)nowPos;\n  vs->DistanceLimit = distanceLimit;\n  vs->Reps[0] = rep0;\n  vs->Reps[1] = rep1;\n  vs->Reps[2] = rep2;\n  vs->Reps[3] = rep3;\n  vs->State = state;\n  vs->RemainLen = len;\n  vs->TempDictionary[0] = tempDictionary[0];\n  #endif\n\n  #ifdef _LZMA_IN_CB\n  vs->Buffer = Buffer;\n  vs->BufferLim = BufferLim;\n  #else\n  *inSizeProcessed = (SizeT)(Buffer - inStream);\n  #endif\n  *outSizeProcessed = nowPos;\n  return LZMA_RESULT_OK;\n}\n"
  },
  {
    "path": "target/linux/lantiq/image/lzma-loader/src/LzmaDecode.h",
    "content": "/* \n  LzmaDecode.h\n  LZMA Decoder interface\n\n  LZMA SDK 4.40 Copyright (c) 1999-2006 Igor Pavlov (2006-05-01)\n  http://www.7-zip.org/\n\n  LZMA SDK is licensed under two licenses:\n  1) GNU Lesser General Public License (GNU LGPL)\n  2) Common Public License (CPL)\n  It means that you can select one of these two licenses and \n  follow rules of that license.\n\n  SPECIAL EXCEPTION:\n  Igor Pavlov, as the author of this code, expressly permits you to \n  statically or dynamically link your code (or bind by name) to the \n  interfaces of this file without subjecting your linked code to the \n  terms of the CPL or GNU LGPL. Any modifications or additions \n  to this file, however, are subject to the LGPL or CPL terms.\n*/\n\n#ifndef __LZMADECODE_H\n#define __LZMADECODE_H\n\n#include \"LzmaTypes.h\"\n\n/* #define _LZMA_IN_CB */\n/* Use callback for input data */\n\n/* #define _LZMA_OUT_READ */\n/* Use read function for output data */\n\n/* #define _LZMA_PROB32 */\n/* It can increase speed on some 32-bit CPUs, \n   but memory usage will be doubled in that case */\n\n/* #define _LZMA_LOC_OPT */\n/* Enable local speed optimizations inside code */\n\n#ifdef _LZMA_PROB32\n#define CProb UInt32\n#else\n#define CProb UInt16\n#endif\n\n#define LZMA_RESULT_OK 0\n#define LZMA_RESULT_DATA_ERROR 1\n\n#ifdef _LZMA_IN_CB\ntypedef struct _ILzmaInCallback\n{\n  int (*Read)(void *object, const unsigned char **buffer, SizeT *bufferSize);\n} ILzmaInCallback;\n#endif\n\n#define LZMA_BASE_SIZE 1846\n#define LZMA_LIT_SIZE 768\n\n#define LZMA_PROPERTIES_SIZE 5\n\ntypedef struct _CLzmaProperties\n{\n  int lc;\n  int lp;\n  int pb;\n  #ifdef _LZMA_OUT_READ\n  UInt32 DictionarySize;\n  #endif\n}CLzmaProperties;\n\nint LzmaDecodeProperties(CLzmaProperties *propsRes, const unsigned char *propsData, int size);\n\n#define LzmaGetNumProbs(Properties) (LZMA_BASE_SIZE + (LZMA_LIT_SIZE << ((Properties)->lc + (Properties)->lp)))\n\n#define kLzmaNeedInitId (-2)\n\ntypedef struct _CLzmaDecoderState\n{\n  CLzmaProperties Properties;\n  CProb *Probs;\n\n  #ifdef _LZMA_IN_CB\n  const unsigned char *Buffer;\n  const unsigned char *BufferLim;\n  #endif\n\n  #ifdef _LZMA_OUT_READ\n  unsigned char *Dictionary;\n  UInt32 Range;\n  UInt32 Code;\n  UInt32 DictionaryPos;\n  UInt32 GlobalPos;\n  UInt32 DistanceLimit;\n  UInt32 Reps[4];\n  int State;\n  int RemainLen;\n  unsigned char TempDictionary[4];\n  #endif\n} CLzmaDecoderState;\n\n#ifdef _LZMA_OUT_READ\n#define LzmaDecoderInit(vs) { (vs)->RemainLen = kLzmaNeedInitId; }\n#endif\n\nint LzmaDecode(CLzmaDecoderState *vs,\n    #ifdef _LZMA_IN_CB\n    ILzmaInCallback *inCallback,\n    #else\n    const unsigned char *inStream, SizeT inSize, SizeT *inSizeProcessed,\n    #endif\n    unsigned char *outStream, SizeT outSize, SizeT *outSizeProcessed);\n\n#endif\n"
  },
  {
    "path": "target/linux/lantiq/image/lzma-loader/src/LzmaTypes.h",
    "content": "/* \nLzmaTypes.h \n\nTypes for LZMA Decoder\n\nThis file written and distributed to public domain by Igor Pavlov.\nThis file is part of LZMA SDK 4.40 (2006-05-01)\n*/\n\n#ifndef __LZMATYPES_H\n#define __LZMATYPES_H\n\n#ifndef _7ZIP_BYTE_DEFINED\n#define _7ZIP_BYTE_DEFINED\ntypedef unsigned char Byte;\n#endif \n\n#ifndef _7ZIP_UINT16_DEFINED\n#define _7ZIP_UINT16_DEFINED\ntypedef unsigned short UInt16;\n#endif \n\n#ifndef _7ZIP_UINT32_DEFINED\n#define _7ZIP_UINT32_DEFINED\n#ifdef _LZMA_UINT32_IS_ULONG\ntypedef unsigned long UInt32;\n#else\ntypedef unsigned int UInt32;\n#endif\n#endif \n\n/* #define _LZMA_NO_SYSTEM_SIZE_T */\n/* You can use it, if you don't want <stddef.h> */\n\n#ifndef _7ZIP_SIZET_DEFINED\n#define _7ZIP_SIZET_DEFINED\n#ifdef _LZMA_NO_SYSTEM_SIZE_T\ntypedef UInt32 SizeT;\n#else\n#include <stddef.h>\ntypedef size_t SizeT;\n#endif\n#endif\n\n#endif\n"
  },
  {
    "path": "target/linux/lantiq/image/lzma-loader/src/Makefile",
    "content": "#\n# Makefile for the LZMA compressed kernel loader for\n# Atheros AR7XXX/AR9XXX based boards\n#\n# Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>\n#\n# Some parts of this file was based on the OpenWrt specific lzma-loader\n# for the BCM47xx and ADM5120 based boards:\n#\tCopyright (C) 2004 Manuel Novoa III (mjn3@codepoet.org)\n#\tCopyright (C) 2005 Mineharu Takahara <mtakahar@yahoo.com>\n#\tCopyright (C) 2005 by Oleg I. Vdovikin <oleg@cs.msu.su>\n#\n# This program is free software; you can redistribute it and/or modify it\n# under the terms of the GNU General Public License version 2 as published\n# by the Free Software Foundation.\n#\n\nLOADADDR\t:=\nLZMA_TEXT_START\t:=\nLOADER_DATA\t:=\nKERNEL_MAGIC\t:=\nBOARD\t\t:=\nFLASH_START\t:=\nFLASH_OFFS\t:=\nFLASH_MAX\t:=\nPLATFORM\t:=\nCACHE_FLAGS\t:=\n\nCC\t\t:= $(CROSS_COMPILE)gcc\nLD\t\t:= $(CROSS_COMPILE)ld\nOBJCOPY\t\t:= $(CROSS_COMPILE)objcopy\nOBJDUMP\t\t:= $(CROSS_COMPILE)objdump\ninclude $(PLATFORM).mk\n\nBIN_FLAGS\t:= -O binary -R .reginfo -R .note -R .comment -R .mdebug \\\n\t\t   -R .MIPS.abiflags -S\n\nCFLAGS\t\t= -D__KERNEL__ -Wall -Wstrict-prototypes -Wno-trigraphs -Os \\\n\t\t  -fno-strict-aliasing -fno-common -fomit-frame-pointer -G 0 \\\n\t\t  -mno-abicalls -fno-pic -ffunction-sections -pipe -mlong-calls \\\n\t\t  -fno-common -ffreestanding -fhonour-copts -nostartfiles \\\n\t\t  -mabi=32 -march=mips32r2 \\\n\t\t  -Wa,-32 -Wa,-march=mips32r2 -Wa,-mips32r2 -Wa,--trap\nCFLAGS\t\t+= -D_LZMA_PROB32\nCFLAGS\t\t+= -DARCH=$(PLATFORM)\nCFLAGS\t\t+= -flto\n\nASFLAGS\t\t= $(CFLAGS) -D__ASSEMBLY__\n\nLDFLAGS\t\t= -static -Wl,--gc-sections -Wl,-no-warn-mismatch\nLDFLAGS\t\t+= -Wl,-e,startup -T loader.lds -Wl,-Ttext,$(LZMA_TEXT_START)\nLDFLAGS\t\t+= -flto -fwhole-program\n\nO_FORMAT \t= $(shell $(OBJDUMP) -i | head -2 | grep elf32)\n\nOBJECTS\t\t:= head.o loader.o cache.o board-$(PLATFORM).o printf.o LzmaDecode.o\n\ninclude $(PLATFORM).mk\nCFLAGS+=$(CACHE_FLAGS)\nASFLAGS+=$(CACHE_FLAGS)\n\nifneq ($(strip $(LOADER_DATA)),)\nOBJECTS\t\t+= data.o\nCFLAGS\t\t+= -DLZMA_WRAPPER=1 -DLOADADDR=$(LOADADDR)\nendif\n\nifneq ($(strip $(KERNEL_MAGIC)),)\nCFLAGS\t\t+= -DCONFIG_KERNEL_MAGIC=$(KERNEL_MAGIC)\nendif\n\nifneq ($(strip $(KERNEL_CMDLINE)),)\nCFLAGS\t\t+= -DCONFIG_KERNEL_CMDLINE='\"$(KERNEL_CMDLINE)\"'\nendif\n\nifneq ($(strip $(FLASH_START)),)\nCFLAGS\t\t+= -DCONFIG_FLASH_START=$(FLASH_START)\nendif\nifneq ($(strip $(FLASH_OFFS)),)\nCFLAGS\t\t+= -DCONFIG_FLASH_OFFS=$(FLASH_OFFS)\nendif\n\nifneq ($(strip $(FLASH_MAX)),)\nCFLAGS\t\t+= -DCONFIG_FLASH_MAX=$(FLASH_MAX)\nendif\n\nBOARD_DEF := $(shell echo $(strip $(BOARD)) | tr a-z A-Z | tr - _)\nifneq ($(BOARD_DEF),)\nCFLAGS\t\t+= -DCONFIG_BOARD_$(BOARD_DEF)\nendif\n\nall: loader.elf\n\n# Don't build dependencies, this may die if $(CC) isn't gcc\ndep:\n\ninstall:\n\n%.o : %.c\n\t$(CC) $(CFLAGS) -c -o $@ $<\n\n%.o : %.S\n\t$(CC) $(ASFLAGS) -c -o $@ $<\n\ndata.o: $(LOADER_DATA)\n\t$(LD) -r -b binary --oformat $(O_FORMAT) -T lzma-data.lds -o $@ $<\n\nloader: $(OBJECTS)\n\t$(CC) $(CFLAGS) $(LDFLAGS) -o $@ $(OBJECTS)\n\nloader.bin: loader\n\t$(OBJCOPY) $(BIN_FLAGS) $< $@\n\nloader2.o: loader.bin\n\t$(LD) -r -b binary --oformat $(O_FORMAT) -o $@ $<\n\nloader.elf: loader2.o\n\t$(LD) -z max-page-size=0x1000 -e startup -T loader2.lds -Ttext $(LOADADDR) -o $@ $<\n\nmrproper: clean\n\nclean:\n\trm -f loader *.elf *.bin *.o\n\n\n\n"
  },
  {
    "path": "target/linux/lantiq/image/lzma-loader/src/board-lantiq.c",
    "content": "/*\n * Arch specific code for Lantiq based boards\n *\n * Copyright (C) 2013 John Crispin <blogic@openwrt.org>\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of the GNU General Public License version 2 as published\n * by the Free Software Foundation.\n */\n\n#include <stddef.h>\n#include \"config.h\"\n\n#define READREG(r)\t\t*(volatile unsigned int *)(r)\n#define WRITEREG(r,v)\t\t*(volatile unsigned int *)(r) = v\n\n#define UART_BASE\t\t0xbe100c00\n#define ASC_TBUF\t\t(UART_BASE | 0x20)\n#define ASC_FSTAT\t\t(UART_BASE | 0x48)\n\n#define TXMASK          0x3F00\n#define TXOFFSET        8\n\nvoid board_putc(char c)\n{\n\twhile ((READREG(ASC_FSTAT) & TXMASK) >> TXOFFSET);\n\n\tWRITEREG(ASC_TBUF, c);\n}\n\nvoid board_init(void)\n{\n}\n"
  },
  {
    "path": "target/linux/lantiq/image/lzma-loader/src/cache.c",
    "content": "/*\n * LZMA compressed kernel loader for Atheros AR7XXX/AR9XXX based boards\n *\n * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>\n *\n * The cache manipulation routine has been taken from the U-Boot project.\n *\t(C) Copyright 2003\n *\tWolfgang Denk, DENX Software Engineering, <wd@denx.de>\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of the GNU General Public License version 2 as published\n * by the Free Software Foundation.\n *\n */\n\n#include \"cache.h\"\n#include \"cacheops.h\"\n#include \"config.h\"\n\n#define cache_op(op,addr)\t\t\t\t\t\t\\\n\t__asm__ __volatile__(\t\t\t\t\t\t\\\n\t\"\t.set\tpush\t\t\t\t\t\\n\"\t\\\n\t\"\t.set\tnoreorder\t\t\t\t\\n\"\t\\\n\t\"\t.set\tmips3\\n\\t\t\t\t\t\\n\"\t\\\n\t\"\tcache\t%0, %1\t\t\t\t\t\\n\"\t\\\n\t\"\t.set\tpop\t\t\t\t\t\\n\"\t\\\n\t:\t\t\t\t\t\t\t\t\\\n\t: \"i\" (op), \"R\" (*(unsigned char *)(addr)))\n\nvoid flush_cache(unsigned long start_addr, unsigned long size)\n{\n\tunsigned long lsize = CONFIG_CACHELINE_SIZE;\n\tunsigned long addr = start_addr & ~(lsize - 1);\n\tunsigned long aend = (start_addr + size - 1) & ~(lsize - 1);\n\n\twhile (1) {\n\t\tcache_op(Hit_Writeback_Inv_D, addr);\n\t\tcache_op(Hit_Invalidate_I, addr);\n\t\tif (addr == aend)\n\t\t\tbreak;\n\t\taddr += lsize;\n\t}\n}\n"
  },
  {
    "path": "target/linux/lantiq/image/lzma-loader/src/cache.h",
    "content": "/*\n * LZMA compressed kernel loader for Atheros AR7XXX/AR9XXX based boards\n *\n * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of the GNU General Public License version 2 as published\n * by the Free Software Foundation.\n *\n */\n\n#ifndef __CACHE_H\n#define __CACHE_H\n\nvoid flush_cache(unsigned long start_addr, unsigned long size);\n\n#endif /* __CACHE_H */\n"
  },
  {
    "path": "target/linux/lantiq/image/lzma-loader/src/cacheops.h",
    "content": "/*\n * Cache operations for the cache instruction.\n *\n * This file is subject to the terms and conditions of the GNU General Public\n * License.  See the file \"COPYING\" in the main directory of this archive\n * for more details.\n *\n * (C) Copyright 1996, 97, 99, 2002, 03 Ralf Baechle\n * (C) Copyright 1999 Silicon Graphics, Inc.\n */\n#ifndef\t__ASM_CACHEOPS_H\n#define\t__ASM_CACHEOPS_H\n\n/*\n * Cache Operations available on all MIPS processors with R4000-style caches\n */\n#define Index_Invalidate_I      0x00\n#define Index_Writeback_Inv_D   0x01\n#define Index_Load_Tag_I\t0x04\n#define Index_Load_Tag_D\t0x05\n#define Index_Store_Tag_I\t0x08\n#define Index_Store_Tag_D\t0x09\n#if defined(CONFIG_CPU_LOONGSON2)\n#define Hit_Invalidate_I\t0x00\n#else\n#define Hit_Invalidate_I\t0x10\n#endif\n#define Hit_Invalidate_D\t0x11\n#define Hit_Writeback_Inv_D\t0x15\n\n/*\n * R4000-specific cacheops\n */\n#define Create_Dirty_Excl_D\t0x0d\n#define Fill\t\t\t0x14\n#define Hit_Writeback_I\t\t0x18\n#define Hit_Writeback_D\t\t0x19\n\n/*\n * R4000SC and R4400SC-specific cacheops\n */\n#define Index_Invalidate_SI     0x02\n#define Index_Writeback_Inv_SD  0x03\n#define Index_Load_Tag_SI\t0x06\n#define Index_Load_Tag_SD\t0x07\n#define Index_Store_Tag_SI\t0x0A\n#define Index_Store_Tag_SD\t0x0B\n#define Create_Dirty_Excl_SD\t0x0f\n#define Hit_Invalidate_SI\t0x12\n#define Hit_Invalidate_SD\t0x13\n#define Hit_Writeback_Inv_SD\t0x17\n#define Hit_Writeback_SD\t0x1b\n#define Hit_Set_Virtual_SI\t0x1e\n#define Hit_Set_Virtual_SD\t0x1f\n\n/*\n * R5000-specific cacheops\n */\n#define R5K_Page_Invalidate_S\t0x17\n\n/*\n * RM7000-specific cacheops\n */\n#define Page_Invalidate_T\t0x16\n\n/*\n * R10000-specific cacheops\n *\n * Cacheops 0x02, 0x06, 0x0a, 0x0c-0x0e, 0x16, 0x1a and 0x1e are unused.\n * Most of the _S cacheops are identical to the R4000SC _SD cacheops.\n */\n#define Index_Writeback_Inv_S\t0x03\n#define Index_Load_Tag_S\t0x07\n#define Index_Store_Tag_S\t0x0B\n#define Hit_Invalidate_S\t0x13\n#define Cache_Barrier\t\t0x14\n#define Hit_Writeback_Inv_S\t0x17\n#define Index_Load_Data_I\t0x18\n#define Index_Load_Data_D\t0x19\n#define Index_Load_Data_S\t0x1b\n#define Index_Store_Data_I\t0x1c\n#define Index_Store_Data_D\t0x1d\n#define Index_Store_Data_S\t0x1f\n\n#endif\t/* __ASM_CACHEOPS_H */\n"
  },
  {
    "path": "target/linux/lantiq/image/lzma-loader/src/config.h",
    "content": "/*\n * LZMA compressed kernel loader for Atheros AR7XXX/AR9XXX based boards\n *\n * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of the GNU General Public License version 2 as published\n * by the Free Software Foundation.\n *\n */\n\n#ifndef _CONFIG_H_\n#define _CONFIG_H_\n\n#ifndef CONFIG_FLASH_OFFS\n#define CONFIG_FLASH_OFFS\t0\n#endif\n\n#ifndef CONFIG_FLASH_MAX\n#define CONFIG_FLASH_MAX\t0\n#endif\n\n#ifndef CONFIG_FLASH_STEP\n#define CONFIG_FLASH_STEP\t0x1000\n#endif\n\n#endif /* _CONFIG_H_ */\n"
  },
  {
    "path": "target/linux/lantiq/image/lzma-loader/src/cp0regdef.h",
    "content": "/*\n * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle\n *\n * Copyright (C) 2001, Monta Vista Software\n * Author: jsun@mvista.com or jsun@junsun.net\n */\n#ifndef _cp0regdef_h_\n#define _cp0regdef_h_\n\n#define CP0_INDEX $0\n#define CP0_RANDOM $1\n#define CP0_ENTRYLO0 $2\n#define CP0_ENTRYLO1 $3\n#define CP0_CONTEXT $4\n#define CP0_PAGEMASK $5\n#define CP0_WIRED $6\n#define CP0_BADVADDR $8\n#define CP0_COUNT $9\n#define CP0_ENTRYHI $10\n#define CP0_COMPARE $11\n#define CP0_STATUS $12\n#define CP0_CAUSE $13\n#define CP0_EPC $14\n#define CP0_PRID $15\n#define CP0_CONFIG $16\n#define CP0_LLADDR $17\n#define CP0_WATCHLO $18\n#define CP0_WATCHHI $19\n#define CP0_XCONTEXT $20\n#define CP0_FRAMEMASK $21\n#define CP0_DIAGNOSTIC $22\n#define CP0_PERFORMANCE $25\n#define CP0_ECC $26\n#define CP0_CACHEERR $27\n#define CP0_TAGLO $28\n#define CP0_TAGHI $29\n#define CP0_ERROREPC $30\n\n#endif\n"
  },
  {
    "path": "target/linux/lantiq/image/lzma-loader/src/head.S",
    "content": "/*\n * LZMA compressed kernel loader for Atheros AR7XXX/AR9XXX based boards\n *\n * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>\n *\n * Some parts of this code was based on the OpenWrt specific lzma-loader\n * for the BCM47xx and ADM5120 based boards:\n *\tCopyright (C) 2004 Manuel Novoa III (mjn3@codepoet.org)\n *\tCopyright (C) 2005 by Oleg I. Vdovikin <oleg@cs.msu.su>\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of the GNU General Public License version 2 as published\n * by the Free Software Foundation.\n */\n\n#include <asm/asm.h>\n#include <asm/regdef.h>\n#include \"cp0regdef.h\"\n#include \"cacheops.h\"\n#include \"config.h\"\n\n#define KSEG0\t\t0x80000000\n\n\t.macro\tehb\n\tsll     zero, 3\n\t.endm\n\n\t.text\n\nLEAF(startup)\n\t.set noreorder\n\t.set mips32\n\n\tmtc0\tzero, CP0_WATCHLO\t# clear watch registers\n\tmtc0\tzero, CP0_WATCHHI\n\tmtc0\tzero, CP0_CAUSE\t\t# clear before writing status register\n\n\tmfc0\tt0, CP0_STATUS\n\tli\tt1, 0x1000001f\n\tor\tt0, t1\n\txori\tt0, 0x1f\n\tmtc0\tt0, CP0_STATUS\n\tehb\n\n\t/*\n\t * Some bootloaders set the 'Kseg0 coherency algorithm' to\n\t * 'Cacheable, noncoherent, write-through, no write allocate'\n\t * and this cause performance issues. Let's go and change it to\n\t * 'Cacheable, noncoherent, write-back, write allocate'\n\t */\n\tmfc0\tt0, CP0_CONFIG\n\tli\tt1, ~7\t\t\t#~CONF_CM_CMASK\n\tand\tt0, t1\n\tori\tt0, 3\t\t\t#CONF_CM_CACHABLE_NONCOHERENT\n\tmtc0\tt0, CP0_CONFIG\n\tnop\n\n\tmtc0\tzero, CP0_COUNT\n\tmtc0\tzero, CP0_COMPARE\n\tehb\n\n\tla\tt0, __reloc_label\t# get linked address of label\n\tbal\t__reloc_label\t\t# branch and link to label to\n\tnop\t\t\t\t# get actual address\n__reloc_label:\n\tsubu\tt0, ra, t0\t\t# get reloc_delta\n\n\tbeqz\tt0, __reloc_done         # if delta is 0 we are in the right place\n\tnop\n\n\t/* Copy our code to the right place */\n\tla\tt1, _code_start\t\t# get linked address of _code_start\n\tla\tt2, _code_end\t\t# get linked address of _code_end\n\taddu\tt0, t0, t1\t\t# calculate actual address of _code_start\n\n__reloc_copy:\n\tlw\tt3, 0(t0)\n\tsw\tt3, 0(t1)\n\tadd\tt1, 4\n\tblt\tt1, t2, __reloc_copy\n\tadd\tt0, 4\n\n\t/* flush cache */\n\tla\tt0, _code_start\n\tla\tt1, _code_end\n\n\tli\tt2, ~(CONFIG_CACHELINE_SIZE - 1)\n\tand\tt0, t2\n\tand\tt1, t2\n\tli\tt2, CONFIG_CACHELINE_SIZE\n\n\tb\t__flush_check\n\tnop\n\n__flush_line:\n\tcache\tHit_Writeback_Inv_D, 0(t0)\n\tcache\tHit_Invalidate_I, 0(t0)\n\tadd\tt0, t2\n\n__flush_check:\n\tbne\tt0, t1, __flush_line\n\tnop\n\n\tsync\n\n__reloc_done:\n\n\t/* clear bss */\n\tla\tt0, _bss_start\n\tla\tt1, _bss_end\n\tb\t__bss_check\n\tnop\n\n__bss_fill:\n\tsw\tzero, 0(t0)\n\taddi\tt0, 4\n\n__bss_check:\n\tbne\tt0, t1, __bss_fill\n\tnop\n\n\t/* Setup new \"C\" stack */\n\tla\tsp, _stack\n\n\t/* reserve stack space for a0-a3 registers */\n\tsubu\tsp, 16\n\n\t/* jump to the decompressor routine */\n\tla\tt0, loader_main\n\tjr\tt0\n\tnop\n\n\t.set reorder\nEND(startup)\n"
  },
  {
    "path": "target/linux/lantiq/image/lzma-loader/src/lantiq.mk",
    "content": "CACHE_FLAGS+=-DCONFIG_ICACHE_SIZE=\"(32 * 1024)\" -DCONFIG_DCACHE_SIZE=\"(32 * 1024)\" -DCONFIG_CACHELINE_SIZE=32\n"
  },
  {
    "path": "target/linux/lantiq/image/lzma-loader/src/loader.c",
    "content": "/*\n * LZMA compressed kernel loader for Atheros AR7XXX/AR9XXX based boards\n *\n * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>\n *\n * Some parts of this code was based on the OpenWrt specific lzma-loader\n * for the BCM47xx and ADM5120 based boards:\n *\tCopyright (C) 2004 Manuel Novoa III (mjn3@codepoet.org)\n *\tCopyright (C) 2005 Mineharu Takahara <mtakahar@yahoo.com>\n *\tCopyright (C) 2005 by Oleg I. Vdovikin <oleg@cs.msu.su>\n *\n * The image_header structure has been taken from the U-Boot project.\n *\t(C) Copyright 2008 Semihalf\n *\t(C) Copyright 2000-2005\n *\tWolfgang Denk, DENX Software Engineering, wd@denx.de.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of the GNU General Public License version 2 as published\n * by the Free Software Foundation.\n */\n\n#include <stddef.h>\n#include <stdint.h>\n\n#include \"config.h\"\n#include \"cache.h\"\n#include \"printf.h\"\n#include \"LzmaDecode.h\"\n\n\n#define KSEG0\t\t\t0x80000000\n#define KSEG1\t\t\t0xa0000000\n\n#define KSEG1ADDR(a)\t\t((((unsigned)(a)) & 0x1fffffffU) | KSEG1)\n\n#undef LZMA_DEBUG\n\n#ifdef LZMA_DEBUG\n#  define DBG(f, a...)\tprintf(f, ## a)\n#else\n#  define DBG(f, a...)\tdo {} while (0)\n#endif\n\n#define IH_MAGIC_OKLI\t\t0x4f4b4c49\t/* 'OKLI' */\n\n#define IH_NMLEN\t\t32\t/* Image Name Length\t\t*/\n\ntypedef struct image_header {\n\tuint32_t\tih_magic;\t/* Image Header Magic Number\t*/\n\tuint32_t\tih_hcrc;\t/* Image Header CRC Checksum\t*/\n\tuint32_t\tih_time;\t/* Image Creation Timestamp\t*/\n\tuint32_t\tih_size;\t/* Image Data Size\t\t*/\n\tuint32_t\tih_load;\t/* Data\t Load  Address\t\t*/\n\tuint32_t\tih_ep;\t\t/* Entry Point Address\t\t*/\n\tuint32_t\tih_dcrc;\t/* Image Data CRC Checksum\t*/\n\tuint8_t\t\tih_os;\t\t/* Operating System\t\t*/\n\tuint8_t\t\tih_arch;\t/* CPU architecture\t\t*/\n\tuint8_t\t\tih_type;\t/* Image Type\t\t\t*/\n\tuint8_t\t\tih_comp;\t/* Compression Type\t\t*/\n\tuint8_t\t\tih_name[IH_NMLEN];\t/* Image Name\t\t*/\n} image_header_t;\n\n/* beyond the image end, size not known in advance */\nextern unsigned char workspace[];\nextern void board_init(void);\n\nstatic CLzmaDecoderState lzma_state;\nstatic unsigned char *lzma_data;\nstatic unsigned long lzma_datasize;\nstatic unsigned long lzma_outsize;\nstatic unsigned long kernel_la;\n\n#ifdef CONFIG_KERNEL_CMDLINE\n#define kernel_argc\t2\nstatic const char kernel_cmdline[] = CONFIG_KERNEL_CMDLINE;\nstatic const char *const kernel_argv[] = {\n\tNULL,\n\tkernel_cmdline,\n\tNULL,\n};\n#endif /* CONFIG_KERNEL_CMDLINE */\n\nstatic void halt(void)\n{\n\tprintf(\"\\nSystem halted!\\n\");\n\tfor(;;);\n}\n\nstatic __inline__ unsigned long get_be32(void *buf)\n{\n\tunsigned char *p = buf;\n\n\treturn (((unsigned long) p[0] << 24) +\n\t        ((unsigned long) p[1] << 16) +\n\t        ((unsigned long) p[2] << 8) +\n\t        (unsigned long) p[3]);\n}\n\nstatic __inline__ unsigned char lzma_get_byte(void)\n{\n\tunsigned char c;\n\n\tlzma_datasize--;\n\tc = *lzma_data++;\n\n\treturn c;\n}\n\nstatic int lzma_init_props(void)\n{\n\tunsigned char props[LZMA_PROPERTIES_SIZE];\n\tint res;\n\tint i;\n\n\t/* read lzma properties */\n\tfor (i = 0; i < LZMA_PROPERTIES_SIZE; i++)\n\t\tprops[i] = lzma_get_byte();\n\n\t/* read the lower half of uncompressed size in the header */\n\tlzma_outsize = ((SizeT) lzma_get_byte()) +\n\t\t       ((SizeT) lzma_get_byte() << 8) +\n\t\t       ((SizeT) lzma_get_byte() << 16) +\n\t\t       ((SizeT) lzma_get_byte() << 24);\n\n\t/* skip rest of the header (upper half of uncompressed size) */\n\tfor (i = 0; i < 4; i++)\n\t\tlzma_get_byte();\n\n\tres = LzmaDecodeProperties(&lzma_state.Properties, props,\n\t\t\t\t\tLZMA_PROPERTIES_SIZE);\n\treturn res;\n}\n\nstatic int lzma_decompress(unsigned char *outStream)\n{\n\tSizeT ip, op;\n\tint ret;\n\n\tlzma_state.Probs = (CProb *) workspace;\n\n\tret = LzmaDecode(&lzma_state, lzma_data, lzma_datasize, &ip, outStream,\n\t\t\t lzma_outsize, &op);\n\n\tif (ret != LZMA_RESULT_OK) {\n\t\tint i;\n\n\t\tDBG(\"LzmaDecode error %d at %08x, osize:%d ip:%d op:%d\\n\",\n\t\t    ret, lzma_data + ip, lzma_outsize, ip, op);\n\n\t\tfor (i = 0; i < 16; i++)\n\t\t\tDBG(\"%02x \", lzma_data[ip + i]);\n\n\t\tDBG(\"\\n\");\n\t}\n\n\treturn ret;\n}\n\n#if (LZMA_WRAPPER)\nstatic void lzma_init_data(void)\n{\n\textern unsigned char _lzma_data_start[];\n\textern unsigned char _lzma_data_end[];\n\n\tkernel_la = LOADADDR;\n\tlzma_data = _lzma_data_start;\n\tlzma_datasize = _lzma_data_end - _lzma_data_start;\n}\n#else\nstatic void lzma_init_data(void)\n{\n\tstruct image_header *hdr = NULL;\n\tunsigned char *flash_base;\n\tunsigned long flash_ofs;\n\tunsigned long kernel_ofs;\n\tunsigned long kernel_size;\n\n\tflash_base = (unsigned char *) KSEG1ADDR(CONFIG_FLASH_START);\n\n\tprintf(\"Looking for OpenWrt image... \");\n\n\tfor (flash_ofs = CONFIG_FLASH_OFFS;\n\t     flash_ofs <= (CONFIG_FLASH_OFFS + CONFIG_FLASH_MAX);\n\t     flash_ofs += CONFIG_FLASH_STEP) {\n\t\tunsigned long magic;\n\t\tunsigned char *p;\n\n\t\tp = flash_base + flash_ofs;\n\t\tmagic = get_be32(p);\n#ifdef CONFIG_KERNEL_MAGIC\n\t\tif (magic == CONFIG_KERNEL_MAGIC) {\n#else\n\t\tif (magic == IH_MAGIC_OKLI) {\n#endif\n\t\t\thdr = (struct image_header *) p;\n\t\t\tbreak;\n\t\t}\n\t}\n\n\tif (hdr == NULL) {\n\t\tprintf(\"not found!\\n\");\n\t\thalt();\n\t}\n\n\tprintf(\"found at 0x%08x\\n\", flash_base + flash_ofs);\n\n\tkernel_ofs = sizeof(struct image_header);\n\tkernel_size = get_be32(&hdr->ih_size);\n\tkernel_la = get_be32(&hdr->ih_load);\n\n\tlzma_data = flash_base + flash_ofs + kernel_ofs;\n\tlzma_datasize = kernel_size;\n}\n#endif /* (LZMA_WRAPPER) */\n\nvoid loader_main(unsigned long reg_a0, unsigned long reg_a1,\n\t\t unsigned long reg_a2, unsigned long reg_a3)\n{\n\tvoid (*kernel_entry) (unsigned long, unsigned long, unsigned long,\n\t\t\t      unsigned long);\n\tint res;\n\n\tboard_init();\n\n\tprintf(\"\\n\\nOpenWrt kernel loader for MIPS based SoC\\n\");\n\tprintf(\"Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>\\n\");\n\n\tlzma_init_data();\n\n\tres = lzma_init_props();\n\tif (res != LZMA_RESULT_OK) {\n\t\tprintf(\"Incorrect LZMA stream properties!\\n\");\n\t\thalt();\n\t}\n\n\tprintf(\"Decompressing kernel... \");\n\n\tres = lzma_decompress((unsigned char *) kernel_la);\n\tif (res != LZMA_RESULT_OK) {\n\t\tprintf(\"failed, \");\n\t\tswitch (res) {\n\t\tcase LZMA_RESULT_DATA_ERROR:\n\t\t\tprintf(\"data error!\\n\");\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tprintf(\"unknown error %d!\\n\", res);\n\t\t}\n\t\thalt();\n\t} else {\n\t\tprintf(\"done!\\n\");\n\t}\n\n\tflush_cache(kernel_la, lzma_outsize);\n\n\tprintf(\"Starting kernel at %08x...\\n\\n\", kernel_la);\n\n#ifdef CONFIG_KERNEL_CMDLINE\n\treg_a0 = kernel_argc;\n\treg_a1 = (unsigned long) kernel_argv;\n\treg_a2 = 0;\n\treg_a3 = 0;\n#endif\n\n\tkernel_entry = (void *) kernel_la;\n\tkernel_entry(reg_a0, reg_a1, reg_a2, reg_a3);\n}\n"
  },
  {
    "path": "target/linux/lantiq/image/lzma-loader/src/loader.lds",
    "content": "OUTPUT_ARCH(mips)\nSECTIONS {\n\t.text : {\n\t\t_code_start = .;\n\t\t*(.text)\n\t\t*(.text.*)\n\t\t*(.rodata)\n\t\t*(.rodata.*)\n\t\t*(.data.lzma)\n\t}\n\n\t. = ALIGN(32);\n\t.data : {\n\t\t*(.data)\n\t\t*(.data.*)\n\t}\n\n\t. = ALIGN(32);\n\t_code_end = .;\n\n\t_bss_start = .;\n\t.bss : {\n\t\t*(.bss)\n\t\t*(.bss.*)\n\t}\n\n\t. = ALIGN(32);\n\t_bss_end = .;\n\n\t. = . + 8192;\n\t_stack = .;\n\n\tworkspace = .;\n}\n"
  },
  {
    "path": "target/linux/lantiq/image/lzma-loader/src/loader2.lds",
    "content": "OUTPUT_ARCH(mips)\nSECTIONS {\n\t.text : {\n\t\tstartup = .;\n\t\t*(.text)\n\t\t*(.text.*)\n\t\t*(.data)\n\t\t*(.data.*)\n\t}\n}\n"
  },
  {
    "path": "target/linux/lantiq/image/lzma-loader/src/lzma-data.lds",
    "content": "OUTPUT_ARCH(mips)\nSECTIONS {\n\t.data.lzma : {\n\t\t_lzma_data_start = .;\n\t\t*(.data)\n\t\t_lzma_data_end = .;\n\t}\n}\n"
  },
  {
    "path": "target/linux/lantiq/image/lzma-loader/src/printf.c",
    "content": "/*\n * Copyright (C) 2001 MontaVista Software Inc.\n * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net\n *\n * This program is free software; you can redistribute  it and/or modify it\n * under  the terms of  the GNU General  Public License as published by the\n * Free Software Foundation;  either version 2 of the  License, or (at your\n * option) any later version.\n *\n */\n\n#include\t\"printf.h\"\n\nextern void board_putc(int ch);\n\n/* this is the maximum width for a variable */\n#define\t\tLP_MAX_BUF\t256\n\n/* macros */\n#define\t\tIsDigit(x)\t( ((x) >= '0') && ((x) <= '9') )\n#define\t\tCtod(x)\t\t( (x) - '0')\n\n/* forward declaration */\nstatic int PrintChar(char *, char, int, int);\nstatic int PrintString(char *, char *, int, int);\nstatic int PrintNum(char *, unsigned long, int, int, int, int, char, int);\n\n/* private variable */\nstatic const char theFatalMsg[] = \"fatal error in lp_Print!\";\n\n/* -*-\n * A low level printf() function.\n */\nstatic void\nlp_Print(void (*output)(void *, char *, int),\n\t void * arg,\n\t char *fmt,\n\t va_list ap)\n{\n\n#define \tOUTPUT(arg, s, l)  \\\n  { if (((l) < 0) || ((l) > LP_MAX_BUF)) { \\\n       (*output)(arg, (char*)theFatalMsg, sizeof(theFatalMsg)-1); for(;;); \\\n    } else { \\\n      (*output)(arg, s, l); \\\n    } \\\n  }\n\n    char buf[LP_MAX_BUF];\n\n    char c;\n    char *s;\n    long int num;\n\n    int longFlag;\n    int negFlag;\n    int width;\n    int prec;\n    int ladjust;\n    char padc;\n\n    int length;\n\n    for(;;) {\n\t{\n\t    /* scan for the next '%' */\n\t    char *fmtStart = fmt;\n\t    while ( (*fmt != '\\0') && (*fmt != '%')) {\n\t\tfmt ++;\n\t    }\n\n\t    /* flush the string found so far */\n\t    OUTPUT(arg, fmtStart, fmt-fmtStart);\n\n\t    /* are we hitting the end? */\n\t    if (*fmt == '\\0') break;\n\t}\n\n\t/* we found a '%' */\n\tfmt ++;\n\n\t/* check for long */\n\tif (*fmt == 'l') {\n\t    longFlag = 1;\n\t    fmt ++;\n\t} else {\n\t    longFlag = 0;\n\t}\n\n\t/* check for other prefixes */\n\twidth = 0;\n\tprec = -1;\n\tladjust = 0;\n\tpadc = ' ';\n\n\tif (*fmt == '-') {\n\t    ladjust = 1;\n\t    fmt ++;\n\t}\n\n\tif (*fmt == '0') {\n\t    padc = '0';\n\t    fmt++;\n\t}\n\n\tif (IsDigit(*fmt)) {\n\t    while (IsDigit(*fmt)) {\n\t\twidth = 10 * width + Ctod(*fmt++);\n\t    }\n\t}\n\n\tif (*fmt == '.') {\n\t    fmt ++;\n\t    if (IsDigit(*fmt)) {\n\t\tprec = 0;\n\t\twhile (IsDigit(*fmt)) {\n\t\t    prec = prec*10 + Ctod(*fmt++);\n\t\t}\n\t    }\n\t}\n\n\n\t/* check format flag */\n\tnegFlag = 0;\n\tswitch (*fmt) {\n\t case 'b':\n\t    if (longFlag) {\n\t\tnum = va_arg(ap, long int);\n\t    } else {\n\t\tnum = va_arg(ap, int);\n\t    }\n\t    length = PrintNum(buf, num, 2, 0, width, ladjust, padc, 0);\n\t    OUTPUT(arg, buf, length);\n\t    break;\n\n\t case 'd':\n\t case 'D':\n\t    if (longFlag) {\n\t\tnum = va_arg(ap, long int);\n\t    } else {\n\t\tnum = va_arg(ap, int);\n\t    }\n\t    if (num < 0) {\n\t\tnum = - num;\n\t\tnegFlag = 1;\n\t    }\n\t    length = PrintNum(buf, num, 10, negFlag, width, ladjust, padc, 0);\n\t    OUTPUT(arg, buf, length);\n\t    break;\n\n\t case 'o':\n\t case 'O':\n\t    if (longFlag) {\n\t\tnum = va_arg(ap, long int);\n\t    } else {\n\t\tnum = va_arg(ap, int);\n\t    }\n\t    length = PrintNum(buf, num, 8, 0, width, ladjust, padc, 0);\n\t    OUTPUT(arg, buf, length);\n\t    break;\n\n\t case 'u':\n\t case 'U':\n\t    if (longFlag) {\n\t\tnum = va_arg(ap, long int);\n\t    } else {\n\t\tnum = va_arg(ap, int);\n\t    }\n\t    length = PrintNum(buf, num, 10, 0, width, ladjust, padc, 0);\n\t    OUTPUT(arg, buf, length);\n\t    break;\n\n\t case 'x':\n\t    if (longFlag) {\n\t\tnum = va_arg(ap, long int);\n\t    } else {\n\t\tnum = va_arg(ap, int);\n\t    }\n\t    length = PrintNum(buf, num, 16, 0, width, ladjust, padc, 0);\n\t    OUTPUT(arg, buf, length);\n\t    break;\n\n\t case 'X':\n\t    if (longFlag) {\n\t\tnum = va_arg(ap, long int);\n\t    } else {\n\t\tnum = va_arg(ap, int);\n\t    }\n\t    length = PrintNum(buf, num, 16, 0, width, ladjust, padc, 1);\n\t    OUTPUT(arg, buf, length);\n\t    break;\n\n\t case 'c':\n\t    c = (char)va_arg(ap, int);\n\t    length = PrintChar(buf, c, width, ladjust);\n\t    OUTPUT(arg, buf, length);\n\t    break;\n\n\t case 's':\n\t    s = (char*)va_arg(ap, char *);\n\t    length = PrintString(buf, s, width, ladjust);\n\t    OUTPUT(arg, buf, length);\n\t    break;\n\n\t case '\\0':\n\t    fmt --;\n\t    break;\n\n\t default:\n\t    /* output this char as it is */\n\t    OUTPUT(arg, fmt, 1);\n\t}\t/* switch (*fmt) */\n\n\tfmt ++;\n    }\t\t/* for(;;) */\n\n    /* special termination call */\n    OUTPUT(arg, \"\\0\", 1);\n}\n\n\n/* --------------- local help functions --------------------- */\nstatic int\nPrintChar(char * buf, char c, int length, int ladjust)\n{\n    int i;\n\n    if (length < 1) length = 1;\n    if (ladjust) {\n\t*buf = c;\n\tfor (i=1; i< length; i++) buf[i] = ' ';\n    } else {\n\tfor (i=0; i< length-1; i++) buf[i] = ' ';\n\tbuf[length - 1] = c;\n    }\n    return length;\n}\n\nstatic int\nPrintString(char * buf, char* s, int length, int ladjust)\n{\n    int i;\n    int len=0;\n    char* s1 = s;\n    while (*s1++) len++;\n    if (length < len) length = len;\n\n    if (ladjust) {\n\tfor (i=0; i< len; i++) buf[i] = s[i];\n\tfor (i=len; i< length; i++) buf[i] = ' ';\n    } else {\n\tfor (i=0; i< length-len; i++) buf[i] = ' ';\n\tfor (i=length-len; i < length; i++) buf[i] = s[i-length+len];\n    }\n    return length;\n}\n\nstatic int\nPrintNum(char * buf, unsigned long u, int base, int negFlag,\n\t int length, int ladjust, char padc, int upcase)\n{\n    /* algorithm :\n     *  1. prints the number from left to right in reverse form.\n     *  2. fill the remaining spaces with padc if length is longer than\n     *     the actual length\n     *     TRICKY : if left adjusted, no \"0\" padding.\n     *\t\t    if negtive, insert  \"0\" padding between \"0\" and number.\n     *  3. if (!ladjust) we reverse the whole string including paddings\n     *  4. otherwise we only reverse the actual string representing the num.\n     */\n\n    int actualLength =0;\n    char *p = buf;\n    int i;\n\n    do {\n\tint tmp = u %base;\n\tif (tmp <= 9) {\n\t    *p++ = '0' + tmp;\n\t} else if (upcase) {\n\t    *p++ = 'A' + tmp - 10;\n\t} else {\n\t    *p++ = 'a' + tmp - 10;\n\t}\n\tu /= base;\n    } while (u != 0);\n\n    if (negFlag) {\n\t*p++ = '-';\n    }\n\n    /* figure out actual length and adjust the maximum length */\n    actualLength = p - buf;\n    if (length < actualLength) length = actualLength;\n\n    /* add padding */\n    if (ladjust) {\n\tpadc = ' ';\n    }\n    if (negFlag && !ladjust && (padc == '0')) {\n\tfor (i = actualLength-1; i< length-1; i++) buf[i] = padc;\n\tbuf[length -1] = '-';\n    } else {\n\tfor (i = actualLength; i< length; i++) buf[i] = padc;\n    }\n\n\n    /* prepare to reverse the string */\n    {\n\tint begin = 0;\n\tint end;\n\tif (ladjust) {\n\t    end = actualLength - 1;\n\t} else {\n\t    end = length -1;\n\t}\n\n\twhile (end > begin) {\n\t    char tmp = buf[begin];\n\t    buf[begin] = buf[end];\n\t    buf[end] = tmp;\n\t    begin ++;\n\t    end --;\n\t}\n    }\n\n    /* adjust the string pointer */\n    return length;\n}\n\nstatic void printf_output(void *arg, char *s, int l)\n{\n    int i;\n\n    // special termination call\n    if ((l==1) && (s[0] == '\\0')) return;\n\n    for (i=0; i< l; i++) {\n\tboard_putc(s[i]);\n\tif (s[i] == '\\n') board_putc('\\r');\n    }\n}\n\nvoid printf(char *fmt, ...)\n{\n    va_list ap;\n    va_start(ap, fmt);\n    lp_Print(printf_output, 0, fmt, ap);\n    va_end(ap);\n}\n"
  },
  {
    "path": "target/linux/lantiq/image/lzma-loader/src/printf.h",
    "content": "/*\n * Copyright (C) 2001 MontaVista Software Inc.\n * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net\n *\n * This program is free software; you can redistribute  it and/or modify it\n * under  the terms of  the GNU General  Public License as published by the\n * Free Software Foundation;  either version 2 of the  License, or (at your\n * option) any later version.\n *\n */\n\n#ifndef _printf_h_\n#define _printf_h_\n\n#include <stdarg.h>\nvoid printf(char *fmt, ...);\n\n#endif /* _printf_h_ */\n"
  },
  {
    "path": "target/linux/lantiq/image/tp-link.mk",
    "content": "DEVICE_VARS += TPLINK_FLASHLAYOUT TPLINK_HWID TPLINK_HWREV TPLINK_HWREVADD TPLINK_HVERSION\n\ndefine Device/dsa-migration\n  DEVICE_COMPAT_VERSION := 1.1\n  DEVICE_COMPAT_MESSAGE := Config cannot be migrated from swconfig to DSA\nendef\n\ndefine Device/lantiqTpLink\n  DEVICE_VENDOR := TP-Link\n  TPLINK_HWREVADD := 0\n  TPLINK_HVERSION := 2\n  KERNEL := kernel-bin | append-dtb | lzma\n  KERNEL_INITRAMFS := kernel-bin | append-dtb | lzma | \\\n\ttplink-v2-header -s -V \"ver. 1.0\"\n  IMAGES := sysupgrade.bin\n  IMAGE/sysupgrade.bin := tplink-v2-image -s -V \"ver. 1.0\" | \\\n\tcheck-size | append-metadata\nendef\n\ndefine Device/tplink_tdw8970\n  $(Device/dsa-migration)\n  $(Device/lantiqTpLink)\n  DEVICE_MODEL := TD-W8970\n  DEVICE_VARIANT := v1\n  TPLINK_FLASHLAYOUT := 8Mltq\n  TPLINK_HWID := 0x89700001\n  TPLINK_HWREV := 1\n  IMAGE_SIZE := 7680k\n  DEVICE_PACKAGES:= kmod-ath9k wpad-basic-wolfssl kmod-usb-dwc2 kmod-usb-ledtrig-usbport\n  SUPPORTED_DEVICES += TDW8970\nendef\nTARGET_DEVICES += tplink_tdw8970\n\ndefine Device/tplink_tdw8980\n  $(Device/dsa-migration)\n  $(Device/lantiqTpLink)\n  DEVICE_MODEL := TD-W8980\n  DEVICE_VARIANT := v1\n  TPLINK_FLASHLAYOUT := 8Mltq\n  TPLINK_HWID := 0x89800001\n  TPLINK_HWREV := 14\n  IMAGE_SIZE := 7680k\n  DEVICE_PACKAGES:= kmod-ath9k kmod-owl-loader wpad-basic-wolfssl kmod-usb-dwc2 kmod-usb-ledtrig-usbport\n  SUPPORTED_DEVICES += TDW8980\nendef\nTARGET_DEVICES += tplink_tdw8980\n\ndefine Device/tplink_vr200\n  $(Device/dsa-migration)\n  $(Device/lantiqTpLink)\n  DEVICE_MODEL := Archer VR200\n  DEVICE_VARIANT := v1\n  TPLINK_FLASHLAYOUT := 16Mltq\n  TPLINK_HWID := 0x63e64801\n  TPLINK_HWREV := 0x53\n  IMAGE_SIZE := 15808k\n  DEVICE_PACKAGES:= kmod-mt76x0e wpad-basic-wolfssl kmod-usb-dwc2 kmod-usb-ledtrig-usbport\n  SUPPORTED_DEVICES += VR200\nendef\nTARGET_DEVICES += tplink_vr200\n\ndefine Device/tplink_vr200v\n  $(Device/dsa-migration)\n  $(Device/lantiqTpLink)\n  DEVICE_MODEL := Archer VR200v\n  DEVICE_VARIANT := v1\n  TPLINK_FLASHLAYOUT := 16Mltq\n  TPLINK_HWID := 0x73b70801\n  TPLINK_HWREV := 0x2f\n  IMAGE_SIZE := 15808k\n  DEVICE_PACKAGES:= kmod-mt76x0e wpad-basic-wolfssl kmod-usb-dwc2 kmod-usb-ledtrig-usbport kmod-ltq-tapi kmod-ltq-vmmc\n  SUPPORTED_DEVICES += VR200v\nendef\nTARGET_DEVICES += tplink_vr200v\n"
  },
  {
    "path": "target/linux/lantiq/image/ubinize-overlay.cfg",
    "content": "[rootfs]\n# Volume mode (other option is static)\nmode=ubi\n# Source image\nimage=root.squashfs\n# Volume ID in UBI image\nvol_id=0\n# Allow for dynamic resize\nvol_type=dynamic\n# Volume name\nvol_name=rootfs\n[rootfs_data]\n# Volume mode (other option is static)\nmode=ubi\n# Volume ID in UBI image\nvol_id=1\n# Allow for dynamic resize\nvol_type=dynamic\n# Volume name\nvol_name=rootfs_data\nvol_size=1MiB\n# Autoresize volume at first mount\nvol_flags=autoresize\n"
  },
  {
    "path": "target/linux/lantiq/image/ubinize.cfg",
    "content": "[rootfs]\n# Volume mode (other option is static)\nmode=ubi\n# Source image\nimage=root.ubifs\n# Volume ID in UBI image\nvol_id=0\n# Allow for dynamic resize\nvol_type=dynamic\n# Volume name\nvol_name=rootfs\n# Autoresize volume at first mount\nvol_flags=autoresize\n\n"
  },
  {
    "path": "target/linux/lantiq/image/vr9.mk",
    "content": "DEVICE_VARS += NETGEAR_BOARD_ID NETGEAR_HW_ID\n\ndefine Device/dsa-migration\n  DEVICE_COMPAT_VERSION := 1.1\n  DEVICE_COMPAT_MESSAGE := Config cannot be migrated from swconfig to DSA\nendef\n\ndefine Device/alphanetworks_asl56026\n  $(Device/dsa-migration)\n  DEVICE_VENDOR := Alpha\n  DEVICE_MODEL := ASL56026\n  DEVICE_ALT0_VENDOR := BT Openreach\n  DEVICE_ALT0_MODEL := ECI VDSL Modem V-2FUb/I\n  IMAGE_SIZE := 7488k\nendef\nTARGET_DEVICES += alphanetworks_asl56026\n\ndefine Device/arcadyan_arv7519rw22\n  $(Device/dsa-migration)\n  DEVICE_VENDOR := Arcadyan\n  DEVICE_MODEL := ARV7519RW22\n  DEVICE_ALT0_VENDOR := Orange\n  DEVICE_ALT0_MODEL := Livebox\n  DEVICE_ALT0_VARIANT := 2.1\n  DEVICE_ALT1_VENDOR := Astoria Networks\n  DEVICE_ALT1_MODEL := ARV7519RW22\n  KERNEL_SIZE := 2048k\n  IMAGE_SIZE := 31232k\n  DEVICE_PACKAGES := kmod-usb-dwc2\n  SUPPORTED_DEVICES += ARV7519RW22\n  DEFAULT := n\nendef\nTARGET_DEVICES += arcadyan_arv7519rw22\n\ndefine Device/arcadyan_vg3503j\n  $(Device/dsa-migration)\n  DEVICE_VENDOR := BT Openreach\n  DEVICE_MODEL := ECI VDSL Modem V-2FUb/R\n  IMAGE_SIZE := 8000k\n  SUPPORTED_DEVICES += VG3503J\nendef\nTARGET_DEVICES += arcadyan_vg3503j\n\ndefine Device/arcadyan_vgv7510kw22-brn\n  $(Device/dsa-migration)\n  $(Device/lantiqBrnImage)\n  DEVICE_VENDOR := Arcadyan\n  DEVICE_MODEL := VGV7510KW22\n  DEVICE_VARIANT := BRN\n  DEVICE_ALT0_VENDOR := o2\n  DEVICE_ALT0_MODEL := Box 6431\n  DEVICE_ALT0_VARIANT := BRN\n  IMAGE_SIZE := 7168k\n  SIGNATURE := BRNDA6431\n  MAGIC := 0x12345678\n  CRC32_POLY := 0x04c11db7\n  DEVICE_PACKAGES := kmod-rt2800-pci wpad-basic-wolfssl kmod-usb-dwc2 kmod-ltq-tapi kmod-ltq-vmmc\n  SUPPORTED_DEVICES += VGV7510KW22BRN\nendef\nTARGET_DEVICES += arcadyan_vgv7510kw22-brn\n\ndefine Device/arcadyan_vgv7510kw22-nor\n  $(Device/dsa-migration)\n  DEVICE_VENDOR := Arcadyan\n  DEVICE_MODEL := VGV7510KW22\n  DEVICE_VARIANT := NOR\n  DEVICE_ALT0_VENDOR := o2\n  DEVICE_ALT0_MODEL := Box 6431\n  DEVICE_ALT0_VARIANT := NOR\n  IMAGE_SIZE := 15232k\n  DEVICE_PACKAGES := kmod-rt2800-pci wpad-basic-wolfssl kmod-usb-dwc2 kmod-ltq-tapi kmod-ltq-vmmc\n  SUPPORTED_DEVICES += VGV7510KW22NOR\nendef\nTARGET_DEVICES += arcadyan_vgv7510kw22-nor\n\ndefine Device/arcadyan_vgv7519-brn\n  $(Device/dsa-migration)\n  $(Device/lantiqBrnImage)\n  DEVICE_VENDOR := Arcadyan\n  DEVICE_MODEL := VGV7519\n  DEVICE_VARIANT := BRN\n  DEVICE_ALT0_VENDOR := KPN\n  DEVICE_ALT0_MODEL := Experiabox 8\n  DEVICE_ALT0_VARIANT := BRN\n  IMAGE_SIZE := 7168k\n  SIGNATURE := 5D00008000\n  MAGIC := 0x12345678\n  CRC32_POLY := 0x2083b8ed\n  DEVICE_PACKAGES := kmod-rt2800-pci wpad-basic-wolfssl kmod-usb-dwc2 kmod-ltq-tapi kmod-ltq-vmmc\n  SUPPORTED_DEVICES += VGV7519BRN\nendef\nTARGET_DEVICES += arcadyan_vgv7519-brn\n\ndefine Device/arcadyan_vgv7519-nor\n  $(Device/dsa-migration)\n  DEVICE_VENDOR := Arcadyan\n  DEVICE_MODEL := VGV7519\n  DEVICE_VARIANT := NOR\n  DEVICE_ALT0_VENDOR := KPN\n  DEVICE_ALT0_MODEL := Experiabox 8\n  DEVICE_ALT0_VARIANT := NOR\n  IMAGE_SIZE := 15360k\n  DEVICE_PACKAGES := kmod-rt2800-pci wpad-basic-wolfssl kmod-usb-dwc2 kmod-ltq-tapi kmod-ltq-vmmc\n  SUPPORTED_DEVICES += VGV7519NOR\nendef\nTARGET_DEVICES += arcadyan_vgv7519-nor\n\ndefine Device/avm_fritz3370\n  $(Device/dsa-migration)\n  $(Device/AVM)\n  $(Device/NAND)\n  DEVICE_MODEL := FRITZ!Box 3370\n  DEVICE_VARIANT := Rev. 2\n  KERNEL_SIZE := 4096k\n  UBINIZE_OPTS := -E 5\n  IMAGES += eva-kernel.bin eva-filesystem.bin\n  IMAGE/eva-kernel.bin := append-kernel\n  IMAGE/eva-filesystem.bin := append-ubi\n  DEVICE_PACKAGES := kmod-ath9k wpad-basic-wolfssl kmod-usb-dwc2 fritz-tffs\nendef\n\ndefine Device/avm_fritz3370-rev2-hynix\n  $(Device/dsa-migration)\n  $(Device/avm_fritz3370)\n  DEVICE_MODEL := FRITZ!Box 3370\n  DEVICE_VARIANT := Rev. 2 (Hynix NAND)\nendef\nTARGET_DEVICES += avm_fritz3370-rev2-hynix\n\ndefine Device/avm_fritz3370-rev2-micron\n  $(Device/dsa-migration)\n  $(Device/avm_fritz3370)\n  DEVICE_MODEL := FRITZ!Box 3370\n  DEVICE_VARIANT := Rev. 2 (Micron NAND)\nendef\nTARGET_DEVICES += avm_fritz3370-rev2-micron\n\ndefine Device/avm_fritz3390\n  $(Device/dsa-migration)\n  $(Device/AVM)\n  $(Device/NAND)\n  DEVICE_MODEL := FRITZ!Box 3390\n  KERNEL_SIZE := 4096k\n  IMAGE_SIZE := 49152k\n  DEVICE_PACKAGES := kmod-ath9k kmod-owl-loader wpad-basic-wolfssl \\\n\tkmod-usb-dwc2 fritz-tffs\nendef\nTARGET_DEVICES += avm_fritz3390\n\ndefine Device/avm_fritz7360sl\n  $(Device/dsa-migration)\n  $(Device/AVM)\n  DEVICE_MODEL := FRITZ!Box 7360 SL\n  IMAGE_SIZE := 15744k\n  DEVICE_PACKAGES := kmod-ath9k kmod-owl-loader wpad-basic-wolfssl kmod-usb-dwc2\n  SUPPORTED_DEVICES += FRITZ7360SL\nendef\nTARGET_DEVICES += avm_fritz7360sl\n\ndefine Device/avm_fritz7360-v2\n  $(Device/dsa-migration)\n  $(Device/AVM)\n  DEVICE_MODEL := FRITZ!Box 7360\n  DEVICE_VARIANT := v2\n  IMAGE_SIZE := 32128k\n  DEVICE_PACKAGES := kmod-ath9k kmod-owl-loader wpad-basic-wolfssl kmod-usb-dwc2\nendef\nTARGET_DEVICES += avm_fritz7360-v2\n\ndefine Device/avm_fritz7362sl\n  $(Device/dsa-migration)\n  $(Device/AVM)\n  $(Device/NAND)\n  DEVICE_MODEL := FRITZ!Box 7362 SL\n  KERNEL_SIZE := 4096k\n  IMAGE_SIZE := 49152k\n  DEVICE_PACKAGES := kmod-ath9k kmod-owl-loader wpad-basic-wolfssl kmod-usb-dwc2 fritz-tffs\nendef\nTARGET_DEVICES += avm_fritz7362sl\n\ndefine Device/avm_fritz7412\n  $(Device/dsa-migration)\n  $(Device/AVM)\n  $(Device/NAND)\n  DEVICE_MODEL := FRITZ!Box 7412\n  BOARD_NAME := FRITZ7412\n  KERNEL_SIZE := 4096k\n  IMAGE_SIZE := 49152k\n  DEVICE_PACKAGES := kmod-ath9k kmod-owl-loader wpad-basic-wolfssl fritz-tffs-nand fritz-caldata\nendef\nTARGET_DEVICES += avm_fritz7412\n\ndefine Device/avm_fritz7430\n  $(Device/dsa-migration)\n  $(Device/AVM)\n  $(Device/NAND)\n  DEVICE_MODEL := FRITZ!Box 7430\n  KERNEL_SIZE := 4096k\n  IMAGE_SIZE := 49152k\n  DEVICE_PACKAGES := kmod-ath9k kmod-owl-loader wpad-basic-wolfssl fritz-tffs-nand fritz-caldata\nendef\nTARGET_DEVICES += avm_fritz7430\n\ndefine Device/bt_homehub-v5a\n  $(Device/dsa-migration)\n  $(Device/NAND)\n  DEVICE_VENDOR := British Telecom (BT)\n  DEVICE_MODEL := Home Hub 5\n  DEVICE_VARIANT := Type A\n  BOARD_NAME := BTHOMEHUBV5A\n  DEVICE_PACKAGES := kmod-ath9k kmod-owl-loader \\\n\tkmod-ath10k-ct ath10k-firmware-qca988x-ct wpad-basic-wolfssl kmod-usb-dwc2\n  SUPPORTED_DEVICES += BTHOMEHUBV5A\nendef\nTARGET_DEVICES += bt_homehub-v5a\n\ndefine Device/buffalo_wbmr-300hpd\n  $(Device/dsa-migration)\n  DEVICE_VENDOR := Buffalo\n  DEVICE_MODEL := WBMR-300HPD\n  IMAGE_SIZE := 15616k\n  DEVICE_PACKAGES := kmod-mt7603 wpad-basic-wolfssl kmod-usb-dwc2\n  SUPPORTED_DEVICES += WBMR300\nendef\nTARGET_DEVICES += buffalo_wbmr-300hpd\n\ndefine Device/lantiq_easy80920-nand\n  $(Device/dsa-migration)\n  $(Device/lantiqFullImage)\n  DEVICE_VENDOR := Lantiq\n  DEVICE_MODEL := VR9 EASY80920\n  DEVICE_VARIANT := NAND\n  IMAGE_SIZE := 64512k\n  DEVICE_PACKAGES := kmod-ath9k kmod-owl-loader wpad-basic-wolfssl kmod-usb-dwc2 kmod-usb-ledtrig-usbport\nendef\nTARGET_DEVICES += lantiq_easy80920-nand\n\ndefine Device/lantiq_easy80920-nor\n  $(Device/dsa-migration)\n  DEVICE_VENDOR := Lantiq\n  DEVICE_MODEL := VR9 EASY80920\n  DEVICE_VARIANT := NOR\n  IMAGE_SIZE := 7936k\n  DEVICE_PACKAGES := kmod-ath9k kmod-owl-loader wpad-basic-wolfssl kmod-usb-dwc2 kmod-usb-ledtrig-usbport\nendef\nTARGET_DEVICES += lantiq_easy80920-nor\n\ndefine Device/netgear_dm200\n  $(Device/dsa-migration)\n  DEVICE_VENDOR := NETGEAR\n  DEVICE_MODEL := DM200\n  IMAGES := sysupgrade.bin factory.img\n  IMAGE/sysupgrade.bin := append-kernel | \\\n\tpad-offset 64k 64 | append-uImage-fakehdr filesystem | \\\n\tpad-offset 64k 64 | append-uImage-fakehdr filesystem | \\\n\tappend-rootfs | pad-rootfs | check-size | append-metadata\n  IMAGE/factory.img := $$(IMAGE/sysupgrade.bin) | netgear-dni\n  IMAGE_SIZE := 7872k\n  NETGEAR_BOARD_ID := DM200\n  NETGEAR_HW_ID := 29765233+8+0+64+0+0\nendef\nTARGET_DEVICES += netgear_dm200\n\ndefine Device/zyxel_p-2812hnu-f1\n  $(Device/dsa-migration)\n  $(Device/NAND)\n  DEVICE_VENDOR := ZyXEL\n  DEVICE_MODEL := P-2812HNU\n  DEVICE_VARIANT := F1\n  BOARD_NAME := P2812HNUF1\n  DEVICE_PACKAGES := kmod-rt2800-pci wpad-basic-wolfssl kmod-usb-dwc2 kmod-usb-ledtrig-usbport\n  KERNEL_SIZE := 3072k\n  SUPPORTED_DEVICES += P2812HNUF1\nendef\nTARGET_DEVICES += zyxel_p-2812hnu-f1\n\ndefine Device/zyxel_p-2812hnu-f3\n  $(Device/dsa-migration)\n  $(Device/NAND)\n  DEVICE_VENDOR := ZyXEL\n  DEVICE_MODEL := P-2812HNU\n  DEVICE_VARIANT := F3\n  BOARD_NAME := P2812HNUF3\n  DEVICE_PACKAGES := kmod-rt2800-pci wpad-basic-wolfssl kmod-usb-dwc2\n  KERNEL_SIZE := 2048k\n  SUPPORTED_DEVICES += P2812HNUF3\n  DEFAULT := n\nendef\nTARGET_DEVICES += zyxel_p-2812hnu-f3\n"
  },
  {
    "path": "target/linux/lantiq/image/xway_legacy.mk",
    "content": "define Device/arcadyan_arv4518pwr01\n  DEVICE_VENDOR := Arcadyan\n  DEVICE_MODEL := ARV4518PWR01\n  IMAGE_SIZE := 3776k\n  DEVICE_PACKAGES := kmod-usb-dwc2 kmod-usb-ledtrig-usbport \\\n\tkmod-ltq-adsl-danube-mei kmod-ltq-adsl-danube \\\n\tkmod-ltq-adsl-danube-fw-a kmod-ltq-atm-danube \\\n\tltq-adsl-app ppp-mod-pppoa \\\n\tkmod-ath5k wpad-basic-wolfssl\n  SUPPORTED_DEVICES += ARV4518PWR01\n  DEFAULT := n\nendef\nTARGET_DEVICES += arcadyan_arv4518pwr01\n\ndefine Device/arcadyan_arv4518pwr01a\n  DEVICE_VENDOR := Arcadyan\n  DEVICE_MODEL := ARV4518PWR01A\n  IMAGE_SIZE := 3776k\n  DEVICE_PACKAGES := kmod-usb-dwc2 kmod-usb-ledtrig-usbport \\\n\tkmod-ltq-adsl-danube-mei kmod-ltq-adsl-danube \\\n\tkmod-ltq-adsl-danube-fw-a kmod-ltq-atm-danube \\\n\tltq-adsl-app ppp-mod-pppoa \\\n\tkmod-ath5k wpad-basic-wolfssl\n  SUPPORTED_DEVICES += ARV4518PWR01A\n  DEFAULT := n\nendef\nTARGET_DEVICES += arcadyan_arv4518pwr01a\n\ndefine Device/arcadyan_arv4520pw\n  DEVICE_VENDOR := Arcadyan\n  DEVICE_MODEL := ARV4520PW\n  DEVICE_ALT0_VENDOR := Vodafone\n  DEVICE_ALT0_MODEL := Easybox 800\n  DEVICE_ALT1_VENDOR := Airties\n  DEVICE_ALT1_MODEL := WAV-281\n  IMAGE_SIZE := 3648k\n  DEVICE_PACKAGES := kmod-usb-dwc2 kmod-usb-ledtrig-usbport \\\n\tkmod-ltq-adsl-danube-mei kmod-ltq-adsl-danube \\\n\tkmod-ltq-adsl-danube-fw-b kmod-ltq-atm-danube \\\n\tltq-adsl-app ppp-mod-pppoa \\\n\tkmod-rt61-pci wpad-basic-wolfssl\n  SUPPORTED_DEVICES += ARV4520PW\n  DEFAULT := n\nendef\nTARGET_DEVICES += arcadyan_arv4520pw\n\ndefine Device/arcadyan_arv4525pw\n  DEVICE_VENDOR := Arcadyan\n  DEVICE_MODEL := ARV4525PW\n  DEVICE_ALT0_VENDOR := Telekom\n  DEVICE_ALT0_MODEL := Speedport W502V\n  DEVICE_ALT0_VARIANT := Typ A\n  IMAGE_SIZE := 3776k\n  DEVICE_PACKAGES := kmod-ath5k wpad-basic-wolfssl \\\n\tkmod-ltq-adsl-danube-mei kmod-ltq-adsl-danube \\\n\tkmod-ltq-adsl-danube-fw-b kmod-ltq-atm-danube \\\n\tltq-adsl-app ppp-mod-pppoa -swconfig\n  SUPPORTED_DEVICES += ARV4525PW\n  DEFAULT := n\nendef\nTARGET_DEVICES += arcadyan_arv4525pw\n\ndefine Device/arcadyan_arv452cqw\n  DEVICE_VENDOR := Arcadyan\n  DEVICE_MODEL := ARV452CQW\n  DEVICE_ALT0_VENDOR := Vodafone\n  DEVICE_ALT0_MODEL := Easybox 801\n  IMAGE_SIZE := 3776k\n  DEVICE_PACKAGES := kmod-usb-dwc2 kmod-usb-ledtrig-usbport \\\n\tkmod-ath5k wpad-basic-wolfssl \\\n\tkmod-ltq-adsl-danube-mei kmod-ltq-adsl-danube \\\n\tkmod-ltq-adsl-danube-fw-b kmod-ltq-atm-danube \\\n\tltq-adsl-app ppp-mod-pppoa\n  SUPPORTED_DEVICES += ARV452CQW\n  DEFAULT := n\nendef\nTARGET_DEVICES += arcadyan_arv452cqw\n"
  },
  {
    "path": "target/linux/lantiq/modules.mk",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2010 OpenWrt.org\n\nI2C_LANTIQ_MODULES:= \\\n  CONFIG_I2C_LANTIQ:drivers/i2c/busses/i2c-lantiq\n\ndefine KernelPackage/i2c-lantiq\n  TITLE:=Lantiq I2C controller\n  $(call i2c_defaults,$(I2C_LANTIQ_MODULES),52)\n  DEPENDS:=+kmod-i2c-core @TARGET_lantiq_falcon\nendef\n\ndefine KernelPackage/i2c-lantiq/description\n  Kernel support for the Lantiq/Falcon I2C controller\nendef\n\n$(eval $(call KernelPackage,i2c-lantiq))\n\n"
  },
  {
    "path": "target/linux/lantiq/patches-5.10/0001-MIPS-lantiq-add-pcie-driver.patch",
    "content": "From 6f933347d0b4ed02d9534f5fa07f7b99f13eeaa1 Mon Sep 17 00:00:00 2001\nFrom: John Crispin <blogic@openwrt.org>\nDate: Thu, 7 Aug 2014 18:12:28 +0200\nSubject: [PATCH 01/36] MIPS: lantiq: add pcie driver\n\nSigned-off-by: John Crispin <blogic@openwrt.org>\n---\n arch/mips/lantiq/Kconfig           |   10 +\n arch/mips/lantiq/xway/sysctrl.c    |    2 +\n arch/mips/pci/Makefile             |    2 +\n arch/mips/pci/fixup-lantiq-pcie.c  |   82 +++\n arch/mips/pci/fixup-lantiq.c       |    5 +-\n arch/mips/pci/ifxmips_pci_common.h |   57 ++\n arch/mips/pci/ifxmips_pcie.c       | 1099 ++++++++++++++++++++++++++++++\n arch/mips/pci/ifxmips_pcie.h       |  135 ++++\n arch/mips/pci/ifxmips_pcie_ar10.h  |  290 ++++++++\n arch/mips/pci/ifxmips_pcie_msi.c   |  392 +++++++++++\n arch/mips/pci/ifxmips_pcie_phy.c   |  478 +++++++++++++\n arch/mips/pci/ifxmips_pcie_pm.c    |  176 +++++\n arch/mips/pci/ifxmips_pcie_pm.h    |   36 +\n arch/mips/pci/ifxmips_pcie_reg.h   | 1001 +++++++++++++++++++++++++++\n arch/mips/pci/ifxmips_pcie_vr9.h   |  271 ++++++++\n arch/mips/pci/pci.c                |   25 +\n arch/mips/pci/pcie-lantiq.h        | 1305 ++++++++++++++++++++++++++++++++++++\n drivers/pci/pcie/aer/Kconfig       |    2 +-\n include/linux/pci.h                |    2 +\n include/linux/pci_ids.h            |    6 +\n 20 files changed, 5374 insertions(+), 2 deletions(-)\n create mode 100644 arch/mips/pci/fixup-lantiq-pcie.c\n create mode 100644 arch/mips/pci/ifxmips_pci_common.h\n create mode 100644 arch/mips/pci/ifxmips_pcie.c\n create mode 100644 arch/mips/pci/ifxmips_pcie.h\n create mode 100644 arch/mips/pci/ifxmips_pcie_ar10.h\n create mode 100644 arch/mips/pci/ifxmips_pcie_msi.c\n create mode 100644 arch/mips/pci/ifxmips_pcie_phy.c\n create mode 100644 arch/mips/pci/ifxmips_pcie_pm.c\n create mode 100644 arch/mips/pci/ifxmips_pcie_pm.h\n create mode 100644 arch/mips/pci/ifxmips_pcie_reg.h\n create mode 100644 arch/mips/pci/ifxmips_pcie_vr9.h\n create mode 100644 arch/mips/pci/pcie-lantiq.h\n\n--- a/arch/mips/lantiq/Kconfig\n+++ b/arch/mips/lantiq/Kconfig\n@@ -20,6 +20,7 @@ config SOC_XWAY\n \tbool \"XWAY\"\n \tselect SOC_TYPE_XWAY\n \tselect HAVE_PCI\n+\tselect ARCH_SUPPORTS_MSI\n \tselect MFD_SYSCON\n \tselect MFD_CORE\n \n@@ -52,4 +53,13 @@ config PCI_LANTIQ\n \tbool \"PCI Support\"\n \tdepends on SOC_XWAY && PCI\n \n+config PCIE_LANTIQ\n+\tbool \"PCIE Support\"\n+\tdepends on SOC_XWAY && PCI\n+\n+config PCIE_LANTIQ_MSI\n+\tbool\n+\tdepends on PCIE_LANTIQ && PCI_MSI\n+\tdefault y\n+\n endif\n--- a/arch/mips/pci/Makefile\n+++ b/arch/mips/pci/Makefile\n@@ -43,6 +43,8 @@ obj-$(CONFIG_PCI_LANTIQ)\t+= pci-lantiq.o\n obj-$(CONFIG_SOC_MT7620)\t+= pci-mt7620.o\n obj-$(CONFIG_SOC_RT288X)\t+= pci-rt2880.o\n obj-$(CONFIG_SOC_RT3883)\t+= pci-rt3883.o\n+obj-$(CONFIG_PCIE_LANTIQ)\t+= ifxmips_pcie_phy.o ifxmips_pcie.o fixup-lantiq-pcie.o\n+obj-$(CONFIG_PCIE_LANTIQ_MSI)\t+= pcie-lantiq-msi.o\n obj-$(CONFIG_TANBAC_TB0219)\t+= fixup-tb0219.o\n obj-$(CONFIG_TANBAC_TB0226)\t+= fixup-tb0226.o\n obj-$(CONFIG_TANBAC_TB0287)\t+= fixup-tb0287.o\n--- /dev/null\n+++ b/arch/mips/pci/fixup-lantiq-pcie.c\n@@ -0,0 +1,74 @@\n+/******************************************************************************\n+**\n+** FILE NAME    : ifxmips_fixup_pcie.c\n+** PROJECT      : IFX UEIP for VRX200\n+** MODULES      : PCIe \n+**\n+** DATE         : 02 Mar 2009\n+** AUTHOR       : Lei Chuanhua\n+** DESCRIPTION  : PCIe Root Complex Driver\n+** COPYRIGHT    :       Copyright (c) 2009\n+**                      Infineon Technologies AG\n+**                      Am Campeon 1-12, 85579 Neubiberg, Germany\n+**\n+**    This program is free software; you can redistribute it and/or modify\n+**    it under the terms of the GNU General Public License as published by\n+**    the Free Software Foundation; either version 2 of the License, or\n+**    (at your option) any later version.\n+** HISTORY\n+** $Version $Date        $Author         $Comment\n+** 0.0.1    17 Mar,2009  Lei Chuanhua    Initial version\n+*******************************************************************************/\n+/*!\n+ \\file ifxmips_fixup_pcie.c\n+ \\ingroup IFX_PCIE  \n+ \\brief PCIe Fixup functions source file\n+*/\n+#include <linux/pci.h>\n+#include <linux/pci_regs.h>\n+#include <linux/pci_ids.h>\n+\n+#include <lantiq_soc.h>\n+\n+#include \"pcie-lantiq.h\"\n+\n+static void\n+ifx_pcie_fixup_resource(struct pci_dev *dev)\n+{\n+    u32 reg;\n+\n+    IFX_PCIE_PRINT(PCIE_MSG_FIXUP, \"%s dev %s: enter\\n\", __func__, pci_name(dev));\n+\n+    printk(\"%s: fixup host controller %s (%04x:%04x)\\n\", \n+        __func__, pci_name(dev), dev->vendor, dev->device); \n+\n+   /* Setup COMMAND register */\n+    reg = PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER /* | \n+          PCI_COMMAND_INTX_DISABLE */| PCI_COMMAND_SERR;\n+    pci_write_config_word(dev, PCI_COMMAND, reg);\n+    IFX_PCIE_PRINT(PCIE_MSG_FIXUP, \"%s dev %s: exit\\n\", __func__, pci_name(dev));\n+}\n+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INFINEON, PCI_DEVICE_ID_INFINEON_PCIE, ifx_pcie_fixup_resource);\n+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LANTIQ, PCI_VENDOR_ID_LANTIQ, ifx_pcie_fixup_resource);\n+\n+static void\n+ifx_pcie_rc_class_early_fixup(struct pci_dev *dev)\n+{\n+    IFX_PCIE_PRINT(PCIE_MSG_FIXUP, \"%s dev %s: enter\\n\", __func__, pci_name(dev));\n+\n+    if (dev->devfn == PCI_DEVFN(0, 0) &&\n+        (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) {\n+\n+        dev->class = (PCI_CLASS_BRIDGE_PCI << 8) | (dev->class & 0xff);\n+\n+        printk(KERN_INFO \"%s: fixed pcie host bridge to pci-pci bridge\\n\", __func__);\n+    }\n+    IFX_PCIE_PRINT(PCIE_MSG_FIXUP, \"%s dev %s: exit\\n\", __func__, pci_name(dev));\n+    mdelay(10);\n+}\n+\n+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INFINEON, PCI_DEVICE_ID_INFINEON_PCIE,\n+     ifx_pcie_rc_class_early_fixup);\n+\n+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LANTIQ, PCI_DEVICE_ID_LANTIQ_PCIE,\n+     ifx_pcie_rc_class_early_fixup);\n--- a/arch/mips/pci/fixup-lantiq.c\n+++ b/arch/mips/pci/fixup-lantiq.c\n@@ -6,12 +6,19 @@\n \n #include <linux/of_irq.h>\n #include <linux/of_pci.h>\n+#include <linux/pci.h>\n+#include \"ifxmips_pci_common.h\"\n \n int (*ltq_pci_plat_arch_init)(struct pci_dev *dev) = NULL;\n int (*ltq_pci_plat_dev_init)(struct pci_dev *dev) = NULL;\n \n int pcibios_plat_dev_init(struct pci_dev *dev)\n {\n+#ifdef CONFIG_PCIE_LANTIQ\n+\tif (pci_find_capability(dev, PCI_CAP_ID_EXP))\n+\t\tifx_pcie_bios_plat_dev_init(dev);\n+#endif\n+\n \tif (ltq_pci_plat_arch_init)\n \t\treturn ltq_pci_plat_arch_init(dev);\n \n@@ -23,5 +30,10 @@ int pcibios_plat_dev_init(struct pci_dev\n \n int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)\n {\n+#ifdef CONFIG_PCIE_LANTIQ\n+\tif (pci_find_capability(dev, PCI_CAP_ID_EXP))\n+\t\treturn ifx_pcie_bios_map_irq(dev, slot, pin);\n+#endif\n+\n \treturn of_irq_parse_and_map_pci(dev, slot, pin);\n }\n--- /dev/null\n+++ b/arch/mips/pci/ifxmips_pci_common.h\n@@ -0,0 +1,53 @@\n+/******************************************************************************\n+**\n+** FILE NAME    : ifxmips_pci_common.h\n+** PROJECT      : IFX UEIP\n+** MODULES      : PCI subsystem\n+**\n+** DATE         : 30 June 2009\n+** AUTHOR       : Lei Chuanhua\n+** DESCRIPTION  : PCIe Root Complex Driver\n+** COPYRIGHT    :       Copyright (c) 2009\n+**                      Infineon Technologies AG\n+**                      Am Campeon 1-12, 85579 Neubiberg, Germany\n+**\n+**    This program is free software; you can redistribute it and/or modify\n+**    it under the terms of the GNU General Public License as published by\n+**    the Free Software Foundation; either version 2 of the License, or\n+**    (at your option) any later version.\n+** HISTORY\n+** $Version $Date        $Author         $Comment\n+** 0.0.1    30 June,2009  Lei Chuanhua    Initial version\n+*******************************************************************************/\n+\n+#ifndef IFXMIPS_PCI_COMMON_H\n+#define IFXMIPS_PCI_COMMON_H\n+#include <linux/version.h>\n+/*!\n+ \\defgroup IFX_PCI_COM  IFX PCI/PCIe common parts for OS integration  \n+ \\brief  PCI/PCIe common parts\n+*/\n+\n+/*!\n+ \\defgroup IFX_PCI_COM_OS OS APIs\n+ \\ingroup IFX_PCI_COM\n+ \\brief PCI/PCIe bus driver OS interface functions\n+*/\n+/*!\n+  \\file ifxmips_pci_common.h\n+  \\ingroup IFX_PCI_COM\n+  \\brief PCI/PCIe bus driver common OS header file\n+*/\n+#define IFX_PCI_CONST const\n+#ifdef CONFIG_IFX_PCI\n+extern int ifx_pci_bios_map_irq(IFX_PCI_CONST struct pci_dev *dev, u8 slot, u8 pin);\n+extern int ifx_pci_bios_plat_dev_init(struct pci_dev *dev);\n+#endif /* COFNIG_IFX_PCI */\n+\n+#ifdef CONFIG_PCIE_LANTIQ\n+extern int ifx_pcie_bios_map_irq(IFX_PCI_CONST struct pci_dev *dev, u8 slot, u8 pin);\n+extern int ifx_pcie_bios_plat_dev_init(struct pci_dev *dev);\n+#endif\n+\n+#endif /* IFXMIPS_PCI_COMMON_H */\n+\n--- /dev/null\n+++ b/arch/mips/pci/ifxmips_pcie.c\n@@ -0,0 +1,1092 @@\n+/*\n+ *  This program is free software; you can redistribute it and/or modify it\n+ *  under the terms of the GNU General Public License version 2 as published\n+ *  by the Free Software Foundation.\n+ *\n+ *  Copyright (C) 2009 Lei Chuanhua <chuanhua.lei@infineon.com>\n+ *  Copyright (C) 2013 John Crispin <blogic@openwrt.org>\n+ */\n+\n+#include <linux/types.h>\n+#include <linux/pci.h>\n+#include <linux/kernel.h>\n+#include <linux/init.h>\n+#include <linux/delay.h>\n+#include <linux/mm.h>\n+#include <asm/paccess.h>\n+#include <linux/pci.h>\n+#include <linux/pci_regs.h>\n+#include <linux/module.h>\n+\n+#include \"ifxmips_pcie.h\"\n+#include \"ifxmips_pcie_reg.h\"\n+\n+/* Enable 32bit io due to its mem mapped io nature */\n+#define IFX_PCIE_ERROR_INT\n+#define IFX_PCIE_IO_32BIT\n+\n+#define IFX_PCIE_IR                     (INT_NUM_IM4_IRL0 + 25)\n+#define IFX_PCIE_INTA                   (INT_NUM_IM4_IRL0 + 8)\n+#define IFX_PCIE_INTB                   (INT_NUM_IM4_IRL0 + 9)\n+#define IFX_PCIE_INTC                   (INT_NUM_IM4_IRL0 + 10)\n+#define IFX_PCIE_INTD                   (INT_NUM_IM4_IRL0 + 11)\n+#define MS(_v, _f)  (((_v) & (_f)) >> _f##_S)\n+#define SM(_v, _f)  (((_v) << _f##_S) & (_f))\n+#define IFX_REG_SET_BIT(_f, _r) \\\n+\tIFX_REG_W32((IFX_REG_R32((_r)) &~ (_f)) | (_f), (_r))\n+\n+#define IFX_PCIE_LTSSM_ENABLE_TIMEOUT 10\n+\n+static DEFINE_SPINLOCK(ifx_pcie_lock);\n+\n+u32 g_pcie_debug_flag = PCIE_MSG_ANY & (~PCIE_MSG_CFG);\n+\n+static ifx_pcie_irq_t pcie_irqs[IFX_PCIE_CORE_NR] = {\n+    {\n+        .ir_irq = {\n+            .irq  = IFX_PCIE_IR,\n+            .name = \"ifx_pcie_rc0\",\n+        },\n+\n+        .legacy_irq = {\n+            {\n+                .irq_bit = PCIE_IRN_INTA,\n+                .irq     = IFX_PCIE_INTA,\n+            },\n+            {\n+                .irq_bit = PCIE_IRN_INTB,\n+                .irq     = IFX_PCIE_INTB,\n+            },\n+            {\n+                .irq_bit = PCIE_IRN_INTC,\n+                .irq     = IFX_PCIE_INTC,\n+            },\n+            {\n+                .irq_bit = PCIE_IRN_INTD,\n+                .irq     = IFX_PCIE_INTD,\n+            },\n+        },\n+    },\n+\n+};\n+\n+void ifx_pcie_debug(const char *fmt, ...)\n+{\n+\tstatic char buf[256] = {0};      /* XXX */\n+\tva_list ap;\n+\n+\tva_start(ap, fmt);\n+\tvsnprintf(buf, sizeof(buf), fmt, ap);\n+\tva_end(ap);\n+\n+\tprintk(\"%s\", buf);\n+}\n+\n+\n+static inline int pcie_ltssm_enable(int pcie_port)\n+{\n+\tint i;\n+\n+\t/* Enable LTSSM */\n+\tIFX_REG_W32(PCIE_RC_CCR_LTSSM_ENABLE, PCIE_RC_CCR(pcie_port));\n+\n+\t/* Wait for the link to come up */\n+\tfor (i = 0; i < IFX_PCIE_LTSSM_ENABLE_TIMEOUT; i++) {\n+\t\tif (!(IFX_REG_R32(PCIE_LCTLSTS(pcie_port)) & PCIE_LCTLSTS_RETRAIN_PENDING))\n+\t\t\treturn 0;\n+\t\tudelay(10);\n+\t}\n+\n+\tprintk(\"%s link timeout!!!!!\\n\", __func__);\n+\treturn -1;\n+}\n+\n+static inline void pcie_status_register_clear(int pcie_port)\n+{\n+\tIFX_REG_W32(0, PCIE_RC_DR(pcie_port));\n+\tIFX_REG_W32(0, PCIE_PCICMDSTS(pcie_port));\n+\tIFX_REG_W32(0, PCIE_DCTLSTS(pcie_port));\n+\tIFX_REG_W32(0, PCIE_LCTLSTS(pcie_port));\n+\tIFX_REG_W32(0, PCIE_SLCTLSTS(pcie_port));\n+\tIFX_REG_W32(0, PCIE_RSTS(pcie_port));\n+\tIFX_REG_W32(0, PCIE_UES_R(pcie_port));\n+\tIFX_REG_W32(0, PCIE_UEMR(pcie_port));\n+\tIFX_REG_W32(0, PCIE_UESR(pcie_port));\n+\tIFX_REG_W32(0, PCIE_CESR(pcie_port));\n+\tIFX_REG_W32(0, PCIE_CEMR(pcie_port));\n+\tIFX_REG_W32(0, PCIE_RESR(pcie_port));\n+\tIFX_REG_W32(0, PCIE_PVCCRSR(pcie_port));\n+\tIFX_REG_W32(0, PCIE_VC0_RSR0(pcie_port));\n+\tIFX_REG_W32(0, PCIE_TPFCS(pcie_port));\n+\tIFX_REG_W32(0, PCIE_TNPFCS(pcie_port));\n+\tIFX_REG_W32(0, PCIE_TCFCS(pcie_port));\n+\tIFX_REG_W32(0, PCIE_QSR(pcie_port));\n+\tIFX_REG_W32(0, PCIE_IOBLSECS(pcie_port));\n+}\n+\n+static inline int ifx_pcie_link_up(int pcie_port)\n+{\n+    return (IFX_REG_R32(PCIE_PHY_SR(pcie_port)) & PCIE_PHY_SR_PHY_LINK_UP) ? 1 : 0;\n+}\n+\n+\n+static inline void pcie_mem_io_setup(int pcie_port)\n+{\n+    u32 reg;\n+    /*\n+     * BAR[0:1] readonly register \n+     * RC contains only minimal BARs for packets mapped to this device \n+     * Mem/IO filters defines a range of memory occupied by memory mapped IO devices that\n+     * reside on the downstream side fo the bridge.\n+     */\n+    reg = SM((PCIE_MEM_PHY_PORT_TO_END(pcie_port) >> 20), PCIE_MBML_MEM_LIMIT_ADDR)\n+        | SM((PCIE_MEM_PHY_PORT_TO_BASE(pcie_port) >> 20), PCIE_MBML_MEM_BASE_ADDR);\n+\n+    IFX_REG_W32(reg, PCIE_MBML(pcie_port));\n+\n+\n+#ifdef IFX_PCIE_PREFETCH_MEM_64BIT\n+    reg = SM((PCIE_MEM_PHY_PORT_TO_END(pcie_port) >> 20), PCIE_PMBL_END_ADDR)\n+        | SM((PCIE_MEM_PHY_PORT_TO_BASE(pcie_port) >> 20), PCIE_PMBL_UPPER_12BIT)\n+        | PCIE_PMBL_64BIT_ADDR;\n+    IFX_REG_W32(reg, PCIE_PMBL(pcie_port));\n+\n+    /* Must configure upper 32bit */\n+    IFX_REG_W32(0, PCIE_PMBU32(pcie_port));\n+    IFX_REG_W32(0, PCIE_PMLU32(pcie_port));\n+#else\n+    /* PCIe_PBML, same as MBML */\n+    IFX_REG_W32(IFX_REG_R32(PCIE_MBML(pcie_port)), PCIE_PMBL(pcie_port));\n+#endif \n+\n+    /* IO Address Range */\n+    reg = SM((PCIE_IO_PHY_PORT_TO_END(pcie_port) >> 12), PCIE_IOBLSECS_IO_LIMIT_ADDR)\n+        | SM((PCIE_IO_PHY_PORT_TO_BASE(pcie_port) >> 12), PCIE_IOBLSECS_IO_BASE_ADDR);\n+#ifdef IFX_PCIE_IO_32BIT    \n+    reg |= PCIE_IOBLSECS_32BIT_IO_ADDR;\n+#endif /* IFX_PCIE_IO_32BIT */\n+    IFX_REG_W32(reg, PCIE_IOBLSECS(pcie_port));\n+\n+#ifdef IFX_PCIE_IO_32BIT\n+    reg = SM((PCIE_IO_PHY_PORT_TO_END(pcie_port) >> 16), PCIE_IO_BANDL_UPPER_16BIT_IO_LIMIT)\n+        | SM((PCIE_IO_PHY_PORT_TO_BASE(pcie_port) >> 16), PCIE_IO_BANDL_UPPER_16BIT_IO_BASE);\n+    IFX_REG_W32(reg, PCIE_IO_BANDL(pcie_port));\n+\n+#endif /* IFX_PCIE_IO_32BIT */\n+}\n+\n+static inline void\n+pcie_device_setup(int pcie_port)\n+{\n+    u32 reg;\n+\n+    /* Device capability register, set up Maximum payload size */\n+    reg = IFX_REG_R32(PCIE_DCAP(pcie_port));\n+    reg |= PCIE_DCAP_ROLE_BASE_ERR_REPORT;\n+    reg |= SM(PCIE_MAX_PAYLOAD_128, PCIE_DCAP_MAX_PAYLOAD_SIZE);\n+\n+    /* Only available for EP */\n+    reg &= ~(PCIE_DCAP_EP_L0S_LATENCY | PCIE_DCAP_EP_L1_LATENCY);\n+    IFX_REG_W32(reg, PCIE_DCAP(pcie_port));\n+\n+    /* Device control and status register */\n+    /* Set Maximum Read Request size for the device as a Requestor */\n+    reg = IFX_REG_R32(PCIE_DCTLSTS(pcie_port));\n+\n+    /* \n+     * Request size can be larger than the MPS used, but the completions returned \n+     * for the read will be bounded by the MPS size.\n+     * In our system, Max request size depends on AHB burst size. It is 64 bytes.\n+     * but we set it as 128 as minimum one.\n+     */\n+    reg |= SM(PCIE_MAX_PAYLOAD_128, PCIE_DCTLSTS_MAX_READ_SIZE)\n+            | SM(PCIE_MAX_PAYLOAD_128, PCIE_DCTLSTS_MAX_PAYLOAD_SIZE);\n+\n+    /* Enable relaxed ordering, no snoop, and all kinds of errors */\n+    reg |= PCIE_DCTLSTS_RELAXED_ORDERING_EN | PCIE_DCTLSTS_ERR_EN | PCIE_DCTLSTS_NO_SNOOP_EN;\n+\n+    IFX_REG_W32(reg, PCIE_DCTLSTS(pcie_port));\n+}\n+\n+static inline void\n+pcie_link_setup(int pcie_port)\n+{\n+    u32 reg;\n+\n+    /*\n+     * XXX, Link capability register, bit 18 for EP CLKREQ# dynamic clock management for L1, L2/3 CPM \n+     * L0s is reported during link training via TS1 order set by N_FTS\n+     */\n+    reg = IFX_REG_R32(PCIE_LCAP(pcie_port));\n+    reg &= ~PCIE_LCAP_L0S_EIXT_LATENCY;\n+    reg |= SM(3, PCIE_LCAP_L0S_EIXT_LATENCY);\n+    IFX_REG_W32(reg, PCIE_LCAP(pcie_port));\n+\n+    /* Link control and status register */\n+    reg = IFX_REG_R32(PCIE_LCTLSTS(pcie_port));\n+\n+    /* Link Enable, ASPM enabled  */\n+    reg &= ~PCIE_LCTLSTS_LINK_DISABLE;\n+\n+#ifdef CONFIG_PCIEASPM\n+    /*  \n+     * We use the same physical reference clock that the platform provides on the connector \n+     * It paved the way for ASPM to calculate the new exit Latency\n+     */\n+    reg |= PCIE_LCTLSTS_SLOT_CLK_CFG;\n+    reg |= PCIE_LCTLSTS_COM_CLK_CFG;\n+    /*\n+     * We should disable ASPM by default except that we have dedicated power management support\n+     * Enable ASPM will cause the system hangup/instability, performance degration\n+     */\n+    reg |= PCIE_LCTLSTS_ASPM_ENABLE;\n+#else\n+    reg &= ~PCIE_LCTLSTS_ASPM_ENABLE;\n+#endif /* CONFIG_PCIEASPM */\n+\n+    /* \n+     * The maximum size of any completion with data packet is bounded by the MPS setting \n+     * in  device control register \n+     */\n+\n+    /* RCB may cause multiple split transactions, two options available, we use 64 byte RCB */\n+    reg &= ~ PCIE_LCTLSTS_RCB128;\n+\n+    IFX_REG_W32(reg, PCIE_LCTLSTS(pcie_port));\n+}\n+\n+static inline void pcie_error_setup(int pcie_port)\n+{\n+\tu32 reg;\n+\n+\t/* \n+\t* Forward ERR_COR, ERR_NONFATAL, ERR_FATAL to the backbone \n+\t* Poisoned write TLPs and completions indicating poisoned TLPs will set the PCIe_PCICMDSTS.MDPE \n+\t*/\n+\treg = IFX_REG_R32(PCIE_INTRBCTRL(pcie_port));\n+\treg |= PCIE_INTRBCTRL_SERR_ENABLE | PCIE_INTRBCTRL_PARITY_ERR_RESP_ENABLE;\n+\n+\tIFX_REG_W32(reg, PCIE_INTRBCTRL(pcie_port));\n+\n+\t/* Uncorrectable Error Mask Register, Unmask <enable> all bits in PCIE_UESR */\n+\treg = IFX_REG_R32(PCIE_UEMR(pcie_port));\n+\treg &= ~PCIE_ALL_UNCORRECTABLE_ERR;\n+\tIFX_REG_W32(reg, PCIE_UEMR(pcie_port));\n+\n+\t/* Uncorrectable Error Severity Register, ALL errors are FATAL */\n+\tIFX_REG_W32(PCIE_ALL_UNCORRECTABLE_ERR, PCIE_UESR(pcie_port));\n+\n+\t/* Correctable Error Mask Register, unmask <enable> all bits */\n+\treg = IFX_REG_R32(PCIE_CEMR(pcie_port));\n+\treg &= ~PCIE_CORRECTABLE_ERR;\n+\tIFX_REG_W32(reg, PCIE_CEMR(pcie_port));\n+\n+\t/* Advanced Error Capabilities and Control Registr */\n+\treg = IFX_REG_R32(PCIE_AECCR(pcie_port));\n+\treg |= PCIE_AECCR_ECRC_CHECK_EN | PCIE_AECCR_ECRC_GEN_EN;\n+\tIFX_REG_W32(reg, PCIE_AECCR(pcie_port));\n+\n+\t/* Root Error Command Register, Report all types of errors */\n+\treg = IFX_REG_R32(PCIE_RECR(pcie_port));\n+\treg |= PCIE_RECR_ERR_REPORT_EN;\n+\tIFX_REG_W32(reg, PCIE_RECR(pcie_port));\n+\n+\t/* Clear the Root status register */\n+\treg = IFX_REG_R32(PCIE_RESR(pcie_port));\n+\tIFX_REG_W32(reg, PCIE_RESR(pcie_port));\n+}\n+\n+static inline void pcie_port_logic_setup(int pcie_port)\n+{\n+\tu32 reg;\n+\n+\t/* FTS number, default 12, increase to 63, may increase time from/to L0s to L0  */\n+\treg = IFX_REG_R32(PCIE_AFR(pcie_port));\n+\treg &= ~(PCIE_AFR_FTS_NUM | PCIE_AFR_COM_FTS_NUM);\n+\treg |= SM(PCIE_AFR_FTS_NUM_DEFAULT, PCIE_AFR_FTS_NUM)\n+\t\t| SM(PCIE_AFR_FTS_NUM_DEFAULT, PCIE_AFR_COM_FTS_NUM);\n+\t/* L0s and L1 entry latency */\n+\treg &= ~(PCIE_AFR_L0S_ENTRY_LATENCY | PCIE_AFR_L1_ENTRY_LATENCY);\n+\treg |= SM(PCIE_AFR_L0S_ENTRY_LATENCY_DEFAULT, PCIE_AFR_L0S_ENTRY_LATENCY)\n+\t\t| SM(PCIE_AFR_L1_ENTRY_LATENCY_DEFAULT, PCIE_AFR_L1_ENTRY_LATENCY);\n+\tIFX_REG_W32(reg, PCIE_AFR(pcie_port));\n+\n+\n+\t/* Port Link Control Register */\n+\treg = IFX_REG_R32(PCIE_PLCR(pcie_port));\n+\treg |= PCIE_PLCR_DLL_LINK_EN;  /* Enable the DLL link */\n+\tIFX_REG_W32(reg, PCIE_PLCR(pcie_port));\n+\n+\t/* Lane Skew Register */\n+\treg = IFX_REG_R32(PCIE_LSR(pcie_port));\n+\t/* Enable ACK/NACK and FC */\n+\treg &= ~(PCIE_LSR_ACKNAK_DISABLE | PCIE_LSR_FC_DISABLE);\n+\tIFX_REG_W32(reg, PCIE_LSR(pcie_port));\n+\n+\t/* Symbol Timer Register and Filter Mask Register 1 */\n+\treg = IFX_REG_R32(PCIE_STRFMR(pcie_port));\n+\n+\t/* Default SKP interval is very accurate already, 5us */\n+\t/* Enable IO/CFG transaction */\n+\treg |= PCIE_STRFMR_RX_CFG_TRANS_ENABLE | PCIE_STRFMR_RX_IO_TRANS_ENABLE;\n+\t/* Disable FC WDT */\n+\treg &= ~PCIE_STRFMR_FC_WDT_DISABLE;\n+\tIFX_REG_W32(reg, PCIE_STRFMR(pcie_port));\n+\n+\t/* Filter Masker Register 2 */\n+\treg = IFX_REG_R32(PCIE_FMR2(pcie_port));\n+\treg |= PCIE_FMR2_VENDOR_MSG1_PASSED_TO_TRGT1 | PCIE_FMR2_VENDOR_MSG0_PASSED_TO_TRGT1;\n+\tIFX_REG_W32(reg, PCIE_FMR2(pcie_port));\n+\n+\t/* VC0 Completion Receive Queue Control Register */\n+\treg = IFX_REG_R32(PCIE_VC0_CRQCR(pcie_port));\n+\treg &= ~PCIE_VC0_CRQCR_CPL_TLP_QUEUE_MODE;\n+\treg |= SM(PCIE_VC0_TLP_QUEUE_MODE_BYPASS, PCIE_VC0_CRQCR_CPL_TLP_QUEUE_MODE);\n+\tIFX_REG_W32(reg, PCIE_VC0_CRQCR(pcie_port));\n+}\n+\n+static inline void pcie_rc_cfg_reg_setup(int pcie_port)\n+{\n+\tu32 reg;\n+\n+\t/* Disable LTSSM */\n+\tIFX_REG_W32(0, PCIE_RC_CCR(pcie_port)); /* Disable LTSSM */\n+\n+\tpcie_mem_io_setup(pcie_port);\n+\n+\t/* XXX, MSI stuff should only apply to EP */\n+\t/* MSI Capability: Only enable 32-bit addresses */\n+\treg = IFX_REG_R32(PCIE_MCAPR(pcie_port));\n+\treg &= ~PCIE_MCAPR_ADDR64_CAP;\n+\n+\treg |= PCIE_MCAPR_MSI_ENABLE;\n+\n+\t/* Disable multiple message */\n+\treg &= ~(PCIE_MCAPR_MULTI_MSG_CAP | PCIE_MCAPR_MULTI_MSG_ENABLE);\n+\tIFX_REG_W32(reg, PCIE_MCAPR(pcie_port));\n+\n+\n+\t/* Enable PME, Soft reset enabled */\n+\treg = IFX_REG_R32(PCIE_PM_CSR(pcie_port));\n+\treg |= PCIE_PM_CSR_PME_ENABLE | PCIE_PM_CSR_SW_RST;\n+\tIFX_REG_W32(reg, PCIE_PM_CSR(pcie_port));\n+\n+\t/* setup the bus */\n+\treg = SM(0, PCIE_BNR_PRIMARY_BUS_NUM) | SM(1, PCIE_PNR_SECONDARY_BUS_NUM) | SM(0xFF, PCIE_PNR_SUB_BUS_NUM);\n+\tIFX_REG_W32(reg, PCIE_BNR(pcie_port));\n+\n+\n+\tpcie_device_setup(pcie_port);\n+\tpcie_link_setup(pcie_port);\n+\tpcie_error_setup(pcie_port);\n+\n+\t/* Root control and capabilities register */\n+\treg = IFX_REG_R32(PCIE_RCTLCAP(pcie_port));\n+\treg |= PCIE_RCTLCAP_SERR_ENABLE | PCIE_RCTLCAP_PME_INT_EN;\n+\tIFX_REG_W32(reg, PCIE_RCTLCAP(pcie_port));\n+\n+\t/* Port VC Capability Register 2 */\n+\treg = IFX_REG_R32(PCIE_PVC2(pcie_port));\n+\treg &= ~PCIE_PVC2_VC_ARB_WRR;\n+\treg |= PCIE_PVC2_VC_ARB_16P_FIXED_WRR;\n+\tIFX_REG_W32(reg, PCIE_PVC2(pcie_port));\n+\n+\t/* VC0 Resource Capability Register */\n+\treg = IFX_REG_R32(PCIE_VC0_RC(pcie_port));\n+\treg &= ~PCIE_VC0_RC_REJECT_SNOOP;\n+\tIFX_REG_W32(reg, PCIE_VC0_RC(pcie_port));\n+\n+\tpcie_port_logic_setup(pcie_port);\n+}\n+\n+static int ifx_pcie_wait_phy_link_up(int pcie_port)\n+{\n+#define IFX_PCIE_PHY_LINK_UP_TIMEOUT  1000 /* XXX, tunable */\n+    int i;\n+\n+    /* Wait for PHY link is up */\n+    for (i = 0; i < IFX_PCIE_PHY_LINK_UP_TIMEOUT; i++) {\n+        if (ifx_pcie_link_up(pcie_port)) {\n+            break;\n+        }\n+        udelay(100);\n+    }\n+    if (i >= IFX_PCIE_PHY_LINK_UP_TIMEOUT) {\n+        printk(KERN_ERR \"%s timeout\\n\", __func__);\n+        return -1;\n+    }\n+\n+    /* Check data link up or not */\n+    if (!(IFX_REG_R32(PCIE_RC_DR(pcie_port)) & PCIE_RC_DR_DLL_UP)) {\n+        printk(KERN_ERR \"%s DLL link is still down\\n\", __func__);\n+        return -1;\n+    }\n+\n+    /* Check Data link active or not */\n+    if (!(IFX_REG_R32(PCIE_LCTLSTS(pcie_port)) & PCIE_LCTLSTS_DLL_ACTIVE)) {\n+        printk(KERN_ERR \"%s DLL is not active\\n\", __func__);\n+        return -1;\n+    }\n+    return 0;\n+}\n+\n+static inline int pcie_app_loigc_setup(int pcie_port)\n+{\n+\t/* supress ahb bus errrors */\n+\tIFX_REG_W32(PCIE_AHB_CTRL_BUS_ERROR_SUPPRESS, PCIE_AHB_CTRL(pcie_port));\n+\n+\t/* Pull PCIe EP out of reset */\n+\tpcie_device_rst_deassert(pcie_port);\n+\n+\t/* Start LTSSM training between RC and EP */\n+\tpcie_ltssm_enable(pcie_port);\n+\n+\t/* Check PHY status after enabling LTSSM */\n+\tif (ifx_pcie_wait_phy_link_up(pcie_port) != 0)\n+\t\treturn -1;\n+\n+\treturn 0;\n+}\n+\n+/*\n+ * The numbers below are directly from the PCIe spec table 3-4/5. \n+ */\n+static inline void pcie_replay_time_update(int pcie_port)\n+{\n+\tu32 reg;\n+\tint nlw;\n+\tint rtl;\n+\n+\treg = IFX_REG_R32(PCIE_LCTLSTS(pcie_port));\n+\n+\tnlw = MS(reg, PCIE_LCTLSTS_NEGOTIATED_LINK_WIDTH);\n+\tswitch (nlw) {\n+\tcase PCIE_MAX_LENGTH_WIDTH_X1:\n+\t\trtl = 1677;\n+\t\tbreak;\n+\tcase PCIE_MAX_LENGTH_WIDTH_X2:\n+\t\trtl = 867;\n+\t\tbreak;\n+\tcase PCIE_MAX_LENGTH_WIDTH_X4:\n+\t\trtl = 462;\n+\t\tbreak;\n+\tcase PCIE_MAX_LENGTH_WIDTH_X8:\n+\t\trtl = 258;\n+\t\tbreak;\n+\tdefault:\n+\t\trtl = 1677;\n+\t\tbreak;\n+\t}\n+\treg = IFX_REG_R32(PCIE_ALTRT(pcie_port));\n+\treg &= ~PCIE_ALTRT_REPLAY_TIME_LIMIT;\n+\treg |= SM(rtl, PCIE_ALTRT_REPLAY_TIME_LIMIT);\n+\tIFX_REG_W32(reg, PCIE_ALTRT(pcie_port));\n+}\n+\n+/*\n+ * Table 359 Enhanced Configuration Address Mapping1)\n+ * 1) This table is defined in Table 7-1, page 341, PCI Express Base Specification v1.1\n+ * Memory Address PCI Express Configuration Space\n+ * A[(20+n-1):20] Bus Number 1 < n < 8\n+ * A[19:15] Device Number\n+ * A[14:12] Function Number\n+ * A[11:8] Extended Register Number\n+ * A[7:2] Register Number\n+ * A[1:0] Along with size of the access, used to generate Byte Enables\n+ * For VR9, only the address bits [22:0] are mapped to the configuration space:\n+ * . Address bits [22:20] select the target bus (1-of-8)1)\n+ * . Address bits [19:15] select the target device (1-of-32) on the bus\n+ * . Address bits [14:12] select the target function (1-of-8) within the device.\n+ * . Address bits [11:2] selects the target dword (1-of-1024) within the selected function.s configuration space\n+ * . Address bits [1:0] define the start byte location within the selected dword.\n+ */\n+static inline u32 pcie_bus_addr(u8 bus_num, u16 devfn, int where)\n+{\n+\tu32 addr;\n+\tu8  bus;\n+\n+\tif (!bus_num) {\n+\t\t/* type 0 */\n+\t\taddr = ((PCI_SLOT(devfn) & 0x1F) << 15) | ((PCI_FUNC(devfn) & 0x7) << 12) | ((where & 0xFFF)& ~3);\n+\t} else {\n+\t\tbus = bus_num;\n+\t\t/* type 1, only support 8 buses  */\n+\t\taddr = ((bus & 0x7) << 20) | ((PCI_SLOT(devfn) & 0x1F) << 15) |\n+\t\t\t((PCI_FUNC(devfn) & 0x7) << 12) | ((where & 0xFFF) & ~3);\n+\t}\n+\treturn addr;\n+}\n+\n+static int pcie_valid_config(int pcie_port, int bus, int dev)\n+{\n+\t/* RC itself */\n+\tif ((bus == 0) && (dev == 0)) {\n+\t\treturn 1;\n+\t}\n+\n+\t/* No physical link */\n+\tif (!ifx_pcie_link_up(pcie_port)) {\n+\t\treturn 0;\n+\t}\n+\n+\t/* Bus zero only has RC itself\n+\t* XXX, check if EP will be integrated \n+\t*/\n+\tif ((bus == 0) && (dev != 0)) {\n+\t\treturn 0;\n+\t}\n+\n+\t/* Maximum 8 buses supported for VRX */\n+\tif (bus > 9) {\n+\t\treturn 0;\n+\t}\n+\n+\t/* \n+\t * PCIe is PtP link, one bus only supports only one device \n+\t * except bus zero and PCIe switch which is virtual bus device\n+\t * The following two conditions really depends on the system design\n+\t * and attached the device.\n+\t * XXX, how about more new switch\n+\t*/\n+\tif ((bus == 1) && (dev != 0)) {\n+\t\treturn 0;\n+\t}\n+\n+\tif ((bus >= 3) && (dev != 0)) {\n+\t\treturn 0;\n+\t}\n+\treturn 1;\n+}\n+\n+static inline u32 ifx_pcie_cfg_rd(int pcie_port, u32 reg)\n+{\n+    return IFX_REG_R32((volatile u32 *)(PCIE_CFG_PORT_TO_BASE(pcie_port) + reg));\n+}\n+\n+static inline void ifx_pcie_cfg_wr(int pcie_port, unsigned int reg, u32 val)\n+{\n+    IFX_REG_W32( val, (volatile u32 *)(PCIE_CFG_PORT_TO_BASE(pcie_port) + reg));\n+}\n+\n+static inline u32 ifx_pcie_rc_cfg_rd(int pcie_port, u32 reg)\n+{\n+    return IFX_REG_R32((volatile u32 *)(PCIE_RC_PORT_TO_BASE(pcie_port) + reg));\n+}\n+\n+static inline void ifx_pcie_rc_cfg_wr(int pcie_port, unsigned int reg, u32 val)\n+{\n+\tIFX_REG_W32(val, (volatile u32 *)(PCIE_RC_PORT_TO_BASE(pcie_port) + reg));\n+}\n+\n+u32 ifx_pcie_bus_enum_read_hack(int where, u32 value)\n+{\n+\tu32 tvalue = value;\n+\n+\tif (where == PCI_PRIMARY_BUS) {\n+\t\tu8 primary, secondary, subordinate;\n+\n+\t\tprimary = tvalue & 0xFF;\n+\t\tsecondary = (tvalue >> 8) & 0xFF;\n+\t\tsubordinate = (tvalue >> 16) & 0xFF;\n+\t\tprimary += pcibios_1st_host_bus_nr();\n+\t\tsecondary += pcibios_1st_host_bus_nr();\n+\t\tsubordinate += pcibios_1st_host_bus_nr();\n+\t\ttvalue = (tvalue & 0xFF000000) | (u32)primary | (u32)(secondary << 8) | (u32)(subordinate << 16);\n+\t}\n+\treturn tvalue;\n+}\n+\n+u32 ifx_pcie_bus_enum_write_hack(int where, u32 value)\n+{\n+    u32 tvalue = value;\n+\n+    if (where == PCI_PRIMARY_BUS) {\n+        u8 primary, secondary, subordinate;\n+\n+        primary = tvalue & 0xFF;\n+        secondary = (tvalue >> 8) & 0xFF;\n+        subordinate = (tvalue >> 16) & 0xFF;\n+        if (primary > 0 && primary != 0xFF) {\n+            primary -= pcibios_1st_host_bus_nr();\n+        }\n+\n+        if (secondary > 0 && secondary != 0xFF) {\n+            secondary -= pcibios_1st_host_bus_nr();\n+        }\n+        if (subordinate > 0 && subordinate != 0xFF) {\n+            subordinate -= pcibios_1st_host_bus_nr();\n+        }\n+        tvalue = (tvalue & 0xFF000000) | (u32)primary | (u32)(secondary << 8) | (u32)(subordinate << 16);\n+    }\n+    else if (where == PCI_SUBORDINATE_BUS) {\n+        u8 subordinate = tvalue & 0xFF;\n+\n+        subordinate = subordinate > 0 ? subordinate - pcibios_1st_host_bus_nr() : 0;\n+        tvalue = subordinate;\n+    }\n+    return tvalue;\n+}\n+\n+static int ifx_pcie_read_config(struct pci_bus *bus, u32 devfn,\n+\t\t\t\tint where, int size, u32 *value)\n+{\n+    u32 data = 0;\n+    int bus_number = bus->number;\n+    static const u32 mask[8] = {0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0};\n+    int ret = PCIBIOS_SUCCESSFUL;\n+    struct ifx_pci_controller *ctrl = bus->sysdata;\n+    int pcie_port = ctrl->port;\n+\n+    if (unlikely(size != 1 && size != 2 && size != 4)){\n+        ret = PCIBIOS_BAD_REGISTER_NUMBER;\n+        goto out;\n+    }\n+\n+    /* Make sure the address is aligned to natural boundary */\n+    if (unlikely(((size - 1) & where))) {\n+        ret = PCIBIOS_BAD_REGISTER_NUMBER;\n+        goto out;\n+    }\n+\n+    /* \n+     * If we are second controller, we have to cheat OS so that it assume \n+     * its bus number starts from 0 in host controller\n+     */\n+    bus_number = ifx_pcie_bus_nr_deduct(bus_number, pcie_port);\n+\n+    /* \n+     * We need to force the bus number to be zero on the root \n+     * bus. Linux numbers the 2nd root bus to start after all \n+     * busses on root 0. \n+     */ \n+    if (bus->parent == NULL) {\n+        bus_number = 0; \n+    }\n+\n+    /* \n+     * PCIe only has a single device connected to it. It is \n+     * always device ID 0. Don't bother doing reads for other \n+     * device IDs on the first segment. \n+     */ \n+    if ((bus_number == 0) && (PCI_SLOT(devfn) != 0)) {\n+        ret = PCIBIOS_FUNC_NOT_SUPPORTED;\n+        goto out; \n+    }\n+\n+    if (pcie_valid_config(pcie_port, bus_number, PCI_SLOT(devfn)) == 0) {\n+        *value = 0xffffffff;\n+        ret = PCIBIOS_DEVICE_NOT_FOUND;\n+        goto out;\n+    }\n+\n+    PCIE_IRQ_LOCK(ifx_pcie_lock);\n+    if (bus_number == 0) { /* RC itself */\n+        u32 t;\n+\n+        t = (where & ~3);\n+        data = ifx_pcie_rc_cfg_rd(pcie_port, t);\n+    } else {\n+        u32 addr = pcie_bus_addr(bus_number, devfn, where);\n+\n+        data = ifx_pcie_cfg_rd(pcie_port, addr);\n+    #ifdef CONFIG_IFX_PCIE_HW_SWAP\n+            data = le32_to_cpu(data);\n+    #endif /* CONFIG_IFX_PCIE_HW_SWAP */\n+    }\n+    /* To get a correct PCI topology, we have to restore the bus number to OS */\n+    data = ifx_pcie_bus_enum_hack(bus, devfn, where, data, pcie_port, 1);\n+\n+    PCIE_IRQ_UNLOCK(ifx_pcie_lock);\n+\n+    *value = (data >> (8 * (where & 3))) & mask[size & 7];\n+out:\n+    return ret;\n+}\n+\n+static u32 ifx_pcie_size_to_value(int where, int size, u32 data, u32 value)\n+{\n+\tu32 shift;\n+\tu32 tdata = data;\n+\n+\tswitch (size) {\n+\tcase 1:\n+\t\tshift = (where & 0x3) << 3;\n+\t\ttdata &= ~(0xffU << shift);\n+\t\ttdata |= ((value & 0xffU) << shift);\n+\t\tbreak;\n+\tcase 2:\n+\t\tshift = (where & 3) << 3;\n+\t\ttdata &= ~(0xffffU << shift);\n+\t\ttdata |= ((value & 0xffffU) << shift);\n+\t\tbreak;\n+\tcase 4:\n+\t\ttdata = value;\n+\t\tbreak;\n+\t}\n+\treturn tdata;\n+}\n+\n+static int ifx_pcie_write_config(struct pci_bus *bus, u32 devfn,\n+\t\t\t\tint where, int size, u32 value)\n+{\n+\tint bus_number = bus->number;\n+\tint ret = PCIBIOS_SUCCESSFUL;\n+\tstruct ifx_pci_controller *ctrl = bus->sysdata;\n+\tint pcie_port = ctrl->port;\n+\tu32 tvalue = value;\n+\tu32 data;\n+\n+\t/* Make sure the address is aligned to natural boundary */\n+\tif (unlikely(((size - 1) & where))) {\n+\t\tret = PCIBIOS_BAD_REGISTER_NUMBER;\n+\t\tgoto out;\n+\t}\n+\t/* \n+\t* If we are second controller, we have to cheat OS so that it assume \n+\t* its bus number starts from 0 in host controller\n+\t*/\n+\tbus_number = ifx_pcie_bus_nr_deduct(bus_number, pcie_port);\n+\n+\t/* \n+\t* We need to force the bus number to be zero on the root \n+\t* bus. Linux numbers the 2nd root bus to start after all \n+\t* busses on root 0. \n+\t*/ \n+\tif (bus->parent == NULL) {\n+\t\tbus_number = 0; \n+\t}\n+\n+\tif (pcie_valid_config(pcie_port, bus_number, PCI_SLOT(devfn)) == 0) {\n+\t\tret = PCIBIOS_DEVICE_NOT_FOUND;\n+\t\tgoto out;\n+\t}\n+\n+\t/* XXX, some PCIe device may need some delay */\n+\tPCIE_IRQ_LOCK(ifx_pcie_lock);\n+\n+\t/* \n+\t* To configure the correct bus topology using native way, we have to cheat Os so that\n+\t* it can configure the PCIe hardware correctly.\n+\t*/\n+\ttvalue = ifx_pcie_bus_enum_hack(bus, devfn, where, value, pcie_port, 0);\n+\n+\tif (bus_number == 0) { /* RC itself */\n+\t\tu32 t;\n+\n+\t\tt = (where & ~3);\n+\t\tdata = ifx_pcie_rc_cfg_rd(pcie_port, t);\n+\n+\t\tdata = ifx_pcie_size_to_value(where, size, data, tvalue);\n+\n+\t\tifx_pcie_rc_cfg_wr(pcie_port, t, data);\n+\t} else {\n+\t\tu32 addr = pcie_bus_addr(bus_number, devfn, where);\n+\n+\t\tdata = ifx_pcie_cfg_rd(pcie_port, addr);\n+#ifdef CONFIG_IFX_PCIE_HW_SWAP\n+\t\tdata = le32_to_cpu(data);\n+#endif\n+\n+\t\tdata = ifx_pcie_size_to_value(where, size, data, tvalue);\n+#ifdef CONFIG_IFX_PCIE_HW_SWAP\n+\t\tdata = cpu_to_le32(data);\n+#endif\n+\t\tifx_pcie_cfg_wr(pcie_port, addr, data);\n+\t}\n+\tPCIE_IRQ_UNLOCK(ifx_pcie_lock);\n+out:\n+\treturn ret;\n+}\n+\n+static struct resource ifx_pcie_io_resource = {\n+\t.name\t= \"PCIe0 I/O space\",\n+\t.start\t= PCIE_IO_PHY_BASE,\n+\t.end\t= PCIE_IO_PHY_END,\n+\t.flags\t= IORESOURCE_IO,\n+};\n+\n+static struct resource ifx_pcie_mem_resource = {\n+\t.name\t= \"PCIe0 Memory space\",\n+\t.start\t= PCIE_MEM_PHY_BASE,\n+\t.end\t= PCIE_MEM_PHY_END,\n+\t.flags\t= IORESOURCE_MEM,\n+};\n+\n+static struct pci_ops ifx_pcie_ops = {\n+\t.read\t= ifx_pcie_read_config,\n+\t.write\t= ifx_pcie_write_config,\n+};\n+\n+static struct ifx_pci_controller ifx_pcie_controller[IFX_PCIE_CORE_NR] = {\n+    {\n+        .pcic = {\n+            .pci_ops      = &ifx_pcie_ops,\n+            .mem_resource = &ifx_pcie_mem_resource,\n+            .io_resource  = &ifx_pcie_io_resource,\n+         },\n+         .port = IFX_PCIE_PORT0,\n+    },\n+};\n+\n+#ifdef IFX_PCIE_ERROR_INT\n+\n+static irqreturn_t pcie_rc_core_isr(int irq, void *dev_id)\n+{\n+\tstruct ifx_pci_controller *ctrl = (struct ifx_pci_controller *)dev_id;\n+\tint pcie_port = ctrl->port;\n+\tu32 reg;\n+\n+\tpr_debug(\"PCIe RC error intr %d\\n\", irq);\n+\treg = IFX_REG_R32(PCIE_IRNCR(pcie_port));\n+\treg &= PCIE_RC_CORE_COMBINED_INT;\n+\tIFX_REG_W32(reg, PCIE_IRNCR(pcie_port));\n+\n+\treturn IRQ_HANDLED;\n+}\n+\n+static int\n+pcie_rc_core_int_init(int pcie_port)\n+{\n+\tint ret;\n+\n+\t/* Enable core interrupt */\n+\tIFX_REG_SET_BIT(PCIE_RC_CORE_COMBINED_INT, PCIE_IRNEN(pcie_port));\n+\n+\t/* Clear it first */\n+\tIFX_REG_SET_BIT(PCIE_RC_CORE_COMBINED_INT, PCIE_IRNCR(pcie_port));\n+\tret = request_irq(pcie_irqs[pcie_port].ir_irq.irq, pcie_rc_core_isr, 0,\n+\t\tpcie_irqs[pcie_port].ir_irq.name, &ifx_pcie_controller[pcie_port]);\n+\tif (ret)\n+\t\tprintk(KERN_ERR \"%s request irq %d failed\\n\", __func__, IFX_PCIE_IR);\n+\n+\treturn ret;\n+}\n+#endif\n+\n+int ifx_pcie_bios_map_irq(IFX_PCI_CONST struct pci_dev *dev, u8 slot, u8 pin)\n+{\n+\tu32 irq_bit = 0;\n+\tint irq = 0;\n+\tstruct ifx_pci_controller *ctrl = dev->bus->sysdata;\n+\tint pcie_port = ctrl->port;\n+\n+\tprintk(\"%s port %d dev %s slot %d pin %d \\n\", __func__, pcie_port, pci_name(dev), slot, pin);\n+\n+\tif ((pin == PCIE_LEGACY_DISABLE) || (pin > PCIE_LEGACY_INT_MAX)) {\n+\t\tprintk(KERN_WARNING \"WARNING: dev %s: invalid interrupt pin %d\\n\", pci_name(dev), pin);\n+\t\treturn -1;\n+\t}\n+\n+\t/* Pin index so minus one */\n+\tirq_bit = pcie_irqs[pcie_port].legacy_irq[pin - 1].irq_bit;\n+\tirq = pcie_irqs[pcie_port].legacy_irq[pin - 1].irq;\n+\tIFX_REG_SET_BIT(irq_bit, PCIE_IRNEN(pcie_port));\n+\tIFX_REG_SET_BIT(irq_bit, PCIE_IRNCR(pcie_port));\n+\tprintk(\"%s dev %s irq %d assigned\\n\", __func__, pci_name(dev), irq);\n+\treturn irq;\n+}\n+\n+int  ifx_pcie_bios_plat_dev_init(struct pci_dev *dev)\n+{\n+    u16 config;\n+#ifdef IFX_PCIE_ERROR_INT\n+    u32 dconfig; \n+    int pos;\n+#endif\n+\n+    /* Enable reporting System errors and parity errors on all devices */ \n+    /* Enable parity checking and error reporting */ \n+    pci_read_config_word(dev, PCI_COMMAND, &config);\n+    config |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR /*| PCI_COMMAND_INVALIDATE |\n+          PCI_COMMAND_FAST_BACK*/;\n+    pci_write_config_word(dev, PCI_COMMAND, config);\n+\n+    if (dev->subordinate) {\n+        /* Set latency timers on sub bridges */\n+        pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER, 0x40); /* XXX, */\n+        /* More bridge error detection */\n+        pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &config);\n+        config |= PCI_BRIDGE_CTL_PARITY | PCI_BRIDGE_CTL_SERR;\n+        pci_write_config_word(dev, PCI_BRIDGE_CONTROL, config);\n+    }\n+#ifdef IFX_PCIE_ERROR_INT\n+    /* Enable the PCIe normal error reporting */\n+    pos = pci_find_capability(dev, PCI_CAP_ID_EXP);\n+    if (pos) {\n+\n+        /* Disable system error generation in response to error messages */\n+        pci_read_config_word(dev, pos + PCI_EXP_RTCTL, &config);\n+        config &= ~(PCI_EXP_RTCTL_SECEE | PCI_EXP_RTCTL_SENFEE | PCI_EXP_RTCTL_SEFEE);\n+        pci_write_config_word(dev, pos + PCI_EXP_RTCTL, config);\n+\n+        /* Clear PCIE Capability's Device Status */\n+        pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &config);\n+        pci_write_config_word(dev, pos + PCI_EXP_DEVSTA, config);\n+\n+        /* Update Device Control */ \n+        pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &config);\n+        /* Correctable Error Reporting */\n+        config |= PCI_EXP_DEVCTL_CERE;\n+        /* Non-Fatal Error Reporting */\n+        config |= PCI_EXP_DEVCTL_NFERE;\n+        /* Fatal Error Reporting */\n+        config |= PCI_EXP_DEVCTL_FERE;\n+        /* Unsupported Request */\n+        config |= PCI_EXP_DEVCTL_URRE;\n+        pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, config);\n+    }\n+\n+    /* Find the Advanced Error Reporting capability */\n+    pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);\n+    if (pos) {\n+        /* Clear Uncorrectable Error Status */ \n+        pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS, &dconfig);\n+        pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS, dconfig);\n+        /* Enable reporting of all uncorrectable errors */\n+        /* Uncorrectable Error Mask - turned on bits disable errors */\n+        pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, 0);\n+        /* \n+        * Leave severity at HW default. This only controls if \n+        * errors are reported as uncorrectable or \n+        * correctable, not if the error is reported. \n+        */ \n+        /* PCI_ERR_UNCOR_SEVER - Uncorrectable Error Severity */\n+        /* Clear Correctable Error Status */\n+        pci_read_config_dword(dev, pos + PCI_ERR_COR_STATUS, &dconfig);\n+        pci_write_config_dword(dev, pos + PCI_ERR_COR_STATUS, dconfig);\n+        /* Enable reporting of all correctable errors */\n+        /* Correctable Error Mask - turned on bits disable errors */\n+        pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, 0);\n+        /* Advanced Error Capabilities */ \n+        pci_read_config_dword(dev, pos + PCI_ERR_CAP, &dconfig);\n+        /* ECRC Generation Enable */\n+        if (dconfig & PCI_ERR_CAP_ECRC_GENC) {\n+            dconfig |= PCI_ERR_CAP_ECRC_GENE;\n+        }\n+        /* ECRC Check Enable */\n+        if (dconfig & PCI_ERR_CAP_ECRC_CHKC) {\n+            dconfig |= PCI_ERR_CAP_ECRC_CHKE;\n+        }\n+        pci_write_config_dword(dev, pos + PCI_ERR_CAP, dconfig);\n+\n+        /* PCI_ERR_HEADER_LOG - Header Log Register (16 bytes) */\n+        /* Enable Root Port's interrupt in response to error messages */\n+        pci_write_config_dword(dev, pos + PCI_ERR_ROOT_COMMAND,\n+              PCI_ERR_ROOT_CMD_COR_EN |\n+              PCI_ERR_ROOT_CMD_NONFATAL_EN |\n+              PCI_ERR_ROOT_CMD_FATAL_EN); \n+        /* Clear the Root status register */\n+        pci_read_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, &dconfig);\n+        pci_write_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, dconfig);\n+    }\n+#endif /* IFX_PCIE_ERROR_INT */\n+    /* WAR, only 128 MRRS is supported, force all EPs to support this value */\n+    pcie_set_readrq(dev, 128);\n+    return 0;\n+}\n+\n+static int\n+pcie_rc_initialize(int pcie_port)\n+{\n+\tint i;\n+#define IFX_PCIE_PHY_LOOP_CNT  5\n+\n+\tpcie_rcu_endian_setup(pcie_port);\n+\n+\tpcie_ep_gpio_rst_init(pcie_port);\n+\n+\t/* \n+\t* XXX, PCIe elastic buffer bug will cause not to be detected. One more \n+\t* reset PCIe PHY will solve this issue \n+\t*/\n+\tfor (i = 0; i < IFX_PCIE_PHY_LOOP_CNT; i++) {\n+\t\t/* Disable PCIe PHY Analog part for sanity check */\n+\t\tpcie_phy_pmu_disable(pcie_port);\n+\n+\t\tpcie_phy_rst_assert(pcie_port);\n+\t\tpcie_phy_rst_deassert(pcie_port);\n+\n+\t\t/* Make sure PHY PLL is stable */\n+\t\tudelay(20);\n+\n+\t\t/* PCIe Core reset enabled, low active, sw programmed */\n+\t\tpcie_core_rst_assert(pcie_port);\n+\n+\t\t/* Put PCIe EP in reset status */\n+\t\tpcie_device_rst_assert(pcie_port);\n+\n+\t\t/* PCI PHY & Core reset disabled, high active, sw programmed */\n+\t\tpcie_core_rst_deassert(pcie_port);\n+\n+\t\t/* Already in a quiet state, program PLL, enable PHY, check ready bit */\n+\t\tpcie_phy_clock_mode_setup(pcie_port);\n+\n+\t\t/* Enable PCIe PHY and Clock */\n+\t\tpcie_core_pmu_setup(pcie_port);\n+\n+\t\t/* Clear status registers */\n+\t\tpcie_status_register_clear(pcie_port);\n+\n+#ifdef CONFIG_PCI_MSI\n+\t\tpcie_msi_init(pcie_port);\n+#endif /* CONFIG_PCI_MSI */\n+\t\tpcie_rc_cfg_reg_setup(pcie_port);\n+\n+\t\t/* Once link is up, break out */\n+\t\tif (pcie_app_loigc_setup(pcie_port) == 0)\n+\t\t\tbreak;\n+\t}\n+\tif (i >= IFX_PCIE_PHY_LOOP_CNT) {\n+\t\tprintk(KERN_ERR \"%s link up failed!!!!!\\n\", __func__);\n+\t\treturn -EIO;\n+\t}\n+\t/* NB, don't increase ACK/NACK timer timeout value, which will cause a lot of COR errors */\n+\tpcie_replay_time_update(pcie_port);\n+\treturn 0;\n+}\n+\n+static int __init ifx_pcie_bios_init(void)\n+{\n+    void __iomem *io_map_base;\n+    int pcie_port;\n+    int startup_port;\n+\n+    /* Enable AHB Master/ Slave */\n+    pcie_ahb_pmu_setup();\n+\n+    startup_port = IFX_PCIE_PORT0;\n+    \n+    for (pcie_port = startup_port; pcie_port < IFX_PCIE_CORE_NR; pcie_port++){\n+\tif (pcie_rc_initialize(pcie_port) == 0) {\n+\t    IFX_PCIE_PRINT(PCIE_MSG_INIT, \"%s: ifx_pcie_cfg_base 0x%p\\n\", \n+                 __func__, PCIE_CFG_PORT_TO_BASE(pcie_port));\n+            /* Otherwise, warning will pop up */\n+            io_map_base = ioremap(PCIE_IO_PHY_PORT_TO_BASE(pcie_port), PCIE_IO_SIZE);\n+            if (io_map_base == NULL) {\n+                IFX_PCIE_PRINT(PCIE_MSG_ERR, \"%s io space ioremap failed\\n\", __func__);\n+                return -ENOMEM;\n+            }\n+            ifx_pcie_controller[pcie_port].pcic.io_map_base = (unsigned long)io_map_base;\n+\n+            register_pci_controller(&ifx_pcie_controller[pcie_port].pcic);\n+            /* XXX, clear error status */\n+\n+            IFX_PCIE_PRINT(PCIE_MSG_INIT, \"%s: mem_resource 0x%p, io_resource 0x%p\\n\", \n+                              __func__, &ifx_pcie_controller[pcie_port].pcic.mem_resource, \n+                              &ifx_pcie_controller[pcie_port].pcic.io_resource);\n+\n+        #ifdef IFX_PCIE_ERROR_INT\n+            pcie_rc_core_int_init(pcie_port);\n+        #endif /* IFX_PCIE_ERROR_INT */\n+        }\n+    }\n+\n+    return 0;\n+}\n+arch_initcall(ifx_pcie_bios_init);\n+\n+MODULE_LICENSE(\"GPL\");\n+MODULE_AUTHOR(\"Chuanhua.Lei@infineon.com\");\n+MODULE_SUPPORTED_DEVICE(\"Infineon builtin PCIe RC module\");\n+MODULE_DESCRIPTION(\"Infineon builtin PCIe RC driver\");\n+\n--- /dev/null\n+++ b/arch/mips/pci/ifxmips_pcie.h\n@@ -0,0 +1,131 @@\n+/******************************************************************************\n+**\n+** FILE NAME    : ifxmips_pcie.h\n+** PROJECT      : IFX UEIP for VRX200\n+** MODULES      : PCIe module\n+**\n+** DATE         : 02 Mar 2009\n+** AUTHOR       : Lei Chuanhua\n+** DESCRIPTION  : PCIe Root Complex Driver\n+** COPYRIGHT    :       Copyright (c) 2009\n+**                      Infineon Technologies AG\n+**                      Am Campeon 1-12, 85579 Neubiberg, Germany\n+**\n+**    This program is free software; you can redistribute it and/or modify\n+**    it under the terms of the GNU General Public License as published by\n+**    the Free Software Foundation; either version 2 of the License, or\n+**    (at your option) any later version.\n+** HISTORY\n+** $Version $Date        $Author         $Comment\n+** 0.0.1    17 Mar,2009  Lei Chuanhua    Initial version\n+*******************************************************************************/\n+#ifndef IFXMIPS_PCIE_H\n+#define IFXMIPS_PCIE_H\n+#include <linux/version.h>\n+#include <linux/types.h>\n+#include <linux/pci.h>\n+#include <linux/interrupt.h>\n+#include \"ifxmips_pci_common.h\"\n+#include \"ifxmips_pcie_reg.h\"\n+\n+/*!\n+ \\defgroup IFX_PCIE  PCI Express bus driver module   \n+ \\brief  PCI Express IP module support VRX200 \n+*/\n+\n+/*!\n+ \\defgroup IFX_PCIE_OS OS APIs\n+ \\ingroup IFX_PCIE\n+ \\brief PCIe bus driver OS interface functions\n+*/\n+\n+/*!\n+ \\file ifxmips_pcie.h\n+ \\ingroup IFX_PCIE  \n+ \\brief header file for PCIe module common header file\n+*/\n+#define PCIE_IRQ_LOCK(lock) do {             \\\n+    unsigned long flags;                     \\\n+    spin_lock_irqsave(&(lock), flags);\n+#define PCIE_IRQ_UNLOCK(lock)                \\\n+    spin_unlock_irqrestore(&(lock), flags);  \\\n+} while (0)\n+\n+#define PCIE_MSG_MSI        0x00000001\n+#define PCIE_MSG_ISR        0x00000002\n+#define PCIE_MSG_FIXUP      0x00000004\n+#define PCIE_MSG_READ_CFG   0x00000008\n+#define PCIE_MSG_WRITE_CFG  0x00000010\n+#define PCIE_MSG_CFG        (PCIE_MSG_READ_CFG | PCIE_MSG_WRITE_CFG)\n+#define PCIE_MSG_REG        0x00000020\n+#define PCIE_MSG_INIT       0x00000040\n+#define PCIE_MSG_ERR        0x00000080\n+#define PCIE_MSG_PHY        0x00000100\n+#define PCIE_MSG_ANY        0x000001ff\n+\n+#define IFX_PCIE_PORT0      0\n+#define IFX_PCIE_PORT1      1\n+\n+#ifdef CONFIG_IFX_PCIE_2ND_CORE\n+#define IFX_PCIE_CORE_NR    2\n+#else\n+#define IFX_PCIE_CORE_NR    1\n+#endif\n+\n+#define IFX_PCIE_ERROR_INT\n+\n+//#define IFX_PCIE_DBG\n+\n+#if defined(IFX_PCIE_DBG)\n+#define IFX_PCIE_PRINT(_m, _fmt, args...) do {   \\\n+        ifx_pcie_debug((_fmt), ##args);          \\\n+} while (0)\n+\n+#define INLINE \n+#else\n+#define IFX_PCIE_PRINT(_m, _fmt, args...)   \\\n+    do {} while(0)\n+#define INLINE inline\n+#endif\n+\n+struct ifx_pci_controller {\n+\tstruct pci_controller   pcic;\n+    \n+\t/* RC specific, per host bus information */\n+\tu32   port;  /* Port index, 0 -- 1st core, 1 -- 2nd core */\n+};\n+\n+typedef struct ifx_pcie_ir_irq {\n+    const unsigned int irq;\n+    const char name[16];\n+}ifx_pcie_ir_irq_t;\n+\n+typedef struct ifx_pcie_legacy_irq{\n+    const u32 irq_bit;\n+    const int irq;\n+}ifx_pcie_legacy_irq_t;\n+\n+typedef struct ifx_pcie_irq {\n+    ifx_pcie_ir_irq_t ir_irq;\n+    ifx_pcie_legacy_irq_t legacy_irq[PCIE_LEGACY_INT_MAX];\n+}ifx_pcie_irq_t;\n+\n+extern u32 g_pcie_debug_flag;\n+extern void ifx_pcie_debug(const char *fmt, ...);\n+extern void pcie_phy_clock_mode_setup(int pcie_port);\n+extern void pcie_msi_pic_init(int pcie_port);\n+extern u32 ifx_pcie_bus_enum_read_hack(int where, u32 value);\n+extern u32 ifx_pcie_bus_enum_write_hack(int where, u32 value);\n+\n+#define CONFIG_VR9\n+\n+#ifdef CONFIG_VR9\n+#include \"ifxmips_pcie_vr9.h\"\n+#elif defined (CONFIG_AR10)\n+#include \"ifxmips_pcie_ar10.h\"\n+#else\n+#error \"PCIE: platform not defined\"\n+#endif /* CONFIG_VR9 */\n+\n+#endif  /* IFXMIPS_PCIE_H */\n+\n--- /dev/null\n+++ b/arch/mips/pci/ifxmips_pcie_ar10.h\n@@ -0,0 +1,290 @@\n+/****************************************************************************\n+                              Copyright (c) 2010\n+                            Lantiq Deutschland GmbH\n+                     Am Campeon 3; 85579 Neubiberg, Germany\n+\n+  For licensing information, see the file 'LICENSE' in the root folder of\n+  this software module.\n+\n+ *****************************************************************************/\n+/*!\n+  \\file ifxmips_pcie_ar10.h\n+  \\ingroup IFX_PCIE\n+  \\brief PCIe RC driver ar10 specific file\n+*/\n+\n+#ifndef IFXMIPS_PCIE_AR10_H\n+#define IFXMIPS_PCIE_AR10_H\n+#ifndef AUTOCONF_INCLUDED\n+#include <linux/config.h>\n+#endif /* AUTOCONF_INCLUDED */\n+#include <linux/types.h>\n+#include <linux/delay.h>\n+\n+/* Project header file */\n+#include <asm/ifx/ifx_types.h>\n+#include <asm/ifx/ifx_pmu.h>\n+#include <asm/ifx/ifx_gpio.h>\n+#include <asm/ifx/ifx_ebu_led.h>\n+\n+static inline void pcie_ep_gpio_rst_init(int pcie_port)\n+{\n+    ifx_ebu_led_enable();\n+    if (pcie_port == 0) {\n+        ifx_ebu_led_set_data(11, 1);        \n+    }\n+    else {\n+        ifx_ebu_led_set_data(12, 1);  \n+    }\n+}\n+\n+static inline void pcie_ahb_pmu_setup(void) \n+{\n+    /* XXX, moved to CGU to control AHBM */\n+}\n+\n+static inline void pcie_rcu_endian_setup(int pcie_port)\n+{\n+    u32 reg;\n+\n+    reg = IFX_REG_R32(IFX_RCU_AHB_ENDIAN);\n+    /* Inbound, big endian */\n+    reg |= IFX_RCU_BE_AHB4S;\n+    if (pcie_port == 0) {\n+        reg |= IFX_RCU_BE_PCIE0M;\n+\n+    #ifdef CONFIG_IFX_PCIE_HW_SWAP\n+        /* Outbound, software swap needed */\n+        reg |= IFX_RCU_BE_AHB3M;\n+        reg &= ~IFX_RCU_BE_PCIE0S;\n+    #else\n+        /* Outbound little endian  */\n+        reg &= ~IFX_RCU_BE_AHB3M;\n+        reg &= ~IFX_RCU_BE_PCIE0S;\n+    #endif\n+    }\n+    else {\n+        reg |= IFX_RCU_BE_PCIE1M;\n+    #ifdef CONFIG_IFX_PCIE1_HW_SWAP\n+        /* Outbound, software swap needed */\n+        reg |= IFX_RCU_BE_AHB3M;\n+        reg &= ~IFX_RCU_BE_PCIE1S;\n+    #else\n+        /* Outbound little endian  */\n+        reg &= ~IFX_RCU_BE_AHB3M;\n+        reg &= ~IFX_RCU_BE_PCIE1S;\n+    #endif\n+    }\n+\n+    IFX_REG_W32(reg, IFX_RCU_AHB_ENDIAN);\n+    IFX_PCIE_PRINT(PCIE_MSG_REG, \"%s IFX_RCU_AHB_ENDIAN: 0x%08x\\n\", __func__, IFX_REG_R32(IFX_RCU_AHB_ENDIAN));\n+}\n+\n+static inline void pcie_phy_pmu_enable(int pcie_port)\n+{\n+    if (pcie_port == 0) { /* XXX, should use macro*/\n+        PCIE0_PHY_PMU_SETUP(IFX_PMU_ENABLE);\n+    }\n+    else {\n+        PCIE1_PHY_PMU_SETUP(IFX_PMU_ENABLE);\n+    }\n+}\n+\n+static inline void pcie_phy_pmu_disable(int pcie_port)\n+{\n+    if (pcie_port == 0) { /* XXX, should use macro*/\n+        PCIE0_PHY_PMU_SETUP(IFX_PMU_DISABLE);\n+    }\n+    else {\n+        PCIE1_PHY_PMU_SETUP(IFX_PMU_DISABLE);\n+    }\n+}\n+\n+static inline void pcie_pdi_big_endian(int pcie_port)\n+{\n+    u32 reg;\n+\n+    reg = IFX_REG_R32(IFX_RCU_AHB_ENDIAN);\n+    if (pcie_port == 0) {\n+        /* Config AHB->PCIe and PDI endianness */\n+        reg |= IFX_RCU_BE_PCIE0_PDI;\n+    }\n+    else {\n+        /* Config AHB->PCIe and PDI endianness */\n+        reg |= IFX_RCU_BE_PCIE1_PDI;\n+    }\n+    IFX_REG_W32(reg, IFX_RCU_AHB_ENDIAN);\n+}\n+\n+static inline void pcie_pdi_pmu_enable(int pcie_port)\n+{\n+    if (pcie_port == 0) {\n+        /* Enable PDI to access PCIe PHY register */\n+        PDI0_PMU_SETUP(IFX_PMU_ENABLE);\n+    }\n+    else {\n+        PDI1_PMU_SETUP(IFX_PMU_ENABLE);\n+    }\n+}\n+\n+static inline void pcie_core_rst_assert(int pcie_port)\n+{\n+    u32 reg;\n+\n+    reg = IFX_REG_R32(IFX_RCU_RST_REQ);\n+\n+    /* Reset Core, bit 22 */\n+    if (pcie_port == 0) {\n+        reg |= 0x00400000;\n+    }\n+    else {\n+        reg |= 0x08000000; /* Bit 27 */\n+    }\n+    IFX_REG_W32(reg, IFX_RCU_RST_REQ);\n+}\n+\n+static inline void pcie_core_rst_deassert(int pcie_port)\n+{\n+    u32 reg;\n+\n+    /* Make sure one micro-second delay */\n+    udelay(1);\n+\n+    reg = IFX_REG_R32(IFX_RCU_RST_REQ);\n+    if (pcie_port == 0) {\n+        reg &= ~0x00400000; /* bit 22 */\n+    }\n+    else {\n+        reg &= ~0x08000000; /* Bit 27 */\n+    }\n+    IFX_REG_W32(reg, IFX_RCU_RST_REQ);\n+}\n+\n+static inline void pcie_phy_rst_assert(int pcie_port)\n+{\n+    u32 reg;\n+\n+    reg = IFX_REG_R32(IFX_RCU_RST_REQ);\n+    if (pcie_port == 0) {\n+        reg |= 0x00001000; /* Bit 12 */\n+    }\n+    else {\n+        reg |= 0x00002000; /* Bit 13 */\n+    }\n+    IFX_REG_W32(reg, IFX_RCU_RST_REQ);\n+}\n+\n+static inline void pcie_phy_rst_deassert(int pcie_port)\n+{\n+    u32 reg;\n+\n+    /* Make sure one micro-second delay */\n+    udelay(1);\n+\n+    reg = IFX_REG_R32(IFX_RCU_RST_REQ);\n+    if (pcie_port == 0) {\n+        reg &= ~0x00001000; /* Bit 12 */\n+    }\n+    else {\n+        reg &= ~0x00002000; /* Bit 13 */\n+    }\n+    IFX_REG_W32(reg, IFX_RCU_RST_REQ);\n+}\n+\n+static inline void pcie_device_rst_assert(int pcie_port)\n+{\n+    if (pcie_port == 0) {\n+        ifx_ebu_led_set_data(11, 0);\n+    }\n+    else {\n+        ifx_ebu_led_set_data(12, 0);\n+    }\n+}\n+\n+static inline void pcie_device_rst_deassert(int pcie_port)\n+{\n+    mdelay(100);\n+    if (pcie_port == 0) {\n+        ifx_ebu_led_set_data(11, 1);\n+    }\n+    else {\n+        ifx_ebu_led_set_data(12, 1);\n+    }\n+    ifx_ebu_led_disable();\n+}\n+\n+static inline void pcie_core_pmu_setup(int pcie_port)\n+{\n+    if (pcie_port == 0) {\n+        PCIE0_CTRL_PMU_SETUP(IFX_PMU_ENABLE);\n+    }\n+    else {\n+        PCIE1_CTRL_PMU_SETUP(IFX_PMU_ENABLE); \n+    }\n+}\n+\n+static inline void pcie_msi_init(int pcie_port)\n+{\n+    pcie_msi_pic_init(pcie_port);\n+    if (pcie_port == 0) {\n+        MSI0_PMU_SETUP(IFX_PMU_ENABLE);\n+    }\n+    else {\n+        MSI1_PMU_SETUP(IFX_PMU_ENABLE);\n+    }\n+}\n+\n+static inline u32\n+ifx_pcie_bus_nr_deduct(u32 bus_number, int pcie_port)\n+{\n+    u32 tbus_number = bus_number;\n+\n+#ifdef CONFIG_IFX_PCIE_2ND_CORE\n+    if (pcie_port == IFX_PCIE_PORT1) { /* Port 1 must check if there are two cores enabled */\n+        if (pcibios_host_nr() > 1) {\n+            tbus_number -= pcibios_1st_host_bus_nr();\n+        }        \n+    }\n+#endif /* CONFIG_IFX_PCI */\n+    return tbus_number;\n+}\n+\n+static inline u32\n+ifx_pcie_bus_enum_hack(struct pci_bus *bus, u32 devfn, int where, u32 value, int pcie_port, int read)\n+{\n+    struct pci_dev *pdev;\n+    u32 tvalue = value;\n+\n+    /* Sanity check */\n+    pdev = pci_get_slot(bus, devfn);\n+    if (pdev == NULL) {\n+        return tvalue;\n+    }\n+\n+    /* Only care about PCI bridge */\n+    if (pdev->hdr_type != PCI_HEADER_TYPE_BRIDGE) {\n+        return tvalue;\n+    }\n+\n+    if (read) { /* Read hack */\n+    #ifdef CONFIG_IFX_PCIE_2ND_CORE\n+        if (pcie_port == IFX_PCIE_PORT1) { /* Port 1 must check if there are two cores enabled */\n+            if (pcibios_host_nr() > 1) {\n+                tvalue = ifx_pcie_bus_enum_read_hack(where, tvalue);\n+            }\n+        }\n+    #endif /* CONFIG_IFX_PCIE_2ND_CORE */\n+    }\n+    else { /* Write hack */\n+    #ifdef CONFIG_IFX_PCIE_2ND_CORE\n+        if (pcie_port == IFX_PCIE_PORT1) { /* Port 1 must check if there are two cores enabled */\n+            if (pcibios_host_nr() > 1) {\n+                tvalue = ifx_pcie_bus_enum_write_hack(where, tvalue);\n+            }\n+        }\n+    #endif\n+    }\n+    return tvalue;\n+}\n+\n+#endif /* IFXMIPS_PCIE_AR10_H */\n--- /dev/null\n+++ b/arch/mips/pci/ifxmips_pcie_msi.c\n@@ -0,0 +1,392 @@\n+/******************************************************************************\n+**\n+** FILE NAME    : ifxmips_pcie_msi.c\n+** PROJECT      : IFX UEIP for VRX200\n+** MODULES      : PCI MSI sub module\n+**\n+** DATE         : 02 Mar 2009\n+** AUTHOR       : Lei Chuanhua\n+** DESCRIPTION  : PCIe MSI Driver\n+** COPYRIGHT    :       Copyright (c) 2009\n+**                      Infineon Technologies AG\n+**                      Am Campeon 1-12, 85579 Neubiberg, Germany\n+**\n+**    This program is free software; you can redistribute it and/or modify\n+**    it under the terms of the GNU General Public License as published by\n+**    the Free Software Foundation; either version 2 of the License, or\n+**    (at your option) any later version.\n+** HISTORY\n+** $Date        $Author         $Comment\n+** 02 Mar,2009  Lei Chuanhua    Initial version\n+*******************************************************************************/\n+/*!\n+ \\defgroup IFX_PCIE_MSI MSI OS APIs\n+ \\ingroup IFX_PCIE\n+ \\brief PCIe bus driver OS interface functions\n+*/\n+\n+/*!\n+ \\file ifxmips_pcie_msi.c\n+ \\ingroup IFX_PCIE \n+ \\brief PCIe MSI OS interface file\n+*/\n+\n+#ifndef AUTOCONF_INCLUDED\n+#include <linux/config.h>\n+#endif /* AUTOCONF_INCLUDED */\n+#include <linux/init.h>\n+#include <linux/sched.h>\n+#include <linux/slab.h>\n+#include <linux/interrupt.h>\n+#include <linux/kernel_stat.h>\n+#include <linux/pci.h>\n+#include <linux/msi.h>\n+#include <linux/module.h>\n+#include <asm/bootinfo.h>\n+#include <asm/irq.h>\n+#include <asm/traps.h>\n+\n+#include <asm/ifx/ifx_types.h>\n+#include <asm/ifx/ifx_regs.h>\n+#include <asm/ifx/common_routines.h>\n+#include <asm/ifx/irq.h>\n+\n+#include \"ifxmips_pcie_reg.h\"\n+#include \"ifxmips_pcie.h\"\n+\n+#define IFX_MSI_IRQ_NUM    16\n+\n+enum {\n+    IFX_PCIE_MSI_IDX0 = 0,\n+    IFX_PCIE_MSI_IDX1,\n+    IFX_PCIE_MSI_IDX2,\n+    IFX_PCIE_MSI_IDX3,\n+};\n+\n+typedef struct ifx_msi_irq_idx {\n+    const int irq;\n+    const int idx;\n+}ifx_msi_irq_idx_t;\n+\n+struct ifx_msi_pic {\n+    volatile u32  pic_table[IFX_MSI_IRQ_NUM];\n+    volatile u32  pic_endian;    /* 0x40  */\n+};\n+typedef struct ifx_msi_pic *ifx_msi_pic_t;\n+\n+typedef struct ifx_msi_irq {\n+    const volatile ifx_msi_pic_t msi_pic_p;\n+    const u32 msi_phy_base;\n+    const ifx_msi_irq_idx_t msi_irq_idx[IFX_MSI_IRQ_NUM];\n+    /*\n+     * Each bit in msi_free_irq_bitmask represents a MSI interrupt that is \n+     * in use.\n+     */\n+    u16 msi_free_irq_bitmask;\n+\n+    /*\n+     * Each bit in msi_multiple_irq_bitmask tells that the device using \n+     * this bit in msi_free_irq_bitmask is also using the next bit. This \n+     * is used so we can disable all of the MSI interrupts when a device \n+     * uses multiple.\n+     */\n+    u16 msi_multiple_irq_bitmask;\n+}ifx_msi_irq_t;\n+\n+static ifx_msi_irq_t msi_irqs[IFX_PCIE_CORE_NR] = {\n+    {\n+        .msi_pic_p = (const volatile ifx_msi_pic_t)IFX_MSI_PIC_REG_BASE,\n+        .msi_phy_base = PCIE_MSI_PHY_BASE,\n+        .msi_irq_idx = {\n+            {IFX_PCIE_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE_MSI_IR1, IFX_PCIE_MSI_IDX1},\n+            {IFX_PCIE_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE_MSI_IR3, IFX_PCIE_MSI_IDX3},\n+            {IFX_PCIE_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE_MSI_IR1, IFX_PCIE_MSI_IDX1},\n+            {IFX_PCIE_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE_MSI_IR3, IFX_PCIE_MSI_IDX3},\n+            {IFX_PCIE_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE_MSI_IR1, IFX_PCIE_MSI_IDX1},\n+            {IFX_PCIE_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE_MSI_IR3, IFX_PCIE_MSI_IDX3},\n+            {IFX_PCIE_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE_MSI_IR1, IFX_PCIE_MSI_IDX1},\n+            {IFX_PCIE_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE_MSI_IR3, IFX_PCIE_MSI_IDX3},\n+        },\n+        .msi_free_irq_bitmask = 0,\n+        .msi_multiple_irq_bitmask= 0,\n+    },\n+#ifdef CONFIG_IFX_PCIE_2ND_CORE\n+    {\n+        .msi_pic_p = (const volatile ifx_msi_pic_t)IFX_MSI1_PIC_REG_BASE,\n+        .msi_phy_base = PCIE1_MSI_PHY_BASE,\n+        .msi_irq_idx = {\n+            {IFX_PCIE1_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE1_MSI_IR1, IFX_PCIE_MSI_IDX1},\n+            {IFX_PCIE1_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE1_MSI_IR3, IFX_PCIE_MSI_IDX3},\n+            {IFX_PCIE1_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE1_MSI_IR1, IFX_PCIE_MSI_IDX1},\n+            {IFX_PCIE1_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE1_MSI_IR3, IFX_PCIE_MSI_IDX3},\n+            {IFX_PCIE1_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE1_MSI_IR1, IFX_PCIE_MSI_IDX1},\n+            {IFX_PCIE1_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE1_MSI_IR3, IFX_PCIE_MSI_IDX3},\n+            {IFX_PCIE1_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE1_MSI_IR1, IFX_PCIE_MSI_IDX1},\n+            {IFX_PCIE1_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE1_MSI_IR3, IFX_PCIE_MSI_IDX3},\n+        },\n+        .msi_free_irq_bitmask = 0,\n+        .msi_multiple_irq_bitmask= 0,\n+\n+    },\n+#endif /* CONFIG_IFX_PCIE_2ND_CORE */\n+};\n+\n+/* \n+ * This lock controls updates to msi_free_irq_bitmask, \n+ * msi_multiple_irq_bitmask and pic register settting\n+ */ \n+static DEFINE_SPINLOCK(ifx_pcie_msi_lock);\n+\n+void pcie_msi_pic_init(int pcie_port)\n+{\n+    spin_lock(&ifx_pcie_msi_lock);\n+    msi_irqs[pcie_port].msi_pic_p->pic_endian = IFX_MSI_PIC_BIG_ENDIAN;\n+    spin_unlock(&ifx_pcie_msi_lock);\n+}\n+\n+/** \n+ * \\fn int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)\n+ * \\brief Called when a driver request MSI interrupts instead of the \n+ * legacy INT A-D. This routine will allocate multiple interrupts \n+ * for MSI devices that support them. A device can override this by \n+ * programming the MSI control bits [6:4] before calling \n+ * pci_enable_msi(). \n+ * \n+ * \\param[in] pdev   Device requesting MSI interrupts \n+ * \\param[in] desc   MSI descriptor \n+ * \n+ * \\return   -EINVAL Invalid pcie root port or invalid msi bit\n+ * \\return    0        OK\n+ * \\ingroup IFX_PCIE_MSI\n+ */\n+int \n+arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)\n+{\n+    int  irq, pos;\n+    u16  control;\n+    int  irq_idx;\n+    int  irq_step;\n+    int configured_private_bits;\n+    int request_private_bits;\n+    struct msi_msg msg;\n+    u16 search_mask;\n+    struct ifx_pci_controller *ctrl = pdev->bus->sysdata;\n+    int pcie_port = ctrl->port;\n+\n+    IFX_PCIE_PRINT(PCIE_MSG_MSI, \"%s %s enter\\n\", __func__, pci_name(pdev));\n+\n+    /* XXX, skip RC MSI itself */\n+    if (pdev->pcie_type == PCI_EXP_TYPE_ROOT_PORT) {\n+        IFX_PCIE_PRINT(PCIE_MSG_MSI, \"%s RC itself doesn't use MSI interrupt\\n\", __func__);\n+        return -EINVAL;\n+    }\n+\n+    /*\n+     * Read the MSI config to figure out how many IRQs this device \n+     * wants.  Most devices only want 1, which will give \n+     * configured_private_bits and request_private_bits equal 0. \n+     */\n+    pci_read_config_word(pdev, desc->msi_attrib.pos + PCI_MSI_FLAGS, &control);\n+\n+    /*\n+     * If the number of private bits has been configured then use \n+     * that value instead of the requested number. This gives the \n+     * driver the chance to override the number of interrupts \n+     * before calling pci_enable_msi(). \n+     */\n+    configured_private_bits = (control & PCI_MSI_FLAGS_QSIZE) >> 4; \n+    if (configured_private_bits == 0) {\n+        /* Nothing is configured, so use the hardware requested size */\n+        request_private_bits = (control & PCI_MSI_FLAGS_QMASK) >> 1;\n+    }\n+    else {\n+        /*\n+         * Use the number of configured bits, assuming the \n+         * driver wanted to override the hardware request \n+         * value.\n+         */\n+        request_private_bits = configured_private_bits;\n+    }\n+\n+    /*\n+     * The PCI 2.3 spec mandates that there are at most 32\n+     * interrupts. If this device asks for more, only give it one.\n+     */\n+    if (request_private_bits > 5) {\n+        request_private_bits = 0;\n+    }\n+again:\n+    /*\n+     * The IRQs have to be aligned on a power of two based on the\n+     * number being requested.\n+     */\n+    irq_step = (1 << request_private_bits);\n+\n+    /* Mask with one bit for each IRQ */\n+    search_mask = (1 << irq_step) - 1;\n+\n+    /*\n+     * We're going to search msi_free_irq_bitmask_lock for zero \n+     * bits. This represents an MSI interrupt number that isn't in \n+     * use.\n+     */\n+    spin_lock(&ifx_pcie_msi_lock);\n+    for (pos = 0; pos < IFX_MSI_IRQ_NUM; pos += irq_step) {\n+        if ((msi_irqs[pcie_port].msi_free_irq_bitmask & (search_mask << pos)) == 0) {\n+            msi_irqs[pcie_port].msi_free_irq_bitmask |= search_mask << pos; \n+            msi_irqs[pcie_port].msi_multiple_irq_bitmask |= (search_mask >> 1) << pos;\n+            break; \n+        }\n+    }\n+    spin_unlock(&ifx_pcie_msi_lock); \n+\n+    /* Make sure the search for available interrupts didn't fail */ \n+    if (pos >= IFX_MSI_IRQ_NUM) {\n+        if (request_private_bits) {\n+            IFX_PCIE_PRINT(PCIE_MSG_MSI, \"%s: Unable to find %d free \"\n+                  \"interrupts, trying just one\", __func__, 1 << request_private_bits);\n+            request_private_bits = 0;\n+            goto again;\n+        }\n+        else {\n+            printk(KERN_ERR \"%s: Unable to find a free MSI interrupt\\n\", __func__);\n+            return -EINVAL;\n+        }\n+    } \n+    irq = msi_irqs[pcie_port].msi_irq_idx[pos].irq;\n+    irq_idx = msi_irqs[pcie_port].msi_irq_idx[pos].idx;\n+\n+    IFX_PCIE_PRINT(PCIE_MSG_MSI, \"pos %d, irq %d irq_idx %d\\n\", pos, irq, irq_idx);\n+\n+    /*\n+     * Initialize MSI. This has to match the memory-write endianess from the device \n+     * Address bits [23:12]\n+     */\n+    spin_lock(&ifx_pcie_msi_lock); \n+    msi_irqs[pcie_port].msi_pic_p->pic_table[pos] = SM(irq_idx, IFX_MSI_PIC_INT_LINE) |\n+                    SM((msi_irqs[pcie_port].msi_phy_base >> 12), IFX_MSI_PIC_MSG_ADDR) |\n+                    SM((1 << pos), IFX_MSI_PIC_MSG_DATA);\n+\n+    /* Enable this entry */\n+    msi_irqs[pcie_port].msi_pic_p->pic_table[pos] &= ~IFX_MSI_PCI_INT_DISABLE;\n+    spin_unlock(&ifx_pcie_msi_lock);\n+\n+    IFX_PCIE_PRINT(PCIE_MSG_MSI, \"pic_table[%d]: 0x%08x\\n\",\n+        pos, msi_irqs[pcie_port].msi_pic_p->pic_table[pos]);\n+\n+    /* Update the number of IRQs the device has available to it */\n+    control &= ~PCI_MSI_FLAGS_QSIZE;\n+    control |= (request_private_bits << 4);\n+    pci_write_config_word(pdev, desc->msi_attrib.pos + PCI_MSI_FLAGS, control);\n+\n+    set_irq_msi(irq, desc);\n+    msg.address_hi = 0x0;\n+    msg.address_lo = msi_irqs[pcie_port].msi_phy_base;\n+    msg.data = SM((1 << pos), IFX_MSI_PIC_MSG_DATA);\n+    IFX_PCIE_PRINT(PCIE_MSG_MSI, \"msi_data: pos %d 0x%08x\\n\", pos, msg.data);\n+\n+    write_msi_msg(irq, &msg);\n+    IFX_PCIE_PRINT(PCIE_MSG_MSI, \"%s exit\\n\", __func__);\n+    return 0;\n+}\n+\n+static int\n+pcie_msi_irq_to_port(unsigned int irq, int *port)\n+{\n+    int ret = 0;\n+\n+    if (irq == IFX_PCIE_MSI_IR0 || irq == IFX_PCIE_MSI_IR1 ||\n+        irq == IFX_PCIE_MSI_IR2 || irq == IFX_PCIE_MSI_IR3) {\n+        *port = IFX_PCIE_PORT0;\n+    }\n+#ifdef CONFIG_IFX_PCIE_2ND_CORE\n+    else if (irq == IFX_PCIE1_MSI_IR0 || irq == IFX_PCIE1_MSI_IR1 ||\n+        irq == IFX_PCIE1_MSI_IR2 || irq == IFX_PCIE1_MSI_IR3) {\n+        *port = IFX_PCIE_PORT1;\n+    }\n+#endif /* CONFIG_IFX_PCIE_2ND_CORE */\n+    else {\n+        printk(KERN_ERR \"%s: Attempted to teardown illegal \" \n+            \"MSI interrupt (%d)\\n\", __func__, irq);\n+        ret = -EINVAL;\n+    }\n+    return ret;\n+}\n+\n+/** \n+ * \\fn void arch_teardown_msi_irq(unsigned int irq)\n+ * \\brief Called when a device no longer needs its MSI interrupts. All \n+ * MSI interrupts for the device are freed. \n+ * \n+ * \\param irq   The devices first irq number. There may be multple in sequence.\n+ * \\return none\n+ * \\ingroup IFX_PCIE_MSI\n+ */\n+void \n+arch_teardown_msi_irq(unsigned int irq)\n+{\n+    int pos;\n+    int number_irqs; \n+    u16 bitmask;\n+    int pcie_port;\n+\n+    IFX_PCIE_PRINT(PCIE_MSG_MSI, \"%s enter\\n\", __func__);\n+\n+    BUG_ON(irq > INT_NUM_IM4_IRL31);\n+\n+    if (pcie_msi_irq_to_port(irq, &pcie_port) != 0) {\n+        return;\n+    }\n+\n+    /* Shift the mask to the correct bit location, not always correct \n+     * Probally, the first match will be chosen.\n+     */\n+    for (pos = 0; pos < IFX_MSI_IRQ_NUM; pos++) {\n+        if ((msi_irqs[pcie_port].msi_irq_idx[pos].irq == irq) \n+            && (msi_irqs[pcie_port].msi_free_irq_bitmask & ( 1 << pos))) {\n+            break;\n+        }\n+    }\n+    if (pos >= IFX_MSI_IRQ_NUM) {\n+        printk(KERN_ERR \"%s: Unable to find a matched MSI interrupt\\n\", __func__);\n+        return;\n+    }\n+    spin_lock(&ifx_pcie_msi_lock);\n+    /* Disable this entry */\n+    msi_irqs[pcie_port].msi_pic_p->pic_table[pos] |= IFX_MSI_PCI_INT_DISABLE;\n+    msi_irqs[pcie_port].msi_pic_p->pic_table[pos] &= ~(IFX_MSI_PIC_INT_LINE | IFX_MSI_PIC_MSG_ADDR | IFX_MSI_PIC_MSG_DATA);\n+    spin_unlock(&ifx_pcie_msi_lock); \n+    /*\n+     * Count the number of IRQs we need to free by looking at the\n+     * msi_multiple_irq_bitmask. Each bit set means that the next\n+     * IRQ is also owned by this device.\n+     */ \n+    number_irqs = 0; \n+    while (((pos + number_irqs) < IFX_MSI_IRQ_NUM) && \n+        (msi_irqs[pcie_port].msi_multiple_irq_bitmask & (1 << (pos + number_irqs)))) {\n+        number_irqs++;\n+    }\n+    number_irqs++;\n+\n+    /* Mask with one bit for each IRQ */\n+    bitmask = (1 << number_irqs) - 1;\n+\n+    bitmask <<= pos;\n+    if ((msi_irqs[pcie_port].msi_free_irq_bitmask & bitmask) != bitmask) {\n+        printk(KERN_ERR \"%s: Attempted to teardown MSI \"\n+             \"interrupt (%d) not in use\\n\", __func__, irq);\n+        return;\n+    }\n+    /* Checks are done, update the in use bitmask */\n+    spin_lock(&ifx_pcie_msi_lock);\n+    msi_irqs[pcie_port].msi_free_irq_bitmask &= ~bitmask;\n+    msi_irqs[pcie_port].msi_multiple_irq_bitmask &= ~(bitmask >> 1);\n+    spin_unlock(&ifx_pcie_msi_lock);\n+    IFX_PCIE_PRINT(PCIE_MSG_MSI, \"%s exit\\n\", __func__);\n+}\n+\n+MODULE_LICENSE(\"GPL\");\n+MODULE_AUTHOR(\"Chuanhua.Lei@infineon.com\");\n+MODULE_SUPPORTED_DEVICE(\"Infineon PCIe IP builtin MSI PIC module\");\n+MODULE_DESCRIPTION(\"Infineon PCIe IP builtin MSI PIC driver\");\n+\n--- /dev/null\n+++ b/arch/mips/pci/ifxmips_pcie_phy.c\n@@ -0,0 +1,478 @@\n+/******************************************************************************\n+**\n+** FILE NAME    : ifxmips_pcie_phy.c\n+** PROJECT      : IFX UEIP for VRX200\n+** MODULES      : PCIe PHY sub module\n+**\n+** DATE         : 14 May 2009\n+** AUTHOR       : Lei Chuanhua\n+** DESCRIPTION  : PCIe Root Complex Driver\n+** COPYRIGHT    :       Copyright (c) 2009\n+**                      Infineon Technologies AG\n+**                      Am Campeon 1-12, 85579 Neubiberg, Germany\n+**\n+**    This program is free software; you can redistribute it and/or modify\n+**    it under the terms of the GNU General Public License as published by\n+**    the Free Software Foundation; either version 2 of the License, or\n+**    (at your option) any later version.\n+** HISTORY\n+** $Version $Date        $Author         $Comment\n+** 0.0.1    14 May,2009  Lei Chuanhua    Initial version\n+*******************************************************************************/\n+/*!\n+ \\file ifxmips_pcie_phy.c\n+ \\ingroup IFX_PCIE  \n+ \\brief PCIe PHY PLL register programming source file\n+*/\n+#include <linux/types.h>\n+#include <linux/kernel.h>\n+#include <asm/paccess.h>\n+#include <linux/delay.h>\n+\n+#include \"ifxmips_pcie_reg.h\"\n+#include \"ifxmips_pcie.h\"\n+\n+/* PCIe PDI only supports 16 bit operation */\n+\n+#define IFX_PCIE_PHY_REG_WRITE16(__addr, __data) \\\n+    ((*(volatile u16 *) (__addr)) = (__data))\n+    \n+#define IFX_PCIE_PHY_REG_READ16(__addr)  \\\n+    (*(volatile u16 *) (__addr))\n+\n+#define IFX_PCIE_PHY_REG16(__addr)   \\\n+    (*(volatile u16 *) (__addr))\n+\n+#define IFX_PCIE_PHY_REG(__reg, __value, __mask) do { \\\n+    u16 read_data;                                    \\\n+    u16 write_data;                                   \\\n+    read_data = IFX_PCIE_PHY_REG_READ16((__reg));      \\\n+    write_data = (read_data & ((u16)~(__mask))) | (((u16)(__value)) & ((u16)(__mask)));\\\n+    IFX_PCIE_PHY_REG_WRITE16((__reg), write_data);               \\\n+} while (0)\n+\n+#define IFX_PCIE_PLL_TIMEOUT 1000 /* Tunnable */\n+\n+//#define IFX_PCI_PHY_REG_DUMP\n+\n+#ifdef IFX_PCI_PHY_REG_DUMP\n+static void\n+pcie_phy_reg_dump(int pcie_port) \n+{\n+    printk(\"PLL REGFILE\\n\");\n+    printk(\"PCIE_PHY_PLL_CTRL1    0x%04x\\n\", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_CTRL1(pcie_port)));\n+    printk(\"PCIE_PHY_PLL_CTRL2    0x%04x\\n\", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_CTRL2(pcie_port)));\n+    printk(\"PCIE_PHY_PLL_CTRL3    0x%04x\\n\", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_CTRL3(pcie_port)));\n+    printk(\"PCIE_PHY_PLL_CTRL4    0x%04x\\n\", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_CTRL4(pcie_port)));\n+    printk(\"PCIE_PHY_PLL_CTRL5    0x%04x\\n\", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_CTRL5(pcie_port)));\n+    printk(\"PCIE_PHY_PLL_CTRL6    0x%04x\\n\", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_CTRL6(pcie_port)));\n+    printk(\"PCIE_PHY_PLL_CTRL7    0x%04x\\n\", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_CTRL7(pcie_port)));\n+    printk(\"PCIE_PHY_PLL_A_CTRL1  0x%04x\\n\", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_A_CTRL1(pcie_port)));\n+    printk(\"PCIE_PHY_PLL_A_CTRL2  0x%04x\\n\", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_A_CTRL2(pcie_port)));\n+    printk(\"PCIE_PHY_PLL_A_CTRL3  0x%04x\\n\", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_A_CTRL3(pcie_port)));\n+    printk(\"PCIE_PHY_PLL_STATUS   0x%04x\\n\", IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_STATUS(pcie_port)));\n+\n+    printk(\"TX1 REGFILE\\n\");\n+    printk(\"PCIE_PHY_TX1_CTRL1    0x%04x\\n\", IFX_PCIE_PHY_REG16(PCIE_PHY_TX1_CTRL1(pcie_port)));\n+    printk(\"PCIE_PHY_TX1_CTRL2    0x%04x\\n\", IFX_PCIE_PHY_REG16(PCIE_PHY_TX1_CTRL2(pcie_port)));\n+    printk(\"PCIE_PHY_TX1_CTRL3    0x%04x\\n\", IFX_PCIE_PHY_REG16(PCIE_PHY_TX1_CTRL3(pcie_port)));\n+    printk(\"PCIE_PHY_TX1_A_CTRL1  0x%04x\\n\", IFX_PCIE_PHY_REG16(PCIE_PHY_TX1_A_CTRL1(pcie_port)));\n+    printk(\"PCIE_PHY_TX1_A_CTRL2  0x%04x\\n\", IFX_PCIE_PHY_REG16(PCIE_PHY_TX1_A_CTRL2(pcie_port)));\n+    printk(\"PCIE_PHY_TX1_MOD1     0x%04x\\n\", IFX_PCIE_PHY_REG16(PCIE_PHY_TX1_MOD1(pcie_port)));\n+    printk(\"PCIE_PHY_TX1_MOD2     0x%04x\\n\", IFX_PCIE_PHY_REG16(PCIE_PHY_TX1_MOD2(pcie_port)));\n+    printk(\"PCIE_PHY_TX1_MOD3     0x%04x\\n\", IFX_PCIE_PHY_REG16(PCIE_PHY_TX1_MOD3(pcie_port)));\n+\n+    printk(\"TX2 REGFILE\\n\");\n+    printk(\"PCIE_PHY_TX2_CTRL1    0x%04x\\n\", IFX_PCIE_PHY_REG16(PCIE_PHY_TX2_CTRL1(pcie_port)));\n+    printk(\"PCIE_PHY_TX2_CTRL2    0x%04x\\n\", IFX_PCIE_PHY_REG16(PCIE_PHY_TX2_CTRL2(pcie_port)));\n+    printk(\"PCIE_PHY_TX2_A_CTRL1  0x%04x\\n\", IFX_PCIE_PHY_REG16(PCIE_PHY_TX2_A_CTRL1(pcie_port)));\n+    printk(\"PCIE_PHY_TX2_A_CTRL2  0x%04x\\n\", IFX_PCIE_PHY_REG16(PCIE_PHY_TX2_A_CTRL2(pcie_port)));\n+    printk(\"PCIE_PHY_TX2_MOD1     0x%04x\\n\", IFX_PCIE_PHY_REG16(PCIE_PHY_TX2_MOD1(pcie_port)));\n+    printk(\"PCIE_PHY_TX2_MOD2     0x%04x\\n\", IFX_PCIE_PHY_REG16(PCIE_PHY_TX2_MOD2(pcie_port)));\n+    printk(\"PCIE_PHY_TX2_MOD3     0x%04x\\n\", IFX_PCIE_PHY_REG16(PCIE_PHY_TX2_MOD3(pcie_port)));\n+\n+    printk(\"RX1 REGFILE\\n\");\n+    printk(\"PCIE_PHY_RX1_CTRL1    0x%04x\\n\", IFX_PCIE_PHY_REG16(PCIE_PHY_RX1_CTRL1(pcie_port)));\n+    printk(\"PCIE_PHY_RX1_CTRL2    0x%04x\\n\", IFX_PCIE_PHY_REG16(PCIE_PHY_RX1_CTRL2(pcie_port)));\n+    printk(\"PCIE_PHY_RX1_CDR      0x%04x\\n\", IFX_PCIE_PHY_REG16(PCIE_PHY_RX1_CDR(pcie_port)));\n+    printk(\"PCIE_PHY_RX1_EI       0x%04x\\n\", IFX_PCIE_PHY_REG16(PCIE_PHY_RX1_EI(pcie_port)));\n+    printk(\"PCIE_PHY_RX1_A_CTRL   0x%04x\\n\", IFX_PCIE_PHY_REG16(PCIE_PHY_RX1_A_CTRL(pcie_port)));\n+}\n+#endif /* IFX_PCI_PHY_REG_DUMP */\n+\n+static void\n+pcie_phy_comm_setup(int pcie_port)\n+{\n+   /* PLL Setting */\n+    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL1(pcie_port), 0x120e, 0xFFFF);\n+\n+    /* increase the bias reference voltage */\n+    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL2(pcie_port), 0x39D7, 0xFFFF);\n+    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL3(pcie_port), 0x0900, 0xFFFF);\n+\n+    /* Endcnt */\n+    IFX_PCIE_PHY_REG(PCIE_PHY_RX1_EI(pcie_port), 0x0004, 0xFFFF);\n+    IFX_PCIE_PHY_REG(PCIE_PHY_RX1_A_CTRL(pcie_port), 0x6803, 0xFFFF);\n+\n+    /* force */\n+    IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL1(pcie_port), 0x0008, 0x0008);\n+\n+    /* predrv_ser_en */\n+    IFX_PCIE_PHY_REG(PCIE_PHY_TX1_A_CTRL2(pcie_port), 0x0706, 0xFFFF);\n+\n+    /* ctrl_lim */\n+    IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL3(pcie_port), 0x1FFF, 0xFFFF);\n+\n+    /* ctrl */\n+    IFX_PCIE_PHY_REG(PCIE_PHY_TX1_A_CTRL1(pcie_port), 0x0800, 0xFF00);\n+\n+    /* predrv_ser_en */\n+    IFX_PCIE_PHY_REG(PCIE_PHY_TX2_A_CTRL2(pcie_port), 0x4702, 0x7F00);\n+\n+    /* RTERM*/\n+    IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL2(pcie_port), 0x2e00, 0xFFFF);\n+\n+    /* Improved 100MHz clock output  */\n+    IFX_PCIE_PHY_REG(PCIE_PHY_TX2_CTRL2(pcie_port), 0x3096, 0xFFFF);\n+    IFX_PCIE_PHY_REG(PCIE_PHY_TX2_A_CTRL2(pcie_port), 0x4707, 0xFFFF);\n+\n+    /* Reduced CDR BW to avoid glitches */\n+    IFX_PCIE_PHY_REG(PCIE_PHY_RX1_CDR(pcie_port), 0x0235, 0xFFFF);\n+}\n+\n+#ifdef CONFIG_IFX_PCIE_PHY_36MHZ_MODE\n+static void \n+pcie_phy_36mhz_mode_setup(int pcie_port) \n+{\n+    IFX_PCIE_PRINT(PCIE_MSG_PHY, \"%s pcie_port %d enter\\n\", __func__, pcie_port);\n+#ifdef IFX_PCI_PHY_REG_DUMP\n+    IFX_PCIE_PRINT(PCIE_MSG_PHY, \"Initial PHY register dump\\n\");\n+    pcie_phy_reg_dump(pcie_port);\n+#endif\n+\n+    /* en_ext_mmd_div_ratio */\n+    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0000, 0x0002);\n+\n+    /* ext_mmd_div_ratio*/\n+    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0000, 0x0070);\n+\n+    /* pll_ensdm */\n+    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0200, 0x0200);\n+\n+    /* en_const_sdm */\n+    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0100, 0x0100);\n+\n+    /* mmd */\n+    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL3(pcie_port), 0x2000, 0xe000);\n+\n+    /* lf_mode */\n+    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL2(pcie_port), 0x0000, 0x4000);\n+\n+    /* const_sdm */\n+    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL1(pcie_port), 0x38e4, 0xFFFF);\n+\n+    /* const sdm */\n+    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x00ee, 0x00FF);\n+\n+    /* pllmod */\n+    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL7(pcie_port), 0x0002, 0xFFFF);\n+    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL6(pcie_port), 0x3a04, 0xFFFF);\n+    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL5(pcie_port), 0xfae3, 0xFFFF);\n+    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL4(pcie_port), 0x1b72, 0xFFFF);\n+\n+    IFX_PCIE_PRINT(PCIE_MSG_PHY, \"%s pcie_port %d exit\\n\", __func__, pcie_port);\n+}\n+#endif /* CONFIG_IFX_PCIE_PHY_36MHZ_MODE */\n+\n+#ifdef CONFIG_IFX_PCIE_PHY_36MHZ_SSC_MODE\n+static void \n+pcie_phy_36mhz_ssc_mode_setup(int pcie_port) \n+{\n+    IFX_PCIE_PRINT(PCIE_MSG_PHY, \"%s pcie_port %d enter\\n\", __func__, pcie_port);\n+#ifdef IFX_PCI_PHY_REG_DUMP\n+    IFX_PCIE_PRINT(PCIE_MSG_PHY, \"Initial PHY register dump\\n\");\n+    pcie_phy_reg_dump(pcie_port);\n+#endif\n+\n+    /* PLL Setting */\n+    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL1(pcie_port), 0x120e, 0xFFFF);\n+\n+    /* Increase the bias reference voltage */\n+    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL2(pcie_port), 0x39D7, 0xFFFF);\n+    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL3(pcie_port), 0x0900, 0xFFFF);\n+\n+    /* Endcnt */\n+    IFX_PCIE_PHY_REG(PCIE_PHY_RX1_EI(pcie_port), 0x0004, 0xFFFF);\n+    IFX_PCIE_PHY_REG(PCIE_PHY_RX1_A_CTRL(pcie_port), 0x6803, 0xFFFF);\n+\n+    /* Force */\n+    IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL1(pcie_port), 0x0008, 0x0008);\n+\n+    /* Predrv_ser_en */\n+    IFX_PCIE_PHY_REG(PCIE_PHY_TX1_A_CTRL2(pcie_port), 0x0706, 0xFFFF);\n+\n+    /* ctrl_lim */\n+    IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL3(pcie_port), 0x1FFF, 0xFFFF);\n+\n+    /* ctrl */\n+    IFX_PCIE_PHY_REG(PCIE_PHY_TX1_A_CTRL1(pcie_port), 0x0800, 0xFF00);\n+\n+    /* predrv_ser_en */\n+    IFX_PCIE_PHY_REG(PCIE_PHY_TX2_A_CTRL2(pcie_port), 0x4702, 0x7F00);\n+\n+    /* RTERM*/\n+    IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL2(pcie_port), 0x2e00, 0xFFFF);\n+\n+    /* en_ext_mmd_div_ratio */\n+    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0000, 0x0002);\n+\n+    /* ext_mmd_div_ratio*/\n+    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0000, 0x0070);\n+\n+    /* pll_ensdm */\n+    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0400, 0x0400);\n+\n+    /* en_const_sdm */\n+    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0200, 0x0200);\n+\n+    /* mmd */\n+    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL3(pcie_port), 0x2000, 0xe000);\n+\n+    /* lf_mode */\n+    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL2(pcie_port), 0x0000, 0x4000);\n+\n+    /* const_sdm */\n+    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL1(pcie_port), 0x38e4, 0xFFFF);\n+\n+    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0000, 0x0100);\n+    /* const sdm */\n+    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x00ee, 0x00FF);\n+\n+    /* pllmod */\n+    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL7(pcie_port), 0x0002, 0xFFFF);\n+    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL6(pcie_port), 0x3a04, 0xFFFF);\n+    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL5(pcie_port), 0xfae3, 0xFFFF);\n+    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL4(pcie_port), 0x1c72, 0xFFFF);\n+\n+    /* improved 100MHz clock output  */\n+    IFX_PCIE_PHY_REG(PCIE_PHY_TX2_CTRL2(pcie_port), 0x3096, 0xFFFF);\n+    IFX_PCIE_PHY_REG(PCIE_PHY_TX2_A_CTRL2(pcie_port), 0x4707, 0xFFFF);\n+\n+    /* reduced CDR BW to avoid glitches */\n+    IFX_PCIE_PHY_REG(PCIE_PHY_RX1_CDR(pcie_port), 0x0235, 0xFFFF);\n+    \n+    IFX_PCIE_PRINT(PCIE_MSG_PHY, \"%s pcie_port %d exit\\n\", __func__, pcie_port);\n+}\n+#endif /* CONFIG_IFX_PCIE_PHY_36MHZ_SSC_MODE */\n+\n+#ifdef CONFIG_IFX_PCIE_PHY_25MHZ_MODE\n+static void \n+pcie_phy_25mhz_mode_setup(int pcie_port) \n+{\n+    IFX_PCIE_PRINT(PCIE_MSG_PHY, \"%s pcie_port %d enter\\n\", __func__, pcie_port);\n+#ifdef IFX_PCI_PHY_REG_DUMP\n+    IFX_PCIE_PRINT(PCIE_MSG_PHY, \"Initial PHY register dump\\n\");\n+    pcie_phy_reg_dump(pcie_port);\n+#endif\n+    /* en_const_sdm */\n+    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0100, 0x0100);\n+\n+    /* pll_ensdm */    \n+    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0000, 0x0200);\n+\n+    /* en_ext_mmd_div_ratio*/\n+    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0002, 0x0002);\n+\n+    /* ext_mmd_div_ratio*/\n+    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0040, 0x0070);\n+\n+    /* mmd */\n+    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL3(pcie_port), 0x6000, 0xe000);\n+\n+    /* lf_mode */\n+    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL2(pcie_port), 0x4000, 0x4000);\n+\n+    IFX_PCIE_PRINT(PCIE_MSG_PHY, \"%s pcie_port %d exit\\n\", __func__, pcie_port);\n+}\n+#endif /* CONFIG_IFX_PCIE_PHY_25MHZ_MODE */\n+\n+#ifdef CONFIG_IFX_PCIE_PHY_100MHZ_MODE\n+static void \n+pcie_phy_100mhz_mode_setup(int pcie_port) \n+{\n+    IFX_PCIE_PRINT(PCIE_MSG_PHY, \"%s pcie_port %d enter\\n\", __func__, pcie_port);\n+#ifdef IFX_PCI_PHY_REG_DUMP\n+    IFX_PCIE_PRINT(PCIE_MSG_PHY, \"Initial PHY register dump\\n\");\n+    pcie_phy_reg_dump(pcie_port);\n+#endif \n+    /* en_ext_mmd_div_ratio */\n+    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0000, 0x0002);\n+\n+    /* ext_mmd_div_ratio*/\n+    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0000, 0x0070);\n+\n+    /* pll_ensdm */\n+    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0200, 0x0200);\n+\n+    /* en_const_sdm */\n+    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0100, 0x0100);\n+\n+    /* mmd */\n+    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL3(pcie_port), 0x2000, 0xe000);\n+\n+    /* lf_mode */\n+    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL2(pcie_port), 0x0000, 0x4000);\n+\n+    /* const_sdm */\n+    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL1(pcie_port), 0x38e4, 0xFFFF);\n+\n+    /* const sdm */\n+    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x00ee, 0x00FF);\n+\n+    /* pllmod */\n+    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL7(pcie_port), 0x0002, 0xFFFF);\n+    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL6(pcie_port), 0x3a04, 0xFFFF);\n+    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL5(pcie_port), 0xfae3, 0xFFFF);\n+    IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL4(pcie_port), 0x1b72, 0xFFFF);\n+\n+    IFX_PCIE_PRINT(PCIE_MSG_PHY, \"%s pcie_port %d exit\\n\", __func__, pcie_port);\n+}\n+#endif /* CONFIG_IFX_PCIE_PHY_100MHZ_MODE */\n+\n+static int\n+pcie_phy_wait_startup_ready(int pcie_port)\n+{\n+    int i;\n+\n+    for (i = 0; i < IFX_PCIE_PLL_TIMEOUT; i++) {\n+        if ((IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_STATUS(pcie_port)) & 0x0040) != 0) {\n+            break;\n+        }\n+        udelay(10);\n+    }\n+    if (i >= IFX_PCIE_PLL_TIMEOUT) {\n+        printk(KERN_ERR \"%s PLL Link timeout\\n\", __func__);\n+        return -1;\n+    }\n+    return 0;\n+}\n+\n+static void \n+pcie_phy_load_enable(int pcie_port, int slice) \n+{\n+    /* Set the load_en of tx/rx slice to '1' */\n+    switch (slice) {\n+        case 1:\n+            IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL1(pcie_port), 0x0010, 0x0010);\n+            break;\n+        case 2:\n+            IFX_PCIE_PHY_REG(PCIE_PHY_TX2_CTRL1(pcie_port), 0x0010, 0x0010);\n+            break;\n+        case 3:\n+            IFX_PCIE_PHY_REG(PCIE_PHY_RX1_CTRL1(pcie_port), 0x0002, 0x0002);\n+            break;\n+    }\n+}\n+\n+static void \n+pcie_phy_load_disable(int pcie_port, int slice) \n+{ \n+    /* set the load_en of tx/rx slice to '0' */ \n+    switch (slice) {\n+        case 1:\n+            IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL1(pcie_port), 0x0000, 0x0010);\n+            break;\n+        case 2:\n+            IFX_PCIE_PHY_REG(PCIE_PHY_TX2_CTRL1(pcie_port), 0x0000, 0x0010);\n+            break;\n+        case 3: \n+            IFX_PCIE_PHY_REG(PCIE_PHY_RX1_CTRL1(pcie_port), 0x0000, 0x0002);\n+            break;\n+    }\n+}\n+\n+static void \n+pcie_phy_load_war(int pcie_port)\n+{\n+    int slice;\n+\n+    for (slice = 1; slice < 4; slice++) {\n+        pcie_phy_load_enable(pcie_port, slice);\n+        udelay(1);\n+        pcie_phy_load_disable(pcie_port, slice);\n+    }\n+}\n+\n+static void \n+pcie_phy_tx2_modulation(int pcie_port)\n+{\n+    IFX_PCIE_PHY_REG(PCIE_PHY_TX2_MOD1(pcie_port), 0x1FFE, 0xFFFF);\n+    IFX_PCIE_PHY_REG(PCIE_PHY_TX2_MOD2(pcie_port), 0xFFFE, 0xFFFF);\n+    IFX_PCIE_PHY_REG(PCIE_PHY_TX2_MOD3(pcie_port), 0x0601, 0xFFFF);\n+    mdelay(1);\n+    IFX_PCIE_PHY_REG(PCIE_PHY_TX2_MOD3(pcie_port), 0x0001, 0xFFFF);\n+}\n+\n+static void \n+pcie_phy_tx1_modulation(int pcie_port)\n+{\n+    IFX_PCIE_PHY_REG(PCIE_PHY_TX1_MOD1(pcie_port), 0x1FFE, 0xFFFF);\n+    IFX_PCIE_PHY_REG(PCIE_PHY_TX1_MOD2(pcie_port), 0xFFFE, 0xFFFF);\n+    IFX_PCIE_PHY_REG(PCIE_PHY_TX1_MOD3(pcie_port), 0x0601, 0xFFFF);\n+    mdelay(1);\n+    IFX_PCIE_PHY_REG(PCIE_PHY_TX1_MOD3(pcie_port), 0x0001, 0xFFFF);\n+}\n+\n+static void\n+pcie_phy_tx_modulation_war(int pcie_port)\n+{\n+    int i;\n+\n+#define PCIE_PHY_MODULATION_NUM 5 \n+    for (i = 0; i < PCIE_PHY_MODULATION_NUM; i++) {\n+        pcie_phy_tx2_modulation(pcie_port);\n+        pcie_phy_tx1_modulation(pcie_port);\n+    }\n+#undef PCIE_PHY_MODULATION_NUM\n+}\n+\n+void\n+pcie_phy_clock_mode_setup(int pcie_port)\n+{\n+    pcie_pdi_big_endian(pcie_port);\n+\n+    /* Enable PDI to access PCIe PHY register */\n+    pcie_pdi_pmu_enable(pcie_port);\n+\n+    /* Configure PLL and PHY clock */\n+    pcie_phy_comm_setup(pcie_port);\n+\n+#ifdef CONFIG_IFX_PCIE_PHY_36MHZ_MODE\n+    pcie_phy_36mhz_mode_setup(pcie_port);\n+#elif defined(CONFIG_IFX_PCIE_PHY_36MHZ_SSC_MODE)\n+    pcie_phy_36mhz_ssc_mode_setup(pcie_port);\n+#elif defined(CONFIG_IFX_PCIE_PHY_25MHZ_MODE)\n+    pcie_phy_25mhz_mode_setup(pcie_port);\n+#elif defined (CONFIG_IFX_PCIE_PHY_100MHZ_MODE)\n+    pcie_phy_100mhz_mode_setup(pcie_port);\n+#else\n+    #error \"PCIE PHY Clock Mode must be chosen first!!!!\"\n+#endif /* CONFIG_IFX_PCIE_PHY_36MHZ_MODE */\n+\n+    /* Enable PCIe PHY and make PLL setting take effect */\n+    pcie_phy_pmu_enable(pcie_port);\n+\n+    /* Check if we are in startup_ready status */\n+    pcie_phy_wait_startup_ready(pcie_port);\n+\n+    pcie_phy_load_war(pcie_port);\n+\n+    /* Apply TX modulation workarounds */\n+    pcie_phy_tx_modulation_war(pcie_port);\n+\n+#ifdef IFX_PCI_PHY_REG_DUMP\n+    IFX_PCIE_PRINT(PCIE_MSG_PHY, \"Modified PHY register dump\\n\");\n+    pcie_phy_reg_dump(pcie_port);\n+#endif\n+}\n+\n--- /dev/null\n+++ b/arch/mips/pci/ifxmips_pcie_pm.c\n@@ -0,0 +1,176 @@\n+/******************************************************************************\n+**\n+** FILE NAME    : ifxmips_pcie_pm.c\n+** PROJECT      : IFX UEIP\n+** MODULES      : PCIE Root Complex Driver\n+**\n+** DATE         : 21 Dec 2009\n+** AUTHOR       : Lei Chuanhua\n+** DESCRIPTION  : PCIE Root Complex Driver Power Managment\n+** COPYRIGHT    :       Copyright (c) 2009\n+**                      Lantiq Deutschland GmbH\n+**                      Am Campeon 3, 85579 Neubiberg, Germany\n+**\n+**    This program is free software; you can redistribute it and/or modify\n+**    it under the terms of the GNU General Public License as published by\n+**    the Free Software Foundation; either version 2 of the License, or\n+**    (at your option) any later version.\n+**\n+** HISTORY\n+** $Date        $Author         $Comment\n+** 21 Dec,2009   Lei Chuanhua    First UEIP release\n+*******************************************************************************/\n+/*!\n+  \\defgroup IFX_PCIE_PM Power Management functions\n+  \\ingroup IFX_PCIE\n+  \\brief IFX PCIE Root Complex Driver power management functions\n+*/\n+\n+/*!\n+ \\file ifxmips_pcie_pm.c\n+ \\ingroup IFX_PCIE    \n+ \\brief source file for PCIE Root Complex Driver Power Management\n+*/\n+\n+#ifndef EXPORT_SYMTAB\n+#define EXPORT_SYMTAB\n+#endif\n+#ifndef AUTOCONF_INCLUDED\n+#include <linux/config.h>\n+#endif /* AUTOCONF_INCLUDED */\n+#include <linux/version.h>\n+#include <linux/module.h>\n+#include <linux/types.h>\n+#include <linux/kernel.h>\n+#include <asm/system.h>\n+\n+/* Project header */\n+#include <asm/ifx/ifx_types.h>\n+#include <asm/ifx/ifx_regs.h>\n+#include <asm/ifx/common_routines.h>\n+#include <asm/ifx/ifx_pmcu.h>\n+#include \"ifxmips_pcie_pm.h\"\n+\n+/** \n+ * \\fn static IFX_PMCU_RETURN_t ifx_pcie_pmcu_state_change(IFX_PMCU_STATE_t pmcuState)\n+ * \\brief the callback function to request pmcu state in the power management hardware-dependent module\n+ *\n+ * \\param pmcuState This parameter is a PMCU state.\n+ *\n+ * \\return IFX_PMCU_RETURN_SUCCESS Set Power State successfully\n+ * \\return IFX_PMCU_RETURN_ERROR   Failed to set power state.\n+ * \\return IFX_PMCU_RETURN_DENIED  Not allowed to operate power state\n+ * \\ingroup IFX_PCIE_PM\n+ */\n+static IFX_PMCU_RETURN_t \n+ifx_pcie_pmcu_state_change(IFX_PMCU_STATE_t pmcuState)\n+{\n+    switch(pmcuState) \n+    {\n+        case IFX_PMCU_STATE_D0:\n+            return IFX_PMCU_RETURN_SUCCESS;\n+        case IFX_PMCU_STATE_D1: // Not Applicable\n+            return IFX_PMCU_RETURN_DENIED;\n+        case IFX_PMCU_STATE_D2: // Not Applicable\n+            return IFX_PMCU_RETURN_DENIED;\n+        case IFX_PMCU_STATE_D3: // Module clock gating and Power gating\n+            return IFX_PMCU_RETURN_SUCCESS;\n+        default:\n+            return IFX_PMCU_RETURN_DENIED;\n+    }\n+}\n+\n+/** \n+ * \\fn static IFX_PMCU_RETURN_t ifx_pcie_pmcu_state_get(IFX_PMCU_STATE_t *pmcuState)\n+ * \\brief the callback function to get pmcu state in the power management hardware-dependent module\n+\n+ * \\param pmcuState Pointer to return power state.\n+ *\n+ * \\return IFX_PMCU_RETURN_SUCCESS Set Power State successfully\n+ * \\return IFX_PMCU_RETURN_ERROR   Failed to set power state.\n+ * \\return IFX_PMCU_RETURN_DENIED  Not allowed to operate power state\n+ * \\ingroup IFX_PCIE_PM\n+ */\n+static IFX_PMCU_RETURN_t \n+ifx_pcie_pmcu_state_get(IFX_PMCU_STATE_t *pmcuState)\n+{\n+    return IFX_PMCU_RETURN_SUCCESS;\n+}\n+\n+/**\n+ * \\fn IFX_PMCU_RETURN_t ifx_pcie_pmcu_prechange(IFX_PMCU_MODULE_t pmcuModule, IFX_PMCU_STATE_t newState, IFX_PMCU_STATE_t oldState)\n+ * \\brief Apply all callbacks registered to be executed before a state change for pmcuModule\n+ * \n+ * \\param   pmcuModule      Module\n+ * \\param   newState        New state\n+ * \\param   oldState        Old state\n+ * \\return  IFX_PMCU_RETURN_SUCCESS Set Power State successfully\n+ * \\return  IFX_PMCU_RETURN_ERROR   Failed to set power state.\n+ * \\ingroup IFX_PCIE_PM\n+ */\n+static IFX_PMCU_RETURN_t \n+ifx_pcie_pmcu_prechange(IFX_PMCU_MODULE_t pmcuModule, IFX_PMCU_STATE_t newState, IFX_PMCU_STATE_t oldState)\n+{\n+    return IFX_PMCU_RETURN_SUCCESS;\n+}\n+\n+/**\n+ * \\fn IFX_PMCU_RETURN_t ifx_pcie_pmcu_postchange(IFX_PMCU_MODULE_t pmcuModule, IFX_PMCU_STATE_t newState, IFX_PMCU_STATE_t oldState)\n+ * \\brief Apply all callbacks registered to be executed before a state change for pmcuModule\n+ * \n+ * \\param   pmcuModule      Module\n+ * \\param   newState        New state\n+ * \\param   oldState        Old state\n+ * \\return IFX_PMCU_RETURN_SUCCESS Set Power State successfully\n+ * \\return IFX_PMCU_RETURN_ERROR   Failed to set power state.\n+ * \\ingroup IFX_PCIE_PM\n+ */\n+static IFX_PMCU_RETURN_t \n+ifx_pcie_pmcu_postchange(IFX_PMCU_MODULE_t pmcuModule, IFX_PMCU_STATE_t newState, IFX_PMCU_STATE_t oldState)\n+{\n+    return IFX_PMCU_RETURN_SUCCESS;\n+}\n+\n+/** \n+ * \\fn static void ifx_pcie_pmcu_init(void)\n+ * \\brief Register with central PMCU module\n+ * \\return none\n+ * \\ingroup IFX_PCIE_PM\n+ */\n+void\n+ifx_pcie_pmcu_init(void)\n+{\n+    IFX_PMCU_REGISTER_t pmcuRegister;\n+\n+    /* XXX, hook driver context */\n+\n+    /* State function register */\n+    memset(&pmcuRegister, 0, sizeof(IFX_PMCU_REGISTER_t));\n+    pmcuRegister.pmcuModule = IFX_PMCU_MODULE_PCIE;\n+    pmcuRegister.pmcuModuleNr = 0;\n+    pmcuRegister.ifx_pmcu_state_change = ifx_pcie_pmcu_state_change;\n+    pmcuRegister.ifx_pmcu_state_get = ifx_pcie_pmcu_state_get;\n+    pmcuRegister.pre = ifx_pcie_pmcu_prechange;\n+    pmcuRegister.post= ifx_pcie_pmcu_postchange;\n+    ifx_pmcu_register(&pmcuRegister); \n+}\n+\n+/** \n+ * \\fn static void ifx_pcie_pmcu_exit(void)\n+ * \\brief Unregister with central PMCU module\n+ *\n+ * \\return none\n+ * \\ingroup IFX_PCIE_PM\n+ */\n+void\n+ifx_pcie_pmcu_exit(void)\n+{\n+    IFX_PMCU_REGISTER_t pmcuUnRegister;\n+\n+   /* XXX, hook driver context */\n+   \n+    pmcuUnRegister.pmcuModule = IFX_PMCU_MODULE_PCIE;\n+    pmcuUnRegister.pmcuModuleNr = 0;\n+    ifx_pmcu_unregister(&pmcuUnRegister);\n+}\n+\n--- /dev/null\n+++ b/arch/mips/pci/ifxmips_pcie_pm.h\n@@ -0,0 +1,36 @@\n+/******************************************************************************\n+**\n+** FILE NAME    : ifxmips_pcie_pm.h\n+** PROJECT      : IFX UEIP\n+** MODULES      : PCIe Root Complex Driver\n+**\n+** DATE         : 21 Dec 2009\n+** AUTHOR       : Lei Chuanhua\n+** DESCRIPTION  : PCIe Root Complex Driver Power Managment\n+** COPYRIGHT    :       Copyright (c) 2009\n+**                      Lantiq Deutschland GmbH\n+**                      Am Campeon 3, 85579 Neubiberg, Germany\n+**\n+**    This program is free software; you can redistribute it and/or modify\n+**    it under the terms of the GNU General Public License as published by\n+**    the Free Software Foundation; either version 2 of the License, or\n+**    (at your option) any later version.\n+**\n+** HISTORY\n+** $Date        $Author         $Comment\n+** 21 Dec,2009   Lei Chuanhua    First UEIP release\n+*******************************************************************************/\n+/*!\n+ \\file ifxmips_pcie_pm.h\n+ \\ingroup IFX_PCIE \n+ \\brief header file for PCIe Root Complex Driver Power Management\n+*/\n+\n+#ifndef IFXMIPS_PCIE_PM_H\n+#define IFXMIPS_PCIE_PM_H\n+\n+void ifx_pcie_pmcu_init(void);\n+void ifx_pcie_pmcu_exit(void);\n+\n+#endif /* IFXMIPS_PCIE_PM_H  */\n+\n--- /dev/null\n+++ b/arch/mips/pci/ifxmips_pcie_reg.h\n@@ -0,0 +1,1001 @@\n+/******************************************************************************\n+**\n+** FILE NAME    : ifxmips_pcie_reg.h\n+** PROJECT      : IFX UEIP for VRX200\n+** MODULES      : PCIe module\n+**\n+** DATE         : 02 Mar 2009\n+** AUTHOR       : Lei Chuanhua\n+** DESCRIPTION  : PCIe Root Complex Driver\n+** COPYRIGHT    :       Copyright (c) 2009\n+**                      Infineon Technologies AG\n+**                      Am Campeon 1-12, 85579 Neubiberg, Germany\n+**\n+**    This program is free software; you can redistribute it and/or modify\n+**    it under the terms of the GNU General Public License as published by\n+**    the Free Software Foundation; either version 2 of the License, or\n+**    (at your option) any later version.\n+** HISTORY\n+** $Version $Date        $Author         $Comment\n+** 0.0.1    17 Mar,2009  Lei Chuanhua    Initial version\n+*******************************************************************************/\n+#ifndef IFXMIPS_PCIE_REG_H\n+#define IFXMIPS_PCIE_REG_H\n+/*!\n+ \\file ifxmips_pcie_reg.h\n+ \\ingroup IFX_PCIE  \n+ \\brief header file for PCIe module register definition\n+*/\n+/* PCIe Address Mapping Base */\n+#define PCIE_CFG_PHY_BASE        0x1D000000UL\n+#define PCIE_CFG_BASE           (KSEG1 + PCIE_CFG_PHY_BASE)\n+#define PCIE_CFG_SIZE           (8 * 1024 * 1024)\n+\n+#define PCIE_MEM_PHY_BASE        0x1C000000UL\n+#define PCIE_MEM_BASE           (KSEG1 + PCIE_MEM_PHY_BASE)\n+#define PCIE_MEM_SIZE           (16 * 1024 * 1024)\n+#define PCIE_MEM_PHY_END        (PCIE_MEM_PHY_BASE + PCIE_MEM_SIZE - 1)\n+\n+#define PCIE_IO_PHY_BASE         0x1D800000UL\n+#define PCIE_IO_BASE            (KSEG1 + PCIE_IO_PHY_BASE)\n+#define PCIE_IO_SIZE            (1 * 1024 * 1024)\n+#define PCIE_IO_PHY_END         (PCIE_IO_PHY_BASE + PCIE_IO_SIZE - 1)\n+\n+#define PCIE_RC_CFG_BASE        (KSEG1 + 0x1D900000)\n+#define PCIE_APP_LOGIC_REG      (KSEG1 + 0x1E100900)\n+#define PCIE_MSI_PHY_BASE        0x1F600000UL\n+\n+#define PCIE_PDI_PHY_BASE        0x1F106800UL\n+#define PCIE_PDI_BASE           (KSEG1 + PCIE_PDI_PHY_BASE)\n+#define PCIE_PDI_SIZE            0x400\n+\n+#define PCIE1_CFG_PHY_BASE        0x19000000UL\n+#define PCIE1_CFG_BASE           (KSEG1 + PCIE1_CFG_PHY_BASE)\n+#define PCIE1_CFG_SIZE           (8 * 1024 * 1024)\n+\n+#define PCIE1_MEM_PHY_BASE        0x18000000UL\n+#define PCIE1_MEM_BASE           (KSEG1 + PCIE1_MEM_PHY_BASE)\n+#define PCIE1_MEM_SIZE           (16 * 1024 * 1024)\n+#define PCIE1_MEM_PHY_END        (PCIE1_MEM_PHY_BASE + PCIE1_MEM_SIZE - 1)\n+\n+#define PCIE1_IO_PHY_BASE         0x19800000UL\n+#define PCIE1_IO_BASE            (KSEG1 + PCIE1_IO_PHY_BASE)\n+#define PCIE1_IO_SIZE            (1 * 1024 * 1024)\n+#define PCIE1_IO_PHY_END         (PCIE1_IO_PHY_BASE + PCIE1_IO_SIZE - 1)\n+\n+#define PCIE1_RC_CFG_BASE        (KSEG1 + 0x19900000)\n+#define PCIE1_APP_LOGIC_REG      (KSEG1 + 0x1E100700)\n+#define PCIE1_MSI_PHY_BASE        0x1F400000UL\n+\n+#define PCIE1_PDI_PHY_BASE        0x1F700400UL\n+#define PCIE1_PDI_BASE           (KSEG1 + PCIE1_PDI_PHY_BASE)\n+#define PCIE1_PDI_SIZE            0x400\n+\n+#define PCIE_CFG_PORT_TO_BASE(X)     ((X) > 0 ? (PCIE1_CFG_BASE) : (PCIE_CFG_BASE))\n+#define PCIE_MEM_PORT_TO_BASE(X)     ((X) > 0 ? (PCIE1_MEM_BASE) : (PCIE_MEM_BASE))\n+#define PCIE_IO_PORT_TO_BASE(X)      ((X) > 0 ? (PCIE1_IO_BASE) : (PCIE_IO_BASE))\n+#define PCIE_MEM_PHY_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_MEM_PHY_BASE) : (PCIE_MEM_PHY_BASE))\n+#define PCIE_MEM_PHY_PORT_TO_END(X)  ((X) > 0 ? (PCIE1_MEM_PHY_END) : (PCIE_MEM_PHY_END))\n+#define PCIE_IO_PHY_PORT_TO_BASE(X)  ((X) > 0 ? (PCIE1_IO_PHY_BASE) : (PCIE_IO_PHY_BASE))\n+#define PCIE_IO_PHY_PORT_TO_END(X)   ((X) > 0 ? (PCIE1_IO_PHY_END) : (PCIE_IO_PHY_END))\n+#define PCIE_APP_PORT_TO_BASE(X)     ((X) > 0 ? (PCIE1_APP_LOGIC_REG) : (PCIE_APP_LOGIC_REG))\n+#define PCIE_RC_PORT_TO_BASE(X)      ((X) > 0 ? (PCIE1_RC_CFG_BASE) : (PCIE_RC_CFG_BASE))\n+#define PCIE_PHY_PORT_TO_BASE(X)     ((X) > 0 ? (PCIE1_PDI_BASE) : (PCIE_PDI_BASE))\n+\n+/* PCIe Application Logic Register */\n+/* RC Core Control Register */\n+#define PCIE_RC_CCR(X)                      (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x10)\n+/* This should be enabled after initializing configuratin registers\n+ * Also should check link status retraining bit\n+ */\n+#define PCIE_RC_CCR_LTSSM_ENABLE             0x00000001    /* Enable LTSSM to continue link establishment */\n+\n+/* RC Core Debug Register */\n+#define PCIE_RC_DR(X)                       (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x14)\n+#define PCIE_RC_DR_DLL_UP                    0x00000001  /* Data Link Layer Up */\n+#define PCIE_RC_DR_CURRENT_POWER_STATE       0x0000000E  /* Current Power State */\n+#define PCIE_RC_DR_CURRENT_POWER_STATE_S     1\n+#define PCIE_RC_DR_CURRENT_LTSSM_STATE       0x000001F0  /* Current LTSSM State */\n+#define PCIE_RC_DR_CURRENT_LTSSM_STATE_S     4\n+\n+#define PCIE_RC_DR_PM_DEV_STATE              0x00000E00  /* Power Management D-State */\n+#define PCIE_RC_DR_PM_DEV_STATE_S            9\n+\n+#define PCIE_RC_DR_PM_ENABLED                0x00001000  /* Power Management State from PMU */\n+#define PCIE_RC_DR_PME_EVENT_ENABLED         0x00002000  /* Power Management Event Enable State */\n+#define PCIE_RC_DR_AUX_POWER_ENABLED         0x00004000  /* Auxiliary Power Enable */\n+\n+/* Current Power State Definition */\n+enum {\n+    PCIE_RC_DR_D0 = 0,\n+    PCIE_RC_DR_D1,   /* Not supported */\n+    PCIE_RC_DR_D2,   /* Not supported */\n+    PCIE_RC_DR_D3,\n+    PCIE_RC_DR_UN,\n+};\n+\n+/* PHY Link Status Register */\n+#define PCIE_PHY_SR(X)                      (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x18)\n+#define PCIE_PHY_SR_PHY_LINK_UP              0x00000001   /* PHY Link Up/Down Indicator */\n+\n+/* Electromechanical Control Register */\n+#define PCIE_EM_CR(X)                       (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x1C)\n+#define PCIE_EM_CR_CARD_IS_PRESENT           0x00000001  /* Card Presence Detect State */\n+#define PCIE_EM_CR_MRL_OPEN                  0x00000002  /* MRL Sensor State */\n+#define PCIE_EM_CR_POWER_FAULT_SET           0x00000004  /* Power Fault Detected */\n+#define PCIE_EM_CR_MRL_SENSOR_SET            0x00000008  /* MRL Sensor Changed */\n+#define PCIE_EM_CR_PRESENT_DETECT_SET        0x00000010  /* Card Presense Detect Changed */\n+#define PCIE_EM_CR_CMD_CPL_INT_SET           0x00000020  /* Command Complete Interrupt */\n+#define PCIE_EM_CR_SYS_INTERLOCK_SET         0x00000040  /* System Electromechanical IterLock Engaged */\n+#define PCIE_EM_CR_ATTENTION_BUTTON_SET      0x00000080  /* Attention Button Pressed */\n+\n+/* Interrupt Status Register */\n+#define PCIE_IR_SR(X)                       (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x20)\n+#define PCIE_IR_SR_PME_CAUSE_MSI             0x00000002  /* MSI caused by PME */\n+#define PCIE_IR_SR_HP_PME_WAKE_GEN           0x00000004  /* Hotplug PME Wake Generation */\n+#define PCIE_IR_SR_HP_MSI                    0x00000008  /* Hotplug MSI */\n+#define PCIE_IR_SR_AHB_LU_ERR                0x00000030  /* AHB Bridge Lookup Error Signals */\n+#define PCIE_IR_SR_AHB_LU_ERR_S              4\n+#define PCIE_IR_SR_INT_MSG_NUM               0x00003E00  /* Interrupt Message Number */\n+#define PCIE_IR_SR_INT_MSG_NUM_S             9\n+#define PCIE_IR_SR_AER_INT_MSG_NUM           0xF8000000  /* Advanced Error Interrupt Message Number */\n+#define PCIE_IR_SR_AER_INT_MSG_NUM_S         27\n+\n+/* Message Control Register */\n+#define PCIE_MSG_CR(X)                      (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x30)\n+#define PCIE_MSG_CR_GEN_PME_TURN_OFF_MSG     0x00000001  /* Generate PME Turn Off Message */\n+#define PCIE_MSG_CR_GEN_UNLOCK_MSG           0x00000002  /* Generate Unlock Message */\n+\n+#define PCIE_VDM_DR(X)                      (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x34)\n+\n+/* Vendor-Defined Message Requester ID Register */\n+#define PCIE_VDM_RID(X)                     (PCIE_APP_PORT_TO_BASE (X) + 0x38)\n+#define PCIE_VDM_RID_VENROR_MSG_REQ_ID       0x0000FFFF\n+#define PCIE_VDM_RID_VDMRID_S                0\n+\n+/* ASPM Control Register */\n+#define PCIE_ASPM_CR(X)                     (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x40)\n+#define PCIE_ASPM_CR_HOT_RST                 0x00000001  /* Hot Reset Request to the downstream device */\n+#define PCIE_ASPM_CR_REQ_EXIT_L1             0x00000002  /* Request to Exit L1 */\n+#define PCIE_ASPM_CR_REQ_ENTER_L1            0x00000004  /* Request to Enter L1 */\n+\n+/* Vendor Message DW0 Register */\n+#define PCIE_VM_MSG_DW0(X)                  (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x50)\n+#define PCIE_VM_MSG_DW0_TYPE                 0x0000001F  /* Message type */\n+#define PCIE_VM_MSG_DW0_TYPE_S               0\n+#define PCIE_VM_MSG_DW0_FORMAT               0x00000060  /* Format */\n+#define PCIE_VM_MSG_DW0_FORMAT_S             5\n+#define PCIE_VM_MSG_DW0_TC                   0x00007000  /* Traffic Class */\n+#define PCIE_VM_MSG_DW0_TC_S                 12\n+#define PCIE_VM_MSG_DW0_ATTR                 0x000C0000  /* Atrributes */\n+#define PCIE_VM_MSG_DW0_ATTR_S               18\n+#define PCIE_VM_MSG_DW0_EP_TLP               0x00100000  /* Poisoned TLP */\n+#define PCIE_VM_MSG_DW0_TD                   0x00200000  /* TLP Digest */\n+#define PCIE_VM_MSG_DW0_LEN                  0xFFC00000  /* Length */\n+#define PCIE_VM_MSG_DW0_LEN_S                22\n+\n+/* Format Definition */\n+enum {\n+    PCIE_VM_MSG_FORMAT_00 = 0,  /* 3DW Hdr, no data*/\n+    PCIE_VM_MSG_FORMAT_01,      /* 4DW Hdr, no data */\n+    PCIE_VM_MSG_FORMAT_10,      /* 3DW Hdr, with data */\n+    PCIE_VM_MSG_FORMAT_11,      /* 4DW Hdr, with data */\n+};\n+\n+/* Traffic Class Definition */\n+enum {\n+    PCIE_VM_MSG_TC0 = 0,\n+    PCIE_VM_MSG_TC1,\n+    PCIE_VM_MSG_TC2,\n+    PCIE_VM_MSG_TC3,\n+    PCIE_VM_MSG_TC4,\n+    PCIE_VM_MSG_TC5,\n+    PCIE_VM_MSG_TC6,\n+    PCIE_VM_MSG_TC7,\n+};\n+\n+/* Attributes Definition */\n+enum {\n+    PCIE_VM_MSG_ATTR_00 = 0,   /* RO and No Snoop cleared */\n+    PCIE_VM_MSG_ATTR_01,       /* RO cleared , No Snoop set */\n+    PCIE_VM_MSG_ATTR_10,       /* RO set, No Snoop cleared*/\n+    PCIE_VM_MSG_ATTR_11,       /* RO and No Snoop set */\n+};\n+\n+/* Payload Size Definition */\n+#define PCIE_VM_MSG_LEN_MIN  0\n+#define PCIE_VM_MSG_LEN_MAX  1024\n+\n+/* Vendor Message DW1 Register */\n+#define PCIE_VM_MSG_DW1(X)                 (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x54)\n+#define PCIE_VM_MSG_DW1_FUNC_NUM            0x00000070  /* Function Number */\n+#define PCIE_VM_MSG_DW1_FUNC_NUM_S          8\n+#define PCIE_VM_MSG_DW1_CODE                0x00FF0000  /* Message Code */\n+#define PCIE_VM_MSG_DW1_CODE_S              16\n+#define PCIE_VM_MSG_DW1_TAG                 0xFF000000  /* Tag */\n+#define PCIE_VM_MSG_DW1_TAG_S               24\n+\n+#define PCIE_VM_MSG_DW2(X)                  (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x58)\n+#define PCIE_VM_MSG_DW3(X)                  (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x5C)\n+\n+/* Vendor Message Request Register */\n+#define PCIE_VM_MSG_REQR(X)                 (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x60)\n+#define PCIE_VM_MSG_REQR_REQ                 0x00000001  /* Vendor Message Request */\n+\n+\n+/* AHB Slave Side Band Control Register */\n+#define PCIE_AHB_SSB(X)                     (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x70)\n+#define PCIE_AHB_SSB_REQ_BCM                0x00000001 /* Slave Reques BCM filed */\n+#define PCIE_AHB_SSB_REQ_EP                 0x00000002 /* Slave Reques EP filed */\n+#define PCIE_AHB_SSB_REQ_TD                 0x00000004 /* Slave Reques TD filed */\n+#define PCIE_AHB_SSB_REQ_ATTR               0x00000018 /* Slave Reques Attribute number */\n+#define PCIE_AHB_SSB_REQ_ATTR_S             3\n+#define PCIE_AHB_SSB_REQ_TC                 0x000000E0 /* Slave Request TC Field */\n+#define PCIE_AHB_SSB_REQ_TC_S               5\n+\n+/* AHB Master SideBand Ctrl Register */\n+#define PCIE_AHB_MSB(X)                     (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x74)\n+#define PCIE_AHB_MSB_RESP_ATTR               0x00000003 /* Master Response Attribute number */\n+#define PCIE_AHB_MSB_RESP_ATTR_S             0\n+#define PCIE_AHB_MSB_RESP_BAD_EOT            0x00000004 /* Master Response Badeot filed */\n+#define PCIE_AHB_MSB_RESP_BCM                0x00000008 /* Master Response BCM filed */\n+#define PCIE_AHB_MSB_RESP_EP                 0x00000010 /* Master Response EP filed */\n+#define PCIE_AHB_MSB_RESP_TD                 0x00000020 /* Master Response TD filed */\n+#define PCIE_AHB_MSB_RESP_FUN_NUM            0x000003C0 /* Master Response Function number */\n+#define PCIE_AHB_MSB_RESP_FUN_NUM_S          6\n+\n+/* AHB Control Register, fixed bus enumeration exception */\n+#define PCIE_AHB_CTRL(X)                     (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x78)\n+#define PCIE_AHB_CTRL_BUS_ERROR_SUPPRESS     0x00000001 \n+\n+/* Interrupt Enalbe Register */\n+#define PCIE_IRNEN(X)                        (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0xF4)\n+#define PCIE_IRNCR(X)                        (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0xF8)\n+#define PCIE_IRNICR(X)                       (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0xFC)\n+\n+/* PCIe interrupt enable/control/capture register definition */\n+#define PCIE_IRN_AER_REPORT                 0x00000001  /* AER Interrupt */\n+#define PCIE_IRN_AER_MSIX                   0x00000002  /* Advanced Error MSI-X Interrupt */\n+#define PCIE_IRN_PME                        0x00000004  /* PME Interrupt */\n+#define PCIE_IRN_HOTPLUG                    0x00000008  /* Hotplug Interrupt */\n+#define PCIE_IRN_RX_VDM_MSG                 0x00000010  /* Vendor-Defined Message Interrupt */\n+#define PCIE_IRN_RX_CORRECTABLE_ERR_MSG     0x00000020  /* Correctable Error Message Interrupt */\n+#define PCIE_IRN_RX_NON_FATAL_ERR_MSG       0x00000040  /* Non-fatal Error Message */\n+#define PCIE_IRN_RX_FATAL_ERR_MSG           0x00000080  /* Fatal Error Message */\n+#define PCIE_IRN_RX_PME_MSG                 0x00000100  /* PME Message Interrupt */\n+#define PCIE_IRN_RX_PME_TURNOFF_ACK         0x00000200  /* PME Turnoff Ack Message Interrupt */\n+#define PCIE_IRN_AHB_BR_FATAL_ERR           0x00000400  /* AHB Fatal Error Interrupt */\n+#define PCIE_IRN_LINK_AUTO_BW_STATUS        0x00000800  /* Link Auto Bandwidth Status Interrupt */\n+#define PCIE_IRN_BW_MGT                     0x00001000  /* Bandwidth Managment Interrupt */\n+#define PCIE_IRN_INTA                       0x00002000  /* INTA */\n+#define PCIE_IRN_INTB                       0x00004000  /* INTB */\n+#define PCIE_IRN_INTC                       0x00008000  /* INTC */\n+#define PCIE_IRN_INTD                       0x00010000  /* INTD */\n+#define PCIE_IRN_WAKEUP                     0x00020000  /* Wake up Interrupt */\n+\n+#define PCIE_RC_CORE_COMBINED_INT    (PCIE_IRN_AER_REPORT |  PCIE_IRN_AER_MSIX | PCIE_IRN_PME | \\\n+                                      PCIE_IRN_HOTPLUG | PCIE_IRN_RX_VDM_MSG | PCIE_IRN_RX_CORRECTABLE_ERR_MSG |\\\n+                                      PCIE_IRN_RX_NON_FATAL_ERR_MSG | PCIE_IRN_RX_FATAL_ERR_MSG | \\\n+                                      PCIE_IRN_RX_PME_MSG | PCIE_IRN_RX_PME_TURNOFF_ACK | PCIE_IRN_AHB_BR_FATAL_ERR | \\\n+                                      PCIE_IRN_LINK_AUTO_BW_STATUS | PCIE_IRN_BW_MGT)\n+/* PCIe RC Configuration Register */\n+#define PCIE_VDID(X)                (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x00)\n+\n+/* Bit definition from pci_reg.h */\n+#define PCIE_PCICMDSTS(X)           (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x04)\n+#define PCIE_CCRID(X)               (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x08)\n+#define PCIE_CLSLTHTBR(X)           (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x0C) /* EP only */\n+/* BAR0, BAR1,Only necessary if the bridges implements a device-specific register set or memory buffer */\n+#define PCIE_BAR0(X)                (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x10) /* Not used*/\n+#define PCIE_BAR1(X)                (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x14) /* Not used */\n+\n+#define PCIE_BNR(X)                 (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x18) /* Mandatory */\n+/* Bus Number Register bits */\n+#define PCIE_BNR_PRIMARY_BUS_NUM             0x000000FF\n+#define PCIE_BNR_PRIMARY_BUS_NUM_S           0\n+#define PCIE_PNR_SECONDARY_BUS_NUM           0x0000FF00\n+#define PCIE_PNR_SECONDARY_BUS_NUM_S         8\n+#define PCIE_PNR_SUB_BUS_NUM                 0x00FF0000\n+#define PCIE_PNR_SUB_BUS_NUM_S               16\n+\n+/* IO Base/Limit Register bits */\n+#define PCIE_IOBLSECS(X)                       (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x1C)  /* RC only */\n+#define PCIE_IOBLSECS_32BIT_IO_ADDR             0x00000001\n+#define PCIE_IOBLSECS_IO_BASE_ADDR              0x000000F0\n+#define PCIE_IOBLSECS_IO_BASE_ADDR_S            4\n+#define PCIE_IOBLSECS_32BIT_IOLIMT              0x00000100\n+#define PCIE_IOBLSECS_IO_LIMIT_ADDR             0x0000F000\n+#define PCIE_IOBLSECS_IO_LIMIT_ADDR_S           12\n+\n+/* Non-prefetchable Memory Base/Limit Register bit */\n+#define PCIE_MBML(X)                           (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x20)  /* RC only */\n+#define PCIE_MBML_MEM_BASE_ADDR                 0x0000FFF0\n+#define PCIE_MBML_MEM_BASE_ADDR_S               4\n+#define PCIE_MBML_MEM_LIMIT_ADDR                0xFFF00000\n+#define PCIE_MBML_MEM_LIMIT_ADDR_S              20\n+\n+/* Prefetchable Memory Base/Limit Register bit */\n+#define PCIE_PMBL(X)                           (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x24)  /* RC only */\n+#define PCIE_PMBL_64BIT_ADDR                    0x00000001\n+#define PCIE_PMBL_UPPER_12BIT                   0x0000FFF0\n+#define PCIE_PMBL_UPPER_12BIT_S                 4\n+#define PCIE_PMBL_E64MA                         0x00010000\n+#define PCIE_PMBL_END_ADDR                      0xFFF00000\n+#define PCIE_PMBL_END_ADDR_S                    20\n+#define PCIE_PMBU32(X)                          (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x28)  /* RC only */\n+#define PCIE_PMLU32(X)                          (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x2C)  /* RC only */\n+\n+/* I/O Base/Limit Upper 16 bits register */\n+#define PCIE_IO_BANDL(X)                        (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x30)  /* RC only */\n+#define PCIE_IO_BANDL_UPPER_16BIT_IO_BASE        0x0000FFFF\n+#define PCIE_IO_BANDL_UPPER_16BIT_IO_BASE_S      0\n+#define PCIE_IO_BANDL_UPPER_16BIT_IO_LIMIT       0xFFFF0000\n+#define PCIE_IO_BANDL_UPPER_16BIT_IO_LIMIT_S     16\n+\n+#define PCIE_CPR(X)                            (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x34)\n+#define PCIE_EBBAR(X)                          (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x38)\n+\n+/* Interrupt and Secondary Bridge Control Register */\n+#define PCIE_INTRBCTRL(X)                      (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x3C)\n+\n+#define PCIE_INTRBCTRL_INT_LINE                 0x000000FF\n+#define PCIE_INTRBCTRL_INT_LINE_S               0\n+#define PCIE_INTRBCTRL_INT_PIN                  0x0000FF00\n+#define PCIE_INTRBCTRL_INT_PIN_S                8\n+#define PCIE_INTRBCTRL_PARITY_ERR_RESP_ENABLE   0x00010000    /* #PERR */\n+#define PCIE_INTRBCTRL_SERR_ENABLE              0x00020000    /* #SERR */\n+#define PCIE_INTRBCTRL_ISA_ENABLE               0x00040000    /* ISA enable, IO 64KB only */\n+#define PCIE_INTRBCTRL_VGA_ENABLE               0x00080000    /* VGA enable */\n+#define PCIE_INTRBCTRL_VGA_16BIT_DECODE         0x00100000    /* VGA 16bit decode */\n+#define PCIE_INTRBCTRL_RST_SECONDARY_BUS        0x00400000    /* Secondary bus rest, hot rest, 1ms */\n+/* Others are read only */\n+enum {\n+    PCIE_INTRBCTRL_INT_NON = 0,\n+    PCIE_INTRBCTRL_INTA,\n+    PCIE_INTRBCTRL_INTB,\n+    PCIE_INTRBCTRL_INTC,\n+    PCIE_INTRBCTRL_INTD,\n+};\n+\n+#define PCIE_PM_CAPR(X)                  (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x40)\n+\n+/* Power Management Control and Status Register */\n+#define PCIE_PM_CSR(X)                   (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x44)\n+\n+#define PCIE_PM_CSR_POWER_STATE           0x00000003   /* Power State */\n+#define PCIE_PM_CSR_POWER_STATE_S         0\n+#define PCIE_PM_CSR_SW_RST                0x00000008   /* Soft Reset Enabled */\n+#define PCIE_PM_CSR_PME_ENABLE            0x00000100   /* PME Enable */\n+#define PCIE_PM_CSR_PME_STATUS            0x00008000   /* PME status */\n+\n+/* MSI Capability Register for EP */\n+#define PCIE_MCAPR(X)                    (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x50)\n+\n+#define PCIE_MCAPR_MSI_CAP_ID             0x000000FF  /* MSI Capability ID */\n+#define PCIE_MCAPR_MSI_CAP_ID_S           0\n+#define PCIE_MCAPR_MSI_NEXT_CAP_PTR       0x0000FF00  /* Next Capability Pointer */\n+#define PCIE_MCAPR_MSI_NEXT_CAP_PTR_S     8\n+#define PCIE_MCAPR_MSI_ENABLE             0x00010000  /* MSI Enable */\n+#define PCIE_MCAPR_MULTI_MSG_CAP          0x000E0000  /* Multiple Message Capable */\n+#define PCIE_MCAPR_MULTI_MSG_CAP_S        17\n+#define PCIE_MCAPR_MULTI_MSG_ENABLE       0x00700000  /* Multiple Message Enable */\n+#define PCIE_MCAPR_MULTI_MSG_ENABLE_S     20\n+#define PCIE_MCAPR_ADDR64_CAP             0X00800000  /* 64-bit Address Capable */\n+\n+/* MSI Message Address Register */\n+#define PCIE_MA(X)                       (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x54)\n+\n+#define PCIE_MA_ADDR_MASK                 0xFFFFFFFC  /* Message Address */\n+\n+/* MSI Message Upper Address Register */\n+#define PCIE_MUA(X)                      (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x58)\n+\n+/* MSI Message Data Register */\n+#define PCIE_MD(X)                       (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x5C)\n+\n+#define PCIE_MD_DATA                      0x0000FFFF  /* Message Data */\n+#define PCIE_MD_DATA_S                    0\n+\n+/* PCI Express Capability Register */\n+#define PCIE_XCAP(X)                     (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x70)\n+\n+#define PCIE_XCAP_ID                      0x000000FF  /* PCI Express Capability ID */\n+#define PCIE_XCAP_ID_S                    0\n+#define PCIE_XCAP_NEXT_CAP                0x0000FF00  /* Next Capability Pointer */\n+#define PCIE_XCAP_NEXT_CAP_S              8\n+#define PCIE_XCAP_VER                     0x000F0000  /* PCI Express Capability Version */\n+#define PCIE_XCAP_VER_S                   16\n+#define PCIE_XCAP_DEV_PORT_TYPE           0x00F00000  /* Device Port Type */\n+#define PCIE_XCAP_DEV_PORT_TYPE_S         20\n+#define PCIE_XCAP_SLOT_IMPLEMENTED        0x01000000  /* Slot Implemented */\n+#define PCIE_XCAP_MSG_INT_NUM             0x3E000000  /* Interrupt Message Number */\n+#define PCIE_XCAP_MSG_INT_NUM_S           25\n+\n+/* Device Capability Register */\n+#define PCIE_DCAP(X)                     (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x74)\n+\n+#define PCIE_DCAP_MAX_PAYLOAD_SIZE        0x00000007   /* Max Payload size */\n+#define PCIE_DCAP_MAX_PAYLOAD_SIZE_S      0\n+#define PCIE_DCAP_PHANTOM_FUNC            0x00000018   /* Phanton Function, not supported */\n+#define PCIE_DCAP_PHANTOM_FUNC_S          3\n+#define PCIE_DCAP_EXT_TAG                 0x00000020   /* Extended Tag Field */\n+#define PCIE_DCAP_EP_L0S_LATENCY          0x000001C0   /* EP L0s latency only */\n+#define PCIE_DCAP_EP_L0S_LATENCY_S        6\n+#define PCIE_DCAP_EP_L1_LATENCY           0x00000E00   /* EP L1 latency only */\n+#define PCIE_DCAP_EP_L1_LATENCY_S         9\n+#define PCIE_DCAP_ROLE_BASE_ERR_REPORT    0x00008000   /* Role Based ERR */\n+\n+/* Maximum payload size supported */\n+enum {\n+    PCIE_MAX_PAYLOAD_128 = 0,\n+    PCIE_MAX_PAYLOAD_256,\n+    PCIE_MAX_PAYLOAD_512,\n+    PCIE_MAX_PAYLOAD_1024,\n+    PCIE_MAX_PAYLOAD_2048,\n+    PCIE_MAX_PAYLOAD_4096,\n+};\n+\n+/* Device Control and Status Register */\n+#define PCIE_DCTLSTS(X)                       (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x78)\n+\n+#define PCIE_DCTLSTS_CORRECTABLE_ERR_EN        0x00000001   /* COR-ERR */\n+#define PCIE_DCTLSTS_NONFATAL_ERR_EN           0x00000002   /* Non-fatal ERR */\n+#define PCIE_DCTLSTS_FATAL_ERR_EN              0x00000004   /* Fatal ERR */\n+#define PCIE_DCTLSYS_UR_REQ_EN                 0x00000008   /* UR ERR */\n+#define PCIE_DCTLSTS_RELAXED_ORDERING_EN       0x00000010   /* Enable relaxing ordering */\n+#define PCIE_DCTLSTS_MAX_PAYLOAD_SIZE          0x000000E0   /* Max payload mask */\n+#define PCIE_DCTLSTS_MAX_PAYLOAD_SIZE_S        5\n+#define PCIE_DCTLSTS_EXT_TAG_EN                0x00000100   /* Extended tag field */\n+#define PCIE_DCTLSTS_PHANTOM_FUNC_EN           0x00000200   /* Phantom Function Enable */\n+#define PCIE_DCTLSTS_AUX_PM_EN                 0x00000400   /* AUX Power PM Enable */\n+#define PCIE_DCTLSTS_NO_SNOOP_EN               0x00000800   /* Enable no snoop, except root port*/\n+#define PCIE_DCTLSTS_MAX_READ_SIZE             0x00007000   /* Max Read Request size*/\n+#define PCIE_DCTLSTS_MAX_READ_SIZE_S           12\n+#define PCIE_DCTLSTS_CORRECTABLE_ERR           0x00010000   /* COR-ERR Detected */\n+#define PCIE_DCTLSTS_NONFATAL_ERR              0x00020000   /* Non-Fatal ERR Detected */\n+#define PCIE_DCTLSTS_FATAL_ER                  0x00040000   /* Fatal ERR Detected */\n+#define PCIE_DCTLSTS_UNSUPPORTED_REQ           0x00080000   /* UR Detected */\n+#define PCIE_DCTLSTS_AUX_POWER                 0x00100000   /* Aux Power Detected */\n+#define PCIE_DCTLSTS_TRANSACT_PENDING          0x00200000   /* Transaction pending */\n+\n+#define PCIE_DCTLSTS_ERR_EN      (PCIE_DCTLSTS_CORRECTABLE_ERR_EN | \\\n+                                  PCIE_DCTLSTS_NONFATAL_ERR_EN | PCIE_DCTLSTS_FATAL_ERR_EN | \\\n+                                  PCIE_DCTLSYS_UR_REQ_EN)\n+\n+/* Link Capability Register */\n+#define PCIE_LCAP(X)                          (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7C)\n+#define PCIE_LCAP_MAX_LINK_SPEED               0x0000000F  /* Max link speed, 0x1 by default */\n+#define PCIE_LCAP_MAX_LINK_SPEED_S             0\n+#define PCIE_LCAP_MAX_LENGTH_WIDTH             0x000003F0  /* Maxium Length Width */\n+#define PCIE_LCAP_MAX_LENGTH_WIDTH_S           4\n+#define PCIE_LCAP_ASPM_LEVEL                   0x00000C00  /* Active State Link PM Support */\n+#define PCIE_LCAP_ASPM_LEVEL_S                 10\n+#define PCIE_LCAP_L0S_EIXT_LATENCY             0x00007000  /* L0s Exit Latency */\n+#define PCIE_LCAP_L0S_EIXT_LATENCY_S           12\n+#define PCIE_LCAP_L1_EXIT_LATENCY              0x00038000  /* L1 Exit Latency */\n+#define PCIE_LCAP_L1_EXIT_LATENCY_S            15\n+#define PCIE_LCAP_CLK_PM                       0x00040000  /* Clock Power Management */\n+#define PCIE_LCAP_SDER                         0x00080000  /* Surprise Down Error Reporting */\n+#define PCIE_LCAP_DLL_ACTIVE_REPROT            0x00100000  /* Data Link Layer Active Reporting Capable */\n+#define PCIE_LCAP_PORT_NUM                     0xFF0000000  /* Port number */\n+#define PCIE_LCAP_PORT_NUM_S                   24\n+\n+/* Maximum Length width definition */\n+#define PCIE_MAX_LENGTH_WIDTH_RES  0x00\n+#define PCIE_MAX_LENGTH_WIDTH_X1   0x01  /* Default */\n+#define PCIE_MAX_LENGTH_WIDTH_X2   0x02\n+#define PCIE_MAX_LENGTH_WIDTH_X4   0x04\n+#define PCIE_MAX_LENGTH_WIDTH_X8   0x08\n+#define PCIE_MAX_LENGTH_WIDTH_X12  0x0C\n+#define PCIE_MAX_LENGTH_WIDTH_X16  0x10\n+#define PCIE_MAX_LENGTH_WIDTH_X32  0x20\n+\n+/* Active State Link PM definition */\n+enum {\n+    PCIE_ASPM_RES0                = 0,\n+    PCIE_ASPM_L0S_ENTRY_SUPPORT,        /* L0s */\n+    PCIE_ASPM_RES1,\n+    PCIE_ASPM_L0S_L1_ENTRY_SUPPORT,     /* L0s and L1, default */\n+};\n+\n+/* L0s Exit Latency definition */\n+enum {\n+    PCIE_L0S_EIXT_LATENCY_L64NS    = 0, /* < 64 ns */\n+    PCIE_L0S_EIXT_LATENCY_B64A128,      /* > 64 ns < 128 ns */\n+    PCIE_L0S_EIXT_LATENCY_B128A256,     /* > 128 ns < 256 ns */\n+    PCIE_L0S_EIXT_LATENCY_B256A512,     /* > 256 ns < 512 ns */\n+    PCIE_L0S_EIXT_LATENCY_B512TO1U,     /* > 512 ns < 1 us */\n+    PCIE_L0S_EIXT_LATENCY_B1A2U,        /* > 1 us < 2 us */\n+    PCIE_L0S_EIXT_LATENCY_B2A4U,        /* > 2 us < 4 us */\n+    PCIE_L0S_EIXT_LATENCY_M4US,         /* > 4 us  */\n+};\n+\n+/* L1 Exit Latency definition */\n+enum {\n+    PCIE_L1_EXIT_LATENCY_L1US  = 0,  /* < 1 us */\n+    PCIE_L1_EXIT_LATENCY_B1A2,       /* > 1 us < 2 us */\n+    PCIE_L1_EXIT_LATENCY_B2A4,       /* > 2 us < 4 us */\n+    PCIE_L1_EXIT_LATENCY_B4A8,       /* > 4 us < 8 us */\n+    PCIE_L1_EXIT_LATENCY_B8A16,      /* > 8 us < 16 us */\n+    PCIE_L1_EXIT_LATENCY_B16A32,     /* > 16 us < 32 us */\n+    PCIE_L1_EXIT_LATENCY_B32A64,     /* > 32 us < 64 us */\n+    PCIE_L1_EXIT_LATENCY_M64US,      /* > 64 us */\n+};\n+\n+/* Link Control and Status Register */\n+#define PCIE_LCTLSTS(X)                     (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x80)\n+#define PCIE_LCTLSTS_ASPM_ENABLE            0x00000003  /* Active State Link PM Control */\n+#define PCIE_LCTLSTS_ASPM_ENABLE_S          0\n+#define PCIE_LCTLSTS_RCB128                 0x00000008  /* Read Completion Boundary 128*/\n+#define PCIE_LCTLSTS_LINK_DISABLE           0x00000010  /* Link Disable */\n+#define PCIE_LCTLSTS_RETRIAN_LINK           0x00000020  /* Retrain Link */\n+#define PCIE_LCTLSTS_COM_CLK_CFG            0x00000040  /* Common Clock Configuration */\n+#define PCIE_LCTLSTS_EXT_SYNC               0x00000080  /* Extended Synch */\n+#define PCIE_LCTLSTS_CLK_PM_EN              0x00000100  /* Enable Clock Powerm Management */\n+#define PCIE_LCTLSTS_LINK_SPEED             0x000F0000  /* Link Speed */\n+#define PCIE_LCTLSTS_LINK_SPEED_S           16\n+#define PCIE_LCTLSTS_NEGOTIATED_LINK_WIDTH  0x03F00000  /* Negotiated Link Width */\n+#define PCIE_LCTLSTS_NEGOTIATED_LINK_WIDTH_S 20\n+#define PCIE_LCTLSTS_RETRAIN_PENDING        0x08000000  /* Link training is ongoing */\n+#define PCIE_LCTLSTS_SLOT_CLK_CFG           0x10000000  /* Slot Clock Configuration */\n+#define PCIE_LCTLSTS_DLL_ACTIVE             0x20000000  /* Data Link Layer Active */\n+\n+/* Slot Capabilities Register */\n+#define PCIE_SLCAP(X)                       (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x84)\n+\n+/* Slot Capabilities */\n+#define PCIE_SLCTLSTS(X)                    (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x88)\n+\n+/* Root Control and Capability Register */\n+#define PCIE_RCTLCAP(X)                     (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x8C)\n+#define PCIE_RCTLCAP_SERR_ON_CORRECTABLE_ERR  0x00000001   /* #SERR on COR-ERR */\n+#define PCIE_RCTLCAP_SERR_ON_NONFATAL_ERR     0x00000002   /* #SERR on Non-Fatal ERR */\n+#define PCIE_RCTLCAP_SERR_ON_FATAL_ERR        0x00000004   /* #SERR on Fatal ERR */\n+#define PCIE_RCTLCAP_PME_INT_EN               0x00000008   /* PME Interrupt Enable */\n+#define PCIE_RCTLCAP_SERR_ENABLE    (PCIE_RCTLCAP_SERR_ON_CORRECTABLE_ERR | \\\n+                                     PCIE_RCTLCAP_SERR_ON_NONFATAL_ERR | PCIE_RCTLCAP_SERR_ON_FATAL_ERR)\n+/* Root Status Register */\n+#define PCIE_RSTS(X)                          (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x90)\n+#define PCIE_RSTS_PME_REQ_ID                   0x0000FFFF   /* PME Request ID */\n+#define PCIE_RSTS_PME_REQ_ID_S                 0\n+#define PCIE_RSTS_PME_STATUS                   0x00010000   /* PME Status */\n+#define PCIE_RSTS_PME_PENDING                  0x00020000   /* PME Pending */\n+\n+/* PCI Express Enhanced Capability Header */\n+#define PCIE_ENHANCED_CAP(X)                (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x100)\n+#define PCIE_ENHANCED_CAP_ID                 0x0000FFFF  /* PCI Express Extended Capability ID */\n+#define PCIE_ENHANCED_CAP_ID_S               0\n+#define PCIE_ENHANCED_CAP_VER                0x000F0000  /* Capability Version */\n+#define PCIE_ENHANCED_CAP_VER_S              16\n+#define PCIE_ENHANCED_CAP_NEXT_OFFSET        0xFFF00000  /* Next Capability Offset */\n+#define PCIE_ENHANCED_CAP_NEXT_OFFSET_S      20\n+\n+/* Uncorrectable Error Status Register */\n+#define PCIE_UES_R(X)                       (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x104)\n+#define PCIE_DATA_LINK_PROTOCOL_ERR          0x00000010  /* Data Link Protocol Error Status */\n+#define PCIE_SURPRISE_DOWN_ERROR             0x00000020  /* Surprise Down Error Status */\n+#define PCIE_POISONED_TLP                    0x00001000  /* Poisoned TLP Status */\n+#define PCIE_FC_PROTOCOL_ERR                 0x00002000  /* Flow Control Protocol Error Status */\n+#define PCIE_COMPLETION_TIMEOUT              0x00004000  /* Completion Timeout Status */\n+#define PCIE_COMPLETOR_ABORT                 0x00008000  /* Completer Abort Error */\n+#define PCIE_UNEXPECTED_COMPLETION           0x00010000  /* Unexpected Completion Status */\n+#define PCIE_RECEIVER_OVERFLOW               0x00020000  /* Receive Overflow Status */\n+#define PCIE_MALFORNED_TLP                   0x00040000  /* Malformed TLP Stauts */\n+#define PCIE_ECRC_ERR                        0x00080000  /* ECRC Error Stauts */\n+#define PCIE_UR_REQ                          0x00100000  /* Unsupported Request Error Status */\n+#define PCIE_ALL_UNCORRECTABLE_ERR    (PCIE_DATA_LINK_PROTOCOL_ERR | PCIE_SURPRISE_DOWN_ERROR | \\\n+                         PCIE_POISONED_TLP | PCIE_FC_PROTOCOL_ERR | PCIE_COMPLETION_TIMEOUT |   \\\n+                         PCIE_COMPLETOR_ABORT | PCIE_UNEXPECTED_COMPLETION | PCIE_RECEIVER_OVERFLOW |\\\n+                         PCIE_MALFORNED_TLP | PCIE_ECRC_ERR | PCIE_UR_REQ)\n+\n+/* Uncorrectable Error Mask Register, Mask means no report */\n+#define PCIE_UEMR(X)                        (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x108)\n+\n+/* Uncorrectable Error Severity Register */\n+#define PCIE_UESR(X)                        (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x10C)\n+\n+/* Correctable Error Status Register */\n+#define PCIE_CESR(X)                        (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x110)\n+#define PCIE_RX_ERR                          0x00000001  /* Receive Error Status */\n+#define PCIE_BAD_TLP                         0x00000040  /* Bad TLP Status */\n+#define PCIE_BAD_DLLP                        0x00000080  /* Bad DLLP Status */\n+#define PCIE_REPLAY_NUM_ROLLOVER             0x00000100  /* Replay Number Rollover Status */\n+#define PCIE_REPLAY_TIMER_TIMEOUT_ERR        0x00001000  /* Reply Timer Timeout Status */\n+#define PCIE_ADVISORY_NONFTAL_ERR            0x00002000  /* Advisory Non-Fatal Error Status */\n+#define PCIE_CORRECTABLE_ERR        (PCIE_RX_ERR | PCIE_BAD_TLP | PCIE_BAD_DLLP | PCIE_REPLAY_NUM_ROLLOVER |\\\n+                                     PCIE_REPLAY_TIMER_TIMEOUT_ERR | PCIE_ADVISORY_NONFTAL_ERR)\n+\n+/* Correctable Error Mask Register */\n+#define PCIE_CEMR(X)                        (volatile u32*)(PCIE_RC_CFG_BASE + 0x114)\n+\n+/* Advanced Error Capabilities and Control Register */\n+#define PCIE_AECCR(X)                       (volatile u32*)(PCIE_RC_CFG_BASE + 0x118)\n+#define PCIE_AECCR_FIRST_ERR_PTR            0x0000001F  /* First Error Pointer */\n+#define PCIE_AECCR_FIRST_ERR_PTR_S          0\n+#define PCIE_AECCR_ECRC_GEN_CAP             0x00000020  /* ECRC Generation Capable */\n+#define PCIE_AECCR_ECRC_GEN_EN              0x00000040  /* ECRC Generation Enable */\n+#define PCIE_AECCR_ECRC_CHECK_CAP           0x00000080  /* ECRC Check Capable */\n+#define PCIE_AECCR_ECRC_CHECK_EN            0x00000100  /* ECRC Check Enable */\n+\n+/* Header Log Register 1 */\n+#define PCIE_HLR1(X)                        (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x11C)\n+\n+/* Header Log Register 2 */\n+#define PCIE_HLR2(X)                        (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x120)\n+\n+/* Header Log Register 3 */\n+#define PCIE_HLR3(X)                        (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x124)\n+\n+/* Header Log Register 4 */\n+#define PCIE_HLR4(X)                        (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x128)\n+\n+/* Root Error Command Register */\n+#define PCIE_RECR(X)                        (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x12C)\n+#define PCIE_RECR_CORRECTABLE_ERR_REPORT_EN  0x00000001 /* COR-ERR */\n+#define PCIE_RECR_NONFATAL_ERR_REPORT_EN     0x00000002 /* Non-Fatal ERR */\n+#define PCIE_RECR_FATAL_ERR_REPORT_EN        0x00000004 /* Fatal ERR */\n+#define PCIE_RECR_ERR_REPORT_EN  (PCIE_RECR_CORRECTABLE_ERR_REPORT_EN | \\\n+                PCIE_RECR_NONFATAL_ERR_REPORT_EN | PCIE_RECR_FATAL_ERR_REPORT_EN)\n+\n+/* Root Error Status Register */\n+#define PCIE_RESR(X)                            (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x130)\n+#define PCIE_RESR_CORRECTABLE_ERR                0x00000001   /* COR-ERR Receveid */\n+#define PCIE_RESR_MULTI_CORRECTABLE_ERR          0x00000002   /* Multiple COR-ERR Received */\n+#define PCIE_RESR_FATAL_NOFATAL_ERR              0x00000004   /* ERR Fatal/Non-Fatal Received */\n+#define PCIE_RESR_MULTI_FATAL_NOFATAL_ERR        0x00000008   /* Multiple ERR Fatal/Non-Fatal Received */\n+#define PCIE_RESR_FIRST_UNCORRECTABLE_FATAL_ERR  0x00000010   /* First UN-COR Fatal */\n+#define PCIR_RESR_NON_FATAL_ERR                  0x00000020   /* Non-Fatal Error Message Received */\n+#define PCIE_RESR_FATAL_ERR                      0x00000040   /* Fatal Message Received */\n+#define PCIE_RESR_AER_INT_MSG_NUM                0xF8000000   /* Advanced Error Interrupt Message Number */\n+#define PCIE_RESR_AER_INT_MSG_NUM_S              27\n+\n+/* Error Source Indentification Register */\n+#define PCIE_ESIR(X)                            (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x134)\n+#define PCIE_ESIR_CORRECTABLE_ERR_SRC_ID         0x0000FFFF\n+#define PCIE_ESIR_CORRECTABLE_ERR_SRC_ID_S       0\n+#define PCIE_ESIR_FATAL_NON_FATAL_SRC_ID         0xFFFF0000\n+#define PCIE_ESIR_FATAL_NON_FATAL_SRC_ID_S       16\n+\n+/* VC Enhanced Capability Header */\n+#define PCIE_VC_ECH(X)                          (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x140)\n+\n+/* Port VC Capability Register */\n+#define PCIE_PVC1(X)                            (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x144)\n+#define PCIE_PVC1_EXT_VC_CNT                    0x00000007  /* Extended VC Count */\n+#define PCIE_PVC1_EXT_VC_CNT_S                  0\n+#define PCIE_PVC1_LOW_PRI_EXT_VC_CNT            0x00000070  /* Low Priority Extended VC Count */\n+#define PCIE_PVC1_LOW_PRI_EXT_VC_CNT_S          4\n+#define PCIE_PVC1_REF_CLK                       0x00000300  /* Reference Clock */\n+#define PCIE_PVC1_REF_CLK_S                     8\n+#define PCIE_PVC1_PORT_ARB_TAB_ENTRY_SIZE       0x00000C00  /* Port Arbitration Table Entry Size */\n+#define PCIE_PVC1_PORT_ARB_TAB_ENTRY_SIZE_S     10\n+\n+/* Extended Virtual Channel Count Defintion */\n+#define PCIE_EXT_VC_CNT_MIN   0\n+#define PCIE_EXT_VC_CNT_MAX   7\n+\n+/* Port Arbitration Table Entry Size Definition */\n+enum {\n+    PCIE_PORT_ARB_TAB_ENTRY_SIZE_S1BIT = 0,\n+    PCIE_PORT_ARB_TAB_ENTRY_SIZE_S2BIT,\n+    PCIE_PORT_ARB_TAB_ENTRY_SIZE_S4BIT,\n+    PCIE_PORT_ARB_TAB_ENTRY_SIZE_S8BIT,\n+};\n+\n+/* Port VC Capability Register 2 */\n+#define PCIE_PVC2(X)                        (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x148)\n+#define PCIE_PVC2_VC_ARB_16P_FIXED_WRR      0x00000001  /* HW Fixed arbitration, 16 phase WRR */\n+#define PCIE_PVC2_VC_ARB_32P_WRR            0x00000002  /* 32 phase WRR */\n+#define PCIE_PVC2_VC_ARB_64P_WRR            0x00000004  /* 64 phase WRR */\n+#define PCIE_PVC2_VC_ARB_128P_WRR           0x00000008  /* 128 phase WRR */\n+#define PCIE_PVC2_VC_ARB_WRR                0x0000000F\n+#define PCIE_PVC2_VC_ARB_TAB_OFFSET         0xFF000000  /* VC arbitration table offset, not support */\n+#define PCIE_PVC2_VC_ARB_TAB_OFFSET_S       24\n+\n+/* Port VC Control and Status Register */     \n+#define PCIE_PVCCRSR(X)                     (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x14C)\n+#define PCIE_PVCCRSR_LOAD_VC_ARB_TAB         0x00000001  /* Load VC Arbitration Table */\n+#define PCIE_PVCCRSR_VC_ARB_SEL              0x0000000E  /* VC Arbitration Select */\n+#define PCIE_PVCCRSR_VC_ARB_SEL_S            1\n+#define PCIE_PVCCRSR_VC_ARB_TAB_STATUS       0x00010000  /* Arbitration Status */\n+\n+/* VC0 Resource Capability Register */\n+#define PCIE_VC0_RC(X)                       (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x150)\n+#define PCIE_VC0_RC_PORT_ARB_HW_FIXED        0x00000001  /* HW Fixed arbitration */\n+#define PCIE_VC0_RC_PORT_ARB_32P_WRR         0x00000002  /* 32 phase WRR */\n+#define PCIE_VC0_RC_PORT_ARB_64P_WRR         0x00000004  /* 64 phase WRR */\n+#define PCIE_VC0_RC_PORT_ARB_128P_WRR        0x00000008  /* 128 phase WRR */\n+#define PCIE_VC0_RC_PORT_ARB_TM_128P_WRR     0x00000010  /* Time-based 128 phase WRR */\n+#define PCIE_VC0_RC_PORT_ARB_TM_256P_WRR     0x00000020  /* Time-based 256 phase WRR */\n+#define PCIE_VC0_RC_PORT_ARB          (PCIE_VC0_RC_PORT_ARB_HW_FIXED | PCIE_VC0_RC_PORT_ARB_32P_WRR |\\\n+                        PCIE_VC0_RC_PORT_ARB_64P_WRR | PCIE_VC0_RC_PORT_ARB_128P_WRR | \\\n+                        PCIE_VC0_RC_PORT_ARB_TM_128P_WRR | PCIE_VC0_RC_PORT_ARB_TM_256P_WRR)\n+\n+#define PCIE_VC0_RC_REJECT_SNOOP             0x00008000  /* Reject Snoop Transactioin */\n+#define PCIE_VC0_RC_MAX_TIMESLOTS            0x007F0000  /* Maximum time Slots */\n+#define PCIE_VC0_RC_MAX_TIMESLOTS_S          16\n+#define PCIE_VC0_RC_PORT_ARB_TAB_OFFSET      0xFF000000  /* Port Arbitration Table Offset */\n+#define PCIE_VC0_RC_PORT_ARB_TAB_OFFSET_S    24\n+\n+/* VC0 Resource Control Register */\n+#define PCIE_VC0_RC0(X)                      (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x154)\n+#define PCIE_VC0_RC0_TVM0                    0x00000001  /* TC0 and VC0 */\n+#define PCIE_VC0_RC0_TVM1                    0x00000002  /* TC1 and VC1 */\n+#define PCIE_VC0_RC0_TVM2                    0x00000004  /* TC2 and VC2 */\n+#define PCIE_VC0_RC0_TVM3                    0x00000008  /* TC3 and VC3 */\n+#define PCIE_VC0_RC0_TVM4                    0x00000010  /* TC4 and VC4 */\n+#define PCIE_VC0_RC0_TVM5                    0x00000020  /* TC5 and VC5 */\n+#define PCIE_VC0_RC0_TVM6                    0x00000040  /* TC6 and VC6 */\n+#define PCIE_VC0_RC0_TVM7                    0x00000080  /* TC7 and VC7 */\n+#define PCIE_VC0_RC0_TC_VC                   0x000000FF  /* TC/VC mask */\n+\n+#define PCIE_VC0_RC0_LOAD_PORT_ARB_TAB       0x00010000  /* Load Port Arbitration Table */\n+#define PCIE_VC0_RC0_PORT_ARB_SEL            0x000E0000  /* Port Arbitration Select */\n+#define PCIE_VC0_RC0_PORT_ARB_SEL_S          17\n+#define PCIE_VC0_RC0_VC_ID                   0x07000000  /* VC ID */\n+#define PCIE_VC0_RC0_VC_ID_S                 24\n+#define PCIE_VC0_RC0_VC_EN                   0x80000000  /* VC Enable */\n+\n+/* VC0 Resource Status Register */\n+#define PCIE_VC0_RSR0(X)                     (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x158)\n+#define PCIE_VC0_RSR0_PORT_ARB_TAB_STATUS    0x00010000  /* Port Arbitration Table Status,not used */\n+#define PCIE_VC0_RSR0_VC_NEG_PENDING         0x00020000  /* VC Negotiation Pending */\n+\n+/* Ack Latency Timer and Replay Timer Register */\n+#define PCIE_ALTRT(X)                         (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x700)\n+#define PCIE_ALTRT_ROUND_TRIP_LATENCY_LIMIT   0x0000FFFF  /* Round Trip Latency Time Limit */\n+#define PCIE_ALTRT_ROUND_TRIP_LATENCY_LIMIT_S 0\n+#define PCIE_ALTRT_REPLAY_TIME_LIMIT          0xFFFF0000  /* Replay Time Limit */\n+#define PCIE_ALTRT_REPLAY_TIME_LIMIT_S        16\n+\n+/* Other Message Register */\n+#define PCIE_OMR(X)                          (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x704)\n+\n+/* Port Force Link Register */\n+#define PCIE_PFLR(X)                         (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x708)\n+#define PCIE_PFLR_LINK_NUM                   0x000000FF  /* Link Number */\n+#define PCIE_PFLR_LINK_NUM_S                 0\n+#define PCIE_PFLR_FORCE_LINK                 0x00008000  /* Force link */\n+#define PCIE_PFLR_LINK_STATE                 0x003F0000  /* Link State */\n+#define PCIE_PFLR_LINK_STATE_S               16\n+#define PCIE_PFLR_LOW_POWER_ENTRY_CNT        0xFF000000  /* Low Power Entrance Count, only for EP */\n+#define PCIE_PFLR_LOW_POWER_ENTRY_CNT_S      24\n+\n+/* Ack Frequency Register */\n+#define PCIE_AFR(X)                          (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x70C)\n+#define PCIE_AFR_AF                          0x000000FF  /* Ack Frequency */\n+#define PCIE_AFR_AF_S                        0\n+#define PCIE_AFR_FTS_NUM                     0x0000FF00  /* The number of Fast Training Sequence from L0S to L0 */\n+#define PCIE_AFR_FTS_NUM_S                   8\n+#define PCIE_AFR_COM_FTS_NUM                 0x00FF0000  /* N_FTS; when common clock is used*/\n+#define PCIE_AFR_COM_FTS_NUM_S               16\n+#define PCIE_AFR_L0S_ENTRY_LATENCY           0x07000000  /* L0s Entrance Latency */\n+#define PCIE_AFR_L0S_ENTRY_LATENCY_S         24\n+#define PCIE_AFR_L1_ENTRY_LATENCY            0x38000000  /* L1 Entrance Latency */\n+#define PCIE_AFR_L1_ENTRY_LATENCY_S          27\n+#define PCIE_AFR_FTS_NUM_DEFAULT             32\n+#define PCIE_AFR_L0S_ENTRY_LATENCY_DEFAULT   7\n+#define PCIE_AFR_L1_ENTRY_LATENCY_DEFAULT    5\n+\n+/* Port Link Control Register */\n+#define PCIE_PLCR(X)                         (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x710)\n+#define PCIE_PLCR_OTHER_MSG_REQ              0x00000001  /* Other Message Request */\n+#define PCIE_PLCR_SCRAMBLE_DISABLE           0x00000002  /* Scramble Disable */  \n+#define PCIE_PLCR_LOOPBACK_EN                0x00000004  /* Loopback Enable */\n+#define PCIE_PLCR_LTSSM_HOT_RST              0x00000008  /* Force LTSSM to the hot reset */\n+#define PCIE_PLCR_DLL_LINK_EN                0x00000020  /* Enable Link initialization */\n+#define PCIE_PLCR_FAST_LINK_SIM_EN           0x00000080  /* Sets all internal timers to fast mode for simulation purposes */\n+#define PCIE_PLCR_LINK_MODE                  0x003F0000  /* Link Mode Enable Mask */\n+#define PCIE_PLCR_LINK_MODE_S                16\n+#define PCIE_PLCR_CORRUPTED_CRC_EN           0x02000000  /* Enabled Corrupt CRC */\n+\n+/* Lane Skew Register */\n+#define PCIE_LSR(X)                          (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x714)\n+#define PCIE_LSR_LANE_SKEW_NUM               0x00FFFFFF  /* Insert Lane Skew for Transmit, not applicable */\n+#define PCIE_LSR_LANE_SKEW_NUM_S             0\n+#define PCIE_LSR_FC_DISABLE                  0x01000000  /* Disable of Flow Control */\n+#define PCIE_LSR_ACKNAK_DISABLE              0x02000000  /* Disable of Ack/Nak */\n+#define PCIE_LSR_LANE_DESKEW_DISABLE         0x80000000  /* Disable of Lane-to-Lane Skew */\n+\n+/* Symbol Number Register */\n+#define PCIE_SNR(X)                          (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x718)\n+#define PCIE_SNR_TS                          0x0000000F  /* Number of TS Symbol */\n+#define PCIE_SNR_TS_S                        0\n+#define PCIE_SNR_SKP                         0x00000700  /* Number of SKP Symbol */\n+#define PCIE_SNR_SKP_S                       8\n+#define PCIE_SNR_REPLAY_TIMER                0x0007C000  /* Timer Modifier for Replay Timer */\n+#define PCIE_SNR_REPLAY_TIMER_S              14\n+#define PCIE_SNR_ACKNAK_LATENCY_TIMER        0x00F80000  /* Timer Modifier for Ack/Nak Latency Timer */\n+#define PCIE_SNR_ACKNAK_LATENCY_TIMER_S      19\n+#define PCIE_SNR_FC_TIMER                    0x1F000000  /* Timer Modifier for Flow Control Watchdog Timer */\n+#define PCIE_SNR_FC_TIMER_S                  28\n+\n+/* Symbol Timer Register and Filter Mask Register 1 */\n+#define PCIE_STRFMR(X)                      (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x71C)\n+#define PCIE_STRFMR_SKP_INTERVAL            0x000007FF  /* SKP lnterval Value */\n+#define PCIE_STRFMR_SKP_INTERVAL_S          0\n+#define PCIE_STRFMR_FC_WDT_DISABLE          0x00008000  /* Disable of FC Watchdog Timer */\n+#define PCIE_STRFMR_TLP_FUNC_MISMATCH_OK    0x00010000  /* Mask Function Mismatch Filtering for Incoming Requests */\n+#define PCIE_STRFMR_POISONED_TLP_OK         0x00020000  /* Mask Poisoned TLP Filtering */\n+#define PCIE_STRFMR_BAR_MATCH_OK            0x00040000  /* Mask BAR Match Filtering */\n+#define PCIE_STRFMR_TYPE1_CFG_REQ_OK        0x00080000  /* Mask Type 1 Configuration Request Filtering */\n+#define PCIE_STRFMR_LOCKED_REQ_OK           0x00100000  /* Mask Locked Request Filtering */\n+#define PCIE_STRFMR_CPL_TAG_ERR_RULES_OK    0x00200000  /* Mask Tag Error Rules for Received Completions */\n+#define PCIE_STRFMR_CPL_REQUESTOR_ID_MISMATCH_OK 0x00400000  /* Mask Requester ID Mismatch Error for Received Completions */\n+#define PCIE_STRFMR_CPL_FUNC_MISMATCH_OK         0x00800000  /* Mask Function Mismatch Error for Received Completions */\n+#define PCIE_STRFMR_CPL_TC_MISMATCH_OK           0x01000000  /* Mask Traffic Class Mismatch Error for Received Completions */\n+#define PCIE_STRFMR_CPL_ATTR_MISMATCH_OK         0x02000000  /* Mask Attribute Mismatch Error for Received Completions */\n+#define PCIE_STRFMR_CPL_LENGTH_MISMATCH_OK       0x04000000  /* Mask Length Mismatch Error for Received Completions */\n+#define PCIE_STRFMR_TLP_ECRC_ERR_OK              0x08000000  /* Mask ECRC Error Filtering */\n+#define PCIE_STRFMR_CPL_TLP_ECRC_OK              0x10000000  /* Mask ECRC Error Filtering for Completions */\n+#define PCIE_STRFMR_RX_TLP_MSG_NO_DROP           0x20000000  /* Send Message TLPs */\n+#define PCIE_STRFMR_RX_IO_TRANS_ENABLE           0x40000000  /* Mask Filtering of received I/O Requests */\n+#define PCIE_STRFMR_RX_CFG_TRANS_ENABLE          0x80000000  /* Mask Filtering of Received Configuration Requests */\n+\n+#define PCIE_DEF_SKP_INTERVAL    700             /* 1180 ~1538 , 125MHz * 2, 250MHz * 1 */\n+\n+/* Filter Masker Register 2 */\n+#define PCIE_FMR2(X)                             (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x720)\n+#define PCIE_FMR2_VENDOR_MSG0_PASSED_TO_TRGT1    0x00000001  /* Mask RADM Filtering and Error Handling Rules */\n+#define PCIE_FMR2_VENDOR_MSG1_PASSED_TO_TRGT1    0x00000002  /* Mask RADM Filtering and Error Handling Rules */\n+\n+/* Debug Register 0 */\n+#define PCIE_DBR0(X)                              (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x728)\n+\n+/* Debug Register 1 */\n+#define PCIE_DBR1(X)                              (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x72C)\n+\n+/* Transmit Posted FC Credit Status Register */\n+#define PCIE_TPFCS(X)                             (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x730)\n+#define PCIE_TPFCS_TX_P_DATA_FC_CREDITS           0x00000FFF /* Transmit Posted Data FC Credits */\n+#define PCIE_TPFCS_TX_P_DATA_FC_CREDITS_S         0\n+#define PCIE_TPFCS_TX_P_HDR_FC_CREDITS            0x000FF000 /* Transmit Posted Header FC Credits */\n+#define PCIE_TPFCS_TX_P_HDR_FC_CREDITS_S          12\n+\n+/* Transmit Non-Posted FC Credit Status */\n+#define PCIE_TNPFCS(X)                            (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x734)\n+#define PCIE_TNPFCS_TX_NP_DATA_FC_CREDITS         0x00000FFF /* Transmit Non-Posted Data FC Credits */\n+#define PCIE_TNPFCS_TX_NP_DATA_FC_CREDITS_S       0\n+#define PCIE_TNPFCS_TX_NP_HDR_FC_CREDITS          0x000FF000 /* Transmit Non-Posted Header FC Credits */\n+#define PCIE_TNPFCS_TX_NP_HDR_FC_CREDITS_S        12\n+\n+/* Transmit Complete FC Credit Status Register */\n+#define PCIE_TCFCS(X)                             (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x738)\n+#define PCIE_TCFCS_TX_CPL_DATA_FC_CREDITS         0x00000FFF /* Transmit Completion Data FC Credits */\n+#define PCIE_TCFCS_TX_CPL_DATA_FC_CREDITS_S       0\n+#define PCIE_TCFCS_TX_CPL_HDR_FC_CREDITS          0x000FF000 /* Transmit Completion Header FC Credits */\n+#define PCIE_TCFCS_TX_CPL_HDR_FC_CREDITS_S        12\n+\n+/* Queue Status Register */\n+#define PCIE_QSR(X)                              (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x73C)\n+#define PCIE_QSR_WAIT_UPDATE_FC_DLL               0x00000001 /* Received TLP FC Credits Not Returned */\n+#define PCIE_QSR_TX_RETRY_BUF_NOT_EMPTY           0x00000002 /* Transmit Retry Buffer Not Empty */\n+#define PCIE_QSR_RX_QUEUE_NOT_EMPTY               0x00000004 /* Received Queue Not Empty */\n+\n+/* VC Transmit Arbitration Register 1 */\n+#define PCIE_VCTAR1(X)                          (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x740)\n+#define PCIE_VCTAR1_WRR_WEIGHT_VC0               0x000000FF /* WRR Weight for VC0 */\n+#define PCIE_VCTAR1_WRR_WEIGHT_VC1               0x0000FF00 /* WRR Weight for VC1 */\n+#define PCIE_VCTAR1_WRR_WEIGHT_VC2               0x00FF0000 /* WRR Weight for VC2 */\n+#define PCIE_VCTAR1_WRR_WEIGHT_VC3               0xFF000000 /* WRR Weight for VC3 */\n+\n+/* VC Transmit Arbitration Register 2 */\n+#define PCIE_VCTAR2(X)                          (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x744)\n+#define PCIE_VCTAR2_WRR_WEIGHT_VC4               0x000000FF /* WRR Weight for VC4 */\n+#define PCIE_VCTAR2_WRR_WEIGHT_VC5               0x0000FF00 /* WRR Weight for VC5 */\n+#define PCIE_VCTAR2_WRR_WEIGHT_VC6               0x00FF0000 /* WRR Weight for VC6 */\n+#define PCIE_VCTAR2_WRR_WEIGHT_VC7               0xFF000000 /* WRR Weight for VC7 */\n+\n+/* VC0 Posted Receive Queue Control Register */\n+#define PCIE_VC0_PRQCR(X)                       (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x748)\n+#define PCIE_VC0_PRQCR_P_DATA_CREDITS            0x00000FFF /* VC0 Posted Data Credits */\n+#define PCIE_VC0_PRQCR_P_DATA_CREDITS_S          0\n+#define PCIE_VC0_PRQCR_P_HDR_CREDITS             0x000FF000 /* VC0 Posted Header Credits */\n+#define PCIE_VC0_PRQCR_P_HDR_CREDITS_S           12\n+#define PCIE_VC0_PRQCR_P_TLP_QUEUE_MODE          0x00E00000 /* VC0 Posted TLP Queue Mode */\n+#define PCIE_VC0_PRQCR_P_TLP_QUEUE_MODE_S        20\n+#define PCIE_VC0_PRQCR_TLP_RELAX_ORDER           0x40000000 /* TLP Type Ordering for VC0 */    \n+#define PCIE_VC0_PRQCR_VC_STRICT_ORDER           0x80000000 /* VC0 Ordering for Receive Queues */\n+\n+/* VC0 Non-Posted Receive Queue Control */\n+#define PCIE_VC0_NPRQCR(X)                      (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x74C)\n+#define PCIE_VC0_NPRQCR_NP_DATA_CREDITS          0x00000FFF /* VC0 Non-Posted Data Credits */\n+#define PCIE_VC0_NPRQCR_NP_DATA_CREDITS_S        0\n+#define PCIE_VC0_NPRQCR_NP_HDR_CREDITS           0x000FF000 /* VC0 Non-Posted Header Credits */\n+#define PCIE_VC0_NPRQCR_NP_HDR_CREDITS_S         12\n+#define PCIE_VC0_NPRQCR_NP_TLP_QUEUE_MODE        0x00E00000 /* VC0 Non-Posted TLP Queue Mode */\n+#define PCIE_VC0_NPRQCR_NP_TLP_QUEUE_MODE_S      20\n+\n+/* VC0 Completion Receive Queue Control */\n+#define PCIE_VC0_CRQCR(X)                       (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x750)\n+#define PCIE_VC0_CRQCR_CPL_DATA_CREDITS          0x00000FFF /* VC0 Completion TLP Queue Mode */\n+#define PCIE_VC0_CRQCR_CPL_DATA_CREDITS_S        0\n+#define PCIE_VC0_CRQCR_CPL_HDR_CREDITS           0x000FF000 /* VC0 Completion Header Credits */\n+#define PCIE_VC0_CRQCR_CPL_HDR_CREDITS_S         12\n+#define PCIE_VC0_CRQCR_CPL_TLP_QUEUE_MODE        0x00E00000 /* VC0 Completion Data Credits */\n+#define PCIE_VC0_CRQCR_CPL_TLP_QUEUE_MODE_S      21\n+\n+/* Applicable to the above three registers */\n+enum {\n+    PCIE_VC0_TLP_QUEUE_MODE_STORE_FORWARD = 1,\n+    PCIE_VC0_TLP_QUEUE_MODE_CUT_THROUGH   = 2,\n+    PCIE_VC0_TLP_QUEUE_MODE_BYPASS        = 4,\n+};\n+\n+/* VC0 Posted Buffer Depth Register */\n+#define PCIE_VC0_PBD(X)                        (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7A8)\n+#define PCIE_VC0_PBD_P_DATA_QUEUE_ENTRIES       0x00003FFF /* VC0 Posted Data Queue Depth */\n+#define PCIE_VC0_PBD_P_DATA_QUEUE_ENTRIES_S     0\n+#define PCIE_VC0_PBD_P_HDR_QUEUE_ENTRIES        0x03FF0000 /* VC0 Posted Header Queue Depth */\n+#define PCIE_VC0_PBD_P_HDR_QUEUE_ENTRIES_S      16\n+\n+/* VC0 Non-Posted Buffer Depth Register */\n+#define PCIE_VC0_NPBD(X)                       (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7AC)\n+#define PCIE_VC0_NPBD_NP_DATA_QUEUE_ENTRIES     0x00003FFF /* VC0 Non-Posted Data Queue Depth */\n+#define PCIE_VC0_NPBD_NP_DATA_QUEUE_ENTRIES_S   0\n+#define PCIE_VC0_NPBD_NP_HDR_QUEUE_ENTRIES      0x03FF0000 /* VC0 Non-Posted Header Queue Depth */\n+#define PCIE_VC0_NPBD_NP_HDR_QUEUE_ENTRIES_S    16\n+\n+/* VC0 Completion Buffer Depth Register */\n+#define PCIE_VC0_CBD(X)                        (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7B0)\n+#define PCIE_VC0_CBD_CPL_DATA_QUEUE_ENTRIES     0x00003FFF /* C0 Completion Data Queue Depth */\n+#define PCIE_VC0_CBD_CPL_DATA_QUEUE_ENTRIES_S   0\n+#define PCIE_VC0_CBD_CPL_HDR_QUEUE_ENTRIES      0x03FF0000 /* VC0 Completion Header Queue Depth */\n+#define PCIE_VC0_CBD_CPL_HDR_QUEUE_ENTRIES_S    16\n+\n+/* PHY Status Register, all zeros in VR9 */\n+#define PCIE_PHYSR(X)                           (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x810)\n+\n+/* PHY Control Register, all zeros in VR9 */\n+#define PCIE_PHYCR(X)                           (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x814)\n+\n+/* \n+ * PCIe PDI PHY register definition, suppose all the following \n+ * stuff is confidential. \n+ * XXX, detailed bit definition\n+ */\n+#define\tPCIE_PHY_PLL_CTRL1(X)       (PCIE_PHY_PORT_TO_BASE(X) + (0x22 << 1))\n+#define\tPCIE_PHY_PLL_CTRL2(X)       (PCIE_PHY_PORT_TO_BASE(X) + (0x23 << 1))\n+#define\tPCIE_PHY_PLL_CTRL3(X)       (PCIE_PHY_PORT_TO_BASE(X) + (0x24 << 1))\n+#define\tPCIE_PHY_PLL_CTRL4(X)       (PCIE_PHY_PORT_TO_BASE(X) + (0x25 << 1))\n+#define\tPCIE_PHY_PLL_CTRL5(X)       (PCIE_PHY_PORT_TO_BASE(X) + (0x26 << 1))\n+#define\tPCIE_PHY_PLL_CTRL6(X)       (PCIE_PHY_PORT_TO_BASE(X) + (0x27 << 1))\n+#define\tPCIE_PHY_PLL_CTRL7(X)       (PCIE_PHY_PORT_TO_BASE(X) + (0x28 << 1))\n+#define\tPCIE_PHY_PLL_A_CTRL1(X)     (PCIE_PHY_PORT_TO_BASE(X) + (0x29 << 1))\n+#define\tPCIE_PHY_PLL_A_CTRL2(X)     (PCIE_PHY_PORT_TO_BASE(X) + (0x2A << 1))\n+#define\tPCIE_PHY_PLL_A_CTRL3(X)     (PCIE_PHY_PORT_TO_BASE(X) + (0x2B << 1))\n+#define\tPCIE_PHY_PLL_STATUS(X)      (PCIE_PHY_PORT_TO_BASE(X) + (0x2C << 1))\n+ \n+#define PCIE_PHY_TX1_CTRL1(X)       (PCIE_PHY_PORT_TO_BASE(X) + (0x30 << 1))\n+#define PCIE_PHY_TX1_CTRL2(X)       (PCIE_PHY_PORT_TO_BASE(X) + (0x31 << 1))\n+#define PCIE_PHY_TX1_CTRL3(X)       (PCIE_PHY_PORT_TO_BASE(X) + (0x32 << 1))\n+#define PCIE_PHY_TX1_A_CTRL1(X)     (PCIE_PHY_PORT_TO_BASE(X) + (0x33 << 1))\n+#define PCIE_PHY_TX1_A_CTRL2(X)     (PCIE_PHY_PORT_TO_BASE(X) + (0x34 << 1))\n+#define PCIE_PHY_TX1_MOD1(X)        (PCIE_PHY_PORT_TO_BASE(X) + (0x35 << 1))\n+#define PCIE_PHY_TX1_MOD2(X)        (PCIE_PHY_PORT_TO_BASE(X) + (0x36 << 1))\n+#define PCIE_PHY_TX1_MOD3(X)        (PCIE_PHY_PORT_TO_BASE(X) + (0x37 << 1))\n+\n+#define PCIE_PHY_TX2_CTRL1(X)       (PCIE_PHY_PORT_TO_BASE(X) + (0x38 << 1))\n+#define PCIE_PHY_TX2_CTRL2(X)       (PCIE_PHY_PORT_TO_BASE(X) + (0x39 << 1))\n+#define PCIE_PHY_TX2_A_CTRL1(X)     (PCIE_PHY_PORT_TO_BASE(X) + (0x3B << 1))\n+#define PCIE_PHY_TX2_A_CTRL2(X)     (PCIE_PHY_PORT_TO_BASE(X) + (0x3C << 1))\n+#define PCIE_PHY_TX2_MOD1(X)        (PCIE_PHY_PORT_TO_BASE(X) + (0x3D << 1))\n+#define PCIE_PHY_TX2_MOD2(X)        (PCIE_PHY_PORT_TO_BASE(X) + (0x3E << 1))\n+#define PCIE_PHY_TX2_MOD3(X)        (PCIE_PHY_PORT_TO_BASE(X) + (0x3F << 1))\n+\n+#define PCIE_PHY_RX1_CTRL1(X)       (PCIE_PHY_PORT_TO_BASE(X) + (0x50 << 1))\n+#define PCIE_PHY_RX1_CTRL2(X)       (PCIE_PHY_PORT_TO_BASE(X) + (0x51 << 1))\n+#define PCIE_PHY_RX1_CDR(X)         (PCIE_PHY_PORT_TO_BASE(X) + (0x52 << 1))\n+#define PCIE_PHY_RX1_EI(X)          (PCIE_PHY_PORT_TO_BASE(X) + (0x53 << 1))\n+#define PCIE_PHY_RX1_A_CTRL(X)      (PCIE_PHY_PORT_TO_BASE(X) + (0x55 << 1))\n+\n+/* Interrupt related stuff */\n+#define PCIE_LEGACY_DISABLE 0\n+#define PCIE_LEGACY_INTA  1\n+#define PCIE_LEGACY_INTB  2\n+#define PCIE_LEGACY_INTC  3\n+#define PCIE_LEGACY_INTD  4\n+#define PCIE_LEGACY_INT_MAX PCIE_LEGACY_INTD\n+\n+#endif /* IFXMIPS_PCIE_REG_H */\n+\n--- /dev/null\n+++ b/arch/mips/pci/ifxmips_pcie_vr9.h\n@@ -0,0 +1,269 @@\n+/****************************************************************************\n+                              Copyright (c) 2010\n+                            Lantiq Deutschland GmbH\n+                     Am Campeon 3; 85579 Neubiberg, Germany\n+\n+  For licensing information, see the file 'LICENSE' in the root folder of\n+  this software module.\n+\n+ *****************************************************************************/\n+/*!\n+  \\file ifxmips_pcie_vr9.h\n+  \\ingroup IFX_PCIE\n+  \\brief PCIe RC driver vr9 specific file\n+*/\n+\n+#ifndef IFXMIPS_PCIE_VR9_H\n+#define IFXMIPS_PCIE_VR9_H\n+\n+#include <linux/types.h>\n+#include <linux/delay.h>\n+\n+#include <linux/gpio.h>\n+#include <lantiq_soc.h>\n+\n+#define IFX_PCIE_GPIO_RESET  494\n+\n+#define IFX_REG_R32    ltq_r32\n+#define IFX_REG_W32    ltq_w32\n+#define CONFIG_IFX_PCIE_HW_SWAP\n+#define IFX_RCU_AHB_ENDIAN                      ((volatile u32*)(IFX_RCU + 0x004C))\n+#define IFX_RCU_RST_REQ                         ((volatile u32*)(IFX_RCU + 0x0010))\n+#define IFX_RCU_AHB_BE_PCIE_PDI                  0x00000080  /* Configure PCIE PDI module in big endian*/\n+\n+#define IFX_RCU                                 (KSEG1 | 0x1F203000)\n+#define IFX_RCU_AHB_BE_PCIE_M                    0x00000001  /* Configure AHB master port that connects to PCIe RC in big endian */\n+#define IFX_RCU_AHB_BE_PCIE_S                    0x00000010  /* Configure AHB slave port that connects to PCIe RC in little endian */\n+#define IFX_RCU_AHB_BE_XBAR_M                    0x00000002  /* Configure AHB master port that connects to XBAR in big endian */\n+#define CONFIG_IFX_PCIE_PHY_36MHZ_MODE\n+\n+#define IFX_PMU1_MODULE_PCIE_PHY   (0)\n+#define IFX_PMU1_MODULE_PCIE_CTRL  (1)\n+#define IFX_PMU1_MODULE_PDI        (4)\n+#define IFX_PMU1_MODULE_MSI        (5)\n+\n+#define IFX_PMU_MODULE_PCIE_L0_CLK (31)\n+\n+\n+#define IFX_GPIO\t\t\t\t(KSEG1 | 0x1E100B00)\n+#define ALT0\t\t\t((volatile u32*)(IFX_GPIO + 0x007c))\n+#define ALT1\t\t\t((volatile u32*)(IFX_GPIO + 0x0080))\n+#define OD\t\t\t((volatile u32*)(IFX_GPIO + 0x0084))\n+#define DIR\t\t\t((volatile u32*)(IFX_GPIO + 0x0078))\n+#define OUT\t\t\t((volatile u32*)(IFX_GPIO + 0x0070))\n+\n+\n+static inline void pcie_ep_gpio_rst_init(int pcie_port)\n+{\n+\n+\tgpio_request(IFX_PCIE_GPIO_RESET, \"pcie-reset\");\n+\tgpio_direction_output(IFX_PCIE_GPIO_RESET, 1);\n+\tgpio_set_value(IFX_PCIE_GPIO_RESET, 1);\n+\n+/*    ifx_gpio_pin_reserve(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);\n+    ifx_gpio_output_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);\n+    ifx_gpio_dir_out_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);\n+    ifx_gpio_altsel0_clear(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);\n+    ifx_gpio_altsel1_clear(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);\n+    ifx_gpio_open_drain_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);*/\n+}\n+\n+static inline void pcie_ahb_pmu_setup(void) \n+{\n+\t/* Enable AHB bus master/slave */\n+\tstruct clk *clk;\n+\tclk = clk_get_sys(\"1d900000.pcie\", \"ahb\");\n+\tclk_enable(clk);\n+\n+    //AHBM_PMU_SETUP(IFX_PMU_ENABLE);\n+    //AHBS_PMU_SETUP(IFX_PMU_ENABLE);\n+}\n+\n+static inline void pcie_rcu_endian_setup(int pcie_port)\n+{\n+    u32 reg;\n+\n+    reg = IFX_REG_R32(IFX_RCU_AHB_ENDIAN);\n+#ifdef CONFIG_IFX_PCIE_HW_SWAP\n+    reg |= IFX_RCU_AHB_BE_PCIE_M;\n+    reg |= IFX_RCU_AHB_BE_PCIE_S;\n+    reg &= ~IFX_RCU_AHB_BE_XBAR_M;\n+#else \n+    reg |= IFX_RCU_AHB_BE_PCIE_M;\n+    reg &= ~IFX_RCU_AHB_BE_PCIE_S;\n+    reg &= ~IFX_RCU_AHB_BE_XBAR_M;\n+#endif /* CONFIG_IFX_PCIE_HW_SWAP */\n+    IFX_REG_W32(reg, IFX_RCU_AHB_ENDIAN);\n+    IFX_PCIE_PRINT(PCIE_MSG_REG, \"%s IFX_RCU_AHB_ENDIAN: 0x%08x\\n\", __func__, IFX_REG_R32(IFX_RCU_AHB_ENDIAN));\n+}\n+\n+static inline void pcie_phy_pmu_enable(int pcie_port)\n+{\n+\tstruct clk *clk;\n+\tclk = clk_get_sys(\"1d900000.pcie\", \"phy\");\n+\tclk_enable(clk);\n+\n+\t//PCIE_PHY_PMU_SETUP(IFX_PMU_ENABLE);\n+}\n+\n+static inline void pcie_phy_pmu_disable(int pcie_port)\n+{\n+\tstruct clk *clk;\n+\tclk = clk_get_sys(\"1d900000.pcie\", \"phy\");\n+\tclk_disable(clk);\n+\n+//    PCIE_PHY_PMU_SETUP(IFX_PMU_DISABLE);\n+}\n+\n+static inline void pcie_pdi_big_endian(int pcie_port)\n+{\n+    u32 reg;\n+\n+    /* SRAM2PDI endianness control. */\n+    reg = IFX_REG_R32(IFX_RCU_AHB_ENDIAN);\n+    /* Config AHB->PCIe and PDI endianness */\n+    reg |= IFX_RCU_AHB_BE_PCIE_PDI;\n+    IFX_REG_W32(reg, IFX_RCU_AHB_ENDIAN);\n+}\n+\n+static inline void pcie_pdi_pmu_enable(int pcie_port)\n+{\n+    /* Enable PDI to access PCIe PHY register */\n+\tstruct clk *clk;\n+\tclk = clk_get_sys(\"1d900000.pcie\", \"pdi\");\n+\tclk_enable(clk);\n+    //PDI_PMU_SETUP(IFX_PMU_ENABLE);\n+}\n+\n+static inline void pcie_core_rst_assert(int pcie_port)\n+{\n+    u32 reg;\n+\n+    reg = IFX_REG_R32(IFX_RCU_RST_REQ);\n+\n+    /* Reset PCIe PHY & Core, bit 22, bit 26 may be affected if write it directly  */\n+    reg |= 0x00400000;\n+    IFX_REG_W32(reg, IFX_RCU_RST_REQ);\n+}\n+\n+static inline void pcie_core_rst_deassert(int pcie_port)\n+{\n+    u32 reg;\n+\n+    /* Make sure one micro-second delay */\n+    udelay(1);\n+\n+    /* Reset PCIe PHY & Core, bit 22 */\n+    reg = IFX_REG_R32(IFX_RCU_RST_REQ);\n+    reg &= ~0x00400000;\n+    IFX_REG_W32(reg, IFX_RCU_RST_REQ);\n+}\n+\n+static inline void pcie_phy_rst_assert(int pcie_port)\n+{\n+    u32 reg;\n+\n+    reg = IFX_REG_R32(IFX_RCU_RST_REQ);\n+    reg |= 0x00001000; /* Bit 12 */\n+    IFX_REG_W32(reg, IFX_RCU_RST_REQ);\n+}\n+\n+static inline void pcie_phy_rst_deassert(int pcie_port)\n+{\n+    u32 reg;\n+\n+    /* Make sure one micro-second delay */\n+    udelay(1);\n+\n+    reg = IFX_REG_R32(IFX_RCU_RST_REQ);\n+    reg &= ~0x00001000; /* Bit 12 */\n+    IFX_REG_W32(reg, IFX_RCU_RST_REQ);\n+}\n+\n+static inline void pcie_device_rst_assert(int pcie_port)\n+{\n+\tgpio_set_value(IFX_PCIE_GPIO_RESET, 0);\n+//    ifx_gpio_output_clear(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);\n+}\n+\n+static inline void pcie_device_rst_deassert(int pcie_port)\n+{\n+    mdelay(100);\n+\tgpio_direction_output(IFX_PCIE_GPIO_RESET, 1);\n+//    gpio_set_value(IFX_PCIE_GPIO_RESET, 1);\n+    //ifx_gpio_output_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);\n+}\n+\n+static inline void pcie_core_pmu_setup(int pcie_port)\n+{\n+\tstruct clk *clk;\n+\tclk = clk_get_sys(\"1d900000.pcie\", \"ctl\");\n+\tclk_enable(clk);\n+\tclk = clk_get_sys(\"1d900000.pcie\", \"bus\");\n+\tclk_enable(clk);\n+\n+    /* PCIe Core controller enabled */\n+//    PCIE_CTRL_PMU_SETUP(IFX_PMU_ENABLE);\n+\n+    /* Enable PCIe L0 Clock */\n+//  PCIE_L0_CLK_PMU_SETUP(IFX_PMU_ENABLE);\n+}\n+\n+static inline void pcie_msi_init(int pcie_port)\n+{\n+\tstruct clk *clk;\n+\tpcie_msi_pic_init(pcie_port);\n+\tclk = clk_get_sys(\"ltq_pcie\", \"msi\");\n+\tclk_enable(clk);\n+//    MSI_PMU_SETUP(IFX_PMU_ENABLE);\n+}\n+\n+static inline u32\n+ifx_pcie_bus_nr_deduct(u32 bus_number, int pcie_port)\n+{\n+    u32 tbus_number = bus_number;\n+\n+#ifdef CONFIG_PCI_LANTIQ\n+    if (pcibios_host_nr() > 1) {\n+        tbus_number -= pcibios_1st_host_bus_nr();\n+    }\n+#endif /* CONFIG_PCI_LANTIQ */\n+    return tbus_number;\n+}\n+\n+static inline u32\n+ifx_pcie_bus_enum_hack(struct pci_bus *bus, u32 devfn, int where, u32 value, int pcie_port, int read)\n+{\n+    struct pci_dev *pdev;\n+    u32 tvalue = value;\n+\n+    /* Sanity check */\n+    pdev = pci_get_slot(bus, devfn);\n+    if (pdev == NULL) {\n+        return tvalue;\n+    }\n+\n+    /* Only care about PCI bridge */\n+    if (pdev->hdr_type != PCI_HEADER_TYPE_BRIDGE) {\n+        return tvalue;\n+    }\n+\n+    if (read) { /* Read hack */\n+    #ifdef CONFIG_PCI_LANTIQ\n+        if (pcibios_host_nr() > 1) {\n+            tvalue = ifx_pcie_bus_enum_read_hack(where, tvalue);\n+        }\n+    #endif /* CONFIG_PCI_LANTIQ */\n+    }\n+    else { /* Write hack */\n+    #ifdef CONFIG_PCI_LANTIQ\n+        if (pcibios_host_nr() > 1) {\n+            tvalue = ifx_pcie_bus_enum_write_hack(where, tvalue);\n+        }\n+    #endif\n+    }\n+    return tvalue;\n+}\n+\n+#endif /* IFXMIPS_PCIE_VR9_H */\n+\n--- a/arch/mips/pci/pci-legacy.c\n+++ b/arch/mips/pci/pci-legacy.c\n@@ -313,3 +313,30 @@ char *__init pcibios_setup(char *str)\n \t\treturn pcibios_plat_setup(str);\n \treturn str;\n }\n+\n+int pcibios_host_nr(void)\n+{\n+    int count = 0;\n+    struct pci_controller *hose;\n+    list_for_each_entry(hose, &controllers, list) {\n+        count++;\n+    }\n+    return count;\n+}\n+EXPORT_SYMBOL(pcibios_host_nr);\n+\n+int pcibios_1st_host_bus_nr(void)\n+{\n+    int bus_nr = 0;\n+    struct pci_controller *hose;\n+\n+    hose = list_first_entry_or_null(&controllers, struct pci_controller, list);\n+\n+    if (hose != NULL) {\n+        if (hose->bus != NULL) {\n+            bus_nr = hose->bus->number + 1;\n+        }\n+    }\n+    return bus_nr;\n+}\n+EXPORT_SYMBOL(pcibios_1st_host_bus_nr);\n--- /dev/null\n+++ b/arch/mips/pci/pcie-lantiq.h\n@@ -0,0 +1,1301 @@\n+/******************************************************************************\n+**\n+** FILE NAME    : ifxmips_pcie_reg.h\n+** PROJECT      : IFX UEIP for VRX200\n+** MODULES      : PCIe module\n+**\n+** DATE         : 02 Mar 2009\n+** AUTHOR       : Lei Chuanhua\n+** DESCRIPTION  : PCIe Root Complex Driver\n+** COPYRIGHT    :       Copyright (c) 2009\n+**                      Infineon Technologies AG\n+**                      Am Campeon 1-12, 85579 Neubiberg, Germany\n+**\n+**    This program is free software; you can redistribute it and/or modify\n+**    it under the terms of the GNU General Public License as published by\n+**    the Free Software Foundation; either version 2 of the License, or\n+**    (at your option) any later version.\n+** HISTORY\n+** $Version $Date        $Author         $Comment\n+** 0.0.1    17 Mar,2009  Lei Chuanhua    Initial version\n+*******************************************************************************/\n+#ifndef IFXMIPS_PCIE_REG_H\n+#define IFXMIPS_PCIE_REG_H\n+#include <linux/version.h>\n+#include <linux/types.h>\n+#include <linux/pci.h>\n+#include <linux/interrupt.h>\n+/*!\n+ \\file ifxmips_pcie_reg.h\n+ \\ingroup IFX_PCIE  \n+ \\brief header file for PCIe module register definition\n+*/\n+/* PCIe Address Mapping Base */\n+#define PCIE_CFG_PHY_BASE        0x1D000000UL\n+#define PCIE_CFG_BASE           (KSEG1 + PCIE_CFG_PHY_BASE)\n+#define PCIE_CFG_SIZE           (8 * 1024 * 1024)\n+\n+#define PCIE_MEM_PHY_BASE        0x1C000000UL\n+#define PCIE_MEM_BASE           (KSEG1 + PCIE_MEM_PHY_BASE)\n+#define PCIE_MEM_SIZE           (16 * 1024 * 1024)\n+#define PCIE_MEM_PHY_END        (PCIE_MEM_PHY_BASE + PCIE_MEM_SIZE - 1)\n+\n+#define PCIE_IO_PHY_BASE         0x1D800000UL\n+#define PCIE_IO_BASE            (KSEG1 + PCIE_IO_PHY_BASE)\n+#define PCIE_IO_SIZE            (1 * 1024 * 1024)\n+#define PCIE_IO_PHY_END         (PCIE_IO_PHY_BASE + PCIE_IO_SIZE - 1)\n+\n+#define PCIE_RC_CFG_BASE        (KSEG1 + 0x1D900000)\n+#define PCIE_APP_LOGIC_REG      (KSEG1 + 0x1E100900)\n+#define PCIE_MSI_PHY_BASE        0x1F600000UL\n+\n+#define PCIE_PDI_PHY_BASE        0x1F106800UL\n+#define PCIE_PDI_BASE           (KSEG1 + PCIE_PDI_PHY_BASE)\n+#define PCIE_PDI_SIZE            0x400\n+\n+#define PCIE1_CFG_PHY_BASE        0x19000000UL\n+#define PCIE1_CFG_BASE           (KSEG1 + PCIE1_CFG_PHY_BASE)\n+#define PCIE1_CFG_SIZE           (8 * 1024 * 1024)\n+\n+#define PCIE1_MEM_PHY_BASE        0x18000000UL\n+#define PCIE1_MEM_BASE           (KSEG1 + PCIE1_MEM_PHY_BASE)\n+#define PCIE1_MEM_SIZE           (16 * 1024 * 1024)\n+#define PCIE1_MEM_PHY_END        (PCIE1_MEM_PHY_BASE + PCIE1_MEM_SIZE - 1)\n+\n+#define PCIE1_IO_PHY_BASE         0x19800000UL\n+#define PCIE1_IO_BASE            (KSEG1 + PCIE1_IO_PHY_BASE)\n+#define PCIE1_IO_SIZE            (1 * 1024 * 1024)\n+#define PCIE1_IO_PHY_END         (PCIE1_IO_PHY_BASE + PCIE1_IO_SIZE - 1)\n+\n+#define PCIE1_RC_CFG_BASE        (KSEG1 + 0x19900000)\n+#define PCIE1_APP_LOGIC_REG      (KSEG1 + 0x1E100700)\n+#define PCIE1_MSI_PHY_BASE        0x1F400000UL\n+\n+#define PCIE1_PDI_PHY_BASE        0x1F700400UL\n+#define PCIE1_PDI_BASE           (KSEG1 + PCIE1_PDI_PHY_BASE)\n+#define PCIE1_PDI_SIZE            0x400\n+\n+#define PCIE_CFG_PORT_TO_BASE(X)     ((X) > 0 ? (PCIE1_CFG_BASE) : (PCIE_CFG_BASE))\n+#define PCIE_MEM_PORT_TO_BASE(X)     ((X) > 0 ? (PCIE1_MEM_BASE) : (PCIE_MEM_BASE))\n+#define PCIE_IO_PORT_TO_BASE(X)      ((X) > 0 ? (PCIE1_IO_BASE) : (PCIE_IO_BASE))\n+#define PCIE_MEM_PHY_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_MEM_PHY_BASE) : (PCIE_MEM_PHY_BASE))\n+#define PCIE_MEM_PHY_PORT_TO_END(X)  ((X) > 0 ? (PCIE1_MEM_PHY_END) : (PCIE_MEM_PHY_END))\n+#define PCIE_IO_PHY_PORT_TO_BASE(X)  ((X) > 0 ? (PCIE1_IO_PHY_BASE) : (PCIE_IO_PHY_BASE))\n+#define PCIE_IO_PHY_PORT_TO_END(X)   ((X) > 0 ? (PCIE1_IO_PHY_END) : (PCIE_IO_PHY_END))\n+#define PCIE_APP_PORT_TO_BASE(X)     ((X) > 0 ? (PCIE1_APP_LOGIC_REG) : (PCIE_APP_LOGIC_REG))\n+#define PCIE_RC_PORT_TO_BASE(X)      ((X) > 0 ? (PCIE1_RC_CFG_BASE) : (PCIE_RC_CFG_BASE))\n+#define PCIE_PHY_PORT_TO_BASE(X)     ((X) > 0 ? (PCIE1_PDI_BASE) : (PCIE_PDI_BASE))\n+\n+/* PCIe Application Logic Register */\n+/* RC Core Control Register */\n+#define PCIE_RC_CCR(X)                      (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x10)\n+/* This should be enabled after initializing configuratin registers\n+ * Also should check link status retraining bit\n+ */\n+#define PCIE_RC_CCR_LTSSM_ENABLE             0x00000001    /* Enable LTSSM to continue link establishment */\n+\n+/* RC Core Debug Register */\n+#define PCIE_RC_DR(X)                       (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x14)\n+#define PCIE_RC_DR_DLL_UP                    0x00000001  /* Data Link Layer Up */\n+#define PCIE_RC_DR_CURRENT_POWER_STATE       0x0000000E  /* Current Power State */\n+#define PCIE_RC_DR_CURRENT_POWER_STATE_S     1\n+#define PCIE_RC_DR_CURRENT_LTSSM_STATE       0x000001F0  /* Current LTSSM State */\n+#define PCIE_RC_DR_CURRENT_LTSSM_STATE_S     4\n+\n+#define PCIE_RC_DR_PM_DEV_STATE              0x00000E00  /* Power Management D-State */\n+#define PCIE_RC_DR_PM_DEV_STATE_S            9\n+\n+#define PCIE_RC_DR_PM_ENABLED                0x00001000  /* Power Management State from PMU */\n+#define PCIE_RC_DR_PME_EVENT_ENABLED         0x00002000  /* Power Management Event Enable State */\n+#define PCIE_RC_DR_AUX_POWER_ENABLED         0x00004000  /* Auxiliary Power Enable */\n+\n+/* Current Power State Definition */\n+enum {\n+    PCIE_RC_DR_D0 = 0,\n+    PCIE_RC_DR_D1,   /* Not supported */\n+    PCIE_RC_DR_D2,   /* Not supported */\n+    PCIE_RC_DR_D3,\n+    PCIE_RC_DR_UN,\n+};\n+\n+/* PHY Link Status Register */\n+#define PCIE_PHY_SR(X)                      (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x18)\n+#define PCIE_PHY_SR_PHY_LINK_UP              0x00000001   /* PHY Link Up/Down Indicator */\n+\n+/* Electromechanical Control Register */\n+#define PCIE_EM_CR(X)                       (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x1C)\n+#define PCIE_EM_CR_CARD_IS_PRESENT           0x00000001  /* Card Presence Detect State */\n+#define PCIE_EM_CR_MRL_OPEN                  0x00000002  /* MRL Sensor State */\n+#define PCIE_EM_CR_POWER_FAULT_SET           0x00000004  /* Power Fault Detected */\n+#define PCIE_EM_CR_MRL_SENSOR_SET            0x00000008  /* MRL Sensor Changed */\n+#define PCIE_EM_CR_PRESENT_DETECT_SET        0x00000010  /* Card Presense Detect Changed */\n+#define PCIE_EM_CR_CMD_CPL_INT_SET           0x00000020  /* Command Complete Interrupt */\n+#define PCIE_EM_CR_SYS_INTERLOCK_SET         0x00000040  /* System Electromechanical IterLock Engaged */\n+#define PCIE_EM_CR_ATTENTION_BUTTON_SET      0x00000080  /* Attention Button Pressed */\n+\n+/* Interrupt Status Register */\n+#define PCIE_IR_SR(X)                       (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x20)\n+#define PCIE_IR_SR_PME_CAUSE_MSI             0x00000002  /* MSI caused by PME */\n+#define PCIE_IR_SR_HP_PME_WAKE_GEN           0x00000004  /* Hotplug PME Wake Generation */\n+#define PCIE_IR_SR_HP_MSI                    0x00000008  /* Hotplug MSI */\n+#define PCIE_IR_SR_AHB_LU_ERR                0x00000030  /* AHB Bridge Lookup Error Signals */\n+#define PCIE_IR_SR_AHB_LU_ERR_S              4\n+#define PCIE_IR_SR_INT_MSG_NUM               0x00003E00  /* Interrupt Message Number */\n+#define PCIE_IR_SR_INT_MSG_NUM_S             9\n+#define PCIE_IR_SR_AER_INT_MSG_NUM           0xF8000000  /* Advanced Error Interrupt Message Number */\n+#define PCIE_IR_SR_AER_INT_MSG_NUM_S         27\n+\n+/* Message Control Register */\n+#define PCIE_MSG_CR(X)                      (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x30)\n+#define PCIE_MSG_CR_GEN_PME_TURN_OFF_MSG     0x00000001  /* Generate PME Turn Off Message */\n+#define PCIE_MSG_CR_GEN_UNLOCK_MSG           0x00000002  /* Generate Unlock Message */\n+\n+#define PCIE_VDM_DR(X)                      (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x34)\n+\n+/* Vendor-Defined Message Requester ID Register */\n+#define PCIE_VDM_RID(X)                     (PCIE_APP_PORT_TO_BASE (X) + 0x38)\n+#define PCIE_VDM_RID_VENROR_MSG_REQ_ID       0x0000FFFF\n+#define PCIE_VDM_RID_VDMRID_S                0\n+\n+/* ASPM Control Register */\n+#define PCIE_ASPM_CR(X)                     (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x40)\n+#define PCIE_ASPM_CR_HOT_RST                 0x00000001  /* Hot Reset Request to the downstream device */\n+#define PCIE_ASPM_CR_REQ_EXIT_L1             0x00000002  /* Request to Exit L1 */\n+#define PCIE_ASPM_CR_REQ_ENTER_L1            0x00000004  /* Request to Enter L1 */\n+\n+/* Vendor Message DW0 Register */\n+#define PCIE_VM_MSG_DW0(X)                  (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x50)\n+#define PCIE_VM_MSG_DW0_TYPE                 0x0000001F  /* Message type */\n+#define PCIE_VM_MSG_DW0_TYPE_S               0\n+#define PCIE_VM_MSG_DW0_FORMAT               0x00000060  /* Format */\n+#define PCIE_VM_MSG_DW0_FORMAT_S             5\n+#define PCIE_VM_MSG_DW0_TC                   0x00007000  /* Traffic Class */\n+#define PCIE_VM_MSG_DW0_TC_S                 12\n+#define PCIE_VM_MSG_DW0_ATTR                 0x000C0000  /* Atrributes */\n+#define PCIE_VM_MSG_DW0_ATTR_S               18\n+#define PCIE_VM_MSG_DW0_EP_TLP               0x00100000  /* Poisoned TLP */\n+#define PCIE_VM_MSG_DW0_TD                   0x00200000  /* TLP Digest */\n+#define PCIE_VM_MSG_DW0_LEN                  0xFFC00000  /* Length */\n+#define PCIE_VM_MSG_DW0_LEN_S                22\n+\n+/* Format Definition */\n+enum {\n+    PCIE_VM_MSG_FORMAT_00 = 0,  /* 3DW Hdr, no data*/\n+    PCIE_VM_MSG_FORMAT_01,      /* 4DW Hdr, no data */\n+    PCIE_VM_MSG_FORMAT_10,      /* 3DW Hdr, with data */\n+    PCIE_VM_MSG_FORMAT_11,      /* 4DW Hdr, with data */\n+};\n+\n+/* Traffic Class Definition */\n+enum {\n+    PCIE_VM_MSG_TC0 = 0,\n+    PCIE_VM_MSG_TC1,\n+    PCIE_VM_MSG_TC2,\n+    PCIE_VM_MSG_TC3,\n+    PCIE_VM_MSG_TC4,\n+    PCIE_VM_MSG_TC5,\n+    PCIE_VM_MSG_TC6,\n+    PCIE_VM_MSG_TC7,\n+};\n+\n+/* Attributes Definition */\n+enum {\n+    PCIE_VM_MSG_ATTR_00 = 0,   /* RO and No Snoop cleared */\n+    PCIE_VM_MSG_ATTR_01,       /* RO cleared , No Snoop set */\n+    PCIE_VM_MSG_ATTR_10,       /* RO set, No Snoop cleared*/\n+    PCIE_VM_MSG_ATTR_11,       /* RO and No Snoop set */\n+};\n+\n+/* Payload Size Definition */\n+#define PCIE_VM_MSG_LEN_MIN  0\n+#define PCIE_VM_MSG_LEN_MAX  1024\n+\n+/* Vendor Message DW1 Register */\n+#define PCIE_VM_MSG_DW1(X)                 (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x54)\n+#define PCIE_VM_MSG_DW1_FUNC_NUM            0x00000070  /* Function Number */\n+#define PCIE_VM_MSG_DW1_FUNC_NUM_S          8\n+#define PCIE_VM_MSG_DW1_CODE                0x00FF0000  /* Message Code */\n+#define PCIE_VM_MSG_DW1_CODE_S              16\n+#define PCIE_VM_MSG_DW1_TAG                 0xFF000000  /* Tag */\n+#define PCIE_VM_MSG_DW1_TAG_S               24\n+\n+#define PCIE_VM_MSG_DW2(X)                  (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x58)\n+#define PCIE_VM_MSG_DW3(X)                  (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x5C)\n+\n+/* Vendor Message Request Register */\n+#define PCIE_VM_MSG_REQR(X)                 (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x60)\n+#define PCIE_VM_MSG_REQR_REQ                 0x00000001  /* Vendor Message Request */\n+\n+\n+/* AHB Slave Side Band Control Register */\n+#define PCIE_AHB_SSB(X)                     (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x70)\n+#define PCIE_AHB_SSB_REQ_BCM                0x00000001 /* Slave Reques BCM filed */\n+#define PCIE_AHB_SSB_REQ_EP                 0x00000002 /* Slave Reques EP filed */\n+#define PCIE_AHB_SSB_REQ_TD                 0x00000004 /* Slave Reques TD filed */\n+#define PCIE_AHB_SSB_REQ_ATTR               0x00000018 /* Slave Reques Attribute number */\n+#define PCIE_AHB_SSB_REQ_ATTR_S             3\n+#define PCIE_AHB_SSB_REQ_TC                 0x000000E0 /* Slave Request TC Field */\n+#define PCIE_AHB_SSB_REQ_TC_S               5\n+\n+/* AHB Master SideBand Ctrl Register */\n+#define PCIE_AHB_MSB(X)                     (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x74)\n+#define PCIE_AHB_MSB_RESP_ATTR               0x00000003 /* Master Response Attribute number */\n+#define PCIE_AHB_MSB_RESP_ATTR_S             0\n+#define PCIE_AHB_MSB_RESP_BAD_EOT            0x00000004 /* Master Response Badeot filed */\n+#define PCIE_AHB_MSB_RESP_BCM                0x00000008 /* Master Response BCM filed */\n+#define PCIE_AHB_MSB_RESP_EP                 0x00000010 /* Master Response EP filed */\n+#define PCIE_AHB_MSB_RESP_TD                 0x00000020 /* Master Response TD filed */\n+#define PCIE_AHB_MSB_RESP_FUN_NUM            0x000003C0 /* Master Response Function number */\n+#define PCIE_AHB_MSB_RESP_FUN_NUM_S          6\n+\n+/* AHB Control Register, fixed bus enumeration exception */\n+#define PCIE_AHB_CTRL(X)                     (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x78)\n+#define PCIE_AHB_CTRL_BUS_ERROR_SUPPRESS     0x00000001 \n+\n+/* Interrupt Enalbe Register */\n+#define PCIE_IRNEN(X)                        (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0xF4)\n+#define PCIE_IRNCR(X)                        (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0xF8)\n+#define PCIE_IRNICR(X)                       (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0xFC)\n+\n+/* PCIe interrupt enable/control/capture register definition */\n+#define PCIE_IRN_AER_REPORT                 0x00000001  /* AER Interrupt */\n+#define PCIE_IRN_AER_MSIX                   0x00000002  /* Advanced Error MSI-X Interrupt */\n+#define PCIE_IRN_PME                        0x00000004  /* PME Interrupt */\n+#define PCIE_IRN_HOTPLUG                    0x00000008  /* Hotplug Interrupt */\n+#define PCIE_IRN_RX_VDM_MSG                 0x00000010  /* Vendor-Defined Message Interrupt */\n+#define PCIE_IRN_RX_CORRECTABLE_ERR_MSG     0x00000020  /* Correctable Error Message Interrupt */\n+#define PCIE_IRN_RX_NON_FATAL_ERR_MSG       0x00000040  /* Non-fatal Error Message */\n+#define PCIE_IRN_RX_FATAL_ERR_MSG           0x00000080  /* Fatal Error Message */\n+#define PCIE_IRN_RX_PME_MSG                 0x00000100  /* PME Message Interrupt */\n+#define PCIE_IRN_RX_PME_TURNOFF_ACK         0x00000200  /* PME Turnoff Ack Message Interrupt */\n+#define PCIE_IRN_AHB_BR_FATAL_ERR           0x00000400  /* AHB Fatal Error Interrupt */\n+#define PCIE_IRN_LINK_AUTO_BW_STATUS        0x00000800  /* Link Auto Bandwidth Status Interrupt */\n+#define PCIE_IRN_BW_MGT                     0x00001000  /* Bandwidth Managment Interrupt */\n+#define PCIE_IRN_INTA                       0x00002000  /* INTA */\n+#define PCIE_IRN_INTB                       0x00004000  /* INTB */\n+#define PCIE_IRN_INTC                       0x00008000  /* INTC */\n+#define PCIE_IRN_INTD                       0x00010000  /* INTD */\n+#define PCIE_IRN_WAKEUP                     0x00020000  /* Wake up Interrupt */\n+\n+#define PCIE_RC_CORE_COMBINED_INT    (PCIE_IRN_AER_REPORT |  PCIE_IRN_AER_MSIX | PCIE_IRN_PME | \\\n+                                      PCIE_IRN_HOTPLUG | PCIE_IRN_RX_VDM_MSG | PCIE_IRN_RX_CORRECTABLE_ERR_MSG |\\\n+                                      PCIE_IRN_RX_NON_FATAL_ERR_MSG | PCIE_IRN_RX_FATAL_ERR_MSG | \\\n+                                      PCIE_IRN_RX_PME_MSG | PCIE_IRN_RX_PME_TURNOFF_ACK | PCIE_IRN_AHB_BR_FATAL_ERR | \\\n+                                      PCIE_IRN_LINK_AUTO_BW_STATUS | PCIE_IRN_BW_MGT)\n+/* PCIe RC Configuration Register */\n+#define PCIE_VDID(X)                (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x00)\n+\n+/* Bit definition from pci_reg.h */\n+#define PCIE_PCICMDSTS(X)           (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x04)\n+#define PCIE_CCRID(X)               (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x08)\n+#define PCIE_CLSLTHTBR(X)           (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x0C) /* EP only */\n+/* BAR0, BAR1,Only necessary if the bridges implements a device-specific register set or memory buffer */\n+#define PCIE_BAR0(X)                (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x10) /* Not used*/\n+#define PCIE_BAR1(X)                (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x14) /* Not used */\n+\n+#define PCIE_BNR(X)                 (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x18) /* Mandatory */\n+/* Bus Number Register bits */\n+#define PCIE_BNR_PRIMARY_BUS_NUM             0x000000FF\n+#define PCIE_BNR_PRIMARY_BUS_NUM_S           0\n+#define PCIE_PNR_SECONDARY_BUS_NUM           0x0000FF00\n+#define PCIE_PNR_SECONDARY_BUS_NUM_S         8\n+#define PCIE_PNR_SUB_BUS_NUM                 0x00FF0000\n+#define PCIE_PNR_SUB_BUS_NUM_S               16\n+\n+/* IO Base/Limit Register bits */\n+#define PCIE_IOBLSECS(X)                       (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x1C)  /* RC only */\n+#define PCIE_IOBLSECS_32BIT_IO_ADDR             0x00000001\n+#define PCIE_IOBLSECS_IO_BASE_ADDR              0x000000F0\n+#define PCIE_IOBLSECS_IO_BASE_ADDR_S            4\n+#define PCIE_IOBLSECS_32BIT_IOLIMT              0x00000100\n+#define PCIE_IOBLSECS_IO_LIMIT_ADDR             0x0000F000\n+#define PCIE_IOBLSECS_IO_LIMIT_ADDR_S           12\n+\n+/* Non-prefetchable Memory Base/Limit Register bit */\n+#define PCIE_MBML(X)                           (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x20)  /* RC only */\n+#define PCIE_MBML_MEM_BASE_ADDR                 0x0000FFF0\n+#define PCIE_MBML_MEM_BASE_ADDR_S               4\n+#define PCIE_MBML_MEM_LIMIT_ADDR                0xFFF00000\n+#define PCIE_MBML_MEM_LIMIT_ADDR_S              20\n+\n+/* Prefetchable Memory Base/Limit Register bit */\n+#define PCIE_PMBL(X)                           (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x24)  /* RC only */\n+#define PCIE_PMBL_64BIT_ADDR                    0x00000001\n+#define PCIE_PMBL_UPPER_12BIT                   0x0000FFF0\n+#define PCIE_PMBL_UPPER_12BIT_S                 4\n+#define PCIE_PMBL_E64MA                         0x00010000\n+#define PCIE_PMBL_END_ADDR                      0xFFF00000\n+#define PCIE_PMBL_END_ADDR_S                    20\n+#define PCIE_PMBU32(X)                          (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x28)  /* RC only */\n+#define PCIE_PMLU32(X)                          (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x2C)  /* RC only */\n+\n+/* I/O Base/Limit Upper 16 bits register */\n+#define PCIE_IO_BANDL(X)                        (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x30)  /* RC only */\n+#define PCIE_IO_BANDL_UPPER_16BIT_IO_BASE        0x0000FFFF\n+#define PCIE_IO_BANDL_UPPER_16BIT_IO_BASE_S      0\n+#define PCIE_IO_BANDL_UPPER_16BIT_IO_LIMIT       0xFFFF0000\n+#define PCIE_IO_BANDL_UPPER_16BIT_IO_LIMIT_S     16\n+\n+#define PCIE_CPR(X)                            (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x34)\n+#define PCIE_EBBAR(X)                          (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x38)\n+\n+/* Interrupt and Secondary Bridge Control Register */\n+#define PCIE_INTRBCTRL(X)                      (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x3C)\n+\n+#define PCIE_INTRBCTRL_INT_LINE                 0x000000FF\n+#define PCIE_INTRBCTRL_INT_LINE_S               0\n+#define PCIE_INTRBCTRL_INT_PIN                  0x0000FF00\n+#define PCIE_INTRBCTRL_INT_PIN_S                8\n+#define PCIE_INTRBCTRL_PARITY_ERR_RESP_ENABLE   0x00010000    /* #PERR */\n+#define PCIE_INTRBCTRL_SERR_ENABLE              0x00020000    /* #SERR */\n+#define PCIE_INTRBCTRL_ISA_ENABLE               0x00040000    /* ISA enable, IO 64KB only */\n+#define PCIE_INTRBCTRL_VGA_ENABLE               0x00080000    /* VGA enable */\n+#define PCIE_INTRBCTRL_VGA_16BIT_DECODE         0x00100000    /* VGA 16bit decode */\n+#define PCIE_INTRBCTRL_RST_SECONDARY_BUS        0x00400000    /* Secondary bus rest, hot rest, 1ms */\n+/* Others are read only */\n+enum {\n+    PCIE_INTRBCTRL_INT_NON = 0,\n+    PCIE_INTRBCTRL_INTA,\n+    PCIE_INTRBCTRL_INTB,\n+    PCIE_INTRBCTRL_INTC,\n+    PCIE_INTRBCTRL_INTD,\n+};\n+\n+#define PCIE_PM_CAPR(X)                  (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x40)\n+\n+/* Power Management Control and Status Register */\n+#define PCIE_PM_CSR(X)                   (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x44)\n+\n+#define PCIE_PM_CSR_POWER_STATE           0x00000003   /* Power State */\n+#define PCIE_PM_CSR_POWER_STATE_S         0\n+#define PCIE_PM_CSR_SW_RST                0x00000008   /* Soft Reset Enabled */\n+#define PCIE_PM_CSR_PME_ENABLE            0x00000100   /* PME Enable */\n+#define PCIE_PM_CSR_PME_STATUS            0x00008000   /* PME status */\n+\n+/* MSI Capability Register for EP */\n+#define PCIE_MCAPR(X)                    (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x50)\n+\n+#define PCIE_MCAPR_MSI_CAP_ID             0x000000FF  /* MSI Capability ID */\n+#define PCIE_MCAPR_MSI_CAP_ID_S           0\n+#define PCIE_MCAPR_MSI_NEXT_CAP_PTR       0x0000FF00  /* Next Capability Pointer */\n+#define PCIE_MCAPR_MSI_NEXT_CAP_PTR_S     8\n+#define PCIE_MCAPR_MSI_ENABLE             0x00010000  /* MSI Enable */\n+#define PCIE_MCAPR_MULTI_MSG_CAP          0x000E0000  /* Multiple Message Capable */\n+#define PCIE_MCAPR_MULTI_MSG_CAP_S        17\n+#define PCIE_MCAPR_MULTI_MSG_ENABLE       0x00700000  /* Multiple Message Enable */\n+#define PCIE_MCAPR_MULTI_MSG_ENABLE_S     20\n+#define PCIE_MCAPR_ADDR64_CAP             0X00800000  /* 64-bit Address Capable */\n+\n+/* MSI Message Address Register */\n+#define PCIE_MA(X)                       (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x54)\n+\n+#define PCIE_MA_ADDR_MASK                 0xFFFFFFFC  /* Message Address */\n+\n+/* MSI Message Upper Address Register */\n+#define PCIE_MUA(X)                      (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x58)\n+\n+/* MSI Message Data Register */\n+#define PCIE_MD(X)                       (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x5C)\n+\n+#define PCIE_MD_DATA                      0x0000FFFF  /* Message Data */\n+#define PCIE_MD_DATA_S                    0\n+\n+/* PCI Express Capability Register */\n+#define PCIE_XCAP(X)                     (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x70)\n+\n+#define PCIE_XCAP_ID                      0x000000FF  /* PCI Express Capability ID */\n+#define PCIE_XCAP_ID_S                    0\n+#define PCIE_XCAP_NEXT_CAP                0x0000FF00  /* Next Capability Pointer */\n+#define PCIE_XCAP_NEXT_CAP_S              8\n+#define PCIE_XCAP_VER                     0x000F0000  /* PCI Express Capability Version */\n+#define PCIE_XCAP_VER_S                   16\n+#define PCIE_XCAP_DEV_PORT_TYPE           0x00F00000  /* Device Port Type */\n+#define PCIE_XCAP_DEV_PORT_TYPE_S         20\n+#define PCIE_XCAP_SLOT_IMPLEMENTED        0x01000000  /* Slot Implemented */\n+#define PCIE_XCAP_MSG_INT_NUM             0x3E000000  /* Interrupt Message Number */\n+#define PCIE_XCAP_MSG_INT_NUM_S           25\n+\n+/* Device Capability Register */\n+#define PCIE_DCAP(X)                     (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x74)\n+\n+#define PCIE_DCAP_MAX_PAYLOAD_SIZE        0x00000007   /* Max Payload size */\n+#define PCIE_DCAP_MAX_PAYLOAD_SIZE_S      0\n+#define PCIE_DCAP_PHANTOM_FUNC            0x00000018   /* Phanton Function, not supported */\n+#define PCIE_DCAP_PHANTOM_FUNC_S          3\n+#define PCIE_DCAP_EXT_TAG                 0x00000020   /* Extended Tag Field */\n+#define PCIE_DCAP_EP_L0S_LATENCY          0x000001C0   /* EP L0s latency only */\n+#define PCIE_DCAP_EP_L0S_LATENCY_S        6\n+#define PCIE_DCAP_EP_L1_LATENCY           0x00000E00   /* EP L1 latency only */\n+#define PCIE_DCAP_EP_L1_LATENCY_S         9\n+#define PCIE_DCAP_ROLE_BASE_ERR_REPORT    0x00008000   /* Role Based ERR */\n+\n+/* Maximum payload size supported */\n+enum {\n+    PCIE_MAX_PAYLOAD_128 = 0,\n+    PCIE_MAX_PAYLOAD_256,\n+    PCIE_MAX_PAYLOAD_512,\n+    PCIE_MAX_PAYLOAD_1024,\n+    PCIE_MAX_PAYLOAD_2048,\n+    PCIE_MAX_PAYLOAD_4096,\n+};\n+\n+/* Device Control and Status Register */\n+#define PCIE_DCTLSTS(X)                       (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x78)\n+\n+#define PCIE_DCTLSTS_CORRECTABLE_ERR_EN        0x00000001   /* COR-ERR */\n+#define PCIE_DCTLSTS_NONFATAL_ERR_EN           0x00000002   /* Non-fatal ERR */\n+#define PCIE_DCTLSTS_FATAL_ERR_EN              0x00000004   /* Fatal ERR */\n+#define PCIE_DCTLSYS_UR_REQ_EN                 0x00000008   /* UR ERR */\n+#define PCIE_DCTLSTS_RELAXED_ORDERING_EN       0x00000010   /* Enable relaxing ordering */\n+#define PCIE_DCTLSTS_MAX_PAYLOAD_SIZE          0x000000E0   /* Max payload mask */\n+#define PCIE_DCTLSTS_MAX_PAYLOAD_SIZE_S        5\n+#define PCIE_DCTLSTS_EXT_TAG_EN                0x00000100   /* Extended tag field */\n+#define PCIE_DCTLSTS_PHANTOM_FUNC_EN           0x00000200   /* Phantom Function Enable */\n+#define PCIE_DCTLSTS_AUX_PM_EN                 0x00000400   /* AUX Power PM Enable */\n+#define PCIE_DCTLSTS_NO_SNOOP_EN               0x00000800   /* Enable no snoop, except root port*/\n+#define PCIE_DCTLSTS_MAX_READ_SIZE             0x00007000   /* Max Read Request size*/\n+#define PCIE_DCTLSTS_MAX_READ_SIZE_S           12\n+#define PCIE_DCTLSTS_CORRECTABLE_ERR           0x00010000   /* COR-ERR Detected */\n+#define PCIE_DCTLSTS_NONFATAL_ERR              0x00020000   /* Non-Fatal ERR Detected */\n+#define PCIE_DCTLSTS_FATAL_ER                  0x00040000   /* Fatal ERR Detected */\n+#define PCIE_DCTLSTS_UNSUPPORTED_REQ           0x00080000   /* UR Detected */\n+#define PCIE_DCTLSTS_AUX_POWER                 0x00100000   /* Aux Power Detected */\n+#define PCIE_DCTLSTS_TRANSACT_PENDING          0x00200000   /* Transaction pending */\n+\n+#define PCIE_DCTLSTS_ERR_EN      (PCIE_DCTLSTS_CORRECTABLE_ERR_EN | \\\n+                                  PCIE_DCTLSTS_NONFATAL_ERR_EN | PCIE_DCTLSTS_FATAL_ERR_EN | \\\n+                                  PCIE_DCTLSYS_UR_REQ_EN)\n+\n+/* Link Capability Register */\n+#define PCIE_LCAP(X)                          (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7C)\n+#define PCIE_LCAP_MAX_LINK_SPEED               0x0000000F  /* Max link speed, 0x1 by default */\n+#define PCIE_LCAP_MAX_LINK_SPEED_S             0\n+#define PCIE_LCAP_MAX_LENGTH_WIDTH             0x000003F0  /* Maxium Length Width */\n+#define PCIE_LCAP_MAX_LENGTH_WIDTH_S           4\n+#define PCIE_LCAP_ASPM_LEVEL                   0x00000C00  /* Active State Link PM Support */\n+#define PCIE_LCAP_ASPM_LEVEL_S                 10\n+#define PCIE_LCAP_L0S_EIXT_LATENCY             0x00007000  /* L0s Exit Latency */\n+#define PCIE_LCAP_L0S_EIXT_LATENCY_S           12\n+#define PCIE_LCAP_L1_EXIT_LATENCY              0x00038000  /* L1 Exit Latency */\n+#define PCIE_LCAP_L1_EXIT_LATENCY_S            15\n+#define PCIE_LCAP_CLK_PM                       0x00040000  /* Clock Power Management */\n+#define PCIE_LCAP_SDER                         0x00080000  /* Surprise Down Error Reporting */\n+#define PCIE_LCAP_DLL_ACTIVE_REPROT            0x00100000  /* Data Link Layer Active Reporting Capable */\n+#define PCIE_LCAP_PORT_NUM                     0xFF0000000  /* Port number */\n+#define PCIE_LCAP_PORT_NUM_S                   24\n+\n+/* Maximum Length width definition */\n+#define PCIE_MAX_LENGTH_WIDTH_RES  0x00\n+#define PCIE_MAX_LENGTH_WIDTH_X1   0x01  /* Default */\n+#define PCIE_MAX_LENGTH_WIDTH_X2   0x02\n+#define PCIE_MAX_LENGTH_WIDTH_X4   0x04\n+#define PCIE_MAX_LENGTH_WIDTH_X8   0x08\n+#define PCIE_MAX_LENGTH_WIDTH_X12  0x0C\n+#define PCIE_MAX_LENGTH_WIDTH_X16  0x10\n+#define PCIE_MAX_LENGTH_WIDTH_X32  0x20\n+\n+/* Active State Link PM definition */\n+enum {\n+    PCIE_ASPM_RES0                = 0,\n+    PCIE_ASPM_L0S_ENTRY_SUPPORT,        /* L0s */\n+    PCIE_ASPM_RES1,\n+    PCIE_ASPM_L0S_L1_ENTRY_SUPPORT,     /* L0s and L1, default */\n+};\n+\n+/* L0s Exit Latency definition */\n+enum {\n+    PCIE_L0S_EIXT_LATENCY_L64NS    = 0, /* < 64 ns */\n+    PCIE_L0S_EIXT_LATENCY_B64A128,      /* > 64 ns < 128 ns */\n+    PCIE_L0S_EIXT_LATENCY_B128A256,     /* > 128 ns < 256 ns */\n+    PCIE_L0S_EIXT_LATENCY_B256A512,     /* > 256 ns < 512 ns */\n+    PCIE_L0S_EIXT_LATENCY_B512TO1U,     /* > 512 ns < 1 us */\n+    PCIE_L0S_EIXT_LATENCY_B1A2U,        /* > 1 us < 2 us */\n+    PCIE_L0S_EIXT_LATENCY_B2A4U,        /* > 2 us < 4 us */\n+    PCIE_L0S_EIXT_LATENCY_M4US,         /* > 4 us  */\n+};\n+\n+/* L1 Exit Latency definition */\n+enum {\n+    PCIE_L1_EXIT_LATENCY_L1US  = 0,  /* < 1 us */\n+    PCIE_L1_EXIT_LATENCY_B1A2,       /* > 1 us < 2 us */\n+    PCIE_L1_EXIT_LATENCY_B2A4,       /* > 2 us < 4 us */\n+    PCIE_L1_EXIT_LATENCY_B4A8,       /* > 4 us < 8 us */\n+    PCIE_L1_EXIT_LATENCY_B8A16,      /* > 8 us < 16 us */\n+    PCIE_L1_EXIT_LATENCY_B16A32,     /* > 16 us < 32 us */\n+    PCIE_L1_EXIT_LATENCY_B32A64,     /* > 32 us < 64 us */\n+    PCIE_L1_EXIT_LATENCY_M64US,      /* > 64 us */\n+};\n+\n+/* Link Control and Status Register */\n+#define PCIE_LCTLSTS(X)                     (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x80)\n+#define PCIE_LCTLSTS_ASPM_ENABLE            0x00000003  /* Active State Link PM Control */\n+#define PCIE_LCTLSTS_ASPM_ENABLE_S          0\n+#define PCIE_LCTLSTS_RCB128                 0x00000008  /* Read Completion Boundary 128*/\n+#define PCIE_LCTLSTS_LINK_DISABLE           0x00000010  /* Link Disable */\n+#define PCIE_LCTLSTS_RETRIAN_LINK           0x00000020  /* Retrain Link */\n+#define PCIE_LCTLSTS_COM_CLK_CFG            0x00000040  /* Common Clock Configuration */\n+#define PCIE_LCTLSTS_EXT_SYNC               0x00000080  /* Extended Synch */\n+#define PCIE_LCTLSTS_CLK_PM_EN              0x00000100  /* Enable Clock Powerm Management */\n+#define PCIE_LCTLSTS_LINK_SPEED             0x000F0000  /* Link Speed */\n+#define PCIE_LCTLSTS_LINK_SPEED_S           16\n+#define PCIE_LCTLSTS_NEGOTIATED_LINK_WIDTH  0x03F00000  /* Negotiated Link Width */\n+#define PCIE_LCTLSTS_NEGOTIATED_LINK_WIDTH_S 20\n+#define PCIE_LCTLSTS_RETRAIN_PENDING        0x08000000  /* Link training is ongoing */\n+#define PCIE_LCTLSTS_SLOT_CLK_CFG           0x10000000  /* Slot Clock Configuration */\n+#define PCIE_LCTLSTS_DLL_ACTIVE             0x20000000  /* Data Link Layer Active */\n+\n+/* Slot Capabilities Register */\n+#define PCIE_SLCAP(X)                       (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x84)\n+\n+/* Slot Capabilities */\n+#define PCIE_SLCTLSTS(X)                    (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x88)\n+\n+/* Root Control and Capability Register */\n+#define PCIE_RCTLCAP(X)                     (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x8C)\n+#define PCIE_RCTLCAP_SERR_ON_CORRECTABLE_ERR  0x00000001   /* #SERR on COR-ERR */\n+#define PCIE_RCTLCAP_SERR_ON_NONFATAL_ERR     0x00000002   /* #SERR on Non-Fatal ERR */\n+#define PCIE_RCTLCAP_SERR_ON_FATAL_ERR        0x00000004   /* #SERR on Fatal ERR */\n+#define PCIE_RCTLCAP_PME_INT_EN               0x00000008   /* PME Interrupt Enable */\n+#define PCIE_RCTLCAP_SERR_ENABLE    (PCIE_RCTLCAP_SERR_ON_CORRECTABLE_ERR | \\\n+                                     PCIE_RCTLCAP_SERR_ON_NONFATAL_ERR | PCIE_RCTLCAP_SERR_ON_FATAL_ERR)\n+/* Root Status Register */\n+#define PCIE_RSTS(X)                          (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x90)\n+#define PCIE_RSTS_PME_REQ_ID                   0x0000FFFF   /* PME Request ID */\n+#define PCIE_RSTS_PME_REQ_ID_S                 0\n+#define PCIE_RSTS_PME_STATUS                   0x00010000   /* PME Status */\n+#define PCIE_RSTS_PME_PENDING                  0x00020000   /* PME Pending */\n+\n+/* PCI Express Enhanced Capability Header */\n+#define PCIE_ENHANCED_CAP(X)                (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x100)\n+#define PCIE_ENHANCED_CAP_ID                 0x0000FFFF  /* PCI Express Extended Capability ID */\n+#define PCIE_ENHANCED_CAP_ID_S               0\n+#define PCIE_ENHANCED_CAP_VER                0x000F0000  /* Capability Version */\n+#define PCIE_ENHANCED_CAP_VER_S              16\n+#define PCIE_ENHANCED_CAP_NEXT_OFFSET        0xFFF00000  /* Next Capability Offset */\n+#define PCIE_ENHANCED_CAP_NEXT_OFFSET_S      20\n+\n+/* Uncorrectable Error Status Register */\n+#define PCIE_UES_R(X)                       (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x104)\n+#define PCIE_DATA_LINK_PROTOCOL_ERR          0x00000010  /* Data Link Protocol Error Status */\n+#define PCIE_SURPRISE_DOWN_ERROR             0x00000020  /* Surprise Down Error Status */\n+#define PCIE_POISONED_TLP                    0x00001000  /* Poisoned TLP Status */\n+#define PCIE_FC_PROTOCOL_ERR                 0x00002000  /* Flow Control Protocol Error Status */\n+#define PCIE_COMPLETION_TIMEOUT              0x00004000  /* Completion Timeout Status */\n+#define PCIE_COMPLETOR_ABORT                 0x00008000  /* Completer Abort Error */\n+#define PCIE_UNEXPECTED_COMPLETION           0x00010000  /* Unexpected Completion Status */\n+#define PCIE_RECEIVER_OVERFLOW               0x00020000  /* Receive Overflow Status */\n+#define PCIE_MALFORNED_TLP                   0x00040000  /* Malformed TLP Stauts */\n+#define PCIE_ECRC_ERR                        0x00080000  /* ECRC Error Stauts */\n+#define PCIE_UR_REQ                          0x00100000  /* Unsupported Request Error Status */\n+#define PCIE_ALL_UNCORRECTABLE_ERR    (PCIE_DATA_LINK_PROTOCOL_ERR | PCIE_SURPRISE_DOWN_ERROR | \\\n+                         PCIE_POISONED_TLP | PCIE_FC_PROTOCOL_ERR | PCIE_COMPLETION_TIMEOUT |   \\\n+                         PCIE_COMPLETOR_ABORT | PCIE_UNEXPECTED_COMPLETION | PCIE_RECEIVER_OVERFLOW |\\\n+                         PCIE_MALFORNED_TLP | PCIE_ECRC_ERR | PCIE_UR_REQ)\n+\n+/* Uncorrectable Error Mask Register, Mask means no report */\n+#define PCIE_UEMR(X)                        (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x108)\n+\n+/* Uncorrectable Error Severity Register */\n+#define PCIE_UESR(X)                        (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x10C)\n+\n+/* Correctable Error Status Register */\n+#define PCIE_CESR(X)                        (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x110)\n+#define PCIE_RX_ERR                          0x00000001  /* Receive Error Status */\n+#define PCIE_BAD_TLP                         0x00000040  /* Bad TLP Status */\n+#define PCIE_BAD_DLLP                        0x00000080  /* Bad DLLP Status */\n+#define PCIE_REPLAY_NUM_ROLLOVER             0x00000100  /* Replay Number Rollover Status */\n+#define PCIE_REPLAY_TIMER_TIMEOUT_ERR        0x00001000  /* Reply Timer Timeout Status */\n+#define PCIE_ADVISORY_NONFTAL_ERR            0x00002000  /* Advisory Non-Fatal Error Status */\n+#define PCIE_CORRECTABLE_ERR        (PCIE_RX_ERR | PCIE_BAD_TLP | PCIE_BAD_DLLP | PCIE_REPLAY_NUM_ROLLOVER |\\\n+                                     PCIE_REPLAY_TIMER_TIMEOUT_ERR | PCIE_ADVISORY_NONFTAL_ERR)\n+\n+/* Correctable Error Mask Register */\n+#define PCIE_CEMR(X)                        (volatile u32*)(PCIE_RC_CFG_BASE + 0x114)\n+\n+/* Advanced Error Capabilities and Control Register */\n+#define PCIE_AECCR(X)                       (volatile u32*)(PCIE_RC_CFG_BASE + 0x118)\n+#define PCIE_AECCR_FIRST_ERR_PTR            0x0000001F  /* First Error Pointer */\n+#define PCIE_AECCR_FIRST_ERR_PTR_S          0\n+#define PCIE_AECCR_ECRC_GEN_CAP             0x00000020  /* ECRC Generation Capable */\n+#define PCIE_AECCR_ECRC_GEN_EN              0x00000040  /* ECRC Generation Enable */\n+#define PCIE_AECCR_ECRC_CHECK_CAP           0x00000080  /* ECRC Check Capable */\n+#define PCIE_AECCR_ECRC_CHECK_EN            0x00000100  /* ECRC Check Enable */\n+\n+/* Header Log Register 1 */\n+#define PCIE_HLR1(X)                        (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x11C)\n+\n+/* Header Log Register 2 */\n+#define PCIE_HLR2(X)                        (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x120)\n+\n+/* Header Log Register 3 */\n+#define PCIE_HLR3(X)                        (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x124)\n+\n+/* Header Log Register 4 */\n+#define PCIE_HLR4(X)                        (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x128)\n+\n+/* Root Error Command Register */\n+#define PCIE_RECR(X)                        (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x12C)\n+#define PCIE_RECR_CORRECTABLE_ERR_REPORT_EN  0x00000001 /* COR-ERR */\n+#define PCIE_RECR_NONFATAL_ERR_REPORT_EN     0x00000002 /* Non-Fatal ERR */\n+#define PCIE_RECR_FATAL_ERR_REPORT_EN        0x00000004 /* Fatal ERR */\n+#define PCIE_RECR_ERR_REPORT_EN  (PCIE_RECR_CORRECTABLE_ERR_REPORT_EN | \\\n+                PCIE_RECR_NONFATAL_ERR_REPORT_EN | PCIE_RECR_FATAL_ERR_REPORT_EN)\n+\n+/* Root Error Status Register */\n+#define PCIE_RESR(X)                            (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x130)\n+#define PCIE_RESR_CORRECTABLE_ERR                0x00000001   /* COR-ERR Receveid */\n+#define PCIE_RESR_MULTI_CORRECTABLE_ERR          0x00000002   /* Multiple COR-ERR Received */\n+#define PCIE_RESR_FATAL_NOFATAL_ERR              0x00000004   /* ERR Fatal/Non-Fatal Received */\n+#define PCIE_RESR_MULTI_FATAL_NOFATAL_ERR        0x00000008   /* Multiple ERR Fatal/Non-Fatal Received */\n+#define PCIE_RESR_FIRST_UNCORRECTABLE_FATAL_ERR  0x00000010   /* First UN-COR Fatal */\n+#define PCIR_RESR_NON_FATAL_ERR                  0x00000020   /* Non-Fatal Error Message Received */\n+#define PCIE_RESR_FATAL_ERR                      0x00000040   /* Fatal Message Received */\n+#define PCIE_RESR_AER_INT_MSG_NUM                0xF8000000   /* Advanced Error Interrupt Message Number */\n+#define PCIE_RESR_AER_INT_MSG_NUM_S              27\n+\n+/* Error Source Indentification Register */\n+#define PCIE_ESIR(X)                            (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x134)\n+#define PCIE_ESIR_CORRECTABLE_ERR_SRC_ID         0x0000FFFF\n+#define PCIE_ESIR_CORRECTABLE_ERR_SRC_ID_S       0\n+#define PCIE_ESIR_FATAL_NON_FATAL_SRC_ID         0xFFFF0000\n+#define PCIE_ESIR_FATAL_NON_FATAL_SRC_ID_S       16\n+\n+/* VC Enhanced Capability Header */\n+#define PCIE_VC_ECH(X)                          (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x140)\n+\n+/* Port VC Capability Register */\n+#define PCIE_PVC1(X)                            (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x144)\n+#define PCIE_PVC1_EXT_VC_CNT                    0x00000007  /* Extended VC Count */\n+#define PCIE_PVC1_EXT_VC_CNT_S                  0\n+#define PCIE_PVC1_LOW_PRI_EXT_VC_CNT            0x00000070  /* Low Priority Extended VC Count */\n+#define PCIE_PVC1_LOW_PRI_EXT_VC_CNT_S          4\n+#define PCIE_PVC1_REF_CLK                       0x00000300  /* Reference Clock */\n+#define PCIE_PVC1_REF_CLK_S                     8\n+#define PCIE_PVC1_PORT_ARB_TAB_ENTRY_SIZE       0x00000C00  /* Port Arbitration Table Entry Size */\n+#define PCIE_PVC1_PORT_ARB_TAB_ENTRY_SIZE_S     10\n+\n+/* Extended Virtual Channel Count Defintion */\n+#define PCIE_EXT_VC_CNT_MIN   0\n+#define PCIE_EXT_VC_CNT_MAX   7\n+\n+/* Port Arbitration Table Entry Size Definition */\n+enum {\n+    PCIE_PORT_ARB_TAB_ENTRY_SIZE_S1BIT = 0,\n+    PCIE_PORT_ARB_TAB_ENTRY_SIZE_S2BIT,\n+    PCIE_PORT_ARB_TAB_ENTRY_SIZE_S4BIT,\n+    PCIE_PORT_ARB_TAB_ENTRY_SIZE_S8BIT,\n+};\n+\n+/* Port VC Capability Register 2 */\n+#define PCIE_PVC2(X)                        (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x148)\n+#define PCIE_PVC2_VC_ARB_16P_FIXED_WRR      0x00000001  /* HW Fixed arbitration, 16 phase WRR */\n+#define PCIE_PVC2_VC_ARB_32P_WRR            0x00000002  /* 32 phase WRR */\n+#define PCIE_PVC2_VC_ARB_64P_WRR            0x00000004  /* 64 phase WRR */\n+#define PCIE_PVC2_VC_ARB_128P_WRR           0x00000008  /* 128 phase WRR */\n+#define PCIE_PVC2_VC_ARB_WRR                0x0000000F\n+#define PCIE_PVC2_VC_ARB_TAB_OFFSET         0xFF000000  /* VC arbitration table offset, not support */\n+#define PCIE_PVC2_VC_ARB_TAB_OFFSET_S       24\n+\n+/* Port VC Control and Status Register */     \n+#define PCIE_PVCCRSR(X)                     (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x14C)\n+#define PCIE_PVCCRSR_LOAD_VC_ARB_TAB         0x00000001  /* Load VC Arbitration Table */\n+#define PCIE_PVCCRSR_VC_ARB_SEL              0x0000000E  /* VC Arbitration Select */\n+#define PCIE_PVCCRSR_VC_ARB_SEL_S            1\n+#define PCIE_PVCCRSR_VC_ARB_TAB_STATUS       0x00010000  /* Arbitration Status */\n+\n+/* VC0 Resource Capability Register */\n+#define PCIE_VC0_RC(X)                       (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x150)\n+#define PCIE_VC0_RC_PORT_ARB_HW_FIXED        0x00000001  /* HW Fixed arbitration */\n+#define PCIE_VC0_RC_PORT_ARB_32P_WRR         0x00000002  /* 32 phase WRR */\n+#define PCIE_VC0_RC_PORT_ARB_64P_WRR         0x00000004  /* 64 phase WRR */\n+#define PCIE_VC0_RC_PORT_ARB_128P_WRR        0x00000008  /* 128 phase WRR */\n+#define PCIE_VC0_RC_PORT_ARB_TM_128P_WRR     0x00000010  /* Time-based 128 phase WRR */\n+#define PCIE_VC0_RC_PORT_ARB_TM_256P_WRR     0x00000020  /* Time-based 256 phase WRR */\n+#define PCIE_VC0_RC_PORT_ARB          (PCIE_VC0_RC_PORT_ARB_HW_FIXED | PCIE_VC0_RC_PORT_ARB_32P_WRR |\\\n+                        PCIE_VC0_RC_PORT_ARB_64P_WRR | PCIE_VC0_RC_PORT_ARB_128P_WRR | \\\n+                        PCIE_VC0_RC_PORT_ARB_TM_128P_WRR | PCIE_VC0_RC_PORT_ARB_TM_256P_WRR)\n+\n+#define PCIE_VC0_RC_REJECT_SNOOP             0x00008000  /* Reject Snoop Transactioin */\n+#define PCIE_VC0_RC_MAX_TIMESLOTS            0x007F0000  /* Maximum time Slots */\n+#define PCIE_VC0_RC_MAX_TIMESLOTS_S          16\n+#define PCIE_VC0_RC_PORT_ARB_TAB_OFFSET      0xFF000000  /* Port Arbitration Table Offset */\n+#define PCIE_VC0_RC_PORT_ARB_TAB_OFFSET_S    24\n+\n+/* VC0 Resource Control Register */\n+#define PCIE_VC0_RC0(X)                      (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x154)\n+#define PCIE_VC0_RC0_TVM0                    0x00000001  /* TC0 and VC0 */\n+#define PCIE_VC0_RC0_TVM1                    0x00000002  /* TC1 and VC1 */\n+#define PCIE_VC0_RC0_TVM2                    0x00000004  /* TC2 and VC2 */\n+#define PCIE_VC0_RC0_TVM3                    0x00000008  /* TC3 and VC3 */\n+#define PCIE_VC0_RC0_TVM4                    0x00000010  /* TC4 and VC4 */\n+#define PCIE_VC0_RC0_TVM5                    0x00000020  /* TC5 and VC5 */\n+#define PCIE_VC0_RC0_TVM6                    0x00000040  /* TC6 and VC6 */\n+#define PCIE_VC0_RC0_TVM7                    0x00000080  /* TC7 and VC7 */\n+#define PCIE_VC0_RC0_TC_VC                   0x000000FF  /* TC/VC mask */\n+\n+#define PCIE_VC0_RC0_LOAD_PORT_ARB_TAB       0x00010000  /* Load Port Arbitration Table */\n+#define PCIE_VC0_RC0_PORT_ARB_SEL            0x000E0000  /* Port Arbitration Select */\n+#define PCIE_VC0_RC0_PORT_ARB_SEL_S          17\n+#define PCIE_VC0_RC0_VC_ID                   0x07000000  /* VC ID */\n+#define PCIE_VC0_RC0_VC_ID_S                 24\n+#define PCIE_VC0_RC0_VC_EN                   0x80000000  /* VC Enable */\n+\n+/* VC0 Resource Status Register */\n+#define PCIE_VC0_RSR0(X)                     (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x158)\n+#define PCIE_VC0_RSR0_PORT_ARB_TAB_STATUS    0x00010000  /* Port Arbitration Table Status,not used */\n+#define PCIE_VC0_RSR0_VC_NEG_PENDING         0x00020000  /* VC Negotiation Pending */\n+\n+/* Ack Latency Timer and Replay Timer Register */\n+#define PCIE_ALTRT(X)                         (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x700)\n+#define PCIE_ALTRT_ROUND_TRIP_LATENCY_LIMIT   0x0000FFFF  /* Round Trip Latency Time Limit */\n+#define PCIE_ALTRT_ROUND_TRIP_LATENCY_LIMIT_S 0\n+#define PCIE_ALTRT_REPLAY_TIME_LIMIT          0xFFFF0000  /* Replay Time Limit */\n+#define PCIE_ALTRT_REPLAY_TIME_LIMIT_S        16\n+\n+/* Other Message Register */\n+#define PCIE_OMR(X)                          (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x704)\n+\n+/* Port Force Link Register */\n+#define PCIE_PFLR(X)                         (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x708)\n+#define PCIE_PFLR_LINK_NUM                   0x000000FF  /* Link Number */\n+#define PCIE_PFLR_LINK_NUM_S                 0\n+#define PCIE_PFLR_FORCE_LINK                 0x00008000  /* Force link */\n+#define PCIE_PFLR_LINK_STATE                 0x003F0000  /* Link State */\n+#define PCIE_PFLR_LINK_STATE_S               16\n+#define PCIE_PFLR_LOW_POWER_ENTRY_CNT        0xFF000000  /* Low Power Entrance Count, only for EP */\n+#define PCIE_PFLR_LOW_POWER_ENTRY_CNT_S      24\n+\n+/* Ack Frequency Register */\n+#define PCIE_AFR(X)                          (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x70C)\n+#define PCIE_AFR_AF                          0x000000FF  /* Ack Frequency */\n+#define PCIE_AFR_AF_S                        0\n+#define PCIE_AFR_FTS_NUM                     0x0000FF00  /* The number of Fast Training Sequence from L0S to L0 */\n+#define PCIE_AFR_FTS_NUM_S                   8\n+#define PCIE_AFR_COM_FTS_NUM                 0x00FF0000  /* N_FTS; when common clock is used*/\n+#define PCIE_AFR_COM_FTS_NUM_S               16\n+#define PCIE_AFR_L0S_ENTRY_LATENCY           0x07000000  /* L0s Entrance Latency */\n+#define PCIE_AFR_L0S_ENTRY_LATENCY_S         24\n+#define PCIE_AFR_L1_ENTRY_LATENCY            0x38000000  /* L1 Entrance Latency */\n+#define PCIE_AFR_L1_ENTRY_LATENCY_S          27\n+#define PCIE_AFR_FTS_NUM_DEFAULT             32\n+#define PCIE_AFR_L0S_ENTRY_LATENCY_DEFAULT   7\n+#define PCIE_AFR_L1_ENTRY_LATENCY_DEFAULT    5\n+\n+/* Port Link Control Register */\n+#define PCIE_PLCR(X)                         (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x710)\n+#define PCIE_PLCR_OTHER_MSG_REQ              0x00000001  /* Other Message Request */\n+#define PCIE_PLCR_SCRAMBLE_DISABLE           0x00000002  /* Scramble Disable */  \n+#define PCIE_PLCR_LOOPBACK_EN                0x00000004  /* Loopback Enable */\n+#define PCIE_PLCR_LTSSM_HOT_RST              0x00000008  /* Force LTSSM to the hot reset */\n+#define PCIE_PLCR_DLL_LINK_EN                0x00000020  /* Enable Link initialization */\n+#define PCIE_PLCR_FAST_LINK_SIM_EN           0x00000080  /* Sets all internal timers to fast mode for simulation purposes */\n+#define PCIE_PLCR_LINK_MODE                  0x003F0000  /* Link Mode Enable Mask */\n+#define PCIE_PLCR_LINK_MODE_S                16\n+#define PCIE_PLCR_CORRUPTED_CRC_EN           0x02000000  /* Enabled Corrupt CRC */\n+\n+/* Lane Skew Register */\n+#define PCIE_LSR(X)                          (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x714)\n+#define PCIE_LSR_LANE_SKEW_NUM               0x00FFFFFF  /* Insert Lane Skew for Transmit, not applicable */\n+#define PCIE_LSR_LANE_SKEW_NUM_S             0\n+#define PCIE_LSR_FC_DISABLE                  0x01000000  /* Disable of Flow Control */\n+#define PCIE_LSR_ACKNAK_DISABLE              0x02000000  /* Disable of Ack/Nak */\n+#define PCIE_LSR_LANE_DESKEW_DISABLE         0x80000000  /* Disable of Lane-to-Lane Skew */\n+\n+/* Symbol Number Register */\n+#define PCIE_SNR(X)                          (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x718)\n+#define PCIE_SNR_TS                          0x0000000F  /* Number of TS Symbol */\n+#define PCIE_SNR_TS_S                        0\n+#define PCIE_SNR_SKP                         0x00000700  /* Number of SKP Symbol */\n+#define PCIE_SNR_SKP_S                       8\n+#define PCIE_SNR_REPLAY_TIMER                0x0007C000  /* Timer Modifier for Replay Timer */\n+#define PCIE_SNR_REPLAY_TIMER_S              14\n+#define PCIE_SNR_ACKNAK_LATENCY_TIMER        0x00F80000  /* Timer Modifier for Ack/Nak Latency Timer */\n+#define PCIE_SNR_ACKNAK_LATENCY_TIMER_S      19\n+#define PCIE_SNR_FC_TIMER                    0x1F000000  /* Timer Modifier for Flow Control Watchdog Timer */\n+#define PCIE_SNR_FC_TIMER_S                  28\n+\n+/* Symbol Timer Register and Filter Mask Register 1 */\n+#define PCIE_STRFMR(X)                      (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x71C)\n+#define PCIE_STRFMR_SKP_INTERVAL            0x000007FF  /* SKP lnterval Value */\n+#define PCIE_STRFMR_SKP_INTERVAL_S          0\n+#define PCIE_STRFMR_FC_WDT_DISABLE          0x00008000  /* Disable of FC Watchdog Timer */\n+#define PCIE_STRFMR_TLP_FUNC_MISMATCH_OK    0x00010000  /* Mask Function Mismatch Filtering for Incoming Requests */\n+#define PCIE_STRFMR_POISONED_TLP_OK         0x00020000  /* Mask Poisoned TLP Filtering */\n+#define PCIE_STRFMR_BAR_MATCH_OK            0x00040000  /* Mask BAR Match Filtering */\n+#define PCIE_STRFMR_TYPE1_CFG_REQ_OK        0x00080000  /* Mask Type 1 Configuration Request Filtering */\n+#define PCIE_STRFMR_LOCKED_REQ_OK           0x00100000  /* Mask Locked Request Filtering */\n+#define PCIE_STRFMR_CPL_TAG_ERR_RULES_OK    0x00200000  /* Mask Tag Error Rules for Received Completions */\n+#define PCIE_STRFMR_CPL_REQUESTOR_ID_MISMATCH_OK 0x00400000  /* Mask Requester ID Mismatch Error for Received Completions */\n+#define PCIE_STRFMR_CPL_FUNC_MISMATCH_OK         0x00800000  /* Mask Function Mismatch Error for Received Completions */\n+#define PCIE_STRFMR_CPL_TC_MISMATCH_OK           0x01000000  /* Mask Traffic Class Mismatch Error for Received Completions */\n+#define PCIE_STRFMR_CPL_ATTR_MISMATCH_OK         0x02000000  /* Mask Attribute Mismatch Error for Received Completions */\n+#define PCIE_STRFMR_CPL_LENGTH_MISMATCH_OK       0x04000000  /* Mask Length Mismatch Error for Received Completions */\n+#define PCIE_STRFMR_TLP_ECRC_ERR_OK              0x08000000  /* Mask ECRC Error Filtering */\n+#define PCIE_STRFMR_CPL_TLP_ECRC_OK              0x10000000  /* Mask ECRC Error Filtering for Completions */\n+#define PCIE_STRFMR_RX_TLP_MSG_NO_DROP           0x20000000  /* Send Message TLPs */\n+#define PCIE_STRFMR_RX_IO_TRANS_ENABLE           0x40000000  /* Mask Filtering of received I/O Requests */\n+#define PCIE_STRFMR_RX_CFG_TRANS_ENABLE          0x80000000  /* Mask Filtering of Received Configuration Requests */\n+\n+#define PCIE_DEF_SKP_INTERVAL    700             /* 1180 ~1538 , 125MHz * 2, 250MHz * 1 */\n+\n+/* Filter Masker Register 2 */\n+#define PCIE_FMR2(X)                             (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x720)\n+#define PCIE_FMR2_VENDOR_MSG0_PASSED_TO_TRGT1    0x00000001  /* Mask RADM Filtering and Error Handling Rules */\n+#define PCIE_FMR2_VENDOR_MSG1_PASSED_TO_TRGT1    0x00000002  /* Mask RADM Filtering and Error Handling Rules */\n+\n+/* Debug Register 0 */\n+#define PCIE_DBR0(X)                              (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x728)\n+\n+/* Debug Register 1 */\n+#define PCIE_DBR1(X)                              (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x72C)\n+\n+/* Transmit Posted FC Credit Status Register */\n+#define PCIE_TPFCS(X)                             (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x730)\n+#define PCIE_TPFCS_TX_P_DATA_FC_CREDITS           0x00000FFF /* Transmit Posted Data FC Credits */\n+#define PCIE_TPFCS_TX_P_DATA_FC_CREDITS_S         0\n+#define PCIE_TPFCS_TX_P_HDR_FC_CREDITS            0x000FF000 /* Transmit Posted Header FC Credits */\n+#define PCIE_TPFCS_TX_P_HDR_FC_CREDITS_S          12\n+\n+/* Transmit Non-Posted FC Credit Status */\n+#define PCIE_TNPFCS(X)                            (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x734)\n+#define PCIE_TNPFCS_TX_NP_DATA_FC_CREDITS         0x00000FFF /* Transmit Non-Posted Data FC Credits */\n+#define PCIE_TNPFCS_TX_NP_DATA_FC_CREDITS_S       0\n+#define PCIE_TNPFCS_TX_NP_HDR_FC_CREDITS          0x000FF000 /* Transmit Non-Posted Header FC Credits */\n+#define PCIE_TNPFCS_TX_NP_HDR_FC_CREDITS_S        12\n+\n+/* Transmit Complete FC Credit Status Register */\n+#define PCIE_TCFCS(X)                             (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x738)\n+#define PCIE_TCFCS_TX_CPL_DATA_FC_CREDITS         0x00000FFF /* Transmit Completion Data FC Credits */\n+#define PCIE_TCFCS_TX_CPL_DATA_FC_CREDITS_S       0\n+#define PCIE_TCFCS_TX_CPL_HDR_FC_CREDITS          0x000FF000 /* Transmit Completion Header FC Credits */\n+#define PCIE_TCFCS_TX_CPL_HDR_FC_CREDITS_S        12\n+\n+/* Queue Status Register */\n+#define PCIE_QSR(X)                              (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x73C)\n+#define PCIE_QSR_WAIT_UPDATE_FC_DLL               0x00000001 /* Received TLP FC Credits Not Returned */\n+#define PCIE_QSR_TX_RETRY_BUF_NOT_EMPTY           0x00000002 /* Transmit Retry Buffer Not Empty */\n+#define PCIE_QSR_RX_QUEUE_NOT_EMPTY               0x00000004 /* Received Queue Not Empty */\n+\n+/* VC Transmit Arbitration Register 1 */\n+#define PCIE_VCTAR1(X)                          (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x740)\n+#define PCIE_VCTAR1_WRR_WEIGHT_VC0               0x000000FF /* WRR Weight for VC0 */\n+#define PCIE_VCTAR1_WRR_WEIGHT_VC1               0x0000FF00 /* WRR Weight for VC1 */\n+#define PCIE_VCTAR1_WRR_WEIGHT_VC2               0x00FF0000 /* WRR Weight for VC2 */\n+#define PCIE_VCTAR1_WRR_WEIGHT_VC3               0xFF000000 /* WRR Weight for VC3 */\n+\n+/* VC Transmit Arbitration Register 2 */\n+#define PCIE_VCTAR2(X)                          (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x744)\n+#define PCIE_VCTAR2_WRR_WEIGHT_VC4               0x000000FF /* WRR Weight for VC4 */\n+#define PCIE_VCTAR2_WRR_WEIGHT_VC5               0x0000FF00 /* WRR Weight for VC5 */\n+#define PCIE_VCTAR2_WRR_WEIGHT_VC6               0x00FF0000 /* WRR Weight for VC6 */\n+#define PCIE_VCTAR2_WRR_WEIGHT_VC7               0xFF000000 /* WRR Weight for VC7 */\n+\n+/* VC0 Posted Receive Queue Control Register */\n+#define PCIE_VC0_PRQCR(X)                       (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x748)\n+#define PCIE_VC0_PRQCR_P_DATA_CREDITS            0x00000FFF /* VC0 Posted Data Credits */\n+#define PCIE_VC0_PRQCR_P_DATA_CREDITS_S          0\n+#define PCIE_VC0_PRQCR_P_HDR_CREDITS             0x000FF000 /* VC0 Posted Header Credits */\n+#define PCIE_VC0_PRQCR_P_HDR_CREDITS_S           12\n+#define PCIE_VC0_PRQCR_P_TLP_QUEUE_MODE          0x00E00000 /* VC0 Posted TLP Queue Mode */\n+#define PCIE_VC0_PRQCR_P_TLP_QUEUE_MODE_S        20\n+#define PCIE_VC0_PRQCR_TLP_RELAX_ORDER           0x40000000 /* TLP Type Ordering for VC0 */    \n+#define PCIE_VC0_PRQCR_VC_STRICT_ORDER           0x80000000 /* VC0 Ordering for Receive Queues */\n+\n+/* VC0 Non-Posted Receive Queue Control */\n+#define PCIE_VC0_NPRQCR(X)                      (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x74C)\n+#define PCIE_VC0_NPRQCR_NP_DATA_CREDITS          0x00000FFF /* VC0 Non-Posted Data Credits */\n+#define PCIE_VC0_NPRQCR_NP_DATA_CREDITS_S        0\n+#define PCIE_VC0_NPRQCR_NP_HDR_CREDITS           0x000FF000 /* VC0 Non-Posted Header Credits */\n+#define PCIE_VC0_NPRQCR_NP_HDR_CREDITS_S         12\n+#define PCIE_VC0_NPRQCR_NP_TLP_QUEUE_MODE        0x00E00000 /* VC0 Non-Posted TLP Queue Mode */\n+#define PCIE_VC0_NPRQCR_NP_TLP_QUEUE_MODE_S      20\n+\n+/* VC0 Completion Receive Queue Control */\n+#define PCIE_VC0_CRQCR(X)                       (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x750)\n+#define PCIE_VC0_CRQCR_CPL_DATA_CREDITS          0x00000FFF /* VC0 Completion TLP Queue Mode */\n+#define PCIE_VC0_CRQCR_CPL_DATA_CREDITS_S        0\n+#define PCIE_VC0_CRQCR_CPL_HDR_CREDITS           0x000FF000 /* VC0 Completion Header Credits */\n+#define PCIE_VC0_CRQCR_CPL_HDR_CREDITS_S         12\n+#define PCIE_VC0_CRQCR_CPL_TLP_QUEUE_MODE        0x00E00000 /* VC0 Completion Data Credits */\n+#define PCIE_VC0_CRQCR_CPL_TLP_QUEUE_MODE_S      21\n+\n+/* Applicable to the above three registers */\n+enum {\n+    PCIE_VC0_TLP_QUEUE_MODE_STORE_FORWARD = 1,\n+    PCIE_VC0_TLP_QUEUE_MODE_CUT_THROUGH   = 2,\n+    PCIE_VC0_TLP_QUEUE_MODE_BYPASS        = 4,\n+};\n+\n+/* VC0 Posted Buffer Depth Register */\n+#define PCIE_VC0_PBD(X)                        (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7A8)\n+#define PCIE_VC0_PBD_P_DATA_QUEUE_ENTRIES       0x00003FFF /* VC0 Posted Data Queue Depth */\n+#define PCIE_VC0_PBD_P_DATA_QUEUE_ENTRIES_S     0\n+#define PCIE_VC0_PBD_P_HDR_QUEUE_ENTRIES        0x03FF0000 /* VC0 Posted Header Queue Depth */\n+#define PCIE_VC0_PBD_P_HDR_QUEUE_ENTRIES_S      16\n+\n+/* VC0 Non-Posted Buffer Depth Register */\n+#define PCIE_VC0_NPBD(X)                       (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7AC)\n+#define PCIE_VC0_NPBD_NP_DATA_QUEUE_ENTRIES     0x00003FFF /* VC0 Non-Posted Data Queue Depth */\n+#define PCIE_VC0_NPBD_NP_DATA_QUEUE_ENTRIES_S   0\n+#define PCIE_VC0_NPBD_NP_HDR_QUEUE_ENTRIES      0x03FF0000 /* VC0 Non-Posted Header Queue Depth */\n+#define PCIE_VC0_NPBD_NP_HDR_QUEUE_ENTRIES_S    16\n+\n+/* VC0 Completion Buffer Depth Register */\n+#define PCIE_VC0_CBD(X)                        (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7B0)\n+#define PCIE_VC0_CBD_CPL_DATA_QUEUE_ENTRIES     0x00003FFF /* C0 Completion Data Queue Depth */\n+#define PCIE_VC0_CBD_CPL_DATA_QUEUE_ENTRIES_S   0\n+#define PCIE_VC0_CBD_CPL_HDR_QUEUE_ENTRIES      0x03FF0000 /* VC0 Completion Header Queue Depth */\n+#define PCIE_VC0_CBD_CPL_HDR_QUEUE_ENTRIES_S    16\n+\n+/* PHY Status Register, all zeros in VR9 */\n+#define PCIE_PHYSR(X)                           (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x810)\n+\n+/* PHY Control Register, all zeros in VR9 */\n+#define PCIE_PHYCR(X)                           (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x814)\n+\n+/* \n+ * PCIe PDI PHY register definition, suppose all the following \n+ * stuff is confidential. \n+ * XXX, detailed bit definition\n+ */\n+#define\tPCIE_PHY_PLL_CTRL1(X)       (PCIE_PHY_PORT_TO_BASE(X) + (0x22 << 1))\n+#define\tPCIE_PHY_PLL_CTRL2(X)       (PCIE_PHY_PORT_TO_BASE(X) + (0x23 << 1))\n+#define\tPCIE_PHY_PLL_CTRL3(X)       (PCIE_PHY_PORT_TO_BASE(X) + (0x24 << 1))\n+#define\tPCIE_PHY_PLL_CTRL4(X)       (PCIE_PHY_PORT_TO_BASE(X) + (0x25 << 1))\n+#define\tPCIE_PHY_PLL_CTRL5(X)       (PCIE_PHY_PORT_TO_BASE(X) + (0x26 << 1))\n+#define\tPCIE_PHY_PLL_CTRL6(X)       (PCIE_PHY_PORT_TO_BASE(X) + (0x27 << 1))\n+#define\tPCIE_PHY_PLL_CTRL7(X)       (PCIE_PHY_PORT_TO_BASE(X) + (0x28 << 1))\n+#define\tPCIE_PHY_PLL_A_CTRL1(X)     (PCIE_PHY_PORT_TO_BASE(X) + (0x29 << 1))\n+#define\tPCIE_PHY_PLL_A_CTRL2(X)     (PCIE_PHY_PORT_TO_BASE(X) + (0x2A << 1))\n+#define\tPCIE_PHY_PLL_A_CTRL3(X)     (PCIE_PHY_PORT_TO_BASE(X) + (0x2B << 1))\n+#define\tPCIE_PHY_PLL_STATUS(X)      (PCIE_PHY_PORT_TO_BASE(X) + (0x2C << 1))\n+ \n+#define PCIE_PHY_TX1_CTRL1(X)       (PCIE_PHY_PORT_TO_BASE(X) + (0x30 << 1))\n+#define PCIE_PHY_TX1_CTRL2(X)       (PCIE_PHY_PORT_TO_BASE(X) + (0x31 << 1))\n+#define PCIE_PHY_TX1_CTRL3(X)       (PCIE_PHY_PORT_TO_BASE(X) + (0x32 << 1))\n+#define PCIE_PHY_TX1_A_CTRL1(X)     (PCIE_PHY_PORT_TO_BASE(X) + (0x33 << 1))\n+#define PCIE_PHY_TX1_A_CTRL2(X)     (PCIE_PHY_PORT_TO_BASE(X) + (0x34 << 1))\n+#define PCIE_PHY_TX1_MOD1(X)        (PCIE_PHY_PORT_TO_BASE(X) + (0x35 << 1))\n+#define PCIE_PHY_TX1_MOD2(X)        (PCIE_PHY_PORT_TO_BASE(X) + (0x36 << 1))\n+#define PCIE_PHY_TX1_MOD3(X)        (PCIE_PHY_PORT_TO_BASE(X) + (0x37 << 1))\n+\n+#define PCIE_PHY_TX2_CTRL1(X)       (PCIE_PHY_PORT_TO_BASE(X) + (0x38 << 1))\n+#define PCIE_PHY_TX2_CTRL2(X)       (PCIE_PHY_PORT_TO_BASE(X) + (0x39 << 1))\n+#define PCIE_PHY_TX2_A_CTRL1(X)     (PCIE_PHY_PORT_TO_BASE(X) + (0x3B << 1))\n+#define PCIE_PHY_TX2_A_CTRL2(X)     (PCIE_PHY_PORT_TO_BASE(X) + (0x3C << 1))\n+#define PCIE_PHY_TX2_MOD1(X)        (PCIE_PHY_PORT_TO_BASE(X) + (0x3D << 1))\n+#define PCIE_PHY_TX2_MOD2(X)        (PCIE_PHY_PORT_TO_BASE(X) + (0x3E << 1))\n+#define PCIE_PHY_TX2_MOD3(X)        (PCIE_PHY_PORT_TO_BASE(X) + (0x3F << 1))\n+\n+#define PCIE_PHY_RX1_CTRL1(X)       (PCIE_PHY_PORT_TO_BASE(X) + (0x50 << 1))\n+#define PCIE_PHY_RX1_CTRL2(X)       (PCIE_PHY_PORT_TO_BASE(X) + (0x51 << 1))\n+#define PCIE_PHY_RX1_CDR(X)         (PCIE_PHY_PORT_TO_BASE(X) + (0x52 << 1))\n+#define PCIE_PHY_RX1_EI(X)          (PCIE_PHY_PORT_TO_BASE(X) + (0x53 << 1))\n+#define PCIE_PHY_RX1_A_CTRL(X)      (PCIE_PHY_PORT_TO_BASE(X) + (0x55 << 1))\n+\n+/* Interrupt related stuff */\n+#define PCIE_LEGACY_DISABLE 0\n+#define PCIE_LEGACY_INTA  1\n+#define PCIE_LEGACY_INTB  2\n+#define PCIE_LEGACY_INTC  3\n+#define PCIE_LEGACY_INTD  4\n+#define PCIE_LEGACY_INT_MAX PCIE_LEGACY_INTD\n+\n+#define PCIE_IRQ_LOCK(lock) do {             \\\n+    unsigned long flags;                     \\\n+    spin_lock_irqsave(&(lock), flags);\n+#define PCIE_IRQ_UNLOCK(lock)                \\\n+    spin_unlock_irqrestore(&(lock), flags);  \\\n+} while (0)\n+\n+#define PCIE_MSG_MSI        0x00000001\n+#define PCIE_MSG_ISR        0x00000002\n+#define PCIE_MSG_FIXUP      0x00000004\n+#define PCIE_MSG_READ_CFG   0x00000008\n+#define PCIE_MSG_WRITE_CFG  0x00000010\n+#define PCIE_MSG_CFG        (PCIE_MSG_READ_CFG | PCIE_MSG_WRITE_CFG)\n+#define PCIE_MSG_REG        0x00000020\n+#define PCIE_MSG_INIT       0x00000040\n+#define PCIE_MSG_ERR        0x00000080\n+#define PCIE_MSG_PHY        0x00000100\n+#define PCIE_MSG_ANY        0x000001ff\n+\n+#define IFX_PCIE_PORT0      0\n+#define IFX_PCIE_PORT1      1\n+\n+#ifdef CONFIG_IFX_PCIE_2ND_CORE\n+#define IFX_PCIE_CORE_NR    2\n+#else\n+#define IFX_PCIE_CORE_NR    1\n+#endif\n+\n+//#define IFX_PCIE_ERROR_INT\n+\n+//#define IFX_PCIE_DBG\n+\n+#if defined(IFX_PCIE_DBG)\n+#define IFX_PCIE_PRINT(_m, _fmt, args...) do {   \\\n+    if (g_pcie_debug_flag & (_m)) {              \\\n+        ifx_pcie_debug((_fmt), ##args);          \\\n+    }                                            \\\n+} while (0)\n+\n+#define INLINE \n+#else\n+#define IFX_PCIE_PRINT(_m, _fmt, args...)   \\\n+    do {} while(0)\n+#define INLINE inline\n+#endif\n+\n+struct ifx_pci_controller {\n+\tstruct pci_controller   pcic;\n+    \n+\t/* RC specific, per host bus information */\n+\tu32   port;  /* Port index, 0 -- 1st core, 1 -- 2nd core */\n+};\n+\n+typedef struct ifx_pcie_ir_irq {\n+    const unsigned int irq;\n+    const char name[16];\n+}ifx_pcie_ir_irq_t;\n+\n+typedef struct ifx_pcie_legacy_irq{\n+    const u32 irq_bit;\n+    const int irq;\n+}ifx_pcie_legacy_irq_t;\n+\n+typedef struct ifx_pcie_irq {\n+    ifx_pcie_ir_irq_t ir_irq;\n+    ifx_pcie_legacy_irq_t legacy_irq[PCIE_LEGACY_INT_MAX];\n+}ifx_pcie_irq_t;\n+\n+extern u32 g_pcie_debug_flag;\n+extern void ifx_pcie_debug(const char *fmt, ...);\n+extern void pcie_phy_clock_mode_setup(int pcie_port);\n+extern void pcie_msi_pic_init(int pcie_port);\n+extern u32 ifx_pcie_bus_enum_read_hack(int where, u32 value);\n+extern u32 ifx_pcie_bus_enum_write_hack(int where, u32 value);\n+\n+\n+#include <linux/types.h>\n+#include <linux/delay.h>\n+#include <linux/gpio.h>\n+#include <linux/clk.h>\n+\n+#include <lantiq_soc.h>\n+\n+#define IFX_PCIE_GPIO_RESET  38\n+#define IFX_REG_R32\tltq_r32\n+#define IFX_REG_W32\tltq_w32\n+#define CONFIG_IFX_PCIE_HW_SWAP\n+#define IFX_RCU_AHB_ENDIAN                      ((volatile u32*)(IFX_RCU + 0x004C))\n+#define IFX_RCU_RST_REQ                         ((volatile u32*)(IFX_RCU + 0x0010))\n+#define IFX_RCU_AHB_BE_PCIE_PDI                  0x00000080  /* Configure PCIE PDI module in big endian*/\n+\n+#define IFX_RCU                                 (KSEG1 | 0x1F203000)\n+#define IFX_RCU_AHB_BE_PCIE_M                    0x00000001  /* Configure AHB master port that connects to PCIe RC in big endian */\n+#define IFX_RCU_AHB_BE_PCIE_S                    0x00000010  /* Configure AHB slave port that connects to PCIe RC in little endian */\n+#define IFX_RCU_AHB_BE_XBAR_M                    0x00000002  /* Configure AHB master port that connects to XBAR in big endian */\n+#define CONFIG_IFX_PCIE_PHY_36MHZ_MODE\n+\n+#define IFX_PMU1_MODULE_PCIE_PHY   (0)\n+#define IFX_PMU1_MODULE_PCIE_CTRL  (1)\n+#define IFX_PMU1_MODULE_PDI        (4)\n+#define IFX_PMU1_MODULE_MSI        (5)\n+\n+#define IFX_PMU_MODULE_PCIE_L0_CLK (31)\n+\n+\n+static inline void pcie_ep_gpio_rst_init(int pcie_port)\n+{\n+}\n+\n+static inline void pcie_ahb_pmu_setup(void)\n+{\n+\tstruct clk *clk;\n+\tclk = clk_get_sys(\"ltq_pcie\", \"ahb\");\n+\tclk_enable(clk);\n+\t//ltq_pmu_enable(PMU_AHBM | PMU_AHBS);\n+}\n+\n+static inline void pcie_rcu_endian_setup(int pcie_port)\n+{\n+    u32 reg;\n+\n+    reg = IFX_REG_R32(IFX_RCU_AHB_ENDIAN);\n+#ifdef CONFIG_IFX_PCIE_HW_SWAP\n+    reg |= IFX_RCU_AHB_BE_PCIE_M;\n+    reg |= IFX_RCU_AHB_BE_PCIE_S;\n+    reg &= ~IFX_RCU_AHB_BE_XBAR_M;\n+#else \n+    reg |= IFX_RCU_AHB_BE_PCIE_M;\n+    reg &= ~IFX_RCU_AHB_BE_PCIE_S;\n+    reg &= ~IFX_RCU_AHB_BE_XBAR_M;\n+#endif /* CONFIG_IFX_PCIE_HW_SWAP */\n+    IFX_REG_W32(reg, IFX_RCU_AHB_ENDIAN);\n+    IFX_PCIE_PRINT(PCIE_MSG_REG, \"%s IFX_RCU_AHB_ENDIAN: 0x%08x\\n\", __func__, IFX_REG_R32(IFX_RCU_AHB_ENDIAN));\n+}\n+\n+static inline void pcie_phy_pmu_enable(int pcie_port)\n+{\n+\tstruct clk *clk;\n+\tclk = clk_get_sys(\"ltq_pcie\", \"phy\");\n+\tclk_enable(clk);\n+\t//ltq_pmu1_enable(1<<IFX_PMU1_MODULE_PCIE_PHY);\n+}\n+\n+static inline void pcie_phy_pmu_disable(int pcie_port)\n+{\n+\tstruct clk *clk;\n+\tclk = clk_get_sys(\"ltq_pcie\", \"phy\");\n+\tclk_disable(clk);\n+\t//ltq_pmu1_disable(1<<IFX_PMU1_MODULE_PCIE_PHY);\n+}\n+\n+static inline void pcie_pdi_big_endian(int pcie_port)\n+{\n+    u32 reg;\n+\n+    /* SRAM2PDI endianness control. */\n+    reg = IFX_REG_R32(IFX_RCU_AHB_ENDIAN);\n+    /* Config AHB->PCIe and PDI endianness */\n+    reg |= IFX_RCU_AHB_BE_PCIE_PDI;\n+    IFX_REG_W32(reg, IFX_RCU_AHB_ENDIAN);\n+}\n+\n+static inline void pcie_pdi_pmu_enable(int pcie_port)\n+{\n+\tstruct clk *clk;\n+\tclk = clk_get_sys(\"ltq_pcie\", \"pdi\");\n+\tclk_enable(clk);\n+\t//ltq_pmu1_enable(1<<IFX_PMU1_MODULE_PDI);\n+}\n+\n+static inline void pcie_core_rst_assert(int pcie_port)\n+{\n+    u32 reg;\n+\n+    reg = IFX_REG_R32(IFX_RCU_RST_REQ);\n+\n+    /* Reset PCIe PHY & Core, bit 22, bit 26 may be affected if write it directly  */\n+    reg |= 0x00400000;\n+    IFX_REG_W32(reg, IFX_RCU_RST_REQ);\n+}\n+\n+static inline void pcie_core_rst_deassert(int pcie_port)\n+{\n+    u32 reg;\n+\n+    /* Make sure one micro-second delay */\n+    udelay(1);\n+\n+    /* Reset PCIe PHY & Core, bit 22 */\n+    reg = IFX_REG_R32(IFX_RCU_RST_REQ);\n+    reg &= ~0x00400000;\n+    IFX_REG_W32(reg, IFX_RCU_RST_REQ);\n+}\n+\n+static inline void pcie_phy_rst_assert(int pcie_port)\n+{\n+    u32 reg;\n+\n+    reg = IFX_REG_R32(IFX_RCU_RST_REQ);\n+    reg |= 0x00001000; /* Bit 12 */\n+    IFX_REG_W32(reg, IFX_RCU_RST_REQ);\n+}\n+\n+static inline void pcie_phy_rst_deassert(int pcie_port)\n+{\n+    u32 reg;\n+\n+    /* Make sure one micro-second delay */\n+    udelay(1);\n+\n+    reg = IFX_REG_R32(IFX_RCU_RST_REQ);\n+    reg &= ~0x00001000; /* Bit 12 */\n+    IFX_REG_W32(reg, IFX_RCU_RST_REQ);\n+}\n+\n+static inline void pcie_device_rst_assert(int pcie_port)\n+{\n+\tgpio_set_value(IFX_PCIE_GPIO_RESET, 0);\n+  //  ifx_gpio_output_clear(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);\n+}\n+\n+static inline void pcie_device_rst_deassert(int pcie_port)\n+{\n+    mdelay(100);\n+\tgpio_set_value(IFX_PCIE_GPIO_RESET, 1);\n+//    ifx_gpio_output_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);\n+}\n+\n+static inline void pcie_core_pmu_setup(int pcie_port)\n+{\n+\tstruct clk *clk;\n+\tclk = clk_get_sys(\"ltq_pcie\", \"ctl\");\n+\tclk_enable(clk);\n+\tclk = clk_get_sys(\"ltq_pcie\", \"bus\");\n+\tclk_enable(clk);\n+\n+\t//ltq_pmu1_enable(1 << IFX_PMU1_MODULE_PCIE_CTRL);\n+\t//ltq_pmu_enable(1 << IFX_PMU_MODULE_PCIE_L0_CLK);\n+}\n+\n+static inline void pcie_msi_init(int pcie_port)\n+{\n+\tstruct clk *clk;\n+    pcie_msi_pic_init(pcie_port);\n+\tclk = clk_get_sys(\"ltq_pcie\", \"msi\");\n+\tclk_enable(clk);\n+\t//ltq_pmu1_enable(1 << IFX_PMU1_MODULE_MSI);\n+}\n+\n+static inline u32\n+ifx_pcie_bus_nr_deduct(u32 bus_number, int pcie_port)\n+{\n+    u32 tbus_number = bus_number;\n+\n+#ifdef CONFIG_PCI_LANTIQ\n+    if (pcibios_host_nr() > 1) {\n+        tbus_number -= pcibios_1st_host_bus_nr();\n+    }\n+#endif /* CONFIG_PCI_LANTIQ */\n+    return tbus_number;\n+}\n+\n+static inline u32\n+ifx_pcie_bus_enum_hack(struct pci_bus *bus, u32 devfn, int where, u32 value, int pcie_port, int read)\n+{\n+    struct pci_dev *pdev;\n+    u32 tvalue = value;\n+\n+    /* Sanity check */\n+    pdev = pci_get_slot(bus, devfn);\n+    if (pdev == NULL) {\n+        return tvalue;\n+    }\n+\n+    /* Only care about PCI bridge */\n+    if (pdev->hdr_type != PCI_HEADER_TYPE_BRIDGE) {\n+        return tvalue;\n+    }\n+\n+    if (read) { /* Read hack */\n+    #ifdef CONFIG_PCI_LANTIQ\n+        if (pcibios_host_nr() > 1) {\n+            tvalue = ifx_pcie_bus_enum_read_hack(where, tvalue);\n+        }\n+    #endif /* CONFIG_PCI_LANTIQ */\n+    }\n+    else { /* Write hack */\n+    #ifdef CONFIG_PCI_LANTIQ\n+        if (pcibios_host_nr() > 1) {\n+            tvalue = ifx_pcie_bus_enum_write_hack(where, tvalue);\n+        }\n+    #endif\n+    }\n+    return tvalue;\n+}\n+\n+#endif /* IFXMIPS_PCIE_VR9_H */\n+\n--- a/drivers/pci/pcie/Kconfig\n+++ b/drivers/pci/pcie/Kconfig\n@@ -51,6 +51,7 @@ config PCIEAER_INJECT\n config PCIE_ECRC\n \tbool \"PCI Express ECRC settings control\"\n \tdepends on PCIEAER\n+\tdefault n\n \thelp\n \t  Used to override firmware/bios settings for PCI Express ECRC\n \t  (transaction layer end-to-end CRC checking).\n--- a/include/linux/pci.h\n+++ b/include/linux/pci.h\n@@ -1420,6 +1420,8 @@ void pci_walk_bus(struct pci_bus *top, i\n \t\t  void *userdata);\n int pci_cfg_space_size(struct pci_dev *dev);\n unsigned char pci_bus_max_busnr(struct pci_bus *bus);\n+int pcibios_host_nr(void);\n+int pcibios_1st_host_bus_nr(void);\n void pci_setup_bridge(struct pci_bus *bus);\n resource_size_t pcibios_window_alignment(struct pci_bus *bus,\n \t\t\t\t\t unsigned long type);\n--- a/include/linux/pci_ids.h\n+++ b/include/linux/pci_ids.h\n@@ -1076,6 +1076,12 @@\n #define PCI_DEVICE_ID_SGI_IOC3\t\t0x0003\n #define PCI_DEVICE_ID_SGI_LITHIUM\t0x1002\n \n+#define PCI_VENDOR_ID_INFINEON\t\t0x15D1\n+#define PCI_DEVICE_ID_INFINEON_DANUBE\t0x000F\n+#define PCI_DEVICE_ID_INFINEON_PCIE\t0x0011\n+#define PCI_VENDOR_ID_LANTIQ\t\t0x1BEF\n+#define PCI_DEVICE_ID_LANTIQ_PCIE\t0x0011\n+\n #define PCI_VENDOR_ID_WINBOND\t\t0x10ad\n #define PCI_DEVICE_ID_WINBOND_82C105\t0x0105\n #define PCI_DEVICE_ID_WINBOND_83C553\t0x0565\n"
  },
  {
    "path": "target/linux/lantiq/patches-5.10/0004-MIPS-lantiq-add-atm-hack.patch",
    "content": "From 9afadf01b1be371ee88491819aa67364684461f9 Mon Sep 17 00:00:00 2001\nFrom: John Crispin <blogic@openwrt.org>\nDate: Fri, 3 Aug 2012 10:27:25 +0200\nSubject: [PATCH 04/36] MIPS: lantiq: add atm hack\n\nSigned-off-by: John Crispin <blogic@openwrt.org>\n---\n arch/mips/include/asm/mach-lantiq/lantiq_atm.h |  196 +++++++++++++++++++++++\n arch/mips/include/asm/mach-lantiq/lantiq_ptm.h |  203 ++++++++++++++++++++++++\n arch/mips/lantiq/irq.c                         |    2 +\n arch/mips/mm/cache.c                           |    4 +\n include/uapi/linux/atm.h                       |    6 +\n net/atm/common.c                               |    6 +\n net/atm/proc.c                                 |    2 +-\n 7 files changed, 416 insertions(+), 1 deletion(-)\n create mode 100644 arch/mips/include/asm/mach-lantiq/lantiq_atm.h\n create mode 100644 arch/mips/include/asm/mach-lantiq/lantiq_ptm.h\n\n--- /dev/null\n+++ b/arch/mips/include/asm/mach-lantiq/lantiq_atm.h\n@@ -0,0 +1,196 @@\n+/******************************************************************************\n+**\n+** FILE NAME    : ifx_atm.h\n+** PROJECT      : UEIP\n+** MODULES      : ATM\n+**\n+** DATE         : 17 Jun 2009\n+** AUTHOR       : Xu Liang\n+** DESCRIPTION  : Global ATM driver header file\n+** COPYRIGHT    :       Copyright (c) 2006\n+**                      Infineon Technologies AG\n+**                      Am Campeon 1-12, 85579 Neubiberg, Germany\n+**\n+**    This program is free software; you can redistribute it and/or modify\n+**    it under the terms of the GNU General Public License as published by\n+**    the Free Software Foundation; either version 2 of the License, or\n+**    (at your option) any later version.\n+**\n+** HISTORY\n+** $Date        $Author         $Comment\n+** 07 JUL 2009  Xu Liang        Init Version\n+*******************************************************************************/\n+\n+#ifndef IFX_ATM_H\n+#define IFX_ATM_H\n+\n+\n+\n+/*!\n+  \\defgroup IFX_ATM UEIP Project - ATM driver module\n+  \\brief UEIP Project - ATM driver module, support Danube, Amazon-SE, AR9, VR9.\n+ */\n+\n+/*!\n+  \\defgroup IFX_ATM_IOCTL IOCTL Commands\n+  \\ingroup IFX_ATM\n+  \\brief IOCTL Commands used by user application.\n+ */\n+\n+/*!\n+  \\defgroup IFX_ATM_STRUCT Structures\n+  \\ingroup IFX_ATM\n+  \\brief Structures used by user application.\n+ */\n+\n+/*!\n+  \\file ifx_atm.h\n+  \\ingroup IFX_ATM\n+  \\brief ATM driver header file\n+ */\n+\n+\n+\n+/*\n+ * ####################################\n+ *              Definition\n+ * ####################################\n+ */\n+\n+/*!\n+  \\addtogroup IFX_ATM_STRUCT\n+ */\n+/*@{*/\n+\n+/*\n+ *  ATM MIB\n+ */\n+\n+/*!\n+  \\struct atm_cell_ifEntry_t\n+  \\brief Structure used for Cell Level MIB Counters.\n+\n+  User application use this structure to call IOCTL command \"PPE_ATM_MIB_CELL\".\n+ */\n+typedef struct {\n+\t__u32\tifHCInOctets_h;     /*!< byte counter of ingress cells (upper 32 bits, total 64 bits)   */\n+\t__u32\tifHCInOctets_l;     /*!< byte counter of ingress cells (lower 32 bits, total 64 bits)   */\n+\t__u32\tifHCOutOctets_h;    /*!< byte counter of egress cells (upper 32 bits, total 64 bits)    */\n+\t__u32\tifHCOutOctets_l;    /*!< byte counter of egress cells (lower 32 bits, total 64 bits)    */\n+\t__u32\tifInErrors;         /*!< counter of error ingress cells     */\n+\t__u32\tifInUnknownProtos;  /*!< counter of unknown ingress cells   */\n+\t__u32\tifOutErrors;        /*!< counter of error egress cells      */\n+} atm_cell_ifEntry_t;\n+\n+/*!\n+  \\struct atm_aal5_ifEntry_t\n+  \\brief Structure used for AAL5 Frame Level MIB Counters.\n+\n+  User application use this structure to call IOCTL command \"PPE_ATM_MIB_AAL5\".\n+ */\n+typedef struct {\n+\t__u32\tifHCInOctets_h;     /*!< byte counter of ingress packets (upper 32 bits, total 64 bits) */\n+\t__u32\tifHCInOctets_l;     /*!< byte counter of ingress packets (lower 32 bits, total 64 bits) */\n+\t__u32\tifHCOutOctets_h;    /*!< byte counter of egress packets (upper 32 bits, total 64 bits)  */\n+\t__u32\tifHCOutOctets_l;    /*!< byte counter of egress packets (lower 32 bits, total 64 bits)  */\n+\t__u32\tifInUcastPkts;      /*!< counter of ingress packets         */\n+\t__u32\tifOutUcastPkts;     /*!< counter of egress packets          */\n+\t__u32\tifInErrors;         /*!< counter of error ingress packets   */\n+\t__u32\tifInDiscards;       /*!< counter of dropped ingress packets */\n+\t__u32\tifOutErros;         /*!< counter of error egress packets    */\n+\t__u32\tifOutDiscards;      /*!< counter of dropped egress packets  */\n+} atm_aal5_ifEntry_t;\n+\n+/*!\n+  \\struct atm_aal5_vcc_t\n+  \\brief Structure used for per PVC AAL5 Frame Level MIB Counters.\n+\n+  This structure is a part of structure \"atm_aal5_vcc_x_t\".\n+ */\n+typedef struct {\n+\t__u32\taal5VccCrcErrors;       /*!< counter of ingress packets with CRC error  */\n+\t__u32\taal5VccSarTimeOuts;     /*!< counter of ingress packets with Re-assemble timeout    */  //no timer support yet\n+\t__u32\taal5VccOverSizedSDUs;   /*!< counter of oversized ingress packets       */\n+} atm_aal5_vcc_t;\n+\n+/*!\n+  \\struct atm_aal5_vcc_x_t\n+  \\brief Structure used for per PVC AAL5 Frame Level MIB Counters.\n+\n+  User application use this structure to call IOCTL command \"PPE_ATM_MIB_VCC\".\n+ */\n+typedef struct {\n+\tint             vpi;        /*!< VPI of the VCC to get MIB counters */\n+\tint             vci;        /*!< VCI of the VCC to get MIB counters */\n+\tatm_aal5_vcc_t  mib_vcc;    /*!< structure to get MIB counters      */\n+} atm_aal5_vcc_x_t;\n+\n+/*@}*/\n+\n+\n+\n+/*\n+ * ####################################\n+ *                IOCTL\n+ * ####################################\n+ */\n+\n+/*!\n+  \\addtogroup IFX_ATM_IOCTL\n+ */\n+/*@{*/\n+\n+/*\n+ *  ioctl Command\n+ */\n+/*!\n+  \\brief ATM IOCTL Magic Number\n+ */\n+#define PPE_ATM_IOC_MAGIC       'o'\n+/*!\n+  \\brief ATM IOCTL Command - Get Cell Level MIB Counters\n+\n+   This command is obsolete. User can get cell level MIB from DSL API.\n+   This command uses structure \"atm_cell_ifEntry_t\" as parameter for output of MIB counters.\n+ */\n+#define PPE_ATM_MIB_CELL        _IOW(PPE_ATM_IOC_MAGIC,  0, atm_cell_ifEntry_t)\n+/*!\n+  \\brief ATM IOCTL Command - Get AAL5 Level MIB Counters\n+\n+   Get AAL5 packet counters.\n+   This command uses structure \"atm_aal5_ifEntry_t\" as parameter for output of MIB counters.\n+ */\n+#define PPE_ATM_MIB_AAL5        _IOW(PPE_ATM_IOC_MAGIC,  1, atm_aal5_ifEntry_t)\n+/*!\n+  \\brief ATM IOCTL Command - Get Per PVC MIB Counters\n+\n+   Get AAL5 packet counters for each PVC.\n+   This command uses structure \"atm_aal5_vcc_x_t\" as parameter for input of VPI/VCI information and output of MIB counters.\n+ */\n+#define PPE_ATM_MIB_VCC         _IOWR(PPE_ATM_IOC_MAGIC, 2, atm_aal5_vcc_x_t)\n+/*!\n+  \\brief Total Number of ATM IOCTL Commands\n+ */\n+#define PPE_ATM_IOC_MAXNR       3\n+\n+/*@}*/\n+\n+\n+\n+/*\n+ * ####################################\n+ *                 API\n+ * ####################################\n+ */\n+\n+#ifdef __KERNEL__\n+struct port_cell_info {\n+    unsigned int    port_num;\n+    unsigned int    tx_link_rate[2];\n+};\n+#endif\n+\n+\n+\n+#endif  //  IFX_ATM_H\n+\n--- /dev/null\n+++ b/arch/mips/include/asm/mach-lantiq/lantiq_ptm.h\n@@ -0,0 +1,203 @@\n+/******************************************************************************\n+**\n+** FILE NAME    : ifx_ptm.h\n+** PROJECT      : UEIP\n+** MODULES      : PTM\n+**\n+** DATE         : 17 Jun 2009\n+** AUTHOR       : Xu Liang\n+** DESCRIPTION  : Global PTM driver header file\n+** COPYRIGHT    :       Copyright (c) 2006\n+**                      Infineon Technologies AG\n+**                      Am Campeon 1-12, 85579 Neubiberg, Germany\n+**\n+**    This program is free software; you can redistribute it and/or modify\n+**    it under the terms of the GNU General Public License as published by\n+**    the Free Software Foundation; either version 2 of the License, or\n+**    (at your option) any later version.\n+**\n+** HISTORY\n+** $Date        $Author         $Comment\n+** 07 JUL 2009  Xu Liang        Init Version\n+*******************************************************************************/\n+\n+#ifndef IFX_PTM_H\n+#define IFX_PTM_H\n+\n+\n+\n+/*!\n+  \\defgroup IFX_PTM UEIP Project - PTM driver module\n+  \\brief UEIP Project - PTM driver module, support Danube, Amazon-SE, AR9, VR9.\n+ */\n+\n+/*!\n+  \\defgroup IFX_PTM_IOCTL IOCTL Commands\n+  \\ingroup IFX_PTM\n+  \\brief IOCTL Commands used by user application.\n+ */\n+\n+/*!\n+  \\defgroup IFX_PTM_STRUCT Structures\n+  \\ingroup IFX_PTM\n+  \\brief Structures used by user application.\n+ */\n+\n+/*!\n+  \\file ifx_ptm.h\n+  \\ingroup IFX_PTM\n+  \\brief PTM driver header file\n+ */\n+\n+\n+\n+/*\n+ * ####################################\n+ *              Definition\n+ * ####################################\n+ */\n+\n+\n+\n+/*\n+ * ####################################\n+ *                IOCTL\n+ * ####################################\n+ */\n+\n+/*!\n+  \\addtogroup IFX_PTM_IOCTL\n+ */\n+/*@{*/\n+\n+/*\n+ *  ioctl Command\n+ */\n+/*!\n+  \\brief PTM IOCTL Command - Get codeword MIB counters.\n+\n+  This command uses structure \"PTM_CW_IF_ENTRY_T\" to get codeword level MIB counters.\n+ */\n+#define IFX_PTM_MIB_CW_GET              SIOCDEVPRIVATE + 1\n+/*!\n+  \\brief PTM IOCTL Command - Get packet MIB counters.\n+\n+  This command uses structure \"PTM_FRAME_MIB_T\" to get packet level MIB counters.\n+ */\n+#define IFX_PTM_MIB_FRAME_GET           SIOCDEVPRIVATE + 2\n+/*!\n+  \\brief PTM IOCTL Command - Get firmware configuration (CRC).\n+\n+  This command uses structure \"IFX_PTM_CFG_T\" to get firmware configuration (CRC).\n+ */\n+#define IFX_PTM_CFG_GET                 SIOCDEVPRIVATE + 3\n+/*!\n+  \\brief PTM IOCTL Command - Set firmware configuration (CRC).\n+\n+  This command uses structure \"IFX_PTM_CFG_T\" to set firmware configuration (CRC).\n+ */\n+#define IFX_PTM_CFG_SET                 SIOCDEVPRIVATE + 4\n+/*!\n+  \\brief PTM IOCTL Command - Program priority value to TX queue mapping.\n+\n+  This command uses structure \"IFX_PTM_PRIO_Q_MAP_T\" to program priority value to TX queue mapping.\n+ */\n+#define IFX_PTM_MAP_PKT_PRIO_TO_Q       SIOCDEVPRIVATE + 14\n+\n+/*@}*/\n+\n+\n+/*!\n+  \\addtogroup IFX_PTM_STRUCT\n+ */\n+/*@{*/\n+\n+/*\n+ *  ioctl Data Type\n+ */\n+\n+/*!\n+  \\typedef PTM_CW_IF_ENTRY_T\n+  \\brief Wrapping of structure \"ptm_cw_ifEntry_t\".\n+ */\n+/*!\n+  \\struct ptm_cw_ifEntry_t\n+  \\brief Structure used for CodeWord level MIB counters.\n+ */\n+typedef struct ptm_cw_ifEntry_t {\n+    uint32_t    ifRxNoIdleCodewords;    /*!< output, number of ingress user codeword */\n+    uint32_t    ifRxIdleCodewords;      /*!< output, number of ingress idle codeword */\n+    uint32_t    ifRxCodingViolation;    /*!< output, number of error ingress codeword */\n+    uint32_t    ifTxNoIdleCodewords;    /*!< output, number of egress user codeword */\n+    uint32_t    ifTxIdleCodewords;      /*!< output, number of egress idle codeword */\n+} PTM_CW_IF_ENTRY_T;\n+\n+/*!\n+  \\typedef PTM_FRAME_MIB_T\n+  \\brief Wrapping of structure \"ptm_frame_mib_t\".\n+ */\n+/*!\n+  \\struct ptm_frame_mib_t\n+  \\brief Structure used for packet level MIB counters.\n+ */\n+typedef struct ptm_frame_mib_t {\n+    uint32_t    RxCorrect;      /*!< output, number of ingress packet */\n+    uint32_t    TC_CrcError;    /*!< output, number of egress packet with CRC error */\n+    uint32_t    RxDropped;      /*!< output, number of dropped ingress packet */\n+    uint32_t    TxSend;         /*!< output, number of egress packet */\n+} PTM_FRAME_MIB_T;\n+\n+/*!\n+  \\typedef IFX_PTM_CFG_T\n+  \\brief Wrapping of structure \"ptm_cfg_t\".\n+ */\n+/*!\n+  \\struct ptm_cfg_t\n+  \\brief Structure used for ETH/TC CRC configuration.\n+ */\n+typedef struct ptm_cfg_t {\n+    uint32_t    RxEthCrcPresent;    /*!< input/output, ingress packet has ETH CRC */\n+    uint32_t    RxEthCrcCheck;      /*!< input/output, check ETH CRC of ingress packet */\n+    uint32_t    RxTcCrcCheck;       /*!< input/output, check TC CRC of ingress codeword */\n+    uint32_t    RxTcCrcLen;         /*!< input/output, length of TC CRC of ingress codeword */\n+    uint32_t    TxEthCrcGen;        /*!< input/output, generate ETH CRC for egress packet */\n+    uint32_t    TxTcCrcGen;         /*!< input/output, generate TC CRC for egress codeword */\n+    uint32_t    TxTcCrcLen;         /*!< input/output, length of TC CRC of egress codeword */\n+} IFX_PTM_CFG_T;\n+\n+/*!\n+  \\typedef IFX_PTM_PRIO_Q_MAP_T\n+  \\brief Wrapping of structure \"ppe_prio_q_map\".\n+ */\n+/*!\n+  \\struct ppe_prio_q_map\n+  \\brief Structure used for Priority Value to TX Queue mapping.\n+ */\n+typedef struct ppe_prio_q_map {\n+    int             pkt_prio;\n+    int             qid;\n+    int             vpi;    //  ignored in eth interface\n+    int             vci;    //  ignored in eth interface\n+} IFX_PTM_PRIO_Q_MAP_T;\n+\n+/*@}*/\n+\n+\n+\n+/*\n+ * ####################################\n+ *                 API\n+ * ####################################\n+ */\n+\n+#ifdef __KERNEL__\n+struct port_cell_info {\n+    unsigned int    port_num;\n+    unsigned int    tx_link_rate[2];\n+};\n+#endif\n+\n+\n+\n+#endif  //  IFX_PTM_H\n+\n--- a/arch/mips/lantiq/irq.c\n+++ b/arch/mips/lantiq/irq.c\n@@ -12,6 +12,7 @@\n #include <linux/of_platform.h>\n #include <linux/of_address.h>\n #include <linux/of_irq.h>\n+#include <linux/module.h>\n \n #include <asm/bootinfo.h>\n #include <asm/irq_cpu.h>\n@@ -91,6 +92,7 @@ void ltq_disable_irq(struct irq_data *d)\n \t}\n \traw_spin_unlock_irqrestore(&ltq_icu_lock, flags);\n }\n+EXPORT_SYMBOL(ltq_mask_and_ack_irq);\n \n void ltq_mask_and_ack_irq(struct irq_data *d)\n {\n--- a/arch/mips/mm/cache.c\n+++ b/arch/mips/mm/cache.c\n@@ -61,6 +61,10 @@ void (*_dma_cache_wback_inv)(unsigned lo\n void (*_dma_cache_wback)(unsigned long start, unsigned long size);\n void (*_dma_cache_inv)(unsigned long start, unsigned long size);\n \n+EXPORT_SYMBOL(_dma_cache_wback_inv);\n+EXPORT_SYMBOL(_dma_cache_wback);\n+EXPORT_SYMBOL(_dma_cache_inv);\n+\n #endif /* CONFIG_DMA_NONCOHERENT */\n \n /*\n--- a/include/uapi/linux/atm.h\n+++ b/include/uapi/linux/atm.h\n@@ -131,8 +131,14 @@\n #define ATM_ABR\t\t4\n #define ATM_ANYCLASS\t5\t\t/* compatible with everything */\n \n+#define ATM_VBR_NRT     ATM_VBR\n+#define ATM_VBR_RT      6\n+#define ATM_UBR_PLUS    7\n+#define ATM_GFR         8\n+\n #define ATM_MAX_PCR\t-1\t\t/* maximum available PCR */\n \n+\n struct atm_trafprm {\n \tunsigned char\ttraffic_class;\t/* traffic class (ATM_UBR, ...) */\n \tint\t\tmax_pcr;\t/* maximum PCR in cells per second */\n--- a/net/atm/proc.c\n+++ b/net/atm/proc.c\n@@ -141,7 +141,7 @@ static void *vcc_seq_next(struct seq_fil\n static void pvc_info(struct seq_file *seq, struct atm_vcc *vcc)\n {\n \tstatic const char *const class_name[] = {\n-\t\t\"off\", \"UBR\", \"CBR\", \"VBR\", \"ABR\"};\n+\t\t\"off\",\"UBR\",\"CBR\",\"NTR-VBR\",\"ABR\",\"ANY\",\"RT-VBR\",\"UBR+\",\"GFR\"};\n \tstatic const char *const aal_name[] = {\n \t\t\"---\",\t\"1\",\t\"2\",\t\"3/4\",\t/*  0- 3 */\n \t\t\"???\",\t\"5\",\t\"???\",\t\"???\",\t/*  4- 7 */\n"
  },
  {
    "path": "target/linux/lantiq/patches-5.10/0008-MIPS-lantiq-backport-old-timer-code.patch",
    "content": "From 94800350cb8d2f29dda2206b5e9a3772024ee168 Mon Sep 17 00:00:00 2001\nFrom: John Crispin <blogic@openwrt.org>\nDate: Thu, 7 Aug 2014 18:30:56 +0200\nSubject: [PATCH 08/36] MIPS: lantiq: backport old timer code\n\nSigned-off-by: John Crispin <blogic@openwrt.org>\n---\n arch/mips/include/asm/mach-lantiq/lantiq_timer.h |  155 ++++\n arch/mips/lantiq/xway/Makefile                   |    2 +-\n arch/mips/lantiq/xway/timer.c                    |  845 ++++++++++++++++++++++\n 3 files changed, 1001 insertions(+), 1 deletion(-)\n create mode 100644 arch/mips/include/asm/mach-lantiq/lantiq_timer.h\n create mode 100644 arch/mips/lantiq/xway/timer.c\n\n--- /dev/null\n+++ b/arch/mips/include/asm/mach-lantiq/lantiq_timer.h\n@@ -0,0 +1,155 @@\n+#ifndef __DANUBE_GPTU_DEV_H__2005_07_26__10_19__\n+#define __DANUBE_GPTU_DEV_H__2005_07_26__10_19__\n+\n+\n+/******************************************************************************\n+       Copyright (c) 2002, Infineon Technologies.  All rights reserved.\n+\n+                               No Warranty\n+   Because the program is licensed free of charge, there is no warranty for\n+   the program, to the extent permitted by applicable law.  Except when\n+   otherwise stated in writing the copyright holders and/or other parties\n+   provide the program \"as is\" without warranty of any kind, either\n+   expressed or implied, including, but not limited to, the implied\n+   warranties of merchantability and fitness for a particular purpose. The\n+   entire risk as to the quality and performance of the program is with\n+   you.  should the program prove defective, you assume the cost of all\n+   necessary servicing, repair or correction.\n+\n+   In no event unless required by applicable law or agreed to in writing\n+   will any copyright holder, or any other party who may modify and/or\n+   redistribute the program as permitted above, be liable to you for\n+   damages, including any general, special, incidental or consequential\n+   damages arising out of the use or inability to use the program\n+   (including but not limited to loss of data or data being rendered\n+   inaccurate or losses sustained by you or third parties or a failure of\n+   the program to operate with any other programs), even if such holder or\n+   other party has been advised of the possibility of such damages.\n+******************************************************************************/\n+\n+\n+/*\n+ * ####################################\n+ *              Definition\n+ * ####################################\n+ */\n+\n+/*\n+ *  Available Timer/Counter Index\n+ */\n+#define TIMER(n, X)                     (n * 2 + (X ? 1 : 0))\n+#define TIMER_ANY                       0x00\n+#define TIMER1A                         TIMER(1, 0)\n+#define TIMER1B                         TIMER(1, 1)\n+#define TIMER2A                         TIMER(2, 0)\n+#define TIMER2B                         TIMER(2, 1)\n+#define TIMER3A                         TIMER(3, 0)\n+#define TIMER3B                         TIMER(3, 1)\n+\n+/*\n+ *  Flag of Timer/Counter\n+ *  These flags specify the way in which timer is configured.\n+ */\n+/*  Bit size of timer/counter.                      */\n+#define TIMER_FLAG_16BIT                0x0000\n+#define TIMER_FLAG_32BIT                0x0001\n+/*  Switch between timer and counter.               */\n+#define TIMER_FLAG_TIMER                0x0000\n+#define TIMER_FLAG_COUNTER              0x0002\n+/*  Stop or continue when overflowing/underflowing. */\n+#define TIMER_FLAG_ONCE                 0x0000\n+#define TIMER_FLAG_CYCLIC               0x0004\n+/*  Count up or counter down.                       */\n+#define TIMER_FLAG_UP                   0x0000\n+#define TIMER_FLAG_DOWN                 0x0008\n+/*  Count on specific level or edge.                */\n+#define TIMER_FLAG_HIGH_LEVEL_SENSITIVE 0x0000\n+#define TIMER_FLAG_LOW_LEVEL_SENSITIVE  0x0040\n+#define TIMER_FLAG_RISE_EDGE            0x0010\n+#define TIMER_FLAG_FALL_EDGE            0x0020\n+#define TIMER_FLAG_ANY_EDGE             0x0030\n+/*  Signal is syncronous to module clock or not.    */\n+#define TIMER_FLAG_UNSYNC               0x0000\n+#define TIMER_FLAG_SYNC                 0x0080\n+/*  Different interrupt handle type.                */\n+#define TIMER_FLAG_NO_HANDLE            0x0000\n+#if defined(__KERNEL__)\n+    #define TIMER_FLAG_CALLBACK_IN_IRQ  0x0100\n+#endif  //  defined(__KERNEL__)\n+#define TIMER_FLAG_SIGNAL               0x0300\n+/*  Internal clock source or external clock source  */\n+#define TIMER_FLAG_INT_SRC              0x0000\n+#define TIMER_FLAG_EXT_SRC              0x1000\n+\n+\n+/*\n+ *  ioctl Command\n+ */\n+#define GPTU_REQUEST_TIMER              0x01    /*  General method to setup timer/counter.  */\n+#define GPTU_FREE_TIMER                 0x02    /*  Free timer/counter.                     */\n+#define GPTU_START_TIMER                0x03    /*  Start or resume timer/counter.          */\n+#define GPTU_STOP_TIMER                 0x04    /*  Suspend timer/counter.                  */\n+#define GPTU_GET_COUNT_VALUE            0x05    /*  Get current count value.                */\n+#define GPTU_CALCULATE_DIVIDER          0x06    /*  Calculate timer divider from given freq.*/\n+#define GPTU_SET_TIMER                  0x07    /*  Simplified method to setup timer.       */\n+#define GPTU_SET_COUNTER                0x08    /*  Simplified method to setup counter.     */\n+\n+/*\n+ *  Data Type Used to Call ioctl\n+ */\n+struct gptu_ioctl_param {\n+    unsigned int                        timer;  /*  In command GPTU_REQUEST_TIMER, GPTU_SET_TIMER, and  *\n+                                                 *  GPTU_SET_COUNTER, this field is ID of expected      *\n+                                                 *  timer/counter. If it's zero, a timer/counter would  *\n+                                                 *  be dynamically allocated and ID would be stored in  *\n+                                                 *  this field.                                         *\n+                                                 *  In command GPTU_GET_COUNT_VALUE, this field is      *\n+                                                 *  ignored.                                            *\n+                                                 *  In other command, this field is ID of timer/counter *\n+                                                 *  allocated.                                          */\n+    unsigned int                        flag;   /*  In command GPTU_REQUEST_TIMER, GPTU_SET_TIMER, and  *\n+                                                 *  GPTU_SET_COUNTER, this field contains flags to      *\n+                                                 *  specify how to configure timer/counter.             *\n+                                                 *  In command GPTU_START_TIMER, zero indicate start    *\n+                                                 *  and non-zero indicate resume timer/counter.         *\n+                                                 *  In other command, this field is ignored.            */\n+    unsigned long                       value;  /*  In command GPTU_REQUEST_TIMER, this field contains  *\n+                                                 *  init/reload value.                                  *\n+                                                 *  In command GPTU_SET_TIMER, this field contains      *\n+                                                 *  frequency (0.001Hz) of timer.                       *\n+                                                 *  In command GPTU_GET_COUNT_VALUE, current count      *\n+                                                 *  value would be stored in this field.                *\n+                                                 *  In command GPTU_CALCULATE_DIVIDER, this field       *\n+                                                 *  contains frequency wanted, and after calculation,   *\n+                                                 *  divider would be stored in this field to overwrite  *\n+                                                 *  the frequency.                                      *\n+                                                 *  In other command, this field is ignored.            */\n+    int                                 pid;    /*  In command GPTU_REQUEST_TIMER and GPTU_SET_TIMER,   *\n+                                                 *  if signal is required, this field contains process  *\n+                                                 *  ID to which signal would be sent.                   *\n+                                                 *  In other command, this field is ignored.            */\n+    int                                 sig;    /*  In command GPTU_REQUEST_TIMER and GPTU_SET_TIMER,   *\n+                                                 *  if signal is required, this field contains signal   *\n+                                                 *  number which would be sent.                         *\n+                                                 *  In other command, this field is ignored.            */\n+};\n+\n+/*\n+ * ####################################\n+ *              Data Type\n+ * ####################################\n+ */\n+typedef void (*timer_callback)(unsigned long arg);\n+\n+extern int lq_request_timer(unsigned int, unsigned int, unsigned long, unsigned long, unsigned long);\n+extern int lq_free_timer(unsigned int);\n+extern int lq_start_timer(unsigned int, int);\n+extern int lq_stop_timer(unsigned int);\n+extern int lq_reset_counter_flags(u32 timer, u32 flags);\n+extern int lq_get_count_value(unsigned int, unsigned long *);\n+extern u32 lq_cal_divider(unsigned long);\n+extern int lq_set_timer(unsigned int, unsigned int, int, int, unsigned int, unsigned long, unsigned long);\n+extern int lq_set_counter(unsigned int timer, unsigned int flag,\n+\tu32 reload, unsigned long arg1, unsigned long arg2);\n+\n+#endif /* __DANUBE_GPTU_DEV_H__2005_07_26__10_19__ */\n--- a/arch/mips/lantiq/xway/Makefile\n+++ b/arch/mips/lantiq/xway/Makefile\n@@ -1,4 +1,10 @@\n # SPDX-License-Identifier: GPL-2.0-only\n-obj-y := prom.o sysctrl.o clk.o dma.o gptu.o dcdc.o\n+obj-y := prom.o sysctrl.o clk.o dma.o dcdc.o\n+\n+ifdef CONFIG_SOC_AMAZON_SE\n+obj-y += gptu.o\n+else\n+obj-y += timer.o\n+endif\n \n obj-y += vmmc.o\n--- /dev/null\n+++ b/arch/mips/lantiq/xway/timer.c\n@@ -0,0 +1,846 @@\n+#ifndef CONFIG_SOC_AMAZON_SE\n+\n+#include <linux/kernel.h>\n+#include <linux/module.h>\n+#include <linux/version.h>\n+#include <linux/types.h>\n+#include <linux/fs.h>\n+#include <linux/miscdevice.h>\n+#include <linux/init.h>\n+#include <linux/uaccess.h>\n+#include <linux/unistd.h>\n+#include <linux/errno.h>\n+#include <linux/interrupt.h>\n+#include <linux/sched.h>\n+#include <linux/sched/signal.h>\n+\n+#include <asm/irq.h>\n+#include <asm/div64.h>\n+#include \"../clk.h\"\n+\n+#include <lantiq_soc.h>\n+#include <lantiq_irq.h>\n+#include <lantiq_timer.h>\n+\n+#define MAX_NUM_OF_32BIT_TIMER_BLOCKS\t6\n+\n+#ifdef TIMER1A\n+#define FIRST_TIMER\t\t\tTIMER1A\n+#else\n+#define FIRST_TIMER\t\t\t2\n+#endif\n+\n+/*\n+ *  GPTC divider is set or not.\n+ */\n+#define GPTU_CLC_RMC_IS_SET\t\t0\n+\n+/*\n+ *  Timer Interrupt (IRQ)\n+ */\n+/*  Must be adjusted when ICU driver is available */\n+#define TIMER_INTERRUPT\t\t\t(INT_NUM_IM3_IRL0 + 22)\n+\n+/*\n+ *  Bits Operation\n+ */\n+#define GET_BITS(x, msb, lsb)\t\t\\\n+\t(((x) & ((1 << ((msb) + 1)) - 1)) >> (lsb))\n+#define SET_BITS(x, msb, lsb, value)\t\\\n+\t(((x) & ~(((1 << ((msb) + 1)) - 1) ^ ((1 << (lsb)) - 1))) | \\\n+\t(((value) & ((1 << (1 + (msb) - (lsb))) - 1)) << (lsb)))\n+\n+/*\n+ *  GPTU Register Mapping\n+ */\n+#define LQ_GPTU\t\t\t(KSEG1 + 0x1E100A00)\n+#define LQ_GPTU_CLC\t\t((volatile u32 *)(LQ_GPTU + 0x0000))\n+#define LQ_GPTU_ID\t\t\t((volatile u32 *)(LQ_GPTU + 0x0008))\n+#define LQ_GPTU_CON(n, X)\t\t((volatile u32 *)(LQ_GPTU + 0x0010 + ((X) * 4) + ((n) - 1) * 0x0020))\t/* X must be either A or B */\n+#define LQ_GPTU_RUN(n, X)\t\t((volatile u32 *)(LQ_GPTU + 0x0018 + ((X) * 4) + ((n) - 1) * 0x0020))\t/* X must be either A or B */\n+#define LQ_GPTU_RELOAD(n, X)\t((volatile u32 *)(LQ_GPTU + 0x0020 + ((X) * 4) + ((n) - 1) * 0x0020))\t/* X must be either A or B */\n+#define LQ_GPTU_COUNT(n, X)\t((volatile u32 *)(LQ_GPTU + 0x0028 + ((X) * 4) + ((n) - 1) * 0x0020))\t/* X must be either A or B */\n+#define LQ_GPTU_IRNEN\t\t((volatile u32 *)(LQ_GPTU + 0x00F4))\n+#define LQ_GPTU_IRNICR\t\t((volatile u32 *)(LQ_GPTU + 0x00F8))\n+#define LQ_GPTU_IRNCR\t\t((volatile u32 *)(LQ_GPTU + 0x00FC))\n+\n+/*\n+ *  Clock Control Register\n+ */\n+#define GPTU_CLC_SMC\t\t\tGET_BITS(*LQ_GPTU_CLC, 23, 16)\n+#define GPTU_CLC_RMC\t\t\tGET_BITS(*LQ_GPTU_CLC, 15, 8)\n+#define GPTU_CLC_FSOE\t\t\t(*LQ_GPTU_CLC & (1 << 5))\n+#define GPTU_CLC_EDIS\t\t\t(*LQ_GPTU_CLC & (1 << 3))\n+#define GPTU_CLC_SPEN\t\t\t(*LQ_GPTU_CLC & (1 << 2))\n+#define GPTU_CLC_DISS\t\t\t(*LQ_GPTU_CLC & (1 << 1))\n+#define GPTU_CLC_DISR\t\t\t(*LQ_GPTU_CLC & (1 << 0))\n+\n+#define GPTU_CLC_SMC_SET(value)\t\tSET_BITS(0, 23, 16, (value))\n+#define GPTU_CLC_RMC_SET(value)\t\tSET_BITS(0, 15, 8, (value))\n+#define GPTU_CLC_FSOE_SET(value)\t((value) ? (1 << 5) : 0)\n+#define GPTU_CLC_SBWE_SET(value)\t((value) ? (1 << 4) : 0)\n+#define GPTU_CLC_EDIS_SET(value)\t((value) ? (1 << 3) : 0)\n+#define GPTU_CLC_SPEN_SET(value)\t((value) ? (1 << 2) : 0)\n+#define GPTU_CLC_DISR_SET(value)\t((value) ? (1 << 0) : 0)\n+\n+/*\n+ *  ID Register\n+ */\n+#define GPTU_ID_ID\t\t\tGET_BITS(*LQ_GPTU_ID, 15, 8)\n+#define GPTU_ID_CFG\t\t\tGET_BITS(*LQ_GPTU_ID, 7, 5)\n+#define GPTU_ID_REV\t\t\tGET_BITS(*LQ_GPTU_ID, 4, 0)\n+\n+/*\n+ *  Control Register of Timer/Counter nX\n+ *    n is the index of block (1 based index)\n+ *    X is either A or B\n+ */\n+#define GPTU_CON_SRC_EG(n, X)\t\t(*LQ_GPTU_CON(n, X) & (1 << 10))\n+#define GPTU_CON_SRC_EXT(n, X)\t\t(*LQ_GPTU_CON(n, X) & (1 << 9))\n+#define GPTU_CON_SYNC(n, X)\t\t(*LQ_GPTU_CON(n, X) & (1 << 8))\n+#define GPTU_CON_EDGE(n, X)\t\tGET_BITS(*LQ_GPTU_CON(n, X), 7, 6)\n+#define GPTU_CON_INV(n, X)\t\t(*LQ_GPTU_CON(n, X) & (1 << 5))\n+#define GPTU_CON_EXT(n, X)\t\t(*LQ_GPTU_CON(n, A) & (1 << 4))\t/* Timer/Counter B does not have this bit */\n+#define GPTU_CON_STP(n, X)\t\t(*LQ_GPTU_CON(n, X) & (1 << 3))\n+#define GPTU_CON_CNT(n, X)\t\t(*LQ_GPTU_CON(n, X) & (1 << 2))\n+#define GPTU_CON_DIR(n, X)\t\t(*LQ_GPTU_CON(n, X) & (1 << 1))\n+#define GPTU_CON_EN(n, X)\t\t(*LQ_GPTU_CON(n, X) & (1 << 0))\n+\n+#define GPTU_CON_SRC_EG_SET(value)\t((value) ? 0 : (1 << 10))\n+#define GPTU_CON_SRC_EXT_SET(value)\t((value) ? (1 << 9) : 0)\n+#define GPTU_CON_SYNC_SET(value)\t((value) ? (1 << 8) : 0)\n+#define GPTU_CON_EDGE_SET(value)\tSET_BITS(0, 7, 6, (value))\n+#define GPTU_CON_INV_SET(value)\t\t((value) ? (1 << 5) : 0)\n+#define GPTU_CON_EXT_SET(value)\t\t((value) ? (1 << 4) : 0)\n+#define GPTU_CON_STP_SET(value)\t\t((value) ? (1 << 3) : 0)\n+#define GPTU_CON_CNT_SET(value)\t\t((value) ? (1 << 2) : 0)\n+#define GPTU_CON_DIR_SET(value)\t\t((value) ? (1 << 1) : 0)\n+\n+#define GPTU_RUN_RL_SET(value)\t\t((value) ? (1 << 2) : 0)\n+#define GPTU_RUN_CEN_SET(value)\t\t((value) ? (1 << 1) : 0)\n+#define GPTU_RUN_SEN_SET(value)\t\t((value) ? (1 << 0) : 0)\n+\n+#define GPTU_IRNEN_TC_SET(n, X, value)\t((value) ? (1 << (((n) - 1) * 2 + (X))) : 0)\n+#define GPTU_IRNCR_TC_SET(n, X, value)\t((value) ? (1 << (((n) - 1) * 2 + (X))) : 0)\n+\n+#define TIMER_FLAG_MASK_SIZE(x)\t\t(x & 0x0001)\n+#define TIMER_FLAG_MASK_TYPE(x)\t\t(x & 0x0002)\n+#define TIMER_FLAG_MASK_STOP(x)\t\t(x & 0x0004)\n+#define TIMER_FLAG_MASK_DIR(x)\t\t(x & 0x0008)\n+#define TIMER_FLAG_NONE_EDGE\t\t0x0000\n+#define TIMER_FLAG_MASK_EDGE(x)\t\t(x & 0x0030)\n+#define TIMER_FLAG_REAL\t\t\t0x0000\n+#define TIMER_FLAG_INVERT\t\t0x0040\n+#define TIMER_FLAG_MASK_INVERT(x)\t(x & 0x0040)\n+#define TIMER_FLAG_MASK_TRIGGER(x)\t(x & 0x0070)\n+#define TIMER_FLAG_MASK_SYNC(x)\t\t(x & 0x0080)\n+#define TIMER_FLAG_CALLBACK_IN_HB\t0x0200\n+#define TIMER_FLAG_MASK_HANDLE(x)\t(x & 0x0300)\n+#define TIMER_FLAG_MASK_SRC(x)\t\t(x & 0x1000)\n+\n+struct timer_dev_timer {\n+\tunsigned int f_irq_on;\n+\tunsigned int irq;\n+\tunsigned int flag;\n+\tunsigned long arg1;\n+\tunsigned long arg2;\n+};\n+\n+struct timer_dev {\n+\tstruct mutex gptu_mutex;\n+\tunsigned int number_of_timers;\n+\tunsigned int occupation;\n+\tunsigned int f_gptu_on;\n+\tstruct timer_dev_timer timer[MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2];\n+};\n+\n+\n+unsigned int ltq_get_fpi_bus_clock(int fpi) {\n+\tstruct clk *clk = clk_get_fpi();\n+\treturn clk_get_rate(clk);\n+}\n+\n+\n+static long gptu_ioctl(struct file *, unsigned int, unsigned long);\n+static int gptu_open(struct inode *, struct file *);\n+static int gptu_release(struct inode *, struct file *);\n+\n+static struct file_operations gptu_fops = {\n+\t.owner = THIS_MODULE,\n+\t.unlocked_ioctl = gptu_ioctl,\n+\t.open = gptu_open,\n+\t.release = gptu_release\n+};\n+\n+static struct miscdevice gptu_miscdev = {\n+\t.minor = MISC_DYNAMIC_MINOR,\n+\t.name = \"gptu\",\n+\t.fops = &gptu_fops,\n+};\n+\n+static struct timer_dev timer_dev;\n+\n+static irqreturn_t timer_irq_handler(int irq, void *p)\n+{\n+\tunsigned int timer;\n+\tunsigned int flag;\n+\tstruct timer_dev_timer *dev_timer = (struct timer_dev_timer *)p;\n+\n+\ttimer = irq - TIMER_INTERRUPT;\n+\tif (timer < timer_dev.number_of_timers\n+\t\t&& dev_timer == &timer_dev.timer[timer]) {\n+\t\t/*  Clear interrupt.    */\n+\t\tltq_w32(1 << timer, LQ_GPTU_IRNCR);\n+\n+\t\t/*  Call user hanler or signal. */\n+\t\tflag = dev_timer->flag;\n+\t\tif (!(timer & 0x01)\n+\t\t\t|| TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT) {\n+\t\t\t/* 16-bit timer or timer A of 32-bit timer  */\n+\t\t\tswitch (TIMER_FLAG_MASK_HANDLE(flag)) {\n+\t\t\tcase TIMER_FLAG_CALLBACK_IN_IRQ:\n+\t\t\tcase TIMER_FLAG_CALLBACK_IN_HB:\n+\t\t\t\tif (dev_timer->arg1)\n+\t\t\t\t\t(*(timer_callback)dev_timer->arg1)(dev_timer->arg2);\n+\t\t\t\tbreak;\n+\t\t\tcase TIMER_FLAG_SIGNAL:\n+\t\t\t\tsend_sig((int)dev_timer->arg2, (struct task_struct *)dev_timer->arg1, 0);\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t}\n+\t}\n+\treturn IRQ_HANDLED;\n+}\n+\n+static inline void lq_enable_gptu(void)\n+{\n+\tstruct clk *clk = clk_get_sys(\"1e100a00.gptu\", NULL);\n+\tclk_enable(clk);\n+\n+\t//ltq_pmu_enable(PMU_GPT);\n+\n+\t/*  Set divider as 1, disable write protection for SPEN, enable module. */\n+\t*LQ_GPTU_CLC =\n+\t\tGPTU_CLC_SMC_SET(0x00) |\n+\t\tGPTU_CLC_RMC_SET(0x01) |\n+\t\tGPTU_CLC_FSOE_SET(0) |\n+\t\tGPTU_CLC_SBWE_SET(1) |\n+\t\tGPTU_CLC_EDIS_SET(0) |\n+\t\tGPTU_CLC_SPEN_SET(0) |\n+\t\tGPTU_CLC_DISR_SET(0);\n+}\n+\n+static inline void lq_disable_gptu(void)\n+{\n+\tstruct clk *clk = clk_get_sys(\"1e100a00.gptu\", NULL);\n+\tltq_w32(0x00, LQ_GPTU_IRNEN);\n+\tltq_w32(0xfff, LQ_GPTU_IRNCR);\n+\n+\t/*  Set divider as 0, enable write protection for SPEN, disable module. */\n+\t*LQ_GPTU_CLC =\n+\t\tGPTU_CLC_SMC_SET(0x00) |\n+\t\tGPTU_CLC_RMC_SET(0x00) |\n+\t\tGPTU_CLC_FSOE_SET(0) |\n+\t\tGPTU_CLC_SBWE_SET(0) |\n+\t\tGPTU_CLC_EDIS_SET(0) |\n+\t\tGPTU_CLC_SPEN_SET(0) |\n+\t\tGPTU_CLC_DISR_SET(1);\n+\n+\tclk_enable(clk);\n+}\n+\n+int lq_request_timer(unsigned int timer, unsigned int flag,\n+\tunsigned long value, unsigned long arg1, unsigned long arg2)\n+{\n+\tint ret = 0;\n+\tunsigned int con_reg, irnen_reg;\n+\tint n, X;\n+\n+\tif (timer >= FIRST_TIMER + timer_dev.number_of_timers)\n+\t\treturn -EINVAL;\n+\n+\tprintk(KERN_INFO \"request_timer(%d, 0x%08X, %lu)...\",\n+\t\ttimer, flag, value);\n+\n+\tif (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT)\n+\t\tvalue &= 0xFFFF;\n+\telse\n+\t\ttimer &= ~0x01;\n+\n+\tmutex_lock(&timer_dev.gptu_mutex);\n+\n+\t/*\n+\t *  Allocate timer.\n+\t */\n+\tif (timer < FIRST_TIMER) {\n+\t\tunsigned int mask;\n+\t\tunsigned int shift;\n+\t\t/* This takes care of TIMER1B which is the only choice for Voice TAPI system */\n+\t\tunsigned int offset = TIMER2A;\n+\n+\t\t/*\n+\t\t *  Pick up a free timer.\n+\t\t */\n+\t\tif (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT) {\n+\t\t\tmask = 1 << offset;\n+\t\t\tshift = 1;\n+\t\t} else {\n+\t\t\tmask = 3 << offset;\n+\t\t\tshift = 2;\n+\t\t}\n+\t\tfor (timer = offset;\n+\t\t     timer < offset + timer_dev.number_of_timers;\n+\t\t     timer += shift, mask <<= shift)\n+\t\t\tif (!(timer_dev.occupation & mask)) {\n+\t\t\t\ttimer_dev.occupation |= mask;\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\tif (timer >= offset + timer_dev.number_of_timers) {\n+\t\t\tprintk(\"failed![%d]\\n\", __LINE__);\n+\t\t\tmutex_unlock(&timer_dev.gptu_mutex);\n+\t\t\treturn -EINVAL;\n+\t\t} else\n+\t\t\tret = timer;\n+\t} else {\n+\t\tregister unsigned int mask;\n+\n+\t\t/*\n+\t\t *  Check if the requested timer is free.\n+\t\t */\n+\t\tmask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;\n+\t\tif ((timer_dev.occupation & mask)) {\n+\t\t\tprintk(\"failed![%d] mask %#x, timer_dev.occupation %#x\\n\",\n+\t\t\t\t__LINE__, mask, timer_dev.occupation);\n+\t\t\tmutex_unlock(&timer_dev.gptu_mutex);\n+\t\t\treturn -EBUSY;\n+\t\t} else {\n+\t\t\ttimer_dev.occupation |= mask;\n+\t\t\tret = 0;\n+\t\t}\n+\t}\n+\n+\t/*\n+\t *  Prepare control register value.\n+\t */\n+\tswitch (TIMER_FLAG_MASK_EDGE(flag)) {\n+\tdefault:\n+\tcase TIMER_FLAG_NONE_EDGE:\n+\t\tcon_reg = GPTU_CON_EDGE_SET(0x00);\n+\t\tbreak;\n+\tcase TIMER_FLAG_RISE_EDGE:\n+\t\tcon_reg = GPTU_CON_EDGE_SET(0x01);\n+\t\tbreak;\n+\tcase TIMER_FLAG_FALL_EDGE:\n+\t\tcon_reg = GPTU_CON_EDGE_SET(0x02);\n+\t\tbreak;\n+\tcase TIMER_FLAG_ANY_EDGE:\n+\t\tcon_reg = GPTU_CON_EDGE_SET(0x03);\n+\t\tbreak;\n+\t}\n+\tif (TIMER_FLAG_MASK_TYPE(flag) == TIMER_FLAG_TIMER)\n+\t\tcon_reg |=\n+\t\t\tTIMER_FLAG_MASK_SRC(flag) ==\n+\t\t\tTIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EXT_SET(1) :\n+\t\t\tGPTU_CON_SRC_EXT_SET(0);\n+\telse\n+\t\tcon_reg |=\n+\t\t\tTIMER_FLAG_MASK_SRC(flag) ==\n+\t\t\tTIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EG_SET(1) :\n+\t\t\tGPTU_CON_SRC_EG_SET(0);\n+\tcon_reg |=\n+\t\tTIMER_FLAG_MASK_SYNC(flag) ==\n+\t\tTIMER_FLAG_UNSYNC ? GPTU_CON_SYNC_SET(0) :\n+\t\tGPTU_CON_SYNC_SET(1);\n+\tcon_reg |=\n+\t\tTIMER_FLAG_MASK_INVERT(flag) ==\n+\t\tTIMER_FLAG_REAL ? GPTU_CON_INV_SET(0) : GPTU_CON_INV_SET(1);\n+\tcon_reg |=\n+\t\tTIMER_FLAG_MASK_SIZE(flag) ==\n+\t\tTIMER_FLAG_16BIT ? GPTU_CON_EXT_SET(0) :\n+\t\tGPTU_CON_EXT_SET(1);\n+\tcon_reg |=\n+\t\tTIMER_FLAG_MASK_STOP(flag) ==\n+\t\tTIMER_FLAG_ONCE ? GPTU_CON_STP_SET(1) : GPTU_CON_STP_SET(0);\n+\tcon_reg |=\n+\t\tTIMER_FLAG_MASK_TYPE(flag) ==\n+\t\tTIMER_FLAG_TIMER ? GPTU_CON_CNT_SET(0) :\n+\t\tGPTU_CON_CNT_SET(1);\n+\tcon_reg |=\n+\t\tTIMER_FLAG_MASK_DIR(flag) ==\n+\t\tTIMER_FLAG_UP ? GPTU_CON_DIR_SET(1) : GPTU_CON_DIR_SET(0);\n+\n+\t/*\n+\t *  Fill up running data.\n+\t */\n+\ttimer_dev.timer[timer - FIRST_TIMER].flag = flag;\n+\ttimer_dev.timer[timer - FIRST_TIMER].arg1 = arg1;\n+\ttimer_dev.timer[timer - FIRST_TIMER].arg2 = arg2;\n+\tif (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)\n+\t\ttimer_dev.timer[timer - FIRST_TIMER + 1].flag = flag;\n+\n+\t/*\n+\t *  Enable GPTU module.\n+\t */\n+\tif (!timer_dev.f_gptu_on) {\n+\t\tlq_enable_gptu();\n+\t\ttimer_dev.f_gptu_on = 1;\n+\t}\n+\n+\t/*\n+\t *  Enable IRQ.\n+\t */\n+\tif (TIMER_FLAG_MASK_HANDLE(flag) != TIMER_FLAG_NO_HANDLE) {\n+\t\tif (TIMER_FLAG_MASK_HANDLE(flag) == TIMER_FLAG_SIGNAL)\n+\t\t\ttimer_dev.timer[timer - FIRST_TIMER].arg1 =\n+\t\t\t\t(unsigned long) find_task_by_vpid((int) arg1);\n+\n+\t\tirnen_reg = 1 << (timer - FIRST_TIMER);\n+\n+\t\tif (TIMER_FLAG_MASK_HANDLE(flag) == TIMER_FLAG_SIGNAL\n+\t\t    || (TIMER_FLAG_MASK_HANDLE(flag) ==\n+\t\t\tTIMER_FLAG_CALLBACK_IN_IRQ\n+\t\t\t&& timer_dev.timer[timer - FIRST_TIMER].arg1)) {\n+\t\t\tenable_irq(timer_dev.timer[timer - FIRST_TIMER].irq);\n+\t\t\ttimer_dev.timer[timer - FIRST_TIMER].f_irq_on = 1;\n+\t\t}\n+\t} else\n+\t\tirnen_reg = 0;\n+\n+\t/*\n+\t *  Write config register, reload value and enable interrupt.\n+\t */\n+\tn = timer >> 1;\n+\tX = timer & 0x01;\n+\t*LQ_GPTU_CON(n, X) = con_reg;\n+\t*LQ_GPTU_RELOAD(n, X) = value;\n+\t/* printk(\"reload value = %d\\n\", (u32)value); */\n+\t*LQ_GPTU_IRNEN |= irnen_reg;\n+\n+\tmutex_unlock(&timer_dev.gptu_mutex);\n+\tprintk(\"successful!\\n\");\n+\treturn ret;\n+}\n+EXPORT_SYMBOL(lq_request_timer);\n+\n+int lq_free_timer(unsigned int timer)\n+{\n+\tunsigned int flag;\n+\tunsigned int mask;\n+\tint n, X;\n+\n+\tif (!timer_dev.f_gptu_on)\n+\t\treturn -EINVAL;\n+\n+\tif (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers)\n+\t\treturn -EINVAL;\n+\n+\tmutex_lock(&timer_dev.gptu_mutex);\n+\n+\tflag = timer_dev.timer[timer - FIRST_TIMER].flag;\n+\tif (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)\n+\t\ttimer &= ~0x01;\n+\n+\tmask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;\n+\tif (((timer_dev.occupation & mask) ^ mask)) {\n+\t\tmutex_unlock(&timer_dev.gptu_mutex);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tn = timer >> 1;\n+\tX = timer & 0x01;\n+\n+\tif (GPTU_CON_EN(n, X))\n+\t\t*LQ_GPTU_RUN(n, X) = GPTU_RUN_CEN_SET(1);\n+\n+\t*LQ_GPTU_IRNEN &= ~GPTU_IRNEN_TC_SET(n, X, 1);\n+\t*LQ_GPTU_IRNCR |= GPTU_IRNCR_TC_SET(n, X, 1);\n+\n+\tif (timer_dev.timer[timer - FIRST_TIMER].f_irq_on) {\n+\t\tdisable_irq(timer_dev.timer[timer - FIRST_TIMER].irq);\n+\t\ttimer_dev.timer[timer - FIRST_TIMER].f_irq_on = 0;\n+\t}\n+\n+\ttimer_dev.occupation &= ~mask;\n+\tif (!timer_dev.occupation && timer_dev.f_gptu_on) {\n+\t\tlq_disable_gptu();\n+\t\ttimer_dev.f_gptu_on = 0;\n+\t}\n+\n+\tmutex_unlock(&timer_dev.gptu_mutex);\n+\n+\treturn 0;\n+}\n+EXPORT_SYMBOL(lq_free_timer);\n+\n+int lq_start_timer(unsigned int timer, int is_resume)\n+{\n+\tunsigned int flag;\n+\tunsigned int mask;\n+\tint n, X;\n+\n+\tif (!timer_dev.f_gptu_on)\n+\t\treturn -EINVAL;\n+\n+\tif (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers)\n+\t\treturn -EINVAL;\n+\n+\tmutex_lock(&timer_dev.gptu_mutex);\n+\n+\tflag = timer_dev.timer[timer - FIRST_TIMER].flag;\n+\tif (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)\n+\t\ttimer &= ~0x01;\n+\n+\tmask = (TIMER_FLAG_MASK_SIZE(flag) ==\n+\tTIMER_FLAG_16BIT ? 1 : 3) << timer;\n+\tif (((timer_dev.occupation & mask) ^ mask)) {\n+\t\tmutex_unlock(&timer_dev.gptu_mutex);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tn = timer >> 1;\n+\tX = timer & 0x01;\n+\n+\t*LQ_GPTU_RUN(n, X) = GPTU_RUN_RL_SET(!is_resume) | GPTU_RUN_SEN_SET(1);\n+\n+\n+\tmutex_unlock(&timer_dev.gptu_mutex);\n+\n+\treturn 0;\n+}\n+EXPORT_SYMBOL(lq_start_timer);\n+\n+int lq_stop_timer(unsigned int timer)\n+{\n+\tunsigned int flag;\n+\tunsigned int mask;\n+\tint n, X;\n+\n+\tif (!timer_dev.f_gptu_on)\n+\t\treturn -EINVAL;\n+\n+\tif (timer < FIRST_TIMER\n+\t    || timer >= FIRST_TIMER + timer_dev.number_of_timers)\n+\t\treturn -EINVAL;\n+\n+\tmutex_lock(&timer_dev.gptu_mutex);\n+\n+\tflag = timer_dev.timer[timer - FIRST_TIMER].flag;\n+\tif (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)\n+\t\ttimer &= ~0x01;\n+\n+\tmask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;\n+\tif (((timer_dev.occupation & mask) ^ mask)) {\n+\t\tmutex_unlock(&timer_dev.gptu_mutex);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tn = timer >> 1;\n+\tX = timer & 0x01;\n+\n+\t*LQ_GPTU_RUN(n, X) = GPTU_RUN_CEN_SET(1);\n+\n+\tmutex_unlock(&timer_dev.gptu_mutex);\n+\n+\treturn 0;\n+}\n+EXPORT_SYMBOL(lq_stop_timer);\n+\n+int lq_reset_counter_flags(u32 timer, u32 flags)\n+{\n+\tunsigned int oflag;\n+\tunsigned int mask, con_reg;\n+\tint n, X;\n+\n+\tif (!timer_dev.f_gptu_on)\n+\t\treturn -EINVAL;\n+\n+\tif (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers)\n+\t\treturn -EINVAL;\n+\n+\tmutex_lock(&timer_dev.gptu_mutex);\n+\n+\toflag = timer_dev.timer[timer - FIRST_TIMER].flag;\n+\tif (TIMER_FLAG_MASK_SIZE(oflag) != TIMER_FLAG_16BIT)\n+\t\ttimer &= ~0x01;\n+\n+\tmask = (TIMER_FLAG_MASK_SIZE(oflag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;\n+\tif (((timer_dev.occupation & mask) ^ mask)) {\n+\t\tmutex_unlock(&timer_dev.gptu_mutex);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tswitch (TIMER_FLAG_MASK_EDGE(flags)) {\n+\tdefault:\n+\tcase TIMER_FLAG_NONE_EDGE:\n+\t\tcon_reg = GPTU_CON_EDGE_SET(0x00);\n+\t\tbreak;\n+\tcase TIMER_FLAG_RISE_EDGE:\n+\t\tcon_reg = GPTU_CON_EDGE_SET(0x01);\n+\t\tbreak;\n+\tcase TIMER_FLAG_FALL_EDGE:\n+\t\tcon_reg = GPTU_CON_EDGE_SET(0x02);\n+\t\tbreak;\n+\tcase TIMER_FLAG_ANY_EDGE:\n+\t\tcon_reg = GPTU_CON_EDGE_SET(0x03);\n+\t\tbreak;\n+\t}\n+\tif (TIMER_FLAG_MASK_TYPE(flags) == TIMER_FLAG_TIMER)\n+\t\tcon_reg |= TIMER_FLAG_MASK_SRC(flags) == TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EXT_SET(1) : GPTU_CON_SRC_EXT_SET(0);\n+\telse\n+\t\tcon_reg |= TIMER_FLAG_MASK_SRC(flags) == TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EG_SET(1) : GPTU_CON_SRC_EG_SET(0);\n+\tcon_reg |= TIMER_FLAG_MASK_SYNC(flags) == TIMER_FLAG_UNSYNC ? GPTU_CON_SYNC_SET(0) : GPTU_CON_SYNC_SET(1);\n+\tcon_reg |= TIMER_FLAG_MASK_INVERT(flags) == TIMER_FLAG_REAL ? GPTU_CON_INV_SET(0) : GPTU_CON_INV_SET(1);\n+\tcon_reg |= TIMER_FLAG_MASK_SIZE(flags) == TIMER_FLAG_16BIT ? GPTU_CON_EXT_SET(0) : GPTU_CON_EXT_SET(1);\n+\tcon_reg |= TIMER_FLAG_MASK_STOP(flags) == TIMER_FLAG_ONCE ? GPTU_CON_STP_SET(1) : GPTU_CON_STP_SET(0);\n+\tcon_reg |= TIMER_FLAG_MASK_TYPE(flags) == TIMER_FLAG_TIMER ? GPTU_CON_CNT_SET(0) : GPTU_CON_CNT_SET(1);\n+\tcon_reg |= TIMER_FLAG_MASK_DIR(flags) == TIMER_FLAG_UP ? GPTU_CON_DIR_SET(1) : GPTU_CON_DIR_SET(0);\n+\n+\ttimer_dev.timer[timer - FIRST_TIMER].flag = flags;\n+\tif (TIMER_FLAG_MASK_SIZE(flags) != TIMER_FLAG_16BIT)\n+\t\ttimer_dev.timer[timer - FIRST_TIMER + 1].flag = flags;\n+\n+\tn = timer >> 1;\n+\tX = timer & 0x01;\n+\n+\t*LQ_GPTU_CON(n, X) = con_reg;\n+\tsmp_wmb();\n+\tmutex_unlock(&timer_dev.gptu_mutex);\n+\treturn 0;\n+}\n+EXPORT_SYMBOL(lq_reset_counter_flags);\n+\n+int lq_get_count_value(unsigned int timer, unsigned long *value)\n+{\n+\tunsigned int flag;\n+\tunsigned int mask;\n+\tint n, X;\n+\n+\tif (!timer_dev.f_gptu_on)\n+\t\treturn -EINVAL;\n+\n+\tif (timer < FIRST_TIMER\n+\t    || timer >= FIRST_TIMER + timer_dev.number_of_timers)\n+\t\treturn -EINVAL;\n+\n+\tmutex_lock(&timer_dev.gptu_mutex);\n+\n+\tflag = timer_dev.timer[timer - FIRST_TIMER].flag;\n+\tif (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)\n+\t\ttimer &= ~0x01;\n+\n+\tmask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;\n+\tif (((timer_dev.occupation & mask) ^ mask)) {\n+\t\tmutex_unlock(&timer_dev.gptu_mutex);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tn = timer >> 1;\n+\tX = timer & 0x01;\n+\n+\t*value = *LQ_GPTU_COUNT(n, X);\n+\n+\n+\tmutex_unlock(&timer_dev.gptu_mutex);\n+\n+\treturn 0;\n+}\n+EXPORT_SYMBOL(lq_get_count_value);\n+\n+u32 lq_cal_divider(unsigned long freq)\n+{\n+\tu64 module_freq, fpi = ltq_get_fpi_bus_clock(2);\n+\tu32 clock_divider = 1;\n+\tmodule_freq = fpi * 1000;\n+\tdo_div(module_freq, clock_divider * freq);\n+\treturn module_freq;\n+}\n+EXPORT_SYMBOL(lq_cal_divider);\n+\n+int lq_set_timer(unsigned int timer, unsigned int freq, int is_cyclic,\n+\tint is_ext_src, unsigned int handle_flag, unsigned long arg1,\n+\tunsigned long arg2)\n+{\n+\tunsigned long divider;\n+\tunsigned int flag;\n+\n+\tdivider = lq_cal_divider(freq);\n+\tif (divider == 0)\n+\t\treturn -EINVAL;\n+\tflag = ((divider & ~0xFFFF) ? TIMER_FLAG_32BIT : TIMER_FLAG_16BIT)\n+\t\t| (is_cyclic ? TIMER_FLAG_CYCLIC : TIMER_FLAG_ONCE)\n+\t\t| (is_ext_src ? TIMER_FLAG_EXT_SRC : TIMER_FLAG_INT_SRC)\n+\t\t| TIMER_FLAG_TIMER | TIMER_FLAG_DOWN\n+\t\t| TIMER_FLAG_MASK_HANDLE(handle_flag);\n+\n+\tprintk(KERN_INFO \"lq_set_timer(%d, %d), divider = %lu\\n\",\n+\t\ttimer, freq, divider);\n+\treturn lq_request_timer(timer, flag, divider, arg1, arg2);\n+}\n+EXPORT_SYMBOL(lq_set_timer);\n+\n+int lq_set_counter(unsigned int timer, unsigned int flag, u32 reload,\n+\tunsigned long arg1, unsigned long arg2)\n+{\n+\tprintk(KERN_INFO \"lq_set_counter(%d, %#x, %d)\\n\", timer, flag, reload);\n+\treturn lq_request_timer(timer, flag, reload, arg1, arg2);\n+}\n+EXPORT_SYMBOL(lq_set_counter);\n+\n+static long gptu_ioctl(struct file *file, unsigned int cmd,\n+\tunsigned long arg)\n+{\n+\tint ret;\n+\tstruct gptu_ioctl_param param;\n+\n+\tif (!access_ok((void __user *)arg, sizeof(struct gptu_ioctl_param)))\n+\t\treturn -EFAULT;\n+\tcopy_from_user(&param, (void __user *)arg, sizeof(param));\n+\n+\tif ((((cmd == GPTU_REQUEST_TIMER || cmd == GPTU_SET_TIMER\n+\t       || GPTU_SET_COUNTER) && param.timer < 2)\n+\t     || cmd == GPTU_GET_COUNT_VALUE || cmd == GPTU_CALCULATE_DIVIDER)\n+\t    && !access_ok((void __user *)arg,\n+\t\t\t   sizeof(struct gptu_ioctl_param)))\n+\t\treturn -EFAULT;\n+\n+\tswitch (cmd) {\n+\tcase GPTU_REQUEST_TIMER:\n+\t\tret = lq_request_timer(param.timer, param.flag, param.value,\n+\t\t\t\t     (unsigned long) param.pid,\n+\t\t\t\t     (unsigned long) param.sig);\n+\t\tif (ret > 0) {\n+\t\t\tcopy_to_user(&((struct gptu_ioctl_param *) arg)->\n+\t\t\t\t      timer, &ret, sizeof(&ret));\n+\t\t\tret = 0;\n+\t\t}\n+\t\tbreak;\n+\tcase GPTU_FREE_TIMER:\n+\t\tret = lq_free_timer(param.timer);\n+\t\tbreak;\n+\tcase GPTU_START_TIMER:\n+\t\tret = lq_start_timer(param.timer, param.flag);\n+\t\tbreak;\n+\tcase GPTU_STOP_TIMER:\n+\t\tret = lq_stop_timer(param.timer);\n+\t\tbreak;\n+\tcase GPTU_GET_COUNT_VALUE:\n+\t\tret = lq_get_count_value(param.timer, &param.value);\n+\t\tif (!ret)\n+\t\t\tcopy_to_user(&((struct gptu_ioctl_param *) arg)->\n+\t\t\t\t      value, &param.value,\n+\t\t\t\t      sizeof(param.value));\n+\t\tbreak;\n+\tcase GPTU_CALCULATE_DIVIDER:\n+\t\tparam.value = lq_cal_divider(param.value);\n+\t\tif (param.value == 0)\n+\t\t\tret = -EINVAL;\n+\t\telse {\n+\t\t\tcopy_to_user(&((struct gptu_ioctl_param *) arg)->\n+\t\t\t\t      value, &param.value,\n+\t\t\t\t      sizeof(param.value));\n+\t\t\tret = 0;\n+\t\t}\n+\t\tbreak;\n+\tcase GPTU_SET_TIMER:\n+\t\tret = lq_set_timer(param.timer, param.value,\n+\t\t\t\t TIMER_FLAG_MASK_STOP(param.flag) !=\n+\t\t\t\t TIMER_FLAG_ONCE ? 1 : 0,\n+\t\t\t\t TIMER_FLAG_MASK_SRC(param.flag) ==\n+\t\t\t\t TIMER_FLAG_EXT_SRC ? 1 : 0,\n+\t\t\t\t TIMER_FLAG_MASK_HANDLE(param.flag) ==\n+\t\t\t\t TIMER_FLAG_SIGNAL ? TIMER_FLAG_SIGNAL :\n+\t\t\t\t TIMER_FLAG_NO_HANDLE,\n+\t\t\t\t (unsigned long) param.pid,\n+\t\t\t\t (unsigned long) param.sig);\n+\t\tif (ret > 0) {\n+\t\t\tcopy_to_user(&((struct gptu_ioctl_param *) arg)->\n+\t\t\t\t      timer, &ret, sizeof(&ret));\n+\t\t\tret = 0;\n+\t\t}\n+\t\tbreak;\n+\tcase GPTU_SET_COUNTER:\n+\t\tlq_set_counter(param.timer, param.flag, param.value, 0, 0);\n+\t\tif (ret > 0) {\n+\t\t\tcopy_to_user(&((struct gptu_ioctl_param *) arg)->\n+\t\t\t\t      timer, &ret, sizeof(&ret));\n+\t\t\tret = 0;\n+\t\t}\n+\t\tbreak;\n+\tdefault:\n+\t\tret = -ENOTTY;\n+\t}\n+\n+\treturn ret;\n+}\n+\n+static int gptu_open(struct inode *inode, struct file *file)\n+{\n+\treturn 0;\n+}\n+\n+static int gptu_release(struct inode *inode, struct file *file)\n+{\n+\treturn 0;\n+}\n+\n+int __init lq_gptu_init(void)\n+{\n+\tint ret;\n+\tunsigned int i;\n+\n+\tltq_w32(0, LQ_GPTU_IRNEN);\n+\tltq_w32(0xfff, LQ_GPTU_IRNCR);\n+\n+\tmemset(&timer_dev, 0, sizeof(timer_dev));\n+\tmutex_init(&timer_dev.gptu_mutex);\n+\n+\tlq_enable_gptu();\n+\ttimer_dev.number_of_timers = GPTU_ID_CFG * 2;\n+\tlq_disable_gptu();\n+\tif (timer_dev.number_of_timers > MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2)\n+\t\ttimer_dev.number_of_timers = MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2;\n+\tprintk(KERN_INFO \"gptu: totally %d 16-bit timers/counters\\n\", timer_dev.number_of_timers);\n+\n+\tret = misc_register(&gptu_miscdev);\n+\tif (ret) {\n+\t\tprintk(KERN_ERR \"gptu: can't misc_register, get error %d\\n\", -ret);\n+\t\treturn ret;\n+\t} else {\n+\t\tprintk(KERN_INFO \"gptu: misc_register on minor %d\\n\", gptu_miscdev.minor);\n+\t}\n+\n+\tfor (i = 0; i < timer_dev.number_of_timers; i++) {\n+\t\tret = request_irq(TIMER_INTERRUPT + i, timer_irq_handler, IRQF_TIMER, gptu_miscdev.name, &timer_dev.timer[i]);\n+\t\tif (ret) {\n+\t\t\tfor (; i >= 0; i--)\n+\t\t\t\tfree_irq(TIMER_INTERRUPT + i, &timer_dev.timer[i]);\n+\t\t\tmisc_deregister(&gptu_miscdev);\n+\t\t\tprintk(KERN_ERR \"gptu: failed in requesting irq (%d), get error %d\\n\", i, -ret);\n+\t\t\treturn ret;\n+\t\t} else {\n+\t\t\ttimer_dev.timer[i].irq = TIMER_INTERRUPT + i;\n+\t\t\tdisable_irq(timer_dev.timer[i].irq);\n+\t\t\tprintk(KERN_INFO \"gptu: succeeded to request irq %d\\n\", timer_dev.timer[i].irq);\n+\t\t}\n+\t}\n+\n+\treturn 0;\n+}\n+\n+void __exit lq_gptu_exit(void)\n+{\n+\tunsigned int i;\n+\n+\tfor (i = 0; i < timer_dev.number_of_timers; i++) {\n+\t\tif (timer_dev.timer[i].f_irq_on)\n+\t\t\tdisable_irq(timer_dev.timer[i].irq);\n+\t\tfree_irq(timer_dev.timer[i].irq, &timer_dev.timer[i]);\n+\t}\n+\tlq_disable_gptu();\n+\tmisc_deregister(&gptu_miscdev);\n+}\n+\n+module_init(lq_gptu_init);\n+module_exit(lq_gptu_exit);\n+\n+#endif\n"
  },
  {
    "path": "target/linux/lantiq/patches-5.10/0018-MTD-nand-lots-of-xrx200-fixes.patch",
    "content": "From 997a8965db8417266bea3fbdcfa3e5655a1b52fa Mon Sep 17 00:00:00 2001\nFrom: John Crispin <blogic@openwrt.org>\nDate: Tue, 9 Sep 2014 23:12:15 +0200\nSubject: [PATCH 18/36] MTD: nand: lots of xrx200 fixes\n\nSigned-off-by: John Crispin <blogic@openwrt.org>\n---\n drivers/mtd/nand/raw/xway_nand.c |   63 ++++++++++++++++++++++++++++++++++++++++++\n 1 file changed, 63 insertions(+)\n\n--- a/drivers/mtd/nand/raw/xway_nand.c\n+++ b/drivers/mtd/nand/raw/xway_nand.c\n@@ -61,6 +61,24 @@\n #define NAND_CON_CSMUX\t\t(1 << 1)\n #define NAND_CON_NANDM\t\t1\n \n+#define DANUBE_PCI_REG32( addr )    (*(volatile u32 *)(addr))\n+#define PCI_CR_PR_OFFSET\t    (KSEG1+0x1E105400)\n+#define PCI_CR_PC_ARB\t\t    (PCI_CR_PR_OFFSET + 0x0080)\n+\n+/*\n+ * req_mask provides a mechanism to prevent interference between\n+ * nand and pci (probably only relevant for the BT Home Hub 2B).\n+ * Setting it causes the corresponding pci req pins to be masked\n+ * during nand access, and also moves ebu locking from the read/write\n+ * functions to the chip select function to ensure that the whole\n+ * operation runs with interrupts disabled.\n+ * In addition it switches on some extra waiting in xway_cmd_ctrl().\n+ * This seems to be necessary if the ebu_cs1 pin has open-drain disabled,\n+ * which in turn seems to be necessary for the nor chip to be recognised\n+ * reliably, on a board (Home Hub 2B again) which has both nor and nand.\n+ */\n+static __be32 req_mask = 0;\n+\n struct xway_nand_data {\n \tstruct nand_controller\tcontroller;\n \tstruct nand_chip\tchip;\n@@ -92,10 +110,22 @@ static void xway_select_chip(struct nand\n \tcase -1:\n \t\tltq_ebu_w32_mask(NAND_CON_CE, 0, EBU_NAND_CON);\n \t\tltq_ebu_w32_mask(NAND_CON_NANDM, 0, EBU_NAND_CON);\n+\n+\t\tif (req_mask) {\n+\t\t\t/* Unmask all external PCI request */\n+\t\t\tDANUBE_PCI_REG32(PCI_CR_PC_ARB) &= ~(req_mask << 16);\n+\t\t}\n+\n \t\tspin_unlock_irqrestore(&ebu_lock, data->csflags);\n \t\tbreak;\n \tcase 0:\n \t\tspin_lock_irqsave(&ebu_lock, data->csflags);\n+\n+\t\tif (req_mask) {\n+\t\t\t/* Mask all external PCI request */\n+\t\t\tDANUBE_PCI_REG32(PCI_CR_PC_ARB) |= (req_mask << 16);\n+\t\t}\n+\n \t\tltq_ebu_w32_mask(0, NAND_CON_NANDM, EBU_NAND_CON);\n \t\tltq_ebu_w32_mask(0, NAND_CON_CE, EBU_NAND_CON);\n \t\tbreak;\n@@ -108,6 +138,11 @@ static void xway_cmd_ctrl(struct nand_ch\n {\n \tstruct mtd_info *mtd = nand_to_mtd(chip);\n \n+\tif (req_mask) {\n+\t\tif (cmd != NAND_CMD_STATUS)\n+\t\t\tltq_ebu_w32(0, EBU_NAND_WAIT); /* Clear nand ready */\n+\t}\n+\n \tif (cmd == NAND_CMD_NONE)\n \t\treturn;\n \n@@ -118,6 +153,24 @@ static void xway_cmd_ctrl(struct nand_ch\n \n \twhile ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0)\n \t\t;\n+\n+\tif (req_mask) {\n+\t       /*\n+\t\t* program and erase have their own busy handlers\n+\t\t* status and sequential in needs no delay\n+\t\t*/\n+\t\tswitch (cmd) {\n+\t\t\tcase NAND_CMD_ERASE1:\n+\t\t\tcase NAND_CMD_SEQIN:\n+\t\t\tcase NAND_CMD_STATUS:\n+\t\t\tcase NAND_CMD_READID:\n+\t\t\treturn;\n+\t\t}\n+\n+\t\t/* wait until command is processed */\n+\t\twhile ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_RD) == 0)\n+\t\t\t;\n+\t}\n }\n \n static int xway_dev_ready(struct nand_chip *chip)\n@@ -170,6 +223,7 @@ static int xway_nand_probe(struct platfo\n \tint err;\n \tu32 cs;\n \tu32 cs_flag = 0;\n+\tconst __be32 *req_mask_ptr;\n \n \t/* Allocate memory for the device structure (and zero it) */\n \tdata = devm_kzalloc(&pdev->dev, sizeof(struct xway_nand_data),\n@@ -206,6 +260,15 @@ static int xway_nand_probe(struct platfo\n \tif (!err && cs == 1)\n \t\tcs_flag = NAND_CON_IN_CS1 | NAND_CON_OUT_CS1;\n \n+\treq_mask_ptr = of_get_property(pdev->dev.of_node,\n+\t\t\t\t\t\"req-mask\", NULL);\n+\n+\t/*\n+\t * Load the PCI req lines to mask from the device tree. If the\n+\t * property is not present, setting req_mask to 0 disables masking.\n+\t */\n+\treq_mask = (req_mask_ptr ? *req_mask_ptr : 0);\n+\n \t/* setup the EBU to run in NAND mode on our base addr */\n \tltq_ebu_w32(CPHYSADDR(data->nandaddr)\n \t\t    | ADDSEL1_MASK(3) | ADDSEL1_REGEN, EBU_ADDSEL1);\n"
  },
  {
    "path": "target/linux/lantiq/patches-5.10/0020-MTD-lantiq-handle-NO_XIP-on-cfi0001-flash.patch",
    "content": "From e3b20f04e9f9cae1babe091fdc1d08d7703ae344 Mon Sep 17 00:00:00 2001\nFrom: John Crispin <blogic@openwrt.org>\nDate: Thu, 7 Aug 2014 18:18:00 +0200\nSubject: [PATCH 20/36] MTD: lantiq: handle NO_XIP on cfi0001 flash\n\nSigned-off-by: John Crispin <blogic@openwrt.org>\n---\n drivers/mtd/maps/lantiq-flash.c |    6 +++++-\n 1 file changed, 5 insertions(+), 1 deletion(-)\n\n--- a/drivers/mtd/maps/lantiq-flash.c\n+++ b/drivers/mtd/maps/lantiq-flash.c\n@@ -129,7 +129,11 @@ ltq_mtd_probe(struct platform_device *pd\n \tif (!ltq_mtd->map)\n \t\treturn -ENOMEM;\n \n-\tltq_mtd->map->phys = ltq_mtd->res->start;\n+\tif (of_find_property(pdev->dev.of_node, \"lantiq,noxip\", NULL))\n+\t\tltq_mtd->map->phys = NO_XIP;\n+\telse\n+\t\tltq_mtd->map->phys = ltq_mtd->res->start;\n+\tltq_mtd->res->start;\n \tltq_mtd->map->size = resource_size(ltq_mtd->res);\n \tltq_mtd->map->virt = devm_ioremap_resource(&pdev->dev, ltq_mtd->res);\n \tif (IS_ERR(ltq_mtd->map->virt))\n"
  },
  {
    "path": "target/linux/lantiq/patches-5.10/0023-NET-PHY-add-led-support-for-intel-xway.patch",
    "content": "From 0a63ab263725c427051a8bbaa0732b749627da27 Mon Sep 17 00:00:00 2001\nFrom: John Crispin <blogic@openwrt.org>\nDate: Thu, 7 Aug 2014 18:15:36 +0200\nSubject: [PATCH 23/36] NET: PHY: adds driver for lantiq PHY11G\n\nSigned-off-by: John Crispin <blogic@openwrt.org>\n---\n drivers/net/phy/Kconfig  |    5 +\n drivers/net/phy/Makefile |    1 +\n drivers/net/phy/lantiq.c |  231 ++++++++++++++++++++++++++++++++++++++++++++++\n 3 files changed, 237 insertions(+)\n create mode 100644 drivers/net/phy/lantiq.c\n\n--- a/drivers/net/phy/intel-xway.c\n+++ b/drivers/net/phy/intel-xway.c\n@@ -157,6 +157,51 @@\n #define PHY_ID_PHY11G_VR9_1_2\t\t0xD565A409\n #define PHY_ID_PHY22F_VR9_1_2\t\t0xD565A419\n \n+#if IS_ENABLED(CONFIG_OF_MDIO)\n+static int vr9_gphy_of_reg_init(struct phy_device *phydev)\n+{\n+\tu32 tmp;\n+\n+\t/* store the led values if one was passed by the devicetree */\n+\tif (!of_property_read_u32(phydev->mdio.dev.of_node, \"lantiq,ledch\", &tmp))\n+\t\tphy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LEDCH, tmp);\n+\n+\tif (!of_property_read_u32(phydev->mdio.dev.of_node, \"lantiq,ledcl\", &tmp))\n+\t\tphy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LEDCL, tmp);\n+\n+\tif (!of_property_read_u32(phydev->mdio.dev.of_node, \"lantiq,led0h\", &tmp))\n+\t\tphy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED0H, tmp);\n+\n+\tif (!of_property_read_u32(phydev->mdio.dev.of_node, \"lantiq,led0l\", &tmp))\n+\t\tphy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED0L, tmp);\n+\n+\tif (!of_property_read_u32(phydev->mdio.dev.of_node, \"lantiq,led1h\", &tmp))\n+\t\tphy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED1H, tmp);\n+\n+\tif (!of_property_read_u32(phydev->mdio.dev.of_node, \"lantiq,led1l\", &tmp))\n+\t\tphy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED1L, tmp);\n+\n+\tif (!of_property_read_u32(phydev->mdio.dev.of_node, \"lantiq,led2h\", &tmp))\n+\t\tphy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED2H,  tmp);\n+\n+\tif (!of_property_read_u32(phydev->mdio.dev.of_node, \"lantiq,led2l\", &tmp))\n+\t\tphy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED2L, tmp);\n+\n+\tif (!of_property_read_u32(phydev->mdio.dev.of_node, \"lantiq,led3h\", &tmp))\n+\t\tphy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED3H, tmp);\n+\n+\tif (!of_property_read_u32(phydev->mdio.dev.of_node, \"lantiq,led3l\", &tmp))\n+\t\tphy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED3L, tmp);\n+\n+\treturn 0;\n+}\n+#else\n+static int vr9_gphy_of_reg_init(struct phy_device *phydev)\n+{\n+\treturn 0;\n+}\n+#endif /* CONFIG_OF_MDIO */\n+\n static int xway_gphy_config_init(struct phy_device *phydev)\n {\n \tint err;\n@@ -204,6 +249,7 @@ static int xway_gphy_config_init(struct\n \tphy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED2H, ledxh);\n \tphy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED2L, ledxl);\n \n+\tvr9_gphy_of_reg_init(phydev);\n \treturn 0;\n }\n \n--- /dev/null\n+++ b/Documentation/devicetree/bindings/phy/phy-lanitq.txt\n@@ -0,0 +1,216 @@\n+Lanitq PHY binding\n+============================================\n+\n+This devicetree binding controls the lantiq ethernet phys led functionality.\n+\n+Example:\n+\tmdio@0 {\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\tcompatible = \"lantiq,xrx200-mdio\";\n+\t\t\tphy5: ethernet-phy@5 {\n+\t\t\treg = <0x1>;\n+\t\t\tcompatible = \"lantiq,phy11g\", \"ethernet-phy-ieee802.3-c22\";\n+\t\t};\n+\t\tphy11: ethernet-phy@11 {\n+\t\t\treg = <0x11>;\n+\t\t\tcompatible = \"lantiq,phy22f\", \"ethernet-phy-ieee802.3-c22\";\n+\t\t\tlantiq,led2h = <0x00>;\n+\t\t\tlantiq,led2l = <0x03>;\n+\t\t};\n+\t\tphy12: ethernet-phy@12 {\n+\t\t\treg = <0x12>;\n+\t\t\tcompatible = \"lantiq,phy22f\", \"ethernet-phy-ieee802.3-c22\";\n+\t\t\tlantiq,led1h = <0x00>;\n+\t\t\tlantiq,led1l = <0x03>;\n+\t\t};\n+\t\tphy13: ethernet-phy@13 {\n+\t\t\treg = <0x13>;\n+\t\t\tcompatible = \"lantiq,phy22f\", \"ethernet-phy-ieee802.3-c22\";\n+\t\t\tlantiq,led2h = <0x00>;\n+\t\t\tlantiq,led2l = <0x03>;\n+\t\t};\n+\t\tphy14: ethernet-phy@14 {\n+\t\t\treg = <0x14>;\n+\t\t\tcompatible = \"lantiq,phy22f\", \"ethernet-phy-ieee802.3-c22\";\n+\t\t\tlantiq,led1h = <0x00>;\n+\t\t\tlantiq,led1l = <0x03>;\n+\t\t};\n+\t};\n+\n+Register Description\n+============================================\n+\n+LEDCH:\n+\n+Name\tHardware Reset Value\n+LEDCH\t0x00C5\n+\n+| 15 |    |    |    |    |    |    |  8 |\n+=========================================\n+|\t\tRES\t\t\t|\n+=========================================\n+\n+|  7 |    |    |    |    |    |    |  0 |\n+=========================================\n+|   FBF   |   SBF   |RES |     NACS     |\n+=========================================\n+\n+Field\tBits\tType\tDescription\n+FBF\t7:6\tRW\tFast Blink Frequency\n+\t\t\t---\n+\t\t\t0x0 (00b) F02HZ 2 Hz blinking frequency\n+\t\t\t0x1 (01b) F04HZ 4 Hz blinking frequency\n+\t\t\t0x2 (10b) F08HZ 8 Hz blinking frequency\n+\t\t\t0x3 (11b) F16HZ 16 Hz blinking frequency\n+\n+SBF\t5:4\tRW\tSlow Blink Frequency\n+\t\t\t---\n+\t\t\t0x0 (00b) F02HZ 2 Hz blinking frequency\n+\t\t\t0x1 (01b) F04HZ 4 Hz blinking frequency\n+\t\t\t0x2 (10b) F08HZ 8 Hz blinking frequency\n+\t\t\t0x3 (11b) F16HZ 16 Hz blinking frequency\n+\n+NACS\t2:0\tRW\tInverse of Scan Function\n+\t\t\t---\n+\t\t\t0x0 (000b) NONE No Function\n+\t\t\t0x1 (001b) LINK Complex function enabled when link is up\n+\t\t\t0x2 (010b) PDOWN Complex function enabled when device is powered-down\n+\t\t\t0x3 (011b) EEE Complex function enabled when device is in EEE mode\n+\t\t\t0x4 (100b) ANEG Complex function enabled when auto-negotiation is running\n+\t\t\t0x5 (101b) ABIST Complex function enabled when analog self-test is running\n+\t\t\t0x6 (110b) CDIAG Complex function enabled when cable diagnostics are running\n+\t\t\t0x7 (111b) TEST Complex function enabled when test mode is running\n+\n+LEDCL:\n+\n+Name\tHardware Reset Value\n+LEDCL\t0x0067\n+\n+| 15 |    |    |    |    |    |    |  8 |\n+=========================================\n+|\t\tRES\t\t\t|\n+=========================================\n+\n+|  7 |    |    |    |    |    |    |  0 |\n+=========================================\n+|RES |     SCAN     |RES |    CBLINK    |\n+=========================================\n+\n+Field\tBits\tType\tDescription\n+SCAN\t6:4\tRW\tComplex Scan Configuration\n+\t\t\t---\n+\t\t\t000 B NONE No Function\n+\t\t\t001 B LINK Complex function enabled when link is up\n+\t\t\t010 B PDOWN Complex function enabled when device is powered-down\n+\t\t\t011 B EEE Complex function enabled when device is in EEE mode\n+\t\t\t100 B ANEG Complex function enabled when auto-negotiation is running\n+\t\t\t101 B ABIST Complex function enabled when analog self-test is running\n+\t\t\t110 B CDIAG Complex function enabled when cable diagnostics are running\n+\t\t\t111 B TEST Complex function enabled when test mode is running\n+\n+CBLINK\t2:0\tRW\tComplex Blinking Configuration\n+\t\t\t---\n+\t\t\t000 B NONE No Function\n+\t\t\t001 B LINK Complex function enabled when link is up\n+\t\t\t010 B PDOWN Complex function enabled when device is powered-down\n+\t\t\t011 B EEE Complex function enabled when device is in EEE mode\n+\t\t\t100 B ANEG Complex function enabled when auto-negotiation is running\n+\t\t\t101 B ABIST Complex function enabled when analog self-test is running\n+\t\t\t110 B CDIAG Complex function enabled when cable diagnostics are running\n+\t\t\t111 B TEST Complex function enabled when test mode is running\n+\n+LEDxH:\n+\n+Name\tHardware Reset Value\n+LED0H\t0x0070\n+LED1H\t0x0020\n+LED2H\t0x0040\n+LED3H\t0x0040\n+\n+| 15 |    |    |    |    |    |    |  8 |\n+=========================================\n+|\t\tRES\t\t\t|\n+=========================================\n+\n+|  7 |    |    |    |    |    |    |  0 |\n+=========================================\n+|        CON        |       BLINKF      |\n+=========================================\n+\n+Field\tBits\tType\tDescription\n+CON\t7:4\tRW\tConstant On Configuration\n+\t\t\t---\n+\t\t\t0x0 (0000b) NONE LED does not light up constantly\n+\t\t\t0x1 (0001b) LINK10 LED is on when link is 10 Mbit/s\n+\t\t\t0x2 (0010b) LINK100 LED is on when link is 100 Mbit/s\n+\t\t\t0x3 (0011b) LINK10X LED is on when link is 10/100 Mbit/s\n+\t\t\t0x4 (0100b) LINK1000 LED is on when link is 1000 Mbit/s\n+\t\t\t0x5 (0101b) LINK10_0 LED is on when link is 10/1000 Mbit/s\n+\t\t\t0x6 (0110b) LINK100X LED is on when link is 100/1000 Mbit/s\n+\t\t\t0x7 (0111b) LINK10XX LED is on when link is 10/100/1000 Mbit/s\n+\t\t\t0x8 (1000b) PDOWN LED is on when device is powered-down\n+\t\t\t0x9 (1001b) EEE LED is on when device is in EEE mode\n+\t\t\t0xA (1010b) ANEG LED is on when auto-negotiation is running\n+\t\t\t0xB (1011b) ABIST LED is on when analog self-test is running\n+\t\t\t0xC (1100b) CDIAG LED is on when cable diagnostics are running\n+\n+BLINKF\t3:0\tRW\tFast Blinking Configuration\n+\t\t\t---\n+\t\t\t0x0 (0000b) NONE No Blinking\n+\t\t\t0x1 (0001b) LINK10 Blink when link is 10 Mbit/s\n+\t\t\t0x2 (0010b) LINK100 Blink when link is 100 Mbit/s\n+\t\t\t0x3 (0011b) LINK10X Blink when link is 10/100 Mbit/s\n+\t\t\t0x4 (0100b) LINK1000 Blink when link is 1000 Mbit/s\n+\t\t\t0x5 (0101b) LINK10_0 Blink when link is 10/1000 Mbit/s\n+\t\t\t0x6 (0110b) LINK100X Blink when link is 100/1000 Mbit/s\n+\t\t\t0x7 (0111b) LINK10XX Blink when link is 10/100/1000 Mbit/s\n+\t\t\t0x8 (1000b) PDOWN Blink when device is powered-down\n+\t\t\t0x9 (1001b) EEE Blink when device is in EEE mode\n+\t\t\t0xA (1010b) ANEG Blink when auto-negotiation is running\n+\t\t\t0xB (1011b) ABIST Blink when analog self-test is running\n+\t\t\t0xC (1100b) CDIAG Blink when cable diagnostics are running\n+\n+LEDxL:\n+\n+Name\tHardware Reset Value\n+LED0L\t0x0003\n+LED1L\t0x0000\n+LED2L\t0x0000\n+LED3L\t0x0020\n+\n+| 15 |    |    |    |    |    |    |  8 |\n+=========================================\n+|\t\tRES\t\t\t|\n+=========================================\n+\n+|  7 |    |    |    |    |    |    |  0 |\n+=========================================\n+|      BLINKS       |       PULSE       |\n+=========================================\n+\n+Field\tBits\tType\tDescription\n+BLINKS\t7:4\tRW\tSlow Blinkin Configuration\n+\t\t\t---\n+\t\t\t0x0 (0000b) NONE No Blinking\n+\t\t\t0x1 (0001b) LINK10 Blink when link is 10 Mbit/s\n+\t\t\t0x2 (0010b) LINK100 Blink when link is 100 Mbit/s\n+\t\t\t0x3 (0011b) LINK10X Blink when link is 10/100 Mbit/s\n+\t\t\t0x4 (0100b) LINK1000 Blink when link is 1000 Mbit/s\n+\t\t\t0x5 (0101b) LINK10_0 Blink when link is 10/1000 Mbit/s\n+\t\t\t0x6 (0110b) LINK100X Blink when link is 100/1000 Mbit/s\n+\t\t\t0x7 (0111b) LINK10XX Blink when link is 10/100/1000 Mbit/s\n+\t\t\t0x8 (1000b) PDOWN Blink when device is powered-down\n+\t\t\t0x9 (1001b) EEE Blink when device is in EEE mode\n+\t\t\t0xA (1010b) ANEG Blink when auto-negotiation is running\n+\t\t\t0xB (1011b) ABIST Blink when analog self-test is running\n+\t\t\t0xC (1100b) CDIAG Blink when cable diagnostics are runningning\n+\n+PULSE\t3:0\tRW\tPulsing Configuration\n+\t\t\tThe pulse field is a mask field by which certain events can be combined\n+\t\t\t---\n+\t\t\t0x0 (0000b) NONE No pulsing\n+\t\t\t0x1 (0001b) TXACT Transmit activity\n+\t\t\t0x2 (0010b) RXACT Receive activity\n+\t\t\t0x4 (0100b) COL Collision\n+\t\t\t0x8 (1000b) RES Reserved\n"
  },
  {
    "path": "target/linux/lantiq/patches-5.10/0028-NET-lantiq-various-etop-fixes.patch",
    "content": "From 870ed9cae083ff8a60a739ef7e74c5a1800533be Mon Sep 17 00:00:00 2001\nFrom: John Crispin <blogic@openwrt.org>\nDate: Tue, 9 Sep 2014 22:45:34 +0200\nSubject: [PATCH 28/36] NET: lantiq: various etop fixes\n\nSigned-off-by: John Crispin <blogic@openwrt.org>\n---\n drivers/net/ethernet/lantiq_etop.c |  555 +++++++++++++++++++++++++-----------\n 1 file changed, 389 insertions(+), 166 deletions(-)\n\n--- a/drivers/net/ethernet/lantiq_etop.c\n+++ b/drivers/net/ethernet/lantiq_etop.c\n@@ -1,7 +1,7 @@\n // SPDX-License-Identifier: GPL-2.0-only\n /*\n  *\n- *   Copyright (C) 2011 John Crispin <blogic@openwrt.org>\n+ *   Copyright (C) 2011-12 John Crispin <blogic@openwrt.org>\n  */\n \n #include <linux/kernel.h>\n@@ -20,11 +20,16 @@\n #include <linux/mm.h>\n #include <linux/platform_device.h>\n #include <linux/ethtool.h>\n+#include <linux/if_vlan.h>\n #include <linux/init.h>\n #include <linux/delay.h>\n #include <linux/io.h>\n #include <linux/dma-mapping.h>\n #include <linux/module.h>\n+#include <linux/clk.h>\n+#include <linux/of_net.h>\n+#include <linux/of_irq.h>\n+#include <linux/of_platform.h>\n \n #include <asm/checksum.h>\n \n@@ -32,7 +37,7 @@\n #include <xway_dma.h>\n #include <lantiq_platform.h>\n \n-#define LTQ_ETOP_MDIO\t\t0x11804\n+#define LTQ_ETOP_MDIO_ACC\t0x11804\n #define MDIO_REQUEST\t\t0x80000000\n #define MDIO_READ\t\t0x40000000\n #define MDIO_ADDR_MASK\t\t0x1f\n@@ -41,44 +46,91 @@\n #define MDIO_REG_OFFSET\t\t0x10\n #define MDIO_VAL_MASK\t\t0xffff\n \n-#define PPE32_CGEN\t\t0x800\n-#define LQ_PPE32_ENET_MAC_CFG\t0x1840\n+#define LTQ_ETOP_MDIO_CFG       0x11800\n+#define MDIO_CFG_MASK           0x6\n+\n+#define LTQ_ETOP_CFG            0x11808\n+#define LTQ_ETOP_IGPLEN         0x11820\n+#define LTQ_ETOP_MAC_CFG\t0x11840\n \n #define LTQ_ETOP_ENETS0\t\t0x11850\n #define LTQ_ETOP_MAC_DA0\t0x1186C\n #define LTQ_ETOP_MAC_DA1\t0x11870\n-#define LTQ_ETOP_CFG\t\t0x16020\n-#define LTQ_ETOP_IGPLEN\t\t0x16080\n+\n+#define MAC_CFG_MASK\t\t0xfff\n+#define MAC_CFG_CGEN\t\t(1 << 11)\n+#define MAC_CFG_DUPLEX\t\t(1 << 2)\n+#define MAC_CFG_SPEED\t\t(1 << 1)\n+#define MAC_CFG_LINK\t\t(1 << 0)\n \n #define MAX_DMA_CHAN\t\t0x8\n #define MAX_DMA_CRC_LEN\t\t0x4\n #define MAX_DMA_DATA_LEN\t0x600\n \n #define ETOP_FTCU\t\tBIT(28)\n-#define ETOP_MII_MASK\t\t0xf\n-#define ETOP_MII_NORMAL\t\t0xd\n-#define ETOP_MII_REVERSE\t0xe\n #define ETOP_PLEN_UNDER\t\t0x40\n-#define ETOP_CGEN\t\t0x800\n+#define ETOP_CFG_MII0\t\t0x01\n \n-/* use 2 static channels for TX/RX */\n-#define LTQ_ETOP_TX_CHANNEL\t1\n-#define LTQ_ETOP_RX_CHANNEL\t6\n-#define IS_TX(x)\t\t(x == LTQ_ETOP_TX_CHANNEL)\n-#define IS_RX(x)\t\t(x == LTQ_ETOP_RX_CHANNEL)\n+#define ETOP_CFG_MASK           0xfff\n+#define ETOP_CFG_FEN0\t\t(1 << 8)\n+#define ETOP_CFG_SEN0\t\t(1 << 6)\n+#define ETOP_CFG_OFF1\t\t(1 << 3)\n+#define ETOP_CFG_REMII0\t\t(1 << 1)\n+#define ETOP_CFG_OFF0\t\t(1 << 0)\n+\n+#define LTQ_GBIT_MDIO_CTL\t0xCC\n+#define LTQ_GBIT_MDIO_DATA\t0xd0\n+#define LTQ_GBIT_GCTL0\t\t0x68\n+#define LTQ_GBIT_PMAC_HD_CTL\t0x8c\n+#define LTQ_GBIT_P0_CTL\t\t0x4\n+#define LTQ_GBIT_PMAC_RX_IPG\t0xa8\n+#define LTQ_GBIT_RGMII_CTL\t0x78\n+\n+#define PMAC_HD_CTL_AS\t\t(1 << 19)\n+#define PMAC_HD_CTL_RXSH\t(1 << 22)\n+\n+/* Switch Enable (0=disable, 1=enable) */\n+#define GCTL0_SE\t\t0x80000000\n+/* Disable MDIO auto polling (0=disable, 1=enable) */\n+#define PX_CTL_DMDIO\t\t0x00400000\n+\n+/* MDC clock divider, clock = 25MHz/((MDC_CLOCK + 1) * 2) */\n+#define MDC_CLOCK_MASK\t\t0xff000000\n+#define MDC_CLOCK_OFFSET\t24\n+\n+/* register information for the gbit's MDIO bus */\n+#define MDIO_XR9_REQUEST\t0x00008000\n+#define MDIO_XR9_READ\t\t0x00000800\n+#define MDIO_XR9_WRITE\t\t0x00000400\n+#define MDIO_XR9_REG_MASK\t0x1f\n+#define MDIO_XR9_ADDR_MASK\t0x1f\n+#define MDIO_XR9_RD_MASK\t0xffff\n+#define MDIO_XR9_REG_OFFSET\t0\n+#define MDIO_XR9_ADDR_OFFSET\t5\n+#define MDIO_XR9_WR_OFFSET\t16\n \n+#define LTQ_DMA_ETOP\t((of_machine_is_compatible(\"lantiq,ase\")) ? \\\n+\t\t\t(INT_NUM_IM3_IRL0) : (INT_NUM_IM2_IRL0))\n+\n+/* the newer xway socks have a embedded 3/7 port gbit multiplexer */\n #define ltq_etop_r32(x)\t\tltq_r32(ltq_etop_membase + (x))\n #define ltq_etop_w32(x, y)\tltq_w32(x, ltq_etop_membase + (y))\n #define ltq_etop_w32_mask(x, y, z)\t\\\n \t\tltq_w32_mask(x, y, ltq_etop_membase + (z))\n \n-#define DRV_VERSION\t\"1.0\"\n+#define ltq_gbit_r32(x)\t\tltq_r32(ltq_gbit_membase + (x))\n+#define ltq_gbit_w32(x, y)\tltq_w32(x, ltq_gbit_membase + (y))\n+#define ltq_gbit_w32_mask(x, y, z)\t\\\n+\t\tltq_w32_mask(x, y, ltq_gbit_membase + (z))\n+\n+#define DRV_VERSION\t\"1.2\"\n \n static void __iomem *ltq_etop_membase;\n+static void __iomem *ltq_gbit_membase;\n \n struct ltq_etop_chan {\n-\tint idx;\n \tint tx_free;\n+\tint irq;\n \tstruct net_device *netdev;\n \tstruct napi_struct napi;\n \tstruct ltq_dma_channel dma;\n@@ -88,23 +140,36 @@ struct ltq_etop_chan {\n struct ltq_etop_priv {\n \tstruct net_device *netdev;\n \tstruct platform_device *pdev;\n-\tstruct ltq_eth_data *pldata;\n \tstruct resource *res;\n \n \tstruct mii_bus *mii_bus;\n \n-\tstruct ltq_etop_chan ch[MAX_DMA_CHAN];\n-\tint tx_free[MAX_DMA_CHAN >> 1];\n+\tstruct ltq_etop_chan txch;\n+\tstruct ltq_etop_chan rxch;\n \n-\tspinlock_t lock;\n+\tint tx_irq;\n+\tint rx_irq;\n+\n+\tunsigned char mac[6];\n+\tphy_interface_t mii_mode;\n+ \n+ \tspinlock_t lock;\n+\n+\tstruct clk *clk_ppe;\n+\tstruct clk *clk_switch;\n+\tstruct clk *clk_ephy;\n+\tstruct clk *clk_ephycgu;\n };\n \n+static int ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr,\n+\t\t\t\tint phy_reg, u16 phy_data);\n+\n static int\n ltq_etop_alloc_skb(struct ltq_etop_chan *ch)\n {\n \tstruct ltq_etop_priv *priv = netdev_priv(ch->netdev);\n \n-\tch->skb[ch->dma.desc] = netdev_alloc_skb(ch->netdev, MAX_DMA_DATA_LEN);\n+\tch->skb[ch->dma.desc] = dev_alloc_skb(MAX_DMA_DATA_LEN);\n \tif (!ch->skb[ch->dma.desc])\n \t\treturn -ENOMEM;\n \tch->dma.desc_base[ch->dma.desc].addr = dma_map_single(&priv->pdev->dev,\n@@ -139,8 +204,11 @@ ltq_etop_hw_receive(struct ltq_etop_chan\n \tspin_unlock_irqrestore(&priv->lock, flags);\n \n \tskb_put(skb, len);\n+\tskb->dev = ch->netdev;\n \tskb->protocol = eth_type_trans(skb, ch->netdev);\n \tnetif_receive_skb(skb);\n+\tch->netdev->stats.rx_packets++;\n+\tch->netdev->stats.rx_bytes += len;\n }\n \n static int\n@@ -148,7 +216,9 @@ ltq_etop_poll_rx(struct napi_struct *nap\n {\n \tstruct ltq_etop_chan *ch = container_of(napi,\n \t\t\t\tstruct ltq_etop_chan, napi);\n+\tstruct ltq_etop_priv *priv = netdev_priv(ch->netdev);\n \tint work_done = 0;\n+\tunsigned long flags;\n \n \twhile (work_done < budget) {\n \t\tstruct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];\n@@ -160,7 +230,9 @@ ltq_etop_poll_rx(struct napi_struct *nap\n \t}\n \tif (work_done < budget) {\n \t\tnapi_complete_done(&ch->napi, work_done);\n+\t\tspin_lock_irqsave(&priv->lock, flags);\n \t\tltq_dma_ack_irq(&ch->dma);\n+\t\tspin_unlock_irqrestore(&priv->lock, flags);\n \t}\n \treturn work_done;\n }\n@@ -172,12 +244,14 @@ ltq_etop_poll_tx(struct napi_struct *nap\n \t\tcontainer_of(napi, struct ltq_etop_chan, napi);\n \tstruct ltq_etop_priv *priv = netdev_priv(ch->netdev);\n \tstruct netdev_queue *txq =\n-\t\tnetdev_get_tx_queue(ch->netdev, ch->idx >> 1);\n+\t\tnetdev_get_tx_queue(ch->netdev, ch->dma.nr >> 1);\n \tunsigned long flags;\n \n \tspin_lock_irqsave(&priv->lock, flags);\n \twhile ((ch->dma.desc_base[ch->tx_free].ctl &\n \t\t\t(LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) {\n+\t\tch->netdev->stats.tx_packets++;\n+\t\tch->netdev->stats.tx_bytes += ch->skb[ch->tx_free]->len;\n \t\tdev_kfree_skb_any(ch->skb[ch->tx_free]);\n \t\tch->skb[ch->tx_free] = NULL;\n \t\tmemset(&ch->dma.desc_base[ch->tx_free], 0,\n@@ -190,7 +264,9 @@ ltq_etop_poll_tx(struct napi_struct *nap\n \tif (netif_tx_queue_stopped(txq))\n \t\tnetif_tx_start_queue(txq);\n \tnapi_complete(&ch->napi);\n+\tspin_lock_irqsave(&priv->lock, flags);\n \tltq_dma_ack_irq(&ch->dma);\n+\tspin_unlock_irqrestore(&priv->lock, flags);\n \treturn 1;\n }\n \n@@ -198,9 +274,10 @@ static irqreturn_t\n ltq_etop_dma_irq(int irq, void *_priv)\n {\n \tstruct ltq_etop_priv *priv = _priv;\n-\tint ch = irq - LTQ_DMA_CH0_INT;\n-\n-\tnapi_schedule(&priv->ch[ch].napi);\n+\tif (irq == priv->txch.dma.irq)\n+\t\tnapi_schedule(&priv->txch.napi);\n+\telse\n+\t\tnapi_schedule(&priv->rxch.napi);\n \treturn IRQ_HANDLED;\n }\n \n@@ -212,7 +289,7 @@ ltq_etop_free_channel(struct net_device\n \tltq_dma_free(&ch->dma);\n \tif (ch->dma.irq)\n \t\tfree_irq(ch->dma.irq, priv);\n-\tif (IS_RX(ch->idx)) {\n+\tif (ch == &priv->txch) {\n \t\tint desc;\n \t\tfor (desc = 0; desc < LTQ_DESC_NUM; desc++)\n \t\t\tdev_kfree_skb_any(ch->skb[ch->dma.desc]);\n@@ -223,66 +300,135 @@ static void\n ltq_etop_hw_exit(struct net_device *dev)\n {\n \tstruct ltq_etop_priv *priv = netdev_priv(dev);\n-\tint i;\n \n-\tltq_pmu_disable(PMU_PPE);\n-\tfor (i = 0; i < MAX_DMA_CHAN; i++)\n-\t\tif (IS_TX(i) || IS_RX(i))\n-\t\t\tltq_etop_free_channel(dev, &priv->ch[i]);\n+\tclk_disable(priv->clk_ppe);\n+\n+\tif (of_machine_is_compatible(\"lantiq,ar9\"))\n+\t\tclk_disable(priv->clk_switch);\n+\n+\tif (of_machine_is_compatible(\"lantiq,ase\")) {\n+\t\tclk_disable(priv->clk_ephy);\n+\t\tclk_disable(priv->clk_ephycgu);\n+\t}\n+\n+\tltq_etop_free_channel(dev, &priv->txch);\n+\tltq_etop_free_channel(dev, &priv->rxch);\n+}\n+\n+static void\n+ltq_etop_gbit_init(struct net_device *dev)\n+{\n+\tstruct ltq_etop_priv *priv = netdev_priv(dev);\n+\n+\tclk_enable(priv->clk_switch);\n+\n+\t/* enable gbit port0 on the SoC */\n+\tltq_gbit_w32_mask((1 << 17), (1 << 18), LTQ_GBIT_P0_CTL);\n+\n+\tltq_gbit_w32_mask(0, GCTL0_SE, LTQ_GBIT_GCTL0);\n+\t/* disable MDIO auto polling mode */\n+\tltq_gbit_w32_mask(0, PX_CTL_DMDIO, LTQ_GBIT_P0_CTL);\n+\t/* set 1522 packet size */\n+\tltq_gbit_w32_mask(0x300, 0, LTQ_GBIT_GCTL0);\n+\t/* disable pmac & dmac headers */\n+\tltq_gbit_w32_mask(PMAC_HD_CTL_AS | PMAC_HD_CTL_RXSH, 0,\n+\t\tLTQ_GBIT_PMAC_HD_CTL);\n+\t/* Due to traffic halt when burst length 8,\n+\t\treplace default IPG value with 0x3B */\n+\tltq_gbit_w32(0x3B, LTQ_GBIT_PMAC_RX_IPG);\n+\t/* set mdc clock to 2.5 MHz */\n+\tltq_gbit_w32_mask(MDC_CLOCK_MASK, 4 << MDC_CLOCK_OFFSET,\n+\t\tLTQ_GBIT_RGMII_CTL);\n }\n \n static int\n ltq_etop_hw_init(struct net_device *dev)\n {\n \tstruct ltq_etop_priv *priv = netdev_priv(dev);\n-\tint i;\n+\tphy_interface_t mii_mode = priv->mii_mode;\n \n-\tltq_pmu_enable(PMU_PPE);\n+\tclk_enable(priv->clk_ppe);\n \n-\tswitch (priv->pldata->mii_mode) {\n+\tif (of_machine_is_compatible(\"lantiq,ar9\")) {\n+\t\tltq_etop_gbit_init(dev);\n+\t\t/* force the etops link to the gbit to MII */\n+\t\tmii_mode = PHY_INTERFACE_MODE_MII;\n+\t}\n+\tltq_etop_w32_mask(MDIO_CFG_MASK, 0, LTQ_ETOP_MDIO_CFG);\n+\tltq_etop_w32_mask(MAC_CFG_MASK, MAC_CFG_CGEN | MAC_CFG_DUPLEX |\n+\t\t\tMAC_CFG_SPEED | MAC_CFG_LINK, LTQ_ETOP_MAC_CFG);\n+\n+\tswitch (mii_mode) {\n \tcase PHY_INTERFACE_MODE_RMII:\n-\t\tltq_etop_w32_mask(ETOP_MII_MASK,\n-\t\t\tETOP_MII_REVERSE, LTQ_ETOP_CFG);\n+\t\tltq_etop_w32_mask(ETOP_CFG_MASK, ETOP_CFG_REMII0 | ETOP_CFG_OFF1 |\n+\t\t\tETOP_CFG_SEN0 | ETOP_CFG_FEN0, LTQ_ETOP_CFG);\n \t\tbreak;\n \n \tcase PHY_INTERFACE_MODE_MII:\n-\t\tltq_etop_w32_mask(ETOP_MII_MASK,\n-\t\t\tETOP_MII_NORMAL, LTQ_ETOP_CFG);\n+\t\tltq_etop_w32_mask(ETOP_CFG_MASK, ETOP_CFG_OFF1 |\n+\t\t\tETOP_CFG_SEN0 | ETOP_CFG_FEN0, LTQ_ETOP_CFG);\n \t\tbreak;\n \n \tdefault:\n+\t\tif (of_machine_is_compatible(\"lantiq,ase\")) {\n+\t\t\tclk_enable(priv->clk_ephy);\n+\t\t\t/* disable external MII */\n+\t\t\tltq_etop_w32_mask(0, ETOP_CFG_MII0, LTQ_ETOP_CFG);\n+\t\t\t/* enable clock for internal PHY */\n+\t\t\tclk_enable(priv->clk_ephycgu);\n+\t\t\t/* we need to write this magic to the internal phy to\n+\t\t\t   make it work */\n+\t\t\tltq_etop_mdio_wr(NULL, 0x8, 0x12, 0xC020);\n+\t\t\tpr_info(\"Selected EPHY mode\\n\");\n+\t\t\tbreak;\n+\t\t}\n \t\tnetdev_err(dev, \"unknown mii mode %d\\n\",\n-\t\t\tpriv->pldata->mii_mode);\n+\t\t\tmii_mode);\n \t\treturn -ENOTSUPP;\n \t}\n \n-\t/* enable crc generation */\n-\tltq_etop_w32(PPE32_CGEN, LQ_PPE32_ENET_MAC_CFG);\n+\treturn 0;\n+}\n+\n+static int\n+ltq_etop_dma_init(struct net_device *dev)\n+{\n+\tstruct ltq_etop_priv *priv = netdev_priv(dev);\n+\tint tx = priv->tx_irq - LTQ_DMA_ETOP;\n+\tint rx = priv->rx_irq - LTQ_DMA_ETOP;\n+\tint err;\n \n \tltq_dma_init_port(DMA_PORT_ETOP);\n \n-\tfor (i = 0; i < MAX_DMA_CHAN; i++) {\n-\t\tint irq = LTQ_DMA_CH0_INT + i;\n-\t\tstruct ltq_etop_chan *ch = &priv->ch[i];\n-\n-\t\tch->idx = ch->dma.nr = i;\n-\t\tch->dma.dev = &priv->pdev->dev;\n-\n-\t\tif (IS_TX(i)) {\n-\t\t\tltq_dma_alloc_tx(&ch->dma);\n-\t\t\trequest_irq(irq, ltq_etop_dma_irq, 0, \"etop_tx\", priv);\n-\t\t} else if (IS_RX(i)) {\n-\t\t\tltq_dma_alloc_rx(&ch->dma);\n-\t\t\tfor (ch->dma.desc = 0; ch->dma.desc < LTQ_DESC_NUM;\n-\t\t\t\t\tch->dma.desc++)\n-\t\t\t\tif (ltq_etop_alloc_skb(ch))\n-\t\t\t\t\treturn -ENOMEM;\n-\t\t\tch->dma.desc = 0;\n-\t\t\trequest_irq(irq, ltq_etop_dma_irq, 0, \"etop_rx\", priv);\n+\tpriv->txch.dma.nr = tx;\n+\tpriv->txch.dma.dev = &priv->pdev->dev;\n+\tltq_dma_alloc_tx(&priv->txch.dma);\n+\terr = request_irq(priv->tx_irq, ltq_etop_dma_irq, 0, \"eth_tx\", priv);\n+\tif (err) {\n+\t\tnetdev_err(dev, \"failed to allocate tx irq\\n\");\n+\t\tgoto err_out;\n+\t}\n+\tpriv->txch.dma.irq = priv->tx_irq;\n+\n+\tpriv->rxch.dma.nr = rx;\n+\tpriv->rxch.dma.dev = &priv->pdev->dev;\n+\tltq_dma_alloc_rx(&priv->rxch.dma);\n+\tfor (priv->rxch.dma.desc = 0; priv->rxch.dma.desc < LTQ_DESC_NUM;\n+\t\t\tpriv->rxch.dma.desc++) {\n+\t\tif (ltq_etop_alloc_skb(&priv->rxch)) {\n+\t\t\tnetdev_err(dev, \"failed to allocate skbs\\n\");\n+\t\t\terr = -ENOMEM;\n+\t\t\tgoto err_out;\n \t\t}\n-\t\tch->dma.irq = irq;\n \t}\n-\treturn 0;\n+\tpriv->rxch.dma.desc = 0;\n+\terr = request_irq(priv->rx_irq, ltq_etop_dma_irq, 0, \"eth_rx\", priv);\n+\tif (err)\n+\t\tnetdev_err(dev, \"failed to allocate rx irq\\n\");\n+\telse\n+\t\tpriv->rxch.dma.irq = priv->rx_irq;\n+err_out:\n+\treturn err;\n }\n \n static void\n@@ -301,6 +447,39 @@ static const struct ethtool_ops ltq_etop\n };\n \n static int\n+ltq_etop_mdio_wr_xr9(struct mii_bus *bus, int phy_addr,\n+\t\tint phy_reg, u16 phy_data)\n+{\n+\tu32 val = MDIO_XR9_REQUEST | MDIO_XR9_WRITE |\n+\t\t(phy_data << MDIO_XR9_WR_OFFSET) |\n+\t\t((phy_addr & MDIO_XR9_ADDR_MASK) << MDIO_XR9_ADDR_OFFSET) |\n+\t\t((phy_reg & MDIO_XR9_REG_MASK) << MDIO_XR9_REG_OFFSET);\n+\n+\twhile (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST)\n+\t\t;\n+\tltq_gbit_w32(val, LTQ_GBIT_MDIO_CTL);\n+\twhile (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST)\n+\t\t;\n+\treturn 0;\n+}\n+\n+static int\n+ltq_etop_mdio_rd_xr9(struct mii_bus *bus, int phy_addr, int phy_reg)\n+{\n+\tu32 val = MDIO_XR9_REQUEST | MDIO_XR9_READ |\n+\t\t((phy_addr & MDIO_XR9_ADDR_MASK) << MDIO_XR9_ADDR_OFFSET) |\n+\t\t((phy_reg & MDIO_XR9_REG_MASK) << MDIO_XR9_REG_OFFSET);\n+\n+\twhile (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST)\n+\t\t;\n+\tltq_gbit_w32(val, LTQ_GBIT_MDIO_CTL);\n+\twhile (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST)\n+\t\t;\n+\tval = ltq_gbit_r32(LTQ_GBIT_MDIO_DATA) & MDIO_XR9_RD_MASK;\n+\treturn val;\n+}\n+\n+static int\n ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr, int phy_reg, u16 phy_data)\n {\n \tu32 val = MDIO_REQUEST |\n@@ -308,9 +487,9 @@ ltq_etop_mdio_wr(struct mii_bus *bus, in\n \t\t((phy_reg & MDIO_REG_MASK) << MDIO_REG_OFFSET) |\n \t\tphy_data;\n \n-\twhile (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST)\n+\twhile (ltq_etop_r32(LTQ_ETOP_MDIO_ACC) & MDIO_REQUEST)\n \t\t;\n-\tltq_etop_w32(val, LTQ_ETOP_MDIO);\n+\tltq_etop_w32(val, LTQ_ETOP_MDIO_ACC);\n \treturn 0;\n }\n \n@@ -321,12 +500,12 @@ ltq_etop_mdio_rd(struct mii_bus *bus, in\n \t\t((phy_addr & MDIO_ADDR_MASK) << MDIO_ADDR_OFFSET) |\n \t\t((phy_reg & MDIO_REG_MASK) << MDIO_REG_OFFSET);\n \n-\twhile (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST)\n+\twhile (ltq_etop_r32(LTQ_ETOP_MDIO_ACC) & MDIO_REQUEST)\n \t\t;\n-\tltq_etop_w32(val, LTQ_ETOP_MDIO);\n-\twhile (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST)\n+\tltq_etop_w32(val, LTQ_ETOP_MDIO_ACC);\n+\twhile (ltq_etop_r32(LTQ_ETOP_MDIO_ACC) & MDIO_REQUEST)\n \t\t;\n-\tval = ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_VAL_MASK;\n+\tval = ltq_etop_r32(LTQ_ETOP_MDIO_ACC) & MDIO_VAL_MASK;\n \treturn val;\n }\n \n@@ -342,7 +521,10 @@ ltq_etop_mdio_probe(struct net_device *d\n \tstruct ltq_etop_priv *priv = netdev_priv(dev);\n \tstruct phy_device *phydev;\n \n-\tphydev = phy_find_first(priv->mii_bus);\n+\tif (of_machine_is_compatible(\"lantiq,ase\"))\n+\t\tphydev = mdiobus_get_phy(priv->mii_bus, 8);\n+\telse\n+\t\tphydev = mdiobus_get_phy(priv->mii_bus, 0);\n \n \tif (!phydev) {\n \t\tnetdev_err(dev, \"no PHY found\\n\");\n@@ -350,14 +532,17 @@ ltq_etop_mdio_probe(struct net_device *d\n \t}\n \n \tphydev = phy_connect(dev, phydev_name(phydev),\n-\t\t\t     &ltq_etop_mdio_link, priv->pldata->mii_mode);\n+\t\t\t     &ltq_etop_mdio_link, priv->mii_mode);\n \n \tif (IS_ERR(phydev)) {\n \t\tnetdev_err(dev, \"Could not attach to PHY\\n\");\n \t\treturn PTR_ERR(phydev);\n \t}\n \n-\tphy_set_max_speed(phydev, SPEED_100);\n+\tif (of_machine_is_compatible(\"lantiq,ar9\"))\n+\t\tphy_set_max_speed(phydev, SPEED_1000);\n+\telse\n+\t\tphy_set_max_speed(phydev, SPEED_100);\n \n \tphy_attached_info(phydev);\n \n@@ -378,8 +563,13 @@ ltq_etop_mdio_init(struct net_device *de\n \t}\n \n \tpriv->mii_bus->priv = dev;\n-\tpriv->mii_bus->read = ltq_etop_mdio_rd;\n-\tpriv->mii_bus->write = ltq_etop_mdio_wr;\n+\tif (of_machine_is_compatible(\"lantiq,ar9\")) {\n+\t\tpriv->mii_bus->read = ltq_etop_mdio_rd_xr9;\n+\t\tpriv->mii_bus->write = ltq_etop_mdio_wr_xr9;\n+\t} else {\n+\t\tpriv->mii_bus->read = ltq_etop_mdio_rd;\n+\t\tpriv->mii_bus->write = ltq_etop_mdio_wr;\n+\t}\n \tpriv->mii_bus->name = \"ltq_mii\";\n \tsnprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, \"%s-%x\",\n \t\tpriv->pdev->name, priv->pdev->id);\n@@ -416,18 +606,21 @@ static int\n ltq_etop_open(struct net_device *dev)\n {\n \tstruct ltq_etop_priv *priv = netdev_priv(dev);\n-\tint i;\n+\tunsigned long flags;\n \n-\tfor (i = 0; i < MAX_DMA_CHAN; i++) {\n-\t\tstruct ltq_etop_chan *ch = &priv->ch[i];\n+\tnapi_enable(&priv->txch.napi);\n+\tnapi_enable(&priv->rxch.napi);\n+\n+\tspin_lock_irqsave(&priv->lock, flags);\n+\tltq_dma_open(&priv->txch.dma);\n+\tltq_dma_enable_irq(&priv->txch.dma);\n+\tltq_dma_open(&priv->rxch.dma);\n+\tltq_dma_enable_irq(&priv->rxch.dma);\n+\tspin_unlock_irqrestore(&priv->lock, flags);\n+\n+\tif (dev->phydev)\n+\t\tphy_start(dev->phydev);\n \n-\t\tif (!IS_TX(i) && (!IS_RX(i)))\n-\t\t\tcontinue;\n-\t\tltq_dma_open(&ch->dma);\n-\t\tltq_dma_enable_irq(&ch->dma);\n-\t\tnapi_enable(&ch->napi);\n-\t}\n-\tphy_start(dev->phydev);\n \tnetif_tx_start_all_queues(dev);\n \treturn 0;\n }\n@@ -436,18 +629,19 @@ static int\n ltq_etop_stop(struct net_device *dev)\n {\n \tstruct ltq_etop_priv *priv = netdev_priv(dev);\n-\tint i;\n+\tunsigned long flags;\n \n \tnetif_tx_stop_all_queues(dev);\n-\tphy_stop(dev->phydev);\n-\tfor (i = 0; i < MAX_DMA_CHAN; i++) {\n-\t\tstruct ltq_etop_chan *ch = &priv->ch[i];\n-\n-\t\tif (!IS_RX(i) && !IS_TX(i))\n-\t\t\tcontinue;\n-\t\tnapi_disable(&ch->napi);\n-\t\tltq_dma_close(&ch->dma);\n-\t}\n+\tif (dev->phydev)\n+\t\tphy_stop(dev->phydev);\n+\tnapi_disable(&priv->txch.napi);\n+\tnapi_disable(&priv->rxch.napi);\n+\n+\tspin_lock_irqsave(&priv->lock, flags);\n+\tltq_dma_close(&priv->txch.dma);\n+\tltq_dma_close(&priv->rxch.dma);\n+\tspin_unlock_irqrestore(&priv->lock, flags);\n+\n \treturn 0;\n }\n \n@@ -457,16 +651,16 @@ ltq_etop_tx(struct sk_buff *skb, struct\n \tint queue = skb_get_queue_mapping(skb);\n \tstruct netdev_queue *txq = netdev_get_tx_queue(dev, queue);\n \tstruct ltq_etop_priv *priv = netdev_priv(dev);\n-\tstruct ltq_etop_chan *ch = &priv->ch[(queue << 1) | 1];\n-\tstruct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];\n-\tint len;\n+\tstruct ltq_dma_desc *desc =\n+\t\t&priv->txch.dma.desc_base[priv->txch.dma.desc];\n \tunsigned long flags;\n \tu32 byte_offset;\n+\tint len;\n \n \tlen = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len;\n \n-\tif ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) || ch->skb[ch->dma.desc]) {\n-\t\tdev_kfree_skb_any(skb);\n+\tif ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) ||\n+\t\t\tpriv->txch.skb[priv->txch.dma.desc]) {\n \t\tnetdev_err(dev, \"tx ring full\\n\");\n \t\tnetif_tx_stop_queue(txq);\n \t\treturn NETDEV_TX_BUSY;\n@@ -474,7 +668,7 @@ ltq_etop_tx(struct sk_buff *skb, struct\n \n \t/* dma needs to start on a 16 byte aligned address */\n \tbyte_offset = CPHYSADDR(skb->data) % 16;\n-\tch->skb[ch->dma.desc] = skb;\n+\tpriv->txch.skb[priv->txch.dma.desc] = skb;\n \n \tnetif_trans_update(dev);\n \n@@ -484,11 +678,11 @@ ltq_etop_tx(struct sk_buff *skb, struct\n \twmb();\n \tdesc->ctl = LTQ_DMA_OWN | LTQ_DMA_SOP | LTQ_DMA_EOP |\n \t\tLTQ_DMA_TX_OFFSET(byte_offset) | (len & LTQ_DMA_SIZE_MASK);\n-\tch->dma.desc++;\n-\tch->dma.desc %= LTQ_DESC_NUM;\n+\tpriv->txch.dma.desc++;\n+\tpriv->txch.dma.desc %= LTQ_DESC_NUM;\n \tspin_unlock_irqrestore(&priv->lock, flags);\n \n-\tif (ch->dma.desc_base[ch->dma.desc].ctl & LTQ_DMA_OWN)\n+\tif (priv->txch.dma.desc_base[priv->txch.dma.desc].ctl & LTQ_DMA_OWN)\n \t\tnetif_tx_stop_queue(txq);\n \n \treturn NETDEV_TX_OK;\n@@ -499,11 +693,14 @@ ltq_etop_change_mtu(struct net_device *d\n {\n \tstruct ltq_etop_priv *priv = netdev_priv(dev);\n \tunsigned long flags;\n+\tint max;\n \n \tdev->mtu = new_mtu;\n \n+\tmax = ETH_HLEN + VLAN_HLEN + new_mtu + ETH_FCS_LEN;\n+\n \tspin_lock_irqsave(&priv->lock, flags);\n-\tltq_etop_w32((ETOP_PLEN_UNDER << 16) | new_mtu, LTQ_ETOP_IGPLEN);\n+\tltq_etop_w32((ETOP_PLEN_UNDER << 16) | max, LTQ_ETOP_IGPLEN);\n \tspin_unlock_irqrestore(&priv->lock, flags);\n \n \treturn 0;\n@@ -556,6 +753,9 @@ ltq_etop_init(struct net_device *dev)\n \tif (err)\n \t\tgoto err_hw;\n \tltq_etop_change_mtu(dev, 1500);\n+\terr = ltq_etop_dma_init(dev);\n+\tif (err)\n+\t\tgoto err_hw;\n \n \tmemcpy(&mac, &priv->pldata->mac, sizeof(struct sockaddr));\n \tif (!is_valid_ether_addr(mac.sa_data)) {\n@@ -573,9 +773,10 @@ ltq_etop_init(struct net_device *dev)\n \t\tdev->addr_assign_type = NET_ADDR_RANDOM;\n \n \tltq_etop_set_multicast_list(dev);\n-\terr = ltq_etop_mdio_init(dev);\n-\tif (err)\n-\t\tgoto err_netdev;\n+\tif (!ltq_etop_mdio_init(dev))\n+\t\tdev->ethtool_ops = &ltq_etop_ethtool_ops;\n+\telse\n+\t\tpr_warn(\"etop: mdio probe failed\\n\");;\n \treturn 0;\n \n err_netdev:\n@@ -595,6 +796,9 @@ ltq_etop_tx_timeout(struct net_device *d\n \terr = ltq_etop_hw_init(dev);\n \tif (err)\n \t\tgoto err_hw;\n+\terr = ltq_etop_dma_init(dev);\n+\tif (err)\n+\t\tgoto err_hw;\n \tnetif_trans_update(dev);\n \tnetif_wake_queue(dev);\n \treturn;\n@@ -618,14 +822,18 @@ static const struct net_device_ops ltq_e\n \t.ndo_tx_timeout = ltq_etop_tx_timeout,\n };\n \n-static int __init\n-ltq_etop_probe(struct platform_device *pdev)\n+static int ltq_etop_probe(struct platform_device *pdev)\n {\n \tstruct net_device *dev;\n \tstruct ltq_etop_priv *priv;\n-\tstruct resource *res;\n+\tstruct resource *res, *gbit_res, irqres[2];\n \tint err;\n-\tint i;\n+\n+\terr = of_irq_to_resource_table(pdev->dev.of_node, irqres, 2);\n+\tif (err != 2) {\n+\t\tdev_err(&pdev->dev, \"failed to get etop irqs\\n\");\n+\t\treturn -EINVAL;\n+\t}\n \n \tres = platform_get_resource(pdev, IORESOURCE_MEM, 0);\n \tif (!res) {\n@@ -651,31 +859,62 @@ ltq_etop_probe(struct platform_device *p\n \t\tgoto err_out;\n \t}\n \n-\tdev = alloc_etherdev_mq(sizeof(struct ltq_etop_priv), 4);\n-\tif (!dev) {\n-\t\terr = -ENOMEM;\n-\t\tgoto err_out;\n+\tif (of_machine_is_compatible(\"lantiq,ar9\")) {\n+\t\tgbit_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);\n+\t\tif (!gbit_res) {\n+\t\t\tdev_err(&pdev->dev, \"failed to get gbit resource\\n\");\n+\t\t\terr = -ENOENT;\n+\t\t\tgoto err_out;\n+\t\t}\n+\t\tltq_gbit_membase = devm_ioremap(&pdev->dev,\n+\t\t\tgbit_res->start, resource_size(gbit_res));\n+\t\tif (!ltq_gbit_membase) {\n+\t\t\tdev_err(&pdev->dev, \"failed to remap gigabit switch %d\\n\",\n+\t\t\t\tpdev->id);\n+\t\t\terr = -ENOMEM;\n+\t\t\tgoto err_out;\n+\t\t}\n \t}\n+\n+\tdev = alloc_etherdev_mq(sizeof(struct ltq_etop_priv), 4);\n \tstrcpy(dev->name, \"eth%d\");\n \tdev->netdev_ops = &ltq_eth_netdev_ops;\n-\tdev->ethtool_ops = &ltq_etop_ethtool_ops;\n \tpriv = netdev_priv(dev);\n \tpriv->res = res;\n \tpriv->pdev = pdev;\n-\tpriv->pldata = dev_get_platdata(&pdev->dev);\n \tpriv->netdev = dev;\n+\tpriv->tx_irq = irqres[0].start;\n+\tpriv->rx_irq = irqres[1].start;\n+\terr = of_get_phy_mode(pdev->dev.of_node, &priv->mii_mode);\n+\tif (err)\n+\t\tpr_err(\"Can't find phy-mode for port\\n\");\n+\n+\tof_get_mac_address(pdev->dev.of_node, priv->mac);\n+\n+\tpriv->clk_ppe = clk_get(&pdev->dev, NULL);\n+\tif (IS_ERR(priv->clk_ppe))\n+\t\treturn PTR_ERR(priv->clk_ppe);\n+\tif (of_machine_is_compatible(\"lantiq,ar9\")) {\n+\t\tpriv->clk_switch = clk_get(&pdev->dev, \"switch\");\n+\t\tif (IS_ERR(priv->clk_switch))\n+\t\t\treturn PTR_ERR(priv->clk_switch);\n+\t}\n+\tif (of_machine_is_compatible(\"lantiq,ase\")) {\n+\t\tpriv->clk_ephy = clk_get(&pdev->dev, \"ephy\");\n+\t\tif (IS_ERR(priv->clk_ephy))\n+\t\t\treturn PTR_ERR(priv->clk_ephy);\n+\t\tpriv->clk_ephycgu = clk_get(&pdev->dev, \"ephycgu\");\n+\t\tif (IS_ERR(priv->clk_ephycgu))\n+\t\t\treturn PTR_ERR(priv->clk_ephycgu);\n+\t}\n+\n \tspin_lock_init(&priv->lock);\n \tSET_NETDEV_DEV(dev, &pdev->dev);\n \n-\tfor (i = 0; i < MAX_DMA_CHAN; i++) {\n-\t\tif (IS_TX(i))\n-\t\t\tnetif_napi_add(dev, &priv->ch[i].napi,\n-\t\t\t\tltq_etop_poll_tx, 8);\n-\t\telse if (IS_RX(i))\n-\t\t\tnetif_napi_add(dev, &priv->ch[i].napi,\n-\t\t\t\tltq_etop_poll_rx, 32);\n-\t\tpriv->ch[i].netdev = dev;\n-\t}\n+\tnetif_napi_add(dev, &priv->txch.napi, ltq_etop_poll_tx, 8);\n+\tnetif_napi_add(dev, &priv->rxch.napi, ltq_etop_poll_rx, 32);\n+\tpriv->txch.netdev = dev;\n+\tpriv->rxch.netdev = dev;\n \n \terr = register_netdev(dev);\n \tif (err)\n@@ -704,31 +943,22 @@ ltq_etop_remove(struct platform_device *\n \treturn 0;\n }\n \n+static const struct of_device_id ltq_etop_match[] = {\n+\t{ .compatible = \"lantiq,etop-xway\" },\n+\t{},\n+};\n+MODULE_DEVICE_TABLE(of, ltq_etop_match);\n+\n static struct platform_driver ltq_mii_driver = {\n+\t.probe = ltq_etop_probe,\n \t.remove = ltq_etop_remove,\n \t.driver = {\n \t\t.name = \"ltq_etop\",\n+\t\t.of_match_table = ltq_etop_match,\n \t},\n };\n \n-int __init\n-init_ltq_etop(void)\n-{\n-\tint ret = platform_driver_probe(&ltq_mii_driver, ltq_etop_probe);\n-\n-\tif (ret)\n-\t\tpr_err(\"ltq_etop: Error registering platform driver!\");\n-\treturn ret;\n-}\n-\n-static void __exit\n-exit_ltq_etop(void)\n-{\n-\tplatform_driver_unregister(&ltq_mii_driver);\n-}\n-\n-module_init(init_ltq_etop);\n-module_exit(exit_ltq_etop);\n+module_platform_driver(ltq_mii_driver);\n \n MODULE_AUTHOR(\"John Crispin <blogic@openwrt.org>\");\n MODULE_DESCRIPTION(\"Lantiq SoC ETOP\");\n"
  },
  {
    "path": "target/linux/lantiq/patches-5.10/0031-I2C-MIPS-lantiq-add-FALC-ON-i2c-bus-master.patch",
    "content": "From f17e50f67fa3c77624edf2ca03fae0d50f0ce39b Mon Sep 17 00:00:00 2001\nFrom: John Crispin <blogic@openwrt.org>\nDate: Thu, 7 Aug 2014 18:26:42 +0200\nSubject: [PATCH 31/36] I2C: MIPS: lantiq: add FALC-ON i2c bus master\n\nThis patch adds the driver needed to make the I2C bus work on FALC-ON SoCs.\n\nSigned-off-by: Thomas Langer <thomas.langer@lantiq.com>\nSigned-off-by: John Crispin <blogic@openwrt.org>\n---\n drivers/i2c/busses/Kconfig      |   10 +\n drivers/i2c/busses/Makefile     |    1 +\n drivers/i2c/busses/i2c-lantiq.c |  747 +++++++++++++++++++++++++++++++++++++++\n drivers/i2c/busses/i2c-lantiq.h |  234 ++++++++++++\n 4 files changed, 992 insertions(+)\n create mode 100644 drivers/i2c/busses/i2c-lantiq.c\n create mode 100644 drivers/i2c/busses/i2c-lantiq.h\n\n--- a/drivers/i2c/busses/Kconfig\n+++ b/drivers/i2c/busses/Kconfig\n@@ -753,6 +753,16 @@ config I2C_MESON\n \t  If you say yes to this option, support will be included for the\n \t  I2C interface on the Amlogic Meson family of SoCs.\n \n+config I2C_LANTIQ\n+\ttristate \"Lantiq I2C interface\"\n+\tdepends on LANTIQ && SOC_FALCON\n+\thelp\n+\t  If you say yes to this option, support will be included for the\n+\t  Lantiq I2C core.\n+\n+\t  This driver can also be built as a module. If so, the module\n+\t  will be called i2c-lantiq.\n+\n config I2C_MPC\n \ttristate \"MPC107/824x/85xx/512x/52xx/83xx/86xx\"\n \tdepends on PPC\n--- a/drivers/i2c/busses/Makefile\n+++ b/drivers/i2c/busses/Makefile\n@@ -72,6 +72,7 @@ obj-$(CONFIG_I2C_IMX_LPI2C)\t+= i2c-imx-l\n obj-$(CONFIG_I2C_IOP3XX)\t+= i2c-iop3xx.o\n obj-$(CONFIG_I2C_JZ4780)\t+= i2c-jz4780.o\n obj-$(CONFIG_I2C_KEMPLD)\t+= i2c-kempld.o\n+obj-$(CONFIG_I2C_LANTIQ)\t+= i2c-lantiq.o\n obj-$(CONFIG_I2C_LPC2K)\t\t+= i2c-lpc2k.o\n obj-$(CONFIG_I2C_MESON)\t\t+= i2c-meson.o\n obj-$(CONFIG_I2C_MPC)\t\t+= i2c-mpc.o\n--- /dev/null\n+++ b/drivers/i2c/busses/i2c-lantiq.c\n@@ -0,0 +1,747 @@\n+\n+/*\n+ * Lantiq I2C bus adapter\n+ *\n+ * Parts based on i2c-designware.c and other i2c drivers from Linux 2.6.33\n+ *\n+ * This program is free software; you can redistribute it and/or modify\n+ * it under the terms of the GNU General Public License as published by\n+ * the Free Software Foundation; either version 2 of the License, or\n+ * (at your option) any later version.\n+ *\n+ * This program is distributed in the hope that it will be useful,\n+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\n+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n+ * GNU General Public License for more details.\n+ *\n+ * You should have received a copy of the GNU General Public License\n+ * along with this program; if not, write to the Free Software\n+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.\n+ *\n+ * Copyright (C) 2012 Thomas Langer <thomas.langer@lantiq.com>\n+ */\n+\n+#include <linux/kernel.h>\n+#include <linux/module.h>\n+#include <linux/delay.h>\n+#include <linux/slab.h> /* for kzalloc, kfree */\n+#include <linux/i2c.h>\n+#include <linux/errno.h>\n+#include <linux/completion.h>\n+#include <linux/interrupt.h>\n+#include <linux/platform_device.h>\n+#include <linux/io.h>\n+#include <linux/of_irq.h>\n+\n+#include <lantiq_soc.h>\n+#include \"i2c-lantiq.h\"\n+\n+/*\n+ * CURRENT ISSUES:\n+ * - no high speed support\n+ * - ten bit mode is not tested (no slave devices)\n+ */\n+\n+/* access macros */\n+#define i2c_r32(reg)\t\\\n+\t__raw_readl(&(priv->membase)->reg)\n+#define i2c_w32(val, reg)\t\\\n+\t__raw_writel(val, &(priv->membase)->reg)\n+#define i2c_w32_mask(clear, set, reg)\t\\\n+\ti2c_w32((i2c_r32(reg) & ~(clear)) | (set), reg)\n+\n+#define DRV_NAME \"i2c-lantiq\"\n+#define DRV_VERSION \"1.00\"\n+\n+#define LTQ_I2C_BUSY_TIMEOUT\t\t20 /* ms */\n+\n+#ifdef DEBUG\n+#define LTQ_I2C_XFER_TIMEOUT\t\t(25*HZ)\n+#else\n+#define LTQ_I2C_XFER_TIMEOUT\t\tHZ\n+#endif\n+\n+#define LTQ_I2C_IMSC_DEFAULT_MASK\t(I2C_IMSC_I2C_P_INT_EN | \\\n+\t\t\t\t\t I2C_IMSC_I2C_ERR_INT_EN)\n+\n+#define LTQ_I2C_ARB_LOST\t\t(1 << 0)\n+#define LTQ_I2C_NACK\t\t\t(1 << 1)\n+#define LTQ_I2C_RX_UFL\t\t\t(1 << 2)\n+#define LTQ_I2C_RX_OFL\t\t\t(1 << 3)\n+#define LTQ_I2C_TX_UFL\t\t\t(1 << 4)\n+#define LTQ_I2C_TX_OFL\t\t\t(1 << 5)\n+\n+struct ltq_i2c {\n+\tstruct mutex mutex;\n+\n+\n+\t/* active clock settings */\n+\tunsigned int input_clock;\t/* clock input for i2c hardware block */\n+\tunsigned int i2c_clock;\t\t/* approximated bus clock in kHz */\n+\n+\tstruct clk *clk_gate;\n+\tstruct clk *clk_input;\n+\n+\n+\t/* resources (memory and interrupts) */\n+\tint irq_lb;\t\t\t\t/* last burst irq */\n+\n+\tstruct lantiq_reg_i2c __iomem *membase;\t/* base of mapped registers */\n+\n+\tstruct i2c_adapter adap;\n+\tstruct device *dev;\n+\n+\tstruct completion cmd_complete;\n+\n+\n+\t/* message transfer data */\n+\tstruct i2c_msg *current_msg;\t/* current message */\n+\tint msgs_num;\t\t/* number of messages to handle */\n+\tu8 *msg_buf;\t\t/* current buffer */\n+\tu32 msg_buf_len;\t/* remaining length of current buffer */\n+\tint msg_err;\t\t/* error status of the current transfer */\n+\n+\n+\t/* master status codes */\n+\tenum {\n+\t\tSTATUS_IDLE,\n+\t\tSTATUS_ADDR,\t/* address phase */\n+\t\tSTATUS_WRITE,\n+\t\tSTATUS_READ,\n+\t\tSTATUS_READ_END,\n+\t\tSTATUS_STOP\n+\t} status;\n+};\n+\n+static irqreturn_t ltq_i2c_isr(int irq, void *dev_id);\n+\n+static inline void enable_burst_irq(struct ltq_i2c *priv)\n+{\n+\ti2c_w32_mask(0, I2C_IMSC_LBREQ_INT_EN | I2C_IMSC_BREQ_INT_EN, imsc);\n+}\n+static inline void disable_burst_irq(struct ltq_i2c *priv)\n+{\n+\ti2c_w32_mask(I2C_IMSC_LBREQ_INT_EN | I2C_IMSC_BREQ_INT_EN, 0, imsc);\n+}\n+\n+static void prepare_msg_send_addr(struct ltq_i2c *priv)\n+{\n+\tstruct i2c_msg *msg = priv->current_msg;\n+\tint rd = !!(msg->flags & I2C_M_RD);\t/* extends to 0 or 1 */\n+\tu16 addr = msg->addr;\n+\n+\t/* new i2c_msg */\n+\tpriv->msg_buf = msg->buf;\n+\tpriv->msg_buf_len = msg->len;\n+\tif (rd)\n+\t\tpriv->status = STATUS_READ;\n+\telse\n+\t\tpriv->status = STATUS_WRITE;\n+\n+\t/* send slave address */\n+\tif (msg->flags & I2C_M_TEN) {\n+\t\ti2c_w32(0xf0 | ((addr & 0x300) >> 7) | rd, txd);\n+\t\ti2c_w32(addr & 0xff, txd);\n+\t} else {\n+\t\ti2c_w32((addr & 0x7f) << 1 | rd, txd);\n+\t}\n+}\n+\n+static void ltq_i2c_set_tx_len(struct ltq_i2c *priv)\n+{\n+\tstruct i2c_msg *msg = priv->current_msg;\n+\tint len = (msg->flags & I2C_M_TEN) ? 2 : 1;\n+\n+\tpr_debug(\"set_tx_len %cX\\n\", (msg->flags & I2C_M_RD) ? 'R' : 'T');\n+\n+\tpriv->status = STATUS_ADDR;\n+\n+\tif (!(msg->flags & I2C_M_RD))\n+\t\tlen += msg->len;\n+\telse\n+\t\t/* set maximum received packet size (before rx int!) */\n+\t\ti2c_w32(msg->len, mrps_ctrl);\n+\ti2c_w32(len, tps_ctrl);\n+\tenable_burst_irq(priv);\n+}\n+\n+static int ltq_i2c_hw_set_clock(struct i2c_adapter *adap)\n+{\n+\tstruct ltq_i2c *priv = i2c_get_adapdata(adap);\n+\tunsigned int input_clock = clk_get_rate(priv->clk_input);\n+\tu32 dec, inc = 1;\n+\n+\t/* clock changed? */\n+\tif (priv->input_clock == input_clock)\n+\t\treturn 0;\n+\n+\t/*\n+\t * this formula is only an approximation, found by the recommended\n+\t * values in the \"I2C Architecture Specification 1.7.1\"\n+\t */\n+\tdec = input_clock / (priv->i2c_clock * 2);\n+\tif (dec <= 6)\n+\t\treturn -ENXIO;\n+\n+\ti2c_w32(0, fdiv_high_cfg);\n+\ti2c_w32((inc << I2C_FDIV_CFG_INC_OFFSET) |\n+\t\t(dec << I2C_FDIV_CFG_DEC_OFFSET),\n+\t\tfdiv_cfg);\n+\n+\tdev_info(priv->dev, \"setup clocks (in %d kHz, bus %d kHz, dec=%d)\\n\",\n+\t\tinput_clock, priv->i2c_clock, dec);\n+\n+\tpriv->input_clock = input_clock;\n+\treturn 0;\n+}\n+\n+static int ltq_i2c_hw_init(struct i2c_adapter *adap)\n+{\n+\tint ret = 0;\n+\tstruct ltq_i2c *priv = i2c_get_adapdata(adap);\n+\n+\t/* disable bus */\n+\ti2c_w32_mask(I2C_RUN_CTRL_RUN_EN, 0, run_ctrl);\n+\n+#ifndef DEBUG\n+\t/* set normal operation clock divider */\n+\ti2c_w32(1 << I2C_CLC_RMC_OFFSET, clc);\n+#else\n+\t/* for debugging a higher divider value! */\n+\ti2c_w32(0xF0 << I2C_CLC_RMC_OFFSET, clc);\n+#endif\n+\n+\t/* setup clock */\n+\tret = ltq_i2c_hw_set_clock(adap);\n+\tif (ret != 0) {\n+\t\tdev_warn(priv->dev, \"invalid clock settings\\n\");\n+\t\treturn ret;\n+\t}\n+\n+\t/* configure fifo */\n+\ti2c_w32(I2C_FIFO_CFG_TXFC | /* tx fifo as flow controller */\n+\t\tI2C_FIFO_CFG_RXFC | /* rx fifo as flow controller */\n+\t\tI2C_FIFO_CFG_TXFA_TXFA2 | /* tx fifo 4-byte aligned */\n+\t\tI2C_FIFO_CFG_RXFA_RXFA2 | /* rx fifo 4-byte aligned */\n+\t\tI2C_FIFO_CFG_TXBS_TXBS0 | /* tx fifo burst size is 1 word */\n+\t\tI2C_FIFO_CFG_RXBS_RXBS0,  /* rx fifo burst size is 1 word */\n+\t\tfifo_cfg);\n+\n+\t/* configure address */\n+\ti2c_w32(I2C_ADDR_CFG_SOPE_EN |\t/* generate stop when no more data in\n+\t\t\t\t\t   the fifo */\n+\t\tI2C_ADDR_CFG_SONA_EN |\t/* generate stop when NA received */\n+\t\tI2C_ADDR_CFG_MnS_EN |\t/* we are master device */\n+\t\t0,\t\t\t/* our slave address (not used!) */\n+\t\taddr_cfg);\n+\n+\t/* enable bus */\n+\ti2c_w32_mask(0, I2C_RUN_CTRL_RUN_EN, run_ctrl);\n+\n+\treturn 0;\n+}\n+\n+static int ltq_i2c_wait_bus_not_busy(struct ltq_i2c *priv)\n+{\n+\tunsigned long timeout;\n+\n+\ttimeout = jiffies + msecs_to_jiffies(LTQ_I2C_BUSY_TIMEOUT);\n+\n+\tdo {\n+\t\tu32 stat = i2c_r32(bus_stat);\n+\n+\t\tif ((stat & I2C_BUS_STAT_BS_MASK) == I2C_BUS_STAT_BS_FREE)\n+\t\t\treturn 0;\n+\n+\t\tcond_resched();\n+\t} while (!time_after_eq(jiffies, timeout));\n+\n+\tdev_err(priv->dev, \"timeout waiting for bus ready\\n\");\n+\treturn -ETIMEDOUT;\n+}\n+\n+static void ltq_i2c_tx(struct ltq_i2c *priv, int last)\n+{\n+\tif (priv->msg_buf_len && priv->msg_buf) {\n+\t\ti2c_w32(*priv->msg_buf, txd);\n+\n+\t\tif (--priv->msg_buf_len)\n+\t\t\tpriv->msg_buf++;\n+\t\telse\n+\t\t\tpriv->msg_buf = NULL;\n+\t} else {\n+\t\tlast = 1;\n+\t}\n+\n+\tif (last)\n+\t\tdisable_burst_irq(priv);\n+}\n+\n+static void ltq_i2c_rx(struct ltq_i2c *priv, int last)\n+{\n+\tu32 fifo_stat, timeout;\n+\tif (priv->msg_buf_len && priv->msg_buf) {\n+\t\ttimeout = 5000000;\n+\t\tdo {\n+\t\t\tfifo_stat = i2c_r32(ffs_stat);\n+\t\t} while (!fifo_stat && --timeout);\n+\t\tif (!timeout) {\n+\t\t\tlast = 1;\n+\t\t\tpr_debug(\"\\nrx timeout\\n\");\n+\t\t\tgoto err;\n+\t\t}\n+\t\twhile (fifo_stat) {\n+\t\t\t*priv->msg_buf = i2c_r32(rxd);\n+\t\t\tif (--priv->msg_buf_len) {\n+\t\t\t\tpriv->msg_buf++;\n+\t\t\t} else {\n+\t\t\t\tpriv->msg_buf = NULL;\n+\t\t\t\tlast = 1;\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t\t/*\n+\t\t\t * do not read more than burst size, otherwise no \"last\n+\t\t\t * burst\" is generated and the transaction is blocked!\n+\t\t\t */\n+\t\t\tfifo_stat = 0;\n+\t\t}\n+\t} else {\n+\t\tlast = 1;\n+\t}\n+err:\n+\tif (last) {\n+\t\tdisable_burst_irq(priv);\n+\n+\t\tif (priv->status == STATUS_READ_END) {\n+\t\t\t/* \n+\t\t\t * do the STATUS_STOP and complete() here, as sometimes\n+\t\t\t * the tx_end is already seen before this is finished\n+\t\t\t */\n+\t\t\tpriv->status = STATUS_STOP;\n+\t\t\tcomplete(&priv->cmd_complete);\n+\t\t} else {\n+\t\t\ti2c_w32(I2C_ENDD_CTRL_SETEND, endd_ctrl);\n+\t\t\tpriv->status = STATUS_READ_END;\n+\t\t}\n+\t}\n+}\n+\n+static void ltq_i2c_xfer_init(struct ltq_i2c *priv)\n+{\n+\t/* enable interrupts */\n+\ti2c_w32(LTQ_I2C_IMSC_DEFAULT_MASK, imsc);\n+\n+\t/* trigger transfer of first msg */\n+\tltq_i2c_set_tx_len(priv);\n+}\n+\n+static void dump_msgs(struct i2c_msg msgs[], int num, int rx)\n+{\n+#if defined(DEBUG)\n+\tint i, j;\n+\tpr_debug(\"Messages %d %s\\n\", num, rx ? \"out\" : \"in\");\n+\tfor (i = 0; i < num; i++) {\n+\t\tpr_debug(\"%2d %cX Msg(%d) addr=0x%X: \", i,\n+\t\t\t(msgs[i].flags & I2C_M_RD) ? 'R' : 'T',\n+\t\t\tmsgs[i].len, msgs[i].addr);\n+\t\tif (!(msgs[i].flags & I2C_M_RD) || rx) {\n+\t\t\tfor (j = 0; j < msgs[i].len; j++)\n+\t\t\t\tpr_debug(\"%02X \", msgs[i].buf[j]);\n+\t\t}\n+\t\tpr_debug(\"\\n\");\n+\t}\n+#endif\n+}\n+\n+static void ltq_i2c_release_bus(struct ltq_i2c *priv)\n+{\n+\tif ((i2c_r32(bus_stat) & I2C_BUS_STAT_BS_MASK) == I2C_BUS_STAT_BS_BM)\n+\t\ti2c_w32(I2C_ENDD_CTRL_SETEND, endd_ctrl);\n+}\n+\n+static int ltq_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],\n+\t\t\t   int num)\n+{\n+\tstruct ltq_i2c *priv = i2c_get_adapdata(adap);\n+\tint ret;\n+\n+\tdev_dbg(priv->dev, \"xfer %u messages\\n\", num);\n+\tdump_msgs(msgs, num, 0);\n+\n+\tmutex_lock(&priv->mutex);\n+\n+\tinit_completion(&priv->cmd_complete);\n+\tpriv->current_msg = msgs;\n+\tpriv->msgs_num = num;\n+\tpriv->msg_err = 0;\n+\tpriv->status = STATUS_IDLE;\n+\n+\t/* wait for the bus to become ready */\n+\tret = ltq_i2c_wait_bus_not_busy(priv);\n+\tif (ret)\n+\t\tgoto done;\n+\n+\twhile (priv->msgs_num) {\n+\t\t/* start the transfers */\n+\t\tltq_i2c_xfer_init(priv);\n+\n+\t\t/* wait for transfers to complete */\n+\t\tret = wait_for_completion_interruptible_timeout(\n+\t\t\t&priv->cmd_complete, LTQ_I2C_XFER_TIMEOUT);\n+\t\tif (ret == 0) {\n+\t\t\tdev_err(priv->dev, \"controller timed out\\n\");\n+\t\t\tltq_i2c_hw_init(adap);\n+\t\t\tret = -ETIMEDOUT;\n+\t\t\tgoto done;\n+\t\t} else if (ret < 0)\n+\t\t\tgoto done;\n+\n+\t\tif (priv->msg_err) {\n+\t\t\tif (priv->msg_err & LTQ_I2C_NACK)\n+\t\t\t\tret = -ENXIO;\n+\t\t\telse\n+\t\t\t\tret = -EREMOTEIO;\n+\t\t\tgoto done;\n+\t\t}\n+\t\tif (--priv->msgs_num)\n+\t\t\tpriv->current_msg++;\n+\t}\n+\t/* no error? */\n+\tret = num;\n+\n+done:\n+\tltq_i2c_release_bus(priv);\n+\n+\tmutex_unlock(&priv->mutex);\n+\n+\tif (ret >= 0)\n+\t\tdump_msgs(msgs, num, 1);\n+\n+\tpr_debug(\"XFER ret %d\\n\", ret);\n+\treturn ret;\n+}\n+\n+static irqreturn_t ltq_i2c_isr_burst(int irq, void *dev_id)\n+{\n+\tstruct ltq_i2c *priv = dev_id;\n+\tstruct i2c_msg *msg = priv->current_msg;\n+\tint last = (irq == priv->irq_lb);\n+\n+\tif (last)\n+\t\tpr_debug(\"LB \");\n+\telse\n+\t\tpr_debug(\"B \");\n+\n+\tif (msg->flags & I2C_M_RD) {\n+\t\tswitch (priv->status) {\n+\t\tcase STATUS_ADDR:\n+\t\t\tpr_debug(\"X\");\n+\t\t\tprepare_msg_send_addr(priv);\n+\t\t\tdisable_burst_irq(priv);\n+\t\t\tbreak;\n+\t\tcase STATUS_READ:\n+\t\tcase STATUS_READ_END:\n+\t\t\tpr_debug(\"R\");\n+\t\t\tltq_i2c_rx(priv, last);\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tdisable_burst_irq(priv);\n+\t\t\tpr_warn(\"Status R %d\\n\", priv->status);\n+\t\t\tbreak;\n+\t\t}\n+\t} else {\n+\t\tswitch (priv->status) {\n+\t\tcase STATUS_ADDR:\n+\t\t\tpr_debug(\"x\");\n+\t\t\tprepare_msg_send_addr(priv);\n+\t\t\tbreak;\n+\t\tcase STATUS_WRITE:\n+\t\t\tpr_debug(\"w\");\n+\t\t\tltq_i2c_tx(priv, last);\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tdisable_burst_irq(priv);\n+\t\t\tpr_warn(\"Status W %d\\n\", priv->status);\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\n+\ti2c_w32(I2C_ICR_BREQ_INT_CLR | I2C_ICR_LBREQ_INT_CLR, icr);\n+\treturn IRQ_HANDLED;\n+}\n+\n+static void ltq_i2c_isr_prot(struct ltq_i2c *priv)\n+{\n+\tu32 i_pro = i2c_r32(p_irqss);\n+\n+\tpr_debug(\"i2c-p\");\n+\n+\t/* not acknowledge */\n+\tif (i_pro & I2C_P_IRQSS_NACK) {\n+\t\tpriv->msg_err |= LTQ_I2C_NACK;\n+\t\tpr_debug(\" nack\");\n+\t}\n+\n+\t/* arbitration lost */\n+\tif (i_pro & I2C_P_IRQSS_AL) {\n+\t\tpriv->msg_err |= LTQ_I2C_ARB_LOST;\n+\t\tpr_debug(\" arb-lost\");\n+\t}\n+\t/* tx -> rx switch */\n+\tif (i_pro & I2C_P_IRQSS_RX)\n+\t\tpr_debug(\" rx\");\n+\n+\t/* tx end */\n+\tif (i_pro & I2C_P_IRQSS_TX_END)\n+\t\tpr_debug(\" txend\");\n+\tpr_debug(\"\\n\");\n+\n+\tif (!priv->msg_err) {\n+\t\t/* tx -> rx switch */\n+\t\tif (i_pro & I2C_P_IRQSS_RX) {\n+\t\t\tpriv->status = STATUS_READ;\n+\t\t\tenable_burst_irq(priv);\n+\t\t}\n+\t\tif (i_pro & I2C_P_IRQSS_TX_END) {\n+\t\t\tif (priv->status == STATUS_READ)\n+\t\t\t\tpriv->status = STATUS_READ_END;\n+\t\t\telse {\n+\t\t\t\tdisable_burst_irq(priv);\n+\t\t\t\tpriv->status = STATUS_STOP;\n+\t\t\t}\n+\t\t}\n+\t}\n+\n+\ti2c_w32(i_pro, p_irqsc);\n+}\n+\n+static irqreturn_t ltq_i2c_isr(int irq, void *dev_id)\n+{\n+\tu32 i_raw, i_err = 0;\n+\tstruct ltq_i2c *priv = dev_id;\n+\n+\ti_raw = i2c_r32(mis);\n+\tpr_debug(\"i_raw 0x%08X\\n\", i_raw);\n+\n+\t/* error interrupt */\n+\tif (i_raw & I2C_RIS_I2C_ERR_INT_INTOCC) {\n+\t\ti_err = i2c_r32(err_irqss);\n+\t\tpr_debug(\"i_err 0x%08X bus_stat 0x%04X\\n\",\n+\t\t\ti_err, i2c_r32(bus_stat));\n+\n+\t\t/* tx fifo overflow (8) */\n+\t\tif (i_err & I2C_ERR_IRQSS_TXF_OFL)\n+\t\t\tpriv->msg_err |= LTQ_I2C_TX_OFL;\n+\n+\t\t/* tx fifo underflow (4) */\n+\t\tif (i_err & I2C_ERR_IRQSS_TXF_UFL)\n+\t\t\tpriv->msg_err |= LTQ_I2C_TX_UFL;\n+\n+\t\t/* rx fifo overflow (2) */\n+\t\tif (i_err & I2C_ERR_IRQSS_RXF_OFL)\n+\t\t\tpriv->msg_err |= LTQ_I2C_RX_OFL;\n+\n+\t\t/* rx fifo underflow (1) */\n+\t\tif (i_err & I2C_ERR_IRQSS_RXF_UFL)\n+\t\t\tpriv->msg_err |= LTQ_I2C_RX_UFL;\n+\n+\t\ti2c_w32(i_err, err_irqsc);\n+\t}\n+\n+\t/* protocol interrupt */\n+\tif (i_raw & I2C_RIS_I2C_P_INT_INTOCC)\n+\t\tltq_i2c_isr_prot(priv);\n+\n+\tif ((priv->msg_err) || (priv->status == STATUS_STOP))\n+\t\tcomplete(&priv->cmd_complete);\n+\n+\treturn IRQ_HANDLED;\n+}\n+\n+static u32 ltq_i2c_functionality(struct i2c_adapter *adap)\n+{\n+\treturn\tI2C_FUNC_I2C |\n+\t\tI2C_FUNC_10BIT_ADDR |\n+\t\tI2C_FUNC_SMBUS_EMUL;\n+}\n+\n+static struct i2c_algorithm ltq_i2c_algorithm = {\n+\t.master_xfer\t= ltq_i2c_xfer,\n+\t.functionality\t= ltq_i2c_functionality,\n+};\n+\n+static int ltq_i2c_probe(struct platform_device *pdev)\n+{\n+\tstruct device_node *node = pdev->dev.of_node;\n+\tstruct ltq_i2c *priv;\n+\tstruct i2c_adapter *adap;\n+\tstruct resource *mmres, irqres[4];\n+\tint ret = 0;\n+\n+\tdev_dbg(&pdev->dev, \"probing\\n\");\n+\n+\tmmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);\n+\tret = of_irq_to_resource_table(node, irqres, 4);\n+\tif (!mmres || (ret != 4)) {\n+\t\tdev_err(&pdev->dev, \"no resources\\n\");\n+\t\treturn -ENODEV;\n+\t}\n+\n+\t/* allocate private data */\n+\tpriv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);\n+\tif (!priv) {\n+\t\tdev_err(&pdev->dev, \"can't allocate private data\\n\");\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\tadap = &priv->adap;\n+\ti2c_set_adapdata(adap, priv);\n+\tadap->owner = THIS_MODULE;\n+\tadap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;\n+\tstrlcpy(adap->name, DRV_NAME \"-adapter\", sizeof(adap->name));\n+\tadap->algo = &ltq_i2c_algorithm;\n+\tadap->dev.parent = &pdev->dev;\n+\tadap->dev.of_node = pdev->dev.of_node;\n+\n+\tif (of_property_read_u32(node, \"clock-frequency\", &priv->i2c_clock)) {\n+\t\tdev_warn(&pdev->dev, \"No I2C speed selected, using 100kHz\\n\");\n+\t\tpriv->i2c_clock = 100000;\n+\t}\n+\n+\tinit_completion(&priv->cmd_complete);\n+\tmutex_init(&priv->mutex);\n+\n+\tpriv->membase = devm_ioremap_resource(&pdev->dev, mmres);\n+\tif (IS_ERR(priv->membase))\n+\t\treturn PTR_ERR(priv->membase);\n+\n+\tpriv->dev = &pdev->dev;\n+\tpriv->irq_lb = irqres[0].start;\n+\n+\tret = devm_request_irq(&pdev->dev, irqres[0].start, ltq_i2c_isr_burst,\n+\t\t0x0, \"i2c lb\", priv);\n+\tif (ret) {\n+\t\tdev_err(&pdev->dev, \"can't get last burst IRQ %d\\n\",\n+\t\t\tirqres[0].start);\n+\t\treturn -ENODEV;\n+\t}\n+\n+\tret = devm_request_irq(&pdev->dev, irqres[1].start, ltq_i2c_isr_burst,\n+\t\t0x0, \"i2c b\", priv);\n+\tif (ret) {\n+\t\tdev_err(&pdev->dev, \"can't get burst IRQ %d\\n\",\n+\t\t\tirqres[1].start);\n+\t\treturn -ENODEV;\n+\t}\n+\n+\tret = devm_request_irq(&pdev->dev, irqres[2].start, ltq_i2c_isr,\n+\t\t0x0, \"i2c err\", priv);\n+\tif (ret) {\n+\t\tdev_err(&pdev->dev, \"can't get error IRQ %d\\n\",\n+\t\t\tirqres[2].start);\n+\t\treturn -ENODEV;\n+\t}\n+\n+\tret = devm_request_irq(&pdev->dev, irqres[3].start, ltq_i2c_isr,\n+\t\t0x0, \"i2c p\", priv);\n+\tif (ret) {\n+\t\tdev_err(&pdev->dev, \"can't get protocol IRQ %d\\n\",\n+\t\t\tirqres[3].start);\n+\t\treturn -ENODEV;\n+\t}\n+\n+\tdev_dbg(&pdev->dev, \"mapped io-space to %p\\n\", priv->membase);\n+\tdev_dbg(&pdev->dev, \"use IRQs %d, %d, %d, %d\\n\", irqres[0].start,\n+\t\tirqres[1].start, irqres[2].start, irqres[3].start);\n+\n+\tpriv->clk_gate = devm_clk_get(&pdev->dev, NULL);\n+\tif (IS_ERR(priv->clk_gate)) {\n+\t\tdev_err(&pdev->dev, \"failed to get i2c clk\\n\");\n+\t\treturn -ENOENT;\n+\t}\n+\n+\t/* this is a static clock, which has no refcounting */\n+\tpriv->clk_input = clk_get_fpi();\n+\tif (IS_ERR(priv->clk_input)) {\n+\t\tdev_err(&pdev->dev, \"failed to get fpi clk\\n\");\n+\t\treturn -ENOENT;\n+\t}\n+\n+\tclk_activate(priv->clk_gate);\n+\n+\t/* add our adapter to the i2c stack */\n+\tret = i2c_add_numbered_adapter(adap);\n+\tif (ret) {\n+\t\tdev_err(&pdev->dev, \"can't register I2C adapter\\n\");\n+\t\tgoto out;\n+\t}\n+\n+\tplatform_set_drvdata(pdev, priv);\n+\ti2c_set_adapdata(adap, priv);\n+\n+\t/* print module version information */\n+\tdev_dbg(&pdev->dev, \"module id=%u revision=%u\\n\",\n+\t\t(i2c_r32(id) & I2C_ID_ID_MASK) >> I2C_ID_ID_OFFSET,\n+\t\t(i2c_r32(id) & I2C_ID_REV_MASK) >> I2C_ID_REV_OFFSET);\n+\n+\t/* initialize HW */\n+\tret = ltq_i2c_hw_init(adap);\n+\tif (ret) {\n+\t\tdev_err(&pdev->dev, \"can't configure adapter\\n\");\n+\t\ti2c_del_adapter(adap);\n+\t\tplatform_set_drvdata(pdev, NULL);\n+\t\tgoto out;\n+\t} else {\n+\t\tdev_info(&pdev->dev, \"version %s\\n\", DRV_VERSION);\n+\t}\n+\n+out:\n+\t/* if init failed, we need to deactivate the clock gate */\n+\tif (ret)\n+\t\tclk_deactivate(priv->clk_gate);\n+\n+\treturn ret;\n+}\n+\n+static int ltq_i2c_remove(struct platform_device *pdev)\n+{\n+\tstruct ltq_i2c *priv = platform_get_drvdata(pdev);\n+\n+\t/* disable bus */\n+\ti2c_w32_mask(I2C_RUN_CTRL_RUN_EN, 0, run_ctrl);\n+\n+\t/* power down the core */\n+\tclk_deactivate(priv->clk_gate);\n+\n+\t/* remove driver */\n+\ti2c_del_adapter(&priv->adap);\n+\tkfree(priv);\n+\n+\tdev_dbg(&pdev->dev, \"removed\\n\");\n+\tplatform_set_drvdata(pdev, NULL);\n+\n+\treturn 0;\n+}\n+static const struct of_device_id ltq_i2c_match[] = {\n+\t{ .compatible = \"lantiq,lantiq-i2c\" },\n+\t{},\n+};\n+MODULE_DEVICE_TABLE(of, ltq_i2c_match);\n+\n+static struct platform_driver ltq_i2c_driver = {\n+\t.probe\t= ltq_i2c_probe,\n+\t.remove\t= ltq_i2c_remove,\n+\t.driver\t= {\n+\t\t.name\t= DRV_NAME,\n+\t\t.owner\t= THIS_MODULE,\n+\t\t.of_match_table = ltq_i2c_match,\n+\t},\n+};\n+\n+module_platform_driver(ltq_i2c_driver);\n+\n+MODULE_DESCRIPTION(\"Lantiq I2C bus adapter\");\n+MODULE_AUTHOR(\"Thomas Langer <thomas.langer@lantiq.com>\");\n+MODULE_ALIAS(\"platform:\" DRV_NAME);\n+MODULE_LICENSE(\"GPL\");\n+MODULE_VERSION(DRV_VERSION);\n--- /dev/null\n+++ b/drivers/i2c/busses/i2c-lantiq.h\n@@ -0,0 +1,234 @@\n+#ifndef I2C_LANTIQ_H\n+#define I2C_LANTIQ_H\n+\n+/* I2C register structure */\n+struct lantiq_reg_i2c {\n+\t/* I2C Kernel Clock Control Register */\n+\tunsigned int clc; /* 0x00000000 */\n+\t/* Reserved */\n+\tunsigned int res_0; /* 0x00000004 */\n+\t/* I2C Identification Register */\n+\tunsigned int id; /* 0x00000008 */\n+\t/* Reserved */\n+\tunsigned int res_1; /* 0x0000000C */\n+\t/*\n+\t * I2C RUN Control Register\n+\t * This register enables and disables the I2C peripheral. Before\n+\t * enabling, the I2C has to be configured properly. After enabling\n+\t * no configuration is possible\n+\t */\n+\tunsigned int run_ctrl; /* 0x00000010 */\n+\t/*\n+\t * I2C End Data Control Register\n+\t * This register is used to either turn around the data transmission\n+\t * direction or to address another slave without sending a stop\n+\t * condition. Also the software can stop the slave-transmitter by\n+\t * sending a not-accolade when working as master-receiver or even\n+\t * stop data transmission immediately when operating as\n+\t * master-transmitter. The writing to the bits of this control\n+\t * register is only effective when in MASTER RECEIVES BYTES, MASTER\n+\t * TRANSMITS BYTES, MASTER RESTART or SLAVE RECEIVE BYTES state\n+\t */\n+\tunsigned int endd_ctrl; /* 0x00000014 */\n+\t/*\n+\t * I2C Fractional Divider Configuration Register\n+\t * These register is used to program the fractional divider of the I2C\n+\t * bus. Before the peripheral is switched on by setting the RUN-bit the\n+\t * two (fixed) values for the two operating frequencies are programmed\n+\t * into these (configuration) registers. The Register FDIV_HIGH_CFG has\n+\t * the same layout as I2C_FDIV_CFG.\n+\t */\n+\tunsigned int fdiv_cfg; /* 0x00000018 */\n+\t/*\n+\t * I2C Fractional Divider (highspeed mode) Configuration Register\n+\t * These register is used to program the fractional divider of the I2C\n+\t * bus. Before the peripheral is switched on by setting the RUN-bit the\n+\t * two (fixed) values for the two operating frequencies are programmed\n+\t * into these (configuration) registers. The Register FDIV_CFG has the\n+\t * same layout as I2C_FDIV_CFG.\n+\t */\n+\tunsigned int fdiv_high_cfg; /* 0x0000001C */\n+\t/* I2C Address Configuration Register */\n+\tunsigned int addr_cfg; /* 0x00000020 */\n+\t/* I2C Bus Status Register\n+\t * This register gives a status information of the I2C. This additional\n+\t * information can be used by the software to start proper actions.\n+\t */\n+\tunsigned int bus_stat; /* 0x00000024 */\n+\t/* I2C FIFO Configuration Register */\n+\tunsigned int fifo_cfg; /* 0x00000028 */\n+\t/* I2C Maximum Received Packet Size Register */\n+\tunsigned int mrps_ctrl; /* 0x0000002C */\n+\t/* I2C Received Packet Size Status Register */\n+\tunsigned int rps_stat; /* 0x00000030 */\n+\t/* I2C Transmit Packet Size Register */\n+\tunsigned int tps_ctrl; /* 0x00000034 */\n+\t/* I2C Filled FIFO Stages Status Register */\n+\tunsigned int ffs_stat; /* 0x00000038 */\n+\t/* Reserved */\n+\tunsigned int res_2; /* 0x0000003C */\n+\t/* I2C Timing Configuration Register */\n+\tunsigned int tim_cfg; /* 0x00000040 */\n+\t/* Reserved */\n+\tunsigned int res_3[7]; /* 0x00000044 */\n+\t/* I2C Error Interrupt Request Source Mask Register */\n+\tunsigned int err_irqsm; /* 0x00000060 */\n+\t/* I2C Error Interrupt Request Source Status Register */\n+\tunsigned int err_irqss; /* 0x00000064 */\n+\t/* I2C Error Interrupt Request Source Clear Register */\n+\tunsigned int err_irqsc; /* 0x00000068 */\n+\t/* Reserved */\n+\tunsigned int res_4; /* 0x0000006C */\n+\t/* I2C Protocol Interrupt Request Source Mask Register */\n+\tunsigned int p_irqsm; /* 0x00000070 */\n+\t/* I2C Protocol Interrupt Request Source Status Register */\n+\tunsigned int p_irqss; /* 0x00000074 */\n+\t/* I2C Protocol Interrupt Request Source Clear Register */\n+\tunsigned int p_irqsc; /* 0x00000078 */\n+\t/* Reserved */\n+\tunsigned int res_5; /* 0x0000007C */\n+\t/* I2C Raw Interrupt Status Register */\n+\tunsigned int ris; /* 0x00000080 */\n+\t/* I2C Interrupt Mask Control Register */\n+\tunsigned int imsc; /* 0x00000084 */\n+\t/* I2C Masked Interrupt Status Register */\n+\tunsigned int mis; /* 0x00000088 */\n+\t/* I2C Interrupt Clear Register */\n+\tunsigned int icr; /* 0x0000008C */\n+\t/* I2C Interrupt Set Register */\n+\tunsigned int isr; /* 0x00000090 */\n+\t/* I2C DMA Enable Register */\n+\tunsigned int dmae; /* 0x00000094 */\n+\t/* Reserved */\n+\tunsigned int res_6[8154]; /* 0x00000098 */\n+\t/* I2C Transmit Data Register */\n+\tunsigned int txd; /* 0x00008000 */\n+\t/* Reserved */\n+\tunsigned int res_7[4095]; /* 0x00008004 */\n+\t/* I2C Receive Data Register */\n+\tunsigned int rxd; /* 0x0000C000 */\n+\t/* Reserved */\n+\tunsigned int res_8[4095]; /* 0x0000C004 */\n+};\n+\n+/*\n+ * Clock Divider for Normal Run Mode\n+ * Max 8-bit divider value. IF RMC is 0 the module is disabled. Note: As long\n+ * as the new divider value RMC is not valid, the register returns 0x0000 00xx\n+ * on reading.\n+ */\n+#define I2C_CLC_RMC_MASK 0x0000FF00\n+/* field offset */\n+#define I2C_CLC_RMC_OFFSET 8\n+\n+/* Fields of \"I2C Identification Register\" */\n+/* Module ID */\n+#define I2C_ID_ID_MASK 0x0000FF00\n+/* field offset */\n+#define I2C_ID_ID_OFFSET 8\n+/* Revision */\n+#define I2C_ID_REV_MASK 0x000000FF\n+/* field offset */\n+#define I2C_ID_REV_OFFSET 0\n+\n+/* Fields of \"I2C Interrupt Mask Control Register\" */\n+/* Enable */\n+#define I2C_IMSC_BREQ_INT_EN 0x00000008\n+/* Enable */\n+#define I2C_IMSC_LBREQ_INT_EN 0x00000004\n+\n+/* Fields of \"I2C Fractional Divider Configuration Register\" */\n+/* field offset */\n+#define I2C_FDIV_CFG_INC_OFFSET 16\n+\n+/* Fields of \"I2C Interrupt Mask Control Register\" */\n+/* Enable */\n+#define I2C_IMSC_I2C_P_INT_EN 0x00000020\n+/* Enable */\n+#define I2C_IMSC_I2C_ERR_INT_EN 0x00000010\n+\n+/* Fields of \"I2C Error Interrupt Request Source Status Register\" */\n+/* TXF_OFL */\n+#define I2C_ERR_IRQSS_TXF_OFL 0x00000008\n+/* TXF_UFL */\n+#define I2C_ERR_IRQSS_TXF_UFL 0x00000004\n+/* RXF_OFL */\n+#define I2C_ERR_IRQSS_RXF_OFL 0x00000002\n+/* RXF_UFL */\n+#define I2C_ERR_IRQSS_RXF_UFL 0x00000001\n+\n+/* Fields of \"I2C Raw Interrupt Status Register\" */\n+/* Read: Interrupt occurred. */\n+#define I2C_RIS_I2C_ERR_INT_INTOCC 0x00000010\n+/* Read: Interrupt occurred. */\n+#define I2C_RIS_I2C_P_INT_INTOCC 0x00000020\n+\n+/* Fields of \"I2C FIFO Configuration Register\" */\n+/* TX FIFO Flow Control */\n+#define I2C_FIFO_CFG_TXFC 0x00020000\n+/* RX FIFO Flow Control */\n+#define I2C_FIFO_CFG_RXFC 0x00010000\n+/* Word aligned (character alignment of four characters) */\n+#define I2C_FIFO_CFG_TXFA_TXFA2 0x00002000\n+/* Word aligned (character alignment of four characters) */\n+#define I2C_FIFO_CFG_RXFA_RXFA2 0x00000200\n+/* 1 word */\n+#define I2C_FIFO_CFG_TXBS_TXBS0 0x00000000\n+\n+/* Fields of \"I2C FIFO Configuration Register\" */\n+/* 1 word */\n+#define I2C_FIFO_CFG_RXBS_RXBS0 0x00000000\n+/* Stop on Packet End Enable */\n+#define I2C_ADDR_CFG_SOPE_EN 0x00200000\n+/* Stop on Not Acknowledge Enable */\n+#define I2C_ADDR_CFG_SONA_EN 0x00100000\n+/* Enable */\n+#define I2C_ADDR_CFG_MnS_EN 0x00080000\n+\n+/* Fields of \"I2C Interrupt Clear Register\" */\n+/* Clear */\n+#define I2C_ICR_BREQ_INT_CLR 0x00000008\n+/* Clear */\n+#define I2C_ICR_LBREQ_INT_CLR 0x00000004\n+\n+/* Fields of \"I2C Fractional Divider Configuration Register\" */\n+/* field offset */\n+#define I2C_FDIV_CFG_DEC_OFFSET 0\n+\n+/* Fields of \"I2C Bus Status Register\" */\n+/* Bus Status */\n+#define I2C_BUS_STAT_BS_MASK 0x00000003\n+/* Read from I2C Bus. */\n+#define I2C_BUS_STAT_RNW_READ 0x00000004\n+/* I2C Bus is free. */\n+#define I2C_BUS_STAT_BS_FREE 0x00000000\n+/*\n+ * The device is working as master and has claimed the control on the\n+ * I2C-bus (busy master).\n+ */\n+#define I2C_BUS_STAT_BS_BM 0x00000002\n+\n+/* Fields of \"I2C RUN Control Register\" */\n+/* Enable */\n+#define I2C_RUN_CTRL_RUN_EN 0x00000001\n+\n+/* Fields of \"I2C End Data Control Register\" */\n+/*\n+ * Set End of Transmission\n+ * Note:Do not write '1' to this bit when bus is free. This will cause an\n+ * abort after the first byte when a new transfer is started.\n+ */\n+#define I2C_ENDD_CTRL_SETEND 0x00000002\n+\n+/* Fields of \"I2C Protocol Interrupt Request Source Status Register\" */\n+/* NACK */\n+#define I2C_P_IRQSS_NACK 0x00000010\n+/* AL */\n+#define I2C_P_IRQSS_AL 0x00000008\n+/* RX */\n+#define I2C_P_IRQSS_RX 0x00000040\n+/* TX_END */\n+#define I2C_P_IRQSS_TX_END 0x00000020\n+\n+\n+#endif /* I2C_LANTIQ_H */\n"
  },
  {
    "path": "target/linux/lantiq/patches-5.10/0035-owrt-lantiq-wifi-and-ethernet-eeprom-handling.patch",
    "content": "From f8c5db89e793a4bc6c1e87bd7b3a5cec16b75bc3 Mon Sep 17 00:00:00 2001\nFrom: John Crispin <blogic@openwrt.org>\nDate: Wed, 10 Sep 2014 22:42:14 +0200\nSubject: [PATCH 35/36] owrt: lantiq: wifi and ethernet eeprom handling\n\nSigned-off-by: John Crispin <blogic@openwrt.org>\n---\n .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h |   3 +\n arch/mips/lantiq/xway/Makefile                     |   3 +\n arch/mips/lantiq/xway/ath5k_eep.c                  | 136 +++++++++++++++++++++\n arch/mips/lantiq/xway/eth_mac.c                    |  25 ++++\n drivers/net/ethernet/lantiq_etop.c                 |   6 +-\n 5 files changed, 172 insertions(+), 1 deletion(-)\n create mode 100644 arch/mips/lantiq/xway/ath5k_eep.c\n create mode 100644 arch/mips/lantiq/xway/eth_mac.c\n\n--- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h\n+++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h\n@@ -102,5 +102,8 @@ int xrx200_gphy_boot(struct device *dev,\n extern void ltq_pmu_enable(unsigned int module);\n extern void ltq_pmu_disable(unsigned int module);\n \n+/* allow the ethernet driver to load a flash mapped mac addr */\n+const u8* ltq_get_eth_mac(void);\n+\n #endif /* CONFIG_SOC_TYPE_XWAY */\n #endif /* _LTQ_XWAY_H__ */\n--- a/arch/mips/lantiq/xway/Makefile\n+++ b/arch/mips/lantiq/xway/Makefile\n@@ -8,3 +8,6 @@ obj-y += timer.o\n endif\n \n obj-y += vmmc.o\n+\n+obj-y += eth_mac.o\n+obj-$(CONFIG_PCI) += ath5k_eep.o\n--- /dev/null\n+++ b/arch/mips/lantiq/xway/ath5k_eep.c\n@@ -0,0 +1,136 @@\n+/*\n+ *  Copyright (C) 2011 Luca Olivetti <luca@ventoso.org>\n+ *  Copyright (C) 2011 John Crispin <blogic@openwrt.org>\n+ *  Copyright (C) 2011 Andrej Vlašić <andrej.vlasic0@gmail.com>\n+ *  Copyright (C) 2013 Álvaro Fernández Rojas <noltari@gmail.com>\n+ *  Copyright (C) 2013 Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us>\n+ *  Copyright (C) 2015 Vittorio Gambaletta <openwrt@vittgam.net>\n+ *\n+ *  This program is free software; you can redistribute it and/or modify it\n+ *  under the terms of the GNU General Public License version 2 as published\n+ *  by the Free Software Foundation.\n+ */\n+\n+#include <linux/init.h>\n+#include <linux/platform_device.h>\n+#include <linux/etherdevice.h>\n+#include <linux/ath5k_platform.h>\n+#include <linux/pci.h>\n+#include <linux/err.h>\n+#include <linux/mtd/mtd.h>\n+#include <lantiq_soc.h>\n+\n+extern int (*ltq_pci_plat_dev_init)(struct pci_dev *dev);\n+struct ath5k_platform_data ath5k_pdata;\n+static u8 athxk_eeprom_mac[6];\n+\n+static int ath5k_pci_plat_dev_init(struct pci_dev *dev)\n+{\n+\tdev->dev.platform_data = &ath5k_pdata;\n+\treturn 0;\n+}\n+\n+static int ath5k_eep_load;\n+int __init of_ath5k_eeprom_probe(struct platform_device *pdev)\n+{\n+\tstruct device_node *np = pdev->dev.of_node, *mtd_np = NULL;\n+\tint mac_offset;\n+\tu32 mac_inc = 0;\n+\tint i;\n+\tstruct mtd_info *the_mtd;\n+\tsize_t flash_readlen;\n+\tconst __be32 *list;\n+\tconst char *part;\n+\tphandle phandle;\n+\n+\tlist = of_get_property(np, \"ath,eep-flash\", &i);\n+\tif (!list || (i != (2 * sizeof(*list))))\n+\t\treturn -ENODEV;\n+\n+\tphandle = be32_to_cpup(list++);\n+\tif (phandle)\n+\t\tmtd_np = of_find_node_by_phandle(phandle);\n+\n+\tif (!mtd_np)\n+\t\treturn -ENODEV;\n+\n+\tpart = of_get_property(mtd_np, \"label\", NULL);\n+\tif (!part)\n+\t\tpart = mtd_np->name;\n+\n+\tthe_mtd = get_mtd_device_nm(part);\n+\tif (IS_ERR(the_mtd))\n+\t\treturn -ENODEV;\n+\n+\tath5k_pdata.eeprom_data = kmalloc(ATH5K_PLAT_EEP_MAX_WORDS<<1, GFP_KERNEL);\n+\n+\ti = mtd_read(the_mtd, be32_to_cpup(list), ATH5K_PLAT_EEP_MAX_WORDS << 1,\n+\t\t&flash_readlen, (void *) ath5k_pdata.eeprom_data);\n+\n+\tif (!of_property_read_u32(np, \"ath,mac-offset\", &mac_offset)) {\n+\t\tsize_t mac_readlen;\n+\t\tmtd_read(the_mtd, mac_offset, 6, &mac_readlen,\n+\t\t\t(void *) athxk_eeprom_mac);\n+\t}\n+\tput_mtd_device(the_mtd);\n+\n+\tif (((ATH5K_PLAT_EEP_MAX_WORDS<<1) != flash_readlen) || i) {\n+\t\tdev_err(&pdev->dev, \"failed to load eeprom from mtd\\n\");\n+\t\treturn -ENODEV;\n+\t}\n+\n+\tif (of_find_property(np, \"ath,eep-swap\", NULL))\n+\t\tfor (i = 0; i < ATH5K_PLAT_EEP_MAX_WORDS; i++)\n+\t\t\tath5k_pdata.eeprom_data[i] = swab16(ath5k_pdata.eeprom_data[i]);\n+\n+\tif (!is_valid_ether_addr(athxk_eeprom_mac) && ltq_get_eth_mac())\n+\t\tether_addr_copy(athxk_eeprom_mac, ltq_get_eth_mac());\n+\n+\tif (!is_valid_ether_addr(athxk_eeprom_mac)) {\n+\t\tdev_warn(&pdev->dev, \"using random mac\\n\");\n+\t\trandom_ether_addr(athxk_eeprom_mac);\n+\t}\n+\n+\tif (!of_property_read_u32(np, \"ath,mac-increment\", &mac_inc))\n+\t\tathxk_eeprom_mac[5] += mac_inc;\n+\n+\tath5k_pdata.macaddr = athxk_eeprom_mac;\n+\tltq_pci_plat_dev_init = ath5k_pci_plat_dev_init;\n+\n+\tdev_info(&pdev->dev, \"loaded ath5k eeprom\\n\");\n+\n+\treturn 0;\n+}\n+\n+static struct of_device_id ath5k_eeprom_ids[] = {\n+\t{ .compatible = \"ath5k,eeprom\" },\n+\t{ }\n+};\n+\n+static struct platform_driver ath5k_eeprom_driver = {\n+\t.driver\t\t= {\n+\t\t.name\t\t= \"ath5k,eeprom\",\n+\t\t.owner\t= THIS_MODULE,\n+\t\t.of_match_table\t= of_match_ptr(ath5k_eeprom_ids),\n+\t},\n+};\n+\n+static int __init of_ath5k_eeprom_init(void)\n+{\n+\tint ret = platform_driver_probe(&ath5k_eeprom_driver, of_ath5k_eeprom_probe);\n+\n+\tif (ret)\n+\t\tath5k_eep_load = 1;\n+\n+\treturn ret;\n+}\n+\n+static int __init of_ath5k_eeprom_init_late(void)\n+{\n+\tif (!ath5k_eep_load)\n+\t\treturn 0;\n+\n+\treturn platform_driver_probe(&ath5k_eeprom_driver, of_ath5k_eeprom_probe);\n+}\n+late_initcall(of_ath5k_eeprom_init_late);\n+subsys_initcall(of_ath5k_eeprom_init);\n--- /dev/null\n+++ b/arch/mips/lantiq/xway/eth_mac.c\n@@ -0,0 +1,25 @@\n+/*\n+ *  Copyright (C) 2012 John Crispin <blogic@openwrt.org>\n+ *\n+ *  This program is free software; you can redistribute it and/or modify it\n+ *  under the terms of the GNU General Public License version 2 as published\n+ *  by the Free Software Foundation.\n+ */\n+\n+#include <linux/init.h>\n+#include <linux/if_ether.h>\n+\n+static u8 eth_mac[6];\n+static int eth_mac_set;\n+\n+const u8* ltq_get_eth_mac(void)\n+{\n+\treturn eth_mac;\n+}\n+\n+static int __init setup_ethaddr(char *str)\n+{\n+\teth_mac_set = mac_pton(str, eth_mac);\n+\treturn !eth_mac_set;\n+}\n+early_param(\"ethaddr\", setup_ethaddr);\n--- a/drivers/net/ethernet/lantiq_etop.c\n+++ b/drivers/net/ethernet/lantiq_etop.c\n@@ -757,7 +757,11 @@ ltq_etop_init(struct net_device *dev)\n \tif (err)\n \t\tgoto err_hw;\n \n-\tmemcpy(&mac, &priv->pldata->mac, sizeof(struct sockaddr));\n+\tmemcpy(&mac.sa_data, ltq_get_eth_mac(), ETH_ALEN);\n+\n+\tif (priv->mac && !is_valid_ether_addr(mac.sa_data))\n+\t\tmemcpy(&mac.sa_data, priv->mac, ETH_ALEN);\n+\n \tif (!is_valid_ether_addr(mac.sa_data)) {\n \t\tpr_warn(\"etop: invalid MAC, using random\\n\");\n \t\teth_random_addr(mac.sa_data);\n"
  },
  {
    "path": "target/linux/lantiq/patches-5.10/0042-arch-mips-increase-io_space_limit.patch",
    "content": "From 9807eb80a1b3bad7a4a89aa6566497bb1cadd6ef Mon Sep 17 00:00:00 2001\nFrom: John Crispin <john@phrozen.org>\nDate: Fri, 3 Jun 2016 13:12:20 +0200\nSubject: [PATCH] arch: mips: increase io_space_limit\n\nthis value comes from x86 and breaks some pci devices\n\nSigned-off-by: John Crispin <john@phrozen.org>\n---\n arch/mips/include/asm/mach-lantiq/spaces.h | 8 ++++++++\n 1 file changed, 8 insertions(+)\n create mode 100644 arch/mips/include/asm/mach-lantiq/spaces.h\n\n--- /dev/null\n+++ b/arch/mips/include/asm/mach-lantiq/spaces.h\n@@ -0,0 +1,8 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+#ifndef __ASM_MACH_LANTIQ_SPACES_H_\n+#define __ASM_MACH_LANTIQ_SPACES_H_\n+\n+#define IO_SPACE_LIMIT  0xffffffff\n+\n+#include <asm/mach-generic/spaces.h>\n+#endif\n"
  },
  {
    "path": "target/linux/lantiq/patches-5.10/0050-USB-DWC2-make-the-lantiq-settings-match-vendor-drive.patch",
    "content": "From de2cad82c4d0872066f83ce59462603852b47f03 Mon Sep 17 00:00:00 2001\nFrom: Hauke Mehrtens <hauke@hauke-m.de>\nDate: Fri, 6 Jan 2017 17:55:24 +0100\nSubject: [PATCH 2/2] usb: dwc2:  add support for other Lantiq SoCs\n\nThe size of the internal RAM of the DesignWare USB controller changed\nbetween the different Lantiq SoCs. We have the following sizes:\n\nAmazon + Danube: 8 KByte\nAmazon SE + arx100: 2 KByte\nxrx200 + xrx300: 2.5 KByte\n\nFor Danube SoC we do not provide the params and let the driver decide\nto use sane defaults, for the Amazon SE and arx100 we use small fifos\nand for the xrx200 and xrx300 SCs a little bit bigger periodic fifo.\nThe auto detection of max_transfer_size and max_packet_count should\nwork, so remove it.\n\nSigned-off-by: Hauke Mehrtens <hauke@hauke-m.de>\n---\n drivers/usb/dwc2/platform.c | 46 ++++++++++++++++++++++++++++++++++++++-------\n 1 file changed, 39 insertions(+), 7 deletions(-)\n\n--- a/drivers/usb/dwc2/params.c\n+++ b/drivers/usb/dwc2/params.c\n@@ -92,7 +92,14 @@ static void dwc2_set_rk_params(struct dw\n \tp->power_down = DWC2_POWER_DOWN_PARAM_NONE;\n }\n \n-static void dwc2_set_ltq_params(struct dwc2_hsotg *hsotg)\n+static void dwc2_set_ltq_danube_params(struct dwc2_hsotg *hsotg)\n+{\n+\tstruct dwc2_core_params *p = &hsotg->params;\n+\n+\tp->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;\n+}\n+\n+static void dwc2_set_ltq_ase_params(struct dwc2_hsotg *hsotg)\n {\n \tstruct dwc2_core_params *p = &hsotg->params;\n \n@@ -100,12 +107,20 @@ static void dwc2_set_ltq_params(struct d\n \tp->host_rx_fifo_size = 288;\n \tp->host_nperio_tx_fifo_size = 128;\n \tp->host_perio_tx_fifo_size = 96;\n-\tp->max_transfer_size = 65535;\n-\tp->max_packet_count = 511;\n \tp->ahbcfg = GAHBCFG_HBSTLEN_INCR16 <<\n \t\tGAHBCFG_HBSTLEN_SHIFT;\n }\n \n+static void dwc2_set_ltq_xrx200_params(struct dwc2_hsotg *hsotg)\n+{\n+\tstruct dwc2_core_params *p = &hsotg->params;\n+\n+\tp->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;\n+\tp->host_rx_fifo_size = 288;\n+\tp->host_nperio_tx_fifo_size = 128;\n+\tp->host_perio_tx_fifo_size = 136;\n+}\n+\n static void dwc2_set_amlogic_params(struct dwc2_hsotg *hsotg)\n {\n \tstruct dwc2_core_params *p = &hsotg->params;\n@@ -196,8 +211,11 @@ const struct of_device_id dwc2_of_match_\n \t{ .compatible = \"brcm,bcm2835-usb\", .data = dwc2_set_bcm_params },\n \t{ .compatible = \"hisilicon,hi6220-usb\", .data = dwc2_set_his_params  },\n \t{ .compatible = \"rockchip,rk3066-usb\", .data = dwc2_set_rk_params },\n-\t{ .compatible = \"lantiq,arx100-usb\", .data = dwc2_set_ltq_params },\n-\t{ .compatible = \"lantiq,xrx200-usb\", .data = dwc2_set_ltq_params },\n+\t{ .compatible = \"lantiq,danube-usb\", .data = &dwc2_set_ltq_danube_params },\n+\t{ .compatible = \"lantiq,ase-usb\", .data = &dwc2_set_ltq_ase_params },\n+\t{ .compatible = \"lantiq,arx100-usb\", .data = &dwc2_set_ltq_ase_params },\n+\t{ .compatible = \"lantiq,xrx200-usb\", .data = &dwc2_set_ltq_xrx200_params },\n+\t{ .compatible = \"lantiq,xrx300-usb\", .data = &dwc2_set_ltq_xrx200_params },\n \t{ .compatible = \"snps,dwc2\" },\n \t{ .compatible = \"samsung,s3c6400-hsotg\",\n \t  .data = dwc2_set_s3c6400_params },\n"
  },
  {
    "path": "target/linux/lantiq/patches-5.10/0051-MIPS-lantiq-improve-USB-initialization.patch",
    "content": "From 14909c4e4e836925668e74fc6e0e85ba0283cbf9 Mon Sep 17 00:00:00 2001\nFrom: Hauke Mehrtens <hauke@hauke-m.de>\nDate: Fri, 6 Jan 2017 17:40:12 +0100\nSubject: [PATCH 2/2] MIPS: lantiq: improve USB initialization\n\nThis adds code to initialize the USB controller and PHY also on Danube,\nAmazon SE and AR10. This code is based on the Vendor driver from\ndifferent UGW versions and compared to the hardware documentation.\n\nSigned-off-by: Hauke Mehrtens <hauke@hauke-m.de>\n---\n arch/mips/lantiq/xway/sysctrl.c |  20 +++++++\n 2 files changed, 110 insertions(+), 30 deletions(-)\n\n\n--- a/arch/mips/lantiq/xway/sysctrl.c\n+++ b/arch/mips/lantiq/xway/sysctrl.c\n@@ -248,6 +248,25 @@ static void pmu_disable(struct clk *clk)\n \t\tpr_warn(\"deactivating PMU module failed!\");\n }\n \n+static void usb_set_clock(void)\n+{\n+\tunsigned int val = ltq_cgu_r32(ifccr);\n+\n+\tif (of_machine_is_compatible(\"lantiq,ar10\") ||\n+\t    of_machine_is_compatible(\"lantiq,grx390\")) {\n+\t\tval &= ~0x03; /* XTAL divided by 3 */\n+\t} else if (of_machine_is_compatible(\"lantiq,ar9\") ||\n+\t\t   of_machine_is_compatible(\"lantiq,vr9\")) {\n+\t\t/* TODO: this depends on the XTAL frequency */\n+\t\tval |= 0x03; /* XTAL divided by 3 */\n+\t} else if (of_machine_is_compatible(\"lantiq,ase\")) {\n+\t\tval |= 0x20; /* from XTAL */\n+\t} else if (of_machine_is_compatible(\"lantiq,danube\")) {\n+\t\tval |= 0x30; /* 12 MHz, generated from 36 MHz */\n+\t}\n+\tltq_cgu_w32(val, ifccr);\n+}\n+\n /* the pci enable helper */\n static int pci_enable(struct clk *clk)\n {\n@@ -571,4 +590,5 @@ void __init ltq_soc_init(void)\n \t\tclkdev_add_pmu(\"1e116000.mei\", \"dfe\", 1, 0, PMU_DFE);\n \t\tclkdev_add_pmu(\"1e100400.serial\", NULL, 1, 0, PMU_ASC0);\n \t}\n+\tusb_set_clock();\n }\n"
  },
  {
    "path": "target/linux/lantiq/patches-5.10/0101-find_active_root.patch",
    "content": "--- a/drivers/mtd/parsers/ofpart_core.c\n+++ b/drivers/mtd/parsers/ofpart_core.c\n@@ -38,6 +38,38 @@ static bool node_has_compatible(struct d\n \treturn of_get_property(pp, \"compatible\", NULL);\n }\n \n+static uint8_t * brnboot_get_selected_root_part(struct mtd_info *master,\n+\t\t\t\t\t\tloff_t offset)\n+{\n+\tstatic uint8_t root_id;\n+\tint err, len;\n+\n+\terr = mtd_read(master, offset, 0x01, &len, &root_id);\n+\n+\tif (mtd_is_bitflip(err) || !err)\n+\t\treturn &root_id;\n+\n+\treturn NULL;\n+}\n+\n+static void brnboot_set_active_root_part(struct mtd_partition *pparts,\n+\t\t\t\t\t struct device_node **part_nodes,\n+\t\t\t\t\t int nr_parts,\n+\t\t\t\t\t uint8_t *root_id)\n+{\n+\tint i;\n+\n+\tfor (i = 0; i < nr_parts; i++) {\n+\t\tint part_root_id;\n+\n+\t\tif (!of_property_read_u32(part_nodes[i], \"brnboot,root-id\", &part_root_id)\n+\t\t    && part_root_id == *root_id) {\n+\t\t\tpparts[i].name = \"firmware\";\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+}\n+\n static int parse_fixed_partitions(struct mtd_info *master,\n \t\t\t\t  const struct mtd_partition **pparts,\n \t\t\t\t  struct mtd_part_parser_data *data)\n@@ -51,6 +83,8 @@ static int parse_fixed_partitions(struct\n \tstruct device_node *pp;\n \tint nr_parts, i, ret = 0;\n \tbool dedicated = true;\n+\tuint8_t *proot_id = NULL;\n+\tstruct device_node **part_nodes;\n \n \t/* Pull of_node from the master device node */\n \tmtd_node = mtd_get_of_node(master);\n@@ -95,7 +129,9 @@ static int parse_fixed_partitions(struct\n \t\treturn 0;\n \n \tparts = kcalloc(nr_parts, sizeof(*parts), GFP_KERNEL);\n-\tif (!parts)\n+\tpart_nodes = kcalloc(nr_parts, sizeof(*part_nodes), GFP_KERNEL);\n+\n+\tif (!parts || !part_nodes)\n \t\treturn -ENOMEM;\n \n \ti = 0;\n@@ -147,6 +183,11 @@ static int parse_fixed_partitions(struct\n \t\tif (of_property_read_bool(pp, \"slc-mode\"))\n \t\t\tparts[i].add_flags |= MTD_SLC_ON_MLC_EMULATION;\n \n+\t\tif (!proot_id && of_device_is_compatible(pp, \"brnboot,root-selector\"))\n+\t\t\tproot_id = brnboot_get_selected_root_part(master, parts[i].offset);\n+\n+\t\tpart_nodes[i] = pp;\n+\n \t\ti++;\n \t}\n \n@@ -156,6 +197,11 @@ static int parse_fixed_partitions(struct\n \tif (quirks && quirks->post_parse)\n \t\tquirks->post_parse(master, parts, nr_parts);\n \n+\tif (proot_id)\n+\t\tbrnboot_set_active_root_part(parts, part_nodes, nr_parts, proot_id);\n+\n+\tkfree(part_nodes);\n+\n \t*pparts = parts;\n \treturn nr_parts;\n \n@@ -166,6 +212,7 @@ ofpart_fail:\n ofpart_none:\n \tof_node_put(pp);\n \tkfree(parts);\n+\tkfree(part_nodes);\n \treturn ret;\n }\n \n"
  },
  {
    "path": "target/linux/lantiq/patches-5.10/0151-lantiq-ifxmips_pcie-use-of.patch",
    "content": "--- a/arch/mips/pci/ifxmips_pcie.c\n+++ b/arch/mips/pci/ifxmips_pcie.c\n@@ -16,8 +16,15 @@\n #include <asm/paccess.h>\n #include <linux/pci.h>\n #include <linux/pci_regs.h>\n+#include <linux/phy/phy.h>\n+#include <linux/regmap.h>\n+#include <linux/reset.h>\n+#include <linux/mfd/syscon.h>\n #include <linux/module.h>\n \n+#include <linux/of_gpio.h>\n+#include <linux/of_platform.h>\n+\n #include \"ifxmips_pcie.h\"\n #include \"ifxmips_pcie_reg.h\"\n \n@@ -40,6 +47,10 @@\n static DEFINE_SPINLOCK(ifx_pcie_lock);\n \n u32 g_pcie_debug_flag = PCIE_MSG_ANY & (~PCIE_MSG_CFG);\n+static int pcie_reset_gpio;\n+static struct phy *ltq_pcie_phy;\n+static struct reset_control *ltq_pcie_reset;\n+static struct regmap *ltq_rcu_regmap;\n \n static ifx_pcie_irq_t pcie_irqs[IFX_PCIE_CORE_NR] = {\n     {\n@@ -82,6 +93,22 @@ void ifx_pcie_debug(const char *fmt, ...\n \tprintk(\"%s\", buf);\n }\n \n+static inline void pcie_ep_gpio_rst_init(int pcie_port)\n+{\n+\tgpio_direction_output(pcie_reset_gpio, 1);\n+\tgpio_set_value(pcie_reset_gpio, 1);\n+}\n+\n+static inline void pcie_device_rst_assert(int pcie_port)\n+{\n+\tgpio_set_value(pcie_reset_gpio, 0);\n+}\n+\n+static inline void pcie_device_rst_deassert(int pcie_port)\n+{\n+\tmdelay(100);\n+\tgpio_direction_output(pcie_reset_gpio, 1);\n+}\n \n static inline int pcie_ltssm_enable(int pcie_port)\n {\n@@ -988,10 +1015,22 @@ int  ifx_pcie_bios_plat_dev_init(struct\n static int\n pcie_rc_initialize(int pcie_port)\n {\n-\tint i;\n+\tint i, ret;\n #define IFX_PCIE_PHY_LOOP_CNT  5\n \n-\tpcie_rcu_endian_setup(pcie_port);\n+\tregmap_update_bits(ltq_rcu_regmap, 0x4c, IFX_RCU_AHB_BE_PCIE_M,\n+\t\t\t   IFX_RCU_AHB_BE_PCIE_M);\n+\n+#ifdef CONFIG_IFX_PCIE_HW_SWAP\n+\tregmap_update_bits(ltq_rcu_regmap, 0x4c, IFX_RCU_AHB_BE_PCIE_S,\n+\t\t\t   IFX_RCU_AHB_BE_PCIE_S);\n+#else\n+\tregmap_update_bits(ltq_rcu_regmap, 0x4c, IFX_RCU_AHB_BE_PCIE_S,\n+\t\t\t   0x0);\n+#endif\n+\n+\tregmap_update_bits(ltq_rcu_regmap, 0x4c, IFX_RCU_AHB_BE_XBAR_M,\n+\t\t\t   0x0);\n \n \tpcie_ep_gpio_rst_init(pcie_port);\n \n@@ -1000,26 +1039,21 @@ pcie_rc_initialize(int pcie_port)\n \t* reset PCIe PHY will solve this issue \n \t*/\n \tfor (i = 0; i < IFX_PCIE_PHY_LOOP_CNT; i++) {\n-\t\t/* Disable PCIe PHY Analog part for sanity check */\n-\t\tpcie_phy_pmu_disable(pcie_port);\n-\n-\t\tpcie_phy_rst_assert(pcie_port);\n-\t\tpcie_phy_rst_deassert(pcie_port);\n-\n-\t\t/* Make sure PHY PLL is stable */\n-\t\tudelay(20);\n-\n-\t\t/* PCIe Core reset enabled, low active, sw programmed */\n-\t\tpcie_core_rst_assert(pcie_port);\n+\t\tret = phy_init(ltq_pcie_phy);\n+\t\tif (ret)\n+\t\t\tcontinue;\n \n \t\t/* Put PCIe EP in reset status */\n \t\tpcie_device_rst_assert(pcie_port);\n \n-\t\t/* PCI PHY & Core reset disabled, high active, sw programmed */\n-\t\tpcie_core_rst_deassert(pcie_port);\n+\t\tudelay(1);\n+\t\treset_control_deassert(ltq_pcie_reset);\n \n-\t\t/* Already in a quiet state, program PLL, enable PHY, check ready bit */\n-\t\tpcie_phy_clock_mode_setup(pcie_port);\n+\t\tret = phy_power_on(ltq_pcie_phy);\n+\t\tif (ret) {\n+\t\t\tphy_exit(ltq_pcie_phy);\n+\t\t\tcontinue;\n+\t\t}\n \n \t\t/* Enable PCIe PHY and Clock */\n \t\tpcie_core_pmu_setup(pcie_port);\n@@ -1035,6 +1069,10 @@ pcie_rc_initialize(int pcie_port)\n \t\t/* Once link is up, break out */\n \t\tif (pcie_app_loigc_setup(pcie_port) == 0)\n \t\t\tbreak;\n+\n+\t\tphy_power_off(ltq_pcie_phy);\n+\t\treset_control_assert(ltq_pcie_reset);\n+\t\tphy_exit(ltq_pcie_phy);\n \t}\n \tif (i >= IFX_PCIE_PHY_LOOP_CNT) {\n \t\tprintk(KERN_ERR \"%s link up failed!!!!!\\n\", __func__);\n@@ -1045,17 +1083,67 @@ pcie_rc_initialize(int pcie_port)\n \treturn 0;\n }\n \n-static int __init ifx_pcie_bios_init(void)\n+static int ifx_pcie_bios_probe(struct platform_device *pdev)\n {\n+    struct device_node *node = pdev->dev.of_node;\n     void __iomem *io_map_base;\n     int pcie_port;\n     int startup_port;\n+    struct device_node *np;\n+    struct pci_bus *bus;\n+\n+    /*\n+     * In case a PCI device is physical present, the Lantiq PCI driver need\n+     * to be loaded prior to the Lantiq PCIe driver. Otherwise none of them\n+     * will work.\n+     *\n+     * In case the lantiq PCI driver is enabled in the device tree, check if\n+     * a PCI bus (hopefully the one of the Lantiq PCI driver one) is already\n+     * registered.\n+     *\n+     * It will fail if there is another PCI controller, this controller is\n+     * registered before the Lantiq PCIe driver is probe and the lantiq PCI\n+     */\n+    np = of_find_compatible_node(NULL, NULL, \"lantiq,pci-xway\");\n+\n+    if (of_device_is_available(np)) {\n+        bus = pci_find_next_bus(bus);\n+\n+        if (!bus)\n+\t     return -EPROBE_DEFER;\n+    }\n \n     /* Enable AHB Master/ Slave */\n     pcie_ahb_pmu_setup();\n \n     startup_port = IFX_PCIE_PORT0;\n-    \n+\n+    ltq_pcie_phy = devm_phy_get(&pdev->dev, \"pcie\");\n+    if (IS_ERR(ltq_pcie_phy)) {\n+        dev_err(&pdev->dev, \"failed to get the PCIe PHY\\n\");\n+        return PTR_ERR(ltq_pcie_phy);\n+    }\n+\n+    ltq_pcie_reset = devm_reset_control_get_shared(&pdev->dev, NULL);\n+    if (IS_ERR(ltq_pcie_reset)) {\n+        dev_err(&pdev->dev, \"failed to get the PCIe reset line\\n\");\n+        return PTR_ERR(ltq_pcie_reset);\n+    }\n+\n+    ltq_rcu_regmap = syscon_regmap_lookup_by_phandle(node, \"lantiq,rcu\");\n+    if (IS_ERR(ltq_rcu_regmap))\n+        return PTR_ERR(ltq_rcu_regmap);\n+\n+    pcie_reset_gpio = of_get_named_gpio(node, \"gpio-reset\", 0);\n+    if (gpio_is_valid(pcie_reset_gpio)) {\n+        int ret = devm_gpio_request(&pdev->dev, pcie_reset_gpio, \"pcie-reset\");\n+        if (ret) {\n+            dev_err(&pdev->dev, \"failed to request gpio %d\\n\", pcie_reset_gpio);\n+            return ret;\n+        }\n+        gpio_direction_output(pcie_reset_gpio, 1);\n+    }\n+\n     for (pcie_port = startup_port; pcie_port < IFX_PCIE_CORE_NR; pcie_port++){\n \tif (pcie_rc_initialize(pcie_port) == 0) {\n \t    IFX_PCIE_PRINT(PCIE_MSG_INIT, \"%s: ifx_pcie_cfg_base 0x%p\\n\", \n@@ -1067,6 +1155,7 @@ static int __init ifx_pcie_bios_init(voi\n                 return -ENOMEM;\n             }\n             ifx_pcie_controller[pcie_port].pcic.io_map_base = (unsigned long)io_map_base;\n+            pci_load_of_ranges(&ifx_pcie_controller[pcie_port].pcic, node);\n \n             register_pci_controller(&ifx_pcie_controller[pcie_port].pcic);\n             /* XXX, clear error status */\n@@ -1083,6 +1172,30 @@ static int __init ifx_pcie_bios_init(voi\n \n     return 0;\n }\n+\n+static const struct of_device_id ifxmips_pcie_match[] = {\n+        { .compatible = \"lantiq,pcie-xrx200\" },\n+        {},\n+};\n+MODULE_DEVICE_TABLE(of, ifxmips_pcie_match);\n+\n+static struct platform_driver ltq_pci_driver = {\n+        .probe = ifx_pcie_bios_probe,\n+        .driver = {\n+                .name = \"pcie-xrx200\",\n+                .owner = THIS_MODULE,\n+                .of_match_table = ifxmips_pcie_match,\n+        },\n+};\n+\n+int __init ifx_pcie_bios_init(void)\n+{\n+        int ret = platform_driver_register(&ltq_pci_driver);\n+        if (ret)\n+                pr_info(\"pcie-xrx200: Error registering platform driver!\");\n+        return ret;\n+}\n+\n arch_initcall(ifx_pcie_bios_init);\n \n MODULE_LICENSE(\"GPL\");\n--- a/arch/mips/pci/ifxmips_pcie_vr9.h\n+++ b/arch/mips/pci/ifxmips_pcie_vr9.h\n@@ -22,8 +22,6 @@\n #include <linux/gpio.h>\n #include <lantiq_soc.h>\n \n-#define IFX_PCIE_GPIO_RESET  494\n-\n #define IFX_REG_R32    ltq_r32\n #define IFX_REG_W32    ltq_w32\n #define CONFIG_IFX_PCIE_HW_SWAP\n@@ -53,21 +51,6 @@\n #define OUT\t\t\t((volatile u32*)(IFX_GPIO + 0x0070))\n \n \n-static inline void pcie_ep_gpio_rst_init(int pcie_port)\n-{\n-\n-\tgpio_request(IFX_PCIE_GPIO_RESET, \"pcie-reset\");\n-\tgpio_direction_output(IFX_PCIE_GPIO_RESET, 1);\n-\tgpio_set_value(IFX_PCIE_GPIO_RESET, 1);\n-\n-/*    ifx_gpio_pin_reserve(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);\n-    ifx_gpio_output_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);\n-    ifx_gpio_dir_out_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);\n-    ifx_gpio_altsel0_clear(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);\n-    ifx_gpio_altsel1_clear(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);\n-    ifx_gpio_open_drain_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);*/\n-}\n-\n static inline void pcie_ahb_pmu_setup(void) \n {\n \t/* Enable AHB bus master/slave */\n@@ -79,24 +62,6 @@ static inline void pcie_ahb_pmu_setup(vo\n     //AHBS_PMU_SETUP(IFX_PMU_ENABLE);\n }\n \n-static inline void pcie_rcu_endian_setup(int pcie_port)\n-{\n-    u32 reg;\n-\n-    reg = IFX_REG_R32(IFX_RCU_AHB_ENDIAN);\n-#ifdef CONFIG_IFX_PCIE_HW_SWAP\n-    reg |= IFX_RCU_AHB_BE_PCIE_M;\n-    reg |= IFX_RCU_AHB_BE_PCIE_S;\n-    reg &= ~IFX_RCU_AHB_BE_XBAR_M;\n-#else \n-    reg |= IFX_RCU_AHB_BE_PCIE_M;\n-    reg &= ~IFX_RCU_AHB_BE_PCIE_S;\n-    reg &= ~IFX_RCU_AHB_BE_XBAR_M;\n-#endif /* CONFIG_IFX_PCIE_HW_SWAP */\n-    IFX_REG_W32(reg, IFX_RCU_AHB_ENDIAN);\n-    IFX_PCIE_PRINT(PCIE_MSG_REG, \"%s IFX_RCU_AHB_ENDIAN: 0x%08x\\n\", __func__, IFX_REG_R32(IFX_RCU_AHB_ENDIAN));\n-}\n-\n static inline void pcie_phy_pmu_enable(int pcie_port)\n {\n \tstruct clk *clk;\n@@ -115,17 +80,6 @@ static inline void pcie_phy_pmu_disable(\n //    PCIE_PHY_PMU_SETUP(IFX_PMU_DISABLE);\n }\n \n-static inline void pcie_pdi_big_endian(int pcie_port)\n-{\n-    u32 reg;\n-\n-    /* SRAM2PDI endianness control. */\n-    reg = IFX_REG_R32(IFX_RCU_AHB_ENDIAN);\n-    /* Config AHB->PCIe and PDI endianness */\n-    reg |= IFX_RCU_AHB_BE_PCIE_PDI;\n-    IFX_REG_W32(reg, IFX_RCU_AHB_ENDIAN);\n-}\n-\n static inline void pcie_pdi_pmu_enable(int pcie_port)\n {\n     /* Enable PDI to access PCIe PHY register */\n@@ -135,65 +89,6 @@ static inline void pcie_pdi_pmu_enable(i\n     //PDI_PMU_SETUP(IFX_PMU_ENABLE);\n }\n \n-static inline void pcie_core_rst_assert(int pcie_port)\n-{\n-    u32 reg;\n-\n-    reg = IFX_REG_R32(IFX_RCU_RST_REQ);\n-\n-    /* Reset PCIe PHY & Core, bit 22, bit 26 may be affected if write it directly  */\n-    reg |= 0x00400000;\n-    IFX_REG_W32(reg, IFX_RCU_RST_REQ);\n-}\n-\n-static inline void pcie_core_rst_deassert(int pcie_port)\n-{\n-    u32 reg;\n-\n-    /* Make sure one micro-second delay */\n-    udelay(1);\n-\n-    /* Reset PCIe PHY & Core, bit 22 */\n-    reg = IFX_REG_R32(IFX_RCU_RST_REQ);\n-    reg &= ~0x00400000;\n-    IFX_REG_W32(reg, IFX_RCU_RST_REQ);\n-}\n-\n-static inline void pcie_phy_rst_assert(int pcie_port)\n-{\n-    u32 reg;\n-\n-    reg = IFX_REG_R32(IFX_RCU_RST_REQ);\n-    reg |= 0x00001000; /* Bit 12 */\n-    IFX_REG_W32(reg, IFX_RCU_RST_REQ);\n-}\n-\n-static inline void pcie_phy_rst_deassert(int pcie_port)\n-{\n-    u32 reg;\n-\n-    /* Make sure one micro-second delay */\n-    udelay(1);\n-\n-    reg = IFX_REG_R32(IFX_RCU_RST_REQ);\n-    reg &= ~0x00001000; /* Bit 12 */\n-    IFX_REG_W32(reg, IFX_RCU_RST_REQ);\n-}\n-\n-static inline void pcie_device_rst_assert(int pcie_port)\n-{\n-\tgpio_set_value(IFX_PCIE_GPIO_RESET, 0);\n-//    ifx_gpio_output_clear(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);\n-}\n-\n-static inline void pcie_device_rst_deassert(int pcie_port)\n-{\n-    mdelay(100);\n-\tgpio_direction_output(IFX_PCIE_GPIO_RESET, 1);\n-//    gpio_set_value(IFX_PCIE_GPIO_RESET, 1);\n-    //ifx_gpio_output_set(IFX_PCIE_GPIO_RESET, ifx_pcie_gpio_module_id);\n-}\n-\n static inline void pcie_core_pmu_setup(int pcie_port)\n {\n \tstruct clk *clk;\n--- a/arch/mips/pci/Makefile\n+++ b/arch/mips/pci/Makefile\n@@ -43,7 +43,7 @@ obj-$(CONFIG_PCI_LANTIQ)\t+= pci-lantiq.o\n obj-$(CONFIG_SOC_MT7620)\t+= pci-mt7620.o\n obj-$(CONFIG_SOC_RT288X)\t+= pci-rt2880.o\n obj-$(CONFIG_SOC_RT3883)\t+= pci-rt3883.o\n-obj-$(CONFIG_PCIE_LANTIQ)\t+= ifxmips_pcie_phy.o ifxmips_pcie.o fixup-lantiq-pcie.o\n+obj-$(CONFIG_PCIE_LANTIQ)\t+= ifxmips_pcie.o fixup-lantiq-pcie.o\n obj-$(CONFIG_PCIE_LANTIQ_MSI)\t+= pcie-lantiq-msi.o\n obj-$(CONFIG_TANBAC_TB0219)\t+= fixup-tb0219.o\n obj-$(CONFIG_TANBAC_TB0226)\t+= fixup-tb0226.o\n"
  },
  {
    "path": "target/linux/lantiq/patches-5.10/0152-lantiq-VPE.patch",
    "content": "--- a/arch/mips/Kconfig\n+++ b/arch/mips/Kconfig\n@@ -2438,6 +2438,12 @@ config MIPS_VPE_LOADER\n \t  Includes a loader for loading an elf relocatable object\n \t  onto another VPE and running it.\n \n+config IFX_VPE_EXT\n+\tbool \"IFX APRP Extensions\"\n+\tdepends on MIPS_VPE_LOADER\n+\thelp\n+\t  IFX included extensions in APRP\n+\n config MIPS_VPE_LOADER_CMP\n \tbool\n \tdefault \"y\"\n--- a/arch/mips/include/asm/vpe.h\n+++ b/arch/mips/include/asm/vpe.h\n@@ -127,4 +127,13 @@ void cleanup_tc(struct tc *tc);\n \n int __init vpe_module_init(void);\n void __exit vpe_module_exit(void);\n+\n+/* For the explanation of the APIs please refer the section \"MT APRP Kernel\n+ * Programming\" in AR9 SW Architecture Specification\n+ */\n+int32_t vpe1_sw_start(void *sw_start_addr, uint32_t tcmask, uint32_t flags);\n+int32_t vpe1_sw_stop(uint32_t flags);\n+uint32_t vpe1_get_load_addr(uint32_t flags);\n+uint32_t vpe1_get_max_mem(uint32_t flags);\n+\n #endif /* _ASM_VPE_H */\n--- a/arch/mips/kernel/vpe-mt.c\n+++ b/arch/mips/kernel/vpe-mt.c\n@@ -29,6 +29,7 @@ int vpe_run(struct vpe *v)\n \tstruct vpe_notifications *notifier;\n \tunsigned int vpeflags;\n \tstruct tc *t;\n+\tunsigned long physical_memsize = 0L;\n \n \t/* check we are the Master VPE */\n \tlocal_irq_save(flags);\n@@ -417,6 +418,8 @@ int __init vpe_module_init(void)\n \t\t\t}\n \n \t\t\tv->ntcs = hw_tcs - aprp_cpu_index();\n+\t\t\twrite_tc_c0_tcbind((read_tc_c0_tcbind() &\n+\t\t\t\t\t\t~TCBIND_CURVPE) | 1);\n \n \t\t\t/* add the tc to the list of this vpe's tc's. */\n \t\t\tlist_add(&t->tc, &v->tc);\n@@ -519,3 +522,47 @@ void __exit vpe_module_exit(void)\n \t\t\trelease_vpe(v);\n \t}\n }\n+\n+#ifdef CONFIG_IFX_VPE_EXT\n+int32_t vpe1_sw_start(void *sw_start_addr, uint32_t tcmask, uint32_t flags)\n+{\n+\tenum vpe_state state;\n+\tstruct vpe *v = get_vpe(tclimit);\n+\tstruct vpe_notifications *not;\n+\n+\tif (tcmask || flags) {\n+\t\tpr_warn(\"Currently tcmask and flags should be 0. Other values are not supported\\n\");\n+\t\treturn -1;\n+\t}\n+\n+\tstate = xchg(&v->state, VPE_STATE_INUSE);\n+\tif (state != VPE_STATE_UNUSED) {\n+\t\tvpe_stop(v);\n+\n+\t\tlist_for_each_entry(not, &v->notify, list) {\n+\t\t\tnot->stop(tclimit);\n+\t\t}\n+\t}\n+\n+\tv->__start = (unsigned long)sw_start_addr;\n+\n+\tif (!vpe_run(v)) {\n+\t\tpr_debug(\"VPE loader: VPE1 running successfully\\n\");\n+\t\treturn 0;\n+\t}\n+\treturn -1;\n+}\n+EXPORT_SYMBOL(vpe1_sw_start);\n+\n+int32_t vpe1_sw_stop(uint32_t flags)\n+{\n+\tstruct vpe *v = get_vpe(tclimit);\n+\n+\tif (!vpe_free(v)) {\n+\t\tpr_debug(\"RP Stopped\\n\");\n+\t\treturn 0;\n+\t} else\n+\t\treturn -1;\n+}\n+EXPORT_SYMBOL(vpe1_sw_stop);\n+#endif\n--- a/arch/mips/kernel/vpe.c\n+++ b/arch/mips/kernel/vpe.c\n@@ -49,6 +49,41 @@ struct vpe_control vpecontrol = {\n \t.tc_list\t= LIST_HEAD_INIT(vpecontrol.tc_list)\n };\n \n+#ifdef CONFIG_IFX_VPE_EXT\n+unsigned int vpe1_load_addr;\n+\n+static int __init load_address(char *str)\n+{\n+\tget_option(&str, &vpe1_load_addr);\n+\treturn 1;\n+}\n+__setup(\"vpe1_load_addr=\", load_address);\n+\n+static unsigned int vpe1_mem;\n+static int __init vpe1mem(char *str)\n+{\n+\tvpe1_mem = memparse(str, &str);\n+\treturn 1;\n+}\n+__setup(\"vpe1_mem=\", vpe1mem);\n+\n+uint32_t vpe1_get_load_addr(uint32_t flags)\n+{\n+\treturn vpe1_load_addr;\n+}\n+EXPORT_SYMBOL(vpe1_get_load_addr);\n+\n+uint32_t vpe1_get_max_mem(uint32_t flags)\n+{\n+\tif (!vpe1_mem)\n+\t\treturn P_SIZE;\n+\telse\n+\t\treturn vpe1_mem;\n+}\n+EXPORT_SYMBOL(vpe1_get_max_mem);\n+\n+#endif\n+\n /* get the vpe associated with this minor */\n struct vpe *get_vpe(int minor)\n {\n--- a/arch/mips/lantiq/prom.c\n+++ b/arch/mips/lantiq/prom.c\n@@ -34,10 +34,14 @@ unsigned long physical_memsize = 0L;\n  */\n static struct ltq_soc_info soc_info;\n \n+/* for Multithreading (APRP), vpe.c will use it */\n+unsigned long cp0_memsize;\n+\n const char *get_system_type(void)\n {\n \treturn soc_info.sys_type;\n }\n+EXPORT_SYMBOL(ltq_soc_type);\n \n int ltq_soc_type(void)\n {\n--- a/arch/mips/include/asm/mipsmtregs.h\n+++ b/arch/mips/include/asm/mipsmtregs.h\n@@ -32,6 +32,9 @@\n #define read_c0_vpeconf1()\t\t__read_32bit_c0_register($1, 3)\n #define write_c0_vpeconf1(val)\t\t__write_32bit_c0_register($1, 3, val)\n \n+#define read_c0_vpeopt()\t\t__read_32bit_c0_register($1, 7)\n+#define write_c0_vpeopt(val)\t\t__write_32bit_c0_register($1, 7, val)\n+\n #define read_c0_tcstatus()\t\t__read_32bit_c0_register($2, 1)\n #define write_c0_tcstatus(val)\t\t__write_32bit_c0_register($2, 1, val)\n \n@@ -378,6 +381,8 @@ do {\t\t\t\t\t\t\t\t\t\\\n #define write_vpe_c0_vpeconf0(val)\tmttc0(1, 2, val)\n #define read_vpe_c0_vpeconf1()\t\tmftc0(1, 3)\n #define write_vpe_c0_vpeconf1(val)\tmttc0(1, 3, val)\n+#define read_vpe_c0_vpeopt()\t\tmftc0(1, 7)\n+#define write_vpe_c0_vpeopt(val)\tmttc0(1, 7, val)\n #define read_vpe_c0_count()\t\tmftc0(9, 0)\n #define write_vpe_c0_count(val)\t\tmttc0(9, 0, val)\n #define read_vpe_c0_status()\t\tmftc0(12, 0)\n"
  },
  {
    "path": "target/linux/lantiq/patches-5.10/0154-lantiq-pci-bar11mask-fix.patch",
    "content": "--- a/arch/mips/pci/pci-lantiq.c\n+++ b/arch/mips/pci/pci-lantiq.c\n@@ -59,6 +59,8 @@\n #define ltq_pci_cfg_w32(x, y)\tltq_w32((x), ltq_pci_mapped_cfg + (y))\n #define ltq_pci_cfg_r32(x)\tltq_r32(ltq_pci_mapped_cfg + (x))\n \n+extern u32 max_low_pfn;\n+\n __iomem void *ltq_pci_mapped_cfg;\n static __iomem void *ltq_pci_membase;\n \n@@ -84,8 +86,8 @@ static inline u32 ltq_calc_bar11mask(voi\n \tu32 mem, bar11mask;\n \n \t/* BAR11MASK value depends on available memory on system. */\n-\tmem = get_num_physpages() * PAGE_SIZE;\n-\tbar11mask = (0x0ffffff0 & ~((1 << (fls(mem) - 1)) - 1)) | 8;\n+\tmem = max_low_pfn << PAGE_SHIFT;\n+\tbar11mask = ((-roundup_pow_of_two(mem)) & 0x0F000000) | 8;\n \n \treturn bar11mask;\n }\n"
  },
  {
    "path": "target/linux/lantiq/patches-5.10/0155-lantiq-VPE-nosmp.patch",
    "content": "--- a/arch/mips/kernel/vpe-mt.c\n+++ b/arch/mips/kernel/vpe-mt.c\n@@ -132,7 +132,10 @@ int vpe_run(struct vpe *v)\n \t * kernels need to turn it on, even if that wasn't the pre-dvpe() state.\n \t */\n #ifdef CONFIG_SMP\n-\tevpe(vpeflags);\n+\tif (!setup_max_cpus) /* nosmp is set */\n+\t\tevpe(EVPE_ENABLE);\n+\telse\n+\t\tevpe(vpeflags);\n #else\n \tevpe(EVPE_ENABLE);\n #endif\n"
  },
  {
    "path": "target/linux/lantiq/patches-5.10/0160-owrt-lantiq-multiple-flash.patch",
    "content": "--- a/drivers/mtd/maps/lantiq-flash.c\n+++ b/drivers/mtd/maps/lantiq-flash.c\n@@ -17,6 +17,7 @@\n #include <linux/mtd/cfi.h>\n #include <linux/platform_device.h>\n #include <linux/mtd/physmap.h>\n+#include <linux/mtd/concat.h>\n #include <linux/of.h>\n \n #include <lantiq_soc.h>\n@@ -36,13 +37,16 @@ enum {\n \tLTQ_NOR_NORMAL\n };\n \n+#define MAX_RESOURCES\t\t4\n+\n struct ltq_mtd {\n-\tstruct resource *res;\n-\tstruct mtd_info *mtd;\n-\tstruct map_info *map;\n+\tstruct mtd_info *mtd[MAX_RESOURCES];\n+\tstruct mtd_info\t*cmtd;\n+\tstruct map_info map[MAX_RESOURCES];\n };\n \n static const char ltq_map_name[] = \"ltq_nor\";\n+static const char * const ltq_probe_types[] = { \"cmdlinepart\", \"ofpart\", NULL };\n \n static map_word\n ltq_read16(struct map_info *map, unsigned long adr)\n@@ -106,11 +110,43 @@ ltq_copy_to(struct map_info *map, unsign\n }\n \n static int\n+ltq_mtd_remove(struct platform_device *pdev)\n+{\n+\tstruct ltq_mtd *ltq_mtd = platform_get_drvdata(pdev);\n+\tint i;\n+\n+\tif (ltq_mtd == NULL)\n+\t\treturn 0;\n+\n+\tif (ltq_mtd->cmtd) {\n+\t\tmtd_device_unregister(ltq_mtd->cmtd);\n+\t\tif (ltq_mtd->cmtd != ltq_mtd->mtd[0])\n+\t\t\tmtd_concat_destroy(ltq_mtd->cmtd);\n+\t}\n+\n+\tfor (i = 0; i < MAX_RESOURCES; i++) {\n+\t\tif (ltq_mtd->mtd[i] != NULL)\n+\t\t\tmap_destroy(ltq_mtd->mtd[i]);\n+\t}\n+\n+\tkfree(ltq_mtd);\n+\n+\treturn 0;\n+}\n+\n+static int\n ltq_mtd_probe(struct platform_device *pdev)\n {\n \tstruct ltq_mtd *ltq_mtd;\n \tstruct cfi_private *cfi;\n-\tint err;\n+\tint err = 0;\n+\tint i;\n+\tint devices_found = 0;\n+\n+\tstatic const char *rom_probe_types[] = {\n+\t\t\"cfi_probe\", \"jedec_probe\", NULL\n+\t};\n+\tconst char **type;\n \n \tltq_mtd = devm_kzalloc(&pdev->dev, sizeof(struct ltq_mtd), GFP_KERNEL);\n \tif (!ltq_mtd)\n@@ -118,75 +154,89 @@ ltq_mtd_probe(struct platform_device *pd\n \n \tplatform_set_drvdata(pdev, ltq_mtd);\n \n-\tltq_mtd->res = platform_get_resource(pdev, IORESOURCE_MEM, 0);\n-\tif (!ltq_mtd->res) {\n-\t\tdev_err(&pdev->dev, \"failed to get memory resource\\n\");\n-\t\treturn -ENOENT;\n+\tfor (i = 0; i < pdev->num_resources; i++) {\n+\t\tprintk(KERN_NOTICE \"lantiq nor flash device: %.8llx at %.8llx\\n\",\n+\t\t       (unsigned long long)resource_size(&pdev->resource[i]),\n+\t\t       (unsigned long long)pdev->resource[i].start);\n+\t\n+\t\tif (!devm_request_mem_region(&pdev->dev,\n+\t\t\tpdev->resource[i].start,\n+\t\t\tresource_size(&pdev->resource[i]),\n+\t\t\tdev_name(&pdev->dev))) {\n+\t\t\tdev_err(&pdev->dev, \"Could not reserve memory region\\n\");\n+\t\t\treturn -ENOMEM;\n+\t\t}\n+\n+\t\tltq_mtd->map[i].name = ltq_map_name;\n+\t\tltq_mtd->map[i].bankwidth = 2;\n+\t\tltq_mtd->map[i].read = ltq_read16;\n+\t\tltq_mtd->map[i].write = ltq_write16;\n+\t\tltq_mtd->map[i].copy_from = ltq_copy_from;\n+\t\tltq_mtd->map[i].copy_to = ltq_copy_to;\n+\n+\t\tif (of_find_property(pdev->dev.of_node, \"lantiq,noxip\", NULL))\n+\t\t\tltq_mtd->map[i].phys = NO_XIP;\n+\t\telse\n+\t\t\tltq_mtd->map[i].phys = pdev->resource[i].start;\n+\t\tltq_mtd->map[i].size = resource_size(&pdev->resource[i]);\n+\t\tltq_mtd->map[i].virt = devm_ioremap(&pdev->dev, pdev->resource[i].start,\n+\t\t\t\t\t\t ltq_mtd->map[i].size);\n+\t\tif (IS_ERR(ltq_mtd->map[i].virt))\n+\t\t\treturn PTR_ERR(ltq_mtd->map[i].virt);\n+\n+\t\tif (ltq_mtd->map[i].virt == NULL) {\n+\t\t\tdev_err(&pdev->dev, \"Failed to ioremap flash region\\n\");\n+\t\t\terr = PTR_ERR(ltq_mtd->map[i].virt);\n+\t\t\tgoto err_out;\n+\t\t}\n+\n+\t\tltq_mtd->map[i].map_priv_1 = LTQ_NOR_PROBING;\n+\t\tfor (type = rom_probe_types; !ltq_mtd->mtd[i] && *type; type++)\n+\t\t\tltq_mtd->mtd[i] = do_map_probe(*type, &ltq_mtd->map[i]);\n+\t\tltq_mtd->map[i].map_priv_1 = LTQ_NOR_NORMAL;\n+\n+\t\tif (!ltq_mtd->mtd[i]) {\n+\t\t\tdev_err(&pdev->dev, \"probing failed\\n\");\n+\t\t\treturn -ENXIO;\n+\t\t} else {\n+\t\t\tdevices_found++;\n+\t\t}\n+\n+\t\tltq_mtd->mtd[i]->owner = THIS_MODULE;\n+\t\tltq_mtd->mtd[i]->dev.parent = &pdev->dev;\n+\n+\t\tcfi = ltq_mtd->map[i].fldrv_priv;\n+\t\tcfi->addr_unlock1 ^= 1;\n+\t\tcfi->addr_unlock2 ^= 1;\n \t}\n \n-\tltq_mtd->map = devm_kzalloc(&pdev->dev, sizeof(struct map_info),\n-\t\t\t\t    GFP_KERNEL);\n-\tif (!ltq_mtd->map)\n-\t\treturn -ENOMEM;\n-\n-\tif (of_find_property(pdev->dev.of_node, \"lantiq,noxip\", NULL))\n-\t\tltq_mtd->map->phys = NO_XIP;\n-\telse\n-\t\tltq_mtd->map->phys = ltq_mtd->res->start;\n-\tltq_mtd->res->start;\n-\tltq_mtd->map->size = resource_size(ltq_mtd->res);\n-\tltq_mtd->map->virt = devm_ioremap_resource(&pdev->dev, ltq_mtd->res);\n-\tif (IS_ERR(ltq_mtd->map->virt))\n-\t\treturn PTR_ERR(ltq_mtd->map->virt);\n-\n-\tltq_mtd->map->name = ltq_map_name;\n-\tltq_mtd->map->bankwidth = 2;\n-\tltq_mtd->map->read = ltq_read16;\n-\tltq_mtd->map->write = ltq_write16;\n-\tltq_mtd->map->copy_from = ltq_copy_from;\n-\tltq_mtd->map->copy_to = ltq_copy_to;\n-\n-\tltq_mtd->map->map_priv_1 = LTQ_NOR_PROBING;\n-\tltq_mtd->mtd = do_map_probe(\"cfi_probe\", ltq_mtd->map);\n-\tltq_mtd->map->map_priv_1 = LTQ_NOR_NORMAL;\n-\n-\tif (!ltq_mtd->mtd) {\n-\t\tdev_err(&pdev->dev, \"probing failed\\n\");\n-\t\treturn -ENXIO;\n+\tif (devices_found == 1) {\n+\t\tltq_mtd->cmtd = ltq_mtd->mtd[0];\n+\t} else if (devices_found > 1) {\n+\t\t/*\n+\t\t * We detected multiple devices. Concatenate them together.\n+\t\t */\n+\t\tltq_mtd->cmtd = mtd_concat_create(ltq_mtd->mtd, devices_found, dev_name(&pdev->dev));\n+\t\tif (ltq_mtd->cmtd == NULL)\n+\t\t\terr = -ENXIO;\n \t}\n \n-\tltq_mtd->mtd->dev.parent = &pdev->dev;\n-\tmtd_set_of_node(ltq_mtd->mtd, pdev->dev.of_node);\n-\n-\tcfi = ltq_mtd->map->fldrv_priv;\n-\tcfi->addr_unlock1 ^= 1;\n-\tcfi->addr_unlock2 ^= 1;\n+\tltq_mtd->cmtd->dev.parent = &pdev->dev;\n+\tmtd_set_of_node(ltq_mtd->cmtd, pdev->dev.of_node);\n \n-\terr = mtd_device_register(ltq_mtd->mtd, NULL, 0);\n+\terr = mtd_device_register(ltq_mtd->cmtd, NULL, 0);\n \tif (err) {\n \t\tdev_err(&pdev->dev, \"failed to add partitions\\n\");\n-\t\tgoto err_destroy;\n+\t\tgoto err_out;\n \t}\n \n \treturn 0;\n \n-err_destroy:\n-\tmap_destroy(ltq_mtd->mtd);\n+err_out:\n+\tltq_mtd_remove(pdev);\n \treturn err;\n }\n \n-static int\n-ltq_mtd_remove(struct platform_device *pdev)\n-{\n-\tstruct ltq_mtd *ltq_mtd = platform_get_drvdata(pdev);\n-\n-\tif (ltq_mtd && ltq_mtd->mtd) {\n-\t\tmtd_device_unregister(ltq_mtd->mtd);\n-\t\tmap_destroy(ltq_mtd->mtd);\n-\t}\n-\treturn 0;\n-}\n-\n static const struct of_device_id ltq_mtd_match[] = {\n \t{ .compatible = \"lantiq,nor\" },\n \t{},\n"
  },
  {
    "path": "target/linux/lantiq/patches-5.10/0300-MTD-cfi-cmdset-0001-disable-buffered-writes.patch",
    "content": "--- a/drivers/mtd/chips/cfi_cmdset_0001.c\n+++ b/drivers/mtd/chips/cfi_cmdset_0001.c\n@@ -39,7 +39,7 @@\n /* #define CMDSET0001_DISABLE_WRITE_SUSPEND */\n \n // debugging, turns off buffer write mode if set to 1\n-#define FORCE_WORD_WRITE 0\n+#define FORCE_WORD_WRITE 1\n \n /* Intel chips */\n #define I82802AB\t0x00ad\n"
  },
  {
    "path": "target/linux/lantiq/patches-5.10/0301-xrx200-add-gphy-clk-src-device-tree-binding.patch",
    "content": "--- a/arch/mips/lantiq/xway/sysctrl.c\n+++ b/arch/mips/lantiq/xway/sysctrl.c\n@@ -426,6 +426,20 @@ static void clkdev_add_clkout(void)\n \t}\n }\n \n+static void set_phy_clock_source(struct device_node *np_cgu)\n+{\n+\tu32 phy_clk_src, ifcc;\n+\n+\tif (!np_cgu)\n+\t\treturn;\n+\n+\tif (of_property_read_u32(np_cgu, \"lantiq,phy-clk-src\", &phy_clk_src))\n+\t\treturn;\n+\n+\tifcc = ltq_cgu_r32(ifccr) & ~(0x1c);\n+\tltq_cgu_w32(ifcc | (phy_clk_src << 2), ifccr);\n+}\n+\n /* bring up all register ranges that we need for basic system control */\n void __init ltq_soc_init(void)\n {\n@@ -591,4 +605,6 @@ void __init ltq_soc_init(void)\n \t\tclkdev_add_pmu(\"1e100400.serial\", NULL, 1, 0, PMU_ASC0);\n \t}\n \tusb_set_clock();\n+\n+\tset_phy_clock_source(np_cgu);\n }\n"
  },
  {
    "path": "target/linux/lantiq/patches-5.10/0310-v5.16-MIPS-lantiq-dma-make-the-burst-length-configurable-b.patch",
    "content": "From 49293bbc50cb7d44223eb49e0f7cb38e7dac2361 Mon Sep 17 00:00:00 2001\nFrom: Aleksander Jan Bajkowski <olek2@wp.pl>\nDate: Tue, 14 Sep 2021 23:21:01 +0200\nSubject: [PATCH 4/5] MIPS: lantiq: dma: make the burst length configurable by\n the drivers\n\nMake the burst length configurable by the drivers.\n\nSigned-off-by: Aleksander Jan Bajkowski <olek2@wp.pl>\nAcked-by: Hauke Mehrtens <hauke@hauke-m.de>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n .../include/asm/mach-lantiq/xway/xway_dma.h   |  2 +-\n arch/mips/lantiq/xway/dma.c                   | 38 ++++++++++++++++---\n 2 files changed, 34 insertions(+), 6 deletions(-)\n\n--- a/arch/mips/include/asm/mach-lantiq/xway/xway_dma.h\n+++ b/arch/mips/include/asm/mach-lantiq/xway/xway_dma.h\n@@ -45,6 +45,6 @@ extern void ltq_dma_close(struct ltq_dma\n extern void ltq_dma_alloc_tx(struct ltq_dma_channel *ch);\n extern void ltq_dma_alloc_rx(struct ltq_dma_channel *ch);\n extern void ltq_dma_free(struct ltq_dma_channel *ch);\n-extern void ltq_dma_init_port(int p);\n+extern void ltq_dma_init_port(int p, int tx_burst, int rx_burst);\n \n #endif\n--- a/arch/mips/lantiq/xway/dma.c\n+++ b/arch/mips/lantiq/xway/dma.c\n@@ -181,7 +181,7 @@ ltq_dma_free(struct ltq_dma_channel *ch)\n EXPORT_SYMBOL_GPL(ltq_dma_free);\n \n void\n-ltq_dma_init_port(int p)\n+ltq_dma_init_port(int p, int tx_burst, int rx_burst)\n {\n \tltq_dma_w32(p, LTQ_DMA_PS);\n \tswitch (p) {\n@@ -190,16 +190,44 @@ ltq_dma_init_port(int p)\n \t\t * Tell the DMA engine to swap the endianness of data frames and\n \t\t * drop packets if the channel arbitration fails.\n \t\t */\n-\t\tltq_dma_w32_mask(0, DMA_ETOP_ENDIANNESS | DMA_PDEN,\n+\t\tltq_dma_w32_mask(0, (DMA_ETOP_ENDIANNESS | DMA_PDEN),\n \t\t\tLTQ_DMA_PCTRL);\n \t\tbreak;\n \n-\tcase DMA_PORT_DEU:\n-\t\tltq_dma_w32((DMA_PCTRL_2W_BURST << DMA_TX_BURST_SHIFT) |\n-\t\t\t(DMA_PCTRL_2W_BURST << DMA_RX_BURST_SHIFT),\n+\tdefault:\n+\t\tbreak;\n+\t}\n+\n+\tswitch (rx_burst) {\n+\tcase 8:\n+\t\tltq_dma_w32_mask(0x0c, (DMA_PCTRL_8W_BURST << DMA_RX_BURST_SHIFT),\n \t\t\tLTQ_DMA_PCTRL);\n \t\tbreak;\n+\tcase 4:\n+\t\tltq_dma_w32_mask(0x0c, (DMA_PCTRL_4W_BURST << DMA_RX_BURST_SHIFT),\n+\t\t\tLTQ_DMA_PCTRL);\n+\t\tbreak;\n+\tcase 2:\n+\t\tltq_dma_w32_mask(0x0c, (DMA_PCTRL_2W_BURST << DMA_RX_BURST_SHIFT),\n+\t\t\tLTQ_DMA_PCTRL);\n+\t\tbreak;\n+\tdefault:\n+\t\tbreak;\n+\t}\n \n+\tswitch (tx_burst) {\n+\tcase 8:\n+\t\tltq_dma_w32_mask(0x30, (DMA_PCTRL_8W_BURST << DMA_TX_BURST_SHIFT),\n+\t\t\tLTQ_DMA_PCTRL);\n+\t\tbreak;\n+\tcase 4:\n+\t\tltq_dma_w32_mask(0x30, (DMA_PCTRL_4W_BURST << DMA_TX_BURST_SHIFT),\n+\t\t\tLTQ_DMA_PCTRL);\n+\t\tbreak;\n+\tcase 2:\n+\t\tltq_dma_w32_mask(0x30, (DMA_PCTRL_2W_BURST << DMA_TX_BURST_SHIFT),\n+\t\t\tLTQ_DMA_PCTRL);\n+\t\tbreak;\n \tdefault:\n \t\tbreak;\n \t}\n"
  },
  {
    "path": "target/linux/lantiq/patches-5.10/0701-NET-lantiq-etop-of-mido.patch",
    "content": "--- a/drivers/net/ethernet/lantiq_etop.c\n+++ b/drivers/net/ethernet/lantiq_etop.c\n@@ -30,6 +30,7 @@\n #include <linux/of_net.h>\n #include <linux/of_irq.h>\n #include <linux/of_platform.h>\n+#include <linux/of_mdio.h>\n \n #include <asm/checksum.h>\n \n@@ -553,7 +554,8 @@ static int\n ltq_etop_mdio_init(struct net_device *dev)\n {\n \tstruct ltq_etop_priv *priv = netdev_priv(dev);\n-\tint err;\n+\tstruct device_node *mdio_np = NULL;\n+\tint err, ret;\n \n \tpriv->mii_bus = mdiobus_alloc();\n \tif (!priv->mii_bus) {\n@@ -573,7 +575,15 @@ ltq_etop_mdio_init(struct net_device *de\n \tpriv->mii_bus->name = \"ltq_mii\";\n \tsnprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, \"%s-%x\",\n \t\tpriv->pdev->name, priv->pdev->id);\n-\tif (mdiobus_register(priv->mii_bus)) {\n+\n+\tmdio_np = of_get_child_by_name(priv->pdev->dev.of_node, \"mdio-bus\");\n+\n+\tif (mdio_np)\n+\t\tret = of_mdiobus_register(priv->mii_bus, mdio_np);\n+\telse\n+\t\tret = mdiobus_register(priv->mii_bus);\n+\n+\tif (ret) {\n \t\terr = -ENXIO;\n \t\tgoto err_out_free_mdiobus;\n \t}\n"
  },
  {
    "path": "target/linux/lantiq/patches-5.10/0702-v5.16-net-lantiq-add-support-for-jumbo-frames.patch",
    "content": "From 998ac358019e491217e752bc6dcbb3afb2a6fa3e Mon Sep 17 00:00:00 2001\nFrom: Aleksander Jan Bajkowski <olek2@wp.pl>\nDate: Sun, 19 Sep 2021 20:24:28 +0200\nSubject: [PATCH] net: lantiq: add support for jumbo frames\n\nAdd support for jumbo frames. Full support for jumbo frames requires\nchanges in the DSA switch driver (lantiq_gswip.c).\n\nTested on BT Hone Hub 5A.\n\nSigned-off-by: Aleksander Jan Bajkowski <olek2@wp.pl>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/ethernet/lantiq_xrx200.c | 64 +++++++++++++++++++++++++---\n 1 file changed, 57 insertions(+), 7 deletions(-)\n\n--- a/drivers/net/ethernet/lantiq_xrx200.c\n+++ b/drivers/net/ethernet/lantiq_xrx200.c\n@@ -14,13 +14,15 @@\n #include <linux/clk.h>\n #include <linux/delay.h>\n \n+#include <linux/if_vlan.h>\n+\n #include <linux/of_net.h>\n #include <linux/of_platform.h>\n \n #include <xway_dma.h>\n \n /* DMA */\n-#define XRX200_DMA_DATA_LEN\t0x600\n+#define XRX200_DMA_DATA_LEN\t(SZ_64K - 1)\n #define XRX200_DMA_RX\t\t0\n #define XRX200_DMA_TX\t\t1\n \n@@ -106,7 +108,8 @@ static void xrx200_flush_dma(struct xrx2\n \t\t\tbreak;\n \n \t\tdesc->ctl = LTQ_DMA_OWN | LTQ_DMA_RX_OFFSET(NET_IP_ALIGN) |\n-\t\t\t    XRX200_DMA_DATA_LEN;\n+\t\t\t    (ch->priv->net_dev->mtu + VLAN_ETH_HLEN +\n+\t\t\t     ETH_FCS_LEN);\n \t\tch->dma.desc++;\n \t\tch->dma.desc %= LTQ_DESC_NUM;\n \t}\n@@ -154,19 +157,20 @@ static int xrx200_close(struct net_devic\n \n static int xrx200_alloc_skb(struct xrx200_chan *ch)\n {\n+\tint len = ch->priv->net_dev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;\n \tstruct sk_buff *skb = ch->skb[ch->dma.desc];\n \tdma_addr_t mapping;\n \tint ret = 0;\n \n \tch->skb[ch->dma.desc] = netdev_alloc_skb_ip_align(ch->priv->net_dev,\n-\t\t\t\t\t\t\t  XRX200_DMA_DATA_LEN);\n+\t\t\t\t\t\t\t  len);\n \tif (!ch->skb[ch->dma.desc]) {\n \t\tret = -ENOMEM;\n \t\tgoto skip;\n \t}\n \n \tmapping = dma_map_single(ch->priv->dev, ch->skb[ch->dma.desc]->data,\n-\t\t\t\t XRX200_DMA_DATA_LEN, DMA_FROM_DEVICE);\n+\t\t\t\t len, DMA_FROM_DEVICE);\n \tif (unlikely(dma_mapping_error(ch->priv->dev, mapping))) {\n \t\tdev_kfree_skb_any(ch->skb[ch->dma.desc]);\n \t\tch->skb[ch->dma.desc] = skb;\n@@ -179,8 +183,7 @@ static int xrx200_alloc_skb(struct xrx20\n \twmb();\n skip:\n \tch->dma.desc_base[ch->dma.desc].ctl =\n-\t\tLTQ_DMA_OWN | LTQ_DMA_RX_OFFSET(NET_IP_ALIGN) |\n-\t\tXRX200_DMA_DATA_LEN;\n+\t\tLTQ_DMA_OWN | LTQ_DMA_RX_OFFSET(NET_IP_ALIGN) | len;\n \n \treturn ret;\n }\n@@ -340,10 +343,57 @@ err_drop:\n \treturn NETDEV_TX_OK;\n }\n \n+static int\n+xrx200_change_mtu(struct net_device *net_dev, int new_mtu)\n+{\n+\tstruct xrx200_priv *priv = netdev_priv(net_dev);\n+\tstruct xrx200_chan *ch_rx = &priv->chan_rx;\n+\tint old_mtu = net_dev->mtu;\n+\tbool running = false;\n+\tstruct sk_buff *skb;\n+\tint curr_desc;\n+\tint ret = 0;\n+\n+\tnet_dev->mtu = new_mtu;\n+\n+\tif (new_mtu <= old_mtu)\n+\t\treturn ret;\n+\n+\trunning = netif_running(net_dev);\n+\tif (running) {\n+\t\tnapi_disable(&ch_rx->napi);\n+\t\tltq_dma_close(&ch_rx->dma);\n+\t}\n+\n+\txrx200_poll_rx(&ch_rx->napi, LTQ_DESC_NUM);\n+\tcurr_desc = ch_rx->dma.desc;\n+\n+\tfor (ch_rx->dma.desc = 0; ch_rx->dma.desc < LTQ_DESC_NUM;\n+\t     ch_rx->dma.desc++) {\n+\t\tskb = ch_rx->skb[ch_rx->dma.desc];\n+\t\tret = xrx200_alloc_skb(ch_rx);\n+\t\tif (ret) {\n+\t\t\tnet_dev->mtu = old_mtu;\n+\t\t\tbreak;\n+\t\t}\n+\t\tdev_kfree_skb_any(skb);\n+\t}\n+\n+\tch_rx->dma.desc = curr_desc;\n+\tif (running) {\n+\t\tnapi_enable(&ch_rx->napi);\n+\t\tltq_dma_open(&ch_rx->dma);\n+\t\tltq_dma_enable_irq(&ch_rx->dma);\n+\t}\n+\n+\treturn ret;\n+}\n+\n static const struct net_device_ops xrx200_netdev_ops = {\n \t.ndo_open\t\t= xrx200_open,\n \t.ndo_stop\t\t= xrx200_close,\n \t.ndo_start_xmit\t\t= xrx200_start_xmit,\n+\t.ndo_change_mtu\t\t= xrx200_change_mtu,\n \t.ndo_set_mac_address\t= eth_mac_addr,\n \t.ndo_validate_addr\t= eth_validate_addr,\n };\n@@ -454,7 +504,7 @@ static int xrx200_probe(struct platform_\n \tnet_dev->netdev_ops = &xrx200_netdev_ops;\n \tSET_NETDEV_DEV(net_dev, dev);\n \tnet_dev->min_mtu = ETH_ZLEN;\n-\tnet_dev->max_mtu = XRX200_DMA_DATA_LEN;\n+\tnet_dev->max_mtu = XRX200_DMA_DATA_LEN - VLAN_ETH_HLEN - ETH_FCS_LEN;\n \n \t/* load the memory ranges */\n \tres = platform_get_resource(pdev, IORESOURCE_MEM, 0);\n"
  },
  {
    "path": "target/linux/lantiq/patches-5.10/0703-v5.16-net-lantiq_xrx200-increase-buffer-reservation.patch",
    "content": "From 1488fc204568f707fe2a42a913788c00a95af30e Mon Sep 17 00:00:00 2001\nFrom: Aleksander Jan Bajkowski <olek2@wp.pl>\nDate: Fri, 17 Dec 2021 01:07:40 +0100\nSubject: [PATCH] net: lantiq_xrx200: increase buffer reservation\n\nIf the user sets a lower mtu on the CPU port than on the switch,\nthen DMA inserts a few more bytes into the buffer than expected.\nIn the worst case, it may exceed the size of the buffer. The\nexperiments showed that the buffer should be a multiple of the\nburst length value. This patch rounds the length of the rx buffer\nupwards and fixes this bug. The reservation of FCS space in the\nbuffer has been removed as PMAC strips the FCS.\n\nFixes: 998ac358019e (\"net: lantiq: add support for jumbo frames\")\nReported-by: Thomas Nixon <tom@tomn.co.uk>\nSigned-off-by: Aleksander Jan Bajkowski <olek2@wp.pl>\nSigned-off-by: Jakub Kicinski <kuba@kernel.org>\n---\n drivers/net/ethernet/lantiq_xrx200.c | 34 ++++++++++++++++++++--------\n 1 file changed, 24 insertions(+), 10 deletions(-)\n\n--- a/drivers/net/ethernet/lantiq_xrx200.c\n+++ b/drivers/net/ethernet/lantiq_xrx200.c\n@@ -70,6 +70,8 @@ struct xrx200_priv {\n \tstruct xrx200_chan chan_tx;\n \tstruct xrx200_chan chan_rx;\n \n+\tu16 rx_buf_size;\n+\n \tstruct net_device *net_dev;\n \tstruct device *dev;\n \n@@ -96,6 +98,16 @@ static void xrx200_pmac_mask(struct xrx2\n \txrx200_pmac_w32(priv, val, offset);\n }\n \n+static int xrx200_max_frame_len(int mtu)\n+{\n+\treturn VLAN_ETH_HLEN + mtu;\n+}\n+\n+static int xrx200_buffer_size(int mtu)\n+{\n+\treturn round_up(xrx200_max_frame_len(mtu), 4 * XRX200_DMA_BURST_LEN);\n+}\n+\n /* drop all the packets from the DMA ring */\n static void xrx200_flush_dma(struct xrx200_chan *ch)\n {\n@@ -108,8 +120,7 @@ static void xrx200_flush_dma(struct xrx2\n \t\t\tbreak;\n \n \t\tdesc->ctl = LTQ_DMA_OWN | LTQ_DMA_RX_OFFSET(NET_IP_ALIGN) |\n-\t\t\t    (ch->priv->net_dev->mtu + VLAN_ETH_HLEN +\n-\t\t\t     ETH_FCS_LEN);\n+\t\t\t    ch->priv->rx_buf_size;\n \t\tch->dma.desc++;\n \t\tch->dma.desc %= LTQ_DESC_NUM;\n \t}\n@@ -157,21 +168,21 @@ static int xrx200_close(struct net_devic\n \n static int xrx200_alloc_skb(struct xrx200_chan *ch)\n {\n-\tint len = ch->priv->net_dev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;\n \tstruct sk_buff *skb = ch->skb[ch->dma.desc];\n+\tstruct xrx200_priv *priv = ch->priv;\n \tdma_addr_t mapping;\n \tint ret = 0;\n \n-\tch->skb[ch->dma.desc] = netdev_alloc_skb_ip_align(ch->priv->net_dev,\n-\t\t\t\t\t\t\t  len);\n+\tch->skb[ch->dma.desc] = netdev_alloc_skb_ip_align(priv->net_dev,\n+\t\t\t\t\t\t\t  priv->rx_buf_size);\n \tif (!ch->skb[ch->dma.desc]) {\n \t\tret = -ENOMEM;\n \t\tgoto skip;\n \t}\n \n-\tmapping = dma_map_single(ch->priv->dev, ch->skb[ch->dma.desc]->data,\n-\t\t\t\t len, DMA_FROM_DEVICE);\n-\tif (unlikely(dma_mapping_error(ch->priv->dev, mapping))) {\n+\tmapping = dma_map_single(priv->dev, ch->skb[ch->dma.desc]->data,\n+\t\t\t\t priv->rx_buf_size, DMA_FROM_DEVICE);\n+\tif (unlikely(dma_mapping_error(priv->dev, mapping))) {\n \t\tdev_kfree_skb_any(ch->skb[ch->dma.desc]);\n \t\tch->skb[ch->dma.desc] = skb;\n \t\tret = -ENOMEM;\n@@ -183,7 +194,7 @@ static int xrx200_alloc_skb(struct xrx20\n \twmb();\n skip:\n \tch->dma.desc_base[ch->dma.desc].ctl =\n-\t\tLTQ_DMA_OWN | LTQ_DMA_RX_OFFSET(NET_IP_ALIGN) | len;\n+\t\tLTQ_DMA_OWN | LTQ_DMA_RX_OFFSET(NET_IP_ALIGN) | priv->rx_buf_size;\n \n \treturn ret;\n }\n@@ -355,6 +366,7 @@ xrx200_change_mtu(struct net_device *net\n \tint ret = 0;\n \n \tnet_dev->mtu = new_mtu;\n+\tpriv->rx_buf_size = xrx200_buffer_size(new_mtu);\n \n \tif (new_mtu <= old_mtu)\n \t\treturn ret;\n@@ -374,6 +386,7 @@ xrx200_change_mtu(struct net_device *net\n \t\tret = xrx200_alloc_skb(ch_rx);\n \t\tif (ret) {\n \t\t\tnet_dev->mtu = old_mtu;\n+\t\t\tpriv->rx_buf_size = xrx200_buffer_size(old_mtu);\n \t\t\tbreak;\n \t\t}\n \t\tdev_kfree_skb_any(skb);\n@@ -504,7 +517,8 @@ static int xrx200_probe(struct platform_\n \tnet_dev->netdev_ops = &xrx200_netdev_ops;\n \tSET_NETDEV_DEV(net_dev, dev);\n \tnet_dev->min_mtu = ETH_ZLEN;\n-\tnet_dev->max_mtu = XRX200_DMA_DATA_LEN - VLAN_ETH_HLEN - ETH_FCS_LEN;\n+\tnet_dev->max_mtu = XRX200_DMA_DATA_LEN - xrx200_max_frame_len(0);\n+\tpriv->rx_buf_size = xrx200_buffer_size(ETH_DATA_LEN);\n \n \t/* load the memory ranges */\n \tres = platform_get_resource(pdev, IORESOURCE_MEM, 0);\n"
  },
  {
    "path": "target/linux/lantiq/patches-5.10/0704-v5.17-net-lantiq_xrx200-add-ingress-SG-DMA-support.patch",
    "content": "From c3e6b2c35b34214c58c1e90d65dab5f5393608e7 Mon Sep 17 00:00:00 2001\nFrom: Aleksander Jan Bajkowski <olek2@wp.pl>\nDate: Mon, 3 Jan 2022 20:43:16 +0100\nSubject: [PATCH] net: lantiq_xrx200: add ingress SG DMA support\n\nThis patch adds support for scatter gather DMA. DMA in PMAC splits\nthe packet into several buffers when the MTU on the CPU port is\nless than the MTU of the switch. The first buffer starts at an\noffset of NET_IP_ALIGN. In subsequent buffers, dma ignores the\noffset. Thanks to this patch, the user can still connect to the\ndevice in such a situation. For normal configurations, the patch\nhas no effect on performance.\n\nSigned-off-by: Aleksander Jan Bajkowski <olek2@wp.pl>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/ethernet/lantiq_xrx200.c | 47 +++++++++++++++++++++++-----\n 1 file changed, 40 insertions(+), 7 deletions(-)\n\n--- a/drivers/net/ethernet/lantiq_xrx200.c\n+++ b/drivers/net/ethernet/lantiq_xrx200.c\n@@ -26,6 +26,9 @@\n #define XRX200_DMA_RX\t\t0\n #define XRX200_DMA_TX\t\t1\n \n+#define XRX200_DMA_PACKET_COMPLETE\t0\n+#define XRX200_DMA_PACKET_IN_PROGRESS\t1\n+\n /* cpu port mac */\n #define PMAC_RX_IPG\t\t0x0024\n #define PMAC_RX_IPG_MASK\t0xf\n@@ -61,6 +64,9 @@ struct xrx200_chan {\n \tstruct ltq_dma_channel dma;\n \tstruct sk_buff *skb[LTQ_DESC_NUM];\n \n+\tstruct sk_buff *skb_head;\n+\tstruct sk_buff *skb_tail;\n+\n \tstruct xrx200_priv *priv;\n };\n \n@@ -204,7 +210,8 @@ static int xrx200_hw_receive(struct xrx2\n \tstruct xrx200_priv *priv = ch->priv;\n \tstruct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];\n \tstruct sk_buff *skb = ch->skb[ch->dma.desc];\n-\tint len = (desc->ctl & LTQ_DMA_SIZE_MASK);\n+\tu32 ctl = desc->ctl;\n+\tint len = (ctl & LTQ_DMA_SIZE_MASK);\n \tstruct net_device *net_dev = priv->net_dev;\n \tint ret;\n \n@@ -220,12 +227,36 @@ static int xrx200_hw_receive(struct xrx2\n \t}\n \n \tskb_put(skb, len);\n-\tskb->protocol = eth_type_trans(skb, net_dev);\n-\tnetif_receive_skb(skb);\n-\tnet_dev->stats.rx_packets++;\n-\tnet_dev->stats.rx_bytes += len;\n \n-\treturn 0;\n+\t/* add buffers to skb via skb->frag_list */\n+\tif (ctl & LTQ_DMA_SOP) {\n+\t\tch->skb_head = skb;\n+\t\tch->skb_tail = skb;\n+\t} else if (ch->skb_head) {\n+\t\tif (ch->skb_head == ch->skb_tail)\n+\t\t\tskb_shinfo(ch->skb_tail)->frag_list = skb;\n+\t\telse\n+\t\t\tch->skb_tail->next = skb;\n+\t\tch->skb_tail = skb;\n+\t\tskb_reserve(ch->skb_tail, -NET_IP_ALIGN);\n+\t\tch->skb_head->len += skb->len;\n+\t\tch->skb_head->data_len += skb->len;\n+\t\tch->skb_head->truesize += skb->truesize;\n+\t}\n+\n+\tif (ctl & LTQ_DMA_EOP) {\n+\t\tch->skb_head->protocol = eth_type_trans(ch->skb_head, net_dev);\n+\t\tnetif_receive_skb(ch->skb_head);\n+\t\tnet_dev->stats.rx_packets++;\n+\t\tnet_dev->stats.rx_bytes += ch->skb_head->len;\n+\t\tch->skb_head = NULL;\n+\t\tch->skb_tail = NULL;\n+\t\tret = XRX200_DMA_PACKET_COMPLETE;\n+\t} else {\n+\t\tret = XRX200_DMA_PACKET_IN_PROGRESS;\n+\t}\n+\n+\treturn ret;\n }\n \n static int xrx200_poll_rx(struct napi_struct *napi, int budget)\n@@ -240,7 +271,9 @@ static int xrx200_poll_rx(struct napi_st\n \n \t\tif ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) {\n \t\t\tret = xrx200_hw_receive(ch);\n-\t\t\tif (ret)\n+\t\t\tif (ret == XRX200_DMA_PACKET_IN_PROGRESS)\n+\t\t\t\tcontinue;\n+\t\t\tif (ret != XRX200_DMA_PACKET_COMPLETE)\n \t\t\t\treturn ret;\n \t\t\trx++;\n \t\t} else {\n"
  },
  {
    "path": "target/linux/lantiq/patches-5.10/0705-v5.13-net-dsa-lantiq-allow-to-use-all-GPHYs-on-xRX300-and-.patch",
    "content": "From a09d042b086202735c4ed64573cdd79933020001 Mon Sep 17 00:00:00 2001\nFrom: Aleksander Jan Bajkowski <olek2@wp.pl>\nDate: Mon, 22 Mar 2021 21:37:15 +0100\nSubject: [PATCH] net: dsa: lantiq: allow to use all GPHYs on xRX300 and xRX330\n\nThis patch allows to use all PHYs on GRX300 and GRX330. The ARX300\nhas 3 and the GRX330 has 4 integrated PHYs connected to different\nports compared to VRX200. Each integrated PHY can work as single\nGigabit Ethernet PHY (GMII) or as double Fast Ethernet PHY (MII).\n\nAllowed port configurations:\n\nxRX200:\nGMAC0: RGMII, MII, REVMII or RMII port\nGMAC1: RGMII, MII, REVMII or RMII port\nGMAC2: GPHY0 (GMII)\nGMAC3: GPHY0 (MII)\nGMAC4: GPHY1 (GMII)\nGMAC5: GPHY1 (MII) or RGMII port\n\nxRX300:\nGMAC0: RGMII port\nGMAC1: GPHY2 (GMII)\nGMAC2: GPHY0 (GMII)\nGMAC3: GPHY0 (MII)\nGMAC4: GPHY1 (GMII)\nGMAC5: GPHY1 (MII) or RGMII port\n\nxRX330:\nGMAC0: RGMII, GMII or RMII port\nGMAC1: GPHY2 (GMII)\nGMAC2: GPHY0 (GMII)\nGMAC3: GPHY0 (MII) or GPHY3 (GMII)\nGMAC4: GPHY1 (GMII)\nGMAC5: GPHY1 (MII), RGMII or RMII port\n\nTested on D-Link DWR966 (xRX330) with OpenWRT.\n\nSigned-off-by: Aleksander Jan Bajkowski <olek2@wp.pl>\nAcked-by: Hauke Mehrtens <hauke@hauke-m.de>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/dsa/lantiq_gswip.c | 142 ++++++++++++++++++++++++++-------\n 1 file changed, 113 insertions(+), 29 deletions(-)\n\n--- a/drivers/net/dsa/lantiq_gswip.c\n+++ b/drivers/net/dsa/lantiq_gswip.c\n@@ -1,6 +1,6 @@\n // SPDX-License-Identifier: GPL-2.0\n /*\n- * Lantiq / Intel GSWIP switch driver for VRX200 SoCs\n+ * Lantiq / Intel GSWIP switch driver for VRX200, xRX300 and xRX330 SoCs\n  *\n  * Copyright (C) 2010 Lantiq Deutschland\n  * Copyright (C) 2012 John Crispin <john@phrozen.org>\n@@ -104,6 +104,7 @@\n #define  GSWIP_MII_CFG_MODE_RMIIP\t0x2\n #define  GSWIP_MII_CFG_MODE_RMIIM\t0x3\n #define  GSWIP_MII_CFG_MODE_RGMII\t0x4\n+#define  GSWIP_MII_CFG_MODE_GMII\t0x9\n #define  GSWIP_MII_CFG_MODE_MASK\t0xf\n #define  GSWIP_MII_CFG_RATE_M2P5\t0x00\n #define  GSWIP_MII_CFG_RATE_M25\t0x10\n@@ -241,6 +242,7 @@\n struct gswip_hw_info {\n \tint max_ports;\n \tint cpu_port;\n+\tconst struct dsa_switch_ops *ops;\n };\n \n struct xway_gphy_match_data {\n@@ -1438,12 +1440,42 @@ static int gswip_port_fdb_dump(struct ds\n \treturn 0;\n }\n \n-static void gswip_phylink_validate(struct dsa_switch *ds, int port,\n-\t\t\t\t   unsigned long *supported,\n-\t\t\t\t   struct phylink_link_state *state)\n+static void gswip_phylink_set_capab(unsigned long *supported,\n+\t\t\t\t    struct phylink_link_state *state)\n {\n \t__ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };\n \n+\t/* Allow all the expected bits */\n+\tphylink_set(mask, Autoneg);\n+\tphylink_set_port_modes(mask);\n+\tphylink_set(mask, Pause);\n+\tphylink_set(mask, Asym_Pause);\n+\n+\t/* With the exclusion of MII, Reverse MII and Reduced MII, we\n+\t * support Gigabit, including Half duplex\n+\t */\n+\tif (state->interface != PHY_INTERFACE_MODE_MII &&\n+\t    state->interface != PHY_INTERFACE_MODE_REVMII &&\n+\t    state->interface != PHY_INTERFACE_MODE_RMII) {\n+\t\tphylink_set(mask, 1000baseT_Full);\n+\t\tphylink_set(mask, 1000baseT_Half);\n+\t}\n+\n+\tphylink_set(mask, 10baseT_Half);\n+\tphylink_set(mask, 10baseT_Full);\n+\tphylink_set(mask, 100baseT_Half);\n+\tphylink_set(mask, 100baseT_Full);\n+\n+\tbitmap_and(supported, supported, mask,\n+\t\t   __ETHTOOL_LINK_MODE_MASK_NBITS);\n+\tbitmap_and(state->advertising, state->advertising, mask,\n+\t\t   __ETHTOOL_LINK_MODE_MASK_NBITS);\n+}\n+\n+static void gswip_xrx200_phylink_validate(struct dsa_switch *ds, int port,\n+\t\t\t\t\t  unsigned long *supported,\n+\t\t\t\t\t  struct phylink_link_state *state)\n+{\n \tswitch (port) {\n \tcase 0:\n \tcase 1:\n@@ -1470,38 +1502,54 @@ static void gswip_phylink_validate(struc\n \t\treturn;\n \t}\n \n-\t/* Allow all the expected bits */\n-\tphylink_set(mask, Autoneg);\n-\tphylink_set_port_modes(mask);\n-\tphylink_set(mask, Pause);\n-\tphylink_set(mask, Asym_Pause);\n+\tgswip_phylink_set_capab(supported, state);\n \n-\t/* With the exclusion of MII, Reverse MII and Reduced MII, we\n-\t * support Gigabit, including Half duplex\n-\t */\n-\tif (state->interface != PHY_INTERFACE_MODE_MII &&\n-\t    state->interface != PHY_INTERFACE_MODE_REVMII &&\n-\t    state->interface != PHY_INTERFACE_MODE_RMII) {\n-\t\tphylink_set(mask, 1000baseT_Full);\n-\t\tphylink_set(mask, 1000baseT_Half);\n+\treturn;\n+\n+unsupported:\n+\tbitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);\n+\tdev_err(ds->dev, \"Unsupported interface '%s' for port %d\\n\",\n+\t\tphy_modes(state->interface), port);\n+}\n+\n+static void gswip_xrx300_phylink_validate(struct dsa_switch *ds, int port,\n+\t\t\t\t\t  unsigned long *supported,\n+\t\t\t\t\t  struct phylink_link_state *state)\n+{\n+\tswitch (port) {\n+\tcase 0:\n+\t\tif (!phy_interface_mode_is_rgmii(state->interface) &&\n+\t\t    state->interface != PHY_INTERFACE_MODE_GMII &&\n+\t\t    state->interface != PHY_INTERFACE_MODE_RMII)\n+\t\t\tgoto unsupported;\n+\t\tbreak;\n+\tcase 1:\n+\tcase 2:\n+\tcase 3:\n+\tcase 4:\n+\t\tif (state->interface != PHY_INTERFACE_MODE_INTERNAL)\n+\t\t\tgoto unsupported;\n+\t\tbreak;\n+\tcase 5:\n+\t\tif (!phy_interface_mode_is_rgmii(state->interface) &&\n+\t\t    state->interface != PHY_INTERFACE_MODE_INTERNAL &&\n+\t\t    state->interface != PHY_INTERFACE_MODE_RMII)\n+\t\t\tgoto unsupported;\n+\t\tbreak;\n+\tdefault:\n+\t\tbitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);\n+\t\tdev_err(ds->dev, \"Unsupported port: %i\\n\", port);\n+\t\treturn;\n \t}\n \n-\tphylink_set(mask, 10baseT_Half);\n-\tphylink_set(mask, 10baseT_Full);\n-\tphylink_set(mask, 100baseT_Half);\n-\tphylink_set(mask, 100baseT_Full);\n+\tgswip_phylink_set_capab(supported, state);\n \n-\tbitmap_and(supported, supported, mask,\n-\t\t   __ETHTOOL_LINK_MODE_MASK_NBITS);\n-\tbitmap_and(state->advertising, state->advertising, mask,\n-\t\t   __ETHTOOL_LINK_MODE_MASK_NBITS);\n \treturn;\n \n unsupported:\n \tbitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);\n \tdev_err(ds->dev, \"Unsupported interface '%s' for port %d\\n\",\n \t\tphy_modes(state->interface), port);\n-\treturn;\n }\n \n static void gswip_port_set_link(struct gswip_priv *priv, int port, bool link)\n@@ -1639,6 +1687,9 @@ static void gswip_phylink_mac_config(str\n \tcase PHY_INTERFACE_MODE_RGMII_TXID:\n \t\tmiicfg |= GSWIP_MII_CFG_MODE_RGMII;\n \t\tbreak;\n+\tcase PHY_INTERFACE_MODE_GMII:\n+\t\tmiicfg |= GSWIP_MII_CFG_MODE_GMII;\n+\t\tbreak;\n \tdefault:\n \t\tdev_err(ds->dev,\n \t\t\t\"Unsupported interface: %d\\n\", state->interface);\n@@ -1765,7 +1816,7 @@ static int gswip_get_sset_count(struct d\n \treturn ARRAY_SIZE(gswip_rmon_cnt);\n }\n \n-static const struct dsa_switch_ops gswip_switch_ops = {\n+static const struct dsa_switch_ops gswip_xrx200_switch_ops = {\n \t.get_tag_protocol\t= gswip_get_tag_protocol,\n \t.setup\t\t\t= gswip_setup,\n \t.port_enable\t\t= gswip_port_enable,\n@@ -1781,7 +1832,31 @@ static const struct dsa_switch_ops gswip\n \t.port_fdb_add\t\t= gswip_port_fdb_add,\n \t.port_fdb_del\t\t= gswip_port_fdb_del,\n \t.port_fdb_dump\t\t= gswip_port_fdb_dump,\n-\t.phylink_validate\t= gswip_phylink_validate,\n+\t.phylink_validate\t= gswip_xrx200_phylink_validate,\n+\t.phylink_mac_config\t= gswip_phylink_mac_config,\n+\t.phylink_mac_link_down\t= gswip_phylink_mac_link_down,\n+\t.phylink_mac_link_up\t= gswip_phylink_mac_link_up,\n+\t.get_strings\t\t= gswip_get_strings,\n+\t.get_ethtool_stats\t= gswip_get_ethtool_stats,\n+\t.get_sset_count\t\t= gswip_get_sset_count,\n+};\n+\n+static const struct dsa_switch_ops gswip_xrx300_switch_ops = {\n+\t.get_tag_protocol\t= gswip_get_tag_protocol,\n+\t.setup\t\t\t= gswip_setup,\n+\t.port_enable\t\t= gswip_port_enable,\n+\t.port_disable\t\t= gswip_port_disable,\n+\t.port_bridge_join\t= gswip_port_bridge_join,\n+\t.port_bridge_leave\t= gswip_port_bridge_leave,\n+\t.port_fast_age\t\t= gswip_port_fast_age,\n+\t.port_vlan_filtering\t= gswip_port_vlan_filtering,\n+\t.port_vlan_add\t\t= gswip_port_vlan_add,\n+\t.port_vlan_del\t\t= gswip_port_vlan_del,\n+\t.port_stp_state_set\t= gswip_port_stp_state_set,\n+\t.port_fdb_add\t\t= gswip_port_fdb_add,\n+\t.port_fdb_del\t\t= gswip_port_fdb_del,\n+\t.port_fdb_dump\t\t= gswip_port_fdb_dump,\n+\t.phylink_validate\t= gswip_xrx300_phylink_validate,\n \t.phylink_mac_config\t= gswip_phylink_mac_config,\n \t.phylink_mac_link_down\t= gswip_phylink_mac_link_down,\n \t.phylink_mac_link_up\t= gswip_phylink_mac_link_up,\n@@ -2043,7 +2118,7 @@ static int gswip_probe(struct platform_d\n \tpriv->ds->dev = dev;\n \tpriv->ds->num_ports = priv->hw_info->max_ports;\n \tpriv->ds->priv = priv;\n-\tpriv->ds->ops = &gswip_switch_ops;\n+\tpriv->ds->ops = priv->hw_info->ops;\n \tpriv->dev = dev;\n \tversion = gswip_switch_r(priv, GSWIP_VERSION);\n \n@@ -2127,10 +2202,19 @@ static int gswip_remove(struct platform_\n static const struct gswip_hw_info gswip_xrx200 = {\n \t.max_ports = 7,\n \t.cpu_port = 6,\n+\t.ops = &gswip_xrx200_switch_ops,\n+};\n+\n+static const struct gswip_hw_info gswip_xrx300 = {\n+\t.max_ports = 7,\n+\t.cpu_port = 6,\n+\t.ops = &gswip_xrx300_switch_ops,\n };\n \n static const struct of_device_id gswip_of_match[] = {\n \t{ .compatible = \"lantiq,xrx200-gswip\", .data = &gswip_xrx200 },\n+\t{ .compatible = \"lantiq,xrx300-gswip\", .data = &gswip_xrx300 },\n+\t{ .compatible = \"lantiq,xrx330-gswip\", .data = &gswip_xrx300 },\n \t{},\n };\n MODULE_DEVICE_TABLE(of, gswip_of_match);\n"
  },
  {
    "path": "target/linux/lantiq/patches-5.10/0706-v5.18-net-lantiq-enable-jumbo-frames-on-GSWIP.patch",
    "content": "From c40bb4fedcd6b8b6a714da5dd466eb88ed2652d1 Mon Sep 17 00:00:00 2001\nFrom: Aleksander Jan Bajkowski <olek2@wp.pl>\nDate: Wed, 9 Mar 2022 00:04:57 +0100\nSubject: net: dsa: lantiq_gswip: enable jumbo frames on GSWIP\n\nThis enables non-standard MTUs on a per-port basis, with the overall\nframe size set based on the CPU port.\n\nWhen the MTU is not changed, this should have no effect.\n\nLong packets crash the switch with MTUs of greater than 2526, so the\nmaximum is limited for now. Medium packets are sometimes dropped (e.g.\nTCP over 2477, UDP over 2516-2519, ICMP over 2526), Hence an MTU value\nof 2400 seems safe.\n\nSigned-off-by: Thomas Nixon <tom@tomn.co.uk>\nSigned-off-by: Aleksander Jan Bajkowski <olek2@wp.pl>\nLink: https://lore.kernel.org/r/20220308230457.1599237-1-olek2@wp.pl\nSigned-off-by: Jakub Kicinski <kuba@kernel.org>\n---\n drivers/net/dsa/lantiq_gswip.c | 53 ++++++++++++++++++++++++++++++++++++++----\n 1 file changed, 49 insertions(+), 4 deletions(-)\n\n--- a/drivers/net/dsa/lantiq_gswip.c\n+++ b/drivers/net/dsa/lantiq_gswip.c\n@@ -213,6 +213,7 @@\n #define  GSWIP_MAC_CTRL_0_GMII_MII\t0x0001\n #define  GSWIP_MAC_CTRL_0_GMII_RGMII\t0x0002\n #define GSWIP_MAC_CTRL_2p(p)\t\t(0x905 + ((p) * 0xC))\n+#define GSWIP_MAC_CTRL_2_LCHKL\t\tBIT(2) /* Frame Length Check Long Enable */\n #define GSWIP_MAC_CTRL_2_MLEN\t\tBIT(3) /* Maximum Untagged Frame Lnegth */\n \n /* Ethernet Switch Fetch DMA Port Control Register */\n@@ -239,6 +240,15 @@\n \n #define XRX200_GPHY_FW_ALIGN\t(16 * 1024)\n \n+/* Maximum packet size supported by the switch. In theory this should be 10240,\n+ * but long packets currently cause lock-ups with an MTU of over 2526. Medium\n+ * packets are sometimes dropped (e.g. TCP over 2477, UDP over 2516-2519, ICMP\n+ * over 2526), hence an MTU value of 2400 seems safe. This issue only affects\n+ * packet reception. This is probably caused by the PPA engine, which is on the\n+ * RX part of the device. Packet transmission works properly up to 10240.\n+ */\n+#define GSWIP_MAX_PACKET_LENGTH\t2400\n+\n struct gswip_hw_info {\n \tint max_ports;\n \tint cpu_port;\n@@ -858,10 +868,6 @@ static int gswip_setup(struct dsa_switch\n \tgswip_switch_mask(priv, 0, GSWIP_PCE_PCTRL_0_INGRESS,\n \t\t\t  GSWIP_PCE_PCTRL_0p(cpu_port));\n \n-\tgswip_switch_mask(priv, 0, GSWIP_MAC_CTRL_2_MLEN,\n-\t\t\t  GSWIP_MAC_CTRL_2p(cpu_port));\n-\tgswip_switch_w(priv, VLAN_ETH_FRAME_LEN + 8 + ETH_FCS_LEN,\n-\t\t       GSWIP_MAC_FLEN);\n \tgswip_switch_mask(priv, 0, GSWIP_BM_QUEUE_GCTRL_GL_MOD,\n \t\t\t  GSWIP_BM_QUEUE_GCTRL);\n \n@@ -878,6 +884,8 @@ static int gswip_setup(struct dsa_switch\n \t\treturn err;\n \t}\n \n+\tds->mtu_enforcement_ingress = true;\n+\n \tgswip_port_enable(ds, cpu_port, NULL);\n \treturn 0;\n }\n@@ -1472,6 +1480,39 @@ static void gswip_phylink_set_capab(unsi\n \t\t   __ETHTOOL_LINK_MODE_MASK_NBITS);\n }\n \n+static int gswip_port_max_mtu(struct dsa_switch *ds, int port)\n+{\n+\t/* Includes 8 bytes for special header. */\n+\treturn GSWIP_MAX_PACKET_LENGTH - VLAN_ETH_HLEN - ETH_FCS_LEN;\n+}\n+\n+static int gswip_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu)\n+{\n+\tstruct gswip_priv *priv = ds->priv;\n+\tint cpu_port = priv->hw_info->cpu_port;\n+\n+\t/* CPU port always has maximum mtu of user ports, so use it to set\n+\t * switch frame size, including 8 byte special header.\n+\t */\n+\tif (port == cpu_port) {\n+\t\tnew_mtu += 8;\n+\t\tgswip_switch_w(priv, VLAN_ETH_HLEN + new_mtu + ETH_FCS_LEN,\n+\t\t\t       GSWIP_MAC_FLEN);\n+\t}\n+\n+\t/* Enable MLEN for ports with non-standard MTUs, including the special\n+\t * header on the CPU port added above.\n+\t */\n+\tif (new_mtu != ETH_DATA_LEN)\n+\t\tgswip_switch_mask(priv, 0, GSWIP_MAC_CTRL_2_MLEN,\n+\t\t\t\t  GSWIP_MAC_CTRL_2p(port));\n+\telse\n+\t\tgswip_switch_mask(priv, GSWIP_MAC_CTRL_2_MLEN, 0,\n+\t\t\t\t  GSWIP_MAC_CTRL_2p(port));\n+\n+\treturn 0;\n+}\n+\n static void gswip_xrx200_phylink_validate(struct dsa_switch *ds, int port,\n \t\t\t\t\t  unsigned long *supported,\n \t\t\t\t\t  struct phylink_link_state *state)\n@@ -1832,6 +1873,8 @@ static const struct dsa_switch_ops gswip\n \t.port_fdb_add\t\t= gswip_port_fdb_add,\n \t.port_fdb_del\t\t= gswip_port_fdb_del,\n \t.port_fdb_dump\t\t= gswip_port_fdb_dump,\n+\t.port_change_mtu\t= gswip_port_change_mtu,\n+\t.port_max_mtu\t\t= gswip_port_max_mtu,\n \t.phylink_validate\t= gswip_xrx200_phylink_validate,\n \t.phylink_mac_config\t= gswip_phylink_mac_config,\n \t.phylink_mac_link_down\t= gswip_phylink_mac_link_down,\n@@ -1856,6 +1899,8 @@ static const struct dsa_switch_ops gswip\n \t.port_fdb_add\t\t= gswip_port_fdb_add,\n \t.port_fdb_del\t\t= gswip_port_fdb_del,\n \t.port_fdb_dump\t\t= gswip_port_fdb_dump,\n+\t.port_change_mtu\t= gswip_port_change_mtu,\n+\t.port_max_mtu\t\t= gswip_port_max_mtu,\n \t.phylink_validate\t= gswip_xrx300_phylink_validate,\n \t.phylink_mac_config\t= gswip_phylink_mac_config,\n \t.phylink_mac_link_down\t= gswip_phylink_mac_link_down,\n"
  },
  {
    "path": "target/linux/lantiq/patches-5.10/0710-v5.16-net-lantiq-configure-the-burst-length-in-ethernet-dr.patch",
    "content": "From 14d4e308e0aa0b78dc7a059716861a4380de3535 Mon Sep 17 00:00:00 2001\nFrom: Aleksander Jan Bajkowski <olek2@wp.pl>\nDate: Tue, 14 Sep 2021 23:21:02 +0200\nSubject: [PATCH 5/5] net: lantiq: configure the burst length in ethernet\n drivers\n\nConfigure the burst length in Ethernet drivers. This improves\nEthernet performance by 58%. According to the vendor BSP,\n8W burst length is supported by ar9 and newer SoCs.\n\nThe NAT benchmark results on xRX200 (Down/Up):\n* 2W: 330 Mb/s\n* 4W: 432 Mb/s    372 Mb/s\n* 8W: 520 Mb/s    389 Mb/s\n\nTested on xRX200 and xRX330.\n\nSigned-off-by: Aleksander Jan Bajkowski <olek2@wp.pl>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/ethernet/lantiq_etop.c   | 21 ++++++++++++++++++---\n drivers/net/ethernet/lantiq_xrx200.c | 21 ++++++++++++++++++---\n 2 files changed, 36 insertions(+), 6 deletions(-)\n\n--- a/drivers/net/ethernet/lantiq_etop.c\n+++ b/drivers/net/ethernet/lantiq_etop.c\n@@ -148,6 +148,9 @@ struct ltq_etop_priv {\n \tstruct ltq_etop_chan txch;\n \tstruct ltq_etop_chan rxch;\n \n+\tint tx_burst_len;\n+\tint rx_burst_len;\n+\n \tint tx_irq;\n \tint rx_irq;\n \n@@ -399,7 +402,7 @@ ltq_etop_dma_init(struct net_device *dev\n \tint rx = priv->rx_irq - LTQ_DMA_ETOP;\n \tint err;\n \n-\tltq_dma_init_port(DMA_PORT_ETOP);\n+\tltq_dma_init_port(DMA_PORT_ETOP, priv->tx_burst_len, rx_burst_len);\n \n \tpriv->txch.dma.nr = tx;\n \tpriv->txch.dma.dev = &priv->pdev->dev;\n@@ -676,8 +679,8 @@ ltq_etop_tx(struct sk_buff *skb, struct\n \t\treturn NETDEV_TX_BUSY;\n \t}\n \n-\t/* dma needs to start on a 16 byte aligned address */\n-\tbyte_offset = CPHYSADDR(skb->data) % 16;\n+\t/* dma needs to start on a burst length value aligned address */\n+\tbyte_offset = CPHYSADDR(skb->data) % (priv->tx_burst_len * 4);\n \tpriv->txch.skb[priv->txch.dma.desc] = skb;\n \n \tnetif_trans_update(dev);\n@@ -925,6 +928,18 @@ static int ltq_etop_probe(struct platfor\n \tspin_lock_init(&priv->lock);\n \tSET_NETDEV_DEV(dev, &pdev->dev);\n \n+\terr = device_property_read_u32(&pdev->dev, \"lantiq,tx-burst-length\", &priv->tx_burst_len);\n+\tif (err < 0) {\n+\t\tdev_err(&pdev->dev, \"unable to read tx-burst-length property\\n\");\n+\t\treturn err;\n+\t}\n+\n+\terr = device_property_read_u32(&pdev->dev, \"lantiq,rx-burst-length\", &priv->rx_burst_len);\n+\tif (err < 0) {\n+\t\tdev_err(&pdev->dev, \"unable to read rx-burst-length property\\n\");\n+\t\treturn err;\n+\t}\n+\n \tnetif_napi_add(dev, &priv->txch.napi, ltq_etop_poll_tx, 8);\n \tnetif_napi_add(dev, &priv->rxch.napi, ltq_etop_poll_rx, 32);\n \tpriv->txch.netdev = dev;\n--- a/drivers/net/ethernet/lantiq_xrx200.c\n+++ b/drivers/net/ethernet/lantiq_xrx200.c\n@@ -81,6 +81,9 @@ struct xrx200_priv {\n \tstruct net_device *net_dev;\n \tstruct device *dev;\n \n+\tint tx_burst_len;\n+\tint rx_burst_len;\n+\n \t__iomem void *pmac_reg;\n };\n \n@@ -363,8 +366,8 @@ static netdev_tx_t xrx200_start_xmit(str\n \tif (unlikely(dma_mapping_error(priv->dev, mapping)))\n \t\tgoto err_drop;\n \n-\t/* dma needs to start on a 16 byte aligned address */\n-\tbyte_offset = mapping % 16;\n+\t/* dma needs to start on a burst length value aligned address */\n+\tbyte_offset = mapping % (priv->tx_burst_len * 4);\n \n \tdesc->addr = mapping - byte_offset;\n \t/* Make sure the address is written before we give it to HW */\n@@ -465,7 +468,7 @@ static int xrx200_dma_init(struct xrx200\n \tint ret = 0;\n \tint i;\n \n-\tltq_dma_init_port(DMA_PORT_ETOP);\n+\tltq_dma_init_port(DMA_PORT_ETOP, priv->tx_burst_len, rx_burst_len);\n \n \tch_rx->dma.nr = XRX200_DMA_RX;\n \tch_rx->dma.dev = priv->dev;\n@@ -584,6 +587,18 @@ static int xrx200_probe(struct platform_\n \tif (err)\n \t\teth_hw_addr_random(net_dev);\n \n+\terr = device_property_read_u32(dev, \"lantiq,tx-burst-length\", &priv->tx_burst_len);\n+\tif (err < 0) {\n+\t\tdev_err(dev, \"unable to read tx-burst-length property\\n\");\n+\t\treturn err;\n+\t}\n+\n+\terr = device_property_read_u32(dev, \"lantiq,rx-burst-length\", &priv->rx_burst_len);\n+\tif (err < 0) {\n+\t\tdev_err(dev, \"unable to read rx-burst-length property\\n\");\n+\t\treturn err;\n+\t}\n+\n \t/* bring up the dma engine and IP core */\n \terr = xrx200_dma_init(priv);\n \tif (err)\n"
  },
  {
    "path": "target/linux/lantiq/patches-5.10/0711-v5.16-net-lantiq_xrx200-Hardcode-the-burst-length-value.patch",
    "content": "From 7e553c44f09a8f536090904c6db5b8c9dbafa03b Mon Sep 17 00:00:00 2001\nFrom: Aleksander Jan Bajkowski <olek2@wp.pl>\nDate: Tue, 26 Oct 2021 22:59:01 +0200\nSubject: [PATCH] net: lantiq_xrx200: Hardcode the burst length value\n\nAll SoCs with this IP core support 8 burst length. Hauke\nsuggested to hardcode this value and simplify the driver.\n\nLink: https://lkml.org/lkml/2021/9/14/1533\nSigned-off-by: Aleksander Jan Bajkowski <olek2@wp.pl>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/ethernet/lantiq_xrx200.c | 21 ++++-----------------\n 1 file changed, 4 insertions(+), 17 deletions(-)\n\n--- a/drivers/net/ethernet/lantiq_xrx200.c\n+++ b/drivers/net/ethernet/lantiq_xrx200.c\n@@ -25,6 +25,7 @@\n #define XRX200_DMA_DATA_LEN\t(SZ_64K - 1)\n #define XRX200_DMA_RX\t\t0\n #define XRX200_DMA_TX\t\t1\n+#define XRX200_DMA_BURST_LEN\t8\n \n #define XRX200_DMA_PACKET_COMPLETE\t0\n #define XRX200_DMA_PACKET_IN_PROGRESS\t1\n@@ -81,9 +82,6 @@ struct xrx200_priv {\n \tstruct net_device *net_dev;\n \tstruct device *dev;\n \n-\tint tx_burst_len;\n-\tint rx_burst_len;\n-\n \t__iomem void *pmac_reg;\n };\n \n@@ -367,7 +365,7 @@ static netdev_tx_t xrx200_start_xmit(str\n \t\tgoto err_drop;\n \n \t/* dma needs to start on a burst length value aligned address */\n-\tbyte_offset = mapping % (priv->tx_burst_len * 4);\n+\tbyte_offset = mapping % (XRX200_DMA_BURST_LEN * 4);\n \n \tdesc->addr = mapping - byte_offset;\n \t/* Make sure the address is written before we give it to HW */\n@@ -468,7 +466,8 @@ static int xrx200_dma_init(struct xrx200\n \tint ret = 0;\n \tint i;\n \n-\tltq_dma_init_port(DMA_PORT_ETOP, priv->tx_burst_len, rx_burst_len);\n+\tltq_dma_init_port(DMA_PORT_ETOP, XRX200_DMA_BURST_LEN,\n+\t\t\t  XRX200_DMA_BURST_LEN);\n \n \tch_rx->dma.nr = XRX200_DMA_RX;\n \tch_rx->dma.dev = priv->dev;\n@@ -587,18 +586,6 @@ static int xrx200_probe(struct platform_\n \tif (err)\n \t\teth_hw_addr_random(net_dev);\n \n-\terr = device_property_read_u32(dev, \"lantiq,tx-burst-length\", &priv->tx_burst_len);\n-\tif (err < 0) {\n-\t\tdev_err(dev, \"unable to read tx-burst-length property\\n\");\n-\t\treturn err;\n-\t}\n-\n-\terr = device_property_read_u32(dev, \"lantiq,rx-burst-length\", &priv->rx_burst_len);\n-\tif (err < 0) {\n-\t\tdev_err(dev, \"unable to read rx-burst-length property\\n\");\n-\t\treturn err;\n-\t}\n-\n \t/* bring up the dma engine and IP core */\n \terr = xrx200_dma_init(priv);\n \tif (err)\n"
  },
  {
    "path": "target/linux/lantiq/patches-5.10/0712-v5.16-net-ethernet-lantiq_etop-Fix-compilation-error.patch",
    "content": "From 68eabc348148ae051631e8dab13c3b1a85c82896 Mon Sep 17 00:00:00 2001\nFrom: Aleksander Jan Bajkowski <olek2@wp.pl>\nDate: Tue, 9 Nov 2021 23:23:54 +0100\nSubject: [PATCH] net: ethernet: lantiq_etop: Fix compilation error\n\nThis fixes the error detected when compiling the driver.\n\nFixes: 14d4e308e0aa (\"net: lantiq: configure the burst length in ethernet drivers\")\nReported-by: kernel test robot <lkp@intel.com>\nSigned-off-by: Aleksander Jan Bajkowski <olek2@wp.pl>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/ethernet/lantiq_etop.c | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/drivers/net/ethernet/lantiq_etop.c\n+++ b/drivers/net/ethernet/lantiq_etop.c\n@@ -402,7 +402,7 @@ ltq_etop_dma_init(struct net_device *dev\n \tint rx = priv->rx_irq - LTQ_DMA_ETOP;\n \tint err;\n \n-\tltq_dma_init_port(DMA_PORT_ETOP, priv->tx_burst_len, rx_burst_len);\n+\tltq_dma_init_port(DMA_PORT_ETOP, priv->tx_burst_len, priv->rx_burst_len);\n \n \tpriv->txch.dma.nr = tx;\n \tpriv->txch.dma.dev = &priv->pdev->dev;\n"
  },
  {
    "path": "target/linux/lantiq/patches-5.10/0713-v5.17-MIPS-lantiq-dma-increase-descritor-count.patch",
    "content": "From 5112e9234bbb89f8dd15c983206bd9107b8436d5 Mon Sep 17 00:00:00 2001\nFrom: Aleksander Jan Bajkowski <olek2@wp.pl>\nDate: Tue, 4 Jan 2022 16:11:42 +0100\nSubject: [PATCH 713/715] MIPS: lantiq: dma: increase descritor count\n\nNAT Performance results on BT Home Hub 5A (kernel 5.10.89, mtu 1500):\n\n\tDown\t\tUp\nBefore\t539 Mbps\t599 Mbps\nAfter\t545 Mbps\t625 Mbps\n\nSigned-off-by: Aleksander Jan Bajkowski <olek2@wp.pl>\nSigned-off-by: Jakub Kicinski <kuba@kernel.org>\n---\n arch/mips/include/asm/mach-lantiq/xway/xway_dma.h | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/arch/mips/include/asm/mach-lantiq/xway/xway_dma.h\n+++ b/arch/mips/include/asm/mach-lantiq/xway/xway_dma.h\n@@ -8,7 +8,7 @@\n #define LTQ_DMA_H__\n \n #define LTQ_DESC_SIZE\t\t0x08\t/* each descriptor is 64bit */\n-#define LTQ_DESC_NUM\t\t0x40\t/* 64 descriptors / channel */\n+#define LTQ_DESC_NUM\t\t0xC0\t/* 192 descriptors / channel */\n \n #define LTQ_DMA_OWN\t\tBIT(31) /* owner bit */\n #define LTQ_DMA_C\t\tBIT(30) /* complete bit */\n"
  },
  {
    "path": "target/linux/lantiq/patches-5.10/0714-v5.17-net-lantiq_xrx200-increase-napi-poll-weigth.patch",
    "content": "From 768818d772d5d4ddc0c7eb2e62848929270ab7a3 Mon Sep 17 00:00:00 2001\nFrom: Aleksander Jan Bajkowski <olek2@wp.pl>\nDate: Tue, 4 Jan 2022 16:11:43 +0100\nSubject: [PATCH 714/715] net: lantiq_xrx200: increase napi poll weigth\n\nNAT Performance results on BT Home Hub 5A (kernel 5.10.89, mtu 1500):\n\n\tDown\t\tUp\nBefore\t545 Mbps\t625 Mbps\nAfter\t577 Mbps\t648 Mbps\n\nSigned-off-by: Aleksander Jan Bajkowski <olek2@wp.pl>\nSigned-off-by: Jakub Kicinski <kuba@kernel.org>\n---\n drivers/net/ethernet/lantiq_xrx200.c | 6 ++++--\n 1 file changed, 4 insertions(+), 2 deletions(-)\n\n--- a/drivers/net/ethernet/lantiq_xrx200.c\n+++ b/drivers/net/ethernet/lantiq_xrx200.c\n@@ -606,8 +606,10 @@ static int xrx200_probe(struct platform_\n \t\t\t PMAC_HD_CTL);\n \n \t/* setup NAPI */\n-\tnetif_napi_add(net_dev, &priv->chan_rx.napi, xrx200_poll_rx, 32);\n-\tnetif_tx_napi_add(net_dev, &priv->chan_tx.napi, xrx200_tx_housekeeping, 32);\n+\tnetif_napi_add(net_dev, &priv->chan_rx.napi, xrx200_poll_rx,\n+\t\t       NAPI_POLL_WEIGHT);\n+\tnetif_tx_napi_add(net_dev, &priv->chan_tx.napi, xrx200_tx_housekeeping,\n+\t\t\t  NAPI_POLL_WEIGHT);\n \n \tplatform_set_drvdata(pdev, priv);\n \n"
  },
  {
    "path": "target/linux/lantiq/patches-5.10/0715-v5.17-net-lantiq_xrx200-convert-to-build_skb.patch",
    "content": "From e015593573b3e3f74bd8a63c05fa92902194a354 Mon Sep 17 00:00:00 2001\nFrom: Aleksander Jan Bajkowski <olek2@wp.pl>\nDate: Tue, 4 Jan 2022 16:11:44 +0100\nSubject: [PATCH 715/715] net: lantiq_xrx200: convert to build_skb\n\nWe can increase the efficiency of rx path by using buffers to receive\npackets then build SKBs around them just before passing into the network\nstack. In contrast, preallocating SKBs too early reduces CPU cache\nefficiency.\n\nNAT Performance results on BT Home Hub 5A (kernel 5.10.89, mtu 1500):\n\n\tDown\t\tUp\nBefore\t577 Mbps\t648 Mbps\nAfter\t624 Mbps\t695 Mbps\n\nSigned-off-by: Aleksander Jan Bajkowski <olek2@wp.pl>\nSigned-off-by: Jakub Kicinski <kuba@kernel.org>\n---\n drivers/net/ethernet/lantiq_xrx200.c | 56 ++++++++++++++++++----------\n 1 file changed, 36 insertions(+), 20 deletions(-)\n\n--- a/drivers/net/ethernet/lantiq_xrx200.c\n+++ b/drivers/net/ethernet/lantiq_xrx200.c\n@@ -63,7 +63,11 @@ struct xrx200_chan {\n \n \tstruct napi_struct napi;\n \tstruct ltq_dma_channel dma;\n-\tstruct sk_buff *skb[LTQ_DESC_NUM];\n+\n+\tunion {\n+\t\tstruct sk_buff *skb[LTQ_DESC_NUM];\n+\t\tvoid *rx_buff[LTQ_DESC_NUM];\n+\t};\n \n \tstruct sk_buff *skb_head;\n \tstruct sk_buff *skb_tail;\n@@ -78,6 +82,7 @@ struct xrx200_priv {\n \tstruct xrx200_chan chan_rx;\n \n \tu16 rx_buf_size;\n+\tu16 rx_skb_size;\n \n \tstruct net_device *net_dev;\n \tstruct device *dev;\n@@ -115,6 +120,12 @@ static int xrx200_buffer_size(int mtu)\n \treturn round_up(xrx200_max_frame_len(mtu), 4 * XRX200_DMA_BURST_LEN);\n }\n \n+static int xrx200_skb_size(u16 buf_size)\n+{\n+\treturn SKB_DATA_ALIGN(buf_size + NET_SKB_PAD + NET_IP_ALIGN) +\n+\t\tSKB_DATA_ALIGN(sizeof(struct skb_shared_info));\n+}\n+\n /* drop all the packets from the DMA ring */\n static void xrx200_flush_dma(struct xrx200_chan *ch)\n {\n@@ -173,30 +184,29 @@ static int xrx200_close(struct net_devic\n \treturn 0;\n }\n \n-static int xrx200_alloc_skb(struct xrx200_chan *ch)\n+static int xrx200_alloc_buf(struct xrx200_chan *ch, void *(*alloc)(unsigned int size))\n {\n-\tstruct sk_buff *skb = ch->skb[ch->dma.desc];\n+\tvoid *buf = ch->rx_buff[ch->dma.desc];\n \tstruct xrx200_priv *priv = ch->priv;\n \tdma_addr_t mapping;\n \tint ret = 0;\n \n-\tch->skb[ch->dma.desc] = netdev_alloc_skb_ip_align(priv->net_dev,\n-\t\t\t\t\t\t\t  priv->rx_buf_size);\n-\tif (!ch->skb[ch->dma.desc]) {\n+\tch->rx_buff[ch->dma.desc] = alloc(priv->rx_skb_size);\n+\tif (!ch->rx_buff[ch->dma.desc]) {\n \t\tret = -ENOMEM;\n \t\tgoto skip;\n \t}\n \n-\tmapping = dma_map_single(priv->dev, ch->skb[ch->dma.desc]->data,\n+\tmapping = dma_map_single(priv->dev, ch->rx_buff[ch->dma.desc],\n \t\t\t\t priv->rx_buf_size, DMA_FROM_DEVICE);\n \tif (unlikely(dma_mapping_error(priv->dev, mapping))) {\n-\t\tdev_kfree_skb_any(ch->skb[ch->dma.desc]);\n-\t\tch->skb[ch->dma.desc] = skb;\n+\t\tskb_free_frag(ch->rx_buff[ch->dma.desc]);\n+\t\tch->rx_buff[ch->dma.desc] = buf;\n \t\tret = -ENOMEM;\n \t\tgoto skip;\n \t}\n \n-\tch->dma.desc_base[ch->dma.desc].addr = mapping;\n+\tch->dma.desc_base[ch->dma.desc].addr = mapping + NET_SKB_PAD + NET_IP_ALIGN;\n \t/* Make sure the address is written before we give it to HW */\n \twmb();\n skip:\n@@ -210,13 +220,14 @@ static int xrx200_hw_receive(struct xrx2\n {\n \tstruct xrx200_priv *priv = ch->priv;\n \tstruct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];\n-\tstruct sk_buff *skb = ch->skb[ch->dma.desc];\n+\tvoid *buf = ch->rx_buff[ch->dma.desc];\n \tu32 ctl = desc->ctl;\n \tint len = (ctl & LTQ_DMA_SIZE_MASK);\n \tstruct net_device *net_dev = priv->net_dev;\n+\tstruct sk_buff *skb;\n \tint ret;\n \n-\tret = xrx200_alloc_skb(ch);\n+\tret = xrx200_alloc_buf(ch, napi_alloc_frag);\n \n \tch->dma.desc++;\n \tch->dma.desc %= LTQ_DESC_NUM;\n@@ -227,19 +238,21 @@ static int xrx200_hw_receive(struct xrx2\n \t\treturn ret;\n \t}\n \n+\tskb = build_skb(buf, priv->rx_skb_size);\n+\tskb_reserve(skb, NET_SKB_PAD);\n \tskb_put(skb, len);\n \n \t/* add buffers to skb via skb->frag_list */\n \tif (ctl & LTQ_DMA_SOP) {\n \t\tch->skb_head = skb;\n \t\tch->skb_tail = skb;\n+\t\tskb_reserve(skb, NET_IP_ALIGN);\n \t} else if (ch->skb_head) {\n \t\tif (ch->skb_head == ch->skb_tail)\n \t\t\tskb_shinfo(ch->skb_tail)->frag_list = skb;\n \t\telse\n \t\t\tch->skb_tail->next = skb;\n \t\tch->skb_tail = skb;\n-\t\tskb_reserve(ch->skb_tail, -NET_IP_ALIGN);\n \t\tch->skb_head->len += skb->len;\n \t\tch->skb_head->data_len += skb->len;\n \t\tch->skb_head->truesize += skb->truesize;\n@@ -395,12 +408,13 @@ xrx200_change_mtu(struct net_device *net\n \tstruct xrx200_chan *ch_rx = &priv->chan_rx;\n \tint old_mtu = net_dev->mtu;\n \tbool running = false;\n-\tstruct sk_buff *skb;\n+\tvoid *buff;\n \tint curr_desc;\n \tint ret = 0;\n \n \tnet_dev->mtu = new_mtu;\n \tpriv->rx_buf_size = xrx200_buffer_size(new_mtu);\n+\tpriv->rx_skb_size = xrx200_skb_size(priv->rx_buf_size);\n \n \tif (new_mtu <= old_mtu)\n \t\treturn ret;\n@@ -416,14 +430,15 @@ xrx200_change_mtu(struct net_device *net\n \n \tfor (ch_rx->dma.desc = 0; ch_rx->dma.desc < LTQ_DESC_NUM;\n \t     ch_rx->dma.desc++) {\n-\t\tskb = ch_rx->skb[ch_rx->dma.desc];\n-\t\tret = xrx200_alloc_skb(ch_rx);\n+\t\tbuff = ch_rx->rx_buff[ch_rx->dma.desc];\n+\t\tret = xrx200_alloc_buf(ch_rx, netdev_alloc_frag);\n \t\tif (ret) {\n \t\t\tnet_dev->mtu = old_mtu;\n \t\t\tpriv->rx_buf_size = xrx200_buffer_size(old_mtu);\n+\t\t\tpriv->rx_skb_size = xrx200_skb_size(priv->rx_buf_size);\n \t\t\tbreak;\n \t\t}\n-\t\tdev_kfree_skb_any(skb);\n+\t\tskb_free_frag(buff);\n \t}\n \n \tch_rx->dma.desc = curr_desc;\n@@ -476,7 +491,7 @@ static int xrx200_dma_init(struct xrx200\n \tltq_dma_alloc_rx(&ch_rx->dma);\n \tfor (ch_rx->dma.desc = 0; ch_rx->dma.desc < LTQ_DESC_NUM;\n \t     ch_rx->dma.desc++) {\n-\t\tret = xrx200_alloc_skb(ch_rx);\n+\t\tret = xrx200_alloc_buf(ch_rx, netdev_alloc_frag);\n \t\tif (ret)\n \t\t\tgoto rx_free;\n \t}\n@@ -511,7 +526,7 @@ rx_ring_free:\n \t/* free the allocated RX ring */\n \tfor (i = 0; i < LTQ_DESC_NUM; i++) {\n \t\tif (priv->chan_rx.skb[i])\n-\t\t\tdev_kfree_skb_any(priv->chan_rx.skb[i]);\n+\t\t\tskb_free_frag(priv->chan_rx.rx_buff[i]);\n \t}\n \n rx_free:\n@@ -528,7 +543,7 @@ static void xrx200_hw_cleanup(struct xrx\n \n \t/* free the allocated RX ring */\n \tfor (i = 0; i < LTQ_DESC_NUM; i++)\n-\t\tdev_kfree_skb_any(priv->chan_rx.skb[i]);\n+\t\tskb_free_frag(priv->chan_rx.rx_buff[i]);\n }\n \n static int xrx200_probe(struct platform_device *pdev)\n@@ -554,6 +569,7 @@ static int xrx200_probe(struct platform_\n \tnet_dev->min_mtu = ETH_ZLEN;\n \tnet_dev->max_mtu = XRX200_DMA_DATA_LEN - xrx200_max_frame_len(0);\n \tpriv->rx_buf_size = xrx200_buffer_size(ETH_DATA_LEN);\n+\tpriv->rx_skb_size = xrx200_skb_size(priv->rx_buf_size);\n \n \t/* load the memory ranges */\n \tres = platform_get_resource(pdev, IORESOURCE_MEM, 0);\n"
  },
  {
    "path": "target/linux/lantiq/patches-5.10/0716-v5.17-net-lantiq_xrx200-fix-use-after-free-bug.patch",
    "content": "From dd830aed23c6e07cd8e2a163742bf3d63c9add08 Mon Sep 17 00:00:00 2001\nFrom: Aleksander Jan Bajkowski <olek2@wp.pl>\nDate: Sat, 5 Mar 2022 12:20:39 +0100\nSubject: net: lantiq_xrx200: fix use after free bug\n\nThe skb->len field is read after the packet is sent to the network\nstack. In the meantime, skb can be freed. This patch fixes this bug.\n\nFixes: c3e6b2c35b34 (\"net: lantiq_xrx200: add ingress SG DMA support\")\nReported-by: Eric Dumazet <eric.dumazet@gmail.com>\nSigned-off-by: Aleksander Jan Bajkowski <olek2@wp.pl>\nAcked-by: Hauke Mehrtens <hauke@hauke-m.de>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/ethernet/lantiq_xrx200.c | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/drivers/net/ethernet/lantiq_xrx200.c\n+++ b/drivers/net/ethernet/lantiq_xrx200.c\n@@ -260,9 +260,9 @@ static int xrx200_hw_receive(struct xrx2\n \n \tif (ctl & LTQ_DMA_EOP) {\n \t\tch->skb_head->protocol = eth_type_trans(ch->skb_head, net_dev);\n-\t\tnetif_receive_skb(ch->skb_head);\n \t\tnet_dev->stats.rx_packets++;\n \t\tnet_dev->stats.rx_bytes += ch->skb_head->len;\n+\t\tnetif_receive_skb(ch->skb_head);\n \t\tch->skb_head = NULL;\n \t\tch->skb_tail = NULL;\n \t\tret = XRX200_DMA_PACKET_COMPLETE;\n"
  },
  {
    "path": "target/linux/lantiq/xrx200/base-files/etc/board.d/01_leds",
    "content": "#\n# Copyright (C) 2011-2015 OpenWrt.org\n#\n\n. /lib/functions/leds.sh\n. /lib/functions/uci-defaults.sh\n\nboard_config_update\n\nled_wifi=\"$(get_dt_led wifi)\"\n[ -n \"$led_wifi\" ] && ucidef_set_led_wlan \"wifi\" \"wifi\" \"$led_wifi\" \"phy0tpt\"\n\nled_dsl=\"$(get_dt_led dsl)\"\n[ -n \"$led_dsl\" ] && {\n\tled_internet=\"$(get_dt_led internet)\"\n\tif [ -n \"$led_internet\" ]; then\n\t\tucidef_set_led_default \"dsl\" \"dsl\" \"$led_dsl\" \"0\"\n\t\tucidef_set_led_netdev \"internet\" \"internet\" \"$led_internet\" \"pppoe-wan\"\n\telse\n\t\tucidef_set_led_netdev \"dsl\" \"dsl\" \"$led_dsl\" \"dsl0\"\n\tfi\n}\n\nboard=$(board_name)\n\ncase \"$board\" in\narcadyan,arv7519rw22)\n\tucidef_set_led_netdev \"lan\" \"lan\" \"green:lan\" \"eth0.1\"\n\t;;\narcadyan,vgv7510kw22-nor|\\\narcadyan,vgv7510kw22-brn|\\\nzyxel,p-2812hnu-f1|\\\nzyxel,p-2812hnu-f3)\n\tucidef_set_led_wlan \"wifi\" \"wifi\" \"green:wlan\" \"phy0radio\"\n\t;;\narcadyan,vgv7519-nor|\\\narcadyan,vgv7519-brn)\n\tucidef_set_led_wlan \"wifi\" \"wifi\" \"green:wireless\" \"phy0radio\"\n\t;;\navm,fritz3370-rev2-hynix|\\\navm,fritz3370-rev2-micron|\\\navm,fritz3390)\n\tucidef_set_led_switch \"lan\" \"LAN\" \"green:lan\" \"switch0\" \"0x17\"\n\t;;\nbt,homehub-v5a)\n\tucidef_set_led_default \"dimmed\" \"dimmed\" \"dimmed\" \"0\"\n\t;;\nbuffalo,wbmr-300hpd)\n\tucidef_set_led_switch \"lan1\" \"LAN1\" \"green:lan1\" \"switch0\" \"0x08\"\n\tucidef_set_led_switch \"lan2\" \"LAN2\" \"green:lan2\" \"switch0\" \"0x04\"\n\tucidef_set_led_switch \"wan\" \"WAN\" \"green:wan\" \"switch0\" \"0x10\"\n\tucidef_set_led_switch \"lan3\" \"LAN3\" \"green:lan3\" \"switch0\" \"0x20\"\n\tucidef_set_led_default \"router\" \"router\" \"green:router\" \"1\"\n\t;;\nnetgear,dm200)\n\tucidef_set_led_netdev \"lan\" \"lan\" \"green:lan\" \"eth0\"\n\t;;\nesac\n\nboard_config_flush\n\nexit 0\n"
  },
  {
    "path": "target/linux/lantiq/xrx200/base-files/etc/board.d/02_network",
    "content": "#\n# Copyright (C) 2011-2015 OpenWrt.org\n#\n\n. /lib/functions/uci-defaults.sh\n. /lib/functions/system.sh\n. /lib/functions/lantiq.sh\n\nlantiq_setup_interfaces()\n{\n\tlocal board=\"$1\"\n\n\tcase \"$board\" in\n\talphanetworks,asl56026|\\\n\tarcadyan,vg3503j)\n\t\tucidef_set_interface_lan \"lan1 lan2\"\n\t\t;;\n\tarcadyan,arv7519rw22)\n\t\tucidef_set_interface_lan \"lan1 lan2 lan3 lan4 lan5\"\n\t\t;;\n\tarcadyan,vgv7510kw22-brn|\\\n\tarcadyan,vgv7510kw22-nor|\\\n\tarcadyan,vgv7519-brn|\\\n\tarcadyan,vgv7519-nor|\\\n\tbt,homehub-v5a|\\\n\tlantiq,easy80920-nand|\\\n\tlantiq,easy80920-nor|\\\n\tzyxel,p-2812hnu-f1|\\\n\tzyxel,p-2812hnu-f3)\n\t\tucidef_set_interfaces_lan_wan \"lan1 lan2 lan3 lan4\" \"wan\"\n\t\t;;\n\tavm,fritz3370-rev2-hynix|\\\n\tavm,fritz3370-rev2-micron|\\\n\tavm,fritz3390|\\\n\tavm,fritz7360sl|\\\n\tavm,fritz7360-v2|\\\n\tavm,fritz7362sl|\\\n\tavm,fritz7430|\\\n\tbuffalo,wbmr-300hpd|\\\n\ttplink,tdw8970|\\\n\ttplink,tdw8980|\\\n\ttplink,vr200|\\\n\ttplink,vr200v)\n\t\tucidef_set_interface_lan \"lan1 lan2 lan3 lan4\"\n\t\t;;\n\tavm,fritz7412|\\\n\tnetgear,dm200)\n\t\tucidef_set_interface_lan \"lan\"\n\t\t;;\n\t*)\n\t\tucidef_set_interface_lan 'eth0'\n\t\t;;\n\tesac\n}\n\nlantiq_setup_dsl()\n{\n\tlocal board=\"$1\"\n\tlocal annex=\"a\"\n\n\tcase \"$board\" in\n\tarcadyan,vgv7510kw22-brn|\\\n\tarcadyan,vgv7510kw22-nor|\\\n\tavm,fritz3370-rev2-hynix|\\\n\tavm,fritz3370-rev2-micron|\\\n\tavm,fritz3390|\\\n\tavm,fritz7360sl|\\\n\tavm,fritz7362sl|\\\n\tavm,fritz7412|\\\n\tavm,fritz7430)\n\t\tannex=\"b\"\n\t\t;;\n\tesac\n\n\tlantiq_setup_dsl_helper \"$annex\"\n}\n\nlantiq_setup_macs()\n{\n\tlocal board=\"$1\"\n\tlocal lan_mac=\"\"\n\tlocal wan_mac=\"\"\n\n\tcase \"$board\" in\n\talphanetworks,asl56026)\n\t\tlan_mac=$(mtd_get_mac_ascii u-boot-env ethaddr)\n\t\twan_mac=$(mtd_get_mac_ascii u-boot-env wanmac)\n\t\t;;\n\tarcadyan,arv7519rw22)\n\t\twan_mac=$(macaddr_add \"$(mtd_get_mac_binary boardconfig 0x16)\" 1)\n\t\t;;\n\tarcadyan,vg3503j|\\\n\tlantiq,easy80920-nand|\\\n\tlantiq,easy80920-nor|\\\n\tzyxel,p-2812hnu-f1|\\\n\tzyxel,p-2812hnu-f3)\n\t\tlan_mac=$(mtd_get_mac_ascii u-boot-env ethaddr)\n\t\twan_mac=$(macaddr_add \"$lan_mac\" 1)\n\t\t;;\n\tarcadyan,vgv7510kw22-brn|\\\n\tarcadyan,vgv7510kw22-nor)\n\t\twan_mac=$(macaddr_add \"$(mtd_get_mac_binary board_config 0x16)\" 2)\n\t\t;;\n\tarcadyan,vgv7519-brn|\\\n\tarcadyan,vgv7519-nor)\n\t\twan_mac=$(mtd_get_mac_binary board_config 0x16)\n\t\t;;\n\tavm,fritz3370-rev2-hynix|\\\n\tavm,fritz3370-rev2-micron)\n\t\tlan_mac=$(fritz_tffs -n maca -i $(find_mtd_part \"tffs (1)\"))\n\t\twan_mac=$(macaddr_add \"$lan_mac\" 3)\n\t\t;;\n\tavm,fritz7360sl)\n\t\twan_mac=$(macaddr_add \"$(mtd_get_mac_binary urlader 0xa91)\" 1)\n\t\t;;\n\tavm,fritz3390|\\\n\tavm,fritz7362sl)\n\t\tlan_mac=$(fritz_tffs -n maca -i $(find_mtd_part \"tffs (1)\"))\n\t\twan_mac=$(fritz_tffs -n macdsl -i $(find_mtd_part \"tffs (1)\"))\n\t\t;;\n\tavm,fritz7412|\\\n\tavm,fritz7430)\n\t\ttffsdev=$(find_mtd_chardev \"nand-tffs\")\n\t\tlan_mac=$(/usr/bin/fritz_tffs_nand -d $tffsdev -n maca -o)\n\t\twan_mac=$(/usr/bin/fritz_tffs_nand -d $tffsdev -n macdsl -o)\n\t\t;;\n\tbt,homehub-v5a)\n\t\tlan_mac=$(mtd_get_mac_binary_ubi caldata 0x110c)\n\t\twan_mac=$(macaddr_add \"$lan_mac\" 1)\n\t\t;;\n\tbuffalo,wbmr-300hpd)\n\t\tlan_mac=$(mtd_get_mac_ascii u-boot-env ethaddr)\n\t\twan_mac=\"$lan_mac\"\n\t\t;;\n\tnetgear,dm200)\n\t\tlan_mac=$(mtd_get_mac_binary ART 0x0)\n\t\twan_mac=$(macaddr_add \"$lan_mac\" 1)\n\t\t;;\n\ttplink,tdw8970|\\\n\ttplink,tdw8980)\n\t\twan_mac=$(macaddr_add \"$(mtd_get_mac_binary boardconfig 0xf100)\" 1)\n\t\t;;\n\ttplink,vr200|\\\n\ttplink,vr200v)\n\t\twan_mac=$(macaddr_add \"$(mtd_get_mac_binary romfile 0xf100)\" 1)\n\t\t;;\n\tesac\n\n\t[ -n \"$lan_mac\" ] && ucidef_set_interface_macaddr \"lan\" \"$lan_mac\"\n\t[ -n \"$wan_mac\" ] && ucidef_set_interface_macaddr \"wan\" \"$wan_mac\"\n}\n\nboard_config_update\nboard=$(board_name)\nlantiq_setup_interfaces $board\nlantiq_setup_dsl $board\nlantiq_setup_macs $board\nboard_config_flush\n\nexit 0\n"
  },
  {
    "path": "target/linux/lantiq/xrx200/base-files/etc/board.d/05_compat-version",
    "content": "#\n# Copyright (C) 2020 OpenWrt.org\n#\n\n. /lib/functions.sh\n. /lib/functions/uci-defaults.sh\n\nboard_config_update\n\ncase \"$(board_name)\" in\n\t*)\n\t\tucidef_set_compat_version \"1.1\"\n\t\t;;\nesac\n\nboard_config_flush\n\nexit 0\n"
  },
  {
    "path": "target/linux/lantiq/xrx200/base-files/etc/hotplug.d/firmware/11-ath10k-caldata",
    "content": "#!/bin/sh\n\n[ -e /lib/firmware/$FIRMWARE ] && exit 0\n\n. /lib/functions/caldata.sh\n\ncase \"$FIRMWARE\" in\n\"ath10k/cal-pci-0000:02:00.0.bin\")\n\tboard=$(board_name)\n\tcase $board in\n\t\tbt,homehub-v5a)\n\t\t\tcaldata_extract_ubi \"caldata\" 0x5000 0x844\n\t\t\tath10k_patch_mac $(macaddr_add $(mtd_get_mac_binary_ubi caldata 0x110c) 3)\n\t\t\t;;\n\t\t*)\n\t\t\tcaldata_die \"board $board is not supported yet\"\n\t\t\t;;\n\tesac\n\t;;\nesac\n"
  },
  {
    "path": "target/linux/lantiq/xrx200/base-files/etc/hotplug.d/firmware/12-ath9k-eeprom",
    "content": "#!/bin/sh\n\n[ -e /lib/firmware/$FIRMWARE ] && exit 0\n\n. /lib/functions/caldata.sh\n\ncase \"$FIRMWARE\" in\n\t\"ath9k-eeprom-pci-0000:00:0e.0.bin\" | \\\n\t\"ath9k-eeprom-pci-0000:01:00.0.bin\" | \\\n\t\"ath9k-eeprom-pci-0000:02:00.0.bin\")\n\t\tboard=$(board_name)\n\n\t\tcase \"$board\" in\n\t\t\tavm,fritz3370-rev2-hynix|\\\n\t\t\tavm,fritz3370-rev2-micron|\\\n\t\t\tavm,fritz7362sl)\n\t\t\t\tcaldata_extract_reverse \"urlader\" 0x1541 0x440\n\t\t\t\t;;\n\t\t\tavm,fritz3390)\n\t\t\t\tcaldata_extract_reverse \"urlader\" 0x2546 0x440\n\t\t\t\t;;\n\t\t\tavm,fritz7360sl|\\\n\t\t\tavm,fritz7360-v2)\n\t\t\t\tcaldata_extract \"urlader\" 0x985 0x1000\n\t\t\t\t;;\n\t\t\tavm,fritz7412|\\\n\t\t\tavm,fritz7430)\n\t\t\t\t/usr/bin/fritz_cal_extract -i 1 -s 0x1e000 -e 0x207 -l 5120 -o /lib/firmware/$FIRMWARE $(find_mtd_chardev \"urlader\") || \\\n\t\t\t\t/usr/bin/fritz_cal_extract -i 1 -s 0x1e800 -e 0x207 -l 5120 -o /lib/firmware/$FIRMWARE $(find_mtd_chardev \"urlader\")\n\t\t\t\t;;\n\t\t\tbt,homehub-v5a)\n\t\t\t\tcaldata_extract_ubi \"caldata\" 0x1000 0x1000\n\t\t\t\tath9k_patch_mac_crc $(macaddr_add $(mtd_get_mac_binary_ubi caldata 0x110c) 2) 0x10c\n\t\t\t\t;;\n\t\t\ttplink,tdw8970|\\\n\t\t\ttplink,tdw8980)\n\t\t\t\tcaldata_extract \"boardconfig\" 0x21000 0x1000\n\t\t\t\t;;\n\t\t\t*)\n\t\t\t\tcaldata_die \"board $board is not supported yet\"\n\t\t\t\t;;\n\t\tesac\n\t\t;;\nesac\n"
  },
  {
    "path": "target/linux/lantiq/xrx200/base-files/etc/uci-defaults/01_led_migration",
    "content": "#\n# Copyright (C) 2013 OpenWrt.org\n#\n\n. /lib/functions/migrations.sh\n\ndo_internet_led_rename()\n{\n\tconfig_load system\n\n\t[ -n $(config_get led_internet name) ] || return\n\t[ -z $(config_get led_dsl name) ] || return\n\n\tuci rename system.led_internet=led_dsl\n\tuci set system.led_dsl.name=dsl\n\n\tlogger -t led-migration \"internet led renamed to dsl\"\n}\n\ncase \"$(board_name)\" in\nalphanetworks,asl56026|\\\narcadyan,arv7519rw22|\\\narcadyan,vg3503j|\\\navm,fritz7360sl|\\\nbt,homehub-v5a)\n\tdo_internet_led_rename\n\t;;\nesac\n\nremove_devicename_leds\n\nmigrations_apply system\n\nexit 0\n"
  },
  {
    "path": "target/linux/lantiq/xrx200/base-files/lib/upgrade/platform.sh",
    "content": "PART_NAME=firmware\nREQUIRE_IMAGE_METADATA=1\n\nplatform_check_image() {\n\treturn 0\n}\n\nplatform_do_upgrade() {\n\tlocal board=$(board_name)\n\n\tcase \"$board\" in\n\tavm,fritz3370-rev2-hynix|\\\n\tavm,fritz3370-rev2-micron|\\\n\tavm,fritz3390|\\\n\tavm,fritz7362sl|\\\n\tavm,fritz7412|\\\n\tavm,fritz7430|\\\n\tbt,homehub-v5a|\\\n\tzyxel,p-2812hnu-f1|\\\n\tzyxel,p-2812hnu-f3)\n\t\tnand_do_upgrade $1\n\t\t;;\n\t*)\n\t\tdefault_do_upgrade \"$1\"\n\t\t;;\n\tesac\n}\n"
  },
  {
    "path": "target/linux/lantiq/xrx200/config-5.10",
    "content": "CONFIG_AT803X_PHY=y\nCONFIG_BLK_MQ_PCI=y\nCONFIG_CPU_HAS_DIEI=y\nCONFIG_CPU_MIPSR2_IRQ_EI=y\nCONFIG_CPU_MIPSR2_IRQ_VI=y\nCONFIG_CPU_RMAP=y\nCONFIG_CRC16=y\nCONFIG_CRYPTO_ACOMP2=y\nCONFIG_CRYPTO_DEFLATE=y\nCONFIG_CRYPTO_HASH_INFO=y\nCONFIG_CRYPTO_LZO=y\nCONFIG_CRYPTO_ZSTD=y\nCONFIG_EXTRA_FIRMWARE=\"lantiq/xrx200_phy11g_a14.bin lantiq/xrx200_phy11g_a22.bin lantiq/xrx200_phy22f_a14.bin lantiq/xrx200_phy22f_a22.bin\"\nCONFIG_EXTRA_FIRMWARE_DIR=\"firmware\"\nCONFIG_GENERIC_ALLOCATOR=y\nCONFIG_GRO_CELLS=y\nCONFIG_HWMON=y\nCONFIG_HW_RANDOM=y\nCONFIG_ICPLUS_PHY=y\nCONFIG_IFX_VPE_EXT=y\nCONFIG_INPUT=y\nCONFIG_INPUT_EVDEV=y\nCONFIG_INPUT_POLLDEV=y\nCONFIG_INTEL_XWAY_PHY=y\n# CONFIG_ISDN is not set\nCONFIG_LANTIQ_XRX200=y\nCONFIG_LZO_COMPRESS=y\nCONFIG_LZO_DECOMPRESS=y\nCONFIG_MIPS_MT=y\n# CONFIG_MIPS_MT_FPAFF is not set\nCONFIG_MIPS_MT_SMP=y\nCONFIG_MIPS_NR_CPU_NR_MAP=2\nCONFIG_MIPS_PERF_SHARED_TC_COUNTERS=y\nCONFIG_MIPS_VPE_APSP_API=y\nCONFIG_MIPS_VPE_APSP_API_MT=y\nCONFIG_MIPS_VPE_LOADER=y\nCONFIG_MIPS_VPE_LOADER_MT=y\nCONFIG_MIPS_VPE_LOADER_TOM=y\nCONFIG_MTD_NAND_CORE=y\nCONFIG_MTD_NAND_ECC=y\nCONFIG_MTD_NAND_ECC_SW_HAMMING=y\nCONFIG_MTD_NAND_PLATFORM=y\nCONFIG_MTD_NAND_XWAY=y\nCONFIG_MTD_RAW_NAND=y\nCONFIG_MTD_UBI=y\nCONFIG_MTD_UBI_BEB_LIMIT=20\nCONFIG_MTD_UBI_BLOCK=y\nCONFIG_MTD_UBI_WL_THRESHOLD=4096\nCONFIG_NET_DEVLINK=y\nCONFIG_NET_DSA=y\nCONFIG_NET_DSA_LANTIQ_GSWIP=y\nCONFIG_NET_DSA_TAG_GSWIP=y\nCONFIG_NET_FLOW_LIMIT=y\nCONFIG_NET_SWITCHDEV=y\nCONFIG_NLS=y\nCONFIG_NR_CPUS=2\nCONFIG_PADATA=y\nCONFIG_PCI=y\nCONFIG_PCIEPORTBUS=y\nCONFIG_PCIE_LANTIQ=y\nCONFIG_PCI_DOMAINS=y\nCONFIG_PCI_LANTIQ=y\nCONFIG_PHY_LANTIQ_VRX200_PCIE=y\nCONFIG_POWER_RESET_GPIO=y\nCONFIG_POWER_SUPPLY=y\nCONFIG_POWER_SUPPLY_HWMON=y\nCONFIG_QUEUED_RWLOCKS=y\nCONFIG_QUEUED_SPINLOCKS=y\nCONFIG_REGULATOR=y\nCONFIG_REGULATOR_FIXED_VOLTAGE=y\nCONFIG_RFS_ACCEL=y\nCONFIG_RPS=y\nCONFIG_SENSORS_LTQ_CPUTEMP=y\nCONFIG_SGL_ALLOC=y\nCONFIG_SMP=y\nCONFIG_SMP_UP=y\nCONFIG_SOC_TYPE_XWAY=y\nCONFIG_SOC_XWAY=y\nCONFIG_SYNC_R4K=y\nCONFIG_SYS_SUPPORTS_SCHED_SMT=y\nCONFIG_SYS_SUPPORTS_SMP=y\nCONFIG_TREE_RCU=y\nCONFIG_TREE_SRCU=y\nCONFIG_UBIFS_FS=y\nCONFIG_USB=y\nCONFIG_USB_COMMON=y\nCONFIG_USB_SUPPORT=y\nCONFIG_XPS=y\nCONFIG_XXHASH=y\nCONFIG_ZLIB_DEFLATE=y\nCONFIG_ZLIB_INFLATE=y\nCONFIG_ZSTD_COMPRESS=y\nCONFIG_ZSTD_DECOMPRESS=y\n"
  },
  {
    "path": "target/linux/lantiq/xrx200/profiles/00-default.mk",
    "content": "define Profile/Default\n\tNAME:=Default Profile\n\tPRIORITY:=1\nendef\n\ndefine Profile/Default/Description\n\tDefault package set compatible with most boards.\nendef\n$(eval $(call Profile,Default))\n"
  },
  {
    "path": "target/linux/lantiq/xrx200/target.mk",
    "content": "ARCH:=mips\nSUBTARGET:=xrx200\nBOARDNAME:=XRX200\nFEATURES+=atm nand ramdisk\nCPU_TYPE:=24kc\n\nDEFAULT_PACKAGES+=kmod-leds-gpio \\\n\tkmod-gpio-button-hotplug \\\n\tltq-vdsl-vr9-vectoring-fw-installer \\\n\tkmod-ltq-vdsl-vr9-mei \\\n\tkmod-ltq-vdsl-vr9 \\\n\tkmod-ltq-atm-vr9 \\\n\tkmod-ltq-deu-vr9 \\\n\tkmod-ltq-ptm-vr9 \\\n\tltq-vdsl-app \\\n\tdsl-vrx200-firmware-xdsl-a \\\n\tdsl-vrx200-firmware-xdsl-b-patch \\\n\tppp-mod-pppoa\n\ndefine Target/Description\n\tLantiq XRX200\nendef\n"
  },
  {
    "path": "target/linux/lantiq/xway/base-files/etc/board.d/01_leds",
    "content": "#\n# Copyright (C) 2011-2015 OpenWrt.org\n#\n\n. /lib/functions/leds.sh\n. /lib/functions/uci-defaults.sh\n\nboard_config_update\n\nled_wifi=\"$(get_dt_led wifi)\"\n[ -n \"$led_wifi\" ] && ucidef_set_led_wlan \"wifi\" \"wifi\" \"$led_wifi\" \"phy0tpt\"\n\nled_usb=\"$(get_dt_led usb)\"\n[ -n \"$led_usb\" ] && ucidef_set_led_usbdev \"usb\" \"usb\" \"$led_usb\" \"1-1\"\n\nled_usb2=\"$(get_dt_led usb2)\"\n[ -n \"$led_usb2\" ] && ucidef_set_led_usbdev \"usb2\" \"usb2\" \"$led_usb2\" \"2-1\"\n\nled_dsl=\"$(get_dt_led dsl)\"\n[ -n \"$led_dsl\" ] && {\n\tled_internet=\"$(get_dt_led internet)\"\n\tif [ -n \"$led_internet\" ]; then\n\t\tucidef_set_led_default \"dsl\" \"dsl\" \"$led_dsl\" \"0\"\n\t\tucidef_set_led_netdev \"internet\" \"internet\" \"$led_internet\" \"pppoe-wan\"\n\telse\n\t\tucidef_set_led_netdev \"dsl\" \"dsl\" \"$led_dsl\" \"dsl0\"\n\tfi\n}\n\nboard=$(board_name)\n\ncase \"$board\" in\narcadyan,arv7506pw11)\n\tucidef_set_led_wlan \"wifi\" \"wifi\" \"green:wlan\" \"phy0radio\"\n\t;;\narcadyan,arv752dpw22)\n\tucidef_set_led_wlan \"wifi\" \"wifi\" \"red:wifi\" \"phy0radio\"\n\t;;\nesac\n\nboard_config_flush\n\nexit 0\n"
  },
  {
    "path": "target/linux/lantiq/xway/base-files/etc/board.d/02_network",
    "content": "#\n# Copyright (C) 2011-2015 OpenWrt.org\n#\n\n. /lib/functions/uci-defaults.sh\n. /lib/functions/system.sh\n. /lib/functions/lantiq.sh\n\nlantiq_setup_interfaces()\n{\n\tlocal board=\"$1\"\n\n\tcase \"$board\" in\n\tarcadyan,arv4510pw)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0:lan:4\" \"2:lan:2\" \"1:lan:3\" \"3:lan:1\" \"5t@eth0\"\n\t\t;;\n\tarcadyan,arv4519pw|\\\n\tarcadyan,arv7510pw22|\\\n\tarcadyan,arv7518pw|\\\n\tarcadyan,arv752dpw22|\\\n\tarcadyan,arv8539pw22|\\\n\tbuffalo,wbmr-hp-g300h)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0t@eth0\" \"2:lan\" \"3:lan\" \"4:lan\" \"5:lan\"\n\t\t;;\n\tarcadyan,arv7506pw11|\\\n\taudiocodes,mp-252|\\\n\tsiemens,gigaset-sx76x)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"1:lan:4\" \"2:lan:3\" \"3:lan:2\" \"4:lan:1\" \"5t@eth0\"\n\t\t;;\n\tarcadyan,arv7519pw|\\\n\tzte,h201l)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0:lan\" \"1:lan\" \"2:lan\" \"3:lan\" \"4t@eth0\"\n\t\t;;\n\tarcadyan,arv752dpw|\\\n\tbt,homehub-v2b)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"1:lan\" \"2:lan\" \"3:lan\" \"4:lan\" \"5t@eth0\"\n\t\t;;\n\tnetgear,dgn3500|\\\n\tnetgear,dgn3500b)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0:lan:4\" \"1:lan:3\" \"2:lan:2\" \"3:lan:1\" \"5t@eth0\"\n\t\t;;\n\tzyxel,p-2601hn)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0:lan\" \"1:lan\" \"2:lan\" \"3:lan\" \"5t@eth0\"\n\t\t;;\n\t*)\n\t\tucidef_set_interface_lan 'eth0'\n\t\t;;\n\tesac\n}\n\nlantiq_setup_dsl()\n{\n\tlocal board=\"$1\"\n\tlocal annex=\"a\"\n\n\tcase \"$board\" in\n\tarcadyan,arv7506pw11|\\\n\tarcadyan,arv7525pw|\\\n\tarcadyan,arv752dpw|\\\n\tarcadyan,arv752dpw22|\\\n\tarcadyan,arv8539pw22|\\\n\tavm,fritz7312|\\\n\tavm,fritz7320|\\\n\tsiemens,gigaset-sx76x|\\\n\tzte,h201l)\n\t\tannex=\"b\"\n\t\t;;\n\tesac\n\n\tlantiq_setup_dsl_helper \"$annex\"\n}\n\nlantiq_setup_macs()\n{\n\tlocal board=\"$1\"\n\tlocal lan_mac=\"\"\n\tlocal wan_mac=\"\"\n\n\tcase \"$board\" in\n\tarcadyan,arv4510pw|\\\n\tbt,homehub-v2b|\\\n\tbt,homehub-v3a|\\\n\tnetgear,dgn3500|\\\n\tnetgear,dgn3500b)\n\t\tlan_mac=$(mtd_get_mac_ascii u-boot-env ethaddr)\n\t\twan_mac=$(macaddr_add \"$lan_mac\" 1)\n\t\t;;\n\tarcadyan,arv7506pw11)\n\t\twan_mac=$(macaddr_add \"$(mtd_get_mac_binary board_config 0x16)\" 2)\n\t\t;;\n\tarcadyan,arv7519pw)\n\t\twan_mac=$(macaddr_add \"$(mtd_get_mac_binary board_config 0x16)\" 1)\n\t\t;;\n\tavm,fritz7312|\\\n\tavm,fritz7320)\n\t\twan_mac=$(macaddr_add \"$(mtd_get_mac_binary urlader 0xa91)\" 1)\n\t\t;;\n\tesac\n\n\t[ -n \"$lan_mac\" ] && ucidef_set_interface_macaddr \"lan\" \"$lan_mac\"\n\t[ -n \"$wan_mac\" ] && ucidef_set_interface_macaddr \"wan\" \"$wan_mac\"\n}\n\nboard_config_update\nboard=$(board_name)\nlantiq_setup_interfaces $board\nlantiq_setup_dsl $board\nlantiq_setup_macs $board\nboard_config_flush\n\nexit 0\n"
  },
  {
    "path": "target/linux/lantiq/xway/base-files/etc/hotplug.d/firmware/12-ath9k-eeprom",
    "content": "#!/bin/sh\n\n[ -e /lib/firmware/$FIRMWARE ] && exit 0\n\n. /lib/functions/caldata.sh\n\ncaldata_extract_swap() {\n\tlocal part=$1\n\tlocal offset=$2\n\tlocal count=$3\n\tlocal mtd\n\n\tmtd=$(find_mtd_chardev $part)\n\t[ -n \"$mtd\" ] || caldata_die \"no mtd device found for partition $part\"\n\n\toffset=$(($offset / 2))\n\tcount=$(($count / 2))\n\n\tdd if=$mtd of=/lib/firmware/$FIRMWARE bs=2 skip=$offset count=$count conv=swab 2>/dev/null || \\\n\t\tcaldata_die \"failed to extract calibration data from $mtd\"\n}\n\ncase \"$FIRMWARE\" in\n\t\"ath9k-eeprom-pci-0000:00:0e.0.bin\" | \\\n\t\"ath9k-eeprom-pci-0000:01:00.0.bin\" | \\\n\t\"ath9k-eeprom-pci-0000:02:00.0.bin\")\n\t\tboard=$(board_name)\n\n\t\tcase \"$board\" in\n\t\t\tarcadyan,arv7518pw)\n\t\t\t\tcaldata_extract_swap \"boardconfig\" 0x400 0x1000\n\t\t\t\t;;\n\t\t\tarcadyan,arv8539pw22)\n\t\t\t\tcaldata_extract_swap \"art\" 0x400 0x1000\n\t\t\t\t;;\n\t\t\tbt,homehub-v2b)\n\t\t\t\tcaldata_extract_swap \"art\" 0x0 0x1000\n\t\t\t\tath9k_patch_mac_crc \"00:00:00:00:00:00\" 0x20c\n\t\t\t\t;;\n\t\t\tbt,homehub-v3a)\n\t\t\t\tcaldata_extract_swap \"art-copy\" 0x0 0x1000\n\t\t\t\tath9k_patch_mac_crc $(macaddr_add $(mtd_get_mac_ascii u-boot-env ethaddr) 2) 0x10c\n\t\t\t\t;;\n\t\t\tnetgear,dgn3500|netgear,dgn3500b)\n\t\t\t\tcaldata_extract \"calibration\" 0xf000 0x1000\n\t\t\t\tath9k_patch_mac_crc $(macaddr_add $(mtd_get_mac_ascii u-boot-env ethaddr) 2) 0x20c\n\t\t\t\t;;\n\t\t\tavm,fritz7312|avm,fritz7320)\n\t\t\t\tcaldata_extract \"urlader\" 0x985 0x1000\n\t\t\t\t;;\n\t\t\t*)\n\t\t\t\tcaldata_die \"board $board is not supported yet\"\n\t\t\t\t;;\n\t\tesac\n\t\t;;\nesac\n"
  },
  {
    "path": "target/linux/lantiq/xway/base-files/etc/uci-defaults/01_led_migration",
    "content": "#\n# Copyright (C) 2013 OpenWrt.org\n#\n\n. /lib/functions/migrations.sh\n\ndo_internet_led_rename()\n{\n\tconfig_load system\n\n\t[ -n $(config_get led_internet name) ] || return\n\t[ -z $(config_get led_dsl name) ] || return\n\n\tuci rename system.led_internet=led_dsl\n\tuci set system.led_dsl.name=dsl\n\n\tlogger -t led-migration \"internet led renamed to dsl\"\n}\n\ncase \"$(board_name)\" in\narcadyan,arv7510pw22|\\\narcadyan,arv752dpw|\\\narcadyan,arv752dpw22|\\\nbt,homehub-v2b|\\\nbt,homehub-v3a)\n\tdo_internet_led_rename\n\t;;\nnetgear,dgn3500|\\\nnetgear,dgn3500b)\n\tmigrate_leds \"blue:wireless=green:wireless\"\n\t;;\nesac\n\nremove_devicename_leds\n\nmigrations_apply system\n\nexit 0\n"
  },
  {
    "path": "target/linux/lantiq/xway/base-files/lib/preinit/05_set_preinit_iface_lantiq",
    "content": "set_preinit_iface() {\n\tifname=eth0\n}\n\nboot_hook_add preinit_main set_preinit_iface\n"
  },
  {
    "path": "target/linux/lantiq/xway/base-files/lib/upgrade/platform.sh",
    "content": "PART_NAME=firmware\nREQUIRE_IMAGE_METADATA=1\n\nplatform_check_image() {\n\treturn 0\n}\n\nplatform_do_upgrade() {\n\tlocal board=$(board_name)\n\n\tcase \"$board\" in\n\tbt,homehub-v2b|\\\n\tbt,homehub-v3a)\n\t\tnand_do_upgrade $1\n\t\t;;\n\t*)\n\t\tdefault_do_upgrade \"$1\"\n\t\t;;\n\tesac\n}\n"
  },
  {
    "path": "target/linux/lantiq/xway/config-5.10",
    "content": "CONFIG_ADM6996_PHY=y\nCONFIG_AR8216_PHY=y\nCONFIG_AT803X_PHY=y\nCONFIG_BLK_MQ_PCI=y\nCONFIG_CPU_HAS_DIEI=y\nCONFIG_CRC16=y\nCONFIG_CRYPTO_ACOMP2=y\nCONFIG_CRYPTO_HASH_INFO=y\nCONFIG_CRYPTO_LZO=y\nCONFIG_ETHERNET_PACKET_MANGLE=y\nCONFIG_GENERIC_ALLOCATOR=y\nCONFIG_HW_RANDOM=y\nCONFIG_INPUT=y\nCONFIG_INPUT_EVDEV=y\nCONFIG_INPUT_POLLDEV=y\n# CONFIG_ISDN is not set\nCONFIG_LANTIQ_ETOP=y\nCONFIG_LZO_COMPRESS=y\nCONFIG_LZO_DECOMPRESS=y\nCONFIG_MTD_NAND_CORE=y\nCONFIG_MTD_NAND_ECC=y\nCONFIG_MTD_NAND_ECC_SW_HAMMING=y\nCONFIG_MTD_NAND_XWAY=y\nCONFIG_MTD_RAW_NAND=y\nCONFIG_MTD_UBI=y\nCONFIG_MTD_UBI_BEB_LIMIT=20\nCONFIG_MTD_UBI_BLOCK=y\nCONFIG_MTD_UBI_WL_THRESHOLD=4096\nCONFIG_NLS=y\nCONFIG_PCI=y\nCONFIG_PCI_DOMAINS=y\nCONFIG_PCI_LANTIQ=y\nCONFIG_PSB6970_PHY=y\nCONFIG_REGULATOR=y\nCONFIG_REGULATOR_FIXED_VOLTAGE=y\nCONFIG_RTL8306_PHY=y\nCONFIG_RTL8366RB_PHY=y\nCONFIG_RTL8366_SMI=y\nCONFIG_SGL_ALLOC=y\nCONFIG_SOC_TYPE_XWAY=y\nCONFIG_SOC_XWAY=y\nCONFIG_SWCONFIG=y\nCONFIG_UBIFS_FS=y\nCONFIG_USB=y\nCONFIG_USB_COMMON=y\nCONFIG_USB_SUPPORT=y\n"
  },
  {
    "path": "target/linux/lantiq/xway/profiles/00-default.mk",
    "content": "define Profile/Default\n\tNAME:=Default Profile\n\tPRIORITY:=1\nendef\n\ndefine Profile/Default/Description\n\tDefault package set compatible with most boards.\nendef\n$(eval $(call Profile,Default))\n"
  },
  {
    "path": "target/linux/lantiq/xway/target.mk",
    "content": "ARCH:=mips\nSUBTARGET:=xway\nBOARDNAME:=XWAY\nFEATURES+=atm nand ramdisk\nCPU_TYPE:=24kc\n\nDEFAULT_PACKAGES+=kmod-leds-gpio kmod-gpio-button-hotplug swconfig\n\ndefine Target/Description\n\tLantiq XWAY\nendef\n"
  },
  {
    "path": "target/linux/lantiq/xway_legacy/base-files/etc/board.d/01_leds",
    "content": "#\n# Copyright (C) 2011-2015 OpenWrt.org\n#\n\n. /lib/functions/leds.sh\n. /lib/functions/uci-defaults.sh\n\nboard_config_update\n\nled_wifi=\"$(get_dt_led wifi)\"\n[ -n \"$led_wifi\" ] && ucidef_set_led_wlan \"wifi\" \"wifi\" \"$led_wifi\" \"phy0tpt\"\n\nled_usb=\"$(get_dt_led usb)\"\n[ -n \"$led_usb\" ] && ucidef_set_led_usbdev \"usb\" \"usb\" \"$led_usb\" \"1-1\"\n\nled_usb2=\"$(get_dt_led usb2)\"\n[ -n \"$led_usb2\" ] && ucidef_set_led_usbdev \"usb2\" \"usb2\" \"$led_usb2\" \"2-1\"\n\nled_dsl=\"$(get_dt_led dsl)\"\n[ -n \"$led_dsl\" ] && {\n\tled_internet=\"$(get_dt_led internet)\"\n\tif [ -n \"$led_internet\" ]; then\n\t\tucidef_set_led_default \"dsl\" \"dsl\" \"$led_dsl\" \"0\"\n\t\tucidef_set_led_netdev \"internet\" \"internet\" \"$led_internet\" \"pppoe-wan\"\n\telse\n\t\tucidef_set_led_netdev \"dsl\" \"dsl\" \"$led_dsl\" \"dsl0\"\n\tfi\n}\n\nboard=$(board_name)\n\ncase \"$board\" in\narcadyan,arv4525pw)\n\tucidef_set_led_netdev \"wifi\" \"wifi\" \"green:wlan\" \"wlan0\"\n\t;;\nesac\n\nboard_config_flush\n\nexit 0\n"
  },
  {
    "path": "target/linux/lantiq/xway_legacy/base-files/etc/board.d/02_network",
    "content": "#\n# Copyright (C) 2011-2015 OpenWrt.org\n#\n\n. /lib/functions/uci-defaults.sh\n. /lib/functions/system.sh\n. /lib/functions/lantiq.sh\n\nlantiq_setup_interfaces()\n{\n\tlocal board=\"$1\"\n\n\tcase \"$board\" in\n\tarcadyan,arv4520pw)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0:lan:4\" \"1:lan:3\" \"2:lan:2\" \"3:lan:1\" \"5t@eth0\"\n\t\t;;\n\t*)\n\t\tucidef_set_interface_lan 'eth0'\n\t\t;;\n\tesac\n}\n\nlantiq_setup_dsl()\n{\n\tlocal board=\"$1\"\n\tlocal annex=\"a\"\n\n\tcase \"$board\" in\n\tarcadyan,arv4520pw|\\\n\tarcadyan,arv4525pw|\\\n\tarcadyan,arv452cqw)\n\t\tannex=\"b\"\n\t\t;;\n\tesac\n\n\tlantiq_setup_dsl_helper \"$annex\"\n}\n\nlantiq_setup_macs()\n{\n\tlocal board=\"$1\"\n\tlocal lan_mac=\"\"\n\tlocal wan_mac=\"\"\n\n\tcase \"$board\" in\n\tesac\n\n\t[ -n \"$lan_mac\" ] && ucidef_set_interface_macaddr \"lan\" \"$lan_mac\"\n\t[ -n \"$wan_mac\" ] && ucidef_set_interface_macaddr \"wan\" \"$wan_mac\"\n}\n\nboard_config_update\nboard=$(board_name)\nlantiq_setup_interfaces $board\nlantiq_setup_dsl $board\nlantiq_setup_macs $board\nboard_config_flush\n\nexit 0\n"
  },
  {
    "path": "target/linux/lantiq/xway_legacy/base-files/etc/uci-defaults/01_led_migration",
    "content": "#\n# Copyright (C) 2013 OpenWrt.org\n#\n\n. /lib/functions/migrations.sh\n\ndo_internet_led_rename()\n{\n\tconfig_load system\n\n\t[ -n $(config_get led_internet name) ] || return\n\t[ -z $(config_get led_dsl name) ] || return\n\n\tuci rename system.led_internet=led_dsl\n\tuci set system.led_dsl.name=dsl\n\n\tlogger -t led-migration \"internet led renamed to dsl\"\n}\n\ncase \"$(board_name)\" in\narcadyan,arv452cqw)\n\tdo_internet_led_rename\n\t;;\nesac\n\nremove_devicename_leds\n\nmigrations_apply system\n\nexit 0\n"
  },
  {
    "path": "target/linux/lantiq/xway_legacy/base-files/lib/preinit/05_set_preinit_iface_lantiq",
    "content": "set_preinit_iface() {\n\tifname=eth0\n}\n\nboot_hook_add preinit_main set_preinit_iface\n"
  },
  {
    "path": "target/linux/lantiq/xway_legacy/base-files/lib/upgrade/platform.sh",
    "content": "PART_NAME=firmware\nREQUIRE_IMAGE_METADATA=1\n\nplatform_check_image() {\n\treturn 0\n}\n\nplatform_do_upgrade() {\n\tdefault_do_upgrade \"$1\"\n}\n"
  },
  {
    "path": "target/linux/lantiq/xway_legacy/config-5.10",
    "content": "CONFIG_ADM6996_PHY=y\nCONFIG_BLK_MQ_PCI=y\nCONFIG_CPU_HAS_DIEI=y\nCONFIG_CRC16=y\nCONFIG_CRYPTO_ACOMP2=y\nCONFIG_CRYPTO_DEFLATE=y\nCONFIG_CRYPTO_LZO=y\nCONFIG_GENERIC_ALLOCATOR=y\n# CONFIG_GPIO_SYSFS is not set\nCONFIG_INPUT=y\nCONFIG_INPUT_EVDEV=y\nCONFIG_INPUT_POLLDEV=y\n# CONFIG_ISDN is not set\nCONFIG_LANTIQ_ETOP=y\n# CONFIG_LEDS_TRIGGER_TIMER is not set\nCONFIG_LZO_COMPRESS=y\nCONFIG_LZO_DECOMPRESS=y\nCONFIG_NLS=y\nCONFIG_PCI=y\nCONFIG_PCI_DOMAINS=y\nCONFIG_PCI_LANTIQ=y\nCONFIG_REGULATOR=y\nCONFIG_REGULATOR_FIXED_VOLTAGE=y\nCONFIG_RTL8306_PHY=y\nCONFIG_SGL_ALLOC=y\nCONFIG_SOC_TYPE_XWAY=y\nCONFIG_SOC_XWAY=y\nCONFIG_SWCONFIG=y\nCONFIG_USB=y\nCONFIG_USB_COMMON=y\nCONFIG_USB_SUPPORT=y\nCONFIG_ZLIB_DEFLATE=y\nCONFIG_ZLIB_INFLATE=y\n"
  },
  {
    "path": "target/linux/lantiq/xway_legacy/profiles/00-default.mk",
    "content": "define Profile/Default\n\tNAME:=Default Profile\n\tPRIORITY:=1\nendef\n\ndefine Profile/Default/Description\n\tDefault package set compatible with most boards.\nendef\n$(eval $(call Profile,Default))\n"
  },
  {
    "path": "target/linux/lantiq/xway_legacy/target.mk",
    "content": "ARCH:=mips\nSUBTARGET:=xway_legacy\nBOARDNAME:=XWAY Legacy\nFEATURES+=atm ramdisk small_flash\nCPU_TYPE:=24kc\n\nDEFAULT_PACKAGES+=kmod-leds-gpio kmod-gpio-button-hotplug swconfig\n\ndefine Target/Description\n\tLantiq XWAY Legacy for old boards with small flash\nendef\n"
  },
  {
    "path": "target/linux/layerscape/Makefile",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2016 Jiang Yutang <jiangyutang1978@gmail.com>\n\ninclude $(TOPDIR)/rules.mk\n\nBOARD:=layerscape\nBOARDNAME:=NXP Layerscape\nKERNEL_PATCHVER:=5.10\nKERNEL_TESTING_PATCHVER:=5.10\nFEATURES:=squashfs nand usb pcie gpio fpu ubifs ext4 rootfs-part boot-part\nSUBTARGETS:=armv8_64b armv7\n\ndefine Target/Description\n\tBuild firmware images for NXP Layerscape based boards.\nendef\n\ninclude $(INCLUDE_DIR)/target.mk\n\nDEFAULT_PACKAGES += kmod-usb3 kmod-usb-dwc3 kmod-usb-storage \\\n  mkf2fs e2fsprogs partx-utils\n\n$(eval $(call BuildTarget))\n"
  },
  {
    "path": "target/linux/layerscape/README",
    "content": "\nLayerscape Quick Start\n\nThis is a quick start guide for Layerscape specific usage, like introducing\nhow to configure, build, and deploy OpenWrt to Layerscape boards, so that\nusers can bring up the board without difficulty.\n\n\n1. Target support\n----------------------------\n* ARMv8 64-bit\n  LS1012ARDB        (QSPI NOR boot)\n  LS1012AFRDM       (QSPI NOR boot)\n  LS1012AFRWY       (QSPI NOR boot)\n  LS1043ARDB        (NOR boot         | SD card boot)\n  LS1046ARDB        (QSPI NOR boot    | SD card boot)\n  LS1046AFRWY       (QSPI NOR boot    | SD card boot)\n  LS1088ARDB        (QSPI NOR boot    | SD card boot)\n  LS2088ARDB        (NOR boot)\n  LX2160ARDB Rev2.0 (FlexSPI NOR boot | SD card boot)\n\n* ARMv7\n  LS1021ATWR        (NOR boot | SD card boot)\n  LS1021AIOT        (SD card boot)\n\n\n2. Build\n--------\nBefore configuration and build, update and install package feeds.\n\n$ ./scripts/feeds update -a\n$ ./scripts/feeds install -a\n\n* make menuconfig\n  Target System:   \"NXP Layerscape\"\n  Subtarget:       (Select subtarget)\n  Target Profile:  (Select device, or \"Multiple devices\")\n  Target Devices:  (Select devices. Available when Target Profile is \"Multiple devices\")\n  Target Images:   (Disable \"GZip images\" if you don't want to unzip manually to use the images.)\n\n  Note: The first time make menuconfig would create a .config file which\n  would include all dependencies for selected target. After that, make\n  menuconfig still could be used to modify packages. If want to change\n  other target, please remove .config and make menuconfig to select again.\n  Otherwise the packages selected in .config would be a mess.\n\n* make download (or make download -j<n>)\n\n* make (or make -j<n>)\n\n* Final firmware/image\n  Path:               bin/targets/layerscape/<subtarget>/\n  Firmware for flash: openwrt-layerscape-<subtarget>-<device>-<rootfs>-firmware.bin\n  Image for SD card:  openwrt-layerscape-<subtarget>-<device>-<rootfs>-sdcard.img.gz\n  Sysupgrade images:  openwrt-layerscape-<subtarget>-<device>-<rootfs>-sysupgrade.bin\n\n\n3. Deploy\n---------\nThe firmware.bin or sdcard.img is an all-in-one image including all things\nfor OpenWrt staring up except LS1012AFRWY (Refer to 3.3).\nIf you want to install all things into flash, please use firmware.bin.\nIf you want to install all things into SD card, please use sdcard.img.\n\n3.1 Program sdcard.img to SD card\n---------------------------------\nsdcard.img could be programmed to SD card in either u-boot environment\nor linux environment. After programming, configure the board to boot\nfrom SD card. (sdcard.img images are gz-iped to save space. Please extract them first.)\n\n* u-boot environment\n\n  => tftp a0000000 <image_name>-sdcard.img\n  => mmc write a0000000 0 a0000\n\n  Note: The default sdcard.img size is 320MB. a0000 is the block number for 320MB.\n  blk_num = filesize / 512.\n\n* linux environment\n\n  $ dd if=./<image_name>-sdcard.img of=/dev/mmcblkx\n\n  Note: Need to check the SD card device name to replace \"mmcblkx\".\n\n3.2 Program firmware.bin to flash\n---------------------------------\n* LS1012ARDB\n  Start up from bank1, and program firmware to bank2 with below commands.\n  Switch to bank2 to start up OpenWrt.\n\n  => tftp a0000000 <firmware_name>-firmware.bin\n  => i2c mw 0x24 0x7 0xfc;i2c mw 0x24 0x3 0xf5\n  => sf probe 0:0\n  => sf erase 0 +$filesize\n  => sf write a0000000 0 $filesize\n  => reset\n\n* LS1043ARDB\n  Start up from bank0, and program firmware to bank4 with below commands.\n  Switch to bank4 to start up OpenWrt.\n\n  => tftp a0000000 <firmware_name>-firmware.bin\n  => protect off all\n  => erase 64000000 +$filesize\n  => cp.b a0000000 64000000 $filesize\n  => cpld reset altbank\n\n* LS1046ARDB\n  Start up from bank1, and program firmware to bank2 with below commands.\n  Switch to bank2 to start up OpenWrt.\n\n  => tftp a0000000 <firmware_name>-firmware.bin\n  => sf probe 0:1\n  => sf erase 0 +$filesize\n  => sf write a0000000 0 $filesize\n  => cpld reset altbank\n\n* LS2088ARDB\n  Start up from bank0, and program firmware to bank4 with below commands.\n  Switch to bank4 to start up OpenWrt.\n\n  => tftp a0000000 <firmware_name>-firmware.bin\n  => protect off all\n  => erase 584000000 +$filesize\n  => cp.b a0000000 584000000 $filesize\n  => qix altbank\n\n* LS1012FRDM/LS1046AFRWY\n  Board has only one bank. Those commands will replace stock bootloader\n  and firmware.\n\n  => tftp a0000000 <firmware_name>-firmware.bin\n  => sf probe 0:0\n  => sf erase 0 +$filesize\n  => sf write a0000000 0 $filesize\n  => reset\n\n* LS1088ARDB/LX2160ARDB Rev2.0\n  Start up from bank0, and program firmware to bank1 with below commands.\n  Switch to bank1 to start up OpenWrt.\n\n  => tftp a0000000 <firmware_name>-firmware.bin\n  => sf probe 0:1\n  => sf erase 0 +$filesize\n  => sf write a0000000 0 $filesize\n  => qix altbank\n\n  Note: old version u-boot of ls1088ardb may use below commands to switch to\n  bank1 instead of 'qix altbank'.\n  => i2c mw 66 50 20;i2c mw 66 10 20;i2c mw 66 10 21\n\n* LS1021ATWR\n  Start up from bank0, and program firmware to bank4 with below commands.\n  Switch to bank4 to start up OpenWrt.\n\n  => tftp a0000000 <firmware_name>-firmware.bin\n  => protect off all\n  => erase 64000000 +$filesize\n  => cp.b a0000000 64000000 $filesize\n  => boot_bank 1\n\n3.3 Program LS1012AFRWY\n-----------------------\n* LS1012AFRWY (QSPI flash + SD card)\n  LS1012AFRWY only supports 2MB QSPI flash. We have to put u-boot, and\n  some firmwares on QSPI flash, and kernel/dtb/rootfs on SD card.\n  So both firmware.bin and sdcard.img are needed for OpenWrt starting up.\n\n  To program sdcard.img, please use linux command described in 3.1 on a\n  linux machine.\n  To program firmware.bin, start up board from QSPI flash, and program\n  firmware with below commands. Reset to start up OpenWrt. (LS1012AFRWY\n  supports only one bank.)\n\n  => tftp 96000000 <firmware_name>-firmware.bin\n  => sf probe 0:0\n  => sf erase 0 +$filesize\n  => sf write 96000000 0 $filesize\n  => reset\n\n\n4. Known issues and limitation\n------------------------------\n* U-boot may fail to read MAC addresses from EEPROM on some boards and there\n  won't be MAC addresses set in environment. This may cause kernel fails to\n  probe these network interfaces. The workaround is to set MAC addresses\n  manually, for example,\n\n  => setenv ethaddr 00:04:9F:04:65:4b\n  => setenv eth1addr 00:04:9F:04:65:4c\n  => saveenv\n\n* In case users want to refer Layerscape SDK doc for network configuration,\n  like TSN (Time-Sensitive Networking) on LS1028A, the OpenWrt LAN/WAN router\n  setting should be removed before that.\n\n  # ubus call network.interface.lan remove\n  # ubus call network.interface.wan remove\n  # ubus call network.interface.wan6 remove\n\n  And firewall may be needed to stop.\n\n  # /etc/init.d/firewall stop\n\n\n5. Other references\n-------------------\n- NXP LSDK source: https://lsdk.github.io/\n\n- NXP LSDK site: https://www.nxp.com/design/software/embedded-software/linux-software-and-development-tools/layerscape-software-development-kit:LAYERSCAPE-SDK\n\n- OpenWrt documentation: https://openwrt.org/docs/start\n"
  },
  {
    "path": "target/linux/layerscape/armv7/config-5.10",
    "content": "CONFIG_AD525X_DPOT=y\nCONFIG_AD525X_DPOT_I2C=y\n# CONFIG_AD525X_DPOT_SPI is not set\nCONFIG_ALIGNMENT_TRAP=y\nCONFIG_APDS9802ALS=y\nCONFIG_AQUANTIA_PHY=y\nCONFIG_ARCH_32BIT_OFF_T=y\nCONFIG_ARCH_DMA_ADDR_T_64BIT=y\nCONFIG_ARCH_HIBERNATION_POSSIBLE=y\nCONFIG_ARCH_KEEP_MEMBLOCK=y\nCONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y\nCONFIG_ARCH_MULTIPLATFORM=y\nCONFIG_ARCH_MULTI_V6_V7=y\nCONFIG_ARCH_MULTI_V7=y\nCONFIG_ARCH_MXC=y\nCONFIG_ARCH_NR_GPIO=0\nCONFIG_ARCH_OPTIONAL_KERNEL_RWX=y\nCONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y\nCONFIG_ARCH_SELECT_MEMORY_MODEL=y\nCONFIG_ARCH_SPARSEMEM_ENABLE=y\nCONFIG_ARCH_SUSPEND_POSSIBLE=y\nCONFIG_ARM=y\nCONFIG_ARM_APPENDED_DTB=y\nCONFIG_ARM_ARCH_TIMER=y\nCONFIG_ARM_ARCH_TIMER_EVTSTREAM=y\nCONFIG_ARM_ATAG_DTB_COMPAT=y\nCONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y\nCONFIG_ARM_CPUIDLE=y\nCONFIG_ARM_CPU_SUSPEND=y\nCONFIG_ARM_ERRATA_430973=y\nCONFIG_ARM_ERRATA_643719=y\nCONFIG_ARM_ERRATA_720789=y\nCONFIG_ARM_ERRATA_754322=y\nCONFIG_ARM_ERRATA_754327=y\nCONFIG_ARM_ERRATA_764369=y\nCONFIG_ARM_ERRATA_775420=y\nCONFIG_ARM_ERRATA_798181=y\nCONFIG_ARM_GIC=y\nCONFIG_ARM_HAS_SG_CHAIN=y\nCONFIG_ARM_HEAVY_MB=y\n# CONFIG_ARM_HIGHBANK_CPUIDLE is not set\n# CONFIG_ARM_IMX8M_DDRC_DEVFREQ is not set\n# CONFIG_ARM_IMX_BUS_DEVFREQ is not set\n# CONFIG_ARM_IMX_CPUFREQ_DT is not set\nCONFIG_ARM_L1_CACHE_SHIFT=6\nCONFIG_ARM_L1_CACHE_SHIFT_6=y\nCONFIG_ARM_LPAE=y\nCONFIG_ARM_PATCH_IDIV=y\nCONFIG_ARM_PATCH_PHYS_VIRT=y\nCONFIG_ARM_PSCI=y\nCONFIG_ARM_PSCI_FW=y\n# CONFIG_ARM_SMMU is not set\nCONFIG_ARM_THUMB=y\nCONFIG_ARM_THUMBEE=y\nCONFIG_ARM_UNWIND=y\nCONFIG_ARM_VIRT_EXT=y\nCONFIG_ATAGS=y\nCONFIG_AUTOFS4_FS=y\nCONFIG_AUTOFS_FS=y\nCONFIG_AUTO_ZRELADDR=y\nCONFIG_BATTERY_SBS=y\nCONFIG_BCM_NET_PHYLIB=y\nCONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y\nCONFIG_BLK_CMDLINE_PARSER=y\nCONFIG_BLK_DEV_BSG=y\nCONFIG_BLK_DEV_LOOP=y\nCONFIG_BLK_DEV_RAM=y\nCONFIG_BLK_DEV_RAM_COUNT=16\nCONFIG_BLK_DEV_RAM_SIZE=262144\nCONFIG_BLK_DEV_SD=y\nCONFIG_BLK_DEV_SR=y\nCONFIG_BLK_MQ_PCI=y\nCONFIG_BLK_MQ_VIRTIO=y\nCONFIG_BLK_PM=y\nCONFIG_BLK_SCSI_REQUEST=y\nCONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0\nCONFIG_BOUNCE=y\nCONFIG_BRCMSTB_GISB_ARB=y\nCONFIG_BROADCOM_PHY=y\nCONFIG_CACHE_L2X0=y\nCONFIG_CDROM=y\nCONFIG_CHECKPOINT_RESTORE=y\nCONFIG_CHR_DEV_SG=y\nCONFIG_CLKDEV_LOOKUP=y\nCONFIG_CLKSRC_IMX_GPT=y\nCONFIG_CLKSRC_MMIO=y\n# CONFIG_CLK_IMX8MM is not set\n# CONFIG_CLK_IMX8MN is not set\n# CONFIG_CLK_IMX8MP is not set\n# CONFIG_CLK_IMX8MQ is not set\nCONFIG_CLK_QORIQ=y\nCONFIG_CLONE_BACKWARDS=y\nCONFIG_CMA=y\nCONFIG_CMA_ALIGNMENT=8\nCONFIG_CMA_AREAS=7\n# CONFIG_CMA_DEBUG is not set\n# CONFIG_CMA_DEBUGFS is not set\nCONFIG_CMA_SIZE_MBYTES=64\n# CONFIG_CMA_SIZE_SEL_MAX is not set\nCONFIG_CMA_SIZE_SEL_MBYTES=y\n# CONFIG_CMA_SIZE_SEL_MIN is not set\n# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set\nCONFIG_CMDLINE_PARTITION=y\nCONFIG_COMMON_CLK=y\nCONFIG_COMPAT_32BIT_TIME=y\nCONFIG_CONFIGFS_FS=y\nCONFIG_CONSOLE_TRANSLATIONS=y\nCONFIG_CONTIG_ALLOC=y\nCONFIG_COREDUMP=y\nCONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y\nCONFIG_CPUFREQ_DT=y\nCONFIG_CPUFREQ_DT_PLATDEV=y\nCONFIG_CPU_32v6K=y\nCONFIG_CPU_32v7=y\nCONFIG_CPU_ABRT_EV7=y\nCONFIG_CPU_CACHE_V7=y\nCONFIG_CPU_CACHE_VIPT=y\nCONFIG_CPU_COPY_V6=y\nCONFIG_CPU_CP15=y\nCONFIG_CPU_CP15_MMU=y\nCONFIG_CPU_FREQ=y\nCONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y\n# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set\nCONFIG_CPU_FREQ_GOV_ATTR_SET=y\nCONFIG_CPU_FREQ_GOV_COMMON=y\n# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set\nCONFIG_CPU_FREQ_GOV_ONDEMAND=y\nCONFIG_CPU_FREQ_GOV_PERFORMANCE=y\n# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set\nCONFIG_CPU_FREQ_GOV_SCHEDUTIL=y\n# CONFIG_CPU_FREQ_GOV_USERSPACE is not set\nCONFIG_CPU_FREQ_STAT=y\nCONFIG_CPU_HAS_ASID=y\nCONFIG_CPU_IDLE=y\nCONFIG_CPU_IDLE_GOV_MENU=y\nCONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y\nCONFIG_CPU_PABRT_V7=y\nCONFIG_CPU_PM=y\nCONFIG_CPU_RMAP=y\nCONFIG_CPU_SPECTRE=y\nCONFIG_CPU_THERMAL=y\nCONFIG_CPU_THUMB_CAPABLE=y\nCONFIG_CPU_TLB_V7=y\nCONFIG_CPU_V7=y\nCONFIG_CRASH_CORE=y\nCONFIG_CRC16=y\n# CONFIG_CRC32_SARWATE is not set\nCONFIG_CRC32_SLICEBY8=y\nCONFIG_CROSS_MEMORY_ATTACH=y\nCONFIG_CRYPTO_CRC32=y\nCONFIG_CRYPTO_CRC32C=y\nCONFIG_CRYPTO_DEFLATE=y\nCONFIG_CRYPTO_HASH_INFO=y\nCONFIG_CRYPTO_LZO=y\nCONFIG_CRYPTO_RNG2=y\nCONFIG_CRYPTO_ZSTD=y\nCONFIG_DCACHE_WORD_ACCESS=y\nCONFIG_DEBUG_ALIGN_RODATA=y\nCONFIG_DEBUG_BUGVERBOSE=y\nCONFIG_DEBUG_LL_INCLUDE=\"mach/debug-macro.S\"\nCONFIG_DECOMPRESS_BZIP2=y\nCONFIG_DECOMPRESS_GZIP=y\nCONFIG_DECOMPRESS_LZMA=y\nCONFIG_DECOMPRESS_LZO=y\nCONFIG_DECOMPRESS_XZ=y\nCONFIG_DETECT_HUNG_TASK=y\n# CONFIG_DEVFREQ_GOV_PASSIVE is not set\n# CONFIG_DEVFREQ_GOV_PERFORMANCE is not set\n# CONFIG_DEVFREQ_GOV_POWERSAVE is not set\n# CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND is not set\n# CONFIG_DEVFREQ_GOV_USERSPACE is not set\n# CONFIG_DEVFREQ_THERMAL is not set\nCONFIG_DMADEVICES=y\nCONFIG_DMA_CMA=y\nCONFIG_DMA_ENGINE=y\nCONFIG_DMA_OF=y\nCONFIG_DMA_OPS=y\nCONFIG_DMA_REMAP=y\nCONFIG_DMA_SHARED_BUFFER=y\nCONFIG_DMA_VIRTUAL_CHANNELS=y\nCONFIG_DNOTIFY=y\nCONFIG_DTC=y\nCONFIG_DT_IDLE_STATES=y\nCONFIG_DUMMY_CONSOLE=y\nCONFIG_DW_DMAC=y\nCONFIG_DW_DMAC_CORE=y\nCONFIG_DW_WATCHDOG=y\nCONFIG_EDAC_ATOMIC_SCRUB=y\nCONFIG_EDAC_SUPPORT=y\nCONFIG_EEPROM_93CX6=y\nCONFIG_EEPROM_AT24=y\nCONFIG_ELF_CORE=y\n# CONFIG_ENABLE_DEFAULT_TRACERS is not set\nCONFIG_ENABLE_MUST_CHECK=y\nCONFIG_EXT4_FS=y\nCONFIG_EXT4_FS_POSIX_ACL=y\nCONFIG_EXT4_FS_SECURITY=y\nCONFIG_F2FS_FS=y\nCONFIG_FAILOVER=y\nCONFIG_FAT_FS=y\n# CONFIG_FEC is not set\nCONFIG_FHANDLE=y\nCONFIG_FIXED_PHY=y\nCONFIG_FIX_EARLYCON_MEM=y\nCONFIG_FORCE_MAX_ZONEORDER=12\nCONFIG_FREEZER=y\nCONFIG_FSL_EDMA=y\nCONFIG_FSL_GUTS=y\nCONFIG_FSL_IFC=y\n# CONFIG_FSL_PPFE is not set\nCONFIG_FSL_PQ_MDIO=y\nCONFIG_FSL_RCPM=y\nCONFIG_FSL_XGMAC_MDIO=y\nCONFIG_FS_IOMAP=y\nCONFIG_FS_MBCACHE=y\nCONFIG_FS_POSIX_ACL=y\nCONFIG_FTRACE=y\n# CONFIG_FTRACE_SYSCALLS is not set\nCONFIG_FUSE_FS=y\nCONFIG_FW_CACHE=y\nCONFIG_FW_LOADER_PAGED_BUF=y\n# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set\nCONFIG_GENERIC_ALLOCATOR=y\nCONFIG_GENERIC_ARCH_TOPOLOGY=y\nCONFIG_GENERIC_BUG=y\nCONFIG_GENERIC_CLOCKEVENTS=y\nCONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y\nCONFIG_GENERIC_CPU_AUTOPROBE=y\nCONFIG_GENERIC_EARLY_IOREMAP=y\nCONFIG_GENERIC_GETTIMEOFDAY=y\nCONFIG_GENERIC_IDLE_POLL_SETUP=y\nCONFIG_GENERIC_IRQ_CHIP=y\nCONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y\nCONFIG_GENERIC_IRQ_MIGRATION=y\nCONFIG_GENERIC_IRQ_MULTI_HANDLER=y\nCONFIG_GENERIC_IRQ_SHOW=y\nCONFIG_GENERIC_IRQ_SHOW_LEVEL=y\nCONFIG_GENERIC_MSI_IRQ=y\nCONFIG_GENERIC_MSI_IRQ_DOMAIN=y\nCONFIG_GENERIC_PCI_IOMAP=y\nCONFIG_GENERIC_PHY=y\nCONFIG_GENERIC_PINCONF=y\nCONFIG_GENERIC_PINCTRL_GROUPS=y\nCONFIG_GENERIC_PINMUX_FUNCTIONS=y\nCONFIG_GENERIC_SCHED_CLOCK=y\nCONFIG_GENERIC_SMP_IDLE_THREAD=y\nCONFIG_GENERIC_STRNCPY_FROM_USER=y\nCONFIG_GENERIC_STRNLEN_USER=y\nCONFIG_GENERIC_TIME_VSYSCALL=y\nCONFIG_GENERIC_VDSO_32=y\nCONFIG_GIANFAR=y\nCONFIG_GLOB=y\nCONFIG_GPIOLIB=y\nCONFIG_GPIO_GENERIC=y\nCONFIG_GPIO_GENERIC_PLATFORM=y\nCONFIG_GPIO_MPC8XXX=y\nCONFIG_GPIO_MXC=y\nCONFIG_HANDLE_DOMAIN_IRQ=y\nCONFIG_HARDEN_BRANCH_PREDICTOR=y\nCONFIG_HARDIRQS_SW_RESEND=y\nCONFIG_HAS_DMA=y\nCONFIG_HAS_IOMEM=y\nCONFIG_HAS_IOPORT_MAP=y\nCONFIG_HAVE_SMP=y\nCONFIG_HID=y\nCONFIG_HID_GENERIC=y\nCONFIG_HIGHMEM=y\nCONFIG_HIGHPTE=y\nCONFIG_HOTPLUG_CPU=y\nCONFIG_HVC_DRIVER=y\nCONFIG_HW_CONSOLE=y\nCONFIG_HW_RANDOM=y\nCONFIG_HZ_FIXED=0\nCONFIG_I2C=y\nCONFIG_I2C_BOARDINFO=y\nCONFIG_I2C_CHARDEV=y\nCONFIG_I2C_COMPAT=y\nCONFIG_I2C_DEMUX_PINCTRL=y\nCONFIG_I2C_DESIGNWARE_CORE=y\nCONFIG_I2C_DESIGNWARE_PLATFORM=y\nCONFIG_I2C_HELPER_AUTO=y\nCONFIG_I2C_IMX=y\n# CONFIG_I2C_IMX_LPI2C is not set\nCONFIG_I2C_MUX=y\nCONFIG_I2C_MUX_PCA954x=y\nCONFIG_I2C_MUX_PINCTRL=y\nCONFIG_I2C_RK3X=y\nCONFIG_I2C_SLAVE=y\nCONFIG_I2C_SLAVE_EEPROM=y\n# CONFIG_I2C_SLAVE_TESTUNIT is not set\nCONFIG_I2C_XILINX=y\nCONFIG_ICPLUS_PHY=y\nCONFIG_ICS932S401=y\nCONFIG_IKCONFIG=y\nCONFIG_IKCONFIG_PROC=y\nCONFIG_IMX2_WDT=y\n# CONFIG_IMX7ULP_WDT is not set\n# CONFIG_IMX8MM_THERMAL is not set\nCONFIG_IMX_DMA=y\n# CONFIG_IMX_GPCV2_PM_DOMAINS is not set\nCONFIG_IMX_INTMUX=y\n# CONFIG_IMX_IRQSTEER is not set\nCONFIG_IMX_SDMA=y\n# CONFIG_IMX_WEIM is not set\nCONFIG_INITRAMFS_SOURCE=\"\"\nCONFIG_INPUT=y\n# CONFIG_INPUT_MISC is not set\n# CONFIG_IOMMU_DEBUGFS is not set\n# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set\n# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set\nCONFIG_IOMMU_SUPPORT=y\nCONFIG_IPC_NS=y\nCONFIG_IRQCHIP=y\nCONFIG_IRQ_DOMAIN=y\nCONFIG_IRQ_DOMAIN_HIERARCHY=y\nCONFIG_IRQ_FORCED_THREADING=y\nCONFIG_IRQ_WORK=y\n# CONFIG_ISDN is not set\nCONFIG_ISL29003=y\nCONFIG_JBD2=y\nCONFIG_KALLSYMS=y\nCONFIG_KCMP=y\nCONFIG_KERNEL_GZIP=y\n# CONFIG_KERNEL_XZ is not set\nCONFIG_KEXEC=y\nCONFIG_KEXEC_CORE=y\nCONFIG_LIBFDT=y\nCONFIG_LOCALVERSION_AUTO=y\nCONFIG_LOCK_DEBUGGING_SUPPORT=y\nCONFIG_LOCK_SPIN_ON_OWNER=y\nCONFIG_LS_EXTIRQ=y\nCONFIG_LS_SCFG_MSI=y\nCONFIG_LZO_COMPRESS=y\nCONFIG_LZO_DECOMPRESS=y\nCONFIG_MAGIC_SYSRQ=y\nCONFIG_MANDATORY_FILE_LOCKING=y\nCONFIG_MARVELL_PHY=y\nCONFIG_MCPM=y\nCONFIG_MDIO_BITBANG=y\nCONFIG_MDIO_BUS=y\nCONFIG_MDIO_DEVICE=y\nCONFIG_MDIO_DEVRES=y\n# CONFIG_MDIO_GPIO is not set\nCONFIG_MEMFD_CREATE=y\nCONFIG_MEMORY=y\nCONFIG_MEMORY_ISOLATION=y\n# CONFIG_MFD_HI6421_SPMI is not set\nCONFIG_MFD_SYSCON=y\n# CONFIG_MFD_VEXPRESS_SYSREG is not set\nCONFIG_MICREL_PHY=y\nCONFIG_MIGHT_HAVE_CACHE_L2X0=y\nCONFIG_MIGRATION=y\nCONFIG_MMC=y\nCONFIG_MMC_BLOCK=y\nCONFIG_MMC_BLOCK_MINORS=16\n# CONFIG_MMC_MXC is not set\nCONFIG_MMC_SDHCI=y\n# CONFIG_MMC_SDHCI_ESDHC_IMX is not set\nCONFIG_MMC_SDHCI_IO_ACCESSORS=y\nCONFIG_MMC_SDHCI_OF_ESDHC=y\n# CONFIG_MMC_SDHCI_PCI is not set\nCONFIG_MMC_SDHCI_PLTFM=y\nCONFIG_MODULES_USE_ELF_REL=y\nCONFIG_MSDOS_FS=y\nCONFIG_MTD_CFI_ADV_OPTIONS=y\nCONFIG_MTD_CFI_GEOMETRY=y\nCONFIG_MTD_CFI_STAA=y\nCONFIG_MTD_CMDLINE_PARTS=y\n# CONFIG_MTD_COMPLEX_MAPPINGS is not set\nCONFIG_MTD_DATAFLASH=y\n# CONFIG_MTD_DATAFLASH_OTP is not set\n# CONFIG_MTD_DATAFLASH_WRITE_VERIFY is not set\nCONFIG_MTD_NAND_CORE=y\nCONFIG_MTD_NAND_ECC=y\nCONFIG_MTD_NAND_ECC_SW_HAMMING=y\nCONFIG_MTD_NAND_FSL_IFC=y\nCONFIG_MTD_PHYSMAP=y\nCONFIG_MTD_RAW_NAND=y\nCONFIG_MTD_SPI_NOR=y\nCONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y\nCONFIG_MTD_SST25L=y\nCONFIG_MTD_UBI=y\nCONFIG_MTD_UBI_BEB_LIMIT=20\n# CONFIG_MTD_UBI_BLOCK is not set\nCONFIG_MTD_UBI_WL_THRESHOLD=4096\nCONFIG_MUTEX_SPIN_ON_OWNER=y\nCONFIG_MX3_IPU=y\nCONFIG_MX3_IPU_IRQS=4\nCONFIG_MXC_CLK=y\n# CONFIG_MXS_DMA is not set\nCONFIG_NAMESPACES=y\nCONFIG_NATIONAL_PHY=y\nCONFIG_NEED_DMA_MAP_STATE=y\nCONFIG_NEON=y\nCONFIG_NET_FAILOVER=y\nCONFIG_NET_FLOW_LIMIT=y\nCONFIG_NET_NS=y\nCONFIG_NET_PTP_CLASSIFY=y\nCONFIG_NET_SWITCHDEV=y\nCONFIG_NLS=y\nCONFIG_NLS_CODEPAGE_437=y\nCONFIG_NLS_ISO8859_1=y\nCONFIG_NLS_UTF8=y\nCONFIG_NO_HZ=y\nCONFIG_NO_HZ_COMMON=y\nCONFIG_NO_HZ_IDLE=y\nCONFIG_NR_CPUS=16\nCONFIG_NTFS_FS=y\nCONFIG_NVMEM=y\n# CONFIG_NVMEM_IMX_IIM is not set\n# CONFIG_NVMEM_SNVS_LPGPR is not set\n# CONFIG_NVMEM_SPMI_SDAM is not set\nCONFIG_NVMEM_SYSFS=y\nCONFIG_OF=y\nCONFIG_OF_ADDRESS=y\nCONFIG_OF_DYNAMIC=y\nCONFIG_OF_EARLY_FLATTREE=y\nCONFIG_OF_FLATTREE=y\nCONFIG_OF_GPIO=y\nCONFIG_OF_IRQ=y\nCONFIG_OF_KOBJ=y\nCONFIG_OF_MDIO=y\nCONFIG_OF_NET=y\nCONFIG_OLD_SIGACTION=y\nCONFIG_OLD_SIGSUSPEND3=y\nCONFIG_OUTER_CACHE=y\nCONFIG_OUTER_CACHE_SYNC=y\nCONFIG_PACKET_DIAG=y\nCONFIG_PADATA=y\nCONFIG_PAGE_OFFSET=0xC0000000\n# CONFIG_PANIC_ON_OOPS is not set\nCONFIG_PANIC_ON_OOPS_VALUE=0\nCONFIG_PANIC_TIMEOUT=0\nCONFIG_PCI=y\nCONFIG_PCIEAER=y\nCONFIG_PCIEASPM=y\nCONFIG_PCIEASPM_DEFAULT=y\n# CONFIG_PCIEASPM_PERFORMANCE is not set\n# CONFIG_PCIEASPM_POWERSAVE is not set\n# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set\nCONFIG_PCIEPORTBUS=y\nCONFIG_PCIE_DW=y\nCONFIG_PCIE_DW_HOST=y\nCONFIG_PCIE_PME=y\nCONFIG_PCI_DOMAINS=y\nCONFIG_PCI_DOMAINS_GENERIC=y\nCONFIG_PCI_ECAM=y\nCONFIG_PCI_HOST_COMMON=y\nCONFIG_PCI_HOST_GENERIC=y\n# CONFIG_PCI_IMX6 is not set\nCONFIG_PCI_LAYERSCAPE=y\nCONFIG_PCI_MSI=y\nCONFIG_PCI_MSI_IRQ_DOMAIN=y\nCONFIG_PERF_USE_VMALLOC=y\nCONFIG_PGTABLE_LEVELS=3\nCONFIG_PHYLIB=y\nCONFIG_PHYS_ADDR_T_64BIT=y\nCONFIG_PID_NS=y\nCONFIG_PINCTRL=y\n# CONFIG_PINCTRL_IMX8MM is not set\n# CONFIG_PINCTRL_IMX8MN is not set\n# CONFIG_PINCTRL_IMX8MP is not set\n# CONFIG_PINCTRL_IMX8MQ is not set\nCONFIG_PL310_ERRATA_588369=y\nCONFIG_PL310_ERRATA_727915=y\nCONFIG_PL310_ERRATA_753970=y\nCONFIG_PL310_ERRATA_769419=y\nCONFIG_PM=y\nCONFIG_PM_CLK=y\nCONFIG_PM_DEVFREQ=y\n# CONFIG_PM_DEVFREQ_EVENT is not set\nCONFIG_PM_OPP=y\nCONFIG_PM_SLEEP=y\nCONFIG_PM_SLEEP_SMP=y\nCONFIG_POWER_RESET=y\nCONFIG_POWER_RESET_BRCMKONA=y\nCONFIG_POWER_RESET_BRCMSTB=y\nCONFIG_POWER_RESET_GPIO=y\nCONFIG_POWER_RESET_GPIO_RESTART=y\nCONFIG_POWER_RESET_SYSCON=y\nCONFIG_POWER_RESET_SYSCON_POWEROFF=y\nCONFIG_POWER_RESET_VEXPRESS=y\nCONFIG_POWER_SUPPLY=y\nCONFIG_PPS=y\nCONFIG_PRINTK_TIME=y\nCONFIG_PROC_CHILDREN=y\nCONFIG_PROC_PAGE_MONITOR=y\nCONFIG_PSTORE=y\n# CONFIG_PSTORE_842_COMPRESS is not set\nCONFIG_PSTORE_COMPRESS=y\nCONFIG_PSTORE_COMPRESS_DEFAULT=\"deflate\"\nCONFIG_PSTORE_CONSOLE=y\nCONFIG_PSTORE_DEFLATE_COMPRESS=y\nCONFIG_PSTORE_DEFLATE_COMPRESS_DEFAULT=y\n# CONFIG_PSTORE_LZ4HC_COMPRESS is not set\n# CONFIG_PSTORE_LZ4_COMPRESS is not set\n# CONFIG_PSTORE_LZO_COMPRESS is not set\nCONFIG_PSTORE_PMSG=y\nCONFIG_PSTORE_RAM=y\n# CONFIG_PSTORE_ZSTD_COMPRESS is not set\nCONFIG_PTP_1588_CLOCK=y\nCONFIG_PTP_1588_CLOCK_QORIQ=y\nCONFIG_QORIQ_CPUFREQ=y\nCONFIG_RAS=y\nCONFIG_RATIONAL=y\nCONFIG_RD_BZIP2=y\nCONFIG_RD_GZIP=y\nCONFIG_RD_LZMA=y\nCONFIG_RD_LZO=y\nCONFIG_RD_XZ=y\nCONFIG_REALTEK_PHY=y\nCONFIG_REED_SOLOMON=y\nCONFIG_REED_SOLOMON_DEC8=y\nCONFIG_REED_SOLOMON_ENC8=y\nCONFIG_REGMAP=y\nCONFIG_REGMAP_I2C=y\nCONFIG_REGMAP_MMIO=y\nCONFIG_REGMAP_SPI=y\nCONFIG_RESET_CONTROLLER=y\nCONFIG_RFS_ACCEL=y\nCONFIG_RPS=y\nCONFIG_RTC_CLASS=y\n# CONFIG_RTC_DRV_CMOS is not set\nCONFIG_RTC_DRV_DS1307=y\nCONFIG_RTC_DRV_DS3232=y\nCONFIG_RTC_DRV_EM3027=y\nCONFIG_RTC_DRV_FSL_FTM_ALARM=y\n# CONFIG_RTC_DRV_IMXDI is not set\n# CONFIG_RTC_DRV_MXC is not set\n# CONFIG_RTC_DRV_MXC_V2 is not set\nCONFIG_RTC_DRV_PCF2127=y\nCONFIG_RTC_I2C_AND_SPI=y\nCONFIG_RWSEM_SPIN_ON_OWNER=y\nCONFIG_SCHED_DEBUG=y\nCONFIG_SCSI=y\nCONFIG_SECCOMP=y\nCONFIG_SECCOMP_FILTER=y\n# CONFIG_SECURITY_DMESG_RESTRICT is not set\nCONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y\nCONFIG_SERIAL_8250_DW=y\nCONFIG_SERIAL_8250_DWLIB=y\nCONFIG_SERIAL_8250_EM=y\nCONFIG_SERIAL_8250_FSL=y\nCONFIG_SERIAL_8250_NR_UARTS=4\nCONFIG_SERIAL_8250_PCI=y\nCONFIG_SERIAL_8250_RUNTIME_UARTS=4\nCONFIG_SERIAL_BCM63XX=y\nCONFIG_SERIAL_BCM63XX_CONSOLE=y\nCONFIG_SERIAL_CONEXANT_DIGICOLOR=y\nCONFIG_SERIAL_CONEXANT_DIGICOLOR_CONSOLE=y\nCONFIG_SERIAL_FSL_LPUART=y\nCONFIG_SERIAL_FSL_LPUART_CONSOLE=y\nCONFIG_SERIAL_IMX=y\nCONFIG_SERIAL_IMX_CONSOLE=y\nCONFIG_SERIAL_IMX_EARLYCON=y\nCONFIG_SERIAL_MCTRL_GPIO=y\nCONFIG_SERIAL_OF_PLATFORM=y\nCONFIG_SERIAL_ST_ASC=y\nCONFIG_SERIAL_ST_ASC_CONSOLE=y\nCONFIG_SERIAL_XILINX_PS_UART=y\nCONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y\nCONFIG_SGL_ALLOC=y\nCONFIG_SG_POOL=y\nCONFIG_SLUB_DEBUG=y\nCONFIG_SMP=y\nCONFIG_SMP_ON_UP=y\nCONFIG_SMSC_PHY=y\nCONFIG_SOCK_DIAG=y\nCONFIG_SOC_BRCMSTB=y\nCONFIG_SOC_BUS=y\n# CONFIG_SOC_IMX50 is not set\n# CONFIG_SOC_IMX51 is not set\n# CONFIG_SOC_IMX53 is not set\n# CONFIG_SOC_IMX6Q is not set\n# CONFIG_SOC_IMX6SL is not set\n# CONFIG_SOC_IMX6SLL is not set\n# CONFIG_SOC_IMX6SX is not set\n# CONFIG_SOC_IMX6UL is not set\n# CONFIG_SOC_IMX7D is not set\n# CONFIG_SOC_IMX7ULP is not set\n# CONFIG_SOC_IMX8M is not set\nCONFIG_SOC_LS1021A=y\n# CONFIG_SOC_VF610 is not set\nCONFIG_SPARSE_IRQ=y\nCONFIG_SPI=y\nCONFIG_SPI_BITBANG=y\nCONFIG_SPI_CADENCE=y\nCONFIG_SPI_DYNAMIC=y\n# CONFIG_SPI_FSL_LPSPI is not set\n# CONFIG_SPI_FSL_QUADSPI is not set\n# CONFIG_SPI_IMX is not set\nCONFIG_SPI_MASTER=y\nCONFIG_SPI_MEM=y\nCONFIG_SPI_SPIDEV=y\nCONFIG_SPI_XILINX=y\nCONFIG_SPMI=y\n# CONFIG_SPMI_HISI3670 is not set\n# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set\nCONFIG_SQUASHFS_DECOMP_SINGLE=y\nCONFIG_SQUASHFS_FILE_CACHE=y\n# CONFIG_SQUASHFS_FILE_DIRECT is not set\nCONFIG_SQUASHFS_LZO=y\nCONFIG_SQUASHFS_ZLIB=y\nCONFIG_SRAM=y\nCONFIG_SRAM_EXEC=y\nCONFIG_SRCU=y\nCONFIG_STACKTRACE=y\nCONFIG_STAGING_BOARD=y\n# CONFIG_STRIP_ASM_SYMS is not set\nCONFIG_SUSPEND=y\nCONFIG_SUSPEND_FREEZER=y\nCONFIG_SWIOTLB=y\nCONFIG_SWPHY=y\nCONFIG_SWP_EMULATE=y\nCONFIG_SYNC_FILE=y\nCONFIG_SYSFS_SYSCALL=y\nCONFIG_SYS_SUPPORTS_APM_EMULATION=y\nCONFIG_SYS_SUPPORTS_HUGETLBFS=y\nCONFIG_THERMAL=y\nCONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y\nCONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0\nCONFIG_THERMAL_GOV_STEP_WISE=y\nCONFIG_THERMAL_OF=y\nCONFIG_TICK_CPU_ACCOUNTING=y\nCONFIG_TIMER_OF=y\nCONFIG_TIMER_PROBE=y\nCONFIG_TMPFS_POSIX_ACL=y\nCONFIG_TREE_RCU=y\nCONFIG_TREE_SRCU=y\nCONFIG_UBIFS_FS=y\n# CONFIG_UCLAMP_TASK is not set\nCONFIG_UEVENT_HELPER_PATH=\"\"\nCONFIG_UNCOMPRESS_INCLUDE=\"debug/uncompress.h\"\nCONFIG_UNIX_DIAG=y\nCONFIG_UNWINDER_ARM=y\nCONFIG_USB_SUPPORT=y\nCONFIG_USER_NS=y\nCONFIG_USE_OF=y\nCONFIG_UTS_NS=y\nCONFIG_VEXPRESS_CONFIG=y\nCONFIG_VFAT_FS=y\nCONFIG_VFP=y\nCONFIG_VFPv3=y\nCONFIG_VIRTIO=y\nCONFIG_VIRTIO_BLK=y\nCONFIG_VIRTIO_CONSOLE=y\nCONFIG_VIRTIO_MMIO=y\nCONFIG_VIRTIO_NET=y\nCONFIG_VIRTIO_PCI=y\nCONFIG_VIRTIO_PCI_LEGACY=y\nCONFIG_VITESSE_PHY=y\nCONFIG_VM_EVENT_COUNTERS=y\nCONFIG_VT=y\nCONFIG_VT_CONSOLE=y\nCONFIG_VT_CONSOLE_SLEEP=y\nCONFIG_VT_HW_CONSOLE_BINDING=y\nCONFIG_WATCHDOG_CORE=y\n# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set\nCONFIG_XILINX_WATCHDOG=y\nCONFIG_XPS=y\nCONFIG_XXHASH=y\nCONFIG_XZ_DEC_ARM=y\nCONFIG_XZ_DEC_ARMTHUMB=y\nCONFIG_XZ_DEC_BCJ=y\nCONFIG_XZ_DEC_IA64=y\nCONFIG_XZ_DEC_POWERPC=y\nCONFIG_XZ_DEC_SPARC=y\nCONFIG_XZ_DEC_X86=y\nCONFIG_ZBOOT_ROM_BSS=0\nCONFIG_ZBOOT_ROM_TEXT=0\nCONFIG_ZLIB_DEFLATE=y\nCONFIG_ZLIB_INFLATE=y\nCONFIG_ZSTD_COMPRESS=y\nCONFIG_ZSTD_DECOMPRESS=y\n"
  },
  {
    "path": "target/linux/layerscape/armv7/target.mk",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright 2018 NXP\n\nARCH:=arm\nBOARDNAME:=ARMv7 based boards\nCPU_TYPE:=cortex-a7\nCPU_SUBTYPE:=neon-vfpv4\nKERNELNAME:=zImage dtbs\n\ndefine Target/Description\n\tBuild firmware images for NXP Layerscape ARMv7 based boards.\nendef\n"
  },
  {
    "path": "target/linux/layerscape/armv8_64b/config-5.10",
    "content": "CONFIG_64BIT=y\nCONFIG_AQUANTIA_PHY=y\nCONFIG_ARCH_DMA_ADDR_T_64BIT=y\nCONFIG_ARCH_HIBERNATION_HEADER=y\nCONFIG_ARCH_HIBERNATION_POSSIBLE=y\nCONFIG_ARCH_KEEP_MEMBLOCK=y\nCONFIG_ARCH_LAYERSCAPE=y\nCONFIG_ARCH_MMAP_RND_BITS=18\nCONFIG_ARCH_MMAP_RND_BITS_MAX=33\nCONFIG_ARCH_MMAP_RND_BITS_MIN=18\nCONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11\nCONFIG_ARCH_PROC_KCORE_TEXT=y\nCONFIG_ARCH_SELECT_MEMORY_MODEL=y\nCONFIG_ARCH_SPARSEMEM_DEFAULT=y\nCONFIG_ARCH_SPARSEMEM_ENABLE=y\nCONFIG_ARCH_STACKWALK=y\nCONFIG_ARCH_SUSPEND_POSSIBLE=y\nCONFIG_ARM64=y\nCONFIG_ARM64_4K_PAGES=y\nCONFIG_ARM64_CNP=y\nCONFIG_ARM64_ERRATUM_1165522=y\nCONFIG_ARM64_ERRATUM_1286807=y\nCONFIG_ARM64_ERRATUM_819472=y\nCONFIG_ARM64_ERRATUM_824069=y\nCONFIG_ARM64_ERRATUM_826319=y\nCONFIG_ARM64_ERRATUM_827319=y\nCONFIG_ARM64_ERRATUM_832075=y\nCONFIG_ARM64_ERRATUM_843419=y\nCONFIG_ARM64_HW_AFDBM=y\nCONFIG_ARM64_MODULE_PLTS=y\nCONFIG_ARM64_PAGE_SHIFT=12\nCONFIG_ARM64_PAN=y\nCONFIG_ARM64_PA_BITS=48\nCONFIG_ARM64_PA_BITS_48=y\nCONFIG_ARM64_PTR_AUTH=y\nCONFIG_ARM64_SVE=y\nCONFIG_ARM64_TAGGED_ADDR_ABI=y\nCONFIG_ARM64_UAO=y\nCONFIG_ARM64_VA_BITS=48\n# CONFIG_ARM64_VA_BITS_39 is not set\nCONFIG_ARM64_VA_BITS_48=y\nCONFIG_ARM64_VHE=y\nCONFIG_ARM64_WORKAROUND_CLEAN_CACHE=y\nCONFIG_ARM64_WORKAROUND_REPEAT_TLBI=y\nCONFIG_ARM64_WORKAROUND_SPECULATIVE_AT=y\nCONFIG_ARM_AMBA=y\nCONFIG_ARM_ARCH_TIMER=y\nCONFIG_ARM_ARCH_TIMER_EVTSTREAM=y\nCONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y\nCONFIG_ARM_CPUIDLE=y\nCONFIG_ARM_GIC=y\nCONFIG_ARM_GIC_V2M=y\nCONFIG_ARM_GIC_V3=y\nCONFIG_ARM_GIC_V3_ITS=y\nCONFIG_ARM_GIC_V3_ITS_FSL_MC=y\nCONFIG_ARM_GIC_V3_ITS_PCI=y\n# CONFIG_ARM_PL172_MPMC is not set\nCONFIG_ARM_PSCI_CPUIDLE=y\nCONFIG_ARM_PSCI_FW=y\nCONFIG_ARM_SMMU=y\n# CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT is not set\n# CONFIG_ARM_SMMU_LEGACY_DT_BINDINGS is not set\nCONFIG_ARM_SMMU_V3=y\n# CONFIG_ARM_SMMU_V3_SVA is not set\nCONFIG_ARM_SP805_WATCHDOG=y\nCONFIG_ASM_MODVERSIONS=y\nCONFIG_ASN1=y\nCONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH=y\nCONFIG_ATA=y\nCONFIG_AUDIT=y\nCONFIG_AUDITSYSCALL=y\nCONFIG_AUDIT_ARCH_COMPAT_GENERIC=y\nCONFIG_AUDIT_GENERIC=y\nCONFIG_AUTOFS4_FS=y\nCONFIG_AUTOFS_FS=y\nCONFIG_BACKLIGHT_CLASS_DEVICE=y\nCONFIG_BALLOON_COMPACTION=y\nCONFIG_BATTERY_BQ27XXX=y\n# CONFIG_BATTERY_BQ27XXX_DT_UPDATES_NVM is not set\nCONFIG_BATTERY_BQ27XXX_I2C=y\nCONFIG_BLK_DEV_BSG=y\nCONFIG_BLK_DEV_BSGLIB=y\nCONFIG_BLK_DEV_INTEGRITY=y\nCONFIG_BLK_DEV_INTEGRITY_T10=y\nCONFIG_BLK_DEV_LOOP=y\nCONFIG_BLK_DEV_RAM=y\nCONFIG_BLK_DEV_RAM_COUNT=16\nCONFIG_BLK_DEV_RAM_SIZE=262144\nCONFIG_BLK_DEV_SD=y\nCONFIG_BLK_MQ_PCI=y\nCONFIG_BLK_MQ_VIRTIO=y\nCONFIG_BLK_PM=y\nCONFIG_BLK_SCSI_REQUEST=y\nCONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0\nCONFIG_BSD_PROCESS_ACCT=y\nCONFIG_BSD_PROCESS_ACCT_V3=y\nCONFIG_BTRFS_FS=y\n# CONFIG_BTRFS_FS_CHECK_INTEGRITY is not set\nCONFIG_BTRFS_FS_POSIX_ACL=y\nCONFIG_CAVIUM_ERRATUM_22375=y\nCONFIG_CAVIUM_ERRATUM_23144=y\nCONFIG_CAVIUM_ERRATUM_23154=y\nCONFIG_CAVIUM_ERRATUM_27456=y\nCONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y\nCONFIG_CHECKPOINT_RESTORE=y\nCONFIG_CHROME_PLATFORMS=y\nCONFIG_CLKDEV_LOOKUP=y\nCONFIG_CLK_LS1028A_PLLDIG=y\nCONFIG_CLK_QORIQ=y\nCONFIG_CLONE_BACKWARDS=y\nCONFIG_CLZ_TAB=y\nCONFIG_CMA=y\nCONFIG_CMA_ALIGNMENT=8\nCONFIG_CMA_AREAS=7\n# CONFIG_CMA_DEBUG is not set\n# CONFIG_CMA_DEBUGFS is not set\nCONFIG_CMA_SIZE_MBYTES=16\n# CONFIG_CMA_SIZE_SEL_MAX is not set\nCONFIG_CMA_SIZE_SEL_MBYTES=y\n# CONFIG_CMA_SIZE_SEL_MIN is not set\n# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set\nCONFIG_COMMON_CLK=y\nCONFIG_COMMON_CLK_CS2000_CP=y\n# CONFIG_COMMON_CLK_FSL_SAI is not set\nCONFIG_COMMON_CLK_XGENE=y\nCONFIG_COMPAT_32BIT_TIME=y\nCONFIG_CONFIGFS_FS=y\nCONFIG_CONSOLE_TRANSLATIONS=y\nCONFIG_CONTIG_ALLOC=y\nCONFIG_COREDUMP=y\nCONFIG_CPUFREQ_DT=y\nCONFIG_CPUFREQ_DT_PLATDEV=y\nCONFIG_CPU_FREQ=y\n# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set\nCONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y\nCONFIG_CPU_FREQ_GOV_ATTR_SET=y\nCONFIG_CPU_FREQ_GOV_COMMON=y\nCONFIG_CPU_FREQ_GOV_CONSERVATIVE=y\nCONFIG_CPU_FREQ_GOV_ONDEMAND=y\nCONFIG_CPU_FREQ_GOV_PERFORMANCE=y\nCONFIG_CPU_FREQ_GOV_POWERSAVE=y\nCONFIG_CPU_FREQ_GOV_SCHEDUTIL=y\nCONFIG_CPU_FREQ_GOV_USERSPACE=y\nCONFIG_CPU_FREQ_STAT=y\nCONFIG_CPU_FREQ_THERMAL=y\nCONFIG_CPU_IDLE=y\nCONFIG_CPU_IDLE_GOV_MENU=y\nCONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y\nCONFIG_CPU_PM=y\nCONFIG_CPU_RMAP=y\nCONFIG_CPU_THERMAL=y\nCONFIG_CRASH_CORE=y\nCONFIG_CRC16=y\n# CONFIG_CRC32_SARWATE is not set\nCONFIG_CRC32_SLICEBY8=y\nCONFIG_CRC7=y\nCONFIG_CRC_ITU_T=y\nCONFIG_CRC_T10DIF=y\nCONFIG_CROSS_MEMORY_ATTACH=y\n# CONFIG_CROS_EC is not set\nCONFIG_CRYPTO_AUTHENC=y\nCONFIG_CRYPTO_BLAKE2B=y\nCONFIG_CRYPTO_CRC32=y\nCONFIG_CRYPTO_CRC32C=y\nCONFIG_CRYPTO_CRCT10DIF=y\nCONFIG_CRYPTO_DEFLATE=y\nCONFIG_CRYPTO_DES=y\nCONFIG_CRYPTO_DEV_FSL_CAAM=y\nCONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API=y\nCONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API_DESC=y\nCONFIG_CRYPTO_DEV_FSL_CAAM_COMMON=y\nCONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API=y\nCONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API_DESC=y\nCONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API_QI=y\n# CONFIG_CRYPTO_DEV_FSL_CAAM_DEBUG is not set\n# CONFIG_CRYPTO_DEV_FSL_CAAM_INTC is not set\nCONFIG_CRYPTO_DEV_FSL_CAAM_JR=y\nCONFIG_CRYPTO_DEV_FSL_CAAM_PKC_API=y\nCONFIG_CRYPTO_DEV_FSL_CAAM_RINGSIZE=9\nCONFIG_CRYPTO_DEV_FSL_CAAM_RNG_API=y\nCONFIG_CRYPTO_DEV_FSL_DPAA2_CAAM=y\nCONFIG_CRYPTO_ECB=y\nCONFIG_CRYPTO_ENGINE=y\nCONFIG_CRYPTO_HASH_INFO=y\nCONFIG_CRYPTO_HW=y\nCONFIG_CRYPTO_LIB_DES=y\nCONFIG_CRYPTO_LIB_SHA256=y\nCONFIG_CRYPTO_LZO=y\nCONFIG_CRYPTO_RNG=y\nCONFIG_CRYPTO_RNG2=y\nCONFIG_CRYPTO_RSA=y\nCONFIG_CRYPTO_SHA256=y\nCONFIG_CRYPTO_XTS=y\nCONFIG_CRYPTO_XXHASH=y\nCONFIG_CRYPTO_ZSTD=y\nCONFIG_DCACHE_WORD_ACCESS=y\nCONFIG_DEBUG_BUGVERBOSE=y\nCONFIG_DEBUG_INFO=y\n# CONFIG_DEBUG_INFO_REDUCED is not set\nCONFIG_DEBUG_MEMORY_INIT=y\nCONFIG_DECOMPRESS_BZIP2=y\nCONFIG_DECOMPRESS_GZIP=y\nCONFIG_DECOMPRESS_LZMA=y\nCONFIG_DECOMPRESS_LZO=y\nCONFIG_DECOMPRESS_XZ=y\nCONFIG_DETECT_HUNG_TASK=y\nCONFIG_DIMLIB=y\nCONFIG_DMADEVICES=y\nCONFIG_DMATEST=y\nCONFIG_DMA_CMA=y\nCONFIG_DMA_DIRECT_REMAP=y\nCONFIG_DMA_ENGINE=y\nCONFIG_DMA_ENGINE_RAID=y\nCONFIG_DMA_OF=y\nCONFIG_DMA_OPS=y\nCONFIG_DMA_REMAP=y\nCONFIG_DMA_SHARED_BUFFER=y\nCONFIG_DMA_VIRTUAL_CHANNELS=y\nCONFIG_DNOTIFY=y\nCONFIG_DPAA2_CONSOLE=y\nCONFIG_DPAA_ERRATUM_A050385=y\nCONFIG_DTC=y\nCONFIG_DT_IDLE_STATES=y\nCONFIG_DUMMY_CONSOLE=y\nCONFIG_EDAC_SUPPORT=y\nCONFIG_EEPROM_AT24=y\nCONFIG_ELF_CORE=y\n# CONFIG_EMBEDDED is not set\nCONFIG_ENABLE_MUST_CHECK=y\nCONFIG_EXT4_FS=y\nCONFIG_EXT4_FS_POSIX_ACL=y\nCONFIG_EXT4_FS_SECURITY=y\nCONFIG_EXTCON=y\nCONFIG_EXTCON_USB_GPIO=y\nCONFIG_F2FS_FS=y\nCONFIG_FAILOVER=y\nCONFIG_FANOTIFY=y\nCONFIG_FAT_FS=y\nCONFIG_FB=y\nCONFIG_FB_ARMCLCD=y\nCONFIG_FB_CFB_COPYAREA=y\nCONFIG_FB_CFB_FILLRECT=y\nCONFIG_FB_CFB_IMAGEBLIT=y\nCONFIG_FB_CMDLINE=y\nCONFIG_FB_DEFERRED_IO=y\nCONFIG_FB_MODE_HELPERS=y\nCONFIG_FB_SYS_COPYAREA=y\nCONFIG_FB_SYS_FILLRECT=y\nCONFIG_FB_SYS_FOPS=y\nCONFIG_FB_SYS_IMAGEBLIT=y\nCONFIG_FHANDLE=y\nCONFIG_FIXED_PHY=y\nCONFIG_FIX_EARLYCON_MEM=y\nCONFIG_FONT_8x16=y\nCONFIG_FONT_8x8=y\nCONFIG_FONT_SUPPORT=y\nCONFIG_FRAMEBUFFER_CONSOLE=y\nCONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y\n# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set\nCONFIG_FRAME_POINTER=y\nCONFIG_FRAME_WARN=2048\nCONFIG_FREEZER=y\n# CONFIG_FSL_BMAN_TEST is not set\nCONFIG_FSL_DPAA=y\nCONFIG_FSL_DPAA2=y\nCONFIG_FSL_DPAA2_ETH=y\nCONFIG_FSL_DPAA2_ETHSW=y\nCONFIG_FSL_DPAA2_PTP_CLOCK=y\n# CONFIG_FSL_DPAA2_QDMA is not set\n# CONFIG_FSL_DPAA_CHECKING is not set\nCONFIG_FSL_DPAA_ETH=y\nCONFIG_FSL_EDMA=y\nCONFIG_FSL_ENETC=y\nCONFIG_FSL_ENETC_MDIO=y\nCONFIG_FSL_ENETC_PTP_CLOCK=y\nCONFIG_FSL_ENETC_VF=y\nCONFIG_FSL_ERRATUM_A008585=y\nCONFIG_FSL_FMAN=y\nCONFIG_FSL_GUTS=y\nCONFIG_FSL_IFC=y\nCONFIG_FSL_MC_BUS=y\nCONFIG_FSL_MC_DPIO=y\nCONFIG_FSL_PPFE=y\nCONFIG_FSL_PPFE_UTIL_DISABLED=y\n# CONFIG_FSL_QMAN_TEST is not set\nCONFIG_FSL_RCPM=y\nCONFIG_FSL_XGMAC_MDIO=y\nCONFIG_FS_IOMAP=y\nCONFIG_FS_MBCACHE=y\nCONFIG_FS_POSIX_ACL=y\nCONFIG_FUSE_FS=y\nCONFIG_FW_CACHE=y\nCONFIG_FW_LOADER_PAGED_BUF=y\n# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set\nCONFIG_GARP=y\nCONFIG_GENERIC_ALLOCATOR=y\nCONFIG_GENERIC_ARCH_TOPOLOGY=y\nCONFIG_GENERIC_BUG=y\nCONFIG_GENERIC_BUG_RELATIVE_POINTERS=y\nCONFIG_GENERIC_CLOCKEVENTS=y\nCONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y\nCONFIG_GENERIC_CPU_AUTOPROBE=y\nCONFIG_GENERIC_CPU_VULNERABILITIES=y\nCONFIG_GENERIC_CSUM=y\nCONFIG_GENERIC_EARLY_IOREMAP=y\nCONFIG_GENERIC_GETTIMEOFDAY=y\nCONFIG_GENERIC_IDLE_POLL_SETUP=y\nCONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y\nCONFIG_GENERIC_IRQ_MIGRATION=y\nCONFIG_GENERIC_IRQ_MULTI_HANDLER=y\nCONFIG_GENERIC_IRQ_SHOW=y\nCONFIG_GENERIC_IRQ_SHOW_LEVEL=y\nCONFIG_GENERIC_MSI_IRQ=y\nCONFIG_GENERIC_MSI_IRQ_DOMAIN=y\nCONFIG_GENERIC_PCI_IOMAP=y\nCONFIG_GENERIC_PHY=y\nCONFIG_GENERIC_SCHED_CLOCK=y\nCONFIG_GENERIC_SMP_IDLE_THREAD=y\nCONFIG_GENERIC_STRNCPY_FROM_USER=y\nCONFIG_GENERIC_STRNLEN_USER=y\nCONFIG_GENERIC_TIME_VSYSCALL=y\n# CONFIG_GIANFAR is not set\nCONFIG_GLOB=y\nCONFIG_GPIOLIB=y\nCONFIG_GPIOLIB_IRQCHIP=y\nCONFIG_GPIO_GENERIC=y\nCONFIG_GPIO_GENERIC_PLATFORM=y\nCONFIG_GPIO_MPC8XXX=y\nCONFIG_GPIO_PCA953X=y\nCONFIG_GPIO_PCA953X_IRQ=y\nCONFIG_HANDLE_DOMAIN_IRQ=y\nCONFIG_HARDIRQS_SW_RESEND=y\nCONFIG_HAS_DMA=y\nCONFIG_HAS_IOMEM=y\nCONFIG_HAS_IOPORT_MAP=y\nCONFIG_HIBERNATE_CALLBACKS=y\nCONFIG_HIBERNATION=y\nCONFIG_HIBERNATION_SNAPSHOT_DEV=y\nCONFIG_HID=y\nCONFIG_HID_A4TECH=y\nCONFIG_HID_APPLE=y\nCONFIG_HID_BELKIN=y\nCONFIG_HID_CHERRY=y\nCONFIG_HID_CHICONY=y\nCONFIG_HID_CYPRESS=y\nCONFIG_HID_EZKEY=y\nCONFIG_HID_GENERIC=y\nCONFIG_HID_KENSINGTON=y\nCONFIG_HID_LOGITECH=y\nCONFIG_HID_MICROSOFT=y\nCONFIG_HID_MONTEREY=y\nCONFIG_HOLES_IN_ZONE=y\nCONFIG_HOTPLUG_CPU=y\nCONFIG_HUGETLBFS=y\nCONFIG_HUGETLB_PAGE=y\nCONFIG_HVC_DRIVER=y\nCONFIG_HVC_IRQ=y\nCONFIG_HVC_XEN=y\nCONFIG_HVC_XEN_FRONTEND=y\nCONFIG_HW_CONSOLE=y\nCONFIG_HW_RANDOM=y\nCONFIG_I2C=y\nCONFIG_I2C_BOARDINFO=y\nCONFIG_I2C_CHARDEV=y\nCONFIG_I2C_COMPAT=y\nCONFIG_I2C_DESIGNWARE_CORE=y\nCONFIG_I2C_DESIGNWARE_PLATFORM=y\nCONFIG_I2C_HELPER_AUTO=y\nCONFIG_I2C_IMX=y\nCONFIG_I2C_MUX=y\nCONFIG_I2C_MUX_PCA954x=y\nCONFIG_I2C_RK3X=y\nCONFIG_I2C_SLAVE=y\n# CONFIG_I2C_SLAVE_TESTUNIT is not set\nCONFIG_IKCONFIG=y\nCONFIG_IKCONFIG_PROC=y\nCONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000\nCONFIG_IMX2_WDT=y\nCONFIG_INET_DIAG=y\n# CONFIG_INET_DIAG_DESTROY is not set\n# CONFIG_INET_RAW_DIAG is not set\nCONFIG_INET_TCP_DIAG=y\nCONFIG_INITRAMFS_SOURCE=\"\"\nCONFIG_INPUT=y\nCONFIG_INPUT_EVDEV=y\nCONFIG_INPUT_FF_MEMLESS=y\nCONFIG_INPUT_KEYBOARD=y\nCONFIG_INPUT_MOUSE=y\nCONFIG_INPUT_MOUSEDEV=y\nCONFIG_INPUT_MOUSEDEV_PSAUX=y\nCONFIG_INPUT_MOUSEDEV_SCREEN_X=1024\nCONFIG_INPUT_MOUSEDEV_SCREEN_Y=768\nCONFIG_INPUT_XEN_KBDDEV_FRONTEND=y\nCONFIG_INTERVAL_TREE=y\nCONFIG_IOMMU_API=y\n# CONFIG_IOMMU_DEBUGFS is not set\nCONFIG_IOMMU_DEFAULT_PASSTHROUGH=y\nCONFIG_IOMMU_DMA=y\nCONFIG_IOMMU_IOVA=y\nCONFIG_IOMMU_IO_PGTABLE=y\n# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set\nCONFIG_IOMMU_IO_PGTABLE_LPAE=y\n# CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST is not set\nCONFIG_IOMMU_SUPPORT=y\nCONFIG_IPC_NS=y\nCONFIG_IRQCHIP=y\nCONFIG_IRQ_BYPASS_MANAGER=y\nCONFIG_IRQ_DOMAIN=y\nCONFIG_IRQ_DOMAIN_HIERARCHY=y\nCONFIG_IRQ_FORCED_THREADING=y\nCONFIG_IRQ_MSI_IOMMU=y\nCONFIG_IRQ_WORK=y\n# CONFIG_ISDN is not set\nCONFIG_JBD2=y\nCONFIG_JUMP_LABEL=y\nCONFIG_KALLSYMS=y\nCONFIG_KALLSYMS_ALL=y\nCONFIG_KCMP=y\nCONFIG_KEXEC=y\nCONFIG_KEXEC_CORE=y\nCONFIG_KEYBOARD_ATKBD=y\nCONFIG_KEYBOARD_GPIO=y\nCONFIG_KSM=y\nCONFIG_LIBCRC32C=y\nCONFIG_LIBFDT=y\nCONFIG_LOCALVERSION_AUTO=y\nCONFIG_LOCK_DEBUGGING_SUPPORT=y\nCONFIG_LOCK_SPIN_ON_OWNER=y\nCONFIG_LOGO=y\nCONFIG_LOGO_LINUX_CLUT224=y\n# CONFIG_LOGO_LINUX_MONO is not set\n# CONFIG_LOGO_LINUX_VGA16 is not set\nCONFIG_LS_EXTIRQ=y\nCONFIG_LS_SCFG_MSI=y\nCONFIG_LZO_COMPRESS=y\nCONFIG_LZO_DECOMPRESS=y\nCONFIG_MAGIC_SYSRQ=y\nCONFIG_MANDATORY_FILE_LOCKING=y\nCONFIG_MDIO_BITBANG=y\nCONFIG_MDIO_BUS=y\nCONFIG_MDIO_BUS_MUX=y\nCONFIG_MDIO_BUS_MUX_MMIOREG=y\nCONFIG_MDIO_BUS_MUX_MULTIPLEXER=y\nCONFIG_MDIO_DEVICE=y\nCONFIG_MDIO_DEVRES=y\n# CONFIG_MDIO_GPIO is not set\nCONFIG_MEMFD_CREATE=y\nCONFIG_MEMORY=y\nCONFIG_MEMORY_BALLOON=y\nCONFIG_MEMORY_ISOLATION=y\nCONFIG_MEMTEST=y\n# CONFIG_MFD_HI6421_SPMI is not set\nCONFIG_MFD_SYSCON=y\n# CONFIG_MFD_VEXPRESS_SYSREG is not set\nCONFIG_MICREL_PHY=y\nCONFIG_MICROSEMI_PHY=y\nCONFIG_MIGRATION=y\nCONFIG_MMC=y\nCONFIG_MMC_BLOCK=y\nCONFIG_MMC_BLOCK_MINORS=32\nCONFIG_MMC_SDHCI=y\nCONFIG_MMC_SDHCI_IO_ACCESSORS=y\nCONFIG_MMC_SDHCI_OF_ESDHC=y\n# CONFIG_MMC_SDHCI_PCI is not set\nCONFIG_MMC_SDHCI_PLTFM=y\nCONFIG_MMU_NOTIFIER=y\nCONFIG_MODULES_USE_ELF_RELA=y\nCONFIG_MODULE_FORCE_LOAD=y\nCONFIG_MODVERSIONS=y\n# CONFIG_MOUSE_BCM5974 is not set\n# CONFIG_MOUSE_CYAPA is not set\nCONFIG_MOUSE_PS2=y\nCONFIG_MOUSE_PS2_ALPS=y\nCONFIG_MOUSE_PS2_BYD=y\nCONFIG_MOUSE_PS2_CYPRESS=y\n# CONFIG_MOUSE_PS2_ELANTECH is not set\nCONFIG_MOUSE_PS2_FOCALTECH=y\nCONFIG_MOUSE_PS2_LOGIPS2PP=y\nCONFIG_MOUSE_PS2_SMBUS=y\nCONFIG_MOUSE_PS2_SYNAPTICS=y\nCONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y\n# CONFIG_MOUSE_PS2_TOUCHKIT is not set\nCONFIG_MOUSE_PS2_TRACKPOINT=y\n# CONFIG_MOUSE_SERIAL is not set\n# CONFIG_MOUSE_VSXXXAA is not set\nCONFIG_MPILIB=y\nCONFIG_MRP=y\nCONFIG_MTD_CFI_ADV_OPTIONS=y\n# CONFIG_MTD_CFI_GEOMETRY is not set\nCONFIG_MTD_CFI_STAA=y\nCONFIG_MTD_CMDLINE_PARTS=y\n# CONFIG_MTD_COMPLEX_MAPPINGS is not set\nCONFIG_MTD_DATAFLASH=y\n# CONFIG_MTD_DATAFLASH_OTP is not set\n# CONFIG_MTD_DATAFLASH_WRITE_VERIFY is not set\nCONFIG_MTD_NAND_CORE=y\nCONFIG_MTD_NAND_ECC=y\nCONFIG_MTD_NAND_ECC_SW_HAMMING=y\nCONFIG_MTD_NAND_FSL_IFC=y\nCONFIG_MTD_PHYSMAP=y\nCONFIG_MTD_RAW_NAND=y\nCONFIG_MTD_SPI_NOR=y\nCONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y\nCONFIG_MTD_SPI_NOR_USE_4K_SECTORS_LIMIT=16384\nCONFIG_MTD_SPLIT_FIRMWARE=y\nCONFIG_MTD_SPLIT_FIT_FW=y\nCONFIG_MTD_SST25L=y\nCONFIG_MTD_UBI=y\nCONFIG_MTD_UBI_BEB_LIMIT=20\n# CONFIG_MTD_UBI_BLOCK is not set\nCONFIG_MTD_UBI_WL_THRESHOLD=4096\nCONFIG_MULTIPLEXER=y\nCONFIG_MUTEX_SPIN_ON_OWNER=y\n# CONFIG_MUX_ADG792A is not set\n# CONFIG_MUX_ADGS1408 is not set\n# CONFIG_MUX_GPIO is not set\nCONFIG_MUX_MMIO=y\nCONFIG_MV_XOR_V2=y\nCONFIG_NAMESPACES=y\nCONFIG_NEED_DMA_MAP_STATE=y\nCONFIG_NEED_MULTIPLE_NODES=y\nCONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK=y\nCONFIG_NEED_SG_DMA_LENGTH=y\nCONFIG_NET_DEVLINK=y\nCONFIG_NET_FAILOVER=y\nCONFIG_NET_FLOW_LIMIT=y\nCONFIG_NET_NS=y\nCONFIG_NET_PTP_CLASSIFY=y\nCONFIG_NET_SWITCHDEV=y\nCONFIG_NLS=y\nCONFIG_NLS_CODEPAGE_437=y\nCONFIG_NLS_ISO8859_1=y\nCONFIG_NODES_SHIFT=2\nCONFIG_NO_HZ_COMMON=y\nCONFIG_NO_HZ_IDLE=y\nCONFIG_NR_CPUS=64\nCONFIG_NUMA=y\nCONFIG_NUMA_BALANCING=y\nCONFIG_NUMA_BALANCING_DEFAULT_ENABLED=y\nCONFIG_NVMEM=y\n# CONFIG_NVMEM_SPMI_SDAM is not set\nCONFIG_NVMEM_SYSFS=y\nCONFIG_OF=y\nCONFIG_OF_ADDRESS=y\nCONFIG_OF_EARLY_FLATTREE=y\nCONFIG_OF_FLATTREE=y\nCONFIG_OF_GPIO=y\nCONFIG_OF_IOMMU=y\nCONFIG_OF_IRQ=y\nCONFIG_OF_KOBJ=y\nCONFIG_OF_MDIO=y\nCONFIG_OF_NET=y\nCONFIG_OF_NUMA=y\nCONFIG_PACKET_DIAG=y\nCONFIG_PADATA=y\nCONFIG_PAGE_POOL=y\nCONFIG_PAGE_REPORTING=y\n# CONFIG_PANIC_ON_OOPS is not set\nCONFIG_PANIC_ON_OOPS_VALUE=0\nCONFIG_PANIC_TIMEOUT=0\nCONFIG_PARAVIRT=y\n# CONFIG_PARTITION_ADVANCED is not set\nCONFIG_PARTITION_PERCPU=y\nCONFIG_PCI=y\nCONFIG_PCIEAER=y\nCONFIG_PCIEASPM=y\nCONFIG_PCIEASPM_DEFAULT=y\n# CONFIG_PCIEASPM_PERFORMANCE is not set\n# CONFIG_PCIEASPM_POWERSAVE is not set\n# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set\nCONFIG_PCIEPORTBUS=y\nCONFIG_PCIE_DW=y\nCONFIG_PCIE_DW_HOST=y\nCONFIG_PCIE_LAYERSCAPE_GEN4=y\nCONFIG_PCIE_MOBIVEIL=y\nCONFIG_PCIE_MOBIVEIL_HOST=y\nCONFIG_PCIE_PME=y\nCONFIG_PCI_ATS=y\nCONFIG_PCI_DOMAINS=y\nCONFIG_PCI_DOMAINS_GENERIC=y\nCONFIG_PCI_ECAM=y\nCONFIG_PCI_HISI=y\nCONFIG_PCI_HOST_COMMON=y\nCONFIG_PCI_HOST_GENERIC=y\nCONFIG_PCI_IOV=y\nCONFIG_PCI_LAYERSCAPE=y\nCONFIG_PCI_MSI=y\nCONFIG_PCI_MSI_IRQ_DOMAIN=y\nCONFIG_PCS_LYNX=y\nCONFIG_PGTABLE_LEVELS=4\nCONFIG_PHYLIB=y\nCONFIG_PHYLINK=y\nCONFIG_PHYS_ADDR_T_64BIT=y\nCONFIG_PHY_XGENE=y\nCONFIG_PID_IN_CONTEXTIDR=y\nCONFIG_PID_NS=y\nCONFIG_PL330_DMA=y\nCONFIG_PM=y\nCONFIG_PM_CLK=y\nCONFIG_PM_OPP=y\nCONFIG_PM_SLEEP=y\nCONFIG_PM_SLEEP_SMP=y\nCONFIG_PM_STD_PARTITION=\"\"\nCONFIG_POWER_RESET=y\nCONFIG_POWER_RESET_SYSCON=y\nCONFIG_POWER_RESET_VEXPRESS=y\nCONFIG_POWER_RESET_XGENE=y\nCONFIG_POWER_SUPPLY=y\nCONFIG_PPS=y\nCONFIG_PREEMPT=y\nCONFIG_PREEMPTION=y\nCONFIG_PREEMPT_COUNT=y\n# CONFIG_PREEMPT_NONE is not set\nCONFIG_PREEMPT_RCU=y\nCONFIG_PRINTK_TIME=y\nCONFIG_PRINT_QUOTA_WARNING=y\nCONFIG_PROC_CHILDREN=y\nCONFIG_PROFILING=y\nCONFIG_PTP_1588_CLOCK=y\nCONFIG_PTP_1588_CLOCK_QORIQ=y\nCONFIG_QCOM_HIDMA=y\nCONFIG_QCOM_HIDMA_MGMT=y\nCONFIG_QCOM_QDF2400_ERRATUM_0065=y\n# CONFIG_QFMT_V1 is not set\n# CONFIG_QFMT_V2 is not set\nCONFIG_QORIQ_CPUFREQ=y\nCONFIG_QORIQ_THERMAL=y\nCONFIG_QUEUED_RWLOCKS=y\nCONFIG_QUEUED_SPINLOCKS=y\nCONFIG_QUOTA=y\nCONFIG_QUOTACTL=y\n# CONFIG_QUOTA_NETLINK_INTERFACE is not set\nCONFIG_RAID6_PQ=y\nCONFIG_RAS=y\nCONFIG_RATIONAL=y\nCONFIG_RD_BZIP2=y\nCONFIG_RD_GZIP=y\nCONFIG_RD_LZMA=y\nCONFIG_RD_LZO=y\nCONFIG_RD_XZ=y\nCONFIG_REALTEK_PHY=y\nCONFIG_REGMAP=y\nCONFIG_REGMAP_I2C=y\nCONFIG_REGMAP_MMIO=y\nCONFIG_REGMAP_SPI=y\nCONFIG_RESET_CONTROLLER=y\nCONFIG_RFS_ACCEL=y\nCONFIG_RODATA_FULL_DEFAULT_ENABLED=y\nCONFIG_RPS=y\nCONFIG_RTC_CLASS=y\nCONFIG_RTC_DRV_DS1307=y\nCONFIG_RTC_DRV_DS3232=y\nCONFIG_RTC_DRV_FSL_FTM_ALARM=y\nCONFIG_RTC_DRV_PCF2127=y\nCONFIG_RTC_DRV_PL031=y\nCONFIG_RTC_I2C_AND_SPI=y\nCONFIG_RWSEM_SPIN_ON_OWNER=y\nCONFIG_SCHED_INFO=y\nCONFIG_SCHED_MC=y\nCONFIG_SCHED_THERMAL_PRESSURE=y\nCONFIG_SCSI=y\n# CONFIG_SCSI_PROC_FS is not set\n# CONFIG_SCSI_SAS_ATA is not set\nCONFIG_SCSI_SAS_ATTRS=y\nCONFIG_SCSI_SAS_HOST_SMP=y\nCONFIG_SCSI_SAS_LIBSAS=y\nCONFIG_SECCOMP=y\nCONFIG_SECCOMP_FILTER=y\nCONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y\nCONFIG_SERIAL_8250_DW=y\nCONFIG_SERIAL_8250_DWLIB=y\nCONFIG_SERIAL_8250_EXTENDED=y\nCONFIG_SERIAL_8250_FSL=y\nCONFIG_SERIAL_8250_NR_UARTS=4\nCONFIG_SERIAL_8250_PCI=y\nCONFIG_SERIAL_8250_RUNTIME_UARTS=4\nCONFIG_SERIAL_8250_SHARE_IRQ=y\nCONFIG_SERIAL_AMBA_PL011=y\nCONFIG_SERIAL_AMBA_PL011_CONSOLE=y\nCONFIG_SERIAL_FSL_LPUART=y\nCONFIG_SERIAL_FSL_LPUART_CONSOLE=y\nCONFIG_SERIAL_MCTRL_GPIO=y\nCONFIG_SERIAL_OF_PLATFORM=y\nCONFIG_SERIAL_SC16IS7XX=y\nCONFIG_SERIAL_SC16IS7XX_CORE=y\n# CONFIG_SERIAL_SC16IS7XX_I2C is not set\nCONFIG_SERIAL_SC16IS7XX_SPI=y\nCONFIG_SERIAL_XILINX_PS_UART=y\nCONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y\nCONFIG_SERIO=y\nCONFIG_SERIO_AMBAKMI=y\nCONFIG_SERIO_LIBPS2=y\nCONFIG_SGL_ALLOC=y\nCONFIG_SG_POOL=y\nCONFIG_SLAB=y\n# CONFIG_SLUB is not set\nCONFIG_SMP=y\nCONFIG_SOCK_DIAG=y\nCONFIG_SOC_BUS=y\nCONFIG_SPARSEMEM=y\nCONFIG_SPARSEMEM_EXTREME=y\nCONFIG_SPARSEMEM_MANUAL=y\nCONFIG_SPARSEMEM_VMEMMAP=y\nCONFIG_SPARSEMEM_VMEMMAP_ENABLE=y\nCONFIG_SPARSE_IRQ=y\nCONFIG_SPI=y\nCONFIG_SPI_FSL_DSPI=y\nCONFIG_SPI_FSL_QUADSPI=y\nCONFIG_SPI_MASTER=y\nCONFIG_SPI_MEM=y\nCONFIG_SPI_NXP_FLEXSPI=y\nCONFIG_SPI_PL022=y\nCONFIG_SPMI=y\n# CONFIG_SPMI_HISI3670 is not set\n# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set\nCONFIG_SQUASHFS_DECOMP_SINGLE=y\nCONFIG_SQUASHFS_FILE_CACHE=y\n# CONFIG_SQUASHFS_FILE_DIRECT is not set\n# CONFIG_SQUASHFS_XZ is not set\nCONFIG_SQUASHFS_ZLIB=y\nCONFIG_SRAM=y\nCONFIG_SRCU=y\n# CONFIG_STRIP_ASM_SYMS is not set\nCONFIG_SUSPEND=y\nCONFIG_SUSPEND_FREEZER=y\nCONFIG_SWIOTLB=y\nCONFIG_SWIOTLB_XEN=y\nCONFIG_SWPHY=y\nCONFIG_SYNC_FILE=y\nCONFIG_SYSCTL_EXCEPTION_TRACE=y\nCONFIG_SYSFS_SYSCALL=y\nCONFIG_SYS_HYPERVISOR=y\nCONFIG_SYS_SUPPORTS_HUGETLBFS=y\nCONFIG_TASKSTATS=y\nCONFIG_TASK_DELAY_ACCT=y\nCONFIG_TASK_IO_ACCOUNTING=y\nCONFIG_TASK_XACCT=y\nCONFIG_THERMAL=y\nCONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y\nCONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0\nCONFIG_THERMAL_EMULATION=y\nCONFIG_THERMAL_GOV_STEP_WISE=y\nCONFIG_THERMAL_OF=y\nCONFIG_THREAD_INFO_IN_TASK=y\nCONFIG_TICK_CPU_ACCOUNTING=y\nCONFIG_TIMER_OF=y\nCONFIG_TIMER_PROBE=y\nCONFIG_TMPFS_POSIX_ACL=y\nCONFIG_TRANSPARENT_HUGEPAGE=y\nCONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y\n# CONFIG_TRANSPARENT_HUGEPAGE_MADVISE is not set\nCONFIG_TREE_RCU=y\nCONFIG_TREE_SRCU=y\n# CONFIG_UACCE is not set\nCONFIG_UBIFS_FS=y\n# CONFIG_UCLAMP_TASK is not set\nCONFIG_UIO=y\nCONFIG_UIO_AEC=y\nCONFIG_UIO_CIF=y\nCONFIG_UIO_DMEM_GENIRQ=y\nCONFIG_UIO_MF624=y\nCONFIG_UIO_NETX=y\nCONFIG_UIO_PCI_GENERIC=y\nCONFIG_UIO_PDRV_GENIRQ=y\n# CONFIG_UIO_PRUSS is not set\nCONFIG_UIO_SERCOS3=y\nCONFIG_UNINLINE_SPIN_UNLOCK=y\nCONFIG_UNIX_DIAG=y\nCONFIG_UNMAP_KERNEL_AT_EL0=y\nCONFIG_USB_SUPPORT=y\nCONFIG_USER_NS=y\nCONFIG_USE_PERCPU_NUMA_NODE_ID=y\nCONFIG_UTS_NS=y\nCONFIG_VEXPRESS_CONFIG=y\nCONFIG_VFAT_FS=y\nCONFIG_VFIO=y\nCONFIG_VFIO_FSL_MC=y\nCONFIG_VFIO_IOMMU_TYPE1=y\n# CONFIG_VFIO_MDEV is not set\n# CONFIG_VFIO_NOIOMMU is not set\nCONFIG_VFIO_PCI=y\nCONFIG_VFIO_PCI_INTX=y\nCONFIG_VFIO_PCI_MMAP=y\n# CONFIG_VFIO_PLATFORM is not set\nCONFIG_VFIO_VIRQFD=y\nCONFIG_VGA_ARB=y\nCONFIG_VGA_ARB_MAX_GPUS=16\nCONFIG_VIDEOMODE_HELPERS=y\nCONFIG_VIRTIO=y\nCONFIG_VIRTIO_BALLOON=y\nCONFIG_VIRTIO_BLK=y\nCONFIG_VIRTIO_CONSOLE=y\n# CONFIG_VIRTIO_IOMMU is not set\nCONFIG_VIRTIO_MMIO=y\nCONFIG_VIRTIO_NET=y\nCONFIG_VIRTIO_PCI=y\nCONFIG_VIRTIO_PCI_LEGACY=y\nCONFIG_VITESSE_PHY=y\nCONFIG_VLAN_8021Q_GVRP=y\nCONFIG_VLAN_8021Q_MVRP=y\nCONFIG_VMAP_STACK=y\nCONFIG_VM_EVENT_COUNTERS=y\nCONFIG_VT=y\nCONFIG_VT_CONSOLE=y\nCONFIG_VT_CONSOLE_SLEEP=y\nCONFIG_VT_HW_CONSOLE_BINDING=y\nCONFIG_WATCHDOG_CORE=y\n# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set\nCONFIG_XARRAY_MULTI=y\nCONFIG_XEN=y\nCONFIG_XENFS=y\nCONFIG_XEN_AUTO_XLATE=y\nCONFIG_XEN_BACKEND=y\nCONFIG_XEN_BALLOON=y\n# CONFIG_XEN_BLKDEV_BACKEND is not set\nCONFIG_XEN_BLKDEV_FRONTEND=y\nCONFIG_XEN_COMPAT_XENFS=y\nCONFIG_XEN_DEV_EVTCHN=y\nCONFIG_XEN_DOM0=y\nCONFIG_XEN_FBDEV_FRONTEND=y\nCONFIG_XEN_GNTDEV=y\nCONFIG_XEN_GRANT_DEV_ALLOC=y\n# CONFIG_XEN_NETDEV_BACKEND is not set\nCONFIG_XEN_NETDEV_FRONTEND=y\nCONFIG_XEN_PRIVCMD=y\n# CONFIG_XEN_PVCALLS_BACKEND is not set\n# CONFIG_XEN_SCSI_FRONTEND is not set\nCONFIG_XEN_SYS_HYPERVISOR=y\n# CONFIG_XEN_WDT is not set\nCONFIG_XEN_XENBUS_FRONTEND=y\nCONFIG_XFS_FS=y\nCONFIG_XFS_POSIX_ACL=y\nCONFIG_XFS_RT=y\nCONFIG_XOR_BLOCKS=y\nCONFIG_XPS=y\nCONFIG_XXHASH=y\nCONFIG_XZ_DEC_ARM=y\nCONFIG_XZ_DEC_ARMTHUMB=y\nCONFIG_XZ_DEC_BCJ=y\nCONFIG_XZ_DEC_IA64=y\nCONFIG_XZ_DEC_POWERPC=y\nCONFIG_XZ_DEC_SPARC=y\nCONFIG_XZ_DEC_X86=y\nCONFIG_ZLIB_DEFLATE=y\nCONFIG_ZLIB_INFLATE=y\nCONFIG_ZONE_DMA32=y\nCONFIG_ZSTD_COMPRESS=y\nCONFIG_ZSTD_DECOMPRESS=y\n"
  },
  {
    "path": "target/linux/layerscape/armv8_64b/target.mk",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2016 Jiang Yutang <jiangyutang1978@gmail.com>\n\nARCH:=aarch64\nBOARDNAME:=ARMv8 64-bit based boards\nKERNELNAME:=Image dtbs\n\ndefine Target/Description\n\tBuild firmware images for NXP Layerscape ARMv8 64-bit based boards.\nendef\n"
  },
  {
    "path": "target/linux/layerscape/base-files/etc/board.d/01_led",
    "content": "#\n# Copyright (C) 2015 OpenWrt.org\n#\n\n. /lib/functions/uci-defaults.sh\n\nboard_config_update\n\nboard=$(board_name)\n\ncase \"$board\" in\ntraverse,ls1043v)\n\tucidef_set_led_netdev \"wan\" \"WAN LED\" \"ls1043v:yellow:wan\" \"eth4\"\n\t;;\ntraverse,ls1043s)\n\tucidef_set_led_netdev \"wan\" \"WAN LED\" \"ls1043s:yellow:wan\" \"eth4\"\n\tucidef_set_led_netdev \"xgact\" \"10G Activity\" \"ls1043s:yellow:10gact\" \"eth6\"\n\tucidef_set_led_netdev \"xglink\" \"10G Link\" \"ls1043s:green:10glink\" \"eth6\"\n\t;;\nesac\n\nboard_config_flush\n\nexit 0\n"
  },
  {
    "path": "target/linux/layerscape/base-files/etc/board.d/02_network",
    "content": "\n. /lib/functions/system.sh\n. /lib/functions/uci-defaults.sh\n\nboard_config_update\n\ncase \"$(board_name)\" in\n\ttraverse,ls1043v)\n\t\tucidef_set_interface_lan \"eth0 eth1 eth2 eth3\"\n\t\tucidef_set_interface_wan \"eth4\"\n\t\t;;\n\ttraverse,ls1043s)\n\t\tucidef_set_interface_lan \"eth0 eth1 eth2 eth3 eth6\"\n\t\tucidef_set_interface_wan \"eth4\"\n\t\t;;\nesac\n\nboard_config_flush\n\nexit 0\n"
  },
  {
    "path": "target/linux/layerscape/base-files/etc/board.d/03_gpio_switches",
    "content": "#\n# Copyright (C) 2015 OpenWrt.org\n#\n\n. /lib/functions/uci-defaults.sh\n\nboard_config_update\n\nboard=$(board_name)\n\ncase \"$board\" in\ntraverse,ls1043v)\n\tucidef_add_gpio_switch \"lte_reset\" \"LTE Reset\" \"377\"\n\tucidef_add_gpio_switch \"lte_disable\" \"LTE Airplane mode\" \"378\"\n\t;;\ntraverse,ls1043s)\n\tucidef_add_gpio_switch \"tensfp_txdisable\" \"SFP+ TX Disable\" \"378\"\n\tucidef_add_gpio_switch \"gigsfp_txdisable\" \"SFP TX Disable\" \"381\"\n\tucidef_add_gpio_switch \"lte_reset\" \"LTE Reset\" \"502\"\n\tucidef_add_gpio_switch \"lte_disable\" \"LTE Airplane Mode\" \"394\"\n\tucidef_add_gpio_switch \"lte_power\" \"LTE Power\" \"395\"\n\t;;\nesac\n\nboard_config_flush\n\nexit 0\n"
  },
  {
    "path": "target/linux/layerscape/base-files/etc/uci-defaults/05_fix-compat-version",
    "content": "#\n# Copyright (C) 2020 OpenWrt.org\n#\n\n. /lib/functions.sh\n\ncase \"$(board_name)\" in\n\tfsl,ls1012a-frwy-sdboot | \\\n\tfsl,ls1012a-rdb | \\\n\tfsl,ls1021a-iot-sdboot | \\\n\tfsl,ls1021a-twr | \\\n\tfsl,ls1021a-twr-sdboot | \\\n\tfsl,ls1043a-rdb | \\\n\tfsl,ls1043a-rdb-sdboot | \\\n\tfsl,ls1046a-rdb | \\\n\tfsl,ls1046a-rdb-sdboot | \\\n\tfsl,ls1088a-rdb | \\\n\tfsl,ls1088a-rdb-sdboot | \\\n\tfsl,ls2088a-rdb)\n\t\tuci set system.@system[0].compat_version=\"2.0\"\n\t\tuci commit system\n\t\t;;\nesac\n\nexit 0\n"
  },
  {
    "path": "target/linux/layerscape/base-files/lib/preinit/02_sysinfo_fixup",
    "content": "do_sysinfo_layerscape_fixup() {\n\t[ -e /tmp/sysinfo/board_name ] || return\n\t[ -e /proc/cmdline ] || return\n\tcmdline=$(strings /proc/cmdline)\n\tcase \"${cmdline}\" in\n\t\t*root=/dev/mmcblk*)\n\t\t\tboard=\"$(strings /tmp/sysinfo/board_name)-sdboot\"\n\t\t\techo ${board} > /tmp/sysinfo/board_name\n\t\t;;\n\tesac\n}\n\nboot_hook_add preinit_main do_sysinfo_layerscape_fixup\n"
  },
  {
    "path": "target/linux/layerscape/base-files/lib/preinit/05_layerscape_reorder_eth",
    "content": "reorder_layerscape_interfaces() {\n\tif [ ! -f /tmp/sysinfo/board_name ]; then\n\t\techo \"No board name found, not doing reorder_layerscape_interfaces\"\n\t\treturn 0\n\tfi\n\n\tboard=$(cat /tmp/sysinfo/board_name)\n\tcase \"$board\" in\n\ttraverse,ls1043v|\\\n\ttraverse,ls1043s)\n\n\t\t# Reorder ethernet interfaces to match the physical order\n\t\tip link set eth2 name fm1-mac3\n\t\tip link set eth4 name eth2\n\t\tip link set eth3 name fm1-mac4\n\t\tip link set eth5 name eth3\n\t\tip link set fm1-mac3 name eth4\n\t\tip link set fm1-mac4 name eth5\n\t\t;;\n\tdefault)\n\t\techo \"Unknown board $board\"\n\t\t;;\n\tesac\n}\n\nboot_hook_add preinit_main reorder_layerscape_interfaces\n"
  },
  {
    "path": "target/linux/layerscape/base-files/lib/preinit/79_move_config",
    "content": ". /lib/functions.sh\n. /lib/upgrade/common.sh\n\nBOOTPART=/dev/mmcblk0p1\n\nmove_config() {\n\tlocal board=$(board_name)\n\n\tcase \"$board\" in\n\tfsl,ls1012a-frwy-sdboot | \\\n\tfsl,ls1021a-iot-sdboot | \\\n\tfsl,ls1021a-twr-sdboot | \\\n\tfsl,ls1043a-rdb-sdboot | \\\n\tfsl,ls1046a-frwy-sdboot | \\\n\tfsl,ls1046a-rdb-sdboot | \\\n\tfsl,ls1088a-rdb-sdboot)\n\t\tif [ -b $BOOTPART ]; then\n\t\t\tmkdir -p /boot\n\t\t\tmount -t ext4 -o rw,noatime $BOOTPART /boot 2>&1\n\t\t\t[ -f \"/boot/$BACKUP_FILE\" ] && mv -f \"/boot/$BACKUP_FILE\" /\n\t\t\tumount /boot\n\t\tfi\n\t\t;;\n\tesac\n}\n\nboot_hook_add preinit_mount_root move_config\n"
  },
  {
    "path": "target/linux/layerscape/base-files/lib/upgrade/platform.sh",
    "content": "#\n# Copyright 2015-2019 Traverse Technologies\n# Copyright 2020 NXP\n#\n\nRAMFS_COPY_BIN=\"/usr/sbin/fw_printenv /usr/sbin/fw_setenv /usr/sbin/ubinfo /bin/echo\"\nRAMFS_COPY_DATA=\"/etc/fw_env.config /var/lock/fw_printenv.lock\"\n\nREQUIRE_IMAGE_METADATA=1\n\nplatform_do_upgrade_sdboot() {\n\tlocal diskdev partdev parttype=ext4\n\tlocal tar_file=\"$1\"\n\tlocal board_dir=$(tar tf $tar_file | grep -m 1 '^sysupgrade-.*/$')\n\tboard_dir=${board_dir%/}\n\n\texport_bootdevice && export_partdevice diskdev 0 || {\n\t\techo \"Unable to determine upgrade device\"\n\t\treturn 1\n\t}\n\n\tif export_partdevice partdev 1; then\n\t\tmount -t $parttype -o rw,noatime \"/dev/$partdev\" /mnt 2>&1\n\t\techo \"Writing kernel...\"\n\t\ttar xf $tar_file ${board_dir}/kernel -O > /mnt/fitImage\n\t\tumount /mnt\n\tfi\n\n\techo \"Erasing rootfs...\"\n\tdd if=/dev/zero of=/dev/mmcblk0p2 bs=1M > /dev/null 2>&1\n\techo \"Writing rootfs...\"\n\ttar xf $tar_file ${board_dir}/root -O  | dd of=/dev/mmcblk0p2 bs=512k > /dev/null 2>&1\n\n}\nplatform_do_upgrade_traverse_nandubi() {\n\tbootsys=$(fw_printenv bootsys | awk -F= '{{print $2}}')\n\tnewbootsys=2\n\tif [ \"$bootsys\" -eq \"2\" ]; then\n\t\tnewbootsys=1\n\tfi\n\n\t# If nand_do_upgrade succeeds, we don't have an opportunity to add any actions of\n\t# our own, so do it here and set back on failure\n\techo \"Setting bootsys to #${newbootsys}\"\n\tfw_setenv bootsys $newbootsys\n\tCI_UBIPART=\"nandubi\"\n\tCI_KERNPART=\"kernel${newbootsys}\"\n\tCI_ROOTPART=\"rootfs${newbootsys}\"\n\tnand_do_upgrade \"$1\" || (echo \"Upgrade failed, setting bootsys ${bootsys}\" && fw_setenv bootsys $bootsys)\n\n}\nplatform_copy_config_sdboot() {\n\tlocal diskdev partdev parttype=ext4\n\n\texport_bootdevice && export_partdevice diskdev 0 || {\n\t\techo \"Unable to determine upgrade device\"\n\t\treturn 1\n\t}\n\n\tif export_partdevice partdev 1; then\n\t\tmount -t $parttype -o rw,noatime \"/dev/$partdev\" /mnt 2>&1\n\t\techo \"Saving config backup...\"\n\t\tcp -af \"$UPGRADE_BACKUP\" \"/mnt/$BACKUP_FILE\"\n\t\tumount /mnt\n\tfi\n}\nplatform_copy_config() {\n\tlocal board=$(board_name)\n\n\tcase \"$board\" in\n\tfsl,ls1012a-frwy-sdboot | \\\n\tfsl,ls1021a-iot-sdboot | \\\n\tfsl,ls1021a-twr-sdboot | \\\n\tfsl,ls1043a-rdb-sdboot | \\\n\tfsl,ls1046a-frwy-sdboot | \\\n\tfsl,ls1046a-rdb-sdboot | \\\n\tfsl,ls1088a-rdb-sdboot | \\\n\tfsl,lx2160a-rdb-sdboot)\n\t\tplatform_copy_config_sdboot\n\t\t;;\n\tesac\n}\nplatform_check_image() {\n\tlocal board=$(board_name)\n\n\tcase \"$board\" in\n\ttraverse,ls1043v | \\\n\ttraverse,ls1043s)\n\t\tnand_do_platform_check \"traverse-ls1043\" $1\n\t\treturn $?\n\t\t;;\n\tfsl,ls1012a-frdm | \\\n\tfsl,ls1012a-frwy-sdboot | \\\n\tfsl,ls1012a-rdb | \\\n\tfsl,ls1021a-iot-sdboot | \\\n\tfsl,ls1021a-twr | \\\n\tfsl,ls1021a-twr-sdboot | \\\n\tfsl,ls1043a-rdb | \\\n\tfsl,ls1043a-rdb-sdboot | \\\n\tfsl,ls1046a-frwy | \\\n\tfsl,ls1046a-frwy-sdboot | \\\n\tfsl,ls1046a-rdb | \\\n\tfsl,ls1046a-rdb-sdboot | \\\n\tfsl,ls1088a-rdb | \\\n\tfsl,ls1088a-rdb-sdboot | \\\n\tfsl,ls2088a-rdb | \\\n\tfsl,lx2160a-rdb | \\\n\tfsl,lx2160a-rdb-sdboot)\n\t\treturn 0\n\t\t;;\n\t*)\n\t\techo \"Sysupgrade is not currently supported on $board\"\n\t\t;;\n\tesac\n\n\treturn 1\n}\nplatform_do_upgrade() {\n\tlocal board=$(board_name)\n\n\t# Force the creation of fw_printenv.lock\n\tmkdir -p /var/lock\n\ttouch /var/lock/fw_printenv.lock\n\n\tcase \"$board\" in\n\ttraverse,ls1043v | \\\n\ttraverse,ls1043s)\n\t\tplatform_do_upgrade_traverse_nandubi \"$1\"\n\t\t;;\n\tfsl,ls1012a-frdm | \\\n\tfsl,ls1012a-rdb | \\\n\tfsl,ls1021a-twr | \\\n\tfsl,ls1043a-rdb | \\\n\tfsl,ls1046a-frwy | \\\n\tfsl,ls1046a-rdb | \\\n\tfsl,ls1088a-rdb | \\\n\tfsl,ls2088a-rdb | \\\n\tfsl,lx2160a-rdb)\n\t\tPART_NAME=firmware\n\t\tdefault_do_upgrade \"$1\"\n\t\t;;\n\tfsl,ls1012a-frwy-sdboot | \\\n\tfsl,ls1021a-iot-sdboot | \\\n\tfsl,ls1021a-twr-sdboot | \\\n\tfsl,ls1043a-rdb-sdboot | \\\n\tfsl,ls1046a-frwy-sdboot | \\\n\tfsl,ls1046a-rdb-sdboot | \\\n\tfsl,ls1088a-rdb-sdboot | \\\n\tfsl,lx2160a-rdb-sdboot)\n\t\tplatform_do_upgrade_sdboot \"$1\"\n\t\treturn 0\n\t\t;;\n\t*)\n\t\techo \"Sysupgrade is not currently supported on $board\"\n\t\t;;\n\tesac\n}\n"
  },
  {
    "path": "target/linux/layerscape/files/arch/arm64/boot/dts/freescale/traverse-ls1043s.dts",
    "content": "/*\n * Device Tree Include file for Traverse LS1043S board.\n *\n * Copyright 2014-2015, Freescale Semiconductor\n * Copyright 2017-2018, Traverse Technologies\n *\n * This file is dual-licensed: you can use it either under the terms\n * of the GPLv2 or the X11 license, at your option. Note that this dual\n * licensing only applies to this file, and not this project as a\n * whole.\n *\n *  a) This library is free software; you can redistribute it and/or\n *     modify it under the terms of the GNU General Public License as\n *     published by the Free Software Foundation; either version 2 of the\n *     License, or (at your option) any later version.\n *\n *     This library is distributed in the hope that it will be useful,\n *     but WITHOUT ANY WARRANTY; without even the implied warranty of\n *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n *     GNU General Public License for more details.\n *\n * Or, alternatively,\n *\n *  b) Permission is hereby granted, free of charge, to any person\n *     obtaining a copy of this software and associated documentation\n *     files (the \"Software\"), to deal in the Software without\n *     restriction, including without limitation the rights to use,\n *     copy, modify, merge, publish, distribute, sublicense, and/or\n *     sell copies of the Software, and to permit persons to whom the\n *     Software is furnished to do so, subject to the following\n *     conditions:\n *\n *     The above copyright notice and this permission notice shall be\n *     included in all copies or substantial portions of the Software.\n *\n *     THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n *     OTHER DEALINGS IN THE SOFTWARE.\n */\n\n/dts-v1/;\n#include \"fsl-ls1043a.dtsi\"\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"Traverse LS1043S\";\n\tcompatible = \"traverse,ls1043s\";\n\n\taliases {\n\t\tcrypto = &crypto;\n\t\tethernet0 = &EMAC0;\n\t\tethernet1 = &EMAC1;\n\t\tethernet2 = &EMAC2;\n\t\tethernet3 = &EMAC3;\n\t\tethernet4 = &EMAC4;\n\t\tethernet5 = &EMAC5;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tgpio0 {\n\t\t\tlabel = \"ls1043s:green:user0\";\n\t\t\tgpios = <&gpio1 23 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t\tgpio1 {\n\t\t\tlabel = \"ls1043s:green:user1\";\n\t\t\tgpios = <&gpio1 24 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t\t/* LED D17 */\n\t\tgpio2 {\n\t\t\tlabel = \"ls1043s:green:wan\";\n\t\t\tgpios = <&gpio1 26 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tgpio3 {\n\t\t\tlabel = \"ls1043s:yellow:wan\";\n\t\t\tgpios = <&gpio1 27 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\t/* LED D18 */\n\t\tgpio4 {\n\t\t\tlabel = \"ls1043s:green:mgmt\";\n\t\t\tgpios = <&gpio1 28 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tgpio5 {\n\t\t\tlabel = \"ls1043s:yellow:mgmt\";\n\t\t\tgpios = <&gpio1 29 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\t/* LED D6 */\n\t\tgpio6 {\n\t\t\tlabel = \"ls1043s:green:user2\";\n\t\t\tgpios = <&gpio1 31 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\t/* SFP+ LEDs - these are for chassis\n\t\t * with lightpipes only\n\t\t */\n\t\tteng_act {\n\t\t\tlabel = \"ls1043s:yellow:10gact\";\n\t\t\tgpios = <&gpio4 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tteng_link {\n\t\t\tlabel = \"ls1043s:green:10glink\";\n\t\t\tgpios = <&gpio4 1 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tpoll-interval = <1000>;\n\t\t/* This button may not be loaded on all boards */\n\t\tbutton@0 {\n\t\t\tlabel = \"Front button\";\n\t\t\tlinux,code = <KEY_SETUP>;\n\t\t\tgpios = <&gpio1 25 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\t/* This is wired to header S3 */\n\t\tbutton@1 {\n\t\t\tlabel = \"Rear button\";\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tgpios = <&gpio1 30 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&esdhc {\n\tmmc-hs200-1_8v;\n\tsd-uhs-sdr104;\n\tsd-uhs-sdr50;\n\tsd-uhs-sdr25;\n\tsd-uhs-sdr12;\n};\n\n&i2c0 {\n\tstatus = \"okay\";\n\trtc@6f {\n\t\tcompatible = \"intersil,isl1208\";\n\t\treg = <0x6f>;\n\t};\n\n\tsfp_pca9534: pca9534@24 {\n\t\tcompatible = \"ti,tca9534\", \"nxp,pca9534\";\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\treg = <0x24>;\n\t\tgpio-base = <100>;\n\t};\n\n\tcontroller@50 {\n\t\tcompatible = \"traverse,controller\";\n\t\treg = <0x50>;\n\t};\n\n\tds125df111@18 {\n\t\tcompatible = \"ti,ds125df111\";\n\t\treg = <0x18>;\n\t};\n\n\temc1704@4c {\n\t\tcompatible = \"microchip,emc1704\";\n\t\treg = <0x4c>;\n\t};\n\n\tpac1934@16 {\n\t\tcompatible = \"microchip,pac1934\";\n\t\treg = <0x16>;\n\t\t/* Monitoring 3.3V, 5V, Vin/12V (voltage only), Vbat/RTC (voltage only) */\n\t\tshunt-resistors = <4000 12000 0 0>;\n\t};\n\n\tpmic@8 {\n\t\tcompatible = \"freescale,mc34vr500\";\n\t\treg = <0x08>;\n\t};\n};\n\n/* I2C Bus for SFP EEPROM and control\n * These are multiplexed so\n * they don't collide when loaded\n */\n&i2c3 {\n\tstatus = \"okay\";\n\ti2c-switch@70 {\n\t\tcompatible = \"nxp,pca9540\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x70>;\n\n\t\tgigsfp_i2c: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t};\n\t\ttensfp_i2c: i2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t};\n\t};\n};\n\n&ifc {\n\tstatus = \"okay\";\n\t#address-cells = <2>;\n\t#size-cells = <1>;\n\t/* Only NAND flash is used on this board */\n\tranges = <0x0 0x0 0x0 0x7e800000 0x00010000>;\n\n\tnand@1,0 {\n\t\tcompatible = \"fsl,ifc-nand\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0 0x0 0x10000>;\n\t};\n};\n\n&duart0 {\n\tstatus = \"okay\";\n};\n\n&duart1 {\n\tstatus = \"okay\";\n};\n\n#include \"fsl-ls1043-post.dtsi\"\n\n&fman0 {\n\tEMAC0: ethernet@e0000 {\n\t\tphy-handle = <&qsgmii_phy1>;\n\t\tphy-connection-type = \"qsgmii\";\n\t\tlocal-mac-address = [0A 00 00 00 00 01];\n\t};\n\n\tEMAC1: ethernet@e2000 {\n\t\tphy-handle = <&qsgmii_phy2>;\n\t\tphy-connection-type = \"qsgmii\";\n\t\tlocal-mac-address = [0A 00 00 00 00 02];\n\t};\n\n\tEMAC2: ethernet@e8000 {\n\t\tphy-handle = <&qsgmii_phy3>;\n\t\tphy-connection-type = \"qsgmii\";\n\t\tlocal-mac-address = [0A 00 00 00 00 03];\n\t};\n\n\tEMAC3: ethernet@ea000 {\n\t\tphy-handle = <&qsgmii_phy4>;\n\t\tphy-connection-type = \"qsgmii\";\n\t\tlocal-mac-address = [0A 00 00 00 00 04];\n\t};\n\n\t/* SFP via AR8031\n\t * We treat this as a fixed-link as the\n\t * AR8031 is hard-configured into\n\t * 1000BASE-X mode\n\t * Should MII control be desired, remove\n\t * fixed-link and add\n\t * phy-handle = <&rgmii_phy1>;\n\t */\n\tEMAC4: ethernet@e4000 {\n\t\tphy-connection-type = \"rgmii\";\n\t\tlocal-mac-address = [0A 00 00 00 00 05];\n\t\tfixed-link {\n\t\t\tspeed = <1000>;\n\t\t\tfull-duplex;\n\t\t};\n\t};\n\n\t/* Connection to Expansion (M.2) slot\n\t * Future WAN (i.e xDSL) plugin\n\t */\n\tEMAC5: ethernet@e6000 {\n\t\tphy-connection-type = \"rgmii-id\";\n\t\tlocal-mac-address = [00 00 00 00 00 06];\n\t\tfixed-link {\n\t\t\tspeed = <1000>;\n\t\t\tfull-duplex;\n\t\t};\n\t};\n\n\t/* 10G SFP+ interface\n\t * This can also run at 1.25 and 2.5G with\n\t * the appropriate SerDes protocol setting in RCW\n\t */\n\tTENSFP: ethernet@f0000 {\n\t\tstatus = \"okay\";\n\t\tphy-connection-type = \"xgmii\";\n\t\tfixed-link {\n\t\t\tspeed = <10000>;\n\t\t\tfull-duplex;\n\t\t};\n\t};\n\n\tmdio@fc000 {\n\t\trgmii_phy1: ethernet-phy@2 {\n\t\t\treg = <0x2>;\n\t\t};\n\t\tqsgmii_phy1: ethernet-phy@4 {\n\t\t\treg = <0x4>;\n\t\t};\n\t\tqsgmii_phy2: ethernet-phy@5 {\n\t\t\treg = <0x5>;\n\t\t};\n\t\tqsgmii_phy3: ethernet-phy@6 {\n\t\t\treg = <0x6>;\n\t\t};\n\t\tqsgmii_phy4: ethernet-phy@7 {\n\t\t\treg = <0x7>;\n\t\t};\n\t};\n};\n\n/* No QUICC engine functions on this board -\n * pins are used for other functions (GPIO, I2C etc.)\n */\n&uqe {\n\tstatus = \"disabled\";\n};\n\n/* LS1043S does not use the QorIQ AHCI\n * controller.\n */\n&sata {\n\tstatus = \"disabled\";\n};\n"
  },
  {
    "path": "target/linux/layerscape/files/arch/arm64/boot/dts/freescale/traverse-ls1043v.dts",
    "content": "/*\n * Device Tree Include file for Traverse LS1043V board.\n *\n * Copyright 2014-2015, Freescale Semiconductor\n * Copyright 2017, Traverse Technologies\n *\n * This file is dual-licensed: you can use it either under the terms\n * of the GPLv2 or the X11 license, at your option. Note that this dual\n * licensing only applies to this file, and not this project as a\n * whole.\n *\n *  a) This library is free software; you can redistribute it and/or\n *     modify it under the terms of the GNU General Public License as\n *     published by the Free Software Foundation; either version 2 of the\n *     License, or (at your option) any later version.\n *\n *     This library is distributed in the hope that it will be useful,\n *     but WITHOUT ANY WARRANTY; without even the implied warranty of\n *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n *     GNU General Public License for more details.\n *\n * Or, alternatively,\n *\n *  b) Permission is hereby granted, free of charge, to any person\n *     obtaining a copy of this software and associated documentation\n *     files (the \"Software\"), to deal in the Software without\n *     restriction, including without limitation the rights to use,\n *     copy, modify, merge, publish, distribute, sublicense, and/or\n *     sell copies of the Software, and to permit persons to whom the\n *     Software is furnished to do so, subject to the following\n *     conditions:\n *\n *     The above copyright notice and this permission notice shall be\n *     included in all copies or substantial portions of the Software.\n *\n *     THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n *     OTHER DEALINGS IN THE SOFTWARE.\n */\n\n/dts-v1/;\n#include \"fsl-ls1043a.dtsi\"\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"Traverse LS1043V\";\n\tcompatible = \"traverse,ls1043v\";\n\n\taliases {\n\t\tcrypto = &crypto;\n\t\tethernet0 = &EMAC0;\n\t\tethernet1 = &EMAC1;\n\t\tethernet2 = &EMAC2;\n\t\tethernet3 = &EMAC3;\n\t\tethernet4 = &EMAC4;\n\t\tethernet5 = &EMAC5;\n\t\tpca9555 = &pca9555;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tgpio0 {\n\t\t\tlabel = \"ls1043v:green:user0\";\n\t\t\tgpios = <&pca9555 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tgpio1 {\n\t\t\tlabel = \"ls1043v:yellow:user0\";\n\t\t\tgpios = <&pca9555 1 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tgpio2 {\n\t\t\tlabel = \"ls1043v:green:user1\";\n\t\t\tgpios = <&pca9555 2 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tgpio3 {\n\t\t\tlabel = \"ls1043v:yellow:user1\";\n\t\t\tgpios = <&pca9555 3 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tgpio4 {\n\t\t\tlabel = \"ls1043v:green:user2\";\n\t\t\tgpios = <&pca9555 4 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t\tgpio5 {\n\t\t\tlabel = \"ls1043v:yellow:wlan\";\n\t\t\tgpios = <&pca9555 5 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t\tgpio6 {\n\t\t\tlabel = \"ls1043v:yellow:wan\";\n\t\t\tgpios = <&pca9555 6 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tpoll-interval = <1000>;\n\t\tbutton@0 {\n\t\t\tlabel = \"Front button\";\n\t\t\tlinux,code = <KEY_SETUP>;\n\t\t\tgpios = <&pca9555 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tbutton@1 {\n\t\t\tlabel = \"Rear button\";\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tgpios = <&pca9555 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&i2c0 {\n\tstatus = \"okay\";\n\trtc@6f {\n\t\tcompatible = \"intersil,isl1208\";\n\t\treg = <0x6f>;\n\t};\n\n\tpca9555: pca9555@20 {\n\t\tcompatible = \"nxp,pca9555\";\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\treg = <0x20>;\n\t\tgpio-base = <0>;\n\t};\n\n\t/* CPU core temp sensor and VDD (1.0V) sensor */\n\tltc2990@4c {\n\t\tcompatible = \"lltc,ltc2990\";\n\t\treg = <0x4C>;\n\t\tlltc,meas-mode = <4 3>;\n\t};\n\n\t/* 3.3V and 5V monitor (may not be loaded on some SKUs) */\n\tltc2990@4f {\n\t\tcompatible = \"lltc,ltc2990\";\n\t\treg = <0x4F>;\n\t\tlltc,meas-mode = <6 3>;\n\t};\n};\n\n&ifc {\n\tstatus = \"okay\";\n\t#address-cells = <2>;\n\t#size-cells = <1>;\n\t/* Only NAND flash is used on this board */\n\tranges = <0x0 0x0 0x0 0x7e800000 0x00010000>;\n\n\tnand@1,0 {\n\t\tcompatible = \"fsl,ifc-nand\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\treg = <0x0 0x0 0x10000>;\n\t};\n};\n\n&duart0 {\n\tstatus = \"okay\";\n};\n\n&duart1 {\n\tstatus = \"okay\";\n};\n\n#include \"fsl-ls1043-post.dtsi\"\n\n&fman0 {\n\tEMAC0: ethernet@e0000 {\n\t\tphy-handle = <&qsgmii_phy1>;\n\t\tphy-connection-type = \"qsgmii\";\n\t\tlocal-mac-address = [0A 00 00 00 00 01];\n\t};\n\n\tEMAC1: ethernet@e2000 {\n\t\tphy-handle = <&qsgmii_phy2>;\n\t\tphy-connection-type = \"qsgmii\";\n\t\tlocal-mac-address = [0A 00 00 00 00 02];\n\t};\n\n\tEMAC2: ethernet@e8000 {\n\t\tphy-handle = <&qsgmii_phy3>;\n\t\tphy-connection-type = \"qsgmii\";\n\t\tlocal-mac-address = [0A 00 00 00 00 03];\n\t};\n\n\tEMAC3: ethernet@ea000 {\n\t\tphy-handle = <&qsgmii_phy4>;\n\t\tphy-connection-type = \"qsgmii\";\n\t\tlocal-mac-address = [0A 00 00 00 00 04];\n\t};\n\tEMAC4: ethernet@e4000 {\n\t\tphy-handle = <&rgmii_phy1>;\n\t\tphy-connection-type = \"rgmii\";\n\t\tlocal-mac-address = [0A 00 00 00 00 05];\n\t};\n\n\t/* Connection to VDSL SoC */\n\tEMAC5: ethernet@e6000 {\n\t\tphy-connection-type = \"rgmii-id\";\n\t\tlocal-mac-address = [00 00 00 00 00 06];\n\t\tfixed-link {\n\t\t\tspeed = <1000>;\n\t\t\tfull-duplex;\n\t\t};\n\t};\n\n\t/* 10G XFI interface - not in use on this platform */\n\tTENSFP: ethernet@f0000 {\n\t\tstatus = \"disabled\";\n\n\t\tphy-connection-type = \"sgmii\";\n\t\tfixed-link {\n\t\t\t/* NB: speed = 1000 and sgmii allows forward compatibility\n\t\t\t*  with both 1G and 10G, the same is not true\n\t\t\t*  in the reverse.\n\t\t\t*/\n\t\t\tspeed = <1000>;\n\t\t\tfull-duplex;\n\t\t};\n\t};\n\n\tmdio@fc000 {\n\t\trgmii_phy1: ethernet-phy@3 {\n\t\t\treg = <0x3>;\n\t\t};\n\t\tqsgmii_phy1: ethernet-phy@4 {\n\t\t\treg = <0x4>;\n\t\t};\n\t\tqsgmii_phy2: ethernet-phy@5 {\n\t\t\treg = <0x5>;\n\t\t};\n\t\tqsgmii_phy3: ethernet-phy@6 {\n\t\t\treg = <0x6>;\n\t\t};\n\t\tqsgmii_phy4: ethernet-phy@7 {\n\t\t\treg = <0x7>;\n\t\t};\n\t};\n};\n\n/* No QUICC engine functions on this board */\n&uqe {\n\tstatus = \"disabled\";\n};\n\n/* No SATA/AHCI on this board */\n&sata {\n\tstatus = \"disabled\";\n};\n"
  },
  {
    "path": "target/linux/layerscape/image/Makefile",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2016 Jiang Yutang <jiangyutang1978@gmail.com>\n\ninclude $(TOPDIR)/rules.mk\ninclude $(INCLUDE_DIR)/image.mk\n\nLS_SD_KERNELPART_SIZE = 40\nLS_SD_KERNELPART_OFFSET = 16\nLS_SD_ROOTFSPART_OFFSET = 64\nLS_SD_IMAGE_SIZE = $(shell echo $$((($(LS_SD_ROOTFSPART_OFFSET) + \\\n\t$(CONFIG_TARGET_ROOTFS_PARTSIZE)))))\n\n# The limitation of flash sysupgrade.bin is 1MB dtb + 16MB kernel + 32MB rootfs\nLS_SYSUPGRADE_IMAGE_SIZE = 49m\n\ndefine Image/Prepare\n\t# Build .dtb for all boards we may run on\n\t$(foreach dts,$(DEVICE_DTS_LIST),\n\t\t$(call Image/BuildDTB,$(DTS_DIR)/$(dts).dts,$(DTS_DIR)/$(dts).dtb)\n\t)\nendef\n\ndefine Build/ls-clean\n\trm -f $@\nendef\n\ndefine Build/ls-append\n\tdd if=$(STAGING_DIR_IMAGE)/$(1) >> $@\nendef\n\ndefine Build/ls-append-dtb\n\tdd if=$(DTS_DIR)/$(1).dtb >> $@\nendef\n\ndefine Build/ls-append-kernel\n\tmkdir -p $@.tmp && \\\n\tcp $(IMAGE_KERNEL) $@.tmp/fitImage && \\\n\tmake_ext4fs -J -L kernel -l \"$(LS_SD_KERNELPART_SIZE)M\" \\\n\t\t$(if $(SOURCE_DATE_EPOCH),-T $(SOURCE_DATE_EPOCH)) \\\n\t\t\"$@.kernel.part\" \"$@.tmp\" && \\\n\tdd if=$@.kernel.part >> $@ && \\\n\trm -rf $@.tmp && \\\n\trm -f $@.kernel.part\nendef\n\ndefine Build/ls-append-sdhead\n\t./gen_sdcard_head_img.sh $(STAGING_DIR_IMAGE)/$(1)-sdcard-head.img \\\n\t\t$(LS_SD_KERNELPART_OFFSET) $(LS_SD_KERNELPART_SIZE) \\\n\t\t$(LS_SD_ROOTFSPART_OFFSET) $(CONFIG_TARGET_ROOTFS_PARTSIZE)\n\tdd if=$(STAGING_DIR_IMAGE)/$(1)-sdcard-head.img >> $@\nendef\n\ndefine Build/traverse-fit\n\t./mkits-multiple-config.sh -o $@.its -A $(LINUX_KARCH) \\\n\t\t-v $(LINUX_VERSION) -k $@ -a $(KERNEL_LOADADDR) \\\n\t\t-e $(if $(KERNEL_ENTRY),$(KERNEL_ENTRY),$(KERNEL_LOADADDR)) \\\n\t\t-C gzip -c 1 -c 2 \\\n\t\t-d $(DEVICE_DTS_DIR)/freescale/traverse-ls1043s.dtb \\\n\t\t-D \"Traverse_LS1043S\" -n \"ls1043s\" -a $(FDT_LOADADDR) -c 1 \\\n\t\t-d $(DEVICE_DTS_DIR)/freescale/traverse-ls1043v.dtb \\\n\t\t-D \"Traverse_LS1043V\" -n \"ls1043v\" -a $(FDT_LOADADDR) -c 2\n\tPATH=$(LINUX_DIR)/scripts/dtc:$(PATH) mkimage -f $@.its $@.new\n\t@mv -f $@.new $@\nendef\n\ndefine Device/fix-sysupgrade\n  DEVICE_COMPAT_VERSION := 2.0\n  DEVICE_COMPAT_MESSAGE := DTB was added to sysupgrade. Image format is different. \\\n\tTo use sysupgrade You need to change firmware partition in bootargs to \"49m@0xf00000(firmware)\" and saveenv. \\\n\tAfter that, You can use \"sysupgrade -F\".\nendef\n\ndefine Device/rework-sdcard-images\n  DEVICE_COMPAT_VERSION := 2.0\n  DEVICE_COMPAT_MESSAGE := SD-card images were changed to squashfs + ext4 overlay combined images. \\\n\tIt is required to flash the entire sd-card again and manually copy config.\nendef\n\ninclude $(SUBTARGET).mk\n\n$(eval $(call BuildImage))\n"
  },
  {
    "path": "target/linux/layerscape/image/armv7.mk",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright 2018-2020 NXP\n\ndefine Device/Default\n  PROFILES := Default\n  FILESYSTEMS := squashfs\n  IMAGES := firmware.bin sysupgrade.bin\n  KERNEL := kernel-bin | uImage none\n  KERNEL_INITRAMFS = kernel-bin | gzip | fit gzip $$(DTS_DIR)/$$(DEVICE_DTS).dtb\n  KERNEL_NAME := zImage\n  KERNEL_LOADADDR := 0x80008000\n  DEVICE_DTS = $(lastword $(subst _, ,$(1)))\n  IMAGE_SIZE := 64m\n  IMAGE/sysupgrade.bin = \\\n    ls-append-dtb $$(DEVICE_DTS) | pad-to 1M | \\\n    append-kernel | pad-to 17M | \\\n    append-rootfs | pad-rootfs | \\\n    check-size $(LS_SYSUPGRADE_IMAGE_SIZE) | append-metadata\nendef\n\ndefine Device/fsl-sdboot\n  KERNEL = kernel-bin | gzip | fit gzip $$(DTS_DIR)/$$(DEVICE_DTS).dtb\n  IMAGES := sdcard.img.gz sysupgrade.bin\n  IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata\nendef\n\ndefine Device/fsl_ls1021a-twr\n  $(Device/fix-sysupgrade)\n  DEVICE_VENDOR := NXP\n  DEVICE_MODEL := TWR-LS1021A\n  DEVICE_VARIANT := Default\n  DEVICE_PACKAGES += layerscape-rcw\n  IMAGE/firmware.bin := \\\n    ls-clean | \\\n    ls-append $(1)-rcw.bin | pad-to 1M | \\\n    ls-append $(1)-uboot.bin | pad-to 3M | \\\n    ls-append $(1)-uboot-env.bin | pad-to 15M | \\\n    ls-append-dtb $$(DEVICE_DTS) | pad-to 16M | \\\n    append-kernel | pad-to 32M | \\\n    append-rootfs | pad-rootfs | check-size\nendef\nTARGET_DEVICES += fsl_ls1021a-twr\n\ndefine Device/fsl_ls1021a-twr-sdboot\n  $(Device/rework-sdcard-images)\n  $(Device/fsl-sdboot)\n  DEVICE_VENDOR := NXP\n  DEVICE_MODEL := TWR-LS1021A\n  DEVICE_VARIANT := SD Card Boot\n  DEVICE_DTS := ls1021a-twr\n  IMAGE/sdcard.img.gz := \\\n    ls-clean | \\\n    ls-append-sdhead $(1) | pad-to 4K | \\\n    ls-append $(1)-uboot.bin | pad-to 3M | \\\n    ls-append $(1)-uboot-env.bin | pad-to 16M | \\\n    ls-append-kernel | pad-to $(LS_SD_ROOTFSPART_OFFSET)M | \\\n    append-rootfs | pad-to $(LS_SD_IMAGE_SIZE)M | gzip\nendef\nTARGET_DEVICES += fsl_ls1021a-twr-sdboot\n\ndefine Device/fsl_ls1021a-iot-sdboot\n  $(Device/rework-sdcard-images)\n  $(Device/fsl-sdboot)\n  DEVICE_VENDOR := NXP\n  DEVICE_MODEL := LS1021A-IoT\n  DEVICE_VARIANT := SD Card Boot\n  DEVICE_DTS := ls1021a-iot\n  SUPPORTED_DEVICES :=\n  IMAGE/sdcard.img.gz := \\\n    ls-clean | \\\n    ls-append-sdhead $(1) | pad-to 4K | \\\n    ls-append $(1)-uboot.bin | pad-to 1M | \\\n    ls-append $(1)-uboot-env.bin | pad-to 16M | \\\n    ls-append-kernel | pad-to $(LS_SD_ROOTFSPART_OFFSET)M | \\\n    append-rootfs | pad-to $(LS_SD_IMAGE_SIZE)M | gzip\nendef\nTARGET_DEVICES += fsl_ls1021a-iot-sdboot\n"
  },
  {
    "path": "target/linux/layerscape/image/armv8_64b.mk",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright 2018-2020 NXP\n\ndefine Device/Default\n  PROFILES := Default\n  IMAGES := firmware.bin sysupgrade.bin\n  FILESYSTEMS := squashfs\n  KERNEL := kernel-bin | gzip | uImage gzip\n  KERNEL_INITRAMFS = kernel-bin | gzip | fit gzip $$(DTS_DIR)/$$(DEVICE_DTS).dtb\nifdef CONFIG_LINUX_5_4\n  KERNEL_LOADADDR := 0x80080000\nelse\n  KERNEL_LOADADDR := 0x80000000\nendif\n  DEVICE_DTS = freescale/$(subst _,-,$(1))\n  IMAGE_SIZE := 64m\n  IMAGE/sysupgrade.bin = \\\n    ls-append-dtb $$(DEVICE_DTS) | pad-to 1M | \\\n    append-kernel | pad-to 17M | \\\n    append-rootfs | pad-rootfs | \\\n    check-size $(LS_SYSUPGRADE_IMAGE_SIZE) | append-metadata\nendef\n\ndefine Device/fsl-sdboot\n  KERNEL = kernel-bin | gzip | fit gzip $$(DTS_DIR)/$$(DEVICE_DTS).dtb\n  IMAGES := sdcard.img.gz sysupgrade.bin\n  IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata\nendef\n\ndefine Device/fsl_ls1012a-frdm\n  DEVICE_VENDOR := NXP\n  DEVICE_MODEL := FRDM-LS1012A\n  DEVICE_PACKAGES += \\\n    layerscape-ppfe \\\n    tfa-ls1012a-frdm \\\n    kmod-ppfe\n  BLOCKSIZE := 256KiB\n  IMAGE/firmware.bin := \\\n    ls-clean | \\\n    ls-append $(1)-bl2.pbl | pad-to 1M | \\\n    ls-append $(1)-fip.bin | pad-to 5M | \\\n    ls-append $(1)-uboot-env.bin | pad-to 10M | \\\n    ls-append pfe.itb | pad-to 15M | \\\n    ls-append-dtb $$(DEVICE_DTS) | pad-to 16M | \\\n    append-kernel | pad-to $$(BLOCKSIZE) | \\\n    append-rootfs | pad-rootfs | check-size\n  IMAGE/sysupgrade.bin := \\\n    append-kernel | pad-to $$(BLOCKSIZE) | \\\n    append-rootfs | pad-rootfs | \\\n    check-size $(LS_SYSUPGRADE_IMAGE_SIZE) | append-metadata\n  KERNEL := kernel-bin | gzip | fit gzip $$(DTS_DIR)/$$(DEVICE_DTS).dtb\n  KERNEL_INITRAMFS := kernel-bin | fit none $$(DTS_DIR)/$$(DEVICE_DTS).dtb\nendef\nTARGET_DEVICES += fsl_ls1012a-frdm\n\ndefine Device/fsl_ls1012a-rdb\n  $(Device/fix-sysupgrade)\n  DEVICE_VENDOR := NXP\n  DEVICE_MODEL := LS1012A-RDB\n  DEVICE_PACKAGES += \\\n    layerscape-ppfe \\\n    tfa-ls1012a-rdb \\\n    kmod-hwmon-ina2xx \\\n    kmod-iio-fxas21002c-i2c \\\n    kmod-iio-fxos8700-i2c \\\n    kmod-ppfe\n  IMAGE/firmware.bin := \\\n    ls-clean | \\\n    ls-append $(1)-bl2.pbl | pad-to 1M | \\\n    ls-append $(1)-fip.bin | pad-to 5M | \\\n    ls-append $(1)-uboot-env.bin | pad-to 10M | \\\n    ls-append pfe.itb | pad-to 15M | \\\n    ls-append-dtb $$(DEVICE_DTS) | pad-to 16M | \\\n    append-kernel | pad-to 32M | \\\n    append-rootfs | pad-rootfs | check-size\nendef\nTARGET_DEVICES += fsl_ls1012a-rdb\n\ndefine Device/fsl_ls1012a-frwy-sdboot\n  $(Device/rework-sdcard-images)\n  $(Device/fsl-sdboot)\n  DEVICE_VENDOR := NXP\n  DEVICE_MODEL := FRWY-LS1012A\n  DEVICE_PACKAGES += \\\n    layerscape-ppfe \\\n    tfa-ls1012a-frwy-sdboot \\\n    kmod-ppfe\n  DEVICE_DTS := freescale/fsl-ls1012a-frwy\n  IMAGES += firmware.bin\n  IMAGE/firmware.bin := \\\n    ls-clean | \\\n    ls-append $(1)-bl2.pbl | pad-to 128K | \\\n    ls-append pfe.itb | pad-to 384K | \\\n    ls-append $(1)-fip.bin | pad-to 1856K | \\\n    ls-append $(1)-uboot-env.bin | pad-to 2048K | \\\n    check-size 2097153\n  IMAGE/sdcard.img.gz := \\\n    ls-clean | \\\n    ls-append-sdhead $(1) | pad-to 16M | \\\n    ls-append-kernel | pad-to $(LS_SD_ROOTFSPART_OFFSET)M | \\\n    append-rootfs | pad-to $(LS_SD_IMAGE_SIZE)M | gzip\nendef\nTARGET_DEVICES += fsl_ls1012a-frwy-sdboot\n\ndefine Device/fsl_ls1043a-rdb\n  $(Device/fix-sysupgrade)\n  DEVICE_VENDOR := NXP\n  DEVICE_MODEL := LS1043A-RDB\n  DEVICE_VARIANT := Default\n  DEVICE_PACKAGES += \\\n    layerscape-fman \\\n    tfa-ls1043a-rdb \\\n    fmc fmc-eth-config \\\n    kmod-ahci-qoriq \\\n    kmod-hwmon-ina2xx \\\n    kmod-hwmon-lm90\nifdef CONFIG_LINUX_5_4\n  DEVICE_DTS := freescale/fsl-ls1043a-rdb-sdk\nelse\n  DEVICE_DTS := freescale/fsl-ls1043a-rdb\nendif\n  IMAGE/firmware.bin := \\\n    ls-clean | \\\n    ls-append $(1)-bl2.pbl | pad-to 1M | \\\n    ls-append $(1)-fip.bin | pad-to 5M | \\\n    ls-append $(1)-uboot-env.bin | pad-to 9M | \\\n    ls-append $(1)-fman.bin | pad-to 15M | \\\n    ls-append-dtb $$(DEVICE_DTS) | pad-to 16M | \\\n    append-kernel | pad-to 32M | \\\n    append-rootfs | pad-rootfs | check-size\nendef\nTARGET_DEVICES += fsl_ls1043a-rdb\n\ndefine Device/fsl_ls1043a-rdb-sdboot\n  $(Device/rework-sdcard-images)\n  $(Device/fsl-sdboot)\n  DEVICE_VENDOR := NXP\n  DEVICE_MODEL := LS1043A-RDB\n  DEVICE_VARIANT := SD Card Boot\n  DEVICE_PACKAGES += \\\n    layerscape-fman \\\n    tfa-ls1043a-rdb-sdboot \\\n    fmc fmc-eth-config \\\n    kmod-ahci-qoriq \\\n    kmod-hwmon-ina2xx \\\n    kmod-hwmon-lm90\nifdef CONFIG_LINUX_5_4\n  DEVICE_DTS := freescale/fsl-ls1043a-rdb-sdk\nelse\n  DEVICE_DTS := freescale/fsl-ls1043a-rdb\nendif\n  IMAGE/sdcard.img.gz := \\\n    ls-clean | \\\n    ls-append-sdhead $(1) | pad-to 4K | \\\n    ls-append $(1)-bl2.pbl | pad-to 1M | \\\n    ls-append $(1)-fip.bin | pad-to 5M | \\\n    ls-append $(1)-uboot-env.bin | pad-to 9M | \\\n    ls-append fsl_ls1043a-rdb-fman.bin | pad-to 16M | \\\n    ls-append-kernel | pad-to $(LS_SD_ROOTFSPART_OFFSET)M | \\\n    append-rootfs | pad-to $(LS_SD_IMAGE_SIZE)M | gzip\nendef\nTARGET_DEVICES += fsl_ls1043a-rdb-sdboot\n\ndefine Device/fsl_ls1046a-frwy\n  DEVICE_VENDOR := NXP\n  DEVICE_MODEL := FRWY-LS1046A\n  DEVICE_VARIANT := Default\n  DEVICE_PACKAGES += \\\n    layerscape-fman \\\n    tfa-ls1046a-frwy\nifdef CONFIG_LINUX_5_4\n  DEVICE_DTS := freescale/fsl-ls1046a-frwy-sdk\nelse\n  DEVICE_DTS := freescale/fsl-ls1046a-frwy\nendif\n  IMAGE/firmware.bin := \\\n    ls-clean | \\\n    ls-append $(1)-bl2.pbl | pad-to 1M | \\\n    ls-append $(1)-fip.bin | pad-to 5M | \\\n    ls-append $(1)-uboot-env.bin | pad-to 9M | \\\n    ls-append fsl_ls1046a-rdb-fman.bin | pad-to 15M | \\\n    ls-append-dtb $$(DEVICE_DTS) | pad-to 16M | \\\n    append-kernel | pad-to 32M | \\\n    append-rootfs | pad-rootfs | check-size\nendef\nTARGET_DEVICES += fsl_ls1046a-frwy\n\ndefine Device/fsl_ls1046a-frwy-sdboot\n  $(Device/fsl-sdboot)\n  DEVICE_VENDOR := NXP\n  DEVICE_MODEL := FRWY-LS1046A\n  DEVICE_VARIANT := SD Card Boot\n  DEVICE_PACKAGES += \\\n    layerscape-fman \\\n    tfa-ls1046a-frwy-sdboot\nifdef CONFIG_LINUX_5_4\n  DEVICE_DTS := freescale/fsl-ls1046a-frwy-sdk\nelse\n  DEVICE_DTS := freescale/fsl-ls1046a-frwy\nendif\n  IMAGE/sdcard.img.gz := \\\n    ls-clean | \\\n    ls-append-sdhead $(1) | pad-to 4K | \\\n    ls-append $(1)-bl2.pbl | pad-to 1M | \\\n    ls-append $(1)-fip.bin | pad-to 5M | \\\n    ls-append $(1)-uboot-env.bin | pad-to 9M | \\\n    ls-append fsl_ls1046a-rdb-fman.bin | pad-to 16M | \\\n    ls-append-kernel | pad-to $(LS_SD_ROOTFSPART_OFFSET)M | \\\n    append-rootfs | pad-to $(LS_SD_IMAGE_SIZE)M | gzip\nendef\nTARGET_DEVICES += fsl_ls1046a-frwy-sdboot\n\ndefine Device/fsl_ls1046a-rdb\n  $(Device/fix-sysupgrade)\n  DEVICE_VENDOR := NXP\n  DEVICE_MODEL := LS1046A-RDB\n  DEVICE_VARIANT := Default\n  DEVICE_PACKAGES += \\\n    layerscape-fman \\\n    tfa-ls1046a-rdb \\\n    fmc fmc-eth-config \\\n    kmod-ahci-qoriq \\\n    kmod-hwmon-ina2xx \\\n    kmod-hwmon-lm90\nifdef CONFIG_LINUX_5_4\n  DEVICE_DTS := freescale/fsl-ls1046a-rdb-sdk\nelse\n  DEVICE_DTS := freescale/fsl-ls1046a-rdb\nendif\n  IMAGE/firmware.bin := \\\n    ls-clean | \\\n    ls-append $(1)-bl2.pbl | pad-to 1M | \\\n    ls-append $(1)-fip.bin | pad-to 5M | \\\n    ls-append $(1)-uboot-env.bin | pad-to 9M | \\\n    ls-append $(1)-fman.bin | pad-to 15M | \\\n    ls-append-dtb $$(DEVICE_DTS) | pad-to 16M | \\\n    append-kernel | pad-to 32M | \\\n    append-rootfs | pad-rootfs | check-size\nendef\nTARGET_DEVICES += fsl_ls1046a-rdb\n\ndefine Device/fsl_ls1046a-rdb-sdboot\n  $(Device/rework-sdcard-images)\n  $(Device/fsl-sdboot)\n  DEVICE_VENDOR := NXP\n  DEVICE_MODEL := LS1046A-RDB\n  DEVICE_VARIANT := SD Card Boot\n  DEVICE_PACKAGES += \\\n    layerscape-fman \\\n    tfa-ls1046a-rdb-sdboot \\\n    fmc fmc-eth-config \\\n    kmod-ahci-qoriq \\\n    kmod-hwmon-ina2xx \\\n    kmod-hwmon-lm90\nifdef CONFIG_LINUX_5_4\n  DEVICE_DTS := freescale/fsl-ls1046a-rdb-sdk\nelse\n  DEVICE_DTS := freescale/fsl-ls1046a-rdb\nendif\n  IMAGE/sdcard.img.gz := \\\n    ls-clean | \\\n    ls-append-sdhead $(1) | pad-to 4K | \\\n    ls-append $(1)-bl2.pbl | pad-to 1M | \\\n    ls-append $(1)-fip.bin | pad-to 5M | \\\n    ls-append $(1)-uboot-env.bin | pad-to 9M | \\\n    ls-append fsl_ls1046a-rdb-fman.bin | pad-to 16M | \\\n    ls-append-kernel | pad-to $(LS_SD_ROOTFSPART_OFFSET)M | \\\n    append-rootfs | pad-to $(LS_SD_IMAGE_SIZE)M | gzip\nendef\nTARGET_DEVICES += fsl_ls1046a-rdb-sdboot\n\ndefine Device/fsl_ls1088a-rdb\n  $(Device/fix-sysupgrade)\n  DEVICE_VENDOR := NXP\n  DEVICE_MODEL := LS1088A-RDB\n  DEVICE_VARIANT := Default\n  DEVICE_PACKAGES += \\\n    layerscape-mc \\\n    layerscape-dpl \\\n    tfa-ls1088a-rdb \\\n    restool \\\n    kmod-ahci-qoriq \\\n    kmod-hwmon-ina2xx \\\n    kmod-hwmon-lm90\n  IMAGE/firmware.bin := \\\n    ls-clean | \\\n    ls-append $(1)-bl2.pbl | pad-to 1M | \\\n    ls-append $(1)-fip.bin | pad-to 5M | \\\n    ls-append $(1)-uboot-env.bin | pad-to 10M | \\\n    ls-append $(1)-mc.itb | pad-to 13M | \\\n    ls-append $(1)-dpl.dtb | pad-to 14M | \\\n    ls-append $(1)-dpc.dtb | pad-to 15M | \\\n    ls-append-dtb $$(DEVICE_DTS) | pad-to 16M | \\\n    append-kernel | pad-to 32M | \\\n    append-rootfs | pad-rootfs | check-size\nendef\nTARGET_DEVICES += fsl_ls1088a-rdb\n\ndefine Device/fsl_ls1088a-rdb-sdboot\n  $(Device/rework-sdcard-images)\n  $(Device/fsl-sdboot)\n  DEVICE_VENDOR := NXP\n  DEVICE_MODEL := LS1088A-RDB\n  DEVICE_VARIANT := SD Card Boot\n  DEVICE_PACKAGES += \\\n    layerscape-mc \\\n    layerscape-dpl \\\n    tfa-ls1088a-rdb-sdboot \\\n    restool \\\n    kmod-ahci-qoriq \\\n    kmod-hwmon-ina2xx \\\n    kmod-hwmon-lm90\n  DEVICE_DTS := freescale/fsl-ls1088a-rdb\n  IMAGE/sdcard.img.gz := \\\n    ls-clean | \\\n    ls-append-sdhead $(1) | pad-to 4K | \\\n    ls-append $(1)-bl2.pbl | pad-to 1M | \\\n    ls-append $(1)-fip.bin | pad-to 5M | \\\n    ls-append $(1)-uboot-env.bin | pad-to 10M | \\\n    ls-append fsl_ls1088a-rdb-mc.itb | pad-to 13M | \\\n    ls-append fsl_ls1088a-rdb-dpl.dtb | pad-to 14M | \\\n    ls-append fsl_ls1088a-rdb-dpc.dtb | pad-to 16M | \\\n    ls-append-kernel | pad-to $(LS_SD_ROOTFSPART_OFFSET)M | \\\n    append-rootfs | pad-to $(LS_SD_IMAGE_SIZE)M | gzip\nendef\nTARGET_DEVICES += fsl_ls1088a-rdb-sdboot\n\ndefine Device/fsl_ls2088a-rdb\n  $(Device/fix-sysupgrade)\n  DEVICE_VENDOR := NXP\n  DEVICE_MODEL := LS2088ARDB\n  DEVICE_PACKAGES += \\\n    layerscape-mc \\\n    layerscape-dpl \\\n    tfa-ls2088a-rdb \\\n    restool \\\n    kmod-ahci-qoriq\n  IMAGE/firmware.bin := \\\n    ls-clean | \\\n    ls-append $(1)-bl2.pbl | pad-to 1M | \\\n    ls-append $(1)-fip.bin | pad-to 5M | \\\n    ls-append $(1)-uboot-env.bin | pad-to 10M | \\\n    ls-append $(1)-mc.itb | pad-to 13M | \\\n    ls-append $(1)-dpl.dtb | pad-to 14M | \\\n    ls-append $(1)-dpc.dtb | pad-to 15M | \\\n    ls-append-dtb $$(DEVICE_DTS) | pad-to 16M | \\\n    append-kernel | pad-to 32M | \\\n    append-rootfs | pad-rootfs | check-size\nendef\nTARGET_DEVICES += fsl_ls2088a-rdb\n\ndefine Device/fsl_lx2160a-rdb\n  DEVICE_VENDOR := NXP\n  DEVICE_MODEL := LX2160A-RDB\n  DEVICE_VARIANT := Rev2.0 silicon\n  DEVICE_PACKAGES += \\\n    layerscape-mc \\\n    layerscape-dpl \\\n    layerscape-ddr-phy \\\n    tfa-lx2160a-rdb \\\n    restool\n  IMAGE/firmware.bin := \\\n    ls-clean | \\\n    ls-append $(1)-bl2.pbl | pad-to 1M | \\\n    ls-append $(1)-fip.bin | pad-to 5M | \\\n    ls-append $(1)-uboot-env.bin | pad-to 8M | \\\n    ls-append $(1)-fip_ddr_all.bin | pad-to 10M | \\\n    ls-append $(1)-mc.itb | pad-to 13M | \\\n    ls-append $(1)-dpl.dtb | pad-to 14M | \\\n    ls-append $(1)-dpc.dtb | pad-to 15M | \\\n    ls-append-dtb $$(DEVICE_DTS) | pad-to 16M | \\\n    append-kernel | pad-to 32M | \\\n    append-rootfs | pad-rootfs | check-size\nendef\nTARGET_DEVICES += fsl_lx2160a-rdb\n\ndefine Device/fsl_lx2160a-rdb-sdboot\n  $(Device/fsl-sdboot)\n  DEVICE_VENDOR := NXP\n  DEVICE_MODEL := LX2160A-RDB\n  DEVICE_VARIANT := Rev2.0 silicon SD Card Boot\n  DEVICE_PACKAGES += \\\n    layerscape-mc \\\n    layerscape-dpl \\\n    layerscape-ddr-phy \\\n    tfa-lx2160a-rdb-sdboot \\\n    restool\n  DEVICE_DTS := freescale/fsl-lx2160a-rdb\n  IMAGE/sdcard.img.gz := \\\n    ls-clean | \\\n    ls-append-sdhead $(1) | pad-to 4K | \\\n    ls-append $(1)-bl2.pbl | pad-to 1M | \\\n    ls-append $(1)-fip.bin | pad-to 5M | \\\n    ls-append $(1)-uboot-env.bin | pad-to 8M | \\\n    ls-append fsl_lx2160a-rdb-fip_ddr_all.bin | pad-to 10M | \\\n    ls-append fsl_lx2160a-rdb-mc.itb | pad-to 13M | \\\n    ls-append fsl_lx2160a-rdb-dpl.dtb | pad-to 14M | \\\n    ls-append fsl_lx2160a-rdb-dpc.dtb | pad-to 16M | \\\n    ls-append-kernel | pad-to $(LS_SD_ROOTFSPART_OFFSET)M | \\\n    append-rootfs | pad-to $(LS_SD_IMAGE_SIZE)M | gzip\nendef\nTARGET_DEVICES += fsl_lx2160a-rdb-sdboot\n\ndefine Device/traverse_ls1043\n  DEVICE_VENDOR := Traverse\n  DEVICE_MODEL := LS1043 Boards\n  KERNEL_NAME := Image\n  KERNEL_SUFFIX := -kernel.itb\n  KERNEL_INSTALL := 1\n  FDT_LOADADDR = 0x90000000\n  FILESYSTEMS := ubifs\n  MKUBIFS_OPTS := -m 1 -e 262016 -c 128\n  DEVICE_PACKAGES += \\\n    layerscape-fman \\\n    uboot-envtools \\\n    kmod-i2c-mux-pca954x \\\n    kmod-hwmon-core \\\n    kmod-gpio-pca953x kmod-input-gpio-keys-polled \\\n    kmod-rtc-isl1208\n  DEVICE_DESCRIPTION = \\\n    Build images for Traverse LS1043 boards. This generates a single image \\\n    capable of booting on any of the boards in this family.\n  DEVICE_DTS = freescale/traverse-ls1043s\n  DEVICE_DTS_DIR = $(LINUX_DIR)/arch/arm64/boot/dts\n  DEVICE_DTS_CONFIG = ls1043s\n  KERNEL := kernel-bin | gzip | traverse-fit gzip $$(DTS_DIR)/$$(DEVICE_DTS).dtb\n  KERNEL_INITRAMFS := kernel-bin | gzip | fit gzip $$(DTS_DIR)/$$(DEVICE_DTS).dtb\n  IMAGES = root sysupgrade.bin\n  IMAGE/root = append-rootfs\n  IMAGE/sysupgrade.bin = sysupgrade-tar | append-metadata\n  MKUBIFS_OPTS := -m 2048 -e 124KiB -c 4096\n  SUPPORTED_DEVICES := traverse,ls1043s traverse,ls1043v\nendef\nTARGET_DEVICES += traverse_ls1043\n"
  },
  {
    "path": "target/linux/layerscape/image/gen_sdcard_head_img.sh",
    "content": "#!/bin/sh\n# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright 2018 NXP\n\nset -x\n[ $# -eq 5 ] || {\n    echo \"SYNTAX: $0 <file> <kernel part offset> <kernel size> <rootfs part offset> <rootfs size>\"\n    exit 1\n}\n\nOUTPUT=\"$1\"\nKERNELOFFSET=\"$(($2 * 1024))\"\nKERNELSIZE=\"$3\"\nROOTFSOFFSET=\"$(($4 * 1024))\"\nROOTFSSIZE=\"$5\"\n\nhead=4\nsect=63\n\nset $(ptgen -o $OUTPUT -h $head -s $sect -t 83 -p ${KERNELSIZE}M@${KERNELOFFSET} -p ${ROOTFSSIZE}M@${ROOTFSOFFSET})\n"
  },
  {
    "path": "target/linux/layerscape/image/mkits-multiple-config.sh",
    "content": "#!/usr/bin/env bash\n# SPDX-License-Identifier: GPL-2.0-or-later\n#\n# Author: Jason Wu <jason.hy.wu@gmail.com>\n# with modifications for multi-DTB-same-image by:\n# Mathew McBride <matt@traverse.com.au>\n#\n# U-Boot firmware supports the booting of images in the Flattened Image\n# Tree (FIT) format.  The FIT format uses a device tree structure to\n# describe a kernel image, device tree blob, ramdisk, etc.  This script\n# creates an Image Tree Source (.its file) which can be passed to the\n# 'mkimage' utility to generate an Image Tree Blob (.itb file).  The .itb\n# file can then be booted by U-Boot (or other bootloaders which support\n# FIT images).  See doc/uImage.FIT/howto.txt in U-Boot source code for\n# additional information on FIT images.\n#\n# This tools supports:\n#   - multi-configuration\n#   - multi-image support - multiple kernel/fdt/ramdsik\n#   - per image configuration:\n#     - hash algorithm and generated required subnodes\n#     - compression\n#     - signature and generated required subnodes\n#\nset -e\n\n# image config limit\nMAX_IMG=50\n# conf config limit\nMAX_CONF=10\n\n# declare main data array\ndeclare -a img_array\ndeclare -a conf_array\n\n# initialize array with empty values\nfor (( index=1; index<=$MAX_IMG; index++ )); do\n\tdeclare -a img$index\n\tfor i in {0..13}; do\n\t\teval img${index}[$i]=\"\"\n\tdone\ndone\n\nfor (( index=1; index<=$MAX_CONF; index++ )); do\n\tdeclare -a conf$index\n\tfor i in {0..9}; do\n\t\teval conf${index}[$i]=\"\"\n\tdone\ndone\n\n# imgX array index information\n#\t0: type of image - kernel, fdt, ramdsik\n#\t1: image location\n#\t2: image index\n#\t3: loadaddr of image\n#\t4: entrypoint of image\n#\t5: compression\n#\t6: hash algorithm\n#\t7: part of the configuration\n#\t8: Human friend name for the image\n#\t9: key file name\n#\t10: signature\n# \t11: conf friendly name\n\n# confX array index information\n#\t0: conf number\n#\t1: kernel conf\n#\t2: fdt conf\n#\t3: rootfs conf\n#\t4: kernel key file\n#\t5: fdt key file\n#\t6: rootfs key file\n#\t7: kernel sign_algorithm\n#\t8: fdt sign_algorithm\n#\t9: rootfs sign_algorithm\n#\t10: conf friendly name\n\nusage() {\n\techo \"Usage: `basename $0` -A arch -v version -o its_file\" \\\n\t\t\"-k kernel -a addr -e entry [-C none] [-h sha1] [-c conf]\"\n\techo -e \"Example1:\\n\\tkernel image ker_img1 with no compression +\"\n\techo -e \"\\tsha1 hash + fdt dtb1 with sha1 and crc32 hash for conf 1\"\n\techo -e \"\\t $ `basename $0` -A arm -v 4.4 \\ \"\n\techo -e \"\\t      -k ker_img1 -C none -h sha1 -e 0x8000 -a 0x8000 -c 1 \\ \"\n\techo -e \"\\t      -d dtb1 -h sha1 -h crc32 -c 1\\n\"\n\techo \"General settings:\"\n\techo -e \"\\t-A ==> set architecture to 'arch'\"\n\techo -e \"\\t-v ==> set kernel version to 'version'\"\n\techo -e \"\\t-o ==> create output file 'its_file' [optional]\"\n\techo \"Input image type:\"\n\techo -e \"\\t-k ==> kernel image 'kernel'\"\n\techo -e \"\\t-d ==> Device Tree Blob 'dtb'\"\n\techo -e \"\\t-r ==> ramdisk image 'ramdisk\"\n\techo \"Per image configurations:\"\n\techo -e \"\\t-C ==> set compression type 'comp'\"\n\techo -e \"\\t-c ==> set image config (multiple -c allowed)\"\n\techo -e \"\\t-a ==> set load address to 'addr' (hex)\"\n\techo -e \"\\t-e ==> set entry point to 'entry' (hex)\"\n\techo -e \"\\t-D ==> human friendly 'name' (one word only)\"\n\techo -e \"\\t-h ==> set hash algorithm (multiple -h allowed)\"\n\techo -e \"\\t-s ==> set signature for given config image\"\n\techo -e \"\\t-K ==> set key file for given config image\"\n\texit 1\n}\n\narray_check()\n{\n\tlocal a=999\n\tlocal max_a=0\n\tlocal max_i=0\n\n\tif echo $1 | grep -q img; then\n\t\tmax_a=$MAX_IMG\n\t\tmax_i=13\n\t\tlet a=$(echo $1 | awk -F \"img\" '{print $2}')\n\telif echo $1 | grep -q conf; then\n\t\tmax_a=$MAX_CONF\n\t\tmax_i=10\n\t\tlet a=$(echo $1 | awk -F \"conf\" '{print $2}')\n\tfi\n\tif [ ${a} -lt 0 -o ${a} -gt ${max_a} -o \\\n\t\t${2} -lt 0 -o ${2} -gt ${max_i} ]; then\n\t\techo \"WARNING: Invalid array name, skipping!!!\"\n\t\treturn 255\n\tfi\n}\n\n#\n# $1:\tarray name\n# $2:\tindex\n# $3:\tvalue\n# $4:\tappend operation\n#\narray_put()\n{\n\t# check if array is declared\n\tarray_check $1 $2 || return 0\n\tif [ -z \"$4\" ]; then\n\t\teval $1[$2]=$3\n\telse\n\t\teval $1[$2]=\\\"\\${$1[$2]} $3\\\"\n\tfi\n}\n\n#\n# $1:\tarray name\n# $2:\tindex\n#\narray_get()\n{\n\tlocal val\n\teval val=\\${$1[$2]}\n\techo $val\n}\n\nparse_args() {\n\tlocal i=-1 k=-1 d=-1 r=-1\n\twhile getopts \":A:a:C:c:D:d:e:h:k:K:o:v:r:s:n:\" OPTION; do\n\t\tcase $OPTION in\n\t\t\tA ) ARCH=$OPTARG;;\n\t\t\ta ) array_put img$i 3 $OPTARG;;\n\t\t\tC ) value_sanity_chk compression $OPTARG;\n\t\t\t\tarray_put img$i 5 $OPTARG;;\n\t\t\tc ) array_put img$i 7 $OPTARG append;;\n\t\t\tD ) array_put img$i 8 $OPTARG;;\n\t\t\td ) i=$(($i + 1));\n\t\t\t\td=$(($d + 1));\n\t\t\t\timg_array[$i]=img$i;\n\t\t\t\tarray_put img$i 0 fdt;\n\t\t\t\tarray_put img$i 1 $OPTARG;\n\t\t\t\tarray_put img$i 2 $d;\n\t\t\t\t;;\n\t\t\te ) array_put img$i 4 $OPTARG;;\n\t\t\th ) value_sanity_chk hash $OPTARG;\n\t\t\t\tarray_put img$i 6 $OPTARG append;;\n\t\t\tk ) i=$(($i + 1));\n\t\t\t\tk=$(($k + 1));\n\t\t\t\timg_array[$i]=img$i;\n\t\t\t\tarray_put img$i 0 \"kernel\";\n\t\t\t\tarray_put img$i 1 $OPTARG;\n\t\t\t\tarray_put img$i 2 $k;\n\t\t\t\t;;\n\t\t\tK ) array_put img$i 9 $OPTARG;;\n\t\t\tn ) array_put img$i 11 $OPTARG;;\n\t\t\to ) OUTPUT=$OPTARG;;\n\t\t\tv ) VERSION=$OPTARG;;\n\t\t\tr ) i=$(($i + 1));\n\t\t\t\tr=$(($r + 1));\n\t\t\t\timg_array[$i]=img$i;\n\t\t\t\tarray_put img$i 0 \"ramdisk\";\n\t\t\t\tarray_put img$i 1 $OPTARG;\n\t\t\t\tarray_put img$i 2 $r;\n\t\t\t\t;;\n\t\t\ts ) value_sanity_chk signature $OPTARG;\n\t\t\t\tarray_put img$i 10 $OPTARG;\n\t\t\t\t;;\n\t\t\t* ) echo \"Invalid option passed to '$0' (options:$@)\"\n\t\t\tusage;;\n\t\tesac\n\tdone\n\tshift $(($OPTIND - 1))\n\t[ $# -gt 0 ] && {\n\t\techo \"Failed to parse all passed arguments (unrecognized: \\\"$@\\\")\"\n\t\texit 1\n\t}\n\t[ -n \"${OUTPUT}\" ] || OUTPUT=fitimage.its\n\t[ -n \"${VERSION}\" ] || VERSION=\"Unknown\"\n\t[ -n \"${ARCH}\" ] || ARCH=arm\n}\n\n#\n# sanity check for signature, compression and hash\n#\nvalue_sanity_chk()\n{\n\tlocal valid=\"\"\n\tcase $1 in\n\t\tsignature) valid=\"sha-1,rsa-2048 sha-256,rsa-2048 sha-256,rsa-4096\";;\n\t\tcompression) valid=\"gzip bzip2 none\";;\n\t\thash) valid=\"sha1 md5 crc32\";;\n\tesac\n\tif ! echo $valid | grep -q \"$2\"; then\n\t\techo \"Error: Invalid $1 provided '$2'\"\n\t\techo \"Valid options are: $valid\"\n\t\texit 255\n\tfi\n}\n\n#\n# Emit the fitImage section bits\n#\n# $1: Section bit type: fitstart   - its header\n#                       imagestart - image section start\n#                       confstart  - configuration section start\n#                       sectend    - section end\n#                       fitend     - fitimage end\n# $2: optional variable for confstart section\n#\nemit_its() {\n\tcase $1 in\n\tfitstart)\n\t\tcat << EOF > ${OUTPUT}\n/dts-v1/;\n\n/ {\n\tdescription = \"U-Boot fitImage for ${VERSION} kernel\";\n\t#address-cells = <1>;\nEOF\n\t;;\n\timagestart)\n\t\techo -e \"\\n\\timages {\" >> ${OUTPUT};;\n\tconfstart)\n#\t\techo -e \"\\tconfigurations {\\n\\t\\tdefault = \\\"conf@${2:-0}\\\";\" \\\n\techo -e \"\\tconfigurations {\\n\" \\\n\t\t\t>> ${OUTPUT};;\n\tsectend)\n\t\techo -e \"\\t};\" >> ${OUTPUT};;\n\tfitend)\n\t\techo -e \"};\" >> ${OUTPUT};;\n\tesac\n}\n\n#\n# Emit kernel image node\n#\nemit_kernel() {\n\tlocal image=${1}\n\tlocal count=${2:-${MAX_IMG}}\n\tlocal loaddaddr=${3:-0x8000}\n\tlocal entrypoint=${4:-0x8000}\n\tlocal compresson=${5:-none}\n\tlocal checksum=${6:-sha1}\n\tlocal name=${7}\n\n\t[ -z \"${name}\" ] || name=\" ${name}\"\n\tcat << EOF >> ${OUTPUT}\n\t\tkernel@${count} {\n\t\t\tdescription = \"Linux Kernel${name}\";\n\t\t\tdata = /incbin/(\"${image}\");\n\t\t\ttype = \"kernel\";\n\t\t\tarch = \"${ARCH}\";\n\t\t\tos = \"linux\";\n\t\t\tcompression = \"${compresson}\";\n\t\t\tload = <${loaddaddr}>;\n\t\t\tentry = <${entrypoint}>;\nEOF\n\temit_cksum ${checksum}\n\n\tif [ -z \"$SIGN_IN_CONF\" ] ; then\n\t\temit_signature \"$9\" \"\" \"\" \"$8\" \"\" \"\"\n\tfi\n\n\techo \"\t\t};\" >> ${OUTPUT}\n}\n\n#\n# Emit fdt node\n#\nemit_fdt() {\n\tlocal image=${1}\n\tlocal count=${2:-${MAX_IMG}}\n\tlocal compresson=${3:-none}\n\tlocal checksum=${4:-sha1}\n\tlocal name=${5}\n\tlocal loadaddr=${6}\n\n\t[ -z \"${name}\" ] || name=\" ${name}\"\n\tcat << EOF >> ${OUTPUT}\n\t\tfdt@${count} {\n\t\t\tdescription = \"Flattened Device Tree blob${name}\";\n\t\t\tdata = /incbin/(\"${image}\");\n\t\t\ttype = \"flat_dt\";\n\t\t\tarch = \"${ARCH}\";\n\t\t\tload = <${loadaddr}>;\n\t\t\tcompression = \"none\";\nEOF\n\temit_cksum ${checksum}\n\tif [ -z \"$SIGN_IN_CONF\" ] ; then\n\t\temit_signature \"\" \"$7\" \"\" \"\" \"$6\" \"\"\n\tfi\n\techo \"\t\t};\" >> ${OUTPUT}\n}\n\n#\n# Emit ramdisk node\n#\nemit_ramdisk() {\n\tlocal image=${1}\n\tlocal count=${2:-${MAX_IMG}}\n\tlocal compresson=${3:-none}\n\tlocal checksum=${4:-sha1}\n\tlocal name=${5}\n\n\t[ -z \"${name}\" ] || name=\" ${name}\"\n\tcat << EOF >> ${OUTPUT}\n\t\tramdisk@${count} {\n\t\t\tdescription = \"ramdisk${name}\";\n\t\t\tdata = /incbin/(\"${image}\");\n\t\t\ttype = \"ramdisk\";\n\t\t\tarch = \"${ARCH}\";\n\t\t\tos = \"linux\";\n\t\t\tcompression = \"${compresson}\";\nEOF\n\temit_cksum ${checksum}\n\tif [ -z \"$SIGN_IN_CONF\" ] ; then\n\t\temit_signature \"\" \"\" \"$7\" \"\" \"\" \"$6\"\n\tfi\n\techo \"\t\t};\" >> ${OUTPUT}\n}\n\n#\n# Emit check sum sub node\n#\nemit_cksum() {\n\tcsum_list=$@\n\tcount=1\n\tfor csum in ${csum_list}; do\n\t\tcat << EOF >> ${OUTPUT}\n\t\t\thash@${count} {\n\t\t\t\talgo = \"${csum}\";\n\t\t\t};\nEOF\n\t\tcount=`expr ${count} + 1`\n\tdone\n}\n\n#\n# Emit signature sub node\n#\nemit_signature() {\n\tlocal kernel=$1\n\tlocal fdt=$2\n\tlocal rootfs=$3\n\tlocal kernel_key=$4\n\tlocal fdt_key=$5\n\tlocal rootfs_key=$6\n\tlocal imgs=\"\"\n\tlocal count=0\n\tlocal chk_list=\"\" algo=\"\" algos=\"\" i=\"\"\n\n\tfor i in kernel fdt rootfs; do\n\t\teval algo=\\$$i\n\t\teval key=\\$${i}_key\n\t\t[ -n \"$algo\" ] || continue\n\t\tif ! echo \"$algos\" | grep -q $algo; then\n\t\t\tif [ -z \"$algos\" ]; then\n\t\t\t\talgos=$algo\n\t\t\telse\n\t\t\t\talgos=\"${algos} $algo\"\n\t\t\tfi\n\t\tfi\n\t\tif ! echo \"$keys\" | grep -q $key; then\n\t\t\tif [ -z \"$keys\" ]; then\n\t\t\t\tkeys=$key\n\t\t\telse\n\t\t\t\tkeys=\"${keys} $key\"\n\t\t\tfi\n\t\tfi\n\tdone\n\n\tfor algo in $algos; do\n\t\tfor key in $keys; do\n\t\t\timg=\"\"\n\t\t\tfor i in kernel fdt rootfs; do\n\t\t\t\teval tmp_algo=\\$$i\n\t\t\t\teval tmp_key=\\$${i}_key\n\t\t\t\t[ \"$tmp_algo\" == \"$algo\" ] || continue\n\t\t\t\t[ \"$tmp_key\" == \"$key\" ] || continue\n\t\t\t\tif [ -z \"$img\" ]; then\n\t\t\t\t\timg=$i\n\t\t\t\telse\n\t\t\t\t\timg=${img},$i\n\t\t\t\tfi\n\t\t\tdone\n\n\t\t\t[ -n \"$img\" ] || continue\n\t\t\tcat << EOF >> ${OUTPUT}\n\t\t\tsignature@${count} {\n\t\t\t\talgo = \"${algo}\";\n\t\t\t\tkey-name-hint = \"${key}\";\nEOF\n\t\t\tif [ -n \"$SIGN_IN_CONF\" ] ; then\n\t\t\t\techo \"\t\t\tsign-images = \\\"$img\\\";\" >> ${OUTPUT}\n\t\t\tfi\n\t\t\techo \"\t\t\t};\" >> ${OUTPUT}\n\n\t\t\tcount=`expr ${count} + 1`\n\t\tdone\n\tdone\n}\n\n#\n# Emit config sub nodes\n#\nemit_config() {\n\tlocal conf_csum=\"sha1\"\n\n\tconfig_name=\"conf@${1}\"\n\tif [ ! -z \"${11}\" ]; then\n\t\tconfig_name=\"${11}\"\n\tfi \n\tif [ -z \"${2}\" ]; then\n\t\techo \"Error: config has no kernel img, skipping conf node!\"\n\t\treturn 0\n\tfi\n\n\t# Test if we have any DTBs at all\n\tif [ -z \"${3}\" ] ; then\n\t\tconf_desc=\"Boot Linux kernel\"\n\t\tfdt_line=\"\"\n\telse\n\t\tconf_desc=\"Boot Linux kernel with FDT blob\"\n\t\tfdt_line=\"\n\t\t\tfdt = \\\"fdt@${3}\\\";\"\n\tfi\n\n\t# Test if we have any ROOTFS at all\n\tif [ -n \"${4}\" ] ; then\n\t\tconf_desc=\"$conf_desc + ramdisk\"\n\t\tfdt_line=\"${fdt_line}\n\t\t\tramdisk = \\\"ramdisk@${4}\\\";\"\n\tfi\n\n\tkernel_line=\"kernel = \\\"kernel@${2}\\\";\"\n\n\tcat << EOF >> ${OUTPUT}\n\t\t${config_name} {\n\t\t\tdescription = \"${conf_desc}\";\n\t\t\t${kernel_line}${fdt_line}\n\t\t\thash@1 {\n\t\t\t\talgo = \"${conf_csum}\";\n\t\t\t};\nEOF\n\tif [ -n \"$SIGN_IN_CONF\" ] ; then\n\t\temit_signature \"$5\" \"$6\" \"$7\" \"$8\" \"$9\" \"${10}\"\n\tfi\n\n\techo \"\t\t};\" >> ${OUTPUT}\n}\n\n#\n# remove prefix space\n#\nremove_prefix_space()\n{\n\techo \"$@\" | sed \"s:^ ::g\"\n}\n\n#\n# generate image nodes and its subnodes\n#\nemit_image_nodes()\n{\n\tlocal t img_c img_i img_index chk\n\tlocal img_type img_path img_count img_loadadr img_entrypoint \\\n\t\timg_compression img_hash img_conf img_name img_key img_sign \\\n\t\timg_index\n\n\temit_its imagestart\n\tfor t in \"kernel\" \"fdt\" \"ramdisk\"; do\n\t\timg_index=0\n\t\tfor a in ${img_array[@]}; do\n\t\t\timg_type=$(array_get $a 0)\n\t\t\timg_path=$(array_get $a 1)\n\t\t\timg_count=$(array_get $a 2)\n\t\t\timg_loadadr=$(array_get $a 3)\n\t\t\timg_entrypoint=$(array_get $a 4)\n\t\t\timg_compression=$(array_get $a 5)\n\t\t\timg_hash=$(array_get $a 6)\n\t\t\timg_conf=$(array_get $a 7)\n\t\t\timg_name=$(array_get $a 8)\n\t\t\timg_key=$(array_get $a 9)\n\t\t\timg_sign=$(array_get $a 10)\n\t\t\timg_cname=$(array_get $a 11)\n\t\t\t\n\t\t\timg_conf=$(remove_prefix_space $img_conf)\n\t\t\timg_hash=$(remove_prefix_space $img_hash)\n\n\t\t\t[ \"${img_type}\" == $t ] || continue\n\t\t\t# generate sub nodes\n\t\t\teval chk=\\$DEF_$t\n\t\t\t[ -n \"${chk}\" ] || eval DEF_$t=$img_count\n\t\t\tcase $t in\n\t\t\t\tkernel) emit_kernel \"$img_path\" \"$img_count\" \\\n\t\t\t\t\t\"$img_loadadr\" \"$img_entrypoint\" \\\n\t\t\t\t\t\"$img_compression\" \"$img_hash\" \\\n\t\t\t\t\t\"$img_name\" \"$img_key\" \"$img_sign\";;\n\t\t\t\tfdt) emit_fdt \"$img_path\" \"$img_count\" \\\n\t\t\t\t\t\"$img_compression\" \"$img_hash\" \\\n\t\t\t\t\t\"$img_name\" \"$img_loadadr\" \"$img_key\" \"$img_sign\"  ;;\n\n\t\t\t\tramdisk) emit_ramdisk \"$img_path\" \"$img_count\" \\\n\t\t\t\t\t\"$img_compression\" \"$img_hash\" \\\n\t\t\t\t\t\"$img_name\" \"$img_key\" \"$img_sign\";;\n\t\t\tesac\n\n\t\t\t# set up configuration data\n\t\t\tfor img_c in $img_conf; do\n\t\t\t\timg_i=\"\"\n\t\t\t\t#set up default configuration if its not set\n\t\t\t\t[ -n \"$DEF_CONFIG\" ] || DEF_CONFIG=$img_c\n\t\t\t\t[ -z \"${img_c}\" ] || conf_array[$img_c]=conf$img_c\n\t\t\t\tarray_put conf$img_c 0 ${img_c}\n\t\t\t\tcase $t in\n\t\t\t\t\tkernel) img_i=1;;\n\t\t\t\t\tfdt) img_i=2;;\n\t\t\t\t\tramdisk) img_i=3;;\n\t\t\t\tesac\n\t\t\t\tarray_put conf$img_c $img_i $img_index\n\t\t\t\tarray_put conf$img_c $(($img_i + 3)) ${img_sign}\n\t\t\t\tarray_put conf$img_c $(($img_i + 6)) ${img_key}\n\t\t\t\tarray_put conf$img_c 10 $img_cname\n\t\t\tdone\n\t\t\timg_index=$((img_index + 1))\n\t\tdone\n\tdone\n\temit_its sectend\n}\n\n#\n# generate configuration node and its subnodes\n#\nemit_configuration_nodes ()\n{\n\tlocal count kernel fdt ramdisk ker_file fdt_file rfs_file ker_sign \\\n\t\tfdt_sign rfs_sign\n\temit_its confstart $DEF_CONFIG\n\tfor a in ${conf_array[@]}; do\n\t\tcount=$(array_get $a 0)\n\t\tkernel=$(array_get $a 1)\n\t\tfdt=$(array_get $a 2)\n\t\tramdisk=$(array_get $a 3)\n\t\ter_file=$(array_get $a 4)\n\t\tfdt_file=$(array_get $a 5)\n\t\trfs_file=$(array_get $a 6)\n\t\tker_sign=$(array_get $a 7)\n\t\tfdt_sign=$(array_get $a 8)\n\t\trfs_sign=$(array_get $a 9)\n\t\tcname=$(array_get $a 10)\n\t\temit_config \"$count\" \"$kernel\" \"$fdt\" \"$ramdisk\" \"$ker_file\" \\\n\t\t\t\"$fdt_file\" \"$rfs_file\" \"$ker_sign\" \"$fdt_sign\" \\\n\t\t\t\"$rfs_sign\" \"${cname}\"\n\tdone\n\tif [ -z \"${DEF_CONFIG}\" ]; then\n\t\temit_config \"0\" \"$DEF_kernel\" \"$DEF_fdt\" \"$DEF_ramdisk\"\n\tfi\n\temit_its sectend\n}\n\n# Set to none empty to create signature sub node under images node\nSIGN_IN_CONF=${SIGN_IN_CONF:-\"\"}\n# Set to default config used\nDEF_CONFIG=${DEF_CONFIG:-\"\"}\n\nparse_args $@\n\nemit_its fitstart\nemit_image_nodes\nemit_configuration_nodes\nemit_its fitend\n"
  },
  {
    "path": "target/linux/layerscape/modules.mk",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) Jiang Yutang <jiangyutang1978@gmail.com>\n\ndefine KernelPackage/ahci-qoriq\n  SUBMENU:=$(BLOCK_MENU)\n  TITLE:=Freescale QorIQ AHCI SATA support\n  KCONFIG:=CONFIG_AHCI_QORIQ\n  FILES:=$(LINUX_DIR)/drivers/ata/ahci_qoriq.ko\n  AUTOLOAD:=$(call AutoLoad,40,ahci-qoriq,1)\n  $(call AddDepends/ata,+kmod-ata-ahci-platform @TARGET_layerscape)\nendef\n\ndefine KernelPackage/ahci-qoriq/description\n This option enables support for the Freescale QorIQ AHCI SoC's\n onboard AHCI SATA.\nendef\n\n$(eval $(call KernelPackage,ahci-qoriq))\n\ndefine KernelPackage/ppfe\n  SUBMENU:=$(NETWORK_DEVICES_MENU)\n  TITLE:=Freescale PPFE Driver support\n  DEPENDS:=@TARGET_layerscape\n  KCONFIG:=CONFIG_FSL_PPFE=y \\\n  \tCONFIG_FSL_PPFE_UTIL_DISABLED=y\n  FILES:=$(LINUX_DIR)/drivers/staging/fsl_ppfe/pfe.ko\n  AUTOLOAD:=$(call AutoLoad,35,pfe)\nendef\n\ndefine KernelPackage/ppfe/description\n Kernel modules for Freescale PPFE Driver support.\nendef\n\n$(eval $(call KernelPackage,ppfe))\n"
  },
  {
    "path": "target/linux/layerscape/patches-5.10/300-add-DTS-for-Traverse-LS1043-Boards.patch",
    "content": "From 5b35aae22b4ca2400e49561c9267aa01346f91d4 Mon Sep 17 00:00:00 2001\nFrom: Mathew McBride <matt@traverse.com.au>\nDate: Tue, 17 Apr 2018 10:01:03 +1000\nSubject: [PATCH] add DTS for Traverse LS1043 Boards\n\nSigned-off-by: Mathew McBride <matt@traverse.com.au>\n[rebase]\nSigned-off-by: Yangbo Lu <yangbo.lu@nxp.com>\n---\n arch/arm64/boot/dts/freescale/Makefile             |  3 +++\n arch/arm64/boot/dts/freescale/traverse-ls1043s.dts | 29 ++++++++++++++++++++++\n arch/arm64/boot/dts/freescale/traverse-ls1043v.dts | 29 ++++++++++++++++++++++\n 3 files changed, 61 insertions(+)\n\n--- a/arch/arm64/boot/dts/freescale/Makefile\n+++ b/arch/arm64/boot/dts/freescale/Makefile\n@@ -28,6 +28,9 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2\n dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-qds.dtb\n dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-rdb.dtb\n \n+dtb-$(CONFIG_ARCH_LAYERSCAPE) += traverse-ls1043v.dtb\n+dtb-$(CONFIG_ARCH_LAYERSCAPE) += traverse-ls1043s.dtb\n+\n dtb-$(CONFIG_ARCH_MXC) += imx8mm-beacon-kit.dtb\n dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb\n dtb-$(CONFIG_ARCH_MXC) += imx8mm-ddr4-evk.dtb\n"
  },
  {
    "path": "target/linux/layerscape/patches-5.10/301-arm-dts-ls1021a-Add-LS1021A-IOT-board-support.patch",
    "content": "From 55e00e402d6143aeb153761f8144d9fee5f1f009 Mon Sep 17 00:00:00 2001\nFrom: Biwen Li <biwen.li@nxp.com>\nDate: Fri, 26 Oct 2018 16:00:37 +0800\nSubject: [PATCH] arm: dts: ls1021a: Add LS1021A-IOT board support\n\nSigned-off-by: Biwen Li <biwen.li@nxp.com>\n[rebase]\nSigned-off-by: Yangbo Lu <yangbo.lu@nxp.com>\n---\n arch/arm/boot/dts/Makefile        |   3 +-\n arch/arm/boot/dts/ls1021a-iot.dts | 262 ++++++++++++++++++++++++++++++++++++++\n 2 files changed, 264 insertions(+), 1 deletion(-)\n create mode 100644 arch/arm/boot/dts/ls1021a-iot.dts\n\n--- a/arch/arm/boot/dts/Makefile\n+++ b/arch/arm/boot/dts/Makefile\n@@ -665,7 +665,8 @@ dtb-$(CONFIG_SOC_LS1021A) += \\\n \tls1021a-moxa-uc-8410a.dtb \\\n \tls1021a-qds.dtb \\\n \tls1021a-tsn.dtb \\\n-\tls1021a-twr.dtb\n+\tls1021a-twr.dtb \\\n+\tls1021a-iot.dtb\n dtb-$(CONFIG_SOC_VF610) += \\\n \tvf500-colibri-eval-v3.dtb \\\n \tvf610-bk4.dtb \\\n--- /dev/null\n+++ b/arch/arm/boot/dts/ls1021a-iot.dts\n@@ -0,0 +1,262 @@\n+/*\n+ * Copyright 2013-2016 Freescale Semiconductor, Inc.\n+ *\n+ * This program is free software; you can redistribute it and/or modify\n+ * it under the terms of the GNU General Public License as published by\n+ * the Free Software Foundation; either version 2 of the License, or\n+ * (at your option) any later version.\n+ */\n+\n+/dts-v1/;\n+#include \"ls1021a.dtsi\"\n+\n+/ {\n+\tmodel = \"LS1021A IOT Board\";\n+\n+\tsys_mclk: clock-mclk {\n+\t\tcompatible = \"fixed-clock\";\n+\t\t#clock-cells = <0>;\n+\t\tclock-frequency = <24576000>;\n+\t};\n+\n+\tregulators {\n+\t\tcompatible = \"simple-bus\";\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\n+\t\treg_3p3v: regulator@0 {\n+\t\t\tcompatible = \"regulator-fixed\";\n+\t\t\treg = <0>;\n+\t\t\tregulator-name = \"3P3V\";\n+\t\t\tregulator-min-microvolt = <3300000>;\n+\t\t\tregulator-max-microvolt = <3300000>;\n+\t\t\tregulator-always-on;\n+\t\t};\n+\n+\t\treg_2p5v: regulator@1 {\n+\t\t\tcompatible = \"regulator-fixed\";\n+\t\t\treg = <1>;\n+\t\t\tregulator-name = \"2P5V\";\n+\t\t\tregulator-min-microvolt = <2500000>;\n+\t\t\tregulator-max-microvolt = <2500000>;\n+\t\t\tregulator-always-on;\n+\t\t};\n+\t};\n+\n+\tsound {\n+\t\tcompatible = \"simple-audio-card\";\n+\t\tsimple-audio-card,format = \"i2s\";\n+\t\tsimple-audio-card,widgets =\n+\t\t\t\"Microphone\", \"Microphone Jack\",\n+\t\t\t\"Headphone\", \"Headphone Jack\",\n+\t\t\t\"Speaker\", \"Speaker Ext\",\n+\t\t\t\"Line\", \"Line In Jack\";\n+\t\tsimple-audio-card,routing =\n+\t\t\t\"MIC_IN\", \"Microphone Jack\",\n+\t\t\t\"Microphone Jack\", \"Mic Bias\",\n+\t\t\t\"LINE_IN\", \"Line In Jack\",\n+\t\t\t\"Headphone Jack\", \"HP_OUT\",\n+\t\t\t\"Speaker Ext\", \"LINE_OUT\";\n+\n+\t\tsimple-audio-card,cpu {\n+\t\t\tsound-dai = <&sai2>;\n+\t\t\tframe-master;\n+\t\t\tbitclock-master;\n+\t\t};\n+\n+\t\tsimple-audio-card,codec {\n+\t\t\tsound-dai = <&codec>;\n+\t\t\tframe-master;\n+\t\t\tbitclock-master;\n+\t\t};\n+\t};\n+\n+\tfirmware {\n+\t\toptee {\n+\t\t\tcompatible = \"linaro,optee-tz\";\n+\t\t\tmethod = \"smc\";\n+\t\t\t};\n+\t\t};\n+};\n+\n+&enet0 {\n+\ttbi-handle = <&tbi1>;\n+\tphy-handle = <&phy1>;\n+\tphy-connection-type = \"sgmii\";\n+\tstatus = \"okay\";\n+};\n+\n+&enet1 {\n+\ttbi-handle = <&tbi1>;\n+\tphy-handle = <&phy3>;\n+\tphy-connection-type = \"sgmii\";\n+\tstatus = \"okay\";\n+};\n+\n+&enet2 {\n+\tfixed-link = <0 1 1000 0 0>;\n+\tphy-connection-type = \"rgmii-id\";\n+\tstatus = \"okay\";\n+};\n+\n+&can0{\n+\tstatus = \"disabled\";\n+};\n+\n+&can1{\n+\tstatus = \"disabled\";\n+};\n+\n+&can2{\n+\tstatus = \"disabled\";\n+};\n+\n+&can3{\n+\tstatus = \"okay\";\n+};\n+\n+&esdhc{\n+\tstatus = \"okay\";\n+};\n+\n+&i2c0 {\n+\tstatus = \"okay\";\n+\n+\tmax1239@35 {\n+\t\tcompatible = \"maxim,max1239\";\n+\t\treg = <0x35>;\n+\t\t#io-channel-cells = <1>;\n+\t};\n+\n+\tcodec: sgtl5000@2a {\n+               #sound-dai-cells=<0x0>;\n+\t\tcompatible = \"fsl,sgtl5000\";\n+\t\treg = <0x2a>;\n+\t\tVDDA-supply = <&reg_3p3v>;\n+\t\tVDDIO-supply = <&reg_2p5v>;\n+\t\tclocks = <&sys_mclk 1>;\n+\t};\n+\n+\tpca9555: pca9555@23 {\n+\t\tcompatible = \"nxp,pca9555\";\n+\t\t/*pinctrl-names = \"default\";*/\n+\t\t/*interrupt-parent = <&gpio2>;\n+\t\tinterrupts = <19 0x2>;*/\n+\t\tgpio-controller;\n+\t\t#gpio-cells = <2>;\n+\t\tinterrupt-controller;\n+\t\t#interrupt-cells = <2>;\n+\t\treg = <0x23>;\n+\t};\n+\n+\tina220@44 {\n+\t\tcompatible = \"ti,ina220\";\n+\t\treg = <0x44>;\n+\t\tshunt-resistor = <1000>;\n+\t};\n+\n+\tina220@45 {\n+\t\tcompatible = \"ti,ina220\";\n+\t\treg = <0x45>;\n+\t\tshunt-resistor = <1000>;\n+\t};\n+\n+\tlm75b@48 {\n+                compatible = \"nxp,lm75a\";\n+                reg = <0x48>;\n+        };\n+\n+\tadt7461a@4c {\n+\t\tcompatible = \"adt7461a\";\n+\t\treg = <0x4c>;\n+\t};\n+\n+\thdmi: sii9022a@39 {\n+\t\tcompatible = \"fsl,sii902x\";\n+\t\treg = <0x39>;\n+\t\tinterrupts = <GIC_SPI 163 IRQ_TYPE_EDGE_RISING>;\n+\t};\n+};\n+\n+&i2c1 {\n+\tstatus = \"disabled\";\n+};\n+\n+&ifc {\n+\tstatus = \"disabled\";\n+};\n+\n+&lpuart0 {\n+\tstatus = \"okay\";\n+};\n+\n+&mdio0 {\n+\tphy0: ethernet-phy@0 {\n+\t\treg = <0x0>;\n+\t};\n+\tphy1: ethernet-phy@1 {\n+\t\treg = <0x1>;\n+\t};\n+\tphy2: ethernet-phy@2 {\n+\t\treg = <0x2>;\n+\t};\n+\tphy3: ethernet-phy@3 {\n+\t\treg = <0x3>;\n+\t};\n+\ttbi1: tbi-phy@1f {\n+\t\treg = <0x1f>;\n+\t\tdevice_type = \"tbi-phy\";\n+\t};\n+};\n+\n+&qspi {\n+\tnum-cs = <2>;\n+\tstatus = \"okay\";\n+\n+\tqflash0: s25fl128s@0 {\n+\t\tcompatible = \"spansion,s25fl129p1\";\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <1>;\n+\t\tspi-max-frequency = <20000000>;\n+\t\treg = <0>;\n+\t};\n+};\n+\n+&sai2 {\n+\tstatus = \"okay\";\n+};\n+\n+&uart0 {\n+\tstatus = \"okay\";\n+};\n+\n+&uart1 {\n+\tstatus = \"okay\";\n+};\n+\n+&dcu {\n+\tdisplay = <&display>;\n+\tstatus = \"okay\";\n+\n+\tdisplay: display@0 {\n+\t\tbits-per-pixel = <24>;\n+\n+\t\tdisplay-timings {\n+\t\t\tnative-mode = <&timing0>;\n+\n+\t\t\ttiming0: mode0 {\n+\t\t\t\tclock-frequency = <25000000>;\n+\t\t\t\thactive = <640>;\n+\t\t\t\tvactive = <480>;\n+\t\t\t\thback-porch = <80>;\n+\t\t\t\thfront-porch = <80>;\n+\t\t\t\tvback-porch = <16>;\n+\t\t\t\tvfront-porch = <16>;\n+\t\t\t\thsync-len = <12>;\n+\t\t\t\tvsync-len = <2>;\n+\t\t\t\thsync-active = <1>;\n+\t\t\t\tvsync-active = <1>;\n+\t\t\t};\n+\t\t};\n+\t};\n+};\n"
  },
  {
    "path": "target/linux/layerscape/patches-5.10/302-arm64-dts-ls1012a-update-with-ppfe-support.patch",
    "content": "From 1bb35ff4ce33e65601c8d9c736be52e4aabd6252 Mon Sep 17 00:00:00 2001\nFrom: Calvin Johnson <calvin.johnson@nxp.com>\nDate: Sat, 16 Sep 2017 14:20:23 +0530\nSubject: [PATCH] arm64: dts: freescale: ls1012a: update with ppfe support\n\nUpdate ls1012a dtsi and platform dts files with support for ppfe.\n\nSigned-off-by: Calvin Johnson <calvin.johnson@nxp.com>\nSigned-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>\n---\n .../boot/dts/freescale/fsl-ls1012a-frdm.dts   | 43 +++++++++++++++++\n .../boot/dts/freescale/fsl-ls1012a-frwy.dts   | 43 +++++++++++++++++\n .../boot/dts/freescale/fsl-ls1012a-qds.dts    | 43 +++++++++++++++++\n .../boot/dts/freescale/fsl-ls1012a-rdb.dts    | 47 +++++++++++++++++++\n .../arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 29 ++++++++++++\n 5 files changed, 205 insertions(+)\n\n--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts\n+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts\n@@ -13,6 +13,11 @@\n \tmodel = \"LS1012A Freedom Board\";\n \tcompatible = \"fsl,ls1012a-frdm\", \"fsl,ls1012a\";\n \n+\taliases {\n+\t\tethernet0 = &pfe_mac0;\n+\t\tethernet1 = &pfe_mac1;\n+\t};\n+\n \tsys_mclk: clock-mclk {\n \t\tcompatible = \"fixed-clock\";\n \t\t#clock-cells = <0>;\n@@ -74,6 +79,44 @@\n \t};\n };\n \n+&pfe {\n+\tstatus = \"okay\";\n+\t#address-cells = <1>;\n+\t#size-cells = <0>;\n+\n+\tpfe_mac0: ethernet@0 {\n+\t\tcompatible = \"fsl,pfe-gemac-port\";\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\treg = <0x0>;\t/* GEM_ID */\n+\t\tfsl,gemac-bus-id = <0x0>;\t/* BUS_ID */\n+\t\tfsl,gemac-phy-id = <0x2>;\t/* PHY_ID */\n+\t\tfsl,mdio-mux-val = <0x0>;\n+\t\tphy-mode = \"sgmii\";\n+\t\tfsl,pfe-phy-if-flags = <0x0>;\n+\n+\t\tmdio@0 {\n+\t\t\treg = <0x1>; /* enabled/disabled */\n+\t\t};\n+\t};\n+\n+\tpfe_mac1: ethernet@1 {\n+\t\tcompatible = \"fsl,pfe-gemac-port\";\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\treg = <0x1>;\t/* GEM_ID */\n+\t\tfsl,gemac-bus-id = <0x1>;\t/* BUS_ID */\n+\t\tfsl,gemac-phy-id = <0x1>;\t/* PHY_ID */\n+\t\tfsl,mdio-mux-val = <0x0>;\n+\t\tphy-mode = \"sgmii\";\n+\t\tfsl,pfe-phy-if-flags = <0x0>;\n+\n+\t\tmdio@0 {\n+\t\t\treg = <0x0>; /* enabled/disabled */\n+\t\t};\n+\t};\n+};\n+\n &qspi {\n \tstatus = \"okay\";\n \n--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-frwy.dts\n+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frwy.dts\n@@ -14,6 +14,11 @@\n / {\n \tmodel = \"LS1012A FRWY Board\";\n \tcompatible = \"fsl,ls1012a-frwy\", \"fsl,ls1012a\";\n+\n+\taliases {\n+\t\tethernet0 = &pfe_mac0;\n+\t\tethernet1 = &pfe_mac1;\n+\t};\n };\n \n &duart0 {\n@@ -24,6 +29,44 @@\n \tstatus = \"okay\";\n };\n \n+&pfe {\n+\tstatus = \"okay\";\n+\t#address-cells = <1>;\n+\t#size-cells = <0>;\n+\n+\tpfe_mac0: ethernet@0 {\n+\t\tcompatible = \"fsl,pfe-gemac-port\";\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\treg = <0x0>;\t/* GEM_ID */\n+\t\tfsl,gemac-bus-id = <0x0>;\t/* BUS_ID */\n+\t\tfsl,gemac-phy-id = <0x2>;\t/* PHY_ID */\n+\t\tfsl,mdio-mux-val = <0x0>;\n+\t\tphy-mode = \"sgmii\";\n+\t\tfsl,pfe-phy-if-flags = <0x0>;\n+\n+\t\tmdio@0 {\n+\t\t\treg = <0x1>; /* enabled/disabled */\n+\t\t};\n+\t};\n+\n+\tpfe_mac1: ethernet@1 {\n+\t\tcompatible = \"fsl,pfe-gemac-port\";\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\treg = <0x1>;\t/* GEM_ID */\n+\t\tfsl,gemac-bus-id = <0x1>;\t/* BUS_ID */\n+\t\tfsl,gemac-phy-id = <0x1>;\t/* PHY_ID */\n+\t\tfsl,mdio-mux-val = <0x0>;\n+\t\tphy-mode = \"sgmii\";\n+\t\tfsl,pfe-phy-if-flags = <0x0>;\n+\n+\t\tmdio@0 {\n+\t\t\treg = <0x0>; /* enabled/disabled */\n+\t\t};\n+\t};\n+};\n+\n &qspi {\n \tstatus = \"okay\";\n \n--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts\n+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts\n@@ -13,6 +13,11 @@\n \tmodel = \"LS1012A QDS Board\";\n \tcompatible = \"fsl,ls1012a-qds\", \"fsl,ls1012a\";\n \n+\taliases {\n+\t\tethernet0 = &pfe_mac0;\n+\t\tethernet1 = &pfe_mac1;\n+\t};\n+\n \tsys_mclk: clock-mclk {\n \t\tcompatible = \"fixed-clock\";\n \t\t#clock-cells = <0>;\n@@ -127,6 +132,44 @@\n \t\t};\n \t};\n };\n+\n+&pfe {\n+\tstatus = \"okay\";\n+\t#address-cells = <1>;\n+\t#size-cells = <0>;\n+\n+\tpfe_mac0: ethernet@0 {\n+\t\tcompatible = \"fsl,pfe-gemac-port\";\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\treg = <0x0>;\t/* GEM_ID */\n+\t\tfsl,gemac-bus-id = <0x0>;\t/* BUS_ID */\n+\t\tfsl,gemac-phy-id = <0x1>;\t/* PHY_ID */\n+\t\tfsl,mdio-mux-val = <0x2>;\n+\t\tphy-mode = \"sgmii-2500\";\n+\t\tfsl,pfe-phy-if-flags = <0x0>;\n+\n+\t\tmdio@0 {\n+\t\t\treg = <0x1>; /* enabled/disabled */\n+\t\t};\n+\t};\n+\n+\tpfe_mac1: ethernet@1 {\n+\t\tcompatible = \"fsl,pfe-gemac-port\";\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\treg = <0x1>;\t/* GEM_ID */\n+\t\tfsl,gemac-bus-id = <0x1>;\t/* BUS_ID */\n+\t\tfsl,gemac-phy-id = <0x2>;\t/* PHY_ID */\n+\t\tfsl,mdio-mux-val = <0x3>;\n+\t\tphy-mode = \"sgmii-2500\";\n+\t\tfsl,pfe-phy-if-flags = <0x0>;\n+\n+\t\tmdio@0 {\n+\t\t\treg = <0x0>; /* enabled/disabled */\n+\t\t};\n+\t};\n+};\n \n &qspi {\n \tstatus = \"okay\";\n--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts\n+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts\n@@ -12,6 +12,15 @@\n / {\n \tmodel = \"LS1012A RDB Board\";\n \tcompatible = \"fsl,ls1012a-rdb\", \"fsl,ls1012a\";\n+\n+\taliases {\n+\t\tethernet0 = &pfe_mac0;\n+\t\tethernet1 = &pfe_mac1;\n+\t};\n+};\n+\n+&pcie1 {\n+\tstatus = \"okay\";\n };\n \n &duart0 {\n@@ -35,6 +44,44 @@\n \tstatus = \"okay\";\n };\n \n+&pfe {\n+\tstatus = \"okay\";\n+\t#address-cells = <1>;\n+\t#size-cells = <0>;\n+\n+\tpfe_mac0: ethernet@0 {\n+\t\tcompatible = \"fsl,pfe-gemac-port\";\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\treg = <0x0>;\t/* GEM_ID */\n+\t\tfsl,gemac-bus-id = <0x0>;\t/* BUS_ID */\n+\t\tfsl,gemac-phy-id = <0x2>;\t/* PHY_ID */\n+\t\tfsl,mdio-mux-val = <0x0>;\n+\t\tphy-mode = \"sgmii\";\n+\t\tfsl,pfe-phy-if-flags = <0x0>;\n+\n+\t\tmdio@0 {\n+\t\t\treg = <0x1>; /* enabled/disabled */\n+\t\t};\n+\t};\n+\n+\tpfe_mac1: ethernet@1 {\n+\t\tcompatible = \"fsl,pfe-gemac-port\";\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\treg = <0x1>;\t/* GEM_ID */\n+\t\tfsl,gemac-bus-id = < 0x1 >;\t/* BUS_ID */\n+\t\tfsl,gemac-phy-id = < 0x1 >;\t/* PHY_ID */\n+\t\tfsl,mdio-mux-val = <0x0>;\n+\t\tphy-mode = \"rgmii-txid\";\n+\t\tfsl,pfe-phy-if-flags = <0x0>;\n+\n+\t\tmdio@0 {\n+\t\t\treg = <0x0>; /* enabled/disabled */\n+\t\t};\n+\t};\n+};\n+\n &qspi {\n \tstatus = \"okay\";\n \n--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi\n+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi\n@@ -531,6 +531,35 @@\n \t\t};\n \t};\n \n+\treserved-memory {\n+\t\t#address-cells = <2>;\n+\t\t#size-cells = <2>;\n+\t\tranges;\n+\n+\t\tpfe_reserved: packetbuffer@83400000 {\n+\t\t\treg = <0 0x83400000 0 0xc00000>;\n+\t\t};\n+\t};\n+\n+\tpfe: pfe@04000000 {\n+\t\tcompatible = \"fsl,pfe\";\n+\t\treg =   <0x0 0x04000000 0x0 0xc00000>,\t/* AXI 16M */\n+\t\t\t<0x0 0x83400000 0x0 0xc00000>;  /* PFE DDR 12M */\n+\t\treg-names = \"pfe\", \"pfe-ddr\";\n+\t\tfsl,pfe-num-interfaces = <0x2>;\n+\t\tinterrupts = <0 172 0x4>,    /* HIF interrupt */\n+\t\t\t     <0 173 0x4>,    /*HIF_NOCPY interrupt */\n+\t\t\t     <0 174 0x4>;    /* WoL interrupt */\n+\t\tinterrupt-names = \"pfe_hif\", \"pfe_hif_nocpy\", \"pfe_wol\";\n+\t\tmemory-region = <&pfe_reserved>;\n+\t\tfsl,pfe-scfg = <&scfg 0>;\n+\t\tfsl,rcpm-wakeup = <&rcpm 0xf0000020>;\n+\t\tclocks = <&clockgen 4 0>;\n+\t\tclock-names = \"pfe\";\n+\n+\t\tstatus = \"okay\";\n+\t};\n+\n \tfirmware {\n \t\toptee {\n \t\t\tcompatible = \"linaro,optee-tz\";\n"
  },
  {
    "path": "target/linux/layerscape/patches-5.10/701-staging-add-fsl_ppfe-driver.patch",
    "content": "From ab06204b9ae48324ed5b7e7026cce47ecd0a376d Mon Sep 17 00:00:00 2001\nFrom: Martin Schiller <ms@dev.tdt.de>\nDate: Mon, 8 Nov 2021 14:56:10 +0100\nSubject: [PATCH] staging: add fsl_ppfe driver\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nThis patch is the squashed version of all ppfe related commits from\nLSDK-21.08.\n\nSee the following git log for further details:\n\ncommit bc389fa57819620b61f86a39444cf22c70e291ad\nAuthor: Calvin Johnson <calvin.johnson@nxp.com>\nDate:   Sat Sep 16 07:05:49 2017 +0530\n\n    net: fsl_ppfe: dts binding for ppfe\n\n    Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>\n    Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>\n\ncommit d3822b65f897e4c421c72bd215f34e41d8c4a40e\nAuthor: Calvin Johnson <calvin.johnson@nxp.com>\nDate:   Sat Sep 16 14:21:37 2017 +0530\n\n    staging: fsl_ppfe/eth: header files for pfe driver\n\n    This patch has all pfe header files.\n\n    Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>\n    Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>\n\ncommit 9184a85f93816a8b81cb363464925757185b7138\nAuthor: Calvin Johnson <calvin.johnson@nxp.com>\nDate:   Sat Sep 16 14:22:17 2017 +0530\n\n    staging: fsl_ppfe/eth: introduce pfe driver\n\n            This patch introduces Linux support for NXP's LS1012A Packet\n    Forwarding Engine (pfe_eth). LS1012A uses hardware packet forwarding\n    engine to provide high performance Ethernet interfaces. The device\n    includes two Ethernet ports.\n\n    Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>\n    Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>\n\ncommit 63f6117f1c9af34bc333425507a8b858fcd61951\nAuthor: Calvin Johnson <calvin.johnson@nxp.com>\nDate:   Wed Oct 11 19:23:38 2017 +0530\n\n    staging: fsl_ppfe/eth: fix RGMII tx delay issue\n\n    Recently logic to enable RGMII tx delay was changed by\n    below patch.\n\n    https://patchwork.kernel.org/patch/9447581/\n\n    Based on the patch, appropriate change is made in PFE driver.\n\n    Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>\n    Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>\n\ncommit adf71df9d53026513da71892a27c455ae23a6d06\nAuthor: Calvin Johnson <calvin.johnson@nxp.com>\nDate:   Wed Oct 18 14:29:30 2017 +0530\n\n    staging: fsl_ppfe/eth: remove unused functions\n\n    Remove unused functions hif_xmit_pkt & hif_lib_xmit_pkt.\n\n    Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>\n\ncommit ea632882dacf4ec21f84fa73ebff7d89d46fbeb3\nAuthor: Calvin Johnson <calvin.johnson@nxp.com>\nDate:   Wed Oct 18 18:34:41 2017 +0530\n\n    staging: fsl_ppfe/eth: fix read/write/ack idx issue\n\n    While fixing checkpatch errors some of the index increments\n    were commented out. They are enabled.\n\n    Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>\n\ncommit 75dc5856eafe3ec988aa52f498ad683332e5a528\nAuthor: Calvin Johnson <calvin.johnson@nxp.com>\nDate:   Fri Oct 27 11:20:47 2017 +0530\n\n    staging: fsl_ppfe/eth: Make phy_ethtool_ksettings_get return void\n\n    Make return value void since function never return meaningful value\n\n    Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>\n\ncommit fd60dff2329a4c20f5638147db315879d4b92097\nAuthor: Calvin Johnson <calvin.johnson@nxp.com>\nDate:   Wed Nov 15 13:45:27 2017 +0530\n\n    staging: fsl_ppfe/eth: add function to update tmu credits\n\n    __hif_lib_update_credit function is used to update the tmu credits.\n    If tx_qos is set, tmu credit is updated based on the number of packets\n    transmitted by tmu.\n\n    Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>\n    Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>\n\ncommit 259418d3755afeabca062df4c177cb6617be7e2b\nAuthor: Kavi Akhila-B46177 <akhila.kavi@nxp.com>\nDate:   Thu Nov 2 12:05:35 2017 +0530\n\n    staging: fsl_ppfe/eth: Avoid packet drop at TMU queues\n\n    Added flow control between TMU queues and PFE Linux driver,\n    based on TMU credits availability.\n    Added tx_qos module parameter to control this behavior.\n    Use queue-0 as default queue to transmit packets.\n\n    Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>\n    Signed-off-by: Akhila Kavi <akhila.kavi@nxp.com>\n    Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>\n\ncommit 48f8aa50bdcccdec699550d10e274711f9f8cb4d\nAuthor: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>\nDate:   Wed Nov 29 12:08:00 2017 +0530\n\n    staging: fsl_ppfe/eth: Enable PFE in clause 45 mode\n\n    when we opearate in clause 45 mode, we need to call\n    the function get_phy_device() with its 3rd argument as\n    \"true\" and then the resultant phy device needs to be\n    register with phy layer via phy_device_register()\n\n    Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>\n\ncommit 217cf01a1eb7c0a1f44c250ab05bb832287069ca\nAuthor: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>\nDate:   Wed Nov 29 12:21:43 2017 +0530\n\n    staging: fsl_ppfe/eth: Disable autonegotiation for 2.5G SGMII\n\n    PCS initialization sequence for 2.5G SGMII interface governs\n    auto negotiation to be in disabled mode\n\n    Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>\n\ncommit 0758955e5d8be44260c3b6877ff78e18c2dc2706\nAuthor: Calvin Johnson <calvin.johnson@nxp.com>\nDate:   Thu Mar 8 13:58:38 2018 +0530\n\n    staging: fsl_ppfe/eth: calculate PFE_PKT_SIZE with SKB_DATA_ALIGN\n\n    pfe packet size was calculated without considering skb data alignment\n    and this resulted in jumbo frames crashing kernel when the\n    cacheline size increased from 64 to 128 bytes with\n    commit 97303480753e (\"arm64: Increase the max granular size\").\n\n    Modify pfe packet size caclulation to include skb data alignment of\n    sizeof(struct skb_shared_info).\n\n    Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>\n\ncommit d336c470781a28fe44a494b4f537a4dbac9fd1dd\nAuthor: Akhil Goyal <akhil.goyal@nxp.com>\nDate:   Fri Apr 13 15:41:28 2018 +0530\n\n    staging: fsl_ppfe/eth: support for userspace networking\n\n    This patch adds the userspace mode support to fsl_ppfe network driver.\n    In the new mode, basic hardware initialization is performed in kernel, while\n    the datapath and HIF handling is the responsibility of the userspace.\n\n    The new command line parameter is added to initialize the ppfe module\n    in userspace mode. By default the module remains in kernelspace networking\n    mode.\n    To enable userspace mode, use \"insmod pfe.ko us=1\"\n\n    Signed-off-by: Akhil Goyal <akhil.goyal@nxp.com>\n    Signed-off-by: Gagandeep Singh <g.singh@nxp.com>\n\ncommit 30f97a6ae76cf7a284fee4b8ad30bce24568ac53\nAuthor: Calvin Johnson <calvin.johnson@nxp.com>\nDate:   Mon Apr 30 11:40:01 2018 +0530\n\n    staging: fsl_ppfe/eth: unregister netdev after pfe_phy_exit\n\n    rmmod pfe.ko throws below warning:\n\n    kernfs: can not remove 'phydev', no directory\n    ------------[ cut here ]------------\n    WARNING: CPU: 0 PID: 2230 at fs/kernfs/dir.c:1481\n    kernfs_remove_by_name_ns+0x90/0xa0\n\n    This is caused when the unregistered netdev structure is accessed to\n    disconnect phy.\n\n    Resolve the issue by unregistering netdev after disconnecting phy.\n\n    Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>\n\ncommit 1b7daa665cd53fe51f19689c5b209fd89551f131\nAuthor: anuj batham <anuj.batham@nxp.com>\nDate:   Fri Apr 27 14:38:09 2018 +0530\n\n    staging: fsl_ppfe/eth: HW parse results for DPDK\n\n    HW Parse results are included in the packet headroom.\n    Length and Offset calculation now accommodates parse info size.\n\n    Signed-off-by: Archana Madhavan <archana.madhavan@nxp.com>\n\ncommit 0aeb9981d44aad6a45eb8f3ead37f91258be173f\nAuthor: Calvin Johnson <calvin.johnson@nxp.com>\nDate:   Wed Jun 20 10:22:32 2018 +0530\n\n    staging: fsl_ppfe/eth: reorganize pfe_netdev_ops\n\n    Reorganize members of struct pfe_netdev_ops to match with the order\n    of members in struct net_device_ops defined in include/linux/netdevice.h\n\n    Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>\n\ncommit 1cbccc5028c337e7c88bf61cf89038cfad449d34\nAuthor: Calvin Johnson <calvin.johnson@nxp.com>\nDate:   Wed Jun 20 10:22:50 2018 +0530\n\n    staging: fsl_ppfe/eth: use mask for rx max frame len\n\n    Define and use PFE_RCR_MAX_FL_MASK to properly set Rx max frame\n    length of MAC Receive Control Register.\n\n    Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>\n\ncommit d8c8ed721470bd47ad5414d8fdc5d093cdd247f7\nAuthor: Calvin Johnson <calvin.johnson@nxp.com>\nDate:   Wed Jun 20 10:23:01 2018 +0530\n\n    staging: fsl_ppfe/eth: define pfe ndo_change_mtu function\n\n    Define ndo_change_mtu function for pfe. This sets the max Rx frame\n    length to the new mtu.\n\n    Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>\n\ncommit f5f50edda84cf9305db06310536525c206970d6c\nAuthor: Calvin Johnson <calvin.johnson@nxp.com>\nDate:   Wed Jun 20 10:23:16 2018 +0530\n\n    staging: fsl_ppfe/eth: remove jumbo frame enable from gemac init\n\n    MAC Receive Control Register was configured to allow jumbo frames.\n    This is removed as jumbo frames can be supported anytime by changing\n    mtu which will in turn modify MAX_FL field of MAC RCR.\n    Jumbo frames caused pfe to hang on LS1012A rev 1.0 Silicon due to\n    erratum A-010897.\n\n    Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>\n\ncommit 53e3c57af87d72ee0299a723499bd911cb1ed25a\nAuthor: Calvin Johnson <calvin.johnson@nxp.com>\nDate:   Wed Jun 20 10:23:32 2018 +0530\n\n    staging: fsl_ppfe/eth: disable CRC removal\n\n    Disable CRC removal from the packet, so that packets are forwarded\n    as is to Linux.\n    CRC configuration in MAC will be reflected in the packet received\n    to Linux.\n\n    Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>\n\ncommit eb55f7878a6ece7edbecd648e147a5683da18c76\nAuthor: Calvin Johnson <calvin.johnson@nxp.com>\nDate:   Wed Jun 20 10:23:41 2018 +0530\n\n    staging: fsl_ppfe/eth: handle ls1012a errata_a010897\n\n    On LS1012A rev 1.0, Jumbo frames are not supported as it causes\n    the PFE controller to hang. A reset of the entire chip is required\n    to resume normal operation.\n\n    To handle this errata, frames with length > 1900 are truncated for\n    rev 1.0 of LS1012A.\n\n    Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>\n\ncommit c7b4f5f8f74925ce1d209ee4fcd5973d5cc5b61c\nAuthor: Calvin Johnson <calvin.johnson@nxp.com>\nDate:   Thu Oct 4 09:38:34 2018 +0530\n\n    staging: fsl_ppfe/eth: replace magic numbers\n\n    Replace magic numbers and some cosmetic changes.\n\n    Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>\n\ncommit c0ed379aa248dd70b2acf5dd8908bec1f6de5487\nAuthor: Calvin Johnson <calvin.johnson@nxp.com>\nDate:   Thu Oct 4 09:39:00 2018 +0530\n\n    staging: fsl_ppfe/eth: resolve indentation warning\n\n    Resolve the following indentation warning:\n\n    drivers/staging/fsl_ppfe/pfe_ls1012a_platform.c:\n    In function ‘pfe_get_gemac_if_proprties’:\n    drivers/staging/fsl_ppfe/pfe_ls1012a_platform.c:96:2:\n    warning: this ‘else’ clause does not guard...\n    [-Wmisleading-indentation]\n      else\n      ^~~~\n    drivers/staging/fsl_ppfe/pfe_ls1012a_platform.c:98:3:\n    note: ...this statement, but the latter is misleadingly indented as\n    if it were guarded by the ‘else’\n       pdata->ls1012a_eth_pdata[port].mdio_muxval = phy_id;\n       ^~~~~\n\n    Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>\n\ncommit c509cb585af2848dbb4ab194bf0fa435e356cb0a\nAuthor: Calvin Johnson <calvin.johnson@nxp.com>\nDate:   Thu Oct 4 09:38:17 2018 +0530\n\n    staging: fsl_ppfe/eth: add fixed-link support\n\n    In cases where MAC is not connected to a normal MDIO-managed PHY\n    device, and instead to a switch, it is configured as a \"fixed-link\".\n    Code to handle this scenario is added here.\n\n    phy_node in the dtb is checked to identify a fixed-link.\n    On identification of a fixed-link, it is registered and connected.\n\n    Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>\n\ncommit 5e93b6ed52d4cdce12a481866c6f211299940734\nAuthor: Shreyansh Jain <shreyansh.jain@nxp.com>\nDate:   Wed Jun 6 14:19:34 2018 +0530\n\n    staging: fsl_ppfe: add support for a char dev for link status\n\n    Read and IOCTL support is added. Application would need to open,\n    read/ioctl the /dev/pfe_us_cdev device.\n    select is pending as it requires a wait_queue.\n\n    Signed-off-by: Shreyansh Jain <shreyansh.jain@nxp.com>\n    Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>\n\ncommit 48e064df94157b0c34f2d75e164ea5c7f4970b7b\nAuthor: Akhil Goyal <akhil.goyal@nxp.com>\nDate:   Thu Jul 5 20:14:21 2018 +0530\n\n    staging: fsl_ppfe: enable hif event from userspace\n\n    HIF interrupts are enabled using ioctl from user space,\n    and epoll wait from user space wakes up when there is an HIF\n    interrupt.\n\n    Signed-off-by: Akhil Goyal <akhil.goyal@nxp.com>\n\ncommit d16d91d3250abec31422b28ff04a973b8b3d73c5\nAuthor: Akhil Goyal <akhil.goyal@nxp.com>\nDate:   Fri Jul 20 16:43:25 2018 +0530\n\n    staging: fsl_ppfe: performance tuning for user space\n\n    interrupt coalescing of 100 usec is added.\n\n    Signed-off-by: Akhil Goyal <akhil.goyal@nxp.com>\n    Signed-off-by: Sachin Saxena <sachin.saxena@nxp.com>\n\ncommit eadb4c9d3e37c44659284fc9190d7e4f04b12aa0\nAuthor: Calvin Johnson <calvin.johnson@nxp.com>\nDate:   Tue Nov 20 21:50:23 2018 +0530\n\n    staging: fsl_ppfe/eth: Update to use SPDX identifiers\n\n    Replace license text with corresponding SPDX identifiers and update the\n    format of existing SPDX identifiers to follow the new guideline\n    Documentation/process/license-rules.rst.\n\n    Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>\n\ncommit a468be7bda6fd98afab1cccb4e7151f23ca096e9\nAuthor: Calvin Johnson <calvin.johnson@nxp.com>\nDate:   Tue Nov 20 21:50:40 2018 +0530\n\n    staging: fsl_ppfe/eth: misc clean up\n\n    - remove redundant hwfeature init\n    - remove unused vars from ls1012a_eth_platform_data\n    - To handle ls1012a errata_a010897, PPFE driver requires GUTS driver\n    to be compiled in. Select FSL_GUTS when PPFE driver is compiled.\n\n    Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>\n\ncommit 0e37bfbeda9510688ad987251aa07e3c88d6ba41\nAuthor: Calvin Johnson <calvin.johnson@nxp.com>\nDate:   Tue Nov 20 21:50:51 2018 +0530\n\n    staging: fsl_ppfe/eth: reorganize platform phy parameters\n\n    - Use \"phy-handle\" and of_* functions to get phy node and fixed-link\n    parameters\n\n    - Reorganize phy parameters and initialize them only if phy-handle\n    or fixed-link is defined in the dtb.\n\n    - correct typo pfe_get_gemac_if_proprties to pfe_get_gemac_if_properties\n\n    Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>\n\ncommit c8703ab06e644e853b12baf082dd703f6a4440a5\nAuthor: Calvin Johnson <calvin.johnson@nxp.com>\nDate:   Fri Nov 23 23:58:28 2018 +0530\n\n    staging: fsl_ppfe/eth: support single interface initialization\n\n    - arrange members of struct mii_bus in sequence matching phy.h\n    - if mdio node is defined, use of_mdiobus_register to register\n      child nodes (phy devices) available on the mdio bus.\n    - remove of_phy_register_fixed_link from pfe_phy_init as it is being\n      handled in pfe_get_gemac_if_properties\n    - remove mdio enabled check\n    - skip phy init, if no PHY or fixed-link\n\n    Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>\n\ncommit 89804e2d74002d01ea3f174048176e498298329a\nAuthor: Calvin Johnson <calvin.johnson@nxp.com>\nDate:   Tue Nov 20 21:51:53 2018 +0530\n\n    net: fsl_ppfe: update dts properties for phy\n\n    Use commonly used phy-handle property and mdio subnode to handle\n    phy properties.\n\n    Deprecate bindings fsl,gemac-phy-id & fsl,pfe-phy-if-flags.\n\n    Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>\n\ncommit 5b0cc262ba7791fb0fae1f81f9619f54a15a75ba\nAuthor: Calvin Johnson <calvin.johnson@nxp.com>\nDate:   Fri Dec 7 19:30:03 2018 +0530\n\n    staging: fsl_ppfe/eth: remove unused code\n\n    - remove gemac-bus-id related code that is unused.\n    - remove unused prototype gemac_set_mdc_div.\n\n    Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>\n\ncommit a5a237f331ab7fcd85b95466f481ddb7023aecc3\nAuthor: Calvin Johnson <calvin.johnson@nxp.com>\nDate:   Mon Dec 10 10:22:33 2018 +0530\n\n    staging: fsl_ppfe/eth: separate mdio init from mac init\n\n    - separate mdio initialization from mac initialization\n    - Define pfe_mdio_priv_s structure to hold mii_bus structure and other\n      related data.\n    - Modify functions to work with the separted mdio init model.\n\n    Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>\n\ncommit 262a03c082de5a93efd7f54bec48b39cda9042a8\nAuthor: Calvin Johnson <calvin.johnson@nxp.com>\nDate:   Wed Mar 27 13:25:57 2019 +0530\n\n    staging: fsl_ppfe/eth: adapt to link mode based phydev changes\n\n    Setting link mode bits have changed with the integration of\n    commit (3c1bcc8 net: ethernet: Convert phydev advertize and\n    supported from u32 to link mode). Adapt to the new method of\n    setting and clearing the link mode bits.\n\n    Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>\n\ncommit 75f911d8ae45215f1c188191da92905ad3f7ad4a\nAuthor: Calvin Johnson <calvin.johnson@nxp.com>\nDate:   Wed Mar 27 19:31:35 2019 +0530\n\n    staging: fsl_ppfe/eth: use generic soc_device infra instead of fsl_guts_get_svr()\n\n    Commit (\"soc: fsl: guts: make fsl_guts_get_svr() static\") has\n    made fsl_guts_get_svr() static and hence use generic soc_device\n    infrastructure to check SoC revision.\n\n    Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>\n\ncommit 0a0ca3d898d15b3d7a206597a68f28134d4dfebd\nAuthor: Calvin Johnson <calvin.johnson@nxp.com>\nDate:   Tue Mar 26 16:52:22 2019 +0530\n\n    staging: fsl_ppfe/eth: use memremap() to map RAM area used by PFE\n\n    RAM area used by PFE should be mapped using memremap() instead of\n    directly traslating physical addr to virtual. This will ensure proper\n    checks are done before the area is used.\n\n    Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>\n\ncommit bfc0c2fedb76ad9c888db421b435d51e33fe276a\nAuthor: Li Yang <leoyang.li@nxp.com>\nDate:   Tue Jun 11 18:24:37 2019 -0500\n\n    staging: fsl_ppfe/eth: remove 'fallback' argument from dev->ndo_select_queue()\n\n    To be consistent with upstream API change.\n\n    Signed-off-by: Li Yang <leoyang.li@nxp.com>\n\ncommit cfd0841983961067efe69379371ddcb49b230dac\nAuthor: Ting Liu <ting.liu@nxp.com>\nDate:   Mon Jun 17 09:27:53 2019 +0200\n\n    staging: fsl_ppfe/eth: prefix header search paths with $(srctree)/\n\n    Currently, the rules for configuring search paths in Kbuild have\n    changed: https://lkml.org/lkml/2019/5/13/37\n\n    This will lead the below error:\n\n    fatal error: pfe/pfe.h: No such file or directory\n\n    Fix it by adding $(srctree)/ prefix to the search paths.\n\n    Signed-off-by: Ting Liu <ting.liu@nxp.com>\n\ncommit 4be722099e4b6bdff2e683234ffaa2dc62fc773d\nAuthor: Calvin Johnson <calvin.johnson@nxp.com>\nDate:   Wed Nov 1 11:11:30 2017 +0530\n\n    staging: fsl_ppfe/eth: add pfe support to Kconfig and Makefile\n\n    Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>\n    [ Aisheng: fix minor conflict due to removed VBOXSF_FS ]\n    Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>\n\ncommit 5a2c9482ec3959dc2010f99897359b9e4006d2a4\nAuthor: Nagesh Koneti <koneti.nagesh@nxp.com>\nDate:   Wed Sep 25 12:01:19 2019 +0530\n\n    staging: fsl_ppfe/eth: Disable termination of CRC fwd.\n\n    LS1012A MAC PCS block has an erratum that is seen with specific PHY AR803x.\n    The issue is triggered by the (spec-compliant) operation of the AR803x PHY\n    on the LS1012A-FRWY board.Due to this, good FCS packet is reported as error\n    packet by MAC, so for these error packets FCS should be validated and\n    discard only real error packets in PFE Rx packet path.\n\n    Signed-off-by: Nagesh Koneti <koneti.nagesh@nxp.com>\n    Signed-off-by: Nagesh Koneti <“koneti.nagesh@nxp.com”>\n\ncommit 36344cfc28f4cbdf606330ab8929e10d0778a087\nAuthor: Li Yang <leoyang.li@nxp.com>\nDate:   Sun Dec 8 18:19:18 2019 -0600\n\n    net: ppfe: Cope with of_get_phy_mode() API change\n\n    Signed-off-by: Li Yang <leoyang.li@nxp.com>\n\ncommit ee2a796cf8990ac06f329c580f18fffefbac6a9a\nAuthor: Anji Jagarlmudi <anji.jagarlmudi@nxp.com>\nDate:   Wed Jan 8 19:06:12 2020 +0530\n\n    staging: fsl_ppfe/eth: Enhance error checking in platform probe\n\n    Fix the kernel crash when MAC addr is not passed in dtb.\n\n    Signed-off-by: Anji Jagarlmudi <anji.jagarlmudi@nxp.com>\n\ncommit 2e8ca14ea6cc8d6816f2a445f3610f6b5b852e7c\nAuthor: Anji Jagarlmudi <anji.jagarlmudi@nxp.com>\nDate:   Mon Apr 6 19:46:05 2020 +0530\n\n    staging: fsl_ppfe/eth: reject unsupported coalescing params\n\n    Set ethtool_ops->supported_coalesce_params to let\n    the core reject unsupported coalescing parameters.\n\n    Signed-off-by: Anji Jagarlmudi <anji.jagarlmudi@nxp.com>\n\ncommit 7ce4dd75c94d8a7dbe4e4ad747b4ddc5be6d83b4\nAuthor: Chaitanya Sakinam <chaitanya.sakinam@nxp.com>\nDate:   Sat Mar 28 00:30:53 2020 +0530\n\n    staging: fsl_ppfe/eth:check \"reg\" property before pfe_get_gemac_if_properties()\n\n    It has been observed that the function pfe_get_gemac_if_properties() is\n    been called blindly for the next two child nodes. There might be some\n    cases where it may go wrong and that lead to missing interfaces.\n    with these changes it is ensured thats not the case.\n\n    Signed-off-by: Chaitanya Sakinam <chaitanya.sakinam@nxp.com>\n    Signed-off-by: Anji J <anji.jagarlmudi@nxp.com>\n\ncommit 7ba7cfb799c8928f4963f86a1ad47e2dd56022b2\nAuthor: Chaitanya Sakinam <chaitanya.sakinam@nxp.com>\nDate:   Sat Mar 28 00:34:13 2020 +0530\n\n    staging: fsl_ppfe/eth: \"struct firmware\" dereference is reduced in many functions\n\n    firmware structure's data variable is the actual elf data. It has been\n    dereferenced in multiple functions and this has been reduced.\n\n    Signed-off-by: Chaitanya Sakinam <chaitanya.sakinam@nxp.com>\n    Signed-off-by: Anji J <anji.jagarlmudi@nxp.com>\n\ncommit 443538bb09b979fcc98a58e18a3eb8cebe25ad4f\nAuthor: Chaitanya Sakinam <chaitanya.sakinam@nxp.com>\nDate:   Sun Mar 29 18:05:50 2020 +0530\n\n    staging: fsl_ppfe/eth: LF-27 load pfe binaries from FDT\n\n    FDT prepared in uboot now has pfe firmware part of it.\n    These changes will read the firmware by default from it and tries to load\n    the elf into the PFE PEs. This help build the pfe driver pasrt of kernel.\n\n    Signed-off-by: Chaitanya Sakinam <chaitanya.sakinam@nxp.com>\n    Signed-off-by: Anji J <anji.jagarlmudi@nxp.com>\n\ncommit 2b1f551c2aee4550ffca5f86031bc4f5e6ccb848\nAuthor: Chaitanya Sakinam <chaitanya.sakinam@nxp.com>\nDate:   Tue Jun 9 15:33:42 2020 +0530\n\n    staging: fsl_ppfe/eth: proper handling for RGMII delay mode\n\n    The correct setting for the RGMII ports on LS1012ARDB is to\n    enable delay on both Tx and Rx. So the phy mode to be matched\n    is PHY_INTERFACE_MODE_RGMII_ID.\n\n    Signed-off-by: Chaitanya Sakinam <chaitanya.sakinam@nxp.com>\n    Signed-off-by: Anji Jagarlmudi <anji.jagarlmudi@nxp.com>\n\ncommit a95d84b87e743bd7c57b287901524f2cffbf38d7\nAuthor: Dong Aisheng <aisheng.dong@nxp.com>\nDate:   Wed Jul 15 16:06:24 2020 +0800\n\n    LF-1762-2 staging: fsl_ppfe: replace '---help---' in Kconfig files with 'help'\n\n    Update Kconfig to cope with upstream change\n    commit 84af7a6194e4 (\"checkpatch: kconfig: prefer 'help' over\n    '---help---'\").\n\n    Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>\n\ncommit 546ef027c2b0768517d903429d56bcd89b919e6d\nAuthor: Chaitanya Sakinam <chaitanya.sakinam@nxp.com>\nDate:   Wed Jul 15 10:36:07 2020 +0530\n\n    staging: fsl_ppfe/eth: Nesting level does not match indentation\n\n    corrected nesting level\n    LF-1661 and Coverity CID: 8879316\n\n    Signed-off-by: Chaitanya Sakinam <chaitanya.sakinam@nxp.com>\n\ncommit c76a95f776e0f3e1a2c8abc1748c662151e29be5\nAuthor: Chaitanya Sakinam <chaitanya.sakinam@nxp.com>\nDate:   Wed Jul 15 11:19:57 2020 +0530\n\n    staging: fsl_ppfe/eth: Initialized scalar variable\n\n    Proper initialization of scalar variable\n    LF-1657 and Coverity CID: 3335133\n\n    Signed-off-by: Chaitanya Sakinam <chaitanya.sakinam@nxp.com>\n\ncommit f48286af915f664c15aa327aaf6d9b61d33eea67\nAuthor: Chaitanya Sakinam <chaitanya.sakinam@nxp.com>\nDate:   Wed Jul 15 11:47:50 2020 +0530\n\n    staging: fsl_ppfe/eth: misspelt variable name\n\n    variable name corrected\n    LF-1656 and Coverity CID: 3335119\n\n    Signed-off-by: Chaitanya Sakinam <chaitanya.sakinam@nxp.com>\n\ncommit a5e006f71fce8e76831704b31218f3d57c0b9924\nAuthor: Chaitanya Sakinam <chaitanya.sakinam@nxp.com>\nDate:   Wed Jul 15 12:10:47 2020 +0530\n\n    staging: fsl_ppfe/eth: Avoiding out-of-bound writes\n\n    avoid out-of-bound writes with proper error handling\n    LF-1654, LF-1652 and Coverity CID: 3335106, 3335090\n\n    Signed-off-by: Chaitanya Sakinam <chaitanya.sakinam@nxp.com>\n\ncommit 957fde83420b6a74a5e96b2f27183274b04211d9\nAuthor: Chaitanya Sakinam <chaitanya.sakinam@nxp.com>\nDate:   Wed Jul 15 13:09:35 2020 +0530\n\n    staging: fsl_ppfe/eth: Initializing scalar variable\n\n    proper initialization of scalar variable.\n    LF-1653 and Coverity CID: 3335101\n\n    Signed-off-by: Chaitanya Sakinam <chaitanya.sakinam@nxp.com>\n\ncommit fae95666a4c992b7f9035ee978e3e289495cbd47\nAuthor: Chaitanya Sakinam <chaitanya.sakinam@nxp.com>\nDate:   Wed Jul 15 13:45:50 2020 +0530\n\n    staging: fsl_ppfe/eth: checking return value\n\n    proper checks added and handled for return value.\n    LF-1644 and Coverity CID: 241888\n\n    Signed-off-by: Chaitanya Sakinam <chaitanya.sakinam@nxp.com>\n\ncommit 5bf7baddb22ecafd6064c9062a804bcd17a326cc\nAuthor: Chaitanya Sakinam <chaitanya.sakinam@nxp.com>\nDate:   Wed Jul 15 14:04:10 2020 +0530\n\n    staging: fsl_ppfe/eth: Avoid out-of-bound access\n\n    proper handling to avoid out-of-bound access\n    LF-1642, LF-1641 and Coverity CID: 240910, 240891\n\n    Signed-off-by: Chaitanya Sakinam <chaitanya.sakinam@nxp.com>\n\ncommit b15d480d66277fc00bc610a91af56263733a4e13\nAuthor: Chaitanya Sakinam <chaitanya.sakinam@nxp.com>\nDate:   Fri Jul 31 10:19:00 2020 +0530\n\n    staging: fsl_ppfe/eth: Avoiding out-of-bound writes\n\n    avoid out-of-bound writes with proper error handling\n    LF-1654, LF-1652 and Coverity CID: 3335106, 3335090\n\n    Signed-off-by: Chaitanya Sakinam <chaitanya.sakinam@nxp.com>\n\ncommit 188992fc4d4173c6bb36e924b5833bb092f7d602\nAuthor: Chaitanya Sakinam <chaitanya.sakinam@nxp.com>\nDate:   Fri Jul 31 10:23:59 2020 +0530\n\n    staging: fsl_ppfe/eth: return value init in error case\n\n    proper err return in error case.\n    LF-1806 and Coverity CID: 10468592\n\n    Signed-off-by: Chaitanya Sakinam <chaitanya.sakinam@nxp.com>\n\ncommit 26d6dd0bd1331dd07764914033fd8e98777fc165\nAuthor: Chaitanya Sakinam <chaitanya.sakinam@nxp.com>\nDate:   Thu Aug 13 12:04:48 2020 +0530\n\n    staging: fsl_ppfe/eth: Avoid recursion in header inclusion\n\n    Avoiding header inclusions that are not necessary and also that are\n    causing header inclusion recursion.\n\n    LF-2102 and Coverity CID: 240838\n\n    Signed-off-by: Chaitanya Sakinam <chaitanya.sakinam@nxp.com>\n\ncommit f18618582d078b87c9ee2e93ebbffee44cd76ec0\nAuthor: Chaitanya Sakinam <chaitanya.sakinam@nxp.com>\nDate:   Thu Aug 13 12:28:25 2020 +0530\n\n    staging: fsl_ppfe/eth: Avoiding return value overwrite\n\n    avoid return value overwrite at the end of function.\n    LF-2136, LF-2137 and Coverity CID: 8879341, 8879364\n\n    Signed-off-by: Chaitanya Sakinam <chaitanya.sakinam@nxp.com>\n\ncommit 4cd4e5f325516d91c630311af4d36472ce19124e\nAuthor: Chaitanya Sakinam <chaitanya.sakinam@nxp.com>\nDate:   Wed Sep 9 17:50:10 2020 +0530\n\n    staging: fsl_ppfe/eth: LF-27 enabling PFE firmware load from FDT\n\n    The macro, \"LOAD_PFEFIRMWARE_FROM_FILESYSTEM\" is been disabled to load\n    the firmware from FDT by default. Enabling the macro will load the\n    firmware from filesystem.\n\n    Also, the Makefile is now tuned to build pfe as per the config option\n\n    Signed-off-by: Chaitanya Sakinam <chaitanya.sakinam@nxp.com>\n\ncommit 175a310323ccfab0025f2da56799bb3939b65c9d\nAuthor: Chaitanya Sakinam <chaitanya.sakinam@nxp.com>\nDate:   Thu Apr 9 18:17:48 2020 +0530\n\n    staging: fsl_ppfe/eth: Ethtool stats correction for IEEE_rx_drop counter\n\n    Due to carrier extended bug the phy counter IEEE_rx_drop counter is\n    incremented some times and phy reports the packet has crc error.\n    Because of this PFE revalidates all the packets that are marked crc\n    error by phy. Now, the counter phy reports is till bogus and this\n    patch decrements the counter by pfe revalidated (and are crc ok)\n    counter amount.\n\n    Signed-off-by: Chaitanya Sakinam <chaitanya.sakinam@nxp.com>\n\ncommit a4683911f7a7d71762a90dabf72faadab5766774\nAuthor: Chaitanya Sakinam <chaitanya.sakinam@nxp.com>\nDate:   Wed Sep 30 17:20:19 2020 +0530\n\n    staging: fsl_ppfe/eth: PFE firmware load enhancements\n\n    PFE driver enhancements to load the PE firmware from filesystem\n    when the firmware is not found in FDT.\n\n    Signed-off-by: Chaitanya Sakinam <chaitanya.sakinam@nxp.com>\n---\n .../devicetree/bindings/net/fsl_ppfe/pfe.txt  |  199 ++\n MAINTAINERS                                   |    8 +\n drivers/staging/Kconfig                       |    2 +\n drivers/staging/Makefile                      |    1 +\n drivers/staging/fsl_ppfe/Kconfig              |   21 +\n drivers/staging/fsl_ppfe/Makefile             |   20 +\n drivers/staging/fsl_ppfe/TODO                 |    2 +\n drivers/staging/fsl_ppfe/include/pfe/cbus.h   |   78 +\n .../staging/fsl_ppfe/include/pfe/cbus/bmu.h   |   55 +\n .../fsl_ppfe/include/pfe/cbus/class_csr.h     |  289 ++\n .../fsl_ppfe/include/pfe/cbus/emac_mtip.h     |  242 ++\n .../staging/fsl_ppfe/include/pfe/cbus/gpi.h   |   86 +\n .../staging/fsl_ppfe/include/pfe/cbus/hif.h   |  100 +\n .../fsl_ppfe/include/pfe/cbus/hif_nocpy.h     |   50 +\n .../fsl_ppfe/include/pfe/cbus/tmu_csr.h       |  168 ++\n .../fsl_ppfe/include/pfe/cbus/util_csr.h      |   61 +\n drivers/staging/fsl_ppfe/include/pfe/pfe.h    |  372 +++\n drivers/staging/fsl_ppfe/pfe_cdev.c           |  258 ++\n drivers/staging/fsl_ppfe/pfe_cdev.h           |   41 +\n drivers/staging/fsl_ppfe/pfe_ctrl.c           |  226 ++\n drivers/staging/fsl_ppfe/pfe_ctrl.h           |  100 +\n drivers/staging/fsl_ppfe/pfe_debugfs.c        |   99 +\n drivers/staging/fsl_ppfe/pfe_debugfs.h        |   13 +\n drivers/staging/fsl_ppfe/pfe_eth.c            | 2587 +++++++++++++++++\n drivers/staging/fsl_ppfe/pfe_eth.h            |  175 ++\n drivers/staging/fsl_ppfe/pfe_firmware.c       |  398 +++\n drivers/staging/fsl_ppfe/pfe_firmware.h       |   21 +\n drivers/staging/fsl_ppfe/pfe_hal.c            | 1517 ++++++++++\n drivers/staging/fsl_ppfe/pfe_hif.c            | 1064 +++++++\n drivers/staging/fsl_ppfe/pfe_hif.h            |  199 ++\n drivers/staging/fsl_ppfe/pfe_hif_lib.c        |  628 ++++\n drivers/staging/fsl_ppfe/pfe_hif_lib.h        |  229 ++\n drivers/staging/fsl_ppfe/pfe_hw.c             |  164 ++\n drivers/staging/fsl_ppfe/pfe_hw.h             |   15 +\n .../staging/fsl_ppfe/pfe_ls1012a_platform.c   |  383 +++\n drivers/staging/fsl_ppfe/pfe_mod.c            |  158 +\n drivers/staging/fsl_ppfe/pfe_mod.h            |  103 +\n drivers/staging/fsl_ppfe/pfe_perfmon.h        |   26 +\n drivers/staging/fsl_ppfe/pfe_sysfs.c          |  840 ++++++\n drivers/staging/fsl_ppfe/pfe_sysfs.h          |   17 +\n 40 files changed, 11015 insertions(+)\n create mode 100644 Documentation/devicetree/bindings/net/fsl_ppfe/pfe.txt\n create mode 100644 drivers/staging/fsl_ppfe/Kconfig\n create mode 100644 drivers/staging/fsl_ppfe/Makefile\n create mode 100644 drivers/staging/fsl_ppfe/TODO\n create mode 100644 drivers/staging/fsl_ppfe/include/pfe/cbus.h\n create mode 100644 drivers/staging/fsl_ppfe/include/pfe/cbus/bmu.h\n create mode 100644 drivers/staging/fsl_ppfe/include/pfe/cbus/class_csr.h\n create mode 100644 drivers/staging/fsl_ppfe/include/pfe/cbus/emac_mtip.h\n create mode 100644 drivers/staging/fsl_ppfe/include/pfe/cbus/gpi.h\n create mode 100644 drivers/staging/fsl_ppfe/include/pfe/cbus/hif.h\n create mode 100644 drivers/staging/fsl_ppfe/include/pfe/cbus/hif_nocpy.h\n create mode 100644 drivers/staging/fsl_ppfe/include/pfe/cbus/tmu_csr.h\n create mode 100644 drivers/staging/fsl_ppfe/include/pfe/cbus/util_csr.h\n create mode 100644 drivers/staging/fsl_ppfe/include/pfe/pfe.h\n create mode 100644 drivers/staging/fsl_ppfe/pfe_cdev.c\n create mode 100644 drivers/staging/fsl_ppfe/pfe_cdev.h\n create mode 100644 drivers/staging/fsl_ppfe/pfe_ctrl.c\n create mode 100644 drivers/staging/fsl_ppfe/pfe_ctrl.h\n create mode 100644 drivers/staging/fsl_ppfe/pfe_debugfs.c\n create mode 100644 drivers/staging/fsl_ppfe/pfe_debugfs.h\n create mode 100644 drivers/staging/fsl_ppfe/pfe_eth.c\n create mode 100644 drivers/staging/fsl_ppfe/pfe_eth.h\n create mode 100644 drivers/staging/fsl_ppfe/pfe_firmware.c\n create mode 100644 drivers/staging/fsl_ppfe/pfe_firmware.h\n create mode 100644 drivers/staging/fsl_ppfe/pfe_hal.c\n create mode 100644 drivers/staging/fsl_ppfe/pfe_hif.c\n create mode 100644 drivers/staging/fsl_ppfe/pfe_hif.h\n create mode 100644 drivers/staging/fsl_ppfe/pfe_hif_lib.c\n create mode 100644 drivers/staging/fsl_ppfe/pfe_hif_lib.h\n create mode 100644 drivers/staging/fsl_ppfe/pfe_hw.c\n create mode 100644 drivers/staging/fsl_ppfe/pfe_hw.h\n create mode 100644 drivers/staging/fsl_ppfe/pfe_ls1012a_platform.c\n create mode 100644 drivers/staging/fsl_ppfe/pfe_mod.c\n create mode 100644 drivers/staging/fsl_ppfe/pfe_mod.h\n create mode 100644 drivers/staging/fsl_ppfe/pfe_perfmon.h\n create mode 100644 drivers/staging/fsl_ppfe/pfe_sysfs.c\n create mode 100644 drivers/staging/fsl_ppfe/pfe_sysfs.h\n\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/net/fsl_ppfe/pfe.txt\n@@ -0,0 +1,199 @@\n+=============================================================================\n+NXP Programmable Packet Forwarding Engine Device Bindings\n+\n+CONTENTS\n+  - PFE Node\n+  - Ethernet Node\n+\n+=============================================================================\n+PFE Node\n+\n+DESCRIPTION\n+\n+PFE Node has all the properties associated with Packet Forwarding Engine block.\n+\n+PROPERTIES\n+\n+- compatible\n+\t\tUsage: required\n+\t\tValue type: <stringlist>\n+\t\tDefinition: Must include \"fsl,pfe\"\n+\n+- reg\n+\t\tUsage: required\n+\t\tValue type: <prop-encoded-array>\n+\t\tDefinition: A standard property.\n+\t\tSpecifies the offset of the following registers:\n+\t\t- PFE configuration registers\n+\t\t- DDR memory used by PFE\n+\n+- fsl,pfe-num-interfaces\n+\t\tUsage: required\n+\t\tValue type: <u32>\n+\t\tDefinition: Must be present. Value can be either one or two.\n+\n+- interrupts\n+\t\tUsage: required\n+\t\tValue type: <prop-encoded-array>\n+\t\tDefinition: Three interrupts are specified in this property.\n+\t\t- HIF interrupt\n+\t\t- HIF NO COPY interrupt\n+\t\t- Wake On LAN interrupt\n+\n+- interrupt-names\n+\t\tUsage: required\n+\t\tValue type: <stringlist>\n+\t\tDefinition: Following strings are defined for the 3 interrupts.\n+\t\t\"pfe_hif\" - HIF interrupt\n+\t\t\"pfe_hif_nocpy\" - HIF NO COPY interrupt\n+\t\t\"pfe_wol\" - Wake On LAN interrupt\n+\n+- memory-region\n+\t\tUsage: required\n+\t\tValue type: <phandle>\n+\t\tDefinition: phandle to a node describing reserved memory used by pfe.\n+\t\tRefer:- Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt\n+\n+- fsl,pfe-scfg\n+\t\tUsage: required\n+\t\tValue type: <phandle>\n+\t\tDefinition: phandle for scfg.\n+\n+- fsl,rcpm-wakeup\n+\t\tUsage: required\n+\t\tValue type: <phandle>\n+\t\tDefinition: phandle for rcpm.\n+\n+- clocks\n+\t\tUsage: required\n+\t\tValue type: <phandle>\n+\t\tDefinition: phandle for clockgen.\n+\n+- clock-names\n+\t\tUsage: required\n+\t\tValue type: <string>\n+\t\tDefinition: phandle for clock name.\n+\n+EXAMPLE\n+\n+pfe: pfe@04000000 {\n+\tcompatible = \"fsl,pfe\";\n+\treg =   <0x0 0x04000000 0x0 0xc00000>,\t/* AXI 16M */\n+\t\t<0x0 0x83400000 0x0 0xc00000>;  /* PFE DDR 12M */\n+\treg-names = \"pfe\", \"pfe-ddr\";\n+\tfsl,pfe-num-interfaces = <0x2>;\n+\tinterrupts = <0 172 0x4>,    /* HIF interrupt */\n+\t\t     <0 173 0x4>,    /*HIF_NOCPY interrupt */\n+\t\t     <0 174 0x4>;    /* WoL interrupt */\n+\tinterrupt-names = \"pfe_hif\", \"pfe_hif_nocpy\", \"pfe_wol\";\n+\tmemory-region = <&pfe_reserved>;\n+\tfsl,pfe-scfg = <&scfg 0>;\n+\tfsl,rcpm-wakeup = <&rcpm 0xf0000020>;\n+\tclocks = <&clockgen 4 0>;\n+\tclock-names = \"pfe\";\n+\n+\tstatus = \"okay\";\n+\tpfe_mac0: ethernet@0 {\n+\t};\n+\n+\tpfe_mac1: ethernet@1 {\n+\t};\n+};\n+\n+=============================================================================\n+Ethernet Node\n+\n+DESCRIPTION\n+\n+Ethernet Node has all the properties associated with PFE used by platforms to\n+connect to PHY:\n+\n+PROPERTIES\n+\n+- compatible\n+\t\tUsage: required\n+\t\tValue type: <stringlist>\n+\t\tDefinition: Must include \"fsl,pfe-gemac-port\"\n+\n+- reg\n+\t\tUsage: required\n+\t\tValue type: <prop-encoded-array>\n+\t\tDefinition: A standard property.\n+\t\tSpecifies the gemacid of the interface.\n+\n+- fsl,gemac-bus-id\n+\t\tUsage: required\n+\t\tValue type: <u32>\n+\t\tDefinition: Must be present. Value should be the id of the bus\n+\t\tconnected to gemac.\n+\n+- fsl,gemac-phy-id (deprecated binding)\n+               Usage: required\n+               Value type: <u32>\n+               Definition: This binding shouldn't be used with new platforms.\n+\t       Must be present. Value should be the id of the phy\n+               connected to gemac.\n+\n+- fsl,mdio-mux-val\n+\t\tUsage: required\n+\t\tValue type: <u32>\n+\t\tDefinition: Must be present. Value can be either 0 or 2 or 3.\n+\t\tThis value is used to configure the mux to enable mdio.\n+\n+- phy-mode\n+\t\tUsage: required\n+\t\tValue type: <string>\n+\t\tDefinition: Must include \"sgmii\"\n+\n+- fsl,pfe-phy-if-flags (deprecated binding)\n+               Usage: required\n+               Value type: <u32>\n+               Definition: This binding shouldn't be used with new platforms.\n+               Must be present. Value should be 0 by default.\n+               If there is not phy connected, this need to be 1.\n+\n+- phy-handle\n+\t\tUsage: optional\n+\t\tValue type: <phandle>\n+\t\tDefinition: phandle to the PHY device connected to this device.\n+\n+- mdio : A required subnode which specifies the mdio bus in the PFE and used as\n+a container for phy nodes according to ../phy.txt.\n+\n+EXAMPLE\n+\n+ethernet@0 {\n+\tcompatible = \"fsl,pfe-gemac-port\";\n+\t#address-cells = <1>;\n+\t#size-cells = <0>;\n+\treg = <0x0>;\t/* GEM_ID */\n+\tfsl,gemac-bus-id = <0x0>;\t/* BUS_ID */\n+\tfsl,mdio-mux-val = <0x0>;\n+\tphy-mode = \"sgmii\";\n+\tphy-handle = <&sgmii_phy1>;\n+};\n+\n+\n+ethernet@1 {\n+\tcompatible = \"fsl,pfe-gemac-port\";\n+\t#address-cells = <1>;\n+\t#size-cells = <0>;\n+\treg = <0x1>;\t/* GEM_ID */\n+\tfsl,gemac-bus-id = <0x1>;\t/* BUS_ID */\n+\tfsl,mdio-mux-val = <0x0>;\n+\tphy-mode = \"sgmii\";\n+\tphy-handle = <&sgmii_phy2>;\n+};\n+\n+mdio@0 {\n+\t#address-cells = <1>;\n+\t#size-cells = <0>;\n+\n+\tsgmii_phy1: ethernet-phy@2 {\n+\t\treg = <0x2>;\n+\t};\n+\n+\tsgmii_phy2: ethernet-phy@1 {\n+\t\treg = <0x1>;\n+\t};\n+};\n--- a/MAINTAINERS\n+++ b/MAINTAINERS\n@@ -7068,6 +7068,14 @@ F:\tdrivers/ptp/ptp_qoriq.c\n F:\tdrivers/ptp/ptp_qoriq_debugfs.c\n F:\tinclude/linux/fsl/ptp_qoriq.h\n \n+FREESCALE QORIQ PPFE ETHERNET DRIVER\n+M:\tAnji Jagarlmudi <anji.jagarlmudi@nxp.com>\n+M:\tCalvin Johnson <calvin.johnson@nxp.com>\n+L:\tnetdev@vger.kernel.org\n+S:\tMaintained\n+F:\tdrivers/staging/fsl_ppfe\n+F:\tDocumentation/devicetree/bindings/net/fsl_ppfe/pfe.txt\n+\n FREESCALE QUAD SPI DRIVER\n M:\tHan Xu <han.xu@nxp.com>\n L:\tlinux-spi@vger.kernel.org\n--- a/drivers/staging/Kconfig\n+++ b/drivers/staging/Kconfig\n@@ -118,4 +118,6 @@ source \"drivers/staging/wfx/Kconfig\"\n \n source \"drivers/staging/hikey9xx/Kconfig\"\n \n+source \"drivers/staging/fsl_ppfe/Kconfig\"\n+\n endif # STAGING\n--- a/drivers/staging/Makefile\n+++ b/drivers/staging/Makefile\n@@ -49,3 +49,4 @@ obj-$(CONFIG_KPC2000)\t\t+= kpc2000/\n obj-$(CONFIG_QLGE)\t\t+= qlge/\n obj-$(CONFIG_WFX)\t\t+= wfx/\n obj-y\t\t\t\t+= hikey9xx/\n+obj-$(CONFIG_FSL_PPFE)\t\t+= fsl_ppfe/\n--- /dev/null\n+++ b/drivers/staging/fsl_ppfe/Kconfig\n@@ -0,0 +1,21 @@\n+#\n+# Freescale Programmable Packet Forwarding Engine driver\n+#\n+config FSL_PPFE\n+\ttristate \"Freescale PPFE Driver\"\n+\tselect FSL_GUTS\n+\tdefault n\n+\thelp\n+\tFreescale LS1012A SoC has a Programmable Packet Forwarding Engine.\n+\tIt provides two high performance ethernet interfaces.\n+\tThis driver initializes, programs and controls the PPFE.\n+\tUse this driver to enable network connectivity on LS1012A platforms.\n+\n+if FSL_PPFE\n+\n+config FSL_PPFE_UTIL_DISABLED\n+\tbool \"Disable PPFE UTIL Processor Engine\"\n+\thelp\n+\tUTIL PE has to be enabled only if required.\n+\n+endif # FSL_PPFE\n--- /dev/null\n+++ b/drivers/staging/fsl_ppfe/Makefile\n@@ -0,0 +1,20 @@\n+#\n+# Makefile for Freesecale PPFE driver\n+#\n+\n+ccflags-y +=  -I $(srctree)/$(src)/include  -I $(srctree)/$(src)\n+\n+obj-$(CONFIG_FSL_PPFE) += pfe.o\n+\n+pfe-y += pfe_mod.o \\\n+\tpfe_hw.o \\\n+\tpfe_firmware.o \\\n+\tpfe_ctrl.o \\\n+\tpfe_hif.o \\\n+\tpfe_hif_lib.o\\\n+\tpfe_eth.o \\\n+\tpfe_sysfs.o \\\n+\tpfe_debugfs.o \\\n+\tpfe_ls1012a_platform.o \\\n+\tpfe_hal.o \\\n+\tpfe_cdev.o\n--- /dev/null\n+++ b/drivers/staging/fsl_ppfe/TODO\n@@ -0,0 +1,2 @@\n+TODO:\n+\t- provide pfe pe monitoring support\n--- /dev/null\n+++ b/drivers/staging/fsl_ppfe/include/pfe/cbus.h\n@@ -0,0 +1,78 @@\n+/*\n+ * Copyright 2015-2016 Freescale Semiconductor, Inc.\n+ * Copyright 2017 NXP\n+ *\n+ * This program is free software; you can redistribute it and/or modify\n+ * it under the terms of the GNU General Public License as published by\n+ * the Free Software Foundation; either version 2 of the License, or\n+ * (at your option) any later version.\n+ *\n+ * This program is distributed in the hope that it will be useful,\n+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\n+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n+ * GNU General Public License for more details.\n+ *\n+ * You should have received a copy of the GNU General Public License\n+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.\n+ */\n+\n+#ifndef _CBUS_H_\n+#define _CBUS_H_\n+\n+#define EMAC1_BASE_ADDR\t(CBUS_BASE_ADDR + 0x200000)\n+#define EGPI1_BASE_ADDR\t(CBUS_BASE_ADDR + 0x210000)\n+#define EMAC2_BASE_ADDR\t(CBUS_BASE_ADDR + 0x220000)\n+#define EGPI2_BASE_ADDR\t(CBUS_BASE_ADDR + 0x230000)\n+#define BMU1_BASE_ADDR\t(CBUS_BASE_ADDR + 0x240000)\n+#define BMU2_BASE_ADDR\t(CBUS_BASE_ADDR + 0x250000)\n+#define ARB_BASE_ADDR\t(CBUS_BASE_ADDR + 0x260000)\n+#define DDR_CONFIG_BASE_ADDR\t(CBUS_BASE_ADDR + 0x270000)\n+#define HIF_BASE_ADDR\t(CBUS_BASE_ADDR + 0x280000)\n+#define HGPI_BASE_ADDR\t(CBUS_BASE_ADDR + 0x290000)\n+#define LMEM_BASE_ADDR\t(CBUS_BASE_ADDR + 0x300000)\n+#define LMEM_SIZE\t0x10000\n+#define LMEM_END\t(LMEM_BASE_ADDR + LMEM_SIZE)\n+#define TMU_CSR_BASE_ADDR\t(CBUS_BASE_ADDR + 0x310000)\n+#define CLASS_CSR_BASE_ADDR\t(CBUS_BASE_ADDR + 0x320000)\n+#define HIF_NOCPY_BASE_ADDR\t(CBUS_BASE_ADDR + 0x350000)\n+#define UTIL_CSR_BASE_ADDR\t(CBUS_BASE_ADDR + 0x360000)\n+#define CBUS_GPT_BASE_ADDR\t(CBUS_BASE_ADDR + 0x370000)\n+\n+/*\n+ * defgroup XXX_MEM_ACCESS_ADDR PE memory access through CSR\n+ * XXX_MEM_ACCESS_ADDR register bit definitions.\n+ */\n+#define PE_MEM_ACCESS_WRITE\tBIT(31)\t/* Internal Memory Write. */\n+#define PE_MEM_ACCESS_IMEM\tBIT(15)\n+#define PE_MEM_ACCESS_DMEM\tBIT(16)\n+\n+/* Byte Enables of the Internal memory access. These are interpred in BE */\n+#define PE_MEM_ACCESS_BYTE_ENABLE(offset, size)\t\\\n+\t({ typeof(size) size_ = (size);\t\t\\\n+\t(((BIT(size_) - 1) << (4 - (offset) - (size_))) & 0xf) << 24; })\n+\n+#include \"cbus/emac_mtip.h\"\n+#include \"cbus/gpi.h\"\n+#include \"cbus/bmu.h\"\n+#include \"cbus/hif.h\"\n+#include \"cbus/tmu_csr.h\"\n+#include \"cbus/class_csr.h\"\n+#include \"cbus/hif_nocpy.h\"\n+#include \"cbus/util_csr.h\"\n+\n+/* PFE cores states */\n+#define CORE_DISABLE\t0x00000000\n+#define CORE_ENABLE\t0x00000001\n+#define CORE_SW_RESET\t0x00000002\n+\n+/* LMEM defines */\n+#define LMEM_HDR_SIZE\t0x0010\n+#define LMEM_BUF_SIZE_LN2\t0x7\n+#define LMEM_BUF_SIZE\tBIT(LMEM_BUF_SIZE_LN2)\n+\n+/* DDR defines */\n+#define DDR_HDR_SIZE\t0x0100\n+#define DDR_BUF_SIZE_LN2\t0xb\n+#define DDR_BUF_SIZE\tBIT(DDR_BUF_SIZE_LN2)\n+\n+#endif /* _CBUS_H_ */\n--- /dev/null\n+++ b/drivers/staging/fsl_ppfe/include/pfe/cbus/bmu.h\n@@ -0,0 +1,55 @@\n+/*\n+ * Copyright 2015-2016 Freescale Semiconductor, Inc.\n+ * Copyright 2017 NXP\n+ *\n+ * This program is free software; you can redistribute it and/or modify\n+ * it under the terms of the GNU General Public License as published by\n+ * the Free Software Foundation; either version 2 of the License, or\n+ * (at your option) any later version.\n+ *\n+ * This program is distributed in the hope that it will be useful,\n+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\n+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n+ * GNU General Public License for more details.\n+ *\n+ * You should have received a copy of the GNU General Public License\n+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.\n+ */\n+\n+#ifndef _BMU_H_\n+#define _BMU_H_\n+\n+#define BMU_VERSION\t0x000\n+#define BMU_CTRL\t0x004\n+#define BMU_UCAST_CONFIG\t0x008\n+#define BMU_UCAST_BASE_ADDR\t0x00c\n+#define BMU_BUF_SIZE\t0x010\n+#define BMU_BUF_CNT\t0x014\n+#define BMU_THRES\t0x018\n+#define BMU_INT_SRC\t0x020\n+#define BMU_INT_ENABLE\t0x024\n+#define BMU_ALLOC_CTRL\t0x030\n+#define BMU_FREE_CTRL\t0x034\n+#define BMU_FREE_ERR_ADDR\t0x038\n+#define BMU_CURR_BUF_CNT\t0x03c\n+#define BMU_MCAST_CNT\t0x040\n+#define BMU_MCAST_ALLOC_CTRL\t0x044\n+#define BMU_REM_BUF_CNT\t0x048\n+#define BMU_LOW_WATERMARK\t0x050\n+#define BMU_HIGH_WATERMARK\t0x054\n+#define BMU_INT_MEM_ACCESS\t0x100\n+\n+struct BMU_CFG {\n+\tunsigned long baseaddr;\n+\tu32 count;\n+\tu32 size;\n+\tu32 low_watermark;\n+\tu32 high_watermark;\n+};\n+\n+#define BMU1_BUF_SIZE\tLMEM_BUF_SIZE_LN2\n+#define BMU2_BUF_SIZE\tDDR_BUF_SIZE_LN2\n+\n+#define BMU2_MCAST_ALLOC_CTRL\t(BMU2_BASE_ADDR + BMU_MCAST_ALLOC_CTRL)\n+\n+#endif /* _BMU_H_ */\n--- /dev/null\n+++ b/drivers/staging/fsl_ppfe/include/pfe/cbus/class_csr.h\n@@ -0,0 +1,289 @@\n+/*\n+ * Copyright 2015-2016 Freescale Semiconductor, Inc.\n+ * Copyright 2017 NXP\n+ *\n+ * This program is free software; you can redistribute it and/or modify\n+ * it under the terms of the GNU General Public License as published by\n+ * the Free Software Foundation; either version 2 of the License, or\n+ * (at your option) any later version.\n+ *\n+ * This program is distributed in the hope that it will be useful,\n+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\n+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n+ * GNU General Public License for more details.\n+ *\n+ * You should have received a copy of the GNU General Public License\n+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.\n+ */\n+\n+#ifndef _CLASS_CSR_H_\n+#define _CLASS_CSR_H_\n+\n+/* @file class_csr.h.\n+ * class_csr - block containing all the classifier control and status register.\n+ * Mapped on CBUS and accessible from all PE's and ARM.\n+ */\n+#define CLASS_VERSION\t(CLASS_CSR_BASE_ADDR + 0x000)\n+#define CLASS_TX_CTRL\t(CLASS_CSR_BASE_ADDR + 0x004)\n+#define CLASS_INQ_PKTPTR\t(CLASS_CSR_BASE_ADDR + 0x010)\n+\n+/* (ddr_hdr_size[24:16], lmem_hdr_size[5:0]) */\n+#define CLASS_HDR_SIZE\t(CLASS_CSR_BASE_ADDR + 0x014)\n+\n+/* LMEM header size for the Classifier block.\\ Data in the LMEM\n+ * is written from this offset.\n+ */\n+#define CLASS_HDR_SIZE_LMEM(off)\t((off) & 0x3f)\n+\n+/* DDR header size for the Classifier block.\\ Data in the DDR\n+ * is written from this offset.\n+ */\n+#define CLASS_HDR_SIZE_DDR(off)\t(((off) & 0x1ff) << 16)\n+\n+#define CLASS_PE0_QB_DM_ADDR0\t(CLASS_CSR_BASE_ADDR + 0x020)\n+\n+/* DMEM address of first [15:0] and second [31:16] buffers on QB side. */\n+#define CLASS_PE0_QB_DM_ADDR1\t(CLASS_CSR_BASE_ADDR + 0x024)\n+\n+/* DMEM address of third [15:0] and fourth [31:16] buffers on QB side. */\n+#define CLASS_PE0_RO_DM_ADDR0\t(CLASS_CSR_BASE_ADDR + 0x060)\n+\n+/* DMEM address of first [15:0] and second [31:16] buffers on RO side. */\n+#define CLASS_PE0_RO_DM_ADDR1\t(CLASS_CSR_BASE_ADDR + 0x064)\n+\n+/* DMEM address of third [15:0] and fourth [31:16] buffers on RO side. */\n+\n+/* @name Class PE memory access. Allows external PE's and HOST to\n+ * read/write PMEM/DMEM memory ranges for each classifier PE.\n+ */\n+/* {sr_pe_mem_cmd[31], csr_pe_mem_wren[27:24], csr_pe_mem_addr[23:0]},\n+ * See \\ref XXX_MEM_ACCESS_ADDR for details.\n+ */\n+#define CLASS_MEM_ACCESS_ADDR\t(CLASS_CSR_BASE_ADDR + 0x100)\n+\n+/* Internal Memory Access Write Data [31:0] */\n+#define CLASS_MEM_ACCESS_WDATA\t(CLASS_CSR_BASE_ADDR + 0x104)\n+\n+/* Internal Memory Access Read Data [31:0] */\n+#define CLASS_MEM_ACCESS_RDATA\t(CLASS_CSR_BASE_ADDR + 0x108)\n+#define CLASS_TM_INQ_ADDR\t(CLASS_CSR_BASE_ADDR + 0x114)\n+#define CLASS_PE_STATUS\t(CLASS_CSR_BASE_ADDR + 0x118)\n+\n+#define CLASS_PHY1_RX_PKTS\t(CLASS_CSR_BASE_ADDR + 0x11c)\n+#define CLASS_PHY1_TX_PKTS\t(CLASS_CSR_BASE_ADDR + 0x120)\n+#define CLASS_PHY1_LP_FAIL_PKTS\t(CLASS_CSR_BASE_ADDR + 0x124)\n+#define CLASS_PHY1_INTF_FAIL_PKTS\t(CLASS_CSR_BASE_ADDR + 0x128)\n+#define CLASS_PHY1_INTF_MATCH_PKTS\t(CLASS_CSR_BASE_ADDR + 0x12c)\n+#define CLASS_PHY1_L3_FAIL_PKTS\t(CLASS_CSR_BASE_ADDR + 0x130)\n+#define CLASS_PHY1_V4_PKTS\t(CLASS_CSR_BASE_ADDR + 0x134)\n+#define CLASS_PHY1_V6_PKTS\t(CLASS_CSR_BASE_ADDR + 0x138)\n+#define CLASS_PHY1_CHKSUM_ERR_PKTS\t(CLASS_CSR_BASE_ADDR + 0x13c)\n+#define CLASS_PHY1_TTL_ERR_PKTS\t(CLASS_CSR_BASE_ADDR + 0x140)\n+#define CLASS_PHY2_RX_PKTS\t(CLASS_CSR_BASE_ADDR + 0x144)\n+#define CLASS_PHY2_TX_PKTS\t(CLASS_CSR_BASE_ADDR + 0x148)\n+#define CLASS_PHY2_LP_FAIL_PKTS\t(CLASS_CSR_BASE_ADDR + 0x14c)\n+#define CLASS_PHY2_INTF_FAIL_PKTS\t(CLASS_CSR_BASE_ADDR + 0x150)\n+#define CLASS_PHY2_INTF_MATCH_PKTS\t(CLASS_CSR_BASE_ADDR + 0x154)\n+#define CLASS_PHY2_L3_FAIL_PKTS\t(CLASS_CSR_BASE_ADDR + 0x158)\n+#define CLASS_PHY2_V4_PKTS\t(CLASS_CSR_BASE_ADDR + 0x15c)\n+#define CLASS_PHY2_V6_PKTS\t(CLASS_CSR_BASE_ADDR + 0x160)\n+#define CLASS_PHY2_CHKSUM_ERR_PKTS\t(CLASS_CSR_BASE_ADDR + 0x164)\n+#define CLASS_PHY2_TTL_ERR_PKTS\t(CLASS_CSR_BASE_ADDR + 0x168)\n+#define CLASS_PHY3_RX_PKTS\t(CLASS_CSR_BASE_ADDR + 0x16c)\n+#define CLASS_PHY3_TX_PKTS\t(CLASS_CSR_BASE_ADDR + 0x170)\n+#define CLASS_PHY3_LP_FAIL_PKTS\t(CLASS_CSR_BASE_ADDR + 0x174)\n+#define CLASS_PHY3_INTF_FAIL_PKTS\t(CLASS_CSR_BASE_ADDR + 0x178)\n+#define CLASS_PHY3_INTF_MATCH_PKTS\t(CLASS_CSR_BASE_ADDR + 0x17c)\n+#define CLASS_PHY3_L3_FAIL_PKTS\t(CLASS_CSR_BASE_ADDR + 0x180)\n+#define CLASS_PHY3_V4_PKTS\t(CLASS_CSR_BASE_ADDR + 0x184)\n+#define CLASS_PHY3_V6_PKTS\t(CLASS_CSR_BASE_ADDR + 0x188)\n+#define CLASS_PHY3_CHKSUM_ERR_PKTS\t(CLASS_CSR_BASE_ADDR + 0x18c)\n+#define CLASS_PHY3_TTL_ERR_PKTS\t(CLASS_CSR_BASE_ADDR + 0x190)\n+#define CLASS_PHY1_ICMP_PKTS\t(CLASS_CSR_BASE_ADDR + 0x194)\n+#define CLASS_PHY1_IGMP_PKTS\t(CLASS_CSR_BASE_ADDR + 0x198)\n+#define CLASS_PHY1_TCP_PKTS\t(CLASS_CSR_BASE_ADDR + 0x19c)\n+#define CLASS_PHY1_UDP_PKTS\t(CLASS_CSR_BASE_ADDR + 0x1a0)\n+#define CLASS_PHY2_ICMP_PKTS\t(CLASS_CSR_BASE_ADDR + 0x1a4)\n+#define CLASS_PHY2_IGMP_PKTS\t(CLASS_CSR_BASE_ADDR + 0x1a8)\n+#define CLASS_PHY2_TCP_PKTS\t(CLASS_CSR_BASE_ADDR + 0x1ac)\n+#define CLASS_PHY2_UDP_PKTS\t(CLASS_CSR_BASE_ADDR + 0x1b0)\n+#define CLASS_PHY3_ICMP_PKTS\t(CLASS_CSR_BASE_ADDR + 0x1b4)\n+#define CLASS_PHY3_IGMP_PKTS\t(CLASS_CSR_BASE_ADDR + 0x1b8)\n+#define CLASS_PHY3_TCP_PKTS\t(CLASS_CSR_BASE_ADDR + 0x1bc)\n+#define CLASS_PHY3_UDP_PKTS\t(CLASS_CSR_BASE_ADDR + 0x1c0)\n+#define CLASS_PHY4_ICMP_PKTS\t(CLASS_CSR_BASE_ADDR + 0x1c4)\n+#define CLASS_PHY4_IGMP_PKTS\t(CLASS_CSR_BASE_ADDR + 0x1c8)\n+#define CLASS_PHY4_TCP_PKTS\t(CLASS_CSR_BASE_ADDR + 0x1cc)\n+#define CLASS_PHY4_UDP_PKTS\t(CLASS_CSR_BASE_ADDR + 0x1d0)\n+#define CLASS_PHY4_RX_PKTS\t(CLASS_CSR_BASE_ADDR + 0x1d4)\n+#define CLASS_PHY4_TX_PKTS\t(CLASS_CSR_BASE_ADDR + 0x1d8)\n+#define CLASS_PHY4_LP_FAIL_PKTS\t(CLASS_CSR_BASE_ADDR + 0x1dc)\n+#define CLASS_PHY4_INTF_FAIL_PKTS\t(CLASS_CSR_BASE_ADDR + 0x1e0)\n+#define CLASS_PHY4_INTF_MATCH_PKTS\t(CLASS_CSR_BASE_ADDR + 0x1e4)\n+#define CLASS_PHY4_L3_FAIL_PKTS\t(CLASS_CSR_BASE_ADDR + 0x1e8)\n+#define CLASS_PHY4_V4_PKTS\t(CLASS_CSR_BASE_ADDR + 0x1ec)\n+#define CLASS_PHY4_V6_PKTS\t(CLASS_CSR_BASE_ADDR + 0x1f0)\n+#define CLASS_PHY4_CHKSUM_ERR_PKTS\t(CLASS_CSR_BASE_ADDR + 0x1f4)\n+#define CLASS_PHY4_TTL_ERR_PKTS\t(CLASS_CSR_BASE_ADDR + 0x1f8)\n+\n+#define CLASS_PE_SYS_CLK_RATIO\t(CLASS_CSR_BASE_ADDR + 0x200)\n+#define CLASS_AFULL_THRES\t(CLASS_CSR_BASE_ADDR + 0x204)\n+#define CLASS_GAP_BETWEEN_READS\t(CLASS_CSR_BASE_ADDR + 0x208)\n+#define CLASS_MAX_BUF_CNT\t(CLASS_CSR_BASE_ADDR + 0x20c)\n+#define CLASS_TSQ_FIFO_THRES\t(CLASS_CSR_BASE_ADDR + 0x210)\n+#define CLASS_TSQ_MAX_CNT\t(CLASS_CSR_BASE_ADDR + 0x214)\n+#define CLASS_IRAM_DATA_0\t(CLASS_CSR_BASE_ADDR + 0x218)\n+#define CLASS_IRAM_DATA_1\t(CLASS_CSR_BASE_ADDR + 0x21c)\n+#define CLASS_IRAM_DATA_2\t(CLASS_CSR_BASE_ADDR + 0x220)\n+#define CLASS_IRAM_DATA_3\t(CLASS_CSR_BASE_ADDR + 0x224)\n+\n+#define CLASS_BUS_ACCESS_ADDR\t(CLASS_CSR_BASE_ADDR + 0x228)\n+\n+#define CLASS_BUS_ACCESS_WDATA\t(CLASS_CSR_BASE_ADDR + 0x22c)\n+#define CLASS_BUS_ACCESS_RDATA\t(CLASS_CSR_BASE_ADDR + 0x230)\n+\n+/* (route_entry_size[9:0], route_hash_size[23:16]\n+ * (this is actually ln2(size)))\n+ */\n+#define CLASS_ROUTE_HASH_ENTRY_SIZE\t(CLASS_CSR_BASE_ADDR + 0x234)\n+\n+#define CLASS_ROUTE_ENTRY_SIZE(size)\t ((size) & 0x1ff)\n+#define CLASS_ROUTE_HASH_SIZE(hash_bits) (((hash_bits) & 0xff) << 16)\n+\n+#define CLASS_ROUTE_TABLE_BASE\t(CLASS_CSR_BASE_ADDR + 0x238)\n+\n+#define CLASS_ROUTE_MULTI\t(CLASS_CSR_BASE_ADDR + 0x23c)\n+#define CLASS_SMEM_OFFSET\t(CLASS_CSR_BASE_ADDR + 0x240)\n+#define CLASS_LMEM_BUF_SIZE\t(CLASS_CSR_BASE_ADDR + 0x244)\n+#define CLASS_VLAN_ID\t(CLASS_CSR_BASE_ADDR + 0x248)\n+#define CLASS_BMU1_BUF_FREE\t(CLASS_CSR_BASE_ADDR + 0x24c)\n+#define CLASS_USE_TMU_INQ\t(CLASS_CSR_BASE_ADDR + 0x250)\n+#define CLASS_VLAN_ID1\t(CLASS_CSR_BASE_ADDR + 0x254)\n+\n+#define CLASS_BUS_ACCESS_BASE\t(CLASS_CSR_BASE_ADDR + 0x258)\n+#define CLASS_BUS_ACCESS_BASE_MASK\t(0xFF000000)\n+/* bit 31:24 of PE peripheral address are stored in CLASS_BUS_ACCESS_BASE */\n+\n+#define CLASS_HIF_PARSE\t(CLASS_CSR_BASE_ADDR + 0x25c)\n+\n+#define CLASS_HOST_PE0_GP\t(CLASS_CSR_BASE_ADDR + 0x260)\n+#define CLASS_PE0_GP\t(CLASS_CSR_BASE_ADDR + 0x264)\n+#define CLASS_HOST_PE1_GP\t(CLASS_CSR_BASE_ADDR + 0x268)\n+#define CLASS_PE1_GP\t(CLASS_CSR_BASE_ADDR + 0x26c)\n+#define CLASS_HOST_PE2_GP\t(CLASS_CSR_BASE_ADDR + 0x270)\n+#define CLASS_PE2_GP\t(CLASS_CSR_BASE_ADDR + 0x274)\n+#define CLASS_HOST_PE3_GP\t(CLASS_CSR_BASE_ADDR + 0x278)\n+#define CLASS_PE3_GP\t(CLASS_CSR_BASE_ADDR + 0x27c)\n+#define CLASS_HOST_PE4_GP\t(CLASS_CSR_BASE_ADDR + 0x280)\n+#define CLASS_PE4_GP\t(CLASS_CSR_BASE_ADDR + 0x284)\n+#define CLASS_HOST_PE5_GP\t(CLASS_CSR_BASE_ADDR + 0x288)\n+#define CLASS_PE5_GP\t(CLASS_CSR_BASE_ADDR + 0x28c)\n+\n+#define CLASS_PE_INT_SRC\t(CLASS_CSR_BASE_ADDR + 0x290)\n+#define CLASS_PE_INT_ENABLE\t(CLASS_CSR_BASE_ADDR + 0x294)\n+\n+#define CLASS_TPID0_TPID1\t(CLASS_CSR_BASE_ADDR + 0x298)\n+#define CLASS_TPID2\t(CLASS_CSR_BASE_ADDR + 0x29c)\n+\n+#define CLASS_L4_CHKSUM_ADDR\t(CLASS_CSR_BASE_ADDR + 0x2a0)\n+\n+#define CLASS_PE0_DEBUG\t(CLASS_CSR_BASE_ADDR + 0x2a4)\n+#define CLASS_PE1_DEBUG\t(CLASS_CSR_BASE_ADDR + 0x2a8)\n+#define CLASS_PE2_DEBUG\t(CLASS_CSR_BASE_ADDR + 0x2ac)\n+#define CLASS_PE3_DEBUG\t(CLASS_CSR_BASE_ADDR + 0x2b0)\n+#define CLASS_PE4_DEBUG\t(CLASS_CSR_BASE_ADDR + 0x2b4)\n+#define CLASS_PE5_DEBUG\t(CLASS_CSR_BASE_ADDR + 0x2b8)\n+\n+#define CLASS_STATE\t(CLASS_CSR_BASE_ADDR + 0x2bc)\n+\n+/* CLASS defines */\n+#define CLASS_PBUF_SIZE\t0x100\t/* Fixed by hardware */\n+#define CLASS_PBUF_HEADER_OFFSET\t0x80\t/* Can be configured */\n+\n+/* Can be configured */\n+#define CLASS_PBUF0_BASE_ADDR\t0x000\n+/* Can be configured */\n+#define CLASS_PBUF1_BASE_ADDR\t(CLASS_PBUF0_BASE_ADDR + CLASS_PBUF_SIZE)\n+/* Can be configured */\n+#define CLASS_PBUF2_BASE_ADDR\t(CLASS_PBUF1_BASE_ADDR + CLASS_PBUF_SIZE)\n+/* Can be configured */\n+#define CLASS_PBUF3_BASE_ADDR\t(CLASS_PBUF2_BASE_ADDR + CLASS_PBUF_SIZE)\n+\n+#define CLASS_PBUF0_HEADER_BASE_ADDR\t(CLASS_PBUF0_BASE_ADDR + \\\n+\t\t\t\t\t\tCLASS_PBUF_HEADER_OFFSET)\n+#define CLASS_PBUF1_HEADER_BASE_ADDR\t(CLASS_PBUF1_BASE_ADDR + \\\n+\t\t\t\t\t\tCLASS_PBUF_HEADER_OFFSET)\n+#define CLASS_PBUF2_HEADER_BASE_ADDR\t(CLASS_PBUF2_BASE_ADDR + \\\n+\t\t\t\t\t\tCLASS_PBUF_HEADER_OFFSET)\n+#define CLASS_PBUF3_HEADER_BASE_ADDR\t(CLASS_PBUF3_BASE_ADDR + \\\n+\t\t\t\t\t\tCLASS_PBUF_HEADER_OFFSET)\n+\n+#define CLASS_PE0_RO_DM_ADDR0_VAL\t((CLASS_PBUF1_BASE_ADDR << 16) | \\\n+\t\t\t\t\t\tCLASS_PBUF0_BASE_ADDR)\n+#define CLASS_PE0_RO_DM_ADDR1_VAL\t((CLASS_PBUF3_BASE_ADDR << 16) | \\\n+\t\t\t\t\t\tCLASS_PBUF2_BASE_ADDR)\n+\n+#define CLASS_PE0_QB_DM_ADDR0_VAL\t((CLASS_PBUF1_HEADER_BASE_ADDR << 16) |\\\n+\t\t\t\t\t\tCLASS_PBUF0_HEADER_BASE_ADDR)\n+#define CLASS_PE0_QB_DM_ADDR1_VAL\t((CLASS_PBUF3_HEADER_BASE_ADDR << 16) |\\\n+\t\t\t\t\t\tCLASS_PBUF2_HEADER_BASE_ADDR)\n+\n+#define CLASS_ROUTE_SIZE\t128\n+#define CLASS_MAX_ROUTE_SIZE\t256\n+#define CLASS_ROUTE_HASH_BITS\t20\n+#define CLASS_ROUTE_HASH_MASK\t(BIT(CLASS_ROUTE_HASH_BITS) - 1)\n+\n+/* Can be configured */\n+#define\tCLASS_ROUTE0_BASE_ADDR\t0x400\n+/* Can be configured */\n+#define CLASS_ROUTE1_BASE_ADDR\t(CLASS_ROUTE0_BASE_ADDR + CLASS_ROUTE_SIZE)\n+/* Can be configured */\n+#define CLASS_ROUTE2_BASE_ADDR\t(CLASS_ROUTE1_BASE_ADDR + CLASS_ROUTE_SIZE)\n+/* Can be configured */\n+#define CLASS_ROUTE3_BASE_ADDR\t(CLASS_ROUTE2_BASE_ADDR + CLASS_ROUTE_SIZE)\n+\n+#define CLASS_SA_SIZE\t128\n+#define CLASS_IPSEC_SA0_BASE_ADDR\t0x600\n+/* not used */\n+#define CLASS_IPSEC_SA1_BASE_ADDR  (CLASS_IPSEC_SA0_BASE_ADDR + CLASS_SA_SIZE)\n+/* not used */\n+#define CLASS_IPSEC_SA2_BASE_ADDR  (CLASS_IPSEC_SA1_BASE_ADDR + CLASS_SA_SIZE)\n+/* not used */\n+#define CLASS_IPSEC_SA3_BASE_ADDR  (CLASS_IPSEC_SA2_BASE_ADDR + CLASS_SA_SIZE)\n+\n+/* generic purpose free dmem buffer, last portion of 2K dmem pbuf */\n+#define CLASS_GP_DMEM_BUF_SIZE\t(2048 - (CLASS_PBUF_SIZE * 4) - \\\n+\t\t\t\t(CLASS_ROUTE_SIZE * 4) - (CLASS_SA_SIZE))\n+#define CLASS_GP_DMEM_BUF\t((void *)(CLASS_IPSEC_SA0_BASE_ADDR + \\\n+\t\t\t\t\tCLASS_SA_SIZE))\n+\n+#define TWO_LEVEL_ROUTE\t\tBIT(0)\n+#define PHYNO_IN_HASH\t\tBIT(1)\n+#define HW_ROUTE_FETCH\t\tBIT(3)\n+#define HW_BRIDGE_FETCH\t\tBIT(5)\n+#define IP_ALIGNED\t\tBIT(6)\n+#define ARC_HIT_CHECK_EN\tBIT(7)\n+#define CLASS_TOE\t\tBIT(11)\n+#define HASH_NORMAL\t\t(0 << 12)\n+#define HASH_CRC_PORT\t\tBIT(12)\n+#define HASH_CRC_IP\t\t(2 << 12)\n+#define HASH_CRC_PORT_IP\t(3 << 12)\n+#define QB2BUS_LE\t\tBIT(15)\n+\n+#define TCP_CHKSUM_DROP\t\tBIT(0)\n+#define UDP_CHKSUM_DROP\t\tBIT(1)\n+#define IPV4_CHKSUM_DROP\tBIT(9)\n+\n+/*CLASS_HIF_PARSE bits*/\n+#define HIF_PKT_CLASS_EN\tBIT(0)\n+#define HIF_PKT_OFFSET(ofst)\t(((ofst) & 0xF) << 1)\n+\n+struct class_cfg {\n+\tu32 toe_mode;\n+\tunsigned long route_table_baseaddr;\n+\tu32 route_table_hash_bits;\n+\tu32 pe_sys_clk_ratio;\n+\tu32 resume;\n+};\n+\n+#endif /* _CLASS_CSR_H_ */\n--- /dev/null\n+++ b/drivers/staging/fsl_ppfe/include/pfe/cbus/emac_mtip.h\n@@ -0,0 +1,242 @@\n+/*\n+ * Copyright 2015-2016 Freescale Semiconductor, Inc.\n+ * Copyright 2017 NXP\n+ *\n+ * This program is free software; you can redistribute it and/or modify\n+ * it under the terms of the GNU General Public License as published by\n+ * the Free Software Foundation; either version 2 of the License, or\n+ * (at your option) any later version.\n+ *\n+ * This program is distributed in the hope that it will be useful,\n+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\n+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n+ * GNU General Public License for more details.\n+ *\n+ * You should have received a copy of the GNU General Public License\n+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.\n+ */\n+\n+#ifndef _EMAC_H_\n+#define _EMAC_H_\n+\n+#include <linux/ethtool.h>\n+\n+#define EMAC_IEVENT_REG\t\t0x004\n+#define EMAC_IMASK_REG\t\t0x008\n+#define EMAC_R_DES_ACTIVE_REG\t0x010\n+#define EMAC_X_DES_ACTIVE_REG\t0x014\n+#define EMAC_ECNTRL_REG\t\t0x024\n+#define EMAC_MII_DATA_REG\t0x040\n+#define EMAC_MII_CTRL_REG\t0x044\n+#define EMAC_MIB_CTRL_STS_REG\t0x064\n+#define EMAC_RCNTRL_REG\t\t0x084\n+#define EMAC_TCNTRL_REG\t\t0x0C4\n+#define EMAC_PHY_ADDR_LOW\t0x0E4\n+#define EMAC_PHY_ADDR_HIGH\t0x0E8\n+#define EMAC_GAUR\t\t0x120\n+#define EMAC_GALR\t\t0x124\n+#define EMAC_TFWR_STR_FWD\t0x144\n+#define EMAC_RX_SECTION_FULL\t0x190\n+#define EMAC_RX_SECTION_EMPTY\t0x194\n+#define EMAC_TX_SECTION_EMPTY\t0x1A0\n+#define EMAC_TRUNC_FL\t\t0x1B0\n+\n+#define RMON_T_DROP\t0x200 /* Count of frames not cntd correctly */\n+#define RMON_T_PACKETS\t0x204 /* RMON TX packet count */\n+#define RMON_T_BC_PKT\t0x208 /* RMON TX broadcast pkts */\n+#define RMON_T_MC_PKT\t0x20c /* RMON TX multicast pkts */\n+#define RMON_T_CRC_ALIGN\t0x210 /* RMON TX pkts with CRC align err */\n+#define RMON_T_UNDERSIZE\t0x214 /* RMON TX pkts < 64 bytes, good CRC */\n+#define RMON_T_OVERSIZE\t0x218 /* RMON TX pkts > MAX_FL bytes good CRC */\n+#define RMON_T_FRAG\t0x21c /* RMON TX pkts < 64 bytes, bad CRC */\n+#define RMON_T_JAB\t0x220 /* RMON TX pkts > MAX_FL bytes, bad CRC */\n+#define RMON_T_COL\t0x224 /* RMON TX collision count */\n+#define RMON_T_P64\t0x228 /* RMON TX 64 byte pkts */\n+#define RMON_T_P65TO127\t0x22c /* RMON TX 65 to 127 byte pkts */\n+#define RMON_T_P128TO255\t0x230 /* RMON TX 128 to 255 byte pkts */\n+#define RMON_T_P256TO511\t0x234 /* RMON TX 256 to 511 byte pkts */\n+#define RMON_T_P512TO1023\t0x238 /* RMON TX 512 to 1023 byte pkts */\n+#define RMON_T_P1024TO2047\t0x23c /* RMON TX 1024 to 2047 byte pkts */\n+#define RMON_T_P_GTE2048\t0x240 /* RMON TX pkts > 2048 bytes */\n+#define RMON_T_OCTETS\t0x244 /* RMON TX octets */\n+#define IEEE_T_DROP\t0x248 /* Count of frames not counted crtly */\n+#define IEEE_T_FRAME_OK\t0x24c /* Frames tx'd OK */\n+#define IEEE_T_1COL\t0x250 /* Frames tx'd with single collision */\n+#define IEEE_T_MCOL\t0x254 /* Frames tx'd with multiple collision */\n+#define IEEE_T_DEF\t0x258 /* Frames tx'd after deferral delay */\n+#define IEEE_T_LCOL\t0x25c /* Frames tx'd with late collision */\n+#define IEEE_T_EXCOL\t0x260 /* Frames tx'd with excesv collisions */\n+#define IEEE_T_MACERR\t0x264 /* Frames tx'd with TX FIFO underrun */\n+#define IEEE_T_CSERR\t0x268 /* Frames tx'd with carrier sense err */\n+#define IEEE_T_SQE\t0x26c /* Frames tx'd with SQE err */\n+#define IEEE_T_FDXFC\t0x270 /* Flow control pause frames tx'd */\n+#define IEEE_T_OCTETS_OK\t0x274 /* Octet count for frames tx'd w/o err */\n+#define RMON_R_PACKETS\t0x284 /* RMON RX packet count */\n+#define RMON_R_BC_PKT\t0x288 /* RMON RX broadcast pkts */\n+#define RMON_R_MC_PKT\t0x28c /* RMON RX multicast pkts */\n+#define RMON_R_CRC_ALIGN\t0x290 /* RMON RX pkts with CRC alignment err */\n+#define RMON_R_UNDERSIZE\t0x294 /* RMON RX pkts < 64 bytes, good CRC */\n+#define RMON_R_OVERSIZE\t0x298 /* RMON RX pkts > MAX_FL bytes good CRC */\n+#define RMON_R_FRAG\t0x29c /* RMON RX pkts < 64 bytes, bad CRC */\n+#define RMON_R_JAB\t0x2a0 /* RMON RX pkts > MAX_FL bytes, bad CRC */\n+#define RMON_R_RESVD_O\t0x2a4 /* Reserved */\n+#define RMON_R_P64\t0x2a8 /* RMON RX 64 byte pkts */\n+#define RMON_R_P65TO127\t0x2ac /* RMON RX 65 to 127 byte pkts */\n+#define RMON_R_P128TO255\t0x2b0 /* RMON RX 128 to 255 byte pkts */\n+#define RMON_R_P256TO511\t0x2b4 /* RMON RX 256 to 511 byte pkts */\n+#define RMON_R_P512TO1023\t0x2b8 /* RMON RX 512 to 1023 byte pkts */\n+#define RMON_R_P1024TO2047\t0x2bc /* RMON RX 1024 to 2047 byte pkts */\n+#define RMON_R_P_GTE2048\t0x2c0 /* RMON RX pkts > 2048 bytes */\n+#define RMON_R_OCTETS\t0x2c4 /* RMON RX octets */\n+#define IEEE_R_DROP\t0x2c8 /* Count frames not counted correctly */\n+#define IEEE_R_FRAME_OK\t0x2cc /* Frames rx'd OK */\n+#define IEEE_R_CRC\t0x2d0 /* Frames rx'd with CRC err */\n+#define IEEE_R_ALIGN\t0x2d4 /* Frames rx'd with alignment err */\n+#define IEEE_R_MACERR\t0x2d8 /* Receive FIFO overflow count */\n+#define IEEE_R_FDXFC\t0x2dc /* Flow control pause frames rx'd */\n+#define IEEE_R_OCTETS_OK\t0x2e0 /* Octet cnt for frames rx'd w/o err */\n+\n+#define EMAC_SMAC_0_0\t0x500 /*Supplemental MAC Address 0 (RW).*/\n+#define EMAC_SMAC_0_1\t0x504 /*Supplemental MAC Address 0 (RW).*/\n+\n+/* GEMAC definitions and settings */\n+\n+#define EMAC_PORT_0\t0\n+#define EMAC_PORT_1\t1\n+\n+/* GEMAC Bit definitions */\n+#define EMAC_IEVENT_HBERR\t\t 0x80000000\n+#define EMAC_IEVENT_BABR\t\t 0x40000000\n+#define EMAC_IEVENT_BABT\t\t 0x20000000\n+#define EMAC_IEVENT_GRA\t\t\t 0x10000000\n+#define EMAC_IEVENT_TXF\t\t\t 0x08000000\n+#define EMAC_IEVENT_TXB\t\t\t 0x04000000\n+#define EMAC_IEVENT_RXF\t\t\t 0x02000000\n+#define EMAC_IEVENT_RXB\t\t\t 0x01000000\n+#define EMAC_IEVENT_MII\t\t\t 0x00800000\n+#define EMAC_IEVENT_EBERR\t\t 0x00400000\n+#define EMAC_IEVENT_LC\t\t\t 0x00200000\n+#define EMAC_IEVENT_RL\t\t\t 0x00100000\n+#define EMAC_IEVENT_UN\t\t\t 0x00080000\n+\n+#define EMAC_IMASK_HBERR                 0x80000000\n+#define EMAC_IMASK_BABR                  0x40000000\n+#define EMAC_IMASKT_BABT                 0x20000000\n+#define EMAC_IMASK_GRA                   0x10000000\n+#define EMAC_IMASKT_TXF                  0x08000000\n+#define EMAC_IMASK_TXB                   0x04000000\n+#define EMAC_IMASKT_RXF                  0x02000000\n+#define EMAC_IMASK_RXB                   0x01000000\n+#define EMAC_IMASK_MII                   0x00800000\n+#define EMAC_IMASK_EBERR                 0x00400000\n+#define EMAC_IMASK_LC                    0x00200000\n+#define EMAC_IMASKT_RL                   0x00100000\n+#define EMAC_IMASK_UN                    0x00080000\n+\n+#define EMAC_RCNTRL_MAX_FL_SHIFT         16\n+#define EMAC_RCNTRL_LOOP                 0x00000001\n+#define EMAC_RCNTRL_DRT                  0x00000002\n+#define EMAC_RCNTRL_MII_MODE             0x00000004\n+#define EMAC_RCNTRL_PROM                 0x00000008\n+#define EMAC_RCNTRL_BC_REJ               0x00000010\n+#define EMAC_RCNTRL_FCE                  0x00000020\n+#define EMAC_RCNTRL_RGMII                0x00000040\n+#define EMAC_RCNTRL_SGMII                0x00000080\n+#define EMAC_RCNTRL_RMII                 0x00000100\n+#define EMAC_RCNTRL_RMII_10T             0x00000200\n+#define EMAC_RCNTRL_CRC_FWD\t\t 0x00004000\n+\n+#define EMAC_TCNTRL_GTS                  0x00000001\n+#define EMAC_TCNTRL_HBC                  0x00000002\n+#define EMAC_TCNTRL_FDEN                 0x00000004\n+#define EMAC_TCNTRL_TFC_PAUSE            0x00000008\n+#define EMAC_TCNTRL_RFC_PAUSE            0x00000010\n+\n+#define EMAC_ECNTRL_RESET                0x00000001      /* reset the EMAC */\n+#define EMAC_ECNTRL_ETHER_EN             0x00000002      /* enable the EMAC */\n+#define EMAC_ECNTRL_MAGIC_ENA\t\t 0x00000004\n+#define EMAC_ECNTRL_SLEEP\t\t 0x00000008\n+#define EMAC_ECNTRL_SPEED                0x00000020\n+#define EMAC_ECNTRL_DBSWAP               0x00000100\n+\n+#define EMAC_X_WMRK_STRFWD               0x00000100\n+\n+#define EMAC_X_DES_ACTIVE_TDAR           0x01000000\n+#define EMAC_R_DES_ACTIVE_RDAR           0x01000000\n+\n+#define EMAC_RX_SECTION_EMPTY_V\t\t0x00010006\n+/*\n+ * The possible operating speeds of the MAC, currently supporting 10, 100 and\n+ * 1000Mb modes.\n+ */\n+enum mac_speed {SPEED_10M, SPEED_100M, SPEED_1000M, SPEED_1000M_PCS};\n+\n+/* MII-related definitios */\n+#define EMAC_MII_DATA_ST         0x40000000      /* Start of frame delimiter */\n+#define EMAC_MII_DATA_OP_RD      0x20000000      /* Perform a read operation */\n+#define EMAC_MII_DATA_OP_CL45_RD 0x30000000      /* Perform a read operation */\n+#define EMAC_MII_DATA_OP_WR      0x10000000      /* Perform a write operation */\n+#define EMAC_MII_DATA_OP_CL45_WR 0x10000000      /* Perform a write operation */\n+#define EMAC_MII_DATA_PA_MSK     0x0f800000      /* PHY Address field mask */\n+#define EMAC_MII_DATA_RA_MSK     0x007c0000      /* PHY Register field mask */\n+#define EMAC_MII_DATA_TA         0x00020000      /* Turnaround */\n+#define EMAC_MII_DATA_DATAMSK    0x0000ffff      /* PHY data field */\n+\n+#define EMAC_MII_DATA_RA_SHIFT   18      /* MII Register address bits */\n+#define EMAC_MII_DATA_RA_MASK\t 0x1F      /* MII Register address mask */\n+#define EMAC_MII_DATA_PA_SHIFT   23      /* MII PHY address bits */\n+#define EMAC_MII_DATA_PA_MASK    0x1F      /* MII PHY address mask */\n+\n+#define EMAC_MII_DATA_RA(v) (((v) & EMAC_MII_DATA_RA_MASK) << \\\n+\t\t\t\tEMAC_MII_DATA_RA_SHIFT)\n+#define EMAC_MII_DATA_PA(v) (((v) & EMAC_MII_DATA_RA_MASK) << \\\n+\t\t\t\tEMAC_MII_DATA_PA_SHIFT)\n+#define EMAC_MII_DATA(v)    ((v) & 0xffff)\n+\n+#define EMAC_MII_SPEED_SHIFT\t1\n+#define EMAC_HOLDTIME_SHIFT\t8\n+#define EMAC_HOLDTIME_MASK\t0x7\n+#define EMAC_HOLDTIME(v)\t(((v) & EMAC_HOLDTIME_MASK) << \\\n+\t\t\t\t\tEMAC_HOLDTIME_SHIFT)\n+\n+/*\n+ * The Address organisation for the MAC device.  All addresses are split into\n+ * two 32-bit register fields.  The first one (bottom) is the lower 32-bits of\n+ * the address and the other field are the high order bits - this may be 16-bits\n+ * in the case of MAC addresses, or 32-bits for the hash address.\n+ * In terms of memory storage, the first item (bottom) is assumed to be at a\n+ * lower address location than 'top'. i.e. top should be at address location of\n+ * 'bottom' + 4 bytes.\n+ */\n+struct pfe_mac_addr {\n+\tu32 bottom;     /* Lower 32-bits of address. */\n+\tu32 top;        /* Upper 32-bits of address. */\n+};\n+\n+/*\n+ * The following is the organisation of the address filters section of the MAC\n+ * registers.  The Cadence MAC contains four possible specific address match\n+ * addresses, if an incoming frame corresponds to any one of these four\n+ * addresses then the frame will be copied to memory.\n+ * It is not necessary for all four of the address match registers to be\n+ * programmed, this is application dependent.\n+ */\n+struct spec_addr {\n+\tstruct pfe_mac_addr one;        /* Specific address register 1. */\n+\tstruct pfe_mac_addr two;        /* Specific address register 2. */\n+\tstruct pfe_mac_addr three;      /* Specific address register 3. */\n+\tstruct pfe_mac_addr four;       /* Specific address register 4. */\n+};\n+\n+struct gemac_cfg {\n+\tu32 mode;\n+\tu32 speed;\n+\tu32 duplex;\n+};\n+\n+/* EMAC Hash size */\n+#define EMAC_HASH_REG_BITS       64\n+\n+#define EMAC_SPEC_ADDR_MAX\t4\n+\n+#endif /* _EMAC_H_ */\n--- /dev/null\n+++ b/drivers/staging/fsl_ppfe/include/pfe/cbus/gpi.h\n@@ -0,0 +1,86 @@\n+/*\n+ * Copyright 2015-2016 Freescale Semiconductor, Inc.\n+ * Copyright 2017 NXP\n+ *\n+ * This program is free software; you can redistribute it and/or modify\n+ * it under the terms of the GNU General Public License as published by\n+ * the Free Software Foundation; either version 2 of the License, or\n+ * (at your option) any later version.\n+ *\n+ * This program is distributed in the hope that it will be useful,\n+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\n+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n+ * GNU General Public License for more details.\n+ *\n+ * You should have received a copy of the GNU General Public License\n+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.\n+ */\n+\n+#ifndef _GPI_H_\n+#define _GPI_H_\n+\n+#define GPI_VERSION\t0x00\n+#define GPI_CTRL\t0x04\n+#define GPI_RX_CONFIG\t0x08\n+#define GPI_HDR_SIZE\t0x0c\n+#define GPI_BUF_SIZE\t0x10\n+#define GPI_LMEM_ALLOC_ADDR\t0x14\n+#define GPI_LMEM_FREE_ADDR\t0x18\n+#define GPI_DDR_ALLOC_ADDR\t0x1c\n+#define GPI_DDR_FREE_ADDR\t0x20\n+#define GPI_CLASS_ADDR\t0x24\n+#define GPI_DRX_FIFO\t0x28\n+#define GPI_TRX_FIFO\t0x2c\n+#define GPI_INQ_PKTPTR\t0x30\n+#define GPI_DDR_DATA_OFFSET\t0x34\n+#define GPI_LMEM_DATA_OFFSET\t0x38\n+#define GPI_TMLF_TX\t0x4c\n+#define GPI_DTX_ASEQ\t0x50\n+#define GPI_FIFO_STATUS\t0x54\n+#define GPI_FIFO_DEBUG\t0x58\n+#define GPI_TX_PAUSE_TIME\t0x5c\n+#define GPI_LMEM_SEC_BUF_DATA_OFFSET\t0x60\n+#define GPI_DDR_SEC_BUF_DATA_OFFSET\t0x64\n+#define GPI_TOE_CHKSUM_EN\t0x68\n+#define GPI_OVERRUN_DROPCNT\t0x6c\n+#define GPI_CSR_MTIP_PAUSE_REG\t\t0x74\n+#define GPI_CSR_MTIP_PAUSE_QUANTUM\t0x78\n+#define GPI_CSR_RX_CNT\t\t\t0x7c\n+#define GPI_CSR_TX_CNT\t\t\t0x80\n+#define GPI_CSR_DEBUG1\t\t\t0x84\n+#define GPI_CSR_DEBUG2\t\t\t0x88\n+\n+struct gpi_cfg {\n+\tu32 lmem_rtry_cnt;\n+\tu32 tmlf_txthres;\n+\tu32 aseq_len;\n+\tu32 mtip_pause_reg;\n+};\n+\n+/* GPI commons defines */\n+#define GPI_LMEM_BUF_EN\t0x1\n+#define GPI_DDR_BUF_EN\t0x1\n+\n+/* EGPI 1 defines */\n+#define EGPI1_LMEM_RTRY_CNT\t0x40\n+#define EGPI1_TMLF_TXTHRES\t0xBC\n+#define EGPI1_ASEQ_LEN\t0x50\n+\n+/* EGPI 2 defines */\n+#define EGPI2_LMEM_RTRY_CNT\t0x40\n+#define EGPI2_TMLF_TXTHRES\t0xBC\n+#define EGPI2_ASEQ_LEN\t0x40\n+\n+/* EGPI 3 defines */\n+#define EGPI3_LMEM_RTRY_CNT\t0x40\n+#define EGPI3_TMLF_TXTHRES\t0xBC\n+#define EGPI3_ASEQ_LEN\t0x40\n+\n+/* HGPI defines */\n+#define HGPI_LMEM_RTRY_CNT\t0x40\n+#define HGPI_TMLF_TXTHRES\t0xBC\n+#define HGPI_ASEQ_LEN\t0x40\n+\n+#define EGPI_PAUSE_TIME\t\t0x000007D0\n+#define EGPI_PAUSE_ENABLE\t0x40000000\n+#endif /* _GPI_H_ */\n--- /dev/null\n+++ b/drivers/staging/fsl_ppfe/include/pfe/cbus/hif.h\n@@ -0,0 +1,100 @@\n+/*\n+ * Copyright 2015-2016 Freescale Semiconductor, Inc.\n+ * Copyright 2017 NXP\n+ *\n+ * This program is free software; you can redistribute it and/or modify\n+ * it under the terms of the GNU General Public License as published by\n+ * the Free Software Foundation; either version 2 of the License, or\n+ * (at your option) any later version.\n+ *\n+ * This program is distributed in the hope that it will be useful,\n+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\n+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n+ * GNU General Public License for more details.\n+ *\n+ * You should have received a copy of the GNU General Public License\n+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.\n+ */\n+\n+#ifndef _HIF_H_\n+#define _HIF_H_\n+\n+/* @file hif.h.\n+ * hif - PFE hif block control and status register.\n+ * Mapped on CBUS and accessible from all PE's and ARM.\n+ */\n+#define HIF_VERSION\t(HIF_BASE_ADDR + 0x00)\n+#define HIF_TX_CTRL\t(HIF_BASE_ADDR + 0x04)\n+#define HIF_TX_CURR_BD_ADDR\t(HIF_BASE_ADDR + 0x08)\n+#define HIF_TX_ALLOC\t(HIF_BASE_ADDR + 0x0c)\n+#define HIF_TX_BDP_ADDR\t(HIF_BASE_ADDR + 0x10)\n+#define HIF_TX_STATUS\t(HIF_BASE_ADDR + 0x14)\n+#define HIF_RX_CTRL\t(HIF_BASE_ADDR + 0x20)\n+#define HIF_RX_BDP_ADDR\t(HIF_BASE_ADDR + 0x24)\n+#define HIF_RX_STATUS\t(HIF_BASE_ADDR + 0x30)\n+#define HIF_INT_SRC\t(HIF_BASE_ADDR + 0x34)\n+#define HIF_INT_ENABLE\t(HIF_BASE_ADDR + 0x38)\n+#define HIF_POLL_CTRL\t(HIF_BASE_ADDR + 0x3c)\n+#define HIF_RX_CURR_BD_ADDR\t(HIF_BASE_ADDR + 0x40)\n+#define HIF_RX_ALLOC\t(HIF_BASE_ADDR + 0x44)\n+#define HIF_TX_DMA_STATUS\t(HIF_BASE_ADDR + 0x48)\n+#define HIF_RX_DMA_STATUS\t(HIF_BASE_ADDR + 0x4c)\n+#define HIF_INT_COAL\t(HIF_BASE_ADDR + 0x50)\n+\n+/* HIF_INT_SRC/ HIF_INT_ENABLE control bits */\n+#define HIF_INT\t\tBIT(0)\n+#define HIF_RXBD_INT\tBIT(1)\n+#define HIF_RXPKT_INT\tBIT(2)\n+#define HIF_TXBD_INT\tBIT(3)\n+#define HIF_TXPKT_INT\tBIT(4)\n+\n+/* HIF_TX_CTRL bits */\n+#define HIF_CTRL_DMA_EN\t\t\tBIT(0)\n+#define HIF_CTRL_BDP_POLL_CTRL_EN\tBIT(1)\n+#define HIF_CTRL_BDP_CH_START_WSTB\tBIT(2)\n+\n+/* HIF_RX_STATUS bits */\n+#define BDP_CSR_RX_DMA_ACTV     BIT(16)\n+\n+/* HIF_INT_ENABLE bits */\n+#define HIF_INT_EN\t\tBIT(0)\n+#define HIF_RXBD_INT_EN\t\tBIT(1)\n+#define HIF_RXPKT_INT_EN\tBIT(2)\n+#define HIF_TXBD_INT_EN\t\tBIT(3)\n+#define HIF_TXPKT_INT_EN\tBIT(4)\n+\n+/* HIF_POLL_CTRL bits*/\n+#define HIF_RX_POLL_CTRL_CYCLE\t0x0400\n+#define HIF_TX_POLL_CTRL_CYCLE\t0x0400\n+\n+/* HIF_INT_COAL bits*/\n+#define HIF_INT_COAL_ENABLE\tBIT(31)\n+\n+/* Buffer descriptor control bits */\n+#define BD_CTRL_BUFLEN_MASK\t0x3fff\n+#define BD_BUF_LEN(x)\t((x) & BD_CTRL_BUFLEN_MASK)\n+#define BD_CTRL_CBD_INT_EN\tBIT(16)\n+#define BD_CTRL_PKT_INT_EN\tBIT(17)\n+#define BD_CTRL_LIFM\t\tBIT(18)\n+#define BD_CTRL_LAST_BD\t\tBIT(19)\n+#define BD_CTRL_DIR\t\tBIT(20)\n+#define BD_CTRL_LMEM_CPY\tBIT(21) /* Valid only for HIF_NOCPY */\n+#define BD_CTRL_PKT_XFER\tBIT(24)\n+#define BD_CTRL_DESC_EN\t\tBIT(31)\n+#define BD_CTRL_PARSE_DISABLE\tBIT(25)\n+#define BD_CTRL_BRFETCH_DISABLE\tBIT(26)\n+#define BD_CTRL_RTFETCH_DISABLE\tBIT(27)\n+\n+/* Buffer descriptor status bits*/\n+#define BD_STATUS_CONN_ID(x)\t((x) & 0xffff)\n+#define BD_STATUS_DIR_PROC_ID\tBIT(16)\n+#define BD_STATUS_CONN_ID_EN\tBIT(17)\n+#define BD_STATUS_PE2PROC_ID(x)\t(((x) & 7) << 18)\n+#define BD_STATUS_LE_DATA\tBIT(21)\n+#define BD_STATUS_CHKSUM_EN\tBIT(22)\n+\n+/* HIF Buffer descriptor status bits */\n+#define DIR_PROC_ID\tBIT(16)\n+#define PROC_ID(id)\t((id) << 18)\n+\n+#endif /* _HIF_H_ */\n--- /dev/null\n+++ b/drivers/staging/fsl_ppfe/include/pfe/cbus/hif_nocpy.h\n@@ -0,0 +1,50 @@\n+/*\n+ * Copyright 2015-2016 Freescale Semiconductor, Inc.\n+ * Copyright 2017 NXP\n+ *\n+ * This program is free software; you can redistribute it and/or modify\n+ * it under the terms of the GNU General Public License as published by\n+ * the Free Software Foundation; either version 2 of the License, or\n+ * (at your option) any later version.\n+ *\n+ * This program is distributed in the hope that it will be useful,\n+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\n+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n+ * GNU General Public License for more details.\n+ *\n+ * You should have received a copy of the GNU General Public License\n+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.\n+ */\n+\n+#ifndef _HIF_NOCPY_H_\n+#define _HIF_NOCPY_H_\n+\n+#define HIF_NOCPY_VERSION\t(HIF_NOCPY_BASE_ADDR + 0x00)\n+#define HIF_NOCPY_TX_CTRL\t(HIF_NOCPY_BASE_ADDR + 0x04)\n+#define HIF_NOCPY_TX_CURR_BD_ADDR\t(HIF_NOCPY_BASE_ADDR + 0x08)\n+#define HIF_NOCPY_TX_ALLOC\t(HIF_NOCPY_BASE_ADDR + 0x0c)\n+#define HIF_NOCPY_TX_BDP_ADDR\t(HIF_NOCPY_BASE_ADDR + 0x10)\n+#define HIF_NOCPY_TX_STATUS\t(HIF_NOCPY_BASE_ADDR + 0x14)\n+#define HIF_NOCPY_RX_CTRL\t(HIF_NOCPY_BASE_ADDR + 0x20)\n+#define HIF_NOCPY_RX_BDP_ADDR\t(HIF_NOCPY_BASE_ADDR + 0x24)\n+#define HIF_NOCPY_RX_STATUS\t(HIF_NOCPY_BASE_ADDR + 0x30)\n+#define HIF_NOCPY_INT_SRC\t(HIF_NOCPY_BASE_ADDR + 0x34)\n+#define HIF_NOCPY_INT_ENABLE\t(HIF_NOCPY_BASE_ADDR + 0x38)\n+#define HIF_NOCPY_POLL_CTRL\t(HIF_NOCPY_BASE_ADDR + 0x3c)\n+#define HIF_NOCPY_RX_CURR_BD_ADDR\t(HIF_NOCPY_BASE_ADDR + 0x40)\n+#define HIF_NOCPY_RX_ALLOC\t(HIF_NOCPY_BASE_ADDR + 0x44)\n+#define HIF_NOCPY_TX_DMA_STATUS\t(HIF_NOCPY_BASE_ADDR + 0x48)\n+#define HIF_NOCPY_RX_DMA_STATUS\t(HIF_NOCPY_BASE_ADDR + 0x4c)\n+#define HIF_NOCPY_RX_INQ0_PKTPTR\t(HIF_NOCPY_BASE_ADDR + 0x50)\n+#define HIF_NOCPY_RX_INQ1_PKTPTR\t(HIF_NOCPY_BASE_ADDR + 0x54)\n+#define HIF_NOCPY_TX_PORT_NO\t(HIF_NOCPY_BASE_ADDR + 0x60)\n+#define HIF_NOCPY_LMEM_ALLOC_ADDR\t(HIF_NOCPY_BASE_ADDR + 0x64)\n+#define HIF_NOCPY_CLASS_ADDR\t(HIF_NOCPY_BASE_ADDR + 0x68)\n+#define HIF_NOCPY_TMU_PORT0_ADDR\t(HIF_NOCPY_BASE_ADDR + 0x70)\n+#define HIF_NOCPY_TMU_PORT1_ADDR\t(HIF_NOCPY_BASE_ADDR + 0x74)\n+#define HIF_NOCPY_TMU_PORT2_ADDR\t(HIF_NOCPY_BASE_ADDR + 0x7c)\n+#define HIF_NOCPY_TMU_PORT3_ADDR\t(HIF_NOCPY_BASE_ADDR + 0x80)\n+#define HIF_NOCPY_TMU_PORT4_ADDR\t(HIF_NOCPY_BASE_ADDR + 0x84)\n+#define HIF_NOCPY_INT_COAL\t(HIF_NOCPY_BASE_ADDR + 0x90)\n+\n+#endif /* _HIF_NOCPY_H_ */\n--- /dev/null\n+++ b/drivers/staging/fsl_ppfe/include/pfe/cbus/tmu_csr.h\n@@ -0,0 +1,168 @@\n+/*\n+ * Copyright 2015-2016 Freescale Semiconductor, Inc.\n+ * Copyright 2017 NXP\n+ *\n+ * This program is free software; you can redistribute it and/or modify\n+ * it under the terms of the GNU General Public License as published by\n+ * the Free Software Foundation; either version 2 of the License, or\n+ * (at your option) any later version.\n+ *\n+ * This program is distributed in the hope that it will be useful,\n+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\n+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n+ * GNU General Public License for more details.\n+ *\n+ * You should have received a copy of the GNU General Public License\n+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.\n+ */\n+\n+#ifndef _TMU_CSR_H_\n+#define _TMU_CSR_H_\n+\n+#define TMU_VERSION\t(TMU_CSR_BASE_ADDR + 0x000)\n+#define TMU_INQ_WATERMARK\t(TMU_CSR_BASE_ADDR + 0x004)\n+#define TMU_PHY_INQ_PKTPTR\t(TMU_CSR_BASE_ADDR + 0x008)\n+#define TMU_PHY_INQ_PKTINFO\t(TMU_CSR_BASE_ADDR + 0x00c)\n+#define TMU_PHY_INQ_FIFO_CNT\t(TMU_CSR_BASE_ADDR + 0x010)\n+#define TMU_SYS_GENERIC_CONTROL\t(TMU_CSR_BASE_ADDR + 0x014)\n+#define TMU_SYS_GENERIC_STATUS\t(TMU_CSR_BASE_ADDR + 0x018)\n+#define TMU_SYS_GEN_CON0\t(TMU_CSR_BASE_ADDR + 0x01c)\n+#define TMU_SYS_GEN_CON1\t(TMU_CSR_BASE_ADDR + 0x020)\n+#define TMU_SYS_GEN_CON2\t(TMU_CSR_BASE_ADDR + 0x024)\n+#define TMU_SYS_GEN_CON3\t(TMU_CSR_BASE_ADDR + 0x028)\n+#define TMU_SYS_GEN_CON4\t(TMU_CSR_BASE_ADDR + 0x02c)\n+#define TMU_TEQ_DISABLE_DROPCHK\t(TMU_CSR_BASE_ADDR + 0x030)\n+#define TMU_TEQ_CTRL\t(TMU_CSR_BASE_ADDR + 0x034)\n+#define TMU_TEQ_QCFG\t(TMU_CSR_BASE_ADDR + 0x038)\n+#define TMU_TEQ_DROP_STAT\t(TMU_CSR_BASE_ADDR + 0x03c)\n+#define TMU_TEQ_QAVG\t(TMU_CSR_BASE_ADDR + 0x040)\n+#define TMU_TEQ_WREG_PROB\t(TMU_CSR_BASE_ADDR + 0x044)\n+#define TMU_TEQ_TRANS_STAT\t(TMU_CSR_BASE_ADDR + 0x048)\n+#define TMU_TEQ_HW_PROB_CFG0\t(TMU_CSR_BASE_ADDR + 0x04c)\n+#define TMU_TEQ_HW_PROB_CFG1\t(TMU_CSR_BASE_ADDR + 0x050)\n+#define TMU_TEQ_HW_PROB_CFG2\t(TMU_CSR_BASE_ADDR + 0x054)\n+#define TMU_TEQ_HW_PROB_CFG3\t(TMU_CSR_BASE_ADDR + 0x058)\n+#define TMU_TEQ_HW_PROB_CFG4\t(TMU_CSR_BASE_ADDR + 0x05c)\n+#define TMU_TEQ_HW_PROB_CFG5\t(TMU_CSR_BASE_ADDR + 0x060)\n+#define TMU_TEQ_HW_PROB_CFG6\t(TMU_CSR_BASE_ADDR + 0x064)\n+#define TMU_TEQ_HW_PROB_CFG7\t(TMU_CSR_BASE_ADDR + 0x068)\n+#define TMU_TEQ_HW_PROB_CFG8\t(TMU_CSR_BASE_ADDR + 0x06c)\n+#define TMU_TEQ_HW_PROB_CFG9\t(TMU_CSR_BASE_ADDR + 0x070)\n+#define TMU_TEQ_HW_PROB_CFG10\t(TMU_CSR_BASE_ADDR + 0x074)\n+#define TMU_TEQ_HW_PROB_CFG11\t(TMU_CSR_BASE_ADDR + 0x078)\n+#define TMU_TEQ_HW_PROB_CFG12\t(TMU_CSR_BASE_ADDR + 0x07c)\n+#define TMU_TEQ_HW_PROB_CFG13\t(TMU_CSR_BASE_ADDR + 0x080)\n+#define TMU_TEQ_HW_PROB_CFG14\t(TMU_CSR_BASE_ADDR + 0x084)\n+#define TMU_TEQ_HW_PROB_CFG15\t(TMU_CSR_BASE_ADDR + 0x088)\n+#define TMU_TEQ_HW_PROB_CFG16\t(TMU_CSR_BASE_ADDR + 0x08c)\n+#define TMU_TEQ_HW_PROB_CFG17\t(TMU_CSR_BASE_ADDR + 0x090)\n+#define TMU_TEQ_HW_PROB_CFG18\t(TMU_CSR_BASE_ADDR + 0x094)\n+#define TMU_TEQ_HW_PROB_CFG19\t(TMU_CSR_BASE_ADDR + 0x098)\n+#define TMU_TEQ_HW_PROB_CFG20\t(TMU_CSR_BASE_ADDR + 0x09c)\n+#define TMU_TEQ_HW_PROB_CFG21\t(TMU_CSR_BASE_ADDR + 0x0a0)\n+#define TMU_TEQ_HW_PROB_CFG22\t(TMU_CSR_BASE_ADDR + 0x0a4)\n+#define TMU_TEQ_HW_PROB_CFG23\t(TMU_CSR_BASE_ADDR + 0x0a8)\n+#define TMU_TEQ_HW_PROB_CFG24\t(TMU_CSR_BASE_ADDR + 0x0ac)\n+#define TMU_TEQ_HW_PROB_CFG25\t(TMU_CSR_BASE_ADDR + 0x0b0)\n+#define TMU_TDQ_IIFG_CFG\t(TMU_CSR_BASE_ADDR + 0x0b4)\n+/* [9:0] Scheduler Enable for each of the scheduler in the TDQ.\n+ * This is a global Enable for all schedulers in PHY0\n+ */\n+#define TMU_TDQ0_SCH_CTRL\t(TMU_CSR_BASE_ADDR + 0x0b8)\n+\n+#define TMU_LLM_CTRL\t(TMU_CSR_BASE_ADDR + 0x0bc)\n+#define TMU_LLM_BASE_ADDR\t(TMU_CSR_BASE_ADDR + 0x0c0)\n+#define TMU_LLM_QUE_LEN\t(TMU_CSR_BASE_ADDR + 0x0c4)\n+#define TMU_LLM_QUE_HEADPTR\t(TMU_CSR_BASE_ADDR + 0x0c8)\n+#define TMU_LLM_QUE_TAILPTR\t(TMU_CSR_BASE_ADDR + 0x0cc)\n+#define TMU_LLM_QUE_DROPCNT\t(TMU_CSR_BASE_ADDR + 0x0d0)\n+#define TMU_INT_EN\t(TMU_CSR_BASE_ADDR + 0x0d4)\n+#define TMU_INT_SRC\t(TMU_CSR_BASE_ADDR + 0x0d8)\n+#define TMU_INQ_STAT\t(TMU_CSR_BASE_ADDR + 0x0dc)\n+#define TMU_CTRL\t(TMU_CSR_BASE_ADDR + 0x0e0)\n+\n+/* [31] Mem Access Command. 0 = Internal Memory Read, 1 = Internal memory\n+ * Write [27:24] Byte Enables of the Internal memory access [23:0] Address of\n+ * the internal memory. This address is used to access both the PM and DM of\n+ * all the PE's\n+ */\n+#define TMU_MEM_ACCESS_ADDR\t(TMU_CSR_BASE_ADDR + 0x0e4)\n+\n+/* Internal Memory Access Write Data */\n+#define TMU_MEM_ACCESS_WDATA\t(TMU_CSR_BASE_ADDR + 0x0e8)\n+/* Internal Memory Access Read Data. The commands are blocked\n+ * at the mem_access only\n+ */\n+#define TMU_MEM_ACCESS_RDATA\t(TMU_CSR_BASE_ADDR + 0x0ec)\n+\n+/* [31:0] PHY0 in queue address (must be initialized with one of the\n+ * xxx_INQ_PKTPTR cbus addresses)\n+ */\n+#define TMU_PHY0_INQ_ADDR\t(TMU_CSR_BASE_ADDR + 0x0f0)\n+/* [31:0] PHY1 in queue address (must be initialized with one of the\n+ * xxx_INQ_PKTPTR cbus addresses)\n+ */\n+#define TMU_PHY1_INQ_ADDR\t(TMU_CSR_BASE_ADDR + 0x0f4)\n+/* [31:0] PHY2 in queue address (must be initialized with one of the\n+ * xxx_INQ_PKTPTR cbus addresses)\n+ */\n+#define TMU_PHY2_INQ_ADDR\t(TMU_CSR_BASE_ADDR + 0x0f8)\n+/* [31:0] PHY3 in queue address (must be initialized with one of the\n+ * xxx_INQ_PKTPTR cbus addresses)\n+ */\n+#define TMU_PHY3_INQ_ADDR\t(TMU_CSR_BASE_ADDR + 0x0fc)\n+#define TMU_BMU_INQ_ADDR\t(TMU_CSR_BASE_ADDR + 0x100)\n+#define TMU_TX_CTRL\t(TMU_CSR_BASE_ADDR + 0x104)\n+\n+#define TMU_BUS_ACCESS_WDATA\t(TMU_CSR_BASE_ADDR + 0x108)\n+#define TMU_BUS_ACCESS\t(TMU_CSR_BASE_ADDR + 0x10c)\n+#define TMU_BUS_ACCESS_RDATA\t(TMU_CSR_BASE_ADDR + 0x110)\n+\n+#define TMU_PE_SYS_CLK_RATIO\t(TMU_CSR_BASE_ADDR + 0x114)\n+#define TMU_PE_STATUS\t(TMU_CSR_BASE_ADDR + 0x118)\n+#define TMU_TEQ_MAX_THRESHOLD\t(TMU_CSR_BASE_ADDR + 0x11c)\n+/* [31:0] PHY4 in queue address (must be initialized with one of the\n+ * xxx_INQ_PKTPTR cbus addresses)\n+ */\n+#define TMU_PHY4_INQ_ADDR\t(TMU_CSR_BASE_ADDR + 0x134)\n+/* [9:0] Scheduler Enable for each of the scheduler in the TDQ.\n+ * This is a global Enable for all schedulers in PHY1\n+ */\n+#define TMU_TDQ1_SCH_CTRL\t(TMU_CSR_BASE_ADDR + 0x138)\n+/* [9:0] Scheduler Enable for each of the scheduler in the TDQ.\n+ * This is a global Enable for all schedulers in PHY2\n+ */\n+#define TMU_TDQ2_SCH_CTRL\t(TMU_CSR_BASE_ADDR + 0x13c)\n+/* [9:0] Scheduler Enable for each of the scheduler in the TDQ.\n+ * This is a global Enable for all schedulers in PHY3\n+ */\n+#define TMU_TDQ3_SCH_CTRL\t(TMU_CSR_BASE_ADDR + 0x140)\n+#define TMU_BMU_BUF_SIZE\t(TMU_CSR_BASE_ADDR + 0x144)\n+/* [31:0] PHY5 in queue address (must be initialized with one of the\n+ * xxx_INQ_PKTPTR cbus addresses)\n+ */\n+#define TMU_PHY5_INQ_ADDR\t(TMU_CSR_BASE_ADDR + 0x148)\n+\n+#define SW_RESET\t\tBIT(0)\t/* Global software reset */\n+#define INQ_RESET\t\tBIT(2)\n+#define TEQ_RESET\t\tBIT(3)\n+#define TDQ_RESET\t\tBIT(4)\n+#define PE_RESET\t\tBIT(5)\n+#define MEM_INIT\t\tBIT(6)\n+#define MEM_INIT_DONE\t\tBIT(7)\n+#define LLM_INIT\t\tBIT(8)\n+#define LLM_INIT_DONE\t\tBIT(9)\n+#define ECC_MEM_INIT_DONE\tBIT(10)\n+\n+struct tmu_cfg {\n+\tu32 pe_sys_clk_ratio;\n+\tunsigned long llm_base_addr;\n+\tu32 llm_queue_len;\n+};\n+\n+/* Not HW related for pfe_ctrl / pfe common defines */\n+#define DEFAULT_MAX_QDEPTH\t80\n+#define DEFAULT_Q0_QDEPTH\t511 /*We keep one large queue for host tx qos */\n+#define DEFAULT_TMU3_QDEPTH\t127\n+\n+#endif /* _TMU_CSR_H_ */\n--- /dev/null\n+++ b/drivers/staging/fsl_ppfe/include/pfe/cbus/util_csr.h\n@@ -0,0 +1,61 @@\n+/*\n+ * Copyright 2015-2016 Freescale Semiconductor, Inc.\n+ * Copyright 2017 NXP\n+ *\n+ * This program is free software; you can redistribute it and/or modify\n+ * it under the terms of the GNU General Public License as published by\n+ * the Free Software Foundation; either version 2 of the License, or\n+ * (at your option) any later version.\n+ *\n+ * This program is distributed in the hope that it will be useful,\n+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\n+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n+ * GNU General Public License for more details.\n+ *\n+ * You should have received a copy of the GNU General Public License\n+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.\n+ */\n+\n+#ifndef _UTIL_CSR_H_\n+#define _UTIL_CSR_H_\n+\n+#define UTIL_VERSION\t(UTIL_CSR_BASE_ADDR + 0x000)\n+#define UTIL_TX_CTRL\t(UTIL_CSR_BASE_ADDR + 0x004)\n+#define UTIL_INQ_PKTPTR\t(UTIL_CSR_BASE_ADDR + 0x010)\n+\n+#define UTIL_HDR_SIZE\t(UTIL_CSR_BASE_ADDR + 0x014)\n+\n+#define UTIL_PE0_QB_DM_ADDR0\t(UTIL_CSR_BASE_ADDR + 0x020)\n+#define UTIL_PE0_QB_DM_ADDR1\t(UTIL_CSR_BASE_ADDR + 0x024)\n+#define UTIL_PE0_RO_DM_ADDR0\t(UTIL_CSR_BASE_ADDR + 0x060)\n+#define UTIL_PE0_RO_DM_ADDR1\t(UTIL_CSR_BASE_ADDR + 0x064)\n+\n+#define UTIL_MEM_ACCESS_ADDR\t(UTIL_CSR_BASE_ADDR + 0x100)\n+#define UTIL_MEM_ACCESS_WDATA\t(UTIL_CSR_BASE_ADDR + 0x104)\n+#define UTIL_MEM_ACCESS_RDATA\t(UTIL_CSR_BASE_ADDR + 0x108)\n+\n+#define UTIL_TM_INQ_ADDR\t(UTIL_CSR_BASE_ADDR + 0x114)\n+#define UTIL_PE_STATUS\t(UTIL_CSR_BASE_ADDR + 0x118)\n+\n+#define UTIL_PE_SYS_CLK_RATIO\t(UTIL_CSR_BASE_ADDR + 0x200)\n+#define UTIL_AFULL_THRES\t(UTIL_CSR_BASE_ADDR + 0x204)\n+#define UTIL_GAP_BETWEEN_READS\t(UTIL_CSR_BASE_ADDR + 0x208)\n+#define UTIL_MAX_BUF_CNT\t(UTIL_CSR_BASE_ADDR + 0x20c)\n+#define UTIL_TSQ_FIFO_THRES\t(UTIL_CSR_BASE_ADDR + 0x210)\n+#define UTIL_TSQ_MAX_CNT\t(UTIL_CSR_BASE_ADDR + 0x214)\n+#define UTIL_IRAM_DATA_0\t(UTIL_CSR_BASE_ADDR + 0x218)\n+#define UTIL_IRAM_DATA_1\t(UTIL_CSR_BASE_ADDR + 0x21c)\n+#define UTIL_IRAM_DATA_2\t(UTIL_CSR_BASE_ADDR + 0x220)\n+#define UTIL_IRAM_DATA_3\t(UTIL_CSR_BASE_ADDR + 0x224)\n+\n+#define UTIL_BUS_ACCESS_ADDR\t(UTIL_CSR_BASE_ADDR + 0x228)\n+#define UTIL_BUS_ACCESS_WDATA\t(UTIL_CSR_BASE_ADDR + 0x22c)\n+#define UTIL_BUS_ACCESS_RDATA\t(UTIL_CSR_BASE_ADDR + 0x230)\n+\n+#define UTIL_INQ_AFULL_THRES\t(UTIL_CSR_BASE_ADDR + 0x234)\n+\n+struct util_cfg {\n+\tu32 pe_sys_clk_ratio;\n+};\n+\n+#endif /* _UTIL_CSR_H_ */\n--- /dev/null\n+++ b/drivers/staging/fsl_ppfe/include/pfe/pfe.h\n@@ -0,0 +1,372 @@\n+/*\n+ * Copyright 2015-2016 Freescale Semiconductor, Inc.\n+ * Copyright 2017 NXP\n+ *\n+ * This program is free software; you can redistribute it and/or modify\n+ * it under the terms of the GNU General Public License as published by\n+ * the Free Software Foundation; either version 2 of the License, or\n+ * (at your option) any later version.\n+ *\n+ * This program is distributed in the hope that it will be useful,\n+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\n+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n+ * GNU General Public License for more details.\n+ *\n+ * You should have received a copy of the GNU General Public License\n+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.\n+ */\n+\n+#ifndef _PFE_H_\n+#define _PFE_H_\n+\n+#include \"cbus.h\"\n+\n+#define CLASS_DMEM_BASE_ADDR(i)\t(0x00000000 | ((i) << 20))\n+/*\n+ * Only valid for mem access register interface\n+ */\n+#define CLASS_IMEM_BASE_ADDR(i)\t(0x00000000 | ((i) << 20))\n+#define CLASS_DMEM_SIZE\t0x00002000\n+#define CLASS_IMEM_SIZE\t0x00008000\n+\n+#define TMU_DMEM_BASE_ADDR(i)\t(0x00000000 + ((i) << 20))\n+/*\n+ * Only valid for mem access register interface\n+ */\n+#define TMU_IMEM_BASE_ADDR(i)\t(0x00000000 + ((i) << 20))\n+#define TMU_DMEM_SIZE\t0x00000800\n+#define TMU_IMEM_SIZE\t0x00002000\n+\n+#define UTIL_DMEM_BASE_ADDR\t0x00000000\n+#define UTIL_DMEM_SIZE\t0x00002000\n+\n+#define PE_LMEM_BASE_ADDR\t0xc3010000\n+#define PE_LMEM_SIZE\t0x8000\n+#define PE_LMEM_END\t(PE_LMEM_BASE_ADDR + PE_LMEM_SIZE)\n+\n+#define DMEM_BASE_ADDR\t0x00000000\n+#define DMEM_SIZE\t0x2000\t/* TMU has less... */\n+#define DMEM_END\t(DMEM_BASE_ADDR + DMEM_SIZE)\n+\n+#define PMEM_BASE_ADDR\t0x00010000\n+#define PMEM_SIZE\t0x8000\t/* TMU has less... */\n+#define PMEM_END\t(PMEM_BASE_ADDR + PMEM_SIZE)\n+\n+/* These check memory ranges from PE point of view/memory map */\n+#define IS_DMEM(addr, len)\t\t\t\t\\\n+\t({ typeof(addr) addr_ = (addr);\t\t\t\\\n+\t((unsigned long)(addr_) >= DMEM_BASE_ADDR) &&\t\\\n+\t(((unsigned long)(addr_) + (len)) <= DMEM_END); })\n+\n+#define IS_PMEM(addr, len)\t\t\t\t\\\n+\t({ typeof(addr) addr_ = (addr);\t\t\t\\\n+\t((unsigned long)(addr_) >= PMEM_BASE_ADDR) &&\t\\\n+\t(((unsigned long)(addr_) + (len)) <= PMEM_END); })\n+\n+#define IS_PE_LMEM(addr, len)\t\t\t\t\\\n+\t({ typeof(addr) addr_ = (addr);\t\t\t\\\n+\t((unsigned long)(addr_) >=\t\t\t\\\n+\tPE_LMEM_BASE_ADDR) &&\t\t\t\t\\\n+\t(((unsigned long)(addr_) +\t\t\t\\\n+\t(len)) <= PE_LMEM_END); })\n+\n+#define IS_PFE_LMEM(addr, len)\t\t\t\t\\\n+\t({ typeof(addr) addr_ = (addr);\t\t\t\\\n+\t((unsigned long)(addr_) >=\t\t\t\\\n+\tCBUS_VIRT_TO_PFE(LMEM_BASE_ADDR)) &&\t\t\\\n+\t(((unsigned long)(addr_) + (len)) <=\t\t\\\n+\tCBUS_VIRT_TO_PFE(LMEM_END)); })\n+\n+#define __IS_PHYS_DDR(addr, len)\t\t\t\\\n+\t({ typeof(addr) addr_ = (addr);\t\t\t\\\n+\t((unsigned long)(addr_) >=\t\t\t\\\n+\tDDR_PHYS_BASE_ADDR) &&\t\t\t\t\\\n+\t(((unsigned long)(addr_) + (len)) <=\t\t\\\n+\tDDR_PHYS_END); })\n+\n+#define IS_PHYS_DDR(addr, len)\t__IS_PHYS_DDR(DDR_PFE_TO_PHYS(addr), len)\n+\n+/*\n+ * If using a run-time virtual address for the cbus base address use this code\n+ */\n+extern void *cbus_base_addr;\n+extern void *ddr_base_addr;\n+extern unsigned long ddr_phys_base_addr;\n+extern unsigned int ddr_size;\n+\n+#define CBUS_BASE_ADDR\tcbus_base_addr\n+#define DDR_PHYS_BASE_ADDR\tddr_phys_base_addr\n+#define DDR_BASE_ADDR\tddr_base_addr\n+#define DDR_SIZE\tddr_size\n+\n+#define DDR_PHYS_END\t(DDR_PHYS_BASE_ADDR + DDR_SIZE)\n+\n+#define LS1012A_PFE_RESET_WA\t/*\n+\t\t\t\t * PFE doesn't have global reset and re-init\n+\t\t\t\t * should takecare few things to make PFE\n+\t\t\t\t * functional after reset\n+\t\t\t\t */\n+#define PFE_CBUS_PHYS_BASE_ADDR\t0xc0000000\t/* CBUS physical base address\n+\t\t\t\t\t\t * as seen by PE's.\n+\t\t\t\t\t\t */\n+/* CBUS physical base address as seen by PE's. */\n+#define PFE_CBUS_PHYS_BASE_ADDR_FROM_PFE\t0xc0000000\n+\n+#define DDR_PHYS_TO_PFE(p)\t(((unsigned long int)(p)) & 0x7FFFFFFF)\n+#define DDR_PFE_TO_PHYS(p)\t(((unsigned long int)(p)) | 0x80000000)\n+#define CBUS_PHYS_TO_PFE(p)\t(((p) - PFE_CBUS_PHYS_BASE_ADDR) + \\\n+\t\t\t\tPFE_CBUS_PHYS_BASE_ADDR_FROM_PFE)\n+/* Translates to PFE address map */\n+\n+#define DDR_PHYS_TO_VIRT(p)\t(((p) - DDR_PHYS_BASE_ADDR) + DDR_BASE_ADDR)\n+#define DDR_VIRT_TO_PHYS(v)\t(((v) - DDR_BASE_ADDR) + DDR_PHYS_BASE_ADDR)\n+#define DDR_VIRT_TO_PFE(p)\t(DDR_PHYS_TO_PFE(DDR_VIRT_TO_PHYS(p)))\n+\n+#define CBUS_VIRT_TO_PFE(v)\t(((v) - CBUS_BASE_ADDR) + \\\n+\t\t\t\tPFE_CBUS_PHYS_BASE_ADDR)\n+#define CBUS_PFE_TO_VIRT(p)\t(((unsigned long int)(p) - \\\n+\t\t\t\tPFE_CBUS_PHYS_BASE_ADDR) + CBUS_BASE_ADDR)\n+\n+/* The below part of the code is used in QOS control driver from host */\n+#define TMU_APB_BASE_ADDR       0xc1000000      /* TMU base address seen by\n+\t\t\t\t\t\t * pe's\n+\t\t\t\t\t\t */\n+\n+enum {\n+\tCLASS0_ID = 0,\n+\tCLASS1_ID,\n+\tCLASS2_ID,\n+\tCLASS3_ID,\n+\tCLASS4_ID,\n+\tCLASS5_ID,\n+\tTMU0_ID,\n+\tTMU1_ID,\n+\tTMU2_ID,\n+\tTMU3_ID,\n+#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)\n+\tUTIL_ID,\n+#endif\n+\tMAX_PE\n+};\n+\n+#define CLASS_MASK\t(BIT(CLASS0_ID) | BIT(CLASS1_ID) |\\\n+\t\t\tBIT(CLASS2_ID) | BIT(CLASS3_ID) |\\\n+\t\t\tBIT(CLASS4_ID) | BIT(CLASS5_ID))\n+#define CLASS_MAX_ID\tCLASS5_ID\n+\n+#define TMU_MASK\t(BIT(TMU0_ID) | BIT(TMU1_ID) |\\\n+\t\t\tBIT(TMU3_ID))\n+\n+#define TMU_MAX_ID\tTMU3_ID\n+\n+#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)\n+#define UTIL_MASK\tBIT(UTIL_ID)\n+#endif\n+\n+struct pe_status {\n+\tu32\tcpu_state;\n+\tu32\tactivity_counter;\n+\tu32\trx;\n+\tunion {\n+\tu32\ttx;\n+\tu32\ttmu_qstatus;\n+\t};\n+\tu32\tdrop;\n+#if defined(CFG_PE_DEBUG)\n+\tu32\tdebug_indicator;\n+\tu32\tdebug[16];\n+#endif\n+} __aligned(16);\n+\n+struct pe_sync_mailbox {\n+\tu32 stop;\n+\tu32 stopped;\n+};\n+\n+/* Drop counter definitions */\n+\n+#define\tCLASS_NUM_DROP_COUNTERS\t13\n+#define\tUTIL_NUM_DROP_COUNTERS\t8\n+\n+/* PE information.\n+ * Structure containing PE's specific information. It is used to create\n+ * generic C functions common to all PE's.\n+ * Before using the library functions this structure needs to be initialized\n+ * with the different registers virtual addresses\n+ * (according to the ARM MMU mmaping). The default initialization supports a\n+ * virtual == physical mapping.\n+ */\n+struct pe_info {\n+\tu32 dmem_base_addr;\t/* PE's dmem base address */\n+\tu32 pmem_base_addr;\t/* PE's pmem base address */\n+\tu32 pmem_size;\t/* PE's pmem size */\n+\n+\tvoid *mem_access_wdata;\t/* PE's _MEM_ACCESS_WDATA register\n+\t\t\t\t * address\n+\t\t\t\t */\n+\tvoid *mem_access_addr;\t/* PE's _MEM_ACCESS_ADDR register\n+\t\t\t\t * address\n+\t\t\t\t */\n+\tvoid *mem_access_rdata;\t/* PE's _MEM_ACCESS_RDATA register\n+\t\t\t\t * address\n+\t\t\t\t */\n+};\n+\n+void pe_lmem_read(u32 *dst, u32 len, u32 offset);\n+void pe_lmem_write(u32 *src, u32 len, u32 offset);\n+\n+void pe_dmem_memcpy_to32(int id, u32 dst, const void *src, unsigned int len);\n+void pe_pmem_memcpy_to32(int id, u32 dst, const void *src, unsigned int len);\n+\n+u32 pe_pmem_read(int id, u32 addr, u8 size);\n+\n+void pe_dmem_write(int id, u32 val, u32 addr, u8 size);\n+u32 pe_dmem_read(int id, u32 addr, u8 size);\n+void class_pe_lmem_memcpy_to32(u32 dst, const void *src, unsigned int len);\n+void class_pe_lmem_memset(u32 dst, int val, unsigned int len);\n+void class_bus_write(u32 val, u32 addr, u8 size);\n+u32 class_bus_read(u32 addr, u8 size);\n+\n+#define class_bus_readl(addr)\tclass_bus_read(addr, 4)\n+#define class_bus_readw(addr)\tclass_bus_read(addr, 2)\n+#define class_bus_readb(addr)\tclass_bus_read(addr, 1)\n+\n+#define class_bus_writel(val, addr)\tclass_bus_write(val, addr, 4)\n+#define class_bus_writew(val, addr)\tclass_bus_write(val, addr, 2)\n+#define class_bus_writeb(val, addr)\tclass_bus_write(val, addr, 1)\n+\n+#define pe_dmem_readl(id, addr)\tpe_dmem_read(id, addr, 4)\n+#define pe_dmem_readw(id, addr)\tpe_dmem_read(id, addr, 2)\n+#define pe_dmem_readb(id, addr)\tpe_dmem_read(id, addr, 1)\n+\n+#define pe_dmem_writel(id, val, addr)\tpe_dmem_write(id, val, addr, 4)\n+#define pe_dmem_writew(id, val, addr)\tpe_dmem_write(id, val, addr, 2)\n+#define pe_dmem_writeb(id, val, addr)\tpe_dmem_write(id, val, addr, 1)\n+\n+/*int pe_load_elf_section(int id, const void *data, elf32_shdr *shdr); */\n+int pe_load_elf_section(int id, const void *data, struct elf32_shdr *shdr,\n+\t\t\tstruct device *dev);\n+\n+void pfe_lib_init(void *cbus_base, void *ddr_base, unsigned long ddr_phys_base,\n+\t\t  unsigned int ddr_size);\n+void bmu_init(void *base, struct BMU_CFG *cfg);\n+void bmu_reset(void *base);\n+void bmu_enable(void *base);\n+void bmu_disable(void *base);\n+void bmu_set_config(void *base, struct BMU_CFG *cfg);\n+\n+/*\n+ * An enumerated type for loopback values.  This can be one of three values, no\n+ * loopback -normal operation, local loopback with internal loopback module of\n+ * MAC or PHY loopback which is through the external PHY.\n+ */\n+#ifndef __MAC_LOOP_ENUM__\n+#define __MAC_LOOP_ENUM__\n+enum mac_loop {LB_NONE, LB_EXT, LB_LOCAL};\n+#endif\n+\n+void gemac_init(void *base, void *config);\n+void gemac_disable_rx_checksum_offload(void *base);\n+void gemac_enable_rx_checksum_offload(void *base);\n+void gemac_set_speed(void *base, enum mac_speed gem_speed);\n+void gemac_set_duplex(void *base, int duplex);\n+void gemac_set_mode(void *base, int mode);\n+void gemac_enable(void *base);\n+void gemac_tx_disable(void *base);\n+void gemac_tx_enable(void *base);\n+void gemac_disable(void *base);\n+void gemac_reset(void *base);\n+void gemac_set_address(void *base, struct spec_addr *addr);\n+struct spec_addr gemac_get_address(void *base);\n+void gemac_set_loop(void *base, enum mac_loop gem_loop);\n+void gemac_set_laddr1(void *base, struct pfe_mac_addr *address);\n+void gemac_set_laddr2(void *base, struct pfe_mac_addr *address);\n+void gemac_set_laddr3(void *base, struct pfe_mac_addr *address);\n+void gemac_set_laddr4(void *base, struct pfe_mac_addr *address);\n+void gemac_set_laddrN(void *base, struct pfe_mac_addr *address,\n+\t\t      unsigned int entry_index);\n+void gemac_clear_laddr1(void *base);\n+void gemac_clear_laddr2(void *base);\n+void gemac_clear_laddr3(void *base);\n+void gemac_clear_laddr4(void *base);\n+void gemac_clear_laddrN(void *base, unsigned int entry_index);\n+struct pfe_mac_addr gemac_get_hash(void *base);\n+void gemac_set_hash(void *base, struct pfe_mac_addr *hash);\n+struct pfe_mac_addr gem_get_laddr1(void *base);\n+struct pfe_mac_addr gem_get_laddr2(void *base);\n+struct pfe_mac_addr gem_get_laddr3(void *base);\n+struct pfe_mac_addr gem_get_laddr4(void *base);\n+struct pfe_mac_addr gem_get_laddrN(void *base, unsigned int entry_index);\n+void gemac_set_config(void *base, struct gemac_cfg *cfg);\n+void gemac_allow_broadcast(void *base);\n+void gemac_no_broadcast(void *base);\n+void gemac_enable_1536_rx(void *base);\n+void gemac_disable_1536_rx(void *base);\n+void gemac_set_rx_max_fl(void *base, int mtu);\n+void gemac_enable_rx_jmb(void *base);\n+void gemac_disable_rx_jmb(void *base);\n+void gemac_enable_stacked_vlan(void *base);\n+void gemac_disable_stacked_vlan(void *base);\n+void gemac_enable_pause_rx(void *base);\n+void gemac_disable_pause_rx(void *base);\n+void gemac_enable_copy_all(void *base);\n+void gemac_disable_copy_all(void *base);\n+void gemac_set_bus_width(void *base, int width);\n+void gemac_set_wol(void *base, u32 wol_conf);\n+\n+void gpi_init(void *base, struct gpi_cfg *cfg);\n+void gpi_reset(void *base);\n+void gpi_enable(void *base);\n+void gpi_disable(void *base);\n+void gpi_set_config(void *base, struct gpi_cfg *cfg);\n+\n+void class_init(struct class_cfg *cfg);\n+void class_reset(void);\n+void class_enable(void);\n+void class_disable(void);\n+void class_set_config(struct class_cfg *cfg);\n+\n+void tmu_reset(void);\n+void tmu_init(struct tmu_cfg *cfg);\n+void tmu_enable(u32 pe_mask);\n+void tmu_disable(u32 pe_mask);\n+u32  tmu_qstatus(u32 if_id);\n+u32  tmu_pkts_processed(u32 if_id);\n+\n+void util_init(struct util_cfg *cfg);\n+void util_reset(void);\n+void util_enable(void);\n+void util_disable(void);\n+\n+void hif_init(void);\n+void hif_tx_enable(void);\n+void hif_tx_disable(void);\n+void hif_rx_enable(void);\n+void hif_rx_disable(void);\n+\n+/* Get Chip Revision level\n+ *\n+ */\n+static inline unsigned int CHIP_REVISION(void)\n+{\n+\t/*For LS1012A return always 1 */\n+\treturn 1;\n+}\n+\n+/* Start HIF rx DMA\n+ *\n+ */\n+static inline void hif_rx_dma_start(void)\n+{\n+\twritel(HIF_CTRL_DMA_EN | HIF_CTRL_BDP_CH_START_WSTB, HIF_RX_CTRL);\n+}\n+\n+/* Start HIF tx DMA\n+ *\n+ */\n+static inline void hif_tx_dma_start(void)\n+{\n+\twritel(HIF_CTRL_DMA_EN | HIF_CTRL_BDP_CH_START_WSTB, HIF_TX_CTRL);\n+}\n+\n+#endif /* _PFE_H_ */\n--- /dev/null\n+++ b/drivers/staging/fsl_ppfe/pfe_cdev.c\n@@ -0,0 +1,258 @@\n+// SPDX-License-Identifier: GPL-2.0+\n+/*\n+ * Copyright 2018 NXP\n+ */\n+\n+/* @pfe_cdev.c.\n+ *  Dummy device representing the PFE US in userspace.\n+ *  - used for interacting with the kernel layer for link status\n+ */\n+\n+#include <linux/eventfd.h>\n+#include <linux/irqreturn.h>\n+#include <linux/io.h>\n+#include <asm/irq.h>\n+\n+#include \"pfe_cdev.h\"\n+#include \"pfe_mod.h\"\n+\n+static int pfe_majno;\n+static struct class *pfe_char_class;\n+static struct device *pfe_char_dev;\n+struct eventfd_ctx *g_trigger;\n+\n+struct pfe_shared_info link_states[PFE_CDEV_ETH_COUNT];\n+\n+static int pfe_cdev_open(struct inode *inp, struct file *fp)\n+{\n+\tpr_debug(\"PFE CDEV device opened.\\n\");\n+\treturn 0;\n+}\n+\n+static ssize_t pfe_cdev_read(struct file *fp, char *buf,\n+\t\t\t     size_t len, loff_t *off)\n+{\n+\tint ret = 0;\n+\n+\tpr_info(\"PFE CDEV attempt copying (%lu) size of user.\\n\",\n+\t\tsizeof(link_states));\n+\n+\tpr_debug(\"Dump link_state on screen before copy_to_user\\n\");\n+\tfor (; ret < PFE_CDEV_ETH_COUNT; ret++) {\n+\t\tpr_debug(\"%u  %u\", link_states[ret].phy_id,\n+\t\t\t link_states[ret].state);\n+\t\tpr_debug(\"\\n\");\n+\t}\n+\n+\t/* Copy to user the value in buffer sized len */\n+\tret = copy_to_user(buf, &link_states, sizeof(link_states));\n+\tif (ret != 0) {\n+\t\tpr_err(\"Failed to send (%d)bytes of (%lu) requested.\\n\",\n+\t\t       ret, len);\n+\t\treturn -EFAULT;\n+\t}\n+\n+\t/* offset set back to 0 as there is contextual reading offset */\n+\t*off = 0;\n+\tpr_debug(\"Read of (%lu) bytes performed.\\n\", sizeof(link_states));\n+\n+\treturn sizeof(link_states);\n+}\n+\n+/**\n+ * This function is for getting some commands from user through non-IOCTL\n+ * channel. It can used to configure the device.\n+ * TODO: To be filled in future, if require duplex communication with user\n+ * space.\n+ */\n+static ssize_t pfe_cdev_write(struct file *fp, const char *buf,\n+\t\t\t      size_t len, loff_t *off)\n+{\n+\tpr_info(\"PFE CDEV Write operation not supported!\\n\");\n+\n+\treturn -EFAULT;\n+}\n+\n+static int pfe_cdev_release(struct inode *inp, struct file *fp)\n+{\n+\tif (g_trigger) {\n+\t\tfree_irq(pfe->hif_irq, g_trigger);\n+\t\teventfd_ctx_put(g_trigger);\n+\t\tg_trigger = NULL;\n+\t}\n+\n+\tpr_info(\"PFE_CDEV: Device successfully closed\\n\");\n+\treturn 0;\n+}\n+\n+/*\n+ * hif_us_isr-\n+ * This ISR routine processes Rx/Tx done interrupts from the HIF hardware block\n+ */\n+static irqreturn_t hif_us_isr(int irq, void *arg)\n+{\n+\tstruct eventfd_ctx *trigger = (struct eventfd_ctx *)arg;\n+\tint int_status;\n+\tint int_enable_mask;\n+\n+\t/*Read hif interrupt source register */\n+\tint_status = readl_relaxed(HIF_INT_SRC);\n+\tint_enable_mask = readl_relaxed(HIF_INT_ENABLE);\n+\n+\tif ((int_status & HIF_INT) == 0)\n+\t\treturn IRQ_NONE;\n+\n+\tif (int_status & HIF_RXPKT_INT) {\n+\t\tint_enable_mask &= ~(HIF_RXPKT_INT);\n+\t\t/* Disable interrupts, they will be enabled after\n+\t\t * they are serviced\n+\t\t */\n+\t\twritel_relaxed(int_enable_mask, HIF_INT_ENABLE);\n+\n+\t\teventfd_signal(trigger, 1);\n+\t}\n+\n+\treturn IRQ_HANDLED;\n+}\n+\n+#define PFE_INTR_COAL_USECS\t100\n+static long pfe_cdev_ioctl(struct file *fp, unsigned int cmd,\n+\t\t\t   unsigned long arg)\n+{\n+\tint ret = -EFAULT;\n+\tint __user *argp = (int __user *)arg;\n+\n+\tpr_debug(\"PFE CDEV IOCTL Called with cmd=(%u)\\n\", cmd);\n+\n+\tswitch (cmd) {\n+\tcase PFE_CDEV_ETH0_STATE_GET:\n+\t\t/* Return an unsigned int (link state) for ETH0 */\n+\t\t*argp = link_states[0].state;\n+\t\tpr_debug(\"Returning state=%d for ETH0\\n\", *argp);\n+\t\tret = 0;\n+\t\tbreak;\n+\tcase PFE_CDEV_ETH1_STATE_GET:\n+\t\t/* Return an unsigned int (link state) for ETH0 */\n+\t\t*argp = link_states[1].state;\n+\t\tpr_debug(\"Returning state=%d for ETH1\\n\", *argp);\n+\t\tret = 0;\n+\t\tbreak;\n+\tcase PFE_CDEV_HIF_INTR_EN:\n+\t\t/* Return success/failure */\n+\t\tg_trigger = eventfd_ctx_fdget(*argp);\n+\t\tif (IS_ERR(g_trigger))\n+\t\t\treturn PTR_ERR(g_trigger);\n+\t\tret = request_irq(pfe->hif_irq, hif_us_isr, 0, \"pfe_hif\",\n+\t\t\t\t  g_trigger);\n+\t\tif (ret) {\n+\t\t\tpr_err(\"%s: failed to get the hif IRQ = %d\\n\",\n+\t\t\t       __func__, pfe->hif_irq);\n+\t\t\teventfd_ctx_put(g_trigger);\n+\t\t\tg_trigger = NULL;\n+\t\t}\n+\t\twritel((PFE_INTR_COAL_USECS * (pfe->ctrl.sys_clk / 1000)) |\n+\t\t\tHIF_INT_COAL_ENABLE, HIF_INT_COAL);\n+\n+\t\tpr_debug(\"request_irq for hif interrupt: %d\\n\", pfe->hif_irq);\n+\t\tret = 0;\n+\t\tbreak;\n+\tdefault:\n+\t\tpr_info(\"Unsupport cmd (%d) for PFE CDEV.\\n\", cmd);\n+\t\tbreak;\n+\t};\n+\n+\treturn ret;\n+}\n+\n+static unsigned int pfe_cdev_poll(struct file *fp,\n+\t\t\t\t  struct poll_table_struct *wait)\n+{\n+\tpr_info(\"PFE CDEV poll method not supported\\n\");\n+\treturn 0;\n+}\n+\n+static const struct file_operations pfe_cdev_fops = {\n+\t.open = pfe_cdev_open,\n+\t.read = pfe_cdev_read,\n+\t.write = pfe_cdev_write,\n+\t.release = pfe_cdev_release,\n+\t.unlocked_ioctl = pfe_cdev_ioctl,\n+\t.poll = pfe_cdev_poll,\n+};\n+\n+int pfe_cdev_init(void)\n+{\n+\tint ret;\n+\n+\tpr_debug(\"PFE CDEV initialization begin\\n\");\n+\n+\t/* Register the major number for the device */\n+\tpfe_majno = register_chrdev(0, PFE_CDEV_NAME, &pfe_cdev_fops);\n+\tif (pfe_majno < 0) {\n+\t\tpr_err(\"Unable to register PFE CDEV. PFE CDEV not available\\n\");\n+\t\tret = pfe_majno;\n+\t\tgoto cleanup;\n+\t}\n+\n+\tpr_debug(\"PFE CDEV assigned major number: %d\\n\", pfe_majno);\n+\n+\t/* Register the class for the device */\n+\tpfe_char_class = class_create(THIS_MODULE, PFE_CLASS_NAME);\n+\tif (IS_ERR(pfe_char_class)) {\n+\t\tpr_err(\n+\t\t\"Failed to init class for PFE CDEV. PFE CDEV not available.\\n\");\n+\t\tret = PTR_ERR(pfe_char_class);\n+\t\tgoto cleanup;\n+\t}\n+\n+\tpr_debug(\"PFE CDEV Class created successfully.\\n\");\n+\n+\t/* Create the device without any parent and without any callback data */\n+\t    pfe_char_dev = device_create(pfe_char_class, NULL,\n+\t\t\t\t\t MKDEV(pfe_majno, 0), NULL,\n+\t\t\t\t\t PFE_CDEV_NAME);\n+\tif (IS_ERR(pfe_char_dev)) {\n+\t\tpr_err(\"Unable to PFE CDEV device. PFE CDEV not available.\\n\");\n+\t\tret = PTR_ERR(pfe_char_dev);\n+\t\tgoto cleanup;\n+\t}\n+\n+\t/* Information structure being shared with the userspace */\n+\tmemset(link_states, 0, sizeof(struct pfe_shared_info) *\n+\t\t\tPFE_CDEV_ETH_COUNT);\n+\n+\tpr_info(\"PFE CDEV created: %s\\n\", PFE_CDEV_NAME);\n+\n+\tret = 0;\n+\treturn ret;\n+\n+cleanup:\n+\tif (!IS_ERR(pfe_char_class))\n+\t\tclass_destroy(pfe_char_class);\n+\n+\tif (pfe_majno > 0)\n+\t\tunregister_chrdev(pfe_majno, PFE_CDEV_NAME);\n+\n+\treturn ret;\n+}\n+\n+void pfe_cdev_exit(void)\n+{\n+\tif (!IS_ERR(pfe_char_dev))\n+\t\tdevice_destroy(pfe_char_class, MKDEV(pfe_majno, 0));\n+\n+\tif (!IS_ERR(pfe_char_class)) {\n+\t\tclass_unregister(pfe_char_class);\n+\t\tclass_destroy(pfe_char_class);\n+\t}\n+\n+\tif (pfe_majno > 0)\n+\t\tunregister_chrdev(pfe_majno, PFE_CDEV_NAME);\n+\n+\t/* reset the variables */\n+\tpfe_majno = 0;\n+\tpfe_char_class = NULL;\n+\tpfe_char_dev = NULL;\n+\n+\tpr_info(\"PFE CDEV Removed.\\n\");\n+}\n--- /dev/null\n+++ b/drivers/staging/fsl_ppfe/pfe_cdev.h\n@@ -0,0 +1,41 @@\n+/* SPDX-License-Identifier: GPL-2.0+ */\n+/*\n+ * Copyright 2018 NXP\n+ */\n+\n+#ifndef _PFE_CDEV_H_\n+#define _PFE_CDEV_H_\n+\n+#include <linux/init.h>\n+#include <linux/device.h>\n+#include <linux/err.h>\n+#include <linux/kernel.h>\n+#include <linux/fs.h>\n+#include <linux/uaccess.h>\n+#include <linux/poll.h>\n+\n+#define  PFE_CDEV_NAME \"pfe_us_cdev\"\n+#define  PFE_CLASS_NAME  \"ppfe_us\"\n+\n+/* Extracted from ls1012a_pfe_platform_data, there are 3 interfaces which are\n+ * supported by PFE driver. Should be updated if number of eth devices are\n+ * changed.\n+ */\n+#define PFE_CDEV_ETH_COUNT 3\n+\n+struct pfe_shared_info {\n+\tuint32_t phy_id; /* Link phy ID */\n+\tuint8_t state;  /* Has either 0 or 1 */\n+};\n+\n+extern struct pfe_shared_info link_states[PFE_CDEV_ETH_COUNT];\n+\n+/* IOCTL Commands */\n+#define PFE_CDEV_ETH0_STATE_GET\t\t_IOR('R', 0, int)\n+#define PFE_CDEV_ETH1_STATE_GET\t\t_IOR('R', 1, int)\n+#define PFE_CDEV_HIF_INTR_EN\t\t_IOWR('R', 2, int)\n+\n+int pfe_cdev_init(void);\n+void pfe_cdev_exit(void);\n+\n+#endif /* _PFE_CDEV_H_ */\n--- /dev/null\n+++ b/drivers/staging/fsl_ppfe/pfe_ctrl.c\n@@ -0,0 +1,226 @@\n+// SPDX-License-Identifier: GPL-2.0+\n+/*\n+ * Copyright 2015-2016 Freescale Semiconductor, Inc.\n+ * Copyright 2017 NXP\n+ */\n+\n+#include <linux/kernel.h>\n+#include <linux/sched.h>\n+#include <linux/module.h>\n+#include <linux/list.h>\n+#include <linux/kthread.h>\n+\n+#include \"pfe_mod.h\"\n+#include \"pfe_ctrl.h\"\n+\n+#define TIMEOUT_MS\t1000\n+\n+int relax(unsigned long end)\n+{\n+\tif (time_after(jiffies, end)) {\n+\t\tif (time_after(jiffies, end + (TIMEOUT_MS * HZ) / 1000))\n+\t\t\treturn -1;\n+\n+\t\tif (need_resched())\n+\t\t\tschedule();\n+\t}\n+\n+\treturn 0;\n+}\n+\n+void pfe_ctrl_suspend(struct pfe_ctrl *ctrl)\n+{\n+\tint id;\n+\n+\tmutex_lock(&ctrl->mutex);\n+\n+\tfor (id = CLASS0_ID; id <= CLASS_MAX_ID; id++)\n+\t\tpe_dmem_write(id, cpu_to_be32(0x1), CLASS_DM_RESUME, 4);\n+\n+\tfor (id = TMU0_ID; id <= TMU_MAX_ID; id++) {\n+\t\tif (id == TMU2_ID)\n+\t\t\tcontinue;\n+\t\tpe_dmem_write(id, cpu_to_be32(0x1), TMU_DM_RESUME, 4);\n+\t}\n+\n+#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)\n+\tpe_dmem_write(UTIL_ID, cpu_to_be32(0x1), UTIL_DM_RESUME, 4);\n+#endif\n+\tmutex_unlock(&ctrl->mutex);\n+}\n+\n+void pfe_ctrl_resume(struct pfe_ctrl *ctrl)\n+{\n+\tint pe_mask = CLASS_MASK | TMU_MASK;\n+\n+#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)\n+\tpe_mask |= UTIL_MASK;\n+#endif\n+\tmutex_lock(&ctrl->mutex);\n+\tpe_start(&pfe->ctrl, pe_mask);\n+\tmutex_unlock(&ctrl->mutex);\n+}\n+\n+/* PE sync stop.\n+ * Stops packet processing for a list of PE's (specified using a bitmask).\n+ * The caller must hold ctrl->mutex.\n+ *\n+ * @param ctrl\t\tControl context\n+ * @param pe_mask\tMask of PE id's to stop\n+ *\n+ */\n+int pe_sync_stop(struct pfe_ctrl *ctrl, int pe_mask)\n+{\n+\tstruct pe_sync_mailbox *mbox;\n+\tint pe_stopped = 0;\n+\tunsigned long end = jiffies + 2;\n+\tint i;\n+\n+\tpe_mask &= 0x2FF;  /*Exclude Util + TMU2 */\n+\n+\tfor (i = 0; i < MAX_PE; i++)\n+\t\tif (pe_mask & (1 << i)) {\n+\t\t\tmbox = (void *)ctrl->sync_mailbox_baseaddr[i];\n+\n+\t\t\tpe_dmem_write(i, cpu_to_be32(0x1), (unsigned\n+\t\t\t\t\tlong)&mbox->stop, 4);\n+\t\t}\n+\n+\twhile (pe_stopped != pe_mask) {\n+\t\tfor (i = 0; i < MAX_PE; i++)\n+\t\t\tif ((pe_mask & (1 << i)) && !(pe_stopped & (1 << i))) {\n+\t\t\t\tmbox = (void *)ctrl->sync_mailbox_baseaddr[i];\n+\n+\t\t\t\tif (pe_dmem_read(i, (unsigned\n+\t\t\t\t\tlong)&mbox->stopped, 4) &\n+\t\t\t\t\tcpu_to_be32(0x1))\n+\t\t\t\t\tpe_stopped |= (1 << i);\n+\t\t\t}\n+\n+\t\tif (relax(end) < 0)\n+\t\t\tgoto err;\n+\t}\n+\n+\treturn 0;\n+\n+err:\n+\tpr_err(\"%s: timeout, %x %x\\n\", __func__, pe_mask, pe_stopped);\n+\n+\tfor (i = 0; i < MAX_PE; i++)\n+\t\tif (pe_mask & (1 << i)) {\n+\t\t\tmbox = (void *)ctrl->sync_mailbox_baseaddr[i];\n+\n+\t\t\tpe_dmem_write(i, cpu_to_be32(0x0), (unsigned\n+\t\t\t\t\tlong)&mbox->stop, 4);\n+\t}\n+\n+\treturn -EIO;\n+}\n+\n+/* PE start.\n+ * Starts packet processing for a list of PE's (specified using a bitmask).\n+ * The caller must hold ctrl->mutex.\n+ *\n+ * @param ctrl\t\tControl context\n+ * @param pe_mask\tMask of PE id's to start\n+ *\n+ */\n+void pe_start(struct pfe_ctrl *ctrl, int pe_mask)\n+{\n+\tstruct pe_sync_mailbox *mbox;\n+\tint i;\n+\n+\tfor (i = 0; i < MAX_PE; i++)\n+\t\tif (pe_mask & (1 << i)) {\n+\t\t\tmbox = (void *)ctrl->sync_mailbox_baseaddr[i];\n+\n+\t\t\tpe_dmem_write(i, cpu_to_be32(0x0), (unsigned\n+\t\t\t\t\tlong)&mbox->stop, 4);\n+\t\t}\n+}\n+\n+/* This function will ensure all PEs are put in to idle state */\n+int pe_reset_all(struct pfe_ctrl *ctrl)\n+{\n+\tstruct pe_sync_mailbox *mbox;\n+\tint pe_stopped = 0;\n+\tunsigned long end = jiffies + 2;\n+\tint i;\n+\tint pe_mask  = CLASS_MASK | TMU_MASK;\n+\n+#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)\n+\tpe_mask |= UTIL_MASK;\n+#endif\n+\n+\tfor (i = 0; i < MAX_PE; i++)\n+\t\tif (pe_mask & (1 << i)) {\n+\t\t\tmbox = (void *)ctrl->sync_mailbox_baseaddr[i];\n+\n+\t\t\tpe_dmem_write(i, cpu_to_be32(0x2), (unsigned\n+\t\t\t\t\tlong)&mbox->stop, 4);\n+\t\t}\n+\n+\twhile (pe_stopped != pe_mask) {\n+\t\tfor (i = 0; i < MAX_PE; i++)\n+\t\t\tif ((pe_mask & (1 << i)) && !(pe_stopped & (1 << i))) {\n+\t\t\t\tmbox = (void *)ctrl->sync_mailbox_baseaddr[i];\n+\n+\t\t\t\tif (pe_dmem_read(i, (unsigned long)\n+\t\t\t\t\t\t\t&mbox->stopped, 4) &\n+\t\t\t\t\t\tcpu_to_be32(0x1))\n+\t\t\t\t\tpe_stopped |= (1 << i);\n+\t\t\t}\n+\n+\t\tif (relax(end) < 0)\n+\t\t\tgoto err;\n+\t}\n+\n+\treturn 0;\n+\n+err:\n+\tpr_err(\"%s: timeout, %x %x\\n\", __func__, pe_mask, pe_stopped);\n+\treturn -EIO;\n+}\n+\n+int pfe_ctrl_init(struct pfe *pfe)\n+{\n+\tstruct pfe_ctrl *ctrl = &pfe->ctrl;\n+\tint id;\n+\n+\tpr_info(\"%s\\n\", __func__);\n+\n+\tmutex_init(&ctrl->mutex);\n+\tspin_lock_init(&ctrl->lock);\n+\n+\tfor (id = CLASS0_ID; id <= CLASS_MAX_ID; id++) {\n+\t\tctrl->sync_mailbox_baseaddr[id] = CLASS_DM_SYNC_MBOX;\n+\t\tctrl->msg_mailbox_baseaddr[id] = CLASS_DM_MSG_MBOX;\n+\t}\n+\n+\tfor (id = TMU0_ID; id <= TMU_MAX_ID; id++) {\n+\t\tif (id == TMU2_ID)\n+\t\t\tcontinue;\n+\t\tctrl->sync_mailbox_baseaddr[id] = TMU_DM_SYNC_MBOX;\n+\t\tctrl->msg_mailbox_baseaddr[id] = TMU_DM_MSG_MBOX;\n+\t}\n+\n+#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)\n+\tctrl->sync_mailbox_baseaddr[UTIL_ID] = UTIL_DM_SYNC_MBOX;\n+\tctrl->msg_mailbox_baseaddr[UTIL_ID] = UTIL_DM_MSG_MBOX;\n+#endif\n+\n+\tctrl->hash_array_baseaddr = pfe->ddr_baseaddr + ROUTE_TABLE_BASEADDR;\n+\tctrl->hash_array_phys_baseaddr = pfe->ddr_phys_baseaddr +\n+\t\t\t\t\t\tROUTE_TABLE_BASEADDR;\n+\n+\tctrl->dev = pfe->dev;\n+\n+\tpr_info(\"%s finished\\n\", __func__);\n+\n+\treturn 0;\n+}\n+\n+void pfe_ctrl_exit(struct pfe *pfe)\n+{\n+\tpr_info(\"%s\\n\", __func__);\n+}\n--- /dev/null\n+++ b/drivers/staging/fsl_ppfe/pfe_ctrl.h\n@@ -0,0 +1,100 @@\n+/* SPDX-License-Identifier: GPL-2.0+ */\n+/*\n+ * Copyright 2015-2016 Freescale Semiconductor, Inc.\n+ * Copyright 2017 NXP\n+ */\n+\n+#ifndef _PFE_CTRL_H_\n+#define _PFE_CTRL_H_\n+\n+#include <linux/dmapool.h>\n+\n+#include \"pfe/pfe.h\"\n+\n+#define DMA_BUF_SIZE_128\t0x80\t/* enough for 1 conntracks */\n+#define DMA_BUF_SIZE_256\t0x100\n+/* enough for 2 conntracks, 1 bridge entry or 1 multicast entry */\n+#define DMA_BUF_SIZE_512\t0x200\n+/* 512bytes dma allocated buffers used by rtp relay feature */\n+#define DMA_BUF_MIN_ALIGNMENT\t8\n+#define DMA_BUF_BOUNDARY\t(4 * 1024)\n+/* bursts can not cross 4k boundary */\n+\n+#define CMD_TX_ENABLE\t0x0501\n+#define CMD_TX_DISABLE\t0x0502\n+\n+#define CMD_RX_LRO\t\t0x0011\n+#define CMD_PKTCAP_ENABLE       0x0d01\n+#define CMD_QM_EXPT_RATE\t0x020c\n+\n+#define CLASS_DM_SH_STATIC\t\t(0x800)\n+#define CLASS_DM_CPU_TICKS\t\t(CLASS_DM_SH_STATIC)\n+#define CLASS_DM_SYNC_MBOX\t\t(0x808)\n+#define CLASS_DM_MSG_MBOX\t\t(0x810)\n+#define CLASS_DM_DROP_CNTR\t\t(0x820)\n+#define CLASS_DM_RESUME\t\t\t(0x854)\n+#define CLASS_DM_PESTATUS\t\t(0x860)\n+#define CLASS_DM_CRC_VALIDATED\t\t(0x14b0)\n+\n+#define TMU_DM_SH_STATIC\t\t(0x80)\n+#define TMU_DM_CPU_TICKS\t\t(TMU_DM_SH_STATIC)\n+#define TMU_DM_SYNC_MBOX\t\t(0x88)\n+#define TMU_DM_MSG_MBOX\t\t\t(0x90)\n+#define TMU_DM_RESUME\t\t\t(0xA0)\n+#define TMU_DM_PESTATUS\t\t\t(0xB0)\n+#define TMU_DM_CONTEXT\t\t\t(0x300)\n+#define TMU_DM_TX_TRANS\t\t\t(0x480)\n+\n+#define UTIL_DM_SH_STATIC\t\t(0x0)\n+#define UTIL_DM_CPU_TICKS\t\t(UTIL_DM_SH_STATIC)\n+#define UTIL_DM_SYNC_MBOX\t\t(0x8)\n+#define UTIL_DM_MSG_MBOX\t\t(0x10)\n+#define UTIL_DM_DROP_CNTR\t\t(0x20)\n+#define UTIL_DM_RESUME\t\t\t(0x40)\n+#define UTIL_DM_PESTATUS\t\t(0x50)\n+\n+struct pfe_ctrl {\n+\tstruct mutex mutex; /* to serialize pfe control access */\n+\tspinlock_t lock;\n+\n+\tvoid *dma_pool;\n+\tvoid *dma_pool_512;\n+\tvoid *dma_pool_128;\n+\n+\tstruct device *dev;\n+\n+\tvoid *hash_array_baseaddr;\t\t/*\n+\t\t\t\t\t\t * Virtual base address of\n+\t\t\t\t\t\t * the conntrack hash array\n+\t\t\t\t\t\t */\n+\tunsigned long hash_array_phys_baseaddr; /*\n+\t\t\t\t\t\t * Physical base address of\n+\t\t\t\t\t\t * the conntrack hash array\n+\t\t\t\t\t\t */\n+\n+\tint (*event_cb)(u16, u16, u16*);\n+\n+\tunsigned long sync_mailbox_baseaddr[MAX_PE]; /*\n+\t\t\t\t\t\t      * Sync mailbox PFE\n+\t\t\t\t\t\t      * internal address,\n+\t\t\t\t\t\t      * initialized\n+\t\t\t\t\t\t      * when parsing elf images\n+\t\t\t\t\t\t      */\n+\tunsigned long msg_mailbox_baseaddr[MAX_PE]; /*\n+\t\t\t\t\t\t     * Msg mailbox PFE internal\n+\t\t\t\t\t\t     * address, initialized\n+\t\t\t\t\t\t     * when parsing elf images\n+\t\t\t\t\t\t     */\n+\tunsigned int sys_clk;\t\t\t/* AXI clock value, in KHz */\n+};\n+\n+int pfe_ctrl_init(struct pfe *pfe);\n+void pfe_ctrl_exit(struct pfe *pfe);\n+int pe_sync_stop(struct pfe_ctrl *ctrl, int pe_mask);\n+void pe_start(struct pfe_ctrl *ctrl, int pe_mask);\n+int pe_reset_all(struct pfe_ctrl *ctrl);\n+void pfe_ctrl_suspend(struct pfe_ctrl *ctrl);\n+void pfe_ctrl_resume(struct pfe_ctrl *ctrl);\n+int relax(unsigned long end);\n+\n+#endif /* _PFE_CTRL_H_ */\n--- /dev/null\n+++ b/drivers/staging/fsl_ppfe/pfe_debugfs.c\n@@ -0,0 +1,99 @@\n+// SPDX-License-Identifier: GPL-2.0+\n+/*\n+ * Copyright 2015-2016 Freescale Semiconductor, Inc.\n+ * Copyright 2017 NXP\n+ */\n+\n+#include <linux/module.h>\n+#include <linux/debugfs.h>\n+#include <linux/platform_device.h>\n+\n+#include \"pfe_mod.h\"\n+\n+static int dmem_show(struct seq_file *s, void *unused)\n+{\n+\tu32 dmem_addr, val;\n+\tint id = (long int)s->private;\n+\tint i;\n+\n+\tfor (dmem_addr = 0; dmem_addr < CLASS_DMEM_SIZE; dmem_addr += 8 * 4) {\n+\t\tseq_printf(s, \"%04x:\", dmem_addr);\n+\n+\t\tfor (i = 0; i < 8; i++) {\n+\t\t\tval = pe_dmem_read(id, dmem_addr + i * 4, 4);\n+\t\t\tseq_printf(s, \" %02x %02x %02x %02x\", val & 0xff,\n+\t\t\t\t   (val >> 8) & 0xff, (val >> 16) & 0xff,\n+\t\t\t\t   (val >> 24) & 0xff);\n+\t\t}\n+\n+\t\tseq_puts(s, \"\\n\");\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int dmem_open(struct inode *inode, struct file *file)\n+{\n+\treturn single_open(file, dmem_show, inode->i_private);\n+}\n+\n+static const struct file_operations dmem_fops = {\n+\t.open\t\t= dmem_open,\n+\t.read\t\t= seq_read,\n+\t.llseek\t\t= seq_lseek,\n+\t.release\t= single_release,\n+};\n+\n+int pfe_debugfs_init(struct pfe *pfe)\n+{\n+\tstruct dentry *d;\n+\n+\tpr_info(\"%s\\n\", __func__);\n+\n+\tpfe->dentry = debugfs_create_dir(\"pfe\", NULL);\n+\tif (IS_ERR_OR_NULL(pfe->dentry))\n+\t\tgoto err_dir;\n+\n+\td = debugfs_create_file(\"pe0_dmem\", 0444, pfe->dentry, (void *)0,\n+\t\t\t\t&dmem_fops);\n+\tif (IS_ERR_OR_NULL(d))\n+\t\tgoto err_pe;\n+\n+\td = debugfs_create_file(\"pe1_dmem\", 0444, pfe->dentry, (void *)1,\n+\t\t\t\t&dmem_fops);\n+\tif (IS_ERR_OR_NULL(d))\n+\t\tgoto err_pe;\n+\n+\td = debugfs_create_file(\"pe2_dmem\", 0444, pfe->dentry, (void *)2,\n+\t\t\t\t&dmem_fops);\n+\tif (IS_ERR_OR_NULL(d))\n+\t\tgoto err_pe;\n+\n+\td = debugfs_create_file(\"pe3_dmem\", 0444, pfe->dentry, (void *)3,\n+\t\t\t\t&dmem_fops);\n+\tif (IS_ERR_OR_NULL(d))\n+\t\tgoto err_pe;\n+\n+\td = debugfs_create_file(\"pe4_dmem\", 0444, pfe->dentry, (void *)4,\n+\t\t\t\t&dmem_fops);\n+\tif (IS_ERR_OR_NULL(d))\n+\t\tgoto err_pe;\n+\n+\td = debugfs_create_file(\"pe5_dmem\", 0444, pfe->dentry, (void *)5,\n+\t\t\t\t&dmem_fops);\n+\tif (IS_ERR_OR_NULL(d))\n+\t\tgoto err_pe;\n+\n+\treturn 0;\n+\n+err_pe:\n+\tdebugfs_remove_recursive(pfe->dentry);\n+\n+err_dir:\n+\treturn -1;\n+}\n+\n+void pfe_debugfs_exit(struct pfe *pfe)\n+{\n+\tdebugfs_remove_recursive(pfe->dentry);\n+}\n--- /dev/null\n+++ b/drivers/staging/fsl_ppfe/pfe_debugfs.h\n@@ -0,0 +1,13 @@\n+/* SPDX-License-Identifier: GPL-2.0+ */\n+/*\n+ * Copyright 2015-2016 Freescale Semiconductor, Inc.\n+ * Copyright 2017 NXP\n+ */\n+\n+#ifndef _PFE_DEBUGFS_H_\n+#define _PFE_DEBUGFS_H_\n+\n+int pfe_debugfs_init(struct pfe *pfe);\n+void pfe_debugfs_exit(struct pfe *pfe);\n+\n+#endif /* _PFE_DEBUGFS_H_ */\n--- /dev/null\n+++ b/drivers/staging/fsl_ppfe/pfe_eth.c\n@@ -0,0 +1,2587 @@\n+// SPDX-License-Identifier: GPL-2.0+\n+/*\n+ * Copyright 2015-2016 Freescale Semiconductor, Inc.\n+ * Copyright 2017 NXP\n+ */\n+\n+/* @pfe_eth.c.\n+ *  Ethernet driver for to handle exception path for PFE.\n+ *  - uses HIF functions to send/receive packets.\n+ *  - uses ctrl function to start/stop interfaces.\n+ *  - uses direct register accesses to control phy operation.\n+ */\n+#include <linux/version.h>\n+#include <linux/kernel.h>\n+#include <linux/interrupt.h>\n+#include <linux/dma-mapping.h>\n+#include <linux/dmapool.h>\n+#include <linux/netdevice.h>\n+#include <linux/etherdevice.h>\n+#include <linux/ethtool.h>\n+#include <linux/mii.h>\n+#include <linux/phy.h>\n+#include <linux/timer.h>\n+#include <linux/hrtimer.h>\n+#include <linux/platform_device.h>\n+\n+#include <net/ip.h>\n+#include <net/sock.h>\n+\n+#include <linux/of.h>\n+#include <linux/of_mdio.h>\n+\n+#include <linux/io.h>\n+#include <asm/irq.h>\n+#include <linux/delay.h>\n+#include <linux/regmap.h>\n+#include <linux/i2c.h>\n+#include <linux/sys_soc.h>\n+\n+#if defined(CONFIG_NF_CONNTRACK_MARK)\n+#include <net/netfilter/nf_conntrack.h>\n+#endif\n+\n+#include \"pfe_mod.h\"\n+#include \"pfe_eth.h\"\n+#include \"pfe_cdev.h\"\n+\n+#define LS1012A_REV_1_0\t\t0x87040010\n+\n+bool pfe_use_old_dts_phy;\n+bool pfe_errata_a010897;\n+\n+static void *cbus_emac_base[3];\n+static void *cbus_gpi_base[3];\n+\n+/* Forward Declaration */\n+static void pfe_eth_exit_one(struct pfe_eth_priv_s *priv);\n+static void pfe_eth_flush_tx(struct pfe_eth_priv_s *priv);\n+static void pfe_eth_flush_txQ(struct pfe_eth_priv_s *priv, int tx_q_num, int\n+\t\t\t\tfrom_tx, int n_desc);\n+\n+/* MDIO registers */\n+#define MDIO_SGMII_CR\t\t\t0x00\n+#define MDIO_SGMII_SR\t\t\t0x01\n+#define MDIO_SGMII_DEV_ABIL_SGMII\t0x04\n+#define MDIO_SGMII_LINK_TMR_L\t\t0x12\n+#define MDIO_SGMII_LINK_TMR_H\t\t0x13\n+#define MDIO_SGMII_IF_MODE\t\t0x14\n+\n+/* SGMII Control defines */\n+#define SGMII_CR_RST\t\t\t0x8000\n+#define SGMII_CR_AN_EN\t\t\t0x1000\n+#define SGMII_CR_RESTART_AN\t\t0x0200\n+#define SGMII_CR_FD\t\t\t0x0100\n+#define SGMII_CR_SPEED_SEL1_1G\t\t0x0040\n+#define SGMII_CR_DEF_VAL\t\t(SGMII_CR_AN_EN | SGMII_CR_FD | \\\n+\t\t\t\t\t SGMII_CR_SPEED_SEL1_1G)\n+\n+/* SGMII IF Mode */\n+#define SGMII_DUPLEX_HALF\t\t0x10\n+#define SGMII_SPEED_10MBPS\t\t0x00\n+#define SGMII_SPEED_100MBPS\t\t0x04\n+#define SGMII_SPEED_1GBPS\t\t0x08\n+#define SGMII_USE_SGMII_AN\t\t0x02\n+#define SGMII_EN\t\t\t0x01\n+\n+/* SGMII Device Ability for SGMII */\n+#define SGMII_DEV_ABIL_ACK\t\t0x4000\n+#define SGMII_DEV_ABIL_EEE_CLK_STP_EN\t0x0100\n+#define SGMII_DEV_ABIL_SGMII\t\t0x0001\n+\n+unsigned int gemac_regs[] = {\n+\t0x0004, /* Interrupt event */\n+\t0x0008, /* Interrupt mask */\n+\t0x0024, /* Ethernet control */\n+\t0x0064, /* MIB Control/Status */\n+\t0x0084, /* Receive control/status */\n+\t0x00C4, /* Transmit control */\n+\t0x00E4, /* Physical address low */\n+\t0x00E8, /* Physical address high */\n+\t0x0144, /* Transmit FIFO Watermark and Store and Forward Control*/\n+\t0x0190, /* Receive FIFO Section Full Threshold */\n+\t0x01A0, /* Transmit FIFO Section Empty Threshold */\n+\t0x01B0, /* Frame Truncation Length */\n+};\n+\n+const struct soc_device_attribute ls1012a_rev1_soc_attr[] = {\n+\t{ .family = \"QorIQ LS1012A\",\n+\t  .soc_id = \"svr:0x87040010\",\n+\t  .revision = \"1.0\",\n+\t  .data = NULL },\n+\t{ },\n+};\n+\n+/********************************************************************/\n+/*                   SYSFS INTERFACE\t\t\t\t    */\n+/********************************************************************/\n+\n+#ifdef PFE_ETH_NAPI_STATS\n+/*\n+ * pfe_eth_show_napi_stats\n+ */\n+static ssize_t pfe_eth_show_napi_stats(struct device *dev,\n+\t\t\t\t       struct device_attribute *attr,\n+\t\t\t\t       char *buf)\n+{\n+\tstruct pfe_eth_priv_s *priv = netdev_priv(to_net_dev(dev));\n+\tssize_t len = 0;\n+\n+\tlen += sprintf(buf + len, \"sched:  %u\\n\",\n+\t\t\tpriv->napi_counters[NAPI_SCHED_COUNT]);\n+\tlen += sprintf(buf + len, \"poll:   %u\\n\",\n+\t\t\tpriv->napi_counters[NAPI_POLL_COUNT]);\n+\tlen += sprintf(buf + len, \"packet: %u\\n\",\n+\t\t\tpriv->napi_counters[NAPI_PACKET_COUNT]);\n+\tlen += sprintf(buf + len, \"budget: %u\\n\",\n+\t\t\tpriv->napi_counters[NAPI_FULL_BUDGET_COUNT]);\n+\tlen += sprintf(buf + len, \"desc:   %u\\n\",\n+\t\t\tpriv->napi_counters[NAPI_DESC_COUNT]);\n+\n+\treturn len;\n+}\n+\n+/*\n+ * pfe_eth_set_napi_stats\n+ */\n+static ssize_t pfe_eth_set_napi_stats(struct device *dev,\n+\t\t\t\t      struct device_attribute *attr,\n+\t\t\t\t      const char *buf, size_t count)\n+{\n+\tstruct pfe_eth_priv_s *priv = netdev_priv(to_net_dev(dev));\n+\n+\tmemset(priv->napi_counters, 0, sizeof(priv->napi_counters));\n+\n+\treturn count;\n+}\n+#endif\n+#ifdef PFE_ETH_TX_STATS\n+/* pfe_eth_show_tx_stats\n+ *\n+ */\n+static ssize_t pfe_eth_show_tx_stats(struct device *dev,\n+\t\t\t\t     struct device_attribute *attr,\n+\t\t\t\t     char *buf)\n+{\n+\tstruct pfe_eth_priv_s *priv = netdev_priv(to_net_dev(dev));\n+\tssize_t len = 0;\n+\tint i;\n+\n+\tlen += sprintf(buf + len, \"TX queues stats:\\n\");\n+\n+\tfor (i = 0; i < emac_txq_cnt; i++) {\n+\t\tstruct netdev_queue *tx_queue = netdev_get_tx_queue(priv->ndev,\n+\t\t\t\t\t\t\t\t\ti);\n+\n+\t\tlen += sprintf(buf + len, \"\\n\");\n+\t\t__netif_tx_lock_bh(tx_queue);\n+\n+\t\thif_tx_lock(&pfe->hif);\n+\t\tlen += sprintf(buf + len,\n+\t\t\t\t\"Queue %2d :  credits               = %10d\\n\"\n+\t\t\t\t, i, hif_lib_tx_credit_avail(pfe, priv->id, i));\n+\t\tlen += sprintf(buf + len,\n+\t\t\t\t \"            tx packets            = %10d\\n\"\n+\t\t\t\t,  pfe->tmu_credit.tx_packets[priv->id][i]);\n+\t\thif_tx_unlock(&pfe->hif);\n+\n+\t\t/* Don't output additionnal stats if queue never used */\n+\t\tif (!pfe->tmu_credit.tx_packets[priv->id][i])\n+\t\t\tgoto skip;\n+\n+\t\tlen += sprintf(buf + len,\n+\t\t\t\t \"            clean_fail            = %10d\\n\"\n+\t\t\t\t, priv->clean_fail[i]);\n+\t\tlen += sprintf(buf + len,\n+\t\t\t\t \"            stop_queue            = %10d\\n\"\n+\t\t\t\t, priv->stop_queue_total[i]);\n+\t\tlen += sprintf(buf + len,\n+\t\t\t\t \"            stop_queue_hif        = %10d\\n\"\n+\t\t\t\t, priv->stop_queue_hif[i]);\n+\t\tlen += sprintf(buf + len,\n+\t\t\t\t\"            stop_queue_hif_client = %10d\\n\"\n+\t\t\t\t, priv->stop_queue_hif_client[i]);\n+\t\tlen += sprintf(buf + len,\n+\t\t\t\t \"            stop_queue_credit     = %10d\\n\"\n+\t\t\t\t, priv->stop_queue_credit[i]);\n+skip:\n+\t\t__netif_tx_unlock_bh(tx_queue);\n+\t}\n+\treturn len;\n+}\n+\n+/* pfe_eth_set_tx_stats\n+ *\n+ */\n+static ssize_t pfe_eth_set_tx_stats(struct device *dev,\n+\t\t\t\t    struct device_attribute *attr,\n+\t\t\t\t    const char *buf, size_t count)\n+{\n+\tstruct pfe_eth_priv_s *priv = netdev_priv(to_net_dev(dev));\n+\tint i;\n+\n+\tfor (i = 0; i < emac_txq_cnt; i++) {\n+\t\tstruct netdev_queue *tx_queue = netdev_get_tx_queue(priv->ndev,\n+\t\t\t\t\t\t\t\t\ti);\n+\n+\t\t__netif_tx_lock_bh(tx_queue);\n+\t\tpriv->clean_fail[i] = 0;\n+\t\tpriv->stop_queue_total[i] = 0;\n+\t\tpriv->stop_queue_hif[i] = 0;\n+\t\tpriv->stop_queue_hif_client[i] = 0;\n+\t\tpriv->stop_queue_credit[i] = 0;\n+\t\t__netif_tx_unlock_bh(tx_queue);\n+\t}\n+\n+\treturn count;\n+}\n+#endif\n+/* pfe_eth_show_txavail\n+ *\n+ */\n+static ssize_t pfe_eth_show_txavail(struct device *dev,\n+\t\t\t\t    struct device_attribute *attr,\n+\t\t\t\t    char *buf)\n+{\n+\tstruct pfe_eth_priv_s *priv = netdev_priv(to_net_dev(dev));\n+\tssize_t len = 0;\n+\tint i;\n+\n+\tfor (i = 0; i < emac_txq_cnt; i++) {\n+\t\tstruct netdev_queue *tx_queue = netdev_get_tx_queue(priv->ndev,\n+\t\t\t\t\t\t\t\t\ti);\n+\n+\t\t__netif_tx_lock_bh(tx_queue);\n+\n+\t\tlen += sprintf(buf + len, \"%d\",\n+\t\t\t\thif_lib_tx_avail(&priv->client, i));\n+\n+\t\t__netif_tx_unlock_bh(tx_queue);\n+\n+\t\tif (i == (emac_txq_cnt - 1))\n+\t\t\tlen += sprintf(buf + len, \"\\n\");\n+\t\telse\n+\t\t\tlen += sprintf(buf + len, \" \");\n+\t}\n+\n+\treturn len;\n+}\n+\n+/* pfe_eth_show_default_priority\n+ *\n+ */\n+static ssize_t pfe_eth_show_default_priority(struct device *dev,\n+\t\t\t\t\t     struct device_attribute *attr,\n+\t\t\t\t\t\tchar *buf)\n+{\n+\tstruct pfe_eth_priv_s *priv = netdev_priv(to_net_dev(dev));\n+\tunsigned long flags;\n+\tint rc;\n+\n+\tspin_lock_irqsave(&priv->lock, flags);\n+\trc = sprintf(buf, \"%d\\n\", priv->default_priority);\n+\tspin_unlock_irqrestore(&priv->lock, flags);\n+\n+\treturn rc;\n+}\n+\n+/* pfe_eth_set_default_priority\n+ *\n+ */\n+\n+static ssize_t pfe_eth_set_default_priority(struct device *dev,\n+\t\t\t\t\t    struct device_attribute *attr,\n+\t\t\t\t\t    const char *buf, size_t count)\n+{\n+\tstruct pfe_eth_priv_s *priv = netdev_priv(to_net_dev(dev));\n+\tunsigned long flags;\n+\n+\tspin_lock_irqsave(&priv->lock, flags);\n+\tpriv->default_priority = kstrtoul(buf, 0, 0);\n+\tspin_unlock_irqrestore(&priv->lock, flags);\n+\n+\treturn count;\n+}\n+\n+static DEVICE_ATTR(txavail, 0444, pfe_eth_show_txavail, NULL);\n+static DEVICE_ATTR(default_priority, 0644, pfe_eth_show_default_priority,\n+\t\t\tpfe_eth_set_default_priority);\n+\n+#ifdef PFE_ETH_NAPI_STATS\n+static DEVICE_ATTR(napi_stats, 0644, pfe_eth_show_napi_stats,\n+\t\t\tpfe_eth_set_napi_stats);\n+#endif\n+\n+#ifdef PFE_ETH_TX_STATS\n+static DEVICE_ATTR(tx_stats, 0644, pfe_eth_show_tx_stats,\n+\t\t\tpfe_eth_set_tx_stats);\n+#endif\n+\n+/*\n+ * pfe_eth_sysfs_init\n+ *\n+ */\n+static int pfe_eth_sysfs_init(struct net_device *ndev)\n+{\n+\tstruct pfe_eth_priv_s *priv = netdev_priv(ndev);\n+\tint err;\n+\n+\t/* Initialize the default values */\n+\n+\t/*\n+\t * By default, packets without conntrack will use this default low\n+\t * priority queue\n+\t */\n+\tpriv->default_priority = 0;\n+\n+\t/* Create our sysfs files */\n+\terr = device_create_file(&ndev->dev, &dev_attr_default_priority);\n+\tif (err) {\n+\t\tnetdev_err(ndev,\n+\t\t\t   \"failed to create default_priority sysfs files\\n\");\n+\t\tgoto err_priority;\n+\t}\n+\n+\terr = device_create_file(&ndev->dev, &dev_attr_txavail);\n+\tif (err) {\n+\t\tnetdev_err(ndev,\n+\t\t\t   \"failed to create default_priority sysfs files\\n\");\n+\t\tgoto err_txavail;\n+\t}\n+\n+#ifdef PFE_ETH_NAPI_STATS\n+\terr = device_create_file(&ndev->dev, &dev_attr_napi_stats);\n+\tif (err) {\n+\t\tnetdev_err(ndev, \"failed to create napi stats sysfs files\\n\");\n+\t\tgoto err_napi;\n+\t}\n+#endif\n+\n+#ifdef PFE_ETH_TX_STATS\n+\terr = device_create_file(&ndev->dev, &dev_attr_tx_stats);\n+\tif (err) {\n+\t\tnetdev_err(ndev, \"failed to create tx stats sysfs files\\n\");\n+\t\tgoto err_tx;\n+\t}\n+#endif\n+\n+\treturn 0;\n+\n+#ifdef PFE_ETH_TX_STATS\n+err_tx:\n+#endif\n+#ifdef PFE_ETH_NAPI_STATS\n+\tdevice_remove_file(&ndev->dev, &dev_attr_napi_stats);\n+\n+err_napi:\n+#endif\n+\tdevice_remove_file(&ndev->dev, &dev_attr_txavail);\n+\n+err_txavail:\n+\tdevice_remove_file(&ndev->dev, &dev_attr_default_priority);\n+\n+err_priority:\n+\treturn -1;\n+}\n+\n+/* pfe_eth_sysfs_exit\n+ *\n+ */\n+void pfe_eth_sysfs_exit(struct net_device *ndev)\n+{\n+#ifdef PFE_ETH_TX_STATS\n+\tdevice_remove_file(&ndev->dev, &dev_attr_tx_stats);\n+#endif\n+\n+#ifdef PFE_ETH_NAPI_STATS\n+\tdevice_remove_file(&ndev->dev, &dev_attr_napi_stats);\n+#endif\n+\tdevice_remove_file(&ndev->dev, &dev_attr_txavail);\n+\tdevice_remove_file(&ndev->dev, &dev_attr_default_priority);\n+}\n+\n+/*************************************************************************/\n+/*\t\tETHTOOL INTERCAE\t\t\t\t\t */\n+/*************************************************************************/\n+\n+/*MTIP GEMAC */\n+static const struct fec_stat {\n+\tchar name[ETH_GSTRING_LEN];\n+\tu16 offset;\n+} fec_stats[] = {\n+\t/* RMON TX */\n+\t{ \"tx_dropped\", RMON_T_DROP },\n+\t{ \"tx_packets\", RMON_T_PACKETS },\n+\t{ \"tx_broadcast\", RMON_T_BC_PKT },\n+\t{ \"tx_multicast\", RMON_T_MC_PKT },\n+\t{ \"tx_crc_errors\", RMON_T_CRC_ALIGN },\n+\t{ \"tx_undersize\", RMON_T_UNDERSIZE },\n+\t{ \"tx_oversize\", RMON_T_OVERSIZE },\n+\t{ \"tx_fragment\", RMON_T_FRAG },\n+\t{ \"tx_jabber\", RMON_T_JAB },\n+\t{ \"tx_collision\", RMON_T_COL },\n+\t{ \"tx_64byte\", RMON_T_P64 },\n+\t{ \"tx_65to127byte\", RMON_T_P65TO127 },\n+\t{ \"tx_128to255byte\", RMON_T_P128TO255 },\n+\t{ \"tx_256to511byte\", RMON_T_P256TO511 },\n+\t{ \"tx_512to1023byte\", RMON_T_P512TO1023 },\n+\t{ \"tx_1024to2047byte\", RMON_T_P1024TO2047 },\n+\t{ \"tx_GTE2048byte\", RMON_T_P_GTE2048 },\n+\t{ \"tx_octets\", RMON_T_OCTETS },\n+\n+\t/* IEEE TX */\n+\t{ \"IEEE_tx_drop\", IEEE_T_DROP },\n+\t{ \"IEEE_tx_frame_ok\", IEEE_T_FRAME_OK },\n+\t{ \"IEEE_tx_1col\", IEEE_T_1COL },\n+\t{ \"IEEE_tx_mcol\", IEEE_T_MCOL },\n+\t{ \"IEEE_tx_def\", IEEE_T_DEF },\n+\t{ \"IEEE_tx_lcol\", IEEE_T_LCOL },\n+\t{ \"IEEE_tx_excol\", IEEE_T_EXCOL },\n+\t{ \"IEEE_tx_macerr\", IEEE_T_MACERR },\n+\t{ \"IEEE_tx_cserr\", IEEE_T_CSERR },\n+\t{ \"IEEE_tx_sqe\", IEEE_T_SQE },\n+\t{ \"IEEE_tx_fdxfc\", IEEE_T_FDXFC },\n+\t{ \"IEEE_tx_octets_ok\", IEEE_T_OCTETS_OK },\n+\n+\t/* RMON RX */\n+\t{ \"rx_packets\", RMON_R_PACKETS },\n+\t{ \"rx_broadcast\", RMON_R_BC_PKT },\n+\t{ \"rx_multicast\", RMON_R_MC_PKT },\n+\t{ \"rx_crc_errors\", RMON_R_CRC_ALIGN },\n+\t{ \"rx_undersize\", RMON_R_UNDERSIZE },\n+\t{ \"rx_oversize\", RMON_R_OVERSIZE },\n+\t{ \"rx_fragment\", RMON_R_FRAG },\n+\t{ \"rx_jabber\", RMON_R_JAB },\n+\t{ \"rx_64byte\", RMON_R_P64 },\n+\t{ \"rx_65to127byte\", RMON_R_P65TO127 },\n+\t{ \"rx_128to255byte\", RMON_R_P128TO255 },\n+\t{ \"rx_256to511byte\", RMON_R_P256TO511 },\n+\t{ \"rx_512to1023byte\", RMON_R_P512TO1023 },\n+\t{ \"rx_1024to2047byte\", RMON_R_P1024TO2047 },\n+\t{ \"rx_GTE2048byte\", RMON_R_P_GTE2048 },\n+\t{ \"rx_octets\", RMON_R_OCTETS },\n+\n+\t/* IEEE RX */\n+\t{ \"IEEE_rx_drop\", IEEE_R_DROP },\n+\t{ \"IEEE_rx_frame_ok\", IEEE_R_FRAME_OK },\n+\t{ \"IEEE_rx_crc\", IEEE_R_CRC },\n+\t{ \"IEEE_rx_align\", IEEE_R_ALIGN },\n+\t{ \"IEEE_rx_macerr\", IEEE_R_MACERR },\n+\t{ \"IEEE_rx_fdxfc\", IEEE_R_FDXFC },\n+\t{ \"IEEE_rx_octets_ok\", IEEE_R_OCTETS_OK },\n+};\n+\n+static void pfe_eth_fill_stats(struct net_device *ndev, struct ethtool_stats\n+\t\t\t\t*stats, u64 *data)\n+{\n+\tstruct pfe_eth_priv_s *priv = netdev_priv(ndev);\n+\tint i;\n+\tu64 pfe_crc_validated = 0;\n+\tint id;\n+\n+\tfor (id = CLASS0_ID; id <= CLASS_MAX_ID; id++) {\n+\t\tpfe_crc_validated += be32_to_cpu(pe_dmem_read(id,\n+\t\t\tCLASS_DM_CRC_VALIDATED + (priv->id * 4), 4));\n+\t}\n+\n+\tfor (i = 0; i < ARRAY_SIZE(fec_stats); i++) {\n+\t\tdata[i] = readl(priv->EMAC_baseaddr + fec_stats[i].offset);\n+\n+\t\tif (fec_stats[i].offset == IEEE_R_DROP)\n+\t\t\tdata[i] -= pfe_crc_validated;\n+\t}\n+}\n+\n+static void pfe_eth_gstrings(struct net_device *netdev,\n+\t\t\t     u32 stringset, u8 *data)\n+{\n+\tint i;\n+\n+\tswitch (stringset) {\n+\tcase ETH_SS_STATS:\n+\t\tfor (i = 0; i < ARRAY_SIZE(fec_stats); i++)\n+\t\t\tmemcpy(data + i * ETH_GSTRING_LEN,\n+\t\t\t       fec_stats[i].name, ETH_GSTRING_LEN);\n+\t\tbreak;\n+\t}\n+}\n+\n+static int pfe_eth_stats_count(struct net_device *ndev, int sset)\n+{\n+\tswitch (sset) {\n+\tcase ETH_SS_STATS:\n+\t\treturn ARRAY_SIZE(fec_stats);\n+\tdefault:\n+\t\treturn -EOPNOTSUPP;\n+\t}\n+}\n+\n+/*\n+ * pfe_eth_gemac_reglen - Return the length of the register structure.\n+ *\n+ */\n+static int pfe_eth_gemac_reglen(struct net_device *ndev)\n+{\n+\tpr_info(\"%s()\\n\", __func__);\n+\treturn (sizeof(gemac_regs) / sizeof(u32));\n+}\n+\n+/*\n+ * pfe_eth_gemac_get_regs - Return the gemac register structure.\n+ *\n+ */\n+static void  pfe_eth_gemac_get_regs(struct net_device *ndev, struct ethtool_regs\n+\t\t\t\t\t*regs, void *regbuf)\n+{\n+\tint i;\n+\n+\tstruct pfe_eth_priv_s *priv = netdev_priv(ndev);\n+\tu32 *buf = (u32 *)regbuf;\n+\n+\tpr_info(\"%s()\\n\", __func__);\n+\tfor (i = 0; i < sizeof(gemac_regs) / sizeof(u32); i++)\n+\t\tbuf[i] = readl(priv->EMAC_baseaddr + gemac_regs[i]);\n+}\n+\n+/*\n+ * pfe_eth_set_wol - Set the magic packet option, in WoL register.\n+ *\n+ */\n+static int pfe_eth_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)\n+{\n+\tstruct pfe_eth_priv_s *priv = netdev_priv(ndev);\n+\n+\tif (wol->wolopts & ~WAKE_MAGIC)\n+\t\treturn -EOPNOTSUPP;\n+\n+\t/* for MTIP we store wol->wolopts */\n+\tpriv->wol = wol->wolopts;\n+\n+\tdevice_set_wakeup_enable(&ndev->dev, wol->wolopts & WAKE_MAGIC);\n+\n+\treturn 0;\n+}\n+\n+/*\n+ *\n+ * pfe_eth_get_wol - Get the WoL options.\n+ *\n+ */\n+static void pfe_eth_get_wol(struct net_device *ndev, struct ethtool_wolinfo\n+\t\t\t\t*wol)\n+{\n+\tstruct pfe_eth_priv_s *priv = netdev_priv(ndev);\n+\n+\twol->supported = WAKE_MAGIC;\n+\twol->wolopts = 0;\n+\n+\tif (priv->wol & WAKE_MAGIC)\n+\t\twol->wolopts = WAKE_MAGIC;\n+\n+\tmemset(&wol->sopass, 0, sizeof(wol->sopass));\n+}\n+\n+/*\n+ * pfe_eth_get_drvinfo -  Fills in the drvinfo structure with some basic info\n+ *\n+ */\n+static void pfe_eth_get_drvinfo(struct net_device *ndev, struct ethtool_drvinfo\n+\t\t\t\t*drvinfo)\n+{\n+\tstrlcpy(drvinfo->driver, DRV_NAME, sizeof(drvinfo->driver));\n+\tstrlcpy(drvinfo->version, DRV_VERSION, sizeof(drvinfo->version));\n+\tstrlcpy(drvinfo->fw_version, \"N/A\", sizeof(drvinfo->fw_version));\n+\tstrlcpy(drvinfo->bus_info, \"N/A\", sizeof(drvinfo->bus_info));\n+}\n+\n+/*\n+ * pfe_eth_set_settings - Used to send commands to PHY.\n+ *\n+ */\n+static int pfe_eth_set_settings(struct net_device *ndev,\n+\t\t\t\tconst struct ethtool_link_ksettings *cmd)\n+{\n+\tstruct pfe_eth_priv_s *priv = netdev_priv(ndev);\n+\tstruct phy_device *phydev = priv->phydev;\n+\n+\tif (!phydev)\n+\t\treturn -ENODEV;\n+\n+\treturn phy_ethtool_ksettings_set(phydev, cmd);\n+}\n+\n+/*\n+ * pfe_eth_getsettings - Return the current settings in the ethtool_cmd\n+ * structure.\n+ *\n+ */\n+static int pfe_eth_get_settings(struct net_device *ndev,\n+\t\t\t\tstruct ethtool_link_ksettings *cmd)\n+{\n+\tstruct pfe_eth_priv_s *priv = netdev_priv(ndev);\n+\tstruct phy_device *phydev = priv->phydev;\n+\n+\tif (!phydev)\n+\t\treturn -ENODEV;\n+\n+\tphy_ethtool_ksettings_get(phydev, cmd);\n+\n+\treturn 0;\n+}\n+\n+/*\n+ * pfe_eth_get_msglevel - Gets the debug message mask.\n+ *\n+ */\n+static uint32_t pfe_eth_get_msglevel(struct net_device *ndev)\n+{\n+\tstruct pfe_eth_priv_s *priv = netdev_priv(ndev);\n+\n+\treturn priv->msg_enable;\n+}\n+\n+/*\n+ * pfe_eth_set_msglevel - Sets the debug message mask.\n+ *\n+ */\n+static void pfe_eth_set_msglevel(struct net_device *ndev, uint32_t data)\n+{\n+\tstruct pfe_eth_priv_s *priv = netdev_priv(ndev);\n+\n+\tpriv->msg_enable = data;\n+}\n+\n+#define HIF_RX_COAL_MAX_CLKS\t\t(~(1 << 31))\n+#define HIF_RX_COAL_CLKS_PER_USEC\t(pfe->ctrl.sys_clk / 1000)\n+#define HIF_RX_COAL_MAX_USECS\t\t(HIF_RX_COAL_MAX_CLKS\t/ \\\n+\t\t\t\t\t\tHIF_RX_COAL_CLKS_PER_USEC)\n+\n+/*\n+ * pfe_eth_set_coalesce - Sets rx interrupt coalescing timer.\n+ *\n+ */\n+static int pfe_eth_set_coalesce(struct net_device *ndev,\n+\t\t\t\tstruct ethtool_coalesce *ec)\n+{\n+\tif (ec->rx_coalesce_usecs > HIF_RX_COAL_MAX_USECS)\n+\t\treturn -EINVAL;\n+\n+\tif (!ec->rx_coalesce_usecs) {\n+\t\twritel(0, HIF_INT_COAL);\n+\t\treturn 0;\n+\t}\n+\n+\twritel((ec->rx_coalesce_usecs * HIF_RX_COAL_CLKS_PER_USEC) |\n+\t\t\tHIF_INT_COAL_ENABLE, HIF_INT_COAL);\n+\n+\treturn 0;\n+}\n+\n+/*\n+ * pfe_eth_get_coalesce - Gets rx interrupt coalescing timer value.\n+ *\n+ */\n+static int pfe_eth_get_coalesce(struct net_device *ndev,\n+\t\t\t\tstruct ethtool_coalesce *ec)\n+{\n+\tint reg_val = readl(HIF_INT_COAL);\n+\n+\tif (reg_val & HIF_INT_COAL_ENABLE)\n+\t\tec->rx_coalesce_usecs = (reg_val & HIF_RX_COAL_MAX_CLKS) /\n+\t\t\t\t\t\tHIF_RX_COAL_CLKS_PER_USEC;\n+\telse\n+\t\tec->rx_coalesce_usecs = 0;\n+\n+\treturn 0;\n+}\n+\n+/*\n+ * pfe_eth_set_pauseparam - Sets pause parameters\n+ *\n+ */\n+static int pfe_eth_set_pauseparam(struct net_device *ndev,\n+\t\t\t\t  struct ethtool_pauseparam *epause)\n+{\n+\tstruct pfe_eth_priv_s *priv = netdev_priv(ndev);\n+\n+\tif (epause->tx_pause != epause->rx_pause) {\n+\t\tnetdev_info(ndev,\n+\t\t\t    \"hardware only support enable/disable both tx and rx\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tpriv->pause_flag = 0;\n+\tpriv->pause_flag |= epause->rx_pause ? PFE_PAUSE_FLAG_ENABLE : 0;\n+\tpriv->pause_flag |= epause->autoneg ? PFE_PAUSE_FLAG_AUTONEG : 0;\n+\n+\tif (epause->rx_pause || epause->autoneg) {\n+\t\tgemac_enable_pause_rx(priv->EMAC_baseaddr);\n+\t\twritel((readl(priv->GPI_baseaddr + GPI_TX_PAUSE_TIME) |\n+\t\t\t\t\tEGPI_PAUSE_ENABLE),\n+\t\t\t\tpriv->GPI_baseaddr + GPI_TX_PAUSE_TIME);\n+\t\tif (priv->phydev) {\n+\t\t\tlinkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT,\n+\t\t\t\t\t priv->phydev->supported);\n+\t\t\tlinkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT,\n+\t\t\t\t\t priv->phydev->supported);\n+\t\t\tlinkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT,\n+\t\t\t\t\t priv->phydev->advertising);\n+\t\t\tlinkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT,\n+\t\t\t\t\t priv->phydev->advertising);\n+\t\t}\n+\t} else {\n+\t\tgemac_disable_pause_rx(priv->EMAC_baseaddr);\n+\t\twritel((readl(priv->GPI_baseaddr + GPI_TX_PAUSE_TIME) &\n+\t\t\t\t\t~EGPI_PAUSE_ENABLE),\n+\t\t\t\tpriv->GPI_baseaddr + GPI_TX_PAUSE_TIME);\n+\t\tif (priv->phydev) {\n+\t\t\tlinkmode_clear_bit(ETHTOOL_LINK_MODE_Pause_BIT,\n+\t\t\t\t\t   priv->phydev->supported);\n+\t\t\tlinkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT,\n+\t\t\t\t\t   priv->phydev->supported);\n+\t\t\tlinkmode_clear_bit(ETHTOOL_LINK_MODE_Pause_BIT,\n+\t\t\t\t\t   priv->phydev->advertising);\n+\t\t\tlinkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT,\n+\t\t\t\t\t   priv->phydev->advertising);\n+\t\t}\n+\t}\n+\n+\treturn 0;\n+}\n+\n+/*\n+ * pfe_eth_get_pauseparam - Gets pause parameters\n+ *\n+ */\n+static void pfe_eth_get_pauseparam(struct net_device *ndev,\n+\t\t\t\t   struct ethtool_pauseparam *epause)\n+{\n+\tstruct pfe_eth_priv_s *priv = netdev_priv(ndev);\n+\n+\tepause->autoneg = (priv->pause_flag & PFE_PAUSE_FLAG_AUTONEG) != 0;\n+\tepause->tx_pause = (priv->pause_flag & PFE_PAUSE_FLAG_ENABLE) != 0;\n+\tepause->rx_pause = epause->tx_pause;\n+}\n+\n+/*\n+ * pfe_eth_get_hash\n+ */\n+#define PFE_HASH_BITS\t6\t\t/* #bits in hash */\n+#define CRC32_POLY\t0xEDB88320\n+\n+static int pfe_eth_get_hash(u8 *addr)\n+{\n+\tunsigned int i, bit, data, crc, hash;\n+\n+\t/* calculate crc32 value of mac address */\n+\tcrc = 0xffffffff;\n+\n+\tfor (i = 0; i < 6; i++) {\n+\t\tdata = addr[i];\n+\t\tfor (bit = 0; bit < 8; bit++, data >>= 1) {\n+\t\t\tcrc = (crc >> 1) ^\n+\t\t\t\t(((crc ^ data) & 1) ? CRC32_POLY : 0);\n+\t\t}\n+\t}\n+\n+\t/*\n+\t * only upper 6 bits (PFE_HASH_BITS) are used\n+\t * which point to specific bit in the hash registers\n+\t */\n+\thash = (crc >> (32 - PFE_HASH_BITS)) & 0x3f;\n+\n+\treturn hash;\n+}\n+\n+const struct ethtool_ops pfe_ethtool_ops = {\n+\t.supported_coalesce_params = ETHTOOL_COALESCE_RX_USECS,\n+\t.get_drvinfo = pfe_eth_get_drvinfo,\n+\t.get_regs_len = pfe_eth_gemac_reglen,\n+\t.get_regs = pfe_eth_gemac_get_regs,\n+\t.get_link = ethtool_op_get_link,\n+\t.get_wol  = pfe_eth_get_wol,\n+\t.set_wol  = pfe_eth_set_wol,\n+\t.set_pauseparam = pfe_eth_set_pauseparam,\n+\t.get_pauseparam = pfe_eth_get_pauseparam,\n+\t.get_strings = pfe_eth_gstrings,\n+\t.get_sset_count = pfe_eth_stats_count,\n+\t.get_ethtool_stats = pfe_eth_fill_stats,\n+\t.get_msglevel = pfe_eth_get_msglevel,\n+\t.set_msglevel = pfe_eth_set_msglevel,\n+\t.set_coalesce = pfe_eth_set_coalesce,\n+\t.get_coalesce = pfe_eth_get_coalesce,\n+\t.get_link_ksettings = pfe_eth_get_settings,\n+\t.set_link_ksettings = pfe_eth_set_settings,\n+};\n+\n+/* pfe_eth_mdio_reset\n+ */\n+int pfe_eth_mdio_reset(struct mii_bus *bus)\n+{\n+\tstruct pfe_mdio_priv_s *priv = (struct pfe_mdio_priv_s *)bus->priv;\n+\tu32 phy_speed;\n+\n+\n+\tmutex_lock(&bus->mdio_lock);\n+\n+\t/*\n+\t * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed)\n+\t *\n+\t * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while\n+\t * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'.\n+\t */\n+\tphy_speed = (DIV_ROUND_UP((pfe->ctrl.sys_clk * 1000), 4000000)\n+\t\t     << EMAC_MII_SPEED_SHIFT);\n+\tphy_speed |= EMAC_HOLDTIME(0x5);\n+\t__raw_writel(phy_speed, priv->mdio_base + EMAC_MII_CTRL_REG);\n+\n+\tmutex_unlock(&bus->mdio_lock);\n+\n+\treturn 0;\n+}\n+\n+/* pfe_eth_mdio_timeout\n+ *\n+ */\n+static int pfe_eth_mdio_timeout(struct pfe_mdio_priv_s *priv, int timeout)\n+{\n+\twhile (!(__raw_readl(priv->mdio_base + EMAC_IEVENT_REG) &\n+\t\t\tEMAC_IEVENT_MII)) {\n+\t\tif (timeout-- <= 0)\n+\t\t\treturn -1;\n+\t\tusleep_range(10, 20);\n+\t}\n+\t__raw_writel(EMAC_IEVENT_MII, priv->mdio_base + EMAC_IEVENT_REG);\n+\treturn 0;\n+}\n+\n+static int pfe_eth_mdio_mux(u8 muxval)\n+{\n+\tstruct i2c_adapter *a;\n+\tstruct i2c_msg msg;\n+\tunsigned char buf[2];\n+\tint ret;\n+\n+\ta = i2c_get_adapter(0);\n+\tif (!a)\n+\t\treturn -ENODEV;\n+\n+\t/* set bit 1 (the second bit) of chip at 0x09, register 0x13 */\n+\tbuf[0] = 0x54; /* reg number */\n+\tbuf[1] = (muxval << 6) | 0x3; /* data */\n+\tmsg.addr = 0x66;\n+\tmsg.buf = buf;\n+\tmsg.len = 2;\n+\tmsg.flags = 0;\n+\tret = i2c_transfer(a, &msg, 1);\n+\ti2c_put_adapter(a);\n+\tif (ret != 1)\n+\t\treturn -ENODEV;\n+\treturn 0;\n+}\n+\n+static int pfe_eth_mdio_write_addr(struct mii_bus *bus, int mii_id,\n+\t\t\t\t   int dev_addr, int regnum)\n+{\n+\tstruct pfe_mdio_priv_s *priv = (struct pfe_mdio_priv_s *)bus->priv;\n+\n+\t__raw_writel(EMAC_MII_DATA_PA(mii_id) |\n+\t\t     EMAC_MII_DATA_RA(dev_addr) |\n+\t\t     EMAC_MII_DATA_TA | EMAC_MII_DATA(regnum),\n+\t\t     priv->mdio_base + EMAC_MII_DATA_REG);\n+\n+\tif (pfe_eth_mdio_timeout(priv, EMAC_MDIO_TIMEOUT)) {\n+\t\tdev_err(&bus->dev, \"phy MDIO address write timeout\\n\");\n+\t\treturn -1;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int pfe_eth_mdio_write(struct mii_bus *bus, int mii_id, int regnum,\n+\t\t\t      u16 value)\n+{\n+\tstruct pfe_mdio_priv_s *priv = (struct pfe_mdio_priv_s *)bus->priv;\n+\n+\t/*To access external PHYs on QDS board mux needs to be configured*/\n+\tif ((mii_id) && (pfe->mdio_muxval[mii_id]))\n+\t\tpfe_eth_mdio_mux(pfe->mdio_muxval[mii_id]);\n+\n+\tif (regnum & MII_ADDR_C45) {\n+\t\tpfe_eth_mdio_write_addr(bus, mii_id, (regnum >> 16) & 0x1f,\n+\t\t\t\t\tregnum & 0xffff);\n+\t\t__raw_writel(EMAC_MII_DATA_OP_CL45_WR |\n+\t\t\t     EMAC_MII_DATA_PA(mii_id) |\n+\t\t\t     EMAC_MII_DATA_RA((regnum >> 16) & 0x1f) |\n+\t\t\t     EMAC_MII_DATA_TA | EMAC_MII_DATA(value),\n+\t\t\t     priv->mdio_base + EMAC_MII_DATA_REG);\n+\t} else {\n+\t\t/* start a write op */\n+\t\t__raw_writel(EMAC_MII_DATA_ST | EMAC_MII_DATA_OP_WR |\n+\t\t\t     EMAC_MII_DATA_PA(mii_id) |\n+\t\t\t     EMAC_MII_DATA_RA(regnum) |\n+\t\t\t     EMAC_MII_DATA_TA | EMAC_MII_DATA(value),\n+\t\t\t     priv->mdio_base + EMAC_MII_DATA_REG);\n+\t}\n+\n+\tif (pfe_eth_mdio_timeout(priv, EMAC_MDIO_TIMEOUT)) {\n+\t\tdev_err(&bus->dev, \"%s: phy MDIO write timeout\\n\", __func__);\n+\t\treturn -1;\n+\t}\n+\treturn 0;\n+}\n+\n+static int pfe_eth_mdio_read(struct mii_bus *bus, int mii_id, int regnum)\n+{\n+\tstruct pfe_mdio_priv_s *priv = (struct pfe_mdio_priv_s *)bus->priv;\n+\tu16 value = 0;\n+\n+\t/*To access external PHYs on QDS board mux needs to be configured*/\n+\tif ((mii_id) && (pfe->mdio_muxval[mii_id]))\n+\t\tpfe_eth_mdio_mux(pfe->mdio_muxval[mii_id]);\n+\n+\tif (regnum & MII_ADDR_C45) {\n+\t\tpfe_eth_mdio_write_addr(bus, mii_id, (regnum >> 16) & 0x1f,\n+\t\t\t\t\tregnum & 0xffff);\n+\t\t__raw_writel(EMAC_MII_DATA_OP_CL45_RD |\n+\t\t\t     EMAC_MII_DATA_PA(mii_id) |\n+\t\t\t     EMAC_MII_DATA_RA((regnum >> 16) & 0x1f) |\n+\t\t\t     EMAC_MII_DATA_TA,\n+\t\t\t     priv->mdio_base + EMAC_MII_DATA_REG);\n+\t} else {\n+\t\t/* start a read op */\n+\t\t__raw_writel(EMAC_MII_DATA_ST | EMAC_MII_DATA_OP_RD |\n+\t\t\t     EMAC_MII_DATA_PA(mii_id) |\n+\t\t\t     EMAC_MII_DATA_RA(regnum) |\n+\t\t\t     EMAC_MII_DATA_TA, priv->mdio_base +\n+\t\t\t     EMAC_MII_DATA_REG);\n+\t}\n+\n+\tif (pfe_eth_mdio_timeout(priv, EMAC_MDIO_TIMEOUT)) {\n+\t\tdev_err(&bus->dev, \"%s: phy MDIO read timeout\\n\", __func__);\n+\t\treturn -1;\n+\t}\n+\n+\tvalue = EMAC_MII_DATA(__raw_readl(priv->mdio_base +\n+\t\t\t\t\t\tEMAC_MII_DATA_REG));\n+\treturn value;\n+}\n+\n+static int pfe_eth_mdio_init(struct pfe *pfe,\n+\t\t\t     struct ls1012a_pfe_platform_data *pfe_info,\n+\t\t\t     int ii)\n+{\n+\tstruct pfe_mdio_priv_s *priv = NULL;\n+\tstruct ls1012a_mdio_platform_data *mdio_info;\n+\tstruct mii_bus *bus;\n+\tstruct device_node *mdio_node;\n+\tint rc = 0;\n+\n+\tmdio_info = (struct ls1012a_mdio_platform_data *)\n+\t\t\t\t\tpfe_info->ls1012a_mdio_pdata;\n+\tmdio_info->id = ii;\n+\n+\tbus = mdiobus_alloc_size(sizeof(struct pfe_mdio_priv_s));\n+\tif (!bus) {\n+\t\tpr_err(\"mdiobus_alloc() failed\\n\");\n+\t\trc = -ENOMEM;\n+\t\tgoto err_mdioalloc;\n+\t}\n+\n+\tbus->name = \"ls1012a MDIO Bus\";\n+\tsnprintf(bus->id, MII_BUS_ID_SIZE, \"ls1012a-%x\", mdio_info->id);\n+\n+\tbus->read = &pfe_eth_mdio_read;\n+\tbus->write = &pfe_eth_mdio_write;\n+\tbus->reset = &pfe_eth_mdio_reset;\n+\tbus->parent = pfe->dev;\n+\tbus->phy_mask = mdio_info->phy_mask;\n+\tbus->irq[0] = mdio_info->irq[0];\n+\tpriv = bus->priv;\n+\tpriv->mdio_base = cbus_emac_base[ii];\n+\n+\tpriv->mdc_div = mdio_info->mdc_div;\n+\tif (!priv->mdc_div)\n+\t\tpriv->mdc_div = 64;\n+\n+\tdev_info(bus->parent, \"%s: mdc_div: %d, phy_mask: %x\\n\",\n+\t\t __func__, priv->mdc_div, bus->phy_mask);\n+\tmdio_node = of_get_child_by_name(pfe->dev->of_node, \"mdio\");\n+\tif ((mdio_info->id == 0) && mdio_node) {\n+\t\trc = of_mdiobus_register(bus, mdio_node);\n+\t\tof_node_put(mdio_node);\n+\t} else {\n+\t\trc = mdiobus_register(bus);\n+\t}\n+\n+\tif (rc) {\n+\t\tdev_err(bus->parent, \"mdiobus_register(%s) failed\\n\",\n+\t\t\tbus->name);\n+\t\tgoto err_mdioregister;\n+\t}\n+\n+\tpriv->mii_bus = bus;\n+\tpfe->mdio.mdio_priv[ii] = priv;\n+\n+\tpfe_eth_mdio_reset(bus);\n+\n+\treturn 0;\n+\n+err_mdioregister:\n+\tmdiobus_free(bus);\n+err_mdioalloc:\n+\treturn rc;\n+}\n+\n+/* pfe_eth_mdio_exit\n+ */\n+static void pfe_eth_mdio_exit(struct pfe *pfe,\n+\t\t\t      int ii)\n+{\n+\tstruct pfe_mdio_priv_s *mdio_priv = pfe->mdio.mdio_priv[ii];\n+\tstruct mii_bus *bus = mdio_priv->mii_bus;\n+\n+\tif (!bus)\n+\t\treturn;\n+\tmdiobus_unregister(bus);\n+\tmdiobus_free(bus);\n+}\n+\n+/* pfe_get_phydev_speed\n+ */\n+static int pfe_get_phydev_speed(struct phy_device *phydev)\n+{\n+\tswitch (phydev->speed) {\n+\tcase 10:\n+\t\t\treturn SPEED_10M;\n+\tcase 100:\n+\t\t\treturn SPEED_100M;\n+\tcase 1000:\n+\tdefault:\n+\t\t\treturn SPEED_1000M;\n+\t}\n+}\n+\n+/* pfe_set_rgmii_speed\n+ */\n+#define RGMIIPCR\t0x434\n+/* RGMIIPCR bit definitions*/\n+#define SCFG_RGMIIPCR_EN_AUTO           (0x00000008)\n+#define SCFG_RGMIIPCR_SETSP_1000M       (0x00000004)\n+#define SCFG_RGMIIPCR_SETSP_100M        (0x00000000)\n+#define SCFG_RGMIIPCR_SETSP_10M         (0x00000002)\n+#define SCFG_RGMIIPCR_SETFD             (0x00000001)\n+\n+#define MDIOSELCR\t0x484\n+#define MDIOSEL_SERDES\t0x0\n+#define MDIOSEL_EXTPHY  0x80000000\n+\n+static void pfe_set_rgmii_speed(struct phy_device *phydev)\n+{\n+\tu32 rgmii_pcr;\n+\n+\tregmap_read(pfe->scfg, RGMIIPCR, &rgmii_pcr);\n+\trgmii_pcr  &= ~(SCFG_RGMIIPCR_SETSP_1000M | SCFG_RGMIIPCR_SETSP_10M);\n+\n+\tswitch (phydev->speed) {\n+\tcase 10:\n+\t\t\trgmii_pcr |= SCFG_RGMIIPCR_SETSP_10M;\n+\t\t\tbreak;\n+\tcase 1000:\n+\t\t\trgmii_pcr |= SCFG_RGMIIPCR_SETSP_1000M;\n+\t\t\tbreak;\n+\tcase 100:\n+\tdefault:\n+\t\t\t/* Default is 100M */\n+\t\t\tbreak;\n+\t}\n+\tregmap_write(pfe->scfg, RGMIIPCR, rgmii_pcr);\n+}\n+\n+/* pfe_get_phydev_duplex\n+ */\n+static int pfe_get_phydev_duplex(struct phy_device *phydev)\n+{\n+\t/*return (phydev->duplex == DUPLEX_HALF) ? DUP_HALF:DUP_FULL ; */\n+\treturn DUPLEX_FULL;\n+}\n+\n+/* pfe_eth_adjust_link\n+ */\n+static void pfe_eth_adjust_link(struct net_device *ndev)\n+{\n+\tstruct pfe_eth_priv_s *priv = netdev_priv(ndev);\n+\tunsigned long flags;\n+\tstruct phy_device *phydev = priv->phydev;\n+\tint new_state = 0;\n+\n+\tnetif_info(priv, drv, ndev, \"%s\\n\", __func__);\n+\n+\tspin_lock_irqsave(&priv->lock, flags);\n+\n+\tif (phydev->link) {\n+\t\t/*\n+\t\t * Now we make sure that we can be in full duplex mode.\n+\t\t * If not, we operate in half-duplex mode.\n+\t\t */\n+\t\tif (phydev->duplex != priv->oldduplex) {\n+\t\t\tnew_state = 1;\n+\t\t\tgemac_set_duplex(priv->EMAC_baseaddr,\n+\t\t\t\t\t pfe_get_phydev_duplex(phydev));\n+\t\t\tpriv->oldduplex = phydev->duplex;\n+\t\t}\n+\n+\t\tif (phydev->speed != priv->oldspeed) {\n+\t\t\tnew_state = 1;\n+\t\t\tgemac_set_speed(priv->EMAC_baseaddr,\n+\t\t\t\t\tpfe_get_phydev_speed(phydev));\n+\t\t\tif (priv->einfo->mii_config ==\n+\t\t\t\t\tPHY_INTERFACE_MODE_RGMII_ID)\n+\t\t\t\tpfe_set_rgmii_speed(phydev);\n+\t\t\tpriv->oldspeed = phydev->speed;\n+\t\t}\n+\n+\t\tif (!priv->oldlink) {\n+\t\t\tnew_state = 1;\n+\t\t\tpriv->oldlink = 1;\n+\t\t}\n+\n+\t} else if (priv->oldlink) {\n+\t\tnew_state = 1;\n+\t\tpriv->oldlink = 0;\n+\t\tpriv->oldspeed = 0;\n+\t\tpriv->oldduplex = -1;\n+\t}\n+\n+\tif (new_state && netif_msg_link(priv))\n+\t\tphy_print_status(phydev);\n+\n+\tspin_unlock_irqrestore(&priv->lock, flags);\n+\n+\t/* Now, dump the details to the cdev.\n+\t * XXX: Locking would be required? (uniprocess arch)\n+\t *      Or, maybe move it in spinlock above\n+\t */\n+\tif (us && priv->einfo->gem_id < PFE_CDEV_ETH_COUNT) {\n+\t\tpr_debug(\"Changing link state from (%u) to (%u) for ID=(%u)\\n\",\n+\t\t\t link_states[priv->einfo->gem_id].state,\n+\t\t\t phydev->link,\n+\t\t\t priv->einfo->gem_id);\n+\t\tlink_states[priv->einfo->gem_id].phy_id = priv->einfo->gem_id;\n+\t\tlink_states[priv->einfo->gem_id].state = phydev->link;\n+\t}\n+}\n+\n+/* pfe_phy_exit\n+ */\n+static void pfe_phy_exit(struct net_device *ndev)\n+{\n+\tstruct pfe_eth_priv_s *priv = netdev_priv(ndev);\n+\n+\tnetif_info(priv, drv, ndev, \"%s\\n\", __func__);\n+\n+\tphy_disconnect(priv->phydev);\n+\tpriv->phydev = NULL;\n+}\n+\n+/* pfe_eth_stop\n+ */\n+static void pfe_eth_stop(struct net_device *ndev, int wake)\n+{\n+\tstruct pfe_eth_priv_s *priv = netdev_priv(ndev);\n+\n+\tnetif_info(priv, drv, ndev, \"%s\\n\", __func__);\n+\n+\tif (wake) {\n+\t\tgemac_tx_disable(priv->EMAC_baseaddr);\n+\t} else {\n+\t\tgemac_disable(priv->EMAC_baseaddr);\n+\t\tgpi_disable(priv->GPI_baseaddr);\n+\n+\t\tif (priv->phydev)\n+\t\t\tphy_stop(priv->phydev);\n+\t}\n+}\n+\n+/* pfe_eth_start\n+ */\n+static int pfe_eth_start(struct pfe_eth_priv_s *priv)\n+{\n+\tnetif_info(priv, drv, priv->ndev, \"%s\\n\", __func__);\n+\n+\tif (priv->phydev)\n+\t\tphy_start(priv->phydev);\n+\n+\tgpi_enable(priv->GPI_baseaddr);\n+\tgemac_enable(priv->EMAC_baseaddr);\n+\n+\treturn 0;\n+}\n+\n+/*\n+ * Configure on chip serdes through mdio\n+ */\n+static void ls1012a_configure_serdes(struct net_device *ndev)\n+{\n+\tstruct pfe_eth_priv_s *eth_priv = netdev_priv(ndev);\n+\tstruct pfe_mdio_priv_s *mdio_priv = pfe->mdio.mdio_priv[eth_priv->id];\n+\tint sgmii_2500 = 0;\n+\tstruct mii_bus *bus = mdio_priv->mii_bus;\n+\tu16 value = 0;\n+\n+\tif (eth_priv->einfo->mii_config == PHY_INTERFACE_MODE_2500SGMII)\n+\t\tsgmii_2500 = 1;\n+\n+\tnetif_info(eth_priv, drv, ndev, \"%s\\n\", __func__);\n+\t/* PCS configuration done with corresponding GEMAC */\n+\n+\tpfe_eth_mdio_read(bus, 0, MDIO_SGMII_CR);\n+\tpfe_eth_mdio_read(bus, 0, MDIO_SGMII_SR);\n+\n+\tpfe_eth_mdio_write(bus, 0, MDIO_SGMII_CR, SGMII_CR_RST);\n+\n+\tif (sgmii_2500) {\n+\t\tpfe_eth_mdio_write(bus, 0, MDIO_SGMII_IF_MODE, SGMII_SPEED_1GBPS\n+\t\t\t\t\t\t\t       | SGMII_EN);\n+\t\tpfe_eth_mdio_write(bus, 0, MDIO_SGMII_DEV_ABIL_SGMII,\n+\t\t\t\t   SGMII_DEV_ABIL_ACK | SGMII_DEV_ABIL_SGMII);\n+\t\tpfe_eth_mdio_write(bus, 0, MDIO_SGMII_LINK_TMR_L, 0xa120);\n+\t\tpfe_eth_mdio_write(bus, 0, MDIO_SGMII_LINK_TMR_H, 0x7);\n+\t\t/* Autonegotiation need to be disabled for 2.5G SGMII mode*/\n+\t\tvalue = SGMII_CR_FD | SGMII_CR_SPEED_SEL1_1G;\n+\t\tpfe_eth_mdio_write(bus, 0, MDIO_SGMII_CR, value);\n+\t} else {\n+\t\tpfe_eth_mdio_write(bus, 0, MDIO_SGMII_IF_MODE,\n+\t\t\t\t   SGMII_SPEED_1GBPS\n+\t\t\t\t   | SGMII_USE_SGMII_AN\n+\t\t\t\t   | SGMII_EN);\n+\t\tpfe_eth_mdio_write(bus, 0, MDIO_SGMII_DEV_ABIL_SGMII,\n+\t\t\t\t   SGMII_DEV_ABIL_EEE_CLK_STP_EN\n+\t\t\t\t   | 0xa0\n+\t\t\t\t   | SGMII_DEV_ABIL_SGMII);\n+\t\tpfe_eth_mdio_write(bus, 0, MDIO_SGMII_LINK_TMR_L, 0x400);\n+\t\tpfe_eth_mdio_write(bus, 0, MDIO_SGMII_LINK_TMR_H, 0x0);\n+\t\tvalue = SGMII_CR_AN_EN | SGMII_CR_FD | SGMII_CR_SPEED_SEL1_1G;\n+\t\tpfe_eth_mdio_write(bus, 0, MDIO_SGMII_CR, value);\n+\t}\n+}\n+\n+/*\n+ * pfe_phy_init\n+ *\n+ */\n+static int pfe_phy_init(struct net_device *ndev)\n+{\n+\tstruct pfe_eth_priv_s *priv = netdev_priv(ndev);\n+\tstruct phy_device *phydev;\n+\tchar phy_id[MII_BUS_ID_SIZE + 3];\n+\tchar bus_id[MII_BUS_ID_SIZE];\n+\tphy_interface_t interface;\n+\n+\tpriv->oldlink = 0;\n+\tpriv->oldspeed = 0;\n+\tpriv->oldduplex = -1;\n+\n+\tsnprintf(bus_id, MII_BUS_ID_SIZE, \"ls1012a-%d\", 0);\n+\tsnprintf(phy_id, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id,\n+\t\t priv->einfo->phy_id);\n+\tnetif_info(priv, drv, ndev, \"%s: %s\\n\", __func__, phy_id);\n+\tinterface = priv->einfo->mii_config;\n+\tif ((interface == PHY_INTERFACE_MODE_SGMII) ||\n+\t    (interface == PHY_INTERFACE_MODE_2500SGMII)) {\n+\t\t/*Configure SGMII PCS */\n+\t\tif (pfe->scfg) {\n+\t\t\t/* Config MDIO from serdes */\n+\t\t\tregmap_write(pfe->scfg, MDIOSELCR, MDIOSEL_SERDES);\n+\t\t}\n+\t\tls1012a_configure_serdes(ndev);\n+\t}\n+\n+\tif (pfe->scfg) {\n+\t\t/*Config MDIO from PAD */\n+\t\tregmap_write(pfe->scfg, MDIOSELCR, MDIOSEL_EXTPHY);\n+\t}\n+\n+\tpriv->oldlink = 0;\n+\tpriv->oldspeed = 0;\n+\tpriv->oldduplex = -1;\n+\tpr_info(\"%s interface %x\\n\", __func__, interface);\n+\n+\tif (priv->phy_node) {\n+\t\tphydev = of_phy_connect(ndev, priv->phy_node,\n+\t\t\t\t\tpfe_eth_adjust_link, 0,\n+\t\t\t\t\tpriv->einfo->mii_config);\n+\t\tif (!(phydev)) {\n+\t\t\tnetdev_err(ndev, \"Unable to connect to phy\\n\");\n+\t\t\treturn -ENODEV;\n+\t\t}\n+\n+\t} else {\n+\t\tphydev = phy_connect(ndev, phy_id,\n+\t\t\t\t     &pfe_eth_adjust_link, interface);\n+\t\tif (IS_ERR(phydev)) {\n+\t\t\tnetdev_err(ndev, \"Unable to connect to phy\\n\");\n+\t\t\treturn PTR_ERR(phydev);\n+\t\t}\n+\t}\n+\n+\tpriv->phydev = phydev;\n+\tphydev->irq = PHY_POLL;\n+\n+\treturn 0;\n+}\n+\n+/* pfe_gemac_init\n+ */\n+static int pfe_gemac_init(struct pfe_eth_priv_s *priv)\n+{\n+\tstruct gemac_cfg cfg;\n+\n+\tnetif_info(priv, ifup, priv->ndev, \"%s\\n\", __func__);\n+\n+\tcfg.mode = 0;\n+\tcfg.speed = SPEED_1000M;\n+\tcfg.duplex = DUPLEX_FULL;\n+\n+\tgemac_set_config(priv->EMAC_baseaddr, &cfg);\n+\tgemac_allow_broadcast(priv->EMAC_baseaddr);\n+\tgemac_enable_1536_rx(priv->EMAC_baseaddr);\n+\tgemac_enable_stacked_vlan(priv->EMAC_baseaddr);\n+\tgemac_enable_pause_rx(priv->EMAC_baseaddr);\n+\tgemac_set_bus_width(priv->EMAC_baseaddr, 64);\n+\n+\t/*GEM will perform checksum verifications*/\n+\tif (priv->ndev->features & NETIF_F_RXCSUM)\n+\t\tgemac_enable_rx_checksum_offload(priv->EMAC_baseaddr);\n+\telse\n+\t\tgemac_disable_rx_checksum_offload(priv->EMAC_baseaddr);\n+\n+\treturn 0;\n+}\n+\n+/* pfe_eth_event_handler\n+ */\n+static int pfe_eth_event_handler(void *data, int event, int qno)\n+{\n+\tstruct pfe_eth_priv_s *priv = data;\n+\n+\tswitch (event) {\n+\tcase EVENT_RX_PKT_IND:\n+\n+\t\tif (qno == 0) {\n+\t\t\tif (napi_schedule_prep(&priv->high_napi)) {\n+\t\t\t\tnetif_info(priv, intr, priv->ndev,\n+\t\t\t\t\t   \"%s: schedule high prio poll\\n\"\n+\t\t\t\t\t   , __func__);\n+\n+#ifdef PFE_ETH_NAPI_STATS\n+\t\t\t\tpriv->napi_counters[NAPI_SCHED_COUNT]++;\n+#endif\n+\n+\t\t\t\t__napi_schedule(&priv->high_napi);\n+\t\t\t}\n+\t\t} else if (qno == 1) {\n+\t\t\tif (napi_schedule_prep(&priv->low_napi)) {\n+\t\t\t\tnetif_info(priv, intr, priv->ndev,\n+\t\t\t\t\t   \"%s: schedule low prio poll\\n\"\n+\t\t\t\t\t   , __func__);\n+\n+#ifdef PFE_ETH_NAPI_STATS\n+\t\t\t\tpriv->napi_counters[NAPI_SCHED_COUNT]++;\n+#endif\n+\t\t\t\t__napi_schedule(&priv->low_napi);\n+\t\t\t}\n+\t\t} else if (qno == 2) {\n+\t\t\tif (napi_schedule_prep(&priv->lro_napi)) {\n+\t\t\t\tnetif_info(priv, intr, priv->ndev,\n+\t\t\t\t\t   \"%s: schedule lro prio poll\\n\"\n+\t\t\t\t\t   , __func__);\n+\n+#ifdef PFE_ETH_NAPI_STATS\n+\t\t\t\tpriv->napi_counters[NAPI_SCHED_COUNT]++;\n+#endif\n+\t\t\t\t__napi_schedule(&priv->lro_napi);\n+\t\t\t}\n+\t\t}\n+\n+\t\tbreak;\n+\n+\tcase EVENT_TXDONE_IND:\n+\t\tpfe_eth_flush_tx(priv);\n+\t\thif_lib_event_handler_start(&priv->client, EVENT_TXDONE_IND, 0);\n+\t\tbreak;\n+\tcase EVENT_HIGH_RX_WM:\n+\tdefault:\n+\t\tbreak;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int pfe_eth_change_mtu(struct net_device *ndev, int new_mtu)\n+{\n+\tstruct pfe_eth_priv_s *priv = netdev_priv(ndev);\n+\n+\tndev->mtu = new_mtu;\n+\tnew_mtu += ETH_HLEN + ETH_FCS_LEN;\n+\tgemac_set_rx_max_fl(priv->EMAC_baseaddr, new_mtu);\n+\n+\treturn 0;\n+}\n+\n+/* pfe_eth_open\n+ */\n+static int pfe_eth_open(struct net_device *ndev)\n+{\n+\tstruct pfe_eth_priv_s *priv = netdev_priv(ndev);\n+\tstruct hif_client_s *client;\n+\tint rc;\n+\n+\tnetif_info(priv, ifup, ndev, \"%s\\n\", __func__);\n+\n+\t/* Register client driver with HIF */\n+\tclient = &priv->client;\n+\tmemset(client, 0, sizeof(*client));\n+\tclient->id = PFE_CL_GEM0 + priv->id;\n+\tclient->tx_qn = emac_txq_cnt;\n+\tclient->rx_qn = EMAC_RXQ_CNT;\n+\tclient->priv = priv;\n+\tclient->pfe = priv->pfe;\n+\tclient->event_handler = pfe_eth_event_handler;\n+\n+\tclient->tx_qsize = EMAC_TXQ_DEPTH;\n+\tclient->rx_qsize = EMAC_RXQ_DEPTH;\n+\n+\trc = hif_lib_client_register(client);\n+\tif (rc) {\n+\t\tnetdev_err(ndev, \"%s: hif_lib_client_register(%d) failed\\n\",\n+\t\t\t   __func__, client->id);\n+\t\tgoto err0;\n+\t}\n+\n+\tnetif_info(priv, drv, ndev, \"%s: registered client: %p\\n\", __func__,\n+\t\t   client);\n+\n+\tpfe_gemac_init(priv);\n+\n+\tif (!is_valid_ether_addr(ndev->dev_addr)) {\n+\t\tnetdev_err(ndev, \"%s: invalid MAC address\\n\", __func__);\n+\t\trc = -EADDRNOTAVAIL;\n+\t\tgoto err1;\n+\t}\n+\n+\tgemac_set_laddrN(priv->EMAC_baseaddr,\n+\t\t\t (struct pfe_mac_addr *)ndev->dev_addr, 1);\n+\n+\tnapi_enable(&priv->high_napi);\n+\tnapi_enable(&priv->low_napi);\n+\tnapi_enable(&priv->lro_napi);\n+\n+\trc = pfe_eth_start(priv);\n+\n+\tnetif_tx_wake_all_queues(ndev);\n+\n+\treturn rc;\n+\n+err1:\n+\thif_lib_client_unregister(&priv->client);\n+\n+err0:\n+\treturn rc;\n+}\n+\n+/*\n+ *  pfe_eth_shutdown\n+ */\n+int pfe_eth_shutdown(struct net_device *ndev, int wake)\n+{\n+\tstruct pfe_eth_priv_s *priv = netdev_priv(ndev);\n+\tint i, qstatus, id;\n+\tunsigned long next_poll = jiffies + 1, end = jiffies +\n+\t\t\t\t(TX_POLL_TIMEOUT_MS * HZ) / 1000;\n+\tint tx_pkts, prv_tx_pkts;\n+\n+\tnetif_info(priv, ifdown, ndev, \"%s\\n\", __func__);\n+\n+\tfor (i = 0; i < emac_txq_cnt; i++)\n+\t\thrtimer_cancel(&priv->fast_tx_timeout[i].timer);\n+\n+\tnetif_tx_stop_all_queues(ndev);\n+\n+\tdo {\n+\t\ttx_pkts = 0;\n+\t\tpfe_eth_flush_tx(priv);\n+\n+\t\tfor (i = 0; i < emac_txq_cnt; i++)\n+\t\t\ttx_pkts += hif_lib_tx_pending(&priv->client, i);\n+\n+\t\tif (tx_pkts) {\n+\t\t\t/*Don't wait forever, break if we cross max timeout */\n+\t\t\tif (time_after(jiffies, end)) {\n+\t\t\t\tpr_err(\n+\t\t\t\t\t\"(%s)Tx is not complete after %dmsec\\n\",\n+\t\t\t\t\tndev->name, TX_POLL_TIMEOUT_MS);\n+\t\t\t\tbreak;\n+\t\t\t}\n+\n+\t\t\tpr_info(\"%s : (%s) Waiting for tx packets to free. Pending tx pkts = %d.\\n\"\n+\t\t\t\t, __func__, ndev->name, tx_pkts);\n+\t\t\tif (need_resched())\n+\t\t\t\tschedule();\n+\t\t}\n+\n+\t} while (tx_pkts);\n+\n+\tend = jiffies + (TX_POLL_TIMEOUT_MS * HZ) / 1000;\n+\n+\tprv_tx_pkts = tmu_pkts_processed(priv->id);\n+\t/*\n+\t * Wait till TMU transmits all pending packets\n+\t * poll tmu_qstatus and pkts processed by TMU for every 10ms\n+\t * Consider TMU is busy, If we see TMU qeueu pending or any packets\n+\t * processed by TMU\n+\t */\n+\twhile (1) {\n+\t\tif (time_after(jiffies, next_poll)) {\n+\t\t\ttx_pkts = tmu_pkts_processed(priv->id);\n+\t\t\tqstatus = tmu_qstatus(priv->id) & 0x7ffff;\n+\n+\t\t\tif (!qstatus && (tx_pkts == prv_tx_pkts))\n+\t\t\t\tbreak;\n+\t\t\t/* Don't wait forever, break if we cross max\n+\t\t\t * timeout(TX_POLL_TIMEOUT_MS)\n+\t\t\t */\n+\t\t\tif (time_after(jiffies, end)) {\n+\t\t\t\tpr_err(\"TMU%d is busy after %dmsec\\n\",\n+\t\t\t\t       priv->id, TX_POLL_TIMEOUT_MS);\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t\tprv_tx_pkts = tx_pkts;\n+\t\t\tnext_poll++;\n+\t\t}\n+\t\tif (need_resched())\n+\t\t\tschedule();\n+\t}\n+\t/* Wait for some more time to complete transmitting packet if any */\n+\tnext_poll = jiffies + 1;\n+\twhile (1) {\n+\t\tif (time_after(jiffies, next_poll))\n+\t\t\tbreak;\n+\t\tif (need_resched())\n+\t\t\tschedule();\n+\t}\n+\n+\tpfe_eth_stop(ndev, wake);\n+\n+\tnapi_disable(&priv->lro_napi);\n+\tnapi_disable(&priv->low_napi);\n+\tnapi_disable(&priv->high_napi);\n+\n+\tfor (id = CLASS0_ID; id <= CLASS_MAX_ID; id++) {\n+\t\tpe_dmem_write(id, 0, CLASS_DM_CRC_VALIDATED\n+\t\t\t      + (priv->id * 4), 4);\n+\t}\n+\n+\thif_lib_client_unregister(&priv->client);\n+\n+\treturn 0;\n+}\n+\n+/* pfe_eth_close\n+ *\n+ */\n+static int pfe_eth_close(struct net_device *ndev)\n+{\n+\tpfe_eth_shutdown(ndev, 0);\n+\n+\treturn 0;\n+}\n+\n+/* pfe_eth_suspend\n+ *\n+ * return value : 1 if netdevice is configured to wakeup system\n+ *                0 otherwise\n+ */\n+int pfe_eth_suspend(struct net_device *ndev)\n+{\n+\tstruct pfe_eth_priv_s *priv = netdev_priv(ndev);\n+\tint retval = 0;\n+\n+\tif (priv->wol) {\n+\t\tgemac_set_wol(priv->EMAC_baseaddr, priv->wol);\n+\t\tretval = 1;\n+\t}\n+\tpfe_eth_shutdown(ndev, priv->wol);\n+\n+\treturn retval;\n+}\n+\n+/* pfe_eth_resume\n+ *\n+ */\n+int pfe_eth_resume(struct net_device *ndev)\n+{\n+\tstruct pfe_eth_priv_s *priv = netdev_priv(ndev);\n+\n+\tif (priv->wol)\n+\t\tgemac_set_wol(priv->EMAC_baseaddr, 0);\n+\tgemac_tx_enable(priv->EMAC_baseaddr);\n+\n+\treturn pfe_eth_open(ndev);\n+}\n+\n+/* pfe_eth_get_queuenum\n+ */\n+static int pfe_eth_get_queuenum(struct pfe_eth_priv_s *priv, struct sk_buff\n+\t\t\t\t\t*skb)\n+{\n+\tint queuenum = 0;\n+\tunsigned long flags;\n+\n+\t/* Get the Fast Path queue number */\n+\t/*\n+\t * Use conntrack mark (if conntrack exists), then packet mark (if any),\n+\t * then fallback to default\n+\t */\n+#if defined(CONFIG_IP_NF_CONNTRACK_MARK) || defined(CONFIG_NF_CONNTRACK_MARK)\n+\tif (skb->_nfct) {\n+\t\tenum ip_conntrack_info cinfo;\n+\t\tstruct nf_conn *ct;\n+\n+\t\tct = nf_ct_get(skb, &cinfo);\n+\n+\t\tif (ct) {\n+\t\t\tu32 connmark;\n+\n+\t\t\tconnmark = ct->mark;\n+\n+\t\t\tif ((connmark & 0x80000000) && priv->id != 0)\n+\t\t\t\tconnmark >>= 16;\n+\n+\t\t\tqueuenum = connmark & EMAC_QUEUENUM_MASK;\n+\t\t}\n+\t} else  {/* continued after #endif ... */\n+#endif\n+\t\tif (skb->mark) {\n+\t\t\tqueuenum = skb->mark & EMAC_QUEUENUM_MASK;\n+\t\t} else {\n+\t\t\tspin_lock_irqsave(&priv->lock, flags);\n+\t\t\tqueuenum = priv->default_priority & EMAC_QUEUENUM_MASK;\n+\t\t\tspin_unlock_irqrestore(&priv->lock, flags);\n+\t\t}\n+#if defined(CONFIG_IP_NF_CONNTRACK_MARK) || defined(CONFIG_NF_CONNTRACK_MARK)\n+\t}\n+#endif\n+\treturn queuenum;\n+}\n+\n+/* pfe_eth_might_stop_tx\n+ *\n+ */\n+static int pfe_eth_might_stop_tx(struct pfe_eth_priv_s *priv, int queuenum,\n+\t\t\t\t struct netdev_queue *tx_queue,\n+\t\t\t\t unsigned int n_desc,\n+\t\t\t\t unsigned int n_segs)\n+{\n+\tktime_t kt;\n+\tint tried = 0;\n+\n+try_again:\n+\tif (unlikely((__hif_tx_avail(&pfe->hif) < n_desc) ||\n+\t(hif_lib_tx_avail(&priv->client, queuenum) < n_desc) ||\n+\t(hif_lib_tx_credit_avail(pfe, priv->id, queuenum) < n_segs))) {\n+\t\tif (!tried) {\n+\t\t\t__hif_lib_update_credit(&priv->client, queuenum);\n+\t\t\ttried = 1;\n+\t\t\tgoto try_again;\n+\t\t}\n+#ifdef PFE_ETH_TX_STATS\n+\t\tif (__hif_tx_avail(&pfe->hif) < n_desc) {\n+\t\t\tpriv->stop_queue_hif[queuenum]++;\n+\t\t} else if (hif_lib_tx_avail(&priv->client, queuenum) < n_desc) {\n+\t\t\tpriv->stop_queue_hif_client[queuenum]++;\n+\t\t} else if (hif_lib_tx_credit_avail(pfe, priv->id, queuenum) <\n+\t\t\tn_segs) {\n+\t\t\tpriv->stop_queue_credit[queuenum]++;\n+\t\t}\n+\t\tpriv->stop_queue_total[queuenum]++;\n+#endif\n+\t\tnetif_tx_stop_queue(tx_queue);\n+\n+\t\tkt = ktime_set(0, LS1012A_TX_FAST_RECOVERY_TIMEOUT_MS *\n+\t\t\t\tNSEC_PER_MSEC);\n+\t\thrtimer_start(&priv->fast_tx_timeout[queuenum].timer, kt,\n+\t\t\t      HRTIMER_MODE_REL);\n+\t\treturn -1;\n+\t} else {\n+\t\treturn 0;\n+\t}\n+}\n+\n+#define SA_MAX_OP 2\n+/* pfe_hif_send_packet\n+ *\n+ * At this level if TX fails we drop the packet\n+ */\n+static void pfe_hif_send_packet(struct sk_buff *skb, struct  pfe_eth_priv_s\n+\t\t\t\t\t*priv, int queuenum)\n+{\n+\tstruct skb_shared_info *sh = skb_shinfo(skb);\n+\tunsigned int nr_frags;\n+\tu32 ctrl = 0;\n+\n+\tnetif_info(priv, tx_queued, priv->ndev, \"%s\\n\", __func__);\n+\n+\tif (skb_is_gso(skb)) {\n+\t\tpriv->stats.tx_dropped++;\n+\t\treturn;\n+\t}\n+\n+\tif (skb->ip_summed == CHECKSUM_PARTIAL)\n+\t\tctrl = HIF_CTRL_TX_CHECKSUM;\n+\n+\tnr_frags = sh->nr_frags;\n+\n+\tif (nr_frags) {\n+\t\tskb_frag_t *f;\n+\t\tint i;\n+\n+\t\t__hif_lib_xmit_pkt(&priv->client, queuenum, skb->data,\n+\t\t\t\t   skb_headlen(skb), ctrl, HIF_FIRST_BUFFER,\n+\t\t\t\t   skb);\n+\n+\t\tfor (i = 0; i < nr_frags - 1; i++) {\n+\t\t\tf = &sh->frags[i];\n+\t\t\t__hif_lib_xmit_pkt(&priv->client, queuenum,\n+\t\t\t\t\t   skb_frag_address(f),\n+\t\t\t\t\t   skb_frag_size(f),\n+\t\t\t\t\t   0x0, 0x0, skb);\n+\t\t}\n+\n+\t\tf = &sh->frags[i];\n+\n+\t\t__hif_lib_xmit_pkt(&priv->client, queuenum,\n+\t\t\t\t   skb_frag_address(f), skb_frag_size(f),\n+\t\t\t\t   0x0, HIF_LAST_BUFFER | HIF_DATA_VALID,\n+\t\t\t\t   skb);\n+\n+\t\tnetif_info(priv, tx_queued, priv->ndev,\n+\t\t\t   \"%s: pkt sent successfully skb:%p nr_frags:%d len:%d\\n\",\n+\t\t\t   __func__, skb, nr_frags, skb->len);\n+\t} else {\n+\t\t__hif_lib_xmit_pkt(&priv->client, queuenum, skb->data,\n+\t\t\t\t   skb->len, ctrl, HIF_FIRST_BUFFER |\n+\t\t\t\t   HIF_LAST_BUFFER | HIF_DATA_VALID,\n+\t\t\t\t   skb);\n+\t\tnetif_info(priv, tx_queued, priv->ndev,\n+\t\t\t   \"%s: pkt sent successfully skb:%p len:%d\\n\",\n+\t\t\t   __func__, skb, skb->len);\n+\t}\n+\thif_tx_dma_start();\n+\tpriv->stats.tx_packets++;\n+\tpriv->stats.tx_bytes += skb->len;\n+\thif_lib_tx_credit_use(pfe, priv->id, queuenum, 1);\n+}\n+\n+/* pfe_eth_flush_txQ\n+ */\n+static void pfe_eth_flush_txQ(struct pfe_eth_priv_s *priv, int tx_q_num, int\n+\t\t\t\tfrom_tx, int n_desc)\n+{\n+\tstruct sk_buff *skb;\n+\tstruct netdev_queue *tx_queue = netdev_get_tx_queue(priv->ndev,\n+\t\t\t\t\t\t\t\ttx_q_num);\n+\tunsigned int flags;\n+\n+\tnetif_info(priv, tx_done, priv->ndev, \"%s\\n\", __func__);\n+\n+\tif (!from_tx)\n+\t\t__netif_tx_lock_bh(tx_queue);\n+\n+\t/* Clean HIF and client queue */\n+\twhile ((skb = hif_lib_tx_get_next_complete(&priv->client,\n+\t\t\t\t\t\t   tx_q_num, &flags,\n+\t\t\t\t\t\t   HIF_TX_DESC_NT))) {\n+\t\tif (flags & HIF_DATA_VALID)\n+\t\t\tdev_kfree_skb_any(skb);\n+\t}\n+\tif (!from_tx)\n+\t\t__netif_tx_unlock_bh(tx_queue);\n+}\n+\n+/* pfe_eth_flush_tx\n+ */\n+static void pfe_eth_flush_tx(struct pfe_eth_priv_s *priv)\n+{\n+\tint ii;\n+\n+\tnetif_info(priv, tx_done, priv->ndev, \"%s\\n\", __func__);\n+\n+\tfor (ii = 0; ii < emac_txq_cnt; ii++) {\n+\t\tpfe_eth_flush_txQ(priv, ii, 0, 0);\n+\t\t__hif_lib_update_credit(&priv->client, ii);\n+\t}\n+}\n+\n+void pfe_tx_get_req_desc(struct sk_buff *skb, unsigned int *n_desc, unsigned int\n+\t\t\t\t*n_segs)\n+{\n+\tstruct skb_shared_info *sh = skb_shinfo(skb);\n+\n+\t/* Scattered data */\n+\tif (sh->nr_frags) {\n+\t\t*n_desc = sh->nr_frags + 1;\n+\t\t*n_segs = 1;\n+\t/* Regular case */\n+\t} else {\n+\t\t*n_desc = 1;\n+\t\t*n_segs = 1;\n+\t}\n+}\n+\n+/* pfe_eth_send_packet\n+ */\n+static int pfe_eth_send_packet(struct sk_buff *skb, struct net_device *ndev)\n+{\n+\tstruct pfe_eth_priv_s *priv = netdev_priv(ndev);\n+\tint tx_q_num = skb_get_queue_mapping(skb);\n+\tint n_desc, n_segs;\n+\tstruct netdev_queue *tx_queue = netdev_get_tx_queue(priv->ndev,\n+\t\t\t\t\t\t\t\ttx_q_num);\n+\n+\tnetif_info(priv, tx_queued, ndev, \"%s\\n\", __func__);\n+\n+\tif ((!skb_is_gso(skb)) && (skb_headroom(skb) < (PFE_PKT_HEADER_SZ +\n+\t\t\tsizeof(unsigned long)))) {\n+\t\tnetif_warn(priv, tx_err, priv->ndev, \"%s: copying skb\\n\",\n+\t\t\t   __func__);\n+\n+\t\tif (pskb_expand_head(skb, (PFE_PKT_HEADER_SZ + sizeof(unsigned\n+\t\t\t\t\tlong)), 0, GFP_ATOMIC)) {\n+\t\t\t/* No need to re-transmit, no way to recover*/\n+\t\t\tkfree_skb(skb);\n+\t\t\tpriv->stats.tx_dropped++;\n+\t\t\treturn NETDEV_TX_OK;\n+\t\t}\n+\t}\n+\n+\tpfe_tx_get_req_desc(skb, &n_desc, &n_segs);\n+\n+\thif_tx_lock(&pfe->hif);\n+\tif (unlikely(pfe_eth_might_stop_tx(priv, tx_q_num, tx_queue, n_desc,\n+\t\t\t\t\t   n_segs))) {\n+#ifdef PFE_ETH_TX_STATS\n+\t\tif (priv->was_stopped[tx_q_num]) {\n+\t\t\tpriv->clean_fail[tx_q_num]++;\n+\t\t\tpriv->was_stopped[tx_q_num] = 0;\n+\t\t}\n+#endif\n+\t\thif_tx_unlock(&pfe->hif);\n+\t\treturn NETDEV_TX_BUSY;\n+\t}\n+\n+\tpfe_hif_send_packet(skb, priv, tx_q_num);\n+\n+\thif_tx_unlock(&pfe->hif);\n+\n+\ttx_queue->trans_start = jiffies;\n+\n+#ifdef PFE_ETH_TX_STATS\n+\tpriv->was_stopped[tx_q_num] = 0;\n+#endif\n+\n+\treturn NETDEV_TX_OK;\n+}\n+\n+/* pfe_eth_select_queue\n+ *\n+ */\n+static u16 pfe_eth_select_queue(struct net_device *ndev, struct sk_buff *skb,\n+\t\t\t\tstruct net_device *sb_dev)\n+{\n+\tstruct pfe_eth_priv_s *priv = netdev_priv(ndev);\n+\n+\treturn pfe_eth_get_queuenum(priv, skb);\n+}\n+\n+/* pfe_eth_get_stats\n+ */\n+static struct net_device_stats *pfe_eth_get_stats(struct net_device *ndev)\n+{\n+\tstruct pfe_eth_priv_s *priv = netdev_priv(ndev);\n+\n+\tnetif_info(priv, drv, ndev, \"%s\\n\", __func__);\n+\n+\treturn &priv->stats;\n+}\n+\n+/* pfe_eth_set_mac_address\n+ */\n+static int pfe_eth_set_mac_address(struct net_device *ndev, void *addr)\n+{\n+\tstruct pfe_eth_priv_s *priv = netdev_priv(ndev);\n+\tstruct sockaddr *sa = addr;\n+\n+\tnetif_info(priv, drv, ndev, \"%s\\n\", __func__);\n+\n+\tif (!is_valid_ether_addr(sa->sa_data))\n+\t\treturn -EADDRNOTAVAIL;\n+\n+\tmemcpy(ndev->dev_addr, sa->sa_data, ETH_ALEN);\n+\n+\tgemac_set_laddrN(priv->EMAC_baseaddr,\n+\t\t\t (struct pfe_mac_addr *)ndev->dev_addr, 1);\n+\n+\treturn 0;\n+}\n+\n+/* pfe_eth_enet_addr_byte_mac\n+ */\n+int pfe_eth_enet_addr_byte_mac(u8 *enet_byte_addr,\n+\t\t\t       struct pfe_mac_addr *enet_addr)\n+{\n+\tif (!enet_byte_addr || !enet_addr) {\n+\t\treturn -1;\n+\n+\t} else {\n+\t\tenet_addr->bottom = enet_byte_addr[0] |\n+\t\t\t(enet_byte_addr[1] << 8) |\n+\t\t\t(enet_byte_addr[2] << 16) |\n+\t\t\t(enet_byte_addr[3] << 24);\n+\t\tenet_addr->top = enet_byte_addr[4] |\n+\t\t\t(enet_byte_addr[5] << 8);\n+\t\treturn 0;\n+\t}\n+}\n+\n+/* pfe_eth_set_multi\n+ */\n+static void pfe_eth_set_multi(struct net_device *ndev)\n+{\n+\tstruct pfe_eth_priv_s *priv = netdev_priv(ndev);\n+\tstruct pfe_mac_addr    hash_addr; /* hash register structure */\n+\t/* specific mac address\tregister structure */\n+\tstruct pfe_mac_addr    spec_addr;\n+\tint\t\tresult; /* index into hash register to set.. */\n+\tint\t\tuc_count = 0;\n+\tstruct netdev_hw_addr *ha;\n+\n+\tif (ndev->flags & IFF_PROMISC) {\n+\t\tnetif_info(priv, drv, ndev, \"entering promiscuous mode\\n\");\n+\n+\t\tpriv->promisc = 1;\n+\t\tgemac_enable_copy_all(priv->EMAC_baseaddr);\n+\t} else {\n+\t\tpriv->promisc = 0;\n+\t\tgemac_disable_copy_all(priv->EMAC_baseaddr);\n+\t}\n+\n+\t/* Enable broadcast frame reception if required. */\n+\tif (ndev->flags & IFF_BROADCAST) {\n+\t\tgemac_allow_broadcast(priv->EMAC_baseaddr);\n+\t} else {\n+\t\tnetif_info(priv, drv, ndev,\n+\t\t\t   \"disabling broadcast frame reception\\n\");\n+\n+\t\tgemac_no_broadcast(priv->EMAC_baseaddr);\n+\t}\n+\n+\tif (ndev->flags & IFF_ALLMULTI) {\n+\t\t/* Set the hash to rx all multicast frames */\n+\t\thash_addr.bottom = 0xFFFFFFFF;\n+\t\thash_addr.top = 0xFFFFFFFF;\n+\t\tgemac_set_hash(priv->EMAC_baseaddr, &hash_addr);\n+\t\tnetdev_for_each_uc_addr(ha, ndev) {\n+\t\t\tif (uc_count >= MAX_UC_SPEC_ADDR_REG)\n+\t\t\t\tbreak;\n+\t\t\tpfe_eth_enet_addr_byte_mac(ha->addr, &spec_addr);\n+\t\t\tgemac_set_laddrN(priv->EMAC_baseaddr, &spec_addr,\n+\t\t\t\t\t uc_count + 2);\n+\t\t\tuc_count++;\n+\t\t}\n+\t} else if ((netdev_mc_count(ndev) > 0)  || (netdev_uc_count(ndev))) {\n+\t\tu8 *addr;\n+\n+\t\thash_addr.bottom = 0;\n+\t\thash_addr.top = 0;\n+\n+\t\tnetdev_for_each_mc_addr(ha, ndev) {\n+\t\t\taddr = ha->addr;\n+\n+\t\t\tnetif_info(priv, drv, ndev,\n+\t\t\t\t   \"adding multicast address %X:%X:%X:%X:%X:%X to gem filter\\n\",\n+\t\t\t\taddr[0], addr[1], addr[2],\n+\t\t\t\taddr[3], addr[4], addr[5]);\n+\n+\t\t\tresult = pfe_eth_get_hash(addr);\n+\n+\t\t\tif (result < EMAC_HASH_REG_BITS) {\n+\t\t\t\tif (result < 32)\n+\t\t\t\t\thash_addr.bottom |= (1 << result);\n+\t\t\t\telse\n+\t\t\t\t\thash_addr.top |= (1 << (result - 32));\n+\t\t\t} else {\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t}\n+\n+\t\tuc_count = -1;\n+\t\tnetdev_for_each_uc_addr(ha, ndev) {\n+\t\t\taddr = ha->addr;\n+\n+\t\t\tif (++uc_count < MAX_UC_SPEC_ADDR_REG)   {\n+\t\t\t\tnetdev_info(ndev,\n+\t\t\t\t\t    \"adding unicast address %02x:%02x:%02x:%02x:%02x:%02x to gem filter\\n\",\n+\t\t\t\t\t    addr[0], addr[1], addr[2],\n+\t\t\t\t\t    addr[3], addr[4], addr[5]);\n+\t\t\t\tpfe_eth_enet_addr_byte_mac(addr, &spec_addr);\n+\t\t\t\tgemac_set_laddrN(priv->EMAC_baseaddr,\n+\t\t\t\t\t\t &spec_addr, uc_count + 2);\n+\t\t\t} else {\n+\t\t\t\tnetif_info(priv, drv, ndev,\n+\t\t\t\t\t   \"adding unicast address %02x:%02x:%02x:%02x:%02x:%02x to gem hash\\n\",\n+\t\t\t\t\t   addr[0], addr[1], addr[2],\n+\t\t\t\t\t   addr[3], addr[4], addr[5]);\n+\n+\t\t\t\tresult = pfe_eth_get_hash(addr);\n+\t\t\t\tif (result >= EMAC_HASH_REG_BITS) {\n+\t\t\t\t\tbreak;\n+\n+\t\t\t\t} else {\n+\t\t\t\t\tif (result < 32)\n+\t\t\t\t\t\thash_addr.bottom |= (1 <<\n+\t\t\t\t\t\t\t\tresult);\n+\t\t\t\t\telse\n+\t\t\t\t\t\thash_addr.top |= (1 <<\n+\t\t\t\t\t\t\t\t(result - 32));\n+\t\t\t\t}\n+\t\t\t}\n+\t\t}\n+\n+\t\tgemac_set_hash(priv->EMAC_baseaddr, &hash_addr);\n+\t}\n+\n+\tif (!(netdev_uc_count(ndev) >= MAX_UC_SPEC_ADDR_REG)) {\n+\t\t/*\n+\t\t *  Check if there are any specific address HW registers that\n+\t\t * need to be flushed\n+\t\t */\n+\t\tfor (uc_count = netdev_uc_count(ndev); uc_count <\n+\t\t\tMAX_UC_SPEC_ADDR_REG; uc_count++)\n+\t\t\tgemac_clear_laddrN(priv->EMAC_baseaddr, uc_count + 2);\n+\t}\n+\n+\tif (ndev->flags & IFF_LOOPBACK)\n+\t\tgemac_set_loop(priv->EMAC_baseaddr, LB_LOCAL);\n+}\n+\n+/* pfe_eth_set_features\n+ */\n+static int pfe_eth_set_features(struct net_device *ndev, netdev_features_t\n+\t\t\t\t\tfeatures)\n+{\n+\tstruct pfe_eth_priv_s *priv = netdev_priv(ndev);\n+\tint rc = 0;\n+\n+\tif (features & NETIF_F_RXCSUM)\n+\t\tgemac_enable_rx_checksum_offload(priv->EMAC_baseaddr);\n+\telse\n+\t\tgemac_disable_rx_checksum_offload(priv->EMAC_baseaddr);\n+\treturn rc;\n+}\n+\n+/* pfe_eth_fast_tx_timeout\n+ */\n+static enum hrtimer_restart pfe_eth_fast_tx_timeout(struct hrtimer *timer)\n+{\n+\tstruct pfe_eth_fast_timer *fast_tx_timeout = container_of(timer, struct\n+\t\t\t\t\t\t\tpfe_eth_fast_timer,\n+\t\t\t\t\t\t\ttimer);\n+\tstruct pfe_eth_priv_s *priv =  container_of(fast_tx_timeout->base,\n+\t\t\t\t\t\t\tstruct pfe_eth_priv_s,\n+\t\t\t\t\t\t\tfast_tx_timeout);\n+\tstruct netdev_queue *tx_queue = netdev_get_tx_queue(priv->ndev,\n+\t\t\t\t\t\tfast_tx_timeout->queuenum);\n+\n+\tif (netif_tx_queue_stopped(tx_queue)) {\n+#ifdef PFE_ETH_TX_STATS\n+\t\tpriv->was_stopped[fast_tx_timeout->queuenum] = 1;\n+#endif\n+\t\tnetif_tx_wake_queue(tx_queue);\n+\t}\n+\n+\treturn HRTIMER_NORESTART;\n+}\n+\n+/* pfe_eth_fast_tx_timeout_init\n+ */\n+static void pfe_eth_fast_tx_timeout_init(struct pfe_eth_priv_s *priv)\n+{\n+\tint i;\n+\n+\tfor (i = 0; i < emac_txq_cnt; i++) {\n+\t\tpriv->fast_tx_timeout[i].queuenum = i;\n+\t\thrtimer_init(&priv->fast_tx_timeout[i].timer, CLOCK_MONOTONIC,\n+\t\t\t     HRTIMER_MODE_REL);\n+\t\tpriv->fast_tx_timeout[i].timer.function =\n+\t\t\t\tpfe_eth_fast_tx_timeout;\n+\t\tpriv->fast_tx_timeout[i].base = priv->fast_tx_timeout;\n+\t}\n+}\n+\n+static struct sk_buff *pfe_eth_rx_skb(struct net_device *ndev,\n+\t\t\t\t      struct\tpfe_eth_priv_s *priv,\n+\t\t\t\t      unsigned int qno)\n+{\n+\tvoid *buf_addr;\n+\tunsigned int rx_ctrl;\n+\tunsigned int desc_ctrl = 0;\n+\tstruct hif_ipsec_hdr *ipsec_hdr = NULL;\n+\tstruct sk_buff *skb;\n+\tstruct sk_buff *skb_frag, *skb_frag_last = NULL;\n+\tint length = 0, offset;\n+\n+\tskb = priv->skb_inflight[qno];\n+\n+\tif (skb) {\n+\t\tskb_frag_last = skb_shinfo(skb)->frag_list;\n+\t\tif (skb_frag_last) {\n+\t\t\twhile (skb_frag_last->next)\n+\t\t\t\tskb_frag_last = skb_frag_last->next;\n+\t\t}\n+\t}\n+\n+\twhile (!(desc_ctrl & CL_DESC_LAST)) {\n+\t\tbuf_addr = hif_lib_receive_pkt(&priv->client, qno, &length,\n+\t\t\t\t\t       &offset, &rx_ctrl, &desc_ctrl,\n+\t\t\t\t\t       (void **)&ipsec_hdr);\n+\t\tif (!buf_addr)\n+\t\t\tgoto incomplete;\n+\n+#ifdef PFE_ETH_NAPI_STATS\n+\t\tpriv->napi_counters[NAPI_DESC_COUNT]++;\n+#endif\n+\n+\t\t/* First frag */\n+\t\tif (desc_ctrl & CL_DESC_FIRST) {\n+\t\t\tskb = build_skb(buf_addr, 0);\n+\t\t\tif (unlikely(!skb))\n+\t\t\t\tgoto pkt_drop;\n+\n+\t\t\tskb_reserve(skb, offset);\n+\t\t\tskb_put(skb, length);\n+\t\t\tskb->dev = ndev;\n+\n+\t\t\tif ((ndev->features & NETIF_F_RXCSUM) && (rx_ctrl &\n+\t\t\t\t\tHIF_CTRL_RX_CHECKSUMMED))\n+\t\t\t\tskb->ip_summed = CHECKSUM_UNNECESSARY;\n+\t\t\telse\n+\t\t\t\tskb_checksum_none_assert(skb);\n+\n+\t\t} else {\n+\t\t\t/* Next frags */\n+\t\t\tif (unlikely(!skb)) {\n+\t\t\t\tpr_err(\"%s: NULL skb_inflight\\n\",\n+\t\t\t\t       __func__);\n+\t\t\t\tgoto pkt_drop;\n+\t\t\t}\n+\n+\t\t\tskb_frag = build_skb(buf_addr, 0);\n+\n+\t\t\tif (unlikely(!skb_frag)) {\n+\t\t\t\tkfree(buf_addr);\n+\t\t\t\tgoto pkt_drop;\n+\t\t\t}\n+\n+\t\t\tskb_reserve(skb_frag, offset);\n+\t\t\tskb_put(skb_frag, length);\n+\n+\t\t\tskb_frag->dev = ndev;\n+\n+\t\t\tif (skb_shinfo(skb)->frag_list)\n+\t\t\t\tskb_frag_last->next = skb_frag;\n+\t\t\telse\n+\t\t\t\tskb_shinfo(skb)->frag_list = skb_frag;\n+\n+\t\t\tskb->truesize += skb_frag->truesize;\n+\t\t\tskb->data_len += length;\n+\t\t\tskb->len += length;\n+\t\t\tskb_frag_last = skb_frag;\n+\t\t}\n+\t}\n+\n+\tpriv->skb_inflight[qno] = NULL;\n+\treturn skb;\n+\n+incomplete:\n+\tpriv->skb_inflight[qno] = skb;\n+\treturn NULL;\n+\n+pkt_drop:\n+\tpriv->skb_inflight[qno] = NULL;\n+\n+\tif (skb)\n+\t\tkfree_skb(skb);\n+\telse\n+\t\tkfree(buf_addr);\n+\n+\tpriv->stats.rx_errors++;\n+\n+\treturn NULL;\n+}\n+\n+/* pfe_eth_poll\n+ */\n+static int pfe_eth_poll(struct pfe_eth_priv_s *priv, struct napi_struct *napi,\n+\t\t\tunsigned int qno, int budget)\n+{\n+\tstruct net_device *ndev = priv->ndev;\n+\tstruct sk_buff *skb;\n+\tint work_done = 0;\n+\tunsigned int len;\n+\n+\tnetif_info(priv, intr, priv->ndev, \"%s\\n\", __func__);\n+\n+#ifdef PFE_ETH_NAPI_STATS\n+\tpriv->napi_counters[NAPI_POLL_COUNT]++;\n+#endif\n+\n+\tdo {\n+\t\tskb = pfe_eth_rx_skb(ndev, priv, qno);\n+\n+\t\tif (!skb)\n+\t\t\tbreak;\n+\n+\t\tlen = skb->len;\n+\n+\t\t/* Packet will be processed */\n+\t\tskb->protocol = eth_type_trans(skb, ndev);\n+\n+\t\tnetif_receive_skb(skb);\n+\n+\t\tpriv->stats.rx_packets++;\n+\t\tpriv->stats.rx_bytes += len;\n+\n+\t\twork_done++;\n+\n+#ifdef PFE_ETH_NAPI_STATS\n+\t\tpriv->napi_counters[NAPI_PACKET_COUNT]++;\n+#endif\n+\n+\t} while (work_done < budget);\n+\n+\t/*\n+\t * If no Rx receive nor cleanup work was done, exit polling mode.\n+\t * No more netif_running(dev) check is required here , as this is\n+\t * checked in net/core/dev.c (2.6.33.5 kernel specific).\n+\t */\n+\tif (work_done < budget) {\n+\t\tnapi_complete(napi);\n+\n+\t\thif_lib_event_handler_start(&priv->client, EVENT_RX_PKT_IND,\n+\t\t\t\t\t    qno);\n+\t}\n+#ifdef PFE_ETH_NAPI_STATS\n+\telse\n+\t\tpriv->napi_counters[NAPI_FULL_BUDGET_COUNT]++;\n+#endif\n+\n+\treturn work_done;\n+}\n+\n+/*\n+ * pfe_eth_lro_poll\n+ */\n+static int pfe_eth_lro_poll(struct napi_struct *napi, int budget)\n+{\n+\tstruct pfe_eth_priv_s *priv = container_of(napi, struct pfe_eth_priv_s,\n+\t\t\t\t\t\t\tlro_napi);\n+\n+\tnetif_info(priv, intr, priv->ndev, \"%s\\n\", __func__);\n+\n+\treturn pfe_eth_poll(priv, napi, 2, budget);\n+}\n+\n+/* pfe_eth_low_poll\n+ */\n+static int pfe_eth_low_poll(struct napi_struct *napi, int budget)\n+{\n+\tstruct pfe_eth_priv_s *priv = container_of(napi, struct pfe_eth_priv_s,\n+\t\t\t\t\t\t\tlow_napi);\n+\n+\tnetif_info(priv, intr, priv->ndev, \"%s\\n\", __func__);\n+\n+\treturn pfe_eth_poll(priv, napi, 1, budget);\n+}\n+\n+/* pfe_eth_high_poll\n+ */\n+static int pfe_eth_high_poll(struct napi_struct *napi, int budget)\n+{\n+\tstruct pfe_eth_priv_s *priv = container_of(napi, struct pfe_eth_priv_s,\n+\t\t\t\t\t\t\thigh_napi);\n+\n+\tnetif_info(priv, intr, priv->ndev, \"%s\\n\", __func__);\n+\n+\treturn pfe_eth_poll(priv, napi, 0, budget);\n+}\n+\n+static const struct net_device_ops pfe_netdev_ops = {\n+\t.ndo_open = pfe_eth_open,\n+\t.ndo_stop = pfe_eth_close,\n+\t.ndo_start_xmit = pfe_eth_send_packet,\n+\t.ndo_select_queue = pfe_eth_select_queue,\n+\t.ndo_set_rx_mode = pfe_eth_set_multi,\n+\t.ndo_set_mac_address = pfe_eth_set_mac_address,\n+\t.ndo_validate_addr = eth_validate_addr,\n+\t.ndo_change_mtu = pfe_eth_change_mtu,\n+\t.ndo_get_stats = pfe_eth_get_stats,\n+\t.ndo_set_features = pfe_eth_set_features,\n+};\n+\n+/* pfe_eth_init_one\n+ */\n+static int pfe_eth_init_one(struct pfe *pfe,\n+\t\t\t    struct ls1012a_pfe_platform_data *pfe_info,\n+\t\t\t    int id)\n+{\n+\tstruct net_device *ndev = NULL;\n+\tstruct pfe_eth_priv_s *priv = NULL;\n+\tstruct ls1012a_eth_platform_data *einfo;\n+\tint err;\n+\n+\teinfo = (struct ls1012a_eth_platform_data *)\n+\t\t\t\tpfe_info->ls1012a_eth_pdata;\n+\n+\t/* einfo never be NULL, but no harm in having this check */\n+\tif (!einfo) {\n+\t\tpr_err(\n+\t\t\t\"%s: pfe missing additional gemacs platform data\\n\"\n+\t\t\t, __func__);\n+\t\terr = -ENODEV;\n+\t\tgoto err0;\n+\t}\n+\n+\tif (us)\n+\t\temac_txq_cnt = EMAC_TXQ_CNT;\n+\t/* Create an ethernet device instance */\n+\tndev = alloc_etherdev_mq(sizeof(*priv), emac_txq_cnt);\n+\n+\tif (!ndev) {\n+\t\tpr_err(\"%s: gemac %d device allocation failed\\n\",\n+\t\t       __func__, einfo[id].gem_id);\n+\t\terr = -ENOMEM;\n+\t\tgoto err0;\n+\t}\n+\n+\tpriv = netdev_priv(ndev);\n+\tpriv->ndev = ndev;\n+\tpriv->id = einfo[id].gem_id;\n+\tpriv->pfe = pfe;\n+\tpriv->phy_node = einfo[id].phy_node;\n+\n+\tSET_NETDEV_DEV(priv->ndev, priv->pfe->dev);\n+\n+\tpfe->eth.eth_priv[id] = priv;\n+\n+\t/* Set the info in the priv to the current info */\n+\tpriv->einfo = &einfo[id];\n+\tpriv->EMAC_baseaddr = cbus_emac_base[id];\n+\tpriv->GPI_baseaddr = cbus_gpi_base[id];\n+\n+\tspin_lock_init(&priv->lock);\n+\n+\tpfe_eth_fast_tx_timeout_init(priv);\n+\n+\t/* Copy the station address into the dev structure, */\n+\tmemcpy(ndev->dev_addr, einfo[id].mac_addr, ETH_ALEN);\n+\n+\tif (us)\n+\t\tgoto phy_init;\n+\n+\tndev->mtu = 1500;\n+\n+\t/* Set MTU limits */\n+\tndev->min_mtu = ETH_MIN_MTU;\n+\n+/*\n+ * Jumbo frames are not supported on LS1012A rev-1.0.\n+ * So max mtu should be restricted to supported frame length.\n+ */\n+\tif (pfe_errata_a010897)\n+\t\tndev->max_mtu = JUMBO_FRAME_SIZE_V1 - ETH_HLEN - ETH_FCS_LEN;\n+\telse\n+\t\tndev->max_mtu = JUMBO_FRAME_SIZE_V2 - ETH_HLEN - ETH_FCS_LEN;\n+\n+\t/*Enable after checksum offload is validated */\n+\tndev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM |\n+\t\tNETIF_F_IPV6_CSUM | NETIF_F_SG;\n+\n+\t/* enabled by default */\n+\tndev->features = ndev->hw_features;\n+\n+\tpriv->usr_features = ndev->features;\n+\n+\tndev->netdev_ops = &pfe_netdev_ops;\n+\n+\tndev->ethtool_ops = &pfe_ethtool_ops;\n+\n+\t/* Enable basic messages by default */\n+\tpriv->msg_enable = NETIF_MSG_IFUP | NETIF_MSG_IFDOWN | NETIF_MSG_LINK |\n+\t\t\t\tNETIF_MSG_PROBE;\n+\n+\tnetif_napi_add(ndev, &priv->low_napi, pfe_eth_low_poll,\n+\t\t       HIF_RX_POLL_WEIGHT - 16);\n+\tnetif_napi_add(ndev, &priv->high_napi, pfe_eth_high_poll,\n+\t\t       HIF_RX_POLL_WEIGHT - 16);\n+\tnetif_napi_add(ndev, &priv->lro_napi, pfe_eth_lro_poll,\n+\t\t       HIF_RX_POLL_WEIGHT - 16);\n+\n+\terr = register_netdev(ndev);\n+\tif (err) {\n+\t\tnetdev_err(ndev, \"register_netdev() failed\\n\");\n+\t\tgoto err1;\n+\t}\n+\n+\tif ((!(pfe_use_old_dts_phy) && !(priv->phy_node)) ||\n+\t    ((pfe_use_old_dts_phy) &&\n+\t      (priv->einfo->phy_flags & GEMAC_NO_PHY))) {\n+\t\tpr_info(\"%s: No PHY or fixed-link\\n\", __func__);\n+\t\tgoto skip_phy_init;\n+\t}\n+\n+phy_init:\n+\tdevice_init_wakeup(&ndev->dev, WAKE_MAGIC);\n+\n+\terr = pfe_phy_init(ndev);\n+\tif (err) {\n+\t\tnetdev_err(ndev, \"%s: pfe_phy_init() failed\\n\",\n+\t\t\t   __func__);\n+\t\tgoto err2;\n+\t}\n+\n+\tif (us) {\n+\t\tif (priv->phydev)\n+\t\t\tphy_start(priv->phydev);\n+\t\treturn 0;\n+\t}\n+\n+\tnetif_carrier_on(ndev);\n+\n+skip_phy_init:\n+\t/* Create all the sysfs files */\n+\tif (pfe_eth_sysfs_init(ndev))\n+\t\tgoto err3;\n+\n+\tnetif_info(priv, probe, ndev, \"%s: created interface, baseaddr: %p\\n\",\n+\t\t   __func__, priv->EMAC_baseaddr);\n+\n+\treturn 0;\n+\n+err3:\n+\tpfe_phy_exit(priv->ndev);\n+err2:\n+\tif (us)\n+\t\tgoto err1;\n+\tunregister_netdev(ndev);\n+err1:\n+\tfree_netdev(priv->ndev);\n+err0:\n+\treturn err;\n+}\n+\n+/* pfe_eth_init\n+ */\n+int pfe_eth_init(struct pfe *pfe)\n+{\n+\tint ii = 0;\n+\tint err;\n+\tstruct ls1012a_pfe_platform_data *pfe_info;\n+\n+\tpr_info(\"%s\\n\", __func__);\n+\n+\tcbus_emac_base[0] = EMAC1_BASE_ADDR;\n+\tcbus_emac_base[1] = EMAC2_BASE_ADDR;\n+\n+\tcbus_gpi_base[0] = EGPI1_BASE_ADDR;\n+\tcbus_gpi_base[1] = EGPI2_BASE_ADDR;\n+\n+\tpfe_info = (struct ls1012a_pfe_platform_data *)\n+\t\t\t\t\tpfe->dev->platform_data;\n+\tif (!pfe_info) {\n+\t\tpr_err(\"%s: pfe missing additional platform data\\n\", __func__);\n+\t\terr = -ENODEV;\n+\t\tgoto err_pdata;\n+\t}\n+\n+\tfor (ii = 0; ii < NUM_GEMAC_SUPPORT; ii++) {\n+\t\terr = pfe_eth_mdio_init(pfe, pfe_info, ii);\n+\t\tif (err) {\n+\t\t\tpr_err(\"%s: pfe_eth_mdio_init() failed\\n\", __func__);\n+\t\t\tgoto err_mdio_init;\n+\t\t}\n+\t}\n+\n+\tif (soc_device_match(ls1012a_rev1_soc_attr))\n+\t\tpfe_errata_a010897 = true;\n+\telse\n+\t\tpfe_errata_a010897 = false;\n+\n+\tfor (ii = 0; ii < NUM_GEMAC_SUPPORT; ii++) {\n+\t\terr = pfe_eth_init_one(pfe, pfe_info, ii);\n+\t\tif (err)\n+\t\t\tgoto err_eth_init;\n+\t}\n+\n+\treturn 0;\n+\n+err_eth_init:\n+\twhile (ii--) {\n+\t\tpfe_eth_exit_one(pfe->eth.eth_priv[ii]);\n+\t\tpfe_eth_mdio_exit(pfe, ii);\n+\t}\n+\n+err_mdio_init:\n+err_pdata:\n+\treturn err;\n+}\n+\n+/* pfe_eth_exit_one\n+ */\n+static void pfe_eth_exit_one(struct pfe_eth_priv_s *priv)\n+{\n+\tnetif_info(priv, probe, priv->ndev, \"%s\\n\", __func__);\n+\n+\tif (!us)\n+\t\tpfe_eth_sysfs_exit(priv->ndev);\n+\n+\tif ((!(pfe_use_old_dts_phy) && !(priv->phy_node)) ||\n+\t    ((pfe_use_old_dts_phy) &&\n+\t      (priv->einfo->phy_flags & GEMAC_NO_PHY))) {\n+\t\tpr_info(\"%s: No PHY or fixed-link\\n\", __func__);\n+\t\tgoto skip_phy_exit;\n+\t}\n+\n+\tpfe_phy_exit(priv->ndev);\n+\n+skip_phy_exit:\n+\tif (!us)\n+\t\tunregister_netdev(priv->ndev);\n+\n+\tfree_netdev(priv->ndev);\n+}\n+\n+/* pfe_eth_exit\n+ */\n+void pfe_eth_exit(struct pfe *pfe)\n+{\n+\tint ii;\n+\n+\tpr_info(\"%s\\n\", __func__);\n+\n+\tfor (ii = NUM_GEMAC_SUPPORT - 1; ii >= 0; ii--)\n+\t\tpfe_eth_exit_one(pfe->eth.eth_priv[ii]);\n+\n+\tfor (ii = NUM_GEMAC_SUPPORT - 1; ii >= 0; ii--)\n+\t\tpfe_eth_mdio_exit(pfe, ii);\n+}\n--- /dev/null\n+++ b/drivers/staging/fsl_ppfe/pfe_eth.h\n@@ -0,0 +1,175 @@\n+/* SPDX-License-Identifier: GPL-2.0+ */\n+/*\n+ * Copyright 2015-2016 Freescale Semiconductor, Inc.\n+ * Copyright 2017 NXP\n+ */\n+\n+#ifndef _PFE_ETH_H_\n+#define _PFE_ETH_H_\n+#include <linux/kernel.h>\n+#include <linux/netdevice.h>\n+#include <linux/etherdevice.h>\n+#include <linux/ethtool.h>\n+#include <linux/mii.h>\n+#include <linux/phy.h>\n+#include <linux/clk.h>\n+#include <linux/interrupt.h>\n+#include <linux/time.h>\n+\n+#define PFE_ETH_NAPI_STATS\n+#define PFE_ETH_TX_STATS\n+\n+#define PFE_ETH_FRAGS_MAX (65536 / HIF_RX_PKT_MIN_SIZE)\n+#define LRO_LEN_COUNT_MAX\t32\n+#define LRO_NB_COUNT_MAX\t32\n+\n+#define PFE_PAUSE_FLAG_ENABLE\t\t1\n+#define PFE_PAUSE_FLAG_AUTONEG\t\t2\n+\n+/* GEMAC configured by SW */\n+/* GEMAC configured by phy lines (not for MII/GMII) */\n+\n+#define GEMAC_SW_FULL_DUPLEX    BIT(9)\n+#define GEMAC_SW_SPEED_10M      (0 << 12)\n+#define GEMAC_SW_SPEED_100M     BIT(12)\n+#define GEMAC_SW_SPEED_1G       (2 << 12)\n+\n+#define GEMAC_NO_PHY            BIT(0)\n+\n+struct ls1012a_eth_platform_data {\n+\t/* board specific information */\n+\tphy_interface_t mii_config;\n+\tu32 phy_flags;\n+\tu32 gem_id;\n+\tu32 phy_id;\n+\tu32 mdio_muxval;\n+\tu8 mac_addr[ETH_ALEN];\n+\tstruct device_node\t*phy_node;\n+};\n+\n+struct ls1012a_mdio_platform_data {\n+\tint id;\n+\tint irq[32];\n+\tu32 phy_mask;\n+\tint mdc_div;\n+};\n+\n+struct ls1012a_pfe_platform_data {\n+\tstruct ls1012a_eth_platform_data ls1012a_eth_pdata[3];\n+\tstruct ls1012a_mdio_platform_data ls1012a_mdio_pdata[3];\n+};\n+\n+#define NUM_GEMAC_SUPPORT\t2\n+#define DRV_NAME\t\t\"pfe-eth\"\n+#define DRV_VERSION\t\t\"1.0\"\n+\n+#define LS1012A_TX_FAST_RECOVERY_TIMEOUT_MS\t3\n+#define TX_POLL_TIMEOUT_MS\t1000\n+\n+#define EMAC_TXQ_CNT\t16\n+#define EMAC_TXQ_DEPTH\t(HIF_TX_DESC_NT)\n+\n+#define JUMBO_FRAME_SIZE_V1\t1900\n+#define JUMBO_FRAME_SIZE_V2\t10258\n+/*\n+ * Client Tx queue threshold, for txQ flush condition.\n+ * It must be smaller than the queue size (in case we ever change it in the\n+ * future).\n+ */\n+#define HIF_CL_TX_FLUSH_MARK\t32\n+\n+/*\n+ * Max number of TX resources (HIF descriptors or skbs) that will be released\n+ * in a single go during batch recycling.\n+ * Should be lower than the flush mark so the SW can provide the HW with a\n+ * continuous stream of packets instead of bursts.\n+ */\n+#define TX_FREE_MAX_COUNT 16\n+#define EMAC_RXQ_CNT\t3\n+#define EMAC_RXQ_DEPTH\tHIF_RX_DESC_NT\n+/* make sure clients can receive a full burst of packets */\n+#define EMAC_RMON_TXBYTES_POS\t0x00\n+#define EMAC_RMON_RXBYTES_POS\t0x14\n+\n+#define EMAC_QUEUENUM_MASK      (emac_txq_cnt - 1)\n+#define EMAC_MDIO_TIMEOUT\t1000\n+#define MAX_UC_SPEC_ADDR_REG 31\n+\n+struct pfe_eth_fast_timer {\n+\tint queuenum;\n+\tstruct hrtimer timer;\n+\tvoid *base;\n+};\n+\n+struct  pfe_eth_priv_s {\n+\tstruct pfe\t\t*pfe;\n+\tstruct hif_client_s\tclient;\n+\tstruct napi_struct\tlro_napi;\n+\tstruct napi_struct\tlow_napi;\n+\tstruct napi_struct\thigh_napi;\n+\tint\t\t\tlow_tmu_q;\n+\tint\t\t\thigh_tmu_q;\n+\tstruct net_device_stats stats;\n+\tstruct net_device\t*ndev;\n+\tint\t\t\tid;\n+\tint\t\t\tpromisc;\n+\tunsigned int\t\tmsg_enable;\n+\tunsigned int\t\tusr_features;\n+\n+\tspinlock_t\t\tlock; /* protect member variables */\n+\tunsigned int\t\tevent_status;\n+\tint\t\t\tirq;\n+\tvoid\t\t\t*EMAC_baseaddr;\n+\tvoid\t\t\t*GPI_baseaddr;\n+\t/* PHY stuff */\n+\tstruct phy_device\t*phydev;\n+\tint\t\t\toldspeed;\n+\tint\t\t\toldduplex;\n+\tint\t\t\toldlink;\n+\tstruct device_node\t*phy_node;\n+\tstruct clk\t\t*gemtx_clk;\n+\tint\t\t\twol;\n+\tint\t\t\tpause_flag;\n+\n+\tint\t\t\tdefault_priority;\n+\tstruct pfe_eth_fast_timer fast_tx_timeout[EMAC_TXQ_CNT];\n+\n+\tstruct ls1012a_eth_platform_data *einfo;\n+\tstruct sk_buff *skb_inflight[EMAC_RXQ_CNT + 6];\n+\n+#ifdef PFE_ETH_TX_STATS\n+\tunsigned int stop_queue_total[EMAC_TXQ_CNT];\n+\tunsigned int stop_queue_hif[EMAC_TXQ_CNT];\n+\tunsigned int stop_queue_hif_client[EMAC_TXQ_CNT];\n+\tunsigned int stop_queue_credit[EMAC_TXQ_CNT];\n+\tunsigned int clean_fail[EMAC_TXQ_CNT];\n+\tunsigned int was_stopped[EMAC_TXQ_CNT];\n+#endif\n+\n+#ifdef PFE_ETH_NAPI_STATS\n+\tunsigned int napi_counters[NAPI_MAX_COUNT];\n+#endif\n+\tunsigned int frags_inflight[EMAC_RXQ_CNT + 6];\n+};\n+\n+struct pfe_eth {\n+\tstruct pfe_eth_priv_s *eth_priv[3];\n+};\n+\n+struct pfe_mdio_priv_s {\n+\tvoid __iomem *mdio_base;\n+\tint\t\t\tmdc_div;\n+\tstruct mii_bus\t\t*mii_bus;\n+};\n+\n+struct pfe_mdio {\n+\tstruct pfe_mdio_priv_s *mdio_priv[3];\n+};\n+\n+int pfe_eth_init(struct pfe *pfe);\n+void pfe_eth_exit(struct pfe *pfe);\n+int pfe_eth_suspend(struct net_device *dev);\n+int pfe_eth_resume(struct net_device *dev);\n+int pfe_eth_mdio_reset(struct mii_bus *bus);\n+\n+#endif /* _PFE_ETH_H_ */\n--- /dev/null\n+++ b/drivers/staging/fsl_ppfe/pfe_firmware.c\n@@ -0,0 +1,398 @@\n+// SPDX-License-Identifier: GPL-2.0+\n+/*\n+ * Copyright 2015-2016 Freescale Semiconductor, Inc.\n+ * Copyright 2017 NXP\n+ */\n+\n+/*\n+ * @file\n+ * Contains all the functions to handle parsing and loading of PE firmware\n+ * files.\n+ */\n+#include <linux/firmware.h>\n+\n+#include \"pfe_mod.h\"\n+#include \"pfe_firmware.h\"\n+#include \"pfe/pfe.h\"\n+#include <linux/of_platform.h>\n+#include <linux/of_address.h>\n+\n+static struct elf32_shdr *get_elf_section_header(const u8 *fw,\n+\t\t\t\t\t\t const char *section)\n+{\n+\tstruct elf32_hdr *elf_hdr = (struct elf32_hdr *)fw;\n+\tstruct elf32_shdr *shdr;\n+\tstruct elf32_shdr *shdr_shstr;\n+\tElf32_Off e_shoff = be32_to_cpu(elf_hdr->e_shoff);\n+\tElf32_Half e_shentsize = be16_to_cpu(elf_hdr->e_shentsize);\n+\tElf32_Half e_shnum = be16_to_cpu(elf_hdr->e_shnum);\n+\tElf32_Half e_shstrndx = be16_to_cpu(elf_hdr->e_shstrndx);\n+\tElf32_Off shstr_offset;\n+\tElf32_Word sh_name;\n+\tconst char *name;\n+\tint i;\n+\n+\t/* Section header strings */\n+\tshdr_shstr = (struct elf32_shdr *)((u8 *)elf_hdr + e_shoff + e_shstrndx\n+\t\t\t\t\t* e_shentsize);\n+\tshstr_offset = be32_to_cpu(shdr_shstr->sh_offset);\n+\n+\tfor (i = 0; i < e_shnum; i++) {\n+\t\tshdr = (struct elf32_shdr *)((u8 *)elf_hdr + e_shoff\n+\t\t\t\t\t     + i * e_shentsize);\n+\n+\t\tsh_name = be32_to_cpu(shdr->sh_name);\n+\n+\t\tname = (const char *)((u8 *)elf_hdr + shstr_offset + sh_name);\n+\n+\t\tif (!strcmp(name, section))\n+\t\t\treturn shdr;\n+\t}\n+\n+\tpr_err(\"%s: didn't find section %s\\n\", __func__, section);\n+\n+\treturn NULL;\n+}\n+\n+#if defined(CFG_DIAGS)\n+static int pfe_get_diags_info(const u8 *fw, struct pfe_diags_info\n+\t\t\t\t*diags_info)\n+{\n+\tstruct elf32_shdr *shdr;\n+\tunsigned long offset, size;\n+\n+\tshdr = get_elf_section_header(fw, \".pfe_diags_str\");\n+\tif (shdr) {\n+\t\toffset = be32_to_cpu(shdr->sh_offset);\n+\t\tsize = be32_to_cpu(shdr->sh_size);\n+\t\tdiags_info->diags_str_base = be32_to_cpu(shdr->sh_addr);\n+\t\tdiags_info->diags_str_size = size;\n+\t\tdiags_info->diags_str_array = kmalloc(size, GFP_KERNEL);\n+\t\tmemcpy(diags_info->diags_str_array, fw + offset, size);\n+\n+\t\treturn 0;\n+\t} else {\n+\t\treturn -1;\n+\t}\n+}\n+#endif\n+\n+static void pfe_check_version_info(const u8 *fw)\n+{\n+\t/*static char *version = NULL;*/\n+\tconst u8 *elf_data = fw;\n+\tstatic char *version;\n+\n+\tstruct elf32_shdr *shdr = get_elf_section_header(fw, \".version\");\n+\n+\tif (shdr) {\n+\t\tif (!version) {\n+\t\t\t/*\n+\t\t\t * this is the first fw we load, use its version\n+\t\t\t * string as reference (whatever it is)\n+\t\t\t */\n+\t\t\tversion = (char *)(elf_data +\n+\t\t\t\t\tbe32_to_cpu(shdr->sh_offset));\n+\n+\t\t\tpr_info(\"PFE binary version: %s\\n\", version);\n+\t\t} else {\n+\t\t\t/*\n+\t\t\t * already have loaded at least one firmware, check\n+\t\t\t * sequence can start now\n+\t\t\t */\n+\t\t\tif (strcmp(version, (char *)(elf_data +\n+\t\t\t\tbe32_to_cpu(shdr->sh_offset)))) {\n+\t\t\t\tpr_info(\n+\t\t\t\t\"WARNING: PFE firmware binaries from incompatible version\\n\");\n+\t\t\t}\n+\t\t}\n+\t} else {\n+\t\t/*\n+\t\t * version cannot be verified, a potential issue that should\n+\t\t * be reported\n+\t\t */\n+\t\tpr_info(\n+\t\t\t \"WARNING: PFE firmware binaries from incompatible version\\n\");\n+\t}\n+}\n+\n+/* PFE elf firmware loader.\n+ * Loads an elf firmware image into a list of PE's (specified using a bitmask)\n+ *\n+ * @param pe_mask\tMask of PE id's to load firmware to\n+ * @param fw\t\tPointer to the firmware image\n+ *\n+ * @return\t\t0 on success, a negative value on error\n+ *\n+ */\n+int pfe_load_elf(int pe_mask, const u8 *fw, struct pfe *pfe)\n+{\n+\tstruct elf32_hdr *elf_hdr = (struct elf32_hdr *)fw;\n+\tElf32_Half sections = be16_to_cpu(elf_hdr->e_shnum);\n+\tstruct elf32_shdr *shdr = (struct elf32_shdr *)(fw +\n+\t\t\t\t\tbe32_to_cpu(elf_hdr->e_shoff));\n+\tint id, section;\n+\tint rc;\n+\n+\tpr_info(\"%s\\n\", __func__);\n+\n+\t/* Some sanity checks */\n+\tif (strncmp(&elf_hdr->e_ident[EI_MAG0], ELFMAG, SELFMAG)) {\n+\t\tpr_err(\"%s: incorrect elf magic number\\n\", __func__);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (elf_hdr->e_ident[EI_CLASS] != ELFCLASS32) {\n+\t\tpr_err(\"%s: incorrect elf class(%x)\\n\", __func__,\n+\t\t       elf_hdr->e_ident[EI_CLASS]);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (elf_hdr->e_ident[EI_DATA] != ELFDATA2MSB) {\n+\t\tpr_err(\"%s: incorrect elf data(%x)\\n\", __func__,\n+\t\t       elf_hdr->e_ident[EI_DATA]);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (be16_to_cpu(elf_hdr->e_type) != ET_EXEC) {\n+\t\tpr_err(\"%s: incorrect elf file type(%x)\\n\", __func__,\n+\t\t       be16_to_cpu(elf_hdr->e_type));\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tfor (section = 0; section < sections; section++, shdr++) {\n+\t\tif (!(be32_to_cpu(shdr->sh_flags) & (SHF_WRITE | SHF_ALLOC |\n+\t\t\tSHF_EXECINSTR)))\n+\t\t\tcontinue;\n+\n+\t\tfor (id = 0; id < MAX_PE; id++)\n+\t\t\tif (pe_mask & (1 << id)) {\n+\t\t\t\trc = pe_load_elf_section(id, elf_hdr, shdr,\n+\t\t\t\t\t\t\t pfe->dev);\n+\t\t\t\tif (rc < 0)\n+\t\t\t\t\tgoto err;\n+\t\t\t}\n+\t}\n+\n+\tpfe_check_version_info(fw);\n+\n+\treturn 0;\n+\n+err:\n+\treturn rc;\n+}\n+\n+int get_firmware_in_fdt(const u8 **pe_fw, const char *name)\n+{\n+\tstruct device_node *np;\n+\tconst unsigned int *len;\n+\tconst void *data;\n+\n+\tif (!strcmp(name, CLASS_FIRMWARE_FILENAME)) {\n+\t\t/* The firmware should be inside the device tree. */\n+\t\tnp = of_find_compatible_node(NULL, NULL,\n+\t\t\t\t\t     \"fsl,pfe-class-firmware\");\n+\t\tif (!np) {\n+\t\t\tpr_info(\"Failed to find the node\\n\");\n+\t\t\treturn -ENOENT;\n+\t\t}\n+\n+\t\tdata = of_get_property(np, \"fsl,class-firmware\", NULL);\n+\t\tif (data) {\n+\t\t\tlen = of_get_property(np, \"length\", NULL);\n+\t\t\tpr_info(\"CLASS fw of length %d bytes loaded from FDT.\\n\",\n+\t\t\t\tbe32_to_cpu(*len));\n+\t\t} else {\n+\t\t\tpr_info(\"fsl,class-firmware not found!!!!\\n\");\n+\t\t\treturn -ENOENT;\n+\t\t}\n+\t\tof_node_put(np);\n+\t\t*pe_fw = data;\n+\t} else if (!strcmp(name, TMU_FIRMWARE_FILENAME)) {\n+\t\tnp = of_find_compatible_node(NULL, NULL,\n+\t\t\t\t\t     \"fsl,pfe-tmu-firmware\");\n+\t\tif (!np) {\n+\t\t\tpr_info(\"Failed to find the node\\n\");\n+\t\t\treturn -ENOENT;\n+\t\t}\n+\n+\t\tdata = of_get_property(np, \"fsl,tmu-firmware\", NULL);\n+\t\tif (data) {\n+\t\t\tlen = of_get_property(np, \"length\", NULL);\n+\t\t\tpr_info(\"TMU fw of length %d bytes loaded from FDT.\\n\",\n+\t\t\t\tbe32_to_cpu(*len));\n+\t\t} else {\n+\t\t\tpr_info(\"fsl,tmu-firmware not found!!!!\\n\");\n+\t\t\treturn -ENOENT;\n+\t\t}\n+\t\tof_node_put(np);\n+\t\t*pe_fw = data;\n+\t} else if (!strcmp(name, UTIL_FIRMWARE_FILENAME)) {\n+\t\tnp = of_find_compatible_node(NULL, NULL,\n+\t\t\t\t\t     \"fsl,pfe-util-firmware\");\n+\t\tif (!np) {\n+\t\t\tpr_info(\"Failed to find the node\\n\");\n+\t\t\treturn -ENOENT;\n+\t\t}\n+\n+\t\tdata = of_get_property(np, \"fsl,util-firmware\", NULL);\n+\t\tif (data) {\n+\t\t\tlen = of_get_property(np, \"length\", NULL);\n+\t\t\tpr_info(\"UTIL fw of length %d bytes loaded from FDT.\\n\",\n+\t\t\t\tbe32_to_cpu(*len));\n+\t\t} else {\n+\t\t\tpr_info(\"fsl,util-firmware not found!!!!\\n\");\n+\t\t\treturn -ENOENT;\n+\t\t}\n+\t\tof_node_put(np);\n+\t\t*pe_fw = data;\n+\t} else {\n+\t\tpr_err(\"firmware:%s not known\\n\", name);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+/* PFE firmware initialization.\n+ * Loads different firmware files from filesystem.\n+ * Initializes PE IMEM/DMEM and UTIL-PE DDR\n+ * Initializes control path symbol addresses (by looking them up in the elf\n+ * firmware files\n+ * Takes PE's out of reset\n+ *\n+ * @return\t0 on success, a negative value on error\n+ *\n+ */\n+int pfe_firmware_init(struct pfe *pfe)\n+{\n+\tconst struct firmware *class_fw, *tmu_fw;\n+\tconst u8 *class_elf_fw, *tmu_elf_fw;\n+\tint rc = 0, fs_load = 0;\n+#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)\n+\tconst struct firmware *util_fw;\n+\tconst u8 *util_elf_fw;\n+\n+#endif\n+\n+\tpr_info(\"%s\\n\", __func__);\n+\n+#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)\n+\tif (get_firmware_in_fdt(&class_elf_fw, CLASS_FIRMWARE_FILENAME) ||\n+\t    get_firmware_in_fdt(&tmu_elf_fw, TMU_FIRMWARE_FILENAME) ||\n+\t    get_firmware_in_fdt(&util_elf_fw, UTIL_FIRMWARE_FILENAME))\n+#else\n+\tif (get_firmware_in_fdt(&class_elf_fw, CLASS_FIRMWARE_FILENAME) ||\n+\t    get_firmware_in_fdt(&tmu_elf_fw, TMU_FIRMWARE_FILENAME))\n+#endif\n+\t{\n+\t\tpr_info(\"%s:PFE firmware not found in FDT.\\n\", __func__);\n+\t\tpr_info(\"%s:Trying to load firmware from filesystem...!\\n\", __func__);\n+\n+\t\t/* look for firmware in filesystem...!*/\n+\t\tfs_load = 1;\n+\t\tif (request_firmware(&class_fw, CLASS_FIRMWARE_FILENAME, pfe->dev)) {\n+\t\t\tpr_err(\"%s: request firmware %s failed\\n\", __func__,\n+\t\t\t       CLASS_FIRMWARE_FILENAME);\n+\t\t\trc = -ETIMEDOUT;\n+\t\t\tgoto err0;\n+\t\t}\n+\t\tclass_elf_fw = class_fw->data;\n+\n+\t\tif (request_firmware(&tmu_fw, TMU_FIRMWARE_FILENAME, pfe->dev)) {\n+\t\t\tpr_err(\"%s: request firmware %s failed\\n\", __func__,\n+\t\t\t       TMU_FIRMWARE_FILENAME);\n+\t\t\trc = -ETIMEDOUT;\n+\t\t\tgoto err1;\n+\t\t}\n+\t\ttmu_elf_fw = tmu_fw->data;\n+\n+#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)\n+\t\tif (request_firmware(&util_fw, UTIL_FIRMWARE_FILENAME, pfe->dev)) {\n+\t\t\tpr_err(\"%s: request firmware %s failed\\n\", __func__,\n+\t\t\t       UTIL_FIRMWARE_FILENAME);\n+\t\t\trc = -ETIMEDOUT;\n+\t\t\tgoto err2;\n+\t\t}\n+\t\tutil_elf_fw = util_fw->data;\n+#endif\n+\t}\n+\n+\trc = pfe_load_elf(CLASS_MASK, class_elf_fw, pfe);\n+\tif (rc < 0) {\n+\t\tpr_err(\"%s: class firmware load failed\\n\", __func__);\n+\t\tgoto err3;\n+\t}\n+\n+#if defined(CFG_DIAGS)\n+\trc = pfe_get_diags_info(class_elf_fw, &pfe->diags.class_diags_info);\n+\tif (rc < 0) {\n+\t\tpr_warn(\n+\t\t\t\"PFE diags won't be available for class PEs\\n\");\n+\t\trc = 0;\n+\t}\n+#endif\n+\n+\trc = pfe_load_elf(TMU_MASK, tmu_elf_fw, pfe);\n+\tif (rc < 0) {\n+\t\tpr_err(\"%s: tmu firmware load failed\\n\", __func__);\n+\t\tgoto err3;\n+\t}\n+\n+#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)\n+\trc = pfe_load_elf(UTIL_MASK, util_elf_fw, pfe);\n+\tif (rc < 0) {\n+\t\tpr_err(\"%s: util firmware load failed\\n\", __func__);\n+\t\tgoto err3;\n+\t}\n+\n+#if defined(CFG_DIAGS)\n+\trc = pfe_get_diags_info(util_elf_fw, &pfe->diags.util_diags_info);\n+\tif (rc < 0) {\n+\t\tpr_warn(\n+\t\t\t\"PFE diags won't be available for util PE\\n\");\n+\t\trc = 0;\n+\t}\n+#endif\n+\n+\tutil_enable();\n+#endif\n+\n+\ttmu_enable(0xf);\n+\tclass_enable();\n+\n+err3:\n+#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)\n+\tif (fs_load)\n+\t\trelease_firmware(util_fw);\n+err2:\n+#endif\n+\tif (fs_load)\n+\t\trelease_firmware(tmu_fw);\n+\n+err1:\n+\tif (fs_load)\n+\t\trelease_firmware(class_fw);\n+\n+err0:\n+\treturn rc;\n+}\n+\n+/* PFE firmware cleanup\n+ * Puts PE's in reset\n+ *\n+ *\n+ */\n+void pfe_firmware_exit(struct pfe *pfe)\n+{\n+\tpr_info(\"%s\\n\", __func__);\n+\n+\tif (pe_reset_all(&pfe->ctrl) != 0)\n+\t\tpr_err(\"Error: Failed to stop PEs, PFE reload may not work correctly\\n\");\n+\n+\tclass_disable();\n+\ttmu_disable(0xf);\n+#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)\n+\tutil_disable();\n+#endif\n+}\n--- /dev/null\n+++ b/drivers/staging/fsl_ppfe/pfe_firmware.h\n@@ -0,0 +1,21 @@\n+/* SPDX-License-Identifier: GPL-2.0+ */\n+/*\n+ * Copyright 2015-2016 Freescale Semiconductor, Inc.\n+ * Copyright 2017 NXP\n+ */\n+\n+#ifndef _PFE_FIRMWARE_H_\n+#define _PFE_FIRMWARE_H_\n+\n+#define CLASS_FIRMWARE_FILENAME\t\t\"ppfe_class_ls1012a.elf\"\n+#define TMU_FIRMWARE_FILENAME\t\t\"ppfe_tmu_ls1012a.elf\"\n+#define UTIL_FIRMWARE_FILENAME\t\t\"ppfe_util_ls1012a.elf\"\n+\n+#define PFE_FW_CHECK_PASS\t\t0\n+#define PFE_FW_CHECK_FAIL\t\t1\n+#define NUM_PFE_FW\t\t\t\t3\n+\n+int pfe_firmware_init(struct pfe *pfe);\n+void pfe_firmware_exit(struct pfe *pfe);\n+\n+#endif /* _PFE_FIRMWARE_H_ */\n--- /dev/null\n+++ b/drivers/staging/fsl_ppfe/pfe_hal.c\n@@ -0,0 +1,1517 @@\n+// SPDX-License-Identifier: GPL-2.0+\n+/*\n+ * Copyright 2015-2016 Freescale Semiconductor, Inc.\n+ * Copyright 2017 NXP\n+ */\n+\n+#include \"pfe_mod.h\"\n+#include \"pfe/pfe.h\"\n+\n+/* A-010897: Jumbo frame is not supported */\n+extern bool pfe_errata_a010897;\n+\n+#define PFE_RCR_MAX_FL_MASK\t0xC000FFFF\n+\n+void *cbus_base_addr;\n+void *ddr_base_addr;\n+unsigned long ddr_phys_base_addr;\n+unsigned int ddr_size;\n+\n+static struct pe_info pe[MAX_PE];\n+\n+/* Initializes the PFE library.\n+ * Must be called before using any of the library functions.\n+ *\n+ * @param[in] cbus_base\t\tCBUS virtual base address (as mapped in\n+ * the host CPU address space)\n+ * @param[in] ddr_base\t\tPFE DDR range virtual base address (as\n+ * mapped in the host CPU address space)\n+ * @param[in] ddr_phys_base\tPFE DDR range physical base address (as\n+ * mapped in platform)\n+ * @param[in] size\t\tPFE DDR range size (as defined by the host\n+ * software)\n+ */\n+void pfe_lib_init(void *cbus_base, void *ddr_base, unsigned long ddr_phys_base,\n+\t\t  unsigned int size)\n+{\n+\tcbus_base_addr = cbus_base;\n+\tddr_base_addr = ddr_base;\n+\tddr_phys_base_addr = ddr_phys_base;\n+\tddr_size = size;\n+\n+\tpe[CLASS0_ID].dmem_base_addr = CLASS_DMEM_BASE_ADDR(0);\n+\tpe[CLASS0_ID].pmem_base_addr = CLASS_IMEM_BASE_ADDR(0);\n+\tpe[CLASS0_ID].pmem_size = CLASS_IMEM_SIZE;\n+\tpe[CLASS0_ID].mem_access_wdata = CLASS_MEM_ACCESS_WDATA;\n+\tpe[CLASS0_ID].mem_access_addr = CLASS_MEM_ACCESS_ADDR;\n+\tpe[CLASS0_ID].mem_access_rdata = CLASS_MEM_ACCESS_RDATA;\n+\n+\tpe[CLASS1_ID].dmem_base_addr = CLASS_DMEM_BASE_ADDR(1);\n+\tpe[CLASS1_ID].pmem_base_addr = CLASS_IMEM_BASE_ADDR(1);\n+\tpe[CLASS1_ID].pmem_size = CLASS_IMEM_SIZE;\n+\tpe[CLASS1_ID].mem_access_wdata = CLASS_MEM_ACCESS_WDATA;\n+\tpe[CLASS1_ID].mem_access_addr = CLASS_MEM_ACCESS_ADDR;\n+\tpe[CLASS1_ID].mem_access_rdata = CLASS_MEM_ACCESS_RDATA;\n+\n+\tpe[CLASS2_ID].dmem_base_addr = CLASS_DMEM_BASE_ADDR(2);\n+\tpe[CLASS2_ID].pmem_base_addr = CLASS_IMEM_BASE_ADDR(2);\n+\tpe[CLASS2_ID].pmem_size = CLASS_IMEM_SIZE;\n+\tpe[CLASS2_ID].mem_access_wdata = CLASS_MEM_ACCESS_WDATA;\n+\tpe[CLASS2_ID].mem_access_addr = CLASS_MEM_ACCESS_ADDR;\n+\tpe[CLASS2_ID].mem_access_rdata = CLASS_MEM_ACCESS_RDATA;\n+\n+\tpe[CLASS3_ID].dmem_base_addr = CLASS_DMEM_BASE_ADDR(3);\n+\tpe[CLASS3_ID].pmem_base_addr = CLASS_IMEM_BASE_ADDR(3);\n+\tpe[CLASS3_ID].pmem_size = CLASS_IMEM_SIZE;\n+\tpe[CLASS3_ID].mem_access_wdata = CLASS_MEM_ACCESS_WDATA;\n+\tpe[CLASS3_ID].mem_access_addr = CLASS_MEM_ACCESS_ADDR;\n+\tpe[CLASS3_ID].mem_access_rdata = CLASS_MEM_ACCESS_RDATA;\n+\n+\tpe[CLASS4_ID].dmem_base_addr = CLASS_DMEM_BASE_ADDR(4);\n+\tpe[CLASS4_ID].pmem_base_addr = CLASS_IMEM_BASE_ADDR(4);\n+\tpe[CLASS4_ID].pmem_size = CLASS_IMEM_SIZE;\n+\tpe[CLASS4_ID].mem_access_wdata = CLASS_MEM_ACCESS_WDATA;\n+\tpe[CLASS4_ID].mem_access_addr = CLASS_MEM_ACCESS_ADDR;\n+\tpe[CLASS4_ID].mem_access_rdata = CLASS_MEM_ACCESS_RDATA;\n+\n+\tpe[CLASS5_ID].dmem_base_addr = CLASS_DMEM_BASE_ADDR(5);\n+\tpe[CLASS5_ID].pmem_base_addr = CLASS_IMEM_BASE_ADDR(5);\n+\tpe[CLASS5_ID].pmem_size = CLASS_IMEM_SIZE;\n+\tpe[CLASS5_ID].mem_access_wdata = CLASS_MEM_ACCESS_WDATA;\n+\tpe[CLASS5_ID].mem_access_addr = CLASS_MEM_ACCESS_ADDR;\n+\tpe[CLASS5_ID].mem_access_rdata = CLASS_MEM_ACCESS_RDATA;\n+\n+\tpe[TMU0_ID].dmem_base_addr = TMU_DMEM_BASE_ADDR(0);\n+\tpe[TMU0_ID].pmem_base_addr = TMU_IMEM_BASE_ADDR(0);\n+\tpe[TMU0_ID].pmem_size = TMU_IMEM_SIZE;\n+\tpe[TMU0_ID].mem_access_wdata = TMU_MEM_ACCESS_WDATA;\n+\tpe[TMU0_ID].mem_access_addr = TMU_MEM_ACCESS_ADDR;\n+\tpe[TMU0_ID].mem_access_rdata = TMU_MEM_ACCESS_RDATA;\n+\n+\tpe[TMU1_ID].dmem_base_addr = TMU_DMEM_BASE_ADDR(1);\n+\tpe[TMU1_ID].pmem_base_addr = TMU_IMEM_BASE_ADDR(1);\n+\tpe[TMU1_ID].pmem_size = TMU_IMEM_SIZE;\n+\tpe[TMU1_ID].mem_access_wdata = TMU_MEM_ACCESS_WDATA;\n+\tpe[TMU1_ID].mem_access_addr = TMU_MEM_ACCESS_ADDR;\n+\tpe[TMU1_ID].mem_access_rdata = TMU_MEM_ACCESS_RDATA;\n+\n+\tpe[TMU3_ID].dmem_base_addr = TMU_DMEM_BASE_ADDR(3);\n+\tpe[TMU3_ID].pmem_base_addr = TMU_IMEM_BASE_ADDR(3);\n+\tpe[TMU3_ID].pmem_size = TMU_IMEM_SIZE;\n+\tpe[TMU3_ID].mem_access_wdata = TMU_MEM_ACCESS_WDATA;\n+\tpe[TMU3_ID].mem_access_addr = TMU_MEM_ACCESS_ADDR;\n+\tpe[TMU3_ID].mem_access_rdata = TMU_MEM_ACCESS_RDATA;\n+\n+#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)\n+\tpe[UTIL_ID].dmem_base_addr = UTIL_DMEM_BASE_ADDR;\n+\tpe[UTIL_ID].mem_access_wdata = UTIL_MEM_ACCESS_WDATA;\n+\tpe[UTIL_ID].mem_access_addr = UTIL_MEM_ACCESS_ADDR;\n+\tpe[UTIL_ID].mem_access_rdata = UTIL_MEM_ACCESS_RDATA;\n+#endif\n+}\n+\n+/* Writes a buffer to PE internal memory from the host\n+ * through indirect access registers.\n+ *\n+ * @param[in] id\t\tPE identification (CLASS0_ID, ..., TMU0_ID,\n+ * ..., UTIL_ID)\n+ * @param[in] src\t\tBuffer source address\n+ * @param[in] mem_access_addr\tDMEM destination address (must be 32bit\n+ * aligned)\n+ * @param[in] len\t\tNumber of bytes to copy\n+ */\n+void pe_mem_memcpy_to32(int id, u32 mem_access_addr, const void *src, unsigned\n+int len)\n+{\n+\tu32 offset = 0, val, addr;\n+\tunsigned int len32 = len >> 2;\n+\tint i;\n+\n+\taddr = mem_access_addr | PE_MEM_ACCESS_WRITE |\n+\t\tPE_MEM_ACCESS_BYTE_ENABLE(0, 4);\n+\n+\tfor (i = 0; i < len32; i++, offset += 4, src += 4) {\n+\t\tval = *(u32 *)src;\n+\t\twritel(cpu_to_be32(val), pe[id].mem_access_wdata);\n+\t\twritel(addr + offset, pe[id].mem_access_addr);\n+\t}\n+\n+\tlen = (len & 0x3);\n+\tif (len) {\n+\t\tval = 0;\n+\n+\t\taddr = (mem_access_addr | PE_MEM_ACCESS_WRITE |\n+\t\t\tPE_MEM_ACCESS_BYTE_ENABLE(0, len)) + offset;\n+\n+\t\tfor (i = 0; i < len; i++, src++)\n+\t\t\tval |= (*(u8 *)src) << (8 * i);\n+\n+\t\twritel(cpu_to_be32(val), pe[id].mem_access_wdata);\n+\t\twritel(addr, pe[id].mem_access_addr);\n+\t}\n+}\n+\n+/* Writes a buffer to PE internal data memory (DMEM) from the host\n+ * through indirect access registers.\n+ * @param[in] id\t\tPE identification (CLASS0_ID, ..., TMU0_ID,\n+ * ..., UTIL_ID)\n+ * @param[in] src\t\tBuffer source address\n+ * @param[in] dst\t\tDMEM destination address (must be 32bit\n+ * aligned)\n+ * @param[in] len\t\tNumber of bytes to copy\n+ */\n+void pe_dmem_memcpy_to32(int id, u32 dst, const void *src, unsigned int len)\n+{\n+\tpe_mem_memcpy_to32(id, pe[id].dmem_base_addr | dst |\n+\t\t\t\tPE_MEM_ACCESS_DMEM, src, len);\n+}\n+\n+/* Writes a buffer to PE internal program memory (PMEM) from the host\n+ * through indirect access registers.\n+ * @param[in] id\t\tPE identification (CLASS0_ID, ..., TMU0_ID,\n+ * ..., TMU3_ID)\n+ * @param[in] src\t\tBuffer source address\n+ * @param[in] dst\t\tPMEM destination address (must be 32bit\n+ * aligned)\n+ * @param[in] len\t\tNumber of bytes to copy\n+ */\n+void pe_pmem_memcpy_to32(int id, u32 dst, const void *src, unsigned int len)\n+{\n+\tpe_mem_memcpy_to32(id, pe[id].pmem_base_addr | (dst & (pe[id].pmem_size\n+\t\t\t\t- 1)) | PE_MEM_ACCESS_IMEM, src, len);\n+}\n+\n+/* Reads PE internal program memory (IMEM) from the host\n+ * through indirect access registers.\n+ * @param[in] id\t\tPE identification (CLASS0_ID, ..., TMU0_ID,\n+ * ..., TMU3_ID)\n+ * @param[in] addr\t\tPMEM read address (must be aligned on size)\n+ * @param[in] size\t\tNumber of bytes to read (maximum 4, must not\n+ * cross 32bit boundaries)\n+ * @return\t\t\tthe data read (in PE endianness, i.e BE).\n+ */\n+u32 pe_pmem_read(int id, u32 addr, u8 size)\n+{\n+\tu32 offset = addr & 0x3;\n+\tu32 mask = 0xffffffff >> ((4 - size) << 3);\n+\tu32 val;\n+\n+\taddr = pe[id].pmem_base_addr | ((addr & ~0x3) & (pe[id].pmem_size - 1))\n+\t\t| PE_MEM_ACCESS_IMEM | PE_MEM_ACCESS_BYTE_ENABLE(offset, size);\n+\n+\twritel(addr, pe[id].mem_access_addr);\n+\tval = be32_to_cpu(readl(pe[id].mem_access_rdata));\n+\n+\treturn (val >> (offset << 3)) & mask;\n+}\n+\n+/* Writes PE internal data memory (DMEM) from the host\n+ * through indirect access registers.\n+ * @param[in] id\t\tPE identification (CLASS0_ID, ..., TMU0_ID,\n+ * ..., UTIL_ID)\n+ * @param[in] addr\t\tDMEM write address (must be aligned on size)\n+ * @param[in] val\t\tValue to write (in PE endianness, i.e BE)\n+ * @param[in] size\t\tNumber of bytes to write (maximum 4, must not\n+ * cross 32bit boundaries)\n+ */\n+void pe_dmem_write(int id, u32 val, u32 addr, u8 size)\n+{\n+\tu32 offset = addr & 0x3;\n+\n+\taddr = pe[id].dmem_base_addr | (addr & ~0x3) | PE_MEM_ACCESS_WRITE |\n+\t\tPE_MEM_ACCESS_DMEM | PE_MEM_ACCESS_BYTE_ENABLE(offset, size);\n+\n+\t/* Indirect access interface is byte swapping data being written */\n+\twritel(cpu_to_be32(val << (offset << 3)), pe[id].mem_access_wdata);\n+\twritel(addr, pe[id].mem_access_addr);\n+}\n+\n+/* Reads PE internal data memory (DMEM) from the host\n+ * through indirect access registers.\n+ * @param[in] id\t\tPE identification (CLASS0_ID, ..., TMU0_ID,\n+ * ..., UTIL_ID)\n+ * @param[in] addr\t\tDMEM read address (must be aligned on size)\n+ * @param[in] size\t\tNumber of bytes to read (maximum 4, must not\n+ * cross 32bit boundaries)\n+ * @return\t\t\tthe data read (in PE endianness, i.e BE).\n+ */\n+u32 pe_dmem_read(int id, u32 addr, u8 size)\n+{\n+\tu32 offset = addr & 0x3;\n+\tu32 mask = 0xffffffff >> ((4 - size) << 3);\n+\tu32 val;\n+\n+\taddr = pe[id].dmem_base_addr | (addr & ~0x3) | PE_MEM_ACCESS_DMEM |\n+\t\t\tPE_MEM_ACCESS_BYTE_ENABLE(offset, size);\n+\n+\twritel(addr, pe[id].mem_access_addr);\n+\n+\t/* Indirect access interface is byte swapping data being read */\n+\tval = be32_to_cpu(readl(pe[id].mem_access_rdata));\n+\n+\treturn (val >> (offset << 3)) & mask;\n+}\n+\n+/* This function is used to write to CLASS internal bus peripherals (ccu,\n+ * pe-lem) from the host\n+ * through indirect access registers.\n+ * @param[in]\tval\tvalue to write\n+ * @param[in]\taddr\tAddress to write to (must be aligned on size)\n+ * @param[in]\tsize\tNumber of bytes to write (1, 2 or 4)\n+ *\n+ */\n+void class_bus_write(u32 val, u32 addr, u8 size)\n+{\n+\tu32 offset = addr & 0x3;\n+\n+\twritel((addr & CLASS_BUS_ACCESS_BASE_MASK), CLASS_BUS_ACCESS_BASE);\n+\n+\taddr = (addr & ~CLASS_BUS_ACCESS_BASE_MASK) | PE_MEM_ACCESS_WRITE |\n+\t\t\t(size << 24);\n+\n+\twritel(cpu_to_be32(val << (offset << 3)), CLASS_BUS_ACCESS_WDATA);\n+\twritel(addr, CLASS_BUS_ACCESS_ADDR);\n+}\n+\n+/* Reads from CLASS internal bus peripherals (ccu, pe-lem) from the host\n+ * through indirect access registers.\n+ * @param[in] addr\tAddress to read from (must be aligned on size)\n+ * @param[in] size\tNumber of bytes to read (1, 2 or 4)\n+ * @return\t\tthe read data\n+ *\n+ */\n+u32 class_bus_read(u32 addr, u8 size)\n+{\n+\tu32 offset = addr & 0x3;\n+\tu32 mask = 0xffffffff >> ((4 - size) << 3);\n+\tu32 val;\n+\n+\twritel((addr & CLASS_BUS_ACCESS_BASE_MASK), CLASS_BUS_ACCESS_BASE);\n+\n+\taddr = (addr & ~CLASS_BUS_ACCESS_BASE_MASK) | (size << 24);\n+\n+\twritel(addr, CLASS_BUS_ACCESS_ADDR);\n+\tval = be32_to_cpu(readl(CLASS_BUS_ACCESS_RDATA));\n+\n+\treturn (val >> (offset << 3)) & mask;\n+}\n+\n+/* Writes data to the cluster memory (PE_LMEM)\n+ * @param[in] dst\tPE LMEM destination address (must be 32bit aligned)\n+ * @param[in] src\tBuffer source address\n+ * @param[in] len\tNumber of bytes to copy\n+ */\n+void class_pe_lmem_memcpy_to32(u32 dst, const void *src, unsigned int len)\n+{\n+\tu32 len32 = len >> 2;\n+\tint i;\n+\n+\tfor (i = 0; i < len32; i++, src += 4, dst += 4)\n+\t\tclass_bus_write(*(u32 *)src, dst, 4);\n+\n+\tif (len & 0x2) {\n+\t\tclass_bus_write(*(u16 *)src, dst, 2);\n+\t\tsrc += 2;\n+\t\tdst += 2;\n+\t}\n+\n+\tif (len & 0x1) {\n+\t\tclass_bus_write(*(u8 *)src, dst, 1);\n+\t\tsrc++;\n+\t\tdst++;\n+\t}\n+}\n+\n+/* Writes value to the cluster memory (PE_LMEM)\n+ * @param[in] dst\tPE LMEM destination address (must be 32bit aligned)\n+ * @param[in] val\tValue to write\n+ * @param[in] len\tNumber of bytes to write\n+ */\n+void class_pe_lmem_memset(u32 dst, int val, unsigned int len)\n+{\n+\tu32 len32 = len >> 2;\n+\tint i;\n+\n+\tval = val | (val << 8) | (val << 16) | (val << 24);\n+\n+\tfor (i = 0; i < len32; i++, dst += 4)\n+\t\tclass_bus_write(val, dst, 4);\n+\n+\tif (len & 0x2) {\n+\t\tclass_bus_write(val, dst, 2);\n+\t\tdst += 2;\n+\t}\n+\n+\tif (len & 0x1) {\n+\t\tclass_bus_write(val, dst, 1);\n+\t\tdst++;\n+\t}\n+}\n+\n+#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)\n+\n+/* Writes UTIL program memory (DDR) from the host.\n+ *\n+ * @param[in] addr\tAddress to write (virtual, must be aligned on size)\n+ * @param[in] val\t\tValue to write (in PE endianness, i.e BE)\n+ * @param[in] size\t\tNumber of bytes to write (2 or 4)\n+ */\n+static void util_pmem_write(u32 val, void *addr, u8 size)\n+{\n+\tvoid *addr64 = (void *)((unsigned long)addr & ~0x7);\n+\tunsigned long off = 8 - ((unsigned long)addr & 0x7) - size;\n+\n+\t/*\n+\t * IMEM should  be loaded as a 64bit swapped value in a 64bit aligned\n+\t * location\n+\t */\n+\tif (size == 4)\n+\t\twritel(be32_to_cpu(val), addr64 + off);\n+\telse\n+\t\twritew(be16_to_cpu((u16)val), addr64 + off);\n+}\n+\n+/* Writes a buffer to UTIL program memory (DDR) from the host.\n+ *\n+ * @param[in] dst\tAddress to write (virtual, must be at least 16bit\n+ * aligned)\n+ * @param[in] src\tBuffer to write (in PE endianness, i.e BE, must have\n+ * same alignment as dst)\n+ * @param[in] len\tNumber of bytes to write (must be at least 16bit\n+ * aligned)\n+ */\n+static void util_pmem_memcpy(void *dst, const void *src, unsigned int len)\n+{\n+\tunsigned int len32;\n+\tint i;\n+\n+\tif ((unsigned long)src & 0x2) {\n+\t\tutil_pmem_write(*(u16 *)src, dst, 2);\n+\t\tsrc += 2;\n+\t\tdst += 2;\n+\t\tlen -= 2;\n+\t}\n+\n+\tlen32 = len >> 2;\n+\n+\tfor (i = 0; i < len32; i++, dst += 4, src += 4)\n+\t\tutil_pmem_write(*(u32 *)src, dst, 4);\n+\n+\tif (len & 0x2)\n+\t\tutil_pmem_write(*(u16 *)src, dst, len & 0x2);\n+}\n+#endif\n+\n+/* Loads an elf section into pmem\n+ * Code needs to be at least 16bit aligned and only PROGBITS sections are\n+ * supported\n+ *\n+ * @param[in] id\tPE identification (CLASS0_ID, ..., TMU0_ID, ...,\n+ * TMU3_ID)\n+ * @param[in] data\tpointer to the elf firmware\n+ * @param[in] shdr\tpointer to the elf section header\n+ *\n+ */\n+static int pe_load_pmem_section(int id, const void *data,\n+\t\t\t\tstruct elf32_shdr *shdr)\n+{\n+\tu32 offset = be32_to_cpu(shdr->sh_offset);\n+\tu32 addr = be32_to_cpu(shdr->sh_addr);\n+\tu32 size = be32_to_cpu(shdr->sh_size);\n+\tu32 type = be32_to_cpu(shdr->sh_type);\n+\n+#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)\n+\tif (id == UTIL_ID) {\n+\t\tpr_err(\"%s: unsupported pmem section for UTIL\\n\",\n+\t\t       __func__);\n+\t\treturn -EINVAL;\n+\t}\n+#endif\n+\n+\tif (((unsigned long)(data + offset) & 0x3) != (addr & 0x3)) {\n+\t\tpr_err(\n+\t\t\t\"%s: load address(%x) and elf file address(%lx) don't have the same alignment\\n\"\n+\t\t\t, __func__, addr, (unsigned long)data + offset);\n+\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (addr & 0x1) {\n+\t\tpr_err(\"%s: load address(%x) is not 16bit aligned\\n\",\n+\t\t       __func__, addr);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (size & 0x1) {\n+\t\tpr_err(\"%s: load size(%x) is not 16bit aligned\\n\",\n+\t\t       __func__, size);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tswitch (type) {\n+\tcase SHT_PROGBITS:\n+\t\tpe_pmem_memcpy_to32(id, addr, data + offset, size);\n+\n+\t\tbreak;\n+\n+\tdefault:\n+\t\tpr_err(\"%s: unsupported section type(%x)\\n\", __func__,\n+\t\t       type);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+/* Loads an elf section into dmem\n+ * Data needs to be at least 32bit aligned, NOBITS sections are correctly\n+ * initialized to 0\n+ *\n+ * @param[in] id\t\tPE identification (CLASS0_ID, ..., TMU0_ID,\n+ * ..., UTIL_ID)\n+ * @param[in] data\t\tpointer to the elf firmware\n+ * @param[in] shdr\t\tpointer to the elf section header\n+ *\n+ */\n+static int pe_load_dmem_section(int id, const void *data,\n+\t\t\t\tstruct elf32_shdr *shdr)\n+{\n+\tu32 offset = be32_to_cpu(shdr->sh_offset);\n+\tu32 addr = be32_to_cpu(shdr->sh_addr);\n+\tu32 size = be32_to_cpu(shdr->sh_size);\n+\tu32 type = be32_to_cpu(shdr->sh_type);\n+\tu32 size32 = size >> 2;\n+\tint i;\n+\n+\tif (((unsigned long)(data + offset) & 0x3) != (addr & 0x3)) {\n+\t\tpr_err(\n+\t\t\t\"%s: load address(%x) and elf file address(%lx) don't have the same alignment\\n\",\n+\t\t\t__func__, addr, (unsigned long)data + offset);\n+\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (addr & 0x3) {\n+\t\tpr_err(\"%s: load address(%x) is not 32bit aligned\\n\",\n+\t\t       __func__, addr);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tswitch (type) {\n+\tcase SHT_PROGBITS:\n+\t\tpe_dmem_memcpy_to32(id, addr, data + offset, size);\n+\t\tbreak;\n+\n+\tcase SHT_NOBITS:\n+\t\tfor (i = 0; i < size32; i++, addr += 4)\n+\t\t\tpe_dmem_write(id, 0, addr, 4);\n+\n+\t\tif (size & 0x3)\n+\t\t\tpe_dmem_write(id, 0, addr, size & 0x3);\n+\n+\t\tbreak;\n+\n+\tdefault:\n+\t\tpr_err(\"%s: unsupported section type(%x)\\n\", __func__,\n+\t\t       type);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+/* Loads an elf section into DDR\n+ * Data needs to be at least 32bit aligned, NOBITS sections are correctly\n+ * initialized to 0\n+ *\n+ * @param[in] id\t\tPE identification (CLASS0_ID, ..., TMU0_ID,\n+ * ..., UTIL_ID)\n+ * @param[in] data\t\tpointer to the elf firmware\n+ * @param[in] shdr\t\tpointer to the elf section header\n+ *\n+ */\n+static int pe_load_ddr_section(int id, const void *data,\n+\t\t\t       struct elf32_shdr *shdr,\n+\t\t\t       struct device *dev) {\n+\tu32 offset = be32_to_cpu(shdr->sh_offset);\n+\tu32 addr = be32_to_cpu(shdr->sh_addr);\n+\tu32 size = be32_to_cpu(shdr->sh_size);\n+\tu32 type = be32_to_cpu(shdr->sh_type);\n+\tu32 flags = be32_to_cpu(shdr->sh_flags);\n+\n+\tswitch (type) {\n+\tcase SHT_PROGBITS:\n+\t\tif (flags & SHF_EXECINSTR) {\n+\t\t\tif (id <= CLASS_MAX_ID) {\n+\t\t\t\t/* DO the loading only once in DDR */\n+\t\t\t\tif (id == CLASS0_ID) {\n+\t\t\t\t\tpr_err(\n+\t\t\t\t\t\t\"%s: load address(%x) and elf file address(%lx) rcvd\\n\",\n+\t\t\t\t\t\t__func__, addr,\n+\t\t\t\t\t\t(unsigned long)data + offset);\n+\t\t\t\t\tif (((unsigned long)(data + offset)\n+\t\t\t\t\t\t& 0x3) != (addr & 0x3)) {\n+\t\t\t\t\t\tpr_err(\n+\t\t\t\t\t\t\t\"%s: load address(%x) and elf file address(%lx) don't have the same alignment\\n\"\n+\t\t\t\t\t\t\t, __func__, addr,\n+\t\t\t\t\t\t(unsigned long)data + offset);\n+\n+\t\t\t\t\t\treturn -EINVAL;\n+\t\t\t\t\t}\n+\n+\t\t\t\t\tif (addr & 0x1) {\n+\t\t\t\t\t\tpr_err(\n+\t\t\t\t\t\t\t\"%s: load address(%x) is not 16bit aligned\\n\"\n+\t\t\t\t\t\t\t, __func__, addr);\n+\t\t\t\t\t\treturn -EINVAL;\n+\t\t\t\t\t}\n+\n+\t\t\t\t\tif (size & 0x1) {\n+\t\t\t\t\t\tpr_err(\n+\t\t\t\t\t\t\t\"%s: load length(%x) is not 16bit aligned\\n\"\n+\t\t\t\t\t\t\t, __func__, size);\n+\t\t\t\t\t\treturn -EINVAL;\n+\t\t\t\t\t}\n+\t\t\t\t\tmemcpy(DDR_PHYS_TO_VIRT(\n+\t\t\t\t\t\tDDR_PFE_TO_PHYS(addr)),\n+\t\t\t\t\t\tdata + offset, size);\n+\t\t\t\t}\n+#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)\n+\t\t\t} else if (id == UTIL_ID) {\n+\t\t\t\tif (((unsigned long)(data + offset) & 0x3)\n+\t\t\t\t\t!= (addr & 0x3)) {\n+\t\t\t\t\tpr_err(\n+\t\t\t\t\t\t\"%s: load address(%x) and elf file address(%lx) don't have the same alignment\\n\"\n+\t\t\t\t\t\t, __func__, addr,\n+\t\t\t\t\t\t(unsigned long)data + offset);\n+\n+\t\t\t\t\treturn -EINVAL;\n+\t\t\t\t}\n+\n+\t\t\t\tif (addr & 0x1) {\n+\t\t\t\t\tpr_err(\n+\t\t\t\t\t\t\"%s: load address(%x) is not 16bit aligned\\n\"\n+\t\t\t\t\t\t, __func__, addr);\n+\t\t\t\t\treturn -EINVAL;\n+\t\t\t\t}\n+\n+\t\t\t\tif (size & 0x1) {\n+\t\t\t\t\tpr_err(\n+\t\t\t\t\t\t\"%s: load length(%x) is not 16bit aligned\\n\"\n+\t\t\t\t\t\t, __func__, size);\n+\t\t\t\t\treturn -EINVAL;\n+\t\t\t\t}\n+\n+\t\t\t\tutil_pmem_memcpy(DDR_PHYS_TO_VIRT(\n+\t\t\t\t\t\t\tDDR_PFE_TO_PHYS(addr)),\n+\t\t\t\t\t\t\tdata + offset, size);\n+\t\t\t}\n+#endif\n+\t\t\t} else {\n+\t\t\t\tpr_err(\n+\t\t\t\t\t\"%s: unsupported ddr section type(%x) for PE(%d)\\n\"\n+\t\t\t\t\t\t, __func__, type, id);\n+\t\t\t\treturn -EINVAL;\n+\t\t\t}\n+\n+\t\t} else {\n+\t\t\tmemcpy(DDR_PHYS_TO_VIRT(DDR_PFE_TO_PHYS(addr)), data\n+\t\t\t\t+ offset, size);\n+\t\t}\n+\n+\t\tbreak;\n+\n+\tcase SHT_NOBITS:\n+\t\tmemset(DDR_PHYS_TO_VIRT(DDR_PFE_TO_PHYS(addr)), 0, size);\n+\n+\t\tbreak;\n+\n+\tdefault:\n+\t\tpr_err(\"%s: unsupported section type(%x)\\n\", __func__,\n+\t\t       type);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+/* Loads an elf section into pe lmem\n+ * Data needs to be at least 32bit aligned, NOBITS sections are correctly\n+ * initialized to 0\n+ *\n+ * @param[in] id\t\tPE identification (CLASS0_ID,..., CLASS5_ID)\n+ * @param[in] data\t\tpointer to the elf firmware\n+ * @param[in] shdr\t\tpointer to the elf section header\n+ *\n+ */\n+static int pe_load_pe_lmem_section(int id, const void *data,\n+\t\t\t\t   struct elf32_shdr *shdr)\n+{\n+\tu32 offset = be32_to_cpu(shdr->sh_offset);\n+\tu32 addr = be32_to_cpu(shdr->sh_addr);\n+\tu32 size = be32_to_cpu(shdr->sh_size);\n+\tu32 type = be32_to_cpu(shdr->sh_type);\n+\n+\tif (id > CLASS_MAX_ID) {\n+\t\tpr_err(\n+\t\t\t\"%s: unsupported pe-lmem section type(%x) for PE(%d)\\n\",\n+\t\t\t __func__, type, id);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (((unsigned long)(data + offset) & 0x3) != (addr & 0x3)) {\n+\t\tpr_err(\n+\t\t\t\"%s: load address(%x) and elf file address(%lx) don't have the same alignment\\n\",\n+\t\t\t__func__, addr, (unsigned long)data + offset);\n+\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (addr & 0x3) {\n+\t\tpr_err(\"%s: load address(%x) is not 32bit aligned\\n\",\n+\t\t       __func__, addr);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tswitch (type) {\n+\tcase SHT_PROGBITS:\n+\t\tclass_pe_lmem_memcpy_to32(addr, data + offset, size);\n+\t\tbreak;\n+\n+\tcase SHT_NOBITS:\n+\t\tclass_pe_lmem_memset(addr, 0, size);\n+\t\tbreak;\n+\n+\tdefault:\n+\t\tpr_err(\"%s: unsupported section type(%x)\\n\", __func__,\n+\t\t       type);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+/* Loads an elf section into a PE\n+ * For now only supports loading a section to dmem (all PE's), pmem (class and\n+ * tmu PE's),\n+ * DDDR (util PE code)\n+ *\n+ * @param[in] id\t\tPE identification (CLASS0_ID, ..., TMU0_ID,\n+ * ..., UTIL_ID)\n+ * @param[in] data\t\tpointer to the elf firmware\n+ * @param[in] shdr\t\tpointer to the elf section header\n+ *\n+ */\n+int pe_load_elf_section(int id, const void *data, struct elf32_shdr *shdr,\n+\t\t\tstruct device *dev) {\n+\tu32 addr = be32_to_cpu(shdr->sh_addr);\n+\tu32 size = be32_to_cpu(shdr->sh_size);\n+\n+\tif (IS_DMEM(addr, size))\n+\t\treturn pe_load_dmem_section(id, data, shdr);\n+\telse if (IS_PMEM(addr, size))\n+\t\treturn pe_load_pmem_section(id, data, shdr);\n+\telse if (IS_PFE_LMEM(addr, size))\n+\t\treturn 0;\n+\telse if (IS_PHYS_DDR(addr, size))\n+\t\treturn pe_load_ddr_section(id, data, shdr, dev);\n+\telse if (IS_PE_LMEM(addr, size))\n+\t\treturn pe_load_pe_lmem_section(id, data, shdr);\n+\n+\tpr_err(\"%s: unsupported memory range(%x)\\n\", __func__,\n+\t       addr);\n+\treturn 0;\n+}\n+\n+/**************************** BMU ***************************/\n+\n+/* Initializes a BMU block.\n+ * @param[in] base\tBMU block base address\n+ * @param[in] cfg\tBMU configuration\n+ */\n+void bmu_init(void *base, struct BMU_CFG *cfg)\n+{\n+\tbmu_disable(base);\n+\n+\tbmu_set_config(base, cfg);\n+\n+\tbmu_reset(base);\n+}\n+\n+/* Resets a BMU block.\n+ * @param[in] base\tBMU block base address\n+ */\n+void bmu_reset(void *base)\n+{\n+\twritel(CORE_SW_RESET, base + BMU_CTRL);\n+\n+\t/* Wait for self clear */\n+\twhile (readl(base + BMU_CTRL) & CORE_SW_RESET)\n+\t\t;\n+}\n+\n+/* Enabled a BMU block.\n+ * @param[in] base\tBMU block base address\n+ */\n+void bmu_enable(void *base)\n+{\n+\twritel(CORE_ENABLE, base + BMU_CTRL);\n+}\n+\n+/* Disables a BMU block.\n+ * @param[in] base\tBMU block base address\n+ */\n+void bmu_disable(void *base)\n+{\n+\twritel(CORE_DISABLE, base + BMU_CTRL);\n+}\n+\n+/* Sets the configuration of a BMU block.\n+ * @param[in] base\tBMU block base address\n+ * @param[in] cfg\tBMU configuration\n+ */\n+void bmu_set_config(void *base, struct BMU_CFG *cfg)\n+{\n+\twritel(cfg->baseaddr, base + BMU_UCAST_BASE_ADDR);\n+\twritel(cfg->count & 0xffff, base + BMU_UCAST_CONFIG);\n+\twritel(cfg->size & 0xffff, base + BMU_BUF_SIZE);\n+\n+\t/* Interrupts are never used */\n+\twritel(cfg->low_watermark, base + BMU_LOW_WATERMARK);\n+\twritel(cfg->high_watermark, base + BMU_HIGH_WATERMARK);\n+\twritel(0x0, base + BMU_INT_ENABLE);\n+}\n+\n+/**************************** MTIP GEMAC ***************************/\n+\n+/* Enable Rx Checksum Engine. With this enabled, Frame with bad IP,\n+ *   TCP or UDP checksums are discarded\n+ *\n+ * @param[in] base\tGEMAC base address.\n+ */\n+void gemac_enable_rx_checksum_offload(void *base)\n+{\n+\t/*Do not find configuration to do this */\n+}\n+\n+/* Disable Rx Checksum Engine.\n+ *\n+ * @param[in] base\tGEMAC base address.\n+ */\n+void gemac_disable_rx_checksum_offload(void *base)\n+{\n+\t/*Do not find configuration to do this */\n+}\n+\n+/* GEMAC set speed.\n+ * @param[in] base\tGEMAC base address\n+ * @param[in] speed\tGEMAC speed (10, 100 or 1000 Mbps)\n+ */\n+void gemac_set_speed(void *base, enum mac_speed gem_speed)\n+{\n+\tu32 ecr = readl(base + EMAC_ECNTRL_REG) & ~EMAC_ECNTRL_SPEED;\n+\tu32 rcr = readl(base + EMAC_RCNTRL_REG) & ~EMAC_RCNTRL_RMII_10T;\n+\n+\tswitch (gem_speed) {\n+\tcase SPEED_10M:\n+\t\t\trcr |= EMAC_RCNTRL_RMII_10T;\n+\t\t\tbreak;\n+\n+\tcase SPEED_1000M:\n+\t\t\tecr |= EMAC_ECNTRL_SPEED;\n+\t\t\tbreak;\n+\n+\tcase SPEED_100M:\n+\tdefault:\n+\t\t\t/*It is in 100M mode */\n+\t\t\tbreak;\n+\t}\n+\twritel(ecr, (base + EMAC_ECNTRL_REG));\n+\twritel(rcr, (base + EMAC_RCNTRL_REG));\n+}\n+\n+/* GEMAC set duplex.\n+ * @param[in] base\tGEMAC base address\n+ * @param[in] duplex\tGEMAC duplex mode (Full, Half)\n+ */\n+void gemac_set_duplex(void *base, int duplex)\n+{\n+\tif (duplex == DUPLEX_HALF) {\n+\t\twritel(readl(base + EMAC_TCNTRL_REG) & ~EMAC_TCNTRL_FDEN, base\n+\t\t\t+ EMAC_TCNTRL_REG);\n+\t\twritel(readl(base + EMAC_RCNTRL_REG) | EMAC_RCNTRL_DRT, (base\n+\t\t\t+ EMAC_RCNTRL_REG));\n+\t} else{\n+\t\twritel(readl(base + EMAC_TCNTRL_REG) | EMAC_TCNTRL_FDEN, base\n+\t\t\t+ EMAC_TCNTRL_REG);\n+\t\twritel(readl(base + EMAC_RCNTRL_REG) & ~EMAC_RCNTRL_DRT, (base\n+\t\t\t+ EMAC_RCNTRL_REG));\n+\t}\n+}\n+\n+/* GEMAC set mode.\n+ * @param[in] base\tGEMAC base address\n+ * @param[in] mode\tGEMAC operation mode (MII, RMII, RGMII, SGMII)\n+ */\n+void gemac_set_mode(void *base, int mode)\n+{\n+\tu32 val = readl(base + EMAC_RCNTRL_REG);\n+\n+\t/*Remove loopbank*/\n+\tval &= ~EMAC_RCNTRL_LOOP;\n+\n+\t/* Enable flow control and MII mode.PFE firmware always expects\n+       CRC should be forwarded by MAC to validate CRC in software.*/\n+\tval |= (EMAC_RCNTRL_FCE | EMAC_RCNTRL_MII_MODE);\n+\n+\twritel(val, base + EMAC_RCNTRL_REG);\n+}\n+\n+/* GEMAC enable function.\n+ * @param[in] base\tGEMAC base address\n+ */\n+void gemac_enable(void *base)\n+{\n+\twritel(readl(base + EMAC_ECNTRL_REG) | EMAC_ECNTRL_ETHER_EN, base +\n+\t\tEMAC_ECNTRL_REG);\n+}\n+\n+/* GEMAC disable function.\n+ * @param[in] base\tGEMAC base address\n+ */\n+void gemac_disable(void *base)\n+{\n+\twritel(readl(base + EMAC_ECNTRL_REG) & ~EMAC_ECNTRL_ETHER_EN, base +\n+\t\tEMAC_ECNTRL_REG);\n+}\n+\n+/* GEMAC TX disable function.\n+ * @param[in] base\tGEMAC base address\n+ */\n+void gemac_tx_disable(void *base)\n+{\n+\twritel(readl(base + EMAC_TCNTRL_REG) | EMAC_TCNTRL_GTS, base +\n+\t\tEMAC_TCNTRL_REG);\n+}\n+\n+void gemac_tx_enable(void *base)\n+{\n+\twritel(readl(base + EMAC_TCNTRL_REG) & ~EMAC_TCNTRL_GTS, base +\n+\t\t\tEMAC_TCNTRL_REG);\n+}\n+\n+/* Sets the hash register of the MAC.\n+ * This register is used for matching unicast and multicast frames.\n+ *\n+ * @param[in] base\tGEMAC base address.\n+ * @param[in] hash\t64-bit hash to be configured.\n+ */\n+void gemac_set_hash(void *base, struct pfe_mac_addr *hash)\n+{\n+\twritel(hash->bottom,  base + EMAC_GALR);\n+\twritel(hash->top, base + EMAC_GAUR);\n+}\n+\n+void gemac_set_laddrN(void *base, struct pfe_mac_addr *address,\n+\t\t      unsigned int entry_index)\n+{\n+\tif ((entry_index < 1) || (entry_index > EMAC_SPEC_ADDR_MAX))\n+\t\treturn;\n+\n+\tentry_index = entry_index - 1;\n+\tif (entry_index < 1) {\n+\t\twritel(htonl(address->bottom),  base + EMAC_PHY_ADDR_LOW);\n+\t\twritel((htonl(address->top) | 0x8808), base +\n+\t\t\tEMAC_PHY_ADDR_HIGH);\n+\t} else {\n+\t\twritel(htonl(address->bottom),  base + ((entry_index - 1) * 8)\n+\t\t\t+ EMAC_SMAC_0_0);\n+\t\twritel((htonl(address->top) | 0x8808), base + ((entry_index -\n+\t\t\t1) * 8) + EMAC_SMAC_0_1);\n+\t}\n+}\n+\n+void gemac_clear_laddrN(void *base, unsigned int entry_index)\n+{\n+\tif ((entry_index < 1) || (entry_index > EMAC_SPEC_ADDR_MAX))\n+\t\treturn;\n+\n+\tentry_index = entry_index - 1;\n+\tif (entry_index < 1) {\n+\t\twritel(0, base + EMAC_PHY_ADDR_LOW);\n+\t\twritel(0, base + EMAC_PHY_ADDR_HIGH);\n+\t} else {\n+\t\twritel(0,  base + ((entry_index - 1) * 8) + EMAC_SMAC_0_0);\n+\t\twritel(0, base + ((entry_index - 1) * 8) + EMAC_SMAC_0_1);\n+\t}\n+}\n+\n+/* Set the loopback mode of the MAC.  This can be either no loopback for\n+ * normal operation, local loopback through MAC internal loopback module or PHY\n+ *   loopback for external loopback through a PHY.  This asserts the external\n+ * loop pin.\n+ *\n+ * @param[in] base\tGEMAC base address.\n+ * @param[in] gem_loop\tLoopback mode to be enabled. LB_LOCAL - MAC\n+ * Loopback,\n+ *\t\t\tLB_EXT - PHY Loopback.\n+ */\n+void gemac_set_loop(void *base, enum mac_loop gem_loop)\n+{\n+\tpr_info(\"%s()\\n\", __func__);\n+\twritel(readl(base + EMAC_RCNTRL_REG) | EMAC_RCNTRL_LOOP, (base +\n+\t\tEMAC_RCNTRL_REG));\n+}\n+\n+/* GEMAC allow frames\n+ * @param[in] base\tGEMAC base address\n+ */\n+void gemac_enable_copy_all(void *base)\n+{\n+\twritel(readl(base + EMAC_RCNTRL_REG) | EMAC_RCNTRL_PROM, (base +\n+\t\tEMAC_RCNTRL_REG));\n+}\n+\n+/* GEMAC do not allow frames\n+ * @param[in] base\tGEMAC base address\n+ */\n+void gemac_disable_copy_all(void *base)\n+{\n+\twritel(readl(base + EMAC_RCNTRL_REG) & ~EMAC_RCNTRL_PROM, (base +\n+\t\tEMAC_RCNTRL_REG));\n+}\n+\n+/* GEMAC allow broadcast function.\n+ * @param[in] base\tGEMAC base address\n+ */\n+void gemac_allow_broadcast(void *base)\n+{\n+\twritel(readl(base + EMAC_RCNTRL_REG) & ~EMAC_RCNTRL_BC_REJ, base +\n+\t\tEMAC_RCNTRL_REG);\n+}\n+\n+/* GEMAC no broadcast function.\n+ * @param[in] base\tGEMAC base address\n+ */\n+void gemac_no_broadcast(void *base)\n+{\n+\twritel(readl(base + EMAC_RCNTRL_REG) | EMAC_RCNTRL_BC_REJ, base +\n+\t\tEMAC_RCNTRL_REG);\n+}\n+\n+/* GEMAC enable 1536 rx function.\n+ * @param[in]\tbase\tGEMAC base address\n+ */\n+void gemac_enable_1536_rx(void *base)\n+{\n+\t/* Set 1536 as Maximum frame length */\n+\twritel((readl(base + EMAC_RCNTRL_REG) & PFE_RCR_MAX_FL_MASK)\n+\t\t| (1536 << 16), base +\tEMAC_RCNTRL_REG);\n+}\n+\n+/* GEMAC set rx Max frame length.\n+ * @param[in]\tbase\tGEMAC base address\n+ * @param[in]\tmtu\tnew mtu\n+ */\n+void gemac_set_rx_max_fl(void *base, int mtu)\n+{\n+\t/* Set mtu as Maximum frame length */\n+\twritel((readl(base + EMAC_RCNTRL_REG) & PFE_RCR_MAX_FL_MASK)\n+\t\t| (mtu << 16), base + EMAC_RCNTRL_REG);\n+}\n+\n+/* GEMAC enable stacked vlan function.\n+ * @param[in]\tbase\tGEMAC base address\n+ */\n+void gemac_enable_stacked_vlan(void *base)\n+{\n+\t/* MTIP doesn't support stacked vlan */\n+}\n+\n+/* GEMAC enable pause rx function.\n+ * @param[in] base\tGEMAC base address\n+ */\n+void gemac_enable_pause_rx(void *base)\n+{\n+\twritel(readl(base + EMAC_RCNTRL_REG) | EMAC_RCNTRL_FCE,\n+\t       base + EMAC_RCNTRL_REG);\n+}\n+\n+/* GEMAC disable pause rx function.\n+ * @param[in] base\tGEMAC base address\n+ */\n+void gemac_disable_pause_rx(void *base)\n+{\n+\twritel(readl(base + EMAC_RCNTRL_REG) & ~EMAC_RCNTRL_FCE,\n+\t       base + EMAC_RCNTRL_REG);\n+}\n+\n+/* GEMAC enable pause tx function.\n+ * @param[in] base GEMAC base address\n+ */\n+void gemac_enable_pause_tx(void *base)\n+{\n+\twritel(EMAC_RX_SECTION_EMPTY_V, base + EMAC_RX_SECTION_EMPTY);\n+}\n+\n+/* GEMAC disable pause tx function.\n+ * @param[in] base GEMAC base address\n+ */\n+void gemac_disable_pause_tx(void *base)\n+{\n+\twritel(0x0, base + EMAC_RX_SECTION_EMPTY);\n+}\n+\n+/* GEMAC wol configuration\n+ * @param[in] base\tGEMAC base address\n+ * @param[in] wol_conf\tWoL register configuration\n+ */\n+void gemac_set_wol(void *base, u32 wol_conf)\n+{\n+\tu32  val = readl(base + EMAC_ECNTRL_REG);\n+\n+\tif (wol_conf)\n+\t\tval |= (EMAC_ECNTRL_MAGIC_ENA | EMAC_ECNTRL_SLEEP);\n+\telse\n+\t\tval &= ~(EMAC_ECNTRL_MAGIC_ENA | EMAC_ECNTRL_SLEEP);\n+\twritel(val, base + EMAC_ECNTRL_REG);\n+}\n+\n+/* Sets Gemac bus width to 64bit\n+ * @param[in] base       GEMAC base address\n+ * @param[in] width     gemac bus width to be set possible values are 32/64/128\n+ */\n+void gemac_set_bus_width(void *base, int width)\n+{\n+}\n+\n+/* Sets Gemac configuration.\n+ * @param[in] base\tGEMAC base address\n+ * @param[in] cfg\tGEMAC configuration\n+ */\n+void gemac_set_config(void *base, struct gemac_cfg *cfg)\n+{\n+\t/*GEMAC config taken from VLSI */\n+\twritel(0x00000004, base + EMAC_TFWR_STR_FWD);\n+\twritel(0x00000005, base + EMAC_RX_SECTION_FULL);\n+\n+\tif (pfe_errata_a010897)\n+\t\twritel(0x0000076c, base + EMAC_TRUNC_FL);\n+\telse\n+\t\twritel(0x00003fff, base + EMAC_TRUNC_FL);\n+\n+\twritel(0x00000030, base + EMAC_TX_SECTION_EMPTY);\n+\twritel(0x00000000, base + EMAC_MIB_CTRL_STS_REG);\n+\n+\tgemac_set_mode(base, cfg->mode);\n+\n+\tgemac_set_speed(base, cfg->speed);\n+\n+\tgemac_set_duplex(base, cfg->duplex);\n+}\n+\n+/**************************** GPI ***************************/\n+\n+/* Initializes a GPI block.\n+ * @param[in] base\tGPI base address\n+ * @param[in] cfg\tGPI configuration\n+ */\n+void gpi_init(void *base, struct gpi_cfg *cfg)\n+{\n+\tgpi_reset(base);\n+\n+\tgpi_disable(base);\n+\n+\tgpi_set_config(base, cfg);\n+}\n+\n+/* Resets a GPI block.\n+ * @param[in] base\tGPI base address\n+ */\n+void gpi_reset(void *base)\n+{\n+\twritel(CORE_SW_RESET, base + GPI_CTRL);\n+}\n+\n+/* Enables a GPI block.\n+ * @param[in] base\tGPI base address\n+ */\n+void gpi_enable(void *base)\n+{\n+\twritel(CORE_ENABLE, base + GPI_CTRL);\n+}\n+\n+/* Disables a GPI block.\n+ * @param[in] base\tGPI base address\n+ */\n+void gpi_disable(void *base)\n+{\n+\twritel(CORE_DISABLE, base + GPI_CTRL);\n+}\n+\n+/* Sets the configuration of a GPI block.\n+ * @param[in] base\tGPI base address\n+ * @param[in] cfg\tGPI configuration\n+ */\n+void gpi_set_config(void *base, struct gpi_cfg *cfg)\n+{\n+\twritel(CBUS_VIRT_TO_PFE(BMU1_BASE_ADDR + BMU_ALLOC_CTRL),\tbase\n+\t\t+ GPI_LMEM_ALLOC_ADDR);\n+\twritel(CBUS_VIRT_TO_PFE(BMU1_BASE_ADDR + BMU_FREE_CTRL),\tbase\n+\t\t+ GPI_LMEM_FREE_ADDR);\n+\twritel(CBUS_VIRT_TO_PFE(BMU2_BASE_ADDR + BMU_ALLOC_CTRL),\tbase\n+\t\t+ GPI_DDR_ALLOC_ADDR);\n+\twritel(CBUS_VIRT_TO_PFE(BMU2_BASE_ADDR + BMU_FREE_CTRL),\tbase\n+\t\t+ GPI_DDR_FREE_ADDR);\n+\twritel(CBUS_VIRT_TO_PFE(CLASS_INQ_PKTPTR), base + GPI_CLASS_ADDR);\n+\twritel(DDR_HDR_SIZE, base + GPI_DDR_DATA_OFFSET);\n+\twritel(LMEM_HDR_SIZE, base + GPI_LMEM_DATA_OFFSET);\n+\twritel(0, base + GPI_LMEM_SEC_BUF_DATA_OFFSET);\n+\twritel(0, base + GPI_DDR_SEC_BUF_DATA_OFFSET);\n+\twritel((DDR_HDR_SIZE << 16) |\tLMEM_HDR_SIZE,\tbase + GPI_HDR_SIZE);\n+\twritel((DDR_BUF_SIZE << 16) |\tLMEM_BUF_SIZE,\tbase + GPI_BUF_SIZE);\n+\n+\twritel(((cfg->lmem_rtry_cnt << 16) | (GPI_DDR_BUF_EN << 1) |\n+\t\tGPI_LMEM_BUF_EN), base + GPI_RX_CONFIG);\n+\twritel(cfg->tmlf_txthres, base + GPI_TMLF_TX);\n+\twritel(cfg->aseq_len,\tbase + GPI_DTX_ASEQ);\n+\twritel(1, base + GPI_TOE_CHKSUM_EN);\n+\n+\tif (cfg->mtip_pause_reg) {\n+\t\twritel(cfg->mtip_pause_reg, base + GPI_CSR_MTIP_PAUSE_REG);\n+\t\twritel(EGPI_PAUSE_TIME, base + GPI_TX_PAUSE_TIME);\n+\t}\n+}\n+\n+/**************************** CLASSIFIER ***************************/\n+\n+/* Initializes CLASSIFIER block.\n+ * @param[in] cfg\tCLASSIFIER configuration\n+ */\n+void class_init(struct class_cfg *cfg)\n+{\n+\tclass_reset();\n+\n+\tclass_disable();\n+\n+\tclass_set_config(cfg);\n+}\n+\n+/* Resets CLASSIFIER block.\n+ *\n+ */\n+void class_reset(void)\n+{\n+\twritel(CORE_SW_RESET, CLASS_TX_CTRL);\n+}\n+\n+/* Enables all CLASS-PE's cores.\n+ *\n+ */\n+void class_enable(void)\n+{\n+\twritel(CORE_ENABLE, CLASS_TX_CTRL);\n+}\n+\n+/* Disables all CLASS-PE's cores.\n+ *\n+ */\n+void class_disable(void)\n+{\n+\twritel(CORE_DISABLE, CLASS_TX_CTRL);\n+}\n+\n+/*\n+ * Sets the configuration of the CLASSIFIER block.\n+ * @param[in] cfg\tCLASSIFIER configuration\n+ */\n+void class_set_config(struct class_cfg *cfg)\n+{\n+\tu32 val;\n+\n+\t/* Initialize route table */\n+\tif (!cfg->resume)\n+\t\tmemset(DDR_PHYS_TO_VIRT(cfg->route_table_baseaddr), 0, (1 <<\n+\t\tcfg->route_table_hash_bits) * CLASS_ROUTE_SIZE);\n+\n+#if !defined(LS1012A_PFE_RESET_WA)\n+\twritel(cfg->pe_sys_clk_ratio,\tCLASS_PE_SYS_CLK_RATIO);\n+#endif\n+\n+\twritel((DDR_HDR_SIZE << 16) | LMEM_HDR_SIZE,\tCLASS_HDR_SIZE);\n+\twritel(LMEM_BUF_SIZE,\t\t\t\tCLASS_LMEM_BUF_SIZE);\n+\twritel(CLASS_ROUTE_ENTRY_SIZE(CLASS_ROUTE_SIZE) |\n+\t\tCLASS_ROUTE_HASH_SIZE(cfg->route_table_hash_bits),\n+\t\tCLASS_ROUTE_HASH_ENTRY_SIZE);\n+\twritel(HIF_PKT_CLASS_EN | HIF_PKT_OFFSET(sizeof(struct hif_hdr)),\n+\t       CLASS_HIF_PARSE);\n+\n+\tval = HASH_CRC_PORT_IP | QB2BUS_LE;\n+\n+#if defined(CONFIG_IP_ALIGNED)\n+\tval |= IP_ALIGNED;\n+#endif\n+\n+\t/*\n+\t *  Class PE packet steering will only work if TOE mode, bridge fetch or\n+\t * route fetch are enabled (see class/qb_fet.v). Route fetch would\n+\t * trigger additional memory copies (likely from DDR because of hash\n+\t * table size, which cannot be reduced because PE software still\n+\t * relies on hash value computed in HW), so when not in TOE mode we\n+\t * simply enable HW bridge fetch even though we don't use it.\n+\t */\n+\tif (cfg->toe_mode)\n+\t\tval |= CLASS_TOE;\n+\telse\n+\t\tval |= HW_BRIDGE_FETCH;\n+\n+\twritel(val, CLASS_ROUTE_MULTI);\n+\n+\twritel(DDR_PHYS_TO_PFE(cfg->route_table_baseaddr),\n+\t       CLASS_ROUTE_TABLE_BASE);\n+\twritel(CLASS_PE0_RO_DM_ADDR0_VAL,\t\tCLASS_PE0_RO_DM_ADDR0);\n+\twritel(CLASS_PE0_RO_DM_ADDR1_VAL,\t\tCLASS_PE0_RO_DM_ADDR1);\n+\twritel(CLASS_PE0_QB_DM_ADDR0_VAL,\t\tCLASS_PE0_QB_DM_ADDR0);\n+\twritel(CLASS_PE0_QB_DM_ADDR1_VAL,\t\tCLASS_PE0_QB_DM_ADDR1);\n+\twritel(CBUS_VIRT_TO_PFE(TMU_PHY_INQ_PKTPTR),\tCLASS_TM_INQ_ADDR);\n+\n+\twritel(23, CLASS_AFULL_THRES);\n+\twritel(23, CLASS_TSQ_FIFO_THRES);\n+\n+\twritel(24, CLASS_MAX_BUF_CNT);\n+\twritel(24, CLASS_TSQ_MAX_CNT);\n+}\n+\n+/**************************** TMU ***************************/\n+\n+void tmu_reset(void)\n+{\n+\twritel(SW_RESET, TMU_CTRL);\n+}\n+\n+/* Initializes TMU block.\n+ * @param[in] cfg\tTMU configuration\n+ */\n+void tmu_init(struct tmu_cfg *cfg)\n+{\n+\tint q, phyno;\n+\n+\ttmu_disable(0xF);\n+\tmdelay(10);\n+\n+#if !defined(LS1012A_PFE_RESET_WA)\n+\t/* keep in soft reset */\n+\twritel(SW_RESET, TMU_CTRL);\n+#endif\n+\twritel(0x3, TMU_SYS_GENERIC_CONTROL);\n+\twritel(750, TMU_INQ_WATERMARK);\n+\twritel(CBUS_VIRT_TO_PFE(EGPI1_BASE_ADDR +\n+\t\tGPI_INQ_PKTPTR),\tTMU_PHY0_INQ_ADDR);\n+\twritel(CBUS_VIRT_TO_PFE(EGPI2_BASE_ADDR +\n+\t\tGPI_INQ_PKTPTR),\tTMU_PHY1_INQ_ADDR);\n+\twritel(CBUS_VIRT_TO_PFE(HGPI_BASE_ADDR +\n+\t\tGPI_INQ_PKTPTR),\tTMU_PHY3_INQ_ADDR);\n+\twritel(CBUS_VIRT_TO_PFE(HIF_NOCPY_RX_INQ0_PKTPTR), TMU_PHY4_INQ_ADDR);\n+\twritel(CBUS_VIRT_TO_PFE(UTIL_INQ_PKTPTR), TMU_PHY5_INQ_ADDR);\n+\twritel(CBUS_VIRT_TO_PFE(BMU2_BASE_ADDR + BMU_FREE_CTRL),\n+\t       TMU_BMU_INQ_ADDR);\n+\n+\twritel(0x3FF,\tTMU_TDQ0_SCH_CTRL);\t/*\n+\t\t\t\t\t\t * enabling all 10\n+\t\t\t\t\t\t * schedulers [9:0] of each TDQ\n+\t\t\t\t\t\t */\n+\twritel(0x3FF,\tTMU_TDQ1_SCH_CTRL);\n+\twritel(0x3FF,\tTMU_TDQ3_SCH_CTRL);\n+\n+#if !defined(LS1012A_PFE_RESET_WA)\n+\twritel(cfg->pe_sys_clk_ratio,\tTMU_PE_SYS_CLK_RATIO);\n+#endif\n+\n+#if !defined(LS1012A_PFE_RESET_WA)\n+\twritel(DDR_PHYS_TO_PFE(cfg->llm_base_addr),\tTMU_LLM_BASE_ADDR);\n+\t/* Extra packet pointers will be stored from this address onwards */\n+\n+\twritel(cfg->llm_queue_len,\tTMU_LLM_QUE_LEN);\n+\twritel(5,\t\t\tTMU_TDQ_IIFG_CFG);\n+\twritel(DDR_BUF_SIZE,\t\tTMU_BMU_BUF_SIZE);\n+\n+\twritel(0x0,\t\t\tTMU_CTRL);\n+\n+\t/* MEM init */\n+\tpr_info(\"%s: mem init\\n\", __func__);\n+\twritel(MEM_INIT,\tTMU_CTRL);\n+\n+\twhile (!(readl(TMU_CTRL) & MEM_INIT_DONE))\n+\t\t;\n+\n+\t/* LLM init */\n+\tpr_info(\"%s: lmem init\\n\", __func__);\n+\twritel(LLM_INIT,\tTMU_CTRL);\n+\n+\twhile (!(readl(TMU_CTRL) & LLM_INIT_DONE))\n+\t\t;\n+#endif\n+\t/* set up each queue for tail drop */\n+\tfor (phyno = 0; phyno < 4; phyno++) {\n+\t\tif (phyno == 2)\n+\t\t\tcontinue;\n+\t\tfor (q = 0; q < 16; q++) {\n+\t\t\tu32 qdepth;\n+\n+\t\t\twritel((phyno << 8) | q, TMU_TEQ_CTRL);\n+\t\t\twritel(1 << 22, TMU_TEQ_QCFG); /*Enable tail drop */\n+\n+\t\t\tif (phyno == 3)\n+\t\t\t\tqdepth = DEFAULT_TMU3_QDEPTH;\n+\t\t\telse\n+\t\t\t\tqdepth = (q == 0) ? DEFAULT_Q0_QDEPTH :\n+\t\t\t\t\t\tDEFAULT_MAX_QDEPTH;\n+\n+\t\t\t/* LOG: 68855 */\n+\t\t\t/*\n+\t\t\t * The following is a workaround for the reordered\n+\t\t\t * packet and BMU2 buffer leakage issue.\n+\t\t\t */\n+\t\t\tif (CHIP_REVISION() == 0)\n+\t\t\t\tqdepth = 31;\n+\n+\t\t\twritel(qdepth << 18, TMU_TEQ_HW_PROB_CFG2);\n+\t\t\twritel(qdepth >> 14, TMU_TEQ_HW_PROB_CFG3);\n+\t\t}\n+\t}\n+\n+#ifdef CFG_LRO\n+\t/* Set TMU-3 queue 5 (LRO) in no-drop mode */\n+\twritel((3 << 8) | TMU_QUEUE_LRO, TMU_TEQ_CTRL);\n+\twritel(0, TMU_TEQ_QCFG);\n+#endif\n+\n+\twritel(0x05, TMU_TEQ_DISABLE_DROPCHK);\n+\n+\twritel(0x0, TMU_CTRL);\n+}\n+\n+/* Enables TMU-PE cores.\n+ * @param[in] pe_mask\tTMU PE mask\n+ */\n+void tmu_enable(u32 pe_mask)\n+{\n+\twritel(readl(TMU_TX_CTRL) | (pe_mask & 0xF), TMU_TX_CTRL);\n+}\n+\n+/* Disables TMU cores.\n+ * @param[in] pe_mask\tTMU PE mask\n+ */\n+void tmu_disable(u32 pe_mask)\n+{\n+\twritel(readl(TMU_TX_CTRL) & ~(pe_mask & 0xF), TMU_TX_CTRL);\n+}\n+\n+/* This will return the tmu queue status\n+ * @param[in] if_id\tgem interface id or TMU index\n+ * @return\t\treturns the bit mask of busy queues, zero means all\n+ * queues are empty\n+ */\n+u32 tmu_qstatus(u32 if_id)\n+{\n+\treturn cpu_to_be32(pe_dmem_read(TMU0_ID + if_id, TMU_DM_PESTATUS +\n+\t\toffsetof(struct pe_status, tmu_qstatus), 4));\n+}\n+\n+u32 tmu_pkts_processed(u32 if_id)\n+{\n+\treturn cpu_to_be32(pe_dmem_read(TMU0_ID + if_id, TMU_DM_PESTATUS +\n+\t\toffsetof(struct pe_status, rx), 4));\n+}\n+\n+/**************************** UTIL ***************************/\n+\n+/* Resets UTIL block.\n+ */\n+void util_reset(void)\n+{\n+\twritel(CORE_SW_RESET, UTIL_TX_CTRL);\n+}\n+\n+/* Initializes UTIL block.\n+ * @param[in] cfg\tUTIL configuration\n+ */\n+void util_init(struct util_cfg *cfg)\n+{\n+\twritel(cfg->pe_sys_clk_ratio,   UTIL_PE_SYS_CLK_RATIO);\n+}\n+\n+/* Enables UTIL-PE core.\n+ *\n+ */\n+void util_enable(void)\n+{\n+\twritel(CORE_ENABLE, UTIL_TX_CTRL);\n+}\n+\n+/* Disables UTIL-PE core.\n+ *\n+ */\n+void util_disable(void)\n+{\n+\twritel(CORE_DISABLE, UTIL_TX_CTRL);\n+}\n+\n+/**************************** HIF ***************************/\n+/* Initializes HIF copy block.\n+ *\n+ */\n+void hif_init(void)\n+{\n+\t/*Initialize HIF registers*/\n+\twritel((HIF_RX_POLL_CTRL_CYCLE << 16) | HIF_TX_POLL_CTRL_CYCLE,\n+\t       HIF_POLL_CTRL);\n+}\n+\n+/* Enable hif tx DMA and interrupt\n+ *\n+ */\n+void hif_tx_enable(void)\n+{\n+\twritel(HIF_CTRL_DMA_EN, HIF_TX_CTRL);\n+\twritel((readl(HIF_INT_ENABLE) | HIF_INT_EN | HIF_TXPKT_INT_EN),\n+\t       HIF_INT_ENABLE);\n+}\n+\n+/* Disable hif tx DMA and interrupt\n+ *\n+ */\n+void hif_tx_disable(void)\n+{\n+\tu32\thif_int;\n+\n+\twritel(0, HIF_TX_CTRL);\n+\n+\thif_int = readl(HIF_INT_ENABLE);\n+\thif_int &= HIF_TXPKT_INT_EN;\n+\twritel(hif_int, HIF_INT_ENABLE);\n+}\n+\n+/* Enable hif rx DMA and interrupt\n+ *\n+ */\n+void hif_rx_enable(void)\n+{\n+\thif_rx_dma_start();\n+\twritel((readl(HIF_INT_ENABLE) | HIF_INT_EN | HIF_RXPKT_INT_EN),\n+\t       HIF_INT_ENABLE);\n+}\n+\n+/* Disable hif rx DMA and interrupt\n+ *\n+ */\n+void hif_rx_disable(void)\n+{\n+\tu32\thif_int;\n+\n+\twritel(0, HIF_RX_CTRL);\n+\n+\thif_int = readl(HIF_INT_ENABLE);\n+\thif_int &= HIF_RXPKT_INT_EN;\n+\twritel(hif_int, HIF_INT_ENABLE);\n+}\n--- /dev/null\n+++ b/drivers/staging/fsl_ppfe/pfe_hif.c\n@@ -0,0 +1,1064 @@\n+// SPDX-License-Identifier: GPL-2.0+\n+/*\n+ * Copyright 2015-2016 Freescale Semiconductor, Inc.\n+ * Copyright 2017 NXP\n+ */\n+\n+#include <linux/kernel.h>\n+#include <linux/interrupt.h>\n+#include <linux/dma-mapping.h>\n+#include <linux/dmapool.h>\n+#include <linux/sched.h>\n+#include <linux/module.h>\n+#include <linux/list.h>\n+#include <linux/kthread.h>\n+#include <linux/slab.h>\n+\n+#include <linux/io.h>\n+#include <asm/irq.h>\n+\n+#include \"pfe_mod.h\"\n+\n+#define HIF_INT_MASK\t(HIF_INT | HIF_RXPKT_INT | HIF_TXPKT_INT)\n+\n+unsigned char napi_first_batch;\n+\n+static void pfe_tx_do_cleanup(unsigned long data);\n+\n+static int pfe_hif_alloc_descr(struct pfe_hif *hif)\n+{\n+\tvoid *addr;\n+\tdma_addr_t dma_addr;\n+\tint err = 0;\n+\n+\tpr_info(\"%s\\n\", __func__);\n+\taddr = dma_alloc_coherent(pfe->dev,\n+\t\t\t\t  HIF_RX_DESC_NT * sizeof(struct hif_desc) +\n+\t\t\t\t  HIF_TX_DESC_NT * sizeof(struct hif_desc),\n+\t\t\t\t  &dma_addr, GFP_KERNEL);\n+\n+\tif (!addr) {\n+\t\tpr_err(\"%s: Could not allocate buffer descriptors!\\n\"\n+\t\t\t, __func__);\n+\t\terr = -ENOMEM;\n+\t\tgoto err0;\n+\t}\n+\n+\thif->descr_baseaddr_p = dma_addr;\n+\thif->descr_baseaddr_v = addr;\n+\thif->rx_ring_size = HIF_RX_DESC_NT;\n+\thif->tx_ring_size = HIF_TX_DESC_NT;\n+\n+\treturn 0;\n+\n+err0:\n+\treturn err;\n+}\n+\n+#if defined(LS1012A_PFE_RESET_WA)\n+static void pfe_hif_disable_rx_desc(struct pfe_hif *hif)\n+{\n+\tint ii;\n+\tstruct hif_desc\t*desc = hif->rx_base;\n+\n+\t/*Mark all descriptors as LAST_BD */\n+\tfor (ii = 0; ii < hif->rx_ring_size; ii++) {\n+\t\tdesc->ctrl |= BD_CTRL_LAST_BD;\n+\t\tdesc++;\n+\t}\n+}\n+\n+struct class_rx_hdr_t {\n+\tu32     next_ptr;       /* ptr to the start of the first DDR buffer */\n+\tu16     length;         /* total packet length */\n+\tu16     phyno;          /* input physical port number */\n+\tu32     status;         /* gemac status bits */\n+\tu32     status2;            /* reserved for software usage */\n+};\n+\n+/* STATUS_BAD_FRAME_ERR is set for all errors (including checksums if enabled)\n+ * except overflow\n+ */\n+#define STATUS_BAD_FRAME_ERR            BIT(16)\n+#define STATUS_LENGTH_ERR               BIT(17)\n+#define STATUS_CRC_ERR                  BIT(18)\n+#define STATUS_TOO_SHORT_ERR            BIT(19)\n+#define STATUS_TOO_LONG_ERR             BIT(20)\n+#define STATUS_CODE_ERR                 BIT(21)\n+#define STATUS_MC_HASH_MATCH            BIT(22)\n+#define STATUS_CUMULATIVE_ARC_HIT       BIT(23)\n+#define STATUS_UNICAST_HASH_MATCH       BIT(24)\n+#define STATUS_IP_CHECKSUM_CORRECT      BIT(25)\n+#define STATUS_TCP_CHECKSUM_CORRECT     BIT(26)\n+#define STATUS_UDP_CHECKSUM_CORRECT     BIT(27)\n+#define STATUS_OVERFLOW_ERR             BIT(28) /* GPI error */\n+#define MIN_PKT_SIZE\t\t\t64\n+\n+static inline void copy_to_lmem(u32 *dst, u32 *src, int len)\n+{\n+\tint i;\n+\n+\tfor (i = 0; i < len; i += sizeof(u32))\t{\n+\t\t*dst = htonl(*src);\n+\t\tdst++; src++;\n+\t}\n+}\n+\n+static void send_dummy_pkt_to_hif(void)\n+{\n+\tvoid *lmem_ptr, *ddr_ptr, *lmem_virt_addr;\n+\tu32 physaddr;\n+\tstruct class_rx_hdr_t local_hdr;\n+\tstatic u32 dummy_pkt[] =  {\n+\t\t0x33221100, 0x2b785544, 0xd73093cb, 0x01000608,\n+\t\t0x04060008, 0x2b780200, 0xd73093cb, 0x0a01a8c0,\n+\t\t0x33221100, 0xa8c05544, 0x00000301, 0x00000000,\n+\t\t0x00000000, 0x00000000, 0x00000000, 0xbe86c51f };\n+\n+\tddr_ptr = (void *)((u64)readl(BMU2_BASE_ADDR + BMU_ALLOC_CTRL));\n+\tif (!ddr_ptr)\n+\t\treturn;\n+\n+\tlmem_ptr = (void *)((u64)readl(BMU1_BASE_ADDR + BMU_ALLOC_CTRL));\n+\tif (!lmem_ptr)\n+\t\treturn;\n+\n+\tpr_info(\"Sending a dummy pkt to HIF %p %p\\n\", ddr_ptr, lmem_ptr);\n+\tphysaddr = (u32)DDR_VIRT_TO_PFE(ddr_ptr);\n+\n+\tlmem_virt_addr = (void *)CBUS_PFE_TO_VIRT((unsigned long int)lmem_ptr);\n+\n+\tlocal_hdr.phyno = htons(0); /* RX_PHY_0 */\n+\tlocal_hdr.length = htons(MIN_PKT_SIZE);\n+\n+\tlocal_hdr.next_ptr = htonl((u32)physaddr);\n+\t/*Mark checksum is correct */\n+\tlocal_hdr.status = htonl((STATUS_IP_CHECKSUM_CORRECT |\n+\t\t\t\tSTATUS_UDP_CHECKSUM_CORRECT |\n+\t\t\t\tSTATUS_TCP_CHECKSUM_CORRECT |\n+\t\t\t\tSTATUS_UNICAST_HASH_MATCH |\n+\t\t\t\tSTATUS_CUMULATIVE_ARC_HIT));\n+\tlocal_hdr.status2 = 0;\n+\n+\tcopy_to_lmem((u32 *)lmem_virt_addr, (u32 *)&local_hdr,\n+\t\t     sizeof(local_hdr));\n+\n+\tcopy_to_lmem((u32 *)(lmem_virt_addr + LMEM_HDR_SIZE), (u32 *)dummy_pkt,\n+\t\t     0x40);\n+\n+\twritel((unsigned long int)lmem_ptr, CLASS_INQ_PKTPTR);\n+}\n+\n+void pfe_hif_rx_idle(struct pfe_hif *hif)\n+{\n+\tint hif_stop_loop = 10;\n+\tu32 rx_status;\n+\n+\tpfe_hif_disable_rx_desc(hif);\n+\tpr_info(\"Bringing hif to idle state...\");\n+\twritel(0, HIF_INT_ENABLE);\n+\t/*If HIF Rx BDP is busy send a dummy packet */\n+\tdo {\n+\t\trx_status = readl(HIF_RX_STATUS);\n+\t\tif (rx_status & BDP_CSR_RX_DMA_ACTV)\n+\t\t\tsend_dummy_pkt_to_hif();\n+\n+\t\tusleep_range(100, 150);\n+\t} while (--hif_stop_loop);\n+\n+\tif (readl(HIF_RX_STATUS) & BDP_CSR_RX_DMA_ACTV)\n+\t\tpr_info(\"Failed\\n\");\n+\telse\n+\t\tpr_info(\"Done\\n\");\n+}\n+#endif\n+\n+static void pfe_hif_free_descr(struct pfe_hif *hif)\n+{\n+\tpr_info(\"%s\\n\", __func__);\n+\n+\tdma_free_coherent(pfe->dev,\n+\t\t\t  hif->rx_ring_size * sizeof(struct hif_desc) +\n+\t\t\t  hif->tx_ring_size * sizeof(struct hif_desc),\n+\t\t\t  hif->descr_baseaddr_v, hif->descr_baseaddr_p);\n+}\n+\n+void pfe_hif_desc_dump(struct pfe_hif *hif)\n+{\n+\tstruct hif_desc\t*desc;\n+\tunsigned long desc_p;\n+\tint ii = 0;\n+\n+\tpr_info(\"%s\\n\", __func__);\n+\n+\tdesc = hif->rx_base;\n+\tdesc_p = (u32)((u64)desc - (u64)hif->descr_baseaddr_v +\n+\t\t\thif->descr_baseaddr_p);\n+\n+\tpr_info(\"HIF Rx desc base %p physical %x\\n\", desc, (u32)desc_p);\n+\tfor (ii = 0; ii < hif->rx_ring_size; ii++) {\n+\t\tpr_info(\"status: %08x, ctrl: %08x, data: %08x, next: %x\\n\",\n+\t\t\treadl(&desc->status), readl(&desc->ctrl),\n+\t\t\treadl(&desc->data), readl(&desc->next));\n+\t\t\tdesc++;\n+\t}\n+\n+\tdesc = hif->tx_base;\n+\tdesc_p = ((u64)desc - (u64)hif->descr_baseaddr_v +\n+\t\t\thif->descr_baseaddr_p);\n+\n+\tpr_info(\"HIF Tx desc base %p physical %x\\n\", desc, (u32)desc_p);\n+\tfor (ii = 0; ii < hif->tx_ring_size; ii++) {\n+\t\tpr_info(\"status: %08x, ctrl: %08x, data: %08x, next: %x\\n\",\n+\t\t\treadl(&desc->status), readl(&desc->ctrl),\n+\t\t\treadl(&desc->data), readl(&desc->next));\n+\t\tdesc++;\n+\t}\n+}\n+\n+/* pfe_hif_release_buffers */\n+static void pfe_hif_release_buffers(struct pfe_hif *hif)\n+{\n+\tstruct hif_desc\t*desc;\n+\tint i = 0;\n+\n+\thif->rx_base = hif->descr_baseaddr_v;\n+\n+\tpr_info(\"%s\\n\", __func__);\n+\n+\t/*Free Rx buffers */\n+\tdesc = hif->rx_base;\n+\tfor (i = 0; i < hif->rx_ring_size; i++) {\n+\t\tif (readl(&desc->data)) {\n+\t\t\tif ((i < hif->shm->rx_buf_pool_cnt) &&\n+\t\t\t    (!hif->shm->rx_buf_pool[i])) {\n+\t\t\t\t/*\n+\t\t\t\t * dma_unmap_single(hif->dev, desc->data,\n+\t\t\t\t * hif->rx_buf_len[i], DMA_FROM_DEVICE);\n+\t\t\t\t */\n+\t\t\t\tdma_unmap_single(hif->dev,\n+\t\t\t\t\t\t DDR_PFE_TO_PHYS(\n+\t\t\t\t\t\t readl(&desc->data)),\n+\t\t\t\t\t\t hif->rx_buf_len[i],\n+\t\t\t\t\t\t DMA_FROM_DEVICE);\n+\t\t\t\thif->shm->rx_buf_pool[i] = hif->rx_buf_addr[i];\n+\t\t\t} else {\n+\t\t\t\tpr_err(\"%s: buffer pool already full\\n\"\n+\t\t\t\t\t, __func__);\n+\t\t\t}\n+\t\t}\n+\n+\t\twritel(0, &desc->data);\n+\t\twritel(0, &desc->status);\n+\t\twritel(0, &desc->ctrl);\n+\t\tdesc++;\n+\t}\n+}\n+\n+/*\n+ * pfe_hif_init_buffers\n+ * This function initializes the HIF Rx/Tx ring descriptors and\n+ * initialize Rx queue with buffers.\n+ */\n+static int pfe_hif_init_buffers(struct pfe_hif *hif)\n+{\n+\tstruct hif_desc\t*desc, *first_desc_p;\n+\tu32 data;\n+\tint i = 0;\n+\n+\tpr_info(\"%s\\n\", __func__);\n+\n+\t/* Check enough Rx buffers available in the shared memory */\n+\tif (hif->shm->rx_buf_pool_cnt < hif->rx_ring_size)\n+\t\treturn -ENOMEM;\n+\n+\thif->rx_base = hif->descr_baseaddr_v;\n+\tmemset(hif->rx_base, 0, hif->rx_ring_size * sizeof(struct hif_desc));\n+\n+\t/*Initialize Rx descriptors */\n+\tdesc = hif->rx_base;\n+\tfirst_desc_p = (struct hif_desc *)hif->descr_baseaddr_p;\n+\n+\tfor (i = 0; i < hif->rx_ring_size; i++) {\n+\t\t/* Initialize Rx buffers from the shared memory */\n+\n+\t\tdata = (u32)dma_map_single(hif->dev, hif->shm->rx_buf_pool[i],\n+\t\t\t\tpfe_pkt_size, DMA_FROM_DEVICE);\n+\t\thif->rx_buf_addr[i] = hif->shm->rx_buf_pool[i];\n+\t\thif->rx_buf_len[i] = pfe_pkt_size;\n+\t\thif->shm->rx_buf_pool[i] = NULL;\n+\n+\t\tif (likely(dma_mapping_error(hif->dev, data) == 0)) {\n+\t\t\twritel(DDR_PHYS_TO_PFE(data), &desc->data);\n+\t\t} else {\n+\t\t\tpr_err(\"%s : low on mem\\n\",  __func__);\n+\n+\t\t\tgoto err;\n+\t\t}\n+\n+\t\twritel(0, &desc->status);\n+\n+\t\t/*\n+\t\t * Ensure everything else is written to DDR before\n+\t\t * writing bd->ctrl\n+\t\t */\n+\t\twmb();\n+\n+\t\twritel((BD_CTRL_PKT_INT_EN | BD_CTRL_LIFM\n+\t\t\t| BD_CTRL_DIR | BD_CTRL_DESC_EN\n+\t\t\t| BD_BUF_LEN(pfe_pkt_size)), &desc->ctrl);\n+\n+\t\t/* Chain descriptors */\n+\t\twritel((u32)DDR_PHYS_TO_PFE(first_desc_p + i + 1), &desc->next);\n+\t\tdesc++;\n+\t}\n+\n+\t/* Overwrite last descriptor to chain it to first one*/\n+\tdesc--;\n+\twritel((u32)DDR_PHYS_TO_PFE(first_desc_p), &desc->next);\n+\n+\thif->rxtoclean_index = 0;\n+\n+\t/*Initialize Rx buffer descriptor ring base address */\n+\twritel(DDR_PHYS_TO_PFE(hif->descr_baseaddr_p), HIF_RX_BDP_ADDR);\n+\n+\thif->tx_base = hif->rx_base + hif->rx_ring_size;\n+\tfirst_desc_p = (struct hif_desc *)hif->descr_baseaddr_p +\n+\t\t\t\thif->rx_ring_size;\n+\tmemset(hif->tx_base, 0, hif->tx_ring_size * sizeof(struct hif_desc));\n+\n+\t/*Initialize tx descriptors */\n+\tdesc = hif->tx_base;\n+\n+\tfor (i = 0; i < hif->tx_ring_size; i++) {\n+\t\t/* Chain descriptors */\n+\t\twritel((u32)DDR_PHYS_TO_PFE(first_desc_p + i + 1), &desc->next);\n+\t\twritel(0, &desc->ctrl);\n+\t\tdesc++;\n+\t}\n+\n+\t/* Overwrite last descriptor to chain it to first one */\n+\tdesc--;\n+\twritel((u32)DDR_PHYS_TO_PFE(first_desc_p), &desc->next);\n+\thif->txavail = hif->tx_ring_size;\n+\thif->txtosend = 0;\n+\thif->txtoclean = 0;\n+\thif->txtoflush = 0;\n+\n+\t/*Initialize Tx buffer descriptor ring base address */\n+\twritel((u32)DDR_PHYS_TO_PFE(first_desc_p), HIF_TX_BDP_ADDR);\n+\n+\treturn 0;\n+\n+err:\n+\tpfe_hif_release_buffers(hif);\n+\treturn -ENOMEM;\n+}\n+\n+/*\n+ * pfe_hif_client_register\n+ *\n+ * This function used to register a client driver with the HIF driver.\n+ *\n+ * Return value:\n+ * 0 - on Successful registration\n+ */\n+static int pfe_hif_client_register(struct pfe_hif *hif, u32 client_id,\n+\t\t\t\t   struct hif_client_shm *client_shm)\n+{\n+\tstruct hif_client *client = &hif->client[client_id];\n+\tu32 i, cnt;\n+\tstruct rx_queue_desc *rx_qbase;\n+\tstruct tx_queue_desc *tx_qbase;\n+\tstruct hif_rx_queue *rx_queue;\n+\tstruct hif_tx_queue *tx_queue;\n+\tint err = 0;\n+\n+\tpr_info(\"%s\\n\", __func__);\n+\n+\tspin_lock_bh(&hif->tx_lock);\n+\n+\tif (test_bit(client_id, &hif->shm->g_client_status[0])) {\n+\t\tpr_err(\"%s: client %d already registered\\n\",\n+\t\t       __func__, client_id);\n+\t\terr = -1;\n+\t\tgoto unlock;\n+\t}\n+\n+\tmemset(client, 0, sizeof(struct hif_client));\n+\n+\t/* Initialize client Rx queues baseaddr, size */\n+\n+\tcnt = CLIENT_CTRL_RX_Q_CNT(client_shm->ctrl);\n+\t/* Check if client is requesting for more queues than supported */\n+\tif (cnt > HIF_CLIENT_QUEUES_MAX)\n+\t\tcnt = HIF_CLIENT_QUEUES_MAX;\n+\n+\tclient->rx_qn = cnt;\n+\trx_qbase = (struct rx_queue_desc *)client_shm->rx_qbase;\n+\tfor (i = 0; i < cnt; i++) {\n+\t\trx_queue = &client->rx_q[i];\n+\t\trx_queue->base = rx_qbase + i * client_shm->rx_qsize;\n+\t\trx_queue->size = client_shm->rx_qsize;\n+\t\trx_queue->write_idx = 0;\n+\t}\n+\n+\t/* Initialize client Tx queues baseaddr, size */\n+\tcnt = CLIENT_CTRL_TX_Q_CNT(client_shm->ctrl);\n+\n+\t/* Check if client is requesting for more queues than supported */\n+\tif (cnt > HIF_CLIENT_QUEUES_MAX)\n+\t\tcnt = HIF_CLIENT_QUEUES_MAX;\n+\n+\tclient->tx_qn = cnt;\n+\ttx_qbase = (struct tx_queue_desc *)client_shm->tx_qbase;\n+\tfor (i = 0; i < cnt; i++) {\n+\t\ttx_queue = &client->tx_q[i];\n+\t\ttx_queue->base = tx_qbase + i * client_shm->tx_qsize;\n+\t\ttx_queue->size = client_shm->tx_qsize;\n+\t\ttx_queue->ack_idx = 0;\n+\t}\n+\n+\tset_bit(client_id, &hif->shm->g_client_status[0]);\n+\n+unlock:\n+\tspin_unlock_bh(&hif->tx_lock);\n+\n+\treturn err;\n+}\n+\n+/*\n+ * pfe_hif_client_unregister\n+ *\n+ * This function used to unregister a client  from the HIF driver.\n+ *\n+ */\n+static void pfe_hif_client_unregister(struct pfe_hif *hif, u32 client_id)\n+{\n+\tpr_info(\"%s\\n\", __func__);\n+\n+\t/*\n+\t * Mark client as no longer available (which prevents further packet\n+\t * receive for this client)\n+\t */\n+\tspin_lock_bh(&hif->tx_lock);\n+\n+\tif (!test_bit(client_id, &hif->shm->g_client_status[0])) {\n+\t\tpr_err(\"%s: client %d not registered\\n\", __func__,\n+\t\t       client_id);\n+\n+\t\tspin_unlock_bh(&hif->tx_lock);\n+\t\treturn;\n+\t}\n+\n+\tclear_bit(client_id, &hif->shm->g_client_status[0]);\n+\n+\tspin_unlock_bh(&hif->tx_lock);\n+}\n+\n+/*\n+ * client_put_rxpacket-\n+ * This functions puts the Rx pkt  in the given client Rx queue.\n+ * It actually swap the Rx pkt in the client Rx descriptor buffer\n+ * and returns the free buffer from it.\n+ *\n+ * If the function returns NULL means client Rx queue is full and\n+ * packet couldn't send to client queue.\n+ */\n+static void *client_put_rxpacket(struct hif_rx_queue *queue, void *pkt, u32 len,\n+\t\t\t\t u32 flags, u32 client_ctrl, u32 *rem_len)\n+{\n+\tvoid *free_pkt = NULL;\n+\tstruct rx_queue_desc *desc = queue->base + queue->write_idx;\n+\n+\tif (readl(&desc->ctrl) & CL_DESC_OWN) {\n+\t\tif (page_mode) {\n+\t\t\tint rem_page_size = PAGE_SIZE -\n+\t\t\t\t\tPRESENT_OFST_IN_PAGE(pkt);\n+\t\t\tint cur_pkt_size = ROUND_MIN_RX_SIZE(len +\n+\t\t\t\t\tpfe_pkt_headroom);\n+\t\t\t*rem_len = (rem_page_size - cur_pkt_size);\n+\t\t\tif (*rem_len) {\n+\t\t\t\tfree_pkt = pkt + cur_pkt_size;\n+\t\t\t\tget_page(virt_to_page(free_pkt));\n+\t\t\t} else {\n+\t\t\t\tfree_pkt = (void\n+\t\t\t\t*)__get_free_page(GFP_ATOMIC | GFP_DMA_PFE);\n+\t\t\t\t*rem_len = pfe_pkt_size;\n+\t\t\t}\n+\t\t} else {\n+\t\t\tfree_pkt = kmalloc(PFE_BUF_SIZE, GFP_ATOMIC |\n+\t\t\t\t\tGFP_DMA_PFE);\n+\t\t\t*rem_len = PFE_BUF_SIZE - pfe_pkt_headroom;\n+\t\t}\n+\n+\t\tif (free_pkt) {\n+\t\t\tdesc->data = pkt;\n+\t\t\tdesc->client_ctrl = client_ctrl;\n+\t\t\t/*\n+\t\t\t * Ensure everything else is written to DDR before\n+\t\t\t * writing bd->ctrl\n+\t\t\t */\n+\t\t\tsmp_wmb();\n+\t\t\twritel(CL_DESC_BUF_LEN(len) | flags, &desc->ctrl);\n+\t\t\tqueue->write_idx = (queue->write_idx + 1)\n+\t\t\t\t\t    & (queue->size - 1);\n+\n+\t\t\tfree_pkt += pfe_pkt_headroom;\n+\t\t}\n+\t}\n+\n+\treturn free_pkt;\n+}\n+\n+/*\n+ * pfe_hif_rx_process-\n+ * This function does pfe hif rx queue processing.\n+ * Dequeue packet from Rx queue and send it to corresponding client queue\n+ */\n+static int pfe_hif_rx_process(struct pfe_hif *hif, int budget)\n+{\n+\tstruct hif_desc\t*desc;\n+\tstruct hif_hdr *pkt_hdr;\n+\tstruct __hif_hdr hif_hdr;\n+\tvoid *free_buf;\n+\tint rtc, len, rx_processed = 0;\n+\tstruct __hif_desc local_desc;\n+\tint flags;\n+\tunsigned int desc_p;\n+\tunsigned int buf_size = 0;\n+\n+\tspin_lock_bh(&hif->lock);\n+\n+\trtc = hif->rxtoclean_index;\n+\n+\twhile (rx_processed < budget) {\n+\t\tdesc = hif->rx_base + rtc;\n+\n+\t\t__memcpy12(&local_desc, desc);\n+\n+\t\t/* ACK pending Rx interrupt */\n+\t\tif (local_desc.ctrl & BD_CTRL_DESC_EN) {\n+\t\t\twritel(HIF_INT | HIF_RXPKT_INT, HIF_INT_SRC);\n+\n+\t\t\tif (rx_processed == 0) {\n+\t\t\t\tif (napi_first_batch == 1) {\n+\t\t\t\t\tdesc_p = hif->descr_baseaddr_p +\n+\t\t\t\t\t((unsigned long int)(desc) -\n+\t\t\t\t\t(unsigned long\n+\t\t\t\t\tint)hif->descr_baseaddr_v);\n+\t\t\t\t\tnapi_first_batch = 0;\n+\t\t\t\t}\n+\t\t\t}\n+\n+\t\t\t__memcpy12(&local_desc, desc);\n+\n+\t\t\tif (local_desc.ctrl & BD_CTRL_DESC_EN)\n+\t\t\t\tbreak;\n+\t\t}\n+\n+\t\tnapi_first_batch = 0;\n+\n+#ifdef HIF_NAPI_STATS\n+\t\thif->napi_counters[NAPI_DESC_COUNT]++;\n+#endif\n+\t\tlen = BD_BUF_LEN(local_desc.ctrl);\n+\t\t/*\n+\t\t * dma_unmap_single(hif->dev, DDR_PFE_TO_PHYS(local_desc.data),\n+\t\t * hif->rx_buf_len[rtc], DMA_FROM_DEVICE);\n+\t\t */\n+\t\tdma_unmap_single(hif->dev, DDR_PFE_TO_PHYS(local_desc.data),\n+\t\t\t\t hif->rx_buf_len[rtc], DMA_FROM_DEVICE);\n+\n+\t\tpkt_hdr = (struct hif_hdr *)hif->rx_buf_addr[rtc];\n+\n+\t\t/* Track last HIF header received */\n+\t\tif (!hif->started) {\n+\t\t\thif->started = 1;\n+\n+\t\t\t__memcpy8(&hif_hdr, pkt_hdr);\n+\n+\t\t\thif->qno = hif_hdr.hdr.q_num;\n+\t\t\thif->client_id = hif_hdr.hdr.client_id;\n+\t\t\thif->client_ctrl = (hif_hdr.hdr.client_ctrl1 << 16) |\n+\t\t\t\t\t\thif_hdr.hdr.client_ctrl;\n+\t\t\tflags = CL_DESC_FIRST;\n+\n+\t\t} else {\n+\t\t\tflags = 0;\n+\t\t}\n+\n+\t\tif (local_desc.ctrl & BD_CTRL_LIFM)\n+\t\t\tflags |= CL_DESC_LAST;\n+\n+\t\t/* Check for valid client id and still registered */\n+\t\tif ((hif->client_id >= HIF_CLIENTS_MAX) ||\n+\t\t    !(test_bit(hif->client_id,\n+\t\t\t&hif->shm->g_client_status[0]))) {\n+\t\t\tprintk_ratelimited(\"%s: packet with invalid client id %d q_num %d\\n\",\n+\t\t\t\t\t   __func__,\n+\t\t\t\t\t   hif->client_id,\n+\t\t\t\t\t   hif->qno);\n+\n+\t\t\tfree_buf = pkt_hdr;\n+\n+\t\t\tgoto pkt_drop;\n+\t\t}\n+\n+\t\t/* Check to valid queue number */\n+\t\tif (hif->client[hif->client_id].rx_qn <= hif->qno) {\n+\t\t\tpr_info(\"%s: packet with invalid queue: %d\\n\"\n+\t\t\t\t, __func__, hif->qno);\n+\t\t\thif->qno = 0;\n+\t\t}\n+\n+\t\tfree_buf =\n+\t\tclient_put_rxpacket(&hif->client[hif->client_id].rx_q[hif->qno],\n+\t\t\t\t    (void *)pkt_hdr, len, flags,\n+\t\t\thif->client_ctrl, &buf_size);\n+\n+\t\thif_lib_indicate_client(hif->client_id, EVENT_RX_PKT_IND,\n+\t\t\t\t\thif->qno);\n+\n+\t\tif (unlikely(!free_buf)) {\n+#ifdef HIF_NAPI_STATS\n+\t\t\thif->napi_counters[NAPI_CLIENT_FULL_COUNT]++;\n+#endif\n+\t\t\t/*\n+\t\t\t * If we want to keep in polling mode to retry later,\n+\t\t\t * we need to tell napi that we consumed\n+\t\t\t * the full budget or we will hit a livelock scenario.\n+\t\t\t * The core code keeps this napi instance\n+\t\t\t * at the head of the list and none of the other\n+\t\t\t * instances get to run\n+\t\t\t */\n+\t\t\trx_processed = budget;\n+\n+\t\t\tif (flags & CL_DESC_FIRST)\n+\t\t\t\thif->started = 0;\n+\n+\t\t\tbreak;\n+\t\t}\n+\n+pkt_drop:\n+\t\t/*Fill free buffer in the descriptor */\n+\t\thif->rx_buf_addr[rtc] = free_buf;\n+\t\thif->rx_buf_len[rtc] = min(pfe_pkt_size, buf_size);\n+\t\twritel((DDR_PHYS_TO_PFE\n+\t\t\t((u32)dma_map_single(hif->dev,\n+\t\t\tfree_buf, hif->rx_buf_len[rtc], DMA_FROM_DEVICE))),\n+\t\t\t&desc->data);\n+\t\t/*\n+\t\t * Ensure everything else is written to DDR before\n+\t\t * writing bd->ctrl\n+\t\t */\n+\t\twmb();\n+\t\twritel((BD_CTRL_PKT_INT_EN | BD_CTRL_LIFM | BD_CTRL_DIR |\n+\t\t\tBD_CTRL_DESC_EN | BD_BUF_LEN(hif->rx_buf_len[rtc])),\n+\t\t\t&desc->ctrl);\n+\n+\t\trtc = (rtc + 1) & (hif->rx_ring_size - 1);\n+\n+\t\tif (local_desc.ctrl & BD_CTRL_LIFM) {\n+\t\t\tif (!(hif->client_ctrl & HIF_CTRL_RX_CONTINUED)) {\n+\t\t\t\trx_processed++;\n+\n+#ifdef HIF_NAPI_STATS\n+\t\t\t\thif->napi_counters[NAPI_PACKET_COUNT]++;\n+#endif\n+\t\t\t}\n+\t\t\thif->started = 0;\n+\t\t}\n+\t}\n+\n+\thif->rxtoclean_index = rtc;\n+\tspin_unlock_bh(&hif->lock);\n+\n+\t/* we made some progress, re-start rx dma in case it stopped */\n+\thif_rx_dma_start();\n+\n+\treturn rx_processed;\n+}\n+\n+/*\n+ * client_ack_txpacket-\n+ * This function ack the Tx packet in the give client Tx queue by resetting\n+ * ownership bit in the descriptor.\n+ */\n+static int client_ack_txpacket(struct pfe_hif *hif, unsigned int client_id,\n+\t\t\t       unsigned int q_no)\n+{\n+\tstruct hif_tx_queue *queue = &hif->client[client_id].tx_q[q_no];\n+\tstruct tx_queue_desc *desc = queue->base + queue->ack_idx;\n+\n+\tif (readl(&desc->ctrl) & CL_DESC_OWN) {\n+\t\twritel((readl(&desc->ctrl) & ~CL_DESC_OWN), &desc->ctrl);\n+\t\tqueue->ack_idx = (queue->ack_idx + 1) & (queue->size - 1);\n+\n+\t\treturn 0;\n+\n+\t} else {\n+\t\t/*This should not happen */\n+\t\tpr_err(\"%s: %d %d %d %d %d %p %d\\n\", __func__,\n+\t\t       hif->txtosend, hif->txtoclean, hif->txavail,\n+\t\t\tclient_id, q_no, queue, queue->ack_idx);\n+\t\tWARN(1, \"%s: doesn't own this descriptor\", __func__);\n+\t\treturn 1;\n+\t}\n+}\n+\n+void __hif_tx_done_process(struct pfe_hif *hif, int count)\n+{\n+\tstruct hif_desc *desc;\n+\tstruct hif_desc_sw *desc_sw;\n+\tint ttc, tx_avl;\n+\tint pkts_done[HIF_CLIENTS_MAX] = {0, 0};\n+\n+\tttc = hif->txtoclean;\n+\ttx_avl = hif->txavail;\n+\n+\twhile ((tx_avl < hif->tx_ring_size) && count--) {\n+\t\tdesc = hif->tx_base + ttc;\n+\n+\t\tif (readl(&desc->ctrl) & BD_CTRL_DESC_EN)\n+\t\t\tbreak;\n+\n+\t\tdesc_sw = &hif->tx_sw_queue[ttc];\n+\n+\t\tif (desc_sw->data) {\n+\t\t\t/*\n+\t\t\t * dmap_unmap_single(hif->dev, desc_sw->data,\n+\t\t\t * desc_sw->len, DMA_TO_DEVICE);\n+\t\t\t */\n+\t\t\tdma_unmap_single(hif->dev, desc_sw->data,\n+\t\t\t\t\t desc_sw->len, DMA_TO_DEVICE);\n+\t\t}\n+\n+\t\tif (desc_sw->client_id >= HIF_CLIENTS_MAX) {\n+\t\t\tpr_err(\"Invalid cl id %d\\n\", desc_sw->client_id);\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\tpkts_done[desc_sw->client_id]++;\n+\n+\t\tclient_ack_txpacket(hif, desc_sw->client_id, desc_sw->q_no);\n+\n+\t\tttc = (ttc + 1) & (hif->tx_ring_size - 1);\n+\t\ttx_avl++;\n+\t}\n+\n+\tif (pkts_done[0])\n+\t\thif_lib_indicate_client(0, EVENT_TXDONE_IND, 0);\n+\tif (pkts_done[1])\n+\t\thif_lib_indicate_client(1, EVENT_TXDONE_IND, 0);\n+\n+\thif->txtoclean = ttc;\n+\thif->txavail = tx_avl;\n+\n+\tif (!count) {\n+\t\ttasklet_schedule(&hif->tx_cleanup_tasklet);\n+\t} else {\n+\t\t/*Enable Tx done interrupt */\n+\t\twritel(readl_relaxed(HIF_INT_ENABLE) | HIF_TXPKT_INT,\n+\t\t       HIF_INT_ENABLE);\n+\t}\n+}\n+\n+static void pfe_tx_do_cleanup(unsigned long data)\n+{\n+\tstruct pfe_hif *hif = (struct pfe_hif *)data;\n+\n+\twritel(HIF_INT | HIF_TXPKT_INT, HIF_INT_SRC);\n+\n+\thif_tx_done_process(hif, 64);\n+}\n+\n+/*\n+ * __hif_xmit_pkt -\n+ * This function puts one packet in the HIF Tx queue\n+ */\n+void __hif_xmit_pkt(struct pfe_hif *hif, unsigned int client_id, unsigned int\n+\t\t\tq_no, void *data, u32 len, unsigned int flags)\n+{\n+\tstruct hif_desc\t*desc;\n+\tstruct hif_desc_sw *desc_sw;\n+\n+\tdesc = hif->tx_base + hif->txtosend;\n+\tdesc_sw = &hif->tx_sw_queue[hif->txtosend];\n+\n+\tdesc_sw->len = len;\n+\tdesc_sw->client_id = client_id;\n+\tdesc_sw->q_no = q_no;\n+\tdesc_sw->flags = flags;\n+\n+\tif (flags & HIF_DONT_DMA_MAP) {\n+\t\tdesc_sw->data = 0;\n+\t\twritel((u32)DDR_PHYS_TO_PFE(data), &desc->data);\n+\t} else {\n+\t\tdesc_sw->data = dma_map_single(hif->dev, data, len,\n+\t\t\t\t\t\tDMA_TO_DEVICE);\n+\t\twritel((u32)DDR_PHYS_TO_PFE(desc_sw->data), &desc->data);\n+\t}\n+\n+\thif->txtosend = (hif->txtosend + 1) & (hif->tx_ring_size - 1);\n+\thif->txavail--;\n+\n+\tif ((!((flags & HIF_DATA_VALID) && (flags &\n+\t\t\t\tHIF_LAST_BUFFER))))\n+\t\tgoto skip_tx;\n+\n+\t/*\n+\t * Ensure everything else is written to DDR before\n+\t * writing bd->ctrl\n+\t */\n+\twmb();\n+\n+\tdo {\n+\t\tdesc_sw = &hif->tx_sw_queue[hif->txtoflush];\n+\t\tdesc = hif->tx_base + hif->txtoflush;\n+\n+\t\tif (desc_sw->flags & HIF_LAST_BUFFER) {\n+\t\t\twritel((BD_CTRL_LIFM |\n+\t\t\t       BD_CTRL_BRFETCH_DISABLE | BD_CTRL_RTFETCH_DISABLE\n+\t\t\t       | BD_CTRL_PARSE_DISABLE | BD_CTRL_DESC_EN |\n+\t\t\t\tBD_CTRL_PKT_INT_EN | BD_BUF_LEN(desc_sw->len)),\n+\t\t\t\t&desc->ctrl);\n+\t\t} else {\n+\t\t\twritel((BD_CTRL_DESC_EN |\n+\t\t\t\tBD_BUF_LEN(desc_sw->len)), &desc->ctrl);\n+\t\t}\n+\t\thif->txtoflush = (hif->txtoflush + 1) & (hif->tx_ring_size - 1);\n+\t}\n+\twhile (hif->txtoflush != hif->txtosend)\n+\t\t;\n+\n+skip_tx:\n+\treturn;\n+}\n+\n+static irqreturn_t wol_isr(int irq, void *dev_id)\n+{\n+\tpr_info(\"WoL\\n\");\n+\tgemac_set_wol(EMAC1_BASE_ADDR, 0);\n+\tgemac_set_wol(EMAC2_BASE_ADDR, 0);\n+\treturn IRQ_HANDLED;\n+}\n+\n+/*\n+ * hif_isr-\n+ * This ISR routine processes Rx/Tx done interrupts from the HIF hardware block\n+ */\n+static irqreturn_t hif_isr(int irq, void *dev_id)\n+{\n+\tstruct pfe_hif *hif = (struct pfe_hif *)dev_id;\n+\tint int_status;\n+\tint int_enable_mask;\n+\n+\t/*Read hif interrupt source register */\n+\tint_status = readl_relaxed(HIF_INT_SRC);\n+\tint_enable_mask = readl_relaxed(HIF_INT_ENABLE);\n+\n+\tif ((int_status & HIF_INT) == 0)\n+\t\treturn IRQ_NONE;\n+\n+\tint_status &= ~(HIF_INT);\n+\n+\tif (int_status & HIF_RXPKT_INT) {\n+\t\tint_status &= ~(HIF_RXPKT_INT);\n+\t\tint_enable_mask &= ~(HIF_RXPKT_INT);\n+\n+\t\tnapi_first_batch = 1;\n+\n+\t\tif (napi_schedule_prep(&hif->napi)) {\n+#ifdef HIF_NAPI_STATS\n+\t\t\thif->napi_counters[NAPI_SCHED_COUNT]++;\n+#endif\n+\t\t\t__napi_schedule(&hif->napi);\n+\t\t}\n+\t}\n+\n+\tif (int_status & HIF_TXPKT_INT) {\n+\t\tint_status &= ~(HIF_TXPKT_INT);\n+\t\tint_enable_mask &= ~(HIF_TXPKT_INT);\n+\t\t/*Schedule tx cleanup tassklet */\n+\t\ttasklet_schedule(&hif->tx_cleanup_tasklet);\n+\t}\n+\n+\t/*Disable interrupts, they will be enabled after they are serviced */\n+\twritel_relaxed(int_enable_mask, HIF_INT_ENABLE);\n+\n+\tif (int_status) {\n+\t\tpr_info(\"%s : Invalid interrupt : %d\\n\", __func__,\n+\t\t\tint_status);\n+\t\twritel(int_status, HIF_INT_SRC);\n+\t}\n+\n+\treturn IRQ_HANDLED;\n+}\n+\n+void hif_process_client_req(struct pfe_hif *hif, int req, int data1, int data2)\n+{\n+\tunsigned int client_id = data1;\n+\n+\tif (client_id >= HIF_CLIENTS_MAX) {\n+\t\tpr_err(\"%s: client id %d out of bounds\\n\", __func__,\n+\t\t       client_id);\n+\t\treturn;\n+\t}\n+\n+\tswitch (req) {\n+\tcase REQUEST_CL_REGISTER:\n+\t\t\t/* Request for register a client */\n+\t\t\tpr_info(\"%s: register client_id %d\\n\",\n+\t\t\t\t__func__, client_id);\n+\t\t\tpfe_hif_client_register(hif, client_id, (struct\n+\t\t\t\thif_client_shm *)&hif->shm->client[client_id]);\n+\t\t\tbreak;\n+\n+\tcase REQUEST_CL_UNREGISTER:\n+\t\t\tpr_info(\"%s: unregister client_id %d\\n\",\n+\t\t\t\t__func__, client_id);\n+\n+\t\t\t/* Request for unregister a client */\n+\t\t\tpfe_hif_client_unregister(hif, client_id);\n+\n+\t\t\tbreak;\n+\n+\tdefault:\n+\t\t\tpr_err(\"%s: unsupported request %d\\n\",\n+\t\t\t       __func__, req);\n+\t\t\tbreak;\n+\t}\n+\n+\t/*\n+\t * Process client Tx queues\n+\t * Currently we don't have checking for tx pending\n+\t */\n+}\n+\n+/*\n+ * pfe_hif_rx_poll\n+ *  This function is NAPI poll function to process HIF Rx queue.\n+ */\n+static int pfe_hif_rx_poll(struct napi_struct *napi, int budget)\n+{\n+\tstruct pfe_hif *hif = container_of(napi, struct pfe_hif, napi);\n+\tint work_done;\n+\n+#ifdef HIF_NAPI_STATS\n+\thif->napi_counters[NAPI_POLL_COUNT]++;\n+#endif\n+\n+\twork_done = pfe_hif_rx_process(hif, budget);\n+\n+\tif (work_done < budget) {\n+\t\tnapi_complete(napi);\n+\t\twritel(readl_relaxed(HIF_INT_ENABLE) | HIF_RXPKT_INT,\n+\t\t       HIF_INT_ENABLE);\n+\t}\n+#ifdef HIF_NAPI_STATS\n+\telse\n+\t\thif->napi_counters[NAPI_FULL_BUDGET_COUNT]++;\n+#endif\n+\n+\treturn work_done;\n+}\n+\n+/*\n+ * pfe_hif_init\n+ * This function initializes the baseaddresses and irq, etc.\n+ */\n+int pfe_hif_init(struct pfe *pfe)\n+{\n+\tstruct pfe_hif *hif = &pfe->hif;\n+\tint err;\n+\n+\tpr_info(\"%s\\n\", __func__);\n+\n+\thif->dev = pfe->dev;\n+\thif->irq = pfe->hif_irq;\n+\n+\terr = pfe_hif_alloc_descr(hif);\n+\tif (err)\n+\t\tgoto err0;\n+\n+\tif (pfe_hif_init_buffers(hif)) {\n+\t\tpr_err(\"%s: Could not initialize buffer descriptors\\n\"\n+\t\t\t, __func__);\n+\t\terr = -ENOMEM;\n+\t\tgoto err1;\n+\t}\n+\n+\t/* Initialize NAPI for Rx processing */\n+\tinit_dummy_netdev(&hif->dummy_dev);\n+\tnetif_napi_add(&hif->dummy_dev, &hif->napi, pfe_hif_rx_poll,\n+\t\t       HIF_RX_POLL_WEIGHT);\n+\tnapi_enable(&hif->napi);\n+\n+\tspin_lock_init(&hif->tx_lock);\n+\tspin_lock_init(&hif->lock);\n+\n+\thif_init();\n+\thif_rx_enable();\n+\thif_tx_enable();\n+\n+\t/* Disable tx done interrupt */\n+\twritel(HIF_INT_MASK, HIF_INT_ENABLE);\n+\n+\tgpi_enable(HGPI_BASE_ADDR);\n+\n+\terr = request_irq(hif->irq, hif_isr, 0, \"pfe_hif\", hif);\n+\tif (err) {\n+\t\tpr_err(\"%s: failed to get the hif IRQ = %d\\n\",\n+\t\t       __func__, hif->irq);\n+\t\tgoto err1;\n+\t}\n+\n+\terr = request_irq(pfe->wol_irq, wol_isr, 0, \"pfe_wol\", pfe);\n+\tif (err) {\n+\t\tpr_err(\"%s: failed to get the wol IRQ = %d\\n\",\n+\t\t       __func__, pfe->wol_irq);\n+\t\tgoto err1;\n+\t}\n+\n+\ttasklet_init(&hif->tx_cleanup_tasklet,\n+\t\t     (void(*)(unsigned long))pfe_tx_do_cleanup,\n+\t\t     (unsigned long)hif);\n+\n+\treturn 0;\n+err1:\n+\tpfe_hif_free_descr(hif);\n+err0:\n+\treturn err;\n+}\n+\n+/* pfe_hif_exit- */\n+void pfe_hif_exit(struct pfe *pfe)\n+{\n+\tstruct pfe_hif *hif = &pfe->hif;\n+\n+\tpr_info(\"%s\\n\", __func__);\n+\n+\ttasklet_kill(&hif->tx_cleanup_tasklet);\n+\n+\tspin_lock_bh(&hif->lock);\n+\thif->shm->g_client_status[0] = 0;\n+\t/* Make sure all clients are disabled*/\n+\thif->shm->g_client_status[1] = 0;\n+\n+\tspin_unlock_bh(&hif->lock);\n+\n+\t/*Disable Rx/Tx */\n+\tgpi_disable(HGPI_BASE_ADDR);\n+\thif_rx_disable();\n+\thif_tx_disable();\n+\n+\tnapi_disable(&hif->napi);\n+\tnetif_napi_del(&hif->napi);\n+\n+\tfree_irq(pfe->wol_irq, pfe);\n+\tfree_irq(hif->irq, hif);\n+\n+\tpfe_hif_release_buffers(hif);\n+\tpfe_hif_free_descr(hif);\n+}\n--- /dev/null\n+++ b/drivers/staging/fsl_ppfe/pfe_hif.h\n@@ -0,0 +1,199 @@\n+/* SPDX-License-Identifier: GPL-2.0+ */\n+/*\n+ * Copyright 2015-2016 Freescale Semiconductor, Inc.\n+ * Copyright 2017 NXP\n+ */\n+\n+#ifndef _PFE_HIF_H_\n+#define _PFE_HIF_H_\n+\n+#include <linux/netdevice.h>\n+\n+#define HIF_NAPI_STATS\n+\n+#define HIF_CLIENT_QUEUES_MAX\t16\n+#define HIF_RX_POLL_WEIGHT\t64\n+\n+#define HIF_RX_PKT_MIN_SIZE 0x800 /* 2KB */\n+#define HIF_RX_PKT_MIN_SIZE_MASK ~(HIF_RX_PKT_MIN_SIZE - 1)\n+#define ROUND_MIN_RX_SIZE(_sz) (((_sz) + (HIF_RX_PKT_MIN_SIZE - 1)) \\\n+\t\t\t\t\t& HIF_RX_PKT_MIN_SIZE_MASK)\n+#define PRESENT_OFST_IN_PAGE(_buf) (((unsigned long int)(_buf) & (PAGE_SIZE \\\n+\t\t\t\t\t- 1)) & HIF_RX_PKT_MIN_SIZE_MASK)\n+\n+enum {\n+\tNAPI_SCHED_COUNT = 0,\n+\tNAPI_POLL_COUNT,\n+\tNAPI_PACKET_COUNT,\n+\tNAPI_DESC_COUNT,\n+\tNAPI_FULL_BUDGET_COUNT,\n+\tNAPI_CLIENT_FULL_COUNT,\n+\tNAPI_MAX_COUNT\n+};\n+\n+/*\n+ * HIF_TX_DESC_NT value should be always greter than 4,\n+ * Otherwise HIF_TX_POLL_MARK will become zero.\n+ */\n+#define HIF_RX_DESC_NT\t\t256\n+#define HIF_TX_DESC_NT\t\t2048\n+\n+#define HIF_FIRST_BUFFER\tBIT(0)\n+#define HIF_LAST_BUFFER\t\tBIT(1)\n+#define HIF_DONT_DMA_MAP\tBIT(2)\n+#define HIF_DATA_VALID\t\tBIT(3)\n+#define HIF_TSO\t\t\tBIT(4)\n+\n+enum {\n+\tPFE_CL_GEM0 = 0,\n+\tPFE_CL_GEM1,\n+\tHIF_CLIENTS_MAX\n+};\n+\n+/*structure to store client queue info */\n+struct hif_rx_queue {\n+\tstruct rx_queue_desc *base;\n+\tu32\tsize;\n+\tu32\twrite_idx;\n+};\n+\n+struct hif_tx_queue {\n+\tstruct tx_queue_desc *base;\n+\tu32\tsize;\n+\tu32\tack_idx;\n+};\n+\n+/*Structure to store the client info */\n+struct hif_client {\n+\tint\trx_qn;\n+\tstruct hif_rx_queue\trx_q[HIF_CLIENT_QUEUES_MAX];\n+\tint\ttx_qn;\n+\tstruct hif_tx_queue\ttx_q[HIF_CLIENT_QUEUES_MAX];\n+};\n+\n+/*HIF hardware buffer descriptor */\n+struct hif_desc {\n+\tu32 ctrl;\n+\tu32 status;\n+\tu32 data;\n+\tu32 next;\n+};\n+\n+struct __hif_desc {\n+\tu32 ctrl;\n+\tu32 status;\n+\tu32 data;\n+};\n+\n+struct hif_desc_sw {\n+\tdma_addr_t data;\n+\tu16 len;\n+\tu8 client_id;\n+\tu8 q_no;\n+\tu16 flags;\n+};\n+\n+struct hif_hdr {\n+\tu8 client_id;\n+\tu8 q_num;\n+\tu16 client_ctrl;\n+\tu16 client_ctrl1;\n+};\n+\n+struct __hif_hdr {\n+\tunion {\n+\t\tstruct hif_hdr hdr;\n+\t\tu32 word[2];\n+\t};\n+};\n+\n+struct hif_ipsec_hdr {\n+\tu16\tsa_handle[2];\n+} __packed;\n+\n+/*  HIF_CTRL_TX... defines */\n+#define HIF_CTRL_TX_CHECKSUM\t\tBIT(2)\n+\n+/*  HIF_CTRL_RX... defines */\n+#define HIF_CTRL_RX_OFFSET_OFST         (24)\n+#define HIF_CTRL_RX_CHECKSUMMED\t\tBIT(2)\n+#define HIF_CTRL_RX_CONTINUED\t\tBIT(1)\n+\n+struct pfe_hif {\n+\t/* To store registered clients in hif layer */\n+\tstruct hif_client client[HIF_CLIENTS_MAX];\n+\tstruct hif_shm *shm;\n+\tint\tirq;\n+\n+\tvoid\t*descr_baseaddr_v;\n+\tunsigned long\tdescr_baseaddr_p;\n+\n+\tstruct hif_desc *rx_base;\n+\tu32\trx_ring_size;\n+\tu32\trxtoclean_index;\n+\tvoid\t*rx_buf_addr[HIF_RX_DESC_NT];\n+\tint\trx_buf_len[HIF_RX_DESC_NT];\n+\tunsigned int qno;\n+\tunsigned int client_id;\n+\tunsigned int client_ctrl;\n+\tunsigned int started;\n+\n+\tstruct hif_desc *tx_base;\n+\tu32\ttx_ring_size;\n+\tu32\ttxtosend;\n+\tu32\ttxtoclean;\n+\tu32\ttxavail;\n+\tu32\ttxtoflush;\n+\tstruct hif_desc_sw tx_sw_queue[HIF_TX_DESC_NT];\n+\n+/* tx_lock synchronizes hif packet tx as well as pfe_hif structure access */\n+\tspinlock_t tx_lock;\n+/* lock synchronizes hif rx queue processing */\n+\tspinlock_t lock;\n+\tstruct net_device\tdummy_dev;\n+\tstruct napi_struct\tnapi;\n+\tstruct device *dev;\n+\n+#ifdef HIF_NAPI_STATS\n+\tunsigned int napi_counters[NAPI_MAX_COUNT];\n+#endif\n+\tstruct tasklet_struct\ttx_cleanup_tasklet;\n+};\n+\n+void __hif_xmit_pkt(struct pfe_hif *hif, unsigned int client_id, unsigned int\n+\t\t\tq_no, void *data, u32 len, unsigned int flags);\n+int hif_xmit_pkt(struct pfe_hif *hif, unsigned int client_id, unsigned int q_no,\n+\t\t void *data, unsigned int len);\n+void __hif_tx_done_process(struct pfe_hif *hif, int count);\n+void hif_process_client_req(struct pfe_hif *hif, int req, int data1, int\n+\t\t\t\tdata2);\n+int pfe_hif_init(struct pfe *pfe);\n+void pfe_hif_exit(struct pfe *pfe);\n+void pfe_hif_rx_idle(struct pfe_hif *hif);\n+static inline void hif_tx_done_process(struct pfe_hif *hif, int count)\n+{\n+\tspin_lock_bh(&hif->tx_lock);\n+\t__hif_tx_done_process(hif, count);\n+\tspin_unlock_bh(&hif->tx_lock);\n+}\n+\n+static inline void hif_tx_lock(struct pfe_hif *hif)\n+{\n+\tspin_lock_bh(&hif->tx_lock);\n+}\n+\n+static inline void hif_tx_unlock(struct pfe_hif *hif)\n+{\n+\tspin_unlock_bh(&hif->tx_lock);\n+}\n+\n+static inline int __hif_tx_avail(struct pfe_hif *hif)\n+{\n+\treturn hif->txavail;\n+}\n+\n+#define __memcpy8(dst, src)\t\tmemcpy(dst, src, 8)\n+#define __memcpy12(dst, src)\t\tmemcpy(dst, src, 12)\n+#define __memcpy(dst, src, len)\t\tmemcpy(dst, src, len)\n+\n+#endif /* _PFE_HIF_H_ */\n--- /dev/null\n+++ b/drivers/staging/fsl_ppfe/pfe_hif_lib.c\n@@ -0,0 +1,628 @@\n+// SPDX-License-Identifier: GPL-2.0+\n+/*\n+ * Copyright 2015-2016 Freescale Semiconductor, Inc.\n+ * Copyright 2017 NXP\n+ */\n+\n+#include <linux/version.h>\n+#include <linux/kernel.h>\n+#include <linux/slab.h>\n+#include <linux/interrupt.h>\n+#include <linux/workqueue.h>\n+#include <linux/dma-mapping.h>\n+#include <linux/dmapool.h>\n+#include <linux/sched.h>\n+#include <linux/skbuff.h>\n+#include <linux/moduleparam.h>\n+#include <linux/cpu.h>\n+\n+#include \"pfe_mod.h\"\n+#include \"pfe_hif.h\"\n+#include \"pfe_hif_lib.h\"\n+\n+unsigned int lro_mode;\n+unsigned int page_mode;\n+unsigned int tx_qos = 1;\n+module_param(tx_qos, uint, 0444);\n+MODULE_PARM_DESC(tx_qos, \"0: disable ,\\n\"\n+\t\t\t \"1: enable (default), guarantee no packet drop at TMU level\\n\");\n+unsigned int pfe_pkt_size;\n+unsigned int pfe_pkt_headroom;\n+unsigned int emac_txq_cnt;\n+\n+/*\n+ * @pfe_hal_lib.c.\n+ * Common functions used by HIF client drivers\n+ */\n+\n+/*HIF shared memory Global variable */\n+struct hif_shm ghif_shm;\n+\n+/* Cleanup the HIF shared memory, release HIF rx_buffer_pool.\n+ * This function should be called after pfe_hif_exit\n+ *\n+ * @param[in] hif_shm\t\tShared memory address location in DDR\n+ */\n+static void pfe_hif_shm_clean(struct hif_shm *hif_shm)\n+{\n+\tint i;\n+\tvoid *pkt;\n+\n+\tfor (i = 0; i < hif_shm->rx_buf_pool_cnt; i++) {\n+\t\tpkt = hif_shm->rx_buf_pool[i];\n+\t\tif (pkt) {\n+\t\t\thif_shm->rx_buf_pool[i] = NULL;\n+\t\t\tpkt -= pfe_pkt_headroom;\n+\n+\t\t\tif (page_mode)\n+\t\t\t\tput_page(virt_to_page(pkt));\n+\t\t\telse\n+\t\t\t\tkfree(pkt);\n+\t\t}\n+\t}\n+}\n+\n+/* Initialize shared memory used between HIF driver and clients,\n+ * allocate rx_buffer_pool required for HIF Rx descriptors.\n+ * This function should be called before initializing HIF driver.\n+ *\n+ * @param[in] hif_shm\t\tShared memory address location in DDR\n+ * @rerurn\t\t\t0 - on succes, <0 on fail to initialize\n+ */\n+static int pfe_hif_shm_init(struct hif_shm *hif_shm)\n+{\n+\tint i;\n+\tvoid *pkt;\n+\n+\tmemset(hif_shm, 0, sizeof(struct hif_shm));\n+\thif_shm->rx_buf_pool_cnt = HIF_RX_DESC_NT;\n+\n+\tfor (i = 0; i < hif_shm->rx_buf_pool_cnt; i++) {\n+\t\tif (page_mode) {\n+\t\t\tpkt = (void *)__get_free_page(GFP_KERNEL |\n+\t\t\t\tGFP_DMA_PFE);\n+\t\t} else {\n+\t\t\tpkt = kmalloc(PFE_BUF_SIZE, GFP_KERNEL | GFP_DMA_PFE);\n+\t\t}\n+\n+\t\tif (pkt)\n+\t\t\thif_shm->rx_buf_pool[i] = pkt + pfe_pkt_headroom;\n+\t\telse\n+\t\t\tgoto err0;\n+\t}\n+\n+\treturn 0;\n+\n+err0:\n+\tpr_err(\"%s Low memory\\n\", __func__);\n+\tpfe_hif_shm_clean(hif_shm);\n+\treturn -ENOMEM;\n+}\n+\n+/*This function sends indication to HIF driver\n+ *\n+ * @param[in] hif\thif context\n+ */\n+static void hif_lib_indicate_hif(struct pfe_hif *hif, int req, int data1, int\n+\t\t\t\t\tdata2)\n+{\n+\thif_process_client_req(hif, req, data1, data2);\n+}\n+\n+void hif_lib_indicate_client(int client_id, int event_type, int qno)\n+{\n+\tstruct hif_client_s *client = pfe->hif_client[client_id];\n+\n+\tif (!client || (event_type >= HIF_EVENT_MAX) || (qno >=\n+\t\tHIF_CLIENT_QUEUES_MAX))\n+\t\treturn;\n+\n+\tif (!test_and_set_bit(qno, &client->queue_mask[event_type]))\n+\t\tclient->event_handler(client->priv, event_type, qno);\n+}\n+\n+/*This function releases Rx queue descriptors memory and pre-filled buffers\n+ *\n+ * @param[in] client\thif_client context\n+ */\n+static void hif_lib_client_release_rx_buffers(struct hif_client_s *client)\n+{\n+\tstruct rx_queue_desc *desc;\n+\tint qno, ii;\n+\tvoid *buf;\n+\n+\tfor (qno = 0; qno < client->rx_qn; qno++) {\n+\t\tdesc = client->rx_q[qno].base;\n+\n+\t\tfor (ii = 0; ii < client->rx_q[qno].size; ii++) {\n+\t\t\tbuf = (void *)desc->data;\n+\t\t\tif (buf) {\n+\t\t\t\tbuf -= pfe_pkt_headroom;\n+\n+\t\t\t\tif (page_mode)\n+\t\t\t\t\tfree_page((unsigned long)buf);\n+\t\t\t\telse\n+\t\t\t\t\tkfree(buf);\n+\n+\t\t\t\tdesc->ctrl = 0;\n+\t\t\t}\n+\n+\t\t\tdesc++;\n+\t\t}\n+\t}\n+\n+\tkfree(client->rx_qbase);\n+}\n+\n+/*This function allocates memory for the rxq descriptors and pre-fill rx queues\n+ * with buffers.\n+ * @param[in] client\tclient context\n+ * @param[in] q_size\tsize of the rxQ, all queues are of same size\n+ */\n+static int hif_lib_client_init_rx_buffers(struct hif_client_s *client, int\n+\t\t\t\t\t\tq_size)\n+{\n+\tstruct rx_queue_desc *desc;\n+\tstruct hif_client_rx_queue *queue;\n+\tint ii, qno;\n+\n+\t/*Allocate memory for the client queues */\n+\tclient->rx_qbase = kzalloc(client->rx_qn * q_size * sizeof(struct\n+\t\t\t\trx_queue_desc), GFP_KERNEL);\n+\tif (!client->rx_qbase)\n+\t\tgoto err;\n+\n+\tfor (qno = 0; qno < client->rx_qn; qno++) {\n+\t\tqueue = &client->rx_q[qno];\n+\n+\t\tqueue->base = client->rx_qbase + qno * q_size * sizeof(struct\n+\t\t\t\trx_queue_desc);\n+\t\tqueue->size = q_size;\n+\t\tqueue->read_idx = 0;\n+\t\tqueue->write_idx = 0;\n+\n+\t\tpr_debug(\"rx queue: %d, base: %p, size: %d\\n\", qno,\n+\t\t\t queue->base, queue->size);\n+\t}\n+\n+\tfor (qno = 0; qno < client->rx_qn; qno++) {\n+\t\tqueue = &client->rx_q[qno];\n+\t\tdesc = queue->base;\n+\n+\t\tfor (ii = 0; ii < queue->size; ii++) {\n+\t\t\tdesc->ctrl = CL_DESC_BUF_LEN(pfe_pkt_size) |\n+\t\t\t\t\tCL_DESC_OWN;\n+\t\t\tdesc++;\n+\t\t}\n+\t}\n+\n+\treturn 0;\n+\n+err:\n+\treturn 1;\n+}\n+\n+\n+static void hif_lib_client_cleanup_tx_queue(struct hif_client_tx_queue *queue)\n+{\n+\tpr_debug(\"%s\\n\", __func__);\n+\n+\t/*\n+\t * Check if there are any pending packets. Client must flush the tx\n+\t * queues before unregistering, by calling by calling\n+\t * hif_lib_tx_get_next_complete()\n+\t *\n+\t * Hif no longer calls since we are no longer registered\n+\t */\n+\tif (queue->tx_pending)\n+\t\tpr_err(\"%s: pending transmit packets\\n\", __func__);\n+}\n+\n+static void hif_lib_client_release_tx_buffers(struct hif_client_s *client)\n+{\n+\tint qno;\n+\n+\tpr_debug(\"%s\\n\", __func__);\n+\n+\tfor (qno = 0; qno < client->tx_qn; qno++)\n+\t\thif_lib_client_cleanup_tx_queue(&client->tx_q[qno]);\n+\n+\tkfree(client->tx_qbase);\n+}\n+\n+static int hif_lib_client_init_tx_buffers(struct hif_client_s *client, int\n+\t\t\t\t\t\tq_size)\n+{\n+\tstruct hif_client_tx_queue *queue;\n+\tint qno;\n+\n+\tclient->tx_qbase = kzalloc(client->tx_qn * q_size * sizeof(struct\n+\t\t\t\t\ttx_queue_desc), GFP_KERNEL);\n+\tif (!client->tx_qbase)\n+\t\treturn 1;\n+\n+\tfor (qno = 0; qno < client->tx_qn; qno++) {\n+\t\tqueue = &client->tx_q[qno];\n+\n+\t\tqueue->base = client->tx_qbase + qno * q_size * sizeof(struct\n+\t\t\t\ttx_queue_desc);\n+\t\tqueue->size = q_size;\n+\t\tqueue->read_idx = 0;\n+\t\tqueue->write_idx = 0;\n+\t\tqueue->tx_pending = 0;\n+\t\tqueue->nocpy_flag = 0;\n+\t\tqueue->prev_tmu_tx_pkts = 0;\n+\t\tqueue->done_tmu_tx_pkts = 0;\n+\n+\t\tpr_debug(\"tx queue: %d, base: %p, size: %d\\n\", qno,\n+\t\t\t queue->base, queue->size);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int hif_lib_event_dummy(void *priv, int event_type, int qno)\n+{\n+\treturn 0;\n+}\n+\n+int hif_lib_client_register(struct hif_client_s *client)\n+{\n+\tstruct hif_shm *hif_shm;\n+\tstruct hif_client_shm *client_shm;\n+\tint err, i;\n+\t/* int loop_cnt = 0; */\n+\n+\tpr_debug(\"%s\\n\", __func__);\n+\n+\t/*Allocate memory before spin_lock*/\n+\tif (hif_lib_client_init_rx_buffers(client, client->rx_qsize)) {\n+\t\terr = -ENOMEM;\n+\t\tgoto err_rx;\n+\t}\n+\n+\tif (hif_lib_client_init_tx_buffers(client, client->tx_qsize)) {\n+\t\terr = -ENOMEM;\n+\t\tgoto err_tx;\n+\t}\n+\n+\tspin_lock_bh(&pfe->hif.lock);\n+\tif (!(client->pfe) || (client->id >= HIF_CLIENTS_MAX) ||\n+\t    (pfe->hif_client[client->id])) {\n+\t\terr = -EINVAL;\n+\t\tgoto err;\n+\t}\n+\n+\thif_shm = client->pfe->hif.shm;\n+\n+\tif (!client->event_handler)\n+\t\tclient->event_handler = hif_lib_event_dummy;\n+\n+\t/*Initialize client specific shared memory */\n+\tclient_shm = (struct hif_client_shm *)&hif_shm->client[client->id];\n+\tclient_shm->rx_qbase = (unsigned long int)client->rx_qbase;\n+\tclient_shm->rx_qsize = client->rx_qsize;\n+\tclient_shm->tx_qbase = (unsigned long int)client->tx_qbase;\n+\tclient_shm->tx_qsize = client->tx_qsize;\n+\tclient_shm->ctrl = (client->tx_qn << CLIENT_CTRL_TX_Q_CNT_OFST) |\n+\t\t\t\t(client->rx_qn << CLIENT_CTRL_RX_Q_CNT_OFST);\n+\t/* spin_lock_init(&client->rx_lock); */\n+\n+\tfor (i = 0; i < HIF_EVENT_MAX; i++) {\n+\t\tclient->queue_mask[i] = 0;  /*\n+\t\t\t\t\t     * By default all events are\n+\t\t\t\t\t     * unmasked\n+\t\t\t\t\t     */\n+\t}\n+\n+\t/*Indicate to HIF driver*/\n+\thif_lib_indicate_hif(&pfe->hif, REQUEST_CL_REGISTER, client->id, 0);\n+\n+\tpr_debug(\"%s: client: %p, client_id: %d, tx_qsize: %d, rx_qsize: %d\\n\",\n+\t\t __func__, client, client->id, client->tx_qsize,\n+\t\t client->rx_qsize);\n+\n+\tclient->cpu_id = -1;\n+\n+\tpfe->hif_client[client->id] = client;\n+\tspin_unlock_bh(&pfe->hif.lock);\n+\n+\treturn 0;\n+\n+err:\n+\tspin_unlock_bh(&pfe->hif.lock);\n+\thif_lib_client_release_tx_buffers(client);\n+\n+err_tx:\n+\thif_lib_client_release_rx_buffers(client);\n+\n+err_rx:\n+\treturn err;\n+}\n+\n+int hif_lib_client_unregister(struct hif_client_s *client)\n+{\n+\tstruct pfe *pfe = client->pfe;\n+\tu32 client_id = client->id;\n+\n+\tpr_info(\n+\t\t\"%s : client: %p, client_id: %d, txQ_depth: %d, rxQ_depth: %d\\n\"\n+\t\t, __func__, client, client->id, client->tx_qsize,\n+\t\tclient->rx_qsize);\n+\n+\tspin_lock_bh(&pfe->hif.lock);\n+\thif_lib_indicate_hif(&pfe->hif, REQUEST_CL_UNREGISTER, client->id, 0);\n+\n+\thif_lib_client_release_tx_buffers(client);\n+\thif_lib_client_release_rx_buffers(client);\n+\tpfe->hif_client[client_id] = NULL;\n+\tspin_unlock_bh(&pfe->hif.lock);\n+\n+\treturn 0;\n+}\n+\n+int hif_lib_event_handler_start(struct hif_client_s *client, int event,\n+\t\t\t\tint qno)\n+{\n+\tstruct hif_client_rx_queue *queue = &client->rx_q[qno];\n+\tstruct rx_queue_desc *desc = queue->base + queue->read_idx;\n+\n+\tif ((event >= HIF_EVENT_MAX) || (qno >= HIF_CLIENT_QUEUES_MAX)) {\n+\t\tpr_debug(\"%s: Unsupported event : %d  queue number : %d\\n\",\n+\t\t\t __func__, event, qno);\n+\t\treturn -1;\n+\t}\n+\n+\ttest_and_clear_bit(qno, &client->queue_mask[event]);\n+\n+\tswitch (event) {\n+\tcase EVENT_RX_PKT_IND:\n+\t\tif (!(desc->ctrl & CL_DESC_OWN))\n+\t\t\thif_lib_indicate_client(client->id,\n+\t\t\t\t\t\tEVENT_RX_PKT_IND, qno);\n+\t\tbreak;\n+\n+\tcase EVENT_HIGH_RX_WM:\n+\tcase EVENT_TXDONE_IND:\n+\tdefault:\n+\t\tbreak;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+/*\n+ * This function gets one packet from the specified client queue\n+ * It also refill the rx buffer\n+ */\n+void *hif_lib_receive_pkt(struct hif_client_s *client, int qno, int *len, int\n+\t\t\t\t*ofst, unsigned int *rx_ctrl,\n+\t\t\t\tunsigned int *desc_ctrl, void **priv_data)\n+{\n+\tstruct hif_client_rx_queue *queue = &client->rx_q[qno];\n+\tstruct rx_queue_desc *desc;\n+\tvoid *pkt = NULL;\n+\n+\t/*\n+\t * Following lock is to protect rx queue access from,\n+\t * hif_lib_event_handler_start.\n+\t * In general below lock is not required, because hif_lib_xmit_pkt and\n+\t * hif_lib_event_handler_start are called from napi poll and which is\n+\t * not re-entrant. But if some client use in different way this lock is\n+\t * required.\n+\t */\n+\t/*spin_lock_irqsave(&client->rx_lock, flags); */\n+\tdesc = queue->base + queue->read_idx;\n+\tif (!(desc->ctrl & CL_DESC_OWN)) {\n+\t\tpkt = desc->data - pfe_pkt_headroom;\n+\n+\t\t*rx_ctrl = desc->client_ctrl;\n+\t\t*desc_ctrl = desc->ctrl;\n+\n+\t\tif (desc->ctrl & CL_DESC_FIRST) {\n+\t\t\tu16 size = *rx_ctrl >> HIF_CTRL_RX_OFFSET_OFST;\n+\n+\t\t\tif (size) {\n+\t\t\t\tsize += PFE_PARSE_INFO_SIZE;\n+\t\t\t\t*len = CL_DESC_BUF_LEN(desc->ctrl) -\n+\t\t\t\t\t\tPFE_PKT_HEADER_SZ - size;\n+\t\t\t\t*ofst = pfe_pkt_headroom + PFE_PKT_HEADER_SZ\n+\t\t\t\t\t\t\t\t+ size;\n+\t\t\t\t*priv_data = desc->data + PFE_PKT_HEADER_SZ;\n+\t\t\t} else {\n+\t\t\t\t*len = CL_DESC_BUF_LEN(desc->ctrl) -\n+\t\t\t\t       PFE_PKT_HEADER_SZ - PFE_PARSE_INFO_SIZE;\n+\t\t\t\t*ofst = pfe_pkt_headroom\n+\t\t\t\t\t+ PFE_PKT_HEADER_SZ\n+\t\t\t\t\t+ PFE_PARSE_INFO_SIZE;\n+\t\t\t\t*priv_data = NULL;\n+\t\t\t}\n+\n+\t\t} else {\n+\t\t\t*len = CL_DESC_BUF_LEN(desc->ctrl);\n+\t\t\t*ofst = pfe_pkt_headroom;\n+\t\t}\n+\n+\t\t/*\n+\t\t * Needed so we don't free a buffer/page\n+\t\t * twice on module_exit\n+\t\t */\n+\t\tdesc->data = NULL;\n+\n+\t\t/*\n+\t\t * Ensure everything else is written to DDR before\n+\t\t * writing bd->ctrl\n+\t\t */\n+\t\tsmp_wmb();\n+\n+\t\tdesc->ctrl = CL_DESC_BUF_LEN(pfe_pkt_size) | CL_DESC_OWN;\n+\t\tqueue->read_idx = (queue->read_idx + 1) & (queue->size - 1);\n+\t}\n+\n+\t/*spin_unlock_irqrestore(&client->rx_lock, flags); */\n+\treturn pkt;\n+}\n+\n+static inline void hif_hdr_write(struct hif_hdr *pkt_hdr, unsigned int\n+\t\t\t\t\tclient_id, unsigned int qno,\n+\t\t\t\t\tu32 client_ctrl)\n+{\n+\t/* Optimize the write since the destinaton may be non-cacheable */\n+\tif (!((unsigned long)pkt_hdr & 0x3)) {\n+\t\t((u32 *)pkt_hdr)[0] = (client_ctrl << 16) | (qno << 8) |\n+\t\t\t\t\tclient_id;\n+\t} else {\n+\t\t((u16 *)pkt_hdr)[0] = (qno << 8) | (client_id & 0xFF);\n+\t\t((u16 *)pkt_hdr)[1] = (client_ctrl & 0xFFFF);\n+\t}\n+}\n+\n+/*This function puts the given packet in the specific client queue */\n+void __hif_lib_xmit_pkt(struct hif_client_s *client, unsigned int qno, void\n+\t\t\t\t*data, unsigned int len, u32 client_ctrl,\n+\t\t\t\tunsigned int flags, void *client_data)\n+{\n+\tstruct hif_client_tx_queue *queue = &client->tx_q[qno];\n+\tstruct tx_queue_desc *desc = queue->base + queue->write_idx;\n+\n+\t/* First buffer */\n+\tif (flags & HIF_FIRST_BUFFER) {\n+\t\tdata -= sizeof(struct hif_hdr);\n+\t\tlen += sizeof(struct hif_hdr);\n+\n+\t\thif_hdr_write(data, client->id, qno, client_ctrl);\n+\t}\n+\n+\tdesc->data = client_data;\n+\tdesc->ctrl = CL_DESC_OWN | CL_DESC_FLAGS(flags);\n+\n+\t__hif_xmit_pkt(&pfe->hif, client->id, qno, data, len, flags);\n+\n+\tqueue->write_idx = (queue->write_idx + 1) & (queue->size - 1);\n+\tqueue->tx_pending++;\n+\tqueue->jiffies_last_packet = jiffies;\n+}\n+\n+void *hif_lib_tx_get_next_complete(struct hif_client_s *client, int qno,\n+\t\t\t\t   unsigned int *flags, int count)\n+{\n+\tstruct hif_client_tx_queue *queue = &client->tx_q[qno];\n+\tstruct tx_queue_desc *desc = queue->base + queue->read_idx;\n+\n+\tpr_debug(\"%s: qno : %d rd_indx: %d pending:%d\\n\", __func__, qno,\n+\t\t queue->read_idx, queue->tx_pending);\n+\n+\tif (!queue->tx_pending)\n+\t\treturn NULL;\n+\n+\tif (queue->nocpy_flag && !queue->done_tmu_tx_pkts) {\n+\t\tu32 tmu_tx_pkts = be32_to_cpu(pe_dmem_read(TMU0_ID +\n+\t\t\tclient->id, TMU_DM_TX_TRANS, 4));\n+\n+\t\tif (queue->prev_tmu_tx_pkts > tmu_tx_pkts)\n+\t\t\tqueue->done_tmu_tx_pkts = UINT_MAX -\n+\t\t\t\tqueue->prev_tmu_tx_pkts + tmu_tx_pkts;\n+\t\telse\n+\t\t\tqueue->done_tmu_tx_pkts = tmu_tx_pkts -\n+\t\t\t\t\t\tqueue->prev_tmu_tx_pkts;\n+\n+\t\tqueue->prev_tmu_tx_pkts  = tmu_tx_pkts;\n+\n+\t\tif (!queue->done_tmu_tx_pkts)\n+\t\t\treturn NULL;\n+\t}\n+\n+\tif (desc->ctrl & CL_DESC_OWN)\n+\t\treturn NULL;\n+\n+\tqueue->read_idx = (queue->read_idx + 1) & (queue->size - 1);\n+\tqueue->tx_pending--;\n+\n+\t*flags = CL_DESC_GET_FLAGS(desc->ctrl);\n+\n+\tif (queue->done_tmu_tx_pkts && (*flags & HIF_LAST_BUFFER))\n+\t\tqueue->done_tmu_tx_pkts--;\n+\n+\treturn desc->data;\n+}\n+\n+static void hif_lib_tmu_credit_init(struct pfe *pfe)\n+{\n+\tint i, q;\n+\n+\tfor (i = 0; i < NUM_GEMAC_SUPPORT; i++)\n+\t\tfor (q = 0; q < emac_txq_cnt; q++) {\n+\t\t\tpfe->tmu_credit.tx_credit_max[i][q] = (q == 0) ?\n+\t\t\t\t\tDEFAULT_Q0_QDEPTH : DEFAULT_MAX_QDEPTH;\n+\t\t\tpfe->tmu_credit.tx_credit[i][q] =\n+\t\t\t\t\tpfe->tmu_credit.tx_credit_max[i][q];\n+\t\t}\n+}\n+\n+/* __hif_lib_update_credit\n+ *\n+ * @param[in] client\thif client context\n+ * @param[in] queue\tqueue number in match with TMU\n+ */\n+void __hif_lib_update_credit(struct hif_client_s *client, unsigned int queue)\n+{\n+\tunsigned int tmu_tx_packets, tmp;\n+\n+\tif (tx_qos) {\n+\t\ttmu_tx_packets = be32_to_cpu(pe_dmem_read(TMU0_ID +\n+\t\t\tclient->id, (TMU_DM_TX_TRANS + (queue * 4)), 4));\n+\n+\t\t/* tx_packets counter overflowed */\n+\t\tif (tmu_tx_packets >\n+\t\t    pfe->tmu_credit.tx_packets[client->id][queue]) {\n+\t\t\ttmp = UINT_MAX - tmu_tx_packets +\n+\t\t\tpfe->tmu_credit.tx_packets[client->id][queue];\n+\n+\t\t\tpfe->tmu_credit.tx_credit[client->id][queue] =\n+\t\t\tpfe->tmu_credit.tx_credit_max[client->id][queue] - tmp;\n+\t\t} else {\n+\t\t/* TMU tx <= pfe_eth tx, normal case or both OF since\n+\t\t * last time\n+\t\t */\n+\t\t\tpfe->tmu_credit.tx_credit[client->id][queue] =\n+\t\t\tpfe->tmu_credit.tx_credit_max[client->id][queue] -\n+\t\t\t(pfe->tmu_credit.tx_packets[client->id][queue] -\n+\t\t\ttmu_tx_packets);\n+\t\t}\n+\t}\n+}\n+\n+int pfe_hif_lib_init(struct pfe *pfe)\n+{\n+\tint rc;\n+\n+\tpr_info(\"%s\\n\", __func__);\n+\n+\tif (lro_mode) {\n+\t\tpage_mode = 1;\n+\t\tpfe_pkt_size = min(PAGE_SIZE, MAX_PFE_PKT_SIZE);\n+\t\tpfe_pkt_headroom = 0;\n+\t} else {\n+\t\tpage_mode = 0;\n+\t\tpfe_pkt_size = PFE_PKT_SIZE;\n+\t\tpfe_pkt_headroom = PFE_PKT_HEADROOM;\n+\t}\n+\n+\tif (tx_qos)\n+\t\temac_txq_cnt = EMAC_TXQ_CNT / 2;\n+\telse\n+\t\temac_txq_cnt = EMAC_TXQ_CNT;\n+\n+\thif_lib_tmu_credit_init(pfe);\n+\tpfe->hif.shm = &ghif_shm;\n+\trc = pfe_hif_shm_init(pfe->hif.shm);\n+\n+\treturn rc;\n+}\n+\n+void pfe_hif_lib_exit(struct pfe *pfe)\n+{\n+\tpr_info(\"%s\\n\", __func__);\n+\n+\tpfe_hif_shm_clean(pfe->hif.shm);\n+}\n--- /dev/null\n+++ b/drivers/staging/fsl_ppfe/pfe_hif_lib.h\n@@ -0,0 +1,229 @@\n+/* SPDX-License-Identifier: GPL-2.0+ */\n+/*\n+ * Copyright 2015-2016 Freescale Semiconductor, Inc.\n+ * Copyright 2017 NXP\n+ */\n+\n+#ifndef _PFE_HIF_LIB_H_\n+#define _PFE_HIF_LIB_H_\n+\n+#include \"pfe_hif.h\"\n+\n+#define HIF_CL_REQ_TIMEOUT\t10\n+#define GFP_DMA_PFE 0\n+#define PFE_PARSE_INFO_SIZE\t16\n+\n+enum {\n+\tREQUEST_CL_REGISTER = 0,\n+\tREQUEST_CL_UNREGISTER,\n+\tHIF_REQUEST_MAX\n+};\n+\n+enum {\n+\t/* Event to indicate that client rx queue is reached water mark level */\n+\tEVENT_HIGH_RX_WM = 0,\n+\t/* Event to indicate that, packet received for client */\n+\tEVENT_RX_PKT_IND,\n+\t/* Event to indicate that, packet tx done for client */\n+\tEVENT_TXDONE_IND,\n+\tHIF_EVENT_MAX\n+};\n+\n+/*structure to store client queue info */\n+\n+/*structure to store client queue info */\n+struct hif_client_rx_queue {\n+\tstruct rx_queue_desc *base;\n+\tu32\tsize;\n+\tu32\tread_idx;\n+\tu32\twrite_idx;\n+};\n+\n+struct hif_client_tx_queue {\n+\tstruct tx_queue_desc *base;\n+\tu32\tsize;\n+\tu32\tread_idx;\n+\tu32\twrite_idx;\n+\tu32\ttx_pending;\n+\tunsigned long jiffies_last_packet;\n+\tu32\tnocpy_flag;\n+\tu32\tprev_tmu_tx_pkts;\n+\tu32\tdone_tmu_tx_pkts;\n+};\n+\n+struct hif_client_s {\n+\tint\tid;\n+\tint\ttx_qn;\n+\tint\trx_qn;\n+\tvoid\t*rx_qbase;\n+\tvoid\t*tx_qbase;\n+\tint\ttx_qsize;\n+\tint\trx_qsize;\n+\tint\tcpu_id;\n+\tstruct hif_client_tx_queue tx_q[HIF_CLIENT_QUEUES_MAX];\n+\tstruct hif_client_rx_queue rx_q[HIF_CLIENT_QUEUES_MAX];\n+\tint (*event_handler)(void *priv, int event, int data);\n+\tunsigned long queue_mask[HIF_EVENT_MAX];\n+\tstruct pfe *pfe;\n+\tvoid *priv;\n+};\n+\n+/*\n+ * Client specific shared memory\n+ * It contains number of Rx/Tx queues, base addresses and queue sizes\n+ */\n+struct hif_client_shm {\n+\tu32 ctrl; /*0-7: number of Rx queues, 8-15: number of tx queues */\n+\tunsigned long rx_qbase; /*Rx queue base address */\n+\tu32 rx_qsize; /*each Rx queue size, all Rx queues are of same size */\n+\tunsigned long tx_qbase; /* Tx queue base address */\n+\tu32 tx_qsize; /*each Tx queue size, all Tx queues are of same size */\n+};\n+\n+/*Client shared memory ctrl bit description */\n+#define CLIENT_CTRL_RX_Q_CNT_OFST\t0\n+#define CLIENT_CTRL_TX_Q_CNT_OFST\t8\n+#define CLIENT_CTRL_RX_Q_CNT(ctrl)\t(((ctrl) >> CLIENT_CTRL_RX_Q_CNT_OFST) \\\n+\t\t\t\t\t\t& 0xFF)\n+#define CLIENT_CTRL_TX_Q_CNT(ctrl)\t(((ctrl) >> CLIENT_CTRL_TX_Q_CNT_OFST) \\\n+\t\t\t\t\t\t& 0xFF)\n+\n+/*\n+ * Shared memory used to communicate between HIF driver and host/client drivers\n+ * Before starting the hif driver rx_buf_pool ans rx_buf_pool_cnt should be\n+ * initialized with host buffers and buffers count in the pool.\n+ * rx_buf_pool_cnt should be >= HIF_RX_DESC_NT.\n+ *\n+ */\n+struct hif_shm {\n+\tu32 rx_buf_pool_cnt; /*Number of rx buffers available*/\n+\t/*Rx buffers required to initialize HIF rx descriptors */\n+\tvoid *rx_buf_pool[HIF_RX_DESC_NT];\n+\tunsigned long g_client_status[2]; /*Global client status bit mask */\n+\t/* Client specific shared memory */\n+\tstruct hif_client_shm client[HIF_CLIENTS_MAX];\n+};\n+\n+#define CL_DESC_OWN\tBIT(31)\n+/* This sets owner ship to HIF driver */\n+#define CL_DESC_LAST\tBIT(30)\n+/* This indicates last packet for multi buffers handling */\n+#define CL_DESC_FIRST\tBIT(29)\n+/* This indicates first packet for multi buffers handling */\n+\n+#define CL_DESC_BUF_LEN(x)\t\t((x) & 0xFFFF)\n+#define CL_DESC_FLAGS(x)\t\t(((x) & 0xF) << 16)\n+#define CL_DESC_GET_FLAGS(x)\t\t(((x) >> 16) & 0xF)\n+\n+struct rx_queue_desc {\n+\tvoid *data;\n+\tu32\tctrl; /*0-15bit len, 16-20bit flags, 31bit owner*/\n+\tu32\tclient_ctrl;\n+};\n+\n+struct tx_queue_desc {\n+\tvoid *data;\n+\tu32\tctrl; /*0-15bit len, 16-20bit flags, 31bit owner*/\n+};\n+\n+/* HIF Rx is not working properly for 2-byte aligned buffers and\n+ * ip_header should be 4byte aligned for better iperformance.\n+ * \"ip_header = 64 + 6(hif_header) + 14 (MAC Header)\" will be 4byte aligned.\n+ */\n+#define PFE_PKT_HEADER_SZ\tsizeof(struct hif_hdr)\n+/* must be big enough for headroom, pkt size and skb shared info */\n+#define PFE_BUF_SIZE\t\t2048\n+#define PFE_PKT_HEADROOM\t128\n+\n+#define SKB_SHARED_INFO_SIZE   SKB_DATA_ALIGN(sizeof(struct skb_shared_info))\n+#define PFE_PKT_SIZE\t\t(PFE_BUF_SIZE - PFE_PKT_HEADROOM \\\n+\t\t\t\t - SKB_SHARED_INFO_SIZE)\n+#define MAX_L2_HDR_SIZE\t\t14\t/* Not correct for VLAN/PPPoE */\n+#define MAX_L3_HDR_SIZE\t\t20\t/* Not correct for IPv6 */\n+#define MAX_L4_HDR_SIZE\t\t60\t/* TCP with maximum options */\n+#define MAX_HDR_SIZE\t\t(MAX_L2_HDR_SIZE + MAX_L3_HDR_SIZE \\\n+\t\t\t\t + MAX_L4_HDR_SIZE)\n+/* Used in page mode to clamp packet size to the maximum supported by the hif\n+ *hw interface (<16KiB)\n+ */\n+#define MAX_PFE_PKT_SIZE\t16380UL\n+\n+extern unsigned int pfe_pkt_size;\n+extern unsigned int pfe_pkt_headroom;\n+extern unsigned int page_mode;\n+extern unsigned int lro_mode;\n+extern unsigned int tx_qos;\n+extern unsigned int emac_txq_cnt;\n+\n+int pfe_hif_lib_init(struct pfe *pfe);\n+void pfe_hif_lib_exit(struct pfe *pfe);\n+int hif_lib_client_register(struct hif_client_s *client);\n+int hif_lib_client_unregister(struct  hif_client_s *client);\n+void __hif_lib_xmit_pkt(struct hif_client_s *client, unsigned int qno, void\n+\t\t\t\t*data, unsigned int len, u32 client_ctrl,\n+\t\t\t\tunsigned int flags, void *client_data);\n+int hif_lib_xmit_pkt(struct hif_client_s *client, unsigned int qno, void *data,\n+\t\t     unsigned int len, u32 client_ctrl, void *client_data);\n+void hif_lib_indicate_client(int cl_id, int event, int data);\n+int hif_lib_event_handler_start(struct hif_client_s *client, int event, int\n+\t\t\t\t\tdata);\n+int hif_lib_tmu_queue_start(struct hif_client_s *client, int qno);\n+int hif_lib_tmu_queue_stop(struct hif_client_s *client, int qno);\n+void *hif_lib_tx_get_next_complete(struct hif_client_s *client, int qno,\n+\t\t\t\t   unsigned int *flags, int count);\n+void *hif_lib_receive_pkt(struct hif_client_s *client, int qno, int *len, int\n+\t\t\t\t*ofst, unsigned int *rx_ctrl,\n+\t\t\t\tunsigned int *desc_ctrl, void **priv_data);\n+void __hif_lib_update_credit(struct hif_client_s *client, unsigned int queue);\n+void hif_lib_set_rx_cpu_affinity(struct hif_client_s *client, int cpu_id);\n+void hif_lib_set_tx_queue_nocpy(struct hif_client_s *client, int qno, int\n+\t\t\t\t\tenable);\n+static inline int hif_lib_tx_avail(struct hif_client_s *client, unsigned int\n+\t\t\t\t\tqno)\n+{\n+\tstruct hif_client_tx_queue *queue = &client->tx_q[qno];\n+\n+\treturn (queue->size - queue->tx_pending);\n+}\n+\n+static inline int hif_lib_get_tx_wr_index(struct hif_client_s *client, unsigned\n+\t\t\t\t\t\tint qno)\n+{\n+\tstruct hif_client_tx_queue *queue = &client->tx_q[qno];\n+\n+\treturn queue->write_idx;\n+}\n+\n+static inline int hif_lib_tx_pending(struct hif_client_s *client, unsigned int\n+\t\t\t\t\tqno)\n+{\n+\tstruct hif_client_tx_queue *queue = &client->tx_q[qno];\n+\n+\treturn queue->tx_pending;\n+}\n+\n+#define hif_lib_tx_credit_avail(pfe, id, qno) \\\n+\t\t\t\t((pfe)->tmu_credit.tx_credit[id][qno])\n+\n+#define hif_lib_tx_credit_max(pfe, id, qno) \\\n+\t\t\t\t((pfe)->tmu_credit.tx_credit_max[id][qno])\n+\n+/*\n+ * Test comment\n+ */\n+#define hif_lib_tx_credit_use(pfe, id, qno, credit)\t\t\t\\\n+\t({ typeof(pfe) pfe_ = pfe;\t\t\t\t\t\\\n+\t\ttypeof(id) id_ = id;\t\t\t\t\t\\\n+\t\ttypeof(qno) qno_ = qno;\t\t\t\t\t\\\n+\t\ttypeof(credit) credit_ = credit;\t\t\t\\\n+\t\tdo {\t\t\t\t\t\t\t\\\n+\t\t\tif (tx_qos) {\t\t\t\t\t\\\n+\t\t\t\t(pfe_)->tmu_credit.tx_credit[id_][qno_]\\\n+\t\t\t\t\t -= credit_;\t\t\t\\\n+\t\t\t\t(pfe_)->tmu_credit.tx_packets[id_][qno_]\\\n+\t\t\t\t\t+= credit_;\t\t\t\\\n+\t\t\t}\t\t\t\t\t\t\\\n+\t\t} while (0);\t\t\t\t\t\t\\\n+\t})\n+\n+#endif /* _PFE_HIF_LIB_H_ */\n--- /dev/null\n+++ b/drivers/staging/fsl_ppfe/pfe_hw.c\n@@ -0,0 +1,164 @@\n+// SPDX-License-Identifier: GPL-2.0+\n+/*\n+ * Copyright 2015-2016 Freescale Semiconductor, Inc.\n+ * Copyright 2017 NXP\n+ */\n+\n+#include \"pfe_mod.h\"\n+#include \"pfe_hw.h\"\n+\n+/* Functions to handle most of pfe hw register initialization */\n+int pfe_hw_init(struct pfe *pfe, int resume)\n+{\n+\tstruct class_cfg class_cfg = {\n+\t\t.pe_sys_clk_ratio = PE_SYS_CLK_RATIO,\n+\t\t.route_table_baseaddr = pfe->ddr_phys_baseaddr +\n+\t\t\t\t\tROUTE_TABLE_BASEADDR,\n+\t\t.route_table_hash_bits = ROUTE_TABLE_HASH_BITS,\n+\t};\n+\n+\tstruct tmu_cfg tmu_cfg = {\n+\t\t.pe_sys_clk_ratio = PE_SYS_CLK_RATIO,\n+\t\t.llm_base_addr = pfe->ddr_phys_baseaddr + TMU_LLM_BASEADDR,\n+\t\t.llm_queue_len = TMU_LLM_QUEUE_LEN,\n+\t};\n+\n+#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)\n+\tstruct util_cfg util_cfg = {\n+\t\t.pe_sys_clk_ratio = PE_SYS_CLK_RATIO,\n+\t};\n+#endif\n+\n+\tstruct BMU_CFG bmu1_cfg = {\n+\t\t.baseaddr = CBUS_VIRT_TO_PFE(LMEM_BASE_ADDR +\n+\t\t\t\t\t\tBMU1_LMEM_BASEADDR),\n+\t\t.count = BMU1_BUF_COUNT,\n+\t\t.size = BMU1_BUF_SIZE,\n+\t\t.low_watermark = 10,\n+\t\t.high_watermark = 15,\n+\t};\n+\n+\tstruct BMU_CFG bmu2_cfg = {\n+\t\t.baseaddr = DDR_PHYS_TO_PFE(pfe->ddr_phys_baseaddr +\n+\t\t\t\t\t\tBMU2_DDR_BASEADDR),\n+\t\t.count = BMU2_BUF_COUNT,\n+\t\t.size = BMU2_BUF_SIZE,\n+\t\t.low_watermark = 250,\n+\t\t.high_watermark = 253,\n+\t};\n+\n+\tstruct gpi_cfg egpi1_cfg = {\n+\t\t.lmem_rtry_cnt = EGPI1_LMEM_RTRY_CNT,\n+\t\t.tmlf_txthres = EGPI1_TMLF_TXTHRES,\n+\t\t.aseq_len = EGPI1_ASEQ_LEN,\n+\t\t.mtip_pause_reg = CBUS_VIRT_TO_PFE(EMAC1_BASE_ADDR +\n+\t\t\t\t\t\tEMAC_TCNTRL_REG),\n+\t};\n+\n+\tstruct gpi_cfg egpi2_cfg = {\n+\t\t.lmem_rtry_cnt = EGPI2_LMEM_RTRY_CNT,\n+\t\t.tmlf_txthres = EGPI2_TMLF_TXTHRES,\n+\t\t.aseq_len = EGPI2_ASEQ_LEN,\n+\t\t.mtip_pause_reg = CBUS_VIRT_TO_PFE(EMAC2_BASE_ADDR +\n+\t\t\t\t\t\tEMAC_TCNTRL_REG),\n+\t};\n+\n+\tstruct gpi_cfg hgpi_cfg = {\n+\t\t.lmem_rtry_cnt = HGPI_LMEM_RTRY_CNT,\n+\t\t.tmlf_txthres = HGPI_TMLF_TXTHRES,\n+\t\t.aseq_len = HGPI_ASEQ_LEN,\n+\t\t.mtip_pause_reg = 0,\n+\t};\n+\n+\tpr_info(\"%s\\n\", __func__);\n+\n+#if !defined(LS1012A_PFE_RESET_WA)\n+\t/* LS1012A needs this to make PE work correctly */\n+\twritel(0x3,     CLASS_PE_SYS_CLK_RATIO);\n+\twritel(0x3,     TMU_PE_SYS_CLK_RATIO);\n+\twritel(0x3,     UTIL_PE_SYS_CLK_RATIO);\n+\tusleep_range(10, 20);\n+#endif\n+\n+\tpr_info(\"CLASS version: %x\\n\", readl(CLASS_VERSION));\n+\tpr_info(\"TMU version: %x\\n\", readl(TMU_VERSION));\n+\n+\tpr_info(\"BMU1 version: %x\\n\", readl(BMU1_BASE_ADDR +\n+\t\tBMU_VERSION));\n+\tpr_info(\"BMU2 version: %x\\n\", readl(BMU2_BASE_ADDR +\n+\t\tBMU_VERSION));\n+\n+\tpr_info(\"EGPI1 version: %x\\n\", readl(EGPI1_BASE_ADDR +\n+\t\tGPI_VERSION));\n+\tpr_info(\"EGPI2 version: %x\\n\", readl(EGPI2_BASE_ADDR +\n+\t\tGPI_VERSION));\n+\tpr_info(\"HGPI version: %x\\n\", readl(HGPI_BASE_ADDR +\n+\t\tGPI_VERSION));\n+\n+\tpr_info(\"HIF version: %x\\n\", readl(HIF_VERSION));\n+\tpr_info(\"HIF NOPCY version: %x\\n\", readl(HIF_NOCPY_VERSION));\n+\n+#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)\n+\tpr_info(\"UTIL version: %x\\n\", readl(UTIL_VERSION));\n+#endif\n+\twhile (!(readl(TMU_CTRL) & ECC_MEM_INIT_DONE))\n+\t\t;\n+\n+\thif_rx_disable();\n+\thif_tx_disable();\n+\n+\tbmu_init(BMU1_BASE_ADDR, &bmu1_cfg);\n+\n+\tpr_info(\"bmu_init(1) done\\n\");\n+\n+\tbmu_init(BMU2_BASE_ADDR, &bmu2_cfg);\n+\n+\tpr_info(\"bmu_init(2) done\\n\");\n+\n+\tclass_cfg.resume = resume ? 1 : 0;\n+\n+\tclass_init(&class_cfg);\n+\n+\tpr_info(\"class_init() done\\n\");\n+\n+\ttmu_init(&tmu_cfg);\n+\n+\tpr_info(\"tmu_init() done\\n\");\n+#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)\n+\tutil_init(&util_cfg);\n+\n+\tpr_info(\"util_init() done\\n\");\n+#endif\n+\tgpi_init(EGPI1_BASE_ADDR, &egpi1_cfg);\n+\n+\tpr_info(\"gpi_init(1) done\\n\");\n+\n+\tgpi_init(EGPI2_BASE_ADDR, &egpi2_cfg);\n+\n+\tpr_info(\"gpi_init(2) done\\n\");\n+\n+\tgpi_init(HGPI_BASE_ADDR, &hgpi_cfg);\n+\n+\tpr_info(\"gpi_init(hif) done\\n\");\n+\n+\tbmu_enable(BMU1_BASE_ADDR);\n+\n+\tpr_info(\"bmu_enable(1) done\\n\");\n+\n+\tbmu_enable(BMU2_BASE_ADDR);\n+\n+\tpr_info(\"bmu_enable(2) done\\n\");\n+\n+\treturn 0;\n+}\n+\n+void pfe_hw_exit(struct pfe *pfe)\n+{\n+\tpr_info(\"%s\\n\", __func__);\n+\n+\tbmu_disable(BMU1_BASE_ADDR);\n+\tbmu_reset(BMU1_BASE_ADDR);\n+\n+\tbmu_disable(BMU2_BASE_ADDR);\n+\tbmu_reset(BMU2_BASE_ADDR);\n+}\n--- /dev/null\n+++ b/drivers/staging/fsl_ppfe/pfe_hw.h\n@@ -0,0 +1,15 @@\n+/* SPDX-License-Identifier: GPL-2.0+ */\n+/*\n+ * Copyright 2015-2016 Freescale Semiconductor, Inc.\n+ * Copyright 2017 NXP\n+ */\n+\n+#ifndef _PFE_HW_H_\n+#define _PFE_HW_H_\n+\n+#define PE_SYS_CLK_RATIO\t1\t/* SYS/AXI = 250MHz, HFE = 500MHz */\n+\n+int pfe_hw_init(struct pfe *pfe, int resume);\n+void pfe_hw_exit(struct pfe *pfe);\n+\n+#endif /* _PFE_HW_H_ */\n--- /dev/null\n+++ b/drivers/staging/fsl_ppfe/pfe_ls1012a_platform.c\n@@ -0,0 +1,383 @@\n+// SPDX-License-Identifier: GPL-2.0+\n+/*\n+ * Copyright 2015-2016 Freescale Semiconductor, Inc.\n+ * Copyright 2017 NXP\n+ */\n+\n+#include <linux/module.h>\n+#include <linux/device.h>\n+#include <linux/of.h>\n+#include <linux/of_net.h>\n+#include <linux/of_address.h>\n+#include <linux/of_mdio.h>\n+#include <linux/platform_device.h>\n+#include <linux/slab.h>\n+#include <linux/clk.h>\n+#include <linux/mfd/syscon.h>\n+#include <linux/regmap.h>\n+\n+#include \"pfe_mod.h\"\n+\n+extern bool pfe_use_old_dts_phy;\n+struct ls1012a_pfe_platform_data pfe_platform_data;\n+\n+static int pfe_get_gemac_if_properties(struct device_node *gem,\n+\t\t\t\t       int port,\n+\t\t\t\t       struct ls1012a_pfe_platform_data\t*pdata)\n+{\n+\tstruct device_node *phy_node = NULL;\n+\tint size;\n+\tint phy_id = 0;\n+\tconst u32 *addr;\n+\tint err;\n+\n+\taddr = of_get_property(gem, \"reg\", &size);\n+\tif (addr)\n+\t\tport = be32_to_cpup(addr);\n+\telse\n+\t\tgoto err;\n+\n+\tpdata->ls1012a_eth_pdata[port].gem_id = port;\n+\n+\tof_get_mac_address(gem, pdata->ls1012a_eth_pdata[port].mac_addr);\n+\n+\tphy_node = of_parse_phandle(gem, \"phy-handle\", 0);\n+\tpdata->ls1012a_eth_pdata[port].phy_node = phy_node;\n+\tif (phy_node) {\n+\t\tpfe_use_old_dts_phy = false;\n+\t\tgoto process_phynode;\n+\t} else if (of_phy_is_fixed_link(gem)) {\n+\t\tpfe_use_old_dts_phy = false;\n+\t\tif (of_phy_register_fixed_link(gem) < 0) {\n+\t\t\tpr_err(\"broken fixed-link specification\\n\");\n+\t\t\tgoto err;\n+\t\t}\n+\t\tphy_node = of_node_get(gem);\n+\t\tpdata->ls1012a_eth_pdata[port].phy_node = phy_node;\n+\t} else if (of_get_property(gem, \"fsl,pfe-phy-if-flags\", &size)) {\n+\t\tpfe_use_old_dts_phy = true;\n+\t\t/* Use old dts properties for phy handling */\n+\t\taddr = of_get_property(gem, \"fsl,pfe-phy-if-flags\", &size);\n+\t\tpdata->ls1012a_eth_pdata[port].phy_flags = be32_to_cpup(addr);\n+\n+\t\taddr = of_get_property(gem, \"fsl,gemac-phy-id\", &size);\n+\t\tif (!addr) {\n+\t\t\tpr_err(\"%s:%d Invalid gemac-phy-id....\\n\", __func__,\n+\t\t\t       __LINE__);\n+\t\t} else {\n+\t\t\tphy_id = be32_to_cpup(addr);\n+\t\t\tpdata->ls1012a_eth_pdata[port].phy_id = phy_id;\n+\t\t\tpdata->ls1012a_mdio_pdata[0].phy_mask &= ~(1 << phy_id);\n+\t\t}\n+\n+\t\t/* If PHY is enabled, read mdio properties */\n+\t\tif (pdata->ls1012a_eth_pdata[port].phy_flags & GEMAC_NO_PHY)\n+\t\t\tgoto done;\n+\n+\t} else {\n+\t\tpr_info(\"%s: No PHY or fixed-link\\n\", __func__);\n+\t\treturn 0;\n+\t}\n+\n+process_phynode:\n+\terr = of_get_phy_mode(gem, &pdata->ls1012a_eth_pdata[port].mii_config);\n+\tif (err)\n+\t\tpr_err(\"%s:%d Incorrect Phy mode....\\n\", __func__,\n+\t\t       __LINE__);\n+\n+\taddr = of_get_property(gem, \"fsl,mdio-mux-val\", &size);\n+\tif (!addr) {\n+\t\tpr_err(\"%s: Invalid mdio-mux-val....\\n\", __func__);\n+\t} else {\n+\t\tphy_id = be32_to_cpup(addr);\n+\t\tpdata->ls1012a_eth_pdata[port].mdio_muxval = phy_id;\n+\t}\n+\n+\tif (pdata->ls1012a_eth_pdata[port].phy_id < 32)\n+\t\tpfe->mdio_muxval[pdata->ls1012a_eth_pdata[port].phy_id] =\n+\t\t\t pdata->ls1012a_eth_pdata[port].mdio_muxval;\n+\n+\n+\tpdata->ls1012a_mdio_pdata[port].irq[0] = PHY_POLL;\n+\n+done:\n+\treturn 0;\n+\n+err:\n+\treturn -1;\n+}\n+\n+/*\n+ *\n+ * pfe_platform_probe -\n+ *\n+ *\n+ */\n+static int pfe_platform_probe(struct platform_device *pdev)\n+{\n+\tstruct resource res;\n+\tint ii = 0, rc, interface_count = 0, size = 0;\n+\tconst u32 *prop;\n+\tstruct device_node *np, *gem = NULL;\n+\tstruct clk *pfe_clk;\n+\n+\tnp = pdev->dev.of_node;\n+\n+\tif (!np) {\n+\t\tpr_err(\"Invalid device node\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tpfe = kzalloc(sizeof(*pfe), GFP_KERNEL);\n+\tif (!pfe) {\n+\t\trc = -ENOMEM;\n+\t\tgoto err_alloc;\n+\t}\n+\n+\tplatform_set_drvdata(pdev, pfe);\n+\n+\tif (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32))) {\n+\t\trc = -ENOMEM;\n+\t\tpr_err(\"unable to configure DMA mask.\\n\");\n+\t\tgoto err_ddr;\n+\t}\n+\n+\tif (of_address_to_resource(np, 1, &res)) {\n+\t\trc = -ENOMEM;\n+\t\tpr_err(\"failed to get ddr resource\\n\");\n+\t\tgoto err_ddr;\n+\t}\n+\n+\tpfe->ddr_phys_baseaddr = res.start;\n+\tpfe->ddr_size = resource_size(&res);\n+\n+\tpfe->ddr_baseaddr = memremap(res.start, resource_size(&res),\n+\t\t\t\t     MEMREMAP_WB);\n+\tif (!pfe->ddr_baseaddr) {\n+\t\tpr_err(\"memremap() ddr failed\\n\");\n+\t\trc = -ENOMEM;\n+\t\tgoto err_ddr;\n+\t}\n+\n+\tpfe->scfg =\n+\t\tsyscon_regmap_lookup_by_phandle(pdev->dev.of_node,\n+\t\t\t\t\t\t\"fsl,pfe-scfg\");\n+\tif (IS_ERR(pfe->scfg)) {\n+\t\tdev_err(&pdev->dev, \"No syscfg phandle specified\\n\");\n+\t\treturn PTR_ERR(pfe->scfg);\n+\t}\n+\n+\tpfe->cbus_baseaddr = of_iomap(np, 0);\n+\tif (!pfe->cbus_baseaddr) {\n+\t\trc = -ENOMEM;\n+\t\tpr_err(\"failed to get axi resource\\n\");\n+\t\tgoto err_axi;\n+\t}\n+\n+\tpfe->hif_irq = platform_get_irq(pdev, 0);\n+\tif (pfe->hif_irq < 0) {\n+\t\tpr_err(\"platform_get_irq for hif failed\\n\");\n+\t\trc = pfe->hif_irq;\n+\t\tgoto err_hif_irq;\n+\t}\n+\n+\tpfe->wol_irq = platform_get_irq(pdev, 2);\n+\tif (pfe->wol_irq < 0) {\n+\t\tpr_err(\"platform_get_irq for WoL failed\\n\");\n+\t\trc = pfe->wol_irq;\n+\t\tgoto err_hif_irq;\n+\t}\n+\n+\t/* Read interface count */\n+\tprop = of_get_property(np, \"fsl,pfe-num-interfaces\", &size);\n+\tif (!prop) {\n+\t\tpr_err(\"Failed to read number of interfaces\\n\");\n+\t\trc = -ENXIO;\n+\t\tgoto err_prop;\n+\t}\n+\n+\tinterface_count = be32_to_cpup(prop);\n+\tif (interface_count <= 0) {\n+\t\tpr_err(\"No ethernet interface count : %d\\n\",\n+\t\t       interface_count);\n+\t\trc = -ENXIO;\n+\t\tgoto err_prop;\n+\t}\n+\n+\tpfe_platform_data.ls1012a_mdio_pdata[0].phy_mask = 0xffffffff;\n+\n+\twhile ((gem = of_get_next_child(np, gem))) {\n+\t\tif (of_find_property(gem, \"reg\", &size)) {\n+\t\t\tpfe_get_gemac_if_properties(gem, ii,\n+\t\t\t\t\t\t&pfe_platform_data);\n+\t\t\tii++;\n+\t\t}\n+\t}\n+\n+\tif (interface_count != ii)\n+\t\tpr_info(\"missing some of gemac interface properties.\\n\");\n+\n+\tpfe->dev = &pdev->dev;\n+\n+\tpfe->dev->platform_data = &pfe_platform_data;\n+\n+\t/* declare WoL capabilities */\n+\tdevice_init_wakeup(&pdev->dev, true);\n+\n+\t/* find the clocks */\n+\tpfe_clk = devm_clk_get(pfe->dev, \"pfe\");\n+\tif (IS_ERR(pfe_clk))\n+\t\treturn PTR_ERR(pfe_clk);\n+\n+\t/* PFE clock is (platform clock / 2) */\n+\t/* save sys_clk value as KHz */\n+\tpfe->ctrl.sys_clk = clk_get_rate(pfe_clk) / (2 * 1000);\n+\n+\trc = pfe_probe(pfe);\n+\tif (rc < 0)\n+\t\tgoto err_probe;\n+\n+\treturn 0;\n+\n+err_probe:\n+err_prop:\n+err_hif_irq:\n+\tiounmap(pfe->cbus_baseaddr);\n+\n+err_axi:\n+\tmemunmap(pfe->ddr_baseaddr);\n+\n+err_ddr:\n+\tplatform_set_drvdata(pdev, NULL);\n+\n+\tkfree(pfe);\n+\n+err_alloc:\n+\treturn rc;\n+}\n+\n+/*\n+ * pfe_platform_remove -\n+ */\n+static int pfe_platform_remove(struct platform_device *pdev)\n+{\n+\tstruct pfe *pfe = platform_get_drvdata(pdev);\n+\tint rc;\n+\n+\tpr_info(\"%s\\n\", __func__);\n+\n+\trc = pfe_remove(pfe);\n+\n+\tiounmap(pfe->cbus_baseaddr);\n+\n+\tmemunmap(pfe->ddr_baseaddr);\n+\n+\tplatform_set_drvdata(pdev, NULL);\n+\n+\tkfree(pfe);\n+\n+\treturn rc;\n+}\n+\n+#ifdef CONFIG_PM\n+#ifdef CONFIG_PM_SLEEP\n+int pfe_platform_suspend(struct device *dev)\n+{\n+\tstruct pfe *pfe = platform_get_drvdata(to_platform_device(dev));\n+\tstruct net_device *netdev;\n+\tint i;\n+\n+\tpfe->wake = 0;\n+\n+\tfor (i = 0; i < (NUM_GEMAC_SUPPORT); i++) {\n+\t\tnetdev = pfe->eth.eth_priv[i]->ndev;\n+\n+\t\tnetif_device_detach(netdev);\n+\n+\t\tif (netif_running(netdev))\n+\t\t\tif (pfe_eth_suspend(netdev))\n+\t\t\t\tpfe->wake = 1;\n+\t}\n+\n+\t/* Shutdown PFE only if we're not waking up the system */\n+\tif (!pfe->wake) {\n+#if defined(LS1012A_PFE_RESET_WA)\n+\t\tpfe_hif_rx_idle(&pfe->hif);\n+#endif\n+\t\tpfe_ctrl_suspend(&pfe->ctrl);\n+\t\tpfe_firmware_exit(pfe);\n+\n+\t\tpfe_hif_exit(pfe);\n+\t\tpfe_hif_lib_exit(pfe);\n+\n+\t\tpfe_hw_exit(pfe);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int pfe_platform_resume(struct device *dev)\n+{\n+\tstruct pfe *pfe = platform_get_drvdata(to_platform_device(dev));\n+\tstruct net_device *netdev;\n+\tint i;\n+\n+\tif (!pfe->wake) {\n+\t\tpfe_hw_init(pfe, 1);\n+\t\tpfe_hif_lib_init(pfe);\n+\t\tpfe_hif_init(pfe);\n+#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)\n+\t\tutil_enable();\n+#endif\n+\t\ttmu_enable(0xf);\n+\t\tclass_enable();\n+\t\tpfe_ctrl_resume(&pfe->ctrl);\n+\t}\n+\n+\tfor (i = 0; i < (NUM_GEMAC_SUPPORT); i++) {\n+\t\tnetdev = pfe->eth.eth_priv[i]->ndev;\n+\n+\t\tif (pfe->mdio.mdio_priv[i]->mii_bus)\n+\t\t\tpfe_eth_mdio_reset(pfe->mdio.mdio_priv[i]->mii_bus);\n+\n+\t\tif (netif_running(netdev))\n+\t\t\tpfe_eth_resume(netdev);\n+\n+\t\tnetif_device_attach(netdev);\n+\t}\n+\treturn 0;\n+}\n+#else\n+#define pfe_platform_suspend NULL\n+#define pfe_platform_resume NULL\n+#endif\n+\n+static const struct dev_pm_ops pfe_platform_pm_ops = {\n+\tSET_SYSTEM_SLEEP_PM_OPS(pfe_platform_suspend, pfe_platform_resume)\n+};\n+#endif\n+\n+static const struct of_device_id pfe_match[] = {\n+\t{\n+\t\t.compatible = \"fsl,pfe\",\n+\t},\n+\t{},\n+};\n+MODULE_DEVICE_TABLE(of, pfe_match);\n+\n+static struct platform_driver pfe_platform_driver = {\n+\t.probe = pfe_platform_probe,\n+\t.remove = pfe_platform_remove,\n+\t.driver = {\n+\t\t.name = \"pfe\",\n+\t\t.of_match_table = pfe_match,\n+#ifdef CONFIG_PM\n+\t\t.pm = &pfe_platform_pm_ops,\n+#endif\n+\t},\n+};\n+\n+module_platform_driver(pfe_platform_driver);\n+MODULE_LICENSE(\"GPL\");\n+MODULE_DESCRIPTION(\"PFE Ethernet driver\");\n+MODULE_AUTHOR(\"NXP DNCPE\");\n--- /dev/null\n+++ b/drivers/staging/fsl_ppfe/pfe_mod.c\n@@ -0,0 +1,158 @@\n+// SPDX-License-Identifier: GPL-2.0+\n+/*\n+ * Copyright 2015-2016 Freescale Semiconductor, Inc.\n+ * Copyright 2017 NXP\n+ */\n+\n+#include <linux/dma-mapping.h>\n+#include \"pfe_mod.h\"\n+#include \"pfe_cdev.h\"\n+\n+unsigned int us;\n+module_param(us, uint, 0444);\n+MODULE_PARM_DESC(us, \"0: module enabled for kernel networking (DEFAULT)\\n\"\n+\t\t\t\"1: module enabled for userspace networking\\n\");\n+struct pfe *pfe;\n+\n+/*\n+ * pfe_probe -\n+ */\n+int pfe_probe(struct pfe *pfe)\n+{\n+\tint rc;\n+\n+\tif (pfe->ddr_size < DDR_MAX_SIZE) {\n+\t\tpr_err(\"%s: required DDR memory (%x) above platform ddr memory (%x)\\n\",\n+\t\t       __func__, (unsigned int)DDR_MAX_SIZE, pfe->ddr_size);\n+\t\trc = -ENOMEM;\n+\t\tgoto err_hw;\n+\t}\n+\n+\tif (((int)(pfe->ddr_phys_baseaddr + BMU2_DDR_BASEADDR) &\n+\t\t\t(8 * SZ_1M - 1)) != 0) {\n+\t\tpr_err(\"%s: BMU2 base address (0x%x) must be aligned on 8MB boundary\\n\",\n+\t\t       __func__, (int)pfe->ddr_phys_baseaddr +\n+\t\t\tBMU2_DDR_BASEADDR);\n+\t\trc = -ENOMEM;\n+\t\tgoto err_hw;\n+\t}\n+\n+\tpr_info(\"cbus_baseaddr: %lx, ddr_baseaddr: %lx, ddr_phys_baseaddr: %lx, ddr_size: %x\\n\",\n+\t\t(unsigned long)pfe->cbus_baseaddr,\n+\t\t(unsigned long)pfe->ddr_baseaddr,\n+\t\tpfe->ddr_phys_baseaddr, pfe->ddr_size);\n+\n+\tpfe_lib_init(pfe->cbus_baseaddr, pfe->ddr_baseaddr,\n+\t\t     pfe->ddr_phys_baseaddr, pfe->ddr_size);\n+\n+\trc = pfe_hw_init(pfe, 0);\n+\tif (rc < 0)\n+\t\tgoto err_hw;\n+\n+\tif (us)\n+\t\tgoto firmware_init;\n+\n+\trc = pfe_hif_lib_init(pfe);\n+\tif (rc < 0)\n+\t\tgoto err_hif_lib;\n+\n+\trc = pfe_hif_init(pfe);\n+\tif (rc < 0)\n+\t\tgoto err_hif;\n+\n+firmware_init:\n+\trc = pfe_firmware_init(pfe);\n+\tif (rc < 0)\n+\t\tgoto err_firmware;\n+\n+\trc = pfe_ctrl_init(pfe);\n+\tif (rc < 0)\n+\t\tgoto err_ctrl;\n+\n+\trc = pfe_eth_init(pfe);\n+\tif (rc < 0)\n+\t\tgoto err_eth;\n+\n+\trc = pfe_sysfs_init(pfe);\n+\tif (rc < 0)\n+\t\tgoto err_sysfs;\n+\n+\trc = pfe_debugfs_init(pfe);\n+\tif (rc < 0)\n+\t\tgoto err_debugfs;\n+\n+\tif (us) {\n+\t\t/* Creating a character device */\n+\t\trc = pfe_cdev_init();\n+\t\tif (rc < 0)\n+\t\t\tgoto err_cdev;\n+\t}\n+\n+\treturn 0;\n+\n+err_cdev:\n+\tpfe_debugfs_exit(pfe);\n+\n+err_debugfs:\n+\tpfe_sysfs_exit(pfe);\n+\n+err_sysfs:\n+\tpfe_eth_exit(pfe);\n+\n+err_eth:\n+\tpfe_ctrl_exit(pfe);\n+\n+err_ctrl:\n+\tpfe_firmware_exit(pfe);\n+\n+err_firmware:\n+\tif (us)\n+\t\tgoto err_hif_lib;\n+\n+\tpfe_hif_exit(pfe);\n+\n+err_hif:\n+\tpfe_hif_lib_exit(pfe);\n+\n+err_hif_lib:\n+\tpfe_hw_exit(pfe);\n+\n+err_hw:\n+\treturn rc;\n+}\n+\n+/*\n+ * pfe_remove -\n+ */\n+int pfe_remove(struct pfe *pfe)\n+{\n+\tpr_info(\"%s\\n\", __func__);\n+\n+\tif (us)\n+\t\tpfe_cdev_exit();\n+\n+\tpfe_debugfs_exit(pfe);\n+\n+\tpfe_sysfs_exit(pfe);\n+\n+\tpfe_eth_exit(pfe);\n+\n+\tpfe_ctrl_exit(pfe);\n+\n+#if defined(LS1012A_PFE_RESET_WA)\n+\tpfe_hif_rx_idle(&pfe->hif);\n+#endif\n+\tpfe_firmware_exit(pfe);\n+\n+\tif (us)\n+\t\tgoto hw_exit;\n+\n+\tpfe_hif_exit(pfe);\n+\n+\tpfe_hif_lib_exit(pfe);\n+\n+hw_exit:\n+\tpfe_hw_exit(pfe);\n+\n+\treturn 0;\n+}\n--- /dev/null\n+++ b/drivers/staging/fsl_ppfe/pfe_mod.h\n@@ -0,0 +1,103 @@\n+/* SPDX-License-Identifier: GPL-2.0+ */\n+/*\n+ * Copyright 2015-2016 Freescale Semiconductor, Inc.\n+ * Copyright 2017 NXP\n+ */\n+\n+#ifndef _PFE_MOD_H_\n+#define _PFE_MOD_H_\n+\n+#include <linux/device.h>\n+#include <linux/elf.h>\n+\n+extern unsigned int us;\n+\n+struct pfe;\n+\n+#include \"pfe_hw.h\"\n+#include \"pfe_firmware.h\"\n+#include \"pfe_ctrl.h\"\n+#include \"pfe_hif.h\"\n+#include \"pfe_hif_lib.h\"\n+#include \"pfe_eth.h\"\n+#include \"pfe_sysfs.h\"\n+#include \"pfe_perfmon.h\"\n+#include \"pfe_debugfs.h\"\n+\n+#define PHYID_MAX_VAL 32\n+\n+struct pfe_tmu_credit {\n+\t/* Number of allowed TX packet in-flight, matches TMU queue size */\n+\tunsigned int tx_credit[NUM_GEMAC_SUPPORT][EMAC_TXQ_CNT];\n+\tunsigned int tx_credit_max[NUM_GEMAC_SUPPORT][EMAC_TXQ_CNT];\n+\tunsigned int tx_packets[NUM_GEMAC_SUPPORT][EMAC_TXQ_CNT];\n+};\n+\n+struct pfe {\n+\tstruct regmap\t*scfg;\n+\tunsigned long ddr_phys_baseaddr;\n+\tvoid *ddr_baseaddr;\n+\tunsigned int ddr_size;\n+\tvoid *cbus_baseaddr;\n+\tvoid *apb_baseaddr;\n+\tunsigned long iram_phys_baseaddr;\n+\tvoid *iram_baseaddr;\n+\tunsigned long ipsec_phys_baseaddr;\n+\tvoid *ipsec_baseaddr;\n+\tint hif_irq;\n+\tint wol_irq;\n+\tint hif_client_irq;\n+\tstruct device *dev;\n+\tstruct dentry *dentry;\n+\tstruct pfe_ctrl ctrl;\n+\tstruct pfe_hif hif;\n+\tstruct pfe_eth eth;\n+\tstruct pfe_mdio mdio;\n+\tstruct hif_client_s *hif_client[HIF_CLIENTS_MAX];\n+#if defined(CFG_DIAGS)\n+\tstruct pfe_diags diags;\n+#endif\n+\tstruct pfe_tmu_credit tmu_credit;\n+\tstruct pfe_cpumon cpumon;\n+\tstruct pfe_memmon memmon;\n+\tint wake;\n+\tint mdio_muxval[PHYID_MAX_VAL];\n+\tstruct clk *hfe_clock;\n+};\n+\n+extern struct pfe *pfe;\n+\n+int pfe_probe(struct pfe *pfe);\n+int pfe_remove(struct pfe *pfe);\n+\n+/* DDR Mapping in reserved memory*/\n+#define ROUTE_TABLE_BASEADDR\t0\n+#define ROUTE_TABLE_HASH_BITS\t15\t/* 32K entries */\n+#define ROUTE_TABLE_SIZE\t((1 << ROUTE_TABLE_HASH_BITS) \\\n+\t\t\t\t  * CLASS_ROUTE_SIZE)\n+#define BMU2_DDR_BASEADDR\t(ROUTE_TABLE_BASEADDR + ROUTE_TABLE_SIZE)\n+#define BMU2_BUF_COUNT\t\t(4096 - 256)\n+/* This is to get a total DDR size of 12MiB */\n+#define BMU2_DDR_SIZE\t\t(DDR_BUF_SIZE * BMU2_BUF_COUNT)\n+#define UTIL_CODE_BASEADDR\t(BMU2_DDR_BASEADDR + BMU2_DDR_SIZE)\n+#define UTIL_CODE_SIZE\t\t(128 * SZ_1K)\n+#define UTIL_DDR_DATA_BASEADDR\t(UTIL_CODE_BASEADDR + UTIL_CODE_SIZE)\n+#define UTIL_DDR_DATA_SIZE\t(64 * SZ_1K)\n+#define CLASS_DDR_DATA_BASEADDR\t(UTIL_DDR_DATA_BASEADDR + UTIL_DDR_DATA_SIZE)\n+#define CLASS_DDR_DATA_SIZE\t(32 * SZ_1K)\n+#define TMU_DDR_DATA_BASEADDR\t(CLASS_DDR_DATA_BASEADDR + CLASS_DDR_DATA_SIZE)\n+#define TMU_DDR_DATA_SIZE\t(32 * SZ_1K)\n+#define TMU_LLM_BASEADDR\t(TMU_DDR_DATA_BASEADDR + TMU_DDR_DATA_SIZE)\n+#define TMU_LLM_QUEUE_LEN\t(8 * 512)\n+/* Must be power of two and at least 16 * 8 = 128 bytes */\n+#define TMU_LLM_SIZE\t\t(4 * 16 * TMU_LLM_QUEUE_LEN)\n+/* (4 TMU's x 16 queues x queue_len) */\n+\n+#define DDR_MAX_SIZE\t\t(TMU_LLM_BASEADDR + TMU_LLM_SIZE)\n+\n+/* LMEM Mapping */\n+#define BMU1_LMEM_BASEADDR\t0\n+#define BMU1_BUF_COUNT\t\t256\n+#define BMU1_LMEM_SIZE\t\t(LMEM_BUF_SIZE * BMU1_BUF_COUNT)\n+\n+#endif /* _PFE_MOD_H */\n--- /dev/null\n+++ b/drivers/staging/fsl_ppfe/pfe_perfmon.h\n@@ -0,0 +1,26 @@\n+/* SPDX-License-Identifier: GPL-2.0+ */\n+/*\n+ * Copyright 2015-2016 Freescale Semiconductor, Inc.\n+ * Copyright 2017 NXP\n+ */\n+\n+#ifndef _PFE_PERFMON_H_\n+#define _PFE_PERFMON_H_\n+\n+#include \"pfe/pfe.h\"\n+\n+#define\tCT_CPUMON_INTERVAL\t(1 * TIMER_TICKS_PER_SEC)\n+\n+struct pfe_cpumon {\n+\tu32 cpu_usage_pct[MAX_PE];\n+\tu32 class_usage_pct;\n+};\n+\n+struct pfe_memmon {\n+\tu32 kernel_memory_allocated;\n+};\n+\n+int pfe_perfmon_init(struct pfe *pfe);\n+void pfe_perfmon_exit(struct pfe *pfe);\n+\n+#endif /* _PFE_PERFMON_H_ */\n--- /dev/null\n+++ b/drivers/staging/fsl_ppfe/pfe_sysfs.c\n@@ -0,0 +1,840 @@\n+// SPDX-License-Identifier: GPL-2.0+\n+/*\n+ * Copyright 2015-2016 Freescale Semiconductor, Inc.\n+ * Copyright 2017 NXP\n+ */\n+\n+#include <linux/module.h>\n+#include <linux/platform_device.h>\n+\n+#include \"pfe_mod.h\"\n+\n+#define PE_EXCEPTION_DUMP_ADDRESS 0x1fa8\n+#define NUM_QUEUES\t\t16\n+\n+static char register_name[20][5] = {\n+\t\"EPC\", \"ECAS\", \"EID\", \"ED\",\n+\t\"r0\", \"r1\", \"r2\", \"r3\",\n+\t\"r4\", \"r5\", \"r6\", \"r7\",\n+\t\"r8\", \"r9\", \"r10\", \"r11\",\n+\t\"r12\", \"r13\", \"r14\", \"r15\",\n+};\n+\n+static char exception_name[14][20] = {\n+\t\"Reset\",\n+\t\"HardwareFailure\",\n+\t\"NMI\",\n+\t\"InstBreakpoint\",\n+\t\"DataBreakpoint\",\n+\t\"Unsupported\",\n+\t\"PrivilegeViolation\",\n+\t\"InstBusError\",\n+\t\"DataBusError\",\n+\t\"AlignmentError\",\n+\t\"ArithmeticError\",\n+\t\"SystemCall\",\n+\t\"MemoryManagement\",\n+\t\"Interrupt\",\n+};\n+\n+static unsigned long class_do_clear;\n+static unsigned long tmu_do_clear;\n+#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)\n+static unsigned long util_do_clear;\n+#endif\n+\n+static ssize_t display_pe_status(char *buf, int id, u32 dmem_addr, unsigned long\n+\t\t\t\t\tdo_clear)\n+{\n+\tssize_t len = 0;\n+\tu32 val;\n+\tchar statebuf[5];\n+\tstruct pfe_cpumon *cpumon = &pfe->cpumon;\n+\tu32 debug_indicator;\n+\tu32 debug[20];\n+\n+\tif (id < CLASS0_ID || id >= MAX_PE)\n+\t\treturn len;\n+\n+\t*(u32 *)statebuf = pe_dmem_read(id, dmem_addr, 4);\n+\tdmem_addr += 4;\n+\n+\tstatebuf[4] = '\\0';\n+\tlen += sprintf(buf + len, \"state=%4s \", statebuf);\n+\n+\tval = pe_dmem_read(id, dmem_addr, 4);\n+\tdmem_addr += 4;\n+\tlen += sprintf(buf + len, \"ctr=%08x \", cpu_to_be32(val));\n+\n+\tval = pe_dmem_read(id, dmem_addr, 4);\n+\tif (do_clear && val)\n+\t\tpe_dmem_write(id, 0, dmem_addr, 4);\n+\tdmem_addr += 4;\n+\tlen += sprintf(buf + len, \"rx=%u \", cpu_to_be32(val));\n+\n+\tval = pe_dmem_read(id, dmem_addr, 4);\n+\tif (do_clear && val)\n+\t\tpe_dmem_write(id, 0, dmem_addr, 4);\n+\tdmem_addr += 4;\n+\tif (id >= TMU0_ID && id <= TMU_MAX_ID)\n+\t\tlen += sprintf(buf + len, \"qstatus=%x\", cpu_to_be32(val));\n+\telse\n+\t\tlen += sprintf(buf + len, \"tx=%u\", cpu_to_be32(val));\n+\n+\tval = pe_dmem_read(id, dmem_addr, 4);\n+\tif (do_clear && val)\n+\t\tpe_dmem_write(id, 0, dmem_addr, 4);\n+\tdmem_addr += 4;\n+\tif (val)\n+\t\tlen += sprintf(buf + len, \" drop=%u\", cpu_to_be32(val));\n+\n+\tlen += sprintf(buf + len, \" load=%d%%\", cpumon->cpu_usage_pct[id]);\n+\n+\tlen += sprintf(buf + len, \"\\n\");\n+\n+\tdebug_indicator = pe_dmem_read(id, dmem_addr, 4);\n+\tdmem_addr += 4;\n+\tif (!strncmp((char *)&debug_indicator, \"DBUG\", 4)) {\n+\t\tint j, last = 0;\n+\n+\t\tfor (j = 0; j < 16; j++) {\n+\t\t\tdebug[j] = pe_dmem_read(id, dmem_addr, 4);\n+\t\t\tif (debug[j]) {\n+\t\t\t\tif (do_clear)\n+\t\t\t\t\tpe_dmem_write(id, 0, dmem_addr, 4);\n+\t\t\t\tlast = j + 1;\n+\t\t\t}\n+\t\t\tdmem_addr += 4;\n+\t\t}\n+\t\tfor (j = 0; j < last; j++) {\n+\t\t\tlen += sprintf(buf + len, \"%08x%s\",\n+\t\t\tcpu_to_be32(debug[j]),\n+\t\t\t(j & 0x7) == 0x7 || j == last - 1 ? \"\\n\" : \" \");\n+\t\t}\n+\t}\n+\n+\tif (!strncmp(statebuf, \"DEAD\", 4)) {\n+\t\tu32 i, dump = PE_EXCEPTION_DUMP_ADDRESS;\n+\n+\t\tlen += sprintf(buf + len, \"Exception details:\\n\");\n+\t\tfor (i = 0; i < 20; i++) {\n+\t\t\tdebug[i] = pe_dmem_read(id, dump, 4);\n+\t\t\tdump += 4;\n+\t\t\tif (i == 2)\n+\t\t\t\tlen += sprintf(buf + len, \"%4s = %08x (=%s) \",\n+\t\t\t\tregister_name[i], cpu_to_be32(debug[i]),\n+\t\t\t\texception_name[min((u32)\n+\t\t\t\tcpu_to_be32(debug[i]), (u32)13)]);\n+\t\t\telse\n+\t\t\t\tlen += sprintf(buf + len, \"%4s = %08x%s\",\n+\t\t\t\tregister_name[i], cpu_to_be32(debug[i]),\n+\t\t\t\t(i & 0x3) == 0x3 || i == 19 ? \"\\n\" : \" \");\n+\t\t}\n+\t}\n+\n+\treturn len;\n+}\n+\n+static ssize_t class_phy_stats(char *buf, int phy)\n+{\n+\tssize_t len = 0;\n+\tint off1 = phy * 0x28;\n+\tint off2 = phy * 0x10;\n+\n+\tif (phy == 3)\n+\t\toff1 = CLASS_PHY4_RX_PKTS - CLASS_PHY1_RX_PKTS;\n+\n+\tlen += sprintf(buf + len, \"phy: %d\\n\", phy);\n+\tlen += sprintf(buf + len,\n+\t\t\t\"  rx:   %10u, tx:   %10u, intf:  %10u, ipv4:    %10u, ipv6: %10u\\n\",\n+\t\t\treadl(CLASS_PHY1_RX_PKTS + off1),\n+\t\t\treadl(CLASS_PHY1_TX_PKTS + off1),\n+\t\t\treadl(CLASS_PHY1_INTF_MATCH_PKTS + off1),\n+\t\t\treadl(CLASS_PHY1_V4_PKTS + off1),\n+\t\t\treadl(CLASS_PHY1_V6_PKTS + off1));\n+\n+\tlen += sprintf(buf + len,\n+\t\t\t\"  icmp: %10u, igmp: %10u, tcp:   %10u, udp:     %10u\\n\",\n+\t\t\treadl(CLASS_PHY1_ICMP_PKTS + off2),\n+\t\t\treadl(CLASS_PHY1_IGMP_PKTS + off2),\n+\t\t\treadl(CLASS_PHY1_TCP_PKTS + off2),\n+\t\t\treadl(CLASS_PHY1_UDP_PKTS + off2));\n+\n+\tlen += sprintf(buf + len, \"  err\\n\");\n+\tlen += sprintf(buf + len,\n+\t\t\t\"  lp:   %10u, intf: %10u, l3:    %10u, chcksum: %10u, ttl:  %10u\\n\",\n+\t\t\treadl(CLASS_PHY1_LP_FAIL_PKTS + off1),\n+\t\t\treadl(CLASS_PHY1_INTF_FAIL_PKTS + off1),\n+\t\t\treadl(CLASS_PHY1_L3_FAIL_PKTS + off1),\n+\t\t\treadl(CLASS_PHY1_CHKSUM_ERR_PKTS + off1),\n+\t\t\treadl(CLASS_PHY1_TTL_ERR_PKTS + off1));\n+\n+\treturn len;\n+}\n+\n+/* qm_read_drop_stat\n+ * This function is used to read the drop statistics from the TMU\n+ * hw drop counter.  Since the hw counter is always cleared afer\n+ * reading, this function maintains the previous drop count, and\n+ * adds the new value to it.  That value can be retrieved by\n+ * passing a pointer to it with the total_drops arg.\n+ *\n+ * @param tmu\t\tTMU number (0 - 3)\n+ * @param queue\t\tqueue number (0 - 15)\n+ * @param total_drops\tpointer to location to store total drops (or NULL)\n+ * @param do_reset\tif TRUE, clear total drops after updating\n+ */\n+u32 qm_read_drop_stat(u32 tmu, u32 queue, u32 *total_drops, int do_reset)\n+{\n+\tstatic u32 qtotal[TMU_MAX_ID + 1][NUM_QUEUES];\n+\tu32 val;\n+\n+\twritel((tmu << 8) | queue, TMU_TEQ_CTRL);\n+\twritel((tmu << 8) | queue, TMU_LLM_CTRL);\n+\tval = readl(TMU_TEQ_DROP_STAT);\n+\tqtotal[tmu][queue] += val;\n+\tif (total_drops)\n+\t\t*total_drops = qtotal[tmu][queue];\n+\tif (do_reset)\n+\t\tqtotal[tmu][queue] = 0;\n+\treturn val;\n+}\n+\n+static ssize_t tmu_queue_stats(char *buf, int tmu, int queue)\n+{\n+\tssize_t len = 0;\n+\tu32 drops;\n+\n+\tlen += sprintf(buf + len, \"%d-%02d, \", tmu, queue);\n+\n+\tdrops = qm_read_drop_stat(tmu, queue, NULL, 0);\n+\n+\t/* Select queue */\n+\twritel((tmu << 8) | queue, TMU_TEQ_CTRL);\n+\twritel((tmu << 8) | queue, TMU_LLM_CTRL);\n+\n+\tlen += sprintf(buf + len,\n+\t\t\t\"(teq) drop: %10u, tx: %10u (llm) head: %08x, tail: %08x, drop: %10u\\n\",\n+\t\tdrops, readl(TMU_TEQ_TRANS_STAT),\n+\t\treadl(TMU_LLM_QUE_HEADPTR), readl(TMU_LLM_QUE_TAILPTR),\n+\t\treadl(TMU_LLM_QUE_DROPCNT));\n+\n+\treturn len;\n+}\n+\n+static ssize_t tmu_queues(char *buf, int tmu)\n+{\n+\tssize_t len = 0;\n+\tint queue;\n+\n+\tfor (queue = 0; queue < 16; queue++)\n+\t\tlen += tmu_queue_stats(buf + len, tmu, queue);\n+\n+\treturn len;\n+}\n+\n+static ssize_t block_version(char *buf, void *addr)\n+{\n+\tssize_t len = 0;\n+\tu32 val;\n+\n+\tval = readl(addr);\n+\tlen += sprintf(buf + len, \"revision: %x, version: %x, id: %x\\n\",\n+\t\t(val >> 24) & 0xff, (val >> 16) & 0xff, val & 0xffff);\n+\n+\treturn len;\n+}\n+\n+static ssize_t bmu(char *buf, int id, void *base)\n+{\n+\tssize_t len = 0;\n+\n+\tlen += sprintf(buf + len, \"%s: %d\\n  \", __func__, id);\n+\n+\tlen += block_version(buf + len, base + BMU_VERSION);\n+\n+\tlen += sprintf(buf + len, \"  buf size:  %x\\n\", (1 << readl(base +\n+\t\t\tBMU_BUF_SIZE)));\n+\tlen += sprintf(buf + len, \"  buf count: %x\\n\", readl(base +\n+\t\t\tBMU_BUF_CNT));\n+\tlen += sprintf(buf + len, \"  buf rem:   %x\\n\", readl(base +\n+\t\t\tBMU_REM_BUF_CNT));\n+\tlen += sprintf(buf + len, \"  buf curr:  %x\\n\", readl(base +\n+\t\t\tBMU_CURR_BUF_CNT));\n+\tlen += sprintf(buf + len, \"  free err:  %x\\n\", readl(base +\n+\t\t\tBMU_FREE_ERR_ADDR));\n+\n+\treturn len;\n+}\n+\n+static ssize_t gpi(char *buf, int id, void *base)\n+{\n+\tssize_t len = 0;\n+\tu32 val;\n+\n+\tlen += sprintf(buf + len, \"%s%d:\\n  \", __func__, id);\n+\tlen += block_version(buf + len, base + GPI_VERSION);\n+\n+\tlen += sprintf(buf + len, \"  tx under stick: %x\\n\", readl(base +\n+\t\t\tGPI_FIFO_STATUS));\n+\tval = readl(base + GPI_FIFO_DEBUG);\n+\tlen += sprintf(buf + len, \"  tx pkts:        %x\\n\", (val >> 23) &\n+\t\t\t0x3f);\n+\tlen += sprintf(buf + len, \"  rx pkts:        %x\\n\", (val >> 18) &\n+\t\t\t0x3f);\n+\tlen += sprintf(buf + len, \"  tx bytes:       %x\\n\", (val >> 9) &\n+\t\t\t0x1ff);\n+\tlen += sprintf(buf + len, \"  rx bytes:       %x\\n\", (val >> 0) &\n+\t\t\t0x1ff);\n+\tlen += sprintf(buf + len, \"  overrun:        %x\\n\", readl(base +\n+\t\t\tGPI_OVERRUN_DROPCNT));\n+\n+\treturn len;\n+}\n+\n+static ssize_t pfe_set_class(struct device *dev, struct device_attribute *attr,\n+\t\t\t     const char *buf, size_t count)\n+{\n+\tclass_do_clear = kstrtoul(buf, 0, 0);\n+\treturn count;\n+}\n+\n+static ssize_t pfe_show_class(struct device *dev, struct device_attribute *attr,\n+\t\t\t      char *buf)\n+{\n+\tssize_t len = 0;\n+\tint id;\n+\tu32 val;\n+\tstruct pfe_cpumon *cpumon = &pfe->cpumon;\n+\n+\tlen += block_version(buf + len, CLASS_VERSION);\n+\n+\tfor (id = CLASS0_ID; id <= CLASS_MAX_ID; id++) {\n+\t\tlen += sprintf(buf + len, \"%d: \", id - CLASS0_ID);\n+\n+\t\tval = readl(CLASS_PE0_DEBUG + id * 4);\n+\t\tlen += sprintf(buf + len, \"pc=1%04x \", val & 0xffff);\n+\n+\t\tlen += display_pe_status(buf + len, id, CLASS_DM_PESTATUS,\n+\t\t\t\t\t\tclass_do_clear);\n+\t}\n+\tlen += sprintf(buf + len, \"aggregate load=%d%%\\n\\n\",\n+\t\t\tcpumon->class_usage_pct);\n+\n+\tlen += sprintf(buf + len, \"pe status:   0x%x\\n\",\n+\t\t\treadl(CLASS_PE_STATUS));\n+\tlen += sprintf(buf + len, \"max buf cnt: 0x%x   afull thres: 0x%x\\n\",\n+\t\t\treadl(CLASS_MAX_BUF_CNT), readl(CLASS_AFULL_THRES));\n+\tlen += sprintf(buf + len, \"tsq max cnt: 0x%x   tsq fifo thres: 0x%x\\n\",\n+\t\t\treadl(CLASS_TSQ_MAX_CNT), readl(CLASS_TSQ_FIFO_THRES));\n+\tlen += sprintf(buf + len, \"state:       0x%x\\n\", readl(CLASS_STATE));\n+\n+\tlen += class_phy_stats(buf + len, 0);\n+\tlen += class_phy_stats(buf + len, 1);\n+\tlen += class_phy_stats(buf + len, 2);\n+\tlen += class_phy_stats(buf + len, 3);\n+\n+\treturn len;\n+}\n+\n+static ssize_t pfe_set_tmu(struct device *dev, struct device_attribute *attr,\n+\t\t\t   const char *buf, size_t count)\n+{\n+\ttmu_do_clear = kstrtoul(buf, 0, 0);\n+\treturn count;\n+}\n+\n+static ssize_t pfe_show_tmu(struct device *dev, struct device_attribute *attr,\n+\t\t\t    char *buf)\n+{\n+\tssize_t len = 0;\n+\tint id;\n+\tu32 val;\n+\n+\tlen += block_version(buf + len, TMU_VERSION);\n+\n+\tfor (id = TMU0_ID; id <= TMU_MAX_ID; id++) {\n+\t\tif (id == TMU2_ID)\n+\t\t\tcontinue;\n+\t\tlen += sprintf(buf + len, \"%d: \", id - TMU0_ID);\n+\n+\t\tlen += display_pe_status(buf + len, id, TMU_DM_PESTATUS,\n+\t\t\t\t\t\ttmu_do_clear);\n+\t}\n+\n+\tlen += sprintf(buf + len, \"pe status:    %x\\n\", readl(TMU_PE_STATUS));\n+\tlen += sprintf(buf + len, \"inq fifo cnt: %x\\n\",\n+\t\t\treadl(TMU_PHY_INQ_FIFO_CNT));\n+\tval = readl(TMU_INQ_STAT);\n+\tlen += sprintf(buf + len, \"inq wr ptr:     %x\\n\", val & 0x3ff);\n+\tlen += sprintf(buf + len, \"inq rd ptr:     %x\\n\", val >> 10);\n+\n+\treturn len;\n+}\n+\n+static unsigned long drops_do_clear;\n+static u32 class_drop_counter[CLASS_NUM_DROP_COUNTERS];\n+#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)\n+static u32 util_drop_counter[UTIL_NUM_DROP_COUNTERS];\n+#endif\n+\n+char *class_drop_description[CLASS_NUM_DROP_COUNTERS] = {\n+\t\"ICC\",\n+\t\"Host Pkt Error\",\n+\t\"Rx Error\",\n+\t\"IPsec Outbound\",\n+\t\"IPsec Inbound\",\n+\t\"EXPT IPsec Error\",\n+\t\"Reassembly\",\n+\t\"Fragmenter\",\n+\t\"NAT-T\",\n+\t\"Socket\",\n+\t\"Multicast\",\n+\t\"NAT-PT\",\n+\t\"Tx Disabled\",\n+};\n+\n+#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)\n+char *util_drop_description[UTIL_NUM_DROP_COUNTERS] = {\n+\t\"IPsec Outbound\",\n+\t\"IPsec Inbound\",\n+\t\"IPsec Rate Limiter\",\n+\t\"Fragmenter\",\n+\t\"Socket\",\n+\t\"Tx Disabled\",\n+\t\"Rx Error\",\n+};\n+#endif\n+\n+static ssize_t pfe_set_drops(struct device *dev, struct device_attribute *attr,\n+\t\t\t     const char *buf, size_t count)\n+{\n+\tdrops_do_clear = kstrtoul(buf, 0, 0);\n+\treturn count;\n+}\n+\n+static u32 tmu_drops[4][16];\n+static ssize_t pfe_show_drops(struct device *dev, struct device_attribute *attr,\n+\t\t\t      char *buf)\n+{\n+\tssize_t len = 0;\n+\tint id, dropnum;\n+\tint tmu, queue;\n+\tu32 val;\n+\tu32 dmem_addr;\n+\tint num_class_drops = 0, num_tmu_drops = 0, num_util_drops = 0;\n+\tstruct pfe_ctrl *ctrl = &pfe->ctrl;\n+\n+\tmemset(class_drop_counter, 0, sizeof(class_drop_counter));\n+\tfor (id = CLASS0_ID; id <= CLASS_MAX_ID; id++) {\n+\t\tif (drops_do_clear)\n+\t\t\tpe_sync_stop(ctrl, (1 << id));\n+\t\tfor (dropnum = 0; dropnum < CLASS_NUM_DROP_COUNTERS;\n+\t\t\tdropnum++) {\n+\t\t\tdmem_addr = CLASS_DM_DROP_CNTR;\n+\t\t\tval = be32_to_cpu(pe_dmem_read(id, dmem_addr, 4));\n+\t\t\tclass_drop_counter[dropnum] += val;\n+\t\t\tnum_class_drops += val;\n+\t\t\tif (drops_do_clear)\n+\t\t\t\tpe_dmem_write(id, 0, dmem_addr, 4);\n+\t\t}\n+\t\tif (drops_do_clear)\n+\t\t\tpe_start(ctrl, (1 << id));\n+\t}\n+\n+#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)\n+\tif (drops_do_clear)\n+\t\tpe_sync_stop(ctrl, (1 << UTIL_ID));\n+\tfor (dropnum = 0; dropnum < UTIL_NUM_DROP_COUNTERS; dropnum++) {\n+\t\tdmem_addr = UTIL_DM_DROP_CNTR;\n+\t\tval = be32_to_cpu(pe_dmem_read(UTIL_ID, dmem_addr, 4));\n+\t\tutil_drop_counter[dropnum] = val;\n+\t\tnum_util_drops += val;\n+\t\tif (drops_do_clear)\n+\t\t\tpe_dmem_write(UTIL_ID, 0, dmem_addr, 4);\n+\t}\n+\tif (drops_do_clear)\n+\t\tpe_start(ctrl, (1 << UTIL_ID));\n+#endif\n+\tfor (tmu = 0; tmu < 4; tmu++) {\n+\t\tfor (queue = 0; queue < 16; queue++) {\n+\t\t\tqm_read_drop_stat(tmu, queue, &tmu_drops[tmu][queue],\n+\t\t\t\t\t  drops_do_clear);\n+\t\t\tnum_tmu_drops += tmu_drops[tmu][queue];\n+\t\t}\n+\t}\n+\n+\tif (num_class_drops == 0 && num_util_drops == 0 && num_tmu_drops == 0)\n+\t\tlen += sprintf(buf + len, \"No PE drops\\n\\n\");\n+\n+\tif (num_class_drops > 0) {\n+\t\tlen += sprintf(buf + len, \"Class PE drops --\\n\");\n+\t\tfor (dropnum = 0; dropnum < CLASS_NUM_DROP_COUNTERS;\n+\t\t\tdropnum++) {\n+\t\t\tif (class_drop_counter[dropnum] > 0)\n+\t\t\t\tlen += sprintf(buf + len, \"  %s: %d\\n\",\n+\t\t\t\t\tclass_drop_description[dropnum],\n+\t\t\t\t\tclass_drop_counter[dropnum]);\n+\t\t}\n+\t\tlen += sprintf(buf + len, \"\\n\");\n+\t}\n+\n+#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)\n+\tif (num_util_drops > 0) {\n+\t\tlen += sprintf(buf + len, \"Util PE drops --\\n\");\n+\t\tfor (dropnum = 0; dropnum < UTIL_NUM_DROP_COUNTERS; dropnum++) {\n+\t\t\tif (util_drop_counter[dropnum] > 0)\n+\t\t\t\tlen += sprintf(buf + len, \"  %s: %d\\n\",\n+\t\t\t\t\tutil_drop_description[dropnum],\n+\t\t\t\t\tutil_drop_counter[dropnum]);\n+\t\t}\n+\t\tlen += sprintf(buf + len, \"\\n\");\n+\t}\n+#endif\n+\tif (num_tmu_drops > 0) {\n+\t\tlen += sprintf(buf + len, \"TMU drops --\\n\");\n+\t\tfor (tmu = 0; tmu < 4; tmu++) {\n+\t\t\tfor (queue = 0; queue < 16; queue++) {\n+\t\t\t\tif (tmu_drops[tmu][queue] > 0)\n+\t\t\t\t\tlen += sprintf(buf + len,\n+\t\t\t\t\t\t\"  TMU%d-Q%d: %d\\n\"\n+\t\t\t\t\t, tmu, queue, tmu_drops[tmu][queue]);\n+\t\t\t}\n+\t\t}\n+\t\tlen += sprintf(buf + len, \"\\n\");\n+\t}\n+\n+\treturn len;\n+}\n+\n+static ssize_t pfe_show_tmu0_queues(struct device *dev, struct device_attribute\n+\t\t\t\t\t*attr, char *buf)\n+{\n+\treturn tmu_queues(buf, 0);\n+}\n+\n+static ssize_t pfe_show_tmu1_queues(struct device *dev, struct device_attribute\n+\t\t\t\t\t*attr, char *buf)\n+{\n+\treturn tmu_queues(buf, 1);\n+}\n+\n+static ssize_t pfe_show_tmu2_queues(struct device *dev, struct device_attribute\n+\t\t\t\t\t*attr, char *buf)\n+{\n+\treturn tmu_queues(buf, 2);\n+}\n+\n+static ssize_t pfe_show_tmu3_queues(struct device *dev, struct device_attribute\n+\t\t\t\t\t*attr, char *buf)\n+{\n+\treturn tmu_queues(buf, 3);\n+}\n+\n+#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)\n+static ssize_t pfe_set_util(struct device *dev, struct device_attribute *attr,\n+\t\t\t    const char *buf, size_t count)\n+{\n+\tutil_do_clear = kstrtoul(buf, NULL, 0);\n+\treturn count;\n+}\n+\n+static ssize_t pfe_show_util(struct device *dev, struct device_attribute *attr,\n+\t\t\t     char *buf)\n+{\n+\tssize_t len = 0;\n+\tstruct pfe_ctrl *ctrl = &pfe->ctrl;\n+\n+\tlen += block_version(buf + len, UTIL_VERSION);\n+\n+\tpe_sync_stop(ctrl, (1 << UTIL_ID));\n+\tlen += display_pe_status(buf + len, UTIL_ID, UTIL_DM_PESTATUS,\n+\t\t\t\t\tutil_do_clear);\n+\tpe_start(ctrl, (1 << UTIL_ID));\n+\n+\tlen += sprintf(buf + len, \"pe status:   %x\\n\", readl(UTIL_PE_STATUS));\n+\tlen += sprintf(buf + len, \"max buf cnt: %x\\n\",\n+\t\t\treadl(UTIL_MAX_BUF_CNT));\n+\tlen += sprintf(buf + len, \"tsq max cnt: %x\\n\",\n+\t\t\treadl(UTIL_TSQ_MAX_CNT));\n+\n+\treturn len;\n+}\n+#endif\n+\n+static ssize_t pfe_show_bmu(struct device *dev, struct device_attribute *attr,\n+\t\t\t    char *buf)\n+{\n+\tssize_t len = 0;\n+\n+\tlen += bmu(buf + len, 1, BMU1_BASE_ADDR);\n+\tlen += bmu(buf + len, 2, BMU2_BASE_ADDR);\n+\n+\treturn len;\n+}\n+\n+static ssize_t pfe_show_hif(struct device *dev, struct device_attribute *attr,\n+\t\t\t    char *buf)\n+{\n+\tssize_t len = 0;\n+\n+\tlen += sprintf(buf + len, \"hif:\\n  \");\n+\tlen += block_version(buf + len, HIF_VERSION);\n+\n+\tlen += sprintf(buf + len, \"  tx curr bd:    %x\\n\",\n+\t\t\treadl(HIF_TX_CURR_BD_ADDR));\n+\tlen += sprintf(buf + len, \"  tx status:     %x\\n\",\n+\t\t\treadl(HIF_TX_STATUS));\n+\tlen += sprintf(buf + len, \"  tx dma status: %x\\n\",\n+\t\t\treadl(HIF_TX_DMA_STATUS));\n+\n+\tlen += sprintf(buf + len, \"  rx curr bd:    %x\\n\",\n+\t\t\treadl(HIF_RX_CURR_BD_ADDR));\n+\tlen += sprintf(buf + len, \"  rx status:     %x\\n\",\n+\t\t\treadl(HIF_RX_STATUS));\n+\tlen += sprintf(buf + len, \"  rx dma status: %x\\n\",\n+\t\t\treadl(HIF_RX_DMA_STATUS));\n+\n+\tlen += sprintf(buf + len, \"hif nocopy:\\n  \");\n+\tlen += block_version(buf + len, HIF_NOCPY_VERSION);\n+\n+\tlen += sprintf(buf + len, \"  tx curr bd:    %x\\n\",\n+\t\t\treadl(HIF_NOCPY_TX_CURR_BD_ADDR));\n+\tlen += sprintf(buf + len, \"  tx status:     %x\\n\",\n+\t\t\treadl(HIF_NOCPY_TX_STATUS));\n+\tlen += sprintf(buf + len, \"  tx dma status: %x\\n\",\n+\t\t\treadl(HIF_NOCPY_TX_DMA_STATUS));\n+\n+\tlen += sprintf(buf + len, \"  rx curr bd:    %x\\n\",\n+\t\t\treadl(HIF_NOCPY_RX_CURR_BD_ADDR));\n+\tlen += sprintf(buf + len, \"  rx status:     %x\\n\",\n+\t\t\treadl(HIF_NOCPY_RX_STATUS));\n+\tlen += sprintf(buf + len, \"  rx dma status: %x\\n\",\n+\t\t\treadl(HIF_NOCPY_RX_DMA_STATUS));\n+\n+\treturn len;\n+}\n+\n+static ssize_t pfe_show_gpi(struct device *dev, struct device_attribute *attr,\n+\t\t\t    char *buf)\n+{\n+\tssize_t len = 0;\n+\n+\tlen += gpi(buf + len, 0, EGPI1_BASE_ADDR);\n+\tlen += gpi(buf + len, 1, EGPI2_BASE_ADDR);\n+\tlen += gpi(buf + len, 3, HGPI_BASE_ADDR);\n+\n+\treturn len;\n+}\n+\n+static ssize_t pfe_show_pfemem(struct device *dev, struct device_attribute\n+\t\t\t\t*attr, char *buf)\n+{\n+\tssize_t len = 0;\n+\tstruct pfe_memmon *memmon = &pfe->memmon;\n+\n+\tlen += sprintf(buf + len, \"Kernel Memory: %d Bytes (%d KB)\\n\",\n+\t\tmemmon->kernel_memory_allocated,\n+\t\t(memmon->kernel_memory_allocated + 1023) / 1024);\n+\n+\treturn len;\n+}\n+\n+static ssize_t pfe_show_crc_revalidated(struct device *dev,\n+\t\t\t\t\tstruct device_attribute *attr,\n+\t\t\t\t\tchar *buf)\n+{\n+\tu64 crc_validated = 0;\n+\tssize_t len = 0;\n+\tint id, phyid;\n+\n+\tlen += sprintf(buf + len, \"FCS re-validated by PFE:\\n\");\n+\n+\tfor (phyid = 0; phyid < 2; phyid++) {\n+\t\tcrc_validated = 0;\n+\t\tfor (id = CLASS0_ID; id <= CLASS_MAX_ID; id++) {\n+\t\t\tcrc_validated += be32_to_cpu(pe_dmem_read(id,\n+\t\t\t\tCLASS_DM_CRC_VALIDATED + (phyid * 4), 4));\n+\t\t}\n+\t\tlen += sprintf(buf + len, \"MAC %d:\\n    count:%10llu\\n\",\n+\t\t\t       phyid, crc_validated);\n+\t}\n+\n+\treturn len;\n+}\n+\n+#ifdef HIF_NAPI_STATS\n+static ssize_t pfe_show_hif_napi_stats(struct device *dev,\n+\t\t\t\t       struct device_attribute *attr,\n+\t\t\t\t       char *buf)\n+{\n+\tstruct platform_device *pdev = to_platform_device(dev);\n+\tstruct pfe *pfe = platform_get_drvdata(pdev);\n+\tssize_t len = 0;\n+\n+\tlen += sprintf(buf + len, \"sched:  %u\\n\",\n+\t\t\tpfe->hif.napi_counters[NAPI_SCHED_COUNT]);\n+\tlen += sprintf(buf + len, \"poll:   %u\\n\",\n+\t\t\tpfe->hif.napi_counters[NAPI_POLL_COUNT]);\n+\tlen += sprintf(buf + len, \"packet: %u\\n\",\n+\t\t\tpfe->hif.napi_counters[NAPI_PACKET_COUNT]);\n+\tlen += sprintf(buf + len, \"budget: %u\\n\",\n+\t\t\tpfe->hif.napi_counters[NAPI_FULL_BUDGET_COUNT]);\n+\tlen += sprintf(buf + len, \"desc:   %u\\n\",\n+\t\t\tpfe->hif.napi_counters[NAPI_DESC_COUNT]);\n+\tlen += sprintf(buf + len, \"full:   %u\\n\",\n+\t\t\tpfe->hif.napi_counters[NAPI_CLIENT_FULL_COUNT]);\n+\n+\treturn len;\n+}\n+\n+static ssize_t pfe_set_hif_napi_stats(struct device *dev,\n+\t\t\t\t      struct device_attribute *attr,\n+\t\t\t\t\tconst char *buf, size_t count)\n+{\n+\tstruct platform_device *pdev = to_platform_device(dev);\n+\tstruct pfe *pfe = platform_get_drvdata(pdev);\n+\n+\tmemset(pfe->hif.napi_counters, 0, sizeof(pfe->hif.napi_counters));\n+\n+\treturn count;\n+}\n+\n+static DEVICE_ATTR(hif_napi_stats, 0644, pfe_show_hif_napi_stats,\n+\t\t\tpfe_set_hif_napi_stats);\n+#endif\n+\n+static DEVICE_ATTR(class, 0644, pfe_show_class, pfe_set_class);\n+static DEVICE_ATTR(tmu, 0644, pfe_show_tmu, pfe_set_tmu);\n+#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)\n+static DEVICE_ATTR(util, 0644, pfe_show_util, pfe_set_util);\n+#endif\n+static DEVICE_ATTR(bmu, 0444, pfe_show_bmu, NULL);\n+static DEVICE_ATTR(hif, 0444, pfe_show_hif, NULL);\n+static DEVICE_ATTR(gpi, 0444, pfe_show_gpi, NULL);\n+static DEVICE_ATTR(drops, 0644, pfe_show_drops, pfe_set_drops);\n+static DEVICE_ATTR(tmu0_queues, 0444, pfe_show_tmu0_queues, NULL);\n+static DEVICE_ATTR(tmu1_queues, 0444, pfe_show_tmu1_queues, NULL);\n+static DEVICE_ATTR(tmu2_queues, 0444, pfe_show_tmu2_queues, NULL);\n+static DEVICE_ATTR(tmu3_queues, 0444, pfe_show_tmu3_queues, NULL);\n+static DEVICE_ATTR(pfemem, 0444, pfe_show_pfemem, NULL);\n+static DEVICE_ATTR(fcs_revalidated, 0444, pfe_show_crc_revalidated, NULL);\n+\n+int pfe_sysfs_init(struct pfe *pfe)\n+{\n+\tif (device_create_file(pfe->dev, &dev_attr_class))\n+\t\tgoto err_class;\n+\n+\tif (device_create_file(pfe->dev, &dev_attr_tmu))\n+\t\tgoto err_tmu;\n+\n+#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)\n+\tif (device_create_file(pfe->dev, &dev_attr_util))\n+\t\tgoto err_util;\n+#endif\n+\n+\tif (device_create_file(pfe->dev, &dev_attr_bmu))\n+\t\tgoto err_bmu;\n+\n+\tif (device_create_file(pfe->dev, &dev_attr_hif))\n+\t\tgoto err_hif;\n+\n+\tif (device_create_file(pfe->dev, &dev_attr_gpi))\n+\t\tgoto err_gpi;\n+\n+\tif (device_create_file(pfe->dev, &dev_attr_drops))\n+\t\tgoto err_drops;\n+\n+\tif (device_create_file(pfe->dev, &dev_attr_tmu0_queues))\n+\t\tgoto err_tmu0_queues;\n+\n+\tif (device_create_file(pfe->dev, &dev_attr_tmu1_queues))\n+\t\tgoto err_tmu1_queues;\n+\n+\tif (device_create_file(pfe->dev, &dev_attr_tmu2_queues))\n+\t\tgoto err_tmu2_queues;\n+\n+\tif (device_create_file(pfe->dev, &dev_attr_tmu3_queues))\n+\t\tgoto err_tmu3_queues;\n+\n+\tif (device_create_file(pfe->dev, &dev_attr_pfemem))\n+\t\tgoto err_pfemem;\n+\n+\tif (device_create_file(pfe->dev, &dev_attr_fcs_revalidated))\n+\t\tgoto err_crc_revalidated;\n+\n+#ifdef HIF_NAPI_STATS\n+\tif (device_create_file(pfe->dev, &dev_attr_hif_napi_stats))\n+\t\tgoto err_hif_napi_stats;\n+#endif\n+\n+\treturn 0;\n+\n+#ifdef HIF_NAPI_STATS\n+err_hif_napi_stats:\n+\tdevice_remove_file(pfe->dev, &dev_attr_fcs_revalidated);\n+#endif\n+\n+err_crc_revalidated:\n+\tdevice_remove_file(pfe->dev, &dev_attr_pfemem);\n+\n+err_pfemem:\n+\tdevice_remove_file(pfe->dev, &dev_attr_tmu3_queues);\n+\n+err_tmu3_queues:\n+\tdevice_remove_file(pfe->dev, &dev_attr_tmu2_queues);\n+\n+err_tmu2_queues:\n+\tdevice_remove_file(pfe->dev, &dev_attr_tmu1_queues);\n+\n+err_tmu1_queues:\n+\tdevice_remove_file(pfe->dev, &dev_attr_tmu0_queues);\n+\n+err_tmu0_queues:\n+\tdevice_remove_file(pfe->dev, &dev_attr_drops);\n+\n+err_drops:\n+\tdevice_remove_file(pfe->dev, &dev_attr_gpi);\n+\n+err_gpi:\n+\tdevice_remove_file(pfe->dev, &dev_attr_hif);\n+\n+err_hif:\n+\tdevice_remove_file(pfe->dev, &dev_attr_bmu);\n+\n+err_bmu:\n+#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)\n+\tdevice_remove_file(pfe->dev, &dev_attr_util);\n+\n+err_util:\n+#endif\n+\tdevice_remove_file(pfe->dev, &dev_attr_tmu);\n+\n+err_tmu:\n+\tdevice_remove_file(pfe->dev, &dev_attr_class);\n+\n+err_class:\n+\treturn -1;\n+}\n+\n+void pfe_sysfs_exit(struct pfe *pfe)\n+{\n+#ifdef HIF_NAPI_STATS\n+\tdevice_remove_file(pfe->dev, &dev_attr_hif_napi_stats);\n+#endif\n+\tdevice_remove_file(pfe->dev, &dev_attr_fcs_revalidated);\n+\tdevice_remove_file(pfe->dev, &dev_attr_pfemem);\n+\tdevice_remove_file(pfe->dev, &dev_attr_tmu3_queues);\n+\tdevice_remove_file(pfe->dev, &dev_attr_tmu2_queues);\n+\tdevice_remove_file(pfe->dev, &dev_attr_tmu1_queues);\n+\tdevice_remove_file(pfe->dev, &dev_attr_tmu0_queues);\n+\tdevice_remove_file(pfe->dev, &dev_attr_drops);\n+\tdevice_remove_file(pfe->dev, &dev_attr_gpi);\n+\tdevice_remove_file(pfe->dev, &dev_attr_hif);\n+\tdevice_remove_file(pfe->dev, &dev_attr_bmu);\n+#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)\n+\tdevice_remove_file(pfe->dev, &dev_attr_util);\n+#endif\n+\tdevice_remove_file(pfe->dev, &dev_attr_tmu);\n+\tdevice_remove_file(pfe->dev, &dev_attr_class);\n+}\n--- /dev/null\n+++ b/drivers/staging/fsl_ppfe/pfe_sysfs.h\n@@ -0,0 +1,17 @@\n+/* SPDX-License-Identifier: GPL-2.0+ */\n+/*\n+ * Copyright 2015-2016 Freescale Semiconductor, Inc.\n+ * Copyright 2017 NXP\n+ */\n+\n+#ifndef _PFE_SYSFS_H_\n+#define _PFE_SYSFS_H_\n+\n+#include <linux/proc_fs.h>\n+\n+u32 qm_read_drop_stat(u32 tmu, u32 queue, u32 *total_drops, int do_reset);\n+\n+int pfe_sysfs_init(struct pfe *pfe);\n+void pfe_sysfs_exit(struct pfe *pfe);\n+\n+#endif /* _PFE_SYSFS_H_ */\n"
  },
  {
    "path": "target/linux/layerscape/patches-5.10/702-phy-Add-2.5G-SGMII-interface-mode.patch",
    "content": "From c918c472546afa83a619ae3cb1a9d7d346c6e288 Mon Sep 17 00:00:00 2001\nFrom: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>\nDate: Wed, 29 Nov 2017 15:27:57 +0530\nSubject: [PATCH 154/173] phy: Add 2.5G SGMII interface mode\n\nAdd 2.5G SGMII interface mode(PHY_INTERFACE_MODE_2500SGMII)\nin existing phy_interface list\n\nSigned-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>\n---\n include/linux/phy.h | 3 +++\n 1 file changed, 3 insertions(+)\n\n--- a/include/linux/phy.h\n+++ b/include/linux/phy.h\n@@ -146,6 +146,7 @@ typedef enum {\n \tPHY_INTERFACE_MODE_USXGMII,\n \t/* 10GBASE-KR - with Clause 73 AN */\n \tPHY_INTERFACE_MODE_10GKR,\n+\tPHY_INTERFACE_MODE_2500SGMII,\n \tPHY_INTERFACE_MODE_MAX,\n } phy_interface_t;\n \n@@ -221,6 +222,8 @@ static inline const char *phy_modes(phy_\n \t\treturn \"10gbase-kr\";\n \tcase PHY_INTERFACE_MODE_100BASEX:\n \t\treturn \"100base-x\";\n+\tcase PHY_INTERFACE_MODE_2500SGMII:\n+\t\treturn \"sgmii-2500\";\n \tdefault:\n \t\treturn \"unknown\";\n \t}\n"
  },
  {
    "path": "target/linux/malta/Makefile",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2010-2011 OpenWrt.org\n\ninclude $(TOPDIR)/rules.mk\n\nBOARD:=malta\nBOARDNAME:=MIPS Malta CoreLV board (qemu)\nSUBTARGETS:=le be le64 be64\nINITRAMFS_EXTRA_FILES:=\nFEATURES:=cpiogz ext4 ramdisk squashfs targz\n\nKERNEL_PATCHVER:=5.10\nKERNEL_TESTING_PATCHVER:=5.15\n\ninclude $(INCLUDE_DIR)/target.mk\n\nDEFAULT_PACKAGES += wpad-basic-wolfssl kmod-mac80211-hwsim kmod-pcnet32 mkf2fs e2fsprogs\n\n$(eval $(call BuildTarget))\n"
  },
  {
    "path": "target/linux/malta/README",
    "content": "This Malta target is intended to be used with the Qemu emulator. It can be used\nto prototype an OpenWrt firmware for MIPS processors. One could also use it to\ntroubleshoot MIPS applications without access to real hardware.\n\nTo use the images built by OpenWrt with qemu, use the following commands:\n\nFor the 32 bit little-endian image:\nqemu-system-mipsel -kernel bin/targets/malta/le/openwrt-malta-le-vmlinux-initramfs.elf -nographic -m 256\n\nFor the 32 bit big-endian image:\nqemu-system-mips -kernel bin/targets/malta/be/openwrt-malta-be-vmlinux-initramfs.elf -nographic -m 256\n\nFor the 64 bit little-endian image:\nqemu-system-mips64el -kernel bin/targets/malta/le64/openwrt-malta-le64-vmlinux-initramfs.elf -cpu MIPS64R2-generic -nographic -m 256\n\nFor the 64 bit big-endian image:\nqemu-system-mips64 -kernel bin/targets/malta/be64/openwrt-malta-be64-vmlinux-initramfs.elf -cpu MIPS64R2-generic -nographic -m 256\n\nand enjoy the system bootin.\n"
  },
  {
    "path": "target/linux/malta/base-files/etc/board.d/00_model",
    "content": "# Copyright (C) 2015 OpenWrt.org\n\n. /lib/functions/uci-defaults.sh\n\nboard_config_update\n\nucidef_set_board_id \"malta\"\nucidef_set_model_name \"MIPS Malta\"\n\nboard_config_flush\n\nexit 0\n"
  },
  {
    "path": "target/linux/malta/base-files/etc/board.d/02_network",
    "content": "\n. /lib/functions/uci-defaults.sh\n\nboard_config_update\n\nucidef_set_interface_wan \"eth0\"\nif [ -d \"/sys/class/net/eth1\" ]; then\n\tucidef_set_interface_lan \"eth1\"\nfi\n\nboard_config_flush\n\nexit 0\n"
  },
  {
    "path": "target/linux/malta/base-files/etc/inittab",
    "content": "::sysinit:/etc/init.d/rcS S boot\n::shutdown:/etc/init.d/rcS K shutdown\ntts/0::askfirst:/usr/libexec/login.sh\nttyS0::askfirst:/usr/libexec/login.sh\nttyS1::askfirst:/usr/libexec/login.sh\nttyS2::askfirst:/usr/libexec/login.sh\ntty1::askfirst:/usr/libexec/login.sh\n"
  },
  {
    "path": "target/linux/malta/be/config-default",
    "content": "CONFIG_CPU_BIG_ENDIAN=y\n# CONFIG_CPU_LITTLE_ENDIAN is not set\nCONFIG_CPU_MIPS32_R2=y\nCONFIG_HIGHMEM=y\n"
  },
  {
    "path": "target/linux/malta/be/target.mk",
    "content": "ARCH:=mips\nCPU_TYPE:=24kc\nSUBTARGET:=be\nBOARDNAME:=Big Endian\n\ndefine Target/Description\n\tBuild BE firmware images for MIPS Malta CoreLV board running in\n\tbig-endian mode\nendef\n"
  },
  {
    "path": "target/linux/malta/be64/config-default",
    "content": "# CONFIG_32BIT is not set\nCONFIG_64BIT=y\nCONFIG_ARCH_MMAP_RND_BITS=12\nCONFIG_CPU_BIG_ENDIAN=y\n# CONFIG_CPU_LITTLE_ENDIAN is not set\nCONFIG_CPU_MIPS64_R2=y\n# CONFIG_MIPS32_N32 is not set\n# CONFIG_MIPS32_O32 is not set\n# CONFIG_MIPS_VA_BITS_48 is not set\n"
  },
  {
    "path": "target/linux/malta/be64/target.mk",
    "content": "ARCH:=mips64\nCPU_TYPE:=mips64r2\nSUBTARGET:=be64\nFEATURES+=source-only\nBOARDNAME:=Big Endian (64-bits)\n\ndefine Target/Description\n\tBuild BE firmware images for MIPS Malta CoreLV board running in\n\tbig-endian and 64-bits mode\nendef\n"
  },
  {
    "path": "target/linux/malta/config-5.10",
    "content": "CONFIG_ARCH_32BIT_OFF_T=y\nCONFIG_ARCH_MAY_HAVE_PC_FDC=y\nCONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y\nCONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y\nCONFIG_ARCH_MMAP_RND_BITS_MAX=15\nCONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15\nCONFIG_ATA=y\nCONFIG_ATA_PIIX=y\nCONFIG_BLK_DEV_BSG=y\nCONFIG_BLK_DEV_BSGLIB=y\n# CONFIG_BLK_DEV_DM is not set\n# CONFIG_BLK_DEV_INITRD is not set\nCONFIG_BLK_DEV_LOOP=y\n# CONFIG_BLK_DEV_MD is not set\nCONFIG_BLK_DEV_RAM=y\nCONFIG_BLK_DEV_RAM_COUNT=16\nCONFIG_BLK_DEV_RAM_SIZE=4096\nCONFIG_BLK_DEV_SD=y\nCONFIG_BLK_MQ_PCI=y\nCONFIG_BLK_SCSI_REQUEST=y\nCONFIG_BOARD_SCACHE=y\nCONFIG_BOOT_ELF32=y\nCONFIG_BOUNCE=y\nCONFIG_BUILTIN_DTB=y\nCONFIG_CEVT_R4K=y\nCONFIG_CLKBLD_I8253=y\nCONFIG_CLKDEV_LOOKUP=y\nCONFIG_CLKEVT_I8253=y\nCONFIG_CLKSRC_I8253=y\nCONFIG_CLKSRC_MIPS_GIC=y\nCONFIG_CLOCKSOURCE_WATCHDOG=y\nCONFIG_CLONE_BACKWARDS=y\nCONFIG_COMMON_CLK=y\n# CONFIG_COMMON_CLK_BOSTON is not set\nCONFIG_COMPAT_32BIT_TIME=y\nCONFIG_CONSOLE_TRANSLATIONS=y\nCONFIG_CPU_GENERIC_DUMP_TLB=y\nCONFIG_CPU_HAS_PREFETCH=y\n# CONFIG_CPU_HAS_SMARTMIPS is not set\nCONFIG_CPU_HAS_SYNC=y\n# CONFIG_CPU_MICROMIPS is not set\n# CONFIG_CPU_MIPS32 is not set\n# CONFIG_CPU_MIPS32_3_5_FEATURES is not set\n# CONFIG_CPU_MIPS32_R1 is not set\n# CONFIG_CPU_MIPS32_R2 is not set\n# CONFIG_CPU_MIPS32_R5 is not set\n# CONFIG_CPU_MIPS32_R5_FEATURES is not set\n# CONFIG_CPU_MIPS32_R6 is not set\n# CONFIG_CPU_MIPS64_R1 is not set\n# CONFIG_CPU_MIPS64_R2 is not set\n# CONFIG_CPU_MIPS64_R6 is not set\n# CONFIG_CPU_MIPSR2 is not set\n# CONFIG_CPU_MIPSR2_IRQ_EI is not set\n# CONFIG_CPU_MIPSR2_IRQ_VI is not set\nCONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y\n# CONFIG_CPU_NEVADA is not set\nCONFIG_CPU_R4K_CACHE_TLB=y\n# CONFIG_CPU_RM7000 is not set\nCONFIG_CPU_RMAP=y\nCONFIG_CPU_SUPPORTS_32BIT_KERNEL=y\nCONFIG_CPU_SUPPORTS_HIGHMEM=y\nCONFIG_CRC16=y\nCONFIG_CRYPTO_CRC32=y\nCONFIG_CRYPTO_CRC32C=y\nCONFIG_CRYPTO_LIB_POLY1305_RSIZE=2\nCONFIG_CRYPTO_RNG2=y\nCONFIG_CSRC_R4K=y\nCONFIG_DMA_MAYBE_COHERENT=y\nCONFIG_DMA_NONCOHERENT=y\nCONFIG_DNOTIFY=y\nCONFIG_DTC=y\nCONFIG_DUMMY_CONSOLE=y\nCONFIG_ENABLE_MUST_CHECK=y\nCONFIG_EXT4_FS=y\nCONFIG_F2FS_FS=y\nCONFIG_FS_IOMAP=y\nCONFIG_FS_MBCACHE=y\nCONFIG_FS_POSIX_ACL=y\nCONFIG_FW_LOADER_PAGED_BUF=y\nCONFIG_GENERIC_ATOMIC64=y\nCONFIG_GENERIC_CLOCKEVENTS=y\nCONFIG_GENERIC_CMOS_UPDATE=y\nCONFIG_GENERIC_CPU_AUTOPROBE=y\nCONFIG_GENERIC_GETTIMEOFDAY=y\nCONFIG_GENERIC_IOMAP=y\nCONFIG_GENERIC_IRQ_CHIP=y\nCONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y\nCONFIG_GENERIC_IRQ_SHOW=y\nCONFIG_GENERIC_ISA_DMA=y\nCONFIG_GENERIC_LIB_ASHLDI3=y\nCONFIG_GENERIC_LIB_ASHRDI3=y\nCONFIG_GENERIC_LIB_CMPDI2=y\nCONFIG_GENERIC_LIB_LSHRDI3=y\nCONFIG_GENERIC_LIB_UCMPDI2=y\nCONFIG_GENERIC_PCI_IOMAP=y\nCONFIG_GENERIC_SCHED_CLOCK=y\nCONFIG_GENERIC_SMP_IDLE_THREAD=y\nCONFIG_GENERIC_TIME_VSYSCALL=y\nCONFIG_GLOB=y\nCONFIG_HANDLE_DOMAIN_IRQ=y\nCONFIG_HARDWARE_WATCHPOINTS=y\nCONFIG_HAS_DMA=y\nCONFIG_HAS_IOMEM=y\nCONFIG_HAS_IOPORT_MAP=y\nCONFIG_HW_CONSOLE=y\nCONFIG_I8253=y\nCONFIG_I8253_LOCK=y\nCONFIG_I8259=y\nCONFIG_INPUT=y\n# CONFIG_INPUT_MISC is not set\nCONFIG_INPUT_MOUSEDEV=y\nCONFIG_INPUT_MOUSEDEV_PSAUX=y\nCONFIG_INPUT_MOUSEDEV_SCREEN_X=1024\nCONFIG_INPUT_MOUSEDEV_SCREEN_Y=768\nCONFIG_IRQCHIP=y\nCONFIG_IRQ_DOMAIN=y\nCONFIG_IRQ_DOMAIN_HIERARCHY=y\nCONFIG_IRQ_FORCED_THREADING=y\nCONFIG_IRQ_MIPS_CPU=y\nCONFIG_IRQ_WORK=y\nCONFIG_ISA_DMA_API=y\nCONFIG_JBD2=y\nCONFIG_JFFS2_FS_POSIX_ACL=y\nCONFIG_JFFS2_FS_SECURITY=y\nCONFIG_KALLSYMS=y\nCONFIG_KERNEL_GZIP=y\n# CONFIG_KERNEL_XZ is not set\nCONFIG_LIBFDT=y\nCONFIG_LOCK_DEBUGGING_SUPPORT=y\nCONFIG_MD=y\nCONFIG_MEMFD_CREATE=y\nCONFIG_MFD_SYSCON=y\nCONFIG_MIGRATION=y\nCONFIG_MIPS=y\nCONFIG_MIPS_ASID_BITS=8\nCONFIG_MIPS_ASID_SHIFT=0\nCONFIG_MIPS_BONITO64=y\nCONFIG_MIPS_CLOCK_VSYSCALL=y\nCONFIG_MIPS_CM=y\n# CONFIG_MIPS_CMDLINE_DTB_EXTEND is not set\nCONFIG_MIPS_CMDLINE_FROM_BOOTLOADER=y\n# CONFIG_MIPS_CMDLINE_FROM_DTB is not set\n# CONFIG_MIPS_CMP is not set\nCONFIG_MIPS_CPC=y\n# CONFIG_MIPS_CPS is not set\nCONFIG_MIPS_CPU_SCACHE=y\n# CONFIG_MIPS_ELF_APPENDED_DTB is not set\nCONFIG_MIPS_EXTERNAL_TIMER=y\nCONFIG_MIPS_GIC=y\nCONFIG_MIPS_L1_CACHE_SHIFT=6\nCONFIG_MIPS_L1_CACHE_SHIFT_6=y\nCONFIG_MIPS_LD_CAN_LINK_VDSO=y\nCONFIG_MIPS_MALTA=y\nCONFIG_MIPS_MSC=y\nCONFIG_MIPS_MT=y\nCONFIG_MIPS_MT_FPAFF=y\nCONFIG_MIPS_MT_SMP=y\nCONFIG_MIPS_NO_APPENDED_DTB=y\nCONFIG_MIPS_NR_CPU_NR_MAP=2\nCONFIG_MIPS_PERF_SHARED_TC_COUNTERS=y\n# CONFIG_MIPS_RAW_APPENDED_DTB is not set\n# CONFIG_MIPS_VPE_LOADER is not set\nCONFIG_MODULES_USE_ELF_REL=y\nCONFIG_MODULE_FORCE_UNLOAD=y\nCONFIG_MTD_CFI_STAA=y\n# CONFIG_MTD_COMPLEX_MAPPINGS is not set\nCONFIG_NEED_DMA_MAP_STATE=y\nCONFIG_NET_FLOW_LIMIT=y\nCONFIG_NLS=y\nCONFIG_NO_GENERIC_PCI_IOPORT_MAP=y\nCONFIG_NO_HZ=y\nCONFIG_NO_HZ_COMMON=y\nCONFIG_NO_HZ_IDLE=y\nCONFIG_NR_CPUS=2\nCONFIG_NVMEM=y\nCONFIG_OF=y\nCONFIG_OF_ADDRESS=y\nCONFIG_OF_EARLY_FLATTREE=y\nCONFIG_OF_FLATTREE=y\nCONFIG_OF_IRQ=y\nCONFIG_OF_KOBJ=y\nCONFIG_OF_NET=y\nCONFIG_PADATA=y\n# CONFIG_PARTITION_ADVANCED is not set\nCONFIG_PATA_LEGACY=y\nCONFIG_PATA_TIMINGS=y\nCONFIG_PCI=y\nCONFIG_PCI_DOMAINS=y\nCONFIG_PCI_DRIVERS_LEGACY=y\nCONFIG_PCI_GT64XXX_PCI0=y\nCONFIG_PCSPKR_PLATFORM=y\nCONFIG_PERF_USE_VMALLOC=y\nCONFIG_PGTABLE_LEVELS=2\nCONFIG_POWER_RESET=y\nCONFIG_POWER_RESET_PIIX4_POWEROFF=y\nCONFIG_POWER_RESET_SYSCON=y\nCONFIG_PRINT_QUOTA_WARNING=y\nCONFIG_PROC_PAGE_MONITOR=y\n# CONFIG_QFMT_V1 is not set\nCONFIG_QFMT_V2=y\nCONFIG_QUEUED_RWLOCKS=y\nCONFIG_QUEUED_SPINLOCKS=y\nCONFIG_QUOTA=y\nCONFIG_QUOTACTL=y\n# CONFIG_QUOTA_NETLINK_INTERFACE is not set\nCONFIG_QUOTA_TREE=y\nCONFIG_RATIONAL=y\nCONFIG_REGMAP=y\nCONFIG_REGMAP_MMIO=y\nCONFIG_RELAY=y\nCONFIG_RFS_ACCEL=y\nCONFIG_RPS=y\nCONFIG_RTC_CLASS=y\nCONFIG_RTC_MC146818_LIB=y\nCONFIG_SATA_HOST=y\nCONFIG_SCSI=y\nCONFIG_SECCOMP=y\nCONFIG_SECCOMP_FILTER=y\nCONFIG_SERIAL_8250_NR_UARTS=4\nCONFIG_SERIAL_8250_RUNTIME_UARTS=4\nCONFIG_SERIO=y\nCONFIG_SERIO_SERPORT=y\nCONFIG_SG_POOL=y\nCONFIG_SMP=y\nCONFIG_SMP_UP=y\nCONFIG_SRCU=y\nCONFIG_SWAP_IO_SPACE=y\nCONFIG_SYNC_R4K=y\nCONFIG_SYSCTL_EXCEPTION_TRACE=y\nCONFIG_SYSFS_DEPRECATED=y\nCONFIG_SYSFS_DEPRECATED_V2=y\nCONFIG_SYS_HAS_CPU_MIPS32_R1=y\nCONFIG_SYS_HAS_CPU_MIPS32_R2=y\nCONFIG_SYS_HAS_CPU_MIPS32_R3_5=y\nCONFIG_SYS_HAS_CPU_MIPS32_R5=y\nCONFIG_SYS_HAS_CPU_MIPS32_R6=y\nCONFIG_SYS_HAS_CPU_MIPS64_R1=y\nCONFIG_SYS_HAS_CPU_MIPS64_R2=y\nCONFIG_SYS_HAS_CPU_MIPS64_R6=y\nCONFIG_SYS_HAS_CPU_NEVADA=y\nCONFIG_SYS_HAS_CPU_RM7000=y\nCONFIG_SYS_SUPPORTS_32BIT_KERNEL=y\nCONFIG_SYS_SUPPORTS_64BIT_KERNEL=y\nCONFIG_SYS_SUPPORTS_ARBIT_HZ=y\nCONFIG_SYS_SUPPORTS_BIG_ENDIAN=y\nCONFIG_SYS_SUPPORTS_HIGHMEM=y\nCONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y\nCONFIG_SYS_SUPPORTS_MICROMIPS=y\nCONFIG_SYS_SUPPORTS_MIPS16=y\nCONFIG_SYS_SUPPORTS_MIPS_CMP=y\nCONFIG_SYS_SUPPORTS_MIPS_CPS=y\nCONFIG_SYS_SUPPORTS_MULTITHREADING=y\nCONFIG_SYS_SUPPORTS_RELOCATABLE=y\nCONFIG_SYS_SUPPORTS_SCHED_SMT=y\nCONFIG_SYS_SUPPORTS_SMARTMIPS=y\nCONFIG_SYS_SUPPORTS_SMP=y\nCONFIG_SYS_SUPPORTS_VPE_LOADER=y\nCONFIG_SYS_SUPPORTS_ZBOOT=y\nCONFIG_TARGET_ISA_REV=1\nCONFIG_TICK_CPU_ACCOUNTING=y\nCONFIG_TIMER_OF=y\nCONFIG_TIMER_PROBE=y\nCONFIG_TREE_RCU=y\nCONFIG_TREE_SRCU=y\nCONFIG_USB_SUPPORT=y\nCONFIG_USE_OF=y\n# CONFIG_VGA_CONSOLE is not set\nCONFIG_VM_EVENT_COUNTERS=y\nCONFIG_VT=y\nCONFIG_VT_CONSOLE=y\nCONFIG_VT_HW_CONSOLE_BINDING=y\nCONFIG_VXFS_FS=y\nCONFIG_WAR_ICACHE_REFILLS=y\nCONFIG_XPS=y\n"
  },
  {
    "path": "target/linux/malta/config-5.15",
    "content": "CONFIG_ARCH_32BIT_OFF_T=y\nCONFIG_ARCH_KEEP_MEMBLOCK=y\nCONFIG_ARCH_MAY_HAVE_PC_FDC=y\nCONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y\nCONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y\nCONFIG_ARCH_MMAP_RND_BITS_MAX=15\nCONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15\nCONFIG_ATA=y\nCONFIG_ATA_PIIX=y\nCONFIG_BLK_DEV_BSG=y\nCONFIG_BLK_DEV_BSGLIB=y\nCONFIG_BLK_DEV_BSG_COMMON=y\n# CONFIG_BLK_DEV_INITRD is not set\nCONFIG_BLK_DEV_LOOP=y\nCONFIG_BLK_DEV_RAM=y\nCONFIG_BLK_DEV_RAM_COUNT=16\nCONFIG_BLK_DEV_RAM_SIZE=4096\nCONFIG_BLK_DEV_SD=y\nCONFIG_BLK_MQ_PCI=y\nCONFIG_BOARD_SCACHE=y\nCONFIG_BOOT_ELF32=y\nCONFIG_BUILTIN_DTB=y\nCONFIG_CEVT_R4K=y\nCONFIG_CLKBLD_I8253=y\nCONFIG_CLKEVT_I8253=y\nCONFIG_CLKSRC_I8253=y\nCONFIG_CLKSRC_MIPS_GIC=y\nCONFIG_CLOCKSOURCE_WATCHDOG=y\nCONFIG_CLONE_BACKWARDS=y\nCONFIG_COMMON_CLK=y\nCONFIG_COMPAT_32BIT_TIME=y\nCONFIG_CONSOLE_TRANSLATIONS=y\nCONFIG_CPU_GENERIC_DUMP_TLB=y\nCONFIG_CPU_HAS_PREFETCH=y\n# CONFIG_CPU_HAS_SMARTMIPS is not set\nCONFIG_CPU_HAS_SYNC=y\n# CONFIG_CPU_MICROMIPS is not set\n# CONFIG_CPU_MIPS32 is not set\n# CONFIG_CPU_MIPS32_3_5_FEATURES is not set\n# CONFIG_CPU_MIPS32_R1 is not set\n# CONFIG_CPU_MIPS32_R2 is not set\n# CONFIG_CPU_MIPS32_R5 is not set\n# CONFIG_CPU_MIPS32_R5_FEATURES is not set\n# CONFIG_CPU_MIPS32_R6 is not set\n# CONFIG_CPU_MIPS64_R1 is not set\n# CONFIG_CPU_MIPS64_R2 is not set\n# CONFIG_CPU_MIPS64_R6 is not set\n# CONFIG_CPU_MIPSR1 is not set\n# CONFIG_CPU_MIPSR2 is not set\n# CONFIG_CPU_MIPSR2_IRQ_EI is not set\n# CONFIG_CPU_MIPSR2_IRQ_VI is not set\nCONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y\n# CONFIG_CPU_NEVADA is not set\nCONFIG_CPU_R4K_CACHE_TLB=y\n# CONFIG_CPU_RM7000 is not set\nCONFIG_CPU_RMAP=y\nCONFIG_CPU_SUPPORTS_32BIT_KERNEL=y\nCONFIG_CPU_SUPPORTS_HIGHMEM=y\nCONFIG_CRC16=y\nCONFIG_CRYPTO_CRC32=y\nCONFIG_CRYPTO_CRC32C=y\nCONFIG_CRYPTO_LIB_POLY1305_RSIZE=2\nCONFIG_CRYPTO_RNG2=y\nCONFIG_CSRC_R4K=y\nCONFIG_DMA_NONCOHERENT=y\nCONFIG_DNOTIFY=y\nCONFIG_DTC=y\nCONFIG_DUMMY_CONSOLE=y\nCONFIG_EXT4_FS=y\nCONFIG_F2FS_FS=y\nCONFIG_FS_IOMAP=y\nCONFIG_FS_MBCACHE=y\nCONFIG_FS_POSIX_ACL=y\nCONFIG_FW_LOADER_PAGED_BUF=y\nCONFIG_GENERIC_ATOMIC64=y\nCONFIG_GENERIC_CLOCKEVENTS=y\nCONFIG_GENERIC_CMOS_UPDATE=y\nCONFIG_GENERIC_CPU_AUTOPROBE=y\nCONFIG_GENERIC_FIND_FIRST_BIT=y\nCONFIG_GENERIC_GETTIMEOFDAY=y\nCONFIG_GENERIC_IOMAP=y\nCONFIG_GENERIC_IRQ_CHIP=y\nCONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y\nCONFIG_GENERIC_IRQ_SHOW=y\nCONFIG_GENERIC_ISA_DMA=y\nCONFIG_GENERIC_LIB_ASHLDI3=y\nCONFIG_GENERIC_LIB_ASHRDI3=y\nCONFIG_GENERIC_LIB_CMPDI2=y\nCONFIG_GENERIC_LIB_LSHRDI3=y\nCONFIG_GENERIC_LIB_UCMPDI2=y\nCONFIG_GENERIC_PCI_IOMAP=y\nCONFIG_GENERIC_SCHED_CLOCK=y\nCONFIG_GENERIC_SMP_IDLE_THREAD=y\nCONFIG_GENERIC_TIME_VSYSCALL=y\nCONFIG_GLOB=y\nCONFIG_HANDLE_DOMAIN_IRQ=y\nCONFIG_HARDWARE_WATCHPOINTS=y\nCONFIG_HAS_DMA=y\nCONFIG_HAS_IOMEM=y\nCONFIG_HAS_IOPORT_MAP=y\nCONFIG_HW_CONSOLE=y\nCONFIG_I8253=y\nCONFIG_I8253_LOCK=y\nCONFIG_I8259=y\nCONFIG_INPUT=y\n# CONFIG_INPUT_MISC is not set\nCONFIG_INPUT_MOUSEDEV=y\nCONFIG_INPUT_MOUSEDEV_PSAUX=y\nCONFIG_INPUT_MOUSEDEV_SCREEN_X=1024\nCONFIG_INPUT_MOUSEDEV_SCREEN_Y=768\nCONFIG_IRQCHIP=y\nCONFIG_IRQ_DOMAIN=y\nCONFIG_IRQ_DOMAIN_HIERARCHY=y\nCONFIG_IRQ_FORCED_THREADING=y\nCONFIG_IRQ_MIPS_CPU=y\nCONFIG_IRQ_WORK=y\nCONFIG_ISA_DMA_API=y\nCONFIG_JBD2=y\nCONFIG_JFFS2_FS_POSIX_ACL=y\nCONFIG_JFFS2_FS_SECURITY=y\nCONFIG_KALLSYMS=y\nCONFIG_KERNEL_GZIP=y\n# CONFIG_KERNEL_XZ is not set\nCONFIG_LIBFDT=y\nCONFIG_LOCK_DEBUGGING_SUPPORT=y\nCONFIG_MD=y\nCONFIG_MEMFD_CREATE=y\nCONFIG_MFD_SYSCON=y\nCONFIG_MIGRATION=y\nCONFIG_MIPS=y\nCONFIG_MIPS_ASID_BITS=8\nCONFIG_MIPS_ASID_SHIFT=0\nCONFIG_MIPS_BONITO64=y\nCONFIG_MIPS_CLOCK_VSYSCALL=y\nCONFIG_MIPS_CM=y\nCONFIG_MIPS_CMDLINE_FROM_BOOTLOADER=y\nCONFIG_MIPS_CPC=y\nCONFIG_MIPS_CPU_SCACHE=y\nCONFIG_MIPS_EBPF_JIT=y\nCONFIG_MIPS_EXTERNAL_TIMER=y\nCONFIG_MIPS_GIC=y\nCONFIG_MIPS_L1_CACHE_SHIFT=6\nCONFIG_MIPS_L1_CACHE_SHIFT_6=y\nCONFIG_MIPS_LD_CAN_LINK_VDSO=y\nCONFIG_MIPS_MALTA=y\nCONFIG_MIPS_MSC=y\nCONFIG_MIPS_MT=y\nCONFIG_MIPS_MT_FPAFF=y\nCONFIG_MIPS_MT_SMP=y\nCONFIG_MIPS_NO_APPENDED_DTB=y\nCONFIG_MIPS_NR_CPU_NR_MAP=2\nCONFIG_MIPS_PERF_SHARED_TC_COUNTERS=y\nCONFIG_MODULES_USE_ELF_REL=y\nCONFIG_MODULE_FORCE_UNLOAD=y\nCONFIG_MTD_CFI_STAA=y\n# CONFIG_MTD_COMPLEX_MAPPINGS is not set\nCONFIG_NEED_DMA_MAP_STATE=y\nCONFIG_NET_FLOW_LIMIT=y\nCONFIG_NLS=y\nCONFIG_NO_GENERIC_PCI_IOPORT_MAP=y\nCONFIG_NO_HZ=y\nCONFIG_NO_HZ_COMMON=y\nCONFIG_NO_HZ_IDLE=y\nCONFIG_NR_CPUS=2\nCONFIG_NVMEM=y\nCONFIG_OF=y\nCONFIG_OF_ADDRESS=y\nCONFIG_OF_EARLY_FLATTREE=y\nCONFIG_OF_FLATTREE=y\nCONFIG_OF_IRQ=y\nCONFIG_OF_KOBJ=y\nCONFIG_PADATA=y\n# CONFIG_PARTITION_ADVANCED is not set\nCONFIG_PATA_LEGACY=y\nCONFIG_PATA_TIMINGS=y\nCONFIG_PCI=y\nCONFIG_PCI_DOMAINS=y\nCONFIG_PCI_DRIVERS_LEGACY=y\nCONFIG_PCI_GT64XXX_PCI0=y\nCONFIG_PCSPKR_PLATFORM=y\nCONFIG_PERF_USE_VMALLOC=y\nCONFIG_PGTABLE_LEVELS=2\nCONFIG_POWER_RESET=y\nCONFIG_POWER_RESET_PIIX4_POWEROFF=y\nCONFIG_POWER_RESET_SYSCON=y\nCONFIG_PRINT_QUOTA_WARNING=y\nCONFIG_PROC_PAGE_MONITOR=y\nCONFIG_PTP_1588_CLOCK_OPTIONAL=y\nCONFIG_QFMT_V2=y\nCONFIG_QUEUED_RWLOCKS=y\nCONFIG_QUEUED_SPINLOCKS=y\nCONFIG_QUOTA=y\nCONFIG_QUOTACTL=y\nCONFIG_QUOTA_TREE=y\nCONFIG_RATIONAL=y\nCONFIG_REGMAP=y\nCONFIG_REGMAP_MMIO=y\nCONFIG_RELAY=y\nCONFIG_RFS_ACCEL=y\nCONFIG_RPS=y\nCONFIG_RTC_CLASS=y\nCONFIG_RTC_MC146818_LIB=y\nCONFIG_SATA_HOST=y\nCONFIG_SCSI=y\nCONFIG_SCSI_COMMON=y\nCONFIG_SECCOMP=y\nCONFIG_SECCOMP_FILTER=y\nCONFIG_SERIAL_8250_NR_UARTS=4\nCONFIG_SERIAL_8250_RUNTIME_UARTS=4\nCONFIG_SERIO=y\nCONFIG_SERIO_SERPORT=y\nCONFIG_SG_POOL=y\nCONFIG_SMP=y\nCONFIG_SMP_UP=y\nCONFIG_SOCK_RX_QUEUE_MAPPING=y\nCONFIG_SRCU=y\nCONFIG_SWAP_IO_SPACE=y\nCONFIG_SYNC_R4K=y\nCONFIG_SYSCTL_EXCEPTION_TRACE=y\nCONFIG_SYSFS_DEPRECATED=y\nCONFIG_SYSFS_DEPRECATED_V2=y\nCONFIG_SYS_HAS_CPU_MIPS32_R1=y\nCONFIG_SYS_HAS_CPU_MIPS32_R2=y\nCONFIG_SYS_HAS_CPU_MIPS32_R3_5=y\nCONFIG_SYS_HAS_CPU_MIPS32_R5=y\nCONFIG_SYS_HAS_CPU_MIPS32_R6=y\nCONFIG_SYS_HAS_CPU_MIPS64_R1=y\nCONFIG_SYS_HAS_CPU_MIPS64_R2=y\nCONFIG_SYS_HAS_CPU_MIPS64_R6=y\nCONFIG_SYS_HAS_CPU_NEVADA=y\nCONFIG_SYS_HAS_CPU_RM7000=y\nCONFIG_SYS_SUPPORTS_32BIT_KERNEL=y\nCONFIG_SYS_SUPPORTS_64BIT_KERNEL=y\nCONFIG_SYS_SUPPORTS_ARBIT_HZ=y\nCONFIG_SYS_SUPPORTS_BIG_ENDIAN=y\nCONFIG_SYS_SUPPORTS_HIGHMEM=y\nCONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y\nCONFIG_SYS_SUPPORTS_MICROMIPS=y\nCONFIG_SYS_SUPPORTS_MIPS16=y\nCONFIG_SYS_SUPPORTS_MIPS_CMP=y\nCONFIG_SYS_SUPPORTS_MIPS_CPS=y\nCONFIG_SYS_SUPPORTS_MULTITHREADING=y\nCONFIG_SYS_SUPPORTS_RELOCATABLE=y\nCONFIG_SYS_SUPPORTS_SCHED_SMT=y\nCONFIG_SYS_SUPPORTS_SMARTMIPS=y\nCONFIG_SYS_SUPPORTS_SMP=y\nCONFIG_SYS_SUPPORTS_VPE_LOADER=y\nCONFIG_SYS_SUPPORTS_ZBOOT=y\nCONFIG_TARGET_ISA_REV=1\nCONFIG_TICK_CPU_ACCOUNTING=y\nCONFIG_TIMER_OF=y\nCONFIG_TIMER_PROBE=y\nCONFIG_TREE_RCU=y\nCONFIG_TREE_SRCU=y\nCONFIG_USB_SUPPORT=y\nCONFIG_USE_OF=y\nCONFIG_VM_EVENT_COUNTERS=y\nCONFIG_VT=y\nCONFIG_VT_CONSOLE=y\nCONFIG_VT_HW_CONSOLE_BINDING=y\nCONFIG_VXFS_FS=y\nCONFIG_WAR_ICACHE_REFILLS=y\nCONFIG_XPS=y\n"
  },
  {
    "path": "target/linux/malta/image/Makefile",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2010 OpenWrt.org\n\ninclude $(TOPDIR)/rules.mk\ninclude $(INCLUDE_DIR)/image.mk\n\ndefine CompressLzma\n  $(STAGING_DIR_HOST)/bin/lzma e $(1) -lc1 -lp2 -pb2 $(2)\nendef\n\ndefine CompressGzip\n\tgzip -9n -c $(1) > $(2)\nendef\n\ndefine MkuImage\n\tmkimage -A mips -O linux -T kernel -a 0x80100000 -C $(1) $(2) \\\n\t\t-e 0x80100000 -n 'MIPS OpenWrt Linux-$(LINUX_VERSION)' \\\n\t\t-d $(3) $(4)\nendef\n\ndefine Image/Prepare\n\t$(call CompressLzma,$(KDIR)/vmlinux,$(KDIR)/vmlinux.bin.lzma)\n\t$(call MkuImage,lzma,,$(KDIR)/vmlinux.bin.lzma,$(KDIR)/uImage.lzma)\n\t$(call CompressGzip,$(KDIR)/vmlinux,$(KDIR)/vmlinux.bin.gz)\n\t$(call MkuImage,gzip,,$(KDIR)/vmlinux.bin.gz,$(KDIR)/uImage.gz)\nendef\n\ndefine Image/BuildKernel\n\tcp $(KDIR)/vmlinux.elf $(BIN_DIR)/$(IMG_PREFIX)-vmlinux.elf\n\tcp $(KDIR)/uImage.lzma $(BIN_DIR)/$(IMG_PREFIX)-uImage-lzma\n\tcp $(KDIR)/uImage.gz $(BIN_DIR)/$(IMG_PREFIX)-uImage-gzip\nendef\n\ndefine Image/Build/Initramfs\n\tcp $(KDIR)/vmlinux-initramfs.elf $(BIN_DIR)/$(IMG_PREFIX)-vmlinux-initramfs.elf\n\tcp $(KDIR)/vmlinux-initramfs $(BIN_DIR)/$(IMG_PREFIX)-vmlinux-initramfs.bin\nendef\n\ndefine Image/Build/gzip\n\tgzip -f9n $(BIN_DIR)/$(IMG_ROOTFS)-$(1).img\nendef\n\n$(eval $(call Image/gzip-ext4-padded-squashfs))\n\ndefine Image/Build\n\t$(call Image/Build/$(1))\n\t$(CP) $(KDIR)/root.$(1) $(BIN_DIR)/$(IMG_ROOTFS)-$(1).img\n\t$(call Image/Build/gzip/$(1))\nendef\n\n$(eval $(call BuildImage))\n"
  },
  {
    "path": "target/linux/malta/le/config-default",
    "content": "CONFIG_CPU_LITTLE_ENDIAN=y\nCONFIG_CPU_MIPS32_R2=y\nCONFIG_HIGHMEM=y\n"
  },
  {
    "path": "target/linux/malta/le/target.mk",
    "content": "ARCH:=mipsel\nCPU_TYPE:=24kc\nSUBTARGET:=le\nFEATURES+=source-only\nBOARDNAME:=Little Endian\n\ndefine Target/Description\n\tBuild LE firmware images for MIPS Malta CoreLV board running in\n\tlittle-endian mode\nendef\n"
  },
  {
    "path": "target/linux/malta/le64/config-default",
    "content": "# CONFIG_32BIT is not set\nCONFIG_64BIT=y\nCONFIG_ARCH_MMAP_RND_BITS=12\nCONFIG_CPU_LITTLE_ENDIAN=y\nCONFIG_CPU_MIPS64_R2=y\n# CONFIG_MIPS32_N32 is not set\n# CONFIG_MIPS32_O32 is not set\n# CONFIG_MIPS_VA_BITS_48 is not set\n"
  },
  {
    "path": "target/linux/malta/le64/target.mk",
    "content": "ARCH:=mips64el\nCPU_TYPE:=mips64r2\nSUBTARGET:=le64\nFEATURES+=source-only\nBOARDNAME:=Little Endian (64-bits)\n\ndefine Target/Description\n\tBuild LE firmware images for MIPS Malta CoreLV board running in\n\tlittle-endian and 64-bits mode\nendef\n"
  },
  {
    "path": "target/linux/mediatek/Makefile",
    "content": "# Copyright (c) 2015 OpenWrt.org\n#\ninclude $(TOPDIR)/rules.mk\n\nARCH:=arm\nBOARD:=mediatek\nBOARDNAME:=MediaTek Ralink ARM\nSUBTARGETS:=mt7622 mt7623 mt7629\nFEATURES:=dt-overlay emmc fpu gpio nand pci pcie rootfs-part separate_ramdisk squashfs usb\n\nKERNEL_PATCHVER:=5.15\n\ninclude $(INCLUDE_DIR)/target.mk\nDEFAULT_PACKAGES += \\\n\tkmod-leds-gpio kmod-gpio-button-hotplug\n\n$(eval $(call BuildTarget))\n"
  },
  {
    "path": "target/linux/mediatek/base-files/etc/hotplug.d/iface/99-mtk-lro",
    "content": "[ ifup = \"$ACTION\" ] && {\n\t[ -n \"$DEVICE\" ] && {\n\t\tif [ \"$INTERFACE\" == \"lan\" ]; then\n\t\t\tif [ -f /usr/sbin/ethtool ]; then\n\t\t\t\tifname=eth0\n\t\t\t\tlan_ip=`uci -q get network.lan.ipaddr`\n\t\t\t\tethdrv=`ethtool -i $ifname | grep mtk_soc_eth`\n\t\t\t\t[ -n \"$ethdrv\" ] && {\n\t\t\t\t\tethtool -N $ifname flow-type tcp4 dst-ip $lan_ip loc 0\n\t\t\t\t}\n\t\t\tfi\n\t\tfi\n\t}\n}\n"
  },
  {
    "path": "target/linux/mediatek/base-files/etc/inittab",
    "content": "::sysinit:/etc/init.d/rcS S boot\n::shutdown:/etc/init.d/rcS K shutdown\n::askconsole:/usr/libexec/login.sh\n"
  },
  {
    "path": "target/linux/mediatek/base-files/etc/uci-defaults/99_fwenv-store-ethaddr.sh",
    "content": "[ ! -e /etc/fw_env.config ] && exit 0\n\n. /lib/functions.sh\n\ncase \"$(board_name)\" in\nbananapi,bpi-r2|\\\nbananapi,bpi-r64|\\\nunielec,u7623-02)\n\t[ -z \"$(fw_printenv -n ethaddr 2>/dev/null)\" ] &&\n\t\tfw_setenv ethaddr \"$(cat /sys/class/net/eth0/address)\"\n\t;;\nesac\n\nexit 0\n"
  },
  {
    "path": "target/linux/mediatek/base-files/lib/preinit/05_set_preinit_iface",
    "content": "set_preinit_iface() {\n\tip link set eth0 up\n\n\tcase $(board_name) in\n\tubnt,unifi-6-lr)\n\t\tifname=eth0\n\t\t;;\n\t*)\n\t\tifname=lan1\n\t\t;;\n\tesac\n}\n\nboot_hook_add preinit_main set_preinit_iface\n\n"
  },
  {
    "path": "target/linux/mediatek/base-files/lib/preinit/06_set_rps_sock_flow",
    "content": "set_rps_sock_flow() {\n\techo 1024 > /proc/sys/net/core/rps_sock_flow_entries\n}\n\nboot_hook_add preinit_main set_rps_sock_flow\n\n"
  },
  {
    "path": "target/linux/mediatek/dts/mt7622-buffalo-wsr-2533dhp2.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n/dts-v1/;\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/gpio/gpio.h>\n\n#include \"mt7622.dtsi\"\n#include \"mt6380.dtsi\"\n\n/ {\n\tmodel = \"Buffalo WSR-2533DHP2\";\n\tcompatible = \"buffalo,wsr-2533dhp2\", \"mediatek,mt7622\";\n\n\taliases {\n\t\tserial0 = &uart0;\n\t\tled-boot = &power_green;\n\t\tled-failsafe = &power_amber;\n\t\tled-running = &power_green;\n\t\tled-upgrade = &power_green;\n\t};\n\n\tchosen {\n\t\tbootargs = \"earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n8 swiotlb=512\";\n\t};\n\n\tmemory {\n\t\treg = <0 0x40000000 0 0x0F000000>;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twireless_amber {\n\t\t\tlabel = \"amber:wireless\";\n\t\t\tgpios = <&pio 2 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tpower_amber: power_amber {\n\t\t\tlabel = \"amber:power\";\n\t\t\tgpios = <&pio 3 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tpower_green: power_green {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&pio 4 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\twireless_green {\n\t\t\tlabel = \"green:wireless\";\n\t\t\tgpios = <&pio 15 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tinternet {\n\t\t\tlabel = \"green:internet\";\n\t\t\tgpios = <&pio 19 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\trouter {\n\t\t\tlabel = \"green:router\";\n\t\t\tgpios = <&pio 20 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\t\tpoll-interval = <100>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&pio 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\t/* GPIO 1 and 16 are a tri-state switch button with\n\t\t * ROUTER / AP / WB.\n\t\t */\n\t\trouter {\n\t\t\tlabel = \"router\";\n\t\t\tgpios = <&pio 1 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_0>;\n\t\t\tlinux,input-type = <EV_SW>;\n\t\t};\n\n\t\tbridge {\n\t\t\tlabel = \"wb\";\n\t\t\tgpios = <&pio 16 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_1>;\n\t\t\tlinux,input-type = <EV_SW>;\n\t\t};\n\n\t\t/* GPIO 18 is a switch button with AUTO / MANUAL. */\n\t\tmanual {\n\t\t\tlabel = \"manual\";\n\t\t\tgpios = <&pio 18 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_2>;\n\t\t\tlinux,input-type = <EV_SW>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&pio 102 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n\n\trtkgsw: rtkgsw@0 {\n\t\tcompatible = \"mediatek,rtk-gsw\";\n\t\tmediatek,ethsys = <&ethsys>;\n\t\tmediatek,mdio = <&mdio>;\n\t\tmediatek,reset-pin = <&pio 54 GPIO_ACTIVE_HIGH>;\n\t};\n};\n\n&cpu0 {\n\tproc-supply = <&mt6380_vcpu_reg>;\n\tsram-supply = <&mt6380_vm_reg>;\n};\n\n&cpu1 {\n\tproc-supply = <&mt6380_vcpu_reg>;\n\tsram-supply = <&mt6380_vm_reg>;\n};\n\n&pcie0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pcie0_pins>;\n\tstatus = \"okay\";\n};\n\n&slot0 {\n\tstatus = \"okay\";\n\n\twifi@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x5000>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\t};\n};\n\n&pio {\n\teth_pins: eth-pins {\n\t\tmux {\n\t\t\tfunction = \"eth\";\n\t\t\tgroups = \"mdc_mdio\", \"rgmii_via_gmac2\";\n\t\t};\n\t};\n\n\t/* Parallel nand is shared pin with eMMC */\n\tparallel_nand_pins: parallel-nand-pins {\n\t\tmux {\n\t\t\tfunction = \"flash\";\n\t\t\tgroups = \"par_nand\";\n\t\t};\n\n\t\tconf-cmd-dat {\n\t\t\tpins = \"NCEB\", \"NWEB\", \"NREB\",\n\t\t\t\t  \"NDL4\", \"NDL5\", \"NDL6\",\n\t\t\t\t  \"NDL7\", \"NRB\", \"NCLE\",\n\t\t\t\t  \"NALE\", \"NDL0\", \"NDL1\",\n\t\t\t\t  \"NDL2\", \"NDL3\";\n\t\t\tinput-enable;\n\t\t\tdrive-strength = <8>;\n\t\t\tbias-pull-up;\n\t\t};\n\t};\n\n\tpcie0_pins: pcie0-pins {\n\t\tmux {\n\t\t\tfunction = \"pcie\";\n\t\t\tgroups = \"pcie0_pad_perst\",\n\t\t\t\t \"pcie0_1_waken\",\n\t\t\t\t \"pcie0_1_clkreq\";\n\t\t};\n\t};\n\n\tpmic_bus_pins: pmic-bus-pins {\n\t\tmux {\n\t\t\tfunction = \"pmic\";\n\t\t\tgroups = \"pmic_bus\";\n\t\t};\n\t};\n\n\tpwm7_pins: pwm1-2-pins {\n\t\tmux {\n\t\t\tfunction = \"pwm\";\n\t\t\tgroups = \"pwm_ch7_2\";\n\t\t};\n\t};\n\n\tuart0_pins: uart0-pins {\n\t\tmux {\n\t\t\tfunction = \"uart\";\n\t\t\tgroups = \"uart0_0_tx_rx\" ;\n\t\t};\n\t};\n\n\twatchdog_pins: watchdog-pins {\n\t\tmux {\n\t\t\tfunction = \"watchdog\";\n\t\t\tgroups = \"watchdog\";\n\t\t};\n\t};\n};\n\n&bch {\n\tstatus = \"okay\";\n};\n\n&eth {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&eth_pins>;\n\tstatus = \"okay\";\n\n\tgmac0: mac@0 {\n\t\tcompatible = \"mediatek,eth-mac\";\n\t\treg = <0>;\n\n\t\tphy-connection-type = \"2500base-x\";\n\n\t\tnvmem-cells = <&macaddr_factory_4>;\n\t\tnvmem-cell-names = \"mac-address\";\n\t\tmac-address-increment = <(-1)>;\n\n\t\tfixed-link {\n\t\t\tspeed = <2500>;\n\t\t\tfull-duplex;\n\t\t\tpause;\n\t\t};\n\t};\n\n\tmdio: mdio-bus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t};\n};\n\n&nandc {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&parallel_nand_pins>;\n\tstatus = \"okay\";\n\n\tnand@0 {\n\t\treg = <0>;\n\t\tnand-ecc-mode = \"hw\";\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"Preloader\";\n\t\t\t\treg = <0x0 0x80000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@80000 {\n\t\t\t\tlabel = \"ATF\";\n\t\t\t\treg = <0x80000 0x40000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@c0000 {\n\t\t\t\tlabel = \"Bootloader\";\n\t\t\t\treg = <0xc0000 0x80000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@140000 {\n\t\t\t\tlabel = \"Config\";\n\t\t\t\treg = <0x140000 0x80000>;\n\t\t\t};\n\n\t\t\tfactory: partition@1c0000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x1c0000 0x40000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@200000 {\n\t\t\t\tcompatible = \"brcm,trx\";\n\t\t\t\tbrcm,trx-magic = <0x32504844>;\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x200000 0x3a00000>;\n\t\t\t};\n\n\t\t\tpartition@3C00000 {\n\t\t\t\tlabel = \"Kernel2\";\n\t\t\t\treg = <0x3c00000 0x3a00000>;\n\t\t\t};\n\n\t\t\tpartition@7600000 {\n\t\t\t\tlabel = \"glbcfg\";\n\t\t\t\treg = <0x7600000 0x200000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@7800000 {\n\t\t\t\tlabel = \"board_data\";\n\t\t\t\treg = <0x7800000 0x200000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pwm {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pwm7_pins>;\n\tstatus = \"okay\";\n};\n\n&pwrap {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pmic_bus_pins>;\n\tstatus = \"okay\";\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&uart0_pins>;\n\tstatus = \"okay\";\n};\n\n&watchdog {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&watchdog_pins>;\n\tstatus = \"okay\";\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmediatek,mtd-eeprom = <&factory 0x0>;\n};\n\n&rtc {\n\tstatus = \"disabled\";\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/mediatek/dts/mt7622-elecom-wrc-2533gent.dts",
    "content": "// SPDX-License-Identifier: (GPL-2.0-only OR MIT)\n/*\n * Copyright (c) 2017 MediaTek Inc.\n * Author: Ming Huang <ming.huang@mediatek.com>\n *\t   Sean Wang <sean.wang@mediatek.com>\n */\n\n/dts-v1/;\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/gpio/gpio.h>\n\n#include \"mt7622.dtsi\"\n#include \"mt6380.dtsi\"\n\n/ {\n\tmodel = \"Elecom WRC-2533\";\n\tcompatible = \"elecom,wrc-2533gent\", \"mediatek,mt7622\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t\tserial0 = &uart0;\n\t};\n\n\tchosen {\n\t\tstdout-path = \"serial0:115200n8\";\n\t\tbootargs = \"earlycon=uart8250,mmio32,0x11002000 swiotlb=512 console=ttyS0,115200n8\";\n\t};\n\n\tcpus {\n\t\tcpu@0 {\n\t\t\tproc-supply = <&mt6380_vcpu_reg>;\n\t\t\tsram-supply = <&mt6380_vm_reg>;\n\t\t};\n\n\t\tcpu@1 {\n\t\t\tproc-supply = <&mt6380_vcpu_reg>;\n\t\t\tsram-supply = <&mt6380_vm_reg>;\n\t\t};\n\t};\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tpoll-interval = <100>;\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tgpios = <&pio 0 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tfactory {\n\t\t\tlabel = \"factory\";\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tgpios = <&pio 102 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tswitch0 {\n\t\t\tlabel = \"switch0\";\n\t\t\tgpios = <&pio 1 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_0>;\n\t\t\tlinux,input-type = <EV_SW>;\n\t\t};\n\n\t\tswitch1 {\n\t\t\tlabel = \"switch1\";\n\t\t\tgpios = <&pio 16 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_1>;\n\t\t\tlinux,input-type = <EV_SW>;\n\t\t};\n\n\t\tswitch2 {\n\t\t\tlabel = \"switch2\";\n\t\t\tgpios = <&pio 17 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_2>;\n\t\t\tlinux,input-type = <EV_SW>;\n\t\t};\n\n\t\tswitch3 {\n\t\t\tlabel = \"switch3\";\n\t\t\tgpios = <&pio 18 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_3>;\n\t\t\tlinux,input-type = <EV_SW>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power_g {\n\t\t\tlabel = \"wrc-2533:green:power\";\n\t\t\tgpios = <&pio 2 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tpower_b {\n\t\t\tlabel = \"wrc-2533:blue:power\";\n\t\t\tgpios = <&pio 19 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tpower_r {\n\t\t\tlabel = \"wrc-2533:red:power\";\n\t\t\tgpios = <&pio 73 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tusb {\n\t\t\tlabel = \"wrc-2533:blue:usb\";\n\t\t\tgpios = <&pio 74 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wrc-2533:red:wps\";\n\t\t\tgpios = <&pio 76 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twifi2 {\n\t\t\tlabel = \"wrc-2533:blue:wifi2g\";\n\t\t\tgpios = <&pio 85 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twifi5 {\n\t\t\tlabel = \"wrc-2533:blue:wifi5g\";\n\t\t\tgpios = <&pio 91 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\treg_usb_vbus: regulator {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"usb_vbus\";\n\t\tregulator-min-microvolt = <5000000>;\n\t\tregulator-max-microvolt = <5000000>;\n\t\tgpio = <&pio 22 GPIO_ACTIVE_LOW>;\n\t\tenable-active-high;\n\t};\n\n\tmemory {\n\t\treg = <0 0x40000000 0 0x3F000000>;\n\t};\n\n\treg_1p8v: regulator-1p8v {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"fixed-1.8V\";\n\t\tregulator-min-microvolt = <1800000>;\n\t\tregulator-max-microvolt = <1800000>;\n\t\tregulator-always-on;\n\t};\n\n\treg_3p3v: regulator-3p3v {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"fixed-3.3V\";\n\t\tregulator-min-microvolt = <3300000>;\n\t\tregulator-max-microvolt = <3300000>;\n\t\tregulator-boot-on;\n\t\tregulator-always-on;\n\t};\n\n\trtkgsw: rtkgsw@0 {\n\t\tcompatible = \"mediatek,rtk-gsw\";\n\t\tmediatek,ethsys = <&ethsys>;\n\t\tmediatek,mdio = <&mdio>;\n\t\tmediatek,reset-pin = <&pio 54 0>;\n\t\tstatus = \"okay\";\n\t};\n};\n\n&pcie0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pcie0_pins>;\n\tstatus = \"okay\";\n};\n\n&slot0 {\n\tmt7615@0,0 {\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x05000>;\n\t};\n};\n\n&pio {\n\t/* eMMC is shared pin with parallel NAND */\n\temmc_pins_default: emmc-pins-default {\n\t\tmux {\n\t\t\tfunction = \"emmc\", \"emmc_rst\";\n\t\t\tgroups = \"emmc\";\n\t\t};\n\n\t\t/* \"NDL0\",\"NDL1\",\"NDL2\",\"NDL3\",\"NDL4\",\"NDL5\",\"NDL6\",\"NDL7\",\n\t\t * \"NRB\",\"NCLE\" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4,\n\t\t * DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively\n\t\t */\n\t\tconf-cmd-dat {\n\t\t\tpins = \"NDL0\", \"NDL1\", \"NDL2\",\n\t\t\t       \"NDL3\", \"NDL4\", \"NDL5\",\n\t\t\t       \"NDL6\", \"NDL7\", \"NRB\";\n\t\t\tinput-enable;\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-clk {\n\t\t\tpins = \"NCLE\";\n\t\t\tbias-pull-down;\n\t\t};\n\t};\n\n\temmc_pins_uhs: emmc-pins-uhs {\n\t\tmux {\n\t\t\tfunction = \"emmc\";\n\t\t\tgroups = \"emmc\";\n\t\t};\n\n\t\tconf-cmd-dat {\n\t\t\tpins = \"NDL0\", \"NDL1\", \"NDL2\",\n\t\t\t       \"NDL3\", \"NDL4\", \"NDL5\",\n\t\t\t       \"NDL6\", \"NDL7\", \"NRB\";\n\t\t\tinput-enable;\n\t\t\tdrive-strength = <4>;\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-clk {\n\t\t\tpins = \"NCLE\";\n\t\t\tdrive-strength = <4>;\n\t\t\tbias-pull-down;\n\t\t};\n\t};\n\n\teth_pins: eth-pins {\n\t\tmux {\n\t\t\tfunction = \"eth\";\n\t\t\tgroups = \"mdc_mdio\", \"rgmii_via_gmac2\";\n\t\t};\n\t};\n\n\ti2c1_pins: i2c1-pins {\n\t\tmux {\n\t\t\tfunction = \"i2c\";\n\t\t\tgroups =  \"i2c1_0\";\n\t\t};\n\t};\n\n\ti2c2_pins: i2c2-pins {\n\t\tmux {\n\t\t\tfunction = \"i2c\";\n\t\t\tgroups =  \"i2c2_0\";\n\t\t};\n\t};\n\n\ti2s1_pins: i2s1-pins {\n\t\tmux {\n\t\t\tfunction = \"i2s\";\n\t\t\tgroups =  \"i2s_out_mclk_bclk_ws\",\n\t\t\t\t  \"i2s1_in_data\",\n\t\t\t\t  \"i2s1_out_data\";\n\t\t};\n\n\t\tconf {\n\t\t\tpins = \"I2S1_IN\", \"I2S1_OUT\", \"I2S_BCLK\",\n\t\t\t       \"I2S_WS\", \"I2S_MCLK\";\n\t\t\tdrive-strength = <12>;\n\t\t\tbias-pull-down;\n\t\t};\n\t};\n\n\tirrx_pins: irrx-pins {\n\t\tmux {\n\t\t\tfunction = \"ir\";\n\t\t\tgroups =  \"ir_1_rx\";\n\t\t};\n\t};\n\n\tirtx_pins: irtx-pins {\n\t\tmux {\n\t\t\tfunction = \"ir\";\n\t\t\tgroups =  \"ir_1_tx\";\n\t\t};\n\t};\n\n\t/* Parallel nand is shared pin with eMMC */\n\tparallel_nand_pins: parallel-nand-pins {\n\t\tmux {\n\t\t\tfunction = \"flash\";\n\t\t\tgroups = \"par_nand\";\n\t\t};\n\t};\n\n\tpcie0_pins: pcie0-pins {\n\t\tmux {\n\t\t\tfunction = \"pcie\";\n\t\t\tgroups = \"pcie0_pad_perst\",\n\t\t\t\t \"pcie0_1_waken\",\n\t\t\t\t \"pcie0_1_clkreq\";\n\t\t};\n\t};\n\n\tpcie1_pins: pcie1-pins {\n\t\tmux {\n\t\t\tfunction = \"pcie\";\n\t\t\tgroups = \"pcie1_pad_perst\",\n\t\t\t\t \"pcie1_0_waken\",\n\t\t\t\t \"pcie1_0_clkreq\";\n\t\t};\n\t};\n\n\tpmic_bus_pins: pmic-bus-pins {\n\t\tmux {\n\t\t\tfunction = \"pmic\";\n\t\t\tgroups = \"pmic_bus\";\n\t\t};\n\t};\n\n\tpwm7_pins: pwm1-2-pins {\n\t\tmux {\n\t\t\tfunction = \"pwm\";\n\t\t\tgroups = \"pwm_ch7_2\";\n\t\t};\n\t};\n\n\twled_pins: wled-pins {\n\t\tmux {\n\t\t\tfunction = \"led\";\n\t\t\tgroups = \"wled\";\n\t\t};\n\t};\n\n\tsd0_pins_default: sd0-pins-default {\n\t\tmux {\n\t\t\tfunction = \"sd\";\n\t\t\tgroups = \"sd_0\";\n\t\t};\n\n\t\t/* \"I2S2_OUT, \"I2S4_IN\"\", \"I2S3_IN\", \"I2S2_IN\",\n\t\t *  \"I2S4_OUT\", \"I2S3_OUT\" are used as DAT0, DAT1,\n\t\t *  DAT2, DAT3, CMD, CLK for SD respectively.\n\t\t */\n\t\tconf-cmd-data {\n\t\t\tpins = \"I2S2_OUT\", \"I2S4_IN\", \"I2S3_IN\",\n\t\t\t       \"I2S2_IN\",\"I2S4_OUT\";\n\t\t\tinput-enable;\n\t\t\tdrive-strength = <8>;\n\t\t\tbias-pull-up;\n\t\t};\n\t\tconf-clk {\n\t\t\tpins = \"I2S3_OUT\";\n\t\t\tdrive-strength = <12>;\n\t\t\tbias-pull-down;\n\t\t};\n\t\tconf-cd {\n\t\t\tpins = \"TXD3\";\n\t\t\tbias-pull-up;\n\t\t};\n\t};\n\n\tsd0_pins_uhs: sd0-pins-uhs {\n\t\tmux {\n\t\t\tfunction = \"sd\";\n\t\t\tgroups = \"sd_0\";\n\t\t};\n\n\t\tconf-cmd-data {\n\t\t\tpins = \"I2S2_OUT\", \"I2S4_IN\", \"I2S3_IN\",\n\t\t\t       \"I2S2_IN\",\"I2S4_OUT\";\n\t\t\tinput-enable;\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tconf-clk {\n\t\t\tpins = \"I2S3_OUT\";\n\t\t\tbias-pull-down;\n\t\t};\n\t};\n\n\t/* Serial NAND is shared pin with SPI-NOR */\n\tserial_nand_pins: serial-nand-pins {\n\t\tmux {\n\t\t\tfunction = \"flash\";\n\t\t\tgroups = \"snfi\";\n\t\t};\n\t};\n\n\tspic0_pins: spic0-pins {\n\t\tmux {\n\t\t\tfunction = \"spi\";\n\t\t\tgroups = \"spic0_0\";\n\t\t};\n\t};\n\n\tspic1_pins: spic1-pins {\n\t\tmux {\n\t\t\tfunction = \"spi\";\n\t\t\tgroups = \"spic1_0\";\n\t\t};\n\t};\n\n\t/* SPI-NOR is shared pin with serial NAND */\n\tspi_nor_pins: spi-nor-pins {\n\t\tmux {\n\t\t\tfunction = \"flash\";\n\t\t\tgroups = \"spi_nor\";\n\t\t};\n\t};\n\n\t/* serial NAND is shared pin with SPI-NOR */\n\tserial_nand_pins: serial-nand-pins {\n\t\tmux {\n\t\t\tfunction = \"flash\";\n\t\t\tgroups = \"snfi\";\n\t\t};\n\t};\n\n\tuart0_pins: uart0-pins {\n\t\tmux {\n\t\t\tfunction = \"uart\";\n\t\t\tgroups = \"uart0_0_tx_rx\" ;\n\t\t};\n\t};\n\n\tuart2_pins: uart2-pins {\n\t\tmux {\n\t\t\tfunction = \"uart\";\n\t\t\tgroups = \"uart2_1_tx_rx\" ;\n\t\t};\n\t};\n\n\twatchdog_pins: watchdog-pins {\n\t\tmux {\n\t\t\tfunction = \"watchdog\";\n\t\t\tgroups = \"watchdog\";\n\t\t};\n\t};\n};\n\n&btif {\n\tstatus = \"disabled\";\n};\n\n&cir {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&irrx_pins>;\n\tstatus = \"okay\";\n};\n\n&eth {\n\tstatus = \"okay\";\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&eth_pins>;\n\tgmac0: mac@0 {\n\t\tcompatible = \"mediatek,eth-mac\";\n\t\treg = <0>;\n\t\tphy-mode = \"sgmii\";\n\t\tfixed-link {\n\t\t\tspeed = <1000>;\n\t\t\tfull-duplex;\n\t\t\tpause;\n\t\t};\n\t};\n\n\tgmac1: mac@1 {\n\t\tcompatible = \"mediatek,eth-mac\";\n\t\treg = <1>;\n\t\tphy-mode = \"rgmii\";\n\t\tfixed-link {\n\t\t\tspeed = <1000>;\n\t\t\tfull-duplex;\n\t\t\tpause;\n\t\t};\n\t};\n\n\tmdio: mdio-bus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t};\n};\n\n&i2c1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&i2c1_pins>;\n\tstatus = \"okay\";\n};\n\n&i2c2 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&i2c2_pins>;\n\tstatus = \"okay\";\n};\n\n&pwm {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pwm7_pins>;\n\tstatus = \"okay\";\n};\n\n&pwrap {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pmic_bus_pins>;\n\n\tstatus = \"okay\";\n};\n\n&bch {\n\tstatus = \"okay\";\n};\n\n&snfi {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&serial_nand_pins>;\n\tstatus = \"okay\";\n\tflash@0 {\n\t\tcompatible = \"spi-nand\";\n\t\treg = <0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tnand-ecc-engine = <&snfi>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"Preloader\";\n\t\t\t\treg = <0x00000 0x0080000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@80000 {\n\t\t\t\tlabel = \"ATF\";\n\t\t\t\treg = <0x80000 0x0040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@c0000 {\n\t\t\t\tlabel = \"uboot\";\n\t\t\t\treg = <0xc0000 0x0080000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@140000 {\n\t\t\t\tlabel = \"uboot-env\";\n\t\t\t\treg = <0x140000 0x0080000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@1c0000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x1c0000 0x0040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@200000 {\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x200000 0x2000000>;\n\t\t\t};\n\n\t\t\tpartition@2200000 {\n\t\t\t\tlabel = \"reserved\";\n\t\t\t\treg = <0x2200000 0x4000000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&spi0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&spic0_pins>;\n\tstatus = \"okay\";\n};\n\n&spi1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&spic1_pins>;\n\tstatus = \"okay\";\n};\n\n&ssusb {\n\tvusb33-supply = <&reg_3p3v>;\n\tvbus-supply = <&reg_usb_vbus>;\n\tstatus = \"okay\";\n};\n\n&u3phy {\n\tstatus = \"okay\";\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&uart0_pins>;\n\tstatus = \"okay\";\n};\n\n&uart2 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&uart2_pins>;\n\tstatus = \"okay\";\n};\n\n&watchdog {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&watchdog_pins>;\n\tstatus = \"okay\";\n};\n\n&wmac {\n\tmediatek,mtd-eeprom = <&factory 0x0000>;\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/mediatek/dts/mt7622-linksys-e8450-ubi.dts",
    "content": "// SPDX-License-Identifier: (GPL-2.0-only OR MIT)\n\n/dts-v1/;\n#include \"mt7622-linksys-e8450.dtsi\"\n\n/ {\n\tmodel = \"Linksys E8450 (UBI)\";\n\tcompatible = \"linksys,e8450-ubi\", \"mediatek,mt7622\";\n\n\taliases {\n\t\tlabel-mac-device = &wan;\n\t};\n};\n\n&snand {\n\tpartitions {\n\t\tcompatible = \"fixed-partitions\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"bl2\";\n\t\t\treg = <0x0 0x80000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@80000 {\n\t\t\tlabel = \"fip\";\n\t\t\treg = <0x80000 0x140000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tfactory: partition@1c0000 {\n\t\t\tlabel = \"factory\";\n\t\t\treg = <0x1c0000 0x100000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@300000 {\n\t\t\tlabel = \"ubi\";\n\t\t\treg = <0x300000 0x7d00000>;\n\t\t};\n\t};\n};\n\n&wmac {\n\tmediatek,mtd-eeprom = <&factory 0x0>;\n\tstatus = \"okay\";\n};\n\n&wmac1 {\n\tmediatek,mtd-eeprom = <&factory 0x5000>;\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_factory_7fff4>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wan {\n\tnvmem-cells = <&macaddr_factory_7fffa>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_7fff4: macaddr@7fff4 {\n\t\treg = <0x7fff4 0x6>;\n\t};\n\n\tmacaddr_factory_7fffa: macaddr@7fffa {\n\t\treg = <0x7fffa 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/mediatek/dts/mt7622-linksys-e8450.dts",
    "content": "// SPDX-License-Identifier: (GPL-2.0-only OR MIT)\n\n/dts-v1/;\n#include \"mt7622-linksys-e8450.dtsi\"\n\n/ {\n\tmodel = \"Linksys E8450\";\n\tcompatible = \"linksys,e8450\", \"mediatek,mt7622\";\n\n\taliases {\n\t\tlabel-mac-device = &wan;\n\t};\n};\n\n&snand {\n\tmediatek,bmt-v2;\n\tmediatek,bmt-table-size = <0x1000>;\n\n\tpartitions {\n\t\tcompatible = \"fixed-partitions\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"Preloader\";\n\t\t\treg = <0x00000 0x0080000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@80000 {\n\t\t\tlabel = \"ATF\";\n\t\t\treg = <0x80000 0x0040000>;\n\t\t};\n\n\t\tpartition@c0000 {\n\t\t\tlabel = \"u-boot\";\n\t\t\treg = <0xc0000 0x0080000>;\n\t\t};\n\n\t\tpartition@140000 {\n\t\t\tlabel = \"u-boot-env\";\n\t\t\treg = <0x140000 0x0080000>;\n\t\t};\n\n\t\tfactory: partition@1c0000 {\n\t\t\tlabel = \"factory\";\n\t\t\treg = <0x1c0000 0x0100000>;\n\t\t};\n\n\t\tpartition@300000 {\n\t\t\tlabel = \"devinfo\";\n\t\t\treg = <0x300000 0x020000>;\n\t\t};\n\n\t\tpartition@320000 {\n\t\t\tlabel = \"senv\";\n\t\t\treg = <0x320000 0x020000>;\n\t\t};\n\n\t\tpartition@360000 {\n\t\t\tlabel = \"bootseq\";\n\t\t\treg = <0x360000 0x020000>;\n\t\t};\n\n\t\tpartition@500000 {\n\t\t\tlabel = \"firmware1\";\n\t\t\tcompatible = \"denx,fit\";\n\t\t\topenwrt,cmdline-match = \"mtdparts=master\";\n\t\t\treg = <0x500000 0x1E00000>;\n\t\t};\n\n\t\tpartition@2300000 {\n\t\t\tlabel = \"firmware2\";\n\t\t\tcompatible = \"denx,fit\";\n\t\t\topenwrt,cmdline-match = \"mtdparts=slave\";\n\t\t\treg = <0x2300000 0x1E00000>;\n\t\t};\n\n\t\tpartition@4100000 {\n\t\t\tlabel = \"data\";\n\t\t\treg = <0x4100000 0x1900000>;\n\t\t};\n\n\t\tpartition@5100000 {\n\t\t\tlabel = \"mfg\";\n\t\t\treg = <0x5a00000 0x1400000>;\n\t\t};\n\t};\n};\n\n&wmac {\n\tmediatek,mtd-eeprom = <&factory 0x0000>;\n\tstatus = \"okay\";\n};\n\n&wmac1 {\n\tmediatek,mtd-eeprom = <&factory 0x05000>;\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_factory_7fff4>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wan {\n\tnvmem-cells = <&macaddr_factory_7fffa>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_7fff4: macaddr@7fff4 {\n\t\treg = <0x7fff4 0x6>;\n\t};\n\n\tmacaddr_factory_7fffa: macaddr@7fffa {\n\t\treg = <0x7fffa 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/mediatek/dts/mt7622-linksys-e8450.dtsi",
    "content": "// SPDX-License-Identifier: (GPL-2.0-only OR MIT)\n\n/dts-v1/;\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/gpio/gpio.h>\n\n#include \"mt7622.dtsi\"\n#include \"mt6380.dtsi\"\n\n/ {\n\tcompatible = \"linksys,e8450\", \"mediatek,mt7622\";\n\n\taliases {\n\t\tserial0 = &uart0;\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tchosen {\n\t\tstdout-path = \"serial0:115200n8\";\n\t\tbootargs = \"earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n1 swiotlb=512\";\n\t};\n\n\tcpus {\n\t\tcpu@0 {\n\t\t\tproc-supply = <&mt6380_vcpu_reg>;\n\t\t\tsram-supply = <&mt6380_vm_reg>;\n\t\t};\n\n\t\tcpu@1 {\n\t\t\tproc-supply = <&mt6380_vcpu_reg>;\n\t\t\tsram-supply = <&mt6380_vm_reg>;\n\t\t};\n\t};\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\tfactory {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&pio 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tgpios = <&pio 102 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tgpio-leds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power_blue {\n\t\t\tlabel = \"power:blue\";\n\t\t\tgpios = <&pio 95 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\tpower_orange {\n\t\t\tlabel = \"power:orange\";\n\t\t\tgpios = <&pio 96 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tinet_blue {\n\t\t\tlabel = \"inet:blue\";\n\t\t\tgpios = <&pio 97 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"off\";\n\t\t};\n\n\t\tinet_orange {\n\t\t\tlabel = \"inet:orange\";\n\t\t\tgpios = <&pio 98 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"off\";\n\t\t};\n\t};\n\n\tmemory {\n\t\treg = <0 0x40000000 0 0x40000000>;\n\t};\n\n\treg_1p8v: regulator-1p8v {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"fixed-1.8V\";\n\t\tregulator-min-microvolt = <1800000>;\n\t\tregulator-max-microvolt = <1800000>;\n\t\tregulator-always-on;\n\t};\n\n\treg_3p3v: regulator-3p3v {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"fixed-3.3V\";\n\t\tregulator-min-microvolt = <3300000>;\n\t\tregulator-max-microvolt = <3300000>;\n\t\tregulator-boot-on;\n\t\tregulator-always-on;\n\t};\n\n\treg_5v: regulator-5v {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"fixed-5V\";\n\t\tregulator-min-microvolt = <5000000>;\n\t\tregulator-max-microvolt = <5000000>;\n\t\tregulator-boot-on;\n\t\tregulator-always-on;\n\t};\n};\n\n&btif {\n\tstatus = \"okay\";\n};\n\n&cir {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&irrx_pins>;\n\tstatus = \"okay\";\n};\n\n&eth {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&eth_pins>;\n\tstatus = \"okay\";\n\n\tgmac0: mac@0 {\n\t\tcompatible = \"mediatek,eth-mac\";\n\t\treg = <0>;\n\t\tphy-mode = \"2500base-x\";\n\n\t\tfixed-link {\n\t\t\tspeed = <2500>;\n\t\t\tfull-duplex;\n\t\t\tpause;\n\t\t};\n\t};\n\n\tmdio-bus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tswitch@0 {\n\t\t\tcompatible = \"mediatek,mt7531\";\n\t\t\treg = <0>;\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <1>;\n\t\t\tinterrupt-parent = <&pio>;\n\t\t\tinterrupts = <53 IRQ_TYPE_LEVEL_HIGH>;\n\t\t\treset-gpios = <&pio 54 0>;\n\n\t\t\tports {\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\n\t\t\t\tport@0 {\n\t\t\t\t\treg = <0>;\n\t\t\t\t\tlabel = \"lan1\";\n\t\t\t\t};\n\n\t\t\t\tport@1 {\n\t\t\t\t\treg = <1>;\n\t\t\t\t\tlabel = \"lan2\";\n\t\t\t\t};\n\n\t\t\t\tport@2 {\n\t\t\t\t\treg = <2>;\n\t\t\t\t\tlabel = \"lan3\";\n\t\t\t\t};\n\n\t\t\t\tport@3 {\n\t\t\t\t\treg = <3>;\n\t\t\t\t\tlabel = \"lan4\";\n\t\t\t\t};\n\n\t\t\t\twan: port@4 {\n\t\t\t\t\treg = <4>;\n\t\t\t\t\tlabel = \"wan\";\n\t\t\t\t};\n\n\t\t\t\tport@6 {\n\t\t\t\t\treg = <6>;\n\t\t\t\t\tlabel = \"cpu\";\n\t\t\t\t\tethernet = <&gmac0>;\n\t\t\t\t\tphy-mode = \"2500base-x\";\n\n\t\t\t\t\tfixed-link {\n\t\t\t\t\t\tspeed = <2500>;\n\t\t\t\t\t\tfull-duplex;\n\t\t\t\t\t\tpause;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t};\n};\n\n&pcie0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pcie0_pins>;\n\tstatus = \"okay\";\n};\n\n&pcie1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pcie1_pins>;\n\tstatus = \"okay\";\n};\n\n&pio {\n\teth_pins: eth-pins {\n\t\tmux {\n\t\t\tfunction = \"eth\";\n\t\t\tgroups = \"mdc_mdio\", \"rgmii_via_gmac2\";\n\t\t};\n\t};\n\n\tirrx_pins: irrx-pins {\n\t\tmux {\n\t\t\tfunction = \"ir\";\n\t\t\tgroups =  \"ir_1_rx\";\n\t\t};\n\t};\n\n\tirtx_pins: irtx-pins {\n\t\tmux {\n\t\t\tfunction = \"ir\";\n\t\t\tgroups =  \"ir_1_tx\";\n\t\t};\n\t};\n\n\tpcie0_pins: pcie0-pins {\n\t\tmux {\n\t\t\tfunction = \"pcie\";\n\t\t\tgroups = \"pcie0_pad_perst\",\n\t\t\t\t \"pcie0_1_waken\",\n\t\t\t\t \"pcie0_1_clkreq\";\n\t\t};\n\t};\n\n\tpcie1_pins: pcie1-pins {\n\t\tmux {\n\t\t\tfunction = \"pcie\";\n\t\t\tgroups = \"pcie1_pad_perst\",\n\t\t\t\t \"pcie1_0_waken\",\n\t\t\t\t \"pcie1_0_clkreq\";\n\t\t};\n\t};\n\n\tpmic_bus_pins: pmic-bus-pins {\n\t\tmux {\n\t\t\tfunction = \"pmic\";\n\t\t\tgroups = \"pmic_bus\";\n\t\t};\n\t};\n\n\tpwm7_pins: pwm1-2-pins {\n\t\tmux {\n\t\t\tfunction = \"pwm\";\n\t\t\tgroups = \"pwm_ch7_2\";\n\t\t};\n\t};\n\n\twled_pins: wled-pins {\n\t\tmux {\n\t\t\tfunction = \"led\";\n\t\t\tgroups = \"wled\";\n\t\t};\n\t};\n\n\t/* Serial NAND is shared pin with SPI-NOR */\n\tserial_nand_pins: serial-nand-pins {\n\t\tmux {\n\t\t\tfunction = \"flash\";\n\t\t\tgroups = \"snfi\";\n\t\t};\n\t};\n\n\tspic0_pins: spic0-pins {\n\t\tmux {\n\t\t\tfunction = \"spi\";\n\t\t\tgroups = \"spic0_0\";\n\t\t};\n\t};\n\n\tspic1_pins: spic1-pins {\n\t\tmux {\n\t\t\tfunction = \"spi\";\n\t\t\tgroups = \"spic1_0\";\n\t\t};\n\t};\n\n\tuart0_pins: uart0-pins {\n\t\tmux {\n\t\t\tfunction = \"uart\";\n\t\t\tgroups = \"uart0_0_tx_rx\" ;\n\t\t};\n\t};\n\n\tuart2_pins: uart2-pins {\n\t\tmux {\n\t\t\tfunction = \"uart\";\n\t\t\tgroups = \"uart2_1_tx_rx\" ;\n\t\t};\n\t};\n\n\twatchdog_pins: watchdog-pins {\n\t\tmux {\n\t\t\tfunction = \"watchdog\";\n\t\t\tgroups = \"watchdog\";\n\t\t};\n\t};\n};\n\n&pwm {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pwm7_pins>;\n\tstatus = \"okay\";\n};\n\n&pwrap {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pmic_bus_pins>;\n\n\tstatus = \"okay\";\n};\n\n&sata {\n\tstatus = \"disabled\";\n};\n\n&sata_phy {\n\tstatus = \"disabled\";\n};\n\n&slot0 {\n\twmac1: mt7915@0,0 {\n\t\treg = <0x0000 0 0 0 0>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\t};\n};\n\n&bch {\n\tstatus = \"okay\";\n};\n\n&snfi {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&serial_nand_pins>;\n\tstatus = \"okay\";\n\n\tsnand: flash@0 {\n\t\tcompatible = \"spi-nand\";\n\t\treg = <0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tnand-ecc-engine = <&snfi>;\n\t};\n};\n\n&spi0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&spic0_pins>;\n\tstatus = \"okay\";\n};\n\n&spi1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&spic1_pins>;\n\tstatus = \"okay\";\n};\n\n&ssusb {\n\tvusb33-supply = <&reg_3p3v>;\n\tvbus-supply = <&reg_5v>;\n\tstatus = \"okay\";\n};\n\n&u3phy {\n\tstatus = \"okay\";\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&uart0_pins>;\n\tstatus = \"okay\";\n};\n\n&uart2 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&uart2_pins>;\n\tstatus = \"okay\";\n};\n\n&rtc {\n\tstatus = \"disabled\";\n};\n\n&watchdog {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&watchdog_pins>;\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/mediatek/dts/mt7622-rfb1-ubi.dts",
    "content": "/dts-v1/;\n\n#include \"mt7622-rfb1.dts\"\n/ {\n\tmodel = \"MT7622_MT7531 RFB (UBI)\";\n\tcompatible = \"mediatek,mt7622-rfb1-ubi\";\n};\n\n&snfi {\n\tflash@0 {\n\t\tmediatek,bmt-v2;\n\t\tmediatek,bmt-remap-range = <0x0 0x6c0000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"Preloader\";\n\t\t\t\treg = <0x00000 0x0080000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@80000 {\n\t\t\t\tlabel = \"ATF\";\n\t\t\t\treg = <0x80000 0x0040000>;\n\t\t\t};\n\n\t\t\tpartition@c0000 {\n\t\t\t\tlabel = \"Bootloader\";\n\t\t\t\treg = <0xc0000 0x0080000>;\n\t\t\t};\n\n\t\t\tpartition@140000 {\n\t\t\t\tlabel = \"Config\";\n\t\t\t\treg = <0x140000 0x0080000>;\n\t\t\t};\n\n\t\t\tfactory: partition@1c0000 {\n\t\t\t\tlabel = \"Factory\";\n\t\t\t\treg = <0x1c0000 0x0100000>;\n\t\t\t};\n\n\t\t\tpartition@200000 {\n\t\t\t\tlabel = \"kernel\";\n\t\t\t\treg = <0x2c0000 0x400000>;\n\t\t\t};\n\n\t\t\tpartition@6c0000 {\n\t\t\t\tlabel = \"ubi\";\n\t\t\t\treg = <0x6c0000 0x6f00000>;\n\t\t\t};\n\n\t\t\t/delete-node/ partition@2200000;\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/mediatek/dts/mt7622-ruijie-rg-ew3200gx-pro.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n/dts-v1/;\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/gpio/gpio.h>\n\n#include \"mt7622.dtsi\"\n#include \"mt6380.dtsi\"\n\n/ {\n\tmodel = \"Ruijie RG-EW3200GX PRO\";\n\tcompatible = \"ruijie,rg-ew3200gx-pro\", \"mediatek,mt7622\";\n\n\taliases {\n\t\tethernet0 = &gmac0;\n\t\tlabel-mac-device = &gmac0;\n\t\tled-boot = &led_system;\n\t\tled-failsafe = &led_system;\n\t\tled-running = &led_system;\n\t\tled-upgrade = &led_system;\n\t\tserial0 = &uart0;\n\t};\n\n\tchosen {\n\t\tstdout-path = \"serial0:115200n1\";\n\t\tbootargs = \"console=ttyS0,115200n1 swiotlb=512\";\n\t};\n\n\tcpus {\n\t\tcpu@0 {\n\t\t\tproc-supply = <&mt6380_vcpu_reg>;\n\t\t\tsram-supply = <&mt6380_vm_reg>;\n\t\t};\n\n\t\tcpu@1 {\n\t\t\tproc-supply = <&mt6380_vcpu_reg>;\n\t\t\tsram-supply = <&mt6380_vm_reg>;\n\t\t};\n\t};\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&pio 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tgpios = <&pio 102 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tgpio-leds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tmesh_green {\n\t\t\tlabel = \"green:mesh\";\n\t\t\tgpios = <&pio 79 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tmesh_red {\n\t\t\tlabel = \"red:mesh\";\n\t\t\tgpios = <&pio 82 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_system: system_blue {\n\t\t\tlabel = \"blue:system\";\n\t\t\tgpios = <&pio 81 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\tmemory {\n\t\treg = <0 0x40000000 0 0x40000000>;\n\t};\n};\n\n&eth {\n\tstatus = \"okay\";\n\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&eth_pins>;\n\n\tgmac0: mac@0 {\n\t\tcompatible = \"mediatek,eth-mac\";\n\t\treg = <0>;\n\t\tphy-connection-type = \"2500base-x\";\n\t\tfixed-link {\n\t\t\tspeed = <2500>;\n\t\t\tfull-duplex;\n\t\t\tpause;\n\t\t};\n\t};\n\n\tmdio: mdio-bus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tswitch@0 {\n\t\t\tcompatible = \"mediatek,mt7531\";\n\t\t\treg = <0>;\n\t\t\treset-gpios = <&pio 54 GPIO_ACTIVE_HIGH>;\n\t\t\t\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\tinterrupt-parent = <&pio>;\n\t\t\tinterrupts = <53 IRQ_TYPE_LEVEL_HIGH>;\n\n\t\t\tports {\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\n\t\t\t\tport@0 {\n\t\t\t\t\treg = <0>;\n\t\t\t\t\tlabel = \"lan1\";\n\t\t\t\t};\n\n\t\t\t\tport@1 {\n\t\t\t\t\treg = <1>;\n\t\t\t\t\tlabel = \"lan2\";\n\t\t\t\t};\n\n\t\t\t\tport@2 {\n\t\t\t\t\treg = <2>;\n\t\t\t\t\tlabel = \"lan3\";\n\t\t\t\t};\n\n\t\t\t\tport@3 {\n\t\t\t\t\treg = <3>;\n\t\t\t\t\tlabel = \"lan4\";\n\t\t\t\t};\n\n\t\t\t\twan: port@4 {\n\t\t\t\t\treg = <4>;\n\t\t\t\t\tlabel = \"wan\";\n\t\t\t\t};\n\n\t\t\t\tport@6 {\n\t\t\t\t\treg = <6>;\n\t\t\t\t\tlabel = \"cpu\";\n\t\t\t\t\tethernet = <&gmac0>;\n\t\t\t\t\tphy-mode = \"2500base-x\";\n\n\t\t\t\t\tfixed-link {\n\t\t\t\t\t\tspeed = <2500>;\n\t\t\t\t\t\tfull-duplex;\n\t\t\t\t\t\tpause;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pcie0 {\n\tstatus = \"okay\";\n\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pcie0_pins>;\n};\n\n&slot0 {\n\tmt7915@0,0 {\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x5000>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\t};\n};\n\n&pio {\n\tepa_elna_pins: epa-elna-pins {\n\t\tmux {\n\t\t\tfunction = \"antsel\";\n\t\t\tgroups = \"antsel0\", \"antsel1\", \"antsel2\", \"antsel3\",\n\t\t\t\t\"antsel4\", \"antsel5\", \"antsel6\", \"antsel7\",\n\t\t\t\t\"antsel8\", \"antsel9\", \"antsel12\", \"antsel13\",\n\t\t\t\t\"antsel14\", \"antsel15\", \"antsel16\", \"antsel17\";\n\t\t};\n\t};\n\n\teth_pins: eth-pins {\n\t\tmux {\n\t\t\tfunction = \"eth\";\n\t\t\tgroups = \"mdc_mdio\", \"rgmii_via_gmac2\";\n\t\t};\n\t};\n\n\tpcie0_pins: pcie0-pins {\n\t\tmux {\n\t\t\tfunction = \"pcie\";\n\t\t\tgroups = \"pcie0_pad_perst\",\n\t\t\t\t \"pcie0_0_waken\",\n\t\t\t\t \"pcie0_0_clkreq\";\n\t\t};\n\t};\n\n\tpmic_bus_pins: pmic-bus-pins {\n\t\tmux {\n\t\t\tfunction = \"pmic\";\n\t\t\tgroups = \"pmic_bus\";\n\t\t};\n\t};\n\n\tspi_nor_pins: spi-nor-pins {\n\t\tmux {\n\t\t\tfunction = \"flash\";\n\t\t\tgroups = \"spi_nor\";\n\t\t};\n\t};\n\n\tuart0_pins: uart0-pins {\n\t\tmux {\n\t\t\tfunction = \"uart\";\n\t\t\tgroups = \"uart0_0_tx_rx\";\n\t\t};\n\t};\n\n\twatchdog_pins: watchdog-pins {\n\t\tmux {\n\t\t\tfunction = \"watchdog\";\n\t\t\tgroups = \"watchdog\";\n\t\t};\n\t};\n};\n\n&pwrap {\n\tstatus = \"okay\";\n\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pmic_bus_pins>;\n};\n\n&nor_flash {\n\tstatus = \"okay\";\n\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&spi_nor_pins>;\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <50000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"Preloader\";\n\t\t\t\treg = <0x0 0x40000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"ATF\";\n\t\t\t\treg = <0x40000 0x20000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@60000 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x60000 0x50000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@B0000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0xb0000 0x20000>;\n\t\t\t};\n\n\t\t\tfactory: partition@D0000 {\n\t\t\t\tlabel = \"Factory\";\n\t\t\t\treg = <0xd0000 0x80000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@150000 {\n\t\t\t\tlabel = \"product_info\";\n\t\t\t\treg = <0x150000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@160000 {\n\t\t\t\tlabel = \"kdump\";\n\t\t\t\treg = <0x160000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@170000 {\n\t\t\t\tcompatible = \"denx,fit\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x170000 0xe90000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&rtc {\n\tstatus = \"disabled\";\n};\n\n&uart0 {\n\tstatus = \"okay\";\n\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&uart0_pins>;\n};\n\n&watchdog {\n\tstatus = \"okay\";\n\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&watchdog_pins>;\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&epa_elna_pins>;\n\tmediatek,mtd-eeprom = <&factory 0x0>;\n};\n"
  },
  {
    "path": "target/linux/mediatek/dts/mt7622-totolink-a8000ru.dts",
    "content": "// SPDX-License-Identifier: (GPL-2.0-only OR MIT)\n\n/dts-v1/;\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/gpio/gpio.h>\n\n#include \"mt7622.dtsi\"\n#include \"mt6380.dtsi\"\n\n/ {\n\tmodel = \"TOTOLINK A8000RU\";\n\tcompatible = \"totolink,a8000ru\", \"mediatek,mt7622\";\n\n\taliases {\n\t\tlabel-mac-device = &gmac0;\n\t\tled-boot = &led_status;\n\t\tled-failsafe = &led_status;\n\t\tled-running = &led_status;\n\t\tled-upgrade = &led_status;\n\t\tserial0 = &uart0;\n\t};\n\n\tchosen {\n\t\tstdout-path = \"serial0:115200n8\";\n\t\tbootargs = \"earlycon=uart8250,mmio32,0x11002000 swiotlb=512\";\n\t};\n\n\tcpus {\n\t\tcpu@0 {\n\t\t\tproc-supply = <&mt6380_vcpu_reg>;\n\t\t\tsram-supply = <&mt6380_vm_reg>;\n\t\t};\n\n\t\tcpu@1 {\n\t\t\tproc-supply = <&mt6380_vcpu_reg>;\n\t\t\tsram-supply = <&mt6380_vm_reg>;\n\t\t};\n\t};\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&pio 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tgpios = <&pio 102 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tgpio-leds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_status: status_red {\n\t\t\tlabel = \"red:status\";\n\t\t\tgpios = <&pio 81 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\treg_1p8v: regulator-1p8v {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"fixed-1.8V\";\n\t\tregulator-min-microvolt = <1800000>;\n\t\tregulator-max-microvolt = <1800000>;\n\t\tregulator-always-on;\n\t};\n\n\treg_3p3v: regulator-3p3v {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"fixed-3.3V\";\n\t\tregulator-min-microvolt = <3300000>;\n\t\tregulator-max-microvolt = <3300000>;\n\t\tregulator-boot-on;\n\t\tregulator-always-on;\n\t};\n\n\trtkgsw: rtkgsw@0 {\n\t\tcompatible = \"mediatek,rtk-gsw\";\n\t\tmediatek,ethsys = <&ethsys>;\n\t\tmediatek,mdio = <&mdio>;\n\t\tmediatek,reset-pin = <&pio 54 0>;\n\t\tstatus = \"okay\";\n\t};\n};\n\n&pcie0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pcie0_pins>;\n\tstatus = \"okay\";\n};\n\n&slot0 {\n\tmt7615@0,0 {\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x5000>;\n\t\tieee80211-freq-limit = <5490000 6000000>;\n\t};\n};\n\n&pcie1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pcie1_pins>;\n\tstatus = \"okay\";\n};\n\n&slot1 {\n\tmt7615@0,0 {\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x10000>;\n\t\tieee80211-freq-limit = <5000000 5490000>;\n\t};\n};\n\n&pio {\n\teth_pins: eth-pins {\n\t\tmux {\n\t\t\tfunction = \"eth\";\n\t\t\tgroups = \"mdc_mdio\", \"rgmii_via_gmac2\";\n\t\t};\n\t};\n\n\tpcie0_pins: pcie0-pins {\n\t\tmux {\n\t\t\tfunction = \"pcie\";\n\t\t\tgroups = \"pcie0_pad_perst\",\n\t\t\t\t \"pcie0_1_waken\",\n\t\t\t\t \"pcie0_1_clkreq\";\n\t\t};\n\t};\n\n\tpcie1_pins: pcie1-pins {\n\t\tmux {\n\t\t\tfunction = \"pcie\";\n\t\t\tgroups = \"pcie1_pad_perst\",\n\t\t\t\t \"pcie1_0_waken\",\n\t\t\t\t \"pcie1_0_clkreq\";\n\t\t};\n\t};\n\n\tpmic_bus_pins: pmic-bus-pins {\n\t\tmux {\n\t\t\tfunction = \"pmic\";\n\t\t\tgroups = \"pmic_bus\";\n\t\t};\n\t};\n\n\t/* serial NAND is shared pin with SPI-NOR */\n\tserial_nand_pins: serial-nand-pins {\n\t\tmux {\n\t\t\tfunction = \"flash\";\n\t\t\tgroups = \"snfi\";\n\t\t};\n\t};\n\n\tuart0_pins: uart0-pins {\n\t\tmux {\n\t\t\tfunction = \"uart\";\n\t\t\tgroups = \"uart0_0_tx_rx\" ;\n\t\t};\n\t};\n\n\twatchdog_pins: watchdog-pins {\n\t\tmux {\n\t\t\tfunction = \"watchdog\";\n\t\t\tgroups = \"watchdog\";\n\t\t};\n\t};\n\n\tepa_elna_pins: epa-elna-pins {\n\t\tmux {\n\t\t\tfunction = \"antsel\";\n\t\t\tgroups = \"antsel0\", \"antsel1\", \"antsel2\", \"antsel3\",\n\t\t\t\t\"antsel4\", \"antsel5\", \"antsel6\", \"antsel7\",\n\t\t\t\t\"antsel8\", \"antsel9\", \"antsel12\", \"antsel13\",\n\t\t\t\t\"antsel14\", \"antsel15\", \"antsel16\", \"antsel17\";\n\t\t};\n\t};\n};\n\n&eth {\n\tstatus = \"okay\";\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&eth_pins>;\n\n\tgmac0: mac@0 {\n\t\tcompatible = \"mediatek,eth-mac\";\n\t\treg = <0>;\n\t\tnvmem-cells = <&macaddr_factory_2a>;\n\t\tnvmem-cell-names = \"mac-address\";\n\t\tphy-connection-type = \"2500base-x\";\n\t\tfixed-link {\n\t\t\tspeed = <2500>;\n\t\t\tfull-duplex;\n\t\t\tpause;\n\t\t};\n\t};\n\n\tgmac1: mac@1 {\n\t\tcompatible = \"mediatek,eth-mac\";\n\t\treg = <1>;\n\t\tphy-mode = \"rgmii\";\n\t\tnvmem-cells = <&macaddr_factory_24>;\n\t\tnvmem-cell-names = \"mac-address\";\n\t\tfixed-link {\n\t\t\tspeed = <1000>;\n\t\t\tfull-duplex;\n\t\t\tpause;\n\t\t};\n\t};\n\n\tmdio: mdio-bus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t};\n};\n\n&pwrap {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pmic_bus_pins>;\n\tstatus = \"okay\";\n};\n\n&bch {\n\tstatus = \"okay\";\n};\n\n&snfi {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&serial_nand_pins>;\n\tstatus = \"okay\";\n\tflash@0 {\n\t\tcompatible = \"spi-nand\";\n\t\treg = <0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tnand-ecc-engine = <&snfi>;\n\t\tmediatek,bmt-v2;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"Preloader\";\n\t\t\t\treg = <0x0 0x80000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@80000 {\n\t\t\t\tlabel = \"ATF\";\n\t\t\t\treg = <0x80000 0x40000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@c0000 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0xc0000 0x80000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@140000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x140000 0x80000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@1c0000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x1c0000 0x40000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@200000 {\n\t\t\t\tlabel = \"ubi\";\n\t\t\t\treg = <0x200000 0x6400000>;\n\t\t\t};\n\n\t\t\tpartition@6600000 {\n\t\t\t\tlabel = \"User_data\";\n\t\t\t\treg = <0x6600000 0x100000>;\n\t\t\t};\n\n\t\t\t/* size of this partition varies due to BMT & bad blocks. */\n\t\t\tpartition@6700000 {\n\t\t\t\tlabel = \"reserved\";\n\t\t\t\treg = <0x6700000 0>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_24: macaddr@24 {\n\t\treg = <0x24 0x6>;\n\t};\n\n\tmacaddr_factory_2a: macaddr@2a {\n\t\treg = <0x2a 0x6>;\n\t};\n};\n\n&ssusb {\n\tvusb33-supply = <&reg_3p3v>;\n\tstatus = \"okay\";\n};\n\n&u3phy {\n\tstatus = \"okay\";\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&uart0_pins>;\n\tstatus = \"okay\";\n};\n\n&watchdog {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&watchdog_pins>;\n\tstatus = \"okay\";\n};\n\n&wmac {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&epa_elna_pins>;\n\tmediatek,mtd-eeprom = <&factory 0x0>;\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr-ubootmod.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7622-ubnt-unifi-6-lr.dtsi\"\n\n/ {\n\tmodel = \"Ubiquiti UniFi 6 LR (U-Boot mod)\";\n\tcompatible = \"ubnt,unifi-6-lr-ubootmod\", \"mediatek,mt7622\";\n};\n\n&nor_partitions {\n\tpartition@0 {\n\t\tlabel = \"bl2\";\n\t\treg = <0x0 0x20000>;\n\t};\n\n\tpartition@20000 {\n\t\tlabel = \"fip\";\n\t\treg = <0x20000 0xa0000>;\n\t};\n\n\tpartition@c0000 {\n\t\tlabel = \"u-boot-env\";\n\t\treg = <0xc0000 0x10000>;\n\t};\n\n\tfactory: partition@d0000 {\n\t\tlabel = \"factory\";\n\t\treg = <0xd0000 0x40000>;\n\t\tread-only;\n\t};\n\n\teeprom: partition@110000 {\n\t\tlabel = \"eeprom\";\n\t\treg = <0x110000 0x10000>;\n\t\tread-only;\n\t};\n\n\tpartition@120000 {\n\t\tlabel = \"recovery\";\n\t\treg = <0x120000 0xee0000>;\n\t};\n\n\tpartition@1000000 {\n\t\tcompatible = \"denx,fit\";\n\t\tlabel = \"firmware\";\n\t\treg = <0x1000000 0x3000000>;\n\t};\n};\n\n&wmac {\n\tmediatek,mtd-eeprom = <&factory 0x0>;\n\tnvmem-cells = <&macaddr_eeprom_0>;\n\tnvmem-cell-names = \"mac-address\";\n\tstatus = \"okay\";\n};\n\n&slot0 {\n\twifi@0,0 {\n\t\treg = <0x0 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x20000>;\n\t\tnvmem-cells = <&macaddr_eeprom_6>;\n\t\tnvmem-cell-names = \"mac-address\";\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\t};\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_eeprom_0>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&eeprom {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_eeprom_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n\n\tmacaddr_eeprom_6: macaddr@6 {\n\t\treg = <0x6 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7622-ubnt-unifi-6-lr.dtsi\"\n\n/ {\n\tmodel = \"Ubiquiti UniFi 6 LR\";\n\tcompatible = \"ubnt,unifi-6-lr\", \"mediatek,mt7622\";\n};\n\n&nor_partitions {\n\tpartition@0 {\n\t\tlabel = \"preloader\";\n\t\treg = <0x0 0x40000>;\n\t};\n\n\tpartition@40000 {\n\t\tlabel = \"atf\";\n\t\treg = <0x40000 0x20000>;\n\t};\n\n\tpartition@60000 {\n\t\tlabel = \"u-boot\";\n\t\treg = <0x60000 0x60000>;\n\t};\n\n\tpartition@c0000 {\n\t\tlabel = \"u-boot-env\";\n\t\treg = <0xc0000 0x10000>;\n\t};\n\n\tfactory: partition@d0000 {\n\t\tlabel = \"factory\";\n\t\treg = <0xd0000 0x40000>;\n\t\tread-only;\n\t};\n\n\teeprom: partition@110000 {\n\t\tlabel = \"eeprom\";\n\t\treg = <0x110000 0x10000>;\n\t\tread-only;\n\t};\n\n\tpartition@120000 {\n\t\tlabel = \"bs\";\n\t\treg = <0x120000 0x10000>;\n\t};\n\n\tpartition@130000 {\n\t\tlabel = \"cfg\";\n\t\treg = <0x130000 0x100000>;\n\t\tread-only;\n\t};\n\n\tpartition@230000 {\n\t\tcompatible = \"denx,fit\";\n\t\tlabel = \"firmware\";\n\t\treg = <0x230000 0x1ee0000>;\n\t};\n\n\tpartition@2110000 {\n\t\tlabel = \"kernel1\";\n\t\treg = <0x2110000 0x1ee0000>;\n\t};\n};\n\n&wmac {\n\tmediatek,mtd-eeprom = <&factory 0x0>;\n\tnvmem-cells = <&macaddr_eeprom_0>;\n\tnvmem-cell-names = \"mac-address\";\n\tstatus = \"okay\";\n};\n\n&slot0 {\n\twifi@0,0 {\n\t\treg = <0x0 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x20000>;\n\t\tnvmem-cells = <&macaddr_eeprom_6>;\n\t\tnvmem-cell-names = \"mac-address\";\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\t};\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_eeprom_0>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&eeprom {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_eeprom_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n\n\tmacaddr_eeprom_6: macaddr@6 {\n\t\treg = <0x6 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/mediatek/dts/mt7622-ubnt-unifi-6-lr.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n/dts-v1/;\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/leds/common.h>\n\n#include \"mt7622.dtsi\"\n#include \"mt6380.dtsi\"\n\n/ {\n\taliases {\n\t\tled-boot = &led_blue;\n\t\tled-failsafe = &led_blue;\n\t\tled-running = &led_blue;\n\t\tled-upgrade = &led_blue;\n\t\tlabel-mac-device = &gmac0;\n\t\tserial0 = &uart0;\n\t};\n\n\tchosen {\n\t\tstdout-path = \"serial0:115200n8\";\n\t\tbootargs = \"earlycon=uart8250,mmio32,0x11002000 swiotlb=512 console=ttyS0,115200n8\";\n\t};\n\n\tcpus {\n\t\tcpu@0 {\n\t\t\tproc-supply = <&mt6380_vcpu_reg>;\n\t\t\tsram-supply = <&mt6380_vm_reg>;\n\t\t};\n\n\t\tcpu@1 {\n\t\t\tproc-supply = <&mt6380_vcpu_reg>;\n\t\t\tsram-supply = <&mt6380_vm_reg>;\n\t\t};\n\t};\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&pio 62 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tmemory {\n\t\treg = <0 0x40000000 0 0x3f000000>;\n\t};\n\n\treg_1p8v: regulator-1p8v {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"fixed-1.8V\";\n\t\tregulator-min-microvolt = <1800000>;\n\t\tregulator-max-microvolt = <1800000>;\n\t\tregulator-always-on;\n\t};\n\n\treg_3p3v: regulator-3p3v {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"fixed-3.3V\";\n\t\tregulator-min-microvolt = <3300000>;\n\t\tregulator-max-microvolt = <3300000>;\n\t\tregulator-boot-on;\n\t\tregulator-always-on;\n\t};\n};\n\n&pcie0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pcie0_pins>;\n\tstatus = \"okay\";\n};\n\n\n&pio {\n\teth_pins: eth-pins {\n\t\tmux {\n\t\t\tfunction = \"eth\";\n\t\t\tgroups = \"mdc_mdio\", \"rgmii_via_gmac2\";\n\t\t};\n\t};\n\n\tpcie0_pins: pcie0-pins {\n\t\tmux {\n\t\t\tfunction = \"pcie\";\n\t\t\tgroups = \"pcie0_pad_perst\",\n\t\t\t\t \"pcie0_1_waken\",\n\t\t\t\t \"pcie0_1_clkreq\";\n\t\t};\n\t};\n\n\tpcie1_pins: pcie1-pins {\n\t\tmux {\n\t\t\tfunction = \"pcie\";\n\t\t\tgroups = \"pcie1_pad_perst\",\n\t\t\t\t \"pcie1_0_waken\",\n\t\t\t\t \"pcie1_0_clkreq\";\n\t\t};\n\t};\n\n\tpmic_bus_pins: pmic-bus-pins {\n\t\tmux {\n\t\t\tfunction = \"pmic\";\n\t\t\tgroups = \"pmic_bus\";\n\t\t};\n\t};\n\n\tspi_nor_pins: spi-nor-pins {\n\t\tmux {\n\t\t\tfunction = \"flash\";\n\t\t\tgroups = \"spi_nor\";\n\t\t};\n\t};\n\n\tuart0_pins: uart0-pins {\n\t\tmux {\n\t\t\tfunction = \"uart\";\n\t\t\tgroups = \"uart0_0_tx_rx\" ;\n\t\t};\n\t};\n\n\tuart3_pins: uart3-pins {\n\t\tmux {\n\t\t\tfunction = \"uart\";\n\t\t\tgroups = \"uart3_1_tx_rx\" ;\n\t\t};\n\t};\n\n\ti2c0_pins: i2c0-pins {\n\t\tmux {\n\t\t\tfunction = \"i2c\";\n\t\t\tgroups =  \"i2c0\";\n\t\t};\n\t};\n\n\twatchdog_pins: watchdog-pins {\n\t\tmux {\n\t\t\tfunction = \"watchdog\";\n\t\t\tgroups = \"watchdog\";\n\t\t};\n\t};\n};\n\n&bch {\n\tstatus = \"okay\";\n};\n\n&btif {\n\tstatus = \"disabled\";\n};\n\n&eth {\n\tstatus = \"okay\";\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&eth_pins>;\n\n\tgmac0: mac@0 {\n\t\tcompatible = \"mediatek,eth-mac\";\n\t\treg = <0>;\n\n\t\tphy-mode = \"2500base-x\";\n\t\tphy-handle = <&phy0>;\n\t\tphy-connection-type = \"2500base-x\";\n\t};\n\n\tmdio: mdio-bus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tphy0: ethernet-phy@8 {\n\t\t\tcompatible = \"ethernet-phy-ieee802.3-c45\";\n\t\t\treg = <0x8>;\n\t\t};\n\t};\n};\n\n&pwrap {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pmic_bus_pins>;\n\n\tstatus = \"okay\";\n};\n\n&nor_flash {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&spi_nor_pins>;\n\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <50000000>;\n\n\t\tnor_partitions: partitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t};\n\t};\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&uart0_pins>;\n\tstatus = \"okay\";\n};\n\n&uart3 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&uart3_pins>;\n\tstatus = \"okay\";\n\n\t/* MT7915 Bluetooth */\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&i2c0_pins>;\n\tstatus = \"okay\";\n\n\tled-controller@30 {\n\t\tcompatible = \"ubnt,ledbar\";\n\t\treg = <0x30>;\n\n\t\tenable-gpio = <&pio 59 0>;\n\n\t\tred {\n\t\t\tlabel = \"red\";\n\t\t};\n\n\t\tgreen {\n\t\t\tlabel = \"green\";\n\t\t};\n\n\t\tled_blue: blue {\n\t\t\tlabel = \"blue\";\n\t\t};\n\t};\n};\n\n&watchdog {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&watchdog_pins>;\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/mediatek/dts/mt7622-xiaomi-redmi-router-ax6s.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n/dts-v1/;\n\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/gpio/gpio.h>\n\n#include \"mt7622.dtsi\"\n#include \"mt6380.dtsi\"\n\n/ {\n\tmodel = \"Xiaomi Redmi Router AX6S\";\n\tcompatible = \"xiaomi,redmi-router-ax6s\", \"mediatek,mt7622\";\n\n\taliases {\n\t\tserial0 = &uart0;\n\t\tled-boot = &led_power_amber;\n\t\tled-failsafe = &led_power_amber;\n\t\tled-running = &led_power_blue;\n\t\tled-upgrade = &led_power_blue;\n\t};\n\n\tchosen {\n\t\tstdout-path = \"serial0:115200n8\";\n\t\tbootargs = \"earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n8 swiotlb=512\";\n\t};\n\n\tmemory {\n\t\treg = <0 0x40000000 0 0x8000000>;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power_blue: power_blue {\n\t\t\tlabel = \"blue:power\";\n\t\t\tgpios = <&pio 18 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_power_amber: power_amber {\n\t\t\tlabel = \"amber:power\";\n\t\t\tgpios = <&pio 17 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_net_blue: net_blue {\n\t\t\tlabel = \"blue:net\";\n\t\t\tgpios = <&pio 01 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_net_amber: net_amber {\n\t\t\tlabel = \"amber:net\";\n\t\t\tgpios = <&pio 16 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&pio 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\tmesh {\n\t\t\tlabel = \"mesh\";\n\t\t\tgpios = <&pio 102 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_9>;\n\t\t\tlinux,input-type = <EV_SW>;\n\t\t};\n\t};\n};\n\n&cpu0 {\n\tproc-supply = <&mt6380_vcpu_reg>;\n\tsram-supply = <&mt6380_vm_reg>;\n};\n\n&cpu1 {\n\tproc-supply = <&mt6380_vcpu_reg>;\n\tsram-supply = <&mt6380_vm_reg>;\n};\n\n&pio {\n\teth_pins: eth-pins {\n\t\tmux {\n\t\t\tfunction = \"eth\";\n\t\t\tgroups = \"mdc_mdio\", \"rgmii_via_gmac2\";\n\t\t};\n\t};\n\n\tpcie0_pins: pcie0-pins {\n\t\tmux {\n\t\t\tfunction = \"pcie\";\n\t\t\tgroups = \"pcie0_pad_perst\",\n\t\t\t\t \"pcie0_1_waken\",\n\t\t\t\t \"pcie0_1_clkreq\";\n\t\t};\n\t};\n\n\tpmic_bus_pins: pmic-bus-pins {\n\t\tmux {\n\t\t\tfunction = \"pmic\";\n\t\t\tgroups = \"pmic_bus\";\n\t\t};\n\t};\n\n\tpwm7_pins: pwm1-2-pins {\n\t\tmux {\n\t\t\tfunction = \"pwm\";\n\t\t\tgroups = \"pwm_ch7_2\";\n\t\t};\n\t};\n\n\t/* Serial NAND is shared pin with SPI-NOR */\n\tserial_nand_pins: serial-nand-pins {\n\t\tmux {\n\t\t\tfunction = \"flash\";\n\t\t\tgroups = \"snfi\";\n\t\t};\n\t};\n\n\tuart0_pins: uart0-pins {\n\t\tmux {\n\t\t\tfunction = \"uart\";\n\t\t\tgroups = \"uart0_0_tx_rx\" ;\n\t\t};\n\t};\n\n\twatchdog_pins: watchdog-pins {\n\t\tmux {\n\t\t\tfunction = \"watchdog\";\n\t\t\tgroups = \"watchdog\";\n\t\t};\n\t};\n};\n\n&eth {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&eth_pins>;\n\tstatus = \"okay\";\n\n\tgmac0: mac@0 {\n\t\tcompatible = \"mediatek,eth-mac\";\n\t\treg = <0>;\n\n\t\tphy-connection-type = \"2500base-x\";\n\n\t\tnvmem-cells = <&macaddr_factory_4>;\n\t\tnvmem-cell-names = \"mac-address\";\n\t\tmac-address-increment = <(-1)>;\n\n\t\tfixed-link {\n\t\t\tspeed = <2500>;\n\t\t\tfull-duplex;\n\t\t\tpause;\n\t\t};\n\t};\n\n\tmdio-bus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tswitch@0 {\n\t\t\tcompatible = \"mediatek,mt7531\";\n\t\t\treg = <0>;\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <1>;\n\t\t\tinterrupt-parent = <&pio>;\n\t\t\tinterrupts = <53 IRQ_TYPE_LEVEL_HIGH>;\n\t\t\treset-gpios = <&pio 54 GPIO_ACTIVE_HIGH>;\n\n\t\t\tports {\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\n\t\t\t\twan: port@1 {\n\t\t\t\t\treg = <1>;\n\t\t\t\t\tlabel = \"wan\";\n\t\t\t\t};\n\n\t\t\t\tport@2 {\n\t\t\t\t\treg = <2>;\n\t\t\t\t\tlabel = \"lan1\";\n\t\t\t\t};\n\n\t\t\t\tport@3 {\n\t\t\t\t\treg = <3>;\n\t\t\t\t\tlabel = \"lan2\";\n\t\t\t\t};\n\n\t\t\t\tport@4 {\n\t\t\t\t\treg = <4>;\n\t\t\t\t\tlabel = \"lan3\";\n\t\t\t\t};\n\n\t\t\t\tport@6 {\n\t\t\t\t\treg = <6>;\n\t\t\t\t\tlabel = \"cpu\";\n\t\t\t\t\tethernet = <&gmac0>;\n\t\t\t\t\tphy-mode = \"2500base-x\";\n\n\t\t\t\t\tfixed-link {\n\t\t\t\t\t\tspeed = <2500>;\n\t\t\t\t\t\tfull-duplex;\n\t\t\t\t\t\tpause;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t};\n};\n\n&bch {\n\tstatus = \"okay\";\n};\n\n&snfi {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&serial_nand_pins>;\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"spi-nand\";\n\t\treg = <0>;\n\t\tspi-tx-bus-width = <4>;\n\t\tspi-rx-bus-width = <4>;\n\t\tnand-ecc-engine = <&snfi>;\n\n\t\tmediatek,bmt-v2;\n\t\tmediatek,bmt-table-size = <0x1000>;\n\t\tmediatek,bmt-remap-range = <0x0 0x6c0000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"Preloader\";\n\t\t\t\treg = <0x0 0x80000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@80000 {\n\t\t\t\tlabel = \"ATF\";\n\t\t\t\treg = <0x80000 0x40000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@c0000 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0xc0000 0x80000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@140000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x140000 0x40000>;\n\t\t\t};\n\n\t\t\tpartition@180000 {\n\t\t\t\tlabel = \"bdata\";\n\t\t\t\treg = <0x180000 0x40000>;\n\t\t\t};\n\n\t\t\tfactory: partition@1c0000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x1c0000 0x80000>;\n\t\t\t\tread-only;\n\n\t\t\t\tcompatible = \"nvmem-cells\";\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\n\t\t\t\tmacaddr_factory_4: macaddr@4 {\n\t\t\t\t\treg = <0x4 0x6>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tpartition@240000 {\n\t\t\t\tlabel = \"crash\";\n\t\t\t\treg = <0x240000 0x40000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@280000 {\n\t\t\t\tlabel = \"crash_log\";\n\t\t\t\treg = <0x280000 0x40000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\t/* Shrunk and renamed from \"firmware\"\n\t\t\t * as to not break luci size checks\n\t\t\t */\n\t\t\tpartition@2c0000 {\n\t\t\t\tlabel = \"kernel\";\n\t\t\t\tcompatible = \"denx,fit\";\n\t\t\t\treg = <0x2c0000 0x400000>;\n\t\t\t};\n\n\t\t\t/* ubi partition is the result of squashing\n\t\t\t * consecutive stock partitions:\n\t\t\t * - firmware (partially)\n\t\t\t * - firmware1\n\t\t\t * - overlay\n\t\t\t * - obr\n\t\t\t */\n\t\t\tpartition@6c0000 {\n\t\t\t\tlabel = \"ubi\";\n\t\t\t\treg = <0x6C0000 0x6f00000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pcie0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pcie0_pins>;\n\tstatus = \"okay\";\n};\n\n&slot0 {\n\tstatus = \"okay\";\n\n\twifi@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x5000>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\t};\n};\n\n&pwm {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pwm7_pins>;\n\tstatus = \"okay\";\n};\n\n&pwrap {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pmic_bus_pins>;\n\tstatus = \"okay\";\n};\n\n&rtc {\n\tstatus = \"disabled\";\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&uart0_pins>;\n\tstatus = \"okay\";\n};\n\n&watchdog {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&watchdog_pins>;\n\tstatus = \"okay\";\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmediatek,mtd-eeprom = <&factory 0x0>;\n};\n"
  },
  {
    "path": "target/linux/mediatek/dts/mt7623a-unielec-u7623-02-emmc-512m.dts",
    "content": "// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)\n/*\n * Copyright 2018 Kristian Evensen <kristian.evensen@gmail.com>\n */\n\n/dts-v1/;\n#include \"mt7623a-unielec-u7623-02.dtsi\"\n\n/ {\n\tmodel = \"UniElec U7623-02 eMMC (legacy loader, 512M RAM)\";\n\tcompatible = \"unielec,u7623-02-emmc-512m\", \"unielec,u7623-02\", \"mediatek,mt7623\";\n\n\tchosen {\n\t\tbootargs = \"earlycon=uart8250,mmio32,0x11004000 console=ttyS0,115200 blkdevparts=mmcblk0:3M@6M(recovery),256M@9M(root) rootfstype=squashfs root=/dev/mmcblk0p2\";\n\t};\n\n\tmemory@80000000 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0 0x80000000 0 0x20000000>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/mediatek/dts/mt7623a-unielec-u7623-02.dts",
    "content": "// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)\n/*\n * Copyright 2018 Kristian Evensen <kristian.evensen@gmail.com>\n */\n\n/dts-v1/;\n#include \"mt7623a-unielec-u7623-02.dtsi\"\n\n/ {\n\tmodel = \"UniElec U7623-02 eMMC\";\n\tcompatible = \"unielec,u7623-02\", \"mediatek,mt7623\";\n};\n"
  },
  {
    "path": "target/linux/mediatek/dts/mt7623a-unielec-u7623-02.dtsi",
    "content": "// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)\n/*\n * Copyright 2018 Kristian Evensen <kristian.evensen@gmail.com>\n */\n\n#include <dt-bindings/input/input.h>\n#include \"mt7623.dtsi\"\n#include \"mt6323.dtsi\"\n\n/ {\n\tcompatible = \"unielec,u7623-02\", \"mediatek,mt7623\";\n\n\taliases {\n\t\tserial0 = &uart2;\n\t\tethernet0 = &gmac0;\n\t\tmmc0 = &mmc0;\n\t\tled-boot = &led3_green;\n\t\tled-failsafe = &led3_green;\n\t\tled-running = &led3_green;\n\t\tled-upgrade = &led3_green;\n\t};\n\n\tchosen {\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\tcpus {\n\t\tcpu@0 {\n\t\t\tproc-supply = <&mt6323_vproc_reg>;\n\t\t};\n\n\t\tcpu@1 {\n\t\t\tproc-supply = <&mt6323_vproc_reg>;\n\t\t};\n\n\t\tcpu@2 {\n\t\t\tproc-supply = <&mt6323_vproc_reg>;\n\t\t};\n\n\t\tcpu@3 {\n\t\t\tproc-supply = <&mt6323_vproc_reg>;\n\t\t};\n\t};\n\n\treg_1p8v: regulator-1p8v {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"fixed-1.8V\";\n\t\tregulator-min-microvolt = <1800000>;\n\t\tregulator-max-microvolt = <1800000>;\n\t\tregulator-boot-on;\n\t\tregulator-always-on;\n\t};\n\n\treg_3p3v: regulator-3p3v {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"fixed-3.3V\";\n\t\tregulator-min-microvolt = <3300000>;\n\t\tregulator-max-microvolt = <3300000>;\n\t\tregulator-boot-on;\n\t\tregulator-always-on;\n\t};\n\n\treg_5v: regulator-5v {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"fixed-5V\";\n\t\tregulator-min-microvolt = <5000000>;\n\t\tregulator-max-microvolt = <5000000>;\n\t\tregulator-boot-on;\n\t\tregulator-always-on;\n\t};\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tpinctrl-names = \"default\";\n\t\tpinctrl-0 = <&key_pins_a>;\n\n\t\tfactory {\n\t\t\tlabel = \"factory\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&pio 256 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tpinctrl-names = \"default\";\n\t\tpinctrl-0 = <&led_pins_unielec>;\n\n\t\tled3_green: led3 {\n\t\t\tlabel = \"u7623-01:green:led3\";\n\t\t\tgpios = <&pio 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled4 {\n\t\t\tlabel = \"u7623-01:green:led4\";\n\t\t\tgpios = <&pio 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&crypto {\n\tstatus = \"okay\";\n};\n\n&eth {\n\tstatus = \"okay\";\n\n\tgmac0: mac@0 {\n\t\tcompatible = \"mediatek,eth-mac\";\n\t\treg = <0>;\n\t\tphy-mode = \"trgmii\";\n\n\t\tfixed-link {\n\t\t\tspeed = <1000>;\n\t\t\tfull-duplex;\n\t\t\tpause;\n\t\t};\n\t};\n\n\tmdio: mdio-bus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tmt7530: switch@0 {\n\t\t\tcompatible = \"mediatek,mt7530\";\n\t\t};\n\t};\n};\n\n&mt7530 {\n\tcompatible = \"mediatek,mt7530\";\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\treg = <0>;\n\tpinctrl-names = \"default\";\n\tmediatek,mcm;\n\tresets = <&ethsys 2>;\n\treset-names = \"mcm\";\n\tcore-supply = <&mt6323_vpa_reg>;\n\tio-supply = <&mt6323_vemc3v3_reg>;\n\n\tdsa,mii-bus = <&mdio>;\n\n\tports {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0>;\n\n\t\tport@0 {\n\t\t\treg = <0>;\n\t\t\tlabel = \"lan0\";\n\t\t\tcpu = <&cpu_port0>;\n\t\t};\n\n\t\tport@1 {\n\t\t\treg = <1>;\n\t\t\tlabel = \"lan1\";\n\t\t\tcpu = <&cpu_port0>;\n\t\t};\n\n\t\tport@2 {\n\t\t\treg = <2>;\n\t\t\tlabel = \"lan2\";\n\t\t\tcpu = <&cpu_port0>;\n\t\t};\n\n\t\tport@3 {\n\t\t\treg = <3>;\n\t\t\tlabel = \"lan3\";\n\t\t\tcpu = <&cpu_port0>;\n\t\t};\n\n\t\tport@4 {\n\t\t\treg = <4>;\n\t\t\tlabel = \"wan\";\n\t\t\tcpu = <&cpu_port0>;\n\t\t};\n\n\t\tcpu_port0: port@6 {\n\t\t\treg = <6>;\n\t\t\tlabel = \"cpu\";\n\t\t\tethernet = <&gmac0>;\n\t\t\tphy-mode = \"trgmii\";\n\n\t\t\tfixed-link {\n\t\t\t\tspeed = <1000>;\n\t\t\t\tfull-duplex;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&mmc0 {\n\tpinctrl-names = \"default\", \"state_uhs\";\n\tpinctrl-0 = <&mmc0_pins_default>;\n\tpinctrl-1 = <&mmc0_pins_uhs>;\n\tstatus = \"okay\";\n\tbus-width = <8>;\n\tmax-frequency = <50000000>;\n\tcap-mmc-highspeed;\n\tvmmc-supply = <&reg_3p3v>;\n\tvqmmc-supply = <&reg_1p8v>;\n\tnon-removable;\n};\n\n&pio {\n\tkey_pins_a: keys-alt {\n\t\tpins-keys {\n\t\t\tpinmux = <MT7623_PIN_256_GPIO256_FUNC_GPIO256>,\n\t\t\t\t <MT7623_PIN_257_GPIO257_FUNC_GPIO257>;\n\t\t\tinput-enable;\n\t\t};\n\t};\n\n\tled_pins_unielec: leds-unielec {\n\t\tpins-leds {\n\t\t\tpinmux = <MT7623_PIN_14_GPIO14_FUNC_GPIO14>,\n\t\t\t\t <MT7623_PIN_15_GPIO15_FUNC_GPIO15>;\n\t\t};\n\t};\n\n\tmmc0_pins_default: mmc0default {\n\t\tpins_cmd_dat {\n\t\t\tpinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>,\n\t\t\t\t <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>,\n\t\t\t\t <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>,\n\t\t\t\t <MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>,\n\t\t\t\t <MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>,\n\t\t\t\t <MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>,\n\t\t\t\t <MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>,\n\t\t\t\t <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>,\n\t\t\t\t <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>;\n\t\t\tinput-enable;\n\t\t\tbias-pull-up;\n\t\t};\n\n\t\tpins_clk {\n\t\t\tpinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>;\n\t\t\tbias-pull-down;\n\t\t};\n\n\t\tpins_rst {\n\t\t\tpinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>;\n\t\t\tbias-pull-up;\n\t\t};\n\t};\n\n\tmmc0_pins_uhs: mmc0 {\n\t\tpins_cmd_dat {\n\t\t\tpinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>,\n\t\t\t\t <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>,\n\t\t\t\t <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>,\n\t\t\t\t <MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>,\n\t\t\t\t <MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>,\n\t\t\t\t <MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>,\n\t\t\t\t <MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>,\n\t\t\t\t <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>,\n\t\t\t\t <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>;\n\t\t\tinput-enable;\n\t\t\tdrive-strength = <MTK_DRIVE_2mA>;\n\t\t\tbias-pull-up = <MTK_PUPD_SET_R1R0_01>;\n\t\t};\n\n\t\tpins_clk {\n\t\t\tpinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>;\n\t\t\tdrive-strength = <MTK_DRIVE_2mA>;\n\t\t\tbias-pull-down = <MTK_PUPD_SET_R1R0_01>;\n\t\t};\n\n\t\tpins_rst {\n\t\t\tpinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>;\n\t\t\tbias-pull-up;\n\t\t};\n\t};\n\n\tpcie_default: pcie_pin_default {\n\t\tpins_cmd_dat {\n\t\t\tpinmux = <MT7623_PIN_208_AUD_EXT_CK1_FUNC_PCIE0_PERST_N>,\n\t\t\t\t <MT7623_PIN_209_AUD_EXT_CK2_FUNC_PCIE1_PERST_N>;\n\t\t\tbias-disable;\n\t\t};\n\t};\n};\n\n&pwm {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pwm_pins_a>;\n\tstatus = \"okay\";\n};\n\n&pwrap {\n\tmt6323 {\n\t\tmt6323led: led {\n\t\t\tcompatible = \"mediatek,mt6323-led\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\n\t\t\tled@0 {\n\t\t\t\treg = <0>;\n\t\t\t\tlabel = \"led0\";\n\t\t\t};\n\t\t};\n\t};\n};\n\n&mt6323keys {\n\tmediatek,long-press-mode = <0>;\n};\n\n&uart2 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&uart2_pins_b>;\n\tstatus = \"okay\";\n};\n\n&usb1 {\n\tvusb33-supply = <&reg_3p3v>;\n\tvbus-supply = <&reg_3p3v>;\n\tstatus = \"okay\";\n};\n\n&u3phy1 {\n\tstatus = \"okay\";\n};\n\n&u3phy2 {\n\tstatus = \"okay\";\n\tmediatek,phy-switch = <&hifsys>;\n};\n\n&pcie {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pcie_default>;\n\tstatus = \"okay\";\n\n\tpcie@0,0 {\n\t\tstatus = \"okay\";\n\t};\n\n\tpcie@1,0 {\n\t\tstatus = \"okay\";\n\t};\n\n\tpcie@2,0 {\n\t\tstatus = \"okay\";\n\t};\n};\n\n&pcie0_phy {\n\tstatus = \"okay\";\n};\n\n&pcie1_phy {\n\tstatus = \"okay\";\n};\n\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/leds/leds-ubnt-ledbar.c",
    "content": "// SPDX-License-Identifier: GPL-2.0-only\n\n#include <linux/delay.h>\n#include <linux/i2c.h>\n#include <linux/init.h>\n#include <linux/leds.h>\n#include <linux/module.h>\n#include <linux/mutex.h>\n#include <linux/of.h>\n#include <linux/of_gpio.h>\n#include <linux/gpio/consumer.h>\n\n/**\n * Driver for the Ubiquiti RGB LED controller (LEDBAR).\n * This Controller is based on a Holtek HT32F52241 and connected\n * via I2C.\n *\n *  - The Controller needs an enable signal set to high when\n *    performing a transaction. On the U6-LR, this is located\n *    at Pin 18 (R6902)\n *\n *  - The Pin is also printed when calling the \"usetled\" function\n *    contained in the ubntapp bootloader application.\n */\n\n#define UBNT_LEDBAR_MAX_BRIGHTNESS\t0xff\n\n#define UBNT_LEDBAR_TRANSACTION_LENGTH\t8\n#define UBNT_LEDBAR_TRANSACTION_SUCCESS\t0xaa\n\n#define UBNT_LEDBAR_TRANSACTION_BLUE_IDX\t2\n#define UBNT_LEDBAR_TRANSACTION_GREEN_IDX\t3\n#define UBNT_LEDBAR_TRANSACTION_RED_IDX\t\t4\n\nstruct ubnt_ledbar {\n\tstruct mutex lock;\n\tstruct i2c_client *client;\n\tstruct led_classdev led_red;\n\tstruct led_classdev led_green;\n\tstruct led_classdev led_blue;\n\tstruct gpio_desc *enable_gpio;\n};\n\nstatic int ubnt_ledbar_perform_transaction(struct ubnt_ledbar *ledbar,\n\t\t\t\t\t   char *transaction)\n{\n\tint ret;\n\tint i;\n\n\tfor (i = 0; i < UBNT_LEDBAR_TRANSACTION_LENGTH; i++)\n\t\ti2c_smbus_write_byte(ledbar->client, transaction[i]);\n\n\treturn i2c_smbus_read_byte(ledbar->client);\n}\n\nstatic int ubnt_ledbar_apply_state(struct ubnt_ledbar *ledbar)\n{\n\tchar setup_msg[UBNT_LEDBAR_TRANSACTION_LENGTH] = {0x40, 0x10, 0x00, 0x00,\n\t\t\t\t\t\t\t  0x00, 0x00, 0x00, 0x11};\n\tchar led_msg[UBNT_LEDBAR_TRANSACTION_LENGTH] = {0x40, 0x00, 0x00, 0x00,\n\t\t\t\t\t\t\t0x00, 0x00, 0x01, 0x00};\n\tchar i2c_response;\n\tint ret = 0;\n\n\tmutex_lock(&ledbar->lock);\n\n\tled_msg[UBNT_LEDBAR_TRANSACTION_BLUE_IDX] = ledbar->led_blue.brightness;\n\tled_msg[UBNT_LEDBAR_TRANSACTION_GREEN_IDX] = ledbar->led_green.brightness;\n\tled_msg[UBNT_LEDBAR_TRANSACTION_RED_IDX] = ledbar->led_red.brightness;\n\n\tgpiod_set_raw_value(ledbar->enable_gpio, 1);\n\n\tmsleep(10);\n\n\ti2c_response = ubnt_ledbar_perform_transaction(ledbar, setup_msg);\n\tif (i2c_response != UBNT_LEDBAR_TRANSACTION_SUCCESS) {\n\t\tdev_err(&ledbar->client->dev, \"Error initializing LED transaction: %02x\\n\", ret);\n\t\tret = -EINVAL;\n\t\tgoto out_gpio;\n\t}\n\n\ti2c_response = ubnt_ledbar_perform_transaction(ledbar, led_msg);\n\tif (i2c_response != UBNT_LEDBAR_TRANSACTION_SUCCESS) {\n\t\tdev_err(&ledbar->client->dev, \"Failed LED transaction: %02x\\n\", ret);\n\t\tret = -EINVAL;\n\t\tgoto out_gpio;\n\t}\n\n\tmsleep(10);\nout_gpio:\n\tgpiod_set_raw_value(ledbar->enable_gpio, 0);\n\n\tmutex_unlock(&ledbar->lock);\n\n\treturn ret;\n}\n\n#define UBNT_LEDBAR_CONTROL_RGBS(name)\t\t\t\t\\\nstatic int ubnt_ledbar_set_##name##_brightness(struct led_classdev *led_cdev,\\\n\t\t\t\t\tenum led_brightness value)\t\\\n{\t\t\t\t\t\t\t\t\t\\\n\tstruct ubnt_ledbar *ledbar = \\\n\t\t\tcontainer_of(led_cdev, struct ubnt_ledbar, led_##name); \\\n\tint ret; \\\n\tled_cdev->brightness = value; \\\n\tret = ubnt_ledbar_apply_state(ledbar); \\\n\treturn ret; \\\n}\n\nUBNT_LEDBAR_CONTROL_RGBS(red);\nUBNT_LEDBAR_CONTROL_RGBS(green);\nUBNT_LEDBAR_CONTROL_RGBS(blue);\n\n\nstatic int ubnt_ledbar_init_led(struct device_node *np, struct ubnt_ledbar *ledbar,\n\t\t\t\tstruct led_classdev *led_cdev)\n{\n\tstruct led_init_data init_data = {};\n\tint ret;\n\n\tif (!np)\n\t\treturn 0;\n\n\tinit_data.fwnode = of_fwnode_handle(np);\n\n\tled_cdev->max_brightness = UBNT_LEDBAR_MAX_BRIGHTNESS;\n\n\tret = devm_led_classdev_register_ext(&ledbar->client->dev, led_cdev,\n\t\t\t\t\t     &init_data);\n\tif (ret)\n\t\tdev_err(&ledbar->client->dev, \"led register err: %d\\n\", ret);\n\n\treturn ret;\n}\n\n\nstatic int ubnt_ledbar_probe(struct i2c_client *client,\n\t\t\t     const struct i2c_device_id *id)\n{\n\tstruct device_node *np = client->dev.of_node;\n\tstruct ubnt_ledbar *ledbar;\n\tint ret;\n\n\tledbar = devm_kzalloc(&client->dev, sizeof(*ledbar), GFP_KERNEL);\n\tif (!ledbar)\n\t\treturn -ENOMEM;\n\n\tledbar->enable_gpio = devm_gpiod_get(&client->dev, \"enable\", GPIOD_OUT_LOW);\n\n\tif (IS_ERR(ledbar->enable_gpio)) {\n\t\tret = PTR_ERR(ledbar->enable_gpio);\n\t\tdev_err(&client->dev, \"Failed to get enable gpio: %d\\n\", ret);\n\t\treturn ret;\n\t}\n\n\tgpiod_direction_output(ledbar->enable_gpio, 0);\n\n\tledbar->client = client;\n\n\tmutex_init(&ledbar->lock);\n\n\ti2c_set_clientdata(client, ledbar);\n\n\tledbar->led_red.brightness_set_blocking = ubnt_ledbar_set_red_brightness;\n\tubnt_ledbar_init_led(of_get_child_by_name(np, \"red\"), ledbar, &ledbar->led_red);\n\n\tledbar->led_green.brightness_set_blocking = ubnt_ledbar_set_green_brightness;\n\tubnt_ledbar_init_led(of_get_child_by_name(np, \"green\"), ledbar, &ledbar->led_green);\n\n\tledbar->led_blue.brightness_set_blocking = ubnt_ledbar_set_blue_brightness;\n\tubnt_ledbar_init_led(of_get_child_by_name(np, \"blue\"), ledbar, &ledbar->led_blue);\n\n\treturn ubnt_ledbar_apply_state(ledbar);\n}\n\nstatic int ubnt_ledbar_remove(struct i2c_client *client)\n{\n\tstruct ubnt_ledbar *ledbar = i2c_get_clientdata(client);\n\n\tmutex_destroy(&ledbar->lock);\n\n\treturn 0;\n}\n\nstatic const struct i2c_device_id ubnt_ledbar_id[] = {\n\t{ \"ubnt-ledbar\", 0 },\n\t{ }\n};\nMODULE_DEVICE_TABLE(i2c, ubnt_ledbar_id);\n\nstatic const struct of_device_id of_ubnt_ledbar_match[] = {\n\t{ .compatible = \"ubnt,ledbar\", },\n\t{},\n};\nMODULE_DEVICE_TABLE(of, of_ubnt_ledbar_match);\n\nstatic struct i2c_driver ubnt_ledbar_driver = {\n\t.driver = {\n\t\t.name\t= \"ubnt-ledbar\",\n\t\t.of_match_table = of_ubnt_ledbar_match,\n\t},\n\t.probe\t\t= ubnt_ledbar_probe,\n\t.remove\t\t= ubnt_ledbar_remove,\n\t.id_table\t= ubnt_ledbar_id,\n};\nmodule_i2c_driver(ubnt_ledbar_driver);\n\nMODULE_DESCRIPTION(\"Ubiquiti LEDBAR driver\");\nMODULE_AUTHOR(\"David Bauer <mail@david-bauer.net>\");\nMODULE_LICENSE(\"GPL v2\");\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/mtk/mt753x/Kconfig",
    "content": "\nconfig MT753X_GSW\n\ttristate \"Driver for the MediaTek MT753x switch\"\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/mtk/mt753x/Makefile",
    "content": "#\n# Makefile for MediaTek MT753x gigabit switch\n#\n\nobj-$(CONFIG_MT753X_GSW)\t+= mt753x.o\n\nmt753x-$(CONFIG_SWCONFIG)\t+= mt753x_swconfig.o\n\nmt753x-y\t\t\t+= mt753x_mdio.o mt7530.o mt7531.o \\\n\t\t\t\t\tmt753x_common.o mt753x_vlan.o \\\n\t\t\t\t\tmt753x_nl.o\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/mtk/mt753x/mt7530.c",
    "content": "// SPDX-License-Identifier: GPL-2.0-only\n/*\n * Copyright (c) 2018 MediaTek Inc.\n * Author: Weijie Gao <weijie.gao@mediatek.com>\n */\n\n#include <linux/kernel.h>\n#include <linux/delay.h>\n\n#include \"mt753x.h\"\n#include \"mt753x_regs.h\"\n\n/* MT7530 registers */\n\n/* Unique fields of PMCR for MT7530 */\n#define FORCE_MODE\t\t\tBIT(15)\n\n/* Unique fields of GMACCR for MT7530 */\n#define VLAN_SUPT_NO_S\t\t\t14\n#define VLAN_SUPT_NO_M\t\t\t0x1c000\n#define LATE_COL_DROP\t\t\tBIT(13)\n\n/* Unique fields of (M)HWSTRAP for MT7530 */\n#define BOND_OPTION\t\t\tBIT(24)\n#define P5_PHY0_SEL\t\t\tBIT(20)\n#define CHG_TRAP\t\t\tBIT(16)\n#define LOOPDET_DIS\t\t\tBIT(14)\n#define P5_INTF_SEL_GMAC5\t\tBIT(13)\n#define SMI_ADDR_S\t\t\t11\n#define SMI_ADDR_M\t\t\t0x1800\n#define XTAL_FSEL_S\t\t\t9\n#define XTAL_FSEL_M\t\t\t0x600\n#define P6_INTF_DIS\t\t\tBIT(8)\n#define P5_INTF_MODE_RGMII\t\tBIT(7)\n#define P5_INTF_DIS_S\t\t\tBIT(6)\n#define C_MDIO_BPS_S\t\t\tBIT(5)\n#define EEPROM_EN_S\t\t\tBIT(4)\n\n/* PHY EEE Register bitmap of define */\n#define PHY_DEV07\t\t\t0x07\n#define PHY_DEV07_REG_03C\t\t0x3c\n\n/* PHY Extend Register 0x14 bitmap of define */\n#define PHY_EXT_REG_14\t\t\t0x14\n\n/* Fields of PHY_EXT_REG_14 */\n#define PHY_EN_DOWN_SHFIT\t\tBIT(4)\n\n/* PHY Token Ring Register 0x10 bitmap of define */\n#define PHY_TR_REG_10\t\t\t0x10\n\n/* PHY Token Ring Register 0x12 bitmap of define */\n#define PHY_TR_REG_12\t\t\t0x12\n\n/* PHY LPI PCS/DSP Control Register bitmap of define */\n#define PHY_LPI_REG_11\t\t\t0x11\n\n/* PHY DEV 0x1e Register bitmap of define */\n#define PHY_DEV1E\t\t\t0x1e\n#define PHY_DEV1E_REG_123\t\t0x123\n#define PHY_DEV1E_REG_A6\t\t0xa6\n\n/* Values of XTAL_FSEL */\n#define XTAL_20MHZ\t\t\t1\n#define XTAL_40MHZ\t\t\t2\n#define XTAL_25MHZ\t\t\t3\n\n#define P6ECR\t\t\t\t0x7830\n#define P6_INTF_MODE_TRGMII\t\tBIT(0)\n\n#define TRGMII_TXCTRL\t\t\t0x7a40\n#define TRAIN_TXEN\t\t\tBIT(31)\n#define TXC_INV\t\t\t\tBIT(30)\n#define TX_DOEO\t\t\t\tBIT(29)\n#define TX_RST\t\t\t\tBIT(28)\n\n#define TRGMII_TD0_CTRL\t\t\t0x7a50\n#define TRGMII_TD1_CTRL\t\t\t0x7a58\n#define TRGMII_TD2_CTRL\t\t\t0x7a60\n#define TRGMII_TD3_CTRL\t\t\t0x7a68\n#define TRGMII_TXCTL_CTRL\t\t0x7a70\n#define TRGMII_TCK_CTRL\t\t\t0x7a78\n#define TRGMII_TD_CTRL(n)\t\t(0x7a50 + (n) * 8)\n#define NUM_TRGMII_CTRL\t\t\t6\n#define TX_DMPEDRV\t\t\tBIT(31)\n#define TX_DM_SR\t\t\tBIT(15)\n#define TX_DMERODT\t\t\tBIT(14)\n#define TX_DMOECTL\t\t\tBIT(13)\n#define TX_TAP_S\t\t\t8\n#define TX_TAP_M\t\t\t0xf00\n#define TX_TRAIN_WD_S\t\t\t0\n#define TX_TRAIN_WD_M\t\t\t0xff\n\n#define TRGMII_TD0_ODT\t\t\t0x7a54\n#define TRGMII_TD1_ODT\t\t\t0x7a5c\n#define TRGMII_TD2_ODT\t\t\t0x7a64\n#define TRGMII_TD3_ODT\t\t\t0x7a6c\n#define TRGMII_TXCTL_ODT\t\t0x7574\n#define TRGMII_TCK_ODT\t\t\t0x757c\n#define TRGMII_TD_ODT(n)\t\t(0x7a54 + (n) * 8)\n#define NUM_TRGMII_ODT\t\t\t6\n#define TX_DM_DRVN_PRE_S\t\t30\n#define TX_DM_DRVN_PRE_M\t\t0xc0000000\n#define TX_DM_DRVP_PRE_S\t\t28\n#define TX_DM_DRVP_PRE_M\t\t0x30000000\n#define TX_DM_TDSEL_S\t\t\t24\n#define TX_DM_TDSEL_M\t\t\t0xf000000\n#define TX_ODTEN\t\t\tBIT(23)\n#define TX_DME_PRE\t\t\tBIT(20)\n#define TX_DM_DRVNT0\t\t\tBIT(19)\n#define TX_DM_DRVPT0\t\t\tBIT(18)\n#define TX_DM_DRVNTE\t\t\tBIT(17)\n#define TX_DM_DRVPTE\t\t\tBIT(16)\n#define TX_DM_ODTN_S\t\t\t12\n#define TX_DM_ODTN_M\t\t\t0x7000\n#define TX_DM_ODTP_S\t\t\t8\n#define TX_DM_ODTP_M\t\t\t0x700\n#define TX_DM_DRVN_S\t\t\t4\n#define TX_DM_DRVN_M\t\t\t0xf0\n#define TX_DM_DRVP_S\t\t\t0\n#define TX_DM_DRVP_M\t\t\t0x0f\n\n#define P5RGMIIRXCR\t\t\t0x7b00\n#define CSR_RGMII_RCTL_CFG_S\t\t24\n#define CSR_RGMII_RCTL_CFG_M\t\t0x7000000\n#define CSR_RGMII_RXD_CFG_S\t\t16\n#define CSR_RGMII_RXD_CFG_M\t\t0x70000\n#define CSR_RGMII_EDGE_ALIGN\t\tBIT(8)\n#define CSR_RGMII_RXC_90DEG_CFG_S\t4\n#define CSR_RGMII_RXC_90DEG_CFG_M\t0xf0\n#define CSR_RGMII_RXC_0DEG_CFG_S\t0\n#define CSR_RGMII_RXC_0DEG_CFG_M\t0x0f\n\n#define P5RGMIITXCR\t\t\t0x7b04\n#define CSR_RGMII_TXEN_CFG_S\t\t16\n#define CSR_RGMII_TXEN_CFG_M\t\t0x70000\n#define CSR_RGMII_TXD_CFG_S\t\t8\n#define CSR_RGMII_TXD_CFG_M\t\t0x700\n#define CSR_RGMII_TXC_CFG_S\t\t0\n#define CSR_RGMII_TXC_CFG_M\t\t0x1f\n\n#define CHIP_REV\t\t\t0x7ffc\n#define CHIP_NAME_S\t\t\t16\n#define CHIP_NAME_M\t\t\t0xffff0000\n#define CHIP_REV_S\t\t\t0\n#define CHIP_REV_M\t\t\t0x0f\n\n/* MMD registers */\n#define CORE_PLL_GROUP2\t\t\t0x401\n#define RG_SYSPLL_EN_NORMAL\t\tBIT(15)\n#define RG_SYSPLL_VODEN\t\t\tBIT(14)\n#define RG_SYSPLL_POSDIV_S\t\t5\n#define RG_SYSPLL_POSDIV_M\t\t0x60\n\n#define CORE_PLL_GROUP4\t\t\t0x403\n#define RG_SYSPLL_DDSFBK_EN\t\tBIT(12)\n#define RG_SYSPLL_BIAS_EN\t\tBIT(11)\n#define RG_SYSPLL_BIAS_LPF_EN\t\tBIT(10)\n\n#define CORE_PLL_GROUP5\t\t\t0x404\n#define RG_LCDDS_PCW_NCPO1_S\t\t0\n#define RG_LCDDS_PCW_NCPO1_M\t\t0xffff\n\n#define CORE_PLL_GROUP6\t\t\t0x405\n#define RG_LCDDS_PCW_NCPO0_S\t\t0\n#define RG_LCDDS_PCW_NCPO0_M\t\t0xffff\n\n#define CORE_PLL_GROUP7\t\t\t0x406\n#define RG_LCDDS_PWDB\t\t\tBIT(15)\n#define RG_LCDDS_ISO_EN\t\t\tBIT(13)\n#define RG_LCCDS_C_S\t\t\t4\n#define RG_LCCDS_C_M\t\t\t0x70\n#define RG_LCDDS_PCW_NCPO_CHG\t\tBIT(3)\n\n#define CORE_PLL_GROUP10\t\t0x409\n#define RG_LCDDS_SSC_DELTA_S\t\t0\n#define RG_LCDDS_SSC_DELTA_M\t\t0xfff\n\n#define CORE_PLL_GROUP11\t\t0x40a\n#define RG_LCDDS_SSC_DELTA1_S\t\t0\n#define RG_LCDDS_SSC_DELTA1_M\t\t0xfff\n\n#define CORE_GSWPLL_GCR_1\t\t0x040d\n#define GSWPLL_PREDIV_S\t\t\t14\n#define GSWPLL_PREDIV_M\t\t\t0xc000\n#define GSWPLL_POSTDIV_200M_S\t\t12\n#define GSWPLL_POSTDIV_200M_M\t\t0x3000\n#define GSWPLL_EN_PRE\t\t\tBIT(11)\n#define GSWPLL_FBKSEL\t\t\tBIT(10)\n#define GSWPLL_BP\t\t\tBIT(9)\n#define GSWPLL_BR\t\t\tBIT(8)\n#define GSWPLL_FBKDIV_200M_S\t\t0\n#define GSWPLL_FBKDIV_200M_M\t\t0xff\n\n#define CORE_GSWPLL_GCR_2\t\t0x040e\n#define GSWPLL_POSTDIV_500M_S\t\t8\n#define GSWPLL_POSTDIV_500M_M\t\t0x300\n#define GSWPLL_FBKDIV_500M_S\t\t0\n#define GSWPLL_FBKDIV_500M_M\t\t0xff\n\n#define TRGMII_GSW_CLK_CG\t\t0x0410\n#define TRGMIICK_EN\t\t\tBIT(1)\n#define GSWCK_EN\t\t\tBIT(0)\n\nstatic int mt7530_mii_read(struct gsw_mt753x *gsw, int phy, int reg)\n{\n\tif (phy < MT753X_NUM_PHYS)\n\t\tphy = (gsw->phy_base + phy) & MT753X_SMI_ADDR_MASK;\n\n\treturn mdiobus_read(gsw->host_bus, phy, reg);\n}\n\nstatic void mt7530_mii_write(struct gsw_mt753x *gsw, int phy, int reg, u16 val)\n{\n\tif (phy < MT753X_NUM_PHYS)\n\t\tphy = (gsw->phy_base + phy) & MT753X_SMI_ADDR_MASK;\n\n\tmdiobus_write(gsw->host_bus, phy, reg, val);\n}\n\nstatic int mt7530_mmd_read(struct gsw_mt753x *gsw, int addr, int devad, u16 reg)\n{\n\tu16 val;\n\n\tif (addr < MT753X_NUM_PHYS)\n\t\taddr = (gsw->phy_base + addr) & MT753X_SMI_ADDR_MASK;\n\n\tmutex_lock(&gsw->host_bus->mdio_lock);\n\n\tgsw->host_bus->write(gsw->host_bus, addr, MII_MMD_ACC_CTL_REG,\n\t\t\t     (MMD_ADDR << MMD_CMD_S) |\n\t\t\t     ((devad << MMD_DEVAD_S) & MMD_DEVAD_M));\n\n\tgsw->host_bus->write(gsw->host_bus, addr, MII_MMD_ADDR_DATA_REG, reg);\n\n\tgsw->host_bus->write(gsw->host_bus, addr, MII_MMD_ACC_CTL_REG,\n\t\t\t     (MMD_DATA << MMD_CMD_S) |\n\t\t\t     ((devad << MMD_DEVAD_S) & MMD_DEVAD_M));\n\n\tval = gsw->host_bus->read(gsw->host_bus, addr, MII_MMD_ADDR_DATA_REG);\n\n\tmutex_unlock(&gsw->host_bus->mdio_lock);\n\n\treturn val;\n}\n\nstatic void mt7530_mmd_write(struct gsw_mt753x *gsw, int addr, int devad,\n\t\t\t     u16 reg, u16 val)\n{\n\tif (addr < MT753X_NUM_PHYS)\n\t\taddr = (gsw->phy_base + addr) & MT753X_SMI_ADDR_MASK;\n\n\tmutex_lock(&gsw->host_bus->mdio_lock);\n\n\tgsw->host_bus->write(gsw->host_bus, addr, MII_MMD_ACC_CTL_REG,\n\t\t      (MMD_ADDR << MMD_CMD_S) |\n\t\t      ((devad << MMD_DEVAD_S) & MMD_DEVAD_M));\n\n\tgsw->host_bus->write(gsw->host_bus, addr, MII_MMD_ADDR_DATA_REG, reg);\n\n\tgsw->host_bus->write(gsw->host_bus, addr, MII_MMD_ACC_CTL_REG,\n\t\t      (MMD_DATA << MMD_CMD_S) |\n\t\t      ((devad << MMD_DEVAD_S) & MMD_DEVAD_M));\n\n\tgsw->host_bus->write(gsw->host_bus, addr, MII_MMD_ADDR_DATA_REG, val);\n\n\tmutex_unlock(&gsw->host_bus->mdio_lock);\n}\n\nstatic void mt7530_core_reg_write(struct gsw_mt753x *gsw, u32 reg, u32 val)\n{\n\tgsw->mmd_write(gsw, 0, 0x1f, reg, val);\n}\n\nstatic void mt7530_trgmii_setting(struct gsw_mt753x *gsw)\n{\n\tu16 i;\n\n\tmt7530_core_reg_write(gsw, CORE_PLL_GROUP5, 0x0780);\n\tmdelay(1);\n\tmt7530_core_reg_write(gsw, CORE_PLL_GROUP6, 0);\n\tmt7530_core_reg_write(gsw, CORE_PLL_GROUP10, 0x87);\n\tmdelay(1);\n\tmt7530_core_reg_write(gsw, CORE_PLL_GROUP11, 0x87);\n\n\t/* PLL BIAS enable */\n\tmt7530_core_reg_write(gsw, CORE_PLL_GROUP4,\n\t\t\t      RG_SYSPLL_DDSFBK_EN | RG_SYSPLL_BIAS_EN);\n\tmdelay(1);\n\n\t/* PLL LPF enable */\n\tmt7530_core_reg_write(gsw, CORE_PLL_GROUP4,\n\t\t\t      RG_SYSPLL_DDSFBK_EN |\n\t\t\t      RG_SYSPLL_BIAS_EN | RG_SYSPLL_BIAS_LPF_EN);\n\n\t/* sys PLL enable */\n\tmt7530_core_reg_write(gsw, CORE_PLL_GROUP2,\n\t\t\t      RG_SYSPLL_EN_NORMAL | RG_SYSPLL_VODEN |\n\t\t\t      (1 << RG_SYSPLL_POSDIV_S));\n\n\t/* LCDDDS PWDS */\n\tmt7530_core_reg_write(gsw, CORE_PLL_GROUP7,\n\t\t\t      (3 << RG_LCCDS_C_S) |\n\t\t\t      RG_LCDDS_PWDB | RG_LCDDS_ISO_EN);\n\tmdelay(1);\n\n\t/* Enable MT7530 TRGMII clock */\n\tmt7530_core_reg_write(gsw, TRGMII_GSW_CLK_CG, GSWCK_EN | TRGMIICK_EN);\n\n\t/* lower Tx Driving */\n\tfor (i = 0 ; i < NUM_TRGMII_ODT; i++)\n\t\tmt753x_reg_write(gsw, TRGMII_TD_ODT(i),\n\t\t\t\t (4 << TX_DM_DRVP_S) | (4 << TX_DM_DRVN_S));\n}\n\nstatic void mt7530_rgmii_setting(struct gsw_mt753x *gsw)\n{\n\tu32 val;\n\n\tmt7530_core_reg_write(gsw, CORE_PLL_GROUP5, 0x0c80);\n\tmdelay(1);\n\tmt7530_core_reg_write(gsw, CORE_PLL_GROUP6, 0);\n\tmt7530_core_reg_write(gsw, CORE_PLL_GROUP10, 0x87);\n\tmdelay(1);\n\tmt7530_core_reg_write(gsw, CORE_PLL_GROUP11, 0x87);\n\n\tval = mt753x_reg_read(gsw, TRGMII_TXCTRL);\n\tval &= ~TXC_INV;\n\tmt753x_reg_write(gsw, TRGMII_TXCTRL, val);\n\n\tmt753x_reg_write(gsw, TRGMII_TCK_CTRL,\n\t\t\t (8 << TX_TAP_S) | (0x55 << TX_TRAIN_WD_S));\n}\n\nstatic int mt7530_mac_port_setup(struct gsw_mt753x *gsw)\n{\n\tu32 hwstrap, p6ecr = 0, p5mcr, p6mcr, phyad;\n\n\thwstrap = mt753x_reg_read(gsw, MHWSTRAP);\n\thwstrap &= ~(P6_INTF_DIS | P5_INTF_MODE_RGMII | P5_INTF_DIS_S);\n\thwstrap |= P5_INTF_SEL_GMAC5;\n\tif (!gsw->port5_cfg.enabled) {\n\t\tp5mcr = FORCE_MODE;\n\t\thwstrap |= P5_INTF_DIS_S;\n\t} else {\n\t\tp5mcr = (IPG_96BIT_WITH_SHORT_IPG << IPG_CFG_S) |\n\t\t\tMAC_MODE | MAC_TX_EN | MAC_RX_EN |\n\t\t\tBKOFF_EN | BACKPR_EN;\n\n\t\tif (gsw->port5_cfg.force_link) {\n\t\t\tp5mcr |= FORCE_MODE | FORCE_LINK | FORCE_RX_FC |\n\t\t\t\t FORCE_TX_FC;\n\t\t\tp5mcr |= gsw->port5_cfg.speed << FORCE_SPD_S;\n\n\t\t\tif (gsw->port5_cfg.duplex)\n\t\t\t\tp5mcr |= FORCE_DPX;\n\t\t}\n\n\t\tswitch (gsw->port5_cfg.phy_mode) {\n\t\tcase PHY_INTERFACE_MODE_MII:\n\t\tcase PHY_INTERFACE_MODE_GMII:\n\t\t\tbreak;\n\t\tcase PHY_INTERFACE_MODE_RGMII:\n\t\t\thwstrap |= P5_INTF_MODE_RGMII;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tdev_info(gsw->dev, \"%s is not supported by port5\\n\",\n\t\t\t\t phy_modes(gsw->port5_cfg.phy_mode));\n\t\t\tp5mcr = FORCE_MODE;\n\t\t\thwstrap |= P5_INTF_DIS_S;\n\t\t}\n\n\t\t/* Port5 to PHY direct mode */\n\t\tif (of_property_read_u32(gsw->port5_cfg.np, \"phy-address\",\n\t\t\t\t\t &phyad))\n\t\t\tgoto parse_p6;\n\n\t\tif (phyad != 0 && phyad != 4) {\n\t\t\tdev_info(gsw->dev,\n\t\t\t\t \"Only PHY 0/4 can be connected to Port 5\\n\");\n\t\t\tgoto parse_p6;\n\t\t}\n\n\t\thwstrap &= ~P5_INTF_SEL_GMAC5;\n\t\tif (phyad == 0)\n\t\t\thwstrap |= P5_PHY0_SEL;\n\t\telse\n\t\t\thwstrap &= ~P5_PHY0_SEL;\n\t}\n\nparse_p6:\n\tif (!gsw->port6_cfg.enabled) {\n\t\tp6mcr = FORCE_MODE;\n\t\thwstrap |= P6_INTF_DIS;\n\t} else {\n\t\tp6mcr = (IPG_96BIT_WITH_SHORT_IPG << IPG_CFG_S) |\n\t\t\tMAC_MODE | MAC_TX_EN | MAC_RX_EN |\n\t\t\tBKOFF_EN | BACKPR_EN;\n\n\t\tif (gsw->port6_cfg.force_link) {\n\t\t\tp6mcr |= FORCE_MODE | FORCE_LINK | FORCE_RX_FC |\n\t\t\t\t FORCE_TX_FC;\n\t\t\tp6mcr |= gsw->port6_cfg.speed << FORCE_SPD_S;\n\n\t\t\tif (gsw->port6_cfg.duplex)\n\t\t\t\tp6mcr |= FORCE_DPX;\n\t\t}\n\n\t\tswitch (gsw->port6_cfg.phy_mode) {\n\t\tcase PHY_INTERFACE_MODE_RGMII:\n\t\t\tp6ecr = BIT(1);\n\t\t\tbreak;\n\t\tcase PHY_INTERFACE_MODE_TRGMII:\n\t\t\t/* set MT7530 central align */\n\t\t\tp6ecr = BIT(0);\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tdev_info(gsw->dev, \"%s is not supported by port6\\n\",\n\t\t\t\t phy_modes(gsw->port6_cfg.phy_mode));\n\t\t\tp6mcr = FORCE_MODE;\n\t\t\thwstrap |= P6_INTF_DIS;\n\t\t}\n\t}\n\n\tmt753x_reg_write(gsw, MHWSTRAP, hwstrap);\n\tmt753x_reg_write(gsw, P6ECR, p6ecr);\n\n\tmt753x_reg_write(gsw, PMCR(5), p5mcr);\n\tmt753x_reg_write(gsw, PMCR(6), p6mcr);\n\n\treturn 0;\n}\n\nstatic void mt7530_core_pll_setup(struct gsw_mt753x *gsw)\n{\n\tu32 hwstrap;\n\n\thwstrap = mt753x_reg_read(gsw, HWSTRAP);\n\n\tswitch ((hwstrap & XTAL_FSEL_M) >> XTAL_FSEL_S) {\n\tcase XTAL_40MHZ:\n\t\t/* Disable MT7530 core clock */\n\t\tmt7530_core_reg_write(gsw, TRGMII_GSW_CLK_CG, 0);\n\n\t\t/* disable MT7530 PLL */\n\t\tmt7530_core_reg_write(gsw, CORE_GSWPLL_GCR_1,\n\t\t\t\t      (2 << GSWPLL_POSTDIV_200M_S) |\n\t\t\t\t      (32 << GSWPLL_FBKDIV_200M_S));\n\n\t\t/* For MT7530 core clock = 500Mhz */\n\t\tmt7530_core_reg_write(gsw, CORE_GSWPLL_GCR_2,\n\t\t\t\t      (1 << GSWPLL_POSTDIV_500M_S) |\n\t\t\t\t      (25 << GSWPLL_FBKDIV_500M_S));\n\n\t\t/* Enable MT7530 PLL */\n\t\tmt7530_core_reg_write(gsw, CORE_GSWPLL_GCR_1,\n\t\t\t\t      (2 << GSWPLL_POSTDIV_200M_S) |\n\t\t\t\t      (32 << GSWPLL_FBKDIV_200M_S) |\n\t\t\t\t      GSWPLL_EN_PRE);\n\n\t\tusleep_range(20, 40);\n\n\t\t/* Enable MT7530 core clock */\n\t\tmt7530_core_reg_write(gsw, TRGMII_GSW_CLK_CG, GSWCK_EN);\n\t\tbreak;\n\tdefault:\n\t\t/* TODO: PLL settings for 20/25MHz */\n\t\tbreak;\n\t}\n\n\thwstrap = mt753x_reg_read(gsw, HWSTRAP);\n\thwstrap |= CHG_TRAP;\n\tif (gsw->direct_phy_access)\n\t\thwstrap &= ~C_MDIO_BPS_S;\n\telse\n\t\thwstrap |= C_MDIO_BPS_S;\n\n\tmt753x_reg_write(gsw, MHWSTRAP, hwstrap);\n\n\tif (gsw->port6_cfg.enabled &&\n\t    gsw->port6_cfg.phy_mode == PHY_INTERFACE_MODE_TRGMII) {\n\t\tmt7530_trgmii_setting(gsw);\n\t} else {\n\t\t/* RGMII */\n\t\tmt7530_rgmii_setting(gsw);\n\t}\n\n\t/* delay setting for 10/1000M */\n\tmt753x_reg_write(gsw, P5RGMIIRXCR,\n\t\t\t CSR_RGMII_EDGE_ALIGN |\n\t\t\t (2 << CSR_RGMII_RXC_0DEG_CFG_S));\n\tmt753x_reg_write(gsw, P5RGMIITXCR, 0x14 << CSR_RGMII_TXC_CFG_S);\n}\n\nstatic int mt7530_sw_detect(struct gsw_mt753x *gsw, struct chip_rev *crev)\n{\n\tu32 rev;\n\n\trev = mt753x_reg_read(gsw, CHIP_REV);\n\n\tif (((rev & CHIP_NAME_M) >> CHIP_NAME_S) == MT7530) {\n\t\tif (crev) {\n\t\t\tcrev->rev = rev & CHIP_REV_M;\n\t\t\tcrev->name = \"MT7530\";\n\t\t}\n\n\t\treturn 0;\n\t}\n\n\treturn -ENODEV;\n}\n\nstatic void mt7530_phy_setting(struct gsw_mt753x *gsw)\n{\n\tint i;\n\tu32 val;\n\n\tfor (i = 0; i < MT753X_NUM_PHYS; i++) {\n\t\t/* Disable EEE */\n\t\tgsw->mmd_write(gsw, i, PHY_DEV07, PHY_DEV07_REG_03C, 0);\n\n\t\t/* Enable HW auto downshift */\n\t\tgsw->mii_write(gsw, i, 0x1f, 0x1);\n\t\tval = gsw->mii_read(gsw, i, PHY_EXT_REG_14);\n\t\tval |= PHY_EN_DOWN_SHFIT;\n\t\tgsw->mii_write(gsw, i, PHY_EXT_REG_14, val);\n\n\t\t/* Increase SlvDPSready time */\n\t\tgsw->mii_write(gsw, i, 0x1f, 0x52b5);\n\t\tgsw->mii_write(gsw, i, PHY_TR_REG_10, 0xafae);\n\t\tgsw->mii_write(gsw, i, PHY_TR_REG_12, 0x2f);\n\t\tgsw->mii_write(gsw, i, PHY_TR_REG_10, 0x8fae);\n\n\t\t/* Increase post_update_timer */\n\t\tgsw->mii_write(gsw, i, 0x1f, 0x3);\n\t\tgsw->mii_write(gsw, i, PHY_LPI_REG_11, 0x4b);\n\t\tgsw->mii_write(gsw, i, 0x1f, 0);\n\n\t\t/* Adjust 100_mse_threshold */\n\t\tgsw->mmd_write(gsw, i, PHY_DEV1E, PHY_DEV1E_REG_123, 0xffff);\n\n\t\t/* Disable mcc */\n\t\tgsw->mmd_write(gsw, i, PHY_DEV1E, PHY_DEV1E_REG_A6, 0x300);\n\t}\n}\n\nstatic inline bool get_phy_access_mode(const struct device_node *np)\n{\n\treturn of_property_read_bool(np, \"mt7530,direct-phy-access\");\n}\n\nstatic int mt7530_sw_init(struct gsw_mt753x *gsw)\n{\n\tint i;\n\tu32 val;\n\n\tgsw->direct_phy_access = get_phy_access_mode(gsw->dev->of_node);\n\n\t/* Force MT7530 to use (in)direct PHY access */\n\tval = mt753x_reg_read(gsw, HWSTRAP);\n\tval |= CHG_TRAP;\n\tif (gsw->direct_phy_access)\n\t\tval &= ~C_MDIO_BPS_S;\n\telse\n\t\tval |= C_MDIO_BPS_S;\n\tmt753x_reg_write(gsw, MHWSTRAP, val);\n\n\t/* Read PHY address base from HWSTRAP */\n\tgsw->phy_base  = (((val & SMI_ADDR_M) >> SMI_ADDR_S) << 3) + 8;\n\tgsw->phy_base &= MT753X_SMI_ADDR_MASK;\n\n\tif (gsw->direct_phy_access) {\n\t\tgsw->mii_read = mt7530_mii_read;\n\t\tgsw->mii_write = mt7530_mii_write;\n\t\tgsw->mmd_read = mt7530_mmd_read;\n\t\tgsw->mmd_write = mt7530_mmd_write;\n\t} else {\n\t\tgsw->mii_read = mt753x_mii_read;\n\t\tgsw->mii_write = mt753x_mii_write;\n\t\tgsw->mmd_read = mt753x_mmd_ind_read;\n\t\tgsw->mmd_write = mt753x_mmd_ind_write;\n\t}\n\n\tfor (i = 0; i < MT753X_NUM_PHYS; i++) {\n\t\tval = gsw->mii_read(gsw, i, MII_BMCR);\n\t\tval |= BMCR_PDOWN;\n\t\tgsw->mii_write(gsw, i, MII_BMCR, val);\n\t}\n\n\t/* Force MAC link down before reset */\n\tmt753x_reg_write(gsw, PMCR(5), FORCE_MODE);\n\tmt753x_reg_write(gsw, PMCR(6), FORCE_MODE);\n\n\t/* Switch soft reset */\n\t/* BUG: sw reset causes gsw int flooding */\n\tmt753x_reg_write(gsw, SYS_CTRL, SW_PHY_RST | SW_SYS_RST | SW_REG_RST);\n\tusleep_range(10, 20);\n\n\t/* global mac control settings configuration */\n\tmt753x_reg_write(gsw, GMACCR,\n\t\t\t LATE_COL_DROP | (15 << MTCC_LMT_S) |\n\t\t\t (2 << MAX_RX_JUMBO_S) | RX_PKT_LEN_MAX_JUMBO);\n\n\tmt7530_core_pll_setup(gsw);\n\tmt7530_mac_port_setup(gsw);\n\n\treturn 0;\n}\n\nstatic int mt7530_sw_post_init(struct gsw_mt753x *gsw)\n{\n\tint i;\n\tu32 val;\n\n\tmt7530_phy_setting(gsw);\n\n\tfor (i = 0; i < MT753X_NUM_PHYS; i++) {\n\t\tval = gsw->mii_read(gsw, i, MII_BMCR);\n\t\tval &= ~BMCR_PDOWN;\n\t\tgsw->mii_write(gsw, i, MII_BMCR, val);\n\t}\n\n\treturn 0;\n}\n\nstruct mt753x_sw_id mt7530_id = {\n\t.model = MT7530,\n\t.detect = mt7530_sw_detect,\n\t.init = mt7530_sw_init,\n\t.post_init = mt7530_sw_post_init\n};\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/mtk/mt753x/mt7530.h",
    "content": "/* SPDX-License-Identifier: GPL-2.0-only */\n/*\n * Copyright (c) 2018 MediaTek Inc.\n */\n\n#ifndef _MT7530_H_\n#define _MT7530_H_\n\n#include \"mt753x.h\"\n\nextern struct mt753x_sw_id mt7530_id;\n\n#endif /* _MT7530_H_ */\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/mtk/mt753x/mt7531.c",
    "content": "// SPDX-License-Identifier: GPL-2.0-only\n/*\n * Copyright (c) 2018 MediaTek Inc.\n * Author: Zhanguo Ju <zhanguo.ju@mediatek.com>\n */\n\n#include <linux/kernel.h>\n#include <linux/delay.h>\n#include <linux/hrtimer.h>\n\n#include \"mt753x.h\"\n#include \"mt753x_regs.h\"\n\n/* MT7531 registers */\n#define SGMII_REG_BASE\t\t\t0x5000\n#define SGMII_REG_PORT_BASE\t\t0x1000\n#define SGMII_REG(p, r)\t\t\t(SGMII_REG_BASE + \\\n\t\t\t\t\t(p) * SGMII_REG_PORT_BASE + (r))\n#define PCS_CONTROL_1(p)\t\tSGMII_REG(p, 0x00)\n#define SGMII_MODE(p)\t\t\tSGMII_REG(p, 0x20)\n#define QPHY_PWR_STATE_CTRL(p)\t\tSGMII_REG(p, 0xe8)\n#define PHYA_CTRL_SIGNAL3(p)\t\tSGMII_REG(p, 0x128)\n\n/* Fields of PCS_CONTROL_1 */\n#define SGMII_LINK_STATUS\t\tBIT(18)\n#define SGMII_AN_ENABLE\t\t\tBIT(12)\n#define SGMII_AN_RESTART\t\tBIT(9)\n\n/* Fields of SGMII_MODE */\n#define SGMII_REMOTE_FAULT_DIS\t\tBIT(8)\n#define SGMII_IF_MODE_FORCE_DUPLEX\tBIT(4)\n#define SGMII_IF_MODE_FORCE_SPEED_S\t0x2\n#define SGMII_IF_MODE_FORCE_SPEED_M\t0x0c\n#define SGMII_IF_MODE_ADVERT_AN\t\tBIT(1)\n\n/* Values of SGMII_IF_MODE_FORCE_SPEED */\n#define SGMII_IF_MODE_FORCE_SPEED_10\t0\n#define SGMII_IF_MODE_FORCE_SPEED_100\t1\n#define SGMII_IF_MODE_FORCE_SPEED_1000\t2\n\n/* Fields of QPHY_PWR_STATE_CTRL */\n#define PHYA_PWD\t\t\tBIT(4)\n\n/* Fields of PHYA_CTRL_SIGNAL3 */\n#define RG_TPHY_SPEED_S\t\t\t2\n#define RG_TPHY_SPEED_M\t\t\t0x0c\n\n/* Values of RG_TPHY_SPEED */\n#define RG_TPHY_SPEED_1000\t\t0\n#define RG_TPHY_SPEED_2500\t\t1\n\n/* Unique fields of (M)HWSTRAP for MT7531 */\n#define XTAL_FSEL_S\t\t\t7\n#define XTAL_FSEL_M\t\t\tBIT(7)\n#define PHY_EN\t\t\t\tBIT(6)\n#define CHG_STRAP\t\t\tBIT(8)\n\n/* Efuse Register Define */\n#define GBE_EFUSE\t\t\t0x7bc8\n#define GBE_SEL_EFUSE_EN\t\tBIT(0)\n\n/* PHY ENABLE Register bitmap define */\n#define PHY_DEV1F\t\t\t0x1f\n#define PHY_DEV1F_REG_44\t\t0x44\n#define PHY_DEV1F_REG_104\t\t0x104\n#define PHY_DEV1F_REG_10A\t\t0x10a\n#define PHY_DEV1F_REG_10B\t\t0x10b\n#define PHY_DEV1F_REG_10C\t\t0x10c\n#define PHY_DEV1F_REG_10D\t\t0x10d\n#define PHY_DEV1F_REG_268\t\t0x268\n#define PHY_DEV1F_REG_269\t\t0x269\n#define PHY_DEV1F_REG_403\t\t0x403\n\n/* Fields of PHY_DEV1F_REG_403 */\n#define GBE_EFUSE_SETTING\t\tBIT(3)\n#define PHY_EN_BYPASS_MODE\t\tBIT(4)\n#define POWER_ON_OFF\t\t\tBIT(5)\n#define PHY_PLL_M\t\t\tGENMASK(9, 8)\n#define PHY_PLL_SEL(x)\t\t\t(((x) << 8) & GENMASK(9, 8))\n\n/* PHY EEE Register bitmap of define */\n#define PHY_DEV07\t\t\t0x07\n#define PHY_DEV07_REG_03C\t\t0x3c\n\n/* PHY Extend Register 0x14 bitmap of define */\n#define PHY_EXT_REG_14\t\t\t0x14\n\n/* Fields of PHY_EXT_REG_14 */\n#define PHY_EN_DOWN_SHFIT\t\tBIT(4)\n\n/* PHY Extend Register 0x17 bitmap of define */\n#define PHY_EXT_REG_17\t\t\t0x17\n\n/* Fields of PHY_EXT_REG_17 */\n#define PHY_LINKDOWN_POWER_SAVING_EN\tBIT(4)\n\n/* PHY Token Ring Register 0x10 bitmap of define */\n#define PHY_TR_REG_10\t\t\t0x10\n\n/* PHY Token Ring Register 0x12 bitmap of define */\n#define PHY_TR_REG_12\t\t\t0x12\n\n/* PHY DEV 0x1e Register bitmap of define */\n#define PHY_DEV1E\t\t\t0x1e\n#define PHY_DEV1E_REG_13\t\t0x13\n#define PHY_DEV1E_REG_14\t\t0x14\n#define PHY_DEV1E_REG_41\t\t0x41\n#define PHY_DEV1E_REG_A6\t\t0xa6\n#define PHY_DEV1E_REG_0C6\t\t0x0c6\n#define PHY_DEV1E_REG_0FE\t\t0x0fe\n#define PHY_DEV1E_REG_123\t\t0x123\n#define PHY_DEV1E_REG_189\t\t0x189\n\n/* Fields of PHY_DEV1E_REG_0C6 */\n#define PHY_POWER_SAVING_S\t\t8\n#define PHY_POWER_SAVING_M\t\t0x300\n#define PHY_POWER_SAVING_TX\t\t0x0\n\n/* Fields of PHY_DEV1E_REG_189 */\n#define DESCRAMBLER_CLEAR_EN\t\t0x1\n\n/* Values of XTAL_FSEL_S */\n#define XTAL_40MHZ\t\t\t0\n#define XTAL_25MHZ\t\t\t1\n\n#define PLLGP_EN\t\t\t0x7820\n#define EN_COREPLL\t\t\tBIT(2)\n#define SW_CLKSW\t\t\tBIT(1)\n#define SW_PLLGP\t\t\tBIT(0)\n\n#define PLLGP_CR0\t\t\t0x78a8\n#define RG_COREPLL_EN\t\t\tBIT(22)\n#define RG_COREPLL_POSDIV_S\t\t23\n#define RG_COREPLL_POSDIV_M\t\t0x3800000\n#define RG_COREPLL_SDM_PCW_S\t\t1\n#define RG_COREPLL_SDM_PCW_M\t\t0x3ffffe\n#define RG_COREPLL_SDM_PCW_CHG\t\tBIT(0)\n\n/* TOP Signals Status Register */\n#define TOP_SIG_SR\t\t\t0x780c\n#define PAD_DUAL_SGMII_EN\t\tBIT(1)\n\n/* RGMII and SGMII PLL clock */\n#define ANA_PLLGP_CR2\t\t\t0x78b0\n#define ANA_PLLGP_CR5\t\t\t0x78bc\n\n/* GPIO mode define */\n#define GPIO_MODE_REGS(x)\t\t(0x7c0c + (((x) / 8) * 4))\n#define GPIO_MODE_S\t\t\t4\n\n/* GPIO GROUP IOLB SMT0 Control */\n#define SMT0_IOLB\t\t\t0x7f04\n#define SMT_IOLB_5_SMI_MDC_EN\t\tBIT(5)\n\n/* Unique fields of PMCR for MT7531 */\n#define FORCE_MODE_EEE1G\t\tBIT(25)\n#define FORCE_MODE_EEE100\t\tBIT(26)\n#define FORCE_MODE_TX_FC\t\tBIT(27)\n#define FORCE_MODE_RX_FC\t\tBIT(28)\n#define FORCE_MODE_DPX\t\t\tBIT(29)\n#define FORCE_MODE_SPD\t\t\tBIT(30)\n#define FORCE_MODE_LNK\t\t\tBIT(31)\n#define FORCE_MODE\t\t\tBIT(15)\n\n#define CHIP_REV\t\t\t0x781C\n#define CHIP_NAME_S\t\t\t16\n#define CHIP_NAME_M\t\t\t0xffff0000\n#define CHIP_REV_S\t\t\t0\n#define CHIP_REV_M\t\t\t0x0f\n#define CHIP_REV_E1\t\t\t0x0\n\n#define CLKGEN_CTRL\t\t\t0x7500\n#define CLK_SKEW_OUT_S\t\t\t8\n#define CLK_SKEW_OUT_M\t\t\t0x300\n#define CLK_SKEW_IN_S\t\t\t6\n#define CLK_SKEW_IN_M\t\t\t0xc0\n#define RXCLK_NO_DELAY\t\t\tBIT(5)\n#define TXCLK_NO_REVERSE\t\tBIT(4)\n#define GP_MODE_S\t\t\t1\n#define GP_MODE_M\t\t\t0x06\n#define GP_CLK_EN\t\t\tBIT(0)\n\n/* Values of GP_MODE */\n#define GP_MODE_RGMII\t\t\t0\n#define GP_MODE_MII\t\t\t1\n#define GP_MODE_REV_MII\t\t\t2\n\n/* Values of CLK_SKEW_IN */\n#define CLK_SKEW_IN_NO_CHANGE\t\t0\n#define CLK_SKEW_IN_DELAY_100PPS\t1\n#define CLK_SKEW_IN_DELAY_200PPS\t2\n#define CLK_SKEW_IN_REVERSE\t\t3\n\n/* Values of CLK_SKEW_OUT */\n#define CLK_SKEW_OUT_NO_CHANGE\t\t0\n#define CLK_SKEW_OUT_DELAY_100PPS\t1\n#define CLK_SKEW_OUT_DELAY_200PPS\t2\n#define CLK_SKEW_OUT_REVERSE\t\t3\n\n/* Proprietory Control Register of Internal Phy device 0x1e */\n#define RXADC_CONTROL_3\t\t\t0xc2\n#define RXADC_LDO_CONTROL_2\t\t0xd3\n\n/* Proprietory Control Register of Internal Phy device 0x1f */\n#define TXVLD_DA_271\t\t\t0x271\n#define TXVLD_DA_272\t\t\t0x272\n#define TXVLD_DA_273\t\t\t0x273\n\n/* DSP Channel and NOD_ADDR*/\n#define DSP_CH\t\t\t\t0x2\n#define DSP_NOD_ADDR\t\t\t0xD\n\n/* gpio pinmux pins and functions define */\nstatic int gpio_int_pins[] = {0};\nstatic int gpio_int_funcs[] = {1};\nstatic int gpio_mdc_pins[] = {11, 20};\nstatic int gpio_mdc_funcs[] = {2, 2};\nstatic int gpio_mdio_pins[] = {12, 21};\nstatic int gpio_mdio_funcs[] = {2, 2};\n\nstatic int mt7531_set_port_sgmii_force_mode(struct gsw_mt753x *gsw, u32 port,\n\t\t\t\t\t    struct mt753x_port_cfg *port_cfg)\n{\n\tu32 speed, port_base, val;\n\tktime_t timeout;\n\tu32 timeout_us;\n\n\tif (port < 5 || port >= MT753X_NUM_PORTS) {\n\t\tdev_info(gsw->dev, \"port %d is not a SGMII port\\n\", port);\n\t\treturn -EINVAL;\n\t}\n\n\tport_base = port - 5;\n\n\tswitch (port_cfg->speed) {\n\tcase MAC_SPD_1000:\n\t\tspeed = RG_TPHY_SPEED_1000;\n\t\tbreak;\n\tcase MAC_SPD_2500:\n\t\tspeed = RG_TPHY_SPEED_2500;\n\t\tbreak;\n\tdefault:\n\t\tdev_info(gsw->dev, \"invalid SGMII speed idx %d for port %d\\n\",\n\t\t\t port_cfg->speed, port);\n\n\t\tspeed = RG_TPHY_SPEED_1000;\n\t}\n\n\t/* Step 1: Speed select register setting */\n\tval = mt753x_reg_read(gsw, PHYA_CTRL_SIGNAL3(port_base));\n\tval &= ~RG_TPHY_SPEED_M;\n\tval |= speed << RG_TPHY_SPEED_S;\n\tmt753x_reg_write(gsw, PHYA_CTRL_SIGNAL3(port_base), val);\n\n\t/* Step 2 : Disable AN */\n\tval = mt753x_reg_read(gsw, PCS_CONTROL_1(port_base));\n\tval &= ~SGMII_AN_ENABLE;\n\tmt753x_reg_write(gsw, PCS_CONTROL_1(port_base), val);\n\n\t/* Step 3: SGMII force mode setting */\n\tval = mt753x_reg_read(gsw, SGMII_MODE(port_base));\n\tval &= ~SGMII_IF_MODE_ADVERT_AN;\n\tval &= ~SGMII_IF_MODE_FORCE_SPEED_M;\n\tval |= SGMII_IF_MODE_FORCE_SPEED_1000 << SGMII_IF_MODE_FORCE_SPEED_S;\n\tval |= SGMII_IF_MODE_FORCE_DUPLEX;\n\t/* For sgmii force mode, 0 is full duplex and 1 is half duplex */\n\tif (port_cfg->duplex)\n\t\tval &= ~SGMII_IF_MODE_FORCE_DUPLEX;\n\n\tmt753x_reg_write(gsw, SGMII_MODE(port_base), val);\n\n\t/* Step 4: XXX: Disable Link partner's AN and set force mode */\n\n\t/* Step 5: XXX: Special setting for PHYA ==> reserved for flexible */\n\n\t/* Step 6 : Release PHYA power down state */\n\tval = mt753x_reg_read(gsw, QPHY_PWR_STATE_CTRL(port_base));\n\tval &= ~PHYA_PWD;\n\tmt753x_reg_write(gsw, QPHY_PWR_STATE_CTRL(port_base), val);\n\n\t/* Step 7 : Polling SGMII_LINK_STATUS */\n\ttimeout_us = 2000000;\n\ttimeout = ktime_add_us(ktime_get(), timeout_us);\n\twhile (1) {\n\t\tval = mt753x_reg_read(gsw, PCS_CONTROL_1(port_base));\n\t\tval &= SGMII_LINK_STATUS;\n\n\t\tif (val)\n\t\t\tbreak;\n\n\t\tif (ktime_compare(ktime_get(), timeout) > 0)\n\t\t\treturn -ETIMEDOUT;\n\t}\n\n\treturn 0;\n}\n\nstatic int mt7531_set_port_sgmii_an_mode(struct gsw_mt753x *gsw, u32 port,\n\t\t\t\t\t struct mt753x_port_cfg *port_cfg)\n{\n\tu32 speed, port_base, val;\n\tktime_t timeout;\n\tu32 timeout_us;\n\n\tif (port < 5 || port >= MT753X_NUM_PORTS) {\n\t\tdev_info(gsw->dev, \"port %d is not a SGMII port\\n\", port);\n\t\treturn -EINVAL;\n\t}\n\n\tport_base = port - 5;\n\n\tswitch (port_cfg->speed) {\n\tcase MAC_SPD_1000:\n\t\tspeed = RG_TPHY_SPEED_1000;\n\t\tbreak;\n\tcase MAC_SPD_2500:\n\t\tspeed = RG_TPHY_SPEED_2500;\n\t\tbreak;\n\tdefault:\n\t\tdev_info(gsw->dev, \"invalid SGMII speed idx %d for port %d\\n\",\n\t\t\t port_cfg->speed, port);\n\n\t\tspeed = RG_TPHY_SPEED_1000;\n\t}\n\n\t/* Step 1: Speed select register setting */\n\tval = mt753x_reg_read(gsw, PHYA_CTRL_SIGNAL3(port_base));\n\tval &= ~RG_TPHY_SPEED_M;\n\tval |= speed << RG_TPHY_SPEED_S;\n\tmt753x_reg_write(gsw, PHYA_CTRL_SIGNAL3(port_base), val);\n\n\t/* Step 2: Remote fault disable */\n\tval = mt753x_reg_read(gsw, SGMII_MODE(port));\n\tval |= SGMII_REMOTE_FAULT_DIS;\n\tmt753x_reg_write(gsw, SGMII_MODE(port), val);\n\n\t/* Step 3: Setting Link partner's AN enable = 1 */\n\n\t/* Step 4: Setting Link partner's device ability for speed/duplex */\n\n\t/* Step 5: AN re-start */\n\tval = mt753x_reg_read(gsw, PCS_CONTROL_1(port));\n\tval |= SGMII_AN_RESTART;\n\tmt753x_reg_write(gsw, PCS_CONTROL_1(port), val);\n\n\t/* Step 6: Special setting for PHYA ==> reserved for flexible */\n\n\t/* Step 7 : Polling SGMII_LINK_STATUS */\n\ttimeout_us = 2000000;\n\ttimeout = ktime_add_us(ktime_get(), timeout_us);\n\twhile (1) {\n\t\tval = mt753x_reg_read(gsw, PCS_CONTROL_1(port_base));\n\t\tval &= SGMII_LINK_STATUS;\n\n\t\tif (val)\n\t\t\tbreak;\n\n\t\tif (ktime_compare(ktime_get(), timeout) > 0)\n\t\t\treturn -ETIMEDOUT;\n\t}\n\n\treturn 0;\n}\n\nstatic int mt7531_set_port_rgmii(struct gsw_mt753x *gsw, u32 port)\n{\n\tu32 val;\n\n\tif (port != 5) {\n\t\tdev_info(gsw->dev, \"RGMII mode is not available for port %d\\n\",\n\t\t\t port);\n\t\treturn -EINVAL;\n\t}\n\n\tval = mt753x_reg_read(gsw, CLKGEN_CTRL);\n\tval |= GP_CLK_EN;\n\tval &= ~GP_MODE_M;\n\tval |= GP_MODE_RGMII << GP_MODE_S;\n\tval |= TXCLK_NO_REVERSE;\n\tval |= RXCLK_NO_DELAY;\n\tval &= ~CLK_SKEW_IN_M;\n\tval |= CLK_SKEW_IN_NO_CHANGE << CLK_SKEW_IN_S;\n\tval &= ~CLK_SKEW_OUT_M;\n\tval |= CLK_SKEW_OUT_NO_CHANGE << CLK_SKEW_OUT_S;\n\tmt753x_reg_write(gsw, CLKGEN_CTRL, val);\n\n\treturn 0;\n}\n\nstatic int mt7531_mac_port_setup(struct gsw_mt753x *gsw, u32 port,\n\t\t\t\t struct mt753x_port_cfg *port_cfg)\n{\n\tu32 pmcr;\n\tu32 speed;\n\n\tif (port < 5 || port >= MT753X_NUM_PORTS) {\n\t\tdev_info(gsw->dev, \"port %d is not a MAC port\\n\", port);\n\t\treturn -EINVAL;\n\t}\n\n\tif (port_cfg->enabled) {\n\t\tpmcr = (IPG_96BIT_WITH_SHORT_IPG << IPG_CFG_S) |\n\t\t       MAC_MODE | MAC_TX_EN | MAC_RX_EN |\n\t\t       BKOFF_EN | BACKPR_EN;\n\n\t\tif (port_cfg->force_link) {\n\t\t\t/* PMCR's speed field 0x11 is reserved,\n\t\t\t * sw should set 0x10\n\t\t\t */\n\t\t\tspeed = port_cfg->speed;\n\t\t\tif (port_cfg->speed == MAC_SPD_2500)\n\t\t\t\tspeed = MAC_SPD_1000;\n\n\t\t\tpmcr |= FORCE_MODE_LNK | FORCE_LINK |\n\t\t\t\tFORCE_MODE_SPD | FORCE_MODE_DPX |\n\t\t\t\tFORCE_MODE_RX_FC | FORCE_MODE_TX_FC |\n\t\t\t\tFORCE_RX_FC | FORCE_TX_FC |\n\t\t\t\t(speed << FORCE_SPD_S);\n\n\t\t\tif (port_cfg->duplex)\n\t\t\t\tpmcr |= FORCE_DPX;\n\t\t}\n\t} else {\n\t\tpmcr = FORCE_MODE_LNK;\n\t}\n\n\tswitch (port_cfg->phy_mode) {\n\tcase PHY_INTERFACE_MODE_RGMII:\n\t\tmt7531_set_port_rgmii(gsw, port);\n\t\tbreak;\n\tcase PHY_INTERFACE_MODE_SGMII:\n\t\tif (port_cfg->force_link)\n\t\t\tmt7531_set_port_sgmii_force_mode(gsw, port, port_cfg);\n\t\telse\n\t\t\tmt7531_set_port_sgmii_an_mode(gsw, port, port_cfg);\n\t\tbreak;\n\tdefault:\n\t\tif (port_cfg->enabled)\n\t\t\tdev_info(gsw->dev, \"%s is not supported by port %d\\n\",\n\t\t\t\t phy_modes(port_cfg->phy_mode), port);\n\n\t\tpmcr = FORCE_MODE_LNK;\n\t}\n\n\tmt753x_reg_write(gsw, PMCR(port), pmcr);\n\n\treturn 0;\n}\n\nstatic void mt7531_core_pll_setup(struct gsw_mt753x *gsw)\n{\n\tu32 hwstrap;\n\tu32 val;\n\n\tval = mt753x_reg_read(gsw, TOP_SIG_SR);\n\tif (val & PAD_DUAL_SGMII_EN)\n\t\treturn;\n\n\thwstrap = mt753x_reg_read(gsw, HWSTRAP);\n\n\tswitch ((hwstrap & XTAL_FSEL_M) >> XTAL_FSEL_S) {\n\tcase XTAL_25MHZ:\n\t\t/* Step 1 : Disable MT7531 COREPLL */\n\t\tval = mt753x_reg_read(gsw, PLLGP_EN);\n\t\tval &= ~EN_COREPLL;\n\t\tmt753x_reg_write(gsw, PLLGP_EN, val);\n\n\t\t/* Step 2: switch to XTAL output */\n\t\tval = mt753x_reg_read(gsw, PLLGP_EN);\n\t\tval |= SW_CLKSW;\n\t\tmt753x_reg_write(gsw, PLLGP_EN, val);\n\n\t\tval = mt753x_reg_read(gsw, PLLGP_CR0);\n\t\tval &= ~RG_COREPLL_EN;\n\t\tmt753x_reg_write(gsw, PLLGP_CR0, val);\n\n\t\t/* Step 3: disable PLLGP and enable program PLLGP */\n\t\tval = mt753x_reg_read(gsw, PLLGP_EN);\n\t\tval |= SW_PLLGP;\n\t\tmt753x_reg_write(gsw, PLLGP_EN, val);\n\n\t\t/* Step 4: program COREPLL output frequency to 500MHz */\n\t\tval = mt753x_reg_read(gsw, PLLGP_CR0);\n\t\tval &= ~RG_COREPLL_POSDIV_M;\n\t\tval |= 2 << RG_COREPLL_POSDIV_S;\n\t\tmt753x_reg_write(gsw, PLLGP_CR0, val);\n\t\tusleep_range(25, 35);\n\n\t\tval = mt753x_reg_read(gsw, PLLGP_CR0);\n\t\tval &= ~RG_COREPLL_SDM_PCW_M;\n\t\tval |= 0x140000 << RG_COREPLL_SDM_PCW_S;\n\t\tmt753x_reg_write(gsw, PLLGP_CR0, val);\n\n\t\t/* Set feedback divide ratio update signal to high */\n\t\tval = mt753x_reg_read(gsw, PLLGP_CR0);\n\t\tval |= RG_COREPLL_SDM_PCW_CHG;\n\t\tmt753x_reg_write(gsw, PLLGP_CR0, val);\n\t\t/* Wait for at least 16 XTAL clocks */\n\t\tusleep_range(10, 20);\n\n\t\t/* Step 5: set feedback divide ratio update signal to low */\n\t\tval = mt753x_reg_read(gsw, PLLGP_CR0);\n\t\tval &= ~RG_COREPLL_SDM_PCW_CHG;\n\t\tmt753x_reg_write(gsw, PLLGP_CR0, val);\n\n\t\t/* Enable 325M clock for SGMII */\n\t\tmt753x_reg_write(gsw, ANA_PLLGP_CR5, 0xad0000);\n\n\t\t/* Enable 250SSC clock for RGMII */\n\t\tmt753x_reg_write(gsw, ANA_PLLGP_CR2, 0x4f40000);\n\n\t\t/* Step 6: Enable MT7531 PLL */\n\t\tval = mt753x_reg_read(gsw, PLLGP_CR0);\n\t\tval |= RG_COREPLL_EN;\n\t\tmt753x_reg_write(gsw, PLLGP_CR0, val);\n\n\t\tval = mt753x_reg_read(gsw, PLLGP_EN);\n\t\tval |= EN_COREPLL;\n\t\tmt753x_reg_write(gsw, PLLGP_EN, val);\n\t\tusleep_range(25, 35);\n\n\t\tbreak;\n\tcase XTAL_40MHZ:\n\t\t/* Step 1 : Disable MT7531 COREPLL */\n\t\tval = mt753x_reg_read(gsw, PLLGP_EN);\n\t\tval &= ~EN_COREPLL;\n\t\tmt753x_reg_write(gsw, PLLGP_EN, val);\n\n\t\t/* Step 2: switch to XTAL output */\n\t\tval = mt753x_reg_read(gsw, PLLGP_EN);\n\t\tval |= SW_CLKSW;\n\t\tmt753x_reg_write(gsw, PLLGP_EN, val);\n\n\t\tval = mt753x_reg_read(gsw, PLLGP_CR0);\n\t\tval &= ~RG_COREPLL_EN;\n\t\tmt753x_reg_write(gsw, PLLGP_CR0, val);\n\n\t\t/* Step 3: disable PLLGP and enable program PLLGP */\n\t\tval = mt753x_reg_read(gsw, PLLGP_EN);\n\t\tval |= SW_PLLGP;\n\t\tmt753x_reg_write(gsw, PLLGP_EN, val);\n\n\t\t/* Step 4: program COREPLL output frequency to 500MHz */\n\t\tval = mt753x_reg_read(gsw, PLLGP_CR0);\n\t\tval &= ~RG_COREPLL_POSDIV_M;\n\t\tval |= 2 << RG_COREPLL_POSDIV_S;\n\t\tmt753x_reg_write(gsw, PLLGP_CR0, val);\n\t\tusleep_range(25, 35);\n\n\t\tval = mt753x_reg_read(gsw, PLLGP_CR0);\n\t\tval &= ~RG_COREPLL_SDM_PCW_M;\n\t\tval |= 0x190000 << RG_COREPLL_SDM_PCW_S;\n\t\tmt753x_reg_write(gsw, PLLGP_CR0, val);\n\n\t\t/* Set feedback divide ratio update signal to high */\n\t\tval = mt753x_reg_read(gsw, PLLGP_CR0);\n\t\tval |= RG_COREPLL_SDM_PCW_CHG;\n\t\tmt753x_reg_write(gsw, PLLGP_CR0, val);\n\t\t/* Wait for at least 16 XTAL clocks */\n\t\tusleep_range(10, 20);\n\n\t\t/* Step 5: set feedback divide ratio update signal to low */\n\t\tval = mt753x_reg_read(gsw, PLLGP_CR0);\n\t\tval &= ~RG_COREPLL_SDM_PCW_CHG;\n\t\tmt753x_reg_write(gsw, PLLGP_CR0, val);\n\n\t\t/* Enable 325M clock for SGMII */\n\t\tmt753x_reg_write(gsw, ANA_PLLGP_CR5, 0xad0000);\n\n\t\t/* Enable 250SSC clock for RGMII */\n\t\tmt753x_reg_write(gsw, ANA_PLLGP_CR2, 0x4f40000);\n\n\t\t/* Step 6: Enable MT7531 PLL */\n\t\tval = mt753x_reg_read(gsw, PLLGP_CR0);\n\t\tval |= RG_COREPLL_EN;\n\t\tmt753x_reg_write(gsw, PLLGP_CR0, val);\n\n\t\tval = mt753x_reg_read(gsw, PLLGP_EN);\n\t\tval |= EN_COREPLL;\n\t\tmt753x_reg_write(gsw, PLLGP_EN, val);\n\t\tusleep_range(25, 35);\n\t\tbreak;\n\t}\n}\n\nstatic int mt7531_internal_phy_calibration(struct gsw_mt753x *gsw)\n{\n\treturn 0;\n}\n\nstatic int mt7531_sw_detect(struct gsw_mt753x *gsw, struct chip_rev *crev)\n{\n\tu32 rev, topsig;\n\n\trev = mt753x_reg_read(gsw, CHIP_REV);\n\n\tif (((rev & CHIP_NAME_M) >> CHIP_NAME_S) == MT7531) {\n\t\tif (crev) {\n\t\t\ttopsig = mt753x_reg_read(gsw, TOP_SIG_SR);\n\n\t\t\tcrev->rev = rev & CHIP_REV_M;\n\t\t\tcrev->name = topsig & PAD_DUAL_SGMII_EN ?\n\t\t\t\t     \"MT7531AE\" : \"MT7531BE\";\n\t\t}\n\n\t\treturn 0;\n\t}\n\n\treturn -ENODEV;\n}\n\nstatic void pinmux_set_mux_7531(struct gsw_mt753x *gsw, u32 pin, u32 mode)\n{\n\tu32 val;\n\n\tval = mt753x_reg_read(gsw, GPIO_MODE_REGS(pin));\n\tval &= ~(0xf << (pin & 7) * GPIO_MODE_S);\n\tval |= mode << (pin & 7) * GPIO_MODE_S;\n\tmt753x_reg_write(gsw, GPIO_MODE_REGS(pin), val);\n}\n\nstatic int mt7531_set_gpio_pinmux(struct gsw_mt753x *gsw)\n{\n\tu32 group = 0;\n\tstruct device_node *np = gsw->dev->of_node;\n\n\t/* Set GPIO 0 interrupt mode */\n\tpinmux_set_mux_7531(gsw, gpio_int_pins[0], gpio_int_funcs[0]);\n\n\tof_property_read_u32(np, \"mediatek,mdio_master_pinmux\", &group);\n\n\t/* group = 0: do nothing, 1: 1st group (AE), 2: 2nd group (BE) */\n\tif (group > 0 && group <= 2) {\n\t\tgroup--;\n\t\tpinmux_set_mux_7531(gsw, gpio_mdc_pins[group],\n\t\t\t\t    gpio_mdc_funcs[group]);\n\t\tpinmux_set_mux_7531(gsw, gpio_mdio_pins[group],\n\t\t\t\t    gpio_mdio_funcs[group]);\n\t}\n\n\treturn 0;\n}\n\nstatic void mt7531_phy_pll_setup(struct gsw_mt753x *gsw)\n{\n\tu32 hwstrap;\n\tu32 val;\n\n\thwstrap = mt753x_reg_read(gsw, HWSTRAP);\n\n\tswitch ((hwstrap & XTAL_FSEL_M) >> XTAL_FSEL_S) {\n\tcase XTAL_25MHZ:\n\t\t/* disable pll auto calibration */\n\t\tgsw->mmd_write(gsw, 0, PHY_DEV1F, PHY_DEV1F_REG_104, 0x608);\n\n\t\t/* change pll sel */\n\t\tval = gsw->mmd_read(gsw, 0, PHY_DEV1F,\n\t\t\t\t     PHY_DEV1F_REG_403);\n\t\tval &= ~(PHY_PLL_M);\n\t\tval |= PHY_PLL_SEL(3);\n\t\tgsw->mmd_write(gsw, 0, PHY_DEV1F, PHY_DEV1F_REG_403, val);\n\n\t\t/* set divider ratio */\n\t\tgsw->mmd_write(gsw, 0, PHY_DEV1F,\n\t\t\t       PHY_DEV1F_REG_10A, 0x1009);\n\n\t\t/* set divider ratio */\n\t\tgsw->mmd_write(gsw, 0, PHY_DEV1F, PHY_DEV1F_REG_10B, 0x7c6);\n\n\t\t/* capacitance and resistance adjustment */\n\t\tgsw->mmd_write(gsw, 0, PHY_DEV1F,\n\t\t\t       PHY_DEV1F_REG_10C, 0xa8be);\n\n\t\tbreak;\n\tcase XTAL_40MHZ:\n\t\t/* disable pll auto calibration */\n\t\tgsw->mmd_write(gsw, 0, PHY_DEV1F, PHY_DEV1F_REG_104, 0x608);\n\n\t\t/* change pll sel */\n\t\tval = gsw->mmd_read(gsw, 0, PHY_DEV1F,\n\t\t\t\t     PHY_DEV1F_REG_403);\n\t\tval &= ~(PHY_PLL_M);\n\t\tval |= PHY_PLL_SEL(3);\n\t\tgsw->mmd_write(gsw, 0, PHY_DEV1F, PHY_DEV1F_REG_403, val);\n\n\t\t/* set divider ratio */\n\t\tgsw->mmd_write(gsw, 0, PHY_DEV1F,\n\t\t\t       PHY_DEV1F_REG_10A, 0x1018);\n\n\t\t/* set divider ratio */\n\t\tgsw->mmd_write(gsw, 0, PHY_DEV1F, PHY_DEV1F_REG_10B, 0xc676);\n\n\t\t/* capacitance and resistance adjustment */\n\t\tgsw->mmd_write(gsw, 0, PHY_DEV1F,\n\t\t\t       PHY_DEV1F_REG_10C, 0xd8be);\n\t\tbreak;\n\t}\n\n\t/* power down pll. additional delay is not required via mdio access */\n\tgsw->mmd_write(gsw, 0, PHY_DEV1F, PHY_DEV1F_REG_10D, 0x10);\n\n\t/* power up pll */\n\tgsw->mmd_write(gsw, 0, PHY_DEV1F, PHY_DEV1F_REG_10D, 0x14);\n}\n\nstatic void mt7531_phy_setting(struct gsw_mt753x *gsw)\n{\n\tint i;\n\tu32 val;\n\n\t/* Adjust DAC TX Delay */\n\tgsw->mmd_write(gsw, 0, PHY_DEV1F, PHY_DEV1F_REG_44, 0xc0);\n\n\tfor (i = 0; i < MT753X_NUM_PHYS; i++) {\n\t\t/* Disable EEE */\n\t\tgsw->mmd_write(gsw, i, PHY_DEV07, PHY_DEV07_REG_03C, 0);\n\n\t\t/* Enable HW auto downshift */\n\t\tgsw->mii_write(gsw, i, 0x1f, 0x1);\n\t\tval = gsw->mii_read(gsw, i, PHY_EXT_REG_14);\n\t\tval |= PHY_EN_DOWN_SHFIT;\n\t\tgsw->mii_write(gsw, i, PHY_EXT_REG_14, val);\n\n\t\t/* Increase SlvDPSready time */\n\t\tgsw->mii_write(gsw, i, 0x1f, 0x52b5);\n\t\tgsw->mii_write(gsw, i, PHY_TR_REG_10, 0xafae);\n\t\tgsw->mii_write(gsw, i, PHY_TR_REG_12, 0x2f);\n\t\tgsw->mii_write(gsw, i, PHY_TR_REG_10, 0x8fae);\n\t\tgsw->mii_write(gsw, i, 0x1f, 0);\n\n\t\t/* Adjust 100_mse_threshold */\n\t\tgsw->mmd_write(gsw, i, PHY_DEV1E, PHY_DEV1E_REG_123, 0xffff);\n\n\t\t/* Disable mcc */\n\t\tgsw->mmd_write(gsw, i, PHY_DEV1E, PHY_DEV1E_REG_A6, 0x300);\n\n\t\t/* PHY link down power saving enable */\n\t\tval = gsw->mii_read(gsw, i, PHY_EXT_REG_17);\n\t\tval |= PHY_LINKDOWN_POWER_SAVING_EN;\n\t\tgsw->mii_write(gsw, i, PHY_EXT_REG_17, val);\n\n\t\tval = gsw->mmd_read(gsw, i, PHY_DEV1E, PHY_DEV1E_REG_0C6);\n\t\tval &= ~PHY_POWER_SAVING_M;\n\t\tval |= PHY_POWER_SAVING_TX << PHY_POWER_SAVING_S;\n\t\tgsw->mmd_write(gsw, i, PHY_DEV1E, PHY_DEV1E_REG_0C6, val);\n\n\t\t/* Set TX Pair delay selection */\n\t\tgsw->mmd_write(gsw, i, PHY_DEV1E, PHY_DEV1E_REG_13, 0x404);\n\t\tgsw->mmd_write(gsw, i, PHY_DEV1E, PHY_DEV1E_REG_14, 0x404);\n\t}\n}\n\nstatic void mt7531_adjust_line_driving(struct gsw_mt753x *gsw, u32 port)\n{\n\t/* For ADC timing margin window for LDO calibration */\n\tgsw->mmd_write(gsw, port, PHY_DEV1E, RXADC_LDO_CONTROL_2, 0x2222);\n\n\t/* Adjust AD sample timing */\n\tgsw->mmd_write(gsw, port, PHY_DEV1E, RXADC_CONTROL_3, 0x4444);\n\n\t/* Adjust Line driver current for different mode */\n\tgsw->mmd_write(gsw, port, PHY_DEV1F, TXVLD_DA_271, 0x2ca5);\n\n\t/* Adjust Line driver current for different mode */\n\tgsw->mmd_write(gsw, port, PHY_DEV1F, TXVLD_DA_272, 0xc6b);\n\n\t/* Adjust Line driver amplitude for 10BT */\n\tgsw->mmd_write(gsw, port, PHY_DEV1F, TXVLD_DA_273, 0x3000);\n\n\t/* Adjust RX Echo path filter */\n\tgsw->mmd_write(gsw, port, PHY_DEV1E, PHY_DEV1E_REG_0FE, 0x2);\n\n\t/* Adjust RX HVGA bias current */\n\tgsw->mmd_write(gsw, port, PHY_DEV1E, PHY_DEV1E_REG_41, 0x3333);\n\n\t/* Adjust TX class AB driver 1 */\n\tgsw->mmd_write(gsw, port, PHY_DEV1F, PHY_DEV1F_REG_268, 0x388);\n\n\t/* Adjust TX class AB driver 2 */\n\tgsw->mmd_write(gsw, port, PHY_DEV1F, PHY_DEV1F_REG_269, 0x4448);\n}\n\nstatic void mt7531_eee_setting(struct gsw_mt753x *gsw, u32 port)\n{\n\tu32 tr_reg_control;\n\tu32 val;\n\n\t/* Disable generate signal to clear the scramble_lock when lpi mode */\n\tval = gsw->mmd_read(gsw, port, PHY_DEV1E, PHY_DEV1E_REG_189);\n\tval &= ~DESCRAMBLER_CLEAR_EN;\n\tgsw->mmd_write(gsw, port, PHY_DEV1E, PHY_DEV1E_REG_189, val);\n\n\t/* roll back CR*/\n\tgsw->mii_write(gsw, port, 0x1f, 0x52b5);\n\tgsw->mmd_write(gsw, port, 0x1e, 0x2d1, 0);\n\ttr_reg_control = (1 << 15) | (0 << 13) | (DSP_CH << 11) |\n\t\t\t (DSP_NOD_ADDR << 7) | (0x8 << 1);\n\tgsw->mii_write(gsw, port, 17, 0x1b);\n\tgsw->mii_write(gsw, port, 18, 0);\n\tgsw->mii_write(gsw, port, 16, tr_reg_control);\n\ttr_reg_control = (1 << 15) | (0 << 13) | (DSP_CH << 11) |\n\t\t\t (DSP_NOD_ADDR << 7) | (0xf << 1);\n\tgsw->mii_write(gsw, port, 17, 0);\n\tgsw->mii_write(gsw, port, 18, 0);\n\tgsw->mii_write(gsw, port, 16, tr_reg_control);\n\n\ttr_reg_control = (1 << 15) | (0 << 13) | (DSP_CH << 11) |\n\t\t\t (DSP_NOD_ADDR << 7) | (0x10 << 1);\n\tgsw->mii_write(gsw, port, 17, 0x500);\n\tgsw->mii_write(gsw, port, 18, 0);\n\tgsw->mii_write(gsw, port, 16, tr_reg_control);\n\tgsw->mii_write(gsw, port, 0x1f, 0);\n}\n\nstatic int mt7531_sw_init(struct gsw_mt753x *gsw)\n{\n\tint i;\n\tu32 val;\n\n\tgsw->phy_base = (gsw->smi_addr + 1) & MT753X_SMI_ADDR_MASK;\n\n\tgsw->mii_read = mt753x_mii_read;\n\tgsw->mii_write = mt753x_mii_write;\n\tgsw->mmd_read = mt753x_mmd_read;\n\tgsw->mmd_write = mt753x_mmd_write;\n\n\tfor (i = 0; i < MT753X_NUM_PHYS; i++) {\n\t\tval = gsw->mii_read(gsw, i, MII_BMCR);\n\t\tval |= BMCR_ISOLATE;\n\t\tgsw->mii_write(gsw, i, MII_BMCR, val);\n\t}\n\n\t/* Force MAC link down before reset */\n\tmt753x_reg_write(gsw, PMCR(5), FORCE_MODE_LNK);\n\tmt753x_reg_write(gsw, PMCR(6), FORCE_MODE_LNK);\n\n\t/* Switch soft reset */\n\tmt753x_reg_write(gsw, SYS_CTRL, SW_SYS_RST | SW_REG_RST);\n\tusleep_range(10, 20);\n\n\t/* Enable MDC input Schmitt Trigger */\n\tval = mt753x_reg_read(gsw, SMT0_IOLB);\n\tmt753x_reg_write(gsw, SMT0_IOLB, val | SMT_IOLB_5_SMI_MDC_EN);\n\n\t/* Set 7531 gpio pinmux */\n\tmt7531_set_gpio_pinmux(gsw);\n\n\t/* Global mac control settings */\n\tmt753x_reg_write(gsw, GMACCR,\n\t\t\t (15 << MTCC_LMT_S) | (11 << MAX_RX_JUMBO_S) |\n\t\t\t RX_PKT_LEN_MAX_JUMBO);\n\n\tmt7531_core_pll_setup(gsw);\n\tmt7531_mac_port_setup(gsw, 5, &gsw->port5_cfg);\n\tmt7531_mac_port_setup(gsw, 6, &gsw->port6_cfg);\n\n\treturn 0;\n}\n\nstatic int mt7531_sw_post_init(struct gsw_mt753x *gsw)\n{\n\tint i;\n\tu32 val;\n\n\tmt7531_phy_pll_setup(gsw);\n\n\t/* Internal PHYs are disabled by default. SW should enable them.\n\t * Note that this may already be enabled in bootloader stage.\n\t */\n\tval = gsw->mmd_read(gsw, 0, PHY_DEV1F, PHY_DEV1F_REG_403);\n\tval |= PHY_EN_BYPASS_MODE;\n\tval &= ~POWER_ON_OFF;\n\tgsw->mmd_write(gsw, 0, PHY_DEV1F, PHY_DEV1F_REG_403, val);\n\n\tmt7531_phy_setting(gsw);\n\n\tfor (i = 0; i < MT753X_NUM_PHYS; i++) {\n\t\tval = gsw->mii_read(gsw, i, MII_BMCR);\n\t\tval &= ~BMCR_ISOLATE;\n\t\tgsw->mii_write(gsw, i, MII_BMCR, val);\n\t}\n\n\tfor (i = 0; i < MT753X_NUM_PHYS; i++)\n\t\tmt7531_adjust_line_driving(gsw, i);\n\n\tfor (i = 0; i < MT753X_NUM_PHYS; i++)\n\t\tmt7531_eee_setting(gsw, i);\n\n\tval = mt753x_reg_read(gsw, CHIP_REV);\n\tval &= CHIP_REV_M;\n\tif (val == CHIP_REV_E1) {\n\t\tmt7531_internal_phy_calibration(gsw);\n\t} else {\n\t\tval = mt753x_reg_read(gsw, GBE_EFUSE);\n\t\tif (val & GBE_SEL_EFUSE_EN) {\n\t\t\tval = gsw->mmd_read(gsw, 0, PHY_DEV1F,\n\t\t\t\t\t    PHY_DEV1F_REG_403);\n\t\t\tval &= ~GBE_EFUSE_SETTING;\n\t\t\tgsw->mmd_write(gsw, 0, PHY_DEV1F, PHY_DEV1F_REG_403,\n\t\t\t\t       val);\n\t\t} else {\n\t\t\tmt7531_internal_phy_calibration(gsw);\n\t\t}\n\t}\n\n\treturn 0;\n}\n\nstruct mt753x_sw_id mt7531_id = {\n\t.model = MT7531,\n\t.detect = mt7531_sw_detect,\n\t.init = mt7531_sw_init,\n\t.post_init = mt7531_sw_post_init\n};\n\nMODULE_LICENSE(\"GPL\");\nMODULE_AUTHOR(\"Zhanguo Ju <zhanguo.ju@mediatek.com>\");\nMODULE_DESCRIPTION(\"Driver for MediaTek MT753x Gigabit Switch\");\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/mtk/mt753x/mt7531.h",
    "content": "/* SPDX-License-Identifier: GPL-2.0-only */\n/*\n * Copyright (c) 2018 MediaTek Inc.\n */\n\n#ifndef _MT7531_H_\n#define _MT7531_H_\n\n#include \"mt753x.h\"\n\nextern struct mt753x_sw_id mt7531_id;\n\n#endif /* _MT7531_H_ */\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/mtk/mt753x/mt753x.h",
    "content": "/* SPDX-License-Identifier: GPL-2.0-only */\n/*\n * Copyright (c) 2018 MediaTek Inc.\n * Author: Weijie Gao <weijie.gao@mediatek.com>\n */\n\n#ifndef _MT753X_H_\n#define _MT753X_H_\n\n#include <linux/list.h>\n#include <linux/mutex.h>\n#include <linux/netdevice.h>\n#include <linux/of_mdio.h>\n#include <linux/workqueue.h>\n#include <linux/gpio/consumer.h>\n\n#ifdef CONFIG_SWCONFIG\n#include <linux/switch.h>\n#endif\n\n#include \"mt753x_vlan.h\"\n\n#define MT753X_DFL_CPU_PORT\t6\n#define MT753X_NUM_PHYS\t\t5\n\n#define MT753X_DFL_SMI_ADDR\t0x1f\n#define MT753X_SMI_ADDR_MASK\t0x1f\n\nstruct gsw_mt753x;\n\nenum mt753x_model {\n\tMT7530 = 0x7530,\n\tMT7531 = 0x7531\n};\n\nstruct mt753x_port_cfg {\n\tstruct device_node *np;\n\tphy_interface_t phy_mode;\n\tu32 enabled: 1;\n\tu32 force_link: 1;\n\tu32 speed: 2;\n\tu32 duplex: 1;\n};\n\nstruct mt753x_phy {\n\tstruct gsw_mt753x *gsw;\n\tstruct net_device netdev;\n\tstruct phy_device *phydev;\n};\n\nstruct gsw_mt753x {\n\tu32 id;\n\n\tstruct device *dev;\n\tstruct mii_bus *host_bus;\n\tstruct mii_bus *gphy_bus;\n\tstruct mutex mii_lock;\t/* MII access lock */\n\tu32 smi_addr;\n\tu32 phy_base;\n\tint direct_phy_access;\n\n\tenum mt753x_model model;\n\tconst char *name;\n\n\tstruct mt753x_port_cfg port5_cfg;\n\tstruct mt753x_port_cfg port6_cfg;\n\n\tint phy_status_poll;\n\tstruct mt753x_phy phys[MT753X_NUM_PHYS];\n\n\tint phy_link_sts;\n\n\tint irq;\n\tint reset_pin;\n\tstruct work_struct irq_worker;\n\n#ifdef CONFIG_SWCONFIG\n\tstruct switch_dev swdev;\n\tu32 cpu_port;\n#endif\n\n\tint global_vlan_enable;\n\tstruct mt753x_vlan_entry vlan_entries[MT753X_NUM_VLANS];\n\tstruct mt753x_port_entry port_entries[MT753X_NUM_PORTS];\n\n\tint (*mii_read)(struct gsw_mt753x *gsw, int phy, int reg);\n\tvoid (*mii_write)(struct gsw_mt753x *gsw, int phy, int reg, u16 val);\n\n\tint (*mmd_read)(struct gsw_mt753x *gsw, int addr, int devad, u16 reg);\n\tvoid (*mmd_write)(struct gsw_mt753x *gsw, int addr, int devad, u16 reg,\n\t\t\t  u16 val);\n\n\tstruct list_head list;\n};\n\nstruct chip_rev {\n\tconst char *name;\n\tu32 rev;\n};\n\nstruct mt753x_sw_id {\n\tenum mt753x_model model;\n\tint (*detect)(struct gsw_mt753x *gsw, struct chip_rev *crev);\n\tint (*init)(struct gsw_mt753x *gsw);\n\tint (*post_init)(struct gsw_mt753x *gsw);\n};\n\nextern struct list_head mt753x_devs;\n\nstruct gsw_mt753x *mt753x_get_gsw(u32 id);\nstruct gsw_mt753x *mt753x_get_first_gsw(void);\nvoid mt753x_put_gsw(void);\nvoid mt753x_lock_gsw(void);\n\nu32 mt753x_reg_read(struct gsw_mt753x *gsw, u32 reg);\nvoid mt753x_reg_write(struct gsw_mt753x *gsw, u32 reg, u32 val);\n\nint mt753x_mii_read(struct gsw_mt753x *gsw, int phy, int reg);\nvoid mt753x_mii_write(struct gsw_mt753x *gsw, int phy, int reg, u16 val);\n\nint mt753x_mmd_read(struct gsw_mt753x *gsw, int addr, int devad, u16 reg);\nvoid mt753x_mmd_write(struct gsw_mt753x *gsw, int addr, int devad, u16 reg,\n\t\t      u16 val);\n\nint mt753x_mmd_ind_read(struct gsw_mt753x *gsw, int addr, int devad, u16 reg);\nvoid mt753x_mmd_ind_write(struct gsw_mt753x *gsw, int addr, int devad, u16 reg,\n\t\t\t  u16 val);\n\nvoid mt753x_irq_worker(struct work_struct *work);\nvoid mt753x_irq_enable(struct gsw_mt753x *gsw);\n\n/* MDIO Indirect Access Registers */\n#define MII_MMD_ACC_CTL_REG\t\t0x0d\n#define MMD_CMD_S\t\t\t14\n#define MMD_CMD_M\t\t\t0xc000\n#define MMD_DEVAD_S\t\t\t0\n#define MMD_DEVAD_M\t\t\t0x1f\n\n/* MMD_CMD: MMD commands */\n#define MMD_ADDR\t\t\t0\n#define MMD_DATA\t\t\t1\n\n#define MII_MMD_ADDR_DATA_REG\t\t0x0e\n\n/* Procedure of MT753x Internal Register Access\n *\n * 1. Internal Register Address\n *\n *    The MT753x has a 16-bit register address and each register is 32-bit.\n *    This means the lowest two bits are not used as the register address is\n *    4-byte aligned.\n *\n *    Rest of the valid bits are divided into two parts:\n *      Bit 15..6 is the Page address\n *      Bit 5..2 is the low address\n *\n *    -------------------------------------------------------------------\n *    | 15  14  13  12  11  10   9   8   7   6 | 5   4   3   2 | 1   0  |\n *    |----------------------------------------|---------------|--------|\n *    |              Page Address              |    Address    | Unused |\n *    -------------------------------------------------------------------\n *\n * 2. MDIO access timing\n *\n *    The MT753x uses the following MDIO timing for a single register read\n *\n *      Phase 1: Write Page Address\n *    -------------------------------------------------------------------\n *    | ST | OP | PHY_ADDR | TYPE | RSVD | TA |  RSVD |    PAGE_ADDR    |\n *    -------------------------------------------------------------------\n *    | 01 | 01 |   11111  |   1  | 1111 | xx | 00000 | REG_ADDR[15..6] |\n *    -------------------------------------------------------------------\n *\n *      Phase 2: Write low Address & Read low word\n *    -------------------------------------------------------------------\n *    | ST | OP | PHY_ADDR | TYPE |    LOW_ADDR    | TA |      DATA     |\n *    -------------------------------------------------------------------\n *    | 01 | 10 |   11111  |   0  | REG_ADDR[5..2] | xx |  DATA[15..0]  |\n *    -------------------------------------------------------------------\n *\n *      Phase 3: Read high word\n *    -------------------------------------------------------------------\n *    | ST | OP | PHY_ADDR | TYPE | RSVD | TA |           DATA          |\n *    -------------------------------------------------------------------\n *    | 01 | 10 |   11111  |   1  | 0000 | xx |       DATA[31..16]      |\n *    -------------------------------------------------------------------\n *\n *    The MT753x uses the following MDIO timing for a single register write\n *\n *      Phase 1: Write Page Address (The same as read)\n *\n *      Phase 2: Write low Address and low word\n *    -------------------------------------------------------------------\n *    | ST | OP | PHY_ADDR | TYPE |    LOW_ADDR    | TA |      DATA     |\n *    -------------------------------------------------------------------\n *    | 01 | 01 |   11111  |   0  | REG_ADDR[5..2] | xx |  DATA[15..0]  |\n *    -------------------------------------------------------------------\n *\n *      Phase 3: write high word\n *    -------------------------------------------------------------------\n *    | ST | OP | PHY_ADDR | TYPE | RSVD | TA |           DATA          |\n *    -------------------------------------------------------------------\n *    | 01 | 01 |   11111  |   1  | 0000 | xx |       DATA[31..16]      |\n *    -------------------------------------------------------------------\n *\n */\n\n/* Internal Register Address fields */\n#define MT753X_REG_PAGE_ADDR_S\t\t6\n#define MT753X_REG_PAGE_ADDR_M\t\t0xffc0\n#define MT753X_REG_ADDR_S\t\t2\n#define MT753X_REG_ADDR_M\t\t0x3c\n#endif /* _MT753X_H_ */\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/mtk/mt753x/mt753x_common.c",
    "content": "// SPDX-License-Identifier: GPL-2.0-only\n/*\n * Copyright (c) 2018 MediaTek Inc.\n * Author: Weijie Gao <weijie.gao@mediatek.com>\n */\n\n#include <linux/kernel.h>\n#include <linux/delay.h>\n\n#include \"mt753x.h\"\n#include \"mt753x_regs.h\"\n\nvoid mt753x_irq_enable(struct gsw_mt753x *gsw)\n{\n\tu32 val;\n\tint i;\n\n\t/* Record initial PHY link status */\n\tfor (i = 0; i < MT753X_NUM_PHYS; i++) {\n\t\tval = gsw->mii_read(gsw, i, MII_BMSR);\n\t\tif (val & BMSR_LSTATUS)\n\t\t\tgsw->phy_link_sts |= BIT(i);\n\t}\n\n\tval = BIT(MT753X_NUM_PHYS) - 1;\n\n\tmt753x_reg_write(gsw, SYS_INT_EN, val);\n}\n\nstatic void display_port_link_status(struct gsw_mt753x *gsw, u32 port)\n{\n\tu32 pmsr, speed_bits;\n\tconst char *speed;\n\n\tpmsr = mt753x_reg_read(gsw, PMSR(port));\n\n\tspeed_bits = (pmsr & MAC_SPD_STS_M) >> MAC_SPD_STS_S;\n\n\tswitch (speed_bits) {\n\tcase MAC_SPD_10:\n\t\tspeed = \"10Mbps\";\n\t\tbreak;\n\tcase MAC_SPD_100:\n\t\tspeed = \"100Mbps\";\n\t\tbreak;\n\tcase MAC_SPD_1000:\n\t\tspeed = \"1Gbps\";\n\t\tbreak;\n\tcase MAC_SPD_2500:\n\t\tspeed = \"2.5Gbps\";\n\t\tbreak;\n\t}\n\n\tif (pmsr & MAC_LNK_STS) {\n\t\tdev_info(gsw->dev, \"Port %d Link is Up - %s/%s\\n\",\n\t\t\t port, speed, (pmsr & MAC_DPX_STS) ? \"Full\" : \"Half\");\n\t} else {\n\t\tdev_info(gsw->dev, \"Port %d Link is Down\\n\", port);\n\t}\n}\n\nvoid mt753x_irq_worker(struct work_struct *work)\n{\n\tstruct gsw_mt753x *gsw;\n\tu32 sts, physts, laststs;\n\tint i;\n\n\tgsw = container_of(work, struct gsw_mt753x, irq_worker);\n\n\tsts = mt753x_reg_read(gsw, SYS_INT_STS);\n\n\t/* Check for changed PHY link status */\n\tfor (i = 0; i < MT753X_NUM_PHYS; i++) {\n\t\tif (!(sts & PHY_LC_INT(i)))\n\t\t\tcontinue;\n\n\t\tlaststs = gsw->phy_link_sts & BIT(i);\n\t\tphysts = !!(gsw->mii_read(gsw, i, MII_BMSR) & BMSR_LSTATUS);\n\t\tphysts <<= i;\n\n\t\tif (physts ^ laststs) {\n\t\t\tgsw->phy_link_sts ^= BIT(i);\n\t\t\tdisplay_port_link_status(gsw, i);\n\t\t}\n\t}\n\n\tmt753x_reg_write(gsw, SYS_INT_STS, sts);\n\n\tenable_irq(gsw->irq);\n}\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/mtk/mt753x/mt753x_mdio.c",
    "content": "// SPDX-License-Identifier: GPL-2.0-only\n/*\n * Copyright (c) 2018 MediaTek Inc.\n * Author: Weijie Gao <weijie.gao@mediatek.com>\n */\n\n#include <linux/kernel.h>\n#include <linux/module.h>\n#include <linux/init.h>\n#include <linux/device.h>\n#include <linux/delay.h>\n#include <linux/reset.h>\n#include <linux/hrtimer.h>\n#include <linux/mii.h>\n#include <linux/of_mdio.h>\n#include <linux/of_platform.h>\n#include <linux/of_gpio.h>\n#include <linux/of_net.h>\n#include <linux/of_irq.h>\n#include <linux/phy.h>\n\n#include \"mt753x.h\"\n#include \"mt753x_swconfig.h\"\n#include \"mt753x_regs.h\"\n#include \"mt753x_nl.h\"\n#include \"mt7530.h\"\n#include \"mt7531.h\"\n\nstatic u32 mt753x_id;\nstruct list_head mt753x_devs;\nstatic DEFINE_MUTEX(mt753x_devs_lock);\n\nstatic struct mt753x_sw_id *mt753x_sw_ids[] = {\n\t&mt7530_id,\n\t&mt7531_id,\n};\n\nu32 mt753x_reg_read(struct gsw_mt753x *gsw, u32 reg)\n{\n\tu32 high, low;\n\n\tmutex_lock(&gsw->host_bus->mdio_lock);\n\n\tgsw->host_bus->write(gsw->host_bus, gsw->smi_addr, 0x1f,\n\t\t(reg & MT753X_REG_PAGE_ADDR_M) >> MT753X_REG_PAGE_ADDR_S);\n\n\tlow = gsw->host_bus->read(gsw->host_bus, gsw->smi_addr,\n\t\t(reg & MT753X_REG_ADDR_M) >> MT753X_REG_ADDR_S);\n\n\thigh = gsw->host_bus->read(gsw->host_bus, gsw->smi_addr, 0x10);\n\n\tmutex_unlock(&gsw->host_bus->mdio_lock);\n\n\treturn (high << 16) | (low & 0xffff);\n}\n\nvoid mt753x_reg_write(struct gsw_mt753x *gsw, u32 reg, u32 val)\n{\n\tmutex_lock(&gsw->host_bus->mdio_lock);\n\n\tgsw->host_bus->write(gsw->host_bus, gsw->smi_addr, 0x1f,\n\t\t(reg & MT753X_REG_PAGE_ADDR_M) >> MT753X_REG_PAGE_ADDR_S);\n\n\tgsw->host_bus->write(gsw->host_bus, gsw->smi_addr,\n\t\t(reg & MT753X_REG_ADDR_M) >> MT753X_REG_ADDR_S, val & 0xffff);\n\n\tgsw->host_bus->write(gsw->host_bus, gsw->smi_addr, 0x10, val >> 16);\n\n\tmutex_unlock(&gsw->host_bus->mdio_lock);\n}\n\n/* Indirect MDIO clause 22/45 access */\nstatic int mt753x_mii_rw(struct gsw_mt753x *gsw, int phy, int reg, u16 data,\n\t\t\t u32 cmd, u32 st)\n{\n\tktime_t timeout;\n\tu32 val, timeout_us;\n\tint ret = 0;\n\n\ttimeout_us = 100000;\n\ttimeout = ktime_add_us(ktime_get(), timeout_us);\n\twhile (1) {\n\t\tval = mt753x_reg_read(gsw, PHY_IAC);\n\n\t\tif ((val & PHY_ACS_ST) == 0)\n\t\t\tbreak;\n\n\t\tif (ktime_compare(ktime_get(), timeout) > 0)\n\t\t\treturn -ETIMEDOUT;\n\t}\n\n\tval = (st << MDIO_ST_S) |\n\t      ((cmd << MDIO_CMD_S) & MDIO_CMD_M) |\n\t      ((phy << MDIO_PHY_ADDR_S) & MDIO_PHY_ADDR_M) |\n\t      ((reg << MDIO_REG_ADDR_S) & MDIO_REG_ADDR_M);\n\n\tif (cmd == MDIO_CMD_WRITE || cmd == MDIO_CMD_ADDR)\n\t\tval |= data & MDIO_RW_DATA_M;\n\n\tmt753x_reg_write(gsw, PHY_IAC, val | PHY_ACS_ST);\n\n\ttimeout_us = 100000;\n\ttimeout = ktime_add_us(ktime_get(), timeout_us);\n\twhile (1) {\n\t\tval = mt753x_reg_read(gsw, PHY_IAC);\n\n\t\tif ((val & PHY_ACS_ST) == 0)\n\t\t\tbreak;\n\n\t\tif (ktime_compare(ktime_get(), timeout) > 0)\n\t\t\treturn -ETIMEDOUT;\n\t}\n\n\tif (cmd == MDIO_CMD_READ || cmd == MDIO_CMD_READ_C45) {\n\t\tval = mt753x_reg_read(gsw, PHY_IAC);\n\t\tret = val & MDIO_RW_DATA_M;\n\t}\n\n\treturn ret;\n}\n\nint mt753x_mii_read(struct gsw_mt753x *gsw, int phy, int reg)\n{\n\tint val;\n\n\tif (phy < MT753X_NUM_PHYS)\n\t\tphy = (gsw->phy_base + phy) & MT753X_SMI_ADDR_MASK;\n\n\tmutex_lock(&gsw->mii_lock);\n\tval = mt753x_mii_rw(gsw, phy, reg, 0, MDIO_CMD_READ, MDIO_ST_C22);\n\tmutex_unlock(&gsw->mii_lock);\n\n\treturn val;\n}\n\nvoid mt753x_mii_write(struct gsw_mt753x *gsw, int phy, int reg, u16 val)\n{\n\tif (phy < MT753X_NUM_PHYS)\n\t\tphy = (gsw->phy_base + phy) & MT753X_SMI_ADDR_MASK;\n\n\tmutex_lock(&gsw->mii_lock);\n\tmt753x_mii_rw(gsw, phy, reg, val, MDIO_CMD_WRITE, MDIO_ST_C22);\n\tmutex_unlock(&gsw->mii_lock);\n}\n\nint mt753x_mmd_read(struct gsw_mt753x *gsw, int addr, int devad, u16 reg)\n{\n\tint val;\n\n\tif (addr < MT753X_NUM_PHYS)\n\t\taddr = (gsw->phy_base + addr) & MT753X_SMI_ADDR_MASK;\n\n\tmutex_lock(&gsw->mii_lock);\n\tmt753x_mii_rw(gsw, addr, devad, reg, MDIO_CMD_ADDR, MDIO_ST_C45);\n\tval = mt753x_mii_rw(gsw, addr, devad, 0, MDIO_CMD_READ_C45,\n\t\t\t    MDIO_ST_C45);\n\tmutex_unlock(&gsw->mii_lock);\n\n\treturn val;\n}\n\nvoid mt753x_mmd_write(struct gsw_mt753x *gsw, int addr, int devad, u16 reg,\n\t\t      u16 val)\n{\n\tif (addr < MT753X_NUM_PHYS)\n\t\taddr = (gsw->phy_base + addr) & MT753X_SMI_ADDR_MASK;\n\n\tmutex_lock(&gsw->mii_lock);\n\tmt753x_mii_rw(gsw, addr, devad, reg, MDIO_CMD_ADDR, MDIO_ST_C45);\n\tmt753x_mii_rw(gsw, addr, devad, val, MDIO_CMD_WRITE, MDIO_ST_C45);\n\tmutex_unlock(&gsw->mii_lock);\n}\n\nint mt753x_mmd_ind_read(struct gsw_mt753x *gsw, int addr, int devad, u16 reg)\n{\n\tu16 val;\n\n\tif (addr < MT753X_NUM_PHYS)\n\t\taddr = (gsw->phy_base + addr) & MT753X_SMI_ADDR_MASK;\n\n\tmutex_lock(&gsw->mii_lock);\n\n\tmt753x_mii_rw(gsw, addr, MII_MMD_ACC_CTL_REG,\n\t\t      (MMD_ADDR << MMD_CMD_S) |\n\t\t      ((devad << MMD_DEVAD_S) & MMD_DEVAD_M),\n\t\t      MDIO_CMD_WRITE, MDIO_ST_C22);\n\n\tmt753x_mii_rw(gsw, addr, MII_MMD_ADDR_DATA_REG, reg,\n\t\t      MDIO_CMD_WRITE, MDIO_ST_C22);\n\n\tmt753x_mii_rw(gsw, addr, MII_MMD_ACC_CTL_REG,\n\t\t      (MMD_DATA << MMD_CMD_S) |\n\t\t      ((devad << MMD_DEVAD_S) & MMD_DEVAD_M),\n\t\t      MDIO_CMD_WRITE, MDIO_ST_C22);\n\n\tval = mt753x_mii_rw(gsw, addr, MII_MMD_ADDR_DATA_REG, 0,\n\t\t\t    MDIO_CMD_READ, MDIO_ST_C22);\n\n\tmutex_unlock(&gsw->mii_lock);\n\n\treturn val;\n}\n\nvoid mt753x_mmd_ind_write(struct gsw_mt753x *gsw, int addr, int devad, u16 reg,\n\t\t\t  u16 val)\n{\n\tif (addr < MT753X_NUM_PHYS)\n\t\taddr = (gsw->phy_base + addr) & MT753X_SMI_ADDR_MASK;\n\n\tmutex_lock(&gsw->mii_lock);\n\n\tmt753x_mii_rw(gsw, addr, MII_MMD_ACC_CTL_REG,\n\t\t      (MMD_ADDR << MMD_CMD_S) |\n\t\t      ((devad << MMD_DEVAD_S) & MMD_DEVAD_M),\n\t\t      MDIO_CMD_WRITE, MDIO_ST_C22);\n\n\tmt753x_mii_rw(gsw, addr, MII_MMD_ADDR_DATA_REG, reg,\n\t\t      MDIO_CMD_WRITE, MDIO_ST_C22);\n\n\tmt753x_mii_rw(gsw, addr, MII_MMD_ACC_CTL_REG,\n\t\t      (MMD_DATA << MMD_CMD_S) |\n\t\t      ((devad << MMD_DEVAD_S) & MMD_DEVAD_M),\n\t\t      MDIO_CMD_WRITE, MDIO_ST_C22);\n\n\tmt753x_mii_rw(gsw, addr, MII_MMD_ADDR_DATA_REG, val,\n\t\t      MDIO_CMD_WRITE, MDIO_ST_C22);\n\n\tmutex_unlock(&gsw->mii_lock);\n}\n\nstatic inline int mt753x_get_duplex(const struct device_node *np)\n{\n\treturn of_property_read_bool(np, \"full-duplex\");\n}\n\nstatic void mt753x_load_port_cfg(struct gsw_mt753x *gsw)\n{\n\tstruct device_node *port_np;\n\tstruct device_node *fixed_link_node;\n\tstruct mt753x_port_cfg *port_cfg;\n\tu32 port;\n\n\tfor_each_child_of_node(gsw->dev->of_node, port_np) {\n\t\tif (!of_device_is_compatible(port_np, \"mediatek,mt753x-port\"))\n\t\t\tcontinue;\n\n\t\tif (!of_device_is_available(port_np))\n\t\t\tcontinue;\n\n\t\tif (of_property_read_u32(port_np, \"reg\", &port))\n\t\t\tcontinue;\n\n\t\tswitch (port) {\n\t\tcase 5:\n\t\t\tport_cfg = &gsw->port5_cfg;\n\t\t\tbreak;\n\t\tcase 6:\n\t\t\tport_cfg = &gsw->port6_cfg;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tcontinue;\n\t\t}\n\n\t\tif (port_cfg->enabled) {\n\t\t\tdev_info(gsw->dev, \"duplicated node for port%d\\n\",\n\t\t\t\t port_cfg->phy_mode);\n\t\t\tcontinue;\n\t\t}\n\n\t\tport_cfg->np = port_np;\n\n\t\tif (of_get_phy_mode(port_np, &port_cfg->phy_mode) < 0) {\n\t\t\tdev_info(gsw->dev, \"incorrect phy-mode %d\\n\", port);\n\t\t\tcontinue;\n\t\t}\n\n\t\tfixed_link_node = of_get_child_by_name(port_np, \"fixed-link\");\n\t\tif (fixed_link_node) {\n\t\t\tu32 speed;\n\n\t\t\tport_cfg->force_link = 1;\n\t\t\tport_cfg->duplex = mt753x_get_duplex(fixed_link_node);\n\n\t\t\tif (of_property_read_u32(fixed_link_node, \"speed\",\n\t\t\t\t\t\t &speed)) {\n\t\t\t\tspeed = 0;\n\t\t\t\tcontinue;\n\t\t\t}\n\n\t\t\tof_node_put(fixed_link_node);\n\n\t\t\tswitch (speed) {\n\t\t\tcase 10:\n\t\t\t\tport_cfg->speed = MAC_SPD_10;\n\t\t\t\tbreak;\n\t\t\tcase 100:\n\t\t\t\tport_cfg->speed = MAC_SPD_100;\n\t\t\t\tbreak;\n\t\t\tcase 1000:\n\t\t\t\tport_cfg->speed = MAC_SPD_1000;\n\t\t\t\tbreak;\n\t\t\tcase 2500:\n\t\t\t\tport_cfg->speed = MAC_SPD_2500;\n\t\t\t\tbreak;\n\t\t\tdefault:\n\t\t\t\tdev_info(gsw->dev, \"incorrect speed %d\\n\",\n\t\t\t\t\t speed);\n\t\t\t\tcontinue;\n\t\t\t}\n\t\t}\n\n\t\tport_cfg->enabled = 1;\n\t}\n}\n\nstatic void mt753x_add_gsw(struct gsw_mt753x *gsw)\n{\n\tmutex_lock(&mt753x_devs_lock);\n\tgsw->id = mt753x_id++;\n\tINIT_LIST_HEAD(&gsw->list);\n\tlist_add_tail(&gsw->list, &mt753x_devs);\n\tmutex_unlock(&mt753x_devs_lock);\n}\n\nstatic void mt753x_remove_gsw(struct gsw_mt753x *gsw)\n{\n\tmutex_lock(&mt753x_devs_lock);\n\tlist_del(&gsw->list);\n\tmutex_unlock(&mt753x_devs_lock);\n}\n\n\nstruct gsw_mt753x *mt753x_get_gsw(u32 id)\n{\n\tstruct gsw_mt753x *dev;\n\n\tmutex_lock(&mt753x_devs_lock);\n\n\tlist_for_each_entry(dev, &mt753x_devs, list) {\n\t\tif (dev->id == id)\n\t\t\treturn dev;\n\t}\n\n\tmutex_unlock(&mt753x_devs_lock);\n\n\treturn NULL;\n}\n\nstruct gsw_mt753x *mt753x_get_first_gsw(void)\n{\n\tstruct gsw_mt753x *dev;\n\n\tmutex_lock(&mt753x_devs_lock);\n\n\tlist_for_each_entry(dev, &mt753x_devs, list)\n\t\treturn dev;\n\n\tmutex_unlock(&mt753x_devs_lock);\n\n\treturn NULL;\n}\n\nvoid mt753x_put_gsw(void)\n{\n\tmutex_unlock(&mt753x_devs_lock);\n}\n\nvoid mt753x_lock_gsw(void)\n{\n\tmutex_lock(&mt753x_devs_lock);\n}\n\nstatic int mt753x_hw_reset(struct gsw_mt753x *gsw)\n{\n\tstruct device_node *np = gsw->dev->of_node;\n\tstruct reset_control *rstc;\n\tint mcm;\n\tint ret = -EINVAL;\n\n\tmcm = of_property_read_bool(np, \"mediatek,mcm\");\n\tif (mcm) {\n\t\trstc = devm_reset_control_get(gsw->dev, \"mcm\");\n\t\tret = IS_ERR(rstc);\n\t\tif (IS_ERR(rstc)) {\n\t\t\tdev_err(gsw->dev, \"Missing reset ctrl of switch\\n\");\n\t\t\treturn ret;\n\t\t}\n\n\t\treset_control_assert(rstc);\n\t\tmsleep(30);\n\t\treset_control_deassert(rstc);\n\n\t\tgsw->reset_pin = -1;\n\t\treturn 0;\n\t}\n\n\tgsw->reset_pin = of_get_named_gpio(np, \"reset-gpios\", 0);\n\tif (gsw->reset_pin < 0) {\n\t\tdev_err(gsw->dev, \"Missing reset pin of switch\\n\");\n\t\treturn ret;\n\t}\n\n\tret = devm_gpio_request(gsw->dev, gsw->reset_pin, \"mt753x-reset\");\n\tif (ret) {\n\t\tdev_info(gsw->dev, \"Failed to request gpio %d\\n\",\n\t\t\t gsw->reset_pin);\n\t\treturn ret;\n\t}\n\n\tgpio_direction_output(gsw->reset_pin, 0);\n\tmsleep(30);\n\tgpio_set_value(gsw->reset_pin, 1);\n\tmsleep(500);\n\n\treturn 0;\n}\n\nstatic irqreturn_t mt753x_irq_handler(int irq, void *dev)\n{\n\tstruct gsw_mt753x *gsw = dev;\n\n\tdisable_irq_nosync(gsw->irq);\n\n\tschedule_work(&gsw->irq_worker);\n\n\treturn IRQ_HANDLED;\n}\n\nstatic int mt753x_probe(struct platform_device *pdev)\n{\n\tstruct gsw_mt753x *gsw;\n\tstruct mt753x_sw_id *sw;\n\tstruct device_node *np = pdev->dev.of_node;\n\tstruct device_node *mdio;\n\tstruct mii_bus *mdio_bus;\n\tint ret = -EINVAL;\n\tstruct chip_rev rev;\n\tstruct mt753x_mapping *map;\n\tint i;\n\n\tmdio = of_parse_phandle(np, \"mediatek,mdio\", 0);\n\tif (!mdio)\n\t\treturn -EINVAL;\n\n\tmdio_bus = of_mdio_find_bus(mdio);\n\tif (!mdio_bus)\n\t\treturn -EPROBE_DEFER;\n\n\tgsw = devm_kzalloc(&pdev->dev, sizeof(struct gsw_mt753x), GFP_KERNEL);\n\tif (!gsw)\n\t\treturn -ENOMEM;\n\n\tgsw->host_bus = mdio_bus;\n\tgsw->dev = &pdev->dev;\n\tmutex_init(&gsw->mii_lock);\n\n\t/* Switch hard reset */\n\tif (mt753x_hw_reset(gsw))\n\t\tgoto fail;\n\n\t/* Fetch the SMI address dirst */\n\tif (of_property_read_u32(np, \"mediatek,smi-addr\", &gsw->smi_addr))\n\t\tgsw->smi_addr = MT753X_DFL_SMI_ADDR;\n\n\t/* Get LAN/WAN port mapping */\n\tmap = mt753x_find_mapping(np);\n\tif (map) {\n\t\tmt753x_apply_mapping(gsw, map);\n\t\tgsw->global_vlan_enable = 1;\n\t\tdev_info(gsw->dev, \"LAN/WAN VLAN setting=%s\\n\", map->name);\n\t}\n\n\t/* Load MAC port configurations */\n\tmt753x_load_port_cfg(gsw);\n\n\t/* Check for valid switch and then initialize */\n\tfor (i = 0; i < ARRAY_SIZE(mt753x_sw_ids); i++) {\n\t\tif (!mt753x_sw_ids[i]->detect(gsw, &rev)) {\n\t\t\tsw = mt753x_sw_ids[i];\n\n\t\t\tgsw->name = rev.name;\n\t\t\tgsw->model = sw->model;\n\n\t\t\tdev_info(gsw->dev, \"Switch is MediaTek %s rev %d\",\n\t\t\t\t gsw->name, rev.rev);\n\n\t\t\t/* Initialize the switch */\n\t\t\tret = sw->init(gsw);\n\t\t\tif (ret)\n\t\t\t\tgoto fail;\n\n\t\t\tbreak;\n\t\t}\n\t}\n\n\tif (i >= ARRAY_SIZE(mt753x_sw_ids)) {\n\t\tdev_err(gsw->dev, \"No mt753x switch found\\n\");\n\t\tgoto fail;\n\t}\n\n\tgsw->irq = platform_get_irq(pdev, 0);\n\tif (gsw->irq >= 0) {\n\t\tret = devm_request_irq(gsw->dev, gsw->irq, mt753x_irq_handler,\n\t\t\t\t       0, dev_name(gsw->dev), gsw);\n\t\tif (ret) {\n\t\t\tdev_err(gsw->dev, \"Failed to request irq %d\\n\",\n\t\t\t\tgsw->irq);\n\t\t\tgoto fail;\n\t\t}\n\n\t\tINIT_WORK(&gsw->irq_worker, mt753x_irq_worker);\n\t}\n\n\tplatform_set_drvdata(pdev, gsw);\n\n\tgsw->phy_status_poll = of_property_read_bool(gsw->dev->of_node,\n\t\t\t\t\t\t     \"mediatek,phy-poll\");\n\n\tmt753x_add_gsw(gsw);\n\n\tmt753x_swconfig_init(gsw);\n\n\tif (sw->post_init)\n\t\tsw->post_init(gsw);\n\n\tif (gsw->irq >= 0)\n\t\tmt753x_irq_enable(gsw);\n\n\treturn 0;\n\nfail:\n\tdevm_kfree(&pdev->dev, gsw);\n\n\treturn ret;\n}\n\nstatic int mt753x_remove(struct platform_device *pdev)\n{\n\tstruct gsw_mt753x *gsw = platform_get_drvdata(pdev);\n\n\tif (gsw->irq >= 0)\n\t\tcancel_work_sync(&gsw->irq_worker);\n\n\tif (gsw->reset_pin >= 0)\n\t\tdevm_gpio_free(&pdev->dev, gsw->reset_pin);\n\n#ifdef CONFIG_SWCONFIG\n\tmt753x_swconfig_destroy(gsw);\n#endif\n\n\tmt753x_remove_gsw(gsw);\n\n\tplatform_set_drvdata(pdev, NULL);\n\n\treturn 0;\n}\n\nstatic const struct of_device_id mt753x_ids[] = {\n\t{ .compatible = \"mediatek,mt753x\" },\n\t{ },\n};\n\nMODULE_DEVICE_TABLE(of, mt753x_ids);\n\nstatic struct platform_driver mt753x_driver = {\n\t.probe = mt753x_probe,\n\t.remove = mt753x_remove,\n\t.driver = {\n\t\t.name = \"mt753x\",\n\t\t.of_match_table = mt753x_ids,\n\t},\n};\n\nstatic int __init mt753x_init(void)\n{\n\tint ret;\n\n\tINIT_LIST_HEAD(&mt753x_devs);\n\tret = platform_driver_register(&mt753x_driver);\n\n\tmt753x_nl_init();\n\n\treturn ret;\n}\nmodule_init(mt753x_init);\n\nstatic void __exit mt753x_exit(void)\n{\n\tmt753x_nl_exit();\n\n\tplatform_driver_unregister(&mt753x_driver);\n}\nmodule_exit(mt753x_exit);\n\nMODULE_LICENSE(\"GPL\");\nMODULE_AUTHOR(\"Weijie Gao <weijie.gao@mediatek.com>\");\nMODULE_DESCRIPTION(\"Driver for MediaTek MT753x Gigabit Switch\");\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/mtk/mt753x/mt753x_nl.c",
    "content": "// SPDX-License-Identifier: GPL-2.0-only\n/*\n * Copyright (c) 2018 MediaTek Inc.\n * Author: Sirui Zhao <Sirui.Zhao@mediatek.com>\n */\n\n#include <linux/types.h>\n#include <linux/kernel.h>\n#include <linux/module.h>\n#include <linux/init.h>\n#include <net/genetlink.h>\n\n#include \"mt753x.h\"\n#include \"mt753x_nl.h\"\n\nstruct mt753x_nl_cmd_item {\n\tenum mt753x_cmd cmd;\n\tbool require_dev;\n\tint (*process)(struct genl_info *info, struct gsw_mt753x *gsw);\n\tu32 nr_required_attrs;\n\tconst enum mt753x_attr *required_attrs;\n};\n\nstatic int mt753x_nl_response(struct sk_buff *skb, struct genl_info *info);\n\n/*\nstatic const struct nla_policy mt753x_nl_cmd_policy[] = {\n\t[MT753X_ATTR_TYPE_MESG] = { .type = NLA_STRING },\n\t[MT753X_ATTR_TYPE_PHY] = { .type = NLA_S32 },\n\t[MT753X_ATTR_TYPE_REG] = { .type = NLA_S32 },\n\t[MT753X_ATTR_TYPE_VAL] = { .type = NLA_S32 },\n\t[MT753X_ATTR_TYPE_DEV_NAME] = { .type = NLA_S32 },\n\t[MT753X_ATTR_TYPE_DEV_ID] = { .type = NLA_S32 },\n\t[MT753X_ATTR_TYPE_DEVAD] = { .type = NLA_S32 },\n};\n*/\n\nstatic const struct genl_ops mt753x_nl_ops[] = {\n\t{\n\t\t.cmd = MT753X_CMD_REQUEST,\n\t\t.doit = mt753x_nl_response,\n//\t\t.policy = mt753x_nl_cmd_policy,\n\t\t.flags = GENL_ADMIN_PERM,\n\t}, {\n\t\t.cmd = MT753X_CMD_READ,\n\t\t.doit = mt753x_nl_response,\n//\t\t.policy = mt753x_nl_cmd_policy,\n\t\t.flags = GENL_ADMIN_PERM,\n\t}, {\n\t\t.cmd = MT753X_CMD_WRITE,\n\t\t.doit = mt753x_nl_response,\n//\t\t.policy = mt753x_nl_cmd_policy,\n\t\t.flags = GENL_ADMIN_PERM,\n\t},\n};\n\nstatic struct genl_family mt753x_nl_family = {\n\t.name =\t\tMT753X_GENL_NAME,\n\t.version =\tMT753X_GENL_VERSION,\n\t.maxattr =\tMT753X_NR_ATTR_TYPE,\n\t.ops =\t\tmt753x_nl_ops,\n\t.n_ops =\tARRAY_SIZE(mt753x_nl_ops),\n};\n\nstatic int mt753x_nl_list_devs(char *buff, int size)\n{\n\tstruct gsw_mt753x *gsw;\n\tint len, total = 0;\n\tchar buf[80];\n\n\tmemset(buff, 0, size);\n\n\tmt753x_lock_gsw();\n\n\tlist_for_each_entry(gsw, &mt753x_devs, list) {\n\t\tlen = snprintf(buf, sizeof(buf),\n\t\t\t       \"id: %d, model: %s, node: %s\\n\",\n\t\t\t       gsw->id, gsw->name, gsw->dev->of_node->name);\n\t\tstrncat(buff, buf, size - total);\n\t\ttotal += len;\n\t}\n\n\tmt753x_put_gsw();\n\n\treturn total;\n}\n\nstatic int mt753x_nl_prepare_reply(struct genl_info *info, u8 cmd,\n\t\t\t\t   struct sk_buff **skbp)\n{\n\tstruct sk_buff *msg;\n\tvoid *reply;\n\n\tif (!info)\n\t\treturn -EINVAL;\n\n\tmsg = genlmsg_new(NLMSG_GOODSIZE, GFP_KERNEL);\n\tif (!msg)\n\t\treturn -ENOMEM;\n\n\t/* Construct send-back message header */\n\treply = genlmsg_put(msg, info->snd_portid, info->snd_seq,\n\t\t\t    &mt753x_nl_family, 0, cmd);\n\tif (!reply) {\n\t\tnlmsg_free(msg);\n\t\treturn -EINVAL;\n\t}\n\n\t*skbp = msg;\n\treturn 0;\n}\n\nstatic int mt753x_nl_send_reply(struct sk_buff *skb, struct genl_info *info)\n{\n\tstruct genlmsghdr *genlhdr = nlmsg_data(nlmsg_hdr(skb));\n\tvoid *reply = genlmsg_data(genlhdr);\n\n\t/* Finalize a generic netlink message (update message header) */\n\tgenlmsg_end(skb, reply);\n\n\t/* reply to a request */\n\treturn genlmsg_reply(skb, info);\n}\n\nstatic s32 mt753x_nl_get_s32(struct genl_info *info, enum mt753x_attr attr,\n\t\t\t     s32 defval)\n{\n\tstruct nlattr *na;\n\n\tna = info->attrs[attr];\n\tif (na)\n\t\treturn nla_get_s32(na);\n\n\treturn defval;\n}\n\nstatic int mt753x_nl_get_u32(struct genl_info *info, enum mt753x_attr attr,\n\t\t\t     u32 *val)\n{\n\tstruct nlattr *na;\n\n\tna = info->attrs[attr];\n\tif (na) {\n\t\t*val = nla_get_u32(na);\n\t\treturn 0;\n\t}\n\n\treturn -1;\n}\n\nstatic struct gsw_mt753x *mt753x_nl_parse_find_gsw(struct genl_info *info)\n{\n\tstruct gsw_mt753x *gsw;\n\tstruct nlattr *na;\n\tint gsw_id;\n\n\tna = info->attrs[MT753X_ATTR_TYPE_DEV_ID];\n\tif (na) {\n\t\tgsw_id = nla_get_s32(na);\n\t\tif (gsw_id >= 0)\n\t\t\tgsw = mt753x_get_gsw(gsw_id);\n\t\telse\n\t\t\tgsw = mt753x_get_first_gsw();\n\t} else {\n\t\tgsw = mt753x_get_first_gsw();\n\t}\n\n\treturn gsw;\n}\n\nstatic int mt753x_nl_get_swdevs(struct genl_info *info, struct gsw_mt753x *gsw)\n{\n\tstruct sk_buff *rep_skb = NULL;\n\tchar dev_info[512];\n\tint ret;\n\n\tret = mt753x_nl_list_devs(dev_info, sizeof(dev_info));\n\tif (!ret) {\n\t\tpr_info(\"No switch registered\\n\");\n\t\treturn -EINVAL;\n\t}\n\n\tret = mt753x_nl_prepare_reply(info, MT753X_CMD_REPLY, &rep_skb);\n\tif (ret < 0)\n\t\tgoto err;\n\n\tret = nla_put_string(rep_skb, MT753X_ATTR_TYPE_MESG, dev_info);\n\tif (ret < 0)\n\t\tgoto err;\n\n\treturn mt753x_nl_send_reply(rep_skb, info);\n\nerr:\n\tif (rep_skb)\n\t\tnlmsg_free(rep_skb);\n\n\treturn ret;\n}\n\nstatic int mt753x_nl_reply_read(struct genl_info *info, struct gsw_mt753x *gsw)\n{\n\tstruct sk_buff *rep_skb = NULL;\n\ts32 phy, devad, reg;\n\tint value;\n\tint ret = 0;\n\n\tphy = mt753x_nl_get_s32(info, MT753X_ATTR_TYPE_PHY, -1);\n\tdevad = mt753x_nl_get_s32(info, MT753X_ATTR_TYPE_DEVAD, -1);\n\treg = mt753x_nl_get_s32(info, MT753X_ATTR_TYPE_REG, -1);\n\n\tif (reg < 0)\n\t\tgoto err;\n\n\tret = mt753x_nl_prepare_reply(info, MT753X_CMD_READ, &rep_skb);\n\tif (ret < 0)\n\t\tgoto err;\n\n\tif (phy >= 0) {\n\t\tif (devad < 0)\n\t\t\tvalue = gsw->mii_read(gsw, phy, reg);\n\t\telse\n\t\t\tvalue = gsw->mmd_read(gsw, phy, devad, reg);\n\t} else {\n\t\tvalue = mt753x_reg_read(gsw, reg);\n\t}\n\n\tret = nla_put_s32(rep_skb, MT753X_ATTR_TYPE_REG, reg);\n\tif (ret < 0)\n\t\tgoto err;\n\n\tret = nla_put_s32(rep_skb, MT753X_ATTR_TYPE_VAL, value);\n\tif (ret < 0)\n\t\tgoto err;\n\n\treturn mt753x_nl_send_reply(rep_skb, info);\n\nerr:\n\tif (rep_skb)\n\t\tnlmsg_free(rep_skb);\n\n\treturn ret;\n}\n\nstatic int mt753x_nl_reply_write(struct genl_info *info, struct gsw_mt753x *gsw)\n{\n\tstruct sk_buff *rep_skb = NULL;\n\ts32 phy, devad, reg;\n\tu32 value;\n\tint ret = 0;\n\n\tphy = mt753x_nl_get_s32(info, MT753X_ATTR_TYPE_PHY, -1);\n\tdevad = mt753x_nl_get_s32(info, MT753X_ATTR_TYPE_DEVAD, -1);\n\treg = mt753x_nl_get_s32(info, MT753X_ATTR_TYPE_REG, -1);\n\n\tif (mt753x_nl_get_u32(info, MT753X_ATTR_TYPE_VAL, &value))\n\t\tgoto err;\n\n\tif (reg < 0)\n\t\tgoto err;\n\n\tret = mt753x_nl_prepare_reply(info, MT753X_CMD_WRITE, &rep_skb);\n\tif (ret < 0)\n\t\tgoto err;\n\n\tif (phy >= 0) {\n\t\tif (devad < 0)\n\t\t\tgsw->mii_write(gsw, phy, reg, value);\n\t\telse\n\t\t\tgsw->mmd_write(gsw, phy, devad, reg, value);\n\t} else {\n\t\tmt753x_reg_write(gsw, reg, value);\n\t}\n\n\tret = nla_put_s32(rep_skb, MT753X_ATTR_TYPE_REG, reg);\n\tif (ret < 0)\n\t\tgoto err;\n\n\tret = nla_put_s32(rep_skb, MT753X_ATTR_TYPE_VAL, value);\n\tif (ret < 0)\n\t\tgoto err;\n\n\treturn mt753x_nl_send_reply(rep_skb, info);\n\nerr:\n\tif (rep_skb)\n\t\tnlmsg_free(rep_skb);\n\n\treturn ret;\n}\n\nstatic const enum mt753x_attr mt753x_nl_cmd_read_attrs[] = {\n\tMT753X_ATTR_TYPE_REG\n};\n\nstatic const enum mt753x_attr mt753x_nl_cmd_write_attrs[] = {\n\tMT753X_ATTR_TYPE_REG,\n\tMT753X_ATTR_TYPE_VAL\n};\n\nstatic const struct mt753x_nl_cmd_item mt753x_nl_cmds[] = {\n\t{\n\t\t.cmd = MT753X_CMD_REQUEST,\n\t\t.require_dev = false,\n\t\t.process = mt753x_nl_get_swdevs\n\t}, {\n\t\t.cmd = MT753X_CMD_READ,\n\t\t.require_dev = true,\n\t\t.process = mt753x_nl_reply_read,\n\t\t.required_attrs = mt753x_nl_cmd_read_attrs,\n\t\t.nr_required_attrs = ARRAY_SIZE(mt753x_nl_cmd_read_attrs),\n\t}, {\n\t\t.cmd = MT753X_CMD_WRITE,\n\t\t.require_dev = true,\n\t\t.process = mt753x_nl_reply_write,\n\t\t.required_attrs = mt753x_nl_cmd_write_attrs,\n\t\t.nr_required_attrs = ARRAY_SIZE(mt753x_nl_cmd_write_attrs),\n\t}\n};\n\nstatic int mt753x_nl_response(struct sk_buff *skb, struct genl_info *info)\n{\n\tstruct genlmsghdr *hdr = nlmsg_data(info->nlhdr);\n\tconst struct mt753x_nl_cmd_item *cmditem = NULL;\n\tstruct gsw_mt753x *gsw = NULL;\n\tu32 sat_req_attrs = 0;\n\tint i, ret;\n\n\tfor (i = 0; i < ARRAY_SIZE(mt753x_nl_cmds); i++) {\n\t\tif (hdr->cmd == mt753x_nl_cmds[i].cmd) {\n\t\t\tcmditem = &mt753x_nl_cmds[i];\n\t\t\tbreak;\n\t\t}\n\t}\n\n\tif (!cmditem) {\n\t\tpr_info(\"mt753x-nl: unknown cmd %u\\n\", hdr->cmd);\n\t\treturn -EINVAL;\n\t}\n\n\tfor (i = 0; i < cmditem->nr_required_attrs; i++) {\n\t\tif (info->attrs[cmditem->required_attrs[i]])\n\t\t\tsat_req_attrs++;\n\t}\n\n\tif (sat_req_attrs != cmditem->nr_required_attrs) {\n\t\tpr_info(\"mt753x-nl: missing required attr(s) for cmd %u\\n\",\n\t\t\thdr->cmd);\n\t\treturn -EINVAL;\n\t}\n\n\tif (cmditem->require_dev) {\n\t\tgsw = mt753x_nl_parse_find_gsw(info);\n\t\tif (!gsw) {\n\t\t\tpr_info(\"mt753x-nl: failed to find switch dev\\n\");\n\t\t\treturn -EINVAL;\n\t\t}\n\t}\n\n\tret = cmditem->process(info, gsw);\n\n\tmt753x_put_gsw();\n\n\treturn ret;\n}\n\nint __init mt753x_nl_init(void)\n{\n\tint ret;\n\n\tret = genl_register_family(&mt753x_nl_family);\n\tif (ret) {\n\t\tpr_info(\"mt753x-nl: genl_register_family_with_ops failed\\n\");\n\t\treturn ret;\n\t}\n\n\treturn 0;\n}\n\nvoid __exit mt753x_nl_exit(void)\n{\n\tgenl_unregister_family(&mt753x_nl_family);\n}\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/mtk/mt753x/mt753x_nl.h",
    "content": "/* SPDX-License-Identifier: GPL-2.0-only */\n/*\n * Copyright (c) 2018 MediaTek Inc.\n * Author: Sirui Zhao <Sirui.Zhao@mediatek.com>\n */\n\n#ifndef _MT753X_NL_H_\n#define _MT753X_NL_H_\n\n#define MT753X_GENL_NAME\t\t\"mt753x\"\n#define MT753X_GENL_VERSION\t\t0x1\n\nenum mt753x_cmd {\n\tMT753X_CMD_UNSPEC = 0,\n\tMT753X_CMD_REQUEST,\n\tMT753X_CMD_REPLY,\n\tMT753X_CMD_READ,\n\tMT753X_CMD_WRITE,\n\n\t__MT753X_CMD_MAX,\n};\n\nenum mt753x_attr {\n\tMT753X_ATTR_TYPE_UNSPEC = 0,\n\tMT753X_ATTR_TYPE_MESG,\n\tMT753X_ATTR_TYPE_PHY,\n\tMT753X_ATTR_TYPE_DEVAD,\n\tMT753X_ATTR_TYPE_REG,\n\tMT753X_ATTR_TYPE_VAL,\n\tMT753X_ATTR_TYPE_DEV_NAME,\n\tMT753X_ATTR_TYPE_DEV_ID,\n\n\t__MT753X_ATTR_TYPE_MAX,\n};\n\n#define MT753X_NR_ATTR_TYPE\t\t(__MT753X_ATTR_TYPE_MAX - 1)\n\n#ifdef __KERNEL__\nint __init mt753x_nl_init(void);\nvoid __exit mt753x_nl_exit(void);\n#endif /* __KERNEL__ */\n\n#endif /* _MT753X_NL_H_ */\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/mtk/mt753x/mt753x_regs.h",
    "content": "/* SPDX-License-Identifier: GPL-2.0-only */\n/*\n * Copyright (c) 2018 MediaTek Inc.\n * Author: Weijie Gao <weijie.gao@mediatek.com>\n */\n\n#ifndef _MT753X_REGS_H_\n#define _MT753X_REGS_H_\n\n#include <linux/bitops.h>\n\n/* Values of Egress TAG Control */\n#define ETAG_CTRL_UNTAG\t\t\t0\n#define ETAG_CTRL_TAG\t\t\t2\n#define ETAG_CTRL_SWAP\t\t\t1\n#define ETAG_CTRL_STACK\t\t\t3\n\n#define VTCR\t\t\t\t0x90\n#define VAWD1\t\t\t\t0x94\n#define VAWD2\t\t\t\t0x98\n\n/* Fields of VTCR */\n#define VTCR_BUSY\t\t\tBIT(31)\n#define IDX_INVLD\t\t\tBIT(16)\n#define VTCR_FUNC_S\t\t\t12\n#define VTCR_FUNC_M\t\t\t0xf000\n#define VTCR_VID_S\t\t\t0\n#define VTCR_VID_M\t\t\t0xfff\n\n/* Values of VTCR_FUNC */\n#define VTCR_READ_VLAN_ENTRY\t\t0\n#define VTCR_WRITE_VLAN_ENTRY\t\t1\n#define VTCR_INVD_VLAN_ENTRY\t\t2\n#define VTCR_ENABLE_VLAN_ENTRY\t\t3\n#define VTCR_READ_ACL_ENTRY\t\t4\n#define VTCR_WRITE_ACL_ENTRY\t\t5\n#define VTCR_READ_TRTCM_TABLE\t\t6\n#define VTCR_WRITE_TRTCM_TABLE\t\t7\n#define VTCR_READ_ACL_MASK_ENTRY\t8\n#define VTCR_WRITE_ACL_MASK_ENTRY\t9\n#define VTCR_READ_ACL_RULE_ENTRY\t10\n#define VTCR_WRITE_ACL_RULE_ENTRY\t11\n#define VTCR_READ_ACL_RATE_ENTRY\t12\n#define VTCR_WRITE_ACL_RATE_ENTRY\t13\n\n/* VLAN entry fields */\n/* VAWD1 */\n#define PORT_STAG\t\t\tBIT(31)\n#define IVL_MAC\t\t\t\tBIT(30)\n#define EG_CON\t\t\t\tBIT(29)\n#define VTAG_EN\t\t\t\tBIT(28)\n#define COPY_PRI\t\t\tBIT(27)\n#define USER_PRI_S\t\t\t24\n#define USER_PRI_M\t\t\t0x7000000\n#define PORT_MEM_S\t\t\t16\n#define PORT_MEM_M\t\t\t0xff0000\n#define S_TAG1_S\t\t\t4\n#define S_TAG1_M\t\t\t0xfff0\n#define FID_S\t\t\t\t1\n#define FID_M\t\t\t\t0x0e\n#define VENTRY_VALID\t\t\tBIT(0)\n\n/* VAWD2 */\n#define S_TAG2_S\t\t\t16\n#define S_TAG2_M\t\t\t0xffff0000\n#define PORT_ETAG_S(p)\t\t\t((p) * 2)\n#define PORT_ETAG_M\t\t\t0x03\n\n#define PORT_CTRL_BASE\t\t\t0x2000\n#define PORT_CTRL_PORT_OFFSET\t\t0x100\n#define PORT_CTRL_REG(p, r)\t\t(PORT_CTRL_BASE + \\\n\t\t\t\t\t(p) * PORT_CTRL_PORT_OFFSET +  (r))\n#define CKGCR(p)\t\t\tPORT_CTRL_REG(p, 0x00)\n#define PCR(p)\t\t\t\tPORT_CTRL_REG(p, 0x04)\n#define PIC(p)\t\t\t\tPORT_CTRL_REG(p, 0x08)\n#define PSC(p)\t\t\t\tPORT_CTRL_REG(p, 0x0c)\n#define PVC(p)\t\t\t\tPORT_CTRL_REG(p, 0x10)\n#define PPBV1(p)\t\t\tPORT_CTRL_REG(p, 0x14)\n#define PPBV2(p)\t\t\tPORT_CTRL_REG(p, 0x18)\n#define BSR(p)\t\t\t\tPORT_CTRL_REG(p, 0x1c)\n#define STAG01\t\t\t\tPORT_CTRL_REG(p, 0x20)\n#define STAG23\t\t\t\tPORT_CTRL_REG(p, 0x24)\n#define STAG45\t\t\t\tPORT_CTRL_REG(p, 0x28)\n#define STAG67\t\t\t\tPORT_CTRL_REG(p, 0x2c)\n\n#define PPBV(p, g)\t\t\t(PPBV1(p) + ((g) / 2) * 4)\n\n/* Fields of PCR */\n#define MLDV2_EN\t\t\tBIT(30)\n#define EG_TAG_S\t\t\t28\n#define EG_TAG_M\t\t\t0x30000000\n#define PORT_PRI_S\t\t\t24\n#define PORT_PRI_M\t\t\t0x7000000\n#define PORT_MATRIX_S\t\t\t16\n#define PORT_MATRIX_M\t\t\t0xff0000\n#define UP2DSCP_EN\t\t\tBIT(12)\n#define UP2TAG_EN\t\t\tBIT(11)\n#define ACL_EN\t\t\t\tBIT(10)\n#define PORT_TX_MIR\t\t\tBIT(9)\n#define PORT_RX_MIR\t\t\tBIT(8)\n#define ACL_MIR\t\t\t\tBIT(7)\n#define MIS_PORT_FW_S\t\t\t4\n#define MIS_PORT_FW_M\t\t\t0x70\n#define VLAN_MIS\t\t\tBIT(2)\n#define PORT_VLAN_S\t\t\t0\n#define PORT_VLAN_M\t\t\t0x03\n\n/* Values of PORT_VLAN */\n#define PORT_MATRIX_MODE\t\t0\n#define FALLBACK_MODE\t\t\t1\n#define CHECK_MODE\t\t\t2\n#define SECURITY_MODE\t\t\t3\n\n/* Fields of PVC */\n#define STAG_VPID_S\t\t\t16\n#define STAG_VPID_M\t\t\t0xffff0000\n#define DIS_PVID\t\t\tBIT(15)\n#define FORCE_PVID\t\t\tBIT(14)\n#define PT_VPM\t\t\t\tBIT(12)\n#define PT_OPTION\t\t\tBIT(11)\n#define PVC_EG_TAG_S\t\t\t8\n#define PVC_EG_TAG_M\t\t\t0x700\n#define VLAN_ATTR_S\t\t\t6\n#define VLAN_ATTR_M\t\t\t0xc0\n#define PVC_PORT_STAG\t\t\tBIT(5)\n#define BC_LKYV_EN\t\t\tBIT(4)\n#define MC_LKYV_EN\t\t\tBIT(3)\n#define UC_LKYV_EN\t\t\tBIT(2)\n#define ACC_FRM_S\t\t\t0\n#define ACC_FRM_M\t\t\t0x03\n\n/* Values of VLAN_ATTR */\n#define VA_USER_PORT\t\t\t0\n#define VA_STACK_PORT\t\t\t1\n#define VA_TRANSLATION_PORT\t\t2\n#define VA_TRANSPARENT_PORT\t\t3\n\n/* Fields of PPBV */\n#define GRP_PORT_PRI_S(g)\t\t(((g) % 2) * 16 + 13)\n#define GRP_PORT_PRI_M\t\t\t0x07\n#define GRP_PORT_VID_S(g)\t\t(((g) % 2) * 16)\n#define GRP_PORT_VID_M\t\t\t0xfff\n\n#define PORT_MAC_CTRL_BASE\t\t0x3000\n#define PORT_MAC_CTRL_PORT_OFFSET\t0x100\n#define PORT_MAC_CTRL_REG(p, r)\t\t(PORT_MAC_CTRL_BASE + \\\n\t\t\t\t\t(p) * PORT_MAC_CTRL_PORT_OFFSET + (r))\n#define PMCR(p)\t\t\t\tPORT_MAC_CTRL_REG(p, 0x00)\n#define PMEEECR(p)\t\t\tPORT_MAC_CTRL_REG(p, 0x04)\n#define PMSR(p)\t\t\t\tPORT_MAC_CTRL_REG(p, 0x08)\n#define PINT_EN(p)\t\t\tPORT_MAC_CTRL_REG(p, 0x10)\n#define PINT_STS(p)\t\t\tPORT_MAC_CTRL_REG(p, 0x14)\n\n#define GMACCR\t\t\t\t(PORT_MAC_CTRL_BASE + 0xe0)\n#define TXCRC_EN\t\t\tBIT(19)\n#define RXCRC_EN\t\t\tBIT(18)\n#define PRMBL_LMT_EN\t\t\tBIT(17)\n#define MTCC_LMT_S\t\t\t9\n#define MTCC_LMT_M\t\t\t0x1e00\n#define MAX_RX_JUMBO_S\t\t\t2\n#define MAX_RX_JUMBO_M\t\t\t0x3c\n#define MAX_RX_PKT_LEN_S\t\t0\n#define MAX_RX_PKT_LEN_M\t\t0x3\n\n/* Values of MAX_RX_PKT_LEN */\n#define RX_PKT_LEN_1518\t\t\t0\n#define RX_PKT_LEN_1536\t\t\t1\n#define RX_PKT_LEN_1522\t\t\t2\n#define RX_PKT_LEN_MAX_JUMBO\t\t3\n\n/* Fields of PMCR */\n#define IPG_CFG_S\t\t\t18\n#define IPG_CFG_M\t\t\t0xc0000\n#define EXT_PHY\t\t\t\tBIT(17)\n#define MAC_MODE\t\t\tBIT(16)\n#define MAC_TX_EN\t\t\tBIT(14)\n#define MAC_RX_EN\t\t\tBIT(13)\n#define MAC_PRE\t\t\t\tBIT(11)\n#define BKOFF_EN\t\t\tBIT(9)\n#define BACKPR_EN\t\t\tBIT(8)\n#define FORCE_EEE1G\t\t\tBIT(7)\n#define FORCE_EEE1000\t\t\tBIT(6)\n#define FORCE_RX_FC\t\t\tBIT(5)\n#define FORCE_TX_FC\t\t\tBIT(4)\n#define FORCE_SPD_S\t\t\t2\n#define FORCE_SPD_M\t\t\t0x0c\n#define FORCE_DPX\t\t\tBIT(1)\n#define FORCE_LINK\t\t\tBIT(0)\n\n/* Fields of PMSR */\n#define EEE1G_STS\t\t\tBIT(7)\n#define EEE100_STS\t\t\tBIT(6)\n#define RX_FC_STS\t\t\tBIT(5)\n#define TX_FC_STS\t\t\tBIT(4)\n#define MAC_SPD_STS_S\t\t\t2\n#define MAC_SPD_STS_M\t\t\t0x0c\n#define MAC_DPX_STS\t\t\tBIT(1)\n#define MAC_LNK_STS\t\t\tBIT(0)\n\n/* Values of MAC_SPD_STS */\n#define MAC_SPD_10\t\t\t0\n#define MAC_SPD_100\t\t\t1\n#define MAC_SPD_1000\t\t\t2\n#define MAC_SPD_2500\t\t\t3\n\n/* Values of IPG_CFG */\n#define IPG_96BIT\t\t\t0\n#define IPG_96BIT_WITH_SHORT_IPG\t1\n#define IPG_64BIT\t\t\t2\n\n#define MIB_COUNTER_BASE\t\t0x4000\n#define MIB_COUNTER_PORT_OFFSET\t\t0x100\n#define MIB_COUNTER_REG(p, r)\t\t(MIB_COUNTER_BASE + \\\n\t\t\t\t\t(p) * MIB_COUNTER_PORT_OFFSET + (r))\n#define STATS_TDPC\t\t\t0x00\n#define STATS_TCRC\t\t\t0x04\n#define STATS_TUPC\t\t\t0x08\n#define STATS_TMPC\t\t\t0x0C\n#define STATS_TBPC\t\t\t0x10\n#define STATS_TCEC\t\t\t0x14\n#define STATS_TSCEC\t\t\t0x18\n#define STATS_TMCEC\t\t\t0x1C\n#define STATS_TDEC\t\t\t0x20\n#define STATS_TLCEC\t\t\t0x24\n#define STATS_TXCEC\t\t\t0x28\n#define STATS_TPPC\t\t\t0x2C\n#define STATS_TL64PC\t\t\t0x30\n#define STATS_TL65PC\t\t\t0x34\n#define STATS_TL128PC\t\t\t0x38\n#define STATS_TL256PC\t\t\t0x3C\n#define STATS_TL512PC\t\t\t0x40\n#define STATS_TL1024PC\t\t\t0x44\n#define STATS_TOC\t\t\t0x48\n#define STATS_RDPC\t\t\t0x60\n#define STATS_RFPC\t\t\t0x64\n#define STATS_RUPC\t\t\t0x68\n#define STATS_RMPC\t\t\t0x6C\n#define STATS_RBPC\t\t\t0x70\n#define STATS_RAEPC\t\t\t0x74\n#define STATS_RCEPC\t\t\t0x78\n#define STATS_RUSPC\t\t\t0x7C\n#define STATS_RFEPC\t\t\t0x80\n#define STATS_ROSPC\t\t\t0x84\n#define STATS_RJEPC\t\t\t0x88\n#define STATS_RPPC\t\t\t0x8C\n#define STATS_RL64PC\t\t\t0x90\n#define STATS_RL65PC\t\t\t0x94\n#define STATS_RL128PC\t\t\t0x98\n#define STATS_RL256PC\t\t\t0x9C\n#define STATS_RL512PC\t\t\t0xA0\n#define STATS_RL1024PC\t\t\t0xA4\n#define STATS_ROC\t\t\t0xA8\n#define STATS_RDPC_CTRL\t\t\t0xB0\n#define STATS_RDPC_ING\t\t\t0xB4\n#define STATS_RDPC_ARL\t\t\t0xB8\n\n#define SYS_CTRL\t\t\t0x7000\n#define SW_PHY_RST\t\t\tBIT(2)\n#define SW_SYS_RST\t\t\tBIT(1)\n#define SW_REG_RST\t\t\tBIT(0)\n\n#define SYS_INT_EN\t\t\t0x7008\n#define SYS_INT_STS\t\t\t0x700c\n#define MAC_PC_INT\t\t\tBIT(16)\n#define PHY_INT(p)\t\t\tBIT((p) + 8)\n#define PHY_LC_INT(p)\t\t\tBIT(p)\n\n#define PHY_IAC\t\t\t\t0x701c\n#define PHY_ACS_ST\t\t\tBIT(31)\n#define MDIO_REG_ADDR_S\t\t\t25\n#define MDIO_REG_ADDR_M\t\t\t0x3e000000\n#define MDIO_PHY_ADDR_S\t\t\t20\n#define MDIO_PHY_ADDR_M\t\t\t0x1f00000\n#define MDIO_CMD_S\t\t\t18\n#define MDIO_CMD_M\t\t\t0xc0000\n#define MDIO_ST_S\t\t\t16\n#define MDIO_ST_M\t\t\t0x30000\n#define MDIO_RW_DATA_S\t\t\t0\n#define MDIO_RW_DATA_M\t\t\t0xffff\n\n/* MDIO_CMD: MDIO commands */\n#define MDIO_CMD_ADDR\t\t\t0\n#define MDIO_CMD_WRITE\t\t\t1\n#define MDIO_CMD_READ\t\t\t2\n#define MDIO_CMD_READ_C45\t\t3\n\n/* MDIO_ST: MDIO start field */\n#define MDIO_ST_C45\t\t\t0\n#define MDIO_ST_C22\t\t\t1\n\n#define HWSTRAP\t\t\t\t0x7800\n#define MHWSTRAP\t\t\t0x7804\n\n#endif /* _MT753X_REGS_H_ */\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/mtk/mt753x/mt753x_swconfig.c",
    "content": "// SPDX-License-Identifier: GPL-2.0-only\n/*\n * Copyright (c) 2018 MediaTek Inc.\n * Author: Weijie Gao <weijie.gao@mediatek.com>\n */\n\n#include <linux/if.h>\n#include <linux/list.h>\n#include <linux/if_ether.h>\n#include <linux/skbuff.h>\n#include <linux/netdevice.h>\n#include <linux/netlink.h>\n#include <linux/bitops.h>\n#include <net/genetlink.h>\n#include <linux/delay.h>\n#include <linux/phy.h>\n#include <linux/netdevice.h>\n#include <linux/etherdevice.h>\n#include <linux/lockdep.h>\n#include <linux/workqueue.h>\n#include <linux/of_device.h>\n\n#include \"mt753x.h\"\n#include \"mt753x_swconfig.h\"\n#include \"mt753x_regs.h\"\n\n#define MT753X_PORT_MIB_TXB_ID\t18\t/* TxByte */\n#define MT753X_PORT_MIB_RXB_ID\t37\t/* RxByte */\n\n#define MIB_DESC(_s, _o, _n)   \\\n\t{                       \\\n\t\t.size = (_s),   \\\n\t\t.offset = (_o), \\\n\t\t.name = (_n),   \\\n\t}\n\nstruct mt753x_mib_desc {\n\tunsigned int size;\n\tunsigned int offset;\n\tconst char *name;\n};\n\nstatic const struct mt753x_mib_desc mt753x_mibs[] = {\n\tMIB_DESC(1, STATS_TDPC, \"TxDrop\"),\n\tMIB_DESC(1, STATS_TCRC, \"TxCRC\"),\n\tMIB_DESC(1, STATS_TUPC, \"TxUni\"),\n\tMIB_DESC(1, STATS_TMPC, \"TxMulti\"),\n\tMIB_DESC(1, STATS_TBPC, \"TxBroad\"),\n\tMIB_DESC(1, STATS_TCEC, \"TxCollision\"),\n\tMIB_DESC(1, STATS_TSCEC, \"TxSingleCol\"),\n\tMIB_DESC(1, STATS_TMCEC, \"TxMultiCol\"),\n\tMIB_DESC(1, STATS_TDEC, \"TxDefer\"),\n\tMIB_DESC(1, STATS_TLCEC, \"TxLateCol\"),\n\tMIB_DESC(1, STATS_TXCEC, \"TxExcCol\"),\n\tMIB_DESC(1, STATS_TPPC, \"TxPause\"),\n\tMIB_DESC(1, STATS_TL64PC, \"Tx64Byte\"),\n\tMIB_DESC(1, STATS_TL65PC, \"Tx65Byte\"),\n\tMIB_DESC(1, STATS_TL128PC, \"Tx128Byte\"),\n\tMIB_DESC(1, STATS_TL256PC, \"Tx256Byte\"),\n\tMIB_DESC(1, STATS_TL512PC, \"Tx512Byte\"),\n\tMIB_DESC(1, STATS_TL1024PC, \"Tx1024Byte\"),\n\tMIB_DESC(2, STATS_TOC, \"TxByte\"),\n\tMIB_DESC(1, STATS_RDPC, \"RxDrop\"),\n\tMIB_DESC(1, STATS_RFPC, \"RxFiltered\"),\n\tMIB_DESC(1, STATS_RUPC, \"RxUni\"),\n\tMIB_DESC(1, STATS_RMPC, \"RxMulti\"),\n\tMIB_DESC(1, STATS_RBPC, \"RxBroad\"),\n\tMIB_DESC(1, STATS_RAEPC, \"RxAlignErr\"),\n\tMIB_DESC(1, STATS_RCEPC, \"RxCRC\"),\n\tMIB_DESC(1, STATS_RUSPC, \"RxUnderSize\"),\n\tMIB_DESC(1, STATS_RFEPC, \"RxFragment\"),\n\tMIB_DESC(1, STATS_ROSPC, \"RxOverSize\"),\n\tMIB_DESC(1, STATS_RJEPC, \"RxJabber\"),\n\tMIB_DESC(1, STATS_RPPC, \"RxPause\"),\n\tMIB_DESC(1, STATS_RL64PC, \"Rx64Byte\"),\n\tMIB_DESC(1, STATS_RL65PC, \"Rx65Byte\"),\n\tMIB_DESC(1, STATS_RL128PC, \"Rx128Byte\"),\n\tMIB_DESC(1, STATS_RL256PC, \"Rx256Byte\"),\n\tMIB_DESC(1, STATS_RL512PC, \"Rx512Byte\"),\n\tMIB_DESC(1, STATS_RL1024PC, \"Rx1024Byte\"),\n\tMIB_DESC(2, STATS_ROC, \"RxByte\"),\n\tMIB_DESC(1, STATS_RDPC_CTRL, \"RxCtrlDrop\"),\n\tMIB_DESC(1, STATS_RDPC_ING, \"RxIngDrop\"),\n\tMIB_DESC(1, STATS_RDPC_ARL, \"RxARLDrop\")\n};\n\nenum {\n\t/* Global attributes. */\n\tMT753X_ATTR_ENABLE_VLAN,\n};\n\nstatic int mt753x_get_vlan_enable(struct switch_dev *dev,\n\t\t\t\t  const struct switch_attr *attr,\n\t\t\t\t  struct switch_val *val)\n{\n\tstruct gsw_mt753x *gsw = container_of(dev, struct gsw_mt753x, swdev);\n\n\tval->value.i = gsw->global_vlan_enable;\n\n\treturn 0;\n}\n\nstatic int mt753x_set_vlan_enable(struct switch_dev *dev,\n\t\t\t\t  const struct switch_attr *attr,\n\t\t\t\t  struct switch_val *val)\n{\n\tstruct gsw_mt753x *gsw = container_of(dev, struct gsw_mt753x, swdev);\n\n\tgsw->global_vlan_enable = val->value.i != 0;\n\n\treturn 0;\n}\n\nstatic int mt753x_get_port_pvid(struct switch_dev *dev, int port, int *val)\n{\n\tstruct gsw_mt753x *gsw = container_of(dev, struct gsw_mt753x, swdev);\n\n\tif (port >= MT753X_NUM_PORTS)\n\t\treturn -EINVAL;\n\n\t*val = mt753x_reg_read(gsw, PPBV1(port));\n\t*val &= GRP_PORT_VID_M;\n\n\treturn 0;\n}\n\nstatic int mt753x_set_port_pvid(struct switch_dev *dev, int port, int pvid)\n{\n\tstruct gsw_mt753x *gsw = container_of(dev, struct gsw_mt753x, swdev);\n\n\tif (port >= MT753X_NUM_PORTS)\n\t\treturn -EINVAL;\n\n\tif (pvid < MT753X_MIN_VID || pvid > MT753X_MAX_VID)\n\t\treturn -EINVAL;\n\n\tgsw->port_entries[port].pvid = pvid;\n\n\treturn 0;\n}\n\nstatic int mt753x_get_vlan_ports(struct switch_dev *dev, struct switch_val *val)\n{\n\tstruct gsw_mt753x *gsw = container_of(dev, struct gsw_mt753x, swdev);\n\tu32 member;\n\tu32 etags;\n\tint i;\n\n\tval->len = 0;\n\n\tif (val->port_vlan < 0 || val->port_vlan >= MT753X_NUM_VLANS)\n\t\treturn -EINVAL;\n\n\tmt753x_vlan_ctrl(gsw, VTCR_READ_VLAN_ENTRY, val->port_vlan);\n\n\tmember = mt753x_reg_read(gsw, VAWD1);\n\tmember &= PORT_MEM_M;\n\tmember >>= PORT_MEM_S;\n\n\tetags = mt753x_reg_read(gsw, VAWD2);\n\n\tfor (i = 0; i < MT753X_NUM_PORTS; i++) {\n\t\tstruct switch_port *p;\n\t\tint etag;\n\n\t\tif (!(member & BIT(i)))\n\t\t\tcontinue;\n\n\t\tp = &val->value.ports[val->len++];\n\t\tp->id = i;\n\n\t\tetag = (etags >> PORT_ETAG_S(i)) & PORT_ETAG_M;\n\n\t\tif (etag == ETAG_CTRL_TAG)\n\t\t\tp->flags |= BIT(SWITCH_PORT_FLAG_TAGGED);\n\t\telse if (etag != ETAG_CTRL_UNTAG)\n\t\t\tdev_info(gsw->dev,\n\t\t\t\t \"vlan egress tag control neither untag nor tag.\\n\");\n\t}\n\n\treturn 0;\n}\n\nstatic int mt753x_set_vlan_ports(struct switch_dev *dev, struct switch_val *val)\n{\n\tstruct gsw_mt753x *gsw = container_of(dev, struct gsw_mt753x, swdev);\n\tu8 member = 0;\n\tu8 etags = 0;\n\tint i;\n\n\tif (val->port_vlan < 0 || val->port_vlan >= MT753X_NUM_VLANS ||\n\t    val->len > MT753X_NUM_PORTS)\n\t\treturn -EINVAL;\n\n\tfor (i = 0; i < val->len; i++) {\n\t\tstruct switch_port *p = &val->value.ports[i];\n\n\t\tif (p->id >= MT753X_NUM_PORTS)\n\t\t\treturn -EINVAL;\n\n\t\tmember |= BIT(p->id);\n\n\t\tif (p->flags & BIT(SWITCH_PORT_FLAG_TAGGED))\n\t\t\tetags |= BIT(p->id);\n\t}\n\n\tgsw->vlan_entries[val->port_vlan].member = member;\n\tgsw->vlan_entries[val->port_vlan].etags = etags;\n\n\treturn 0;\n}\n\nstatic int mt753x_set_vid(struct switch_dev *dev,\n\t\t\t  const struct switch_attr *attr,\n\t\t\t  struct switch_val *val)\n{\n\tstruct gsw_mt753x *gsw = container_of(dev, struct gsw_mt753x, swdev);\n\tint vlan;\n\tu16 vid;\n\n\tvlan = val->port_vlan;\n\tvid = (u16)val->value.i;\n\n\tif (vlan < 0 || vlan >= MT753X_NUM_VLANS)\n\t\treturn -EINVAL;\n\n\tif (vid < MT753X_MIN_VID || vid > MT753X_MAX_VID)\n\t\treturn -EINVAL;\n\n\tgsw->vlan_entries[vlan].vid = vid;\n\treturn 0;\n}\n\nstatic int mt753x_get_vid(struct switch_dev *dev,\n\t\t\t  const struct switch_attr *attr,\n\t\t\t  struct switch_val *val)\n{\n\tval->value.i = val->port_vlan;\n\treturn 0;\n}\n\nstatic int mt753x_get_port_link(struct switch_dev *dev, int port,\n\t\t\t\tstruct switch_port_link *link)\n{\n\tstruct gsw_mt753x *gsw = container_of(dev, struct gsw_mt753x, swdev);\n\tu32 speed, pmsr;\n\n\tif (port < 0 || port >= MT753X_NUM_PORTS)\n\t\treturn -EINVAL;\n\n\tpmsr = mt753x_reg_read(gsw, PMSR(port));\n\n\tlink->link = pmsr & MAC_LNK_STS;\n\tlink->duplex = pmsr & MAC_DPX_STS;\n\tspeed = (pmsr & MAC_SPD_STS_M) >> MAC_SPD_STS_S;\n\n\tswitch (speed) {\n\tcase MAC_SPD_10:\n\t\tlink->speed = SWITCH_PORT_SPEED_10;\n\t\tbreak;\n\tcase MAC_SPD_100:\n\t\tlink->speed = SWITCH_PORT_SPEED_100;\n\t\tbreak;\n\tcase MAC_SPD_1000:\n\t\tlink->speed = SWITCH_PORT_SPEED_1000;\n\t\tbreak;\n\tcase MAC_SPD_2500:\n\t\t/* TODO: swconfig has no support for 2500 now */\n\t\tlink->speed = SWITCH_PORT_SPEED_UNKNOWN;\n\t\tbreak;\n\t}\n\n\treturn 0;\n}\n\nstatic int mt753x_set_port_link(struct switch_dev *dev, int port,\n\t\t\t\tstruct switch_port_link *link)\n{\n#ifndef MODULE\n\tif (port >= MT753X_NUM_PHYS)\n\t\treturn -EINVAL;\n\n\treturn switch_generic_set_link(dev, port, link);\n#else\n\treturn -ENOTSUPP;\n#endif\n}\n\nstatic u64 get_mib_counter(struct gsw_mt753x *gsw, int i, int port)\n{\n\tunsigned int offset;\n\tu64 lo, hi, hi2;\n\n\toffset = mt753x_mibs[i].offset;\n\n\tif (mt753x_mibs[i].size == 1)\n\t\treturn mt753x_reg_read(gsw, MIB_COUNTER_REG(port, offset));\n\n\tdo {\n\t\thi = mt753x_reg_read(gsw, MIB_COUNTER_REG(port, offset + 4));\n\t\tlo = mt753x_reg_read(gsw, MIB_COUNTER_REG(port, offset));\n\t\thi2 = mt753x_reg_read(gsw, MIB_COUNTER_REG(port, offset + 4));\n\t} while (hi2 != hi);\n\n\treturn (hi << 32) | lo;\n}\n\nstatic int mt753x_get_port_mib(struct switch_dev *dev,\n\t\t\t       const struct switch_attr *attr,\n\t\t\t       struct switch_val *val)\n{\n\tstatic char buf[4096];\n\tstruct gsw_mt753x *gsw = container_of(dev, struct gsw_mt753x, swdev);\n\tint i, len = 0;\n\n\tif (val->port_vlan >= MT753X_NUM_PORTS)\n\t\treturn -EINVAL;\n\n\tlen += snprintf(buf + len, sizeof(buf) - len,\n\t\t\t\"Port %d MIB counters\\n\", val->port_vlan);\n\n\tfor (i = 0; i < ARRAY_SIZE(mt753x_mibs); ++i) {\n\t\tu64 counter;\n\n\t\tlen += snprintf(buf + len, sizeof(buf) - len,\n\t\t\t\t\"%-11s: \", mt753x_mibs[i].name);\n\t\tcounter = get_mib_counter(gsw, i, val->port_vlan);\n\t\tlen += snprintf(buf + len, sizeof(buf) - len, \"%llu\\n\",\n\t\t\t\tcounter);\n\t}\n\n\tval->value.s = buf;\n\tval->len = len;\n\treturn 0;\n}\n\nstatic int mt753x_get_port_stats(struct switch_dev *dev, int port,\n\t\t\t\t struct switch_port_stats *stats)\n{\n\tstruct gsw_mt753x *gsw = container_of(dev, struct gsw_mt753x, swdev);\n\n\tif (port < 0 || port >= MT753X_NUM_PORTS)\n\t\treturn -EINVAL;\n\n\tstats->tx_bytes = get_mib_counter(gsw, MT753X_PORT_MIB_TXB_ID, port);\n\tstats->rx_bytes = get_mib_counter(gsw, MT753X_PORT_MIB_RXB_ID, port);\n\n\treturn 0;\n}\n\nstatic void mt753x_port_isolation(struct gsw_mt753x *gsw)\n{\n\tint i;\n\n\tfor (i = 0; i < MT753X_NUM_PORTS; i++)\n\t\tmt753x_reg_write(gsw, PCR(i),\n\t\t\t\t BIT(gsw->cpu_port) << PORT_MATRIX_S);\n\n\tmt753x_reg_write(gsw, PCR(gsw->cpu_port), PORT_MATRIX_M);\n\n\tfor (i = 0; i < MT753X_NUM_PORTS; i++)\n\t\tmt753x_reg_write(gsw, PVC(i),\n\t\t\t\t (0x8100 << STAG_VPID_S) |\n\t\t\t\t (VA_TRANSPARENT_PORT << VLAN_ATTR_S));\n}\n\nstatic int mt753x_apply_config(struct switch_dev *dev)\n{\n\tstruct gsw_mt753x *gsw = container_of(dev, struct gsw_mt753x, swdev);\n\n\tif (!gsw->global_vlan_enable) {\n\t\tmt753x_port_isolation(gsw);\n\t\treturn 0;\n\t}\n\n\tmt753x_apply_vlan_config(gsw);\n\n\treturn 0;\n}\n\nstatic int mt753x_reset_switch(struct switch_dev *dev)\n{\n\tstruct gsw_mt753x *gsw = container_of(dev, struct gsw_mt753x, swdev);\n\tint i;\n\n\tmemset(gsw->port_entries, 0, sizeof(gsw->port_entries));\n\tmemset(gsw->vlan_entries, 0, sizeof(gsw->vlan_entries));\n\n\t/* set default vid of each vlan to the same number of vlan, so the vid\n\t * won't need be set explicitly.\n\t */\n\tfor (i = 0; i < MT753X_NUM_VLANS; i++)\n\t\tgsw->vlan_entries[i].vid = i;\n\n\treturn 0;\n}\n\nstatic int mt753x_phy_read16(struct switch_dev *dev, int addr, u8 reg,\n\t\t\t     u16 *value)\n{\n\tstruct gsw_mt753x *gsw = container_of(dev, struct gsw_mt753x, swdev);\n\n\t*value = gsw->mii_read(gsw, addr, reg);\n\n\treturn 0;\n}\n\nstatic int mt753x_phy_write16(struct switch_dev *dev, int addr, u8 reg,\n\t\t\t      u16 value)\n{\n\tstruct gsw_mt753x *gsw = container_of(dev, struct gsw_mt753x, swdev);\n\n\tgsw->mii_write(gsw, addr, reg, value);\n\n\treturn 0;\n}\n\nstatic const struct switch_attr mt753x_global[] = {\n\t{\n\t\t.type = SWITCH_TYPE_INT,\n\t\t.name = \"enable_vlan\",\n\t\t.description = \"VLAN mode (1:enabled)\",\n\t\t.max = 1,\n\t\t.id = MT753X_ATTR_ENABLE_VLAN,\n\t\t.get = mt753x_get_vlan_enable,\n\t\t.set = mt753x_set_vlan_enable,\n\t}\n};\n\nstatic const struct switch_attr mt753x_port[] = {\n\t{\n\t\t.type = SWITCH_TYPE_STRING,\n\t\t.name = \"mib\",\n\t\t.description = \"Get MIB counters for port\",\n\t\t.get = mt753x_get_port_mib,\n\t\t.set = NULL,\n\t},\n};\n\nstatic const struct switch_attr mt753x_vlan[] = {\n\t{\n\t\t.type = SWITCH_TYPE_INT,\n\t\t.name = \"vid\",\n\t\t.description = \"VLAN ID (0-4094)\",\n\t\t.set = mt753x_set_vid,\n\t\t.get = mt753x_get_vid,\n\t\t.max = 4094,\n\t},\n};\n\nstatic const struct switch_dev_ops mt753x_swdev_ops = {\n\t.attr_global = {\n\t\t.attr = mt753x_global,\n\t\t.n_attr = ARRAY_SIZE(mt753x_global),\n\t},\n\t.attr_port = {\n\t\t.attr = mt753x_port,\n\t\t.n_attr = ARRAY_SIZE(mt753x_port),\n\t},\n\t.attr_vlan = {\n\t\t.attr = mt753x_vlan,\n\t\t.n_attr = ARRAY_SIZE(mt753x_vlan),\n\t},\n\t.get_vlan_ports = mt753x_get_vlan_ports,\n\t.set_vlan_ports = mt753x_set_vlan_ports,\n\t.get_port_pvid = mt753x_get_port_pvid,\n\t.set_port_pvid = mt753x_set_port_pvid,\n\t.get_port_link = mt753x_get_port_link,\n\t.set_port_link = mt753x_set_port_link,\n\t.get_port_stats = mt753x_get_port_stats,\n\t.apply_config = mt753x_apply_config,\n\t.reset_switch = mt753x_reset_switch,\n\t.phy_read16 = mt753x_phy_read16,\n\t.phy_write16 = mt753x_phy_write16,\n};\n\nint mt753x_swconfig_init(struct gsw_mt753x *gsw)\n{\n\tstruct device_node *np = gsw->dev->of_node;\n\tstruct switch_dev *swdev;\n\tint ret;\n\n\tif (of_property_read_u32(np, \"mediatek,cpuport\", &gsw->cpu_port))\n\t\tgsw->cpu_port = MT753X_DFL_CPU_PORT;\n\n\tswdev = &gsw->swdev;\n\n\tswdev->name = gsw->name;\n\tswdev->alias = gsw->name;\n\tswdev->cpu_port = gsw->cpu_port;\n\tswdev->ports = MT753X_NUM_PORTS;\n\tswdev->vlans = MT753X_NUM_VLANS;\n\tswdev->ops = &mt753x_swdev_ops;\n\n\tret = register_switch(swdev, NULL);\n\tif (ret) {\n\t\tdev_notice(gsw->dev, \"Failed to register switch %s\\n\",\n\t\t\t   swdev->name);\n\t\treturn ret;\n\t}\n\n\tmt753x_apply_config(swdev);\n\n\treturn 0;\n}\n\nvoid mt753x_swconfig_destroy(struct gsw_mt753x *gsw)\n{\n\tunregister_switch(&gsw->swdev);\n}\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/mtk/mt753x/mt753x_swconfig.h",
    "content": "/* SPDX-License-Identifier: GPL-2.0-only */\n/*\n * Copyright (c) 2018 MediaTek Inc.\n * Author: Weijie Gao <weijie.gao@mediatek.com>\n */\n\n#ifndef _MT753X_SWCONFIG_H_\n#define _MT753X_SWCONFIG_H_\n\n#ifdef CONFIG_SWCONFIG\n#include <linux/switch.h>\n#include \"mt753x.h\"\n\nint mt753x_swconfig_init(struct gsw_mt753x *gsw);\nvoid mt753x_swconfig_destroy(struct gsw_mt753x *gsw);\n#else\nstatic inline int mt753x_swconfig_init(struct gsw_mt753x *gsw)\n{\n\tmt753x_apply_vlan_config(gsw);\n\n\treturn 0;\n}\n\nstatic inline void mt753x_swconfig_destroy(struct gsw_mt753x *gsw)\n{\n}\n#endif\n\n#endif /* _MT753X_SWCONFIG_H_ */\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/mtk/mt753x/mt753x_vlan.c",
    "content": "// SPDX-License-Identifier: GPL-2.0-only\n/*\n * Copyright (c) 2018 MediaTek Inc.\n */\n\n#include \"mt753x.h\"\n#include \"mt753x_regs.h\"\n\nstruct mt753x_mapping mt753x_def_mapping[] = {\n\t{\n\t\t.name = \"llllw\",\n\t\t.pvids = { 1, 1, 1, 1, 2, 2, 1 },\n\t\t.members = { 0, 0x4f, 0x30 },\n\t\t.etags = { 0, 0, 0 },\n\t\t.vids = { 0, 1, 2 },\n\t}, {\n\t\t.name = \"wllll\",\n\t\t.pvids = { 2, 1, 1, 1, 1, 2, 1 },\n\t\t.members = { 0, 0x5e, 0x21 },\n\t\t.etags = { 0, 0, 0 },\n\t\t.vids = { 0, 1, 2 },\n\t}, {\n\t\t.name = \"lwlll\",\n\t\t.pvids = { 1, 2, 1, 1, 1, 2, 1 },\n\t\t.members = { 0, 0x5d, 0x22 },\n\t\t.etags = { 0, 0, 0 },\n\t\t.vids = { 0, 1, 2 },\n\t},\n};\n\nvoid mt753x_vlan_ctrl(struct gsw_mt753x *gsw, u32 cmd, u32 val)\n{\n\tint i;\n\n\tmt753x_reg_write(gsw, VTCR,\n\t\t\t VTCR_BUSY | ((cmd << VTCR_FUNC_S) & VTCR_FUNC_M) |\n\t\t\t (val & VTCR_VID_M));\n\n\tfor (i = 0; i < 300; i++) {\n\t\tu32 val = mt753x_reg_read(gsw, VTCR);\n\n\t\tif ((val & VTCR_BUSY) == 0)\n\t\t\tbreak;\n\n\t\tusleep_range(1000, 1100);\n\t}\n\n\tif (i == 300)\n\t\tdev_info(gsw->dev, \"vtcr timeout\\n\");\n}\n\nstatic void mt753x_write_vlan_entry(struct gsw_mt753x *gsw, int vlan, u16 vid,\n\t\t\t\t    u8 ports, u8 etags)\n{\n\tint port;\n\tu32 val;\n\n\t/* vlan port membership */\n\tif (ports)\n\t\tmt753x_reg_write(gsw, VAWD1,\n\t\t\t\t IVL_MAC | VTAG_EN | VENTRY_VALID |\n\t\t\t\t ((ports << PORT_MEM_S) & PORT_MEM_M));\n\telse\n\t\tmt753x_reg_write(gsw, VAWD1, 0);\n\n\t/* egress mode */\n\tval = 0;\n\tfor (port = 0; port < MT753X_NUM_PORTS; port++) {\n\t\tif (etags & BIT(port))\n\t\t\tval |= ETAG_CTRL_TAG << PORT_ETAG_S(port);\n\t\telse\n\t\t\tval |= ETAG_CTRL_UNTAG << PORT_ETAG_S(port);\n\t}\n\tmt753x_reg_write(gsw, VAWD2, val);\n\n\t/* write to vlan table */\n\tmt753x_vlan_ctrl(gsw, VTCR_WRITE_VLAN_ENTRY, vid);\n}\n\nvoid mt753x_apply_vlan_config(struct gsw_mt753x *gsw)\n{\n\tint i, j;\n\tu8 tag_ports;\n\tu8 untag_ports;\n\n\t/* set all ports as security mode */\n\tfor (i = 0; i < MT753X_NUM_PORTS; i++)\n\t\tmt753x_reg_write(gsw, PCR(i),\n\t\t\t\t PORT_MATRIX_M | SECURITY_MODE);\n\n\t/* check if a port is used in tag/untag vlan egress mode */\n\ttag_ports = 0;\n\tuntag_ports = 0;\n\n\tfor (i = 0; i < MT753X_NUM_VLANS; i++) {\n\t\tu8 member = gsw->vlan_entries[i].member;\n\t\tu8 etags = gsw->vlan_entries[i].etags;\n\n\t\tif (!member)\n\t\t\tcontinue;\n\n\t\tfor (j = 0; j < MT753X_NUM_PORTS; j++) {\n\t\t\tif (!(member & BIT(j)))\n\t\t\t\tcontinue;\n\n\t\t\tif (etags & BIT(j))\n\t\t\t\ttag_ports |= 1u << j;\n\t\t\telse\n\t\t\t\tuntag_ports |= 1u << j;\n\t\t}\n\t}\n\n\t/* set all untag-only ports as transparent and the rest as user port */\n\tfor (i = 0; i < MT753X_NUM_PORTS; i++) {\n\t\tu32 pvc_mode = 0x8100 << STAG_VPID_S;\n\n\t\tif (untag_ports & BIT(i) && !(tag_ports & BIT(i)))\n\t\t\tpvc_mode = (0x8100 << STAG_VPID_S) |\n\t\t\t\t(VA_TRANSPARENT_PORT << VLAN_ATTR_S);\n\n\t\tmt753x_reg_write(gsw, PVC(i), pvc_mode);\n\t}\n\n\t/* first clear the switch vlan table */\n\tfor (i = 0; i < MT753X_NUM_VLANS; i++)\n\t\tmt753x_write_vlan_entry(gsw, i, i, 0, 0);\n\n\t/* now program only vlans with members to avoid\n\t * clobbering remapped entries in later iterations\n\t */\n\tfor (i = 0; i < MT753X_NUM_VLANS; i++) {\n\t\tu16 vid = gsw->vlan_entries[i].vid;\n\t\tu8 member = gsw->vlan_entries[i].member;\n\t\tu8 etags = gsw->vlan_entries[i].etags;\n\n\t\tif (member)\n\t\t\tmt753x_write_vlan_entry(gsw, i, vid, member, etags);\n\t}\n\n\t/* Port Default PVID */\n\tfor (i = 0; i < MT753X_NUM_PORTS; i++) {\n\t\tint vlan = gsw->port_entries[i].pvid;\n\t\tu16 pvid = 0;\n\t\tu32 val;\n\n\t\tif (vlan < MT753X_NUM_VLANS && gsw->vlan_entries[vlan].member)\n\t\t\tpvid = gsw->vlan_entries[vlan].vid;\n\n\t\tval = mt753x_reg_read(gsw, PPBV1(i));\n\t\tval &= ~GRP_PORT_VID_M;\n\t\tval |= pvid;\n\t\tmt753x_reg_write(gsw, PPBV1(i), val);\n\t}\n}\n\nstruct mt753x_mapping *mt753x_find_mapping(struct device_node *np)\n{\n\tconst char *map;\n\tint i;\n\n\tif (of_property_read_string(np, \"mediatek,portmap\", &map))\n\t\treturn NULL;\n\n\tfor (i = 0; i < ARRAY_SIZE(mt753x_def_mapping); i++)\n\t\tif (!strcmp(map, mt753x_def_mapping[i].name))\n\t\t\treturn &mt753x_def_mapping[i];\n\n\treturn NULL;\n}\n\nvoid mt753x_apply_mapping(struct gsw_mt753x *gsw, struct mt753x_mapping *map)\n{\n\tint i = 0;\n\n\tfor (i = 0; i < MT753X_NUM_PORTS; i++)\n\t\tgsw->port_entries[i].pvid = map->pvids[i];\n\n\tfor (i = 0; i < MT753X_NUM_VLANS; i++) {\n\t\tgsw->vlan_entries[i].member = map->members[i];\n\t\tgsw->vlan_entries[i].etags = map->etags[i];\n\t\tgsw->vlan_entries[i].vid = map->vids[i];\n\t}\n}\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/mtk/mt753x/mt753x_vlan.h",
    "content": "/* SPDX-License-Identifier: GPL-2.0-only */\n/*\n * Copyright (c) 2018 MediaTek Inc.\n */\n\n#ifndef _MT753X_VLAN_H_\n#define _MT753X_VLAN_H_\n\n#define MT753X_NUM_PORTS\t7\n#define MT753X_NUM_VLANS\t4095\n#define MT753X_MAX_VID\t\t4095\n#define MT753X_MIN_VID\t\t0\n\nstruct gsw_mt753x;\n\nstruct mt753x_port_entry {\n\tu16\tpvid;\n};\n\nstruct mt753x_vlan_entry {\n\tu16\tvid;\n\tu8\tmember;\n\tu8\tetags;\n};\n\nstruct mt753x_mapping {\n\tchar\t*name;\n\tu16\tpvids[MT753X_NUM_PORTS];\n\tu8\tmembers[MT753X_NUM_VLANS];\n\tu8\tetags[MT753X_NUM_VLANS];\n\tu16\tvids[MT753X_NUM_VLANS];\n};\n\nextern struct mt753x_mapping mt753x_defaults[];\n\nvoid mt753x_vlan_ctrl(struct gsw_mt753x *gsw, u32 cmd, u32 val);\nvoid mt753x_apply_vlan_config(struct gsw_mt753x *gsw);\nstruct mt753x_mapping *mt753x_find_mapping(struct device_node *np);\nvoid mt753x_apply_mapping(struct gsw_mt753x *gsw, struct mt753x_mapping *map);\n#endif /* _MT753X_VLAN_H_ */\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/Makefile",
    "content": "obj-$(CONFIG_RTL8367S_GSW) += rtl8367s_gsw.o\nrtl8367s_gsw-objs := rtl8367s_mdio.o rtl8367s_dbg.o\nifeq ($(CONFIG_SWCONFIG),y)\nrtl8367s_gsw-objs += rtl8367s.o\nendif\nrtl8367s_gsw-objs += rtl8367c/acl.o\nrtl8367s_gsw-objs += rtl8367c/cpu.o\nrtl8367s_gsw-objs += rtl8367c/dot1x.o\nrtl8367s_gsw-objs += rtl8367c/eee.o\nrtl8367s_gsw-objs += rtl8367c/igmp.o\nrtl8367s_gsw-objs += rtl8367c/interrupt.o\nrtl8367s_gsw-objs += rtl8367c/l2.o\nrtl8367s_gsw-objs += rtl8367c/leaky.o\nrtl8367s_gsw-objs += rtl8367c/led.o\nrtl8367s_gsw-objs += rtl8367c/mirror.o\nrtl8367s_gsw-objs += rtl8367c/oam.o\nrtl8367s_gsw-objs += rtl8367c/port.o\nrtl8367s_gsw-objs += rtl8367c/ptp.o\nrtl8367s_gsw-objs += rtl8367c/qos.o\nrtl8367s_gsw-objs += rtl8367c/rate.o\nrtl8367s_gsw-objs += rtl8367c/rldp.o\nrtl8367s_gsw-objs += rtl8367c/rtk_switch.o\nrtl8367s_gsw-objs += rtl8367c/rtl8367c_asicdrv_acl.o\nrtl8367s_gsw-objs += rtl8367c/rtl8367c_asicdrv.o\nrtl8367s_gsw-objs += rtl8367c/rtl8367c_asicdrv_cputag.o\nrtl8367s_gsw-objs += rtl8367c/rtl8367c_asicdrv_dot1x.o\nrtl8367s_gsw-objs += rtl8367c/rtl8367c_asicdrv_eav.o\nrtl8367s_gsw-objs += rtl8367c/rtl8367c_asicdrv_eee.o\nrtl8367s_gsw-objs += rtl8367c/rtl8367c_asicdrv_fc.o\nrtl8367s_gsw-objs += rtl8367c/rtl8367c_asicdrv_green.o\nrtl8367s_gsw-objs += rtl8367c/rtl8367c_asicdrv_hsb.o\nrtl8367s_gsw-objs += rtl8367c/rtl8367c_asicdrv_igmp.o\nrtl8367s_gsw-objs += rtl8367c/rtl8367c_asicdrv_inbwctrl.o\nrtl8367s_gsw-objs += rtl8367c/rtl8367c_asicdrv_interrupt.o\nrtl8367s_gsw-objs += rtl8367c/rtl8367c_asicdrv_led.o\nrtl8367s_gsw-objs += rtl8367c/rtl8367c_asicdrv_lut.o\nrtl8367s_gsw-objs += rtl8367c/rtl8367c_asicdrv_meter.o\nrtl8367s_gsw-objs += rtl8367c/rtl8367c_asicdrv_mib.o\nrtl8367s_gsw-objs += rtl8367c/rtl8367c_asicdrv_mirror.o\nrtl8367s_gsw-objs += rtl8367c/rtl8367c_asicdrv_misc.o\nrtl8367s_gsw-objs += rtl8367c/rtl8367c_asicdrv_oam.o\nrtl8367s_gsw-objs += rtl8367c/rtl8367c_asicdrv_phy.o\nrtl8367s_gsw-objs += rtl8367c/rtl8367c_asicdrv_port.o\nrtl8367s_gsw-objs += rtl8367c/rtl8367c_asicdrv_portIsolation.o\nrtl8367s_gsw-objs += rtl8367c/rtl8367c_asicdrv_qos.o\nrtl8367s_gsw-objs += rtl8367c/rtl8367c_asicdrv_rldp.o\nrtl8367s_gsw-objs += rtl8367c/rtl8367c_asicdrv_rma.o\nrtl8367s_gsw-objs += rtl8367c/rtl8367c_asicdrv_scheduling.o\nrtl8367s_gsw-objs += rtl8367c/rtl8367c_asicdrv_storm.o\nrtl8367s_gsw-objs += rtl8367c/rtl8367c_asicdrv_svlan.o\nrtl8367s_gsw-objs += rtl8367c/rtl8367c_asicdrv_trunking.o\nrtl8367s_gsw-objs += rtl8367c/rtl8367c_asicdrv_unknownMulticast.o\nrtl8367s_gsw-objs += rtl8367c/rtl8367c_asicdrv_vlan.o\nrtl8367s_gsw-objs += rtl8367c/smi.o\nrtl8367s_gsw-objs += rtl8367c/stat.o\nrtl8367s_gsw-objs += rtl8367c/storm.o\nrtl8367s_gsw-objs += rtl8367c/svlan.o\nrtl8367s_gsw-objs += rtl8367c/trap.o\nrtl8367s_gsw-objs += rtl8367c/trunk.o\nrtl8367s_gsw-objs += rtl8367c/vlan.o\n\nccflags-y += -Werror -D_LITTLE_ENDIAN -DMDC_MDIO_OPERATION\n\nccflags-y += -Idrivers/net/phy/rtk/rtl8367c/include\nccflags-y += -Iinclude/linux/\n\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/modules.builtin",
    "content": "kernel/drivers/net/phy/rtk/rtl8367s_gsw.ko\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/acl.c",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * $Revision: 76306 $\n * $Date: 2017-03-08 15:13:58 +0800 (週三, 08 三月 2017) $\n *\n * Purpose : RTK switch high-level API for RTL8367/RTL8367C\n * Feature : Here is a list of all functions and variables in ACL module.\n *\n */\n\n#include <rtk_switch.h>\n#include <rtk_error.h>\n#include <acl.h>\n#include <vlan.h>\n#include <svlan.h>\n#include <rate.h>\n#include <string.h>\n\n#include <rtl8367c_asicdrv.h>\n#include <rtl8367c_asicdrv_acl.h>\n#include <rtl8367c_asicdrv_hsb.h>\n#include <rtl8367c_asicdrv_vlan.h>\n#include <rtl8367c_asicdrv_svlan.h>\n#include <rtl8367c_asicdrv_cputag.h>\n#include <rtl8367c_asicdrv_mib.h>\n\nCONST_T rtk_uint8 filter_templateField[RTL8367C_ACLTEMPLATENO][RTL8367C_ACLRULEFIELDNO] = {\n    {ACL_DMAC0,             ACL_DMAC1,          ACL_DMAC2,          ACL_SMAC0,          ACL_SMAC1,          ACL_SMAC2,          ACL_ETHERTYPE,      ACL_FIELD_SELECT15},\n    {ACL_IP4SIP0,           ACL_IP4SIP1,        ACL_IP4DIP0,        ACL_IP4DIP1,        ACL_FIELD_SELECT13, ACL_FIELD_SELECT14, ACL_FIELD_SELECT02, ACL_FIELD_SELECT15},\n    {ACL_IP6SIP0WITHIPV4,   ACL_IP6SIP1WITHIPV4,ACL_FIELD_SELECT03, ACL_FIELD_SELECT04, ACL_FIELD_SELECT05, ACL_FIELD_SELECT06, ACL_FIELD_SELECT07, ACL_FIELD_SELECT08},\n    {ACL_IP6DIP0WITHIPV4,   ACL_IP6DIP1WITHIPV4,ACL_FIELD_SELECT09, ACL_FIELD_SELECT10, ACL_FIELD_SELECT11, ACL_FIELD_SELECT12, ACL_FIELD_SELECT13, ACL_FIELD_SELECT14},\n    {ACL_VIDRANGE,          ACL_IPRANGE,        ACL_PORTRANGE,      ACL_CTAG,           ACL_STAG,           ACL_FIELD_SELECT13, ACL_FIELD_SELECT14, ACL_FIELD_SELECT15}\n};\n\nCONST_T rtk_uint8 filter_advanceCaretagField[RTL8367C_ACLTEMPLATENO][2] = {\n    {TRUE,      7},\n    {TRUE,      7},\n    {FALSE,     0},\n    {FALSE,     0},\n    {TRUE,      7},\n};\n\n\nCONST_T rtk_uint8 filter_fieldTemplateIndex[FILTER_FIELD_END][RTK_FILTER_FIELD_USED_MAX] = {\n    {0x00, 0x01,0x02},\n    {0x03, 0x04,0x05},\n    {0x06},\n    {0x43},\n    {0x44},\n    {0x10, 0x11},\n    {0x12, 0x13},\n    {0x24},\n    {0x25},\n    {0x35},\n    {0x35},\n    {0x20, 0x21,0x22,0x23},\n    {0x30, 0x31,0x32,0x33},\n    {0x26},\n    {0x27},\n    {0x14},\n    {0x15},\n    {0x16},\n    {0x14},\n    {0x15},\n    {0x14},\n    {0x14},\n    {0x14},\n\n    {0x40},\n    {0x41},\n    {0x42},\n\n    {0x14},\n    {0x15},\n    {0x16},\n    {0x22},\n    {0x23},\n    {0x24},\n    {0x25},\n    {0x26},\n    {0x27},\n    {0x32},\n    {0x33},\n    {0x34},\n    {0x35},\n    {0x36},\n    {0x37},\n    {0x47},\n\n    {0xFF} /* Pattern Match */\n};\n\nCONST_T rtk_uint8 filter_fieldSize[FILTER_FIELD_END] = {\n    3, 3, 1, 1, 1,\n    2, 2, 1, 1, 1, 1, 4, 4, 1, 1,\n    1, 1, 1, 1, 1, 1, 1, 1,\n    1, 1, 1,\n    1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,\n    8\n};\n\nCONST_T rtk_uint16 field_selector[RTL8367C_FIELDSEL_FORMAT_NUMBER][2] =\n{\n    {FIELDSEL_FORMAT_DEFAULT, 0},    /* Field Selector 0 */\n    {FIELDSEL_FORMAT_DEFAULT, 0},    /* Field Selector 1 */\n    {FIELDSEL_FORMAT_IPPAYLOAD, 12}, /* Field Selector 2 */\n    {FIELDSEL_FORMAT_IPV6, 10},      /* Field Selector 3 */\n    {FIELDSEL_FORMAT_IPV6, 8},       /* Field Selector 4 */\n    {FIELDSEL_FORMAT_IPV4, 0},       /* Field Selector 5 */\n    {FIELDSEL_FORMAT_IPV4, 8},       /* Field Selector 6 */\n    {FIELDSEL_FORMAT_IPV6, 0},       /* Field Selector 7 */\n    {FIELDSEL_FORMAT_IPV6, 6},       /* Field Selector 8 */\n    {FIELDSEL_FORMAT_IPV6, 26},      /* Field Selector 9 */\n    {FIELDSEL_FORMAT_IPV6, 24},      /* Field Selector 10 */\n    {FIELDSEL_FORMAT_DEFAULT, 0},    /* Field Selector 11 */\n    {FIELDSEL_FORMAT_IPV4, 6},       /* Field Selector 12 */\n    {FIELDSEL_FORMAT_IPPAYLOAD, 0},  /* Field Selector 13 */\n    {FIELDSEL_FORMAT_IPPAYLOAD, 2},  /* Field Selector 14 */\n    {FIELDSEL_FORMAT_DEFAULT, 0}     /* Field Selector 15 */\n};\n\n\nstatic rtk_api_ret_t _rtk_filter_igrAcl_writeDataField(rtl8367c_aclrule *aclRule, rtk_filter_field_t *fieldPtr);\n\n\n/* Function Name:\n *      rtk_filter_igrAcl_init\n * Description:\n *      ACL initialization function\n * Input:\n *      None\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_NULL_POINTER - Pointer pFilter_field or pFilter_cfg point to NULL.\n * Note:\n *      This function enable and intialize ACL function\n */\nrtk_api_ret_t rtk_filter_igrAcl_init(void)\n{\n    rtl8367c_acltemplate_t       aclTemp;\n    rtk_uint32                 i, j;\n    rtk_api_ret_t          ret;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if ((ret = rtk_filter_igrAcl_cfg_delAll()) != RT_ERR_OK)\n        return ret;\n\n    for(i = 0; i < RTL8367C_ACLTEMPLATENO; i++)\n    {\n        for(j = 0; j < RTL8367C_ACLRULEFIELDNO;j++)\n            aclTemp.field[j] = filter_templateField[i][j];\n\n        if ((ret = rtl8367c_setAsicAclTemplate(i, &aclTemp)) != RT_ERR_OK)\n            return ret;\n    }\n\n    for(i = 0; i < RTL8367C_FIELDSEL_FORMAT_NUMBER; i++)\n    {\n        if ((ret = rtl8367c_setAsicFieldSelector(i, field_selector[i][0], field_selector[i][1])) != RT_ERR_OK)\n            return ret;\n    }\n\n    RTK_SCAN_ALL_PHY_PORTMASK(i)\n    {\n        if ((ret = rtl8367c_setAsicAcl(i, TRUE)) != RT_ERR_OK)\n            return ret;\n\n        if ((ret = rtl8367c_setAsicAclUnmatchedPermit(i, TRUE)) != RT_ERR_OK)\n            return ret;\n    }\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_filter_igrAcl_field_add\n * Description:\n *      Add comparison rule to an ACL configuration\n * Input:\n *      pFilter_cfg     - The ACL configuration that this function will add comparison rule\n *      pFilter_field   - The comparison rule that will be added.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - OK\n *      RT_ERR_FAILED           - Failed\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_NULL_POINTER     - Pointer pFilter_field or pFilter_cfg point to NULL.\n *      RT_ERR_INPUT            - Invalid input parameters.\n * Note:\n *      This function add a comparison rule (*pFilter_field) to an ACL configuration (*pFilter_cfg).\n *      Pointer pFilter_cfg points to an ACL configuration structure, this structure keeps multiple ACL\n *      comparison rules by means of linked list. Pointer pFilter_field will be added to linked\n *      list keeped by structure that pFilter_cfg points to.\n */\nrtk_api_ret_t rtk_filter_igrAcl_field_add(rtk_filter_cfg_t* pFilter_cfg, rtk_filter_field_t* pFilter_field)\n{\n    rtk_uint32 i;\n    rtk_filter_field_t *tailPtr;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(NULL == pFilter_cfg || NULL == pFilter_field)\n        return RT_ERR_NULL_POINTER;\n\n    if(pFilter_field->fieldType >= FILTER_FIELD_END)\n        return RT_ERR_ENTRY_INDEX;\n\n\n    if(0 == pFilter_field->fieldTemplateNo)\n    {\n        pFilter_field->fieldTemplateNo = filter_fieldSize[pFilter_field->fieldType];\n\n        for(i = 0; i < pFilter_field->fieldTemplateNo; i++)\n        {\n            pFilter_field->fieldTemplateIdx[i] = filter_fieldTemplateIndex[pFilter_field->fieldType][i];\n        }\n    }\n\n    if(NULL == pFilter_cfg->fieldHead)\n    {\n        pFilter_cfg->fieldHead = pFilter_field;\n    }\n    else\n    {\n        if (pFilter_cfg->fieldHead->next == NULL)\n        {\n            pFilter_cfg->fieldHead->next = pFilter_field;\n        }\n        else\n        {\n            tailPtr = pFilter_cfg->fieldHead->next;\n            while( tailPtr->next != NULL)\n            {\n                tailPtr = tailPtr->next;\n            }\n            tailPtr->next = pFilter_field;\n        }\n    }\n\n    return RT_ERR_OK;\n}\n\nstatic rtk_api_ret_t _rtk_filter_igrAcl_writeDataField(rtl8367c_aclrule *aclRule, rtk_filter_field_t *fieldPtr)\n{\n    rtk_uint32 i, tempIdx,fieldIdx, ipValue, ipMask;\n    rtk_uint32 ip6addr[RTK_IPV6_ADDR_WORD_LENGTH];\n    rtk_uint32 ip6mask[RTK_IPV6_ADDR_WORD_LENGTH];\n\n    for(i = 0; i < fieldPtr->fieldTemplateNo; i++)\n    {\n        tempIdx = (fieldPtr->fieldTemplateIdx[i] & 0xF0) >> 4;\n\n        aclRule[tempIdx].valid = TRUE;\n    }\n\n    switch (fieldPtr->fieldType)\n    {\n    /* use DMAC structure as representative for mac structure */\n    case FILTER_FIELD_DMAC:\n    case FILTER_FIELD_SMAC:\n\n        for(i = 0; i < fieldPtr->fieldTemplateNo; i++)\n        {\n            tempIdx = (fieldPtr->fieldTemplateIdx[i] & 0xF0) >> 4;\n            fieldIdx = fieldPtr->fieldTemplateIdx[i] & 0x0F;\n\n            aclRule[tempIdx].data_bits.field[fieldIdx] = fieldPtr->filter_pattern_union.mac.value.octet[5 - i*2] | (fieldPtr->filter_pattern_union.mac.value.octet[5 - (i*2 + 1)] << 8);\n            aclRule[tempIdx].care_bits.field[fieldIdx] = fieldPtr->filter_pattern_union.mac.mask.octet[5 - i*2] | (fieldPtr->filter_pattern_union.mac.mask.octet[5 - (i*2 + 1)] << 8);\n        }\n        break;\n    case FILTER_FIELD_ETHERTYPE:\n        for(i = 0; i < fieldPtr->fieldTemplateNo; i++)\n        {\n            tempIdx = (fieldPtr->fieldTemplateIdx[i] & 0xF0) >> 4;\n            fieldIdx = fieldPtr->fieldTemplateIdx[i] & 0x0F;\n\n            aclRule[tempIdx].data_bits.field[fieldIdx] = fieldPtr->filter_pattern_union.etherType.value;\n            aclRule[tempIdx].care_bits.field[fieldIdx] = fieldPtr->filter_pattern_union.etherType.mask;\n        }\n        break;\n    case FILTER_FIELD_IPV4_SIP:\n    case FILTER_FIELD_IPV4_DIP:\n\n        ipValue = fieldPtr->filter_pattern_union.sip.value;\n        ipMask = fieldPtr->filter_pattern_union.sip.mask;\n\n        for(i = 0; i < fieldPtr->fieldTemplateNo; i++)\n        {\n            tempIdx = (fieldPtr->fieldTemplateIdx[i] & 0xF0) >> 4;\n            fieldIdx = fieldPtr->fieldTemplateIdx[i] & 0x0F;\n\n            aclRule[tempIdx].data_bits.field[fieldIdx] = (0xFFFF & (ipValue >> (i*16)));\n            aclRule[tempIdx].care_bits.field[fieldIdx] = (0xFFFF & (ipMask >> (i*16)));\n        }\n        break;\n    case FILTER_FIELD_IPV4_TOS:\n        for(i = 0; i < fieldPtr->fieldTemplateNo; i++)\n        {\n            tempIdx = (fieldPtr->fieldTemplateIdx[i] & 0xF0) >> 4;\n            fieldIdx = fieldPtr->fieldTemplateIdx[i] & 0x0F;\n\n            aclRule[tempIdx].data_bits.field[fieldIdx] = fieldPtr->filter_pattern_union.ipTos.value & 0xFF;\n            aclRule[tempIdx].care_bits.field[fieldIdx] = fieldPtr->filter_pattern_union.ipTos.mask  & 0xFF;\n        }\n        break;\n    case FILTER_FIELD_IPV4_PROTOCOL:\n        for(i = 0; i < fieldPtr->fieldTemplateNo; i++)\n        {\n            tempIdx = (fieldPtr->fieldTemplateIdx[i] & 0xF0) >> 4;\n            fieldIdx = fieldPtr->fieldTemplateIdx[i] & 0x0F;\n\n            aclRule[tempIdx].data_bits.field[fieldIdx] = fieldPtr->filter_pattern_union.protocol.value & 0xFF;\n            aclRule[tempIdx].care_bits.field[fieldIdx] = fieldPtr->filter_pattern_union.protocol.mask  & 0xFF;\n        }\n        break;\n    case FILTER_FIELD_IPV6_SIPV6:\n    case FILTER_FIELD_IPV6_DIPV6:\n        for(i = 0; i < RTK_IPV6_ADDR_WORD_LENGTH; i++)\n        {\n            ip6addr[i] = fieldPtr->filter_pattern_union.sipv6.value.addr[i];\n            ip6mask[i] = fieldPtr->filter_pattern_union.sipv6.mask.addr[i];\n        }\n\n        for(i = 0; i < fieldPtr->fieldTemplateNo; i++)\n        {\n            tempIdx = (fieldPtr->fieldTemplateIdx[i] & 0xF0) >> 4;\n            fieldIdx = fieldPtr->fieldTemplateIdx[i] & 0x0F;\n\n            if(i < 2)\n            {\n                aclRule[tempIdx].data_bits.field[fieldIdx] = ((ip6addr[0] & (0xFFFF << (i * 16))) >> (i * 16));\n                aclRule[tempIdx].care_bits.field[fieldIdx] = ((ip6mask[0] & (0xFFFF << (i * 16))) >> (i * 16));\n            }\n            else\n            {\n                /*default acl template for ipv6 address supports MSB 32-bits and LSB 32-bits only*/\n                aclRule[tempIdx].data_bits.field[fieldIdx] = ((ip6addr[3] & (0xFFFF << ((i&1) * 16))) >> ((i&1) * 16));\n                aclRule[tempIdx].care_bits.field[fieldIdx] = ((ip6mask[3] & (0xFFFF << ((i&1) * 16))) >> ((i&1) * 16));\n            }\n        }\n\n        break;\n    case FILTER_FIELD_CTAG:\n    case FILTER_FIELD_STAG:\n\n        for(i = 0; i < fieldPtr->fieldTemplateNo; i++)\n        {\n            tempIdx = (fieldPtr->fieldTemplateIdx[i] & 0xF0) >> 4;\n            fieldIdx = fieldPtr->fieldTemplateIdx[i] & 0x0F;\n\n            aclRule[tempIdx].data_bits.field[fieldIdx] = (fieldPtr->filter_pattern_union.l2tag.pri.value << 13) | (fieldPtr->filter_pattern_union.l2tag.cfi.value << 12) | fieldPtr->filter_pattern_union.l2tag.vid.value;\n            aclRule[tempIdx].care_bits.field[fieldIdx] = (fieldPtr->filter_pattern_union.l2tag.pri.mask << 13) | (fieldPtr->filter_pattern_union.l2tag.cfi.mask << 12) | fieldPtr->filter_pattern_union.l2tag.vid.mask;\n        }\n        break;\n    case FILTER_FIELD_IPV4_FLAG:\n\n        for(i = 0; i < fieldPtr->fieldTemplateNo; i++)\n        {\n            tempIdx = (fieldPtr->fieldTemplateIdx[i] & 0xF0) >> 4;\n            fieldIdx = fieldPtr->fieldTemplateIdx[i] & 0x0F;\n\n            aclRule[tempIdx].data_bits.field[fieldIdx] &= 0x1FFF;\n            aclRule[tempIdx].data_bits.field[fieldIdx] |= (fieldPtr->filter_pattern_union.ipFlag.xf.value << 15);\n            aclRule[tempIdx].data_bits.field[fieldIdx] |= (fieldPtr->filter_pattern_union.ipFlag.df.value << 14);\n            aclRule[tempIdx].data_bits.field[fieldIdx] |= (fieldPtr->filter_pattern_union.ipFlag.mf.value << 13);\n\n            aclRule[tempIdx].care_bits.field[fieldIdx] &= 0x1FFF;\n            aclRule[tempIdx].care_bits.field[fieldIdx] |= (fieldPtr->filter_pattern_union.ipFlag.xf.mask << 15);\n            aclRule[tempIdx].care_bits.field[fieldIdx] |= (fieldPtr->filter_pattern_union.ipFlag.df.mask << 14);\n            aclRule[tempIdx].care_bits.field[fieldIdx] |= (fieldPtr->filter_pattern_union.ipFlag.mf.mask << 13);\n        }\n\n        break;\n    case FILTER_FIELD_IPV4_OFFSET:\n\n        for(i = 0; i < fieldPtr->fieldTemplateNo; i++)\n        {\n            tempIdx = (fieldPtr->fieldTemplateIdx[i] & 0xF0) >> 4;\n            fieldIdx = fieldPtr->fieldTemplateIdx[i] & 0x0F;\n\n            aclRule[tempIdx].data_bits.field[fieldIdx] &= 0xE000;\n            aclRule[tempIdx].data_bits.field[fieldIdx] |= fieldPtr->filter_pattern_union.inData.value;\n\n            aclRule[tempIdx].care_bits.field[fieldIdx] &= 0xE000;\n            aclRule[tempIdx].care_bits.field[fieldIdx] |= fieldPtr->filter_pattern_union.inData.mask;\n        }\n\n        break;\n\n    case FILTER_FIELD_IPV6_TRAFFIC_CLASS:\n        for(i = 0; i < fieldPtr->fieldTemplateNo; i++)\n        {\n            tempIdx = (fieldPtr->fieldTemplateIdx[i] & 0xF0) >> 4;\n            fieldIdx = fieldPtr->fieldTemplateIdx[i] & 0x0F;\n\n\n            aclRule[tempIdx].data_bits.field[fieldIdx] = (fieldPtr->filter_pattern_union.inData.value << 4)&0x0FF0;\n            aclRule[tempIdx].care_bits.field[fieldIdx] = (fieldPtr->filter_pattern_union.inData.mask << 4)&0x0FF0;\n        }\n        break;\n    case FILTER_FIELD_IPV6_NEXT_HEADER:\n        for(i = 0; i < fieldPtr->fieldTemplateNo; i++)\n        {\n            tempIdx = (fieldPtr->fieldTemplateIdx[i] & 0xF0) >> 4;\n            fieldIdx = fieldPtr->fieldTemplateIdx[i] & 0x0F;\n\n            aclRule[tempIdx].data_bits.field[fieldIdx] = fieldPtr->filter_pattern_union.inData.value << 8;\n            aclRule[tempIdx].care_bits.field[fieldIdx] = fieldPtr->filter_pattern_union.inData.mask << 8;\n        }\n        break;\n    case FILTER_FIELD_TCP_SPORT:\n        for(i = 0; i < fieldPtr->fieldTemplateNo; i++)\n        {\n            tempIdx = (fieldPtr->fieldTemplateIdx[i] & 0xF0) >> 4;\n            fieldIdx = fieldPtr->fieldTemplateIdx[i] & 0x0F;\n\n            aclRule[tempIdx].data_bits.field[fieldIdx] = fieldPtr->filter_pattern_union.tcpSrcPort.value;\n            aclRule[tempIdx].care_bits.field[fieldIdx] = fieldPtr->filter_pattern_union.tcpSrcPort.mask;\n        }\n        break;\n    case FILTER_FIELD_TCP_DPORT:\n        for(i = 0; i < fieldPtr->fieldTemplateNo; i++)\n        {\n            tempIdx = (fieldPtr->fieldTemplateIdx[i] & 0xF0) >> 4;\n            fieldIdx = fieldPtr->fieldTemplateIdx[i] & 0x0F;\n\n            aclRule[tempIdx].data_bits.field[fieldIdx] = fieldPtr->filter_pattern_union.tcpDstPort.value;\n            aclRule[tempIdx].care_bits.field[fieldIdx] = fieldPtr->filter_pattern_union.tcpDstPort.mask;\n        }\n        break;\n    case FILTER_FIELD_TCP_FLAG:\n\n        for(i = 0; i < fieldPtr->fieldTemplateNo; i++)\n        {\n            tempIdx = (fieldPtr->fieldTemplateIdx[i] & 0xF0) >> 4;\n            fieldIdx = fieldPtr->fieldTemplateIdx[i] & 0x0F;\n\n            aclRule[tempIdx].data_bits.field[fieldIdx] |= (fieldPtr->filter_pattern_union.tcpFlag.cwr.value << 7);\n            aclRule[tempIdx].data_bits.field[fieldIdx] |= (fieldPtr->filter_pattern_union.tcpFlag.ece.value << 6);\n            aclRule[tempIdx].data_bits.field[fieldIdx] |= (fieldPtr->filter_pattern_union.tcpFlag.urg.value << 5);\n            aclRule[tempIdx].data_bits.field[fieldIdx] |= (fieldPtr->filter_pattern_union.tcpFlag.ack.value << 4);\n            aclRule[tempIdx].data_bits.field[fieldIdx] |= (fieldPtr->filter_pattern_union.tcpFlag.psh.value << 3);\n            aclRule[tempIdx].data_bits.field[fieldIdx] |= (fieldPtr->filter_pattern_union.tcpFlag.rst.value << 2);\n            aclRule[tempIdx].data_bits.field[fieldIdx] |= (fieldPtr->filter_pattern_union.tcpFlag.syn.value << 1);\n            aclRule[tempIdx].data_bits.field[fieldIdx] |= fieldPtr->filter_pattern_union.tcpFlag.fin.value;\n\n            aclRule[tempIdx].care_bits.field[fieldIdx] |= (fieldPtr->filter_pattern_union.tcpFlag.cwr.mask << 7);\n            aclRule[tempIdx].care_bits.field[fieldIdx] |= (fieldPtr->filter_pattern_union.tcpFlag.ece.mask << 6);\n            aclRule[tempIdx].care_bits.field[fieldIdx] |= (fieldPtr->filter_pattern_union.tcpFlag.urg.mask << 5);\n            aclRule[tempIdx].care_bits.field[fieldIdx] |= (fieldPtr->filter_pattern_union.tcpFlag.ack.mask << 4);\n            aclRule[tempIdx].care_bits.field[fieldIdx] |= (fieldPtr->filter_pattern_union.tcpFlag.psh.mask << 3);\n            aclRule[tempIdx].care_bits.field[fieldIdx] |= (fieldPtr->filter_pattern_union.tcpFlag.rst.mask << 2);\n            aclRule[tempIdx].care_bits.field[fieldIdx] |= (fieldPtr->filter_pattern_union.tcpFlag.syn.mask << 1);\n            aclRule[tempIdx].care_bits.field[fieldIdx] |= fieldPtr->filter_pattern_union.tcpFlag.fin.mask;\n        }\n        break;\n    case FILTER_FIELD_UDP_SPORT:\n        for(i = 0; i < fieldPtr->fieldTemplateNo; i++)\n        {\n            tempIdx = (fieldPtr->fieldTemplateIdx[i] & 0xF0) >> 4;\n            fieldIdx = fieldPtr->fieldTemplateIdx[i] & 0x0F;\n\n            aclRule[tempIdx].data_bits.field[fieldIdx] = fieldPtr->filter_pattern_union.udpSrcPort.value;\n            aclRule[tempIdx].care_bits.field[fieldIdx] = fieldPtr->filter_pattern_union.udpSrcPort.mask;\n        }\n        break;\n    case FILTER_FIELD_UDP_DPORT:\n        for(i = 0; i < fieldPtr->fieldTemplateNo; i++)\n        {\n            tempIdx = (fieldPtr->fieldTemplateIdx[i] & 0xF0) >> 4;\n            fieldIdx = fieldPtr->fieldTemplateIdx[i] & 0x0F;\n\n            aclRule[tempIdx].data_bits.field[fieldIdx] = fieldPtr->filter_pattern_union.udpDstPort.value;\n            aclRule[tempIdx].care_bits.field[fieldIdx] = fieldPtr->filter_pattern_union.udpDstPort.mask;\n        }\n        break;\n    case FILTER_FIELD_ICMP_CODE:\n        for(i = 0; i < fieldPtr->fieldTemplateNo; i++)\n        {\n            tempIdx = (fieldPtr->fieldTemplateIdx[i] & 0xF0) >> 4;\n            fieldIdx = fieldPtr->fieldTemplateIdx[i] & 0x0F;\n\n            aclRule[tempIdx].data_bits.field[fieldIdx] &= 0xFF00;\n            aclRule[tempIdx].data_bits.field[fieldIdx] |= fieldPtr->filter_pattern_union.icmpCode.value;\n            aclRule[tempIdx].care_bits.field[fieldIdx] &= 0xFF00;\n            aclRule[tempIdx].care_bits.field[fieldIdx] |= fieldPtr->filter_pattern_union.icmpCode.mask;\n        }\n        break;\n    case FILTER_FIELD_ICMP_TYPE:\n        for(i = 0; i < fieldPtr->fieldTemplateNo; i++)\n        {\n            tempIdx = (fieldPtr->fieldTemplateIdx[i] & 0xF0) >> 4;\n            fieldIdx = fieldPtr->fieldTemplateIdx[i] & 0x0F;\n\n            aclRule[tempIdx].data_bits.field[fieldIdx] &= 0x00FF;\n            aclRule[tempIdx].data_bits.field[fieldIdx] |= (fieldPtr->filter_pattern_union.icmpType.value << 8);\n            aclRule[tempIdx].care_bits.field[fieldIdx] &= 0x00FF;\n            aclRule[tempIdx].care_bits.field[fieldIdx] |= (fieldPtr->filter_pattern_union.icmpType.mask << 8);\n        }\n        break;\n    case FILTER_FIELD_IGMP_TYPE:\n        for(i = 0; i < fieldPtr->fieldTemplateNo; i++)\n        {\n            tempIdx = (fieldPtr->fieldTemplateIdx[i] & 0xF0) >> 4;\n            fieldIdx = fieldPtr->fieldTemplateIdx[i] & 0x0F;\n\n            aclRule[tempIdx].data_bits.field[fieldIdx] = (fieldPtr->filter_pattern_union.igmpType.value << 8);\n            aclRule[tempIdx].care_bits.field[fieldIdx] = (fieldPtr->filter_pattern_union.igmpType.mask << 8);\n        }\n        break;\n    case FILTER_FIELD_PATTERN_MATCH:\n        for(i = 0; i < fieldPtr->fieldTemplateNo; i++)\n        {\n            tempIdx = (fieldPtr->fieldTemplateIdx[i] & 0xF0) >> 4;\n            fieldIdx = fieldPtr->fieldTemplateIdx[i] & 0x0F;\n\n            aclRule[tempIdx].data_bits.field[fieldIdx] = ((fieldPtr->filter_pattern_union.pattern.value[i/2] >> (16 * (i%2))) & 0x0000FFFF );\n            aclRule[tempIdx].care_bits.field[fieldIdx] = ((fieldPtr->filter_pattern_union.pattern.mask[i/2] >> (16 * (i%2))) & 0x0000FFFF );\n        }\n        break;\n    case FILTER_FIELD_VID_RANGE:\n    case FILTER_FIELD_IP_RANGE:\n    case FILTER_FIELD_PORT_RANGE:\n    default:\n        tempIdx = (fieldPtr->fieldTemplateIdx[0] & 0xF0) >> 4;\n        fieldIdx = fieldPtr->fieldTemplateIdx[0] & 0x0F;\n\n        aclRule[tempIdx].data_bits.field[fieldIdx] = fieldPtr->filter_pattern_union.inData.value;\n        aclRule[tempIdx].care_bits.field[fieldIdx] = fieldPtr->filter_pattern_union.inData.mask;\n        break;\n    }\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_filter_igrAcl_cfg_add\n * Description:\n *      Add an ACL configuration to ASIC\n * Input:\n *      filter_id       - Start index of ACL configuration.\n *      pFilter_cfg     - The ACL configuration that this function will add comparison rule\n *      pFilter_action  - Action(s) of ACL configuration.\n * Output:\n *      ruleNum - number of rules written in acl table\n * Return:\n *      RT_ERR_OK                               - OK\n *      RT_ERR_FAILED                           - Failed\n *      RT_ERR_SMI                              - SMI access error\n *      RT_ERR_NULL_POINTER                     - Pointer pFilter_field or pFilter_cfg point to NULL.\n *      RT_ERR_INPUT                            - Invalid input parameters.\n *      RT_ERR_ENTRY_INDEX                      - Invalid filter_id .\n *      RT_ERR_NULL_POINTER                     - Pointer pFilter_action or pFilter_cfg point to NULL.\n *      RT_ERR_FILTER_INACL_ACT_NOT_SUPPORT     - Action is not supported in this chip.\n *      RT_ERR_FILTER_INACL_RULE_NOT_SUPPORT    - Rule is not supported.\n * Note:\n *      This function store pFilter_cfg, pFilter_action into ASIC. The starting\n *      index(es) is filter_id.\n */\nrtk_api_ret_t rtk_filter_igrAcl_cfg_add(rtk_filter_id_t filter_id, rtk_filter_cfg_t* pFilter_cfg, rtk_filter_action_t* pFilter_action, rtk_filter_number_t *ruleNum)\n{\n    rtk_api_ret_t               retVal;\n    rtk_uint32                  careTagData, careTagMask;\n    rtk_uint32                  i,vidx, svidx, actType, ruleId;\n    rtk_uint32                  aclActCtrl;\n    rtk_uint32                  cpuPort;\n    rtk_filter_field_t*         fieldPtr;\n    rtl8367c_aclrule            aclRule[RTL8367C_ACLTEMPLATENO];\n    rtl8367c_aclrule            tempRule;\n    rtl8367c_acl_act_t          aclAct;\n    rtk_uint32                  noRulesAdd;\n    rtk_uint32                  portmask;\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(filter_id > RTL8367C_ACLRULEMAX )\n        return RT_ERR_ENTRY_INDEX;\n\n    if((NULL == pFilter_cfg) || (NULL == pFilter_action) || (NULL == ruleNum))\n        return RT_ERR_NULL_POINTER;\n\n    fieldPtr = pFilter_cfg->fieldHead;\n\n    /* init RULE */\n    for(i = 0; i < RTL8367C_ACLTEMPLATENO; i++)\n    {\n        memset(&aclRule[i], 0, sizeof(rtl8367c_aclrule));\n\n        aclRule[i].data_bits.type= i;\n        aclRule[i].care_bits.type= 0x7;\n    }\n\n    while(NULL != fieldPtr)\n    {\n        _rtk_filter_igrAcl_writeDataField(aclRule, fieldPtr);\n\n        fieldPtr = fieldPtr->next;\n    }\n\n    /*set care tag mask in User Defined Field 15*/\n    /*Follow care tag should not be used while ACL template and User defined fields are fully control by system designer*/\n    /*those advanced packet type care tag is used in default template design structure only*/\n    careTagData = 0;\n    careTagMask = 0;\n\n    for(i = CARE_TAG_TCP; i < CARE_TAG_END; i++)\n    {\n        if(pFilter_cfg->careTag.tagType[i].mask)\n            careTagMask = careTagMask | (1 << (i-CARE_TAG_TCP));\n\n        if(pFilter_cfg->careTag.tagType[i].value)\n            careTagData = careTagData | (1 << (i-CARE_TAG_TCP));\n    }\n\n    if(careTagData || careTagMask)\n    {\n        i = 0;\n        while(i < RTL8367C_ACLTEMPLATENO)\n        {\n            if(aclRule[i].valid == 1 && filter_advanceCaretagField[i][0] == TRUE)\n            {\n\n                aclRule[i].data_bits.field[filter_advanceCaretagField[i][1]] = careTagData & 0xFFFF;\n                aclRule[i].care_bits.field[filter_advanceCaretagField[i][1]] = careTagMask & 0xFFFF;\n                break;\n            }\n            i++;\n        }\n        /*none of previous used template containing field 15*/\n        if(i == RTL8367C_ACLTEMPLATENO)\n        {\n            i = 0;\n            while(i < RTL8367C_ACLTEMPLATENO)\n            {\n                if(filter_advanceCaretagField[i][0] == TRUE)\n                {\n                    aclRule[i].data_bits.field[filter_advanceCaretagField[i][1]] = careTagData & 0xFFFF;\n                    aclRule[i].care_bits.field[filter_advanceCaretagField[i][1]] = careTagMask & 0xFFFF;\n                    aclRule[i].valid = 1;\n                    break;\n                }\n                i++;\n            }\n        }\n    }\n\n    /*Check rule number*/\n    noRulesAdd = 0;\n    for(i = 0; i < RTL8367C_ACLTEMPLATENO; i++)\n    {\n        if(1 == aclRule[i].valid)\n        {\n            noRulesAdd ++;\n        }\n    }\n\n    *ruleNum = noRulesAdd;\n\n    if((filter_id + noRulesAdd - 1) > RTL8367C_ACLRULEMAX)\n    {\n        return RT_ERR_ENTRY_INDEX;\n    }\n\n    /*set care tag mask in TAG Indicator*/\n    careTagData = 0;\n    careTagMask = 0;\n\n    for(i = 0; i <= CARE_TAG_IPV6;i++)\n    {\n        if(0 == pFilter_cfg->careTag.tagType[i].mask )\n        {\n            careTagMask &=  ~(1 << i);\n        }\n        else\n        {\n            careTagMask |= (1 << i);\n            if(0 == pFilter_cfg->careTag.tagType[i].value )\n                careTagData &= ~(1 << i);\n            else\n                careTagData |= (1 << i);\n        }\n    }\n\n    for(i = 0; i < RTL8367C_ACLTEMPLATENO; i++)\n    {\n        aclRule[i].data_bits.tag_exist = (careTagData) & ACL_RULE_CARETAG_MASK;\n        aclRule[i].care_bits.tag_exist = (careTagMask) & ACL_RULE_CARETAG_MASK;\n    }\n\n    RTK_CHK_PORTMASK_VALID(&pFilter_cfg->activeport.value);\n    RTK_CHK_PORTMASK_VALID(&pFilter_cfg->activeport.mask);\n\n    for(i = 0; i < RTL8367C_ACLTEMPLATENO; i++)\n    {\n        if(TRUE == aclRule[i].valid)\n        {\n            if(rtk_switch_portmask_L2P_get(&pFilter_cfg->activeport.value, &portmask) != RT_ERR_OK)\n                return RT_ERR_PORT_MASK;\n\n            aclRule[i].data_bits.active_portmsk = portmask;\n\n            if(rtk_switch_portmask_L2P_get(&pFilter_cfg->activeport.mask, &portmask) != RT_ERR_OK)\n                return RT_ERR_PORT_MASK;\n\n            aclRule[i].care_bits.active_portmsk = portmask;\n        }\n    }\n\n    if(pFilter_cfg->invert >= FILTER_INVERT_END )\n        return RT_ERR_INPUT;\n\n\n    /*Last action gets high priority if actions are the same*/\n    memset(&aclAct, 0, sizeof(rtl8367c_acl_act_t));\n    aclActCtrl = 0;\n    for(actType = 0; actType < FILTER_ENACT_END; actType ++)\n    {\n        if(pFilter_action->actEnable[actType])\n        {\n            switch (actType)\n            {\n            case FILTER_ENACT_CVLAN_INGRESS:\n                if(pFilter_action->filterCvlanVid > RTL8367C_EVIDMAX)\n                    return RT_ERR_INPUT;\n\n                if((retVal = rtk_vlan_checkAndCreateMbr(pFilter_action->filterCvlanVid, &vidx)) != RT_ERR_OK)\n                {\n                    return retVal;\n                }\n                aclAct.cact = FILTER_ENACT_CVLAN_TYPE(actType);\n                aclAct.cvidx_cact = vidx;\n\n                if(aclActCtrl &(FILTER_ENACT_CVLAN_MASK))\n                {\n                    if(aclAct.cact_ext == FILTER_ENACT_CACTEXT_TAGONLY)\n                        aclAct.cact_ext = FILTER_ENACT_CACTEXT_BOTHVLANTAG;\n                }\n                else\n                {\n                    aclAct.cact_ext = FILTER_ENACT_CACTEXT_VLANONLY;\n                }\n\n                aclActCtrl |= FILTER_ENACT_CVLAN_MASK;\n                break;\n            case FILTER_ENACT_CVLAN_EGRESS:\n                if(pFilter_action->filterCvlanVid > RTL8367C_EVIDMAX)\n                    return RT_ERR_INPUT;\n\n                if((retVal = rtk_vlan_checkAndCreateMbr(pFilter_action->filterCvlanVid, &vidx)) != RT_ERR_OK)\n                    return retVal;\n\n                aclAct.cact = FILTER_ENACT_CVLAN_TYPE(actType);\n                aclAct.cvidx_cact = vidx;\n\n                if(aclActCtrl &(FILTER_ENACT_CVLAN_MASK))\n                {\n                    if(aclAct.cact_ext == FILTER_ENACT_CACTEXT_TAGONLY)\n                        aclAct.cact_ext = FILTER_ENACT_CACTEXT_BOTHVLANTAG;\n                }\n                else\n                {\n                    aclAct.cact_ext = FILTER_ENACT_CACTEXT_VLANONLY;\n                }\n\n                aclActCtrl |= FILTER_ENACT_CVLAN_MASK;\n                break;\n             case FILTER_ENACT_CVLAN_SVID:\n\n                aclAct.cact = FILTER_ENACT_CVLAN_TYPE(actType);\n\n                if(aclActCtrl &(FILTER_ENACT_CVLAN_MASK))\n                {\n                    if(aclAct.cact_ext == FILTER_ENACT_CACTEXT_TAGONLY)\n                        aclAct.cact_ext = FILTER_ENACT_CACTEXT_BOTHVLANTAG;\n                }\n                else\n                {\n                    aclAct.cact_ext = FILTER_ENACT_CACTEXT_VLANONLY;\n                }\n\n                aclActCtrl |= FILTER_ENACT_CVLAN_MASK;\n                break;\n             case FILTER_ENACT_POLICING_1:\n                if(pFilter_action->filterPolicingIdx[1] >= (RTK_METER_NUM + RTL8367C_MAX_LOG_CNT_NUM))\n                    return RT_ERR_INPUT;\n\n                aclAct.cact = FILTER_ENACT_CVLAN_TYPE(actType);\n                aclAct.cvidx_cact = pFilter_action->filterPolicingIdx[1];\n\n                if(aclActCtrl &(FILTER_ENACT_CVLAN_MASK))\n                {\n                    if(aclAct.cact_ext == FILTER_ENACT_CACTEXT_TAGONLY)\n                        aclAct.cact_ext = FILTER_ENACT_CACTEXT_BOTHVLANTAG;\n                }\n                else\n                {\n                    aclAct.cact_ext = FILTER_ENACT_CACTEXT_VLANONLY;\n                }\n\n                aclActCtrl |= FILTER_ENACT_CVLAN_MASK;\n                break;\n\n            case FILTER_ENACT_SVLAN_INGRESS:\n            case FILTER_ENACT_SVLAN_EGRESS:\n\n                if((retVal = rtk_svlan_checkAndCreateMbr(pFilter_action->filterSvlanVid, &svidx)) != RT_ERR_OK)\n                    return retVal;\n\n                aclAct.sact = FILTER_ENACT_SVLAN_TYPE(actType);\n                aclAct.svidx_sact = svidx;\n                aclActCtrl |= FILTER_ENACT_SVLAN_MASK;\n                break;\n            case FILTER_ENACT_SVLAN_CVID:\n\n                aclAct.sact = FILTER_ENACT_SVLAN_TYPE(actType);\n                aclActCtrl |= FILTER_ENACT_SVLAN_MASK;\n                break;\n            case FILTER_ENACT_POLICING_2:\n                if(pFilter_action->filterPolicingIdx[2] >= (RTK_METER_NUM + RTL8367C_MAX_LOG_CNT_NUM))\n                    return RT_ERR_INPUT;\n\n                aclAct.sact = FILTER_ENACT_SVLAN_TYPE(actType);\n                aclAct.svidx_sact = pFilter_action->filterPolicingIdx[2];\n                aclActCtrl |= FILTER_ENACT_SVLAN_MASK;\n                break;\n            case FILTER_ENACT_POLICING_0:\n                if(pFilter_action->filterPolicingIdx[0] >= (RTK_METER_NUM + RTL8367C_MAX_LOG_CNT_NUM))\n                    return RT_ERR_INPUT;\n\n                aclAct.aclmeteridx = pFilter_action->filterPolicingIdx[0];\n                aclActCtrl |= FILTER_ENACT_POLICING_MASK;\n                break;\n            case FILTER_ENACT_PRIORITY:\n            case FILTER_ENACT_1P_REMARK:\n                if(pFilter_action->filterPriority > RTL8367C_PRIMAX)\n                    return RT_ERR_INPUT;\n\n                aclAct.priact = FILTER_ENACT_PRI_TYPE(actType);\n                aclAct.pridx = pFilter_action->filterPriority;\n                aclActCtrl |= FILTER_ENACT_PRIORITY_MASK;\n                break;\n            case FILTER_ENACT_DSCP_REMARK:\n                if(pFilter_action->filterPriority > RTL8367C_DSCPMAX)\n                    return RT_ERR_INPUT;\n\n                aclAct.priact = FILTER_ENACT_PRI_TYPE(actType);\n                aclAct.pridx = pFilter_action->filterPriority;\n                aclActCtrl |= FILTER_ENACT_PRIORITY_MASK;\n                break;\n            case FILTER_ENACT_POLICING_3:\n                if(pFilter_action->filterPriority >= (RTK_METER_NUM + RTL8367C_MAX_LOG_CNT_NUM))\n                    return RT_ERR_INPUT;\n\n                aclAct.priact = FILTER_ENACT_PRI_TYPE(actType);\n                aclAct.pridx = pFilter_action->filterPolicingIdx[3];\n                aclActCtrl |= FILTER_ENACT_PRIORITY_MASK;\n                break;\n            case FILTER_ENACT_DROP:\n\n                aclAct.fwdact = FILTER_ENACT_FWD_TYPE(FILTER_ENACT_REDIRECT);\n                aclAct.fwdact_ext = FALSE;\n\n                aclAct.fwdpmask = 0;\n                aclActCtrl |= FILTER_ENACT_FWD_MASK;\n                break;\n            case FILTER_ENACT_REDIRECT:\n                RTK_CHK_PORTMASK_VALID(&pFilter_action->filterPortmask);\n\n                aclAct.fwdact = FILTER_ENACT_FWD_TYPE(actType);\n                aclAct.fwdact_ext = FALSE;\n\n                if(rtk_switch_portmask_L2P_get(&pFilter_action->filterPortmask, &portmask) != RT_ERR_OK)\n                    return RT_ERR_PORT_MASK;\n                aclAct.fwdpmask = portmask;\n\n                aclActCtrl |= FILTER_ENACT_FWD_MASK;\n                break;\n\n            case FILTER_ENACT_ADD_DSTPORT:\n                RTK_CHK_PORTMASK_VALID(&pFilter_action->filterPortmask);\n\n                aclAct.fwdact = FILTER_ENACT_FWD_TYPE(actType);\n                aclAct.fwdact_ext = FALSE;\n\n                if(rtk_switch_portmask_L2P_get(&pFilter_action->filterPortmask, &portmask) != RT_ERR_OK)\n                    return RT_ERR_PORT_MASK;\n                aclAct.fwdpmask = portmask;\n\n                aclActCtrl |= FILTER_ENACT_FWD_MASK;\n                break;\n            case FILTER_ENACT_MIRROR:\n                RTK_CHK_PORTMASK_VALID(&pFilter_action->filterPortmask);\n\n                aclAct.fwdact = FILTER_ENACT_FWD_TYPE(actType);\n                aclAct.cact_ext = FALSE;\n\n                if(rtk_switch_portmask_L2P_get(&pFilter_action->filterPortmask, &portmask) != RT_ERR_OK)\n                    return RT_ERR_PORT_MASK;\n                aclAct.fwdpmask = portmask;\n\n                aclActCtrl |= FILTER_ENACT_FWD_MASK;\n                break;\n            case FILTER_ENACT_TRAP_CPU:\n\n                aclAct.fwdact = FILTER_ENACT_FWD_TYPE(actType);\n                aclAct.fwdact_ext = FALSE;\n\n                aclActCtrl |= FILTER_ENACT_FWD_MASK;\n                break;\n            case FILTER_ENACT_COPY_CPU:\n                if((retVal = rtl8367c_getAsicCputagTrapPort(&cpuPort)) != RT_ERR_OK)\n                    return retVal;\n\n                aclAct.fwdact = FILTER_ENACT_FWD_TYPE(FILTER_ENACT_MIRROR);\n                aclAct.fwdact_ext = FALSE;\n\n                aclAct.fwdpmask = 1 << cpuPort;\n                aclActCtrl |= FILTER_ENACT_FWD_MASK;\n                break;\n            case FILTER_ENACT_ISOLATION:\n                RTK_CHK_PORTMASK_VALID(&pFilter_action->filterPortmask);\n\n                aclAct.fwdact_ext = TRUE;\n\n                if(rtk_switch_portmask_L2P_get(&pFilter_action->filterPortmask, &portmask) != RT_ERR_OK)\n                    return RT_ERR_PORT_MASK;\n                aclAct.fwdpmask = portmask;\n\n                aclActCtrl |= FILTER_ENACT_FWD_MASK;\n                break;\n\n            case FILTER_ENACT_INTERRUPT:\n\n                aclAct.aclint = TRUE;\n                aclActCtrl |= FILTER_ENACT_INTGPIO_MASK;\n                break;\n            case FILTER_ENACT_GPO:\n\n                aclAct.gpio_en = TRUE;\n                aclAct.gpio_pin = pFilter_action->filterPin;\n                aclActCtrl |= FILTER_ENACT_INTGPIO_MASK;\n                break;\n             case FILTER_ENACT_EGRESSCTAG_TAG:\n\n                if(aclActCtrl &(FILTER_ENACT_CVLAN_MASK))\n                {\n                    if(aclAct.cact_ext == FILTER_ENACT_CACTEXT_VLANONLY)\n                        aclAct.cact_ext = FILTER_ENACT_CACTEXT_BOTHVLANTAG;\n                }\n                else\n                {\n                    aclAct.cact_ext = FILTER_ENACT_CACTEXT_TAGONLY;\n                }\n                aclAct.tag_fmt = FILTER_CTAGFMT_TAG;\n                aclActCtrl |= FILTER_ENACT_CVLAN_MASK;\n                break;\n             case FILTER_ENACT_EGRESSCTAG_UNTAG:\n\n                if(aclActCtrl &(FILTER_ENACT_CVLAN_MASK))\n                {\n                    if(aclAct.cact_ext == FILTER_ENACT_CACTEXT_VLANONLY)\n                        aclAct.cact_ext = FILTER_ENACT_CACTEXT_BOTHVLANTAG;\n                }\n                else\n                {\n                    aclAct.cact_ext = FILTER_ENACT_CACTEXT_TAGONLY;\n                }\n                aclAct.tag_fmt = FILTER_CTAGFMT_UNTAG;\n                aclActCtrl |= FILTER_ENACT_CVLAN_MASK;\n                break;\n             case FILTER_ENACT_EGRESSCTAG_KEEP:\n\n                if(aclActCtrl &(FILTER_ENACT_CVLAN_MASK))\n                {\n                    if(aclAct.cact_ext == FILTER_ENACT_CACTEXT_VLANONLY)\n                        aclAct.cact_ext = FILTER_ENACT_CACTEXT_BOTHVLANTAG;\n                }\n                else\n                {\n                    aclAct.cact_ext = FILTER_ENACT_CACTEXT_TAGONLY;\n                }\n                aclAct.tag_fmt = FILTER_CTAGFMT_KEEP;\n                aclActCtrl |= FILTER_ENACT_CVLAN_MASK;\n                break;\n             case FILTER_ENACT_EGRESSCTAG_KEEPAND1PRMK:\n\n                if(aclActCtrl &(FILTER_ENACT_CVLAN_MASK))\n                {\n                    if(aclAct.cact_ext == FILTER_ENACT_CACTEXT_VLANONLY)\n                        aclAct.cact_ext = FILTER_ENACT_CACTEXT_BOTHVLANTAG;\n                }\n                else\n                {\n                    aclAct.cact_ext = FILTER_ENACT_CACTEXT_TAGONLY;\n                }\n                aclAct.tag_fmt = FILTER_CTAGFMT_KEEP1PRMK;\n                aclActCtrl |= FILTER_ENACT_CVLAN_MASK;\n                break;\n           default:\n                return RT_ERR_FILTER_INACL_ACT_NOT_SUPPORT;\n            }\n        }\n    }\n\n\n    /*check if free ACL rules are enough*/\n    for(i = filter_id; i < (filter_id + noRulesAdd); i++)\n    {\n        if((retVal = rtl8367c_getAsicAclRule(i, &tempRule)) != RT_ERR_OK )\n            return retVal;\n\n        if(tempRule.valid == TRUE)\n        {\n            return RT_ERR_TBL_FULL;\n        }\n    }\n\n    ruleId = 0;\n    for(i = 0; i < RTL8367C_ACLTEMPLATENO; i++)\n    {\n        if(aclRule[i].valid == TRUE)\n        {\n            /* write ACL action control */\n            if((retVal = rtl8367c_setAsicAclActCtrl(filter_id + ruleId, aclActCtrl)) != RT_ERR_OK )\n                return retVal;\n            /* write ACL action */\n            if((retVal = rtl8367c_setAsicAclAct(filter_id + ruleId, &aclAct)) != RT_ERR_OK )\n                return retVal;\n\n            /* write ACL not */\n            if((retVal = rtl8367c_setAsicAclNot(filter_id + ruleId, pFilter_cfg->invert)) != RT_ERR_OK )\n                return retVal;\n            /* write ACL rule */\n            if((retVal = rtl8367c_setAsicAclRule(filter_id + ruleId, &aclRule[i])) != RT_ERR_OK )\n                return retVal;\n\n            /* only the first rule will be written with input action control, aclActCtrl of other rules will be zero */\n            aclActCtrl = 0;\n            memset(&aclAct, 0, sizeof(rtl8367c_acl_act_t));\n\n            ruleId ++;\n        }\n    }\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_filter_igrAcl_cfg_del\n * Description:\n *      Delete an ACL configuration from ASIC\n * Input:\n *      filter_id   - Start index of ACL configuration.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - OK\n *      RT_ERR_FAILED           - Failed\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_FILTER_ENTRYIDX  - Invalid filter_id.\n * Note:\n *      This function delete a group of ACL rules starting from filter_id.\n */\nrtk_api_ret_t rtk_filter_igrAcl_cfg_del(rtk_filter_id_t filter_id)\n{\n    rtl8367c_aclrule initRule;\n    rtl8367c_acl_act_t  initAct;\n    rtk_api_ret_t ret;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(filter_id > RTL8367C_ACLRULEMAX )\n        return RT_ERR_FILTER_ENTRYIDX;\n\n    memset(&initRule, 0, sizeof(rtl8367c_aclrule));\n    memset(&initAct, 0, sizeof(rtl8367c_acl_act_t));\n\n    if((ret = rtl8367c_setAsicAclRule(filter_id, &initRule)) != RT_ERR_OK)\n        return ret;\n    if((ret = rtl8367c_setAsicAclActCtrl(filter_id, FILTER_ENACT_INIT_MASK))!= RT_ERR_OK)\n        return ret;\n    if((ret = rtl8367c_setAsicAclAct(filter_id, &initAct)) != RT_ERR_OK)\n        return ret;\n    if((ret = rtl8367c_setAsicAclNot(filter_id, DISABLED)) != RT_ERR_OK )\n        return ret;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_filter_igrAcl_cfg_delAll\n * Description:\n *      Delete all ACL entries from ASIC\n * Input:\n *      None\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n * Note:\n *      This function delete all ACL configuration from ASIC.\n */\nrtk_api_ret_t rtk_filter_igrAcl_cfg_delAll(void)\n{\n    rtk_uint32            i;\n    rtk_api_ret_t     ret;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    for(i = 0; i < RTL8367C_ACLRULENO; i++)\n    {\n        if((ret = rtl8367c_setAsicAclActCtrl(i, FILTER_ENACT_INIT_MASK))!= RT_ERR_OK)\n            return ret;\n        if((ret = rtl8367c_setAsicAclNot(i, DISABLED)) != RT_ERR_OK )\n            return ret;\n    }\n\n    return rtl8367c_setAsicRegBit(RTL8367C_REG_ACL_RESET_CFG, RTL8367C_ACL_RESET_CFG_OFFSET, TRUE);;\n}\n\n/* Function Name:\n *      rtk_filter_igrAcl_cfg_get\n * Description:\n *      Get one ingress acl configuration from ASIC.\n * Input:\n *      filter_id       - Start index of ACL configuration.\n * Output:\n *      pFilter_cfg     - buffer pointer of ingress acl data\n *      pFilter_action  - buffer pointer of ingress acl action\n * Return:\n *      RT_ERR_OK               - OK\n *      RT_ERR_FAILED           - Failed\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_NULL_POINTER     - Pointer pFilter_action or pFilter_cfg point to NULL.\n *      RT_ERR_FILTER_ENTRYIDX  - Invalid entry index.\n * Note:\n *      This function get configuration from ASIC.\n */\nrtk_api_ret_t rtk_filter_igrAcl_cfg_get(rtk_filter_id_t filter_id, rtk_filter_cfg_raw_t *pFilter_cfg, rtk_filter_action_t *pAction)\n{\n    rtk_api_ret_t               retVal;\n    rtk_uint32                  i, tmp;\n    rtl8367c_aclrule            aclRule;\n    rtl8367c_acl_act_t          aclAct;\n    rtk_uint32                  cpuPort;\n    rtl8367c_acltemplate_t      type;\n    rtl8367c_svlan_memconf_t    svlan_cfg;\n    rtl8367c_vlanconfiguser     vlanMC;\n    rtk_uint32                  phyPmask;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(NULL == pFilter_cfg || NULL == pAction)\n        return RT_ERR_NULL_POINTER;\n\n    if(filter_id > RTL8367C_ACLRULEMAX)\n        return RT_ERR_ENTRY_INDEX;\n\n    if ((retVal = rtl8367c_getAsicAclRule(filter_id, &aclRule)) != RT_ERR_OK)\n        return retVal;\n\n    /* Check valid */\n    if(aclRule.valid == 0)\n    {\n        pFilter_cfg->valid = DISABLED;\n        return RT_ERR_OK;\n    }\n\n    phyPmask = aclRule.data_bits.active_portmsk;\n    if(rtk_switch_portmask_P2L_get(phyPmask,&(pFilter_cfg->activeport.value)) != RT_ERR_OK)\n        return RT_ERR_FAILED;\n\n    phyPmask = aclRule.care_bits.active_portmsk;\n    if(rtk_switch_portmask_P2L_get(phyPmask,&(pFilter_cfg->activeport.mask)) != RT_ERR_OK)\n        return RT_ERR_FAILED;\n\n    for(i = 0; i <= CARE_TAG_IPV6; i++)\n    {\n        if(aclRule.data_bits.tag_exist & (1 << i))\n            pFilter_cfg->careTag.tagType[i].value = 1;\n        else\n            pFilter_cfg->careTag.tagType[i].value = 0;\n\n        if (aclRule.care_bits.tag_exist & (1 << i))\n            pFilter_cfg->careTag.tagType[i].mask = 1;\n        else\n            pFilter_cfg->careTag.tagType[i].mask = 0;\n    }\n\n    if(filter_advanceCaretagField[aclRule.data_bits.type][0] == TRUE)\n    {\n        /* Advanced Care tag setting */\n        for(i = CARE_TAG_TCP; i < CARE_TAG_END; i++)\n        {\n            if(aclRule.data_bits.field[filter_advanceCaretagField[aclRule.data_bits.type][1]] & (0x0001 << (i-CARE_TAG_TCP)) )\n                pFilter_cfg->careTag.tagType[i].value = 1;\n            else\n                pFilter_cfg->careTag.tagType[i].value = 0;\n\n            if(aclRule.care_bits.field[filter_advanceCaretagField[aclRule.care_bits.type][1]] & (0x0001 << (i-CARE_TAG_TCP)) )\n                pFilter_cfg->careTag.tagType[i].mask = 1;\n            else\n                pFilter_cfg->careTag.tagType[i].mask = 0;\n        }\n    }\n\n    for(i = 0; i < RTL8367C_ACLRULEFIELDNO; i++)\n    {\n        pFilter_cfg->careFieldRaw[i] = aclRule.care_bits.field[i];\n        pFilter_cfg->dataFieldRaw[i] = aclRule.data_bits.field[i];\n    }\n\n    if ((retVal = rtl8367c_getAsicAclNot(filter_id, &tmp))!= RT_ERR_OK)\n        return retVal;\n\n    pFilter_cfg->invert = tmp;\n\n    pFilter_cfg->valid = aclRule.valid;\n\n    memset(pAction, 0, sizeof(rtk_filter_action_t));\n\n    if ((retVal = rtl8367c_getAsicAclActCtrl(filter_id, &tmp))!= RT_ERR_OK)\n        return retVal;\n\n    if ((retVal = rtl8367c_getAsicAclAct(filter_id, &aclAct)) != RT_ERR_OK)\n        return retVal;\n\n    if(tmp & FILTER_ENACT_FWD_MASK)\n    {\n        if(TRUE == aclAct.fwdact_ext)\n        {\n            pAction->actEnable[FILTER_ENACT_ISOLATION] = TRUE;\n\n            phyPmask = aclAct.fwdpmask;\n            if(rtk_switch_portmask_P2L_get(phyPmask,&(pAction->filterPortmask)) != RT_ERR_OK)\n                return RT_ERR_FAILED;\n        }\n        else if(aclAct.fwdact == RTL8367C_ACL_FWD_TRAP)\n        {\n            pAction->actEnable[FILTER_ENACT_TRAP_CPU] = TRUE;\n        }\n        else if (aclAct.fwdact == RTL8367C_ACL_FWD_MIRRORFUNTION )\n        {\n            pAction->actEnable[FILTER_ENACT_MIRROR] = TRUE;\n\n            phyPmask = aclAct.fwdpmask;\n            if(rtk_switch_portmask_P2L_get(phyPmask,&(pAction->filterPortmask)) != RT_ERR_OK)\n                return RT_ERR_FAILED;\n        }\n        else if (aclAct.fwdact == RTL8367C_ACL_FWD_REDIRECT)\n        {\n            if(aclAct.fwdpmask == 0 )\n                pAction->actEnable[FILTER_ENACT_DROP] = TRUE;\n            else\n            {\n                pAction->actEnable[FILTER_ENACT_REDIRECT] = TRUE;\n\n                phyPmask = aclAct.fwdpmask;\n                if(rtk_switch_portmask_P2L_get(phyPmask,&(pAction->filterPortmask)) != RT_ERR_OK)\n                    return RT_ERR_FAILED;\n            }\n        }\n        else if (aclAct.fwdact == RTL8367C_ACL_FWD_MIRROR)\n        {\n            if((retVal = rtl8367c_getAsicCputagTrapPort(&cpuPort)) != RT_ERR_OK)\n                return retVal;\n            if (aclAct.fwdpmask == (1 << cpuPort))\n            {\n                pAction->actEnable[FILTER_ENACT_COPY_CPU] = TRUE;\n            }\n            else\n            {\n                pAction->actEnable[FILTER_ENACT_ADD_DSTPORT] = TRUE;\n\n                phyPmask = aclAct.fwdpmask;\n                if(rtk_switch_portmask_P2L_get(phyPmask,&(pAction->filterPortmask)) != RT_ERR_OK)\n                    return RT_ERR_FAILED;\n            }\n        }\n        else\n        {\n            return RT_ERR_FAILED;\n        }\n    }\n\n    if(tmp & FILTER_ENACT_POLICING_MASK)\n    {\n        pAction->actEnable[FILTER_ENACT_POLICING_0] = TRUE;\n        pAction->filterPolicingIdx[0] = aclAct.aclmeteridx;\n    }\n\n    if(tmp & FILTER_ENACT_PRIORITY_MASK)\n    {\n        if(aclAct.priact == FILTER_ENACT_PRI_TYPE(FILTER_ENACT_PRIORITY))\n        {\n            pAction->actEnable[FILTER_ENACT_PRIORITY] = TRUE;\n            pAction->filterPriority = aclAct.pridx;\n        }\n        else if(aclAct.priact == FILTER_ENACT_PRI_TYPE(FILTER_ENACT_1P_REMARK))\n        {\n            pAction->actEnable[FILTER_ENACT_1P_REMARK] = TRUE;\n            pAction->filterPriority = aclAct.pridx;\n        }\n        else if(aclAct.priact == FILTER_ENACT_PRI_TYPE(FILTER_ENACT_DSCP_REMARK))\n        {\n            pAction->actEnable[FILTER_ENACT_DSCP_REMARK] = TRUE;\n            pAction->filterPriority = aclAct.pridx;\n        }\n        else if(aclAct.priact == FILTER_ENACT_PRI_TYPE(FILTER_ENACT_POLICING_3))\n        {\n            pAction->actEnable[FILTER_ENACT_POLICING_3] = TRUE;\n            pAction->filterPolicingIdx[3]  = aclAct.pridx;\n        }\n    }\n\n    if(tmp & FILTER_ENACT_SVLAN_MASK)\n    {\n        if(aclAct.sact == FILTER_ENACT_SVLAN_TYPE(FILTER_ENACT_SVLAN_INGRESS))\n        {\n            if((retVal = rtl8367c_getAsicSvlanMemberConfiguration(aclAct.svidx_sact, &svlan_cfg)) != RT_ERR_OK)\n                return retVal;\n\n            pAction->actEnable[FILTER_ENACT_SVLAN_INGRESS] = TRUE;\n            pAction->filterSvlanIdx = aclAct.svidx_sact;\n            pAction->filterSvlanVid = svlan_cfg.vs_svid;\n        }\n        else if(aclAct.sact == FILTER_ENACT_SVLAN_TYPE(FILTER_ENACT_SVLAN_EGRESS))\n        {\n            if((retVal = rtl8367c_getAsicSvlanMemberConfiguration(aclAct.svidx_sact, &svlan_cfg)) != RT_ERR_OK)\n                return retVal;\n\n            pAction->actEnable[FILTER_ENACT_SVLAN_EGRESS] = TRUE;\n            pAction->filterSvlanIdx = aclAct.svidx_sact;\n            pAction->filterSvlanVid = svlan_cfg.vs_svid;\n        }\n        else if(aclAct.sact == FILTER_ENACT_SVLAN_TYPE(FILTER_ENACT_SVLAN_CVID))\n            pAction->actEnable[FILTER_ENACT_SVLAN_CVID] = TRUE;\n        else if(aclAct.sact == FILTER_ENACT_SVLAN_TYPE(FILTER_ENACT_POLICING_2))\n        {\n            pAction->actEnable[FILTER_ENACT_POLICING_2] = TRUE;\n            pAction->filterPolicingIdx[2]  = aclAct.svidx_sact;\n        }\n    }\n\n\n    if(tmp & FILTER_ENACT_CVLAN_MASK)\n    {\n        if(FILTER_ENACT_CACTEXT_TAGONLY == aclAct.cact_ext ||\n            FILTER_ENACT_CACTEXT_BOTHVLANTAG == aclAct.cact_ext )\n        {\n            if(FILTER_CTAGFMT_UNTAG == aclAct.tag_fmt)\n            {\n                pAction->actEnable[FILTER_ENACT_EGRESSCTAG_UNTAG] = TRUE;\n            }\n            else if(FILTER_CTAGFMT_TAG == aclAct.tag_fmt)\n            {\n                pAction->actEnable[FILTER_ENACT_EGRESSCTAG_TAG] = TRUE;\n            }\n            else if(FILTER_CTAGFMT_KEEP == aclAct.tag_fmt)\n            {\n                pAction->actEnable[FILTER_ENACT_EGRESSCTAG_KEEP] = TRUE;\n            }\n             else if(FILTER_CTAGFMT_KEEP1PRMK== aclAct.tag_fmt)\n            {\n                pAction->actEnable[FILTER_ENACT_EGRESSCTAG_KEEPAND1PRMK] = TRUE;\n            }\n\n        }\n\n        if(FILTER_ENACT_CACTEXT_VLANONLY == aclAct.cact_ext ||\n            FILTER_ENACT_CACTEXT_BOTHVLANTAG == aclAct.cact_ext )\n        {\n            if(aclAct.cact == FILTER_ENACT_CVLAN_TYPE(FILTER_ENACT_CVLAN_INGRESS))\n            {\n                if((retVal = rtl8367c_getAsicVlanMemberConfig(aclAct.cvidx_cact, &vlanMC)) != RT_ERR_OK)\n                    return retVal;\n\n                pAction->actEnable[FILTER_ENACT_CVLAN_INGRESS] = TRUE;\n                pAction->filterCvlanIdx  = aclAct.cvidx_cact;\n                pAction->filterCvlanVid  = vlanMC.evid;\n            }\n            else if(aclAct.cact == FILTER_ENACT_CVLAN_TYPE(FILTER_ENACT_CVLAN_EGRESS))\n            {\n                if((retVal = rtl8367c_getAsicVlanMemberConfig(aclAct.cvidx_cact, &vlanMC)) != RT_ERR_OK)\n                    return retVal;\n\n                pAction->actEnable[FILTER_ENACT_CVLAN_EGRESS] = TRUE;\n                pAction->filterCvlanIdx  = aclAct.cvidx_cact;\n                pAction->filterCvlanVid  = vlanMC.evid;\n            }\n            else if(aclAct.cact == FILTER_ENACT_CVLAN_TYPE(FILTER_ENACT_CVLAN_SVID))\n            {\n                pAction->actEnable[FILTER_ENACT_CVLAN_SVID] = TRUE;\n            }\n            else if(aclAct.cact == FILTER_ENACT_CVLAN_TYPE(FILTER_ENACT_POLICING_1))\n            {\n                pAction->actEnable[FILTER_ENACT_POLICING_1] = TRUE;\n                pAction->filterPolicingIdx[1]  = aclAct.cvidx_cact;\n            }\n        }\n    }\n\n    if(tmp & FILTER_ENACT_INTGPIO_MASK)\n    {\n        if(TRUE == aclAct.aclint)\n        {\n            pAction->actEnable[FILTER_ENACT_INTERRUPT] = TRUE;\n        }\n\n        if(TRUE == aclAct.gpio_en)\n        {\n            pAction->actEnable[FILTER_ENACT_GPO] = TRUE;\n            pAction->filterPin = aclAct.gpio_pin;\n        }\n    }\n\n    /* Get field type of RAW data */\n    if ((retVal = rtl8367c_getAsicAclTemplate(aclRule.data_bits.type, &type))!= RT_ERR_OK)\n        return retVal;\n\n    for(i = 0; i < RTL8367C_ACLRULEFIELDNO; i++)\n    {\n        pFilter_cfg->fieldRawType[i] = type.field[i];\n    }/* end of for(i...) */\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_filter_igrAcl_unmatchAction_set\n * Description:\n *      Set action to packets when no ACL configuration match\n * Input:\n *      port    - Port id.\n *      action  - Action.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port id.\n *      RT_ERR_INPUT        - Invalid input parameters.\n * Note:\n *      This function sets action of packets when no ACL configruation matches.\n */\nrtk_api_ret_t rtk_filter_igrAcl_unmatchAction_set(rtk_port_t port, rtk_filter_unmatch_action_t action)\n{\n    rtk_api_ret_t ret;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check port valid */\n    RTK_CHK_PORT_VALID(port);\n\n    if(action >= FILTER_UNMATCH_END)\n        return RT_ERR_INPUT;\n\n    if((ret = rtl8367c_setAsicAclUnmatchedPermit(rtk_switch_port_L2P_get(port), action)) != RT_ERR_OK)\n       return ret;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_filter_igrAcl_unmatchAction_get\n * Description:\n *      Get action to packets when no ACL configuration match\n * Input:\n *      port    - Port id.\n * Output:\n *      pAction - Action.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port id.\n *      RT_ERR_INPUT        - Invalid input parameters.\n * Note:\n *      This function gets action of packets when no ACL configruation matches.\n */\nrtk_api_ret_t rtk_filter_igrAcl_unmatchAction_get(rtk_port_t port, rtk_filter_unmatch_action_t* pAction)\n{\n    rtk_api_ret_t ret;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(NULL == pAction)\n        return RT_ERR_NULL_POINTER;\n\n    /* Check port valid */\n    RTK_CHK_PORT_VALID(port);\n\n    if((ret = rtl8367c_getAsicAclUnmatchedPermit(rtk_switch_port_L2P_get(port), pAction)) != RT_ERR_OK)\n       return ret;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_filter_igrAcl_state_set\n * Description:\n *      Set state of ingress ACL.\n * Input:\n *      port    - Port id.\n *      state   - Ingress ACL state.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port id.\n *      RT_ERR_INPUT        - Invalid input parameters.\n * Note:\n *      This function gets action of packets when no ACL configruation matches.\n */\nrtk_api_ret_t rtk_filter_igrAcl_state_set(rtk_port_t port, rtk_filter_state_t state)\n{\n    rtk_api_ret_t ret;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check port valid */\n    RTK_CHK_PORT_VALID(port);\n\n    if(state >= RTK_ENABLE_END)\n        return RT_ERR_INPUT;\n\n    if((ret = rtl8367c_setAsicAcl(rtk_switch_port_L2P_get(port), state)) != RT_ERR_OK)\n       return ret;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_filter_igrAcl_state_get\n * Description:\n *      Get state of ingress ACL.\n * Input:\n *      port    - Port id.\n * Output:\n *      pState  - Ingress ACL state.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port id.\n *      RT_ERR_INPUT        - Invalid input parameters.\n * Note:\n *      This function gets action of packets when no ACL configruation matches.\n */\nrtk_api_ret_t rtk_filter_igrAcl_state_get(rtk_port_t port, rtk_filter_state_t* pState)\n{\n    rtk_api_ret_t ret;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(NULL == pState)\n        return RT_ERR_NULL_POINTER;\n\n    /* Check port valid */\n    RTK_CHK_PORT_VALID(port);\n\n    if((ret = rtl8367c_getAsicAcl(rtk_switch_port_L2P_get(port), pState)) != RT_ERR_OK)\n       return ret;\n\n    return RT_ERR_OK;\n}\n/* Function Name:\n *      rtk_filter_igrAcl_template_set\n * Description:\n *      Set template of ingress ACL.\n * Input:\n *      template - Ingress ACL template\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n *      RT_ERR_INPUT           - Invalid input parameters.\n * Note:\n *      This function set ACL template.\n */\nrtk_api_ret_t rtk_filter_igrAcl_template_set(rtk_filter_template_t *aclTemplate)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32 idxField;\n    rtl8367c_acltemplate_t aclType;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(aclTemplate->index >= RTK_MAX_NUM_OF_FILTER_TYPE)\n        return RT_ERR_INPUT;\n\n    for(idxField = 0; idxField < RTK_MAX_NUM_OF_FILTER_FIELD; idxField++)\n    {\n        if(aclTemplate->fieldType[idxField] < FILTER_FIELD_RAW_DMAC_15_0 ||\n            (aclTemplate->fieldType[idxField] > FILTER_FIELD_RAW_CTAG && aclTemplate->fieldType[idxField] < FILTER_FIELD_RAW_IPV4_SIP_15_0 ) ||\n            (aclTemplate->fieldType[idxField] > FILTER_FIELD_RAW_IPV4_DIP_31_16 && aclTemplate->fieldType[idxField] < FILTER_FIELD_RAW_IPV6_SIP_15_0 ) ||\n            (aclTemplate->fieldType[idxField] > FILTER_FIELD_RAW_IPV6_DIP_31_16 && aclTemplate->fieldType[idxField] < FILTER_FIELD_RAW_VIDRANGE ) ||\n            (aclTemplate->fieldType[idxField] > FILTER_FIELD_RAW_FIELD_VALID && aclTemplate->fieldType[idxField] < FILTER_FIELD_RAW_FIELD_SELECT00 ) ||\n            aclTemplate->fieldType[idxField] >= FILTER_FIELD_RAW_END)\n        {\n            return RT_ERR_INPUT;\n        }\n    }\n\n    for(idxField = 0; idxField < RTK_MAX_NUM_OF_FILTER_FIELD; idxField++)\n    {\n        aclType.field[idxField] = aclTemplate->fieldType[idxField];\n    }\n\n    if((retVal = rtl8367c_setAsicAclTemplate(aclTemplate->index, &aclType)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_filter_igrAcl_template_get\n * Description:\n *      Get template of ingress ACL.\n * Input:\n *      template - Ingress ACL template\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n * Note:\n *      This function gets template of ACL.\n */\nrtk_api_ret_t rtk_filter_igrAcl_template_get(rtk_filter_template_t *aclTemplate)\n{\n    rtk_api_ret_t ret;\n    rtk_uint32 idxField;\n    rtl8367c_acltemplate_t aclType;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(NULL == aclTemplate)\n        return RT_ERR_NULL_POINTER;\n\n    if(aclTemplate->index >= RTK_MAX_NUM_OF_FILTER_TYPE)\n        return RT_ERR_INPUT;\n\n   if((ret = rtl8367c_getAsicAclTemplate(aclTemplate->index, &aclType)) != RT_ERR_OK)\n       return ret;\n\n    for(idxField = 0; idxField < RTK_MAX_NUM_OF_FILTER_FIELD; idxField ++)\n    {\n        aclTemplate->fieldType[idxField] = aclType.field[idxField];\n    }\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_filter_igrAcl_field_sel_set\n * Description:\n *      Set user defined field selectors in HSB\n * Input:\n *      index       - index of field selector 0-15\n *      format      - Format of field selector\n *      offset      - Retrieving data offset\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n * Note:\n *      System support 16 user defined field selctors.\n *      Each selector can be enabled or disable.\n *      User can defined retrieving 16-bits in many predefiend\n *      standard l2/l3/l4 payload.\n */\nrtk_api_ret_t rtk_filter_igrAcl_field_sel_set(rtk_uint32 index, rtk_field_sel_t format, rtk_uint32 offset)\n{\n    rtk_api_ret_t ret;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(index >= RTL8367C_FIELDSEL_FORMAT_NUMBER)\n        return RT_ERR_OUT_OF_RANGE;\n\n    if(format >= FORMAT_END)\n        return RT_ERR_OUT_OF_RANGE;\n\n    if(offset > RTL8367C_FIELDSEL_MAX_OFFSET)\n        return RT_ERR_OUT_OF_RANGE;\n\n    if((ret = rtl8367c_setAsicFieldSelector(index, (rtk_uint32)format, offset)) != RT_ERR_OK)\n       return ret;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_filter_igrAcl_field_sel_get\n * Description:\n *      Get user defined field selectors in HSB\n * Input:\n *      index       - index of field selector 0-15\n * Output:\n *      pFormat     - Format of field selector\n *      pOffset     - Retrieving data offset\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n * Note:\n *      None.\n */\nrtk_api_ret_t rtk_filter_igrAcl_field_sel_get(rtk_uint32 index, rtk_field_sel_t *pFormat, rtk_uint32 *pOffset)\n{\n    rtk_api_ret_t ret;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(NULL == pFormat || NULL == pOffset)\n        return RT_ERR_NULL_POINTER;\n\n    if(index >= RTL8367C_FIELDSEL_FORMAT_NUMBER)\n        return RT_ERR_OUT_OF_RANGE;\n\n    if((ret = rtl8367c_getAsicFieldSelector(index, pFormat, pOffset)) != RT_ERR_OK)\n       return ret;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_filter_iprange_set\n * Description:\n *      Set IP Range check\n * Input:\n *      index       - index of IP Range 0-15\n *      type        - IP Range check type, 0:Delete a entry, 1: IPv4_SIP, 2: IPv4_DIP, 3:IPv6_SIP, 4:IPv6_DIP\n *      upperIp     - The upper bound of IP range\n *      lowerIp     - The lower Bound of IP range\n * Output:\n *      None.\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n *      RT_ERR_OUT_OF_RANGE    - The parameter is out of range\n *      RT_ERR_INPUT           - Input error\n * Note:\n *      upperIp must be larger or equal than lowerIp.\n */\nrtk_api_ret_t rtk_filter_iprange_set(rtk_uint32 index, rtk_filter_iprange_t type, ipaddr_t upperIp, ipaddr_t lowerIp)\n{\n    rtk_api_ret_t ret;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(index > RTL8367C_ACLRANGEMAX)\n        return RT_ERR_OUT_OF_RANGE;\n\n    if(type >= IPRANGE_END)\n        return RT_ERR_OUT_OF_RANGE;\n\n    if(lowerIp > upperIp)\n        return RT_ERR_INPUT;\n\n    if((ret = rtl8367c_setAsicAclIpRange(index, type, upperIp, lowerIp)) != RT_ERR_OK)\n       return ret;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_filter_iprange_get\n * Description:\n *      Set IP Range check\n * Input:\n *      index       - index of IP Range 0-15\n * Output:\n *      pType        - IP Range check type, 0:Delete a entry, 1: IPv4_SIP, 2: IPv4_DIP, 3:IPv6_SIP, 4:IPv6_DIP\n *      pUpperIp     - The upper bound of IP range\n *      pLowerIp     - The lower Bound of IP range\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n *      RT_ERR_OUT_OF_RANGE    - The parameter is out of range\n * Note:\n *      None.\n */\nrtk_api_ret_t rtk_filter_iprange_get(rtk_uint32 index, rtk_filter_iprange_t *pType, ipaddr_t *pUpperIp, ipaddr_t *pLowerIp)\n{\n    rtk_api_ret_t ret;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if((NULL == pType) || (NULL == pUpperIp) || (NULL == pLowerIp))\n        return RT_ERR_NULL_POINTER;\n\n    if(index > RTL8367C_ACLRANGEMAX)\n        return RT_ERR_OUT_OF_RANGE;\n\n    if((ret = rtl8367c_getAsicAclIpRange(index, pType, pUpperIp, pLowerIp)) != RT_ERR_OK)\n       return ret;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_filter_vidrange_set\n * Description:\n *      Set VID Range check\n * Input:\n *      index       - index of VID Range 0-15\n *      type        - IP Range check type, 0:Delete a entry, 1: CVID, 2: SVID\n *      upperVid    - The upper bound of VID range\n *      lowerVid    - The lower Bound of VID range\n * Output:\n *      None.\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n *      RT_ERR_OUT_OF_RANGE    - The parameter is out of range\n *      RT_ERR_INPUT           - Input error\n * Note:\n *      upperVid must be larger or equal than lowerVid.\n */\nrtk_api_ret_t rtk_filter_vidrange_set(rtk_uint32 index, rtk_filter_vidrange_t type, rtk_uint32 upperVid, rtk_uint32 lowerVid)\n{\n    rtk_api_ret_t ret;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(index > RTL8367C_ACLRANGEMAX)\n        return RT_ERR_OUT_OF_RANGE;\n\n    if(type >= VIDRANGE_END)\n        return RT_ERR_OUT_OF_RANGE;\n\n    if(lowerVid > upperVid)\n        return RT_ERR_INPUT;\n\n    if( (upperVid > RTL8367C_VIDMAX) || (lowerVid > RTL8367C_VIDMAX))\n        return RT_ERR_OUT_OF_RANGE;\n\n    if((ret = rtl8367c_setAsicAclVidRange(index, type, upperVid, lowerVid)) != RT_ERR_OK)\n       return ret;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_filter_vidrange_get\n * Description:\n *      Get VID Range check\n * Input:\n *      index       - index of VID Range 0-15\n * Output:\n *      pType        - IP Range check type, 0:Unused, 1: CVID, 2: SVID\n *      pUpperVid    - The upper bound of VID range\n *      pLowerVid    - The lower Bound of VID range\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n *      RT_ERR_OUT_OF_RANGE    - The parameter is out of range\n * Note:\n *      None.\n */\nrtk_api_ret_t rtk_filter_vidrange_get(rtk_uint32 index, rtk_filter_vidrange_t *pType, rtk_uint32 *pUpperVid, rtk_uint32 *pLowerVid)\n{\n    rtk_api_ret_t ret;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if((NULL == pType) || (NULL == pUpperVid) || (NULL == pLowerVid))\n        return RT_ERR_NULL_POINTER;\n\n    if(index > RTL8367C_ACLRANGEMAX)\n        return RT_ERR_OUT_OF_RANGE;\n\n    if((ret = rtl8367c_getAsicAclVidRange(index, pType, pUpperVid, pLowerVid)) != RT_ERR_OK)\n       return ret;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_filter_portrange_set\n * Description:\n *      Set Port Range check\n * Input:\n *      index       - index of Port Range 0-15\n *      type        - IP Range check type, 0:Delete a entry, 1: Source Port, 2: Destnation Port\n *      upperPort   - The upper bound of Port range\n *      lowerPort   - The lower Bound of Port range\n * Output:\n *      None.\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n *      RT_ERR_OUT_OF_RANGE    - The parameter is out of range\n *      RT_ERR_INPUT           - Input error\n * Note:\n *      upperPort must be larger or equal than lowerPort.\n */\nrtk_api_ret_t rtk_filter_portrange_set(rtk_uint32 index, rtk_filter_portrange_t type, rtk_uint32 upperPort, rtk_uint32 lowerPort)\n{\n    rtk_api_ret_t ret;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(index > RTL8367C_ACLRANGEMAX)\n        return RT_ERR_OUT_OF_RANGE;\n\n    if(type >= PORTRANGE_END)\n        return RT_ERR_OUT_OF_RANGE;\n\n    if(lowerPort > upperPort)\n        return RT_ERR_INPUT;\n\n    if(upperPort > RTL8367C_ACL_PORTRANGEMAX)\n        return RT_ERR_INPUT;\n\n    if(lowerPort > RTL8367C_ACL_PORTRANGEMAX)\n        return RT_ERR_INPUT;\n\n    if((ret = rtl8367c_setAsicAclPortRange(index, type, upperPort, lowerPort)) != RT_ERR_OK)\n       return ret;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_filter_portrange_get\n * Description:\n *      Set Port Range check\n * Input:\n *      index       - index of Port Range 0-15\n * Output:\n *      pType       - IP Range check type, 0:Delete a entry, 1: Source Port, 2: Destnation Port\n *      pUpperPort  - The upper bound of Port range\n *      pLowerPort  - The lower Bound of Port range\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n *      RT_ERR_OUT_OF_RANGE    - The parameter is out of range\n *      RT_ERR_INPUT           - Input error\n * Note:\n *      None.\n */\nrtk_api_ret_t rtk_filter_portrange_get(rtk_uint32 index, rtk_filter_portrange_t *pType, rtk_uint32 *pUpperPort, rtk_uint32 *pLowerPort)\n{\n    rtk_api_ret_t ret;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if((NULL == pType) || (NULL == pUpperPort) || (NULL == pLowerPort))\n        return RT_ERR_NULL_POINTER;\n\n    if(index > RTL8367C_ACLRANGEMAX)\n        return RT_ERR_OUT_OF_RANGE;\n\n    if((ret = rtl8367c_getAsicAclPortRange(index, pType, pUpperPort, pLowerPort)) != RT_ERR_OK)\n       return ret;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_filter_igrAclPolarity_set\n * Description:\n *      Set ACL Goip control palarity\n * Input:\n *      polarity - 1: High, 0: Low\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n * Note:\n *      none\n */\nrtk_api_ret_t rtk_filter_igrAclPolarity_set(rtk_uint32 polarity)\n{\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(polarity > 1)\n        return RT_ERR_OUT_OF_RANGE;\n    return rtl8367c_setAsicAclGpioPolarity(polarity);\n}\n/* Function Name:\n *      rtk_filter_igrAclPolarity_get\n * Description:\n *      Get ACL Goip control palarity\n * Input:\n *      pPolarity - 1: High, 0: Low\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n * Note:\n *      none\n */\nrtk_api_ret_t rtk_filter_igrAclPolarity_get(rtk_uint32* pPolarity)\n{\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(NULL == pPolarity)\n        return RT_ERR_NULL_POINTER;\n\n    return rtl8367c_getAsicAclGpioPolarity(pPolarity);\n}\n\n\n\n\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/cpu.c",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * $Revision: 76306 $\n * $Date: 2017-03-08 15:13:58 +0800 (週三, 08 三月 2017) $\n *\n * Purpose : RTK switch high-level API for RTL8367/RTL8367C\n * Feature : Here is a list of all functions and variables in CPU module.\n *\n */\n\n#include <rtk_switch.h>\n#include <rtk_error.h>\n#include <cpu.h>\n#include <string.h>\n\n#include <rtl8367c_asicdrv.h>\n#include <rtl8367c_asicdrv_cputag.h>\n\n/* Function Name:\n *      rtk_cpu_enable_set\n * Description:\n *      Set CPU port function enable/disable.\n * Input:\n *      enable - CPU port function enable\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameter.\n *      RT_ERR_PORT_ID      - Invalid port number.\n * Note:\n *      The API can set CPU port function enable/disable.\n */\nrtk_api_ret_t rtk_cpu_enable_set(rtk_enable_t enable)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if (enable >= RTK_ENABLE_END)\n        return RT_ERR_ENABLE;\n\n    if ((retVal = rtl8367c_setAsicCputagEnable(enable)) != RT_ERR_OK)\n        return retVal;\n\n    if (DISABLED == enable)\n    {\n        if ((retVal = rtl8367c_setAsicCputagPortmask(0)) != RT_ERR_OK)\n            return retVal;\n    }\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_cpu_enable_get\n * Description:\n *      Get CPU port and its setting.\n * Input:\n *      None\n * Output:\n *      pEnable - CPU port function enable\n * Return:\n *      RT_ERR_OK               - OK\n *      RT_ERR_FAILED           - Failed\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_INPUT            - Invalid input parameters.\n *      RT_ERR_L2_NO_CPU_PORT   - CPU port is not exist\n * Note:\n *      The API can get CPU port function enable/disable.\n */\nrtk_api_ret_t rtk_cpu_enable_get(rtk_enable_t *pEnable)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(NULL == pEnable)\n        return RT_ERR_NULL_POINTER;\n\n    if ((retVal = rtl8367c_getAsicCputagEnable(pEnable)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_cpu_tagPort_set\n * Description:\n *      Set CPU port and CPU tag insert mode.\n * Input:\n *      port - Port id.\n *      mode - CPU tag insert for packets egress from CPU port.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameter.\n *      RT_ERR_PORT_ID      - Invalid port number.\n * Note:\n *      The API can set CPU port and inserting proprietary CPU tag mode (Length/Type 0x8899)\n *      to the frame that transmitting to CPU port.\n *      The inset cpu tag mode is as following:\n *      - CPU_INSERT_TO_ALL\n *      - CPU_INSERT_TO_TRAPPING\n *      - CPU_INSERT_TO_NONE\n */\nrtk_api_ret_t rtk_cpu_tagPort_set(rtk_port_t port, rtk_cpu_insert_t mode)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check port Valid */\n    RTK_CHK_PORT_VALID(port);\n\n    if (mode >= CPU_INSERT_END)\n        return RT_ERR_INPUT;\n\n    if ((retVal = rtl8367c_setAsicCputagPortmask(1<<rtk_switch_port_L2P_get(port))) != RT_ERR_OK)\n        return retVal;\n\n    if ((retVal = rtl8367c_setAsicCputagTrapPort(rtk_switch_port_L2P_get(port))) != RT_ERR_OK)\n        return retVal;\n\n    if ((retVal = rtl8367c_setAsicCputagInsertMode(mode)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_cpu_tagPort_get\n * Description:\n *      Get CPU port and CPU tag insert mode.\n * Input:\n *      None\n * Output:\n *      pPort - Port id.\n *      pMode - CPU tag insert for packets egress from CPU port, 0:all insert 1:Only for trapped packets 2:no insert.\n * Return:\n *      RT_ERR_OK               - OK\n *      RT_ERR_FAILED           - Failed\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_INPUT            - Invalid input parameters.\n *      RT_ERR_L2_NO_CPU_PORT   - CPU port is not exist\n * Note:\n *      The API can get configured CPU port and its setting.\n *      The inset cpu tag mode is as following:\n *      - CPU_INSERT_TO_ALL\n *      - CPU_INSERT_TO_TRAPPING\n *      - CPU_INSERT_TO_NONE\n */\nrtk_api_ret_t rtk_cpu_tagPort_get(rtk_port_t *pPort, rtk_cpu_insert_t *pMode)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32 pmsk, port;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(NULL == pPort)\n        return RT_ERR_NULL_POINTER;\n\n    if(NULL == pMode)\n        return RT_ERR_NULL_POINTER;\n\n    if ((retVal = rtl8367c_getAsicCputagPortmask(&pmsk)) != RT_ERR_OK)\n        return retVal;\n\n    if ((retVal = rtl8367c_getAsicCputagTrapPort(&port)) != RT_ERR_OK)\n        return retVal;\n\n    *pPort = rtk_switch_port_P2L_get(port);\n\n    if ((retVal = rtl8367c_getAsicCputagInsertMode(pMode)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n\n/* Function Name:\n *      rtk_cpu_awarePort_set\n * Description:\n *      Set CPU aware port mask.\n * Input:\n *      portmask - Port mask.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_MASK      - Invalid port mask.\n * Note:\n *      The API can set configured CPU aware port mask.\n */\nrtk_api_ret_t rtk_cpu_awarePort_set(rtk_portmask_t *pPortmask)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32 phyMbrPmask;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check Valid port mask */\n    if(NULL == pPortmask)\n        return RT_ERR_NULL_POINTER;\n\n    /* Check port mask valid */\n    RTK_CHK_PORTMASK_VALID(pPortmask);\n\n    if(rtk_switch_portmask_L2P_get(pPortmask, &phyMbrPmask) != RT_ERR_OK)\n        return RT_ERR_FAILED;\n\n    if ((retVal = rtl8367c_setAsicCputagPortmask(phyMbrPmask)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_cpu_awarePort_get\n * Description:\n *      Get CPU aware port mask.\n * Input:\n *      None\n * Output:\n *      pPortmask - Port mask.\n * Return:\n *      RT_ERR_OK               - OK\n *      RT_ERR_FAILED           - Failed\n *      RT_ERR_SMI              - SMI access error\n * Note:\n *      The API can get configured CPU aware port mask.\n */\nrtk_api_ret_t rtk_cpu_awarePort_get(rtk_portmask_t *pPortmask)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32 pmsk;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(NULL == pPortmask)\n        return RT_ERR_NULL_POINTER;\n\n    if ((retVal = rtl8367c_getAsicCputagPortmask(&pmsk)) != RT_ERR_OK)\n        return retVal;\n\n    if(rtk_switch_portmask_P2L_get(pmsk, pPortmask) != RT_ERR_OK)\n        return RT_ERR_FAILED;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_cpu_tagPosition_set\n * Description:\n *      Set CPU tag position.\n * Input:\n *      position - CPU tag position.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT      - Invalid input.\n * Note:\n *      The API can set CPU tag position.\n */\nrtk_api_ret_t rtk_cpu_tagPosition_set(rtk_cpu_position_t position)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if (position >= CPU_POS_END)\n        return RT_ERR_INPUT;\n\n    if ((retVal = rtl8367c_setAsicCputagPosition(position)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_cpu_tagPosition_get\n * Description:\n *      Get CPU tag position.\n * Input:\n *      None\n * Output:\n *      pPosition - CPU tag position.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT      - Invalid input.\n * Note:\n *      The API can get CPU tag position.\n */\nrtk_api_ret_t rtk_cpu_tagPosition_get(rtk_cpu_position_t *pPosition)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(NULL == pPosition)\n        return RT_ERR_NULL_POINTER;\n\n    if ((retVal = rtl8367c_getAsicCputagPosition(pPosition)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_cpu_tagLength_set\n * Description:\n *      Set CPU tag length.\n * Input:\n *      length - CPU tag length.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT      - Invalid input.\n * Note:\n *      The API can set CPU tag length.\n */\nrtk_api_ret_t rtk_cpu_tagLength_set(rtk_cpu_tag_length_t length)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if (length >= CPU_LEN_END)\n        return RT_ERR_INPUT;\n\n    if ((retVal = rtl8367c_setAsicCputagMode(length)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_cpu_tagLength_get\n * Description:\n *      Get CPU tag length.\n * Input:\n *      None\n * Output:\n *      pLength - CPU tag length.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT      - Invalid input.\n * Note:\n *      The API can get CPU tag length.\n */\nrtk_api_ret_t rtk_cpu_tagLength_get(rtk_cpu_tag_length_t *pLength)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(NULL == pLength)\n        return RT_ERR_NULL_POINTER;\n\n    if ((retVal = rtl8367c_getAsicCputagMode(pLength)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_cpu_priRemap_set\n * Description:\n *      Configure CPU priorities mapping to internal absolute priority.\n * Input:\n *      int_pri     - internal priority value.\n *      new_pri    - new internal priority value.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - OK\n *      RT_ERR_FAILED           - Failed\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_INPUT            - Invalid input parameters.\n *      RT_ERR_VLAN_PRIORITY    - Invalid 1p priority.\n *      RT_ERR_QOS_INT_PRIORITY - Invalid priority.\n * Note:\n *      Priority of CPU tag assignment for internal asic priority, and it is used for queue usage and packet scheduling.\n */\nrtk_api_ret_t rtk_cpu_priRemap_set(rtk_pri_t int_pri, rtk_pri_t new_pri)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if (new_pri > RTL8367C_PRIMAX || int_pri > RTL8367C_PRIMAX)\n        return  RT_ERR_VLAN_PRIORITY;\n\n    if ((retVal = rtl8367c_setAsicCputagPriorityRemapping(int_pri, new_pri)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_cpu_priRemap_get\n * Description:\n *      Configure CPU priorities mapping to internal absolute priority.\n * Input:\n *      int_pri     - internal priority value.\n * Output:\n *      pNew_pri    - new internal priority value.\n * Return:\n *      RT_ERR_OK               - OK\n *      RT_ERR_FAILED           - Failed\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_INPUT            - Invalid input parameters.\n *      RT_ERR_VLAN_PRIORITY    - Invalid 1p priority.\n *      RT_ERR_QOS_INT_PRIORITY - Invalid priority.\n * Note:\n *      Priority of CPU tag assignment for internal asic priority, and it is used for queue usage and packet scheduling.\n */\nrtk_api_ret_t rtk_cpu_priRemap_get(rtk_pri_t int_pri, rtk_pri_t *pNew_pri)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(NULL == pNew_pri)\n        return RT_ERR_NULL_POINTER;\n\n    if (int_pri > RTL8367C_PRIMAX)\n        return  RT_ERR_QOS_INT_PRIORITY;\n\n    if ((retVal = rtl8367c_getAsicCputagPriorityRemapping(int_pri, pNew_pri)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_cpu_acceptLength_set\n * Description:\n *      Set CPU accept  length.\n * Input:\n *      length - CPU tag length.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT      - Invalid input.\n * Note:\n *      The API can set CPU accept length.\n */\nrtk_api_ret_t rtk_cpu_acceptLength_set(rtk_cpu_rx_length_t length)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if (length >= CPU_RX_END)\n        return RT_ERR_INPUT;\n\n    if ((retVal = rtl8367c_setAsicCputagRxMinLength(length)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_cpu_acceptLength_get\n * Description:\n *      Get CPU accept length.\n * Input:\n *      None\n * Output:\n *      pLength - CPU tag length.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT      - Invalid input.\n * Note:\n *      The API can get CPU accept length.\n */\nrtk_api_ret_t rtk_cpu_acceptLength_get(rtk_cpu_rx_length_t *pLength)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(NULL == pLength)\n        return RT_ERR_NULL_POINTER;\n\n    if ((retVal = rtl8367c_getAsicCputagRxMinLength(pLength)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n\n\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/dot1x.c",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * $Revision: 75783 $\n * $Date: 2017-02-13 14:54:53 +0800 (週一, 13 二月 2017) $\n *\n * Purpose : RTK switch high-level API for RTL8367/RTL8367C\n * Feature : Here is a list of all functions and variables in 1X module.\n *\n */\n\n#include <rtk_switch.h>\n#include <rtk_error.h>\n#include <dot1x.h>\n#include <string.h>\n#include <vlan.h>\n#include <rtl8367c_asicdrv.h>\n#include <rtl8367c_asicdrv_dot1x.h>\n#include <rtl8367c_asicdrv_rma.h>\n#include <rtl8367c_asicdrv_lut.h>\n#include <rtl8367c_asicdrv_vlan.h>\n\n/* Function Name:\n *      rtk_dot1x_unauthPacketOper_set\n * Description:\n *      Set 802.1x unauth action configuration.\n * Input:\n *      port            - Port id.\n *      unauth_action   - 802.1X unauth action.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number.\n *      RT_ERR_INPUT        - Invalid input parameter.\n * Note:\n *      This API can set 802.1x unauth action configuration.\n *      The unauth action is as following:\n *      - DOT1X_ACTION_DROP\n *      - DOT1X_ACTION_TRAP2CPU\n *      - DOT1X_ACTION_GUESTVLAN\n */\nrtk_api_ret_t rtk_dot1x_unauthPacketOper_set(rtk_port_t port, rtk_dot1x_unauth_action_t unauth_action)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check port Valid */\n    RTK_CHK_PORT_VALID(port);\n\n    if (unauth_action >= DOT1X_ACTION_END)\n        return RT_ERR_DOT1X_PROC;\n\n    if ((retVal = rtl8367c_setAsic1xProcConfig(rtk_switch_port_L2P_get(port), unauth_action)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_dot1x_unauthPacketOper_get\n * Description:\n *      Get 802.1x unauth action configuration.\n * Input:\n *      port - Port id.\n * Output:\n *      pUnauth_action - 802.1X unauth action.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n *      RT_ERR_PORT_ID      - Invalid port number.\n * Note:\n *      This API can get 802.1x unauth action configuration.\n *      The unauth action is as following:\n *      - DOT1X_ACTION_DROP\n *      - DOT1X_ACTION_TRAP2CPU\n *      - DOT1X_ACTION_GUESTVLAN\n */\nrtk_api_ret_t rtk_dot1x_unauthPacketOper_get(rtk_port_t port, rtk_dot1x_unauth_action_t *pUnauth_action)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check port Valid */\n    RTK_CHK_PORT_VALID(port);\n\n    if(NULL == pUnauth_action)\n        return RT_ERR_NULL_POINTER;\n\n    if ((retVal = rtl8367c_getAsic1xProcConfig(rtk_switch_port_L2P_get(port), pUnauth_action)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_dot1x_eapolFrame2CpuEnable_set\n * Description:\n *      Set 802.1x EAPOL packet trap to CPU configuration\n * Input:\n *      enable - The status of 802.1x EAPOL packet.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_ENABLE       - Invalid enable input.\n * Note:\n *      To support 802.1x authentication functionality, EAPOL frame (ether type = 0x888E) has to\n *      be trapped to CPU.\n *      The status of EAPOL frame trap to CPU is as following:\n *      - DISABLED\n *      - ENABLED\n */\nrtk_api_ret_t rtk_dot1x_eapolFrame2CpuEnable_set(rtk_enable_t enable)\n{\n    rtk_api_ret_t retVal;\n    rtl8367c_rma_t rmacfg;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if (enable >= RTK_ENABLE_END)\n        return RT_ERR_ENABLE;\n\n    if ((retVal = rtl8367c_getAsicRma(3, &rmacfg)) != RT_ERR_OK)\n        return retVal;\n\n    if (ENABLED == enable)\n        rmacfg.operation = RMAOP_TRAP_TO_CPU;\n    else if (DISABLED == enable)\n        rmacfg.operation = RMAOP_FORWARD;\n\n    if ((retVal = rtl8367c_setAsicRma(3, &rmacfg)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_dot1x_eapolFrame2CpuEnable_get\n * Description:\n *      Get 802.1x EAPOL packet trap to CPU configuration\n * Input:\n *      None\n * Output:\n *      pEnable - The status of 802.1x EAPOL packet.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n * Note:\n *      To support 802.1x authentication functionality, EAPOL frame (ether type = 0x888E) has to\n *      be trapped to CPU.\n *      The status of EAPOL frame trap to CPU is as following:\n *      - DISABLED\n *      - ENABLED\n */\nrtk_api_ret_t rtk_dot1x_eapolFrame2CpuEnable_get(rtk_enable_t *pEnable)\n{\n    rtk_api_ret_t retVal;\n    rtl8367c_rma_t rmacfg;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(NULL == pEnable)\n        return RT_ERR_NULL_POINTER;\n\n    if ((retVal = rtl8367c_getAsicRma(3, &rmacfg)) != RT_ERR_OK)\n        return retVal;\n\n    if (RMAOP_TRAP_TO_CPU == rmacfg.operation)\n        *pEnable = ENABLED;\n    else\n        *pEnable = DISABLED;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_dot1x_portBasedEnable_set\n * Description:\n *      Set 802.1x port-based enable configuration\n * Input:\n *      port - Port id.\n *      enable - The status of 802.1x port.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK                   - OK\n *      RT_ERR_FAILED               - Failed\n *      RT_ERR_SMI                  - SMI access error\n *      RT_ERR_PORT_ID              - Invalid port number.\n *      RT_ERR_ENABLE               - Invalid enable input.\n *      RT_ERR_DOT1X_PORTBASEDPNEN  - 802.1X port-based enable error\n * Note:\n *      The API can update the port-based port enable register content. If a port is 802.1x\n *      port based network access control \"enabled\", it should be authenticated so packets\n *      from that port won't be dropped or trapped to CPU.\n *      The status of 802.1x port-based network access control is as following:\n *      - DISABLED\n *      - ENABLED\n */\nrtk_api_ret_t rtk_dot1x_portBasedEnable_set(rtk_port_t port, rtk_enable_t enable)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check port Valid */\n    RTK_CHK_PORT_VALID(port);\n\n    if (enable >= RTK_ENABLE_END)\n        return RT_ERR_ENABLE;\n\n    if ((retVal = rtl8367c_setAsic1xPBEnConfig(rtk_switch_port_L2P_get(port),enable)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_dot1x_portBasedEnable_get\n * Description:\n *      Get 802.1x port-based enable configuration\n * Input:\n *      port - Port id.\n * Output:\n *      pEnable - The status of 802.1x port.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n *      RT_ERR_PORT_ID      - Invalid port number.\n * Note:\n *      The API can get the 802.1x port-based port status.\n */\nrtk_api_ret_t rtk_dot1x_portBasedEnable_get(rtk_port_t port, rtk_enable_t *pEnable)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check port Valid */\n    RTK_CHK_PORT_VALID(port);\n\n    if(NULL == pEnable)\n        return RT_ERR_NULL_POINTER;\n\n    if ((retVal = rtl8367c_getAsic1xPBEnConfig(rtk_switch_port_L2P_get(port), pEnable)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_dot1x_portBasedAuthStatus_set\n * Description:\n *      Set 802.1x port-based auth. port configuration\n * Input:\n *      port - Port id.\n *      port_auth - The status of 802.1x port.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK                   - OK\n *      RT_ERR_FAILED               - Failed\n *      RT_ERR_SMI                  - SMI access error\n *      RT_ERR_PORT_ID              - Invalid port number.\n *     RT_ERR_DOT1X_PORTBASEDAUTH   - 802.1X port-based auth error\n * Note:\n *      The authenticated status of 802.1x port-based network access control is as following:\n *      - UNAUTH\n *      - AUTH\n */\nrtk_api_ret_t rtk_dot1x_portBasedAuthStatus_set(rtk_port_t port, rtk_dot1x_auth_status_t port_auth)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check port Valid */\n    RTK_CHK_PORT_VALID(port);\n\n     if (port_auth >= AUTH_STATUS_END)\n        return RT_ERR_DOT1X_PORTBASEDAUTH;\n\n    if ((retVal = rtl8367c_setAsic1xPBAuthConfig(rtk_switch_port_L2P_get(port), port_auth)) != RT_ERR_OK)\n        return retVal;\n\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_dot1x_portBasedAuthStatus_get\n * Description:\n *      Get 802.1x port-based auth. port configuration\n * Input:\n *      port - Port id.\n * Output:\n *      pPort_auth - The status of 802.1x port.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n *      RT_ERR_PORT_ID      - Invalid port number.\n * Note:\n *      The API can get 802.1x port-based port auth.information.\n */\nrtk_api_ret_t rtk_dot1x_portBasedAuthStatus_get(rtk_port_t port, rtk_dot1x_auth_status_t *pPort_auth)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(NULL == pPort_auth)\n        return RT_ERR_NULL_POINTER;\n\n    /* Check port Valid */\n    RTK_CHK_PORT_VALID(port);\n\n    if ((retVal = rtl8367c_getAsic1xPBAuthConfig(rtk_switch_port_L2P_get(port), pPort_auth)) != RT_ERR_OK)\n        return retVal;\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_dot1x_portBasedDirection_set\n * Description:\n *      Set 802.1x port-based operational direction configuration\n * Input:\n *      port            - Port id.\n *      port_direction  - Operation direction\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK                   - OK\n *      RT_ERR_FAILED               - Failed\n *      RT_ERR_SMI                  - SMI access error\n *      RT_ERR_PORT_ID              - Invalid port number.\n *      RT_ERR_DOT1X_PORTBASEDOPDIR - 802.1X port-based operation direction error\n * Note:\n *      The operate controlled direction of 802.1x port-based network access control is as following:\n *      - BOTH\n *      - IN\n */\nrtk_api_ret_t rtk_dot1x_portBasedDirection_set(rtk_port_t port, rtk_dot1x_direction_t port_direction)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check port Valid */\n    RTK_CHK_PORT_VALID(port);\n\n    if (port_direction >= DIRECTION_END)\n        return RT_ERR_DOT1X_PORTBASEDOPDIR;\n\n    if ((retVal = rtl8367c_setAsic1xPBOpdirConfig(rtk_switch_port_L2P_get(port), port_direction)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_dot1x_portBasedDirection_get\n * Description:\n *      Get 802.1X port-based operational direction configuration\n * Input:\n *      port - Port id.\n * Output:\n *      pPort_direction - Operation direction\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n *      RT_ERR_PORT_ID      - Invalid port number.\n * Note:\n *      The API can get 802.1x port-based operational direction information.\n */\nrtk_api_ret_t rtk_dot1x_portBasedDirection_get(rtk_port_t port, rtk_dot1x_direction_t *pPort_direction)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(NULL == pPort_direction)\n        return RT_ERR_NULL_POINTER;\n\n    /* Check port Valid */\n    RTK_CHK_PORT_VALID(port);\n\n    if ((retVal = rtl8367c_getAsic1xPBOpdirConfig(rtk_switch_port_L2P_get(port), pPort_direction)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_dot1x_macBasedEnable_set\n * Description:\n *      Set 802.1x mac-based port enable configuration\n * Input:\n *      port - Port id.\n *      enable - The status of 802.1x port.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK                   - OK\n *      RT_ERR_FAILED               - Failed\n *      RT_ERR_SMI                  - SMI access error\n *      RT_ERR_PORT_ID              - Invalid port number.\n *      RT_ERR_ENABLE               - Invalid enable input.\n *      RT_ERR_DOT1X_MACBASEDPNEN   - 802.1X mac-based enable error\n * Note:\n *      If a port is 802.1x MAC based network access control \"enabled\", the incoming packets should\n *       be authenticated so packets from that port won't be dropped or trapped to CPU.\n *      The status of 802.1x MAC-based network access control is as following:\n *      - DISABLED\n *      - ENABLED\n */\nrtk_api_ret_t rtk_dot1x_macBasedEnable_set(rtk_port_t port, rtk_enable_t enable)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check port Valid */\n    RTK_CHK_PORT_VALID(port);\n\n    if (enable >= RTK_ENABLE_END)\n        return RT_ERR_ENABLE;\n\n    if ((retVal = rtl8367c_setAsic1xMBEnConfig(rtk_switch_port_L2P_get(port),enable)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_dot1x_macBasedEnable_get\n * Description:\n *      Get 802.1x mac-based port enable configuration\n * Input:\n *      port - Port id.\n * Output:\n *      pEnable - The status of 802.1x port.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n *      RT_ERR_PORT_ID      - Invalid port number.\n * Note:\n *      If a port is 802.1x MAC based network access control \"enabled\", the incoming packets should\n *      be authenticated so packets from that port wont be dropped or trapped to CPU.\n *      The status of 802.1x MAC-based network access control is as following:\n *      - DISABLED\n *      - ENABLED\n */\nrtk_api_ret_t rtk_dot1x_macBasedEnable_get(rtk_port_t port, rtk_enable_t *pEnable)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(NULL == pEnable)\n        return RT_ERR_NULL_POINTER;\n\n    /* Check port Valid */\n    RTK_CHK_PORT_VALID(port);\n\n    if ((retVal = rtl8367c_getAsic1xMBEnConfig(rtk_switch_port_L2P_get(port), pEnable)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_dot1x_macBasedAuthMac_add\n * Description:\n *      Add an authenticated MAC to ASIC\n * Input:\n *      port        - Port id.\n *      pAuth_mac   - The authenticated MAC.\n *      fid         - filtering database.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK                   - OK\n *      RT_ERR_FAILED               - Failed\n *      RT_ERR_SMI                  - SMI access error\n *      RT_ERR_PORT_ID              - Invalid port number.\n *      RT_ERR_ENABLE               - Invalid enable input.\n *      RT_ERR_DOT1X_MACBASEDPNEN   - 802.1X mac-based enable error\n * Note:\n *      The API can add a 802.1x authenticated MAC address to port. If the MAC does not exist in LUT,\n *      user can't add this MAC to auth status.\n */\nrtk_api_ret_t rtk_dot1x_macBasedAuthMac_add(rtk_port_t port, rtk_mac_t *pAuth_mac, rtk_fid_t fid)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32 method;\n    rtl8367c_luttb l2Table;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* must be unicast address */\n    if ((pAuth_mac == NULL) || (pAuth_mac->octet[0] & 0x1))\n        return RT_ERR_MAC;\n\n    /* Check port Valid */\n    RTK_CHK_PORT_VALID(port);\n\n    if (fid > RTL8367C_FIDMAX)\n        return RT_ERR_L2_FID;\n\n    memset(&l2Table, 0, sizeof(rtl8367c_luttb));\n\n    /* fill key (MAC,FID) to get L2 entry */\n    memcpy(l2Table.mac.octet, pAuth_mac->octet, ETHER_ADDR_LEN);\n    l2Table.fid = fid;\n    method = LUTREADMETHOD_MAC;\n    retVal = rtl8367c_getAsicL2LookupTb(method, &l2Table);\n    if ( RT_ERR_OK == retVal)\n    {\n        if (l2Table.spa != rtk_switch_port_L2P_get(port))\n            return RT_ERR_DOT1X_MAC_PORT_MISMATCH;\n\n        memcpy(l2Table.mac.octet, pAuth_mac->octet, ETHER_ADDR_LEN);\n        l2Table.fid = fid;\n        l2Table.efid = 0;\n        l2Table.auth = 1;\n        retVal = rtl8367c_setAsicL2LookupTb(&l2Table);\n        return retVal;\n    }\n    else\n        return retVal;\n\n}\n\n/* Function Name:\n *      rtk_dot1x_macBasedAuthMac_del\n * Description:\n *      Delete an authenticated MAC to ASIC\n * Input:\n *      port - Port id.\n *      pAuth_mac - The authenticated MAC.\n *      fid - filtering database.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_MAC          - Invalid MAC address.\n *      RT_ERR_PORT_ID      - Invalid port number.\n * Note:\n *      The API can delete a 802.1x authenticated MAC address to port. It only change the auth status of\n *      the MAC and won't delete it from LUT.\n */\nrtk_api_ret_t rtk_dot1x_macBasedAuthMac_del(rtk_port_t port, rtk_mac_t *pAuth_mac, rtk_fid_t fid)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32 method;\n    rtl8367c_luttb l2Table;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* must be unicast address */\n    if ((pAuth_mac == NULL) || (pAuth_mac->octet[0] & 0x1))\n        return RT_ERR_MAC;\n\n    /* Check port Valid */\n    RTK_CHK_PORT_VALID(port);\n\n    if (fid > RTL8367C_FIDMAX)\n        return RT_ERR_L2_FID;\n\n    memset(&l2Table, 0, sizeof(rtl8367c_luttb));\n\n    /* fill key (MAC,FID) to get L2 entry */\n    memcpy(l2Table.mac.octet, pAuth_mac->octet, ETHER_ADDR_LEN);\n    l2Table.fid = fid;\n    method = LUTREADMETHOD_MAC;\n    retVal = rtl8367c_getAsicL2LookupTb(method, &l2Table);\n    if (RT_ERR_OK == retVal)\n    {\n        if (l2Table.spa != rtk_switch_port_L2P_get(port))\n            return RT_ERR_DOT1X_MAC_PORT_MISMATCH;\n\n        memcpy(l2Table.mac.octet, pAuth_mac->octet, ETHER_ADDR_LEN);\n        l2Table.fid = fid;\n        l2Table.auth = 0;\n        retVal = rtl8367c_setAsicL2LookupTb(&l2Table);\n        return retVal;\n    }\n    else\n        return retVal;\n\n}\n\n/* Function Name:\n *      rtk_dot1x_macBasedDirection_set\n * Description:\n *      Set 802.1x mac-based operational direction configuration\n * Input:\n *      mac_direction - Operation direction\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK                   - OK\n *      RT_ERR_FAILED               - Failed\n *      RT_ERR_SMI                  - SMI access error\n *      RT_ERR_INPUT                - Invalid input parameter.\n *      RT_ERR_DOT1X_MACBASEDOPDIR  - 802.1X mac-based operation direction error\n * Note:\n *      The operate controlled direction of 802.1x mac-based network access control is as following:\n *      - BOTH\n *      - IN\n */\nrtk_api_ret_t rtk_dot1x_macBasedDirection_set(rtk_dot1x_direction_t mac_direction)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if (mac_direction >= DIRECTION_END)\n        return RT_ERR_DOT1X_MACBASEDOPDIR;\n\n    if ((retVal = rtl8367c_setAsic1xMBOpdirConfig(mac_direction)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_dot1x_macBasedDirection_get\n * Description:\n *      Get 802.1x mac-based operational direction configuration\n * Input:\n *      port - Port id.\n * Output:\n *      pMac_direction - Operation direction\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n * Note:\n *      The API can get 802.1x mac-based operational direction information.\n */\nrtk_api_ret_t rtk_dot1x_macBasedDirection_get(rtk_dot1x_direction_t *pMac_direction)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(NULL == pMac_direction)\n        return RT_ERR_NULL_POINTER;\n\n    if ((retVal = rtl8367c_getAsic1xMBOpdirConfig(pMac_direction)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      Set 802.1x guest VLAN configuration\n * Description:\n *      Set 802.1x mac-based operational direction configuration\n * Input:\n *      vid - 802.1x guest VLAN ID\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameter.\n * Note:\n *      The operate controlled 802.1x guest VLAN\n */\nrtk_api_ret_t rtk_dot1x_guestVlan_set(rtk_vlan_t vid)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32 index;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* vid must be 0~4095 */\n    if (vid > RTL8367C_VIDMAX)\n        return RT_ERR_VLAN_VID;\n\n    if((retVal = rtk_vlan_checkAndCreateMbr(vid, &index)) != RT_ERR_OK)\n        return retVal;\n\n    if ((retVal = rtl8367c_setAsic1xGuestVidx(index)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_dot1x_guestVlan_get\n * Description:\n *      Get 802.1x guest VLAN configuration\n * Input:\n *      None\n * Output:\n *      pVid - 802.1x guest VLAN ID\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n * Note:\n *      The API can get 802.1x guest VLAN information.\n */\nrtk_api_ret_t rtk_dot1x_guestVlan_get(rtk_vlan_t *pVid)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32 gvidx;\n    rtl8367c_vlanconfiguser vlanMC;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(NULL == pVid)\n        return RT_ERR_NULL_POINTER;\n\n    if ((retVal = rtl8367c_getAsic1xGuestVidx(&gvidx)) != RT_ERR_OK)\n        return retVal;\n\n    if ((retVal = rtl8367c_getAsicVlanMemberConfig(gvidx, &vlanMC)) != RT_ERR_OK)\n        return retVal;\n\n    *pVid = vlanMC.evid;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_dot1x_guestVlan2Auth_set\n * Description:\n *      Set 802.1x guest VLAN to auth host configuration\n * Input:\n *      enable - The status of guest VLAN to auth host.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameter.\n * Note:\n *      The operational direction of 802.1x guest VLAN to auth host control is as following:\n *      - ENABLED\n *      - DISABLED\n */\nrtk_api_ret_t rtk_dot1x_guestVlan2Auth_set(rtk_enable_t enable)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if (enable >= RTK_ENABLE_END)\n        return RT_ERR_ENABLE;\n\n    if ((retVal = rtl8367c_setAsic1xGVOpdir(enable)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_dot1x_guestVlan2Auth_get\n * Description:\n *      Get 802.1x guest VLAN to auth host configuration\n * Input:\n *      None\n * Output:\n *      pEnable - The status of guest VLAN to auth host.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n * Note:\n *      The API can get 802.1x guest VLAN to auth host information.\n */\nrtk_api_ret_t rtk_dot1x_guestVlan2Auth_get(rtk_enable_t *pEnable)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(NULL == pEnable)\n        return RT_ERR_NULL_POINTER;\n\n    if ((retVal = rtl8367c_getAsic1xGVOpdir(pEnable)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/eee.c",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * $Revision: 48156 $\n * $Date: 2014-05-29 16:39:06 +0800 (週四, 29 五月 2014) $\n *\n * Purpose : RTK switch high-level API for RTL8367/RTL8367C\n * Feature : Here is a list of all functions and variables in EEE module.\n *\n */\n\n#include <rtk_switch.h>\n#include <rtk_error.h>\n#include <eee.h>\n#include <string.h>\n\n#include <rtl8367c_asicdrv.h>\n#include <rtl8367c_asicdrv_eee.h>\n#include <rtl8367c_asicdrv_phy.h>\n\n/* Function Name:\n *      rtk_eee_init\n * Description:\n *      EEE function initialization.\n * Input:\n *      None\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n * Note:\n *      This API is used to initialize EEE status.\n */\nrtk_api_ret_t rtk_eee_init(void)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if((retVal = rtl8367c_setAsicRegBit(0x0018, 10, 1)) != RT_ERR_OK)\n        return retVal;\n\n    if((retVal = rtl8367c_setAsicRegBit(0x0018, 11, 1)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_eee_portEnable_set\n * Description:\n *      Set enable status of EEE function.\n * Input:\n *      port - port id.\n *      enable - enable EEE status.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n *      RT_ERR_PORT_ID - Invalid port number.\n *      RT_ERR_ENABLE - Invalid enable input.\n * Note:\n *      This API can set EEE function to the specific port.\n *      The configuration of the port is as following:\n *      - DISABLE\n *      - ENABLE\n */\nrtk_api_ret_t rtk_eee_portEnable_set(rtk_port_t port, rtk_enable_t enable)\n{\n    rtk_api_ret_t   retVal;\n    rtk_uint32      regData;\n    rtk_uint32    phy_port;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check port is UTP port */\n    RTK_CHK_PORT_IS_UTP(port);\n\n    if (enable>=RTK_ENABLE_END)\n        return RT_ERR_INPUT;\n\n    phy_port = rtk_switch_port_L2P_get(port);\n\n    if ((retVal = rtl8367c_setAsicEee100M(phy_port,enable))!=RT_ERR_OK)\n        return retVal;\n    if ((retVal = rtl8367c_setAsicEeeGiga(phy_port,enable))!=RT_ERR_OK)\n        return retVal;\n\n    if ((retVal = rtl8367c_setAsicPHYReg(phy_port, RTL8367C_PHY_PAGE_ADDRESS, 0))!=RT_ERR_OK)\n        return retVal;\n    if ((retVal = rtl8367c_getAsicPHYReg(phy_port, 0, &regData))!=RT_ERR_OK)\n        return retVal;\n    regData |= 0x0200;\n    if ((retVal = rtl8367c_setAsicPHYReg(phy_port, 0, regData))!=RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_eee_portEnable_get\n * Description:\n *      Get enable status of EEE function\n * Input:\n *      port - Port id.\n * Output:\n *      pEnable - Back pressure status.\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n *      RT_ERR_PORT_ID - Invalid port number.\n * Note:\n *      This API can get EEE function to the specific port.\n *      The configuration of the port is as following:\n *      - DISABLE\n *      - ENABLE\n */\n\nrtk_api_ret_t rtk_eee_portEnable_get(rtk_port_t port, rtk_enable_t *pEnable)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32 regData1, regData2;\n    rtk_uint32    phy_port;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check port is UTP port */\n    RTK_CHK_PORT_IS_UTP(port);\n\n    if(NULL == pEnable)\n        return RT_ERR_NULL_POINTER;\n\n    phy_port = rtk_switch_port_L2P_get(port);\n\n    if ((retVal = rtl8367c_getAsicEee100M(phy_port,&regData1))!=RT_ERR_OK)\n        return retVal;\n    if ((retVal = rtl8367c_getAsicEeeGiga(phy_port,&regData2))!=RT_ERR_OK)\n        return retVal;\n\n    if (regData1==1&&regData2==1)\n        *pEnable = ENABLED;\n    else\n        *pEnable = DISABLED;\n\n    return RT_ERR_OK;\n}\n\n\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/i2c.c",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * $Revision: 63932 $\n * $Date: 2015-12-08 14:06:29 +0800 (周二, 08 十二月 2015) $\n *\n * Purpose : RTK switch high-level API for RTL8367/RTL8367C\n * Feature : Here is a list of all functions and variables in i2c module.\n *\n */\n\n#include <rtk_switch.h>\n#include <rtk_error.h>\n#include <port.h>\n#include <string.h>\n#include <rtl8367c_reg.h>\n\n#include <rtl8367c_asicdrv_i2c.h>\n#include <rtk_switch.h>\n#include <rtl8367c_asicdrv.h>\n#include <rtk_types.h>\n#include <i2c.h>\n\n\nstatic rtk_I2C_16bit_mode_t rtk_i2c_mode = I2C_LSB_16BIT_MODE;\n\n\n/* Function Name:\n *      rtk_i2c_init\n * Description:\n *      I2C smart function initialization.\n * Input:\n *      None\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n * Note:\n *      This API is used to initialize EEE status.\n *      need used GPIO pins\n *      OpenDrain and clock\n */\nrtk_api_ret_t rtk_i2c_init(void)\n{\n    rtk_uint32 retVal;\n  switch_chip_t ChipID;\n  /* probe switch */\n  if((retVal = rtk_switch_probe(&ChipID)) != RT_ERR_OK)\n      return retVal;\n\n  if( ChipID == CHIP_RTL8370B )\n  {\n   /*set GPIO8, GPIO9, OpenDrain as I2C, clock = 252KHZ   */\n      if((retVal = rtl8367c_setAsicReg(RTL8367C_REG_M_I2C_SYS_CTL, 0x5c3f)) != RT_ERR_OK)\n        return retVal;\n  }\n  else\n      return RT_ERR_FAILED;\n  return  RT_ERR_OK;\n}\n\n\n/* Function Name:\n *      rtk_i2c_mode_set\n * Description:\n *      Set I2C data byte-order.\n * Input:\n *      i2cmode - byte-order mode\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_INPUT        - Invalid input parameter.\n * Note:\n *      This API can set I2c traffic's byte-order .\n */\nrtk_api_ret_t rtk_i2c_mode_set( rtk_I2C_16bit_mode_t i2cmode )\n{\n    if(i2cmode >= I2C_Mode_END)\n    {\n        return RT_ERR_INPUT;\n    }\n    else if(i2cmode == I2C_70B_LSB_16BIT_MODE)\n    {\n        rtk_i2c_mode = I2C_70B_LSB_16BIT_MODE;\n\n        return RT_ERR_OK;\n    }\n    else if( i2cmode == I2C_LSB_16BIT_MODE)\n    {\n        rtk_i2c_mode = I2C_LSB_16BIT_MODE;\n        return RT_ERR_OK;\n    }\n    else\n        return RT_ERR_FAILED;\n\n    return RT_ERR_OK;\n}\n\n\n/* Function Name:\n *      rtk_i2c_mode_get\n * Description:\n *      Get i2c traffic byte-order setting.\n * Input:\n *      None\n * Output:\n *      pI2cMode - i2c byte-order\n * Return:\n *      RT_ERR_OK               - OK\n *      RT_ERR_FAILED           - Failed\n *      RT_ERR_NULL_POINTER     - input parameter is null pointer\n * Note:\n *      The API can get i2c traffic byte-order setting.\n */\nrtk_api_ret_t rtk_i2c_mode_get( rtk_I2C_16bit_mode_t * pI2cMode)\n{\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n    if(NULL == pI2cMode)\n        return RT_ERR_NULL_POINTER;\n    if(rtk_i2c_mode == I2C_70B_LSB_16BIT_MODE)\n        *pI2cMode = 1;\n    else if ((rtk_i2c_mode == I2C_LSB_16BIT_MODE))\n        *pI2cMode = 0;\n    else\n        return RT_ERR_FAILED;\n    return RT_ERR_OK;\n}\n\n\n/* Function Name:\n *      rtk_i2c_gpioPinGroup_set\n * Description:\n *      Set i2c SDA & SCL used GPIO pins group.\n * Input:\n *      pins_group - GPIO pins group\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - OK\n *      RT_ERR_FAILED           - Failed\n *      RT_ERR_INPUT        - Invalid input parameter.\n * Note:\n *      The API can set i2c used gpio pins group.\n *      There are three group pins could be used\n */\nrtk_api_ret_t rtk_i2c_gpioPinGroup_set( rtk_I2C_gpio_pin_t pins_group )\n{\n    rtk_uint32 retVal;\n\n\n    if( ( pins_group > I2C_GPIO_PIN_END )|| ( pins_group < I2C_GPIO_PIN_8_9) )\n        return RT_ERR_INPUT;\n\n    if( (retVal = rtl8367c_setAsicI2CGpioPinGroup(pins_group) ) != RT_ERR_OK )\n        return retVal ;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_i2c_gpioPinGroup_get\n * Description:\n *      Get i2c SDA & SCL used GPIO pins group.\n * Input:\n *      None\n * Output:\n *      pPins_group - GPIO pins group\n * Return:\n *      RT_ERR_OK               - OK\n *      RT_ERR_NULL_POINTER     - input parameter is null pointer\n * Note:\n *      The API can get i2c used gpio pins group.\n *      There are three group pins could be used\n */\nrtk_api_ret_t rtk_i2c_gpioPinGroup_get( rtk_I2C_gpio_pin_t * pPins_group )\n{\n    rtk_uint32 retVal;\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(NULL == pPins_group)\n        return RT_ERR_NULL_POINTER;\n    if( (retVal = rtl8367c_getAsicI2CGpioPinGroup(pPins_group) ) != RT_ERR_OK )\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_i2c_data_read\n * Description:\n *      read i2c slave device register.\n * Input:\n *      deviceAddr   -   access Slave device address\n *      slaveRegAddr -   access Slave register address\n * Output:\n *      pRegData     -   read data\n * Return:\n *      RT_ERR_OK               - OK\n *      RT_ERR_NULL_POINTER     - input parameter is null pointer\n * Note:\n *      The API can access i2c slave and read i2c slave device register.\n */\nrtk_api_ret_t rtk_i2c_data_read(rtk_uint8 deviceAddr, rtk_uint32 slaveRegAddr, rtk_uint32 *pRegData)\n{\n     rtk_uint32 retVal, counter=0;\n     rtk_uint8 controlByte_W, controlByte_R;\n     rtk_uint8 slaveRegAddr_L, slaveRegAddr_H = 0x0, temp;\n     rtk_uint8 regData_L, regData_H;\n\n   /* control byte :deviceAddress + W,  deviceAddress + R   */\n    controlByte_W = (rtk_uint8)(deviceAddr << 1) ;\n    controlByte_R = (rtk_uint8)(controlByte_W | 0x1);\n\n    slaveRegAddr_L = (rtk_uint8) (slaveRegAddr & 0x00FF) ;\n    slaveRegAddr_H = (rtk_uint8) (slaveRegAddr >>8) ;\n\n    if( rtk_i2c_mode == I2C_70B_LSB_16BIT_MODE)\n    {\n        temp = slaveRegAddr_L ;\n        slaveRegAddr_L = slaveRegAddr_H;\n        slaveRegAddr_H = temp;\n    }\n\n\n  /*check bus state: idle*/\n  for(counter = 3000; counter>0; counter--)\n  {\n    if ( (retVal = rtl8367c_setAsicI2C_checkBusIdle() ) == RT_ERR_OK)\n         break;\n  }\n  if( counter ==0 )\n      return retVal; /*i2c is busy*/\n\n   /*tx Start cmd*/\n   if( (retVal = rtl8367c_setAsicI2CStartCmd() ) != RT_ERR_OK )\n       return retVal ;\n\n\n  /*tx control _W*/\n   if( (retVal = rtl8367c_setAsicI2CTxOneCharCmd(controlByte_W))!= RT_ERR_OK )\n      return retVal ;\n\n\n  /*check if RX ack from slave*/\n   if( (retVal = rtl8367c_setAsicI2CcheckRxAck()) != RT_ERR_OK )\n        return retVal;\n\n    /* tx slave buffer address low 8 bits */\n   if( (retVal = rtl8367c_setAsicI2CTxOneCharCmd(slaveRegAddr_L))!= RT_ERR_OK )\n         return retVal  ;\n\n   /*check if RX ack from slave*/\n   if( (retVal = rtl8367c_setAsicI2CcheckRxAck()) != RT_ERR_OK )\n        return retVal;\n\n\n\n        /* tx slave buffer address high 8 bits */\n   if( (retVal = rtl8367c_setAsicI2CTxOneCharCmd(slaveRegAddr_H))!= RT_ERR_OK )\n         return retVal  ;\n\n\n   /*check if RX ack from slave*/\n   if( (retVal = rtl8367c_setAsicI2CcheckRxAck()) != RT_ERR_OK )\n        return retVal;\n\n\n   /*tx Start cmd*/\n   if( (retVal = rtl8367c_setAsicI2CStartCmd() ) != RT_ERR_OK )\n       return retVal ;\n\n      /*tx control _R*/\n   if( (retVal = rtl8367c_setAsicI2CTxOneCharCmd(controlByte_R))!= RT_ERR_OK )\n       return retVal ;\n\n\n  /*check if RX ack from slave*/\n   if( (retVal = rtl8367c_setAsicI2CcheckRxAck()) != RT_ERR_OK )\n        return retVal;\n\n\n    /* rx low 8bit data*/\n   if( ( retVal = rtl8367c_setAsicI2CRxOneCharCmd( &regData_L) ) != RT_ERR_OK )\n        return retVal;\n\n\n\n    /* tx ack to slave, keep receive */\n    if( (retVal = rtl8367c_setAsicI2CTxAckCmd()) != RT_ERR_OK )\n        return retVal;\n\n     /* rx high 8bit data*/\n    if( ( retVal = rtl8367c_setAsicI2CRxOneCharCmd( &regData_H) ) != RT_ERR_OK )\n        return retVal;\n\n\n\n    /* tx Noack to slave, Stop receive */\n     if( (retVal = rtl8367c_setAsicI2CTxNoAckCmd()) != RT_ERR_OK )\n        return retVal;\n\n\n    /*tx Stop cmd */\n    if( (retVal = rtl8367c_setAsicI2CStopCmd()) != RT_ERR_OK )\n        return retVal;\n\n    *pRegData = (regData_H << 8) | regData_L;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_i2c_data_write\n * Description:\n *      write data to i2c slave device register\n * Input:\n *      deviceAddr   -   access Slave device address\n *      slaveRegAddr -   access Slave register address\n *      regData      -   data to set\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - OK\n * Note:\n *      The API can access i2c slave and setting i2c slave device register.\n */\nrtk_api_ret_t rtk_i2c_data_write(rtk_uint8 deviceAddr, rtk_uint32 slaveRegAddr, rtk_uint32 regData)\n{\n     rtk_uint32 retVal,counter;\n     rtk_uint8 controlByte_W;\n     rtk_uint8 slaveRegAddr_L, slaveRegAddr_H = 0x0, temp;\n     rtk_uint8 regData_L, regData_H;\n\n  /* control byte :deviceAddress + W    */\n    controlByte_W = (rtk_uint8)(deviceAddr<< 1) ;\n\n    slaveRegAddr_L = (rtk_uint8) (slaveRegAddr & 0x00FF) ;\n    slaveRegAddr_H = (rtk_uint8) (slaveRegAddr >>8) ;\n\n    regData_H   = (rtk_uint8) (regData>> 8);\n    regData_L   = (rtk_uint8) (regData & 0x00FF);\n\n    if( rtk_i2c_mode == I2C_70B_LSB_16BIT_MODE)\n    {\n        temp = slaveRegAddr_L ;\n        slaveRegAddr_L = slaveRegAddr_H;\n        slaveRegAddr_H = temp;\n    }\n\n\n  /*check bus state: idle*/\n  for(counter = 3000; counter>0; counter--)\n  {\n    if ( (retVal = rtl8367c_setAsicI2C_checkBusIdle() ) == RT_ERR_OK)\n        break;\n  }\n\n  if( counter ==0 )\n      return retVal; /*i2c is busy*/\n\n\n   /*tx Start cmd*/\n   if( (retVal = rtl8367c_setAsicI2CStartCmd() ) != RT_ERR_OK )\n       return retVal ;\n\n\n  /*tx control _W*/\n   if( (retVal = rtl8367c_setAsicI2CTxOneCharCmd(controlByte_W))!= RT_ERR_OK )\n      return retVal ;\n\n\n  /*check if RX ack from slave*/\n   if( (retVal = rtl8367c_setAsicI2CcheckRxAck()) != RT_ERR_OK )\n        return retVal;\n\n\n    /* tx slave buffer address low 8 bits */\n   if( (retVal = rtl8367c_setAsicI2CTxOneCharCmd(slaveRegAddr_L))!= RT_ERR_OK )\n        return retVal;\n\n\n   /*check if RX ack from slave*/\n   if( (retVal = rtl8367c_setAsicI2CcheckRxAck()) != RT_ERR_OK )\n        return retVal;\n\n\n   /* tx slave buffer address high 8 bits */\n   if( (retVal = rtl8367c_setAsicI2CTxOneCharCmd(slaveRegAddr_H))!= RT_ERR_OK )\n        return retVal;\n\n\n   /*check if RX ack from slave*/\n   if( (retVal = rtl8367c_setAsicI2CcheckRxAck()) != RT_ERR_OK )\n        return retVal;\n\n\n     /*tx Datavlue LSB*/\n   if( (retVal = rtl8367c_setAsicI2CTxOneCharCmd(regData_L))!= RT_ERR_OK )\n        return retVal;\n\n\n   /*check if RX ack from slave*/\n   if( (retVal = rtl8367c_setAsicI2CcheckRxAck()) != RT_ERR_OK )\n        return retVal;\n\n\n   /*tx Datavlue MSB*/\n   if( (retVal = rtl8367c_setAsicI2CTxOneCharCmd(regData_H))!= RT_ERR_OK )\n        return retVal;\n\n\n   /*check if RX ack from slave*/\n   if( (retVal = rtl8367c_setAsicI2CcheckRxAck()) != RT_ERR_OK )\n        return retVal;\n\n\n    /*tx Stop cmd */\n    if( (retVal = rtl8367c_setAsicI2CStopCmd()) != RT_ERR_OK )\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n\n\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/igmp.c",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * $Revision: 76306 $\n * $Date: 2017-03-08 15:13:58 +0800 (週三, 08 三月 2017) $\n *\n * Purpose : RTK switch high-level API for RTL8367/RTL8367C\n * Feature : Here is a list of all functions and variables in IGMP module.\n *\n */\n\n#include <rtk_switch.h>\n#include <rtk_error.h>\n#include <igmp.h>\n#include <string.h>\n\n#include <rtl8367c_asicdrv.h>\n#include <rtl8367c_asicdrv_igmp.h>\n#include <rtl8367c_asicdrv_lut.h>\n\n\n/* Function Name:\n *      rtk_igmp_init\n * Description:\n *      This API enables H/W IGMP and set a default initial configuration.\n * Input:\n *      None.\n * Output:\n *      None.\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n * Note:\n *      This API enables H/W IGMP and set a default initial configuration.\n */\nrtk_api_ret_t rtk_igmp_init(void)\n{\n    rtk_api_ret_t retVal;\n    rtk_port_t port;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if ((retVal = rtl8367c_setAsicLutIpMulticastLookup(ENABLED))!=RT_ERR_OK)\n        return retVal;\n\n    if ((retVal = rtl8367c_setAsicLutIpLookupMethod(1))!=RT_ERR_OK)\n        return retVal;\n\n    RTK_SCAN_ALL_PHY_PORTMASK(port)\n    {\n        if ((retVal = rtl8367c_setAsicIGMPv1Opeartion(port, PROTOCOL_OP_ASIC))!=RT_ERR_OK)\n            return retVal;\n\n        if ((retVal = rtl8367c_setAsicIGMPv2Opeartion(port, PROTOCOL_OP_ASIC))!=RT_ERR_OK)\n            return retVal;\n\n        if ((retVal = rtl8367c_setAsicIGMPv3Opeartion(port, PROTOCOL_OP_FLOOD))!=RT_ERR_OK)\n            return retVal;\n\n        if ((retVal = rtl8367c_setAsicMLDv1Opeartion(port, PROTOCOL_OP_ASIC))!=RT_ERR_OK)\n            return retVal;\n\n        if ((retVal = rtl8367c_setAsicMLDv2Opeartion(port, PROTOCOL_OP_FLOOD))!=RT_ERR_OK)\n            return retVal;\n    }\n\n    if ((retVal = rtl8367c_setAsicIGMPAllowDynamicRouterPort(rtk_switch_phyPortMask_get()))!=RT_ERR_OK)\n        return retVal;\n\n    if ((retVal = rtl8367c_setAsicIGMPFastLeaveEn(ENABLED))!=RT_ERR_OK)\n        return retVal;\n\n    if ((retVal = rtl8367c_setAsicIGMPReportLeaveFlood(1))!=RT_ERR_OK)\n        return retVal;\n\n    if ((retVal = rtl8367c_setAsicIgmp(ENABLED))!=RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_igmp_state_set\n * Description:\n *      This API set H/W IGMP state.\n * Input:\n *      enabled     - H/W IGMP state\n * Output:\n *      None.\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n *      RT_ERR_INPUT           - Error parameter\n * Note:\n *      This API set H/W IGMP state.\n */\nrtk_api_ret_t rtk_igmp_state_set(rtk_enable_t enabled)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if (enabled >= RTK_ENABLE_END)\n        return RT_ERR_INPUT;\n\n    if ((retVal = rtl8367c_setAsicIgmp(enabled))!=RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_igmp_state_get\n * Description:\n *      This API get H/W IGMP state.\n * Input:\n *      None.\n * Output:\n *      pEnabled        - H/W IGMP state\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n *      RT_ERR_INPUT           - Error parameter\n * Note:\n *      This API set current H/W IGMP state.\n */\nrtk_api_ret_t rtk_igmp_state_get(rtk_enable_t *pEnabled)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(pEnabled == NULL)\n        return RT_ERR_NULL_POINTER;\n\n    if ((retVal = rtl8367c_getAsicIgmp(pEnabled))!=RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_igmp_static_router_port_set\n * Description:\n *      Configure static router port\n * Input:\n *      pPortmask    - Static Port mask\n * Output:\n *      None.\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n *      RT_ERR_PORT_MASK       - Error parameter\n * Note:\n *      This API set static router port\n */\nrtk_api_ret_t rtk_igmp_static_router_port_set(rtk_portmask_t *pPortmask)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32 pmask;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check Valid port mask */\n    if(pPortmask == NULL)\n        return RT_ERR_NULL_POINTER;\n\n    RTK_CHK_PORTMASK_VALID(pPortmask);\n\n    if ((retVal = rtk_switch_portmask_L2P_get(pPortmask, &pmask))!=RT_ERR_OK)\n        return retVal;\n\n    if ((retVal = rtl8367c_setAsicIGMPStaticRouterPort(pmask))!=RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_igmp_static_router_port_get\n * Description:\n *      Get static router port\n * Input:\n *      None.\n * Output:\n *      pPortmask       - Static port mask\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n *      RT_ERR_PORT_MASK       - Error parameter\n * Note:\n *      This API get static router port\n */\nrtk_api_ret_t rtk_igmp_static_router_port_get(rtk_portmask_t *pPortmask)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32 pmask;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(pPortmask == NULL)\n        return RT_ERR_NULL_POINTER;\n\n    if ((retVal = rtl8367c_getAsicIGMPStaticRouterPort(&pmask))!=RT_ERR_OK)\n        return retVal;\n\n    if ((retVal = rtk_switch_portmask_P2L_get(pmask, pPortmask))!=RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_igmp_protocol_set\n * Description:\n *      set IGMP/MLD protocol action\n * Input:\n *      port        - Port ID\n *      protocol    - IGMP/MLD protocol\n *      action      - Per-port and per-protocol IGMP action seeting\n * Output:\n *      None.\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n *      RT_ERR_PORT_MASK       - Error parameter\n * Note:\n *      This API set IGMP/MLD protocol action\n */\nrtk_api_ret_t rtk_igmp_protocol_set(rtk_port_t port, rtk_igmp_protocol_t protocol, rtk_igmp_action_t action)\n{\n    rtk_uint32      operation;\n    rtk_api_ret_t   retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check port valid */\n    RTK_CHK_PORT_VALID(port);\n\n    if(protocol >= PROTOCOL_END)\n        return RT_ERR_INPUT;\n\n    if(action >= IGMP_ACTION_END)\n        return RT_ERR_INPUT;\n\n    switch(action)\n    {\n        case IGMP_ACTION_FORWARD:\n            operation = PROTOCOL_OP_FLOOD;\n            break;\n        case IGMP_ACTION_TRAP2CPU:\n            operation = PROTOCOL_OP_TRAP;\n            break;\n        case IGMP_ACTION_DROP:\n            operation = PROTOCOL_OP_DROP;\n            break;\n        case IGMP_ACTION_ASIC:\n            operation = PROTOCOL_OP_ASIC;\n            break;\n        default:\n            return RT_ERR_INPUT;\n    }\n\n    switch(protocol)\n    {\n        case PROTOCOL_IGMPv1:\n            if ((retVal = rtl8367c_setAsicIGMPv1Opeartion(rtk_switch_port_L2P_get(port), operation))!=RT_ERR_OK)\n                return retVal;\n\n            break;\n        case PROTOCOL_IGMPv2:\n            if ((retVal = rtl8367c_setAsicIGMPv2Opeartion(rtk_switch_port_L2P_get(port), operation))!=RT_ERR_OK)\n                return retVal;\n\n            break;\n        case PROTOCOL_IGMPv3:\n            if ((retVal = rtl8367c_setAsicIGMPv3Opeartion(rtk_switch_port_L2P_get(port), operation))!=RT_ERR_OK)\n                return retVal;\n\n            break;\n        case PROTOCOL_MLDv1:\n            if ((retVal = rtl8367c_setAsicMLDv1Opeartion(rtk_switch_port_L2P_get(port), operation))!=RT_ERR_OK)\n                return retVal;\n\n            break;\n        case PROTOCOL_MLDv2:\n            if ((retVal = rtl8367c_setAsicMLDv2Opeartion(rtk_switch_port_L2P_get(port), operation))!=RT_ERR_OK)\n                return retVal;\n\n            break;\n        default:\n            return RT_ERR_INPUT;\n\n    }\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_igmp_protocol_get\n * Description:\n *      set IGMP/MLD protocol action\n * Input:\n *      port        - Port ID\n *      protocol    - IGMP/MLD protocol\n *      action      - Per-port and per-protocol IGMP action seeting\n * Output:\n *      None.\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n *      RT_ERR_PORT_MASK       - Error parameter\n * Note:\n *      This API set IGMP/MLD protocol action\n */\nrtk_api_ret_t rtk_igmp_protocol_get(rtk_port_t port, rtk_igmp_protocol_t protocol, rtk_igmp_action_t *pAction)\n{\n    rtk_uint32      operation;\n    rtk_api_ret_t   retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check port valid */\n    RTK_CHK_PORT_VALID(port);\n\n    if(protocol >= PROTOCOL_END)\n        return RT_ERR_INPUT;\n\n    if(pAction == NULL)\n        return RT_ERR_NULL_POINTER;\n\n    switch(protocol)\n    {\n        case PROTOCOL_IGMPv1:\n            if ((retVal = rtl8367c_getAsicIGMPv1Opeartion(rtk_switch_port_L2P_get(port), &operation))!=RT_ERR_OK)\n                return retVal;\n\n            break;\n        case PROTOCOL_IGMPv2:\n            if ((retVal = rtl8367c_getAsicIGMPv2Opeartion(rtk_switch_port_L2P_get(port), &operation))!=RT_ERR_OK)\n                return retVal;\n\n            break;\n        case PROTOCOL_IGMPv3:\n            if ((retVal = rtl8367c_getAsicIGMPv3Opeartion(rtk_switch_port_L2P_get(port), &operation))!=RT_ERR_OK)\n                return retVal;\n\n            break;\n        case PROTOCOL_MLDv1:\n            if ((retVal = rtl8367c_getAsicMLDv1Opeartion(rtk_switch_port_L2P_get(port), &operation))!=RT_ERR_OK)\n                return retVal;\n\n            break;\n        case PROTOCOL_MLDv2:\n            if ((retVal = rtl8367c_getAsicMLDv2Opeartion(rtk_switch_port_L2P_get(port), &operation))!=RT_ERR_OK)\n                return retVal;\n\n            break;\n        default:\n            return RT_ERR_INPUT;\n\n    }\n\n    switch(operation)\n    {\n        case PROTOCOL_OP_FLOOD:\n            *pAction = IGMP_ACTION_FORWARD;\n            break;\n        case PROTOCOL_OP_TRAP:\n            *pAction = IGMP_ACTION_TRAP2CPU;\n            break;\n        case PROTOCOL_OP_DROP:\n            *pAction = IGMP_ACTION_DROP;\n            break;\n        case PROTOCOL_OP_ASIC:\n            *pAction = IGMP_ACTION_ASIC;\n            break;\n        default:\n            return RT_ERR_FAILED;\n    }\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_igmp_fastLeave_set\n * Description:\n *      set IGMP/MLD FastLeave state\n * Input:\n *      state       - ENABLED: Enable FastLeave, DISABLED: disable FastLeave\n * Output:\n *      None.\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_INPUT           - Error Input\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n * Note:\n *      This API set IGMP/MLD FastLeave state\n */\nrtk_api_ret_t rtk_igmp_fastLeave_set(rtk_enable_t state)\n{\n    rtk_api_ret_t   retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(state >= RTK_ENABLE_END)\n        return RT_ERR_INPUT;\n\n    if ((retVal = rtl8367c_setAsicIGMPFastLeaveEn((rtk_uint32)state))!=RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_igmp_fastLeave_get\n * Description:\n *      get IGMP/MLD FastLeave state\n * Input:\n *      None\n * Output:\n *      pState      - ENABLED: Enable FastLeave, DISABLED: disable FastLeave\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_NULL_POINTER    - NULL pointer\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n * Note:\n *      This API get IGMP/MLD FastLeave state\n */\nrtk_api_ret_t rtk_igmp_fastLeave_get(rtk_enable_t *pState)\n{\n    rtk_uint32      fast_leave;\n    rtk_api_ret_t   retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(pState == NULL)\n        return RT_ERR_NULL_POINTER;\n\n    if ((retVal = rtl8367c_getAsicIGMPFastLeaveEn(&fast_leave))!=RT_ERR_OK)\n        return retVal;\n\n    *pState = ((fast_leave == 1) ? ENABLED : DISABLED);\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_igmp_maxGroup_set\n * Description:\n *      Set per port multicast group learning limit.\n * Input:\n *      port        - Port ID\n *      group       - The number of multicast group learning limit.\n * Output:\n *      None.\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_PORT_ID         - Error Port ID\n *      RT_ERR_OUT_OF_RANGE    - parameter out of range\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n * Note:\n *      This API set per port multicast group learning limit.\n */\nrtk_api_ret_t rtk_igmp_maxGroup_set(rtk_port_t port, rtk_uint32 group)\n{\n    rtk_api_ret_t   retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check port valid */\n    RTK_CHK_PORT_VALID(port);\n\n    if(group > RTL8367C_IGMP_MAX_GOUP)\n        return RT_ERR_OUT_OF_RANGE;\n\n    if ((retVal = rtl8367c_setAsicIGMPPortMAXGroup(rtk_switch_port_L2P_get(port), group))!=RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_igmp_maxGroup_get\n * Description:\n *      Get per port multicast group learning limit.\n * Input:\n *      port        - Port ID\n * Output:\n *      pGroup      - The number of multicast group learning limit.\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_PORT_ID         - Error Port ID\n *      RT_ERR_NULL_POINTER    - Null pointer\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n * Note:\n *      This API get per port multicast group learning limit.\n */\nrtk_api_ret_t rtk_igmp_maxGroup_get(rtk_port_t port, rtk_uint32 *pGroup)\n{\n    rtk_api_ret_t   retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check port valid */\n    RTK_CHK_PORT_VALID(port);\n\n    if(pGroup == NULL)\n        return RT_ERR_NULL_POINTER;\n\n    if ((retVal = rtl8367c_getAsicIGMPPortMAXGroup(rtk_switch_port_L2P_get(port), pGroup))!=RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_igmp_currentGroup_get\n * Description:\n *      Get per port multicast group learning count.\n * Input:\n *      port        - Port ID\n * Output:\n *      pGroup      - The number of multicast group learning count.\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_PORT_ID         - Error Port ID\n *      RT_ERR_NULL_POINTER    - Null pointer\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n * Note:\n *      This API get per port multicast group learning count.\n */\nrtk_api_ret_t rtk_igmp_currentGroup_get(rtk_port_t port, rtk_uint32 *pGroup)\n{\n    rtk_api_ret_t   retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check port valid */\n    RTK_CHK_PORT_VALID(port);\n\n    if(pGroup == NULL)\n        return RT_ERR_NULL_POINTER;\n\n    if ((retVal = rtl8367c_getAsicIGMPPortCurrentGroup(rtk_switch_port_L2P_get(port), pGroup))!=RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_igmp_tableFullAction_set\n * Description:\n *      set IGMP/MLD Table Full Action\n * Input:\n *      action      - Table Full Action\n * Output:\n *      None.\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_INPUT           - Error Input\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n * Note:\n */\nrtk_api_ret_t rtk_igmp_tableFullAction_set(rtk_igmp_tableFullAction_t action)\n{\n    rtk_api_ret_t   retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(action >= IGMP_TABLE_FULL_OP_END)\n        return RT_ERR_INPUT;\n\n    if ((retVal = rtl8367c_setAsicIGMPTableFullOP((rtk_uint32)action))!=RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_igmp_tableFullAction_get\n * Description:\n *      get IGMP/MLD Table Full Action\n * Input:\n *      None\n * Output:\n *      pAction     - Table Full Action\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_NULL_POINTER    - Null pointer\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n * Note:\n */\nrtk_api_ret_t rtk_igmp_tableFullAction_get(rtk_igmp_tableFullAction_t *pAction)\n{\n    rtk_api_ret_t   retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(NULL == pAction)\n        return RT_ERR_NULL_POINTER;\n\n    if ((retVal = rtl8367c_getAsicIGMPTableFullOP((rtk_uint32 *)pAction))!=RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_igmp_checksumErrorAction_set\n * Description:\n *      set IGMP/MLD Checksum Error Action\n * Input:\n *      action      - Checksum error Action\n * Output:\n *      None.\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_INPUT           - Error Input\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n * Note:\n */\nrtk_api_ret_t rtk_igmp_checksumErrorAction_set(rtk_igmp_checksumErrorAction_t action)\n{\n    rtk_api_ret_t   retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(action >= IGMP_CRC_ERR_OP_END)\n        return RT_ERR_INPUT;\n\n    if ((retVal = rtl8367c_setAsicIGMPCRCErrOP((rtk_uint32)action))!=RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n\n/* Function Name:\n *      rtk_igmp_checksumErrorAction_get\n * Description:\n *      get IGMP/MLD Checksum Error Action\n * Input:\n *      None\n * Output:\n *      pAction     - Checksum error Action\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_NULL_POINTER    - Null pointer\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n * Note:\n */\nrtk_api_ret_t rtk_igmp_checksumErrorAction_get(rtk_igmp_checksumErrorAction_t *pAction)\n{\n    rtk_api_ret_t   retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(NULL == pAction)\n        return RT_ERR_NULL_POINTER;\n\n    if ((retVal = rtl8367c_getAsicIGMPCRCErrOP((rtk_uint32 *)pAction))!=RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_igmp_leaveTimer_set\n * Description:\n *      set IGMP/MLD Leave timer\n * Input:\n *      timer       - Leave timer\n * Output:\n *      None.\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_INPUT           - Error Input\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n * Note:\n */\nrtk_api_ret_t rtk_igmp_leaveTimer_set(rtk_uint32 timer)\n{\n    rtk_api_ret_t   retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(timer > RTL8367C_MAX_LEAVE_TIMER)\n        return RT_ERR_INPUT;\n\n    if ((retVal = rtl8367c_setAsicIGMPLeaveTimer(timer))!=RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_igmp_leaveTimer_get\n * Description:\n *      get IGMP/MLD Leave timer\n * Input:\n *      None\n * Output:\n *      pTimer      - Leave Timer.\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_NULL_POINTER    - Null pointer\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n * Note:\n */\nrtk_api_ret_t rtk_igmp_leaveTimer_get(rtk_uint32 *pTimer)\n{\n    rtk_api_ret_t   retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(NULL == pTimer)\n        return RT_ERR_NULL_POINTER;\n\n    if ((retVal = rtl8367c_getAsicIGMPLeaveTimer(pTimer))!=RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_igmp_queryInterval_set\n * Description:\n *      set IGMP/MLD Query Interval\n * Input:\n *      interval     - Query Interval\n * Output:\n *      None.\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_INPUT           - Error Input\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n * Note:\n */\nrtk_api_ret_t rtk_igmp_queryInterval_set(rtk_uint32 interval)\n{\n    rtk_api_ret_t   retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(interval > RTL8367C_MAX_QUERY_INT)\n        return RT_ERR_INPUT;\n\n    if ((retVal = rtl8367c_setAsicIGMPQueryInterval(interval))!=RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_igmp_queryInterval_get\n * Description:\n *      get IGMP/MLD Query Interval\n * Input:\n *      None.\n * Output:\n *      pInterval   - Query Interval\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_NULL_POINTER    - Null pointer\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n * Note:\n */\nrtk_api_ret_t rtk_igmp_queryInterval_get(rtk_uint32 *pInterval)\n{\n    rtk_api_ret_t   retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(NULL == pInterval)\n        return RT_ERR_NULL_POINTER;\n\n    if ((retVal = rtl8367c_getAsicIGMPQueryInterval(pInterval))!=RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_igmp_robustness_set\n * Description:\n *      set IGMP/MLD Robustness value\n * Input:\n *      robustness     - Robustness value\n * Output:\n *      None.\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_INPUT           - Error Input\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n * Note:\n */\nrtk_api_ret_t rtk_igmp_robustness_set(rtk_uint32 robustness)\n{\n    rtk_api_ret_t   retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(robustness > RTL8367C_MAX_ROB_VAR)\n        return RT_ERR_INPUT;\n\n    if ((retVal = rtl8367c_setAsicIGMPRobVar(robustness))!=RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_igmp_robustness_get\n * Description:\n *      get IGMP/MLD Robustness value\n * Input:\n *      None\n * Output:\n *      pRobustness     - Robustness value.\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_NULL_POINTER    - Null pointer\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n * Note:\n */\nrtk_api_ret_t rtk_igmp_robustness_get(rtk_uint32 *pRobustness)\n{\n    rtk_api_ret_t   retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(NULL == pRobustness)\n        return RT_ERR_NULL_POINTER;\n\n    if ((retVal = rtl8367c_getAsicIGMPRobVar(pRobustness))!=RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_igmp_dynamicRouterRortAllow_set\n * Description:\n *      Configure dynamic router port allow option\n * Input:\n *      pPortmask    - Dynamic Port allow mask\n * Output:\n *      None.\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n *      RT_ERR_PORT_MASK       - Error parameter\n * Note:\n *\n */\nrtk_api_ret_t rtk_igmp_dynamicRouterPortAllow_set(rtk_portmask_t *pPortmask)\n{\n    rtk_api_ret_t   retVal;\n    rtk_uint32 pmask;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(NULL == pPortmask)\n        return RT_ERR_NULL_POINTER;\n\n    RTK_CHK_PORTMASK_VALID(pPortmask);\n\n    if ((retVal = rtk_switch_portmask_L2P_get(pPortmask, &pmask))!=RT_ERR_OK)\n        return retVal;\n\n    if ((retVal = rtl8367c_setAsicIGMPAllowDynamicRouterPort(pmask))!=RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_igmp_dynamicRouterRortAllow_get\n * Description:\n *      Get dynamic router port allow option\n * Input:\n *      None.\n * Output:\n *      pPortmask    - Dynamic Port allow mask\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_NULL_POINTER    - Null pointer\n *      RT_ERR_SMI             - SMI access error\n *      RT_ERR_PORT_MASK       - Error parameter\n * Note:\n *\n */\nrtk_api_ret_t rtk_igmp_dynamicRouterPortAllow_get(rtk_portmask_t *pPortmask)\n{\n    rtk_api_ret_t   retVal;\n    rtk_uint32 pmask;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(NULL == pPortmask)\n        return RT_ERR_NULL_POINTER;\n\n    if ((retVal = rtl8367c_getAsicIGMPAllowDynamicRouterPort(&pmask))!=RT_ERR_OK)\n        return retVal;\n\n    if ((retVal = rtk_switch_portmask_P2L_get(pmask, pPortmask))!=RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_igmp_dynamicRouterPort_get\n * Description:\n *      Get dynamic router port\n * Input:\n *      None.\n * Output:\n *      pDynamicRouterPort    - Dynamic Router Port\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_NULL_POINTER    - Null pointer\n *      RT_ERR_SMI             - SMI access error\n *      RT_ERR_PORT_MASK       - Error parameter\n * Note:\n *\n */\nrtk_api_ret_t rtk_igmp_dynamicRouterPort_get(rtk_igmp_dynamicRouterPort_t *pDynamicRouterPort)\n{\n    rtk_api_ret_t   retVal;\n    rtk_uint32 port;\n    rtk_uint32 timer;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(NULL == pDynamicRouterPort)\n        return RT_ERR_NULL_POINTER;\n\n    if ((retVal = rtl8367c_getAsicIGMPdynamicRouterPort1(&port, &timer))!= RT_ERR_OK)\n        return retVal;\n\n    if (port == RTL8367C_ROUTER_PORT_INVALID)\n    {\n        pDynamicRouterPort->dynamicRouterPort0Valid = DISABLED;\n        pDynamicRouterPort->dynamicRouterPort0      = 0;\n        pDynamicRouterPort->dynamicRouterPort0Timer = 0;\n    }\n    else\n    {\n        pDynamicRouterPort->dynamicRouterPort0Valid = ENABLED;\n        pDynamicRouterPort->dynamicRouterPort0      = rtk_switch_port_P2L_get(port);\n        pDynamicRouterPort->dynamicRouterPort0Timer = timer;\n    }\n\n    if ((retVal = rtl8367c_getAsicIGMPdynamicRouterPort2(&port, &timer))!= RT_ERR_OK)\n        return retVal;\n\n    if (port == RTL8367C_ROUTER_PORT_INVALID)\n    {\n        pDynamicRouterPort->dynamicRouterPort1Valid = DISABLED;\n        pDynamicRouterPort->dynamicRouterPort1      = 0;\n        pDynamicRouterPort->dynamicRouterPort1Timer = 0;\n    }\n    else\n    {\n        pDynamicRouterPort->dynamicRouterPort1Valid = ENABLED;\n        pDynamicRouterPort->dynamicRouterPort1      = rtk_switch_port_P2L_get(port);\n        pDynamicRouterPort->dynamicRouterPort1Timer = timer;\n    }\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_igmp_suppressionEnable_set\n * Description:\n *      Configure IGMPv1/v2 & MLDv1 Report/Leave/Done suppression\n * Input:\n *      reportSuppression   - Report suppression\n *      leaveSuppression    - Leave suppression\n * Output:\n *      None.\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n *      RT_ERR_INPUT           - Error Input\n * Note:\n *\n */\nrtk_api_ret_t rtk_igmp_suppressionEnable_set(rtk_enable_t reportSuppression, rtk_enable_t leaveSuppression)\n{\n    rtk_api_ret_t   retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(reportSuppression >= RTK_ENABLE_END)\n        return RT_ERR_INPUT;\n\n    if(leaveSuppression >= RTK_ENABLE_END)\n        return RT_ERR_INPUT;\n\n    if ((retVal = rtl8367c_setAsicIGMPSuppression((rtk_uint32)reportSuppression, (rtk_uint32)leaveSuppression))!=RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_igmp_suppressionEnable_get\n * Description:\n *      Get IGMPv1/v2 & MLDv1 Report/Leave/Done suppression\n * Input:\n *      None\n * Output:\n *      pReportSuppression  - Report suppression\n *      pLeaveSuppression   - Leave suppression\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n *      RT_ERR_NULL_POINTER    - Null pointer\n * Note:\n *\n */\nrtk_api_ret_t rtk_igmp_suppressionEnable_get(rtk_enable_t *pReportSuppression, rtk_enable_t *pLeaveSuppression)\n{\n    rtk_api_ret_t   retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(NULL == pReportSuppression)\n        return RT_ERR_NULL_POINTER;\n\n    if(NULL == pLeaveSuppression)\n        return RT_ERR_NULL_POINTER;\n\n    if ((retVal = rtl8367c_getAsicIGMPSuppression((rtk_uint32 *)pReportSuppression, (rtk_uint32 *)pLeaveSuppression))!=RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_igmp_portRxPktEnable_set\n * Description:\n *      Configure IGMP/MLD RX Packet configuration\n * Input:\n *      port       - Port ID\n *      pRxCfg     - RX Packet Configuration\n * Output:\n *      None.\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n *      RT_ERR_INPUT           - Error Input\n *      RT_ERR_NULL_POINTER    - Null pointer\n * Note:\n *\n */\nrtk_api_ret_t rtk_igmp_portRxPktEnable_set(rtk_port_t port, rtk_igmp_rxPktEnable_t *pRxCfg)\n{\n    rtk_api_ret_t   retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check port valid */\n    RTK_CHK_PORT_VALID(port);\n\n    if(NULL == pRxCfg)\n        return RT_ERR_NULL_POINTER;\n\n    if(pRxCfg->rxQuery >= RTK_ENABLE_END)\n        return RT_ERR_INPUT;\n\n    if(pRxCfg->rxReport >= RTK_ENABLE_END)\n        return RT_ERR_INPUT;\n\n    if(pRxCfg->rxLeave >= RTK_ENABLE_END)\n        return RT_ERR_INPUT;\n\n    if(pRxCfg->rxMRP >= RTK_ENABLE_END)\n        return RT_ERR_INPUT;\n\n    if(pRxCfg->rxMcast >= RTK_ENABLE_END)\n        return RT_ERR_INPUT;\n\n    if ((retVal = rtl8367c_setAsicIGMPQueryRX(rtk_switch_port_L2P_get(port), (rtk_uint32)pRxCfg->rxQuery))!=RT_ERR_OK)\n        return retVal;\n\n    if ((retVal = rtl8367c_setAsicIGMPReportRX(rtk_switch_port_L2P_get(port), (rtk_uint32)pRxCfg->rxReport))!=RT_ERR_OK)\n        return retVal;\n\n    if ((retVal = rtl8367c_setAsicIGMPLeaveRX(rtk_switch_port_L2P_get(port), (rtk_uint32)pRxCfg->rxLeave))!=RT_ERR_OK)\n        return retVal;\n\n    if ((retVal = rtl8367c_setAsicIGMPMRPRX(rtk_switch_port_L2P_get(port), (rtk_uint32)pRxCfg->rxMRP))!=RT_ERR_OK)\n        return retVal;\n\n    if ((retVal = rtl8367c_setAsicIGMPMcDataRX(rtk_switch_port_L2P_get(port), (rtk_uint32)pRxCfg->rxMcast))!=RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_igmp_portRxPktEnable_get\n * Description:\n *      Get IGMP/MLD RX Packet configuration\n * Input:\n *      port       - Port ID\n *      pRxCfg     - RX Packet Configuration\n * Output:\n *      None.\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n *      RT_ERR_INPUT           - Error Input\n *      RT_ERR_NULL_POINTER    - Null pointer\n * Note:\n *\n */\nrtk_api_ret_t rtk_igmp_portRxPktEnable_get(rtk_port_t port, rtk_igmp_rxPktEnable_t *pRxCfg)\n{\n    rtk_api_ret_t   retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check port valid */\n    RTK_CHK_PORT_VALID(port);\n\n    if(NULL == pRxCfg)\n        return RT_ERR_NULL_POINTER;\n\n    if ((retVal = rtl8367c_getAsicIGMPQueryRX(rtk_switch_port_L2P_get(port), (rtk_uint32 *)&(pRxCfg->rxQuery)))!=RT_ERR_OK)\n        return retVal;\n\n    if ((retVal = rtl8367c_getAsicIGMPReportRX(rtk_switch_port_L2P_get(port), (rtk_uint32 *)&(pRxCfg->rxReport)))!=RT_ERR_OK)\n        return retVal;\n\n    if ((retVal = rtl8367c_getAsicIGMPLeaveRX(rtk_switch_port_L2P_get(port), (rtk_uint32 *)&(pRxCfg->rxLeave)))!=RT_ERR_OK)\n        return retVal;\n\n    if ((retVal = rtl8367c_getAsicIGMPMRPRX(rtk_switch_port_L2P_get(port), (rtk_uint32 *)&(pRxCfg->rxMRP)))!=RT_ERR_OK)\n        return retVal;\n\n    if ((retVal = rtl8367c_getAsicIGMPMcDataRX(rtk_switch_port_L2P_get(port), (rtk_uint32 *)&(pRxCfg->rxMcast)))!=RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_igmp_groupInfo_get\n * Description:\n *      Get IGMP/MLD Group database\n * Input:\n *      indes       - Index (0~255)\n * Output:\n *      pGroup      - Group database information.\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n *      RT_ERR_INPUT           - Error Input\n *      RT_ERR_NULL_POINTER    - Null pointer\n * Note:\n *\n */\nrtk_api_ret_t rtk_igmp_groupInfo_get(rtk_uint32 index, rtk_igmp_groupInfo_t *pGroup)\n{\n    rtk_api_ret_t   retVal;\n    rtk_uint32      valid;\n    rtl8367c_igmpgroup  grp;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check index */\n    if(index > RTL8367C_IGMP_MAX_GOUP)\n        return RT_ERR_INPUT;\n\n    if(NULL == pGroup)\n        return RT_ERR_NULL_POINTER;\n\n    if ((retVal = rtl8367c_getAsicIGMPGroup(index, &valid, &grp))!=RT_ERR_OK)\n        return retVal;\n\n    memset(pGroup, 0x00, sizeof(rtk_igmp_groupInfo_t));\n    pGroup->valid = valid;\n    pGroup->reportSuppFlag = grp.report_supp_flag;\n\n    if(grp.p0_timer != 0)\n    {\n        RTK_PORTMASK_PORT_SET((pGroup->member), rtk_switch_port_P2L_get(0));\n        pGroup->timer[rtk_switch_port_P2L_get(0)] = grp.p0_timer;\n    }\n\n    if(grp.p1_timer != 0)\n    {\n        RTK_PORTMASK_PORT_SET((pGroup->member), rtk_switch_port_P2L_get(1));\n        pGroup->timer[rtk_switch_port_P2L_get(1)] = grp.p1_timer;\n    }\n\n    if(grp.p2_timer != 0)\n    {\n        RTK_PORTMASK_PORT_SET((pGroup->member), rtk_switch_port_P2L_get(2));\n        pGroup->timer[rtk_switch_port_P2L_get(2)] = grp.p2_timer;\n    }\n\n    if(grp.p3_timer != 0)\n    {\n        RTK_PORTMASK_PORT_SET((pGroup->member), rtk_switch_port_P2L_get(3));\n        pGroup->timer[rtk_switch_port_P2L_get(3)] = grp.p3_timer;\n    }\n\n    if(grp.p4_timer != 0)\n    {\n        RTK_PORTMASK_PORT_SET((pGroup->member), rtk_switch_port_P2L_get(4));\n        pGroup->timer[rtk_switch_port_P2L_get(4)] = grp.p4_timer;\n    }\n\n    if(grp.p5_timer != 0)\n    {\n        RTK_PORTMASK_PORT_SET((pGroup->member), rtk_switch_port_P2L_get(5));\n        pGroup->timer[rtk_switch_port_P2L_get(5)] = grp.p5_timer;\n    }\n\n    if(grp.p6_timer != 0)\n    {\n        RTK_PORTMASK_PORT_SET((pGroup->member), rtk_switch_port_P2L_get(6));\n        pGroup->timer[rtk_switch_port_P2L_get(6)] = grp.p6_timer;\n    }\n\n    if(grp.p7_timer != 0)\n    {\n        RTK_PORTMASK_PORT_SET((pGroup->member), rtk_switch_port_P2L_get(7));\n        pGroup->timer[rtk_switch_port_P2L_get(7)] = grp.p7_timer;\n    }\n\n    if(grp.p8_timer != 0)\n    {\n        RTK_PORTMASK_PORT_SET((pGroup->member), rtk_switch_port_P2L_get(8));\n        pGroup->timer[rtk_switch_port_P2L_get(8)] = grp.p8_timer;\n    }\n\n    if(grp.p9_timer != 0)\n    {\n        RTK_PORTMASK_PORT_SET((pGroup->member), rtk_switch_port_P2L_get(9));\n        pGroup->timer[rtk_switch_port_P2L_get(9)] = grp.p9_timer;\n    }\n\n    if(grp.p10_timer != 0)\n    {\n        RTK_PORTMASK_PORT_SET((pGroup->member), rtk_switch_port_P2L_get(10));\n        pGroup->timer[rtk_switch_port_P2L_get(10)] = grp.p10_timer;\n    }\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_igmp_ReportLeaveFwdAction_set\n * Description:\n *      Set Report Leave packet forwarding action\n * Input:\n *      action      - Action\n * Output:\n *      None.\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n *      RT_ERR_INPUT           - Error Input\n * Note:\n *\n */\nrtk_api_ret_t rtk_igmp_ReportLeaveFwdAction_set(rtk_igmp_ReportLeaveFwdAct_t action)\n{\n    rtk_api_ret_t   retVal;\n    rtk_uint32      regData;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    switch(action)\n    {\n        case IGMP_REPORT_LEAVE_TO_ROUTER:\n            regData = 1;\n            break;\n        case IGMP_REPORT_LEAVE_TO_ALLPORT:\n            regData = 2;\n            break;\n        case IGMP_REPORT_LEAVE_TO_ROUTER_PORT_ADV:\n            regData = 3;\n            break;\n        default:\n            return RT_ERR_INPUT;\n    }\n\n    if ((retVal = rtl8367c_setAsicIGMPReportLeaveFlood(regData))!=RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_igmp_ReportLeaveFwdAction_get\n * Description:\n *      Get Report Leave packet forwarding action\n * Input:\n *      action      - Action\n * Output:\n *      None.\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n *      RT_ERR_INPUT           - Error Input\n *      RT_ERR_NULL_POINTER    - Null Pointer\n * Note:\n *\n */\nrtk_api_ret_t rtk_igmp_ReportLeaveFwdAction_get(rtk_igmp_ReportLeaveFwdAct_t *pAction)\n{\n    rtk_api_ret_t   retVal;\n    rtk_uint32      regData;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(NULL == pAction)\n        return RT_ERR_NULL_POINTER;\n\n    if ((retVal = rtl8367c_getAsicIGMPReportLeaveFlood(&regData))!=RT_ERR_OK)\n        return retVal;\n\n    switch(regData)\n    {\n        case 1:\n            *pAction = IGMP_REPORT_LEAVE_TO_ROUTER;\n            break;\n        case 2:\n            *pAction = IGMP_REPORT_LEAVE_TO_ALLPORT;\n            break;\n        case 3:\n            *pAction = IGMP_REPORT_LEAVE_TO_ROUTER_PORT_ADV;\n            break;\n        default:\n            return RT_ERR_FAILED;\n    }\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_igmp_dropLeaveZeroEnable_set\n * Description:\n *      Set the function of droppping Leave packet with group IP = 0.0.0.0\n * Input:\n *      enabled      - Action 1: drop, 0:pass\n * Output:\n *      None.\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n *      RT_ERR_INPUT           - Error Input\n * Note:\n *\n */\nrtk_api_ret_t rtk_igmp_dropLeaveZeroEnable_set(rtk_enable_t enabled)\n{\n    rtk_api_ret_t   retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(enabled >= RTK_ENABLE_END)\n        return RT_ERR_INPUT;\n\n    if ((retVal = rtl8367c_setAsicIGMPDropLeaveZero(enabled))!=RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n\n}\n\n/* Function Name:\n *      rtk_igmp_dropLeaveZeroEnable_get\n * Description:\n *      Get the function of droppping Leave packet with group IP = 0.0.0.0\n * Input:\n *      None\n * Output:\n *      pEnabled.   - Action 1: drop, 0:pass\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n *      RT_ERR_INPUT           - Error Input\n *      RT_ERR_NULL_POINTER    - Null Pointer\n * Note:\n *\n */\nrtk_api_ret_t rtk_igmp_dropLeaveZeroEnable_get(rtk_enable_t *pEnabled)\n{\n    rtk_api_ret_t   retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(NULL == pEnabled)\n        return RT_ERR_NULL_POINTER;\n\n    if ((retVal = rtl8367c_getAsicIGMPDropLeaveZero((rtk_uint32 *)pEnabled))!=RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n\n}\n\n/* Function Name:\n *      rtk_igmp_bypassGroupRange_set\n * Description:\n *      Set Bypass group\n * Input:\n *      group       - bypassed group\n *      enabled     - enabled 1: Bypassed, 0: not bypass\n * Output:\n *      None.\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n *      RT_ERR_INPUT           - Error Input\n * Note:\n *\n */\nrtk_api_ret_t rtk_igmp_bypassGroupRange_set(rtk_igmp_bypassGroup_t group, rtk_enable_t enabled)\n{\n    rtk_api_ret_t   retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(group >= IGMP_BYPASS_GROUP_END)\n        return RT_ERR_INPUT;\n\n    if(enabled >= RTK_ENABLE_END)\n        return RT_ERR_INPUT;\n\n    if ((retVal = rtl8367c_setAsicIGMPBypassGroup(group, enabled))!=RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_igmp_bypassGroupRange_get\n * Description:\n *      get Bypass group\n * Input:\n *      group       - bypassed group\n * Output:\n *      pEnable     - enabled 1: Bypassed, 0: not bypass\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n *      RT_ERR_INPUT           - Error Input\n *      RT_ERR_NULL_POINTER    - Null Pointer\n * Note:\n *\n */\nrtk_api_ret_t rtk_igmp_bypassGroupRange_get(rtk_igmp_bypassGroup_t group, rtk_enable_t *pEnable)\n{\n    rtk_api_ret_t   retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(group >= IGMP_BYPASS_GROUP_END)\n        return RT_ERR_INPUT;\n\n    if(NULL == pEnable)\n        return RT_ERR_NULL_POINTER;\n\n    if ((retVal = rtl8367c_getAsicIGMPBypassGroup(group, pEnable))!=RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/acl.h",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * Purpose : RTL8367/RTL8367C switch high-level API\n *\n * Feature : The file includes ACL module high-layer API defination\n *\n */\n\n#ifndef __RTK_API_ACL_H__\n#define __RTK_API_ACL_H__\n\n/*\n * Data Type Declaration\n */\n#define RTK_FILTER_RAW_FIELD_NUMBER                8\n\n#define ACL_DEFAULT_ABILITY                         0\n#define ACL_DEFAULT_UNMATCH_PERMIT                  1\n\n#define ACL_RULE_FREE                               0\n#define ACL_RULE_INAVAILABLE                        1\n#define ACL_RULE_CARETAG_MASK                       0x1F\n#define FILTER_POLICING_MAX                         4\n#define FILTER_LOGGING_MAX                          8\n#define FILTER_PATTERN_MAX                          4\n\n#define FILTER_ENACT_CVLAN_MASK         0x01\n#define FILTER_ENACT_SVLAN_MASK         0x02\n#define FILTER_ENACT_PRIORITY_MASK      0x04\n#define FILTER_ENACT_POLICING_MASK      0x08\n#define FILTER_ENACT_FWD_MASK           0x10\n#define FILTER_ENACT_INTGPIO_MASK       0x20\n#define FILTER_ENACT_INIT_MASK          0x3F\n\ntypedef enum rtk_filter_act_cactext_e\n{\n    FILTER_ENACT_CACTEXT_VLANONLY=0,\n    FILTER_ENACT_CACTEXT_BOTHVLANTAG,\n    FILTER_ENACT_CACTEXT_TAGONLY,\n    FILTER_ENACT_CACTEXT_END,\n\n\n}rtk_filter_act_cactext_t;\n\ntypedef enum rtk_filter_act_ctagfmt_e\n{\n    FILTER_CTAGFMT_UNTAG=0,\n    FILTER_CTAGFMT_TAG,\n    FILTER_CTAGFMT_KEEP,\n    FILTER_CTAGFMT_KEEP1PRMK,\n\n\n}rtk_filter_act_ctag_t;\n\n\n\n\n\n#define RTK_MAX_NUM_OF_FILTER_TYPE                  5\n#define RTK_MAX_NUM_OF_FILTER_FIELD                 8\n\n#define RTK_DOT_1AS_TIMESTAMP_UNIT_IN_WORD_LENGTH   3UL\n#define RTK_IPV6_ADDR_WORD_LENGTH                   4UL\n\n#define FILTER_ENACT_CVLAN_TYPE(type)   (type - FILTER_ENACT_CVLAN_INGRESS)\n#define FILTER_ENACT_SVLAN_TYPE(type)   (type - FILTER_ENACT_SVLAN_INGRESS)\n#define FILTER_ENACT_FWD_TYPE(type)     (type - FILTER_ENACT_ADD_DSTPORT)\n#define FILTER_ENACT_PRI_TYPE(type)     (type - FILTER_ENACT_PRIORITY)\n\n#define RTK_FILTER_FIELD_USED_MAX                   8\n#define RTK_FILTER_FIELD_INDEX(template, index)     ((template << 4) + index)\n\n\ntypedef enum rtk_filter_act_enable_e\n{\n    /* CVLAN */\n    FILTER_ENACT_CVLAN_INGRESS = 0,\n    FILTER_ENACT_CVLAN_EGRESS,\n    FILTER_ENACT_CVLAN_SVID,\n    FILTER_ENACT_POLICING_1,\n\n    /* SVLAN */\n    FILTER_ENACT_SVLAN_INGRESS,\n    FILTER_ENACT_SVLAN_EGRESS,\n    FILTER_ENACT_SVLAN_CVID,\n    FILTER_ENACT_POLICING_2,\n\n    /* Policing and Logging */\n    FILTER_ENACT_POLICING_0,\n\n    /* Forward */\n    FILTER_ENACT_COPY_CPU,\n    FILTER_ENACT_DROP,\n    FILTER_ENACT_ADD_DSTPORT,\n    FILTER_ENACT_REDIRECT,\n    FILTER_ENACT_MIRROR,\n    FILTER_ENACT_TRAP_CPU,\n    FILTER_ENACT_ISOLATION,\n\n    /* QoS */\n    FILTER_ENACT_PRIORITY,\n    FILTER_ENACT_DSCP_REMARK,\n    FILTER_ENACT_1P_REMARK,\n    FILTER_ENACT_POLICING_3,\n\n    /* Interrutp and GPO */\n    FILTER_ENACT_INTERRUPT,\n    FILTER_ENACT_GPO,\n\n    /*VLAN tag*/\n    FILTER_ENACT_EGRESSCTAG_UNTAG,\n    FILTER_ENACT_EGRESSCTAG_TAG,\n    FILTER_ENACT_EGRESSCTAG_KEEP,\n    FILTER_ENACT_EGRESSCTAG_KEEPAND1PRMK,\n\n    FILTER_ENACT_END,\n} rtk_filter_act_enable_t;\n\n\ntypedef struct\n{\n    rtk_filter_act_enable_t actEnable[FILTER_ENACT_END];\n\n    /* CVLAN acton */\n    rtk_uint32      filterCvlanVid;\n    rtk_uint32      filterCvlanIdx;\n    /* SVLAN action */\n    rtk_uint32      filterSvlanVid;\n    rtk_uint32      filterSvlanIdx;\n\n    /* Policing action */\n    rtk_uint32      filterPolicingIdx[FILTER_POLICING_MAX];\n\n    /* Forwarding action */\n    rtk_portmask_t  filterPortmask;\n\n    /* QOS action */\n    rtk_uint32      filterPriority;\n\n    /*GPO*/\n    rtk_uint32      filterPin;\n\n} rtk_filter_action_t;\n\ntypedef struct rtk_filter_flag_s\n{\n    rtk_uint32 value;\n    rtk_uint32 mask;\n} rtk_filter_flag_t;\n\ntypedef enum rtk_filter_care_tag_index_e\n{\n    CARE_TAG_CTAG = 0,\n    CARE_TAG_STAG,\n    CARE_TAG_PPPOE,\n    CARE_TAG_IPV4,\n    CARE_TAG_IPV6,\n    CARE_TAG_TCP,\n    CARE_TAG_UDP,\n    CARE_TAG_ARP,\n    CARE_TAG_RSV1,\n    CARE_TAG_RSV2,\n    CARE_TAG_ICMP,\n    CARE_TAG_IGMP,\n    CARE_TAG_LLC,\n    CARE_TAG_RSV3,\n    CARE_TAG_HTTP,\n    CARE_TAG_RSV4,\n    CARE_TAG_RSV5,\n    CARE_TAG_DHCP,\n    CARE_TAG_DHCPV6,\n    CARE_TAG_SNMP,\n    CARE_TAG_OAM,\n    CARE_TAG_END,\n} rtk_filter_care_tag_index_t;\n\ntypedef struct rtk_filter_care_tag_s\n{\n    rtk_filter_flag_t tagType[CARE_TAG_END];\n} rtk_filter_care_tag_t;\n\ntypedef struct rtk_filter_field rtk_filter_field_t;\n\ntypedef struct\n{\n    rtk_uint32 value[RTK_DOT_1AS_TIMESTAMP_UNIT_IN_WORD_LENGTH];\n} rtk_filter_dot1as_timestamp_t;\n\ntypedef enum rtk_filter_field_data_type_e\n{\n    FILTER_FIELD_DATA_MASK = 0,\n    FILTER_FIELD_DATA_RANGE,\n    FILTER_FIELD_DATA_END ,\n} rtk_filter_field_data_type_t;\n\ntypedef struct rtk_filter_ip_s\n{\n    rtk_uint32 dataType;\n    rtk_uint32 rangeStart;\n    rtk_uint32 rangeEnd;\n    rtk_uint32 value;\n    rtk_uint32 mask;\n} rtk_filter_ip_t;\n\ntypedef struct rtk_filter_mac_s\n{\n    rtk_uint32 dataType;\n    rtk_mac_t value;\n    rtk_mac_t mask;\n    rtk_mac_t rangeStart;\n    rtk_mac_t rangeEnd;\n} rtk_filter_mac_t;\n\ntypedef rtk_uint32 rtk_filter_op_t;\n\ntypedef struct rtk_filter_value_s\n{\n    rtk_uint32 dataType;\n    rtk_uint32 value;\n    rtk_uint32 mask;\n    rtk_uint32 rangeStart;\n    rtk_uint32 rangeEnd;\n\n} rtk_filter_value_t;\n\ntypedef struct rtk_filter_activeport_s\n{\n    rtk_portmask_t value;\n    rtk_portmask_t mask;\n\n} rtk_filter_activeport_t;\n\n\n\ntypedef struct rtk_filter_tag_s\n{\n    rtk_filter_value_t pri;\n    rtk_filter_flag_t cfi;\n    rtk_filter_value_t vid;\n} rtk_filter_tag_t;\n\ntypedef struct rtk_filter_ipFlag_s\n{\n    rtk_filter_flag_t xf;\n    rtk_filter_flag_t mf;\n    rtk_filter_flag_t df;\n} rtk_filter_ipFlag_t;\n\ntypedef struct\n{\n    rtk_uint32 addr[RTK_IPV6_ADDR_WORD_LENGTH];\n} rtk_filter_ip6_addr_t;\n\ntypedef struct\n{\n    rtk_uint32 dataType;\n    rtk_filter_ip6_addr_t value;\n    rtk_filter_ip6_addr_t mask;\n    rtk_filter_ip6_addr_t rangeStart;\n    rtk_filter_ip6_addr_t rangeEnd;\n} rtk_filter_ip6_t;\n\ntypedef rtk_uint32 rtk_filter_number_t;\n\ntypedef struct rtk_filter_pattern_s\n{\n    rtk_uint32 value[FILTER_PATTERN_MAX];\n    rtk_uint32 mask[FILTER_PATTERN_MAX];\n} rtk_filter_pattern_t;\n\ntypedef struct rtk_filter_tcpFlag_s\n{\n    rtk_filter_flag_t urg;\n    rtk_filter_flag_t ack;\n    rtk_filter_flag_t psh;\n    rtk_filter_flag_t rst;\n    rtk_filter_flag_t syn;\n    rtk_filter_flag_t fin;\n    rtk_filter_flag_t ns;\n    rtk_filter_flag_t cwr;\n    rtk_filter_flag_t ece;\n} rtk_filter_tcpFlag_t;\n\ntypedef rtk_uint32 rtk_filter_field_raw_t;\n\ntypedef enum rtk_filter_field_temple_input_e\n{\n    FILTER_FIELD_TEMPLE_INPUT_TYPE = 0,\n    FILTER_FIELD_TEMPLE_INPUT_INDEX,\n    FILTER_FIELD_TEMPLE_INPUT_MAX ,\n} rtk_filter_field_temple_input_t;\n\nstruct rtk_filter_field\n{\n    rtk_uint32 fieldType;\n\n    union\n    {\n        /* L2 struct */\n        rtk_filter_mac_t       dmac;\n        rtk_filter_mac_t       smac;\n        rtk_filter_value_t     etherType;\n        rtk_filter_tag_t       ctag;\n        rtk_filter_tag_t       relayCtag;\n        rtk_filter_tag_t       stag;\n        rtk_filter_tag_t       l2tag;\n        rtk_filter_dot1as_timestamp_t dot1asTimeStamp;\n        rtk_filter_mac_t       mac;\n\n        /* L3 struct */\n        rtk_filter_ip_t      sip;\n        rtk_filter_ip_t      dip;\n        rtk_filter_ip_t      ip;\n        rtk_filter_value_t   protocol;\n        rtk_filter_value_t   ipTos;\n        rtk_filter_ipFlag_t  ipFlag;\n        rtk_filter_value_t   ipOffset;\n        rtk_filter_ip6_t     sipv6;\n        rtk_filter_ip6_t     dipv6;\n        rtk_filter_ip6_t     ipv6;\n        rtk_filter_value_t   ipv6TrafficClass;\n        rtk_filter_value_t   ipv6NextHeader;\n        rtk_filter_value_t   flowLabel;\n\n        /* L4 struct */\n        rtk_filter_value_t   tcpSrcPort;\n        rtk_filter_value_t   tcpDstPort;\n        rtk_filter_tcpFlag_t tcpFlag;\n        rtk_filter_value_t   tcpSeqNumber;\n        rtk_filter_value_t   tcpAckNumber;\n        rtk_filter_value_t   udpSrcPort;\n        rtk_filter_value_t   udpDstPort;\n        rtk_filter_value_t   icmpCode;\n        rtk_filter_value_t   icmpType;\n        rtk_filter_value_t   igmpType;\n\n        /* pattern match */\n        rtk_filter_pattern_t pattern;\n\n        rtk_filter_value_t   inData;\n\n    } filter_pattern_union;\n\n    rtk_uint32 fieldTemplateNo;\n    rtk_uint32 fieldTemplateIdx[RTK_FILTER_FIELD_USED_MAX];\n\n    struct rtk_filter_field *next;\n};\n\ntypedef enum rtk_filter_field_type_e\n{\n    FILTER_FIELD_DMAC = 0,\n    FILTER_FIELD_SMAC,\n    FILTER_FIELD_ETHERTYPE,\n    FILTER_FIELD_CTAG,\n    FILTER_FIELD_STAG,\n\n    FILTER_FIELD_IPV4_SIP,\n    FILTER_FIELD_IPV4_DIP,\n    FILTER_FIELD_IPV4_TOS,\n    FILTER_FIELD_IPV4_PROTOCOL,\n    FILTER_FIELD_IPV4_FLAG,\n    FILTER_FIELD_IPV4_OFFSET,\n    FILTER_FIELD_IPV6_SIPV6,\n    FILTER_FIELD_IPV6_DIPV6,\n    FILTER_FIELD_IPV6_TRAFFIC_CLASS,\n    FILTER_FIELD_IPV6_NEXT_HEADER,\n\n    FILTER_FIELD_TCP_SPORT,\n    FILTER_FIELD_TCP_DPORT,\n    FILTER_FIELD_TCP_FLAG,\n    FILTER_FIELD_UDP_SPORT,\n    FILTER_FIELD_UDP_DPORT,\n    FILTER_FIELD_ICMP_CODE,\n    FILTER_FIELD_ICMP_TYPE,\n    FILTER_FIELD_IGMP_TYPE,\n\n    FILTER_FIELD_VID_RANGE,\n    FILTER_FIELD_IP_RANGE,\n    FILTER_FIELD_PORT_RANGE,\n\n    FILTER_FIELD_USER_DEFINED00,\n    FILTER_FIELD_USER_DEFINED01,\n    FILTER_FIELD_USER_DEFINED02,\n    FILTER_FIELD_USER_DEFINED03,\n    FILTER_FIELD_USER_DEFINED04,\n    FILTER_FIELD_USER_DEFINED05,\n    FILTER_FIELD_USER_DEFINED06,\n    FILTER_FIELD_USER_DEFINED07,\n    FILTER_FIELD_USER_DEFINED08,\n    FILTER_FIELD_USER_DEFINED09,\n    FILTER_FIELD_USER_DEFINED10,\n    FILTER_FIELD_USER_DEFINED11,\n    FILTER_FIELD_USER_DEFINED12,\n    FILTER_FIELD_USER_DEFINED13,\n    FILTER_FIELD_USER_DEFINED14,\n    FILTER_FIELD_USER_DEFINED15,\n\n    FILTER_FIELD_PATTERN_MATCH,\n\n    FILTER_FIELD_END,\n} rtk_filter_field_type_t;\n\n\ntypedef enum rtk_filter_field_type_raw_e\n{\n    FILTER_FIELD_RAW_UNUSED = 0,\n    FILTER_FIELD_RAW_DMAC_15_0,\n    FILTER_FIELD_RAW_DMAC_31_16,\n    FILTER_FIELD_RAW_DMAC_47_32,\n    FILTER_FIELD_RAW_SMAC_15_0,\n    FILTER_FIELD_RAW_SMAC_31_16,\n    FILTER_FIELD_RAW_SMAC_47_32,\n    FILTER_FIELD_RAW_ETHERTYPE,\n    FILTER_FIELD_RAW_STAG,\n    FILTER_FIELD_RAW_CTAG,\n\n    FILTER_FIELD_RAW_IPV4_SIP_15_0 = 0x10,\n    FILTER_FIELD_RAW_IPV4_SIP_31_16,\n    FILTER_FIELD_RAW_IPV4_DIP_15_0,\n    FILTER_FIELD_RAW_IPV4_DIP_31_16,\n\n\n    FILTER_FIELD_RAW_IPV6_SIP_15_0 = 0x20,\n    FILTER_FIELD_RAW_IPV6_SIP_31_16,\n    FILTER_FIELD_RAW_IPV6_DIP_15_0 = 0x28,\n    FILTER_FIELD_RAW_IPV6_DIP_31_16,\n\n    FILTER_FIELD_RAW_VIDRANGE = 0x30,\n    FILTER_FIELD_RAW_IPRANGE,\n    FILTER_FIELD_RAW_PORTRANGE,\n    FILTER_FIELD_RAW_FIELD_VALID,\n\n    FILTER_FIELD_RAW_FIELD_SELECT00 = 0x40,\n    FILTER_FIELD_RAW_FIELD_SELECT01,\n    FILTER_FIELD_RAW_FIELD_SELECT02,\n    FILTER_FIELD_RAW_FIELD_SELECT03,\n    FILTER_FIELD_RAW_FIELD_SELECT04,\n    FILTER_FIELD_RAW_FIELD_SELECT05,\n    FILTER_FIELD_RAW_FIELD_SELECT06,\n    FILTER_FIELD_RAW_FIELD_SELECT07,\n    FILTER_FIELD_RAW_FIELD_SELECT08,\n    FILTER_FIELD_RAW_FIELD_SELECT09,\n    FILTER_FIELD_RAW_FIELD_SELECT10,\n    FILTER_FIELD_RAW_FIELD_SELECT11,\n    FILTER_FIELD_RAW_FIELD_SELECT12,\n    FILTER_FIELD_RAW_FIELD_SELECT13,\n    FILTER_FIELD_RAW_FIELD_SELECT14,\n    FILTER_FIELD_RAW_FIELD_SELECT15,\n\n    FILTER_FIELD_RAW_END,\n} rtk_filter_field_type_raw_t;\n\ntypedef enum rtk_filter_flag_care_type_e\n{\n    FILTER_FLAG_CARE_DONT_CARE = 0,\n    FILTER_FLAG_CARE_1,\n    FILTER_FLAG_CARE_0,\n    FILTER_FLAG_END\n} rtk_filter_flag_care_type_t;\n\ntypedef rtk_uint32  rtk_filter_id_t;    /* filter id type */\n\ntypedef enum rtk_filter_invert_e\n{\n    FILTER_INVERT_DISABLE = 0,\n    FILTER_INVERT_ENABLE,\n    FILTER_INVERT_END,\n} rtk_filter_invert_t;\n\ntypedef rtk_uint32 rtk_filter_state_t;\n\ntypedef rtk_uint32 rtk_filter_unmatch_action_t;\n\ntypedef enum rtk_filter_unmatch_action_e\n{\n    FILTER_UNMATCH_DROP = 0,\n    FILTER_UNMATCH_PERMIT,\n    FILTER_UNMATCH_END,\n} rtk_filter_unmatch_action_type_t;\n\ntypedef struct\n{\n    rtk_filter_field_t      *fieldHead;\n    rtk_filter_care_tag_t   careTag;\n    rtk_filter_activeport_t activeport;\n\n    rtk_filter_invert_t     invert;\n} rtk_filter_cfg_t;\n\ntypedef struct\n{\n    rtk_filter_field_raw_t      dataFieldRaw[RTK_FILTER_RAW_FIELD_NUMBER];\n    rtk_filter_field_raw_t      careFieldRaw[RTK_FILTER_RAW_FIELD_NUMBER];\n    rtk_filter_field_type_raw_t fieldRawType[RTK_FILTER_RAW_FIELD_NUMBER];\n    rtk_filter_care_tag_t       careTag;\n    rtk_filter_activeport_t     activeport;\n\n    rtk_filter_invert_t         invert;\n    rtk_enable_t                valid;\n} rtk_filter_cfg_raw_t;\n\ntypedef struct\n{\n    rtk_uint32 index;\n    rtk_filter_field_type_raw_t fieldType[RTK_FILTER_RAW_FIELD_NUMBER];\n} rtk_filter_template_t;\n\ntypedef enum rtk_field_sel_e\n{\n    FORMAT_DEFAULT = 0,\n    FORMAT_RAW,\n    FORMAT_LLC,\n    FORMAT_IPV4,\n    FORMAT_ARP,\n    FORMAT_IPV6,\n    FORMAT_IPPAYLOAD,\n    FORMAT_L4PAYLOAD,\n    FORMAT_END\n}rtk_field_sel_t;\n\ntypedef enum rtk_filter_iprange_e\n{\n    IPRANGE_UNUSED = 0,\n    IPRANGE_IPV4_SIP,\n    IPRANGE_IPV4_DIP,\n    IPRANGE_IPV6_SIP,\n    IPRANGE_IPV6_DIP,\n    IPRANGE_END\n}rtk_filter_iprange_t;\n\ntypedef enum rtk_filter_vidrange_e\n{\n    VIDRANGE_UNUSED = 0,\n    VIDRANGE_CVID,\n    VIDRANGE_SVID,\n    VIDRANGE_END\n}rtk_filter_vidrange_t;\n\ntypedef enum rtk_filter_portrange_e\n{\n    PORTRANGE_UNUSED = 0,\n    PORTRANGE_SPORT,\n    PORTRANGE_DPORT,\n    PORTRANGE_END\n}rtk_filter_portrange_t;\n\n/* Function Name:\n *      rtk_filter_igrAcl_init\n * Description:\n *      ACL initialization function\n * Input:\n *      None\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_NULL_POINTER - Pointer pFilter_field or pFilter_cfg point to NULL.\n * Note:\n *      This function enable and intialize ACL function\n */\nextern rtk_api_ret_t rtk_filter_igrAcl_init(void);\n\n/* Function Name:\n *      rtk_filter_igrAcl_field_add\n * Description:\n *      Add comparison rule to an ACL configuration\n * Input:\n *      pFilter_cfg     - The ACL configuration that this function will add comparison rule\n *      pFilter_field   - The comparison rule that will be added.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - OK\n *      RT_ERR_FAILED           - Failed\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_NULL_POINTER     - Pointer pFilter_field or pFilter_cfg point to NULL.\n *      RT_ERR_INPUT            - Invalid input parameters.\n * Note:\n *      This function add a comparison rule (*pFilter_field) to an ACL configuration (*pFilter_cfg).\n *      Pointer pFilter_cfg points to an ACL configuration structure, this structure keeps multiple ACL\n *      comparison rules by means of linked list. Pointer pFilter_field will be added to linked\n *      list keeped by structure that pFilter_cfg points to.\n */\nextern rtk_api_ret_t rtk_filter_igrAcl_field_add(rtk_filter_cfg_t *pFilter_cfg, rtk_filter_field_t *pFilter_field);\n\n/* Function Name:\n *      rtk_filter_igrAcl_cfg_add\n * Description:\n *      Add an ACL configuration to ASIC\n * Input:\n *      filter_id       - Start index of ACL configuration.\n *      pFilter_cfg     - The ACL configuration that this function will add comparison rule\n *      pFilter_action  - Action(s) of ACL configuration.\n * Output:\n *      ruleNum - number of rules written in acl table\n * Return:\n *      RT_ERR_OK                               - OK\n *      RT_ERR_FAILED                           - Failed\n *      RT_ERR_SMI                              - SMI access error\n *      RT_ERR_NULL_POINTER                     - Pointer pFilter_field or pFilter_cfg point to NULL.\n *      RT_ERR_INPUT                            - Invalid input parameters.\n *      RT_ERR_ENTRY_INDEX                      - Invalid filter_id .\n *      RT_ERR_NULL_POINTER                     - Pointer pFilter_action or pFilter_cfg point to NULL.\n *      RT_ERR_FILTER_INACL_ACT_NOT_SUPPORT     - Action is not supported in this chip.\n *      RT_ERR_FILTER_INACL_RULE_NOT_SUPPORT    - Rule is not supported.\n * Note:\n *      This function store pFilter_cfg, pFilter_action into ASIC. The starting\n *      index(es) is filter_id.\n */\nextern rtk_api_ret_t rtk_filter_igrAcl_cfg_add(rtk_filter_id_t filter_id, rtk_filter_cfg_t *pFilter_cfg, rtk_filter_action_t *pAction, rtk_filter_number_t *ruleNum);\n\n/* Function Name:\n *      rtk_filter_igrAcl_cfg_del\n * Description:\n *      Delete an ACL configuration from ASIC\n * Input:\n *      filter_id   - Start index of ACL configuration.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - OK\n *      RT_ERR_FAILED           - Failed\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_FILTER_ENTRYIDX  - Invalid filter_id.\n * Note:\n *      This function delete a group of ACL rules starting from filter_id.\n */\nextern rtk_api_ret_t rtk_filter_igrAcl_cfg_del(rtk_filter_id_t filter_id);\n\n/* Function Name:\n *      rtk_filter_igrAcl_cfg_delAll\n * Description:\n *      Delete all ACL entries from ASIC\n * Input:\n *      None\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n * Note:\n *      This function delete all ACL configuration from ASIC.\n */\nextern rtk_api_ret_t rtk_filter_igrAcl_cfg_delAll(void);\n\n/* Function Name:\n *      rtk_filter_igrAcl_cfg_get\n * Description:\n *      Get one ingress acl configuration from ASIC.\n * Input:\n *      filter_id       - Start index of ACL configuration.\n * Output:\n *      pFilter_cfg     - buffer pointer of ingress acl data\n *      pFilter_action  - buffer pointer of ingress acl action\n * Return:\n *      RT_ERR_OK               - OK\n *      RT_ERR_FAILED           - Failed\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_NULL_POINTER     - Pointer pFilter_action or pFilter_cfg point to NULL.\n *      RT_ERR_FILTER_ENTRYIDX  - Invalid entry index.\n * Note:\n *      This function delete all ACL configuration from ASIC.\n */\nextern rtk_api_ret_t rtk_filter_igrAcl_cfg_get(rtk_filter_id_t filter_id, rtk_filter_cfg_raw_t *pFilter_cfg, rtk_filter_action_t *pAction);\n\n/* Function Name:\n *      rtk_filter_igrAcl_unmatchAction_set\n * Description:\n *      Set action to packets when no ACL configuration match\n * Input:\n *      port    - Port id.\n *      action  - Action.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port id.\n *      RT_ERR_INPUT        - Invalid input parameters.\n * Note:\n *      This function sets action of packets when no ACL configruation matches.\n */\nextern rtk_api_ret_t rtk_filter_igrAcl_unmatchAction_set(rtk_port_t port, rtk_filter_unmatch_action_t action);\n\n/* Function Name:\n *      rtk_filter_igrAcl_unmatchAction_get\n * Description:\n *      Get action to packets when no ACL configuration match\n * Input:\n *      port    - Port id.\n * Output:\n *      pAction - Action.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port id.\n *      RT_ERR_INPUT        - Invalid input parameters.\n * Note:\n *      This function gets action of packets when no ACL configruation matches.\n */\nextern rtk_api_ret_t rtk_filter_igrAcl_unmatchAction_get(rtk_port_t port, rtk_filter_unmatch_action_t* action);\n\n/* Function Name:\n *      rtk_filter_igrAcl_state_set\n * Description:\n *      Set state of ingress ACL.\n * Input:\n *      port    - Port id.\n *      state   - Ingress ACL state.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port id.\n *      RT_ERR_INPUT        - Invalid input parameters.\n * Note:\n *      This function gets action of packets when no ACL configruation matches.\n */\nextern rtk_api_ret_t rtk_filter_igrAcl_state_set(rtk_port_t port, rtk_filter_state_t state);\n\n/* Function Name:\n *      rtk_filter_igrAcl_state_get\n * Description:\n *      Get state of ingress ACL.\n * Input:\n *      port    - Port id.\n * Output:\n *      pState  - Ingress ACL state.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port id.\n *      RT_ERR_INPUT        - Invalid input parameters.\n * Note:\n *      This function gets action of packets when no ACL configruation matches.\n */\nextern rtk_api_ret_t rtk_filter_igrAcl_state_get(rtk_port_t port, rtk_filter_state_t* state);\n\n/* Function Name:\n *      rtk_filter_igrAcl_template_set\n * Description:\n *      Set template of ingress ACL.\n * Input:\n *      template - Ingress ACL template\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n *      RT_ERR_INPUT           - Invalid input parameters.\n * Note:\n *      This function set ACL template.\n */\nextern rtk_api_ret_t rtk_filter_igrAcl_template_set(rtk_filter_template_t *aclTemplate);\n\n/* Function Name:\n *      rtk_filter_igrAcl_template_get\n * Description:\n *      Get template of ingress ACL.\n * Input:\n *      template - Ingress ACL template\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n * Note:\n *      This function gets template of ACL.\n */\nextern rtk_api_ret_t rtk_filter_igrAcl_template_get(rtk_filter_template_t *aclTemplate);\n\n/* Function Name:\n *      rtk_filter_igrAcl_field_sel_set\n * Description:\n *      Set user defined field selectors in HSB\n * Input:\n *      index       - index of field selector 0-15\n *      format      - Format of field selector\n *      offset      - Retrieving data offset\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n * Note:\n *      System support 16 user defined field selctors.\n *      Each selector can be enabled or disable.\n *      User can defined retrieving 16-bits in many predefiend\n *      standard l2/l3/l4 payload.\n */\nextern rtk_api_ret_t rtk_filter_igrAcl_field_sel_set(rtk_uint32 index, rtk_field_sel_t format, rtk_uint32 offset);\n\n/* Function Name:\n *      rtk_filter_igrAcl_field_sel_get\n * Description:\n *      Get user defined field selectors in HSB\n * Input:\n *      index       - index of field selector 0-15\n * Output:\n *      pFormat     - Format of field selector\n *      pOffset     - Retrieving data offset\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n * Note:\n *      None.\n */\nextern rtk_api_ret_t rtk_filter_igrAcl_field_sel_get(rtk_uint32 index, rtk_field_sel_t *pFormat, rtk_uint32 *pOffset);\n\n/* Function Name:\n *      rtk_filter_iprange_set\n * Description:\n *      Set IP Range check\n * Input:\n *      index       - index of IP Range 0-15\n *      type        - IP Range check type, 0:Delete a entry, 1: IPv4_SIP, 2: IPv4_DIP, 3:IPv6_SIP, 4:IPv6_DIP\n *      upperIp     - The upper bound of IP range\n *      lowerIp     - The lower Bound of IP range\n * Output:\n *      None.\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n *      RT_ERR_OUT_OF_RANGE    - The parameter is out of range\n *      RT_ERR_INPUT           - Input error\n * Note:\n *      upperIp must be larger or equal than lowerIp.\n */\nextern rtk_api_ret_t rtk_filter_iprange_set(rtk_uint32 index, rtk_filter_iprange_t type, ipaddr_t upperIp, ipaddr_t lowerIp);\n\n/* Function Name:\n *      rtk_filter_iprange_get\n * Description:\n *      Set IP Range check\n * Input:\n *      index       - index of IP Range 0-15\n * Output:\n *      pType        - IP Range check type, 0:Delete a entry, 1: IPv4_SIP, 2: IPv4_DIP, 3:IPv6_SIP, 4:IPv6_DIP\n *      pUpperIp     - The upper bound of IP range\n *      pLowerIp     - The lower Bound of IP range\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n *      RT_ERR_OUT_OF_RANGE    - The parameter is out of range\n * Note:\n *      upperIp must be larger or equal than lowerIp.\n */\nextern rtk_api_ret_t rtk_filter_iprange_get(rtk_uint32 index, rtk_filter_iprange_t *pType, ipaddr_t *pUpperIp, ipaddr_t *pLowerIp);\n\n/* Function Name:\n *      rtk_filter_vidrange_set\n * Description:\n *      Set VID Range check\n * Input:\n *      index       - index of VID Range 0-15\n *      type        - IP Range check type, 0:Delete a entry, 1: CVID, 2: SVID\n *      upperVid    - The upper bound of VID range\n *      lowerVid    - The lower Bound of VID range\n * Output:\n *      None.\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n *      RT_ERR_OUT_OF_RANGE    - The parameter is out of range\n *      RT_ERR_INPUT           - Input error\n * Note:\n *      upperVid must be larger or equal than lowerVid.\n */\nextern rtk_api_ret_t rtk_filter_vidrange_set(rtk_uint32 index, rtk_filter_vidrange_t type, rtk_uint32 upperVid, rtk_uint32 lowerVid);\n\n/* Function Name:\n *      rtk_filter_vidrange_get\n * Description:\n *      Get VID Range check\n * Input:\n *      index       - index of VID Range 0-15\n * Output:\n *      pType        - IP Range check type, 0:Unused, 1: CVID, 2: SVID\n *      pUpperVid    - The upper bound of VID range\n *      pLowerVid    - The lower Bound of VID range\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n *      RT_ERR_OUT_OF_RANGE    - The parameter is out of range\n * Note:\n *      None.\n */\nextern rtk_api_ret_t rtk_filter_vidrange_get(rtk_uint32 index, rtk_filter_vidrange_t *pType, rtk_uint32 *pUpperVid, rtk_uint32 *pLowerVid);\n\n/* Function Name:\n *      rtk_filter_portrange_set\n * Description:\n *      Set Port Range check\n * Input:\n *      index       - index of Port Range 0-15\n *      type        - IP Range check type, 0:Delete a entry, 1: Source Port, 2: Destnation Port\n *      upperPort   - The upper bound of Port range\n *      lowerPort   - The lower Bound of Port range\n * Output:\n *      None.\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n *      RT_ERR_OUT_OF_RANGE    - The parameter is out of range\n *      RT_ERR_INPUT           - Input error\n * Note:\n *      upperPort must be larger or equal than lowerPort.\n */\nextern rtk_api_ret_t rtk_filter_portrange_set(rtk_uint32 index, rtk_filter_portrange_t type, rtk_uint32 upperPort, rtk_uint32 lowerPort);\n\n/* Function Name:\n *      rtk_filter_portrange_get\n * Description:\n *      Set Port Range check\n * Input:\n *      index       - index of Port Range 0-15\n * Output:\n *      pType       - IP Range check type, 0:Delete a entry, 1: Source Port, 2: Destnation Port\n *      pUpperPort  - The upper bound of Port range\n *      pLowerPort  - The lower Bound of Port range\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n *      RT_ERR_OUT_OF_RANGE    - The parameter is out of range\n *      RT_ERR_INPUT           - Input error\n * Note:\n *      None.\n */\nextern rtk_api_ret_t rtk_filter_portrange_get(rtk_uint32 index, rtk_filter_portrange_t *pType, rtk_uint32 *pUpperPort, rtk_uint32 *pLowerPort);\n\n/* Function Name:\n *      rtk_filter_igrAclPolarity_set\n * Description:\n *      Set ACL Goip control palarity\n * Input:\n *      polarity - 1: High, 0: Low\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n * Note:\n *      none\n */\nextern rtk_api_ret_t rtk_filter_igrAclPolarity_set(rtk_uint32 polarity);\n\n/* Function Name:\n *      rtk_filter_igrAclPolarity_get\n * Description:\n *      Get ACL Goip control palarity\n * Input:\n *      pPolarity - 1: High, 0: Low\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n * Note:\n *      none\n */\nextern rtk_api_ret_t rtk_filter_igrAclPolarity_get(rtk_uint32* pPolarity);\n\n\n#endif /* __RTK_API_ACL_H__ */\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/cpu.h",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * Purpose : RTL8367/RTL8367C switch high-level API\n *\n * Feature : The file includes CPU module high-layer API defination\n *\n */\n\n#ifndef __RTK_API_CPU_H__\n#define __RTK_API_CPU_H__\n\n\n/*\n * Data Type Declaration\n */\ntypedef enum rtk_cpu_insert_e\n{\n    CPU_INSERT_TO_ALL = 0,\n    CPU_INSERT_TO_TRAPPING,\n    CPU_INSERT_TO_NONE,\n    CPU_INSERT_END\n}rtk_cpu_insert_t;\n\ntypedef enum rtk_cpu_position_e\n{\n    CPU_POS_AFTER_SA = 0,\n    CPU_POS_BEFORE_CRC,\n    CPU_POS_END\n}rtk_cpu_position_t;\n\ntypedef enum rtk_cpu_tag_length_e\n{\n    CPU_LEN_8BYTES = 0,\n    CPU_LEN_4BYTES,\n    CPU_LEN_END\n}rtk_cpu_tag_length_t;\n\n\ntypedef enum rtk_cpu_rx_length_e\n{\n    CPU_RX_72BYTES = 0,\n    CPU_RX_64BYTES,\n    CPU_RX_END\n}rtk_cpu_rx_length_t;\n\n\n/* Function Name:\n *      rtk_cpu_enable_set\n * Description:\n *      Set CPU port function enable/disable.\n * Input:\n *      enable - CPU port function enable\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameter.\n *      RT_ERR_PORT_ID      - Invalid port number.\n * Note:\n *      The API can set CPU port function enable/disable.\n */\nextern rtk_api_ret_t rtk_cpu_enable_set(rtk_enable_t enable);\n\n/* Function Name:\n *      rtk_cpu_enable_get\n * Description:\n *      Get CPU port and its setting.\n * Input:\n *      None\n * Output:\n *      pEnable - CPU port function enable\n * Return:\n *      RT_ERR_OK               - OK\n *      RT_ERR_FAILED           - Failed\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_INPUT            - Invalid input parameters.\n *      RT_ERR_L2_NO_CPU_PORT   - CPU port is not exist\n * Note:\n *      The API can get CPU port function enable/disable.\n */\nextern rtk_api_ret_t rtk_cpu_enable_get(rtk_enable_t *pEnable);\n\n/* Function Name:\n *      rtk_cpu_tagPort_set\n * Description:\n *      Set CPU port and CPU tag insert mode.\n * Input:\n *      port - Port id.\n *      mode - CPU tag insert for packets egress from CPU port.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameter.\n *      RT_ERR_PORT_ID      - Invalid port number.\n * Note:\n *      The API can set CPU port and inserting proprietary CPU tag mode (Length/Type 0x8899)\n *      to the frame that transmitting to CPU port.\n *      The inset cpu tag mode is as following:\n *      - CPU_INSERT_TO_ALL\n *      - CPU_INSERT_TO_TRAPPING\n *      - CPU_INSERT_TO_NONE\n */\nextern rtk_api_ret_t rtk_cpu_tagPort_set(rtk_port_t port, rtk_cpu_insert_t mode);\n\n/* Function Name:\n *      rtk_cpu_tagPort_get\n * Description:\n *      Get CPU port and CPU tag insert mode.\n * Input:\n *      None\n * Output:\n *      pPort - Port id.\n *      pMode - CPU tag insert for packets egress from CPU port, 0:all insert 1:Only for trapped packets 2:no insert.\n * Return:\n *      RT_ERR_OK               - OK\n *      RT_ERR_FAILED           - Failed\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_INPUT            - Invalid input parameters.\n *      RT_ERR_L2_NO_CPU_PORT   - CPU port is not exist\n * Note:\n *      The API can get configured CPU port and its setting.\n *      The inset cpu tag mode is as following:\n *      - CPU_INSERT_TO_ALL\n *      - CPU_INSERT_TO_TRAPPING\n *      - CPU_INSERT_TO_NONE\n */\nextern rtk_api_ret_t rtk_cpu_tagPort_get(rtk_port_t *pPort, rtk_cpu_insert_t *pMode);\n\n/* Function Name:\n *      rtk_cpu_awarePort_set\n * Description:\n *      Set CPU aware port mask.\n * Input:\n *      portmask - Port mask.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_MASK      - Invalid port mask.\n * Note:\n *      The API can set configured CPU aware port mask.\n */\nextern rtk_api_ret_t rtk_cpu_awarePort_set(rtk_portmask_t *pPortmask);\n\n\n/* Function Name:\n *      rtk_cpu_awarePort_get\n * Description:\n *      Get CPU aware port mask.\n * Input:\n *      None\n * Output:\n *      pPortmask - Port mask.\n * Return:\n *      RT_ERR_OK               - OK\n *      RT_ERR_FAILED           - Failed\n *      RT_ERR_SMI              - SMI access error\n * Note:\n *      The API can get configured CPU aware port mask.\n */\nextern rtk_api_ret_t rtk_cpu_awarePort_get(rtk_portmask_t *pPortmask);\n\n/* Function Name:\n *      rtk_cpu_tagPosition_set\n * Description:\n *      Set CPU tag position.\n * Input:\n *      position - CPU tag position.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT      - Invalid input.\n * Note:\n *      The API can set CPU tag position.\n */\nextern rtk_api_ret_t rtk_cpu_tagPosition_set(rtk_cpu_position_t position);\n\n/* Function Name:\n *      rtk_cpu_tagPosition_get\n * Description:\n *      Get CPU tag position.\n * Input:\n *      None\n * Output:\n *      pPosition - CPU tag position.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT      - Invalid input.\n * Note:\n *      The API can get CPU tag position.\n */\nextern rtk_api_ret_t rtk_cpu_tagPosition_get(rtk_cpu_position_t *pPosition);\n\n/* Function Name:\n *      rtk_cpu_tagLength_set\n * Description:\n *      Set CPU tag length.\n * Input:\n *      length - CPU tag length.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT      - Invalid input.\n * Note:\n *      The API can set CPU tag length.\n */\nextern rtk_api_ret_t rtk_cpu_tagLength_set(rtk_cpu_tag_length_t length);\n\n/* Function Name:\n *      rtk_cpu_tagLength_get\n * Description:\n *      Get CPU tag length.\n * Input:\n *      None\n * Output:\n *      pLength - CPU tag length.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT      - Invalid input.\n * Note:\n *      The API can get CPU tag length.\n */\nextern rtk_api_ret_t rtk_cpu_tagLength_get(rtk_cpu_tag_length_t *pLength);\n\n/* Function Name:\n *      rtk_cpu_acceptLength_set\n * Description:\n *      Set CPU accept  length.\n * Input:\n *      length - CPU tag length.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT      - Invalid input.\n * Note:\n *      The API can set CPU accept length.\n */\nextern rtk_api_ret_t rtk_cpu_acceptLength_set(rtk_cpu_rx_length_t length);\n\n/* Function Name:\n *      rtk_cpu_acceptLength_get\n * Description:\n *      Get CPU accept length.\n * Input:\n *      None\n * Output:\n *      pLength - CPU tag length.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT      - Invalid input.\n * Note:\n *      The API can get CPU accept length.\n */\nextern rtk_api_ret_t rtk_cpu_acceptLength_get(rtk_cpu_rx_length_t *pLength);\n\n/* Function Name:\n *      rtk_cpu_priRemap_set\n * Description:\n *      Configure CPU priorities mapping to internal absolute priority.\n * Input:\n *      int_pri     - internal priority value.\n *      new_pri    - new internal priority value.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - OK\n *      RT_ERR_FAILED           - Failed\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_INPUT            - Invalid input parameters.\n *      RT_ERR_VLAN_PRIORITY    - Invalid 1p priority.\n *      RT_ERR_QOS_INT_PRIORITY - Invalid priority.\n * Note:\n *      Priority of CPU tag assignment for internal asic priority, and it is used for queue usage and packet scheduling.\n */\nextern rtk_api_ret_t rtk_cpu_priRemap_set(rtk_pri_t int_pri, rtk_pri_t new_pri);\n\n/* Function Name:\n *      rtk_cpu_priRemap_get\n * Description:\n *      Configure CPU priorities mapping to internal absolute priority.\n * Input:\n *      int_pri     - internal priority value.\n * Output:\n *      pNew_pri    - new internal priority value.\n * Return:\n *      RT_ERR_OK               - OK\n *      RT_ERR_FAILED           - Failed\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_INPUT            - Invalid input parameters.\n *      RT_ERR_VLAN_PRIORITY    - Invalid 1p priority.\n *      RT_ERR_QOS_INT_PRIORITY - Invalid priority.\n * Note:\n *      Priority of CPU tag assignment for internal asic priority, and it is used for queue usage and packet scheduling.\n */\nextern rtk_api_ret_t rtk_cpu_priRemap_get(rtk_pri_t int_pri, rtk_pri_t *pNew_pri);\n\n\n#endif /* __RTK_API_CPU_H__ */\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/dot1x.h",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * Purpose : RTL8367/RTL8367C switch high-level API\n *\n * Feature : The file includes 1X module high-layer API defination\n *\n */\n\n#ifndef __RTK_API_DOT1X_H__\n#define __RTK_API_DOT1X_H__\n\n\n/* Type of port-based dot1x auth/unauth*/\ntypedef enum rtk_dot1x_auth_status_e\n{\n    UNAUTH = 0,\n    AUTH,\n    AUTH_STATUS_END\n} rtk_dot1x_auth_status_t;\n\ntypedef enum rtk_dot1x_direction_e\n{\n    DIR_BOTH = 0,\n    DIR_IN,\n    DIRECTION_END\n} rtk_dot1x_direction_t;\n\n/* unauth pkt action */\ntypedef enum rtk_dot1x_unauth_action_e\n{\n    DOT1X_ACTION_DROP = 0,\n    DOT1X_ACTION_TRAP2CPU,\n    DOT1X_ACTION_GUESTVLAN,\n    DOT1X_ACTION_END\n} rtk_dot1x_unauth_action_t;\n\n/* Function Name:\n *      rtk_dot1x_unauthPacketOper_set\n * Description:\n *      Set 802.1x unauth action configuration.\n * Input:\n *      port            - Port id.\n *      unauth_action   - 802.1X unauth action.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number.\n *      RT_ERR_INPUT        - Invalid input parameter.\n * Note:\n *      This API can set 802.1x unauth action configuration.\n *      The unauth action is as following:\n *      - DOT1X_ACTION_DROP\n *      - DOT1X_ACTION_TRAP2CPU\n *      - DOT1X_ACTION_GUESTVLAN\n */\nextern rtk_api_ret_t rtk_dot1x_unauthPacketOper_set(rtk_port_t port, rtk_dot1x_unauth_action_t unauth_action);\n\n/* Function Name:\n *      rtk_dot1x_unauthPacketOper_get\n * Description:\n *      Get 802.1x unauth action configuration.\n * Input:\n *      port - Port id.\n * Output:\n *      pUnauth_action - 802.1X unauth action.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n *      RT_ERR_PORT_ID      - Invalid port number.\n * Note:\n *      This API can get 802.1x unauth action configuration.\n *      The unauth action is as following:\n *      - DOT1X_ACTION_DROP\n *      - DOT1X_ACTION_TRAP2CPU\n *      - DOT1X_ACTION_GUESTVLAN\n */\nextern rtk_api_ret_t rtk_dot1x_unauthPacketOper_get(rtk_port_t port, rtk_dot1x_unauth_action_t *pUnauth_action);\n\n/* Function Name:\n *      rtk_dot1x_eapolFrame2CpuEnable_set\n * Description:\n *      Set 802.1x EAPOL packet trap to CPU configuration\n * Input:\n *      enable - The status of 802.1x EAPOL packet.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_ENABLE       - Invalid enable input.\n * Note:\n *      To support 802.1x authentication functionality, EAPOL frame (ether type = 0x888E) has to\n *      be trapped to CPU.\n *      The status of EAPOL frame trap to CPU is as following:\n *      - DISABLED\n *      - ENABLED\n */\nextern rtk_api_ret_t rtk_dot1x_eapolFrame2CpuEnable_set(rtk_enable_t enable);\n\n/* Function Name:\n *      rtk_dot1x_eapolFrame2CpuEnable_get\n * Description:\n *      Get 802.1x EAPOL packet trap to CPU configuration\n * Input:\n *      None\n * Output:\n *      pEnable - The status of 802.1x EAPOL packet.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n * Note:\n *      To support 802.1x authentication functionality, EAPOL frame (ether type = 0x888E) has to\n *      be trapped to CPU.\n *      The status of EAPOL frame trap to CPU is as following:\n *      - DISABLED\n *      - ENABLED\n */\nextern rtk_api_ret_t rtk_dot1x_eapolFrame2CpuEnable_get(rtk_enable_t *pEnable);\n\n/* Function Name:\n *      rtk_dot1x_portBasedEnable_set\n * Description:\n *      Set 802.1x port-based enable configuration\n * Input:\n *      port - Port id.\n *      enable - The status of 802.1x port.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK                   - OK\n *      RT_ERR_FAILED               - Failed\n *      RT_ERR_SMI                  - SMI access error\n *      RT_ERR_PORT_ID              - Invalid port number.\n *      RT_ERR_ENABLE               - Invalid enable input.\n *      RT_ERR_DOT1X_PORTBASEDPNEN  - 802.1X port-based enable error\n * Note:\n *      The API can update the port-based port enable register content. If a port is 802.1x\n *      port based network access control \"enabled\", it should be authenticated so packets\n *      from that port won't be dropped or trapped to CPU.\n *      The status of 802.1x port-based network access control is as following:\n *      - DISABLED\n *      - ENABLED\n */\nextern rtk_api_ret_t rtk_dot1x_portBasedEnable_set(rtk_port_t port, rtk_enable_t enable);\n\n/* Function Name:\n *      rtk_dot1x_portBasedEnable_get\n * Description:\n *      Get 802.1x port-based enable configuration\n * Input:\n *      port - Port id.\n * Output:\n *      pEnable - The status of 802.1x port.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n *      RT_ERR_PORT_ID      - Invalid port number.\n * Note:\n *      The API can get the 802.1x port-based port status.\n */\nextern rtk_api_ret_t rtk_dot1x_portBasedEnable_get(rtk_port_t port, rtk_enable_t *pEnable);\n\n/* Function Name:\n *      rtk_dot1x_portBasedAuthStatus_set\n * Description:\n *      Set 802.1x port-based auth. port configuration\n * Input:\n *      port - Port id.\n *      port_auth - The status of 802.1x port.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK                   - OK\n *      RT_ERR_FAILED               - Failed\n *      RT_ERR_SMI                  - SMI access error\n *      RT_ERR_PORT_ID              - Invalid port number.\n *     RT_ERR_DOT1X_PORTBASEDAUTH   - 802.1X port-based auth error\n * Note:\n *      The authenticated status of 802.1x port-based network access control is as following:\n *      - UNAUTH\n *      - AUTH\n */\nextern rtk_api_ret_t rtk_dot1x_portBasedAuthStatus_set(rtk_port_t port, rtk_dot1x_auth_status_t port_auth);\n\n/* Function Name:\n *      rtk_dot1x_portBasedAuthStatus_get\n * Description:\n *      Get 802.1x port-based auth. port configuration\n * Input:\n *      port - Port id.\n * Output:\n *      pPort_auth - The status of 802.1x port.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n *      RT_ERR_PORT_ID      - Invalid port number.\n * Note:\n *      The API can get 802.1x port-based port auth.information.\n */\nextern rtk_api_ret_t rtk_dot1x_portBasedAuthStatus_get(rtk_port_t port, rtk_dot1x_auth_status_t *pPort_auth);\n\n/* Function Name:\n *      rtk_dot1x_portBasedDirection_set\n * Description:\n *      Set 802.1x port-based operational direction configuration\n * Input:\n *      port            - Port id.\n *      port_direction  - Operation direction\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK                   - OK\n *      RT_ERR_FAILED               - Failed\n *      RT_ERR_SMI                  - SMI access error\n *      RT_ERR_PORT_ID              - Invalid port number.\n *      RT_ERR_DOT1X_PORTBASEDOPDIR - 802.1X port-based operation direction error\n * Note:\n *      The operate controlled direction of 802.1x port-based network access control is as following:\n *      - BOTH\n *      - IN\n */\nextern rtk_api_ret_t rtk_dot1x_portBasedDirection_set(rtk_port_t port, rtk_dot1x_direction_t port_direction);\n\n/* Function Name:\n *      rtk_dot1x_portBasedDirection_get\n * Description:\n *      Get 802.1X port-based operational direction configuration\n * Input:\n *      port - Port id.\n * Output:\n *      pPort_direction - Operation direction\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n *      RT_ERR_PORT_ID      - Invalid port number.\n * Note:\n *      The API can get 802.1x port-based operational direction information.\n */\nextern rtk_api_ret_t rtk_dot1x_portBasedDirection_get(rtk_port_t port, rtk_dot1x_direction_t *pPort_direction);\n\n/* Function Name:\n *      rtk_dot1x_macBasedEnable_set\n * Description:\n *      Set 802.1x mac-based port enable configuration\n * Input:\n *      port - Port id.\n *      enable - The status of 802.1x port.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK                   - OK\n *      RT_ERR_FAILED               - Failed\n *      RT_ERR_SMI                  - SMI access error\n *      RT_ERR_PORT_ID              - Invalid port number.\n *      RT_ERR_ENABLE               - Invalid enable input.\n *      RT_ERR_DOT1X_MACBASEDPNEN   - 802.1X mac-based enable error\n * Note:\n *      If a port is 802.1x MAC based network access control \"enabled\", the incoming packets should\n *       be authenticated so packets from that port won't be dropped or trapped to CPU.\n *      The status of 802.1x MAC-based network access control is as following:\n *      - DISABLED\n *      - ENABLED\n */\nextern rtk_api_ret_t rtk_dot1x_macBasedEnable_set(rtk_port_t port, rtk_enable_t enable);\n\n/* Function Name:\n *      rtk_dot1x_macBasedEnable_get\n * Description:\n *      Get 802.1x mac-based port enable configuration\n * Input:\n *      port - Port id.\n * Output:\n *      pEnable - The status of 802.1x port.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n *      RT_ERR_PORT_ID      - Invalid port number.\n * Note:\n *      If a port is 802.1x MAC based network access control \"enabled\", the incoming packets should\n *      be authenticated so packets from that port wont be dropped or trapped to CPU.\n *      The status of 802.1x MAC-based network access control is as following:\n *      - DISABLED\n *      - ENABLED\n */\nextern rtk_api_ret_t rtk_dot1x_macBasedEnable_get(rtk_port_t port, rtk_enable_t *pEnable);\n\n/* Function Name:\n *      rtk_dot1x_macBasedAuthMac_add\n * Description:\n *      Add an authenticated MAC to ASIC\n * Input:\n *      port        - Port id.\n *      pAuth_mac   - The authenticated MAC.\n *      fid         - filtering database.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK                   - OK\n *      RT_ERR_FAILED               - Failed\n *      RT_ERR_SMI                  - SMI access error\n *      RT_ERR_PORT_ID              - Invalid port number.\n *      RT_ERR_ENABLE               - Invalid enable input.\n *      RT_ERR_DOT1X_MACBASEDPNEN   - 802.1X mac-based enable error\n * Note:\n *      The API can add a 802.1x authenticated MAC address to port. If the MAC does not exist in LUT,\n *      user can't add this MAC to auth status.\n */\nextern rtk_api_ret_t rtk_dot1x_macBasedAuthMac_add(rtk_port_t port, rtk_mac_t *pAuth_mac, rtk_fid_t fid);\n\n/* Function Name:\n *      rtk_dot1x_macBasedAuthMac_del\n * Description:\n *      Delete an authenticated MAC to ASIC\n * Input:\n *      port - Port id.\n *      pAuth_mac - The authenticated MAC.\n *      fid - filtering database.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_MAC          - Invalid MAC address.\n *      RT_ERR_PORT_ID      - Invalid port number.\n * Note:\n *      The API can delete a 802.1x authenticated MAC address to port. It only change the auth status of\n *      the MAC and won't delete it from LUT.\n */\nextern rtk_api_ret_t rtk_dot1x_macBasedAuthMac_del(rtk_port_t port, rtk_mac_t *pAuth_mac, rtk_fid_t fid);\n\n/* Function Name:\n *      rtk_dot1x_macBasedDirection_set\n * Description:\n *      Set 802.1x mac-based operational direction configuration\n * Input:\n *      mac_direction - Operation direction\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK                   - OK\n *      RT_ERR_FAILED               - Failed\n *      RT_ERR_SMI                  - SMI access error\n *      RT_ERR_INPUT                - Invalid input parameter.\n *      RT_ERR_DOT1X_MACBASEDOPDIR  - 802.1X mac-based operation direction error\n * Note:\n *      The operate controlled direction of 802.1x mac-based network access control is as following:\n *      - BOTH\n *      - IN\n */\nextern rtk_api_ret_t rtk_dot1x_macBasedDirection_set(rtk_dot1x_direction_t mac_direction);\n\n/* Function Name:\n *      rtk_dot1x_macBasedDirection_get\n * Description:\n *      Get 802.1x mac-based operational direction configuration\n * Input:\n *      port - Port id.\n * Output:\n *      pMac_direction - Operation direction\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n * Note:\n *      The API can get 802.1x mac-based operational direction information.\n */\nextern rtk_api_ret_t rtk_dot1x_macBasedDirection_get(rtk_dot1x_direction_t *pMac_direction);\n\n/* Function Name:\n *      Set 802.1x guest VLAN configuration\n * Description:\n *      Set 802.1x mac-based operational direction configuration\n * Input:\n *      vid - 802.1x guest VLAN ID\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameter.\n * Note:\n *      The operate controlled 802.1x guest VLAN\n */\nextern rtk_api_ret_t rtk_dot1x_guestVlan_set(rtk_vlan_t vid);\n\n/* Function Name:\n *      rtk_dot1x_guestVlan_get\n * Description:\n *      Get 802.1x guest VLAN configuration\n * Input:\n *      None\n * Output:\n *      pVid - 802.1x guest VLAN ID\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n * Note:\n *      The API can get 802.1x guest VLAN information.\n */\nextern rtk_api_ret_t rtk_dot1x_guestVlan_get(rtk_vlan_t *pVid);\n\n/* Function Name:\n *      rtk_dot1x_guestVlan2Auth_set\n * Description:\n *      Set 802.1x guest VLAN to auth host configuration\n * Input:\n *      enable - The status of guest VLAN to auth host.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameter.\n * Note:\n *      The operational direction of 802.1x guest VLAN to auth host control is as following:\n *      - ENABLED\n *      - DISABLED\n */\nextern rtk_api_ret_t rtk_dot1x_guestVlan2Auth_set(rtk_enable_t enable);\n\n/* Function Name:\n *      rtk_dot1x_guestVlan2Auth_get\n * Description:\n *      Get 802.1x guest VLAN to auth host configuration\n * Input:\n *      None\n * Output:\n *      pEnable - The status of guest VLAN to auth host.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n * Note:\n *      The API can get 802.1x guest VLAN to auth host information.\n */\nextern rtk_api_ret_t rtk_dot1x_guestVlan2Auth_get(rtk_enable_t *pEnable);\n\n\n#endif /* __RTK_API_DOT1X_H__ */\n\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/eee.h",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * Purpose : RTL8367/RTL8367C switch high-level API\n *\n * Feature : The file includes EEE module high-layer API defination\n *\n */\n\n#ifndef __RTK_API_EEE_H__\n#define __RTK_API_EEE_H__\n\n/* Function Name:\n *      rtk_eee_init\n * Description:\n *      EEE function initialization.\n * Input:\n *      None\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n * Note:\n *      This API is used to initialize EEE status.\n */\nextern rtk_api_ret_t rtk_eee_init(void);\n\n/* Function Name:\n *      rtk_eee_portEnable_set\n * Description:\n *      Set enable status of EEE function.\n * Input:\n *      port - port id.\n *      enable - enable EEE status.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n *      RT_ERR_PORT_ID - Invalid port number.\n *      RT_ERR_ENABLE - Invalid enable input.\n * Note:\n *      This API can set EEE function to the specific port.\n *      The configuration of the port is as following:\n *      - DISABLE\n *      - ENABLE\n */\nextern rtk_api_ret_t rtk_eee_portEnable_set(rtk_port_t port, rtk_enable_t enable);\n\n/* Function Name:\n *      rtk_eee_portEnable_get\n * Description:\n *      Get port admin configuration of the specific port.\n * Input:\n *      port - Port id.\n * Output:\n *      pEnable - Back pressure status.\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n *      RT_ERR_PORT_ID - Invalid port number.\n * Note:\n *      This API can set EEE function to the specific port.\n *      The configuration of the port is as following:\n *      - DISABLE\n *      - ENABLE\n */\nextern rtk_api_ret_t rtk_eee_portEnable_get(rtk_port_t port, rtk_enable_t *pEnable);\n\n\n#endif /* __RTK_API_EEE_H__ */\n\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/i2c.h",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * Purpose : RTL8367/RTL8367C switch high-level API\n *\n * Feature : The file includes I2C module high-layer API defination\n *\n */\n\n\n#ifndef __RTK_API_I2C_H__\n#define __RTK_API_I2C_H__\n#include <rtk_types.h>\n\n#define I2C_GPIO_MAX_GROUP (3)\n\ntypedef enum rtk_I2C_16bit_mode_e{\n    I2C_LSB_16BIT_MODE = 0,\n    I2C_70B_LSB_16BIT_MODE,\n    I2C_Mode_END\n}rtk_I2C_16bit_mode_t;\n\n\ntypedef enum rtk_I2C_gpio_pin_e{\n    I2C_GPIO_PIN_8_9 = 0,\n    I2C_GPIO_PIN_15_16 ,\n    I2C_GPIO_PIN_35_36 ,\n    I2C_GPIO_PIN_END\n}rtk_I2C_gpio_pin_t;\n\n\n/* Function Name:\n *      rtk_i2c_data_read\n * Description:\n *      read i2c slave device register.\n * Input:\n *      deviceAddr   -   access Slave device address\n *      slaveRegAddr -   access Slave register address\n * Output:\n *      pRegData     -   read data\n * Return:\n *      RT_ERR_OK               - OK\n *      RT_ERR_NULL_POINTER     - input parameter is null pointer\n * Note:\n *      The API can access i2c slave and read i2c slave device register.\n */\nextern rtk_api_ret_t rtk_i2c_data_read(rtk_uint8 deviceAddr, rtk_uint32 slaveRegAddr, rtk_uint32 *pRegData);\n\n/* Function Name:\n *      rtk_i2c_data_write\n * Description:\n *      write data to i2c slave device register\n * Input:\n *      deviceAddr   -   access Slave device address\n *      slaveRegAddr -   access Slave register address\n *      regData      -   data to set\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - OK\n * Note:\n *      The API can access i2c slave and setting i2c slave device register.\n */\nextern rtk_api_ret_t rtk_i2c_data_write(rtk_uint8 deviceAddr, rtk_uint32 slaveRegAddr, rtk_uint32 regData);\n\n\n/* Function Name:\n *      rtk_i2c_init\n * Description:\n *      I2C smart function initialization.\n * Input:\n *      None\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n * Note:\n *      This API is used to initialize EEE status.\n *      need used GPIO pins\n *      OpenDrain and clock\n */\nextern rtk_api_ret_t rtk_i2c_init(void);\n\n/* Function Name:\n *      rtk_i2c_mode_set\n * Description:\n *      Set I2C data byte-order.\n * Input:\n *      i2cmode - byte-order mode\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_INPUT        - Invalid input parameter.\n * Note:\n *      This API can set I2c traffic's byte-order .\n */\nextern rtk_api_ret_t rtk_i2c_mode_set( rtk_I2C_16bit_mode_t i2cmode);\n\n/* Function Name:\n *      rtk_i2c_mode_get\n * Description:\n *      Get i2c traffic byte-order setting.\n * Input:\n *      None\n * Output:\n *      pI2cMode - i2c byte-order\n * Return:\n *      RT_ERR_OK               - OK\n *      RT_ERR_FAILED           - Failed\n *      RT_ERR_NULL_POINTER     - input parameter is null pointer\n * Note:\n *      The API can get i2c traffic byte-order setting.\n */\nextern rtk_api_ret_t rtk_i2c_mode_get( rtk_I2C_16bit_mode_t * pI2cMode);\n\n\n/* Function Name:\n *      rtk_i2c_gpioPinGroup_set\n * Description:\n *      Set i2c SDA & SCL used GPIO pins group.\n * Input:\n *      pins_group - GPIO pins group\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - OK\n *      RT_ERR_FAILED           - Failed\n *      RT_ERR_INPUT        - Invalid input parameter.\n * Note:\n *      The API can set i2c used gpio pins group.\n *      There are three group pins could be used\n */\nextern rtk_api_ret_t rtk_i2c_gpioPinGroup_set( rtk_I2C_gpio_pin_t pins_group);\n\n/* Function Name:\n *      rtk_i2c_gpioPinGroup_get\n * Description:\n *      Get i2c SDA & SCL used GPIO pins group.\n * Input:\n *      None\n * Output:\n *      pPins_group - GPIO pins group\n * Return:\n *      RT_ERR_OK               - OK\n *      RT_ERR_NULL_POINTER     - input parameter is null pointer\n * Note:\n *      The API can get i2c used gpio pins group.\n *      There are three group pins could be used\n */\nextern rtk_api_ret_t rtk_i2c_gpioPinGroup_get(rtk_I2C_gpio_pin_t * pPins_group);\n\n\n\n\n\n\n\n#endif\n\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/igmp.h",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * Purpose : RTL8367/RTL8367C switch high-level API\n *\n * Feature : The file includes IGMP module high-layer API defination\n *\n */\n\n#ifndef __RTK_API_IGMP_H__\n#define __RTK_API_IGMP_H__\n\n/*\n * Data Type Declaration\n */\ntypedef enum rtk_igmp_type_e\n{\n    IGMP_IPV4 = 0,\n    IGMP_PPPOE_IPV4,\n    IGMP_MLD,\n    IGMP_PPPOE_MLD,\n    IGMP_TYPE_END\n} rtk_igmp_type_t;\n\ntypedef enum rtk_trap_igmp_action_e\n{\n    IGMP_ACTION_FORWARD = 0,\n    IGMP_ACTION_TRAP2CPU,\n    IGMP_ACTION_DROP,\n    IGMP_ACTION_ASIC,\n    IGMP_ACTION_END\n} rtk_igmp_action_t;\n\ntypedef enum rtk_igmp_protocol_e\n{\n    PROTOCOL_IGMPv1 = 0,\n    PROTOCOL_IGMPv2,\n    PROTOCOL_IGMPv3,\n    PROTOCOL_MLDv1,\n    PROTOCOL_MLDv2,\n    PROTOCOL_END\n} rtk_igmp_protocol_t;\n\ntypedef enum rtk_igmp_tableFullAction_e\n{\n    IGMP_TABLE_FULL_FORWARD = 0,\n    IGMP_TABLE_FULL_DROP,\n    IGMP_TABLE_FULL_TRAP,\n    IGMP_TABLE_FULL_OP_END\n}rtk_igmp_tableFullAction_t;\n\ntypedef enum rtk_igmp_checksumErrorAction_e\n{\n    IGMP_CRC_ERR_DROP = 0,\n    IGMP_CRC_ERR_TRAP,\n    IGMP_CRC_ERR_FORWARD,\n    IGMP_CRC_ERR_OP_END\n}rtk_igmp_checksumErrorAction_t;\n\ntypedef enum rtk_igmp_bypassGroup_e\n{\n    IGMP_BYPASS_224_0_0_X = 0,\n    IGMP_BYPASS_224_0_1_X,\n    IGMP_BYPASS_239_255_255_X,\n    IGMP_BYPASS_IPV6_00XX,\n    IGMP_BYPASS_GROUP_END\n}rtk_igmp_bypassGroup_t;\n\n\ntypedef struct rtk_igmp_dynamicRouterPort_s\n{\n    rtk_enable_t    dynamicRouterPort0Valid;\n    rtk_port_t      dynamicRouterPort0;\n    rtk_uint32      dynamicRouterPort0Timer;\n    rtk_enable_t    dynamicRouterPort1Valid;\n    rtk_port_t      dynamicRouterPort1;\n    rtk_uint32      dynamicRouterPort1Timer;\n\n}rtk_igmp_dynamicRouterPort_t;\n\ntypedef struct rtk_igmp_rxPktEnable_s\n{\n    rtk_enable_t rxQuery;\n    rtk_enable_t rxReport;\n    rtk_enable_t rxLeave;\n    rtk_enable_t rxMRP;\n    rtk_enable_t rxMcast;\n}rtk_igmp_rxPktEnable_t;\n\ntypedef struct rtk_igmp_groupInfo_s\n{\n    rtk_enable_t    valid;\n    rtk_portmask_t  member;\n    rtk_uint32      timer[RTK_PORT_MAX];\n    rtk_uint32      reportSuppFlag;\n}rtk_igmp_groupInfo_t;\n\ntypedef enum rtk_igmp_ReportLeaveFwdAct_e\n{\n    IGMP_REPORT_LEAVE_TO_ROUTER = 0,\n    IGMP_REPORT_LEAVE_TO_ALLPORT,\n    IGMP_REPORT_LEAVE_TO_ROUTER_PORT_ADV,\n    IGMP_REPORT_LEAVE_ACT_END\n}rtk_igmp_ReportLeaveFwdAct_t;\n\n/* Function Name:\n *      rtk_igmp_init\n * Description:\n *      This API enables H/W IGMP and set a default initial configuration.\n * Input:\n *      None.\n * Output:\n *      None.\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n * Note:\n *      This API enables H/W IGMP and set a default initial configuration.\n */\nextern rtk_api_ret_t rtk_igmp_init(void);\n\n/* Function Name:\n *      rtk_igmp_state_set\n * Description:\n *      This API set H/W IGMP state.\n * Input:\n *      enabled     - H/W IGMP state\n * Output:\n *      None.\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n *      RT_ERR_INPUT           - Error parameter\n * Note:\n *      This API set H/W IGMP state.\n */\nextern rtk_api_ret_t rtk_igmp_state_set(rtk_enable_t enabled);\n\n/* Function Name:\n *      rtk_igmp_state_get\n * Description:\n *      This API get H/W IGMP state.\n * Input:\n *      None.\n * Output:\n *      pEnabled        - H/W IGMP state\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n *      RT_ERR_INPUT           - Error parameter\n * Note:\n *      This API set current H/W IGMP state.\n */\nextern rtk_api_ret_t rtk_igmp_state_get(rtk_enable_t *pEnabled);\n\n/* Function Name:\n *      rtk_igmp_static_router_port_set\n * Description:\n *      Configure static router port\n * Input:\n *      pPortmask    - Static Port mask\n * Output:\n *      None.\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n *      RT_ERR_PORT_MASK       - Error parameter\n * Note:\n *      This API set static router port\n */\nextern rtk_api_ret_t rtk_igmp_static_router_port_set(rtk_portmask_t *pPortmask);\n\n/* Function Name:\n *      rtk_igmp_static_router_port_get\n * Description:\n *      Get static router port\n * Input:\n *      None.\n * Output:\n *      pPortmask       - Static port mask\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n *      RT_ERR_PORT_MASK       - Error parameter\n * Note:\n *      This API get static router port\n */\nextern rtk_api_ret_t rtk_igmp_static_router_port_get(rtk_portmask_t *pPortmask);\n\n/* Function Name:\n *      rtk_igmp_protocol_set\n * Description:\n *      set IGMP/MLD protocol action\n * Input:\n *      port        - Port ID\n *      protocol    - IGMP/MLD protocol\n *      action      - Per-port and per-protocol IGMP action seeting\n * Output:\n *      None.\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n *      RT_ERR_PORT_MASK       - Error parameter\n * Note:\n *      This API set IGMP/MLD protocol action\n */\nextern rtk_api_ret_t rtk_igmp_protocol_set(rtk_port_t port, rtk_igmp_protocol_t protocol, rtk_igmp_action_t action);\n\n/* Function Name:\n *      rtk_igmp_protocol_get\n * Description:\n *      set IGMP/MLD protocol action\n * Input:\n *      port        - Port ID\n *      protocol    - IGMP/MLD protocol\n *      action      - Per-port and per-protocol IGMP action seeting\n * Output:\n *      None.\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n *      RT_ERR_PORT_MASK       - Error parameter\n * Note:\n *      This API set IGMP/MLD protocol action\n */\nextern rtk_api_ret_t rtk_igmp_protocol_get(rtk_port_t port, rtk_igmp_protocol_t protocol, rtk_igmp_action_t *pAction);\n\n/* Function Name:\n *      rtk_igmp_fastLeave_set\n * Description:\n *      set IGMP/MLD FastLeave state\n * Input:\n *      state       - ENABLED: Enable FastLeave, DISABLED: disable FastLeave\n * Output:\n *      None.\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_INPUT           - Error Input\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n * Note:\n *      This API set IGMP/MLD FastLeave state\n */\nextern rtk_api_ret_t rtk_igmp_fastLeave_set(rtk_enable_t state);\n\n/* Function Name:\n *      rtk_igmp_fastLeave_get\n * Description:\n *      get IGMP/MLD FastLeave state\n * Input:\n *      None\n * Output:\n *      pState      - ENABLED: Enable FastLeave, DISABLED: disable FastLeave\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_NULL_POINTER    - NULL pointer\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n * Note:\n *      This API get IGMP/MLD FastLeave state\n */\nextern rtk_api_ret_t rtk_igmp_fastLeave_get(rtk_enable_t *pState);\n\n/* Function Name:\n *      rtk_igmp_maxGroup_set\n * Description:\n *      Set per port multicast group learning limit.\n * Input:\n *      port        - Port ID\n *      group       - The number of multicast group learning limit.\n * Output:\n *      None.\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_PORT_ID         - Error Port ID\n *      RT_ERR_OUT_OF_RANGE    - parameter out of range\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n * Note:\n *      This API set per port multicast group learning limit.\n */\nextern rtk_api_ret_t rtk_igmp_maxGroup_set(rtk_port_t port, rtk_uint32 group);\n\n/* Function Name:\n *      rtk_igmp_maxGroup_get\n * Description:\n *      Get per port multicast group learning limit.\n * Input:\n *      port        - Port ID\n * Output:\n *      pGroup      - The number of multicast group learning limit.\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_PORT_ID         - Error Port ID\n *      RT_ERR_NULL_POINTER    - Null pointer\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n * Note:\n *      This API get per port multicast group learning limit.\n */\nextern rtk_api_ret_t rtk_igmp_maxGroup_get(rtk_port_t port, rtk_uint32 *pGroup);\n\n/* Function Name:\n *      rtk_igmp_currentGroup_get\n * Description:\n *      Get per port multicast group learning count.\n * Input:\n *      port        - Port ID\n * Output:\n *      pGroup      - The number of multicast group learning count.\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_PORT_ID         - Error Port ID\n *      RT_ERR_NULL_POINTER    - Null pointer\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n * Note:\n *      This API get per port multicast group learning count.\n */\nextern rtk_api_ret_t rtk_igmp_currentGroup_get(rtk_port_t port, rtk_uint32 *pGroup);\n\n/* Function Name:\n *      rtk_igmp_tableFullAction_set\n * Description:\n *      set IGMP/MLD Table Full Action\n * Input:\n *      action      - Table Full Action\n * Output:\n *      None.\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_INPUT           - Error Input\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n * Note:\n */\nextern rtk_api_ret_t rtk_igmp_tableFullAction_set(rtk_igmp_tableFullAction_t action);\n\n/* Function Name:\n *      rtk_igmp_tableFullAction_get\n * Description:\n *      get IGMP/MLD Table Full Action\n * Input:\n *      None\n * Output:\n *      pAction     - Table Full Action\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_NULL_POINTER    - Null pointer\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n * Note:\n */\nextern rtk_api_ret_t rtk_igmp_tableFullAction_get(rtk_igmp_tableFullAction_t *pAction);\n\n/* Function Name:\n *      rtk_igmp_checksumErrorAction_set\n * Description:\n *      set IGMP/MLD Checksum Error Action\n * Input:\n *      action      - Checksum error Action\n * Output:\n *      None.\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_INPUT           - Error Input\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n * Note:\n */\nextern rtk_api_ret_t rtk_igmp_checksumErrorAction_set(rtk_igmp_checksumErrorAction_t action);\n\n/* Function Name:\n *      rtk_igmp_checksumErrorAction_get\n * Description:\n *      get IGMP/MLD Checksum Error Action\n * Input:\n *      None\n * Output:\n *      pAction     - Checksum error Action\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_NULL_POINTER    - Null pointer\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n * Note:\n */\nextern rtk_api_ret_t rtk_igmp_checksumErrorAction_get(rtk_igmp_checksumErrorAction_t *pAction);\n\n/* Function Name:\n *      rtk_igmp_leaveTimer_set\n * Description:\n *      set IGMP/MLD Leave timer\n * Input:\n *      timer       - Leave timer\n * Output:\n *      None.\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_INPUT           - Error Input\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n * Note:\n */\nextern rtk_api_ret_t rtk_igmp_leaveTimer_set(rtk_uint32 timer);\n\n/* Function Name:\n *      rtk_igmp_leaveTimer_get\n * Description:\n *      get IGMP/MLD Leave timer\n * Input:\n *      None\n * Output:\n *      pTimer      - Leave Timer.\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_NULL_POINTER    - Null pointer\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n * Note:\n */\nextern rtk_api_ret_t rtk_igmp_leaveTimer_get(rtk_uint32 *pTimer);\n\n/* Function Name:\n *      rtk_igmp_queryInterval_set\n * Description:\n *      set IGMP/MLD Query Interval\n * Input:\n *      interval     - Query Interval\n * Output:\n *      None.\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_INPUT           - Error Input\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n * Note:\n */\nextern rtk_api_ret_t rtk_igmp_queryInterval_set(rtk_uint32 interval);\n\n/* Function Name:\n *      rtk_igmp_queryInterval_get\n * Description:\n *      get IGMP/MLD Query Interval\n * Input:\n *      None.\n * Output:\n *      pInterval   - Query Interval\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_NULL_POINTER    - Null pointer\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n * Note:\n */\nextern rtk_api_ret_t rtk_igmp_queryInterval_get(rtk_uint32 *pInterval);\n\n/* Function Name:\n *      rtk_igmp_robustness_set\n * Description:\n *      set IGMP/MLD Robustness value\n * Input:\n *      robustness     - Robustness value\n * Output:\n *      None.\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_INPUT           - Error Input\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n * Note:\n */\nextern rtk_api_ret_t rtk_igmp_robustness_set(rtk_uint32 robustness);\n\n/* Function Name:\n *      rtk_igmp_robustness_get\n * Description:\n *      get IGMP/MLD Robustness value\n * Input:\n *      None\n * Output:\n *      pRobustness     - Robustness value.\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_NULL_POINTER    - Null pointer\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n * Note:\n */\nextern rtk_api_ret_t rtk_igmp_robustness_get(rtk_uint32 *pRobustness);\n\n/* Function Name:\n *      rtk_igmp_dynamicRouterRortAllow_set\n * Description:\n *      Configure dynamic router port allow option\n * Input:\n *      pPortmask    - Dynamic Port allow mask\n * Output:\n *      None.\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n *      RT_ERR_PORT_MASK       - Error parameter\n * Note:\n *\n */\nextern rtk_api_ret_t rtk_igmp_dynamicRouterPortAllow_set(rtk_portmask_t *pPortmask);\n\n/* Function Name:\n *      rtk_igmp_dynamicRouterRortAllow_get\n * Description:\n *      Get dynamic router port allow option\n * Input:\n *      None.\n * Output:\n *      pPortmask    - Dynamic Port allow mask\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n *      RT_ERR_PORT_MASK       - Error parameter\n * Note:\n *\n */\nextern rtk_api_ret_t rtk_igmp_dynamicRouterPortAllow_get(rtk_portmask_t *pPortmask);\n\n/* Function Name:\n *      rtk_igmp_dynamicRouterPort_get\n * Description:\n *      Get dynamic router port\n * Input:\n *      None.\n * Output:\n *      pDynamicRouterPort    - Dynamic Router Port\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_NULL_POINTER    - Null pointer\n *      RT_ERR_SMI             - SMI access error\n *      RT_ERR_PORT_MASK       - Error parameter\n * Note:\n *\n */\nextern rtk_api_ret_t rtk_igmp_dynamicRouterPort_get(rtk_igmp_dynamicRouterPort_t *pDynamicRouterPort);\n\n/* Function Name:\n *      rtk_igmp_suppressionEnable_set\n * Description:\n *      Configure IGMPv1/v2 & MLDv1 Report/Leave/Done suppression\n * Input:\n *      reportSuppression   - Report suppression\n *      leaveSuppression    - Leave suppression\n * Output:\n *      None.\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n *      RT_ERR_INPUT           - Error Input\n * Note:\n *\n */\nextern rtk_api_ret_t rtk_igmp_suppressionEnable_set(rtk_enable_t reportSuppression, rtk_enable_t leaveSuppression);\n\n/* Function Name:\n *      rtk_igmp_suppressionEnable_get\n * Description:\n *      Get IGMPv1/v2 & MLDv1 Report/Leave/Done suppression\n * Input:\n *      None\n * Output:\n *      pReportSuppression  - Report suppression\n *      pLeaveSuppression   - Leave suppression\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n *      RT_ERR_NULL_POINTER    - Null pointer\n * Note:\n *\n */\nextern rtk_api_ret_t rtk_igmp_suppressionEnable_get(rtk_enable_t *pReportSuppression, rtk_enable_t *pLeaveSuppression);\n\n/* Function Name:\n *      rtk_igmp_portRxPktEnable_set\n * Description:\n *      Configure IGMP/MLD RX Packet configuration\n * Input:\n *      port       - Port ID\n *      pRxCfg     - RX Packet Configuration\n * Output:\n *      None.\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n *      RT_ERR_INPUT           - Error Input\n *      RT_ERR_NULL_POINTER    - Null pointer\n * Note:\n *\n */\nextern rtk_api_ret_t rtk_igmp_portRxPktEnable_set(rtk_port_t port, rtk_igmp_rxPktEnable_t *pRxCfg);\n\n/* Function Name:\n *      rtk_igmp_portRxPktEnable_get\n * Description:\n *      Get IGMP/MLD RX Packet configuration\n * Input:\n *      port       - Port ID\n *      pRxCfg     - RX Packet Configuration\n * Output:\n *      None.\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n *      RT_ERR_INPUT           - Error Input\n *      RT_ERR_NULL_POINTER    - Null pointer\n * Note:\n *\n */\nextern rtk_api_ret_t rtk_igmp_portRxPktEnable_get(rtk_port_t port, rtk_igmp_rxPktEnable_t *pRxCfg);\n\n/* Function Name:\n *      rtk_igmp_groupInfo_get\n * Description:\n *      Get IGMP/MLD Group database\n * Input:\n *      indes       - Index (0~255)\n * Output:\n *      pGroup      - Group database information.\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n *      RT_ERR_INPUT           - Error Input\n *      RT_ERR_NULL_POINTER    - Null pointer\n * Note:\n *\n */\nextern rtk_api_ret_t rtk_igmp_groupInfo_get(rtk_uint32 index, rtk_igmp_groupInfo_t *pGroup);\n\n/* Function Name:\n *      rtk_igmp_ReportLeaveFwdAction_set\n * Description:\n *      Set Report Leave packet forwarding action\n * Input:\n *      action      - Action\n * Output:\n *      None.\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n *      RT_ERR_INPUT           - Error Input\n * Note:\n *\n */\nextern rtk_api_ret_t rtk_igmp_ReportLeaveFwdAction_set(rtk_igmp_ReportLeaveFwdAct_t action);\n\n/* Function Name:\n *      rtk_igmp_ReportLeaveFwdAction_get\n * Description:\n *      Get Report Leave packet forwarding action\n * Input:\n *      action      - Action\n * Output:\n *      None.\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n *      RT_ERR_INPUT           - Error Input\n *      RT_ERR_NULL_POINTER    - Null Pointer\n * Note:\n *\n */\nextern rtk_api_ret_t rtk_igmp_ReportLeaveFwdAction_get(rtk_igmp_ReportLeaveFwdAct_t *pAction);\n\n/* Function Name:\n *      rtk_igmp_dropLeaveZeroEnable_set\n * Description:\n *      Set the function of droppping Leave packet with group IP = 0.0.0.0\n * Input:\n *      enabled      - Action 1: drop, 0:pass\n * Output:\n *      None.\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n *      RT_ERR_INPUT           - Error Input\n * Note:\n *\n */\nextern rtk_api_ret_t rtk_igmp_dropLeaveZeroEnable_set(rtk_enable_t enabled);\n\n/* Function Name:\n *      rtk_igmp_dropLeaveZeroEnable_get\n * Description:\n *      Get the function of droppping Leave packet with group IP = 0.0.0.0\n * Input:\n *      None\n * Output:\n *      pEnabled.   - Action 1: drop, 0:pass\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n *      RT_ERR_INPUT           - Error Input\n *      RT_ERR_NULL_POINTER    - Null Pointer\n * Note:\n *\n */\nextern rtk_api_ret_t rtk_igmp_dropLeaveZeroEnable_get(rtk_enable_t *pEnabled);\n\n/* Function Name:\n *      rtk_igmp_bypassGroupRange_set\n * Description:\n *      Set Bypass group\n * Input:\n *      group       - bypassed group\n *      enabled     - enabled 1: Bypassed, 0: not bypass\n * Output:\n *      None.\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n *      RT_ERR_INPUT           - Error Input\n * Note:\n *\n */\nextern rtk_api_ret_t rtk_igmp_bypassGroupRange_set(rtk_igmp_bypassGroup_t group, rtk_enable_t enabled);\n\n/* Function Name:\n *      rtk_igmp_bypassGroupRange_get\n * Description:\n *      get Bypass group\n * Input:\n *      group       - bypassed group\n * Output:\n *      pEnable     - enabled 1: Bypassed, 0: not bypass\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n *      RT_ERR_INPUT           - Error Input\n *      RT_ERR_NULL_POINTER    - Null Pointer\n * Note:\n *\n */\nextern rtk_api_ret_t rtk_igmp_bypassGroupRange_get(rtk_igmp_bypassGroup_t group, rtk_enable_t *pEnable);\n\n#endif /* __RTK_API_IGMP_H__ */\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/interrupt.h",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * Purpose : RTL8367/RTL8367C switch high-level API\n *\n * Feature : The file includes Interrupt module high-layer API defination\n *\n */\n\n#ifndef __RTK_API_INTERRUPT_H__\n#define __RTK_API_INTERRUPT_H__\n\n\n/*\n * Data Type Declaration\n */\n#define RTK_MAX_NUM_OF_INTERRUPT_TYPE               1\n\n\ntypedef struct  rtk_int_status_s\n{\n    rtk_uint16 value[RTK_MAX_NUM_OF_INTERRUPT_TYPE];\n} rtk_int_status_t;\n\ntypedef struct rtk_int_info_s\n{\n    rtk_portmask_t  portMask;\n    rtk_uint32      meterMask;\n    rtk_uint32      systemLearnOver;\n}rtk_int_info_t;\n\ntypedef enum rtk_int_type_e\n{\n    INT_TYPE_LINK_STATUS = 0,\n    INT_TYPE_METER_EXCEED,\n    INT_TYPE_LEARN_LIMIT,\n    INT_TYPE_LINK_SPEED,\n    INT_TYPE_CONGEST,\n    INT_TYPE_GREEN_FEATURE,\n    INT_TYPE_LOOP_DETECT,\n    INT_TYPE_8051,\n    INT_TYPE_CABLE_DIAG,\n    INT_TYPE_ACL,\n    INT_TYPE_RESERVED, /* Unused */\n    INT_TYPE_SLIENT,\n    INT_TYPE_END\n}rtk_int_type_t;\n\ntypedef enum rtk_int_advType_e\n{\n    ADV_L2_LEARN_PORT_MASK = 0,\n    ADV_SPEED_CHANGE_PORT_MASK,\n    ADV_SPECIAL_CONGESTION_PORT_MASK,\n    ADV_PORT_LINKDOWN_PORT_MASK,\n    ADV_PORT_LINKUP_PORT_MASK,\n    ADV_METER_EXCEED_MASK,\n    ADV_RLDP_LOOPED,\n    ADV_RLDP_RELEASED,\n    ADV_END,\n} rtk_int_advType_t;\n\ntypedef enum rtk_int_polarity_e\n{\n    INT_POLAR_HIGH = 0,\n    INT_POLAR_LOW,\n    INT_POLAR_END\n} rtk_int_polarity_t;\n\n/* Function Name:\n *      rtk_int_polarity_set\n * Description:\n *      Set interrupt polarity configuration.\n * Input:\n *      type - Interruptpolarity type.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n * Note:\n *      The API can set interrupt polarity configuration.\n */\nextern rtk_api_ret_t rtk_int_polarity_set(rtk_int_polarity_t type);\n\n/* Function Name:\n *      rtk_int_polarity_get\n * Description:\n *      Get interrupt polarity configuration.\n * Input:\n *      None\n * Output:\n *      pType - Interruptpolarity type.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n * Note:\n *      The API can get interrupt polarity configuration.\n */\nextern rtk_api_ret_t rtk_int_polarity_get(rtk_int_polarity_t *pType);\n\n/* Function Name:\n *      rtk_int_control_set\n * Description:\n *      Set interrupt trigger status configuration.\n * Input:\n *      type - Interrupt type.\n *      enable - Interrupt status.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n *      RT_ERR_ENABLE       - Invalid enable input.\n * Note:\n *      The API can set interrupt status configuration.\n *      The interrupt trigger status is shown in the following:\n *      - INT_TYPE_LINK_STATUS\n *      - INT_TYPE_METER_EXCEED\n *      - INT_TYPE_LEARN_LIMIT\n *      - INT_TYPE_LINK_SPEED\n *      - INT_TYPE_CONGEST\n *      - INT_TYPE_GREEN_FEATURE\n *      - INT_TYPE_LOOP_DETECT\n *      - INT_TYPE_8051,\n *      - INT_TYPE_CABLE_DIAG,\n *      - INT_TYPE_ACL,\n *      - INT_TYPE_SLIENT\n */\nextern rtk_api_ret_t rtk_int_control_set(rtk_int_type_t type, rtk_enable_t enable);\n\n/* Function Name:\n *      rtk_int_control_get\n * Description:\n *      Get interrupt trigger status configuration.\n * Input:\n *      type - Interrupt type.\n * Output:\n *      pEnable - Interrupt status.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n * Note:\n *      The API can get interrupt status configuration.\n *      The interrupt trigger status is shown in the following:\n *      - INT_TYPE_LINK_STATUS\n *      - INT_TYPE_METER_EXCEED\n *      - INT_TYPE_LEARN_LIMIT\n *      - INT_TYPE_LINK_SPEED\n *      - INT_TYPE_CONGEST\n *      - INT_TYPE_GREEN_FEATURE\n *      - INT_TYPE_LOOP_DETECT\n *      - INT_TYPE_8051,\n *      - INT_TYPE_CABLE_DIAG,\n *      - INT_TYPE_ACL,\n *      - INT_TYPE_SLIENT\n */\nextern rtk_api_ret_t rtk_int_control_get(rtk_int_type_t type, rtk_enable_t* pEnable);\n\n/* Function Name:\n *      rtk_int_status_set\n * Description:\n *      Set interrupt trigger status to clean.\n * Input:\n *      None\n * Output:\n *      pStatusMask - Interrupt status bit mask.\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n *      RT_ERR_INPUT - Invalid input parameters.\n * Note:\n *      The API can clean interrupt trigger status when interrupt happened.\n *      The interrupt trigger status is shown in the following:\n *      - INT_TYPE_LINK_STATUS    (value[0] (Bit0))\n *      - INT_TYPE_METER_EXCEED   (value[0] (Bit1))\n *      - INT_TYPE_LEARN_LIMIT    (value[0] (Bit2))\n *      - INT_TYPE_LINK_SPEED     (value[0] (Bit3))\n *      - INT_TYPE_CONGEST        (value[0] (Bit4))\n *      - INT_TYPE_GREEN_FEATURE  (value[0] (Bit5))\n *      - INT_TYPE_LOOP_DETECT    (value[0] (Bit6))\n *      - INT_TYPE_8051           (value[0] (Bit7))\n *      - INT_TYPE_CABLE_DIAG     (value[0] (Bit8))\n *      - INT_TYPE_ACL            (value[0] (Bit9))\n *      - INT_TYPE_SLIENT         (value[0] (Bit11))\n *      The status will be cleared after execute this API.\n */\nextern rtk_api_ret_t rtk_int_status_set(rtk_int_status_t *pStatusMask);\n\n/* Function Name:\n *      rtk_int_status_get\n * Description:\n *      Get interrupt trigger status.\n * Input:\n *      None\n * Output:\n *      pStatusMask - Interrupt status bit mask.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n * Note:\n *      The API can get interrupt trigger status when interrupt happened.\n *      The interrupt trigger status is shown in the following:\n *      - INT_TYPE_LINK_STATUS    (value[0] (Bit0))\n *      - INT_TYPE_METER_EXCEED   (value[0] (Bit1))\n *      - INT_TYPE_LEARN_LIMIT    (value[0] (Bit2))\n *      - INT_TYPE_LINK_SPEED     (value[0] (Bit3))\n *      - INT_TYPE_CONGEST        (value[0] (Bit4))\n *      - INT_TYPE_GREEN_FEATURE  (value[0] (Bit5))\n *      - INT_TYPE_LOOP_DETECT    (value[0] (Bit6))\n *      - INT_TYPE_8051           (value[0] (Bit7))\n *      - INT_TYPE_CABLE_DIAG     (value[0] (Bit8))\n *      - INT_TYPE_ACL            (value[0] (Bit9))\n *      - INT_TYPE_SLIENT         (value[0] (Bit11))\n *\n */\nextern rtk_api_ret_t rtk_int_status_get(rtk_int_status_t* pStatusMask);\n\n/* Function Name:\n *      rtk_int_advanceInfo_get\n * Description:\n *      Get interrupt advanced information.\n * Input:\n *      adv_type - Advanced interrupt type.\n * Output:\n *      info - Information per type.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n * Note:\n *      This API can get advanced information when interrupt happened.\n *      The status will be cleared after execute this API.\n */\nextern rtk_api_ret_t rtk_int_advanceInfo_get(rtk_int_advType_t adv_type, rtk_int_info_t* info);\n\n\n#endif /* __RTK_API_INTERRUPT_H__ */\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/l2.h",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * Purpose : RTL8367/RTL8367C switch high-level API\n *\n * Feature : The file includes L2 module high-layer API defination\n *\n */\n\n#ifndef __RTK_API_L2_H__\n#define __RTK_API_L2_H__\n\n\n/*\n * Data Type Declaration\n */\n#define RTK_MAX_NUM_OF_LEARN_LIMIT                  (rtk_switch_maxLutAddrNumber_get())\n\n#define RTK_MAC_ADDR_LEN                            6\n#define RTK_MAX_LUT_ADDRESS                         (RTK_MAX_NUM_OF_LEARN_LIMIT)\n#define RTK_MAX_LUT_ADDR_ID                         (RTK_MAX_LUT_ADDRESS - 1)\n\ntypedef rtk_uint32 rtk_l2_age_time_t;\n\ntypedef enum rtk_l2_flood_type_e\n{\n    FLOOD_UNKNOWNDA = 0,\n    FLOOD_UNKNOWNMC,\n    FLOOD_BC,\n    FLOOD_END\n} rtk_l2_flood_type_t;\n\ntypedef rtk_uint32 rtk_l2_flushItem_t;\n\ntypedef enum rtk_l2_flushType_e\n{\n    FLUSH_TYPE_BY_PORT = 0,       /* physical port       */\n    FLUSH_TYPE_BY_PORT_VID,       /* physical port + VID */\n    FLUSH_TYPE_BY_PORT_FID,       /* physical port + FID */\n    FLUSH_TYPE_END\n} rtk_l2_flushType_t;\n\ntypedef struct rtk_l2_flushCfg_s\n{\n    rtk_enable_t    flushByVid;\n    rtk_vlan_t      vid;\n    rtk_enable_t    flushByFid;\n    rtk_uint32      fid;\n    rtk_enable_t    flushByPort;\n    rtk_port_t      port;\n    rtk_enable_t    flushByMac;\n    rtk_mac_t       ucastAddr;\n    rtk_enable_t    flushStaticAddr;\n    rtk_enable_t    flushAddrOnAllPorts; /* this is used when flushByVid */\n} rtk_l2_flushCfg_t;\n\ntypedef enum rtk_l2_read_method_e{\n\n    READMETHOD_MAC = 0,\n    READMETHOD_ADDRESS,\n    READMETHOD_NEXT_ADDRESS,\n    READMETHOD_NEXT_L2UC,\n    READMETHOD_NEXT_L2MC,\n    READMETHOD_NEXT_L3MC,\n    READMETHOD_NEXT_L2L3MC,\n    READMETHOD_NEXT_L2UCSPA,\n    READMETHOD_END\n}rtk_l2_read_method_t;\n\n/* l2 limit learning count action */\ntypedef enum rtk_l2_limitLearnCntAction_e\n{\n    LIMIT_LEARN_CNT_ACTION_DROP = 0,\n    LIMIT_LEARN_CNT_ACTION_FORWARD,\n    LIMIT_LEARN_CNT_ACTION_TO_CPU,\n    LIMIT_LEARN_CNT_ACTION_END\n} rtk_l2_limitLearnCntAction_t;\n\ntypedef enum rtk_l2_ipmc_lookup_type_e\n{\n    LOOKUP_MAC = 0,\n    LOOKUP_IP,\n    LOOKUP_IP_VID,\n    LOOKUP_END\n} rtk_l2_ipmc_lookup_type_t;\n\n/* l2 address table - unicast data structure */\ntypedef struct rtk_l2_ucastAddr_s\n{\n    rtk_mac_t       mac;\n    rtk_uint32      ivl;\n    rtk_uint32      cvid;\n    rtk_uint32      fid;\n    rtk_uint32      efid;\n    rtk_uint32      port;\n    rtk_uint32      sa_block;\n    rtk_uint32      da_block;\n    rtk_uint32      auth;\n    rtk_uint32      is_static;\n    rtk_uint32      priority;\n    rtk_uint32      sa_pri_en;\n    rtk_uint32      fwd_pri_en;\n    rtk_uint32      address;\n}rtk_l2_ucastAddr_t;\n\n/* l2 address table - multicast data structure */\ntypedef struct rtk_l2_mcastAddr_s\n{\n    rtk_uint32      vid;\n    rtk_mac_t       mac;\n    rtk_uint32      fid;\n    rtk_portmask_t  portmask;\n    rtk_uint32      ivl;\n    rtk_uint32      priority;\n    rtk_uint32      fwd_pri_en;\n    rtk_uint32      igmp_asic;\n    rtk_uint32      igmp_index;\n    rtk_uint32      address;\n}rtk_l2_mcastAddr_t;\n\n/* l2 address table - ip multicast data structure */\ntypedef struct rtk_l2_ipMcastAddr_s\n{\n    ipaddr_t        dip;\n    ipaddr_t        sip;\n    rtk_portmask_t  portmask;\n    rtk_uint32      priority;\n    rtk_uint32      fwd_pri_en;\n    rtk_uint32      igmp_asic;\n    rtk_uint32      igmp_index;\n    rtk_uint32      address;\n}rtk_l2_ipMcastAddr_t;\n\n/* l2 address table - ip VID multicast data structure */\ntypedef struct rtk_l2_ipVidMcastAddr_s\n{\n    ipaddr_t        dip;\n    ipaddr_t        sip;\n    rtk_uint32      vid;\n    rtk_portmask_t  portmask;\n    rtk_uint32      address;\n}rtk_l2_ipVidMcastAddr_t;\n\ntypedef struct rtk_l2_addr_table_s\n{\n    rtk_uint32  index;\n    ipaddr_t    sip;\n    ipaddr_t    dip;\n    rtk_mac_t   mac;\n    rtk_uint32  sa_block;\n    rtk_uint32  auth;\n    rtk_portmask_t  portmask;\n    rtk_uint32  age;\n    rtk_uint32  ivl;\n    rtk_uint32  cvid;\n    rtk_uint32  fid;\n    rtk_uint32  is_ipmul;\n    rtk_uint32  is_static;\n    rtk_uint32  is_ipvidmul;\n    rtk_uint32  l3_vid;\n}rtk_l2_addr_table_t;\n\ntypedef enum rtk_l2_clearStatus_e\n{\n    L2_CLEAR_STATE_FINISH = 0,\n    L2_CLEAR_STATE_BUSY,\n    L2_CLEAR_STATE_END\n}rtk_l2_clearStatus_t;\n\n/* Function Name:\n *      rtk_l2_init\n * Description:\n *      Initialize l2 module of the specified device.\n * Input:\n *      None\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK          - OK\n *      RT_ERR_FAILED      - Failed\n *      RT_ERR_SMI         - SMI access error\n * Note:\n *      Initialize l2 module before calling any l2 APIs.\n */\nextern rtk_api_ret_t rtk_l2_init(void);\n\n/* Function Name:\n *      rtk_l2_addr_add\n * Description:\n *      Add LUT unicast entry.\n * Input:\n *      pMac - 6 bytes unicast(I/G bit is 0) mac address to be written into LUT.\n *      pL2_data - Unicast entry parameter\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - OK\n *      RT_ERR_FAILED           - Failed\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_PORT_ID          - Invalid port number.\n *      RT_ERR_MAC              - Invalid MAC address.\n *      RT_ERR_L2_FID           - Invalid FID .\n *      RT_ERR_L2_INDEXTBL_FULL - hashed index is full of entries.\n *      RT_ERR_INPUT            - Invalid input parameters.\n * Note:\n *      If the unicast mac address already existed in LUT, it will udpate the status of the entry.\n *      Otherwise, it will find an empty or asic auto learned entry to write. If all the entries\n *      with the same hash value can't be replaced, ASIC will return a RT_ERR_L2_INDEXTBL_FULL error.\n */\nextern rtk_api_ret_t rtk_l2_addr_add(rtk_mac_t *pMac, rtk_l2_ucastAddr_t *pL2_data);\n\n/* Function Name:\n *      rtk_l2_addr_get\n * Description:\n *      Get LUT unicast entry.\n * Input:\n *      pMac    - 6 bytes unicast(I/G bit is 0) mac address to be written into LUT.\n * Output:\n *      pL2_data - Unicast entry parameter\n * Return:\n *      RT_ERR_OK                   - OK\n *      RT_ERR_FAILED               - Failed\n *      RT_ERR_SMI                  - SMI access error\n *      RT_ERR_PORT_ID              - Invalid port number.\n *      RT_ERR_MAC                  - Invalid MAC address.\n *      RT_ERR_L2_FID               - Invalid FID .\n *      RT_ERR_L2_ENTRY_NOTFOUND    - No such LUT entry.\n *      RT_ERR_INPUT                - Invalid input parameters.\n * Note:\n *      If the unicast mac address existed in LUT, it will return the port and fid where\n *      the mac is learned. Otherwise, it will return a RT_ERR_L2_ENTRY_NOTFOUND error.\n */\nextern rtk_api_ret_t rtk_l2_addr_get(rtk_mac_t *pMac, rtk_l2_ucastAddr_t *pL2_data);\n\n/* Function Name:\n *      rtk_l2_addr_next_get\n * Description:\n *      Get Next LUT unicast entry.\n * Input:\n *      read_method     - The reading method.\n *      port            - The port number if the read_metohd is READMETHOD_NEXT_L2UCSPA\n *      pAddress        - The Address ID\n * Output:\n *      pL2_data - Unicast entry parameter\n * Return:\n *      RT_ERR_OK                   - OK\n *      RT_ERR_FAILED               - Failed\n *      RT_ERR_SMI                  - SMI access error\n *      RT_ERR_PORT_ID              - Invalid port number.\n *      RT_ERR_MAC                  - Invalid MAC address.\n *      RT_ERR_L2_FID               - Invalid FID .\n *      RT_ERR_L2_ENTRY_NOTFOUND    - No such LUT entry.\n *      RT_ERR_INPUT                - Invalid input parameters.\n * Note:\n *      Get the next unicast entry after the current entry pointed by pAddress.\n *      The address of next entry is returned by pAddress. User can use (address + 1)\n *      as pAddress to call this API again for dumping all entries is LUT.\n */\nextern rtk_api_ret_t rtk_l2_addr_next_get(rtk_l2_read_method_t read_method, rtk_port_t port, rtk_uint32 *pAddress, rtk_l2_ucastAddr_t *pL2_data);\n\n/* Function Name:\n *      rtk_l2_addr_del\n * Description:\n *      Delete LUT unicast entry.\n * Input:\n *      pMac - 6 bytes unicast(I/G bit is 0) mac address to be written into LUT.\n *      fid - Filtering database\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK                   - OK\n *      RT_ERR_FAILED               - Failed\n *      RT_ERR_SMI                  - SMI access error\n *      RT_ERR_PORT_ID              - Invalid port number.\n *      RT_ERR_MAC                  - Invalid MAC address.\n *      RT_ERR_L2_FID               - Invalid FID .\n *      RT_ERR_L2_ENTRY_NOTFOUND    - No such LUT entry.\n *      RT_ERR_INPUT                - Invalid input parameters.\n * Note:\n *      If the mac has existed in the LUT, it will be deleted. Otherwise, it will return RT_ERR_L2_ENTRY_NOTFOUND.\n */\nextern rtk_api_ret_t rtk_l2_addr_del(rtk_mac_t *pMac, rtk_l2_ucastAddr_t *pL2_data);\n\n/* Function Name:\n *      rtk_l2_mcastAddr_add\n * Description:\n *      Add LUT multicast entry.\n * Input:\n *      pMcastAddr  - L2 multicast entry structure\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - OK\n *      RT_ERR_FAILED           - Failed\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_PORT_ID          - Invalid port number.\n *      RT_ERR_MAC              - Invalid MAC address.\n *      RT_ERR_L2_FID           - Invalid FID .\n *      RT_ERR_L2_VID           - Invalid VID .\n *      RT_ERR_L2_INDEXTBL_FULL - hashed index is full of entries.\n *      RT_ERR_PORT_MASK        - Invalid portmask.\n *      RT_ERR_INPUT            - Invalid input parameters.\n * Note:\n *      If the multicast mac address already existed in the LUT, it will udpate the\n *      port mask of the entry. Otherwise, it will find an empty or asic auto learned\n *      entry to write. If all the entries with the same hash value can't be replaced,\n *      ASIC will return a RT_ERR_L2_INDEXTBL_FULL error.\n */\nextern rtk_api_ret_t rtk_l2_mcastAddr_add(rtk_l2_mcastAddr_t *pMcastAddr);\n\n/* Function Name:\n *      rtk_l2_mcastAddr_get\n * Description:\n *      Get LUT multicast entry.\n * Input:\n *      pMcastAddr  - L2 multicast entry structure\n * Output:\n *      pMcastAddr  - L2 multicast entry structure\n * Return:\n *      RT_ERR_OK                   - OK\n *      RT_ERR_FAILED               - Failed\n *      RT_ERR_SMI                  - SMI access error\n *      RT_ERR_MAC                  - Invalid MAC address.\n *      RT_ERR_L2_FID               - Invalid FID .\n *      RT_ERR_L2_VID               - Invalid VID .\n *      RT_ERR_L2_ENTRY_NOTFOUND    - No such LUT entry.\n *      RT_ERR_INPUT                - Invalid input parameters.\n * Note:\n *      If the multicast mac address existed in the LUT, it will return the port where\n *      the mac is learned. Otherwise, it will return a RT_ERR_L2_ENTRY_NOTFOUND error.\n */\nextern rtk_api_ret_t rtk_l2_mcastAddr_get(rtk_l2_mcastAddr_t *pMcastAddr);\n\n/* Function Name:\n *      rtk_l2_mcastAddr_next_get\n * Description:\n *      Get Next L2 Multicast entry.\n * Input:\n *      pAddress        - The Address ID\n * Output:\n *      pMcastAddr  - L2 multicast entry structure\n * Return:\n *      RT_ERR_OK                   - OK\n *      RT_ERR_FAILED               - Failed\n *      RT_ERR_SMI                  - SMI access error\n *      RT_ERR_L2_ENTRY_NOTFOUND    - No such LUT entry.\n *      RT_ERR_INPUT                - Invalid input parameters.\n * Note:\n *      Get the next L2 multicast entry after the current entry pointed by pAddress.\n *      The address of next entry is returned by pAddress. User can use (address + 1)\n *      as pAddress to call this API again for dumping all multicast entries is LUT.\n */\nextern rtk_api_ret_t rtk_l2_mcastAddr_next_get(rtk_uint32 *pAddress, rtk_l2_mcastAddr_t *pMcastAddr);\n\n/* Function Name:\n *      rtk_l2_mcastAddr_del\n * Description:\n *      Delete LUT multicast entry.\n * Input:\n *      pMcastAddr  - L2 multicast entry structure\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK                   - OK\n *      RT_ERR_FAILED               - Failed\n *      RT_ERR_SMI                  - SMI access error\n *      RT_ERR_MAC                  - Invalid MAC address.\n *      RT_ERR_L2_FID               - Invalid FID .\n *      RT_ERR_L2_VID               - Invalid VID .\n *      RT_ERR_L2_ENTRY_NOTFOUND    - No such LUT entry.\n *      RT_ERR_INPUT                - Invalid input parameters.\n * Note:\n *      If the mac has existed in the LUT, it will be deleted. Otherwise, it will return RT_ERR_L2_ENTRY_NOTFOUND.\n */\nextern rtk_api_ret_t rtk_l2_mcastAddr_del(rtk_l2_mcastAddr_t *pMcastAddr);\n\n/* Function Name:\n *      rtk_l2_ipMcastAddr_add\n * Description:\n *      Add Lut IP multicast entry\n * Input:\n *      pIpMcastAddr    - IP Multicast entry\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - OK\n *      RT_ERR_FAILED           - Failed\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_PORT_ID          - Invalid port number.\n *      RT_ERR_L2_INDEXTBL_FULL - hashed index is full of entries.\n *      RT_ERR_PORT_MASK        - Invalid portmask.\n *      RT_ERR_INPUT            - Invalid input parameters.\n * Note:\n *      System supports L2 entry with IP multicast DIP/SIP to forward IP multicasting frame as user\n *      desired. If this function is enabled, then system will be looked up L2 IP multicast entry to\n *      forward IP multicast frame directly without flooding.\n */\nextern rtk_api_ret_t rtk_l2_ipMcastAddr_add(rtk_l2_ipMcastAddr_t *pIpMcastAddr);\n\n/* Function Name:\n *      rtk_l2_ipMcastAddr_get\n * Description:\n *      Get LUT IP multicast entry.\n * Input:\n *      pIpMcastAddr    - IP Multicast entry\n * Output:\n *      pIpMcastAddr    - IP Multicast entry\n * Return:\n *      RT_ERR_OK                   - OK\n *      RT_ERR_FAILED               - Failed\n *      RT_ERR_SMI                  - SMI access error\n *      RT_ERR_L2_ENTRY_NOTFOUND    - No such LUT entry.\n *      RT_ERR_INPUT                - Invalid input parameters.\n * Note:\n *      The API can get Lut table of IP multicast entry.\n */\nextern rtk_api_ret_t rtk_l2_ipMcastAddr_get(rtk_l2_ipMcastAddr_t *pIpMcastAddr);\n\n/* Function Name:\n *      rtk_l2_ipMcastAddr_next_get\n * Description:\n *      Get Next IP Multicast entry.\n * Input:\n *      pAddress        - The Address ID\n * Output:\n *      pIpMcastAddr    - IP Multicast entry\n * Return:\n *      RT_ERR_OK                   - OK\n *      RT_ERR_FAILED               - Failed\n *      RT_ERR_SMI                  - SMI access error\n *      RT_ERR_L2_ENTRY_NOTFOUND    - No such LUT entry.\n *      RT_ERR_INPUT                - Invalid input parameters.\n * Note:\n *      Get the next IP multicast entry after the current entry pointed by pAddress.\n *      The address of next entry is returned by pAddress. User can use (address + 1)\n *      as pAddress to call this API again for dumping all IP multicast entries is LUT.\n */\nextern rtk_api_ret_t rtk_l2_ipMcastAddr_next_get(rtk_uint32 *pAddress, rtk_l2_ipMcastAddr_t *pIpMcastAddr);\n\n/* Function Name:\n *      rtk_l2_ipMcastAddr_del\n * Description:\n *      Delete a ip multicast address entry from the specified device.\n * Input:\n *      pIpMcastAddr    - IP Multicast entry\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK                   - OK\n *      RT_ERR_FAILED               - Failed\n *      RT_ERR_SMI                  - SMI access error\n *      RT_ERR_L2_ENTRY_NOTFOUND    - No such LUT entry.\n *      RT_ERR_INPUT                - Invalid input parameters.\n * Note:\n *      The API can delete a IP multicast address entry from the specified device.\n */\nextern rtk_api_ret_t rtk_l2_ipMcastAddr_del(rtk_l2_ipMcastAddr_t *pIpMcastAddr);\n\n/* Function Name:\n *      rtk_l2_ipVidMcastAddr_add\n * Description:\n *      Add Lut IP multicast+VID entry\n * Input:\n *      pIpVidMcastAddr - IP & VID multicast Entry\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - OK\n *      RT_ERR_FAILED           - Failed\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_PORT_ID          - Invalid port number.\n *      RT_ERR_L2_INDEXTBL_FULL - hashed index is full of entries.\n *      RT_ERR_PORT_MASK        - Invalid portmask.\n *      RT_ERR_INPUT            - Invalid input parameters.\n * Note:\n *\n */\nextern rtk_api_ret_t rtk_l2_ipVidMcastAddr_add(rtk_l2_ipVidMcastAddr_t *pIpVidMcastAddr);\n\n/* Function Name:\n *      rtk_l2_ipVidMcastAddr_get\n * Description:\n *      Get LUT IP multicast+VID entry.\n * Input:\n *      pIpVidMcastAddr - IP & VID multicast Entry\n * Output:\n *      pIpVidMcastAddr - IP & VID multicast Entry\n * Return:\n *      RT_ERR_OK                   - OK\n *      RT_ERR_FAILED               - Failed\n *      RT_ERR_SMI                  - SMI access error\n *      RT_ERR_L2_ENTRY_NOTFOUND    - No such LUT entry.\n *      RT_ERR_INPUT                - Invalid input parameters.\n * Note:\n *\n */\nextern rtk_api_ret_t rtk_l2_ipVidMcastAddr_get(rtk_l2_ipVidMcastAddr_t *pIpVidMcastAddr);\n\n/* Function Name:\n *      rtk_l2_ipVidMcastAddr_next_get\n * Description:\n *      Get Next IP Multicast+VID entry.\n * Input:\n *      pAddress        - The Address ID\n * Output:\n *      pIpVidMcastAddr - IP & VID multicast Entry\n * Return:\n *      RT_ERR_OK                   - OK\n *      RT_ERR_FAILED               - Failed\n *      RT_ERR_SMI                  - SMI access error\n *      RT_ERR_L2_ENTRY_NOTFOUND    - No such LUT entry.\n *      RT_ERR_INPUT                - Invalid input parameters.\n * Note:\n *      Get the next IP multicast entry after the current entry pointed by pAddress.\n *      The address of next entry is returned by pAddress. User can use (address + 1)\n *      as pAddress to call this API again for dumping all IP multicast entries is LUT.\n */\nextern rtk_api_ret_t rtk_l2_ipVidMcastAddr_next_get(rtk_uint32 *pAddress, rtk_l2_ipVidMcastAddr_t *pIpVidMcastAddr);\n\n/* Function Name:\n *      rtk_l2_ipVidMcastAddr_del\n * Description:\n *      Delete a ip multicast+VID address entry from the specified device.\n * Input:\n *      pIpVidMcastAddr - IP & VID multicast Entry\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK                   - OK\n *      RT_ERR_FAILED               - Failed\n *      RT_ERR_SMI                  - SMI access error\n *      RT_ERR_L2_ENTRY_NOTFOUND    - No such LUT entry.\n *      RT_ERR_INPUT                - Invalid input parameters.\n * Note:\n *\n */\nextern rtk_api_ret_t rtk_l2_ipVidMcastAddr_del(rtk_l2_ipVidMcastAddr_t *pIpVidMcastAddr);\n\n/* Function Name:\n *      rtk_l2_ucastAddr_flush\n * Description:\n *      Flush L2 mac address by type in the specified device (both dynamic and static).\n * Input:\n *      pConfig - flush configuration\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number.\n *      RT_ERR_VLAN_VID     - Invalid VID parameter.\n *      RT_ERR_INPUT        - Invalid input parameters.\n * Note:\n *      flushByVid          - 1: Flush by VID, 0: Don't flush by VID\n *      vid                 - VID (0 ~ 4095)\n *      flushByFid          - 1: Flush by FID, 0: Don't flush by FID\n *      fid                 - FID (0 ~ 15)\n *      flushByPort         - 1: Flush by Port, 0: Don't flush by Port\n *      port                - Port ID\n *      flushByMac          - Not Supported\n *      ucastAddr           - Not Supported\n *      flushStaticAddr     - 1: Flush both Static and Dynamic entries, 0: Flush only Dynamic entries\n *      flushAddrOnAllPorts - 1: Flush VID-matched entries at all ports, 0: Flush VID-matched entries per port.\n */\nextern rtk_api_ret_t rtk_l2_ucastAddr_flush(rtk_l2_flushCfg_t *pConfig);\n\n/* Function Name:\n *      rtk_l2_table_clear\n * Description:\n *      Flush all static & dynamic entries in LUT.\n * Input:\n *      None\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n * Note:\n *\n */\nextern rtk_api_ret_t rtk_l2_table_clear(void);\n\n/* Function Name:\n *      rtk_l2_table_clearStatus_get\n * Description:\n *      Get table clear status\n * Input:\n *      None\n * Output:\n *      pStatus - Clear status, 1:Busy, 0:finish\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n * Note:\n *\n */\nextern rtk_api_ret_t rtk_l2_table_clearStatus_get(rtk_l2_clearStatus_t *pStatus);\n\n/* Function Name:\n *      rtk_l2_flushLinkDownPortAddrEnable_set\n * Description:\n *      Set HW flush linkdown port mac configuration of the specified device.\n * Input:\n *      port - Port id.\n *      enable - link down flush status\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number.\n *      RT_ERR_ENABLE       - Invalid enable input.\n * Note:\n *      The status of flush linkdown port address is as following:\n *      - DISABLED\n *      - ENABLED\n */\nextern rtk_api_ret_t rtk_l2_flushLinkDownPortAddrEnable_set(rtk_port_t port, rtk_enable_t enable);\n\n/* Function Name:\n *      rtk_l2_flushLinkDownPortAddrEnable_get\n * Description:\n *      Get HW flush linkdown port mac configuration of the specified device.\n * Input:\n *      port - Port id.\n * Output:\n *      pEnable - link down flush status\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number.\n * Note:\n *      The status of flush linkdown port address is as following:\n *      - DISABLED\n *      - ENABLED\n */\nextern rtk_api_ret_t rtk_l2_flushLinkDownPortAddrEnable_get(rtk_port_t port, rtk_enable_t *pEnable);\n\n/* Function Name:\n *      rtk_l2_agingEnable_set\n * Description:\n *      Set L2 LUT aging status per port setting.\n * Input:\n *      port    - Port id.\n *      enable  - Aging status\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number.\n *      RT_ERR_ENABLE       - Invalid enable input.\n * Note:\n *      This API can be used to set L2 LUT aging status per port.\n */\nextern rtk_api_ret_t rtk_l2_agingEnable_set(rtk_port_t port, rtk_enable_t enable);\n\n/* Function Name:\n *      rtk_l2_agingEnable_get\n * Description:\n *      Get L2 LUT aging status per port setting.\n * Input:\n *      port - Port id.\n * Output:\n *      pEnable - Aging status\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number.\n * Note:\n *      This API can be used to get L2 LUT aging function per port.\n */\nextern rtk_api_ret_t rtk_l2_agingEnable_get(rtk_port_t port, rtk_enable_t *pEnable);\n\n/* Function Name:\n *      rtk_l2_limitLearningCnt_set\n * Description:\n *      Set per-Port auto learning limit number\n * Input:\n *      port    - Port id.\n *      mac_cnt - Auto learning entries limit number\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK                   - OK\n *      RT_ERR_FAILED               - Failed\n *      RT_ERR_SMI                  - SMI access error\n *      RT_ERR_PORT_ID              - Invalid port number.\n *      RT_ERR_LIMITED_L2ENTRY_NUM  - Invalid auto learning limit number\n * Note:\n *      The API can set per-port ASIC auto learning limit number from 0(disable learning)\n *      to 8k.\n */\nextern rtk_api_ret_t rtk_l2_limitLearningCnt_set(rtk_port_t port, rtk_mac_cnt_t mac_cnt);\n\n/* Function Name:\n *      rtk_l2_limitLearningCnt_get\n * Description:\n *      Get per-Port auto learning limit number\n * Input:\n *      port - Port id.\n * Output:\n *      pMac_cnt - Auto learning entries limit number\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number.\n * Note:\n *      The API can get per-port ASIC auto learning limit number.\n */\nextern rtk_api_ret_t rtk_l2_limitLearningCnt_get(rtk_port_t port, rtk_mac_cnt_t *pMac_cnt);\n\n/* Function Name:\n *      rtk_l2_limitSystemLearningCnt_set\n * Description:\n *      Set System auto learning limit number\n * Input:\n *      mac_cnt - Auto learning entries limit number\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK                   - OK\n *      RT_ERR_FAILED               - Failed\n *      RT_ERR_SMI                  - SMI access error\n *      RT_ERR_LIMITED_L2ENTRY_NUM  - Invalid auto learning limit number\n * Note:\n *      The API can set system ASIC auto learning limit number from 0(disable learning)\n *      to 2112.\n */\nextern rtk_api_ret_t rtk_l2_limitSystemLearningCnt_set(rtk_mac_cnt_t mac_cnt);\n\n/* Function Name:\n *      rtk_l2_limitSystemLearningCnt_get\n * Description:\n *      Get System auto learning limit number\n * Input:\n *      None\n * Output:\n *      pMac_cnt - Auto learning entries limit number\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number.\n * Note:\n *      The API can get system ASIC auto learning limit number.\n */\nextern rtk_api_ret_t rtk_l2_limitSystemLearningCnt_get(rtk_mac_cnt_t *pMac_cnt);\n\n/* Function Name:\n *      rtk_l2_limitLearningCntAction_set\n * Description:\n *      Configure auto learn over limit number action.\n * Input:\n *      port - Port id.\n *      action - Auto learning entries limit number\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number.\n *      RT_ERR_NOT_ALLOWED  - Invalid learn over action\n * Note:\n *      The API can set SA unknown packet action while auto learn limit number is over\n *      The action symbol as following:\n *      - LIMIT_LEARN_CNT_ACTION_DROP,\n *      - LIMIT_LEARN_CNT_ACTION_FORWARD,\n *      - LIMIT_LEARN_CNT_ACTION_TO_CPU,\n */\nextern rtk_api_ret_t rtk_l2_limitLearningCntAction_set(rtk_port_t port, rtk_l2_limitLearnCntAction_t action);\n\n/* Function Name:\n *      rtk_l2_limitLearningCntAction_get\n * Description:\n *      Get auto learn over limit number action.\n * Input:\n *      port - Port id.\n * Output:\n *      pAction - Learn over action\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number.\n * Note:\n *      The API can get SA unknown packet action while auto learn limit number is over\n *      The action symbol as following:\n *      - LIMIT_LEARN_CNT_ACTION_DROP,\n *      - LIMIT_LEARN_CNT_ACTION_FORWARD,\n *      - LIMIT_LEARN_CNT_ACTION_TO_CPU,\n */\nextern rtk_api_ret_t rtk_l2_limitLearningCntAction_get(rtk_port_t port, rtk_l2_limitLearnCntAction_t *pAction);\n\n/* Function Name:\n *      rtk_l2_limitSystemLearningCntAction_set\n * Description:\n *      Configure system auto learn over limit number action.\n * Input:\n *      port - Port id.\n *      action - Auto learning entries limit number\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number.\n *      RT_ERR_NOT_ALLOWED  - Invalid learn over action\n * Note:\n *      The API can set SA unknown packet action while auto learn limit number is over\n *      The action symbol as following:\n *      - LIMIT_LEARN_CNT_ACTION_DROP,\n *      - LIMIT_LEARN_CNT_ACTION_FORWARD,\n *      - LIMIT_LEARN_CNT_ACTION_TO_CPU,\n */\nextern rtk_api_ret_t rtk_l2_limitSystemLearningCntAction_set(rtk_l2_limitLearnCntAction_t action);\n\n/* Function Name:\n *      rtk_l2_limitSystemLearningCntAction_get\n * Description:\n *      Get system auto learn over limit number action.\n * Input:\n *      None.\n * Output:\n *      pAction - Learn over action\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number.\n * Note:\n *      The API can get SA unknown packet action while auto learn limit number is over\n *      The action symbol as following:\n *      - LIMIT_LEARN_CNT_ACTION_DROP,\n *      - LIMIT_LEARN_CNT_ACTION_FORWARD,\n *      - LIMIT_LEARN_CNT_ACTION_TO_CPU,\n */\nextern rtk_api_ret_t rtk_l2_limitSystemLearningCntAction_get(rtk_l2_limitLearnCntAction_t *pAction);\n\n/* Function Name:\n *      rtk_l2_limitSystemLearningCntPortMask_set\n * Description:\n *      Configure system auto learn portmask\n * Input:\n *      pPortmask - Port Mask\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_MASK    - Invalid port mask.\n * Note:\n *\n */\nextern rtk_api_ret_t rtk_l2_limitSystemLearningCntPortMask_set(rtk_portmask_t *pPortmask);\n\n/* Function Name:\n *      rtk_l2_limitSystemLearningCntPortMask_get\n * Description:\n *      get system auto learn portmask\n * Input:\n *      None\n * Output:\n *      pPortmask - Port Mask\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_NULL_POINTER - Null pointer.\n * Note:\n *\n */\nextern rtk_api_ret_t rtk_l2_limitSystemLearningCntPortMask_get(rtk_portmask_t *pPortmask);\n\n/* Function Name:\n *      rtk_l2_learningCnt_get\n * Description:\n *      Get per-Port current auto learning number\n * Input:\n *      port - Port id.\n * Output:\n *      pMac_cnt - ASIC auto learning entries number\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number.\n * Note:\n *      The API can get per-port ASIC auto learning number\n */\nextern rtk_api_ret_t rtk_l2_learningCnt_get(rtk_port_t port, rtk_mac_cnt_t *pMac_cnt);\n\n/* Function Name:\n *      rtk_l2_floodPortMask_set\n * Description:\n *      Set flooding portmask\n * Input:\n *      type - flooding type.\n *      pFlood_portmask - flooding porkmask\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_MASK    - Invalid portmask.\n *      RT_ERR_INPUT        - Invalid input parameters.\n * Note:\n *      This API can set the flooding mask.\n *      The flooding type is as following:\n *      - FLOOD_UNKNOWNDA\n *      - FLOOD_UNKNOWNMC\n *      - FLOOD_BC\n */\nextern rtk_api_ret_t rtk_l2_floodPortMask_set(rtk_l2_flood_type_t floood_type, rtk_portmask_t *pFlood_portmask);\n\n/* Function Name:\n *      rtk_l2_floodPortMask_get\n * Description:\n *      Get flooding portmask\n * Input:\n *      type - flooding type.\n * Output:\n *      pFlood_portmask - flooding porkmask\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number.\n * Note:\n *      This API can get the flooding mask.\n *      The flooding type is as following:\n *      - FLOOD_UNKNOWNDA\n *      - FLOOD_UNKNOWNMC\n *      - FLOOD_BC\n */\nextern rtk_api_ret_t rtk_l2_floodPortMask_get(rtk_l2_flood_type_t floood_type, rtk_portmask_t *pFlood_portmask);\n\n/* Function Name:\n *      rtk_l2_localPktPermit_set\n * Description:\n *      Set permittion of frames if source port and destination port are the same.\n * Input:\n *      port - Port id.\n *      permit - permittion status\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number.\n *      RT_ERR_ENABLE       - Invalid permit value.\n * Note:\n *      This API is setted to permit frame if its source port is equal to destination port.\n */\nextern rtk_api_ret_t rtk_l2_localPktPermit_set(rtk_port_t port, rtk_enable_t permit);\n\n/* Function Name:\n *      rtk_l2_localPktPermit_get\n * Description:\n *      Get permittion of frames if source port and destination port are the same.\n * Input:\n *      port - Port id.\n * Output:\n *      pPermit - permittion status\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number.\n * Note:\n *      This API is to get permittion status for frames if its source port is equal to destination port.\n */\nextern rtk_api_ret_t rtk_l2_localPktPermit_get(rtk_port_t port, rtk_enable_t *pPermit);\n\n/* Function Name:\n *      rtk_l2_aging_set\n * Description:\n *      Set LUT agging out speed\n * Input:\n *      aging_time - Agging out time.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - OK\n *      RT_ERR_FAILED           - Failed\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_OUT_OF_RANGE     - input out of range.\n * Note:\n *      The API can set LUT agging out period for each entry and the range is from 14s to 800s.\n */\nextern rtk_api_ret_t rtk_l2_aging_set(rtk_l2_age_time_t aging_time);\n\n/* Function Name:\n *      rtk_l2_aging_get\n * Description:\n *      Get LUT agging out time\n * Input:\n *      None\n * Output:\n *      pEnable - Aging status\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number.\n * Note:\n *      The API can get LUT agging out period for each entry.\n */\nextern rtk_api_ret_t rtk_l2_aging_get(rtk_l2_age_time_t *pAging_time);\n\n/* Function Name:\n *      rtk_l2_ipMcastAddrLookup_set\n * Description:\n *      Set Lut IP multicast lookup function\n * Input:\n *      type - Lookup type for IPMC packet.\n * Output:\n *      None.\n * Return:\n *      RT_ERR_OK          - OK\n *      RT_ERR_FAILED      - Failed\n *      RT_ERR_SMI         - SMI access error\n * Note:\n *      This API can work with rtk_l2_ipMcastAddrLookupException_add.\n *      If users set the lookup type to DIP, the group in exception table\n *      will be lookup by DIP+SIP\n *      If users set the lookup type to DIP+SIP, the group in exception table\n *      will be lookup by only DIP\n */\nextern rtk_api_ret_t rtk_l2_ipMcastAddrLookup_set(rtk_l2_ipmc_lookup_type_t type);\n\n/* Function Name:\n *      rtk_l2_ipMcastAddrLookup_get\n * Description:\n *      Get Lut IP multicast lookup function\n * Input:\n *      None.\n * Output:\n *      pType - Lookup type for IPMC packet.\n * Return:\n *      RT_ERR_OK          - OK\n *      RT_ERR_FAILED      - Failed\n *      RT_ERR_SMI         - SMI access error\n * Note:\n *      None.\n */\nextern rtk_api_ret_t rtk_l2_ipMcastAddrLookup_get(rtk_l2_ipmc_lookup_type_t *pType);\n\n/* Function Name:\n *      rtk_l2_ipMcastForwardRouterPort_set\n * Description:\n *      Set IPMC packet forward to rounter port also or not\n * Input:\n *      enabled - 1: Inlcude router port, 0, exclude router port\n * Output:\n *      None.\n * Return:\n *      RT_ERR_OK          - OK\n *      RT_ERR_FAILED      - Failed\n *      RT_ERR_SMI         - SMI access error\n * Note:\n *\n */\nextern rtk_api_ret_t rtk_l2_ipMcastForwardRouterPort_set(rtk_enable_t enabled);\n\n/* Function Name:\n *      rtk_l2_ipMcastForwardRouterPort_get\n * Description:\n *      Get IPMC packet forward to rounter port also or not\n * Input:\n *      None.\n * Output:\n *      pEnabled    - 1: Inlcude router port, 0, exclude router port\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_NULL_POINTER - Null pointer\n * Note:\n *\n */\nextern rtk_api_ret_t rtk_l2_ipMcastForwardRouterPort_get(rtk_enable_t *pEnabled);\n\n/* Function Name:\n *      rtk_l2_ipMcastGroupEntry_add\n * Description:\n *      Add an IP Multicast entry to group table\n * Input:\n *      ip_addr     - IP address\n *      vid         - VLAN ID\n *      pPortmask   - portmask\n * Output:\n *      None.\n * Return:\n *      RT_ERR_OK          - OK\n *      RT_ERR_FAILED      - Failed\n *      RT_ERR_SMI         - SMI access error\n *      RT_ERR_TBL_FULL    - Table Full\n * Note:\n *      Add an entry to IP Multicast Group table.\n */\nextern rtk_api_ret_t rtk_l2_ipMcastGroupEntry_add(ipaddr_t ip_addr, rtk_uint32 vid, rtk_portmask_t *pPortmask);\n\n/* Function Name:\n *      rtk_l2_ipMcastGroupEntry_del\n * Description:\n *      Delete an entry from IP Multicast group table\n * Input:\n *      ip_addr     - IP address\n *      vid         - VLAN ID\n * Output:\n *      None.\n * Return:\n *      RT_ERR_OK          - OK\n *      RT_ERR_FAILED      - Failed\n *      RT_ERR_SMI         - SMI access error\n *      RT_ERR_TBL_FULL    - Table Full\n * Note:\n *      Delete an entry from IP Multicast group table.\n */\nextern rtk_api_ret_t rtk_l2_ipMcastGroupEntry_del(ipaddr_t ip_addr, rtk_uint32 vid);\n\n/* Function Name:\n *      rtk_l2_ipMcastGroupEntry_get\n * Description:\n *      get an entry from IP Multicast group table\n * Input:\n *      ip_addr     - IP address\n *      vid         - VLAN ID\n * Output:\n *      pPortmask   - member port mask\n * Return:\n *      RT_ERR_OK          - OK\n *      RT_ERR_FAILED      - Failed\n *      RT_ERR_SMI         - SMI access error\n *      RT_ERR_TBL_FULL    - Table Full\n * Note:\n *      Delete an entry from IP Multicast group table.\n */\nextern rtk_api_ret_t rtk_l2_ipMcastGroupEntry_get(ipaddr_t ip_addr, rtk_uint32 vid, rtk_portmask_t *pPortmask);\n\n/* Function Name:\n *      rtk_l2_entry_get\n * Description:\n *      Get LUT unicast entry.\n * Input:\n *      pL2_entry - Index field in the structure.\n * Output:\n *      pL2_entry - other fields such as MAC, port, age...\n * Return:\n *      RT_ERR_OK               - OK\n *      RT_ERR_FAILED           - Failed\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_L2_EMPTY_ENTRY   - Empty LUT entry.\n *      RT_ERR_INPUT            - Invalid input parameters.\n * Note:\n *      This API is used to get address by index from 0~2111.\n */\nextern rtk_api_ret_t rtk_l2_entry_get(rtk_l2_addr_table_t *pL2_entry);\n\n\n#endif /* __RTK_API_L2_H__ */\n\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/leaky.h",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * Purpose : RTL8367/RTL8367C switch high-level API\n *\n * Feature : The file includes Leaky module high-layer API defination\n *\n */\n\n#ifndef __RTK_API_LEAKY_H__\n#define __RTK_API_LEAKY_H__\n\n\ntypedef enum rtk_leaky_type_e\n{\n    LEAKY_BRG_GROUP = 0,\n    LEAKY_FD_PAUSE,\n    LEAKY_SP_MCAST,\n    LEAKY_1X_PAE,\n    LEAKY_UNDEF_BRG_04,\n    LEAKY_UNDEF_BRG_05,\n    LEAKY_UNDEF_BRG_06,\n    LEAKY_UNDEF_BRG_07,\n    LEAKY_PROVIDER_BRIDGE_GROUP_ADDRESS,\n    LEAKY_UNDEF_BRG_09,\n    LEAKY_UNDEF_BRG_0A,\n    LEAKY_UNDEF_BRG_0B,\n    LEAKY_UNDEF_BRG_0C,\n    LEAKY_PROVIDER_BRIDGE_GVRP_ADDRESS,\n    LEAKY_8021AB,\n    LEAKY_UNDEF_BRG_0F,\n    LEAKY_BRG_MNGEMENT,\n    LEAKY_UNDEFINED_11,\n    LEAKY_UNDEFINED_12,\n    LEAKY_UNDEFINED_13,\n    LEAKY_UNDEFINED_14,\n    LEAKY_UNDEFINED_15,\n    LEAKY_UNDEFINED_16,\n    LEAKY_UNDEFINED_17,\n    LEAKY_UNDEFINED_18,\n    LEAKY_UNDEFINED_19,\n    LEAKY_UNDEFINED_1A,\n    LEAKY_UNDEFINED_1B,\n    LEAKY_UNDEFINED_1C,\n    LEAKY_UNDEFINED_1D,\n    LEAKY_UNDEFINED_1E,\n    LEAKY_UNDEFINED_1F,\n    LEAKY_GMRP,\n    LEAKY_GVRP,\n    LEAKY_UNDEF_GARP_22,\n    LEAKY_UNDEF_GARP_23,\n    LEAKY_UNDEF_GARP_24,\n    LEAKY_UNDEF_GARP_25,\n    LEAKY_UNDEF_GARP_26,\n    LEAKY_UNDEF_GARP_27,\n    LEAKY_UNDEF_GARP_28,\n    LEAKY_UNDEF_GARP_29,\n    LEAKY_UNDEF_GARP_2A,\n    LEAKY_UNDEF_GARP_2B,\n    LEAKY_UNDEF_GARP_2C,\n    LEAKY_UNDEF_GARP_2D,\n    LEAKY_UNDEF_GARP_2E,\n    LEAKY_UNDEF_GARP_2F,\n    LEAKY_IGMP,\n    LEAKY_IPMULTICAST,\n    LEAKY_CDP,\n    LEAKY_CSSTP,\n    LEAKY_LLDP,\n    LEAKY_END,\n}rtk_leaky_type_t;\n\n/* Function Name:\n *      rtk_leaky_vlan_set\n * Description:\n *      Set VLAN leaky.\n * Input:\n *      type - Packet type for VLAN leaky.\n *      enable - Leaky status.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n *      RT_ERR_ENABLE       - Invalid enable input\n * Note:\n *      This API can set VLAN leaky for RMA ,IGMP/MLD, CDP, CSSTP, and LLDP packets.\n *      The leaky frame types are as following:\n *      - LEAKY_BRG_GROUP,\n *      - LEAKY_FD_PAUSE,\n *      - LEAKY_SP_MCAST,\n *      - LEAKY_1X_PAE,\n *      - LEAKY_UNDEF_BRG_04,\n *      - LEAKY_UNDEF_BRG_05,\n *      - LEAKY_UNDEF_BRG_06,\n *      - LEAKY_UNDEF_BRG_07,\n *      - LEAKY_PROVIDER_BRIDGE_GROUP_ADDRESS,\n *      - LEAKY_UNDEF_BRG_09,\n *      - LEAKY_UNDEF_BRG_0A,\n *      - LEAKY_UNDEF_BRG_0B,\n *      - LEAKY_UNDEF_BRG_0C,\n *      - LEAKY_PROVIDER_BRIDGE_GVRP_ADDRESS,\n *      - LEAKY_8021AB,\n *      - LEAKY_UNDEF_BRG_0F,\n *      - LEAKY_BRG_MNGEMENT,\n *      - LEAKY_UNDEFINED_11,\n *      - LEAKY_UNDEFINED_12,\n *      - LEAKY_UNDEFINED_13,\n *      - LEAKY_UNDEFINED_14,\n *      - LEAKY_UNDEFINED_15,\n *      - LEAKY_UNDEFINED_16,\n *      - LEAKY_UNDEFINED_17,\n *      - LEAKY_UNDEFINED_18,\n *      - LEAKY_UNDEFINED_19,\n *      - LEAKY_UNDEFINED_1A,\n *      - LEAKY_UNDEFINED_1B,\n *      - LEAKY_UNDEFINED_1C,\n *      - LEAKY_UNDEFINED_1D,\n *      - LEAKY_UNDEFINED_1E,\n *      - LEAKY_UNDEFINED_1F,\n *      - LEAKY_GMRP,\n *      - LEAKY_GVRP,\n *      - LEAKY_UNDEF_GARP_22,\n *      - LEAKY_UNDEF_GARP_23,\n *      - LEAKY_UNDEF_GARP_24,\n *      - LEAKY_UNDEF_GARP_25,\n *      - LEAKY_UNDEF_GARP_26,\n *      - LEAKY_UNDEF_GARP_27,\n *      - LEAKY_UNDEF_GARP_28,\n *      - LEAKY_UNDEF_GARP_29,\n *      - LEAKY_UNDEF_GARP_2A,\n *      - LEAKY_UNDEF_GARP_2B,\n *      - LEAKY_UNDEF_GARP_2C,\n *      - LEAKY_UNDEF_GARP_2D,\n *      - LEAKY_UNDEF_GARP_2E,\n *      - LEAKY_UNDEF_GARP_2F,\n *      - LEAKY_IGMP,\n *      - LEAKY_IPMULTICAST.\n *      - LEAKY_CDP,\n *      - LEAKY_CSSTP,\n *      - LEAKY_LLDP.\n */\nextern rtk_api_ret_t rtk_leaky_vlan_set(rtk_leaky_type_t type, rtk_enable_t enable);\n\n/* Function Name:\n *      rtk_leaky_vlan_get\n * Description:\n *      Get VLAN leaky.\n * Input:\n *      type - Packet type for VLAN leaky.\n * Output:\n *      pEnable - Leaky status.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n * Note:\n *      This API can get VLAN leaky status for RMA ,IGMP/MLD, CDP, CSSTP, and LLDP  packets.\n *      The leaky frame types are as following:\n *      - LEAKY_BRG_GROUP,\n *      - LEAKY_FD_PAUSE,\n *      - LEAKY_SP_MCAST,\n *      - LEAKY_1X_PAE,\n *      - LEAKY_UNDEF_BRG_04,\n *      - LEAKY_UNDEF_BRG_05,\n *      - LEAKY_UNDEF_BRG_06,\n *      - LEAKY_UNDEF_BRG_07,\n *      - LEAKY_PROVIDER_BRIDGE_GROUP_ADDRESS,\n *      - LEAKY_UNDEF_BRG_09,\n *      - LEAKY_UNDEF_BRG_0A,\n *      - LEAKY_UNDEF_BRG_0B,\n *      - LEAKY_UNDEF_BRG_0C,\n *      - LEAKY_PROVIDER_BRIDGE_GVRP_ADDRESS,\n *      - LEAKY_8021AB,\n *      - LEAKY_UNDEF_BRG_0F,\n *      - LEAKY_BRG_MNGEMENT,\n *      - LEAKY_UNDEFINED_11,\n *      - LEAKY_UNDEFINED_12,\n *      - LEAKY_UNDEFINED_13,\n *      - LEAKY_UNDEFINED_14,\n *      - LEAKY_UNDEFINED_15,\n *      - LEAKY_UNDEFINED_16,\n *      - LEAKY_UNDEFINED_17,\n *      - LEAKY_UNDEFINED_18,\n *      - LEAKY_UNDEFINED_19,\n *      - LEAKY_UNDEFINED_1A,\n *      - LEAKY_UNDEFINED_1B,\n *      - LEAKY_UNDEFINED_1C,\n *      - LEAKY_UNDEFINED_1D,\n *      - LEAKY_UNDEFINED_1E,\n *      - LEAKY_UNDEFINED_1F,\n *      - LEAKY_GMRP,\n *      - LEAKY_GVRP,\n *      - LEAKY_UNDEF_GARP_22,\n *      - LEAKY_UNDEF_GARP_23,\n *      - LEAKY_UNDEF_GARP_24,\n *      - LEAKY_UNDEF_GARP_25,\n *      - LEAKY_UNDEF_GARP_26,\n *      - LEAKY_UNDEF_GARP_27,\n *      - LEAKY_UNDEF_GARP_28,\n *      - LEAKY_UNDEF_GARP_29,\n *      - LEAKY_UNDEF_GARP_2A,\n *      - LEAKY_UNDEF_GARP_2B,\n *      - LEAKY_UNDEF_GARP_2C,\n *      - LEAKY_UNDEF_GARP_2D,\n *      - LEAKY_UNDEF_GARP_2E,\n *      - LEAKY_UNDEF_GARP_2F,\n *      - LEAKY_IGMP,\n *      - LEAKY_IPMULTICAST.\n *      - LEAKY_CDP,\n *      - LEAKY_CSSTP,\n *      - LEAKY_LLDP.\n */\nextern rtk_api_ret_t rtk_leaky_vlan_get(rtk_leaky_type_t type, rtk_enable_t *pEnable);\n\n/* Function Name:\n *      rtk_leaky_portIsolation_set\n * Description:\n *      Set port isolation leaky.\n * Input:\n *      type - Packet type for port isolation leaky.\n *      enable - Leaky status.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n *      RT_ERR_ENABLE       - Invalid enable input\n * Note:\n *      This API can set port isolation leaky for RMA ,IGMP/MLD, CDP, CSSTP, and LLDP  packets.\n *      The leaky frame types are as following:\n *      - LEAKY_BRG_GROUP,\n *      - LEAKY_FD_PAUSE,\n *      - LEAKY_SP_MCAST,\n *      - LEAKY_1X_PAE,\n *      - LEAKY_UNDEF_BRG_04,\n *      - LEAKY_UNDEF_BRG_05,\n *      - LEAKY_UNDEF_BRG_06,\n *      - LEAKY_UNDEF_BRG_07,\n *      - LEAKY_PROVIDER_BRIDGE_GROUP_ADDRESS,\n *      - LEAKY_UNDEF_BRG_09,\n *      - LEAKY_UNDEF_BRG_0A,\n *      - LEAKY_UNDEF_BRG_0B,\n *      - LEAKY_UNDEF_BRG_0C,\n *      - LEAKY_PROVIDER_BRIDGE_GVRP_ADDRESS,\n *      - LEAKY_8021AB,\n *      - LEAKY_UNDEF_BRG_0F,\n *      - LEAKY_BRG_MNGEMENT,\n *      - LEAKY_UNDEFINED_11,\n *      - LEAKY_UNDEFINED_12,\n *      - LEAKY_UNDEFINED_13,\n *      - LEAKY_UNDEFINED_14,\n *      - LEAKY_UNDEFINED_15,\n *      - LEAKY_UNDEFINED_16,\n *      - LEAKY_UNDEFINED_17,\n *      - LEAKY_UNDEFINED_18,\n *      - LEAKY_UNDEFINED_19,\n *      - LEAKY_UNDEFINED_1A,\n *      - LEAKY_UNDEFINED_1B,\n *      - LEAKY_UNDEFINED_1C,\n *      - LEAKY_UNDEFINED_1D,\n *      - LEAKY_UNDEFINED_1E,\n *      - LEAKY_UNDEFINED_1F,\n *      - LEAKY_GMRP,\n *      - LEAKY_GVRP,\n *      - LEAKY_UNDEF_GARP_22,\n *      - LEAKY_UNDEF_GARP_23,\n *      - LEAKY_UNDEF_GARP_24,\n *      - LEAKY_UNDEF_GARP_25,\n *      - LEAKY_UNDEF_GARP_26,\n *      - LEAKY_UNDEF_GARP_27,\n *      - LEAKY_UNDEF_GARP_28,\n *      - LEAKY_UNDEF_GARP_29,\n *      - LEAKY_UNDEF_GARP_2A,\n *      - LEAKY_UNDEF_GARP_2B,\n *      - LEAKY_UNDEF_GARP_2C,\n *      - LEAKY_UNDEF_GARP_2D,\n *      - LEAKY_UNDEF_GARP_2E,\n *      - LEAKY_UNDEF_GARP_2F,\n *      - LEAKY_IGMP,\n *      - LEAKY_IPMULTICAST.\n *      - LEAKY_CDP,\n *      - LEAKY_CSSTP,\n *      - LEAKY_LLDP.\n */\nextern rtk_api_ret_t rtk_leaky_portIsolation_set(rtk_leaky_type_t type, rtk_enable_t enable);\n\n/* Function Name:\n *      rtk_leaky_portIsolation_get\n * Description:\n *      Get port isolation leaky.\n * Input:\n *      type - Packet type for port isolation leaky.\n * Output:\n *      pEnable - Leaky status.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n * Note:\n *      This API can get port isolation leaky status for RMA ,IGMP/MLD, CDP, CSSTP, and LLDP  packets.\n *      The leaky frame types are as following:\n *      - LEAKY_BRG_GROUP,\n *      - LEAKY_FD_PAUSE,\n *      - LEAKY_SP_MCAST,\n *      - LEAKY_1X_PAE,\n *      - LEAKY_UNDEF_BRG_04,\n *      - LEAKY_UNDEF_BRG_05,\n *      - LEAKY_UNDEF_BRG_06,\n *      - LEAKY_UNDEF_BRG_07,\n *      - LEAKY_PROVIDER_BRIDGE_GROUP_ADDRESS,\n *      - LEAKY_UNDEF_BRG_09,\n *      - LEAKY_UNDEF_BRG_0A,\n *      - LEAKY_UNDEF_BRG_0B,\n *      - LEAKY_UNDEF_BRG_0C,\n *      - LEAKY_PROVIDER_BRIDGE_GVRP_ADDRESS,\n *      - LEAKY_8021AB,\n *      - LEAKY_UNDEF_BRG_0F,\n *      - LEAKY_BRG_MNGEMENT,\n *      - LEAKY_UNDEFINED_11,\n *      - LEAKY_UNDEFINED_12,\n *      - LEAKY_UNDEFINED_13,\n *      - LEAKY_UNDEFINED_14,\n *      - LEAKY_UNDEFINED_15,\n *      - LEAKY_UNDEFINED_16,\n *      - LEAKY_UNDEFINED_17,\n *      - LEAKY_UNDEFINED_18,\n *      - LEAKY_UNDEFINED_19,\n *      - LEAKY_UNDEFINED_1A,\n *      - LEAKY_UNDEFINED_1B,\n *      - LEAKY_UNDEFINED_1C,\n *      - LEAKY_UNDEFINED_1D,\n *      - LEAKY_UNDEFINED_1E,\n *      - LEAKY_UNDEFINED_1F,\n *      - LEAKY_GMRP,\n *      - LEAKY_GVRP,\n *      - LEAKY_UNDEF_GARP_22,\n *      - LEAKY_UNDEF_GARP_23,\n *      - LEAKY_UNDEF_GARP_24,\n *      - LEAKY_UNDEF_GARP_25,\n *      - LEAKY_UNDEF_GARP_26,\n *      - LEAKY_UNDEF_GARP_27,\n *      - LEAKY_UNDEF_GARP_28,\n *      - LEAKY_UNDEF_GARP_29,\n *      - LEAKY_UNDEF_GARP_2A,\n *      - LEAKY_UNDEF_GARP_2B,\n *      - LEAKY_UNDEF_GARP_2C,\n *      - LEAKY_UNDEF_GARP_2D,\n *      - LEAKY_UNDEF_GARP_2E,\n *      - LEAKY_UNDEF_GARP_2F,\n *      - LEAKY_IGMP,\n *      - LEAKY_IPMULTICAST.\n *      - LEAKY_CDP,\n *      - LEAKY_CSSTP,\n *      - LEAKY_LLDP.\n */\nextern rtk_api_ret_t rtk_leaky_portIsolation_get(rtk_leaky_type_t type, rtk_enable_t *pEnable);\n\n#endif /* __RTK_API_LEAKY_H__ */\n\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/led.h",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * Purpose : RTL8367/RTL8367C switch high-level API\n *\n * Feature : The file includes LED module high-layer API defination\n *\n */\n\n#ifndef __RTK_API_LED_H__\n#define __RTK_API_LED_H__\n\ntypedef enum rtk_led_operation_e\n{\n    LED_OP_SCAN=0,\n    LED_OP_PARALLEL,\n    LED_OP_SERIAL,\n    LED_OP_END,\n}rtk_led_operation_t;\n\n\ntypedef enum rtk_led_active_e\n{\n    LED_ACTIVE_HIGH=0,\n    LED_ACTIVE_LOW,\n    LED_ACTIVE_END,\n}rtk_led_active_t;\n\ntypedef enum rtk_led_config_e\n{\n    LED_CONFIG_LEDOFF=0,\n    LED_CONFIG_DUPCOL,\n    LED_CONFIG_LINK_ACT,\n    LED_CONFIG_SPD1000,\n    LED_CONFIG_SPD100,\n    LED_CONFIG_SPD10,\n    LED_CONFIG_SPD1000ACT,\n    LED_CONFIG_SPD100ACT,\n    LED_CONFIG_SPD10ACT,\n    LED_CONFIG_SPD10010ACT,\n    LED_CONFIG_LOOPDETECT,\n    LED_CONFIG_EEE,\n    LED_CONFIG_LINKRX,\n    LED_CONFIG_LINKTX,\n    LED_CONFIG_MASTER,\n    LED_CONFIG_ACT,\n    LED_CONFIG_END,\n}rtk_led_congig_t;\n\ntypedef struct rtk_led_ability_s\n{\n    rtk_enable_t link_10m;\n    rtk_enable_t link_100m;\n    rtk_enable_t link_500m;\n    rtk_enable_t link_1000m;\n    rtk_enable_t act_rx;\n    rtk_enable_t act_tx;\n}rtk_led_ability_t;\n\ntypedef enum rtk_led_blink_rate_e\n{\n    LED_BLINKRATE_32MS=0,\n    LED_BLINKRATE_64MS,\n    LED_BLINKRATE_128MS,\n    LED_BLINKRATE_256MS,\n    LED_BLINKRATE_512MS,\n    LED_BLINKRATE_1024MS,\n    LED_BLINKRATE_48MS,\n    LED_BLINKRATE_96MS,\n    LED_BLINKRATE_END,\n}rtk_led_blink_rate_t;\n\ntypedef enum rtk_led_group_e\n{\n    LED_GROUP_0 = 0,\n    LED_GROUP_1,\n    LED_GROUP_2,\n    LED_GROUP_END\n}rtk_led_group_t;\n\n\ntypedef enum rtk_led_force_mode_e\n{\n    LED_FORCE_NORMAL=0,\n    LED_FORCE_BLINK,\n    LED_FORCE_OFF,\n    LED_FORCE_ON,\n    LED_FORCE_END\n}rtk_led_force_mode_t;\n\ntypedef enum rtk_led_serialOutput_e\n{\n    SERIAL_LED_NONE = 0,\n    SERIAL_LED_0,\n    SERIAL_LED_0_1,\n    SERIAL_LED_0_2,\n    SERIAL_LED_END,\n}rtk_led_serialOutput_t;\n\n\n/* Function Name:\n *      rtk_led_enable_set\n * Description:\n *      Set Led enable congiuration\n * Input:\n *      group       - LED group id.\n *      pPortmask    - LED enable port mask.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n * Note:\n *      The API can be used to enable LED per port per group.\n */\nextern rtk_api_ret_t rtk_led_enable_set(rtk_led_group_t group, rtk_portmask_t *pPortmask);\n\n/* Function Name:\n *      rtk_led_enable_get\n * Description:\n *      Get Led enable congiuration\n * Input:\n *      group - LED group id.\n * Output:\n *      pPortmask - LED enable port mask.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n * Note:\n *      The API can be used to get LED enable status.\n */\nextern rtk_api_ret_t rtk_led_enable_get(rtk_led_group_t group, rtk_portmask_t *pPortmask);\n\n/* Function Name:\n *      rtk_led_operation_set\n * Description:\n *      Set Led operation mode\n * Input:\n *      mode - LED operation mode.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n * Note:\n *      The API can set Led operation mode.\n *      The modes that can be set are as following:\n *      - LED_OP_SCAN,\n *      - LED_OP_PARALLEL,\n *      - LED_OP_SERIAL,\n */\nextern rtk_api_ret_t rtk_led_operation_set(rtk_led_operation_t mode);\n\n/* Function Name:\n *      rtk_led_operation_get\n * Description:\n *      Get Led operation mode\n * Input:\n *      None\n * Output:\n *      pMode - Support LED operation mode.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n * Note:\n *      The API can get Led operation mode.\n *      The modes that can be set are as following:\n *      - LED_OP_SCAN,\n *      - LED_OP_PARALLEL,\n *      - LED_OP_SERIAL,\n */\nextern rtk_api_ret_t rtk_led_operation_get(rtk_led_operation_t *pMode);\n\n/* Function Name:\n *      rtk_led_modeForce_set\n * Description:\n *      Set Led group to congiuration force mode\n * Input:\n *      port    - port ID\n *      group   - Support LED group id.\n *      mode    - Support LED force mode.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n *      RT_ERR_PORT_ID      - Error Port ID\n * Note:\n *      The API can force to one force mode.\n *      The force modes that can be set are as following:\n *      - LED_FORCE_NORMAL,\n *      - LED_FORCE_BLINK,\n *      - LED_FORCE_OFF,\n *      - LED_FORCE_ON.\n */\nextern rtk_api_ret_t rtk_led_modeForce_set(rtk_port_t port, rtk_led_group_t group, rtk_led_force_mode_t mode);\n\n/* Function Name:\n *      rtk_led_modeForce_get\n * Description:\n *      Get Led group to congiuration force mode\n * Input:\n *      port  - port ID\n *      group - Support LED group id.\n *      pMode - Support LED force mode.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n *      RT_ERR_PORT_ID      - Error Port ID\n * Note:\n *      The API can get forced Led group mode.\n *      The force modes that can be set are as following:\n *      - LED_FORCE_NORMAL,\n *      - LED_FORCE_BLINK,\n *      - LED_FORCE_OFF,\n *      - LED_FORCE_ON.\n */\nextern rtk_api_ret_t rtk_led_modeForce_get(rtk_port_t port, rtk_led_group_t group, rtk_led_force_mode_t *pMode);\n\n/* Function Name:\n *      rtk_led_blinkRate_set\n * Description:\n *      Set LED blinking rate\n * Input:\n *      blinkRate - blinking rate.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n * Note:\n *      ASIC support 6 types of LED blinking rates at 43ms, 84ms, 120ms, 170ms, 340ms and 670ms.\n */\nextern rtk_api_ret_t rtk_led_blinkRate_set(rtk_led_blink_rate_t blinkRate);\n\n/* Function Name:\n *      rtk_led_blinkRate_get\n * Description:\n *      Get LED blinking rate at mode 0 to mode 3\n * Input:\n *      None\n * Output:\n *      pBlinkRate - blinking rate.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n * Note:\n *      There are  6 types of LED blinking rates at 43ms, 84ms, 120ms, 170ms, 340ms and 670ms.\n */\nextern rtk_api_ret_t rtk_led_blinkRate_get(rtk_led_blink_rate_t *pBlinkRate);\n\n/* Function Name:\n *      rtk_led_groupConfig_set\n * Description:\n *      Set per group Led to congiuration mode\n * Input:\n *      group   - LED group.\n *      config  - LED configuration\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n * Note:\n *      The API can set LED indicated information configuration for each LED group with 1 to 1 led mapping to each port.\n *      - Definition  LED Statuses      Description\n *      - 0000        LED_Off           LED pin Tri-State.\n *      - 0001        Dup/Col           Collision, Full duplex Indicator.\n *      - 0010        Link/Act          Link, Activity Indicator.\n *      - 0011        Spd1000           1000Mb/s Speed Indicator.\n *      - 0100        Spd100            100Mb/s Speed Indicator.\n *      - 0101        Spd10             10Mb/s Speed Indicator.\n *      - 0110        Spd1000/Act       1000Mb/s Speed/Activity Indicator.\n *      - 0111        Spd100/Act        100Mb/s Speed/Activity Indicator.\n *      - 1000        Spd10/Act         10Mb/s Speed/Activity Indicator.\n *      - 1001        Spd100 (10)/Act   10/100Mb/s Speed/Activity Indicator.\n *      - 1010        LoopDetect        LoopDetect Indicator.\n *      - 1011        EEE               EEE Indicator.\n *      - 1100        Link/Rx           Link, Activity Indicator.\n *      - 1101        Link/Tx           Link, Activity Indicator.\n *      - 1110        Master            Link on Master Indicator.\n *      - 1111        Act               Activity Indicator. Low for link established.\n */\nextern rtk_api_ret_t rtk_led_groupConfig_set(rtk_led_group_t group, rtk_led_congig_t config);\n\n/* Function Name:\n *      rtk_led_groupConfig_get\n * Description:\n *      Get Led group congiuration mode\n * Input:\n *      group - LED group.\n * Output:\n *      pConfig - LED configuration.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n * Note:\n *       The API can get LED indicated information configuration for each LED group.\n */\nextern rtk_api_ret_t rtk_led_groupConfig_get(rtk_led_group_t group, rtk_led_congig_t *pConfig);\n\n/* Function Name:\n *      rtk_led_groupAbility_set\n * Description:\n *      Configure per group Led ability\n * Input:\n *      group    - LED group.\n *      pAbility - LED ability\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n * Note:\n *      None.\n */\n\nextern rtk_api_ret_t rtk_led_groupAbility_set(rtk_led_group_t group, rtk_led_ability_t *pAbility);\n\n/* Function Name:\n *      rtk_led_groupAbility_get\n * Description:\n *      Get per group Led ability\n * Input:\n *      group    - LED group.\n *      pAbility - LED ability\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n * Note:\n *      None.\n */\n\nextern rtk_api_ret_t rtk_led_groupAbility_get(rtk_led_group_t group, rtk_led_ability_t *pAbility);\n\n/* Function Name:\n *      rtk_led_serialMode_set\n * Description:\n *      Set Led serial mode active congiuration\n * Input:\n *      active - LED group.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n * Note:\n *      The API can set LED serial mode active congiuration.\n */\nextern rtk_api_ret_t rtk_led_serialMode_set(rtk_led_active_t active);\n\n/* Function Name:\n *      rtk_led_serialMode_get\n * Description:\n *      Get Led group congiuration mode\n * Input:\n *      group - LED group.\n * Output:\n *      pConfig - LED configuration.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n * Note:\n *       The API can get LED serial mode active configuration.\n */\nextern rtk_api_ret_t rtk_led_serialMode_get(rtk_led_active_t *pActive);\n\n/* Function Name:\n *      rtk_led_OutputEnable_set\n * Description:\n *      This API set LED I/O state.\n * Input:\n *      enabled     - LED I/O state\n * Output:\n *      None.\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n *      RT_ERR_INPUT           - Error parameter\n * Note:\n *      This API set LED I/O state.\n */\nextern rtk_api_ret_t rtk_led_OutputEnable_set(rtk_enable_t state);\n\n\n/* Function Name:\n *      rtk_led_OutputEnable_get\n * Description:\n *      This API get LED I/O state.\n * Input:\n *      None.\n * Output:\n *      pEnabled        - LED I/O state\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n *      RT_ERR_INPUT           - Error parameter\n * Note:\n *      This API set current LED I/O  state.\n */\nextern rtk_api_ret_t rtk_led_OutputEnable_get(rtk_enable_t *pState);\n\n/* Function Name:\n *      rtk_led_serialModePortmask_set\n * Description:\n *      This API configure Serial LED output Group and portmask\n * Input:\n *      output          - output group\n *      pPortmask       - output portmask\n * Output:\n *      None.\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n *      RT_ERR_INPUT           - Error parameter\n * Note:\n *      None.\n */\nextern rtk_api_ret_t rtk_led_serialModePortmask_set(rtk_led_serialOutput_t output, rtk_portmask_t *pPortmask);\n\n/* Function Name:\n *      rtk_led_serialModePortmask_get\n * Description:\n *      This API get Serial LED output Group and portmask\n * Input:\n *      None.\n * Output:\n *      pOutput         - output group\n *      pPortmask       - output portmask\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n *      RT_ERR_INPUT           - Error parameter\n * Note:\n *      None.\n */\nextern rtk_api_ret_t rtk_led_serialModePortmask_get(rtk_led_serialOutput_t *pOutput, rtk_portmask_t *pPortmask);\n\n#endif /* __RTK_API_LED_H__ */\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/mirror.h",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * Purpose : RTL8367/RTL8367C switch high-level API\n *\n * Feature : The file includes Mirror module high-layer API defination\n *\n */\n\n#ifndef __RTK_API_MIRROR_H__\n#define __RTK_API_MIRROR_H__\n\ntypedef enum rtk_mirror_keep_e\n{\n    MIRROR_FOLLOW_VLAN = 0,\n    MIRROR_KEEP_ORIGINAL,\n    MIRROR_KEEP_END\n}rtk_mirror_keep_t;\n\n\n/* Function Name:\n *      rtk_mirror_portBased_set\n * Description:\n *      Set port mirror function.\n * Input:\n *      mirroring_port          - Monitor port.\n *      pMirrored_rx_portmask   - Rx mirror port mask.\n *      pMirrored_tx_portmask   - Tx mirror port mask.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number\n *      RT_ERR_PORT_MASK    - Invalid portmask.\n * Note:\n *      The API is to set mirror function of source port and mirror port.\n *      The mirror port can only be set to one port and the TX and RX mirror ports\n *      should be identical.\n */\nextern rtk_api_ret_t rtk_mirror_portBased_set(rtk_port_t mirroring_port, rtk_portmask_t *pMirrored_rx_portmask, rtk_portmask_t *pMirrored_tx_portmask);\n\n/* Function Name:\n *      rtk_mirror_portBased_get\n * Description:\n *      Get port mirror function.\n * Input:\n *      None\n * Output:\n *      pMirroring_port         - Monitor port.\n *      pMirrored_rx_portmask   - Rx mirror port mask.\n *      pMirrored_tx_portmask   - Tx mirror port mask.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n * Note:\n *      The API is to get mirror function of source port and mirror port.\n */\nextern rtk_api_ret_t rtk_mirror_portBased_get(rtk_port_t* pMirroring_port, rtk_portmask_t *pMirrored_rx_portmask, rtk_portmask_t *pMirrored_tx_portmask);\n\n/* Function Name:\n *      rtk_mirror_portIso_set\n * Description:\n *      Set mirror port isolation.\n * Input:\n *      enable |Mirror isolation status.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_ENABLE       - Invalid enable input\n * Note:\n *      The API is to set mirror isolation function that prevent normal forwarding packets to miror port.\n */\nextern rtk_api_ret_t rtk_mirror_portIso_set(rtk_enable_t enable);\n\n/* Function Name:\n *      rtk_mirror_portIso_get\n * Description:\n *      Get mirror port isolation.\n * Input:\n *      None\n * Output:\n *      pEnable |Mirror isolation status.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n * Note:\n *      The API is to get mirror isolation status.\n */\nextern rtk_api_ret_t rtk_mirror_portIso_get(rtk_enable_t *pEnable);\n\n/* Function Name:\n *      rtk_mirror_vlanLeaky_set\n * Description:\n *      Set mirror VLAN leaky.\n * Input:\n *      txenable -TX leaky enable.\n *      rxenable - RX leaky enable.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_ENABLE       - Invalid enable input\n * Note:\n *      The API is to set mirror VLAN leaky function forwarding packets to miror port.\n */\nextern rtk_api_ret_t rtk_mirror_vlanLeaky_set(rtk_enable_t txenable, rtk_enable_t rxenable);\n\n\n/* Function Name:\n *      rtk_mirror_vlanLeaky_get\n * Description:\n *      Get mirror VLAN leaky.\n * Input:\n *      None\n * Output:\n *      pTxenable - TX leaky enable.\n *      pRxenable - RX leaky enable.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n * Note:\n *      The API is to get mirror VLAN leaky status.\n */\nextern rtk_api_ret_t rtk_mirror_vlanLeaky_get(rtk_enable_t *pTxenable, rtk_enable_t *pRxenable);\n\n/* Function Name:\n *      rtk_mirror_isolationLeaky_set\n * Description:\n *      Set mirror Isolation leaky.\n * Input:\n *      txenable -TX leaky enable.\n *      rxenable - RX leaky enable.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_ENABLE       - Invalid enable input\n * Note:\n *      The API is to set mirror VLAN leaky function forwarding packets to miror port.\n */\nextern rtk_api_ret_t rtk_mirror_isolationLeaky_set(rtk_enable_t txenable, rtk_enable_t rxenable);\n\n/* Function Name:\n *      rtk_mirror_isolationLeaky_get\n * Description:\n *      Get mirror isolation leaky.\n * Input:\n *      None\n * Output:\n *      pTxenable - TX leaky enable.\n *      pRxenable - RX leaky enable.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n * Note:\n *      The API is to get mirror isolation leaky status.\n */\nextern rtk_api_ret_t rtk_mirror_isolationLeaky_get(rtk_enable_t *pTxenable, rtk_enable_t *pRxenable);\n\n/* Function Name:\n *      rtk_mirror_keep_set\n * Description:\n *      Set mirror packet format keep.\n * Input:\n *      mode - -mirror keep mode.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_ENABLE       - Invalid enable input\n * Note:\n *      The API is to set  -mirror keep mode.\n *      The mirror keep mode is as following:\n *      - MIRROR_FOLLOW_VLAN\n *      - MIRROR_KEEP_ORIGINAL\n *      - MIRROR_KEEP_END\n */\nextern rtk_api_ret_t rtk_mirror_keep_set(rtk_mirror_keep_t mode);\n\n\n/* Function Name:\n *      rtk_mirror_keep_get\n * Description:\n *      Get mirror packet format keep.\n * Input:\n *      None\n * Output:\n *      pMode -mirror keep mode.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n * Note:\n *      The API is to get mirror keep mode.\n  *      The mirror keep mode is as following:\n *      - MIRROR_FOLLOW_VLAN\n *      - MIRROR_KEEP_ORIGINAL\n *      - MIRROR_KEEP_END\n */\nextern rtk_api_ret_t rtk_mirror_keep_get(rtk_mirror_keep_t *pMode);\n\n/* Function Name:\n *      rtk_mirror_override_set\n * Description:\n *      Set port mirror override function.\n * Input:\n *      rxMirror        - 1: output mirrored packet, 0: output normal forward packet\n *      txMirror        - 1: output mirrored packet, 0: output normal forward packet\n *      aclMirror       - 1: output mirrored packet, 0: output normal forward packet\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n * Note:\n *      The API is to set mirror override function.\n *      This function control the output format when a port output\n *      normal forward & mirrored packet at the same time.\n */\nextern rtk_api_ret_t rtk_mirror_override_set(rtk_enable_t rxMirror, rtk_enable_t txMirror, rtk_enable_t aclMirror);\n\n/* Function Name:\n *      rtk_mirror_override_get\n * Description:\n *      Get port mirror override function.\n * Input:\n *      None\n * Output:\n *      pRxMirror       - 1: output mirrored packet, 0: output normal forward packet\n *      pTxMirror       - 1: output mirrored packet, 0: output normal forward packet\n *      pAclMirror      - 1: output mirrored packet, 0: output normal forward packet\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_NULL_POINTER - Null Pointer\n * Note:\n *      The API is to Get mirror override function.\n *      This function control the output format when a port output\n *      normal forward & mirrored packet at the same time.\n */\nextern rtk_api_ret_t rtk_mirror_override_get(rtk_enable_t *pRxMirror, rtk_enable_t *pTxMirror, rtk_enable_t *pAclMirror);\n\n#endif /* __RTK_API_MIRROR_H__ */\n\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/oam.h",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * $Revision: 76306 $\n * $Date: 2017-03-08 15:13:58 +0800 (週三, 08 三月 2017) $\n *\n * Purpose : RTL8367/RTL8367C switch high-level API\n *\n * Feature : The file includes the following modules and sub-modules\n *           (1) OAM (802.3ah) configuration\n *\n */\n\n#ifndef __RTK_OAM_H__\n#define __RTK_OAM_H__\n\n/*\n * Symbol Definition\n */\n\n\n/*\n * Data Declaration\n */\n\n\n/*\n * Macro Declaration\n */\n\ntypedef enum rtk_oam_parser_act_e\n{\n    OAM_PARSER_ACTION_FORWARD = 0,\n    OAM_PARSER_ACTION_LOOPBACK,\n    OAM_PARSER_ACTION_DISCARD,\n    OAM_PARSER_ACTION_END,\n\n} rtk_oam_parser_act_t;\n\ntypedef enum rtk_oam_multiplexer_act_e\n{\n    OAM_MULTIPLEXER_ACTION_FORWARD = 0,\n    OAM_MULTIPLEXER_ACTION_DISCARD,\n    OAM_MULTIPLEXER_ACTION_CPUONLY,\n    OAM_MULTIPLEXER_ACTION_END,\n\n} rtk_oam_multiplexer_act_t;\n\n\n/*\n * Function Declaration\n */\n\n/* Function Name:\n *      rtk_oam_init\n * Description:\n *      Initialize oam module.\n * Input:\n *      None\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n * Note:\n *      Must initialize oam module before calling any oam APIs.\n */\nextern rtk_api_ret_t rtk_oam_init(void);\n\n/* Function Name:\n *      rtk_oam_state_set\n * Description:\n *      This API set OAM state.\n * Input:\n *      enabled     -OAMstate\n * Output:\n *      None.\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n *      RT_ERR_INPUT           - Error parameter\n * Note:\n *      This API set OAM state.\n */\nextern rtk_api_ret_t rtk_oam_state_set(rtk_enable_t enabled);\n\n/* Function Name:\n *      rtk_oam_state_get\n * Description:\n *      This API get OAM state.\n * Input:\n *      None.\n * Output:\n *      pEnabled        - H/W IGMP state\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n *      RT_ERR_INPUT           - Error parameter\n * Note:\n *      This API set current OAM state.\n */\nextern rtk_api_ret_t rtk_oam_state_get(rtk_enable_t *pEnabled);\n\n\n/* Module Name : OAM */\n\n/* Function Name:\n *      rtk_oam_parserAction_set\n * Description:\n *      Set OAM parser action\n * Input:\n *      port    - port id\n *      action  - parser action\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n *      RT_ERR_PORT_ID      - invalid port id\n * Note:\n *      None\n */\nextern rtk_api_ret_t rtk_oam_parserAction_set(rtk_port_t port, rtk_oam_parser_act_t action);\n\n/* Function Name:\n *      rtk_oam_parserAction_set\n * Description:\n *      Get OAM parser action\n * Input:\n *      port    - port id\n * Output:\n *      pAction  - parser action\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n *      RT_ERR_PORT_ID      - invalid port id\n * Note:\n *      None\n */\nextern rtk_api_ret_t rtk_oam_parserAction_get(rtk_port_t port, rtk_oam_parser_act_t *pAction);\n\n\n/* Function Name:\n *      rtk_oam_multiplexerAction_set\n * Description:\n *      Set OAM multiplexer action\n * Input:\n *      port    - port id\n *      action  - parser action\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n *      RT_ERR_PORT_ID      - invalid port id\n * Note:\n *      None\n */\nextern rtk_api_ret_t rtk_oam_multiplexerAction_set(rtk_port_t port, rtk_oam_multiplexer_act_t action);\n\n/* Function Name:\n *      rtk_oam_multiplexerAction_set\n * Description:\n *      Get OAM multiplexer action\n * Input:\n *      port    - port id\n * Output:\n *      pAction  - parser action\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n *      RT_ERR_PORT_ID      - invalid port id\n * Note:\n *      None\n */\nextern rtk_api_ret_t rtk_oam_multiplexerAction_get(rtk_port_t port, rtk_oam_multiplexer_act_t *pAction);\n\n\n#endif /* __RTK_OAM_H__ */\n\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/port.h",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * Purpose : RTL8367/RTL8367C switch high-level API\n *\n * Feature : The file includes port module high-layer API defination\n *\n */\n\n#ifndef __RTK_API_PORT_H__\n#define __RTK_API_PORT_H__\n\n/*\n * Data Type Declaration\n */\n\n#define PHY_CONTROL_REG                             0\n#define PHY_STATUS_REG                              1\n#define PHY_AN_ADVERTISEMENT_REG                    4\n#define PHY_AN_LINKPARTNER_REG                      5\n#define PHY_1000_BASET_CONTROL_REG                  9\n#define PHY_1000_BASET_STATUS_REG                   10\n#define PHY_RESOLVED_REG                            26\n\n#define RTK_EFID_MAX                                0x7\n\n#define RTK_FIBER_FORCE_1000M                       3\n#define RTK_FIBER_FORCE_100M                        5\n#define RTK_FIBER_FORCE_100M1000M                   7\n\n#define RTK_INDRECT_ACCESS_CRTL                     0x1f00\n#define RTK_INDRECT_ACCESS_STATUS                   0x1f01\n#define RTK_INDRECT_ACCESS_ADDRESS                  0x1f02\n#define RTK_INDRECT_ACCESS_WRITE_DATA               0x1f03\n#define RTK_INDRECT_ACCESS_READ_DATA                0x1f04\n#define RTK_INDRECT_ACCESS_DELAY                    0x1f80\n#define RTK_INDRECT_ACCESS_BURST                    0x1f81\n#define RTK_RW_MASK                                 0x2\n#define RTK_CMD_MASK                                0x1\n#define RTK_PHY_BUSY_OFFSET                         2\n\n\ntypedef enum rtk_mode_ext_e\n{\n    MODE_EXT_DISABLE = 0,\n    MODE_EXT_RGMII,\n    MODE_EXT_MII_MAC,\n    MODE_EXT_MII_PHY,\n    MODE_EXT_TMII_MAC,\n    MODE_EXT_TMII_PHY,\n    MODE_EXT_GMII,\n    MODE_EXT_RMII_MAC,\n    MODE_EXT_RMII_PHY,\n    MODE_EXT_SGMII,\n    MODE_EXT_HSGMII,\n    MODE_EXT_1000X_100FX,\n    MODE_EXT_1000X,\n    MODE_EXT_100FX,\n    MODE_EXT_RGMII_2,\n    MODE_EXT_MII_MAC_2,\n    MODE_EXT_MII_PHY_2,\n    MODE_EXT_TMII_MAC_2,\n    MODE_EXT_TMII_PHY_2,\n    MODE_EXT_RMII_MAC_2,\n    MODE_EXT_RMII_PHY_2,\n    MODE_EXT_END\n} rtk_mode_ext_t;\n\ntypedef enum rtk_port_duplex_e\n{\n    PORT_HALF_DUPLEX = 0,\n    PORT_FULL_DUPLEX,\n    PORT_DUPLEX_END\n} rtk_port_duplex_t;\n\ntypedef enum rtk_port_linkStatus_e\n{\n    PORT_LINKDOWN = 0,\n    PORT_LINKUP,\n    PORT_LINKSTATUS_END\n} rtk_port_linkStatus_t;\n\ntypedef struct  rtk_port_mac_ability_s\n{\n    rtk_uint32 forcemode;\n    rtk_uint32 speed;\n    rtk_uint32 duplex;\n    rtk_uint32 link;\n    rtk_uint32 nway;\n    rtk_uint32 txpause;\n    rtk_uint32 rxpause;\n}rtk_port_mac_ability_t;\n\ntypedef struct rtk_port_phy_ability_s\n{\n    rtk_uint32    AutoNegotiation;  /*PHY register 0.12 setting for auto-negotiation process*/\n    rtk_uint32    Half_10;          /*PHY register 4.5 setting for 10BASE-TX half duplex capable*/\n    rtk_uint32    Full_10;          /*PHY register 4.6 setting for 10BASE-TX full duplex capable*/\n    rtk_uint32    Half_100;         /*PHY register 4.7 setting for 100BASE-TX half duplex capable*/\n    rtk_uint32    Full_100;         /*PHY register 4.8 setting for 100BASE-TX full duplex capable*/\n    rtk_uint32    Full_1000;        /*PHY register 9.9 setting for 1000BASE-T full duplex capable*/\n    rtk_uint32    FC;               /*PHY register 4.10 setting for flow control capability*/\n    rtk_uint32    AsyFC;            /*PHY register 4.11 setting for  asymmetric flow control capability*/\n} rtk_port_phy_ability_t;\n\ntypedef rtk_uint32  rtk_port_phy_data_t;     /* phy page  */\n\ntypedef enum rtk_port_phy_mdix_mode_e\n{\n    PHY_AUTO_CROSSOVER_MODE= 0,\n    PHY_FORCE_MDI_MODE,\n    PHY_FORCE_MDIX_MODE,\n    PHY_FORCE_MODE_END\n} rtk_port_phy_mdix_mode_t;\n\ntypedef enum rtk_port_phy_mdix_status_e\n{\n    PHY_STATUS_AUTO_MDI_MODE= 0,\n    PHY_STATUS_AUTO_MDIX_MODE,\n    PHY_STATUS_FORCE_MDI_MODE,\n    PHY_STATUS_FORCE_MDIX_MODE,\n    PHY_STATUS_FORCE_MODE_END\n} rtk_port_phy_mdix_status_t;\n\ntypedef rtk_uint32  rtk_port_phy_page_t;     /* phy page  */\n\ntypedef enum rtk_port_phy_reg_e\n{\n    PHY_REG_CONTROL             = 0,\n    PHY_REG_STATUS,\n    PHY_REG_IDENTIFIER_1,\n    PHY_REG_IDENTIFIER_2,\n    PHY_REG_AN_ADVERTISEMENT,\n    PHY_REG_AN_LINKPARTNER,\n    PHY_REG_1000_BASET_CONTROL  = 9,\n    PHY_REG_1000_BASET_STATUS,\n    PHY_REG_END                 = 32\n} rtk_port_phy_reg_t;\n\ntypedef enum rtk_port_phy_test_mode_e\n{\n    PHY_TEST_MODE_NORMAL= 0,\n    PHY_TEST_MODE_1,\n    PHY_TEST_MODE_2,\n    PHY_TEST_MODE_3,\n    PHY_TEST_MODE_4,\n    PHY_TEST_MODE_END\n} rtk_port_phy_test_mode_t;\n\ntypedef enum rtk_port_speed_e\n{\n    PORT_SPEED_10M = 0,\n    PORT_SPEED_100M,\n    PORT_SPEED_1000M,\n    PORT_SPEED_500M,\n    PORT_SPEED_2500M,\n    PORT_SPEED_END\n} rtk_port_speed_t;\n\ntypedef enum rtk_port_media_e\n{\n    PORT_MEDIA_COPPER = 0,\n    PORT_MEDIA_FIBER,\n    PORT_MEDIA_END\n}rtk_port_media_t;\n\ntypedef struct rtk_rtctResult_s\n{\n    rtk_port_speed_t    linkType;\n    union\n    {\n        struct fe_result_s\n        {\n            rtk_uint32      isRxShort;\n            rtk_uint32      isTxShort;\n            rtk_uint32      isRxOpen;\n            rtk_uint32      isTxOpen;\n            rtk_uint32      isRxMismatch;\n            rtk_uint32      isTxMismatch;\n            rtk_uint32      isRxLinedriver;\n            rtk_uint32      isTxLinedriver;\n            rtk_uint32      rxLen;\n            rtk_uint32      txLen;\n        } fe_result;\n\n        struct ge_result_s\n        {\n            rtk_uint32      channelAShort;\n            rtk_uint32      channelBShort;\n            rtk_uint32      channelCShort;\n            rtk_uint32      channelDShort;\n\n            rtk_uint32      channelAOpen;\n            rtk_uint32      channelBOpen;\n            rtk_uint32      channelCOpen;\n            rtk_uint32      channelDOpen;\n\n            rtk_uint32      channelAMismatch;\n            rtk_uint32      channelBMismatch;\n            rtk_uint32      channelCMismatch;\n            rtk_uint32      channelDMismatch;\n\n            rtk_uint32      channelALinedriver;\n            rtk_uint32      channelBLinedriver;\n            rtk_uint32      channelCLinedriver;\n            rtk_uint32      channelDLinedriver;\n\n            rtk_uint32      channelALen;\n            rtk_uint32      channelBLen;\n            rtk_uint32      channelCLen;\n            rtk_uint32      channelDLen;\n        } ge_result;\n    }result;\n} rtk_rtctResult_t;\n\n/* Function Name:\n *      rtk_port_phyAutoNegoAbility_set\n * Description:\n *      Set ethernet PHY auto-negotiation desired ability.\n * Input:\n *      port        - port id.\n *      pAbility    - Ability structure\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - OK\n *      RT_ERR_FAILED           - Failed\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_PORT_ID          - Invalid port number.\n *      RT_ERR_PHY_REG_ID       - Invalid PHY address\n *      RT_ERR_INPUT            - Invalid input parameters.\n *      RT_ERR_BUSYWAIT_TIMEOUT - PHY access busy\n * Note:\n *      If Full_1000 bit is set to 1, the AutoNegotiation will be automatic set to 1. While both AutoNegotiation and Full_1000 are set to 0, the PHY speed and duplex selection will\n *      be set as following 100F > 100H > 10F > 10H priority sequence.\n */\nextern rtk_api_ret_t rtk_port_phyAutoNegoAbility_set(rtk_port_t port, rtk_port_phy_ability_t *pAbility);\n\n/* Function Name:\n *      rtk_port_phyAutoNegoAbility_get\n * Description:\n *      Get PHY ability through PHY registers.\n * Input:\n *      port - Port id.\n * Output:\n *      pAbility - Ability structure\n * Return:\n *      RT_ERR_OK               - OK\n *      RT_ERR_FAILED           - Failed\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_PORT_ID          - Invalid port number.\n *      RT_ERR_PHY_REG_ID       - Invalid PHY address\n *      RT_ERR_INPUT            - Invalid input parameters.\n *      RT_ERR_BUSYWAIT_TIMEOUT - PHY access busy\n * Note:\n *      Get the capablity of specified PHY.\n */\nextern rtk_api_ret_t rtk_port_phyAutoNegoAbility_get(rtk_port_t port, rtk_port_phy_ability_t *pAbility);\n\n/* Function Name:\n *      rtk_port_phyForceModeAbility_set\n * Description:\n *      Set the port speed/duplex mode/pause/asy_pause in the PHY force mode.\n * Input:\n *      port        - port id.\n *      pAbility    - Ability structure\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - OK\n *      RT_ERR_FAILED           - Failed\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_PORT_ID          - Invalid port number.\n *      RT_ERR_PHY_REG_ID       - Invalid PHY address\n *      RT_ERR_INPUT            - Invalid input parameters.\n *      RT_ERR_BUSYWAIT_TIMEOUT - PHY access busy\n * Note:\n *      While both AutoNegotiation and Full_1000 are set to 0, the PHY speed and duplex selection will\n *      be set as following 100F > 100H > 10F > 10H priority sequence.\n */\nextern rtk_api_ret_t rtk_port_phyForceModeAbility_set(rtk_port_t port, rtk_port_phy_ability_t *pAbility);\n\n/* Function Name:\n *      rtk_port_phyForceModeAbility_get\n * Description:\n *      Get PHY ability through PHY registers.\n * Input:\n *      port - Port id.\n * Output:\n *      pAbility - Ability structure\n * Return:\n *      RT_ERR_OK               - OK\n *      RT_ERR_FAILED           - Failed\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_PORT_ID          - Invalid port number.\n *      RT_ERR_PHY_REG_ID       - Invalid PHY address\n *      RT_ERR_INPUT            - Invalid input parameters.\n *      RT_ERR_BUSYWAIT_TIMEOUT - PHY access busy\n * Note:\n *      Get the capablity of specified PHY.\n */\nextern rtk_api_ret_t rtk_port_phyForceModeAbility_get(rtk_port_t port, rtk_port_phy_ability_t *pAbility);\n\n/* Function Name:\n *      rtk_port_phyStatus_get\n * Description:\n *      Get ethernet PHY linking status\n * Input:\n *      port - Port id.\n * Output:\n *      linkStatus  - PHY link status\n *      speed       - PHY link speed\n *      duplex      - PHY duplex mode\n * Return:\n *      RT_ERR_OK               - OK\n *      RT_ERR_FAILED           - Failed\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_PORT_ID          - Invalid port number.\n *      RT_ERR_PHY_REG_ID       - Invalid PHY address\n *      RT_ERR_INPUT            - Invalid input parameters.\n *      RT_ERR_BUSYWAIT_TIMEOUT - PHY access busy\n * Note:\n *      API will return auto negotiation status of phy.\n */\nextern rtk_api_ret_t rtk_port_phyStatus_get(rtk_port_t port, rtk_port_linkStatus_t *pLinkStatus, rtk_port_speed_t *pSpeed, rtk_port_duplex_t *pDuplex);\n\n/* Function Name:\n *      rtk_port_macForceLink_set\n * Description:\n *      Set port force linking configuration.\n * Input:\n *      port            - port id.\n *      pPortability    - port ability configuration\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number.\n * Note:\n *      This API can set Port/MAC force mode properties.\n */\nextern rtk_api_ret_t rtk_port_macForceLink_set(rtk_port_t port, rtk_port_mac_ability_t *pPortability);\n\n/* Function Name:\n *      rtk_port_macForceLink_get\n * Description:\n *      Get port force linking configuration.\n * Input:\n *      port - Port id.\n * Output:\n *      pPortability - port ability configuration\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number.\n *      RT_ERR_INPUT        - Invalid input parameters.\n * Note:\n *      This API can get Port/MAC force mode properties.\n */\nextern rtk_api_ret_t rtk_port_macForceLink_get(rtk_port_t port, rtk_port_mac_ability_t *pPortability);\n\n/* Function Name:\n *      rtk_port_macForceLinkExt_set\n * Description:\n *      Set external interface force linking configuration.\n * Input:\n *      port            - external port ID\n *      mode            - external interface mode\n *      pPortability    - port ability configuration\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n * Note:\n *      This API can set external interface force mode properties.\n *      The external interface can be set to:\n *      - MODE_EXT_DISABLE,\n *      - MODE_EXT_RGMII,\n *      - MODE_EXT_MII_MAC,\n *      - MODE_EXT_MII_PHY,\n *      - MODE_EXT_TMII_MAC,\n *      - MODE_EXT_TMII_PHY,\n *      - MODE_EXT_GMII,\n *      - MODE_EXT_RMII_MAC,\n *      - MODE_EXT_RMII_PHY,\n *      - MODE_EXT_SGMII,\n *      - MODE_EXT_HSGMII,\n *      - MODE_EXT_1000X_100FX,\n *      - MODE_EXT_1000X,\n *      - MODE_EXT_100FX,\n */\nextern rtk_api_ret_t rtk_port_macForceLinkExt_set(rtk_port_t port, rtk_mode_ext_t mode, rtk_port_mac_ability_t *pPortability);\n\n/* Function Name:\n *      rtk_port_macForceLinkExt_get\n * Description:\n *      Set external interface force linking configuration.\n * Input:\n *      port            - external port ID\n * Output:\n *      pMode           - external interface mode\n *      pPortability    - port ability configuration\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n * Note:\n *      This API can get external interface force mode properties.\n */\nextern rtk_api_ret_t rtk_port_macForceLinkExt_get(rtk_port_t port, rtk_mode_ext_t *pMode, rtk_port_mac_ability_t *pPortability);\n\n/* Function Name:\n *      rtk_port_macStatus_get\n * Description:\n *      Get port link status.\n * Input:\n *      port - Port id.\n * Output:\n *      pPortstatus - port ability configuration\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number.\n * Note:\n *      This API can get Port/PHY properties.\n */\nextern rtk_api_ret_t rtk_port_macStatus_get(rtk_port_t port, rtk_port_mac_ability_t *pPortstatus);\n\n/* Function Name:\n *      rtk_port_macLocalLoopbackEnable_set\n * Description:\n *      Set Port Local Loopback. (Redirect TX to RX.)\n * Input:\n *      port    - Port id.\n *      enable  - Loopback state, 0:disable, 1:enable\n * Output:\n *      None.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number.\n * Note:\n *      This API can enable/disable Local loopback in MAC.\n *      For UTP port, This API will also enable the digital\n *      loopback bit in PHY register for sync of speed between\n *      PHY and MAC. For EXT port, users need to force the\n *      link state by themself.\n */\nextern rtk_api_ret_t rtk_port_macLocalLoopbackEnable_set(rtk_port_t port, rtk_enable_t enable);\n\n/* Function Name:\n *      rtk_port_macLocalLoopbackEnable_get\n * Description:\n *      Get Port Local Loopback. (Redirect TX to RX.)\n * Input:\n *      port    - Port id.\n * Output:\n *      pEnable  - Loopback state, 0:disable, 1:enable\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number.\n * Note:\n *      None.\n */\nextern rtk_api_ret_t rtk_port_macLocalLoopbackEnable_get(rtk_port_t port, rtk_enable_t *pEnable);\n\n/* Function Name:\n *      rtk_port_phyReg_set\n * Description:\n *      Set PHY register data of the specific port.\n * Input:\n *      port    - port id.\n *      reg     - Register id\n *      regData - Register data\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - OK\n *      RT_ERR_FAILED           - Failed\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_PORT_ID          - Invalid port number.\n *      RT_ERR_PHY_REG_ID       - Invalid PHY address\n *      RT_ERR_BUSYWAIT_TIMEOUT - PHY access busy\n * Note:\n *      This API can set PHY register data of the specific port.\n */\nextern rtk_api_ret_t rtk_port_phyReg_set(rtk_port_t port, rtk_port_phy_reg_t reg, rtk_port_phy_data_t value);\n\n/* Function Name:\n *      rtk_port_phyReg_get\n * Description:\n *      Get PHY register data of the specific port.\n * Input:\n *      port    - Port id.\n *      reg     - Register id\n * Output:\n *      pData   - Register data\n * Return:\n *      RT_ERR_OK               - OK\n *      RT_ERR_FAILED           - Failed\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_PORT_ID          - Invalid port number.\n *      RT_ERR_PHY_REG_ID       - Invalid PHY address\n *      RT_ERR_BUSYWAIT_TIMEOUT - PHY access busy\n * Note:\n *      This API can get PHY register data of the specific port.\n */\nextern rtk_api_ret_t rtk_port_phyReg_get(rtk_port_t port, rtk_port_phy_reg_t reg, rtk_port_phy_data_t *pData);\n\n/* Function Name:\n *      rtk_port_backpressureEnable_set\n * Description:\n *      Set the half duplex backpressure enable status of the specific port.\n * Input:\n *      port    - port id.\n *      enable  - Back pressure status.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number.\n *      RT_ERR_ENABLE       - Invalid enable input.\n * Note:\n *      This API can set the half duplex backpressure enable status of the specific port.\n *      The half duplex backpressure enable status of the port is as following:\n *      - DISABLE\n *      - ENABLE\n */\nextern rtk_api_ret_t rtk_port_backpressureEnable_set(rtk_port_t port, rtk_enable_t enable);\n\n/* Function Name:\n *      rtk_port_backpressureEnable_get\n * Description:\n *      Get the half duplex backpressure enable status of the specific port.\n * Input:\n *      port - Port id.\n * Output:\n *      pEnable - Back pressure status.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number.\n * Note:\n *      This API can get the half duplex backpressure enable status of the specific port.\n *      The half duplex backpressure enable status of the port is as following:\n *      - DISABLE\n *      - ENABLE\n */\nextern rtk_api_ret_t rtk_port_backpressureEnable_get(rtk_port_t port, rtk_enable_t *pEnable);\n\n/* Function Name:\n *      rtk_port_adminEnable_set\n * Description:\n *      Set port admin configuration of the specific port.\n * Input:\n *      port    - port id.\n *      enable  - Back pressure status.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number.\n *      RT_ERR_ENABLE       - Invalid enable input.\n * Note:\n *      This API can set port admin configuration of the specific port.\n *      The port admin configuration of the port is as following:\n *      - DISABLE\n *      - ENABLE\n */\nextern rtk_api_ret_t rtk_port_adminEnable_set(rtk_port_t port, rtk_enable_t enable);\n\n/* Function Name:\n *      rtk_port_adminEnable_get\n * Description:\n *      Get port admin configurationof the specific port.\n * Input:\n *      port - Port id.\n * Output:\n *      pEnable - Back pressure status.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number.\n * Note:\n *      This API can get port admin configuration of the specific port.\n *      The port admin configuration of the port is as following:\n *      - DISABLE\n *      - ENABLE\n */\nextern rtk_api_ret_t rtk_port_adminEnable_get(rtk_port_t port, rtk_enable_t *pEnable);\n\n/* Function Name:\n *      rtk_port_isolation_set\n * Description:\n *      Set permitted port isolation portmask\n * Input:\n *      port         - port id.\n *      pPortmask    - Permit port mask\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number.\n *      RT_ERR_PORT_MASK    - Invalid portmask.\n * Note:\n *      This API set the port mask that a port can trasmit packet to of each port\n *      A port can only transmit packet to ports included in permitted portmask\n */\nextern rtk_api_ret_t rtk_port_isolation_set(rtk_port_t port, rtk_portmask_t *pPortmask);\n\n/* Function Name:\n *      rtk_port_isolation_get\n * Description:\n *      Get permitted port isolation portmask\n * Input:\n *      port - Port id.\n * Output:\n *      pPortmask - Permit port mask\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number.\n * Note:\n *      This API get the port mask that a port can trasmit packet to of each port\n *      A port can only transmit packet to ports included in permitted portmask\n */\nextern rtk_api_ret_t rtk_port_isolation_get(rtk_port_t port, rtk_portmask_t *pPortmask);\n\n/* Function Name:\n *      rtk_port_rgmiiDelayExt_set\n * Description:\n *      Set RGMII interface delay value for TX and RX.\n * Input:\n *      txDelay - TX delay value, 1 for delay 2ns and 0 for no-delay\n *      rxDelay - RX delay value, 0~7 for delay setup.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n * Note:\n *      This API can set external interface 2 RGMII delay.\n *      In TX delay, there are 2 selection: no-delay and 2ns delay.\n *      In RX dekay, there are 8 steps for delay tunning. 0 for no-delay, and 7 for maximum delay.\n */\nextern rtk_api_ret_t rtk_port_rgmiiDelayExt_set(rtk_port_t port, rtk_data_t txDelay, rtk_data_t rxDelay);\n\n/* Function Name:\n *      rtk_port_rgmiiDelayExt_get\n * Description:\n *      Get RGMII interface delay value for TX and RX.\n * Input:\n *      None\n * Output:\n *      pTxDelay - TX delay value\n *      pRxDelay - RX delay value\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n * Note:\n *      This API can set external interface 2 RGMII delay.\n *      In TX delay, there are 2 selection: no-delay and 2ns delay.\n *      In RX dekay, there are 8 steps for delay tunning. 0 for n0-delay, and 7 for maximum delay.\n */\nextern rtk_api_ret_t rtk_port_rgmiiDelayExt_get(rtk_port_t port, rtk_data_t *pTxDelay, rtk_data_t *pRxDelay);\n\n/* Function Name:\n *      rtk_port_phyEnableAll_set\n * Description:\n *      Set all PHY enable status.\n * Input:\n *      enable - PHY Enable State.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_ENABLE       - Invalid enable input.\n * Note:\n *      This API can set all PHY status.\n *      The configuration of all PHY is as following:\n *      - DISABLE\n *      - ENABLE\n */\nextern rtk_api_ret_t rtk_port_phyEnableAll_set(rtk_enable_t enable);\n\n/* Function Name:\n *      rtk_port_phyEnableAll_get\n * Description:\n *      Get all PHY enable status.\n * Input:\n *      None\n * Output:\n *      pEnable - PHY Enable State.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n * Note:\n *      This API can set all PHY status.\n *      The configuration of all PHY is as following:\n *      - DISABLE\n *      - ENABLE\n */\nextern rtk_api_ret_t rtk_port_phyEnableAll_get(rtk_enable_t *pEnable);\n\n/* Function Name:\n *      rtk_port_efid_set\n * Description:\n *      Set port-based enhanced filtering database\n * Input:\n *      port - Port id.\n *      efid - Specified enhanced filtering database.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n *      RT_ERR_L2_FID - Invalid fid.\n *      RT_ERR_INPUT - Invalid input parameter.\n *      RT_ERR_PORT_ID - Invalid port ID.\n * Note:\n *      The API can set port-based enhanced filtering database.\n */\nextern rtk_api_ret_t rtk_port_efid_set(rtk_port_t port, rtk_data_t efid);\n\n/* Function Name:\n *      rtk_port_efid_get\n * Description:\n *      Get port-based enhanced filtering database\n * Input:\n *      port - Port id.\n * Output:\n *      pEfid - Specified enhanced filtering database.\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n *      RT_ERR_INPUT - Invalid input parameters.\n *      RT_ERR_PORT_ID - Invalid port ID.\n * Note:\n *      The API can get port-based enhanced filtering database status.\n */\nextern rtk_api_ret_t rtk_port_efid_get(rtk_port_t port, rtk_data_t *pEfid);\n\n/* Function Name:\n *      rtk_port_phyComboPortMedia_set\n * Description:\n *      Set Combo port media type\n * Input:\n *      port    - Port id. (Should be Port 4)\n *      media   - Media (COPPER or FIBER)\n * Output:\n *      None.\n * Return:\n *      RT_ERR_OK               - OK\n *      RT_ERR_FAILED           - Failed\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_INPUT            - Invalid input parameters.\n *      RT_ERR_PORT_ID          - Invalid port ID.\n * Note:\n *      The API can Set Combo port media type.\n */\nextern rtk_api_ret_t rtk_port_phyComboPortMedia_set(rtk_port_t port, rtk_port_media_t media);\n\n/* Function Name:\n *      rtk_port_phyComboPortMedia_get\n * Description:\n *      Get Combo port media type\n * Input:\n *      port    - Port id. (Should be Port 4)\n * Output:\n *      pMedia  - Media (COPPER or FIBER)\n * Return:\n *      RT_ERR_OK               - OK\n *      RT_ERR_FAILED           - Failed\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_INPUT            - Invalid input parameters.\n *      RT_ERR_PORT_ID          - Invalid port ID.\n * Note:\n *      The API can Set Combo port media type.\n */\nextern rtk_api_ret_t rtk_port_phyComboPortMedia_get(rtk_port_t port, rtk_port_media_t *pMedia);\n\n/* Function Name:\n *      rtk_port_rtctEnable_set\n * Description:\n *      Enable RTCT test\n * Input:\n *      pPortmask    - Port mask of RTCT enabled port\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - OK\n *      RT_ERR_FAILED           - Failed\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_PORT_MASK        - Invalid port mask.\n * Note:\n *      The API can enable RTCT Test\n */\nextern rtk_api_ret_t rtk_port_rtctEnable_set(rtk_portmask_t *pPortmask);\n\n/* Function Name:\n *      rtk_port_rtctDisable_set\n * Description:\n *      Disable RTCT test\n * Input:\n *      pPortmask    - Port mask of RTCT disabled port\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - OK\n *      RT_ERR_FAILED           - Failed\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_PORT_MASK        - Invalid port mask.\n * Note:\n *      The API can disable RTCT Test\n */\nrtk_api_ret_t rtk_port_rtctDisable_set(rtk_portmask_t *pPortmask);\n\n\n/* Function Name:\n *      rtk_port_rtctResult_get\n * Description:\n *      Get the result of RTCT test\n * Input:\n *      port        - Port ID\n * Output:\n *      pRtctResult - The result of RTCT result\n * Return:\n *      RT_ERR_OK                   - OK\n *      RT_ERR_FAILED               - Failed\n *      RT_ERR_SMI                  - SMI access error\n *      RT_ERR_PORT_ID              - Invalid port ID.\n *      RT_ERR_PHY_RTCT_NOT_FINISH  - Testing does not finish.\n * Note:\n *      The API can get RTCT test result.\n *      RTCT test may takes 4.8 seconds to finish its test at most.\n *      Thus, if this API return RT_ERR_PHY_RTCT_NOT_FINISH or\n *      other error code, the result can not be referenced and\n *      user should call this API again until this API returns\n *      a RT_ERR_OK.\n *      The result is stored at pRtctResult->ge_result\n *      pRtctResult->linkType is unused.\n *      The unit of channel length is 2.5cm. Ex. 300 means 300 * 2.5 = 750cm = 7.5M\n */\nextern rtk_api_ret_t rtk_port_rtctResult_get(rtk_port_t port, rtk_rtctResult_t *pRtctResult);\n\n/* Function Name:\n *      rtk_port_sds_reset\n * Description:\n *      Reset Serdes\n * Input:\n *      port        - Port ID\n * Output:\n *      None.\n * Return:\n *      RT_ERR_OK                   - OK\n *      RT_ERR_FAILED               - Failed\n *      RT_ERR_SMI                  - SMI access error\n *      RT_ERR_PORT_ID              - Invalid port ID.\n * Note:\n *      The API can reset Serdes\n */\nextern rtk_api_ret_t rtk_port_sds_reset(rtk_port_t port);\n\n/* Function Name:\n *      rtk_port_sgmiiLinkStatus_get\n * Description:\n *      Get SGMII status\n * Input:\n *      port        - Port ID\n * Output:\n *      pSignalDetect   - Signal detect\n *      pSync           - Sync\n *      pLink           - Link\n * Return:\n *      RT_ERR_OK                   - OK\n *      RT_ERR_FAILED               - Failed\n *      RT_ERR_SMI                  - SMI access error\n *      RT_ERR_PORT_ID              - Invalid port ID.\n * Note:\n *      The API can reset Serdes\n */\nextern rtk_api_ret_t rtk_port_sgmiiLinkStatus_get(rtk_port_t port, rtk_data_t *pSignalDetect, rtk_data_t *pSync, rtk_port_linkStatus_t *pLink);\n\n/* Function Name:\n *      rtk_port_sgmiiNway_set\n * Description:\n *      Configure SGMII/HSGMII port Nway state\n * Input:\n *      port        - Port ID\n *      state       - Nway state\n * Output:\n *      None.\n * Return:\n *      RT_ERR_OK                   - OK\n *      RT_ERR_FAILED               - Failed\n *      RT_ERR_SMI                  - SMI access error\n *      RT_ERR_PORT_ID              - Invalid port ID.\n * Note:\n *      The API configure SGMII/HSGMII port Nway state\n */\nextern rtk_api_ret_t rtk_port_sgmiiNway_set(rtk_port_t port, rtk_enable_t state);\n\n/* Function Name:\n *      rtk_port_sgmiiNway_get\n * Description:\n *      Get SGMII/HSGMII port Nway state\n * Input:\n *      port        - Port ID\n * Output:\n *      pState      - Nway state\n * Return:\n *      RT_ERR_OK                   - OK\n *      RT_ERR_FAILED               - Failed\n *      RT_ERR_SMI                  - SMI access error\n *      RT_ERR_PORT_ID              - Invalid port ID.\n * Note:\n *      The API can get SGMII/HSGMII port Nway state\n */\nextern rtk_api_ret_t rtk_port_sgmiiNway_get(rtk_port_t port, rtk_enable_t *pState);\n\n#endif /* __RTK_API_PORT_H__ */\n\n\n\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/ptp.h",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * Purpose : RTL8367/RTL8367C switch high-level API\n *\n * Feature : The file includes time module high-layer API defination\n *\n */\n\n#ifndef __RTK_API_PTP_H__\n#define __RTK_API_PTP_H__\n\n/*\n * Symbol Definition\n */\n#define RTK_MAX_NUM_OF_NANO_SECOND                     0x3B9AC9FF\n#define RTK_PTP_INTR_MASK                                          0xFF\n#define RTK_MAX_NUM_OF_TPID                                    0xFFFF\n\n/* Message Type */\ntypedef enum rtk_ptp_msgType_e\n{\n    PTP_MSG_TYPE_TX_SYNC = 0,\n    PTP_MSG_TYPE_TX_DELAY_REQ,\n    PTP_MSG_TYPE_TX_PDELAY_REQ,\n    PTP_MSG_TYPE_TX_PDELAY_RESP,\n    PTP_MSG_TYPE_RX_SYNC,\n    PTP_MSG_TYPE_RX_DELAY_REQ,\n    PTP_MSG_TYPE_RX_PDELAY_REQ,\n    PTP_MSG_TYPE_RX_PDELAY_RESP,\n    PTP_MSG_TYPE_END\n} rtk_ptp_msgType_t;\n\ntypedef enum rtk_ptp_intType_e\n{\n    PTP_INT_TYPE_TX_SYNC = 0,\n    PTP_INT_TYPE_TX_DELAY_REQ,\n    PTP_INT_TYPE_TX_PDELAY_REQ,\n    PTP_INT_TYPE_TX_PDELAY_RESP,\n    PTP_INT_TYPE_RX_SYNC,\n    PTP_INT_TYPE_RX_DELAY_REQ,\n    PTP_INT_TYPE_RX_PDELAY_REQ,\n    PTP_INT_TYPE_RX_PDELAY_RESP,\n    PTP_INT_TYPE_ALL,\n    PTP_INT_TYPE_END\n}rtk_ptp_intType_t;\n\ntypedef enum rtk_ptp_sys_adjust_e\n{\n    SYS_ADJUST_PLUS = 0,\n    SYS_ADJUST_MINUS,\n    SYS_ADJUST_END\n} rtk_ptp_sys_adjust_t;\n\n\n/* Reference Time */\ntypedef struct rtk_ptp_timeStamp_s\n{\n    rtk_uint32 sec;\n    rtk_uint32 nsec;\n} rtk_ptp_timeStamp_t;\n\ntypedef struct rtk_ptp_info_s\n{\n    rtk_uint32 sequenceId;\n    rtk_ptp_timeStamp_t   timeStamp;\n} rtk_ptp_info_t;\n\ntypedef rtk_uint32 rtk_ptp_tpid_t;\n\ntypedef rtk_uint32  rtk_ptp_intStatus_t;     /* interrupt status mask  */\n\n/*\n * Data Declaration\n */\n\n/*\n * Function Declaration\n */\n/* Function Name:\n *      rtk_time_init\n * Description:\n *      PTP function initialization.\n * Input:\n *      None\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n * Note:\n *      This API is used to initialize EEE status.\n */\nextern rtk_api_ret_t rtk_ptp_init(void);\n\n/* Function Name:\n *      rtk_ptp_mac_set\n * Description:\n *      Configure PTP mac address.\n * Input:\n *      mac - mac address to parser PTP packets.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameter.\n * Note:\n *      None\n */\nextern rtk_api_ret_t rtk_ptp_mac_set(rtk_mac_t mac);\n\n/* Function Name:\n *      rtk_ptp_mac_get\n * Description:\n *      Get PTP mac address.\n * Input:\n *      None\n * Output:\n *      pMac - mac address to parser PTP packets.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameter.\n * Note:\n *      None\n */\nextern rtk_api_ret_t rtk_ptp_mac_get(rtk_mac_t *pMac);\n\n/* Function Name:\n *      rtk_ptp_tpid_set\n * Description:\n *      Configure PTP accepted outer & inner tag TPID.\n * Input:\n *      outerId - Ether type of S-tag frame parsing in PTP ports.\n *      innerId - Ether type of C-tag frame parsing in PTP ports.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameter.\n * Note:\n *      None\n */\nextern rtk_api_ret_t rtk_ptp_tpid_set(rtk_ptp_tpid_t outerId, rtk_ptp_tpid_t innerId);\n\n/* Function Name:\n *      rtk_ptp_tpid_get\n * Description:\n *      Get PTP accepted outer & inner tag TPID.\n * Input:\n *      None\n * Output:\n *      pOuterId - Ether type of S-tag frame parsing in PTP ports.\n *      pInnerId - Ether type of C-tag frame parsing in PTP ports.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n * Note:\n *      None\n */\nextern rtk_api_ret_t rtk_ptp_tpid_get(rtk_ptp_tpid_t *pOuterId, rtk_ptp_tpid_t *pInnerId);\n\n/* Function Name:\n *      rtk_ptp_refTime_set\n * Description:\n *      Set the reference time of the specified device.\n * Input:\n *      timeStamp - reference timestamp value\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n *      RT_ERR_INPUT    - invalid input parameter\n * Applicable:\n *      8390, 8380\n * Note:\n *      None\n */\nextern rtk_api_ret_t rtk_ptp_refTime_set(rtk_ptp_timeStamp_t timeStamp);\n\n/* Function Name:\n *      rtk_ptp_refTime_get\n * Description:\n *      Get the reference time of the specified device.\n * Input:\n * Output:\n *      pTimeStamp - pointer buffer of the reference time\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n *      RT_ERR_UNIT_ID      - invalid unit id\n *      RT_ERR_NOT_INIT     - The module is not initial\n *      RT_ERR_NULL_POINTER - input parameter may be null pointer\n * Applicable:\n *      8390, 8380\n * Note:\n *      None\n */\nextern rtk_api_ret_t rtk_ptp_refTime_get(rtk_ptp_timeStamp_t *pTimeStamp);\n\n/* Function Name:\n *      rtk_ptp_refTimeAdjust_set\n * Description:\n *      Adjust the reference time.\n * Input:\n *      unit      - unit id\n *      sign      - significant\n *      timeStamp - reference timestamp value\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n *      RT_ERR_UNIT_ID  - invalid unit id\n *      RT_ERR_NOT_INIT - The module is not initial\n *      RT_ERR_INPUT    - invalid input parameter\n * Note:\n *      sign=0 for positive adjustment, sign=1 for negative adjustment.\n */\nextern rtk_api_ret_t rtk_ptp_refTimeAdjust_set(rtk_ptp_sys_adjust_t sign, rtk_ptp_timeStamp_t timeStamp);\n\n/* Function Name:\n *      rtk_ptp_refTimeEnable_set\n * Description:\n *      Set the enable state of reference time of the specified device.\n * Input:\n *      enable - status\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n *      RT_ERR_INPUT    - invalid input parameter\n * Note:\n *      None\n */\nextern rtk_api_ret_t rtk_ptp_refTimeEnable_set(rtk_enable_t enable);\n\n/* Function Name:\n *      rtk_ptp_refTimeEnable_get\n * Description:\n *      Get the enable state of reference time of the specified device.\n * Input:\n * Output:\n *      pEnable - status\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n *      RT_ERR_UNIT_ID      - invalid unit id\n *      RT_ERR_NOT_INIT     - The module is not initial\n *      RT_ERR_NULL_POINTER - input parameter may be null pointer\n * Applicable:\n *      8390, 8380\n * Note:\n *      None\n */\nextern rtk_api_ret_t rtk_ptp_refTimeEnable_get(rtk_enable_t *pEnable);\n\n/* Function Name:\n *      rtk_ptp_portEnable_set\n * Description:\n *      Set PTP status of the specified port.\n * Input:\n *      port   - port id\n *      enable - status\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n *      RT_ERR_PORT     - invalid port id\n *      RT_ERR_INPUT    - invalid input parameter\n * Note:\n *      None\n */\nextern rtk_api_ret_t rtk_ptp_portEnable_set(rtk_port_t port, rtk_enable_t enable);\n\n/* Function Name:\n *      rtk_ptp_portEnable_get\n * Description:\n *      Get PTP status of the specified port.\n * Input:\n *      port    - port id\n * Output:\n *      pEnable - status\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n *      RT_ERR_PORT         - invalid port id\n *      RT_ERR_NULL_POINTER - input parameter may be null pointer\n * Note:\n *      None\n */\nextern rtk_api_ret_t rtk_ptp_portEnable_get(rtk_port_t port, rtk_enable_t *pEnable);\n\n/* Function Name:\n *      rtk_ptp_portTimestamp_get\n * Description:\n *      Get PTP timstamp according to the PTP identifier on the dedicated port from the specified device.\n * Input:\n *      unit       - unit id\n *      port       - port id\n *      type       - PTP message type\n * Output:\n *      pInfo      - pointer buffer of sequence ID and timestamp\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n *      RT_ERR_PORT_ID      - invalid port id\n *      RT_ERR_INPUT        - invalid input parameter\n *      RT_ERR_NULL_POINTER - input parameter may be null pointer\n * Applicable:\n *      8390, 8380\n * Note:\n *      None\n */\nextern rtk_api_ret_t rtk_ptp_portTimestamp_get( rtk_port_t port, rtk_ptp_msgType_t type, rtk_ptp_info_t *pInfo);\n\n/* Function Name:\n *      rtk_ptp_intControl_set\n * Description:\n *      Set PTP interrupt trigger status configuration.\n * Input:\n *      type - Interrupt type.\n *      enable - Interrupt status.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n *      RT_ERR_ENABLE       - Invalid enable input.\n * Note:\n *      The API can set PTP interrupt status configuration.\n *      The interrupt trigger status is shown in the following:\n *          PTP_INT_TYPE_TX_SYNC = 0,\n *          PTP_INT_TYPE_TX_DELAY_REQ,\n *          PTP_INT_TYPE_TX_PDELAY_REQ,\n *          PTP_INT_TYPE_TX_PDELAY_RESP,\n *          PTP_INT_TYPE_RX_SYNC,\n *          PTP_INT_TYPE_RX_DELAY_REQ,\n *          PTP_INT_TYPE_RX_PDELAY_REQ,\n *          PTP_INT_TYPE_RX_PDELAY_RESP,\n *          PTP_INT_TYPE_ALL,\n */\nextern rtk_api_ret_t rtk_ptp_intControl_set(rtk_ptp_intType_t type, rtk_enable_t enable);\n\n/* Function Name:\n *      rtk_ptp_intControl_get\n * Description:\n *      Get PTP interrupt trigger status configuration.\n * Input:\n *      type - Interrupt type.\n * Output:\n *      pEnable - Interrupt status.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n * Note:\n *      The API can get interrupt status configuration.\n *      The interrupt trigger status is shown in the following:\n *          PTP_INT_TYPE_TX_SYNC = 0,\n *          PTP_INT_TYPE_TX_DELAY_REQ,\n *          PTP_INT_TYPE_TX_PDELAY_REQ,\n *          PTP_INT_TYPE_TX_PDELAY_RESP,\n *          PTP_INT_TYPE_RX_SYNC,\n *          PTP_INT_TYPE_RX_DELAY_REQ,\n *          PTP_INT_TYPE_RX_PDELAY_REQ,\n *          PTP_INT_TYPE_RX_PDELAY_RESP,\n */\nextern rtk_api_ret_t rtk_ptp_intControl_get(rtk_ptp_intType_t type, rtk_enable_t *pEnable);\n\n\n/* Function Name:\n *      rtk_ptp_intStatus_get\n * Description:\n *      Get PTP port interrupt trigger status.\n * Input:\n *      port           - physical port\n * Output:\n *      pStatusMask - Interrupt status bit mask.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n * Note:\n *      The API can get interrupt trigger status when interrupt happened.\n *      The interrupt trigger status is shown in the following:\n *      - PORT 0  INT    (value[0] (Bit0))\n *      - PORT 1  INT    (value[0] (Bit1))\n *      - PORT 2  INT    (value[0] (Bit2))\n *      - PORT 3  INT    (value[0] (Bit3))\n *      - PORT 4  INT   (value[0] (Bit4))\n\n *\n */\nextern rtk_api_ret_t rtk_ptp_intStatus_get(rtk_ptp_intStatus_t *pStatusMask);\n\n/* Function Name:\n *      rtk_ptp_portIntStatus_set\n * Description:\n *      Set PTP port interrupt trigger status to clean.\n * Input:\n *      port           - physical port\n *      statusMask - Interrupt status bit mask.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n *      RT_ERR_INPUT - Invalid input parameters.\n * Note:\n *      The API can clean interrupt trigger status when interrupt happened.\n *      The interrupt trigger status is shown in the following:\n *      - PTP_INT_TYPE_TX_SYNC              (value[0] (Bit0))\n *      - PTP_INT_TYPE_TX_DELAY_REQ      (value[0] (Bit1))\n *      - PTP_INT_TYPE_TX_PDELAY_REQ    (value[0] (Bit2))\n *      - PTP_INT_TYPE_TX_PDELAY_RESP   (value[0] (Bit3))\n *      - PTP_INT_TYPE_RX_SYNC              (value[0] (Bit4))\n *      - PTP_INT_TYPE_RX_DELAY_REQ      (value[0] (Bit5))\n *      - PTP_INT_TYPE_RX_PDELAY_REQ    (value[0] (Bit6))\n *      - PTP_INT_TYPE_RX_PDELAY_RESP   (value[0] (Bit7))\n *      The status will be cleared after execute this API.\n */\nextern rtk_api_ret_t rtk_ptp_portIntStatus_set(rtk_port_t port, rtk_ptp_intStatus_t statusMask);\n\n/* Function Name:\n *      rtk_ptp_portIntStatus_get\n * Description:\n *      Get PTP port interrupt trigger status.\n * Input:\n *      port           - physical port\n * Output:\n *      pStatusMask - Interrupt status bit mask.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n * Note:\n *      The API can get interrupt trigger status when interrupt happened.\n *      The interrupt trigger status is shown in the following:\n *      - PTP_INT_TYPE_TX_SYNC              (value[0] (Bit0))\n *      - PTP_INT_TYPE_TX_DELAY_REQ      (value[0] (Bit1))\n *      - PTP_INT_TYPE_TX_PDELAY_REQ    (value[0] (Bit2))\n *      - PTP_INT_TYPE_TX_PDELAY_RESP   (value[0] (Bit3))\n *      - PTP_INT_TYPE_RX_SYNC              (value[0] (Bit4))\n *      - PTP_INT_TYPE_RX_DELAY_REQ      (value[0] (Bit5))\n *      - PTP_INT_TYPE_RX_PDELAY_REQ    (value[0] (Bit6))\n *      - PTP_INT_TYPE_RX_PDELAY_RESP   (value[0] (Bit7))\n *\n */\nextern rtk_api_ret_t rtk_ptp_portIntStatus_get(rtk_port_t port, rtk_ptp_intStatus_t *pStatusMask);\n\n/* Function Name:\n *      rtk_ptp_portPtpTrap_set\n * Description:\n *      Set PTP packet trap of the specified port.\n * Input:\n *      port   - port id\n *      enable - status\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n *      RT_ERR_PORT     - invalid port id\n *      RT_ERR_INPUT    - invalid input parameter\n * Note:\n *      None\n */\nextern rtk_api_ret_t rtk_ptp_portTrap_set(rtk_port_t port, rtk_enable_t enable);\n\n/* Function Name:\n *      rtk_ptp_portPtpEnable_get\n * Description:\n *      Get PTP packet trap of the specified port.\n * Input:\n *      port    - port id\n * Output:\n *      pEnable - status\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n *      RT_ERR_PORT         - invalid port id\n *      RT_ERR_NULL_POINTER - input parameter may be null pointer\n * Note:\n *      None\n */\nextern rtk_api_ret_t rtk_ptp_portTrap_get(rtk_port_t port, rtk_enable_t *pEnable);\n\n#endif /* __RTK_API_PTP_H__ */\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/qos.h",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * Purpose : RTL8367/RTL8367C switch high-level API\n *\n * Feature : The file includes QoS module high-layer API defination\n *\n */\n\n#ifndef __RTK_API_QOS_H__\n#define __RTK_API_QOS_H__\n\n/*\n * Data Type Declaration\n */\n#define QOS_DEFAULT_TICK_PERIOD                     (19-1)\n#define QOS_DEFAULT_BYTE_PER_TOKEN                  34\n#define QOS_DEFAULT_LK_THRESHOLD                    (34*3) /* Why use 0x400? */\n\n\n#define QOS_DEFAULT_INGRESS_BANDWIDTH               0x3FFF /* 0x3FFF => unlimit */\n#define QOS_DEFAULT_EGRESS_BANDWIDTH                0x3D08 /*( 0x3D08 + 1) * 64Kbps => 1Gbps*/\n#define QOS_DEFAULT_PREIFP                          1\n#define QOS_DEFAULT_PACKET_USED_PAGES_FC            0x60\n#define QOS_DEFAULT_PACKET_USED_FC_EN               0\n#define QOS_DEFAULT_QUEUE_BASED_FC_EN               1\n\n#define QOS_DEFAULT_PRIORITY_SELECT_PORT            8\n#define QOS_DEFAULT_PRIORITY_SELECT_1Q              0\n#define QOS_DEFAULT_PRIORITY_SELECT_ACL             0\n#define QOS_DEFAULT_PRIORITY_SELECT_DSCP            0\n\n#define QOS_DEFAULT_DSCP_MAPPING_PRIORITY           0\n\n#define QOS_DEFAULT_1Q_REMARKING_ABILITY            0\n#define QOS_DEFAULT_DSCP_REMARKING_ABILITY          0\n#define QOS_DEFAULT_QUEUE_GAP                       20\n#define QOS_DEFAULT_QUEUE_NO_MAX                    6\n#define QOS_DEFAULT_AVERAGE_PACKET_RATE             0x3FFF\n#define QOS_DEFAULT_BURST_SIZE_IN_APR               0x3F\n#define QOS_DEFAULT_PEAK_PACKET_RATE                2\n#define QOS_DEFAULT_SCHEDULER_ABILITY_APR           1     /*disable*/\n#define QOS_DEFAULT_SCHEDULER_ABILITY_PPR           1    /*disable*/\n#define QOS_DEFAULT_SCHEDULER_ABILITY_WFQ           1    /*disable*/\n\n#define QOS_WEIGHT_MAX                              127\n\n#define RTK_MAX_NUM_OF_PRIORITY                     8\n#define RTK_MAX_NUM_OF_QUEUE                        8\n\n#define RTK_PRIMAX                                             7\n#define RTK_QIDMAX                                             7\n#define RTK_DSCPMAX                                         63\n\n\n/* enum Priority Selection Index */\ntypedef enum rtk_qos_priDecTbl_e\n{\n    PRIDECTBL_IDX0 = 0,\n    PRIDECTBL_IDX1,\n    PRIDECTBL_END,\n}rtk_qos_priDecTbl_t;\n\n\n/* Types of 802.1p remarking source */\ntypedef enum rtk_qos_1pRmkSrc_e\n{\n    DOT1P_RMK_SRC_USER_PRI,\n    DOT1P_RMK_SRC_TAG_PRI,\n    DOT1P_RMK_SRC_END\n} rtk_qos_1pRmkSrc_t;\n\n\n/* Types of DSCP remarking source */\ntypedef enum rtk_qos_dscpRmkSrc_e\n{\n    DSCP_RMK_SRC_INT_PRI,\n    DSCP_RMK_SRC_DSCP,\n    DSCP_RMK_SRC_USER_PRI,\n    DSCP_RMK_SRC_END\n} rtk_qos_dscpRmkSrc_t;\n\n\n\n\ntypedef struct rtk_priority_select_s\n{\n    rtk_uint32 port_pri;\n    rtk_uint32 dot1q_pri;\n    rtk_uint32 acl_pri;\n    rtk_uint32 dscp_pri;\n    rtk_uint32 cvlan_pri;\n    rtk_uint32 svlan_pri;\n    rtk_uint32 dmac_pri;\n    rtk_uint32 smac_pri;\n} rtk_priority_select_t;\n\ntypedef struct rtk_qos_pri2queue_s\n{\n    rtk_uint32 pri2queue[RTK_MAX_NUM_OF_PRIORITY];\n} rtk_qos_pri2queue_t;\n\ntypedef struct rtk_qos_queue_weights_s\n{\n    rtk_uint32 weights[RTK_MAX_NUM_OF_QUEUE];\n} rtk_qos_queue_weights_t;\n\ntypedef enum rtk_qos_scheduling_type_e\n{\n    WFQ = 0,        /* Weighted-Fair-Queue */\n    WRR,            /* Weighted-Round-Robin */\n    SCHEDULING_TYPE_END\n} rtk_qos_scheduling_type_t;\n\ntypedef rtk_uint32  rtk_queue_num_t;    /* queue number*/\n\n/* Function Name:\n *      rtk_qos_init\n * Description:\n *      Configure Qos default settings with queue number assigment to each port.\n * Input:\n *      queueNum - Queue number of each port.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_QUEUE_NUM    - Invalid queue number.\n *      RT_ERR_INPUT        - Invalid input parameters.\n * Note:\n *      This API will initialize related Qos setting with queue number assigment.\n *      The queue number is from 1 to 8.\n */\nextern rtk_api_ret_t rtk_qos_init(rtk_queue_num_t queueNum);\n\n/* Function Name:\n *      rtk_qos_priSel_set\n * Description:\n *      Configure the priority order among different priority mechanism.\n * Input:\n *      index - Priority decision table index (0~1)\n *      pPriDec - Priority assign for port, dscp, 802.1p, cvlan, svlan, acl based priority decision.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK                   - OK\n *      RT_ERR_FAILED               - Failed\n *      RT_ERR_SMI                  - SMI access error\n *      RT_ERR_QOS_SEL_PRI_SOURCE   - Invalid priority decision source parameter.\n * Note:\n *      ASIC will follow user priority setting of mechanisms to select mapped queue priority for receiving frame.\n *      If two priority mechanisms are the same, the ASIC will chose the highest priority from mechanisms to\n *      assign queue priority to receiving frame.\n *      The priority sources are:\n *      - PRIDEC_PORT\n *      - PRIDEC_ACL\n *      - PRIDEC_DSCP\n *      - PRIDEC_1Q\n *      - PRIDEC_1AD\n *      - PRIDEC_CVLAN\n *      - PRIDEC_DA\n *      - PRIDEC_SA\n */\nextern rtk_api_ret_t rtk_qos_priSel_set(rtk_qos_priDecTbl_t index, rtk_priority_select_t *pPriDec);\n\n\n/* Function Name:\n *      rtk_qos_priSel_get\n * Description:\n *      Get the priority order configuration among different priority mechanism.\n * Input:\n *      index - Priority decision table index (0~1)\n * Output:\n *      pPriDec - Priority assign for port, dscp, 802.1p, cvlan, svlan, acl based priority decision .\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n * Note:\n *      ASIC will follow user priority setting of mechanisms to select mapped queue priority for receiving frame.\n *      If two priority mechanisms are the same, the ASIC will chose the highest priority from mechanisms to\n *      assign queue priority to receiving frame.\n *      The priority sources are:\n *      - PRIDEC_PORT,\n *      - PRIDEC_ACL,\n *      - PRIDEC_DSCP,\n *      - PRIDEC_1Q,\n *      - PRIDEC_1AD,\n *      - PRIDEC_CVLAN,\n *      - PRIDEC_DA,\n *      - PRIDEC_SA,\n */\nextern rtk_api_ret_t rtk_qos_priSel_get(rtk_qos_priDecTbl_t index, rtk_priority_select_t *pPriDec);\n\n/* Function Name:\n *      rtk_qos_1pPriRemap_set\n * Description:\n *      Configure 1Q priorities mapping to internal absolute priority.\n * Input:\n *      dot1p_pri   - 802.1p priority value.\n *      int_pri     - internal priority value.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - OK\n *      RT_ERR_FAILED           - Failed\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_INPUT            - Invalid input parameters.\n *      RT_ERR_VLAN_PRIORITY    - Invalid 1p priority.\n *      RT_ERR_QOS_INT_PRIORITY - Invalid priority.\n * Note:\n *      Priority of 802.1Q assignment for internal asic priority, and it is used for queue usage and packet scheduling.\n */\nextern rtk_api_ret_t rtk_qos_1pPriRemap_set(rtk_pri_t dot1p_pri, rtk_pri_t int_pri);\n\n/* Function Name:\n *      rtk_qos_1pPriRemap_get\n * Description:\n *      Get 1Q priorities mapping to internal absolute priority.\n * Input:\n *      dot1p_pri - 802.1p priority value .\n * Output:\n *      pInt_pri - internal priority value.\n * Return:\n *      RT_ERR_OK               - OK\n *      RT_ERR_FAILED           - Failed\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_VLAN_PRIORITY    - Invalid priority.\n *      RT_ERR_QOS_INT_PRIORITY - Invalid priority.\n * Note:\n *      Priority of 802.1Q assigment for internal asic priority, and it is uesed for queue usage and packet scheduling.\n */\nextern rtk_api_ret_t rtk_qos_1pPriRemap_get(rtk_pri_t dot1p_pri, rtk_pri_t *pInt_pri);\n\n\n/* Function Name:\n *      rtk_qos_1pRemarkSrcSel_set\n * Description:\n *      Set remarking source of 802.1p remarking.\n * Input:\n *      type      - remarking source\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n *      RT_ERR_NOT_INIT         - The module is not initial\n *      RT_ERR_PORT_ID  - invalid port id\n *      RT_ERR_INPUT            - invalid input parameter\n\n * Note:\n *      The API can configure 802.1p remark functionality to map original 802.1p value or internal\n *      priority to TX DSCP value.\n */\nextern rtk_api_ret_t rtk_qos_1pRemarkSrcSel_set(rtk_qos_1pRmkSrc_t type);\n\n/* Function Name:\n *      rtk_qos_1pRemarkSrcSel_get\n * Description:\n *      Get remarking source of 802.1p remarking.\n * Input:\n *      none\n * Output:\n *      pType      - remarking source\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n *      RT_ERR_NOT_INIT         - The module is not initial\n *      RT_ERR_PORT_ID          - invalid port id\n *      RT_ERR_INPUT            - invalid input parameter\n *      RT_ERR_NULL_POINTER     - input parameter may be null pointer\n\n * Note:\n *      None\n */\nextern rtk_api_ret_t rtk_qos_1pRemarkSrcSel_get(rtk_qos_1pRmkSrc_t *pType);\n\n/* Function Name:\n *      rtk_qos_dscpPriRemap_set\n * Description:\n *      Map dscp value to internal priority.\n * Input:\n *      dscp    - Dscp value of receiving frame\n *      int_pri - internal priority value .\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - OK\n *      RT_ERR_FAILED           - Failed\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_INPUT            - Invalid input parameters.\n *      RT_ERR_QOS_DSCP_VALUE   - Invalid DSCP value.\n *      RT_ERR_QOS_INT_PRIORITY - Invalid priority.\n * Note:\n *      The Differentiated Service Code Point is a selector for router's per-hop behaviors. As a selector, there is no implication that a numerically\n *      greater DSCP implies a better network service. As can be seen, the DSCP totally overlaps the old precedence field of TOS. So if values of\n *      DSCP are carefully chosen then backward compatibility can be achieved.\n */\nextern rtk_api_ret_t rtk_qos_dscpPriRemap_set(rtk_dscp_t dscp, rtk_pri_t int_pri);\n\n/* Function Name:\n *      rtk_qos_dscpPriRemap_get\n * Description:\n *      Get dscp value to internal priority.\n * Input:\n *      dscp - Dscp value of receiving frame\n * Output:\n *      pInt_pri - internal priority value.\n * Return:\n *      RT_ERR_OK               - OK\n *      RT_ERR_FAILED           - Failed\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_QOS_DSCP_VALUE   - Invalid DSCP value.\n * Note:\n *      The Differentiated Service Code Point is a selector for router's per-hop behaviors. As a selector, there is no implication that a numerically\n *      greater DSCP implies a better network service. As can be seen, the DSCP totally overlaps the old precedence field of TOS. So if values of\n *      DSCP are carefully chosen then backward compatibility can be achieved.\n */\nextern rtk_api_ret_t rtk_qos_dscpPriRemap_get(rtk_dscp_t dscp, rtk_pri_t *pInt_pri);\n\n/* Function Name:\n *      rtk_qos_portPri_set\n * Description:\n *      Configure priority usage to each port.\n * Input:\n *      port - Port id.\n *      int_pri - internal priority value.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - OK\n *      RT_ERR_FAILED           - Failed\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_PORT_ID          - Invalid port number.\n *      RT_ERR_QOS_SEL_PORT_PRI - Invalid port priority.\n *      RT_ERR_QOS_INT_PRIORITY - Invalid priority.\n * Note:\n *      The API can set priority of port assignments for queue usage and packet scheduling.\n */\nextern rtk_api_ret_t rtk_qos_portPri_set(rtk_port_t port, rtk_pri_t int_pri) ;\n\n/* Function Name:\n *      rtk_qos_portPri_get\n * Description:\n *      Get priority usage to each port.\n * Input:\n *      port - Port id.\n * Output:\n *      pInt_pri - internal priority value.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number.\n *      RT_ERR_INPUT        - Invalid input parameters.\n * Note:\n *      The API can get priority of port assignments for queue usage and packet scheduling.\n */\nextern rtk_api_ret_t rtk_qos_portPri_get(rtk_port_t port, rtk_pri_t *pInt_pri) ;\n\n/* Function Name:\n *      rtk_qos_queueNum_set\n * Description:\n *      Set output queue number for each port.\n * Input:\n *      port    - Port id.\n *      index   - Mapping queue number (1~8)\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number.\n *      RT_ERR_QUEUE_NUM    - Invalid queue number.\n * Note:\n *      The API can set the output queue number of the specified port. The queue number is from 1 to 8.\n */\nextern rtk_api_ret_t rtk_qos_queueNum_set(rtk_port_t port, rtk_queue_num_t queue_num);\n\n/* Function Name:\n *      rtk_qos_queueNum_get\n * Description:\n *      Get output queue number.\n * Input:\n *      port - Port id.\n * Output:\n *      pQueue_num - Mapping queue number\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number.\n * Note:\n *      The API will return the output queue number of the specified port. The queue number is from 1 to 8.\n */\nextern rtk_api_ret_t rtk_qos_queueNum_get(rtk_port_t port, rtk_queue_num_t *pQueue_num);\n\n/* Function Name:\n *      rtk_qos_priMap_set\n * Description:\n *      Set output queue number for each port.\n * Input:\n *      queue_num   - Queue number usage.\n *      pPri2qid    - Priority mapping to queue ID.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - OK\n *      RT_ERR_FAILED           - Failed\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_INPUT            - Invalid input parameters.\n *      RT_ERR_QUEUE_NUM        - Invalid queue number.\n *      RT_ERR_QUEUE_ID         - Invalid queue id.\n *      RT_ERR_PORT_ID          - Invalid port number.\n *      RT_ERR_QOS_INT_PRIORITY - Invalid priority.\n * Note:\n *      ASIC supports priority mapping to queue with different queue number from 1 to 8.\n *      For different queue numbers usage, ASIC supports different internal available queue IDs.\n */\nextern rtk_api_ret_t rtk_qos_priMap_set(rtk_queue_num_t queue_num, rtk_qos_pri2queue_t *pPri2qid);\n\n\n/* Function Name:\n *      rtk_qos_priMap_get\n * Description:\n *      Get priority to queue ID mapping table parameters.\n * Input:\n *      queue_num - Queue number usage.\n * Output:\n *      pPri2qid - Priority mapping to queue ID.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n *      RT_ERR_QUEUE_NUM    - Invalid queue number.\n * Note:\n *      The API can return the mapping queue id of the specified priority and queue number.\n *      The queue number is from 1 to 8.\n */\nextern rtk_api_ret_t rtk_qos_priMap_get(rtk_queue_num_t queue_num, rtk_qos_pri2queue_t *pPri2qid);\n\n/* Function Name:\n *      rtk_qos_schedulingQueue_set\n * Description:\n *      Set weight and type of queues in dedicated port.\n * Input:\n *      port        - Port id.\n *      pQweights   - The array of weights for WRR/WFQ queue (0 for STRICT_PRIORITY queue).\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - OK\n *      RT_ERR_FAILED           - Failed\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_PORT_ID          - Invalid port number.\n *      RT_ERR_QOS_QUEUE_WEIGHT - Invalid queue weight.\n * Note:\n *      The API can set weight and type, strict priority or weight fair queue (WFQ) for\n *      dedicated port for using queues. If queue id is not included in queue usage,\n *      then its type and weight setting in dummy for setting. There are priorities\n *      as queue id in strict queues. It means strict queue id 5 carrying higher priority\n *      than strict queue id 4. The WFQ queue weight is from 1 to 128, and weight 0 is\n *      for strict priority queue type.\n */\nextern rtk_api_ret_t rtk_qos_schedulingQueue_set(rtk_port_t port, rtk_qos_queue_weights_t *pQweights);\n\n/* Function Name:\n *      rtk_qos_schedulingQueue_get\n * Description:\n *      Get weight and type of queues in dedicated port.\n * Input:\n *      port - Port id.\n * Output:\n *      pQweights - The array of weights for WRR/WFQ queue (0 for STRICT_PRIORITY queue).\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n *      RT_ERR_PORT_ID      - Invalid port number.\n * Note:\n *      The API can get weight and type, strict priority or weight fair queue (WFQ) for dedicated port for using queues.\n *      The WFQ queue weight is from 1 to 128, and weight 0 is for strict priority queue type.\n */\nextern rtk_api_ret_t rtk_qos_schedulingQueue_get(rtk_port_t port, rtk_qos_queue_weights_t *pQweights);\n\n/* Function Name:\n *      rtk_qos_1pRemarkEnable_set\n * Description:\n *      Set 1p Remarking state\n * Input:\n *      port        - Port id.\n *      enable      - State of per-port 1p Remarking\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number.\n *      RT_ERR_ENABLE       - Invalid enable parameter.\n * Note:\n *      The API can enable or disable 802.1p remarking ability for whole system.\n *      The status of 802.1p remark:\n *      - DISABLED\n *      - ENABLED\n */\nextern rtk_api_ret_t rtk_qos_1pRemarkEnable_set(rtk_port_t port, rtk_enable_t enable);\n\n/* Function Name:\n *      rtk_qos_1pRemarkEnable_get\n * Description:\n *      Get 802.1p remarking ability.\n * Input:\n *      port - Port id.\n * Output:\n *      pEnable - Status of 802.1p remark.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number.\n * Note:\n *      The API can get 802.1p remarking ability.\n *      The status of 802.1p remark:\n *      - DISABLED\n *      - ENABLED\n */\nextern rtk_api_ret_t rtk_qos_1pRemarkEnable_get(rtk_port_t port, rtk_enable_t *pEnable);\n\n/* Function Name:\n *      rtk_qos_1pRemark_set\n * Description:\n *      Set 802.1p remarking parameter.\n * Input:\n *      int_pri     - Internal priority value.\n *      dot1p_pri   - 802.1p priority value.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - OK\n *      RT_ERR_FAILED           - Failed\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_VLAN_PRIORITY    - Invalid 1p priority.\n *      RT_ERR_QOS_INT_PRIORITY - Invalid priority.\n * Note:\n *      The API can set 802.1p parameters source priority and new priority.\n */\nextern rtk_api_ret_t rtk_qos_1pRemark_set(rtk_pri_t int_pri, rtk_pri_t dot1p_pri);\n\n/* Function Name:\n *      rtk_qos_1pRemark_get\n * Description:\n *      Get 802.1p remarking parameter.\n * Input:\n *      int_pri - Internal priority value.\n * Output:\n *      pDot1p_pri - 802.1p priority value.\n * Return:\n *      RT_ERR_OK               - OK\n *      RT_ERR_FAILED           - Failed\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_QOS_INT_PRIORITY - Invalid priority.\n * Note:\n *      The API can get 802.1p remarking parameters. It would return new priority of ingress priority.\n */\nextern rtk_api_ret_t rtk_qos_1pRemark_get(rtk_pri_t int_pri, rtk_pri_t *pDot1p_pri);\n\n/* Function Name:\n *      rtk_qos_dscpRemarkEnable_set\n * Description:\n *      Set DSCP remarking ability.\n * Input:\n *      port    - Port id.\n *      enable  - status of DSCP remark.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - OK\n *      RT_ERR_FAILED           - Failed\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_PORT_ID          - Invalid port number.\n *      RT_ERR_QOS_INT_PRIORITY - Invalid priority.\n *      RT_ERR_ENABLE           - Invalid enable parameter.\n * Note:\n *      The API can enable or disable DSCP remarking ability for whole system.\n *      The status of DSCP remark:\n *      - DISABLED\n *      - ENABLED\n */\nextern rtk_api_ret_t rtk_qos_dscpRemarkEnable_set(rtk_port_t port, rtk_enable_t enable);\n\n/* Function Name:\n *      rtk_qos_dscpRemarkEnable_get\n * Description:\n *      Get DSCP remarking ability.\n * Input:\n *      port - Port id.\n * Output:\n *      pEnable - status of DSCP remarking.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number.\n * Note:\n *      The API can get DSCP remarking ability.\n *      The status of DSCP remark:\n *      - DISABLED\n *      - ENABLED\n */\nextern rtk_api_ret_t rtk_qos_dscpRemarkEnable_get(rtk_port_t port, rtk_enable_t *pEnable);\n\n/* Function Name:\n *      rtk_qos_dscpRemark_set\n * Description:\n *      Set DSCP remarking parameter.\n * Input:\n *      int_pri - Internal priority value.\n *      dscp    - DSCP value.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - OK\n *      RT_ERR_FAILED           - Failed\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_QOS_INT_PRIORITY - Invalid priority.\n *      RT_ERR_QOS_DSCP_VALUE   - Invalid DSCP value.\n * Note:\n *      The API can set DSCP value and mapping priority.\n */\nextern rtk_api_ret_t rtk_qos_dscpRemark_set(rtk_pri_t int_pri, rtk_dscp_t dscp);\n\n/* Function Name:\n *      rtk_qos_dscpRemark_get\n * Description:\n *      Get DSCP remarking parameter.\n * Input:\n *      int_pri - Internal priority value.\n * Output:\n *      Dscp - DSCP value.\n * Return:\n *      RT_ERR_OK               - OK\n *      RT_ERR_FAILED           - Failed\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_QOS_INT_PRIORITY - Invalid priority.\n * Note:\n *      The API can get DSCP parameters. It would return DSCP value for mapping priority.\n */\nextern rtk_api_ret_t rtk_qos_dscpRemark_get(rtk_pri_t int_pri, rtk_dscp_t *pDscp);\n\n/* Function Name:\n *      rtk_qos_dscpRemarkSrcSel_set\n * Description:\n *      Set remarking source of DSCP remarking.\n * Input:\n *      type      - remarking source\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n *      RT_ERR_NOT_INIT         - The module is not initial\n *      RT_ERR_PORT_ID  - invalid port id\n *      RT_ERR_INPUT            - invalid input parameter\n\n * Note:\n *      The API can configure DSCP remark functionality to map original DSCP value or internal\n *      priority to TX DSCP value.\n */\nextern rtk_api_ret_t rtk_qos_dscpRemarkSrcSel_set(rtk_qos_dscpRmkSrc_t type);\n\n\n/* Function Name:\n *      rtk_qos_dcpRemarkSrcSel_get\n * Description:\n *      Get remarking source of DSCP remarking.\n * Input:\n *      none\n * Output:\n *      pType      - remarking source\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n *      RT_ERR_NOT_INIT         - The module is not initial\n *      RT_ERR_PORT_ID          - invalid port id\n *      RT_ERR_INPUT            - invalid input parameter\n *      RT_ERR_NULL_POINTER     - input parameter may be null pointer\n\n * Note:\n *      None\n */\nextern rtk_api_ret_t rtk_qos_dscpRemarkSrcSel_get(rtk_qos_dscpRmkSrc_t *pType);\n\n\n/* Function Name:\n *      rtk_qos_dscpRemark2Dscp_set\n * Description:\n *      Set DSCP to remarked DSCP mapping.\n * Input:\n *      dscp    - DSCP value\n *      rmkDscp - remarked DSCP value\n * Output:\n *      None.\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n *      RT_ERR_QOS_DSCP_VALUE   - Invalid dscp value\n * Note:\n *      dscp parameter can be DSCP value or internal priority according to configuration of API\n *      dal_apollomp_qos_dscpRemarkSrcSel_set(), because DSCP remark functionality can map original DSCP\n *      value or internal priority to TX DSCP value.\n */\nextern rtk_api_ret_t rtk_qos_dscpRemark2Dscp_set(rtk_dscp_t dscp, rtk_dscp_t rmkDscp);\n\n/* Function Name:\n *      rtk_qos_dscpRemark2Dscp_get\n * Description:\n *      Get DSCP to remarked DSCP mapping.\n * Input:\n *      dscp    - DSCP value\n * Output:\n *      pDscp   - remarked DSCP value\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n *      RT_ERR_QOS_DSCP_VALUE   - Invalid dscp value\n *      RT_ERR_NULL_POINTER     - NULL pointer\n * Note:\n *      None.\n */\nextern rtk_api_ret_t rtk_qos_dscpRemark2Dscp_get(rtk_dscp_t dscp, rtk_dscp_t *pDscp);\n\n/* Function Name:\n *      rtk_qos_portPriSelIndex_set\n * Description:\n *      Configure priority decision index to each port.\n * Input:\n *      port - Port id.\n *      index - priority decision index.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - OK\n *      RT_ERR_FAILED           - Failed\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_PORT_ID          - Invalid port number.\n *      RT_ERR_ENTRY_INDEX - Invalid entry index.\n * Note:\n *      The API can set priority of port assignments for queue usage and packet scheduling.\n */\nextern rtk_api_ret_t rtk_qos_portPriSelIndex_set(rtk_port_t port, rtk_qos_priDecTbl_t index);\n\n/* Function Name:\n *      rtk_qos_portPriSelIndex_get\n * Description:\n *      Get priority decision index from each port.\n * Input:\n *      port - Port id.\n * Output:\n *      pIndex - priority decision index.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number.\n * Note:\n *      The API can get priority of port assignments for queue usage and packet scheduling.\n */\nextern rtk_api_ret_t rtk_qos_portPriSelIndex_get(rtk_port_t port, rtk_qos_priDecTbl_t *pIndex);\n\n#endif /* __RTK_API_QOS_H__ */\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rate.h",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * Purpose : RTL8367/RTL8367C switch high-level API\n *\n * Feature : The file includes rate module high-layer API defination\n *\n */\n\n#ifndef __RTK_API_RATE_H__\n#define __RTK_API_RATE_H__\n\n/*\n * Include Files\n */\n//#include <rtk_types.h>\n\n/*\n * Data Type Declaration\n */\n#define RTK_MAX_METER_ID            (rtk_switch_maxMeterId_get())\n#define RTK_METER_NUM               (RTK_MAX_METER_ID + 1)\n\ntypedef enum rtk_meter_type_e{\n    METER_TYPE_KBPS = 0,    /* Kbps */\n    METER_TYPE_PPS,         /* Packet per second */\n    METER_TYPE_END\n}rtk_meter_type_t;\n\n\n/*\n * Function Declaration\n */\n\n /* Rate */\n/* Function Name:\n *      rtk_rate_shareMeter_set\n * Description:\n *      Set meter configuration\n * Input:\n *      index       - shared meter index\n *      type        - shared meter type\n *      rate        - rate of share meter\n *      ifg_include - include IFG or not, ENABLE:include DISABLE:exclude\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - OK\n *      RT_ERR_FAILED           - Failed\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_FILTER_METER_ID  - Invalid meter\n *      RT_ERR_RATE             - Invalid rate\n *      RT_ERR_INPUT            - Invalid input parameters\n * Note:\n *      The API can set shared meter rate and ifg include for each meter.\n *      The rate unit is 1 kbps and the range is from 8k to 1048568k if type is METER_TYPE_KBPS and\n *      the granularity of rate is 8 kbps.\n *      The rate unit is packets per second and the range is 1 ~ 0x1FFF if type is METER_TYPE_PPS.\n *      The ifg_include parameter is used\n *      for rate calculation with/without inter-frame-gap and preamble.\n */\nrtk_api_ret_t rtk_rate_shareMeter_set(rtk_meter_id_t index, rtk_meter_type_t type, rtk_rate_t rate, rtk_enable_t ifg_include);\n\n/* Function Name:\n *      rtk_rate_shareMeter_get\n * Description:\n *      Get meter configuration\n * Input:\n *      index        - shared meter index\n * Output:\n *      pType        - Meter Type\n *      pRate        - pointer of rate of share meter\n *      pIfg_include - include IFG or not, ENABLE:include DISABLE:exclude\n * Return:\n *      RT_ERR_OK               - OK\n *      RT_ERR_FAILED           - Failed\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_FILTER_METER_ID  - Invalid meter\n * Note:\n *\n */\nrtk_api_ret_t rtk_rate_shareMeter_get(rtk_meter_id_t index, rtk_meter_type_t *pType, rtk_rate_t *pRate, rtk_enable_t *pIfg_include);\n\n/* Function Name:\n *      rtk_rate_shareMeterBucket_set\n * Description:\n *      Set meter Bucket Size\n * Input:\n *      index        - shared meter index\n *      bucket_size  - Bucket Size\n * Output:\n *      None.\n * Return:\n *      RT_ERR_OK               - OK\n *      RT_ERR_FAILED           - Failed\n *      RT_ERR_INPUT            - Error Input\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_FILTER_METER_ID  - Invalid meter\n * Note:\n *      The API can set shared meter bucket size.\n */\nextern rtk_api_ret_t rtk_rate_shareMeterBucket_set(rtk_meter_id_t index, rtk_uint32 bucket_size);\n\n/* Function Name:\n *      rtk_rate_shareMeterBucket_get\n * Description:\n *      Get meter Bucket Size\n * Input:\n *      index        - shared meter index\n * Output:\n *      pBucket_size - Bucket Size\n * Return:\n *      RT_ERR_OK               - OK\n *      RT_ERR_FAILED           - Failed\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_FILTER_METER_ID  - Invalid meter\n * Note:\n *      The API can get shared meter bucket size.\n */\nextern rtk_api_ret_t rtk_rate_shareMeterBucket_get(rtk_meter_id_t index, rtk_uint32 *pBucket_size);\n\n/* Function Name:\n *      rtk_rate_igrBandwidthCtrlRate_set\n * Description:\n *      Set port ingress bandwidth control\n * Input:\n *      port        - Port id\n *      rate        - Rate of share meter\n *      ifg_include - include IFG or not, ENABLE:include DISABLE:exclude\n *      fc_enable   - enable flow control or not, ENABLE:use flow control DISABLE:drop\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number.\n *      RT_ERR_ENABLE       - Invalid IFG parameter.\n *      RT_ERR_INBW_RATE    - Invalid ingress rate parameter.\n * Note:\n *      The rate unit is 1 kbps and the range is from 8k to 1048568k. The granularity of rate is 8 kbps.\n *      The ifg_include parameter is used for rate calculation with/without inter-frame-gap and preamble.\n */\nextern rtk_api_ret_t rtk_rate_igrBandwidthCtrlRate_set( rtk_port_t port, rtk_rate_t rate,  rtk_enable_t ifg_include, rtk_enable_t fc_enable);\n\n/* Function Name:\n *      rtk_rate_igrBandwidthCtrlRate_get\n * Description:\n *      Get port ingress bandwidth control\n * Input:\n *      port - Port id\n * Output:\n *      pRate           - Rate of share meter\n *      pIfg_include    - Rate's calculation including IFG, ENABLE:include DISABLE:exclude\n *      pFc_enable      - enable flow control or not, ENABLE:use flow control DISABLE:drop\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number.\n *      RT_ERR_INPUT        - Invalid input parameters.\n * Note:\n *     The rate unit is 1 kbps and the range is from 8k to 1048568k. The granularity of rate is 8 kbps.\n *     The ifg_include parameter is used for rate calculation with/without inter-frame-gap and preamble.\n */\nextern rtk_api_ret_t rtk_rate_igrBandwidthCtrlRate_get(rtk_port_t port, rtk_rate_t *pRate, rtk_enable_t *pIfg_include, rtk_enable_t *pFc_enable);\n\n/* Function Name:\n *      rtk_rate_egrBandwidthCtrlRate_set\n * Description:\n *      Set port egress bandwidth control\n * Input:\n *      port        - Port id\n *      rate        - Rate of egress bandwidth\n *      ifg_include - include IFG or not, ENABLE:include DISABLE:exclude\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number.\n *      RT_ERR_INPUT        - Invalid input parameters.\n *      RT_ERR_QOS_EBW_RATE - Invalid egress bandwidth/rate\n * Note:\n *     The rate unit is 1 kbps and the range is from 8k to 1048568k. The granularity of rate is 8 kbps.\n *     The ifg_include parameter is used for rate calculation with/without inter-frame-gap and preamble.\n */\nextern rtk_api_ret_t rtk_rate_egrBandwidthCtrlRate_set(rtk_port_t port, rtk_rate_t rate,  rtk_enable_t ifg_includ);\n\n/* Function Name:\n *      rtk_rate_egrBandwidthCtrlRate_get\n * Description:\n *      Get port egress bandwidth control\n * Input:\n *      port - Port id\n * Output:\n *      pRate           - Rate of egress bandwidth\n *      pIfg_include    - Rate's calculation including IFG, ENABLE:include DISABLE:exclude\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number.\n *      RT_ERR_INPUT        - Invalid input parameters.\n * Note:\n *     The rate unit is 1 kbps and the range is from 8k to 1048568k. The granularity of rate is 8 kbps.\n *     The ifg_include parameter is used for rate calculation with/without inter-frame-gap and preamble.\n */\nextern rtk_api_ret_t rtk_rate_egrBandwidthCtrlRate_get(rtk_port_t port, rtk_rate_t *pRate, rtk_enable_t *pIfg_include);\n\n/* Function Name:\n *      rtk_rate_egrQueueBwCtrlEnable_set\n * Description:\n *      Set enable status of egress bandwidth control on specified queue.\n * Input:\n *      port   - port id\n *      queue  - queue id\n *      enable - enable status of egress queue bandwidth control\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n *      RT_ERR_PORT_ID          - invalid port id\n *      RT_ERR_QUEUE_ID         - invalid queue id\n *      RT_ERR_INPUT            - invalid input parameter\n * Note:\n *      None\n */\nextern rtk_api_ret_t rtk_rate_egrQueueBwCtrlEnable_set(rtk_port_t port, rtk_qid_t queue, rtk_enable_t enable);\n\n/* Function Name:\n *      rtk_rate_egrQueueBwCtrlRate_get\n * Description:\n *      Get rate of egress bandwidth control on specified queue.\n * Input:\n *      port  - port id\n *      queue - queue id\n *      pIndex - shared meter index\n * Output:\n *      pRate - pointer to rate of egress queue bandwidth control\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n *      RT_ERR_PORT_ID          - invalid port id\n *      RT_ERR_QUEUE_ID         - invalid queue id\n *      RT_ERR_FILTER_METER_ID  - Invalid meter id\n * Note:\n *    None.\n */\nextern rtk_api_ret_t rtk_rate_egrQueueBwCtrlEnable_get(rtk_port_t port, rtk_qid_t queue, rtk_enable_t *pEnable);\n\n/* Function Name:\n *      rtk_rate_egrQueueBwCtrlRate_set\n * Description:\n *      Set rate of egress bandwidth control on specified queue.\n * Input:\n *      port  - port id\n *      queue - queue id\n *      index - shared meter index\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n *      RT_ERR_PORT_ID          - invalid port id\n *      RT_ERR_QUEUE_ID         - invalid queue id\n *      RT_ERR_FILTER_METER_ID  - Invalid meter id\n * Note:\n *    The actual rate control is set in shared meters.\n *    The unit of granularity is 8Kbps.\n */\nextern rtk_api_ret_t rtk_rate_egrQueueBwCtrlRate_set(rtk_port_t port, rtk_qid_t queue, rtk_meter_id_t index);\n\n/* Function Name:\n *      rtk_rate_egrQueueBwCtrlRate_get\n * Description:\n *      Get rate of egress bandwidth control on specified queue.\n * Input:\n *      port  - port id\n *      queue - queue id\n *      pIndex - shared meter index\n * Output:\n *      pRate - pointer to rate of egress queue bandwidth control\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n *      RT_ERR_PORT_ID          - invalid port id\n *      RT_ERR_QUEUE_ID         - invalid queue id\n *      RT_ERR_FILTER_METER_ID  - Invalid meter id\n * Note:\n *    The actual rate control is set in shared meters.\n *    The unit of granularity is 8Kbps.\n */\nextern rtk_api_ret_t rtk_rate_egrQueueBwCtrlRate_get(rtk_port_t port, rtk_qid_t queue, rtk_meter_id_t *pIndex);\n\n#endif /* __RTK_API_RATE_H__ */\n\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rldp.h",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * $Revision: 76306 $\n * $Date: 2017-03-08 15:13:58 +0800 (gT, 08 T 2017) $\n *\n * Purpose : Declaration of RLDP and RLPP API\n *\n * Feature : The file have include the following module and sub-modules\n *           1) RLDP and RLPP configuration and status\n *\n */\n\n\n#ifndef __RTK_RLDP_H__\n#define __RTK_RLDP_H__\n\n\n/*\n * Include Files\n */\n\n\n/*\n * Symbol Definition\n */\ntypedef enum rtk_rldp_trigger_e\n{\n    RTK_RLDP_TRIGGER_SAMOVING = 0,\n    RTK_RLDP_TRIGGER_PERIOD,\n    RTK_RLDP_TRIGGER_END\n} rtk_rldp_trigger_t;\n\ntypedef enum rtk_rldp_cmpType_e\n{\n    RTK_RLDP_CMPTYPE_MAGIC = 0,     /* Compare the RLDP with magic only */\n    RTK_RLDP_CMPTYPE_MAGIC_ID,      /* Compare the RLDP with both magic + ID */\n    RTK_RLDP_CMPTYPE_END\n} rtk_rldp_cmpType_t;\n\ntypedef enum rtk_rldp_loopStatus_e\n{\n    RTK_RLDP_LOOPSTS_NONE = 0,\n    RTK_RLDP_LOOPSTS_LOOPING,\n    RTK_RLDP_LOOPSTS_END\n} rtk_rldp_loopStatus_t;\n\ntypedef enum rtk_rlpp_trapType_e\n{\n    RTK_RLPP_TRAPTYPE_NONE = 0,\n    RTK_RLPP_TRAPTYPE_CPU,\n    RTK_RLPP_TRAPTYPE_END\n} rtk_rlpp_trapType_t;\n\ntypedef struct rtk_rldp_config_s\n{\n    rtk_enable_t        rldp_enable;\n    rtk_rldp_trigger_t trigger_mode;\n    rtk_mac_t           magic;\n    rtk_rldp_cmpType_t  compare_type;\n    rtk_uint32              interval_check; /* Checking interval for check state */\n    rtk_uint32              num_check;      /* Checking number for check state */\n    rtk_uint32              interval_loop;  /* Checking interval for loop state */\n    rtk_uint32              num_loop;       /* Checking number for loop state */\n} rtk_rldp_config_t;\n\ntypedef struct rtk_rldp_portConfig_s\n{\n    rtk_enable_t        tx_enable;\n} rtk_rldp_portConfig_t;\n\ntypedef struct rtk_rldp_status_s\n{\n    rtk_mac_t           id;\n} rtk_rldp_status_t;\n\ntypedef struct rtk_rldp_portStatus_s\n{\n    rtk_rldp_loopStatus_t   loop_status;\n    rtk_rldp_loopStatus_t   loop_enter;\n    rtk_rldp_loopStatus_t   loop_leave;\n} rtk_rldp_portStatus_t;\n\n/*\n * Data Declaration\n */\n\n\n/*\n * Macro Declaration\n */\n\n#define RTK_RLDP_INTERVAL_MAX  0xffff\n#define RTK_RLDP_NUM_MAX       0xff\n\n\n/*\n * Function Declaration\n */\n\n/* Module Name : RLDP */\n\n\n/* Function Name:\n *      rtk_rldp_config_set\n * Description:\n *      Set RLDP module configuration\n * Input:\n *      pConfig - configuration structure of RLDP\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n *      RT_ERR_INPUT\n *      RT_ERR_NULL_POINTER\n * Note:\n *      None\n */\nextern rtk_api_ret_t rtk_rldp_config_set(rtk_rldp_config_t *pConfig);\n\n\n/* Function Name:\n *      rtk_rldp_config_get\n * Description:\n *      Get RLDP module configuration\n * Input:\n *      None\n * Output:\n *      pConfig - configuration structure of RLDP\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n *      RT_ERR_INPUT\n *      RT_ERR_NULL_POINTER\n * Note:\n *      None\n */\nextern rtk_api_ret_t rtk_rldp_config_get(rtk_rldp_config_t *pConfig);\n\n\n/* Function Name:\n *      rtk_rldp_portConfig_set\n * Description:\n *      Set per port RLDP module configuration\n * Input:\n *      port   - port number to be configured\n *      pPortConfig - per port configuration structure of RLDP\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n *      RT_ERR_INPUT\n *      RT_ERR_NULL_POINTER\n * Note:\n *      None\n */\nextern rtk_api_ret_t rtk_rldp_portConfig_set(rtk_port_t port, rtk_rldp_portConfig_t *pPortConfig);\n\n\n/* Function Name:\n *      rtk_rldp_portConfig_get\n * Description:\n *      Get per port RLDP module configuration\n * Input:\n *      port    - port number to be get\n * Output:\n *      pPortConfig - per port configuration structure of RLDP\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n *      RT_ERR_INPUT\n *      RT_ERR_NULL_POINTER\n * Note:\n *      None\n */\nextern rtk_api_ret_t rtk_rldp_portConfig_get(rtk_port_t port, rtk_rldp_portConfig_t *pPortConfig);\n\n\n/* Function Name:\n *      rtk_rldp_status_get\n * Description:\n *      Get RLDP module status\n * Input:\n *      None\n * Output:\n *      pStatus - status structure of RLDP\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n *      RT_ERR_NULL_POINTER\n * Note:\n *      None\n */\nextern rtk_api_ret_t rtk_rldp_status_get(rtk_rldp_status_t *pStatus);\n\n\n/* Function Name:\n *      rtk_rldp_portStatus_get\n * Description:\n *      Get RLDP module status\n * Input:\n *      port    - port number to be get\n * Output:\n *      pPortStatus - per port status structure of RLDP\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n *      RT_ERR_INPUT\n *      RT_ERR_NULL_POINTER\n * Note:\n *      None\n */\nextern rtk_api_ret_t rtk_rldp_portStatus_get(rtk_port_t port, rtk_rldp_portStatus_t *pPortStatus);\n\n\n/* Function Name:\n *      rtk_rldp_portStatus_clear\n * Description:\n *      Clear RLDP module status\n * Input:\n *      port    - port number to be clear\n *      pPortStatus - per port status structure of RLDP\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n *      RT_ERR_INPUT\n *      RT_ERR_NULL_POINTER\n * Note:\n *      Clear operation effect loop_enter and loop_leave only, other field in\n *      the structure are don't care\n */\nextern rtk_api_ret_t rtk_rldp_portStatus_set(rtk_port_t port, rtk_rldp_portStatus_t *pPortStatus);\n\n\n/* Function Name:\n *      rtk_rldp_portLoopPair_get\n * Description:\n *      Get RLDP port loop pairs\n * Input:\n *      port    - port number to be get\n * Output:\n *      pPortmask - per port related loop ports\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n *      RT_ERR_INPUT\n *      RT_ERR_NULL_POINTER\n * Note:\n *      None\n */\nextern rtk_api_ret_t rtk_rldp_portLoopPair_get(rtk_port_t port, rtk_portmask_t *pPortmask);\n\n#endif /* __RTK_RLDP_H__ */\n\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtk_error.h",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * $Revision: 76306 $\n * $Date: 2017-03-08 15:13:58 +0800 (週三, 08 三月 2017) $\n *\n * Purpose : Definition the error number in the SDK.\n * Feature : error definition\n *\n */\n\n#ifndef __COMMON_RT_ERROR_H__\n#define __COMMON_RT_ERROR_H__\n\n/*\n * Include Files\n */\n\n/*\n * Data Type Declaration\n */\ntypedef enum rt_error_code_e\n{\n    RT_ERR_FAILED = -1,                             /* General Error                                                                    */\n\n    /* 0x0000xxxx for common error code */\n    RT_ERR_OK = 0,                                  /* 0x00000000, OK                                                                   */\n    RT_ERR_INPUT,                                   /* 0x00000001, invalid input parameter                                              */\n    RT_ERR_UNIT_ID,                                 /* 0x00000002, invalid unit id                                                      */\n    RT_ERR_PORT_ID,                                 /* 0x00000003, invalid port id                                                      */\n    RT_ERR_PORT_MASK,                               /* 0x00000004, invalid port mask                                                    */\n    RT_ERR_PORT_LINKDOWN,                           /* 0x00000005, link down port status                                                */\n    RT_ERR_ENTRY_INDEX,                             /* 0x00000006, invalid entry index                                                  */\n    RT_ERR_NULL_POINTER,                            /* 0x00000007, input parameter is null pointer                                      */\n    RT_ERR_QUEUE_ID,                                /* 0x00000008, invalid queue id                                                     */\n    RT_ERR_QUEUE_NUM,                               /* 0x00000009, invalid queue number                                                 */\n    RT_ERR_BUSYWAIT_TIMEOUT,                        /* 0x0000000a, busy watting time out                                                */\n    RT_ERR_MAC,                                     /* 0x0000000b, invalid mac address                                                  */\n    RT_ERR_OUT_OF_RANGE,                            /* 0x0000000c, input parameter out of range                                         */\n    RT_ERR_CHIP_NOT_SUPPORTED,                      /* 0x0000000d, functions not supported by this chip model                           */\n    RT_ERR_SMI,                                     /* 0x0000000e, SMI error                                                            */\n    RT_ERR_NOT_INIT,                                /* 0x0000000f, The module is not initial                                            */\n    RT_ERR_CHIP_NOT_FOUND,                          /* 0x00000010, The chip can not found                                               */\n    RT_ERR_NOT_ALLOWED,                             /* 0x00000011, actions not allowed by the function                                  */\n    RT_ERR_DRIVER_NOT_FOUND,                        /* 0x00000012, The driver can not found                                             */\n    RT_ERR_SEM_LOCK_FAILED,                         /* 0x00000013, Failed to lock semaphore                                             */\n    RT_ERR_SEM_UNLOCK_FAILED,                       /* 0x00000014, Failed to unlock semaphore                                           */\n    RT_ERR_ENABLE,                                  /* 0x00000015, invalid enable parameter                                             */\n    RT_ERR_TBL_FULL,                                /* 0x00000016, input table full                                                     */\n\n    /* 0x0001xxxx for vlan */\n    RT_ERR_VLAN_VID = 0x00010000,                   /* 0x00010000, invalid vid                                                          */\n    RT_ERR_VLAN_PRIORITY,                           /* 0x00010001, invalid 1p priority                                                  */\n    RT_ERR_VLAN_EMPTY_ENTRY,                        /* 0x00010002, emtpy entry of vlan table                                            */\n    RT_ERR_VLAN_ACCEPT_FRAME_TYPE,                  /* 0x00010003, invalid accept frame type                                            */\n    RT_ERR_VLAN_EXIST,                              /* 0x00010004, vlan is exist                                                        */\n    RT_ERR_VLAN_ENTRY_NOT_FOUND,                    /* 0x00010005, specified vlan entry not found                                       */\n    RT_ERR_VLAN_PORT_MBR_EXIST,                     /* 0x00010006, member port exist in the specified vlan                              */\n    RT_ERR_VLAN_PROTO_AND_PORT,                     /* 0x00010008, invalid protocol and port based vlan                              */\n\n    /* 0x0002xxxx for svlan */\n    RT_ERR_SVLAN_ENTRY_INDEX = 0x00020000,          /* 0x00020000, invalid svid entry no                                                */\n    RT_ERR_SVLAN_ETHER_TYPE,                        /* 0x00020001, invalid SVLAN ether type                                             */\n    RT_ERR_SVLAN_TABLE_FULL,                        /* 0x00020002, no empty entry in SVLAN table                                        */\n    RT_ERR_SVLAN_ENTRY_NOT_FOUND,                   /* 0x00020003, specified svlan entry not found                                      */\n    RT_ERR_SVLAN_EXIST,                             /* 0x00020004, SVLAN entry is exist                                                 */\n    RT_ERR_SVLAN_VID,                               /* 0x00020005, invalid svid                                                         */\n\n    /* 0x0003xxxx for MSTP */\n    RT_ERR_MSTI = 0x00030000,                       /* 0x00030000, invalid msti                                                         */\n    RT_ERR_MSTP_STATE,                              /* 0x00030001, invalid spanning tree status                                         */\n    RT_ERR_MSTI_EXIST,                              /* 0x00030002, MSTI exist                                                           */\n    RT_ERR_MSTI_NOT_EXIST,                          /* 0x00030003, MSTI not exist                                                       */\n\n    /* 0x0004xxxx for BUCKET */\n    RT_ERR_TIMESLOT = 0x00040000,                   /* 0x00040000, invalid time slot                                                    */\n    RT_ERR_TOKEN,                                   /* 0x00040001, invalid token amount                                                 */\n    RT_ERR_RATE,                                    /* 0x00040002, invalid rate                                                         */\n    RT_ERR_TICK,                                    /* 0x00040003, invalid tick                                                 */\n\n    /* 0x0005xxxx for RMA */\n    RT_ERR_RMA_ADDR = 0x00050000,                   /* 0x00050000, invalid rma mac address                                              */\n    RT_ERR_RMA_ACTION,                              /* 0x00050001, invalid rma action                                                   */\n\n    /* 0x0006xxxx for L2 */\n    RT_ERR_L2_HASH_KEY = 0x00060000,                /* 0x00060000, invalid L2 Hash key                                                  */\n    RT_ERR_L2_HASH_INDEX,                           /* 0x00060001, invalid L2 Hash index                                                */\n    RT_ERR_L2_CAM_INDEX,                            /* 0x00060002, invalid L2 CAM index                                                 */\n    RT_ERR_L2_ENRTYSEL,                             /* 0x00060003, invalid EntrySel                                                     */\n    RT_ERR_L2_INDEXTABLE_INDEX,                     /* 0x00060004, invalid L2 index table(=portMask table) index                        */\n    RT_ERR_LIMITED_L2ENTRY_NUM,                     /* 0x00060005, invalid limited L2 entry number                                      */\n    RT_ERR_L2_AGGREG_PORT,                          /* 0x00060006, this aggregated port is not the lowest physical\n                                                                   port of its aggregation group                                        */\n    RT_ERR_L2_FID,                                  /* 0x00060007, invalid fid                                                          */\n    RT_ERR_L2_VID,                                 /* 0x00060008, invalid cvid                                                         */\n    RT_ERR_L2_NO_EMPTY_ENTRY,                       /* 0x00060009, no empty entry in L2 table                                           */\n    RT_ERR_L2_ENTRY_NOTFOUND,                       /* 0x0006000a, specified entry not found                                            */\n    RT_ERR_L2_INDEXTBL_FULL,                        /* 0x0006000b, the L2 index table is full                                           */\n    RT_ERR_L2_INVALID_FLOWTYPE,                     /* 0x0006000c, invalid L2 flow type                                                 */\n    RT_ERR_L2_L2UNI_PARAM,                          /* 0x0006000d, invalid L2 unicast parameter                                         */\n    RT_ERR_L2_L2MULTI_PARAM,                        /* 0x0006000e, invalid L2 multicast parameter                                       */\n    RT_ERR_L2_IPMULTI_PARAM,                        /* 0x0006000f, invalid L2 ip multicast parameter                                    */\n    RT_ERR_L2_PARTIAL_HASH_KEY,                     /* 0x00060010, invalid L2 partial Hash key                                          */\n    RT_ERR_L2_EMPTY_ENTRY,                          /* 0x00060011, the entry is empty(invalid)                                          */\n    RT_ERR_L2_FLUSH_TYPE,                           /* 0x00060012, the flush type is invalid                                            */\n    RT_ERR_L2_NO_CPU_PORT,                          /* 0x00060013, CPU port not exist                                                   */\n\n    /* 0x0007xxxx for FILTER (PIE) */\n    RT_ERR_FILTER_BLOCKNUM = 0x00070000,            /* 0x00070000, invalid block number                                                 */\n    RT_ERR_FILTER_ENTRYIDX,                         /* 0x00070001, invalid entry index                                                  */\n    RT_ERR_FILTER_CUTLINE,                          /* 0x00070002, invalid cutline value                                                */\n    RT_ERR_FILTER_FLOWTBLBLOCK,                     /* 0x00070003, block belongs to flow table                                          */\n    RT_ERR_FILTER_INACLBLOCK,                       /* 0x00070004, block belongs to ingress ACL                                         */\n    RT_ERR_FILTER_ACTION,                           /* 0x00070005, action doesn't consist to entry type                                 */\n    RT_ERR_FILTER_INACL_RULENUM,                    /* 0x00070006, invalid ACL rulenum                                                  */\n    RT_ERR_FILTER_INACL_TYPE,                       /* 0x00070007, entry type isn't an ingress ACL rule                                 */\n    RT_ERR_FILTER_INACL_EXIST,                      /* 0x00070008, ACL entry is already exit                                            */\n    RT_ERR_FILTER_INACL_EMPTY,                      /* 0x00070009, ACL entry is empty                                                   */\n    RT_ERR_FILTER_FLOWTBL_TYPE,                     /* 0x0007000a, entry type isn't an flow table rule                                  */\n    RT_ERR_FILTER_FLOWTBL_RULENUM,                  /* 0x0007000b, invalid flow table rulenum                                           */\n    RT_ERR_FILTER_FLOWTBL_EMPTY,                    /* 0x0007000c, flow table entry is empty                                            */\n    RT_ERR_FILTER_FLOWTBL_EXIST,                    /* 0x0007000d, flow table entry is already exist                                    */\n    RT_ERR_FILTER_METER_ID,                         /* 0x0007000e, invalid metering id                                                  */\n    RT_ERR_FILTER_LOG_ID,                           /* 0x0007000f, invalid log id                                                       */\n    RT_ERR_FILTER_INACL_NONE_BEGIN_IDX,             /* 0x00070010, entry index is not starting index of a group of rules                */\n    RT_ERR_FILTER_INACL_ACT_NOT_SUPPORT,            /* 0x00070011, action not support                                                    */\n    RT_ERR_FILTER_INACL_RULE_NOT_SUPPORT,           /* 0x00070012, rule not support                                                   */\n\n    /* 0x0008xxxx for ACL Rate Limit */\n    RT_ERR_ACLRL_HTHR = 0x00080000,                 /* 0x00080000, invalid high threshold                                               */\n    RT_ERR_ACLRL_TIMESLOT,                          /* 0x00080001, invalid time slot                                                    */\n    RT_ERR_ACLRL_TOKEN,                             /* 0x00080002, invalid token amount                                                 */\n    RT_ERR_ACLRL_RATE,                              /* 0x00080003, invalid rate                                                         */\n\n    /* 0x0009xxxx for Link aggregation */\n    RT_ERR_LA_CPUPORT = 0x00090000,                 /* 0x00090000, CPU port can not be aggregated port                                  */\n    RT_ERR_LA_TRUNK_ID,                             /* 0x00090001, invalid trunk id                                                     */\n    RT_ERR_LA_PORTMASK,                             /* 0x00090002, invalid port mask                                                    */\n    RT_ERR_LA_HASHMASK,                             /* 0x00090003, invalid hash mask                                                    */\n    RT_ERR_LA_DUMB,                                 /* 0x00090004, this API should be used in 802.1ad dumb mode                         */\n    RT_ERR_LA_PORTNUM_DUMB,                         /* 0x00090005, it can only aggregate at most four ports when 802.1ad dumb mode      */\n    RT_ERR_LA_PORTNUM_NORMAL,                       /* 0x00090006, it can only aggregate at most eight ports when 802.1ad normal mode   */\n    RT_ERR_LA_MEMBER_OVERLAP,                       /* 0x00090007, the specified port mask is overlapped with other group               */\n    RT_ERR_LA_NOT_MEMBER_PORT,                      /* 0x00090008, the port is not a member port of the trunk                           */\n    RT_ERR_LA_TRUNK_NOT_EXIST,                      /* 0x00090009, the trunk doesn't exist                                              */\n\n\n    /* 0x000axxxx for storm filter */\n    RT_ERR_SFC_TICK_PERIOD = 0x000a0000,            /* 0x000a0000, invalid SFC tick period                                              */\n    RT_ERR_SFC_UNKNOWN_GROUP,                       /* 0x000a0001, Unknown Storm filter group                                           */\n\n    /* 0x000bxxxx for pattern match */\n    RT_ERR_PM_MASK = 0x000b0000,                    /* 0x000b0000, invalid pattern length. Pattern length should be 8                   */\n    RT_ERR_PM_LENGTH,                               /* 0x000b0001, invalid pattern match mask, first byte must care                     */\n    RT_ERR_PM_MODE,                                 /* 0x000b0002, invalid pattern match mode                                           */\n\n    /* 0x000cxxxx for input bandwidth control */\n    RT_ERR_INBW_TICK_PERIOD = 0x000c0000,           /* 0x000c0000, invalid tick period for input bandwidth control                      */\n    RT_ERR_INBW_TOKEN_AMOUNT,                       /* 0x000c0001, invalid amount of token for input bandwidth control                  */\n    RT_ERR_INBW_FCON_VALUE,                         /* 0x000c0002, invalid flow control ON threshold value for input bandwidth control  */\n    RT_ERR_INBW_FCOFF_VALUE,                        /* 0x000c0003, invalid flow control OFF threshold value for input bandwidth control */\n    RT_ERR_INBW_FC_ALLOWANCE,                       /* 0x000c0004, invalid allowance of incomming packet for input bandwidth control    */\n    RT_ERR_INBW_RATE,                               /* 0x000c0005, invalid input bandwidth                                              */\n\n    /* 0x000dxxxx for QoS */\n    RT_ERR_QOS_1P_PRIORITY = 0x000d0000,            /* 0x000d0000, invalid 802.1P priority                                              */\n    RT_ERR_QOS_DSCP_VALUE,                          /* 0x000d0001, invalid DSCP value                                                   */\n    RT_ERR_QOS_INT_PRIORITY,                        /* 0x000d0002, invalid internal priority                                            */\n    RT_ERR_QOS_SEL_DSCP_PRI,                        /* 0x000d0003, invalid DSCP selection priority                                      */\n    RT_ERR_QOS_SEL_PORT_PRI,                        /* 0x000d0004, invalid port selection priority                                      */\n    RT_ERR_QOS_SEL_IN_ACL_PRI,                      /* 0x000d0005, invalid ingress ACL selection priority                               */\n    RT_ERR_QOS_SEL_CLASS_PRI,                       /* 0x000d0006, invalid classifier selection priority                                */\n    RT_ERR_QOS_EBW_RATE,                            /* 0x000d0007, invalid egress bandwidth rate                                        */\n    RT_ERR_QOS_SCHE_TYPE,                           /* 0x000d0008, invalid QoS scheduling type                                          */\n    RT_ERR_QOS_QUEUE_WEIGHT,                        /* 0x000d0009, invalid Queue weight                                                 */\n    RT_ERR_QOS_SEL_PRI_SOURCE,                      /* 0x000d000a, invalid selection of priority source                                                 */\n\n    /* 0x000exxxx for port ability */\n    RT_ERR_PHY_PAGE_ID = 0x000e0000,                /* 0x000e0000, invalid PHY page id                                                  */\n    RT_ERR_PHY_REG_ID,                              /* 0x000e0001, invalid PHY reg id                                                   */\n    RT_ERR_PHY_DATAMASK,                            /* 0x000e0002, invalid PHY data mask                                                */\n    RT_ERR_PHY_AUTO_NEGO_MODE,                      /* 0x000e0003, invalid PHY auto-negotiation mode*/\n    RT_ERR_PHY_SPEED,                               /* 0x000e0004, invalid PHY speed setting                                            */\n    RT_ERR_PHY_DUPLEX,                              /* 0x000e0005, invalid PHY duplex setting                                           */\n    RT_ERR_PHY_FORCE_ABILITY,                       /* 0x000e0006, invalid PHY force mode ability parameter                             */\n    RT_ERR_PHY_FORCE_1000,                          /* 0x000e0007, invalid PHY force mode 1G speed setting                              */\n    RT_ERR_PHY_TXRX,                                /* 0x000e0008, invalid PHY tx/rx                                                    */\n    RT_ERR_PHY_ID,                                  /* 0x000e0009, invalid PHY id                                                       */\n    RT_ERR_PHY_RTCT_NOT_FINISH,                     /* 0x000e000a, PHY RTCT in progress                                                 */\n\n    /* 0x000fxxxx for mirror */\n    RT_ERR_MIRROR_DIRECTION = 0x000f0000,           /* 0x000f0000, invalid error mirror direction                                       */\n    RT_ERR_MIRROR_SESSION_FULL,                     /* 0x000f0001, mirroring session is full                                            */\n    RT_ERR_MIRROR_SESSION_NOEXIST,                  /* 0x000f0002, mirroring session not exist                                          */\n    RT_ERR_MIRROR_PORT_EXIST,                       /* 0x000f0003, mirroring port already exists                                        */\n    RT_ERR_MIRROR_PORT_NOT_EXIST,                   /* 0x000f0004, mirroring port does not exists                                       */\n    RT_ERR_MIRROR_PORT_FULL,                        /* 0x000f0005, Exceeds maximum number of supported mirroring port                   */\n\n    /* 0x0010xxxx for stat */\n    RT_ERR_STAT_INVALID_GLOBAL_CNTR = 0x00100000,   /* 0x00100000, Invalid Global Counter                                               */\n    RT_ERR_STAT_INVALID_PORT_CNTR,                  /* 0x00100001, Invalid Port Counter                                                 */\n    RT_ERR_STAT_GLOBAL_CNTR_FAIL,                   /* 0x00100002, Could not retrieve/reset Global Counter                              */\n    RT_ERR_STAT_PORT_CNTR_FAIL,                     /* 0x00100003, Could not retrieve/reset Port Counter                                */\n    RT_ERR_STAT_INVALID_CNTR,                       /* 0x00100004, Invalid Counter                                                      */\n    RT_ERR_STAT_CNTR_FAIL,                          /* 0x00100005, Could not retrieve/reset Counter                                     */\n\n    /* 0x0011xxxx for dot1x */\n    RT_ERR_DOT1X_INVALID_DIRECTION = 0x00110000,    /* 0x00110000, Invalid Authentication Direction                                     */\n    RT_ERR_DOT1X_PORTBASEDPNEN,                     /* 0x00110001, Port-based enable port error                                         */\n    RT_ERR_DOT1X_PORTBASEDAUTH,                     /* 0x00110002, Port-based auth port error                                           */\n    RT_ERR_DOT1X_PORTBASEDOPDIR,                    /* 0x00110003, Port-based opdir error                                               */\n    RT_ERR_DOT1X_MACBASEDPNEN,                      /* 0x00110004, MAC-based enable port error                                          */\n    RT_ERR_DOT1X_MACBASEDOPDIR,                     /* 0x00110005, MAC-based opdir error                                                */\n    RT_ERR_DOT1X_PROC,                              /* 0x00110006, unauthorized behavior error                                          */\n    RT_ERR_DOT1X_GVLANIDX,                          /* 0x00110007, guest vlan index error                                               */\n    RT_ERR_DOT1X_GVLANTALK,                         /* 0x00110008, guest vlan OPDIR error                                               */\n    RT_ERR_DOT1X_MAC_PORT_MISMATCH,                 /* 0x00110009, Auth MAC and port mismatch eror                                      */\n\n    RT_ERR_END                                       /* The symbol is the latest symbol                                                  */\n} rt_error_code_t;\n\n\n#endif /* __COMMON_RT_ERROR_H__ */\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtk_hal.h",
    "content": "#ifndef __RTK_HAL_H__\n#define __RTK_HAL_H__\n#include \"ra_ioctl.h\"\n\n#define RTK_SW_VID_RANGE        16\nvoid rtk_hal_switch_init(void);\nvoid rtk_hal_dump_mib(void);\nvoid rtk_hal_dump_full_mib(void);\nint rtk_hal_dump_vlan(void);\nvoid rtk_hal_clear_vlan(void);\nint rtk_hal_set_vlan(struct ra_switch_ioctl_data *data);\nint rtk_hal_set_ingress_rate(struct ra_switch_ioctl_data *data);\nint rtk_hal_set_egress_rate(struct ra_switch_ioctl_data *data);\nvoid rtk_hal_dump_table(void);\nvoid rtk_hal_clear_table(void);\nvoid rtk_hal_get_phy_status(struct ra_switch_ioctl_data *data);\nvoid rtk_hal_set_port_mirror(struct ra_switch_ioctl_data *data);\nvoid rtk_hal_read_reg(struct ra_switch_ioctl_data *data);\nvoid rtk_hal_write_reg(struct ra_switch_ioctl_data *data);\nvoid rtk_hal_qos_en(struct ra_switch_ioctl_data *data);\nvoid rtk_hal_qos_set_table2type(struct ra_switch_ioctl_data *data);\nvoid rtk_hal_qos_get_table2type(struct ra_switch_ioctl_data *data);\nvoid rtk_hal_qos_set_port2table(struct ra_switch_ioctl_data *data);\nvoid rtk_hal_qos_get_port2table(struct ra_switch_ioctl_data *data);\nvoid rtk_hal_qos_set_port2pri(struct ra_switch_ioctl_data *data);\nvoid rtk_hal_qos_get_port2pri(struct ra_switch_ioctl_data *data);\nvoid rtk_hal_qos_set_dscp2pri(struct ra_switch_ioctl_data *data);\nvoid rtk_hal_qos_get_dscp2pri(struct ra_switch_ioctl_data *data);\nvoid rtk_hal_qos_set_pri2queue(struct ra_switch_ioctl_data *data);\nvoid rtk_hal_qos_get_pri2queue(struct ra_switch_ioctl_data *data);\nvoid rtk_hal_qos_set_queue_weight(struct ra_switch_ioctl_data *data);\nvoid rtk_hal_qos_get_queue_weight(struct ra_switch_ioctl_data *data);\nvoid rtk_hal_enable_igmpsnoop(struct ra_switch_ioctl_data *data);\nvoid rtk_hal_disable_igmpsnoop(void);\nvoid rtk_hal_set_phy_test_mode(struct ra_switch_ioctl_data *data);\nvoid rtk_hal_get_phy_reg(struct ra_switch_ioctl_data *data);\nvoid rtk_hal_set_phy_reg(struct ra_switch_ioctl_data *data);\nvoid rtk_hal_vlan_tag(struct ra_switch_ioctl_data *data);\nvoid rtk_hal_vlan_portpvid_set(rtk_port_t port, rtk_vlan_t pvid, rtk_pri_t priority);\nvoid rtk_hal_add_table(struct ra_switch_ioctl_data *data);\nvoid rtk_hal_del_table(struct ra_switch_ioctl_data *data);\nvoid rtk_hal_vlan_mode(struct ra_switch_ioctl_data *data);\nvoid rtk_hal_set_port_trunk(struct ra_switch_ioctl_data *data);\n#endif\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtk_switch.h",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * $Revision: 76336 $\n * $Date: 2017-03-09 10:41:21 +0800 (週四, 09 三月 2017) $\n *\n * Purpose : RTK switch high-level API\n * Feature : Here is a list of all functions and variables in this module.\n *\n */\n\n#ifndef __RTK_SWITCH_H__\n#define __RTK_SWITCH_H__\n\n#include <rtk_types.h>\n\n#define UNDEFINE_PHY_PORT   (0xFF)\n#define RTK_SWITCH_PORT_NUM (32)\n\n#define MAXPKTLEN_CFG_ID_MAX (1)\n\n#define RTK_SWITCH_MAX_PKTLEN (0x3FFF)\n\ntypedef enum init_state_e\n{\n    INIT_NOT_COMPLETED = 0,\n    INIT_COMPLETED,\n    INIT_STATE_END\n} init_state_t;\n\ntypedef enum switch_chip_e\n{\n    CHIP_RTL8367C = 0,\n    CHIP_RTL8370B,\n    CHIP_RTL8364B,\n    CHIP_RTL8363SC_VB,\n    CHIP_END\n}switch_chip_t;\n\ntypedef enum port_type_e\n{\n    UTP_PORT = 0,\n    EXT_PORT,\n    UNKNOWN_PORT = 0xFF,\n    PORT_TYPE_END\n}port_type_t;\n\ntypedef struct rtk_switch_halCtrl_s\n{\n    switch_chip_t   switch_type;\n    rtk_uint32      l2p_port[RTK_SWITCH_PORT_NUM];\n    rtk_uint32      p2l_port[RTK_SWITCH_PORT_NUM];\n    port_type_t     log_port_type[RTK_SWITCH_PORT_NUM];\n    rtk_uint32      ptp_port[RTK_SWITCH_PORT_NUM];\n    rtk_uint32      valid_portmask;\n    rtk_uint32      valid_utp_portmask;\n    rtk_uint32      valid_ext_portmask;\n    rtk_uint32      valid_cpu_portmask;\n    rtk_uint32      min_phy_port;\n    rtk_uint32      max_phy_port;\n    rtk_uint32      phy_portmask;\n    rtk_uint32      combo_logical_port;\n    rtk_uint32      hsg_logical_port;\n    rtk_uint32      sg_logical_portmask;\n    rtk_uint32      max_meter_id;\n    rtk_uint32      max_lut_addr_num;\n    rtk_uint32      trunk_group_mask;\n\n}rtk_switch_halCtrl_t;\n\ntypedef enum rtk_switch_maxPktLen_linkSpeed_e {\n     MAXPKTLEN_LINK_SPEED_FE = 0,\n     MAXPKTLEN_LINK_SPEED_GE,\n     MAXPKTLEN_LINK_SPEED_END,\n} rtk_switch_maxPktLen_linkSpeed_t;\n\n\n/* UTIL MACRO */\n#define RTK_CHK_INIT_STATE()                                \\\n    do                                                      \\\n    {                                                       \\\n        if(rtk_switch_initialState_get() != INIT_COMPLETED) \\\n        {                                                   \\\n            return RT_ERR_NOT_INIT;                         \\\n        }                                                   \\\n    }while(0)\n\n#define RTK_CHK_PORT_VALID(__port__)                            \\\n    do                                                          \\\n    {                                                           \\\n        if(rtk_switch_logicalPortCheck(__port__) != RT_ERR_OK)  \\\n        {                                                       \\\n            return RT_ERR_PORT_ID;                              \\\n        }                                                       \\\n    }while(0)\n\n#define RTK_CHK_PORT_IS_UTP(__port__)                           \\\n    do                                                          \\\n    {                                                           \\\n        if(rtk_switch_isUtpPort(__port__) != RT_ERR_OK)         \\\n        {                                                       \\\n            return RT_ERR_PORT_ID;                              \\\n        }                                                       \\\n    }while(0)\n\n#define RTK_CHK_PORT_IS_EXT(__port__)                           \\\n    do                                                          \\\n    {                                                           \\\n        if(rtk_switch_isExtPort(__port__) != RT_ERR_OK)         \\\n        {                                                       \\\n            return RT_ERR_PORT_ID;                              \\\n        }                                                       \\\n    }while(0)\n\n#define RTK_CHK_PORT_IS_COMBO(__port__)                         \\\n    do                                                          \\\n    {                                                           \\\n        if(rtk_switch_isComboPort(__port__) != RT_ERR_OK)       \\\n        {                                                       \\\n            return RT_ERR_PORT_ID;                              \\\n        }                                                       \\\n    }while(0)\n\n#define RTK_CHK_PORT_IS_PTP(__port__)                           \\\n    do                                                          \\\n    {                                                           \\\n        if(rtk_switch_isPtpPort(__port__) != RT_ERR_OK)         \\\n        {                                                       \\\n            return RT_ERR_PORT_ID;                              \\\n        }                                                       \\\n    }while(0)\n\n#define RTK_CHK_PORTMASK_VALID(__portmask__)                        \\\n    do                                                              \\\n    {                                                               \\\n        if(rtk_switch_isPortMaskValid(__portmask__) != RT_ERR_OK)   \\\n        {                                                           \\\n            return RT_ERR_PORT_MASK;                                \\\n        }                                                           \\\n    }while(0)\n\n#define RTK_CHK_PORTMASK_VALID_ONLY_UTP(__portmask__)               \\\n    do                                                              \\\n    {                                                               \\\n        if(rtk_switch_isPortMaskUtp(__portmask__) != RT_ERR_OK)     \\\n        {                                                           \\\n            return RT_ERR_PORT_MASK;                                \\\n        }                                                           \\\n    }while(0)\n\n#define RTK_CHK_PORTMASK_VALID_ONLY_EXT(__portmask__)               \\\n    do                                                              \\\n    {                                                               \\\n        if(rtk_switch_isPortMaskExt(__portmask__) != RT_ERR_OK)     \\\n        {                                                           \\\n            return RT_ERR_PORT_MASK;                                \\\n        }                                                           \\\n    }while(0)\n\n#define RTK_CHK_TRUNK_GROUP_VALID(__grpId__)                        \\\n    do                                                              \\\n    {                                                               \\\n        if(rtk_switch_isValidTrunkGrpId(__grpId__) != RT_ERR_OK)    \\\n        {                                                           \\\n            return RT_ERR_LA_TRUNK_ID;                              \\\n        }                                                           \\\n    }while(0)\n\n#define RTK_PORTMASK_IS_PORT_SET(__portmask__, __port__)    (((__portmask__).bits[0] & (0x00000001 << __port__)) ? 1 : 0)\n#define RTK_PORTMASK_IS_EMPTY(__portmask__)                 (((__portmask__).bits[0] == 0) ? 1 : 0)\n#define RTK_PORTMASK_CLEAR(__portmask__)                    ((__portmask__).bits[0] = 0)\n#define RTK_PORTMASK_PORT_SET(__portmask__, __port__)       ((__portmask__).bits[0] |= (0x00000001 << __port__))\n#define RTK_PORTMASK_PORT_CLEAR(__portmask__, __port__)     ((__portmask__).bits[0] &= ~(0x00000001 << __port__))\n#define RTK_PORTMASK_ALLPORT_SET(__portmask__)              (rtk_switch_logPortMask_get(&__portmask__))\n#define RTK_PORTMASK_SCAN(__portmask__, __port__)           for(__port__ = 0; __port__ < RTK_SWITCH_PORT_NUM; __port__++)  if(RTK_PORTMASK_IS_PORT_SET(__portmask__, __port__))\n#define RTK_PORTMASK_COMPARE(__portmask_A__, __portmask_B__)    ((__portmask_A__).bits[0] - (__portmask_B__).bits[0])\n\n#define RTK_SCAN_ALL_PHY_PORTMASK(__port__)                 for(__port__ = 0; __port__ < RTK_SWITCH_PORT_NUM; __port__++)  if( (rtk_switch_phyPortMask_get() & (0x00000001 << __port__)))\n#define RTK_SCAN_ALL_LOG_PORT(__port__)                     for(__port__ = 0; __port__ < RTK_SWITCH_PORT_NUM; __port__++)  if( rtk_switch_logicalPortCheck(__port__) == RT_ERR_OK)\n#define RTK_SCAN_ALL_LOG_PORTMASK(__portmask__)             for((__portmask__).bits[0] = 0; (__portmask__).bits[0] < 0x7FFFF; (__portmask__).bits[0]++)  if( rtk_switch_isPortMaskValid(&__portmask__) == RT_ERR_OK)\n\n/* Port mask defination */\n#define RTK_PHY_PORTMASK_ALL                                (rtk_switch_phyPortMask_get())\n\n/* Port defination*/\n#define RTK_MAX_LOGICAL_PORT_ID                             (rtk_switch_maxLogicalPort_get())\n\n/* Function Name:\n *      rtk_switch_probe\n * Description:\n *      Probe switch\n * Input:\n *      None\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Switch probed\n *      RT_ERR_FAILED   - Switch Unprobed.\n * Note:\n *\n */\nextern rtk_api_ret_t rtk_switch_probe(switch_chip_t *pSwitchChip);\n\n/* Function Name:\n *      rtk_switch_initialState_set\n * Description:\n *      Set initial status\n * Input:\n *      state   - Initial state;\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Initialized\n *      RT_ERR_FAILED   - Uninitialized\n * Note:\n *\n */\nextern rtk_api_ret_t rtk_switch_initialState_set(init_state_t state);\n\n/* Function Name:\n *      rtk_switch_initialState_get\n * Description:\n *      Get initial status\n * Input:\n *      None\n * Output:\n *      None\n * Return:\n *      INIT_COMPLETED     - Initialized\n *      INIT_NOT_COMPLETED - Uninitialized\n * Note:\n *\n */\nextern init_state_t rtk_switch_initialState_get(void);\n\n/* Function Name:\n *      rtk_switch_logicalPortCheck\n * Description:\n *      Check logical port ID.\n * Input:\n *      logicalPort     - logical port ID\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Port ID is correct\n *      RT_ERR_FAILED   - Port ID is not correct\n *      RT_ERR_NOT_INIT - Not Initialize\n * Note:\n *\n */\nextern rtk_api_ret_t rtk_switch_logicalPortCheck(rtk_port_t logicalPort);\n\n/* Function Name:\n *      rtk_switch_isUtpPort\n * Description:\n *      Check is logical port a UTP port\n * Input:\n *      logicalPort     - logical port ID\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Port ID is a UTP port\n *      RT_ERR_FAILED   - Port ID is not a UTP port\n *      RT_ERR_NOT_INIT - Not Initialize\n * Note:\n *\n */\nextern rtk_api_ret_t rtk_switch_isUtpPort(rtk_port_t logicalPort);\n\n/* Function Name:\n *      rtk_switch_isExtPort\n * Description:\n *      Check is logical port a Extension port\n * Input:\n *      logicalPort     - logical port ID\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Port ID is a EXT port\n *      RT_ERR_FAILED   - Port ID is not a EXT port\n *      RT_ERR_NOT_INIT - Not Initialize\n * Note:\n *\n */\nextern rtk_api_ret_t rtk_switch_isExtPort(rtk_port_t logicalPort);\n\n/* Function Name:\n *      rtk_switch_isHsgPort\n * Description:\n *      Check is logical port a HSG port\n * Input:\n *      logicalPort     - logical port ID\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Port ID is a HSG port\n *      RT_ERR_FAILED   - Port ID is not a HSG port\n *      RT_ERR_NOT_INIT - Not Initialize\n * Note:\n *\n */\nextern rtk_api_ret_t rtk_switch_isHsgPort(rtk_port_t logicalPort);\n\n/* Function Name:\n *      rtk_switch_isSgmiiPort\n * Description:\n *      Check is logical port a SGMII port\n * Input:\n *      logicalPort     - logical port ID\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Port ID is a SGMII port\n *      RT_ERR_FAILED   - Port ID is not a SGMII port\n *      RT_ERR_NOT_INIT - Not Initialize\n * Note:\n *\n */\nextern rtk_api_ret_t rtk_switch_isSgmiiPort(rtk_port_t logicalPort);\n\n/* Function Name:\n *      rtk_switch_isCPUPort\n * Description:\n *      Check is logical port a CPU port\n * Input:\n *      logicalPort     - logical port ID\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Port ID is a CPU port\n *      RT_ERR_FAILED   - Port ID is not a CPU port\n *      RT_ERR_NOT_INIT - Not Initialize\n * Note:\n *\n */\nextern rtk_api_ret_t rtk_switch_isCPUPort(rtk_port_t logicalPort);\n\n/* Function Name:\n *      rtk_switch_isComboPort\n * Description:\n *      Check is logical port a Combo port\n * Input:\n *      logicalPort     - logical port ID\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Port ID is a combo port\n *      RT_ERR_FAILED   - Port ID is not a combo port\n *      RT_ERR_NOT_INIT - Not Initialize\n * Note:\n *\n */\nextern rtk_api_ret_t rtk_switch_isComboPort(rtk_port_t logicalPort);\n\n/* Function Name:\n *      rtk_switch_ComboPort_get\n * Description:\n *      Get Combo port ID\n * Input:\n *      None\n * Output:\n *      None\n * Return:\n *      Port ID of combo port\n * Note:\n *\n */\nextern rtk_uint32 rtk_switch_ComboPort_get(void);\n\n/* Function Name:\n *      rtk_switch_isPtpPort\n * Description:\n *      Check is logical port a PTP port\n * Input:\n *      logicalPort     - logical port ID\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Port ID is a PTP port\n *      RT_ERR_FAILED   - Port ID is not a PTP port\n *      RT_ERR_NOT_INIT - Not Initialize\n * Note:\n *\n */\nextern rtk_api_ret_t rtk_switch_isPtpPort(rtk_port_t logicalPort);\n\n/* Function Name:\n *      rtk_switch_port_L2P_get\n * Description:\n *      Get physical port ID\n * Input:\n *      logicalPort       - logical port ID\n * Output:\n *      None\n * Return:\n *      Physical port ID\n * Note:\n *\n */\nextern rtk_uint32 rtk_switch_port_L2P_get(rtk_port_t logicalPort);\n\n/* Function Name:\n *      rtk_switch_port_P2L_get\n * Description:\n *      Get logical port ID\n * Input:\n *      physicalPort       - physical port ID\n * Output:\n *      None\n * Return:\n *      logical port ID\n * Note:\n *\n */\nextern rtk_port_t rtk_switch_port_P2L_get(rtk_uint32 physicalPort);\n\n/* Function Name:\n *      rtk_switch_isPortMaskValid\n * Description:\n *      Check portmask is valid or not\n * Input:\n *      pPmask       - logical port mask\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - port mask is valid\n *      RT_ERR_FAILED       - port mask is not valid\n *      RT_ERR_NOT_INIT     - Not Initialize\n *      RT_ERR_NULL_POINTER - Null pointer\n * Note:\n *\n */\nextern rtk_api_ret_t rtk_switch_isPortMaskValid(rtk_portmask_t *pPmask);\n\n/* Function Name:\n *      rtk_switch_isPortMaskUtp\n * Description:\n *      Check all ports in portmask are only UTP port\n * Input:\n *      pPmask       - logical port mask\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Only UTP port in port mask\n *      RT_ERR_FAILED       - Not only UTP port in port mask\n *      RT_ERR_NOT_INIT     - Not Initialize\n *      RT_ERR_NULL_POINTER - Null pointer\n * Note:\n *\n */\nextern rtk_api_ret_t rtk_switch_isPortMaskUtp(rtk_portmask_t *pPmask);\n\n/* Function Name:\n *      rtk_switch_isPortMaskExt\n * Description:\n *      Check all ports in portmask are only EXT port\n * Input:\n *      pPmask       - logical port mask\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Only EXT port in port mask\n *      RT_ERR_FAILED       - Not only EXT port in port mask\n *      RT_ERR_NOT_INIT     - Not Initialize\n *      RT_ERR_NULL_POINTER - Null pointer\n * Note:\n *\n */\nextern rtk_api_ret_t rtk_switch_isPortMaskExt(rtk_portmask_t *pPmask);\n\n/* Function Name:\n *      rtk_switch_portmask_L2P_get\n * Description:\n *      Get physicl portmask from logical portmask\n * Input:\n *      pLogicalPmask       - logical port mask\n * Output:\n *      pPhysicalPortmask   - physical port mask\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_NOT_INIT     - Not Initialize\n *      RT_ERR_NULL_POINTER - Null pointer\n *      RT_ERR_PORT_MASK    - Error port mask\n * Note:\n *\n */\nextern rtk_api_ret_t rtk_switch_portmask_L2P_get(rtk_portmask_t *pLogicalPmask, rtk_uint32 *pPhysicalPortmask);\n\n/* Function Name:\n *      rtk_switch_portmask_P2L_get\n * Description:\n *      Get logical portmask from physical portmask\n * Input:\n *      physicalPortmask    - physical port mask\n * Output:\n *      pLogicalPmask       - logical port mask\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_NOT_INIT     - Not Initialize\n *      RT_ERR_NULL_POINTER - Null pointer\n *      RT_ERR_PORT_MASK    - Error port mask\n * Note:\n *\n */\nextern rtk_api_ret_t rtk_switch_portmask_P2L_get(rtk_uint32 physicalPortmask, rtk_portmask_t *pLogicalPmask);\n\n/* Function Name:\n *      rtk_switch_phyPortMask_get\n * Description:\n *      Get physical portmask\n * Input:\n *      None\n * Output:\n *      None\n * Return:\n *      0x00                - Not Initialize\n *      Other value         - Physical port mask\n * Note:\n *\n */\nrtk_uint32 rtk_switch_phyPortMask_get(void);\n\n/* Function Name:\n *      rtk_switch_logPortMask_get\n * Description:\n *      Get Logical portmask\n * Input:\n *      None\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_NOT_INIT     - Not Initialize\n *      RT_ERR_NULL_POINTER - Null pointer\n * Note:\n *\n */\nrtk_api_ret_t rtk_switch_logPortMask_get(rtk_portmask_t *pPortmask);\n\n/* Function Name:\n *      rtk_switch_init\n * Description:\n *      Set chip to default configuration enviroment\n * Input:\n *      None\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n * Note:\n *      The API can set chip registers to default configuration for different release chip model.\n */\nextern rtk_api_ret_t rtk_switch_init(void);\n\n/* Function Name:\n *      rtk_switch_portMaxPktLen_set\n * Description:\n *      Set Max packet length\n * Input:\n *      port    - Port ID\n *      speed   - Speed\n *      cfgId   - Configuration ID\n * Output:\n *      None.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Error Input\n * Note:\n */\nextern rtk_api_ret_t rtk_switch_portMaxPktLen_set(rtk_port_t port, rtk_switch_maxPktLen_linkSpeed_t speed, rtk_uint32 cfgId);\n\n/* Function Name:\n *      rtk_switch_portMaxPktLen_get\n * Description:\n *      Get Max packet length\n * Input:\n *      port    - Port ID\n *      speed   - Speed\n * Output:\n *      pCfgId  - Configuration ID\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Error Input\n * Note:\n */\nextern rtk_api_ret_t rtk_switch_portMaxPktLen_get(rtk_port_t port, rtk_switch_maxPktLen_linkSpeed_t speed, rtk_uint32 *pCfgId);\n\n/* Function Name:\n *      rtk_switch_maxPktLenCfg_set\n * Description:\n *      Set Max packet length configuration\n * Input:\n *      cfgId   - Configuration ID\n *      pktLen  - Max packet length\n * Output:\n *      None.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Error Input\n * Note:\n */\nextern rtk_api_ret_t rtk_switch_maxPktLenCfg_set(rtk_uint32 cfgId, rtk_uint32 pktLen);\n\n/* Function Name:\n *      rtk_switch_maxPktLenCfg_get\n * Description:\n *      Get Max packet length configuration\n * Input:\n *      cfgId   - Configuration ID\n *      pPktLen - Max packet length\n * Output:\n *      None.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Error Input\n * Note:\n */\nextern rtk_api_ret_t rtk_switch_maxPktLenCfg_get(rtk_uint32 cfgId, rtk_uint32 *pPktLen);\n\n/* Function Name:\n *      rtk_switch_greenEthernet_set\n * Description:\n *      Set all Ports Green Ethernet state.\n * Input:\n *      enable - Green Ethernet state.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - OK\n *      RT_ERR_FAILED   - Failed\n *      RT_ERR_SMI      - SMI access error\n *      RT_ERR_ENABLE   - Invalid enable input.\n * Note:\n *      This API can set all Ports Green Ethernet state.\n *      The configuration is as following:\n *      - DISABLE\n *      - ENABLE\n */\nextern rtk_api_ret_t rtk_switch_greenEthernet_set(rtk_enable_t enable);\n\n/* Function Name:\n *      rtk_switch_greenEthernet_get\n * Description:\n *      Get all Ports Green Ethernet state.\n * Input:\n *      None\n * Output:\n *      pEnable - Green Ethernet state.\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n * Note:\n *      This API can get Green Ethernet state.\n */\nextern rtk_api_ret_t rtk_switch_greenEthernet_get(rtk_enable_t *pEnable);\n\n/* Function Name:\n *      rtk_switch_maxLogicalPort_get\n * Description:\n *      Get Max logical port ID\n * Input:\n *      None\n * Output:\n *      None\n * Return:\n *      Max logical port\n * Note:\n *      This API can get max logical port\n */\nextern rtk_port_t rtk_switch_maxLogicalPort_get(void);\n\n/* Function Name:\n *      rtk_switch_maxMeterId_get\n * Description:\n *      Get Max Meter ID\n * Input:\n *      None\n * Output:\n *      None\n * Return:\n *      0x00                - Not Initialize\n *      Other value         - Max Meter ID\n * Note:\n *\n */\nextern rtk_uint32 rtk_switch_maxMeterId_get(void);\n\n/* Function Name:\n *      rtk_switch_maxLutAddrNumber_get\n * Description:\n *      Get Max LUT Address number\n * Input:\n *      None\n * Output:\n *      None\n * Return:\n *      0x00                - Not Initialize\n *      Other value         - Max LUT Address number\n * Note:\n *\n */\nextern rtk_uint32 rtk_switch_maxLutAddrNumber_get(void);\n\n/* Function Name:\n *      rtk_switch_isValidTrunkGrpId\n * Description:\n *      Check if trunk group is valid or not\n * Input:\n *      grpId       - Group ID\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Trunk Group ID is valid\n *      RT_ERR_LA_TRUNK_ID  - Trunk Group ID is not valid\n * Note:\n *\n */\nrtk_uint32 rtk_switch_isValidTrunkGrpId(rtk_uint32 grpId);\n\n#endif\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtk_types.h",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * $Revision: 76306 $\n * $Date: 2017-03-08 15:13:58 +0800 (gT, 08 T 2017) $\n *\n * Purpose : RTL8367C switch high-level type enum definition.\n * Feature :\n *\n */\n\n#ifndef _RTL8367C_TYPES_H_\n#define _RTL8367C_TYPES_H_\n\n//#include <stdio.h>\n\ntypedef unsigned long long      rtk_uint64;\ntypedef long long               rtk_int64;\ntypedef unsigned int            rtk_uint32;\ntypedef int                     rtk_int32;\ntypedef unsigned short          rtk_uint16;\ntypedef short                   rtk_int16;\ntypedef unsigned char           rtk_uint8;\ntypedef char                    rtk_int8;\n\n#define CONST_T     const\n\n#define RTK_TOTAL_NUM_OF_WORD_FOR_1BIT_PORT_LIST    1\n\n#define RTK_MAX_NUM_OF_PORT                         8\n#define RTK_PORT_ID_MAX                             (RTK_MAX_NUM_OF_PORT-1)\n#define RTK_PHY_ID_MAX                              (RTK_MAX_NUM_OF_PORT-4)\n#define RTK_MAX_PORT_MASK                           0xFF\n\n#define RTK_WHOLE_SYSTEM                            0xFF\n\ntypedef struct rtk_portmask_s\n{\n    rtk_uint32  bits[RTK_TOTAL_NUM_OF_WORD_FOR_1BIT_PORT_LIST];\n} rtk_portmask_t;\n\ntypedef enum rtk_enable_e\n{\n    DISABLED = 0,\n    ENABLED,\n    RTK_ENABLE_END\n} rtk_enable_t;\n\n#ifndef ETHER_ADDR_LEN\n#define ETHER_ADDR_LEN      6\n#endif\n\n/* ethernet address type */\ntypedef struct  rtk_mac_s\n{\n    rtk_uint8 octet[ETHER_ADDR_LEN];\n} rtk_mac_t;\n\ntypedef rtk_uint32  rtk_pri_t;      /* priority vlaue */\ntypedef rtk_uint32  rtk_qid_t;      /* queue id type */\ntypedef rtk_uint32  rtk_data_t;\ntypedef rtk_uint32  rtk_dscp_t;     /* dscp vlaue */\ntypedef rtk_uint32  rtk_fid_t;      /* filter id type */\ntypedef rtk_uint32  rtk_vlan_t;     /* vlan id type */\ntypedef rtk_uint32  rtk_mac_cnt_t;  /* MAC count type  */\ntypedef rtk_uint32  rtk_meter_id_t; /* meter id type  */\ntypedef rtk_uint32  rtk_rate_t;     /* rate type  */\n\ntypedef enum rtk_port_e\n{\n    UTP_PORT0 = 0,\n    UTP_PORT1,\n    UTP_PORT2,\n    UTP_PORT3,\n    UTP_PORT4,\n    UTP_PORT5,\n    UTP_PORT6,\n    UTP_PORT7,\n\n    EXT_PORT0 = 16,\n    EXT_PORT1,\n    EXT_PORT2,\n\n    UNDEFINE_PORT = 30,\n    RTK_PORT_MAX = 31\n} rtk_port_t;\n\n\n#ifndef _RTL_TYPES_H\n\n#if 0\ntypedef unsigned long long      uint64;\ntypedef long long               int64;\ntypedef unsigned int            uint32;\ntypedef int                     int32;\ntypedef unsigned short          uint16;\ntypedef short                   int16;\ntypedef unsigned char           uint8;\ntypedef char                    int8;\n#endif\n\ntypedef rtk_uint32                  ipaddr_t;\ntypedef rtk_uint32                  memaddr;\n\n#ifndef ETHER_ADDR_LEN\n#define ETHER_ADDR_LEN      6\n#endif\n\ntypedef struct ether_addr_s {\n    rtk_uint8 octet[ETHER_ADDR_LEN];\n} ether_addr_t;\n\n#ifdef __KERNEL__\n#define rtlglue_printf printk\n#else\n#define rtlglue_printf printf\n#endif\n#define PRINT           rtlglue_printf\n#endif /*_RTL_TYPES_H*/\n\n/* type abstraction */\n#ifdef EMBEDDED_SUPPORT\n\ntypedef rtk_int16                   rtk_api_ret_t;\ntypedef rtk_int16                   ret_t;\ntypedef rtk_uint32                  rtk_u_long;\n\n#else\n\ntypedef rtk_int32                   rtk_api_ret_t;\ntypedef rtk_int32                   ret_t;\ntypedef rtk_uint64                  rtk_u_long_t;\n\n#endif\n\n#ifndef NULL\n#define NULL 0\n#endif\n\n#ifndef TRUE\n#define TRUE 1\n#endif\n\n#ifndef FALSE\n#define FALSE 0\n#endif\n\n#define CONST           const\n#endif /* _RTL8367C_TYPES_H_ */\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtl8367c_asicdrv.h",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * $Revision: 76306 $\n * $Date: 2017-03-08 15:13:58 +0800 (gT, 08 T 2017) $\n *\n * Purpose : RTL8367C switch high-level API for RTL8367C\n * Feature :\n *\n */\n\n\n#ifndef _RTL8367C_ASICDRV_H_\n#define _RTL8367C_ASICDRV_H_\n\n#include <rtk_types.h>\n#include <rtk_error.h>\n#include <rtl8367c_reg.h>\n#include <rtl8367c_base.h>\n\n#define RTL8367C_REGBITLENGTH               16\n#define RTL8367C_REGDATAMAX                 0xFFFF\n\n#define RTL8367C_VIDMAX                     0xFFF\n#define RTL8367C_EVIDMAX                    0x1FFF\n#define RTL8367C_CVIDXNO                    32\n#define RTL8367C_CVIDXMAX                   (RTL8367C_CVIDXNO-1)\n\n#define RTL8367C_PRIMAX                     7\n#define RTL8367C_DSCPMAX                    63\n\n#define RTL8367C_PORTNO                     11\n#define RTL8367C_PORTIDMAX                  (RTL8367C_PORTNO-1)\n#define RTL8367C_PMSKMAX                    ((1<<(RTL8367C_PORTNO))-1)\n#define RTL8367C_PORTMASK                   0x7FF\n\n#define RTL8367C_PHYNO                      5\n#define RTL8367C_PHYIDMAX                  (RTL8367C_PHYNO-1)\n\n#define RTL8367C_SVIDXNO                    64\n#define RTL8367C_SVIDXMAX                   (RTL8367C_SVIDXNO-1)\n#define RTL8367C_MSTIMAX                    15\n\n#define RTL8367C_METERNO                    64\n#define RTL8367C_METERMAX                   (RTL8367C_METERNO-1)\n#define RTL8367C_METERBUCKETSIZEMAX         0xFFFF\n\n#define RTL8367C_QUEUENO                    8\n#define RTL8367C_QIDMAX                     (RTL8367C_QUEUENO-1)\n\n#define RTL8367C_PHY_BUSY_CHECK_COUNTER     1000\n\n#define RTL8367C_QOS_GRANULARTY_MAX         0x7FFFF\n#define RTL8367C_QOS_GRANULARTY_LSB_MASK    0xFFFF\n#define RTL8367C_QOS_GRANULARTY_LSB_OFFSET  0\n#define RTL8367C_QOS_GRANULARTY_MSB_MASK    0x70000\n#define RTL8367C_QOS_GRANULARTY_MSB_OFFSET  16\n\n#define RTL8367C_QOS_GRANULARTY_UNIT_KBPS   8\n\n#define RTL8367C_QOS_RATE_INPUT_MAX         (0x1FFFF * 8)\n#define RTL8367C_QOS_RATE_INPUT_MAX_HSG     (0x7FFFF * 8)\n#define RTL8367C_QOS_RATE_INPUT_MIN         8\n#define RTL8367C_QOS_PPS_INPUT_MAX          (0x7FFFF)\n#define RTL8367C_QOS_PPS_INPUT_MIN          1\n\n#define RTL8367C_QUEUE_MASK                 0xFF\n\n#define RTL8367C_EFIDMAX                    0x7\n#define RTL8367C_FIDMAX                     0xF\n\n#define RTL8367C_EAV_SECONDMAX                  0xFFFFFFFF\n#define RTL8367C_EAV_NANOSECONDMAX          0x3B9AC9FF\n\n\n/* the above macro is generated by genDotH */\n#define RTL8367C_VALID_REG_NO               3869\n\n/*=======================================================================\n *  Enum\n *========================================================================*/\nenum RTL8367C_TABLE_ACCESS_OP\n{\n    TB_OP_READ = 0,\n    TB_OP_WRITE\n};\n\nenum RTL8367C_TABLE_ACCESS_TARGET\n{\n    TB_TARGET_ACLRULE = 1,\n    TB_TARGET_ACLACT,\n    TB_TARGET_CVLAN,\n    TB_TARGET_L2,\n    TB_TARGET_IGMP_GROUP\n};\n\n#define RTL8367C_TABLE_ACCESS_REG_DATA(op, target)    ((op << 3) | target)\n\n/*=======================================================================\n *  Structures\n *========================================================================*/\n\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\nextern ret_t rtl8367c_setAsicRegBit(rtk_uint32 reg, rtk_uint32 bit, rtk_uint32 value);\nextern ret_t rtl8367c_getAsicRegBit(rtk_uint32 reg, rtk_uint32 bit, rtk_uint32 *pValue);\n\nextern ret_t rtl8367c_setAsicRegBits(rtk_uint32 reg, rtk_uint32 bits, rtk_uint32 value);\nextern ret_t rtl8367c_getAsicRegBits(rtk_uint32 reg, rtk_uint32 bits, rtk_uint32 *pValue);\n\nextern ret_t rtl8367c_setAsicReg(rtk_uint32 reg, rtk_uint32 value);\nextern ret_t rtl8367c_getAsicReg(rtk_uint32 reg, rtk_uint32 *pValue);\n\n#ifdef __cplusplus\n}\n#endif\n\n\n\n#endif /*#ifndef _RTL8367C_ASICDRV_H_*/\n\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtl8367c_asicdrv_acl.h",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * $Revision: 76306 $\n * $Date: 2017-03-08 15:13:58 +0800 (gT, 08 T 2017) $\n *\n * Purpose : RTL8367C switch high-level API for RTL8367C\n * Feature : ACL related function drivers\n *\n */\n\n#ifndef _RTL8367C_ASICDRV_ACL_H_\n#define _RTL8367C_ASICDRV_ACL_H_\n\n#include <rtl8367c_asicdrv.h>\n\n#define RTL8367C_ACLRULENO                  96\n\n#define RTL8367C_ACLRULEMAX                 (RTL8367C_ACLRULENO-1)\n#define RTL8367C_ACLRULEFIELDNO             8\n#define RTL8367C_ACLTEMPLATENO              5\n#define RTL8367C_ACLTYPEMAX                 (RTL8367C_ACLTEMPLATENO-1)\n\n#define RTL8367C_ACLRULETBLEN               9\n#define RTL8367C_ACLACTTBLEN                4\n#define RTL8367C_ACLRULETBADDR(type, rule)  ((type << 6) | rule)\n#define RTL8367C_ACLRULETBADDR2(type, rule) ((type << 5) | (rule + 64))\n\n#define ACL_ACT_CVLAN_ENABLE_MASK           0x1\n#define ACL_ACT_SVLAN_ENABLE_MASK           0x2\n#define ACL_ACT_PRIORITY_ENABLE_MASK        0x4\n#define ACL_ACT_POLICING_ENABLE_MASK        0x8\n#define ACL_ACT_FWD_ENABLE_MASK             0x10\n#define ACL_ACT_INTGPIO_ENABLE_MASK         0x20\n\n#define RTL8367C_ACLRULETAGBITS             5\n\n#define RTL8367C_ACLRANGENO                 16\n\n#define RTL8367C_ACLRANGEMAX                (RTL8367C_ACLRANGENO-1)\n\n#define RTL8367C_ACL_PORTRANGEMAX           (0xFFFF)\n#define RTL8367C_ACL_ACT_TABLE_LEN          (4)\n\nenum ACLTCAMTYPES\n{\n    CAREBITS= 0,\n    DATABITS\n};\n\ntypedef enum aclFwdAct\n{\n    RTL8367C_ACL_FWD_MIRROR = 0,\n    RTL8367C_ACL_FWD_REDIRECT,\n    RTL8367C_ACL_FWD_MIRRORFUNTION,\n    RTL8367C_ACL_FWD_TRAP,\n} rtl8367c_aclFwd_t;\n\nenum ACLFIELDTYPES\n{\n    ACL_UNUSED,\n    ACL_DMAC0,\n    ACL_DMAC1,\n    ACL_DMAC2,\n    ACL_SMAC0,\n    ACL_SMAC1,\n    ACL_SMAC2,\n    ACL_ETHERTYPE,\n    ACL_STAG,\n    ACL_CTAG,\n    ACL_IP4SIP0 = 0x10,\n    ACL_IP4SIP1,\n    ACL_IP4DIP0,\n    ACL_IP4DIP1,\n    ACL_IP6SIP0WITHIPV4 = 0x20,\n    ACL_IP6SIP1WITHIPV4,\n    ACL_IP6DIP0WITHIPV4 = 0x28,\n    ACL_IP6DIP1WITHIPV4,\n    ACL_VIDRANGE = 0x30,\n    ACL_IPRANGE,\n    ACL_PORTRANGE,\n    ACL_FIELD_VALID,\n    ACL_FIELD_SELECT00 = 0x40,\n    ACL_FIELD_SELECT01,\n    ACL_FIELD_SELECT02,\n    ACL_FIELD_SELECT03,\n    ACL_FIELD_SELECT04,\n    ACL_FIELD_SELECT05,\n    ACL_FIELD_SELECT06,\n    ACL_FIELD_SELECT07,\n    ACL_FIELD_SELECT08,\n    ACL_FIELD_SELECT09,\n    ACL_FIELD_SELECT10,\n    ACL_FIELD_SELECT11,\n    ACL_FIELD_SELECT12,\n    ACL_FIELD_SELECT13,\n    ACL_FIELD_SELECT14,\n    ACL_FIELD_SELECT15,\n    ACL_TCPSPORT = 0x80,\n    ACL_TCPDPORT,\n    ACL_TCPFLAG,\n    ACL_UDPSPORT,\n    ACL_UDPDPORT,\n    ACL_ICMPCODETYPE,\n    ACL_IGMPTYPE,\n    ACL_SPORT,\n    ACL_DPORT,\n    ACL_IP4TOSPROTO,\n    ACL_IP4FLAGOFF,\n    ACL_TCNH,\n    ACL_CPUTAG,\n    ACL_L2PAYLOAD,\n    ACL_IP6SIP0,\n    ACL_IP6SIP1,\n    ACL_IP6SIP2,\n    ACL_IP6SIP3,\n    ACL_IP6SIP4,\n    ACL_IP6SIP5,\n    ACL_IP6SIP6,\n    ACL_IP6SIP7,\n    ACL_IP6DIP0,\n    ACL_IP6DIP1,\n    ACL_IP6DIP2,\n    ACL_IP6DIP3,\n    ACL_IP6DIP4,\n    ACL_IP6DIP5,\n    ACL_IP6DIP6,\n    ACL_IP6DIP7,\n    ACL_TYPE_END\n};\n\nstruct acl_rule_smi_st{\n    rtk_uint16 rule_info;\n    rtk_uint16 field[RTL8367C_ACLRULEFIELDNO];\n};\n\nstruct acl_rule_smi_ext_st{\n    rtk_uint16 rule_info;\n};\n\ntypedef struct ACLRULESMI{\n    struct acl_rule_smi_st  care_bits;\n    rtk_uint16      valid:1;\n    struct acl_rule_smi_st  data_bits;\n\n    struct acl_rule_smi_ext_st care_bits_ext;\n    struct acl_rule_smi_ext_st data_bits_ext;\n}rtl8367c_aclrulesmi;\n\nstruct acl_rule_st{\n    rtk_uint16 active_portmsk:11;\n    rtk_uint16 type:3;\n    rtk_uint16 tag_exist:5;\n    rtk_uint16 field[RTL8367C_ACLRULEFIELDNO];\n};\n\ntypedef struct ACLRULE{\n    struct acl_rule_st  data_bits;\n    rtk_uint16      valid:1;\n    struct acl_rule_st  care_bits;\n}rtl8367c_aclrule;\n\n\ntypedef struct rtl8367c_acltemplate_s{\n    rtk_uint8 field[8];\n}rtl8367c_acltemplate_t;\n\n\ntypedef struct acl_act_s{\n    rtk_uint16 cvidx_cact:7;\n    rtk_uint16 cact:2;\n    rtk_uint16 svidx_sact:7;\n    rtk_uint16 sact:2;\n\n\n    rtk_uint16 aclmeteridx:7;\n    rtk_uint16 fwdpmask:11;\n    rtk_uint16 fwdact:2;\n\n    rtk_uint16 pridx:7;\n    rtk_uint16 priact:2;\n    rtk_uint16 gpio_pin:4;\n    rtk_uint16 gpio_en:1;\n    rtk_uint16 aclint:1;\n\n    rtk_uint16 cact_ext:2;\n    rtk_uint16 fwdact_ext:1;\n    rtk_uint16 tag_fmt:2;\n}rtl8367c_acl_act_t;\n\ntypedef struct acl_rule_union_s\n{\n    rtl8367c_aclrule aclRule;\n    rtl8367c_acl_act_t aclAct;\n    rtk_uint32 aclActCtrl;\n    rtk_uint32 aclNot;\n}rtl8367c_acl_rule_union_t;\n\n\nextern ret_t rtl8367c_setAsicAcl(rtk_uint32 port, rtk_uint32 enabled);\nextern ret_t rtl8367c_getAsicAcl(rtk_uint32 port, rtk_uint32* pEnabled);\nextern ret_t rtl8367c_setAsicAclUnmatchedPermit(rtk_uint32 port, rtk_uint32 enabled);\nextern ret_t rtl8367c_getAsicAclUnmatchedPermit(rtk_uint32 port, rtk_uint32* pEnabled);\nextern ret_t rtl8367c_setAsicAclRule(rtk_uint32 index, rtl8367c_aclrule *pAclRule);\nextern ret_t rtl8367c_getAsicAclRule(rtk_uint32 index, rtl8367c_aclrule *pAclRule);\nextern ret_t rtl8367c_setAsicAclNot(rtk_uint32 index, rtk_uint32 not);\nextern ret_t rtl8367c_getAsicAclNot(rtk_uint32 index, rtk_uint32* pNot);\nextern ret_t rtl8367c_setAsicAclTemplate(rtk_uint32 index, rtl8367c_acltemplate_t* pAclType);\nextern ret_t rtl8367c_getAsicAclTemplate(rtk_uint32 index, rtl8367c_acltemplate_t *pAclType);\nextern ret_t rtl8367c_setAsicAclAct(rtk_uint32 index, rtl8367c_acl_act_t* pAclAct);\nextern ret_t rtl8367c_getAsicAclAct(rtk_uint32 index, rtl8367c_acl_act_t *pAclAct);\nextern ret_t rtl8367c_setAsicAclActCtrl(rtk_uint32 index, rtk_uint32 aclActCtrl);\nextern ret_t rtl8367c_getAsicAclActCtrl(rtk_uint32 index, rtk_uint32 *aclActCtrl);\nextern ret_t rtl8367c_setAsicAclPortRange(rtk_uint32 index, rtk_uint32 type, rtk_uint32 upperPort, rtk_uint32 lowerPort);\nextern ret_t rtl8367c_getAsicAclPortRange(rtk_uint32 index, rtk_uint32* pType, rtk_uint32* pUpperPort, rtk_uint32* pLowerPort);\nextern ret_t rtl8367c_setAsicAclVidRange(rtk_uint32 index, rtk_uint32 type, rtk_uint32 upperVid, rtk_uint32 lowerVid);\nextern ret_t rtl8367c_getAsicAclVidRange(rtk_uint32 index, rtk_uint32* pType, rtk_uint32* pUpperVid, rtk_uint32* pLowerVid);\nextern ret_t rtl8367c_setAsicAclIpRange(rtk_uint32 index, rtk_uint32 type, ipaddr_t upperIp, ipaddr_t lowerIp);\nextern ret_t rtl8367c_getAsicAclIpRange(rtk_uint32 index, rtk_uint32* pType, ipaddr_t* pUpperIp, ipaddr_t* pLowerIp);\nextern ret_t rtl8367c_setAsicAclGpioPolarity(rtk_uint32 polarity);\nextern ret_t rtl8367c_getAsicAclGpioPolarity(rtk_uint32* pPolarity);\n\n#endif /*_RTL8367C_ASICDRV_ACL_H_*/\n\n\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtl8367c_asicdrv_cputag.h",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * $Revision: 76306 $\n * $Date: 2017-03-08 15:13:58 +0800 (gT, 08 T 2017) $\n *\n * Purpose : RTL8367C switch high-level API for RTL8367C\n * Feature : Proprietary CPU-tag related function drivers\n *\n */\n\n#ifndef _RTL8367C_ASICDRV_CPUTAG_H_\n#define _RTL8367C_ASICDRV_CPUTAG_H_\n\n#include <rtl8367c_asicdrv.h>\n\nenum CPUTAG_INSERT_MODE\n{\n    CPUTAG_INSERT_TO_ALL = 0,\n    CPUTAG_INSERT_TO_TRAPPING,\n    CPUTAG_INSERT_TO_NO,\n    CPUTAG_INSERT_END\n};\n\nextern ret_t rtl8367c_setAsicCputagEnable(rtk_uint32 enabled);\nextern ret_t rtl8367c_getAsicCputagEnable(rtk_uint32 *pEnabled);\nextern ret_t rtl8367c_setAsicCputagTrapPort(rtk_uint32 port);\nextern ret_t rtl8367c_getAsicCputagTrapPort(rtk_uint32 *pPort);\nextern ret_t rtl8367c_setAsicCputagPortmask(rtk_uint32 portmask);\nextern ret_t rtl8367c_getAsicCputagPortmask(rtk_uint32 *pPmsk);\nextern ret_t rtl8367c_setAsicCputagInsertMode(rtk_uint32 mode);\nextern ret_t rtl8367c_getAsicCputagInsertMode(rtk_uint32 *pMode);\nextern ret_t rtl8367c_setAsicCputagPriorityRemapping(rtk_uint32 srcPri, rtk_uint32 newPri);\nextern ret_t rtl8367c_getAsicCputagPriorityRemapping(rtk_uint32 srcPri, rtk_uint32 *pNewPri);\nextern ret_t rtl8367c_setAsicCputagPosition(rtk_uint32 postion);\nextern ret_t rtl8367c_getAsicCputagPosition(rtk_uint32* pPostion);\nextern ret_t rtl8367c_setAsicCputagMode(rtk_uint32 mode);\nextern ret_t rtl8367c_getAsicCputagMode(rtk_uint32 *pMode);\nextern ret_t rtl8367c_setAsicCputagRxMinLength(rtk_uint32 mode);\nextern ret_t rtl8367c_getAsicCputagRxMinLength(rtk_uint32 *pMode);\n\n#endif /*#ifndef _RTL8367C_ASICDRV_CPUTAG_H_*/\n\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtl8367c_asicdrv_dot1x.h",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * $Revision: 76306 $\n * $Date: 2017-03-08 15:13:58 +0800 (gT, 08 T 2017) $\n *\n * Purpose : RTL8367C switch high-level API for RTL8367C\n * Feature : 802.1X related functions\n *\n */\n\n#ifndef _RTL8367C_ASICDRV_DOT1X_H_\n#define _RTL8367C_ASICDRV_DOT1X_H_\n\n#include <rtl8367c_asicdrv.h>\n\nenum DOT1X_UNAUTH_BEHAV\n{\n    DOT1X_UNAUTH_DROP = 0,\n    DOT1X_UNAUTH_TRAP,\n    DOT1X_UNAUTH_GVLAN,\n    DOT1X_UNAUTH_END\n};\n\nextern ret_t rtl8367c_setAsic1xPBEnConfig(rtk_uint32 port, rtk_uint32 enabled);\nextern ret_t rtl8367c_getAsic1xPBEnConfig(rtk_uint32 port, rtk_uint32 *pEnabled);\nextern ret_t rtl8367c_setAsic1xPBAuthConfig(rtk_uint32 port, rtk_uint32 auth);\nextern ret_t rtl8367c_getAsic1xPBAuthConfig(rtk_uint32 port, rtk_uint32 *pAuth);\nextern ret_t rtl8367c_setAsic1xPBOpdirConfig(rtk_uint32 port, rtk_uint32 opdir);\nextern ret_t rtl8367c_getAsic1xPBOpdirConfig(rtk_uint32 port, rtk_uint32 *pOpdir);\nextern ret_t rtl8367c_setAsic1xMBEnConfig(rtk_uint32 port, rtk_uint32 enabled);\nextern ret_t rtl8367c_getAsic1xMBEnConfig(rtk_uint32 port, rtk_uint32 *pEnabled);\nextern ret_t rtl8367c_setAsic1xMBOpdirConfig(rtk_uint32 opdir);\nextern ret_t rtl8367c_getAsic1xMBOpdirConfig(rtk_uint32 *pOpdir);\nextern ret_t rtl8367c_setAsic1xProcConfig(rtk_uint32 port, rtk_uint32 proc);\nextern ret_t rtl8367c_getAsic1xProcConfig(rtk_uint32 port, rtk_uint32 *pProc);\nextern ret_t rtl8367c_setAsic1xGuestVidx(rtk_uint32 index);\nextern ret_t rtl8367c_getAsic1xGuestVidx(rtk_uint32 *pIndex);\nextern ret_t rtl8367c_setAsic1xGVOpdir(rtk_uint32 enabled);\nextern ret_t rtl8367c_getAsic1xGVOpdir(rtk_uint32 *pEnabled);\nextern ret_t rtl8367c_setAsic1xTrapPriority(rtk_uint32 priority);\nextern ret_t rtl8367c_getAsic1xTrapPriority(rtk_uint32 *pPriority);\n\n\n#endif /*_RTL8367C_ASICDRV_DOT1X_H_*/\n\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtl8367c_asicdrv_eav.h",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * $Revision: 76306 $\n * $Date: 2017-03-08 15:13:58 +0800 (gT, 08 T 2017) $\n *\n * Purpose : RTL8367C switch high-level API for RTL8367C\n * Feature : Ethernet AV related functions\n *\n */\n\n#ifndef _RTL8367C_ASICDRV_EAV_H_\n#define _RTL8367C_ASICDRV_EAV_H_\n\n#include <rtl8367c_asicdrv.h>\n\ntypedef enum RTL8367C_PTP_TIME_CMD_E\n{\n    PTP_TIME_READ = 0,\n    PTP_TIME_WRITE,\n    PTP_TIME_INC,\n    PTP_TIME_DEC,\n    PTP_TIME_CMD_END\n}RTL8367C_PTP_TIME_CMD;\n\ntypedef enum RTL8367C_PTP_TIME_ADJ_E\n{\n    PTP_TIME_ADJ_INC = 0,\n    PTP_TIME_ADJ_DEC,\n    PTP_TIME_ADJ_END\n}RTL8367C_PTP_TIME_ADJ;\n\ntypedef enum RTL8367C_PTP_TIME_CTRL_E\n{\n    PTP_TIME_CTRL_STOP = 0,\n    PTP_TIME_CTRL_START,\n    PTP_TIME_CTRL_END\n}RTL8367C_PTP_TIME_CTRL;\n\ntypedef enum RTL8367C_PTP_INTR_IMRS_E\n{\n    PTP_IMRS_TX_SYNC,\n    PTP_IMRS_TX_DELAY_REQ,\n    PTP_IMRS_TX_PDELAY_REQ,\n    PTP_IMRS_TX_PDELAY_RESP,\n    PTP_IMRS_RX_SYNC,\n    PTP_IMRS_RX_DELAY_REQ,\n    PTP_IMRS_RX_PDELAY_REQ,\n    PTP_IMRS_RX_PDELAY_RESP,\n    PTP_IMRS_END,\n}RTL8367C_PTP_INTR_IMRS;\n\n\ntypedef enum RTL8367C_PTP_PKT_TYPE_E\n{\n    PTP_PKT_TYPE_TX_SYNC,\n    PTP_PKT_TYPE_TX_DELAY_REQ,\n    PTP_PKT_TYPE_TX_PDELAY_REQ,\n    PTP_PKT_TYPE_TX_PDELAY_RESP,\n    PTP_PKT_TYPE_RX_SYNC,\n    PTP_PKT_TYPE_RX_DELAY_REQ,\n    PTP_PKT_TYPE_RX_PDELAY_REQ,\n    PTP_PKT_TYPE_RX_PDELAY_RESP,\n    PTP_PKT_TYPE_END,\n}RTL8367C_PTP_PKT_TYPE;\n\ntypedef struct  rtl8367c_ptp_time_stamp_s{\n    rtk_uint32 sequence_id;\n    rtk_uint32 second;\n    rtk_uint32 nano_second;\n}rtl8367c_ptp_time_stamp_t;\n\n#define RTL8367C_PTP_INTR_MASK        0xFF\n\n#define RTL8367C_PTP_PORT_MASK        0x3FF\n\nextern ret_t rtl8367c_setAsicEavMacAddress(ether_addr_t mac);\nextern ret_t rtl8367c_getAsicEavMacAddress(ether_addr_t *pMac);\nextern ret_t rtl8367c_setAsicEavTpid(rtk_uint32 outerTag, rtk_uint32 innerTag);\nextern ret_t rtl8367c_getAsicEavTpid(rtk_uint32* pOuterTag, rtk_uint32* pInnerTag);\nextern ret_t rtl8367c_setAsicEavSysTime(rtk_uint32 second, rtk_uint32 nanoSecond);\nextern ret_t rtl8367c_getAsicEavSysTime(rtk_uint32* pSecond, rtk_uint32* pNanoSecond);\nextern ret_t rtl8367c_setAsicEavSysTimeAdjust(rtk_uint32 type, rtk_uint32 second, rtk_uint32 nanoSecond);\nextern ret_t rtl8367c_setAsicEavSysTimeCtrl(rtk_uint32 control);\nextern ret_t rtl8367c_getAsicEavSysTimeCtrl(rtk_uint32* pControl);\nextern ret_t rtl8367c_setAsicEavInterruptMask(rtk_uint32 imr);\nextern ret_t rtl8367c_getAsicEavInterruptMask(rtk_uint32* pImr);\nextern ret_t rtl8367c_getAsicEavInterruptStatus(rtk_uint32* pIms);\nextern ret_t rtl8367c_setAsicEavPortInterruptStatus(rtk_uint32 port, rtk_uint32 ims);\nextern ret_t rtl8367c_getAsicEavPortInterruptStatus(rtk_uint32 port, rtk_uint32* pIms);\nextern ret_t rtl8367c_setAsicEavPortEnable(rtk_uint32 port, rtk_uint32 enabled);\nextern ret_t rtl8367c_getAsicEavPortEnable(rtk_uint32 port, rtk_uint32 *pEnabled);\nextern ret_t rtl8367c_getAsicEavPortTimeStamp(rtk_uint32 port, rtk_uint32 type, rtl8367c_ptp_time_stamp_t* timeStamp);\n\nextern ret_t rtl8367c_setAsicEavTrap(rtk_uint32 port, rtk_uint32 enabled);\nextern ret_t rtl8367c_getAsicEavTrap(rtk_uint32 port, rtk_uint32 *pEnabled);\nextern ret_t rtl8367c_setAsicEavEnable(rtk_uint32 port, rtk_uint32 enabled);\nextern ret_t rtl8367c_getAsicEavEnable(rtk_uint32 port, rtk_uint32 *pEnabled);\nextern ret_t rtl8367c_setAsicEavPriRemapping(rtk_uint32 srcpriority, rtk_uint32 priority);\nextern ret_t rtl8367c_getAsicEavPriRemapping(rtk_uint32 srcpriority, rtk_uint32 *pPriority);\n\n#endif /*#ifndef _RTL8367C_ASICDRV_EAV_H_*/\n\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtl8367c_asicdrv_eee.h",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * $Revision: 48989 $\n * $Date: 2014-07-01 15:45:24 +0800 (gG, 01 C 2014) $\n *\n * Purpose : RTL8370 switch high-level API for RTL8367C\n * Feature :\n *\n */\n\n#ifndef _RTL8367C_ASICDRV_EEE_H_\n#define _RTL8367C_ASICDRV_EEE_H_\n\n#include <rtl8367c_asicdrv.h>\n\n#define EEE_OCP_PHY_ADDR    (0xA5D0)\n\nextern ret_t rtl8367c_setAsicEee100M(rtk_uint32 port, rtk_uint32 enable);\nextern ret_t rtl8367c_getAsicEee100M(rtk_uint32 port, rtk_uint32 *enable);\nextern ret_t rtl8367c_setAsicEeeGiga(rtk_uint32 port, rtk_uint32 enable);\nextern ret_t rtl8367c_getAsicEeeGiga(rtk_uint32 port, rtk_uint32 *enable);\n\n\n#endif /*_RTL8367C_ASICDRV_EEE_H_*/\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtl8367c_asicdrv_fc.h",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * $Revision: 76306 $\n * $Date: 2017-03-08 15:13:58 +0800 (gT, 08 T 2017) $\n *\n * Purpose : RTL8367C switch high-level API for RTL8367C\n * Feature : Flow control related functions\n *\n */\n\n#ifndef _RTL8367C_ASICDRV_FC_H_\n#define _RTL8367C_ASICDRV_FC_H_\n\n#include <rtl8367c_asicdrv.h>\n\n#define RTL8367C_PAGE_NUMBER    0x600\n\n\nenum FLOW_CONTROL_TYPE\n{\n    FC_EGRESS = 0,\n    FC_INGRESS,\n};\n\nenum FC_JUMBO_SIZE\n{\n    FC_JUMBO_SIZE_3K = 0,\n    FC_JUMBO_SIZE_4K,\n    FC_JUMBO_SIZE_6K,\n    FC_JUMBO_SIZE_9K,\n    FC_JUMBO_SIZE_END,\n\n};\n\n\nextern ret_t rtl8367c_setAsicFlowControlSelect(rtk_uint32 select);\nextern ret_t rtl8367c_getAsicFlowControlSelect(rtk_uint32 *pSelect);\nextern ret_t rtl8367c_setAsicFlowControlJumboMode(rtk_uint32 enabled);\nextern ret_t rtl8367c_getAsicFlowControlJumboMode(rtk_uint32* pEnabled);\nextern ret_t rtl8367c_setAsicFlowControlJumboModeSize(rtk_uint32 size);\nextern ret_t rtl8367c_getAsicFlowControlJumboModeSize(rtk_uint32* pSize);\nextern ret_t rtl8367c_setAsicFlowControlQueueEgressEnable(rtk_uint32 port, rtk_uint32 qid, rtk_uint32 enabled);\nextern ret_t rtl8367c_getAsicFlowControlQueueEgressEnable(rtk_uint32 port, rtk_uint32 qid, rtk_uint32* pEnabled);\nextern ret_t rtl8367c_setAsicFlowControlDropAll(rtk_uint32 dropall);\nextern ret_t rtl8367c_getAsicFlowControlDropAll(rtk_uint32* pDropall);\nextern ret_t rtl8367c_setAsicFlowControlPauseAllThreshold(rtk_uint32 threshold);\nextern ret_t rtl8367c_getAsicFlowControlPauseAllThreshold(rtk_uint32 *pThreshold);\nextern ret_t rtl8367c_setAsicFlowControlSystemThreshold(rtk_uint32 onThreshold, rtk_uint32 offThreshold);\nextern ret_t rtl8367c_getAsicFlowControlSystemThreshold(rtk_uint32 *pOnThreshold, rtk_uint32 *pOffThreshold);\nextern ret_t rtl8367c_setAsicFlowControlSharedThreshold(rtk_uint32 onThreshold, rtk_uint32 offThreshold);\nextern ret_t rtl8367c_getAsicFlowControlSharedThreshold(rtk_uint32 *pOnThreshold, rtk_uint32 *pOffThreshold);\nextern ret_t rtl8367c_setAsicFlowControlPortThreshold(rtk_uint32 onThreshold, rtk_uint32 offThreshold);\nextern ret_t rtl8367c_getAsicFlowControlPortThreshold(rtk_uint32 *pOnThreshold, rtk_uint32 *pOffThreshold);\nextern ret_t rtl8367c_setAsicFlowControlPortPrivateThreshold(rtk_uint32 onThreshold, rtk_uint32 offThreshold);\nextern ret_t rtl8367c_getAsicFlowControlPortPrivateThreshold(rtk_uint32 *pOnThreshold, rtk_uint32 *pOffThreshold);\nextern ret_t rtl8367c_setAsicFlowControlSystemDropThreshold(rtk_uint32 onThreshold, rtk_uint32 offThreshold);\nextern ret_t rtl8367c_getAsicFlowControlSystemDropThreshold(rtk_uint32 *pOnThreshold, rtk_uint32 *pOffThreshold);\nextern ret_t rtl8367c_setAsicFlowControlSharedDropThreshold(rtk_uint32 onThreshold, rtk_uint32 offThreshold);\nextern ret_t rtl8367c_getAsicFlowControlSharedDropThreshold(rtk_uint32 *pOnThreshold, rtk_uint32 *pOffThreshold);\nextern ret_t rtl8367c_setAsicFlowControlPortDropThreshold(rtk_uint32 onThreshold, rtk_uint32 offThreshold);\nextern ret_t rtl8367c_getAsicFlowControlPortDropThreshold(rtk_uint32 *pOnThreshold, rtk_uint32 *pOffThreshold);\nextern ret_t rtl8367c_setAsicFlowControlPortPrivateDropThreshold(rtk_uint32 onThreshold, rtk_uint32 offThreshold);\nextern ret_t rtl8367c_getAsicFlowControlPortPrivateDropThreshold(rtk_uint32 *pOnThreshold, rtk_uint32 *pOffThreshold);\nextern ret_t rtl8367c_setAsicFlowControlSystemJumboThreshold(rtk_uint32 onThreshold, rtk_uint32 offThreshold);\nextern ret_t rtl8367c_getAsicFlowControlSystemJumboThreshold(rtk_uint32 *pOnThreshold, rtk_uint32 *pOffThreshold);\nextern ret_t rtl8367c_setAsicFlowControlSharedJumboThreshold(rtk_uint32 onThreshold, rtk_uint32 offThreshold);\nextern ret_t rtl8367c_getAsicFlowControlSharedJumboThreshold(rtk_uint32 *pOnThreshold, rtk_uint32 *pOffThreshold);\nextern ret_t rtl8367c_setAsicFlowControlPortJumboThreshold(rtk_uint32 onThreshold, rtk_uint32 offThreshold);\nextern ret_t rtl8367c_getAsicFlowControlPortJumboThreshold(rtk_uint32 *pOnThreshold, rtk_uint32 *pOffThreshold);\nextern ret_t rtl8367c_setAsicFlowControlPortPrivateJumboThreshold(rtk_uint32 onThreshold, rtk_uint32 offThreshold);\nextern ret_t rtl8367c_getAsicFlowControlPortPrivateJumboThreshold(rtk_uint32 *pOnThreshold, rtk_uint32 *pOffThreshold);\n\nextern ret_t rtl8367c_setAsicEgressFlowControlPortDropGap(rtk_uint32 gap);\nextern ret_t rtl8367c_getAsicEgressFlowControlPortDropGap(rtk_uint32 *pGap);\nextern ret_t rtl8367c_setAsicEgressFlowControlQueueDropGap(rtk_uint32 gap);\nextern ret_t rtl8367c_getAsicEgressFlowControlQueueDropGap(rtk_uint32 *pGap);\nextern ret_t rtl8367c_setAsicEgressFlowControlPortDropThreshold(rtk_uint32 port, rtk_uint32 threshold);\nextern ret_t rtl8367c_getAsicEgressFlowControlPortDropThreshold(rtk_uint32 port, rtk_uint32 *pThreshold);\nextern ret_t rtl8367c_setAsicEgressFlowControlQueueDropThreshold(rtk_uint32 qid, rtk_uint32 threshold);\nextern ret_t rtl8367c_getAsicEgressFlowControlQueueDropThreshold(rtk_uint32 qid, rtk_uint32 *pThreshold);\nextern ret_t rtl8367c_getAsicEgressQueueEmptyPortMask(rtk_uint32 *pPortmask);\nextern ret_t rtl8367c_getAsicTotalPage(rtk_uint32 *pPageCount);\nextern ret_t rtl8367c_getAsicPulbicPage(rtk_uint32 *pPageCount);\nextern ret_t rtl8367c_getAsicMaxTotalPage(rtk_uint32 *pPageCount);\nextern ret_t rtl8367c_getAsicMaxPulbicPage(rtk_uint32 *pPageCount);\nextern ret_t rtl8367c_getAsicPortPage(rtk_uint32 port, rtk_uint32 *pPageCount);\nextern ret_t rtl8367c_getAsicPortPageMax(rtk_uint32 port, rtk_uint32 *pPageCount);\nextern ret_t rtl8367c_setAsicFlowControlEgressPortIndep(rtk_uint32 port, rtk_uint32 enable);\nextern ret_t rtl8367c_getAsicFlowControlEgressPortIndep(rtk_uint32 port, rtk_uint32 *pEnable);\n\n#endif /*_RTL8367C_ASICDRV_FC_H_*/\n\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtl8367c_asicdrv_green.h",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * $Revision: 76306 $\n * $Date: 2017-03-08 15:13:58 +0800 (gT, 08 T 2017) $\n *\n * Purpose : RTL8367C switch high-level API for RTL8367C\n * Feature : Green ethernet related functions\n *\n */\n\n#ifndef _RTL8367C_ASICDRV_GREEN_H_\n#define _RTL8367C_ASICDRV_GREEN_H_\n\n#include <rtl8367c_asicdrv.h>\n#include <rtl8367c_asicdrv_phy.h>\n\n#define PHY_POWERSAVING_REG                         24\n\nextern ret_t rtl8367c_setAsicGreenTrafficType(rtk_uint32 priority, rtk_uint32 traffictype);\nextern ret_t rtl8367c_getAsicGreenTrafficType(rtk_uint32 priority, rtk_uint32* pTraffictype);\nextern ret_t rtl8367c_getAsicGreenPortPage(rtk_uint32 port, rtk_uint32* pPage);\nextern ret_t rtl8367c_getAsicGreenHighPriorityTraffic(rtk_uint32 port, rtk_uint32* pIndicator);\nextern ret_t rtl8367c_setAsicGreenHighPriorityTraffic(rtk_uint32 port);\nextern ret_t rtl8367c_setAsicGreenEthernet(rtk_uint32 port, rtk_uint32 green);\nextern ret_t rtl8367c_getAsicGreenEthernet(rtk_uint32 port, rtk_uint32* green);\nextern ret_t rtl8367c_setAsicPowerSaving(rtk_uint32 phy, rtk_uint32 enable);\nextern ret_t rtl8367c_getAsicPowerSaving(rtk_uint32 phy, rtk_uint32* enable);\n#endif /*#ifndef _RTL8367C_ASICDRV_GREEN_H_*/\n\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtl8367c_asicdrv_hsb.h",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * $Revision: 76306 $\n * $Date: 2017-03-08 15:13:58 +0800 (gT, 08 T 2017) $\n *\n * Purpose : RTL8367C switch high-level API for RTL8367C\n * Feature : Field selector related functions\n *\n */\n\n#ifndef _RTL8367C_ASICDRV__HSB_H_\n#define _RTL8367C_ASICDRV__HSB_H_\n\n#include <rtl8367c_asicdrv.h>\n\n#define RTL8367C_FIELDSEL_FORMAT_NUMBER      (16)\n#define RTL8367C_FIELDSEL_MAX_OFFSET         (255)\n\nenum FIELDSEL_FORMAT_FORMAT\n{\n    FIELDSEL_FORMAT_DEFAULT = 0,\n    FIELDSEL_FORMAT_RAW,\n    FIELDSEL_FORMAT_LLC,\n    FIELDSEL_FORMAT_IPV4,\n    FIELDSEL_FORMAT_ARP,\n    FIELDSEL_FORMAT_IPV6,\n    FIELDSEL_FORMAT_IPPAYLOAD,\n    FIELDSEL_FORMAT_L4PAYLOAD,\n    FIELDSEL_FORMAT_END\n};\n\nextern ret_t rtl8367c_setAsicFieldSelector(rtk_uint32 index, rtk_uint32 format, rtk_uint32 offset);\nextern ret_t rtl8367c_getAsicFieldSelector(rtk_uint32 index, rtk_uint32* pFormat, rtk_uint32* pOffset);\n\n#endif /*_RTL8367C_ASICDRV__HSB_H_*/\n\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtl8367c_asicdrv_i2c.h",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * $Revision: 38651 $\n * $Date: 2016-02-27 14:32:56 +0800 (PT, 17 | 2016) $\n *\n * Purpose : RTL8367C switch high-level API for RTL8367C\n * Feature : I2C related functions\n *\n */\n\n\n#ifndef _RTL8367C_ASICDRV_I2C_H_\n#define _RTL8367C_ASICDRV_I2C_H_\n#include <rtk_types.h>\n#include <rtl8367c_asicdrv.h>\n\n\n#define TIMEROUT_FOR_MICROSEMI (0x400)\n\n#define GPIO_INPUT 1\n#define GPIO_OUTPUT 2\n\nextern ret_t rtl8367c_setAsicI2C_checkBusIdle(void);\nextern ret_t rtl8367c_setAsicI2CStartCmd(void);\nextern ret_t rtl8367c_setAsicI2CStopCmd(void);\nextern ret_t rtl8367c_setAsicI2CTxOneCharCmd(rtk_uint8 oneChar);\nextern ret_t rtl8367c_setAsicI2CcheckRxAck(void);\nextern ret_t rtl8367c_setAsicI2CRxOneCharCmd(rtk_uint8 *pValue);\nextern ret_t rtl8367c_setAsicI2CTxAckCmd(void);\nextern ret_t rtl8367c_setAsicI2CTxNoAckCmd(void);\nextern ret_t rtl8367c_setAsicI2CSoftRSTseqCmd(void);\nextern ret_t rtl8367c_setAsicI2CGpioPinGroup(rtk_uint32 pinGroup_ID);\nextern ret_t rtl8367c_getAsicI2CGpioPinGroup(rtk_uint32 * pPinGroup_ID);\n\n\n\n\n\n#endif /*#ifndef _RTL8367C_ASICDRV_I2C_H_*/\n\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtl8367c_asicdrv_igmp.h",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * $Revision: 76306 $\n * $Date: 2017-03-08 15:13:58 +0800 (週三, 08 三月 2017) $\n *\n * Purpose : RTL8367C switch high-level API for RTL8367C\n * Feature : IGMP related functions\n *\n */\n\n#ifndef _RTL8367C_ASICDRV_IGMP_H_\n#define _RTL8367C_ASICDRV_IGMP_H_\n\n/****************************************************************/\n/* Header File inclusion                                        */\n/****************************************************************/\n#include <rtl8367c_asicdrv.h>\n\n#define RTL8367C_MAX_LEAVE_TIMER        (7)\n#define RTL8367C_MAX_QUERY_INT          (0xFFFF)\n#define RTL8367C_MAX_ROB_VAR            (7)\n\n#define RTL8367C_IGMP_GOUP_NO           (256)\n#define RTL8367C_IGMP_MAX_GOUP          (0xFF)\n#define RTL8367C_IGMP_GRP_BLEN          (3)\n#define RTL8367C_ROUTER_PORT_INVALID    (0xF)\n\nenum RTL8367C_IGMPTABLE_FULL_OP\n{\n    TABLE_FULL_FORWARD = 0,\n    TABLE_FULL_DROP,\n    TABLE_FULL_TRAP,\n    TABLE_FULL_OP_END\n};\n\nenum RTL8367C_CRC_ERR_OP\n{\n    CRC_ERR_DROP = 0,\n    CRC_ERR_TRAP,\n    CRC_ERR_FORWARD,\n    CRC_ERR_OP_END\n};\n\nenum RTL8367C_IGMP_MLD_PROTOCOL_OP\n{\n    PROTOCOL_OP_ASIC = 0,\n    PROTOCOL_OP_FLOOD,\n    PROTOCOL_OP_TRAP,\n    PROTOCOL_OP_DROP,\n    PROTOCOL_OP_END\n};\n\nenum RTL8367C_IGMP_MLD_BYPASS_GROUP\n{\n    BYPASS_224_0_0_X = 0,\n    BYPASS_224_0_1_X,\n    BYPASS_239_255_255_X,\n    BYPASS_IPV6_00XX,\n    BYPASS_GROUP_END\n};\n\ntypedef struct\n{\n    rtk_uint32 p0_timer;\n    rtk_uint32 p1_timer;\n    rtk_uint32 p2_timer;\n    rtk_uint32 p3_timer;\n    rtk_uint32 p4_timer;\n    rtk_uint32 p5_timer;\n    rtk_uint32 p6_timer;\n    rtk_uint32 p7_timer;\n    rtk_uint32 p8_timer;\n    rtk_uint32 p9_timer;\n    rtk_uint32 p10_timer;\n    rtk_uint32 report_supp_flag;\n\n}rtl8367c_igmpgroup;\n/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * This program is the proprietary software of Realtek Semiconductor\n * Corporation and/or its licensors, and only be used, duplicated,\n * modified or distributed under the authorized license from Realtek.\n *\n * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER\n * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED.\n *\n * $Revision: 76306 $\n * $Date: 2017-03-08 15:13:58 +0800 (週三, 08 三月 2017) $\n *\n * Purpose : RTL8367C switch high-level API for RTL8367C\n * Feature : IGMP related functions\n *\n */\n#include <rtl8367c_asicdrv_igmp.h>\n\nret_t rtl8367c_setAsicIgmp(rtk_uint32 enabled);\nret_t rtl8367c_getAsicIgmp(rtk_uint32 *pEnabled);\nret_t rtl8367c_setAsicIpMulticastVlanLeaky(rtk_uint32 port, rtk_uint32 enabled );\nret_t rtl8367c_getAsicIpMulticastVlanLeaky(rtk_uint32 port, rtk_uint32 *pEnabled );\nret_t rtl8367c_setAsicIGMPTableFullOP(rtk_uint32 operation);\nret_t rtl8367c_getAsicIGMPTableFullOP(rtk_uint32 *pOperation);\nret_t rtl8367c_setAsicIGMPCRCErrOP(rtk_uint32 operation);\nret_t rtl8367c_getAsicIGMPCRCErrOP(rtk_uint32 *pOperation);\nret_t rtl8367c_setAsicIGMPFastLeaveEn(rtk_uint32 enabled);\nret_t rtl8367c_getAsicIGMPFastLeaveEn(rtk_uint32 *pEnabled);\nret_t rtl8367c_setAsicIGMPLeaveTimer(rtk_uint32 leave_timer);\nret_t rtl8367c_getAsicIGMPLeaveTimer(rtk_uint32 *pLeave_timer);\nret_t rtl8367c_setAsicIGMPQueryInterval(rtk_uint32 interval);\nret_t rtl8367c_getAsicIGMPQueryInterval(rtk_uint32 *pInterval);\nret_t rtl8367c_setAsicIGMPRobVar(rtk_uint32 rob_var);\nret_t rtl8367c_getAsicIGMPRobVar(rtk_uint32 *pRob_var);\nret_t rtl8367c_setAsicIGMPStaticRouterPort(rtk_uint32 pmsk);\nret_t rtl8367c_getAsicIGMPStaticRouterPort(rtk_uint32 *pMsk);\nret_t rtl8367c_setAsicIGMPAllowDynamicRouterPort(rtk_uint32 pmsk);\nret_t rtl8367c_getAsicIGMPAllowDynamicRouterPort(rtk_uint32 *pPmsk);\nret_t rtl8367c_getAsicIGMPdynamicRouterPort1(rtk_uint32 *pPort, rtk_uint32 *pTimer);\nret_t rtl8367c_getAsicIGMPdynamicRouterPort2(rtk_uint32 *pPort, rtk_uint32 *pTimer);\nret_t rtl8367c_setAsicIGMPSuppression(rtk_uint32 report_supp_enabled, rtk_uint32 leave_supp_enabled);\nret_t rtl8367c_getAsicIGMPSuppression(rtk_uint32 *pReport_supp_enabled, rtk_uint32 *pLeave_supp_enabled);\nret_t rtl8367c_setAsicIGMPQueryRX(rtk_uint32 port, rtk_uint32 allow_query);\nret_t rtl8367c_getAsicIGMPQueryRX(rtk_uint32 port, rtk_uint32 *pAllow_query);\nret_t rtl8367c_setAsicIGMPReportRX(rtk_uint32 port, rtk_uint32 allow_report);\nret_t rtl8367c_getAsicIGMPReportRX(rtk_uint32 port, rtk_uint32 *pAllow_report);\nret_t rtl8367c_setAsicIGMPLeaveRX(rtk_uint32 port, rtk_uint32 allow_leave);\nret_t rtl8367c_getAsicIGMPLeaveRX(rtk_uint32 port, rtk_uint32 *pAllow_leave);\nret_t rtl8367c_setAsicIGMPMRPRX(rtk_uint32 port, rtk_uint32 allow_mrp);\nret_t rtl8367c_getAsicIGMPMRPRX(rtk_uint32 port, rtk_uint32 *pAllow_mrp);\nret_t rtl8367c_setAsicIGMPMcDataRX(rtk_uint32 port, rtk_uint32 allow_mcdata);\nret_t rtl8367c_getAsicIGMPMcDataRX(rtk_uint32 port, rtk_uint32 *pAllow_mcdata);\nret_t rtl8367c_setAsicIGMPv1Opeartion(rtk_uint32 port, rtk_uint32 igmpv1_op);\nret_t rtl8367c_getAsicIGMPv1Opeartion(rtk_uint32 port, rtk_uint32 *pIgmpv1_op);\nret_t rtl8367c_setAsicIGMPv2Opeartion(rtk_uint32 port, rtk_uint32 igmpv2_op);\nret_t rtl8367c_getAsicIGMPv2Opeartion(rtk_uint32 port, rtk_uint32 *pIgmpv2_op);\nret_t rtl8367c_setAsicIGMPv3Opeartion(rtk_uint32 port, rtk_uint32 igmpv3_op);\nret_t rtl8367c_getAsicIGMPv3Opeartion(rtk_uint32 port, rtk_uint32 *pIgmpv3_op);\nret_t rtl8367c_setAsicMLDv1Opeartion(rtk_uint32 port, rtk_uint32 mldv1_op);\nret_t rtl8367c_getAsicMLDv1Opeartion(rtk_uint32 port, rtk_uint32 *pMldv1_op);\nret_t rtl8367c_setAsicMLDv2Opeartion(rtk_uint32 port, rtk_uint32 mldv2_op);\nret_t rtl8367c_getAsicMLDv2Opeartion(rtk_uint32 port, rtk_uint32 *pMldv2_op);\nret_t rtl8367c_setAsicIGMPPortMAXGroup(rtk_uint32 port, rtk_uint32 max_group);\nret_t rtl8367c_getAsicIGMPPortMAXGroup(rtk_uint32 port, rtk_uint32 *pMax_group);\nret_t rtl8367c_getAsicIGMPPortCurrentGroup(rtk_uint32 port, rtk_uint32 *pCurrent_group);\nret_t rtl8367c_getAsicIGMPGroup(rtk_uint32 idx, rtk_uint32 *pValid, rtl8367c_igmpgroup *pGrp);\nret_t rtl8367c_setAsicIpMulticastPortIsoLeaky(rtk_uint32 port, rtk_uint32 enabled);\nret_t rtl8367c_getAsicIpMulticastPortIsoLeaky(rtk_uint32 port, rtk_uint32 *pEnabled);\nret_t rtl8367c_setAsicIGMPReportLeaveFlood(rtk_uint32 flood);\nret_t rtl8367c_getAsicIGMPReportLeaveFlood(rtk_uint32 *pFlood);\nret_t rtl8367c_setAsicIGMPDropLeaveZero(rtk_uint32 drop);\nret_t rtl8367c_getAsicIGMPDropLeaveZero(rtk_uint32 *pDrop);\nret_t rtl8367c_setAsicIGMPBypassStormCTRL(rtk_uint32 bypass);\nret_t rtl8367c_getAsicIGMPBypassStormCTRL(rtk_uint32 *pBypass);\nret_t rtl8367c_setAsicIGMPIsoLeaky(rtk_uint32 leaky);\nret_t rtl8367c_getAsicIGMPIsoLeaky(rtk_uint32 *pLeaky);\nret_t rtl8367c_setAsicIGMPVLANLeaky(rtk_uint32 leaky);\nret_t rtl8367c_getAsicIGMPVLANLeaky(rtk_uint32 *pLeaky);\nret_t rtl8367c_setAsicIGMPBypassGroup(rtk_uint32 bypassType, rtk_uint32 enabled);\nret_t rtl8367c_getAsicIGMPBypassGroup(rtk_uint32 bypassType, rtk_uint32 *pEnabled);\n\n#endif /*#ifndef _RTL8367C_ASICDRV_IGMP_H_*/\n\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtl8367c_asicdrv_inbwctrl.h",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * $Revision: 76306 $\n * $Date: 2017-03-08 15:13:58 +0800 (gT, 08 T 2017) $\n *\n * Purpose : RTL8367C switch high-level API for RTL8367C\n * Feature : Ingress bandwidth control related functions\n *\n */\n\n#ifndef _RTL8367C_ASICDRV_INBWCTRL_H_\n#define _RTL8367C_ASICDRV_INBWCTRL_H_\n\n#include <rtl8367c_asicdrv.h>\n\nextern ret_t rtl8367c_setAsicPortIngressBandwidth(rtk_uint32 port, rtk_uint32 bandwidth, rtk_uint32 preifg, rtk_uint32 enableFC);\nextern ret_t rtl8367c_getAsicPortIngressBandwidth(rtk_uint32 port, rtk_uint32* pBandwidth, rtk_uint32* pPreifg, rtk_uint32* pEnableFC );\nextern ret_t rtl8367c_setAsicPortIngressBandwidthBypass(rtk_uint32 enabled);\nextern ret_t rtl8367c_getAsicPortIngressBandwidthBypass(rtk_uint32* pEnabled);\n\n\n#endif /*_RTL8367C_ASICDRV_INBWCTRL_H_*/\n\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtl8367c_asicdrv_interrupt.h",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * $Revision: 76306 $\n * $Date: 2017-03-08 15:13:58 +0800 (gT, 08 T 2017) $\n *\n * Purpose : RTL8367C switch high-level API for RTL8367C\n * Feature : Interrupt related functions\n *\n */\n\n#ifndef _RTL8367C_ASICDRV_INTERRUPT_H_\n#define _RTL8367C_ASICDRV_INTERRUPT_H_\n\n#include <rtl8367c_asicdrv.h>\n\ntypedef enum RTL8367C_INTR_IMRS_E\n{\n    IMRS_LINK_CHANGE,\n    IMRS_METER_EXCEED,\n    IMRS_L2_LEARN,\n    IMRS_SPEED_CHANGE,\n    IMRS_SPECIAL_CONGESTION,\n    IMRS_GREEN_FEATURE,\n    IMRS_LOOP_DETECTION,\n    IMRS_8051,\n    IMRS_CABLE_DIAG,\n    IMRS_ACL,\n    IMRS_RESERVED, /* Unused */\n    IMRS_SLIENT,\n    IMRS_END,\n}RTL8367C_INTR_IMRS;\n\ntypedef enum RTL8367C_INTR_INDICATOR_E\n{\n    INTRST_L2_LEARN = 0,\n    INTRST_SPEED_CHANGE,\n    INTRST_SPECIAL_CONGESTION,\n    INTRST_PORT_LINKDOWN,\n    INTRST_PORT_LINKUP,\n    INTRST_METER0_15,\n    INTRST_METER16_31,\n    INTRST_RLDP_LOOPED,\n    INTRST_RLDP_RELEASED,\n    INTRST_SYS_LEARN,\n    INTRST_END,\n}RTL8367C_INTR_INDICATOR;\n\nextern ret_t rtl8367c_setAsicInterruptPolarity(rtk_uint32 polarity);\nextern ret_t rtl8367c_getAsicInterruptPolarity(rtk_uint32* pPolarity);\nextern ret_t rtl8367c_setAsicInterruptMask(rtk_uint32 imr);\nextern ret_t rtl8367c_getAsicInterruptMask(rtk_uint32* pImr);\nextern ret_t rtl8367c_setAsicInterruptStatus(rtk_uint32 ims);\nextern ret_t rtl8367c_getAsicInterruptStatus(rtk_uint32* pIms);\nextern ret_t rtl8367c_setAsicInterruptRelatedStatus(rtk_uint32 type, rtk_uint32 status);\nextern ret_t rtl8367c_getAsicInterruptRelatedStatus(rtk_uint32 type, rtk_uint32* pStatus);\n\n\n#endif /*#ifndef _RTL8367C_ASICDRV_INTERRUPT_H_*/\n\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtl8367c_asicdrv_led.h",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * $Revision: 76306 $\n * $Date: 2017-03-08 15:13:58 +0800 (gT, 08 T 2017) $\n *\n * Purpose : RTL8367C switch high-level API for RTL8367C\n * Feature : LED related functions\n *\n */\n\n#ifndef _RTL8367C_ASICDRV_LED_H_\n#define _RTL8367C_ASICDRV_LED_H_\n\n#include <rtl8367c_asicdrv.h>\n\n#define RTL8367C_LEDGROUPNO                 3\n#define RTL8367C_LEDGROUPMASK               0x7\n#define RTL8367C_LED_FORCE_MODE_BASE        RTL8367C_REG_CPU_FORCE_LED0_CFG0\n#define RTL8367C_LED_FORCE_CTRL             RTL8367C_REG_CPU_FORCE_LED_CFG\n\nenum RTL8367C_LEDOP{\n\n    LEDOP_SCAN0=0,\n    LEDOP_SCAN1,\n    LEDOP_PARALLEL,\n    LEDOP_SERIAL,\n    LEDOP_END,\n};\n\nenum RTL8367C_LEDSERACT{\n\n    LEDSERACT_HIGH=0,\n    LEDSERACT_LOW,\n    LEDSERACT_MAX,\n};\n\nenum RTL8367C_LEDSER{\n\n    LEDSER_16G=0,\n    LEDSER_8G,\n    LEDSER_MAX,\n};\n\nenum RTL8367C_LEDCONF{\n\n    LEDCONF_LEDOFF=0,\n    LEDCONF_DUPCOL,\n    LEDCONF_LINK_ACT,\n    LEDCONF_SPD1000,\n    LEDCONF_SPD100,\n    LEDCONF_SPD10,\n    LEDCONF_SPD1000ACT,\n    LEDCONF_SPD100ACT,\n    LEDCONF_SPD10ACT,\n    LEDCONF_SPD10010ACT,\n    LEDCONF_LOOPDETECT,\n    LEDCONF_EEE,\n    LEDCONF_LINKRX,\n    LEDCONF_LINKTX,\n    LEDCONF_MASTER,\n    LEDCONF_ACT,\n    LEDCONF_END\n};\n\nenum RTL8367C_LEDBLINKRATE{\n\n    LEDBLINKRATE_32MS=0,\n    LEDBLINKRATE_64MS,\n    LEDBLINKRATE_128MS,\n    LEDBLINKRATE_256MS,\n    LEDBLINKRATE_512MS,\n    LEDBLINKRATE_1024MS,\n    LEDBLINKRATE_48MS,\n    LEDBLINKRATE_96MS,\n    LEDBLINKRATE_END,\n};\n\nenum RTL8367C_LEDFORCEMODE{\n\n    LEDFORCEMODE_NORMAL=0,\n    LEDFORCEMODE_BLINK,\n    LEDFORCEMODE_OFF,\n    LEDFORCEMODE_ON,\n    LEDFORCEMODE_END,\n};\n\nenum RTL8367C_LEDFORCERATE{\n\n    LEDFORCERATE_512MS=0,\n    LEDFORCERATE_1024MS,\n    LEDFORCERATE_2048MS,\n    LEDFORCERATE_NORMAL,\n    LEDFORCERATE_END,\n\n};\n\nenum RTL8367C_LEDMODE\n{\n    RTL8367C_LED_MODE_0 = 0,\n    RTL8367C_LED_MODE_1,\n    RTL8367C_LED_MODE_2,\n    RTL8367C_LED_MODE_3,\n    RTL8367C_LED_MODE_END\n};\n\nextern ret_t rtl8367c_setAsicLedIndicateInfoConfig(rtk_uint32 ledno, rtk_uint32 config);\nextern ret_t rtl8367c_getAsicLedIndicateInfoConfig(rtk_uint32 ledno, rtk_uint32* pConfig);\nextern ret_t rtl8367c_setAsicForceLed(rtk_uint32 port, rtk_uint32 group, rtk_uint32 mode);\nextern ret_t rtl8367c_getAsicForceLed(rtk_uint32 port, rtk_uint32 group, rtk_uint32* pMode);\nextern ret_t rtl8367c_setAsicForceGroupLed(rtk_uint32 groupmask, rtk_uint32 mode);\nextern ret_t rtl8367c_getAsicForceGroupLed(rtk_uint32* groupmask, rtk_uint32* pMode);\nextern ret_t rtl8367c_setAsicLedBlinkRate(rtk_uint32 blinkRate);\nextern ret_t rtl8367c_getAsicLedBlinkRate(rtk_uint32* pBlinkRate);\nextern ret_t rtl8367c_setAsicLedForceBlinkRate(rtk_uint32 blinkRate);\nextern ret_t rtl8367c_getAsicLedForceBlinkRate(rtk_uint32* pBlinkRate);\nextern ret_t rtl8367c_setAsicLedGroupMode(rtk_uint32 mode);\nextern ret_t rtl8367c_getAsicLedGroupMode(rtk_uint32* pMode);\nextern ret_t rtl8367c_setAsicLedGroupEnable(rtk_uint32 group, rtk_uint32 portmask);\nextern ret_t rtl8367c_getAsicLedGroupEnable(rtk_uint32 group, rtk_uint32 *portmask);\nextern ret_t rtl8367c_setAsicLedOperationMode(rtk_uint32 mode);\nextern ret_t rtl8367c_getAsicLedOperationMode(rtk_uint32 *mode);\nextern ret_t rtl8367c_setAsicLedSerialModeConfig(rtk_uint32 active, rtk_uint32 serimode);\nextern ret_t rtl8367c_getAsicLedSerialModeConfig(rtk_uint32 *active, rtk_uint32 *serimode);\nextern ret_t rtl8367c_setAsicLedOutputEnable(rtk_uint32 enabled);\nextern ret_t rtl8367c_getAsicLedOutputEnable(rtk_uint32 *ptr_enabled);\nextern ret_t rtl8367c_setAsicLedSerialOutput(rtk_uint32 output, rtk_uint32 pmask);\nextern ret_t rtl8367c_getAsicLedSerialOutput(rtk_uint32 *pOutput, rtk_uint32 *pPmask);\n\n\n#endif /*#ifndef _RTL8367C_ASICDRV_LED_H_*/\n\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtl8367c_asicdrv_lut.h",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * $Revision: 76306 $\n * $Date: 2017-03-08 15:13:58 +0800 (gT, 08 T 2017) $\n *\n * Purpose : RTL8367C switch high-level API for RTL8367C\n * Feature : LUT related functions\n *\n */\n\n\n#ifndef _RTL8367C_ASICDRV_LUT_H_\n#define _RTL8367C_ASICDRV_LUT_H_\n\n#include <rtl8367c_asicdrv.h>\n\n#define RTL8367C_LUT_AGETIMERMAX        (7)\n#define RTL8367C_LUT_AGESPEEDMAX        (3)\n#define RTL8367C_LUT_LEARNLIMITMAX      (0x1040)\n#define RTL8367C_LUT_ADDRMAX            (0x103F)\n#define RTL8367C_LUT_IPMCGRP_TABLE_MAX  (0x3F)\n#define RTL8367C_LUT_ENTRY_SIZE         (6)\n#define RTL8367C_LUT_BUSY_CHECK_NO      (10)\n\n#define RTL8367C_LUT_TABLE_SIZE         (6)\n\nenum RTL8367C_LUTHASHMETHOD{\n\n    LUTHASHMETHOD_SVL=0,\n    LUTHASHMETHOD_IVL,\n    LUTHASHMETHOD_END,\n};\n\n\nenum RTL8367C_LRNOVERACT{\n\n    LRNOVERACT_FORWARD=0,\n    LRNOVERACT_DROP,\n    LRNOVERACT_TRAP,\n    LRNOVERACT_END,\n};\n\nenum RTL8367C_LUTREADMETHOD{\n\n    LUTREADMETHOD_MAC =0,\n    LUTREADMETHOD_ADDRESS,\n    LUTREADMETHOD_NEXT_ADDRESS,\n    LUTREADMETHOD_NEXT_L2UC,\n    LUTREADMETHOD_NEXT_L2MC,\n    LUTREADMETHOD_NEXT_L3MC,\n    LUTREADMETHOD_NEXT_L2L3MC,\n    LUTREADMETHOD_NEXT_L2UCSPA,\n};\n\nenum RTL8367C_FLUSHMODE\n{\n    FLUSHMDOE_PORT = 0,\n    FLUSHMDOE_VID,\n    FLUSHMDOE_FID,\n    FLUSHMDOE_END,\n};\n\nenum RTL8367C_FLUSHTYPE\n{\n    FLUSHTYPE_DYNAMIC = 0,\n    FLUSHTYPE_BOTH,\n    FLUSHTYPE_END,\n};\n\n\ntypedef struct LUTTABLE{\n\n    ipaddr_t sip;\n    ipaddr_t dip;\n    ether_addr_t mac;\n    rtk_uint16 ivl_svl:1;\n    rtk_uint16 cvid_fid:12;\n    rtk_uint16 fid:4;\n    rtk_uint16 efid:3;\n\n    rtk_uint16 nosalearn:1;\n    rtk_uint16 da_block:1;\n    rtk_uint16 sa_block:1;\n    rtk_uint16 auth:1;\n    rtk_uint16 lut_pri:3;\n    rtk_uint16 sa_en:1;\n    rtk_uint16 fwd_en:1;\n    rtk_uint16 mbr:11;\n    rtk_uint16 spa:4;\n    rtk_uint16 age:3;\n    rtk_uint16 l3lookup:1;\n    rtk_uint16 igmp_asic:1;\n    rtk_uint16 igmpidx:8;\n\n    rtk_uint16 lookup_hit:1;\n    rtk_uint16 lookup_busy:1;\n    rtk_uint16 address:13;\n\n    rtk_uint16 l3vidlookup:1;\n    rtk_uint16 l3_vid:12;\n\n    rtk_uint16 wait_time;\n\n}rtl8367c_luttb;\n\nextern ret_t rtl8367c_setAsicLutIpMulticastLookup(rtk_uint32 enabled);\nextern ret_t rtl8367c_getAsicLutIpMulticastLookup(rtk_uint32* pEnabled);\nextern ret_t rtl8367c_setAsicLutIpMulticastVidLookup(rtk_uint32 enabled);\nextern ret_t rtl8367c_getAsicLutIpMulticastVidLookup(rtk_uint32* pEnabled);\nextern ret_t rtl8367c_setAsicLutAgeTimerSpeed(rtk_uint32 timer, rtk_uint32 speed);\nextern ret_t rtl8367c_getAsicLutAgeTimerSpeed(rtk_uint32* pTimer, rtk_uint32* pSpeed);\nextern ret_t rtl8367c_setAsicLutCamTbUsage(rtk_uint32 enabled);\nextern ret_t rtl8367c_getAsicLutCamTbUsage(rtk_uint32* pEnabled);\nextern ret_t rtl8367c_getAsicLutCamType(rtk_uint32* pType);\nextern ret_t rtl8367c_setAsicLutLearnLimitNo(rtk_uint32 port, rtk_uint32 number);\nextern ret_t rtl8367c_getAsicLutLearnLimitNo(rtk_uint32 port, rtk_uint32* pNumber);\nextern ret_t rtl8367c_setAsicSystemLutLearnLimitNo(rtk_uint32 number);\nextern ret_t rtl8367c_getAsicSystemLutLearnLimitNo(rtk_uint32 *pNumber);\nextern ret_t rtl8367c_setAsicLutLearnOverAct(rtk_uint32 action);\nextern ret_t rtl8367c_getAsicLutLearnOverAct(rtk_uint32* pAction);\nextern ret_t rtl8367c_setAsicSystemLutLearnOverAct(rtk_uint32 action);\nextern ret_t rtl8367c_getAsicSystemLutLearnOverAct(rtk_uint32 *pAction);\nextern ret_t rtl8367c_setAsicSystemLutLearnPortMask(rtk_uint32 portmask);\nextern ret_t rtl8367c_getAsicSystemLutLearnPortMask(rtk_uint32 *pPortmask);\nextern ret_t rtl8367c_setAsicL2LookupTb(rtl8367c_luttb *pL2Table);\nextern ret_t rtl8367c_getAsicL2LookupTb(rtk_uint32 method, rtl8367c_luttb *pL2Table);\nextern ret_t rtl8367c_getAsicLutLearnNo(rtk_uint32 port, rtk_uint32* pNumber);\nextern ret_t rtl8367c_setAsicLutIpLookupMethod(rtk_uint32 type);\nextern ret_t rtl8367c_getAsicLutIpLookupMethod(rtk_uint32* pType);\nextern ret_t rtl8367c_setAsicLutForceFlush(rtk_uint32 portmask);\nextern ret_t rtl8367c_getAsicLutForceFlushStatus(rtk_uint32 *pPortmask);\nextern ret_t rtl8367c_setAsicLutFlushMode(rtk_uint32 mode);\nextern ret_t rtl8367c_getAsicLutFlushMode(rtk_uint32* pMode);\nextern ret_t rtl8367c_setAsicLutFlushType(rtk_uint32 type);\nextern ret_t rtl8367c_getAsicLutFlushType(rtk_uint32* pType);\nextern ret_t rtl8367c_setAsicLutFlushVid(rtk_uint32 vid);\nextern ret_t rtl8367c_getAsicLutFlushVid(rtk_uint32* pVid);\nextern ret_t rtl8367c_setAsicLutFlushFid(rtk_uint32 fid);\nextern ret_t rtl8367c_getAsicLutFlushFid(rtk_uint32* pFid);\nextern ret_t rtl8367c_setAsicLutDisableAging(rtk_uint32 port, rtk_uint32 disabled);\nextern ret_t rtl8367c_getAsicLutDisableAging(rtk_uint32 port, rtk_uint32 *pDisabled);\nextern ret_t rtl8367c_setAsicLutIPMCGroup(rtk_uint32 index, ipaddr_t group_addr, rtk_uint32 vid, rtk_uint32 pmask, rtk_uint32 valid);\nextern ret_t rtl8367c_getAsicLutIPMCGroup(rtk_uint32 index, ipaddr_t *pGroup_addr, rtk_uint32 *pVid, rtk_uint32 *pPmask, rtk_uint32 *pValid);\nextern ret_t rtl8367c_setAsicLutLinkDownForceAging(rtk_uint32 enable);\nextern ret_t rtl8367c_getAsicLutLinkDownForceAging(rtk_uint32 *pEnable);\nextern ret_t rtl8367c_setAsicLutFlushAll(void);\nextern ret_t rtl8367c_getAsicLutFlushAllStatus(rtk_uint32 *pBusyStatus);\nextern ret_t rtl8367c_setAsicLutIpmcFwdRouterPort(rtk_uint32 enable);\nextern ret_t rtl8367c_getAsicLutIpmcFwdRouterPort(rtk_uint32 *pEnable);\n\n#endif /*_RTL8367C_ASICDRV_LUT_H_*/\n\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtl8367c_asicdrv_meter.h",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * $Revision: 76306 $\n * $Date: 2017-03-08 15:13:58 +0800 (gT, 08 T 2017) $\n *\n * Purpose : RTL8367C switch high-level API for RTL8367C\n * Feature : Shared meter related functions\n *\n */\n\n#ifndef _RTL8367C_ASICDRV_METER_H_\n#define _RTL8367C_ASICDRV_METER_H_\n\n#include <rtl8367c_asicdrv.h>\n\n\nextern ret_t rtl8367c_setAsicShareMeter(rtk_uint32 index, rtk_uint32 rate, rtk_uint32 ifg);\nextern ret_t rtl8367c_getAsicShareMeter(rtk_uint32 index, rtk_uint32 *pRate, rtk_uint32 *pIfg);\nextern ret_t rtl8367c_setAsicShareMeterBucketSize(rtk_uint32 index, rtk_uint32 lbThreshold);\nextern ret_t rtl8367c_getAsicShareMeterBucketSize(rtk_uint32 index, rtk_uint32 *pLbThreshold);\nextern ret_t rtl8367c_setAsicShareMeterType(rtk_uint32 index, rtk_uint32 type);\nextern ret_t rtl8367c_getAsicShareMeterType(rtk_uint32 index, rtk_uint32 *pType);\nextern ret_t rtl8367c_setAsicMeterExceedStatus(rtk_uint32 index);\nextern ret_t rtl8367c_getAsicMeterExceedStatus(rtk_uint32 index, rtk_uint32* pStatus);\n\n#endif /*_RTL8367C_ASICDRV_FC_H_*/\n\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtl8367c_asicdrv_mib.h",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * $Revision: 76306 $\n * $Date: 2017-03-08 15:13:58 +0800 (gT, 08 T 2017) $\n *\n * Purpose : RTL8367C switch high-level API for RTL8367C\n * Feature : MIB related functions\n *\n */\n\n#ifndef _RTL8367C_ASICDRV_MIB_H_\n#define _RTL8367C_ASICDRV_MIB_H_\n\n#include <rtl8367c_asicdrv.h>\n\n#define RTL8367C_MIB_PORT_OFFSET                (0x7C)\n#define RTL8367C_MIB_LEARNENTRYDISCARD_OFFSET   (0x420)\n\n#define RTL8367C_MAX_LOG_CNT_NUM                (32)\n#define RTL8367C_MIB_MAX_LOG_CNT_IDX            (RTL8367C_MAX_LOG_CNT_NUM - 1)\n#define RTL8367C_MIB_LOG_CNT_OFFSET             (0x3E0)\n#define RTL8367C_MIB_MAX_LOG_MODE_IDX           (16-1)\n\ntypedef enum RTL8367C_MIBCOUNTER_E{\n\n    /* RX */\n    ifInOctets = 0,\n\n    dot3StatsFCSErrors,\n    dot3StatsSymbolErrors,\n    dot3InPauseFrames,\n    dot3ControlInUnknownOpcodes,\n\n    etherStatsFragments,\n    etherStatsJabbers,\n    ifInUcastPkts,\n    etherStatsDropEvents,\n\n    ifInMulticastPkts,\n    ifInBroadcastPkts,\n    inMldChecksumError,\n    inIgmpChecksumError,\n    inMldSpecificQuery,\n    inMldGeneralQuery,\n    inIgmpSpecificQuery,\n    inIgmpGeneralQuery,\n    inMldLeaves,\n    inIgmpLeaves,\n\n    /* TX/RX */\n    etherStatsOctets,\n\n    etherStatsUnderSizePkts,\n    etherOversizeStats,\n    etherStatsPkts64Octets,\n    etherStatsPkts65to127Octets,\n    etherStatsPkts128to255Octets,\n    etherStatsPkts256to511Octets,\n    etherStatsPkts512to1023Octets,\n    etherStatsPkts1024to1518Octets,\n\n    /* TX */\n    ifOutOctets,\n\n    dot3StatsSingleCollisionFrames,\n    dot3StatMultipleCollisionFrames,\n    dot3sDeferredTransmissions,\n    dot3StatsLateCollisions,\n    etherStatsCollisions,\n    dot3StatsExcessiveCollisions,\n    dot3OutPauseFrames,\n    ifOutDiscards,\n\n    /* ALE */\n    dot1dTpPortInDiscards,\n    ifOutUcastPkts,\n    ifOutMulticastPkts,\n    ifOutBroadcastPkts,\n    outOampduPkts,\n    inOampduPkts,\n\n    inIgmpJoinsSuccess,\n    inIgmpJoinsFail,\n    inMldJoinsSuccess,\n    inMldJoinsFail,\n    inReportSuppressionDrop,\n    inLeaveSuppressionDrop,\n    outIgmpReports,\n    outIgmpLeaves,\n    outIgmpGeneralQuery,\n    outIgmpSpecificQuery,\n    outMldReports,\n    outMldLeaves,\n    outMldGeneralQuery,\n    outMldSpecificQuery,\n    inKnownMulticastPkts,\n\n    /*Device only */\n    dot1dTpLearnedEntryDiscards,\n    RTL8367C_MIBS_NUMBER,\n\n}RTL8367C_MIBCOUNTER;\n\n\nextern ret_t rtl8367c_setAsicMIBsCounterReset(rtk_uint32 greset, rtk_uint32 qmreset, rtk_uint32 pmask);\nextern ret_t rtl8367c_getAsicMIBsCounter(rtk_uint32 port,RTL8367C_MIBCOUNTER mibIdx, rtk_uint64* pCounter);\nextern ret_t rtl8367c_getAsicMIBsLogCounter(rtk_uint32 index, rtk_uint32 *pCounter);\nextern ret_t rtl8367c_getAsicMIBsControl(rtk_uint32* pMask);\n\nextern ret_t rtl8367c_setAsicMIBsResetValue(rtk_uint32 value);\nextern ret_t rtl8367c_getAsicMIBsResetValue(rtk_uint32* value);\n\nextern ret_t rtl8367c_setAsicMIBsUsageMode(rtk_uint32 mode);\nextern ret_t rtl8367c_getAsicMIBsUsageMode(rtk_uint32* pMode);\nextern ret_t rtl8367c_setAsicMIBsTimer(rtk_uint32 timer);\nextern ret_t rtl8367c_getAsicMIBsTimer(rtk_uint32* pTimer);\nextern ret_t rtl8367c_setAsicMIBsLoggingMode(rtk_uint32 index, rtk_uint32 mode);\nextern ret_t rtl8367c_getAsicMIBsLoggingMode(rtk_uint32 index, rtk_uint32* pMode);\nextern ret_t rtl8367c_setAsicMIBsLoggingType(rtk_uint32 index, rtk_uint32 type);\nextern ret_t rtl8367c_getAsicMIBsLoggingType(rtk_uint32 index, rtk_uint32* pType);\nextern ret_t rtl8367c_setAsicMIBsResetLoggingCounter(rtk_uint32 index);\nextern ret_t rtl8367c_setAsicMIBsLength(rtk_uint32 txLengthMode, rtk_uint32 rxLengthMode);\nextern ret_t rtl8367c_getAsicMIBsLength(rtk_uint32 *pTxLengthMode, rtk_uint32 *pRxLengthMode);\n\n#endif /*#ifndef _RTL8367C_ASICDRV_MIB_H_*/\n\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtl8367c_asicdrv_mirror.h",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * $Revision: 76306 $\n * $Date: 2017-03-08 15:13:58 +0800 (gT, 08 T 2017) $\n *\n * Purpose : RTL8367C switch high-level API for RTL8367C\n * Feature : Port mirror related functions\n *\n */\n\n#ifndef _RTL8367C_ASICDRV_MIRROR_H_\n#define _RTL8367C_ASICDRV_MIRROR_H_\n\n#include <rtl8367c_asicdrv.h>\n\nextern ret_t rtl8367c_setAsicPortMirror(rtk_uint32 source, rtk_uint32 monitor);\nextern ret_t rtl8367c_getAsicPortMirror(rtk_uint32 *pSource, rtk_uint32 *pMonitor);\nextern ret_t rtl8367c_setAsicPortMirrorRxFunction(rtk_uint32 enabled);\nextern ret_t rtl8367c_getAsicPortMirrorRxFunction(rtk_uint32* pEnabled);\nextern ret_t rtl8367c_setAsicPortMirrorTxFunction(rtk_uint32 enabled);\nextern ret_t rtl8367c_getAsicPortMirrorTxFunction(rtk_uint32* pEnabled);\nextern ret_t rtl8367c_setAsicPortMirrorIsolation(rtk_uint32 enabled);\nextern ret_t rtl8367c_getAsicPortMirrorIsolation(rtk_uint32* pEnabled);\nextern ret_t rtl8367c_setAsicPortMirrorPriority(rtk_uint32 priority);\nextern ret_t rtl8367c_getAsicPortMirrorPriority(rtk_uint32* pPriority);\nextern ret_t rtl8367c_setAsicPortMirrorMask(rtk_uint32 SourcePortmask);\nextern ret_t rtl8367c_getAsicPortMirrorMask(rtk_uint32 *pSourcePortmask);\nextern ret_t rtl8367c_setAsicPortMirrorVlanRxLeaky(rtk_uint32 enabled);\nextern ret_t rtl8367c_getAsicPortMirrorVlanRxLeaky(rtk_uint32* pEnabled);\nextern ret_t rtl8367c_setAsicPortMirrorVlanTxLeaky(rtk_uint32 enabled);\nextern ret_t rtl8367c_getAsicPortMirrorVlanTxLeaky(rtk_uint32* pEnabled);\nextern ret_t rtl8367c_setAsicPortMirrorIsolationRxLeaky(rtk_uint32 enabled);\nextern ret_t rtl8367c_getAsicPortMirrorIsolationRxLeaky(rtk_uint32* pEnabled);\nextern ret_t rtl8367c_setAsicPortMirrorIsolationTxLeaky(rtk_uint32 enabled);\nextern ret_t rtl8367c_getAsicPortMirrorIsolationTxLeaky(rtk_uint32* pEnabled);\nextern ret_t rtl8367c_setAsicPortMirrorRealKeep(rtk_uint32 mode);\nextern ret_t rtl8367c_getAsicPortMirrorRealKeep(rtk_uint32* pMode);\nextern ret_t rtl8367c_setAsicPortMirrorOverride(rtk_uint32 rxMirror, rtk_uint32 txMirror, rtk_uint32 aclMirror);\nextern ret_t rtl8367c_getAsicPortMirrorOverride(rtk_uint32 *pRxMirror, rtk_uint32 *pTxMirror, rtk_uint32 *pAclMirror);\n\n#endif /*#ifndef _RTL8367C_ASICDRV_MIRROR_H_*/\n\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtl8367c_asicdrv_misc.h",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * $Revision: 76306 $\n * $Date: 2017-03-08 15:13:58 +0800 (gT, 08 T 2017) $\n *\n * Purpose : RTL8367C switch high-level API for RTL8367C\n * Feature : Miscellaneous functions\n *\n */\n\n#ifndef _RTL8367C_ASICDRV_MISC_H_\n#define _RTL8367C_ASICDRV_MISC_H_\n\n#include <rtl8367c_asicdrv.h>\n\nextern ret_t rtl8367c_setAsicMacAddress(ether_addr_t mac);\nextern ret_t rtl8367c_getAsicMacAddress(ether_addr_t *pMac);\nextern ret_t rtl8367c_getAsicDebugInfo(rtk_uint32 port, rtk_uint32 *pDebugifo);\nextern ret_t rtl8367c_setAsicPortJamMode(rtk_uint32 mode);\nextern ret_t rtl8367c_getAsicPortJamMode(rtk_uint32* pMode);\nextern ret_t rtl8367c_setAsicMaxLengthCfg(rtk_uint32 cfgId, rtk_uint32 maxLength);\nextern ret_t rtl8367c_getAsicMaxLengthCfg(rtk_uint32 cfgId, rtk_uint32 *pMaxLength);\nextern ret_t rtl8367c_setAsicMaxLength(rtk_uint32 port, rtk_uint32 type, rtk_uint32 cfgId);\nextern ret_t rtl8367c_getAsicMaxLength(rtk_uint32 port, rtk_uint32 type, rtk_uint32 *pCfgId);\n\n#endif /*_RTL8367C_ASICDRV_MISC_H_*/\n\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtl8367c_asicdrv_oam.h",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * $Revision: 42321 $\n * $Date: 2013-08-26 13:51:29 +0800 (g@, 26 K 2013) $\n *\n * Purpose : RTL8367C switch high-level API for RTL8367C\n * Feature : OAM related functions\n *\n */\n\n#ifndef _RTL8367C_ASICDRV_OAM_H_\n#define _RTL8367C_ASICDRV_OAM_H_\n\n#include <rtl8367c_asicdrv.h>\n\nenum OAMPARACT\n{\n    OAM_PARFWD = 0,\n    OAM_PARLB,\n    OAM_PARDISCARD,\n    OAM_PARFWDCPU\n};\n\nenum OAMMULACT\n{\n    OAM_MULFWD = 0,\n    OAM_MULDISCARD,\n    OAM_MULCPU\n};\n\nextern ret_t rtl8367c_setAsicOamParser(rtk_uint32 port, rtk_uint32 parser);\nextern ret_t rtl8367c_getAsicOamParser(rtk_uint32 port, rtk_uint32* pParser);\nextern ret_t rtl8367c_setAsicOamMultiplexer(rtk_uint32 port, rtk_uint32 multiplexer);\nextern ret_t rtl8367c_getAsicOamMultiplexer(rtk_uint32 port, rtk_uint32* pMultiplexer);\nextern ret_t rtl8367c_setAsicOamCpuPri(rtk_uint32 priority);\nextern ret_t rtl8367c_getAsicOamCpuPri(rtk_uint32 *pPriority);\nextern ret_t rtl8367c_setAsicOamEnable(rtk_uint32 enabled);\nextern ret_t rtl8367c_getAsicOamEnable(rtk_uint32 *pEnabled);\n#endif /*_RTL8367C_ASICDRV_OAM_H_*/\n\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtl8367c_asicdrv_phy.h",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * $Revision: 76306 $\n * $Date: 2017-03-08 15:13:58 +0800 (gT, 08 T 2017) $\n *\n * Purpose : RTL8367C switch high-level API for RTL8367C\n * Feature : PHY related functions\n *\n */\n\n#ifndef _RTL8367C_ASICDRV_PHY_H_\n#define _RTL8367C_ASICDRV_PHY_H_\n\n#include <rtl8367c_asicdrv.h>\n\n#define RTL8367C_PHY_REGNOMAX           0x1F\n#define RTL8367C_PHY_EXTERNALMAX        0x7\n\n#define RTL8367C_PHY_BASE               0x2000\n#define RTL8367C_PHY_EXT_BASE           0xA000\n\n#define RTL8367C_PHY_OFFSET             5\n#define RTL8367C_PHY_EXT_OFFSET         9\n\n#define RTL8367C_PHY_PAGE_ADDRESS       31\n\n\nextern ret_t rtl8367c_setAsicPHYReg(rtk_uint32 phyNo, rtk_uint32 phyAddr, rtk_uint32 regData );\nextern ret_t rtl8367c_getAsicPHYReg(rtk_uint32 phyNo, rtk_uint32 phyAddr, rtk_uint32* pRegData );\nextern ret_t rtl8367c_setAsicPHYOCPReg(rtk_uint32 phyNo, rtk_uint32 ocpAddr, rtk_uint32 ocpData );\nextern ret_t rtl8367c_getAsicPHYOCPReg(rtk_uint32 phyNo, rtk_uint32 ocpAddr, rtk_uint32 *pRegData );\nextern ret_t rtl8367c_setAsicSdsReg(rtk_uint32 sdsId, rtk_uint32 sdsReg, rtk_uint32 sdsPage,  rtk_uint32 value);\nextern ret_t rtl8367c_getAsicSdsReg(rtk_uint32 sdsId, rtk_uint32 sdsReg, rtk_uint32 sdsPage, rtk_uint32 *value);\n\n#endif /*#ifndef _RTL8367C_ASICDRV_PHY_H_*/\n\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtl8367c_asicdrv_port.h",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * $Revision: 76333 $\n * $Date: 2017-03-09 09:33:15 +0800 (g|, 09 T 2017) $\n *\n * Purpose : RTL8367C switch high-level API for RTL8367C\n * Feature : Port security related functions\n *\n */\n\n#ifndef _RTL8367C_ASICDRV_PORTSECURITY_H_\n#define _RTL8367C_ASICDRV_PORTSECURITY_H_\n\n#include <rtl8367c_asicdrv.h>\n#include <rtl8367c_asicdrv_unknownMulticast.h>\n#include <rtl8367c_asicdrv_phy.h>\n\n/****************************************************************/\n/* Type Definition                                              */\n/****************************************************************/\n\n#define RTL8367C_MAC7       7\n#define RTL8367C_EXTNO       3\n\n#define RTL8367C_RTCT_PAGE          (11)\n#define RTL8367C_RTCT_RESULT_A_REG  (27)\n#define RTL8367C_RTCT_RESULT_B_REG  (28)\n#define RTL8367C_RTCT_RESULT_C_REG  (29)\n#define RTL8367C_RTCT_RESULT_D_REG  (30)\n#define RTL8367C_RTCT_STATUS_REG    (26)\n\nenum L2_SECURITY_BEHAVE\n{\n    L2_BEHAVE_FLOODING = 0,\n    L2_BEHAVE_DROP,\n    L2_BEHAVE_TRAP,\n    L2_BEHAVE_END\n};\n\nenum L2_UNDA_BEHAVE\n{\n    L2_UNDA_BEHAVE_FLOODING_PMASK = 0,\n    L2_UNDA_BEHAVE_DROP,\n    L2_UNDA_BEHAVE_TRAP,\n    L2_UNDA_BEHAVE_FLOODING,\n    L2_UNDA_BEHAVE_END\n};\n\nenum L2_SECURITY_SA_BEHAVE\n{\n    L2_BEHAVE_SA_FLOODING = 0,\n    L2_BEHAVE_SA_DROP,\n    L2_BEHAVE_SA_TRAP,\n    L2_BEHAVE_SA_COPY28051,\n    L2_BEHAVE_SA_END\n};\n\n/* enum for port current link speed */\nenum SPEEDMODE\n{\n    SPD_10M = 0,\n    SPD_100M,\n    SPD_1000M,\n    SPD_2500M\n};\n\n/* enum for mac link mode */\nenum LINKMODE\n{\n    MAC_NORMAL = 0,\n    MAC_FORCE,\n};\n\n/* enum for port current link duplex mode */\nenum DUPLEXMODE\n{\n    HALF_DUPLEX = 0,\n    FULL_DUPLEX\n};\n\n/* enum for port current MST mode */\nenum MSTMODE\n{\n    SLAVE_MODE= 0,\n    MASTER_MODE\n};\n\n\nenum EXTMODE\n{\n    EXT_DISABLE = 0,\n    EXT_RGMII,\n    EXT_MII_MAC,\n    EXT_MII_PHY,\n    EXT_TMII_MAC,\n    EXT_TMII_PHY,\n    EXT_GMII,\n    EXT_RMII_MAC,\n    EXT_RMII_PHY,\n    EXT_SGMII,\n    EXT_HSGMII,\n    EXT_1000X_100FX,\n    EXT_1000X,\n    EXT_100FX,\n    EXT_RGMII_2,\n    EXT_MII_MAC_2,\n    EXT_MII_PHY_2,\n    EXT_TMII_MAC_2,\n    EXT_TMII_PHY_2,\n    EXT_RMII_MAC_2,\n    EXT_RMII_PHY_2,\n    EXT_END\n};\n\nenum DOSTYPE\n{\n    DOS_DAEQSA = 0,\n    DOS_LANDATTACKS,\n    DOS_BLATATTACKS,\n    DOS_SYNFINSCAN,\n    DOS_XMASCAN,\n    DOS_NULLSCAN,\n    DOS_SYN1024,\n    DOS_TCPSHORTHDR,\n    DOS_TCPFRAGERROR,\n    DOS_ICMPFRAGMENT,\n    DOS_END,\n\n};\n\ntypedef struct  rtl8367c_port_ability_s{\n    rtk_uint16 forcemode;\n    rtk_uint16 mstfault;\n    rtk_uint16 mstmode;\n    rtk_uint16 nway;\n    rtk_uint16 txpause;\n    rtk_uint16 rxpause;\n    rtk_uint16 link;\n    rtk_uint16 duplex;\n    rtk_uint16 speed;\n}rtl8367c_port_ability_t;\n\ntypedef struct  rtl8367c_port_status_s{\n\n    rtk_uint16 lpi1000;\n    rtk_uint16 lpi100;\n    rtk_uint16 mstfault;\n    rtk_uint16 mstmode;\n    rtk_uint16 nway;\n    rtk_uint16 txpause;\n    rtk_uint16 rxpause;\n    rtk_uint16 link;\n    rtk_uint16 duplex;\n    rtk_uint16 speed;\n\n}rtl8367c_port_status_t;\n\ntypedef struct rtct_result_s\n{\n    rtk_uint32      channelAShort;\n    rtk_uint32      channelBShort;\n    rtk_uint32      channelCShort;\n    rtk_uint32      channelDShort;\n\n    rtk_uint32      channelAOpen;\n    rtk_uint32      channelBOpen;\n    rtk_uint32      channelCOpen;\n    rtk_uint32      channelDOpen;\n\n    rtk_uint32      channelAMismatch;\n    rtk_uint32      channelBMismatch;\n    rtk_uint32      channelCMismatch;\n    rtk_uint32      channelDMismatch;\n\n    rtk_uint32      channelALinedriver;\n    rtk_uint32      channelBLinedriver;\n    rtk_uint32      channelCLinedriver;\n    rtk_uint32      channelDLinedriver;\n\n    rtk_uint32      channelALen;\n    rtk_uint32      channelBLen;\n    rtk_uint32      channelCLen;\n    rtk_uint32      channelDLen;\n} rtl8367c_port_rtct_result_t;\n\n\n/****************************************************************/\n/* Driver Proto Type Definition                                 */\n/****************************************************************/\nextern ret_t rtl8367c_setAsicPortUnknownDaBehavior(rtk_uint32 port, rtk_uint32 behavior);\nextern ret_t rtl8367c_getAsicPortUnknownDaBehavior(rtk_uint32 port, rtk_uint32 *pBehavior);\nextern ret_t rtl8367c_setAsicPortUnknownSaBehavior(rtk_uint32 behavior);\nextern ret_t rtl8367c_getAsicPortUnknownSaBehavior(rtk_uint32 *pBehavior);\nextern ret_t rtl8367c_setAsicPortUnmatchedSaBehavior(rtk_uint32 behavior);\nextern ret_t rtl8367c_getAsicPortUnmatchedSaBehavior(rtk_uint32 *pBehavior);\nextern ret_t rtl8367c_setAsicPortUnmatchedSaMoving(rtk_uint32 port, rtk_uint32 enabled);\nextern ret_t rtl8367c_getAsicPortUnmatchedSaMoving(rtk_uint32 port, rtk_uint32 *pEnabled);\nextern ret_t rtl8367c_setAsicPortUnknownDaFloodingPortmask(rtk_uint32 portmask);\nextern ret_t rtl8367c_getAsicPortUnknownDaFloodingPortmask(rtk_uint32 *pPortmask);\nextern ret_t rtl8367c_setAsicPortUnknownMulticastFloodingPortmask(rtk_uint32 portmask);\nextern ret_t rtl8367c_getAsicPortUnknownMulticastFloodingPortmask(rtk_uint32 *pPortmask);\nextern ret_t rtl8367c_setAsicPortBcastFloodingPortmask(rtk_uint32 portmask);\nextern ret_t rtl8367c_getAsicPortBcastFloodingPortmask(rtk_uint32 *pPortmask);\nextern ret_t rtl8367c_setAsicPortBlockSpa(rtk_uint32 port, rtk_uint32 block);\nextern ret_t rtl8367c_getAsicPortBlockSpa(rtk_uint32 port, rtk_uint32 *pBlock);\nextern ret_t rtl8367c_setAsicPortForceLink(rtk_uint32 port, rtl8367c_port_ability_t *pPortAbility);\nextern ret_t rtl8367c_getAsicPortForceLink(rtk_uint32 port, rtl8367c_port_ability_t *pPortAbility);\nextern ret_t rtl8367c_getAsicPortStatus(rtk_uint32 port, rtl8367c_port_status_t *pPortStatus);\nextern ret_t rtl8367c_setAsicPortForceLinkExt(rtk_uint32 id, rtl8367c_port_ability_t *pPortAbility);\nextern ret_t rtl8367c_getAsicPortForceLinkExt(rtk_uint32 id, rtl8367c_port_ability_t *pPortAbility);\nextern ret_t rtl8367c_setAsicPortExtMode(rtk_uint32 id, rtk_uint32 mode);\nextern ret_t rtl8367c_getAsicPortExtMode(rtk_uint32 id, rtk_uint32 *pMode);\nextern ret_t rtl8367c_setAsicPortDos(rtk_uint32 type, rtk_uint32 drop);\nextern ret_t rtl8367c_getAsicPortDos(rtk_uint32 type, rtk_uint32* pDrop);\nextern ret_t rtl8367c_setAsicPortEnableAll(rtk_uint32 enable);\nextern ret_t rtl8367c_getAsicPortEnableAll(rtk_uint32 *pEnable);\nextern ret_t rtl8367c_setAsicPortSmallIpg(rtk_uint32 port, rtk_uint32 enable);\nextern ret_t rtl8367c_getAsicPortSmallIpg(rtk_uint32 port, rtk_uint32* pEnable);\nextern ret_t rtl8367c_setAsicPortLoopback(rtk_uint32 port, rtk_uint32 enable);\nextern ret_t rtl8367c_getAsicPortLoopback(rtk_uint32 port, rtk_uint32 *pEnable);\nextern ret_t rtl8367c_setAsicPortRTCTEnable(rtk_uint32 portmask);\nextern ret_t rtl8367c_setAsicPortRTCTDisable(rtk_uint32 portmask);\nextern ret_t rtl8367c_getAsicPortRTCTResult(rtk_uint32 port, rtl8367c_port_rtct_result_t *pResult);\nextern ret_t rtl8367c_sdsReset(rtk_uint32 id);\nextern ret_t rtl8367c_getSdsLinkStatus(rtk_uint32 ext_id, rtk_uint32 *pSignalDetect, rtk_uint32 *pSync, rtk_uint32 *pLink);\nextern ret_t rtl8367c_setSgmiiNway(rtk_uint32 ext_id, rtk_uint32 state);\nextern ret_t rtl8367c_getSgmiiNway(rtk_uint32 ext_id, rtk_uint32 *pState);\n\n#endif /*_RTL8367C_ASICDRV_PORTSECURITY_H_*/\n\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtl8367c_asicdrv_portIsolation.h",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * $Revision: 76306 $\n * $Date: 2017-03-08 15:13:58 +0800 (gT, 08 T 2017) $\n *\n * Purpose : RTL8367C switch high-level API for RTL8367C\n * Feature : Port isolation related functions\n *\n */\n\n#ifndef _RTL8367C_ASICDRV_PORTISOLATION_H_\n#define _RTL8367C_ASICDRV_PORTISOLATION_H_\n\n#include <rtl8367c_asicdrv.h>\n\nextern ret_t rtl8367c_setAsicPortIsolationPermittedPortmask(rtk_uint32 port, rtk_uint32 permitPortmask);\nextern ret_t rtl8367c_getAsicPortIsolationPermittedPortmask(rtk_uint32 port, rtk_uint32 *pPermitPortmask);\nextern ret_t rtl8367c_setAsicPortIsolationEfid(rtk_uint32 port, rtk_uint32 efid);\nextern ret_t rtl8367c_getAsicPortIsolationEfid(rtk_uint32 port, rtk_uint32 *pEfid);\n\n#endif /*_RTL8367C_ASICDRV_PORTISOLATION_H_*/\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtl8367c_asicdrv_qos.h",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * $Revision: 76306 $\n * $Date: 2017-03-08 15:13:58 +0800 (gT, 08 T 2017) $\n *\n * Purpose : RTL8367C switch high-level API for RTL8367C\n * Feature : Qos related functions\n *\n */\n\n#ifndef _RTL8367C_ASICDRV_QOS_H_\n#define _RTL8367C_ASICDRV_QOS_H_\n\n#include <rtl8367c_asicdrv.h>\n\n#define RTL8367C_DECISIONPRIMAX    0xFF\n\n/* enum Priority Selection Types */\nenum PRIDECISION\n{\n    PRIDEC_PORT = 0,\n    PRIDEC_ACL,\n    PRIDEC_DSCP,\n    PRIDEC_1Q,\n    PRIDEC_1AD,\n    PRIDEC_CVLAN,\n    PRIDEC_DA,\n    PRIDEC_SA,\n    PRIDEC_END,\n};\n\n/* enum Priority Selection Index */\nenum RTL8367C_PRIDEC_TABLE\n{\n    PRIDEC_IDX0 = 0,\n    PRIDEC_IDX1,\n    PRIDEC_IDX_END,\n};\n\nenum RTL8367C_DOT1P_PRISEL\n{\n    DOT1P_PRISEL_USER =  0,\n    DOT1P_PRISEL_TAG,\n    DOT1P_PRISEL_END\n};\n\nenum RTL8367C_DSCP_PRISEL\n{\n    DSCP_PRISEL_INTERNAL =  0,\n    DSCP_PRISEL_DSCP,\n    DSCP_PRISEL_USER ,\n    DSCP_PRISEL_END\n};\n\n\nextern ret_t rtl8367c_setAsicRemarkingDot1pAbility(rtk_uint32 port, rtk_uint32 enabled);\nextern ret_t rtl8367c_getAsicRemarkingDot1pAbility(rtk_uint32 port, rtk_uint32* pEnabled);\nextern ret_t rtl8367c_setAsicRemarkingDot1pParameter(rtk_uint32 priority, rtk_uint32 newPriority );\nextern ret_t rtl8367c_getAsicRemarkingDot1pParameter(rtk_uint32 priority, rtk_uint32 *pNewPriority );\nextern  ret_t rtl8367c_setAsicRemarkingDot1pSrc(rtk_uint32 type);\nextern  ret_t rtl8367c_getAsicRemarkingDot1pSrc(rtk_uint32 *pType);\nextern ret_t rtl8367c_setAsicRemarkingDscpAbility(rtk_uint32 enabled);\nextern ret_t rtl8367c_getAsicRemarkingDscpAbility(rtk_uint32* pEnabled);\nextern ret_t rtl8367c_setAsicRemarkingDscpParameter(rtk_uint32 priority, rtk_uint32 newDscp );\nextern ret_t rtl8367c_getAsicRemarkingDscpParameter(rtk_uint32 priority, rtk_uint32* pNewDscp );\n\nextern ret_t rtl8367c_setAsicPriorityDot1qRemapping(rtk_uint32 srcpriority, rtk_uint32 priority );\nextern ret_t rtl8367c_getAsicPriorityDot1qRemapping(rtk_uint32 srcpriority, rtk_uint32 *pPriority );\nextern ret_t rtl8367c_setAsicPriorityDscpBased(rtk_uint32 dscp, rtk_uint32 priority );\nextern ret_t rtl8367c_getAsicPriorityDscpBased(rtk_uint32 dscp, rtk_uint32 *pPriority );\nextern ret_t rtl8367c_setAsicPriorityPortBased(rtk_uint32 port, rtk_uint32 priority );\nextern ret_t rtl8367c_getAsicPriorityPortBased(rtk_uint32 port, rtk_uint32 *pPriority );\nextern ret_t rtl8367c_setAsicPriorityDecision(rtk_uint32 index, rtk_uint32 prisrc, rtk_uint32 decisionPri);\nextern ret_t rtl8367c_getAsicPriorityDecision(rtk_uint32 index, rtk_uint32 prisrc, rtk_uint32* pDecisionPri);\nextern ret_t rtl8367c_setAsicPriorityToQIDMappingTable(rtk_uint32 qnum, rtk_uint32 priority, rtk_uint32 qid );\nextern ret_t rtl8367c_getAsicPriorityToQIDMappingTable(rtk_uint32 qnum, rtk_uint32 priority, rtk_uint32* pQid);\nextern ret_t rtl8367c_setAsicOutputQueueMappingIndex(rtk_uint32 port, rtk_uint32 qnum );\nextern ret_t rtl8367c_getAsicOutputQueueMappingIndex(rtk_uint32 port, rtk_uint32 *pQnum );\n\nextern ret_t rtl8367c_setAsicRemarkingDscpSrc(rtk_uint32 type);\nextern ret_t rtl8367c_getAsicRemarkingDscpSrc(rtk_uint32 *pType);\nextern ret_t rtl8367c_setAsicRemarkingDscp2Dscp(rtk_uint32 dscp, rtk_uint32 rmkDscp);\nextern ret_t rtl8367c_getAsicRemarkingDscp2Dscp(rtk_uint32 dscp, rtk_uint32 *pRmkDscp);\n\nextern ret_t rtl8367c_setAsicPortPriorityDecisionIndex(rtk_uint32 port, rtk_uint32 index );\nextern ret_t rtl8367c_getAsicPortPriorityDecisionIndex(rtk_uint32 port, rtk_uint32 *pIndex );\n\n#endif /*#ifndef _RTL8367C_ASICDRV_QOS_H_*/\n\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtl8367c_asicdrv_rldp.h",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * $Revision: 42321 $\n * $Date: 2013-08-26 13:51:29 +0800 (g@, 26 K 2013) $\n *\n * Purpose : RTL8367C switch high-level API for RTL8367C\n * Feature : RLDP related functions\n *\n */\n\n#ifndef _RTL8367C_ASICDRV_RLDP_H_\n#define _RTL8367C_ASICDRV_RLDP_H_\n\n#include <rtl8367c_asicdrv.h>\n#include <string.h>\n\nextern ret_t rtl8367c_setAsicRldp(rtk_uint32 enabled);\nextern ret_t rtl8367c_getAsicRldp(rtk_uint32 *pEnabled);\nextern ret_t rtl8367c_setAsicRldpEnable8051(rtk_uint32 enabled);\nextern ret_t rtl8367c_getAsicRldpEnable8051(rtk_uint32 *pEnabled);\nextern ret_t rtl8367c_setAsicRldpCompareRandomNumber(rtk_uint32 enabled);\nextern ret_t rtl8367c_getAsicRldpCompareRandomNumber(rtk_uint32 *pEnabled);\nextern ret_t rtl8367c_setAsicRldpIndicatorSource(rtk_uint32 src);\nextern ret_t rtl8367c_getAsicRldpIndicatorSource(rtk_uint32 *pSrc);\nextern ret_t rtl8367c_setAsicRldpCheckingStatePara(rtk_uint32 retryCount, rtk_uint32 retryPeriod);\nextern ret_t rtl8367c_getAsicRldpCheckingStatePara(rtk_uint32 *pRetryCount, rtk_uint32 *pRetryPeriod);\nextern ret_t rtl8367c_setAsicRldpLoopStatePara(rtk_uint32 retryCount, rtk_uint32 retryPeriod);\nextern ret_t rtl8367c_getAsicRldpLoopStatePara(rtk_uint32 *pRetryCount, rtk_uint32 *pRetryPeriod);\nextern ret_t rtl8367c_setAsicRldpTxPortmask(rtk_uint32 portmask);\nextern ret_t rtl8367c_getAsicRldpTxPortmask(rtk_uint32 *pPortmask);\nextern ret_t rtl8367c_setAsicRldpMagicNum(ether_addr_t seed);\nextern ret_t rtl8367c_getAsicRldpMagicNum(ether_addr_t *pSeed);\nextern ret_t rtl8367c_getAsicRldpLoopedPortmask(rtk_uint32 *pPortmask);\nextern ret_t rtl8367c_setAsicRldp8051Portmask(rtk_uint32 portmask);\nextern ret_t rtl8367c_getAsicRldp8051Portmask(rtk_uint32 *pPortmask);\n\n\nextern ret_t rtl8367c_getAsicRldpRandomNumber(ether_addr_t *pRandNumber);\nextern ret_t rtl8367c_getAsicRldpLoopedPortPair(rtk_uint32 port, rtk_uint32 *pLoopedPair);\nextern ret_t rtl8367c_setAsicRlppTrap8051(rtk_uint32 enabled);\nextern ret_t rtl8367c_getAsicRlppTrap8051(rtk_uint32 *pEnabled);\n\nextern ret_t rtl8367c_setAsicRldpLeaveLoopedPortmask(rtk_uint32 portmask);\nextern ret_t rtl8367c_getAsicRldpLeaveLoopedPortmask(rtk_uint32 *pPortmask);\n\nextern ret_t rtl8367c_setAsicRldpEnterLoopedPortmask(rtk_uint32 portmask);\nextern ret_t rtl8367c_getAsicRldpEnterLoopedPortmask(rtk_uint32 *pPortmask);\n\nextern ret_t rtl8367c_setAsicRldpTriggerMode(rtk_uint32 enabled);\nextern ret_t rtl8367c_getAsicRldpTriggerMode(rtk_uint32 *pEnabled);\n\n#endif /*_RTL8367C_ASICDRV_RLDP_H_*/\n\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtl8367c_asicdrv_rma.h",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * $Revision: 64716 $\n * $Date: 2015-12-31 16:31:55 +0800 (g|, 31 QG 2015) $\n *\n * Purpose : RTL8367C switch high-level API for RTL8367C\n * Feature : RMA related functions\n *\n */\n\n#ifndef _RTL8367C_ASICDRV_RMA_H_\n#define _RTL8367C_ASICDRV_RMA_H_\n\n#include <rtl8367c_asicdrv.h>\n\n#define RTL8367C_RMAMAX                     0x2F\n\nenum RTL8367C_RMAOP\n{\n    RMAOP_FORWARD = 0,\n    RMAOP_TRAP_TO_CPU,\n    RMAOP_DROP,\n    RMAOP_FORWARD_EXCLUDE_CPU,\n    RMAOP_END\n};\n\n\ntypedef struct  rtl8367c_rma_s{\n\n    rtk_uint16 operation;\n    rtk_uint16 discard_storm_filter;\n    rtk_uint16 trap_priority;\n    rtk_uint16 keep_format;\n    rtk_uint16 vlan_leaky;\n    rtk_uint16 portiso_leaky;\n\n}rtl8367c_rma_t;\n\n\nextern ret_t rtl8367c_setAsicRma(rtk_uint32 index, rtl8367c_rma_t* pRmacfg);\nextern ret_t rtl8367c_getAsicRma(rtk_uint32 index, rtl8367c_rma_t* pRmacfg);\nextern ret_t rtl8367c_setAsicRmaCdp(rtl8367c_rma_t* pRmacfg);\nextern ret_t rtl8367c_getAsicRmaCdp(rtl8367c_rma_t* pRmacfg);\nextern ret_t rtl8367c_setAsicRmaCsstp(rtl8367c_rma_t* pRmacfg);\nextern ret_t rtl8367c_getAsicRmaCsstp(rtl8367c_rma_t* pRmacfg);\nextern ret_t rtl8367c_setAsicRmaLldp(rtk_uint32 enabled, rtl8367c_rma_t* pRmacfg);\nextern ret_t rtl8367c_getAsicRmaLldp(rtk_uint32 *pEnabled, rtl8367c_rma_t* pRmacfg);\n\n#endif /*#ifndef _RTL8367C_ASICDRV_RMA_H_*/\n\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtl8367c_asicdrv_scheduling.h",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * $Revision: 76306 $\n * $Date: 2017-03-08 15:13:58 +0800 (gT, 08 T 2017) $\n *\n * Purpose : RTL8367C switch high-level API for RTL8367C\n * Feature : Packet Scheduling related functions\n *\n */\n\n#ifndef _RTL8367C_ASICDRV_SCHEDULING_H_\n#define _RTL8367C_ASICDRV_SCHEDULING_H_\n\n#include <rtl8367c_asicdrv.h>\n\n#define RTL8367C_QWEIGHTMAX    0x7F\n#define RTL8367C_PORT_QUEUE_METER_INDEX_MAX    7\n\n/* enum for queue type */\nenum QUEUETYPE\n{\n    QTYPE_STRICT = 0,\n    QTYPE_WFQ,\n};\nextern ret_t rtl8367c_setAsicLeakyBucketParameter(rtk_uint32 tick, rtk_uint32 token);\nextern ret_t rtl8367c_getAsicLeakyBucketParameter(rtk_uint32 *tick, rtk_uint32 *token);\nextern ret_t rtl8367c_setAsicAprMeter(rtk_uint32 port, rtk_uint32 qid, rtk_uint32 apridx);\nextern ret_t rtl8367c_getAsicAprMeter(rtk_uint32 port, rtk_uint32 qid, rtk_uint32 *apridx);\nextern ret_t rtl8367c_setAsicPprMeter(rtk_uint32 port, rtk_uint32 qid, rtk_uint32 ppridx);\nextern ret_t rtl8367c_getAsicPprMeter(rtk_uint32 port, rtk_uint32 qid, rtk_uint32 *ppridx);\nextern ret_t rtl8367c_setAsicAprEnable(rtk_uint32 port, rtk_uint32 aprEnable);\nextern ret_t rtl8367c_getAsicAprEnable(rtk_uint32 port, rtk_uint32 *aprEnable);\nextern ret_t rtl8367c_setAsicPprEnable(rtk_uint32 port, rtk_uint32 pprEnable);\nextern ret_t rtl8367c_getAsicPprEnable(rtk_uint32 port, rtk_uint32 *pprEnable);\n\nextern ret_t rtl8367c_setAsicWFQWeight(rtk_uint32, rtk_uint32 queueid, rtk_uint32 weight );\nextern ret_t rtl8367c_getAsicWFQWeight(rtk_uint32, rtk_uint32 queueid, rtk_uint32 *weight );\nextern ret_t rtl8367c_setAsicWFQBurstSize(rtk_uint32 burstsize);\nextern ret_t rtl8367c_getAsicWFQBurstSize(rtk_uint32 *burstsize);\n\nextern ret_t rtl8367c_setAsicQueueType(rtk_uint32 port, rtk_uint32 qid, rtk_uint32 queueType);\nextern ret_t rtl8367c_getAsicQueueType(rtk_uint32 port, rtk_uint32 qid, rtk_uint32 *queueType);\nextern ret_t rtl8367c_setAsicQueueRate(rtk_uint32 port, rtk_uint32 qid, rtk_uint32 ppridx, rtk_uint32 apridx );\nextern ret_t rtl8367c_getAsicQueueRate(rtk_uint32 port, rtk_uint32 qid, rtk_uint32* ppridx, rtk_uint32* apridx );\nextern ret_t rtl8367c_setAsicPortEgressRate(rtk_uint32 port, rtk_uint32 rate);\nextern ret_t rtl8367c_getAsicPortEgressRate(rtk_uint32 port, rtk_uint32 *rate);\nextern ret_t rtl8367c_setAsicPortEgressRateIfg(rtk_uint32 ifg);\nextern ret_t rtl8367c_getAsicPortEgressRateIfg(rtk_uint32 *ifg);\n\n#endif /*_RTL8367C_ASICDRV_SCHEDULING_H_*/\n\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtl8367c_asicdrv_storm.h",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * $Revision: 76306 $\n * $Date: 2017-03-08 15:13:58 +0800 (gT, 08 T 2017) $\n *\n * Purpose : RTL8367C switch high-level API for RTL8367C\n * Feature : Storm control filtering related functions\n *\n */\n\n#ifndef _RTL8367C_ASICDRV_STORM_H_\n#define _RTL8367C_ASICDRV_STORM_H_\n\n#include <rtl8367c_asicdrv.h>\n\nextern ret_t rtl8367c_setAsicStormFilterBroadcastEnable(rtk_uint32 port, rtk_uint32 enabled);\nextern ret_t rtl8367c_getAsicStormFilterBroadcastEnable(rtk_uint32 port, rtk_uint32 *pEnabled);\nextern ret_t rtl8367c_setAsicStormFilterBroadcastMeter(rtk_uint32 port, rtk_uint32 meter);\nextern ret_t rtl8367c_getAsicStormFilterBroadcastMeter(rtk_uint32 port, rtk_uint32 *pMeter);\nextern ret_t rtl8367c_setAsicStormFilterMulticastEnable(rtk_uint32 port, rtk_uint32 enabled);\nextern ret_t rtl8367c_getAsicStormFilterMulticastEnable(rtk_uint32 port, rtk_uint32 *pEnabled);\nextern ret_t rtl8367c_setAsicStormFilterMulticastMeter(rtk_uint32 port, rtk_uint32 meter);\nextern ret_t rtl8367c_getAsicStormFilterMulticastMeter(rtk_uint32 port, rtk_uint32 *pMeter);\nextern ret_t rtl8367c_setAsicStormFilterUnknownMulticastEnable(rtk_uint32 port, rtk_uint32 enabled);\nextern ret_t rtl8367c_getAsicStormFilterUnknownMulticastEnable(rtk_uint32 port, rtk_uint32 *pEnabled);\nextern ret_t rtl8367c_setAsicStormFilterUnknownMulticastMeter(rtk_uint32 port, rtk_uint32 meter);\nextern ret_t rtl8367c_getAsicStormFilterUnknownMulticastMeter(rtk_uint32 port, rtk_uint32 *pMeter);\nextern ret_t rtl8367c_setAsicStormFilterUnknownUnicastEnable(rtk_uint32 port, rtk_uint32 enabled);\nextern ret_t rtl8367c_getAsicStormFilterUnknownUnicastEnable(rtk_uint32 port, rtk_uint32 *pEnabled);\nextern ret_t rtl8367c_setAsicStormFilterUnknownUnicastMeter(rtk_uint32 port, rtk_uint32 meter);\nextern ret_t rtl8367c_getAsicStormFilterUnknownUnicastMeter(rtk_uint32 port, rtk_uint32 *pMeter);\nextern ret_t rtl8367c_setAsicStormFilterExtBroadcastMeter(rtk_uint32 meter);\nextern ret_t rtl8367c_getAsicStormFilterExtBroadcastMeter(rtk_uint32 *pMeter);\nextern ret_t rtl8367c_setAsicStormFilterExtMulticastMeter(rtk_uint32 meter);\nextern ret_t rtl8367c_getAsicStormFilterExtMulticastMeter(rtk_uint32 *pMeter);\nextern ret_t rtl8367c_setAsicStormFilterExtUnknownMulticastMeter(rtk_uint32 meter);\nextern ret_t rtl8367c_getAsicStormFilterExtUnknownMulticastMeter(rtk_uint32 *pMeter);\nextern ret_t rtl8367c_setAsicStormFilterExtUnknownUnicastMeter(rtk_uint32 meter);\nextern ret_t rtl8367c_getAsicStormFilterExtUnknownUnicastMeter(rtk_uint32 *pMeter);\nextern ret_t rtl8367c_setAsicStormFilterExtBroadcastEnable(rtk_uint32 enabled);\nextern ret_t rtl8367c_getAsicStormFilterExtBroadcastEnable(rtk_uint32 *pEnabled);\nextern ret_t rtl8367c_setAsicStormFilterExtMulticastEnable(rtk_uint32 enabled);\nextern ret_t rtl8367c_getAsicStormFilterExtMulticastEnable(rtk_uint32 *pEnabled);\nextern ret_t rtl8367c_setAsicStormFilterExtUnknownMulticastEnable(rtk_uint32 enabled);\nextern ret_t rtl8367c_getAsicStormFilterExtUnknownMulticastEnable(rtk_uint32 *pEnabled);\nextern ret_t rtl8367c_setAsicStormFilterExtUnknownUnicastEnable(rtk_uint32 enabled);\nextern ret_t rtl8367c_getAsicStormFilterExtUnknownUnicastEnable(rtk_uint32 *pEnabled);\nextern ret_t rtl8367c_setAsicStormFilterExtEnablePortMask(rtk_uint32 portmask);\nextern ret_t rtl8367c_getAsicStormFilterExtEnablePortMask(rtk_uint32 *pPortmask);\n\n\n#endif /*_RTL8367C_ASICDRV_STORM_H_*/\n\n\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtl8367c_asicdrv_svlan.h",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * $Revision: 76306 $\n * $Date: 2017-03-08 15:13:58 +0800 (gT, 08 T 2017) $\n *\n * Purpose : RTL8367C switch high-level API for RTL8367C\n * Feature : SVLAN related functions\n *\n */\n\n#ifndef _RTL8367C_ASICDRV_SVLAN_H_\n#define _RTL8367C_ASICDRV_SVLAN_H_\n\n#include <rtl8367c_asicdrv.h>\n\n#define RTL8367C_C2SIDXNO               128\n#define RTL8367C_C2SIDXMAX              (RTL8367C_C2SIDXNO-1)\n#define RTL8367C_MC2SIDXNO              32\n#define RTL8367C_MC2SIDXMAX             (RTL8367C_MC2SIDXNO-1)\n#define RTL8367C_SP2CIDXNO              128\n#define RTL8367C_SP2CMAX                (RTL8367C_SP2CIDXNO-1)\n\n#define RTL8367C_SVLAN_MEMCONF_LEN      4\n#define RTL8367C_SVLAN_MC2S_LEN         5\n#define RTL8367C_SVLAN_SP2C_LEN         2\n\nenum RTL8367C_SPRISEL\n{\n    SPRISEL_INTERNALPRI =  0,\n    SPRISEL_CTAGPRI,\n    SPRISEL_VSPRI,\n    SPRISEL_PBPRI,\n    SPRISEL_END\n};\n\nenum RTL8367C_SUNACCEPT\n{\n    SUNACCEPT_DROP =  0,\n    SUNACCEPT_TRAP,\n    SUNACCEPT_SVLAN,\n    SUNACCEPT_END\n};\n\nenum RTL8367C_SVLAN_MC2S_MODE\n{\n    SVLAN_MC2S_MODE_MAC =  0,\n    SVLAN_MC2S_MODE_IP,\n    SVLAN_MC2S_MODE_END\n};\n\n\ntypedef struct  rtl8367c_svlan_memconf_s{\n\n    rtk_uint16 vs_member:11;\n    rtk_uint16 vs_untag:11;\n\n    rtk_uint16 vs_fid_msti:4;\n    rtk_uint16 vs_priority:3;\n    rtk_uint16 vs_force_fid:1;\n    rtk_uint16 reserved:8;\n\n    rtk_uint16 vs_svid:12;\n    rtk_uint16 vs_efiden:1;\n    rtk_uint16 vs_efid:3;\n\n\n}rtl8367c_svlan_memconf_t;\n\n\ntypedef struct  rtl8367c_svlan_mc2s_s{\n\n    rtk_uint16 valid:1;\n    rtk_uint16 format:1;\n    rtk_uint16 svidx:6;\n    rtk_uint32 sdata;\n    rtk_uint32 smask;\n}rtl8367c_svlan_mc2s_t;\n\n\ntypedef struct  rtl8367c_svlan_s2c_s{\n\n    rtk_uint16 valid:1;\n    rtk_uint16 svidx:6;\n    rtk_uint16 dstport:4;\n    rtk_uint32 vid:12;\n}rtl8367c_svlan_s2c_t;\n\nextern ret_t rtl8367c_setAsicSvlanIngressUntag(rtk_uint32 mode);\nextern ret_t rtl8367c_getAsicSvlanIngressUntag(rtk_uint32* pMode);\nextern ret_t rtl8367c_setAsicSvlanIngressUnmatch(rtk_uint32 mode);\nextern ret_t rtl8367c_getAsicSvlanIngressUnmatch(rtk_uint32* pMode);\nextern ret_t rtl8367c_setAsicSvlanTrapPriority(rtk_uint32 priority);\nextern ret_t rtl8367c_getAsicSvlanTrapPriority(rtk_uint32* pPriority);\nextern ret_t rtl8367c_setAsicSvlanDefaultVlan(rtk_uint32 port, rtk_uint32 index);\nextern ret_t rtl8367c_getAsicSvlanDefaultVlan(rtk_uint32 port, rtk_uint32* pIndex);\n\nextern ret_t rtl8367c_setAsicSvlanMemberConfiguration(rtk_uint32 index,rtl8367c_svlan_memconf_t* pSvlanMemCfg);\nextern ret_t rtl8367c_getAsicSvlanMemberConfiguration(rtk_uint32 index,rtl8367c_svlan_memconf_t* pSvlanMemCfg);\n\nextern ret_t rtl8367c_setAsicSvlanPrioritySel(rtk_uint32 priSel);\nextern ret_t rtl8367c_getAsicSvlanPrioritySel(rtk_uint32* pPriSel);\nextern ret_t rtl8367c_setAsicSvlanTpid(rtk_uint32 protocolType);\nextern ret_t rtl8367c_getAsicSvlanTpid(rtk_uint32* pProtocolType);\nextern ret_t rtl8367c_setAsicSvlanUplinkPortMask(rtk_uint32 portMask);\nextern ret_t rtl8367c_getAsicSvlanUplinkPortMask(rtk_uint32* pPortmask);\nextern ret_t rtl8367c_setAsicSvlanEgressUnassign(rtk_uint32 enabled);\nextern ret_t rtl8367c_getAsicSvlanEgressUnassign(rtk_uint32* pEnabled);\nextern ret_t rtl8367c_setAsicSvlanC2SConf(rtk_uint32 index, rtk_uint32 evid, rtk_uint32 portmask, rtk_uint32 svidx);\nextern ret_t rtl8367c_getAsicSvlanC2SConf(rtk_uint32 index, rtk_uint32* pEvid, rtk_uint32* pPortmask, rtk_uint32* pSvidx);\nextern ret_t rtl8367c_setAsicSvlanMC2SConf(rtk_uint32 index,rtl8367c_svlan_mc2s_t* pSvlanMc2sCfg);\nextern ret_t rtl8367c_getAsicSvlanMC2SConf(rtk_uint32 index,rtl8367c_svlan_mc2s_t* pSvlanMc2sCfg);\nextern ret_t rtl8367c_setAsicSvlanSP2CConf(rtk_uint32 index,rtl8367c_svlan_s2c_t* pSvlanSp2cCfg);\nextern ret_t rtl8367c_getAsicSvlanSP2CConf(rtk_uint32 index,rtl8367c_svlan_s2c_t* pSvlanSp2cCfg);\nextern ret_t rtl8367c_setAsicSvlanDmacCvidSel(rtk_uint32 port, rtk_uint32 enabled);\nextern ret_t rtl8367c_getAsicSvlanDmacCvidSel(rtk_uint32 port, rtk_uint32* pEnabled);\nextern ret_t rtl8367c_setAsicSvlanUntagVlan(rtk_uint32 index);\nextern ret_t rtl8367c_getAsicSvlanUntagVlan(rtk_uint32* pIndex);\nextern ret_t rtl8367c_setAsicSvlanUnmatchVlan(rtk_uint32 index);\nextern ret_t rtl8367c_getAsicSvlanUnmatchVlan(rtk_uint32* pIndex);\nextern ret_t rtl8367c_setAsicSvlanLookupType(rtk_uint32 type);\nextern ret_t rtl8367c_getAsicSvlanLookupType(rtk_uint32* pType);\n\n\n#endif /*#ifndef _RTL8367C_ASICDRV_SVLAN_H_*/\n\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtl8367c_asicdrv_trunking.h",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * $Revision: 76306 $\n * $Date: 2017-03-08 15:13:58 +0800 (gT, 08 T 2017) $\n *\n * Purpose : RTL8367C switch high-level API for RTL8367C\n * Feature : Port trunking related functions\n *\n */\n\n\n#ifndef _RTL8367C_ASICDRV_TRUNKING_H_\n#define _RTL8367C_ASICDRV_TRUNKING_H_\n\n#include <rtl8367c_asicdrv.h>\n\n#define RTL8367C_MAX_TRUNK_GID              (2)\n#define RTL8367C_TRUNKING_PORTNO            (4)\n#define RTL8367C_TRUNKING1_PORTN0           (2)\n#define RTL8367C_TRUNKING_HASHVALUE_MAX     (15)\n\nextern ret_t rtl8367c_setAsicTrunkingGroup(rtk_uint32 group, rtk_uint32 portmask);\nextern ret_t rtl8367c_getAsicTrunkingGroup(rtk_uint32 group, rtk_uint32* pPortmask);\nextern ret_t rtl8367c_setAsicTrunkingFlood(rtk_uint32 enabled);\nextern ret_t rtl8367c_getAsicTrunkingFlood(rtk_uint32* pEnabled);\nextern ret_t rtl8367c_setAsicTrunkingHashSelect(rtk_uint32 hashsel);\nextern ret_t rtl8367c_getAsicTrunkingHashSelect(rtk_uint32* pHashsel);\n\nextern ret_t rtl8367c_getAsicQeueuEmptyStatus(rtk_uint32* pPortmask);\n\nextern ret_t rtl8367c_setAsicTrunkingMode(rtk_uint32 mode);\nextern ret_t rtl8367c_getAsicTrunkingMode(rtk_uint32* pMode);\nextern ret_t rtl8367c_setAsicTrunkingFc(rtk_uint32 group, rtk_uint32 enabled);\nextern ret_t rtl8367c_getAsicTrunkingFc(rtk_uint32 group, rtk_uint32* pEnabled);\nextern ret_t rtl8367c_setAsicTrunkingHashTable(rtk_uint32 hashval, rtk_uint32 portId);\nextern ret_t rtl8367c_getAsicTrunkingHashTable(rtk_uint32 hashval, rtk_uint32* pPortId);\nextern ret_t rtl8367c_setAsicTrunkingHashTable1(rtk_uint32 hashval, rtk_uint32 portId);\nextern ret_t rtl8367c_getAsicTrunkingHashTable1(rtk_uint32 hashval, rtk_uint32* pPortId);\n\n#endif /*_RTL8367C_ASICDRV_TRUNKING_H_*/\n\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtl8367c_asicdrv_unknownMulticast.h",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * $Revision: 76306 $\n * $Date: 2017-03-08 15:13:58 +0800 (gT, 08 T 2017) $\n *\n * Purpose : RTL8367C switch high-level API for RTL8367C\n * Feature : Unkown multicast related functions\n *\n */\n\n#ifndef _RTL8367C_ASICDRV_UNKNOWNMULTICAST_H_\n#define _RTL8367C_ASICDRV_UNKNOWNMULTICAST_H_\n\n#include <rtl8367c_asicdrv.h>\n\nenum L2_UNKOWN_MULTICAST_BEHAVE\n{\n    L2_UNKOWN_MULTICAST_FLOODING = 0,\n    L2_UNKOWN_MULTICAST_DROP,\n    L2_UNKOWN_MULTICAST_TRAP,\n    L2_UNKOWN_MULTICAST_DROP_EXCLUDE_RMA,\n    L2_UNKOWN_MULTICAST_END\n};\n\nenum L3_UNKOWN_MULTICAST_BEHAVE\n{\n    L3_UNKOWN_MULTICAST_FLOODING = 0,\n    L3_UNKOWN_MULTICAST_DROP,\n    L3_UNKOWN_MULTICAST_TRAP,\n    L3_UNKOWN_MULTICAST_ROUTER,\n    L3_UNKOWN_MULTICAST_END\n};\n\nenum MULTICASTTYPE{\n    MULTICAST_TYPE_IPV4 = 0,\n    MULTICAST_TYPE_IPV6,\n    MULTICAST_TYPE_L2,\n    MULTICAST_TYPE_END\n};\n\nextern ret_t rtl8367c_setAsicUnknownL2MulticastBehavior(rtk_uint32 port, rtk_uint32 behave);\nextern ret_t rtl8367c_getAsicUnknownL2MulticastBehavior(rtk_uint32 port, rtk_uint32 *pBehave);\nextern ret_t rtl8367c_setAsicUnknownIPv4MulticastBehavior(rtk_uint32 port, rtk_uint32 behave);\nextern ret_t rtl8367c_getAsicUnknownIPv4MulticastBehavior(rtk_uint32 port, rtk_uint32 *pBehave);\nextern ret_t rtl8367c_setAsicUnknownIPv6MulticastBehavior(rtk_uint32 port, rtk_uint32 behave);\nextern ret_t rtl8367c_getAsicUnknownIPv6MulticastBehavior(rtk_uint32 port, rtk_uint32 *pBehave);\nextern ret_t rtl8367c_setAsicUnknownMulticastTrapPriority(rtk_uint32 priority);\nextern ret_t rtl8367c_getAsicUnknownMulticastTrapPriority(rtk_uint32 *pPriority);\n\n#endif /*_RTL8367C_ASICDRV_UNKNOWNMULTICAST_H_*/\n\n\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtl8367c_asicdrv_vlan.h",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * $Revision: 76306 $\n * $Date: 2017-03-08 15:13:58 +0800 (gT, 08 T 2017) $\n *\n * Purpose : RTL8367C switch high-level API for RTL8367C\n * Feature : VLAN related functions\n *\n */\n\n\n#ifndef _RTL8367C_ASICDRV_VLAN_H_\n#define _RTL8367C_ASICDRV_VLAN_H_\n\n/****************************************************************/\n/* Header File inclusion                                        */\n/****************************************************************/\n#include <rtl8367c_asicdrv.h>\n\n/****************************************************************/\n/* Constant Definition                                          */\n/****************************************************************/\n#define RTL8367C_PROTOVLAN_GIDX_MAX 3\n#define RTL8367C_PROTOVLAN_GROUPNO  4\n\n#define RTL8367C_VLAN_BUSY_CHECK_NO     (10)\n\n#define RTL8367C_VLAN_MBRCFG_LEN    (4)\n#define RTL8367C_VLAN_4KTABLE_LEN   (3)\n\n/****************************************************************/\n/* Type Definition                                              */\n/****************************************************************/\ntypedef struct  VLANCONFIGUSER\n{\n    rtk_uint16  evid;\n    rtk_uint16  mbr;\n    rtk_uint16  fid_msti;\n    rtk_uint16  envlanpol;\n    rtk_uint16  meteridx;\n    rtk_uint16  vbpen;\n    rtk_uint16  vbpri;\n}rtl8367c_vlanconfiguser;\n\ntypedef struct  USER_VLANTABLE{\n\n    rtk_uint16  vid;\n    rtk_uint16  mbr;\n    rtk_uint16  untag;\n    rtk_uint16  fid_msti;\n    rtk_uint16  envlanpol;\n    rtk_uint16  meteridx;\n    rtk_uint16  vbpen;\n    rtk_uint16  vbpri;\n    rtk_uint16  ivl_svl;\n\n}rtl8367c_user_vlan4kentry;\n\ntypedef enum\n{\n    FRAME_TYPE_BOTH = 0,\n    FRAME_TYPE_TAGGED_ONLY,\n    FRAME_TYPE_UNTAGGED_ONLY,\n    FRAME_TYPE_MAX_BOUND\n} rtl8367c_accframetype;\n\ntypedef enum\n{\n    EG_TAG_MODE_ORI = 0,\n    EG_TAG_MODE_KEEP,\n    EG_TAG_MODE_PRI_TAG,\n    EG_TAG_MODE_REAL_KEEP,\n    EG_TAG_MODE_END\n} rtl8367c_egtagmode;\n\ntypedef enum\n{\n    PPVLAN_FRAME_TYPE_ETHERNET = 0,\n    PPVLAN_FRAME_TYPE_LLC,\n    PPVLAN_FRAME_TYPE_RFC1042,\n    PPVLAN_FRAME_TYPE_END\n} rtl8367c_provlan_frametype;\n\nenum RTL8367C_STPST\n{\n    STPST_DISABLED = 0,\n    STPST_BLOCKING,\n    STPST_LEARNING,\n    STPST_FORWARDING\n};\n\nenum RTL8367C_RESVIDACT\n{\n    RES_VID_ACT_UNTAG = 0,\n    RES_VID_ACT_TAG,\n    RES_VID_ACT_END\n};\n\ntypedef struct\n{\n    rtl8367c_provlan_frametype  frameType;\n    rtk_uint32                      etherType;\n} rtl8367c_protocolgdatacfg;\n\ntypedef struct\n{\n    rtk_uint32 valid;\n    rtk_uint32 vlan_idx;\n    rtk_uint32 priority;\n} rtl8367c_protocolvlancfg;\n\nextern ret_t rtl8367c_setAsicVlanMemberConfig(rtk_uint32 index, rtl8367c_vlanconfiguser *pVlanCg);\nextern ret_t rtl8367c_getAsicVlanMemberConfig(rtk_uint32 index, rtl8367c_vlanconfiguser *pVlanCg);\nextern ret_t rtl8367c_setAsicVlan4kEntry(rtl8367c_user_vlan4kentry *pVlan4kEntry );\nextern ret_t rtl8367c_getAsicVlan4kEntry(rtl8367c_user_vlan4kentry *pVlan4kEntry );\nextern ret_t rtl8367c_setAsicVlanAccpetFrameType(rtk_uint32 port, rtl8367c_accframetype frameType);\nextern ret_t rtl8367c_getAsicVlanAccpetFrameType(rtk_uint32 port, rtl8367c_accframetype *pFrameType);\nextern ret_t rtl8367c_setAsicVlanIngressFilter(rtk_uint32 port, rtk_uint32 enabled);\nextern ret_t rtl8367c_getAsicVlanIngressFilter(rtk_uint32 port, rtk_uint32 *pEnable);\nextern ret_t rtl8367c_setAsicVlanEgressTagMode(rtk_uint32 port, rtl8367c_egtagmode tagMode);\nextern ret_t rtl8367c_getAsicVlanEgressTagMode(rtk_uint32 port, rtl8367c_egtagmode *pTagMode);\nextern ret_t rtl8367c_setAsicVlanPortBasedVID(rtk_uint32 port, rtk_uint32 index, rtk_uint32 pri);\nextern ret_t rtl8367c_getAsicVlanPortBasedVID(rtk_uint32 port, rtk_uint32 *pIndex, rtk_uint32 *pPri);\nextern ret_t rtl8367c_setAsicVlanProtocolBasedGroupData(rtk_uint32 index, rtl8367c_protocolgdatacfg *pPbCfg);\nextern ret_t rtl8367c_getAsicVlanProtocolBasedGroupData(rtk_uint32 index, rtl8367c_protocolgdatacfg *pPbCfg);\nextern ret_t rtl8367c_setAsicVlanPortAndProtocolBased(rtk_uint32 port, rtk_uint32 index, rtl8367c_protocolvlancfg *pPpbCfg);\nextern ret_t rtl8367c_getAsicVlanPortAndProtocolBased(rtk_uint32 port, rtk_uint32 index, rtl8367c_protocolvlancfg *pPpbCfg);\nextern ret_t rtl8367c_setAsicVlanFilter(rtk_uint32 enabled);\nextern ret_t rtl8367c_getAsicVlanFilter(rtk_uint32* pEnabled);\n\nextern ret_t rtl8367c_setAsicPortBasedFid(rtk_uint32 port, rtk_uint32 fid);\nextern ret_t rtl8367c_getAsicPortBasedFid(rtk_uint32 port, rtk_uint32* pFid);\nextern ret_t rtl8367c_setAsicPortBasedFidEn(rtk_uint32 port, rtk_uint32 enabled);\nextern ret_t rtl8367c_getAsicPortBasedFidEn(rtk_uint32 port, rtk_uint32* pEnabled);\nextern ret_t rtl8367c_setAsicSpanningTreeStatus(rtk_uint32 port, rtk_uint32 msti, rtk_uint32 state);\nextern ret_t rtl8367c_getAsicSpanningTreeStatus(rtk_uint32 port, rtk_uint32 msti, rtk_uint32* pState);\nextern ret_t rtl8367c_setAsicVlanUntagDscpPriorityEn(rtk_uint32 enabled);\nextern ret_t rtl8367c_getAsicVlanUntagDscpPriorityEn(rtk_uint32* enabled);\nextern ret_t rtl8367c_setAsicVlanTransparent(rtk_uint32 port, rtk_uint32 portmask);\nextern ret_t rtl8367c_getAsicVlanTransparent(rtk_uint32 port, rtk_uint32 *pPortmask);\nextern ret_t rtl8367c_setAsicVlanEgressKeep(rtk_uint32 port, rtk_uint32 portmask);\nextern ret_t rtl8367c_getAsicVlanEgressKeep(rtk_uint32 port, rtk_uint32* pPortmask);\nextern ret_t rtl8367c_setReservedVidAction(rtk_uint32 vid0Action, rtk_uint32 vid4095Action);\nextern ret_t rtl8367c_getReservedVidAction(rtk_uint32 *pVid0Action, rtk_uint32 *pVid4095Action);\nextern ret_t rtl8367c_setRealKeepRemarkEn(rtk_uint32 enabled);\nextern ret_t rtl8367c_getRealKeepRemarkEn(rtk_uint32 *pEnabled);\nextern ret_t rtl8367c_resetVlan(void);\n\n#endif /*#ifndef _RTL8367C_ASICDRV_VLAN_H_*/\n\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtl8367c_base.h",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * $Revision: 76306 $\n * $Date: 2017-03-08 15:13:58 +0800 (gT, 08 T 2017) $\n *\n * Purpose : RTL8367C switch high-level API for RTL8367C\n * Feature : Regsiter MACRO related definition\n *\n */\n\n#ifndef _RTL8367C_BASE_H_\n#define _RTL8367C_BASE_H_\n\n#include <rtl8367c_reg.h>\n\n/* (16'h0000) port_reg */\n\n#define    RTL8367C_PORT_SPECIAL_CONGEST_MODE_TIMER_BASE        RTL8367C_REG_PKTGEN_PORT0_TIMER\n#define    RTL8367C_PORT_SPECIAL_CONGEST_MODE_TIMER_REG(port)    (RTL8367C_PORT_SPECIAL_CONGEST_MODE_TIMER_BASE + (port << 5))\n\n#define    RTL8367C_PORT_MISC_CFG_BASE                            RTL8367C_REG_PORT0_MISC_CFG\n#define    RTL8367C_PORT_MISC_CFG_REG(port)                        (RTL8367C_PORT_MISC_CFG_BASE + (port << 5))\n#define    RTL8367C_1QREMARK_ENABLE_OFFSET                         RTL8367C_PORT0_MISC_CFG_DOT1Q_REMARK_ENABLE_OFFSET\n#define    RTL8367C_1QREMARK_ENABLE_MASK                        RTL8367C_PORT0_MISC_CFG_DOT1Q_REMARK_ENABLE_MASK\n\n#define    RTL8367C_INGRESSBW_PORT_IFG_MASK                        RTL8367C_PORT0_MISC_CFG_INGRESSBW_IFG_MASK\n#define    RTL8367C_VLAN_EGRESS_MDOE_MASK                        RTL8367C_PORT0_MISC_CFG_VLAN_EGRESS_MODE_MASK\n#define    RTL8367C_SPECIALCONGEST_SUSTAIN_TIMER_MASK            RTL8367C_PORT0_MISC_CFG_CONGESTION_SUSTAIN_TIME_MASK\n\n#define    RTL8367C_INGRESSBW_PORT_RATE_LSB_BASE                RTL8367C_REG_INGRESSBW_PORT0_RATE_CTRL0\n#define    RTL8367C_INGRESSBW_PORT_RATE_LSB_REG(port)            (RTL8367C_INGRESSBW_PORT_RATE_LSB_BASE + (port << 5))\n\n#define    RTL8367C_PORT_SMALL_IPG_REG(port)                    (RTL8367C_REG_PORT0_MISC_CFG + (port*0x20))\n\n#define    RTL8367C_PORT_EEE_CFG_BASE                           RTL8367C_REG_PORT0_EEECFG\n#define    RTL8367C_PORT_EEE_CFG_REG(port)                      (RTL8367C_REG_PORT0_EEECFG + (port << 5))\n#define    RTL8367C_PORT_EEE_100M_OFFSET                        RTL8367C_PORT0_EEECFG_EEE_100M_OFFSET\n#define    RTL8367C_PORT_EEE_100M_MASK                          RTL8367C_PORT0_EEECFG_EEE_100M_MASK\n#define    RTL8367C_PORT_EEE_GIGA_OFFSET                        RTL8367C_PORT0_EEECFG_EEE_GIGA_500M_OFFSET\n#define    RTL8367C_PORT_EEE_GIGA_MASK                          RTL8367C_PORT0_EEECFG_EEE_GIGA_500M_MASK\n\n\n/* (16'h0200) outq_reg */\n\n#define    RTL8367C_FLOWCTRL_QUEUE_DROP_ON_BASE                    RTL8367C_REG_FLOWCTRL_QUEUE0_DROP_ON\n#define    RTL8367C_FLOWCTRL_QUEUE_DROP_ON_REG(queue)            (RTL8367C_FLOWCTRL_QUEUE_DROP_ON_BASE + queue)\n#define    RTL8367C_FLOWCTRL_QUEUE_DROP_ON_MASK                    RTL8367C_FLOWCTRL_QUEUE0_DROP_ON_MASK\n\n#define    RTL8367C_FLOWCTRL_PORT_DROP_ON_BASE                    RTL8367C_REG_FLOWCTRL_PORT0_DROP_ON\n#define    RTL8367C_FLOWCTRL_PORT_DROP_ON_REG(PORT)                (RTL8367C_FLOWCTRL_PORT_DROP_ON_BASE + PORT)\n#define    RTL8367C_FLOWCTRL_PORT_DROP_ON_MASK                    RTL8367C_FLOWCTRL_PORT0_DROP_ON_MASK\n\n#define    RTL8367C_FLOWCTRL_PORT_GAP_REG                        RTL8367C_REG_FLOWCTRL_PORT_GAP\n#define    RTL8367C_FLOWCTRL_QUEUE_GAP_REG                        RTL8367C_REG_FLOWCTRL_QUEUE_GAP\n#define    RTL8367C_FLOWCTRL_PORT_QEMPTY_REG                    RTL8367C_REG_PORT_QEMPTY\n\n/* (16'h0300) sch_reg */\n\n#define    RTL8367C_SCHEDULE_WFQ_BURST_SIZE_REG                    RTL8367C_REG_SCHEDULE_WFQ_BURST_SIZE\n\n#define    RTL8367C_SCHEDULE_QUEUE_TYPE_BASE                    RTL8367C_REG_SCHEDULE_QUEUE_TYPE_CTRL0\n#define    RTL8367C_SCHEDULE_QUEUE_TYPE_REG(port)                (RTL8367C_SCHEDULE_QUEUE_TYPE_BASE + (port >> 1))\n#define    RTL8367C_SCHEDULE_QUEUE_TYPE_OFFSET(port, queue)        (((port & 0x1) << 3) + queue)\n#define    RTL8367C_SCHEDULE_QUEUE_TYPE_MASK(port, queue)         RTL8367C_SCHEDULE_QUEUE_TYPE_OFFSET(port, queue)\n\n#define    RTL8367C_SCHEDULE_PORT_QUEUE_WFQ_WEIGHT_BASE            RTL8367C_REG_SCHEDULE_PORT0_QUEUE0_WFQ_WEIGHT\n#define    RTL8367C_SCHEDULE_PORT_QUEUE_WFQ_WEIGHT_REG(port, queue)    (RTL8367C_SCHEDULE_PORT_QUEUE_WFQ_WEIGHT_BASE + (port << 3) + queue)\n\n#define    RTL8367C_SCHEDULE_APR_CTRL_REG                       RTL8367C_REG_SCHEDULE_APR_CTRL0\n#define    RTL8367C_SCHEDULE_APR_CTRL_OFFSET(port)                (port)\n#define    RTL8367C_SCHEDULE_APR_CTRL_MASK(port)                (1 << RTL8367C_SCHEDULE_APR_CTRL_OFFSET(port))\n\n#define    RTL8367C_SCHEDULE_PORT_APR_METER_BASE                RTL8367C_REG_SCHEDULE_PORT0_APR_METER_CTRL0\n#define    RTL8367C_SCHEDULE_PORT_APR_METER_REG(port, queue)    (RTL8367C_SCHEDULE_PORT_APR_METER_BASE + (port << 2) + (queue / 5))\n#define    RTL8367C_SCHEDULE_PORT_APR_METER_OFFSET(queue)        (3 * (queue % 5))\n#define    RTL8367C_SCHEDULE_PORT_APR_METER_MASK(queue)            (RTL8367C_SCHEDULE_PORT0_APR_METER_CTRL0_QUEUE0_APR_METER_MASK << RTL8367C_SCHEDULE_PORT_APR_METER_OFFSET(queue))\n\n#define    RTL8367C_PORT_EGRESSBW_LSB_BASE                        RTL8367C_REG_PORT0_EGRESSBW_CTRL0\n#define    RTL8367C_PORT_EGRESSBW_LSB_REG(port)                    (RTL8367C_PORT_EGRESSBW_LSB_BASE + (port << 1))\n\n#define    RTL8367C_PORT_EGRESSBW_MSB_BASE                        RTL8367C_REG_PORT0_EGRESSBW_CTRL1\n#define    RTL8367C_PORT_EGRESSBW_MSB_REG(port)                    (RTL8367C_PORT_EGRESSBW_MSB_BASE + (port << 1))\n\n/* (16'h0500) table_reg */\n\n#define    RTL8367C_TABLE_ACCESS_CTRL_REG                        RTL8367C_REG_TABLE_ACCESS_CTRL\n\n#define    RTL8367C_TABLE_ACCESS_ADDR_REG                        RTL8367C_REG_TABLE_ACCESS_ADDR\n\n#define    RTL8367C_TABLE_ACCESS_STATUS_REG                        RTL8367C_REG_TABLE_LUT_ADDR\n\n#define    RTL8367C_TABLE_ACCESS_WRDATA_BASE                    RTL8367C_REG_TABLE_WRITE_DATA0\n#define    RTL8367C_TABLE_ACCESS_WRDATA_REG(index)                (RTL8367C_TABLE_ACCESS_WRDATA_BASE + index)\n\n#define    RTL8367C_TABLE_ACCESS_RDDATA_BASE                    RTL8367C_REG_TABLE_READ_DATA0\n#define    RTL8367C_TABLE_ACCESS_RDDATA_REG(index)                (RTL8367C_TABLE_ACCESS_RDDATA_BASE + index)\n\n\n\n/* (16'h0600) acl_reg */\n\n#define    RTL8367C_ACL_RULE_TEMPLATE_CTRL_BASE                    RTL8367C_REG_ACL_RULE_TEMPLATE0_CTRL0\n#define    RTL8367C_ACL_RULE_TEMPLATE_CTRL_REG(template)        (RTL8367C_ACL_RULE_TEMPLATE_CTRL_BASE + template * 0x4)\n#define    RTL8367C_ACL_TEMPLATE_FIELD_OFFSET(field)            ((field & 0x01) <<3)\n#define    RTL8367C_ACL_TEMPLATE_FIELD_MASK(field)                (0x3F << RTL8367C_ACL_TEMPLATE_FIELD_OFFSET(field))\n\n#define    RTL8367C_ACL_ACTION_CTRL_BASE                        RTL8367C_REG_ACL_ACTION_CTRL0\n#define    RTL8367C_ACL_ACTION_CTRL_REG(rule)                   (RTL8367C_ACL_ACTION_CTRL_BASE + (rule >> 1))\n#define    RTL8367C_ACL_ACTION_CTRL2_BASE                        RTL8367C_REG_ACL_ACTION_CTRL32\n#define    RTL8367C_ACL_ACTION_CTRL2_REG(rule)                  (RTL8367C_ACL_ACTION_CTRL2_BASE + ((rule-64) >> 1))\n\n#define    RTL8367C_ACL_OP_NOT_OFFSET(rule)                        (6 + ((rule & 0x1) << 3))\n#define    RTL8367C_ACL_OP_NOT_MASK(rule)                        (1 << RTL8367C_ACL_OP_NOT_OFFSET(rule))\n#define    RTL8367C_ACL_OP_ACTION_OFFSET(rule)                    ((rule & 0x1) << 3)\n#define    RTL8367C_ACL_OP_ACTION_MASK(rule)                    (0x3F << RTL8367C_ACL_OP_ACTION_OFFSET(rule))\n\n#define    RTL8367C_ACL_ENABLE_REG                                RTL8367C_REG_ACL_ENABLE\n#define    RTL8367C_ACL_UNMATCH_PERMIT_REG                        RTL8367C_REG_ACL_UNMATCH_PERMIT\n\n/* (16'h0700) cvlan_reg */\n\n#define    RTL8367C_VLAN_PVID_CTRL_BASE                            RTL8367C_REG_VLAN_PVID_CTRL0\n#define    RTL8367C_VLAN_PVID_CTRL_REG(port)                    (RTL8367C_VLAN_PVID_CTRL_BASE + (port >> 1))\n#define    RTL8367C_PORT_VIDX_OFFSET(port)                        ((port &1)<<3)\n#define    RTL8367C_PORT_VIDX_MASK(port)                        (RTL8367C_PORT0_VIDX_MASK << RTL8367C_PORT_VIDX_OFFSET(port))\n\n#define    RTL8367C_VLAN_PPB_VALID_BASE                            RTL8367C_REG_VLAN_PPB0_VALID\n#define    RTL8367C_VLAN_PPB_VALID_REG(item)                    (RTL8367C_VLAN_PPB_VALID_BASE + (item << 3))\n\n#define    RTL8367C_VLAN_PPB_CTRL_BASE                            RTL8367C_REG_VLAN_PPB0_CTRL0\n#define    RTL8367C_VLAN_PPB_CTRL_REG(item, port)               (RTL8367C_VLAN_PPB_CTRL_BASE + (item << 3) + (port / 3) )\n#define    RTL8367C_VLAN_PPB_CTRL_OFFSET(port)                    ((port % 3) * 5)\n#define    RTL8367C_VLAN_PPB_CTRL_MASK(port)                    (RTL8367C_VLAN_PPB0_CTRL0_PORT0_INDEX_MASK << RTL8367C_VLAN_PPB_CTRL_OFFSET(port))\n\n#define    RTL8367C_VLAN_PPB_FRAMETYPE_BASE                    RTL8367C_REG_VLAN_PPB0_CTRL2\n#define    RTL8367C_VLAN_PPB_FRAMETYPE_REG(item)               (RTL8367C_VLAN_PPB_FRAMETYPE_BASE + (item << 3))\n#define    RTL8367C_VLAN_PPB_FRAMETYPE_MASK                    RTL8367C_VLAN_PPB0_CTRL2_FRAME_TYPE_MASK\n\n#define    RTL8367C_VLAN_PPB_ETHERTYPR_BASE                        RTL8367C_REG_VLAN_PPB0_CTRL3\n#define    RTL8367C_VLAN_PPB_ETHERTYPR_REG(item)                (RTL8367C_VLAN_PPB_ETHERTYPR_BASE + (item << 3))\n\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION_BASE                RTL8367C_REG_VLAN_MEMBER_CONFIGURATION0_CTRL0\n\n\n#define    RTL8367C_VLAN_CTRL_REG                                RTL8367C_REG_VLAN_CTRL\n\n#define    RTL8367C_VLAN_INGRESS_REG                            RTL8367C_REG_VLAN_INGRESS\n\n#define    RTL8367C_VLAN_ACCEPT_FRAME_TYPE_BASE                    RTL8367C_REG_VLAN_ACCEPT_FRAME_TYPE_CTRL0\n#define    RTL8367C_VLAN_ACCEPT_FRAME_TYPE_REG(port)            (RTL8367C_VLAN_ACCEPT_FRAME_TYPE_BASE + (port >> 3))\n#define    RTL8367C_VLAN_ACCEPT_FRAME_TYPE_MASK(port)           (RTL8367C_PORT0_FRAME_TYPE_MASK << ((port & 0x7) << 1))\n\n#define    RTL8367C_PORT_EFID_BASE                                RTL8367C_REG_PORT_EFID_CTRL0\n#define    RTL8367C_PORT_EFID_REG(port)                            (RTL8367C_PORT_EFID_BASE + (port >> 2))\n#define    RTL8367C_PORT_EFID_OFFSET(port)                         ((port & 0x3) << 2)\n#define    RTL8367C_PORT_EFID_MASK(port)                        (RTL8367C_PORT0_EFID_MASK << RTL8367C_PORT_EFID_OFFSET(port))\n\n#define    RTL8367C_PORT_PBFIDEN_REG                            RTL8367C_REG_PORT_PBFIDEN\n\n#define    RTL8367C_PORT_PBFID_BASE                             RTL8367C_REG_PORT0_PBFID\n#define    RTL8367C_PORT_PBFID_REG(port)                        (RTL8367C_PORT_PBFID_BASE + port)\n\n/* (16'h0800) dpm_reg */\n\n#define    RTL8367C_RMA_CTRL_BASE                                RTL8367C_REG_RMA_CTRL00\n\n\n#define    RTL8367C_VLAN_PORTBASED_PRIORITY_BASE                RTL8367C_REG_VLAN_PORTBASED_PRIORITY_CTRL0\n#define    RTL8367C_VLAN_PORTBASED_PRIORITY_REG(port)            (RTL8367C_VLAN_PORTBASED_PRIORITY_BASE + (port >> 2))\n#define    RTL8367C_VLAN_PORTBASED_PRIORITY_OFFSET(port)        ((port & 0x3) << 2)\n#define    RTL8367C_VLAN_PORTBASED_PRIORITY_MASK(port)            (0x7 << RTL8367C_VLAN_PORTBASED_PRIORITY_OFFSET(port))\n\n#define    RTL8367C_VLAN_PPB_PRIORITY_ITEM_BASE                    RTL8367C_REG_VLAN_PPB_PRIORITY_ITEM0_CTRL0\n#define    RTL8367C_VLAN_PPB_PRIORITY_ITEM_REG(port, item)        (RTL8367C_VLAN_PPB_PRIORITY_ITEM_BASE + (item << 2)+ (port>>2))\n#define    RTL8367C_VLAN_PPB_PRIORITY_ITEM_OFFSET(port)            ((port & 0x3) <<2)\n#define    RTL8367C_VLAN_PPB_PRIORITY_ITEM_MASK(port)            (RTL8367C_VLAN_PPB_PRIORITY_ITEM0_CTRL0_PORT0_PRIORITY_MASK << RTL8367C_VLAN_PPB_PRIORITY_ITEM_OFFSET(port))\n\n#define    RTL8367C_QOS_1Q_PRIORITY_REMAPPING_BASE                RTL8367C_REG_QOS_1Q_PRIORITY_REMAPPING_CTRL0\n#define    RTL8367C_QOS_1Q_PRIORITY_REMAPPING_REG(pri)            (RTL8367C_QOS_1Q_PRIORITY_REMAPPING_BASE + (pri >> 2))\n#define    RTL8367C_QOS_1Q_PRIORITY_REMAPPING_OFFSET(pri)        ((pri & 0x3) << 2)\n#define    RTL8367C_QOS_1Q_PRIORITY_REMAPPING_MASK(pri)            (0x7 << RTL8367C_QOS_1Q_PRIORITY_REMAPPING_OFFSET(pri))\n\n#define    RTL8367C_QOS_DSCP_TO_PRIORITY_BASE                    RTL8367C_REG_QOS_DSCP_TO_PRIORITY_CTRL0\n#define    RTL8367C_QOS_DSCP_TO_PRIORITY_REG(dscp)                (RTL8367C_QOS_DSCP_TO_PRIORITY_BASE + (dscp >> 2))\n#define    RTL8367C_QOS_DSCP_TO_PRIORITY_OFFSET(dscp)            ((dscp & 0x3) << 2)\n#define    RTL8367C_QOS_DSCP_TO_PRIORITY_MASK(dscp)                (0x7 << RTL8367C_QOS_DSCP_TO_PRIORITY_OFFSET(dscp))\n\n#define    RTL8367C_QOS_PORTBASED_PRIORITY_BASE                    RTL8367C_REG_QOS_PORTBASED_PRIORITY_CTRL0\n#define    RTL8367C_QOS_PORTBASED_PRIORITY_REG(port)            (RTL8367C_QOS_PORTBASED_PRIORITY_BASE + (port >> 2))\n#define    RTL8367C_QOS_PORTBASED_PRIORITY_OFFSET(port)            ((port & 0x3) << 2)\n#define    RTL8367C_QOS_PORTBASED_PRIORITY_MASK(port)            (0x7 << RTL8367C_QOS_PORTBASED_PRIORITY_OFFSET(port))\n\n#define    RTL8367C_QOS_INTERNAL_PRIORITY_DECISION_BASE            RTL8367C_REG_QOS_INTERNAL_PRIORITY_DECISION_CTRL0\n#define    RTL8367C_QOS_INTERNAL_PRIORITY_DECISION_REG(src)        (RTL8367C_QOS_INTERNAL_PRIORITY_DECISION_BASE + (src >> 1))\n#define    RTL8367C_QOS_INTERNAL_PRIORITY_DECISION_OFFSET(src)  ((src & 1) << 3)\n#define    RTL8367C_QOS_INTERNAL_PRIORITY_DECISION_MASK(src)    (RTL8367C_QOS_INTERNAL_PRIORITY_DECISION_CTRL0_QOS_PORT_WEIGHT_MASK << RTL8367C_QOS_INTERNAL_PRIORITY_DECISION2_OFFSET(src))\n\n#define    RTL8367C_QOS_INTERNAL_PRIORITY_DECISION2_BASE            RTL8367C_REG_QOS_INTERNAL_PRIORITY_DECISION2_CTRL0\n#define    RTL8367C_QOS_INTERNAL_PRIORITY_DECISION2_REG(src)        (RTL8367C_QOS_INTERNAL_PRIORITY_DECISION2_BASE + (src >> 1))\n#define    RTL8367C_QOS_INTERNAL_PRIORITY_DECISION2_OFFSET(src)  ((src & 1) << 3)\n#define    RTL8367C_QOS_INTERNAL_PRIORITY_DECISION2_MASK(src)    (RTL8367C_QOS_INTERNAL_PRIORITY_DECISION2_CTRL0_QOS_PORT_WEIGHT_MASK << RTL8367C_QOS_INTERNAL_PRIORITY_DECISION2_OFFSET(src))\n\n#define    RTL8367C_QOS_INTERNAL_PRIORITY_DECISION_IDX_CTRL            RTL8367C_REG_QOS_INTERNAL_PRIORITY_DECISION_IDX\n#define    RTL8367C_QOS_INTERNAL_PRIORITY_DECISION_IDX(port)  (1 << port)\n\n#define    RTL8367C_QOS_PRIPORITY_REMAPPING_IN_CPU_BASE            RTL8367C_REG_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL0\n#define    RTL8367C_QOS_PRIPORITY_REMAPPING_IN_CPU_REG(pri)        (RTL8367C_QOS_PRIPORITY_REMAPPING_IN_CPU_BASE + (pri >> 2))\n#define    RTL8367C_QOS_PRIPORITY_REMAPPING_IN_CPU_OFFSET(pri)  ((pri & 0x3) << 2)\n#define    RTL8367C_QOS_PRIPORITY_REMAPPING_IN_CPU_MASK(pri)    (RTL8367C_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL0_PRIORITY0_MASK << RTL8367C_QOS_PRIPORITY_REMAPPING_IN_CPU_OFFSET(pri))\n\n#define    RTL8367C_QOS_TRAP_PRIORITY_CTRL0_REG                RTL8367C_REG_QOS_TRAP_PRIORITY0\n\n#define    RTL8367C_QOS_TRAP_PRIORITY_CTRL1_REG                RTL8367C_REG_QOS_TRAP_PRIORITY1\n\n#define    RTL8367C_QOS_DSCP_TO_DSCP_BASE                             RTL8367C_REG_QOS_DSCP_REMARK_DSCP_CTRL0\n#define    RTL8367C_QOS_DSCP_TO_DSCP_REG(dscp)                     (RTL8367C_REG_QOS_DSCP_REMARK_DSCP_CTRL0 + (dscp >> 1))\n#define    RTL8367C_QOS_DSCP_TO_DSCP_OFFSET(dscp)                ((dscp & 0x1) << 8)\n#define    RTL8367C_QOS_DSCP_TO_DSCP_MASK(dscp)                   (0x3F << RTL8367C_QOS_DSCP_TO_DSCP_OFFSET(dscp))\n\n#define    RTL8367C_UNUCAST_FLOADING_PMSK_REG                    RTL8367C_REG_UNDA_FLOODING_PMSK\n\n#define    RTL8367C_UNMCAST_FLOADING_PMSK_REG                    RTL8367C_REG_UNMCAST_FLOADING_PMSK\n\n#define    RTL8367C_BCAST_FLOADING_PMSK_REG                        RTL8367C_REG_BCAST_FLOADING_PMSK\n\n#define    RTL8367C_PORT_ISOLATION_PORT_MASK_BASE                RTL8367C_REG_PORT_ISOLATION_PORT0_MASK\n#define    RTL8367C_PORT_ISOLATION_PORT_MASK_REG(port)            (RTL8367C_PORT_ISOLATION_PORT_MASK_BASE + port)\n\n#define    RTL8367C_FORCE_CTRL_REG                                RTL8367C_REG_FORCE_CTRL\n\n#define    RTL8367C_SOURCE_PORT_BLOCK_REG                        RTL8367C_REG_SOURCE_PORT_PERMIT\n\n#define    RTL8367C_IPMCAST_VLAN_LEAKY_REG                        RTL8367C_REG_IPMCAST_VLAN_LEAKY\n\n#define    RTL8367C_IPMCAST_PORTISO_LEAKY_REG                    RTL8367C_REG_IPMCAST_PORTISO_LEAKY\n\n#define    RTL8367C_PORT_SECURIT_CTRL_REG                        RTL8367C_REG_PORT_SECURITY_CTRL\n\n#define    RTL8367C_UNKNOWN_IPV4_MULTICAST_BASE                    RTL8367C_REG_UNKNOWN_IPV4_MULTICAST_CTRL0\n#define    RTL8367C_UNKNOWN_IPV4_MULTICAST_REG(port)            (RTL8367C_UNKNOWN_IPV4_MULTICAST_BASE + (port >> 3))\n#define    RTL8367C_UNKNOWN_IPV4_MULTICAST_OFFSET(port)            ((port & 0x7) << 1)\n#define    RTL8367C_UNKNOWN_IPV4_MULTICAST_MASK(port)            (RTL8367C_PORT0_UNKNOWN_IP4_MCAST_MASK << RTL8367C_UNKNOWN_IPV4_MULTICAST_OFFSET(port))\n\n#define    RTL8367C_UNKNOWN_IPV6_MULTICAST_BASE                    RTL8367C_REG_UNKNOWN_IPV6_MULTICAST_CTRL0\n#define    RTL8367C_UNKNOWN_IPV6_MULTICAST_REG(port)            (RTL8367C_UNKNOWN_IPV6_MULTICAST_BASE + (port >> 3))\n#define    RTL8367C_UNKNOWN_IPV6_MULTICAST_OFFSET(port)            ((port & 0x7) << 1)\n#define    RTL8367C_UNKNOWN_IPV6_MULTICAST_MASK(port)            (RTL8367C_PORT0_UNKNOWN_IP4_MCAST_MASK << RTL8367C_UNKNOWN_IPV6_MULTICAST_OFFSET(port))\n\n#define    RTL8367C_UNKNOWN_L2_MULTICAST_BASE                    RTL8367C_REG_UNKNOWN_L2_MULTICAST_CTRL0\n#define    RTL8367C_UNKNOWN_L2_MULTICAST_REG(port)                (RTL8367C_UNKNOWN_L2_MULTICAST_BASE + (port >> 3))\n#define    RTL8367C_UNKNOWN_L2_MULTICAST_OFFSET(port)            ((port & 0x7) << 1)\n#define    RTL8367C_UNKNOWN_L2_MULTICAST_MASK(port)                (RTL8367C_PORT0_UNKNOWN_L2_MCAST_MASK << RTL8367C_UNKNOWN_L2_MULTICAST_OFFSET(port))\n\n#define    RTL8367C_PORT_TRUNK_CTRL_REG                            RTL8367C_REG_PORT_TRUNK_CTRL\n#define    RTL8367C_PORT_TRUNK_HASH_MASK                           0x007F\n\n#define    RTL8367C_PORT_TRUNK_GROUP_MASK_REG    RTL8367C_REG_PORT_TRUNK_GROUP_MASK\n#define    RTL8367C_PORT_TRUNK_GROUP_MASK_OFFSET(group)    (group << 2)\n#define    RTL8367C_PORT_TRUNK_GROUP_MASK_MASK(group)    (RTL8367C_PORT_TRUNK_GROUP0_MASK_MASK << RTL8367C_PORT_TRUNK_GROUP_MASK_OFFSET(group))\n\n#define    RTL8367C_PORT_TRUNK_FLOWCTRL_REG                        RTL8367C_REG_PORT_TRUNK_FLOWCTRL\n\n#define    RTL8367C_QOS_PORT_QUEUE_NUMBER_BASE                    RTL8367C_REG_QOS_PORT_QUEUE_NUMBER_CTRL0\n#define    RTL8367C_QOS_PORT_QUEUE_NUMBER_REG(port)                (RTL8367C_QOS_PORT_QUEUE_NUMBER_BASE + (port >> 2))\n#define    RTL8367C_QOS_PORT_QUEUE_NUMBER_OFFSET(port)            ((port & 0x3) << 2)\n#define    RTL8367C_QOS_PORT_QUEUE_NUMBER_MASK(port)            (0x7 << RTL8367C_QOS_PORT_QUEUE_NUMBER_OFFSET(port))\n\n#define    RTL8367C_QOS_1Q_PRIORITY_TO_QID_BASE                    RTL8367C_REG_QOS_1Q_PRIORITY_TO_QID_CTRL0\n#define    RTL8367C_QOS_1Q_PRIORITY_TO_QID_REG(index, pri)        (RTL8367C_QOS_1Q_PRIORITY_TO_QID_BASE + (index << 1) + (pri >> 2))\n#define    RTL8367C_QOS_1Q_PRIORITY_TO_QID_OFFSET(pri)            ((pri & 0x3) << 2)\n#define    RTL8367C_QOS_1Q_PRIORITY_TO_QID_MASK(pri)            (RTL8367C_QOS_1Q_PRIORITY_TO_QID_CTRL0_PRIORITY0_TO_QID_MASK << RTL8367C_QOS_1Q_PRIORITY_TO_QID_OFFSET(pri))\n\n#define    RTL8367C_DEBUG_INFO_BASE                                RTL8367C_REG_PORT_DEBUG_INFO_CTRL0\n#define    RTL8367C_DEBUG_INFO_REG(port)                        (RTL8367C_DEBUG_INFO_BASE + (port >>1))\n#define    RTL8367C_DEBUG_INFO_OFFSET(port)                        ((port&1)<<3)\n#define    RTL8367C_DEBUG_INFO_MASK(port)                        (RTL8367C_PORT0_DEBUG_INFO_MASK << RTL8367C_DEBUG_INFO_OFFSET(port))\n\n/* (16'h0a00) l2_reg */\n\n#define    RTL8367C_VLAN_MSTI_BASE                                RTL8367C_REG_VLAN_MSTI0_CTRL0\n#define    RTL8367C_VLAN_MSTI_REG(tree, port)                    (RTL8367C_VLAN_MSTI_BASE + (tree << 1) + (port >> 3))\n#define    RTL8367C_VLAN_MSTI_OFFSET(port)                        ((port & 0x7) << 1)\n#define    RTL8367C_VLAN_MSTI_MASK(port)                        (RTL8367C_VLAN_MSTI0_CTRL0_PORT0_STATE_MASK << RTL8367C_VLAN_MSTI_OFFSET(port))\n\n#define    RTL8367C_LUT_PORT_LEARN_LIMITNO_BASE                    RTL8367C_REG_LUT_PORT0_LEARN_LIMITNO\n#define    RTL8367C_LUT_PORT_LEARN_LIMITNO_REG(port)            (RTL8367C_LUT_PORT_LEARN_LIMITNO_BASE + port)\n\n#define    RTL8367C_LUT_CFG_REG                                    RTL8367C_REG_LUT_CFG\n\n#define    RTL8367C_LUT_AGEOUT_CTRL_REG                            RTL8367C_REG_LUT_AGEOUT_CTRL\n\n#define    RTL8367C_FORCE_FLUSH_REG                                RTL8367C_REG_FORCE_FLUSH\n\n#define    RTL8367C_STORM_BCAST_REG                                RTL8367C_REG_STORM_BCAST\n\n#define    RTL8367C_STORM_MCAST_REG                                RTL8367C_REG_STORM_MCAST\n\n#define    RTL8367C_STORM_UNKNOWN_UCAST_REG                        RTL8367C_REG_STORM_UNKOWN_UCAST\n\n#define    RTL8367C_STORM_UNKNOWN_MCAST_REG                        RTL8367C_REG_STORM_UNKOWN_MCAST\n\n#define    RTL8367C_STORM_BCAST_METER_CTRL_BASE                    RTL8367C_REG_STORM_BCAST_METER_CTRL0\n#define    RTL8367C_STORM_BCAST_METER_CTRL_REG(port)            (RTL8367C_STORM_BCAST_METER_CTRL_BASE + (port >> 1))\n#define    RTL8367C_STORM_BCAST_METER_CTRL_OFFSET(port)            ((port & 0x1) << 3)\n#define    RTL8367C_STORM_BCAST_METER_CTRL_MASK(port)            (0xFF << RTL8367C_STORM_BCAST_METER_CTRL_OFFSET(port))\n\n#define    RTL8367C_STORM_MCAST_METER_CTRL_BASE                    RTL8367C_REG_STORM_MCAST_METER_CTRL0\n#define    RTL8367C_STORM_MCAST_METER_CTRL_REG(port)            (RTL8367C_STORM_MCAST_METER_CTRL_BASE + (port >> 1))\n#define    RTL8367C_STORM_MCAST_METER_CTRL_OFFSET(port)            ((port & 0x1) << 3)\n#define    RTL8367C_STORM_MCAST_METER_CTRL_MASK(port)            (0xFF << RTL8367C_STORM_MCAST_METER_CTRL_OFFSET(port))\n\n#define    RTL8367C_STORM_UNDA_METER_CTRL_BASE                    RTL8367C_REG_STORM_UNDA_METER_CTRL0\n#define    RTL8367C_STORM_UNDA_METER_CTRL_REG(port)                (RTL8367C_STORM_UNDA_METER_CTRL_BASE + (port >> 1))\n#define    RTL8367C_STORM_UNDA_METER_CTRL_OFFSET(port)            ((port & 0x1) << 3)\n#define    RTL8367C_STORM_UNDA_METER_CTRL_MASK(port)            (0xFF << RTL8367C_STORM_UNDA_METER_CTRL_OFFSET(port))\n\n#define    RTL8367C_STORM_UNMC_METER_CTRL_BASE                    RTL8367C_REG_STORM_UNMC_METER_CTRL0\n#define    RTL8367C_STORM_UNMC_METER_CTRL_REG(port)                (RTL8367C_STORM_UNMC_METER_CTRL_BASE + (port >> 1))\n#define    RTL8367C_STORM_UNMC_METER_CTRL_OFFSET(port)            ((port & 0x1) << 3)\n#define    RTL8367C_STORM_UNMC_METER_CTRL_MASK(port)            (0xFF << RTL8367C_STORM_UNMC_METER_CTRL_OFFSET(port))\n\n#define    RTL8367C_OAM_PARSER_OFFSET(port)                        (port*2)\n#define    RTL8367C_OAM_PARSER_MASK(port)                        (RTL8367C_PORT0_PARACT_MASK << RTL8367C_OAM_PARSER_OFFSET(port))\n\n#define    RTL8367C_OAM_MULTIPLEXER_OFFSET(port)                (port*2)\n#define    RTL8367C_OAM_MULTIPLEXER_MASK(port)                    (RTL8367C_PORT0_PARACT_MASK << RTL8367C_OAM_MULTIPLEXER_OFFSET(port))\n\n#define    RTL8367C_OAM_CTRL_REG                                RTL8367C_REG_OAM_CTRL\n\n#define    RTL8367C_DOT1X_PORT_ENABLE_REG                        RTL8367C_REG_DOT1X_PORT_ENABLE\n\n#define    RTL8367C_DOT1X_MAC_ENABLE_REG                        RTL8367C_REG_DOT1X_MAC_ENABLE\n\n#define    RTL8367C_DOT1X_PORT_AUTH_REG                            RTL8367C_REG_DOT1X_PORT_AUTH\n\n#define    RTL8367C_DOT1X_PORT_OPDIR_REG                        RTL8367C_REG_DOT1X_PORT_OPDIR\n\n#define    RTL8367C_DOT1X_UNAUTH_ACT_BASE                        RTL8367C_REG_DOT1X_UNAUTH_ACT_W0\n#define    RTL8367C_DOT1X_UNAUTH_ACT_OFFSET(port)                ((port & 0x7) << 1)\n#define    RTL8367C_DOT1X_UNAUTH_ACT_MASK(port)                    (RTL8367C_DOT1X_PORT0_UNAUTHBH_MASK << RTL8367C_DOT1X_UNAUTH_ACT_OFFSET(port))\n\n#define    RTL8367C_DOT1X_CFG_REG                                RTL8367C_REG_DOT1X_CFG\n\n#define    RTL8367C_REG_L2_LRN_CNT_BASE                            RTL8367C_REG_L2_LRN_CNT_CTRL0\n#define    RTL8367C_REG_L2_LRN_CNT_REG(port)                    (RTL8367C_REG_L2_LRN_CNT_BASE + port)\n\n/* (16'h0b00) mltvlan_reg */\n\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY_BASE_REG(index)        (RTL8367C_REG_SVLAN_MCAST2S_ENTRY0_CTRL0 + index*5)\n\n/* (16'h0c00) svlan_reg */\n\n#define    RTL8367C_SVLAN_MEMBERCFG_BASE_REG(index)                (RTL8367C_REG_SVLAN_MEMBERCFG0_CTRL1 + index*3)\n#define    RTL8367C_SVLAN_C2SCFG_BASE_REG(index)                  (RTL8367C_REG_SVLAN_C2SCFG0_CTRL0+ index*3)\n#define    RTL8367C_SVLAN_CFG_REG                                RTL8367C_REG_SVLAN_CFG\n\n/* (16'h0f00) hsactrl_reg */\n\n#define    RTL8367C_SVLAN_S2C_ENTRY_BASE_REG(index)                (RTL8367C_REG_SVLAN_SP2C_ENTRY0_CTRL0 + index*2)\n\n/* (16'h1000) mib_reg */\n\n#define    RTL8367C_MIB_COUNTER_BASE_REG                        RTL8367C_REG_MIB_COUNTER0\n\n#define    RTL8367C_MIB_ADDRESS_REG                                RTL8367C_REG_MIB_ADDRESS\n\n#define    RTL8367C_MIB_CTRL_REG                                RTL8367C_REG_MIB_CTRL0\n#define    RTL8367C_MIB_PORT07_MASK                                (0xFF<<RTL8367C_PORT0_RESET_OFFSET)\n\n/* (16'h1100) intrpt_reg */\n\n#define    RTL8367C_INTR_CTRL_REG                                RTL8367C_REG_INTR_CTRL\n\n#define    RTL8367C_INTR_IMR_REG                                RTL8367C_REG_INTR_IMR\n\n#define    RTL8367C_INTR_IMS_REG                                RTL8367C_REG_INTR_IMS\n\n#define    RTL8367C_INTR_INDICATOR_BASED                        RTL8367C_REG_LEARN_OVER_INDICATOR\n#define    RTL8367C_LEARN_OVER_INDICATOR_REG                    RTL8367C_REG_LEARN_OVER_INDICATOR\n\n#define    RTL8367C_SPEED_CHANGE_INDICATOR_REG                    RTL8367C_REG_SPEED_CHANGE_INDICATOR\n\n#define    RTL8367C_PORT_LINKDOWN_INDICATOR_REG                    RTL8367C_REG_PORT_LINKDOWN_INDICATOR\n\n#define    RTL8367C_PORT_LINKUP_INDICATOR_REG                    RTL8367C_REG_PORT_LINKUP_INDICATOR\n\n#define    RTL8367C_REG_METER_EXCEED_INDICATOR_BASE                RTL8367C_REG_METER_EXCEED_INDICATOR0\n#define    RTL8367C_REG_METER_EXCEED_INDICATOR_REG(meter)        (RTL8367C_REG_METER_EXCEED_INDICATOR_BASE + (meter >> 4))\n#define    RTL8367C_REG_METER_EXCEED_INDICATOR_OFFSET(meter)    (meter & 0xF)\n\n/* (16'h1200) swcore_reg */\n\n#define    RTL8367C_VS_TPID_REG                                    RTL8367C_REG_VS_TPID\n\n#define    RTL8367C_SWITCH_MAC_BASE                                RTL8367C_REG_SWITCH_MAC0\n\n#define    RTL8367C_REMARKING_CTRL_REG                            RTL8367C_REG_SWITCH_CTRL0\n\n#define    RTL8367C_QOS_DSCP_REMARK_BASE                        RTL8367C_REG_QOS_DSCP_REMARK_CTRL0\n#define    RTL8367C_QOS_DSCP_REMARK_REG(pri)                    (RTL8367C_QOS_DSCP_REMARK_BASE + (pri >> 1))\n#define    RTL8367C_QOS_DSCP_REMARK_OFFSET(pri)                    (((pri) & 0x1) << 3)\n#define    RTL8367C_QOS_DSCP_REMARK_MASK(pri)                    (0x3F << RTL8367C_QOS_DSCP_REMARK_OFFSET(pri))\n\n#define    RTL8367C_QOS_1Q_REMARK_BASE                            RTL8367C_REG_QOS_1Q_REMARK_CTRL0\n#define    RTL8367C_QOS_1Q_REMARK_REG(pri)                        (RTL8367C_QOS_1Q_REMARK_BASE + (pri >> 2))\n#define    RTL8367C_QOS_1Q_REMARK_OFFSET(pri)                    ((pri & 0x3) << 2)\n#define    RTL8367C_QOS_1Q_REMARK_MASK(pri)                        (0x7 << RTL8367C_QOS_1Q_REMARK_OFFSET(pri))\n\n#define    RTL8367C_PTKGEN_PAYLOAD_CTRL0_REG                    RTL8367C_REG_PTKGEN_PAYLOAD_CTRL0\n\n#define    RTL8367C_PTKGEN_PAYLOAD_CTRL1_REG                    RTL8367C_REG_PTKGEN_PAYLOAD_CTRL1\n\n#define    RTL8367C_SVLAN_UPLINK_PORTMASK_REG                    RTL8367C_REG_SVLAN_UPLINK_PORTMASK\n\n#define    RTL8367C_CPU_PORT_MASK_REG                            RTL8367C_REG_CPU_PORT_MASK\n\n#define    RTL8367C_CPU_CTRL_REG                                RTL8367C_REG_CPU_CTRL\n\n#define    RTL8367C_MIRROR_CTRL_REG                                RTL8367C_REG_MIRROR_CTRL\n\n\n#define    RTL8367C_FLOWCRTL_EGRESS_QUEUE_ENABLE_BASE            RTL8367C_REG_FLOWCRTL_EGRESS_QUEUE_ENABLE_CTRL0\n#define    RTL8367C_FLOWCRTL_EGRESS_QUEUE_ENABLE_REG(port)        (RTL8367C_FLOWCRTL_EGRESS_QUEUE_ENABLE_BASE + (port >> 1))\n#define    RTL8367C_FLOWCRTL_EGRESS_QUEUE_ENABLE_REG_OFFSET(port)    ((port & 0x1) << 3)\n#define    RTL8367C_FLOWCRTL_EGRESS_QUEUE_ENABLE_REG_MASK(port)    (RTL8367C_PORT0_QUEUE_MASK_MASK << RTL8367C_FLOWCRTL_EGRESS_QUEUE_ENABLE_REG_OFFSET(port))\n\n\n#define    RTL8367C_FLOWCTRL_PORT_PAGE_COUNTER_BASE                RTL8367C_REG_FLOWCTRL_PORT0_PAGE_COUNTER\n#define    RTL8367C_FLOWCTRL_PORT_PAGE_COUNTER_REG(port)        (RTL8367C_FLOWCTRL_PORT_PAGE_COUNTER_BASE + port)\n#define    RTL8367C_FLOWCTRL_PORT_PAGE_COUNTER_MASK                RTL8367C_FLOWCTRL_PORT0_PAGE_COUNTER_MASK\n\n#define    RTL8367C_FLOWCTRL_PORT_PAGE_MAX_BASE                    RTL8367C_REG_FLOWCTRL_PORT0_PAGE_MAX\n#define    RTL8367C_FLOWCTRL_PORT_PAGE_MAX_REG(port)            (RTL8367C_FLOWCTRL_PORT_PAGE_MAX_BASE + port)\n#define    RTL8367C_FLOWCTRL_PORT_PAGE_MAX_MASK                    RTL8367C_FLOWCTRL_PORT0_PAGE_MAX_MASK\n\n#define    RTL8367C_FIELD_SELECTOR_REG(index)                    (RTL8367C_REG_FIELD_SELECTOR0 + index)\n#define    RTL8367C_FIELD_SELECTOR_ENABLE_OFFSET                 RTL8367C_FIELD_SELECTOR0_ENABLE_OFFSET\n#define    RTL8367C_FIELD_SELECTOR_ENABLE_MASK                    RTL8367C_FIELD_SELECTOR0_ENABLE_MASK\n#define    RTL8367C_FIELD_SELECTOR_FORMAT_OFFSET                RTL8367C_FIELD_SELECTOR0_FORMAT_OFFSET\n#define    RTL8367C_FIELD_SELECTOR_FORMAT_MASK                    RTL8367C_FIELD_SELECTOR0_FORMAT_MASK\n#define    RTL8367C_FIELD_SELECTOR_OFFSET_OFFSET                  RTL8367C_FIELD_SELECTOR0_OFFSET_OFFSET\n#define    RTL8367C_FIELD_SELECTOR_OFFSET_MASK                    RTL8367C_FIELD_SELECTOR0_OFFSET_MASK\n\n/* (16'h1300) chip_reg*/\n\n/* (16'h1400) mtrpool_reg */\n#define    RTL8367C_METER_RATE_BASE                                RTL8367C_REG_METER0_RATE_CTRL0\n#define    RTL8367C_METER_RATE_REG(meter)                        ((meter << 1) + RTL8367C_METER_RATE_BASE)\n\n#define    RTL8367C_METER_BUCKET_SIZE_BASE                        RTL8367C_REG_METER0_BUCKET_SIZE\n#define    RTL8367C_METER_BUCKET_SIZE_REG(meter)                (RTL8367C_METER_BUCKET_SIZE_BASE + meter)\n\n#define    RTL8367C_LEAKY_BUCKET_TICK_REG                        RTL8367C_REG_METER_CTRL0\n#define    RTL8367C_LEAKY_BUCKET_TICK_OFFSET                    RTL8367C_METER_TICK_OFFSET\n#define    RTL8367C_LEAKY_BUCKET_TICK_MASK                        RTL8367C_METER_TICK_MASK\n\n#define    RTL8367C_LEAKY_BUCKET_TOKEN_REG                        RTL8367C_REG_METER_CTRL1\n#define    RTL8367C_LEAKY_BUCKET_TOKEN_OFFSET                    RTL8367C_METER_CTRL1_OFFSET\n#define    RTL8367C_LEAKY_BUCKET_TOKEN_MASK                        RTL8367C_METER_CTRL1_MASK\n\n#define    RTL8367C_METER_OVERRATE_INDICATOR_BASE                RTL8367C_REG_METER_OVERRATE_INDICATOR0\n#define    RTL8367C_METER_OVERRATE_INDICATOR_REG(meter)            (RTL8367C_METER_OVERRATE_INDICATOR_BASE + (meter >> 4))\n#define    RTL8367C_METER_EXCEED_OFFSET(meter)                    (meter & 0xF)\n#define    RTL8367C_METER_EXCEED_MASK(meter)                    (1 << RTL8367C_METER_EXCEED_OFFSET(meter))\n\n#define    RTL8367C_METER_IFG_CTRL_BASE                            RTL8367C_REG_METER_IFG_CTRL0\n#define    RTL8367C_METER_IFG_CTRL_REG(meter)                    (RTL8367C_METER_IFG_CTRL_BASE + (meter >> 4))\n#define    RTL8367C_METER_IFG_OFFSET(meter)                        (meter & 0xF)\n#define    RTL8367C_METER_IFG_MASK(meter)                        (1 << RTL8367C_METER_IFG_OFFSET(meter))\n\n#define    RTL8367C_FLOWCTRL_CTRL_REG                            RTL8367C_REG_FLOWCTRL_CTRL0\n\n/* (16'h1800)8051_RLDP_EEE_reg */\n#define    RTL8367C_EEELLDP_CTRL0_REG                            RTL8367C_REG_EEELLDP_CTRL0\n\n#define    RTL8367C_EEELLDP_CTRL1_REG                            RTL8367C_REG_EEELLDP_CTRL1\n\n#define    RTL8367C_EEELLDP_PMSK_REG                            RTL8367C_REG_EEELLDP_PMSK\n\n#define    RTL8367C_EEELLDP_TX_FRAMEU_REG_BASE                    RTL8367C_REG_EEELLDP_FRAMEU00\n\n#define    RTL8367C_EEELLDP_TX_CAP_FRAMEL_REG_BASE                RTL8367C_REG_EEELLDP_CAP_FRAMEL00\n\n#define    RTL8367C_EEELLDP_RX_VALUE_PORT_BASE                    RTL8367C_REG_EEELLDP_RX_VALUE_P00_00\n#define    RTL8367C_EEELLDP_RX_VALUE_PORT_REG(port)                (RTL8367C_EEELLDP_RX_VALUE_PORT_BASE + (port * 9))\n\n#define    RTL8367C_RLDP_CTRL0_REG                                RTL8367C_REG_RLDP_CTRL0\n#define    RTL8367C_RLDP_MODE_OFFSET    14\n\n#define    RTL8367C_RLDP_RETRY_COUNT_REG                        RTL8367C_REG_RLDP_CTRL1\n\n#define    RTL8367C_RLDP_RETRY_PERIOD_LOOPSTATE_REG                RTL8367C_REG_RLDP_CTRL2\n\n#define    RTL8367C_RLDP_RETRY_PERIOD_CHKSTATE_REG                RTL8367C_REG_RLDP_CTRL3\n\n#define    RTL8367C_RLDP_TX_PMSK_REG                            RTL8367C_REG_RLDP_CTRL4\n\n#define    RTL8367C_RLDP_RAND_NUM_REG_BASE                        RTL8367C_REG_RLDP_RAND_NUM0\n\n#define    RTL8367C_RLDP_MAGIC_NUM_REG_BASE                        RTL8367C_REG_RLDP_MAGIC_NUM0\n\n#define    RTL8367C_RLDP_LOOP_PMSK_REG                            RTL8367C_REG_RLDP_LOOPSTATUS_INDICATOR\n\n#define    RTL8367C_RLDP_LOOP_PORT_BASE                            RTL8367C_REG_RLDP_LOOP_PORT_REG0\n#define    RTL8367C_RLDP_LOOP_PORT_REG(port)                    (RTL8367C_RLDP_LOOP_PORT_BASE + (port >> 1))\n#define    RTL8367C_RLDP_LOOP_PORT_OFFSET(port)                    ((port & 0x1) << 3)\n#define    RTL8367C_RLDP_LOOP_PORT_MASK(port)                    (RTL8367C_RLDP_LOOP_PORT_00_MASK << RTL8367C_RLDP_LOOP_PORT_OFFSET(port))\n\n#define    RTL8367C_PAGEMETER_PORT_BASE                            RTL8367C_REG_PAGEMETER_PORT0_CTRL0\n#define    RTL8367C_PAGEMETER_PORT_REG(port)                    (RTL8367C_PAGEMETER_PORT_BASE + 0x20*port)\n\n#define    RTL8367C_HIGHPRI_INDICATOR_REG                        RTL8367C_REG_HIGHPRI_INDICATOR\n#define    RTL8367C_PORT_INDICATOR_OFFSET(port)                    (port)\n#define    RTL8367C_PORT_INDICATOR_MASK(port)                    (RTL8367C_PORT0_INDICATOR_MASK << RTL8367C_PORT_INDICATOR_OFFSET(port))\n\n#define    RTL8367C_HIGHPRI_CFG_REG                                RTL8367C_REG_HIGHPRI_CFG\n\n#define    RTL8367C_EAV_PRIORITY_REMAPPING_BASE                    RTL8367C_REG_EAV_CTRL1\n#define    RTL8367C_EAV_PRIORITY_REMAPPING_REG(pri)                (RTL8367C_EAV_PRIORITY_REMAPPING_BASE + (pri >> 2))\n#define    RTL8367C_EAV_PRIORITY_REMAPPING_OFFSET(pri)            ((pri & 0x3) * RTL8367C_REMAP_EAV_PRI1_REGEN_OFFSET)\n#define    RTL8367C_EAV_PRIORITY_REMAPPING_MASK(pri)            (RTL8367C_REMAP_EAV_PRI0_REGEN_MASK << RTL8367C_EAV_PRIORITY_REMAPPING_OFFSET(pri))\n\n#define    RTL8367C_EEEP_CFG_BASE                                RTL8367C_REG_PORT0_EEECFG\n#define    RTL8367C_EEEP_CFG_REG(port)                            (RTL8367C_EEEP_CFG_BASE + (port*0x20))\n\n#define    RTL8367C_PKG_CFG_BASE                                RTL8367C_REG_PKTGEN_PORT0_CTRL\n#define    RTL8367C_PKG_CFG_REG(port)                            (RTL8367C_PKG_CFG_BASE + (port*0x20))\n\n#define    RTL8367C_PKG_DA_BASE                                    RTL8367C_REG_PKTGEN_PORT0_DA0\n#define    RTL8367C_PKG_DA_REG(port)                            (RTL8367C_PKG_DA_BASE + (port*0x20))\n\n#define    RTL8367C_PKG_SA_BASE                                    RTL8367C_REG_PKTGEN_PORT0_SA0\n#define    RTL8367C_PKG_SA_REG(port)                            (RTL8367C_PKG_SA_BASE + (port*0x20))\n\n#define    RTL8367C_PKG_NUM_BASE                                RTL8367C_REG_PKTGEN_PORT0_COUNTER0\n#define    RTL8367C_PKG_NUM_REG(port)                            (RTL8367C_PKG_NUM_BASE + (port*0x20))\n\n#define    RTL8367C_PKG_LENGTH_BASE                                RTL8367C_REG_PKTGEN_PORT0_TX_LENGTH\n#define    RTL8367C_PKG_LENGTH_REG(port)                        (RTL8367C_PKG_LENGTH_BASE + (port*0x20))\n\n/* (16'h1c00)IGMP_MLD_reg */\n#define    RTL8367C_IGMP_GROUP_USAGE_BASE                       RTL8367C_REG_IGMP_GROUP_USAGE_LIST0\n#define    RTL8367C_IGMP_GROUP_USAGE_REG(idx)                   (RTL8367C_IGMP_GROUP_USAGE_BASE + (idx / 16))\n\n#define    RTL8367C_FALLBACK_BASE                               RTL8367C_REG_FALLBACK_PORT0_CFG0\n#define    RTL8367C_FALLBACK_PORT_CFG_REG(port)                 (RTL8367C_FALLBACK_BASE + (port * 4))\n#define    RTL8367C_FALLBACK_PORT_MON_CNT_REG(port)             (RTL8367C_FALLBACK_BASE + 1 + (port * 4))\n#define    RTL8367C_FALLBACK_PORT_ERR_CNT_REG(port)             (RTL8367C_FALLBACK_BASE + 3 + (port * 4))\n\n\n/* (16'h6400)timer_1588 */\n#define    RTL8367C_EAV_CFG_BASE                                              RTL8367C_REG_P0_EAV_CFG\n#define    RTL8367C_EAV_PORT_CFG_REG(port)                              (RTL8367C_EAV_CFG_BASE + (port *0x10))\n#define    RTL8367C_EAV_CFG_PTP_PHY_EN_EN_OFFSET                 RTL8367C_P0_EAV_CFG_PTP_PHY_EN_EN_OFFSET\n#define    RTL8367C_EAV_CFG_RX_PDELAY_RESP_OFFSET                RTL8367C_P0_EAV_CFG_RX_PDELAY_RESP_OFFSET\n#define    RTL8367C_EAV_CFG_RX_PDELAY_REQ_OFFSET                 RTL8367C_P0_EAV_CFG_RX_PDELAY_REQ_OFFSET\n#define    RTL8367C_EAV_CFG_RX_DELAY_REQ_OFFSET                   RTL8367C_P0_EAV_CFG_RX_DELAY_REQ_OFFSET\n#define    RTL8367C_EAV_CFG_RX_SYNC_OFFSET                            RTL8367C_P0_EAV_CFG_RX_SYNC_OFFSET\n#define    RTL8367C_EAV_CFG_TX_PDELAY_RESP_OFFSET                RTL8367C_P0_EAV_CFG_TX_PDELAY_RESP_OFFSET\n#define    RTL8367C_EAV_CFG_TX_PDELAY_REQ_OFFSET                 RTL8367C_P0_EAV_CFG_TX_PDELAY_REQ_OFFSET\n#define    RTL8367C_EAV_CFG_TX_DELAY_REQ_OFFSET                   RTL8367C_P0_EAV_CFG_TX_DELAY_REQ_OFFSET\n#define    RTL8367C_EAV_CFG_TX_SYNC_OFFSET                            RTL8367C_P0_EAV_CFG_TX_SYNC_OFFSET\n\n#define    RTL8367C_REG_TX_SYNC_SEQ_ID_BASE                       RTL8367C_REG_P0_TX_SYNC_SEQ_ID\n#define    RTL8367C_REG_TX_SYNC_SEQ_ID(port)                        (RTL8367C_REG_TX_SYNC_SEQ_ID_BASE + (port *0x10))\n#define    RTL8367C_REG_SEQ_ID(port, type)                              (RTL8367C_REG_TX_SYNC_SEQ_ID_BASE + type + (port *0x10))\n\n#define    RTL8367C_REG_TX_DELAY_REQ_SEQ_ID_BASE              RTL8367C_REG_P0_TX_DELAY_REQ_SEQ_ID\n#define    RTL8367C_REG_TX_PDELAY_REQ_SEQ_ID_BASE          RTL8367C_REG_P0_TX_PDELAY_REQ_SEQ_ID\n#define    RTL8367C_REG_TX_PDELAY_RESP_SEQ_ID_BASE        RTL8367C_REG_P0_TX_PDELAY_RESP_SEQ_ID\n#define    RTL8367C_REG_RX_SYNC_SEQ_ID_BASE                        RTL8367C_REG_P0_RX_SYNC_SEQ_ID\n#define    RTL8367C_REG_RX_DELAY_REQ_SEQ_ID_BASE            RTL8367C_REG_P0_RX_DELAY_REQ_SEQ_ID\n#define    RTL8367C_REG_RX_PDELAY_REQ_SEQ_ID_BASE        RTL8367C_REG_P0_RX_PDELAY_REQ_SEQ_ID\n#define    RTL8367C_REG_RX_PDELAY_RESP_SEQ_ID_BASE        RTL8367C_REG_P0_RX_PDELAY_RESP_SEQ_ID\n\n#define    RTL8367C_REG_PORT_NSEC_L_BASE                            RTL8367C_REG_P0_PORT_NSEC_15_0\n#define    RTL8367C_REG_PORT_NSEC_L(port)                            (RTL8367C_REG_PORT_NSEC_L_BASE + (port *0x10))\n#define    RTL8367C_REG_PORT_NSEC_H_BASE                            RTL8367C_REG_P0_PORT_NSEC_26_16\n#define    RTL8367C_REG_PORT_NSEC_H(port)                            (RTL8367C_REG_PORT_NSEC_H_BASE + (port *0x10))\n#define    RTL8367C_PORT_NSEC_H_OFFSET                                RTL8367C_P0_PORT_NSEC_26_16_OFFSET\n#define    RTL8367C_PORT_NSEC_H_MASK                                   RTL8367C_P0_PORT_NSEC_26_16_MASK\n\n#define    RTL8367C_REG_PORT_SEC_L_BASE                                RTL8367C_REG_P0_PORT_SEC_15_0\n#define    RTL8367C_REG_PORT_SEC_L(port)                            (RTL8367C_REG_PORT_SEC_L_BASE + (port *0x10))\n#define    RTL8367C_REG_PORT_SEC_H_BASE                            RTL8367C_REG_P0_PORT_SEC_31_16\n#define    RTL8367C_REG_PORT_SEC_H(port)                            (RTL8367C_REG_PORT_SEC_H_BASE + (port *0x10))\n\n#endif /*#ifndef _RTL8367C_BASE_H_*/\n\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/rtl8367c_reg.h",
    "content": "#ifndef _RTL8367C_REG_H_\n#define _RTL8367C_REG_H_\n\n/************************************************************\nauto-generated register address and field data\n*************************************************************/\n\n/* (16'h0000)port_reg */\n\n#define    RTL8367C_REG_PORT0_CGST_HALF_CFG    0x0000\n#define    RTL8367C_PORT0_CGST_HALF_CFG_CONGESTION_TIME_OFFSET    4\n#define    RTL8367C_PORT0_CGST_HALF_CFG_CONGESTION_TIME_MASK    0xF0\n#define    RTL8367C_PORT0_CGST_HALF_CFG_CONGESTION_SUSTAIN_TIME_OFFSET    0\n#define    RTL8367C_PORT0_CGST_HALF_CFG_CONGESTION_SUSTAIN_TIME_MASK    0xF\n\n#define    RTL8367C_REG_PKTGEN_PORT0_CTRL    0x0001\n#define    RTL8367C_PKTGEN_PORT0_CTRL_STATUS_OFFSET    15\n#define    RTL8367C_PKTGEN_PORT0_CTRL_STATUS_MASK    0x8000\n#define    RTL8367C_PKTGEN_PORT0_CTRL_PKTGEN_STS_OFFSET    13\n#define    RTL8367C_PKTGEN_PORT0_CTRL_PKTGEN_STS_MASK    0x2000\n#define    RTL8367C_PKTGEN_PORT0_CTRL_CRC_NO_ERROR_OFFSET    4\n#define    RTL8367C_PKTGEN_PORT0_CTRL_CRC_NO_ERROR_MASK    0x10\n#define    RTL8367C_PKTGEN_PORT0_CTRL_CMD_START_OFFSET    0\n#define    RTL8367C_PKTGEN_PORT0_CTRL_CMD_START_MASK    0x1\n\n#define    RTL8367C_REG_TX_ERR_CNT_PORT0    0x0002\n#define    RTL8367C_TX_ERR_CNT_PORT0_OFFSET    0\n#define    RTL8367C_TX_ERR_CNT_PORT0_MASK    0x7\n\n#define    RTL8367C_REG_PKTGEN_PORT0_DA0    0x0003\n\n#define    RTL8367C_REG_PKTGEN_PORT0_DA1    0x0004\n\n#define    RTL8367C_REG_PKTGEN_PORT0_DA2    0x0005\n\n#define    RTL8367C_REG_PKTGEN_PORT0_SA0    0x0006\n\n#define    RTL8367C_REG_PKTGEN_PORT0_SA1    0x0007\n\n#define    RTL8367C_REG_PKTGEN_PORT0_SA2    0x0008\n\n#define    RTL8367C_REG_PKTGEN_PORT0_COUNTER0    0x0009\n\n#define    RTL8367C_REG_PKTGEN_PORT0_COUNTER1    0x000a\n#define    RTL8367C_PKTGEN_PORT0_COUNTER1_OFFSET    0\n#define    RTL8367C_PKTGEN_PORT0_COUNTER1_MASK    0xFF\n\n#define    RTL8367C_REG_PKTGEN_PORT0_TX_LENGTH    0x000b\n#define    RTL8367C_PKTGEN_PORT0_TX_LENGTH_OFFSET    0\n#define    RTL8367C_PKTGEN_PORT0_TX_LENGTH_MASK    0x3FFF\n\n#define    RTL8367C_REG_PKTGEN_PORT0_TIMER    0x000d\n#define    RTL8367C_PKTGEN_PORT0_TIMER_TIMER_OFFSET    4\n#define    RTL8367C_PKTGEN_PORT0_TIMER_TIMER_MASK    0xF0\n#define    RTL8367C_PKTGEN_PORT0_TIMER_RX_DMA_ERR_FLAG_OFFSET    3\n#define    RTL8367C_PKTGEN_PORT0_TIMER_RX_DMA_ERR_FLAG_MASK    0x8\n\n#define    RTL8367C_REG_PORT0_MISC_CFG    0x000e\n#define    RTL8367C_PORT0_MISC_CFG_SMALL_TAG_IPG_OFFSET    15\n#define    RTL8367C_PORT0_MISC_CFG_SMALL_TAG_IPG_MASK    0x8000\n#define    RTL8367C_PORT0_MISC_CFG_TX_ITFSP_MODE_OFFSET    14\n#define    RTL8367C_PORT0_MISC_CFG_TX_ITFSP_MODE_MASK    0x4000\n#define    RTL8367C_PORT0_MISC_CFG_FLOWCTRL_INDEP_OFFSET    13\n#define    RTL8367C_PORT0_MISC_CFG_FLOWCTRL_INDEP_MASK    0x2000\n#define    RTL8367C_PORT0_MISC_CFG_DOT1Q_REMARK_ENABLE_OFFSET    12\n#define    RTL8367C_PORT0_MISC_CFG_DOT1Q_REMARK_ENABLE_MASK    0x1000\n#define    RTL8367C_PORT0_MISC_CFG_INGRESSBW_FLOWCTRL_OFFSET    11\n#define    RTL8367C_PORT0_MISC_CFG_INGRESSBW_FLOWCTRL_MASK    0x800\n#define    RTL8367C_PORT0_MISC_CFG_INGRESSBW_IFG_OFFSET    10\n#define    RTL8367C_PORT0_MISC_CFG_INGRESSBW_IFG_MASK    0x400\n#define    RTL8367C_PORT0_MISC_CFG_RX_SPC_OFFSET    9\n#define    RTL8367C_PORT0_MISC_CFG_RX_SPC_MASK    0x200\n#define    RTL8367C_PORT0_MISC_CFG_CRC_SKIP_OFFSET    8\n#define    RTL8367C_PORT0_MISC_CFG_CRC_SKIP_MASK    0x100\n#define    RTL8367C_PORT0_MISC_CFG_PKTGEN_TX_FIRST_OFFSET    7\n#define    RTL8367C_PORT0_MISC_CFG_PKTGEN_TX_FIRST_MASK    0x80\n#define    RTL8367C_PORT0_MISC_CFG_MAC_LOOPBACK_OFFSET    6\n#define    RTL8367C_PORT0_MISC_CFG_MAC_LOOPBACK_MASK    0x40\n#define    RTL8367C_PORT0_MISC_CFG_VLAN_EGRESS_MODE_OFFSET    4\n#define    RTL8367C_PORT0_MISC_CFG_VLAN_EGRESS_MODE_MASK    0x30\n#define    RTL8367C_PORT0_MISC_CFG_CONGESTION_SUSTAIN_TIME_OFFSET    0\n#define    RTL8367C_PORT0_MISC_CFG_CONGESTION_SUSTAIN_TIME_MASK    0xF\n\n#define    RTL8367C_REG_INGRESSBW_PORT0_RATE_CTRL0    0x000f\n\n#define    RTL8367C_REG_INGRESSBW_PORT0_RATE_CTRL1    0x0010\n#define    RTL8367C_INGRESSBW_PORT0_RATE_CTRL1_DUMMY_OFFSET    3\n#define    RTL8367C_INGRESSBW_PORT0_RATE_CTRL1_DUMMY_MASK    0xFFF8\n#define    RTL8367C_INGRESSBW_PORT0_RATE_CTRL1_INGRESSBW_RATE16_OFFSET    0\n#define    RTL8367C_INGRESSBW_PORT0_RATE_CTRL1_INGRESSBW_RATE16_MASK    0x7\n\n#define    RTL8367C_REG_PORT0_FORCE_RATE0    0x0011\n\n#define    RTL8367C_REG_PORT0_FORCE_RATE1    0x0012\n\n#define    RTL8367C_REG_PORT0_CURENT_RATE0    0x0013\n\n#define    RTL8367C_REG_PORT0_CURENT_RATE1    0x0014\n\n#define    RTL8367C_REG_PORT0_PAGE_COUNTER    0x0015\n#define    RTL8367C_PORT0_PAGE_COUNTER_OFFSET    0\n#define    RTL8367C_PORT0_PAGE_COUNTER_MASK    0x7F\n\n#define    RTL8367C_REG_PAGEMETER_PORT0_CTRL0    0x0016\n\n#define    RTL8367C_REG_PAGEMETER_PORT0_CTRL1    0x0017\n\n#define    RTL8367C_REG_PORT0_EEECFG    0x0018\n#define    RTL8367C_PORT0_EEECFG_EEEP_ENABLE_TX_OFFSET    14\n#define    RTL8367C_PORT0_EEECFG_EEEP_ENABLE_TX_MASK    0x4000\n#define    RTL8367C_PORT0_EEECFG_EEEP_ENABLE_RX_OFFSET    13\n#define    RTL8367C_PORT0_EEECFG_EEEP_ENABLE_RX_MASK    0x2000\n#define    RTL8367C_PORT0_EEECFG_EEE_FORCE_OFFSET    12\n#define    RTL8367C_PORT0_EEECFG_EEE_FORCE_MASK    0x1000\n#define    RTL8367C_PORT0_EEECFG_EEE_100M_OFFSET    11\n#define    RTL8367C_PORT0_EEECFG_EEE_100M_MASK    0x800\n#define    RTL8367C_PORT0_EEECFG_EEE_GIGA_500M_OFFSET    10\n#define    RTL8367C_PORT0_EEECFG_EEE_GIGA_500M_MASK    0x400\n#define    RTL8367C_PORT0_EEECFG_EEE_TX_OFFSET    9\n#define    RTL8367C_PORT0_EEECFG_EEE_TX_MASK    0x200\n#define    RTL8367C_PORT0_EEECFG_EEE_RX_OFFSET    8\n#define    RTL8367C_PORT0_EEECFG_EEE_RX_MASK    0x100\n#define    RTL8367C_PORT0_EEECFG_EEE_DSP_RX_OFFSET    6\n#define    RTL8367C_PORT0_EEECFG_EEE_DSP_RX_MASK    0x40\n#define    RTL8367C_PORT0_EEECFG_EEE_LPI_OFFSET    5\n#define    RTL8367C_PORT0_EEECFG_EEE_LPI_MASK    0x20\n#define    RTL8367C_PORT0_EEECFG_EEE_TX_LPI_OFFSET    4\n#define    RTL8367C_PORT0_EEECFG_EEE_TX_LPI_MASK    0x10\n#define    RTL8367C_PORT0_EEECFG_EEE_RX_LPI_OFFSET    3\n#define    RTL8367C_PORT0_EEECFG_EEE_RX_LPI_MASK    0x8\n#define    RTL8367C_PORT0_EEECFG_EEE_PAUSE_INDICATOR_OFFSET    2\n#define    RTL8367C_PORT0_EEECFG_EEE_PAUSE_INDICATOR_MASK    0x4\n#define    RTL8367C_PORT0_EEECFG_EEE_WAKE_REQ_OFFSET    1\n#define    RTL8367C_PORT0_EEECFG_EEE_WAKE_REQ_MASK    0x2\n#define    RTL8367C_PORT0_EEECFG_EEE_SLEEP_REQ_OFFSET    0\n#define    RTL8367C_PORT0_EEECFG_EEE_SLEEP_REQ_MASK    0x1\n\n#define    RTL8367C_REG_PORT0_EEETXMTR    0x0019\n\n#define    RTL8367C_REG_PORT0_EEERXMTR    0x001a\n\n#define    RTL8367C_REG_PORT0_EEEPTXMTR    0x001b\n\n#define    RTL8367C_REG_PORT0_EEEPRXMTR    0x001c\n\n#define    RTL8367C_REG_PTP_PORT0_CFG1    0x001e\n#define    RTL8367C_PTP_PORT0_CFG1_OFFSET    7\n#define    RTL8367C_PTP_PORT0_CFG1_MASK    0xFF\n\n#define    RTL8367C_REG_P0_MSIC1    0x001f\n#define    RTL8367C_P0_MSIC1_OFFSET    0\n#define    RTL8367C_P0_MSIC1_MASK    0x1\n\n#define    RTL8367C_REG_PORT1_CGST_HALF_CFG    0x0020\n#define    RTL8367C_PORT1_CGST_HALF_CFG_CONGESTION_TIME_OFFSET    4\n#define    RTL8367C_PORT1_CGST_HALF_CFG_CONGESTION_TIME_MASK    0xF0\n#define    RTL8367C_PORT1_CGST_HALF_CFG_CONGESTION_SUSTAIN_TIME_OFFSET    0\n#define    RTL8367C_PORT1_CGST_HALF_CFG_CONGESTION_SUSTAIN_TIME_MASK    0xF\n\n#define    RTL8367C_REG_PKTGEN_PORT1_CTRL    0x0021\n#define    RTL8367C_PKTGEN_PORT1_CTRL_STATUS_OFFSET    15\n#define    RTL8367C_PKTGEN_PORT1_CTRL_STATUS_MASK    0x8000\n#define    RTL8367C_PKTGEN_PORT1_CTRL_PKTGEN_STS_OFFSET    13\n#define    RTL8367C_PKTGEN_PORT1_CTRL_PKTGEN_STS_MASK    0x2000\n#define    RTL8367C_PKTGEN_PORT1_CTRL_CRC_NO_ERROR_OFFSET    4\n#define    RTL8367C_PKTGEN_PORT1_CTRL_CRC_NO_ERROR_MASK    0x10\n#define    RTL8367C_PKTGEN_PORT1_CTRL_CMD_START_OFFSET    0\n#define    RTL8367C_PKTGEN_PORT1_CTRL_CMD_START_MASK    0x1\n\n#define    RTL8367C_REG_TX_ERR_CNT_PORT1    0x0022\n#define    RTL8367C_TX_ERR_CNT_PORT1_OFFSET    0\n#define    RTL8367C_TX_ERR_CNT_PORT1_MASK    0x7\n\n#define    RTL8367C_REG_PKTGEN_PORT1_DA0    0x0023\n\n#define    RTL8367C_REG_PKTGEN_PORT1_DA1    0x0024\n\n#define    RTL8367C_REG_PKTGEN_PORT1_DA2    0x0025\n\n#define    RTL8367C_REG_PKTGEN_PORT1_SA0    0x0026\n\n#define    RTL8367C_REG_PKTGEN_PORT1_SA1    0x0027\n\n#define    RTL8367C_REG_PKTGEN_PORT1_SA2    0x0028\n\n#define    RTL8367C_REG_PKTGEN_PORT1_COUNTER0    0x0029\n\n#define    RTL8367C_REG_PKTGEN_PORT1_COUNTER1    0x002a\n#define    RTL8367C_PKTGEN_PORT1_COUNTER1_OFFSET    0\n#define    RTL8367C_PKTGEN_PORT1_COUNTER1_MASK    0xFF\n\n#define    RTL8367C_REG_PKTGEN_PORT1_TX_LENGTH    0x002b\n#define    RTL8367C_PKTGEN_PORT1_TX_LENGTH_OFFSET    0\n#define    RTL8367C_PKTGEN_PORT1_TX_LENGTH_MASK    0x3FFF\n\n#define    RTL8367C_REG_PKTGEN_PORT1_TIMER    0x002d\n#define    RTL8367C_PKTGEN_PORT1_TIMER_TIMER_OFFSET    4\n#define    RTL8367C_PKTGEN_PORT1_TIMER_TIMER_MASK    0xF0\n#define    RTL8367C_PKTGEN_PORT1_TIMER_RX_DMA_ERR_FLAG_OFFSET    3\n#define    RTL8367C_PKTGEN_PORT1_TIMER_RX_DMA_ERR_FLAG_MASK    0x8\n\n#define    RTL8367C_REG_PORT1_MISC_CFG    0x002e\n#define    RTL8367C_PORT1_MISC_CFG_SMALL_TAG_IPG_OFFSET    15\n#define    RTL8367C_PORT1_MISC_CFG_SMALL_TAG_IPG_MASK    0x8000\n#define    RTL8367C_PORT1_MISC_CFG_TX_ITFSP_MODE_OFFSET    14\n#define    RTL8367C_PORT1_MISC_CFG_TX_ITFSP_MODE_MASK    0x4000\n#define    RTL8367C_PORT1_MISC_CFG_FLOWCTRL_INDEP_OFFSET    13\n#define    RTL8367C_PORT1_MISC_CFG_FLOWCTRL_INDEP_MASK    0x2000\n#define    RTL8367C_PORT1_MISC_CFG_DOT1Q_REMARK_ENABLE_OFFSET    12\n#define    RTL8367C_PORT1_MISC_CFG_DOT1Q_REMARK_ENABLE_MASK    0x1000\n#define    RTL8367C_PORT1_MISC_CFG_INGRESSBW_FLOWCTRL_OFFSET    11\n#define    RTL8367C_PORT1_MISC_CFG_INGRESSBW_FLOWCTRL_MASK    0x800\n#define    RTL8367C_PORT1_MISC_CFG_INGRESSBW_IFG_OFFSET    10\n#define    RTL8367C_PORT1_MISC_CFG_INGRESSBW_IFG_MASK    0x400\n#define    RTL8367C_PORT1_MISC_CFG_RX_SPC_OFFSET    9\n#define    RTL8367C_PORT1_MISC_CFG_RX_SPC_MASK    0x200\n#define    RTL8367C_PORT1_MISC_CFG_CRC_SKIP_OFFSET    8\n#define    RTL8367C_PORT1_MISC_CFG_CRC_SKIP_MASK    0x100\n#define    RTL8367C_PORT1_MISC_CFG_PKTGEN_TX_FIRST_OFFSET    7\n#define    RTL8367C_PORT1_MISC_CFG_PKTGEN_TX_FIRST_MASK    0x80\n#define    RTL8367C_PORT1_MISC_CFG_MAC_LOOPBACK_OFFSET    6\n#define    RTL8367C_PORT1_MISC_CFG_MAC_LOOPBACK_MASK    0x40\n#define    RTL8367C_PORT1_MISC_CFG_VLAN_EGRESS_MODE_OFFSET    4\n#define    RTL8367C_PORT1_MISC_CFG_VLAN_EGRESS_MODE_MASK    0x30\n#define    RTL8367C_PORT1_MISC_CFG_CONGESTION_SUSTAIN_TIME_OFFSET    0\n#define    RTL8367C_PORT1_MISC_CFG_CONGESTION_SUSTAIN_TIME_MASK    0xF\n\n#define    RTL8367C_REG_INGRESSBW_PORT1_RATE_CTRL0    0x002f\n\n#define    RTL8367C_REG_INGRESSBW_PORT1_RATE_CTRL1    0x0030\n#define    RTL8367C_INGRESSBW_PORT1_RATE_CTRL1_DUMMY_OFFSET    3\n#define    RTL8367C_INGRESSBW_PORT1_RATE_CTRL1_DUMMY_MASK    0xFFF8\n#define    RTL8367C_INGRESSBW_PORT1_RATE_CTRL1_INGRESSBW_RATE16_OFFSET    0\n#define    RTL8367C_INGRESSBW_PORT1_RATE_CTRL1_INGRESSBW_RATE16_MASK    0x7\n\n#define    RTL8367C_REG_PORT1_FORCE_RATE0    0x0031\n\n#define    RTL8367C_REG_PORT1_FORCE_RATE1    0x0032\n\n#define    RTL8367C_REG_PORT1_CURENT_RATE0    0x0033\n\n#define    RTL8367C_REG_PORT1_CURENT_RATE1    0x0034\n\n#define    RTL8367C_REG_PORT1_PAGE_COUNTER    0x0035\n#define    RTL8367C_PORT1_PAGE_COUNTER_OFFSET    0\n#define    RTL8367C_PORT1_PAGE_COUNTER_MASK    0x7F\n\n#define    RTL8367C_REG_PAGEMETER_PORT1_CTRL0    0x0036\n\n#define    RTL8367C_REG_PAGEMETER_PORT1_CTRL1    0x0037\n\n#define    RTL8367C_REG_PORT1_EEECFG    0x0038\n#define    RTL8367C_PORT1_EEECFG_EEEP_ENABLE_TX_OFFSET    14\n#define    RTL8367C_PORT1_EEECFG_EEEP_ENABLE_TX_MASK    0x4000\n#define    RTL8367C_PORT1_EEECFG_EEEP_ENABLE_RX_OFFSET    13\n#define    RTL8367C_PORT1_EEECFG_EEEP_ENABLE_RX_MASK    0x2000\n#define    RTL8367C_PORT1_EEECFG_EEE_FORCE_OFFSET    12\n#define    RTL8367C_PORT1_EEECFG_EEE_FORCE_MASK    0x1000\n#define    RTL8367C_PORT1_EEECFG_EEE_100M_OFFSET    11\n#define    RTL8367C_PORT1_EEECFG_EEE_100M_MASK    0x800\n#define    RTL8367C_PORT1_EEECFG_EEE_GIGA_500M_OFFSET    10\n#define    RTL8367C_PORT1_EEECFG_EEE_GIGA_500M_MASK    0x400\n#define    RTL8367C_PORT1_EEECFG_EEE_TX_OFFSET    9\n#define    RTL8367C_PORT1_EEECFG_EEE_TX_MASK    0x200\n#define    RTL8367C_PORT1_EEECFG_EEE_RX_OFFSET    8\n#define    RTL8367C_PORT1_EEECFG_EEE_RX_MASK    0x100\n#define    RTL8367C_PORT1_EEECFG_EEE_DSP_RX_OFFSET    6\n#define    RTL8367C_PORT1_EEECFG_EEE_DSP_RX_MASK    0x40\n#define    RTL8367C_PORT1_EEECFG_EEE_LPI_OFFSET    5\n#define    RTL8367C_PORT1_EEECFG_EEE_LPI_MASK    0x20\n#define    RTL8367C_PORT1_EEECFG_EEE_TX_LPI_OFFSET    4\n#define    RTL8367C_PORT1_EEECFG_EEE_TX_LPI_MASK    0x10\n#define    RTL8367C_PORT1_EEECFG_EEE_RX_LPI_OFFSET    3\n#define    RTL8367C_PORT1_EEECFG_EEE_RX_LPI_MASK    0x8\n#define    RTL8367C_PORT1_EEECFG_EEE_PAUSE_INDICATOR_OFFSET    2\n#define    RTL8367C_PORT1_EEECFG_EEE_PAUSE_INDICATOR_MASK    0x4\n#define    RTL8367C_PORT1_EEECFG_EEE_WAKE_REQ_OFFSET    1\n#define    RTL8367C_PORT1_EEECFG_EEE_WAKE_REQ_MASK    0x2\n#define    RTL8367C_PORT1_EEECFG_EEE_SLEEP_REQ_OFFSET    0\n#define    RTL8367C_PORT1_EEECFG_EEE_SLEEP_REQ_MASK    0x1\n\n#define    RTL8367C_REG_PORT1_EEETXMTR    0x0039\n\n#define    RTL8367C_REG_PORT1_EEERXMTR    0x003a\n\n#define    RTL8367C_REG_PORT1_EEEPTXMTR    0x003b\n\n#define    RTL8367C_REG_PORT1_EEEPRXMTR    0x003c\n\n#define    RTL8367C_REG_PTP_PORT1_CFG1    0x003e\n#define    RTL8367C_PTP_PORT1_CFG1_OFFSET    7\n#define    RTL8367C_PTP_PORT1_CFG1_MASK    0xFF\n\n#define    RTL8367C_REG_P1_MSIC1    0x003f\n#define    RTL8367C_P1_MSIC1_OFFSET    0\n#define    RTL8367C_P1_MSIC1_MASK    0x1\n\n#define    RTL8367C_REG_PORT2_CGST_HALF_CFG    0x0040\n#define    RTL8367C_PORT2_CGST_HALF_CFG_CONGESTION_TIME_OFFSET    4\n#define    RTL8367C_PORT2_CGST_HALF_CFG_CONGESTION_TIME_MASK    0xF0\n#define    RTL8367C_PORT2_CGST_HALF_CFG_CONGESTION_SUSTAIN_TIME_OFFSET    0\n#define    RTL8367C_PORT2_CGST_HALF_CFG_CONGESTION_SUSTAIN_TIME_MASK    0xF\n\n#define    RTL8367C_REG_PKTGEN_PORT2_CTRL    0x0041\n#define    RTL8367C_PKTGEN_PORT2_CTRL_STATUS_OFFSET    15\n#define    RTL8367C_PKTGEN_PORT2_CTRL_STATUS_MASK    0x8000\n#define    RTL8367C_PKTGEN_PORT2_CTRL_PKTGEN_STS_OFFSET    13\n#define    RTL8367C_PKTGEN_PORT2_CTRL_PKTGEN_STS_MASK    0x2000\n#define    RTL8367C_PKTGEN_PORT2_CTRL_CRC_NO_ERROR_OFFSET    4\n#define    RTL8367C_PKTGEN_PORT2_CTRL_CRC_NO_ERROR_MASK    0x10\n#define    RTL8367C_PKTGEN_PORT2_CTRL_CMD_START_OFFSET    0\n#define    RTL8367C_PKTGEN_PORT2_CTRL_CMD_START_MASK    0x1\n\n#define    RTL8367C_REG_TX_ERR_CNT_PORT2    0x0042\n#define    RTL8367C_TX_ERR_CNT_PORT2_OFFSET    0\n#define    RTL8367C_TX_ERR_CNT_PORT2_MASK    0x7\n\n#define    RTL8367C_REG_PKTGEN_PORT2_DA0    0x0043\n\n#define    RTL8367C_REG_PKTGEN_PORT2_DA1    0x0044\n\n#define    RTL8367C_REG_PKTGEN_PORT2_DA2    0x0045\n\n#define    RTL8367C_REG_PKTGEN_PORT2_SA0    0x0046\n\n#define    RTL8367C_REG_PKTGEN_PORT2_SA1    0x0047\n\n#define    RTL8367C_REG_PKTGEN_PORT2_SA2    0x0048\n\n#define    RTL8367C_REG_PKTGEN_PORT2_COUNTER0    0x0049\n\n#define    RTL8367C_REG_PKTGEN_PORT2_COUNTER1    0x004a\n#define    RTL8367C_PKTGEN_PORT2_COUNTER1_OFFSET    0\n#define    RTL8367C_PKTGEN_PORT2_COUNTER1_MASK    0xFF\n\n#define    RTL8367C_REG_PKTGEN_PORT2_TX_LENGTH    0x004b\n#define    RTL8367C_PKTGEN_PORT2_TX_LENGTH_OFFSET    0\n#define    RTL8367C_PKTGEN_PORT2_TX_LENGTH_MASK    0x3FFF\n\n#define    RTL8367C_REG_PKTGEN_PORT2_TIMER    0x004d\n#define    RTL8367C_PKTGEN_PORT2_TIMER_TIMER_OFFSET    4\n#define    RTL8367C_PKTGEN_PORT2_TIMER_TIMER_MASK    0xF0\n#define    RTL8367C_PKTGEN_PORT2_TIMER_RX_DMA_ERR_FLAG_OFFSET    3\n#define    RTL8367C_PKTGEN_PORT2_TIMER_RX_DMA_ERR_FLAG_MASK    0x8\n\n#define    RTL8367C_REG_PORT2_MISC_CFG    0x004e\n#define    RTL8367C_PORT2_MISC_CFG_SMALL_TAG_IPG_OFFSET    15\n#define    RTL8367C_PORT2_MISC_CFG_SMALL_TAG_IPG_MASK    0x8000\n#define    RTL8367C_PORT2_MISC_CFG_TX_ITFSP_MODE_OFFSET    14\n#define    RTL8367C_PORT2_MISC_CFG_TX_ITFSP_MODE_MASK    0x4000\n#define    RTL8367C_PORT2_MISC_CFG_FLOWCTRL_INDEP_OFFSET    13\n#define    RTL8367C_PORT2_MISC_CFG_FLOWCTRL_INDEP_MASK    0x2000\n#define    RTL8367C_PORT2_MISC_CFG_DOT1Q_REMARK_ENABLE_OFFSET    12\n#define    RTL8367C_PORT2_MISC_CFG_DOT1Q_REMARK_ENABLE_MASK    0x1000\n#define    RTL8367C_PORT2_MISC_CFG_INGRESSBW_FLOWCTRL_OFFSET    11\n#define    RTL8367C_PORT2_MISC_CFG_INGRESSBW_FLOWCTRL_MASK    0x800\n#define    RTL8367C_PORT2_MISC_CFG_INGRESSBW_IFG_OFFSET    10\n#define    RTL8367C_PORT2_MISC_CFG_INGRESSBW_IFG_MASK    0x400\n#define    RTL8367C_PORT2_MISC_CFG_RX_SPC_OFFSET    9\n#define    RTL8367C_PORT2_MISC_CFG_RX_SPC_MASK    0x200\n#define    RTL8367C_PORT2_MISC_CFG_CRC_SKIP_OFFSET    8\n#define    RTL8367C_PORT2_MISC_CFG_CRC_SKIP_MASK    0x100\n#define    RTL8367C_PORT2_MISC_CFG_PKTGEN_TX_FIRST_OFFSET    7\n#define    RTL8367C_PORT2_MISC_CFG_PKTGEN_TX_FIRST_MASK    0x80\n#define    RTL8367C_PORT2_MISC_CFG_MAC_LOOPBACK_OFFSET    6\n#define    RTL8367C_PORT2_MISC_CFG_MAC_LOOPBACK_MASK    0x40\n#define    RTL8367C_PORT2_MISC_CFG_VLAN_EGRESS_MODE_OFFSET    4\n#define    RTL8367C_PORT2_MISC_CFG_VLAN_EGRESS_MODE_MASK    0x30\n#define    RTL8367C_PORT2_MISC_CFG_CONGESTION_SUSTAIN_TIME_OFFSET    0\n#define    RTL8367C_PORT2_MISC_CFG_CONGESTION_SUSTAIN_TIME_MASK    0xF\n\n#define    RTL8367C_REG_INGRESSBW_PORT2_RATE_CTRL0    0x004f\n\n#define    RTL8367C_REG_INGRESSBW_PORT2_RATE_CTRL1    0x0050\n#define    RTL8367C_INGRESSBW_PORT2_RATE_CTRL1_DUMMY_OFFSET    3\n#define    RTL8367C_INGRESSBW_PORT2_RATE_CTRL1_DUMMY_MASK    0xFFF8\n#define    RTL8367C_INGRESSBW_PORT2_RATE_CTRL1_INGRESSBW_RATE16_OFFSET    0\n#define    RTL8367C_INGRESSBW_PORT2_RATE_CTRL1_INGRESSBW_RATE16_MASK    0x7\n\n#define    RTL8367C_REG_PORT2_FORCE_RATE0    0x0051\n\n#define    RTL8367C_REG_PORT2_FORCE_RATE1    0x0052\n\n#define    RTL8367C_REG_PORT2_CURENT_RATE0    0x0053\n\n#define    RTL8367C_REG_PORT2_CURENT_RATE1    0x0054\n\n#define    RTL8367C_REG_PORT2_PAGE_COUNTER    0x0055\n#define    RTL8367C_PORT2_PAGE_COUNTER_OFFSET    0\n#define    RTL8367C_PORT2_PAGE_COUNTER_MASK    0x7F\n\n#define    RTL8367C_REG_PAGEMETER_PORT2_CTRL0    0x0056\n\n#define    RTL8367C_REG_PAGEMETER_PORT2_CTRL1    0x0057\n\n#define    RTL8367C_REG_PORT2_EEECFG    0x0058\n#define    RTL8367C_PORT2_EEECFG_EEEP_ENABLE_TX_OFFSET    14\n#define    RTL8367C_PORT2_EEECFG_EEEP_ENABLE_TX_MASK    0x4000\n#define    RTL8367C_PORT2_EEECFG_EEEP_ENABLE_RX_OFFSET    13\n#define    RTL8367C_PORT2_EEECFG_EEEP_ENABLE_RX_MASK    0x2000\n#define    RTL8367C_PORT2_EEECFG_EEE_FORCE_OFFSET    12\n#define    RTL8367C_PORT2_EEECFG_EEE_FORCE_MASK    0x1000\n#define    RTL8367C_PORT2_EEECFG_EEE_100M_OFFSET    11\n#define    RTL8367C_PORT2_EEECFG_EEE_100M_MASK    0x800\n#define    RTL8367C_PORT2_EEECFG_EEE_GIGA_500M_OFFSET    10\n#define    RTL8367C_PORT2_EEECFG_EEE_GIGA_500M_MASK    0x400\n#define    RTL8367C_PORT2_EEECFG_EEE_TX_OFFSET    9\n#define    RTL8367C_PORT2_EEECFG_EEE_TX_MASK    0x200\n#define    RTL8367C_PORT2_EEECFG_EEE_RX_OFFSET    8\n#define    RTL8367C_PORT2_EEECFG_EEE_RX_MASK    0x100\n#define    RTL8367C_PORT2_EEECFG_EEE_DSP_RX_OFFSET    6\n#define    RTL8367C_PORT2_EEECFG_EEE_DSP_RX_MASK    0x40\n#define    RTL8367C_PORT2_EEECFG_EEE_LPI_OFFSET    5\n#define    RTL8367C_PORT2_EEECFG_EEE_LPI_MASK    0x20\n#define    RTL8367C_PORT2_EEECFG_EEE_TX_LPI_OFFSET    4\n#define    RTL8367C_PORT2_EEECFG_EEE_TX_LPI_MASK    0x10\n#define    RTL8367C_PORT2_EEECFG_EEE_RX_LPI_OFFSET    3\n#define    RTL8367C_PORT2_EEECFG_EEE_RX_LPI_MASK    0x8\n#define    RTL8367C_PORT2_EEECFG_EEE_PAUSE_INDICATOR_OFFSET    2\n#define    RTL8367C_PORT2_EEECFG_EEE_PAUSE_INDICATOR_MASK    0x4\n#define    RTL8367C_PORT2_EEECFG_EEE_WAKE_REQ_OFFSET    1\n#define    RTL8367C_PORT2_EEECFG_EEE_WAKE_REQ_MASK    0x2\n#define    RTL8367C_PORT2_EEECFG_EEE_SLEEP_REQ_OFFSET    0\n#define    RTL8367C_PORT2_EEECFG_EEE_SLEEP_REQ_MASK    0x1\n\n#define    RTL8367C_REG_PORT2_EEETXMTR    0x0059\n\n#define    RTL8367C_REG_PORT2_EEERXMTR    0x005a\n\n#define    RTL8367C_REG_PORT2_EEEPTXMTR    0x005b\n\n#define    RTL8367C_REG_PORT2_EEEPRXMTR    0x005c\n\n#define    RTL8367C_REG_PTP_PORT2_CFG1    0x005e\n#define    RTL8367C_PTP_PORT2_CFG1_OFFSET    7\n#define    RTL8367C_PTP_PORT2_CFG1_MASK    0xFF\n\n#define    RTL8367C_REG_P2_MSIC1    0x005f\n#define    RTL8367C_P2_MSIC1_OFFSET    0\n#define    RTL8367C_P2_MSIC1_MASK    0x1\n\n#define    RTL8367C_REG_PORT3_CGST_HALF_CFG    0x0060\n#define    RTL8367C_PORT3_CGST_HALF_CFG_CONGESTION_TIME_OFFSET    4\n#define    RTL8367C_PORT3_CGST_HALF_CFG_CONGESTION_TIME_MASK    0xF0\n#define    RTL8367C_PORT3_CGST_HALF_CFG_CONGESTION_SUSTAIN_TIME_OFFSET    0\n#define    RTL8367C_PORT3_CGST_HALF_CFG_CONGESTION_SUSTAIN_TIME_MASK    0xF\n\n#define    RTL8367C_REG_PKTGEN_PORT3_CTRL    0x0061\n#define    RTL8367C_PKTGEN_PORT3_CTRL_STATUS_OFFSET    15\n#define    RTL8367C_PKTGEN_PORT3_CTRL_STATUS_MASK    0x8000\n#define    RTL8367C_PKTGEN_PORT3_CTRL_PKTGEN_STS_OFFSET    13\n#define    RTL8367C_PKTGEN_PORT3_CTRL_PKTGEN_STS_MASK    0x2000\n#define    RTL8367C_PKTGEN_PORT3_CTRL_CRC_NO_ERROR_OFFSET    4\n#define    RTL8367C_PKTGEN_PORT3_CTRL_CRC_NO_ERROR_MASK    0x10\n#define    RTL8367C_PKTGEN_PORT3_CTRL_CMD_START_OFFSET    0\n#define    RTL8367C_PKTGEN_PORT3_CTRL_CMD_START_MASK    0x1\n\n#define    RTL8367C_REG_TX_ERR_CNT_PORT3    0x0062\n#define    RTL8367C_TX_ERR_CNT_PORT3_OFFSET    0\n#define    RTL8367C_TX_ERR_CNT_PORT3_MASK    0x7\n\n#define    RTL8367C_REG_PKTGEN_PORT3_DA0    0x0063\n\n#define    RTL8367C_REG_PKTGEN_PORT3_DA1    0x0064\n\n#define    RTL8367C_REG_PKTGEN_PORT3_DA2    0x0065\n\n#define    RTL8367C_REG_PKTGEN_PORT3_SA0    0x0066\n\n#define    RTL8367C_REG_PKTGEN_PORT3_SA1    0x0067\n\n#define    RTL8367C_REG_PKTGEN_PORT3_SA2    0x0068\n\n#define    RTL8367C_REG_PKTGEN_PORT3_COUNTER0    0x0069\n\n#define    RTL8367C_REG_PKTGEN_PORT3_COUNTER1    0x006a\n#define    RTL8367C_PKTGEN_PORT3_COUNTER1_OFFSET    0\n#define    RTL8367C_PKTGEN_PORT3_COUNTER1_MASK    0xFF\n\n#define    RTL8367C_REG_PKTGEN_PORT3_TX_LENGTH    0x006b\n#define    RTL8367C_PKTGEN_PORT3_TX_LENGTH_OFFSET    0\n#define    RTL8367C_PKTGEN_PORT3_TX_LENGTH_MASK    0x3FFF\n\n#define    RTL8367C_REG_PKTGEN_PORT3_TIMER    0x006d\n#define    RTL8367C_PKTGEN_PORT3_TIMER_TIMER_OFFSET    4\n#define    RTL8367C_PKTGEN_PORT3_TIMER_TIMER_MASK    0xF0\n#define    RTL8367C_PKTGEN_PORT3_TIMER_RX_DMA_ERR_FLAG_OFFSET    3\n#define    RTL8367C_PKTGEN_PORT3_TIMER_RX_DMA_ERR_FLAG_MASK    0x8\n\n#define    RTL8367C_REG_PORT3_MISC_CFG    0x006e\n#define    RTL8367C_PORT3_MISC_CFG_SMALL_TAG_IPG_OFFSET    15\n#define    RTL8367C_PORT3_MISC_CFG_SMALL_TAG_IPG_MASK    0x8000\n#define    RTL8367C_PORT3_MISC_CFG_TX_ITFSP_MODE_OFFSET    14\n#define    RTL8367C_PORT3_MISC_CFG_TX_ITFSP_MODE_MASK    0x4000\n#define    RTL8367C_PORT3_MISC_CFG_FLOWCTRL_INDEP_OFFSET    13\n#define    RTL8367C_PORT3_MISC_CFG_FLOWCTRL_INDEP_MASK    0x2000\n#define    RTL8367C_PORT3_MISC_CFG_DOT1Q_REMARK_ENABLE_OFFSET    12\n#define    RTL8367C_PORT3_MISC_CFG_DOT1Q_REMARK_ENABLE_MASK    0x1000\n#define    RTL8367C_PORT3_MISC_CFG_INGRESSBW_FLOWCTRL_OFFSET    11\n#define    RTL8367C_PORT3_MISC_CFG_INGRESSBW_FLOWCTRL_MASK    0x800\n#define    RTL8367C_PORT3_MISC_CFG_INGRESSBW_IFG_OFFSET    10\n#define    RTL8367C_PORT3_MISC_CFG_INGRESSBW_IFG_MASK    0x400\n#define    RTL8367C_PORT3_MISC_CFG_RX_SPC_OFFSET    9\n#define    RTL8367C_PORT3_MISC_CFG_RX_SPC_MASK    0x200\n#define    RTL8367C_PORT3_MISC_CFG_CRC_SKIP_OFFSET    8\n#define    RTL8367C_PORT3_MISC_CFG_CRC_SKIP_MASK    0x100\n#define    RTL8367C_PORT3_MISC_CFG_PKTGEN_TX_FIRST_OFFSET    7\n#define    RTL8367C_PORT3_MISC_CFG_PKTGEN_TX_FIRST_MASK    0x80\n#define    RTL8367C_PORT3_MISC_CFG_MAC_LOOPBACK_OFFSET    6\n#define    RTL8367C_PORT3_MISC_CFG_MAC_LOOPBACK_MASK    0x40\n#define    RTL8367C_PORT3_MISC_CFG_VLAN_EGRESS_MODE_OFFSET    4\n#define    RTL8367C_PORT3_MISC_CFG_VLAN_EGRESS_MODE_MASK    0x30\n#define    RTL8367C_PORT3_MISC_CFG_CONGESTION_SUSTAIN_TIME_OFFSET    0\n#define    RTL8367C_PORT3_MISC_CFG_CONGESTION_SUSTAIN_TIME_MASK    0xF\n\n#define    RTL8367C_REG_INGRESSBW_PORT3_RATE_CTRL0    0x006f\n\n#define    RTL8367C_REG_INGRESSBW_PORT3_RATE_CTRL1    0x0070\n#define    RTL8367C_INGRESSBW_PORT3_RATE_CTRL1_DUMMY_OFFSET    3\n#define    RTL8367C_INGRESSBW_PORT3_RATE_CTRL1_DUMMY_MASK    0xFFF8\n#define    RTL8367C_INGRESSBW_PORT3_RATE_CTRL1_INGRESSBW_RATE16_OFFSET    0\n#define    RTL8367C_INGRESSBW_PORT3_RATE_CTRL1_INGRESSBW_RATE16_MASK    0x7\n\n#define    RTL8367C_REG_PORT3_FORCE_RATE0    0x0071\n\n#define    RTL8367C_REG_PORT3_FORCE_RATE1    0x0072\n\n#define    RTL8367C_REG_PORT3_CURENT_RATE0    0x0073\n\n#define    RTL8367C_REG_PORT3_CURENT_RATE1    0x0074\n\n#define    RTL8367C_REG_PORT3_PAGE_COUNTER    0x0075\n#define    RTL8367C_PORT3_PAGE_COUNTER_OFFSET    0\n#define    RTL8367C_PORT3_PAGE_COUNTER_MASK    0x7F\n\n#define    RTL8367C_REG_PAGEMETER_PORT3_CTRL0    0x0076\n\n#define    RTL8367C_REG_PAGEMETER_PORT3_CTRL1    0x0077\n\n#define    RTL8367C_REG_PORT3_EEECFG    0x0078\n#define    RTL8367C_PORT3_EEECFG_EEEP_ENABLE_TX_OFFSET    14\n#define    RTL8367C_PORT3_EEECFG_EEEP_ENABLE_TX_MASK    0x4000\n#define    RTL8367C_PORT3_EEECFG_EEEP_ENABLE_RX_OFFSET    13\n#define    RTL8367C_PORT3_EEECFG_EEEP_ENABLE_RX_MASK    0x2000\n#define    RTL8367C_PORT3_EEECFG_EEE_FORCE_OFFSET    12\n#define    RTL8367C_PORT3_EEECFG_EEE_FORCE_MASK    0x1000\n#define    RTL8367C_PORT3_EEECFG_EEE_100M_OFFSET    11\n#define    RTL8367C_PORT3_EEECFG_EEE_100M_MASK    0x800\n#define    RTL8367C_PORT3_EEECFG_EEE_GIGA_500M_OFFSET    10\n#define    RTL8367C_PORT3_EEECFG_EEE_GIGA_500M_MASK    0x400\n#define    RTL8367C_PORT3_EEECFG_EEE_TX_OFFSET    9\n#define    RTL8367C_PORT3_EEECFG_EEE_TX_MASK    0x200\n#define    RTL8367C_PORT3_EEECFG_EEE_RX_OFFSET    8\n#define    RTL8367C_PORT3_EEECFG_EEE_RX_MASK    0x100\n#define    RTL8367C_PORT3_EEECFG_EEE_DSP_RX_OFFSET    6\n#define    RTL8367C_PORT3_EEECFG_EEE_DSP_RX_MASK    0x40\n#define    RTL8367C_PORT3_EEECFG_EEE_LPI_OFFSET    5\n#define    RTL8367C_PORT3_EEECFG_EEE_LPI_MASK    0x20\n#define    RTL8367C_PORT3_EEECFG_EEE_TX_LPI_OFFSET    4\n#define    RTL8367C_PORT3_EEECFG_EEE_TX_LPI_MASK    0x10\n#define    RTL8367C_PORT3_EEECFG_EEE_RX_LPI_OFFSET    3\n#define    RTL8367C_PORT3_EEECFG_EEE_RX_LPI_MASK    0x8\n#define    RTL8367C_PORT3_EEECFG_EEE_PAUSE_INDICATOR_OFFSET    2\n#define    RTL8367C_PORT3_EEECFG_EEE_PAUSE_INDICATOR_MASK    0x4\n#define    RTL8367C_PORT3_EEECFG_EEE_WAKE_REQ_OFFSET    1\n#define    RTL8367C_PORT3_EEECFG_EEE_WAKE_REQ_MASK    0x2\n#define    RTL8367C_PORT3_EEECFG_EEE_SLEEP_REQ_OFFSET    0\n#define    RTL8367C_PORT3_EEECFG_EEE_SLEEP_REQ_MASK    0x1\n\n#define    RTL8367C_REG_PORT3_EEETXMTR    0x0079\n\n#define    RTL8367C_REG_PORT3_EEERXMTR    0x007a\n\n#define    RTL8367C_REG_PORT3_EEEPTXMTR    0x007b\n\n#define    RTL8367C_REG_PORT3_EEEPRXMTR    0x007c\n\n#define    RTL8367C_REG_PTP_PORT3_CFG1    0x007e\n#define    RTL8367C_PTP_PORT3_CFG1_OFFSET    7\n#define    RTL8367C_PTP_PORT3_CFG1_MASK    0xFF\n\n#define    RTL8367C_REG_P3_MSIC1    0x007f\n#define    RTL8367C_P3_MSIC1_OFFSET    0\n#define    RTL8367C_P3_MSIC1_MASK    0x1\n\n#define    RTL8367C_REG_PORT4_CGST_HALF_CFG    0x0080\n#define    RTL8367C_PORT4_CGST_HALF_CFG_CONGESTION_TIME_OFFSET    4\n#define    RTL8367C_PORT4_CGST_HALF_CFG_CONGESTION_TIME_MASK    0xF0\n#define    RTL8367C_PORT4_CGST_HALF_CFG_CONGESTION_SUSTAIN_TIME_OFFSET    0\n#define    RTL8367C_PORT4_CGST_HALF_CFG_CONGESTION_SUSTAIN_TIME_MASK    0xF\n\n#define    RTL8367C_REG_PKTGEN_PORT4_CTRL    0x0081\n#define    RTL8367C_PKTGEN_PORT4_CTRL_STATUS_OFFSET    15\n#define    RTL8367C_PKTGEN_PORT4_CTRL_STATUS_MASK    0x8000\n#define    RTL8367C_PKTGEN_PORT4_CTRL_PKTGEN_STS_OFFSET    13\n#define    RTL8367C_PKTGEN_PORT4_CTRL_PKTGEN_STS_MASK    0x2000\n#define    RTL8367C_PKTGEN_PORT4_CTRL_CRC_NO_ERROR_OFFSET    4\n#define    RTL8367C_PKTGEN_PORT4_CTRL_CRC_NO_ERROR_MASK    0x10\n#define    RTL8367C_PKTGEN_PORT4_CTRL_CMD_START_OFFSET    0\n#define    RTL8367C_PKTGEN_PORT4_CTRL_CMD_START_MASK    0x1\n\n#define    RTL8367C_REG_TX_ERR_CNT_PORT4    0x0082\n#define    RTL8367C_TX_ERR_CNT_PORT4_OFFSET    0\n#define    RTL8367C_TX_ERR_CNT_PORT4_MASK    0x7\n\n#define    RTL8367C_REG_PKTGEN_PORT4_DA0    0x0083\n\n#define    RTL8367C_REG_PKTGEN_PORT4_DA1    0x0084\n\n#define    RTL8367C_REG_PKTGEN_PORT4_DA2    0x0085\n\n#define    RTL8367C_REG_PKTGEN_PORT4_SA0    0x0086\n\n#define    RTL8367C_REG_PKTGEN_PORT4_SA1    0x0087\n\n#define    RTL8367C_REG_PKTGEN_PORT4_SA2    0x0088\n\n#define    RTL8367C_REG_PKTGEN_PORT4_COUNTER0    0x0089\n\n#define    RTL8367C_REG_PKTGEN_PORT4_COUNTER1    0x008a\n#define    RTL8367C_PKTGEN_PORT4_COUNTER1_OFFSET    0\n#define    RTL8367C_PKTGEN_PORT4_COUNTER1_MASK    0xFF\n\n#define    RTL8367C_REG_PKTGEN_PORT4_TX_LENGTH    0x008b\n#define    RTL8367C_PKTGEN_PORT4_TX_LENGTH_OFFSET    0\n#define    RTL8367C_PKTGEN_PORT4_TX_LENGTH_MASK    0x3FFF\n\n#define    RTL8367C_REG_PKTGEN_PORT4_TIMER    0x008d\n#define    RTL8367C_PKTGEN_PORT4_TIMER_TIMER_OFFSET    4\n#define    RTL8367C_PKTGEN_PORT4_TIMER_TIMER_MASK    0xF0\n#define    RTL8367C_PKTGEN_PORT4_TIMER_RX_DMA_ERR_FLAG_OFFSET    3\n#define    RTL8367C_PKTGEN_PORT4_TIMER_RX_DMA_ERR_FLAG_MASK    0x8\n\n#define    RTL8367C_REG_PORT4_MISC_CFG    0x008e\n#define    RTL8367C_PORT4_MISC_CFG_SMALL_TAG_IPG_OFFSET    15\n#define    RTL8367C_PORT4_MISC_CFG_SMALL_TAG_IPG_MASK    0x8000\n#define    RTL8367C_PORT4_MISC_CFG_TX_ITFSP_MODE_OFFSET    14\n#define    RTL8367C_PORT4_MISC_CFG_TX_ITFSP_MODE_MASK    0x4000\n#define    RTL8367C_PORT4_MISC_CFG_FLOWCTRL_INDEP_OFFSET    13\n#define    RTL8367C_PORT4_MISC_CFG_FLOWCTRL_INDEP_MASK    0x2000\n#define    RTL8367C_PORT4_MISC_CFG_DOT1Q_REMARK_ENABLE_OFFSET    12\n#define    RTL8367C_PORT4_MISC_CFG_DOT1Q_REMARK_ENABLE_MASK    0x1000\n#define    RTL8367C_PORT4_MISC_CFG_INGRESSBW_FLOWCTRL_OFFSET    11\n#define    RTL8367C_PORT4_MISC_CFG_INGRESSBW_FLOWCTRL_MASK    0x800\n#define    RTL8367C_PORT4_MISC_CFG_INGRESSBW_IFG_OFFSET    10\n#define    RTL8367C_PORT4_MISC_CFG_INGRESSBW_IFG_MASK    0x400\n#define    RTL8367C_PORT4_MISC_CFG_RX_SPC_OFFSET    9\n#define    RTL8367C_PORT4_MISC_CFG_RX_SPC_MASK    0x200\n#define    RTL8367C_PORT4_MISC_CFG_CRC_SKIP_OFFSET    8\n#define    RTL8367C_PORT4_MISC_CFG_CRC_SKIP_MASK    0x100\n#define    RTL8367C_PORT4_MISC_CFG_PKTGEN_TX_FIRST_OFFSET    7\n#define    RTL8367C_PORT4_MISC_CFG_PKTGEN_TX_FIRST_MASK    0x80\n#define    RTL8367C_PORT4_MISC_CFG_MAC_LOOPBACK_OFFSET    6\n#define    RTL8367C_PORT4_MISC_CFG_MAC_LOOPBACK_MASK    0x40\n#define    RTL8367C_PORT4_MISC_CFG_VLAN_EGRESS_MODE_OFFSET    4\n#define    RTL8367C_PORT4_MISC_CFG_VLAN_EGRESS_MODE_MASK    0x30\n#define    RTL8367C_PORT4_MISC_CFG_CONGESTION_SUSTAIN_TIME_OFFSET    0\n#define    RTL8367C_PORT4_MISC_CFG_CONGESTION_SUSTAIN_TIME_MASK    0xF\n\n#define    RTL8367C_REG_INGRESSBW_PORT4_RATE_CTRL0    0x008f\n\n#define    RTL8367C_REG_INGRESSBW_PORT4_RATE_CTRL1    0x0090\n#define    RTL8367C_INGRESSBW_PORT4_RATE_CTRL1_DUMMY_OFFSET    3\n#define    RTL8367C_INGRESSBW_PORT4_RATE_CTRL1_DUMMY_MASK    0xFFF8\n#define    RTL8367C_INGRESSBW_PORT4_RATE_CTRL1_INGRESSBW_RATE16_OFFSET    0\n#define    RTL8367C_INGRESSBW_PORT4_RATE_CTRL1_INGRESSBW_RATE16_MASK    0x7\n\n#define    RTL8367C_REG_PORT4_FORCE_RATE0    0x0091\n\n#define    RTL8367C_REG_PORT4_FORCE_RATE1    0x0092\n\n#define    RTL8367C_REG_PORT4_CURENT_RATE0    0x0093\n\n#define    RTL8367C_REG_PORT4_CURENT_RATE1    0x0094\n\n#define    RTL8367C_REG_PORT4_PAGE_COUNTER    0x0095\n#define    RTL8367C_PORT4_PAGE_COUNTER_OFFSET    0\n#define    RTL8367C_PORT4_PAGE_COUNTER_MASK    0x7F\n\n#define    RTL8367C_REG_PAGEMETER_PORT4_CTRL0    0x0096\n\n#define    RTL8367C_REG_PAGEMETER_PORT4_CTRL1    0x0097\n\n#define    RTL8367C_REG_PORT4_EEECFG    0x0098\n#define    RTL8367C_PORT4_EEECFG_EEEP_ENABLE_TX_OFFSET    14\n#define    RTL8367C_PORT4_EEECFG_EEEP_ENABLE_TX_MASK    0x4000\n#define    RTL8367C_PORT4_EEECFG_EEEP_ENABLE_RX_OFFSET    13\n#define    RTL8367C_PORT4_EEECFG_EEEP_ENABLE_RX_MASK    0x2000\n#define    RTL8367C_PORT4_EEECFG_EEE_FORCE_OFFSET    12\n#define    RTL8367C_PORT4_EEECFG_EEE_FORCE_MASK    0x1000\n#define    RTL8367C_PORT4_EEECFG_EEE_100M_OFFSET    11\n#define    RTL8367C_PORT4_EEECFG_EEE_100M_MASK    0x800\n#define    RTL8367C_PORT4_EEECFG_EEE_GIGA_500M_OFFSET    10\n#define    RTL8367C_PORT4_EEECFG_EEE_GIGA_500M_MASK    0x400\n#define    RTL8367C_PORT4_EEECFG_EEE_TX_OFFSET    9\n#define    RTL8367C_PORT4_EEECFG_EEE_TX_MASK    0x200\n#define    RTL8367C_PORT4_EEECFG_EEE_RX_OFFSET    8\n#define    RTL8367C_PORT4_EEECFG_EEE_RX_MASK    0x100\n#define    RTL8367C_PORT4_EEECFG_EEE_DSP_RX_OFFSET    6\n#define    RTL8367C_PORT4_EEECFG_EEE_DSP_RX_MASK    0x40\n#define    RTL8367C_PORT4_EEECFG_EEE_LPI_OFFSET    5\n#define    RTL8367C_PORT4_EEECFG_EEE_LPI_MASK    0x20\n#define    RTL8367C_PORT4_EEECFG_EEE_TX_LPI_OFFSET    4\n#define    RTL8367C_PORT4_EEECFG_EEE_TX_LPI_MASK    0x10\n#define    RTL8367C_PORT4_EEECFG_EEE_RX_LPI_OFFSET    3\n#define    RTL8367C_PORT4_EEECFG_EEE_RX_LPI_MASK    0x8\n#define    RTL8367C_PORT4_EEECFG_EEE_PAUSE_INDICATOR_OFFSET    2\n#define    RTL8367C_PORT4_EEECFG_EEE_PAUSE_INDICATOR_MASK    0x4\n#define    RTL8367C_PORT4_EEECFG_EEE_WAKE_REQ_OFFSET    1\n#define    RTL8367C_PORT4_EEECFG_EEE_WAKE_REQ_MASK    0x2\n#define    RTL8367C_PORT4_EEECFG_EEE_SLEEP_REQ_OFFSET    0\n#define    RTL8367C_PORT4_EEECFG_EEE_SLEEP_REQ_MASK    0x1\n\n#define    RTL8367C_REG_PORT4_EEETXMTR    0x0099\n\n#define    RTL8367C_REG_PORT4_EEERXMTR    0x009a\n\n#define    RTL8367C_REG_PORT4_EEEPTXMTR    0x009b\n\n#define    RTL8367C_REG_PORT4_EEEPRXMTR    0x009c\n\n#define    RTL8367C_REG_PTP_PORT4_CFG1    0x009e\n#define    RTL8367C_PTP_PORT4_CFG1_OFFSET    7\n#define    RTL8367C_PTP_PORT4_CFG1_MASK    0xFF\n\n#define    RTL8367C_REG_P4_MSIC1    0x009f\n#define    RTL8367C_P4_MSIC1_OFFSET    0\n#define    RTL8367C_P4_MSIC1_MASK    0x1\n\n#define    RTL8367C_REG_PORT5_CGST_HALF_CFG    0x00a0\n#define    RTL8367C_PORT5_CGST_HALF_CFG_CONGESTION_TIME_OFFSET    4\n#define    RTL8367C_PORT5_CGST_HALF_CFG_CONGESTION_TIME_MASK    0xF0\n#define    RTL8367C_PORT5_CGST_HALF_CFG_CONGESTION_SUSTAIN_TIME_OFFSET    0\n#define    RTL8367C_PORT5_CGST_HALF_CFG_CONGESTION_SUSTAIN_TIME_MASK    0xF\n\n#define    RTL8367C_REG_PKTGEN_PORT5_CTRL    0x00a1\n#define    RTL8367C_PKTGEN_PORT5_CTRL_STATUS_OFFSET    15\n#define    RTL8367C_PKTGEN_PORT5_CTRL_STATUS_MASK    0x8000\n#define    RTL8367C_PKTGEN_PORT5_CTRL_PKTGEN_STS_OFFSET    13\n#define    RTL8367C_PKTGEN_PORT5_CTRL_PKTGEN_STS_MASK    0x2000\n#define    RTL8367C_PKTGEN_PORT5_CTRL_CRC_NO_ERROR_OFFSET    4\n#define    RTL8367C_PKTGEN_PORT5_CTRL_CRC_NO_ERROR_MASK    0x10\n#define    RTL8367C_PKTGEN_PORT5_CTRL_CMD_START_OFFSET    0\n#define    RTL8367C_PKTGEN_PORT5_CTRL_CMD_START_MASK    0x1\n\n#define    RTL8367C_REG_TX_ERR_CNT_PORT5    0x00a2\n#define    RTL8367C_TX_ERR_CNT_PORT5_OFFSET    0\n#define    RTL8367C_TX_ERR_CNT_PORT5_MASK    0x7\n\n#define    RTL8367C_REG_PKTGEN_PORT5_DA0    0x00a3\n\n#define    RTL8367C_REG_PKTGEN_PORT5_DA1    0x00a4\n\n#define    RTL8367C_REG_PKTGEN_PORT5_DA2    0x00a5\n\n#define    RTL8367C_REG_PKTGEN_PORT5_SA0    0x00a6\n\n#define    RTL8367C_REG_PKTGEN_PORT5_SA1    0x00a7\n\n#define    RTL8367C_REG_PKTGEN_PORT5_SA2    0x00a8\n\n#define    RTL8367C_REG_PKTGEN_PORT5_COUNTER0    0x00a9\n\n#define    RTL8367C_REG_PKTGEN_PORT5_COUNTER1    0x00aa\n#define    RTL8367C_PKTGEN_PORT5_COUNTER1_OFFSET    0\n#define    RTL8367C_PKTGEN_PORT5_COUNTER1_MASK    0xFF\n\n#define    RTL8367C_REG_PKTGEN_PORT5_TX_LENGTH    0x00ab\n#define    RTL8367C_PKTGEN_PORT5_TX_LENGTH_OFFSET    0\n#define    RTL8367C_PKTGEN_PORT5_TX_LENGTH_MASK    0x3FFF\n\n#define    RTL8367C_REG_PKTGEN_PORT5_TIMER    0x00ad\n#define    RTL8367C_PKTGEN_PORT5_TIMER_TIMER_OFFSET    4\n#define    RTL8367C_PKTGEN_PORT5_TIMER_TIMER_MASK    0xF0\n#define    RTL8367C_PKTGEN_PORT5_TIMER_RX_DMA_ERR_FLAG_OFFSET    3\n#define    RTL8367C_PKTGEN_PORT5_TIMER_RX_DMA_ERR_FLAG_MASK    0x8\n\n#define    RTL8367C_REG_PORT5_MISC_CFG    0x00ae\n#define    RTL8367C_PORT5_MISC_CFG_SMALL_TAG_IPG_OFFSET    15\n#define    RTL8367C_PORT5_MISC_CFG_SMALL_TAG_IPG_MASK    0x8000\n#define    RTL8367C_PORT5_MISC_CFG_TX_ITFSP_MODE_OFFSET    14\n#define    RTL8367C_PORT5_MISC_CFG_TX_ITFSP_MODE_MASK    0x4000\n#define    RTL8367C_PORT5_MISC_CFG_FLOWCTRL_INDEP_OFFSET    13\n#define    RTL8367C_PORT5_MISC_CFG_FLOWCTRL_INDEP_MASK    0x2000\n#define    RTL8367C_PORT5_MISC_CFG_DOT1Q_REMARK_ENABLE_OFFSET    12\n#define    RTL8367C_PORT5_MISC_CFG_DOT1Q_REMARK_ENABLE_MASK    0x1000\n#define    RTL8367C_PORT5_MISC_CFG_INGRESSBW_FLOWCTRL_OFFSET    11\n#define    RTL8367C_PORT5_MISC_CFG_INGRESSBW_FLOWCTRL_MASK    0x800\n#define    RTL8367C_PORT5_MISC_CFG_INGRESSBW_IFG_OFFSET    10\n#define    RTL8367C_PORT5_MISC_CFG_INGRESSBW_IFG_MASK    0x400\n#define    RTL8367C_PORT5_MISC_CFG_RX_SPC_OFFSET    9\n#define    RTL8367C_PORT5_MISC_CFG_RX_SPC_MASK    0x200\n#define    RTL8367C_PORT5_MISC_CFG_CRC_SKIP_OFFSET    8\n#define    RTL8367C_PORT5_MISC_CFG_CRC_SKIP_MASK    0x100\n#define    RTL8367C_PORT5_MISC_CFG_PKTGEN_TX_FIRST_OFFSET    7\n#define    RTL8367C_PORT5_MISC_CFG_PKTGEN_TX_FIRST_MASK    0x80\n#define    RTL8367C_PORT5_MISC_CFG_MAC_LOOPBACK_OFFSET    6\n#define    RTL8367C_PORT5_MISC_CFG_MAC_LOOPBACK_MASK    0x40\n#define    RTL8367C_PORT5_MISC_CFG_VLAN_EGRESS_MODE_OFFSET    4\n#define    RTL8367C_PORT5_MISC_CFG_VLAN_EGRESS_MODE_MASK    0x30\n#define    RTL8367C_PORT5_MISC_CFG_CONGESTION_SUSTAIN_TIME_OFFSET    0\n#define    RTL8367C_PORT5_MISC_CFG_CONGESTION_SUSTAIN_TIME_MASK    0xF\n\n#define    RTL8367C_REG_INGRESSBW_PORT5_RATE_CTRL0    0x00af\n\n#define    RTL8367C_REG_INGRESSBW_PORT5_RATE_CTRL1    0x00b0\n#define    RTL8367C_INGRESSBW_PORT5_RATE_CTRL1_DUMMY_OFFSET    3\n#define    RTL8367C_INGRESSBW_PORT5_RATE_CTRL1_DUMMY_MASK    0xFFF8\n#define    RTL8367C_INGRESSBW_PORT5_RATE_CTRL1_INGRESSBW_RATE16_OFFSET    0\n#define    RTL8367C_INGRESSBW_PORT5_RATE_CTRL1_INGRESSBW_RATE16_MASK    0x7\n\n#define    RTL8367C_REG_PORT5_FORCE_RATE0    0x00b1\n\n#define    RTL8367C_REG_PORT5_FORCE_RATE1    0x00b2\n\n#define    RTL8367C_REG_PORT5_CURENT_RATE0    0x00b3\n\n#define    RTL8367C_REG_PORT5_CURENT_RATE1    0x00b4\n\n#define    RTL8367C_REG_PORT5_PAGE_COUNTER    0x00b5\n#define    RTL8367C_PORT5_PAGE_COUNTER_OFFSET    0\n#define    RTL8367C_PORT5_PAGE_COUNTER_MASK    0x7F\n\n#define    RTL8367C_REG_PAGEMETER_PORT5_CTRL0    0x00b6\n\n#define    RTL8367C_REG_PAGEMETER_PORT5_CTRL1    0x00b7\n\n#define    RTL8367C_REG_PORT5_EEECFG    0x00b8\n#define    RTL8367C_PORT5_EEECFG_EEEP_ENABLE_TX_OFFSET    14\n#define    RTL8367C_PORT5_EEECFG_EEEP_ENABLE_TX_MASK    0x4000\n#define    RTL8367C_PORT5_EEECFG_EEEP_ENABLE_RX_OFFSET    13\n#define    RTL8367C_PORT5_EEECFG_EEEP_ENABLE_RX_MASK    0x2000\n#define    RTL8367C_PORT5_EEECFG_EEE_FORCE_OFFSET    12\n#define    RTL8367C_PORT5_EEECFG_EEE_FORCE_MASK    0x1000\n#define    RTL8367C_PORT5_EEECFG_EEE_100M_OFFSET    11\n#define    RTL8367C_PORT5_EEECFG_EEE_100M_MASK    0x800\n#define    RTL8367C_PORT5_EEECFG_EEE_GIGA_500M_OFFSET    10\n#define    RTL8367C_PORT5_EEECFG_EEE_GIGA_500M_MASK    0x400\n#define    RTL8367C_PORT5_EEECFG_EEE_TX_OFFSET    9\n#define    RTL8367C_PORT5_EEECFG_EEE_TX_MASK    0x200\n#define    RTL8367C_PORT5_EEECFG_EEE_RX_OFFSET    8\n#define    RTL8367C_PORT5_EEECFG_EEE_RX_MASK    0x100\n#define    RTL8367C_PORT5_EEECFG_EEE_DSP_RX_OFFSET    6\n#define    RTL8367C_PORT5_EEECFG_EEE_DSP_RX_MASK    0x40\n#define    RTL8367C_PORT5_EEECFG_EEE_LPI_OFFSET    5\n#define    RTL8367C_PORT5_EEECFG_EEE_LPI_MASK    0x20\n#define    RTL8367C_PORT5_EEECFG_EEE_TX_LPI_OFFSET    4\n#define    RTL8367C_PORT5_EEECFG_EEE_TX_LPI_MASK    0x10\n#define    RTL8367C_PORT5_EEECFG_EEE_RX_LPI_OFFSET    3\n#define    RTL8367C_PORT5_EEECFG_EEE_RX_LPI_MASK    0x8\n#define    RTL8367C_PORT5_EEECFG_EEE_PAUSE_INDICATOR_OFFSET    2\n#define    RTL8367C_PORT5_EEECFG_EEE_PAUSE_INDICATOR_MASK    0x4\n#define    RTL8367C_PORT5_EEECFG_EEE_WAKE_REQ_OFFSET    1\n#define    RTL8367C_PORT5_EEECFG_EEE_WAKE_REQ_MASK    0x2\n#define    RTL8367C_PORT5_EEECFG_EEE_SLEEP_REQ_OFFSET    0\n#define    RTL8367C_PORT5_EEECFG_EEE_SLEEP_REQ_MASK    0x1\n\n#define    RTL8367C_REG_PORT5_EEETXMTR    0x00b9\n\n#define    RTL8367C_REG_PORT5_EEERXMTR    0x00ba\n\n#define    RTL8367C_REG_PORT5_EEEPTXMTR    0x00bb\n\n#define    RTL8367C_REG_PORT5_EEEPRXMTR    0x00bc\n\n#define    RTL8367C_REG_PTP_PORT5_CFG1    0x00be\n#define    RTL8367C_PTP_PORT5_CFG1_OFFSET    7\n#define    RTL8367C_PTP_PORT5_CFG1_MASK    0xFF\n\n#define    RTL8367C_REG_P5_MSIC1    0x00bf\n#define    RTL8367C_P5_MSIC1_OFFSET    0\n#define    RTL8367C_P5_MSIC1_MASK    0x1\n\n#define    RTL8367C_REG_PORT6_CGST_HALF_CFG    0x00c0\n#define    RTL8367C_PORT6_CGST_HALF_CFG_CONGESTION_TIME_OFFSET    4\n#define    RTL8367C_PORT6_CGST_HALF_CFG_CONGESTION_TIME_MASK    0xF0\n#define    RTL8367C_PORT6_CGST_HALF_CFG_CONGESTION_SUSTAIN_TIME_OFFSET    0\n#define    RTL8367C_PORT6_CGST_HALF_CFG_CONGESTION_SUSTAIN_TIME_MASK    0xF\n\n#define    RTL8367C_REG_PKTGEN_PORT6_CTRL    0x00c1\n#define    RTL8367C_PKTGEN_PORT6_CTRL_STATUS_OFFSET    15\n#define    RTL8367C_PKTGEN_PORT6_CTRL_STATUS_MASK    0x8000\n#define    RTL8367C_PKTGEN_PORT6_CTRL_PKTGEN_STS_OFFSET    13\n#define    RTL8367C_PKTGEN_PORT6_CTRL_PKTGEN_STS_MASK    0x2000\n#define    RTL8367C_PKTGEN_PORT6_CTRL_CRC_NO_ERROR_OFFSET    4\n#define    RTL8367C_PKTGEN_PORT6_CTRL_CRC_NO_ERROR_MASK    0x10\n#define    RTL8367C_PKTGEN_PORT6_CTRL_CMD_START_OFFSET    0\n#define    RTL8367C_PKTGEN_PORT6_CTRL_CMD_START_MASK    0x1\n\n#define    RTL8367C_REG_TX_ERR_CNT_PORT6    0x00c2\n#define    RTL8367C_TX_ERR_CNT_PORT6_OFFSET    0\n#define    RTL8367C_TX_ERR_CNT_PORT6_MASK    0x7\n\n#define    RTL8367C_REG_PKTGEN_PORT6_DA0    0x00c3\n\n#define    RTL8367C_REG_PKTGEN_PORT6_DA1    0x00c4\n\n#define    RTL8367C_REG_PKTGEN_PORT6_DA2    0x00c5\n\n#define    RTL8367C_REG_PKTGEN_PORT6_SA0    0x00c6\n\n#define    RTL8367C_REG_PKTGEN_PORT6_SA1    0x00c7\n\n#define    RTL8367C_REG_PKTGEN_PORT6_SA2    0x00c8\n\n#define    RTL8367C_REG_PKTGEN_PORT6_COUNTER0    0x00c9\n\n#define    RTL8367C_REG_PKTGEN_PORT6_COUNTER1    0x00ca\n#define    RTL8367C_PKTGEN_PORT6_COUNTER1_OFFSET    0\n#define    RTL8367C_PKTGEN_PORT6_COUNTER1_MASK    0xFF\n\n#define    RTL8367C_REG_PKTGEN_PORT6_TX_LENGTH    0x00cb\n#define    RTL8367C_PKTGEN_PORT6_TX_LENGTH_OFFSET    0\n#define    RTL8367C_PKTGEN_PORT6_TX_LENGTH_MASK    0x3FFF\n\n#define    RTL8367C_REG_PKTGEN_PORT6_TIMER    0x00cd\n#define    RTL8367C_PKTGEN_PORT6_TIMER_TIMER_OFFSET    4\n#define    RTL8367C_PKTGEN_PORT6_TIMER_TIMER_MASK    0xF0\n#define    RTL8367C_PKTGEN_PORT6_TIMER_RX_DMA_ERR_FLAG_OFFSET    3\n#define    RTL8367C_PKTGEN_PORT6_TIMER_RX_DMA_ERR_FLAG_MASK    0x8\n\n#define    RTL8367C_REG_PORT6_MISC_CFG    0x00ce\n#define    RTL8367C_PORT6_MISC_CFG_SMALL_TAG_IPG_OFFSET    15\n#define    RTL8367C_PORT6_MISC_CFG_SMALL_TAG_IPG_MASK    0x8000\n#define    RTL8367C_PORT6_MISC_CFG_TX_ITFSP_MODE_OFFSET    14\n#define    RTL8367C_PORT6_MISC_CFG_TX_ITFSP_MODE_MASK    0x4000\n#define    RTL8367C_PORT6_MISC_CFG_FLOWCTRL_INDEP_OFFSET    13\n#define    RTL8367C_PORT6_MISC_CFG_FLOWCTRL_INDEP_MASK    0x2000\n#define    RTL8367C_PORT6_MISC_CFG_DOT1Q_REMARK_ENABLE_OFFSET    12\n#define    RTL8367C_PORT6_MISC_CFG_DOT1Q_REMARK_ENABLE_MASK    0x1000\n#define    RTL8367C_PORT6_MISC_CFG_INGRESSBW_FLOWCTRL_OFFSET    11\n#define    RTL8367C_PORT6_MISC_CFG_INGRESSBW_FLOWCTRL_MASK    0x800\n#define    RTL8367C_PORT6_MISC_CFG_INGRESSBW_IFG_OFFSET    10\n#define    RTL8367C_PORT6_MISC_CFG_INGRESSBW_IFG_MASK    0x400\n#define    RTL8367C_PORT6_MISC_CFG_RX_SPC_OFFSET    9\n#define    RTL8367C_PORT6_MISC_CFG_RX_SPC_MASK    0x200\n#define    RTL8367C_PORT6_MISC_CFG_CRC_SKIP_OFFSET    8\n#define    RTL8367C_PORT6_MISC_CFG_CRC_SKIP_MASK    0x100\n#define    RTL8367C_PORT6_MISC_CFG_PKTGEN_TX_FIRST_OFFSET    7\n#define    RTL8367C_PORT6_MISC_CFG_PKTGEN_TX_FIRST_MASK    0x80\n#define    RTL8367C_PORT6_MISC_CFG_MAC_LOOPBACK_OFFSET    6\n#define    RTL8367C_PORT6_MISC_CFG_MAC_LOOPBACK_MASK    0x40\n#define    RTL8367C_PORT6_MISC_CFG_VLAN_EGRESS_MODE_OFFSET    4\n#define    RTL8367C_PORT6_MISC_CFG_VLAN_EGRESS_MODE_MASK    0x30\n#define    RTL8367C_PORT6_MISC_CFG_CONGESTION_SUSTAIN_TIME_OFFSET    0\n#define    RTL8367C_PORT6_MISC_CFG_CONGESTION_SUSTAIN_TIME_MASK    0xF\n\n#define    RTL8367C_REG_INGRESSBW_PORT6_RATE_CTRL0    0x00cf\n\n#define    RTL8367C_REG_INGRESSBW_PORT6_RATE_CTRL1    0x00d0\n#define    RTL8367C_INGRESSBW_PORT6_RATE_CTRL1_DUMMY_OFFSET    3\n#define    RTL8367C_INGRESSBW_PORT6_RATE_CTRL1_DUMMY_MASK    0xFFF8\n#define    RTL8367C_INGRESSBW_PORT6_RATE_CTRL1_INGRESSBW_RATE16_OFFSET    0\n#define    RTL8367C_INGRESSBW_PORT6_RATE_CTRL1_INGRESSBW_RATE16_MASK    0x7\n\n#define    RTL8367C_REG_PORT6_FORCE_RATE0    0x00d1\n\n#define    RTL8367C_REG_PORT6_FORCE_RATE1    0x00d2\n\n#define    RTL8367C_REG_PORT6_CURENT_RATE0    0x00d3\n\n#define    RTL8367C_REG_PORT6_CURENT_RATE1    0x00d4\n\n#define    RTL8367C_REG_PORT6_PAGE_COUNTER    0x00d5\n#define    RTL8367C_PORT6_PAGE_COUNTER_OFFSET    0\n#define    RTL8367C_PORT6_PAGE_COUNTER_MASK    0x7F\n\n#define    RTL8367C_REG_PAGEMETER_PORT6_CTRL0    0x00d6\n\n#define    RTL8367C_REG_PAGEMETER_PORT6_CTRL1    0x00d7\n\n#define    RTL8367C_REG_PORT6_EEECFG    0x00d8\n#define    RTL8367C_PORT6_EEECFG_EEEP_ENABLE_TX_OFFSET    14\n#define    RTL8367C_PORT6_EEECFG_EEEP_ENABLE_TX_MASK    0x4000\n#define    RTL8367C_PORT6_EEECFG_EEEP_ENABLE_RX_OFFSET    13\n#define    RTL8367C_PORT6_EEECFG_EEEP_ENABLE_RX_MASK    0x2000\n#define    RTL8367C_PORT6_EEECFG_EEE_FORCE_OFFSET    12\n#define    RTL8367C_PORT6_EEECFG_EEE_FORCE_MASK    0x1000\n#define    RTL8367C_PORT6_EEECFG_EEE_100M_OFFSET    11\n#define    RTL8367C_PORT6_EEECFG_EEE_100M_MASK    0x800\n#define    RTL8367C_PORT6_EEECFG_EEE_GIGA_500M_OFFSET    10\n#define    RTL8367C_PORT6_EEECFG_EEE_GIGA_500M_MASK    0x400\n#define    RTL8367C_PORT6_EEECFG_EEE_TX_OFFSET    9\n#define    RTL8367C_PORT6_EEECFG_EEE_TX_MASK    0x200\n#define    RTL8367C_PORT6_EEECFG_EEE_RX_OFFSET    8\n#define    RTL8367C_PORT6_EEECFG_EEE_RX_MASK    0x100\n#define    RTL8367C_PORT6_EEECFG_EEE_DSP_RX_OFFSET    6\n#define    RTL8367C_PORT6_EEECFG_EEE_DSP_RX_MASK    0x40\n#define    RTL8367C_PORT6_EEECFG_EEE_LPI_OFFSET    5\n#define    RTL8367C_PORT6_EEECFG_EEE_LPI_MASK    0x20\n#define    RTL8367C_PORT6_EEECFG_EEE_TX_LPI_OFFSET    4\n#define    RTL8367C_PORT6_EEECFG_EEE_TX_LPI_MASK    0x10\n#define    RTL8367C_PORT6_EEECFG_EEE_RX_LPI_OFFSET    3\n#define    RTL8367C_PORT6_EEECFG_EEE_RX_LPI_MASK    0x8\n#define    RTL8367C_PORT6_EEECFG_EEE_PAUSE_INDICATOR_OFFSET    2\n#define    RTL8367C_PORT6_EEECFG_EEE_PAUSE_INDICATOR_MASK    0x4\n#define    RTL8367C_PORT6_EEECFG_EEE_WAKE_REQ_OFFSET    1\n#define    RTL8367C_PORT6_EEECFG_EEE_WAKE_REQ_MASK    0x2\n#define    RTL8367C_PORT6_EEECFG_EEE_SLEEP_REQ_OFFSET    0\n#define    RTL8367C_PORT6_EEECFG_EEE_SLEEP_REQ_MASK    0x1\n\n#define    RTL8367C_REG_PORT6_EEETXMTR    0x00d9\n\n#define    RTL8367C_REG_PORT6_EEERXMTR    0x00da\n\n#define    RTL8367C_REG_PORT6_EEEPTXMTR    0x00db\n\n#define    RTL8367C_REG_PORT6_EEEPRXMTR    0x00dc\n\n#define    RTL8367C_REG_PTP_PORT6_CFG1    0x00de\n#define    RTL8367C_PTP_PORT6_CFG1_OFFSET    7\n#define    RTL8367C_PTP_PORT6_CFG1_MASK    0xFF\n\n#define    RTL8367C_REG_P6_MSIC1    0x00df\n#define    RTL8367C_P6_MSIC1_OFFSET    0\n#define    RTL8367C_P6_MSIC1_MASK    0x1\n\n#define    RTL8367C_REG_PORT7_CGST_HALF_CFG    0x00e0\n#define    RTL8367C_PORT7_CGST_HALF_CFG_CONGESTION_TIME_OFFSET    4\n#define    RTL8367C_PORT7_CGST_HALF_CFG_CONGESTION_TIME_MASK    0xF0\n#define    RTL8367C_PORT7_CGST_HALF_CFG_CONGESTION_SUSTAIN_TIME_OFFSET    0\n#define    RTL8367C_PORT7_CGST_HALF_CFG_CONGESTION_SUSTAIN_TIME_MASK    0xF\n\n#define    RTL8367C_REG_PKTGEN_PORT7_CTRL    0x00e1\n#define    RTL8367C_PKTGEN_PORT7_CTRL_STATUS_OFFSET    15\n#define    RTL8367C_PKTGEN_PORT7_CTRL_STATUS_MASK    0x8000\n#define    RTL8367C_PKTGEN_PORT7_CTRL_PKTGEN_STS_OFFSET    13\n#define    RTL8367C_PKTGEN_PORT7_CTRL_PKTGEN_STS_MASK    0x2000\n#define    RTL8367C_PKTGEN_PORT7_CTRL_CRC_NO_ERROR_OFFSET    4\n#define    RTL8367C_PKTGEN_PORT7_CTRL_CRC_NO_ERROR_MASK    0x10\n#define    RTL8367C_PKTGEN_PORT7_CTRL_CMD_START_OFFSET    0\n#define    RTL8367C_PKTGEN_PORT7_CTRL_CMD_START_MASK    0x1\n\n#define    RTL8367C_REG_TX_ERR_CNT_PORT7    0x00e2\n#define    RTL8367C_TX_ERR_CNT_PORT7_OFFSET    0\n#define    RTL8367C_TX_ERR_CNT_PORT7_MASK    0x7\n\n#define    RTL8367C_REG_PKTGEN_PORT7_DA0    0x00e3\n\n#define    RTL8367C_REG_PKTGEN_PORT7_DA1    0x00e4\n\n#define    RTL8367C_REG_PKTGEN_PORT7_DA2    0x00e5\n\n#define    RTL8367C_REG_PKTGEN_PORT7_SA0    0x00e6\n\n#define    RTL8367C_REG_PKTGEN_PORT7_SA1    0x00e7\n\n#define    RTL8367C_REG_PKTGEN_PORT7_SA2    0x00e8\n\n#define    RTL8367C_REG_PKTGEN_PORT7_COUNTER0    0x00e9\n\n#define    RTL8367C_REG_PKTGEN_PORT7_COUNTER1    0x00ea\n#define    RTL8367C_PKTGEN_PORT7_COUNTER1_OFFSET    0\n#define    RTL8367C_PKTGEN_PORT7_COUNTER1_MASK    0xFF\n\n#define    RTL8367C_REG_PKTGEN_PORT7_TX_LENGTH    0x00eb\n#define    RTL8367C_PKTGEN_PORT7_TX_LENGTH_OFFSET    0\n#define    RTL8367C_PKTGEN_PORT7_TX_LENGTH_MASK    0x3FFF\n\n#define    RTL8367C_REG_PKTGEN_PORT7_TIMER    0x00ed\n#define    RTL8367C_PKTGEN_PORT7_TIMER_TIMER_OFFSET    4\n#define    RTL8367C_PKTGEN_PORT7_TIMER_TIMER_MASK    0xF0\n#define    RTL8367C_PKTGEN_PORT7_TIMER_RX_DMA_ERR_FLAG_OFFSET    3\n#define    RTL8367C_PKTGEN_PORT7_TIMER_RX_DMA_ERR_FLAG_MASK    0x8\n\n#define    RTL8367C_REG_PORT7_MISC_CFG    0x00ee\n#define    RTL8367C_PORT7_MISC_CFG_SMALL_TAG_IPG_OFFSET    15\n#define    RTL8367C_PORT7_MISC_CFG_SMALL_TAG_IPG_MASK    0x8000\n#define    RTL8367C_PORT7_MISC_CFG_TX_ITFSP_MODE_OFFSET    14\n#define    RTL8367C_PORT7_MISC_CFG_TX_ITFSP_MODE_MASK    0x4000\n#define    RTL8367C_PORT7_MISC_CFG_FLOWCTRL_INDEP_OFFSET    13\n#define    RTL8367C_PORT7_MISC_CFG_FLOWCTRL_INDEP_MASK    0x2000\n#define    RTL8367C_PORT7_MISC_CFG_DOT1Q_REMARK_ENABLE_OFFSET    12\n#define    RTL8367C_PORT7_MISC_CFG_DOT1Q_REMARK_ENABLE_MASK    0x1000\n#define    RTL8367C_PORT7_MISC_CFG_INGRESSBW_FLOWCTRL_OFFSET    11\n#define    RTL8367C_PORT7_MISC_CFG_INGRESSBW_FLOWCTRL_MASK    0x800\n#define    RTL8367C_PORT7_MISC_CFG_INGRESSBW_IFG_OFFSET    10\n#define    RTL8367C_PORT7_MISC_CFG_INGRESSBW_IFG_MASK    0x400\n#define    RTL8367C_PORT7_MISC_CFG_RX_SPC_OFFSET    9\n#define    RTL8367C_PORT7_MISC_CFG_RX_SPC_MASK    0x200\n#define    RTL8367C_PORT7_MISC_CFG_CRC_SKIP_OFFSET    8\n#define    RTL8367C_PORT7_MISC_CFG_CRC_SKIP_MASK    0x100\n#define    RTL8367C_PORT7_MISC_CFG_PKTGEN_TX_FIRST_OFFSET    7\n#define    RTL8367C_PORT7_MISC_CFG_PKTGEN_TX_FIRST_MASK    0x80\n#define    RTL8367C_PORT7_MISC_CFG_MAC_LOOPBACK_OFFSET    6\n#define    RTL8367C_PORT7_MISC_CFG_MAC_LOOPBACK_MASK    0x40\n#define    RTL8367C_PORT7_MISC_CFG_VLAN_EGRESS_MODE_OFFSET    4\n#define    RTL8367C_PORT7_MISC_CFG_VLAN_EGRESS_MODE_MASK    0x30\n#define    RTL8367C_PORT7_MISC_CFG_CONGESTION_SUSTAIN_TIME_OFFSET    0\n#define    RTL8367C_PORT7_MISC_CFG_CONGESTION_SUSTAIN_TIME_MASK    0xF\n\n#define    RTL8367C_REG_INGRESSBW_PORT7_RATE_CTRL0    0x00ef\n\n#define    RTL8367C_REG_INGRESSBW_PORT7_RATE_CTRL1    0x00f0\n#define    RTL8367C_INGRESSBW_PORT7_RATE_CTRL1_DUMMY_OFFSET    3\n#define    RTL8367C_INGRESSBW_PORT7_RATE_CTRL1_DUMMY_MASK    0xFFF8\n#define    RTL8367C_INGRESSBW_PORT7_RATE_CTRL1_INGRESSBW_RATE16_OFFSET    0\n#define    RTL8367C_INGRESSBW_PORT7_RATE_CTRL1_INGRESSBW_RATE16_MASK    0x7\n\n#define    RTL8367C_REG_PORT7_FORCE_RATE0    0x00f1\n\n#define    RTL8367C_REG_PORT7_FORCE_RATE1    0x00f2\n\n#define    RTL8367C_REG_PORT7_CURENT_RATE0    0x00f3\n\n#define    RTL8367C_REG_PORT7_CURENT_RATE1    0x00f4\n\n#define    RTL8367C_REG_PORT7_PAGE_COUNTER    0x00f5\n#define    RTL8367C_PORT7_PAGE_COUNTER_OFFSET    0\n#define    RTL8367C_PORT7_PAGE_COUNTER_MASK    0x7F\n\n#define    RTL8367C_REG_PAGEMETER_PORT7_CTRL0    0x00f6\n\n#define    RTL8367C_REG_PAGEMETER_PORT7_CTRL1    0x00f7\n\n#define    RTL8367C_REG_PORT7_EEECFG    0x00f8\n#define    RTL8367C_PORT7_EEECFG_EEEP_ENABLE_TX_OFFSET    14\n#define    RTL8367C_PORT7_EEECFG_EEEP_ENABLE_TX_MASK    0x4000\n#define    RTL8367C_PORT7_EEECFG_EEEP_ENABLE_RX_OFFSET    13\n#define    RTL8367C_PORT7_EEECFG_EEEP_ENABLE_RX_MASK    0x2000\n#define    RTL8367C_PORT7_EEECFG_EEE_FORCE_OFFSET    12\n#define    RTL8367C_PORT7_EEECFG_EEE_FORCE_MASK    0x1000\n#define    RTL8367C_PORT7_EEECFG_EEE_100M_OFFSET    11\n#define    RTL8367C_PORT7_EEECFG_EEE_100M_MASK    0x800\n#define    RTL8367C_PORT7_EEECFG_EEE_GIGA_500M_OFFSET    10\n#define    RTL8367C_PORT7_EEECFG_EEE_GIGA_500M_MASK    0x400\n#define    RTL8367C_PORT7_EEECFG_EEE_TX_OFFSET    9\n#define    RTL8367C_PORT7_EEECFG_EEE_TX_MASK    0x200\n#define    RTL8367C_PORT7_EEECFG_EEE_RX_OFFSET    8\n#define    RTL8367C_PORT7_EEECFG_EEE_RX_MASK    0x100\n#define    RTL8367C_PORT7_EEECFG_EEE_DSP_RX_OFFSET    6\n#define    RTL8367C_PORT7_EEECFG_EEE_DSP_RX_MASK    0x40\n#define    RTL8367C_PORT7_EEECFG_EEE_LPI_OFFSET    5\n#define    RTL8367C_PORT7_EEECFG_EEE_LPI_MASK    0x20\n#define    RTL8367C_PORT7_EEECFG_EEE_TX_LPI_OFFSET    4\n#define    RTL8367C_PORT7_EEECFG_EEE_TX_LPI_MASK    0x10\n#define    RTL8367C_PORT7_EEECFG_EEE_RX_LPI_OFFSET    3\n#define    RTL8367C_PORT7_EEECFG_EEE_RX_LPI_MASK    0x8\n#define    RTL8367C_PORT7_EEECFG_EEE_PAUSE_INDICATOR_OFFSET    2\n#define    RTL8367C_PORT7_EEECFG_EEE_PAUSE_INDICATOR_MASK    0x4\n#define    RTL8367C_PORT7_EEECFG_EEE_WAKE_REQ_OFFSET    1\n#define    RTL8367C_PORT7_EEECFG_EEE_WAKE_REQ_MASK    0x2\n#define    RTL8367C_PORT7_EEECFG_EEE_SLEEP_REQ_OFFSET    0\n#define    RTL8367C_PORT7_EEECFG_EEE_SLEEP_REQ_MASK    0x1\n\n#define    RTL8367C_REG_PORT7_EEETXMTR    0x00f9\n\n#define    RTL8367C_REG_PORT7_EEERXMTR    0x00fa\n\n#define    RTL8367C_REG_PORT7_EEEPTXMTR    0x00fb\n\n#define    RTL8367C_REG_PORT7_EEEPRXMTR    0x00fc\n\n#define    RTL8367C_REG_PTP_PORT7_CFG1    0x00fe\n#define    RTL8367C_PTP_PORT7_CFG1_OFFSET    7\n#define    RTL8367C_PTP_PORT7_CFG1_MASK    0xFF\n\n#define    RTL8367C_REG_P7_MSIC1    0x00ff\n#define    RTL8367C_P7_MSIC1_OFFSET    0\n#define    RTL8367C_P7_MSIC1_MASK    0x1\n\n#define    RTL8367C_REG_PORT8_CGST_HALF_CFG    0x0100\n#define    RTL8367C_PORT8_CGST_HALF_CFG_CONGESTION_TIME_OFFSET    4\n#define    RTL8367C_PORT8_CGST_HALF_CFG_CONGESTION_TIME_MASK    0xF0\n#define    RTL8367C_PORT8_CGST_HALF_CFG_CONGESTION_SUSTAIN_TIME_OFFSET    0\n#define    RTL8367C_PORT8_CGST_HALF_CFG_CONGESTION_SUSTAIN_TIME_MASK    0xF\n\n#define    RTL8367C_REG_PKTGEN_PORT8_CTRL    0x0101\n#define    RTL8367C_PKTGEN_PORT8_CTRL_STATUS_OFFSET    15\n#define    RTL8367C_PKTGEN_PORT8_CTRL_STATUS_MASK    0x8000\n#define    RTL8367C_PKTGEN_PORT8_CTRL_PKTGEN_STS_OFFSET    13\n#define    RTL8367C_PKTGEN_PORT8_CTRL_PKTGEN_STS_MASK    0x2000\n#define    RTL8367C_PKTGEN_PORT8_CTRL_CRC_NO_ERROR_OFFSET    4\n#define    RTL8367C_PKTGEN_PORT8_CTRL_CRC_NO_ERROR_MASK    0x10\n#define    RTL8367C_PKTGEN_PORT8_CTRL_CMD_START_OFFSET    0\n#define    RTL8367C_PKTGEN_PORT8_CTRL_CMD_START_MASK    0x1\n\n#define    RTL8367C_REG_TX_ERR_CNT_PORT8    0x0102\n#define    RTL8367C_TX_ERR_CNT_PORT8_OFFSET    0\n#define    RTL8367C_TX_ERR_CNT_PORT8_MASK    0x7\n\n#define    RTL8367C_REG_PKTGEN_PORT8_DA0    0x0103\n\n#define    RTL8367C_REG_PKTGEN_PORT8_DA1    0x0104\n\n#define    RTL8367C_REG_PKTGEN_PORT8_DA2    0x0105\n\n#define    RTL8367C_REG_PKTGEN_PORT8_SA0    0x0106\n\n#define    RTL8367C_REG_PKTGEN_PORT8_SA1    0x0107\n\n#define    RTL8367C_REG_PKTGEN_PORT8_SA2    0x0108\n\n#define    RTL8367C_REG_PKTGEN_PORT8_COUNTER0    0x0109\n\n#define    RTL8367C_REG_PKTGEN_PORT8_COUNTER1    0x010a\n#define    RTL8367C_PKTGEN_PORT8_COUNTER1_OFFSET    0\n#define    RTL8367C_PKTGEN_PORT8_COUNTER1_MASK    0xFF\n\n#define    RTL8367C_REG_PKTGEN_PORT8_TX_LENGTH    0x010b\n#define    RTL8367C_PKTGEN_PORT8_TX_LENGTH_OFFSET    0\n#define    RTL8367C_PKTGEN_PORT8_TX_LENGTH_MASK    0x3FFF\n\n#define    RTL8367C_REG_PKTGEN_PORT8_TIMER    0x010d\n#define    RTL8367C_PKTGEN_PORT8_TIMER_TIMER_OFFSET    4\n#define    RTL8367C_PKTGEN_PORT8_TIMER_TIMER_MASK    0xF0\n#define    RTL8367C_PKTGEN_PORT8_TIMER_RX_DMA_ERR_FLAG_OFFSET    3\n#define    RTL8367C_PKTGEN_PORT8_TIMER_RX_DMA_ERR_FLAG_MASK    0x8\n\n#define    RTL8367C_REG_PORT8_MISC_CFG    0x010e\n#define    RTL8367C_PORT8_MISC_CFG_SMALL_TAG_IPG_OFFSET    15\n#define    RTL8367C_PORT8_MISC_CFG_SMALL_TAG_IPG_MASK    0x8000\n#define    RTL8367C_PORT8_MISC_CFG_TX_ITFSP_MODE_OFFSET    14\n#define    RTL8367C_PORT8_MISC_CFG_TX_ITFSP_MODE_MASK    0x4000\n#define    RTL8367C_PORT8_MISC_CFG_FLOWCTRL_INDEP_OFFSET    13\n#define    RTL8367C_PORT8_MISC_CFG_FLOWCTRL_INDEP_MASK    0x2000\n#define    RTL8367C_PORT8_MISC_CFG_DOT1Q_REMARK_ENABLE_OFFSET    12\n#define    RTL8367C_PORT8_MISC_CFG_DOT1Q_REMARK_ENABLE_MASK    0x1000\n#define    RTL8367C_PORT8_MISC_CFG_INGRESSBW_FLOWCTRL_OFFSET    11\n#define    RTL8367C_PORT8_MISC_CFG_INGRESSBW_FLOWCTRL_MASK    0x800\n#define    RTL8367C_PORT8_MISC_CFG_INGRESSBW_IFG_OFFSET    10\n#define    RTL8367C_PORT8_MISC_CFG_INGRESSBW_IFG_MASK    0x400\n#define    RTL8367C_PORT8_MISC_CFG_RX_SPC_OFFSET    9\n#define    RTL8367C_PORT8_MISC_CFG_RX_SPC_MASK    0x200\n#define    RTL8367C_PORT8_MISC_CFG_CRC_SKIP_OFFSET    8\n#define    RTL8367C_PORT8_MISC_CFG_CRC_SKIP_MASK    0x100\n#define    RTL8367C_PORT8_MISC_CFG_PKTGEN_TX_FIRST_OFFSET    7\n#define    RTL8367C_PORT8_MISC_CFG_PKTGEN_TX_FIRST_MASK    0x80\n#define    RTL8367C_PORT8_MISC_CFG_MAC_LOOPBACK_OFFSET    6\n#define    RTL8367C_PORT8_MISC_CFG_MAC_LOOPBACK_MASK    0x40\n#define    RTL8367C_PORT8_MISC_CFG_VLAN_EGRESS_MODE_OFFSET    4\n#define    RTL8367C_PORT8_MISC_CFG_VLAN_EGRESS_MODE_MASK    0x30\n#define    RTL8367C_PORT8_MISC_CFG_CONGESTION_SUSTAIN_TIME_OFFSET    0\n#define    RTL8367C_PORT8_MISC_CFG_CONGESTION_SUSTAIN_TIME_MASK    0xF\n\n#define    RTL8367C_REG_INGRESSBW_PORT8_RATE_CTRL0    0x010f\n\n#define    RTL8367C_REG_INGRESSBW_PORT8_RATE_CTRL1    0x0110\n#define    RTL8367C_INGRESSBW_PORT8_RATE_CTRL1_DUMMY_OFFSET    3\n#define    RTL8367C_INGRESSBW_PORT8_RATE_CTRL1_DUMMY_MASK    0xFFF8\n#define    RTL8367C_INGRESSBW_PORT8_RATE_CTRL1_INGRESSBW_RATE16_OFFSET    0\n#define    RTL8367C_INGRESSBW_PORT8_RATE_CTRL1_INGRESSBW_RATE16_MASK    0x7\n\n#define    RTL8367C_REG_PORT8_FORCE_RATE0    0x0111\n\n#define    RTL8367C_REG_PORT8_FORCE_RATE1    0x0112\n\n#define    RTL8367C_REG_PORT8_CURENT_RATE0    0x0113\n\n#define    RTL8367C_REG_PORT8_CURENT_RATE1    0x0114\n\n#define    RTL8367C_REG_PORT8_PAGE_COUNTER    0x0115\n#define    RTL8367C_PORT8_PAGE_COUNTER_OFFSET    0\n#define    RTL8367C_PORT8_PAGE_COUNTER_MASK    0x7F\n\n#define    RTL8367C_REG_PAGEMETER_PORT8_CTRL0    0x0116\n\n#define    RTL8367C_REG_PAGEMETER_PORT8_CTRL1    0x0117\n\n#define    RTL8367C_REG_PORT8_EEECFG    0x0118\n#define    RTL8367C_PORT8_EEECFG_EEEP_ENABLE_TX_OFFSET    14\n#define    RTL8367C_PORT8_EEECFG_EEEP_ENABLE_TX_MASK    0x4000\n#define    RTL8367C_PORT8_EEECFG_EEEP_ENABLE_RX_OFFSET    13\n#define    RTL8367C_PORT8_EEECFG_EEEP_ENABLE_RX_MASK    0x2000\n#define    RTL8367C_PORT8_EEECFG_EEE_FORCE_OFFSET    12\n#define    RTL8367C_PORT8_EEECFG_EEE_FORCE_MASK    0x1000\n#define    RTL8367C_PORT8_EEECFG_EEE_100M_OFFSET    11\n#define    RTL8367C_PORT8_EEECFG_EEE_100M_MASK    0x800\n#define    RTL8367C_PORT8_EEECFG_EEE_GIGA_500M_OFFSET    10\n#define    RTL8367C_PORT8_EEECFG_EEE_GIGA_500M_MASK    0x400\n#define    RTL8367C_PORT8_EEECFG_EEE_TX_OFFSET    9\n#define    RTL8367C_PORT8_EEECFG_EEE_TX_MASK    0x200\n#define    RTL8367C_PORT8_EEECFG_EEE_RX_OFFSET    8\n#define    RTL8367C_PORT8_EEECFG_EEE_RX_MASK    0x100\n#define    RTL8367C_PORT8_EEECFG_EEE_DSP_RX_OFFSET    6\n#define    RTL8367C_PORT8_EEECFG_EEE_DSP_RX_MASK    0x40\n#define    RTL8367C_PORT8_EEECFG_EEE_LPI_OFFSET    5\n#define    RTL8367C_PORT8_EEECFG_EEE_LPI_MASK    0x20\n#define    RTL8367C_PORT8_EEECFG_EEE_TX_LPI_OFFSET    4\n#define    RTL8367C_PORT8_EEECFG_EEE_TX_LPI_MASK    0x10\n#define    RTL8367C_PORT8_EEECFG_EEE_RX_LPI_OFFSET    3\n#define    RTL8367C_PORT8_EEECFG_EEE_RX_LPI_MASK    0x8\n#define    RTL8367C_PORT8_EEECFG_EEE_PAUSE_INDICATOR_OFFSET    2\n#define    RTL8367C_PORT8_EEECFG_EEE_PAUSE_INDICATOR_MASK    0x4\n#define    RTL8367C_PORT8_EEECFG_EEE_WAKE_REQ_OFFSET    1\n#define    RTL8367C_PORT8_EEECFG_EEE_WAKE_REQ_MASK    0x2\n#define    RTL8367C_PORT8_EEECFG_EEE_SLEEP_REQ_OFFSET    0\n#define    RTL8367C_PORT8_EEECFG_EEE_SLEEP_REQ_MASK    0x1\n\n#define    RTL8367C_REG_PORT8_EEETXMTR    0x0119\n\n#define    RTL8367C_REG_PORT8_EEERXMTR    0x011a\n\n#define    RTL8367C_REG_PORT8_EEEPTXMTR    0x011b\n\n#define    RTL8367C_REG_PORT8_EEEPRXMTR    0x011c\n\n#define    RTL8367C_REG_PTP_PORT8_CFG1    0x011e\n#define    RTL8367C_PTP_PORT8_CFG1_OFFSET    7\n#define    RTL8367C_PTP_PORT8_CFG1_MASK    0xFF\n\n#define    RTL8367C_REG_P8_MSIC1    0x011f\n#define    RTL8367C_P8_MSIC1_OFFSET    0\n#define    RTL8367C_P8_MSIC1_MASK    0x1\n\n#define    RTL8367C_REG_PORT9_CGST_HALF_CFG    0x0120\n#define    RTL8367C_PORT9_CGST_HALF_CFG_CONGESTION_TIME_OFFSET    4\n#define    RTL8367C_PORT9_CGST_HALF_CFG_CONGESTION_TIME_MASK    0xF0\n#define    RTL8367C_PORT9_CGST_HALF_CFG_CONGESTION_SUSTAIN_TIME_OFFSET    0\n#define    RTL8367C_PORT9_CGST_HALF_CFG_CONGESTION_SUSTAIN_TIME_MASK    0xF\n\n#define    RTL8367C_REG_PKTGEN_PORT9_CTRL    0x0121\n#define    RTL8367C_PKTGEN_PORT9_CTRL_STATUS_OFFSET    15\n#define    RTL8367C_PKTGEN_PORT9_CTRL_STATUS_MASK    0x8000\n#define    RTL8367C_PKTGEN_PORT9_CTRL_PKTGEN_STS_OFFSET    13\n#define    RTL8367C_PKTGEN_PORT9_CTRL_PKTGEN_STS_MASK    0x2000\n#define    RTL8367C_PKTGEN_PORT9_CTRL_CRC_NO_ERROR_OFFSET    4\n#define    RTL8367C_PKTGEN_PORT9_CTRL_CRC_NO_ERROR_MASK    0x10\n#define    RTL8367C_PKTGEN_PORT9_CTRL_CMD_START_OFFSET    0\n#define    RTL8367C_PKTGEN_PORT9_CTRL_CMD_START_MASK    0x1\n\n#define    RTL8367C_REG_TX_ERR_CNT_PORT9    0x0122\n#define    RTL8367C_TX_ERR_CNT_PORT9_OFFSET    0\n#define    RTL8367C_TX_ERR_CNT_PORT9_MASK    0x7\n\n#define    RTL8367C_REG_PKTGEN_PORT9_DA0    0x0123\n\n#define    RTL8367C_REG_PKTGEN_PORT9_DA1    0x0124\n\n#define    RTL8367C_REG_PKTGEN_PORT9_DA2    0x0125\n\n#define    RTL8367C_REG_PKTGEN_PORT9_SA0    0x0126\n\n#define    RTL8367C_REG_PKTGEN_PORT9_SA1    0x0127\n\n#define    RTL8367C_REG_PKTGEN_PORT9_SA2    0x0128\n\n#define    RTL8367C_REG_PKTGEN_PORT9_COUNTER0    0x0129\n\n#define    RTL8367C_REG_PKTGEN_PORT9_COUNTER1    0x012a\n#define    RTL8367C_PKTGEN_PORT9_COUNTER1_OFFSET    0\n#define    RTL8367C_PKTGEN_PORT9_COUNTER1_MASK    0xFF\n\n#define    RTL8367C_REG_PKTGEN_PORT9_TX_LENGTH    0x012b\n#define    RTL8367C_PKTGEN_PORT9_TX_LENGTH_OFFSET    0\n#define    RTL8367C_PKTGEN_PORT9_TX_LENGTH_MASK    0x3FFF\n\n#define    RTL8367C_REG_PKTGEN_PORT9_TIMER    0x012d\n#define    RTL8367C_PKTGEN_PORT9_TIMER_TIMER_OFFSET    4\n#define    RTL8367C_PKTGEN_PORT9_TIMER_TIMER_MASK    0xF0\n#define    RTL8367C_PKTGEN_PORT9_TIMER_RX_DMA_ERR_FLAG_OFFSET    3\n#define    RTL8367C_PKTGEN_PORT9_TIMER_RX_DMA_ERR_FLAG_MASK    0x8\n\n#define    RTL8367C_REG_PORT9_MISC_CFG    0x012e\n#define    RTL8367C_PORT9_MISC_CFG_SMALL_TAG_IPG_OFFSET    15\n#define    RTL8367C_PORT9_MISC_CFG_SMALL_TAG_IPG_MASK    0x8000\n#define    RTL8367C_PORT9_MISC_CFG_TX_ITFSP_MODE_OFFSET    14\n#define    RTL8367C_PORT9_MISC_CFG_TX_ITFSP_MODE_MASK    0x4000\n#define    RTL8367C_PORT9_MISC_CFG_FLOWCTRL_INDEP_OFFSET    13\n#define    RTL8367C_PORT9_MISC_CFG_FLOWCTRL_INDEP_MASK    0x2000\n#define    RTL8367C_PORT9_MISC_CFG_DOT1Q_REMARK_ENABLE_OFFSET    12\n#define    RTL8367C_PORT9_MISC_CFG_DOT1Q_REMARK_ENABLE_MASK    0x1000\n#define    RTL8367C_PORT9_MISC_CFG_INGRESSBW_FLOWCTRL_OFFSET    11\n#define    RTL8367C_PORT9_MISC_CFG_INGRESSBW_FLOWCTRL_MASK    0x800\n#define    RTL8367C_PORT9_MISC_CFG_INGRESSBW_IFG_OFFSET    10\n#define    RTL8367C_PORT9_MISC_CFG_INGRESSBW_IFG_MASK    0x400\n#define    RTL8367C_PORT9_MISC_CFG_RX_SPC_OFFSET    9\n#define    RTL8367C_PORT9_MISC_CFG_RX_SPC_MASK    0x200\n#define    RTL8367C_PORT9_MISC_CFG_CRC_SKIP_OFFSET    8\n#define    RTL8367C_PORT9_MISC_CFG_CRC_SKIP_MASK    0x100\n#define    RTL8367C_PORT9_MISC_CFG_PKTGEN_TX_FIRST_OFFSET    7\n#define    RTL8367C_PORT9_MISC_CFG_PKTGEN_TX_FIRST_MASK    0x80\n#define    RTL8367C_PORT9_MISC_CFG_MAC_LOOPBACK_OFFSET    6\n#define    RTL8367C_PORT9_MISC_CFG_MAC_LOOPBACK_MASK    0x40\n#define    RTL8367C_PORT9_MISC_CFG_VLAN_EGRESS_MODE_OFFSET    4\n#define    RTL8367C_PORT9_MISC_CFG_VLAN_EGRESS_MODE_MASK    0x30\n#define    RTL8367C_PORT9_MISC_CFG_CONGESTION_SUSTAIN_TIME_OFFSET    0\n#define    RTL8367C_PORT9_MISC_CFG_CONGESTION_SUSTAIN_TIME_MASK    0xF\n\n#define    RTL8367C_REG_INGRESSBW_PORT9_RATE_CTRL0    0x012f\n\n#define    RTL8367C_REG_INGRESSBW_PORT9_RATE_CTRL1    0x0130\n#define    RTL8367C_INGRESSBW_PORT9_RATE_CTRL1_DUMMY_OFFSET    3\n#define    RTL8367C_INGRESSBW_PORT9_RATE_CTRL1_DUMMY_MASK    0xFFF8\n#define    RTL8367C_INGRESSBW_PORT9_RATE_CTRL1_INGRESSBW_RATE16_OFFSET    0\n#define    RTL8367C_INGRESSBW_PORT9_RATE_CTRL1_INGRESSBW_RATE16_MASK    0x7\n\n#define    RTL8367C_REG_PORT9_FORCE_RATE0    0x0131\n\n#define    RTL8367C_REG_PORT9_FORCE_RATE1    0x0132\n\n#define    RTL8367C_REG_PORT9_CURENT_RATE0    0x0133\n\n#define    RTL8367C_REG_PORT9_CURENT_RATE1    0x0134\n\n#define    RTL8367C_REG_PORT9_PAGE_COUNTER    0x0135\n#define    RTL8367C_PORT9_PAGE_COUNTER_OFFSET    0\n#define    RTL8367C_PORT9_PAGE_COUNTER_MASK    0x7F\n\n#define    RTL8367C_REG_PAGEMETER_PORT9_CTRL0    0x0136\n\n#define    RTL8367C_REG_PAGEMETER_PORT9_CTRL1    0x0137\n\n#define    RTL8367C_REG_PORT9_EEECFG    0x0138\n#define    RTL8367C_PORT9_EEECFG_EEEP_ENABLE_TX_OFFSET    14\n#define    RTL8367C_PORT9_EEECFG_EEEP_ENABLE_TX_MASK    0x4000\n#define    RTL8367C_PORT9_EEECFG_EEEP_ENABLE_RX_OFFSET    13\n#define    RTL8367C_PORT9_EEECFG_EEEP_ENABLE_RX_MASK    0x2000\n#define    RTL8367C_PORT9_EEECFG_EEE_FORCE_OFFSET    12\n#define    RTL8367C_PORT9_EEECFG_EEE_FORCE_MASK    0x1000\n#define    RTL8367C_PORT9_EEECFG_EEE_100M_OFFSET    11\n#define    RTL8367C_PORT9_EEECFG_EEE_100M_MASK    0x800\n#define    RTL8367C_PORT9_EEECFG_EEE_GIGA_500M_OFFSET    10\n#define    RTL8367C_PORT9_EEECFG_EEE_GIGA_500M_MASK    0x400\n#define    RTL8367C_PORT9_EEECFG_EEE_TX_OFFSET    9\n#define    RTL8367C_PORT9_EEECFG_EEE_TX_MASK    0x200\n#define    RTL8367C_PORT9_EEECFG_EEE_RX_OFFSET    8\n#define    RTL8367C_PORT9_EEECFG_EEE_RX_MASK    0x100\n#define    RTL8367C_PORT9_EEECFG_EEE_DSP_RX_OFFSET    6\n#define    RTL8367C_PORT9_EEECFG_EEE_DSP_RX_MASK    0x40\n#define    RTL8367C_PORT9_EEECFG_EEE_LPI_OFFSET    5\n#define    RTL8367C_PORT9_EEECFG_EEE_LPI_MASK    0x20\n#define    RTL8367C_PORT9_EEECFG_EEE_TX_LPI_OFFSET    4\n#define    RTL8367C_PORT9_EEECFG_EEE_TX_LPI_MASK    0x10\n#define    RTL8367C_PORT9_EEECFG_EEE_RX_LPI_OFFSET    3\n#define    RTL8367C_PORT9_EEECFG_EEE_RX_LPI_MASK    0x8\n#define    RTL8367C_PORT9_EEECFG_EEE_PAUSE_INDICATOR_OFFSET    2\n#define    RTL8367C_PORT9_EEECFG_EEE_PAUSE_INDICATOR_MASK    0x4\n#define    RTL8367C_PORT9_EEECFG_EEE_WAKE_REQ_OFFSET    1\n#define    RTL8367C_PORT9_EEECFG_EEE_WAKE_REQ_MASK    0x2\n#define    RTL8367C_PORT9_EEECFG_EEE_SLEEP_REQ_OFFSET    0\n#define    RTL8367C_PORT9_EEECFG_EEE_SLEEP_REQ_MASK    0x1\n\n#define    RTL8367C_REG_PORT9_EEETXMTR    0x0139\n\n#define    RTL8367C_REG_PORT9_EEERXMTR    0x013a\n\n#define    RTL8367C_REG_PORT9_EEEPTXMTR    0x013b\n\n#define    RTL8367C_REG_PORT9_EEEPRXMTR    0x013c\n\n#define    RTL8367C_REG_PTP_PORT9_CFG1    0x013e\n#define    RTL8367C_PTP_PORT9_CFG1_OFFSET    7\n#define    RTL8367C_PTP_PORT9_CFG1_MASK    0xFF\n\n#define    RTL8367C_REG_P9_MSIC1    0x013f\n#define    RTL8367C_P9_MSIC1_OFFSET    0\n#define    RTL8367C_P9_MSIC1_MASK    0x1\n\n#define    RTL8367C_REG_PORT10_CGST_HALF_CFG    0x0140\n#define    RTL8367C_PORT10_CGST_HALF_CFG_CONGESTION_TIME_OFFSET    4\n#define    RTL8367C_PORT10_CGST_HALF_CFG_CONGESTION_TIME_MASK    0xF0\n#define    RTL8367C_PORT10_CGST_HALF_CFG_CONGESTION_SUSTAIN_TIME_OFFSET    0\n#define    RTL8367C_PORT10_CGST_HALF_CFG_CONGESTION_SUSTAIN_TIME_MASK    0xF\n\n#define    RTL8367C_REG_PKTGEN_PORT10_CTRL    0x0141\n#define    RTL8367C_PKTGEN_PORT10_CTRL_STATUS_OFFSET    15\n#define    RTL8367C_PKTGEN_PORT10_CTRL_STATUS_MASK    0x8000\n#define    RTL8367C_PKTGEN_PORT10_CTRL_PKTGEN_STS_OFFSET    13\n#define    RTL8367C_PKTGEN_PORT10_CTRL_PKTGEN_STS_MASK    0x2000\n#define    RTL8367C_PKTGEN_PORT10_CTRL_CRC_NO_ERROR_OFFSET    4\n#define    RTL8367C_PKTGEN_PORT10_CTRL_CRC_NO_ERROR_MASK    0x10\n#define    RTL8367C_PKTGEN_PORT10_CTRL_CMD_START_OFFSET    0\n#define    RTL8367C_PKTGEN_PORT10_CTRL_CMD_START_MASK    0x1\n\n#define    RTL8367C_REG_TX_ERR_CNT_PORT10    0x0142\n#define    RTL8367C_TX_ERR_CNT_PORT10_OFFSET    0\n#define    RTL8367C_TX_ERR_CNT_PORT10_MASK    0x7\n\n#define    RTL8367C_REG_PKTGEN_PORT10_DA0    0x0143\n\n#define    RTL8367C_REG_PKTGEN_PORT10_DA1    0x0144\n\n#define    RTL8367C_REG_PKTGEN_PORT10_DA2    0x0145\n\n#define    RTL8367C_REG_PKTGEN_PORT10_SA0    0x0146\n\n#define    RTL8367C_REG_PKTGEN_PORT10_SA1    0x0147\n\n#define    RTL8367C_REG_PKTGEN_PORT10_SA2    0x0148\n\n#define    RTL8367C_REG_PKTGEN_PORT10_COUNTER0    0x0149\n\n#define    RTL8367C_REG_PKTGEN_PORT10_COUNTER1    0x014a\n#define    RTL8367C_PKTGEN_PORT10_COUNTER1_OFFSET    0\n#define    RTL8367C_PKTGEN_PORT10_COUNTER1_MASK    0xFF\n\n#define    RTL8367C_REG_PKTGEN_PORT10_TX_LENGTH    0x014b\n#define    RTL8367C_PKTGEN_PORT10_TX_LENGTH_OFFSET    0\n#define    RTL8367C_PKTGEN_PORT10_TX_LENGTH_MASK    0x3FFF\n\n#define    RTL8367C_REG_PKTGEN_PORT10_TIMER    0x014d\n#define    RTL8367C_PKTGEN_PORT10_TIMER_TIMER_OFFSET    4\n#define    RTL8367C_PKTGEN_PORT10_TIMER_TIMER_MASK    0xF0\n#define    RTL8367C_PKTGEN_PORT10_TIMER_RX_DMA_ERR_FLAG_OFFSET    3\n#define    RTL8367C_PKTGEN_PORT10_TIMER_RX_DMA_ERR_FLAG_MASK    0x8\n\n#define    RTL8367C_REG_PORT10_MISC_CFG    0x014e\n#define    RTL8367C_PORT10_MISC_CFG_SMALL_TAG_IPG_OFFSET    15\n#define    RTL8367C_PORT10_MISC_CFG_SMALL_TAG_IPG_MASK    0x8000\n#define    RTL8367C_PORT10_MISC_CFG_TX_ITFSP_MODE_OFFSET    14\n#define    RTL8367C_PORT10_MISC_CFG_TX_ITFSP_MODE_MASK    0x4000\n#define    RTL8367C_PORT10_MISC_CFG_FLOWCTRL_INDEP_OFFSET    13\n#define    RTL8367C_PORT10_MISC_CFG_FLOWCTRL_INDEP_MASK    0x2000\n#define    RTL8367C_PORT10_MISC_CFG_DOT1Q_REMARK_ENABLE_OFFSET    12\n#define    RTL8367C_PORT10_MISC_CFG_DOT1Q_REMARK_ENABLE_MASK    0x1000\n#define    RTL8367C_PORT10_MISC_CFG_INGRESSBW_FLOWCTRL_OFFSET    11\n#define    RTL8367C_PORT10_MISC_CFG_INGRESSBW_FLOWCTRL_MASK    0x800\n#define    RTL8367C_PORT10_MISC_CFG_INGRESSBW_IFG_OFFSET    10\n#define    RTL8367C_PORT10_MISC_CFG_INGRESSBW_IFG_MASK    0x400\n#define    RTL8367C_PORT10_MISC_CFG_RX_SPC_OFFSET    9\n#define    RTL8367C_PORT10_MISC_CFG_RX_SPC_MASK    0x200\n#define    RTL8367C_PORT10_MISC_CFG_CRC_SKIP_OFFSET    8\n#define    RTL8367C_PORT10_MISC_CFG_CRC_SKIP_MASK    0x100\n#define    RTL8367C_PORT10_MISC_CFG_PKTGEN_TX_FIRST_OFFSET    7\n#define    RTL8367C_PORT10_MISC_CFG_PKTGEN_TX_FIRST_MASK    0x80\n#define    RTL8367C_PORT10_MISC_CFG_MAC_LOOPBACK_OFFSET    6\n#define    RTL8367C_PORT10_MISC_CFG_MAC_LOOPBACK_MASK    0x40\n#define    RTL8367C_PORT10_MISC_CFG_VLAN_EGRESS_MODE_OFFSET    4\n#define    RTL8367C_PORT10_MISC_CFG_VLAN_EGRESS_MODE_MASK    0x30\n#define    RTL8367C_PORT10_MISC_CFG_CONGESTION_SUSTAIN_TIME_OFFSET    0\n#define    RTL8367C_PORT10_MISC_CFG_CONGESTION_SUSTAIN_TIME_MASK    0xF\n\n#define    RTL8367C_REG_INGRESSBW_PORT10_RATE_CTRL0    0x014f\n\n#define    RTL8367C_REG_INGRESSBW_PORT10_RATE_CTRL1    0x0150\n#define    RTL8367C_INGRESSBW_PORT10_RATE_CTRL1_DUMMY_OFFSET    3\n#define    RTL8367C_INGRESSBW_PORT10_RATE_CTRL1_DUMMY_MASK    0xFFF8\n#define    RTL8367C_INGRESSBW_PORT10_RATE_CTRL1_INGRESSBW_RATE16_OFFSET    0\n#define    RTL8367C_INGRESSBW_PORT10_RATE_CTRL1_INGRESSBW_RATE16_MASK    0x7\n\n#define    RTL8367C_REG_PORT10_FORCE_RATE0    0x0151\n\n#define    RTL8367C_REG_PORT10_FORCE_RATE1    0x0152\n\n#define    RTL8367C_REG_PORT10_CURENT_RATE0    0x0153\n\n#define    RTL8367C_REG_PORT10_CURENT_RATE1    0x0154\n\n#define    RTL8367C_REG_PORT10_PAGE_COUNTER    0x0155\n#define    RTL8367C_PORT10_PAGE_COUNTER_OFFSET    0\n#define    RTL8367C_PORT10_PAGE_COUNTER_MASK    0x7F\n\n#define    RTL8367C_REG_PAGEMETER_PORT10_CTRL0    0x0156\n\n#define    RTL8367C_REG_PAGEMETER_PORT10_CTRL1    0x0157\n\n#define    RTL8367C_REG_PORT10_EEECFG    0x0158\n#define    RTL8367C_PORT10_EEECFG_EEEP_ENABLE_TX_OFFSET    14\n#define    RTL8367C_PORT10_EEECFG_EEEP_ENABLE_TX_MASK    0x4000\n#define    RTL8367C_PORT10_EEECFG_EEEP_ENABLE_RX_OFFSET    13\n#define    RTL8367C_PORT10_EEECFG_EEEP_ENABLE_RX_MASK    0x2000\n#define    RTL8367C_PORT10_EEECFG_EEE_FORCE_OFFSET    12\n#define    RTL8367C_PORT10_EEECFG_EEE_FORCE_MASK    0x1000\n#define    RTL8367C_PORT10_EEECFG_EEE_100M_OFFSET    11\n#define    RTL8367C_PORT10_EEECFG_EEE_100M_MASK    0x800\n#define    RTL8367C_PORT10_EEECFG_EEE_GIGA_500M_OFFSET    10\n#define    RTL8367C_PORT10_EEECFG_EEE_GIGA_500M_MASK    0x400\n#define    RTL8367C_PORT10_EEECFG_EEE_TX_OFFSET    9\n#define    RTL8367C_PORT10_EEECFG_EEE_TX_MASK    0x200\n#define    RTL8367C_PORT10_EEECFG_EEE_RX_OFFSET    8\n#define    RTL8367C_PORT10_EEECFG_EEE_RX_MASK    0x100\n#define    RTL8367C_PORT10_EEECFG_EEE_DSP_RX_OFFSET    6\n#define    RTL8367C_PORT10_EEECFG_EEE_DSP_RX_MASK    0x40\n#define    RTL8367C_PORT10_EEECFG_EEE_LPI_OFFSET    5\n#define    RTL8367C_PORT10_EEECFG_EEE_LPI_MASK    0x20\n#define    RTL8367C_PORT10_EEECFG_EEE_TX_LPI_OFFSET    4\n#define    RTL8367C_PORT10_EEECFG_EEE_TX_LPI_MASK    0x10\n#define    RTL8367C_PORT10_EEECFG_EEE_RX_LPI_OFFSET    3\n#define    RTL8367C_PORT10_EEECFG_EEE_RX_LPI_MASK    0x8\n#define    RTL8367C_PORT10_EEECFG_EEE_PAUSE_INDICATOR_OFFSET    2\n#define    RTL8367C_PORT10_EEECFG_EEE_PAUSE_INDICATOR_MASK    0x4\n#define    RTL8367C_PORT10_EEECFG_EEE_WAKE_REQ_OFFSET    1\n#define    RTL8367C_PORT10_EEECFG_EEE_WAKE_REQ_MASK    0x2\n#define    RTL8367C_PORT10_EEECFG_EEE_SLEEP_REQ_OFFSET    0\n#define    RTL8367C_PORT10_EEECFG_EEE_SLEEP_REQ_MASK    0x1\n\n#define    RTL8367C_REG_PORT10_EEETXMTR    0x0159\n\n#define    RTL8367C_REG_PORT10_EEERXMTR    0x015a\n\n#define    RTL8367C_REG_PORT10_EEEPTXMTR    0x015b\n\n#define    RTL8367C_REG_PORT10_EEEPRXMTR    0x015c\n\n#define    RTL8367C_REG_PTP_PORT10_CFG1    0x015e\n#define    RTL8367C_PTP_PORT10_CFG1_OFFSET    7\n#define    RTL8367C_PTP_PORT10_CFG1_MASK    0xFF\n\n#define    RTL8367C_REG_P10_MSIC1    0x015f\n#define    RTL8367C_P10_MSIC1_OFFSET    0\n#define    RTL8367C_P10_MSIC1_MASK    0x1\n\n/* (16'h0200)outq_reg */\n\n#define    RTL8367C_REG_FLOWCTRL_QUEUE0_DROP_ON    0x0200\n#define    RTL8367C_FLOWCTRL_QUEUE0_DROP_ON_OFFSET    0\n#define    RTL8367C_FLOWCTRL_QUEUE0_DROP_ON_MASK    0x7FF\n\n#define    RTL8367C_REG_FLOWCTRL_QUEUE1_DROP_ON    0x0201\n#define    RTL8367C_FLOWCTRL_QUEUE1_DROP_ON_OFFSET    0\n#define    RTL8367C_FLOWCTRL_QUEUE1_DROP_ON_MASK    0x7FF\n\n#define    RTL8367C_REG_FLOWCTRL_QUEUE2_DROP_ON    0x0202\n#define    RTL8367C_FLOWCTRL_QUEUE2_DROP_ON_OFFSET    0\n#define    RTL8367C_FLOWCTRL_QUEUE2_DROP_ON_MASK    0x7FF\n\n#define    RTL8367C_REG_FLOWCTRL_QUEUE3_DROP_ON    0x0203\n#define    RTL8367C_FLOWCTRL_QUEUE3_DROP_ON_OFFSET    0\n#define    RTL8367C_FLOWCTRL_QUEUE3_DROP_ON_MASK    0x7FF\n\n#define    RTL8367C_REG_FLOWCTRL_QUEUE4_DROP_ON    0x0204\n#define    RTL8367C_FLOWCTRL_QUEUE4_DROP_ON_OFFSET    0\n#define    RTL8367C_FLOWCTRL_QUEUE4_DROP_ON_MASK    0x7FF\n\n#define    RTL8367C_REG_FLOWCTRL_QUEUE5_DROP_ON    0x0205\n#define    RTL8367C_FLOWCTRL_QUEUE5_DROP_ON_OFFSET    0\n#define    RTL8367C_FLOWCTRL_QUEUE5_DROP_ON_MASK    0x7FF\n\n#define    RTL8367C_REG_FLOWCTRL_QUEUE6_DROP_ON    0x0206\n#define    RTL8367C_FLOWCTRL_QUEUE6_DROP_ON_OFFSET    0\n#define    RTL8367C_FLOWCTRL_QUEUE6_DROP_ON_MASK    0x7FF\n\n#define    RTL8367C_REG_FLOWCTRL_QUEUE7_DROP_ON    0x0207\n#define    RTL8367C_FLOWCTRL_QUEUE7_DROP_ON_OFFSET    0\n#define    RTL8367C_FLOWCTRL_QUEUE7_DROP_ON_MASK    0x7FF\n\n#define    RTL8367C_REG_FLOWCTRL_PORT0_DROP_ON    0x0208\n#define    RTL8367C_FLOWCTRL_PORT0_DROP_ON_OFFSET    0\n#define    RTL8367C_FLOWCTRL_PORT0_DROP_ON_MASK    0x7FF\n\n#define    RTL8367C_REG_FLOWCTRL_PORT1_DROP_ON    0x0209\n#define    RTL8367C_FLOWCTRL_PORT1_DROP_ON_OFFSET    0\n#define    RTL8367C_FLOWCTRL_PORT1_DROP_ON_MASK    0x7FF\n\n#define    RTL8367C_REG_FLOWCTRL_PORT2_DROP_ON    0x020a\n#define    RTL8367C_FLOWCTRL_PORT2_DROP_ON_OFFSET    0\n#define    RTL8367C_FLOWCTRL_PORT2_DROP_ON_MASK    0x7FF\n\n#define    RTL8367C_REG_FLOWCTRL_PORT3_DROP_ON    0x020b\n#define    RTL8367C_FLOWCTRL_PORT3_DROP_ON_OFFSET    0\n#define    RTL8367C_FLOWCTRL_PORT3_DROP_ON_MASK    0x7FF\n\n#define    RTL8367C_REG_FLOWCTRL_PORT4_DROP_ON    0x020c\n#define    RTL8367C_FLOWCTRL_PORT4_DROP_ON_OFFSET    0\n#define    RTL8367C_FLOWCTRL_PORT4_DROP_ON_MASK    0x7FF\n\n#define    RTL8367C_REG_FLOWCTRL_PORT5_DROP_ON    0x020d\n#define    RTL8367C_FLOWCTRL_PORT5_DROP_ON_OFFSET    0\n#define    RTL8367C_FLOWCTRL_PORT5_DROP_ON_MASK    0x7FF\n\n#define    RTL8367C_REG_FLOWCTRL_PORT6_DROP_ON    0x020e\n#define    RTL8367C_FLOWCTRL_PORT6_DROP_ON_OFFSET    0\n#define    RTL8367C_FLOWCTRL_PORT6_DROP_ON_MASK    0x7FF\n\n#define    RTL8367C_REG_FLOWCTRL_PORT7_DROP_ON    0x020f\n#define    RTL8367C_FLOWCTRL_PORT7_DROP_ON_OFFSET    0\n#define    RTL8367C_FLOWCTRL_PORT7_DROP_ON_MASK    0x7FF\n\n#define    RTL8367C_REG_FLOWCTRL_PORT8_DROP_ON    0x0210\n#define    RTL8367C_FLOWCTRL_PORT8_DROP_ON_OFFSET    0\n#define    RTL8367C_FLOWCTRL_PORT8_DROP_ON_MASK    0x7FF\n\n#define    RTL8367C_REG_FLOWCTRL_PORT9_DROP_ON    0x0211\n#define    RTL8367C_FLOWCTRL_PORT9_DROP_ON_OFFSET    0\n#define    RTL8367C_FLOWCTRL_PORT9_DROP_ON_MASK    0x7FF\n\n#define    RTL8367C_REG_FLOWCTRL_PORT10_DROP_ON    0x0212\n#define    RTL8367C_FLOWCTRL_PORT10_DROP_ON_OFFSET    0\n#define    RTL8367C_FLOWCTRL_PORT10_DROP_ON_MASK    0x7FF\n\n#define    RTL8367C_REG_FLOWCTRL_PORT_GAP    0x0218\n#define    RTL8367C_FLOWCTRL_PORT_GAP_OFFSET    0\n#define    RTL8367C_FLOWCTRL_PORT_GAP_MASK    0x7FF\n\n#define    RTL8367C_REG_FLOWCTRL_QUEUE_GAP    0x0219\n#define    RTL8367C_FLOWCTRL_QUEUE_GAP_OFFSET    0\n#define    RTL8367C_FLOWCTRL_QUEUE_GAP_MASK    0x7FF\n\n#define    RTL8367C_REG_PORT_QEMPTY    0x022d\n#define    RTL8367C_PORT_QEMPTY_OFFSET    0\n#define    RTL8367C_PORT_QEMPTY_MASK    0x7FF\n\n#define    RTL8367C_REG_FLOWCTRL_DEBUG_CTRL0    0x022e\n#define    RTL8367C_FLOWCTRL_DEBUG_CTRL0_OFFSET    0\n#define    RTL8367C_FLOWCTRL_DEBUG_CTRL0_MASK    0xF\n\n#define    RTL8367C_REG_FLOWCTRL_DEBUG_CTRL1    0x022f\n#define    RTL8367C_TOTAL_OFFSET    9\n#define    RTL8367C_TOTAL_MASK    0x200\n#define    RTL8367C_PORT_MAX_OFFSET    8\n#define    RTL8367C_PORT_MAX_MASK    0x100\n#define    RTL8367C_QMAX_MASK_OFFSET    0\n#define    RTL8367C_QMAX_MASK_MASK    0xFF\n\n#define    RTL8367C_REG_FLOWCTRL_QUEUE0_PAGE_COUNT    0x0230\n#define    RTL8367C_FLOWCTRL_QUEUE0_PAGE_COUNT_OFFSET    0\n#define    RTL8367C_FLOWCTRL_QUEUE0_PAGE_COUNT_MASK    0x7FF\n\n#define    RTL8367C_REG_FLOWCTRL_QUEUE1_PAGE_COUNT    0x0231\n#define    RTL8367C_FLOWCTRL_QUEUE1_PAGE_COUNT_OFFSET    0\n#define    RTL8367C_FLOWCTRL_QUEUE1_PAGE_COUNT_MASK    0x7FF\n\n#define    RTL8367C_REG_FLOWCTRL_QUEUE2_PAGE_COUNT    0x0232\n#define    RTL8367C_FLOWCTRL_QUEUE2_PAGE_COUNT_OFFSET    0\n#define    RTL8367C_FLOWCTRL_QUEUE2_PAGE_COUNT_MASK    0x7FF\n\n#define    RTL8367C_REG_FLOWCTRL_QUEUE3_PAGE_COUNT    0x0233\n#define    RTL8367C_FLOWCTRL_QUEUE3_PAGE_COUNT_OFFSET    0\n#define    RTL8367C_FLOWCTRL_QUEUE3_PAGE_COUNT_MASK    0x7FF\n\n#define    RTL8367C_REG_FLOWCTRL_QUEUE4_PAGE_COUNT    0x0234\n#define    RTL8367C_FLOWCTRL_QUEUE4_PAGE_COUNT_OFFSET    0\n#define    RTL8367C_FLOWCTRL_QUEUE4_PAGE_COUNT_MASK    0x7FF\n\n#define    RTL8367C_REG_FLOWCTRL_QUEUE5_PAGE_COUNT    0x0235\n#define    RTL8367C_FLOWCTRL_QUEUE5_PAGE_COUNT_OFFSET    0\n#define    RTL8367C_FLOWCTRL_QUEUE5_PAGE_COUNT_MASK    0x7FF\n\n#define    RTL8367C_REG_FLOWCTRL_QUEUE6_PAGE_COUNT    0x0236\n#define    RTL8367C_FLOWCTRL_QUEUE6_PAGE_COUNT_OFFSET    0\n#define    RTL8367C_FLOWCTRL_QUEUE6_PAGE_COUNT_MASK    0x7FF\n\n#define    RTL8367C_REG_FLOWCTRL_QUEUE7_PAGE_COUNT    0x0237\n#define    RTL8367C_FLOWCTRL_QUEUE7_PAGE_COUNT_OFFSET    0\n#define    RTL8367C_FLOWCTRL_QUEUE7_PAGE_COUNT_MASK    0x7FF\n\n#define    RTL8367C_REG_FLOWCTRL_PORT_PAGE_COUNT    0x0238\n#define    RTL8367C_FLOWCTRL_PORT_PAGE_COUNT_OFFSET    0\n#define    RTL8367C_FLOWCTRL_PORT_PAGE_COUNT_MASK    0x7FF\n\n#define    RTL8367C_REG_FLOWCTRL_QUEUE0_MAX_PAGE_COUNT    0x0239\n#define    RTL8367C_FLOWCTRL_QUEUE0_MAX_PAGE_COUNT_OFFSET    0\n#define    RTL8367C_FLOWCTRL_QUEUE0_MAX_PAGE_COUNT_MASK    0x7FF\n\n#define    RTL8367C_REG_FLOWCTRL_QUEUE1_MAX_PAGE_COUNT    0x023a\n#define    RTL8367C_FLOWCTRL_QUEUE1_MAX_PAGE_COUNT_OFFSET    0\n#define    RTL8367C_FLOWCTRL_QUEUE1_MAX_PAGE_COUNT_MASK    0x7FF\n\n#define    RTL8367C_REG_FLOWCTRL_QUEUE2_MAX_PAGE_COUNT    0x023b\n#define    RTL8367C_FLOWCTRL_QUEUE2_MAX_PAGE_COUNT_OFFSET    0\n#define    RTL8367C_FLOWCTRL_QUEUE2_MAX_PAGE_COUNT_MASK    0x7FF\n\n#define    RTL8367C_REG_FLOWCTRL_QUEUE3_MAX_PAGE_COUNT    0x023c\n#define    RTL8367C_FLOWCTRL_QUEUE3_MAX_PAGE_COUNT_OFFSET    0\n#define    RTL8367C_FLOWCTRL_QUEUE3_MAX_PAGE_COUNT_MASK    0x7FF\n\n#define    RTL8367C_REG_FLOWCTRL_QUEUE4_MAX_PAGE_COUNT    0x023d\n#define    RTL8367C_FLOWCTRL_QUEUE4_MAX_PAGE_COUNT_OFFSET    0\n#define    RTL8367C_FLOWCTRL_QUEUE4_MAX_PAGE_COUNT_MASK    0x7FF\n\n#define    RTL8367C_REG_FLOWCTRL_QUEUE5_MAX_PAGE_COUNT    0x023e\n#define    RTL8367C_FLOWCTRL_QUEUE5_MAX_PAGE_COUNT_OFFSET    0\n#define    RTL8367C_FLOWCTRL_QUEUE5_MAX_PAGE_COUNT_MASK    0x7FF\n\n#define    RTL8367C_REG_FLOWCTRL_QUEUE6_MAX_PAGE_COUNT    0x023f\n#define    RTL8367C_FLOWCTRL_QUEUE6_MAX_PAGE_COUNT_OFFSET    0\n#define    RTL8367C_FLOWCTRL_QUEUE6_MAX_PAGE_COUNT_MASK    0x7FF\n\n#define    RTL8367C_REG_FLOWCTRL_QUEUE7_MAX_PAGE_COUNT    0x0240\n#define    RTL8367C_FLOWCTRL_QUEUE7_MAX_PAGE_COUNT_OFFSET    0\n#define    RTL8367C_FLOWCTRL_QUEUE7_MAX_PAGE_COUNT_MASK    0x7FF\n\n#define    RTL8367C_REG_FLOWCTRL_PORT_MAX_PAGE_COUNT    0x0241\n#define    RTL8367C_FLOWCTRL_PORT_MAX_PAGE_COUNT_OFFSET    0\n#define    RTL8367C_FLOWCTRL_PORT_MAX_PAGE_COUNT_MASK    0x7FF\n\n#define    RTL8367C_REG_FLOWCTRL_TOTAL_PACKET_COUNT    0x0243\n\n#define    RTL8367C_REG_HIGH_QUEUE_MASK0    0x0244\n#define    RTL8367C_PORT1_HIGH_QUEUE_MASK_OFFSET    8\n#define    RTL8367C_PORT1_HIGH_QUEUE_MASK_MASK    0xFF00\n#define    RTL8367C_PORT0_HIGH_QUEUE_MASK_OFFSET    0\n#define    RTL8367C_PORT0_HIGH_QUEUE_MASK_MASK    0xFF\n\n#define    RTL8367C_REG_HIGH_QUEUE_MASK1    0x0245\n#define    RTL8367C_PORT3_HIGH_QUEUE_MASK_OFFSET    8\n#define    RTL8367C_PORT3_HIGH_QUEUE_MASK_MASK    0xFF00\n#define    RTL8367C_PORT2_HIGH_QUEUE_MASK_OFFSET    0\n#define    RTL8367C_PORT2_HIGH_QUEUE_MASK_MASK    0xFF\n\n#define    RTL8367C_REG_HIGH_QUEUE_MASK2    0x0246\n#define    RTL8367C_PORT5_HIGH_QUEUE_MASK_OFFSET    8\n#define    RTL8367C_PORT5_HIGH_QUEUE_MASK_MASK    0xFF00\n#define    RTL8367C_PORT4_HIGH_QUEUE_MASK_OFFSET    0\n#define    RTL8367C_PORT4_HIGH_QUEUE_MASK_MASK    0xFF\n\n#define    RTL8367C_REG_HIGH_QUEUE_MASK3    0x0247\n#define    RTL8367C_PORT7_HIGH_QUEUE_MASK_OFFSET    8\n#define    RTL8367C_PORT7_HIGH_QUEUE_MASK_MASK    0xFF00\n#define    RTL8367C_PORT6_HIGH_QUEUE_MASK_OFFSET    0\n#define    RTL8367C_PORT6_HIGH_QUEUE_MASK_MASK    0xFF\n\n#define    RTL8367C_REG_HIGH_QUEUE_MASK4    0x0248\n#define    RTL8367C_PORT9_HIGH_QUEUE_MASK_OFFSET    8\n#define    RTL8367C_PORT9_HIGH_QUEUE_MASK_MASK    0xFF00\n#define    RTL8367C_PORT8_HIGH_QUEUE_MASK_OFFSET    0\n#define    RTL8367C_PORT8_HIGH_QUEUE_MASK_MASK    0xFF\n\n#define    RTL8367C_REG_HIGH_QUEUE_MASK5    0x0249\n#define    RTL8367C_HIGH_QUEUE_MASK5_OFFSET    0\n#define    RTL8367C_HIGH_QUEUE_MASK5_MASK    0xFF\n\n#define    RTL8367C_REG_LOW_QUEUE_TH    0x024c\n#define    RTL8367C_LOW_QUEUE_TH_OFFSET    0\n#define    RTL8367C_LOW_QUEUE_TH_MASK    0x7FF\n\n#define    RTL8367C_REG_TH_TX_PREFET    0x0250\n#define    RTL8367C_TH_TX_PREFET_OFFSET    0\n#define    RTL8367C_TH_TX_PREFET_MASK    0xFF\n\n#define    RTL8367C_REG_DUMMY_0251    0x0251\n\n#define    RTL8367C_REG_DUMMY_0252    0x0252\n\n#define    RTL8367C_REG_DUMMY_0253    0x0253\n\n#define    RTL8367C_REG_DUMMY_0254    0x0254\n\n#define    RTL8367C_REG_DUMMY_0255    0x0255\n\n#define    RTL8367C_REG_DUMMY_0256    0x0256\n\n#define    RTL8367C_REG_DUMMY_0257    0x0257\n\n#define    RTL8367C_REG_DUMMY_0258    0x0258\n\n#define    RTL8367C_REG_DUMMY_0259    0x0259\n\n#define    RTL8367C_REG_DUMMY_025A    0x025A\n\n#define    RTL8367C_REG_DUMMY_025B    0x025B\n\n#define    RTL8367C_REG_DUMMY_025C    0x025C\n\n#define    RTL8367C_REG_Q_TXPKT_CNT_CTL    0x025d\n#define    RTL8367C_QUEUE_PKT_CNT_CLR_OFFSET    4\n#define    RTL8367C_QUEUE_PKT_CNT_CLR_MASK    0x10\n#define    RTL8367C_PORT_ID_QUEUE_PKT_CNT_OFFSET    0\n#define    RTL8367C_PORT_ID_QUEUE_PKT_CNT_MASK    0xF\n\n#define    RTL8367C_REG_Q0_TXPKT_CNT_L    0x025e\n\n#define    RTL8367C_REG_Q0_TXPKT_CNT_H    0x025f\n\n#define    RTL8367C_REG_Q1_TXPKT_CNT_L    0x0260\n\n#define    RTL8367C_REG_Q1_TXPKT_CNT_H    0x0261\n\n#define    RTL8367C_REG_Q2_TXPKT_CNT_L    0x0262\n\n#define    RTL8367C_REG_Q2_TXPKT_CNT_H    0x0263\n\n#define    RTL8367C_REG_Q3_TXPKT_CNT_L    0x0264\n\n#define    RTL8367C_REG_Q3_TXPKT_CNT_H    0x0265\n\n#define    RTL8367C_REG_Q4_TXPKT_CNT_L    0x0266\n\n#define    RTL8367C_REG_Q4_TXPKT_CNT_H    0x0267\n\n#define    RTL8367C_REG_Q5_TXPKT_CNT_L    0x0268\n\n#define    RTL8367C_REG_Q5_TXPKT_CNT_H    0x0269\n\n#define    RTL8367C_REG_Q6_TXPKT_CNT_L    0x026a\n\n#define    RTL8367C_REG_Q6_TXPKT_CNT_H    0x026b\n\n#define    RTL8367C_REG_Q7_TXPKT_CNT_L    0x026c\n\n#define    RTL8367C_REG_Q7_TXPKT_CNT_H    0x026d\n\n/* (16'h0300)sch_reg */\n\n#define    RTL8367C_REG_SCHEDULE_WFQ_CTRL    0x0300\n#define    RTL8367C_SCHEDULE_WFQ_CTRL_OFFSET    0\n#define    RTL8367C_SCHEDULE_WFQ_CTRL_MASK    0x1\n\n#define    RTL8367C_REG_SCHEDULE_WFQ_BURST_SIZE    0x0301\n\n#define    RTL8367C_REG_SCHEDULE_QUEUE_TYPE_CTRL0    0x0302\n#define    RTL8367C_PORT1_QUEUE7_TYPE_OFFSET    15\n#define    RTL8367C_PORT1_QUEUE7_TYPE_MASK    0x8000\n#define    RTL8367C_PORT1_QUEUE6_TYPE_OFFSET    14\n#define    RTL8367C_PORT1_QUEUE6_TYPE_MASK    0x4000\n#define    RTL8367C_PORT1_QUEUE5_TYPE_OFFSET    13\n#define    RTL8367C_PORT1_QUEUE5_TYPE_MASK    0x2000\n#define    RTL8367C_PORT1_QUEUE4_TYPE_OFFSET    12\n#define    RTL8367C_PORT1_QUEUE4_TYPE_MASK    0x1000\n#define    RTL8367C_PORT1_QUEUE3_TYPE_OFFSET    11\n#define    RTL8367C_PORT1_QUEUE3_TYPE_MASK    0x800\n#define    RTL8367C_PORT1_QUEUE2_TYPE_OFFSET    10\n#define    RTL8367C_PORT1_QUEUE2_TYPE_MASK    0x400\n#define    RTL8367C_PORT1_QUEUE1_TYPE_OFFSET    9\n#define    RTL8367C_PORT1_QUEUE1_TYPE_MASK    0x200\n#define    RTL8367C_PORT1_QUEUE0_TYPE_OFFSET    8\n#define    RTL8367C_PORT1_QUEUE0_TYPE_MASK    0x100\n#define    RTL8367C_PORT0_QUEUE7_TYPE_OFFSET    7\n#define    RTL8367C_PORT0_QUEUE7_TYPE_MASK    0x80\n#define    RTL8367C_PORT0_QUEUE6_TYPE_OFFSET    6\n#define    RTL8367C_PORT0_QUEUE6_TYPE_MASK    0x40\n#define    RTL8367C_PORT0_QUEUE5_TYPE_OFFSET    5\n#define    RTL8367C_PORT0_QUEUE5_TYPE_MASK    0x20\n#define    RTL8367C_PORT0_QUEUE4_TYPE_OFFSET    4\n#define    RTL8367C_PORT0_QUEUE4_TYPE_MASK    0x10\n#define    RTL8367C_PORT0_QUEUE3_TYPE_OFFSET    3\n#define    RTL8367C_PORT0_QUEUE3_TYPE_MASK    0x8\n#define    RTL8367C_PORT0_QUEUE2_TYPE_OFFSET    2\n#define    RTL8367C_PORT0_QUEUE2_TYPE_MASK    0x4\n#define    RTL8367C_PORT0_QUEUE1_TYPE_OFFSET    1\n#define    RTL8367C_PORT0_QUEUE1_TYPE_MASK    0x2\n#define    RTL8367C_PORT0_QUEUE0_TYPE_OFFSET    0\n#define    RTL8367C_PORT0_QUEUE0_TYPE_MASK    0x1\n\n#define    RTL8367C_REG_SCHEDULE_QUEUE_TYPE_CTRL1    0x0303\n#define    RTL8367C_PORT3_QUEUE7_TYPE_OFFSET    15\n#define    RTL8367C_PORT3_QUEUE7_TYPE_MASK    0x8000\n#define    RTL8367C_PORT3_QUEUE6_TYPE_OFFSET    14\n#define    RTL8367C_PORT3_QUEUE6_TYPE_MASK    0x4000\n#define    RTL8367C_PORT3_QUEUE5_TYPE_OFFSET    13\n#define    RTL8367C_PORT3_QUEUE5_TYPE_MASK    0x2000\n#define    RTL8367C_PORT3_QUEUE4_TYPE_OFFSET    12\n#define    RTL8367C_PORT3_QUEUE4_TYPE_MASK    0x1000\n#define    RTL8367C_PORT3_QUEUE3_TYPE_OFFSET    11\n#define    RTL8367C_PORT3_QUEUE3_TYPE_MASK    0x800\n#define    RTL8367C_PORT3_QUEUE2_TYPE_OFFSET    10\n#define    RTL8367C_PORT3_QUEUE2_TYPE_MASK    0x400\n#define    RTL8367C_PORT3_QUEUE1_TYPE_OFFSET    9\n#define    RTL8367C_PORT3_QUEUE1_TYPE_MASK    0x200\n#define    RTL8367C_PORT3_QUEUE0_TYPE_OFFSET    8\n#define    RTL8367C_PORT3_QUEUE0_TYPE_MASK    0x100\n#define    RTL8367C_PORT2_QUEUE7_TYPE_OFFSET    7\n#define    RTL8367C_PORT2_QUEUE7_TYPE_MASK    0x80\n#define    RTL8367C_PORT2_QUEUE6_TYPE_OFFSET    6\n#define    RTL8367C_PORT2_QUEUE6_TYPE_MASK    0x40\n#define    RTL8367C_PORT2_QUEUE5_TYPE_OFFSET    5\n#define    RTL8367C_PORT2_QUEUE5_TYPE_MASK    0x20\n#define    RTL8367C_PORT2_QUEUE4_TYPE_OFFSET    4\n#define    RTL8367C_PORT2_QUEUE4_TYPE_MASK    0x10\n#define    RTL8367C_PORT2_QUEUE3_TYPE_OFFSET    3\n#define    RTL8367C_PORT2_QUEUE3_TYPE_MASK    0x8\n#define    RTL8367C_PORT2_QUEUE2_TYPE_OFFSET    2\n#define    RTL8367C_PORT2_QUEUE2_TYPE_MASK    0x4\n#define    RTL8367C_PORT2_QUEUE1_TYPE_OFFSET    1\n#define    RTL8367C_PORT2_QUEUE1_TYPE_MASK    0x2\n#define    RTL8367C_PORT2_QUEUE0_TYPE_OFFSET    0\n#define    RTL8367C_PORT2_QUEUE0_TYPE_MASK    0x1\n\n#define    RTL8367C_REG_SCHEDULE_QUEUE_TYPE_CTRL2    0x0304\n#define    RTL8367C_PORT5_QUEUE7_TYPE_OFFSET    15\n#define    RTL8367C_PORT5_QUEUE7_TYPE_MASK    0x8000\n#define    RTL8367C_PORT5_QUEUE6_TYPE_OFFSET    14\n#define    RTL8367C_PORT5_QUEUE6_TYPE_MASK    0x4000\n#define    RTL8367C_PORT5_QUEUE5_TYPE_OFFSET    13\n#define    RTL8367C_PORT5_QUEUE5_TYPE_MASK    0x2000\n#define    RTL8367C_PORT5_QUEUE4_TYPE_OFFSET    12\n#define    RTL8367C_PORT5_QUEUE4_TYPE_MASK    0x1000\n#define    RTL8367C_PORT5_QUEUE3_TYPE_OFFSET    11\n#define    RTL8367C_PORT5_QUEUE3_TYPE_MASK    0x800\n#define    RTL8367C_PORT5_QUEUE2_TYPE_OFFSET    10\n#define    RTL8367C_PORT5_QUEUE2_TYPE_MASK    0x400\n#define    RTL8367C_PORT5_QUEUE1_TYPE_OFFSET    9\n#define    RTL8367C_PORT5_QUEUE1_TYPE_MASK    0x200\n#define    RTL8367C_PORT5_QUEUE0_TYPE_OFFSET    8\n#define    RTL8367C_PORT5_QUEUE0_TYPE_MASK    0x100\n#define    RTL8367C_PORT4_QUEUE7_TYPE_OFFSET    7\n#define    RTL8367C_PORT4_QUEUE7_TYPE_MASK    0x80\n#define    RTL8367C_PORT4_QUEUE6_TYPE_OFFSET    6\n#define    RTL8367C_PORT4_QUEUE6_TYPE_MASK    0x40\n#define    RTL8367C_PORT4_QUEUE5_TYPE_OFFSET    5\n#define    RTL8367C_PORT4_QUEUE5_TYPE_MASK    0x20\n#define    RTL8367C_PORT4_QUEUE4_TYPE_OFFSET    4\n#define    RTL8367C_PORT4_QUEUE4_TYPE_MASK    0x10\n#define    RTL8367C_PORT4_QUEUE3_TYPE_OFFSET    3\n#define    RTL8367C_PORT4_QUEUE3_TYPE_MASK    0x8\n#define    RTL8367C_PORT4_QUEUE2_TYPE_OFFSET    2\n#define    RTL8367C_PORT4_QUEUE2_TYPE_MASK    0x4\n#define    RTL8367C_PORT4_QUEUE1_TYPE_OFFSET    1\n#define    RTL8367C_PORT4_QUEUE1_TYPE_MASK    0x2\n#define    RTL8367C_PORT4_QUEUE0_TYPE_OFFSET    0\n#define    RTL8367C_PORT4_QUEUE0_TYPE_MASK    0x1\n\n#define    RTL8367C_REG_SCHEDULE_QUEUE_TYPE_CTRL3    0x0305\n#define    RTL8367C_PORT7_QUEUE7_TYPE_OFFSET    15\n#define    RTL8367C_PORT7_QUEUE7_TYPE_MASK    0x8000\n#define    RTL8367C_PORT7_QUEUE6_TYPE_OFFSET    14\n#define    RTL8367C_PORT7_QUEUE6_TYPE_MASK    0x4000\n#define    RTL8367C_PORT7_QUEUE5_TYPE_OFFSET    13\n#define    RTL8367C_PORT7_QUEUE5_TYPE_MASK    0x2000\n#define    RTL8367C_PORT7_QUEUE4_TYPE_OFFSET    12\n#define    RTL8367C_PORT7_QUEUE4_TYPE_MASK    0x1000\n#define    RTL8367C_PORT7_QUEUE3_TYPE_OFFSET    11\n#define    RTL8367C_PORT7_QUEUE3_TYPE_MASK    0x800\n#define    RTL8367C_PORT7_QUEUE2_TYPE_OFFSET    10\n#define    RTL8367C_PORT7_QUEUE2_TYPE_MASK    0x400\n#define    RTL8367C_PORT7_QUEUE1_TYPE_OFFSET    9\n#define    RTL8367C_PORT7_QUEUE1_TYPE_MASK    0x200\n#define    RTL8367C_PORT7_QUEUE0_TYPE_OFFSET    8\n#define    RTL8367C_PORT7_QUEUE0_TYPE_MASK    0x100\n#define    RTL8367C_PORT6_QUEUE7_TYPE_OFFSET    7\n#define    RTL8367C_PORT6_QUEUE7_TYPE_MASK    0x80\n#define    RTL8367C_PORT6_QUEUE6_TYPE_OFFSET    6\n#define    RTL8367C_PORT6_QUEUE6_TYPE_MASK    0x40\n#define    RTL8367C_PORT6_QUEUE5_TYPE_OFFSET    5\n#define    RTL8367C_PORT6_QUEUE5_TYPE_MASK    0x20\n#define    RTL8367C_PORT6_QUEUE4_TYPE_OFFSET    4\n#define    RTL8367C_PORT6_QUEUE4_TYPE_MASK    0x10\n#define    RTL8367C_PORT6_QUEUE3_TYPE_OFFSET    3\n#define    RTL8367C_PORT6_QUEUE3_TYPE_MASK    0x8\n#define    RTL8367C_PORT6_QUEUE2_TYPE_OFFSET    2\n#define    RTL8367C_PORT6_QUEUE2_TYPE_MASK    0x4\n#define    RTL8367C_PORT6_QUEUE1_TYPE_OFFSET    1\n#define    RTL8367C_PORT6_QUEUE1_TYPE_MASK    0x2\n#define    RTL8367C_SCHEDULE_QUEUE_TYPE_CTRL3_PORT6_QUEUE0_TYPE_OFFSET    0\n#define    RTL8367C_SCHEDULE_QUEUE_TYPE_CTRL3_PORT6_QUEUE0_TYPE_MASK    0x1\n\n#define    RTL8367C_REG_SCHEDULE_QUEUE_TYPE_CTRL4    0x0306\n#define    RTL8367C_PORT9_QUEUE7_TYPE_OFFSET    15\n#define    RTL8367C_PORT9_QUEUE7_TYPE_MASK    0x8000\n#define    RTL8367C_PORT9_QUEUE6_TYPE_OFFSET    14\n#define    RTL8367C_PORT9_QUEUE6_TYPE_MASK    0x4000\n#define    RTL8367C_PORT9_QUEUE5_TYPE_OFFSET    13\n#define    RTL8367C_PORT9_QUEUE5_TYPE_MASK    0x2000\n#define    RTL8367C_PORT9_QUEUE4_TYPE_OFFSET    12\n#define    RTL8367C_PORT9_QUEUE4_TYPE_MASK    0x1000\n#define    RTL8367C_PORT9_QUEUE3_TYPE_OFFSET    11\n#define    RTL8367C_PORT9_QUEUE3_TYPE_MASK    0x800\n#define    RTL8367C_PORT9_QUEUE2_TYPE_OFFSET    10\n#define    RTL8367C_PORT9_QUEUE2_TYPE_MASK    0x400\n#define    RTL8367C_PORT9_QUEUE1_TYPE_OFFSET    9\n#define    RTL8367C_PORT9_QUEUE1_TYPE_MASK    0x200\n#define    RTL8367C_PORT9_QUEUE0_TYPE_OFFSET    8\n#define    RTL8367C_PORT9_QUEUE0_TYPE_MASK    0x100\n#define    RTL8367C_PORT8_QUEUE7_TYPE_OFFSET    7\n#define    RTL8367C_PORT8_QUEUE7_TYPE_MASK    0x80\n#define    RTL8367C_PORT8_QUEUE6_TYPE_OFFSET    6\n#define    RTL8367C_PORT8_QUEUE6_TYPE_MASK    0x40\n#define    RTL8367C_PORT8_QUEUE5_TYPE_OFFSET    5\n#define    RTL8367C_PORT8_QUEUE5_TYPE_MASK    0x20\n#define    RTL8367C_PORT8_QUEUE4_TYPE_OFFSET    4\n#define    RTL8367C_PORT8_QUEUE4_TYPE_MASK    0x10\n#define    RTL8367C_PORT8_QUEUE3_TYPE_OFFSET    3\n#define    RTL8367C_PORT8_QUEUE3_TYPE_MASK    0x8\n#define    RTL8367C_PORT8_QUEUE2_TYPE_OFFSET    2\n#define    RTL8367C_PORT8_QUEUE2_TYPE_MASK    0x4\n#define    RTL8367C_PORT8_QUEUE1_TYPE_OFFSET    1\n#define    RTL8367C_PORT8_QUEUE1_TYPE_MASK    0x2\n#define    RTL8367C_SCHEDULE_QUEUE_TYPE_CTRL4_PORT6_QUEUE0_TYPE_OFFSET    0\n#define    RTL8367C_SCHEDULE_QUEUE_TYPE_CTRL4_PORT6_QUEUE0_TYPE_MASK    0x1\n\n#define    RTL8367C_REG_SCHEDULE_QUEUE_TYPE_CTRL5    0x0307\n#define    RTL8367C_PORT10_QUEUE7_TYPE_OFFSET    7\n#define    RTL8367C_PORT10_QUEUE7_TYPE_MASK    0x80\n#define    RTL8367C_PORT10_QUEUE6_TYPE_OFFSET    6\n#define    RTL8367C_PORT10_QUEUE6_TYPE_MASK    0x40\n#define    RTL8367C_PORT10_QUEUE5_TYPE_OFFSET    5\n#define    RTL8367C_PORT10_QUEUE5_TYPE_MASK    0x20\n#define    RTL8367C_PORT10_QUEUE4_TYPE_OFFSET    4\n#define    RTL8367C_PORT10_QUEUE4_TYPE_MASK    0x10\n#define    RTL8367C_PORT10_QUEUE3_TYPE_OFFSET    3\n#define    RTL8367C_PORT10_QUEUE3_TYPE_MASK    0x8\n#define    RTL8367C_PORT10_QUEUE2_TYPE_OFFSET    2\n#define    RTL8367C_PORT10_QUEUE2_TYPE_MASK    0x4\n#define    RTL8367C_PORT10_QUEUE1_TYPE_OFFSET    1\n#define    RTL8367C_PORT10_QUEUE1_TYPE_MASK    0x2\n#define    RTL8367C_PORT10_QUEUE0_TYPE_OFFSET    0\n#define    RTL8367C_PORT10_QUEUE0_TYPE_MASK    0x1\n\n#define    RTL8367C_REG_SCHEDULE_APR_CTRL0    0x030a\n#define    RTL8367C_PORT10_APR_ENABLE_OFFSET    10\n#define    RTL8367C_PORT10_APR_ENABLE_MASK    0x400\n#define    RTL8367C_PORT9_APR_ENABLE_OFFSET    9\n#define    RTL8367C_PORT9_APR_ENABLE_MASK    0x200\n#define    RTL8367C_PORT8_APR_ENABLE_OFFSET    8\n#define    RTL8367C_PORT8_APR_ENABLE_MASK    0x100\n#define    RTL8367C_PORT7_APR_ENABLE_OFFSET    7\n#define    RTL8367C_PORT7_APR_ENABLE_MASK    0x80\n#define    RTL8367C_PORT6_APR_ENABLE_OFFSET    6\n#define    RTL8367C_PORT6_APR_ENABLE_MASK    0x40\n#define    RTL8367C_PORT5_APR_ENABLE_OFFSET    5\n#define    RTL8367C_PORT5_APR_ENABLE_MASK    0x20\n#define    RTL8367C_PORT4_APR_ENABLE_OFFSET    4\n#define    RTL8367C_PORT4_APR_ENABLE_MASK    0x10\n#define    RTL8367C_PORT3_APR_ENABLE_OFFSET    3\n#define    RTL8367C_PORT3_APR_ENABLE_MASK    0x8\n#define    RTL8367C_PORT2_APR_ENABLE_OFFSET    2\n#define    RTL8367C_PORT2_APR_ENABLE_MASK    0x4\n#define    RTL8367C_PORT1_APR_ENABLE_OFFSET    1\n#define    RTL8367C_PORT1_APR_ENABLE_MASK    0x2\n#define    RTL8367C_PORT0_APR_ENABLE_OFFSET    0\n#define    RTL8367C_PORT0_APR_ENABLE_MASK    0x1\n\n#define    RTL8367C_REG_SCHEDULE_PORT0_QUEUE0_WFQ_WEIGHT    0x030c\n\n#define    RTL8367C_REG_SCHEDULE_PORT0_QUEUE1_WFQ_WEIGHT    0x030d\n#define    RTL8367C_SCHEDULE_PORT0_QUEUE1_WFQ_WEIGHT_OFFSET    0\n#define    RTL8367C_SCHEDULE_PORT0_QUEUE1_WFQ_WEIGHT_MASK    0x7F\n\n#define    RTL8367C_REG_SCHEDULE_PORT0_QUEUE2_WFQ_WEIGHT    0x030e\n#define    RTL8367C_SCHEDULE_PORT0_QUEUE2_WFQ_WEIGHT_OFFSET    0\n#define    RTL8367C_SCHEDULE_PORT0_QUEUE2_WFQ_WEIGHT_MASK    0x7F\n\n#define    RTL8367C_REG_SCHEDULE_PORT0_QUEUE3_WFQ_WEIGHT    0x030f\n#define    RTL8367C_SCHEDULE_PORT0_QUEUE3_WFQ_WEIGHT_OFFSET    0\n#define    RTL8367C_SCHEDULE_PORT0_QUEUE3_WFQ_WEIGHT_MASK    0x7F\n\n#define    RTL8367C_REG_SCHEDULE_PORT0_QUEUE4_WFQ_WEIGHT    0x0310\n#define    RTL8367C_SCHEDULE_PORT0_QUEUE4_WFQ_WEIGHT_OFFSET    0\n#define    RTL8367C_SCHEDULE_PORT0_QUEUE4_WFQ_WEIGHT_MASK    0x7F\n\n#define    RTL8367C_REG_SCHEDULE_PORT0_QUEUE5_WFQ_WEIGHT    0x0311\n#define    RTL8367C_SCHEDULE_PORT0_QUEUE5_WFQ_WEIGHT_OFFSET    0\n#define    RTL8367C_SCHEDULE_PORT0_QUEUE5_WFQ_WEIGHT_MASK    0x7F\n\n#define    RTL8367C_REG_SCHEDULE_PORT0_QUEUE6_WFQ_WEIGHT    0x0312\n#define    RTL8367C_SCHEDULE_PORT0_QUEUE6_WFQ_WEIGHT_OFFSET    0\n#define    RTL8367C_SCHEDULE_PORT0_QUEUE6_WFQ_WEIGHT_MASK    0x7F\n\n#define    RTL8367C_REG_SCHEDULE_PORT0_QUEUE7_WFQ_WEIGHT    0x0313\n#define    RTL8367C_SCHEDULE_PORT0_QUEUE7_WFQ_WEIGHT_OFFSET    0\n#define    RTL8367C_SCHEDULE_PORT0_QUEUE7_WFQ_WEIGHT_MASK    0x7F\n\n#define    RTL8367C_REG_SCHEDULE_PORT1_QUEUE0_WFQ_WEIGHT    0x0314\n\n#define    RTL8367C_REG_SCHEDULE_PORT1_QUEUE1_WFQ_WEIGHT    0x0315\n#define    RTL8367C_SCHEDULE_PORT1_QUEUE1_WFQ_WEIGHT_OFFSET    0\n#define    RTL8367C_SCHEDULE_PORT1_QUEUE1_WFQ_WEIGHT_MASK    0x7F\n\n#define    RTL8367C_REG_SCHEDULE_PORT1_QUEUE2_WFQ_WEIGHT    0x0316\n#define    RTL8367C_SCHEDULE_PORT1_QUEUE2_WFQ_WEIGHT_OFFSET    0\n#define    RTL8367C_SCHEDULE_PORT1_QUEUE2_WFQ_WEIGHT_MASK    0x7F\n\n#define    RTL8367C_REG_SCHEDULE_PORT1_QUEUE3_WFQ_WEIGHT    0x0317\n#define    RTL8367C_SCHEDULE_PORT1_QUEUE3_WFQ_WEIGHT_OFFSET    0\n#define    RTL8367C_SCHEDULE_PORT1_QUEUE3_WFQ_WEIGHT_MASK    0x7F\n\n#define    RTL8367C_REG_SCHEDULE_PORT1_QUEUE4_WFQ_WEIGHT    0x0318\n#define    RTL8367C_SCHEDULE_PORT1_QUEUE4_WFQ_WEIGHT_OFFSET    0\n#define    RTL8367C_SCHEDULE_PORT1_QUEUE4_WFQ_WEIGHT_MASK    0x7F\n\n#define    RTL8367C_REG_SCHEDULE_PORT1_QUEUE5_WFQ_WEIGHT    0x0319\n#define    RTL8367C_SCHEDULE_PORT1_QUEUE5_WFQ_WEIGHT_OFFSET    0\n#define    RTL8367C_SCHEDULE_PORT1_QUEUE5_WFQ_WEIGHT_MASK    0x7F\n\n#define    RTL8367C_REG_SCHEDULE_PORT1_QUEUE6_WFQ_WEIGHT    0x031a\n#define    RTL8367C_SCHEDULE_PORT1_QUEUE6_WFQ_WEIGHT_OFFSET    0\n#define    RTL8367C_SCHEDULE_PORT1_QUEUE6_WFQ_WEIGHT_MASK    0x7F\n\n#define    RTL8367C_REG_SCHEDULE_PORT1_QUEUE7_WFQ_WEIGHT    0x031b\n#define    RTL8367C_SCHEDULE_PORT1_QUEUE7_WFQ_WEIGHT_OFFSET    0\n#define    RTL8367C_SCHEDULE_PORT1_QUEUE7_WFQ_WEIGHT_MASK    0x7F\n\n#define    RTL8367C_REG_SCHEDULE_PORT2_QUEUE0_WFQ_WEIGHT    0x031c\n\n#define    RTL8367C_REG_SCHEDULE_PORT2_QUEUE1_WFQ_WEIGHT    0x031d\n#define    RTL8367C_SCHEDULE_PORT2_QUEUE1_WFQ_WEIGHT_OFFSET    0\n#define    RTL8367C_SCHEDULE_PORT2_QUEUE1_WFQ_WEIGHT_MASK    0x7F\n\n#define    RTL8367C_REG_SCHEDULE_PORT2_QUEUE2_WFQ_WEIGHT    0x031e\n#define    RTL8367C_SCHEDULE_PORT2_QUEUE2_WFQ_WEIGHT_OFFSET    0\n#define    RTL8367C_SCHEDULE_PORT2_QUEUE2_WFQ_WEIGHT_MASK    0x7F\n\n#define    RTL8367C_REG_SCHEDULE_PORT2_QUEUE3_WFQ_WEIGHT    0x031f\n#define    RTL8367C_SCHEDULE_PORT2_QUEUE3_WFQ_WEIGHT_OFFSET    0\n#define    RTL8367C_SCHEDULE_PORT2_QUEUE3_WFQ_WEIGHT_MASK    0x7F\n\n#define    RTL8367C_REG_SCHEDULE_PORT2_QUEUE4_WFQ_WEIGHT    0x0320\n#define    RTL8367C_SCHEDULE_PORT2_QUEUE4_WFQ_WEIGHT_OFFSET    0\n#define    RTL8367C_SCHEDULE_PORT2_QUEUE4_WFQ_WEIGHT_MASK    0x7F\n\n#define    RTL8367C_REG_SCHEDULE_PORT2_QUEUE5_WFQ_WEIGHT    0x0321\n#define    RTL8367C_SCHEDULE_PORT2_QUEUE5_WFQ_WEIGHT_OFFSET    0\n#define    RTL8367C_SCHEDULE_PORT2_QUEUE5_WFQ_WEIGHT_MASK    0x7F\n\n#define    RTL8367C_REG_SCHEDULE_PORT2_QUEUE6_WFQ_WEIGHT    0x0322\n#define    RTL8367C_SCHEDULE_PORT2_QUEUE6_WFQ_WEIGHT_OFFSET    0\n#define    RTL8367C_SCHEDULE_PORT2_QUEUE6_WFQ_WEIGHT_MASK    0x7F\n\n#define    RTL8367C_REG_SCHEDULE_PORT2_QUEUE7_WFQ_WEIGHT    0x0323\n#define    RTL8367C_SCHEDULE_PORT2_QUEUE7_WFQ_WEIGHT_OFFSET    0\n#define    RTL8367C_SCHEDULE_PORT2_QUEUE7_WFQ_WEIGHT_MASK    0x7F\n\n#define    RTL8367C_REG_SCHEDULE_PORT3_QUEUE0_WFQ_WEIGHT    0x0324\n\n#define    RTL8367C_REG_SCHEDULE_PORT3_QUEUE1_WFQ_WEIGHT    0x0325\n#define    RTL8367C_SCHEDULE_PORT3_QUEUE1_WFQ_WEIGHT_OFFSET    0\n#define    RTL8367C_SCHEDULE_PORT3_QUEUE1_WFQ_WEIGHT_MASK    0x7F\n\n#define    RTL8367C_REG_SCHEDULE_PORT3_QUEUE2_WFQ_WEIGHT    0x0326\n#define    RTL8367C_SCHEDULE_PORT3_QUEUE2_WFQ_WEIGHT_OFFSET    0\n#define    RTL8367C_SCHEDULE_PORT3_QUEUE2_WFQ_WEIGHT_MASK    0x7F\n\n#define    RTL8367C_REG_SCHEDULE_PORT3_QUEUE3_WFQ_WEIGHT    0x0327\n#define    RTL8367C_SCHEDULE_PORT3_QUEUE3_WFQ_WEIGHT_OFFSET    0\n#define    RTL8367C_SCHEDULE_PORT3_QUEUE3_WFQ_WEIGHT_MASK    0x7F\n\n#define    RTL8367C_REG_SCHEDULE_PORT3_QUEUE4_WFQ_WEIGHT    0x0328\n#define    RTL8367C_SCHEDULE_PORT3_QUEUE4_WFQ_WEIGHT_OFFSET    0\n#define    RTL8367C_SCHEDULE_PORT3_QUEUE4_WFQ_WEIGHT_MASK    0x7F\n\n#define    RTL8367C_REG_SCHEDULE_PORT3_QUEUE5_WFQ_WEIGHT    0x0329\n#define    RTL8367C_SCHEDULE_PORT3_QUEUE5_WFQ_WEIGHT_OFFSET    0\n#define    RTL8367C_SCHEDULE_PORT3_QUEUE5_WFQ_WEIGHT_MASK    0x7F\n\n#define    RTL8367C_REG_SCHEDULE_PORT3_QUEUE6_WFQ_WEIGHT    0x032a\n#define    RTL8367C_SCHEDULE_PORT3_QUEUE6_WFQ_WEIGHT_OFFSET    0\n#define    RTL8367C_SCHEDULE_PORT3_QUEUE6_WFQ_WEIGHT_MASK    0x7F\n\n#define    RTL8367C_REG_SCHEDULE_PORT3_QUEUE7_WFQ_WEIGHT    0x032b\n#define    RTL8367C_SCHEDULE_PORT3_QUEUE7_WFQ_WEIGHT_OFFSET    0\n#define    RTL8367C_SCHEDULE_PORT3_QUEUE7_WFQ_WEIGHT_MASK    0x7F\n\n#define    RTL8367C_REG_SCHEDULE_PORT4_QUEUE0_WFQ_WEIGHT    0x032c\n\n#define    RTL8367C_REG_SCHEDULE_PORT4_QUEUE1_WFQ_WEIGHT    0x032d\n#define    RTL8367C_SCHEDULE_PORT4_QUEUE1_WFQ_WEIGHT_OFFSET    0\n#define    RTL8367C_SCHEDULE_PORT4_QUEUE1_WFQ_WEIGHT_MASK    0x7F\n\n#define    RTL8367C_REG_SCHEDULE_PORT4_QUEUE2_WFQ_WEIGHT    0x032e\n#define    RTL8367C_SCHEDULE_PORT4_QUEUE2_WFQ_WEIGHT_OFFSET    0\n#define    RTL8367C_SCHEDULE_PORT4_QUEUE2_WFQ_WEIGHT_MASK    0x7F\n\n#define    RTL8367C_REG_SCHEDULE_PORT4_QUEUE3_WFQ_WEIGHT    0x032f\n#define    RTL8367C_SCHEDULE_PORT4_QUEUE3_WFQ_WEIGHT_OFFSET    0\n#define    RTL8367C_SCHEDULE_PORT4_QUEUE3_WFQ_WEIGHT_MASK    0x7F\n\n#define    RTL8367C_REG_SCHEDULE_PORT4_QUEUE4_WFQ_WEIGHT    0x0330\n#define    RTL8367C_SCHEDULE_PORT4_QUEUE4_WFQ_WEIGHT_OFFSET    0\n#define    RTL8367C_SCHEDULE_PORT4_QUEUE4_WFQ_WEIGHT_MASK    0x7F\n\n#define    RTL8367C_REG_SCHEDULE_PORT4_QUEUE5_WFQ_WEIGHT    0x0331\n#define    RTL8367C_SCHEDULE_PORT4_QUEUE5_WFQ_WEIGHT_OFFSET    0\n#define    RTL8367C_SCHEDULE_PORT4_QUEUE5_WFQ_WEIGHT_MASK    0x7F\n\n#define    RTL8367C_REG_SCHEDULE_PORT4_QUEUE6_WFQ_WEIGHT    0x0332\n#define    RTL8367C_SCHEDULE_PORT4_QUEUE6_WFQ_WEIGHT_OFFSET    0\n#define    RTL8367C_SCHEDULE_PORT4_QUEUE6_WFQ_WEIGHT_MASK    0x7F\n\n#define    RTL8367C_REG_SCHEDULE_PORT4_QUEUE7_WFQ_WEIGHT    0x0333\n#define    RTL8367C_SCHEDULE_PORT4_QUEUE7_WFQ_WEIGHT_OFFSET    0\n#define    RTL8367C_SCHEDULE_PORT4_QUEUE7_WFQ_WEIGHT_MASK    0x7F\n\n#define    RTL8367C_REG_SCHEDULE_PORT5_QUEUE0_WFQ_WEIGHT    0x0334\n\n#define    RTL8367C_REG_SCHEDULE_PORT5_QUEUE1_WFQ_WEIGHT    0x0335\n#define    RTL8367C_SCHEDULE_PORT5_QUEUE1_WFQ_WEIGHT_OFFSET    0\n#define    RTL8367C_SCHEDULE_PORT5_QUEUE1_WFQ_WEIGHT_MASK    0x7F\n\n#define    RTL8367C_REG_SCHEDULE_PORT5_QUEUE2_WFQ_WEIGHT    0x0336\n#define    RTL8367C_SCHEDULE_PORT5_QUEUE2_WFQ_WEIGHT_OFFSET    0\n#define    RTL8367C_SCHEDULE_PORT5_QUEUE2_WFQ_WEIGHT_MASK    0x7F\n\n#define    RTL8367C_REG_SCHEDULE_PORT5_QUEUE3_WFQ_WEIGHT    0x0337\n#define    RTL8367C_SCHEDULE_PORT5_QUEUE3_WFQ_WEIGHT_OFFSET    0\n#define    RTL8367C_SCHEDULE_PORT5_QUEUE3_WFQ_WEIGHT_MASK    0x7F\n\n#define    RTL8367C_REG_SCHEDULE_PORT5_QUEUE4_WFQ_WEIGHT    0x0338\n#define    RTL8367C_SCHEDULE_PORT5_QUEUE4_WFQ_WEIGHT_OFFSET    0\n#define    RTL8367C_SCHEDULE_PORT5_QUEUE4_WFQ_WEIGHT_MASK    0x7F\n\n#define    RTL8367C_REG_SCHEDULE_PORT5_QUEUE5_WFQ_WEIGHT    0x0339\n#define    RTL8367C_SCHEDULE_PORT5_QUEUE5_WFQ_WEIGHT_OFFSET    0\n#define    RTL8367C_SCHEDULE_PORT5_QUEUE5_WFQ_WEIGHT_MASK    0x7F\n\n#define    RTL8367C_REG_SCHEDULE_PORT5_QUEUE6_WFQ_WEIGHT    0x033a\n#define    RTL8367C_SCHEDULE_PORT5_QUEUE6_WFQ_WEIGHT_OFFSET    0\n#define    RTL8367C_SCHEDULE_PORT5_QUEUE6_WFQ_WEIGHT_MASK    0x7F\n\n#define    RTL8367C_REG_SCHEDULE_PORT5_QUEUE7_WFQ_WEIGHT    0x033b\n#define    RTL8367C_SCHEDULE_PORT5_QUEUE7_WFQ_WEIGHT_OFFSET    0\n#define    RTL8367C_SCHEDULE_PORT5_QUEUE7_WFQ_WEIGHT_MASK    0x7F\n\n#define    RTL8367C_REG_SCHEDULE_PORT6_QUEUE0_WFQ_WEIGHT    0x033c\n\n#define    RTL8367C_REG_SCHEDULE_PORT6_QUEUE1_WFQ_WEIGHT    0x033d\n#define    RTL8367C_SCHEDULE_PORT6_QUEUE1_WFQ_WEIGHT_OFFSET    0\n#define    RTL8367C_SCHEDULE_PORT6_QUEUE1_WFQ_WEIGHT_MASK    0x7F\n\n#define    RTL8367C_REG_SCHEDULE_PORT6_QUEUE2_WFQ_WEIGHT    0x033e\n#define    RTL8367C_SCHEDULE_PORT6_QUEUE2_WFQ_WEIGHT_OFFSET    0\n#define    RTL8367C_SCHEDULE_PORT6_QUEUE2_WFQ_WEIGHT_MASK    0x7F\n\n#define    RTL8367C_REG_SCHEDULE_PORT6_QUEUE3_WFQ_WEIGHT    0x033f\n#define    RTL8367C_SCHEDULE_PORT6_QUEUE3_WFQ_WEIGHT_OFFSET    0\n#define    RTL8367C_SCHEDULE_PORT6_QUEUE3_WFQ_WEIGHT_MASK    0x7F\n\n#define    RTL8367C_REG_SCHEDULE_PORT6_QUEUE4_WFQ_WEIGHT    0x0340\n#define    RTL8367C_SCHEDULE_PORT6_QUEUE4_WFQ_WEIGHT_OFFSET    0\n#define    RTL8367C_SCHEDULE_PORT6_QUEUE4_WFQ_WEIGHT_MASK    0x7F\n\n#define    RTL8367C_REG_SCHEDULE_PORT6_QUEUE5_WFQ_WEIGHT    0x0341\n#define    RTL8367C_SCHEDULE_PORT6_QUEUE5_WFQ_WEIGHT_OFFSET    0\n#define    RTL8367C_SCHEDULE_PORT6_QUEUE5_WFQ_WEIGHT_MASK    0x7F\n\n#define    RTL8367C_REG_SCHEDULE_PORT6_QUEUE6_WFQ_WEIGHT    0x0342\n#define    RTL8367C_SCHEDULE_PORT6_QUEUE6_WFQ_WEIGHT_OFFSET    0\n#define    RTL8367C_SCHEDULE_PORT6_QUEUE6_WFQ_WEIGHT_MASK    0x7F\n\n#define    RTL8367C_REG_SCHEDULE_PORT6_QUEUE7_WFQ_WEIGHT    0x0343\n#define    RTL8367C_SCHEDULE_PORT6_QUEUE7_WFQ_WEIGHT_OFFSET    0\n#define    RTL8367C_SCHEDULE_PORT6_QUEUE7_WFQ_WEIGHT_MASK    0x7F\n\n#define    RTL8367C_REG_SCHEDULE_PORT7_QUEUE0_WFQ_WEIGHT    0x0344\n\n#define    RTL8367C_REG_SCHEDULE_PORT7_QUEUE1_WFQ_WEIGHT    0x0345\n#define    RTL8367C_SCHEDULE_PORT7_QUEUE1_WFQ_WEIGHT_OFFSET    0\n#define    RTL8367C_SCHEDULE_PORT7_QUEUE1_WFQ_WEIGHT_MASK    0x7F\n\n#define    RTL8367C_REG_SCHEDULE_PORT7_QUEUE2_WFQ_WEIGHT    0x0346\n#define    RTL8367C_SCHEDULE_PORT7_QUEUE2_WFQ_WEIGHT_OFFSET    0\n#define    RTL8367C_SCHEDULE_PORT7_QUEUE2_WFQ_WEIGHT_MASK    0x7F\n\n#define    RTL8367C_REG_SCHEDULE_PORT7_QUEUE3_WFQ_WEIGHT    0x0347\n#define    RTL8367C_SCHEDULE_PORT7_QUEUE3_WFQ_WEIGHT_OFFSET    0\n#define    RTL8367C_SCHEDULE_PORT7_QUEUE3_WFQ_WEIGHT_MASK    0x7F\n\n#define    RTL8367C_REG_SCHEDULE_PORT7_QUEUE4_WFQ_WEIGHT    0x0348\n#define    RTL8367C_SCHEDULE_PORT7_QUEUE4_WFQ_WEIGHT_OFFSET    0\n#define    RTL8367C_SCHEDULE_PORT7_QUEUE4_WFQ_WEIGHT_MASK    0x7F\n\n#define    RTL8367C_REG_SCHEDULE_PORT7_QUEUE5_WFQ_WEIGHT    0x0349\n#define    RTL8367C_SCHEDULE_PORT7_QUEUE5_WFQ_WEIGHT_OFFSET    0\n#define    RTL8367C_SCHEDULE_PORT7_QUEUE5_WFQ_WEIGHT_MASK    0x7F\n\n#define    RTL8367C_REG_SCHEDULE_PORT7_QUEUE6_WFQ_WEIGHT    0x034a\n#define    RTL8367C_SCHEDULE_PORT7_QUEUE6_WFQ_WEIGHT_OFFSET    0\n#define    RTL8367C_SCHEDULE_PORT7_QUEUE6_WFQ_WEIGHT_MASK    0x7F\n\n#define    RTL8367C_REG_SCHEDULE_PORT7_QUEUE7_WFQ_WEIGHT    0x034b\n#define    RTL8367C_SCHEDULE_PORT7_QUEUE7_WFQ_WEIGHT_OFFSET    0\n#define    RTL8367C_SCHEDULE_PORT7_QUEUE7_WFQ_WEIGHT_MASK    0x7F\n\n#define    RTL8367C_REG_SCHEDULE_PORT8_QUEUE0_WFQ_WEIGHT    0x034c\n\n#define    RTL8367C_REG_SCHEDULE_PORT8_QUEUE1_WFQ_WEIGHT    0x034d\n#define    RTL8367C_SCHEDULE_PORT8_QUEUE1_WFQ_WEIGHT_OFFSET    0\n#define    RTL8367C_SCHEDULE_PORT8_QUEUE1_WFQ_WEIGHT_MASK    0x7F\n\n#define    RTL8367C_REG_SCHEDULE_PORT8_QUEUE2_WFQ_WEIGHT    0x034e\n#define    RTL8367C_SCHEDULE_PORT8_QUEUE2_WFQ_WEIGHT_OFFSET    0\n#define    RTL8367C_SCHEDULE_PORT8_QUEUE2_WFQ_WEIGHT_MASK    0x7F\n\n#define    RTL8367C_REG_SCHEDULE_PORT8_QUEUE3_WFQ_WEIGHT    0x034f\n#define    RTL8367C_SCHEDULE_PORT8_QUEUE3_WFQ_WEIGHT_OFFSET    0\n#define    RTL8367C_SCHEDULE_PORT8_QUEUE3_WFQ_WEIGHT_MASK    0x7F\n\n#define    RTL8367C_REG_SCHEDULE_PORT8_QUEUE4_WFQ_WEIGHT    0x0350\n#define    RTL8367C_SCHEDULE_PORT8_QUEUE4_WFQ_WEIGHT_OFFSET    0\n#define    RTL8367C_SCHEDULE_PORT8_QUEUE4_WFQ_WEIGHT_MASK    0x7F\n\n#define    RTL8367C_REG_SCHEDULE_PORT8_QUEUE5_WFQ_WEIGHT    0x0351\n#define    RTL8367C_SCHEDULE_PORT8_QUEUE5_WFQ_WEIGHT_OFFSET    0\n#define    RTL8367C_SCHEDULE_PORT8_QUEUE5_WFQ_WEIGHT_MASK    0x7F\n\n#define    RTL8367C_REG_SCHEDULE_PORT8_QUEUE6_WFQ_WEIGHT    0x0352\n#define    RTL8367C_SCHEDULE_PORT8_QUEUE6_WFQ_WEIGHT_OFFSET    0\n#define    RTL8367C_SCHEDULE_PORT8_QUEUE6_WFQ_WEIGHT_MASK    0x7F\n\n#define    RTL8367C_REG_SCHEDULE_PORT8_QUEUE7_WFQ_WEIGHT    0x0353\n#define    RTL8367C_SCHEDULE_PORT8_QUEUE7_WFQ_WEIGHT_OFFSET    0\n#define    RTL8367C_SCHEDULE_PORT8_QUEUE7_WFQ_WEIGHT_MASK    0x7F\n\n#define    RTL8367C_REG_SCHEDULE_PORT9_QUEUE0_WFQ_WEIGHT    0x0354\n\n#define    RTL8367C_REG_SCHEDULE_PORT9_QUEUE1_WFQ_WEIGHT    0x0355\n#define    RTL8367C_SCHEDULE_PORT9_QUEUE1_WFQ_WEIGHT_OFFSET    0\n#define    RTL8367C_SCHEDULE_PORT9_QUEUE1_WFQ_WEIGHT_MASK    0x7F\n\n#define    RTL8367C_REG_SCHEDULE_PORT9_QUEUE2_WFQ_WEIGHT    0x0356\n#define    RTL8367C_SCHEDULE_PORT9_QUEUE2_WFQ_WEIGHT_OFFSET    0\n#define    RTL8367C_SCHEDULE_PORT9_QUEUE2_WFQ_WEIGHT_MASK    0x7F\n\n#define    RTL8367C_REG_SCHEDULE_PORT9_QUEUE3_WFQ_WEIGHT    0x0357\n#define    RTL8367C_SCHEDULE_PORT9_QUEUE3_WFQ_WEIGHT_OFFSET    0\n#define    RTL8367C_SCHEDULE_PORT9_QUEUE3_WFQ_WEIGHT_MASK    0x7F\n\n#define    RTL8367C_REG_SCHEDULE_PORT9_QUEUE4_WFQ_WEIGHT    0x0358\n#define    RTL8367C_SCHEDULE_PORT9_QUEUE4_WFQ_WEIGHT_OFFSET    0\n#define    RTL8367C_SCHEDULE_PORT9_QUEUE4_WFQ_WEIGHT_MASK    0x7F\n\n#define    RTL8367C_REG_SCHEDULE_PORT9_QUEUE5_WFQ_WEIGHT    0x0359\n#define    RTL8367C_SCHEDULE_PORT9_QUEUE5_WFQ_WEIGHT_OFFSET    0\n#define    RTL8367C_SCHEDULE_PORT9_QUEUE5_WFQ_WEIGHT_MASK    0x7F\n\n#define    RTL8367C_REG_SCHEDULE_PORT9_QUEUE6_WFQ_WEIGHT    0x035a\n#define    RTL8367C_SCHEDULE_PORT9_QUEUE6_WFQ_WEIGHT_OFFSET    0\n#define    RTL8367C_SCHEDULE_PORT9_QUEUE6_WFQ_WEIGHT_MASK    0x7F\n\n#define    RTL8367C_REG_SCHEDULE_PORT9_QUEUE7_WFQ_WEIGHT    0x035b\n#define    RTL8367C_SCHEDULE_PORT9_QUEUE7_WFQ_WEIGHT_OFFSET    0\n#define    RTL8367C_SCHEDULE_PORT9_QUEUE7_WFQ_WEIGHT_MASK    0x7F\n\n#define    RTL8367C_REG_SCHEDULE_PORT10_QUEUE0_WFQ_WEIGHT    0x035c\n\n#define    RTL8367C_REG_SCHEDULE_PORT10_QUEUE1_WFQ_WEIGHT    0x035d\n#define    RTL8367C_SCHEDULE_PORT10_QUEUE1_WFQ_WEIGHT_OFFSET    0\n#define    RTL8367C_SCHEDULE_PORT10_QUEUE1_WFQ_WEIGHT_MASK    0x7F\n\n#define    RTL8367C_REG_SCHEDULE_PORT10_QUEUE2_WFQ_WEIGHT    0x035e\n#define    RTL8367C_SCHEDULE_PORT10_QUEUE2_WFQ_WEIGHT_OFFSET    0\n#define    RTL8367C_SCHEDULE_PORT10_QUEUE2_WFQ_WEIGHT_MASK    0x7F\n\n#define    RTL8367C_REG_SCHEDULE_PORT10_QUEUE3_WFQ_WEIGHT    0x035f\n#define    RTL8367C_SCHEDULE_PORT10_QUEUE3_WFQ_WEIGHT_OFFSET    0\n#define    RTL8367C_SCHEDULE_PORT10_QUEUE3_WFQ_WEIGHT_MASK    0x7F\n\n#define    RTL8367C_REG_SCHEDULE_PORT10_QUEUE4_WFQ_WEIGHT    0x0360\n#define    RTL8367C_SCHEDULE_PORT10_QUEUE4_WFQ_WEIGHT_OFFSET    0\n#define    RTL8367C_SCHEDULE_PORT10_QUEUE4_WFQ_WEIGHT_MASK    0x7F\n\n#define    RTL8367C_REG_SCHEDULE_PORT10_QUEUE5_WFQ_WEIGHT    0x0361\n#define    RTL8367C_SCHEDULE_PORT10_QUEUE5_WFQ_WEIGHT_OFFSET    0\n#define    RTL8367C_SCHEDULE_PORT10_QUEUE5_WFQ_WEIGHT_MASK    0x7F\n\n#define    RTL8367C_REG_SCHEDULE_PORT10_QUEUE6_WFQ_WEIGHT    0x0362\n#define    RTL8367C_SCHEDULE_PORT10_QUEUE6_WFQ_WEIGHT_OFFSET    0\n#define    RTL8367C_SCHEDULE_PORT10_QUEUE6_WFQ_WEIGHT_MASK    0x7F\n\n#define    RTL8367C_REG_SCHEDULE_PORT10_QUEUE7_WFQ_WEIGHT    0x0363\n#define    RTL8367C_SCHEDULE_PORT10_QUEUE7_WFQ_WEIGHT_OFFSET    0\n#define    RTL8367C_SCHEDULE_PORT10_QUEUE7_WFQ_WEIGHT_MASK    0x7F\n\n#define    RTL8367C_REG_PORT0_EGRESSBW_CTRL0    0x038c\n\n#define    RTL8367C_REG_PORT0_EGRESSBW_CTRL1    0x038d\n#define    RTL8367C_PORT0_EGRESSBW_CTRL1_OFFSET    0\n#define    RTL8367C_PORT0_EGRESSBW_CTRL1_MASK    0x1\n\n#define    RTL8367C_REG_PORT1_EGRESSBW_CTRL0    0x038e\n\n#define    RTL8367C_REG_PORT1_EGRESSBW_CTRL1    0x038f\n#define    RTL8367C_PORT1_EGRESSBW_CTRL1_OFFSET    0\n#define    RTL8367C_PORT1_EGRESSBW_CTRL1_MASK    0x1\n\n#define    RTL8367C_REG_PORT2_EGRESSBW_CTRL0    0x0390\n\n#define    RTL8367C_REG_PORT2_EGRESSBW_CTRL1    0x0391\n#define    RTL8367C_PORT2_EGRESSBW_CTRL1_OFFSET    0\n#define    RTL8367C_PORT2_EGRESSBW_CTRL1_MASK    0x1\n\n#define    RTL8367C_REG_PORT3_EGRESSBW_CTRL0    0x0392\n\n#define    RTL8367C_REG_PORT3_EGRESSBW_CTRL1    0x0393\n#define    RTL8367C_PORT3_EGRESSBW_CTRL1_OFFSET    0\n#define    RTL8367C_PORT3_EGRESSBW_CTRL1_MASK    0x1\n\n#define    RTL8367C_REG_PORT4_EGRESSBW_CTRL0    0x0394\n\n#define    RTL8367C_REG_PORT4_EGRESSBW_CTRL1    0x0395\n#define    RTL8367C_PORT4_EGRESSBW_CTRL1_OFFSET    0\n#define    RTL8367C_PORT4_EGRESSBW_CTRL1_MASK    0x1\n\n#define    RTL8367C_REG_PORT5_EGRESSBW_CTRL0    0x0396\n\n#define    RTL8367C_REG_PORT5_EGRESSBW_CTRL1    0x0397\n#define    RTL8367C_PORT5_EGRESSBW_CTRL1_OFFSET    0\n#define    RTL8367C_PORT5_EGRESSBW_CTRL1_MASK    0x1\n\n#define    RTL8367C_REG_PORT6_EGRESSBW_CTRL0    0x0398\n\n#define    RTL8367C_REG_PORT6_EGRESSBW_CTRL1    0x0399\n#define    RTL8367C_PORT6_EGRESSBW_CTRL1_OFFSET    0\n#define    RTL8367C_PORT6_EGRESSBW_CTRL1_MASK    0x7\n\n#define    RTL8367C_REG_PORT7_EGRESSBW_CTRL0    0x039a\n\n#define    RTL8367C_REG_PORT7_EGRESSBW_CTRL1    0x039b\n#define    RTL8367C_PORT7_EGRESSBW_CTRL1_OFFSET    0\n#define    RTL8367C_PORT7_EGRESSBW_CTRL1_MASK    0x1\n\n#define    RTL8367C_REG_PORT8_EGRESSBW_CTRL0    0x039c\n\n#define    RTL8367C_REG_PORT8_EGRESSBW_CTRL1    0x039d\n#define    RTL8367C_PORT8_EGRESSBW_CTRL1_OFFSET    0\n#define    RTL8367C_PORT8_EGRESSBW_CTRL1_MASK    0x1\n\n#define    RTL8367C_REG_PORT9_EGRESSBW_CTRL0    0x039e\n\n#define    RTL8367C_REG_PORT9_EGRESSBW_CTRL1    0x039f\n#define    RTL8367C_PORT9_EGRESSBW_CTRL1_OFFSET    0\n#define    RTL8367C_PORT9_EGRESSBW_CTRL1_MASK    0x7\n\n#define    RTL8367C_REG_PORT10_EGRESSBW_CTRL0    0x03a0\n\n#define    RTL8367C_REG_PORT10_EGRESSBW_CTRL1    0x03a1\n#define    RTL8367C_PORT10_EGRESSBW_CTRL1_OFFSET    0\n#define    RTL8367C_PORT10_EGRESSBW_CTRL1_MASK    0x1\n\n#define    RTL8367C_REG_SCHEDULE_PORT0_APR_METER_CTRL0    0x03ac\n#define    RTL8367C_SCHEDULE_PORT0_APR_METER_CTRL0_QUEUE4_APR_METER_OFFSET    12\n#define    RTL8367C_SCHEDULE_PORT0_APR_METER_CTRL0_QUEUE4_APR_METER_MASK    0x7000\n#define    RTL8367C_SCHEDULE_PORT0_APR_METER_CTRL0_QUEUE3_APR_METER_OFFSET    9\n#define    RTL8367C_SCHEDULE_PORT0_APR_METER_CTRL0_QUEUE3_APR_METER_MASK    0xE00\n#define    RTL8367C_SCHEDULE_PORT0_APR_METER_CTRL0_QUEUE2_APR_METER_OFFSET    6\n#define    RTL8367C_SCHEDULE_PORT0_APR_METER_CTRL0_QUEUE2_APR_METER_MASK    0x1C0\n#define    RTL8367C_SCHEDULE_PORT0_APR_METER_CTRL0_QUEUE1_APR_METER_OFFSET    3\n#define    RTL8367C_SCHEDULE_PORT0_APR_METER_CTRL0_QUEUE1_APR_METER_MASK    0x38\n#define    RTL8367C_SCHEDULE_PORT0_APR_METER_CTRL0_QUEUE0_APR_METER_OFFSET    0\n#define    RTL8367C_SCHEDULE_PORT0_APR_METER_CTRL0_QUEUE0_APR_METER_MASK    0x7\n\n#define    RTL8367C_REG_SCHEDULE_PORT0_APR_METER_CTRL1    0x03ad\n#define    RTL8367C_SCHEDULE_PORT0_APR_METER_CTRL1_QUEUE7_APR_METER_OFFSET    6\n#define    RTL8367C_SCHEDULE_PORT0_APR_METER_CTRL1_QUEUE7_APR_METER_MASK    0x1C0\n#define    RTL8367C_SCHEDULE_PORT0_APR_METER_CTRL1_QUEUE6_APR_METER_OFFSET    3\n#define    RTL8367C_SCHEDULE_PORT0_APR_METER_CTRL1_QUEUE6_APR_METER_MASK    0x38\n#define    RTL8367C_SCHEDULE_PORT0_APR_METER_CTRL1_QUEUE5_APR_METER_OFFSET    0\n#define    RTL8367C_SCHEDULE_PORT0_APR_METER_CTRL1_QUEUE5_APR_METER_MASK    0x7\n\n#define    RTL8367C_REG_SCHEDULE_PORT1_APR_METER_CTRL0    0x03b0\n#define    RTL8367C_SCHEDULE_PORT1_APR_METER_CTRL0_QUEUE4_APR_METER_OFFSET    12\n#define    RTL8367C_SCHEDULE_PORT1_APR_METER_CTRL0_QUEUE4_APR_METER_MASK    0x7000\n#define    RTL8367C_SCHEDULE_PORT1_APR_METER_CTRL0_QUEUE3_APR_METER_OFFSET    9\n#define    RTL8367C_SCHEDULE_PORT1_APR_METER_CTRL0_QUEUE3_APR_METER_MASK    0xE00\n#define    RTL8367C_SCHEDULE_PORT1_APR_METER_CTRL0_QUEUE2_APR_METER_OFFSET    6\n#define    RTL8367C_SCHEDULE_PORT1_APR_METER_CTRL0_QUEUE2_APR_METER_MASK    0x1C0\n#define    RTL8367C_SCHEDULE_PORT1_APR_METER_CTRL0_QUEUE1_APR_METER_OFFSET    3\n#define    RTL8367C_SCHEDULE_PORT1_APR_METER_CTRL0_QUEUE1_APR_METER_MASK    0x38\n#define    RTL8367C_SCHEDULE_PORT1_APR_METER_CTRL0_QUEUE0_APR_METER_OFFSET    0\n#define    RTL8367C_SCHEDULE_PORT1_APR_METER_CTRL0_QUEUE0_APR_METER_MASK    0x7\n\n#define    RTL8367C_REG_SCHEDULE_PORT1_APR_METER_CTRL1    0x03b1\n#define    RTL8367C_SCHEDULE_PORT1_APR_METER_CTRL1_QUEUE7_APR_METER_OFFSET    6\n#define    RTL8367C_SCHEDULE_PORT1_APR_METER_CTRL1_QUEUE7_APR_METER_MASK    0x1C0\n#define    RTL8367C_SCHEDULE_PORT1_APR_METER_CTRL1_QUEUE6_APR_METER_OFFSET    3\n#define    RTL8367C_SCHEDULE_PORT1_APR_METER_CTRL1_QUEUE6_APR_METER_MASK    0x38\n#define    RTL8367C_SCHEDULE_PORT1_APR_METER_CTRL1_QUEUE5_APR_METER_OFFSET    0\n#define    RTL8367C_SCHEDULE_PORT1_APR_METER_CTRL1_QUEUE5_APR_METER_MASK    0x7\n\n#define    RTL8367C_REG_SCHEDULE_PORT2_APR_METER_CTRL0    0x03b4\n#define    RTL8367C_SCHEDULE_PORT2_APR_METER_CTRL0_QUEUE4_APR_METER_OFFSET    12\n#define    RTL8367C_SCHEDULE_PORT2_APR_METER_CTRL0_QUEUE4_APR_METER_MASK    0x7000\n#define    RTL8367C_SCHEDULE_PORT2_APR_METER_CTRL0_QUEUE3_APR_METER_OFFSET    9\n#define    RTL8367C_SCHEDULE_PORT2_APR_METER_CTRL0_QUEUE3_APR_METER_MASK    0xE00\n#define    RTL8367C_SCHEDULE_PORT2_APR_METER_CTRL0_QUEUE2_APR_METER_OFFSET    6\n#define    RTL8367C_SCHEDULE_PORT2_APR_METER_CTRL0_QUEUE2_APR_METER_MASK    0x1C0\n#define    RTL8367C_SCHEDULE_PORT2_APR_METER_CTRL0_QUEUE1_APR_METER_OFFSET    3\n#define    RTL8367C_SCHEDULE_PORT2_APR_METER_CTRL0_QUEUE1_APR_METER_MASK    0x38\n#define    RTL8367C_SCHEDULE_PORT2_APR_METER_CTRL0_QUEUE0_APR_METER_OFFSET    0\n#define    RTL8367C_SCHEDULE_PORT2_APR_METER_CTRL0_QUEUE0_APR_METER_MASK    0x7\n\n#define    RTL8367C_REG_SCHEDULE_PORT2_APR_METER_CTRL1    0x03b5\n#define    RTL8367C_SCHEDULE_PORT2_APR_METER_CTRL1_QUEUE7_APR_METER_OFFSET    6\n#define    RTL8367C_SCHEDULE_PORT2_APR_METER_CTRL1_QUEUE7_APR_METER_MASK    0x1C0\n#define    RTL8367C_SCHEDULE_PORT2_APR_METER_CTRL1_QUEUE6_APR_METER_OFFSET    3\n#define    RTL8367C_SCHEDULE_PORT2_APR_METER_CTRL1_QUEUE6_APR_METER_MASK    0x38\n#define    RTL8367C_SCHEDULE_PORT2_APR_METER_CTRL1_QUEUE5_APR_METER_OFFSET    0\n#define    RTL8367C_SCHEDULE_PORT2_APR_METER_CTRL1_QUEUE5_APR_METER_MASK    0x7\n\n#define    RTL8367C_REG_SCHEDULE_PORT3_APR_METER_CTRL0    0x03b8\n#define    RTL8367C_SCHEDULE_PORT3_APR_METER_CTRL0_QUEUE4_APR_METER_OFFSET    12\n#define    RTL8367C_SCHEDULE_PORT3_APR_METER_CTRL0_QUEUE4_APR_METER_MASK    0x7000\n#define    RTL8367C_SCHEDULE_PORT3_APR_METER_CTRL0_QUEUE3_APR_METER_OFFSET    9\n#define    RTL8367C_SCHEDULE_PORT3_APR_METER_CTRL0_QUEUE3_APR_METER_MASK    0xE00\n#define    RTL8367C_SCHEDULE_PORT3_APR_METER_CTRL0_QUEUE2_APR_METER_OFFSET    6\n#define    RTL8367C_SCHEDULE_PORT3_APR_METER_CTRL0_QUEUE2_APR_METER_MASK    0x1C0\n#define    RTL8367C_SCHEDULE_PORT3_APR_METER_CTRL0_QUEUE1_APR_METER_OFFSET    3\n#define    RTL8367C_SCHEDULE_PORT3_APR_METER_CTRL0_QUEUE1_APR_METER_MASK    0x38\n#define    RTL8367C_SCHEDULE_PORT3_APR_METER_CTRL0_QUEUE0_APR_METER_OFFSET    0\n#define    RTL8367C_SCHEDULE_PORT3_APR_METER_CTRL0_QUEUE0_APR_METER_MASK    0x7\n\n#define    RTL8367C_REG_SCHEDULE_PORT3_APR_METER_CTRL1    0x03b9\n#define    RTL8367C_SCHEDULE_PORT3_APR_METER_CTRL1_QUEUE7_APR_METER_OFFSET    6\n#define    RTL8367C_SCHEDULE_PORT3_APR_METER_CTRL1_QUEUE7_APR_METER_MASK    0x1C0\n#define    RTL8367C_SCHEDULE_PORT3_APR_METER_CTRL1_QUEUE6_APR_METER_OFFSET    3\n#define    RTL8367C_SCHEDULE_PORT3_APR_METER_CTRL1_QUEUE6_APR_METER_MASK    0x38\n#define    RTL8367C_SCHEDULE_PORT3_APR_METER_CTRL1_QUEUE5_APR_METER_OFFSET    0\n#define    RTL8367C_SCHEDULE_PORT3_APR_METER_CTRL1_QUEUE5_APR_METER_MASK    0x7\n\n#define    RTL8367C_REG_SCHEDULE_PORT4_APR_METER_CTRL0    0x03bc\n#define    RTL8367C_SCHEDULE_PORT4_APR_METER_CTRL0_QUEUE4_APR_METER_OFFSET    12\n#define    RTL8367C_SCHEDULE_PORT4_APR_METER_CTRL0_QUEUE4_APR_METER_MASK    0x7000\n#define    RTL8367C_SCHEDULE_PORT4_APR_METER_CTRL0_QUEUE3_APR_METER_OFFSET    9\n#define    RTL8367C_SCHEDULE_PORT4_APR_METER_CTRL0_QUEUE3_APR_METER_MASK    0xE00\n#define    RTL8367C_SCHEDULE_PORT4_APR_METER_CTRL0_QUEUE2_APR_METER_OFFSET    6\n#define    RTL8367C_SCHEDULE_PORT4_APR_METER_CTRL0_QUEUE2_APR_METER_MASK    0x1C0\n#define    RTL8367C_SCHEDULE_PORT4_APR_METER_CTRL0_QUEUE1_APR_METER_OFFSET    3\n#define    RTL8367C_SCHEDULE_PORT4_APR_METER_CTRL0_QUEUE1_APR_METER_MASK    0x38\n#define    RTL8367C_SCHEDULE_PORT4_APR_METER_CTRL0_QUEUE0_APR_METER_OFFSET    0\n#define    RTL8367C_SCHEDULE_PORT4_APR_METER_CTRL0_QUEUE0_APR_METER_MASK    0x7\n\n#define    RTL8367C_REG_SCHEDULE_PORT4_APR_METER_CTRL1    0x03bd\n#define    RTL8367C_SCHEDULE_PORT4_APR_METER_CTRL1_QUEUE7_APR_METER_OFFSET    6\n#define    RTL8367C_SCHEDULE_PORT4_APR_METER_CTRL1_QUEUE7_APR_METER_MASK    0x1C0\n#define    RTL8367C_SCHEDULE_PORT4_APR_METER_CTRL1_QUEUE6_APR_METER_OFFSET    3\n#define    RTL8367C_SCHEDULE_PORT4_APR_METER_CTRL1_QUEUE6_APR_METER_MASK    0x38\n#define    RTL8367C_SCHEDULE_PORT4_APR_METER_CTRL1_QUEUE5_APR_METER_OFFSET    0\n#define    RTL8367C_SCHEDULE_PORT4_APR_METER_CTRL1_QUEUE5_APR_METER_MASK    0x7\n\n#define    RTL8367C_REG_SCHEDULE_PORT5_APR_METER_CTRL0    0x03c0\n#define    RTL8367C_SCHEDULE_PORT5_APR_METER_CTRL0_QUEUE4_APR_METER_OFFSET    12\n#define    RTL8367C_SCHEDULE_PORT5_APR_METER_CTRL0_QUEUE4_APR_METER_MASK    0x7000\n#define    RTL8367C_SCHEDULE_PORT5_APR_METER_CTRL0_QUEUE3_APR_METER_OFFSET    9\n#define    RTL8367C_SCHEDULE_PORT5_APR_METER_CTRL0_QUEUE3_APR_METER_MASK    0xE00\n#define    RTL8367C_SCHEDULE_PORT5_APR_METER_CTRL0_QUEUE2_APR_METER_OFFSET    6\n#define    RTL8367C_SCHEDULE_PORT5_APR_METER_CTRL0_QUEUE2_APR_METER_MASK    0x1C0\n#define    RTL8367C_SCHEDULE_PORT5_APR_METER_CTRL0_QUEUE1_APR_METER_OFFSET    3\n#define    RTL8367C_SCHEDULE_PORT5_APR_METER_CTRL0_QUEUE1_APR_METER_MASK    0x38\n#define    RTL8367C_SCHEDULE_PORT5_APR_METER_CTRL0_QUEUE0_APR_METER_OFFSET    0\n#define    RTL8367C_SCHEDULE_PORT5_APR_METER_CTRL0_QUEUE0_APR_METER_MASK    0x7\n\n#define    RTL8367C_REG_SCHEDULE_PORT5_APR_METER_CTRL1    0x03c1\n#define    RTL8367C_SCHEDULE_PORT5_APR_METER_CTRL1_QUEUE7_APR_METER_OFFSET    6\n#define    RTL8367C_SCHEDULE_PORT5_APR_METER_CTRL1_QUEUE7_APR_METER_MASK    0x1C0\n#define    RTL8367C_SCHEDULE_PORT5_APR_METER_CTRL1_QUEUE6_APR_METER_OFFSET    3\n#define    RTL8367C_SCHEDULE_PORT5_APR_METER_CTRL1_QUEUE6_APR_METER_MASK    0x38\n#define    RTL8367C_SCHEDULE_PORT5_APR_METER_CTRL1_QUEUE5_APR_METER_OFFSET    0\n#define    RTL8367C_SCHEDULE_PORT5_APR_METER_CTRL1_QUEUE5_APR_METER_MASK    0x7\n\n#define    RTL8367C_REG_SCHEDULE_PORT6_APR_METER_CTRL0    0x03c4\n#define    RTL8367C_SCHEDULE_PORT6_APR_METER_CTRL0_QUEUE4_APR_METER_OFFSET    12\n#define    RTL8367C_SCHEDULE_PORT6_APR_METER_CTRL0_QUEUE4_APR_METER_MASK    0x7000\n#define    RTL8367C_SCHEDULE_PORT6_APR_METER_CTRL0_QUEUE3_APR_METER_OFFSET    9\n#define    RTL8367C_SCHEDULE_PORT6_APR_METER_CTRL0_QUEUE3_APR_METER_MASK    0xE00\n#define    RTL8367C_SCHEDULE_PORT6_APR_METER_CTRL0_QUEUE2_APR_METER_OFFSET    6\n#define    RTL8367C_SCHEDULE_PORT6_APR_METER_CTRL0_QUEUE2_APR_METER_MASK    0x1C0\n#define    RTL8367C_SCHEDULE_PORT6_APR_METER_CTRL0_QUEUE1_APR_METER_OFFSET    3\n#define    RTL8367C_SCHEDULE_PORT6_APR_METER_CTRL0_QUEUE1_APR_METER_MASK    0x38\n#define    RTL8367C_SCHEDULE_PORT6_APR_METER_CTRL0_QUEUE0_APR_METER_OFFSET    0\n#define    RTL8367C_SCHEDULE_PORT6_APR_METER_CTRL0_QUEUE0_APR_METER_MASK    0x7\n\n#define    RTL8367C_REG_SCHEDULE_PORT6_APR_METER_CTRL1    0x03c5\n#define    RTL8367C_SCHEDULE_PORT6_APR_METER_CTRL1_QUEUE7_APR_METER_OFFSET    6\n#define    RTL8367C_SCHEDULE_PORT6_APR_METER_CTRL1_QUEUE7_APR_METER_MASK    0x1C0\n#define    RTL8367C_SCHEDULE_PORT6_APR_METER_CTRL1_QUEUE6_APR_METER_OFFSET    3\n#define    RTL8367C_SCHEDULE_PORT6_APR_METER_CTRL1_QUEUE6_APR_METER_MASK    0x38\n#define    RTL8367C_SCHEDULE_PORT6_APR_METER_CTRL1_QUEUE5_APR_METER_OFFSET    0\n#define    RTL8367C_SCHEDULE_PORT6_APR_METER_CTRL1_QUEUE5_APR_METER_MASK    0x7\n\n#define    RTL8367C_REG_SCHEDULE_PORT7_APR_METER_CTRL0    0x03c8\n#define    RTL8367C_SCHEDULE_PORT7_APR_METER_CTRL0_QUEUE4_APR_METER_OFFSET    12\n#define    RTL8367C_SCHEDULE_PORT7_APR_METER_CTRL0_QUEUE4_APR_METER_MASK    0x7000\n#define    RTL8367C_SCHEDULE_PORT7_APR_METER_CTRL0_QUEUE3_APR_METER_OFFSET    9\n#define    RTL8367C_SCHEDULE_PORT7_APR_METER_CTRL0_QUEUE3_APR_METER_MASK    0xE00\n#define    RTL8367C_SCHEDULE_PORT7_APR_METER_CTRL0_QUEUE2_APR_METER_OFFSET    6\n#define    RTL8367C_SCHEDULE_PORT7_APR_METER_CTRL0_QUEUE2_APR_METER_MASK    0x1C0\n#define    RTL8367C_SCHEDULE_PORT7_APR_METER_CTRL0_QUEUE1_APR_METER_OFFSET    3\n#define    RTL8367C_SCHEDULE_PORT7_APR_METER_CTRL0_QUEUE1_APR_METER_MASK    0x38\n#define    RTL8367C_SCHEDULE_PORT7_APR_METER_CTRL0_QUEUE0_APR_METER_OFFSET    0\n#define    RTL8367C_SCHEDULE_PORT7_APR_METER_CTRL0_QUEUE0_APR_METER_MASK    0x7\n\n#define    RTL8367C_REG_SCHEDULE_PORT7_APR_METER_CTRL1    0x03c9\n#define    RTL8367C_SCHEDULE_PORT7_APR_METER_CTRL1_QUEUE7_APR_METER_OFFSET    6\n#define    RTL8367C_SCHEDULE_PORT7_APR_METER_CTRL1_QUEUE7_APR_METER_MASK    0x1C0\n#define    RTL8367C_SCHEDULE_PORT7_APR_METER_CTRL1_QUEUE6_APR_METER_OFFSET    3\n#define    RTL8367C_SCHEDULE_PORT7_APR_METER_CTRL1_QUEUE6_APR_METER_MASK    0x38\n#define    RTL8367C_SCHEDULE_PORT7_APR_METER_CTRL1_QUEUE5_APR_METER_OFFSET    0\n#define    RTL8367C_SCHEDULE_PORT7_APR_METER_CTRL1_QUEUE5_APR_METER_MASK    0x7\n\n#define    RTL8367C_REG_SCHEDULE_PORT8_APR_METER_CTRL0    0x03ca\n#define    RTL8367C_SCHEDULE_PORT8_APR_METER_CTRL0_QUEUE4_APR_METER_OFFSET    12\n#define    RTL8367C_SCHEDULE_PORT8_APR_METER_CTRL0_QUEUE4_APR_METER_MASK    0x7000\n#define    RTL8367C_SCHEDULE_PORT8_APR_METER_CTRL0_QUEUE3_APR_METER_OFFSET    9\n#define    RTL8367C_SCHEDULE_PORT8_APR_METER_CTRL0_QUEUE3_APR_METER_MASK    0xE00\n#define    RTL8367C_SCHEDULE_PORT8_APR_METER_CTRL0_QUEUE2_APR_METER_OFFSET    6\n#define    RTL8367C_SCHEDULE_PORT8_APR_METER_CTRL0_QUEUE2_APR_METER_MASK    0x1C0\n#define    RTL8367C_SCHEDULE_PORT8_APR_METER_CTRL0_QUEUE1_APR_METER_OFFSET    3\n#define    RTL8367C_SCHEDULE_PORT8_APR_METER_CTRL0_QUEUE1_APR_METER_MASK    0x38\n#define    RTL8367C_SCHEDULE_PORT8_APR_METER_CTRL0_QUEUE0_APR_METER_OFFSET    0\n#define    RTL8367C_SCHEDULE_PORT8_APR_METER_CTRL0_QUEUE0_APR_METER_MASK    0x7\n\n#define    RTL8367C_REG_SCHEDULE_PORT8_APR_METER_CTRL1    0x03cb\n#define    RTL8367C_SCHEDULE_PORT8_APR_METER_CTRL1_QUEUE7_APR_METER_OFFSET    6\n#define    RTL8367C_SCHEDULE_PORT8_APR_METER_CTRL1_QUEUE7_APR_METER_MASK    0x1C0\n#define    RTL8367C_SCHEDULE_PORT8_APR_METER_CTRL1_QUEUE6_APR_METER_OFFSET    3\n#define    RTL8367C_SCHEDULE_PORT8_APR_METER_CTRL1_QUEUE6_APR_METER_MASK    0x38\n#define    RTL8367C_SCHEDULE_PORT8_APR_METER_CTRL1_QUEUE5_APR_METER_OFFSET    0\n#define    RTL8367C_SCHEDULE_PORT8_APR_METER_CTRL1_QUEUE5_APR_METER_MASK    0x7\n\n#define    RTL8367C_REG_SCHEDULE_PORT9_APR_METER_CTRL0    0x03cc\n#define    RTL8367C_SCHEDULE_PORT9_APR_METER_CTRL0_QUEUE4_APR_METER_OFFSET    12\n#define    RTL8367C_SCHEDULE_PORT9_APR_METER_CTRL0_QUEUE4_APR_METER_MASK    0x7000\n#define    RTL8367C_SCHEDULE_PORT9_APR_METER_CTRL0_QUEUE3_APR_METER_OFFSET    9\n#define    RTL8367C_SCHEDULE_PORT9_APR_METER_CTRL0_QUEUE3_APR_METER_MASK    0xE00\n#define    RTL8367C_SCHEDULE_PORT9_APR_METER_CTRL0_QUEUE2_APR_METER_OFFSET    6\n#define    RTL8367C_SCHEDULE_PORT9_APR_METER_CTRL0_QUEUE2_APR_METER_MASK    0x1C0\n#define    RTL8367C_SCHEDULE_PORT9_APR_METER_CTRL0_QUEUE1_APR_METER_OFFSET    3\n#define    RTL8367C_SCHEDULE_PORT9_APR_METER_CTRL0_QUEUE1_APR_METER_MASK    0x38\n#define    RTL8367C_SCHEDULE_PORT9_APR_METER_CTRL0_QUEUE0_APR_METER_OFFSET    0\n#define    RTL8367C_SCHEDULE_PORT9_APR_METER_CTRL0_QUEUE0_APR_METER_MASK    0x7\n\n#define    RTL8367C_REG_SCHEDULE_PORT9_APR_METER_CTRL1    0x03cd\n#define    RTL8367C_SCHEDULE_PORT9_APR_METER_CTRL1_QUEUE7_APR_METER_OFFSET    6\n#define    RTL8367C_SCHEDULE_PORT9_APR_METER_CTRL1_QUEUE7_APR_METER_MASK    0x1C0\n#define    RTL8367C_SCHEDULE_PORT9_APR_METER_CTRL1_QUEUE6_APR_METER_OFFSET    3\n#define    RTL8367C_SCHEDULE_PORT9_APR_METER_CTRL1_QUEUE6_APR_METER_MASK    0x38\n#define    RTL8367C_SCHEDULE_PORT9_APR_METER_CTRL1_QUEUE5_APR_METER_OFFSET    0\n#define    RTL8367C_SCHEDULE_PORT9_APR_METER_CTRL1_QUEUE5_APR_METER_MASK    0x7\n\n#define    RTL8367C_REG_SCHEDULE_PORT10_APR_METER_CTRL0    0x03ce\n#define    RTL8367C_SCHEDULE_PORT10_APR_METER_CTRL0_QUEUE4_APR_METER_OFFSET    12\n#define    RTL8367C_SCHEDULE_PORT10_APR_METER_CTRL0_QUEUE4_APR_METER_MASK    0x7000\n#define    RTL8367C_SCHEDULE_PORT10_APR_METER_CTRL0_QUEUE3_APR_METER_OFFSET    9\n#define    RTL8367C_SCHEDULE_PORT10_APR_METER_CTRL0_QUEUE3_APR_METER_MASK    0xE00\n#define    RTL8367C_SCHEDULE_PORT10_APR_METER_CTRL0_QUEUE2_APR_METER_OFFSET    6\n#define    RTL8367C_SCHEDULE_PORT10_APR_METER_CTRL0_QUEUE2_APR_METER_MASK    0x1C0\n#define    RTL8367C_SCHEDULE_PORT10_APR_METER_CTRL0_QUEUE1_APR_METER_OFFSET    3\n#define    RTL8367C_SCHEDULE_PORT10_APR_METER_CTRL0_QUEUE1_APR_METER_MASK    0x38\n#define    RTL8367C_SCHEDULE_PORT10_APR_METER_CTRL0_QUEUE0_APR_METER_OFFSET    0\n#define    RTL8367C_SCHEDULE_PORT10_APR_METER_CTRL0_QUEUE0_APR_METER_MASK    0x7\n\n#define    RTL8367C_REG_SCHEDULE_PORT10_APR_METER_CTRL1    0x03cf\n#define    RTL8367C_SCHEDULE_PORT10_APR_METER_CTRL1_QUEUE7_APR_METER_OFFSET    6\n#define    RTL8367C_SCHEDULE_PORT10_APR_METER_CTRL1_QUEUE7_APR_METER_MASK    0x1C0\n#define    RTL8367C_SCHEDULE_PORT10_APR_METER_CTRL1_QUEUE6_APR_METER_OFFSET    3\n#define    RTL8367C_SCHEDULE_PORT10_APR_METER_CTRL1_QUEUE6_APR_METER_MASK    0x38\n#define    RTL8367C_SCHEDULE_PORT10_APR_METER_CTRL1_QUEUE5_APR_METER_OFFSET    0\n#define    RTL8367C_SCHEDULE_PORT10_APR_METER_CTRL1_QUEUE5_APR_METER_MASK    0x7\n\n#define    RTL8367C_REG_LINE_RATE_1G_L    0x03ec\n\n#define    RTL8367C_REG_LINE_RATE_1G_H    0x03ed\n#define    RTL8367C_LINE_RATE_1G_H_OFFSET    0\n#define    RTL8367C_LINE_RATE_1G_H_MASK    0x1\n\n#define    RTL8367C_REG_LINE_RATE_100_L    0x03ee\n\n#define    RTL8367C_REG_LINE_RATE_100_H    0x03ef\n#define    RTL8367C_LINE_RATE_100_H_OFFSET    0\n#define    RTL8367C_LINE_RATE_100_H_MASK    0x1\n\n#define    RTL8367C_REG_LINE_RATE_10_L    0x03f0\n\n#define    RTL8367C_REG_LINE_RATE_10_H    0x03f1\n#define    RTL8367C_LINE_RATE_10_H_OFFSET    0\n#define    RTL8367C_LINE_RATE_10_H_MASK    0x1\n\n#define    RTL8367C_REG_DUMMY_03f2    0x03f2\n\n#define    RTL8367C_REG_DUMMY_03f3    0x03f3\n\n#define    RTL8367C_REG_DUMMY_03f4    0x03f4\n\n#define    RTL8367C_REG_DUMMY_03f5    0x03f5\n\n#define    RTL8367C_REG_DUMMY_03f6    0x03f6\n\n#define    RTL8367C_REG_BYPASS_LINE_RATE    0x03f7\n#define    RTL8367C_BYPASS_PORT10_CONSTRAINT_OFFSET    5\n#define    RTL8367C_BYPASS_PORT10_CONSTRAINT_MASK    0x20\n#define    RTL8367C_BYPASS_PORT9_CONSTRAINT_OFFSET    4\n#define    RTL8367C_BYPASS_PORT9_CONSTRAINT_MASK    0x10\n#define    RTL8367C_BYPASS_PORT8_CONSTRAINT_OFFSET    3\n#define    RTL8367C_BYPASS_PORT8_CONSTRAINT_MASK    0x8\n#define    RTL8367C_BYPASS_PORT7_CONSTRAINT_OFFSET    2\n#define    RTL8367C_BYPASS_PORT7_CONSTRAINT_MASK    0x4\n#define    RTL8367C_BYPASS_PORT6_CONSTRAINT_OFFSET    1\n#define    RTL8367C_BYPASS_PORT6_CONSTRAINT_MASK    0x2\n#define    RTL8367C_BYPASS_PORT5_CONSTRAINT_OFFSET    0\n#define    RTL8367C_BYPASS_PORT5_CONSTRAINT_MASK    0x1\n\n#define    RTL8367C_REG_LINE_RATE_500_H    0x03f8\n#define    RTL8367C_LINE_RATE_500_H_OFFSET    0\n#define    RTL8367C_LINE_RATE_500_H_MASK    0x7\n\n#define    RTL8367C_REG_LINE_RATE_500_L    0x03f9\n\n#define    RTL8367C_REG_LINE_RATE_HSG_H    0x03fa\n#define    RTL8367C_LINE_RATE_HSG_H_OFFSET    0\n#define    RTL8367C_LINE_RATE_HSG_H_MASK    0x7\n\n#define    RTL8367C_REG_LINE_RATE_HSG_L    0x03fb\n\n/* (16'h0500)table_reg */\n\n#define    RTL8367C_REG_TABLE_ACCESS_CTRL    0x0500\n#define    RTL8367C_TABLE_ACCESS_CTRL_SPA_OFFSET    8\n#define    RTL8367C_TABLE_ACCESS_CTRL_SPA_MASK    0xF00\n#define    RTL8367C_ACCESS_METHOD_OFFSET    4\n#define    RTL8367C_ACCESS_METHOD_MASK    0x70\n#define    RTL8367C_COMMAND_TYPE_OFFSET    3\n#define    RTL8367C_COMMAND_TYPE_MASK    0x8\n#define    RTL8367C_TABLE_TYPE_OFFSET    0\n#define    RTL8367C_TABLE_TYPE_MASK    0x7\n\n#define    RTL8367C_REG_TABLE_ACCESS_ADDR    0x0501\n#define    RTL8367C_TABLE_ACCESS_ADDR_OFFSET    0\n#define    RTL8367C_TABLE_ACCESS_ADDR_MASK    0x1FFF\n\n#define    RTL8367C_REG_TABLE_LUT_ADDR    0x0502\n#define    RTL8367C_ADDRESS2_OFFSET    14\n#define    RTL8367C_ADDRESS2_MASK    0x4000\n#define    RTL8367C_TABLE_LUT_ADDR_BUSY_FLAG_OFFSET    13\n#define    RTL8367C_TABLE_LUT_ADDR_BUSY_FLAG_MASK    0x2000\n#define    RTL8367C_HIT_STATUS_OFFSET    12\n#define    RTL8367C_HIT_STATUS_MASK    0x1000\n#define    RTL8367C_TABLE_LUT_ADDR_TYPE_OFFSET    11\n#define    RTL8367C_TABLE_LUT_ADDR_TYPE_MASK    0x800\n#define    RTL8367C_TABLE_LUT_ADDR_ADDRESS_OFFSET    0\n#define    RTL8367C_TABLE_LUT_ADDR_ADDRESS_MASK    0x7FF\n\n#define    RTL8367C_REG_HSA_HSB_LATCH    0x0503\n#define    RTL8367C_LATCH_ALWAYS_OFFSET    15\n#define    RTL8367C_LATCH_ALWAYS_MASK    0x8000\n#define    RTL8367C_LATCH_FIRST_OFFSET    14\n#define    RTL8367C_LATCH_FIRST_MASK    0x4000\n#define    RTL8367C_SPA_EN_OFFSET    13\n#define    RTL8367C_SPA_EN_MASK    0x2000\n#define    RTL8367C_FORWARD_EN_OFFSET    12\n#define    RTL8367C_FORWARD_EN_MASK    0x1000\n#define    RTL8367C_REASON_EN_OFFSET    11\n#define    RTL8367C_REASON_EN_MASK    0x800\n#define    RTL8367C_HSA_HSB_LATCH_SPA_OFFSET    8\n#define    RTL8367C_HSA_HSB_LATCH_SPA_MASK    0x700\n#define    RTL8367C_FORWARD_OFFSET    6\n#define    RTL8367C_FORWARD_MASK    0xC0\n#define    RTL8367C_REASON_OFFSET    0\n#define    RTL8367C_REASON_MASK    0x3F\n\n#define    RTL8367C_REG_HSA_HSB_LATCH2    0x0504\n#define    RTL8367C_HSA_HSB_LATCH2_Reserved_OFFSET    1\n#define    RTL8367C_HSA_HSB_LATCH2_Reserved_MASK    0xFFFE\n#define    RTL8367C_SPA2_OFFSET    0\n#define    RTL8367C_SPA2_MASK    0x1\n\n#define    RTL8367C_REG_TABLE_WRITE_DATA0    0x0510\n\n#define    RTL8367C_REG_TABLE_WRITE_DATA1    0x0511\n\n#define    RTL8367C_REG_TABLE_WRITE_DATA2    0x0512\n\n#define    RTL8367C_REG_TABLE_WRITE_DATA3    0x0513\n\n#define    RTL8367C_REG_TABLE_WRITE_DATA4    0x0514\n\n#define    RTL8367C_REG_TABLE_WRITE_DATA5    0x0515\n\n#define    RTL8367C_REG_TABLE_WRITE_DATA6    0x0516\n\n#define    RTL8367C_REG_TABLE_WRITE_DATA7    0x0517\n\n#define    RTL8367C_REG_TABLE_WRITE_DATA8    0x0518\n\n#define    RTL8367C_REG_TABLE_WRITE_DATA9    0x0519\n#define    RTL8367C_TABLE_WRITE_DATA9_OFFSET    0\n#define    RTL8367C_TABLE_WRITE_DATA9_MASK    0xF\n\n#define    RTL8367C_REG_TABLE_READ_DATA0    0x0520\n\n#define    RTL8367C_REG_TABLE_READ_DATA1    0x0521\n\n#define    RTL8367C_REG_TABLE_READ_DATA2    0x0522\n\n#define    RTL8367C_REG_TABLE_READ_DATA3    0x0523\n\n#define    RTL8367C_REG_TABLE_READ_DATA4    0x0524\n\n#define    RTL8367C_REG_TABLE_READ_DATA5    0x0525\n\n#define    RTL8367C_REG_TABLE_READ_DATA6    0x0526\n\n#define    RTL8367C_REG_TABLE_READ_DATA7    0x0527\n\n#define    RTL8367C_REG_TABLE_READ_DATA8    0x0528\n\n#define    RTL8367C_REG_TABLE_READ_DATA9    0x0529\n#define    RTL8367C_TABLE_READ_DATA9_OFFSET    0\n#define    RTL8367C_TABLE_READ_DATA9_MASK    0xF\n\n#define    RTL8367C_REG_TBL_DUMMY00    0x0550\n\n#define    RTL8367C_REG_TBL_DUMMY01    0x0551\n\n/* (16'h0600)acl_reg */\n\n#define    RTL8367C_REG_ACL_RULE_TEMPLATE0_CTRL0    0x0600\n#define    RTL8367C_ACL_RULE_TEMPLATE0_CTRL0_FIELD1_OFFSET    8\n#define    RTL8367C_ACL_RULE_TEMPLATE0_CTRL0_FIELD1_MASK    0x7F00\n#define    RTL8367C_ACL_RULE_TEMPLATE0_CTRL0_FIELD0_OFFSET    0\n#define    RTL8367C_ACL_RULE_TEMPLATE0_CTRL0_FIELD0_MASK    0x7F\n\n#define    RTL8367C_REG_ACL_RULE_TEMPLATE0_CTRL1    0x0601\n#define    RTL8367C_ACL_RULE_TEMPLATE0_CTRL1_FIELD3_OFFSET    8\n#define    RTL8367C_ACL_RULE_TEMPLATE0_CTRL1_FIELD3_MASK    0x7F00\n#define    RTL8367C_ACL_RULE_TEMPLATE0_CTRL1_FIELD2_OFFSET    0\n#define    RTL8367C_ACL_RULE_TEMPLATE0_CTRL1_FIELD2_MASK    0x7F\n\n#define    RTL8367C_REG_ACL_RULE_TEMPLATE0_CTRL2    0x0602\n#define    RTL8367C_ACL_RULE_TEMPLATE0_CTRL2_FIELD5_OFFSET    8\n#define    RTL8367C_ACL_RULE_TEMPLATE0_CTRL2_FIELD5_MASK    0x7F00\n#define    RTL8367C_ACL_RULE_TEMPLATE0_CTRL2_FIELD4_OFFSET    0\n#define    RTL8367C_ACL_RULE_TEMPLATE0_CTRL2_FIELD4_MASK    0x7F\n\n#define    RTL8367C_REG_ACL_RULE_TEMPLATE0_CTRL3    0x0603\n#define    RTL8367C_ACL_RULE_TEMPLATE0_CTRL3_FIELD7_OFFSET    8\n#define    RTL8367C_ACL_RULE_TEMPLATE0_CTRL3_FIELD7_MASK    0x7F00\n#define    RTL8367C_ACL_RULE_TEMPLATE0_CTRL3_FIELD6_OFFSET    0\n#define    RTL8367C_ACL_RULE_TEMPLATE0_CTRL3_FIELD6_MASK    0x7F\n\n#define    RTL8367C_REG_ACL_RULE_TEMPLATE1_CTRL0    0x0604\n#define    RTL8367C_ACL_RULE_TEMPLATE1_CTRL0_FIELD1_OFFSET    8\n#define    RTL8367C_ACL_RULE_TEMPLATE1_CTRL0_FIELD1_MASK    0x7F00\n#define    RTL8367C_ACL_RULE_TEMPLATE1_CTRL0_FIELD0_OFFSET    0\n#define    RTL8367C_ACL_RULE_TEMPLATE1_CTRL0_FIELD0_MASK    0x7F\n\n#define    RTL8367C_REG_ACL_RULE_TEMPLATE1_CTRL1    0x0605\n#define    RTL8367C_ACL_RULE_TEMPLATE1_CTRL1_FIELD3_OFFSET    8\n#define    RTL8367C_ACL_RULE_TEMPLATE1_CTRL1_FIELD3_MASK    0x7F00\n#define    RTL8367C_ACL_RULE_TEMPLATE1_CTRL1_FIELD2_OFFSET    0\n#define    RTL8367C_ACL_RULE_TEMPLATE1_CTRL1_FIELD2_MASK    0x7F\n\n#define    RTL8367C_REG_ACL_RULE_TEMPLATE1_CTRL2    0x0606\n#define    RTL8367C_ACL_RULE_TEMPLATE1_CTRL2_FIELD5_OFFSET    8\n#define    RTL8367C_ACL_RULE_TEMPLATE1_CTRL2_FIELD5_MASK    0x7F00\n#define    RTL8367C_ACL_RULE_TEMPLATE1_CTRL2_FIELD4_OFFSET    0\n#define    RTL8367C_ACL_RULE_TEMPLATE1_CTRL2_FIELD4_MASK    0x7F\n\n#define    RTL8367C_REG_ACL_RULE_TEMPLATE1_CTRL3    0x0607\n#define    RTL8367C_ACL_RULE_TEMPLATE1_CTRL3_FIELD7_OFFSET    8\n#define    RTL8367C_ACL_RULE_TEMPLATE1_CTRL3_FIELD7_MASK    0x7F00\n#define    RTL8367C_ACL_RULE_TEMPLATE1_CTRL3_FIELD6_OFFSET    0\n#define    RTL8367C_ACL_RULE_TEMPLATE1_CTRL3_FIELD6_MASK    0x7F\n\n#define    RTL8367C_REG_ACL_RULE_TEMPLATE2_CTRL0    0x0608\n#define    RTL8367C_ACL_RULE_TEMPLATE2_CTRL0_FIELD1_OFFSET    8\n#define    RTL8367C_ACL_RULE_TEMPLATE2_CTRL0_FIELD1_MASK    0x7F00\n#define    RTL8367C_ACL_RULE_TEMPLATE2_CTRL0_FIELD0_OFFSET    0\n#define    RTL8367C_ACL_RULE_TEMPLATE2_CTRL0_FIELD0_MASK    0x7F\n\n#define    RTL8367C_REG_ACL_RULE_TEMPLATE2_CTRL1    0x0609\n#define    RTL8367C_ACL_RULE_TEMPLATE2_CTRL1_FIELD3_OFFSET    8\n#define    RTL8367C_ACL_RULE_TEMPLATE2_CTRL1_FIELD3_MASK    0x7F00\n#define    RTL8367C_ACL_RULE_TEMPLATE2_CTRL1_FIELD2_OFFSET    0\n#define    RTL8367C_ACL_RULE_TEMPLATE2_CTRL1_FIELD2_MASK    0x7F\n\n#define    RTL8367C_REG_ACL_RULE_TEMPLATE2_CTRL2    0x060a\n#define    RTL8367C_ACL_RULE_TEMPLATE2_CTRL2_FIELD5_OFFSET    8\n#define    RTL8367C_ACL_RULE_TEMPLATE2_CTRL2_FIELD5_MASK    0x7F00\n#define    RTL8367C_ACL_RULE_TEMPLATE2_CTRL2_FIELD4_OFFSET    0\n#define    RTL8367C_ACL_RULE_TEMPLATE2_CTRL2_FIELD4_MASK    0x7F\n\n#define    RTL8367C_REG_ACL_RULE_TEMPLATE2_CTRL3    0x060b\n#define    RTL8367C_ACL_RULE_TEMPLATE2_CTRL3_FIELD7_OFFSET    8\n#define    RTL8367C_ACL_RULE_TEMPLATE2_CTRL3_FIELD7_MASK    0x7F00\n#define    RTL8367C_ACL_RULE_TEMPLATE2_CTRL3_FIELD6_OFFSET    0\n#define    RTL8367C_ACL_RULE_TEMPLATE2_CTRL3_FIELD6_MASK    0x7F\n\n#define    RTL8367C_REG_ACL_RULE_TEMPLATE3_CTRL0    0x060c\n#define    RTL8367C_ACL_RULE_TEMPLATE3_CTRL0_FIELD1_OFFSET    8\n#define    RTL8367C_ACL_RULE_TEMPLATE3_CTRL0_FIELD1_MASK    0x7F00\n#define    RTL8367C_ACL_RULE_TEMPLATE3_CTRL0_FIELD0_OFFSET    0\n#define    RTL8367C_ACL_RULE_TEMPLATE3_CTRL0_FIELD0_MASK    0x7F\n\n#define    RTL8367C_REG_ACL_RULE_TEMPLATE3_CTRL1    0x060d\n#define    RTL8367C_ACL_RULE_TEMPLATE3_CTRL1_FIELD3_OFFSET    8\n#define    RTL8367C_ACL_RULE_TEMPLATE3_CTRL1_FIELD3_MASK    0x7F00\n#define    RTL8367C_ACL_RULE_TEMPLATE3_CTRL1_FIELD2_OFFSET    0\n#define    RTL8367C_ACL_RULE_TEMPLATE3_CTRL1_FIELD2_MASK    0x7F\n\n#define    RTL8367C_REG_ACL_RULE_TEMPLATE3_CTRL2    0x060e\n#define    RTL8367C_ACL_RULE_TEMPLATE3_CTRL2_FIELD5_OFFSET    8\n#define    RTL8367C_ACL_RULE_TEMPLATE3_CTRL2_FIELD5_MASK    0x7F00\n#define    RTL8367C_ACL_RULE_TEMPLATE3_CTRL2_FIELD4_OFFSET    0\n#define    RTL8367C_ACL_RULE_TEMPLATE3_CTRL2_FIELD4_MASK    0x7F\n\n#define    RTL8367C_REG_ACL_RULE_TEMPLATE3_CTRL3    0x060f\n#define    RTL8367C_ACL_RULE_TEMPLATE3_CTRL3_FIELD7_OFFSET    8\n#define    RTL8367C_ACL_RULE_TEMPLATE3_CTRL3_FIELD7_MASK    0x7F00\n#define    RTL8367C_ACL_RULE_TEMPLATE3_CTRL3_FIELD6_OFFSET    0\n#define    RTL8367C_ACL_RULE_TEMPLATE3_CTRL3_FIELD6_MASK    0x7F\n\n#define    RTL8367C_REG_ACL_RULE_TEMPLATE4_CTRL0    0x0610\n#define    RTL8367C_ACL_RULE_TEMPLATE4_CTRL0_FIELD1_OFFSET    8\n#define    RTL8367C_ACL_RULE_TEMPLATE4_CTRL0_FIELD1_MASK    0x7F00\n#define    RTL8367C_ACL_RULE_TEMPLATE4_CTRL0_FIELD0_OFFSET    0\n#define    RTL8367C_ACL_RULE_TEMPLATE4_CTRL0_FIELD0_MASK    0x7F\n\n#define    RTL8367C_REG_ACL_RULE_TEMPLATE4_CTRL1    0x0611\n#define    RTL8367C_ACL_RULE_TEMPLATE4_CTRL1_FIELD3_OFFSET    8\n#define    RTL8367C_ACL_RULE_TEMPLATE4_CTRL1_FIELD3_MASK    0x7F00\n#define    RTL8367C_ACL_RULE_TEMPLATE4_CTRL1_FIELD2_OFFSET    0\n#define    RTL8367C_ACL_RULE_TEMPLATE4_CTRL1_FIELD2_MASK    0x7F\n\n#define    RTL8367C_REG_ACL_RULE_TEMPLATE4_CTRL2    0x0612\n#define    RTL8367C_ACL_RULE_TEMPLATE4_CTRL2_FIELD5_OFFSET    8\n#define    RTL8367C_ACL_RULE_TEMPLATE4_CTRL2_FIELD5_MASK    0x7F00\n#define    RTL8367C_ACL_RULE_TEMPLATE4_CTRL2_FIELD4_OFFSET    0\n#define    RTL8367C_ACL_RULE_TEMPLATE4_CTRL2_FIELD4_MASK    0x7F\n\n#define    RTL8367C_REG_ACL_RULE_TEMPLATE4_CTRL3    0x0613\n#define    RTL8367C_ACL_RULE_TEMPLATE4_CTRL3_FIELD7_OFFSET    8\n#define    RTL8367C_ACL_RULE_TEMPLATE4_CTRL3_FIELD7_MASK    0x7F00\n#define    RTL8367C_ACL_RULE_TEMPLATE4_CTRL3_FIELD6_OFFSET    0\n#define    RTL8367C_ACL_RULE_TEMPLATE4_CTRL3_FIELD6_MASK    0x7F\n\n#define    RTL8367C_REG_ACL_ACTION_CTRL0    0x0614\n#define    RTL8367C_OP1_NOT_OFFSET    14\n#define    RTL8367C_OP1_NOT_MASK    0x4000\n#define    RTL8367C_ACT1_GPIO_OFFSET    13\n#define    RTL8367C_ACT1_GPIO_MASK    0x2000\n#define    RTL8367C_ACT1_FORWARD_OFFSET    12\n#define    RTL8367C_ACT1_FORWARD_MASK    0x1000\n#define    RTL8367C_ACT1_POLICING_OFFSET    11\n#define    RTL8367C_ACT1_POLICING_MASK    0x800\n#define    RTL8367C_ACT1_PRIORITY_OFFSET    10\n#define    RTL8367C_ACT1_PRIORITY_MASK    0x400\n#define    RTL8367C_ACT1_SVID_OFFSET    9\n#define    RTL8367C_ACT1_SVID_MASK    0x200\n#define    RTL8367C_ACT1_CVID_OFFSET    8\n#define    RTL8367C_ACT1_CVID_MASK    0x100\n#define    RTL8367C_OP0_NOT_OFFSET    6\n#define    RTL8367C_OP0_NOT_MASK    0x40\n#define    RTL8367C_ACT0_GPIO_OFFSET    5\n#define    RTL8367C_ACT0_GPIO_MASK    0x20\n#define    RTL8367C_ACT0_FORWARD_OFFSET    4\n#define    RTL8367C_ACT0_FORWARD_MASK    0x10\n#define    RTL8367C_ACT0_POLICING_OFFSET    3\n#define    RTL8367C_ACT0_POLICING_MASK    0x8\n#define    RTL8367C_ACT0_PRIORITY_OFFSET    2\n#define    RTL8367C_ACT0_PRIORITY_MASK    0x4\n#define    RTL8367C_ACT0_SVID_OFFSET    1\n#define    RTL8367C_ACT0_SVID_MASK    0x2\n#define    RTL8367C_ACT0_CVID_OFFSET    0\n#define    RTL8367C_ACT0_CVID_MASK    0x1\n\n#define    RTL8367C_REG_ACL_ACTION_CTRL1    0x0615\n#define    RTL8367C_OP3_NOT_OFFSET    14\n#define    RTL8367C_OP3_NOT_MASK    0x4000\n#define    RTL8367C_ACT3_GPIO_OFFSET    13\n#define    RTL8367C_ACT3_GPIO_MASK    0x2000\n#define    RTL8367C_ACT3_FORWARD_OFFSET    12\n#define    RTL8367C_ACT3_FORWARD_MASK    0x1000\n#define    RTL8367C_ACT3_POLICING_OFFSET    11\n#define    RTL8367C_ACT3_POLICING_MASK    0x800\n#define    RTL8367C_ACT3_PRIORITY_OFFSET    10\n#define    RTL8367C_ACT3_PRIORITY_MASK    0x400\n#define    RTL8367C_ACT3_SVID_OFFSET    9\n#define    RTL8367C_ACT3_SVID_MASK    0x200\n#define    RTL8367C_ACT3_CVID_OFFSET    8\n#define    RTL8367C_ACT3_CVID_MASK    0x100\n#define    RTL8367C_OP2_NOT_OFFSET    6\n#define    RTL8367C_OP2_NOT_MASK    0x40\n#define    RTL8367C_ACT2_GPIO_OFFSET    5\n#define    RTL8367C_ACT2_GPIO_MASK    0x20\n#define    RTL8367C_ACT2_FORWARD_OFFSET    4\n#define    RTL8367C_ACT2_FORWARD_MASK    0x10\n#define    RTL8367C_ACT2_POLICING_OFFSET    3\n#define    RTL8367C_ACT2_POLICING_MASK    0x8\n#define    RTL8367C_ACT2_PRIORITY_OFFSET    2\n#define    RTL8367C_ACT2_PRIORITY_MASK    0x4\n#define    RTL8367C_ACT2_SVID_OFFSET    1\n#define    RTL8367C_ACT2_SVID_MASK    0x2\n#define    RTL8367C_ACT2_CVID_OFFSET    0\n#define    RTL8367C_ACT2_CVID_MASK    0x1\n\n#define    RTL8367C_REG_ACL_ACTION_CTRL2    0x0616\n#define    RTL8367C_OP5_NOT_OFFSET    14\n#define    RTL8367C_OP5_NOT_MASK    0x4000\n#define    RTL8367C_ACT5_GPIO_OFFSET    13\n#define    RTL8367C_ACT5_GPIO_MASK    0x2000\n#define    RTL8367C_ACT5_FORWARD_OFFSET    12\n#define    RTL8367C_ACT5_FORWARD_MASK    0x1000\n#define    RTL8367C_ACT5_POLICING_OFFSET    11\n#define    RTL8367C_ACT5_POLICING_MASK    0x800\n#define    RTL8367C_ACT5_PRIORITY_OFFSET    10\n#define    RTL8367C_ACT5_PRIORITY_MASK    0x400\n#define    RTL8367C_ACT5_SVID_OFFSET    9\n#define    RTL8367C_ACT5_SVID_MASK    0x200\n#define    RTL8367C_ACT5_CVID_OFFSET    8\n#define    RTL8367C_ACT5_CVID_MASK    0x100\n#define    RTL8367C_OP4_NOT_OFFSET    6\n#define    RTL8367C_OP4_NOT_MASK    0x40\n#define    RTL8367C_ACT4_GPIO_OFFSET    5\n#define    RTL8367C_ACT4_GPIO_MASK    0x20\n#define    RTL8367C_ACT4_FORWARD_OFFSET    4\n#define    RTL8367C_ACT4_FORWARD_MASK    0x10\n#define    RTL8367C_ACT4_POLICING_OFFSET    3\n#define    RTL8367C_ACT4_POLICING_MASK    0x8\n#define    RTL8367C_ACT4_PRIORITY_OFFSET    2\n#define    RTL8367C_ACT4_PRIORITY_MASK    0x4\n#define    RTL8367C_ACT4_SVID_OFFSET    1\n#define    RTL8367C_ACT4_SVID_MASK    0x2\n#define    RTL8367C_ACT4_CVID_OFFSET    0\n#define    RTL8367C_ACT4_CVID_MASK    0x1\n\n#define    RTL8367C_REG_ACL_ACTION_CTRL3    0x0617\n#define    RTL8367C_OP7_NOT_OFFSET    14\n#define    RTL8367C_OP7_NOT_MASK    0x4000\n#define    RTL8367C_ACT7_GPIO_OFFSET    13\n#define    RTL8367C_ACT7_GPIO_MASK    0x2000\n#define    RTL8367C_ACT7_FORWARD_OFFSET    12\n#define    RTL8367C_ACT7_FORWARD_MASK    0x1000\n#define    RTL8367C_ACT7_POLICING_OFFSET    11\n#define    RTL8367C_ACT7_POLICING_MASK    0x800\n#define    RTL8367C_ACT7_PRIORITY_OFFSET    10\n#define    RTL8367C_ACT7_PRIORITY_MASK    0x400\n#define    RTL8367C_ACT7_SVID_OFFSET    9\n#define    RTL8367C_ACT7_SVID_MASK    0x200\n#define    RTL8367C_ACT7_CVID_OFFSET    8\n#define    RTL8367C_ACT7_CVID_MASK    0x100\n#define    RTL8367C_OP6_NOT_OFFSET    6\n#define    RTL8367C_OP6_NOT_MASK    0x40\n#define    RTL8367C_ACT6_GPIO_OFFSET    5\n#define    RTL8367C_ACT6_GPIO_MASK    0x20\n#define    RTL8367C_ACT6_FORWARD_OFFSET    4\n#define    RTL8367C_ACT6_FORWARD_MASK    0x10\n#define    RTL8367C_ACT6_POLICING_OFFSET    3\n#define    RTL8367C_ACT6_POLICING_MASK    0x8\n#define    RTL8367C_ACT6_PRIORITY_OFFSET    2\n#define    RTL8367C_ACT6_PRIORITY_MASK    0x4\n#define    RTL8367C_ACT6_SVID_OFFSET    1\n#define    RTL8367C_ACT6_SVID_MASK    0x2\n#define    RTL8367C_ACT6_CVID_OFFSET    0\n#define    RTL8367C_ACT6_CVID_MASK    0x1\n\n#define    RTL8367C_REG_ACL_ACTION_CTRL4    0x0618\n#define    RTL8367C_OP9_NOT_OFFSET    14\n#define    RTL8367C_OP9_NOT_MASK    0x4000\n#define    RTL8367C_ACT9_GPIO_OFFSET    13\n#define    RTL8367C_ACT9_GPIO_MASK    0x2000\n#define    RTL8367C_ACT9_FORWARD_OFFSET    12\n#define    RTL8367C_ACT9_FORWARD_MASK    0x1000\n#define    RTL8367C_ACT9_POLICING_OFFSET    11\n#define    RTL8367C_ACT9_POLICING_MASK    0x800\n#define    RTL8367C_ACT9_PRIORITY_OFFSET    10\n#define    RTL8367C_ACT9_PRIORITY_MASK    0x400\n#define    RTL8367C_ACT9_SVID_OFFSET    9\n#define    RTL8367C_ACT9_SVID_MASK    0x200\n#define    RTL8367C_ACT9_CVID_OFFSET    8\n#define    RTL8367C_ACT9_CVID_MASK    0x100\n#define    RTL8367C_OP8_NOT_OFFSET    6\n#define    RTL8367C_OP8_NOT_MASK    0x40\n#define    RTL8367C_ACT8_GPIO_OFFSET    5\n#define    RTL8367C_ACT8_GPIO_MASK    0x20\n#define    RTL8367C_ACT8_FORWARD_OFFSET    4\n#define    RTL8367C_ACT8_FORWARD_MASK    0x10\n#define    RTL8367C_ACT8_POLICING_OFFSET    3\n#define    RTL8367C_ACT8_POLICING_MASK    0x8\n#define    RTL8367C_ACT8_PRIORITY_OFFSET    2\n#define    RTL8367C_ACT8_PRIORITY_MASK    0x4\n#define    RTL8367C_ACT8_SVID_OFFSET    1\n#define    RTL8367C_ACT8_SVID_MASK    0x2\n#define    RTL8367C_ACT8_CVID_OFFSET    0\n#define    RTL8367C_ACT8_CVID_MASK    0x1\n\n#define    RTL8367C_REG_ACL_ACTION_CTRL5    0x0619\n#define    RTL8367C_OP11_NOT_OFFSET    14\n#define    RTL8367C_OP11_NOT_MASK    0x4000\n#define    RTL8367C_ACT11_GPIO_OFFSET    13\n#define    RTL8367C_ACT11_GPIO_MASK    0x2000\n#define    RTL8367C_ACT11_FORWARD_OFFSET    12\n#define    RTL8367C_ACT11_FORWARD_MASK    0x1000\n#define    RTL8367C_ACT11_POLICING_OFFSET    11\n#define    RTL8367C_ACT11_POLICING_MASK    0x800\n#define    RTL8367C_ACT11_PRIORITY_OFFSET    10\n#define    RTL8367C_ACT11_PRIORITY_MASK    0x400\n#define    RTL8367C_ACT11_SVID_OFFSET    9\n#define    RTL8367C_ACT11_SVID_MASK    0x200\n#define    RTL8367C_ACT11_CVID_OFFSET    8\n#define    RTL8367C_ACT11_CVID_MASK    0x100\n#define    RTL8367C_OP10_NOT_OFFSET    6\n#define    RTL8367C_OP10_NOT_MASK    0x40\n#define    RTL8367C_ACT10_GPIO_OFFSET    5\n#define    RTL8367C_ACT10_GPIO_MASK    0x20\n#define    RTL8367C_ACT10_FORWARD_OFFSET    4\n#define    RTL8367C_ACT10_FORWARD_MASK    0x10\n#define    RTL8367C_ACT10_POLICING_OFFSET    3\n#define    RTL8367C_ACT10_POLICING_MASK    0x8\n#define    RTL8367C_ACT10_PRIORITY_OFFSET    2\n#define    RTL8367C_ACT10_PRIORITY_MASK    0x4\n#define    RTL8367C_ACT10_SVID_OFFSET    1\n#define    RTL8367C_ACT10_SVID_MASK    0x2\n#define    RTL8367C_ACT10_CVID_OFFSET    0\n#define    RTL8367C_ACT10_CVID_MASK    0x1\n\n#define    RTL8367C_REG_ACL_ACTION_CTRL6    0x061a\n#define    RTL8367C_OP13_NOT_OFFSET    14\n#define    RTL8367C_OP13_NOT_MASK    0x4000\n#define    RTL8367C_ACT13_GPIO_OFFSET    13\n#define    RTL8367C_ACT13_GPIO_MASK    0x2000\n#define    RTL8367C_ACT13_FORWARD_OFFSET    12\n#define    RTL8367C_ACT13_FORWARD_MASK    0x1000\n#define    RTL8367C_ACT13_POLICING_OFFSET    11\n#define    RTL8367C_ACT13_POLICING_MASK    0x800\n#define    RTL8367C_ACT13_PRIORITY_OFFSET    10\n#define    RTL8367C_ACT13_PRIORITY_MASK    0x400\n#define    RTL8367C_ACT13_SVID_OFFSET    9\n#define    RTL8367C_ACT13_SVID_MASK    0x200\n#define    RTL8367C_ACT13_CVID_OFFSET    8\n#define    RTL8367C_ACT13_CVID_MASK    0x100\n#define    RTL8367C_OP12_NOT_OFFSET    6\n#define    RTL8367C_OP12_NOT_MASK    0x40\n#define    RTL8367C_ACT12_GPIO_OFFSET    5\n#define    RTL8367C_ACT12_GPIO_MASK    0x20\n#define    RTL8367C_ACT12_FORWARD_OFFSET    4\n#define    RTL8367C_ACT12_FORWARD_MASK    0x10\n#define    RTL8367C_ACT12_POLICING_OFFSET    3\n#define    RTL8367C_ACT12_POLICING_MASK    0x8\n#define    RTL8367C_ACT12_PRIORITY_OFFSET    2\n#define    RTL8367C_ACT12_PRIORITY_MASK    0x4\n#define    RTL8367C_ACT12_SVID_OFFSET    1\n#define    RTL8367C_ACT12_SVID_MASK    0x2\n#define    RTL8367C_ACT12_CVID_OFFSET    0\n#define    RTL8367C_ACT12_CVID_MASK    0x1\n\n#define    RTL8367C_REG_ACL_ACTION_CTRL7    0x061b\n#define    RTL8367C_OP15_NOT_OFFSET    14\n#define    RTL8367C_OP15_NOT_MASK    0x4000\n#define    RTL8367C_ACT15_GPIO_OFFSET    13\n#define    RTL8367C_ACT15_GPIO_MASK    0x2000\n#define    RTL8367C_ACT15_FORWARD_OFFSET    12\n#define    RTL8367C_ACT15_FORWARD_MASK    0x1000\n#define    RTL8367C_ACT15_POLICING_OFFSET    11\n#define    RTL8367C_ACT15_POLICING_MASK    0x800\n#define    RTL8367C_ACT15_PRIORITY_OFFSET    10\n#define    RTL8367C_ACT15_PRIORITY_MASK    0x400\n#define    RTL8367C_ACT15_SVID_OFFSET    9\n#define    RTL8367C_ACT15_SVID_MASK    0x200\n#define    RTL8367C_ACT15_CVID_OFFSET    8\n#define    RTL8367C_ACT15_CVID_MASK    0x100\n#define    RTL8367C_OP14_NOT_OFFSET    6\n#define    RTL8367C_OP14_NOT_MASK    0x40\n#define    RTL8367C_ACT14_GPIO_OFFSET    5\n#define    RTL8367C_ACT14_GPIO_MASK    0x20\n#define    RTL8367C_ACT14_FORWARD_OFFSET    4\n#define    RTL8367C_ACT14_FORWARD_MASK    0x10\n#define    RTL8367C_ACT14_POLICING_OFFSET    3\n#define    RTL8367C_ACT14_POLICING_MASK    0x8\n#define    RTL8367C_ACT14_PRIORITY_OFFSET    2\n#define    RTL8367C_ACT14_PRIORITY_MASK    0x4\n#define    RTL8367C_ACT14_SVID_OFFSET    1\n#define    RTL8367C_ACT14_SVID_MASK    0x2\n#define    RTL8367C_ACT14_CVID_OFFSET    0\n#define    RTL8367C_ACT14_CVID_MASK    0x1\n\n#define    RTL8367C_REG_ACL_ACTION_CTRL8    0x061c\n#define    RTL8367C_OP17_NOT_OFFSET    14\n#define    RTL8367C_OP17_NOT_MASK    0x4000\n#define    RTL8367C_ACT17_GPIO_OFFSET    13\n#define    RTL8367C_ACT17_GPIO_MASK    0x2000\n#define    RTL8367C_ACT17_FORWARD_OFFSET    12\n#define    RTL8367C_ACT17_FORWARD_MASK    0x1000\n#define    RTL8367C_ACT17_POLICING_OFFSET    11\n#define    RTL8367C_ACT17_POLICING_MASK    0x800\n#define    RTL8367C_ACT17_PRIORITY_OFFSET    10\n#define    RTL8367C_ACT17_PRIORITY_MASK    0x400\n#define    RTL8367C_ACT17_SVID_OFFSET    9\n#define    RTL8367C_ACT17_SVID_MASK    0x200\n#define    RTL8367C_ACT17_CVID_OFFSET    8\n#define    RTL8367C_ACT17_CVID_MASK    0x100\n#define    RTL8367C_OP16_NOT_OFFSET    6\n#define    RTL8367C_OP16_NOT_MASK    0x40\n#define    RTL8367C_ACT16_GPIO_OFFSET    5\n#define    RTL8367C_ACT16_GPIO_MASK    0x20\n#define    RTL8367C_ACT16_FORWARD_OFFSET    4\n#define    RTL8367C_ACT16_FORWARD_MASK    0x10\n#define    RTL8367C_ACT16_POLICING_OFFSET    3\n#define    RTL8367C_ACT16_POLICING_MASK    0x8\n#define    RTL8367C_ACT16_PRIORITY_OFFSET    2\n#define    RTL8367C_ACT16_PRIORITY_MASK    0x4\n#define    RTL8367C_ACT16_SVID_OFFSET    1\n#define    RTL8367C_ACT16_SVID_MASK    0x2\n#define    RTL8367C_ACT16_CVID_OFFSET    0\n#define    RTL8367C_ACT16_CVID_MASK    0x1\n\n#define    RTL8367C_REG_ACL_ACTION_CTRL9    0x061d\n#define    RTL8367C_OP19_NOT_OFFSET    14\n#define    RTL8367C_OP19_NOT_MASK    0x4000\n#define    RTL8367C_ACT19_GPIO_OFFSET    13\n#define    RTL8367C_ACT19_GPIO_MASK    0x2000\n#define    RTL8367C_ACT19_FORWARD_OFFSET    12\n#define    RTL8367C_ACT19_FORWARD_MASK    0x1000\n#define    RTL8367C_ACT19_POLICING_OFFSET    11\n#define    RTL8367C_ACT19_POLICING_MASK    0x800\n#define    RTL8367C_ACT19_PRIORITY_OFFSET    10\n#define    RTL8367C_ACT19_PRIORITY_MASK    0x400\n#define    RTL8367C_ACT19_SVID_OFFSET    9\n#define    RTL8367C_ACT19_SVID_MASK    0x200\n#define    RTL8367C_ACT19_CVID_OFFSET    8\n#define    RTL8367C_ACT19_CVID_MASK    0x100\n#define    RTL8367C_OP18_NOT_OFFSET    6\n#define    RTL8367C_OP18_NOT_MASK    0x40\n#define    RTL8367C_ACT18_GPIO_OFFSET    5\n#define    RTL8367C_ACT18_GPIO_MASK    0x20\n#define    RTL8367C_ACT18_FORWARD_OFFSET    4\n#define    RTL8367C_ACT18_FORWARD_MASK    0x10\n#define    RTL8367C_ACT18_POLICING_OFFSET    3\n#define    RTL8367C_ACT18_POLICING_MASK    0x8\n#define    RTL8367C_ACT18_PRIORITY_OFFSET    2\n#define    RTL8367C_ACT18_PRIORITY_MASK    0x4\n#define    RTL8367C_ACT18_SVID_OFFSET    1\n#define    RTL8367C_ACT18_SVID_MASK    0x2\n#define    RTL8367C_ACT18_CVID_OFFSET    0\n#define    RTL8367C_ACT18_CVID_MASK    0x1\n\n#define    RTL8367C_REG_ACL_ACTION_CTRL10    0x061e\n#define    RTL8367C_OP21_NOT_OFFSET    14\n#define    RTL8367C_OP21_NOT_MASK    0x4000\n#define    RTL8367C_ACT21_GPIO_OFFSET    13\n#define    RTL8367C_ACT21_GPIO_MASK    0x2000\n#define    RTL8367C_ACT21_FORWARD_OFFSET    12\n#define    RTL8367C_ACT21_FORWARD_MASK    0x1000\n#define    RTL8367C_ACT21_POLICING_OFFSET    11\n#define    RTL8367C_ACT21_POLICING_MASK    0x800\n#define    RTL8367C_ACT21_PRIORITY_OFFSET    10\n#define    RTL8367C_ACT21_PRIORITY_MASK    0x400\n#define    RTL8367C_ACT21_SVID_OFFSET    9\n#define    RTL8367C_ACT21_SVID_MASK    0x200\n#define    RTL8367C_ACT21_CVID_OFFSET    8\n#define    RTL8367C_ACT21_CVID_MASK    0x100\n#define    RTL8367C_OP20_NOT_OFFSET    6\n#define    RTL8367C_OP20_NOT_MASK    0x40\n#define    RTL8367C_ACT20_GPIO_OFFSET    5\n#define    RTL8367C_ACT20_GPIO_MASK    0x20\n#define    RTL8367C_ACT20_FORWARD_OFFSET    4\n#define    RTL8367C_ACT20_FORWARD_MASK    0x10\n#define    RTL8367C_ACT20_POLICING_OFFSET    3\n#define    RTL8367C_ACT20_POLICING_MASK    0x8\n#define    RTL8367C_ACT20_PRIORITY_OFFSET    2\n#define    RTL8367C_ACT20_PRIORITY_MASK    0x4\n#define    RTL8367C_ACT20_SVID_OFFSET    1\n#define    RTL8367C_ACT20_SVID_MASK    0x2\n#define    RTL8367C_ACT20_CVID_OFFSET    0\n#define    RTL8367C_ACT20_CVID_MASK    0x1\n\n#define    RTL8367C_REG_ACL_ACTION_CTRL11    0x061f\n#define    RTL8367C_OP23_NOT_OFFSET    14\n#define    RTL8367C_OP23_NOT_MASK    0x4000\n#define    RTL8367C_ACT23_GPIO_OFFSET    13\n#define    RTL8367C_ACT23_GPIO_MASK    0x2000\n#define    RTL8367C_ACT23_FORWARD_OFFSET    12\n#define    RTL8367C_ACT23_FORWARD_MASK    0x1000\n#define    RTL8367C_ACT23_POLICING_OFFSET    11\n#define    RTL8367C_ACT23_POLICING_MASK    0x800\n#define    RTL8367C_ACT23_PRIORITY_OFFSET    10\n#define    RTL8367C_ACT23_PRIORITY_MASK    0x400\n#define    RTL8367C_ACT23_SVID_OFFSET    9\n#define    RTL8367C_ACT23_SVID_MASK    0x200\n#define    RTL8367C_ACT23_CVID_OFFSET    8\n#define    RTL8367C_ACT23_CVID_MASK    0x100\n#define    RTL8367C_OP22_NOT_OFFSET    6\n#define    RTL8367C_OP22_NOT_MASK    0x40\n#define    RTL8367C_ACT22_GPIO_OFFSET    5\n#define    RTL8367C_ACT22_GPIO_MASK    0x20\n#define    RTL8367C_ACT22_FORWARD_OFFSET    4\n#define    RTL8367C_ACT22_FORWARD_MASK    0x10\n#define    RTL8367C_ACT22_POLICING_OFFSET    3\n#define    RTL8367C_ACT22_POLICING_MASK    0x8\n#define    RTL8367C_ACT22_PRIORITY_OFFSET    2\n#define    RTL8367C_ACT22_PRIORITY_MASK    0x4\n#define    RTL8367C_ACT22_SVID_OFFSET    1\n#define    RTL8367C_ACT22_SVID_MASK    0x2\n#define    RTL8367C_ACT22_CVID_OFFSET    0\n#define    RTL8367C_ACT22_CVID_MASK    0x1\n\n#define    RTL8367C_REG_ACL_ACTION_CTRL12    0x0620\n#define    RTL8367C_OP25_NOT_OFFSET    14\n#define    RTL8367C_OP25_NOT_MASK    0x4000\n#define    RTL8367C_ACT25_GPIO_OFFSET    13\n#define    RTL8367C_ACT25_GPIO_MASK    0x2000\n#define    RTL8367C_ACT25_FORWARD_OFFSET    12\n#define    RTL8367C_ACT25_FORWARD_MASK    0x1000\n#define    RTL8367C_ACT25_POLICING_OFFSET    11\n#define    RTL8367C_ACT25_POLICING_MASK    0x800\n#define    RTL8367C_ACT25_PRIORITY_OFFSET    10\n#define    RTL8367C_ACT25_PRIORITY_MASK    0x400\n#define    RTL8367C_ACT25_SVID_OFFSET    9\n#define    RTL8367C_ACT25_SVID_MASK    0x200\n#define    RTL8367C_ACT25_CVID_OFFSET    8\n#define    RTL8367C_ACT25_CVID_MASK    0x100\n#define    RTL8367C_OP24_NOT_OFFSET    6\n#define    RTL8367C_OP24_NOT_MASK    0x40\n#define    RTL8367C_ACT24_GPIO_OFFSET    5\n#define    RTL8367C_ACT24_GPIO_MASK    0x20\n#define    RTL8367C_ACT24_FORWARD_OFFSET    4\n#define    RTL8367C_ACT24_FORWARD_MASK    0x10\n#define    RTL8367C_ACT24_POLICING_OFFSET    3\n#define    RTL8367C_ACT24_POLICING_MASK    0x8\n#define    RTL8367C_ACT24_PRIORITY_OFFSET    2\n#define    RTL8367C_ACT24_PRIORITY_MASK    0x4\n#define    RTL8367C_ACT24_SVID_OFFSET    1\n#define    RTL8367C_ACT24_SVID_MASK    0x2\n#define    RTL8367C_ACT24_CVID_OFFSET    0\n#define    RTL8367C_ACT24_CVID_MASK    0x1\n\n#define    RTL8367C_REG_ACL_ACTION_CTRL13    0x0621\n#define    RTL8367C_OP27_NOT_OFFSET    14\n#define    RTL8367C_OP27_NOT_MASK    0x4000\n#define    RTL8367C_ACT27_GPIO_OFFSET    13\n#define    RTL8367C_ACT27_GPIO_MASK    0x2000\n#define    RTL8367C_ACT27_FORWARD_OFFSET    12\n#define    RTL8367C_ACT27_FORWARD_MASK    0x1000\n#define    RTL8367C_ACT27_POLICING_OFFSET    11\n#define    RTL8367C_ACT27_POLICING_MASK    0x800\n#define    RTL8367C_ACT27_PRIORITY_OFFSET    10\n#define    RTL8367C_ACT27_PRIORITY_MASK    0x400\n#define    RTL8367C_ACT27_SVID_OFFSET    9\n#define    RTL8367C_ACT27_SVID_MASK    0x200\n#define    RTL8367C_ACT27_CVID_OFFSET    8\n#define    RTL8367C_ACT27_CVID_MASK    0x100\n#define    RTL8367C_OP26_NOT_OFFSET    6\n#define    RTL8367C_OP26_NOT_MASK    0x40\n#define    RTL8367C_ACT26_GPIO_OFFSET    5\n#define    RTL8367C_ACT26_GPIO_MASK    0x20\n#define    RTL8367C_ACT26_FORWARD_OFFSET    4\n#define    RTL8367C_ACT26_FORWARD_MASK    0x10\n#define    RTL8367C_ACT26_POLICING_OFFSET    3\n#define    RTL8367C_ACT26_POLICING_MASK    0x8\n#define    RTL8367C_ACT26_PRIORITY_OFFSET    2\n#define    RTL8367C_ACT26_PRIORITY_MASK    0x4\n#define    RTL8367C_ACT26_SVID_OFFSET    1\n#define    RTL8367C_ACT26_SVID_MASK    0x2\n#define    RTL8367C_ACT26_CVID_OFFSET    0\n#define    RTL8367C_ACT26_CVID_MASK    0x1\n\n#define    RTL8367C_REG_ACL_ACTION_CTRL14    0x0622\n#define    RTL8367C_OP29_NOT_OFFSET    14\n#define    RTL8367C_OP29_NOT_MASK    0x4000\n#define    RTL8367C_ACT29_GPIO_OFFSET    13\n#define    RTL8367C_ACT29_GPIO_MASK    0x2000\n#define    RTL8367C_ACT29_FORWARD_OFFSET    12\n#define    RTL8367C_ACT29_FORWARD_MASK    0x1000\n#define    RTL8367C_ACT29_POLICING_OFFSET    11\n#define    RTL8367C_ACT29_POLICING_MASK    0x800\n#define    RTL8367C_ACT29_PRIORITY_OFFSET    10\n#define    RTL8367C_ACT29_PRIORITY_MASK    0x400\n#define    RTL8367C_ACT29_SVID_OFFSET    9\n#define    RTL8367C_ACT29_SVID_MASK    0x200\n#define    RTL8367C_ACT29_CVID_OFFSET    8\n#define    RTL8367C_ACT29_CVID_MASK    0x100\n#define    RTL8367C_OP28_NOT_OFFSET    6\n#define    RTL8367C_OP28_NOT_MASK    0x40\n#define    RTL8367C_ACT28_GPIO_OFFSET    5\n#define    RTL8367C_ACT28_GPIO_MASK    0x20\n#define    RTL8367C_ACT28_FORWARD_OFFSET    4\n#define    RTL8367C_ACT28_FORWARD_MASK    0x10\n#define    RTL8367C_ACT28_POLICING_OFFSET    3\n#define    RTL8367C_ACT28_POLICING_MASK    0x8\n#define    RTL8367C_ACT28_PRIORITY_OFFSET    2\n#define    RTL8367C_ACT28_PRIORITY_MASK    0x4\n#define    RTL8367C_ACT28_SVID_OFFSET    1\n#define    RTL8367C_ACT28_SVID_MASK    0x2\n#define    RTL8367C_ACT28_CVID_OFFSET    0\n#define    RTL8367C_ACT28_CVID_MASK    0x1\n\n#define    RTL8367C_REG_ACL_ACTION_CTRL15    0x0623\n#define    RTL8367C_OP31_NOT_OFFSET    14\n#define    RTL8367C_OP31_NOT_MASK    0x4000\n#define    RTL8367C_ACT31_GPIO_OFFSET    13\n#define    RTL8367C_ACT31_GPIO_MASK    0x2000\n#define    RTL8367C_ACT31_FORWARD_OFFSET    12\n#define    RTL8367C_ACT31_FORWARD_MASK    0x1000\n#define    RTL8367C_ACT31_POLICING_OFFSET    11\n#define    RTL8367C_ACT31_POLICING_MASK    0x800\n#define    RTL8367C_ACT31_PRIORITY_OFFSET    10\n#define    RTL8367C_ACT31_PRIORITY_MASK    0x400\n#define    RTL8367C_ACT31_SVID_OFFSET    9\n#define    RTL8367C_ACT31_SVID_MASK    0x200\n#define    RTL8367C_ACT31_CVID_OFFSET    8\n#define    RTL8367C_ACT31_CVID_MASK    0x100\n#define    RTL8367C_OP30_NOT_OFFSET    6\n#define    RTL8367C_OP30_NOT_MASK    0x40\n#define    RTL8367C_ACT30_GPIO_OFFSET    5\n#define    RTL8367C_ACT30_GPIO_MASK    0x20\n#define    RTL8367C_ACT30_FORWARD_OFFSET    4\n#define    RTL8367C_ACT30_FORWARD_MASK    0x10\n#define    RTL8367C_ACT30_POLICING_OFFSET    3\n#define    RTL8367C_ACT30_POLICING_MASK    0x8\n#define    RTL8367C_ACT30_PRIORITY_OFFSET    2\n#define    RTL8367C_ACT30_PRIORITY_MASK    0x4\n#define    RTL8367C_ACT30_SVID_OFFSET    1\n#define    RTL8367C_ACT30_SVID_MASK    0x2\n#define    RTL8367C_ACT30_CVID_OFFSET    0\n#define    RTL8367C_ACT30_CVID_MASK    0x1\n\n#define    RTL8367C_REG_ACL_ACTION_CTRL16    0x0624\n#define    RTL8367C_OP33_NOT_OFFSET    14\n#define    RTL8367C_OP33_NOT_MASK    0x4000\n#define    RTL8367C_ACT33_GPIO_OFFSET    13\n#define    RTL8367C_ACT33_GPIO_MASK    0x2000\n#define    RTL8367C_ACT33_FORWARD_OFFSET    12\n#define    RTL8367C_ACT33_FORWARD_MASK    0x1000\n#define    RTL8367C_ACT33_POLICING_OFFSET    11\n#define    RTL8367C_ACT33_POLICING_MASK    0x800\n#define    RTL8367C_ACT33_PRIORITY_OFFSET    10\n#define    RTL8367C_ACT33_PRIORITY_MASK    0x400\n#define    RTL8367C_ACT33_SVID_OFFSET    9\n#define    RTL8367C_ACT33_SVID_MASK    0x200\n#define    RTL8367C_ACT33_CVID_OFFSET    8\n#define    RTL8367C_ACT33_CVID_MASK    0x100\n#define    RTL8367C_OP32_NOT_OFFSET    6\n#define    RTL8367C_OP32_NOT_MASK    0x40\n#define    RTL8367C_ACT32_GPIO_OFFSET    5\n#define    RTL8367C_ACT32_GPIO_MASK    0x20\n#define    RTL8367C_ACT32_FORWARD_OFFSET    4\n#define    RTL8367C_ACT32_FORWARD_MASK    0x10\n#define    RTL8367C_ACT32_POLICING_OFFSET    3\n#define    RTL8367C_ACT32_POLICING_MASK    0x8\n#define    RTL8367C_ACT32_PRIORITY_OFFSET    2\n#define    RTL8367C_ACT32_PRIORITY_MASK    0x4\n#define    RTL8367C_ACT32_SVID_OFFSET    1\n#define    RTL8367C_ACT32_SVID_MASK    0x2\n#define    RTL8367C_ACT32_CVID_OFFSET    0\n#define    RTL8367C_ACT32_CVID_MASK    0x1\n\n#define    RTL8367C_REG_ACL_ACTION_CTRL17    0x0625\n#define    RTL8367C_OP35_NOT_OFFSET    14\n#define    RTL8367C_OP35_NOT_MASK    0x4000\n#define    RTL8367C_ACT35_GPIO_OFFSET    13\n#define    RTL8367C_ACT35_GPIO_MASK    0x2000\n#define    RTL8367C_ACT35_FORWARD_OFFSET    12\n#define    RTL8367C_ACT35_FORWARD_MASK    0x1000\n#define    RTL8367C_ACT35_POLICING_OFFSET    11\n#define    RTL8367C_ACT35_POLICING_MASK    0x800\n#define    RTL8367C_ACT35_PRIORITY_OFFSET    10\n#define    RTL8367C_ACT35_PRIORITY_MASK    0x400\n#define    RTL8367C_ACT35_SVID_OFFSET    9\n#define    RTL8367C_ACT35_SVID_MASK    0x200\n#define    RTL8367C_ACT35_CVID_OFFSET    8\n#define    RTL8367C_ACT35_CVID_MASK    0x100\n#define    RTL8367C_OP34_NOT_OFFSET    6\n#define    RTL8367C_OP34_NOT_MASK    0x40\n#define    RTL8367C_ACT34_GPIO_OFFSET    5\n#define    RTL8367C_ACT34_GPIO_MASK    0x20\n#define    RTL8367C_ACT34_FORWARD_OFFSET    4\n#define    RTL8367C_ACT34_FORWARD_MASK    0x10\n#define    RTL8367C_ACT34_POLICING_OFFSET    3\n#define    RTL8367C_ACT34_POLICING_MASK    0x8\n#define    RTL8367C_ACT34_PRIORITY_OFFSET    2\n#define    RTL8367C_ACT34_PRIORITY_MASK    0x4\n#define    RTL8367C_ACT34_SVID_OFFSET    1\n#define    RTL8367C_ACT34_SVID_MASK    0x2\n#define    RTL8367C_ACT34_CVID_OFFSET    0\n#define    RTL8367C_ACT34_CVID_MASK    0x1\n\n#define    RTL8367C_REG_ACL_ACTION_CTRL18    0x0626\n#define    RTL8367C_OP37_NOT_OFFSET    14\n#define    RTL8367C_OP37_NOT_MASK    0x4000\n#define    RTL8367C_ACT37_GPIO_OFFSET    13\n#define    RTL8367C_ACT37_GPIO_MASK    0x2000\n#define    RTL8367C_ACT37_FORWARD_OFFSET    12\n#define    RTL8367C_ACT37_FORWARD_MASK    0x1000\n#define    RTL8367C_ACT37_POLICING_OFFSET    11\n#define    RTL8367C_ACT37_POLICING_MASK    0x800\n#define    RTL8367C_ACT37_PRIORITY_OFFSET    10\n#define    RTL8367C_ACT37_PRIORITY_MASK    0x400\n#define    RTL8367C_ACT37_SVID_OFFSET    9\n#define    RTL8367C_ACT37_SVID_MASK    0x200\n#define    RTL8367C_ACT37_CVID_OFFSET    8\n#define    RTL8367C_ACT37_CVID_MASK    0x100\n#define    RTL8367C_OP36_NOT_OFFSET    6\n#define    RTL8367C_OP36_NOT_MASK    0x40\n#define    RTL8367C_ACT36_GPIO_OFFSET    5\n#define    RTL8367C_ACT36_GPIO_MASK    0x20\n#define    RTL8367C_ACT36_FORWARD_OFFSET    4\n#define    RTL8367C_ACT36_FORWARD_MASK    0x10\n#define    RTL8367C_ACT36_POLICING_OFFSET    3\n#define    RTL8367C_ACT36_POLICING_MASK    0x8\n#define    RTL8367C_ACT36_PRIORITY_OFFSET    2\n#define    RTL8367C_ACT36_PRIORITY_MASK    0x4\n#define    RTL8367C_ACT36_SVID_OFFSET    1\n#define    RTL8367C_ACT36_SVID_MASK    0x2\n#define    RTL8367C_ACT36_CVID_OFFSET    0\n#define    RTL8367C_ACT36_CVID_MASK    0x1\n\n#define    RTL8367C_REG_ACL_ACTION_CTRL19    0x0627\n#define    RTL8367C_OP39_NOT_OFFSET    14\n#define    RTL8367C_OP39_NOT_MASK    0x4000\n#define    RTL8367C_ACT39_GPIO_OFFSET    13\n#define    RTL8367C_ACT39_GPIO_MASK    0x2000\n#define    RTL8367C_ACT39_FORWARD_OFFSET    12\n#define    RTL8367C_ACT39_FORWARD_MASK    0x1000\n#define    RTL8367C_ACT39_POLICING_OFFSET    11\n#define    RTL8367C_ACT39_POLICING_MASK    0x800\n#define    RTL8367C_ACT39_PRIORITY_OFFSET    10\n#define    RTL8367C_ACT39_PRIORITY_MASK    0x400\n#define    RTL8367C_ACT39_SVID_OFFSET    9\n#define    RTL8367C_ACT39_SVID_MASK    0x200\n#define    RTL8367C_ACT39_CVID_OFFSET    8\n#define    RTL8367C_ACT39_CVID_MASK    0x100\n#define    RTL8367C_OP38_NOT_OFFSET    6\n#define    RTL8367C_OP38_NOT_MASK    0x40\n#define    RTL8367C_ACT38_GPIO_OFFSET    5\n#define    RTL8367C_ACT38_GPIO_MASK    0x20\n#define    RTL8367C_ACT38_FORWARD_OFFSET    4\n#define    RTL8367C_ACT38_FORWARD_MASK    0x10\n#define    RTL8367C_ACT38_POLICING_OFFSET    3\n#define    RTL8367C_ACT38_POLICING_MASK    0x8\n#define    RTL8367C_ACT38_PRIORITY_OFFSET    2\n#define    RTL8367C_ACT38_PRIORITY_MASK    0x4\n#define    RTL8367C_ACT38_SVID_OFFSET    1\n#define    RTL8367C_ACT38_SVID_MASK    0x2\n#define    RTL8367C_ACT38_CVID_OFFSET    0\n#define    RTL8367C_ACT38_CVID_MASK    0x1\n\n#define    RTL8367C_REG_ACL_ACTION_CTRL20    0x0628\n#define    RTL8367C_OP41_NOT_OFFSET    14\n#define    RTL8367C_OP41_NOT_MASK    0x4000\n#define    RTL8367C_ACT41_GPIO_OFFSET    13\n#define    RTL8367C_ACT41_GPIO_MASK    0x2000\n#define    RTL8367C_ACT41_FORWARD_OFFSET    12\n#define    RTL8367C_ACT41_FORWARD_MASK    0x1000\n#define    RTL8367C_ACT41_POLICING_OFFSET    11\n#define    RTL8367C_ACT41_POLICING_MASK    0x800\n#define    RTL8367C_ACT41_PRIORITY_OFFSET    10\n#define    RTL8367C_ACT41_PRIORITY_MASK    0x400\n#define    RTL8367C_ACT41_SVID_OFFSET    9\n#define    RTL8367C_ACT41_SVID_MASK    0x200\n#define    RTL8367C_ACT41_CVID_OFFSET    8\n#define    RTL8367C_ACT41_CVID_MASK    0x100\n#define    RTL8367C_OP40_NOT_OFFSET    6\n#define    RTL8367C_OP40_NOT_MASK    0x40\n#define    RTL8367C_ACT40_GPIO_OFFSET    5\n#define    RTL8367C_ACT40_GPIO_MASK    0x20\n#define    RTL8367C_ACT40_FORWARD_OFFSET    4\n#define    RTL8367C_ACT40_FORWARD_MASK    0x10\n#define    RTL8367C_ACT40_POLICING_OFFSET    3\n#define    RTL8367C_ACT40_POLICING_MASK    0x8\n#define    RTL8367C_ACT40_PRIORITY_OFFSET    2\n#define    RTL8367C_ACT40_PRIORITY_MASK    0x4\n#define    RTL8367C_ACT40_SVID_OFFSET    1\n#define    RTL8367C_ACT40_SVID_MASK    0x2\n#define    RTL8367C_ACT40_CVID_OFFSET    0\n#define    RTL8367C_ACT40_CVID_MASK    0x1\n\n#define    RTL8367C_REG_ACL_ACTION_CTRL21    0x0629\n#define    RTL8367C_OP43_NOT_OFFSET    14\n#define    RTL8367C_OP43_NOT_MASK    0x4000\n#define    RTL8367C_ACT43_GPIO_OFFSET    13\n#define    RTL8367C_ACT43_GPIO_MASK    0x2000\n#define    RTL8367C_ACT43_FORWARD_OFFSET    12\n#define    RTL8367C_ACT43_FORWARD_MASK    0x1000\n#define    RTL8367C_ACT43_POLICING_OFFSET    11\n#define    RTL8367C_ACT43_POLICING_MASK    0x800\n#define    RTL8367C_ACT43_PRIORITY_OFFSET    10\n#define    RTL8367C_ACT43_PRIORITY_MASK    0x400\n#define    RTL8367C_ACT43_SVID_OFFSET    9\n#define    RTL8367C_ACT43_SVID_MASK    0x200\n#define    RTL8367C_ACT43_CVID_OFFSET    8\n#define    RTL8367C_ACT43_CVID_MASK    0x100\n#define    RTL8367C_OP42_NOT_OFFSET    6\n#define    RTL8367C_OP42_NOT_MASK    0x40\n#define    RTL8367C_ACT42_GPIO_OFFSET    5\n#define    RTL8367C_ACT42_GPIO_MASK    0x20\n#define    RTL8367C_ACT42_FORWARD_OFFSET    4\n#define    RTL8367C_ACT42_FORWARD_MASK    0x10\n#define    RTL8367C_ACT42_POLICING_OFFSET    3\n#define    RTL8367C_ACT42_POLICING_MASK    0x8\n#define    RTL8367C_ACT42_PRIORITY_OFFSET    2\n#define    RTL8367C_ACT42_PRIORITY_MASK    0x4\n#define    RTL8367C_ACT42_SVID_OFFSET    1\n#define    RTL8367C_ACT42_SVID_MASK    0x2\n#define    RTL8367C_ACT42_CVID_OFFSET    0\n#define    RTL8367C_ACT42_CVID_MASK    0x1\n\n#define    RTL8367C_REG_ACL_ACTION_CTRL22    0x062a\n#define    RTL8367C_OP45_NOT_OFFSET    14\n#define    RTL8367C_OP45_NOT_MASK    0x4000\n#define    RTL8367C_ACT45_GPIO_OFFSET    13\n#define    RTL8367C_ACT45_GPIO_MASK    0x2000\n#define    RTL8367C_ACT45_FORWARD_OFFSET    12\n#define    RTL8367C_ACT45_FORWARD_MASK    0x1000\n#define    RTL8367C_ACT45_POLICING_OFFSET    11\n#define    RTL8367C_ACT45_POLICING_MASK    0x800\n#define    RTL8367C_ACT45_PRIORITY_OFFSET    10\n#define    RTL8367C_ACT45_PRIORITY_MASK    0x400\n#define    RTL8367C_ACT45_SVID_OFFSET    9\n#define    RTL8367C_ACT45_SVID_MASK    0x200\n#define    RTL8367C_ACT45_CVID_OFFSET    8\n#define    RTL8367C_ACT45_CVID_MASK    0x100\n#define    RTL8367C_OP44_NOT_OFFSET    6\n#define    RTL8367C_OP44_NOT_MASK    0x40\n#define    RTL8367C_ACT44_GPIO_OFFSET    5\n#define    RTL8367C_ACT44_GPIO_MASK    0x20\n#define    RTL8367C_ACT44_FORWARD_OFFSET    4\n#define    RTL8367C_ACT44_FORWARD_MASK    0x10\n#define    RTL8367C_ACT44_POLICING_OFFSET    3\n#define    RTL8367C_ACT44_POLICING_MASK    0x8\n#define    RTL8367C_ACT44_PRIORITY_OFFSET    2\n#define    RTL8367C_ACT44_PRIORITY_MASK    0x4\n#define    RTL8367C_ACT44_SVID_OFFSET    1\n#define    RTL8367C_ACT44_SVID_MASK    0x2\n#define    RTL8367C_ACT44_CVID_OFFSET    0\n#define    RTL8367C_ACT44_CVID_MASK    0x1\n\n#define    RTL8367C_REG_ACL_ACTION_CTRL23    0x062b\n#define    RTL8367C_OP47_NOT_OFFSET    14\n#define    RTL8367C_OP47_NOT_MASK    0x4000\n#define    RTL8367C_ACT47_GPIO_OFFSET    13\n#define    RTL8367C_ACT47_GPIO_MASK    0x2000\n#define    RTL8367C_ACT47_FORWARD_OFFSET    12\n#define    RTL8367C_ACT47_FORWARD_MASK    0x1000\n#define    RTL8367C_ACT47_POLICING_OFFSET    11\n#define    RTL8367C_ACT47_POLICING_MASK    0x800\n#define    RTL8367C_ACT47_PRIORITY_OFFSET    10\n#define    RTL8367C_ACT47_PRIORITY_MASK    0x400\n#define    RTL8367C_ACT47_SVID_OFFSET    9\n#define    RTL8367C_ACT47_SVID_MASK    0x200\n#define    RTL8367C_ACT47_CVID_OFFSET    8\n#define    RTL8367C_ACT47_CVID_MASK    0x100\n#define    RTL8367C_OP46_NOT_OFFSET    6\n#define    RTL8367C_OP46_NOT_MASK    0x40\n#define    RTL8367C_ACT46_GPIO_OFFSET    5\n#define    RTL8367C_ACT46_GPIO_MASK    0x20\n#define    RTL8367C_ACT46_FORWARD_OFFSET    4\n#define    RTL8367C_ACT46_FORWARD_MASK    0x10\n#define    RTL8367C_ACT46_POLICING_OFFSET    3\n#define    RTL8367C_ACT46_POLICING_MASK    0x8\n#define    RTL8367C_ACT46_PRIORITY_OFFSET    2\n#define    RTL8367C_ACT46_PRIORITY_MASK    0x4\n#define    RTL8367C_ACT46_SVID_OFFSET    1\n#define    RTL8367C_ACT46_SVID_MASK    0x2\n#define    RTL8367C_ACT46_CVID_OFFSET    0\n#define    RTL8367C_ACT46_CVID_MASK    0x1\n\n#define    RTL8367C_REG_ACL_ACTION_CTRL24    0x062c\n#define    RTL8367C_OP49_NOT_OFFSET    14\n#define    RTL8367C_OP49_NOT_MASK    0x4000\n#define    RTL8367C_ACT49_GPIO_OFFSET    13\n#define    RTL8367C_ACT49_GPIO_MASK    0x2000\n#define    RTL8367C_ACT49_FORWARD_OFFSET    12\n#define    RTL8367C_ACT49_FORWARD_MASK    0x1000\n#define    RTL8367C_ACT49_POLICING_OFFSET    11\n#define    RTL8367C_ACT49_POLICING_MASK    0x800\n#define    RTL8367C_ACT49_PRIORITY_OFFSET    10\n#define    RTL8367C_ACT49_PRIORITY_MASK    0x400\n#define    RTL8367C_ACT49_SVID_OFFSET    9\n#define    RTL8367C_ACT49_SVID_MASK    0x200\n#define    RTL8367C_ACT49_CVID_OFFSET    8\n#define    RTL8367C_ACT49_CVID_MASK    0x100\n#define    RTL8367C_OP48_NOT_OFFSET    6\n#define    RTL8367C_OP48_NOT_MASK    0x40\n#define    RTL8367C_ACT48_GPIO_OFFSET    5\n#define    RTL8367C_ACT48_GPIO_MASK    0x20\n#define    RTL8367C_ACT48_FORWARD_OFFSET    4\n#define    RTL8367C_ACT48_FORWARD_MASK    0x10\n#define    RTL8367C_ACT48_POLICING_OFFSET    3\n#define    RTL8367C_ACT48_POLICING_MASK    0x8\n#define    RTL8367C_ACT48_PRIORITY_OFFSET    2\n#define    RTL8367C_ACT48_PRIORITY_MASK    0x4\n#define    RTL8367C_ACT48_SVID_OFFSET    1\n#define    RTL8367C_ACT48_SVID_MASK    0x2\n#define    RTL8367C_ACT48_CVID_OFFSET    0\n#define    RTL8367C_ACT48_CVID_MASK    0x1\n\n#define    RTL8367C_REG_ACL_ACTION_CTRL25    0x062d\n#define    RTL8367C_OP51_NOT_OFFSET    14\n#define    RTL8367C_OP51_NOT_MASK    0x4000\n#define    RTL8367C_ACT51_GPIO_OFFSET    13\n#define    RTL8367C_ACT51_GPIO_MASK    0x2000\n#define    RTL8367C_ACT51_FORWARD_OFFSET    12\n#define    RTL8367C_ACT51_FORWARD_MASK    0x1000\n#define    RTL8367C_ACT51_POLICING_OFFSET    11\n#define    RTL8367C_ACT51_POLICING_MASK    0x800\n#define    RTL8367C_ACT51_PRIORITY_OFFSET    10\n#define    RTL8367C_ACT51_PRIORITY_MASK    0x400\n#define    RTL8367C_ACT51_SVID_OFFSET    9\n#define    RTL8367C_ACT51_SVID_MASK    0x200\n#define    RTL8367C_ACT51_CVID_OFFSET    8\n#define    RTL8367C_ACT51_CVID_MASK    0x100\n#define    RTL8367C_OP50_NOT_OFFSET    6\n#define    RTL8367C_OP50_NOT_MASK    0x40\n#define    RTL8367C_ACT50_GPIO_OFFSET    5\n#define    RTL8367C_ACT50_GPIO_MASK    0x20\n#define    RTL8367C_ACT50_FORWARD_OFFSET    4\n#define    RTL8367C_ACT50_FORWARD_MASK    0x10\n#define    RTL8367C_ACT50_POLICING_OFFSET    3\n#define    RTL8367C_ACT50_POLICING_MASK    0x8\n#define    RTL8367C_ACT50_PRIORITY_OFFSET    2\n#define    RTL8367C_ACT50_PRIORITY_MASK    0x4\n#define    RTL8367C_ACT50_SVID_OFFSET    1\n#define    RTL8367C_ACT50_SVID_MASK    0x2\n#define    RTL8367C_ACT50_CVID_OFFSET    0\n#define    RTL8367C_ACT50_CVID_MASK    0x1\n\n#define    RTL8367C_REG_ACL_ACTION_CTRL26    0x062e\n#define    RTL8367C_OP53_NOT_OFFSET    14\n#define    RTL8367C_OP53_NOT_MASK    0x4000\n#define    RTL8367C_ACT53_GPIO_OFFSET    13\n#define    RTL8367C_ACT53_GPIO_MASK    0x2000\n#define    RTL8367C_ACT53_FORWARD_OFFSET    12\n#define    RTL8367C_ACT53_FORWARD_MASK    0x1000\n#define    RTL8367C_ACT53_POLICING_OFFSET    11\n#define    RTL8367C_ACT53_POLICING_MASK    0x800\n#define    RTL8367C_ACT53_PRIORITY_OFFSET    10\n#define    RTL8367C_ACT53_PRIORITY_MASK    0x400\n#define    RTL8367C_ACT53_SVID_OFFSET    9\n#define    RTL8367C_ACT53_SVID_MASK    0x200\n#define    RTL8367C_ACT53_CVID_OFFSET    8\n#define    RTL8367C_ACT53_CVID_MASK    0x100\n#define    RTL8367C_OP52_NOT_OFFSET    6\n#define    RTL8367C_OP52_NOT_MASK    0x40\n#define    RTL8367C_ACT52_GPIO_OFFSET    5\n#define    RTL8367C_ACT52_GPIO_MASK    0x20\n#define    RTL8367C_ACT52_FORWARD_OFFSET    4\n#define    RTL8367C_ACT52_FORWARD_MASK    0x10\n#define    RTL8367C_ACT52_POLICING_OFFSET    3\n#define    RTL8367C_ACT52_POLICING_MASK    0x8\n#define    RTL8367C_ACT52_PRIORITY_OFFSET    2\n#define    RTL8367C_ACT52_PRIORITY_MASK    0x4\n#define    RTL8367C_ACT52_SVID_OFFSET    1\n#define    RTL8367C_ACT52_SVID_MASK    0x2\n#define    RTL8367C_ACT52_CVID_OFFSET    0\n#define    RTL8367C_ACT52_CVID_MASK    0x1\n\n#define    RTL8367C_REG_ACL_ACTION_CTRL27    0x062f\n#define    RTL8367C_OP55_NOT_OFFSET    14\n#define    RTL8367C_OP55_NOT_MASK    0x4000\n#define    RTL8367C_ACT55_GPIO_OFFSET    13\n#define    RTL8367C_ACT55_GPIO_MASK    0x2000\n#define    RTL8367C_ACT55_FORWARD_OFFSET    12\n#define    RTL8367C_ACT55_FORWARD_MASK    0x1000\n#define    RTL8367C_ACT55_POLICING_OFFSET    11\n#define    RTL8367C_ACT55_POLICING_MASK    0x800\n#define    RTL8367C_ACT55_PRIORITY_OFFSET    10\n#define    RTL8367C_ACT55_PRIORITY_MASK    0x400\n#define    RTL8367C_ACT55_SVID_OFFSET    9\n#define    RTL8367C_ACT55_SVID_MASK    0x200\n#define    RTL8367C_ACT55_CVID_OFFSET    8\n#define    RTL8367C_ACT55_CVID_MASK    0x100\n#define    RTL8367C_OP54_NOT_OFFSET    6\n#define    RTL8367C_OP54_NOT_MASK    0x40\n#define    RTL8367C_ACT54_GPIO_OFFSET    5\n#define    RTL8367C_ACT54_GPIO_MASK    0x20\n#define    RTL8367C_ACT54_FORWARD_OFFSET    4\n#define    RTL8367C_ACT54_FORWARD_MASK    0x10\n#define    RTL8367C_ACT54_POLICING_OFFSET    3\n#define    RTL8367C_ACT54_POLICING_MASK    0x8\n#define    RTL8367C_ACT54_PRIORITY_OFFSET    2\n#define    RTL8367C_ACT54_PRIORITY_MASK    0x4\n#define    RTL8367C_ACT54_SVID_OFFSET    1\n#define    RTL8367C_ACT54_SVID_MASK    0x2\n#define    RTL8367C_ACT54_CVID_OFFSET    0\n#define    RTL8367C_ACT54_CVID_MASK    0x1\n\n#define    RTL8367C_REG_ACL_ACTION_CTRL28    0x0630\n#define    RTL8367C_OP57_NOT_OFFSET    14\n#define    RTL8367C_OP57_NOT_MASK    0x4000\n#define    RTL8367C_ACT57_GPIO_OFFSET    13\n#define    RTL8367C_ACT57_GPIO_MASK    0x2000\n#define    RTL8367C_ACT57_FORWARD_OFFSET    12\n#define    RTL8367C_ACT57_FORWARD_MASK    0x1000\n#define    RTL8367C_ACT57_POLICING_OFFSET    11\n#define    RTL8367C_ACT57_POLICING_MASK    0x800\n#define    RTL8367C_ACT57_PRIORITY_OFFSET    10\n#define    RTL8367C_ACT57_PRIORITY_MASK    0x400\n#define    RTL8367C_ACT57_SVID_OFFSET    9\n#define    RTL8367C_ACT57_SVID_MASK    0x200\n#define    RTL8367C_ACT57_CVID_OFFSET    8\n#define    RTL8367C_ACT57_CVID_MASK    0x100\n#define    RTL8367C_OP56_NOT_OFFSET    6\n#define    RTL8367C_OP56_NOT_MASK    0x40\n#define    RTL8367C_ACT56_GPIO_OFFSET    5\n#define    RTL8367C_ACT56_GPIO_MASK    0x20\n#define    RTL8367C_ACT56_FORWARD_OFFSET    4\n#define    RTL8367C_ACT56_FORWARD_MASK    0x10\n#define    RTL8367C_ACT56_POLICING_OFFSET    3\n#define    RTL8367C_ACT56_POLICING_MASK    0x8\n#define    RTL8367C_ACT56_PRIORITY_OFFSET    2\n#define    RTL8367C_ACT56_PRIORITY_MASK    0x4\n#define    RTL8367C_ACT56_SVID_OFFSET    1\n#define    RTL8367C_ACT56_SVID_MASK    0x2\n#define    RTL8367C_ACT56_CVID_OFFSET    0\n#define    RTL8367C_ACT56_CVID_MASK    0x1\n\n#define    RTL8367C_REG_ACL_ACTION_CTRL29    0x0631\n#define    RTL8367C_OP59_NOT_OFFSET    14\n#define    RTL8367C_OP59_NOT_MASK    0x4000\n#define    RTL8367C_ACT59_GPIO_OFFSET    13\n#define    RTL8367C_ACT59_GPIO_MASK    0x2000\n#define    RTL8367C_ACT59_FORWARD_OFFSET    12\n#define    RTL8367C_ACT59_FORWARD_MASK    0x1000\n#define    RTL8367C_ACT59_POLICING_OFFSET    11\n#define    RTL8367C_ACT59_POLICING_MASK    0x800\n#define    RTL8367C_ACT59_PRIORITY_OFFSET    10\n#define    RTL8367C_ACT59_PRIORITY_MASK    0x400\n#define    RTL8367C_ACT59_SVID_OFFSET    9\n#define    RTL8367C_ACT59_SVID_MASK    0x200\n#define    RTL8367C_ACT59_CVID_OFFSET    8\n#define    RTL8367C_ACT59_CVID_MASK    0x100\n#define    RTL8367C_OP58_NOT_OFFSET    6\n#define    RTL8367C_OP58_NOT_MASK    0x40\n#define    RTL8367C_ACT58_GPIO_OFFSET    5\n#define    RTL8367C_ACT58_GPIO_MASK    0x20\n#define    RTL8367C_ACT58_FORWARD_OFFSET    4\n#define    RTL8367C_ACT58_FORWARD_MASK    0x10\n#define    RTL8367C_ACT58_POLICING_OFFSET    3\n#define    RTL8367C_ACT58_POLICING_MASK    0x8\n#define    RTL8367C_ACT58_PRIORITY_OFFSET    2\n#define    RTL8367C_ACT58_PRIORITY_MASK    0x4\n#define    RTL8367C_ACT58_SVID_OFFSET    1\n#define    RTL8367C_ACT58_SVID_MASK    0x2\n#define    RTL8367C_ACT58_CVID_OFFSET    0\n#define    RTL8367C_ACT58_CVID_MASK    0x1\n\n#define    RTL8367C_REG_ACL_ACTION_CTRL30    0x0632\n#define    RTL8367C_OP61_NOT_OFFSET    14\n#define    RTL8367C_OP61_NOT_MASK    0x4000\n#define    RTL8367C_ACT61_GPIO_OFFSET    13\n#define    RTL8367C_ACT61_GPIO_MASK    0x2000\n#define    RTL8367C_ACT61_FORWARD_OFFSET    12\n#define    RTL8367C_ACT61_FORWARD_MASK    0x1000\n#define    RTL8367C_ACT61_POLICING_OFFSET    11\n#define    RTL8367C_ACT61_POLICING_MASK    0x800\n#define    RTL8367C_ACT61_PRIORITY_OFFSET    10\n#define    RTL8367C_ACT61_PRIORITY_MASK    0x400\n#define    RTL8367C_ACT61_SVID_OFFSET    9\n#define    RTL8367C_ACT61_SVID_MASK    0x200\n#define    RTL8367C_ACT61_CVID_OFFSET    8\n#define    RTL8367C_ACT61_CVID_MASK    0x100\n#define    RTL8367C_OP60_NOT_OFFSET    6\n#define    RTL8367C_OP60_NOT_MASK    0x40\n#define    RTL8367C_ACT60_GPIO_OFFSET    5\n#define    RTL8367C_ACT60_GPIO_MASK    0x20\n#define    RTL8367C_ACT60_FORWARD_OFFSET    4\n#define    RTL8367C_ACT60_FORWARD_MASK    0x10\n#define    RTL8367C_ACT60_POLICING_OFFSET    3\n#define    RTL8367C_ACT60_POLICING_MASK    0x8\n#define    RTL8367C_ACT60_PRIORITY_OFFSET    2\n#define    RTL8367C_ACT60_PRIORITY_MASK    0x4\n#define    RTL8367C_ACT60_SVID_OFFSET    1\n#define    RTL8367C_ACT60_SVID_MASK    0x2\n#define    RTL8367C_ACT60_CVID_OFFSET    0\n#define    RTL8367C_ACT60_CVID_MASK    0x1\n\n#define    RTL8367C_REG_ACL_ACTION_CTRL31    0x0633\n#define    RTL8367C_OP63_NOT_OFFSET    14\n#define    RTL8367C_OP63_NOT_MASK    0x4000\n#define    RTL8367C_ACT63_GPIO_OFFSET    13\n#define    RTL8367C_ACT63_GPIO_MASK    0x2000\n#define    RTL8367C_ACT63_FORWARD_OFFSET    12\n#define    RTL8367C_ACT63_FORWARD_MASK    0x1000\n#define    RTL8367C_ACT63_POLICING_OFFSET    11\n#define    RTL8367C_ACT63_POLICING_MASK    0x800\n#define    RTL8367C_ACT63_PRIORITY_OFFSET    10\n#define    RTL8367C_ACT63_PRIORITY_MASK    0x400\n#define    RTL8367C_ACT63_SVID_OFFSET    9\n#define    RTL8367C_ACT63_SVID_MASK    0x200\n#define    RTL8367C_ACT63_CVID_OFFSET    8\n#define    RTL8367C_ACT63_CVID_MASK    0x100\n#define    RTL8367C_OP62_NOT_OFFSET    6\n#define    RTL8367C_OP62_NOT_MASK    0x40\n#define    RTL8367C_ACT62_GPIO_OFFSET    5\n#define    RTL8367C_ACT62_GPIO_MASK    0x20\n#define    RTL8367C_ACT62_FORWARD_OFFSET    4\n#define    RTL8367C_ACT62_FORWARD_MASK    0x10\n#define    RTL8367C_ACT62_POLICING_OFFSET    3\n#define    RTL8367C_ACT62_POLICING_MASK    0x8\n#define    RTL8367C_ACT62_PRIORITY_OFFSET    2\n#define    RTL8367C_ACT62_PRIORITY_MASK    0x4\n#define    RTL8367C_ACT62_SVID_OFFSET    1\n#define    RTL8367C_ACT62_SVID_MASK    0x2\n#define    RTL8367C_ACT62_CVID_OFFSET    0\n#define    RTL8367C_ACT62_CVID_MASK    0x1\n\n#define    RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY0_CTRL0    0x0635\n\n#define    RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY0_CTRL1    0x0636\n\n#define    RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY0_CTRL2    0x0637\n#define    RTL8367C_ACL_SDPORT_RANGE_ENTRY0_CTRL2_OFFSET    0\n#define    RTL8367C_ACL_SDPORT_RANGE_ENTRY0_CTRL2_MASK    0x3\n\n#define    RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY1_CTRL0    0x0638\n\n#define    RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY1_CTRL1    0x0639\n\n#define    RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY1_CTRL2    0x063a\n#define    RTL8367C_ACL_SDPORT_RANGE_ENTRY1_CTRL2_OFFSET    0\n#define    RTL8367C_ACL_SDPORT_RANGE_ENTRY1_CTRL2_MASK    0x3\n\n#define    RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY2_CTRL0    0x063b\n\n#define    RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY2_CTRL1    0x063c\n\n#define    RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY2_CTRL2    0x063d\n#define    RTL8367C_ACL_SDPORT_RANGE_ENTRY2_CTRL2_OFFSET    0\n#define    RTL8367C_ACL_SDPORT_RANGE_ENTRY2_CTRL2_MASK    0x3\n\n#define    RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY3_CTRL0    0x063e\n\n#define    RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY3_CTRL1    0x063f\n\n#define    RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY3_CTRL2    0x0640\n#define    RTL8367C_ACL_SDPORT_RANGE_ENTRY3_CTRL2_OFFSET    0\n#define    RTL8367C_ACL_SDPORT_RANGE_ENTRY3_CTRL2_MASK    0x3\n\n#define    RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY4_CTRL0    0x0641\n\n#define    RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY4_CTRL1    0x0642\n\n#define    RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY4_CTRL2    0x0643\n#define    RTL8367C_ACL_SDPORT_RANGE_ENTRY4_CTRL2_OFFSET    0\n#define    RTL8367C_ACL_SDPORT_RANGE_ENTRY4_CTRL2_MASK    0x3\n\n#define    RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY5_CTRL0    0x0644\n\n#define    RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY5_CTRL1    0x0645\n\n#define    RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY5_CTRL2    0x0646\n#define    RTL8367C_ACL_SDPORT_RANGE_ENTRY5_CTRL2_OFFSET    0\n#define    RTL8367C_ACL_SDPORT_RANGE_ENTRY5_CTRL2_MASK    0x3\n\n#define    RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY6_CTRL0    0x0647\n\n#define    RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY6_CTRL1    0x0648\n\n#define    RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY6_CTRL2    0x0649\n#define    RTL8367C_ACL_SDPORT_RANGE_ENTRY6_CTRL2_OFFSET    0\n#define    RTL8367C_ACL_SDPORT_RANGE_ENTRY6_CTRL2_MASK    0x3\n\n#define    RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY7_CTRL0    0x064a\n\n#define    RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY7_CTRL1    0x064b\n\n#define    RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY7_CTRL2    0x064c\n#define    RTL8367C_ACL_SDPORT_RANGE_ENTRY7_CTRL2_OFFSET    0\n#define    RTL8367C_ACL_SDPORT_RANGE_ENTRY7_CTRL2_MASK    0x3\n\n#define    RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY8_CTRL0    0x064d\n\n#define    RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY8_CTRL1    0x064e\n\n#define    RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY8_CTRL2    0x064f\n#define    RTL8367C_ACL_SDPORT_RANGE_ENTRY8_CTRL2_OFFSET    0\n#define    RTL8367C_ACL_SDPORT_RANGE_ENTRY8_CTRL2_MASK    0x3\n\n#define    RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY9_CTRL0    0x0650\n\n#define    RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY9_CTRL1    0x0651\n\n#define    RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY9_CTRL2    0x0652\n#define    RTL8367C_ACL_SDPORT_RANGE_ENTRY9_CTRL2_OFFSET    0\n#define    RTL8367C_ACL_SDPORT_RANGE_ENTRY9_CTRL2_MASK    0x3\n\n#define    RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY10_CTRL0    0x0653\n\n#define    RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY10_CTRL1    0x0654\n\n#define    RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY10_CTRL2    0x0655\n#define    RTL8367C_ACL_SDPORT_RANGE_ENTRY10_CTRL2_OFFSET    0\n#define    RTL8367C_ACL_SDPORT_RANGE_ENTRY10_CTRL2_MASK    0x3\n\n#define    RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY11_CTRL0    0x0656\n\n#define    RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY11_CTRL1    0x0657\n\n#define    RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY11_CTRL2    0x0658\n#define    RTL8367C_ACL_SDPORT_RANGE_ENTRY11_CTRL2_OFFSET    0\n#define    RTL8367C_ACL_SDPORT_RANGE_ENTRY11_CTRL2_MASK    0x3\n\n#define    RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY12_CTRL0    0x0659\n\n#define    RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY12_CTRL1    0x065a\n\n#define    RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY12_CTRL2    0x065b\n#define    RTL8367C_ACL_SDPORT_RANGE_ENTRY12_CTRL2_OFFSET    0\n#define    RTL8367C_ACL_SDPORT_RANGE_ENTRY12_CTRL2_MASK    0x3\n\n#define    RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY13_CTRL0    0x065c\n\n#define    RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY13_CTRL1    0x065d\n\n#define    RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY13_CTRL2    0x065e\n#define    RTL8367C_ACL_SDPORT_RANGE_ENTRY13_CTRL2_OFFSET    0\n#define    RTL8367C_ACL_SDPORT_RANGE_ENTRY13_CTRL2_MASK    0x3\n\n#define    RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY14_CTRL0    0x065f\n\n#define    RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY14_CTRL1    0x0660\n\n#define    RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY14_CTRL2    0x0661\n#define    RTL8367C_ACL_SDPORT_RANGE_ENTRY14_CTRL2_OFFSET    0\n#define    RTL8367C_ACL_SDPORT_RANGE_ENTRY14_CTRL2_MASK    0x3\n\n#define    RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY15_CTRL0    0x0662\n\n#define    RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY15_CTRL1    0x0663\n\n#define    RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY15_CTRL2    0x0664\n#define    RTL8367C_ACL_SDPORT_RANGE_ENTRY15_CTRL2_OFFSET    0\n#define    RTL8367C_ACL_SDPORT_RANGE_ENTRY15_CTRL2_MASK    0x3\n\n#define    RTL8367C_REG_ACL_VID_RANGE_ENTRY0_CTRL0    0x0665\n#define    RTL8367C_ACL_VID_RANGE_ENTRY0_CTRL0_OFFSET    0\n#define    RTL8367C_ACL_VID_RANGE_ENTRY0_CTRL0_MASK    0xFFF\n\n#define    RTL8367C_REG_ACL_VID_RANGE_ENTRY0_CTRL1    0x0666\n#define    RTL8367C_ACL_VID_RANGE_ENTRY0_CTRL1_CHECK0_TYPE_OFFSET    12\n#define    RTL8367C_ACL_VID_RANGE_ENTRY0_CTRL1_CHECK0_TYPE_MASK    0x3000\n#define    RTL8367C_ACL_VID_RANGE_ENTRY0_CTRL1_CHECK0_HIGH_OFFSET    0\n#define    RTL8367C_ACL_VID_RANGE_ENTRY0_CTRL1_CHECK0_HIGH_MASK    0xFFF\n\n#define    RTL8367C_REG_ACL_VID_RANGE_ENTRY1_CTRL0    0x0667\n#define    RTL8367C_ACL_VID_RANGE_ENTRY1_CTRL0_OFFSET    0\n#define    RTL8367C_ACL_VID_RANGE_ENTRY1_CTRL0_MASK    0xFFF\n\n#define    RTL8367C_REG_ACL_VID_RANGE_ENTRY1_CTRL1    0x0668\n#define    RTL8367C_ACL_VID_RANGE_ENTRY1_CTRL1_CHECK1_TYPE_OFFSET    12\n#define    RTL8367C_ACL_VID_RANGE_ENTRY1_CTRL1_CHECK1_TYPE_MASK    0x3000\n#define    RTL8367C_ACL_VID_RANGE_ENTRY1_CTRL1_CHECK1_HIGH_OFFSET    0\n#define    RTL8367C_ACL_VID_RANGE_ENTRY1_CTRL1_CHECK1_HIGH_MASK    0xFFF\n\n#define    RTL8367C_REG_ACL_VID_RANGE_ENTRY2_CTRL0    0x0669\n#define    RTL8367C_ACL_VID_RANGE_ENTRY2_CTRL0_OFFSET    0\n#define    RTL8367C_ACL_VID_RANGE_ENTRY2_CTRL0_MASK    0xFFF\n\n#define    RTL8367C_REG_ACL_VID_RANGE_ENTRY2_CTRL1    0x066a\n#define    RTL8367C_ACL_VID_RANGE_ENTRY2_CTRL1_CHECK2_TYPE_OFFSET    12\n#define    RTL8367C_ACL_VID_RANGE_ENTRY2_CTRL1_CHECK2_TYPE_MASK    0x3000\n#define    RTL8367C_ACL_VID_RANGE_ENTRY2_CTRL1_CHECK2_HIGH_OFFSET    0\n#define    RTL8367C_ACL_VID_RANGE_ENTRY2_CTRL1_CHECK2_HIGH_MASK    0xFFF\n\n#define    RTL8367C_REG_ACL_VID_RANGE_ENTRY3_CTRL0    0x066b\n#define    RTL8367C_ACL_VID_RANGE_ENTRY3_CTRL0_OFFSET    0\n#define    RTL8367C_ACL_VID_RANGE_ENTRY3_CTRL0_MASK    0xFFF\n\n#define    RTL8367C_REG_ACL_VID_RANGE_ENTRY3_CTRL1    0x066c\n#define    RTL8367C_ACL_VID_RANGE_ENTRY3_CTRL1_CHECK3_TYPE_OFFSET    12\n#define    RTL8367C_ACL_VID_RANGE_ENTRY3_CTRL1_CHECK3_TYPE_MASK    0x3000\n#define    RTL8367C_ACL_VID_RANGE_ENTRY3_CTRL1_CHECK3_HIGH_OFFSET    0\n#define    RTL8367C_ACL_VID_RANGE_ENTRY3_CTRL1_CHECK3_HIGH_MASK    0xFFF\n\n#define    RTL8367C_REG_ACL_VID_RANGE_ENTRY4_CTRL0    0x066d\n#define    RTL8367C_ACL_VID_RANGE_ENTRY4_CTRL0_OFFSET    0\n#define    RTL8367C_ACL_VID_RANGE_ENTRY4_CTRL0_MASK    0xFFF\n\n#define    RTL8367C_REG_ACL_VID_RANGE_ENTRY4_CTRL1    0x066e\n#define    RTL8367C_ACL_VID_RANGE_ENTRY4_CTRL1_CHECK4_TYPE_OFFSET    12\n#define    RTL8367C_ACL_VID_RANGE_ENTRY4_CTRL1_CHECK4_TYPE_MASK    0x3000\n#define    RTL8367C_ACL_VID_RANGE_ENTRY4_CTRL1_CHECK4_HIGH_OFFSET    0\n#define    RTL8367C_ACL_VID_RANGE_ENTRY4_CTRL1_CHECK4_HIGH_MASK    0xFFF\n\n#define    RTL8367C_REG_ACL_VID_RANGE_ENTRY5_CTRL0    0x066f\n#define    RTL8367C_ACL_VID_RANGE_ENTRY5_CTRL0_OFFSET    0\n#define    RTL8367C_ACL_VID_RANGE_ENTRY5_CTRL0_MASK    0xFFF\n\n#define    RTL8367C_REG_ACL_VID_RANGE_ENTRY5_CTRL1    0x0670\n#define    RTL8367C_ACL_VID_RANGE_ENTRY5_CTRL1_CHECK5_TYPE_OFFSET    12\n#define    RTL8367C_ACL_VID_RANGE_ENTRY5_CTRL1_CHECK5_TYPE_MASK    0x3000\n#define    RTL8367C_ACL_VID_RANGE_ENTRY5_CTRL1_CHECK5_HIGH_OFFSET    0\n#define    RTL8367C_ACL_VID_RANGE_ENTRY5_CTRL1_CHECK5_HIGH_MASK    0xFFF\n\n#define    RTL8367C_REG_ACL_VID_RANGE_ENTRY6_CTRL0    0x0671\n#define    RTL8367C_ACL_VID_RANGE_ENTRY6_CTRL0_OFFSET    0\n#define    RTL8367C_ACL_VID_RANGE_ENTRY6_CTRL0_MASK    0xFFF\n\n#define    RTL8367C_REG_ACL_VID_RANGE_ENTRY6_CTRL1    0x0672\n#define    RTL8367C_ACL_VID_RANGE_ENTRY6_CTRL1_CHECK6_TYPE_OFFSET    12\n#define    RTL8367C_ACL_VID_RANGE_ENTRY6_CTRL1_CHECK6_TYPE_MASK    0x3000\n#define    RTL8367C_ACL_VID_RANGE_ENTRY6_CTRL1_CHECK6_HIGH_OFFSET    0\n#define    RTL8367C_ACL_VID_RANGE_ENTRY6_CTRL1_CHECK6_HIGH_MASK    0xFFF\n\n#define    RTL8367C_REG_ACL_VID_RANGE_ENTRY7_CTRL0    0x0673\n#define    RTL8367C_ACL_VID_RANGE_ENTRY7_CTRL0_OFFSET    0\n#define    RTL8367C_ACL_VID_RANGE_ENTRY7_CTRL0_MASK    0xFFF\n\n#define    RTL8367C_REG_ACL_VID_RANGE_ENTRY7_CTRL1    0x0674\n#define    RTL8367C_ACL_VID_RANGE_ENTRY7_CTRL1_CHECK7_TYPE_OFFSET    12\n#define    RTL8367C_ACL_VID_RANGE_ENTRY7_CTRL1_CHECK7_TYPE_MASK    0x3000\n#define    RTL8367C_ACL_VID_RANGE_ENTRY7_CTRL1_CHECK7_HIGH_OFFSET    0\n#define    RTL8367C_ACL_VID_RANGE_ENTRY7_CTRL1_CHECK7_HIGH_MASK    0xFFF\n\n#define    RTL8367C_REG_ACL_VID_RANGE_ENTRY8_CTRL0    0x0675\n#define    RTL8367C_ACL_VID_RANGE_ENTRY8_CTRL0_OFFSET    0\n#define    RTL8367C_ACL_VID_RANGE_ENTRY8_CTRL0_MASK    0xFFF\n\n#define    RTL8367C_REG_ACL_VID_RANGE_ENTRY8_CTRL1    0x0676\n#define    RTL8367C_ACL_VID_RANGE_ENTRY8_CTRL1_CHECK8_TYPE_OFFSET    12\n#define    RTL8367C_ACL_VID_RANGE_ENTRY8_CTRL1_CHECK8_TYPE_MASK    0x3000\n#define    RTL8367C_ACL_VID_RANGE_ENTRY8_CTRL1_CHECK8_HIGH_OFFSET    0\n#define    RTL8367C_ACL_VID_RANGE_ENTRY8_CTRL1_CHECK8_HIGH_MASK    0xFFF\n\n#define    RTL8367C_REG_ACL_VID_RANGE_ENTRY9_CTRL0    0x0677\n#define    RTL8367C_ACL_VID_RANGE_ENTRY9_CTRL0_OFFSET    0\n#define    RTL8367C_ACL_VID_RANGE_ENTRY9_CTRL0_MASK    0xFFF\n\n#define    RTL8367C_REG_ACL_VID_RANGE_ENTRY9_CTRL1    0x0678\n#define    RTL8367C_ACL_VID_RANGE_ENTRY9_CTRL1_CHECK9_TYPE_OFFSET    12\n#define    RTL8367C_ACL_VID_RANGE_ENTRY9_CTRL1_CHECK9_TYPE_MASK    0x3000\n#define    RTL8367C_ACL_VID_RANGE_ENTRY9_CTRL1_CHECK9_HIGH_OFFSET    0\n#define    RTL8367C_ACL_VID_RANGE_ENTRY9_CTRL1_CHECK9_HIGH_MASK    0xFFF\n\n#define    RTL8367C_REG_ACL_VID_RANGE_ENTRY10_CTRL0    0x0679\n#define    RTL8367C_ACL_VID_RANGE_ENTRY10_CTRL0_OFFSET    0\n#define    RTL8367C_ACL_VID_RANGE_ENTRY10_CTRL0_MASK    0xFFF\n\n#define    RTL8367C_REG_ACL_VID_RANGE_ENTRY10_CTRL1    0x067a\n#define    RTL8367C_ACL_VID_RANGE_ENTRY10_CTRL1_CHECK10_TYPE_OFFSET    12\n#define    RTL8367C_ACL_VID_RANGE_ENTRY10_CTRL1_CHECK10_TYPE_MASK    0x3000\n#define    RTL8367C_ACL_VID_RANGE_ENTRY10_CTRL1_CHECK10_HIGH_OFFSET    0\n#define    RTL8367C_ACL_VID_RANGE_ENTRY10_CTRL1_CHECK10_HIGH_MASK    0xFFF\n\n#define    RTL8367C_REG_ACL_VID_RANGE_ENTRY11_CTRL0    0x067b\n#define    RTL8367C_ACL_VID_RANGE_ENTRY11_CTRL0_OFFSET    0\n#define    RTL8367C_ACL_VID_RANGE_ENTRY11_CTRL0_MASK    0xFFF\n\n#define    RTL8367C_REG_ACL_VID_RANGE_ENTRY11_CTRL1    0x067c\n#define    RTL8367C_ACL_VID_RANGE_ENTRY11_CTRL1_CHECK11_TYPE_OFFSET    12\n#define    RTL8367C_ACL_VID_RANGE_ENTRY11_CTRL1_CHECK11_TYPE_MASK    0x3000\n#define    RTL8367C_ACL_VID_RANGE_ENTRY11_CTRL1_CHECK11_HIGH_OFFSET    0\n#define    RTL8367C_ACL_VID_RANGE_ENTRY11_CTRL1_CHECK11_HIGH_MASK    0xFFF\n\n#define    RTL8367C_REG_ACL_VID_RANGE_ENTRY12_CTRL0    0x067d\n#define    RTL8367C_ACL_VID_RANGE_ENTRY12_CTRL0_OFFSET    0\n#define    RTL8367C_ACL_VID_RANGE_ENTRY12_CTRL0_MASK    0xFFF\n\n#define    RTL8367C_REG_ACL_VID_RANGE_ENTRY12_CTRL1    0x067e\n#define    RTL8367C_ACL_VID_RANGE_ENTRY12_CTRL1_CHECK12_TYPE_OFFSET    12\n#define    RTL8367C_ACL_VID_RANGE_ENTRY12_CTRL1_CHECK12_TYPE_MASK    0x3000\n#define    RTL8367C_ACL_VID_RANGE_ENTRY12_CTRL1_CHECK12_HIGH_OFFSET    0\n#define    RTL8367C_ACL_VID_RANGE_ENTRY12_CTRL1_CHECK12_HIGH_MASK    0xFFF\n\n#define    RTL8367C_REG_ACL_VID_RANGE_ENTRY13_CTRL0    0x067f\n#define    RTL8367C_ACL_VID_RANGE_ENTRY13_CTRL0_OFFSET    0\n#define    RTL8367C_ACL_VID_RANGE_ENTRY13_CTRL0_MASK    0xFFF\n\n#define    RTL8367C_REG_ACL_VID_RANGE_ENTRY13_CTRL1    0x0680\n#define    RTL8367C_ACL_VID_RANGE_ENTRY13_CTRL1_CHECK13_TYPE_OFFSET    12\n#define    RTL8367C_ACL_VID_RANGE_ENTRY13_CTRL1_CHECK13_TYPE_MASK    0x3000\n#define    RTL8367C_ACL_VID_RANGE_ENTRY13_CTRL1_CHECK13_HIGH_OFFSET    0\n#define    RTL8367C_ACL_VID_RANGE_ENTRY13_CTRL1_CHECK13_HIGH_MASK    0xFFF\n\n#define    RTL8367C_REG_ACL_VID_RANGE_ENTRY14_CTRL0    0x0681\n#define    RTL8367C_ACL_VID_RANGE_ENTRY14_CTRL0_OFFSET    0\n#define    RTL8367C_ACL_VID_RANGE_ENTRY14_CTRL0_MASK    0xFFF\n\n#define    RTL8367C_REG_ACL_VID_RANGE_ENTRY14_CTRL1    0x0682\n#define    RTL8367C_ACL_VID_RANGE_ENTRY14_CTRL1_CHECK14_TYPE_OFFSET    12\n#define    RTL8367C_ACL_VID_RANGE_ENTRY14_CTRL1_CHECK14_TYPE_MASK    0x3000\n#define    RTL8367C_ACL_VID_RANGE_ENTRY14_CTRL1_CHECK14_HIGH_OFFSET    0\n#define    RTL8367C_ACL_VID_RANGE_ENTRY14_CTRL1_CHECK14_HIGH_MASK    0xFFF\n\n#define    RTL8367C_REG_ACL_VID_RANGE_ENTRY15_CTRL0    0x0683\n#define    RTL8367C_ACL_VID_RANGE_ENTRY15_CTRL0_OFFSET    0\n#define    RTL8367C_ACL_VID_RANGE_ENTRY15_CTRL0_MASK    0xFFF\n\n#define    RTL8367C_REG_ACL_VID_RANGE_ENTRY15_CTRL1    0x0684\n#define    RTL8367C_ACL_VID_RANGE_ENTRY15_CTRL1_CHECK15_TYPE_OFFSET    12\n#define    RTL8367C_ACL_VID_RANGE_ENTRY15_CTRL1_CHECK15_TYPE_MASK    0x3000\n#define    RTL8367C_ACL_VID_RANGE_ENTRY15_CTRL1_CHECK15_HIGH_OFFSET    0\n#define    RTL8367C_ACL_VID_RANGE_ENTRY15_CTRL1_CHECK15_HIGH_MASK    0xFFF\n\n#define    RTL8367C_REG_ACL_IP_RANGE_ENTRY0_CTRL0    0x0685\n\n#define    RTL8367C_REG_ACL_IP_RANGE_ENTRY0_CTRL1    0x0686\n\n#define    RTL8367C_REG_ACL_IP_RANGE_ENTRY0_CTRL2    0x0687\n\n#define    RTL8367C_REG_ACL_IP_RANGE_ENTRY0_CTRL3    0x0688\n\n#define    RTL8367C_REG_ACL_IP_RANGE_ENTRY0_CTRL4    0x0689\n#define    RTL8367C_ACL_IP_RANGE_ENTRY0_CTRL4_OFFSET    0\n#define    RTL8367C_ACL_IP_RANGE_ENTRY0_CTRL4_MASK    0x7\n\n#define    RTL8367C_REG_ACL_IP_RANGE_ENTRY1_CTRL0    0x068a\n\n#define    RTL8367C_REG_ACL_IP_RANGE_ENTRY1_CTRL1    0x068b\n\n#define    RTL8367C_REG_ACL_IP_RANGE_ENTRY1_CTRL2    0x068c\n\n#define    RTL8367C_REG_ACL_IP_RANGE_ENTRY1_CTRL3    0x068d\n\n#define    RTL8367C_REG_ACL_IP_RANGE_ENTRY1_CTRL4    0x068e\n#define    RTL8367C_ACL_IP_RANGE_ENTRY1_CTRL4_OFFSET    0\n#define    RTL8367C_ACL_IP_RANGE_ENTRY1_CTRL4_MASK    0x7\n\n#define    RTL8367C_REG_ACL_IP_RANGE_ENTRY2_CTRL0    0x068f\n\n#define    RTL8367C_REG_ACL_IP_RANGE_ENTRY2_CTRL1    0x0690\n\n#define    RTL8367C_REG_ACL_IP_RANGE_ENTRY2_CTRL2    0x0691\n\n#define    RTL8367C_REG_ACL_IP_RANGE_ENTRY2_CTRL3    0x0692\n\n#define    RTL8367C_REG_ACL_IP_RANGE_ENTRY2_CTRL4    0x0693\n#define    RTL8367C_ACL_IP_RANGE_ENTRY2_CTRL4_OFFSET    0\n#define    RTL8367C_ACL_IP_RANGE_ENTRY2_CTRL4_MASK    0x7\n\n#define    RTL8367C_REG_ACL_IP_RANGE_ENTRY3_CTRL0    0x0694\n\n#define    RTL8367C_REG_ACL_IP_RANGE_ENTRY3_CTRL1    0x0695\n\n#define    RTL8367C_REG_ACL_IP_RANGE_ENTRY3_CTRL2    0x0696\n\n#define    RTL8367C_REG_ACL_IP_RANGE_ENTRY3_CTRL3    0x0697\n\n#define    RTL8367C_REG_ACL_IP_RANGE_ENTRY3_CTRL4    0x0698\n#define    RTL8367C_ACL_IP_RANGE_ENTRY3_CTRL4_OFFSET    0\n#define    RTL8367C_ACL_IP_RANGE_ENTRY3_CTRL4_MASK    0x7\n\n#define    RTL8367C_REG_ACL_IP_RANGE_ENTRY4_CTRL0    0x0699\n\n#define    RTL8367C_REG_ACL_IP_RANGE_ENTRY4_CTRL1    0x069a\n\n#define    RTL8367C_REG_ACL_IP_RANGE_ENTRY4_CTRL2    0x069b\n\n#define    RTL8367C_REG_ACL_IP_RANGE_ENTRY4_CTRL3    0x069c\n\n#define    RTL8367C_REG_ACL_IP_RANGE_ENTRY4_CTRL4    0x069d\n#define    RTL8367C_ACL_IP_RANGE_ENTRY4_CTRL4_OFFSET    0\n#define    RTL8367C_ACL_IP_RANGE_ENTRY4_CTRL4_MASK    0x7\n\n#define    RTL8367C_REG_ACL_IP_RANGE_ENTRY5_CTRL0    0x069e\n\n#define    RTL8367C_REG_ACL_IP_RANGE_ENTRY5_CTRL1    0x069f\n\n#define    RTL8367C_REG_ACL_IP_RANGE_ENTRY5_CTRL2    0x06a0\n\n#define    RTL8367C_REG_ACL_IP_RANGE_ENTRY5_CTRL3    0x06a1\n\n#define    RTL8367C_REG_ACL_IP_RANGE_ENTRY5_CTRL4    0x06a2\n#define    RTL8367C_ACL_IP_RANGE_ENTRY5_CTRL4_OFFSET    0\n#define    RTL8367C_ACL_IP_RANGE_ENTRY5_CTRL4_MASK    0x7\n\n#define    RTL8367C_REG_ACL_IP_RANGE_ENTRY6_CTRL0    0x06a3\n\n#define    RTL8367C_REG_ACL_IP_RANGE_ENTRY6_CTRL1    0x06a4\n\n#define    RTL8367C_REG_ACL_IP_RANGE_ENTRY6_CTRL2    0x06a5\n\n#define    RTL8367C_REG_ACL_IP_RANGE_ENTRY6_CTRL3    0x06a6\n\n#define    RTL8367C_REG_ACL_IP_RANGE_ENTRY6_CTRL4    0x06a7\n#define    RTL8367C_ACL_IP_RANGE_ENTRY6_CTRL4_OFFSET    0\n#define    RTL8367C_ACL_IP_RANGE_ENTRY6_CTRL4_MASK    0x7\n\n#define    RTL8367C_REG_ACL_IP_RANGE_ENTRY7_CTRL0    0x06a8\n\n#define    RTL8367C_REG_ACL_IP_RANGE_ENTRY7_CTRL1    0x06a9\n\n#define    RTL8367C_REG_ACL_IP_RANGE_ENTRY7_CTRL2    0x06aa\n\n#define    RTL8367C_REG_ACL_IP_RANGE_ENTRY7_CTRL3    0x06ab\n\n#define    RTL8367C_REG_ACL_IP_RANGE_ENTRY7_CTRL4    0x06ac\n#define    RTL8367C_ACL_IP_RANGE_ENTRY7_CTRL4_OFFSET    0\n#define    RTL8367C_ACL_IP_RANGE_ENTRY7_CTRL4_MASK    0x7\n\n#define    RTL8367C_REG_ACL_IP_RANGE_ENTRY8_CTRL0    0x06ad\n\n#define    RTL8367C_REG_ACL_IP_RANGE_ENTRY8_CTRL1    0x06ae\n\n#define    RTL8367C_REG_ACL_IP_RANGE_ENTRY8_CTRL2    0x06af\n\n#define    RTL8367C_REG_ACL_IP_RANGE_ENTRY8_CTRL3    0x06b0\n\n#define    RTL8367C_REG_ACL_IP_RANGE_ENTRY8_CTRL4    0x06b1\n#define    RTL8367C_ACL_IP_RANGE_ENTRY8_CTRL4_OFFSET    0\n#define    RTL8367C_ACL_IP_RANGE_ENTRY8_CTRL4_MASK    0x7\n\n#define    RTL8367C_REG_ACL_IP_RANGE_ENTRY9_CTRL0    0x06b2\n\n#define    RTL8367C_REG_ACL_IP_RANGE_ENTRY9_CTRL1    0x06b3\n\n#define    RTL8367C_REG_ACL_IP_RANGE_ENTRY9_CTRL2    0x06b4\n\n#define    RTL8367C_REG_ACL_IP_RANGE_ENTRY9_CTRL3    0x06b5\n\n#define    RTL8367C_REG_ACL_IP_RANGE_ENTRY9_CTRL4    0x06b6\n#define    RTL8367C_ACL_IP_RANGE_ENTRY9_CTRL4_OFFSET    0\n#define    RTL8367C_ACL_IP_RANGE_ENTRY9_CTRL4_MASK    0x7\n\n#define    RTL8367C_REG_ACL_IP_RANGE_ENTRY10_CTRL0    0x06b7\n\n#define    RTL8367C_REG_ACL_IP_RANGE_ENTRY10_CTRL1    0x06b8\n\n#define    RTL8367C_REG_ACL_IP_RANGE_ENTRY10_CTRL2    0x06b9\n\n#define    RTL8367C_REG_ACL_IP_RANGE_ENTRY10_CTRL3    0x06ba\n\n#define    RTL8367C_REG_ACL_IP_RANGE_ENTRY10_CTRL4    0x06bb\n#define    RTL8367C_ACL_IP_RANGE_ENTRY10_CTRL4_OFFSET    0\n#define    RTL8367C_ACL_IP_RANGE_ENTRY10_CTRL4_MASK    0x7\n\n#define    RTL8367C_REG_ACL_IP_RANGE_ENTRY11_CTRL0    0x06bc\n\n#define    RTL8367C_REG_ACL_IP_RANGE_ENTRY11_CTRL1    0x06bd\n\n#define    RTL8367C_REG_ACL_IP_RANGE_ENTRY11_CTRL2    0x06be\n\n#define    RTL8367C_REG_ACL_IP_RANGE_ENTRY11_CTRL3    0x06bf\n\n#define    RTL8367C_REG_ACL_IP_RANGE_ENTRY11_CTRL4    0x06c0\n#define    RTL8367C_ACL_IP_RANGE_ENTRY11_CTRL4_OFFSET    0\n#define    RTL8367C_ACL_IP_RANGE_ENTRY11_CTRL4_MASK    0x7\n\n#define    RTL8367C_REG_ACL_IP_RANGE_ENTRY12_CTRL0    0x06c1\n\n#define    RTL8367C_REG_ACL_IP_RANGE_ENTRY12_CTRL1    0x06c2\n\n#define    RTL8367C_REG_ACL_IP_RANGE_ENTRY12_CTRL2    0x06c3\n\n#define    RTL8367C_REG_ACL_IP_RANGE_ENTRY12_CTRL3    0x06c4\n\n#define    RTL8367C_REG_ACL_IP_RANGE_ENTRY12_CTRL4    0x06c5\n#define    RTL8367C_ACL_IP_RANGE_ENTRY12_CTRL4_OFFSET    0\n#define    RTL8367C_ACL_IP_RANGE_ENTRY12_CTRL4_MASK    0x7\n\n#define    RTL8367C_REG_ACL_IP_RANGE_ENTRY13_CTRL0    0x06c6\n\n#define    RTL8367C_REG_ACL_IP_RANGE_ENTRY13_CTRL1    0x06c7\n\n#define    RTL8367C_REG_ACL_IP_RANGE_ENTRY13_CTRL2    0x06c8\n\n#define    RTL8367C_REG_ACL_IP_RANGE_ENTRY13_CTRL3    0x06c9\n\n#define    RTL8367C_REG_ACL_IP_RANGE_ENTRY13_CTRL4    0x06ca\n#define    RTL8367C_ACL_IP_RANGE_ENTRY13_CTRL4_OFFSET    0\n#define    RTL8367C_ACL_IP_RANGE_ENTRY13_CTRL4_MASK    0x7\n\n#define    RTL8367C_REG_ACL_IP_RANGE_ENTRY14_CTRL0    0x06cb\n\n#define    RTL8367C_REG_ACL_IP_RANGE_ENTRY14_CTRL1    0x06cc\n\n#define    RTL8367C_REG_ACL_IP_RANGE_ENTRY14_CTRL2    0x06cd\n\n#define    RTL8367C_REG_ACL_IP_RANGE_ENTRY14_CTRL3    0x06ce\n\n#define    RTL8367C_REG_ACL_IP_RANGE_ENTRY14_CTRL4    0x06cf\n#define    RTL8367C_ACL_IP_RANGE_ENTRY14_CTRL4_OFFSET    0\n#define    RTL8367C_ACL_IP_RANGE_ENTRY14_CTRL4_MASK    0x7\n\n#define    RTL8367C_REG_ACL_IP_RANGE_ENTRY15_CTRL0    0x06d0\n\n#define    RTL8367C_REG_ACL_IP_RANGE_ENTRY15_CTRL1    0x06d1\n\n#define    RTL8367C_REG_ACL_IP_RANGE_ENTRY15_CTRL2    0x06d2\n\n#define    RTL8367C_REG_ACL_IP_RANGE_ENTRY15_CTRL3    0x06d3\n\n#define    RTL8367C_REG_ACL_IP_RANGE_ENTRY15_CTRL4    0x06d4\n#define    RTL8367C_ACL_IP_RANGE_ENTRY15_CTRL4_OFFSET    0\n#define    RTL8367C_ACL_IP_RANGE_ENTRY15_CTRL4_MASK    0x7\n\n#define    RTL8367C_REG_ACL_ENABLE    0x06d5\n#define    RTL8367C_PORT10_ENABLE_OFFSET    10\n#define    RTL8367C_PORT10_ENABLE_MASK    0x400\n#define    RTL8367C_PORT9_ENABLE_OFFSET    9\n#define    RTL8367C_PORT9_ENABLE_MASK    0x200\n#define    RTL8367C_PORT8_ENABLE_OFFSET    8\n#define    RTL8367C_PORT8_ENABLE_MASK    0x100\n#define    RTL8367C_PORT7_ENABLE_OFFSET    7\n#define    RTL8367C_PORT7_ENABLE_MASK    0x80\n#define    RTL8367C_PORT6_ENABLE_OFFSET    6\n#define    RTL8367C_PORT6_ENABLE_MASK    0x40\n#define    RTL8367C_PORT5_ENABLE_OFFSET    5\n#define    RTL8367C_PORT5_ENABLE_MASK    0x20\n#define    RTL8367C_PORT4_ENABLE_OFFSET    4\n#define    RTL8367C_PORT4_ENABLE_MASK    0x10\n#define    RTL8367C_PORT3_ENABLE_OFFSET    3\n#define    RTL8367C_PORT3_ENABLE_MASK    0x8\n#define    RTL8367C_PORT2_ENABLE_OFFSET    2\n#define    RTL8367C_PORT2_ENABLE_MASK    0x4\n#define    RTL8367C_PORT1_ENABLE_OFFSET    1\n#define    RTL8367C_PORT1_ENABLE_MASK    0x2\n#define    RTL8367C_PORT0_ENABLE_OFFSET    0\n#define    RTL8367C_PORT0_ENABLE_MASK    0x1\n\n#define    RTL8367C_REG_ACL_UNMATCH_PERMIT    0x06d6\n#define    RTL8367C_PORT10_PERMIT_OFFSET    10\n#define    RTL8367C_PORT10_PERMIT_MASK    0x400\n#define    RTL8367C_PORT9_PERMIT_OFFSET    9\n#define    RTL8367C_PORT9_PERMIT_MASK    0x200\n#define    RTL8367C_PORT8_PERMIT_OFFSET    8\n#define    RTL8367C_PORT8_PERMIT_MASK    0x100\n#define    RTL8367C_PORT7_PERMIT_OFFSET    7\n#define    RTL8367C_PORT7_PERMIT_MASK    0x80\n#define    RTL8367C_PORT6_PERMIT_OFFSET    6\n#define    RTL8367C_PORT6_PERMIT_MASK    0x40\n#define    RTL8367C_PORT5_PERMIT_OFFSET    5\n#define    RTL8367C_PORT5_PERMIT_MASK    0x20\n#define    RTL8367C_PORT4_PERMIT_OFFSET    4\n#define    RTL8367C_PORT4_PERMIT_MASK    0x10\n#define    RTL8367C_PORT3_PERMIT_OFFSET    3\n#define    RTL8367C_PORT3_PERMIT_MASK    0x8\n#define    RTL8367C_PORT2_PERMIT_OFFSET    2\n#define    RTL8367C_PORT2_PERMIT_MASK    0x4\n#define    RTL8367C_PORT1_PERMIT_OFFSET    1\n#define    RTL8367C_PORT1_PERMIT_MASK    0x2\n#define    RTL8367C_PORT0_PERMIT_OFFSET    0\n#define    RTL8367C_PORT0_PERMIT_MASK    0x1\n\n#define    RTL8367C_REG_ACL_GPIO_POLARITY    0x06d7\n#define    RTL8367C_ACL_GPIO_POLARITY_OFFSET    0\n#define    RTL8367C_ACL_GPIO_POLARITY_MASK    0x1\n\n#define    RTL8367C_REG_ACL_LOG_CNT_TYPE    0x06d8\n#define    RTL8367C_ACL_LOG_CNT_TYPE_COUNTER15_TYPE_OFFSET    15\n#define    RTL8367C_ACL_LOG_CNT_TYPE_COUNTER15_TYPE_MASK    0x8000\n#define    RTL8367C_ACL_LOG_CNT_TYPE_COUNTER14_TYPE_OFFSET    14\n#define    RTL8367C_ACL_LOG_CNT_TYPE_COUNTER14_TYPE_MASK    0x4000\n#define    RTL8367C_ACL_LOG_CNT_TYPE_COUNTER13_TYPE_OFFSET    13\n#define    RTL8367C_ACL_LOG_CNT_TYPE_COUNTER13_TYPE_MASK    0x2000\n#define    RTL8367C_ACL_LOG_CNT_TYPE_COUNTER12_TYPE_OFFSET    12\n#define    RTL8367C_ACL_LOG_CNT_TYPE_COUNTER12_TYPE_MASK    0x1000\n#define    RTL8367C_ACL_LOG_CNT_TYPE_COUNTER11_TYPE_OFFSET    11\n#define    RTL8367C_ACL_LOG_CNT_TYPE_COUNTER11_TYPE_MASK    0x800\n#define    RTL8367C_ACL_LOG_CNT_TYPE_COUNTER10_TYPE_OFFSET    10\n#define    RTL8367C_ACL_LOG_CNT_TYPE_COUNTER10_TYPE_MASK    0x400\n#define    RTL8367C_ACL_LOG_CNT_TYPE_COUNTER9_TYPE_OFFSET    9\n#define    RTL8367C_ACL_LOG_CNT_TYPE_COUNTER9_TYPE_MASK    0x200\n#define    RTL8367C_ACL_LOG_CNT_TYPE_COUNTER8_TYPE_OFFSET    8\n#define    RTL8367C_ACL_LOG_CNT_TYPE_COUNTER8_TYPE_MASK    0x100\n#define    RTL8367C_ACL_LOG_CNT_TYPE_COUNTER7_TYPE_OFFSET    7\n#define    RTL8367C_ACL_LOG_CNT_TYPE_COUNTER7_TYPE_MASK    0x80\n#define    RTL8367C_ACL_LOG_CNT_TYPE_COUNTER6_TYPE_OFFSET    6\n#define    RTL8367C_ACL_LOG_CNT_TYPE_COUNTER6_TYPE_MASK    0x40\n#define    RTL8367C_ACL_LOG_CNT_TYPE_COUNTER5_TYPE_OFFSET    5\n#define    RTL8367C_ACL_LOG_CNT_TYPE_COUNTER5_TYPE_MASK    0x20\n#define    RTL8367C_ACL_LOG_CNT_TYPE_COUNTER4_TYPE_OFFSET    4\n#define    RTL8367C_ACL_LOG_CNT_TYPE_COUNTER4_TYPE_MASK    0x10\n#define    RTL8367C_ACL_LOG_CNT_TYPE_COUNTER3_TYPE_OFFSET    3\n#define    RTL8367C_ACL_LOG_CNT_TYPE_COUNTER3_TYPE_MASK    0x8\n#define    RTL8367C_ACL_LOG_CNT_TYPE_COUNTER2_TYPE_OFFSET    2\n#define    RTL8367C_ACL_LOG_CNT_TYPE_COUNTER2_TYPE_MASK    0x4\n#define    RTL8367C_ACL_LOG_CNT_TYPE_COUNTER1_TYPE_OFFSET    1\n#define    RTL8367C_ACL_LOG_CNT_TYPE_COUNTER1_TYPE_MASK    0x2\n#define    RTL8367C_ACL_LOG_CNT_TYPE_COUNTER0_TYPE_OFFSET    0\n#define    RTL8367C_ACL_LOG_CNT_TYPE_COUNTER0_TYPE_MASK    0x1\n\n#define    RTL8367C_REG_ACL_RESET_CFG    0x06d9\n#define    RTL8367C_ACL_RESET_CFG_OFFSET    0\n#define    RTL8367C_ACL_RESET_CFG_MASK    0x1\n\n#define    RTL8367C_REG_ACL_DUMMY00    0x06E0\n\n#define    RTL8367C_REG_ACL_DUMMY01    0x06E1\n\n#define    RTL8367C_REG_ACL_DUMMY02    0x06E2\n\n#define    RTL8367C_REG_ACL_DUMMY03    0x06E3\n\n#define    RTL8367C_REG_ACL_DUMMY04    0x06E4\n\n#define    RTL8367C_REG_ACL_DUMMY05    0x06E5\n\n#define    RTL8367C_REG_ACL_DUMMY06    0x06E6\n\n#define    RTL8367C_REG_ACL_DUMMY07    0x06E7\n\n#define    RTL8367C_REG_ACL_REASON_01    0x06E8\n#define    RTL8367C_ACL_ACT_1_OFFSET    8\n#define    RTL8367C_ACL_ACT_1_MASK    0xFF00\n#define    RTL8367C_ACL_ACT_0_OFFSET    0\n#define    RTL8367C_ACL_ACT_0_MASK    0xFF\n\n#define    RTL8367C_REG_ACL_REASON_23    0x06E9\n#define    RTL8367C_ACL_ACT_3_OFFSET    8\n#define    RTL8367C_ACL_ACT_3_MASK    0xFF00\n#define    RTL8367C_ACL_ACT_2_OFFSET    0\n#define    RTL8367C_ACL_ACT_2_MASK    0xFF\n\n#define    RTL8367C_REG_ACL_REASON_45    0x06EA\n#define    RTL8367C_ACL_ACT_5_OFFSET    8\n#define    RTL8367C_ACL_ACT_5_MASK    0xFF00\n#define    RTL8367C_ACL_ACT_4_OFFSET    0\n#define    RTL8367C_ACL_ACT_4_MASK    0xFF\n\n#define    RTL8367C_REG_ACL_ACCESS_MODE    0x06EB\n#define    RTL8367C_ACL_ACCESS_MODE_OFFSET    0\n#define    RTL8367C_ACL_ACCESS_MODE_MASK    0x1\n\n#define    RTL8367C_REG_ACL_ACTION_CTRL32    0x06F0\n#define    RTL8367C_OP65_NOT_OFFSET    14\n#define    RTL8367C_OP65_NOT_MASK    0x4000\n#define    RTL8367C_ACT65_GPIO_OFFSET    13\n#define    RTL8367C_ACT65_GPIO_MASK    0x2000\n#define    RTL8367C_ACT65_FORWARD_OFFSET    12\n#define    RTL8367C_ACT65_FORWARD_MASK    0x1000\n#define    RTL8367C_ACT65_POLICING_OFFSET    11\n#define    RTL8367C_ACT65_POLICING_MASK    0x800\n#define    RTL8367C_ACT65_PRIORITY_OFFSET    10\n#define    RTL8367C_ACT65_PRIORITY_MASK    0x400\n#define    RTL8367C_ACT65_SVID_OFFSET    9\n#define    RTL8367C_ACT65_SVID_MASK    0x200\n#define    RTL8367C_ACT65_CVID_OFFSET    8\n#define    RTL8367C_ACT65_CVID_MASK    0x100\n#define    RTL8367C_OP64_NOT_OFFSET    6\n#define    RTL8367C_OP64_NOT_MASK    0x40\n#define    RTL8367C_ACT64_GPIO_OFFSET    5\n#define    RTL8367C_ACT64_GPIO_MASK    0x20\n#define    RTL8367C_ACT64_FORWARD_OFFSET    4\n#define    RTL8367C_ACT64_FORWARD_MASK    0x10\n#define    RTL8367C_ACT64_POLICING_OFFSET    3\n#define    RTL8367C_ACT64_POLICING_MASK    0x8\n#define    RTL8367C_ACT64_PRIORITY_OFFSET    2\n#define    RTL8367C_ACT64_PRIORITY_MASK    0x4\n#define    RTL8367C_ACT64_SVID_OFFSET    1\n#define    RTL8367C_ACT64_SVID_MASK    0x2\n#define    RTL8367C_ACT64_CVID_OFFSET    0\n#define    RTL8367C_ACT64_CVID_MASK    0x1\n\n#define    RTL8367C_REG_ACL_ACTION_CTRL33    0x06F1\n#define    RTL8367C_OP67_NOT_OFFSET    14\n#define    RTL8367C_OP67_NOT_MASK    0x4000\n#define    RTL8367C_ACT67_GPIO_OFFSET    13\n#define    RTL8367C_ACT67_GPIO_MASK    0x2000\n#define    RTL8367C_ACT67_FORWARD_OFFSET    12\n#define    RTL8367C_ACT67_FORWARD_MASK    0x1000\n#define    RTL8367C_ACT67_POLICING_OFFSET    11\n#define    RTL8367C_ACT67_POLICING_MASK    0x800\n#define    RTL8367C_ACT67_PRIORITY_OFFSET    10\n#define    RTL8367C_ACT67_PRIORITY_MASK    0x400\n#define    RTL8367C_ACT67_SVID_OFFSET    9\n#define    RTL8367C_ACT67_SVID_MASK    0x200\n#define    RTL8367C_ACT67_CVID_OFFSET    8\n#define    RTL8367C_ACT67_CVID_MASK    0x100\n#define    RTL8367C_OP66_NOT_OFFSET    6\n#define    RTL8367C_OP66_NOT_MASK    0x40\n#define    RTL8367C_ACT66_GPIO_OFFSET    5\n#define    RTL8367C_ACT66_GPIO_MASK    0x20\n#define    RTL8367C_ACT66_FORWARD_OFFSET    4\n#define    RTL8367C_ACT66_FORWARD_MASK    0x10\n#define    RTL8367C_ACT66_POLICING_OFFSET    3\n#define    RTL8367C_ACT66_POLICING_MASK    0x8\n#define    RTL8367C_ACT66_PRIORITY_OFFSET    2\n#define    RTL8367C_ACT66_PRIORITY_MASK    0x4\n#define    RTL8367C_ACT66_SVID_OFFSET    1\n#define    RTL8367C_ACT66_SVID_MASK    0x2\n#define    RTL8367C_ACT66_CVID_OFFSET    0\n#define    RTL8367C_ACT66_CVID_MASK    0x1\n\n#define    RTL8367C_REG_ACL_ACTION_CTRL34    0x06F2\n#define    RTL8367C_OP69_NOT_OFFSET    14\n#define    RTL8367C_OP69_NOT_MASK    0x4000\n#define    RTL8367C_ACT69_GPIO_OFFSET    13\n#define    RTL8367C_ACT69_GPIO_MASK    0x2000\n#define    RTL8367C_ACT69_FORWARD_OFFSET    12\n#define    RTL8367C_ACT69_FORWARD_MASK    0x1000\n#define    RTL8367C_ACT69_POLICING_OFFSET    11\n#define    RTL8367C_ACT69_POLICING_MASK    0x800\n#define    RTL8367C_ACT69_PRIORITY_OFFSET    10\n#define    RTL8367C_ACT69_PRIORITY_MASK    0x400\n#define    RTL8367C_ACT69_SVID_OFFSET    9\n#define    RTL8367C_ACT69_SVID_MASK    0x200\n#define    RTL8367C_ACT69_CVID_OFFSET    8\n#define    RTL8367C_ACT69_CVID_MASK    0x100\n#define    RTL8367C_OP68_NOT_OFFSET    6\n#define    RTL8367C_OP68_NOT_MASK    0x40\n#define    RTL8367C_ACT68_GPIO_OFFSET    5\n#define    RTL8367C_ACT68_GPIO_MASK    0x20\n#define    RTL8367C_ACT68_FORWARD_OFFSET    4\n#define    RTL8367C_ACT68_FORWARD_MASK    0x10\n#define    RTL8367C_ACT68_POLICING_OFFSET    3\n#define    RTL8367C_ACT68_POLICING_MASK    0x8\n#define    RTL8367C_ACT68_PRIORITY_OFFSET    2\n#define    RTL8367C_ACT68_PRIORITY_MASK    0x4\n#define    RTL8367C_ACT68_SVID_OFFSET    1\n#define    RTL8367C_ACT68_SVID_MASK    0x2\n#define    RTL8367C_ACT68_CVID_OFFSET    0\n#define    RTL8367C_ACT68_CVID_MASK    0x1\n\n#define    RTL8367C_REG_ACL_ACTION_CTRL35    0x06F3\n#define    RTL8367C_OP71_NOT_OFFSET    14\n#define    RTL8367C_OP71_NOT_MASK    0x4000\n#define    RTL8367C_ACT71_GPIO_OFFSET    13\n#define    RTL8367C_ACT71_GPIO_MASK    0x2000\n#define    RTL8367C_ACT71_FORWARD_OFFSET    12\n#define    RTL8367C_ACT71_FORWARD_MASK    0x1000\n#define    RTL8367C_ACT71_POLICING_OFFSET    11\n#define    RTL8367C_ACT71_POLICING_MASK    0x800\n#define    RTL8367C_ACT71_PRIORITY_OFFSET    10\n#define    RTL8367C_ACT71_PRIORITY_MASK    0x400\n#define    RTL8367C_ACT71_SVID_OFFSET    9\n#define    RTL8367C_ACT71_SVID_MASK    0x200\n#define    RTL8367C_ACT71_CVID_OFFSET    8\n#define    RTL8367C_ACT71_CVID_MASK    0x100\n#define    RTL8367C_OP70_NOT_OFFSET    6\n#define    RTL8367C_OP70_NOT_MASK    0x40\n#define    RTL8367C_ACT70_GPIO_OFFSET    5\n#define    RTL8367C_ACT70_GPIO_MASK    0x20\n#define    RTL8367C_ACT70_FORWARD_OFFSET    4\n#define    RTL8367C_ACT70_FORWARD_MASK    0x10\n#define    RTL8367C_ACT70_POLICING_OFFSET    3\n#define    RTL8367C_ACT70_POLICING_MASK    0x8\n#define    RTL8367C_ACT70_PRIORITY_OFFSET    2\n#define    RTL8367C_ACT70_PRIORITY_MASK    0x4\n#define    RTL8367C_ACT70_SVID_OFFSET    1\n#define    RTL8367C_ACT70_SVID_MASK    0x2\n#define    RTL8367C_ACT70_CVID_OFFSET    0\n#define    RTL8367C_ACT70_CVID_MASK    0x1\n\n#define    RTL8367C_REG_ACL_ACTION_CTRL36    0x06F4\n#define    RTL8367C_OP73_NOT_OFFSET    14\n#define    RTL8367C_OP73_NOT_MASK    0x4000\n#define    RTL8367C_ACT73_GPIO_OFFSET    13\n#define    RTL8367C_ACT73_GPIO_MASK    0x2000\n#define    RTL8367C_ACT73_FORWARD_OFFSET    12\n#define    RTL8367C_ACT73_FORWARD_MASK    0x1000\n#define    RTL8367C_ACT73_POLICING_OFFSET    11\n#define    RTL8367C_ACT73_POLICING_MASK    0x800\n#define    RTL8367C_ACT73_PRIORITY_OFFSET    10\n#define    RTL8367C_ACT73_PRIORITY_MASK    0x400\n#define    RTL8367C_ACT73_SVID_OFFSET    9\n#define    RTL8367C_ACT73_SVID_MASK    0x200\n#define    RTL8367C_ACT73_CVID_OFFSET    8\n#define    RTL8367C_ACT73_CVID_MASK    0x100\n#define    RTL8367C_OP72_NOT_OFFSET    6\n#define    RTL8367C_OP72_NOT_MASK    0x40\n#define    RTL8367C_ACT72_GPIO_OFFSET    5\n#define    RTL8367C_ACT72_GPIO_MASK    0x20\n#define    RTL8367C_ACT72_FORWARD_OFFSET    4\n#define    RTL8367C_ACT72_FORWARD_MASK    0x10\n#define    RTL8367C_ACT72_POLICING_OFFSET    3\n#define    RTL8367C_ACT72_POLICING_MASK    0x8\n#define    RTL8367C_ACT72_PRIORITY_OFFSET    2\n#define    RTL8367C_ACT72_PRIORITY_MASK    0x4\n#define    RTL8367C_ACT72_SVID_OFFSET    1\n#define    RTL8367C_ACT72_SVID_MASK    0x2\n#define    RTL8367C_ACT72_CVID_OFFSET    0\n#define    RTL8367C_ACT72_CVID_MASK    0x1\n\n#define    RTL8367C_REG_ACL_ACTION_CTRL37    0x06F5\n#define    RTL8367C_OP75_NOT_OFFSET    14\n#define    RTL8367C_OP75_NOT_MASK    0x4000\n#define    RTL8367C_ACT75_GPIO_OFFSET    13\n#define    RTL8367C_ACT75_GPIO_MASK    0x2000\n#define    RTL8367C_ACT75_FORWARD_OFFSET    12\n#define    RTL8367C_ACT75_FORWARD_MASK    0x1000\n#define    RTL8367C_ACT75_POLICING_OFFSET    11\n#define    RTL8367C_ACT75_POLICING_MASK    0x800\n#define    RTL8367C_ACT75_PRIORITY_OFFSET    10\n#define    RTL8367C_ACT75_PRIORITY_MASK    0x400\n#define    RTL8367C_ACT75_SVID_OFFSET    9\n#define    RTL8367C_ACT75_SVID_MASK    0x200\n#define    RTL8367C_ACT75_CVID_OFFSET    8\n#define    RTL8367C_ACT75_CVID_MASK    0x100\n#define    RTL8367C_OP74_NOT_OFFSET    6\n#define    RTL8367C_OP74_NOT_MASK    0x40\n#define    RTL8367C_ACT74_GPIO_OFFSET    5\n#define    RTL8367C_ACT74_GPIO_MASK    0x20\n#define    RTL8367C_ACT74_FORWARD_OFFSET    4\n#define    RTL8367C_ACT74_FORWARD_MASK    0x10\n#define    RTL8367C_ACT74_POLICING_OFFSET    3\n#define    RTL8367C_ACT74_POLICING_MASK    0x8\n#define    RTL8367C_ACT74_PRIORITY_OFFSET    2\n#define    RTL8367C_ACT74_PRIORITY_MASK    0x4\n#define    RTL8367C_ACT74_SVID_OFFSET    1\n#define    RTL8367C_ACT74_SVID_MASK    0x2\n#define    RTL8367C_ACT74_CVID_OFFSET    0\n#define    RTL8367C_ACT74_CVID_MASK    0x1\n\n#define    RTL8367C_REG_ACL_ACTION_CTRL38    0x06F6\n#define    RTL8367C_OP77_NOT_OFFSET    14\n#define    RTL8367C_OP77_NOT_MASK    0x4000\n#define    RTL8367C_ACT77_GPIO_OFFSET    13\n#define    RTL8367C_ACT77_GPIO_MASK    0x2000\n#define    RTL8367C_ACT77_FORWARD_OFFSET    12\n#define    RTL8367C_ACT77_FORWARD_MASK    0x1000\n#define    RTL8367C_ACT77_POLICING_OFFSET    11\n#define    RTL8367C_ACT77_POLICING_MASK    0x800\n#define    RTL8367C_ACT77_PRIORITY_OFFSET    10\n#define    RTL8367C_ACT77_PRIORITY_MASK    0x400\n#define    RTL8367C_ACT77_SVID_OFFSET    9\n#define    RTL8367C_ACT77_SVID_MASK    0x200\n#define    RTL8367C_ACT77_CVID_OFFSET    8\n#define    RTL8367C_ACT77_CVID_MASK    0x100\n#define    RTL8367C_OP76_NOT_OFFSET    6\n#define    RTL8367C_OP76_NOT_MASK    0x40\n#define    RTL8367C_ACT76_GPIO_OFFSET    5\n#define    RTL8367C_ACT76_GPIO_MASK    0x20\n#define    RTL8367C_ACT76_FORWARD_OFFSET    4\n#define    RTL8367C_ACT76_FORWARD_MASK    0x10\n#define    RTL8367C_ACT76_POLICING_OFFSET    3\n#define    RTL8367C_ACT76_POLICING_MASK    0x8\n#define    RTL8367C_ACT76_PRIORITY_OFFSET    2\n#define    RTL8367C_ACT76_PRIORITY_MASK    0x4\n#define    RTL8367C_ACT76_SVID_OFFSET    1\n#define    RTL8367C_ACT76_SVID_MASK    0x2\n#define    RTL8367C_ACT76_CVID_OFFSET    0\n#define    RTL8367C_ACT76_CVID_MASK    0x1\n\n#define    RTL8367C_REG_ACL_ACTION_CTRL39    0x06F7\n#define    RTL8367C_OP79_NOT_OFFSET    14\n#define    RTL8367C_OP79_NOT_MASK    0x4000\n#define    RTL8367C_ACT79_GPIO_OFFSET    13\n#define    RTL8367C_ACT79_GPIO_MASK    0x2000\n#define    RTL8367C_ACT79_FORWARD_OFFSET    12\n#define    RTL8367C_ACT79_FORWARD_MASK    0x1000\n#define    RTL8367C_ACT79_POLICING_OFFSET    11\n#define    RTL8367C_ACT79_POLICING_MASK    0x800\n#define    RTL8367C_ACT79_PRIORITY_OFFSET    10\n#define    RTL8367C_ACT79_PRIORITY_MASK    0x400\n#define    RTL8367C_ACT79_SVID_OFFSET    9\n#define    RTL8367C_ACT79_SVID_MASK    0x200\n#define    RTL8367C_ACT79_CVID_OFFSET    8\n#define    RTL8367C_ACT79_CVID_MASK    0x100\n#define    RTL8367C_OP78_NOT_OFFSET    6\n#define    RTL8367C_OP78_NOT_MASK    0x40\n#define    RTL8367C_ACT78_GPIO_OFFSET    5\n#define    RTL8367C_ACT78_GPIO_MASK    0x20\n#define    RTL8367C_ACT78_FORWARD_OFFSET    4\n#define    RTL8367C_ACT78_FORWARD_MASK    0x10\n#define    RTL8367C_ACT78_POLICING_OFFSET    3\n#define    RTL8367C_ACT78_POLICING_MASK    0x8\n#define    RTL8367C_ACT78_PRIORITY_OFFSET    2\n#define    RTL8367C_ACT78_PRIORITY_MASK    0x4\n#define    RTL8367C_ACT78_SVID_OFFSET    1\n#define    RTL8367C_ACT78_SVID_MASK    0x2\n#define    RTL8367C_ACT78_CVID_OFFSET    0\n#define    RTL8367C_ACT78_CVID_MASK    0x1\n\n#define    RTL8367C_REG_ACL_ACTION_CTRL40    0x06F8\n#define    RTL8367C_OP81_NOT_OFFSET    14\n#define    RTL8367C_OP81_NOT_MASK    0x4000\n#define    RTL8367C_ACT81_GPIO_OFFSET    13\n#define    RTL8367C_ACT81_GPIO_MASK    0x2000\n#define    RTL8367C_ACT81_FORWARD_OFFSET    12\n#define    RTL8367C_ACT81_FORWARD_MASK    0x1000\n#define    RTL8367C_ACT81_POLICING_OFFSET    11\n#define    RTL8367C_ACT81_POLICING_MASK    0x800\n#define    RTL8367C_ACT81_PRIORITY_OFFSET    10\n#define    RTL8367C_ACT81_PRIORITY_MASK    0x400\n#define    RTL8367C_ACT81_SVID_OFFSET    9\n#define    RTL8367C_ACT81_SVID_MASK    0x200\n#define    RTL8367C_ACT81_CVID_OFFSET    8\n#define    RTL8367C_ACT81_CVID_MASK    0x100\n#define    RTL8367C_OP80_NOT_OFFSET    6\n#define    RTL8367C_OP80_NOT_MASK    0x40\n#define    RTL8367C_ACT80_GPIO_OFFSET    5\n#define    RTL8367C_ACT80_GPIO_MASK    0x20\n#define    RTL8367C_ACT80_FORWARD_OFFSET    4\n#define    RTL8367C_ACT80_FORWARD_MASK    0x10\n#define    RTL8367C_ACT80_POLICING_OFFSET    3\n#define    RTL8367C_ACT80_POLICING_MASK    0x8\n#define    RTL8367C_ACT80_PRIORITY_OFFSET    2\n#define    RTL8367C_ACT80_PRIORITY_MASK    0x4\n#define    RTL8367C_ACT80_SVID_OFFSET    1\n#define    RTL8367C_ACT80_SVID_MASK    0x2\n#define    RTL8367C_ACT80_CVID_OFFSET    0\n#define    RTL8367C_ACT80_CVID_MASK    0x1\n\n#define    RTL8367C_REG_ACL_ACTION_CTRL41    0x06F9\n#define    RTL8367C_OP83_NOT_OFFSET    14\n#define    RTL8367C_OP83_NOT_MASK    0x4000\n#define    RTL8367C_ACT83_GPIO_OFFSET    13\n#define    RTL8367C_ACT83_GPIO_MASK    0x2000\n#define    RTL8367C_ACT83_FORWARD_OFFSET    12\n#define    RTL8367C_ACT83_FORWARD_MASK    0x1000\n#define    RTL8367C_ACT83_POLICING_OFFSET    11\n#define    RTL8367C_ACT83_POLICING_MASK    0x800\n#define    RTL8367C_ACT83_PRIORITY_OFFSET    10\n#define    RTL8367C_ACT83_PRIORITY_MASK    0x400\n#define    RTL8367C_ACT83_SVID_OFFSET    9\n#define    RTL8367C_ACT83_SVID_MASK    0x200\n#define    RTL8367C_ACT83_CVID_OFFSET    8\n#define    RTL8367C_ACT83_CVID_MASK    0x100\n#define    RTL8367C_OP82_NOT_OFFSET    6\n#define    RTL8367C_OP82_NOT_MASK    0x40\n#define    RTL8367C_ACT82_GPIO_OFFSET    5\n#define    RTL8367C_ACT82_GPIO_MASK    0x20\n#define    RTL8367C_ACT82_FORWARD_OFFSET    4\n#define    RTL8367C_ACT82_FORWARD_MASK    0x10\n#define    RTL8367C_ACT82_POLICING_OFFSET    3\n#define    RTL8367C_ACT82_POLICING_MASK    0x8\n#define    RTL8367C_ACT82_PRIORITY_OFFSET    2\n#define    RTL8367C_ACT82_PRIORITY_MASK    0x4\n#define    RTL8367C_ACT82_SVID_OFFSET    1\n#define    RTL8367C_ACT82_SVID_MASK    0x2\n#define    RTL8367C_ACT82_CVID_OFFSET    0\n#define    RTL8367C_ACT82_CVID_MASK    0x1\n\n#define    RTL8367C_REG_ACL_ACTION_CTRL42    0x06FA\n#define    RTL8367C_OP85_NOT_OFFSET    14\n#define    RTL8367C_OP85_NOT_MASK    0x4000\n#define    RTL8367C_ACT85_GPIO_OFFSET    13\n#define    RTL8367C_ACT85_GPIO_MASK    0x2000\n#define    RTL8367C_ACT85_FORWARD_OFFSET    12\n#define    RTL8367C_ACT85_FORWARD_MASK    0x1000\n#define    RTL8367C_ACT85_POLICING_OFFSET    11\n#define    RTL8367C_ACT85_POLICING_MASK    0x800\n#define    RTL8367C_ACT85_PRIORITY_OFFSET    10\n#define    RTL8367C_ACT85_PRIORITY_MASK    0x400\n#define    RTL8367C_ACT85_SVID_OFFSET    9\n#define    RTL8367C_ACT85_SVID_MASK    0x200\n#define    RTL8367C_ACT85_CVID_OFFSET    8\n#define    RTL8367C_ACT85_CVID_MASK    0x100\n#define    RTL8367C_OP84_NOT_OFFSET    6\n#define    RTL8367C_OP84_NOT_MASK    0x40\n#define    RTL8367C_ACT84_GPIO_OFFSET    5\n#define    RTL8367C_ACT84_GPIO_MASK    0x20\n#define    RTL8367C_ACT84_FORWARD_OFFSET    4\n#define    RTL8367C_ACT84_FORWARD_MASK    0x10\n#define    RTL8367C_ACT84_POLICING_OFFSET    3\n#define    RTL8367C_ACT84_POLICING_MASK    0x8\n#define    RTL8367C_ACT84_PRIORITY_OFFSET    2\n#define    RTL8367C_ACT84_PRIORITY_MASK    0x4\n#define    RTL8367C_ACT84_SVID_OFFSET    1\n#define    RTL8367C_ACT84_SVID_MASK    0x2\n#define    RTL8367C_ACT84_CVID_OFFSET    0\n#define    RTL8367C_ACT84_CVID_MASK    0x1\n\n#define    RTL8367C_REG_ACL_ACTION_CTRL43    0x06FB\n#define    RTL8367C_OP87_NOT_OFFSET    14\n#define    RTL8367C_OP87_NOT_MASK    0x4000\n#define    RTL8367C_ACT87_GPIO_OFFSET    13\n#define    RTL8367C_ACT87_GPIO_MASK    0x2000\n#define    RTL8367C_ACT87_FORWARD_OFFSET    12\n#define    RTL8367C_ACT87_FORWARD_MASK    0x1000\n#define    RTL8367C_ACT87_POLICING_OFFSET    11\n#define    RTL8367C_ACT87_POLICING_MASK    0x800\n#define    RTL8367C_ACT87_PRIORITY_OFFSET    10\n#define    RTL8367C_ACT87_PRIORITY_MASK    0x400\n#define    RTL8367C_ACT87_SVID_OFFSET    9\n#define    RTL8367C_ACT87_SVID_MASK    0x200\n#define    RTL8367C_ACT87_CVID_OFFSET    8\n#define    RTL8367C_ACT87_CVID_MASK    0x100\n#define    RTL8367C_OP86_NOT_OFFSET    6\n#define    RTL8367C_OP86_NOT_MASK    0x40\n#define    RTL8367C_ACT86_GPIO_OFFSET    5\n#define    RTL8367C_ACT86_GPIO_MASK    0x20\n#define    RTL8367C_ACT86_FORWARD_OFFSET    4\n#define    RTL8367C_ACT86_FORWARD_MASK    0x10\n#define    RTL8367C_ACT86_POLICING_OFFSET    3\n#define    RTL8367C_ACT86_POLICING_MASK    0x8\n#define    RTL8367C_ACT86_PRIORITY_OFFSET    2\n#define    RTL8367C_ACT86_PRIORITY_MASK    0x4\n#define    RTL8367C_ACT86_SVID_OFFSET    1\n#define    RTL8367C_ACT86_SVID_MASK    0x2\n#define    RTL8367C_ACT86_CVID_OFFSET    0\n#define    RTL8367C_ACT86_CVID_MASK    0x1\n\n#define    RTL8367C_REG_ACL_ACTION_CTRL44    0x06FC\n#define    RTL8367C_OP89_NOT_OFFSET    14\n#define    RTL8367C_OP89_NOT_MASK    0x4000\n#define    RTL8367C_ACT89_GPIO_OFFSET    13\n#define    RTL8367C_ACT89_GPIO_MASK    0x2000\n#define    RTL8367C_ACT89_FORWARD_OFFSET    12\n#define    RTL8367C_ACT89_FORWARD_MASK    0x1000\n#define    RTL8367C_ACT89_POLICING_OFFSET    11\n#define    RTL8367C_ACT89_POLICING_MASK    0x800\n#define    RTL8367C_ACT89_PRIORITY_OFFSET    10\n#define    RTL8367C_ACT89_PRIORITY_MASK    0x400\n#define    RTL8367C_ACT89_SVID_OFFSET    9\n#define    RTL8367C_ACT89_SVID_MASK    0x200\n#define    RTL8367C_ACT89_CVID_OFFSET    8\n#define    RTL8367C_ACT89_CVID_MASK    0x100\n#define    RTL8367C_OP88_NOT_OFFSET    6\n#define    RTL8367C_OP88_NOT_MASK    0x40\n#define    RTL8367C_ACT88_GPIO_OFFSET    5\n#define    RTL8367C_ACT88_GPIO_MASK    0x20\n#define    RTL8367C_ACT88_FORWARD_OFFSET    4\n#define    RTL8367C_ACT88_FORWARD_MASK    0x10\n#define    RTL8367C_ACT88_POLICING_OFFSET    3\n#define    RTL8367C_ACT88_POLICING_MASK    0x8\n#define    RTL8367C_ACT88_PRIORITY_OFFSET    2\n#define    RTL8367C_ACT88_PRIORITY_MASK    0x4\n#define    RTL8367C_ACT88_SVID_OFFSET    1\n#define    RTL8367C_ACT88_SVID_MASK    0x2\n#define    RTL8367C_ACT88_CVID_OFFSET    0\n#define    RTL8367C_ACT88_CVID_MASK    0x1\n\n#define    RTL8367C_REG_ACL_ACTION_CTRL45    0x06FD\n#define    RTL8367C_OP91_NOT_OFFSET    14\n#define    RTL8367C_OP91_NOT_MASK    0x4000\n#define    RTL8367C_ACT91_GPIO_OFFSET    13\n#define    RTL8367C_ACT91_GPIO_MASK    0x2000\n#define    RTL8367C_ACT91_FORWARD_OFFSET    12\n#define    RTL8367C_ACT91_FORWARD_MASK    0x1000\n#define    RTL8367C_ACT91_POLICING_OFFSET    11\n#define    RTL8367C_ACT91_POLICING_MASK    0x800\n#define    RTL8367C_ACT91_PRIORITY_OFFSET    10\n#define    RTL8367C_ACT91_PRIORITY_MASK    0x400\n#define    RTL8367C_ACT91_SVID_OFFSET    9\n#define    RTL8367C_ACT91_SVID_MASK    0x200\n#define    RTL8367C_ACT91_CVID_OFFSET    8\n#define    RTL8367C_ACT91_CVID_MASK    0x100\n#define    RTL8367C_OP90_NOT_OFFSET    6\n#define    RTL8367C_OP90_NOT_MASK    0x40\n#define    RTL8367C_ACT90_GPIO_OFFSET    5\n#define    RTL8367C_ACT90_GPIO_MASK    0x20\n#define    RTL8367C_ACT90_FORWARD_OFFSET    4\n#define    RTL8367C_ACT90_FORWARD_MASK    0x10\n#define    RTL8367C_ACT90_POLICING_OFFSET    3\n#define    RTL8367C_ACT90_POLICING_MASK    0x8\n#define    RTL8367C_ACT90_PRIORITY_OFFSET    2\n#define    RTL8367C_ACT90_PRIORITY_MASK    0x4\n#define    RTL8367C_ACT90_SVID_OFFSET    1\n#define    RTL8367C_ACT90_SVID_MASK    0x2\n#define    RTL8367C_ACT90_CVID_OFFSET    0\n#define    RTL8367C_ACT90_CVID_MASK    0x1\n\n#define    RTL8367C_REG_ACL_ACTION_CTRL46    0x06FE\n#define    RTL8367C_OP93_NOT_OFFSET    14\n#define    RTL8367C_OP93_NOT_MASK    0x4000\n#define    RTL8367C_ACT93_GPIO_OFFSET    13\n#define    RTL8367C_ACT93_GPIO_MASK    0x2000\n#define    RTL8367C_ACT93_FORWARD_OFFSET    12\n#define    RTL8367C_ACT93_FORWARD_MASK    0x1000\n#define    RTL8367C_ACT93_POLICING_OFFSET    11\n#define    RTL8367C_ACT93_POLICING_MASK    0x800\n#define    RTL8367C_ACT93_PRIORITY_OFFSET    10\n#define    RTL8367C_ACT93_PRIORITY_MASK    0x400\n#define    RTL8367C_ACT93_SVID_OFFSET    9\n#define    RTL8367C_ACT93_SVID_MASK    0x200\n#define    RTL8367C_ACT93_CVID_OFFSET    8\n#define    RTL8367C_ACT93_CVID_MASK    0x100\n#define    RTL8367C_OP92_NOT_OFFSET    6\n#define    RTL8367C_OP92_NOT_MASK    0x40\n#define    RTL8367C_ACT92_GPIO_OFFSET    5\n#define    RTL8367C_ACT92_GPIO_MASK    0x20\n#define    RTL8367C_ACT92_FORWARD_OFFSET    4\n#define    RTL8367C_ACT92_FORWARD_MASK    0x10\n#define    RTL8367C_ACT92_POLICING_OFFSET    3\n#define    RTL8367C_ACT92_POLICING_MASK    0x8\n#define    RTL8367C_ACT92_PRIORITY_OFFSET    2\n#define    RTL8367C_ACT92_PRIORITY_MASK    0x4\n#define    RTL8367C_ACT92_SVID_OFFSET    1\n#define    RTL8367C_ACT92_SVID_MASK    0x2\n#define    RTL8367C_ACT92_CVID_OFFSET    0\n#define    RTL8367C_ACT92_CVID_MASK    0x1\n\n#define    RTL8367C_REG_ACL_ACTION_CTRL47    0x06FF\n#define    RTL8367C_OP95_NOT_OFFSET    14\n#define    RTL8367C_OP95_NOT_MASK    0x4000\n#define    RTL8367C_ACT95_GPIO_OFFSET    13\n#define    RTL8367C_ACT95_GPIO_MASK    0x2000\n#define    RTL8367C_ACT95_FORWARD_OFFSET    12\n#define    RTL8367C_ACT95_FORWARD_MASK    0x1000\n#define    RTL8367C_ACT95_POLICING_OFFSET    11\n#define    RTL8367C_ACT95_POLICING_MASK    0x800\n#define    RTL8367C_ACT95_PRIORITY_OFFSET    10\n#define    RTL8367C_ACT95_PRIORITY_MASK    0x400\n#define    RTL8367C_ACT95_SVID_OFFSET    9\n#define    RTL8367C_ACT95_SVID_MASK    0x200\n#define    RTL8367C_ACT95_CVID_OFFSET    8\n#define    RTL8367C_ACT95_CVID_MASK    0x100\n#define    RTL8367C_OP94_NOT_OFFSET    6\n#define    RTL8367C_OP94_NOT_MASK    0x40\n#define    RTL8367C_ACT94_GPIO_OFFSET    5\n#define    RTL8367C_ACT94_GPIO_MASK    0x20\n#define    RTL8367C_ACT94_FORWARD_OFFSET    4\n#define    RTL8367C_ACT94_FORWARD_MASK    0x10\n#define    RTL8367C_ACT94_POLICING_OFFSET    3\n#define    RTL8367C_ACT94_POLICING_MASK    0x8\n#define    RTL8367C_ACT94_PRIORITY_OFFSET    2\n#define    RTL8367C_ACT94_PRIORITY_MASK    0x4\n#define    RTL8367C_ACT94_SVID_OFFSET    1\n#define    RTL8367C_ACT94_SVID_MASK    0x2\n#define    RTL8367C_ACT94_CVID_OFFSET    0\n#define    RTL8367C_ACT94_CVID_MASK    0x1\n\n/* (16'h0700)cvlan_reg */\n\n#define    RTL8367C_REG_VLAN_PVID_CTRL0    0x0700\n#define    RTL8367C_PORT1_VIDX_OFFSET    8\n#define    RTL8367C_PORT1_VIDX_MASK    0x1F00\n#define    RTL8367C_PORT0_VIDX_OFFSET    0\n#define    RTL8367C_PORT0_VIDX_MASK    0x1F\n\n#define    RTL8367C_REG_VLAN_PVID_CTRL1    0x0701\n#define    RTL8367C_PORT3_VIDX_OFFSET    8\n#define    RTL8367C_PORT3_VIDX_MASK    0x1F00\n#define    RTL8367C_PORT2_VIDX_OFFSET    0\n#define    RTL8367C_PORT2_VIDX_MASK    0x1F\n\n#define    RTL8367C_REG_VLAN_PVID_CTRL2    0x0702\n#define    RTL8367C_PORT5_VIDX_OFFSET    8\n#define    RTL8367C_PORT5_VIDX_MASK    0x1F00\n#define    RTL8367C_PORT4_VIDX_OFFSET    0\n#define    RTL8367C_PORT4_VIDX_MASK    0x1F\n\n#define    RTL8367C_REG_VLAN_PVID_CTRL3    0x0703\n#define    RTL8367C_PORT7_VIDX_OFFSET    8\n#define    RTL8367C_PORT7_VIDX_MASK    0x1F00\n#define    RTL8367C_PORT6_VIDX_OFFSET    0\n#define    RTL8367C_PORT6_VIDX_MASK    0x1F\n\n#define    RTL8367C_REG_VLAN_PVID_CTRL4    0x0704\n#define    RTL8367C_PORT9_VIDX_OFFSET    8\n#define    RTL8367C_PORT9_VIDX_MASK    0x1F00\n#define    RTL8367C_PORT8_VIDX_OFFSET    0\n#define    RTL8367C_PORT8_VIDX_MASK    0x1F\n\n#define    RTL8367C_REG_VLAN_PVID_CTRL5    0x0705\n#define    RTL8367C_VLAN_PVID_CTRL5_OFFSET    0\n#define    RTL8367C_VLAN_PVID_CTRL5_MASK    0x1F\n\n#define    RTL8367C_REG_VLAN_PPB0_VALID    0x0708\n#define    RTL8367C_VLAN_PPB0_VALID_VALID_EXT_OFFSET    8\n#define    RTL8367C_VLAN_PPB0_VALID_VALID_EXT_MASK    0x700\n#define    RTL8367C_VLAN_PPB0_VALID_VALID_OFFSET    0\n#define    RTL8367C_VLAN_PPB0_VALID_VALID_MASK    0xFF\n\n#define    RTL8367C_REG_VLAN_PPB0_CTRL0    0x0709\n#define    RTL8367C_VLAN_PPB0_CTRL0_PORT2_INDEX_OFFSET    10\n#define    RTL8367C_VLAN_PPB0_CTRL0_PORT2_INDEX_MASK    0x7C00\n#define    RTL8367C_VLAN_PPB0_CTRL0_PORT1_INDEX_OFFSET    5\n#define    RTL8367C_VLAN_PPB0_CTRL0_PORT1_INDEX_MASK    0x3E0\n#define    RTL8367C_VLAN_PPB0_CTRL0_PORT0_INDEX_OFFSET    0\n#define    RTL8367C_VLAN_PPB0_CTRL0_PORT0_INDEX_MASK    0x1F\n\n#define    RTL8367C_REG_VLAN_PPB0_CTRL1    0x070a\n#define    RTL8367C_VLAN_PPB0_CTRL1_PORT5_INDEX_OFFSET    10\n#define    RTL8367C_VLAN_PPB0_CTRL1_PORT5_INDEX_MASK    0x7C00\n#define    RTL8367C_VLAN_PPB0_CTRL1_PORT4_INDEX_OFFSET    5\n#define    RTL8367C_VLAN_PPB0_CTRL1_PORT4_INDEX_MASK    0x3E0\n#define    RTL8367C_VLAN_PPB0_CTRL1_PORT3_INDEX_OFFSET    0\n#define    RTL8367C_VLAN_PPB0_CTRL1_PORT3_INDEX_MASK    0x1F\n\n#define    RTL8367C_REG_VLAN_PPB0_CTRL2    0x070b\n#define    RTL8367C_VLAN_PPB0_CTRL2_FRAME_TYPE_OFFSET    10\n#define    RTL8367C_VLAN_PPB0_CTRL2_FRAME_TYPE_MASK    0xC00\n#define    RTL8367C_VLAN_PPB0_CTRL2_PORT7_INDEX_OFFSET    5\n#define    RTL8367C_VLAN_PPB0_CTRL2_PORT7_INDEX_MASK    0x3E0\n#define    RTL8367C_VLAN_PPB0_CTRL2_PORT6_INDEX_OFFSET    0\n#define    RTL8367C_VLAN_PPB0_CTRL2_PORT6_INDEX_MASK    0x1F\n\n#define    RTL8367C_REG_VLAN_PPB0_CTRL4    0x070c\n#define    RTL8367C_VLAN_PPB0_CTRL4_PORT10_INDEX_OFFSET    10\n#define    RTL8367C_VLAN_PPB0_CTRL4_PORT10_INDEX_MASK    0x7C00\n#define    RTL8367C_VLAN_PPB0_CTRL4_PORT9_INDEX_OFFSET    5\n#define    RTL8367C_VLAN_PPB0_CTRL4_PORT9_INDEX_MASK    0x3E0\n#define    RTL8367C_VLAN_PPB0_CTRL4_PORT8_INDEX_OFFSET    0\n#define    RTL8367C_VLAN_PPB0_CTRL4_PORT8_INDEX_MASK    0x1F\n\n#define    RTL8367C_REG_VLAN_PPB0_CTRL3    0x070f\n\n#define    RTL8367C_REG_VLAN_PPB1_VALID    0x0710\n#define    RTL8367C_VLAN_PPB1_VALID_VALID_EXT_OFFSET    8\n#define    RTL8367C_VLAN_PPB1_VALID_VALID_EXT_MASK    0x700\n#define    RTL8367C_VLAN_PPB1_VALID_VALID_OFFSET    0\n#define    RTL8367C_VLAN_PPB1_VALID_VALID_MASK    0xFF\n\n#define    RTL8367C_REG_VLAN_PPB1_CTRL0    0x0711\n#define    RTL8367C_VLAN_PPB1_CTRL0_PORT2_INDEX_OFFSET    10\n#define    RTL8367C_VLAN_PPB1_CTRL0_PORT2_INDEX_MASK    0x7C00\n#define    RTL8367C_VLAN_PPB1_CTRL0_PORT1_INDEX_OFFSET    5\n#define    RTL8367C_VLAN_PPB1_CTRL0_PORT1_INDEX_MASK    0x3E0\n#define    RTL8367C_VLAN_PPB1_CTRL0_PORT0_INDEX_OFFSET    0\n#define    RTL8367C_VLAN_PPB1_CTRL0_PORT0_INDEX_MASK    0x1F\n\n#define    RTL8367C_REG_VLAN_PPB1_CTRL1    0x0712\n#define    RTL8367C_VLAN_PPB1_CTRL1_PORT5_INDEX_OFFSET    10\n#define    RTL8367C_VLAN_PPB1_CTRL1_PORT5_INDEX_MASK    0x7C00\n#define    RTL8367C_VLAN_PPB1_CTRL1_PORT4_INDEX_OFFSET    5\n#define    RTL8367C_VLAN_PPB1_CTRL1_PORT4_INDEX_MASK    0x3E0\n#define    RTL8367C_VLAN_PPB1_CTRL1_PORT3_INDEX_OFFSET    0\n#define    RTL8367C_VLAN_PPB1_CTRL1_PORT3_INDEX_MASK    0x1F\n\n#define    RTL8367C_REG_VLAN_PPB1_CTRL2    0x0713\n#define    RTL8367C_VLAN_PPB1_CTRL2_FRAME_TYPE_OFFSET    10\n#define    RTL8367C_VLAN_PPB1_CTRL2_FRAME_TYPE_MASK    0xC00\n#define    RTL8367C_VLAN_PPB1_CTRL2_PORT7_INDEX_OFFSET    5\n#define    RTL8367C_VLAN_PPB1_CTRL2_PORT7_INDEX_MASK    0x3E0\n#define    RTL8367C_VLAN_PPB1_CTRL2_PORT6_INDEX_OFFSET    0\n#define    RTL8367C_VLAN_PPB1_CTRL2_PORT6_INDEX_MASK    0x1F\n\n#define    RTL8367C_REG_VLAN_PPB1_CTRL4    0x0714\n#define    RTL8367C_VLAN_PPB1_CTRL4_PORT10_INDEX_OFFSET    10\n#define    RTL8367C_VLAN_PPB1_CTRL4_PORT10_INDEX_MASK    0x7C00\n#define    RTL8367C_VLAN_PPB1_CTRL4_PORT9_INDEX_OFFSET    5\n#define    RTL8367C_VLAN_PPB1_CTRL4_PORT9_INDEX_MASK    0x3E0\n#define    RTL8367C_VLAN_PPB1_CTRL4_PORT8_INDEX_OFFSET    0\n#define    RTL8367C_VLAN_PPB1_CTRL4_PORT8_INDEX_MASK    0x1F\n\n#define    RTL8367C_REG_VLAN_PPB1_CTRL3    0x0717\n\n#define    RTL8367C_REG_VLAN_PPB2_VALID    0x0718\n#define    RTL8367C_VLAN_PPB2_VALID_VALID_EXT_OFFSET    8\n#define    RTL8367C_VLAN_PPB2_VALID_VALID_EXT_MASK    0x700\n#define    RTL8367C_VLAN_PPB2_VALID_VALID_OFFSET    0\n#define    RTL8367C_VLAN_PPB2_VALID_VALID_MASK    0xFF\n\n#define    RTL8367C_REG_VLAN_PPB2_CTRL0    0x0719\n#define    RTL8367C_VLAN_PPB2_CTRL0_PORT2_INDEX_OFFSET    10\n#define    RTL8367C_VLAN_PPB2_CTRL0_PORT2_INDEX_MASK    0x7C00\n#define    RTL8367C_VLAN_PPB2_CTRL0_PORT1_INDEX_OFFSET    5\n#define    RTL8367C_VLAN_PPB2_CTRL0_PORT1_INDEX_MASK    0x3E0\n#define    RTL8367C_VLAN_PPB2_CTRL0_PORT0_INDEX_OFFSET    0\n#define    RTL8367C_VLAN_PPB2_CTRL0_PORT0_INDEX_MASK    0x1F\n\n#define    RTL8367C_REG_VLAN_PPB2_CTRL1    0x071a\n#define    RTL8367C_VLAN_PPB2_CTRL1_PORT5_INDEX_OFFSET    10\n#define    RTL8367C_VLAN_PPB2_CTRL1_PORT5_INDEX_MASK    0x7C00\n#define    RTL8367C_VLAN_PPB2_CTRL1_PORT4_INDEX_OFFSET    5\n#define    RTL8367C_VLAN_PPB2_CTRL1_PORT4_INDEX_MASK    0x3E0\n#define    RTL8367C_VLAN_PPB2_CTRL1_PORT3_INDEX_OFFSET    0\n#define    RTL8367C_VLAN_PPB2_CTRL1_PORT3_INDEX_MASK    0x1F\n\n#define    RTL8367C_REG_VLAN_PPB2_CTRL2    0x071b\n#define    RTL8367C_VLAN_PPB2_CTRL2_FRAME_TYPE_OFFSET    10\n#define    RTL8367C_VLAN_PPB2_CTRL2_FRAME_TYPE_MASK    0xC00\n#define    RTL8367C_VLAN_PPB2_CTRL2_PORT7_INDEX_OFFSET    5\n#define    RTL8367C_VLAN_PPB2_CTRL2_PORT7_INDEX_MASK    0x3E0\n#define    RTL8367C_VLAN_PPB2_CTRL2_PORT6_INDEX_OFFSET    0\n#define    RTL8367C_VLAN_PPB2_CTRL2_PORT6_INDEX_MASK    0x1F\n\n#define    RTL8367C_REG_VLAN_PPB2_CTRL4    0x071c\n#define    RTL8367C_VLAN_PPB2_CTRL4_PORT10_INDEX_OFFSET    10\n#define    RTL8367C_VLAN_PPB2_CTRL4_PORT10_INDEX_MASK    0x7C00\n#define    RTL8367C_VLAN_PPB2_CTRL4_PORT9_INDEX_OFFSET    5\n#define    RTL8367C_VLAN_PPB2_CTRL4_PORT9_INDEX_MASK    0x3E0\n#define    RTL8367C_VLAN_PPB2_CTRL4_PORT8_INDEX_OFFSET    0\n#define    RTL8367C_VLAN_PPB2_CTRL4_PORT8_INDEX_MASK    0x1F\n\n#define    RTL8367C_REG_VLAN_PPB2_CTRL3    0x071f\n\n#define    RTL8367C_REG_VLAN_PPB3_VALID    0x0720\n#define    RTL8367C_VLAN_PPB3_VALID_VALID_EXT_OFFSET    8\n#define    RTL8367C_VLAN_PPB3_VALID_VALID_EXT_MASK    0x700\n#define    RTL8367C_VLAN_PPB3_VALID_VALID_OFFSET    0\n#define    RTL8367C_VLAN_PPB3_VALID_VALID_MASK    0xFF\n\n#define    RTL8367C_REG_VLAN_PPB3_CTRL0    0x0721\n#define    RTL8367C_VLAN_PPB3_CTRL0_PORT2_INDEX_OFFSET    10\n#define    RTL8367C_VLAN_PPB3_CTRL0_PORT2_INDEX_MASK    0x7C00\n#define    RTL8367C_VLAN_PPB3_CTRL0_PORT1_INDEX_OFFSET    5\n#define    RTL8367C_VLAN_PPB3_CTRL0_PORT1_INDEX_MASK    0x3E0\n#define    RTL8367C_VLAN_PPB3_CTRL0_PORT0_INDEX_OFFSET    0\n#define    RTL8367C_VLAN_PPB3_CTRL0_PORT0_INDEX_MASK    0x1F\n\n#define    RTL8367C_REG_VLAN_PPB3_CTRL1    0x0722\n#define    RTL8367C_VLAN_PPB3_CTRL1_PORT5_INDEX_OFFSET    10\n#define    RTL8367C_VLAN_PPB3_CTRL1_PORT5_INDEX_MASK    0x7C00\n#define    RTL8367C_VLAN_PPB3_CTRL1_PORT4_INDEX_OFFSET    5\n#define    RTL8367C_VLAN_PPB3_CTRL1_PORT4_INDEX_MASK    0x3E0\n#define    RTL8367C_VLAN_PPB3_CTRL1_PORT3_INDEX_OFFSET    0\n#define    RTL8367C_VLAN_PPB3_CTRL1_PORT3_INDEX_MASK    0x1F\n\n#define    RTL8367C_REG_VLAN_PPB3_CTRL2    0x0723\n#define    RTL8367C_VLAN_PPB3_CTRL2_FRAME_TYPE_OFFSET    10\n#define    RTL8367C_VLAN_PPB3_CTRL2_FRAME_TYPE_MASK    0xC00\n#define    RTL8367C_VLAN_PPB3_CTRL2_PORT7_INDEX_OFFSET    5\n#define    RTL8367C_VLAN_PPB3_CTRL2_PORT7_INDEX_MASK    0x3E0\n#define    RTL8367C_VLAN_PPB3_CTRL2_PORT6_INDEX_OFFSET    0\n#define    RTL8367C_VLAN_PPB3_CTRL2_PORT6_INDEX_MASK    0x1F\n\n#define    RTL8367C_REG_VLAN_PPB3_CTRL4    0x0724\n#define    RTL8367C_VLAN_PPB3_CTRL4_PORT10_INDEX_OFFSET    10\n#define    RTL8367C_VLAN_PPB3_CTRL4_PORT10_INDEX_MASK    0x7C00\n#define    RTL8367C_VLAN_PPB3_CTRL4_PORT9_INDEX_OFFSET    5\n#define    RTL8367C_VLAN_PPB3_CTRL4_PORT9_INDEX_MASK    0x3E0\n#define    RTL8367C_VLAN_PPB3_CTRL4_PORT8_INDEX_OFFSET    0\n#define    RTL8367C_VLAN_PPB3_CTRL4_PORT8_INDEX_MASK    0x1F\n\n#define    RTL8367C_REG_VLAN_PPB3_CTRL3    0x0727\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION0_CTRL0    0x0728\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION0_CTRL0_MBR_EXT_OFFSET    8\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION0_CTRL0_MBR_EXT_MASK    0x700\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION0_CTRL0_MBR_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION0_CTRL0_MBR_MASK    0xFF\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION0_CTRL1    0x0729\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION0_CTRL1_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION0_CTRL1_MASK    0xF\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION0_CTRL2    0x072a\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION0_CTRL2_METERIDX_EXT_OFFSET    10\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION0_CTRL2_METERIDX_EXT_MASK    0x400\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION0_CTRL2_METERIDX_OFFSET    5\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION0_CTRL2_METERIDX_MASK    0x3E0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION0_CTRL2_ENVLANPOL_OFFSET    4\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION0_CTRL2_ENVLANPOL_MASK    0x10\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION0_CTRL2_VBPRI_OFFSET    1\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION0_CTRL2_VBPRI_MASK    0xE\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION0_CTRL2_VBPEN_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION0_CTRL2_VBPEN_MASK    0x1\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION0_CTRL3    0x072b\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION0_CTRL3_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION0_CTRL3_MASK    0x1FFF\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION1_CTRL0    0x072c\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION1_CTRL0_MBR_EXT_OFFSET    8\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION1_CTRL0_MBR_EXT_MASK    0x700\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION1_CTRL0_MBR_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION1_CTRL0_MBR_MASK    0xFF\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION1_CTRL1    0x072d\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION1_CTRL1_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION1_CTRL1_MASK    0xF\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION1_CTRL2    0x072e\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION1_CTRL2_METERIDX_EXT_OFFSET    10\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION1_CTRL2_METERIDX_EXT_MASK    0x400\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION1_CTRL2_METERIDX_OFFSET    5\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION1_CTRL2_METERIDX_MASK    0x3E0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION1_CTRL2_ENVLANPOL_OFFSET    4\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION1_CTRL2_ENVLANPOL_MASK    0x10\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION1_CTRL2_VBPRI_OFFSET    1\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION1_CTRL2_VBPRI_MASK    0xE\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION1_CTRL2_VBPEN_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION1_CTRL2_VBPEN_MASK    0x1\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION1_CTRL3    0x072f\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION1_CTRL3_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION1_CTRL3_MASK    0x1FFF\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION2_CTRL0    0x0730\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION2_CTRL0_MBR_EXT_OFFSET    8\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION2_CTRL0_MBR_EXT_MASK    0x700\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION2_CTRL0_MBR_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION2_CTRL0_MBR_MASK    0xFF\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION2_CTRL1    0x0731\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION2_CTRL1_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION2_CTRL1_MASK    0xF\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION2_CTRL2    0x0732\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION2_CTRL2_METERIDX_EXT_OFFSET    10\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION2_CTRL2_METERIDX_EXT_MASK    0x400\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION2_CTRL2_METERIDX_OFFSET    5\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION2_CTRL2_METERIDX_MASK    0x3E0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION2_CTRL2_ENVLANPOL_OFFSET    4\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION2_CTRL2_ENVLANPOL_MASK    0x10\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION2_CTRL2_VBPRI_OFFSET    1\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION2_CTRL2_VBPRI_MASK    0xE\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION2_CTRL2_VBPEN_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION2_CTRL2_VBPEN_MASK    0x1\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION2_CTRL3    0x0733\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION2_CTRL3_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION2_CTRL3_MASK    0x1FFF\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION3_CTRL0    0x0734\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION3_CTRL0_MBR_EXT_OFFSET    8\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION3_CTRL0_MBR_EXT_MASK    0x700\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION3_CTRL0_MBR_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION3_CTRL0_MBR_MASK    0xFF\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION3_CTRL1    0x0735\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION3_CTRL1_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION3_CTRL1_MASK    0xF\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION3_CTRL2    0x0736\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION3_CTRL2_METERIDX_EXT_OFFSET    10\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION3_CTRL2_METERIDX_EXT_MASK    0x400\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION3_CTRL2_METERIDX_OFFSET    5\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION3_CTRL2_METERIDX_MASK    0x3E0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION3_CTRL2_ENVLANPOL_OFFSET    4\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION3_CTRL2_ENVLANPOL_MASK    0x10\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION3_CTRL2_VBPRI_OFFSET    1\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION3_CTRL2_VBPRI_MASK    0xE\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION3_CTRL2_VBPEN_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION3_CTRL2_VBPEN_MASK    0x1\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION3_CTRL3    0x0737\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION3_CTRL3_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION3_CTRL3_MASK    0x1FFF\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION4_CTRL0    0x0738\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION4_CTRL0_MBR_EXT_OFFSET    8\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION4_CTRL0_MBR_EXT_MASK    0x700\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION4_CTRL0_MBR_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION4_CTRL0_MBR_MASK    0xFF\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION4_CTRL1    0x0739\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION4_CTRL1_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION4_CTRL1_MASK    0xF\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION4_CTRL2    0x073a\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION4_CTRL2_METERIDX_EXT_OFFSET    10\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION4_CTRL2_METERIDX_EXT_MASK    0x400\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION4_CTRL2_METERIDX_OFFSET    5\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION4_CTRL2_METERIDX_MASK    0x3E0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION4_CTRL2_ENVLANPOL_OFFSET    4\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION4_CTRL2_ENVLANPOL_MASK    0x10\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION4_CTRL2_VBPRI_OFFSET    1\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION4_CTRL2_VBPRI_MASK    0xE\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION4_CTRL2_VBPEN_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION4_CTRL2_VBPEN_MASK    0x1\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION4_CTRL3    0x073b\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION4_CTRL3_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION4_CTRL3_MASK    0x1FFF\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION5_CTRL0    0x073c\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION5_CTRL0_MBR_EXT_OFFSET    8\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION5_CTRL0_MBR_EXT_MASK    0x700\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION5_CTRL0_MBR_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION5_CTRL0_MBR_MASK    0xFF\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION5_CTRL1    0x073d\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION5_CTRL1_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION5_CTRL1_MASK    0xF\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION5_CTRL2    0x073e\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION5_CTRL2_METERIDX_EXT_OFFSET    10\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION5_CTRL2_METERIDX_EXT_MASK    0x400\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION5_CTRL2_METERIDX_OFFSET    5\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION5_CTRL2_METERIDX_MASK    0x3E0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION5_CTRL2_ENVLANPOL_OFFSET    4\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION5_CTRL2_ENVLANPOL_MASK    0x10\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION5_CTRL2_VBPRI_OFFSET    1\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION5_CTRL2_VBPRI_MASK    0xE\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION5_CTRL2_VBPEN_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION5_CTRL2_VBPEN_MASK    0x1\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION5_CTRL3    0x073f\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION5_CTRL3_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION5_CTRL3_MASK    0x1FFF\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION6_CTRL0    0x0740\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION6_CTRL0_MBR_EXT_OFFSET    8\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION6_CTRL0_MBR_EXT_MASK    0x700\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION6_CTRL0_MBR_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION6_CTRL0_MBR_MASK    0xFF\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION6_CTRL1    0x0741\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION6_CTRL1_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION6_CTRL1_MASK    0xF\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION6_CTRL2    0x0742\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION6_CTRL2_METERIDX_EXT_OFFSET    10\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION6_CTRL2_METERIDX_EXT_MASK    0x400\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION6_CTRL2_METERIDX_OFFSET    5\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION6_CTRL2_METERIDX_MASK    0x3E0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION6_CTRL2_ENVLANPOL_OFFSET    4\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION6_CTRL2_ENVLANPOL_MASK    0x10\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION6_CTRL2_VBPRI_OFFSET    1\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION6_CTRL2_VBPRI_MASK    0xE\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION6_CTRL2_VBPEN_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION6_CTRL2_VBPEN_MASK    0x1\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION6_CTRL3    0x0743\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION6_CTRL3_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION6_CTRL3_MASK    0x1FFF\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION7_CTRL0    0x0744\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION7_CTRL0_MBR_EXT_OFFSET    8\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION7_CTRL0_MBR_EXT_MASK    0x700\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION7_CTRL0_MBR_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION7_CTRL0_MBR_MASK    0xFF\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION7_CTRL1    0x0745\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION7_CTRL1_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION7_CTRL1_MASK    0xF\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION7_CTRL2    0x0746\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION7_CTRL2_METERIDX_EXT_OFFSET    10\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION7_CTRL2_METERIDX_EXT_MASK    0x400\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION7_CTRL2_METERIDX_OFFSET    5\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION7_CTRL2_METERIDX_MASK    0x3E0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION7_CTRL2_ENVLANPOL_OFFSET    4\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION7_CTRL2_ENVLANPOL_MASK    0x10\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION7_CTRL2_VBPRI_OFFSET    1\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION7_CTRL2_VBPRI_MASK    0xE\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION7_CTRL2_VBPEN_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION7_CTRL2_VBPEN_MASK    0x1\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION7_CTRL3    0x0747\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION7_CTRL3_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION7_CTRL3_MASK    0x1FFF\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION8_CTRL0    0x0748\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION8_CTRL0_MBR_EXT_OFFSET    8\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION8_CTRL0_MBR_EXT_MASK    0x700\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION8_CTRL0_MBR_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION8_CTRL0_MBR_MASK    0xFF\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION8_CTRL1    0x0749\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION8_CTRL1_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION8_CTRL1_MASK    0xF\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION8_CTRL2    0x074a\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION8_CTRL2_METERIDX_EXT_OFFSET    10\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION8_CTRL2_METERIDX_EXT_MASK    0x400\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION8_CTRL2_METERIDX_OFFSET    5\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION8_CTRL2_METERIDX_MASK    0x3E0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION8_CTRL2_ENVLANPOL_OFFSET    4\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION8_CTRL2_ENVLANPOL_MASK    0x10\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION8_CTRL2_VBPRI_OFFSET    1\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION8_CTRL2_VBPRI_MASK    0xE\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION8_CTRL2_VBPEN_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION8_CTRL2_VBPEN_MASK    0x1\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION8_CTRL3    0x074b\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION8_CTRL3_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION8_CTRL3_MASK    0x1FFF\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION9_CTRL0    0x074c\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION9_CTRL0_MBR_EXT_OFFSET    8\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION9_CTRL0_MBR_EXT_MASK    0x700\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION9_CTRL0_MBR_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION9_CTRL0_MBR_MASK    0xFF\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION9_CTRL1    0x074d\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION9_CTRL1_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION9_CTRL1_MASK    0xF\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION9_CTRL2    0x074e\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION9_CTRL2_METERIDX_EXT_OFFSET    10\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION9_CTRL2_METERIDX_EXT_MASK    0x400\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION9_CTRL2_METERIDX_OFFSET    5\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION9_CTRL2_METERIDX_MASK    0x3E0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION9_CTRL2_ENVLANPOL_OFFSET    4\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION9_CTRL2_ENVLANPOL_MASK    0x10\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION9_CTRL2_VBPRI_OFFSET    1\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION9_CTRL2_VBPRI_MASK    0xE\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION9_CTRL2_VBPEN_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION9_CTRL2_VBPEN_MASK    0x1\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION9_CTRL3    0x074f\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION9_CTRL3_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION9_CTRL3_MASK    0x1FFF\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION10_CTRL0    0x0750\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION10_CTRL0_MBR_EXT_OFFSET    8\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION10_CTRL0_MBR_EXT_MASK    0x700\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION10_CTRL0_MBR_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION10_CTRL0_MBR_MASK    0xFF\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION10_CTRL1    0x0751\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION10_CTRL1_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION10_CTRL1_MASK    0xF\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION10_CTRL2    0x0752\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION10_CTRL2_METERIDX_EXT_OFFSET    10\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION10_CTRL2_METERIDX_EXT_MASK    0x400\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION10_CTRL2_METERIDX_OFFSET    5\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION10_CTRL2_METERIDX_MASK    0x3E0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION10_CTRL2_ENVLANPOL_OFFSET    4\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION10_CTRL2_ENVLANPOL_MASK    0x10\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION10_CTRL2_VBPRI_OFFSET    1\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION10_CTRL2_VBPRI_MASK    0xE\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION10_CTRL2_VBPEN_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION10_CTRL2_VBPEN_MASK    0x1\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION10_CTRL3    0x0753\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION10_CTRL3_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION10_CTRL3_MASK    0x1FFF\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION11_CTRL0    0x0754\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION11_CTRL0_MBR_EXT_OFFSET    8\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION11_CTRL0_MBR_EXT_MASK    0x700\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION11_CTRL0_MBR_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION11_CTRL0_MBR_MASK    0xFF\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION11_CTRL1    0x0755\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION11_CTRL1_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION11_CTRL1_MASK    0xF\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION11_CTRL2    0x0756\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION11_CTRL2_METERIDX_EXT_OFFSET    10\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION11_CTRL2_METERIDX_EXT_MASK    0x400\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION11_CTRL2_METERIDX_OFFSET    5\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION11_CTRL2_METERIDX_MASK    0x3E0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION11_CTRL2_ENVLANPOL_OFFSET    4\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION11_CTRL2_ENVLANPOL_MASK    0x10\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION11_CTRL2_VBPRI_OFFSET    1\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION11_CTRL2_VBPRI_MASK    0xE\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION11_CTRL2_VBPEN_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION11_CTRL2_VBPEN_MASK    0x1\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION11_CTRL3    0x0757\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION11_CTRL3_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION11_CTRL3_MASK    0x1FFF\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION12_CTRL0    0x0758\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION12_CTRL0_MBR_EXT_OFFSET    8\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION12_CTRL0_MBR_EXT_MASK    0x700\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION12_CTRL0_MBR_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION12_CTRL0_MBR_MASK    0xFF\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION12_CTRL1    0x0759\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION12_CTRL1_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION12_CTRL1_MASK    0xF\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION12_CTRL2    0x075a\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION12_CTRL2_METERIDX_EXT_OFFSET    10\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION12_CTRL2_METERIDX_EXT_MASK    0x400\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION12_CTRL2_METERIDX_OFFSET    5\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION12_CTRL2_METERIDX_MASK    0x3E0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION12_CTRL2_ENVLANPOL_OFFSET    4\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION12_CTRL2_ENVLANPOL_MASK    0x10\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION12_CTRL2_VBPRI_OFFSET    1\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION12_CTRL2_VBPRI_MASK    0xE\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION12_CTRL2_VBPEN_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION12_CTRL2_VBPEN_MASK    0x1\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION12_CTRL3    0x075b\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION12_CTRL3_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION12_CTRL3_MASK    0x1FFF\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION13_CTRL0    0x075c\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION13_CTRL0_MBR_EXT_OFFSET    8\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION13_CTRL0_MBR_EXT_MASK    0x700\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION13_CTRL0_MBR_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION13_CTRL0_MBR_MASK    0xFF\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION13_CTRL1    0x075d\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION13_CTRL1_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION13_CTRL1_MASK    0xF\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION13_CTRL2    0x075e\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION13_CTRL2_METERIDX_EXT_OFFSET    10\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION13_CTRL2_METERIDX_EXT_MASK    0x400\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION13_CTRL2_METERIDX_OFFSET    5\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION13_CTRL2_METERIDX_MASK    0x3E0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION13_CTRL2_ENVLANPOL_OFFSET    4\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION13_CTRL2_ENVLANPOL_MASK    0x10\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION13_CTRL2_VBPRI_OFFSET    1\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION13_CTRL2_VBPRI_MASK    0xE\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION13_CTRL2_VBPEN_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION13_CTRL2_VBPEN_MASK    0x1\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION13_CTRL3    0x075f\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION13_CTRL3_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION13_CTRL3_MASK    0x1FFF\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION14_CTRL0    0x0760\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION14_CTRL0_MBR_EXT_OFFSET    8\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION14_CTRL0_MBR_EXT_MASK    0x700\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION14_CTRL0_MBR_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION14_CTRL0_MBR_MASK    0xFF\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION14_CTRL1    0x0761\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION14_CTRL1_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION14_CTRL1_MASK    0xF\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION14_CTRL2    0x0762\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION14_CTRL2_METERIDX_EXT_OFFSET    10\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION14_CTRL2_METERIDX_EXT_MASK    0x400\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION14_CTRL2_METERIDX_OFFSET    5\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION14_CTRL2_METERIDX_MASK    0x3E0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION14_CTRL2_ENVLANPOL_OFFSET    4\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION14_CTRL2_ENVLANPOL_MASK    0x10\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION14_CTRL2_VBPRI_OFFSET    1\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION14_CTRL2_VBPRI_MASK    0xE\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION14_CTRL2_VBPEN_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION14_CTRL2_VBPEN_MASK    0x1\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION14_CTRL3    0x0763\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION14_CTRL3_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION14_CTRL3_MASK    0x1FFF\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION15_CTRL0    0x0764\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION15_CTRL0_MBR_EXT_OFFSET    8\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION15_CTRL0_MBR_EXT_MASK    0x700\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION15_CTRL0_MBR_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION15_CTRL0_MBR_MASK    0xFF\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION15_CTRL1    0x0765\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION15_CTRL1_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION15_CTRL1_MASK    0xF\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION15_CTRL2    0x0766\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION15_CTRL2_METERIDX_EXT_OFFSET    10\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION15_CTRL2_METERIDX_EXT_MASK    0x400\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION15_CTRL2_METERIDX_OFFSET    5\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION15_CTRL2_METERIDX_MASK    0x3E0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION15_CTRL2_ENVLANPOL_OFFSET    4\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION15_CTRL2_ENVLANPOL_MASK    0x10\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION15_CTRL2_VBPRI_OFFSET    1\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION15_CTRL2_VBPRI_MASK    0xE\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION15_CTRL2_VBPEN_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION15_CTRL2_VBPEN_MASK    0x1\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION15_CTRL3    0x0767\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION15_CTRL3_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION15_CTRL3_MASK    0x1FFF\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION16_CTRL0    0x0768\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION16_CTRL0_MBR_EXT_OFFSET    8\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION16_CTRL0_MBR_EXT_MASK    0x700\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION16_CTRL0_MBR_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION16_CTRL0_MBR_MASK    0xFF\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION16_CTRL1    0x0769\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION16_CTRL1_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION16_CTRL1_MASK    0xF\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION16_CTRL2    0x076a\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION16_CTRL2_METERIDX_EXT_OFFSET    10\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION16_CTRL2_METERIDX_EXT_MASK    0x400\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION16_CTRL2_METERIDX_OFFSET    5\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION16_CTRL2_METERIDX_MASK    0x3E0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION16_CTRL2_ENVLANPOL_OFFSET    4\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION16_CTRL2_ENVLANPOL_MASK    0x10\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION16_CTRL2_VBPRI_OFFSET    1\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION16_CTRL2_VBPRI_MASK    0xE\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION16_CTRL2_VBPEN_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION16_CTRL2_VBPEN_MASK    0x1\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION16_CTRL3    0x076b\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION16_CTRL3_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION16_CTRL3_MASK    0x1FFF\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION17_CTRL0    0x076c\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION17_CTRL0_MBR_EXT_OFFSET    8\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION17_CTRL0_MBR_EXT_MASK    0x700\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION17_CTRL0_MBR_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION17_CTRL0_MBR_MASK    0xFF\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION17_CTRL1    0x076d\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION17_CTRL1_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION17_CTRL1_MASK    0xF\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION17_CTRL2    0x076e\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION17_CTRL2_METERIDX_EXT_OFFSET    10\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION17_CTRL2_METERIDX_EXT_MASK    0x400\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION17_CTRL2_METERIDX_OFFSET    5\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION17_CTRL2_METERIDX_MASK    0x3E0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION17_CTRL2_ENVLANPOL_OFFSET    4\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION17_CTRL2_ENVLANPOL_MASK    0x10\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION17_CTRL2_VBPRI_OFFSET    1\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION17_CTRL2_VBPRI_MASK    0xE\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION17_CTRL2_VBPEN_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION17_CTRL2_VBPEN_MASK    0x1\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION17_CTRL3    0x076f\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION17_CTRL3_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION17_CTRL3_MASK    0x1FFF\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION18_CTRL0    0x0770\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION18_CTRL0_MBR_EXT_OFFSET    8\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION18_CTRL0_MBR_EXT_MASK    0x700\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION18_CTRL0_MBR_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION18_CTRL0_MBR_MASK    0xFF\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION18_CTRL1    0x0771\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION18_CTRL1_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION18_CTRL1_MASK    0xF\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION18_CTRL2    0x0772\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION18_CTRL2_METERIDX_EXT_OFFSET    10\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION18_CTRL2_METERIDX_EXT_MASK    0x400\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION18_CTRL2_METERIDX_OFFSET    5\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION18_CTRL2_METERIDX_MASK    0x3E0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION18_CTRL2_ENVLANPOL_OFFSET    4\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION18_CTRL2_ENVLANPOL_MASK    0x10\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION18_CTRL2_VBPRI_OFFSET    1\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION18_CTRL2_VBPRI_MASK    0xE\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION18_CTRL2_VBPEN_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION18_CTRL2_VBPEN_MASK    0x1\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION18_CTRL3    0x0773\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION18_CTRL3_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION18_CTRL3_MASK    0x1FFF\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION19_CTRL0    0x0774\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION19_CTRL0_MBR_EXT_OFFSET    8\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION19_CTRL0_MBR_EXT_MASK    0x700\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION19_CTRL0_MBR_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION19_CTRL0_MBR_MASK    0xFF\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION19_CTRL1    0x0775\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION19_CTRL1_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION19_CTRL1_MASK    0xF\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION19_CTRL2    0x0776\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION19_CTRL2_METERIDX_EXT_OFFSET    10\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION19_CTRL2_METERIDX_EXT_MASK    0x400\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION19_CTRL2_METERIDX_OFFSET    5\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION19_CTRL2_METERIDX_MASK    0x3E0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION19_CTRL2_ENVLANPOL_OFFSET    4\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION19_CTRL2_ENVLANPOL_MASK    0x10\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION19_CTRL2_VBPRI_OFFSET    1\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION19_CTRL2_VBPRI_MASK    0xE\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION19_CTRL2_VBPEN_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION19_CTRL2_VBPEN_MASK    0x1\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION19_CTRL3    0x0777\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION19_CTRL3_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION19_CTRL3_MASK    0x1FFF\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION20_CTRL0    0x0778\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION20_CTRL0_MBR_EXT_OFFSET    8\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION20_CTRL0_MBR_EXT_MASK    0x700\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION20_CTRL0_MBR_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION20_CTRL0_MBR_MASK    0xFF\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION20_CTRL1    0x0779\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION20_CTRL1_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION20_CTRL1_MASK    0xF\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION20_CTRL2    0x077a\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION20_CTRL2_METERIDX_EXT_OFFSET    10\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION20_CTRL2_METERIDX_EXT_MASK    0x400\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION20_CTRL2_METERIDX_OFFSET    5\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION20_CTRL2_METERIDX_MASK    0x3E0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION20_CTRL2_ENVLANPOL_OFFSET    4\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION20_CTRL2_ENVLANPOL_MASK    0x10\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION20_CTRL2_VBPRI_OFFSET    1\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION20_CTRL2_VBPRI_MASK    0xE\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION20_CTRL2_VBPEN_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION20_CTRL2_VBPEN_MASK    0x1\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION20_CTRL3    0x077b\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION20_CTRL3_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION20_CTRL3_MASK    0x1FFF\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION21_CTRL0    0x077c\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION21_CTRL0_MBR_EXT_OFFSET    8\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION21_CTRL0_MBR_EXT_MASK    0x700\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION21_CTRL0_MBR_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION21_CTRL0_MBR_MASK    0xFF\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION21_CTRL1    0x077d\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION21_CTRL1_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION21_CTRL1_MASK    0xF\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION21_CTRL2    0x077e\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION21_CTRL2_METERIDX_EXT_OFFSET    10\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION21_CTRL2_METERIDX_EXT_MASK    0x400\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION21_CTRL2_METERIDX_OFFSET    5\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION21_CTRL2_METERIDX_MASK    0x3E0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION21_CTRL2_ENVLANPOL_OFFSET    4\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION21_CTRL2_ENVLANPOL_MASK    0x10\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION21_CTRL2_VBPRI_OFFSET    1\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION21_CTRL2_VBPRI_MASK    0xE\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION21_CTRL2_VBPEN_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION21_CTRL2_VBPEN_MASK    0x1\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION21_CTRL3    0x077f\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION21_CTRL3_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION21_CTRL3_MASK    0x1FFF\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION22_CTRL0    0x0780\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION22_CTRL0_MBR_EXT_OFFSET    8\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION22_CTRL0_MBR_EXT_MASK    0x700\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION22_CTRL0_MBR_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION22_CTRL0_MBR_MASK    0xFF\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION22_CTRL1    0x0781\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION22_CTRL1_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION22_CTRL1_MASK    0xF\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION22_CTRL2    0x0782\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION22_CTRL2_METERIDX_EXT_OFFSET    10\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION22_CTRL2_METERIDX_EXT_MASK    0x400\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION22_CTRL2_METERIDX_OFFSET    5\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION22_CTRL2_METERIDX_MASK    0x3E0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION22_CTRL2_ENVLANPOL_OFFSET    4\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION22_CTRL2_ENVLANPOL_MASK    0x10\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION22_CTRL2_VBPRI_OFFSET    1\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION22_CTRL2_VBPRI_MASK    0xE\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION22_CTRL2_VBPEN_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION22_CTRL2_VBPEN_MASK    0x1\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION22_CTRL3    0x0783\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION22_CTRL3_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION22_CTRL3_MASK    0x1FFF\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION23_CTRL0    0x0784\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION23_CTRL0_MBR_EXT_OFFSET    8\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION23_CTRL0_MBR_EXT_MASK    0x700\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION23_CTRL0_MBR_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION23_CTRL0_MBR_MASK    0xFF\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION23_CTRL1    0x0785\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION23_CTRL1_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION23_CTRL1_MASK    0xF\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION23_CTRL2    0x0786\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION23_CTRL2_METERIDX_EXT_OFFSET    10\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION23_CTRL2_METERIDX_EXT_MASK    0x400\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION23_CTRL2_METERIDX_OFFSET    5\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION23_CTRL2_METERIDX_MASK    0x3E0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION23_CTRL2_ENVLANPOL_OFFSET    4\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION23_CTRL2_ENVLANPOL_MASK    0x10\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION23_CTRL2_VBPRI_OFFSET    1\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION23_CTRL2_VBPRI_MASK    0xE\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION23_CTRL2_VBPEN_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION23_CTRL2_VBPEN_MASK    0x1\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION23_CTRL3    0x0787\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION23_CTRL3_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION23_CTRL3_MASK    0x1FFF\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION24_CTRL0    0x0788\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION24_CTRL0_MBR_EXT_OFFSET    8\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION24_CTRL0_MBR_EXT_MASK    0x700\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION24_CTRL0_MBR_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION24_CTRL0_MBR_MASK    0xFF\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION24_CTRL1    0x0789\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION24_CTRL1_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION24_CTRL1_MASK    0xF\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION24_CTRL2    0x078a\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION24_CTRL2_METERIDX_EXT_OFFSET    10\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION24_CTRL2_METERIDX_EXT_MASK    0x400\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION24_CTRL2_METERIDX_OFFSET    5\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION24_CTRL2_METERIDX_MASK    0x3E0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION24_CTRL2_ENVLANPOL_OFFSET    4\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION24_CTRL2_ENVLANPOL_MASK    0x10\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION24_CTRL2_VBPRI_OFFSET    1\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION24_CTRL2_VBPRI_MASK    0xE\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION24_CTRL2_VBPEN_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION24_CTRL2_VBPEN_MASK    0x1\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION24_CTRL3    0x078b\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION24_CTRL3_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION24_CTRL3_MASK    0x1FFF\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION25_CTRL0    0x078c\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION25_CTRL0_MBR_EXT_OFFSET    8\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION25_CTRL0_MBR_EXT_MASK    0x700\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION25_CTRL0_MBR_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION25_CTRL0_MBR_MASK    0xFF\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION25_CTRL1    0x078d\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION25_CTRL1_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION25_CTRL1_MASK    0xF\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION25_CTRL2    0x078e\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION25_CTRL2_METERIDX_EXT_OFFSET    10\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION25_CTRL2_METERIDX_EXT_MASK    0x400\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION25_CTRL2_METERIDX_OFFSET    5\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION25_CTRL2_METERIDX_MASK    0x3E0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION25_CTRL2_ENVLANPOL_OFFSET    4\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION25_CTRL2_ENVLANPOL_MASK    0x10\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION25_CTRL2_VBPRI_OFFSET    1\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION25_CTRL2_VBPRI_MASK    0xE\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION25_CTRL2_VBPEN_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION25_CTRL2_VBPEN_MASK    0x1\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION25_CTRL3    0x078f\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION25_CTRL3_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION25_CTRL3_MASK    0x1FFF\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION26_CTRL0    0x0790\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION26_CTRL0_MBR_EXT_OFFSET    8\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION26_CTRL0_MBR_EXT_MASK    0x700\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION26_CTRL0_MBR_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION26_CTRL0_MBR_MASK    0xFF\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION26_CTRL1    0x0791\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION26_CTRL1_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION26_CTRL1_MASK    0xF\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION26_CTRL2    0x0792\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION26_CTRL2_METERIDX_EXT_OFFSET    10\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION26_CTRL2_METERIDX_EXT_MASK    0x400\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION26_CTRL2_METERIDX_OFFSET    5\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION26_CTRL2_METERIDX_MASK    0x3E0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION26_CTRL2_ENVLANPOL_OFFSET    4\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION26_CTRL2_ENVLANPOL_MASK    0x10\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION26_CTRL2_VBPRI_OFFSET    1\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION26_CTRL2_VBPRI_MASK    0xE\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION26_CTRL2_VBPEN_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION26_CTRL2_VBPEN_MASK    0x1\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION26_CTRL3    0x0793\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION26_CTRL3_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION26_CTRL3_MASK    0x1FFF\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION27_CTRL0    0x0794\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION27_CTRL0_MBR_EXT_OFFSET    8\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION27_CTRL0_MBR_EXT_MASK    0x700\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION27_CTRL0_MBR_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION27_CTRL0_MBR_MASK    0xFF\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION27_CTRL1    0x0795\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION27_CTRL1_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION27_CTRL1_MASK    0xF\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION27_CTRL2    0x0796\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION27_CTRL2_METERIDX_EXT_OFFSET    10\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION27_CTRL2_METERIDX_EXT_MASK    0x400\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION27_CTRL2_METERIDX_OFFSET    5\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION27_CTRL2_METERIDX_MASK    0x3E0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION27_CTRL2_ENVLANPOL_OFFSET    4\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION27_CTRL2_ENVLANPOL_MASK    0x10\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION27_CTRL2_VBPRI_OFFSET    1\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION27_CTRL2_VBPRI_MASK    0xE\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION27_CTRL2_VBPEN_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION27_CTRL2_VBPEN_MASK    0x1\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION27_CTRL3    0x0797\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION27_CTRL3_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION27_CTRL3_MASK    0x1FFF\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION28_CTRL0    0x0798\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION28_CTRL0_MBR_EXT_OFFSET    8\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION28_CTRL0_MBR_EXT_MASK    0x700\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION28_CTRL0_MBR_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION28_CTRL0_MBR_MASK    0xFF\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION28_CTRL1    0x0799\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION28_CTRL1_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION28_CTRL1_MASK    0xF\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION28_CTRL2    0x079a\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION28_CTRL2_METERIDX_EXT_OFFSET    10\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION28_CTRL2_METERIDX_EXT_MASK    0x400\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION28_CTRL2_METERIDX_OFFSET    5\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION28_CTRL2_METERIDX_MASK    0x3E0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION28_CTRL2_ENVLANPOL_OFFSET    4\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION28_CTRL2_ENVLANPOL_MASK    0x10\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION28_CTRL2_VBPRI_OFFSET    1\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION28_CTRL2_VBPRI_MASK    0xE\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION28_CTRL2_VBPEN_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION28_CTRL2_VBPEN_MASK    0x1\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION28_CTRL3    0x079b\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION28_CTRL3_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION28_CTRL3_MASK    0x1FFF\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION29_CTRL0    0x079c\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION29_CTRL0_MBR_EXT_OFFSET    8\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION29_CTRL0_MBR_EXT_MASK    0x700\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION29_CTRL0_MBR_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION29_CTRL0_MBR_MASK    0xFF\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION29_CTRL1    0x079d\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION29_CTRL1_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION29_CTRL1_MASK    0xF\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION29_CTRL2    0x079e\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION29_CTRL2_METERIDX_EXT_OFFSET    10\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION29_CTRL2_METERIDX_EXT_MASK    0x400\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION29_CTRL2_METERIDX_OFFSET    5\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION29_CTRL2_METERIDX_MASK    0x3E0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION29_CTRL2_ENVLANPOL_OFFSET    4\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION29_CTRL2_ENVLANPOL_MASK    0x10\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION29_CTRL2_VBPRI_OFFSET    1\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION29_CTRL2_VBPRI_MASK    0xE\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION29_CTRL2_VBPEN_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION29_CTRL2_VBPEN_MASK    0x1\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION29_CTRL3    0x079f\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION29_CTRL3_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION29_CTRL3_MASK    0x1FFF\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION30_CTRL0    0x07a0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION30_CTRL0_MBR_EXT_OFFSET    8\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION30_CTRL0_MBR_EXT_MASK    0x700\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION30_CTRL0_MBR_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION30_CTRL0_MBR_MASK    0xFF\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION30_CTRL1    0x07a1\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION30_CTRL1_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION30_CTRL1_MASK    0xF\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION30_CTRL2    0x07a2\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION30_CTRL2_METERIDX_EXT_OFFSET    10\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION30_CTRL2_METERIDX_EXT_MASK    0x400\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION30_CTRL2_METERIDX_OFFSET    5\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION30_CTRL2_METERIDX_MASK    0x3E0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION30_CTRL2_ENVLANPOL_OFFSET    4\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION30_CTRL2_ENVLANPOL_MASK    0x10\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION30_CTRL2_VBPRI_OFFSET    1\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION30_CTRL2_VBPRI_MASK    0xE\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION30_CTRL2_VBPEN_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION30_CTRL2_VBPEN_MASK    0x1\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION30_CTRL3    0x07a3\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION30_CTRL3_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION30_CTRL3_MASK    0x1FFF\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION31_CTRL0    0x07a4\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION31_CTRL0_MBR_EXT_OFFSET    8\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION31_CTRL0_MBR_EXT_MASK    0x700\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION31_CTRL0_MBR_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION31_CTRL0_MBR_MASK    0xFF\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION31_CTRL1    0x07a5\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION31_CTRL1_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION31_CTRL1_MASK    0xF\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION31_CTRL2    0x07a6\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION31_CTRL2_METERIDX_EXT_OFFSET    10\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION31_CTRL2_METERIDX_EXT_MASK    0x400\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION31_CTRL2_METERIDX_OFFSET    5\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION31_CTRL2_METERIDX_MASK    0x3E0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION31_CTRL2_ENVLANPOL_OFFSET    4\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION31_CTRL2_ENVLANPOL_MASK    0x10\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION31_CTRL2_VBPRI_OFFSET    1\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION31_CTRL2_VBPRI_MASK    0xE\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION31_CTRL2_VBPEN_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION31_CTRL2_VBPEN_MASK    0x1\n\n#define    RTL8367C_REG_VLAN_MEMBER_CONFIGURATION31_CTRL3    0x07a7\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION31_CTRL3_OFFSET    0\n#define    RTL8367C_VLAN_MEMBER_CONFIGURATION31_CTRL3_MASK    0x1FFF\n\n#define    RTL8367C_REG_VLAN_CTRL    0x07a8\n#define    RTL8367C_VLAN_CTRL_OFFSET    0\n#define    RTL8367C_VLAN_CTRL_MASK    0x1\n\n#define    RTL8367C_REG_VLAN_INGRESS    0x07a9\n#define    RTL8367C_VLAN_INGRESS_OFFSET    0\n#define    RTL8367C_VLAN_INGRESS_MASK    0x7FF\n\n#define    RTL8367C_REG_VLAN_ACCEPT_FRAME_TYPE_CTRL0    0x07aa\n#define    RTL8367C_PORT7_FRAME_TYPE_OFFSET    14\n#define    RTL8367C_PORT7_FRAME_TYPE_MASK    0xC000\n#define    RTL8367C_PORT6_FRAME_TYPE_OFFSET    12\n#define    RTL8367C_PORT6_FRAME_TYPE_MASK    0x3000\n#define    RTL8367C_PORT5_FRAME_TYPE_OFFSET    10\n#define    RTL8367C_PORT5_FRAME_TYPE_MASK    0xC00\n#define    RTL8367C_PORT4_FRAME_TYPE_OFFSET    8\n#define    RTL8367C_PORT4_FRAME_TYPE_MASK    0x300\n#define    RTL8367C_PORT3_FRAME_TYPE_OFFSET    6\n#define    RTL8367C_PORT3_FRAME_TYPE_MASK    0xC0\n#define    RTL8367C_PORT2_FRAME_TYPE_OFFSET    4\n#define    RTL8367C_PORT2_FRAME_TYPE_MASK    0x30\n#define    RTL8367C_PORT1_FRAME_TYPE_OFFSET    2\n#define    RTL8367C_PORT1_FRAME_TYPE_MASK    0xC\n#define    RTL8367C_PORT0_FRAME_TYPE_OFFSET    0\n#define    RTL8367C_PORT0_FRAME_TYPE_MASK    0x3\n\n#define    RTL8367C_REG_VLAN_ACCEPT_FRAME_TYPE_CTRL1    0x07ab\n#define    RTL8367C_PORT10_FRAME_TYPE_OFFSET    4\n#define    RTL8367C_PORT10_FRAME_TYPE_MASK    0x30\n#define    RTL8367C_PORT9_FRAME_TYPE_OFFSET    2\n#define    RTL8367C_PORT9_FRAME_TYPE_MASK    0xC\n#define    RTL8367C_PORT8_FRAME_TYPE_OFFSET    0\n#define    RTL8367C_PORT8_FRAME_TYPE_MASK    0x3\n\n#define    RTL8367C_REG_PORT_PBFIDEN    0x07ac\n#define    RTL8367C_PORT_PBFIDEN_OFFSET    0\n#define    RTL8367C_PORT_PBFIDEN_MASK    0x7FF\n\n#define    RTL8367C_REG_PORT0_PBFID    0x07ad\n#define    RTL8367C_PORT0_PBFID_OFFSET    0\n#define    RTL8367C_PORT0_PBFID_MASK    0xF\n\n#define    RTL8367C_REG_PORT1_PBFID    0x07ae\n#define    RTL8367C_PORT1_PBFID_OFFSET    0\n#define    RTL8367C_PORT1_PBFID_MASK    0xF\n\n#define    RTL8367C_REG_PORT2_PBFID    0x07af\n#define    RTL8367C_PORT2_PBFID_OFFSET    0\n#define    RTL8367C_PORT2_PBFID_MASK    0xF\n\n#define    RTL8367C_REG_PORT3_PBFID    0x07b0\n#define    RTL8367C_PORT3_PBFID_OFFSET    0\n#define    RTL8367C_PORT3_PBFID_MASK    0xF\n\n#define    RTL8367C_REG_PORT4_PBFID    0x07b1\n#define    RTL8367C_PORT4_PBFID_OFFSET    0\n#define    RTL8367C_PORT4_PBFID_MASK    0xF\n\n#define    RTL8367C_REG_PORT5_PBFID    0x07b2\n#define    RTL8367C_PORT5_PBFID_OFFSET    0\n#define    RTL8367C_PORT5_PBFID_MASK    0xF\n\n#define    RTL8367C_REG_PORT6_PBFID    0x07b3\n#define    RTL8367C_PORT6_PBFID_OFFSET    0\n#define    RTL8367C_PORT6_PBFID_MASK    0xF\n\n#define    RTL8367C_REG_PORT7_PBFID    0x07b4\n#define    RTL8367C_PORT7_PBFID_OFFSET    0\n#define    RTL8367C_PORT7_PBFID_MASK    0xF\n\n#define    RTL8367C_REG_VLAN_EXT_CTRL    0x07b5\n#define    RTL8367C_VLAN_1P_REMARK_BYPASS_REALKEEP_OFFSET    2\n#define    RTL8367C_VLAN_1P_REMARK_BYPASS_REALKEEP_MASK    0x4\n#define    RTL8367C_VLAN_VID4095_TYPE_OFFSET    1\n#define    RTL8367C_VLAN_VID4095_TYPE_MASK    0x2\n#define    RTL8367C_VLAN_VID0_TYPE_OFFSET    0\n#define    RTL8367C_VLAN_VID0_TYPE_MASK    0x1\n\n#define    RTL8367C_REG_VLAN_EXT_CTRL2    0x07b6\n#define    RTL8367C_VLAN_EXT_CTRL2_OFFSET    0\n#define    RTL8367C_VLAN_EXT_CTRL2_MASK    0x1\n\n#define    RTL8367C_REG_PORT8_PBFID    0x07b7\n#define    RTL8367C_PORT8_PBFID_OFFSET    0\n#define    RTL8367C_PORT8_PBFID_MASK    0xF\n\n#define    RTL8367C_REG_PORT9_PBFID    0x07b8\n#define    RTL8367C_PORT9_PBFID_OFFSET    0\n#define    RTL8367C_PORT9_PBFID_MASK    0xF\n\n#define    RTL8367C_REG_PORT10_PBFID    0x07b9\n#define    RTL8367C_PORT10_PBFID_OFFSET    0\n#define    RTL8367C_PORT10_PBFID_MASK    0xF\n\n#define    RTL8367C_REG_CVLAN_DUMMY00    0x07E0\n\n#define    RTL8367C_REG_CVLAN_DUMMY01    0x07E1\n\n#define    RTL8367C_REG_CVLAN_DUMMY02    0x07E2\n\n#define    RTL8367C_REG_CVLAN_DUMMY03    0x07E3\n\n#define    RTL8367C_REG_CVLAN_DUMMY04    0x07E4\n\n#define    RTL8367C_REG_CVLAN_DUMMY05    0x07E5\n\n#define    RTL8367C_REG_CVLAN_DUMMY06    0x07E6\n\n#define    RTL8367C_REG_CVLAN_DUMMY07    0x07E7\n\n#define    RTL8367C_REG_CVLAN_DUMMY08    0x07E8\n\n#define    RTL8367C_REG_CVLAN_DUMMY09    0x07E9\n\n#define    RTL8367C_REG_CVLAN_DUMMY10    0x07EA\n\n#define    RTL8367C_REG_CVLAN_DUMMY11    0x07EB\n\n#define    RTL8367C_REG_CVLAN_DUMMY12    0x07EC\n\n#define    RTL8367C_REG_CVLAN_DUMMY13    0x07ED\n\n#define    RTL8367C_REG_CVLAN_DUMMY14    0x07EE\n\n#define    RTL8367C_REG_CVLAN_DUMMY15    0x07EF\n\n/* (16'h0800)dpm_reg */\n\n#define    RTL8367C_REG_RMA_CTRL00    0x0800\n#define    RTL8367C_RMA_CTRL00_OPERATION_OFFSET    7\n#define    RTL8367C_RMA_CTRL00_OPERATION_MASK    0x180\n#define    RTL8367C_RMA_CTRL00_DISCARD_STORM_FILTER_OFFSET    6\n#define    RTL8367C_RMA_CTRL00_DISCARD_STORM_FILTER_MASK    0x40\n#define    RTL8367C_TRAP_PRIORITY_OFFSET    3\n#define    RTL8367C_TRAP_PRIORITY_MASK    0x38\n#define    RTL8367C_RMA_CTRL00_KEEP_FORMAT_OFFSET    2\n#define    RTL8367C_RMA_CTRL00_KEEP_FORMAT_MASK    0x4\n#define    RTL8367C_RMA_CTRL00_VLAN_LEAKY_OFFSET    1\n#define    RTL8367C_RMA_CTRL00_VLAN_LEAKY_MASK    0x2\n#define    RTL8367C_RMA_CTRL00_PORTISO_LEAKY_OFFSET    0\n#define    RTL8367C_RMA_CTRL00_PORTISO_LEAKY_MASK    0x1\n\n#define    RTL8367C_REG_RMA_CTRL01    0x0801\n#define    RTL8367C_RMA_CTRL01_OPERATION_OFFSET    7\n#define    RTL8367C_RMA_CTRL01_OPERATION_MASK    0x180\n#define    RTL8367C_RMA_CTRL01_DISCARD_STORM_FILTER_OFFSET    6\n#define    RTL8367C_RMA_CTRL01_DISCARD_STORM_FILTER_MASK    0x40\n#define    RTL8367C_RMA_CTRL01_KEEP_FORMAT_OFFSET    2\n#define    RTL8367C_RMA_CTRL01_KEEP_FORMAT_MASK    0x4\n#define    RTL8367C_RMA_CTRL01_VLAN_LEAKY_OFFSET    1\n#define    RTL8367C_RMA_CTRL01_VLAN_LEAKY_MASK    0x2\n#define    RTL8367C_RMA_CTRL01_PORTISO_LEAKY_OFFSET    0\n#define    RTL8367C_RMA_CTRL01_PORTISO_LEAKY_MASK    0x1\n\n#define    RTL8367C_REG_RMA_CTRL02    0x0802\n#define    RTL8367C_RMA_CTRL02_OPERATION_OFFSET    7\n#define    RTL8367C_RMA_CTRL02_OPERATION_MASK    0x180\n#define    RTL8367C_RMA_CTRL02_DISCARD_STORM_FILTER_OFFSET    6\n#define    RTL8367C_RMA_CTRL02_DISCARD_STORM_FILTER_MASK    0x40\n#define    RTL8367C_RMA_CTRL02_KEEP_FORMAT_OFFSET    2\n#define    RTL8367C_RMA_CTRL02_KEEP_FORMAT_MASK    0x4\n#define    RTL8367C_RMA_CTRL02_VLAN_LEAKY_OFFSET    1\n#define    RTL8367C_RMA_CTRL02_VLAN_LEAKY_MASK    0x2\n#define    RTL8367C_RMA_CTRL02_PORTISO_LEAKY_OFFSET    0\n#define    RTL8367C_RMA_CTRL02_PORTISO_LEAKY_MASK    0x1\n\n#define    RTL8367C_REG_RMA_CTRL03    0x0803\n#define    RTL8367C_RMA_CTRL03_OPERATION_OFFSET    7\n#define    RTL8367C_RMA_CTRL03_OPERATION_MASK    0x180\n#define    RTL8367C_RMA_CTRL03_DISCARD_STORM_FILTER_OFFSET    6\n#define    RTL8367C_RMA_CTRL03_DISCARD_STORM_FILTER_MASK    0x40\n#define    RTL8367C_RMA_CTRL03_KEEP_FORMAT_OFFSET    2\n#define    RTL8367C_RMA_CTRL03_KEEP_FORMAT_MASK    0x4\n#define    RTL8367C_RMA_CTRL03_VLAN_LEAKY_OFFSET    1\n#define    RTL8367C_RMA_CTRL03_VLAN_LEAKY_MASK    0x2\n#define    RTL8367C_RMA_CTRL03_PORTISO_LEAKY_OFFSET    0\n#define    RTL8367C_RMA_CTRL03_PORTISO_LEAKY_MASK    0x1\n\n#define    RTL8367C_REG_RMA_CTRL04    0x0804\n#define    RTL8367C_RMA_CTRL04_OPERATION_OFFSET    7\n#define    RTL8367C_RMA_CTRL04_OPERATION_MASK    0x180\n#define    RTL8367C_RMA_CTRL04_DISCARD_STORM_FILTER_OFFSET    6\n#define    RTL8367C_RMA_CTRL04_DISCARD_STORM_FILTER_MASK    0x40\n#define    RTL8367C_RMA_CTRL04_KEEP_FORMAT_OFFSET    2\n#define    RTL8367C_RMA_CTRL04_KEEP_FORMAT_MASK    0x4\n#define    RTL8367C_RMA_CTRL04_VLAN_LEAKY_OFFSET    1\n#define    RTL8367C_RMA_CTRL04_VLAN_LEAKY_MASK    0x2\n#define    RTL8367C_RMA_CTRL04_PORTISO_LEAKY_OFFSET    0\n#define    RTL8367C_RMA_CTRL04_PORTISO_LEAKY_MASK    0x1\n\n#define    RTL8367C_REG_RMA_CTRL08    0x0808\n#define    RTL8367C_RMA_CTRL08_OPERATION_OFFSET    7\n#define    RTL8367C_RMA_CTRL08_OPERATION_MASK    0x180\n#define    RTL8367C_RMA_CTRL08_DISCARD_STORM_FILTER_OFFSET    6\n#define    RTL8367C_RMA_CTRL08_DISCARD_STORM_FILTER_MASK    0x40\n#define    RTL8367C_RMA_CTRL08_KEEP_FORMAT_OFFSET    2\n#define    RTL8367C_RMA_CTRL08_KEEP_FORMAT_MASK    0x4\n#define    RTL8367C_RMA_CTRL08_VLAN_LEAKY_OFFSET    1\n#define    RTL8367C_RMA_CTRL08_VLAN_LEAKY_MASK    0x2\n#define    RTL8367C_RMA_CTRL08_PORTISO_LEAKY_OFFSET    0\n#define    RTL8367C_RMA_CTRL08_PORTISO_LEAKY_MASK    0x1\n\n#define    RTL8367C_REG_RMA_CTRL0D    0x080d\n#define    RTL8367C_RMA_CTRL0D_OPERATION_OFFSET    7\n#define    RTL8367C_RMA_CTRL0D_OPERATION_MASK    0x180\n#define    RTL8367C_RMA_CTRL0D_DISCARD_STORM_FILTER_OFFSET    6\n#define    RTL8367C_RMA_CTRL0D_DISCARD_STORM_FILTER_MASK    0x40\n#define    RTL8367C_RMA_CTRL0D_KEEP_FORMAT_OFFSET    2\n#define    RTL8367C_RMA_CTRL0D_KEEP_FORMAT_MASK    0x4\n#define    RTL8367C_RMA_CTRL0D_VLAN_LEAKY_OFFSET    1\n#define    RTL8367C_RMA_CTRL0D_VLAN_LEAKY_MASK    0x2\n#define    RTL8367C_RMA_CTRL0D_PORTISO_LEAKY_OFFSET    0\n#define    RTL8367C_RMA_CTRL0D_PORTISO_LEAKY_MASK    0x1\n\n#define    RTL8367C_REG_RMA_CTRL0E    0x080e\n#define    RTL8367C_RMA_CTRL0E_OPERATION_OFFSET    7\n#define    RTL8367C_RMA_CTRL0E_OPERATION_MASK    0x180\n#define    RTL8367C_RMA_CTRL0E_DISCARD_STORM_FILTER_OFFSET    6\n#define    RTL8367C_RMA_CTRL0E_DISCARD_STORM_FILTER_MASK    0x40\n#define    RTL8367C_RMA_CTRL0E_KEEP_FORMAT_OFFSET    2\n#define    RTL8367C_RMA_CTRL0E_KEEP_FORMAT_MASK    0x4\n#define    RTL8367C_RMA_CTRL0E_VLAN_LEAKY_OFFSET    1\n#define    RTL8367C_RMA_CTRL0E_VLAN_LEAKY_MASK    0x2\n#define    RTL8367C_RMA_CTRL0E_PORTISO_LEAKY_OFFSET    0\n#define    RTL8367C_RMA_CTRL0E_PORTISO_LEAKY_MASK    0x1\n\n#define    RTL8367C_REG_RMA_CTRL10    0x0810\n#define    RTL8367C_RMA_CTRL10_OPERATION_OFFSET    7\n#define    RTL8367C_RMA_CTRL10_OPERATION_MASK    0x180\n#define    RTL8367C_RMA_CTRL10_DISCARD_STORM_FILTER_OFFSET    6\n#define    RTL8367C_RMA_CTRL10_DISCARD_STORM_FILTER_MASK    0x40\n#define    RTL8367C_RMA_CTRL10_KEEP_FORMAT_OFFSET    2\n#define    RTL8367C_RMA_CTRL10_KEEP_FORMAT_MASK    0x4\n#define    RTL8367C_RMA_CTRL10_VLAN_LEAKY_OFFSET    1\n#define    RTL8367C_RMA_CTRL10_VLAN_LEAKY_MASK    0x2\n#define    RTL8367C_RMA_CTRL10_PORTISO_LEAKY_OFFSET    0\n#define    RTL8367C_RMA_CTRL10_PORTISO_LEAKY_MASK    0x1\n\n#define    RTL8367C_REG_RMA_CTRL11    0x0811\n#define    RTL8367C_RMA_CTRL11_OPERATION_OFFSET    7\n#define    RTL8367C_RMA_CTRL11_OPERATION_MASK    0x180\n#define    RTL8367C_RMA_CTRL11_DISCARD_STORM_FILTER_OFFSET    6\n#define    RTL8367C_RMA_CTRL11_DISCARD_STORM_FILTER_MASK    0x40\n#define    RTL8367C_RMA_CTRL11_KEEP_FORMAT_OFFSET    2\n#define    RTL8367C_RMA_CTRL11_KEEP_FORMAT_MASK    0x4\n#define    RTL8367C_RMA_CTRL11_VLAN_LEAKY_OFFSET    1\n#define    RTL8367C_RMA_CTRL11_VLAN_LEAKY_MASK    0x2\n#define    RTL8367C_RMA_CTRL11_PORTISO_LEAKY_OFFSET    0\n#define    RTL8367C_RMA_CTRL11_PORTISO_LEAKY_MASK    0x1\n\n#define    RTL8367C_REG_RMA_CTRL12    0x0812\n#define    RTL8367C_RMA_CTRL12_OPERATION_OFFSET    7\n#define    RTL8367C_RMA_CTRL12_OPERATION_MASK    0x180\n#define    RTL8367C_RMA_CTRL12_DISCARD_STORM_FILTER_OFFSET    6\n#define    RTL8367C_RMA_CTRL12_DISCARD_STORM_FILTER_MASK    0x40\n#define    RTL8367C_RMA_CTRL12_KEEP_FORMAT_OFFSET    2\n#define    RTL8367C_RMA_CTRL12_KEEP_FORMAT_MASK    0x4\n#define    RTL8367C_RMA_CTRL12_VLAN_LEAKY_OFFSET    1\n#define    RTL8367C_RMA_CTRL12_VLAN_LEAKY_MASK    0x2\n#define    RTL8367C_RMA_CTRL12_PORTISO_LEAKY_OFFSET    0\n#define    RTL8367C_RMA_CTRL12_PORTISO_LEAKY_MASK    0x1\n\n#define    RTL8367C_REG_RMA_CTRL13    0x0813\n#define    RTL8367C_RMA_CTRL13_OPERATION_OFFSET    7\n#define    RTL8367C_RMA_CTRL13_OPERATION_MASK    0x180\n#define    RTL8367C_RMA_CTRL13_DISCARD_STORM_FILTER_OFFSET    6\n#define    RTL8367C_RMA_CTRL13_DISCARD_STORM_FILTER_MASK    0x40\n#define    RTL8367C_RMA_CTRL13_KEEP_FORMAT_OFFSET    2\n#define    RTL8367C_RMA_CTRL13_KEEP_FORMAT_MASK    0x4\n#define    RTL8367C_RMA_CTRL13_VLAN_LEAKY_OFFSET    1\n#define    RTL8367C_RMA_CTRL13_VLAN_LEAKY_MASK    0x2\n#define    RTL8367C_RMA_CTRL13_PORTISO_LEAKY_OFFSET    0\n#define    RTL8367C_RMA_CTRL13_PORTISO_LEAKY_MASK    0x1\n\n#define    RTL8367C_REG_RMA_CTRL18    0x0818\n#define    RTL8367C_RMA_CTRL18_OPERATION_OFFSET    7\n#define    RTL8367C_RMA_CTRL18_OPERATION_MASK    0x180\n#define    RTL8367C_RMA_CTRL18_DISCARD_STORM_FILTER_OFFSET    6\n#define    RTL8367C_RMA_CTRL18_DISCARD_STORM_FILTER_MASK    0x40\n#define    RTL8367C_RMA_CTRL18_KEEP_FORMAT_OFFSET    2\n#define    RTL8367C_RMA_CTRL18_KEEP_FORMAT_MASK    0x4\n#define    RTL8367C_RMA_CTRL18_VLAN_LEAKY_OFFSET    1\n#define    RTL8367C_RMA_CTRL18_VLAN_LEAKY_MASK    0x2\n#define    RTL8367C_RMA_CTRL18_PORTISO_LEAKY_OFFSET    0\n#define    RTL8367C_RMA_CTRL18_PORTISO_LEAKY_MASK    0x1\n\n#define    RTL8367C_REG_RMA_CTRL1A    0x081a\n#define    RTL8367C_RMA_CTRL1A_OPERATION_OFFSET    7\n#define    RTL8367C_RMA_CTRL1A_OPERATION_MASK    0x180\n#define    RTL8367C_RMA_CTRL1A_DISCARD_STORM_FILTER_OFFSET    6\n#define    RTL8367C_RMA_CTRL1A_DISCARD_STORM_FILTER_MASK    0x40\n#define    RTL8367C_RMA_CTRL1A_KEEP_FORMAT_OFFSET    2\n#define    RTL8367C_RMA_CTRL1A_KEEP_FORMAT_MASK    0x4\n#define    RTL8367C_RMA_CTRL1A_VLAN_LEAKY_OFFSET    1\n#define    RTL8367C_RMA_CTRL1A_VLAN_LEAKY_MASK    0x2\n#define    RTL8367C_RMA_CTRL1A_PORTISO_LEAKY_OFFSET    0\n#define    RTL8367C_RMA_CTRL1A_PORTISO_LEAKY_MASK    0x1\n\n#define    RTL8367C_REG_RMA_CTRL20    0x0820\n#define    RTL8367C_RMA_CTRL20_OPERATION_OFFSET    7\n#define    RTL8367C_RMA_CTRL20_OPERATION_MASK    0x180\n#define    RTL8367C_RMA_CTRL20_DISCARD_STORM_FILTER_OFFSET    6\n#define    RTL8367C_RMA_CTRL20_DISCARD_STORM_FILTER_MASK    0x40\n#define    RTL8367C_RMA_CTRL20_KEEP_FORMAT_OFFSET    2\n#define    RTL8367C_RMA_CTRL20_KEEP_FORMAT_MASK    0x4\n#define    RTL8367C_RMA_CTRL20_VLAN_LEAKY_OFFSET    1\n#define    RTL8367C_RMA_CTRL20_VLAN_LEAKY_MASK    0x2\n#define    RTL8367C_RMA_CTRL20_PORTISO_LEAKY_OFFSET    0\n#define    RTL8367C_RMA_CTRL20_PORTISO_LEAKY_MASK    0x1\n\n#define    RTL8367C_REG_RMA_CTRL21    0x0821\n#define    RTL8367C_RMA_CTRL21_OPERATION_OFFSET    7\n#define    RTL8367C_RMA_CTRL21_OPERATION_MASK    0x180\n#define    RTL8367C_RMA_CTRL21_DISCARD_STORM_FILTER_OFFSET    6\n#define    RTL8367C_RMA_CTRL21_DISCARD_STORM_FILTER_MASK    0x40\n#define    RTL8367C_RMA_CTRL21_KEEP_FORMAT_OFFSET    2\n#define    RTL8367C_RMA_CTRL21_KEEP_FORMAT_MASK    0x4\n#define    RTL8367C_RMA_CTRL21_VLAN_LEAKY_OFFSET    1\n#define    RTL8367C_RMA_CTRL21_VLAN_LEAKY_MASK    0x2\n#define    RTL8367C_RMA_CTRL21_PORTISO_LEAKY_OFFSET    0\n#define    RTL8367C_RMA_CTRL21_PORTISO_LEAKY_MASK    0x1\n\n#define    RTL8367C_REG_RMA_CTRL22    0x0822\n#define    RTL8367C_RMA_CTRL22_OPERATION_OFFSET    7\n#define    RTL8367C_RMA_CTRL22_OPERATION_MASK    0x180\n#define    RTL8367C_RMA_CTRL22_DISCARD_STORM_FILTER_OFFSET    6\n#define    RTL8367C_RMA_CTRL22_DISCARD_STORM_FILTER_MASK    0x40\n#define    RTL8367C_RMA_CTRL22_KEEP_FORMAT_OFFSET    2\n#define    RTL8367C_RMA_CTRL22_KEEP_FORMAT_MASK    0x4\n#define    RTL8367C_RMA_CTRL22_VLAN_LEAKY_OFFSET    1\n#define    RTL8367C_RMA_CTRL22_VLAN_LEAKY_MASK    0x2\n#define    RTL8367C_RMA_CTRL22_PORTISO_LEAKY_OFFSET    0\n#define    RTL8367C_RMA_CTRL22_PORTISO_LEAKY_MASK    0x1\n\n#define    RTL8367C_REG_RMA_CTRL_CDP    0x0830\n#define    RTL8367C_RMA_CTRL_CDP_OPERATION_OFFSET    7\n#define    RTL8367C_RMA_CTRL_CDP_OPERATION_MASK    0x180\n#define    RTL8367C_RMA_CTRL_CDP_DISCARD_STORM_FILTER_OFFSET    6\n#define    RTL8367C_RMA_CTRL_CDP_DISCARD_STORM_FILTER_MASK    0x40\n#define    RTL8367C_RMA_CTRL_CDP_KEEP_FORMAT_OFFSET    2\n#define    RTL8367C_RMA_CTRL_CDP_KEEP_FORMAT_MASK    0x4\n#define    RTL8367C_RMA_CTRL_CDP_VLAN_LEAKY_OFFSET    1\n#define    RTL8367C_RMA_CTRL_CDP_VLAN_LEAKY_MASK    0x2\n#define    RTL8367C_RMA_CTRL_CDP_PORTISO_LEAKY_OFFSET    0\n#define    RTL8367C_RMA_CTRL_CDP_PORTISO_LEAKY_MASK    0x1\n\n#define    RTL8367C_REG_RMA_CTRL_CSSTP    0x0831\n#define    RTL8367C_RMA_CTRL_CSSTP_OPERATION_OFFSET    7\n#define    RTL8367C_RMA_CTRL_CSSTP_OPERATION_MASK    0x180\n#define    RTL8367C_RMA_CTRL_CSSTP_DISCARD_STORM_FILTER_OFFSET    6\n#define    RTL8367C_RMA_CTRL_CSSTP_DISCARD_STORM_FILTER_MASK    0x40\n#define    RTL8367C_RMA_CTRL_CSSTP_KEEP_FORMAT_OFFSET    2\n#define    RTL8367C_RMA_CTRL_CSSTP_KEEP_FORMAT_MASK    0x4\n#define    RTL8367C_RMA_CTRL_CSSTP_VLAN_LEAKY_OFFSET    1\n#define    RTL8367C_RMA_CTRL_CSSTP_VLAN_LEAKY_MASK    0x2\n#define    RTL8367C_RMA_CTRL_CSSTP_PORTISO_LEAKY_OFFSET    0\n#define    RTL8367C_RMA_CTRL_CSSTP_PORTISO_LEAKY_MASK    0x1\n\n#define    RTL8367C_REG_RMA_CTRL_LLDP    0x0832\n#define    RTL8367C_RMA_CTRL_LLDP_OPERATION_OFFSET    7\n#define    RTL8367C_RMA_CTRL_LLDP_OPERATION_MASK    0x180\n#define    RTL8367C_RMA_CTRL_LLDP_DISCARD_STORM_FILTER_OFFSET    6\n#define    RTL8367C_RMA_CTRL_LLDP_DISCARD_STORM_FILTER_MASK    0x40\n#define    RTL8367C_RMA_CTRL_LLDP_KEEP_FORMAT_OFFSET    2\n#define    RTL8367C_RMA_CTRL_LLDP_KEEP_FORMAT_MASK    0x4\n#define    RTL8367C_RMA_CTRL_LLDP_VLAN_LEAKY_OFFSET    1\n#define    RTL8367C_RMA_CTRL_LLDP_VLAN_LEAKY_MASK    0x2\n#define    RTL8367C_RMA_CTRL_LLDP_PORTISO_LEAKY_OFFSET    0\n#define    RTL8367C_RMA_CTRL_LLDP_PORTISO_LEAKY_MASK    0x1\n\n#define    RTL8367C_REG_RMA_LLDP_EN    0x0833\n#define    RTL8367C_RMA_LLDP_EN_OFFSET    0\n#define    RTL8367C_RMA_LLDP_EN_MASK    0x1\n\n#define    RTL8367C_REG_VLAN_PORTBASED_PRIORITY_CTRL0    0x0851\n#define    RTL8367C_VLAN_PORTBASED_PRIORITY_CTRL0_PORT3_PRIORITY_OFFSET    12\n#define    RTL8367C_VLAN_PORTBASED_PRIORITY_CTRL0_PORT3_PRIORITY_MASK    0x7000\n#define    RTL8367C_VLAN_PORTBASED_PRIORITY_CTRL0_PORT2_PRIORITY_OFFSET    8\n#define    RTL8367C_VLAN_PORTBASED_PRIORITY_CTRL0_PORT2_PRIORITY_MASK    0x700\n#define    RTL8367C_VLAN_PORTBASED_PRIORITY_CTRL0_PORT1_PRIORITY_OFFSET    4\n#define    RTL8367C_VLAN_PORTBASED_PRIORITY_CTRL0_PORT1_PRIORITY_MASK    0x70\n#define    RTL8367C_VLAN_PORTBASED_PRIORITY_CTRL0_PORT0_PRIORITY_OFFSET    0\n#define    RTL8367C_VLAN_PORTBASED_PRIORITY_CTRL0_PORT0_PRIORITY_MASK    0x7\n\n#define    RTL8367C_REG_VLAN_PORTBASED_PRIORITY_CTRL1    0x0852\n#define    RTL8367C_VLAN_PORTBASED_PRIORITY_CTRL1_PORT7_PRIORITY_OFFSET    12\n#define    RTL8367C_VLAN_PORTBASED_PRIORITY_CTRL1_PORT7_PRIORITY_MASK    0x7000\n#define    RTL8367C_VLAN_PORTBASED_PRIORITY_CTRL1_PORT6_PRIORITY_OFFSET    8\n#define    RTL8367C_VLAN_PORTBASED_PRIORITY_CTRL1_PORT6_PRIORITY_MASK    0x700\n#define    RTL8367C_VLAN_PORTBASED_PRIORITY_CTRL1_PORT5_PRIORITY_OFFSET    4\n#define    RTL8367C_VLAN_PORTBASED_PRIORITY_CTRL1_PORT5_PRIORITY_MASK    0x70\n#define    RTL8367C_VLAN_PORTBASED_PRIORITY_CTRL1_PORT4_PRIORITY_OFFSET    0\n#define    RTL8367C_VLAN_PORTBASED_PRIORITY_CTRL1_PORT4_PRIORITY_MASK    0x7\n\n#define    RTL8367C_REG_VLAN_PORTBASED_PRIORITY_CTRL2    0x0853\n#define    RTL8367C_VLAN_PORTBASED_PRIORITY_CTRL2_PORT10_PRIORITY_OFFSET    8\n#define    RTL8367C_VLAN_PORTBASED_PRIORITY_CTRL2_PORT10_PRIORITY_MASK    0x700\n#define    RTL8367C_VLAN_PORTBASED_PRIORITY_CTRL2_PORT9_PRIORITY_OFFSET    4\n#define    RTL8367C_VLAN_PORTBASED_PRIORITY_CTRL2_PORT9_PRIORITY_MASK    0x70\n#define    RTL8367C_VLAN_PORTBASED_PRIORITY_CTRL2_PORT8_PRIORITY_OFFSET    0\n#define    RTL8367C_VLAN_PORTBASED_PRIORITY_CTRL2_PORT8_PRIORITY_MASK    0x7\n\n#define    RTL8367C_REG_VLAN_PPB_PRIORITY_ITEM0_CTRL0    0x0855\n#define    RTL8367C_VLAN_PPB_PRIORITY_ITEM0_CTRL0_PORT3_PRIORITY_OFFSET    12\n#define    RTL8367C_VLAN_PPB_PRIORITY_ITEM0_CTRL0_PORT3_PRIORITY_MASK    0x7000\n#define    RTL8367C_VLAN_PPB_PRIORITY_ITEM0_CTRL0_PORT2_PRIORITY_OFFSET    8\n#define    RTL8367C_VLAN_PPB_PRIORITY_ITEM0_CTRL0_PORT2_PRIORITY_MASK    0x700\n#define    RTL8367C_VLAN_PPB_PRIORITY_ITEM0_CTRL0_PORT1_PRIORITY_OFFSET    4\n#define    RTL8367C_VLAN_PPB_PRIORITY_ITEM0_CTRL0_PORT1_PRIORITY_MASK    0x70\n#define    RTL8367C_VLAN_PPB_PRIORITY_ITEM0_CTRL0_PORT0_PRIORITY_OFFSET    0\n#define    RTL8367C_VLAN_PPB_PRIORITY_ITEM0_CTRL0_PORT0_PRIORITY_MASK    0x7\n\n#define    RTL8367C_REG_VLAN_PPB_PRIORITY_ITEM0_CTRL1    0x0856\n#define    RTL8367C_VLAN_PPB_PRIORITY_ITEM0_CTRL1_PORT7_PRIORITY_OFFSET    12\n#define    RTL8367C_VLAN_PPB_PRIORITY_ITEM0_CTRL1_PORT7_PRIORITY_MASK    0x7000\n#define    RTL8367C_VLAN_PPB_PRIORITY_ITEM0_CTRL1_PORT6_PRIORITY_OFFSET    8\n#define    RTL8367C_VLAN_PPB_PRIORITY_ITEM0_CTRL1_PORT6_PRIORITY_MASK    0x700\n#define    RTL8367C_VLAN_PPB_PRIORITY_ITEM0_CTRL1_PORT5_PRIORITY_OFFSET    4\n#define    RTL8367C_VLAN_PPB_PRIORITY_ITEM0_CTRL1_PORT5_PRIORITY_MASK    0x70\n#define    RTL8367C_VLAN_PPB_PRIORITY_ITEM0_CTRL1_PORT4_PRIORITY_OFFSET    0\n#define    RTL8367C_VLAN_PPB_PRIORITY_ITEM0_CTRL1_PORT4_PRIORITY_MASK    0x7\n\n#define    RTL8367C_REG_VLAN_PPB_PRIORITY_ITEM0_CTRL2    0x0857\n#define    RTL8367C_VLAN_PPB_PRIORITY_ITEM0_CTRL2_PORT10_PRIORITY_OFFSET    8\n#define    RTL8367C_VLAN_PPB_PRIORITY_ITEM0_CTRL2_PORT10_PRIORITY_MASK    0x700\n#define    RTL8367C_VLAN_PPB_PRIORITY_ITEM0_CTRL2_PORT9_PRIORITY_OFFSET    4\n#define    RTL8367C_VLAN_PPB_PRIORITY_ITEM0_CTRL2_PORT9_PRIORITY_MASK    0x70\n#define    RTL8367C_VLAN_PPB_PRIORITY_ITEM0_CTRL2_PORT8_PRIORITY_OFFSET    0\n#define    RTL8367C_VLAN_PPB_PRIORITY_ITEM0_CTRL2_PORT8_PRIORITY_MASK    0x7\n\n#define    RTL8367C_REG_VLAN_PPB_PRIORITY_ITEM1_CTRL0    0x0859\n#define    RTL8367C_VLAN_PPB_PRIORITY_ITEM1_CTRL0_PORT3_PRIORITY_OFFSET    12\n#define    RTL8367C_VLAN_PPB_PRIORITY_ITEM1_CTRL0_PORT3_PRIORITY_MASK    0x7000\n#define    RTL8367C_VLAN_PPB_PRIORITY_ITEM1_CTRL0_PORT2_PRIORITY_OFFSET    8\n#define    RTL8367C_VLAN_PPB_PRIORITY_ITEM1_CTRL0_PORT2_PRIORITY_MASK    0x700\n#define    RTL8367C_VLAN_PPB_PRIORITY_ITEM1_CTRL0_PORT1_PRIORITY_OFFSET    4\n#define    RTL8367C_VLAN_PPB_PRIORITY_ITEM1_CTRL0_PORT1_PRIORITY_MASK    0x70\n#define    RTL8367C_VLAN_PPB_PRIORITY_ITEM1_CTRL0_PORT0_PRIORITY_OFFSET    0\n#define    RTL8367C_VLAN_PPB_PRIORITY_ITEM1_CTRL0_PORT0_PRIORITY_MASK    0x7\n\n#define    RTL8367C_REG_VLAN_PPB_PRIORITY_ITEM1_CTRL1    0x085a\n#define    RTL8367C_VLAN_PPB_PRIORITY_ITEM1_CTRL1_PORT7_PRIORITY_OFFSET    12\n#define    RTL8367C_VLAN_PPB_PRIORITY_ITEM1_CTRL1_PORT7_PRIORITY_MASK    0x7000\n#define    RTL8367C_VLAN_PPB_PRIORITY_ITEM1_CTRL1_PORT6_PRIORITY_OFFSET    8\n#define    RTL8367C_VLAN_PPB_PRIORITY_ITEM1_CTRL1_PORT6_PRIORITY_MASK    0x700\n#define    RTL8367C_VLAN_PPB_PRIORITY_ITEM1_CTRL1_PORT5_PRIORITY_OFFSET    4\n#define    RTL8367C_VLAN_PPB_PRIORITY_ITEM1_CTRL1_PORT5_PRIORITY_MASK    0x70\n#define    RTL8367C_VLAN_PPB_PRIORITY_ITEM1_CTRL1_PORT4_PRIORITY_OFFSET    0\n#define    RTL8367C_VLAN_PPB_PRIORITY_ITEM1_CTRL1_PORT4_PRIORITY_MASK    0x7\n\n#define    RTL8367C_REG_VLAN_PPB_PRIORITY_ITEM1_CTRL2    0x085b\n#define    RTL8367C_VLAN_PPB_PRIORITY_ITEM1_CTRL2_PORT10_PRIORITY_OFFSET    8\n#define    RTL8367C_VLAN_PPB_PRIORITY_ITEM1_CTRL2_PORT10_PRIORITY_MASK    0x700\n#define    RTL8367C_VLAN_PPB_PRIORITY_ITEM1_CTRL2_PORT9_PRIORITY_OFFSET    4\n#define    RTL8367C_VLAN_PPB_PRIORITY_ITEM1_CTRL2_PORT9_PRIORITY_MASK    0x70\n#define    RTL8367C_VLAN_PPB_PRIORITY_ITEM1_CTRL2_PORT8_PRIORITY_OFFSET    0\n#define    RTL8367C_VLAN_PPB_PRIORITY_ITEM1_CTRL2_PORT8_PRIORITY_MASK    0x7\n\n#define    RTL8367C_REG_VLAN_PPB_PRIORITY_ITEM2_CTRL0    0x085d\n#define    RTL8367C_VLAN_PPB_PRIORITY_ITEM2_CTRL0_PORT3_PRIORITY_OFFSET    12\n#define    RTL8367C_VLAN_PPB_PRIORITY_ITEM2_CTRL0_PORT3_PRIORITY_MASK    0x7000\n#define    RTL8367C_VLAN_PPB_PRIORITY_ITEM2_CTRL0_PORT2_PRIORITY_OFFSET    8\n#define    RTL8367C_VLAN_PPB_PRIORITY_ITEM2_CTRL0_PORT2_PRIORITY_MASK    0x700\n#define    RTL8367C_VLAN_PPB_PRIORITY_ITEM2_CTRL0_PORT1_PRIORITY_OFFSET    4\n#define    RTL8367C_VLAN_PPB_PRIORITY_ITEM2_CTRL0_PORT1_PRIORITY_MASK    0x70\n#define    RTL8367C_VLAN_PPB_PRIORITY_ITEM2_CTRL0_PORT0_PRIORITY_OFFSET    0\n#define    RTL8367C_VLAN_PPB_PRIORITY_ITEM2_CTRL0_PORT0_PRIORITY_MASK    0x7\n\n#define    RTL8367C_REG_VLAN_PPB_PRIORITY_ITEM2_CTRL1    0x085e\n#define    RTL8367C_VLAN_PPB_PRIORITY_ITEM2_CTRL1_PORT7_PRIORITY_OFFSET    12\n#define    RTL8367C_VLAN_PPB_PRIORITY_ITEM2_CTRL1_PORT7_PRIORITY_MASK    0x7000\n#define    RTL8367C_VLAN_PPB_PRIORITY_ITEM2_CTRL1_PORT6_PRIORITY_OFFSET    8\n#define    RTL8367C_VLAN_PPB_PRIORITY_ITEM2_CTRL1_PORT6_PRIORITY_MASK    0x700\n#define    RTL8367C_VLAN_PPB_PRIORITY_ITEM2_CTRL1_PORT5_PRIORITY_OFFSET    4\n#define    RTL8367C_VLAN_PPB_PRIORITY_ITEM2_CTRL1_PORT5_PRIORITY_MASK    0x70\n#define    RTL8367C_VLAN_PPB_PRIORITY_ITEM2_CTRL1_PORT4_PRIORITY_OFFSET    0\n#define    RTL8367C_VLAN_PPB_PRIORITY_ITEM2_CTRL1_PORT4_PRIORITY_MASK    0x7\n\n#define    RTL8367C_REG_VLAN_PPB_PRIORITY_ITEM2_CTRL2    0x085f\n#define    RTL8367C_VLAN_PPB_PRIORITY_ITEM2_CTRL2_PORT10_PRIORITY_OFFSET    8\n#define    RTL8367C_VLAN_PPB_PRIORITY_ITEM2_CTRL2_PORT10_PRIORITY_MASK    0x700\n#define    RTL8367C_VLAN_PPB_PRIORITY_ITEM2_CTRL2_PORT9_PRIORITY_OFFSET    4\n#define    RTL8367C_VLAN_PPB_PRIORITY_ITEM2_CTRL2_PORT9_PRIORITY_MASK    0x70\n#define    RTL8367C_VLAN_PPB_PRIORITY_ITEM2_CTRL2_PORT8_PRIORITY_OFFSET    0\n#define    RTL8367C_VLAN_PPB_PRIORITY_ITEM2_CTRL2_PORT8_PRIORITY_MASK    0x7\n\n#define    RTL8367C_REG_VLAN_PPB_PRIORITY_ITEM3_CTRL0    0x0861\n#define    RTL8367C_VLAN_PPB_PRIORITY_ITEM3_CTRL0_PORT3_PRIORITY_OFFSET    12\n#define    RTL8367C_VLAN_PPB_PRIORITY_ITEM3_CTRL0_PORT3_PRIORITY_MASK    0x7000\n#define    RTL8367C_VLAN_PPB_PRIORITY_ITEM3_CTRL0_PORT2_PRIORITY_OFFSET    8\n#define    RTL8367C_VLAN_PPB_PRIORITY_ITEM3_CTRL0_PORT2_PRIORITY_MASK    0x700\n#define    RTL8367C_VLAN_PPB_PRIORITY_ITEM3_CTRL0_PORT1_PRIORITY_OFFSET    4\n#define    RTL8367C_VLAN_PPB_PRIORITY_ITEM3_CTRL0_PORT1_PRIORITY_MASK    0x70\n#define    RTL8367C_VLAN_PPB_PRIORITY_ITEM3_CTRL0_PORT0_PRIORITY_OFFSET    0\n#define    RTL8367C_VLAN_PPB_PRIORITY_ITEM3_CTRL0_PORT0_PRIORITY_MASK    0x7\n\n#define    RTL8367C_REG_VLAN_PPB_PRIORITY_ITEM3_CTRL1    0x0862\n#define    RTL8367C_VLAN_PPB_PRIORITY_ITEM3_CTRL1_PORT7_PRIORITY_OFFSET    12\n#define    RTL8367C_VLAN_PPB_PRIORITY_ITEM3_CTRL1_PORT7_PRIORITY_MASK    0x7000\n#define    RTL8367C_VLAN_PPB_PRIORITY_ITEM3_CTRL1_PORT6_PRIORITY_OFFSET    8\n#define    RTL8367C_VLAN_PPB_PRIORITY_ITEM3_CTRL1_PORT6_PRIORITY_MASK    0x700\n#define    RTL8367C_VLAN_PPB_PRIORITY_ITEM3_CTRL1_PORT5_PRIORITY_OFFSET    4\n#define    RTL8367C_VLAN_PPB_PRIORITY_ITEM3_CTRL1_PORT5_PRIORITY_MASK    0x70\n#define    RTL8367C_VLAN_PPB_PRIORITY_ITEM3_CTRL1_PORT4_PRIORITY_OFFSET    0\n#define    RTL8367C_VLAN_PPB_PRIORITY_ITEM3_CTRL1_PORT4_PRIORITY_MASK    0x7\n\n#define    RTL8367C_REG_VLAN_PPB_PRIORITY_ITEM3_CTRL2    0x0863\n#define    RTL8367C_VLAN_PPB_PRIORITY_ITEM3_CTRL2_PORT10_PRIORITY_OFFSET    8\n#define    RTL8367C_VLAN_PPB_PRIORITY_ITEM3_CTRL2_PORT10_PRIORITY_MASK    0x700\n#define    RTL8367C_VLAN_PPB_PRIORITY_ITEM3_CTRL2_PORT9_PRIORITY_OFFSET    4\n#define    RTL8367C_VLAN_PPB_PRIORITY_ITEM3_CTRL2_PORT9_PRIORITY_MASK    0x70\n#define    RTL8367C_VLAN_PPB_PRIORITY_ITEM3_CTRL2_PORT8_PRIORITY_OFFSET    0\n#define    RTL8367C_VLAN_PPB_PRIORITY_ITEM3_CTRL2_PORT8_PRIORITY_MASK    0x7\n\n#define    RTL8367C_REG_QOS_1Q_PRIORITY_REMAPPING_CTRL0    0x0865\n#define    RTL8367C_QOS_1Q_PRIORITY_REMAPPING_CTRL0_PRIORITY3_OFFSET    12\n#define    RTL8367C_QOS_1Q_PRIORITY_REMAPPING_CTRL0_PRIORITY3_MASK    0x7000\n#define    RTL8367C_QOS_1Q_PRIORITY_REMAPPING_CTRL0_PRIORITY2_OFFSET    8\n#define    RTL8367C_QOS_1Q_PRIORITY_REMAPPING_CTRL0_PRIORITY2_MASK    0x700\n#define    RTL8367C_QOS_1Q_PRIORITY_REMAPPING_CTRL0_PRIORITY1_OFFSET    4\n#define    RTL8367C_QOS_1Q_PRIORITY_REMAPPING_CTRL0_PRIORITY1_MASK    0x70\n#define    RTL8367C_QOS_1Q_PRIORITY_REMAPPING_CTRL0_PRIORITY0_OFFSET    0\n#define    RTL8367C_QOS_1Q_PRIORITY_REMAPPING_CTRL0_PRIORITY0_MASK    0x7\n\n#define    RTL8367C_REG_QOS_1Q_PRIORITY_REMAPPING_CTRL1    0x0866\n#define    RTL8367C_QOS_1Q_PRIORITY_REMAPPING_CTRL1_PRIORITY7_OFFSET    12\n#define    RTL8367C_QOS_1Q_PRIORITY_REMAPPING_CTRL1_PRIORITY7_MASK    0x7000\n#define    RTL8367C_QOS_1Q_PRIORITY_REMAPPING_CTRL1_PRIORITY6_OFFSET    8\n#define    RTL8367C_QOS_1Q_PRIORITY_REMAPPING_CTRL1_PRIORITY6_MASK    0x700\n#define    RTL8367C_QOS_1Q_PRIORITY_REMAPPING_CTRL1_PRIORITY5_OFFSET    4\n#define    RTL8367C_QOS_1Q_PRIORITY_REMAPPING_CTRL1_PRIORITY5_MASK    0x70\n#define    RTL8367C_QOS_1Q_PRIORITY_REMAPPING_CTRL1_PRIORITY4_OFFSET    0\n#define    RTL8367C_QOS_1Q_PRIORITY_REMAPPING_CTRL1_PRIORITY4_MASK    0x7\n\n#define    RTL8367C_REG_QOS_DSCP_TO_PRIORITY_CTRL0    0x0867\n#define    RTL8367C_DSCP3_PRIORITY_OFFSET    12\n#define    RTL8367C_DSCP3_PRIORITY_MASK    0x7000\n#define    RTL8367C_DSCP2_PRIORITY_OFFSET    8\n#define    RTL8367C_DSCP2_PRIORITY_MASK    0x700\n#define    RTL8367C_DSCP1_PRIORITY_OFFSET    4\n#define    RTL8367C_DSCP1_PRIORITY_MASK    0x70\n#define    RTL8367C_DSCP0_PRIORITY_OFFSET    0\n#define    RTL8367C_DSCP0_PRIORITY_MASK    0x7\n\n#define    RTL8367C_REG_QOS_DSCP_TO_PRIORITY_CTRL1    0x0868\n#define    RTL8367C_DSCP7_PRIORITY_OFFSET    12\n#define    RTL8367C_DSCP7_PRIORITY_MASK    0x7000\n#define    RTL8367C_DSCP6_PRIORITY_OFFSET    8\n#define    RTL8367C_DSCP6_PRIORITY_MASK    0x700\n#define    RTL8367C_DSCP5_PRIORITY_OFFSET    4\n#define    RTL8367C_DSCP5_PRIORITY_MASK    0x70\n#define    RTL8367C_DSCP4_PRIORITY_OFFSET    0\n#define    RTL8367C_DSCP4_PRIORITY_MASK    0x7\n\n#define    RTL8367C_REG_QOS_DSCP_TO_PRIORITY_CTRL2    0x0869\n#define    RTL8367C_DSCP11_PRIORITY_OFFSET    12\n#define    RTL8367C_DSCP11_PRIORITY_MASK    0x7000\n#define    RTL8367C_DSCP10_PRIORITY_OFFSET    8\n#define    RTL8367C_DSCP10_PRIORITY_MASK    0x700\n#define    RTL8367C_DSCP9_PRIORITY_OFFSET    4\n#define    RTL8367C_DSCP9_PRIORITY_MASK    0x70\n#define    RTL8367C_DSCP8_PRIORITY_OFFSET    0\n#define    RTL8367C_DSCP8_PRIORITY_MASK    0x7\n\n#define    RTL8367C_REG_QOS_DSCP_TO_PRIORITY_CTRL3    0x086a\n#define    RTL8367C_DSCP15_PRIORITY_OFFSET    12\n#define    RTL8367C_DSCP15_PRIORITY_MASK    0x7000\n#define    RTL8367C_DSCP14_PRIORITY_OFFSET    8\n#define    RTL8367C_DSCP14_PRIORITY_MASK    0x700\n#define    RTL8367C_DSCP13_PRIORITY_OFFSET    4\n#define    RTL8367C_DSCP13_PRIORITY_MASK    0x70\n#define    RTL8367C_DSCP12_PRIORITY_OFFSET    0\n#define    RTL8367C_DSCP12_PRIORITY_MASK    0x7\n\n#define    RTL8367C_REG_QOS_DSCP_TO_PRIORITY_CTRL4    0x086b\n#define    RTL8367C_DSCP19_PRIORITY_OFFSET    12\n#define    RTL8367C_DSCP19_PRIORITY_MASK    0x7000\n#define    RTL8367C_DSCP18_PRIORITY_OFFSET    8\n#define    RTL8367C_DSCP18_PRIORITY_MASK    0x700\n#define    RTL8367C_DSCP17_PRIORITY_OFFSET    4\n#define    RTL8367C_DSCP17_PRIORITY_MASK    0x70\n#define    RTL8367C_DSCP16_PRIORITY_OFFSET    0\n#define    RTL8367C_DSCP16_PRIORITY_MASK    0x7\n\n#define    RTL8367C_REG_QOS_DSCP_TO_PRIORITY_CTRL5    0x086c\n#define    RTL8367C_DSCP23_PRIORITY_OFFSET    12\n#define    RTL8367C_DSCP23_PRIORITY_MASK    0x7000\n#define    RTL8367C_DSCP22_PRIORITY_OFFSET    8\n#define    RTL8367C_DSCP22_PRIORITY_MASK    0x700\n#define    RTL8367C_DSCP21_PRIORITY_OFFSET    4\n#define    RTL8367C_DSCP21_PRIORITY_MASK    0x70\n#define    RTL8367C_DSCP20_PRIORITY_OFFSET    0\n#define    RTL8367C_DSCP20_PRIORITY_MASK    0x7\n\n#define    RTL8367C_REG_QOS_DSCP_TO_PRIORITY_CTRL6    0x086d\n#define    RTL8367C_DSCP27_PRIORITY_OFFSET    12\n#define    RTL8367C_DSCP27_PRIORITY_MASK    0x7000\n#define    RTL8367C_DSCP26_PRIORITY_OFFSET    8\n#define    RTL8367C_DSCP26_PRIORITY_MASK    0x700\n#define    RTL8367C_DSCP25_PRIORITY_OFFSET    4\n#define    RTL8367C_DSCP25_PRIORITY_MASK    0x70\n#define    RTL8367C_DSCP24_PRIORITY_OFFSET    0\n#define    RTL8367C_DSCP24_PRIORITY_MASK    0x7\n\n#define    RTL8367C_REG_QOS_DSCP_TO_PRIORITY_CTRL7    0x086e\n#define    RTL8367C_DSCP31_PRIORITY_OFFSET    12\n#define    RTL8367C_DSCP31_PRIORITY_MASK    0x7000\n#define    RTL8367C_DSCP30_PRIORITY_OFFSET    8\n#define    RTL8367C_DSCP30_PRIORITY_MASK    0x700\n#define    RTL8367C_DSCP29_PRIORITY_OFFSET    4\n#define    RTL8367C_DSCP29_PRIORITY_MASK    0x70\n#define    RTL8367C_DSCP28_PRIORITY_OFFSET    0\n#define    RTL8367C_DSCP28_PRIORITY_MASK    0x7\n\n#define    RTL8367C_REG_QOS_DSCP_TO_PRIORITY_CTRL8    0x086f\n#define    RTL8367C_DSCP35_PRIORITY_OFFSET    12\n#define    RTL8367C_DSCP35_PRIORITY_MASK    0x7000\n#define    RTL8367C_DSCP34_PRIORITY_OFFSET    8\n#define    RTL8367C_DSCP34_PRIORITY_MASK    0x700\n#define    RTL8367C_DSCP33_PRIORITY_OFFSET    4\n#define    RTL8367C_DSCP33_PRIORITY_MASK    0x70\n#define    RTL8367C_DSCP32_PRIORITY_OFFSET    0\n#define    RTL8367C_DSCP32_PRIORITY_MASK    0x7\n\n#define    RTL8367C_REG_QOS_DSCP_TO_PRIORITY_CTRL9    0x0870\n#define    RTL8367C_DSCP39_PRIORITY_OFFSET    12\n#define    RTL8367C_DSCP39_PRIORITY_MASK    0x7000\n#define    RTL8367C_DSCP38_PRIORITY_OFFSET    8\n#define    RTL8367C_DSCP38_PRIORITY_MASK    0x700\n#define    RTL8367C_DSCP37_PRIORITY_OFFSET    4\n#define    RTL8367C_DSCP37_PRIORITY_MASK    0x70\n#define    RTL8367C_DSCP36_PRIORITY_OFFSET    0\n#define    RTL8367C_DSCP36_PRIORITY_MASK    0x7\n\n#define    RTL8367C_REG_QOS_DSCP_TO_PRIORITY_CTRL10    0x0871\n#define    RTL8367C_DSCP43_PRIORITY_OFFSET    12\n#define    RTL8367C_DSCP43_PRIORITY_MASK    0x7000\n#define    RTL8367C_DSCP42_PRIORITY_OFFSET    8\n#define    RTL8367C_DSCP42_PRIORITY_MASK    0x700\n#define    RTL8367C_DSCP41_PRIORITY_OFFSET    4\n#define    RTL8367C_DSCP41_PRIORITY_MASK    0x70\n#define    RTL8367C_DSCP40_PRIORITY_OFFSET    0\n#define    RTL8367C_DSCP40_PRIORITY_MASK    0x7\n\n#define    RTL8367C_REG_QOS_DSCP_TO_PRIORITY_CTRL11    0x0872\n#define    RTL8367C_DSCP47_PRIORITY_OFFSET    12\n#define    RTL8367C_DSCP47_PRIORITY_MASK    0x7000\n#define    RTL8367C_DSCP46_PRIORITY_OFFSET    8\n#define    RTL8367C_DSCP46_PRIORITY_MASK    0x700\n#define    RTL8367C_DSCP45_PRIORITY_OFFSET    4\n#define    RTL8367C_DSCP45_PRIORITY_MASK    0x70\n#define    RTL8367C_DSCP44_PRIORITY_OFFSET    0\n#define    RTL8367C_DSCP44_PRIORITY_MASK    0x7\n\n#define    RTL8367C_REG_QOS_DSCP_TO_PRIORITY_CTRL12    0x0873\n#define    RTL8367C_DSCP51_PRIORITY_OFFSET    12\n#define    RTL8367C_DSCP51_PRIORITY_MASK    0x7000\n#define    RTL8367C_DSCP50_PRIORITY_OFFSET    8\n#define    RTL8367C_DSCP50_PRIORITY_MASK    0x700\n#define    RTL8367C_DSCP49_PRIORITY_OFFSET    4\n#define    RTL8367C_DSCP49_PRIORITY_MASK    0x70\n#define    RTL8367C_DSCP48_PRIORITY_OFFSET    0\n#define    RTL8367C_DSCP48_PRIORITY_MASK    0x7\n\n#define    RTL8367C_REG_QOS_DSCP_TO_PRIORITY_CTRL13    0x0874\n#define    RTL8367C_DSCP55_PRIORITY_OFFSET    12\n#define    RTL8367C_DSCP55_PRIORITY_MASK    0x7000\n#define    RTL8367C_DSCP54_PRIORITY_OFFSET    8\n#define    RTL8367C_DSCP54_PRIORITY_MASK    0x700\n#define    RTL8367C_DSCP53_PRIORITY_OFFSET    4\n#define    RTL8367C_DSCP53_PRIORITY_MASK    0x70\n#define    RTL8367C_DSCP52_PRIORITY_OFFSET    0\n#define    RTL8367C_DSCP52_PRIORITY_MASK    0x7\n\n#define    RTL8367C_REG_QOS_DSCP_TO_PRIORITY_CTRL14    0x0875\n#define    RTL8367C_DSCP59_PRIORITY_OFFSET    12\n#define    RTL8367C_DSCP59_PRIORITY_MASK    0x7000\n#define    RTL8367C_DSCP58_PRIORITY_OFFSET    8\n#define    RTL8367C_DSCP58_PRIORITY_MASK    0x700\n#define    RTL8367C_DSCP57_PRIORITY_OFFSET    4\n#define    RTL8367C_DSCP57_PRIORITY_MASK    0x70\n#define    RTL8367C_DSCP56_PRIORITY_OFFSET    0\n#define    RTL8367C_DSCP56_PRIORITY_MASK    0x7\n\n#define    RTL8367C_REG_QOS_DSCP_TO_PRIORITY_CTRL15    0x0876\n#define    RTL8367C_DSCP63_PRIORITY_OFFSET    12\n#define    RTL8367C_DSCP63_PRIORITY_MASK    0x7000\n#define    RTL8367C_DSCP62_PRIORITY_OFFSET    8\n#define    RTL8367C_DSCP62_PRIORITY_MASK    0x700\n#define    RTL8367C_DSCP61_PRIORITY_OFFSET    4\n#define    RTL8367C_DSCP61_PRIORITY_MASK    0x70\n#define    RTL8367C_DSCP60_PRIORITY_OFFSET    0\n#define    RTL8367C_DSCP60_PRIORITY_MASK    0x7\n\n#define    RTL8367C_REG_QOS_PORTBASED_PRIORITY_CTRL0    0x0877\n#define    RTL8367C_QOS_PORTBASED_PRIORITY_CTRL0_PORT3_PRIORITY_OFFSET    12\n#define    RTL8367C_QOS_PORTBASED_PRIORITY_CTRL0_PORT3_PRIORITY_MASK    0x7000\n#define    RTL8367C_QOS_PORTBASED_PRIORITY_CTRL0_PORT2_PRIORITY_OFFSET    8\n#define    RTL8367C_QOS_PORTBASED_PRIORITY_CTRL0_PORT2_PRIORITY_MASK    0x700\n#define    RTL8367C_QOS_PORTBASED_PRIORITY_CTRL0_PORT1_PRIORITY_OFFSET    4\n#define    RTL8367C_QOS_PORTBASED_PRIORITY_CTRL0_PORT1_PRIORITY_MASK    0x70\n#define    RTL8367C_QOS_PORTBASED_PRIORITY_CTRL0_PORT0_PRIORITY_OFFSET    0\n#define    RTL8367C_QOS_PORTBASED_PRIORITY_CTRL0_PORT0_PRIORITY_MASK    0x7\n\n#define    RTL8367C_REG_QOS_PORTBASED_PRIORITY_CTRL1    0x0878\n#define    RTL8367C_QOS_PORTBASED_PRIORITY_CTRL1_PORT7_PRIORITY_OFFSET    12\n#define    RTL8367C_QOS_PORTBASED_PRIORITY_CTRL1_PORT7_PRIORITY_MASK    0x7000\n#define    RTL8367C_QOS_PORTBASED_PRIORITY_CTRL1_PORT6_PRIORITY_OFFSET    8\n#define    RTL8367C_QOS_PORTBASED_PRIORITY_CTRL1_PORT6_PRIORITY_MASK    0x700\n#define    RTL8367C_QOS_PORTBASED_PRIORITY_CTRL1_PORT5_PRIORITY_OFFSET    4\n#define    RTL8367C_QOS_PORTBASED_PRIORITY_CTRL1_PORT5_PRIORITY_MASK    0x70\n#define    RTL8367C_QOS_PORTBASED_PRIORITY_CTRL1_PORT4_PRIORITY_OFFSET    0\n#define    RTL8367C_QOS_PORTBASED_PRIORITY_CTRL1_PORT4_PRIORITY_MASK    0x7\n\n#define    RTL8367C_REG_DUMMY0879    0x0879\n#define    RTL8367C_DUMMY0879_OFFSET    0\n#define    RTL8367C_DUMMY0879_MASK    0x1\n\n#define    RTL8367C_REG_QOS_PORTBASED_PRIORITY_CTRL2    0x087a\n#define    RTL8367C_QOS_PORTBASED_PRIORITY_CTRL2_PORT10_PRIORITY_OFFSET    8\n#define    RTL8367C_QOS_PORTBASED_PRIORITY_CTRL2_PORT10_PRIORITY_MASK    0x700\n#define    RTL8367C_QOS_PORTBASED_PRIORITY_CTRL2_PORT9_PRIORITY_OFFSET    4\n#define    RTL8367C_QOS_PORTBASED_PRIORITY_CTRL2_PORT9_PRIORITY_MASK    0x70\n#define    RTL8367C_QOS_PORTBASED_PRIORITY_CTRL2_PORT8_PRIORITY_OFFSET    0\n#define    RTL8367C_QOS_PORTBASED_PRIORITY_CTRL2_PORT8_PRIORITY_MASK    0x7\n\n#define    RTL8367C_REG_QOS_INTERNAL_PRIORITY_DECISION_CTRL0    0x087b\n#define    RTL8367C_QOS_INTERNAL_PRIORITY_DECISION_CTRL0_QOS_ACL_WEIGHT_OFFSET    8\n#define    RTL8367C_QOS_INTERNAL_PRIORITY_DECISION_CTRL0_QOS_ACL_WEIGHT_MASK    0xFF00\n#define    RTL8367C_QOS_INTERNAL_PRIORITY_DECISION_CTRL0_QOS_PORT_WEIGHT_OFFSET    0\n#define    RTL8367C_QOS_INTERNAL_PRIORITY_DECISION_CTRL0_QOS_PORT_WEIGHT_MASK    0xFF\n\n#define    RTL8367C_REG_QOS_INTERNAL_PRIORITY_DECISION_CTRL1    0x087c\n#define    RTL8367C_QOS_INTERNAL_PRIORITY_DECISION_CTRL1_QOS_DOT1Q_WEIGHT_OFFSET    8\n#define    RTL8367C_QOS_INTERNAL_PRIORITY_DECISION_CTRL1_QOS_DOT1Q_WEIGHT_MASK    0xFF00\n#define    RTL8367C_QOS_INTERNAL_PRIORITY_DECISION_CTRL1_QOS_DSCP_WEIGHT_OFFSET    0\n#define    RTL8367C_QOS_INTERNAL_PRIORITY_DECISION_CTRL1_QOS_DSCP_WEIGHT_MASK    0xFF\n\n#define    RTL8367C_REG_QOS_INTERNAL_PRIORITY_DECISION_CTRL2    0x087d\n#define    RTL8367C_QOS_INTERNAL_PRIORITY_DECISION_CTRL2_QOS_CVLAN_WEIGHT_OFFSET    8\n#define    RTL8367C_QOS_INTERNAL_PRIORITY_DECISION_CTRL2_QOS_CVLAN_WEIGHT_MASK    0xFF00\n#define    RTL8367C_QOS_INTERNAL_PRIORITY_DECISION_CTRL2_QOS_SVLAN_WEIGHT_OFFSET    0\n#define    RTL8367C_QOS_INTERNAL_PRIORITY_DECISION_CTRL2_QOS_SVLAN_WEIGHT_MASK    0xFF\n\n#define    RTL8367C_REG_QOS_INTERNAL_PRIORITY_DECISION_CTRL3    0x087e\n#define    RTL8367C_QOS_INTERNAL_PRIORITY_DECISION_CTRL3_QOS_SA_WEIGHT_OFFSET    8\n#define    RTL8367C_QOS_INTERNAL_PRIORITY_DECISION_CTRL3_QOS_SA_WEIGHT_MASK    0xFF00\n#define    RTL8367C_QOS_INTERNAL_PRIORITY_DECISION_CTRL3_QOS_LUTFWD_WEIGHT_OFFSET    0\n#define    RTL8367C_QOS_INTERNAL_PRIORITY_DECISION_CTRL3_QOS_LUTFWD_WEIGHT_MASK    0xFF\n\n#define    RTL8367C_REG_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL0    0x087f\n#define    RTL8367C_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL0_PRIORITY3_OFFSET    12\n#define    RTL8367C_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL0_PRIORITY3_MASK    0x7000\n#define    RTL8367C_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL0_PRIORITY2_OFFSET    8\n#define    RTL8367C_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL0_PRIORITY2_MASK    0x700\n#define    RTL8367C_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL0_PRIORITY1_OFFSET    4\n#define    RTL8367C_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL0_PRIORITY1_MASK    0x70\n#define    RTL8367C_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL0_PRIORITY0_OFFSET    0\n#define    RTL8367C_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL0_PRIORITY0_MASK    0x7\n\n#define    RTL8367C_REG_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL1    0x0880\n#define    RTL8367C_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL1_PRIORITY7_OFFSET    12\n#define    RTL8367C_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL1_PRIORITY7_MASK    0x7000\n#define    RTL8367C_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL1_PRIORITY6_OFFSET    8\n#define    RTL8367C_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL1_PRIORITY6_MASK    0x700\n#define    RTL8367C_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL1_PRIORITY5_OFFSET    4\n#define    RTL8367C_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL1_PRIORITY5_MASK    0x70\n#define    RTL8367C_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL1_PRIORITY4_OFFSET    0\n#define    RTL8367C_QOS_PRIORITY_REMAPPING_IN_CPU_CTRL1_PRIORITY4_MASK    0x7\n\n#define    RTL8367C_REG_QOS_TRAP_PRIORITY0    0x0881\n#define    RTL8367C_UNKNOWN_MC_PRIORTY_OFFSET    12\n#define    RTL8367C_UNKNOWN_MC_PRIORTY_MASK    0x7000\n#define    RTL8367C_SVLAN_PRIOIRTY_OFFSET    8\n#define    RTL8367C_SVLAN_PRIOIRTY_MASK    0x700\n#define    RTL8367C_OAM_PRIOIRTY_OFFSET    4\n#define    RTL8367C_OAM_PRIOIRTY_MASK    0x70\n#define    RTL8367C_DOT1X_PRIORTY_OFFSET    0\n#define    RTL8367C_DOT1X_PRIORTY_MASK    0x7\n\n#define    RTL8367C_REG_QOS_TRAP_PRIORITY1    0x0882\n#define    RTL8367C_DW8051_TRAP_PRI_OFFSET    4\n#define    RTL8367C_DW8051_TRAP_PRI_MASK    0x70\n#define    RTL8367C_EEELLDP_TRAP_PRI_OFFSET    0\n#define    RTL8367C_EEELLDP_TRAP_PRI_MASK    0x7\n\n#define    RTL8367C_REG_MAX_LENGTH_CFG    0x0883\n#define    RTL8367C_MAX_LENGTH_GIGA_OFFSET    8\n#define    RTL8367C_MAX_LENGTH_GIGA_MASK    0xFF00\n#define    RTL8367C_MAX_LENGTH_10_100M_OFFSET    0\n#define    RTL8367C_MAX_LENGTH_10_100M_MASK    0xFF\n\n#define    RTL8367C_REG_MAX_LEN_RX_TX    0x0884\n#define    RTL8367C_MAX_LEN_RX_TX_OFFSET    0\n#define    RTL8367C_MAX_LEN_RX_TX_MASK    0x3\n\n#define    RTL8367C_REG_QOS_INTERNAL_PRIORITY_DECISION2_CTRL0    0x0885\n#define    RTL8367C_QOS_INTERNAL_PRIORITY_DECISION2_CTRL0_QOS_ACL_WEIGHT_OFFSET    8\n#define    RTL8367C_QOS_INTERNAL_PRIORITY_DECISION2_CTRL0_QOS_ACL_WEIGHT_MASK    0xFF00\n#define    RTL8367C_QOS_INTERNAL_PRIORITY_DECISION2_CTRL0_QOS_PORT_WEIGHT_OFFSET    0\n#define    RTL8367C_QOS_INTERNAL_PRIORITY_DECISION2_CTRL0_QOS_PORT_WEIGHT_MASK    0xFF\n\n#define    RTL8367C_REG_QOS_INTERNAL_PRIORITY_DECISION2_CTRL1    0x0886\n#define    RTL8367C_QOS_INTERNAL_PRIORITY_DECISION2_CTRL1_QOS_DOT1Q_WEIGHT_OFFSET    8\n#define    RTL8367C_QOS_INTERNAL_PRIORITY_DECISION2_CTRL1_QOS_DOT1Q_WEIGHT_MASK    0xFF00\n#define    RTL8367C_QOS_INTERNAL_PRIORITY_DECISION2_CTRL1_QOS_DSCP_WEIGHT_OFFSET    0\n#define    RTL8367C_QOS_INTERNAL_PRIORITY_DECISION2_CTRL1_QOS_DSCP_WEIGHT_MASK    0xFF\n\n#define    RTL8367C_REG_QOS_INTERNAL_PRIORITY_DECISION2_CTRL2    0x0887\n#define    RTL8367C_QOS_INTERNAL_PRIORITY_DECISION2_CTRL2_QOS_CVLAN_WEIGHT_OFFSET    8\n#define    RTL8367C_QOS_INTERNAL_PRIORITY_DECISION2_CTRL2_QOS_CVLAN_WEIGHT_MASK    0xFF00\n#define    RTL8367C_QOS_INTERNAL_PRIORITY_DECISION2_CTRL2_QOS_SVLAN_WEIGHT_OFFSET    0\n#define    RTL8367C_QOS_INTERNAL_PRIORITY_DECISION2_CTRL2_QOS_SVLAN_WEIGHT_MASK    0xFF\n\n#define    RTL8367C_REG_QOS_INTERNAL_PRIORITY_DECISION2_CTRL3    0x0888\n#define    RTL8367C_QOS_INTERNAL_PRIORITY_DECISION2_CTRL3_QOS_SA_WEIGHT_OFFSET    8\n#define    RTL8367C_QOS_INTERNAL_PRIORITY_DECISION2_CTRL3_QOS_SA_WEIGHT_MASK    0xFF00\n#define    RTL8367C_QOS_INTERNAL_PRIORITY_DECISION2_CTRL3_QOS_LUTFWD_WEIGHT_OFFSET    0\n#define    RTL8367C_QOS_INTERNAL_PRIORITY_DECISION2_CTRL3_QOS_LUTFWD_WEIGHT_MASK    0xFF\n\n#define    RTL8367C_REG_QOS_INTERNAL_PRIORITY_DECISION_IDX    0x0889\n#define    RTL8367C_QOS_INTERNAL_PRIORITY_DECISION_IDX_OFFSET    0\n#define    RTL8367C_QOS_INTERNAL_PRIORITY_DECISION_IDX_MASK    0x7FF\n\n#define    RTL8367C_REG_MAX_LENGTH_CFG_EXT    0x088a\n#define    RTL8367C_MAX_LENGTH_GIGA_EXT_OFFSET    3\n#define    RTL8367C_MAX_LENGTH_GIGA_EXT_MASK    0x38\n#define    RTL8367C_MAX_LENGTH_10_100M_EXT_OFFSET    0\n#define    RTL8367C_MAX_LENGTH_10_100M_EXT_MASK    0x7\n\n#define    RTL8367C_REG_MAX_LEN_RX_TX_CFG0    0x088c\n#define    RTL8367C_MAX_LEN_RX_TX_CFG0_OFFSET    0\n#define    RTL8367C_MAX_LEN_RX_TX_CFG0_MASK    0x3FFF\n\n#define    RTL8367C_REG_MAX_LEN_RX_TX_CFG1    0x088d\n#define    RTL8367C_MAX_LEN_RX_TX_CFG1_OFFSET    0\n#define    RTL8367C_MAX_LEN_RX_TX_CFG1_MASK    0x3FFF\n\n#define    RTL8367C_REG_UNDA_FLOODING_PMSK    0x0890\n#define    RTL8367C_UNDA_FLOODING_PMSK_OFFSET    0\n#define    RTL8367C_UNDA_FLOODING_PMSK_MASK    0x7FF\n\n#define    RTL8367C_REG_UNMCAST_FLOADING_PMSK    0x0891\n#define    RTL8367C_UNMCAST_FLOADING_PMSK_OFFSET    0\n#define    RTL8367C_UNMCAST_FLOADING_PMSK_MASK    0x7FF\n\n#define    RTL8367C_REG_BCAST_FLOADING_PMSK    0x0892\n#define    RTL8367C_BCAST_FLOADING_PMSK_OFFSET    0\n#define    RTL8367C_BCAST_FLOADING_PMSK_MASK    0x7FF\n\n#define    RTL8367C_REG_PORT_TRUNK_HASH_MAPPING_CTRL2    0x08a0\n#define    RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL2_HASH7_OFFSET    14\n#define    RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL2_HASH7_MASK    0xC000\n#define    RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL2_HASH6_OFFSET    12\n#define    RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL2_HASH6_MASK    0x3000\n#define    RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL2_HASH5_OFFSET    10\n#define    RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL2_HASH5_MASK    0xC00\n#define    RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL2_HASH4_OFFSET    8\n#define    RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL2_HASH4_MASK    0x300\n#define    RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL2_HASH3_OFFSET    6\n#define    RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL2_HASH3_MASK    0xC0\n#define    RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL2_HASH2_OFFSET    4\n#define    RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL2_HASH2_MASK    0x30\n#define    RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL2_HASH1_OFFSET    2\n#define    RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL2_HASH1_MASK    0xC\n#define    RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL2_HASH0_OFFSET    0\n#define    RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL2_HASH0_MASK    0x3\n\n#define    RTL8367C_REG_PORT_TRUNK_HASH_MAPPING_CTRL3    0x08a1\n#define    RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL3_HASH15_OFFSET    14\n#define    RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL3_HASH15_MASK    0xC000\n#define    RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL3_HASH14_OFFSET    12\n#define    RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL3_HASH14_MASK    0x3000\n#define    RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL3_HASH13_OFFSET    10\n#define    RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL3_HASH13_MASK    0xC00\n#define    RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL3_HASH12_OFFSET    8\n#define    RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL3_HASH12_MASK    0x300\n#define    RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL3_HASH11_OFFSET    6\n#define    RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL3_HASH11_MASK    0xC0\n#define    RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL3_HASH10_OFFSET    4\n#define    RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL3_HASH10_MASK    0x30\n#define    RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL3_HASH9_OFFSET    2\n#define    RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL3_HASH9_MASK    0xC\n#define    RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL3_HASH8_OFFSET    0\n#define    RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL3_HASH8_MASK    0x3\n\n#define    RTL8367C_REG_PORT_ISOLATION_PORT0_MASK    0x08a2\n#define    RTL8367C_PORT_ISOLATION_PORT0_MASK_OFFSET    0\n#define    RTL8367C_PORT_ISOLATION_PORT0_MASK_MASK    0x7FF\n\n#define    RTL8367C_REG_PORT_ISOLATION_PORT1_MASK    0x08a3\n#define    RTL8367C_PORT_ISOLATION_PORT1_MASK_OFFSET    0\n#define    RTL8367C_PORT_ISOLATION_PORT1_MASK_MASK    0x7FF\n\n#define    RTL8367C_REG_PORT_ISOLATION_PORT2_MASK    0x08a4\n#define    RTL8367C_PORT_ISOLATION_PORT2_MASK_OFFSET    0\n#define    RTL8367C_PORT_ISOLATION_PORT2_MASK_MASK    0x7FF\n\n#define    RTL8367C_REG_PORT_ISOLATION_PORT3_MASK    0x08a5\n#define    RTL8367C_PORT_ISOLATION_PORT3_MASK_OFFSET    0\n#define    RTL8367C_PORT_ISOLATION_PORT3_MASK_MASK    0x7FF\n\n#define    RTL8367C_REG_PORT_ISOLATION_PORT4_MASK    0x08a6\n#define    RTL8367C_PORT_ISOLATION_PORT4_MASK_OFFSET    0\n#define    RTL8367C_PORT_ISOLATION_PORT4_MASK_MASK    0x7FF\n\n#define    RTL8367C_REG_PORT_ISOLATION_PORT5_MASK    0x08a7\n#define    RTL8367C_PORT_ISOLATION_PORT5_MASK_OFFSET    0\n#define    RTL8367C_PORT_ISOLATION_PORT5_MASK_MASK    0x7FF\n\n#define    RTL8367C_REG_PORT_ISOLATION_PORT6_MASK    0x08a8\n#define    RTL8367C_PORT_ISOLATION_PORT6_MASK_OFFSET    0\n#define    RTL8367C_PORT_ISOLATION_PORT6_MASK_MASK    0x7FF\n\n#define    RTL8367C_REG_PORT_ISOLATION_PORT7_MASK    0x08a9\n#define    RTL8367C_PORT_ISOLATION_PORT7_MASK_OFFSET    0\n#define    RTL8367C_PORT_ISOLATION_PORT7_MASK_MASK    0x7FF\n\n#define    RTL8367C_REG_PORT_ISOLATION_PORT8_MASK    0x08aa\n#define    RTL8367C_PORT_ISOLATION_PORT8_MASK_OFFSET    0\n#define    RTL8367C_PORT_ISOLATION_PORT8_MASK_MASK    0x7FF\n\n#define    RTL8367C_REG_PORT_ISOLATION_PORT9_MASK    0x08ab\n#define    RTL8367C_PORT_ISOLATION_PORT9_MASK_OFFSET    0\n#define    RTL8367C_PORT_ISOLATION_PORT9_MASK_MASK    0x7FF\n\n#define    RTL8367C_REG_PORT_ISOLATION_PORT10_MASK    0x08ac\n#define    RTL8367C_PORT_ISOLATION_PORT10_MASK_OFFSET    0\n#define    RTL8367C_PORT_ISOLATION_PORT10_MASK_MASK    0x7FF\n\n#define    RTL8367C_REG_FORCE_CTRL    0x08b4\n#define    RTL8367C_FORCE_CTRL_OFFSET    0\n#define    RTL8367C_FORCE_CTRL_MASK    0x7FF\n\n#define    RTL8367C_REG_FORCE_PORT0_MASK    0x08b5\n#define    RTL8367C_FORCE_PORT0_MASK_OFFSET    0\n#define    RTL8367C_FORCE_PORT0_MASK_MASK    0x7FF\n\n#define    RTL8367C_REG_FORCE_PORT1_MASK    0x08b6\n#define    RTL8367C_FORCE_PORT1_MASK_OFFSET    0\n#define    RTL8367C_FORCE_PORT1_MASK_MASK    0x7FF\n\n#define    RTL8367C_REG_FORCE_PORT2_MASK    0x08b7\n#define    RTL8367C_FORCE_PORT2_MASK_OFFSET    0\n#define    RTL8367C_FORCE_PORT2_MASK_MASK    0x7FF\n\n#define    RTL8367C_REG_FORCE_PORT3_MASK    0x08b8\n#define    RTL8367C_FORCE_PORT3_MASK_OFFSET    0\n#define    RTL8367C_FORCE_PORT3_MASK_MASK    0x7FF\n\n#define    RTL8367C_REG_FORCE_PORT4_MASK    0x08b9\n#define    RTL8367C_FORCE_PORT4_MASK_OFFSET    0\n#define    RTL8367C_FORCE_PORT4_MASK_MASK    0x7FF\n\n#define    RTL8367C_REG_FORCE_PORT5_MASK    0x08ba\n#define    RTL8367C_FORCE_PORT5_MASK_OFFSET    0\n#define    RTL8367C_FORCE_PORT5_MASK_MASK    0x7FF\n\n#define    RTL8367C_REG_FORCE_PORT6_MASK    0x08bb\n#define    RTL8367C_FORCE_PORT6_MASK_OFFSET    0\n#define    RTL8367C_FORCE_PORT6_MASK_MASK    0x7FF\n\n#define    RTL8367C_REG_FORCE_PORT7_MASK    0x08bc\n#define    RTL8367C_FORCE_PORT7_MASK_OFFSET    0\n#define    RTL8367C_FORCE_PORT7_MASK_MASK    0x7FF\n\n#define    RTL8367C_REG_FORCE_PORT8_MASK    0x08bd\n#define    RTL8367C_FORCE_PORT8_MASK_OFFSET    0\n#define    RTL8367C_FORCE_PORT8_MASK_MASK    0x7FF\n\n#define    RTL8367C_REG_FORCE_PORT9_MASK    0x08be\n#define    RTL8367C_FORCE_PORT9_MASK_OFFSET    0\n#define    RTL8367C_FORCE_PORT9_MASK_MASK    0x7FF\n\n#define    RTL8367C_REG_FORCE_PORT10_MASK    0x08bf\n#define    RTL8367C_FORCE_PORT10_MASK_OFFSET    0\n#define    RTL8367C_FORCE_PORT10_MASK_MASK    0x7FF\n\n#define    RTL8367C_REG_SOURCE_PORT_PERMIT    0x08c5\n#define    RTL8367C_SOURCE_PORT_PERMIT_OFFSET    0\n#define    RTL8367C_SOURCE_PORT_PERMIT_MASK    0x7FF\n\n#define    RTL8367C_REG_IPMCAST_VLAN_LEAKY    0x08c6\n#define    RTL8367C_IPMCAST_VLAN_LEAKY_OFFSET    0\n#define    RTL8367C_IPMCAST_VLAN_LEAKY_MASK    0x7FF\n\n#define    RTL8367C_REG_IPMCAST_PORTISO_LEAKY    0x08c7\n#define    RTL8367C_IPMCAST_PORTISO_LEAKY_OFFSET    0\n#define    RTL8367C_IPMCAST_PORTISO_LEAKY_MASK    0x7FF\n\n#define    RTL8367C_REG_PORT_SECURITY_CTRL    0x08c8\n#define    RTL8367C_UNKNOWN_UNICAST_DA_BEHAVE_OFFSET    6\n#define    RTL8367C_UNKNOWN_UNICAST_DA_BEHAVE_MASK    0xC0\n#define    RTL8367C_LUT_LEARN_OVER_ACT_OFFSET    4\n#define    RTL8367C_LUT_LEARN_OVER_ACT_MASK    0x30\n#define    RTL8367C_UNMATCHED_SA_BEHAVE_OFFSET    2\n#define    RTL8367C_UNMATCHED_SA_BEHAVE_MASK    0xC\n#define    RTL8367C_UNKNOWN_SA_BEHAVE_OFFSET    0\n#define    RTL8367C_UNKNOWN_SA_BEHAVE_MASK    0x3\n\n#define    RTL8367C_REG_UNKNOWN_IPV4_MULTICAST_CTRL0    0x08c9\n#define    RTL8367C_PORT7_UNKNOWN_IP4_MCAST_OFFSET    14\n#define    RTL8367C_PORT7_UNKNOWN_IP4_MCAST_MASK    0xC000\n#define    RTL8367C_PORT6_UNKNOWN_IP4_MCAST_OFFSET    12\n#define    RTL8367C_PORT6_UNKNOWN_IP4_MCAST_MASK    0x3000\n#define    RTL8367C_PORT5_UNKNOWN_IP4_MCAST_OFFSET    10\n#define    RTL8367C_PORT5_UNKNOWN_IP4_MCAST_MASK    0xC00\n#define    RTL8367C_PORT4_UNKNOWN_IP4_MCAST_OFFSET    8\n#define    RTL8367C_PORT4_UNKNOWN_IP4_MCAST_MASK    0x300\n#define    RTL8367C_PORT3_UNKNOWN_IP4_MCAST_OFFSET    6\n#define    RTL8367C_PORT3_UNKNOWN_IP4_MCAST_MASK    0xC0\n#define    RTL8367C_PORT2_UNKNOWN_IP4_MCAST_OFFSET    4\n#define    RTL8367C_PORT2_UNKNOWN_IP4_MCAST_MASK    0x30\n#define    RTL8367C_PORT1_UNKNOWN_IP4_MCAST_OFFSET    2\n#define    RTL8367C_PORT1_UNKNOWN_IP4_MCAST_MASK    0xC\n#define    RTL8367C_PORT0_UNKNOWN_IP4_MCAST_OFFSET    0\n#define    RTL8367C_PORT0_UNKNOWN_IP4_MCAST_MASK    0x3\n\n#define    RTL8367C_REG_UNKNOWN_IPV4_MULTICAST_CTRL1    0x08ca\n#define    RTL8367C_PORT10_UNKNOWN_IP4_MCAST_OFFSET    4\n#define    RTL8367C_PORT10_UNKNOWN_IP4_MCAST_MASK    0x30\n#define    RTL8367C_PORT9_UNKNOWN_IP4_MCAST_OFFSET    2\n#define    RTL8367C_PORT9_UNKNOWN_IP4_MCAST_MASK    0xC\n#define    RTL8367C_PORT8_UNKNOWN_IP4_MCAST_OFFSET    0\n#define    RTL8367C_PORT8_UNKNOWN_IP4_MCAST_MASK    0x3\n\n#define    RTL8367C_REG_UNKNOWN_IPV6_MULTICAST_CTRL0    0x08cb\n#define    RTL8367C_PORT7_UNKNOWN_IP6_MCAST_OFFSET    14\n#define    RTL8367C_PORT7_UNKNOWN_IP6_MCAST_MASK    0xC000\n#define    RTL8367C_PORT6_UNKNOWN_IP6_MCAST_OFFSET    12\n#define    RTL8367C_PORT6_UNKNOWN_IP6_MCAST_MASK    0x3000\n#define    RTL8367C_PORT5_UNKNOWN_IP6_MCAST_OFFSET    10\n#define    RTL8367C_PORT5_UNKNOWN_IP6_MCAST_MASK    0xC00\n#define    RTL8367C_PORT4_UNKNOWN_IP6_MCAST_OFFSET    8\n#define    RTL8367C_PORT4_UNKNOWN_IP6_MCAST_MASK    0x300\n#define    RTL8367C_PORT3_UNKNOWN_IP6_MCAST_OFFSET    6\n#define    RTL8367C_PORT3_UNKNOWN_IP6_MCAST_MASK    0xC0\n#define    RTL8367C_PORT2_UNKNOWN_IP6_MCAST_OFFSET    4\n#define    RTL8367C_PORT2_UNKNOWN_IP6_MCAST_MASK    0x30\n#define    RTL8367C_PORT1_UNKNOWN_IP6_MCAST_OFFSET    2\n#define    RTL8367C_PORT1_UNKNOWN_IP6_MCAST_MASK    0xC\n#define    RTL8367C_PORT0_UNKNOWN_IP6_MCAST_OFFSET    0\n#define    RTL8367C_PORT0_UNKNOWN_IP6_MCAST_MASK    0x3\n\n#define    RTL8367C_REG_UNKNOWN_IPV6_MULTICAST_CTRL1    0x08cc\n#define    RTL8367C_PORT10_UNKNOWN_IP6_MCAST_OFFSET    4\n#define    RTL8367C_PORT10_UNKNOWN_IP6_MCAST_MASK    0x30\n#define    RTL8367C_PORT9_UNKNOWN_IP6_MCAST_OFFSET    2\n#define    RTL8367C_PORT9_UNKNOWN_IP6_MCAST_MASK    0xC\n#define    RTL8367C_PORT8_UNKNOWN_IP6_MCAST_OFFSET    0\n#define    RTL8367C_PORT8_UNKNOWN_IP6_MCAST_MASK    0x3\n\n#define    RTL8367C_REG_UNKNOWN_L2_MULTICAST_CTRL0    0x08cd\n#define    RTL8367C_PORT7_UNKNOWN_L2_MCAST_OFFSET    14\n#define    RTL8367C_PORT7_UNKNOWN_L2_MCAST_MASK    0xC000\n#define    RTL8367C_PORT6_UNKNOWN_L2_MCAST_OFFSET    12\n#define    RTL8367C_PORT6_UNKNOWN_L2_MCAST_MASK    0x3000\n#define    RTL8367C_PORT5_UNKNOWN_L2_MCAST_OFFSET    10\n#define    RTL8367C_PORT5_UNKNOWN_L2_MCAST_MASK    0xC00\n#define    RTL8367C_PORT4_UNKNOWN_L2_MCAST_OFFSET    8\n#define    RTL8367C_PORT4_UNKNOWN_L2_MCAST_MASK    0x300\n#define    RTL8367C_PORT3_UNKNOWN_L2_MCAST_OFFSET    6\n#define    RTL8367C_PORT3_UNKNOWN_L2_MCAST_MASK    0xC0\n#define    RTL8367C_PORT2_UNKNOWN_L2_MCAST_OFFSET    4\n#define    RTL8367C_PORT2_UNKNOWN_L2_MCAST_MASK    0x30\n#define    RTL8367C_PORT1_UNKNOWN_L2_MCAST_OFFSET    2\n#define    RTL8367C_PORT1_UNKNOWN_L2_MCAST_MASK    0xC\n#define    RTL8367C_PORT0_UNKNOWN_L2_MCAST_OFFSET    0\n#define    RTL8367C_PORT0_UNKNOWN_L2_MCAST_MASK    0x3\n\n#define    RTL8367C_REG_PORT_TRUNK_DROP_CTRL    0x08ce\n#define    RTL8367C_PORT_TRUNK_DROP_CTRL_OFFSET    0\n#define    RTL8367C_PORT_TRUNK_DROP_CTRL_MASK    0x1\n\n#define    RTL8367C_REG_PORT_TRUNK_CTRL    0x08cf\n#define    RTL8367C_PORT_TRUNK_DUMB_OFFSET    8\n#define    RTL8367C_PORT_TRUNK_DUMB_MASK    0x100\n#define    RTL8367C_PORT_TRUNK_FLOOD_OFFSET    7\n#define    RTL8367C_PORT_TRUNK_FLOOD_MASK    0x80\n#define    RTL8367C_DPORT_HASH_OFFSET    6\n#define    RTL8367C_DPORT_HASH_MASK    0x40\n#define    RTL8367C_SPORT_HASH_OFFSET    5\n#define    RTL8367C_SPORT_HASH_MASK    0x20\n#define    RTL8367C_DIP_HASH_OFFSET    4\n#define    RTL8367C_DIP_HASH_MASK    0x10\n#define    RTL8367C_SIP_HASH_OFFSET    3\n#define    RTL8367C_SIP_HASH_MASK    0x8\n#define    RTL8367C_DMAC_HASH_OFFSET    2\n#define    RTL8367C_DMAC_HASH_MASK    0x4\n#define    RTL8367C_SMAC_HASH_OFFSET    1\n#define    RTL8367C_SMAC_HASH_MASK    0x2\n#define    RTL8367C_SPA_HASH_OFFSET    0\n#define    RTL8367C_SPA_HASH_MASK    0x1\n\n#define    RTL8367C_REG_PORT_TRUNK_GROUP_MASK    0x08d0\n#define    RTL8367C_PORT_TRUNK_GROUP2_MASK_OFFSET    8\n#define    RTL8367C_PORT_TRUNK_GROUP2_MASK_MASK    0x300\n#define    RTL8367C_PORT_TRUNK_GROUP1_MASK_OFFSET    4\n#define    RTL8367C_PORT_TRUNK_GROUP1_MASK_MASK    0xF0\n#define    RTL8367C_PORT_TRUNK_GROUP0_MASK_OFFSET    0\n#define    RTL8367C_PORT_TRUNK_GROUP0_MASK_MASK    0xF\n\n#define    RTL8367C_REG_PORT_TRUNK_FLOWCTRL    0x08d1\n#define    RTL8367C_EN_FLOWCTRL_TG2_OFFSET    2\n#define    RTL8367C_EN_FLOWCTRL_TG2_MASK    0x4\n#define    RTL8367C_EN_FLOWCTRL_TG1_OFFSET    1\n#define    RTL8367C_EN_FLOWCTRL_TG1_MASK    0x2\n#define    RTL8367C_EN_FLOWCTRL_TG0_OFFSET    0\n#define    RTL8367C_EN_FLOWCTRL_TG0_MASK    0x1\n\n#define    RTL8367C_REG_PORT_TRUNK_HASH_MAPPING_CTRL0    0x08d2\n#define    RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL0_HASH7_OFFSET    14\n#define    RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL0_HASH7_MASK    0xC000\n#define    RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL0_HASH6_OFFSET    12\n#define    RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL0_HASH6_MASK    0x3000\n#define    RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL0_HASH5_OFFSET    10\n#define    RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL0_HASH5_MASK    0xC00\n#define    RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL0_HASH4_OFFSET    8\n#define    RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL0_HASH4_MASK    0x300\n#define    RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL0_HASH3_OFFSET    6\n#define    RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL0_HASH3_MASK    0xC0\n#define    RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL0_HASH2_OFFSET    4\n#define    RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL0_HASH2_MASK    0x30\n#define    RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL0_HASH1_OFFSET    2\n#define    RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL0_HASH1_MASK    0xC\n#define    RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL0_HASH0_OFFSET    0\n#define    RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL0_HASH0_MASK    0x3\n\n#define    RTL8367C_REG_PORT_TRUNK_HASH_MAPPING_CTRL1    0x08d3\n#define    RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL1_HASH15_OFFSET    14\n#define    RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL1_HASH15_MASK    0xC000\n#define    RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL1_HASH14_OFFSET    12\n#define    RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL1_HASH14_MASK    0x3000\n#define    RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL1_HASH13_OFFSET    10\n#define    RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL1_HASH13_MASK    0xC00\n#define    RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL1_HASH12_OFFSET    8\n#define    RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL1_HASH12_MASK    0x300\n#define    RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL1_HASH11_OFFSET    6\n#define    RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL1_HASH11_MASK    0xC0\n#define    RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL1_HASH10_OFFSET    4\n#define    RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL1_HASH10_MASK    0x30\n#define    RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL1_HASH9_OFFSET    2\n#define    RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL1_HASH9_MASK    0xC\n#define    RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL1_HASH8_OFFSET    0\n#define    RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL1_HASH8_MASK    0x3\n\n#define    RTL8367C_REG_DOS_CFG    0x08d4\n#define    RTL8367C_DROP_ICMPFRAGMENT_OFFSET    9\n#define    RTL8367C_DROP_ICMPFRAGMENT_MASK    0x200\n#define    RTL8367C_DROP_TCPFRAGERROR_OFFSET    8\n#define    RTL8367C_DROP_TCPFRAGERROR_MASK    0x100\n#define    RTL8367C_DROP_TCPSHORTHDR_OFFSET    7\n#define    RTL8367C_DROP_TCPSHORTHDR_MASK    0x80\n#define    RTL8367C_DROP_SYN1024_OFFSET    6\n#define    RTL8367C_DROP_SYN1024_MASK    0x40\n#define    RTL8367C_DROP_NULLSCAN_OFFSET    5\n#define    RTL8367C_DROP_NULLSCAN_MASK    0x20\n#define    RTL8367C_DROP_XMASCAN_OFFSET    4\n#define    RTL8367C_DROP_XMASCAN_MASK    0x10\n#define    RTL8367C_DROP_SYNFINSCAN_OFFSET    3\n#define    RTL8367C_DROP_SYNFINSCAN_MASK    0x8\n#define    RTL8367C_DROP_BLATATTACKS_OFFSET    2\n#define    RTL8367C_DROP_BLATATTACKS_MASK    0x4\n#define    RTL8367C_DROP_LANDATTACKS_OFFSET    1\n#define    RTL8367C_DROP_LANDATTACKS_MASK    0x2\n#define    RTL8367C_DROP_DAEQSA_OFFSET    0\n#define    RTL8367C_DROP_DAEQSA_MASK    0x1\n\n#define    RTL8367C_REG_UNKNOWN_L2_MULTICAST_CTRL1    0x08d5\n#define    RTL8367C_PORT10_UNKNOWN_L2_MCAST_OFFSET    4\n#define    RTL8367C_PORT10_UNKNOWN_L2_MCAST_MASK    0x30\n#define    RTL8367C_PORT9_UNKNOWN_L2_MCAST_OFFSET    2\n#define    RTL8367C_PORT9_UNKNOWN_L2_MCAST_MASK    0xC\n#define    RTL8367C_PORT8_UNKNOWN_L2_MCAST_OFFSET    0\n#define    RTL8367C_PORT8_UNKNOWN_L2_MCAST_MASK    0x3\n\n#define    RTL8367C_REG_VLAN_EGRESS_KEEP_CTRL4    0x08d6\n#define    RTL8367C_PORT9_VLAN_KEEP_MASK_OFFSET    8\n#define    RTL8367C_PORT9_VLAN_KEEP_MASK_MASK    0xFF00\n#define    RTL8367C_PORT8_VLAN_KEEP_MASK_OFFSET    0\n#define    RTL8367C_PORT8_VLAN_KEEP_MASK_MASK    0xFF\n\n#define    RTL8367C_REG_VLAN_EGRESS_KEEP_CTRL5    0x08d7\n#define    RTL8367C_VLAN_EGRESS_KEEP_CTRL5_OFFSET    0\n#define    RTL8367C_VLAN_EGRESS_KEEP_CTRL5_MASK    0xFF\n\n#define    RTL8367C_REG_VLAN_EGRESS_KEEP_CTRL0_EXT    0x08d8\n#define    RTL8367C_PORT1_VLAN_KEEP_MASK_EXT_OFFSET    3\n#define    RTL8367C_PORT1_VLAN_KEEP_MASK_EXT_MASK    0x38\n#define    RTL8367C_PORT0_VLAN_KEEP_MASK_EXT_OFFSET    0\n#define    RTL8367C_PORT0_VLAN_KEEP_MASK_EXT_MASK    0x7\n\n#define    RTL8367C_REG_VLAN_EGRESS_KEEP_CTRL1_EXT    0x08d9\n#define    RTL8367C_PORT3_VLAN_KEEP_MASK_EXT_OFFSET    3\n#define    RTL8367C_PORT3_VLAN_KEEP_MASK_EXT_MASK    0x38\n#define    RTL8367C_PORT2_VLAN_KEEP_MASK_EXT_OFFSET    0\n#define    RTL8367C_PORT2_VLAN_KEEP_MASK_EXT_MASK    0x7\n\n#define    RTL8367C_REG_VLAN_EGRESS_KEEP_CTRL2_EXT    0x08da\n#define    RTL8367C_PORT5_VLAN_KEEP_MASK_EXT_OFFSET    3\n#define    RTL8367C_PORT5_VLAN_KEEP_MASK_EXT_MASK    0x38\n#define    RTL8367C_PORT4_VLAN_KEEP_MASK_EXT_OFFSET    0\n#define    RTL8367C_PORT4_VLAN_KEEP_MASK_EXT_MASK    0x7\n\n#define    RTL8367C_REG_VLAN_EGRESS_KEEP_CTRL3_EXT    0x08db\n#define    RTL8367C_PORT7_VLAN_KEEP_MASK_EXT_OFFSET    3\n#define    RTL8367C_PORT7_VLAN_KEEP_MASK_EXT_MASK    0x38\n#define    RTL8367C_PORT6_VLAN_KEEP_MASK_EXT_OFFSET    0\n#define    RTL8367C_PORT6_VLAN_KEEP_MASK_EXT_MASK    0x7\n\n#define    RTL8367C_REG_VLAN_EGRESS_KEEP_CTRL4_EXT    0x08dc\n#define    RTL8367C_PORT9_VLAN_KEEP_MASK_EXT_OFFSET    3\n#define    RTL8367C_PORT9_VLAN_KEEP_MASK_EXT_MASK    0x38\n#define    RTL8367C_PORT8_VLAN_KEEP_MASK_EXT_OFFSET    0\n#define    RTL8367C_PORT8_VLAN_KEEP_MASK_EXT_MASK    0x7\n\n#define    RTL8367C_REG_VLAN_EGRESS_KEEP_CTRL5_EXT    0x08dd\n#define    RTL8367C_VLAN_EGRESS_KEEP_CTRL5_EXT_OFFSET    0\n#define    RTL8367C_VLAN_EGRESS_KEEP_CTRL5_EXT_MASK    0x7\n\n#define    RTL8367C_REG_VLAN_EGRESS_TRANS_CTRL10    0x08de\n#define    RTL8367C_VLAN_EGRESS_TRANS_CTRL10_OFFSET    0\n#define    RTL8367C_VLAN_EGRESS_TRANS_CTRL10_MASK    0x7FF\n\n#define    RTL8367C_REG_FPGA_VER_CEN    0x08e0\n\n#define    RTL8367C_REG_FPGA_TIME_CEN    0x08e1\n\n#define    RTL8367C_REG_FPGA_DATE_CEN    0x08e2\n\n#define    RTL8367C_REG_QOS_PORT_QUEUE_NUMBER_CTRL0    0x0900\n#define    RTL8367C_PORT3_NUMBER_OFFSET    12\n#define    RTL8367C_PORT3_NUMBER_MASK    0x7000\n#define    RTL8367C_PORT2_NUMBER_OFFSET    8\n#define    RTL8367C_PORT2_NUMBER_MASK    0x700\n#define    RTL8367C_PORT1_NUMBER_OFFSET    4\n#define    RTL8367C_PORT1_NUMBER_MASK    0x70\n#define    RTL8367C_PORT0_NUMBER_OFFSET    0\n#define    RTL8367C_PORT0_NUMBER_MASK    0x7\n\n#define    RTL8367C_REG_QOS_PORT_QUEUE_NUMBER_CTRL1    0x0901\n#define    RTL8367C_PORT7_NUMBER_OFFSET    12\n#define    RTL8367C_PORT7_NUMBER_MASK    0x7000\n#define    RTL8367C_PORT6_NUMBER_OFFSET    8\n#define    RTL8367C_PORT6_NUMBER_MASK    0x700\n#define    RTL8367C_PORT5_NUMBER_OFFSET    4\n#define    RTL8367C_PORT5_NUMBER_MASK    0x70\n#define    RTL8367C_PORT4_NUMBER_OFFSET    0\n#define    RTL8367C_PORT4_NUMBER_MASK    0x7\n\n#define    RTL8367C_REG_QOS_PORT_QUEUE_NUMBER_CTRL2    0x0902\n#define    RTL8367C_PORT10_NUMBER_OFFSET    8\n#define    RTL8367C_PORT10_NUMBER_MASK    0x700\n#define    RTL8367C_PORT9_NUMBER_OFFSET    4\n#define    RTL8367C_PORT9_NUMBER_MASK    0x70\n#define    RTL8367C_PORT8_NUMBER_OFFSET    0\n#define    RTL8367C_PORT8_NUMBER_MASK    0x7\n\n#define    RTL8367C_REG_QOS_1Q_PRIORITY_TO_QID_CTRL0    0x0904\n#define    RTL8367C_QOS_1Q_PRIORITY_TO_QID_CTRL0_PRIORITY3_TO_QID_OFFSET    12\n#define    RTL8367C_QOS_1Q_PRIORITY_TO_QID_CTRL0_PRIORITY3_TO_QID_MASK    0x7000\n#define    RTL8367C_QOS_1Q_PRIORITY_TO_QID_CTRL0_PRIORITY2_TO_QID_OFFSET    8\n#define    RTL8367C_QOS_1Q_PRIORITY_TO_QID_CTRL0_PRIORITY2_TO_QID_MASK    0x700\n#define    RTL8367C_QOS_1Q_PRIORITY_TO_QID_CTRL0_PRIORITY1_TO_QID_OFFSET    4\n#define    RTL8367C_QOS_1Q_PRIORITY_TO_QID_CTRL0_PRIORITY1_TO_QID_MASK    0x70\n#define    RTL8367C_QOS_1Q_PRIORITY_TO_QID_CTRL0_PRIORITY0_TO_QID_OFFSET    0\n#define    RTL8367C_QOS_1Q_PRIORITY_TO_QID_CTRL0_PRIORITY0_TO_QID_MASK    0x7\n\n#define    RTL8367C_REG_QOS_1Q_PRIORITY_TO_QID_CTRL1    0x0905\n#define    RTL8367C_QOS_1Q_PRIORITY_TO_QID_CTRL1_PRIORITY7_TO_QID_OFFSET    12\n#define    RTL8367C_QOS_1Q_PRIORITY_TO_QID_CTRL1_PRIORITY7_TO_QID_MASK    0x7000\n#define    RTL8367C_QOS_1Q_PRIORITY_TO_QID_CTRL1_PRIORITY6_TO_QID_OFFSET    8\n#define    RTL8367C_QOS_1Q_PRIORITY_TO_QID_CTRL1_PRIORITY6_TO_QID_MASK    0x700\n#define    RTL8367C_QOS_1Q_PRIORITY_TO_QID_CTRL1_PRIORITY5_TO_QID_OFFSET    4\n#define    RTL8367C_QOS_1Q_PRIORITY_TO_QID_CTRL1_PRIORITY5_TO_QID_MASK    0x70\n#define    RTL8367C_QOS_1Q_PRIORITY_TO_QID_CTRL1_PRIORITY4_TO_QID_OFFSET    0\n#define    RTL8367C_QOS_1Q_PRIORITY_TO_QID_CTRL1_PRIORITY4_TO_QID_MASK    0x7\n\n#define    RTL8367C_REG_QOS_2Q_PRIORITY_TO_QID_CTRL0    0x0906\n#define    RTL8367C_QOS_2Q_PRIORITY_TO_QID_CTRL0_PRIORITY3_TO_QID_OFFSET    12\n#define    RTL8367C_QOS_2Q_PRIORITY_TO_QID_CTRL0_PRIORITY3_TO_QID_MASK    0x7000\n#define    RTL8367C_QOS_2Q_PRIORITY_TO_QID_CTRL0_PRIORITY2_TO_QID_OFFSET    8\n#define    RTL8367C_QOS_2Q_PRIORITY_TO_QID_CTRL0_PRIORITY2_TO_QID_MASK    0x700\n#define    RTL8367C_QOS_2Q_PRIORITY_TO_QID_CTRL0_PRIORITY1_TO_QID_OFFSET    4\n#define    RTL8367C_QOS_2Q_PRIORITY_TO_QID_CTRL0_PRIORITY1_TO_QID_MASK    0x70\n#define    RTL8367C_QOS_2Q_PRIORITY_TO_QID_CTRL0_PRIORITY0_TO_QID_OFFSET    0\n#define    RTL8367C_QOS_2Q_PRIORITY_TO_QID_CTRL0_PRIORITY0_TO_QID_MASK    0x7\n\n#define    RTL8367C_REG_QOS_2Q_PRIORITY_TO_QID_CTRL1    0x0907\n#define    RTL8367C_QOS_2Q_PRIORITY_TO_QID_CTRL1_PRIORITY7_TO_QID_OFFSET    12\n#define    RTL8367C_QOS_2Q_PRIORITY_TO_QID_CTRL1_PRIORITY7_TO_QID_MASK    0x7000\n#define    RTL8367C_QOS_2Q_PRIORITY_TO_QID_CTRL1_PRIORITY6_TO_QID_OFFSET    8\n#define    RTL8367C_QOS_2Q_PRIORITY_TO_QID_CTRL1_PRIORITY6_TO_QID_MASK    0x700\n#define    RTL8367C_QOS_2Q_PRIORITY_TO_QID_CTRL1_PRIORITY5_TO_QID_OFFSET    4\n#define    RTL8367C_QOS_2Q_PRIORITY_TO_QID_CTRL1_PRIORITY5_TO_QID_MASK    0x70\n#define    RTL8367C_QOS_2Q_PRIORITY_TO_QID_CTRL1_PRIORITY4_TO_QID_OFFSET    0\n#define    RTL8367C_QOS_2Q_PRIORITY_TO_QID_CTRL1_PRIORITY4_TO_QID_MASK    0x7\n\n#define    RTL8367C_REG_QOS_3Q_PRIORITY_TO_QID_CTRL0    0x0908\n#define    RTL8367C_QOS_3Q_PRIORITY_TO_QID_CTRL0_PRIORITY3_TO_QID_OFFSET    12\n#define    RTL8367C_QOS_3Q_PRIORITY_TO_QID_CTRL0_PRIORITY3_TO_QID_MASK    0x7000\n#define    RTL8367C_QOS_3Q_PRIORITY_TO_QID_CTRL0_PRIORITY2_TO_QID_OFFSET    8\n#define    RTL8367C_QOS_3Q_PRIORITY_TO_QID_CTRL0_PRIORITY2_TO_QID_MASK    0x700\n#define    RTL8367C_QOS_3Q_PRIORITY_TO_QID_CTRL0_PRIORITY1_TO_QID_OFFSET    4\n#define    RTL8367C_QOS_3Q_PRIORITY_TO_QID_CTRL0_PRIORITY1_TO_QID_MASK    0x70\n#define    RTL8367C_QOS_3Q_PRIORITY_TO_QID_CTRL0_PRIORITY0_TO_QID_OFFSET    0\n#define    RTL8367C_QOS_3Q_PRIORITY_TO_QID_CTRL0_PRIORITY0_TO_QID_MASK    0x7\n\n#define    RTL8367C_REG_QOS_3Q_PRIORITY_TO_QID_CTRL1    0x0909\n#define    RTL8367C_QOS_3Q_PRIORITY_TO_QID_CTRL1_PRIORITY7_TO_QID_OFFSET    12\n#define    RTL8367C_QOS_3Q_PRIORITY_TO_QID_CTRL1_PRIORITY7_TO_QID_MASK    0x7000\n#define    RTL8367C_QOS_3Q_PRIORITY_TO_QID_CTRL1_PRIORITY6_TO_QID_OFFSET    8\n#define    RTL8367C_QOS_3Q_PRIORITY_TO_QID_CTRL1_PRIORITY6_TO_QID_MASK    0x700\n#define    RTL8367C_QOS_3Q_PRIORITY_TO_QID_CTRL1_PRIORITY5_TO_QID_OFFSET    4\n#define    RTL8367C_QOS_3Q_PRIORITY_TO_QID_CTRL1_PRIORITY5_TO_QID_MASK    0x70\n#define    RTL8367C_QOS_3Q_PRIORITY_TO_QID_CTRL1_PRIORITY4_TO_QID_OFFSET    0\n#define    RTL8367C_QOS_3Q_PRIORITY_TO_QID_CTRL1_PRIORITY4_TO_QID_MASK    0x7\n\n#define    RTL8367C_REG_QOS_4Q_PRIORITY_TO_QID_CTRL0    0x090a\n#define    RTL8367C_QOS_4Q_PRIORITY_TO_QID_CTRL0_PRIORITY3_TO_QID_OFFSET    12\n#define    RTL8367C_QOS_4Q_PRIORITY_TO_QID_CTRL0_PRIORITY3_TO_QID_MASK    0x7000\n#define    RTL8367C_QOS_4Q_PRIORITY_TO_QID_CTRL0_PRIORITY2_TO_QID_OFFSET    8\n#define    RTL8367C_QOS_4Q_PRIORITY_TO_QID_CTRL0_PRIORITY2_TO_QID_MASK    0x700\n#define    RTL8367C_QOS_4Q_PRIORITY_TO_QID_CTRL0_PRIORITY1_TO_QID_OFFSET    4\n#define    RTL8367C_QOS_4Q_PRIORITY_TO_QID_CTRL0_PRIORITY1_TO_QID_MASK    0x70\n#define    RTL8367C_QOS_4Q_PRIORITY_TO_QID_CTRL0_PRIORITY0_TO_QID_OFFSET    0\n#define    RTL8367C_QOS_4Q_PRIORITY_TO_QID_CTRL0_PRIORITY0_TO_QID_MASK    0x7\n\n#define    RTL8367C_REG_QOS_4Q_PRIORITY_TO_QID_CTRL1    0x090b\n#define    RTL8367C_QOS_4Q_PRIORITY_TO_QID_CTRL1_PRIORITY7_TO_QID_OFFSET    12\n#define    RTL8367C_QOS_4Q_PRIORITY_TO_QID_CTRL1_PRIORITY7_TO_QID_MASK    0x7000\n#define    RTL8367C_QOS_4Q_PRIORITY_TO_QID_CTRL1_PRIORITY6_TO_QID_OFFSET    8\n#define    RTL8367C_QOS_4Q_PRIORITY_TO_QID_CTRL1_PRIORITY6_TO_QID_MASK    0x700\n#define    RTL8367C_QOS_4Q_PRIORITY_TO_QID_CTRL1_PRIORITY5_TO_QID_OFFSET    4\n#define    RTL8367C_QOS_4Q_PRIORITY_TO_QID_CTRL1_PRIORITY5_TO_QID_MASK    0x70\n#define    RTL8367C_QOS_4Q_PRIORITY_TO_QID_CTRL1_PRIORITY4_TO_QID_OFFSET    0\n#define    RTL8367C_QOS_4Q_PRIORITY_TO_QID_CTRL1_PRIORITY4_TO_QID_MASK    0x7\n\n#define    RTL8367C_REG_QOS_5Q_PRIORITY_TO_QID_CTRL0    0x090c\n#define    RTL8367C_QOS_5Q_PRIORITY_TO_QID_CTRL0_PRIORITY3_TO_QID_OFFSET    12\n#define    RTL8367C_QOS_5Q_PRIORITY_TO_QID_CTRL0_PRIORITY3_TO_QID_MASK    0x7000\n#define    RTL8367C_QOS_5Q_PRIORITY_TO_QID_CTRL0_PRIORITY2_TO_QID_OFFSET    8\n#define    RTL8367C_QOS_5Q_PRIORITY_TO_QID_CTRL0_PRIORITY2_TO_QID_MASK    0x700\n#define    RTL8367C_QOS_5Q_PRIORITY_TO_QID_CTRL0_PRIORITY1_TO_QID_OFFSET    4\n#define    RTL8367C_QOS_5Q_PRIORITY_TO_QID_CTRL0_PRIORITY1_TO_QID_MASK    0x70\n#define    RTL8367C_QOS_5Q_PRIORITY_TO_QID_CTRL0_PRIORITY0_TO_QID_OFFSET    0\n#define    RTL8367C_QOS_5Q_PRIORITY_TO_QID_CTRL0_PRIORITY0_TO_QID_MASK    0x7\n\n#define    RTL8367C_REG_QOS_5Q_PRIORITY_TO_QID_CTRL1    0x090d\n#define    RTL8367C_QOS_5Q_PRIORITY_TO_QID_CTRL1_PRIORITY7_TO_QID_OFFSET    12\n#define    RTL8367C_QOS_5Q_PRIORITY_TO_QID_CTRL1_PRIORITY7_TO_QID_MASK    0x7000\n#define    RTL8367C_QOS_5Q_PRIORITY_TO_QID_CTRL1_PRIORITY6_TO_QID_OFFSET    8\n#define    RTL8367C_QOS_5Q_PRIORITY_TO_QID_CTRL1_PRIORITY6_TO_QID_MASK    0x700\n#define    RTL8367C_QOS_5Q_PRIORITY_TO_QID_CTRL1_PRIORITY5_TO_QID_OFFSET    4\n#define    RTL8367C_QOS_5Q_PRIORITY_TO_QID_CTRL1_PRIORITY5_TO_QID_MASK    0x70\n#define    RTL8367C_QOS_5Q_PRIORITY_TO_QID_CTRL1_PRIORITY4_TO_QID_OFFSET    0\n#define    RTL8367C_QOS_5Q_PRIORITY_TO_QID_CTRL1_PRIORITY4_TO_QID_MASK    0x7\n\n#define    RTL8367C_REG_QOS_6Q_PRIORITY_TO_QID_CTRL0    0x090e\n#define    RTL8367C_QOS_6Q_PRIORITY_TO_QID_CTRL0_PRIORITY3_TO_QID_OFFSET    12\n#define    RTL8367C_QOS_6Q_PRIORITY_TO_QID_CTRL0_PRIORITY3_TO_QID_MASK    0x7000\n#define    RTL8367C_QOS_6Q_PRIORITY_TO_QID_CTRL0_PRIORITY2_TO_QID_OFFSET    8\n#define    RTL8367C_QOS_6Q_PRIORITY_TO_QID_CTRL0_PRIORITY2_TO_QID_MASK    0x700\n#define    RTL8367C_QOS_6Q_PRIORITY_TO_QID_CTRL0_PRIORITY1_TO_QID_OFFSET    4\n#define    RTL8367C_QOS_6Q_PRIORITY_TO_QID_CTRL0_PRIORITY1_TO_QID_MASK    0x70\n#define    RTL8367C_QOS_6Q_PRIORITY_TO_QID_CTRL0_PRIORITY0_TO_QID_OFFSET    0\n#define    RTL8367C_QOS_6Q_PRIORITY_TO_QID_CTRL0_PRIORITY0_TO_QID_MASK    0x7\n\n#define    RTL8367C_REG_QOS_6Q_PRIORITY_TO_QID_CTRL1    0x090f\n#define    RTL8367C_QOS_6Q_PRIORITY_TO_QID_CTRL1_PRIORITY7_TO_QID_OFFSET    12\n#define    RTL8367C_QOS_6Q_PRIORITY_TO_QID_CTRL1_PRIORITY7_TO_QID_MASK    0x7000\n#define    RTL8367C_QOS_6Q_PRIORITY_TO_QID_CTRL1_PRIORITY6_TO_QID_OFFSET    8\n#define    RTL8367C_QOS_6Q_PRIORITY_TO_QID_CTRL1_PRIORITY6_TO_QID_MASK    0x700\n#define    RTL8367C_QOS_6Q_PRIORITY_TO_QID_CTRL1_PRIORITY5_TO_QID_OFFSET    4\n#define    RTL8367C_QOS_6Q_PRIORITY_TO_QID_CTRL1_PRIORITY5_TO_QID_MASK    0x70\n#define    RTL8367C_QOS_6Q_PRIORITY_TO_QID_CTRL1_PRIORITY4_TO_QID_OFFSET    0\n#define    RTL8367C_QOS_6Q_PRIORITY_TO_QID_CTRL1_PRIORITY4_TO_QID_MASK    0x7\n\n#define    RTL8367C_REG_QOS_7Q_PRIORITY_TO_QID_CTRL0    0x0910\n#define    RTL8367C_QOS_7Q_PRIORITY_TO_QID_CTRL0_PRIORITY3_TO_QID_OFFSET    12\n#define    RTL8367C_QOS_7Q_PRIORITY_TO_QID_CTRL0_PRIORITY3_TO_QID_MASK    0x7000\n#define    RTL8367C_QOS_7Q_PRIORITY_TO_QID_CTRL0_PRIORITY2_TO_QID_OFFSET    8\n#define    RTL8367C_QOS_7Q_PRIORITY_TO_QID_CTRL0_PRIORITY2_TO_QID_MASK    0x700\n#define    RTL8367C_QOS_7Q_PRIORITY_TO_QID_CTRL0_PRIORITY1_TO_QID_OFFSET    4\n#define    RTL8367C_QOS_7Q_PRIORITY_TO_QID_CTRL0_PRIORITY1_TO_QID_MASK    0x70\n#define    RTL8367C_QOS_7Q_PRIORITY_TO_QID_CTRL0_PRIORITY0_TO_QID_OFFSET    0\n#define    RTL8367C_QOS_7Q_PRIORITY_TO_QID_CTRL0_PRIORITY0_TO_QID_MASK    0x7\n\n#define    RTL8367C_REG_QOS_7Q_PRIORITY_TO_QID_CTRL1    0x0911\n#define    RTL8367C_QOS_7Q_PRIORITY_TO_QID_CTRL1_PRIORITY7_TO_QID_OFFSET    12\n#define    RTL8367C_QOS_7Q_PRIORITY_TO_QID_CTRL1_PRIORITY7_TO_QID_MASK    0x7000\n#define    RTL8367C_QOS_7Q_PRIORITY_TO_QID_CTRL1_PRIORITY6_TO_QID_OFFSET    8\n#define    RTL8367C_QOS_7Q_PRIORITY_TO_QID_CTRL1_PRIORITY6_TO_QID_MASK    0x700\n#define    RTL8367C_QOS_7Q_PRIORITY_TO_QID_CTRL1_PRIORITY5_TO_QID_OFFSET    4\n#define    RTL8367C_QOS_7Q_PRIORITY_TO_QID_CTRL1_PRIORITY5_TO_QID_MASK    0x70\n#define    RTL8367C_QOS_7Q_PRIORITY_TO_QID_CTRL1_PRIORITY4_TO_QID_OFFSET    0\n#define    RTL8367C_QOS_7Q_PRIORITY_TO_QID_CTRL1_PRIORITY4_TO_QID_MASK    0x7\n\n#define    RTL8367C_REG_QOS_8Q_PRIORITY_TO_QID_CTRL0    0x0912\n#define    RTL8367C_QOS_8Q_PRIORITY_TO_QID_CTRL0_PRIORITY3_TO_QID_OFFSET    12\n#define    RTL8367C_QOS_8Q_PRIORITY_TO_QID_CTRL0_PRIORITY3_TO_QID_MASK    0x7000\n#define    RTL8367C_QOS_8Q_PRIORITY_TO_QID_CTRL0_PRIORITY2_TO_QID_OFFSET    8\n#define    RTL8367C_QOS_8Q_PRIORITY_TO_QID_CTRL0_PRIORITY2_TO_QID_MASK    0x700\n#define    RTL8367C_QOS_8Q_PRIORITY_TO_QID_CTRL0_PRIORITY1_TO_QID_OFFSET    4\n#define    RTL8367C_QOS_8Q_PRIORITY_TO_QID_CTRL0_PRIORITY1_TO_QID_MASK    0x70\n#define    RTL8367C_QOS_8Q_PRIORITY_TO_QID_CTRL0_PRIORITY0_TO_QID_OFFSET    0\n#define    RTL8367C_QOS_8Q_PRIORITY_TO_QID_CTRL0_PRIORITY0_TO_QID_MASK    0x7\n\n#define    RTL8367C_REG_QOS_8Q_PRIORITY_TO_QID_CTRL1    0x0913\n#define    RTL8367C_QOS_8Q_PRIORITY_TO_QID_CTRL1_PRIORITY7_TO_QID_OFFSET    12\n#define    RTL8367C_QOS_8Q_PRIORITY_TO_QID_CTRL1_PRIORITY7_TO_QID_MASK    0x7000\n#define    RTL8367C_QOS_8Q_PRIORITY_TO_QID_CTRL1_PRIORITY6_TO_QID_OFFSET    8\n#define    RTL8367C_QOS_8Q_PRIORITY_TO_QID_CTRL1_PRIORITY6_TO_QID_MASK    0x700\n#define    RTL8367C_QOS_8Q_PRIORITY_TO_QID_CTRL1_PRIORITY5_TO_QID_OFFSET    4\n#define    RTL8367C_QOS_8Q_PRIORITY_TO_QID_CTRL1_PRIORITY5_TO_QID_MASK    0x70\n#define    RTL8367C_QOS_8Q_PRIORITY_TO_QID_CTRL1_PRIORITY4_TO_QID_OFFSET    0\n#define    RTL8367C_QOS_8Q_PRIORITY_TO_QID_CTRL1_PRIORITY4_TO_QID_MASK    0x7\n\n#define    RTL8367C_REG_HIGHPRI_INDICATOR    0x0915\n#define    RTL8367C_PORT10_INDICATOR_OFFSET    10\n#define    RTL8367C_PORT10_INDICATOR_MASK    0x400\n#define    RTL8367C_PORT9_INDICATOR_OFFSET    9\n#define    RTL8367C_PORT9_INDICATOR_MASK    0x200\n#define    RTL8367C_PORT8_INDICATOR_OFFSET    8\n#define    RTL8367C_PORT8_INDICATOR_MASK    0x100\n#define    RTL8367C_PORT7_INDICATOR_OFFSET    7\n#define    RTL8367C_PORT7_INDICATOR_MASK    0x80\n#define    RTL8367C_PORT6_INDICATOR_OFFSET    6\n#define    RTL8367C_PORT6_INDICATOR_MASK    0x40\n#define    RTL8367C_PORT5_INDICATOR_OFFSET    5\n#define    RTL8367C_PORT5_INDICATOR_MASK    0x20\n#define    RTL8367C_PORT4_INDICATOR_OFFSET    4\n#define    RTL8367C_PORT4_INDICATOR_MASK    0x10\n#define    RTL8367C_PORT3_INDICATOR_OFFSET    3\n#define    RTL8367C_PORT3_INDICATOR_MASK    0x8\n#define    RTL8367C_PORT2_INDICATOR_OFFSET    2\n#define    RTL8367C_PORT2_INDICATOR_MASK    0x4\n#define    RTL8367C_PORT1_INDICATOR_OFFSET    1\n#define    RTL8367C_PORT1_INDICATOR_MASK    0x2\n#define    RTL8367C_PORT0_INDICATOR_OFFSET    0\n#define    RTL8367C_PORT0_INDICATOR_MASK    0x1\n\n#define    RTL8367C_REG_HIGHPRI_CFG    0x0916\n#define    RTL8367C_HIGHPRI_CFG_OFFSET    0\n#define    RTL8367C_HIGHPRI_CFG_MASK    0xFF\n\n#define    RTL8367C_REG_PORT_DEBUG_INFO_CTRL0    0x0917\n#define    RTL8367C_PORT1_DEBUG_INFO_OFFSET    8\n#define    RTL8367C_PORT1_DEBUG_INFO_MASK    0xFF00\n#define    RTL8367C_PORT0_DEBUG_INFO_OFFSET    0\n#define    RTL8367C_PORT0_DEBUG_INFO_MASK    0xFF\n\n#define    RTL8367C_REG_PORT_DEBUG_INFO_CTRL1    0x0918\n#define    RTL8367C_PORT3_DEBUG_INFO_OFFSET    8\n#define    RTL8367C_PORT3_DEBUG_INFO_MASK    0xFF00\n#define    RTL8367C_PORT2_DEBUG_INFO_OFFSET    0\n#define    RTL8367C_PORT2_DEBUG_INFO_MASK    0xFF\n\n#define    RTL8367C_REG_PORT_DEBUG_INFO_CTRL2    0x0919\n#define    RTL8367C_PORT5_DEBUG_INFO_OFFSET    8\n#define    RTL8367C_PORT5_DEBUG_INFO_MASK    0xFF00\n#define    RTL8367C_PORT4_DEBUG_INFO_OFFSET    0\n#define    RTL8367C_PORT4_DEBUG_INFO_MASK    0xFF\n\n#define    RTL8367C_REG_PORT_DEBUG_INFO_CTRL3    0x091a\n#define    RTL8367C_PORT7_DEBUG_INFO_OFFSET    8\n#define    RTL8367C_PORT7_DEBUG_INFO_MASK    0xFF00\n#define    RTL8367C_PORT6_DEBUG_INFO_OFFSET    0\n#define    RTL8367C_PORT6_DEBUG_INFO_MASK    0xFF\n\n#define    RTL8367C_REG_PORT_DEBUG_INFO_CTRL4    0x091b\n#define    RTL8367C_PORT9_DEBUG_INFO_OFFSET    8\n#define    RTL8367C_PORT9_DEBUG_INFO_MASK    0xFF00\n#define    RTL8367C_PORT8_DEBUG_INFO_OFFSET    0\n#define    RTL8367C_PORT8_DEBUG_INFO_MASK    0xFF\n\n#define    RTL8367C_REG_PORT_DEBUG_INFO_CTRL5    0x091c\n#define    RTL8367C_PORT10_DEBUG_INFO_OFFSET    0\n#define    RTL8367C_PORT10_DEBUG_INFO_MASK    0xFF\n\n#define    RTL8367C_REG_PORT_DEBUG_INFO_CTRL6    0x091d\n#define    RTL8367C_PORT7_DEBUG_INDICATOR_OFFSET    14\n#define    RTL8367C_PORT7_DEBUG_INDICATOR_MASK    0xC000\n#define    RTL8367C_PORT6_DEBUG_INDICATOR_OFFSET    12\n#define    RTL8367C_PORT6_DEBUG_INDICATOR_MASK    0x3000\n#define    RTL8367C_PORT5_DEBUG_INDICATOR_OFFSET    10\n#define    RTL8367C_PORT5_DEBUG_INDICATOR_MASK    0xC00\n#define    RTL8367C_PORT4_DEBUG_INDICATOR_OFFSET    8\n#define    RTL8367C_PORT4_DEBUG_INDICATOR_MASK    0x300\n#define    RTL8367C_PORT3_DEBUG_INDICATOR_OFFSET    6\n#define    RTL8367C_PORT3_DEBUG_INDICATOR_MASK    0xC0\n#define    RTL8367C_PORT2_DEBUG_INDICATOR_OFFSET    4\n#define    RTL8367C_PORT2_DEBUG_INDICATOR_MASK    0x30\n#define    RTL8367C_PORT1_DEBUG_INDICATOR_OFFSET    2\n#define    RTL8367C_PORT1_DEBUG_INDICATOR_MASK    0xC\n#define    RTL8367C_PORT0_DEBUG_INDICATOR_OFFSET    0\n#define    RTL8367C_PORT0_DEBUG_INDICATOR_MASK    0x3\n\n#define    RTL8367C_REG_PORT_DEBUG_INFO_CTRL7    0x091e\n#define    RTL8367C_PORT10_DEBUG_INDICATOR_OFFSET    4\n#define    RTL8367C_PORT10_DEBUG_INDICATOR_MASK    0x30\n#define    RTL8367C_PORT9_DEBUG_INDICATOR_OFFSET    2\n#define    RTL8367C_PORT9_DEBUG_INDICATOR_MASK    0xC\n#define    RTL8367C_PORT8_DEBUG_INDICATOR_OFFSET    0\n#define    RTL8367C_PORT8_DEBUG_INDICATOR_MASK    0x3\n\n#define    RTL8367C_REG_FLOWCRTL_EGRESS_QUEUE_ENABLE_CTRL0    0x0930\n#define    RTL8367C_PORT1_QUEUE_MASK_OFFSET    8\n#define    RTL8367C_PORT1_QUEUE_MASK_MASK    0xFF00\n#define    RTL8367C_PORT0_QUEUE_MASK_OFFSET    0\n#define    RTL8367C_PORT0_QUEUE_MASK_MASK    0xFF\n\n#define    RTL8367C_REG_FLOWCRTL_EGRESS_QUEUE_ENABLE_CTRL1    0x0931\n#define    RTL8367C_PORT3_QUEUE_MASK_OFFSET    8\n#define    RTL8367C_PORT3_QUEUE_MASK_MASK    0xFF00\n#define    RTL8367C_PORT2_QUEUE_MASK_OFFSET    0\n#define    RTL8367C_PORT2_QUEUE_MASK_MASK    0xFF\n\n#define    RTL8367C_REG_FLOWCRTL_EGRESS_QUEUE_ENABLE_CTRL2    0x0932\n#define    RTL8367C_PORT5_QUEUE_MASK_OFFSET    8\n#define    RTL8367C_PORT5_QUEUE_MASK_MASK    0xFF00\n#define    RTL8367C_PORT4_QUEUE_MASK_OFFSET    0\n#define    RTL8367C_PORT4_QUEUE_MASK_MASK    0xFF\n\n#define    RTL8367C_REG_FLOWCRTL_EGRESS_QUEUE_ENABLE_CTRL3    0x0933\n#define    RTL8367C_PORT7_QUEUE_MASK_OFFSET    8\n#define    RTL8367C_PORT7_QUEUE_MASK_MASK    0xFF00\n#define    RTL8367C_PORT6_QUEUE_MASK_OFFSET    0\n#define    RTL8367C_PORT6_QUEUE_MASK_MASK    0xFF\n\n#define    RTL8367C_REG_FLOWCRTL_EGRESS_QUEUE_ENABLE_CTRL4    0x0934\n#define    RTL8367C_PORT9_QUEUE_MASK_OFFSET    8\n#define    RTL8367C_PORT9_QUEUE_MASK_MASK    0xFF00\n#define    RTL8367C_PORT8_QUEUE_MASK_OFFSET    0\n#define    RTL8367C_PORT8_QUEUE_MASK_MASK    0xFF\n\n#define    RTL8367C_REG_FLOWCRTL_EGRESS_QUEUE_ENABLE_CTRL5    0x0935\n#define    RTL8367C_FLOWCRTL_EGRESS_QUEUE_ENABLE_CTRL5_OFFSET    0\n#define    RTL8367C_FLOWCRTL_EGRESS_QUEUE_ENABLE_CTRL5_MASK    0xFF\n\n#define    RTL8367C_REG_FLOWCRTL_EGRESS_PORT_ENABLE    0x0938\n#define    RTL8367C_FLOWCRTL_EGRESS_PORT_ENABLE_OFFSET    0\n#define    RTL8367C_FLOWCRTL_EGRESS_PORT_ENABLE_MASK    0xFF\n\n#define    RTL8367C_REG_EAV_CTRL    0x0939\n#define    RTL8367C_EAV_TRAP_CPU_OFFSET    1\n#define    RTL8367C_EAV_TRAP_CPU_MASK    0x2\n#define    RTL8367C_EAV_TRAP_8051_OFFSET    0\n#define    RTL8367C_EAV_TRAP_8051_MASK    0x1\n\n#define    RTL8367C_REG_UNTAG_DSCP_PRI_CFG    0x093a\n#define    RTL8367C_UNTAG_DSCP_PRI_CFG_OFFSET    0\n#define    RTL8367C_UNTAG_DSCP_PRI_CFG_MASK    0x1\n\n#define    RTL8367C_REG_VLAN_EGRESS_KEEP_CTRL0    0x093b\n#define    RTL8367C_PORT1_VLAN_KEEP_MASK_OFFSET    8\n#define    RTL8367C_PORT1_VLAN_KEEP_MASK_MASK    0xFF00\n#define    RTL8367C_PORT0_VLAN_KEEP_MASK_OFFSET    0\n#define    RTL8367C_PORT0_VLAN_KEEP_MASK_MASK    0xFF\n\n#define    RTL8367C_REG_VLAN_EGRESS_KEEP_CTRL1    0x093c\n#define    RTL8367C_PORT3_VLAN_KEEP_MASK_OFFSET    8\n#define    RTL8367C_PORT3_VLAN_KEEP_MASK_MASK    0xFF00\n#define    RTL8367C_PORT2_VLAN_KEEP_MASK_OFFSET    0\n#define    RTL8367C_PORT2_VLAN_KEEP_MASK_MASK    0xFF\n\n#define    RTL8367C_REG_VLAN_EGRESS_KEEP_CTRL2    0x093d\n#define    RTL8367C_PORT5_VLAN_KEEP_MASK_OFFSET    8\n#define    RTL8367C_PORT5_VLAN_KEEP_MASK_MASK    0xFF00\n#define    RTL8367C_PORT4_VLAN_KEEP_MASK_OFFSET    0\n#define    RTL8367C_PORT4_VLAN_KEEP_MASK_MASK    0xFF\n\n#define    RTL8367C_REG_VLAN_EGRESS_KEEP_CTRL3    0x093e\n#define    RTL8367C_PORT7_VLAN_KEEP_MASK_OFFSET    8\n#define    RTL8367C_PORT7_VLAN_KEEP_MASK_MASK    0xFF00\n#define    RTL8367C_PORT6_VLAN_KEEP_MASK_OFFSET    0\n#define    RTL8367C_PORT6_VLAN_KEEP_MASK_MASK    0xFF\n\n#define    RTL8367C_REG_VLAN_TRANSPARENT_EN_CFG    0x093f\n#define    RTL8367C_VLAN_TRANSPARENT_EN_CFG_OFFSET    0\n#define    RTL8367C_VLAN_TRANSPARENT_EN_CFG_MASK    0x1\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY0_H    0x0940\n#define    RTL8367C_IPMC_GROUP_ENTRY0_H_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_ENTRY0_H_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY0_L    0x0941\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY1_H    0x0942\n#define    RTL8367C_IPMC_GROUP_ENTRY1_H_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_ENTRY1_H_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY1_L    0x0943\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY2_H    0x0944\n#define    RTL8367C_IPMC_GROUP_ENTRY2_H_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_ENTRY2_H_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY2_L    0x0945\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY3_H    0x0946\n#define    RTL8367C_IPMC_GROUP_ENTRY3_H_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_ENTRY3_H_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY3_L    0x0947\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY4_H    0x0948\n#define    RTL8367C_IPMC_GROUP_ENTRY4_H_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_ENTRY4_H_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY4_L    0x0949\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY5_H    0x094a\n#define    RTL8367C_IPMC_GROUP_ENTRY5_H_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_ENTRY5_H_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY5_L    0x094b\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY6_H    0x094c\n#define    RTL8367C_IPMC_GROUP_ENTRY6_H_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_ENTRY6_H_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY6_L    0x094d\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY7_H    0x094e\n#define    RTL8367C_IPMC_GROUP_ENTRY7_H_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_ENTRY7_H_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY7_L    0x094f\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY8_H    0x0950\n#define    RTL8367C_IPMC_GROUP_ENTRY8_H_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_ENTRY8_H_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY8_L    0x0951\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY9_H    0x0952\n#define    RTL8367C_IPMC_GROUP_ENTRY9_H_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_ENTRY9_H_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY9_L    0x0953\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY10_H    0x0954\n#define    RTL8367C_IPMC_GROUP_ENTRY10_H_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_ENTRY10_H_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY10_L    0x0955\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY11_H    0x0956\n#define    RTL8367C_IPMC_GROUP_ENTRY11_H_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_ENTRY11_H_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY11_L    0x0957\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY12_H    0x0958\n#define    RTL8367C_IPMC_GROUP_ENTRY12_H_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_ENTRY12_H_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY12_L    0x0959\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY13_H    0x095a\n#define    RTL8367C_IPMC_GROUP_ENTRY13_H_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_ENTRY13_H_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY13_L    0x095b\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY14_H    0x095c\n#define    RTL8367C_IPMC_GROUP_ENTRY14_H_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_ENTRY14_H_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY14_L    0x095d\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY15_H    0x095e\n#define    RTL8367C_IPMC_GROUP_ENTRY15_H_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_ENTRY15_H_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY15_L    0x095f\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY16_H    0x0960\n#define    RTL8367C_IPMC_GROUP_ENTRY16_H_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_ENTRY16_H_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY16_L    0x0961\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY17_H    0x0962\n#define    RTL8367C_IPMC_GROUP_ENTRY17_H_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_ENTRY17_H_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY17_L    0x0963\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY18_H    0x0964\n#define    RTL8367C_IPMC_GROUP_ENTRY18_H_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_ENTRY18_H_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY18_L    0x0965\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY19_H    0x0966\n#define    RTL8367C_IPMC_GROUP_ENTRY19_H_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_ENTRY19_H_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY19_L    0x0967\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY20_H    0x0968\n#define    RTL8367C_IPMC_GROUP_ENTRY20_H_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_ENTRY20_H_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY20_L    0x0969\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY21_H    0x096a\n#define    RTL8367C_IPMC_GROUP_ENTRY21_H_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_ENTRY21_H_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY21_L    0x096b\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY22_H    0x096c\n#define    RTL8367C_IPMC_GROUP_ENTRY22_H_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_ENTRY22_H_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY22_L    0x096d\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY23_H    0x096e\n#define    RTL8367C_IPMC_GROUP_ENTRY23_H_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_ENTRY23_H_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY23_L    0x096f\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY24_H    0x0970\n#define    RTL8367C_IPMC_GROUP_ENTRY24_H_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_ENTRY24_H_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY24_L    0x0971\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY25_H    0x0972\n#define    RTL8367C_IPMC_GROUP_ENTRY25_H_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_ENTRY25_H_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY25_L    0x0973\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY26_H    0x0974\n#define    RTL8367C_IPMC_GROUP_ENTRY26_H_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_ENTRY26_H_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY26_L    0x0975\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY27_H    0x0976\n#define    RTL8367C_IPMC_GROUP_ENTRY27_H_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_ENTRY27_H_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY27_L    0x0977\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY28_H    0x0978\n#define    RTL8367C_IPMC_GROUP_ENTRY28_H_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_ENTRY28_H_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY28_L    0x0979\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY29_H    0x097a\n#define    RTL8367C_IPMC_GROUP_ENTRY29_H_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_ENTRY29_H_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY29_L    0x097b\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY30_H    0x097c\n#define    RTL8367C_IPMC_GROUP_ENTRY30_H_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_ENTRY30_H_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY30_L    0x097d\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY31_H    0x097e\n#define    RTL8367C_IPMC_GROUP_ENTRY31_H_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_ENTRY31_H_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY31_L    0x097f\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY32_H    0x0980\n#define    RTL8367C_IPMC_GROUP_ENTRY32_H_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_ENTRY32_H_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY32_L    0x0981\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY33_H    0x0982\n#define    RTL8367C_IPMC_GROUP_ENTRY33_H_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_ENTRY33_H_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY33_L    0x0983\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY34_H    0x0984\n#define    RTL8367C_IPMC_GROUP_ENTRY34_H_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_ENTRY34_H_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY34_L    0x0985\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY35_H    0x0986\n#define    RTL8367C_IPMC_GROUP_ENTRY35_H_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_ENTRY35_H_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY35_L    0x0987\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY36_H    0x0988\n#define    RTL8367C_IPMC_GROUP_ENTRY36_H_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_ENTRY36_H_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY36_L    0x0989\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY37_H    0x098a\n#define    RTL8367C_IPMC_GROUP_ENTRY37_H_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_ENTRY37_H_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY37_L    0x098b\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY38_H    0x098c\n#define    RTL8367C_IPMC_GROUP_ENTRY38_H_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_ENTRY38_H_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY38_L    0x098d\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY39_H    0x098e\n#define    RTL8367C_IPMC_GROUP_ENTRY39_H_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_ENTRY39_H_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY39_L    0x098f\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY40_H    0x0990\n#define    RTL8367C_IPMC_GROUP_ENTRY40_H_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_ENTRY40_H_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY40_L    0x0991\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY41_H    0x0992\n#define    RTL8367C_IPMC_GROUP_ENTRY41_H_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_ENTRY41_H_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY41_L    0x0993\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY42_H    0x0994\n#define    RTL8367C_IPMC_GROUP_ENTRY42_H_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_ENTRY42_H_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY42_L    0x0995\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY43_H    0x0996\n#define    RTL8367C_IPMC_GROUP_ENTRY43_H_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_ENTRY43_H_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY43_L    0x0997\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY44_H    0x0998\n#define    RTL8367C_IPMC_GROUP_ENTRY44_H_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_ENTRY44_H_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY44_L    0x0999\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY45_H    0x099a\n#define    RTL8367C_IPMC_GROUP_ENTRY45_H_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_ENTRY45_H_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY45_L    0x099b\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY46_H    0x099c\n#define    RTL8367C_IPMC_GROUP_ENTRY46_H_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_ENTRY46_H_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY46_L    0x099d\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY47_H    0x099e\n#define    RTL8367C_IPMC_GROUP_ENTRY47_H_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_ENTRY47_H_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY47_L    0x099f\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY48_H    0x09a0\n#define    RTL8367C_IPMC_GROUP_ENTRY48_H_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_ENTRY48_H_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY48_L    0x09a1\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY49_H    0x09a2\n#define    RTL8367C_IPMC_GROUP_ENTRY49_H_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_ENTRY49_H_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY49_L    0x09a3\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY50_H    0x09a4\n#define    RTL8367C_IPMC_GROUP_ENTRY50_H_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_ENTRY50_H_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY50_L    0x09a5\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY51_H    0x09a6\n#define    RTL8367C_IPMC_GROUP_ENTRY51_H_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_ENTRY51_H_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY51_L    0x09a7\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY52_H    0x09a8\n#define    RTL8367C_IPMC_GROUP_ENTRY52_H_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_ENTRY52_H_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY52_L    0x09a9\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY53_H    0x09aa\n#define    RTL8367C_IPMC_GROUP_ENTRY53_H_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_ENTRY53_H_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY53_L    0x09ab\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY54_H    0x09ac\n#define    RTL8367C_IPMC_GROUP_ENTRY54_H_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_ENTRY54_H_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY54_L    0x09ad\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY55_H    0x09ae\n#define    RTL8367C_IPMC_GROUP_ENTRY55_H_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_ENTRY55_H_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY55_L    0x09af\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY56_H    0x09b0\n#define    RTL8367C_IPMC_GROUP_ENTRY56_H_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_ENTRY56_H_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY56_L    0x09b1\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY57_H    0x09b2\n#define    RTL8367C_IPMC_GROUP_ENTRY57_H_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_ENTRY57_H_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY57_L    0x09b3\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY58_H    0x09b4\n#define    RTL8367C_IPMC_GROUP_ENTRY58_H_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_ENTRY58_H_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY58_L    0x09b5\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY59_H    0x09b6\n#define    RTL8367C_IPMC_GROUP_ENTRY59_H_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_ENTRY59_H_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY59_L    0x09b7\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY60_H    0x09b8\n#define    RTL8367C_IPMC_GROUP_ENTRY60_H_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_ENTRY60_H_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY60_L    0x09b9\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY61_H    0x09ba\n#define    RTL8367C_IPMC_GROUP_ENTRY61_H_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_ENTRY61_H_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY61_L    0x09bb\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY62_H    0x09bc\n#define    RTL8367C_IPMC_GROUP_ENTRY62_H_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_ENTRY62_H_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY62_L    0x09bd\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY63_H    0x09be\n#define    RTL8367C_IPMC_GROUP_ENTRY63_H_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_ENTRY63_H_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_ENTRY63_L    0x09bf\n\n#define    RTL8367C_REG_UNKNOWN_UNICAST_DA_PORT_BEHAVE    0x09C0\n#define    RTL8367C_Port7_ACTION_OFFSET    14\n#define    RTL8367C_Port7_ACTION_MASK    0xC000\n#define    RTL8367C_Port6_ACTION_OFFSET    12\n#define    RTL8367C_Port6_ACTION_MASK    0x3000\n#define    RTL8367C_Port5_ACTION_OFFSET    10\n#define    RTL8367C_Port5_ACTION_MASK    0xC00\n#define    RTL8367C_Port4_ACTION_OFFSET    8\n#define    RTL8367C_Port4_ACTION_MASK    0x300\n#define    RTL8367C_Port3_ACTION_OFFSET    6\n#define    RTL8367C_Port3_ACTION_MASK    0xC0\n#define    RTL8367C_Port2_ACTION_OFFSET    4\n#define    RTL8367C_Port2_ACTION_MASK    0x30\n#define    RTL8367C_Port1_ACTION_OFFSET    2\n#define    RTL8367C_Port1_ACTION_MASK    0xC\n#define    RTL8367C_Port0_ACTION_OFFSET    0\n#define    RTL8367C_Port0_ACTION_MASK    0x3\n\n#define    RTL8367C_REG_MIRROR_CTRL3    0x09C1\n#define    RTL8367C_MIRROR_ACL_OVERRIDE_EN_OFFSET    2\n#define    RTL8367C_MIRROR_ACL_OVERRIDE_EN_MASK    0x4\n#define    RTL8367C_MIRROR_TX_OVERRIDE_EN_OFFSET    1\n#define    RTL8367C_MIRROR_TX_OVERRIDE_EN_MASK    0x2\n#define    RTL8367C_MIRROR_RX_OVERRIDE_EN_OFFSET    0\n#define    RTL8367C_MIRROR_RX_OVERRIDE_EN_MASK    0x1\n\n#define    RTL8367C_REG_DPM_DUMMY02    0x09C2\n\n#define    RTL8367C_REG_DPM_DUMMY03    0x09C3\n\n#define    RTL8367C_REG_DPM_DUMMY04    0x09C4\n\n#define    RTL8367C_REG_DPM_DUMMY05    0x09C5\n\n#define    RTL8367C_REG_DPM_DUMMY06    0x09C6\n\n#define    RTL8367C_REG_DPM_DUMMY07    0x09C7\n\n#define    RTL8367C_REG_DPM_DUMMY08    0x09C8\n\n#define    RTL8367C_REG_DPM_DUMMY09    0x09C9\n\n#define    RTL8367C_REG_DPM_DUMMY10    0x09CA\n\n#define    RTL8367C_REG_DPM_DUMMY11    0x09CB\n\n#define    RTL8367C_REG_DPM_DUMMY12    0x09CC\n\n#define    RTL8367C_REG_DPM_DUMMY13    0x09CD\n\n#define    RTL8367C_REG_DPM_DUMMY14    0x09CE\n\n#define    RTL8367C_REG_DPM_DUMMY15    0x09CF\n\n#define    RTL8367C_REG_VLAN_EGRESS_TRANS_CTRL0    0x09D0\n#define    RTL8367C_VLAN_EGRESS_TRANS_CTRL0_OFFSET    0\n#define    RTL8367C_VLAN_EGRESS_TRANS_CTRL0_MASK    0x7FF\n\n#define    RTL8367C_REG_VLAN_EGRESS_TRANS_CTRL1    0x09D1\n#define    RTL8367C_VLAN_EGRESS_TRANS_CTRL1_OFFSET    0\n#define    RTL8367C_VLAN_EGRESS_TRANS_CTRL1_MASK    0x7FF\n\n#define    RTL8367C_REG_VLAN_EGRESS_TRANS_CTRL2    0x09D2\n#define    RTL8367C_VLAN_EGRESS_TRANS_CTRL2_OFFSET    0\n#define    RTL8367C_VLAN_EGRESS_TRANS_CTRL2_MASK    0x7FF\n\n#define    RTL8367C_REG_VLAN_EGRESS_TRANS_CTRL3    0x09D3\n#define    RTL8367C_VLAN_EGRESS_TRANS_CTRL3_OFFSET    0\n#define    RTL8367C_VLAN_EGRESS_TRANS_CTRL3_MASK    0x7FF\n\n#define    RTL8367C_REG_VLAN_EGRESS_TRANS_CTRL4    0x09D4\n#define    RTL8367C_VLAN_EGRESS_TRANS_CTRL4_OFFSET    0\n#define    RTL8367C_VLAN_EGRESS_TRANS_CTRL4_MASK    0x7FF\n\n#define    RTL8367C_REG_VLAN_EGRESS_TRANS_CTRL5    0x09D5\n#define    RTL8367C_VLAN_EGRESS_TRANS_CTRL5_OFFSET    0\n#define    RTL8367C_VLAN_EGRESS_TRANS_CTRL5_MASK    0x7FF\n\n#define    RTL8367C_REG_VLAN_EGRESS_TRANS_CTRL6    0x09D6\n#define    RTL8367C_VLAN_EGRESS_TRANS_CTRL6_OFFSET    0\n#define    RTL8367C_VLAN_EGRESS_TRANS_CTRL6_MASK    0x7FF\n\n#define    RTL8367C_REG_VLAN_EGRESS_TRANS_CTRL7    0x09D7\n#define    RTL8367C_VLAN_EGRESS_TRANS_CTRL7_OFFSET    0\n#define    RTL8367C_VLAN_EGRESS_TRANS_CTRL7_MASK    0x7FF\n\n#define    RTL8367C_REG_VLAN_EGRESS_TRANS_CTRL8    0x09D8\n#define    RTL8367C_VLAN_EGRESS_TRANS_CTRL8_OFFSET    0\n#define    RTL8367C_VLAN_EGRESS_TRANS_CTRL8_MASK    0x7FF\n\n#define    RTL8367C_REG_VLAN_EGRESS_TRANS_CTRL9    0x09D9\n#define    RTL8367C_VLAN_EGRESS_TRANS_CTRL9_OFFSET    0\n#define    RTL8367C_VLAN_EGRESS_TRANS_CTRL9_MASK    0x7FF\n\n#define    RTL8367C_REG_MIRROR_CTRL2    0x09DA\n#define    RTL8367C_MIRROR_REALKEEP_EN_OFFSET    4\n#define    RTL8367C_MIRROR_REALKEEP_EN_MASK    0x10\n#define    RTL8367C_MIRROR_RX_ISOLATION_LEAKY_OFFSET    3\n#define    RTL8367C_MIRROR_RX_ISOLATION_LEAKY_MASK    0x8\n#define    RTL8367C_MIRROR_TX_ISOLATION_LEAKY_OFFSET    2\n#define    RTL8367C_MIRROR_TX_ISOLATION_LEAKY_MASK    0x4\n#define    RTL8367C_MIRROR_RX_VLAN_LEAKY_OFFSET    1\n#define    RTL8367C_MIRROR_RX_VLAN_LEAKY_MASK    0x2\n#define    RTL8367C_MIRROR_TX_VLAN_LEAKY_OFFSET    0\n#define    RTL8367C_MIRROR_TX_VLAN_LEAKY_MASK    0x1\n\n#define    RTL8367C_REG_OUTPUT_DROP_CFG    0x09DB\n#define    RTL8367C_ENABLE_PMASK_EXT_OFFSET    13\n#define    RTL8367C_ENABLE_PMASK_EXT_MASK    0xE000\n#define    RTL8367C_ENABLE_BC_OFFSET    12\n#define    RTL8367C_ENABLE_BC_MASK    0x1000\n#define    RTL8367C_ENABLE_MC_OFFSET    11\n#define    RTL8367C_ENABLE_MC_MASK    0x800\n#define    RTL8367C_ENABLE_UC_OFFSET    10\n#define    RTL8367C_ENABLE_UC_MASK    0x400\n#define    RTL8367C_ENABLE_PMASK_OFFSET    0\n#define    RTL8367C_ENABLE_PMASK_MASK    0xFF\n\n#define    RTL8367C_REG_UNKNOWN_UNICAST_DA_PORT_BEHAVE_EXT    0x09DC\n#define    RTL8367C_PORT10_ACTION_OFFSET    4\n#define    RTL8367C_PORT10_ACTION_MASK    0x30\n#define    RTL8367C_PORT9_ACTION_OFFSET    2\n#define    RTL8367C_PORT9_ACTION_MASK    0xC\n#define    RTL8367C_PORT8_ACTION_OFFSET    0\n#define    RTL8367C_PORT8_ACTION_MASK    0x3\n\n#define    RTL8367C_REG_RMK_CFG_SEL_CTRL    0x09DF\n#define    RTL8367C_RMK_1Q_CFG_SEL_OFFSET    2\n#define    RTL8367C_RMK_1Q_CFG_SEL_MASK    0x4\n#define    RTL8367C_RMK_DSCP_CFG_SEL_OFFSET    0\n#define    RTL8367C_RMK_DSCP_CFG_SEL_MASK    0x3\n\n#define    RTL8367C_REG_QOS_DSCP_REMARK_DSCP_CTRL0    0x09E0\n#define    RTL8367C_DSCP1_DSCP_OFFSET    8\n#define    RTL8367C_DSCP1_DSCP_MASK    0x3F00\n#define    RTL8367C_DSCP0_DSCP_OFFSET    0\n#define    RTL8367C_DSCP0_DSCP_MASK    0x3F\n\n#define    RTL8367C_REG_QOS_DSCP_REMARK_DSCP_CTRL1    0x09E1\n#define    RTL8367C_DSCP3_DSCP_OFFSET    8\n#define    RTL8367C_DSCP3_DSCP_MASK    0x3F00\n#define    RTL8367C_DSCP2_DSCP_OFFSET    0\n#define    RTL8367C_DSCP2_DSCP_MASK    0x3F\n\n#define    RTL8367C_REG_QOS_DSCP_REMARK_DSCP_CTRL2    0x09E2\n#define    RTL8367C_DSCP5_DSCP_OFFSET    8\n#define    RTL8367C_DSCP5_DSCP_MASK    0x3F00\n#define    RTL8367C_DSCP4_DSCP_OFFSET    0\n#define    RTL8367C_DSCP4_DSCP_MASK    0x3F\n\n#define    RTL8367C_REG_QOS_DSCP_REMARK_DSCP_CTRL3    0x09E3\n#define    RTL8367C_DSCP7_DSCP_OFFSET    8\n#define    RTL8367C_DSCP7_DSCP_MASK    0x3F00\n#define    RTL8367C_DSCP6_DSCP_OFFSET    0\n#define    RTL8367C_DSCP6_DSCP_MASK    0x3F\n\n#define    RTL8367C_REG_QOS_DSCP_REMARK_DSCP_CTRL4    0x09E4\n#define    RTL8367C_DSCP9_DSCP_OFFSET    8\n#define    RTL8367C_DSCP9_DSCP_MASK    0x3F00\n#define    RTL8367C_DSCP8_DSCP_OFFSET    0\n#define    RTL8367C_DSCP8_DSCP_MASK    0x3F\n\n#define    RTL8367C_REG_QOS_DSCP_REMARK_DSCP_CTRL5    0x09E5\n#define    RTL8367C_DSCP11_DSCP_OFFSET    8\n#define    RTL8367C_DSCP11_DSCP_MASK    0x3F00\n#define    RTL8367C_DSCP10_DSCP_OFFSET    0\n#define    RTL8367C_DSCP10_DSCP_MASK    0x3F\n\n#define    RTL8367C_REG_QOS_DSCP_REMARK_DSCP_CTRL6    0x09E6\n#define    RTL8367C_DSCP13_DSCP_OFFSET    8\n#define    RTL8367C_DSCP13_DSCP_MASK    0x3F00\n#define    RTL8367C_DSCP12_DSCP_OFFSET    0\n#define    RTL8367C_DSCP12_DSCP_MASK    0x3F\n\n#define    RTL8367C_REG_QOS_DSCP_REMARK_DSCP_CTRL7    0x09E7\n#define    RTL8367C_DSCP15_DSCP_OFFSET    8\n#define    RTL8367C_DSCP15_DSCP_MASK    0x3F00\n#define    RTL8367C_DSCP14_DSCP_OFFSET    0\n#define    RTL8367C_DSCP14_DSCP_MASK    0x3F\n\n#define    RTL8367C_REG_QOS_DSCP_REMARK_DSCP_CTRL8    0x09E8\n#define    RTL8367C_DSCP17_DSCP_OFFSET    8\n#define    RTL8367C_DSCP17_DSCP_MASK    0x3F00\n#define    RTL8367C_DSCP16_DSCP_OFFSET    0\n#define    RTL8367C_DSCP16_DSCP_MASK    0x3F\n\n#define    RTL8367C_REG_QOS_DSCP_REMARK_DSCP_CTRL9    0x09E9\n#define    RTL8367C_DSCP19_DSCP_OFFSET    8\n#define    RTL8367C_DSCP19_DSCP_MASK    0x3F00\n#define    RTL8367C_DSCP18_DSCP_OFFSET    0\n#define    RTL8367C_DSCP18_DSCP_MASK    0x3F\n\n#define    RTL8367C_REG_QOS_DSCP_REMARK_DSCP_CTRL10    0x09EA\n#define    RTL8367C_DSCP21_DSCP_OFFSET    8\n#define    RTL8367C_DSCP21_DSCP_MASK    0x3F00\n#define    RTL8367C_DSCP20_DSCP_OFFSET    0\n#define    RTL8367C_DSCP20_DSCP_MASK    0x3F\n\n#define    RTL8367C_REG_QOS_DSCP_REMARK_DSCP_CTRL11    0x09EB\n#define    RTL8367C_DSCP23_DSCP_OFFSET    8\n#define    RTL8367C_DSCP23_DSCP_MASK    0x3F00\n#define    RTL8367C_DSCP22_DSCP_OFFSET    0\n#define    RTL8367C_DSCP22_DSCP_MASK    0x3F\n\n#define    RTL8367C_REG_QOS_DSCP_REMARK_DSCP_CTRL12    0x09EC\n#define    RTL8367C_DSCP25_DSCP_OFFSET    8\n#define    RTL8367C_DSCP25_DSCP_MASK    0x3F00\n#define    RTL8367C_DSCP24_DSCP_OFFSET    0\n#define    RTL8367C_DSCP24_DSCP_MASK    0x3F\n\n#define    RTL8367C_REG_QOS_DSCP_REMARK_DSCP_CTRL13    0x09ED\n#define    RTL8367C_DSCP27_DSCP_OFFSET    8\n#define    RTL8367C_DSCP27_DSCP_MASK    0x3F00\n#define    RTL8367C_DSCP26_DSCP_OFFSET    0\n#define    RTL8367C_DSCP26_DSCP_MASK    0x3F\n\n#define    RTL8367C_REG_QOS_DSCP_REMARK_DSCP_CTRL14    0x09EE\n#define    RTL8367C_DSCP29_DSCP_OFFSET    8\n#define    RTL8367C_DSCP29_DSCP_MASK    0x3F00\n#define    RTL8367C_DSCP28_DSCP_OFFSET    0\n#define    RTL8367C_DSCP28_DSCP_MASK    0x3F\n\n#define    RTL8367C_REG_QOS_DSCP_REMARK_DSCP_CTRL15    0x09EF\n#define    RTL8367C_DSCP31_DSCP_OFFSET    8\n#define    RTL8367C_DSCP31_DSCP_MASK    0x3F00\n#define    RTL8367C_DSCP30_DSCP_OFFSET    0\n#define    RTL8367C_DSCP30_DSCP_MASK    0x3F\n\n#define    RTL8367C_REG_QOS_DSCP_REMARK_DSCP_CTRL16    0x09F0\n#define    RTL8367C_DSCP33_DSCP_OFFSET    8\n#define    RTL8367C_DSCP33_DSCP_MASK    0x3F00\n#define    RTL8367C_DSCP32_DSCP_OFFSET    0\n#define    RTL8367C_DSCP32_DSCP_MASK    0x3F\n\n#define    RTL8367C_REG_QOS_DSCP_REMARK_DSCP_CTRL17    0x09F1\n#define    RTL8367C_DSCP35_DSCP_OFFSET    8\n#define    RTL8367C_DSCP35_DSCP_MASK    0x3F00\n#define    RTL8367C_DSCP34_DSCP_OFFSET    0\n#define    RTL8367C_DSCP34_DSCP_MASK    0x3F\n\n#define    RTL8367C_REG_QOS_DSCP_REMARK_DSCP_CTRL18    0x09F2\n#define    RTL8367C_DSCP37_DSCP_OFFSET    8\n#define    RTL8367C_DSCP37_DSCP_MASK    0x3F00\n#define    RTL8367C_DSCP36_DSCP_OFFSET    0\n#define    RTL8367C_DSCP36_DSCP_MASK    0x3F\n\n#define    RTL8367C_REG_QOS_DSCP_REMARK_DSCP_CTRL19    0x09F3\n#define    RTL8367C_DSCP39_DSCP_OFFSET    8\n#define    RTL8367C_DSCP39_DSCP_MASK    0x3F00\n#define    RTL8367C_DSCP38_DSCP_OFFSET    0\n#define    RTL8367C_DSCP38_DSCP_MASK    0x3F\n\n#define    RTL8367C_REG_QOS_DSCP_REMARK_DSCP_CTRL20    0x09F4\n#define    RTL8367C_DSCP41_DSCP_OFFSET    8\n#define    RTL8367C_DSCP41_DSCP_MASK    0x3F00\n#define    RTL8367C_DSCP40_DSCP_OFFSET    0\n#define    RTL8367C_DSCP40_DSCP_MASK    0x3F\n\n#define    RTL8367C_REG_QOS_DSCP_REMARK_DSCP_CTRL21    0x09F5\n#define    RTL8367C_DSCP43_DSCP_OFFSET    8\n#define    RTL8367C_DSCP43_DSCP_MASK    0x3F00\n#define    RTL8367C_DSCP42_DSCP_OFFSET    0\n#define    RTL8367C_DSCP42_DSCP_MASK    0x3F\n\n#define    RTL8367C_REG_QOS_DSCP_REMARK_DSCP_CTRL22    0x09F6\n#define    RTL8367C_DSCP45_DSCP_OFFSET    8\n#define    RTL8367C_DSCP45_DSCP_MASK    0x3F00\n#define    RTL8367C_DSCP44_DSCP_OFFSET    0\n#define    RTL8367C_DSCP44_DSCP_MASK    0x3F\n\n#define    RTL8367C_REG_QOS_DSCP_REMARK_DSCP_CTRL23    0x09F7\n#define    RTL8367C_DSCP47_DSCP_OFFSET    8\n#define    RTL8367C_DSCP47_DSCP_MASK    0x3F00\n#define    RTL8367C_DSCP46_DSCP_OFFSET    0\n#define    RTL8367C_DSCP46_DSCP_MASK    0x3F\n\n#define    RTL8367C_REG_QOS_DSCP_REMARK_DSCP_CTRL24    0x09F8\n#define    RTL8367C_DSCP49_DSCP_OFFSET    8\n#define    RTL8367C_DSCP49_DSCP_MASK    0x3F00\n#define    RTL8367C_DSCP48_DSCP_OFFSET    0\n#define    RTL8367C_DSCP48_DSCP_MASK    0x3F\n\n#define    RTL8367C_REG_QOS_DSCP_REMARK_DSCP_CTRL25    0x09F9\n#define    RTL8367C_DSCP51_DSCP_OFFSET    8\n#define    RTL8367C_DSCP51_DSCP_MASK    0x3F00\n#define    RTL8367C_DSCP50_DSCP_OFFSET    0\n#define    RTL8367C_DSCP50_DSCP_MASK    0x3F\n\n#define    RTL8367C_REG_QOS_DSCP_REMARK_DSCP_CTRL26    0x09FA\n#define    RTL8367C_DSCP53_DSCP_OFFSET    8\n#define    RTL8367C_DSCP53_DSCP_MASK    0x3F00\n#define    RTL8367C_DSCP52_DSCP_OFFSET    0\n#define    RTL8367C_DSCP52_DSCP_MASK    0x3F\n\n#define    RTL8367C_REG_QOS_DSCP_REMARK_DSCP_CTRL27    0x09FB\n#define    RTL8367C_DSCP55_DSCP_OFFSET    8\n#define    RTL8367C_DSCP55_DSCP_MASK    0x3F00\n#define    RTL8367C_DSCP54_DSCP_OFFSET    0\n#define    RTL8367C_DSCP54_DSCP_MASK    0x3F\n\n#define    RTL8367C_REG_QOS_DSCP_REMARK_DSCP_CTRL28    0x09FC\n#define    RTL8367C_DSCP57_DSCP_OFFSET    8\n#define    RTL8367C_DSCP57_DSCP_MASK    0x3F00\n#define    RTL8367C_DSCP56_DSCP_OFFSET    0\n#define    RTL8367C_DSCP56_DSCP_MASK    0x3F\n\n#define    RTL8367C_REG_QOS_DSCP_REMARK_DSCP_CTRL29    0x09FD\n#define    RTL8367C_DSCP59_DSCP_OFFSET    8\n#define    RTL8367C_DSCP59_DSCP_MASK    0x3F00\n#define    RTL8367C_DSCP58_DSCP_OFFSET    0\n#define    RTL8367C_DSCP58_DSCP_MASK    0x3F\n\n#define    RTL8367C_REG_QOS_DSCP_REMARK_DSCP_CTRL30    0x09FE\n#define    RTL8367C_DSCP61_DSCP_OFFSET    8\n#define    RTL8367C_DSCP61_DSCP_MASK    0x3F00\n#define    RTL8367C_DSCP60_DSCP_OFFSET    0\n#define    RTL8367C_DSCP60_DSCP_MASK    0x3F\n\n#define    RTL8367C_REG_QOS_DSCP_REMARK_DSCP_CTRL31    0x09FF\n#define    RTL8367C_DSCP63_DSCP_OFFSET    8\n#define    RTL8367C_DSCP63_DSCP_MASK    0x3F00\n#define    RTL8367C_DSCP62_DSCP_OFFSET    0\n#define    RTL8367C_DSCP62_DSCP_MASK    0x3F\n\n/* (16'h0a00)l2_reg */\n\n#define    RTL8367C_REG_VLAN_MSTI0_CTRL0    0x0a00\n#define    RTL8367C_VLAN_MSTI0_CTRL0_PORT7_STATE_OFFSET    14\n#define    RTL8367C_VLAN_MSTI0_CTRL0_PORT7_STATE_MASK    0xC000\n#define    RTL8367C_VLAN_MSTI0_CTRL0_PORT6_STATE_OFFSET    12\n#define    RTL8367C_VLAN_MSTI0_CTRL0_PORT6_STATE_MASK    0x3000\n#define    RTL8367C_VLAN_MSTI0_CTRL0_PORT5_STATE_OFFSET    10\n#define    RTL8367C_VLAN_MSTI0_CTRL0_PORT5_STATE_MASK    0xC00\n#define    RTL8367C_VLAN_MSTI0_CTRL0_PORT4_STATE_OFFSET    8\n#define    RTL8367C_VLAN_MSTI0_CTRL0_PORT4_STATE_MASK    0x300\n#define    RTL8367C_VLAN_MSTI0_CTRL0_PORT3_STATE_OFFSET    6\n#define    RTL8367C_VLAN_MSTI0_CTRL0_PORT3_STATE_MASK    0xC0\n#define    RTL8367C_VLAN_MSTI0_CTRL0_PORT2_STATE_OFFSET    4\n#define    RTL8367C_VLAN_MSTI0_CTRL0_PORT2_STATE_MASK    0x30\n#define    RTL8367C_VLAN_MSTI0_CTRL0_PORT1_STATE_OFFSET    2\n#define    RTL8367C_VLAN_MSTI0_CTRL0_PORT1_STATE_MASK    0xC\n#define    RTL8367C_VLAN_MSTI0_CTRL0_PORT0_STATE_OFFSET    0\n#define    RTL8367C_VLAN_MSTI0_CTRL0_PORT0_STATE_MASK    0x3\n\n#define    RTL8367C_REG_VLAN_MSTI0_CTRL1    0x0a01\n#define    RTL8367C_VLAN_MSTI0_CTRL1_PORT10_STATE_OFFSET    4\n#define    RTL8367C_VLAN_MSTI0_CTRL1_PORT10_STATE_MASK    0x30\n#define    RTL8367C_VLAN_MSTI0_CTRL1_PORT9_STATE_OFFSET    2\n#define    RTL8367C_VLAN_MSTI0_CTRL1_PORT9_STATE_MASK    0xC\n#define    RTL8367C_VLAN_MSTI0_CTRL1_PORT8_STATE_OFFSET    0\n#define    RTL8367C_VLAN_MSTI0_CTRL1_PORT8_STATE_MASK    0x3\n\n#define    RTL8367C_REG_VLAN_MSTI1_CTRL0    0x0a02\n#define    RTL8367C_VLAN_MSTI1_CTRL0_PORT7_STATE_OFFSET    14\n#define    RTL8367C_VLAN_MSTI1_CTRL0_PORT7_STATE_MASK    0xC000\n#define    RTL8367C_VLAN_MSTI1_CTRL0_PORT6_STATE_OFFSET    12\n#define    RTL8367C_VLAN_MSTI1_CTRL0_PORT6_STATE_MASK    0x3000\n#define    RTL8367C_VLAN_MSTI1_CTRL0_PORT5_STATE_OFFSET    10\n#define    RTL8367C_VLAN_MSTI1_CTRL0_PORT5_STATE_MASK    0xC00\n#define    RTL8367C_VLAN_MSTI1_CTRL0_PORT4_STATE_OFFSET    8\n#define    RTL8367C_VLAN_MSTI1_CTRL0_PORT4_STATE_MASK    0x300\n#define    RTL8367C_VLAN_MSTI1_CTRL0_PORT3_STATE_OFFSET    6\n#define    RTL8367C_VLAN_MSTI1_CTRL0_PORT3_STATE_MASK    0xC0\n#define    RTL8367C_VLAN_MSTI1_CTRL0_PORT2_STATE_OFFSET    4\n#define    RTL8367C_VLAN_MSTI1_CTRL0_PORT2_STATE_MASK    0x30\n#define    RTL8367C_VLAN_MSTI1_CTRL0_PORT1_STATE_OFFSET    2\n#define    RTL8367C_VLAN_MSTI1_CTRL0_PORT1_STATE_MASK    0xC\n#define    RTL8367C_VLAN_MSTI1_CTRL0_PORT0_STATE_OFFSET    0\n#define    RTL8367C_VLAN_MSTI1_CTRL0_PORT0_STATE_MASK    0x3\n\n#define    RTL8367C_REG_VLAN_MSTI1_CTRL1    0x0a03\n#define    RTL8367C_VLAN_MSTI1_CTRL1_PORT10_STATE_OFFSET    4\n#define    RTL8367C_VLAN_MSTI1_CTRL1_PORT10_STATE_MASK    0x30\n#define    RTL8367C_VLAN_MSTI1_CTRL1_PORT9_STATE_OFFSET    2\n#define    RTL8367C_VLAN_MSTI1_CTRL1_PORT9_STATE_MASK    0xC\n#define    RTL8367C_VLAN_MSTI1_CTRL1_PORT8_STATE_OFFSET    0\n#define    RTL8367C_VLAN_MSTI1_CTRL1_PORT8_STATE_MASK    0x3\n\n#define    RTL8367C_REG_VLAN_MSTI2_CTRL0    0x0a04\n#define    RTL8367C_VLAN_MSTI2_CTRL0_PORT7_STATE_OFFSET    14\n#define    RTL8367C_VLAN_MSTI2_CTRL0_PORT7_STATE_MASK    0xC000\n#define    RTL8367C_VLAN_MSTI2_CTRL0_PORT6_STATE_OFFSET    12\n#define    RTL8367C_VLAN_MSTI2_CTRL0_PORT6_STATE_MASK    0x3000\n#define    RTL8367C_VLAN_MSTI2_CTRL0_PORT5_STATE_OFFSET    10\n#define    RTL8367C_VLAN_MSTI2_CTRL0_PORT5_STATE_MASK    0xC00\n#define    RTL8367C_VLAN_MSTI2_CTRL0_PORT4_STATE_OFFSET    8\n#define    RTL8367C_VLAN_MSTI2_CTRL0_PORT4_STATE_MASK    0x300\n#define    RTL8367C_VLAN_MSTI2_CTRL0_PORT3_STATE_OFFSET    6\n#define    RTL8367C_VLAN_MSTI2_CTRL0_PORT3_STATE_MASK    0xC0\n#define    RTL8367C_VLAN_MSTI2_CTRL0_PORT2_STATE_OFFSET    4\n#define    RTL8367C_VLAN_MSTI2_CTRL0_PORT2_STATE_MASK    0x30\n#define    RTL8367C_VLAN_MSTI2_CTRL0_PORT1_STATE_OFFSET    2\n#define    RTL8367C_VLAN_MSTI2_CTRL0_PORT1_STATE_MASK    0xC\n#define    RTL8367C_VLAN_MSTI2_CTRL0_PORT0_STATE_OFFSET    0\n#define    RTL8367C_VLAN_MSTI2_CTRL0_PORT0_STATE_MASK    0x3\n\n#define    RTL8367C_REG_VLAN_MSTI2_CTRL1    0x0a05\n#define    RTL8367C_VLAN_MSTI2_CTRL1_PORT10_STATE_OFFSET    4\n#define    RTL8367C_VLAN_MSTI2_CTRL1_PORT10_STATE_MASK    0x30\n#define    RTL8367C_VLAN_MSTI2_CTRL1_PORT9_STATE_OFFSET    2\n#define    RTL8367C_VLAN_MSTI2_CTRL1_PORT9_STATE_MASK    0xC\n#define    RTL8367C_VLAN_MSTI2_CTRL1_PORT8_STATE_OFFSET    0\n#define    RTL8367C_VLAN_MSTI2_CTRL1_PORT8_STATE_MASK    0x3\n\n#define    RTL8367C_REG_VLAN_MSTI3_CTRL0    0x0a06\n#define    RTL8367C_VLAN_MSTI3_CTRL0_PORT7_STATE_OFFSET    14\n#define    RTL8367C_VLAN_MSTI3_CTRL0_PORT7_STATE_MASK    0xC000\n#define    RTL8367C_VLAN_MSTI3_CTRL0_PORT6_STATE_OFFSET    12\n#define    RTL8367C_VLAN_MSTI3_CTRL0_PORT6_STATE_MASK    0x3000\n#define    RTL8367C_VLAN_MSTI3_CTRL0_PORT5_STATE_OFFSET    10\n#define    RTL8367C_VLAN_MSTI3_CTRL0_PORT5_STATE_MASK    0xC00\n#define    RTL8367C_VLAN_MSTI3_CTRL0_PORT4_STATE_OFFSET    8\n#define    RTL8367C_VLAN_MSTI3_CTRL0_PORT4_STATE_MASK    0x300\n#define    RTL8367C_VLAN_MSTI3_CTRL0_PORT3_STATE_OFFSET    6\n#define    RTL8367C_VLAN_MSTI3_CTRL0_PORT3_STATE_MASK    0xC0\n#define    RTL8367C_VLAN_MSTI3_CTRL0_PORT2_STATE_OFFSET    4\n#define    RTL8367C_VLAN_MSTI3_CTRL0_PORT2_STATE_MASK    0x30\n#define    RTL8367C_VLAN_MSTI3_CTRL0_PORT1_STATE_OFFSET    2\n#define    RTL8367C_VLAN_MSTI3_CTRL0_PORT1_STATE_MASK    0xC\n#define    RTL8367C_VLAN_MSTI3_CTRL0_PORT0_STATE_OFFSET    0\n#define    RTL8367C_VLAN_MSTI3_CTRL0_PORT0_STATE_MASK    0x3\n\n#define    RTL8367C_REG_VLAN_MSTI3_CTRL1    0x0a07\n#define    RTL8367C_VLAN_MSTI3_CTRL1_PORT10_STATE_OFFSET    4\n#define    RTL8367C_VLAN_MSTI3_CTRL1_PORT10_STATE_MASK    0x30\n#define    RTL8367C_VLAN_MSTI3_CTRL1_PORT9_STATE_OFFSET    2\n#define    RTL8367C_VLAN_MSTI3_CTRL1_PORT9_STATE_MASK    0xC\n#define    RTL8367C_VLAN_MSTI3_CTRL1_PORT8_STATE_OFFSET    0\n#define    RTL8367C_VLAN_MSTI3_CTRL1_PORT8_STATE_MASK    0x3\n\n#define    RTL8367C_REG_VLAN_MSTI4_CTRL0    0x0a08\n#define    RTL8367C_VLAN_MSTI4_CTRL0_PORT7_STATE_OFFSET    14\n#define    RTL8367C_VLAN_MSTI4_CTRL0_PORT7_STATE_MASK    0xC000\n#define    RTL8367C_VLAN_MSTI4_CTRL0_PORT6_STATE_OFFSET    12\n#define    RTL8367C_VLAN_MSTI4_CTRL0_PORT6_STATE_MASK    0x3000\n#define    RTL8367C_VLAN_MSTI4_CTRL0_PORT5_STATE_OFFSET    10\n#define    RTL8367C_VLAN_MSTI4_CTRL0_PORT5_STATE_MASK    0xC00\n#define    RTL8367C_VLAN_MSTI4_CTRL0_PORT4_STATE_OFFSET    8\n#define    RTL8367C_VLAN_MSTI4_CTRL0_PORT4_STATE_MASK    0x300\n#define    RTL8367C_VLAN_MSTI4_CTRL0_PORT3_STATE_OFFSET    6\n#define    RTL8367C_VLAN_MSTI4_CTRL0_PORT3_STATE_MASK    0xC0\n#define    RTL8367C_VLAN_MSTI4_CTRL0_PORT2_STATE_OFFSET    4\n#define    RTL8367C_VLAN_MSTI4_CTRL0_PORT2_STATE_MASK    0x30\n#define    RTL8367C_VLAN_MSTI4_CTRL0_PORT1_STATE_OFFSET    2\n#define    RTL8367C_VLAN_MSTI4_CTRL0_PORT1_STATE_MASK    0xC\n#define    RTL8367C_VLAN_MSTI4_CTRL0_PORT0_STATE_OFFSET    0\n#define    RTL8367C_VLAN_MSTI4_CTRL0_PORT0_STATE_MASK    0x3\n\n#define    RTL8367C_REG_VLAN_MSTI4_CTRL1    0x0a09\n#define    RTL8367C_VLAN_MSTI4_CTRL1_PORT10_STATE_OFFSET    4\n#define    RTL8367C_VLAN_MSTI4_CTRL1_PORT10_STATE_MASK    0x30\n#define    RTL8367C_VLAN_MSTI4_CTRL1_PORT9_STATE_OFFSET    2\n#define    RTL8367C_VLAN_MSTI4_CTRL1_PORT9_STATE_MASK    0xC\n#define    RTL8367C_VLAN_MSTI4_CTRL1_PORT8_STATE_OFFSET    0\n#define    RTL8367C_VLAN_MSTI4_CTRL1_PORT8_STATE_MASK    0x3\n\n#define    RTL8367C_REG_VLAN_MSTI5_CTRL0    0x0a0a\n#define    RTL8367C_VLAN_MSTI5_CTRL0_PORT7_STATE_OFFSET    14\n#define    RTL8367C_VLAN_MSTI5_CTRL0_PORT7_STATE_MASK    0xC000\n#define    RTL8367C_VLAN_MSTI5_CTRL0_PORT6_STATE_OFFSET    12\n#define    RTL8367C_VLAN_MSTI5_CTRL0_PORT6_STATE_MASK    0x3000\n#define    RTL8367C_VLAN_MSTI5_CTRL0_PORT5_STATE_OFFSET    10\n#define    RTL8367C_VLAN_MSTI5_CTRL0_PORT5_STATE_MASK    0xC00\n#define    RTL8367C_VLAN_MSTI5_CTRL0_PORT4_STATE_OFFSET    8\n#define    RTL8367C_VLAN_MSTI5_CTRL0_PORT4_STATE_MASK    0x300\n#define    RTL8367C_VLAN_MSTI5_CTRL0_PORT3_STATE_OFFSET    6\n#define    RTL8367C_VLAN_MSTI5_CTRL0_PORT3_STATE_MASK    0xC0\n#define    RTL8367C_VLAN_MSTI5_CTRL0_PORT2_STATE_OFFSET    4\n#define    RTL8367C_VLAN_MSTI5_CTRL0_PORT2_STATE_MASK    0x30\n#define    RTL8367C_VLAN_MSTI5_CTRL0_PORT1_STATE_OFFSET    2\n#define    RTL8367C_VLAN_MSTI5_CTRL0_PORT1_STATE_MASK    0xC\n#define    RTL8367C_VLAN_MSTI5_CTRL0_PORT0_STATE_OFFSET    0\n#define    RTL8367C_VLAN_MSTI5_CTRL0_PORT0_STATE_MASK    0x3\n\n#define    RTL8367C_REG_VLAN_MSTI5_CTRL1    0x0a0b\n#define    RTL8367C_VLAN_MSTI5_CTRL1_PORT10_STATE_OFFSET    4\n#define    RTL8367C_VLAN_MSTI5_CTRL1_PORT10_STATE_MASK    0x30\n#define    RTL8367C_VLAN_MSTI5_CTRL1_PORT9_STATE_OFFSET    2\n#define    RTL8367C_VLAN_MSTI5_CTRL1_PORT9_STATE_MASK    0xC\n#define    RTL8367C_VLAN_MSTI5_CTRL1_PORT8_STATE_OFFSET    0\n#define    RTL8367C_VLAN_MSTI5_CTRL1_PORT8_STATE_MASK    0x3\n\n#define    RTL8367C_REG_VLAN_MSTI6_CTRL0    0x0a0c\n#define    RTL8367C_VLAN_MSTI6_CTRL0_PORT7_STATE_OFFSET    14\n#define    RTL8367C_VLAN_MSTI6_CTRL0_PORT7_STATE_MASK    0xC000\n#define    RTL8367C_VLAN_MSTI6_CTRL0_PORT6_STATE_OFFSET    12\n#define    RTL8367C_VLAN_MSTI6_CTRL0_PORT6_STATE_MASK    0x3000\n#define    RTL8367C_VLAN_MSTI6_CTRL0_PORT5_STATE_OFFSET    10\n#define    RTL8367C_VLAN_MSTI6_CTRL0_PORT5_STATE_MASK    0xC00\n#define    RTL8367C_VLAN_MSTI6_CTRL0_PORT4_STATE_OFFSET    8\n#define    RTL8367C_VLAN_MSTI6_CTRL0_PORT4_STATE_MASK    0x300\n#define    RTL8367C_VLAN_MSTI6_CTRL0_PORT3_STATE_OFFSET    6\n#define    RTL8367C_VLAN_MSTI6_CTRL0_PORT3_STATE_MASK    0xC0\n#define    RTL8367C_VLAN_MSTI6_CTRL0_PORT2_STATE_OFFSET    4\n#define    RTL8367C_VLAN_MSTI6_CTRL0_PORT2_STATE_MASK    0x30\n#define    RTL8367C_VLAN_MSTI6_CTRL0_PORT1_STATE_OFFSET    2\n#define    RTL8367C_VLAN_MSTI6_CTRL0_PORT1_STATE_MASK    0xC\n#define    RTL8367C_VLAN_MSTI6_CTRL0_PORT0_STATE_OFFSET    0\n#define    RTL8367C_VLAN_MSTI6_CTRL0_PORT0_STATE_MASK    0x3\n\n#define    RTL8367C_REG_VLAN_MSTI6_CTRL1    0x0a0d\n#define    RTL8367C_VLAN_MSTI6_CTRL1_PORT10_STATE_OFFSET    4\n#define    RTL8367C_VLAN_MSTI6_CTRL1_PORT10_STATE_MASK    0x30\n#define    RTL8367C_VLAN_MSTI6_CTRL1_PORT9_STATE_OFFSET    2\n#define    RTL8367C_VLAN_MSTI6_CTRL1_PORT9_STATE_MASK    0xC\n#define    RTL8367C_VLAN_MSTI6_CTRL1_PORT8_STATE_OFFSET    0\n#define    RTL8367C_VLAN_MSTI6_CTRL1_PORT8_STATE_MASK    0x3\n\n#define    RTL8367C_REG_VLAN_MSTI7_CTRL0    0x0a0e\n#define    RTL8367C_VLAN_MSTI7_CTRL0_PORT7_STATE_OFFSET    14\n#define    RTL8367C_VLAN_MSTI7_CTRL0_PORT7_STATE_MASK    0xC000\n#define    RTL8367C_VLAN_MSTI7_CTRL0_PORT6_STATE_OFFSET    12\n#define    RTL8367C_VLAN_MSTI7_CTRL0_PORT6_STATE_MASK    0x3000\n#define    RTL8367C_VLAN_MSTI7_CTRL0_PORT5_STATE_OFFSET    10\n#define    RTL8367C_VLAN_MSTI7_CTRL0_PORT5_STATE_MASK    0xC00\n#define    RTL8367C_VLAN_MSTI7_CTRL0_PORT4_STATE_OFFSET    8\n#define    RTL8367C_VLAN_MSTI7_CTRL0_PORT4_STATE_MASK    0x300\n#define    RTL8367C_VLAN_MSTI7_CTRL0_PORT3_STATE_OFFSET    6\n#define    RTL8367C_VLAN_MSTI7_CTRL0_PORT3_STATE_MASK    0xC0\n#define    RTL8367C_VLAN_MSTI7_CTRL0_PORT2_STATE_OFFSET    4\n#define    RTL8367C_VLAN_MSTI7_CTRL0_PORT2_STATE_MASK    0x30\n#define    RTL8367C_VLAN_MSTI7_CTRL0_PORT1_STATE_OFFSET    2\n#define    RTL8367C_VLAN_MSTI7_CTRL0_PORT1_STATE_MASK    0xC\n#define    RTL8367C_VLAN_MSTI7_CTRL0_PORT0_STATE_OFFSET    0\n#define    RTL8367C_VLAN_MSTI7_CTRL0_PORT0_STATE_MASK    0x3\n\n#define    RTL8367C_REG_VLAN_MSTI7_CTRL1    0x0a0f\n#define    RTL8367C_VLAN_MSTI7_CTRL1_PORT10_STATE_OFFSET    4\n#define    RTL8367C_VLAN_MSTI7_CTRL1_PORT10_STATE_MASK    0x30\n#define    RTL8367C_VLAN_MSTI7_CTRL1_PORT9_STATE_OFFSET    2\n#define    RTL8367C_VLAN_MSTI7_CTRL1_PORT9_STATE_MASK    0xC\n#define    RTL8367C_VLAN_MSTI7_CTRL1_PORT8_STATE_OFFSET    0\n#define    RTL8367C_VLAN_MSTI7_CTRL1_PORT8_STATE_MASK    0x3\n\n#define    RTL8367C_REG_VLAN_MSTI8_CTRL0    0x0a10\n#define    RTL8367C_VLAN_MSTI8_CTRL0_PORT7_STATE_OFFSET    14\n#define    RTL8367C_VLAN_MSTI8_CTRL0_PORT7_STATE_MASK    0xC000\n#define    RTL8367C_VLAN_MSTI8_CTRL0_PORT6_STATE_OFFSET    12\n#define    RTL8367C_VLAN_MSTI8_CTRL0_PORT6_STATE_MASK    0x3000\n#define    RTL8367C_VLAN_MSTI8_CTRL0_PORT5_STATE_OFFSET    10\n#define    RTL8367C_VLAN_MSTI8_CTRL0_PORT5_STATE_MASK    0xC00\n#define    RTL8367C_VLAN_MSTI8_CTRL0_PORT4_STATE_OFFSET    8\n#define    RTL8367C_VLAN_MSTI8_CTRL0_PORT4_STATE_MASK    0x300\n#define    RTL8367C_VLAN_MSTI8_CTRL0_PORT3_STATE_OFFSET    6\n#define    RTL8367C_VLAN_MSTI8_CTRL0_PORT3_STATE_MASK    0xC0\n#define    RTL8367C_VLAN_MSTI8_CTRL0_PORT2_STATE_OFFSET    4\n#define    RTL8367C_VLAN_MSTI8_CTRL0_PORT2_STATE_MASK    0x30\n#define    RTL8367C_VLAN_MSTI8_CTRL0_PORT1_STATE_OFFSET    2\n#define    RTL8367C_VLAN_MSTI8_CTRL0_PORT1_STATE_MASK    0xC\n#define    RTL8367C_VLAN_MSTI8_CTRL0_PORT0_STATE_OFFSET    0\n#define    RTL8367C_VLAN_MSTI8_CTRL0_PORT0_STATE_MASK    0x3\n\n#define    RTL8367C_REG_VLAN_MSTI8_CTRL1    0x0a11\n#define    RTL8367C_VLAN_MSTI8_CTRL1_PORT10_STATE_OFFSET    4\n#define    RTL8367C_VLAN_MSTI8_CTRL1_PORT10_STATE_MASK    0x30\n#define    RTL8367C_VLAN_MSTI8_CTRL1_PORT9_STATE_OFFSET    2\n#define    RTL8367C_VLAN_MSTI8_CTRL1_PORT9_STATE_MASK    0xC\n#define    RTL8367C_VLAN_MSTI8_CTRL1_PORT8_STATE_OFFSET    0\n#define    RTL8367C_VLAN_MSTI8_CTRL1_PORT8_STATE_MASK    0x3\n\n#define    RTL8367C_REG_VLAN_MSTI9_CTRL0    0x0a12\n#define    RTL8367C_VLAN_MSTI9_CTRL0_PORT7_STATE_OFFSET    14\n#define    RTL8367C_VLAN_MSTI9_CTRL0_PORT7_STATE_MASK    0xC000\n#define    RTL8367C_VLAN_MSTI9_CTRL0_PORT6_STATE_OFFSET    12\n#define    RTL8367C_VLAN_MSTI9_CTRL0_PORT6_STATE_MASK    0x3000\n#define    RTL8367C_VLAN_MSTI9_CTRL0_PORT5_STATE_OFFSET    10\n#define    RTL8367C_VLAN_MSTI9_CTRL0_PORT5_STATE_MASK    0xC00\n#define    RTL8367C_VLAN_MSTI9_CTRL0_PORT4_STATE_OFFSET    8\n#define    RTL8367C_VLAN_MSTI9_CTRL0_PORT4_STATE_MASK    0x300\n#define    RTL8367C_VLAN_MSTI9_CTRL0_PORT3_STATE_OFFSET    6\n#define    RTL8367C_VLAN_MSTI9_CTRL0_PORT3_STATE_MASK    0xC0\n#define    RTL8367C_VLAN_MSTI9_CTRL0_PORT2_STATE_OFFSET    4\n#define    RTL8367C_VLAN_MSTI9_CTRL0_PORT2_STATE_MASK    0x30\n#define    RTL8367C_VLAN_MSTI9_CTRL0_PORT1_STATE_OFFSET    2\n#define    RTL8367C_VLAN_MSTI9_CTRL0_PORT1_STATE_MASK    0xC\n#define    RTL8367C_VLAN_MSTI9_CTRL0_PORT0_STATE_OFFSET    0\n#define    RTL8367C_VLAN_MSTI9_CTRL0_PORT0_STATE_MASK    0x3\n\n#define    RTL8367C_REG_VLAN_MSTI9_CTRL1    0x0a13\n#define    RTL8367C_VLAN_MSTI9_CTRL1_PORT10_STATE_OFFSET    4\n#define    RTL8367C_VLAN_MSTI9_CTRL1_PORT10_STATE_MASK    0x30\n#define    RTL8367C_VLAN_MSTI9_CTRL1_PORT9_STATE_OFFSET    2\n#define    RTL8367C_VLAN_MSTI9_CTRL1_PORT9_STATE_MASK    0xC\n#define    RTL8367C_VLAN_MSTI9_CTRL1_PORT8_STATE_OFFSET    0\n#define    RTL8367C_VLAN_MSTI9_CTRL1_PORT8_STATE_MASK    0x3\n\n#define    RTL8367C_REG_VLAN_MSTI10_CTRL0    0x0a14\n#define    RTL8367C_VLAN_MSTI10_CTRL0_PORT7_STATE_OFFSET    14\n#define    RTL8367C_VLAN_MSTI10_CTRL0_PORT7_STATE_MASK    0xC000\n#define    RTL8367C_VLAN_MSTI10_CTRL0_PORT6_STATE_OFFSET    12\n#define    RTL8367C_VLAN_MSTI10_CTRL0_PORT6_STATE_MASK    0x3000\n#define    RTL8367C_VLAN_MSTI10_CTRL0_PORT5_STATE_OFFSET    10\n#define    RTL8367C_VLAN_MSTI10_CTRL0_PORT5_STATE_MASK    0xC00\n#define    RTL8367C_VLAN_MSTI10_CTRL0_PORT4_STATE_OFFSET    8\n#define    RTL8367C_VLAN_MSTI10_CTRL0_PORT4_STATE_MASK    0x300\n#define    RTL8367C_VLAN_MSTI10_CTRL0_PORT3_STATE_OFFSET    6\n#define    RTL8367C_VLAN_MSTI10_CTRL0_PORT3_STATE_MASK    0xC0\n#define    RTL8367C_VLAN_MSTI10_CTRL0_PORT2_STATE_OFFSET    4\n#define    RTL8367C_VLAN_MSTI10_CTRL0_PORT2_STATE_MASK    0x30\n#define    RTL8367C_VLAN_MSTI10_CTRL0_PORT1_STATE_OFFSET    2\n#define    RTL8367C_VLAN_MSTI10_CTRL0_PORT1_STATE_MASK    0xC\n#define    RTL8367C_VLAN_MSTI10_CTRL0_PORT0_STATE_OFFSET    0\n#define    RTL8367C_VLAN_MSTI10_CTRL0_PORT0_STATE_MASK    0x3\n\n#define    RTL8367C_REG_VLAN_MSTI10_CTRL1    0x0a15\n#define    RTL8367C_VLAN_MSTI10_CTRL1_PORT10_STATE_OFFSET    4\n#define    RTL8367C_VLAN_MSTI10_CTRL1_PORT10_STATE_MASK    0x30\n#define    RTL8367C_VLAN_MSTI10_CTRL1_PORT9_STATE_OFFSET    2\n#define    RTL8367C_VLAN_MSTI10_CTRL1_PORT9_STATE_MASK    0xC\n#define    RTL8367C_VLAN_MSTI10_CTRL1_PORT8_STATE_OFFSET    0\n#define    RTL8367C_VLAN_MSTI10_CTRL1_PORT8_STATE_MASK    0x3\n\n#define    RTL8367C_REG_VLAN_MSTI11_CTRL0    0x0a16\n#define    RTL8367C_VLAN_MSTI11_CTRL0_PORT7_STATE_OFFSET    14\n#define    RTL8367C_VLAN_MSTI11_CTRL0_PORT7_STATE_MASK    0xC000\n#define    RTL8367C_VLAN_MSTI11_CTRL0_PORT6_STATE_OFFSET    12\n#define    RTL8367C_VLAN_MSTI11_CTRL0_PORT6_STATE_MASK    0x3000\n#define    RTL8367C_VLAN_MSTI11_CTRL0_PORT5_STATE_OFFSET    10\n#define    RTL8367C_VLAN_MSTI11_CTRL0_PORT5_STATE_MASK    0xC00\n#define    RTL8367C_VLAN_MSTI11_CTRL0_PORT4_STATE_OFFSET    8\n#define    RTL8367C_VLAN_MSTI11_CTRL0_PORT4_STATE_MASK    0x300\n#define    RTL8367C_VLAN_MSTI11_CTRL0_PORT3_STATE_OFFSET    6\n#define    RTL8367C_VLAN_MSTI11_CTRL0_PORT3_STATE_MASK    0xC0\n#define    RTL8367C_VLAN_MSTI11_CTRL0_PORT2_STATE_OFFSET    4\n#define    RTL8367C_VLAN_MSTI11_CTRL0_PORT2_STATE_MASK    0x30\n#define    RTL8367C_VLAN_MSTI11_CTRL0_PORT1_STATE_OFFSET    2\n#define    RTL8367C_VLAN_MSTI11_CTRL0_PORT1_STATE_MASK    0xC\n#define    RTL8367C_VLAN_MSTI11_CTRL0_PORT0_STATE_OFFSET    0\n#define    RTL8367C_VLAN_MSTI11_CTRL0_PORT0_STATE_MASK    0x3\n\n#define    RTL8367C_REG_VLAN_MSTI11_CTRL1    0x0a17\n#define    RTL8367C_VLAN_MSTI11_CTRL1_PORT10_STATE_OFFSET    4\n#define    RTL8367C_VLAN_MSTI11_CTRL1_PORT10_STATE_MASK    0x30\n#define    RTL8367C_VLAN_MSTI11_CTRL1_PORT9_STATE_OFFSET    2\n#define    RTL8367C_VLAN_MSTI11_CTRL1_PORT9_STATE_MASK    0xC\n#define    RTL8367C_VLAN_MSTI11_CTRL1_PORT8_STATE_OFFSET    0\n#define    RTL8367C_VLAN_MSTI11_CTRL1_PORT8_STATE_MASK    0x3\n\n#define    RTL8367C_REG_VLAN_MSTI12_CTRL0    0x0a18\n#define    RTL8367C_VLAN_MSTI12_CTRL0_PORT7_STATE_OFFSET    14\n#define    RTL8367C_VLAN_MSTI12_CTRL0_PORT7_STATE_MASK    0xC000\n#define    RTL8367C_VLAN_MSTI12_CTRL0_PORT6_STATE_OFFSET    12\n#define    RTL8367C_VLAN_MSTI12_CTRL0_PORT6_STATE_MASK    0x3000\n#define    RTL8367C_VLAN_MSTI12_CTRL0_PORT5_STATE_OFFSET    10\n#define    RTL8367C_VLAN_MSTI12_CTRL0_PORT5_STATE_MASK    0xC00\n#define    RTL8367C_VLAN_MSTI12_CTRL0_PORT4_STATE_OFFSET    8\n#define    RTL8367C_VLAN_MSTI12_CTRL0_PORT4_STATE_MASK    0x300\n#define    RTL8367C_VLAN_MSTI12_CTRL0_PORT3_STATE_OFFSET    6\n#define    RTL8367C_VLAN_MSTI12_CTRL0_PORT3_STATE_MASK    0xC0\n#define    RTL8367C_VLAN_MSTI12_CTRL0_PORT2_STATE_OFFSET    4\n#define    RTL8367C_VLAN_MSTI12_CTRL0_PORT2_STATE_MASK    0x30\n#define    RTL8367C_VLAN_MSTI12_CTRL0_PORT1_STATE_OFFSET    2\n#define    RTL8367C_VLAN_MSTI12_CTRL0_PORT1_STATE_MASK    0xC\n#define    RTL8367C_VLAN_MSTI12_CTRL0_PORT0_STATE_OFFSET    0\n#define    RTL8367C_VLAN_MSTI12_CTRL0_PORT0_STATE_MASK    0x3\n\n#define    RTL8367C_REG_VLAN_MSTI12_CTRL1    0x0a19\n#define    RTL8367C_VLAN_MSTI12_CTRL1_PORT10_STATE_OFFSET    4\n#define    RTL8367C_VLAN_MSTI12_CTRL1_PORT10_STATE_MASK    0x30\n#define    RTL8367C_VLAN_MSTI12_CTRL1_PORT9_STATE_OFFSET    2\n#define    RTL8367C_VLAN_MSTI12_CTRL1_PORT9_STATE_MASK    0xC\n#define    RTL8367C_VLAN_MSTI12_CTRL1_PORT8_STATE_OFFSET    0\n#define    RTL8367C_VLAN_MSTI12_CTRL1_PORT8_STATE_MASK    0x3\n\n#define    RTL8367C_REG_VLAN_MSTI13_CTRL0    0x0a1a\n#define    RTL8367C_VLAN_MSTI13_CTRL0_PORT7_STATE_OFFSET    14\n#define    RTL8367C_VLAN_MSTI13_CTRL0_PORT7_STATE_MASK    0xC000\n#define    RTL8367C_VLAN_MSTI13_CTRL0_PORT6_STATE_OFFSET    12\n#define    RTL8367C_VLAN_MSTI13_CTRL0_PORT6_STATE_MASK    0x3000\n#define    RTL8367C_VLAN_MSTI13_CTRL0_PORT5_STATE_OFFSET    10\n#define    RTL8367C_VLAN_MSTI13_CTRL0_PORT5_STATE_MASK    0xC00\n#define    RTL8367C_VLAN_MSTI13_CTRL0_PORT4_STATE_OFFSET    8\n#define    RTL8367C_VLAN_MSTI13_CTRL0_PORT4_STATE_MASK    0x300\n#define    RTL8367C_VLAN_MSTI13_CTRL0_PORT3_STATE_OFFSET    6\n#define    RTL8367C_VLAN_MSTI13_CTRL0_PORT3_STATE_MASK    0xC0\n#define    RTL8367C_VLAN_MSTI13_CTRL0_PORT2_STATE_OFFSET    4\n#define    RTL8367C_VLAN_MSTI13_CTRL0_PORT2_STATE_MASK    0x30\n#define    RTL8367C_VLAN_MSTI13_CTRL0_PORT1_STATE_OFFSET    2\n#define    RTL8367C_VLAN_MSTI13_CTRL0_PORT1_STATE_MASK    0xC\n#define    RTL8367C_VLAN_MSTI13_CTRL0_PORT0_STATE_OFFSET    0\n#define    RTL8367C_VLAN_MSTI13_CTRL0_PORT0_STATE_MASK    0x3\n\n#define    RTL8367C_REG_VLAN_MSTI13_CTRL1    0x0a1b\n#define    RTL8367C_VLAN_MSTI13_CTRL1_PORT10_STATE_OFFSET    4\n#define    RTL8367C_VLAN_MSTI13_CTRL1_PORT10_STATE_MASK    0x30\n#define    RTL8367C_VLAN_MSTI13_CTRL1_PORT9_STATE_OFFSET    2\n#define    RTL8367C_VLAN_MSTI13_CTRL1_PORT9_STATE_MASK    0xC\n#define    RTL8367C_VLAN_MSTI13_CTRL1_PORT8_STATE_OFFSET    0\n#define    RTL8367C_VLAN_MSTI13_CTRL1_PORT8_STATE_MASK    0x3\n\n#define    RTL8367C_REG_VLAN_MSTI14_CTRL0    0x0a1c\n#define    RTL8367C_VLAN_MSTI14_CTRL0_PORT7_STATE_OFFSET    14\n#define    RTL8367C_VLAN_MSTI14_CTRL0_PORT7_STATE_MASK    0xC000\n#define    RTL8367C_VLAN_MSTI14_CTRL0_PORT6_STATE_OFFSET    12\n#define    RTL8367C_VLAN_MSTI14_CTRL0_PORT6_STATE_MASK    0x3000\n#define    RTL8367C_VLAN_MSTI14_CTRL0_PORT5_STATE_OFFSET    10\n#define    RTL8367C_VLAN_MSTI14_CTRL0_PORT5_STATE_MASK    0xC00\n#define    RTL8367C_VLAN_MSTI14_CTRL0_PORT4_STATE_OFFSET    8\n#define    RTL8367C_VLAN_MSTI14_CTRL0_PORT4_STATE_MASK    0x300\n#define    RTL8367C_VLAN_MSTI14_CTRL0_PORT3_STATE_OFFSET    6\n#define    RTL8367C_VLAN_MSTI14_CTRL0_PORT3_STATE_MASK    0xC0\n#define    RTL8367C_VLAN_MSTI14_CTRL0_PORT2_STATE_OFFSET    4\n#define    RTL8367C_VLAN_MSTI14_CTRL0_PORT2_STATE_MASK    0x30\n#define    RTL8367C_VLAN_MSTI14_CTRL0_PORT1_STATE_OFFSET    2\n#define    RTL8367C_VLAN_MSTI14_CTRL0_PORT1_STATE_MASK    0xC\n#define    RTL8367C_VLAN_MSTI14_CTRL0_PORT0_STATE_OFFSET    0\n#define    RTL8367C_VLAN_MSTI14_CTRL0_PORT0_STATE_MASK    0x3\n\n#define    RTL8367C_REG_VLAN_MSTI14_CTRL1    0x0a1d\n#define    RTL8367C_VLAN_MSTI14_CTRL1_PORT10_STATE_OFFSET    4\n#define    RTL8367C_VLAN_MSTI14_CTRL1_PORT10_STATE_MASK    0x30\n#define    RTL8367C_VLAN_MSTI14_CTRL1_PORT9_STATE_OFFSET    2\n#define    RTL8367C_VLAN_MSTI14_CTRL1_PORT9_STATE_MASK    0xC\n#define    RTL8367C_VLAN_MSTI14_CTRL1_PORT8_STATE_OFFSET    0\n#define    RTL8367C_VLAN_MSTI14_CTRL1_PORT8_STATE_MASK    0x3\n\n#define    RTL8367C_REG_VLAN_MSTI15_CTRL0    0x0a1e\n#define    RTL8367C_VLAN_MSTI15_CTRL0_PORT7_STATE_OFFSET    14\n#define    RTL8367C_VLAN_MSTI15_CTRL0_PORT7_STATE_MASK    0xC000\n#define    RTL8367C_VLAN_MSTI15_CTRL0_PORT6_STATE_OFFSET    12\n#define    RTL8367C_VLAN_MSTI15_CTRL0_PORT6_STATE_MASK    0x3000\n#define    RTL8367C_VLAN_MSTI15_CTRL0_PORT5_STATE_OFFSET    10\n#define    RTL8367C_VLAN_MSTI15_CTRL0_PORT5_STATE_MASK    0xC00\n#define    RTL8367C_VLAN_MSTI15_CTRL0_PORT4_STATE_OFFSET    8\n#define    RTL8367C_VLAN_MSTI15_CTRL0_PORT4_STATE_MASK    0x300\n#define    RTL8367C_VLAN_MSTI15_CTRL0_PORT3_STATE_OFFSET    6\n#define    RTL8367C_VLAN_MSTI15_CTRL0_PORT3_STATE_MASK    0xC0\n#define    RTL8367C_VLAN_MSTI15_CTRL0_PORT2_STATE_OFFSET    4\n#define    RTL8367C_VLAN_MSTI15_CTRL0_PORT2_STATE_MASK    0x30\n#define    RTL8367C_VLAN_MSTI15_CTRL0_PORT1_STATE_OFFSET    2\n#define    RTL8367C_VLAN_MSTI15_CTRL0_PORT1_STATE_MASK    0xC\n#define    RTL8367C_VLAN_MSTI15_CTRL0_PORT0_STATE_OFFSET    0\n#define    RTL8367C_VLAN_MSTI15_CTRL0_PORT0_STATE_MASK    0x3\n\n#define    RTL8367C_REG_VLAN_MSTI15_CTRL1    0x0a1f\n#define    RTL8367C_VLAN_MSTI15_CTRL1_PORT10_STATE_OFFSET    4\n#define    RTL8367C_VLAN_MSTI15_CTRL1_PORT10_STATE_MASK    0x30\n#define    RTL8367C_VLAN_MSTI15_CTRL1_PORT9_STATE_OFFSET    2\n#define    RTL8367C_VLAN_MSTI15_CTRL1_PORT9_STATE_MASK    0xC\n#define    RTL8367C_VLAN_MSTI15_CTRL1_PORT8_STATE_OFFSET    0\n#define    RTL8367C_VLAN_MSTI15_CTRL1_PORT8_STATE_MASK    0x3\n\n#define    RTL8367C_REG_LUT_PORT0_LEARN_LIMITNO    0x0a20\n#define    RTL8367C_LUT_PORT0_LEARN_LIMITNO_OFFSET    0\n#define    RTL8367C_LUT_PORT0_LEARN_LIMITNO_MASK    0x1FFF\n\n#define    RTL8367C_REG_LUT_PORT1_LEARN_LIMITNO    0x0a21\n#define    RTL8367C_LUT_PORT1_LEARN_LIMITNO_OFFSET    0\n#define    RTL8367C_LUT_PORT1_LEARN_LIMITNO_MASK    0x1FFF\n\n#define    RTL8367C_REG_LUT_PORT2_LEARN_LIMITNO    0x0a22\n#define    RTL8367C_LUT_PORT2_LEARN_LIMITNO_OFFSET    0\n#define    RTL8367C_LUT_PORT2_LEARN_LIMITNO_MASK    0x1FFF\n\n#define    RTL8367C_REG_LUT_PORT3_LEARN_LIMITNO    0x0a23\n#define    RTL8367C_LUT_PORT3_LEARN_LIMITNO_OFFSET    0\n#define    RTL8367C_LUT_PORT3_LEARN_LIMITNO_MASK    0x1FFF\n\n#define    RTL8367C_REG_LUT_PORT4_LEARN_LIMITNO    0x0a24\n#define    RTL8367C_LUT_PORT4_LEARN_LIMITNO_OFFSET    0\n#define    RTL8367C_LUT_PORT4_LEARN_LIMITNO_MASK    0x1FFF\n\n#define    RTL8367C_REG_LUT_PORT5_LEARN_LIMITNO    0x0a25\n#define    RTL8367C_LUT_PORT5_LEARN_LIMITNO_OFFSET    0\n#define    RTL8367C_LUT_PORT5_LEARN_LIMITNO_MASK    0x1FFF\n\n#define    RTL8367C_REG_LUT_PORT6_LEARN_LIMITNO    0x0a26\n#define    RTL8367C_LUT_PORT6_LEARN_LIMITNO_OFFSET    0\n#define    RTL8367C_LUT_PORT6_LEARN_LIMITNO_MASK    0x1FFF\n\n#define    RTL8367C_REG_LUT_PORT7_LEARN_LIMITNO    0x0a27\n#define    RTL8367C_LUT_PORT7_LEARN_LIMITNO_OFFSET    0\n#define    RTL8367C_LUT_PORT7_LEARN_LIMITNO_MASK    0x1FFF\n\n#define    RTL8367C_REG_LUT_SYS_LEARN_LIMITNO    0x0a28\n#define    RTL8367C_LUT_SYS_LEARN_LIMITNO_OFFSET    0\n#define    RTL8367C_LUT_SYS_LEARN_LIMITNO_MASK    0x1FFF\n\n#define    RTL8367C_REG_LUT_LRN_SYS_LMT_CTRL    0x0a29\n#define    RTL8367C_LUT_SYSTEM_LEARN_PMASK1_OFFSET    12\n#define    RTL8367C_LUT_SYSTEM_LEARN_PMASK1_MASK    0x7000\n#define    RTL8367C_LUT_SYSTEM_LEARN_OVER_ACT_OFFSET    10\n#define    RTL8367C_LUT_SYSTEM_LEARN_OVER_ACT_MASK    0xC00\n#define    RTL8367C_LUT_SYSTEM_LEARN_PMASK_OFFSET    0\n#define    RTL8367C_LUT_SYSTEM_LEARN_PMASK_MASK    0xFF\n\n#define    RTL8367C_REG_LUT_PORT8_LEARN_LIMITNO    0x0a2a\n#define    RTL8367C_LUT_PORT8_LEARN_LIMITNO_OFFSET    0\n#define    RTL8367C_LUT_PORT8_LEARN_LIMITNO_MASK    0x1FFF\n\n#define    RTL8367C_REG_LUT_PORT9_LEARN_LIMITNO    0x0a2b\n#define    RTL8367C_LUT_PORT9_LEARN_LIMITNO_OFFSET    0\n#define    RTL8367C_LUT_PORT9_LEARN_LIMITNO_MASK    0x1FFF\n\n#define    RTL8367C_REG_LUT_PORT10_LEARN_LIMITNO    0x0a2c\n#define    RTL8367C_LUT_PORT10_LEARN_LIMITNO_OFFSET    0\n#define    RTL8367C_LUT_PORT10_LEARN_LIMITNO_MASK    0x1FFF\n\n#define    RTL8367C_REG_LUT_CFG    0x0a30\n#define    RTL8367C_AGE_SPEED_OFFSET    8\n#define    RTL8367C_AGE_SPEED_MASK    0x300\n#define    RTL8367C_BCAM_DISABLE_OFFSET    6\n#define    RTL8367C_BCAM_DISABLE_MASK    0x40\n#define    RTL8367C_LINKDOWN_AGEOUT_OFFSET    5\n#define    RTL8367C_LINKDOWN_AGEOUT_MASK    0x20\n#define    RTL8367C_LUT_IPMC_HASH_OFFSET    4\n#define    RTL8367C_LUT_IPMC_HASH_MASK    0x10\n#define    RTL8367C_LUT_IPMC_LOOKUP_OP_OFFSET    3\n#define    RTL8367C_LUT_IPMC_LOOKUP_OP_MASK    0x8\n#define    RTL8367C_AGE_TIMER_OFFSET    0\n#define    RTL8367C_AGE_TIMER_MASK    0x7\n\n#define    RTL8367C_REG_LUT_AGEOUT_CTRL    0x0a31\n#define    RTL8367C_LUT_AGEOUT_CTRL_OFFSET    0\n#define    RTL8367C_LUT_AGEOUT_CTRL_MASK    0x7FF\n\n#define    RTL8367C_REG_PORT_EFID_CTRL0    0x0a32\n#define    RTL8367C_PORT3_EFID_OFFSET    12\n#define    RTL8367C_PORT3_EFID_MASK    0x7000\n#define    RTL8367C_PORT2_EFID_OFFSET    8\n#define    RTL8367C_PORT2_EFID_MASK    0x700\n#define    RTL8367C_PORT1_EFID_OFFSET    4\n#define    RTL8367C_PORT1_EFID_MASK    0x70\n#define    RTL8367C_PORT0_EFID_OFFSET    0\n#define    RTL8367C_PORT0_EFID_MASK    0x7\n\n#define    RTL8367C_REG_PORT_EFID_CTRL1    0x0a33\n#define    RTL8367C_PORT7_EFID_OFFSET    12\n#define    RTL8367C_PORT7_EFID_MASK    0x7000\n#define    RTL8367C_PORT6_EFID_OFFSET    8\n#define    RTL8367C_PORT6_EFID_MASK    0x700\n#define    RTL8367C_PORT5_EFID_OFFSET    4\n#define    RTL8367C_PORT5_EFID_MASK    0x70\n#define    RTL8367C_PORT4_EFID_OFFSET    0\n#define    RTL8367C_PORT4_EFID_MASK    0x7\n\n#define    RTL8367C_REG_PORT_EFID_CTRL2    0x0a34\n#define    RTL8367C_PORT10_EFID_OFFSET    8\n#define    RTL8367C_PORT10_EFID_MASK    0x700\n#define    RTL8367C_PORT9_EFID_OFFSET    4\n#define    RTL8367C_PORT9_EFID_MASK    0x70\n#define    RTL8367C_PORT8_EFID_OFFSET    0\n#define    RTL8367C_PORT8_EFID_MASK    0x7\n\n#define    RTL8367C_REG_FORCE_FLUSH1    0x0a35\n#define    RTL8367C_BUSY_STATUS1_OFFSET    3\n#define    RTL8367C_BUSY_STATUS1_MASK    0x38\n#define    RTL8367C_PORTMASK1_OFFSET    0\n#define    RTL8367C_PORTMASK1_MASK    0x7\n\n#define    RTL8367C_REG_FORCE_FLUSH    0x0a36\n#define    RTL8367C_BUSY_STATUS_OFFSET    8\n#define    RTL8367C_BUSY_STATUS_MASK    0xFF00\n#define    RTL8367C_FORCE_FLUSH_PORTMASK_OFFSET    0\n#define    RTL8367C_FORCE_FLUSH_PORTMASK_MASK    0xFF\n\n#define    RTL8367C_REG_L2_FLUSH_CTRL1    0x0a37\n#define    RTL8367C_LUT_FLUSH_FID_OFFSET    12\n#define    RTL8367C_LUT_FLUSH_FID_MASK    0xF000\n#define    RTL8367C_LUT_FLUSH_VID_OFFSET    0\n#define    RTL8367C_LUT_FLUSH_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_L2_FLUSH_CTRL2    0x0a38\n#define    RTL8367C_LUT_FLUSH_TYPE_OFFSET    2\n#define    RTL8367C_LUT_FLUSH_TYPE_MASK    0x4\n#define    RTL8367C_LUT_FLUSH_MODE_OFFSET    0\n#define    RTL8367C_LUT_FLUSH_MODE_MASK    0x3\n\n#define    RTL8367C_REG_L2_FLUSH_CTRL3    0x0a39\n#define    RTL8367C_L2_FLUSH_CTRL3_OFFSET    0\n#define    RTL8367C_L2_FLUSH_CTRL3_MASK    0x1\n\n#define    RTL8367C_REG_LUT_CFG2    0x0a3a\n#define    RTL8367C_LUT_IPMC_FWD_RPORT_OFFSET    1\n#define    RTL8367C_LUT_IPMC_FWD_RPORT_MASK    0x2\n#define    RTL8367C_LUT_IPMC_VID_HASH_OFFSET    0\n#define    RTL8367C_LUT_IPMC_VID_HASH_MASK    0x1\n\n#define    RTL8367C_REG_FLUSH_STATUS    0x0a3f\n#define    RTL8367C_FLUSH_STATUS_OFFSET    0\n#define    RTL8367C_FLUSH_STATUS_MASK    0x1\n\n#define    RTL8367C_REG_STORM_BCAST    0x0a40\n#define    RTL8367C_STORM_BCAST_OFFSET    0\n#define    RTL8367C_STORM_BCAST_MASK    0x7FF\n\n#define    RTL8367C_REG_STORM_MCAST    0x0a41\n#define    RTL8367C_STORM_MCAST_OFFSET    0\n#define    RTL8367C_STORM_MCAST_MASK    0x7FF\n\n#define    RTL8367C_REG_STORM_UNKOWN_UCAST    0x0a42\n#define    RTL8367C_STORM_UNKOWN_UCAST_OFFSET    0\n#define    RTL8367C_STORM_UNKOWN_UCAST_MASK    0x7FF\n\n#define    RTL8367C_REG_STORM_UNKOWN_MCAST    0x0a43\n#define    RTL8367C_STORM_UNKOWN_MCAST_OFFSET    0\n#define    RTL8367C_STORM_UNKOWN_MCAST_MASK    0x7FF\n\n#define    RTL8367C_REG_STORM_BCAST_METER_CTRL0    0x0a44\n#define    RTL8367C_STORM_BCAST_METER_CTRL0_PORT1_METERIDX_OFFSET    8\n#define    RTL8367C_STORM_BCAST_METER_CTRL0_PORT1_METERIDX_MASK    0x3F00\n#define    RTL8367C_STORM_BCAST_METER_CTRL0_PORT0_METERIDX_OFFSET    0\n#define    RTL8367C_STORM_BCAST_METER_CTRL0_PORT0_METERIDX_MASK    0x3F\n\n#define    RTL8367C_REG_STORM_BCAST_METER_CTRL1    0x0a45\n#define    RTL8367C_STORM_BCAST_METER_CTRL1_PORT3_METERIDX_OFFSET    8\n#define    RTL8367C_STORM_BCAST_METER_CTRL1_PORT3_METERIDX_MASK    0x3F00\n#define    RTL8367C_STORM_BCAST_METER_CTRL1_PORT2_METERIDX_OFFSET    0\n#define    RTL8367C_STORM_BCAST_METER_CTRL1_PORT2_METERIDX_MASK    0x3F\n\n#define    RTL8367C_REG_STORM_BCAST_METER_CTRL2    0x0a46\n#define    RTL8367C_STORM_BCAST_METER_CTRL2_PORT5_METERIDX_OFFSET    8\n#define    RTL8367C_STORM_BCAST_METER_CTRL2_PORT5_METERIDX_MASK    0x3F00\n#define    RTL8367C_STORM_BCAST_METER_CTRL2_PORT4_METERIDX_OFFSET    0\n#define    RTL8367C_STORM_BCAST_METER_CTRL2_PORT4_METERIDX_MASK    0x3F\n\n#define    RTL8367C_REG_STORM_BCAST_METER_CTRL3    0x0a47\n#define    RTL8367C_STORM_BCAST_METER_CTRL3_PORT7_METERIDX_OFFSET    8\n#define    RTL8367C_STORM_BCAST_METER_CTRL3_PORT7_METERIDX_MASK    0x3F00\n#define    RTL8367C_STORM_BCAST_METER_CTRL3_PORT6_METERIDX_OFFSET    0\n#define    RTL8367C_STORM_BCAST_METER_CTRL3_PORT6_METERIDX_MASK    0x3F\n\n#define    RTL8367C_REG_STORM_BCAST_METER_CTRL4    0x0a48\n#define    RTL8367C_STORM_BCAST_METER_CTRL4_PORT9_METERIDX_OFFSET    8\n#define    RTL8367C_STORM_BCAST_METER_CTRL4_PORT9_METERIDX_MASK    0x3F00\n#define    RTL8367C_STORM_BCAST_METER_CTRL4_PORT8_METERIDX_OFFSET    0\n#define    RTL8367C_STORM_BCAST_METER_CTRL4_PORT8_METERIDX_MASK    0x3F\n\n#define    RTL8367C_REG_STORM_BCAST_METER_CTRL5    0x0a49\n#define    RTL8367C_STORM_BCAST_METER_CTRL5_OFFSET    0\n#define    RTL8367C_STORM_BCAST_METER_CTRL5_MASK    0x3F\n\n#define    RTL8367C_REG_STORM_MCAST_METER_CTRL0    0x0a4c\n#define    RTL8367C_STORM_MCAST_METER_CTRL0_PORT1_METERIDX_OFFSET    8\n#define    RTL8367C_STORM_MCAST_METER_CTRL0_PORT1_METERIDX_MASK    0x3F00\n#define    RTL8367C_STORM_MCAST_METER_CTRL0_PORT0_METERIDX_OFFSET    0\n#define    RTL8367C_STORM_MCAST_METER_CTRL0_PORT0_METERIDX_MASK    0x3F\n\n#define    RTL8367C_REG_STORM_MCAST_METER_CTRL1    0x0a4d\n#define    RTL8367C_STORM_MCAST_METER_CTRL1_PORT3_METERIDX_OFFSET    8\n#define    RTL8367C_STORM_MCAST_METER_CTRL1_PORT3_METERIDX_MASK    0x3F00\n#define    RTL8367C_STORM_MCAST_METER_CTRL1_PORT2_METERIDX_OFFSET    0\n#define    RTL8367C_STORM_MCAST_METER_CTRL1_PORT2_METERIDX_MASK    0x3F\n\n#define    RTL8367C_REG_STORM_MCAST_METER_CTRL2    0x0a4e\n#define    RTL8367C_STORM_MCAST_METER_CTRL2_PORT5_METERIDX_OFFSET    8\n#define    RTL8367C_STORM_MCAST_METER_CTRL2_PORT5_METERIDX_MASK    0x3F00\n#define    RTL8367C_STORM_MCAST_METER_CTRL2_PORT4_METERIDX_OFFSET    0\n#define    RTL8367C_STORM_MCAST_METER_CTRL2_PORT4_METERIDX_MASK    0x3F\n\n#define    RTL8367C_REG_STORM_MCAST_METER_CTRL3    0x0a4f\n#define    RTL8367C_STORM_MCAST_METER_CTRL3_PORT7_METERIDX_OFFSET    8\n#define    RTL8367C_STORM_MCAST_METER_CTRL3_PORT7_METERIDX_MASK    0x3F00\n#define    RTL8367C_STORM_MCAST_METER_CTRL3_PORT6_METERIDX_OFFSET    0\n#define    RTL8367C_STORM_MCAST_METER_CTRL3_PORT6_METERIDX_MASK    0x3F\n\n#define    RTL8367C_REG_STORM_MCAST_METER_CTRL4    0x0a50\n#define    RTL8367C_STORM_MCAST_METER_CTRL4_PORT9_METERIDX_OFFSET    8\n#define    RTL8367C_STORM_MCAST_METER_CTRL4_PORT9_METERIDX_MASK    0x3F00\n#define    RTL8367C_STORM_MCAST_METER_CTRL4_PORT8_METERIDX_OFFSET    0\n#define    RTL8367C_STORM_MCAST_METER_CTRL4_PORT8_METERIDX_MASK    0x3F\n\n#define    RTL8367C_REG_STORM_MCAST_METER_CTRL5    0x0a51\n#define    RTL8367C_STORM_MCAST_METER_CTRL5_OFFSET    0\n#define    RTL8367C_STORM_MCAST_METER_CTRL5_MASK    0x3F\n\n#define    RTL8367C_REG_STORM_UNDA_METER_CTRL0    0x0a54\n#define    RTL8367C_STORM_UNDA_METER_CTRL0_PORT1_METERIDX_OFFSET    8\n#define    RTL8367C_STORM_UNDA_METER_CTRL0_PORT1_METERIDX_MASK    0x3F00\n#define    RTL8367C_STORM_UNDA_METER_CTRL0_PORT0_METERIDX_OFFSET    0\n#define    RTL8367C_STORM_UNDA_METER_CTRL0_PORT0_METERIDX_MASK    0x3F\n\n#define    RTL8367C_REG_STORM_UNDA_METER_CTRL1    0x0a55\n#define    RTL8367C_STORM_UNDA_METER_CTRL1_PORT3_METERIDX_OFFSET    8\n#define    RTL8367C_STORM_UNDA_METER_CTRL1_PORT3_METERIDX_MASK    0x3F00\n#define    RTL8367C_STORM_UNDA_METER_CTRL1_PORT2_METERIDX_OFFSET    0\n#define    RTL8367C_STORM_UNDA_METER_CTRL1_PORT2_METERIDX_MASK    0x3F\n\n#define    RTL8367C_REG_STORM_UNDA_METER_CTRL2    0x0a56\n#define    RTL8367C_STORM_UNDA_METER_CTRL2_PORT5_METERIDX_OFFSET    8\n#define    RTL8367C_STORM_UNDA_METER_CTRL2_PORT5_METERIDX_MASK    0x3F00\n#define    RTL8367C_STORM_UNDA_METER_CTRL2_PORT4_METERIDX_OFFSET    0\n#define    RTL8367C_STORM_UNDA_METER_CTRL2_PORT4_METERIDX_MASK    0x3F\n\n#define    RTL8367C_REG_STORM_UNDA_METER_CTRL3    0x0a57\n#define    RTL8367C_STORM_UNDA_METER_CTRL3_PORT7_METERIDX_OFFSET    8\n#define    RTL8367C_STORM_UNDA_METER_CTRL3_PORT7_METERIDX_MASK    0x3F00\n#define    RTL8367C_STORM_UNDA_METER_CTRL3_PORT6_METERIDX_OFFSET    0\n#define    RTL8367C_STORM_UNDA_METER_CTRL3_PORT6_METERIDX_MASK    0x3F\n\n#define    RTL8367C_REG_STORM_UNDA_METER_CTRL4    0x0a58\n#define    RTL8367C_STORM_UNDA_METER_CTRL4_PORT9_METERIDX_OFFSET    8\n#define    RTL8367C_STORM_UNDA_METER_CTRL4_PORT9_METERIDX_MASK    0x3F00\n#define    RTL8367C_STORM_UNDA_METER_CTRL4_PORT8_METERIDX_OFFSET    0\n#define    RTL8367C_STORM_UNDA_METER_CTRL4_PORT8_METERIDX_MASK    0x3F\n\n#define    RTL8367C_REG_STORM_UNDA_METER_CTRL5    0x0a59\n#define    RTL8367C_STORM_UNDA_METER_CTRL5_OFFSET    0\n#define    RTL8367C_STORM_UNDA_METER_CTRL5_MASK    0x3F\n\n#define    RTL8367C_REG_STORM_UNMC_METER_CTRL0    0x0a5c\n#define    RTL8367C_STORM_UNMC_METER_CTRL0_PORT1_METERIDX_OFFSET    8\n#define    RTL8367C_STORM_UNMC_METER_CTRL0_PORT1_METERIDX_MASK    0x3F00\n#define    RTL8367C_STORM_UNMC_METER_CTRL0_PORT0_METERIDX_OFFSET    0\n#define    RTL8367C_STORM_UNMC_METER_CTRL0_PORT0_METERIDX_MASK    0x3F\n\n#define    RTL8367C_REG_STORM_UNMC_METER_CTRL1    0x0a5d\n#define    RTL8367C_STORM_UNMC_METER_CTRL1_PORT3_METERIDX_OFFSET    8\n#define    RTL8367C_STORM_UNMC_METER_CTRL1_PORT3_METERIDX_MASK    0x3F00\n#define    RTL8367C_STORM_UNMC_METER_CTRL1_PORT2_METERIDX_OFFSET    0\n#define    RTL8367C_STORM_UNMC_METER_CTRL1_PORT2_METERIDX_MASK    0x3F\n\n#define    RTL8367C_REG_STORM_UNMC_METER_CTRL2    0x0a5e\n#define    RTL8367C_STORM_UNMC_METER_CTRL2_PORT5_METERIDX_OFFSET    8\n#define    RTL8367C_STORM_UNMC_METER_CTRL2_PORT5_METERIDX_MASK    0x3F00\n#define    RTL8367C_STORM_UNMC_METER_CTRL2_PORT4_METERIDX_OFFSET    0\n#define    RTL8367C_STORM_UNMC_METER_CTRL2_PORT4_METERIDX_MASK    0x3F\n\n#define    RTL8367C_REG_STORM_UNMC_METER_CTRL3    0x0a5f\n#define    RTL8367C_STORM_UNMC_METER_CTRL3_PORT7_METERIDX_OFFSET    8\n#define    RTL8367C_STORM_UNMC_METER_CTRL3_PORT7_METERIDX_MASK    0x3F00\n#define    RTL8367C_STORM_UNMC_METER_CTRL3_PORT6_METERIDX_OFFSET    0\n#define    RTL8367C_STORM_UNMC_METER_CTRL3_PORT6_METERIDX_MASK    0x3F\n\n#define    RTL8367C_REG_STORM_EXT_CFG    0x0a60\n#define    RTL8367C_STORM_EXT_EN_PORTMASK_EXT_OFFSET    14\n#define    RTL8367C_STORM_EXT_EN_PORTMASK_EXT_MASK    0x4000\n#define    RTL8367C_STORM_UNKNOWN_MCAST_EXT_EN_OFFSET    13\n#define    RTL8367C_STORM_UNKNOWN_MCAST_EXT_EN_MASK    0x2000\n#define    RTL8367C_STORM_UNKNOWN_UCAST_EXT_EN_OFFSET    12\n#define    RTL8367C_STORM_UNKNOWN_UCAST_EXT_EN_MASK    0x1000\n#define    RTL8367C_STORM_MCAST_EXT_EN_OFFSET    11\n#define    RTL8367C_STORM_MCAST_EXT_EN_MASK    0x800\n#define    RTL8367C_STORM_BCAST_EXT_EN_OFFSET    10\n#define    RTL8367C_STORM_BCAST_EXT_EN_MASK    0x400\n#define    RTL8367C_STORM_EXT_EN_PORTMASK_OFFSET    0\n#define    RTL8367C_STORM_EXT_EN_PORTMASK_MASK    0x3FF\n\n#define    RTL8367C_REG_STORM_EXT_MTRIDX_CFG0    0x0a61\n#define    RTL8367C_MC_STORM_EXT_METERIDX_OFFSET    8\n#define    RTL8367C_MC_STORM_EXT_METERIDX_MASK    0x3F00\n#define    RTL8367C_BC_STORM_EXT_METERIDX_OFFSET    0\n#define    RTL8367C_BC_STORM_EXT_METERIDX_MASK    0x3F\n\n#define    RTL8367C_REG_STORM_EXT_MTRIDX_CFG1    0x0a62\n#define    RTL8367C_UNMC_STORM_EXT_METERIDX_OFFSET    8\n#define    RTL8367C_UNMC_STORM_EXT_METERIDX_MASK    0x3F00\n#define    RTL8367C_UNUC_STORM_EXT_METERIDX_OFFSET    0\n#define    RTL8367C_UNUC_STORM_EXT_METERIDX_MASK    0x3F\n\n#define    RTL8367C_REG_STORM_UNMC_METER_CTRL4    0x0a63\n#define    RTL8367C_STORM_UNMC_METER_CTRL4_PORT9_METERIDX_OFFSET    8\n#define    RTL8367C_STORM_UNMC_METER_CTRL4_PORT9_METERIDX_MASK    0x3F00\n#define    RTL8367C_STORM_UNMC_METER_CTRL4_PORT8_METERIDX_OFFSET    0\n#define    RTL8367C_STORM_UNMC_METER_CTRL4_PORT8_METERIDX_MASK    0x3F\n\n#define    RTL8367C_REG_STORM_UNMC_METER_CTRL5    0x0a64\n#define    RTL8367C_STORM_UNMC_METER_CTRL5_OFFSET    0\n#define    RTL8367C_STORM_UNMC_METER_CTRL5_MASK    0x3F\n\n#define    RTL8367C_REG_OAM_PARSER_CTRL0    0x0a70\n#define    RTL8367C_PORT7_PARACT_OFFSET    14\n#define    RTL8367C_PORT7_PARACT_MASK    0xC000\n#define    RTL8367C_PORT6_PARACT_OFFSET    12\n#define    RTL8367C_PORT6_PARACT_MASK    0x3000\n#define    RTL8367C_PORT5_PARACT_OFFSET    10\n#define    RTL8367C_PORT5_PARACT_MASK    0xC00\n#define    RTL8367C_PORT4_PARACT_OFFSET    8\n#define    RTL8367C_PORT4_PARACT_MASK    0x300\n#define    RTL8367C_PORT3_PARACT_OFFSET    6\n#define    RTL8367C_PORT3_PARACT_MASK    0xC0\n#define    RTL8367C_PORT2_PARACT_OFFSET    4\n#define    RTL8367C_PORT2_PARACT_MASK    0x30\n#define    RTL8367C_PORT1_PARACT_OFFSET    2\n#define    RTL8367C_PORT1_PARACT_MASK    0xC\n#define    RTL8367C_PORT0_PARACT_OFFSET    0\n#define    RTL8367C_PORT0_PARACT_MASK    0x3\n\n#define    RTL8367C_REG_OAM_PARSER_CTRL1    0x0a71\n#define    RTL8367C_PORT10_PARACT_OFFSET    4\n#define    RTL8367C_PORT10_PARACT_MASK    0x30\n#define    RTL8367C_PORT9_PARACT_OFFSET    2\n#define    RTL8367C_PORT9_PARACT_MASK    0xC\n#define    RTL8367C_PORT8_PARACT_OFFSET    0\n#define    RTL8367C_PORT8_PARACT_MASK    0x3\n\n#define    RTL8367C_REG_OAM_MULTIPLEXER_CTRL0    0x0a72\n#define    RTL8367C_PORT7_MULACT_OFFSET    14\n#define    RTL8367C_PORT7_MULACT_MASK    0xC000\n#define    RTL8367C_PORT6_MULACT_OFFSET    12\n#define    RTL8367C_PORT6_MULACT_MASK    0x3000\n#define    RTL8367C_PORT5_MULACT_OFFSET    10\n#define    RTL8367C_PORT5_MULACT_MASK    0xC00\n#define    RTL8367C_PORT4_MULACT_OFFSET    8\n#define    RTL8367C_PORT4_MULACT_MASK    0x300\n#define    RTL8367C_PORT3_MULACT_OFFSET    6\n#define    RTL8367C_PORT3_MULACT_MASK    0xC0\n#define    RTL8367C_PORT2_MULACT_OFFSET    4\n#define    RTL8367C_PORT2_MULACT_MASK    0x30\n#define    RTL8367C_PORT1_MULACT_OFFSET    2\n#define    RTL8367C_PORT1_MULACT_MASK    0xC\n#define    RTL8367C_PORT0_MULACT_OFFSET    0\n#define    RTL8367C_PORT0_MULACT_MASK    0x3\n\n#define    RTL8367C_REG_OAM_MULTIPLEXER_CTRL1    0x0a73\n#define    RTL8367C_PORT10_MULACT_OFFSET    4\n#define    RTL8367C_PORT10_MULACT_MASK    0x30\n#define    RTL8367C_PORT9_MULACT_OFFSET    2\n#define    RTL8367C_PORT9_MULACT_MASK    0xC\n#define    RTL8367C_PORT8_MULACT_OFFSET    0\n#define    RTL8367C_PORT8_MULACT_MASK    0x3\n\n#define    RTL8367C_REG_OAM_CTRL    0x0a74\n#define    RTL8367C_OAM_CTRL_OFFSET    0\n#define    RTL8367C_OAM_CTRL_MASK    0x1\n\n#define    RTL8367C_REG_DOT1X_PORT_ENABLE    0x0a80\n#define    RTL8367C_DOT1X_PORT_ENABLE_OFFSET    0\n#define    RTL8367C_DOT1X_PORT_ENABLE_MASK    0x7FF\n\n#define    RTL8367C_REG_DOT1X_MAC_ENABLE    0x0a81\n#define    RTL8367C_DOT1X_MAC_ENABLE_OFFSET    0\n#define    RTL8367C_DOT1X_MAC_ENABLE_MASK    0x7FF\n\n#define    RTL8367C_REG_DOT1X_PORT_AUTH    0x0a82\n#define    RTL8367C_DOT1X_PORT_AUTH_OFFSET    0\n#define    RTL8367C_DOT1X_PORT_AUTH_MASK    0x7FF\n\n#define    RTL8367C_REG_DOT1X_PORT_OPDIR    0x0a83\n#define    RTL8367C_DOT1X_PORT_OPDIR_OFFSET    0\n#define    RTL8367C_DOT1X_PORT_OPDIR_MASK    0x7FF\n\n#define    RTL8367C_REG_DOT1X_UNAUTH_ACT_W0    0x0a84\n#define    RTL8367C_DOT1X_PORT7_UNAUTHBH_OFFSET    14\n#define    RTL8367C_DOT1X_PORT7_UNAUTHBH_MASK    0xC000\n#define    RTL8367C_DOT1X_PORT6_UNAUTHBH_OFFSET    12\n#define    RTL8367C_DOT1X_PORT6_UNAUTHBH_MASK    0x3000\n#define    RTL8367C_DOT1X_PORT5_UNAUTHBH_OFFSET    10\n#define    RTL8367C_DOT1X_PORT5_UNAUTHBH_MASK    0xC00\n#define    RTL8367C_DOT1X_PORT4_UNAUTHBH_OFFSET    8\n#define    RTL8367C_DOT1X_PORT4_UNAUTHBH_MASK    0x300\n#define    RTL8367C_DOT1X_PORT3_UNAUTHBH_OFFSET    6\n#define    RTL8367C_DOT1X_PORT3_UNAUTHBH_MASK    0xC0\n#define    RTL8367C_DOT1X_PORT2_UNAUTHBH_OFFSET    4\n#define    RTL8367C_DOT1X_PORT2_UNAUTHBH_MASK    0x30\n#define    RTL8367C_DOT1X_PORT1_UNAUTHBH_OFFSET    2\n#define    RTL8367C_DOT1X_PORT1_UNAUTHBH_MASK    0xC\n#define    RTL8367C_DOT1X_PORT0_UNAUTHBH_OFFSET    0\n#define    RTL8367C_DOT1X_PORT0_UNAUTHBH_MASK    0x3\n\n#define    RTL8367C_REG_DOT1X_UNAUTH_ACT_W1    0x0a85\n#define    RTL8367C_DOT1X_PORT10_UNAUTHBH_OFFSET    4\n#define    RTL8367C_DOT1X_PORT10_UNAUTHBH_MASK    0x30\n#define    RTL8367C_DOT1X_PORT9_UNAUTHBH_OFFSET    2\n#define    RTL8367C_DOT1X_PORT9_UNAUTHBH_MASK    0xC\n#define    RTL8367C_DOT1X_PORT8_UNAUTHBH_OFFSET    0\n#define    RTL8367C_DOT1X_PORT8_UNAUTHBH_MASK    0x3\n\n#define    RTL8367C_REG_DOT1X_CFG    0x0a86\n#define    RTL8367C_DOT1X_GVOPDIR_OFFSET    6\n#define    RTL8367C_DOT1X_GVOPDIR_MASK    0x40\n#define    RTL8367C_DOT1X_MAC_OPDIR_OFFSET    5\n#define    RTL8367C_DOT1X_MAC_OPDIR_MASK    0x20\n#define    RTL8367C_DOT1X_GVIDX_OFFSET    0\n#define    RTL8367C_DOT1X_GVIDX_MASK    0x1F\n\n#define    RTL8367C_REG_L2_LRN_CNT_CTRL0    0x0a87\n#define    RTL8367C_L2_LRN_CNT_CTRL0_OFFSET    0\n#define    RTL8367C_L2_LRN_CNT_CTRL0_MASK    0x1FFF\n\n#define    RTL8367C_REG_L2_LRN_CNT_CTRL1    0x0a88\n#define    RTL8367C_L2_LRN_CNT_CTRL1_OFFSET    0\n#define    RTL8367C_L2_LRN_CNT_CTRL1_MASK    0x1FFF\n\n#define    RTL8367C_REG_L2_LRN_CNT_CTRL2    0x0a89\n#define    RTL8367C_L2_LRN_CNT_CTRL2_OFFSET    0\n#define    RTL8367C_L2_LRN_CNT_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_L2_LRN_CNT_CTRL3    0x0a8a\n#define    RTL8367C_L2_LRN_CNT_CTRL3_OFFSET    0\n#define    RTL8367C_L2_LRN_CNT_CTRL3_MASK    0x1FFF\n\n#define    RTL8367C_REG_L2_LRN_CNT_CTRL4    0x0a8b\n#define    RTL8367C_L2_LRN_CNT_CTRL4_OFFSET    0\n#define    RTL8367C_L2_LRN_CNT_CTRL4_MASK    0x1FFF\n\n#define    RTL8367C_REG_L2_LRN_CNT_CTRL5    0x0a8c\n#define    RTL8367C_L2_LRN_CNT_CTRL5_OFFSET    0\n#define    RTL8367C_L2_LRN_CNT_CTRL5_MASK    0x1FFF\n\n#define    RTL8367C_REG_L2_LRN_CNT_CTRL6    0x0a8d\n#define    RTL8367C_L2_LRN_CNT_CTRL6_OFFSET    0\n#define    RTL8367C_L2_LRN_CNT_CTRL6_MASK    0x1FFF\n\n#define    RTL8367C_REG_L2_LRN_CNT_CTRL7    0x0a8e\n#define    RTL8367C_L2_LRN_CNT_CTRL7_OFFSET    0\n#define    RTL8367C_L2_LRN_CNT_CTRL7_MASK    0x1FFF\n\n#define    RTL8367C_REG_L2_LRN_CNT_CTRL8    0x0a8f\n#define    RTL8367C_L2_LRN_CNT_CTRL8_OFFSET    0\n#define    RTL8367C_L2_LRN_CNT_CTRL8_MASK    0x1FFF\n\n#define    RTL8367C_REG_L2_LRN_CNT_CTRL9    0x0a90\n#define    RTL8367C_L2_LRN_CNT_CTRL9_OFFSET    0\n#define    RTL8367C_L2_LRN_CNT_CTRL9_MASK    0x1FFF\n\n#define    RTL8367C_REG_L2_LRN_CNT_CTRL10    0x0a92\n#define    RTL8367C_L2_LRN_CNT_CTRL10_OFFSET    0\n#define    RTL8367C_L2_LRN_CNT_CTRL10_MASK    0x1FFF\n\n#define    RTL8367C_REG_LUT_LRN_UNDER_STATUS    0x0a91\n#define    RTL8367C_LUT_LRN_UNDER_STATUS_OFFSET    0\n#define    RTL8367C_LUT_LRN_UNDER_STATUS_MASK    0x7FF\n\n#define    RTL8367C_REG_L2_SA_MOVING_FORBID    0x0aa0\n#define    RTL8367C_L2_SA_MOVING_FORBID_OFFSET    0\n#define    RTL8367C_L2_SA_MOVING_FORBID_MASK    0x7FF\n\n#define    RTL8367C_REG_DRPORT_LEARN_CTRL    0x0aa1\n#define    RTL8367C_FORBID1_OFFSET    1\n#define    RTL8367C_FORBID1_MASK    0x2\n#define    RTL8367C_FORBID0_OFFSET    0\n#define    RTL8367C_FORBID0_MASK    0x1\n\n#define    RTL8367C_REG_L2_DUMMY02    0x0aa2\n\n#define    RTL8367C_REG_L2_DUMMY03    0x0aa3\n\n#define    RTL8367C_REG_L2_DUMMY04    0x0aa4\n\n#define    RTL8367C_REG_L2_DUMMY05    0x0aa5\n\n#define    RTL8367C_REG_L2_DUMMY06    0x0aa6\n\n#define    RTL8367C_REG_L2_DUMMY07    0x0aa7\n\n#define    RTL8367C_REG_IPMC_GROUP_PMSK_00    0x0AC0\n#define    RTL8367C_IPMC_GROUP_PMSK_00_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_PMSK_00_MASK    0x7FF\n\n#define    RTL8367C_REG_IPMC_GROUP_PMSK_01    0x0AC1\n#define    RTL8367C_IPMC_GROUP_PMSK_01_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_PMSK_01_MASK    0x7FF\n\n#define    RTL8367C_REG_IPMC_GROUP_PMSK_02    0x0AC2\n#define    RTL8367C_IPMC_GROUP_PMSK_02_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_PMSK_02_MASK    0x7FF\n\n#define    RTL8367C_REG_IPMC_GROUP_PMSK_03    0x0AC3\n#define    RTL8367C_IPMC_GROUP_PMSK_03_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_PMSK_03_MASK    0x7FF\n\n#define    RTL8367C_REG_IPMC_GROUP_PMSK_04    0x0AC4\n#define    RTL8367C_IPMC_GROUP_PMSK_04_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_PMSK_04_MASK    0x7FF\n\n#define    RTL8367C_REG_IPMC_GROUP_PMSK_05    0x0AC5\n#define    RTL8367C_IPMC_GROUP_PMSK_05_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_PMSK_05_MASK    0x7FF\n\n#define    RTL8367C_REG_IPMC_GROUP_PMSK_06    0x0AC6\n#define    RTL8367C_IPMC_GROUP_PMSK_06_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_PMSK_06_MASK    0x7FF\n\n#define    RTL8367C_REG_IPMC_GROUP_PMSK_07    0x0AC7\n#define    RTL8367C_IPMC_GROUP_PMSK_07_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_PMSK_07_MASK    0x7FF\n\n#define    RTL8367C_REG_IPMC_GROUP_PMSK_08    0x0AC8\n#define    RTL8367C_IPMC_GROUP_PMSK_08_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_PMSK_08_MASK    0x7FF\n\n#define    RTL8367C_REG_IPMC_GROUP_PMSK_09    0x0AC9\n#define    RTL8367C_IPMC_GROUP_PMSK_09_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_PMSK_09_MASK    0x7FF\n\n#define    RTL8367C_REG_IPMC_GROUP_PMSK_10    0x0ACA\n#define    RTL8367C_IPMC_GROUP_PMSK_10_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_PMSK_10_MASK    0x7FF\n\n#define    RTL8367C_REG_IPMC_GROUP_PMSK_11    0x0ACB\n#define    RTL8367C_IPMC_GROUP_PMSK_11_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_PMSK_11_MASK    0x7FF\n\n#define    RTL8367C_REG_IPMC_GROUP_PMSK_12    0x0ACC\n#define    RTL8367C_IPMC_GROUP_PMSK_12_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_PMSK_12_MASK    0x7FF\n\n#define    RTL8367C_REG_IPMC_GROUP_PMSK_13    0x0ACD\n#define    RTL8367C_IPMC_GROUP_PMSK_13_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_PMSK_13_MASK    0x7FF\n\n#define    RTL8367C_REG_IPMC_GROUP_PMSK_14    0x0ACE\n#define    RTL8367C_IPMC_GROUP_PMSK_14_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_PMSK_14_MASK    0x7FF\n\n#define    RTL8367C_REG_IPMC_GROUP_PMSK_15    0x0ACF\n#define    RTL8367C_IPMC_GROUP_PMSK_15_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_PMSK_15_MASK    0x7FF\n\n#define    RTL8367C_REG_IPMC_GROUP_PMSK_16    0x0AD0\n#define    RTL8367C_IPMC_GROUP_PMSK_16_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_PMSK_16_MASK    0x7FF\n\n#define    RTL8367C_REG_IPMC_GROUP_PMSK_17    0x0AD1\n#define    RTL8367C_IPMC_GROUP_PMSK_17_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_PMSK_17_MASK    0x7FF\n\n#define    RTL8367C_REG_IPMC_GROUP_PMSK_18    0x0AD2\n#define    RTL8367C_IPMC_GROUP_PMSK_18_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_PMSK_18_MASK    0x7FF\n\n#define    RTL8367C_REG_IPMC_GROUP_PMSK_19    0x0AD3\n#define    RTL8367C_IPMC_GROUP_PMSK_19_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_PMSK_19_MASK    0x7FF\n\n#define    RTL8367C_REG_IPMC_GROUP_PMSK_20    0x0AD4\n#define    RTL8367C_IPMC_GROUP_PMSK_20_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_PMSK_20_MASK    0x7FF\n\n#define    RTL8367C_REG_IPMC_GROUP_PMSK_21    0x0AD5\n#define    RTL8367C_IPMC_GROUP_PMSK_21_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_PMSK_21_MASK    0x7FF\n\n#define    RTL8367C_REG_IPMC_GROUP_PMSK_22    0x0AD6\n#define    RTL8367C_IPMC_GROUP_PMSK_22_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_PMSK_22_MASK    0x7FF\n\n#define    RTL8367C_REG_IPMC_GROUP_PMSK_23    0x0AD7\n#define    RTL8367C_IPMC_GROUP_PMSK_23_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_PMSK_23_MASK    0x7FF\n\n#define    RTL8367C_REG_IPMC_GROUP_PMSK_24    0x0AD8\n#define    RTL8367C_IPMC_GROUP_PMSK_24_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_PMSK_24_MASK    0x7FF\n\n#define    RTL8367C_REG_IPMC_GROUP_PMSK_25    0x0AD9\n#define    RTL8367C_IPMC_GROUP_PMSK_25_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_PMSK_25_MASK    0x7FF\n\n#define    RTL8367C_REG_IPMC_GROUP_PMSK_26    0x0ADA\n#define    RTL8367C_IPMC_GROUP_PMSK_26_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_PMSK_26_MASK    0x7FF\n\n#define    RTL8367C_REG_IPMC_GROUP_PMSK_27    0x0ADB\n#define    RTL8367C_IPMC_GROUP_PMSK_27_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_PMSK_27_MASK    0x7FF\n\n#define    RTL8367C_REG_IPMC_GROUP_PMSK_28    0x0ADC\n#define    RTL8367C_IPMC_GROUP_PMSK_28_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_PMSK_28_MASK    0x7FF\n\n#define    RTL8367C_REG_IPMC_GROUP_PMSK_29    0x0ADD\n#define    RTL8367C_IPMC_GROUP_PMSK_29_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_PMSK_29_MASK    0x7FF\n\n#define    RTL8367C_REG_IPMC_GROUP_PMSK_30    0x0ADE\n#define    RTL8367C_IPMC_GROUP_PMSK_30_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_PMSK_30_MASK    0x7FF\n\n#define    RTL8367C_REG_IPMC_GROUP_PMSK_31    0x0ADF\n#define    RTL8367C_IPMC_GROUP_PMSK_31_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_PMSK_31_MASK    0x7FF\n\n#define    RTL8367C_REG_IPMC_GROUP_PMSK_32    0x0AE0\n#define    RTL8367C_IPMC_GROUP_PMSK_32_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_PMSK_32_MASK    0x7FF\n\n#define    RTL8367C_REG_IPMC_GROUP_PMSK_33    0x0AE1\n#define    RTL8367C_IPMC_GROUP_PMSK_33_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_PMSK_33_MASK    0x7FF\n\n#define    RTL8367C_REG_IPMC_GROUP_PMSK_34    0x0AE2\n#define    RTL8367C_IPMC_GROUP_PMSK_34_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_PMSK_34_MASK    0x7FF\n\n#define    RTL8367C_REG_IPMC_GROUP_PMSK_35    0x0AE3\n#define    RTL8367C_IPMC_GROUP_PMSK_35_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_PMSK_35_MASK    0x7FF\n\n#define    RTL8367C_REG_IPMC_GROUP_PMSK_36    0x0AE4\n#define    RTL8367C_IPMC_GROUP_PMSK_36_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_PMSK_36_MASK    0x7FF\n\n#define    RTL8367C_REG_IPMC_GROUP_PMSK_37    0x0AE5\n#define    RTL8367C_IPMC_GROUP_PMSK_37_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_PMSK_37_MASK    0x7FF\n\n#define    RTL8367C_REG_IPMC_GROUP_PMSK_38    0x0AE6\n#define    RTL8367C_IPMC_GROUP_PMSK_38_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_PMSK_38_MASK    0x7FF\n\n#define    RTL8367C_REG_IPMC_GROUP_PMSK_39    0x0AE7\n#define    RTL8367C_IPMC_GROUP_PMSK_39_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_PMSK_39_MASK    0x7FF\n\n#define    RTL8367C_REG_IPMC_GROUP_PMSK_40    0x0AE8\n#define    RTL8367C_IPMC_GROUP_PMSK_40_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_PMSK_40_MASK    0x7FF\n\n#define    RTL8367C_REG_IPMC_GROUP_PMSK_41    0x0AE9\n#define    RTL8367C_IPMC_GROUP_PMSK_41_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_PMSK_41_MASK    0x7FF\n\n#define    RTL8367C_REG_IPMC_GROUP_PMSK_42    0x0AEA\n#define    RTL8367C_IPMC_GROUP_PMSK_42_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_PMSK_42_MASK    0x7FF\n\n#define    RTL8367C_REG_IPMC_GROUP_PMSK_43    0x0AEB\n#define    RTL8367C_IPMC_GROUP_PMSK_43_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_PMSK_43_MASK    0x7FF\n\n#define    RTL8367C_REG_IPMC_GROUP_PMSK_44    0x0AEC\n#define    RTL8367C_IPMC_GROUP_PMSK_44_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_PMSK_44_MASK    0x7FF\n\n#define    RTL8367C_REG_IPMC_GROUP_PMSK_45    0x0AED\n#define    RTL8367C_IPMC_GROUP_PMSK_45_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_PMSK_45_MASK    0x7FF\n\n#define    RTL8367C_REG_IPMC_GROUP_PMSK_46    0x0AEE\n#define    RTL8367C_IPMC_GROUP_PMSK_46_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_PMSK_46_MASK    0x7FF\n\n#define    RTL8367C_REG_IPMC_GROUP_PMSK_47    0x0AEF\n#define    RTL8367C_IPMC_GROUP_PMSK_47_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_PMSK_47_MASK    0x7FF\n\n#define    RTL8367C_REG_IPMC_GROUP_PMSK_48    0x0AF0\n#define    RTL8367C_IPMC_GROUP_PMSK_48_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_PMSK_48_MASK    0x7FF\n\n#define    RTL8367C_REG_IPMC_GROUP_PMSK_49    0x0AF1\n#define    RTL8367C_IPMC_GROUP_PMSK_49_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_PMSK_49_MASK    0x7FF\n\n#define    RTL8367C_REG_IPMC_GROUP_PMSK_50    0x0AF2\n#define    RTL8367C_IPMC_GROUP_PMSK_50_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_PMSK_50_MASK    0x7FF\n\n#define    RTL8367C_REG_IPMC_GROUP_PMSK_51    0x0AF3\n#define    RTL8367C_IPMC_GROUP_PMSK_51_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_PMSK_51_MASK    0x7FF\n\n#define    RTL8367C_REG_IPMC_GROUP_PMSK_52    0x0AF4\n#define    RTL8367C_IPMC_GROUP_PMSK_52_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_PMSK_52_MASK    0x7FF\n\n#define    RTL8367C_REG_IPMC_GROUP_PMSK_53    0x0AF5\n#define    RTL8367C_IPMC_GROUP_PMSK_53_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_PMSK_53_MASK    0x7FF\n\n#define    RTL8367C_REG_IPMC_GROUP_PMSK_54    0x0AF6\n#define    RTL8367C_IPMC_GROUP_PMSK_54_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_PMSK_54_MASK    0x7FF\n\n#define    RTL8367C_REG_IPMC_GROUP_PMSK_55    0x0AF7\n#define    RTL8367C_IPMC_GROUP_PMSK_55_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_PMSK_55_MASK    0x7FF\n\n#define    RTL8367C_REG_IPMC_GROUP_PMSK_56    0x0AF8\n#define    RTL8367C_IPMC_GROUP_PMSK_56_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_PMSK_56_MASK    0x7FF\n\n#define    RTL8367C_REG_IPMC_GROUP_PMSK_57    0x0AF9\n#define    RTL8367C_IPMC_GROUP_PMSK_57_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_PMSK_57_MASK    0x7FF\n\n#define    RTL8367C_REG_IPMC_GROUP_PMSK_58    0x0AFA\n#define    RTL8367C_IPMC_GROUP_PMSK_58_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_PMSK_58_MASK    0x7FF\n\n#define    RTL8367C_REG_IPMC_GROUP_PMSK_59    0x0AFB\n#define    RTL8367C_IPMC_GROUP_PMSK_59_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_PMSK_59_MASK    0x7FF\n\n#define    RTL8367C_REG_IPMC_GROUP_PMSK_60    0x0AFC\n#define    RTL8367C_IPMC_GROUP_PMSK_60_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_PMSK_60_MASK    0x7FF\n\n#define    RTL8367C_REG_IPMC_GROUP_PMSK_61    0x0AFD\n#define    RTL8367C_IPMC_GROUP_PMSK_61_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_PMSK_61_MASK    0x7FF\n\n#define    RTL8367C_REG_IPMC_GROUP_PMSK_62    0x0AFE\n#define    RTL8367C_IPMC_GROUP_PMSK_62_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_PMSK_62_MASK    0x7FF\n\n#define    RTL8367C_REG_IPMC_GROUP_PMSK_63    0x0AFF\n#define    RTL8367C_IPMC_GROUP_PMSK_63_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_PMSK_63_MASK    0x7FF\n\n/* (16'h0b00)mltvlan_reg */\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY0_CTRL0    0x0b00\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY0_CTRL0_VALID_OFFSET    7\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY0_CTRL0_VALID_MASK    0x80\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY0_CTRL0_FORMAT_OFFSET    6\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY0_CTRL0_FORMAT_MASK    0x40\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY0_CTRL0_SVIDX_OFFSET    0\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY0_CTRL0_SVIDX_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY0_CTRL1    0x0b01\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY0_CTRL2    0x0b02\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY0_CTRL3    0x0b03\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY0_CTRL4    0x0b04\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY1_CTRL0    0x0b05\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY1_CTRL0_VALID_OFFSET    7\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY1_CTRL0_VALID_MASK    0x80\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY1_CTRL0_FORMAT_OFFSET    6\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY1_CTRL0_FORMAT_MASK    0x40\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY1_CTRL0_SVIDX_OFFSET    0\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY1_CTRL0_SVIDX_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY1_CTRL1    0x0b06\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY1_CTRL2    0x0b07\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY1_CTRL3    0x0b08\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY1_CTRL4    0x0b09\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY2_CTRL0    0x0b0a\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY2_CTRL0_VALID_OFFSET    7\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY2_CTRL0_VALID_MASK    0x80\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY2_CTRL0_FORMAT_OFFSET    6\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY2_CTRL0_FORMAT_MASK    0x40\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY2_CTRL0_SVIDX_OFFSET    0\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY2_CTRL0_SVIDX_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY2_CTRL1    0x0b0b\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY2_CTRL2    0x0b0c\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY2_CTRL3    0x0b0d\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY2_CTRL4    0x0b0e\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY3_CTRL0    0x0b0f\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY3_CTRL0_VALID_OFFSET    7\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY3_CTRL0_VALID_MASK    0x80\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY3_CTRL0_FORMAT_OFFSET    6\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY3_CTRL0_FORMAT_MASK    0x40\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY3_CTRL0_SVIDX_OFFSET    0\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY3_CTRL0_SVIDX_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY3_CTRL1    0x0b10\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY3_CTRL2    0x0b11\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY3_CTRL3    0x0b12\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY3_CTRL4    0x0b13\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY4_CTRL0    0x0b14\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY4_CTRL0_VALID_OFFSET    7\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY4_CTRL0_VALID_MASK    0x80\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY4_CTRL0_FORMAT_OFFSET    6\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY4_CTRL0_FORMAT_MASK    0x40\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY4_CTRL0_SVIDX_OFFSET    0\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY4_CTRL0_SVIDX_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY4_CTRL1    0x0b15\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY4_CTRL2    0x0b16\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY4_CTRL3    0x0b17\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY4_CTRL4    0x0b18\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY5_CTRL0    0x0b19\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY5_CTRL0_VALID_OFFSET    7\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY5_CTRL0_VALID_MASK    0x80\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY5_CTRL0_FORMAT_OFFSET    6\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY5_CTRL0_FORMAT_MASK    0x40\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY5_CTRL0_SVIDX_OFFSET    0\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY5_CTRL0_SVIDX_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY5_CTRL1    0x0b1a\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY5_CTRL2    0x0b1b\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY5_CTRL3    0x0b1c\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY5_CTRL4    0x0b1d\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY6_CTRL0    0x0b1e\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY6_CTRL0_VALID_OFFSET    7\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY6_CTRL0_VALID_MASK    0x80\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY6_CTRL0_FORMAT_OFFSET    6\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY6_CTRL0_FORMAT_MASK    0x40\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY6_CTRL0_SVIDX_OFFSET    0\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY6_CTRL0_SVIDX_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY6_CTRL1    0x0b1f\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY6_CTRL2    0x0b20\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY6_CTRL3    0x0b21\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY6_CTRL4    0x0b22\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY7_CTRL0    0x0b23\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY7_CTRL0_VALID_OFFSET    7\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY7_CTRL0_VALID_MASK    0x80\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY7_CTRL0_FORMAT_OFFSET    6\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY7_CTRL0_FORMAT_MASK    0x40\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY7_CTRL0_SVIDX_OFFSET    0\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY7_CTRL0_SVIDX_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY7_CTRL1    0x0b24\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY7_CTRL2    0x0b25\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY7_CTRL3    0x0b26\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY7_CTRL4    0x0b27\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY8_CTRL0    0x0b28\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY8_CTRL0_VALID_OFFSET    7\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY8_CTRL0_VALID_MASK    0x80\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY8_CTRL0_FORMAT_OFFSET    6\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY8_CTRL0_FORMAT_MASK    0x40\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY8_CTRL0_SVIDX_OFFSET    0\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY8_CTRL0_SVIDX_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY8_CTRL1    0x0b29\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY8_CTRL2    0x0b2a\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY8_CTRL3    0x0b2b\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY8_CTRL4    0x0b2c\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY9_CTRL0    0x0b2d\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY9_CTRL0_VALID_OFFSET    7\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY9_CTRL0_VALID_MASK    0x80\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY9_CTRL0_FORMAT_OFFSET    6\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY9_CTRL0_FORMAT_MASK    0x40\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY9_CTRL0_SVIDX_OFFSET    0\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY9_CTRL0_SVIDX_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY9_CTRL1    0x0b2e\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY9_CTRL2    0x0b2f\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY9_CTRL3    0x0b30\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY9_CTRL4    0x0b31\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY10_CTRL0    0x0b32\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY10_CTRL0_VALID_OFFSET    7\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY10_CTRL0_VALID_MASK    0x80\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY10_CTRL0_FORMAT_OFFSET    6\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY10_CTRL0_FORMAT_MASK    0x40\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY10_CTRL0_SVIDX_OFFSET    0\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY10_CTRL0_SVIDX_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY10_CTRL1    0x0b33\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY10_CTRL2    0x0b34\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY10_CTRL3    0x0b35\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY10_CTRL4    0x0b36\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY11_CTRL0    0x0b37\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY11_CTRL0_VALID_OFFSET    7\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY11_CTRL0_VALID_MASK    0x80\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY11_CTRL0_FORMAT_OFFSET    6\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY11_CTRL0_FORMAT_MASK    0x40\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY11_CTRL0_SVIDX_OFFSET    0\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY11_CTRL0_SVIDX_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY11_CTRL1    0x0b38\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY11_CTRL2    0x0b39\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY11_CTRL3    0x0b3a\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY11_CTRL4    0x0b3b\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY12_CTRL0    0x0b3c\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY12_CTRL0_VALID_OFFSET    7\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY12_CTRL0_VALID_MASK    0x80\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY12_CTRL0_FORMAT_OFFSET    6\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY12_CTRL0_FORMAT_MASK    0x40\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY12_CTRL0_SVIDX_OFFSET    0\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY12_CTRL0_SVIDX_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY12_CTRL1    0x0b3d\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY12_CTRL2    0x0b3e\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY12_CTRL3    0x0b3f\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY12_CTRL4    0x0b40\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY13_CTRL0    0x0b41\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY13_CTRL0_VALID_OFFSET    7\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY13_CTRL0_VALID_MASK    0x80\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY13_CTRL0_FORMAT_OFFSET    6\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY13_CTRL0_FORMAT_MASK    0x40\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY13_CTRL0_SVIDX_OFFSET    0\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY13_CTRL0_SVIDX_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY13_CTRL1    0x0b42\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY13_CTRL2    0x0b43\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY13_CTRL3    0x0b44\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY13_CTRL4    0x0b45\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY14_CTRL0    0x0b46\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY14_CTRL0_VALID_OFFSET    7\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY14_CTRL0_VALID_MASK    0x80\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY14_CTRL0_FORMAT_OFFSET    6\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY14_CTRL0_FORMAT_MASK    0x40\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY14_CTRL0_SVIDX_OFFSET    0\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY14_CTRL0_SVIDX_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY14_CTRL1    0x0b47\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY14_CTRL2    0x0b48\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY14_CTRL3    0x0b49\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY14_CTRL4    0x0b4a\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY15_CTRL0    0x0b4b\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY15_CTRL0_VALID_OFFSET    7\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY15_CTRL0_VALID_MASK    0x80\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY15_CTRL0_FORMAT_OFFSET    6\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY15_CTRL0_FORMAT_MASK    0x40\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY15_CTRL0_SVIDX_OFFSET    0\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY15_CTRL0_SVIDX_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY15_CTRL1    0x0b4c\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY15_CTRL2    0x0b4d\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY15_CTRL3    0x0b4e\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY15_CTRL4    0x0b4f\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY16_CTRL0    0x0b50\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY16_CTRL0_VALID_OFFSET    7\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY16_CTRL0_VALID_MASK    0x80\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY16_CTRL0_FORMAT_OFFSET    6\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY16_CTRL0_FORMAT_MASK    0x40\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY16_CTRL0_SVIDX_OFFSET    0\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY16_CTRL0_SVIDX_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY16_CTRL1    0x0b51\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY16_CTRL2    0x0b52\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY16_CTRL3    0x0b53\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY16_CTRL4    0x0b54\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY17_CTRL0    0x0b55\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY17_CTRL0_VALID_OFFSET    7\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY17_CTRL0_VALID_MASK    0x80\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY17_CTRL0_FORMAT_OFFSET    6\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY17_CTRL0_FORMAT_MASK    0x40\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY17_CTRL0_SVIDX_OFFSET    0\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY17_CTRL0_SVIDX_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY17_CTRL1    0x0b56\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY17_CTRL2    0x0b57\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY17_CTRL3    0x0b58\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY17_CTRL4    0x0b59\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY18_CTRL0    0x0b5a\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY18_CTRL0_VALID_OFFSET    7\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY18_CTRL0_VALID_MASK    0x80\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY18_CTRL0_FORMAT_OFFSET    6\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY18_CTRL0_FORMAT_MASK    0x40\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY18_CTRL0_SVIDX_OFFSET    0\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY18_CTRL0_SVIDX_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY18_CTRL1    0x0b5b\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY18_CTRL2    0x0b5c\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY18_CTRL3    0x0b5d\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY18_CTRL4    0x0b5e\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY19_CTRL0    0x0b5f\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY19_CTRL0_VALID_OFFSET    7\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY19_CTRL0_VALID_MASK    0x80\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY19_CTRL0_FORMAT_OFFSET    6\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY19_CTRL0_FORMAT_MASK    0x40\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY19_CTRL0_SVIDX_OFFSET    0\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY19_CTRL0_SVIDX_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY19_CTRL1    0x0b60\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY19_CTRL2    0x0b61\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY19_CTRL3    0x0b62\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY19_CTRL4    0x0b63\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY20_CTRL0    0x0b64\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY20_CTRL0_VALID_OFFSET    7\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY20_CTRL0_VALID_MASK    0x80\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY20_CTRL0_FORMAT_OFFSET    6\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY20_CTRL0_FORMAT_MASK    0x40\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY20_CTRL0_SVIDX_OFFSET    0\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY20_CTRL0_SVIDX_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY20_CTRL1    0x0b65\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY20_CTRL2    0x0b66\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY20_CTRL3    0x0b67\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY20_CTRL4    0x0b68\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY21_CTRL0    0x0b69\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY21_CTRL0_VALID_OFFSET    7\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY21_CTRL0_VALID_MASK    0x80\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY21_CTRL0_FORMAT_OFFSET    6\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY21_CTRL0_FORMAT_MASK    0x40\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY21_CTRL0_SVIDX_OFFSET    0\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY21_CTRL0_SVIDX_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY21_CTRL1    0x0b6a\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY21_CTRL2    0x0b6b\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY21_CTRL3    0x0b6c\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY21_CTRL4    0x0b6d\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY22_CTRL0    0x0b6e\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY22_CTRL0_VALID_OFFSET    7\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY22_CTRL0_VALID_MASK    0x80\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY22_CTRL0_FORMAT_OFFSET    6\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY22_CTRL0_FORMAT_MASK    0x40\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY22_CTRL0_SVIDX_OFFSET    0\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY22_CTRL0_SVIDX_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY22_CTRL1    0x0b6f\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY22_CTRL2    0x0b70\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY22_CTRL3    0x0b71\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY22_CTRL4    0x0b72\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY23_CTRL0    0x0b73\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY23_CTRL0_VALID_OFFSET    7\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY23_CTRL0_VALID_MASK    0x80\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY23_CTRL0_FORMAT_OFFSET    6\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY23_CTRL0_FORMAT_MASK    0x40\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY23_CTRL0_SVIDX_OFFSET    0\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY23_CTRL0_SVIDX_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY23_CTRL1    0x0b74\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY23_CTRL2    0x0b75\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY23_CTRL3    0x0b76\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY23_CTRL4    0x0b77\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY24_CTRL0    0x0b78\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY24_CTRL0_VALID_OFFSET    7\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY24_CTRL0_VALID_MASK    0x80\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY24_CTRL0_FORMAT_OFFSET    6\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY24_CTRL0_FORMAT_MASK    0x40\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY24_CTRL0_SVIDX_OFFSET    0\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY24_CTRL0_SVIDX_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY24_CTRL1    0x0b79\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY24_CTRL2    0x0b7a\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY24_CTRL3    0x0b7b\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY24_CTRL4    0x0b7c\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY25_CTRL0    0x0b7d\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY25_CTRL0_VALID_OFFSET    7\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY25_CTRL0_VALID_MASK    0x80\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY25_CTRL0_FORMAT_OFFSET    6\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY25_CTRL0_FORMAT_MASK    0x40\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY25_CTRL0_SVIDX_OFFSET    0\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY25_CTRL0_SVIDX_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY25_CTRL1    0x0b7e\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY25_CTRL2    0x0b7f\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY25_CTRL3    0x0b80\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY25_CTRL4    0x0b81\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY26_CTRL0    0x0b82\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY26_CTRL0_VALID_OFFSET    7\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY26_CTRL0_VALID_MASK    0x80\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY26_CTRL0_FORMAT_OFFSET    6\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY26_CTRL0_FORMAT_MASK    0x40\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY26_CTRL0_SVIDX_OFFSET    0\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY26_CTRL0_SVIDX_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY26_CTRL1    0x0b83\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY26_CTRL2    0x0b84\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY26_CTRL3    0x0b85\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY26_CTRL4    0x0b86\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY27_CTRL0    0x0b87\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY27_CTRL0_VALID_OFFSET    7\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY27_CTRL0_VALID_MASK    0x80\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY27_CTRL0_FORMAT_OFFSET    6\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY27_CTRL0_FORMAT_MASK    0x40\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY27_CTRL0_SVIDX_OFFSET    0\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY27_CTRL0_SVIDX_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY27_CTRL1    0x0b88\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY27_CTRL2    0x0b89\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY27_CTRL3    0x0b8a\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY27_CTRL4    0x0b8b\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY28_CTRL0    0x0b8c\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY28_CTRL0_VALID_OFFSET    7\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY28_CTRL0_VALID_MASK    0x80\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY28_CTRL0_FORMAT_OFFSET    6\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY28_CTRL0_FORMAT_MASK    0x40\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY28_CTRL0_SVIDX_OFFSET    0\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY28_CTRL0_SVIDX_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY28_CTRL1    0x0b8d\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY28_CTRL2    0x0b8e\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY28_CTRL3    0x0b8f\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY28_CTRL4    0x0b90\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY29_CTRL0    0x0b91\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY29_CTRL0_VALID_OFFSET    7\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY29_CTRL0_VALID_MASK    0x80\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY29_CTRL0_FORMAT_OFFSET    6\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY29_CTRL0_FORMAT_MASK    0x40\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY29_CTRL0_SVIDX_OFFSET    0\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY29_CTRL0_SVIDX_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY29_CTRL1    0x0b92\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY29_CTRL2    0x0b93\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY29_CTRL3    0x0b94\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY29_CTRL4    0x0b95\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY30_CTRL0    0x0b96\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY30_CTRL0_VALID_OFFSET    7\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY30_CTRL0_VALID_MASK    0x80\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY30_CTRL0_FORMAT_OFFSET    6\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY30_CTRL0_FORMAT_MASK    0x40\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY30_CTRL0_SVIDX_OFFSET    0\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY30_CTRL0_SVIDX_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY30_CTRL1    0x0b97\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY30_CTRL2    0x0b98\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY30_CTRL3    0x0b99\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY30_CTRL4    0x0b9a\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY31_CTRL0    0x0b9b\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY31_CTRL0_VALID_OFFSET    7\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY31_CTRL0_VALID_MASK    0x80\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY31_CTRL0_FORMAT_OFFSET    6\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY31_CTRL0_FORMAT_MASK    0x40\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY31_CTRL0_SVIDX_OFFSET    0\n#define    RTL8367C_SVLAN_MCAST2S_ENTRY31_CTRL0_SVIDX_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY31_CTRL1    0x0b9c\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY31_CTRL2    0x0b9d\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY31_CTRL3    0x0b9e\n\n#define    RTL8367C_REG_SVLAN_MCAST2S_ENTRY31_CTRL4    0x0b9f\n\n#define    RTL8367C_REG_MLTVLAN_DUMMY_0    0x0ba0\n\n#define    RTL8367C_REG_MLTVLAN_DUMMY_1    0x0ba1\n\n#define    RTL8367C_REG_MLTVLAN_DUMMY_2    0x0ba2\n\n#define    RTL8367C_REG_MLTVLAN_DUMMY_3    0x0ba3\n\n#define    RTL8367C_REG_MLTVLAN_DUMMY_4    0x0ba4\n\n#define    RTL8367C_REG_MLTVLAN_DUMMY_5    0x0ba5\n\n#define    RTL8367C_REG_MLTVLAN_DUMMY_6    0x0ba6\n\n#define    RTL8367C_REG_MLTVLAN_DUMMY_7    0x0ba7\n\n/* (16'h0c00)svlan_reg */\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG0_CTRL1    0x0c01\n#define    RTL8367C_SVLAN_MEMBERCFG0_CTRL1_VS_UNTAGSET_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG0_CTRL1_VS_UNTAGSET_MASK    0xFF00\n#define    RTL8367C_SVLAN_MEMBERCFG0_CTRL1_VS_SMBR_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG0_CTRL1_VS_SMBR_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG0_CTRL2    0x0c02\n#define    RTL8367C_SVLAN_MEMBERCFG0_CTRL2_VS_FIDEN_OFFSET    7\n#define    RTL8367C_SVLAN_MEMBERCFG0_CTRL2_VS_FIDEN_MASK    0x80\n#define    RTL8367C_SVLAN_MEMBERCFG0_CTRL2_VS_SPRI_OFFSET    4\n#define    RTL8367C_SVLAN_MEMBERCFG0_CTRL2_VS_SPRI_MASK    0x70\n#define    RTL8367C_SVLAN_MEMBERCFG0_CTRL2_VS_FID_MSTI_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG0_CTRL2_VS_FID_MSTI_MASK    0xF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG0_CTRL3    0x0c03\n#define    RTL8367C_SVLAN_MEMBERCFG0_CTRL3_VS_EFID_OFFSET    13\n#define    RTL8367C_SVLAN_MEMBERCFG0_CTRL3_VS_EFID_MASK    0xE000\n#define    RTL8367C_SVLAN_MEMBERCFG0_CTRL3_VS_EFIDEN_OFFSET    12\n#define    RTL8367C_SVLAN_MEMBERCFG0_CTRL3_VS_EFIDEN_MASK    0x1000\n#define    RTL8367C_SVLAN_MEMBERCFG0_CTRL3_VS_SVID_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG0_CTRL3_VS_SVID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG1_CTRL1    0x0c04\n#define    RTL8367C_SVLAN_MEMBERCFG1_CTRL1_VS_UNTAGSET_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG1_CTRL1_VS_UNTAGSET_MASK    0xFF00\n#define    RTL8367C_SVLAN_MEMBERCFG1_CTRL1_VS_SMBR_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG1_CTRL1_VS_SMBR_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG1_CTRL2    0x0c05\n#define    RTL8367C_SVLAN_MEMBERCFG1_CTRL2_VS_FIDEN_OFFSET    7\n#define    RTL8367C_SVLAN_MEMBERCFG1_CTRL2_VS_FIDEN_MASK    0x80\n#define    RTL8367C_SVLAN_MEMBERCFG1_CTRL2_VS_SPRI_OFFSET    4\n#define    RTL8367C_SVLAN_MEMBERCFG1_CTRL2_VS_SPRI_MASK    0x70\n#define    RTL8367C_SVLAN_MEMBERCFG1_CTRL2_VS_FID_MSTI_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG1_CTRL2_VS_FID_MSTI_MASK    0xF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG1_CTRL3    0x0c06\n#define    RTL8367C_SVLAN_MEMBERCFG1_CTRL3_VS_EFID_OFFSET    13\n#define    RTL8367C_SVLAN_MEMBERCFG1_CTRL3_VS_EFID_MASK    0xE000\n#define    RTL8367C_SVLAN_MEMBERCFG1_CTRL3_VS_EFIDEN_OFFSET    12\n#define    RTL8367C_SVLAN_MEMBERCFG1_CTRL3_VS_EFIDEN_MASK    0x1000\n#define    RTL8367C_SVLAN_MEMBERCFG1_CTRL3_VS_SVID_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG1_CTRL3_VS_SVID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG2_CTRL1    0x0c07\n#define    RTL8367C_SVLAN_MEMBERCFG2_CTRL1_VS_UNTAGSET_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG2_CTRL1_VS_UNTAGSET_MASK    0xFF00\n#define    RTL8367C_SVLAN_MEMBERCFG2_CTRL1_VS_SMBR_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG2_CTRL1_VS_SMBR_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG2_CTRL2    0x0c08\n#define    RTL8367C_SVLAN_MEMBERCFG2_CTRL2_VS_FIDEN_OFFSET    7\n#define    RTL8367C_SVLAN_MEMBERCFG2_CTRL2_VS_FIDEN_MASK    0x80\n#define    RTL8367C_SVLAN_MEMBERCFG2_CTRL2_VS_SPRI_OFFSET    4\n#define    RTL8367C_SVLAN_MEMBERCFG2_CTRL2_VS_SPRI_MASK    0x70\n#define    RTL8367C_SVLAN_MEMBERCFG2_CTRL2_VS_FID_MSTI_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG2_CTRL2_VS_FID_MSTI_MASK    0xF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG2_CTRL3    0x0c09\n#define    RTL8367C_SVLAN_MEMBERCFG2_CTRL3_VS_EFID_OFFSET    13\n#define    RTL8367C_SVLAN_MEMBERCFG2_CTRL3_VS_EFID_MASK    0xE000\n#define    RTL8367C_SVLAN_MEMBERCFG2_CTRL3_VS_EFIDEN_OFFSET    12\n#define    RTL8367C_SVLAN_MEMBERCFG2_CTRL3_VS_EFIDEN_MASK    0x1000\n#define    RTL8367C_SVLAN_MEMBERCFG2_CTRL3_VS_SVID_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG2_CTRL3_VS_SVID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG3_CTRL1    0x0c0a\n#define    RTL8367C_SVLAN_MEMBERCFG3_CTRL1_VS_UNTAGSET_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG3_CTRL1_VS_UNTAGSET_MASK    0xFF00\n#define    RTL8367C_SVLAN_MEMBERCFG3_CTRL1_VS_SMBR_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG3_CTRL1_VS_SMBR_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG3_CTRL2    0x0c0b\n#define    RTL8367C_SVLAN_MEMBERCFG3_CTRL2_VS_FIDEN_OFFSET    7\n#define    RTL8367C_SVLAN_MEMBERCFG3_CTRL2_VS_FIDEN_MASK    0x80\n#define    RTL8367C_SVLAN_MEMBERCFG3_CTRL2_VS_SPRI_OFFSET    4\n#define    RTL8367C_SVLAN_MEMBERCFG3_CTRL2_VS_SPRI_MASK    0x70\n#define    RTL8367C_SVLAN_MEMBERCFG3_CTRL2_VS_FID_MSTI_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG3_CTRL2_VS_FID_MSTI_MASK    0xF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG3_CTRL3    0x0c0c\n#define    RTL8367C_SVLAN_MEMBERCFG3_CTRL3_VS_EFID_OFFSET    13\n#define    RTL8367C_SVLAN_MEMBERCFG3_CTRL3_VS_EFID_MASK    0xE000\n#define    RTL8367C_SVLAN_MEMBERCFG3_CTRL3_VS_EFIDEN_OFFSET    12\n#define    RTL8367C_SVLAN_MEMBERCFG3_CTRL3_VS_EFIDEN_MASK    0x1000\n#define    RTL8367C_SVLAN_MEMBERCFG3_CTRL3_VS_SVID_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG3_CTRL3_VS_SVID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG4_CTRL1    0x0c0d\n#define    RTL8367C_SVLAN_MEMBERCFG4_CTRL1_VS_UNTAGSET_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG4_CTRL1_VS_UNTAGSET_MASK    0xFF00\n#define    RTL8367C_SVLAN_MEMBERCFG4_CTRL1_VS_SMBR_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG4_CTRL1_VS_SMBR_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG4_CTRL2    0x0c0e\n#define    RTL8367C_SVLAN_MEMBERCFG4_CTRL2_VS_FIDEN_OFFSET    7\n#define    RTL8367C_SVLAN_MEMBERCFG4_CTRL2_VS_FIDEN_MASK    0x80\n#define    RTL8367C_SVLAN_MEMBERCFG4_CTRL2_VS_SPRI_OFFSET    4\n#define    RTL8367C_SVLAN_MEMBERCFG4_CTRL2_VS_SPRI_MASK    0x70\n#define    RTL8367C_SVLAN_MEMBERCFG4_CTRL2_VS_FID_MSTI_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG4_CTRL2_VS_FID_MSTI_MASK    0xF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG4_CTRL3    0x0c0f\n#define    RTL8367C_SVLAN_MEMBERCFG4_CTRL3_VS_EFID_OFFSET    13\n#define    RTL8367C_SVLAN_MEMBERCFG4_CTRL3_VS_EFID_MASK    0xE000\n#define    RTL8367C_SVLAN_MEMBERCFG4_CTRL3_VS_EFIDEN_OFFSET    12\n#define    RTL8367C_SVLAN_MEMBERCFG4_CTRL3_VS_EFIDEN_MASK    0x1000\n#define    RTL8367C_SVLAN_MEMBERCFG4_CTRL3_VS_SVID_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG4_CTRL3_VS_SVID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG5_CTRL1    0x0c10\n#define    RTL8367C_SVLAN_MEMBERCFG5_CTRL1_VS_UNTAGSET_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG5_CTRL1_VS_UNTAGSET_MASK    0xFF00\n#define    RTL8367C_SVLAN_MEMBERCFG5_CTRL1_VS_SMBR_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG5_CTRL1_VS_SMBR_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG5_CTRL2    0x0c11\n#define    RTL8367C_SVLAN_MEMBERCFG5_CTRL2_VS_FIDEN_OFFSET    7\n#define    RTL8367C_SVLAN_MEMBERCFG5_CTRL2_VS_FIDEN_MASK    0x80\n#define    RTL8367C_SVLAN_MEMBERCFG5_CTRL2_VS_SPRI_OFFSET    4\n#define    RTL8367C_SVLAN_MEMBERCFG5_CTRL2_VS_SPRI_MASK    0x70\n#define    RTL8367C_SVLAN_MEMBERCFG5_CTRL2_VS_FID_MSTI_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG5_CTRL2_VS_FID_MSTI_MASK    0xF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG5_CTRL3    0x0c12\n#define    RTL8367C_SVLAN_MEMBERCFG5_CTRL3_VS_EFID_OFFSET    13\n#define    RTL8367C_SVLAN_MEMBERCFG5_CTRL3_VS_EFID_MASK    0xE000\n#define    RTL8367C_SVLAN_MEMBERCFG5_CTRL3_VS_EFIDEN_OFFSET    12\n#define    RTL8367C_SVLAN_MEMBERCFG5_CTRL3_VS_EFIDEN_MASK    0x1000\n#define    RTL8367C_SVLAN_MEMBERCFG5_CTRL3_VS_SVID_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG5_CTRL3_VS_SVID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG6_CTRL1    0x0c13\n#define    RTL8367C_SVLAN_MEMBERCFG6_CTRL1_VS_UNTAGSET_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG6_CTRL1_VS_UNTAGSET_MASK    0xFF00\n#define    RTL8367C_SVLAN_MEMBERCFG6_CTRL1_VS_SMBR_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG6_CTRL1_VS_SMBR_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG6_CTRL2    0x0c14\n#define    RTL8367C_SVLAN_MEMBERCFG6_CTRL2_VS_FIDEN_OFFSET    7\n#define    RTL8367C_SVLAN_MEMBERCFG6_CTRL2_VS_FIDEN_MASK    0x80\n#define    RTL8367C_SVLAN_MEMBERCFG6_CTRL2_VS_SPRI_OFFSET    4\n#define    RTL8367C_SVLAN_MEMBERCFG6_CTRL2_VS_SPRI_MASK    0x70\n#define    RTL8367C_SVLAN_MEMBERCFG6_CTRL2_VS_FID_MSTI_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG6_CTRL2_VS_FID_MSTI_MASK    0xF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG6_CTRL3    0x0c15\n#define    RTL8367C_SVLAN_MEMBERCFG6_CTRL3_VS_EFID_OFFSET    13\n#define    RTL8367C_SVLAN_MEMBERCFG6_CTRL3_VS_EFID_MASK    0xE000\n#define    RTL8367C_SVLAN_MEMBERCFG6_CTRL3_VS_EFIDEN_OFFSET    12\n#define    RTL8367C_SVLAN_MEMBERCFG6_CTRL3_VS_EFIDEN_MASK    0x1000\n#define    RTL8367C_SVLAN_MEMBERCFG6_CTRL3_VS_SVID_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG6_CTRL3_VS_SVID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG7_CTRL1    0x0c16\n#define    RTL8367C_SVLAN_MEMBERCFG7_CTRL1_VS_UNTAGSET_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG7_CTRL1_VS_UNTAGSET_MASK    0xFF00\n#define    RTL8367C_SVLAN_MEMBERCFG7_CTRL1_VS_SMBR_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG7_CTRL1_VS_SMBR_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG7_CTRL2    0x0c17\n#define    RTL8367C_SVLAN_MEMBERCFG7_CTRL2_VS_FIDEN_OFFSET    7\n#define    RTL8367C_SVLAN_MEMBERCFG7_CTRL2_VS_FIDEN_MASK    0x80\n#define    RTL8367C_SVLAN_MEMBERCFG7_CTRL2_VS_SPRI_OFFSET    4\n#define    RTL8367C_SVLAN_MEMBERCFG7_CTRL2_VS_SPRI_MASK    0x70\n#define    RTL8367C_SVLAN_MEMBERCFG7_CTRL2_VS_FID_MSTI_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG7_CTRL2_VS_FID_MSTI_MASK    0xF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG7_CTRL3    0x0c18\n#define    RTL8367C_SVLAN_MEMBERCFG7_CTRL3_VS_EFID_OFFSET    13\n#define    RTL8367C_SVLAN_MEMBERCFG7_CTRL3_VS_EFID_MASK    0xE000\n#define    RTL8367C_SVLAN_MEMBERCFG7_CTRL3_VS_EFIDEN_OFFSET    12\n#define    RTL8367C_SVLAN_MEMBERCFG7_CTRL3_VS_EFIDEN_MASK    0x1000\n#define    RTL8367C_SVLAN_MEMBERCFG7_CTRL3_VS_SVID_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG7_CTRL3_VS_SVID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG8_CTRL1    0x0c19\n#define    RTL8367C_SVLAN_MEMBERCFG8_CTRL1_VS_UNTAGSET_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG8_CTRL1_VS_UNTAGSET_MASK    0xFF00\n#define    RTL8367C_SVLAN_MEMBERCFG8_CTRL1_VS_SMBR_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG8_CTRL1_VS_SMBR_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG8_CTRL2    0x0c1a\n#define    RTL8367C_SVLAN_MEMBERCFG8_CTRL2_VS_FIDEN_OFFSET    7\n#define    RTL8367C_SVLAN_MEMBERCFG8_CTRL2_VS_FIDEN_MASK    0x80\n#define    RTL8367C_SVLAN_MEMBERCFG8_CTRL2_VS_SPRI_OFFSET    4\n#define    RTL8367C_SVLAN_MEMBERCFG8_CTRL2_VS_SPRI_MASK    0x70\n#define    RTL8367C_SVLAN_MEMBERCFG8_CTRL2_VS_FID_MSTI_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG8_CTRL2_VS_FID_MSTI_MASK    0xF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG8_CTRL3    0x0c1b\n#define    RTL8367C_SVLAN_MEMBERCFG8_CTRL3_VS_EFID_OFFSET    13\n#define    RTL8367C_SVLAN_MEMBERCFG8_CTRL3_VS_EFID_MASK    0xE000\n#define    RTL8367C_SVLAN_MEMBERCFG8_CTRL3_VS_EFIDEN_OFFSET    12\n#define    RTL8367C_SVLAN_MEMBERCFG8_CTRL3_VS_EFIDEN_MASK    0x1000\n#define    RTL8367C_SVLAN_MEMBERCFG8_CTRL3_VS_SVID_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG8_CTRL3_VS_SVID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG9_CTRL1    0x0c1c\n#define    RTL8367C_SVLAN_MEMBERCFG9_CTRL1_VS_UNTAGSET_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG9_CTRL1_VS_UNTAGSET_MASK    0xFF00\n#define    RTL8367C_SVLAN_MEMBERCFG9_CTRL1_VS_SMBR_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG9_CTRL1_VS_SMBR_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG9_CTRL2    0x0c1d\n#define    RTL8367C_SVLAN_MEMBERCFG9_CTRL2_VS_FIDEN_OFFSET    7\n#define    RTL8367C_SVLAN_MEMBERCFG9_CTRL2_VS_FIDEN_MASK    0x80\n#define    RTL8367C_SVLAN_MEMBERCFG9_CTRL2_VS_SPRI_OFFSET    4\n#define    RTL8367C_SVLAN_MEMBERCFG9_CTRL2_VS_SPRI_MASK    0x70\n#define    RTL8367C_SVLAN_MEMBERCFG9_CTRL2_VS_FID_MSTI_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG9_CTRL2_VS_FID_MSTI_MASK    0xF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG9_CTRL3    0x0c1e\n#define    RTL8367C_SVLAN_MEMBERCFG9_CTRL3_VS_EFID_OFFSET    13\n#define    RTL8367C_SVLAN_MEMBERCFG9_CTRL3_VS_EFID_MASK    0xE000\n#define    RTL8367C_SVLAN_MEMBERCFG9_CTRL3_VS_EFIDEN_OFFSET    12\n#define    RTL8367C_SVLAN_MEMBERCFG9_CTRL3_VS_EFIDEN_MASK    0x1000\n#define    RTL8367C_SVLAN_MEMBERCFG9_CTRL3_VS_SVID_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG9_CTRL3_VS_SVID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG10_CTRL1    0x0c1f\n#define    RTL8367C_SVLAN_MEMBERCFG10_CTRL1_VS_UNTAGSET_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG10_CTRL1_VS_UNTAGSET_MASK    0xFF00\n#define    RTL8367C_SVLAN_MEMBERCFG10_CTRL1_VS_SMBR_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG10_CTRL1_VS_SMBR_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG10_CTRL2    0x0c20\n#define    RTL8367C_SVLAN_MEMBERCFG10_CTRL2_VS_FIDEN_OFFSET    7\n#define    RTL8367C_SVLAN_MEMBERCFG10_CTRL2_VS_FIDEN_MASK    0x80\n#define    RTL8367C_SVLAN_MEMBERCFG10_CTRL2_VS_SPRI_OFFSET    4\n#define    RTL8367C_SVLAN_MEMBERCFG10_CTRL2_VS_SPRI_MASK    0x70\n#define    RTL8367C_SVLAN_MEMBERCFG10_CTRL2_VS_FID_MSTI_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG10_CTRL2_VS_FID_MSTI_MASK    0xF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG10_CTRL3    0x0c21\n#define    RTL8367C_SVLAN_MEMBERCFG10_CTRL3_VS_EFID_OFFSET    13\n#define    RTL8367C_SVLAN_MEMBERCFG10_CTRL3_VS_EFID_MASK    0xE000\n#define    RTL8367C_SVLAN_MEMBERCFG10_CTRL3_VS_EFIDEN_OFFSET    12\n#define    RTL8367C_SVLAN_MEMBERCFG10_CTRL3_VS_EFIDEN_MASK    0x1000\n#define    RTL8367C_SVLAN_MEMBERCFG10_CTRL3_VS_SVID_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG10_CTRL3_VS_SVID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG11_CTRL1    0x0c22\n#define    RTL8367C_SVLAN_MEMBERCFG11_CTRL1_VS_UNTAGSET_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG11_CTRL1_VS_UNTAGSET_MASK    0xFF00\n#define    RTL8367C_SVLAN_MEMBERCFG11_CTRL1_VS_SMBR_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG11_CTRL1_VS_SMBR_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG11_CTRL2    0x0c23\n#define    RTL8367C_SVLAN_MEMBERCFG11_CTRL2_VS_FIDEN_OFFSET    7\n#define    RTL8367C_SVLAN_MEMBERCFG11_CTRL2_VS_FIDEN_MASK    0x80\n#define    RTL8367C_SVLAN_MEMBERCFG11_CTRL2_VS_SPRI_OFFSET    4\n#define    RTL8367C_SVLAN_MEMBERCFG11_CTRL2_VS_SPRI_MASK    0x70\n#define    RTL8367C_SVLAN_MEMBERCFG11_CTRL2_VS_FID_MSTI_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG11_CTRL2_VS_FID_MSTI_MASK    0xF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG11_CTRL3    0x0c24\n#define    RTL8367C_SVLAN_MEMBERCFG11_CTRL3_VS_EFID_OFFSET    13\n#define    RTL8367C_SVLAN_MEMBERCFG11_CTRL3_VS_EFID_MASK    0xE000\n#define    RTL8367C_SVLAN_MEMBERCFG11_CTRL3_VS_EFIDEN_OFFSET    12\n#define    RTL8367C_SVLAN_MEMBERCFG11_CTRL3_VS_EFIDEN_MASK    0x1000\n#define    RTL8367C_SVLAN_MEMBERCFG11_CTRL3_VS_SVID_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG11_CTRL3_VS_SVID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG12_CTRL1    0x0c25\n#define    RTL8367C_SVLAN_MEMBERCFG12_CTRL1_VS_UNTAGSET_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG12_CTRL1_VS_UNTAGSET_MASK    0xFF00\n#define    RTL8367C_SVLAN_MEMBERCFG12_CTRL1_VS_SMBR_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG12_CTRL1_VS_SMBR_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG12_CTRL2    0x0c26\n#define    RTL8367C_SVLAN_MEMBERCFG12_CTRL2_VS_FIDEN_OFFSET    7\n#define    RTL8367C_SVLAN_MEMBERCFG12_CTRL2_VS_FIDEN_MASK    0x80\n#define    RTL8367C_SVLAN_MEMBERCFG12_CTRL2_VS_SPRI_OFFSET    4\n#define    RTL8367C_SVLAN_MEMBERCFG12_CTRL2_VS_SPRI_MASK    0x70\n#define    RTL8367C_SVLAN_MEMBERCFG12_CTRL2_VS_FID_MSTI_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG12_CTRL2_VS_FID_MSTI_MASK    0xF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG12_CTRL3    0x0c27\n#define    RTL8367C_SVLAN_MEMBERCFG12_CTRL3_VS_EFID_OFFSET    13\n#define    RTL8367C_SVLAN_MEMBERCFG12_CTRL3_VS_EFID_MASK    0xE000\n#define    RTL8367C_SVLAN_MEMBERCFG12_CTRL3_VS_EFIDEN_OFFSET    12\n#define    RTL8367C_SVLAN_MEMBERCFG12_CTRL3_VS_EFIDEN_MASK    0x1000\n#define    RTL8367C_SVLAN_MEMBERCFG12_CTRL3_VS_SVID_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG12_CTRL3_VS_SVID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG13_CTRL1    0x0c28\n#define    RTL8367C_SVLAN_MEMBERCFG13_CTRL1_VS_UNTAGSET_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG13_CTRL1_VS_UNTAGSET_MASK    0xFF00\n#define    RTL8367C_SVLAN_MEMBERCFG13_CTRL1_VS_SMBR_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG13_CTRL1_VS_SMBR_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG13_CTRL2    0x0c29\n#define    RTL8367C_SVLAN_MEMBERCFG13_CTRL2_VS_FIDEN_OFFSET    7\n#define    RTL8367C_SVLAN_MEMBERCFG13_CTRL2_VS_FIDEN_MASK    0x80\n#define    RTL8367C_SVLAN_MEMBERCFG13_CTRL2_VS_SPRI_OFFSET    4\n#define    RTL8367C_SVLAN_MEMBERCFG13_CTRL2_VS_SPRI_MASK    0x70\n#define    RTL8367C_SVLAN_MEMBERCFG13_CTRL2_VS_FID_MSTI_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG13_CTRL2_VS_FID_MSTI_MASK    0xF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG13_CTRL3    0x0c2a\n#define    RTL8367C_SVLAN_MEMBERCFG13_CTRL3_VS_EFID_OFFSET    13\n#define    RTL8367C_SVLAN_MEMBERCFG13_CTRL3_VS_EFID_MASK    0xE000\n#define    RTL8367C_SVLAN_MEMBERCFG13_CTRL3_VS_EFIDEN_OFFSET    12\n#define    RTL8367C_SVLAN_MEMBERCFG13_CTRL3_VS_EFIDEN_MASK    0x1000\n#define    RTL8367C_SVLAN_MEMBERCFG13_CTRL3_VS_SVID_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG13_CTRL3_VS_SVID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG14_CTRL1    0x0c2b\n#define    RTL8367C_SVLAN_MEMBERCFG14_CTRL1_VS_UNTAGSET_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG14_CTRL1_VS_UNTAGSET_MASK    0xFF00\n#define    RTL8367C_SVLAN_MEMBERCFG14_CTRL1_VS_SMBR_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG14_CTRL1_VS_SMBR_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG14_CTRL2    0x0c2c\n#define    RTL8367C_SVLAN_MEMBERCFG14_CTRL2_VS_FIDEN_OFFSET    7\n#define    RTL8367C_SVLAN_MEMBERCFG14_CTRL2_VS_FIDEN_MASK    0x80\n#define    RTL8367C_SVLAN_MEMBERCFG14_CTRL2_VS_SPRI_OFFSET    4\n#define    RTL8367C_SVLAN_MEMBERCFG14_CTRL2_VS_SPRI_MASK    0x70\n#define    RTL8367C_SVLAN_MEMBERCFG14_CTRL2_VS_FID_MSTI_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG14_CTRL2_VS_FID_MSTI_MASK    0xF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG14_CTRL3    0x0c2d\n#define    RTL8367C_SVLAN_MEMBERCFG14_CTRL3_VS_EFID_OFFSET    13\n#define    RTL8367C_SVLAN_MEMBERCFG14_CTRL3_VS_EFID_MASK    0xE000\n#define    RTL8367C_SVLAN_MEMBERCFG14_CTRL3_VS_EFIDEN_OFFSET    12\n#define    RTL8367C_SVLAN_MEMBERCFG14_CTRL3_VS_EFIDEN_MASK    0x1000\n#define    RTL8367C_SVLAN_MEMBERCFG14_CTRL3_VS_SVID_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG14_CTRL3_VS_SVID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG15_CTRL1    0x0c2e\n#define    RTL8367C_SVLAN_MEMBERCFG15_CTRL1_VS_UNTAGSET_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG15_CTRL1_VS_UNTAGSET_MASK    0xFF00\n#define    RTL8367C_SVLAN_MEMBERCFG15_CTRL1_VS_SMBR_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG15_CTRL1_VS_SMBR_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG15_CTRL2    0x0c2f\n#define    RTL8367C_SVLAN_MEMBERCFG15_CTRL2_VS_FIDEN_OFFSET    7\n#define    RTL8367C_SVLAN_MEMBERCFG15_CTRL2_VS_FIDEN_MASK    0x80\n#define    RTL8367C_SVLAN_MEMBERCFG15_CTRL2_VS_SPRI_OFFSET    4\n#define    RTL8367C_SVLAN_MEMBERCFG15_CTRL2_VS_SPRI_MASK    0x70\n#define    RTL8367C_SVLAN_MEMBERCFG15_CTRL2_VS_FID_MSTI_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG15_CTRL2_VS_FID_MSTI_MASK    0xF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG15_CTRL3    0x0c30\n#define    RTL8367C_SVLAN_MEMBERCFG15_CTRL3_VS_EFID_OFFSET    13\n#define    RTL8367C_SVLAN_MEMBERCFG15_CTRL3_VS_EFID_MASK    0xE000\n#define    RTL8367C_SVLAN_MEMBERCFG15_CTRL3_VS_EFIDEN_OFFSET    12\n#define    RTL8367C_SVLAN_MEMBERCFG15_CTRL3_VS_EFIDEN_MASK    0x1000\n#define    RTL8367C_SVLAN_MEMBERCFG15_CTRL3_VS_SVID_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG15_CTRL3_VS_SVID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG16_CTRL1    0x0c31\n#define    RTL8367C_SVLAN_MEMBERCFG16_CTRL1_VS_UNTAGSET_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG16_CTRL1_VS_UNTAGSET_MASK    0xFF00\n#define    RTL8367C_SVLAN_MEMBERCFG16_CTRL1_VS_SMBR_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG16_CTRL1_VS_SMBR_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG16_CTRL2    0x0c32\n#define    RTL8367C_SVLAN_MEMBERCFG16_CTRL2_VS_FIDEN_OFFSET    7\n#define    RTL8367C_SVLAN_MEMBERCFG16_CTRL2_VS_FIDEN_MASK    0x80\n#define    RTL8367C_SVLAN_MEMBERCFG16_CTRL2_VS_SPRI_OFFSET    4\n#define    RTL8367C_SVLAN_MEMBERCFG16_CTRL2_VS_SPRI_MASK    0x70\n#define    RTL8367C_SVLAN_MEMBERCFG16_CTRL2_VS_FID_MSTI_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG16_CTRL2_VS_FID_MSTI_MASK    0xF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG16_CTRL3    0x0c33\n#define    RTL8367C_SVLAN_MEMBERCFG16_CTRL3_VS_EFID_OFFSET    13\n#define    RTL8367C_SVLAN_MEMBERCFG16_CTRL3_VS_EFID_MASK    0xE000\n#define    RTL8367C_SVLAN_MEMBERCFG16_CTRL3_VS_EFIDEN_OFFSET    12\n#define    RTL8367C_SVLAN_MEMBERCFG16_CTRL3_VS_EFIDEN_MASK    0x1000\n#define    RTL8367C_SVLAN_MEMBERCFG16_CTRL3_VS_SVID_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG16_CTRL3_VS_SVID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG17_CTRL1    0x0c34\n#define    RTL8367C_SVLAN_MEMBERCFG17_CTRL1_VS_UNTAGSET_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG17_CTRL1_VS_UNTAGSET_MASK    0xFF00\n#define    RTL8367C_SVLAN_MEMBERCFG17_CTRL1_VS_SMBR_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG17_CTRL1_VS_SMBR_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG17_CTRL2    0x0c35\n#define    RTL8367C_SVLAN_MEMBERCFG17_CTRL2_VS_FIDEN_OFFSET    7\n#define    RTL8367C_SVLAN_MEMBERCFG17_CTRL2_VS_FIDEN_MASK    0x80\n#define    RTL8367C_SVLAN_MEMBERCFG17_CTRL2_VS_SPRI_OFFSET    4\n#define    RTL8367C_SVLAN_MEMBERCFG17_CTRL2_VS_SPRI_MASK    0x70\n#define    RTL8367C_SVLAN_MEMBERCFG17_CTRL2_VS_FID_MSTI_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG17_CTRL2_VS_FID_MSTI_MASK    0xF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG17_CTRL3    0x0c36\n#define    RTL8367C_SVLAN_MEMBERCFG17_CTRL3_VS_EFID_OFFSET    13\n#define    RTL8367C_SVLAN_MEMBERCFG17_CTRL3_VS_EFID_MASK    0xE000\n#define    RTL8367C_SVLAN_MEMBERCFG17_CTRL3_VS_EFIDEN_OFFSET    12\n#define    RTL8367C_SVLAN_MEMBERCFG17_CTRL3_VS_EFIDEN_MASK    0x1000\n#define    RTL8367C_SVLAN_MEMBERCFG17_CTRL3_VS_SVID_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG17_CTRL3_VS_SVID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG18_CTRL1    0x0c37\n#define    RTL8367C_SVLAN_MEMBERCFG18_CTRL1_VS_UNTAGSET_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG18_CTRL1_VS_UNTAGSET_MASK    0xFF00\n#define    RTL8367C_SVLAN_MEMBERCFG18_CTRL1_VS_SMBR_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG18_CTRL1_VS_SMBR_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG18_CTRL2    0x0c38\n#define    RTL8367C_SVLAN_MEMBERCFG18_CTRL2_VS_FIDEN_OFFSET    7\n#define    RTL8367C_SVLAN_MEMBERCFG18_CTRL2_VS_FIDEN_MASK    0x80\n#define    RTL8367C_SVLAN_MEMBERCFG18_CTRL2_VS_SPRI_OFFSET    4\n#define    RTL8367C_SVLAN_MEMBERCFG18_CTRL2_VS_SPRI_MASK    0x70\n#define    RTL8367C_SVLAN_MEMBERCFG18_CTRL2_VS_FID_MSTI_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG18_CTRL2_VS_FID_MSTI_MASK    0xF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG18_CTRL3    0x0c39\n#define    RTL8367C_SVLAN_MEMBERCFG18_CTRL3_VS_EFID_OFFSET    13\n#define    RTL8367C_SVLAN_MEMBERCFG18_CTRL3_VS_EFID_MASK    0xE000\n#define    RTL8367C_SVLAN_MEMBERCFG18_CTRL3_VS_EFIDEN_OFFSET    12\n#define    RTL8367C_SVLAN_MEMBERCFG18_CTRL3_VS_EFIDEN_MASK    0x1000\n#define    RTL8367C_SVLAN_MEMBERCFG18_CTRL3_VS_SVID_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG18_CTRL3_VS_SVID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG19_CTRL1    0x0c3a\n#define    RTL8367C_SVLAN_MEMBERCFG19_CTRL1_VS_UNTAGSET_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG19_CTRL1_VS_UNTAGSET_MASK    0xFF00\n#define    RTL8367C_SVLAN_MEMBERCFG19_CTRL1_VS_SMBR_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG19_CTRL1_VS_SMBR_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG19_CTRL2    0x0c3b\n#define    RTL8367C_SVLAN_MEMBERCFG19_CTRL2_VS_FIDEN_OFFSET    7\n#define    RTL8367C_SVLAN_MEMBERCFG19_CTRL2_VS_FIDEN_MASK    0x80\n#define    RTL8367C_SVLAN_MEMBERCFG19_CTRL2_VS_SPRI_OFFSET    4\n#define    RTL8367C_SVLAN_MEMBERCFG19_CTRL2_VS_SPRI_MASK    0x70\n#define    RTL8367C_SVLAN_MEMBERCFG19_CTRL2_VS_FID_MSTI_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG19_CTRL2_VS_FID_MSTI_MASK    0xF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG19_CTRL3    0x0c3c\n#define    RTL8367C_SVLAN_MEMBERCFG19_CTRL3_VS_EFID_OFFSET    13\n#define    RTL8367C_SVLAN_MEMBERCFG19_CTRL3_VS_EFID_MASK    0xE000\n#define    RTL8367C_SVLAN_MEMBERCFG19_CTRL3_VS_EFIDEN_OFFSET    12\n#define    RTL8367C_SVLAN_MEMBERCFG19_CTRL3_VS_EFIDEN_MASK    0x1000\n#define    RTL8367C_SVLAN_MEMBERCFG19_CTRL3_VS_SVID_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG19_CTRL3_VS_SVID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG20_CTRL1    0x0c3d\n#define    RTL8367C_SVLAN_MEMBERCFG20_CTRL1_VS_UNTAGSET_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG20_CTRL1_VS_UNTAGSET_MASK    0xFF00\n#define    RTL8367C_SVLAN_MEMBERCFG20_CTRL1_VS_SMBR_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG20_CTRL1_VS_SMBR_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG20_CTRL2    0x0c3e\n#define    RTL8367C_SVLAN_MEMBERCFG20_CTRL2_VS_FIDEN_OFFSET    7\n#define    RTL8367C_SVLAN_MEMBERCFG20_CTRL2_VS_FIDEN_MASK    0x80\n#define    RTL8367C_SVLAN_MEMBERCFG20_CTRL2_VS_SPRI_OFFSET    4\n#define    RTL8367C_SVLAN_MEMBERCFG20_CTRL2_VS_SPRI_MASK    0x70\n#define    RTL8367C_SVLAN_MEMBERCFG20_CTRL2_VS_FID_MSTI_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG20_CTRL2_VS_FID_MSTI_MASK    0xF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG20_CTRL3    0x0c3f\n#define    RTL8367C_SVLAN_MEMBERCFG20_CTRL3_VS_EFID_OFFSET    13\n#define    RTL8367C_SVLAN_MEMBERCFG20_CTRL3_VS_EFID_MASK    0xE000\n#define    RTL8367C_SVLAN_MEMBERCFG20_CTRL3_VS_EFIDEN_OFFSET    12\n#define    RTL8367C_SVLAN_MEMBERCFG20_CTRL3_VS_EFIDEN_MASK    0x1000\n#define    RTL8367C_SVLAN_MEMBERCFG20_CTRL3_VS_SVID_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG20_CTRL3_VS_SVID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG21_CTRL1    0x0c40\n#define    RTL8367C_SVLAN_MEMBERCFG21_CTRL1_VS_UNTAGSET_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG21_CTRL1_VS_UNTAGSET_MASK    0xFF00\n#define    RTL8367C_SVLAN_MEMBERCFG21_CTRL1_VS_SMBR_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG21_CTRL1_VS_SMBR_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG21_CTRL2    0x0c41\n#define    RTL8367C_SVLAN_MEMBERCFG21_CTRL2_VS_FIDEN_OFFSET    7\n#define    RTL8367C_SVLAN_MEMBERCFG21_CTRL2_VS_FIDEN_MASK    0x80\n#define    RTL8367C_SVLAN_MEMBERCFG21_CTRL2_VS_SPRI_OFFSET    4\n#define    RTL8367C_SVLAN_MEMBERCFG21_CTRL2_VS_SPRI_MASK    0x70\n#define    RTL8367C_SVLAN_MEMBERCFG21_CTRL2_VS_FID_MSTI_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG21_CTRL2_VS_FID_MSTI_MASK    0xF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG21_CTRL3    0x0c42\n#define    RTL8367C_SVLAN_MEMBERCFG21_CTRL3_VS_EFID_OFFSET    13\n#define    RTL8367C_SVLAN_MEMBERCFG21_CTRL3_VS_EFID_MASK    0xE000\n#define    RTL8367C_SVLAN_MEMBERCFG21_CTRL3_VS_EFIDEN_OFFSET    12\n#define    RTL8367C_SVLAN_MEMBERCFG21_CTRL3_VS_EFIDEN_MASK    0x1000\n#define    RTL8367C_SVLAN_MEMBERCFG21_CTRL3_VS_SVID_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG21_CTRL3_VS_SVID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG22_CTRL1    0x0c43\n#define    RTL8367C_SVLAN_MEMBERCFG22_CTRL1_VS_UNTAGSET_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG22_CTRL1_VS_UNTAGSET_MASK    0xFF00\n#define    RTL8367C_SVLAN_MEMBERCFG22_CTRL1_VS_SMBR_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG22_CTRL1_VS_SMBR_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG22_CTRL2    0x0c44\n#define    RTL8367C_SVLAN_MEMBERCFG22_CTRL2_VS_FIDEN_OFFSET    7\n#define    RTL8367C_SVLAN_MEMBERCFG22_CTRL2_VS_FIDEN_MASK    0x80\n#define    RTL8367C_SVLAN_MEMBERCFG22_CTRL2_VS_SPRI_OFFSET    4\n#define    RTL8367C_SVLAN_MEMBERCFG22_CTRL2_VS_SPRI_MASK    0x70\n#define    RTL8367C_SVLAN_MEMBERCFG22_CTRL2_VS_FID_MSTI_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG22_CTRL2_VS_FID_MSTI_MASK    0xF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG22_CTRL3    0x0c45\n#define    RTL8367C_SVLAN_MEMBERCFG22_CTRL3_VS_EFID_OFFSET    13\n#define    RTL8367C_SVLAN_MEMBERCFG22_CTRL3_VS_EFID_MASK    0xE000\n#define    RTL8367C_SVLAN_MEMBERCFG22_CTRL3_VS_EFIDEN_OFFSET    12\n#define    RTL8367C_SVLAN_MEMBERCFG22_CTRL3_VS_EFIDEN_MASK    0x1000\n#define    RTL8367C_SVLAN_MEMBERCFG22_CTRL3_VS_SVID_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG22_CTRL3_VS_SVID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG23_CTRL1    0x0c46\n#define    RTL8367C_SVLAN_MEMBERCFG23_CTRL1_VS_UNTAGSET_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG23_CTRL1_VS_UNTAGSET_MASK    0xFF00\n#define    RTL8367C_SVLAN_MEMBERCFG23_CTRL1_VS_SMBR_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG23_CTRL1_VS_SMBR_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG23_CTRL2    0x0c47\n#define    RTL8367C_SVLAN_MEMBERCFG23_CTRL2_VS_FIDEN_OFFSET    7\n#define    RTL8367C_SVLAN_MEMBERCFG23_CTRL2_VS_FIDEN_MASK    0x80\n#define    RTL8367C_SVLAN_MEMBERCFG23_CTRL2_VS_SPRI_OFFSET    4\n#define    RTL8367C_SVLAN_MEMBERCFG23_CTRL2_VS_SPRI_MASK    0x70\n#define    RTL8367C_SVLAN_MEMBERCFG23_CTRL2_VS_FID_MSTI_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG23_CTRL2_VS_FID_MSTI_MASK    0xF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG23_CTRL3    0x0c48\n#define    RTL8367C_SVLAN_MEMBERCFG23_CTRL3_VS_EFID_OFFSET    13\n#define    RTL8367C_SVLAN_MEMBERCFG23_CTRL3_VS_EFID_MASK    0xE000\n#define    RTL8367C_SVLAN_MEMBERCFG23_CTRL3_VS_EFIDEN_OFFSET    12\n#define    RTL8367C_SVLAN_MEMBERCFG23_CTRL3_VS_EFIDEN_MASK    0x1000\n#define    RTL8367C_SVLAN_MEMBERCFG23_CTRL3_VS_SVID_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG23_CTRL3_VS_SVID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG24_CTRL1    0x0c49\n#define    RTL8367C_SVLAN_MEMBERCFG24_CTRL1_VS_UNTAGSET_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG24_CTRL1_VS_UNTAGSET_MASK    0xFF00\n#define    RTL8367C_SVLAN_MEMBERCFG24_CTRL1_VS_SMBR_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG24_CTRL1_VS_SMBR_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG24_CTRL2    0x0c4a\n#define    RTL8367C_SVLAN_MEMBERCFG24_CTRL2_VS_FIDEN_OFFSET    7\n#define    RTL8367C_SVLAN_MEMBERCFG24_CTRL2_VS_FIDEN_MASK    0x80\n#define    RTL8367C_SVLAN_MEMBERCFG24_CTRL2_VS_SPRI_OFFSET    4\n#define    RTL8367C_SVLAN_MEMBERCFG24_CTRL2_VS_SPRI_MASK    0x70\n#define    RTL8367C_SVLAN_MEMBERCFG24_CTRL2_VS_FID_MSTI_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG24_CTRL2_VS_FID_MSTI_MASK    0xF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG24_CTRL3    0x0c4b\n#define    RTL8367C_SVLAN_MEMBERCFG24_CTRL3_VS_EFID_OFFSET    13\n#define    RTL8367C_SVLAN_MEMBERCFG24_CTRL3_VS_EFID_MASK    0xE000\n#define    RTL8367C_SVLAN_MEMBERCFG24_CTRL3_VS_EFIDEN_OFFSET    12\n#define    RTL8367C_SVLAN_MEMBERCFG24_CTRL3_VS_EFIDEN_MASK    0x1000\n#define    RTL8367C_SVLAN_MEMBERCFG24_CTRL3_VS_SVID_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG24_CTRL3_VS_SVID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG25_CTRL1    0x0c4c\n#define    RTL8367C_SVLAN_MEMBERCFG25_CTRL1_VS_UNTAGSET_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG25_CTRL1_VS_UNTAGSET_MASK    0xFF00\n#define    RTL8367C_SVLAN_MEMBERCFG25_CTRL1_VS_SMBR_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG25_CTRL1_VS_SMBR_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG25_CTRL2    0x0c4d\n#define    RTL8367C_SVLAN_MEMBERCFG25_CTRL2_VS_FIDEN_OFFSET    7\n#define    RTL8367C_SVLAN_MEMBERCFG25_CTRL2_VS_FIDEN_MASK    0x80\n#define    RTL8367C_SVLAN_MEMBERCFG25_CTRL2_VS_SPRI_OFFSET    4\n#define    RTL8367C_SVLAN_MEMBERCFG25_CTRL2_VS_SPRI_MASK    0x70\n#define    RTL8367C_SVLAN_MEMBERCFG25_CTRL2_VS_FID_MSTI_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG25_CTRL2_VS_FID_MSTI_MASK    0xF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG25_CTRL3    0x0c4e\n#define    RTL8367C_SVLAN_MEMBERCFG25_CTRL3_VS_EFID_OFFSET    13\n#define    RTL8367C_SVLAN_MEMBERCFG25_CTRL3_VS_EFID_MASK    0xE000\n#define    RTL8367C_SVLAN_MEMBERCFG25_CTRL3_VS_EFIDEN_OFFSET    12\n#define    RTL8367C_SVLAN_MEMBERCFG25_CTRL3_VS_EFIDEN_MASK    0x1000\n#define    RTL8367C_SVLAN_MEMBERCFG25_CTRL3_VS_SVID_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG25_CTRL3_VS_SVID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG26_CTRL1    0x0c4f\n#define    RTL8367C_SVLAN_MEMBERCFG26_CTRL1_VS_UNTAGSET_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG26_CTRL1_VS_UNTAGSET_MASK    0xFF00\n#define    RTL8367C_SVLAN_MEMBERCFG26_CTRL1_VS_SMBR_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG26_CTRL1_VS_SMBR_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG26_CTRL2    0x0c50\n#define    RTL8367C_SVLAN_MEMBERCFG26_CTRL2_VS_FIDEN_OFFSET    7\n#define    RTL8367C_SVLAN_MEMBERCFG26_CTRL2_VS_FIDEN_MASK    0x80\n#define    RTL8367C_SVLAN_MEMBERCFG26_CTRL2_VS_SPRI_OFFSET    4\n#define    RTL8367C_SVLAN_MEMBERCFG26_CTRL2_VS_SPRI_MASK    0x70\n#define    RTL8367C_SVLAN_MEMBERCFG26_CTRL2_VS_FID_MSTI_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG26_CTRL2_VS_FID_MSTI_MASK    0xF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG26_CTRL3    0x0c51\n#define    RTL8367C_SVLAN_MEMBERCFG26_CTRL3_VS_EFID_OFFSET    13\n#define    RTL8367C_SVLAN_MEMBERCFG26_CTRL3_VS_EFID_MASK    0xE000\n#define    RTL8367C_SVLAN_MEMBERCFG26_CTRL3_VS_EFIDEN_OFFSET    12\n#define    RTL8367C_SVLAN_MEMBERCFG26_CTRL3_VS_EFIDEN_MASK    0x1000\n#define    RTL8367C_SVLAN_MEMBERCFG26_CTRL3_VS_SVID_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG26_CTRL3_VS_SVID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG27_CTRL1    0x0c52\n#define    RTL8367C_SVLAN_MEMBERCFG27_CTRL1_VS_UNTAGSET_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG27_CTRL1_VS_UNTAGSET_MASK    0xFF00\n#define    RTL8367C_SVLAN_MEMBERCFG27_CTRL1_VS_SMBR_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG27_CTRL1_VS_SMBR_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG27_CTRL2    0x0c53\n#define    RTL8367C_SVLAN_MEMBERCFG27_CTRL2_VS_FIDEN_OFFSET    7\n#define    RTL8367C_SVLAN_MEMBERCFG27_CTRL2_VS_FIDEN_MASK    0x80\n#define    RTL8367C_SVLAN_MEMBERCFG27_CTRL2_VS_SPRI_OFFSET    4\n#define    RTL8367C_SVLAN_MEMBERCFG27_CTRL2_VS_SPRI_MASK    0x70\n#define    RTL8367C_SVLAN_MEMBERCFG27_CTRL2_VS_FID_MSTI_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG27_CTRL2_VS_FID_MSTI_MASK    0xF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG27_CTRL3    0x0c54\n#define    RTL8367C_SVLAN_MEMBERCFG27_CTRL3_VS_EFID_OFFSET    13\n#define    RTL8367C_SVLAN_MEMBERCFG27_CTRL3_VS_EFID_MASK    0xE000\n#define    RTL8367C_SVLAN_MEMBERCFG27_CTRL3_VS_EFIDEN_OFFSET    12\n#define    RTL8367C_SVLAN_MEMBERCFG27_CTRL3_VS_EFIDEN_MASK    0x1000\n#define    RTL8367C_SVLAN_MEMBERCFG27_CTRL3_VS_SVID_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG27_CTRL3_VS_SVID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG28_CTRL1    0x0c55\n#define    RTL8367C_SVLAN_MEMBERCFG28_CTRL1_VS_UNTAGSET_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG28_CTRL1_VS_UNTAGSET_MASK    0xFF00\n#define    RTL8367C_SVLAN_MEMBERCFG28_CTRL1_VS_SMBR_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG28_CTRL1_VS_SMBR_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG28_CTRL2    0x0c56\n#define    RTL8367C_SVLAN_MEMBERCFG28_CTRL2_VS_FIDEN_OFFSET    7\n#define    RTL8367C_SVLAN_MEMBERCFG28_CTRL2_VS_FIDEN_MASK    0x80\n#define    RTL8367C_SVLAN_MEMBERCFG28_CTRL2_VS_SPRI_OFFSET    4\n#define    RTL8367C_SVLAN_MEMBERCFG28_CTRL2_VS_SPRI_MASK    0x70\n#define    RTL8367C_SVLAN_MEMBERCFG28_CTRL2_VS_FID_MSTI_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG28_CTRL2_VS_FID_MSTI_MASK    0xF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG28_CTRL3    0x0c57\n#define    RTL8367C_SVLAN_MEMBERCFG28_CTRL3_VS_EFID_OFFSET    13\n#define    RTL8367C_SVLAN_MEMBERCFG28_CTRL3_VS_EFID_MASK    0xE000\n#define    RTL8367C_SVLAN_MEMBERCFG28_CTRL3_VS_EFIDEN_OFFSET    12\n#define    RTL8367C_SVLAN_MEMBERCFG28_CTRL3_VS_EFIDEN_MASK    0x1000\n#define    RTL8367C_SVLAN_MEMBERCFG28_CTRL3_VS_SVID_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG28_CTRL3_VS_SVID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG29_CTRL1    0x0c58\n#define    RTL8367C_SVLAN_MEMBERCFG29_CTRL1_VS_UNTAGSET_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG29_CTRL1_VS_UNTAGSET_MASK    0xFF00\n#define    RTL8367C_SVLAN_MEMBERCFG29_CTRL1_VS_SMBR_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG29_CTRL1_VS_SMBR_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG29_CTRL2    0x0c59\n#define    RTL8367C_SVLAN_MEMBERCFG29_CTRL2_VS_FIDEN_OFFSET    7\n#define    RTL8367C_SVLAN_MEMBERCFG29_CTRL2_VS_FIDEN_MASK    0x80\n#define    RTL8367C_SVLAN_MEMBERCFG29_CTRL2_VS_SPRI_OFFSET    4\n#define    RTL8367C_SVLAN_MEMBERCFG29_CTRL2_VS_SPRI_MASK    0x70\n#define    RTL8367C_SVLAN_MEMBERCFG29_CTRL2_VS_FID_MSTI_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG29_CTRL2_VS_FID_MSTI_MASK    0xF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG29_CTRL3    0x0c5a\n#define    RTL8367C_SVLAN_MEMBERCFG29_CTRL3_VS_EFID_OFFSET    13\n#define    RTL8367C_SVLAN_MEMBERCFG29_CTRL3_VS_EFID_MASK    0xE000\n#define    RTL8367C_SVLAN_MEMBERCFG29_CTRL3_VS_EFIDEN_OFFSET    12\n#define    RTL8367C_SVLAN_MEMBERCFG29_CTRL3_VS_EFIDEN_MASK    0x1000\n#define    RTL8367C_SVLAN_MEMBERCFG29_CTRL3_VS_SVID_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG29_CTRL3_VS_SVID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG30_CTRL1    0x0c5b\n#define    RTL8367C_SVLAN_MEMBERCFG30_CTRL1_VS_UNTAGSET_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG30_CTRL1_VS_UNTAGSET_MASK    0xFF00\n#define    RTL8367C_SVLAN_MEMBERCFG30_CTRL1_VS_SMBR_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG30_CTRL1_VS_SMBR_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG30_CTRL2    0x0c5c\n#define    RTL8367C_SVLAN_MEMBERCFG30_CTRL2_VS_FIDEN_OFFSET    7\n#define    RTL8367C_SVLAN_MEMBERCFG30_CTRL2_VS_FIDEN_MASK    0x80\n#define    RTL8367C_SVLAN_MEMBERCFG30_CTRL2_VS_SPRI_OFFSET    4\n#define    RTL8367C_SVLAN_MEMBERCFG30_CTRL2_VS_SPRI_MASK    0x70\n#define    RTL8367C_SVLAN_MEMBERCFG30_CTRL2_VS_FID_MSTI_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG30_CTRL2_VS_FID_MSTI_MASK    0xF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG30_CTRL3    0x0c5d\n#define    RTL8367C_SVLAN_MEMBERCFG30_CTRL3_VS_EFID_OFFSET    13\n#define    RTL8367C_SVLAN_MEMBERCFG30_CTRL3_VS_EFID_MASK    0xE000\n#define    RTL8367C_SVLAN_MEMBERCFG30_CTRL3_VS_EFIDEN_OFFSET    12\n#define    RTL8367C_SVLAN_MEMBERCFG30_CTRL3_VS_EFIDEN_MASK    0x1000\n#define    RTL8367C_SVLAN_MEMBERCFG30_CTRL3_VS_SVID_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG30_CTRL3_VS_SVID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG31_CTRL1    0x0c5e\n#define    RTL8367C_SVLAN_MEMBERCFG31_CTRL1_VS_UNTAGSET_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG31_CTRL1_VS_UNTAGSET_MASK    0xFF00\n#define    RTL8367C_SVLAN_MEMBERCFG31_CTRL1_VS_SMBR_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG31_CTRL1_VS_SMBR_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG31_CTRL2    0x0c5f\n#define    RTL8367C_SVLAN_MEMBERCFG31_CTRL2_VS_FIDEN_OFFSET    7\n#define    RTL8367C_SVLAN_MEMBERCFG31_CTRL2_VS_FIDEN_MASK    0x80\n#define    RTL8367C_SVLAN_MEMBERCFG31_CTRL2_VS_SPRI_OFFSET    4\n#define    RTL8367C_SVLAN_MEMBERCFG31_CTRL2_VS_SPRI_MASK    0x70\n#define    RTL8367C_SVLAN_MEMBERCFG31_CTRL2_VS_FID_MSTI_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG31_CTRL2_VS_FID_MSTI_MASK    0xF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG31_CTRL3    0x0c60\n#define    RTL8367C_SVLAN_MEMBERCFG31_CTRL3_VS_EFID_OFFSET    13\n#define    RTL8367C_SVLAN_MEMBERCFG31_CTRL3_VS_EFID_MASK    0xE000\n#define    RTL8367C_SVLAN_MEMBERCFG31_CTRL3_VS_EFIDEN_OFFSET    12\n#define    RTL8367C_SVLAN_MEMBERCFG31_CTRL3_VS_EFIDEN_MASK    0x1000\n#define    RTL8367C_SVLAN_MEMBERCFG31_CTRL3_VS_SVID_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG31_CTRL3_VS_SVID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG32_CTRL1    0x0c61\n#define    RTL8367C_SVLAN_MEMBERCFG32_CTRL1_VS_UNTAGSET_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG32_CTRL1_VS_UNTAGSET_MASK    0xFF00\n#define    RTL8367C_SVLAN_MEMBERCFG32_CTRL1_VS_SMBR_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG32_CTRL1_VS_SMBR_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG32_CTRL2    0x0c62\n#define    RTL8367C_SVLAN_MEMBERCFG32_CTRL2_VS_FIDEN_OFFSET    7\n#define    RTL8367C_SVLAN_MEMBERCFG32_CTRL2_VS_FIDEN_MASK    0x80\n#define    RTL8367C_SVLAN_MEMBERCFG32_CTRL2_VS_SPRI_OFFSET    4\n#define    RTL8367C_SVLAN_MEMBERCFG32_CTRL2_VS_SPRI_MASK    0x70\n#define    RTL8367C_SVLAN_MEMBERCFG32_CTRL2_VS_FID_MSTI_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG32_CTRL2_VS_FID_MSTI_MASK    0xF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG32_CTRL3    0x0c63\n#define    RTL8367C_SVLAN_MEMBERCFG32_CTRL3_VS_EFID_OFFSET    13\n#define    RTL8367C_SVLAN_MEMBERCFG32_CTRL3_VS_EFID_MASK    0xE000\n#define    RTL8367C_SVLAN_MEMBERCFG32_CTRL3_VS_EFIDEN_OFFSET    12\n#define    RTL8367C_SVLAN_MEMBERCFG32_CTRL3_VS_EFIDEN_MASK    0x1000\n#define    RTL8367C_SVLAN_MEMBERCFG32_CTRL3_VS_SVID_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG32_CTRL3_VS_SVID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG33_CTRL1    0x0c64\n#define    RTL8367C_SVLAN_MEMBERCFG33_CTRL1_VS_UNTAGSET_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG33_CTRL1_VS_UNTAGSET_MASK    0xFF00\n#define    RTL8367C_SVLAN_MEMBERCFG33_CTRL1_VS_SMBR_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG33_CTRL1_VS_SMBR_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG33_CTRL2    0x0c65\n#define    RTL8367C_SVLAN_MEMBERCFG33_CTRL2_VS_FIDEN_OFFSET    7\n#define    RTL8367C_SVLAN_MEMBERCFG33_CTRL2_VS_FIDEN_MASK    0x80\n#define    RTL8367C_SVLAN_MEMBERCFG33_CTRL2_VS_SPRI_OFFSET    4\n#define    RTL8367C_SVLAN_MEMBERCFG33_CTRL2_VS_SPRI_MASK    0x70\n#define    RTL8367C_SVLAN_MEMBERCFG33_CTRL2_VS_FID_MSTI_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG33_CTRL2_VS_FID_MSTI_MASK    0xF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG33_CTRL3    0x0c66\n#define    RTL8367C_SVLAN_MEMBERCFG33_CTRL3_VS_EFID_OFFSET    13\n#define    RTL8367C_SVLAN_MEMBERCFG33_CTRL3_VS_EFID_MASK    0xE000\n#define    RTL8367C_SVLAN_MEMBERCFG33_CTRL3_VS_EFIDEN_OFFSET    12\n#define    RTL8367C_SVLAN_MEMBERCFG33_CTRL3_VS_EFIDEN_MASK    0x1000\n#define    RTL8367C_SVLAN_MEMBERCFG33_CTRL3_VS_SVID_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG33_CTRL3_VS_SVID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG34_CTRL1    0x0c67\n#define    RTL8367C_SVLAN_MEMBERCFG34_CTRL1_VS_UNTAGSET_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG34_CTRL1_VS_UNTAGSET_MASK    0xFF00\n#define    RTL8367C_SVLAN_MEMBERCFG34_CTRL1_VS_SMBR_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG34_CTRL1_VS_SMBR_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG34_CTRL2    0x0c68\n#define    RTL8367C_SVLAN_MEMBERCFG34_CTRL2_VS_FIDEN_OFFSET    7\n#define    RTL8367C_SVLAN_MEMBERCFG34_CTRL2_VS_FIDEN_MASK    0x80\n#define    RTL8367C_SVLAN_MEMBERCFG34_CTRL2_VS_SPRI_OFFSET    4\n#define    RTL8367C_SVLAN_MEMBERCFG34_CTRL2_VS_SPRI_MASK    0x70\n#define    RTL8367C_SVLAN_MEMBERCFG34_CTRL2_VS_FID_MSTI_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG34_CTRL2_VS_FID_MSTI_MASK    0xF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG34_CTRL3    0x0c69\n#define    RTL8367C_SVLAN_MEMBERCFG34_CTRL3_VS_EFID_OFFSET    13\n#define    RTL8367C_SVLAN_MEMBERCFG34_CTRL3_VS_EFID_MASK    0xE000\n#define    RTL8367C_SVLAN_MEMBERCFG34_CTRL3_VS_EFIDEN_OFFSET    12\n#define    RTL8367C_SVLAN_MEMBERCFG34_CTRL3_VS_EFIDEN_MASK    0x1000\n#define    RTL8367C_SVLAN_MEMBERCFG34_CTRL3_VS_SVID_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG34_CTRL3_VS_SVID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG35_CTRL1    0x0c6a\n#define    RTL8367C_SVLAN_MEMBERCFG35_CTRL1_VS_UNTAGSET_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG35_CTRL1_VS_UNTAGSET_MASK    0xFF00\n#define    RTL8367C_SVLAN_MEMBERCFG35_CTRL1_VS_SMBR_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG35_CTRL1_VS_SMBR_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG35_CTRL2    0x0c6b\n#define    RTL8367C_SVLAN_MEMBERCFG35_CTRL2_VS_FIDEN_OFFSET    7\n#define    RTL8367C_SVLAN_MEMBERCFG35_CTRL2_VS_FIDEN_MASK    0x80\n#define    RTL8367C_SVLAN_MEMBERCFG35_CTRL2_VS_SPRI_OFFSET    4\n#define    RTL8367C_SVLAN_MEMBERCFG35_CTRL2_VS_SPRI_MASK    0x70\n#define    RTL8367C_SVLAN_MEMBERCFG35_CTRL2_VS_FID_MSTI_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG35_CTRL2_VS_FID_MSTI_MASK    0xF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG35_CTRL3    0x0c6c\n#define    RTL8367C_SVLAN_MEMBERCFG35_CTRL3_VS_EFID_OFFSET    13\n#define    RTL8367C_SVLAN_MEMBERCFG35_CTRL3_VS_EFID_MASK    0xE000\n#define    RTL8367C_SVLAN_MEMBERCFG35_CTRL3_VS_EFIDEN_OFFSET    12\n#define    RTL8367C_SVLAN_MEMBERCFG35_CTRL3_VS_EFIDEN_MASK    0x1000\n#define    RTL8367C_SVLAN_MEMBERCFG35_CTRL3_VS_SVID_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG35_CTRL3_VS_SVID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG36_CTRL1    0x0c6d\n#define    RTL8367C_SVLAN_MEMBERCFG36_CTRL1_VS_UNTAGSET_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG36_CTRL1_VS_UNTAGSET_MASK    0xFF00\n#define    RTL8367C_SVLAN_MEMBERCFG36_CTRL1_VS_SMBR_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG36_CTRL1_VS_SMBR_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG36_CTRL2    0x0c6e\n#define    RTL8367C_SVLAN_MEMBERCFG36_CTRL2_VS_FIDEN_OFFSET    7\n#define    RTL8367C_SVLAN_MEMBERCFG36_CTRL2_VS_FIDEN_MASK    0x80\n#define    RTL8367C_SVLAN_MEMBERCFG36_CTRL2_VS_SPRI_OFFSET    4\n#define    RTL8367C_SVLAN_MEMBERCFG36_CTRL2_VS_SPRI_MASK    0x70\n#define    RTL8367C_SVLAN_MEMBERCFG36_CTRL2_VS_FID_MSTI_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG36_CTRL2_VS_FID_MSTI_MASK    0xF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG36_CTRL3    0x0c6f\n#define    RTL8367C_SVLAN_MEMBERCFG36_CTRL3_VS_EFID_OFFSET    13\n#define    RTL8367C_SVLAN_MEMBERCFG36_CTRL3_VS_EFID_MASK    0xE000\n#define    RTL8367C_SVLAN_MEMBERCFG36_CTRL3_VS_EFIDEN_OFFSET    12\n#define    RTL8367C_SVLAN_MEMBERCFG36_CTRL3_VS_EFIDEN_MASK    0x1000\n#define    RTL8367C_SVLAN_MEMBERCFG36_CTRL3_VS_SVID_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG36_CTRL3_VS_SVID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG37_CTRL1    0x0c70\n#define    RTL8367C_SVLAN_MEMBERCFG37_CTRL1_VS_UNTAGSET_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG37_CTRL1_VS_UNTAGSET_MASK    0xFF00\n#define    RTL8367C_SVLAN_MEMBERCFG37_CTRL1_VS_SMBR_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG37_CTRL1_VS_SMBR_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG37_CTRL2    0x0c71\n#define    RTL8367C_SVLAN_MEMBERCFG37_CTRL2_VS_FIDEN_OFFSET    7\n#define    RTL8367C_SVLAN_MEMBERCFG37_CTRL2_VS_FIDEN_MASK    0x80\n#define    RTL8367C_SVLAN_MEMBERCFG37_CTRL2_VS_SPRI_OFFSET    4\n#define    RTL8367C_SVLAN_MEMBERCFG37_CTRL2_VS_SPRI_MASK    0x70\n#define    RTL8367C_SVLAN_MEMBERCFG37_CTRL2_VS_FID_MSTI_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG37_CTRL2_VS_FID_MSTI_MASK    0xF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG37_CTRL3    0x0c72\n#define    RTL8367C_SVLAN_MEMBERCFG37_CTRL3_VS_EFID_OFFSET    13\n#define    RTL8367C_SVLAN_MEMBERCFG37_CTRL3_VS_EFID_MASK    0xE000\n#define    RTL8367C_SVLAN_MEMBERCFG37_CTRL3_VS_EFIDEN_OFFSET    12\n#define    RTL8367C_SVLAN_MEMBERCFG37_CTRL3_VS_EFIDEN_MASK    0x1000\n#define    RTL8367C_SVLAN_MEMBERCFG37_CTRL3_VS_SVID_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG37_CTRL3_VS_SVID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG38_CTRL1    0x0c73\n#define    RTL8367C_SVLAN_MEMBERCFG38_CTRL1_VS_UNTAGSET_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG38_CTRL1_VS_UNTAGSET_MASK    0xFF00\n#define    RTL8367C_SVLAN_MEMBERCFG38_CTRL1_VS_SMBR_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG38_CTRL1_VS_SMBR_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG38_CTRL2    0x0c74\n#define    RTL8367C_SVLAN_MEMBERCFG38_CTRL2_VS_FIDEN_OFFSET    7\n#define    RTL8367C_SVLAN_MEMBERCFG38_CTRL2_VS_FIDEN_MASK    0x80\n#define    RTL8367C_SVLAN_MEMBERCFG38_CTRL2_VS_SPRI_OFFSET    4\n#define    RTL8367C_SVLAN_MEMBERCFG38_CTRL2_VS_SPRI_MASK    0x70\n#define    RTL8367C_SVLAN_MEMBERCFG38_CTRL2_VS_FID_MSTI_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG38_CTRL2_VS_FID_MSTI_MASK    0xF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG38_CTRL3    0x0c75\n#define    RTL8367C_SVLAN_MEMBERCFG38_CTRL3_VS_EFID_OFFSET    13\n#define    RTL8367C_SVLAN_MEMBERCFG38_CTRL3_VS_EFID_MASK    0xE000\n#define    RTL8367C_SVLAN_MEMBERCFG38_CTRL3_VS_EFIDEN_OFFSET    12\n#define    RTL8367C_SVLAN_MEMBERCFG38_CTRL3_VS_EFIDEN_MASK    0x1000\n#define    RTL8367C_SVLAN_MEMBERCFG38_CTRL3_VS_SVID_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG38_CTRL3_VS_SVID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG39_CTRL1    0x0c76\n#define    RTL8367C_SVLAN_MEMBERCFG39_CTRL1_VS_UNTAGSET_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG39_CTRL1_VS_UNTAGSET_MASK    0xFF00\n#define    RTL8367C_SVLAN_MEMBERCFG39_CTRL1_VS_SMBR_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG39_CTRL1_VS_SMBR_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG39_CTRL2    0x0c77\n#define    RTL8367C_SVLAN_MEMBERCFG39_CTRL2_VS_FIDEN_OFFSET    7\n#define    RTL8367C_SVLAN_MEMBERCFG39_CTRL2_VS_FIDEN_MASK    0x80\n#define    RTL8367C_SVLAN_MEMBERCFG39_CTRL2_VS_SPRI_OFFSET    4\n#define    RTL8367C_SVLAN_MEMBERCFG39_CTRL2_VS_SPRI_MASK    0x70\n#define    RTL8367C_SVLAN_MEMBERCFG39_CTRL2_VS_FID_MSTI_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG39_CTRL2_VS_FID_MSTI_MASK    0xF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG39_CTRL3    0x0c78\n#define    RTL8367C_SVLAN_MEMBERCFG39_CTRL3_VS_EFID_OFFSET    13\n#define    RTL8367C_SVLAN_MEMBERCFG39_CTRL3_VS_EFID_MASK    0xE000\n#define    RTL8367C_SVLAN_MEMBERCFG39_CTRL3_VS_EFIDEN_OFFSET    12\n#define    RTL8367C_SVLAN_MEMBERCFG39_CTRL3_VS_EFIDEN_MASK    0x1000\n#define    RTL8367C_SVLAN_MEMBERCFG39_CTRL3_VS_SVID_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG39_CTRL3_VS_SVID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG40_CTRL1    0x0c79\n#define    RTL8367C_SVLAN_MEMBERCFG40_CTRL1_VS_UNTAGSET_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG40_CTRL1_VS_UNTAGSET_MASK    0xFF00\n#define    RTL8367C_SVLAN_MEMBERCFG40_CTRL1_VS_SMBR_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG40_CTRL1_VS_SMBR_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG40_CTRL2    0x0c7a\n#define    RTL8367C_SVLAN_MEMBERCFG40_CTRL2_VS_FIDEN_OFFSET    7\n#define    RTL8367C_SVLAN_MEMBERCFG40_CTRL2_VS_FIDEN_MASK    0x80\n#define    RTL8367C_SVLAN_MEMBERCFG40_CTRL2_VS_SPRI_OFFSET    4\n#define    RTL8367C_SVLAN_MEMBERCFG40_CTRL2_VS_SPRI_MASK    0x70\n#define    RTL8367C_SVLAN_MEMBERCFG40_CTRL2_VS_FID_MSTI_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG40_CTRL2_VS_FID_MSTI_MASK    0xF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG40_CTRL3    0x0c7b\n#define    RTL8367C_SVLAN_MEMBERCFG40_CTRL3_VS_EFID_OFFSET    13\n#define    RTL8367C_SVLAN_MEMBERCFG40_CTRL3_VS_EFID_MASK    0xE000\n#define    RTL8367C_SVLAN_MEMBERCFG40_CTRL3_VS_EFIDEN_OFFSET    12\n#define    RTL8367C_SVLAN_MEMBERCFG40_CTRL3_VS_EFIDEN_MASK    0x1000\n#define    RTL8367C_SVLAN_MEMBERCFG40_CTRL3_VS_SVID_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG40_CTRL3_VS_SVID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG41_CTRL1    0x0c7c\n#define    RTL8367C_SVLAN_MEMBERCFG41_CTRL1_VS_UNTAGSET_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG41_CTRL1_VS_UNTAGSET_MASK    0xFF00\n#define    RTL8367C_SVLAN_MEMBERCFG41_CTRL1_VS_SMBR_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG41_CTRL1_VS_SMBR_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG41_CTRL2    0x0c7d\n#define    RTL8367C_SVLAN_MEMBERCFG41_CTRL2_VS_FIDEN_OFFSET    7\n#define    RTL8367C_SVLAN_MEMBERCFG41_CTRL2_VS_FIDEN_MASK    0x80\n#define    RTL8367C_SVLAN_MEMBERCFG41_CTRL2_VS_SPRI_OFFSET    4\n#define    RTL8367C_SVLAN_MEMBERCFG41_CTRL2_VS_SPRI_MASK    0x70\n#define    RTL8367C_SVLAN_MEMBERCFG41_CTRL2_VS_FID_MSTI_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG41_CTRL2_VS_FID_MSTI_MASK    0xF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG41_CTRL3    0x0c7e\n#define    RTL8367C_SVLAN_MEMBERCFG41_CTRL3_VS_EFID_OFFSET    13\n#define    RTL8367C_SVLAN_MEMBERCFG41_CTRL3_VS_EFID_MASK    0xE000\n#define    RTL8367C_SVLAN_MEMBERCFG41_CTRL3_VS_EFIDEN_OFFSET    12\n#define    RTL8367C_SVLAN_MEMBERCFG41_CTRL3_VS_EFIDEN_MASK    0x1000\n#define    RTL8367C_SVLAN_MEMBERCFG41_CTRL3_VS_SVID_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG41_CTRL3_VS_SVID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG42_CTRL1    0x0c7f\n#define    RTL8367C_SVLAN_MEMBERCFG42_CTRL1_VS_UNTAGSET_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG42_CTRL1_VS_UNTAGSET_MASK    0xFF00\n#define    RTL8367C_SVLAN_MEMBERCFG42_CTRL1_VS_SMBR_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG42_CTRL1_VS_SMBR_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG42_CTRL2    0x0c80\n#define    RTL8367C_SVLAN_MEMBERCFG42_CTRL2_VS_FIDEN_OFFSET    7\n#define    RTL8367C_SVLAN_MEMBERCFG42_CTRL2_VS_FIDEN_MASK    0x80\n#define    RTL8367C_SVLAN_MEMBERCFG42_CTRL2_VS_SPRI_OFFSET    4\n#define    RTL8367C_SVLAN_MEMBERCFG42_CTRL2_VS_SPRI_MASK    0x70\n#define    RTL8367C_SVLAN_MEMBERCFG42_CTRL2_VS_FID_MSTI_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG42_CTRL2_VS_FID_MSTI_MASK    0xF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG42_CTRL3    0x0c81\n#define    RTL8367C_SVLAN_MEMBERCFG42_CTRL3_VS_EFID_OFFSET    13\n#define    RTL8367C_SVLAN_MEMBERCFG42_CTRL3_VS_EFID_MASK    0xE000\n#define    RTL8367C_SVLAN_MEMBERCFG42_CTRL3_VS_EFIDEN_OFFSET    12\n#define    RTL8367C_SVLAN_MEMBERCFG42_CTRL3_VS_EFIDEN_MASK    0x1000\n#define    RTL8367C_SVLAN_MEMBERCFG42_CTRL3_VS_SVID_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG42_CTRL3_VS_SVID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG43_CTRL1    0x0c82\n#define    RTL8367C_SVLAN_MEMBERCFG43_CTRL1_VS_UNTAGSET_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG43_CTRL1_VS_UNTAGSET_MASK    0xFF00\n#define    RTL8367C_SVLAN_MEMBERCFG43_CTRL1_VS_SMBR_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG43_CTRL1_VS_SMBR_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG43_CTRL2    0x0c83\n#define    RTL8367C_SVLAN_MEMBERCFG43_CTRL2_VS_FIDEN_OFFSET    7\n#define    RTL8367C_SVLAN_MEMBERCFG43_CTRL2_VS_FIDEN_MASK    0x80\n#define    RTL8367C_SVLAN_MEMBERCFG43_CTRL2_VS_SPRI_OFFSET    4\n#define    RTL8367C_SVLAN_MEMBERCFG43_CTRL2_VS_SPRI_MASK    0x70\n#define    RTL8367C_SVLAN_MEMBERCFG43_CTRL2_VS_FID_MSTI_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG43_CTRL2_VS_FID_MSTI_MASK    0xF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG43_CTRL3    0x0c84\n#define    RTL8367C_SVLAN_MEMBERCFG43_CTRL3_VS_EFID_OFFSET    13\n#define    RTL8367C_SVLAN_MEMBERCFG43_CTRL3_VS_EFID_MASK    0xE000\n#define    RTL8367C_SVLAN_MEMBERCFG43_CTRL3_VS_EFIDEN_OFFSET    12\n#define    RTL8367C_SVLAN_MEMBERCFG43_CTRL3_VS_EFIDEN_MASK    0x1000\n#define    RTL8367C_SVLAN_MEMBERCFG43_CTRL3_VS_SVID_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG43_CTRL3_VS_SVID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG44_CTRL1    0x0c85\n#define    RTL8367C_SVLAN_MEMBERCFG44_CTRL1_VS_UNTAGSET_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG44_CTRL1_VS_UNTAGSET_MASK    0xFF00\n#define    RTL8367C_SVLAN_MEMBERCFG44_CTRL1_VS_SMBR_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG44_CTRL1_VS_SMBR_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG44_CTRL2    0x0c86\n#define    RTL8367C_SVLAN_MEMBERCFG44_CTRL2_VS_FIDEN_OFFSET    7\n#define    RTL8367C_SVLAN_MEMBERCFG44_CTRL2_VS_FIDEN_MASK    0x80\n#define    RTL8367C_SVLAN_MEMBERCFG44_CTRL2_VS_SPRI_OFFSET    4\n#define    RTL8367C_SVLAN_MEMBERCFG44_CTRL2_VS_SPRI_MASK    0x70\n#define    RTL8367C_SVLAN_MEMBERCFG44_CTRL2_VS_FID_MSTI_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG44_CTRL2_VS_FID_MSTI_MASK    0xF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG44_CTRL3    0x0c87\n#define    RTL8367C_SVLAN_MEMBERCFG44_CTRL3_VS_EFID_OFFSET    13\n#define    RTL8367C_SVLAN_MEMBERCFG44_CTRL3_VS_EFID_MASK    0xE000\n#define    RTL8367C_SVLAN_MEMBERCFG44_CTRL3_VS_EFIDEN_OFFSET    12\n#define    RTL8367C_SVLAN_MEMBERCFG44_CTRL3_VS_EFIDEN_MASK    0x1000\n#define    RTL8367C_SVLAN_MEMBERCFG44_CTRL3_VS_SVID_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG44_CTRL3_VS_SVID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG45_CTRL1    0x0c88\n#define    RTL8367C_SVLAN_MEMBERCFG45_CTRL1_VS_UNTAGSET_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG45_CTRL1_VS_UNTAGSET_MASK    0xFF00\n#define    RTL8367C_SVLAN_MEMBERCFG45_CTRL1_VS_SMBR_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG45_CTRL1_VS_SMBR_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG45_CTRL2    0x0c89\n#define    RTL8367C_SVLAN_MEMBERCFG45_CTRL2_VS_FIDEN_OFFSET    7\n#define    RTL8367C_SVLAN_MEMBERCFG45_CTRL2_VS_FIDEN_MASK    0x80\n#define    RTL8367C_SVLAN_MEMBERCFG45_CTRL2_VS_SPRI_OFFSET    4\n#define    RTL8367C_SVLAN_MEMBERCFG45_CTRL2_VS_SPRI_MASK    0x70\n#define    RTL8367C_SVLAN_MEMBERCFG45_CTRL2_VS_FID_MSTI_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG45_CTRL2_VS_FID_MSTI_MASK    0xF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG45_CTRL3    0x0c8a\n#define    RTL8367C_SVLAN_MEMBERCFG45_CTRL3_VS_EFID_OFFSET    13\n#define    RTL8367C_SVLAN_MEMBERCFG45_CTRL3_VS_EFID_MASK    0xE000\n#define    RTL8367C_SVLAN_MEMBERCFG45_CTRL3_VS_EFIDEN_OFFSET    12\n#define    RTL8367C_SVLAN_MEMBERCFG45_CTRL3_VS_EFIDEN_MASK    0x1000\n#define    RTL8367C_SVLAN_MEMBERCFG45_CTRL3_VS_SVID_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG45_CTRL3_VS_SVID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG46_CTRL1    0x0c8b\n#define    RTL8367C_SVLAN_MEMBERCFG46_CTRL1_VS_UNTAGSET_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG46_CTRL1_VS_UNTAGSET_MASK    0xFF00\n#define    RTL8367C_SVLAN_MEMBERCFG46_CTRL1_VS_SMBR_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG46_CTRL1_VS_SMBR_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG46_CTRL2    0x0c8c\n#define    RTL8367C_SVLAN_MEMBERCFG46_CTRL2_VS_FIDEN_OFFSET    7\n#define    RTL8367C_SVLAN_MEMBERCFG46_CTRL2_VS_FIDEN_MASK    0x80\n#define    RTL8367C_SVLAN_MEMBERCFG46_CTRL2_VS_SPRI_OFFSET    4\n#define    RTL8367C_SVLAN_MEMBERCFG46_CTRL2_VS_SPRI_MASK    0x70\n#define    RTL8367C_SVLAN_MEMBERCFG46_CTRL2_VS_FID_MSTI_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG46_CTRL2_VS_FID_MSTI_MASK    0xF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG46_CTRL3    0x0c8d\n#define    RTL8367C_SVLAN_MEMBERCFG46_CTRL3_VS_EFID_OFFSET    13\n#define    RTL8367C_SVLAN_MEMBERCFG46_CTRL3_VS_EFID_MASK    0xE000\n#define    RTL8367C_SVLAN_MEMBERCFG46_CTRL3_VS_EFIDEN_OFFSET    12\n#define    RTL8367C_SVLAN_MEMBERCFG46_CTRL3_VS_EFIDEN_MASK    0x1000\n#define    RTL8367C_SVLAN_MEMBERCFG46_CTRL3_VS_SVID_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG46_CTRL3_VS_SVID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG47_CTRL1    0x0c8e\n#define    RTL8367C_SVLAN_MEMBERCFG47_CTRL1_VS_UNTAGSET_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG47_CTRL1_VS_UNTAGSET_MASK    0xFF00\n#define    RTL8367C_SVLAN_MEMBERCFG47_CTRL1_VS_SMBR_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG47_CTRL1_VS_SMBR_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG47_CTRL2    0x0c8f\n#define    RTL8367C_SVLAN_MEMBERCFG47_CTRL2_VS_FIDEN_OFFSET    7\n#define    RTL8367C_SVLAN_MEMBERCFG47_CTRL2_VS_FIDEN_MASK    0x80\n#define    RTL8367C_SVLAN_MEMBERCFG47_CTRL2_VS_SPRI_OFFSET    4\n#define    RTL8367C_SVLAN_MEMBERCFG47_CTRL2_VS_SPRI_MASK    0x70\n#define    RTL8367C_SVLAN_MEMBERCFG47_CTRL2_VS_FID_MSTI_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG47_CTRL2_VS_FID_MSTI_MASK    0xF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG47_CTRL3    0x0c90\n#define    RTL8367C_SVLAN_MEMBERCFG47_CTRL3_VS_EFID_OFFSET    13\n#define    RTL8367C_SVLAN_MEMBERCFG47_CTRL3_VS_EFID_MASK    0xE000\n#define    RTL8367C_SVLAN_MEMBERCFG47_CTRL3_VS_EFIDEN_OFFSET    12\n#define    RTL8367C_SVLAN_MEMBERCFG47_CTRL3_VS_EFIDEN_MASK    0x1000\n#define    RTL8367C_SVLAN_MEMBERCFG47_CTRL3_VS_SVID_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG47_CTRL3_VS_SVID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG48_CTRL1    0x0c91\n#define    RTL8367C_SVLAN_MEMBERCFG48_CTRL1_VS_UNTAGSET_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG48_CTRL1_VS_UNTAGSET_MASK    0xFF00\n#define    RTL8367C_SVLAN_MEMBERCFG48_CTRL1_VS_SMBR_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG48_CTRL1_VS_SMBR_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG48_CTRL2    0x0c92\n#define    RTL8367C_SVLAN_MEMBERCFG48_CTRL2_VS_FIDEN_OFFSET    7\n#define    RTL8367C_SVLAN_MEMBERCFG48_CTRL2_VS_FIDEN_MASK    0x80\n#define    RTL8367C_SVLAN_MEMBERCFG48_CTRL2_VS_SPRI_OFFSET    4\n#define    RTL8367C_SVLAN_MEMBERCFG48_CTRL2_VS_SPRI_MASK    0x70\n#define    RTL8367C_SVLAN_MEMBERCFG48_CTRL2_VS_FID_MSTI_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG48_CTRL2_VS_FID_MSTI_MASK    0xF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG48_CTRL3    0x0c93\n#define    RTL8367C_SVLAN_MEMBERCFG48_CTRL3_VS_EFID_OFFSET    13\n#define    RTL8367C_SVLAN_MEMBERCFG48_CTRL3_VS_EFID_MASK    0xE000\n#define    RTL8367C_SVLAN_MEMBERCFG48_CTRL3_VS_EFIDEN_OFFSET    12\n#define    RTL8367C_SVLAN_MEMBERCFG48_CTRL3_VS_EFIDEN_MASK    0x1000\n#define    RTL8367C_SVLAN_MEMBERCFG48_CTRL3_VS_SVID_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG48_CTRL3_VS_SVID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG49_CTRL1    0x0c94\n#define    RTL8367C_SVLAN_MEMBERCFG49_CTRL1_VS_UNTAGSET_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG49_CTRL1_VS_UNTAGSET_MASK    0xFF00\n#define    RTL8367C_SVLAN_MEMBERCFG49_CTRL1_VS_SMBR_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG49_CTRL1_VS_SMBR_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG49_CTRL2    0x0c95\n#define    RTL8367C_SVLAN_MEMBERCFG49_CTRL2_VS_FIDEN_OFFSET    7\n#define    RTL8367C_SVLAN_MEMBERCFG49_CTRL2_VS_FIDEN_MASK    0x80\n#define    RTL8367C_SVLAN_MEMBERCFG49_CTRL2_VS_SPRI_OFFSET    4\n#define    RTL8367C_SVLAN_MEMBERCFG49_CTRL2_VS_SPRI_MASK    0x70\n#define    RTL8367C_SVLAN_MEMBERCFG49_CTRL2_VS_FID_MSTI_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG49_CTRL2_VS_FID_MSTI_MASK    0xF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG49_CTRL3    0x0c96\n#define    RTL8367C_SVLAN_MEMBERCFG49_CTRL3_VS_EFID_OFFSET    13\n#define    RTL8367C_SVLAN_MEMBERCFG49_CTRL3_VS_EFID_MASK    0xE000\n#define    RTL8367C_SVLAN_MEMBERCFG49_CTRL3_VS_EFIDEN_OFFSET    12\n#define    RTL8367C_SVLAN_MEMBERCFG49_CTRL3_VS_EFIDEN_MASK    0x1000\n#define    RTL8367C_SVLAN_MEMBERCFG49_CTRL3_VS_SVID_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG49_CTRL3_VS_SVID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG50_CTRL1    0x0c97\n#define    RTL8367C_SVLAN_MEMBERCFG50_CTRL1_VS_UNTAGSET_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG50_CTRL1_VS_UNTAGSET_MASK    0xFF00\n#define    RTL8367C_SVLAN_MEMBERCFG50_CTRL1_VS_SMBR_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG50_CTRL1_VS_SMBR_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG50_CTRL2    0x0c98\n#define    RTL8367C_SVLAN_MEMBERCFG50_CTRL2_VS_FIDEN_OFFSET    7\n#define    RTL8367C_SVLAN_MEMBERCFG50_CTRL2_VS_FIDEN_MASK    0x80\n#define    RTL8367C_SVLAN_MEMBERCFG50_CTRL2_VS_SPRI_OFFSET    4\n#define    RTL8367C_SVLAN_MEMBERCFG50_CTRL2_VS_SPRI_MASK    0x70\n#define    RTL8367C_SVLAN_MEMBERCFG50_CTRL2_VS_FID_MSTI_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG50_CTRL2_VS_FID_MSTI_MASK    0xF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG50_CTRL3    0x0c99\n#define    RTL8367C_SVLAN_MEMBERCFG50_CTRL3_VS_EFID_OFFSET    13\n#define    RTL8367C_SVLAN_MEMBERCFG50_CTRL3_VS_EFID_MASK    0xE000\n#define    RTL8367C_SVLAN_MEMBERCFG50_CTRL3_VS_EFIDEN_OFFSET    12\n#define    RTL8367C_SVLAN_MEMBERCFG50_CTRL3_VS_EFIDEN_MASK    0x1000\n#define    RTL8367C_SVLAN_MEMBERCFG50_CTRL3_VS_SVID_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG50_CTRL3_VS_SVID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG51_CTRL1    0x0c9a\n#define    RTL8367C_SVLAN_MEMBERCFG51_CTRL1_VS_UNTAGSET_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG51_CTRL1_VS_UNTAGSET_MASK    0xFF00\n#define    RTL8367C_SVLAN_MEMBERCFG51_CTRL1_VS_SMBR_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG51_CTRL1_VS_SMBR_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG51_CTRL2    0x0c9b\n#define    RTL8367C_SVLAN_MEMBERCFG51_CTRL2_VS_FIDEN_OFFSET    7\n#define    RTL8367C_SVLAN_MEMBERCFG51_CTRL2_VS_FIDEN_MASK    0x80\n#define    RTL8367C_SVLAN_MEMBERCFG51_CTRL2_VS_SPRI_OFFSET    4\n#define    RTL8367C_SVLAN_MEMBERCFG51_CTRL2_VS_SPRI_MASK    0x70\n#define    RTL8367C_SVLAN_MEMBERCFG51_CTRL2_VS_FID_MSTI_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG51_CTRL2_VS_FID_MSTI_MASK    0xF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG51_CTRL3    0x0c9c\n#define    RTL8367C_SVLAN_MEMBERCFG51_CTRL3_VS_EFID_OFFSET    13\n#define    RTL8367C_SVLAN_MEMBERCFG51_CTRL3_VS_EFID_MASK    0xE000\n#define    RTL8367C_SVLAN_MEMBERCFG51_CTRL3_VS_EFIDEN_OFFSET    12\n#define    RTL8367C_SVLAN_MEMBERCFG51_CTRL3_VS_EFIDEN_MASK    0x1000\n#define    RTL8367C_SVLAN_MEMBERCFG51_CTRL3_VS_SVID_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG51_CTRL3_VS_SVID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG52_CTRL1    0x0c9d\n#define    RTL8367C_SVLAN_MEMBERCFG52_CTRL1_VS_UNTAGSET_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG52_CTRL1_VS_UNTAGSET_MASK    0xFF00\n#define    RTL8367C_SVLAN_MEMBERCFG52_CTRL1_VS_SMBR_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG52_CTRL1_VS_SMBR_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG52_CTRL2    0x0c9e\n#define    RTL8367C_SVLAN_MEMBERCFG52_CTRL2_VS_FIDEN_OFFSET    7\n#define    RTL8367C_SVLAN_MEMBERCFG52_CTRL2_VS_FIDEN_MASK    0x80\n#define    RTL8367C_SVLAN_MEMBERCFG52_CTRL2_VS_SPRI_OFFSET    4\n#define    RTL8367C_SVLAN_MEMBERCFG52_CTRL2_VS_SPRI_MASK    0x70\n#define    RTL8367C_SVLAN_MEMBERCFG52_CTRL2_VS_FID_MSTI_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG52_CTRL2_VS_FID_MSTI_MASK    0xF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG52_CTRL3    0x0c9f\n#define    RTL8367C_SVLAN_MEMBERCFG52_CTRL3_VS_EFID_OFFSET    13\n#define    RTL8367C_SVLAN_MEMBERCFG52_CTRL3_VS_EFID_MASK    0xE000\n#define    RTL8367C_SVLAN_MEMBERCFG52_CTRL3_VS_EFIDEN_OFFSET    12\n#define    RTL8367C_SVLAN_MEMBERCFG52_CTRL3_VS_EFIDEN_MASK    0x1000\n#define    RTL8367C_SVLAN_MEMBERCFG52_CTRL3_VS_SVID_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG52_CTRL3_VS_SVID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG53_CTRL1    0x0ca0\n#define    RTL8367C_SVLAN_MEMBERCFG53_CTRL1_VS_UNTAGSET_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG53_CTRL1_VS_UNTAGSET_MASK    0xFF00\n#define    RTL8367C_SVLAN_MEMBERCFG53_CTRL1_VS_SMBR_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG53_CTRL1_VS_SMBR_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG53_CTRL2    0x0ca1\n#define    RTL8367C_SVLAN_MEMBERCFG53_CTRL2_VS_FIDEN_OFFSET    7\n#define    RTL8367C_SVLAN_MEMBERCFG53_CTRL2_VS_FIDEN_MASK    0x80\n#define    RTL8367C_SVLAN_MEMBERCFG53_CTRL2_VS_SPRI_OFFSET    4\n#define    RTL8367C_SVLAN_MEMBERCFG53_CTRL2_VS_SPRI_MASK    0x70\n#define    RTL8367C_SVLAN_MEMBERCFG53_CTRL2_VS_FID_MSTI_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG53_CTRL2_VS_FID_MSTI_MASK    0xF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG53_CTRL3    0x0ca2\n#define    RTL8367C_SVLAN_MEMBERCFG53_CTRL3_VS_EFID_OFFSET    13\n#define    RTL8367C_SVLAN_MEMBERCFG53_CTRL3_VS_EFID_MASK    0xE000\n#define    RTL8367C_SVLAN_MEMBERCFG53_CTRL3_VS_EFIDEN_OFFSET    12\n#define    RTL8367C_SVLAN_MEMBERCFG53_CTRL3_VS_EFIDEN_MASK    0x1000\n#define    RTL8367C_SVLAN_MEMBERCFG53_CTRL3_VS_SVID_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG53_CTRL3_VS_SVID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG54_CTRL1    0x0ca3\n#define    RTL8367C_SVLAN_MEMBERCFG54_CTRL1_VS_UNTAGSET_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG54_CTRL1_VS_UNTAGSET_MASK    0xFF00\n#define    RTL8367C_SVLAN_MEMBERCFG54_CTRL1_VS_SMBR_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG54_CTRL1_VS_SMBR_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG54_CTRL2    0x0ca4\n#define    RTL8367C_SVLAN_MEMBERCFG54_CTRL2_VS_FIDEN_OFFSET    7\n#define    RTL8367C_SVLAN_MEMBERCFG54_CTRL2_VS_FIDEN_MASK    0x80\n#define    RTL8367C_SVLAN_MEMBERCFG54_CTRL2_VS_SPRI_OFFSET    4\n#define    RTL8367C_SVLAN_MEMBERCFG54_CTRL2_VS_SPRI_MASK    0x70\n#define    RTL8367C_SVLAN_MEMBERCFG54_CTRL2_VS_FID_MSTI_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG54_CTRL2_VS_FID_MSTI_MASK    0xF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG54_CTRL3    0x0ca5\n#define    RTL8367C_SVLAN_MEMBERCFG54_CTRL3_VS_EFID_OFFSET    13\n#define    RTL8367C_SVLAN_MEMBERCFG54_CTRL3_VS_EFID_MASK    0xE000\n#define    RTL8367C_SVLAN_MEMBERCFG54_CTRL3_VS_EFIDEN_OFFSET    12\n#define    RTL8367C_SVLAN_MEMBERCFG54_CTRL3_VS_EFIDEN_MASK    0x1000\n#define    RTL8367C_SVLAN_MEMBERCFG54_CTRL3_VS_SVID_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG54_CTRL3_VS_SVID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG55_CTRL1    0x0ca6\n#define    RTL8367C_SVLAN_MEMBERCFG55_CTRL1_VS_UNTAGSET_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG55_CTRL1_VS_UNTAGSET_MASK    0xFF00\n#define    RTL8367C_SVLAN_MEMBERCFG55_CTRL1_VS_SMBR_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG55_CTRL1_VS_SMBR_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG55_CTRL2    0x0ca7\n#define    RTL8367C_SVLAN_MEMBERCFG55_CTRL2_VS_FIDEN_OFFSET    7\n#define    RTL8367C_SVLAN_MEMBERCFG55_CTRL2_VS_FIDEN_MASK    0x80\n#define    RTL8367C_SVLAN_MEMBERCFG55_CTRL2_VS_SPRI_OFFSET    4\n#define    RTL8367C_SVLAN_MEMBERCFG55_CTRL2_VS_SPRI_MASK    0x70\n#define    RTL8367C_SVLAN_MEMBERCFG55_CTRL2_VS_FID_MSTI_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG55_CTRL2_VS_FID_MSTI_MASK    0xF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG55_CTRL3    0x0ca8\n#define    RTL8367C_SVLAN_MEMBERCFG55_CTRL3_VS_EFID_OFFSET    13\n#define    RTL8367C_SVLAN_MEMBERCFG55_CTRL3_VS_EFID_MASK    0xE000\n#define    RTL8367C_SVLAN_MEMBERCFG55_CTRL3_VS_EFIDEN_OFFSET    12\n#define    RTL8367C_SVLAN_MEMBERCFG55_CTRL3_VS_EFIDEN_MASK    0x1000\n#define    RTL8367C_SVLAN_MEMBERCFG55_CTRL3_VS_SVID_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG55_CTRL3_VS_SVID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG56_CTRL1    0x0ca9\n#define    RTL8367C_SVLAN_MEMBERCFG56_CTRL1_VS_UNTAGSET_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG56_CTRL1_VS_UNTAGSET_MASK    0xFF00\n#define    RTL8367C_SVLAN_MEMBERCFG56_CTRL1_VS_SMBR_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG56_CTRL1_VS_SMBR_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG56_CTRL2    0x0caa\n#define    RTL8367C_SVLAN_MEMBERCFG56_CTRL2_VS_FIDEN_OFFSET    7\n#define    RTL8367C_SVLAN_MEMBERCFG56_CTRL2_VS_FIDEN_MASK    0x80\n#define    RTL8367C_SVLAN_MEMBERCFG56_CTRL2_VS_SPRI_OFFSET    4\n#define    RTL8367C_SVLAN_MEMBERCFG56_CTRL2_VS_SPRI_MASK    0x70\n#define    RTL8367C_SVLAN_MEMBERCFG56_CTRL2_VS_FID_MSTI_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG56_CTRL2_VS_FID_MSTI_MASK    0xF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG56_CTRL3    0x0cab\n#define    RTL8367C_SVLAN_MEMBERCFG56_CTRL3_VS_EFID_OFFSET    13\n#define    RTL8367C_SVLAN_MEMBERCFG56_CTRL3_VS_EFID_MASK    0xE000\n#define    RTL8367C_SVLAN_MEMBERCFG56_CTRL3_VS_EFIDEN_OFFSET    12\n#define    RTL8367C_SVLAN_MEMBERCFG56_CTRL3_VS_EFIDEN_MASK    0x1000\n#define    RTL8367C_SVLAN_MEMBERCFG56_CTRL3_VS_SVID_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG56_CTRL3_VS_SVID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG57_CTRL1    0x0cac\n#define    RTL8367C_SVLAN_MEMBERCFG57_CTRL1_VS_UNTAGSET_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG57_CTRL1_VS_UNTAGSET_MASK    0xFF00\n#define    RTL8367C_SVLAN_MEMBERCFG57_CTRL1_VS_SMBR_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG57_CTRL1_VS_SMBR_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG57_CTRL2    0x0cad\n#define    RTL8367C_SVLAN_MEMBERCFG57_CTRL2_VS_FIDEN_OFFSET    7\n#define    RTL8367C_SVLAN_MEMBERCFG57_CTRL2_VS_FIDEN_MASK    0x80\n#define    RTL8367C_SVLAN_MEMBERCFG57_CTRL2_VS_SPRI_OFFSET    4\n#define    RTL8367C_SVLAN_MEMBERCFG57_CTRL2_VS_SPRI_MASK    0x70\n#define    RTL8367C_SVLAN_MEMBERCFG57_CTRL2_VS_FID_MSTI_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG57_CTRL2_VS_FID_MSTI_MASK    0xF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG57_CTRL3    0x0cae\n#define    RTL8367C_SVLAN_MEMBERCFG57_CTRL3_VS_EFID_OFFSET    13\n#define    RTL8367C_SVLAN_MEMBERCFG57_CTRL3_VS_EFID_MASK    0xE000\n#define    RTL8367C_SVLAN_MEMBERCFG57_CTRL3_VS_EFIDEN_OFFSET    12\n#define    RTL8367C_SVLAN_MEMBERCFG57_CTRL3_VS_EFIDEN_MASK    0x1000\n#define    RTL8367C_SVLAN_MEMBERCFG57_CTRL3_VS_SVID_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG57_CTRL3_VS_SVID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG58_CTRL1    0x0caf\n#define    RTL8367C_SVLAN_MEMBERCFG58_CTRL1_VS_UNTAGSET_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG58_CTRL1_VS_UNTAGSET_MASK    0xFF00\n#define    RTL8367C_SVLAN_MEMBERCFG58_CTRL1_VS_SMBR_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG58_CTRL1_VS_SMBR_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG58_CTRL2    0x0cb0\n#define    RTL8367C_SVLAN_MEMBERCFG58_CTRL2_VS_FIDEN_OFFSET    7\n#define    RTL8367C_SVLAN_MEMBERCFG58_CTRL2_VS_FIDEN_MASK    0x80\n#define    RTL8367C_SVLAN_MEMBERCFG58_CTRL2_VS_SPRI_OFFSET    4\n#define    RTL8367C_SVLAN_MEMBERCFG58_CTRL2_VS_SPRI_MASK    0x70\n#define    RTL8367C_SVLAN_MEMBERCFG58_CTRL2_VS_FID_MSTI_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG58_CTRL2_VS_FID_MSTI_MASK    0xF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG58_CTRL3    0x0cb1\n#define    RTL8367C_SVLAN_MEMBERCFG58_CTRL3_VS_EFID_OFFSET    13\n#define    RTL8367C_SVLAN_MEMBERCFG58_CTRL3_VS_EFID_MASK    0xE000\n#define    RTL8367C_SVLAN_MEMBERCFG58_CTRL3_VS_EFIDEN_OFFSET    12\n#define    RTL8367C_SVLAN_MEMBERCFG58_CTRL3_VS_EFIDEN_MASK    0x1000\n#define    RTL8367C_SVLAN_MEMBERCFG58_CTRL3_VS_SVID_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG58_CTRL3_VS_SVID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG59_CTRL1    0x0cb2\n#define    RTL8367C_SVLAN_MEMBERCFG59_CTRL1_VS_UNTAGSET_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG59_CTRL1_VS_UNTAGSET_MASK    0xFF00\n#define    RTL8367C_SVLAN_MEMBERCFG59_CTRL1_VS_SMBR_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG59_CTRL1_VS_SMBR_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG59_CTRL2    0x0cb3\n#define    RTL8367C_SVLAN_MEMBERCFG59_CTRL2_VS_FIDEN_OFFSET    7\n#define    RTL8367C_SVLAN_MEMBERCFG59_CTRL2_VS_FIDEN_MASK    0x80\n#define    RTL8367C_SVLAN_MEMBERCFG59_CTRL2_VS_SPRI_OFFSET    4\n#define    RTL8367C_SVLAN_MEMBERCFG59_CTRL2_VS_SPRI_MASK    0x70\n#define    RTL8367C_SVLAN_MEMBERCFG59_CTRL2_VS_FID_MSTI_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG59_CTRL2_VS_FID_MSTI_MASK    0xF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG59_CTRL3    0x0cb4\n#define    RTL8367C_SVLAN_MEMBERCFG59_CTRL3_VS_EFID_OFFSET    13\n#define    RTL8367C_SVLAN_MEMBERCFG59_CTRL3_VS_EFID_MASK    0xE000\n#define    RTL8367C_SVLAN_MEMBERCFG59_CTRL3_VS_EFIDEN_OFFSET    12\n#define    RTL8367C_SVLAN_MEMBERCFG59_CTRL3_VS_EFIDEN_MASK    0x1000\n#define    RTL8367C_SVLAN_MEMBERCFG59_CTRL3_VS_SVID_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG59_CTRL3_VS_SVID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG60_CTRL1    0x0cb5\n#define    RTL8367C_SVLAN_MEMBERCFG60_CTRL1_VS_UNTAGSET_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG60_CTRL1_VS_UNTAGSET_MASK    0xFF00\n#define    RTL8367C_SVLAN_MEMBERCFG60_CTRL1_VS_SMBR_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG60_CTRL1_VS_SMBR_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG60_CTRL2    0x0cb6\n#define    RTL8367C_SVLAN_MEMBERCFG60_CTRL2_VS_FIDEN_OFFSET    7\n#define    RTL8367C_SVLAN_MEMBERCFG60_CTRL2_VS_FIDEN_MASK    0x80\n#define    RTL8367C_SVLAN_MEMBERCFG60_CTRL2_VS_SPRI_OFFSET    4\n#define    RTL8367C_SVLAN_MEMBERCFG60_CTRL2_VS_SPRI_MASK    0x70\n#define    RTL8367C_SVLAN_MEMBERCFG60_CTRL2_VS_FID_MSTI_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG60_CTRL2_VS_FID_MSTI_MASK    0xF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG60_CTRL3    0x0cb7\n#define    RTL8367C_SVLAN_MEMBERCFG60_CTRL3_VS_EFID_OFFSET    13\n#define    RTL8367C_SVLAN_MEMBERCFG60_CTRL3_VS_EFID_MASK    0xE000\n#define    RTL8367C_SVLAN_MEMBERCFG60_CTRL3_VS_EFIDEN_OFFSET    12\n#define    RTL8367C_SVLAN_MEMBERCFG60_CTRL3_VS_EFIDEN_MASK    0x1000\n#define    RTL8367C_SVLAN_MEMBERCFG60_CTRL3_VS_SVID_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG60_CTRL3_VS_SVID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG61_CTRL1    0x0cb8\n#define    RTL8367C_SVLAN_MEMBERCFG61_CTRL1_VS_UNTAGSET_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG61_CTRL1_VS_UNTAGSET_MASK    0xFF00\n#define    RTL8367C_SVLAN_MEMBERCFG61_CTRL1_VS_SMBR_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG61_CTRL1_VS_SMBR_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG61_CTRL2    0x0cb9\n#define    RTL8367C_SVLAN_MEMBERCFG61_CTRL2_VS_FIDEN_OFFSET    7\n#define    RTL8367C_SVLAN_MEMBERCFG61_CTRL2_VS_FIDEN_MASK    0x80\n#define    RTL8367C_SVLAN_MEMBERCFG61_CTRL2_VS_SPRI_OFFSET    4\n#define    RTL8367C_SVLAN_MEMBERCFG61_CTRL2_VS_SPRI_MASK    0x70\n#define    RTL8367C_SVLAN_MEMBERCFG61_CTRL2_VS_FID_MSTI_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG61_CTRL2_VS_FID_MSTI_MASK    0xF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG61_CTRL3    0x0cba\n#define    RTL8367C_SVLAN_MEMBERCFG61_CTRL3_VS_EFID_OFFSET    13\n#define    RTL8367C_SVLAN_MEMBERCFG61_CTRL3_VS_EFID_MASK    0xE000\n#define    RTL8367C_SVLAN_MEMBERCFG61_CTRL3_VS_EFIDEN_OFFSET    12\n#define    RTL8367C_SVLAN_MEMBERCFG61_CTRL3_VS_EFIDEN_MASK    0x1000\n#define    RTL8367C_SVLAN_MEMBERCFG61_CTRL3_VS_SVID_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG61_CTRL3_VS_SVID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG62_CTRL1    0x0cbb\n#define    RTL8367C_SVLAN_MEMBERCFG62_CTRL1_VS_UNTAGSET_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG62_CTRL1_VS_UNTAGSET_MASK    0xFF00\n#define    RTL8367C_SVLAN_MEMBERCFG62_CTRL1_VS_SMBR_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG62_CTRL1_VS_SMBR_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG62_CTRL2    0x0cbc\n#define    RTL8367C_SVLAN_MEMBERCFG62_CTRL2_VS_FIDEN_OFFSET    7\n#define    RTL8367C_SVLAN_MEMBERCFG62_CTRL2_VS_FIDEN_MASK    0x80\n#define    RTL8367C_SVLAN_MEMBERCFG62_CTRL2_VS_SPRI_OFFSET    4\n#define    RTL8367C_SVLAN_MEMBERCFG62_CTRL2_VS_SPRI_MASK    0x70\n#define    RTL8367C_SVLAN_MEMBERCFG62_CTRL2_VS_FID_MSTI_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG62_CTRL2_VS_FID_MSTI_MASK    0xF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG62_CTRL3    0x0cbd\n#define    RTL8367C_SVLAN_MEMBERCFG62_CTRL3_VS_EFID_OFFSET    13\n#define    RTL8367C_SVLAN_MEMBERCFG62_CTRL3_VS_EFID_MASK    0xE000\n#define    RTL8367C_SVLAN_MEMBERCFG62_CTRL3_VS_EFIDEN_OFFSET    12\n#define    RTL8367C_SVLAN_MEMBERCFG62_CTRL3_VS_EFIDEN_MASK    0x1000\n#define    RTL8367C_SVLAN_MEMBERCFG62_CTRL3_VS_SVID_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG62_CTRL3_VS_SVID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG63_CTRL1    0x0cbe\n#define    RTL8367C_SVLAN_MEMBERCFG63_CTRL1_VS_UNTAGSET_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG63_CTRL1_VS_UNTAGSET_MASK    0xFF00\n#define    RTL8367C_SVLAN_MEMBERCFG63_CTRL1_VS_SMBR_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG63_CTRL1_VS_SMBR_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG63_CTRL2    0x0cbf\n#define    RTL8367C_SVLAN_MEMBERCFG63_CTRL2_VS_FIDEN_OFFSET    7\n#define    RTL8367C_SVLAN_MEMBERCFG63_CTRL2_VS_FIDEN_MASK    0x80\n#define    RTL8367C_SVLAN_MEMBERCFG63_CTRL2_VS_SPRI_OFFSET    4\n#define    RTL8367C_SVLAN_MEMBERCFG63_CTRL2_VS_SPRI_MASK    0x70\n#define    RTL8367C_SVLAN_MEMBERCFG63_CTRL2_VS_FID_MSTI_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG63_CTRL2_VS_FID_MSTI_MASK    0xF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG63_CTRL3    0x0cc0\n#define    RTL8367C_SVLAN_MEMBERCFG63_CTRL3_VS_EFID_OFFSET    13\n#define    RTL8367C_SVLAN_MEMBERCFG63_CTRL3_VS_EFID_MASK    0xE000\n#define    RTL8367C_SVLAN_MEMBERCFG63_CTRL3_VS_EFIDEN_OFFSET    12\n#define    RTL8367C_SVLAN_MEMBERCFG63_CTRL3_VS_EFIDEN_MASK    0x1000\n#define    RTL8367C_SVLAN_MEMBERCFG63_CTRL3_VS_SVID_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG63_CTRL3_VS_SVID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG0_CTRL4    0x0cc1\n#define    RTL8367C_SVLAN_MEMBERCFG0_CTRL4_VS_UNTAGSET_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG0_CTRL4_VS_UNTAGSET_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_MEMBERCFG0_CTRL4_VS_SMBR_EXT_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG0_CTRL4_VS_SMBR_EXT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG1_CTRL4    0x0cc2\n#define    RTL8367C_SVLAN_MEMBERCFG1_CTRL4_VS_UNTAGSET_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG1_CTRL4_VS_UNTAGSET_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_MEMBERCFG1_CTRL4_VS_SMBR_EXT_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG1_CTRL4_VS_SMBR_EXT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG2_CTRL4    0x0cc3\n#define    RTL8367C_SVLAN_MEMBERCFG2_CTRL4_VS_UNTAGSET_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG2_CTRL4_VS_UNTAGSET_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_MEMBERCFG2_CTRL4_VS_SMBR_EXT_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG2_CTRL4_VS_SMBR_EXT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG3_CTRL4    0x0cc4\n#define    RTL8367C_SVLAN_MEMBERCFG3_CTRL4_VS_UNTAGSET_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG3_CTRL4_VS_UNTAGSET_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_MEMBERCFG3_CTRL4_VS_SMBR_EXT_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG3_CTRL4_VS_SMBR_EXT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG4_CTRL4    0x0cc5\n#define    RTL8367C_SVLAN_MEMBERCFG4_CTRL4_VS_UNTAGSET_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG4_CTRL4_VS_UNTAGSET_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_MEMBERCFG4_CTRL4_VS_SMBR_EXT_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG4_CTRL4_VS_SMBR_EXT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG5_CTRL4    0x0cc6\n#define    RTL8367C_SVLAN_MEMBERCFG5_CTRL4_VS_UNTAGSET_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG5_CTRL4_VS_UNTAGSET_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_MEMBERCFG5_CTRL4_VS_SMBR_EXT_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG5_CTRL4_VS_SMBR_EXT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG6_CTRL4    0x0cc7\n#define    RTL8367C_SVLAN_MEMBERCFG6_CTRL4_VS_UNTAGSET_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG6_CTRL4_VS_UNTAGSET_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_MEMBERCFG6_CTRL4_VS_SMBR_EXT_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG6_CTRL4_VS_SMBR_EXT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG7_CTRL4    0x0cc8\n#define    RTL8367C_SVLAN_MEMBERCFG7_CTRL4_VS_UNTAGSET_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG7_CTRL4_VS_UNTAGSET_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_MEMBERCFG7_CTRL4_VS_SMBR_EXT_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG7_CTRL4_VS_SMBR_EXT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG8_CTRL4    0x0cc9\n#define    RTL8367C_SVLAN_MEMBERCFG8_CTRL4_VS_UNTAGSET_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG8_CTRL4_VS_UNTAGSET_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_MEMBERCFG8_CTRL4_VS_SMBR_EXT_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG8_CTRL4_VS_SMBR_EXT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG9_CTRL4    0x0cca\n#define    RTL8367C_SVLAN_MEMBERCFG9_CTRL4_VS_UNTAGSET_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG9_CTRL4_VS_UNTAGSET_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_MEMBERCFG9_CTRL4_VS_SMBR_EXT_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG9_CTRL4_VS_SMBR_EXT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG10_CTRL4    0x0ccb\n#define    RTL8367C_SVLAN_MEMBERCFG10_CTRL4_VS_UNTAGSET_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG10_CTRL4_VS_UNTAGSET_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_MEMBERCFG10_CTRL4_VS_SMBR_EXT_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG10_CTRL4_VS_SMBR_EXT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG11_CTRL4    0x0ccc\n#define    RTL8367C_SVLAN_MEMBERCFG11_CTRL4_VS_UNTAGSET_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG11_CTRL4_VS_UNTAGSET_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_MEMBERCFG11_CTRL4_VS_SMBR_EXT_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG11_CTRL4_VS_SMBR_EXT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG12_CTRL4    0x0ccd\n#define    RTL8367C_SVLAN_MEMBERCFG12_CTRL4_VS_UNTAGSET_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG12_CTRL4_VS_UNTAGSET_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_MEMBERCFG12_CTRL4_VS_SMBR_EXT_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG12_CTRL4_VS_SMBR_EXT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG13_CTRL4    0x0cce\n#define    RTL8367C_SVLAN_MEMBERCFG13_CTRL4_VS_UNTAGSET_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG13_CTRL4_VS_UNTAGSET_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_MEMBERCFG13_CTRL4_VS_SMBR_EXT_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG13_CTRL4_VS_SMBR_EXT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG14_CTRL4    0x0ccf\n#define    RTL8367C_SVLAN_MEMBERCFG14_CTRL4_VS_UNTAGSET_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG14_CTRL4_VS_UNTAGSET_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_MEMBERCFG14_CTRL4_VS_SMBR_EXT_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG14_CTRL4_VS_SMBR_EXT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG15_CTRL4    0x0cd0\n#define    RTL8367C_SVLAN_MEMBERCFG15_CTRL4_VS_UNTAGSET_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG15_CTRL4_VS_UNTAGSET_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_MEMBERCFG15_CTRL4_VS_SMBR_EXT_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG15_CTRL4_VS_SMBR_EXT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG16_CTRL4    0x0cd1\n#define    RTL8367C_SVLAN_MEMBERCFG16_CTRL4_VS_UNTAGSET_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG16_CTRL4_VS_UNTAGSET_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_MEMBERCFG16_CTRL4_VS_SMBR_EXT_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG16_CTRL4_VS_SMBR_EXT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG17_CTRL4    0x0cd2\n#define    RTL8367C_SVLAN_MEMBERCFG17_CTRL4_VS_UNTAGSET_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG17_CTRL4_VS_UNTAGSET_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_MEMBERCFG17_CTRL4_VS_SMBR_EXT_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG17_CTRL4_VS_SMBR_EXT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG18_CTRL4    0x0cd3\n#define    RTL8367C_SVLAN_MEMBERCFG18_CTRL4_VS_UNTAGSET_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG18_CTRL4_VS_UNTAGSET_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_MEMBERCFG18_CTRL4_VS_SMBR_EXT_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG18_CTRL4_VS_SMBR_EXT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG19_CTRL4    0x0cd4\n#define    RTL8367C_SVLAN_MEMBERCFG19_CTRL4_VS_UNTAGSET_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG19_CTRL4_VS_UNTAGSET_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_MEMBERCFG19_CTRL4_VS_SMBR_EXT_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG19_CTRL4_VS_SMBR_EXT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG20_CTRL4    0x0cd5\n#define    RTL8367C_SVLAN_MEMBERCFG20_CTRL4_VS_UNTAGSET_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG20_CTRL4_VS_UNTAGSET_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_MEMBERCFG20_CTRL4_VS_SMBR_EXT_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG20_CTRL4_VS_SMBR_EXT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG21_CTRL4    0x0cd6\n#define    RTL8367C_SVLAN_MEMBERCFG21_CTRL4_VS_UNTAGSET_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG21_CTRL4_VS_UNTAGSET_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_MEMBERCFG21_CTRL4_VS_SMBR_EXT_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG21_CTRL4_VS_SMBR_EXT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG22_CTRL4    0x0cd7\n#define    RTL8367C_SVLAN_MEMBERCFG22_CTRL4_VS_UNTAGSET_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG22_CTRL4_VS_UNTAGSET_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_MEMBERCFG22_CTRL4_VS_SMBR_EXT_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG22_CTRL4_VS_SMBR_EXT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG23_CTRL4    0x0cd8\n#define    RTL8367C_SVLAN_MEMBERCFG23_CTRL4_VS_UNTAGSET_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG23_CTRL4_VS_UNTAGSET_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_MEMBERCFG23_CTRL4_VS_SMBR_EXT_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG23_CTRL4_VS_SMBR_EXT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG24_CTRL4    0x0cd9\n#define    RTL8367C_SVLAN_MEMBERCFG24_CTRL4_VS_UNTAGSET_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG24_CTRL4_VS_UNTAGSET_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_MEMBERCFG24_CTRL4_VS_SMBR_EXT_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG24_CTRL4_VS_SMBR_EXT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG25_CTRL4    0x0cda\n#define    RTL8367C_SVLAN_MEMBERCFG25_CTRL4_VS_UNTAGSET_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG25_CTRL4_VS_UNTAGSET_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_MEMBERCFG25_CTRL4_VS_SMBR_EXT_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG25_CTRL4_VS_SMBR_EXT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG26_CTRL4    0x0cdb\n#define    RTL8367C_SVLAN_MEMBERCFG26_CTRL4_VS_UNTAGSET_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG26_CTRL4_VS_UNTAGSET_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_MEMBERCFG26_CTRL4_VS_SMBR_EXT_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG26_CTRL4_VS_SMBR_EXT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG27_CTRL4    0x0cdc\n#define    RTL8367C_SVLAN_MEMBERCFG27_CTRL4_VS_UNTAGSET_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG27_CTRL4_VS_UNTAGSET_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_MEMBERCFG27_CTRL4_VS_SMBR_EXT_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG27_CTRL4_VS_SMBR_EXT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG28_CTRL4    0x0cdd\n#define    RTL8367C_SVLAN_MEMBERCFG28_CTRL4_VS_UNTAGSET_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG28_CTRL4_VS_UNTAGSET_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_MEMBERCFG28_CTRL4_VS_SMBR_EXT_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG28_CTRL4_VS_SMBR_EXT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG29_CTRL4    0x0cde\n#define    RTL8367C_SVLAN_MEMBERCFG29_CTRL4_VS_UNTAGSET_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG29_CTRL4_VS_UNTAGSET_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_MEMBERCFG29_CTRL4_VS_SMBR_EXT_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG29_CTRL4_VS_SMBR_EXT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG30_CTRL4    0x0cdf\n#define    RTL8367C_SVLAN_MEMBERCFG30_CTRL4_VS_UNTAGSET_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG30_CTRL4_VS_UNTAGSET_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_MEMBERCFG30_CTRL4_VS_SMBR_EXT_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG30_CTRL4_VS_SMBR_EXT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG31_CTRL4    0x0ce0\n#define    RTL8367C_SVLAN_MEMBERCFG31_CTRL4_VS_UNTAGSET_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG31_CTRL4_VS_UNTAGSET_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_MEMBERCFG31_CTRL4_VS_SMBR_EXT_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG31_CTRL4_VS_SMBR_EXT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG32_CTRL4    0x0ce1\n#define    RTL8367C_SVLAN_MEMBERCFG32_CTRL4_VS_UNTAGSET_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG32_CTRL4_VS_UNTAGSET_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_MEMBERCFG32_CTRL4_VS_SMBR_EXT_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG32_CTRL4_VS_SMBR_EXT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG33_CTRL4    0x0ce2\n#define    RTL8367C_SVLAN_MEMBERCFG33_CTRL4_VS_UNTAGSET_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG33_CTRL4_VS_UNTAGSET_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_MEMBERCFG33_CTRL4_VS_SMBR_EXT_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG33_CTRL4_VS_SMBR_EXT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG34_CTRL4    0x0ce3\n#define    RTL8367C_SVLAN_MEMBERCFG34_CTRL4_VS_UNTAGSET_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG34_CTRL4_VS_UNTAGSET_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_MEMBERCFG34_CTRL4_VS_SMBR_EXT_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG34_CTRL4_VS_SMBR_EXT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG35_CTRL4    0x0ce4\n#define    RTL8367C_SVLAN_MEMBERCFG35_CTRL4_VS_UNTAGSET_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG35_CTRL4_VS_UNTAGSET_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_MEMBERCFG35_CTRL4_VS_SMBR_EXT_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG35_CTRL4_VS_SMBR_EXT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG36_CTRL4    0x0ce5\n#define    RTL8367C_SVLAN_MEMBERCFG36_CTRL4_VS_UNTAGSET_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG36_CTRL4_VS_UNTAGSET_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_MEMBERCFG36_CTRL4_VS_SMBR_EXT_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG36_CTRL4_VS_SMBR_EXT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG37_CTRL4    0x0ce6\n#define    RTL8367C_SVLAN_MEMBERCFG37_CTRL4_VS_UNTAGSET_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG37_CTRL4_VS_UNTAGSET_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_MEMBERCFG37_CTRL4_VS_SMBR_EXT_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG37_CTRL4_VS_SMBR_EXT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG38_CTRL4    0x0ce7\n#define    RTL8367C_SVLAN_MEMBERCFG38_CTRL4_VS_UNTAGSET_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG38_CTRL4_VS_UNTAGSET_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_MEMBERCFG38_CTRL4_VS_SMBR_EXT_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG38_CTRL4_VS_SMBR_EXT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG39_CTRL4    0x0ce8\n#define    RTL8367C_SVLAN_MEMBERCFG39_CTRL4_VS_UNTAGSET_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG39_CTRL4_VS_UNTAGSET_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_MEMBERCFG39_CTRL4_VS_SMBR_EXT_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG39_CTRL4_VS_SMBR_EXT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG40_CTRL4    0x0ce9\n#define    RTL8367C_SVLAN_MEMBERCFG40_CTRL4_VS_UNTAGSET_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG40_CTRL4_VS_UNTAGSET_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_MEMBERCFG40_CTRL4_VS_SMBR_EXT_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG40_CTRL4_VS_SMBR_EXT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG41_CTRL4    0x0cea\n#define    RTL8367C_SVLAN_MEMBERCFG41_CTRL4_VS_UNTAGSET_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG41_CTRL4_VS_UNTAGSET_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_MEMBERCFG41_CTRL4_VS_SMBR_EXT_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG41_CTRL4_VS_SMBR_EXT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG42_CTRL4    0x0ceb\n#define    RTL8367C_SVLAN_MEMBERCFG42_CTRL4_VS_UNTAGSET_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG42_CTRL4_VS_UNTAGSET_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_MEMBERCFG42_CTRL4_VS_SMBR_EXT_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG42_CTRL4_VS_SMBR_EXT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG43_CTRL4    0x0cec\n#define    RTL8367C_SVLAN_MEMBERCFG43_CTRL4_VS_UNTAGSET_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG43_CTRL4_VS_UNTAGSET_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_MEMBERCFG43_CTRL4_VS_SMBR_EXT_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG43_CTRL4_VS_SMBR_EXT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG44_CTRL4    0x0ced\n#define    RTL8367C_SVLAN_MEMBERCFG44_CTRL4_VS_UNTAGSET_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG44_CTRL4_VS_UNTAGSET_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_MEMBERCFG44_CTRL4_VS_SMBR_EXT_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG44_CTRL4_VS_SMBR_EXT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG45_CTRL4    0x0cee\n#define    RTL8367C_SVLAN_MEMBERCFG45_CTRL4_VS_UNTAGSET_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG45_CTRL4_VS_UNTAGSET_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_MEMBERCFG45_CTRL4_VS_SMBR_EXT_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG45_CTRL4_VS_SMBR_EXT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG46_CTRL4    0x0cef\n#define    RTL8367C_SVLAN_MEMBERCFG46_CTRL4_VS_UNTAGSET_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG46_CTRL4_VS_UNTAGSET_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_MEMBERCFG46_CTRL4_VS_SMBR_EXT_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG46_CTRL4_VS_SMBR_EXT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG47_CTRL4    0x0cf0\n#define    RTL8367C_SVLAN_MEMBERCFG47_CTRL4_VS_UNTAGSET_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG47_CTRL4_VS_UNTAGSET_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_MEMBERCFG47_CTRL4_VS_SMBR_EXT_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG47_CTRL4_VS_SMBR_EXT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG48_CTRL4    0x0cf1\n#define    RTL8367C_SVLAN_MEMBERCFG48_CTRL4_VS_UNTAGSET_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG48_CTRL4_VS_UNTAGSET_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_MEMBERCFG48_CTRL4_VS_SMBR_EXT_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG48_CTRL4_VS_SMBR_EXT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG49_CTRL4    0x0cf2\n#define    RTL8367C_SVLAN_MEMBERCFG49_CTRL4_VS_UNTAGSET_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG49_CTRL4_VS_UNTAGSET_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_MEMBERCFG49_CTRL4_VS_SMBR_EXT_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG49_CTRL4_VS_SMBR_EXT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG50_CTRL4    0x0cf3\n#define    RTL8367C_SVLAN_MEMBERCFG50_CTRL4_VS_UNTAGSET_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG50_CTRL4_VS_UNTAGSET_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_MEMBERCFG50_CTRL4_VS_SMBR_EXT_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG50_CTRL4_VS_SMBR_EXT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG51_CTRL4    0x0cf4\n#define    RTL8367C_SVLAN_MEMBERCFG51_CTRL4_VS_UNTAGSET_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG51_CTRL4_VS_UNTAGSET_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_MEMBERCFG51_CTRL4_VS_SMBR_EXT_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG51_CTRL4_VS_SMBR_EXT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG52_CTRL4    0x0cf5\n#define    RTL8367C_SVLAN_MEMBERCFG52_CTRL4_VS_UNTAGSET_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG52_CTRL4_VS_UNTAGSET_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_MEMBERCFG52_CTRL4_VS_SMBR_EXT_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG52_CTRL4_VS_SMBR_EXT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG53_CTRL4    0x0cf6\n#define    RTL8367C_SVLAN_MEMBERCFG53_CTRL4_VS_UNTAGSET_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG53_CTRL4_VS_UNTAGSET_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_MEMBERCFG53_CTRL4_VS_SMBR_EXT_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG53_CTRL4_VS_SMBR_EXT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG54_CTRL4    0x0cf7\n#define    RTL8367C_SVLAN_MEMBERCFG54_CTRL4_VS_UNTAGSET_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG54_CTRL4_VS_UNTAGSET_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_MEMBERCFG54_CTRL4_VS_SMBR_EXT_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG54_CTRL4_VS_SMBR_EXT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG55_CTRL4    0x0cf8\n#define    RTL8367C_SVLAN_MEMBERCFG55_CTRL4_VS_UNTAGSET_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG55_CTRL4_VS_UNTAGSET_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_MEMBERCFG55_CTRL4_VS_SMBR_EXT_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG55_CTRL4_VS_SMBR_EXT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG56_CTRL4    0x0cf9\n#define    RTL8367C_SVLAN_MEMBERCFG56_CTRL4_VS_UNTAGSET_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG56_CTRL4_VS_UNTAGSET_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_MEMBERCFG56_CTRL4_VS_SMBR_EXT_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG56_CTRL4_VS_SMBR_EXT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG57_CTRL4    0x0cfa\n#define    RTL8367C_SVLAN_MEMBERCFG57_CTRL4_VS_UNTAGSET_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG57_CTRL4_VS_UNTAGSET_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_MEMBERCFG57_CTRL4_VS_SMBR_EXT_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG57_CTRL4_VS_SMBR_EXT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG58_CTRL4    0x0cfb\n#define    RTL8367C_SVLAN_MEMBERCFG58_CTRL4_VS_UNTAGSET_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG58_CTRL4_VS_UNTAGSET_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_MEMBERCFG58_CTRL4_VS_SMBR_EXT_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG58_CTRL4_VS_SMBR_EXT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG59_CTRL4    0x0cfc\n#define    RTL8367C_SVLAN_MEMBERCFG59_CTRL4_VS_UNTAGSET_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG59_CTRL4_VS_UNTAGSET_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_MEMBERCFG59_CTRL4_VS_SMBR_EXT_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG59_CTRL4_VS_SMBR_EXT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG60_CTRL4    0x0cfd\n#define    RTL8367C_SVLAN_MEMBERCFG60_CTRL4_VS_UNTAGSET_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG60_CTRL4_VS_UNTAGSET_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_MEMBERCFG60_CTRL4_VS_SMBR_EXT_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG60_CTRL4_VS_SMBR_EXT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG61_CTRL4    0x0cfe\n#define    RTL8367C_SVLAN_MEMBERCFG61_CTRL4_VS_UNTAGSET_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG61_CTRL4_VS_UNTAGSET_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_MEMBERCFG61_CTRL4_VS_SMBR_EXT_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG61_CTRL4_VS_SMBR_EXT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG62_CTRL4    0x0cff\n#define    RTL8367C_SVLAN_MEMBERCFG62_CTRL4_VS_UNTAGSET_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG62_CTRL4_VS_UNTAGSET_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_MEMBERCFG62_CTRL4_VS_SMBR_EXT_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG62_CTRL4_VS_SMBR_EXT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_C2SCFG0_CTRL0    0x0d00\n#define    RTL8367C_SVLAN_C2SCFG0_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG0_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG0_CTRL1    0x0d01\n#define    RTL8367C_SVLAN_C2SCFG0_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG0_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG0_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG0_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG0_CTRL2    0x0d02\n#define    RTL8367C_SVLAN_C2SCFG0_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG0_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG1_CTRL0    0x0d03\n#define    RTL8367C_SVLAN_C2SCFG1_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG1_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG1_CTRL1    0x0d04\n#define    RTL8367C_SVLAN_C2SCFG1_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG1_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG1_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG1_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG1_CTRL2    0x0d05\n#define    RTL8367C_SVLAN_C2SCFG1_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG1_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG2_CTRL0    0x0d06\n#define    RTL8367C_SVLAN_C2SCFG2_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG2_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG2_CTRL1    0x0d07\n#define    RTL8367C_SVLAN_C2SCFG2_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG2_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG2_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG2_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG2_CTRL2    0x0d08\n#define    RTL8367C_SVLAN_C2SCFG2_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG2_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG3_CTRL0    0x0d09\n#define    RTL8367C_SVLAN_C2SCFG3_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG3_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG3_CTRL1    0x0d0a\n#define    RTL8367C_SVLAN_C2SCFG3_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG3_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG3_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG3_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG3_CTRL2    0x0d0b\n#define    RTL8367C_SVLAN_C2SCFG3_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG3_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG4_CTRL0    0x0d0c\n#define    RTL8367C_SVLAN_C2SCFG4_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG4_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG4_CTRL1    0x0d0d\n#define    RTL8367C_SVLAN_C2SCFG4_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG4_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG4_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG4_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG4_CTRL2    0x0d0e\n#define    RTL8367C_SVLAN_C2SCFG4_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG4_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG5_CTRL0    0x0d0f\n#define    RTL8367C_SVLAN_C2SCFG5_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG5_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG5_CTRL1    0x0d10\n#define    RTL8367C_SVLAN_C2SCFG5_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG5_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG5_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG5_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG5_CTRL2    0x0d11\n#define    RTL8367C_SVLAN_C2SCFG5_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG5_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG6_CTRL0    0x0d12\n#define    RTL8367C_SVLAN_C2SCFG6_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG6_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG6_CTRL1    0x0d13\n#define    RTL8367C_SVLAN_C2SCFG6_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG6_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG6_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG6_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG6_CTRL2    0x0d14\n#define    RTL8367C_SVLAN_C2SCFG6_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG6_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG7_CTRL0    0x0d15\n#define    RTL8367C_SVLAN_C2SCFG7_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG7_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG7_CTRL1    0x0d16\n#define    RTL8367C_SVLAN_C2SCFG7_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG7_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG7_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG7_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG7_CTRL2    0x0d17\n#define    RTL8367C_SVLAN_C2SCFG7_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG7_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG8_CTRL0    0x0d18\n#define    RTL8367C_SVLAN_C2SCFG8_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG8_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG8_CTRL1    0x0d19\n#define    RTL8367C_SVLAN_C2SCFG8_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG8_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG8_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG8_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG8_CTRL2    0x0d1a\n#define    RTL8367C_SVLAN_C2SCFG8_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG8_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG9_CTRL0    0x0d1b\n#define    RTL8367C_SVLAN_C2SCFG9_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG9_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG9_CTRL1    0x0d1c\n#define    RTL8367C_SVLAN_C2SCFG9_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG9_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG9_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG9_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG9_CTRL2    0x0d1d\n#define    RTL8367C_SVLAN_C2SCFG9_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG9_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG10_CTRL0    0x0d1e\n#define    RTL8367C_SVLAN_C2SCFG10_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG10_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG10_CTRL1    0x0d1f\n#define    RTL8367C_SVLAN_C2SCFG10_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG10_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG10_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG10_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG10_CTRL2    0x0d20\n#define    RTL8367C_SVLAN_C2SCFG10_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG10_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG11_CTRL0    0x0d21\n#define    RTL8367C_SVLAN_C2SCFG11_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG11_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG11_CTRL1    0x0d22\n#define    RTL8367C_SVLAN_C2SCFG11_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG11_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG11_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG11_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG11_CTRL2    0x0d23\n#define    RTL8367C_SVLAN_C2SCFG11_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG11_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG12_CTRL0    0x0d24\n#define    RTL8367C_SVLAN_C2SCFG12_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG12_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG12_CTRL1    0x0d25\n#define    RTL8367C_SVLAN_C2SCFG12_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG12_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG12_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG12_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG12_CTRL2    0x0d26\n#define    RTL8367C_SVLAN_C2SCFG12_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG12_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG13_CTRL0    0x0d27\n#define    RTL8367C_SVLAN_C2SCFG13_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG13_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG13_CTRL1    0x0d28\n#define    RTL8367C_SVLAN_C2SCFG13_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG13_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG13_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG13_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG13_CTRL2    0x0d29\n#define    RTL8367C_SVLAN_C2SCFG13_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG13_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG14_CTRL0    0x0d2a\n#define    RTL8367C_SVLAN_C2SCFG14_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG14_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG14_CTRL1    0x0d2b\n#define    RTL8367C_SVLAN_C2SCFG14_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG14_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG14_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG14_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG14_CTRL2    0x0d2c\n#define    RTL8367C_SVLAN_C2SCFG14_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG14_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG15_CTRL0    0x0d2d\n#define    RTL8367C_SVLAN_C2SCFG15_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG15_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG15_CTRL1    0x0d2e\n#define    RTL8367C_SVLAN_C2SCFG15_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG15_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG15_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG15_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG15_CTRL2    0x0d2f\n#define    RTL8367C_SVLAN_C2SCFG15_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG15_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG16_CTRL0    0x0d30\n#define    RTL8367C_SVLAN_C2SCFG16_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG16_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG16_CTRL1    0x0d31\n#define    RTL8367C_SVLAN_C2SCFG16_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG16_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG16_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG16_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG16_CTRL2    0x0d32\n#define    RTL8367C_SVLAN_C2SCFG16_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG16_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG17_CTRL0    0x0d33\n#define    RTL8367C_SVLAN_C2SCFG17_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG17_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG17_CTRL1    0x0d34\n#define    RTL8367C_SVLAN_C2SCFG17_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG17_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG17_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG17_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG17_CTRL2    0x0d35\n#define    RTL8367C_SVLAN_C2SCFG17_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG17_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG18_CTRL0    0x0d36\n#define    RTL8367C_SVLAN_C2SCFG18_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG18_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG18_CTRL1    0x0d37\n#define    RTL8367C_SVLAN_C2SCFG18_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG18_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG18_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG18_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG18_CTRL2    0x0d38\n#define    RTL8367C_SVLAN_C2SCFG18_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG18_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG19_CTRL0    0x0d39\n#define    RTL8367C_SVLAN_C2SCFG19_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG19_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG19_CTRL1    0x0d3a\n#define    RTL8367C_SVLAN_C2SCFG19_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG19_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG19_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG19_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG19_CTRL2    0x0d3b\n#define    RTL8367C_SVLAN_C2SCFG19_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG19_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG20_CTRL0    0x0d3c\n#define    RTL8367C_SVLAN_C2SCFG20_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG20_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG20_CTRL1    0x0d3d\n#define    RTL8367C_SVLAN_C2SCFG20_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG20_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG20_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG20_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG20_CTRL2    0x0d3e\n#define    RTL8367C_SVLAN_C2SCFG20_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG20_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG21_CTRL0    0x0d3f\n#define    RTL8367C_SVLAN_C2SCFG21_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG21_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG21_CTRL1    0x0d40\n#define    RTL8367C_SVLAN_C2SCFG21_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG21_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG21_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG21_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG21_CTRL2    0x0d41\n#define    RTL8367C_SVLAN_C2SCFG21_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG21_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG22_CTRL0    0x0d42\n#define    RTL8367C_SVLAN_C2SCFG22_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG22_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG22_CTRL1    0x0d43\n#define    RTL8367C_SVLAN_C2SCFG22_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG22_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG22_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG22_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG22_CTRL2    0x0d44\n#define    RTL8367C_SVLAN_C2SCFG22_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG22_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG23_CTRL0    0x0d45\n#define    RTL8367C_SVLAN_C2SCFG23_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG23_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG23_CTRL1    0x0d46\n#define    RTL8367C_SVLAN_C2SCFG23_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG23_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG23_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG23_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG23_CTRL2    0x0d47\n#define    RTL8367C_SVLAN_C2SCFG23_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG23_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG24_CTRL0    0x0d48\n#define    RTL8367C_SVLAN_C2SCFG24_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG24_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG24_CTRL1    0x0d49\n#define    RTL8367C_SVLAN_C2SCFG24_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG24_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG24_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG24_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG24_CTRL2    0x0d4a\n#define    RTL8367C_SVLAN_C2SCFG24_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG24_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG25_CTRL0    0x0d4b\n#define    RTL8367C_SVLAN_C2SCFG25_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG25_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG25_CTRL1    0x0d4c\n#define    RTL8367C_SVLAN_C2SCFG25_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG25_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG25_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG25_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG25_CTRL2    0x0d4d\n#define    RTL8367C_SVLAN_C2SCFG25_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG25_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG26_CTRL0    0x0d4e\n#define    RTL8367C_SVLAN_C2SCFG26_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG26_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG26_CTRL1    0x0d4f\n#define    RTL8367C_SVLAN_C2SCFG26_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG26_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG26_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG26_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG26_CTRL2    0x0d50\n#define    RTL8367C_SVLAN_C2SCFG26_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG26_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG27_CTRL0    0x0d51\n#define    RTL8367C_SVLAN_C2SCFG27_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG27_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG27_CTRL1    0x0d52\n#define    RTL8367C_SVLAN_C2SCFG27_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG27_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG27_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG27_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG27_CTRL2    0x0d53\n#define    RTL8367C_SVLAN_C2SCFG27_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG27_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG28_CTRL0    0x0d54\n#define    RTL8367C_SVLAN_C2SCFG28_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG28_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG28_CTRL1    0x0d55\n#define    RTL8367C_SVLAN_C2SCFG28_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG28_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG28_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG28_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG28_CTRL2    0x0d56\n#define    RTL8367C_SVLAN_C2SCFG28_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG28_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG29_CTRL0    0x0d57\n#define    RTL8367C_SVLAN_C2SCFG29_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG29_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG29_CTRL1    0x0d58\n#define    RTL8367C_SVLAN_C2SCFG29_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG29_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG29_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG29_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG29_CTRL2    0x0d59\n#define    RTL8367C_SVLAN_C2SCFG29_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG29_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG30_CTRL0    0x0d5a\n#define    RTL8367C_SVLAN_C2SCFG30_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG30_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG30_CTRL1    0x0d5b\n#define    RTL8367C_SVLAN_C2SCFG30_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG30_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG30_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG30_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG30_CTRL2    0x0d5c\n#define    RTL8367C_SVLAN_C2SCFG30_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG30_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG31_CTRL0    0x0d5d\n#define    RTL8367C_SVLAN_C2SCFG31_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG31_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG31_CTRL1    0x0d5e\n#define    RTL8367C_SVLAN_C2SCFG31_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG31_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG31_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG31_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG31_CTRL2    0x0d5f\n#define    RTL8367C_SVLAN_C2SCFG31_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG31_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG32_CTRL0    0x0d60\n#define    RTL8367C_SVLAN_C2SCFG32_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG32_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG32_CTRL1    0x0d61\n#define    RTL8367C_SVLAN_C2SCFG32_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG32_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG32_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG32_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG32_CTRL2    0x0d62\n#define    RTL8367C_SVLAN_C2SCFG32_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG32_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG33_CTRL0    0x0d63\n#define    RTL8367C_SVLAN_C2SCFG33_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG33_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG33_CTRL1    0x0d64\n#define    RTL8367C_SVLAN_C2SCFG33_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG33_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG33_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG33_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG33_CTRL2    0x0d65\n#define    RTL8367C_SVLAN_C2SCFG33_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG33_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG34_CTRL0    0x0d66\n#define    RTL8367C_SVLAN_C2SCFG34_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG34_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG34_CTRL1    0x0d67\n#define    RTL8367C_SVLAN_C2SCFG34_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG34_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG34_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG34_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG34_CTRL2    0x0d68\n#define    RTL8367C_SVLAN_C2SCFG34_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG34_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG35_CTRL0    0x0d69\n#define    RTL8367C_SVLAN_C2SCFG35_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG35_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG35_CTRL1    0x0d6a\n#define    RTL8367C_SVLAN_C2SCFG35_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG35_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG35_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG35_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG35_CTRL2    0x0d6b\n#define    RTL8367C_SVLAN_C2SCFG35_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG35_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG36_CTRL0    0x0d6c\n#define    RTL8367C_SVLAN_C2SCFG36_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG36_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG36_CTRL1    0x0d6d\n#define    RTL8367C_SVLAN_C2SCFG36_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG36_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG36_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG36_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG36_CTRL2    0x0d6e\n#define    RTL8367C_SVLAN_C2SCFG36_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG36_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG37_CTRL0    0x0d6f\n#define    RTL8367C_SVLAN_C2SCFG37_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG37_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG37_CTRL1    0x0d70\n#define    RTL8367C_SVLAN_C2SCFG37_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG37_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG37_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG37_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG37_CTRL2    0x0d71\n#define    RTL8367C_SVLAN_C2SCFG37_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG37_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG38_CTRL0    0x0d72\n#define    RTL8367C_SVLAN_C2SCFG38_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG38_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG38_CTRL1    0x0d73\n#define    RTL8367C_SVLAN_C2SCFG38_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG38_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG38_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG38_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG38_CTRL2    0x0d74\n#define    RTL8367C_SVLAN_C2SCFG38_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG38_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG39_CTRL0    0x0d75\n#define    RTL8367C_SVLAN_C2SCFG39_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG39_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG39_CTRL1    0x0d76\n#define    RTL8367C_SVLAN_C2SCFG39_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG39_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG39_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG39_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG39_CTRL2    0x0d77\n#define    RTL8367C_SVLAN_C2SCFG39_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG39_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG40_CTRL0    0x0d78\n#define    RTL8367C_SVLAN_C2SCFG40_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG40_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG40_CTRL1    0x0d79\n#define    RTL8367C_SVLAN_C2SCFG40_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG40_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG40_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG40_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG40_CTRL2    0x0d7a\n#define    RTL8367C_SVLAN_C2SCFG40_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG40_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG41_CTRL0    0x0d7b\n#define    RTL8367C_SVLAN_C2SCFG41_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG41_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG41_CTRL1    0x0d7c\n#define    RTL8367C_SVLAN_C2SCFG41_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG41_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG41_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG41_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG41_CTRL2    0x0d7d\n#define    RTL8367C_SVLAN_C2SCFG41_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG41_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG42_CTRL0    0x0d7e\n#define    RTL8367C_SVLAN_C2SCFG42_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG42_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG42_CTRL1    0x0d7f\n#define    RTL8367C_SVLAN_C2SCFG42_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG42_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG42_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG42_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG42_CTRL2    0x0d80\n#define    RTL8367C_SVLAN_C2SCFG42_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG42_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG43_CTRL0    0x0d81\n#define    RTL8367C_SVLAN_C2SCFG43_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG43_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG43_CTRL1    0x0d82\n#define    RTL8367C_SVLAN_C2SCFG43_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG43_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG43_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG43_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG43_CTRL2    0x0d83\n#define    RTL8367C_SVLAN_C2SCFG43_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG43_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG44_CTRL0    0x0d84\n#define    RTL8367C_SVLAN_C2SCFG44_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG44_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG44_CTRL1    0x0d85\n#define    RTL8367C_SVLAN_C2SCFG44_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG44_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG44_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG44_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG44_CTRL2    0x0d86\n#define    RTL8367C_SVLAN_C2SCFG44_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG44_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG45_CTRL0    0x0d87\n#define    RTL8367C_SVLAN_C2SCFG45_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG45_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG45_CTRL1    0x0d88\n#define    RTL8367C_SVLAN_C2SCFG45_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG45_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG45_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG45_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG45_CTRL2    0x0d89\n#define    RTL8367C_SVLAN_C2SCFG45_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG45_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG46_CTRL0    0x0d8a\n#define    RTL8367C_SVLAN_C2SCFG46_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG46_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG46_CTRL1    0x0d8b\n#define    RTL8367C_SVLAN_C2SCFG46_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG46_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG46_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG46_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG46_CTRL2    0x0d8c\n#define    RTL8367C_SVLAN_C2SCFG46_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG46_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG47_CTRL0    0x0d8d\n#define    RTL8367C_SVLAN_C2SCFG47_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG47_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG47_CTRL1    0x0d8e\n#define    RTL8367C_SVLAN_C2SCFG47_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG47_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG47_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG47_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG47_CTRL2    0x0d8f\n#define    RTL8367C_SVLAN_C2SCFG47_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG47_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG48_CTRL0    0x0d90\n#define    RTL8367C_SVLAN_C2SCFG48_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG48_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG48_CTRL1    0x0d91\n#define    RTL8367C_SVLAN_C2SCFG48_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG48_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG48_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG48_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG48_CTRL2    0x0d92\n#define    RTL8367C_SVLAN_C2SCFG48_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG48_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG49_CTRL0    0x0d93\n#define    RTL8367C_SVLAN_C2SCFG49_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG49_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG49_CTRL1    0x0d94\n#define    RTL8367C_SVLAN_C2SCFG49_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG49_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG49_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG49_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG49_CTRL2    0x0d95\n#define    RTL8367C_SVLAN_C2SCFG49_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG49_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG50_CTRL0    0x0d96\n#define    RTL8367C_SVLAN_C2SCFG50_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG50_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG50_CTRL1    0x0d97\n#define    RTL8367C_SVLAN_C2SCFG50_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG50_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG50_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG50_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG50_CTRL2    0x0d98\n#define    RTL8367C_SVLAN_C2SCFG50_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG50_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG51_CTRL0    0x0d99\n#define    RTL8367C_SVLAN_C2SCFG51_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG51_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG51_CTRL1    0x0d9a\n#define    RTL8367C_SVLAN_C2SCFG51_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG51_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG51_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG51_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG51_CTRL2    0x0d9b\n#define    RTL8367C_SVLAN_C2SCFG51_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG51_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG52_CTRL0    0x0d9c\n#define    RTL8367C_SVLAN_C2SCFG52_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG52_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG52_CTRL1    0x0d9d\n#define    RTL8367C_SVLAN_C2SCFG52_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG52_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG52_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG52_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG52_CTRL2    0x0d9e\n#define    RTL8367C_SVLAN_C2SCFG52_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG52_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG53_CTRL0    0x0d9f\n#define    RTL8367C_SVLAN_C2SCFG53_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG53_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG53_CTRL1    0x0da0\n#define    RTL8367C_SVLAN_C2SCFG53_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG53_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG53_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG53_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG53_CTRL2    0x0da1\n#define    RTL8367C_SVLAN_C2SCFG53_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG53_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG54_CTRL0    0x0da2\n#define    RTL8367C_SVLAN_C2SCFG54_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG54_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG54_CTRL1    0x0da3\n#define    RTL8367C_SVLAN_C2SCFG54_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG54_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG54_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG54_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG54_CTRL2    0x0da4\n#define    RTL8367C_SVLAN_C2SCFG54_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG54_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG55_CTRL0    0x0da5\n#define    RTL8367C_SVLAN_C2SCFG55_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG55_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG55_CTRL1    0x0da6\n#define    RTL8367C_SVLAN_C2SCFG55_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG55_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG55_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG55_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG55_CTRL2    0x0da7\n#define    RTL8367C_SVLAN_C2SCFG55_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG55_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG56_CTRL0    0x0da8\n#define    RTL8367C_SVLAN_C2SCFG56_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG56_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG56_CTRL1    0x0da9\n#define    RTL8367C_SVLAN_C2SCFG56_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG56_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG56_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG56_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG56_CTRL2    0x0daa\n#define    RTL8367C_SVLAN_C2SCFG56_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG56_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG57_CTRL0    0x0dab\n#define    RTL8367C_SVLAN_C2SCFG57_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG57_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG57_CTRL1    0x0dac\n#define    RTL8367C_SVLAN_C2SCFG57_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG57_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG57_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG57_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG57_CTRL2    0x0dad\n#define    RTL8367C_SVLAN_C2SCFG57_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG57_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG58_CTRL0    0x0dae\n#define    RTL8367C_SVLAN_C2SCFG58_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG58_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG58_CTRL1    0x0daf\n#define    RTL8367C_SVLAN_C2SCFG58_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG58_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG58_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG58_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG58_CTRL2    0x0db0\n#define    RTL8367C_SVLAN_C2SCFG58_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG58_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG59_CTRL0    0x0db1\n#define    RTL8367C_SVLAN_C2SCFG59_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG59_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG59_CTRL1    0x0db2\n#define    RTL8367C_SVLAN_C2SCFG59_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG59_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG59_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG59_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG59_CTRL2    0x0db3\n#define    RTL8367C_SVLAN_C2SCFG59_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG59_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG60_CTRL0    0x0db4\n#define    RTL8367C_SVLAN_C2SCFG60_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG60_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG60_CTRL1    0x0db5\n#define    RTL8367C_SVLAN_C2SCFG60_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG60_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG60_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG60_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG60_CTRL2    0x0db6\n#define    RTL8367C_SVLAN_C2SCFG60_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG60_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG61_CTRL0    0x0db7\n#define    RTL8367C_SVLAN_C2SCFG61_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG61_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG61_CTRL1    0x0db8\n#define    RTL8367C_SVLAN_C2SCFG61_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG61_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG61_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG61_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG61_CTRL2    0x0db9\n#define    RTL8367C_SVLAN_C2SCFG61_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG61_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG62_CTRL0    0x0dba\n#define    RTL8367C_SVLAN_C2SCFG62_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG62_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG62_CTRL1    0x0dbb\n#define    RTL8367C_SVLAN_C2SCFG62_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG62_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG62_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG62_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG62_CTRL2    0x0dbc\n#define    RTL8367C_SVLAN_C2SCFG62_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG62_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG63_CTRL0    0x0dbd\n#define    RTL8367C_SVLAN_C2SCFG63_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG63_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG63_CTRL1    0x0dbe\n#define    RTL8367C_SVLAN_C2SCFG63_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG63_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG63_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG63_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG63_CTRL2    0x0dbf\n#define    RTL8367C_SVLAN_C2SCFG63_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG63_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG64_CTRL0    0x0dc0\n#define    RTL8367C_SVLAN_C2SCFG64_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG64_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG64_CTRL1    0x0dc1\n#define    RTL8367C_SVLAN_C2SCFG64_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG64_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG64_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG64_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG64_CTRL2    0x0dc2\n#define    RTL8367C_SVLAN_C2SCFG64_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG64_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG65_CTRL0    0x0dc3\n#define    RTL8367C_SVLAN_C2SCFG65_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG65_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG65_CTRL1    0x0dc4\n#define    RTL8367C_SVLAN_C2SCFG65_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG65_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG65_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG65_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG65_CTRL2    0x0dc5\n#define    RTL8367C_SVLAN_C2SCFG65_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG65_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG66_CTRL0    0x0dc6\n#define    RTL8367C_SVLAN_C2SCFG66_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG66_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG66_CTRL1    0x0dc7\n#define    RTL8367C_SVLAN_C2SCFG66_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG66_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG66_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG66_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG66_CTRL2    0x0dc8\n#define    RTL8367C_SVLAN_C2SCFG66_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG66_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG67_CTRL0    0x0dc9\n#define    RTL8367C_SVLAN_C2SCFG67_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG67_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG67_CTRL1    0x0dca\n#define    RTL8367C_SVLAN_C2SCFG67_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG67_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG67_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG67_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG67_CTRL2    0x0dcb\n#define    RTL8367C_SVLAN_C2SCFG67_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG67_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG68_CTRL0    0x0dcc\n#define    RTL8367C_SVLAN_C2SCFG68_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG68_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG68_CTRL1    0x0dcd\n#define    RTL8367C_SVLAN_C2SCFG68_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG68_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG68_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG68_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG68_CTRL2    0x0dce\n#define    RTL8367C_SVLAN_C2SCFG68_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG68_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG69_CTRL0    0x0dcf\n#define    RTL8367C_SVLAN_C2SCFG69_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG69_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG69_CTRL1    0x0dd0\n#define    RTL8367C_SVLAN_C2SCFG69_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG69_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG69_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG69_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG69_CTRL2    0x0dd1\n#define    RTL8367C_SVLAN_C2SCFG69_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG69_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG70_CTRL0    0x0dd2\n#define    RTL8367C_SVLAN_C2SCFG70_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG70_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG70_CTRL1    0x0dd3\n#define    RTL8367C_SVLAN_C2SCFG70_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG70_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG70_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG70_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG70_CTRL2    0x0dd4\n#define    RTL8367C_SVLAN_C2SCFG70_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG70_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG71_CTRL0    0x0dd5\n#define    RTL8367C_SVLAN_C2SCFG71_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG71_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG71_CTRL1    0x0dd6\n#define    RTL8367C_SVLAN_C2SCFG71_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG71_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG71_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG71_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG71_CTRL2    0x0dd7\n#define    RTL8367C_SVLAN_C2SCFG71_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG71_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG72_CTRL0    0x0dd8\n#define    RTL8367C_SVLAN_C2SCFG72_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG72_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG72_CTRL1    0x0dd9\n#define    RTL8367C_SVLAN_C2SCFG72_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG72_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG72_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG72_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG72_CTRL2    0x0dda\n#define    RTL8367C_SVLAN_C2SCFG72_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG72_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG73_CTRL0    0x0ddb\n#define    RTL8367C_SVLAN_C2SCFG73_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG73_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG73_CTRL1    0x0ddc\n#define    RTL8367C_SVLAN_C2SCFG73_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG73_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG73_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG73_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG73_CTRL2    0x0ddd\n#define    RTL8367C_SVLAN_C2SCFG73_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG73_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG74_CTRL0    0x0dde\n#define    RTL8367C_SVLAN_C2SCFG74_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG74_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG74_CTRL1    0x0ddf\n#define    RTL8367C_SVLAN_C2SCFG74_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG74_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG74_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG74_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG74_CTRL2    0x0de0\n#define    RTL8367C_SVLAN_C2SCFG74_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG74_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG75_CTRL0    0x0de1\n#define    RTL8367C_SVLAN_C2SCFG75_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG75_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG75_CTRL1    0x0de2\n#define    RTL8367C_SVLAN_C2SCFG75_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG75_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG75_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG75_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG75_CTRL2    0x0de3\n#define    RTL8367C_SVLAN_C2SCFG75_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG75_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG76_CTRL0    0x0de4\n#define    RTL8367C_SVLAN_C2SCFG76_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG76_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG76_CTRL1    0x0de5\n#define    RTL8367C_SVLAN_C2SCFG76_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG76_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG76_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG76_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG76_CTRL2    0x0de6\n#define    RTL8367C_SVLAN_C2SCFG76_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG76_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG77_CTRL0    0x0de7\n#define    RTL8367C_SVLAN_C2SCFG77_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG77_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG77_CTRL1    0x0de8\n#define    RTL8367C_SVLAN_C2SCFG77_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG77_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG77_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG77_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG77_CTRL2    0x0de9\n#define    RTL8367C_SVLAN_C2SCFG77_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG77_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG78_CTRL0    0x0dea\n#define    RTL8367C_SVLAN_C2SCFG78_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG78_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG78_CTRL1    0x0deb\n#define    RTL8367C_SVLAN_C2SCFG78_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG78_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG78_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG78_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG78_CTRL2    0x0dec\n#define    RTL8367C_SVLAN_C2SCFG78_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG78_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG79_CTRL0    0x0ded\n#define    RTL8367C_SVLAN_C2SCFG79_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG79_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG79_CTRL1    0x0dee\n#define    RTL8367C_SVLAN_C2SCFG79_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG79_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG79_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG79_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG79_CTRL2    0x0def\n#define    RTL8367C_SVLAN_C2SCFG79_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG79_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG80_CTRL0    0x0df0\n#define    RTL8367C_SVLAN_C2SCFG80_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG80_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG80_CTRL1    0x0df1\n#define    RTL8367C_SVLAN_C2SCFG80_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG80_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG80_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG80_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG80_CTRL2    0x0df2\n#define    RTL8367C_SVLAN_C2SCFG80_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG80_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG81_CTRL0    0x0df3\n#define    RTL8367C_SVLAN_C2SCFG81_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG81_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG81_CTRL1    0x0df4\n#define    RTL8367C_SVLAN_C2SCFG81_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG81_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG81_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG81_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG81_CTRL2    0x0df5\n#define    RTL8367C_SVLAN_C2SCFG81_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG81_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG82_CTRL0    0x0df6\n#define    RTL8367C_SVLAN_C2SCFG82_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG82_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG82_CTRL1    0x0df7\n#define    RTL8367C_SVLAN_C2SCFG82_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG82_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG82_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG82_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG82_CTRL2    0x0df8\n#define    RTL8367C_SVLAN_C2SCFG82_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG82_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG83_CTRL0    0x0df9\n#define    RTL8367C_SVLAN_C2SCFG83_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG83_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG83_CTRL1    0x0dfa\n#define    RTL8367C_SVLAN_C2SCFG83_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG83_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG83_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG83_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG83_CTRL2    0x0dfb\n#define    RTL8367C_SVLAN_C2SCFG83_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG83_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG84_CTRL0    0x0dfc\n#define    RTL8367C_SVLAN_C2SCFG84_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG84_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG84_CTRL1    0x0dfd\n#define    RTL8367C_SVLAN_C2SCFG84_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG84_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG84_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG84_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG84_CTRL2    0x0dfe\n#define    RTL8367C_SVLAN_C2SCFG84_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG84_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG85_CTRL0    0x0dff\n#define    RTL8367C_SVLAN_C2SCFG85_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG85_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG85_CTRL1    0x0e00\n#define    RTL8367C_SVLAN_C2SCFG85_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG85_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG85_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG85_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG85_CTRL2    0x0e01\n#define    RTL8367C_SVLAN_C2SCFG85_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG85_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG86_CTRL0    0x0e02\n#define    RTL8367C_SVLAN_C2SCFG86_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG86_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG86_CTRL1    0x0e03\n#define    RTL8367C_SVLAN_C2SCFG86_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG86_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG86_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG86_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG86_CTRL2    0x0e04\n#define    RTL8367C_SVLAN_C2SCFG86_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG86_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG87_CTRL0    0x0e05\n#define    RTL8367C_SVLAN_C2SCFG87_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG87_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG87_CTRL1    0x0e06\n#define    RTL8367C_SVLAN_C2SCFG87_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG87_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG87_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG87_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG87_CTRL2    0x0e07\n#define    RTL8367C_SVLAN_C2SCFG87_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG87_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG88_CTRL0    0x0e08\n#define    RTL8367C_SVLAN_C2SCFG88_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG88_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG88_CTRL1    0x0e09\n#define    RTL8367C_SVLAN_C2SCFG88_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG88_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG88_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG88_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG88_CTRL2    0x0e0a\n#define    RTL8367C_SVLAN_C2SCFG88_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG88_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG89_CTRL0    0x0e0b\n#define    RTL8367C_SVLAN_C2SCFG89_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG89_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG89_CTRL1    0x0e0c\n#define    RTL8367C_SVLAN_C2SCFG89_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG89_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG89_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG89_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG89_CTRL2    0x0e0d\n#define    RTL8367C_SVLAN_C2SCFG89_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG89_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG90_CTRL0    0x0e0e\n#define    RTL8367C_SVLAN_C2SCFG90_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG90_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG90_CTRL1    0x0e0f\n#define    RTL8367C_SVLAN_C2SCFG90_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG90_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG90_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG90_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG90_CTRL2    0x0e10\n#define    RTL8367C_SVLAN_C2SCFG90_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG90_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG91_CTRL0    0x0e11\n#define    RTL8367C_SVLAN_C2SCFG91_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG91_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG91_CTRL1    0x0e12\n#define    RTL8367C_SVLAN_C2SCFG91_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG91_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG91_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG91_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG91_CTRL2    0x0e13\n#define    RTL8367C_SVLAN_C2SCFG91_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG91_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG92_CTRL0    0x0e14\n#define    RTL8367C_SVLAN_C2SCFG92_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG92_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG92_CTRL1    0x0e15\n#define    RTL8367C_SVLAN_C2SCFG92_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG92_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG92_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG92_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG92_CTRL2    0x0e16\n#define    RTL8367C_SVLAN_C2SCFG92_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG92_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG93_CTRL0    0x0e17\n#define    RTL8367C_SVLAN_C2SCFG93_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG93_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG93_CTRL1    0x0e18\n#define    RTL8367C_SVLAN_C2SCFG93_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG93_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG93_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG93_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG93_CTRL2    0x0e19\n#define    RTL8367C_SVLAN_C2SCFG93_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG93_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG94_CTRL0    0x0e1a\n#define    RTL8367C_SVLAN_C2SCFG94_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG94_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG94_CTRL1    0x0e1b\n#define    RTL8367C_SVLAN_C2SCFG94_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG94_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG94_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG94_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG94_CTRL2    0x0e1c\n#define    RTL8367C_SVLAN_C2SCFG94_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG94_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG95_CTRL0    0x0e1d\n#define    RTL8367C_SVLAN_C2SCFG95_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG95_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG95_CTRL1    0x0e1e\n#define    RTL8367C_SVLAN_C2SCFG95_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG95_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG95_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG95_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG95_CTRL2    0x0e1f\n#define    RTL8367C_SVLAN_C2SCFG95_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG95_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG96_CTRL0    0x0e20\n#define    RTL8367C_SVLAN_C2SCFG96_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG96_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG96_CTRL1    0x0e21\n#define    RTL8367C_SVLAN_C2SCFG96_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG96_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG96_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG96_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG96_CTRL2    0x0e22\n#define    RTL8367C_SVLAN_C2SCFG96_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG96_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG97_CTRL0    0x0e23\n#define    RTL8367C_SVLAN_C2SCFG97_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG97_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG97_CTRL1    0x0e24\n#define    RTL8367C_SVLAN_C2SCFG97_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG97_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG97_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG97_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG97_CTRL2    0x0e25\n#define    RTL8367C_SVLAN_C2SCFG97_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG97_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG98_CTRL0    0x0e26\n#define    RTL8367C_SVLAN_C2SCFG98_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG98_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG98_CTRL1    0x0e27\n#define    RTL8367C_SVLAN_C2SCFG98_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG98_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG98_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG98_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG98_CTRL2    0x0e28\n#define    RTL8367C_SVLAN_C2SCFG98_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG98_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG99_CTRL0    0x0e29\n#define    RTL8367C_SVLAN_C2SCFG99_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG99_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG99_CTRL1    0x0e2a\n#define    RTL8367C_SVLAN_C2SCFG99_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG99_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG99_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG99_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG99_CTRL2    0x0e2b\n#define    RTL8367C_SVLAN_C2SCFG99_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG99_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG100_CTRL0    0x0e2c\n#define    RTL8367C_SVLAN_C2SCFG100_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG100_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG100_CTRL1    0x0e2d\n#define    RTL8367C_SVLAN_C2SCFG100_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG100_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG100_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG100_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG100_CTRL2    0x0e2e\n#define    RTL8367C_SVLAN_C2SCFG100_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG100_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG101_CTRL0    0x0e2f\n#define    RTL8367C_SVLAN_C2SCFG101_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG101_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG101_CTRL1    0x0e30\n#define    RTL8367C_SVLAN_C2SCFG101_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG101_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG101_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG101_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG101_CTRL2    0x0e31\n#define    RTL8367C_SVLAN_C2SCFG101_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG101_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG102_CTRL0    0x0e32\n#define    RTL8367C_SVLAN_C2SCFG102_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG102_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG102_CTRL1    0x0e33\n#define    RTL8367C_SVLAN_C2SCFG102_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG102_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG102_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG102_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG102_CTRL2    0x0e34\n#define    RTL8367C_SVLAN_C2SCFG102_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG102_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG103_CTRL0    0x0e35\n#define    RTL8367C_SVLAN_C2SCFG103_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG103_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG103_CTRL1    0x0e36\n#define    RTL8367C_SVLAN_C2SCFG103_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG103_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG103_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG103_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG103_CTRL2    0x0e37\n#define    RTL8367C_SVLAN_C2SCFG103_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG103_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG104_CTRL0    0x0e38\n#define    RTL8367C_SVLAN_C2SCFG104_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG104_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG104_CTRL1    0x0e39\n#define    RTL8367C_SVLAN_C2SCFG104_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG104_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG104_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG104_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG104_CTRL2    0x0e3a\n#define    RTL8367C_SVLAN_C2SCFG104_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG104_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG105_CTRL0    0x0e3b\n#define    RTL8367C_SVLAN_C2SCFG105_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG105_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG105_CTRL1    0x0e3c\n#define    RTL8367C_SVLAN_C2SCFG105_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG105_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG105_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG105_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG105_CTRL2    0x0e3d\n#define    RTL8367C_SVLAN_C2SCFG105_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG105_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG106_CTRL0    0x0e3e\n#define    RTL8367C_SVLAN_C2SCFG106_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG106_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG106_CTRL1    0x0e3f\n#define    RTL8367C_SVLAN_C2SCFG106_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG106_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG106_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG106_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG106_CTRL2    0x0e40\n#define    RTL8367C_SVLAN_C2SCFG106_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG106_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG107_CTRL0    0x0e41\n#define    RTL8367C_SVLAN_C2SCFG107_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG107_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG107_CTRL1    0x0e42\n#define    RTL8367C_SVLAN_C2SCFG107_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG107_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG107_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG107_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG107_CTRL2    0x0e43\n#define    RTL8367C_SVLAN_C2SCFG107_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG107_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG108_CTRL0    0x0e44\n#define    RTL8367C_SVLAN_C2SCFG108_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG108_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG108_CTRL1    0x0e45\n#define    RTL8367C_SVLAN_C2SCFG108_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG108_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG108_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG108_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG108_CTRL2    0x0e46\n#define    RTL8367C_SVLAN_C2SCFG108_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG108_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG109_CTRL0    0x0e47\n#define    RTL8367C_SVLAN_C2SCFG109_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG109_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG109_CTRL1    0x0e48\n#define    RTL8367C_SVLAN_C2SCFG109_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG109_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG109_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG109_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG109_CTRL2    0x0e49\n#define    RTL8367C_SVLAN_C2SCFG109_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG109_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG110_CTRL0    0x0e4a\n#define    RTL8367C_SVLAN_C2SCFG110_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG110_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG110_CTRL1    0x0e4b\n#define    RTL8367C_SVLAN_C2SCFG110_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG110_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG110_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG110_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG110_CTRL2    0x0e4c\n#define    RTL8367C_SVLAN_C2SCFG110_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG110_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG111_CTRL0    0x0e4d\n#define    RTL8367C_SVLAN_C2SCFG111_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG111_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG111_CTRL1    0x0e4e\n#define    RTL8367C_SVLAN_C2SCFG111_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG111_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG111_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG111_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG111_CTRL2    0x0e4f\n#define    RTL8367C_SVLAN_C2SCFG111_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG111_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG112_CTRL0    0x0e50\n#define    RTL8367C_SVLAN_C2SCFG112_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG112_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG112_CTRL1    0x0e51\n#define    RTL8367C_SVLAN_C2SCFG112_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG112_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG112_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG112_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG112_CTRL2    0x0e52\n#define    RTL8367C_SVLAN_C2SCFG112_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG112_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG113_CTRL0    0x0e53\n#define    RTL8367C_SVLAN_C2SCFG113_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG113_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG113_CTRL1    0x0e54\n#define    RTL8367C_SVLAN_C2SCFG113_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG113_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG113_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG113_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG113_CTRL2    0x0e55\n#define    RTL8367C_SVLAN_C2SCFG113_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG113_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG114_CTRL0    0x0e56\n#define    RTL8367C_SVLAN_C2SCFG114_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG114_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG114_CTRL1    0x0e57\n#define    RTL8367C_SVLAN_C2SCFG114_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG114_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG114_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG114_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG114_CTRL2    0x0e58\n#define    RTL8367C_SVLAN_C2SCFG114_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG114_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG115_CTRL0    0x0e59\n#define    RTL8367C_SVLAN_C2SCFG115_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG115_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG115_CTRL1    0x0e5a\n#define    RTL8367C_SVLAN_C2SCFG115_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG115_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG115_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG115_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG115_CTRL2    0x0e5b\n#define    RTL8367C_SVLAN_C2SCFG115_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG115_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG116_CTRL0    0x0e5c\n#define    RTL8367C_SVLAN_C2SCFG116_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG116_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG116_CTRL1    0x0e5d\n#define    RTL8367C_SVLAN_C2SCFG116_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG116_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG116_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG116_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG116_CTRL2    0x0e5e\n#define    RTL8367C_SVLAN_C2SCFG116_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG116_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG117_CTRL0    0x0e5f\n#define    RTL8367C_SVLAN_C2SCFG117_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG117_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG117_CTRL1    0x0e60\n#define    RTL8367C_SVLAN_C2SCFG117_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG117_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG117_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG117_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG117_CTRL2    0x0e61\n#define    RTL8367C_SVLAN_C2SCFG117_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG117_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG118_CTRL0    0x0e62\n#define    RTL8367C_SVLAN_C2SCFG118_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG118_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG118_CTRL1    0x0e63\n#define    RTL8367C_SVLAN_C2SCFG118_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG118_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG118_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG118_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG118_CTRL2    0x0e64\n#define    RTL8367C_SVLAN_C2SCFG118_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG118_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG119_CTRL0    0x0e65\n#define    RTL8367C_SVLAN_C2SCFG119_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG119_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG119_CTRL1    0x0e66\n#define    RTL8367C_SVLAN_C2SCFG119_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG119_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG119_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG119_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG119_CTRL2    0x0e67\n#define    RTL8367C_SVLAN_C2SCFG119_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG119_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG120_CTRL0    0x0e68\n#define    RTL8367C_SVLAN_C2SCFG120_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG120_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG120_CTRL1    0x0e69\n#define    RTL8367C_SVLAN_C2SCFG120_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG120_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG120_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG120_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG120_CTRL2    0x0e6a\n#define    RTL8367C_SVLAN_C2SCFG120_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG120_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG121_CTRL0    0x0e6b\n#define    RTL8367C_SVLAN_C2SCFG121_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG121_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG121_CTRL1    0x0e6c\n#define    RTL8367C_SVLAN_C2SCFG121_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG121_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG121_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG121_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG121_CTRL2    0x0e6d\n#define    RTL8367C_SVLAN_C2SCFG121_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG121_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG122_CTRL0    0x0e6e\n#define    RTL8367C_SVLAN_C2SCFG122_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG122_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG122_CTRL1    0x0e6f\n#define    RTL8367C_SVLAN_C2SCFG122_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG122_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG122_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG122_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG122_CTRL2    0x0e70\n#define    RTL8367C_SVLAN_C2SCFG122_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG122_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG123_CTRL0    0x0e71\n#define    RTL8367C_SVLAN_C2SCFG123_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG123_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG123_CTRL1    0x0e72\n#define    RTL8367C_SVLAN_C2SCFG123_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG123_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG123_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG123_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG123_CTRL2    0x0e73\n#define    RTL8367C_SVLAN_C2SCFG123_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG123_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG124_CTRL0    0x0e74\n#define    RTL8367C_SVLAN_C2SCFG124_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG124_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG124_CTRL1    0x0e75\n#define    RTL8367C_SVLAN_C2SCFG124_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG124_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG124_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG124_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG124_CTRL2    0x0e76\n#define    RTL8367C_SVLAN_C2SCFG124_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG124_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG125_CTRL0    0x0e77\n#define    RTL8367C_SVLAN_C2SCFG125_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG125_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG125_CTRL1    0x0e78\n#define    RTL8367C_SVLAN_C2SCFG125_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG125_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG125_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG125_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG125_CTRL2    0x0e79\n#define    RTL8367C_SVLAN_C2SCFG125_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG125_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG126_CTRL0    0x0e7a\n#define    RTL8367C_SVLAN_C2SCFG126_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG126_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG126_CTRL1    0x0e7b\n#define    RTL8367C_SVLAN_C2SCFG126_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG126_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG126_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG126_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG126_CTRL2    0x0e7c\n#define    RTL8367C_SVLAN_C2SCFG126_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG126_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG127_CTRL0    0x0e7d\n#define    RTL8367C_SVLAN_C2SCFG127_CTRL0_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG127_CTRL0_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_C2SCFG127_CTRL1    0x0e7e\n#define    RTL8367C_SVLAN_C2SCFG127_CTRL1_C2SENPMSK_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_C2SCFG127_CTRL1_C2SENPMSK_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_C2SCFG127_CTRL1_C2SENPMSK_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG127_CTRL1_C2SENPMSK_MASK    0xFF\n\n#define    RTL8367C_REG_SVLAN_C2SCFG127_CTRL2    0x0e7f\n#define    RTL8367C_SVLAN_C2SCFG127_CTRL2_OFFSET    0\n#define    RTL8367C_SVLAN_C2SCFG127_CTRL2_MASK    0x1FFF\n\n#define    RTL8367C_REG_SVLAN_CFG    0x0e80\n#define    RTL8367C_VS_PORT7_DMACVIDSEL_OFFSET    14\n#define    RTL8367C_VS_PORT7_DMACVIDSEL_MASK    0x4000\n#define    RTL8367C_VS_PORT6_DMACVIDSEL_OFFSET    13\n#define    RTL8367C_VS_PORT6_DMACVIDSEL_MASK    0x2000\n#define    RTL8367C_VS_PORT5_DMACVIDSEL_OFFSET    12\n#define    RTL8367C_VS_PORT5_DMACVIDSEL_MASK    0x1000\n#define    RTL8367C_VS_PORT4_DMACVIDSEL_OFFSET    11\n#define    RTL8367C_VS_PORT4_DMACVIDSEL_MASK    0x800\n#define    RTL8367C_VS_PORT3_DMACVIDSEL_OFFSET    10\n#define    RTL8367C_VS_PORT3_DMACVIDSEL_MASK    0x400\n#define    RTL8367C_VS_PORT2_DMACVIDSEL_OFFSET    9\n#define    RTL8367C_VS_PORT2_DMACVIDSEL_MASK    0x200\n#define    RTL8367C_VS_PORT1_DMACVIDSEL_OFFSET    8\n#define    RTL8367C_VS_PORT1_DMACVIDSEL_MASK    0x100\n#define    RTL8367C_VS_PORT0_DMACVIDSEL_OFFSET    7\n#define    RTL8367C_VS_PORT0_DMACVIDSEL_MASK    0x80\n#define    RTL8367C_VS_UIFSEG_OFFSET    6\n#define    RTL8367C_VS_UIFSEG_MASK    0x40\n#define    RTL8367C_VS_UNMAT_OFFSET    4\n#define    RTL8367C_VS_UNMAT_MASK    0x30\n#define    RTL8367C_VS_UNTAG_OFFSET    2\n#define    RTL8367C_VS_UNTAG_MASK    0xC\n#define    RTL8367C_VS_SPRISEL_OFFSET    0\n#define    RTL8367C_VS_SPRISEL_MASK    0x3\n\n#define    RTL8367C_REG_SVLAN_PORTBASED_SVIDX_CTRL0    0x0e81\n#define    RTL8367C_VS_PORT1_SVIDX_OFFSET    8\n#define    RTL8367C_VS_PORT1_SVIDX_MASK    0x3F00\n#define    RTL8367C_VS_PORT0_SVIDX_OFFSET    0\n#define    RTL8367C_VS_PORT0_SVIDX_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_PORTBASED_SVIDX_CTRL1    0x0e82\n#define    RTL8367C_VS_PORT3_SVIDX_OFFSET    8\n#define    RTL8367C_VS_PORT3_SVIDX_MASK    0x3F00\n#define    RTL8367C_VS_PORT2_SVIDX_OFFSET    0\n#define    RTL8367C_VS_PORT2_SVIDX_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_PORTBASED_SVIDX_CTRL2    0x0e83\n#define    RTL8367C_VS_PORT5_SVIDX_OFFSET    8\n#define    RTL8367C_VS_PORT5_SVIDX_MASK    0x3F00\n#define    RTL8367C_VS_PORT4_SVIDX_OFFSET    0\n#define    RTL8367C_VS_PORT4_SVIDX_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_PORTBASED_SVIDX_CTRL3    0x0e84\n#define    RTL8367C_VS_PORT7_SVIDX_OFFSET    8\n#define    RTL8367C_VS_PORT7_SVIDX_MASK    0x3F00\n#define    RTL8367C_VS_PORT6_SVIDX_OFFSET    0\n#define    RTL8367C_VS_PORT6_SVIDX_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_UNTAG_UNMAT_CFG    0x0e85\n#define    RTL8367C_VS_UNTAG_SVIDX_OFFSET    8\n#define    RTL8367C_VS_UNTAG_SVIDX_MASK    0x3F00\n#define    RTL8367C_VS_UNMAT_SVIDX_OFFSET    0\n#define    RTL8367C_VS_UNMAT_SVIDX_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_LOOKUP_TYPE    0x0e86\n#define    RTL8367C_SVLAN_LOOKUP_TYPE_OFFSET    0\n#define    RTL8367C_SVLAN_LOOKUP_TYPE_MASK    0x1\n\n#define    RTL8367C_REG_IPMC_GROUP_VALID_15_0    0x0e87\n\n#define    RTL8367C_REG_IPMC_GROUP_VALID_31_16    0x0e88\n\n#define    RTL8367C_REG_IPMC_GROUP_VALID_47_32    0x0e89\n\n#define    RTL8367C_REG_IPMC_GROUP_VALID_63_48    0x0e8a\n\n#define    RTL8367C_REG_SVLAN_PORTBASED_SVIDX_CTRL4    0x0e8b\n#define    RTL8367C_VS_PORT9_SVIDX_OFFSET    8\n#define    RTL8367C_VS_PORT9_SVIDX_MASK    0x3F00\n#define    RTL8367C_VS_PORT8_SVIDX_OFFSET    0\n#define    RTL8367C_VS_PORT8_SVIDX_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_PORTBASED_SVIDX_CTRL5    0x0e8c\n#define    RTL8367C_SVLAN_PORTBASED_SVIDX_CTRL5_OFFSET    0\n#define    RTL8367C_SVLAN_PORTBASED_SVIDX_CTRL5_MASK    0x3F\n\n#define    RTL8367C_REG_SVLAN_CFG_EXT    0x0e8d\n#define    RTL8367C_VS_PORT10_DMACVIDSEL_OFFSET    2\n#define    RTL8367C_VS_PORT10_DMACVIDSEL_MASK    0x4\n#define    RTL8367C_VS_PORT9_DMACVIDSEL_OFFSET    1\n#define    RTL8367C_VS_PORT9_DMACVIDSEL_MASK    0x2\n#define    RTL8367C_VS_PORT8_DMACVIDSEL_OFFSET    0\n#define    RTL8367C_VS_PORT8_DMACVIDSEL_MASK    0x1\n\n#define    RTL8367C_REG_SVLAN_MEMBERCFG63_CTRL4    0x0e8e\n#define    RTL8367C_SVLAN_MEMBERCFG63_CTRL4_VS_UNTAGSET_EXT_OFFSET    8\n#define    RTL8367C_SVLAN_MEMBERCFG63_CTRL4_VS_UNTAGSET_EXT_MASK    0x700\n#define    RTL8367C_SVLAN_MEMBERCFG63_CTRL4_VS_SMBR_EXT_OFFSET    0\n#define    RTL8367C_SVLAN_MEMBERCFG63_CTRL4_VS_SMBR_EXT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_DUMMY_0    0x0e90\n\n#define    RTL8367C_REG_SVLAN_DUMMY_1    0x0e91\n\n#define    RTL8367C_REG_SVLAN_DUMMY_2    0x0e92\n\n#define    RTL8367C_REG_SVLAN_DUMMY_3    0x0e93\n\n#define    RTL8367C_REG_SVLAN_DUMMY_4    0x0e94\n\n#define    RTL8367C_REG_SVLAN_DUMMY_5    0x0e95\n\n#define    RTL8367C_REG_SVLAN_DUMMY_6    0x0e96\n\n#define    RTL8367C_REG_SVLAN_DUMMY_7    0x0e97\n\n#define    RTL8367C_REG_SVLAN_DUMMY_8    0x0e98\n\n#define    RTL8367C_REG_SVLAN_DUMMY_9    0x0e99\n\n#define    RTL8367C_REG_SVLAN_DUMMY_10    0x0e9a\n\n#define    RTL8367C_REG_SVLAN_DUMMY_11    0x0e9b\n\n#define    RTL8367C_REG_SVLAN_DUMMY_12    0x0e9c\n\n#define    RTL8367C_REG_SVLAN_DUMMY_13    0x0e9d\n\n#define    RTL8367C_REG_SVLAN_DUMMY_14    0x0e9e\n\n#define    RTL8367C_REG_SVLAN_DUMMY_15    0x0e9f\n\n#define    RTL8367C_REG_SVLAN_DUMMY_16    0x0ea0\n\n#define    RTL8367C_REG_SVLAN_DUMMY_17    0x0ea1\n\n#define    RTL8367C_REG_SVLAN_DUMMY_18    0x0ea2\n\n#define    RTL8367C_REG_SVLAN_DUMMY_19    0x0ea3\n\n#define    RTL8367C_REG_SVLAN_DUMMY_20    0x0ea4\n\n#define    RTL8367C_REG_SVLAN_DUMMY_21    0x0ea5\n\n#define    RTL8367C_REG_SVLAN_DUMMY_22    0x0ea6\n\n#define    RTL8367C_REG_SVLAN_DUMMY_23    0x0ea7\n\n#define    RTL8367C_REG_SVLAN_DUMMY_24    0x0ea8\n\n#define    RTL8367C_REG_SVLAN_DUMMY_25    0x0ea9\n\n#define    RTL8367C_REG_SVLAN_DUMMY_26    0x0eaa\n\n#define    RTL8367C_REG_SVLAN_DUMMY_27    0x0eab\n\n#define    RTL8367C_REG_SVLAN_DUMMY_28    0x0eac\n\n#define    RTL8367C_REG_SVLAN_DUMMY_29    0x0ead\n\n#define    RTL8367C_REG_SVLAN_DUMMY_30    0x0eae\n\n#define    RTL8367C_REG_SVLAN_DUMMY_31    0x0eaf\n\n#define    RTL8367C_REG_IPMC_GROUP_VID_00    0x0eb0\n#define    RTL8367C_IPMC_GROUP_VID_00_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_VID_00_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_VID_01    0x0eb1\n#define    RTL8367C_IPMC_GROUP_VID_01_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_VID_01_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_VID_02    0x0eb2\n#define    RTL8367C_IPMC_GROUP_VID_02_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_VID_02_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_VID_03    0x0eb3\n#define    RTL8367C_IPMC_GROUP_VID_03_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_VID_03_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_VID_04    0x0eb4\n#define    RTL8367C_IPMC_GROUP_VID_04_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_VID_04_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_VID_05    0x0eb5\n#define    RTL8367C_IPMC_GROUP_VID_05_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_VID_05_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_VID_06    0x0eb6\n#define    RTL8367C_IPMC_GROUP_VID_06_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_VID_06_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_VID_07    0x0eb7\n#define    RTL8367C_IPMC_GROUP_VID_07_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_VID_07_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_VID_08    0x0eb8\n#define    RTL8367C_IPMC_GROUP_VID_08_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_VID_08_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_VID_09    0x0eb9\n#define    RTL8367C_IPMC_GROUP_VID_09_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_VID_09_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_VID_10    0x0eba\n#define    RTL8367C_IPMC_GROUP_VID_10_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_VID_10_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_VID_11    0x0ebb\n#define    RTL8367C_IPMC_GROUP_VID_11_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_VID_11_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_VID_12    0x0ebc\n#define    RTL8367C_IPMC_GROUP_VID_12_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_VID_12_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_VID_13    0x0ebd\n#define    RTL8367C_IPMC_GROUP_VID_13_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_VID_13_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_VID_14    0x0ebe\n#define    RTL8367C_IPMC_GROUP_VID_14_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_VID_14_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_VID_15    0x0ebf\n#define    RTL8367C_IPMC_GROUP_VID_15_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_VID_15_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_VID_16    0x0ec0\n#define    RTL8367C_IPMC_GROUP_VID_16_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_VID_16_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_VID_17    0x0ec1\n#define    RTL8367C_IPMC_GROUP_VID_17_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_VID_17_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_VID_18    0x0ec2\n#define    RTL8367C_IPMC_GROUP_VID_18_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_VID_18_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_VID_19    0x0ec3\n#define    RTL8367C_IPMC_GROUP_VID_19_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_VID_19_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_VID_20    0x0ec4\n#define    RTL8367C_IPMC_GROUP_VID_20_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_VID_20_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_VID_21    0x0ec5\n#define    RTL8367C_IPMC_GROUP_VID_21_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_VID_21_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_VID_22    0x0ec6\n#define    RTL8367C_IPMC_GROUP_VID_22_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_VID_22_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_VID_23    0x0ec7\n#define    RTL8367C_IPMC_GROUP_VID_23_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_VID_23_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_VID_24    0x0ec8\n#define    RTL8367C_IPMC_GROUP_VID_24_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_VID_24_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_VID_25    0x0ec9\n#define    RTL8367C_IPMC_GROUP_VID_25_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_VID_25_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_VID_26    0x0eca\n#define    RTL8367C_IPMC_GROUP_VID_26_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_VID_26_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_VID_27    0x0ecb\n#define    RTL8367C_IPMC_GROUP_VID_27_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_VID_27_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_VID_28    0x0ecc\n#define    RTL8367C_IPMC_GROUP_VID_28_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_VID_28_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_VID_29    0x0ecd\n#define    RTL8367C_IPMC_GROUP_VID_29_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_VID_29_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_VID_30    0x0ece\n#define    RTL8367C_IPMC_GROUP_VID_30_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_VID_30_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_VID_31    0x0ecf\n#define    RTL8367C_IPMC_GROUP_VID_31_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_VID_31_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_VID_32    0x0ed0\n#define    RTL8367C_IPMC_GROUP_VID_32_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_VID_32_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_VID_33    0x0ed1\n#define    RTL8367C_IPMC_GROUP_VID_33_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_VID_33_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_VID_34    0x0ed2\n#define    RTL8367C_IPMC_GROUP_VID_34_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_VID_34_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_VID_35    0x0ed3\n#define    RTL8367C_IPMC_GROUP_VID_35_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_VID_35_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_VID_36    0x0ed4\n#define    RTL8367C_IPMC_GROUP_VID_36_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_VID_36_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_VID_37    0x0ed5\n#define    RTL8367C_IPMC_GROUP_VID_37_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_VID_37_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_VID_38    0x0ed6\n#define    RTL8367C_IPMC_GROUP_VID_38_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_VID_38_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_VID_39    0x0ed7\n#define    RTL8367C_IPMC_GROUP_VID_39_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_VID_39_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_VID_40    0x0ed8\n#define    RTL8367C_IPMC_GROUP_VID_40_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_VID_40_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_VID_41    0x0ed9\n#define    RTL8367C_IPMC_GROUP_VID_41_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_VID_41_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_VID_42    0x0eda\n#define    RTL8367C_IPMC_GROUP_VID_42_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_VID_42_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_VID_43    0x0edb\n#define    RTL8367C_IPMC_GROUP_VID_43_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_VID_43_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_VID_44    0x0edc\n#define    RTL8367C_IPMC_GROUP_VID_44_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_VID_44_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_VID_45    0x0edd\n#define    RTL8367C_IPMC_GROUP_VID_45_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_VID_45_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_VID_46    0x0ede\n#define    RTL8367C_IPMC_GROUP_VID_46_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_VID_46_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_VID_47    0x0edf\n#define    RTL8367C_IPMC_GROUP_VID_47_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_VID_47_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_VID_48    0x0ef0\n#define    RTL8367C_IPMC_GROUP_VID_48_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_VID_48_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_VID_49    0x0ef1\n#define    RTL8367C_IPMC_GROUP_VID_49_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_VID_49_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_VID_50    0x0ef2\n#define    RTL8367C_IPMC_GROUP_VID_50_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_VID_50_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_VID_51    0x0ef3\n#define    RTL8367C_IPMC_GROUP_VID_51_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_VID_51_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_VID_52    0x0ef4\n#define    RTL8367C_IPMC_GROUP_VID_52_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_VID_52_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_VID_53    0x0ef5\n#define    RTL8367C_IPMC_GROUP_VID_53_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_VID_53_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_VID_54    0x0ef6\n#define    RTL8367C_IPMC_GROUP_VID_54_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_VID_54_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_VID_55    0x0ef7\n#define    RTL8367C_IPMC_GROUP_VID_55_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_VID_55_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_VID_56    0x0ef8\n#define    RTL8367C_IPMC_GROUP_VID_56_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_VID_56_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_VID_57    0x0ef9\n#define    RTL8367C_IPMC_GROUP_VID_57_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_VID_57_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_VID_58    0x0efa\n#define    RTL8367C_IPMC_GROUP_VID_58_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_VID_58_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_VID_59    0x0efb\n#define    RTL8367C_IPMC_GROUP_VID_59_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_VID_59_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_VID_60    0x0efc\n#define    RTL8367C_IPMC_GROUP_VID_60_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_VID_60_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_VID_61    0x0efd\n#define    RTL8367C_IPMC_GROUP_VID_61_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_VID_61_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_VID_62    0x0efe\n#define    RTL8367C_IPMC_GROUP_VID_62_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_VID_62_MASK    0xFFF\n\n#define    RTL8367C_REG_IPMC_GROUP_VID_63    0x0eff\n#define    RTL8367C_IPMC_GROUP_VID_63_OFFSET    0\n#define    RTL8367C_IPMC_GROUP_VID_63_MASK    0xFFF\n\n/* (16'h0f00)hsactrl_reg */\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY0_CTRL0    0x0f00\n#define    RTL8367C_SVLAN_SP2C_ENTRY0_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY0_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY0_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY0_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY0_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY0_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY0_CTRL1    0x0f01\n#define    RTL8367C_SVLAN_SP2C_ENTRY0_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY0_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY0_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY0_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY1_CTRL0    0x0f02\n#define    RTL8367C_SVLAN_SP2C_ENTRY1_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY1_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY1_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY1_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY1_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY1_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY1_CTRL1    0x0f03\n#define    RTL8367C_SVLAN_SP2C_ENTRY1_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY1_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY1_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY1_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY2_CTRL0    0x0f04\n#define    RTL8367C_SVLAN_SP2C_ENTRY2_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY2_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY2_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY2_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY2_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY2_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY2_CTRL1    0x0f05\n#define    RTL8367C_SVLAN_SP2C_ENTRY2_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY2_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY2_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY2_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY3_CTRL0    0x0f06\n#define    RTL8367C_SVLAN_SP2C_ENTRY3_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY3_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY3_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY3_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY3_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY3_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY3_CTRL1    0x0f07\n#define    RTL8367C_SVLAN_SP2C_ENTRY3_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY3_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY3_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY3_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY4_CTRL0    0x0f08\n#define    RTL8367C_SVLAN_SP2C_ENTRY4_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY4_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY4_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY4_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY4_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY4_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY4_CTRL1    0x0f09\n#define    RTL8367C_SVLAN_SP2C_ENTRY4_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY4_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY4_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY4_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY5_CTRL0    0x0f0a\n#define    RTL8367C_SVLAN_SP2C_ENTRY5_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY5_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY5_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY5_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY5_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY5_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY5_CTRL1    0x0f0b\n#define    RTL8367C_SVLAN_SP2C_ENTRY5_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY5_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY5_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY5_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY6_CTRL0    0x0f0c\n#define    RTL8367C_SVLAN_SP2C_ENTRY6_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY6_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY6_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY6_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY6_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY6_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY6_CTRL1    0x0f0d\n#define    RTL8367C_SVLAN_SP2C_ENTRY6_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY6_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY6_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY6_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY7_CTRL0    0x0f0e\n#define    RTL8367C_SVLAN_SP2C_ENTRY7_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY7_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY7_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY7_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY7_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY7_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY7_CTRL1    0x0f0f\n#define    RTL8367C_SVLAN_SP2C_ENTRY7_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY7_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY7_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY7_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY8_CTRL0    0x0f10\n#define    RTL8367C_SVLAN_SP2C_ENTRY8_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY8_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY8_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY8_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY8_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY8_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY8_CTRL1    0x0f11\n#define    RTL8367C_SVLAN_SP2C_ENTRY8_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY8_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY8_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY8_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY9_CTRL0    0x0f12\n#define    RTL8367C_SVLAN_SP2C_ENTRY9_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY9_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY9_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY9_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY9_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY9_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY9_CTRL1    0x0f13\n#define    RTL8367C_SVLAN_SP2C_ENTRY9_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY9_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY9_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY9_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY10_CTRL0    0x0f14\n#define    RTL8367C_SVLAN_SP2C_ENTRY10_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY10_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY10_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY10_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY10_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY10_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY10_CTRL1    0x0f15\n#define    RTL8367C_SVLAN_SP2C_ENTRY10_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY10_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY10_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY10_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY11_CTRL0    0x0f16\n#define    RTL8367C_SVLAN_SP2C_ENTRY11_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY11_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY11_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY11_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY11_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY11_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY11_CTRL1    0x0f17\n#define    RTL8367C_SVLAN_SP2C_ENTRY11_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY11_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY11_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY11_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY12_CTRL0    0x0f18\n#define    RTL8367C_SVLAN_SP2C_ENTRY12_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY12_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY12_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY12_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY12_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY12_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY12_CTRL1    0x0f19\n#define    RTL8367C_SVLAN_SP2C_ENTRY12_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY12_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY12_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY12_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY13_CTRL0    0x0f1a\n#define    RTL8367C_SVLAN_SP2C_ENTRY13_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY13_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY13_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY13_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY13_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY13_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY13_CTRL1    0x0f1b\n#define    RTL8367C_SVLAN_SP2C_ENTRY13_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY13_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY13_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY13_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY14_CTRL0    0x0f1c\n#define    RTL8367C_SVLAN_SP2C_ENTRY14_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY14_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY14_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY14_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY14_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY14_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY14_CTRL1    0x0f1d\n#define    RTL8367C_SVLAN_SP2C_ENTRY14_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY14_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY14_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY14_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY15_CTRL0    0x0f1e\n#define    RTL8367C_SVLAN_SP2C_ENTRY15_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY15_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY15_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY15_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY15_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY15_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY15_CTRL1    0x0f1f\n#define    RTL8367C_SVLAN_SP2C_ENTRY15_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY15_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY15_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY15_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY16_CTRL0    0x0f20\n#define    RTL8367C_SVLAN_SP2C_ENTRY16_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY16_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY16_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY16_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY16_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY16_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY16_CTRL1    0x0f21\n#define    RTL8367C_SVLAN_SP2C_ENTRY16_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY16_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY16_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY16_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY17_CTRL0    0x0f22\n#define    RTL8367C_SVLAN_SP2C_ENTRY17_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY17_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY17_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY17_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY17_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY17_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY17_CTRL1    0x0f23\n#define    RTL8367C_SVLAN_SP2C_ENTRY17_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY17_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY17_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY17_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY18_CTRL0    0x0f24\n#define    RTL8367C_SVLAN_SP2C_ENTRY18_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY18_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY18_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY18_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY18_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY18_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY18_CTRL1    0x0f25\n#define    RTL8367C_SVLAN_SP2C_ENTRY18_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY18_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY18_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY18_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY19_CTRL0    0x0f26\n#define    RTL8367C_SVLAN_SP2C_ENTRY19_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY19_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY19_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY19_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY19_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY19_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY19_CTRL1    0x0f27\n#define    RTL8367C_SVLAN_SP2C_ENTRY19_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY19_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY19_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY19_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY20_CTRL0    0x0f28\n#define    RTL8367C_SVLAN_SP2C_ENTRY20_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY20_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY20_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY20_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY20_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY20_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY20_CTRL1    0x0f29\n#define    RTL8367C_SVLAN_SP2C_ENTRY20_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY20_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY20_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY20_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY21_CTRL0    0x0f2a\n#define    RTL8367C_SVLAN_SP2C_ENTRY21_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY21_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY21_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY21_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY21_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY21_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY21_CTRL1    0x0f2b\n#define    RTL8367C_SVLAN_SP2C_ENTRY21_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY21_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY21_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY21_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY22_CTRL0    0x0f2c\n#define    RTL8367C_SVLAN_SP2C_ENTRY22_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY22_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY22_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY22_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY22_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY22_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY22_CTRL1    0x0f2d\n#define    RTL8367C_SVLAN_SP2C_ENTRY22_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY22_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY22_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY22_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY23_CTRL0    0x0f2e\n#define    RTL8367C_SVLAN_SP2C_ENTRY23_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY23_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY23_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY23_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY23_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY23_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY23_CTRL1    0x0f2f\n#define    RTL8367C_SVLAN_SP2C_ENTRY23_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY23_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY23_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY23_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY24_CTRL0    0x0f30\n#define    RTL8367C_SVLAN_SP2C_ENTRY24_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY24_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY24_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY24_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY24_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY24_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY24_CTRL1    0x0f31\n#define    RTL8367C_SVLAN_SP2C_ENTRY24_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY24_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY24_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY24_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY25_CTRL0    0x0f32\n#define    RTL8367C_SVLAN_SP2C_ENTRY25_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY25_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY25_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY25_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY25_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY25_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY25_CTRL1    0x0f33\n#define    RTL8367C_SVLAN_SP2C_ENTRY25_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY25_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY25_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY25_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY26_CTRL0    0x0f34\n#define    RTL8367C_SVLAN_SP2C_ENTRY26_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY26_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY26_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY26_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY26_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY26_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY26_CTRL1    0x0f35\n#define    RTL8367C_SVLAN_SP2C_ENTRY26_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY26_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY26_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY26_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY27_CTRL0    0x0f36\n#define    RTL8367C_SVLAN_SP2C_ENTRY27_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY27_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY27_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY27_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY27_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY27_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY27_CTRL1    0x0f37\n#define    RTL8367C_SVLAN_SP2C_ENTRY27_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY27_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY27_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY27_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY28_CTRL0    0x0f38\n#define    RTL8367C_SVLAN_SP2C_ENTRY28_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY28_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY28_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY28_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY28_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY28_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY28_CTRL1    0x0f39\n#define    RTL8367C_SVLAN_SP2C_ENTRY28_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY28_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY28_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY28_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY29_CTRL0    0x0f3a\n#define    RTL8367C_SVLAN_SP2C_ENTRY29_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY29_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY29_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY29_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY29_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY29_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY29_CTRL1    0x0f3b\n#define    RTL8367C_SVLAN_SP2C_ENTRY29_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY29_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY29_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY29_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY30_CTRL0    0x0f3c\n#define    RTL8367C_SVLAN_SP2C_ENTRY30_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY30_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY30_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY30_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY30_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY30_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY30_CTRL1    0x0f3d\n#define    RTL8367C_SVLAN_SP2C_ENTRY30_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY30_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY30_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY30_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY31_CTRL0    0x0f3e\n#define    RTL8367C_SVLAN_SP2C_ENTRY31_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY31_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY31_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY31_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY31_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY31_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY31_CTRL1    0x0f3f\n#define    RTL8367C_SVLAN_SP2C_ENTRY31_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY31_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY31_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY31_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY32_CTRL0    0x0f40\n#define    RTL8367C_SVLAN_SP2C_ENTRY32_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY32_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY32_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY32_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY32_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY32_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY32_CTRL1    0x0f41\n#define    RTL8367C_SVLAN_SP2C_ENTRY32_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY32_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY32_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY32_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY33_CTRL0    0x0f42\n#define    RTL8367C_SVLAN_SP2C_ENTRY33_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY33_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY33_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY33_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY33_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY33_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY33_CTRL1    0x0f43\n#define    RTL8367C_SVLAN_SP2C_ENTRY33_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY33_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY33_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY33_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY34_CTRL0    0x0f44\n#define    RTL8367C_SVLAN_SP2C_ENTRY34_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY34_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY34_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY34_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY34_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY34_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY34_CTRL1    0x0f45\n#define    RTL8367C_SVLAN_SP2C_ENTRY34_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY34_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY34_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY34_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY35_CTRL0    0x0f46\n#define    RTL8367C_SVLAN_SP2C_ENTRY35_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY35_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY35_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY35_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY35_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY35_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY35_CTRL1    0x0f47\n#define    RTL8367C_SVLAN_SP2C_ENTRY35_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY35_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY35_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY35_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY36_CTRL0    0x0f48\n#define    RTL8367C_SVLAN_SP2C_ENTRY36_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY36_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY36_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY36_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY36_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY36_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY36_CTRL1    0x0f49\n#define    RTL8367C_SVLAN_SP2C_ENTRY36_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY36_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY36_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY36_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY37_CTRL0    0x0f4a\n#define    RTL8367C_SVLAN_SP2C_ENTRY37_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY37_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY37_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY37_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY37_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY37_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY37_CTRL1    0x0f4b\n#define    RTL8367C_SVLAN_SP2C_ENTRY37_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY37_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY37_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY37_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY38_CTRL0    0x0f4c\n#define    RTL8367C_SVLAN_SP2C_ENTRY38_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY38_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY38_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY38_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY38_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY38_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY38_CTRL1    0x0f4d\n#define    RTL8367C_SVLAN_SP2C_ENTRY38_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY38_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY38_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY38_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY39_CTRL0    0x0f4e\n#define    RTL8367C_SVLAN_SP2C_ENTRY39_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY39_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY39_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY39_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY39_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY39_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY39_CTRL1    0x0f4f\n#define    RTL8367C_SVLAN_SP2C_ENTRY39_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY39_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY39_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY39_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY40_CTRL0    0x0f50\n#define    RTL8367C_SVLAN_SP2C_ENTRY40_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY40_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY40_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY40_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY40_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY40_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY40_CTRL1    0x0f51\n#define    RTL8367C_SVLAN_SP2C_ENTRY40_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY40_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY40_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY40_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY41_CTRL0    0x0f52\n#define    RTL8367C_SVLAN_SP2C_ENTRY41_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY41_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY41_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY41_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY41_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY41_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY41_CTRL1    0x0f53\n#define    RTL8367C_SVLAN_SP2C_ENTRY41_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY41_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY41_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY41_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY42_CTRL0    0x0f54\n#define    RTL8367C_SVLAN_SP2C_ENTRY42_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY42_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY42_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY42_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY42_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY42_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY42_CTRL1    0x0f55\n#define    RTL8367C_SVLAN_SP2C_ENTRY42_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY42_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY42_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY42_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY43_CTRL0    0x0f56\n#define    RTL8367C_SVLAN_SP2C_ENTRY43_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY43_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY43_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY43_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY43_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY43_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY43_CTRL1    0x0f57\n#define    RTL8367C_SVLAN_SP2C_ENTRY43_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY43_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY43_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY43_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY44_CTRL0    0x0f58\n#define    RTL8367C_SVLAN_SP2C_ENTRY44_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY44_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY44_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY44_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY44_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY44_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY44_CTRL1    0x0f59\n#define    RTL8367C_SVLAN_SP2C_ENTRY44_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY44_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY44_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY44_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY45_CTRL0    0x0f5a\n#define    RTL8367C_SVLAN_SP2C_ENTRY45_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY45_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY45_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY45_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY45_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY45_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY45_CTRL1    0x0f5b\n#define    RTL8367C_SVLAN_SP2C_ENTRY45_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY45_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY45_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY45_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY46_CTRL0    0x0f5c\n#define    RTL8367C_SVLAN_SP2C_ENTRY46_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY46_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY46_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY46_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY46_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY46_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY46_CTRL1    0x0f5d\n#define    RTL8367C_SVLAN_SP2C_ENTRY46_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY46_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY46_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY46_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY47_CTRL0    0x0f5e\n#define    RTL8367C_SVLAN_SP2C_ENTRY47_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY47_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY47_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY47_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY47_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY47_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY47_CTRL1    0x0f5f\n#define    RTL8367C_SVLAN_SP2C_ENTRY47_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY47_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY47_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY47_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY48_CTRL0    0x0f60\n#define    RTL8367C_SVLAN_SP2C_ENTRY48_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY48_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY48_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY48_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY48_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY48_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY48_CTRL1    0x0f61\n#define    RTL8367C_SVLAN_SP2C_ENTRY48_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY48_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY48_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY48_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY49_CTRL0    0x0f62\n#define    RTL8367C_SVLAN_SP2C_ENTRY49_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY49_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY49_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY49_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY49_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY49_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY49_CTRL1    0x0f63\n#define    RTL8367C_SVLAN_SP2C_ENTRY49_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY49_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY49_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY49_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY50_CTRL0    0x0f64\n#define    RTL8367C_SVLAN_SP2C_ENTRY50_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY50_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY50_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY50_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY50_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY50_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY50_CTRL1    0x0f65\n#define    RTL8367C_SVLAN_SP2C_ENTRY50_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY50_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY50_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY50_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY51_CTRL0    0x0f66\n#define    RTL8367C_SVLAN_SP2C_ENTRY51_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY51_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY51_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY51_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY51_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY51_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY51_CTRL1    0x0f67\n#define    RTL8367C_SVLAN_SP2C_ENTRY51_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY51_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY51_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY51_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY52_CTRL0    0x0f68\n#define    RTL8367C_SVLAN_SP2C_ENTRY52_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY52_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY52_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY52_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY52_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY52_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY52_CTRL1    0x0f69\n#define    RTL8367C_SVLAN_SP2C_ENTRY52_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY52_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY52_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY52_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY53_CTRL0    0x0f6a\n#define    RTL8367C_SVLAN_SP2C_ENTRY53_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY53_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY53_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY53_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY53_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY53_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY53_CTRL1    0x0f6b\n#define    RTL8367C_SVLAN_SP2C_ENTRY53_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY53_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY53_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY53_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY54_CTRL0    0x0f6c\n#define    RTL8367C_SVLAN_SP2C_ENTRY54_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY54_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY54_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY54_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY54_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY54_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY54_CTRL1    0x0f6d\n#define    RTL8367C_SVLAN_SP2C_ENTRY54_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY54_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY54_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY54_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY55_CTRL0    0x0f6e\n#define    RTL8367C_SVLAN_SP2C_ENTRY55_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY55_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY55_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY55_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY55_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY55_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY55_CTRL1    0x0f6f\n#define    RTL8367C_SVLAN_SP2C_ENTRY55_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY55_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY55_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY55_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY56_CTRL0    0x0f70\n#define    RTL8367C_SVLAN_SP2C_ENTRY56_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY56_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY56_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY56_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY56_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY56_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY56_CTRL1    0x0f71\n#define    RTL8367C_SVLAN_SP2C_ENTRY56_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY56_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY56_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY56_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY57_CTRL0    0x0f72\n#define    RTL8367C_SVLAN_SP2C_ENTRY57_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY57_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY57_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY57_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY57_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY57_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY57_CTRL1    0x0f73\n#define    RTL8367C_SVLAN_SP2C_ENTRY57_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY57_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY57_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY57_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY58_CTRL0    0x0f74\n#define    RTL8367C_SVLAN_SP2C_ENTRY58_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY58_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY58_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY58_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY58_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY58_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY58_CTRL1    0x0f75\n#define    RTL8367C_SVLAN_SP2C_ENTRY58_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY58_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY58_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY58_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY59_CTRL0    0x0f76\n#define    RTL8367C_SVLAN_SP2C_ENTRY59_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY59_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY59_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY59_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY59_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY59_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY59_CTRL1    0x0f77\n#define    RTL8367C_SVLAN_SP2C_ENTRY59_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY59_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY59_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY59_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY60_CTRL0    0x0f78\n#define    RTL8367C_SVLAN_SP2C_ENTRY60_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY60_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY60_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY60_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY60_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY60_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY60_CTRL1    0x0f79\n#define    RTL8367C_SVLAN_SP2C_ENTRY60_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY60_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY60_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY60_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY61_CTRL0    0x0f7a\n#define    RTL8367C_SVLAN_SP2C_ENTRY61_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY61_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY61_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY61_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY61_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY61_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY61_CTRL1    0x0f7b\n#define    RTL8367C_SVLAN_SP2C_ENTRY61_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY61_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY61_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY61_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY62_CTRL0    0x0f7c\n#define    RTL8367C_SVLAN_SP2C_ENTRY62_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY62_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY62_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY62_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY62_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY62_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY62_CTRL1    0x0f7d\n#define    RTL8367C_SVLAN_SP2C_ENTRY62_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY62_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY62_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY62_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY63_CTRL0    0x0f7e\n#define    RTL8367C_SVLAN_SP2C_ENTRY63_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY63_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY63_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY63_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY63_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY63_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY63_CTRL1    0x0f7f\n#define    RTL8367C_SVLAN_SP2C_ENTRY63_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY63_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY63_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY63_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY64_CTRL0    0x0f80\n#define    RTL8367C_SVLAN_SP2C_ENTRY64_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY64_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY64_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY64_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY64_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY64_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY64_CTRL1    0x0f81\n#define    RTL8367C_SVLAN_SP2C_ENTRY64_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY64_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY64_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY64_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY65_CTRL0    0x0f82\n#define    RTL8367C_SVLAN_SP2C_ENTRY65_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY65_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY65_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY65_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY65_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY65_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY65_CTRL1    0x0f83\n#define    RTL8367C_SVLAN_SP2C_ENTRY65_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY65_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY65_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY65_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY66_CTRL0    0x0f84\n#define    RTL8367C_SVLAN_SP2C_ENTRY66_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY66_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY66_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY66_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY66_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY66_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY66_CTRL1    0x0f85\n#define    RTL8367C_SVLAN_SP2C_ENTRY66_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY66_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY66_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY66_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY67_CTRL0    0x0f86\n#define    RTL8367C_SVLAN_SP2C_ENTRY67_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY67_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY67_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY67_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY67_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY67_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY67_CTRL1    0x0f87\n#define    RTL8367C_SVLAN_SP2C_ENTRY67_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY67_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY67_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY67_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY68_CTRL0    0x0f88\n#define    RTL8367C_SVLAN_SP2C_ENTRY68_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY68_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY68_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY68_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY68_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY68_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY68_CTRL1    0x0f89\n#define    RTL8367C_SVLAN_SP2C_ENTRY68_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY68_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY68_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY68_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY69_CTRL0    0x0f8a\n#define    RTL8367C_SVLAN_SP2C_ENTRY69_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY69_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY69_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY69_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY69_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY69_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY69_CTRL1    0x0f8b\n#define    RTL8367C_SVLAN_SP2C_ENTRY69_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY69_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY69_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY69_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY70_CTRL0    0x0f8c\n#define    RTL8367C_SVLAN_SP2C_ENTRY70_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY70_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY70_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY70_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY70_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY70_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY70_CTRL1    0x0f8d\n#define    RTL8367C_SVLAN_SP2C_ENTRY70_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY70_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY70_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY70_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY71_CTRL0    0x0f8e\n#define    RTL8367C_SVLAN_SP2C_ENTRY71_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY71_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY71_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY71_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY71_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY71_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY71_CTRL1    0x0f8f\n#define    RTL8367C_SVLAN_SP2C_ENTRY71_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY71_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY71_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY71_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY72_CTRL0    0x0f90\n#define    RTL8367C_SVLAN_SP2C_ENTRY72_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY72_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY72_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY72_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY72_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY72_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY72_CTRL1    0x0f91\n#define    RTL8367C_SVLAN_SP2C_ENTRY72_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY72_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY72_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY72_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY73_CTRL0    0x0f92\n#define    RTL8367C_SVLAN_SP2C_ENTRY73_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY73_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY73_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY73_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY73_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY73_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY73_CTRL1    0x0f93\n#define    RTL8367C_SVLAN_SP2C_ENTRY73_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY73_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY73_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY73_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY74_CTRL0    0x0f94\n#define    RTL8367C_SVLAN_SP2C_ENTRY74_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY74_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY74_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY74_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY74_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY74_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY74_CTRL1    0x0f95\n#define    RTL8367C_SVLAN_SP2C_ENTRY74_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY74_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY74_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY74_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY75_CTRL0    0x0f96\n#define    RTL8367C_SVLAN_SP2C_ENTRY75_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY75_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY75_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY75_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY75_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY75_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY75_CTRL1    0x0f97\n#define    RTL8367C_SVLAN_SP2C_ENTRY75_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY75_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY75_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY75_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY76_CTRL0    0x0f98\n#define    RTL8367C_SVLAN_SP2C_ENTRY76_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY76_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY76_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY76_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY76_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY76_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY76_CTRL1    0x0f99\n#define    RTL8367C_SVLAN_SP2C_ENTRY76_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY76_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY76_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY76_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY77_CTRL0    0x0f9a\n#define    RTL8367C_SVLAN_SP2C_ENTRY77_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY77_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY77_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY77_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY77_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY77_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY77_CTRL1    0x0f9b\n#define    RTL8367C_SVLAN_SP2C_ENTRY77_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY77_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY77_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY77_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY78_CTRL0    0x0f9c\n#define    RTL8367C_SVLAN_SP2C_ENTRY78_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY78_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY78_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY78_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY78_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY78_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY78_CTRL1    0x0f9d\n#define    RTL8367C_SVLAN_SP2C_ENTRY78_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY78_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY78_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY78_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY79_CTRL0    0x0f9e\n#define    RTL8367C_SVLAN_SP2C_ENTRY79_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY79_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY79_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY79_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY79_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY79_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY79_CTRL1    0x0f9f\n#define    RTL8367C_SVLAN_SP2C_ENTRY79_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY79_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY79_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY79_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY80_CTRL0    0x0fa0\n#define    RTL8367C_SVLAN_SP2C_ENTRY80_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY80_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY80_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY80_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY80_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY80_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY80_CTRL1    0x0fa1\n#define    RTL8367C_SVLAN_SP2C_ENTRY80_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY80_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY80_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY80_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY81_CTRL0    0x0fa2\n#define    RTL8367C_SVLAN_SP2C_ENTRY81_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY81_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY81_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY81_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY81_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY81_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY81_CTRL1    0x0fa3\n#define    RTL8367C_SVLAN_SP2C_ENTRY81_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY81_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY81_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY81_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY82_CTRL0    0x0fa4\n#define    RTL8367C_SVLAN_SP2C_ENTRY82_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY82_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY82_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY82_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY82_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY82_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY82_CTRL1    0x0fa5\n#define    RTL8367C_SVLAN_SP2C_ENTRY82_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY82_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY82_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY82_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY83_CTRL0    0x0fa6\n#define    RTL8367C_SVLAN_SP2C_ENTRY83_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY83_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY83_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY83_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY83_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY83_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY83_CTRL1    0x0fa7\n#define    RTL8367C_SVLAN_SP2C_ENTRY83_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY83_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY83_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY83_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY84_CTRL0    0x0fa8\n#define    RTL8367C_SVLAN_SP2C_ENTRY84_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY84_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY84_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY84_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY84_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY84_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY84_CTRL1    0x0fa9\n#define    RTL8367C_SVLAN_SP2C_ENTRY84_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY84_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY84_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY84_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY85_CTRL0    0x0faa\n#define    RTL8367C_SVLAN_SP2C_ENTRY85_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY85_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY85_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY85_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY85_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY85_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY85_CTRL1    0x0fab\n#define    RTL8367C_SVLAN_SP2C_ENTRY85_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY85_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY85_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY85_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY86_CTRL0    0x0fac\n#define    RTL8367C_SVLAN_SP2C_ENTRY86_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY86_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY86_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY86_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY86_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY86_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY86_CTRL1    0x0fad\n#define    RTL8367C_SVLAN_SP2C_ENTRY86_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY86_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY86_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY86_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY87_CTRL0    0x0fae\n#define    RTL8367C_SVLAN_SP2C_ENTRY87_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY87_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY87_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY87_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY87_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY87_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY87_CTRL1    0x0faf\n#define    RTL8367C_SVLAN_SP2C_ENTRY87_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY87_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY87_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY87_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY88_CTRL0    0x0fb0\n#define    RTL8367C_SVLAN_SP2C_ENTRY88_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY88_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY88_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY88_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY88_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY88_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY88_CTRL1    0x0fb1\n#define    RTL8367C_SVLAN_SP2C_ENTRY88_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY88_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY88_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY88_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY89_CTRL0    0x0fb2\n#define    RTL8367C_SVLAN_SP2C_ENTRY89_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY89_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY89_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY89_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY89_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY89_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY89_CTRL1    0x0fb3\n#define    RTL8367C_SVLAN_SP2C_ENTRY89_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY89_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY89_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY89_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY90_CTRL0    0x0fb4\n#define    RTL8367C_SVLAN_SP2C_ENTRY90_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY90_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY90_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY90_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY90_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY90_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY90_CTRL1    0x0fb5\n#define    RTL8367C_SVLAN_SP2C_ENTRY90_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY90_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY90_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY90_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY91_CTRL0    0x0fb6\n#define    RTL8367C_SVLAN_SP2C_ENTRY91_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY91_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY91_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY91_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY91_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY91_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY91_CTRL1    0x0fb7\n#define    RTL8367C_SVLAN_SP2C_ENTRY91_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY91_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY91_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY91_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY92_CTRL0    0x0fb8\n#define    RTL8367C_SVLAN_SP2C_ENTRY92_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY92_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY92_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY92_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY92_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY92_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY92_CTRL1    0x0fb9\n#define    RTL8367C_SVLAN_SP2C_ENTRY92_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY92_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY92_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY92_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY93_CTRL0    0x0fba\n#define    RTL8367C_SVLAN_SP2C_ENTRY93_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY93_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY93_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY93_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY93_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY93_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY93_CTRL1    0x0fbb\n#define    RTL8367C_SVLAN_SP2C_ENTRY93_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY93_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY93_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY93_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY94_CTRL0    0x0fbc\n#define    RTL8367C_SVLAN_SP2C_ENTRY94_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY94_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY94_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY94_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY94_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY94_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY94_CTRL1    0x0fbd\n#define    RTL8367C_SVLAN_SP2C_ENTRY94_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY94_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY94_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY94_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY95_CTRL0    0x0fbe\n#define    RTL8367C_SVLAN_SP2C_ENTRY95_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY95_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY95_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY95_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY95_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY95_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY95_CTRL1    0x0fbf\n#define    RTL8367C_SVLAN_SP2C_ENTRY95_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY95_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY95_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY95_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY96_CTRL0    0x0fc0\n#define    RTL8367C_SVLAN_SP2C_ENTRY96_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY96_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY96_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY96_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY96_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY96_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY96_CTRL1    0x0fc1\n#define    RTL8367C_SVLAN_SP2C_ENTRY96_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY96_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY96_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY96_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY97_CTRL0    0x0fc2\n#define    RTL8367C_SVLAN_SP2C_ENTRY97_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY97_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY97_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY97_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY97_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY97_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY97_CTRL1    0x0fc3\n#define    RTL8367C_SVLAN_SP2C_ENTRY97_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY97_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY97_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY97_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY98_CTRL0    0x0fc4\n#define    RTL8367C_SVLAN_SP2C_ENTRY98_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY98_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY98_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY98_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY98_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY98_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY98_CTRL1    0x0fc5\n#define    RTL8367C_SVLAN_SP2C_ENTRY98_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY98_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY98_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY98_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY99_CTRL0    0x0fc6\n#define    RTL8367C_SVLAN_SP2C_ENTRY99_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY99_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY99_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY99_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY99_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY99_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY99_CTRL1    0x0fc7\n#define    RTL8367C_SVLAN_SP2C_ENTRY99_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY99_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY99_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY99_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY100_CTRL0    0x0fc8\n#define    RTL8367C_SVLAN_SP2C_ENTRY100_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY100_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY100_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY100_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY100_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY100_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY100_CTRL1    0x0fc9\n#define    RTL8367C_SVLAN_SP2C_ENTRY100_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY100_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY100_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY100_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY101_CTRL0    0x0fca\n#define    RTL8367C_SVLAN_SP2C_ENTRY101_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY101_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY101_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY101_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY101_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY101_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY101_CTRL1    0x0fcb\n#define    RTL8367C_SVLAN_SP2C_ENTRY101_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY101_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY101_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY101_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY102_CTRL0    0x0fcc\n#define    RTL8367C_SVLAN_SP2C_ENTRY102_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY102_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY102_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY102_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY102_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY102_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY102_CTRL1    0x0fcd\n#define    RTL8367C_SVLAN_SP2C_ENTRY102_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY102_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY102_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY102_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY103_CTRL0    0x0fce\n#define    RTL8367C_SVLAN_SP2C_ENTRY103_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY103_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY103_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY103_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY103_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY103_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY103_CTRL1    0x0fcf\n#define    RTL8367C_SVLAN_SP2C_ENTRY103_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY103_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY103_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY103_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY104_CTRL0    0x0fd0\n#define    RTL8367C_SVLAN_SP2C_ENTRY104_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY104_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY104_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY104_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY104_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY104_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY104_CTRL1    0x0fd1\n#define    RTL8367C_SVLAN_SP2C_ENTRY104_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY104_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY104_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY104_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY105_CTRL0    0x0fd2\n#define    RTL8367C_SVLAN_SP2C_ENTRY105_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY105_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY105_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY105_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY105_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY105_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY105_CTRL1    0x0fd3\n#define    RTL8367C_SVLAN_SP2C_ENTRY105_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY105_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY105_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY105_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY106_CTRL0    0x0fd4\n#define    RTL8367C_SVLAN_SP2C_ENTRY106_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY106_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY106_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY106_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY106_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY106_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY106_CTRL1    0x0fd5\n#define    RTL8367C_SVLAN_SP2C_ENTRY106_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY106_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY106_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY106_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY107_CTRL0    0x0fd6\n#define    RTL8367C_SVLAN_SP2C_ENTRY107_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY107_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY107_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY107_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY107_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY107_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY107_CTRL1    0x0fd7\n#define    RTL8367C_SVLAN_SP2C_ENTRY107_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY107_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY107_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY107_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY108_CTRL0    0x0fd8\n#define    RTL8367C_SVLAN_SP2C_ENTRY108_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY108_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY108_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY108_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY108_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY108_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY108_CTRL1    0x0fd9\n#define    RTL8367C_SVLAN_SP2C_ENTRY108_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY108_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY108_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY108_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY109_CTRL0    0x0fda\n#define    RTL8367C_SVLAN_SP2C_ENTRY109_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY109_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY109_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY109_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY109_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY109_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY109_CTRL1    0x0fdb\n#define    RTL8367C_SVLAN_SP2C_ENTRY109_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY109_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY109_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY109_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY110_CTRL0    0x0fdc\n#define    RTL8367C_SVLAN_SP2C_ENTRY110_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY110_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY110_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY110_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY110_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY110_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY110_CTRL1    0x0fdd\n#define    RTL8367C_SVLAN_SP2C_ENTRY110_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY110_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY110_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY110_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY111_CTRL0    0x0fde\n#define    RTL8367C_SVLAN_SP2C_ENTRY111_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY111_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY111_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY111_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY111_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY111_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY111_CTRL1    0x0fdf\n#define    RTL8367C_SVLAN_SP2C_ENTRY111_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY111_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY111_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY111_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY112_CTRL0    0x0fe0\n#define    RTL8367C_SVLAN_SP2C_ENTRY112_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY112_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY112_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY112_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY112_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY112_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY112_CTRL1    0x0fe1\n#define    RTL8367C_SVLAN_SP2C_ENTRY112_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY112_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY112_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY112_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY113_CTRL0    0x0fe2\n#define    RTL8367C_SVLAN_SP2C_ENTRY113_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY113_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY113_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY113_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY113_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY113_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY113_CTRL1    0x0fe3\n#define    RTL8367C_SVLAN_SP2C_ENTRY113_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY113_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY113_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY113_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY114_CTRL0    0x0fe4\n#define    RTL8367C_SVLAN_SP2C_ENTRY114_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY114_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY114_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY114_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY114_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY114_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY114_CTRL1    0x0fe5\n#define    RTL8367C_SVLAN_SP2C_ENTRY114_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY114_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY114_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY114_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY115_CTRL0    0x0fe6\n#define    RTL8367C_SVLAN_SP2C_ENTRY115_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY115_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY115_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY115_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY115_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY115_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY115_CTRL1    0x0fe7\n#define    RTL8367C_SVLAN_SP2C_ENTRY115_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY115_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY115_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY115_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY116_CTRL0    0x0fe8\n#define    RTL8367C_SVLAN_SP2C_ENTRY116_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY116_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY116_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY116_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY116_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY116_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY116_CTRL1    0x0fe9\n#define    RTL8367C_SVLAN_SP2C_ENTRY116_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY116_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY116_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY116_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY117_CTRL0    0x0fea\n#define    RTL8367C_SVLAN_SP2C_ENTRY117_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY117_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY117_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY117_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY117_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY117_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY117_CTRL1    0x0feb\n#define    RTL8367C_SVLAN_SP2C_ENTRY117_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY117_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY117_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY117_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY118_CTRL0    0x0fec\n#define    RTL8367C_SVLAN_SP2C_ENTRY118_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY118_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY118_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY118_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY118_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY118_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY118_CTRL1    0x0fed\n#define    RTL8367C_SVLAN_SP2C_ENTRY118_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY118_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY118_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY118_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY119_CTRL0    0x0fee\n#define    RTL8367C_SVLAN_SP2C_ENTRY119_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY119_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY119_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY119_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY119_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY119_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY119_CTRL1    0x0fef\n#define    RTL8367C_SVLAN_SP2C_ENTRY119_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY119_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY119_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY119_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY120_CTRL0    0x0ff0\n#define    RTL8367C_SVLAN_SP2C_ENTRY120_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY120_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY120_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY120_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY120_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY120_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY120_CTRL1    0x0ff1\n#define    RTL8367C_SVLAN_SP2C_ENTRY120_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY120_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY120_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY120_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY121_CTRL0    0x0ff2\n#define    RTL8367C_SVLAN_SP2C_ENTRY121_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY121_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY121_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY121_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY121_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY121_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY121_CTRL1    0x0ff3\n#define    RTL8367C_SVLAN_SP2C_ENTRY121_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY121_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY121_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY121_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY122_CTRL0    0x0ff4\n#define    RTL8367C_SVLAN_SP2C_ENTRY122_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY122_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY122_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY122_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY122_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY122_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY122_CTRL1    0x0ff5\n#define    RTL8367C_SVLAN_SP2C_ENTRY122_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY122_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY122_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY122_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY123_CTRL0    0x0ff6\n#define    RTL8367C_SVLAN_SP2C_ENTRY123_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY123_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY123_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY123_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY123_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY123_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY123_CTRL1    0x0ff7\n#define    RTL8367C_SVLAN_SP2C_ENTRY123_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY123_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY123_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY123_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY124_CTRL0    0x0ff8\n#define    RTL8367C_SVLAN_SP2C_ENTRY124_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY124_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY124_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY124_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY124_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY124_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY124_CTRL1    0x0ff9\n#define    RTL8367C_SVLAN_SP2C_ENTRY124_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY124_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY124_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY124_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY125_CTRL0    0x0ffa\n#define    RTL8367C_SVLAN_SP2C_ENTRY125_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY125_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY125_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY125_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY125_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY125_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY125_CTRL1    0x0ffb\n#define    RTL8367C_SVLAN_SP2C_ENTRY125_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY125_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY125_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY125_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY126_CTRL0    0x0ffc\n#define    RTL8367C_SVLAN_SP2C_ENTRY126_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY126_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY126_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY126_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY126_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY126_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY126_CTRL1    0x0ffd\n#define    RTL8367C_SVLAN_SP2C_ENTRY126_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY126_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY126_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY126_CTRL1_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY127_CTRL0    0x0ffe\n#define    RTL8367C_SVLAN_SP2C_ENTRY127_CTRL0_DST_PORT1_OFFSET    9\n#define    RTL8367C_SVLAN_SP2C_ENTRY127_CTRL0_DST_PORT1_MASK    0x200\n#define    RTL8367C_SVLAN_SP2C_ENTRY127_CTRL0_SVIDX_OFFSET    3\n#define    RTL8367C_SVLAN_SP2C_ENTRY127_CTRL0_SVIDX_MASK    0x1F8\n#define    RTL8367C_SVLAN_SP2C_ENTRY127_CTRL0_DST_PORT_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY127_CTRL0_DST_PORT_MASK    0x7\n\n#define    RTL8367C_REG_SVLAN_SP2C_ENTRY127_CTRL1    0x0fff\n#define    RTL8367C_SVLAN_SP2C_ENTRY127_CTRL1_VALID_OFFSET    12\n#define    RTL8367C_SVLAN_SP2C_ENTRY127_CTRL1_VALID_MASK    0x1000\n#define    RTL8367C_SVLAN_SP2C_ENTRY127_CTRL1_VID_OFFSET    0\n#define    RTL8367C_SVLAN_SP2C_ENTRY127_CTRL1_VID_MASK    0xFFF\n\n/* (16'h1000)mib_reg */\n\n#define    RTL8367C_REG_MIB_COUNTER0    0x1000\n\n#define    RTL8367C_REG_MIB_COUNTER1    0x1001\n\n#define    RTL8367C_REG_MIB_COUNTER2    0x1002\n\n#define    RTL8367C_REG_MIB_COUNTER3    0x1003\n\n#define    RTL8367C_REG_MIB_ADDRESS    0x1004\n#define    RTL8367C_MIB_ADDRESS_OFFSET    0\n#define    RTL8367C_MIB_ADDRESS_MASK    0x1FF\n\n#define    RTL8367C_REG_MIB_CTRL0    0x1005\n#define    RTL8367C_PORT10_RESET_OFFSET    15\n#define    RTL8367C_PORT10_RESET_MASK    0x8000\n#define    RTL8367C_PORT9_RESET_OFFSET    14\n#define    RTL8367C_PORT9_RESET_MASK    0x4000\n#define    RTL8367C_PORT8_RESET_OFFSET    13\n#define    RTL8367C_PORT8_RESET_MASK    0x2000\n#define    RTL8367C_RESET_VALUE_OFFSET    12\n#define    RTL8367C_RESET_VALUE_MASK    0x1000\n#define    RTL8367C_GLOBAL_RESET_OFFSET    11\n#define    RTL8367C_GLOBAL_RESET_MASK    0x800\n#define    RTL8367C_QM_RESET_OFFSET    10\n#define    RTL8367C_QM_RESET_MASK    0x400\n#define    RTL8367C_PORT7_RESET_OFFSET    9\n#define    RTL8367C_PORT7_RESET_MASK    0x200\n#define    RTL8367C_PORT6_RESET_OFFSET    8\n#define    RTL8367C_PORT6_RESET_MASK    0x100\n#define    RTL8367C_PORT5_RESET_OFFSET    7\n#define    RTL8367C_PORT5_RESET_MASK    0x80\n#define    RTL8367C_PORT4_RESET_OFFSET    6\n#define    RTL8367C_PORT4_RESET_MASK    0x40\n#define    RTL8367C_PORT3_RESET_OFFSET    5\n#define    RTL8367C_PORT3_RESET_MASK    0x20\n#define    RTL8367C_PORT2_RESET_OFFSET    4\n#define    RTL8367C_PORT2_RESET_MASK    0x10\n#define    RTL8367C_PORT1_RESET_OFFSET    3\n#define    RTL8367C_PORT1_RESET_MASK    0x8\n#define    RTL8367C_PORT0_RESET_OFFSET    2\n#define    RTL8367C_PORT0_RESET_MASK    0x4\n#define    RTL8367C_RESET_FLAG_OFFSET    1\n#define    RTL8367C_RESET_FLAG_MASK    0x2\n#define    RTL8367C_MIB_CTRL0_BUSY_FLAG_OFFSET    0\n#define    RTL8367C_MIB_CTRL0_BUSY_FLAG_MASK    0x1\n\n#define    RTL8367C_REG_MIB_CTRL1    0x1007\n#define    RTL8367C_COUNTER15_RESET_OFFSET    15\n#define    RTL8367C_COUNTER15_RESET_MASK    0x8000\n#define    RTL8367C_COUNTER14_RESET_OFFSET    14\n#define    RTL8367C_COUNTER14_RESET_MASK    0x4000\n#define    RTL8367C_COUNTER13_RESET_OFFSET    13\n#define    RTL8367C_COUNTER13_RESET_MASK    0x2000\n#define    RTL8367C_COUNTER12_RESET_OFFSET    12\n#define    RTL8367C_COUNTER12_RESET_MASK    0x1000\n#define    RTL8367C_COUNTER11_RESET_OFFSET    11\n#define    RTL8367C_COUNTER11_RESET_MASK    0x800\n#define    RTL8367C_COUNTER10_RESET_OFFSET    10\n#define    RTL8367C_COUNTER10_RESET_MASK    0x400\n#define    RTL8367C_COUNTER9_RESET_OFFSET    9\n#define    RTL8367C_COUNTER9_RESET_MASK    0x200\n#define    RTL8367C_COUNTER8_RESET_OFFSET    8\n#define    RTL8367C_COUNTER8_RESET_MASK    0x100\n#define    RTL8367C_COUNTER7_RESET_OFFSET    7\n#define    RTL8367C_COUNTER7_RESET_MASK    0x80\n#define    RTL8367C_COUNTER6_RESET_OFFSET    6\n#define    RTL8367C_COUNTER6_RESET_MASK    0x40\n#define    RTL8367C_COUNTER5_RESET_OFFSET    5\n#define    RTL8367C_COUNTER5_RESET_MASK    0x20\n#define    RTL8367C_COUNTER4_RESET_OFFSET    4\n#define    RTL8367C_COUNTER4_RESET_MASK    0x10\n#define    RTL8367C_COUNTER3_RESET_OFFSET    3\n#define    RTL8367C_COUNTER3_RESET_MASK    0x8\n#define    RTL8367C_COUNTER2_RESET_OFFSET    2\n#define    RTL8367C_COUNTER2_RESET_MASK    0x4\n#define    RTL8367C_COUNTER1_RESET_OFFSET    1\n#define    RTL8367C_COUNTER1_RESET_MASK    0x2\n#define    RTL8367C_COUNTER0_RESET_OFFSET    0\n#define    RTL8367C_COUNTER0_RESET_MASK    0x1\n\n#define    RTL8367C_REG_MIB_CTRL2    0x1008\n#define    RTL8367C_COUNTER31_RESET_OFFSET    15\n#define    RTL8367C_COUNTER31_RESET_MASK    0x8000\n#define    RTL8367C_COUNTER30_RESET_OFFSET    14\n#define    RTL8367C_COUNTER30_RESET_MASK    0x4000\n#define    RTL8367C_COUNTER29_RESET_OFFSET    13\n#define    RTL8367C_COUNTER29_RESET_MASK    0x2000\n#define    RTL8367C_COUNTER28_RESET_OFFSET    12\n#define    RTL8367C_COUNTER28_RESET_MASK    0x1000\n#define    RTL8367C_COUNTER27_RESET_OFFSET    11\n#define    RTL8367C_COUNTER27_RESET_MASK    0x800\n#define    RTL8367C_COUNTER26_RESET_OFFSET    10\n#define    RTL8367C_COUNTER26_RESET_MASK    0x400\n#define    RTL8367C_COUNTER25_RESET_OFFSET    9\n#define    RTL8367C_COUNTER25_RESET_MASK    0x200\n#define    RTL8367C_COUNTER24_RESET_OFFSET    8\n#define    RTL8367C_COUNTER24_RESET_MASK    0x100\n#define    RTL8367C_COUNTER23_RESET_OFFSET    7\n#define    RTL8367C_COUNTER23_RESET_MASK    0x80\n#define    RTL8367C_COUNTER22_RESET_OFFSET    6\n#define    RTL8367C_COUNTER22_RESET_MASK    0x40\n#define    RTL8367C_COUNTER21_RESET_OFFSET    5\n#define    RTL8367C_COUNTER21_RESET_MASK    0x20\n#define    RTL8367C_COUNTER20_RESET_OFFSET    4\n#define    RTL8367C_COUNTER20_RESET_MASK    0x10\n#define    RTL8367C_COUNTER19_RESET_OFFSET    3\n#define    RTL8367C_COUNTER19_RESET_MASK    0x8\n#define    RTL8367C_COUNTER18_RESET_OFFSET    2\n#define    RTL8367C_COUNTER18_RESET_MASK    0x4\n#define    RTL8367C_COUNTER17_RESET_OFFSET    1\n#define    RTL8367C_COUNTER17_RESET_MASK    0x2\n#define    RTL8367C_COUNTER16_RESET_OFFSET    0\n#define    RTL8367C_COUNTER16_RESET_MASK    0x1\n\n#define    RTL8367C_REG_MIB_CTRL3    0x1009\n#define    RTL8367C_COUNTER15_MODE_OFFSET    15\n#define    RTL8367C_COUNTER15_MODE_MASK    0x8000\n#define    RTL8367C_COUNTER14_MODE_OFFSET    14\n#define    RTL8367C_COUNTER14_MODE_MASK    0x4000\n#define    RTL8367C_COUNTER13_MODE_OFFSET    13\n#define    RTL8367C_COUNTER13_MODE_MASK    0x2000\n#define    RTL8367C_COUNTER12_MODE_OFFSET    12\n#define    RTL8367C_COUNTER12_MODE_MASK    0x1000\n#define    RTL8367C_COUNTER11_MODE_OFFSET    11\n#define    RTL8367C_COUNTER11_MODE_MASK    0x800\n#define    RTL8367C_COUNTER10_MODE_OFFSET    10\n#define    RTL8367C_COUNTER10_MODE_MASK    0x400\n#define    RTL8367C_COUNTER9_MODE_OFFSET    9\n#define    RTL8367C_COUNTER9_MODE_MASK    0x200\n#define    RTL8367C_COUNTER8_MODE_OFFSET    8\n#define    RTL8367C_COUNTER8_MODE_MASK    0x100\n#define    RTL8367C_COUNTER7_MODE_OFFSET    7\n#define    RTL8367C_COUNTER7_MODE_MASK    0x80\n#define    RTL8367C_COUNTER6_MODE_OFFSET    6\n#define    RTL8367C_COUNTER6_MODE_MASK    0x40\n#define    RTL8367C_COUNTER5_MODE_OFFSET    5\n#define    RTL8367C_COUNTER5_MODE_MASK    0x20\n#define    RTL8367C_COUNTER4_MODE_OFFSET    4\n#define    RTL8367C_COUNTER4_MODE_MASK    0x10\n#define    RTL8367C_COUNTER3_MODE_OFFSET    3\n#define    RTL8367C_COUNTER3_MODE_MASK    0x8\n#define    RTL8367C_COUNTER2_MODE_OFFSET    2\n#define    RTL8367C_COUNTER2_MODE_MASK    0x4\n#define    RTL8367C_COUNTER1_MODE_OFFSET    1\n#define    RTL8367C_COUNTER1_MODE_MASK    0x2\n#define    RTL8367C_COUNTER0_MODE_OFFSET    0\n#define    RTL8367C_COUNTER0_MODE_MASK    0x1\n\n#define    RTL8367C_REG_MIB_CTRL4    0x100a\n#define    RTL8367C_MIB_USAGE_MODE_OFFSET    8\n#define    RTL8367C_MIB_USAGE_MODE_MASK    0x100\n#define    RTL8367C_MIB_TIMER_OFFSET    0\n#define    RTL8367C_MIB_TIMER_MASK    0xFF\n\n#define    RTL8367C_REG_MIB_CTRL5    0x100b\n#define    RTL8367C_MIB_CTRL5_COUNTER15_TYPE_OFFSET    15\n#define    RTL8367C_MIB_CTRL5_COUNTER15_TYPE_MASK    0x8000\n#define    RTL8367C_MIB_CTRL5_COUNTER14_TYPE_OFFSET    14\n#define    RTL8367C_MIB_CTRL5_COUNTER14_TYPE_MASK    0x4000\n#define    RTL8367C_MIB_CTRL5_COUNTER13_TYPE_OFFSET    13\n#define    RTL8367C_MIB_CTRL5_COUNTER13_TYPE_MASK    0x2000\n#define    RTL8367C_MIB_CTRL5_COUNTER12_TYPE_OFFSET    12\n#define    RTL8367C_MIB_CTRL5_COUNTER12_TYPE_MASK    0x1000\n#define    RTL8367C_MIB_CTRL5_COUNTER11_TYPE_OFFSET    11\n#define    RTL8367C_MIB_CTRL5_COUNTER11_TYPE_MASK    0x800\n#define    RTL8367C_MIB_CTRL5_COUNTER10_TYPE_OFFSET    10\n#define    RTL8367C_MIB_CTRL5_COUNTER10_TYPE_MASK    0x400\n#define    RTL8367C_MIB_CTRL5_COUNTER9_TYPE_OFFSET    9\n#define    RTL8367C_MIB_CTRL5_COUNTER9_TYPE_MASK    0x200\n#define    RTL8367C_MIB_CTRL5_COUNTER8_TYPE_OFFSET    8\n#define    RTL8367C_MIB_CTRL5_COUNTER8_TYPE_MASK    0x100\n#define    RTL8367C_MIB_CTRL5_COUNTER7_TYPE_OFFSET    7\n#define    RTL8367C_MIB_CTRL5_COUNTER7_TYPE_MASK    0x80\n#define    RTL8367C_MIB_CTRL5_COUNTER6_TYPE_OFFSET    6\n#define    RTL8367C_MIB_CTRL5_COUNTER6_TYPE_MASK    0x40\n#define    RTL8367C_MIB_CTRL5_COUNTER5_TYPE_OFFSET    5\n#define    RTL8367C_MIB_CTRL5_COUNTER5_TYPE_MASK    0x20\n#define    RTL8367C_MIB_CTRL5_COUNTER4_TYPE_OFFSET    4\n#define    RTL8367C_MIB_CTRL5_COUNTER4_TYPE_MASK    0x10\n#define    RTL8367C_MIB_CTRL5_COUNTER3_TYPE_OFFSET    3\n#define    RTL8367C_MIB_CTRL5_COUNTER3_TYPE_MASK    0x8\n#define    RTL8367C_MIB_CTRL5_COUNTER2_TYPE_OFFSET    2\n#define    RTL8367C_MIB_CTRL5_COUNTER2_TYPE_MASK    0x4\n#define    RTL8367C_MIB_CTRL5_COUNTER1_TYPE_OFFSET    1\n#define    RTL8367C_MIB_CTRL5_COUNTER1_TYPE_MASK    0x2\n#define    RTL8367C_MIB_CTRL5_COUNTER0_TYPE_OFFSET    0\n#define    RTL8367C_MIB_CTRL5_COUNTER0_TYPE_MASK    0x1\n\n/* (16'h1100)intrpt_reg */\n\n#define    RTL8367C_REG_INTR_CTRL    0x1100\n#define    RTL8367C_INTR_CTRL_OFFSET    0\n#define    RTL8367C_INTR_CTRL_MASK    0x1\n\n#define    RTL8367C_REG_INTR_IMR    0x1101\n#define    RTL8367C_INTR_IMR_SLIENT_START_2_OFFSET    12\n#define    RTL8367C_INTR_IMR_SLIENT_START_2_MASK    0x1000\n#define    RTL8367C_INTR_IMR_SLIENT_START_OFFSET    11\n#define    RTL8367C_INTR_IMR_SLIENT_START_MASK    0x800\n#define    RTL8367C_INTR_IMR_ACL_ACTION_OFFSET    9\n#define    RTL8367C_INTR_IMR_ACL_ACTION_MASK    0x200\n#define    RTL8367C_INTR_IMR_CABLE_DIAG_FIN_OFFSET    8\n#define    RTL8367C_INTR_IMR_CABLE_DIAG_FIN_MASK    0x100\n#define    RTL8367C_INTR_IMR_INTERRUPT_8051_OFFSET    7\n#define    RTL8367C_INTR_IMR_INTERRUPT_8051_MASK    0x80\n#define    RTL8367C_INTR_IMR_LOOP_DETECTION_OFFSET    6\n#define    RTL8367C_INTR_IMR_LOOP_DETECTION_MASK    0x40\n#define    RTL8367C_INTR_IMR_GREEN_TIMER_OFFSET    5\n#define    RTL8367C_INTR_IMR_GREEN_TIMER_MASK    0x20\n#define    RTL8367C_INTR_IMR_SPECIAL_CONGEST_OFFSET    4\n#define    RTL8367C_INTR_IMR_SPECIAL_CONGEST_MASK    0x10\n#define    RTL8367C_INTR_IMR_SPEED_CHANGE_OFFSET    3\n#define    RTL8367C_INTR_IMR_SPEED_CHANGE_MASK    0x8\n#define    RTL8367C_INTR_IMR_LEARN_OVER_OFFSET    2\n#define    RTL8367C_INTR_IMR_LEARN_OVER_MASK    0x4\n#define    RTL8367C_INTR_IMR_METER_EXCEEDED_OFFSET    1\n#define    RTL8367C_INTR_IMR_METER_EXCEEDED_MASK    0x2\n#define    RTL8367C_INTR_IMR_LINK_CHANGE_OFFSET    0\n#define    RTL8367C_INTR_IMR_LINK_CHANGE_MASK    0x1\n\n#define    RTL8367C_REG_INTR_IMS    0x1102\n#define    RTL8367C_INTR_IMS_SLIENT_START_2_OFFSET    12\n#define    RTL8367C_INTR_IMS_SLIENT_START_2_MASK    0x1000\n#define    RTL8367C_INTR_IMS_SLIENT_START_OFFSET    11\n#define    RTL8367C_INTR_IMS_SLIENT_START_MASK    0x800\n#define    RTL8367C_INTR_IMS_ACL_ACTION_OFFSET    9\n#define    RTL8367C_INTR_IMS_ACL_ACTION_MASK    0x200\n#define    RTL8367C_INTR_IMS_CABLE_DIAG_FIN_OFFSET    8\n#define    RTL8367C_INTR_IMS_CABLE_DIAG_FIN_MASK    0x100\n#define    RTL8367C_INTR_IMS_INTERRUPT_8051_OFFSET    7\n#define    RTL8367C_INTR_IMS_INTERRUPT_8051_MASK    0x80\n#define    RTL8367C_INTR_IMS_LOOP_DETECTION_OFFSET    6\n#define    RTL8367C_INTR_IMS_LOOP_DETECTION_MASK    0x40\n#define    RTL8367C_INTR_IMS_GREEN_TIMER_OFFSET    5\n#define    RTL8367C_INTR_IMS_GREEN_TIMER_MASK    0x20\n#define    RTL8367C_INTR_IMS_SPECIAL_CONGEST_OFFSET    4\n#define    RTL8367C_INTR_IMS_SPECIAL_CONGEST_MASK    0x10\n#define    RTL8367C_INTR_IMS_SPEED_CHANGE_OFFSET    3\n#define    RTL8367C_INTR_IMS_SPEED_CHANGE_MASK    0x8\n#define    RTL8367C_INTR_IMS_LEARN_OVER_OFFSET    2\n#define    RTL8367C_INTR_IMS_LEARN_OVER_MASK    0x4\n#define    RTL8367C_INTR_IMS_METER_EXCEEDED_OFFSET    1\n#define    RTL8367C_INTR_IMS_METER_EXCEEDED_MASK    0x2\n#define    RTL8367C_INTR_IMS_LINK_CHANGE_OFFSET    0\n#define    RTL8367C_INTR_IMS_LINK_CHANGE_MASK    0x1\n\n#define    RTL8367C_REG_LEARN_OVER_INDICATOR    0x1103\n#define    RTL8367C_LEARN_OVER_INDICATOR_OFFSET    0\n#define    RTL8367C_LEARN_OVER_INDICATOR_MASK    0x7FF\n\n#define    RTL8367C_REG_SPEED_CHANGE_INDICATOR    0x1104\n#define    RTL8367C_SPEED_CHANGE_INDICATOR_OFFSET    0\n#define    RTL8367C_SPEED_CHANGE_INDICATOR_MASK    0x7FF\n\n#define    RTL8367C_REG_SPECIAL_CONGEST_INDICATOR    0x1105\n#define    RTL8367C_SPECIAL_CONGEST_INDICATOR_OFFSET    0\n#define    RTL8367C_SPECIAL_CONGEST_INDICATOR_MASK    0x7FF\n\n#define    RTL8367C_REG_PORT_LINKDOWN_INDICATOR    0x1106\n#define    RTL8367C_PORT_LINKDOWN_INDICATOR_OFFSET    0\n#define    RTL8367C_PORT_LINKDOWN_INDICATOR_MASK    0x7FF\n\n#define    RTL8367C_REG_PORT_LINKUP_INDICATOR    0x1107\n#define    RTL8367C_PORT_LINKUP_INDICATOR_OFFSET    0\n#define    RTL8367C_PORT_LINKUP_INDICATOR_MASK    0x7FF\n\n#define    RTL8367C_REG_SYSTEM_LEARN_OVER_INDICATOR    0x1108\n#define    RTL8367C_SYSTEM_LEARN_OVER_INDICATOR_OFFSET    0\n#define    RTL8367C_SYSTEM_LEARN_OVER_INDICATOR_MASK    0x1\n\n#define    RTL8367C_REG_INTR_IMR_8051    0x1118\n#define    RTL8367C_INTR_IMR_8051_SLIENT_START_2_OFFSET    13\n#define    RTL8367C_INTR_IMR_8051_SLIENT_START_2_MASK    0x2000\n#define    RTL8367C_INTR_IMR_8051_SLIENT_START_OFFSET    12\n#define    RTL8367C_INTR_IMR_8051_SLIENT_START_MASK    0x1000\n#define    RTL8367C_INTR_IMR_8051_ACL_ACTION_OFFSET    10\n#define    RTL8367C_INTR_IMR_8051_ACL_ACTION_MASK    0x400\n#define    RTL8367C_INTR_IMR_8051_SAMOVING_8051_OFFSET    9\n#define    RTL8367C_INTR_IMR_8051_SAMOVING_8051_MASK    0x200\n#define    RTL8367C_INTR_IMR_8051_CABLE_DIAG_FIN_8051_OFFSET    8\n#define    RTL8367C_INTR_IMR_8051_CABLE_DIAG_FIN_8051_MASK    0x100\n#define    RTL8367C_INTR_IMR_8051_EEELLDP_8051_OFFSET    7\n#define    RTL8367C_INTR_IMR_8051_EEELLDP_8051_MASK    0x80\n#define    RTL8367C_INTR_IMR_8051_LOOP_DETECTION_8051_OFFSET    6\n#define    RTL8367C_INTR_IMR_8051_LOOP_DETECTION_8051_MASK    0x40\n#define    RTL8367C_INTR_IMR_8051_GREEN_TIMER_8051_OFFSET    5\n#define    RTL8367C_INTR_IMR_8051_GREEN_TIMER_8051_MASK    0x20\n#define    RTL8367C_INTR_IMR_8051_SPECIAL_CONGEST_8051_OFFSET    4\n#define    RTL8367C_INTR_IMR_8051_SPECIAL_CONGEST_8051_MASK    0x10\n#define    RTL8367C_INTR_IMR_8051_SPEED_CHANGE_8051_OFFSET    3\n#define    RTL8367C_INTR_IMR_8051_SPEED_CHANGE_8051_MASK    0x8\n#define    RTL8367C_INTR_IMR_8051_LEARN_OVER_8051_OFFSET    2\n#define    RTL8367C_INTR_IMR_8051_LEARN_OVER_8051_MASK    0x4\n#define    RTL8367C_INTR_IMR_8051_METER_EXCEEDED_8051_OFFSET    1\n#define    RTL8367C_INTR_IMR_8051_METER_EXCEEDED_8051_MASK    0x2\n#define    RTL8367C_INTR_IMR_8051_LINK_CHANGE_8051_OFFSET    0\n#define    RTL8367C_INTR_IMR_8051_LINK_CHANGE_8051_MASK    0x1\n\n#define    RTL8367C_REG_INTR_IMS_8051    0x1119\n#define    RTL8367C_INTR_IMS_8051_SLIENT_START_2_OFFSET    13\n#define    RTL8367C_INTR_IMS_8051_SLIENT_START_2_MASK    0x2000\n#define    RTL8367C_INTR_IMS_8051_SLIENT_START_OFFSET    12\n#define    RTL8367C_INTR_IMS_8051_SLIENT_START_MASK    0x1000\n#define    RTL8367C_INTR_IMS_8051_ACL_ACTION_OFFSET    10\n#define    RTL8367C_INTR_IMS_8051_ACL_ACTION_MASK    0x400\n#define    RTL8367C_INTR_IMS_8051_SAMOVING_8051_OFFSET    9\n#define    RTL8367C_INTR_IMS_8051_SAMOVING_8051_MASK    0x200\n#define    RTL8367C_INTR_IMS_8051_CABLE_DIAG_FIN_8051_OFFSET    8\n#define    RTL8367C_INTR_IMS_8051_CABLE_DIAG_FIN_8051_MASK    0x100\n#define    RTL8367C_INTR_IMS_8051_EEELLDP_8051_OFFSET    7\n#define    RTL8367C_INTR_IMS_8051_EEELLDP_8051_MASK    0x80\n#define    RTL8367C_INTR_IMS_8051_LOOP_DETECTION_8051_OFFSET    6\n#define    RTL8367C_INTR_IMS_8051_LOOP_DETECTION_8051_MASK    0x40\n#define    RTL8367C_INTR_IMS_8051_GREEN_TIMER_8051_OFFSET    5\n#define    RTL8367C_INTR_IMS_8051_GREEN_TIMER_8051_MASK    0x20\n#define    RTL8367C_INTR_IMS_8051_SPECIAL_CONGEST_8051_OFFSET    4\n#define    RTL8367C_INTR_IMS_8051_SPECIAL_CONGEST_8051_MASK    0x10\n#define    RTL8367C_INTR_IMS_8051_SPEED_CHANGE_8051_OFFSET    3\n#define    RTL8367C_INTR_IMS_8051_SPEED_CHANGE_8051_MASK    0x8\n#define    RTL8367C_INTR_IMS_8051_LEARN_OVER_8051_OFFSET    2\n#define    RTL8367C_INTR_IMS_8051_LEARN_OVER_8051_MASK    0x4\n#define    RTL8367C_INTR_IMS_8051_METER_EXCEEDED_8051_OFFSET    1\n#define    RTL8367C_INTR_IMS_8051_METER_EXCEEDED_8051_MASK    0x2\n#define    RTL8367C_INTR_IMS_8051_LINK_CHANGE_8051_OFFSET    0\n#define    RTL8367C_INTR_IMS_8051_LINK_CHANGE_8051_MASK    0x1\n\n#define    RTL8367C_REG_DW8051_INT_CPU    0x111a\n#define    RTL8367C_DW8051_INT_CPU_OFFSET    0\n#define    RTL8367C_DW8051_INT_CPU_MASK    0x1\n\n#define    RTL8367C_REG_LEARN_OVER_INDICATOR_8051    0x1120\n#define    RTL8367C_LEARN_OVER_INDICATOR_8051_OFFSET    0\n#define    RTL8367C_LEARN_OVER_INDICATOR_8051_MASK    0x7FF\n\n#define    RTL8367C_REG_SPEED_CHANGE_INDICATOR_8051    0x1121\n#define    RTL8367C_SPEED_CHANGE_INDICATOR_8051_OFFSET    0\n#define    RTL8367C_SPEED_CHANGE_INDICATOR_8051_MASK    0x7FF\n\n#define    RTL8367C_REG_SPECIAL_CONGEST_INDICATOR_8051    0x1122\n#define    RTL8367C_SPECIAL_CONGEST_INDICATOR_8051_OFFSET    0\n#define    RTL8367C_SPECIAL_CONGEST_INDICATOR_8051_MASK    0x7FF\n\n#define    RTL8367C_REG_PORT_LINKDOWN_INDICATOR_8051    0x1123\n#define    RTL8367C_PORT_LINKDOWN_INDICATOR_8051_OFFSET    0\n#define    RTL8367C_PORT_LINKDOWN_INDICATOR_8051_MASK    0x7FF\n\n#define    RTL8367C_REG_PORT_LINKUP_INDICATOR_8051    0x1124\n#define    RTL8367C_PORT_LINKUP_INDICATOR_8051_OFFSET    0\n#define    RTL8367C_PORT_LINKUP_INDICATOR_8051_MASK    0x7FF\n\n#define    RTL8367C_REG_DUMMY_1125    0x1125\n\n#define    RTL8367C_REG_DUMMY_1126    0x1126\n\n#define    RTL8367C_REG_DUMMY_1127    0x1127\n\n#define    RTL8367C_REG_DUMMY_1128    0x1128\n\n#define    RTL8367C_REG_DUMMY_1129    0x1129\n\n#define    RTL8367C_REG_INTR_IMS_BUFFER_RESET    0x112a\n#define    RTL8367C_INTR_IMS_BUFFER_RESET_IMR_BUFF_RESET_OFFSET    1\n#define    RTL8367C_INTR_IMS_BUFFER_RESET_IMR_BUFF_RESET_MASK    0x2\n#define    RTL8367C_INTR_IMS_BUFFER_RESET_BUFFER_RESET_OFFSET    0\n#define    RTL8367C_INTR_IMS_BUFFER_RESET_BUFFER_RESET_MASK    0x1\n\n#define    RTL8367C_REG_INTR_IMS_8051_BUFFER_RESET    0x112b\n#define    RTL8367C_INTR_IMS_8051_BUFFER_RESET_IMR_BUFF_RESET_OFFSET    1\n#define    RTL8367C_INTR_IMS_8051_BUFFER_RESET_IMR_BUFF_RESET_MASK    0x2\n#define    RTL8367C_INTR_IMS_8051_BUFFER_RESET_BUFFER_RESET_OFFSET    0\n#define    RTL8367C_INTR_IMS_8051_BUFFER_RESET_BUFFER_RESET_MASK    0x1\n\n#define    RTL8367C_REG_GPHY_INTRPT_8051    0x112c\n#define    RTL8367C_IMS_GPHY_8051_H_OFFSET    13\n#define    RTL8367C_IMS_GPHY_8051_H_MASK    0xE000\n#define    RTL8367C_IMR_GPHY_8051_H_OFFSET    10\n#define    RTL8367C_IMR_GPHY_8051_H_MASK    0x1C00\n#define    RTL8367C_IMS_GPHY_8051_OFFSET    5\n#define    RTL8367C_IMS_GPHY_8051_MASK    0x3E0\n#define    RTL8367C_IMR_GPHY_8051_OFFSET    0\n#define    RTL8367C_IMR_GPHY_8051_MASK    0x1F\n\n#define    RTL8367C_REG_GPHY_INTRPT    0x112d\n#define    RTL8367C_IMS_GPHY_H_OFFSET    13\n#define    RTL8367C_IMS_GPHY_H_MASK    0xE000\n#define    RTL8367C_IMR_GPHY_H_OFFSET    10\n#define    RTL8367C_IMR_GPHY_H_MASK    0x1C00\n#define    RTL8367C_IMS_GPHY_OFFSET    5\n#define    RTL8367C_IMS_GPHY_MASK    0x3E0\n#define    RTL8367C_IMR_GPHY_OFFSET    0\n#define    RTL8367C_IMR_GPHY_MASK    0x1F\n\n#define    RTL8367C_REG_THERMAL_INTRPT    0x112e\n#define    RTL8367C_IMS_TM_HIGH_OFFSET    3\n#define    RTL8367C_IMS_TM_HIGH_MASK    0x8\n#define    RTL8367C_IMR_TM_HIGH_OFFSET    2\n#define    RTL8367C_IMR_TM_HIGH_MASK    0x4\n#define    RTL8367C_IMS_TM_LOW_OFFSET    1\n#define    RTL8367C_IMS_TM_LOW_MASK    0x2\n#define    RTL8367C_IMR_TM_LOW_OFFSET    0\n#define    RTL8367C_IMR_TM_LOW_MASK    0x1\n\n#define    RTL8367C_REG_THERMAL_INTRPT_8051    0x112f\n#define    RTL8367C_IMS_TM_HIGH_8051_OFFSET    3\n#define    RTL8367C_IMS_TM_HIGH_8051_MASK    0x8\n#define    RTL8367C_IMR_TM_HIGH_8051_OFFSET    2\n#define    RTL8367C_IMR_TM_HIGH_8051_MASK    0x4\n#define    RTL8367C_IMS_TM_LOW_8051_OFFSET    1\n#define    RTL8367C_IMS_TM_LOW_8051_MASK    0x2\n#define    RTL8367C_IMR_TM_LOW_8051_OFFSET    0\n#define    RTL8367C_IMR_TM_LOW_8051_MASK    0x1\n\n#define    RTL8367C_REG_SDS_LINK_CHG_INT    0x1130\n#define    RTL8367C_IMS_SDS_LINK_STS_C7_OFFSET    15\n#define    RTL8367C_IMS_SDS_LINK_STS_C7_MASK    0x8000\n#define    RTL8367C_IMS_SDS_LINK_STS_C6_OFFSET    14\n#define    RTL8367C_IMS_SDS_LINK_STS_C6_MASK    0x4000\n#define    RTL8367C_IMS_SDS_LINK_STS_C5_OFFSET    13\n#define    RTL8367C_IMS_SDS_LINK_STS_C5_MASK    0x2000\n#define    RTL8367C_IMS_SDS_LINK_STS_C4_OFFSET    12\n#define    RTL8367C_IMS_SDS_LINK_STS_C4_MASK    0x1000\n#define    RTL8367C_IMS_SDS_LINK_STS_C3_OFFSET    11\n#define    RTL8367C_IMS_SDS_LINK_STS_C3_MASK    0x800\n#define    RTL8367C_IMS_SDS_LINK_STS_C2_OFFSET    10\n#define    RTL8367C_IMS_SDS_LINK_STS_C2_MASK    0x400\n#define    RTL8367C_IMS_SDS_LINK_STS_C1_OFFSET    9\n#define    RTL8367C_IMS_SDS_LINK_STS_C1_MASK    0x200\n#define    RTL8367C_IMS_SDS_LINK_STS_C0_OFFSET    8\n#define    RTL8367C_IMS_SDS_LINK_STS_C0_MASK    0x100\n#define    RTL8367C_IMR_SDS_LINK_STS_C7_OFFSET    7\n#define    RTL8367C_IMR_SDS_LINK_STS_C7_MASK    0x80\n#define    RTL8367C_IMR_SDS_LINK_STS_C6_OFFSET    6\n#define    RTL8367C_IMR_SDS_LINK_STS_C6_MASK    0x40\n#define    RTL8367C_IMR_SDS_LINK_STS_C5_OFFSET    5\n#define    RTL8367C_IMR_SDS_LINK_STS_C5_MASK    0x20\n#define    RTL8367C_IMR_SDS_LINK_STS_C4_OFFSET    4\n#define    RTL8367C_IMR_SDS_LINK_STS_C4_MASK    0x10\n#define    RTL8367C_IMR_SDS_LINK_STS_C3_OFFSET    3\n#define    RTL8367C_IMR_SDS_LINK_STS_C3_MASK    0x8\n#define    RTL8367C_IMR_SDS_LINK_STS_C2_OFFSET    2\n#define    RTL8367C_IMR_SDS_LINK_STS_C2_MASK    0x4\n#define    RTL8367C_IMR_SDS_LINK_STS_C1_OFFSET    1\n#define    RTL8367C_IMR_SDS_LINK_STS_C1_MASK    0x2\n#define    RTL8367C_IMR_SDS_LINK_STS_C0_OFFSET    0\n#define    RTL8367C_IMR_SDS_LINK_STS_C0_MASK    0x1\n\n#define    RTL8367C_REG_SDS_LINK_CHG_INT_8051    0x1131\n#define    RTL8367C_IMS_SDS_LINK_STS_C7_8051_OFFSET    15\n#define    RTL8367C_IMS_SDS_LINK_STS_C7_8051_MASK    0x8000\n#define    RTL8367C_IMS_SDS_LINK_STS_C6_8051_OFFSET    14\n#define    RTL8367C_IMS_SDS_LINK_STS_C6_8051_MASK    0x4000\n#define    RTL8367C_IMS_SDS_LINK_STS_C5_8051_OFFSET    13\n#define    RTL8367C_IMS_SDS_LINK_STS_C5_8051_MASK    0x2000\n#define    RTL8367C_IMS_SDS_LINK_STS_C4_8051_OFFSET    12\n#define    RTL8367C_IMS_SDS_LINK_STS_C4_8051_MASK    0x1000\n#define    RTL8367C_IMS_SDS_LINK_STS_C3_8051_OFFSET    11\n#define    RTL8367C_IMS_SDS_LINK_STS_C3_8051_MASK    0x800\n#define    RTL8367C_IMS_SDS_LINK_STS_C2_8051_OFFSET    10\n#define    RTL8367C_IMS_SDS_LINK_STS_C2_8051_MASK    0x400\n#define    RTL8367C_IMS_SDS_LINK_STS_C1_8051_OFFSET    9\n#define    RTL8367C_IMS_SDS_LINK_STS_C1_8051_MASK    0x200\n#define    RTL8367C_IMS_SDS_LINK_STS_C0_8051_OFFSET    8\n#define    RTL8367C_IMS_SDS_LINK_STS_C0_8051_MASK    0x100\n#define    RTL8367C_IMR_SDS_LINK_STS_C7_8051_OFFSET    7\n#define    RTL8367C_IMR_SDS_LINK_STS_C7_8051_MASK    0x80\n#define    RTL8367C_IMR_SDS_LINK_STS_C6_8051_OFFSET    6\n#define    RTL8367C_IMR_SDS_LINK_STS_C6_8051_MASK    0x40\n#define    RTL8367C_IMR_SDS_LINK_STS_C5_8051_OFFSET    5\n#define    RTL8367C_IMR_SDS_LINK_STS_C5_8051_MASK    0x20\n#define    RTL8367C_IMR_SDS_LINK_STS_C4_8051_OFFSET    4\n#define    RTL8367C_IMR_SDS_LINK_STS_C4_8051_MASK    0x10\n#define    RTL8367C_IMR_SDS_LINK_STS_C3_8051_OFFSET    3\n#define    RTL8367C_IMR_SDS_LINK_STS_C3_8051_MASK    0x8\n#define    RTL8367C_IMR_SDS_LINK_STS_C2_8051_OFFSET    2\n#define    RTL8367C_IMR_SDS_LINK_STS_C2_8051_MASK    0x4\n#define    RTL8367C_IMR_SDS_LINK_STS_C1_8051_OFFSET    1\n#define    RTL8367C_IMR_SDS_LINK_STS_C1_8051_MASK    0x2\n#define    RTL8367C_IMR_SDS_LINK_STS_C0_8051_OFFSET    0\n#define    RTL8367C_IMR_SDS_LINK_STS_C0_8051_MASK    0x1\n\n/* (16'h1200)swcore_reg */\n\n#define    RTL8367C_REG_MAX_LENGTH_LIMINT_IPG    0x1200\n#define    RTL8367C_MAX_LENTH_CTRL_OFFSET    13\n#define    RTL8367C_MAX_LENTH_CTRL_MASK    0x6000\n#define    RTL8367C_PAGES_BEFORE_FCDROP_OFFSET    6\n#define    RTL8367C_PAGES_BEFORE_FCDROP_MASK    0x1FC0\n#define    RTL8367C_CHECK_MIN_IPG_RXDV_OFFSET    5\n#define    RTL8367C_CHECK_MIN_IPG_RXDV_MASK    0x20\n#define    RTL8367C_LIMIT_IPG_CFG_OFFSET    0\n#define    RTL8367C_LIMIT_IPG_CFG_MASK    0x1F\n\n#define    RTL8367C_REG_IOL_RXDROP_CFG    0x1201\n#define    RTL8367C_RX_IOL_MAX_LENGTH_CFG_OFFSET    13\n#define    RTL8367C_RX_IOL_MAX_LENGTH_CFG_MASK    0x2000\n#define    RTL8367C_RX_IOL_ERROR_LENGTH_CFG_OFFSET    12\n#define    RTL8367C_RX_IOL_ERROR_LENGTH_CFG_MASK    0x1000\n#define    RTL8367C_RX_NODROP_PAUSE_CFG_OFFSET    8\n#define    RTL8367C_RX_NODROP_PAUSE_CFG_MASK    0x100\n#define    RTL8367C_RX_DV_CNT_CFG_OFFSET    0\n#define    RTL8367C_RX_DV_CNT_CFG_MASK    0x3F\n\n#define    RTL8367C_REG_VS_TPID    0x1202\n\n#define    RTL8367C_REG_INBW_BOUND    0x1203\n#define    RTL8367C_LBOUND_OFFSET    4\n#define    RTL8367C_LBOUND_MASK    0xF0\n#define    RTL8367C_HBOUND_OFFSET    0\n#define    RTL8367C_HBOUND_MASK    0xF\n\n#define    RTL8367C_REG_CFG_TX_ITFSP_OP    0x1204\n#define    RTL8367C_MASK_OFFSET    1\n#define    RTL8367C_MASK_MASK    0x2\n#define    RTL8367C_OP_OFFSET    0\n#define    RTL8367C_OP_MASK    0x1\n\n#define    RTL8367C_REG_INBW_BOUND2    0x1205\n#define    RTL8367C_LBOUND2_H_OFFSET    9\n#define    RTL8367C_LBOUND2_H_MASK    0x200\n#define    RTL8367C_HBOUND2_H_OFFSET    8\n#define    RTL8367C_HBOUND2_H_MASK    0x100\n#define    RTL8367C_LBOUND2_OFFSET    4\n#define    RTL8367C_LBOUND2_MASK    0xF0\n#define    RTL8367C_HBOUND2_OFFSET    0\n#define    RTL8367C_HBOUND2_MASK    0xF\n\n#define    RTL8367C_REG_CFG_48PASS1_DROP    0x1206\n#define    RTL8367C_CFG_48PASS1_DROP_OFFSET    0\n#define    RTL8367C_CFG_48PASS1_DROP_MASK    0x1\n\n#define    RTL8367C_REG_CFG_BACKPRESSURE    0x1207\n#define    RTL8367C_LONGTXE_OFFSET    12\n#define    RTL8367C_LONGTXE_MASK    0x1000\n#define    RTL8367C_EN_BYPASS_ERROR_OFFSET    8\n#define    RTL8367C_EN_BYPASS_ERROR_MASK    0x100\n#define    RTL8367C_EN_BACKPRESSURE_OFFSET    4\n#define    RTL8367C_EN_BACKPRESSURE_MASK    0x10\n#define    RTL8367C_EN_48_PASS_1_OFFSET    0\n#define    RTL8367C_EN_48_PASS_1_MASK    0x1\n\n#define    RTL8367C_REG_CFG_UNHIOL    0x1208\n#define    RTL8367C_IOL_BACKOFF_OFFSET    12\n#define    RTL8367C_IOL_BACKOFF_MASK    0x1000\n#define    RTL8367C_BACKOFF_RANDOM_TIME_OFFSET    8\n#define    RTL8367C_BACKOFF_RANDOM_TIME_MASK    0x100\n#define    RTL8367C_DISABLE_BACK_OFF_OFFSET    4\n#define    RTL8367C_DISABLE_BACK_OFF_MASK    0x10\n#define    RTL8367C_IPG_COMPENSATION_OFFSET    0\n#define    RTL8367C_IPG_COMPENSATION_MASK    0x1\n\n#define    RTL8367C_REG_SWITCH_MAC0    0x1209\n\n#define    RTL8367C_REG_SWITCH_MAC1    0x120a\n\n#define    RTL8367C_REG_SWITCH_MAC2    0x120b\n\n#define    RTL8367C_REG_SWITCH_CTRL0    0x120c\n#define    RTL8367C_REMARKING_DSCP_ENABLE_OFFSET    8\n#define    RTL8367C_REMARKING_DSCP_ENABLE_MASK    0x100\n#define    RTL8367C_SHORT_IPG_OFFSET    4\n#define    RTL8367C_SHORT_IPG_MASK    0x10\n#define    RTL8367C_PAUSE_MAX128_OFFSET    0\n#define    RTL8367C_PAUSE_MAX128_MASK    0x1\n\n#define    RTL8367C_REG_QOS_DSCP_REMARK_CTRL0    0x120d\n#define    RTL8367C_INTPRI1_DSCP_OFFSET    8\n#define    RTL8367C_INTPRI1_DSCP_MASK    0x3F00\n#define    RTL8367C_INTPRI0_DSCP_OFFSET    0\n#define    RTL8367C_INTPRI0_DSCP_MASK    0x3F\n\n#define    RTL8367C_REG_QOS_DSCP_REMARK_CTRL1    0x120e\n#define    RTL8367C_INTPRI3_DSCP_OFFSET    8\n#define    RTL8367C_INTPRI3_DSCP_MASK    0x3F00\n#define    RTL8367C_INTPRI2_DSCP_OFFSET    0\n#define    RTL8367C_INTPRI2_DSCP_MASK    0x3F\n\n#define    RTL8367C_REG_QOS_DSCP_REMARK_CTRL2    0x120f\n#define    RTL8367C_INTPRI5_DSCP_OFFSET    8\n#define    RTL8367C_INTPRI5_DSCP_MASK    0x3F00\n#define    RTL8367C_INTPRI4_DSCP_OFFSET    0\n#define    RTL8367C_INTPRI4_DSCP_MASK    0x3F\n\n#define    RTL8367C_REG_QOS_DSCP_REMARK_CTRL3    0x1210\n#define    RTL8367C_INTPRI7_DSCP_OFFSET    8\n#define    RTL8367C_INTPRI7_DSCP_MASK    0x3F00\n#define    RTL8367C_INTPRI6_DSCP_OFFSET    0\n#define    RTL8367C_INTPRI6_DSCP_MASK    0x3F\n\n#define    RTL8367C_REG_QOS_1Q_REMARK_CTRL0    0x1211\n#define    RTL8367C_INTPRI3_PRI_OFFSET    12\n#define    RTL8367C_INTPRI3_PRI_MASK    0x7000\n#define    RTL8367C_INTPRI2_PRI_OFFSET    8\n#define    RTL8367C_INTPRI2_PRI_MASK    0x700\n#define    RTL8367C_INTPRI1_PRI_OFFSET    4\n#define    RTL8367C_INTPRI1_PRI_MASK    0x70\n#define    RTL8367C_INTPRI0_PRI_OFFSET    0\n#define    RTL8367C_INTPRI0_PRI_MASK    0x7\n\n#define    RTL8367C_REG_QOS_1Q_REMARK_CTRL1    0x1212\n#define    RTL8367C_INTPRI7_PRI_OFFSET    12\n#define    RTL8367C_INTPRI7_PRI_MASK    0x7000\n#define    RTL8367C_INTPRI6_PRI_OFFSET    8\n#define    RTL8367C_INTPRI6_PRI_MASK    0x700\n#define    RTL8367C_INTPRI5_PRI_OFFSET    4\n#define    RTL8367C_INTPRI5_PRI_MASK    0x70\n#define    RTL8367C_INTPRI4_PRI_OFFSET    0\n#define    RTL8367C_INTPRI4_PRI_MASK    0x7\n\n#define    RTL8367C_REG_PKTGEN_COMMAND    0x1213\n#define    RTL8367C_PKTGEN_STOP_OFFSET    8\n#define    RTL8367C_PKTGEN_STOP_MASK    0x100\n#define    RTL8367C_PKTGEN_START_OFFSET    4\n#define    RTL8367C_PKTGEN_START_MASK    0x10\n#define    RTL8367C_PKTGEN_BYPASS_FLOWCONTROL_OFFSET    0\n#define    RTL8367C_PKTGEN_BYPASS_FLOWCONTROL_MASK    0x1\n\n#define    RTL8367C_REG_SW_DUMMY0    0x1214\n#define    RTL8367C_SW_DUMMY0_DUMMY_OFFSET    4\n#define    RTL8367C_SW_DUMMY0_DUMMY_MASK    0xFFF0\n#define    RTL8367C_EEE_DEFER_TXLPI_OFFSET    3\n#define    RTL8367C_EEE_DEFER_TXLPI_MASK    0x8\n#define    RTL8367C_INGRESSBW_BYPASS_EN_OFFSET    2\n#define    RTL8367C_INGRESSBW_BYPASS_EN_MASK    0x4\n#define    RTL8367C_CFG_RX_MIN_OFFSET    0\n#define    RTL8367C_CFG_RX_MIN_MASK    0x3\n\n#define    RTL8367C_REG_SW_DUMMY1    0x1215\n\n#define    RTL8367C_REG_PKTGEN_PAUSE_TIME    0x1216\n\n#define    RTL8367C_REG_SVLAN_UPLINK_PORTMASK    0x1218\n#define    RTL8367C_SVLAN_UPLINK_PORTMASK_OFFSET    0\n#define    RTL8367C_SVLAN_UPLINK_PORTMASK_MASK    0x7FF\n\n#define    RTL8367C_REG_CPU_PORT_MASK    0x1219\n#define    RTL8367C_CPU_PORT_MASK_OFFSET    0\n#define    RTL8367C_CPU_PORT_MASK_MASK    0x7FF\n\n#define    RTL8367C_REG_CPU_CTRL    0x121a\n#define    RTL8367C_CPU_TRAP_PORT_EXT_OFFSET    10\n#define    RTL8367C_CPU_TRAP_PORT_EXT_MASK    0x400\n#define    RTL8367C_CPU_TAG_FORMAT_OFFSET    9\n#define    RTL8367C_CPU_TAG_FORMAT_MASK    0x200\n#define    RTL8367C_IOL_16DROP_OFFSET    8\n#define    RTL8367C_IOL_16DROP_MASK    0x100\n#define    RTL8367C_CPU_TAG_RXBYTECOUNT_OFFSET    7\n#define    RTL8367C_CPU_TAG_RXBYTECOUNT_MASK    0x80\n#define    RTL8367C_CPU_TAG_POSITION_OFFSET    6\n#define    RTL8367C_CPU_TAG_POSITION_MASK    0x40\n#define    RTL8367C_CPU_TRAP_PORT_OFFSET    3\n#define    RTL8367C_CPU_TRAP_PORT_MASK    0x38\n#define    RTL8367C_CPU_INSERTMODE_OFFSET    1\n#define    RTL8367C_CPU_INSERTMODE_MASK    0x6\n#define    RTL8367C_CPU_EN_OFFSET    0\n#define    RTL8367C_CPU_EN_MASK    0x1\n\n#define    RTL8367C_REG_MIRROR_CTRL    0x121c\n#define    RTL8367C_MIRROR_CTRL_DUMMY_OFFSET    12\n#define    RTL8367C_MIRROR_CTRL_DUMMY_MASK    0xF000\n#define    RTL8367C_MIRROR_ISO_OFFSET    11\n#define    RTL8367C_MIRROR_ISO_MASK    0x800\n#define    RTL8367C_MIRROR_TX_OFFSET    10\n#define    RTL8367C_MIRROR_TX_MASK    0x400\n#define    RTL8367C_MIRROR_RX_OFFSET    9\n#define    RTL8367C_MIRROR_RX_MASK    0x200\n#define    RTL8367C_MIRROR_MONITOR_PORT_OFFSET    4\n#define    RTL8367C_MIRROR_MONITOR_PORT_MASK    0xF0\n#define    RTL8367C_MIRROR_SOURCE_PORT_OFFSET    0\n#define    RTL8367C_MIRROR_SOURCE_PORT_MASK    0xF\n\n#define    RTL8367C_REG_FLOWCTRL_CTRL0    0x121d\n#define    RTL8367C_FLOWCTRL_TYPE_OFFSET    15\n#define    RTL8367C_FLOWCTRL_TYPE_MASK    0x8000\n#define    RTL8367C_DROP_ALL_THRESHOLD_OFFSET    5\n#define    RTL8367C_DROP_ALL_THRESHOLD_MASK    0x7FE0\n#define    RTL8367C_DROP_ALL_THRESHOLD_MSB_OFFSET    4\n#define    RTL8367C_DROP_ALL_THRESHOLD_MSB_MASK    0x10\n#define    RTL8367C_ITFSP_REG_OFFSET    0\n#define    RTL8367C_ITFSP_REG_MASK    0x7\n\n#define    RTL8367C_REG_FLOWCTRL_ALL_ON    0x121e\n#define    RTL8367C_CFG_RLDPACT_OFFSET    12\n#define    RTL8367C_CFG_RLDPACT_MASK    0x1000\n#define    RTL8367C_FLOWCTRL_ALL_ON_THRESHOLD_OFFSET    0\n#define    RTL8367C_FLOWCTRL_ALL_ON_THRESHOLD_MASK    0x7FF\n\n#define    RTL8367C_REG_FLOWCTRL_SYS_ON    0x121f\n#define    RTL8367C_FLOWCTRL_SYS_ON_OFFSET    0\n#define    RTL8367C_FLOWCTRL_SYS_ON_MASK    0x7FF\n\n#define    RTL8367C_REG_FLOWCTRL_SYS_OFF    0x1220\n#define    RTL8367C_FLOWCTRL_SYS_OFF_OFFSET    0\n#define    RTL8367C_FLOWCTRL_SYS_OFF_MASK    0x7FF\n\n#define    RTL8367C_REG_FLOWCTRL_SHARE_ON    0x1221\n#define    RTL8367C_FLOWCTRL_SHARE_ON_OFFSET    0\n#define    RTL8367C_FLOWCTRL_SHARE_ON_MASK    0x7FF\n\n#define    RTL8367C_REG_FLOWCTRL_SHARE_OFF    0x1222\n#define    RTL8367C_FLOWCTRL_SHARE_OFF_OFFSET    0\n#define    RTL8367C_FLOWCTRL_SHARE_OFF_MASK    0x7FF\n\n#define    RTL8367C_REG_FLOWCTRL_FCOFF_SYS_ON    0x1223\n#define    RTL8367C_FLOWCTRL_FCOFF_SYS_ON_OFFSET    0\n#define    RTL8367C_FLOWCTRL_FCOFF_SYS_ON_MASK    0x7FF\n\n#define    RTL8367C_REG_FLOWCTRL_FCOFF_SYS_OFF    0x1224\n#define    RTL8367C_FLOWCTRL_FCOFF_SYS_OFF_OFFSET    0\n#define    RTL8367C_FLOWCTRL_FCOFF_SYS_OFF_MASK    0x7FF\n\n#define    RTL8367C_REG_FLOWCTRL_FCOFF_SHARE_ON    0x1225\n#define    RTL8367C_FLOWCTRL_FCOFF_SHARE_ON_OFFSET    0\n#define    RTL8367C_FLOWCTRL_FCOFF_SHARE_ON_MASK    0x7FF\n\n#define    RTL8367C_REG_FLOWCTRL_FCOFF_SHARE_OFF    0x1226\n#define    RTL8367C_FLOWCTRL_FCOFF_SHARE_OFF_OFFSET    0\n#define    RTL8367C_FLOWCTRL_FCOFF_SHARE_OFF_MASK    0x7FF\n\n#define    RTL8367C_REG_FLOWCTRL_PORT_ON    0x1227\n#define    RTL8367C_FLOWCTRL_PORT_ON_OFFSET    0\n#define    RTL8367C_FLOWCTRL_PORT_ON_MASK    0x7FF\n\n#define    RTL8367C_REG_FLOWCTRL_PORT_OFF    0x1228\n#define    RTL8367C_FLOWCTRL_PORT_OFF_OFFSET    0\n#define    RTL8367C_FLOWCTRL_PORT_OFF_MASK    0x7FF\n\n#define    RTL8367C_REG_FLOWCTRL_PORT_PRIVATE_ON    0x1229\n#define    RTL8367C_FLOWCTRL_PORT_PRIVATE_ON_OFFSET    0\n#define    RTL8367C_FLOWCTRL_PORT_PRIVATE_ON_MASK    0x7FF\n\n#define    RTL8367C_REG_FLOWCTRL_PORT_PRIVATE_OFF    0x122a\n#define    RTL8367C_FLOWCTRL_PORT_PRIVATE_OFF_OFFSET    0\n#define    RTL8367C_FLOWCTRL_PORT_PRIVATE_OFF_MASK    0x7FF\n\n#define    RTL8367C_REG_RRCP_CTRL0    0x122b\n#define    RTL8367C_COL_SEL_OFFSET    14\n#define    RTL8367C_COL_SEL_MASK    0x4000\n#define    RTL8367C_CRS_SEL_OFFSET    13\n#define    RTL8367C_CRS_SEL_MASK    0x2000\n#define    RTL8367C_RRCP_PBVLAN_EN_OFFSET    11\n#define    RTL8367C_RRCP_PBVLAN_EN_MASK    0x800\n#define    RTL8367C_RRCPV3_SECURITY_CRC_OFFSET    10\n#define    RTL8367C_RRCPV3_SECURITY_CRC_MASK    0x400\n#define    RTL8367C_RRCPV3_HANDLE_OFFSET    8\n#define    RTL8367C_RRCPV3_HANDLE_MASK    0x300\n#define    RTL8367C_RRCPV1_MALFORMED_ACT_OFFSET    5\n#define    RTL8367C_RRCPV1_MALFORMED_ACT_MASK    0x60\n#define    RTL8367C_RRCP_VLANLEAKY_OFFSET    4\n#define    RTL8367C_RRCP_VLANLEAKY_MASK    0x10\n#define    RTL8367C_RRCPV1_SECURITY_CRC_GET_OFFSET    3\n#define    RTL8367C_RRCPV1_SECURITY_CRC_GET_MASK    0x8\n#define    RTL8367C_RRCPV1_SECURITY_CRC_SET_OFFSET    2\n#define    RTL8367C_RRCPV1_SECURITY_CRC_SET_MASK    0x4\n#define    RTL8367C_RRCPV1_HANDLE_OFFSET    1\n#define    RTL8367C_RRCPV1_HANDLE_MASK    0x2\n#define    RTL8367C_RRCP_ENABLE_OFFSET    0\n#define    RTL8367C_RRCP_ENABLE_MASK    0x1\n\n#define    RTL8367C_REG_RRCP_CTRL1    0x122c\n#define    RTL8367C_RRCP_ADMIN_PMSK_OFFSET    8\n#define    RTL8367C_RRCP_ADMIN_PMSK_MASK    0xFF00\n#define    RTL8367C_RRCP_AUTH_PMSK_OFFSET    0\n#define    RTL8367C_RRCP_AUTH_PMSK_MASK    0xFF\n\n#define    RTL8367C_REG_RRCP_CTRL2    0x122d\n#define    RTL8367C_RRCPV1_HELLOFWD_TAG_OFFSET    9\n#define    RTL8367C_RRCPV1_HELLOFWD_TAG_MASK    0x600\n#define    RTL8367C_RRCP_FWD_TAG_OFFSET    7\n#define    RTL8367C_RRCP_FWD_TAG_MASK    0x180\n#define    RTL8367C_RRCPV1_REPLY_TAG_OFFSET    6\n#define    RTL8367C_RRCPV1_REPLY_TAG_MASK    0x40\n#define    RTL8367C_RRCPV1_HELLO_COUNT_OFFSET    3\n#define    RTL8367C_RRCPV1_HELLO_COUNT_MASK    0x38\n#define    RTL8367C_RRCPV1_HELLO_PEDIOD_OFFSET    0\n#define    RTL8367C_RRCPV1_HELLO_PEDIOD_MASK    0x3\n\n#define    RTL8367C_REG_RRCP_CTRL3    0x122e\n#define    RTL8367C_RRCP_TAG_PRIORITY_OFFSET    13\n#define    RTL8367C_RRCP_TAG_PRIORITY_MASK    0xE000\n#define    RTL8367C_RRCP_TAG_VID_OFFSET    0\n#define    RTL8367C_RRCP_TAG_VID_MASK    0xFFF\n\n#define    RTL8367C_REG_FLOWCTRL_FCOFF_PORT_ON    0x122f\n#define    RTL8367C_FLOWCTRL_FCOFF_PORT_ON_OFFSET    0\n#define    RTL8367C_FLOWCTRL_FCOFF_PORT_ON_MASK    0x7FF\n\n#define    RTL8367C_REG_FLOWCTRL_FCOFF_PORT_OFF    0x1230\n#define    RTL8367C_FLOWCTRL_FCOFF_PORT_OFF_OFFSET    0\n#define    RTL8367C_FLOWCTRL_FCOFF_PORT_OFF_MASK    0x7FF\n\n#define    RTL8367C_REG_FLOWCTRL_FCOFF_PORT_PRIVATE_ON    0x1231\n#define    RTL8367C_FLOWCTRL_FCOFF_PORT_PRIVATE_ON_OFFSET    0\n#define    RTL8367C_FLOWCTRL_FCOFF_PORT_PRIVATE_ON_MASK    0x7FF\n\n#define    RTL8367C_REG_FLOWCTRL_FCOFF_PORT_PRIVATE_OFF    0x1232\n#define    RTL8367C_FLOWCTRL_FCOFF_PORT_PRIVATE_OFF_OFFSET    0\n#define    RTL8367C_FLOWCTRL_FCOFF_PORT_PRIVATE_OFF_MASK    0x7FF\n\n#define    RTL8367C_REG_FLOWCTRL_JUMBO_SYS_ON    0x1233\n#define    RTL8367C_FLOWCTRL_JUMBO_SYS_ON_OFFSET    0\n#define    RTL8367C_FLOWCTRL_JUMBO_SYS_ON_MASK    0x7FF\n\n#define    RTL8367C_REG_FLOWCTRL_JUMBO_SYS_OFF    0x1234\n#define    RTL8367C_FLOWCTRL_JUMBO_SYS_OFF_OFFSET    0\n#define    RTL8367C_FLOWCTRL_JUMBO_SYS_OFF_MASK    0x7FF\n\n#define    RTL8367C_REG_FLOWCTRL_JUMBO_SHARE_ON    0x1235\n#define    RTL8367C_FLOWCTRL_JUMBO_SHARE_ON_OFFSET    0\n#define    RTL8367C_FLOWCTRL_JUMBO_SHARE_ON_MASK    0x7FF\n\n#define    RTL8367C_REG_FLOWCTRL_JUMBO_SHARE_OFF    0x1236\n#define    RTL8367C_FLOWCTRL_JUMBO_SHARE_OFF_OFFSET    0\n#define    RTL8367C_FLOWCTRL_JUMBO_SHARE_OFF_MASK    0x7FF\n\n#define    RTL8367C_REG_FLOWCTRL_JUMBO_PORT_ON    0x1237\n#define    RTL8367C_FLOWCTRL_JUMBO_PORT_ON_OFFSET    0\n#define    RTL8367C_FLOWCTRL_JUMBO_PORT_ON_MASK    0x7FF\n\n#define    RTL8367C_REG_FLOWCTRL_JUMBO_PORT_OFF    0x1238\n#define    RTL8367C_FLOWCTRL_JUMBO_PORT_OFF_OFFSET    0\n#define    RTL8367C_FLOWCTRL_JUMBO_PORT_OFF_MASK    0x7FF\n\n#define    RTL8367C_REG_FLOWCTRL_JUMBO_PORT_PRIVATE_ON    0x1239\n#define    RTL8367C_FLOWCTRL_JUMBO_PORT_PRIVATE_ON_OFFSET    0\n#define    RTL8367C_FLOWCTRL_JUMBO_PORT_PRIVATE_ON_MASK    0x7FF\n\n#define    RTL8367C_REG_FLOWCTRL_JUMBO_PORT_PRIVATE_OFF    0x123a\n#define    RTL8367C_FLOWCTRL_JUMBO_PORT_PRIVATE_OFF_OFFSET    0\n#define    RTL8367C_FLOWCTRL_JUMBO_PORT_PRIVATE_OFF_MASK    0x7FF\n\n#define    RTL8367C_REG_FLOWCTRL_JUMBO_SIZE    0x123b\n#define    RTL8367C_JUMBO_MODE_OFFSET    2\n#define    RTL8367C_JUMBO_MODE_MASK    0x4\n#define    RTL8367C_JUMBO_SIZE_OFFSET    0\n#define    RTL8367C_JUMBO_SIZE_MASK    0x3\n\n#define    RTL8367C_REG_FLOWCTRL_TOTAL_PAGE_COUNTER    0x124c\n#define    RTL8367C_FLOWCTRL_TOTAL_PAGE_COUNTER_OFFSET    0\n#define    RTL8367C_FLOWCTRL_TOTAL_PAGE_COUNTER_MASK    0x7FF\n\n#define    RTL8367C_REG_FLOWCTRL_PUBLIC_PAGE_COUNTER    0x124d\n#define    RTL8367C_FLOWCTRL_PUBLIC_PAGE_COUNTER_OFFSET    0\n#define    RTL8367C_FLOWCTRL_PUBLIC_PAGE_COUNTER_MASK    0x7FF\n\n#define    RTL8367C_REG_FLOWCTRL_TOTAL_PAGE_MAX    0x124e\n#define    RTL8367C_FLOWCTRL_TOTAL_PAGE_MAX_OFFSET    0\n#define    RTL8367C_FLOWCTRL_TOTAL_PAGE_MAX_MASK    0x7FF\n\n#define    RTL8367C_REG_FLOWCTRL_PUBLIC_PAGE_MAX    0x124f\n#define    RTL8367C_FLOWCTRL_PUBLIC_PAGE_MAX_OFFSET    0\n#define    RTL8367C_FLOWCTRL_PUBLIC_PAGE_MAX_MASK    0x7FF\n\n#define    RTL8367C_REG_FLOWCTRL_PORT0_PAGE_COUNTER    0x1250\n#define    RTL8367C_FLOWCTRL_PORT0_PAGE_COUNTER_OFFSET    0\n#define    RTL8367C_FLOWCTRL_PORT0_PAGE_COUNTER_MASK    0x7FF\n\n#define    RTL8367C_REG_FLOWCTRL_PORT1_PAGE_COUNTER    0x1251\n#define    RTL8367C_FLOWCTRL_PORT1_PAGE_COUNTER_OFFSET    0\n#define    RTL8367C_FLOWCTRL_PORT1_PAGE_COUNTER_MASK    0x7FF\n\n#define    RTL8367C_REG_FLOWCTRL_PORT2_PAGE_COUNTER    0x1252\n#define    RTL8367C_FLOWCTRL_PORT2_PAGE_COUNTER_OFFSET    0\n#define    RTL8367C_FLOWCTRL_PORT2_PAGE_COUNTER_MASK    0x7FF\n\n#define    RTL8367C_REG_FLOWCTRL_PORT3_PAGE_COUNTER    0x1253\n#define    RTL8367C_FLOWCTRL_PORT3_PAGE_COUNTER_OFFSET    0\n#define    RTL8367C_FLOWCTRL_PORT3_PAGE_COUNTER_MASK    0x7FF\n\n#define    RTL8367C_REG_FLOWCTRL_PORT4_PAGE_COUNTER    0x1254\n#define    RTL8367C_FLOWCTRL_PORT4_PAGE_COUNTER_OFFSET    0\n#define    RTL8367C_FLOWCTRL_PORT4_PAGE_COUNTER_MASK    0x7FF\n\n#define    RTL8367C_REG_FLOWCTRL_PORT5_PAGE_COUNTER    0x1255\n#define    RTL8367C_FLOWCTRL_PORT5_PAGE_COUNTER_OFFSET    0\n#define    RTL8367C_FLOWCTRL_PORT5_PAGE_COUNTER_MASK    0x7FF\n\n#define    RTL8367C_REG_FLOWCTRL_PORT6_PAGE_COUNTER    0x1256\n#define    RTL8367C_FLOWCTRL_PORT6_PAGE_COUNTER_OFFSET    0\n#define    RTL8367C_FLOWCTRL_PORT6_PAGE_COUNTER_MASK    0x7FF\n\n#define    RTL8367C_REG_FLOWCTRL_PORT7_PAGE_COUNTER    0x1257\n#define    RTL8367C_FLOWCTRL_PORT7_PAGE_COUNTER_OFFSET    0\n#define    RTL8367C_FLOWCTRL_PORT7_PAGE_COUNTER_MASK    0x7FF\n\n#define    RTL8367C_REG_FLOWCTRL_PUBLIC_FCOFF_PAGE_COUNTER    0x1258\n#define    RTL8367C_FLOWCTRL_PUBLIC_FCOFF_PAGE_COUNTER_OFFSET    0\n#define    RTL8367C_FLOWCTRL_PUBLIC_FCOFF_PAGE_COUNTER_MASK    0x7FF\n\n#define    RTL8367C_REG_FLOWCTRL_PUBLIC_JUMBO_PAGE_COUNTER    0x1259\n#define    RTL8367C_FLOWCTRL_PUBLIC_JUMBO_PAGE_COUNTER_OFFSET    0\n#define    RTL8367C_FLOWCTRL_PUBLIC_JUMBO_PAGE_COUNTER_MASK    0x7FF\n\n#define    RTL8367C_REG_FLOWCTRL_MAX_PUBLIC_FCOFF_PAGE_COUNTER    0x125a\n#define    RTL8367C_FLOWCTRL_MAX_PUBLIC_FCOFF_PAGE_COUNTER_OFFSET    0\n#define    RTL8367C_FLOWCTRL_MAX_PUBLIC_FCOFF_PAGE_COUNTER_MASK    0x7FF\n\n#define    RTL8367C_REG_FLOWCTRL_MAX_PUBLIC_JUMBO_PAGE_COUNTER    0x125b\n#define    RTL8367C_FLOWCTRL_MAX_PUBLIC_JUMBO_PAGE_COUNTER_OFFSET    0\n#define    RTL8367C_FLOWCTRL_MAX_PUBLIC_JUMBO_PAGE_COUNTER_MASK    0x7FF\n\n#define    RTL8367C_REG_FLOWCTRL_PORT0_PAGE_MAX    0x1260\n#define    RTL8367C_FLOWCTRL_PORT0_PAGE_MAX_OFFSET    0\n#define    RTL8367C_FLOWCTRL_PORT0_PAGE_MAX_MASK    0x7FF\n\n#define    RTL8367C_REG_FLOWCTRL_PORT1_PAGE_MAX    0x1261\n#define    RTL8367C_FLOWCTRL_PORT1_PAGE_MAX_OFFSET    0\n#define    RTL8367C_FLOWCTRL_PORT1_PAGE_MAX_MASK    0x7FF\n\n#define    RTL8367C_REG_FLOWCTRL_PORT2_PAGE_MAX    0x1262\n#define    RTL8367C_FLOWCTRL_PORT2_PAGE_MAX_OFFSET    0\n#define    RTL8367C_FLOWCTRL_PORT2_PAGE_MAX_MASK    0x7FF\n\n#define    RTL8367C_REG_FLOWCTRL_PORT3_PAGE_MAX    0x1263\n#define    RTL8367C_FLOWCTRL_PORT3_PAGE_MAX_OFFSET    0\n#define    RTL8367C_FLOWCTRL_PORT3_PAGE_MAX_MASK    0x7FF\n\n#define    RTL8367C_REG_FLOWCTRL_PORT4_PAGE_MAX    0x1264\n#define    RTL8367C_FLOWCTRL_PORT4_PAGE_MAX_OFFSET    0\n#define    RTL8367C_FLOWCTRL_PORT4_PAGE_MAX_MASK    0x7FF\n\n#define    RTL8367C_REG_FLOWCTRL_PORT5_PAGE_MAX    0x1265\n#define    RTL8367C_FLOWCTRL_PORT5_PAGE_MAX_OFFSET    0\n#define    RTL8367C_FLOWCTRL_PORT5_PAGE_MAX_MASK    0x7FF\n\n#define    RTL8367C_REG_FLOWCTRL_PORT6_PAGE_MAX    0x1266\n#define    RTL8367C_FLOWCTRL_PORT6_PAGE_MAX_OFFSET    0\n#define    RTL8367C_FLOWCTRL_PORT6_PAGE_MAX_MASK    0x7FF\n\n#define    RTL8367C_REG_FLOWCTRL_PORT7_PAGE_MAX    0x1267\n#define    RTL8367C_FLOWCTRL_PORT7_PAGE_MAX_OFFSET    0\n#define    RTL8367C_FLOWCTRL_PORT7_PAGE_MAX_MASK    0x7FF\n\n#define    RTL8367C_REG_FLOWCTRL_PAGE_COUNT_CLEAR    0x1268\n#define    RTL8367C_DIS_SKIP_FP_OFFSET    1\n#define    RTL8367C_DIS_SKIP_FP_MASK    0x2\n#define    RTL8367C_PAGE_COUNT_CLEAR_OFFSET    0\n#define    RTL8367C_PAGE_COUNT_CLEAR_MASK    0x1\n\n#define    RTL8367C_REG_FLOWCTRL_PORT8_PAGE_MAX    0x1269\n#define    RTL8367C_FLOWCTRL_PORT8_PAGE_MAX_OFFSET    0\n#define    RTL8367C_FLOWCTRL_PORT8_PAGE_MAX_MASK    0x7FF\n\n#define    RTL8367C_REG_FLOWCTRL_PORT9_PAGE_MAX    0x126a\n#define    RTL8367C_FLOWCTRL_PORT9_PAGE_MAX_OFFSET    0\n#define    RTL8367C_FLOWCTRL_PORT9_PAGE_MAX_MASK    0x7FF\n\n#define    RTL8367C_REG_FLOWCTRL_PORT10_PAGE_MAX    0x126b\n#define    RTL8367C_FLOWCTRL_PORT10_PAGE_MAX_OFFSET    0\n#define    RTL8367C_FLOWCTRL_PORT10_PAGE_MAX_MASK    0x7FF\n\n#define    RTL8367C_REG_FLOWCTRL_PORT8_PAGE_COUNTER    0x126c\n#define    RTL8367C_FLOWCTRL_PORT8_PAGE_COUNTER_OFFSET    0\n#define    RTL8367C_FLOWCTRL_PORT8_PAGE_COUNTER_MASK    0x7FF\n\n#define    RTL8367C_REG_FLOWCTRL_PORT9_PAGE_COUNTER    0x126d\n#define    RTL8367C_FLOWCTRL_PORT9_PAGE_COUNTER_OFFSET    0\n#define    RTL8367C_FLOWCTRL_PORT9_PAGE_COUNTER_MASK    0x7FF\n\n#define    RTL8367C_REG_FLOWCTRL_PORT10_PAGE_COUNTER    0x126e\n#define    RTL8367C_FLOWCTRL_PORT10_PAGE_COUNTER_OFFSET    0\n#define    RTL8367C_FLOWCTRL_PORT10_PAGE_COUNTER_MASK    0x7FF\n\n#define    RTL8367C_REG_RRCP_CTRL1_H    0x126f\n#define    RTL8367C_RRCP_ADMIN_PMSK_P10_8_OFFSET    3\n#define    RTL8367C_RRCP_ADMIN_PMSK_P10_8_MASK    0x38\n#define    RTL8367C_RRCP_AUTH_PMSK_P10_8_OFFSET    0\n#define    RTL8367C_RRCP_AUTH_PMSK_P10_8_MASK    0x7\n\n#define    RTL8367C_REG_EMA_CTRL0    0x1270\n#define    RTL8367C_CFG_DVSE_VIAROM_OFFSET    13\n#define    RTL8367C_CFG_DVSE_VIAROM_MASK    0x2000\n#define    RTL8367C_CFG_DVSE_MIBRAM_OFFSET    12\n#define    RTL8367C_CFG_DVSE_MIBRAM_MASK    0x1000\n#define    RTL8367C_CFG_DVSE_IROM_OFFSET    11\n#define    RTL8367C_CFG_DVSE_IROM_MASK    0x800\n#define    RTL8367C_CFG_DVSE_ERAM_OFFSET    10\n#define    RTL8367C_CFG_DVSE_ERAM_MASK    0x400\n#define    RTL8367C_CFG_DVSE_IRAM_OFFSET    9\n#define    RTL8367C_CFG_DVSE_IRAM_MASK    0x200\n#define    RTL8367C_CFG_DVSE_NICRAM_OFFSET    8\n#define    RTL8367C_CFG_DVSE_NICRAM_MASK    0x100\n#define    RTL8367C_CFG_DVSE_CVLANRAM_OFFSET    7\n#define    RTL8367C_CFG_DVSE_CVLANRAM_MASK    0x80\n#define    RTL8367C_CFG_DVSE_ACTRAM_OFFSET    6\n#define    RTL8367C_CFG_DVSE_ACTRAM_MASK    0x40\n#define    RTL8367C_CFG_DVSE_INQRAM_OFFSET    5\n#define    RTL8367C_CFG_DVSE_INQRAM_MASK    0x20\n#define    RTL8367C_CFG_DVSE_HSARAM_OFFSET    4\n#define    RTL8367C_CFG_DVSE_HSARAM_MASK    0x10\n#define    RTL8367C_CFG_DVSE_OUTQRAM_OFFSET    3\n#define    RTL8367C_CFG_DVSE_OUTQRAM_MASK    0x8\n#define    RTL8367C_CFG_DVSE_HTRAM_OFFSET    2\n#define    RTL8367C_CFG_DVSE_HTRAM_MASK    0x4\n#define    RTL8367C_CFG_DVSE_PBRAM_OFFSET    1\n#define    RTL8367C_CFG_DVSE_PBRAM_MASK    0x2\n#define    RTL8367C_CFG_DVSE_L2RAM_OFFSET    0\n#define    RTL8367C_CFG_DVSE_L2RAM_MASK    0x1\n\n#define    RTL8367C_REG_EMA_CTRL1    0x1271\n#define    RTL8367C_CFG_DVS_OUTQRAM_OFFSET    12\n#define    RTL8367C_CFG_DVS_OUTQRAM_MASK    0xF000\n#define    RTL8367C_CFG_DVS_HTRAM_OFFSET    8\n#define    RTL8367C_CFG_DVS_HTRAM_MASK    0x700\n#define    RTL8367C_CFG_DVS_PBRAM_OFFSET    4\n#define    RTL8367C_CFG_DVS_PBRAM_MASK    0xF0\n#define    RTL8367C_CFG_DVS_L2RAM_OFFSET    0\n#define    RTL8367C_CFG_DVS_L2RAM_MASK    0xF\n\n#define    RTL8367C_REG_EMA_CTRL2    0x1272\n#define    RTL8367C_CFG_DVS_CVLANRAM_OFFSET    12\n#define    RTL8367C_CFG_DVS_CVLANRAM_MASK    0xF000\n#define    RTL8367C_CFG_DVS_ACTRAM_OFFSET    8\n#define    RTL8367C_CFG_DVS_ACTRAM_MASK    0xF00\n#define    RTL8367C_CFG_DVS_INQRAM_OFFSET    4\n#define    RTL8367C_CFG_DVS_INQRAM_MASK    0xF0\n#define    RTL8367C_CFG_DVS_HSARAM_OFFSET    0\n#define    RTL8367C_CFG_DVS_HSARAM_MASK    0xF\n\n#define    RTL8367C_REG_EMA_CTRL3    0x1273\n#define    RTL8367C_CFG_DVS_IROM_OFFSET    12\n#define    RTL8367C_CFG_DVS_IROM_MASK    0xF000\n#define    RTL8367C_CFG_DVS_ERAM_OFFSET    8\n#define    RTL8367C_CFG_DVS_ERAM_MASK    0xF00\n#define    RTL8367C_CFG_DVS_IRAM_OFFSET    4\n#define    RTL8367C_CFG_DVS_IRAM_MASK    0xF0\n#define    RTL8367C_CFG_DVS_NICRAM_OFFSET    0\n#define    RTL8367C_CFG_DVS_NICRAM_MASK    0xF\n\n#define    RTL8367C_REG_EMA_CTRL4    0x1274\n#define    RTL8367C_CFG_DVS_VIAROM_OFFSET    4\n#define    RTL8367C_CFG_DVS_VIAROM_MASK    0xF0\n#define    RTL8367C_CFG_DVS_MIBRAM_OFFSET    0\n#define    RTL8367C_CFG_DVS_MIBRAM_MASK    0xF\n\n#define    RTL8367C_REG_DIAG_MODE    0x1275\n#define    RTL8367C_DIAG_MODE_OFFSET    0\n#define    RTL8367C_DIAG_MODE_MASK    0x1F\n\n#define    RTL8367C_REG_BIST_MODE    0x1276\n\n#define    RTL8367C_REG_STS_BIST_DONE    0x1277\n\n#define    RTL8367C_REG_STS_BIST_RLT0    0x1278\n#define    RTL8367C_STS_BIST_RLT0_OFFSET    0\n#define    RTL8367C_STS_BIST_RLT0_MASK    0x1\n\n#define    RTL8367C_REG_STS_BIST_RLT1    0x1279\n\n#define    RTL8367C_REG_STS_BIST_RLT2    0x127a\n\n#define    RTL8367C_REG_STS_BIST_RLT3    0x127b\n#define    RTL8367C_STS_BIST_RLT3_OFFSET    0\n#define    RTL8367C_STS_BIST_RLT3_MASK    0x3FF\n\n#define    RTL8367C_REG_STS_BIST_RLT4    0x127c\n#define    RTL8367C_STS_BIST_RLT4_OFFSET    0\n#define    RTL8367C_STS_BIST_RLT4_MASK    0x7\n\n#define    RTL8367C_REG_VIAROM_MISR    0x127d\n\n#define    RTL8367C_REG_DRF_BIST_MODE    0x1280\n#define    RTL8367C_DRF_TCAMDEL_OFFSET    15\n#define    RTL8367C_DRF_TCAMDEL_MASK    0x8000\n#define    RTL8367C_CFG_DRF_BIST_MODE_OFFSET    0\n#define    RTL8367C_CFG_DRF_BIST_MODE_MASK    0x7FFF\n\n#define    RTL8367C_REG_STS_DRF_BIST    0x1281\n#define    RTL8367C_STS_DRF_BIST_OFFSET    0\n#define    RTL8367C_STS_DRF_BIST_MASK    0x7FFF\n\n#define    RTL8367C_REG_STS_DRF_BIST_RLT0    0x1282\n#define    RTL8367C_STS_DRF_BIST_RLT0_OFFSET    0\n#define    RTL8367C_STS_DRF_BIST_RLT0_MASK    0x1\n\n#define    RTL8367C_REG_STS_DRF_BIST_RLT1    0x1283\n\n#define    RTL8367C_REG_STS_DRF_BIST_RLT2    0x1284\n\n#define    RTL8367C_REG_STS_DRF_BIST_RLT3    0x1285\n#define    RTL8367C_STS_DRF_BIST_RLT3_OFFSET    0\n#define    RTL8367C_STS_DRF_BIST_RLT3_MASK    0x3FF\n\n#define    RTL8367C_REG_STS_DRF_BIST_RLT4    0x1286\n#define    RTL8367C_STS_DRF_BIST_RLT4_OFFSET    0\n#define    RTL8367C_STS_DRF_BIST_RLT4_MASK    0x7FFF\n\n#define    RTL8367C_REG_RAM_DRF_CTRL    0x1289\n#define    RTL8367C_RAM_DRF_CTRL_OFFSET    0\n#define    RTL8367C_RAM_DRF_CTRL_MASK    0x1\n\n#define    RTL8367C_REG_MIB_RMON_LEN_CTRL    0x128a\n#define    RTL8367C_RX_LENGTH_CTRL_OFFSET    1\n#define    RTL8367C_RX_LENGTH_CTRL_MASK    0x2\n#define    RTL8367C_TX_LENGTH_CTRL_OFFSET    0\n#define    RTL8367C_TX_LENGTH_CTRL_MASK    0x1\n\n#define    RTL8367C_REG_COND0_BISR_OUT0    0x1290\n\n#define    RTL8367C_REG_COND0_BISR_OUT1    0x1291\n\n#define    RTL8367C_REG_COND0_BISR_OUT2    0x1292\n\n#define    RTL8367C_REG_COND0_BISR_OUT3    0x1293\n\n#define    RTL8367C_REG_COND0_BISR_OUT4    0x1294\n#define    RTL8367C_COND0_BISR_OUT4_OFFSET    0\n#define    RTL8367C_COND0_BISR_OUT4_MASK    0x3F\n\n#define    RTL8367C_REG_COND0_BISR_OUT5    0x1295\n#define    RTL8367C_COND0_BISR_OUT5_OFFSET    0\n#define    RTL8367C_COND0_BISR_OUT5_MASK    0x7\n\n#define    RTL8367C_REG_CHG_DUPLEX_CFG    0x1296\n#define    RTL8367C_CHG_COL_CNT_PORT_OFFSET    13\n#define    RTL8367C_CHG_COL_CNT_PORT_MASK    0xE000\n#define    RTL8367C_CHG_COL_CNT_OFFSET    8\n#define    RTL8367C_CHG_COL_CNT_MASK    0x1F00\n#define    RTL8367C_CFG_CHG_DUP_EN_OFFSET    7\n#define    RTL8367C_CFG_CHG_DUP_EN_MASK    0x80\n#define    RTL8367C_CFG_CHG_DUP_THR_OFFSET    2\n#define    RTL8367C_CFG_CHG_DUP_THR_MASK    0x7C\n#define    RTL8367C_CFG_CHG_DUP_CONGEST_OFFSET    1\n#define    RTL8367C_CFG_CHG_DUP_CONGEST_MASK    0x2\n#define    RTL8367C_CFG_CHG_DUP_REF_OFFSET    0\n#define    RTL8367C_CFG_CHG_DUP_REF_MASK    0x1\n\n#define    RTL8367C_REG_COND0_BIST_PASS    0x1297\n#define    RTL8367C_COND0_DRF_BIST_NOFAIL_OFFSET    1\n#define    RTL8367C_COND0_DRF_BIST_NOFAIL_MASK    0x2\n#define    RTL8367C_COND0_BIST_NOFAIL_OFFSET    0\n#define    RTL8367C_COND0_BIST_NOFAIL_MASK    0x1\n\n#define    RTL8367C_REG_COND1_BISR_OUT0    0x1298\n\n#define    RTL8367C_REG_COND1_BISR_OUT1    0x1299\n\n#define    RTL8367C_REG_COND1_BISR_OUT2    0x129a\n\n#define    RTL8367C_REG_COND1_BISR_OUT3    0x129b\n\n#define    RTL8367C_REG_COND1_BISR_OUT4    0x129c\n#define    RTL8367C_COND1_BISR_OUT4_OFFSET    0\n#define    RTL8367C_COND1_BISR_OUT4_MASK    0x3F\n\n#define    RTL8367C_REG_COND1_BISR_OUT5    0x129d\n#define    RTL8367C_COND1_BISR_OUT5_OFFSET    0\n#define    RTL8367C_COND1_BISR_OUT5_MASK    0x7\n\n#define    RTL8367C_REG_COND1_BIST_PASS    0x129f\n#define    RTL8367C_COND1_DRF_BIST_NOFAIL_OFFSET    1\n#define    RTL8367C_COND1_DRF_BIST_NOFAIL_MASK    0x2\n#define    RTL8367C_COND1_BIST_NOFAIL_OFFSET    0\n#define    RTL8367C_COND1_BIST_NOFAIL_MASK    0x1\n\n#define    RTL8367C_REG_EEE_TX_THR_Giga_500M    0x12a0\n\n#define    RTL8367C_REG_EEE_TX_THR_FE    0x12a1\n\n#define    RTL8367C_REG_EEE_MISC    0x12a3\n#define    RTL8367C_EEE_REQ_SET1_OFFSET    13\n#define    RTL8367C_EEE_REQ_SET1_MASK    0x2000\n#define    RTL8367C_EEE_REQ_SET0_OFFSET    12\n#define    RTL8367C_EEE_REQ_SET0_MASK    0x1000\n#define    RTL8367C_EEE_WAKE_SET1_OFFSET    9\n#define    RTL8367C_EEE_WAKE_SET1_MASK    0x200\n#define    RTL8367C_EEE_Wake_SET0_OFFSET    8\n#define    RTL8367C_EEE_Wake_SET0_MASK    0x100\n#define    RTL8367C_EEE_TU_GIGA_500M_OFFSET    4\n#define    RTL8367C_EEE_TU_GIGA_500M_MASK    0x30\n#define    RTL8367C_EEE_TU_100M_OFFSET    2\n#define    RTL8367C_EEE_TU_100M_MASK    0xC\n\n#define    RTL8367C_REG_EEE_GIGA_CTRL0    0x12a4\n#define    RTL8367C_EEE_TW_GIGA_OFFSET    8\n#define    RTL8367C_EEE_TW_GIGA_MASK    0xFF00\n#define    RTL8367C_EEE_TR_GIGA_500M_OFFSET    0\n#define    RTL8367C_EEE_TR_GIGA_500M_MASK    0xFF\n\n#define    RTL8367C_REG_EEE_GIGA_CTRL1    0x12a5\n#define    RTL8367C_EEE_TD_GIGA_500M_OFFSET    8\n#define    RTL8367C_EEE_TD_GIGA_500M_MASK    0xFF00\n#define    RTL8367C_EEE_TP_GIGA_OFFSET    0\n#define    RTL8367C_EEE_TP_GIGA_MASK    0xFF\n\n#define    RTL8367C_REG_EEE_100M_CTRL0    0x12a6\n#define    RTL8367C_EEE_TW_100M_OFFSET    8\n#define    RTL8367C_EEE_TW_100M_MASK    0xFF00\n#define    RTL8367C_EEE_TR_100M_OFFSET    0\n#define    RTL8367C_EEE_TR_100M_MASK    0xFF\n\n#define    RTL8367C_REG_EEE_100M_CTRL1    0x12a7\n#define    RTL8367C_EEE_TD_100M_OFFSET    8\n#define    RTL8367C_EEE_TD_100M_MASK    0xFF00\n#define    RTL8367C_EEE_TP_100M_OFFSET    0\n#define    RTL8367C_EEE_TP_100M_MASK    0xFF\n\n#define    RTL8367C_REG_RX_FC_REG    0x12aa\n#define    RTL8367C_EN_EEE_HALF_DUP_OFFSET    8\n#define    RTL8367C_EN_EEE_HALF_DUP_MASK    0x100\n#define    RTL8367C_RX_PGCNT_OFFSET    0\n#define    RTL8367C_RX_PGCNT_MASK    0xFF\n\n#define    RTL8367C_REG_MAX_FIFO_SIZE    0x12af\n#define    RTL8367C_MAX_FIFO_SIZE_OFFSET    0\n#define    RTL8367C_MAX_FIFO_SIZE_MASK    0xF\n\n#define    RTL8367C_REG_EEEP_RX_RATE_GIGA    0x12b0\n\n#define    RTL8367C_REG_EEEP_RX_RATE_100M    0x12b1\n\n#define    RTL8367C_REG_DUMMY_REG_12_2    0x12b2\n\n#define    RTL8367C_REG_EEEP_TX_RATE_GIGA    0x12b3\n\n#define    RTL8367C_REG_EEEP_TX_RATE_100M    0x12b4\n\n#define    RTL8367C_REG_DUMMY_REG_12_3    0x12b5\n\n#define    RTL8367C_REG_EEEP_GIGA_CTRL0    0x12b6\n#define    RTL8367C_EEEP_TR_GIGA_OFFSET    8\n#define    RTL8367C_EEEP_TR_GIGA_MASK    0xFF00\n#define    RTL8367C_EEEP_RW_GIGA_MST_OFFSET    0\n#define    RTL8367C_EEEP_RW_GIGA_MST_MASK    0xFF\n\n#define    RTL8367C_REG_EEEP_GIGA_CTRL1    0x12b7\n#define    RTL8367C_EEEP_TW_GIGA_OFFSET    8\n#define    RTL8367C_EEEP_TW_GIGA_MASK    0xFF00\n#define    RTL8367C_EEEP_TP_GIGA_OFFSET    0\n#define    RTL8367C_EEEP_TP_GIGA_MASK    0xFF\n\n#define    RTL8367C_REG_EEEP_GIGA_CTRL2    0x12b8\n#define    RTL8367C_EEEP_TXEN_GIGA_OFFSET    12\n#define    RTL8367C_EEEP_TXEN_GIGA_MASK    0x1000\n#define    RTL8367C_EEEP_TU_GIGA_OFFSET    8\n#define    RTL8367C_EEEP_TU_GIGA_MASK    0x300\n#define    RTL8367C_EEEP_TS_GIGA_OFFSET    0\n#define    RTL8367C_EEEP_TS_GIGA_MASK    0xFF\n\n#define    RTL8367C_REG_EEEP_100M_CTRL0    0x12b9\n#define    RTL8367C_EEEP_TR_100M_OFFSET    8\n#define    RTL8367C_EEEP_TR_100M_MASK    0xFF00\n#define    RTL8367C_EEEP_RW_100M_OFFSET    0\n#define    RTL8367C_EEEP_RW_100M_MASK    0xFF\n\n#define    RTL8367C_REG_EEEP_100M_CTRL1    0x12ba\n#define    RTL8367C_EEEP_TW_100M_OFFSET    8\n#define    RTL8367C_EEEP_TW_100M_MASK    0xFF00\n#define    RTL8367C_EEEP_TP_100M_OFFSET    0\n#define    RTL8367C_EEEP_TP_100M_MASK    0xFF\n\n#define    RTL8367C_REG_EEEP_100M_CTRL2    0x12bb\n#define    RTL8367C_EEEP_TXEN_100M_OFFSET    12\n#define    RTL8367C_EEEP_TXEN_100M_MASK    0x1000\n#define    RTL8367C_EEEP_TU_100M_OFFSET    8\n#define    RTL8367C_EEEP_TU_100M_MASK    0x300\n#define    RTL8367C_EEEP_TS_100M_OFFSET    0\n#define    RTL8367C_EEEP_TS_100M_MASK    0xFF\n\n#define    RTL8367C_REG_EEEP_CTRL0    0x12bc\n#define    RTL8367C_EEEP_CTRL0_DUMMY_OFFSET    8\n#define    RTL8367C_EEEP_CTRL0_DUMMY_MASK    0xFF00\n#define    RTL8367C_EEEP_SLEEP_STEP_OFFSET    0\n#define    RTL8367C_EEEP_SLEEP_STEP_MASK    0xFF\n\n#define    RTL8367C_REG_EEEP_CTRL1    0x12bd\n#define    RTL8367C_EEEP_TXR_GIGA_OFFSET    8\n#define    RTL8367C_EEEP_TXR_GIGA_MASK    0xFF00\n#define    RTL8367C_EEEP_TXR_100M_OFFSET    0\n#define    RTL8367C_EEEP_TXR_100M_MASK    0xFF\n\n#define    RTL8367C_REG_BACK_PRESSURE_IPG    0x12be\n#define    RTL8367C_BACK_PRESSURE_IPG_OFFSET    0\n#define    RTL8367C_BACK_PRESSURE_IPG_MASK    0x3\n\n#define    RTL8367C_REG_TX_ESD_LEVEL    0x12bf\n#define    RTL8367C_TX_ESD_LEVEL_MODE_OFFSET    8\n#define    RTL8367C_TX_ESD_LEVEL_MODE_MASK    0x100\n#define    RTL8367C_LEVEL_OFFSET    0\n#define    RTL8367C_LEVEL_MASK    0xFF\n\n#define    RTL8367C_REG_RRCP_CTRL4    0x12e0\n\n#define    RTL8367C_REG_RRCP_CTRL5    0x12e1\n\n#define    RTL8367C_REG_RRCP_CTRL6    0x12e2\n\n#define    RTL8367C_REG_RRCP_CTRL7    0x12e3\n\n#define    RTL8367C_REG_RRCP_CTRL8    0x12e4\n\n#define    RTL8367C_REG_RRCP_CTRL9    0x12e5\n\n#define    RTL8367C_REG_RRCP_CTRL10    0x12e6\n\n#define    RTL8367C_REG_FIELD_SELECTOR0    0x12e7\n#define    RTL8367C_FIELD_SELECTOR0_FORMAT_OFFSET    8\n#define    RTL8367C_FIELD_SELECTOR0_FORMAT_MASK    0x700\n#define    RTL8367C_FIELD_SELECTOR0_OFFSET_OFFSET    0\n#define    RTL8367C_FIELD_SELECTOR0_OFFSET_MASK    0xFF\n\n#define    RTL8367C_REG_FIELD_SELECTOR1    0x12e8\n#define    RTL8367C_FIELD_SELECTOR1_FORMAT_OFFSET    8\n#define    RTL8367C_FIELD_SELECTOR1_FORMAT_MASK    0x700\n#define    RTL8367C_FIELD_SELECTOR1_OFFSET_OFFSET    0\n#define    RTL8367C_FIELD_SELECTOR1_OFFSET_MASK    0xFF\n\n#define    RTL8367C_REG_FIELD_SELECTOR2    0x12e9\n#define    RTL8367C_FIELD_SELECTOR2_FORMAT_OFFSET    8\n#define    RTL8367C_FIELD_SELECTOR2_FORMAT_MASK    0x700\n#define    RTL8367C_FIELD_SELECTOR2_OFFSET_OFFSET    0\n#define    RTL8367C_FIELD_SELECTOR2_OFFSET_MASK    0xFF\n\n#define    RTL8367C_REG_FIELD_SELECTOR3    0x12ea\n#define    RTL8367C_FIELD_SELECTOR3_FORMAT_OFFSET    8\n#define    RTL8367C_FIELD_SELECTOR3_FORMAT_MASK    0x700\n#define    RTL8367C_FIELD_SELECTOR3_OFFSET_OFFSET    0\n#define    RTL8367C_FIELD_SELECTOR3_OFFSET_MASK    0xFF\n\n#define    RTL8367C_REG_FIELD_SELECTOR4    0x12eb\n#define    RTL8367C_FIELD_SELECTOR4_FORMAT_OFFSET    8\n#define    RTL8367C_FIELD_SELECTOR4_FORMAT_MASK    0x700\n#define    RTL8367C_FIELD_SELECTOR4_OFFSET_OFFSET    0\n#define    RTL8367C_FIELD_SELECTOR4_OFFSET_MASK    0xFF\n\n#define    RTL8367C_REG_FIELD_SELECTOR5    0x12ec\n#define    RTL8367C_FIELD_SELECTOR5_FORMAT_OFFSET    8\n#define    RTL8367C_FIELD_SELECTOR5_FORMAT_MASK    0x700\n#define    RTL8367C_FIELD_SELECTOR5_OFFSET_OFFSET    0\n#define    RTL8367C_FIELD_SELECTOR5_OFFSET_MASK    0xFF\n\n#define    RTL8367C_REG_FIELD_SELECTOR6    0x12ed\n#define    RTL8367C_FIELD_SELECTOR6_FORMAT_OFFSET    8\n#define    RTL8367C_FIELD_SELECTOR6_FORMAT_MASK    0x700\n#define    RTL8367C_FIELD_SELECTOR6_OFFSET_OFFSET    0\n#define    RTL8367C_FIELD_SELECTOR6_OFFSET_MASK    0xFF\n\n#define    RTL8367C_REG_FIELD_SELECTOR7    0x12ee\n#define    RTL8367C_FIELD_SELECTOR7_FORMAT_OFFSET    8\n#define    RTL8367C_FIELD_SELECTOR7_FORMAT_MASK    0x700\n#define    RTL8367C_FIELD_SELECTOR7_OFFSET_OFFSET    0\n#define    RTL8367C_FIELD_SELECTOR7_OFFSET_MASK    0xFF\n\n#define    RTL8367C_REG_FIELD_SELECTOR8    0x12ef\n#define    RTL8367C_FIELD_SELECTOR8_FORMAT_OFFSET    8\n#define    RTL8367C_FIELD_SELECTOR8_FORMAT_MASK    0x700\n#define    RTL8367C_FIELD_SELECTOR8_OFFSET_OFFSET    0\n#define    RTL8367C_FIELD_SELECTOR8_OFFSET_MASK    0xFF\n\n#define    RTL8367C_REG_FIELD_SELECTOR9    0x12f0\n#define    RTL8367C_FIELD_SELECTOR9_FORMAT_OFFSET    8\n#define    RTL8367C_FIELD_SELECTOR9_FORMAT_MASK    0x700\n#define    RTL8367C_FIELD_SELECTOR9_OFFSET_OFFSET    0\n#define    RTL8367C_FIELD_SELECTOR9_OFFSET_MASK    0xFF\n\n#define    RTL8367C_REG_FIELD_SELECTOR10    0x12f1\n#define    RTL8367C_FIELD_SELECTOR10_FORMAT_OFFSET    8\n#define    RTL8367C_FIELD_SELECTOR10_FORMAT_MASK    0x700\n#define    RTL8367C_FIELD_SELECTOR10_OFFSET_OFFSET    0\n#define    RTL8367C_FIELD_SELECTOR10_OFFSET_MASK    0xFF\n\n#define    RTL8367C_REG_FIELD_SELECTOR11    0x12f2\n#define    RTL8367C_FIELD_SELECTOR11_FORMAT_OFFSET    8\n#define    RTL8367C_FIELD_SELECTOR11_FORMAT_MASK    0x700\n#define    RTL8367C_FIELD_SELECTOR11_OFFSET_OFFSET    0\n#define    RTL8367C_FIELD_SELECTOR11_OFFSET_MASK    0xFF\n\n#define    RTL8367C_REG_FIELD_SELECTOR12    0x12f3\n#define    RTL8367C_FIELD_SELECTOR12_FORMAT_OFFSET    8\n#define    RTL8367C_FIELD_SELECTOR12_FORMAT_MASK    0x700\n#define    RTL8367C_FIELD_SELECTOR12_OFFSET_OFFSET    0\n#define    RTL8367C_FIELD_SELECTOR12_OFFSET_MASK    0xFF\n\n#define    RTL8367C_REG_FIELD_SELECTOR13    0x12f4\n#define    RTL8367C_FIELD_SELECTOR13_FORMAT_OFFSET    8\n#define    RTL8367C_FIELD_SELECTOR13_FORMAT_MASK    0x700\n#define    RTL8367C_FIELD_SELECTOR13_OFFSET_OFFSET    0\n#define    RTL8367C_FIELD_SELECTOR13_OFFSET_MASK    0xFF\n\n#define    RTL8367C_REG_FIELD_SELECTOR14    0x12f5\n#define    RTL8367C_FIELD_SELECTOR14_FORMAT_OFFSET    8\n#define    RTL8367C_FIELD_SELECTOR14_FORMAT_MASK    0x700\n#define    RTL8367C_FIELD_SELECTOR14_OFFSET_OFFSET    0\n#define    RTL8367C_FIELD_SELECTOR14_OFFSET_MASK    0xFF\n\n#define    RTL8367C_REG_FIELD_SELECTOR15    0x12f6\n#define    RTL8367C_FIELD_SELECTOR15_FORMAT_OFFSET    8\n#define    RTL8367C_FIELD_SELECTOR15_FORMAT_MASK    0x700\n#define    RTL8367C_FIELD_SELECTOR15_OFFSET_OFFSET    0\n#define    RTL8367C_FIELD_SELECTOR15_OFFSET_MASK    0xFF\n\n#define    RTL8367C_REG_HWPKT_GEN_MISC_H    0x12f7\n#define    RTL8367C_PKT_GEN_SUSPEND_P10_8_OFFSET    3\n#define    RTL8367C_PKT_GEN_SUSPEND_P10_8_MASK    0x38\n#define    RTL8367C_PKT_GEN_STATUS_P10_8_OFFSET    0\n#define    RTL8367C_PKT_GEN_STATUS_P10_8_MASK    0x7\n\n#define    RTL8367C_REG_MIRROR_SRC_PMSK    0x12fb\n#define    RTL8367C_MIRROR_SRC_PMSK_OFFSET    0\n#define    RTL8367C_MIRROR_SRC_PMSK_MASK    0x7FF\n\n#define    RTL8367C_REG_EEE_BURSTSIZE    0x12fc\n\n#define    RTL8367C_REG_EEE_IFG_CFG    0x12fd\n#define    RTL8367C_EEE_IFG_CFG_OFFSET    0\n#define    RTL8367C_EEE_IFG_CFG_MASK    0x1\n\n#define    RTL8367C_REG_FPGA_VER_MAC    0x12fe\n\n#define    RTL8367C_REG_HWPKT_GEN_MISC    0x12ff\n#define    RTL8367C_PKT_GEN_SUSPEND_OFFSET    8\n#define    RTL8367C_PKT_GEN_SUSPEND_MASK    0xFF00\n#define    RTL8367C_PKT_GEN_STATUS_OFFSET    0\n#define    RTL8367C_PKT_GEN_STATUS_MASK    0xFF\n\n/* (16'h1300)chip_reg */\n\n#define    RTL8367C_REG_CHIP_NUMBER    0x1300\n\n#define    RTL8367C_REG_CHIP_VER    0x1301\n#define    RTL8367C_VERID_OFFSET    12\n#define    RTL8367C_VERID_MASK    0xF000\n#define    RTL8367C_MCID_OFFSET    8\n#define    RTL8367C_MCID_MASK    0xF00\n#define    RTL8367C_MODEL_ID_OFFSET    4\n#define    RTL8367C_MODEL_ID_MASK    0xF0\n#define    RTL8367C_AFE_VERSION_OFFSET    0\n#define    RTL8367C_AFE_VERSION_MASK    0x1\n\n#define    RTL8367C_REG_CHIP_DEBUG0    0x1303\n#define    RTL8367C_SEL33_EXT2_OFFSET    10\n#define    RTL8367C_SEL33_EXT2_MASK    0x400\n#define    RTL8367C_SEL33_EXT1_OFFSET    9\n#define    RTL8367C_SEL33_EXT1_MASK    0x200\n#define    RTL8367C_SEL33_EXT0_OFFSET    8\n#define    RTL8367C_SEL33_EXT0_MASK    0x100\n#define    RTL8367C_DRI_OTHER_OFFSET    7\n#define    RTL8367C_DRI_OTHER_MASK    0x80\n#define    RTL8367C_DRI_EXT1_RG_OFFSET    6\n#define    RTL8367C_DRI_EXT1_RG_MASK    0x40\n#define    RTL8367C_DRI_EXT0_RG_OFFSET    5\n#define    RTL8367C_DRI_EXT0_RG_MASK    0x20\n#define    RTL8367C_DRI_EXT1_OFFSET    4\n#define    RTL8367C_DRI_EXT1_MASK    0x10\n#define    RTL8367C_DRI_EXT0_OFFSET    3\n#define    RTL8367C_DRI_EXT0_MASK    0x8\n#define    RTL8367C_SLR_OTHER_OFFSET    2\n#define    RTL8367C_SLR_OTHER_MASK    0x4\n#define    RTL8367C_SLR_EXT1_OFFSET    1\n#define    RTL8367C_SLR_EXT1_MASK    0x2\n#define    RTL8367C_SLR_EXT0_OFFSET    0\n#define    RTL8367C_SLR_EXT0_MASK    0x1\n\n#define    RTL8367C_REG_CHIP_DEBUG1    0x1304\n#define    RTL8367C_RG1_DN_OFFSET    12\n#define    RTL8367C_RG1_DN_MASK    0x7000\n#define    RTL8367C_RG1_DP_OFFSET    8\n#define    RTL8367C_RG1_DP_MASK    0x700\n#define    RTL8367C_RG0_DN_OFFSET    4\n#define    RTL8367C_RG0_DN_MASK    0x70\n#define    RTL8367C_RG0_DP_OFFSET    0\n#define    RTL8367C_RG0_DP_MASK    0x7\n\n#define    RTL8367C_REG_DIGITAL_INTERFACE_SELECT    0x1305\n#define    RTL8367C_ORG_COL_OFFSET    15\n#define    RTL8367C_ORG_COL_MASK    0x8000\n#define    RTL8367C_ORG_CRS_OFFSET    14\n#define    RTL8367C_ORG_CRS_MASK    0x4000\n#define    RTL8367C_SKIP_MII_1_RXER_OFFSET    13\n#define    RTL8367C_SKIP_MII_1_RXER_MASK    0x2000\n#define    RTL8367C_SKIP_MII_0_RXER_OFFSET    12\n#define    RTL8367C_SKIP_MII_0_RXER_MASK    0x1000\n#define    RTL8367C_SELECT_GMII_1_OFFSET    4\n#define    RTL8367C_SELECT_GMII_1_MASK    0xF0\n#define    RTL8367C_SELECT_GMII_0_OFFSET    0\n#define    RTL8367C_SELECT_GMII_0_MASK    0xF\n\n#define    RTL8367C_REG_EXT0_RGMXF    0x1306\n#define    RTL8367C_EXT0_RGTX_INV_OFFSET    6\n#define    RTL8367C_EXT0_RGTX_INV_MASK    0x40\n#define    RTL8367C_EXT0_RGRX_INV_OFFSET    5\n#define    RTL8367C_EXT0_RGRX_INV_MASK    0x20\n#define    RTL8367C_EXT0_RGMXF_OFFSET    0\n#define    RTL8367C_EXT0_RGMXF_MASK    0x1F\n\n#define    RTL8367C_REG_EXT1_RGMXF    0x1307\n#define    RTL8367C_EXT1_RGTX_INV_OFFSET    6\n#define    RTL8367C_EXT1_RGTX_INV_MASK    0x40\n#define    RTL8367C_EXT1_RGRX_INV_OFFSET    5\n#define    RTL8367C_EXT1_RGRX_INV_MASK    0x20\n#define    RTL8367C_EXT1_RGMXF_OFFSET    0\n#define    RTL8367C_EXT1_RGMXF_MASK    0x1F\n\n#define    RTL8367C_REG_BISR_CTRL    0x1308\n#define    RTL8367C_BISR_CTRL_OFFSET    0\n#define    RTL8367C_BISR_CTRL_MASK    0x7\n\n#define    RTL8367C_REG_SLF_IF    0x1309\n#define    RTL8367C_LINK_DOWN_CLR_FIFO_OFFSET    7\n#define    RTL8367C_LINK_DOWN_CLR_FIFO_MASK    0x80\n#define    RTL8367C_LOOPBACK_OFFSET    6\n#define    RTL8367C_LOOPBACK_MASK    0x40\n#define    RTL8367C_WATER_LEVEL_OFFSET    4\n#define    RTL8367C_WATER_LEVEL_MASK    0x30\n#define    RTL8367C_SLF_IF_OFFSET    0\n#define    RTL8367C_SLF_IF_MASK    0x3\n\n#define    RTL8367C_REG_I2C_CLOCK_DIV    0x130a\n#define    RTL8367C_I2C_CLOCK_DIV_OFFSET    0\n#define    RTL8367C_I2C_CLOCK_DIV_MASK    0x3FF\n\n#define    RTL8367C_REG_MDX_MDC_DIV    0x130b\n#define    RTL8367C_MDX_MDC_DIV_OFFSET    0\n#define    RTL8367C_MDX_MDC_DIV_MASK    0x3FF\n\n#define    RTL8367C_REG_MISCELLANEOUS_CONFIGURE0    0x130c\n#define    RTL8367C_ADCCKI_FROM_PAD_OFFSET    14\n#define    RTL8367C_ADCCKI_FROM_PAD_MASK    0x4000\n#define    RTL8367C_ADCCKI_EN_OFFSET    13\n#define    RTL8367C_ADCCKI_EN_MASK    0x2000\n#define    RTL8367C_FLASH_ENABLE_OFFSET    12\n#define    RTL8367C_FLASH_ENABLE_MASK    0x1000\n#define    RTL8367C_EEE_ENABLE_OFFSET    11\n#define    RTL8367C_EEE_ENABLE_MASK    0x800\n#define    RTL8367C_NIC_ENABLE_OFFSET    10\n#define    RTL8367C_NIC_ENABLE_MASK    0x400\n#define    RTL8367C_FT_ENABLE_OFFSET    9\n#define    RTL8367C_FT_ENABLE_MASK    0x200\n#define    RTL8367C_OLT_ENABLE_OFFSET    8\n#define    RTL8367C_OLT_ENABLE_MASK    0x100\n#define    RTL8367C_RTCT_EN_OFFSET    7\n#define    RTL8367C_RTCT_EN_MASK    0x80\n#define    RTL8367C_PON_LIGHT_EN_OFFSET    6\n#define    RTL8367C_PON_LIGHT_EN_MASK    0x40\n#define    RTL8367C_DW8051_EN_OFFSET    5\n#define    RTL8367C_DW8051_EN_MASK    0x20\n#define    RTL8367C_AUTOLOAD_EN_OFFSET    4\n#define    RTL8367C_AUTOLOAD_EN_MASK    0x10\n#define    RTL8367C_NRESTORE_EN_OFFSET    3\n#define    RTL8367C_NRESTORE_EN_MASK    0x8\n#define    RTL8367C_DIS_PON_TABLE_INIT_OFFSET    2\n#define    RTL8367C_DIS_PON_TABLE_INIT_MASK    0x4\n#define    RTL8367C_DIS_PON_BIST_OFFSET    1\n#define    RTL8367C_DIS_PON_BIST_MASK    0x2\n#define    RTL8367C_EFUSE_EN_OFFSET    0\n#define    RTL8367C_EFUSE_EN_MASK    0x1\n\n#define    RTL8367C_REG_MISCELLANEOUS_CONFIGURE1    0x130d\n#define    RTL8367C_EEPROM_DEV_ADR_OFFSET    8\n#define    RTL8367C_EEPROM_DEV_ADR_MASK    0x7F00\n#define    RTL8367C_EEPROM_MSB_OFFSET    7\n#define    RTL8367C_EEPROM_MSB_MASK    0x80\n#define    RTL8367C_EEPROM_ADDRESS_16B_OFFSET    6\n#define    RTL8367C_EEPROM_ADDRESS_16B_MASK    0x40\n#define    RTL8367C_EEPROM_DWONLOAD_COMPLETE_OFFSET    3\n#define    RTL8367C_EEPROM_DWONLOAD_COMPLETE_MASK    0x8\n#define    RTL8367C_SPI_SLAVE_EN_OFFSET    2\n#define    RTL8367C_SPI_SLAVE_EN_MASK    0x4\n#define    RTL8367C_SMI_SEL_OFFSET    0\n#define    RTL8367C_SMI_SEL_MASK    0x3\n\n#define    RTL8367C_REG_PHY_AD    0x130f\n#define    RTL8367C_EN_PHY_MAX_POWER_OFFSET    14\n#define    RTL8367C_EN_PHY_MAX_POWER_MASK    0x4000\n#define    RTL8367C_EN_PHY_SEL_DEG_OFFSET    13\n#define    RTL8367C_EN_PHY_SEL_DEG_MASK    0x2000\n#define    RTL8367C_EXTPHY_AD_OFFSET    8\n#define    RTL8367C_EXTPHY_AD_MASK    0x1F00\n#define    RTL8367C_EN_PHY_LOW_POWER_MODE_OFFSET    7\n#define    RTL8367C_EN_PHY_LOW_POWER_MODE_MASK    0x80\n#define    RTL8367C_EN_PHY_GREEN_OFFSET    6\n#define    RTL8367C_EN_PHY_GREEN_MASK    0x40\n#define    RTL8367C_PDNPHY_OFFSET    5\n#define    RTL8367C_PDNPHY_MASK    0x20\n#define    RTL8367C_INTPHY_AD_OFFSET    0\n#define    RTL8367C_INTPHY_AD_MASK    0x1F\n\n#define    RTL8367C_REG_DIGITAL_INTERFACE0_FORCE    0x1310\n#define    RTL8367C_GMII_0_FORCE_OFFSET    12\n#define    RTL8367C_GMII_0_FORCE_MASK    0x1000\n#define    RTL8367C_RGMII_0_FORCE_OFFSET    0\n#define    RTL8367C_RGMII_0_FORCE_MASK    0xFFF\n\n#define    RTL8367C_REG_DIGITAL_INTERFACE1_FORCE    0x1311\n#define    RTL8367C_GMII_1_FORCE_OFFSET    12\n#define    RTL8367C_GMII_1_FORCE_MASK    0x1000\n#define    RTL8367C_RGMII_1_FORCE_OFFSET    0\n#define    RTL8367C_RGMII_1_FORCE_MASK    0xFFF\n\n#define    RTL8367C_REG_MAC0_FORCE_SELECT    0x1312\n#define    RTL8367C_EN_MAC0_FORCE_OFFSET    12\n#define    RTL8367C_EN_MAC0_FORCE_MASK    0x1000\n#define    RTL8367C_MAC0_FORCE_ABLTY_OFFSET    0\n#define    RTL8367C_MAC0_FORCE_ABLTY_MASK    0xFFF\n\n#define    RTL8367C_REG_MAC1_FORCE_SELECT    0x1313\n#define    RTL8367C_EN_MAC1_FORCE_OFFSET    12\n#define    RTL8367C_EN_MAC1_FORCE_MASK    0x1000\n#define    RTL8367C_MAC1_FORCE_ABLTY_OFFSET    0\n#define    RTL8367C_MAC1_FORCE_ABLTY_MASK    0xFFF\n\n#define    RTL8367C_REG_MAC2_FORCE_SELECT    0x1314\n#define    RTL8367C_EN_MAC2_FORCE_OFFSET    12\n#define    RTL8367C_EN_MAC2_FORCE_MASK    0x1000\n#define    RTL8367C_MAC2_FORCE_ABLTY_OFFSET    0\n#define    RTL8367C_MAC2_FORCE_ABLTY_MASK    0xFFF\n\n#define    RTL8367C_REG_MAC3_FORCE_SELECT    0x1315\n#define    RTL8367C_EN_MAC3_FORCE_OFFSET    12\n#define    RTL8367C_EN_MAC3_FORCE_MASK    0x1000\n#define    RTL8367C_MAC3_FORCE_ABLTY_OFFSET    0\n#define    RTL8367C_MAC3_FORCE_ABLTY_MASK    0xFFF\n\n#define    RTL8367C_REG_MAC4_FORCE_SELECT    0x1316\n#define    RTL8367C_EN_MAC4_FORCE_OFFSET    12\n#define    RTL8367C_EN_MAC4_FORCE_MASK    0x1000\n#define    RTL8367C_MAC4_FORCE_ABLTY_OFFSET    0\n#define    RTL8367C_MAC4_FORCE_ABLTY_MASK    0xFFF\n\n#define    RTL8367C_REG_MAC5_FORCE_SELECT    0x1317\n#define    RTL8367C_EN_MAC5_FORCE_OFFSET    12\n#define    RTL8367C_EN_MAC5_FORCE_MASK    0x1000\n#define    RTL8367C_MAC5_FORCE_ABLTY_OFFSET    0\n#define    RTL8367C_MAC5_FORCE_ABLTY_MASK    0xFFF\n\n#define    RTL8367C_REG_MAC6_FORCE_SELECT    0x1318\n#define    RTL8367C_EN_MAC6_FORCE_OFFSET    12\n#define    RTL8367C_EN_MAC6_FORCE_MASK    0x1000\n#define    RTL8367C_MAC6_FORCE_ABLTY_OFFSET    0\n#define    RTL8367C_MAC6_FORCE_ABLTY_MASK    0xFFF\n\n#define    RTL8367C_REG_MAC7_FORCE_SELECT    0x1319\n#define    RTL8367C_EN_MAC7_FORCE_OFFSET    12\n#define    RTL8367C_EN_MAC7_FORCE_MASK    0x1000\n#define    RTL8367C_MAC7_FORCE_ABLTY_OFFSET    0\n#define    RTL8367C_MAC7_FORCE_ABLTY_MASK    0xFFF\n\n#define    RTL8367C_REG_M10_FORCE_SELECT    0x131c\n#define    RTL8367C_EN_M10_FORCE_OFFSET    12\n#define    RTL8367C_EN_M10_FORCE_MASK    0x1000\n#define    RTL8367C_M10_FORCE_ABLTY_OFFSET    0\n#define    RTL8367C_M10_FORCE_ABLTY_MASK    0xFFF\n\n#define    RTL8367C_REG_CHIP_RESET    0x1322\n#define    RTL8367C_GPHY_RESET_OFFSET    6\n#define    RTL8367C_GPHY_RESET_MASK    0x40\n#define    RTL8367C_NIC_RST_OFFSET    5\n#define    RTL8367C_NIC_RST_MASK    0x20\n#define    RTL8367C_DW8051_RST_OFFSET    4\n#define    RTL8367C_DW8051_RST_MASK    0x10\n#define    RTL8367C_SDS_RST_OFFSET    3\n#define    RTL8367C_SDS_RST_MASK    0x8\n#define    RTL8367C_CONFIG_RST_OFFSET    2\n#define    RTL8367C_CONFIG_RST_MASK    0x4\n#define    RTL8367C_SW_RST_OFFSET    1\n#define    RTL8367C_SW_RST_MASK    0x2\n#define    RTL8367C_CHIP_RST_OFFSET    0\n#define    RTL8367C_CHIP_RST_MASK    0x1\n\n#define    RTL8367C_REG_DIGITAL_DEBUG_0    0x1323\n\n#define    RTL8367C_REG_DIGITAL_DEBUG_1    0x1324\n\n#define    RTL8367C_REG_INTERNAL_PHY_MDC_DRIVER    0x1325\n#define    RTL8367C_INTERNAL_PHY_MDC_DRIVER_OFFSET    0\n#define    RTL8367C_INTERNAL_PHY_MDC_DRIVER_MASK    0x3FF\n\n#define    RTL8367C_REG_LINKDOWN_TIME_CTRL    0x1326\n#define    RTL8367C_LINKDOWN_TIME_CFG_OFFSET    9\n#define    RTL8367C_LINKDOWN_TIME_CFG_MASK    0x7E00\n#define    RTL8367C_LINKDOWN_TIME_ENABLE_OFFSET    8\n#define    RTL8367C_LINKDOWN_TIME_ENABLE_MASK    0x100\n#define    RTL8367C_LINKDOWN_TIME_OFFSET    0\n#define    RTL8367C_LINKDOWN_TIME_MASK    0xFF\n\n#define    RTL8367C_REG_PHYACK_TIMEOUT    0x1331\n\n#define    RTL8367C_REG_MDXACK_TIMEOUT    0x1333\n\n#define    RTL8367C_REG_DW8051_RDY    0x1336\n#define    RTL8367C_VIAROM_WRITE_EN_OFFSET    9\n#define    RTL8367C_VIAROM_WRITE_EN_MASK    0x200\n#define    RTL8367C_SPIF_CK2_OFFSET    8\n#define    RTL8367C_SPIF_CK2_MASK    0x100\n#define    RTL8367C_RRCP_MDOE_OFFSET    7\n#define    RTL8367C_RRCP_MDOE_MASK    0x80\n#define    RTL8367C_DW8051_RATE_OFFSET    4\n#define    RTL8367C_DW8051_RATE_MASK    0x70\n#define    RTL8367C_IROM_MSB_OFFSET    2\n#define    RTL8367C_IROM_MSB_MASK    0xC\n#define    RTL8367C_ACS_IROM_ENABLE_OFFSET    1\n#define    RTL8367C_ACS_IROM_ENABLE_MASK    0x2\n#define    RTL8367C_DW8051_READY_OFFSET    0\n#define    RTL8367C_DW8051_READY_MASK    0x1\n\n#define    RTL8367C_REG_BIST_CTRL    0x133c\n#define    RTL8367C_DRF_BIST_DONE_ALL_OFFSET    5\n#define    RTL8367C_DRF_BIST_DONE_ALL_MASK    0x20\n#define    RTL8367C_DRF_BIST_PAUSE_ALL_OFFSET    4\n#define    RTL8367C_DRF_BIST_PAUSE_ALL_MASK    0x10\n#define    RTL8367C_BIST_DOAN_ALL_OFFSET    3\n#define    RTL8367C_BIST_DOAN_ALL_MASK    0x8\n#define    RTL8367C_BIST_PASS_OFFSET    0\n#define    RTL8367C_BIST_PASS_MASK    0x7\n\n#define    RTL8367C_REG_DIAG_MODE2    0x133d\n#define    RTL8367C_DIAG_MODE2_ACTRAM_OFFSET    1\n#define    RTL8367C_DIAG_MODE2_ACTRAM_MASK    0x2\n#define    RTL8367C_DIAG_MODE2_BCAM_ACTION_OFFSET    0\n#define    RTL8367C_DIAG_MODE2_BCAM_ACTION_MASK    0x1\n\n#define    RTL8367C_REG_MDX_PHY_REG0    0x133e\n#define    RTL8367C_PHY_BRD_MASK_OFFSET    4\n#define    RTL8367C_PHY_BRD_MASK_MASK    0x1F0\n#define    RTL8367C_MDX_INDACC_PAGE_OFFSET    0\n#define    RTL8367C_MDX_INDACC_PAGE_MASK    0xF\n\n#define    RTL8367C_REG_MDX_PHY_REG1    0x133f\n#define    RTL8367C_PHY_BRD_MODE_OFFSET    5\n#define    RTL8367C_PHY_BRD_MODE_MASK    0x20\n#define    RTL8367C_BRD_PHYAD_OFFSET    0\n#define    RTL8367C_BRD_PHYAD_MASK    0x1F\n\n#define    RTL8367C_REG_DEBUG_SIGNAL_SELECT_SW    0x1340\n\n#define    RTL8367C_REG_DEBUG_SIGNAL_SELECT_B    0x1341\n#define    RTL8367C_DEBUG_MX_OFFSET    9\n#define    RTL8367C_DEBUG_MX_MASK    0xE00\n#define    RTL8367C_DEBUG_SHIFT_MISC_OFFSET    6\n#define    RTL8367C_DEBUG_SHIFT_MISC_MASK    0x1C0\n#define    RTL8367C_DEBUG_SHIFT_SW_OFFSET    3\n#define    RTL8367C_DEBUG_SHIFT_SW_MASK    0x38\n#define    RTL8367C_DEBUG_SHIFT_GPHY_OFFSET    0\n#define    RTL8367C_DEBUG_SHIFT_GPHY_MASK    0x7\n\n#define    RTL8367C_REG_DEBUG_SIGNAL_I    0x1343\n\n#define    RTL8367C_REG_DEBUG_SIGNAL_H    0x1344\n\n#define    RTL8367C_REG_DBGO_SEL_GPHY    0x1345\n\n#define    RTL8367C_REG_DBGO_SEL_MISC    0x1346\n\n#define    RTL8367C_REG_BYPASS_ABLTY_LOCK    0x1349\n#define    RTL8367C_BYPASS_ABLTY_LOCK_OFFSET    0\n#define    RTL8367C_BYPASS_ABLTY_LOCK_MASK    0xFF\n\n#define    RTL8367C_REG_BYPASS_ABLTY_LOCK_EXT    0x134a\n#define    RTL8367C_BYPASS_P10_ABILIITY_LOCK_OFFSET    3\n#define    RTL8367C_BYPASS_P10_ABILIITY_LOCK_MASK    0x8\n#define    RTL8367C_BYPASS_EXT_ABILITY_LOCK_OFFSET    0\n#define    RTL8367C_BYPASS_EXT_ABILITY_LOCK_MASK    0x7\n\n#define    RTL8367C_REG_ACL_GPIO    0x134f\n#define    RTL8367C_ACL_GPIO_13_OFFSET    13\n#define    RTL8367C_ACL_GPIO_13_MASK    0x2000\n#define    RTL8367C_ACL_GPIO_12_OFFSET    12\n#define    RTL8367C_ACL_GPIO_12_MASK    0x1000\n#define    RTL8367C_ACL_GPIO_11_OFFSET    11\n#define    RTL8367C_ACL_GPIO_11_MASK    0x800\n#define    RTL8367C_ACL_GPIO_10_OFFSET    10\n#define    RTL8367C_ACL_GPIO_10_MASK    0x400\n#define    RTL8367C_ACL_GPIO_9_OFFSET    9\n#define    RTL8367C_ACL_GPIO_9_MASK    0x200\n#define    RTL8367C_ACL_GPIO_8_OFFSET    8\n#define    RTL8367C_ACL_GPIO_8_MASK    0x100\n#define    RTL8367C_ACL_GPIO_7_OFFSET    7\n#define    RTL8367C_ACL_GPIO_7_MASK    0x80\n#define    RTL8367C_ACL_GPIO_6_OFFSET    6\n#define    RTL8367C_ACL_GPIO_6_MASK    0x40\n#define    RTL8367C_ACL_GPIO_5_OFFSET    5\n#define    RTL8367C_ACL_GPIO_5_MASK    0x20\n#define    RTL8367C_ACL_GPIO_4_OFFSET    4\n#define    RTL8367C_ACL_GPIO_4_MASK    0x10\n#define    RTL8367C_ACL_GPIO_3_OFFSET    3\n#define    RTL8367C_ACL_GPIO_3_MASK    0x8\n#define    RTL8367C_ACL_GPIO_2_OFFSET    2\n#define    RTL8367C_ACL_GPIO_2_MASK    0x4\n#define    RTL8367C_ACL_GPIO_1_OFFSET    1\n#define    RTL8367C_ACL_GPIO_1_MASK    0x2\n#define    RTL8367C_ACL_GPIO_0_OFFSET    0\n#define    RTL8367C_ACL_GPIO_0_MASK    0x1\n\n#define    RTL8367C_REG_EN_GPIO    0x1350\n#define    RTL8367C_EN_GPIO_13_OFFSET    13\n#define    RTL8367C_EN_GPIO_13_MASK    0x2000\n#define    RTL8367C_EN_GPIO_12_OFFSET    12\n#define    RTL8367C_EN_GPIO_12_MASK    0x1000\n#define    RTL8367C_EN_GPIO_11_OFFSET    11\n#define    RTL8367C_EN_GPIO_11_MASK    0x800\n#define    RTL8367C_EN_GPIO_10_OFFSET    10\n#define    RTL8367C_EN_GPIO_10_MASK    0x400\n#define    RTL8367C_EN_GPIO_9_OFFSET    9\n#define    RTL8367C_EN_GPIO_9_MASK    0x200\n#define    RTL8367C_EN_GPIO_8_OFFSET    8\n#define    RTL8367C_EN_GPIO_8_MASK    0x100\n#define    RTL8367C_EN_GPIO_7_OFFSET    7\n#define    RTL8367C_EN_GPIO_7_MASK    0x80\n#define    RTL8367C_EN_GPIO_6_OFFSET    6\n#define    RTL8367C_EN_GPIO_6_MASK    0x40\n#define    RTL8367C_EN_GPIO_5_OFFSET    5\n#define    RTL8367C_EN_GPIO_5_MASK    0x20\n#define    RTL8367C_EN_GPIO_4_OFFSET    4\n#define    RTL8367C_EN_GPIO_4_MASK    0x10\n#define    RTL8367C_EN_GPIO_3_OFFSET    3\n#define    RTL8367C_EN_GPIO_3_MASK    0x8\n#define    RTL8367C_EN_GPIO_2_OFFSET    2\n#define    RTL8367C_EN_GPIO_2_MASK    0x4\n#define    RTL8367C_EN_GPIO_1_OFFSET    1\n#define    RTL8367C_EN_GPIO_1_MASK    0x2\n#define    RTL8367C_EN_GPIO_0_OFFSET    0\n#define    RTL8367C_EN_GPIO_0_MASK    0x1\n\n#define    RTL8367C_REG_CFG_MULTI_PIN    0x1351\n#define    RTL8367C_CFG_MULTI_PIN_OFFSET    0\n#define    RTL8367C_CFG_MULTI_PIN_MASK    0x3\n\n#define    RTL8367C_REG_PORT0_STATUS    0x1352\n#define    RTL8367C_PORT0_STATUS_EN_1000_LPI_OFFSET    11\n#define    RTL8367C_PORT0_STATUS_EN_1000_LPI_MASK    0x800\n#define    RTL8367C_PORT0_STATUS_EN_100_LPI_OFFSET    10\n#define    RTL8367C_PORT0_STATUS_EN_100_LPI_MASK    0x400\n#define    RTL8367C_PORT0_STATUS_NWAY_FAULT_OFFSET    9\n#define    RTL8367C_PORT0_STATUS_NWAY_FAULT_MASK    0x200\n#define    RTL8367C_PORT0_STATUS_LINK_ON_MASTER_OFFSET    8\n#define    RTL8367C_PORT0_STATUS_LINK_ON_MASTER_MASK    0x100\n#define    RTL8367C_PORT0_STATUS_NWAY_CAP_OFFSET    7\n#define    RTL8367C_PORT0_STATUS_NWAY_CAP_MASK    0x80\n#define    RTL8367C_PORT0_STATUS_TX_FLOWCTRL_CAP_OFFSET    6\n#define    RTL8367C_PORT0_STATUS_TX_FLOWCTRL_CAP_MASK    0x40\n#define    RTL8367C_PORT0_STATUS_RX_FLOWCTRL_CAP_OFFSET    5\n#define    RTL8367C_PORT0_STATUS_RX_FLOWCTRL_CAP_MASK    0x20\n#define    RTL8367C_PORT0_STATUS_LINK_STATE_OFFSET    4\n#define    RTL8367C_PORT0_STATUS_LINK_STATE_MASK    0x10\n#define    RTL8367C_PORT0_STATUS_FULL_DUPLUX_CAP_OFFSET    2\n#define    RTL8367C_PORT0_STATUS_FULL_DUPLUX_CAP_MASK    0x4\n#define    RTL8367C_PORT0_STATUS_LINK_SPEED_OFFSET    0\n#define    RTL8367C_PORT0_STATUS_LINK_SPEED_MASK    0x3\n\n#define    RTL8367C_REG_PORT1_STATUS    0x1353\n#define    RTL8367C_PORT1_STATUS_EN_1000_LPI_OFFSET    11\n#define    RTL8367C_PORT1_STATUS_EN_1000_LPI_MASK    0x800\n#define    RTL8367C_PORT1_STATUS_EN_100_LPI_OFFSET    10\n#define    RTL8367C_PORT1_STATUS_EN_100_LPI_MASK    0x400\n#define    RTL8367C_PORT1_STATUS_NWAY_FAULT_OFFSET    9\n#define    RTL8367C_PORT1_STATUS_NWAY_FAULT_MASK    0x200\n#define    RTL8367C_PORT1_STATUS_LINK_ON_MASTER_OFFSET    8\n#define    RTL8367C_PORT1_STATUS_LINK_ON_MASTER_MASK    0x100\n#define    RTL8367C_PORT1_STATUS_NWAY_CAP_OFFSET    7\n#define    RTL8367C_PORT1_STATUS_NWAY_CAP_MASK    0x80\n#define    RTL8367C_PORT1_STATUS_TX_FLOWCTRL_CAP_OFFSET    6\n#define    RTL8367C_PORT1_STATUS_TX_FLOWCTRL_CAP_MASK    0x40\n#define    RTL8367C_PORT1_STATUS_RX_FLOWCTRL_CAP_OFFSET    5\n#define    RTL8367C_PORT1_STATUS_RX_FLOWCTRL_CAP_MASK    0x20\n#define    RTL8367C_PORT1_STATUS_LINK_STATE_OFFSET    4\n#define    RTL8367C_PORT1_STATUS_LINK_STATE_MASK    0x10\n#define    RTL8367C_PORT1_STATUS_FULL_DUPLUX_CAP_OFFSET    2\n#define    RTL8367C_PORT1_STATUS_FULL_DUPLUX_CAP_MASK    0x4\n#define    RTL8367C_PORT1_STATUS_LINK_SPEED_OFFSET    0\n#define    RTL8367C_PORT1_STATUS_LINK_SPEED_MASK    0x3\n\n#define    RTL8367C_REG_PORT2_STATUS    0x1354\n#define    RTL8367C_PORT2_STATUS_EN_1000_LPI_OFFSET    11\n#define    RTL8367C_PORT2_STATUS_EN_1000_LPI_MASK    0x800\n#define    RTL8367C_PORT2_STATUS_EN_100_LPI_OFFSET    10\n#define    RTL8367C_PORT2_STATUS_EN_100_LPI_MASK    0x400\n#define    RTL8367C_PORT2_STATUS_NWAY_FAULT_OFFSET    9\n#define    RTL8367C_PORT2_STATUS_NWAY_FAULT_MASK    0x200\n#define    RTL8367C_PORT2_STATUS_LINK_ON_MASTER_OFFSET    8\n#define    RTL8367C_PORT2_STATUS_LINK_ON_MASTER_MASK    0x100\n#define    RTL8367C_PORT2_STATUS_NWAY_CAP_OFFSET    7\n#define    RTL8367C_PORT2_STATUS_NWAY_CAP_MASK    0x80\n#define    RTL8367C_PORT2_STATUS_TX_FLOWCTRL_CAP_OFFSET    6\n#define    RTL8367C_PORT2_STATUS_TX_FLOWCTRL_CAP_MASK    0x40\n#define    RTL8367C_PORT2_STATUS_RX_FLOWCTRL_CAP_OFFSET    5\n#define    RTL8367C_PORT2_STATUS_RX_FLOWCTRL_CAP_MASK    0x20\n#define    RTL8367C_PORT2_STATUS_LINK_STATE_OFFSET    4\n#define    RTL8367C_PORT2_STATUS_LINK_STATE_MASK    0x10\n#define    RTL8367C_PORT2_STATUS_FULL_DUPLUX_CAP_OFFSET    2\n#define    RTL8367C_PORT2_STATUS_FULL_DUPLUX_CAP_MASK    0x4\n#define    RTL8367C_PORT2_STATUS_LINK_SPEED_OFFSET    0\n#define    RTL8367C_PORT2_STATUS_LINK_SPEED_MASK    0x3\n\n#define    RTL8367C_REG_PORT3_STATUS    0x1355\n#define    RTL8367C_PORT3_STATUS_EN_1000_LPI_OFFSET    11\n#define    RTL8367C_PORT3_STATUS_EN_1000_LPI_MASK    0x800\n#define    RTL8367C_PORT3_STATUS_EN_100_LPI_OFFSET    10\n#define    RTL8367C_PORT3_STATUS_EN_100_LPI_MASK    0x400\n#define    RTL8367C_PORT3_STATUS_NWAY_FAULT_OFFSET    9\n#define    RTL8367C_PORT3_STATUS_NWAY_FAULT_MASK    0x200\n#define    RTL8367C_PORT3_STATUS_LINK_ON_MASTER_OFFSET    8\n#define    RTL8367C_PORT3_STATUS_LINK_ON_MASTER_MASK    0x100\n#define    RTL8367C_PORT3_STATUS_NWAY_CAP_OFFSET    7\n#define    RTL8367C_PORT3_STATUS_NWAY_CAP_MASK    0x80\n#define    RTL8367C_PORT3_STATUS_TX_FLOWCTRL_CAP_OFFSET    6\n#define    RTL8367C_PORT3_STATUS_TX_FLOWCTRL_CAP_MASK    0x40\n#define    RTL8367C_PORT3_STATUS_RX_FLOWCTRL_CAP_OFFSET    5\n#define    RTL8367C_PORT3_STATUS_RX_FLOWCTRL_CAP_MASK    0x20\n#define    RTL8367C_PORT3_STATUS_LINK_STATE_OFFSET    4\n#define    RTL8367C_PORT3_STATUS_LINK_STATE_MASK    0x10\n#define    RTL8367C_PORT3_STATUS_FULL_DUPLUX_CAP_OFFSET    2\n#define    RTL8367C_PORT3_STATUS_FULL_DUPLUX_CAP_MASK    0x4\n#define    RTL8367C_PORT3_STATUS_LINK_SPEED_OFFSET    0\n#define    RTL8367C_PORT3_STATUS_LINK_SPEED_MASK    0x3\n\n#define    RTL8367C_REG_PORT4_STATUS    0x1356\n#define    RTL8367C_PORT4_STATUS_EN_1000_LPI_OFFSET    11\n#define    RTL8367C_PORT4_STATUS_EN_1000_LPI_MASK    0x800\n#define    RTL8367C_PORT4_STATUS_EN_100_LPI_OFFSET    10\n#define    RTL8367C_PORT4_STATUS_EN_100_LPI_MASK    0x400\n#define    RTL8367C_PORT4_STATUS_NWAY_FAULT_OFFSET    9\n#define    RTL8367C_PORT4_STATUS_NWAY_FAULT_MASK    0x200\n#define    RTL8367C_PORT4_STATUS_LINK_ON_MASTER_OFFSET    8\n#define    RTL8367C_PORT4_STATUS_LINK_ON_MASTER_MASK    0x100\n#define    RTL8367C_PORT4_STATUS_NWAY_CAP_OFFSET    7\n#define    RTL8367C_PORT4_STATUS_NWAY_CAP_MASK    0x80\n#define    RTL8367C_PORT4_STATUS_TX_FLOWCTRL_CAP_OFFSET    6\n#define    RTL8367C_PORT4_STATUS_TX_FLOWCTRL_CAP_MASK    0x40\n#define    RTL8367C_PORT4_STATUS_RX_FLOWCTRL_CAP_OFFSET    5\n#define    RTL8367C_PORT4_STATUS_RX_FLOWCTRL_CAP_MASK    0x20\n#define    RTL8367C_PORT4_STATUS_LINK_STATE_OFFSET    4\n#define    RTL8367C_PORT4_STATUS_LINK_STATE_MASK    0x10\n#define    RTL8367C_PORT4_STATUS_FULL_DUPLUX_CAP_OFFSET    2\n#define    RTL8367C_PORT4_STATUS_FULL_DUPLUX_CAP_MASK    0x4\n#define    RTL8367C_PORT4_STATUS_LINK_SPEED_OFFSET    0\n#define    RTL8367C_PORT4_STATUS_LINK_SPEED_MASK    0x3\n\n#define    RTL8367C_REG_PORT5_STATUS    0x1357\n#define    RTL8367C_PORT5_STATUS_EN_1000_LPI_OFFSET    11\n#define    RTL8367C_PORT5_STATUS_EN_1000_LPI_MASK    0x800\n#define    RTL8367C_PORT5_STATUS_EN_100_LPI_OFFSET    10\n#define    RTL8367C_PORT5_STATUS_EN_100_LPI_MASK    0x400\n#define    RTL8367C_PORT5_STATUS_NWAY_FAULT_OFFSET    9\n#define    RTL8367C_PORT5_STATUS_NWAY_FAULT_MASK    0x200\n#define    RTL8367C_PORT5_STATUS_LINK_ON_MASTER_OFFSET    8\n#define    RTL8367C_PORT5_STATUS_LINK_ON_MASTER_MASK    0x100\n#define    RTL8367C_PORT5_STATUS_NWAY_CAP_OFFSET    7\n#define    RTL8367C_PORT5_STATUS_NWAY_CAP_MASK    0x80\n#define    RTL8367C_PORT5_STATUS_TX_FLOWCTRL_CAP_OFFSET    6\n#define    RTL8367C_PORT5_STATUS_TX_FLOWCTRL_CAP_MASK    0x40\n#define    RTL8367C_PORT5_STATUS_RX_FLOWCTRL_CAP_OFFSET    5\n#define    RTL8367C_PORT5_STATUS_RX_FLOWCTRL_CAP_MASK    0x20\n#define    RTL8367C_PORT5_STATUS_LINK_STATE_OFFSET    4\n#define    RTL8367C_PORT5_STATUS_LINK_STATE_MASK    0x10\n#define    RTL8367C_PORT5_STATUS_FULL_DUPLUX_CAP_OFFSET    2\n#define    RTL8367C_PORT5_STATUS_FULL_DUPLUX_CAP_MASK    0x4\n#define    RTL8367C_PORT5_STATUS_LINK_SPEED_OFFSET    0\n#define    RTL8367C_PORT5_STATUS_LINK_SPEED_MASK    0x3\n\n#define    RTL8367C_REG_PORT6_STATUS    0x1358\n#define    RTL8367C_PORT6_STATUS_EN_1000_LPI_OFFSET    11\n#define    RTL8367C_PORT6_STATUS_EN_1000_LPI_MASK    0x800\n#define    RTL8367C_PORT6_STATUS_EN_100_LPI_OFFSET    10\n#define    RTL8367C_PORT6_STATUS_EN_100_LPI_MASK    0x400\n#define    RTL8367C_PORT6_STATUS_NWAY_FAULT_OFFSET    9\n#define    RTL8367C_PORT6_STATUS_NWAY_FAULT_MASK    0x200\n#define    RTL8367C_PORT6_STATUS_LINK_ON_MASTER_OFFSET    8\n#define    RTL8367C_PORT6_STATUS_LINK_ON_MASTER_MASK    0x100\n#define    RTL8367C_PORT6_STATUS_NWAY_CAP_OFFSET    7\n#define    RTL8367C_PORT6_STATUS_NWAY_CAP_MASK    0x80\n#define    RTL8367C_PORT6_STATUS_TX_FLOWCTRL_CAP_OFFSET    6\n#define    RTL8367C_PORT6_STATUS_TX_FLOWCTRL_CAP_MASK    0x40\n#define    RTL8367C_PORT6_STATUS_RX_FLOWCTRL_CAP_OFFSET    5\n#define    RTL8367C_PORT6_STATUS_RX_FLOWCTRL_CAP_MASK    0x20\n#define    RTL8367C_PORT6_STATUS_LINK_STATE_OFFSET    4\n#define    RTL8367C_PORT6_STATUS_LINK_STATE_MASK    0x10\n#define    RTL8367C_PORT6_STATUS_FULL_DUPLUX_CAP_OFFSET    2\n#define    RTL8367C_PORT6_STATUS_FULL_DUPLUX_CAP_MASK    0x4\n#define    RTL8367C_PORT6_STATUS_LINK_SPEED_OFFSET    0\n#define    RTL8367C_PORT6_STATUS_LINK_SPEED_MASK    0x3\n\n#define    RTL8367C_REG_PORT7_STATUS    0x1359\n#define    RTL8367C_PORT7_STATUS_EN_1000_LPI_OFFSET    11\n#define    RTL8367C_PORT7_STATUS_EN_1000_LPI_MASK    0x800\n#define    RTL8367C_PORT7_STATUS_EN_100_LPI_OFFSET    10\n#define    RTL8367C_PORT7_STATUS_EN_100_LPI_MASK    0x400\n#define    RTL8367C_PORT7_STATUS_NWAY_FAULT_OFFSET    9\n#define    RTL8367C_PORT7_STATUS_NWAY_FAULT_MASK    0x200\n#define    RTL8367C_PORT7_STATUS_LINK_ON_MASTER_OFFSET    8\n#define    RTL8367C_PORT7_STATUS_LINK_ON_MASTER_MASK    0x100\n#define    RTL8367C_PORT7_STATUS_NWAY_CAP_OFFSET    7\n#define    RTL8367C_PORT7_STATUS_NWAY_CAP_MASK    0x80\n#define    RTL8367C_PORT7_STATUS_TX_FLOWCTRL_CAP_OFFSET    6\n#define    RTL8367C_PORT7_STATUS_TX_FLOWCTRL_CAP_MASK    0x40\n#define    RTL8367C_PORT7_STATUS_RX_FLOWCTRL_CAP_OFFSET    5\n#define    RTL8367C_PORT7_STATUS_RX_FLOWCTRL_CAP_MASK    0x20\n#define    RTL8367C_PORT7_STATUS_LINK_STATE_OFFSET    4\n#define    RTL8367C_PORT7_STATUS_LINK_STATE_MASK    0x10\n#define    RTL8367C_PORT7_STATUS_FULL_DUPLUX_CAP_OFFSET    2\n#define    RTL8367C_PORT7_STATUS_FULL_DUPLUX_CAP_MASK    0x4\n#define    RTL8367C_PORT7_STATUS_LINK_SPEED_OFFSET    0\n#define    RTL8367C_PORT7_STATUS_LINK_SPEED_MASK    0x3\n\n#define    RTL8367C_REG_PORT8_STATUS    0x135a\n#define    RTL8367C_PORT8_STATUS_EN_1000_LPI_OFFSET    11\n#define    RTL8367C_PORT8_STATUS_EN_1000_LPI_MASK    0x800\n#define    RTL8367C_PORT8_STATUS_EN_100_LPI_OFFSET    10\n#define    RTL8367C_PORT8_STATUS_EN_100_LPI_MASK    0x400\n#define    RTL8367C_PORT8_STATUS_NWAY_FAULT_OFFSET    9\n#define    RTL8367C_PORT8_STATUS_NWAY_FAULT_MASK    0x200\n#define    RTL8367C_PORT8_STATUS_LINK_ON_MASTER_OFFSET    8\n#define    RTL8367C_PORT8_STATUS_LINK_ON_MASTER_MASK    0x100\n#define    RTL8367C_PORT8_STATUS_NWAY_CAP_OFFSET    7\n#define    RTL8367C_PORT8_STATUS_NWAY_CAP_MASK    0x80\n#define    RTL8367C_PORT8_STATUS_TX_FLOWCTRL_CAP_OFFSET    6\n#define    RTL8367C_PORT8_STATUS_TX_FLOWCTRL_CAP_MASK    0x40\n#define    RTL8367C_PORT8_STATUS_RX_FLOWCTRL_CAP_OFFSET    5\n#define    RTL8367C_PORT8_STATUS_RX_FLOWCTRL_CAP_MASK    0x20\n#define    RTL8367C_PORT8_STATUS_LINK_STATE_OFFSET    4\n#define    RTL8367C_PORT8_STATUS_LINK_STATE_MASK    0x10\n#define    RTL8367C_PORT8_STATUS_FULL_DUPLUX_CAP_OFFSET    2\n#define    RTL8367C_PORT8_STATUS_FULL_DUPLUX_CAP_MASK    0x4\n#define    RTL8367C_PORT8_STATUS_LINK_SPEED_OFFSET    0\n#define    RTL8367C_PORT8_STATUS_LINK_SPEED_MASK    0x3\n\n#define    RTL8367C_REG_PORT9_STATUS    0x135b\n#define    RTL8367C_PORT9_STATUS_EN_1000_LPI_OFFSET    11\n#define    RTL8367C_PORT9_STATUS_EN_1000_LPI_MASK    0x800\n#define    RTL8367C_PORT9_STATUS_EN_100_LPI_OFFSET    10\n#define    RTL8367C_PORT9_STATUS_EN_100_LPI_MASK    0x400\n#define    RTL8367C_PORT9_STATUS_NWAY_FAULT_OFFSET    9\n#define    RTL8367C_PORT9_STATUS_NWAY_FAULT_MASK    0x200\n#define    RTL8367C_PORT9_STATUS_LINK_ON_MASTER_OFFSET    8\n#define    RTL8367C_PORT9_STATUS_LINK_ON_MASTER_MASK    0x100\n#define    RTL8367C_PORT9_STATUS_NWAY_CAP_OFFSET    7\n#define    RTL8367C_PORT9_STATUS_NWAY_CAP_MASK    0x80\n#define    RTL8367C_PORT9_STATUS_TX_FLOWCTRL_CAP_OFFSET    6\n#define    RTL8367C_PORT9_STATUS_TX_FLOWCTRL_CAP_MASK    0x40\n#define    RTL8367C_PORT9_STATUS_RX_FLOWCTRL_CAP_OFFSET    5\n#define    RTL8367C_PORT9_STATUS_RX_FLOWCTRL_CAP_MASK    0x20\n#define    RTL8367C_PORT9_STATUS_LINK_STATE_OFFSET    4\n#define    RTL8367C_PORT9_STATUS_LINK_STATE_MASK    0x10\n#define    RTL8367C_PORT9_STATUS_FULL_DUPLUX_CAP_OFFSET    2\n#define    RTL8367C_PORT9_STATUS_FULL_DUPLUX_CAP_MASK    0x4\n#define    RTL8367C_PORT9_STATUS_LINK_SPEED_OFFSET    0\n#define    RTL8367C_PORT9_STATUS_LINK_SPEED_MASK    0x3\n\n#define    RTL8367C_REG_PORT10_STATUS    0x135c\n#define    RTL8367C_PORT10_STATUS_EN_1000_LPI_OFFSET    11\n#define    RTL8367C_PORT10_STATUS_EN_1000_LPI_MASK    0x800\n#define    RTL8367C_PORT10_STATUS_EN_100_LPI_OFFSET    10\n#define    RTL8367C_PORT10_STATUS_EN_100_LPI_MASK    0x400\n#define    RTL8367C_PORT10_STATUS_NWAY_FAULT_OFFSET    9\n#define    RTL8367C_PORT10_STATUS_NWAY_FAULT_MASK    0x200\n#define    RTL8367C_PORT10_STATUS_LINK_ON_MASTER_OFFSET    8\n#define    RTL8367C_PORT10_STATUS_LINK_ON_MASTER_MASK    0x100\n#define    RTL8367C_PORT10_STATUS_NWAY_CAP_OFFSET    7\n#define    RTL8367C_PORT10_STATUS_NWAY_CAP_MASK    0x80\n#define    RTL8367C_PORT10_STATUS_TX_FLOWCTRL_CAP_OFFSET    6\n#define    RTL8367C_PORT10_STATUS_TX_FLOWCTRL_CAP_MASK    0x40\n#define    RTL8367C_PORT10_STATUS_RX_FLOWCTRL_CAP_OFFSET    5\n#define    RTL8367C_PORT10_STATUS_RX_FLOWCTRL_CAP_MASK    0x20\n#define    RTL8367C_PORT10_STATUS_LINK_STATE_OFFSET    4\n#define    RTL8367C_PORT10_STATUS_LINK_STATE_MASK    0x10\n#define    RTL8367C_PORT10_STATUS_FULL_DUPLUX_CAP_OFFSET    2\n#define    RTL8367C_PORT10_STATUS_FULL_DUPLUX_CAP_MASK    0x4\n#define    RTL8367C_PORT10_STATUS_LINK_SPEED_OFFSET    0\n#define    RTL8367C_PORT10_STATUS_LINK_SPEED_MASK    0x3\n\n#define    RTL8367C_REG_UPS_CTRL0    0x1362\n#define    RTL8367C_P3_REF_SD_BIT0_OFFSET    8\n#define    RTL8367C_P3_REF_SD_BIT0_MASK    0xFF00\n#define    RTL8367C_P2_REF_SD_OFFSET    0\n#define    RTL8367C_P2_REF_SD_MASK    0xFF\n\n#define    RTL8367C_REG_UPS_CTRL1    0x1363\n#define    RTL8367C_UPS_OUT_OFFSET    8\n#define    RTL8367C_UPS_OUT_MASK    0xFF00\n#define    RTL8367C_UPS_WRITE_PULSE_OFFSET    1\n#define    RTL8367C_UPS_WRITE_PULSE_MASK    0x2\n#define    RTL8367C_UPS_EN_OFFSET    0\n#define    RTL8367C_UPS_EN_MASK    0x1\n\n#define    RTL8367C_REG_UPS_CTRL2    0x1364\n#define    RTL8367C_IGNOE_MAC8_LINK_OFFSET    15\n#define    RTL8367C_IGNOE_MAC8_LINK_MASK    0x8000\n#define    RTL8367C_AGREE_SLEEP_OFFSET    14\n#define    RTL8367C_AGREE_SLEEP_MASK    0x4000\n#define    RTL8367C_WAIT_FOR_AGREEMENT_OFFSET    13\n#define    RTL8367C_WAIT_FOR_AGREEMENT_MASK    0x2000\n#define    RTL8367C_WAKE_UP_BY_LINK_OFFSET    12\n#define    RTL8367C_WAKE_UP_BY_LINK_MASK    0x1000\n#define    RTL8367C_WAKE_UP_BY_PHY_OFFSET    11\n#define    RTL8367C_WAKE_UP_BY_PHY_MASK    0x800\n#define    RTL8367C_SLOW_CLK_TGL_RATE_OFFSET    7\n#define    RTL8367C_SLOW_CLK_TGL_RATE_MASK    0x780\n#define    RTL8367C_PLL_G1_CTRL_EN_OFFSET    6\n#define    RTL8367C_PLL_G1_CTRL_EN_MASK    0x40\n#define    RTL8367C_PLL_G0_CTRL_EN_OFFSET    5\n#define    RTL8367C_PLL_G0_CTRL_EN_MASK    0x20\n#define    RTL8367C_SLOW_DOWN_PLL_EN_OFFSET    4\n#define    RTL8367C_SLOW_DOWN_PLL_EN_MASK    0x10\n#define    RTL8367C_SLOW_DOWN_CLK_EN_OFFSET    3\n#define    RTL8367C_SLOW_DOWN_CLK_EN_MASK    0x8\n#define    RTL8367C_GATING_CLK_SDS_EN_OFFSET    2\n#define    RTL8367C_GATING_CLK_SDS_EN_MASK    0x4\n#define    RTL8367C_GATING_CLK_CHIP_EN_OFFSET    1\n#define    RTL8367C_GATING_CLK_CHIP_EN_MASK    0x2\n#define    RTL8367C_GATING_SW_EN_OFFSET    0\n#define    RTL8367C_GATING_SW_EN_MASK    0x1\n\n#define    RTL8367C_REG_GATING_CLK_1    0x1365\n#define    RTL8367C_ALDPS_MODE_4_OFFSET    15\n#define    RTL8367C_ALDPS_MODE_4_MASK    0x8000\n#define    RTL8367C_ALDPS_MODE_3_OFFSET    14\n#define    RTL8367C_ALDPS_MODE_3_MASK    0x4000\n#define    RTL8367C_ALDPS_MODE_2_OFFSET    13\n#define    RTL8367C_ALDPS_MODE_2_MASK    0x2000\n#define    RTL8367C_ALDPS_MODE_1_OFFSET    12\n#define    RTL8367C_ALDPS_MODE_1_MASK    0x1000\n#define    RTL8367C_ALDPS_MODE_0_OFFSET    11\n#define    RTL8367C_ALDPS_MODE_0_MASK    0x800\n#define    RTL8367C_UPS_DBGO_OFFSET    10\n#define    RTL8367C_UPS_DBGO_MASK    0x400\n#define    RTL8367C_IFMX_AFF_NOT_FF_OUT_OFFSET    9\n#define    RTL8367C_IFMX_AFF_NOT_FF_OUT_MASK    0x200\n#define    RTL8367C_WATER_LEVEL_FD_OFFSET    6\n#define    RTL8367C_WATER_LEVEL_FD_MASK    0x1C0\n#define    RTL8367C_WATER_LEVEL_Y2X_OFFSET    3\n#define    RTL8367C_WATER_LEVEL_Y2X_MASK    0x38\n#define    RTL8367C_WATER_LEVEL_X2Y_2_OFFSET    2\n#define    RTL8367C_WATER_LEVEL_X2Y_2_MASK    0x4\n#define    RTL8367C_IGNOE_MAC10_LINK_OFFSET    1\n#define    RTL8367C_IGNOE_MAC10_LINK_MASK    0x2\n#define    RTL8367C_IGNOE_MAC9_LINK_OFFSET    0\n#define    RTL8367C_IGNOE_MAC9_LINK_MASK    0x1\n\n#define    RTL8367C_REG_UPS_CTRL4    0x1366\n#define    RTL8367C_PROB_EN_OFFSET    6\n#define    RTL8367C_PROB_EN_MASK    0x40\n#define    RTL8367C_PLL_DOWN_OFFSET    1\n#define    RTL8367C_PLL_DOWN_MASK    0x2\n#define    RTL8367C_XTAL_DOWN_OFFSET    0\n#define    RTL8367C_XTAL_DOWN_MASK    0x1\n\n#define    RTL8367C_REG_UPS_CTRL5    0x1367\n#define    RTL8367C_FRC_CPU_ACPT_OFFSET    3\n#define    RTL8367C_FRC_CPU_ACPT_MASK    0x8\n#define    RTL8367C_UPS_CPU_ACPT_OFFSET    2\n#define    RTL8367C_UPS_CPU_ACPT_MASK    0x4\n#define    RTL8367C_UPS_DBG_4_OFFSET    0\n#define    RTL8367C_UPS_DBG_4_MASK    0x3\n\n#define    RTL8367C_REG_UPS_CTRL6    0x1368\n#define    RTL8367C_UPS_CTRL6_OFFSET    0\n#define    RTL8367C_UPS_CTRL6_MASK    0xF\n\n#define    RTL8367C_REG_EFUSE_CMD_70B    0x1369\n\n#define    RTL8367C_REG_EFUSE_CMD    0x1370\n#define    RTL8367C_EFUSE_TIME_OUT_FLAG_OFFSET    3\n#define    RTL8367C_EFUSE_TIME_OUT_FLAG_MASK    0x8\n#define    RTL8367C_EFUSE_ACCESS_BUSY_OFFSET    2\n#define    RTL8367C_EFUSE_ACCESS_BUSY_MASK    0x4\n#define    RTL8367C_EFUSE_COMMAND_EN_OFFSET    1\n#define    RTL8367C_EFUSE_COMMAND_EN_MASK    0x2\n#define    RTL8367C_EFUSE_WR_OFFSET    0\n#define    RTL8367C_EFUSE_WR_MASK    0x1\n\n#define    RTL8367C_REG_EFUSE_ADR    0x1371\n#define    RTL8367C_DUMMY_15_10_OFFSET    8\n#define    RTL8367C_DUMMY_15_10_MASK    0xFF00\n#define    RTL8367C_EFUSE_ADDRESS_OFFSET    0\n#define    RTL8367C_EFUSE_ADDRESS_MASK    0xFF\n\n#define    RTL8367C_REG_EFUSE_WDAT    0x1372\n\n#define    RTL8367C_REG_EFUSE_RDAT    0x1373\n\n#define    RTL8367C_REG_I2C_CTRL    0x1374\n#define    RTL8367C_MDX_MST_FAIL_LAT_OFFSET    1\n#define    RTL8367C_MDX_MST_FAIL_LAT_MASK    0x2\n#define    RTL8367C_MDX_MST_FAIL_CLRPS_OFFSET    0\n#define    RTL8367C_MDX_MST_FAIL_CLRPS_MASK    0x1\n\n#define    RTL8367C_REG_EEE_CFG    0x1375\n#define    RTL8367C_CFG_BYPASS_GATELPTD_OFFSET    11\n#define    RTL8367C_CFG_BYPASS_GATELPTD_MASK    0x800\n#define    RTL8367C_EEE_ABT_ADDR2_OFFSET    6\n#define    RTL8367C_EEE_ABT_ADDR2_MASK    0x7C0\n#define    RTL8367C_EEE_ABT_ADDR1_OFFSET    1\n#define    RTL8367C_EEE_ABT_ADDR1_MASK    0x3E\n#define    RTL8367C_EEE_POLL_EN_OFFSET    0\n#define    RTL8367C_EEE_POLL_EN_MASK    0x1\n\n#define    RTL8367C_REG_EEE_PAGE    0x1376\n\n#define    RTL8367C_REG_EEE_EXT_PAGE    0x1377\n\n#define    RTL8367C_REG_EEE_EN_SPD1000    0x1378\n\n#define    RTL8367C_REG_EEE_EN_SPD100    0x1379\n\n#define    RTL8367C_REG_EEE_LP_SPD1000    0x137a\n\n#define    RTL8367C_REG_EEE_LP_SPD100    0x137b\n\n#define    RTL8367C_REG_DW8051_PRO_REG0    0x13a0\n\n#define    RTL8367C_REG_DW8051_PRO_REG1    0x13a1\n\n#define    RTL8367C_REG_DW8051_PRO_REG2    0x13a2\n\n#define    RTL8367C_REG_DW8051_PRO_REG3    0x13a3\n\n#define    RTL8367C_REG_DW8051_PRO_REG4    0x13a4\n\n#define    RTL8367C_REG_DW8051_PRO_REG5    0x13a5\n\n#define    RTL8367C_REG_DW8051_PRO_REG6    0x13a6\n\n#define    RTL8367C_REG_DW8051_PRO_REG7    0x13a7\n\n#define    RTL8367C_REG_PROTECT_ID    0x13c0\n\n#define    RTL8367C_REG_CHIP_VER_INTL    0x13c1\n#define    RTL8367C_CHIP_VER_INTL_OFFSET    0\n#define    RTL8367C_CHIP_VER_INTL_MASK    0xF\n\n#define    RTL8367C_REG_MAGIC_ID    0x13c2\n\n#define    RTL8367C_REG_DIGITAL_INTERFACE_SELECT_1    0x13c3\n#define    RTL8367C_SKIP_MII_2_RXER_OFFSET    4\n#define    RTL8367C_SKIP_MII_2_RXER_MASK    0x10\n#define    RTL8367C_SELECT_GMII_2_OFFSET    0\n#define    RTL8367C_SELECT_GMII_2_MASK    0xF\n\n#define    RTL8367C_REG_DIGITAL_INTERFACE2_FORCE    0x13c4\n#define    RTL8367C_GMII_2_FORCE_OFFSET    12\n#define    RTL8367C_GMII_2_FORCE_MASK    0x1000\n#define    RTL8367C_RGMII_2_FORCE_OFFSET    0\n#define    RTL8367C_RGMII_2_FORCE_MASK    0xFFF\n\n#define    RTL8367C_REG_EXT2_RGMXF    0x13c5\n#define    RTL8367C_EXT2_RGTX_INV_OFFSET    6\n#define    RTL8367C_EXT2_RGTX_INV_MASK    0x40\n#define    RTL8367C_EXT2_RGRX_INV_OFFSET    5\n#define    RTL8367C_EXT2_RGRX_INV_MASK    0x20\n#define    RTL8367C_EXT2_RGMXF_OFFSET    0\n#define    RTL8367C_EXT2_RGMXF_MASK    0x1F\n\n#define    RTL8367C_REG_ROUTER_UPS_CFG    0x13c6\n#define    RTL8367C_UPS_Status_OFFSET    1\n#define    RTL8367C_UPS_Status_MASK    0x2\n#define    RTL8367C_SoftStart_OFFSET    0\n#define    RTL8367C_SoftStart_MASK    0x1\n\n#define    RTL8367C_REG_CTRL_GPIO    0x13c7\n#define    RTL8367C_CTRL_GPIO_13_OFFSET    13\n#define    RTL8367C_CTRL_GPIO_13_MASK    0x2000\n#define    RTL8367C_CTRL_GPIO_12_OFFSET    12\n#define    RTL8367C_CTRL_GPIO_12_MASK    0x1000\n#define    RTL8367C_CTRL_GPIO_11_OFFSET    11\n#define    RTL8367C_CTRL_GPIO_11_MASK    0x800\n#define    RTL8367C_CTRL_GPIO_10_OFFSET    10\n#define    RTL8367C_CTRL_GPIO_10_MASK    0x400\n#define    RTL8367C_CTRL_GPIO_9_OFFSET    9\n#define    RTL8367C_CTRL_GPIO_9_MASK    0x200\n#define    RTL8367C_CTRL_GPIO_8_OFFSET    8\n#define    RTL8367C_CTRL_GPIO_8_MASK    0x100\n#define    RTL8367C_CTRL_GPIO_7_OFFSET    7\n#define    RTL8367C_CTRL_GPIO_7_MASK    0x80\n#define    RTL8367C_CTRL_GPIO_6_OFFSET    6\n#define    RTL8367C_CTRL_GPIO_6_MASK    0x40\n#define    RTL8367C_CTRL_GPIO_5_OFFSET    5\n#define    RTL8367C_CTRL_GPIO_5_MASK    0x20\n#define    RTL8367C_CTRL_GPIO_4_OFFSET    4\n#define    RTL8367C_CTRL_GPIO_4_MASK    0x10\n#define    RTL8367C_CTRL_GPIO_3_OFFSET    3\n#define    RTL8367C_CTRL_GPIO_3_MASK    0x8\n#define    RTL8367C_CTRL_GPIO_2_OFFSET    2\n#define    RTL8367C_CTRL_GPIO_2_MASK    0x4\n#define    RTL8367C_CTRL_GPIO_1_OFFSET    1\n#define    RTL8367C_CTRL_GPIO_1_MASK    0x2\n#define    RTL8367C_CTRL_GPIO_0_OFFSET    0\n#define    RTL8367C_CTRL_GPIO_0_MASK    0x1\n\n#define    RTL8367C_REG_SEL_GPIO    0x13c8\n#define    RTL8367C_SEL_GPIO_13_OFFSET    13\n#define    RTL8367C_SEL_GPIO_13_MASK    0x2000\n#define    RTL8367C_SEL_GPIO_12_OFFSET    12\n#define    RTL8367C_SEL_GPIO_12_MASK    0x1000\n#define    RTL8367C_SEL_GPIO_11_OFFSET    11\n#define    RTL8367C_SEL_GPIO_11_MASK    0x800\n#define    RTL8367C_SEL_GPIO_10_OFFSET    10\n#define    RTL8367C_SEL_GPIO_10_MASK    0x400\n#define    RTL8367C_SEL_GPIO_9_OFFSET    9\n#define    RTL8367C_SEL_GPIO_9_MASK    0x200\n#define    RTL8367C_SEL_GPIO_8_OFFSET    8\n#define    RTL8367C_SEL_GPIO_8_MASK    0x100\n#define    RTL8367C_SEL_GPIO_7_OFFSET    7\n#define    RTL8367C_SEL_GPIO_7_MASK    0x80\n#define    RTL8367C_SEL_GPIO_6_OFFSET    6\n#define    RTL8367C_SEL_GPIO_6_MASK    0x40\n#define    RTL8367C_SEL_GPIO_5_OFFSET    5\n#define    RTL8367C_SEL_GPIO_5_MASK    0x20\n#define    RTL8367C_SEL_GPIO_4_OFFSET    4\n#define    RTL8367C_SEL_GPIO_4_MASK    0x10\n#define    RTL8367C_SEL_GPIO_3_OFFSET    3\n#define    RTL8367C_SEL_GPIO_3_MASK    0x8\n#define    RTL8367C_SEL_GPIO_2_OFFSET    2\n#define    RTL8367C_SEL_GPIO_2_MASK    0x4\n#define    RTL8367C_SEL_GPIO_1_OFFSET    1\n#define    RTL8367C_SEL_GPIO_1_MASK    0x2\n#define    RTL8367C_SEL_GPIO_0_OFFSET    0\n#define    RTL8367C_SEL_GPIO_0_MASK    0x1\n\n#define    RTL8367C_REG_STATUS_GPIO    0x13c9\n#define    RTL8367C_STATUS_GPIO_OFFSET    0\n#define    RTL8367C_STATUS_GPIO_MASK    0x3FFF\n\n#define    RTL8367C_REG_SYNC_ETH_CFG    0x13e0\n#define    RTL8367C_DUMMY2_OFFSET    9\n#define    RTL8367C_DUMMY2_MASK    0xFE00\n#define    RTL8367C_RFC2819_TYPE_OFFSET    8\n#define    RTL8367C_RFC2819_TYPE_MASK    0x100\n#define    RTL8367C_DUMMY1_OFFSET    7\n#define    RTL8367C_DUMMY1_MASK    0x80\n#define    RTL8367C_FIBER_SYNCE125_L_SEL_OFFSET    6\n#define    RTL8367C_FIBER_SYNCE125_L_SEL_MASK    0x40\n#define    RTL8367C_SYNC_ETH_EN_RTT2_OFFSET    5\n#define    RTL8367C_SYNC_ETH_EN_RTT2_MASK    0x20\n#define    RTL8367C_SYNC_ETH_EN_RTT1_OFFSET    4\n#define    RTL8367C_SYNC_ETH_EN_RTT1_MASK    0x10\n#define    RTL8367C_SYNC_ETH_SEL_DPLL_OFFSET    3\n#define    RTL8367C_SYNC_ETH_SEL_DPLL_MASK    0x8\n#define    RTL8367C_SYNC_ETH_SEL_PHYREF_OFFSET    2\n#define    RTL8367C_SYNC_ETH_SEL_PHYREF_MASK    0x4\n#define    RTL8367C_SYNC_ETH_SEL_XTAL_OFFSET    1\n#define    RTL8367C_SYNC_ETH_SEL_XTAL_MASK    0x2\n#define    RTL8367C_DUMMY0_OFFSET    0\n#define    RTL8367C_DUMMY0_MASK    0x1\n\n#define    RTL8367C_REG_LED_DRI_CFG    0x13e1\n#define    RTL8367C_LED_DRI_CFG_DUMMY_OFFSET    1\n#define    RTL8367C_LED_DRI_CFG_DUMMY_MASK    0xFFFE\n#define    RTL8367C_LED_DRIVING_OFFSET    0\n#define    RTL8367C_LED_DRIVING_MASK    0x1\n\n#define    RTL8367C_REG_CHIP_DEBUG2    0x13e2\n#define    RTL8367C_RG2_DN_OFFSET    6\n#define    RTL8367C_RG2_DN_MASK    0x1C0\n#define    RTL8367C_RG2_DP_OFFSET    3\n#define    RTL8367C_RG2_DP_MASK    0x38\n#define    RTL8367C_DRI_EXT2_RG_OFFSET    2\n#define    RTL8367C_DRI_EXT2_RG_MASK    0x4\n#define    RTL8367C_DRI_EXT2_OFFSET    1\n#define    RTL8367C_DRI_EXT2_MASK    0x2\n#define    RTL8367C_SLR_EXT2_OFFSET    0\n#define    RTL8367C_SLR_EXT2_MASK    0x1\n\n#define    RTL8367C_REG_DIGITAL_DEBUG_2    0x13e3\n\n#define    RTL8367C_REG_FIBER_RTL_OUI_CFG0    0x13e4\n#define    RTL8367C_FIBER_RTL_OUI_CFG0_OFFSET    0\n#define    RTL8367C_FIBER_RTL_OUI_CFG0_MASK    0xFF\n\n#define    RTL8367C_REG_FIBER_RTL_OUI_CFG1    0x13e5\n\n#define    RTL8367C_REG_FIBER_CFG_0    0x13e6\n#define    RTL8367C_REV_NUM_OFFSET    8\n#define    RTL8367C_REV_NUM_MASK    0xF00\n#define    RTL8367C_MODEL_NUM_OFFSET    0\n#define    RTL8367C_MODEL_NUM_MASK    0x3F\n\n#define    RTL8367C_REG_FIBER_CFG_1    0x13e7\n#define    RTL8367C_SDS_FRC_REG4_OFFSET    12\n#define    RTL8367C_SDS_FRC_REG4_MASK    0x1000\n#define    RTL8367C_SDS_FRC_REG4_FIB100_OFFSET    11\n#define    RTL8367C_SDS_FRC_REG4_FIB100_MASK    0x800\n#define    RTL8367C_SEL_MASK_ONL_OFFSET    5\n#define    RTL8367C_SEL_MASK_ONL_MASK    0x20\n#define    RTL8367C_DIS_QUALITY_IN_MASK_OFFSET    4\n#define    RTL8367C_DIS_QUALITY_IN_MASK_MASK    0x10\n#define    RTL8367C_SDS_FRC_MODE_OFFSET    3\n#define    RTL8367C_SDS_FRC_MODE_MASK    0x8\n#define    RTL8367C_SDS_MODE_OFFSET    0\n#define    RTL8367C_SDS_MODE_MASK    0x7\n\n#define    RTL8367C_REG_FIBER_CFG_2    0x13e8\n#define    RTL8367C_SEL_SDET_PS_OFFSET    12\n#define    RTL8367C_SEL_SDET_PS_MASK    0xF000\n#define    RTL8367C_UTP_DIS_RX_OFFSET    10\n#define    RTL8367C_UTP_DIS_RX_MASK    0xC00\n#define    RTL8367C_UTP_FRC_LD_OFFSET    8\n#define    RTL8367C_UTP_FRC_LD_MASK    0x300\n#define    RTL8367C_SDS_RX_DISABLE_OFFSET    6\n#define    RTL8367C_SDS_RX_DISABLE_MASK    0xC0\n#define    RTL8367C_SDS_TX_DISABLE_OFFSET    4\n#define    RTL8367C_SDS_TX_DISABLE_MASK    0x30\n#define    RTL8367C_FIBER_CFG_2_SDS_PWR_ISO_OFFSET    2\n#define    RTL8367C_FIBER_CFG_2_SDS_PWR_ISO_MASK    0xC\n#define    RTL8367C_SDS_FRC_LD_OFFSET    0\n#define    RTL8367C_SDS_FRC_LD_MASK    0x3\n\n#define    RTL8367C_REG_FIBER_CFG_3    0x13e9\n#define    RTL8367C_FIBER_CFG_3_OFFSET    0\n#define    RTL8367C_FIBER_CFG_3_MASK    0xFFF\n\n#define    RTL8367C_REG_FIBER_CFG_4    0x13ea\n\n#define    RTL8367C_REG_UTP_FIB_DET    0x13eb\n#define    RTL8367C_FORCE_SEL_FIBER_OFFSET    14\n#define    RTL8367C_FORCE_SEL_FIBER_MASK    0xC000\n#define    RTL8367C_FIB_FINAL_TIMER_OFFSET    12\n#define    RTL8367C_FIB_FINAL_TIMER_MASK    0x3000\n#define    RTL8367C_FIB_LINK_TIMER_OFFSET    10\n#define    RTL8367C_FIB_LINK_TIMER_MASK    0xC00\n#define    RTL8367C_FIB_SDET_TIMER_OFFSET    8\n#define    RTL8367C_FIB_SDET_TIMER_MASK    0x300\n#define    RTL8367C_UTP_LINK_TIMER_OFFSET    6\n#define    RTL8367C_UTP_LINK_TIMER_MASK    0xC0\n#define    RTL8367C_UTP_SDET_TIMER_OFFSET    4\n#define    RTL8367C_UTP_SDET_TIMER_MASK    0x30\n#define    RTL8367C_FORCE_AUTODET_OFFSET    3\n#define    RTL8367C_FORCE_AUTODET_MASK    0x8\n#define    RTL8367C_AUTODET_FSM_CLR_OFFSET    2\n#define    RTL8367C_AUTODET_FSM_CLR_MASK    0x4\n#define    RTL8367C_UTP_FIRST_OFFSET    1\n#define    RTL8367C_UTP_FIRST_MASK    0x2\n#define    RTL8367C_UTP_FIB_DISAUTODET_OFFSET    0\n#define    RTL8367C_UTP_FIB_DISAUTODET_MASK    0x1\n\n#define    RTL8367C_REG_NRESTORE_MAGIC_NUM    0x13ec\n#define    RTL8367C_NRESTORE_MAGIC_NUM_MASK    0xFFFF\n#define    RTL8367C_EEPROM_PROGRAM_CYCLE_OFFSET    0\n#define    RTL8367C_EEPROM_PROGRAM_CYCLE_MASK    0x3\n\n#define    RTL8367C_REG_MAC_ACTIVE    0x13ee\n#define    RTL8367C_MAC_ACTIVE_H_OFFSET    9\n#define    RTL8367C_MAC_ACTIVE_H_MASK    0xE00\n#define    RTL8367C_FORCE_MAC_ACTIVE_OFFSET    8\n#define    RTL8367C_FORCE_MAC_ACTIVE_MASK    0x100\n#define    RTL8367C_MAC_ACTIVE_OFFSET    0\n#define    RTL8367C_MAC_ACTIVE_MASK    0xFF\n\n#define    RTL8367C_REG_SERDES_RESULT    0x13ef\n#define    RTL8367C_FIB100_DET_1_OFFSET    12\n#define    RTL8367C_FIB100_DET_1_MASK    0x1000\n#define    RTL8367C_FIB_ISO_1_OFFSET    11\n#define    RTL8367C_FIB_ISO_1_MASK    0x800\n#define    RTL8367C_SDS_ANFAULT_1_OFFSET    10\n#define    RTL8367C_SDS_ANFAULT_1_MASK    0x400\n#define    RTL8367C_SDS_INTB_1_OFFSET    9\n#define    RTL8367C_SDS_INTB_1_MASK    0x200\n#define    RTL8367C_SDS_LINK_OK_1_OFFSET    8\n#define    RTL8367C_SDS_LINK_OK_1_MASK    0x100\n#define    RTL8367C_FIB100_DET_OFFSET    4\n#define    RTL8367C_FIB100_DET_MASK    0x10\n#define    RTL8367C_FIB_ISO_OFFSET    3\n#define    RTL8367C_FIB_ISO_MASK    0x8\n#define    RTL8367C_SDS_ANFAULT_OFFSET    2\n#define    RTL8367C_SDS_ANFAULT_MASK    0x4\n#define    RTL8367C_SDS_INTB_OFFSET    1\n#define    RTL8367C_SDS_INTB_MASK    0x2\n#define    RTL8367C_SDS_LINK_OK_OFFSET    0\n#define    RTL8367C_SDS_LINK_OK_MASK    0x1\n\n#define    RTL8367C_REG_CHIP_ECO    0x13f0\n#define    RTL8367C_CFG_CHIP_ECO_OFFSET    1\n#define    RTL8367C_CFG_CHIP_ECO_MASK    0xFFFE\n#define    RTL8367C_CFG_CKOUTEN_OFFSET    0\n#define    RTL8367C_CFG_CKOUTEN_MASK    0x1\n\n#define    RTL8367C_REG_WAKELPI_SLOT_PRD    0x13f1\n#define    RTL8367C_WAKELPI_SLOT_PRD_OFFSET    0\n#define    RTL8367C_WAKELPI_SLOT_PRD_MASK    0x1F\n\n#define    RTL8367C_REG_WAKELPI_SLOT_PG0    0x13f2\n#define    RTL8367C_WAKELPI_SLOT_P1_OFFSET    8\n#define    RTL8367C_WAKELPI_SLOT_P1_MASK    0x1F00\n#define    RTL8367C_WAKELPI_SLOT_P0_OFFSET    0\n#define    RTL8367C_WAKELPI_SLOT_P0_MASK    0x1F\n\n#define    RTL8367C_REG_WAKELPI_SLOT_PG1    0x13f3\n#define    RTL8367C_WAKELPI_SLOT_P3_OFFSET    8\n#define    RTL8367C_WAKELPI_SLOT_P3_MASK    0x1F00\n#define    RTL8367C_WAKELPI_SLOT_P2_OFFSET    0\n#define    RTL8367C_WAKELPI_SLOT_P2_MASK    0x1F\n\n#define    RTL8367C_REG_WAKELPI_SLOT_PG2    0x13f4\n#define    RTL8367C_WAKELPI_SLOT_P5_OFFSET    8\n#define    RTL8367C_WAKELPI_SLOT_P5_MASK    0x1F00\n#define    RTL8367C_WAKELPI_SLOT_P4_OFFSET    0\n#define    RTL8367C_WAKELPI_SLOT_P4_MASK    0x1F\n\n#define    RTL8367C_REG_WAKELPI_SLOT_PG3    0x13f5\n#define    RTL8367C_WAKELPI_SLOT_P7_OFFSET    8\n#define    RTL8367C_WAKELPI_SLOT_P7_MASK    0x1F00\n#define    RTL8367C_WAKELPI_SLOT_P6_OFFSET    0\n#define    RTL8367C_WAKELPI_SLOT_P6_MASK    0x1F\n\n#define    RTL8367C_REG_SYNC_FIFO_0    0x13f6\n#define    RTL8367C_SYNC_FIFO_TX_OFFSET    8\n#define    RTL8367C_SYNC_FIFO_TX_MASK    0x700\n#define    RTL8367C_SYNC_FIFO_RX_OFFSET    0\n#define    RTL8367C_SYNC_FIFO_RX_MASK    0xFF\n\n#define    RTL8367C_REG_SYNC_FIFO_1    0x13f7\n#define    RTL8367C_SYNC_FIFO_RX_ERR_P10_8_OFFSET    11\n#define    RTL8367C_SYNC_FIFO_RX_ERR_P10_8_MASK    0x3800\n#define    RTL8367C_SYNC_FIFO_TX_ERR_OFFSET    8\n#define    RTL8367C_SYNC_FIFO_TX_ERR_MASK    0x700\n#define    RTL8367C_SYNC_FIFO_RX_ERR_OFFSET    0\n#define    RTL8367C_SYNC_FIFO_RX_ERR_MASK    0xFF\n\n#define    RTL8367C_REG_RGM_EEE    0x13f8\n#define    RTL8367C_EXT2_PAD_STOP_EN_OFFSET    14\n#define    RTL8367C_EXT2_PAD_STOP_EN_MASK    0x4000\n#define    RTL8367C_EXT1_PAD_STOP_EN_OFFSET    13\n#define    RTL8367C_EXT1_PAD_STOP_EN_MASK    0x2000\n#define    RTL8367C_EXT0_PAD_STOP_EN_OFFSET    12\n#define    RTL8367C_EXT0_PAD_STOP_EN_MASK    0x1000\n#define    RTL8367C_EXT2_CYCLE_PAD_OFFSET    8\n#define    RTL8367C_EXT2_CYCLE_PAD_MASK    0xF00\n#define    RTL8367C_EXT1_CYCLE_PAD_OFFSET    4\n#define    RTL8367C_EXT1_CYCLE_PAD_MASK    0xF0\n#define    RTL8367C_EXT0_CYCLE_PAD_OFFSET    0\n#define    RTL8367C_EXT0_CYCLE_PAD_MASK    0xF\n\n#define    RTL8367C_REG_EXT_TXC_DLY    0x13f9\n#define    RTL8367C_EXT1_GMII_TX_DELAY_OFFSET    12\n#define    RTL8367C_EXT1_GMII_TX_DELAY_MASK    0x7000\n#define    RTL8367C_EXT0_GMII_TX_DELAY_OFFSET    9\n#define    RTL8367C_EXT0_GMII_TX_DELAY_MASK    0xE00\n#define    RTL8367C_EXT2_RGMII_TX_DELAY_OFFSET    6\n#define    RTL8367C_EXT2_RGMII_TX_DELAY_MASK    0x1C0\n#define    RTL8367C_EXT1_RGMII_TX_DELAY_OFFSET    3\n#define    RTL8367C_EXT1_RGMII_TX_DELAY_MASK    0x38\n#define    RTL8367C_EXT0_RGMII_TX_DELAY_OFFSET    0\n#define    RTL8367C_EXT0_RGMII_TX_DELAY_MASK    0x7\n\n#define    RTL8367C_REG_IO_MISC_CTRL    0x13fa\n#define    RTL8367C_IO_BUZZER_EN_OFFSET    3\n#define    RTL8367C_IO_BUZZER_EN_MASK    0x8\n#define    RTL8367C_IO_INTRPT_EN_OFFSET    2\n#define    RTL8367C_IO_INTRPT_EN_MASK    0x4\n#define    RTL8367C_IO_NRESTORE_EN_OFFSET    1\n#define    RTL8367C_IO_NRESTORE_EN_MASK    0x2\n#define    RTL8367C_IO_UART_EN_OFFSET    0\n#define    RTL8367C_IO_UART_EN_MASK    0x1\n\n#define    RTL8367C_REG_CHIP_DUMMY_NO    0x13fb\n#define    RTL8367C_CHIP_DUMMY_NO_OFFSET    0\n#define    RTL8367C_CHIP_DUMMY_NO_MASK    0xF\n\n#define    RTL8367C_REG_RC_CALIB_CFG    0x13fc\n#define    RTL8367C_TRIG_BURN_EFUSE_OFFSET    9\n#define    RTL8367C_TRIG_BURN_EFUSE_MASK    0x200\n#define    RTL8367C_AMP_CALIB_FAIL_OFFSET    8\n#define    RTL8367C_AMP_CALIB_FAIL_MASK    0x100\n#define    RTL8367C_R_CALIB_FAIL_OFFSET    7\n#define    RTL8367C_R_CALIB_FAIL_MASK    0x80\n#define    RTL8367C_CFG_CALIB_MODE_OFFSET    6\n#define    RTL8367C_CFG_CALIB_MODE_MASK    0x40\n#define    RTL8367C_CENTER_PORT_SEL_OFFSET    3\n#define    RTL8367C_CENTER_PORT_SEL_MASK    0x38\n#define    RTL8367C_CALIB_FINISH_OFFSET    2\n#define    RTL8367C_CALIB_FINISH_MASK    0x4\n#define    RTL8367C_CFG_CALIB_OPTION_OFFSET    1\n#define    RTL8367C_CFG_CALIB_OPTION_MASK    0x2\n#define    RTL8367C_CFG_CALIB_EN_OFFSET    0\n#define    RTL8367C_CFG_CALIB_EN_MASK    0x1\n\n#define    RTL8367C_REG_WAKELPI_SLOT_PG4    0x13fd\n#define    RTL8367C_WAKELPI_SLOT_P9_OFFSET    8\n#define    RTL8367C_WAKELPI_SLOT_P9_MASK    0x1F00\n#define    RTL8367C_WAKELPI_SLOT_P8_OFFSET    0\n#define    RTL8367C_WAKELPI_SLOT_P8_MASK    0x1F\n\n#define    RTL8367C_REG_WAKELPI_SLOT_PG5    0x13fe\n#define    RTL8367C_WAKELPI_SLOT_PG5_OFFSET    0\n#define    RTL8367C_WAKELPI_SLOT_PG5_MASK    0x1F\n\n/* (16'h1400)mtrpool_reg */\n\n#define    RTL8367C_REG_METER0_RATE_CTRL0    0x1400\n\n#define    RTL8367C_REG_METER0_RATE_CTRL1    0x1401\n#define    RTL8367C_METER0_RATE_CTRL1_OFFSET    0\n#define    RTL8367C_METER0_RATE_CTRL1_MASK    0x7\n\n#define    RTL8367C_REG_METER1_RATE_CTRL0    0x1402\n\n#define    RTL8367C_REG_METER1_RATE_CTRL1    0x1403\n#define    RTL8367C_METER1_RATE_CTRL1_OFFSET    0\n#define    RTL8367C_METER1_RATE_CTRL1_MASK    0x7\n\n#define    RTL8367C_REG_METER2_RATE_CTRL0    0x1404\n\n#define    RTL8367C_REG_METER2_RATE_CTRL1    0x1405\n#define    RTL8367C_METER2_RATE_CTRL1_OFFSET    0\n#define    RTL8367C_METER2_RATE_CTRL1_MASK    0x7\n\n#define    RTL8367C_REG_METER3_RATE_CTRL0    0x1406\n\n#define    RTL8367C_REG_METER3_RATE_CTRL1    0x1407\n#define    RTL8367C_METER3_RATE_CTRL1_OFFSET    0\n#define    RTL8367C_METER3_RATE_CTRL1_MASK    0x7\n\n#define    RTL8367C_REG_METER4_RATE_CTRL0    0x1408\n\n#define    RTL8367C_REG_METER4_RATE_CTRL1    0x1409\n#define    RTL8367C_METER4_RATE_CTRL1_OFFSET    0\n#define    RTL8367C_METER4_RATE_CTRL1_MASK    0x7\n\n#define    RTL8367C_REG_METER5_RATE_CTRL0    0x140a\n\n#define    RTL8367C_REG_METER5_RATE_CTRL1    0x140b\n#define    RTL8367C_METER5_RATE_CTRL1_OFFSET    0\n#define    RTL8367C_METER5_RATE_CTRL1_MASK    0x7\n\n#define    RTL8367C_REG_METER6_RATE_CTRL0    0x140c\n\n#define    RTL8367C_REG_METER6_RATE_CTRL1    0x140d\n#define    RTL8367C_METER6_RATE_CTRL1_OFFSET    0\n#define    RTL8367C_METER6_RATE_CTRL1_MASK    0x7\n\n#define    RTL8367C_REG_METER7_RATE_CTRL0    0x140e\n\n#define    RTL8367C_REG_METER7_RATE_CTRL1    0x140f\n#define    RTL8367C_METER7_RATE_CTRL1_OFFSET    0\n#define    RTL8367C_METER7_RATE_CTRL1_MASK    0x7\n\n#define    RTL8367C_REG_METER8_RATE_CTRL0    0x1410\n\n#define    RTL8367C_REG_METER8_RATE_CTRL1    0x1411\n#define    RTL8367C_METER8_RATE_CTRL1_OFFSET    0\n#define    RTL8367C_METER8_RATE_CTRL1_MASK    0x7\n\n#define    RTL8367C_REG_METER9_RATE_CTRL0    0x1412\n\n#define    RTL8367C_REG_METER9_RATE_CTRL1    0x1413\n#define    RTL8367C_METER9_RATE_CTRL1_OFFSET    0\n#define    RTL8367C_METER9_RATE_CTRL1_MASK    0x7\n\n#define    RTL8367C_REG_METER10_RATE_CTRL0    0x1414\n\n#define    RTL8367C_REG_METER10_RATE_CTRL1    0x1415\n#define    RTL8367C_METER10_RATE_CTRL1_OFFSET    0\n#define    RTL8367C_METER10_RATE_CTRL1_MASK    0x7\n\n#define    RTL8367C_REG_METER11_RATE_CTRL0    0x1416\n\n#define    RTL8367C_REG_METER11_RATE_CTRL1    0x1417\n#define    RTL8367C_METER11_RATE_CTRL1_OFFSET    0\n#define    RTL8367C_METER11_RATE_CTRL1_MASK    0x7\n\n#define    RTL8367C_REG_METER12_RATE_CTRL0    0x1418\n\n#define    RTL8367C_REG_METER12_RATE_CTRL1    0x1419\n#define    RTL8367C_METER12_RATE_CTRL1_OFFSET    0\n#define    RTL8367C_METER12_RATE_CTRL1_MASK    0x7\n\n#define    RTL8367C_REG_METER13_RATE_CTRL0    0x141a\n\n#define    RTL8367C_REG_METER13_RATE_CTRL1    0x141b\n#define    RTL8367C_METER13_RATE_CTRL1_OFFSET    0\n#define    RTL8367C_METER13_RATE_CTRL1_MASK    0x7\n\n#define    RTL8367C_REG_METER14_RATE_CTRL0    0x141c\n\n#define    RTL8367C_REG_METER14_RATE_CTRL1    0x141d\n#define    RTL8367C_METER14_RATE_CTRL1_OFFSET    0\n#define    RTL8367C_METER14_RATE_CTRL1_MASK    0x7\n\n#define    RTL8367C_REG_METER15_RATE_CTRL0    0x141e\n\n#define    RTL8367C_REG_METER15_RATE_CTRL1    0x141f\n#define    RTL8367C_METER15_RATE_CTRL1_OFFSET    0\n#define    RTL8367C_METER15_RATE_CTRL1_MASK    0x7\n\n#define    RTL8367C_REG_METER16_RATE_CTRL0    0x1420\n\n#define    RTL8367C_REG_METER16_RATE_CTRL1    0x1421\n#define    RTL8367C_METER16_RATE_CTRL1_OFFSET    0\n#define    RTL8367C_METER16_RATE_CTRL1_MASK    0x7\n\n#define    RTL8367C_REG_METER17_RATE_CTRL0    0x1422\n\n#define    RTL8367C_REG_METER17_RATE_CTRL1    0x1423\n#define    RTL8367C_METER17_RATE_CTRL1_OFFSET    0\n#define    RTL8367C_METER17_RATE_CTRL1_MASK    0x7\n\n#define    RTL8367C_REG_METER18_RATE_CTRL0    0x1424\n\n#define    RTL8367C_REG_METER18_RATE_CTRL1    0x1425\n#define    RTL8367C_METER18_RATE_CTRL1_OFFSET    0\n#define    RTL8367C_METER18_RATE_CTRL1_MASK    0x7\n\n#define    RTL8367C_REG_METER19_RATE_CTRL0    0x1426\n\n#define    RTL8367C_REG_METER19_RATE_CTRL1    0x1427\n#define    RTL8367C_METER19_RATE_CTRL1_OFFSET    0\n#define    RTL8367C_METER19_RATE_CTRL1_MASK    0x7\n\n#define    RTL8367C_REG_METER20_RATE_CTRL0    0x1428\n\n#define    RTL8367C_REG_METER20_RATE_CTRL1    0x1429\n#define    RTL8367C_METER20_RATE_CTRL1_OFFSET    0\n#define    RTL8367C_METER20_RATE_CTRL1_MASK    0x7\n\n#define    RTL8367C_REG_METER21_RATE_CTRL0    0x142a\n\n#define    RTL8367C_REG_METER21_RATE_CTRL1    0x142b\n#define    RTL8367C_METER21_RATE_CTRL1_OFFSET    0\n#define    RTL8367C_METER21_RATE_CTRL1_MASK    0x7\n\n#define    RTL8367C_REG_METER22_RATE_CTRL0    0x142c\n\n#define    RTL8367C_REG_METER22_RATE_CTRL1    0x142d\n#define    RTL8367C_METER22_RATE_CTRL1_OFFSET    0\n#define    RTL8367C_METER22_RATE_CTRL1_MASK    0x7\n\n#define    RTL8367C_REG_METER23_RATE_CTRL0    0x142e\n\n#define    RTL8367C_REG_METER23_RATE_CTRL1    0x142f\n#define    RTL8367C_METER23_RATE_CTRL1_OFFSET    0\n#define    RTL8367C_METER23_RATE_CTRL1_MASK    0x7\n\n#define    RTL8367C_REG_METER24_RATE_CTRL0    0x1430\n\n#define    RTL8367C_REG_METER24_RATE_CTRL1    0x1431\n#define    RTL8367C_METER24_RATE_CTRL1_OFFSET    0\n#define    RTL8367C_METER24_RATE_CTRL1_MASK    0x7\n\n#define    RTL8367C_REG_METER25_RATE_CTRL0    0x1432\n\n#define    RTL8367C_REG_METER25_RATE_CTRL1    0x1433\n#define    RTL8367C_METER25_RATE_CTRL1_OFFSET    0\n#define    RTL8367C_METER25_RATE_CTRL1_MASK    0x7\n\n#define    RTL8367C_REG_METER26_RATE_CTRL0    0x1434\n\n#define    RTL8367C_REG_METER26_RATE_CTRL1    0x1435\n#define    RTL8367C_METER26_RATE_CTRL1_OFFSET    0\n#define    RTL8367C_METER26_RATE_CTRL1_MASK    0x7\n\n#define    RTL8367C_REG_METER27_RATE_CTRL0    0x1436\n\n#define    RTL8367C_REG_METER27_RATE_CTRL1    0x1437\n#define    RTL8367C_METER27_RATE_CTRL1_OFFSET    0\n#define    RTL8367C_METER27_RATE_CTRL1_MASK    0x7\n\n#define    RTL8367C_REG_METER28_RATE_CTRL0    0x1438\n\n#define    RTL8367C_REG_METER28_RATE_CTRL1    0x1439\n#define    RTL8367C_METER28_RATE_CTRL1_OFFSET    0\n#define    RTL8367C_METER28_RATE_CTRL1_MASK    0x7\n\n#define    RTL8367C_REG_METER29_RATE_CTRL0    0x143a\n\n#define    RTL8367C_REG_METER29_RATE_CTRL1    0x143b\n#define    RTL8367C_METER29_RATE_CTRL1_OFFSET    0\n#define    RTL8367C_METER29_RATE_CTRL1_MASK    0x7\n\n#define    RTL8367C_REG_METER30_RATE_CTRL0    0x143c\n\n#define    RTL8367C_REG_METER30_RATE_CTRL1    0x143d\n#define    RTL8367C_METER30_RATE_CTRL1_OFFSET    0\n#define    RTL8367C_METER30_RATE_CTRL1_MASK    0x7\n\n#define    RTL8367C_REG_METER31_RATE_CTRL0    0x143e\n\n#define    RTL8367C_REG_METER31_RATE_CTRL1    0x143f\n#define    RTL8367C_METER31_RATE_CTRL1_OFFSET    0\n#define    RTL8367C_METER31_RATE_CTRL1_MASK    0x7\n\n#define    RTL8367C_REG_METER_MODE_SETTING0    0x1440\n\n#define    RTL8367C_REG_METER_MODE_SETTING1    0x1441\n\n#define    RTL8367C_REG_METER_MODE_TOKEN_CFG    0x1442\n#define    RTL8367C_METER_MODE_TOKEN_CFG_OFFSET    0\n#define    RTL8367C_METER_MODE_TOKEN_CFG_MASK    0x7FF\n\n#define    RTL8367C_REG_METER0_BUCKET_SIZE    0x1600\n\n#define    RTL8367C_REG_METER1_BUCKET_SIZE    0x1601\n\n#define    RTL8367C_REG_METER2_BUCKET_SIZE    0x1602\n\n#define    RTL8367C_REG_METER3_BUCKET_SIZE    0x1603\n\n#define    RTL8367C_REG_METER4_BUCKET_SIZE    0x1604\n\n#define    RTL8367C_REG_METER5_BUCKET_SIZE    0x1605\n\n#define    RTL8367C_REG_METER6_BUCKET_SIZE    0x1606\n\n#define    RTL8367C_REG_METER7_BUCKET_SIZE    0x1607\n\n#define    RTL8367C_REG_METER8_BUCKET_SIZE    0x1608\n\n#define    RTL8367C_REG_METER9_BUCKET_SIZE    0x1609\n\n#define    RTL8367C_REG_METER10_BUCKET_SIZE    0x160a\n\n#define    RTL8367C_REG_METER11_BUCKET_SIZE    0x160b\n\n#define    RTL8367C_REG_METER12_BUCKET_SIZE    0x160c\n\n#define    RTL8367C_REG_METER13_BUCKET_SIZE    0x160d\n\n#define    RTL8367C_REG_METER14_BUCKET_SIZE    0x160e\n\n#define    RTL8367C_REG_METER15_BUCKET_SIZE    0x160f\n\n#define    RTL8367C_REG_METER16_BUCKET_SIZE    0x1610\n\n#define    RTL8367C_REG_METER17_BUCKET_SIZE    0x1611\n\n#define    RTL8367C_REG_METER18_BUCKET_SIZE    0x1612\n\n#define    RTL8367C_REG_METER19_BUCKET_SIZE    0x1613\n\n#define    RTL8367C_REG_METER20_BUCKET_SIZE    0x1614\n\n#define    RTL8367C_REG_METER21_BUCKET_SIZE    0x1615\n\n#define    RTL8367C_REG_METER22_BUCKET_SIZE    0x1616\n\n#define    RTL8367C_REG_METER23_BUCKET_SIZE    0x1617\n\n#define    RTL8367C_REG_METER24_BUCKET_SIZE    0x1618\n\n#define    RTL8367C_REG_METER25_BUCKET_SIZE    0x1619\n\n#define    RTL8367C_REG_METER26_BUCKET_SIZE    0x161a\n\n#define    RTL8367C_REG_METER27_BUCKET_SIZE    0x161b\n\n#define    RTL8367C_REG_METER28_BUCKET_SIZE    0x161c\n\n#define    RTL8367C_REG_METER29_BUCKET_SIZE    0x161d\n\n#define    RTL8367C_REG_METER30_BUCKET_SIZE    0x161e\n\n#define    RTL8367C_REG_METER31_BUCKET_SIZE    0x161f\n\n#define    RTL8367C_REG_METER_CTRL0    0x1700\n#define    RTL8367C_METER_OP_OFFSET    8\n#define    RTL8367C_METER_OP_MASK    0x100\n#define    RTL8367C_METER_TICK_OFFSET    0\n#define    RTL8367C_METER_TICK_MASK    0xFF\n\n#define    RTL8367C_REG_METER_CTRL1    0x1701\n#define    RTL8367C_METER_CTRL1_OFFSET    0\n#define    RTL8367C_METER_CTRL1_MASK    0xFF\n\n#define    RTL8367C_REG_METER_OVERRATE_INDICATOR0    0x1702\n\n#define    RTL8367C_REG_METER_OVERRATE_INDICATOR1    0x1703\n\n#define    RTL8367C_REG_METER_OVERRATE_INDICATOR0_8051    0x1704\n\n#define    RTL8367C_REG_METER_OVERRATE_INDICATOR1_8051    0x1705\n\n#define    RTL8367C_REG_METER_IFG_CTRL0    0x1712\n#define    RTL8367C_METER15_IFG_OFFSET    15\n#define    RTL8367C_METER15_IFG_MASK    0x8000\n#define    RTL8367C_METER14_IFG_OFFSET    14\n#define    RTL8367C_METER14_IFG_MASK    0x4000\n#define    RTL8367C_METER13_IFG_OFFSET    13\n#define    RTL8367C_METER13_IFG_MASK    0x2000\n#define    RTL8367C_METER12_IFG_OFFSET    12\n#define    RTL8367C_METER12_IFG_MASK    0x1000\n#define    RTL8367C_METER11_IFG_OFFSET    11\n#define    RTL8367C_METER11_IFG_MASK    0x800\n#define    RTL8367C_METER10_IFG_OFFSET    10\n#define    RTL8367C_METER10_IFG_MASK    0x400\n#define    RTL8367C_METER9_IFG_OFFSET    9\n#define    RTL8367C_METER9_IFG_MASK    0x200\n#define    RTL8367C_METER8_IFG_OFFSET    8\n#define    RTL8367C_METER8_IFG_MASK    0x100\n#define    RTL8367C_METER7_IFG_OFFSET    7\n#define    RTL8367C_METER7_IFG_MASK    0x80\n#define    RTL8367C_METER6_IFG_OFFSET    6\n#define    RTL8367C_METER6_IFG_MASK    0x40\n#define    RTL8367C_METER5_IFG_OFFSET    5\n#define    RTL8367C_METER5_IFG_MASK    0x20\n#define    RTL8367C_METER4_IFG_OFFSET    4\n#define    RTL8367C_METER4_IFG_MASK    0x10\n#define    RTL8367C_METER3_IFG_OFFSET    3\n#define    RTL8367C_METER3_IFG_MASK    0x8\n#define    RTL8367C_METER2_IFG_OFFSET    2\n#define    RTL8367C_METER2_IFG_MASK    0x4\n#define    RTL8367C_METER1_IFG_OFFSET    1\n#define    RTL8367C_METER1_IFG_MASK    0x2\n#define    RTL8367C_METER0_IFG_OFFSET    0\n#define    RTL8367C_METER0_IFG_MASK    0x1\n\n#define    RTL8367C_REG_METER_IFG_CTRL1    0x1713\n#define    RTL8367C_METER31_IFG_OFFSET    15\n#define    RTL8367C_METER31_IFG_MASK    0x8000\n#define    RTL8367C_METER30_IFG_OFFSET    14\n#define    RTL8367C_METER30_IFG_MASK    0x4000\n#define    RTL8367C_METER29_IFG_OFFSET    13\n#define    RTL8367C_METER29_IFG_MASK    0x2000\n#define    RTL8367C_METER28_IFG_OFFSET    12\n#define    RTL8367C_METER28_IFG_MASK    0x1000\n#define    RTL8367C_METER27_IFG_OFFSET    11\n#define    RTL8367C_METER27_IFG_MASK    0x800\n#define    RTL8367C_METER26_IFG_OFFSET    10\n#define    RTL8367C_METER26_IFG_MASK    0x400\n#define    RTL8367C_METER25_IFG_OFFSET    9\n#define    RTL8367C_METER25_IFG_MASK    0x200\n#define    RTL8367C_METER24_IFG_OFFSET    8\n#define    RTL8367C_METER24_IFG_MASK    0x100\n#define    RTL8367C_METER23_IFG_OFFSET    7\n#define    RTL8367C_METER23_IFG_MASK    0x80\n#define    RTL8367C_METER22_IFG_OFFSET    6\n#define    RTL8367C_METER22_IFG_MASK    0x40\n#define    RTL8367C_METER21_IFG_OFFSET    5\n#define    RTL8367C_METER21_IFG_MASK    0x20\n#define    RTL8367C_METER20_IFG_OFFSET    4\n#define    RTL8367C_METER20_IFG_MASK    0x10\n#define    RTL8367C_METER19_IFG_OFFSET    3\n#define    RTL8367C_METER19_IFG_MASK    0x8\n#define    RTL8367C_METER18_IFG_OFFSET    2\n#define    RTL8367C_METER18_IFG_MASK    0x4\n#define    RTL8367C_METER17_IFG_OFFSET    1\n#define    RTL8367C_METER17_IFG_MASK    0x2\n#define    RTL8367C_METER16_IFG_OFFSET    0\n#define    RTL8367C_METER16_IFG_MASK    0x1\n\n#define    RTL8367C_REG_METER_CTRL2    0x1722\n#define    RTL8367C_cfg_mtr_tick_8g_OFFSET    8\n#define    RTL8367C_cfg_mtr_tick_8g_MASK    0xFF00\n#define    RTL8367C_cfg_mtr_dec_cnt_8g_OFFSET    0\n#define    RTL8367C_cfg_mtr_dec_cnt_8g_MASK    0xFF\n\n#define    RTL8367C_REG_DUMMY_1723    0x1723\n\n#define    RTL8367C_REG_DUMMY_1724    0x1724\n\n#define    RTL8367C_REG_DUMMY_1725    0x1725\n\n#define    RTL8367C_REG_DUMMY_1726    0x1726\n\n#define    RTL8367C_REG_DUMMY_1727    0x1727\n\n#define    RTL8367C_REG_DUMMY_1728    0x1728\n\n#define    RTL8367C_REG_DUMMY_1729    0x1729\n\n#define    RTL8367C_REG_DUMMY_172A    0x172a\n\n#define    RTL8367C_REG_DUMMY_172B    0x172b\n\n#define    RTL8367C_REG_DUMMY_172C    0x172c\n\n#define    RTL8367C_REG_DUMMY_172D    0x172d\n\n#define    RTL8367C_REG_DUMMY_172E    0x172e\n\n#define    RTL8367C_REG_DUMMY_172F    0x172f\n\n#define    RTL8367C_REG_DUMMY_1730    0x1730\n\n#define    RTL8367C_REG_DUMMY_1731    0x1731\n\n#define    RTL8367C_REG_METER32_RATE_CTRL0    0x1740\n\n#define    RTL8367C_REG_METER32_RATE_CTRL1    0x1741\n#define    RTL8367C_METER32_RATE_CTRL1_OFFSET    0\n#define    RTL8367C_METER32_RATE_CTRL1_MASK    0x7\n\n#define    RTL8367C_REG_METER33_RATE_CTRL0    0x1742\n\n#define    RTL8367C_REG_METER33_RATE_CTRL1    0x1743\n#define    RTL8367C_METER33_RATE_CTRL1_OFFSET    0\n#define    RTL8367C_METER33_RATE_CTRL1_MASK    0x7\n\n#define    RTL8367C_REG_METER34_RATE_CTRL0    0x1744\n\n#define    RTL8367C_REG_METER34_RATE_CTRL1    0x1745\n#define    RTL8367C_METER34_RATE_CTRL1_OFFSET    0\n#define    RTL8367C_METER34_RATE_CTRL1_MASK    0x7\n\n#define    RTL8367C_REG_METER35_RATE_CTRL0    0x1746\n\n#define    RTL8367C_REG_METER35_RATE_CTRL1    0x1747\n#define    RTL8367C_METER35_RATE_CTRL1_OFFSET    0\n#define    RTL8367C_METER35_RATE_CTRL1_MASK    0x7\n\n#define    RTL8367C_REG_METER36_RATE_CTRL0    0x1748\n\n#define    RTL8367C_REG_METER36_RATE_CTRL1    0x1749\n#define    RTL8367C_METER36_RATE_CTRL1_OFFSET    0\n#define    RTL8367C_METER36_RATE_CTRL1_MASK    0x7\n\n#define    RTL8367C_REG_METER37_RATE_CTRL0    0x174a\n\n#define    RTL8367C_REG_METER37_RATE_CTRL1    0x174b\n#define    RTL8367C_METER37_RATE_CTRL1_OFFSET    0\n#define    RTL8367C_METER37_RATE_CTRL1_MASK    0x7\n\n#define    RTL8367C_REG_METER38_RATE_CTRL0    0x174c\n\n#define    RTL8367C_REG_METER38_RATE_CTRL1    0x174d\n#define    RTL8367C_METER38_RATE_CTRL1_OFFSET    0\n#define    RTL8367C_METER38_RATE_CTRL1_MASK    0x7\n\n#define    RTL8367C_REG_METER39_RATE_CTRL0    0x174e\n\n#define    RTL8367C_REG_METER39_RATE_CTRL1    0x174f\n#define    RTL8367C_METER39_RATE_CTRL1_OFFSET    0\n#define    RTL8367C_METER39_RATE_CTRL1_MASK    0x7\n\n#define    RTL8367C_REG_METER40_RATE_CTRL0    0x1750\n\n#define    RTL8367C_REG_METER40_RATE_CTRL1    0x1751\n#define    RTL8367C_METER40_RATE_CTRL1_OFFSET    0\n#define    RTL8367C_METER40_RATE_CTRL1_MASK    0x7\n\n#define    RTL8367C_REG_METER41_RATE_CTRL0    0x1752\n\n#define    RTL8367C_REG_METER41_RATE_CTRL1    0x1753\n#define    RTL8367C_METER41_RATE_CTRL1_OFFSET    0\n#define    RTL8367C_METER41_RATE_CTRL1_MASK    0x7\n\n#define    RTL8367C_REG_METER42_RATE_CTRL0    0x1754\n\n#define    RTL8367C_REG_METER42_RATE_CTRL1    0x1755\n#define    RTL8367C_METER42_RATE_CTRL1_OFFSET    0\n#define    RTL8367C_METER42_RATE_CTRL1_MASK    0x7\n\n#define    RTL8367C_REG_METER43_RATE_CTRL0    0x1756\n\n#define    RTL8367C_REG_METER43_RATE_CTRL1    0x1757\n#define    RTL8367C_METER43_RATE_CTRL1_OFFSET    0\n#define    RTL8367C_METER43_RATE_CTRL1_MASK    0x7\n\n#define    RTL8367C_REG_METER44_RATE_CTRL0    0x1758\n\n#define    RTL8367C_REG_METER44_RATE_CTRL1    0x1759\n#define    RTL8367C_METER44_RATE_CTRL1_OFFSET    0\n#define    RTL8367C_METER44_RATE_CTRL1_MASK    0x7\n\n#define    RTL8367C_REG_METER45_RATE_CTRL0    0x175a\n\n#define    RTL8367C_REG_METER45_RATE_CTRL1    0x175b\n#define    RTL8367C_METER45_RATE_CTRL1_OFFSET    0\n#define    RTL8367C_METER45_RATE_CTRL1_MASK    0x7\n\n#define    RTL8367C_REG_METER46_RATE_CTRL0    0x175c\n\n#define    RTL8367C_REG_METER46_RATE_CTRL1    0x175d\n#define    RTL8367C_METER46_RATE_CTRL1_OFFSET    0\n#define    RTL8367C_METER46_RATE_CTRL1_MASK    0x7\n\n#define    RTL8367C_REG_METER47_RATE_CTRL0    0x175e\n\n#define    RTL8367C_REG_METER47_RATE_CTRL1    0x175f\n#define    RTL8367C_METER47_RATE_CTRL1_OFFSET    0\n#define    RTL8367C_METER47_RATE_CTRL1_MASK    0x7\n\n#define    RTL8367C_REG_METER48_RATE_CTRL0    0x1760\n\n#define    RTL8367C_REG_METER48_RATE_CTRL1    0x1761\n#define    RTL8367C_METER48_RATE_CTRL1_OFFSET    0\n#define    RTL8367C_METER48_RATE_CTRL1_MASK    0x7\n\n#define    RTL8367C_REG_METER49_RATE_CTRL0    0x1762\n\n#define    RTL8367C_REG_METER49_RATE_CTRL1    0x1763\n#define    RTL8367C_METER49_RATE_CTRL1_OFFSET    0\n#define    RTL8367C_METER49_RATE_CTRL1_MASK    0x7\n\n#define    RTL8367C_REG_METER50_RATE_CTRL0    0x1764\n\n#define    RTL8367C_REG_METER50_RATE_CTRL1    0x1765\n#define    RTL8367C_METER50_RATE_CTRL1_OFFSET    0\n#define    RTL8367C_METER50_RATE_CTRL1_MASK    0x7\n\n#define    RTL8367C_REG_METER51_RATE_CTRL0    0x1766\n\n#define    RTL8367C_REG_METER51_RATE_CTRL1    0x1767\n#define    RTL8367C_METER51_RATE_CTRL1_OFFSET    0\n#define    RTL8367C_METER51_RATE_CTRL1_MASK    0x7\n\n#define    RTL8367C_REG_METER52_RATE_CTRL0    0x1768\n\n#define    RTL8367C_REG_METER52_RATE_CTRL1    0x1769\n#define    RTL8367C_METER52_RATE_CTRL1_OFFSET    0\n#define    RTL8367C_METER52_RATE_CTRL1_MASK    0x7\n\n#define    RTL8367C_REG_METER53_RATE_CTRL0    0x176a\n\n#define    RTL8367C_REG_METER53_RATE_CTRL1    0x176b\n#define    RTL8367C_METER53_RATE_CTRL1_OFFSET    0\n#define    RTL8367C_METER53_RATE_CTRL1_MASK    0x7\n\n#define    RTL8367C_REG_METER54_RATE_CTRL0    0x176c\n\n#define    RTL8367C_REG_METER54_RATE_CTRL1    0x176d\n#define    RTL8367C_METER54_RATE_CTRL1_OFFSET    0\n#define    RTL8367C_METER54_RATE_CTRL1_MASK    0x7\n\n#define    RTL8367C_REG_METER55_RATE_CTRL0    0x176e\n\n#define    RTL8367C_REG_METER55_RATE_CTRL1    0x176f\n#define    RTL8367C_METER55_RATE_CTRL1_OFFSET    0\n#define    RTL8367C_METER55_RATE_CTRL1_MASK    0x7\n\n#define    RTL8367C_REG_METER56_RATE_CTRL0    0x1770\n\n#define    RTL8367C_REG_METER56_RATE_CTRL1    0x1771\n#define    RTL8367C_METER56_RATE_CTRL1_OFFSET    0\n#define    RTL8367C_METER56_RATE_CTRL1_MASK    0x7\n\n#define    RTL8367C_REG_METER57_RATE_CTRL0    0x1772\n\n#define    RTL8367C_REG_METER57_RATE_CTRL1    0x1773\n#define    RTL8367C_METER57_RATE_CTRL1_OFFSET    0\n#define    RTL8367C_METER57_RATE_CTRL1_MASK    0x7\n\n#define    RTL8367C_REG_METER58_RATE_CTRL0    0x1774\n\n#define    RTL8367C_REG_METER58_RATE_CTRL1    0x1775\n#define    RTL8367C_METER58_RATE_CTRL1_OFFSET    0\n#define    RTL8367C_METER58_RATE_CTRL1_MASK    0x7\n\n#define    RTL8367C_REG_METER59_RATE_CTRL0    0x1776\n\n#define    RTL8367C_REG_METER59_RATE_CTRL1    0x1777\n#define    RTL8367C_METER59_RATE_CTRL1_OFFSET    0\n#define    RTL8367C_METER59_RATE_CTRL1_MASK    0x7\n\n#define    RTL8367C_REG_METER60_RATE_CTRL0    0x1778\n\n#define    RTL8367C_REG_METER60_RATE_CTRL1    0x1779\n#define    RTL8367C_METER60_RATE_CTRL1_OFFSET    0\n#define    RTL8367C_METER60_RATE_CTRL1_MASK    0x7\n\n#define    RTL8367C_REG_METER61_RATE_CTRL0    0x177a\n\n#define    RTL8367C_REG_METER61_RATE_CTRL1    0x177b\n#define    RTL8367C_METER61_RATE_CTRL1_OFFSET    0\n#define    RTL8367C_METER61_RATE_CTRL1_MASK    0x7\n\n#define    RTL8367C_REG_METER62_RATE_CTRL0    0x177c\n\n#define    RTL8367C_REG_METER62_RATE_CTRL1    0x177d\n#define    RTL8367C_METER62_RATE_CTRL1_OFFSET    0\n#define    RTL8367C_METER62_RATE_CTRL1_MASK    0x7\n\n#define    RTL8367C_REG_METER63_RATE_CTRL0    0x177e\n\n#define    RTL8367C_REG_METER63_RATE_CTRL1    0x177f\n#define    RTL8367C_METER63_RATE_CTRL1_OFFSET    0\n#define    RTL8367C_METER63_RATE_CTRL1_MASK    0x7\n\n#define    RTL8367C_REG_METER_MODE_SETTING2    0x1780\n\n#define    RTL8367C_REG_METER_MODE_SETTING3    0x1781\n\n#define    RTL8367C_REG_METER32_BUCKET_SIZE    0x1790\n\n#define    RTL8367C_REG_METER33_BUCKET_SIZE    0x1791\n\n#define    RTL8367C_REG_METER34_BUCKET_SIZE    0x1792\n\n#define    RTL8367C_REG_METER35_BUCKET_SIZE    0x1793\n\n#define    RTL8367C_REG_METER36_BUCKET_SIZE    0x1794\n\n#define    RTL8367C_REG_METER37_BUCKET_SIZE    0x1795\n\n#define    RTL8367C_REG_METER38_BUCKET_SIZE    0x1796\n\n#define    RTL8367C_REG_METER39_BUCKET_SIZE    0x1797\n\n#define    RTL8367C_REG_METER40_BUCKET_SIZE    0x1798\n\n#define    RTL8367C_REG_METER41_BUCKET_SIZE    0x1799\n\n#define    RTL8367C_REG_METER42_BUCKET_SIZE    0x179a\n\n#define    RTL8367C_REG_METER43_BUCKET_SIZE    0x179b\n\n#define    RTL8367C_REG_METER44_BUCKET_SIZE    0x179c\n\n#define    RTL8367C_REG_METER45_BUCKET_SIZE    0x179d\n\n#define    RTL8367C_REG_METER46_BUCKET_SIZE    0x179e\n\n#define    RTL8367C_REG_METER47_BUCKET_SIZE    0x179f\n\n#define    RTL8367C_REG_METER48_BUCKET_SIZE    0x17a0\n\n#define    RTL8367C_REG_METER49_BUCKET_SIZE    0x17a1\n\n#define    RTL8367C_REG_METER50_BUCKET_SIZE    0x17a2\n\n#define    RTL8367C_REG_METER51_BUCKET_SIZE    0x17a3\n\n#define    RTL8367C_REG_METER52_BUCKET_SIZE    0x17a4\n\n#define    RTL8367C_REG_METER53_BUCKET_SIZE    0x17a5\n\n#define    RTL8367C_REG_METER54_BUCKET_SIZE    0x17a6\n\n#define    RTL8367C_REG_METER55_BUCKET_SIZE    0x17a7\n\n#define    RTL8367C_REG_METER56_BUCKET_SIZE    0x17a8\n\n#define    RTL8367C_REG_METER57_BUCKET_SIZE    0x17a9\n\n#define    RTL8367C_REG_METER58_BUCKET_SIZE    0x17aa\n\n#define    RTL8367C_REG_METER59_BUCKET_SIZE    0x17ab\n\n#define    RTL8367C_REG_METER60_BUCKET_SIZE    0x17ac\n\n#define    RTL8367C_REG_METER61_BUCKET_SIZE    0x17ad\n\n#define    RTL8367C_REG_METER62_BUCKET_SIZE    0x17ae\n\n#define    RTL8367C_REG_METER63_BUCKET_SIZE    0x17af\n\n#define    RTL8367C_REG_METER_OVERRATE_INDICATOR2    0x17b0\n\n#define    RTL8367C_REG_METER_OVERRATE_INDICATOR3    0x17b1\n\n#define    RTL8367C_REG_METER_OVERRATE_INDICATOR2_8051    0x17b2\n\n#define    RTL8367C_REG_METER_OVERRATE_INDICATOR3_8051    0x17b3\n\n#define    RTL8367C_REG_METER_IFG_CTRL2    0x17b4\n#define    RTL8367C_METER47_IFG_OFFSET    15\n#define    RTL8367C_METER47_IFG_MASK    0x8000\n#define    RTL8367C_METER46_IFG_OFFSET    14\n#define    RTL8367C_METER46_IFG_MASK    0x4000\n#define    RTL8367C_METER45_IFG_OFFSET    13\n#define    RTL8367C_METER45_IFG_MASK    0x2000\n#define    RTL8367C_METER44_IFG_OFFSET    12\n#define    RTL8367C_METER44_IFG_MASK    0x1000\n#define    RTL8367C_METER43_IFG_OFFSET    11\n#define    RTL8367C_METER43_IFG_MASK    0x800\n#define    RTL8367C_METER42_IFG_OFFSET    10\n#define    RTL8367C_METER42_IFG_MASK    0x400\n#define    RTL8367C_METER41_IFG_OFFSET    9\n#define    RTL8367C_METER41_IFG_MASK    0x200\n#define    RTL8367C_METER40_IFG_OFFSET    8\n#define    RTL8367C_METER40_IFG_MASK    0x100\n#define    RTL8367C_METER39_IFG_OFFSET    7\n#define    RTL8367C_METER39_IFG_MASK    0x80\n#define    RTL8367C_METER38_IFG_OFFSET    6\n#define    RTL8367C_METER38_IFG_MASK    0x40\n#define    RTL8367C_METER37_IFG_OFFSET    5\n#define    RTL8367C_METER37_IFG_MASK    0x20\n#define    RTL8367C_METER36_IFG_OFFSET    4\n#define    RTL8367C_METER36_IFG_MASK    0x10\n#define    RTL8367C_METER35_IFG_OFFSET    3\n#define    RTL8367C_METER35_IFG_MASK    0x8\n#define    RTL8367C_METER34_IFG_OFFSET    2\n#define    RTL8367C_METER34_IFG_MASK    0x4\n#define    RTL8367C_METER33_IFG_OFFSET    1\n#define    RTL8367C_METER33_IFG_MASK    0x2\n#define    RTL8367C_METER32_IFG_OFFSET    0\n#define    RTL8367C_METER32_IFG_MASK    0x1\n\n#define    RTL8367C_REG_METER_IFG_CTRL3    0x17b5\n#define    RTL8367C_METER63_IFG_OFFSET    15\n#define    RTL8367C_METER63_IFG_MASK    0x8000\n#define    RTL8367C_METER62_IFG_OFFSET    14\n#define    RTL8367C_METER62_IFG_MASK    0x4000\n#define    RTL8367C_METER61_IFG_OFFSET    13\n#define    RTL8367C_METER61_IFG_MASK    0x2000\n#define    RTL8367C_METER60_IFG_OFFSET    12\n#define    RTL8367C_METER60_IFG_MASK    0x1000\n#define    RTL8367C_METER59_IFG_OFFSET    11\n#define    RTL8367C_METER59_IFG_MASK    0x800\n#define    RTL8367C_METER58_IFG_OFFSET    10\n#define    RTL8367C_METER58_IFG_MASK    0x400\n#define    RTL8367C_METER57_IFG_OFFSET    9\n#define    RTL8367C_METER57_IFG_MASK    0x200\n#define    RTL8367C_METER56_IFG_OFFSET    8\n#define    RTL8367C_METER56_IFG_MASK    0x100\n#define    RTL8367C_METER55_IFG_OFFSET    7\n#define    RTL8367C_METER55_IFG_MASK    0x80\n#define    RTL8367C_METER54_IFG_OFFSET    6\n#define    RTL8367C_METER54_IFG_MASK    0x40\n#define    RTL8367C_METER53_IFG_OFFSET    5\n#define    RTL8367C_METER53_IFG_MASK    0x20\n#define    RTL8367C_METER52_IFG_OFFSET    4\n#define    RTL8367C_METER52_IFG_MASK    0x10\n#define    RTL8367C_METER51_IFG_OFFSET    3\n#define    RTL8367C_METER51_IFG_MASK    0x8\n#define    RTL8367C_METER50_IFG_OFFSET    2\n#define    RTL8367C_METER50_IFG_MASK    0x4\n#define    RTL8367C_METER49_IFG_OFFSET    1\n#define    RTL8367C_METER49_IFG_MASK    0x2\n#define    RTL8367C_METER48_IFG_OFFSET    0\n#define    RTL8367C_METER48_IFG_MASK    0x1\n\n#define    RTL8367C_REG_METER_MISC    0x17b6\n#define    RTL8367C_METER_MISC_OFFSET    0\n#define    RTL8367C_METER_MISC_MASK    0x1\n\n/* (16'h1800)8051_RLDP_EEE_reg */\n\n#define    RTL8367C_REG_EEELLDP_CTRL0    0x1820\n#define    RTL8367C_EEELLDP_SUBTYPE_OFFSET    6\n#define    RTL8367C_EEELLDP_SUBTYPE_MASK    0x3FC0\n#define    RTL8367C_EEELLDP_TRAP_8051_OFFSET    2\n#define    RTL8367C_EEELLDP_TRAP_8051_MASK    0x4\n#define    RTL8367C_EEELLDP_TRAP_CPU_OFFSET    1\n#define    RTL8367C_EEELLDP_TRAP_CPU_MASK    0x2\n#define    RTL8367C_EEELLDP_ENABLE_OFFSET    0\n#define    RTL8367C_EEELLDP_ENABLE_MASK    0x1\n\n#define    RTL8367C_REG_EEELLDP_PMSK    0x1822\n#define    RTL8367C_EEELLDP_PMSK_OFFSET    0\n#define    RTL8367C_EEELLDP_PMSK_MASK    0x7FF\n\n#define    RTL8367C_REG_EEELLDP_RX_VALUE_P00_08    0x1843\n\n#define    RTL8367C_REG_EEELLDP_RX_VALUE_P00_07    0x1844\n\n#define    RTL8367C_REG_EEELLDP_RX_VALUE_P00_06    0x1845\n\n#define    RTL8367C_REG_EEELLDP_RX_VALUE_P00_05    0x1846\n\n#define    RTL8367C_REG_EEELLDP_RX_VALUE_P00_04    0x1847\n\n#define    RTL8367C_REG_EEELLDP_RX_VALUE_P00_03    0x1848\n\n#define    RTL8367C_REG_EEELLDP_RX_VALUE_P00_02    0x1849\n\n#define    RTL8367C_REG_EEELLDP_RX_VALUE_P00_01    0x184a\n\n#define    RTL8367C_REG_EEELLDP_RX_VALUE_P00_00    0x184b\n\n#define    RTL8367C_REG_EEELLDP_RX_VALUE_P01_08    0x184c\n\n#define    RTL8367C_REG_EEELLDP_RX_VALUE_P01_07    0x184d\n\n#define    RTL8367C_REG_EEELLDP_RX_VALUE_P01_06    0x184e\n\n#define    RTL8367C_REG_EEELLDP_RX_VALUE_P01_05    0x184f\n\n#define    RTL8367C_REG_EEELLDP_RX_VALUE_P01_04    0x1850\n\n#define    RTL8367C_REG_EEELLDP_RX_VALUE_P01_03    0x1851\n\n#define    RTL8367C_REG_EEELLDP_RX_VALUE_P01_02    0x1852\n\n#define    RTL8367C_REG_EEELLDP_RX_VALUE_P01_01    0x1853\n\n#define    RTL8367C_REG_EEELLDP_RX_VALUE_P01_00    0x1854\n\n#define    RTL8367C_REG_EEELLDP_RX_VALUE_P02_08    0x1855\n\n#define    RTL8367C_REG_EEELLDP_RX_VALUE_P02_07    0x1856\n\n#define    RTL8367C_REG_EEELLDP_RX_VALUE_P02_06    0x1857\n\n#define    RTL8367C_REG_EEELLDP_RX_VALUE_P02_05    0x1858\n\n#define    RTL8367C_REG_EEELLDP_RX_VALUE_P02_04    0x1859\n\n#define    RTL8367C_REG_EEELLDP_RX_VALUE_P02_03    0x185a\n\n#define    RTL8367C_REG_EEELLDP_RX_VALUE_P02_02    0x185b\n\n#define    RTL8367C_REG_EEELLDP_RX_VALUE_P02_01    0x185c\n\n#define    RTL8367C_REG_EEELLDP_RX_VALUE_P02_00    0x185d\n\n#define    RTL8367C_REG_EEELLDP_RX_VALUE_P03_08    0x185e\n\n#define    RTL8367C_REG_EEELLDP_RX_VALUE_P03_07    0x185f\n\n#define    RTL8367C_REG_EEELLDP_RX_VALUE_P03_06    0x1860\n\n#define    RTL8367C_REG_EEELLDP_RX_VALUE_P03_05    0x1861\n\n#define    RTL8367C_REG_EEELLDP_RX_VALUE_P03_04    0x1862\n\n#define    RTL8367C_REG_EEELLDP_RX_VALUE_P03_03    0x1863\n\n#define    RTL8367C_REG_EEELLDP_RX_VALUE_P03_02    0x1864\n\n#define    RTL8367C_REG_EEELLDP_RX_VALUE_P03_01    0x1865\n\n#define    RTL8367C_REG_EEELLDP_RX_VALUE_P03_00    0x1866\n\n#define    RTL8367C_REG_EEELLDP_RX_VALUE_P04_08    0x1867\n\n#define    RTL8367C_REG_EEELLDP_RX_VALUE_P04_07    0x1868\n\n#define    RTL8367C_REG_EEELLDP_RX_VALUE_P04_06    0x1869\n\n#define    RTL8367C_REG_EEELLDP_RX_VALUE_P04_05    0x186a\n\n#define    RTL8367C_REG_EEELLDP_RX_VALUE_P04_04    0x186b\n\n#define    RTL8367C_REG_EEELLDP_RX_VALUE_P04_03    0x186c\n\n#define    RTL8367C_REG_EEELLDP_RX_VALUE_P04_02    0x186d\n\n#define    RTL8367C_REG_EEELLDP_RX_VALUE_P04_01    0x186e\n\n#define    RTL8367C_REG_EEELLDP_RX_VALUE_P04_00    0x186f\n\n#define    RTL8367C_REG_EEELLDP_RX_VALUE_P05_08    0x1870\n\n#define    RTL8367C_REG_EEELLDP_RX_VALUE_P05_07    0x1871\n\n#define    RTL8367C_REG_EEELLDP_RX_VALUE_P05_06    0x1872\n\n#define    RTL8367C_REG_EEELLDP_RX_VALUE_P05_05    0x1873\n\n#define    RTL8367C_REG_EEELLDP_RX_VALUE_P05_04    0x1874\n\n#define    RTL8367C_REG_EEELLDP_RX_VALUE_P05_03    0x1875\n\n#define    RTL8367C_REG_EEELLDP_RX_VALUE_P05_02    0x1876\n\n#define    RTL8367C_REG_EEELLDP_RX_VALUE_P05_01    0x1877\n\n#define    RTL8367C_REG_EEELLDP_RX_VALUE_P05_00    0x1878\n\n#define    RTL8367C_REG_EEELLDP_RX_VALUE_P06_08    0x1879\n\n#define    RTL8367C_REG_EEELLDP_RX_VALUE_P06_07    0x187a\n\n#define    RTL8367C_REG_EEELLDP_RX_VALUE_P06_06    0x187b\n\n#define    RTL8367C_REG_EEELLDP_RX_VALUE_P06_05    0x187c\n\n#define    RTL8367C_REG_EEELLDP_RX_VALUE_P06_04    0x187d\n\n#define    RTL8367C_REG_EEELLDP_RX_VALUE_P06_03    0x187e\n\n#define    RTL8367C_REG_EEELLDP_RX_VALUE_P06_02    0x187f\n\n#define    RTL8367C_REG_EEELLDP_RX_VALUE_P06_01    0x1880\n\n#define    RTL8367C_REG_EEELLDP_RX_VALUE_P06_00    0x1881\n\n#define    RTL8367C_REG_EEELLDP_RX_VALUE_P07_08    0x1882\n\n#define    RTL8367C_REG_EEELLDP_RX_VALUE_P07_07    0x1883\n\n#define    RTL8367C_REG_EEELLDP_RX_VALUE_P07_06    0x1884\n\n#define    RTL8367C_REG_EEELLDP_RX_VALUE_P07_05    0x1885\n\n#define    RTL8367C_REG_EEELLDP_RX_VALUE_P07_04    0x1886\n\n#define    RTL8367C_REG_EEELLDP_RX_VALUE_P07_03    0x1887\n\n#define    RTL8367C_REG_EEELLDP_RX_VALUE_P07_02    0x1888\n\n#define    RTL8367C_REG_EEELLDP_RX_VALUE_P07_01    0x1889\n\n#define    RTL8367C_REG_EEELLDP_RX_VALUE_P07_00    0x188a\n\n#define    RTL8367C_REG_EEELLDP_RX_VALUE_P08_08    0x188b\n\n#define    RTL8367C_REG_EEELLDP_RX_VALUE_P08_07    0x188c\n\n#define    RTL8367C_REG_EEELLDP_RX_VALUE_P08_06    0x188d\n\n#define    RTL8367C_REG_EEELLDP_RX_VALUE_P08_05    0x188e\n\n#define    RTL8367C_REG_EEELLDP_RX_VALUE_P08_04    0x188f\n\n#define    RTL8367C_REG_EEELLDP_RX_VALUE_P08_03    0x1890\n\n#define    RTL8367C_REG_EEELLDP_RX_VALUE_P08_02    0x1891\n\n#define    RTL8367C_REG_EEELLDP_RX_VALUE_P08_01    0x1892\n\n#define    RTL8367C_REG_EEELLDP_RX_VALUE_P08_00    0x1893\n\n#define    RTL8367C_REG_EEELLDP_RX_VALUE_P09_08    0x1894\n\n#define    RTL8367C_REG_EEELLDP_RX_VALUE_P09_07    0x1895\n\n#define    RTL8367C_REG_EEELLDP_RX_VALUE_P09_06    0x1896\n\n#define    RTL8367C_REG_EEELLDP_RX_VALUE_P09_05    0x1897\n\n#define    RTL8367C_REG_EEELLDP_RX_VALUE_P09_04    0x1898\n\n#define    RTL8367C_REG_EEELLDP_RX_VALUE_P09_03    0x1899\n\n#define    RTL8367C_REG_EEELLDP_RX_VALUE_P09_02    0x189a\n\n#define    RTL8367C_REG_EEELLDP_RX_VALUE_P09_01    0x189b\n\n#define    RTL8367C_REG_EEELLDP_RX_VALUE_P09_00    0x189c\n\n#define    RTL8367C_REG_EEELLDP_RX_VALUE_P10_08    0x189d\n\n#define    RTL8367C_REG_EEELLDP_RX_VALUE_P10_07    0x189e\n\n#define    RTL8367C_REG_EEELLDP_RX_VALUE_P10_06    0x189f\n\n#define    RTL8367C_REG_EEELLDP_RX_VALUE_P10_05    0x18a0\n\n#define    RTL8367C_REG_EEELLDP_RX_VALUE_P10_04    0x18a1\n\n#define    RTL8367C_REG_EEELLDP_RX_VALUE_P10_03    0x18a2\n\n#define    RTL8367C_REG_EEELLDP_RX_VALUE_P10_02    0x18a3\n\n#define    RTL8367C_REG_EEELLDP_RX_VALUE_P10_01    0x18a4\n\n#define    RTL8367C_REG_EEELLDP_RX_VALUE_P10_00    0x18a5\n\n#define    RTL8367C_REG_RLDP_CTRL0    0x18e0\n#define    RTL8367C_RLDP_TRIGGER_MODE_OFFSET    14\n#define    RTL8367C_RLDP_TRIGGER_MODE_MASK    0x4000\n#define    RTL8367C_RLDP_8051_LOOP_PORTMSK_OFFSET    6\n#define    RTL8367C_RLDP_8051_LOOP_PORTMSK_MASK    0x3FC0\n#define    RTL8367C_RLPP_8051_TRAP_OFFSET    5\n#define    RTL8367C_RLPP_8051_TRAP_MASK    0x20\n#define    RTL8367C_RLDP_INDICATOR_SOURCE_OFFSET    4\n#define    RTL8367C_RLDP_INDICATOR_SOURCE_MASK    0x10\n#define    RTL8367C_RLDP_GEN_RANDOM_OFFSET    3\n#define    RTL8367C_RLDP_GEN_RANDOM_MASK    0x8\n#define    RTL8367C_RLDP_COMP_ID_OFFSET    2\n#define    RTL8367C_RLDP_COMP_ID_MASK    0x4\n#define    RTL8367C_RLDP_8051_ENABLE_OFFSET    1\n#define    RTL8367C_RLDP_8051_ENABLE_MASK    0x2\n#define    RTL8367C_RLDP_ENABLE_OFFSET    0\n#define    RTL8367C_RLDP_ENABLE_MASK    0x1\n\n#define    RTL8367C_REG_RLDP_CTRL1    0x18e1\n#define    RTL8367C_RLDP_RETRY_COUNT_LOOPSTATE_OFFSET    8\n#define    RTL8367C_RLDP_RETRY_COUNT_LOOPSTATE_MASK    0xFF00\n#define    RTL8367C_RLDP_RETRY_COUNT_CHKSTATE_OFFSET    0\n#define    RTL8367C_RLDP_RETRY_COUNT_CHKSTATE_MASK    0xFF\n\n#define    RTL8367C_REG_RLDP_CTRL2    0x18e2\n\n#define    RTL8367C_REG_RLDP_CTRL3    0x18e3\n\n#define    RTL8367C_REG_RLDP_CTRL4    0x18e4\n#define    RTL8367C_RLDP_CTRL4_OFFSET    0\n#define    RTL8367C_RLDP_CTRL4_MASK    0x7FF\n\n#define    RTL8367C_REG_RLDP_RAND_NUM0    0x18e5\n\n#define    RTL8367C_REG_RLDP_RAND_NUM1    0x18e6\n\n#define    RTL8367C_REG_RLDP_RAND_NUM2    0x18e7\n\n#define    RTL8367C_REG_RLDP_MAGIC_NUM0    0x18e8\n\n#define    RTL8367C_REG_RLDP_MAGIC_NUM1    0x18e9\n\n#define    RTL8367C_REG_RLDP_MAGIC_NUM2    0x18ea\n\n#define    RTL8367C_REG_RLDP_LOOPED_INDICATOR    0x18eb\n#define    RTL8367C_RLDP_LOOPED_INDICATOR_OFFSET    0\n#define    RTL8367C_RLDP_LOOPED_INDICATOR_MASK    0x7FF\n\n#define    RTL8367C_REG_RLDP_LOOP_PORT_REG0    0x18ec\n#define    RTL8367C_RLDP_LOOP_PORT_01_OFFSET    8\n#define    RTL8367C_RLDP_LOOP_PORT_01_MASK    0xF00\n#define    RTL8367C_RLDP_LOOP_PORT_00_OFFSET    0\n#define    RTL8367C_RLDP_LOOP_PORT_00_MASK    0xF\n\n#define    RTL8367C_REG_RLDP_LOOP_PORT_REG1    0x18ed\n#define    RTL8367C_RLDP_LOOP_PORT_03_OFFSET    8\n#define    RTL8367C_RLDP_LOOP_PORT_03_MASK    0xF00\n#define    RTL8367C_RLDP_LOOP_PORT_02_OFFSET    0\n#define    RTL8367C_RLDP_LOOP_PORT_02_MASK    0xF\n\n#define    RTL8367C_REG_RLDP_LOOP_PORT_REG2    0x18ee\n#define    RTL8367C_RLDP_LOOP_PORT_05_OFFSET    8\n#define    RTL8367C_RLDP_LOOP_PORT_05_MASK    0xF00\n#define    RTL8367C_RLDP_LOOP_PORT_04_OFFSET    0\n#define    RTL8367C_RLDP_LOOP_PORT_04_MASK    0xF\n\n#define    RTL8367C_REG_RLDP_LOOP_PORT_REG3    0x18ef\n#define    RTL8367C_RLDP_LOOP_PORT_07_OFFSET    8\n#define    RTL8367C_RLDP_LOOP_PORT_07_MASK    0xF00\n#define    RTL8367C_RLDP_LOOP_PORT_06_OFFSET    0\n#define    RTL8367C_RLDP_LOOP_PORT_06_MASK    0xF\n\n#define    RTL8367C_REG_RLDP_RELEASED_INDICATOR    0x18f0\n#define    RTL8367C_RLDP_RELEASED_INDICATOR_OFFSET    0\n#define    RTL8367C_RLDP_RELEASED_INDICATOR_MASK    0x7FF\n\n#define    RTL8367C_REG_RLDP_LOOPSTATUS_INDICATOR    0x18f1\n#define    RTL8367C_RLDP_LOOPSTATUS_INDICATOR_OFFSET    0\n#define    RTL8367C_RLDP_LOOPSTATUS_INDICATOR_MASK    0x7FF\n\n#define    RTL8367C_REG_RLDP_LOOP_PORT_REG4    0x18f2\n#define    RTL8367C_RLDP_LOOP_PORT_9_OFFSET    8\n#define    RTL8367C_RLDP_LOOP_PORT_9_MASK    0xF00\n#define    RTL8367C_RLDP_LOOP_PORT_8_OFFSET    0\n#define    RTL8367C_RLDP_LOOP_PORT_8_MASK    0xF\n\n#define    RTL8367C_REG_RLDP_LOOP_PORT_REG5    0x18f3\n#define    RTL8367C_RLDP_LOOP_PORT_REG5_OFFSET    0\n#define    RTL8367C_RLDP_LOOP_PORT_REG5_MASK    0xF\n\n#define    RTL8367C_REG_RLDP_CTRL5    0x18f4\n#define    RTL8367C_RLDP_CTRL5_OFFSET    0\n#define    RTL8367C_RLDP_CTRL5_MASK    0x7\n\n/* (16'h1900)EEE_EEEP_reg */\n\n#define    RTL8367C_REG_EEE_500M_CTRL0    0x1900\n#define    RTL8367C_EEE_500M_CTRL0_OFFSET    0\n#define    RTL8367C_EEE_500M_CTRL0_MASK    0xFF\n\n#define    RTL8367C_REG_EEE_RXIDLE_GIGA_CTRL    0x1901\n#define    RTL8367C_EEE_RXIDLE_GIGA_EN_OFFSET    8\n#define    RTL8367C_EEE_RXIDLE_GIGA_EN_MASK    0x100\n#define    RTL8367C_EEE_RXIDLE_GIGA_OFFSET    0\n#define    RTL8367C_EEE_RXIDLE_GIGA_MASK    0xFF\n\n#define    RTL8367C_REG_EEE_RXIDLE_500M_CTRL    0x1902\n#define    RTL8367C_EEE_RXIDLE_500M_EN_OFFSET    8\n#define    RTL8367C_EEE_RXIDLE_500M_EN_MASK    0x100\n#define    RTL8367C_EEE_RXIDLE_500M_OFFSET    0\n#define    RTL8367C_EEE_RXIDLE_500M_MASK    0xFF\n\n#define    RTL8367C_REG_EEE_DECISION_GIGA_500M    0x1903\n#define    RTL8367C_EEE_DECISION_GIGA_OFFSET    8\n#define    RTL8367C_EEE_DECISION_GIGA_MASK    0xFF00\n#define    RTL8367C_EEE_DECISION_500M_OFFSET    0\n#define    RTL8367C_EEE_DECISION_500M_MASK    0xFF\n\n#define    RTL8367C_REG_EEE_DECISION_100M    0x1904\n#define    RTL8367C_EEE_DECISION_100M_OFFSET    0\n#define    RTL8367C_EEE_DECISION_100M_MASK    0xFF\n\n#define    RTL8367C_REG_EEEP_DEFER_TXLPI    0x1905\n#define    RTL8367C_EEEP_DEFER_TXLPI_OFFSET    0\n#define    RTL8367C_EEEP_DEFER_TXLPI_MASK    0x1\n\n#define    RTL8367C_REG_EEEP_EN    0x1906\n#define    RTL8367C_EEEP_SLAVE_EN_OFFSET    3\n#define    RTL8367C_EEEP_SLAVE_EN_MASK    0x8\n#define    RTL8367C_EEEP_100M_OFFSET    2\n#define    RTL8367C_EEEP_100M_MASK    0x4\n#define    RTL8367C_EEEP_500M_OFFSET    1\n#define    RTL8367C_EEEP_500M_MASK    0x2\n#define    RTL8367C_EEEP_GIGA_OFFSET    0\n#define    RTL8367C_EEEP_GIGA_MASK    0x1\n\n#define    RTL8367C_REG_EEEP_TI_GIGA_500M    0x1907\n#define    RTL8367C_EEEP_TI_GIGA_OFFSET    8\n#define    RTL8367C_EEEP_TI_GIGA_MASK    0xFF00\n#define    RTL8367C_EEEP_TI_500M_OFFSET    0\n#define    RTL8367C_EEEP_TI_500M_MASK    0xFF\n\n#define    RTL8367C_REG_EEEP_TI_100M    0x1908\n#define    RTL8367C_EEEP_TI_100M_OFFSET    0\n#define    RTL8367C_EEEP_TI_100M_MASK    0xFF\n\n#define    RTL8367C_REG_EEEP_CTRL2    0x1909\n#define    RTL8367C_EEEP_CTRL2_OFFSET    0\n#define    RTL8367C_EEEP_CTRL2_MASK    0xFF\n\n#define    RTL8367C_REG_EEEP_RX_RATE_500M    0x190b\n\n#define    RTL8367C_REG_EEEP_RW_GIGA_SLV    0x190c\n#define    RTL8367C_EEEP_RW_GIGA_SLV_OFFSET    0\n#define    RTL8367C_EEEP_RW_GIGA_SLV_MASK    0xFF\n\n#define    RTL8367C_REG_EEEP_TMR_GIGA    0x190d\n#define    RTL8367C_RX_IDLE_EEEP_GIGA_OFFSET    8\n#define    RTL8367C_RX_IDLE_EEEP_GIGA_MASK    0xFF00\n#define    RTL8367C_RX_MIN_SLP_TMR_GIGA_OFFSET    0\n#define    RTL8367C_RX_MIN_SLP_TMR_GIGA_MASK    0xFF\n\n#define    RTL8367C_REG_EEEP_TMR_500M    0x190e\n#define    RTL8367C_RX_IDLE_EEEP_500M_OFFSET    8\n#define    RTL8367C_RX_IDLE_EEEP_500M_MASK    0xFF00\n#define    RTL8367C_RX_MIN_SLP_TMR_500M_OFFSET    0\n#define    RTL8367C_RX_MIN_SLP_TMR_500M_MASK    0xFF\n\n#define    RTL8367C_REG_EEEP_TMR_100M    0x190f\n#define    RTL8367C_RX_IDLE_EEEP_100M_OFFSET    8\n#define    RTL8367C_RX_IDLE_EEEP_100M_MASK    0xFF00\n#define    RTL8367C_RX_MIN_SLP_TMR_100M_OFFSET    0\n#define    RTL8367C_RX_MIN_SLP_TMR_100M_MASK    0xFF\n\n#define    RTL8367C_REG_EEEP_RW_500M_MST_SLV    0x1910\n#define    RTL8367C_EEEP_RW_500M_MST_OFFSET    8\n#define    RTL8367C_EEEP_RW_500M_MST_MASK    0xFF00\n#define    RTL8367C_EEEP_RW_500M_SLV_OFFSET    0\n#define    RTL8367C_EEEP_RW_500M_SLV_MASK    0xFF\n\n#define    RTL8367C_REG_EEEP_500M_CTRL0    0x1911\n#define    RTL8367C_EEEP_500M_CTRL0_OFFSET    0\n#define    RTL8367C_EEEP_500M_CTRL0_MASK    0xFF\n\n#define    RTL8367C_REG_EEEP_500M_CTRL1    0x1912\n#define    RTL8367C_EEEP_TW_500M_OFFSET    8\n#define    RTL8367C_EEEP_TW_500M_MASK    0xFF00\n#define    RTL8367C_EEEP_TP_500M_OFFSET    0\n#define    RTL8367C_EEEP_TP_500M_MASK    0xFF\n\n#define    RTL8367C_REG_EEEP_500M_CTRL2    0x1913\n#define    RTL8367C_EEEP_TXEN_500M_OFFSET    12\n#define    RTL8367C_EEEP_TXEN_500M_MASK    0x1000\n#define    RTL8367C_EEEP_TU_500M_OFFSET    8\n#define    RTL8367C_EEEP_TU_500M_MASK    0x300\n#define    RTL8367C_EEEP_TS_500M_OFFSET    0\n#define    RTL8367C_EEEP_TS_500M_MASK    0xFF\n\n#define    RTL8367C_REG_EEE_NEW_CTRL0    0x1914\n#define    RTL8367C_LINK_UP_DELAY_OFFSET    3\n#define    RTL8367C_LINK_UP_DELAY_MASK    0x18\n#define    RTL8367C_EEE_TXLPI_ORI_OFFSET    2\n#define    RTL8367C_EEE_TXLPI_ORI_MASK    0x4\n#define    RTL8367C_REALTX_SEL_OFFSET    1\n#define    RTL8367C_REALTX_SEL_MASK    0x2\n#define    RTL8367C_EN_FC_EFCT_OFFSET    0\n#define    RTL8367C_EN_FC_EFCT_MASK    0x1\n\n#define    RTL8367C_REG_EEE_LONGIDLE_100M    0x1915\n#define    RTL8367C_EEE_LONGIDLE_100M_OFFSET    0\n#define    RTL8367C_EEE_LONGIDLE_100M_MASK    0x3FF\n\n#define    RTL8367C_REG_EEE_LONGIDLE_500M    0x1916\n#define    RTL8367C_EEE_LONGIDLE_500M_OFFSET    0\n#define    RTL8367C_EEE_LONGIDLE_500M_MASK    0x3FF\n\n#define    RTL8367C_REG_EEE_LONGIDLE_GIGA    0x1917\n#define    RTL8367C_EEE_LONGIDLE_GIGA_OFFSET    0\n#define    RTL8367C_EEE_LONGIDLE_GIGA_MASK    0x3FF\n\n#define    RTL8367C_REG_EEE_MINIPG_100M    0x1918\n\n#define    RTL8367C_REG_EEE_MINIPG_500M    0x1919\n\n#define    RTL8367C_REG_EEE_MINIPG_GIGA    0x191A\n\n#define    RTL8367C_REG_EEE_LONGIDLE_CTRL0    0x191B\n#define    RTL8367C_TX_IDLEN_REQ_100M_OFFSET    10\n#define    RTL8367C_TX_IDLEN_REQ_100M_MASK    0x400\n#define    RTL8367C_TX_IDLEN_REQ_500M_OFFSET    9\n#define    RTL8367C_TX_IDLEN_REQ_500M_MASK    0x200\n#define    RTL8367C_TX_IDLEN_REQ_GIGA_OFFSET    8\n#define    RTL8367C_TX_IDLEN_REQ_GIGA_MASK    0x100\n#define    RTL8367C_EEE_LONGIDLE_CTRL0_TX_LPI_MINIPG_100M_OFFSET    0\n#define    RTL8367C_EEE_LONGIDLE_CTRL0_TX_LPI_MINIPG_100M_MASK    0xFF\n\n#define    RTL8367C_REG_EEE_LONGIDLE_CTRL1    0x191C\n#define    RTL8367C_EEE_LONGIDLE_CTRL1_TX_LPI_MINIPG_GELITE_OFFSET    8\n#define    RTL8367C_EEE_LONGIDLE_CTRL1_TX_LPI_MINIPG_GELITE_MASK    0xFF00\n#define    RTL8367C_EEE_LONGIDLE_CTRL1_TX_LPI_MINIPG_GIGA_OFFSET    0\n#define    RTL8367C_EEE_LONGIDLE_CTRL1_TX_LPI_MINIPG_GIGA_MASK    0xFF\n\n#define    RTL8367C_REG_EEE_TD_CTRL_H    0x191d\n#define    RTL8367C_REF_RXLPI_OFFSET    8\n#define    RTL8367C_REF_RXLPI_MASK    0x100\n#define    RTL8367C_LOW_Q_TX_DELAY_GE_500M_H_OFFSET    4\n#define    RTL8367C_LOW_Q_TX_DELAY_GE_500M_H_MASK    0xF0\n#define    RTL8367C_LOW_Q_TX_DELAY_FE_H_OFFSET    0\n#define    RTL8367C_LOW_Q_TX_DELAY_FE_H_MASK    0xF\n\n/* (16'h1a00)nic_reg */\n\n#define    RTL8367C_REG_NIC_RXRDRL    0x1a04\n#define    RTL8367C_NIC_RXRDRL_OFFSET    0\n#define    RTL8367C_NIC_RXRDRL_MASK    0xFF\n\n#define    RTL8367C_REG_NIC_RXRDRH    0x1a05\n#define    RTL8367C_NIC_RXRDRH_OFFSET    0\n#define    RTL8367C_NIC_RXRDRH_MASK    0xFF\n\n#define    RTL8367C_REG_NIC_TXASRL    0x1a08\n#define    RTL8367C_NIC_TXASRL_OFFSET    0\n#define    RTL8367C_NIC_TXASRL_MASK    0xFF\n\n#define    RTL8367C_REG_NIC_TXASRH    0x1a09\n#define    RTL8367C_NIC_TXASRH_OFFSET    0\n#define    RTL8367C_NIC_TXASRH_MASK    0xFF\n\n#define    RTL8367C_REG_NIC_RXCMDR    0x1a0c\n#define    RTL8367C_NIC_RXCMDR_OFFSET    0\n#define    RTL8367C_NIC_RXCMDR_MASK    0x1\n\n#define    RTL8367C_REG_NIC_TXCMDR    0x1a0d\n#define    RTL8367C_NIC_TXCMDR_OFFSET    0\n#define    RTL8367C_NIC_TXCMDR_MASK    0x1\n\n#define    RTL8367C_REG_NIC_IMS    0x1a0e\n#define    RTL8367C_NIC_RXIS_OFFSET    7\n#define    RTL8367C_NIC_RXIS_MASK    0x80\n#define    RTL8367C_NIC_TXIS_OFFSET    6\n#define    RTL8367C_NIC_TXIS_MASK    0x40\n#define    RTL8367C_NIC_TXES_OFFSET    5\n#define    RTL8367C_NIC_TXES_MASK    0x20\n#define    RTL8367C_NIC_IMS_DMY_OFFSET    4\n#define    RTL8367C_NIC_IMS_DMY_MASK    0x10\n#define    RTL8367C_NIC_RXBUS_OFFSET    3\n#define    RTL8367C_NIC_RXBUS_MASK    0x8\n#define    RTL8367C_NIC_TXBOS_OFFSET    2\n#define    RTL8367C_NIC_TXBOS_MASK    0x4\n#define    RTL8367C_NIC_RXMIS_OFFSET    1\n#define    RTL8367C_NIC_RXMIS_MASK    0x2\n#define    RTL8367C_NIC_TXNLS_OFFSET    0\n#define    RTL8367C_NIC_TXNLS_MASK    0x1\n\n#define    RTL8367C_REG_NIC_IMR    0x1a0f\n#define    RTL8367C_NIC_RXIE_OFFSET    7\n#define    RTL8367C_NIC_RXIE_MASK    0x80\n#define    RTL8367C_NIC_TXIE_OFFSET    6\n#define    RTL8367C_NIC_TXIE_MASK    0x40\n#define    RTL8367C_NIC_TXEE_OFFSET    5\n#define    RTL8367C_NIC_TXEE_MASK    0x20\n#define    RTL8367C_NIC_IMR_DMY_OFFSET    4\n#define    RTL8367C_NIC_IMR_DMY_MASK    0x10\n#define    RTL8367C_NIC_RXBUE_OFFSET    3\n#define    RTL8367C_NIC_RXBUE_MASK    0x8\n#define    RTL8367C_NIC_TXBOE_OFFSET    2\n#define    RTL8367C_NIC_TXBOE_MASK    0x4\n#define    RTL8367C_NIC_RXMIE_OFFSET    1\n#define    RTL8367C_NIC_RXMIE_MASK    0x2\n#define    RTL8367C_NIC_TXNLE_OFFSET    0\n#define    RTL8367C_NIC_TXNLE_MASK    0x1\n\n#define    RTL8367C_REG_NIC_RXCR0    0x1a14\n#define    RTL8367C_NIC_HFPPE_OFFSET    7\n#define    RTL8367C_NIC_HFPPE_MASK    0x80\n#define    RTL8367C_NIC_HFMPE_OFFSET    6\n#define    RTL8367C_NIC_HFMPE_MASK    0x40\n#define    RTL8367C_NIC_RXBPE_OFFSET    5\n#define    RTL8367C_NIC_RXBPE_MASK    0x20\n#define    RTL8367C_NIC_RXMPE_OFFSET    4\n#define    RTL8367C_NIC_RXMPE_MASK    0x10\n#define    RTL8367C_NIC_RXPPS_OFFSET    2\n#define    RTL8367C_NIC_RXPPS_MASK    0xC\n#define    RTL8367C_NIC_RXAPE_OFFSET    1\n#define    RTL8367C_NIC_RXAPE_MASK    0x2\n#define    RTL8367C_NIC_ARPPE_OFFSET    0\n#define    RTL8367C_NIC_ARPPE_MASK    0x1\n\n#define    RTL8367C_REG_NIC_RXCR1    0x1a15\n#define    RTL8367C_NIC_RL4CEPE_OFFSET    4\n#define    RTL8367C_NIC_RL4CEPE_MASK    0x10\n#define    RTL8367C_NIC_RL3CEPE_OFFSET    3\n#define    RTL8367C_NIC_RL3CEPE_MASK    0x8\n#define    RTL8367C_NIC_RCRCEPE_OFFSET    2\n#define    RTL8367C_NIC_RCRCEPE_MASK    0x4\n#define    RTL8367C_NIC_RMCRC_OFFSET    1\n#define    RTL8367C_NIC_RMCRC_MASK    0x2\n#define    RTL8367C_NIC_RXENABLE_OFFSET    0\n#define    RTL8367C_NIC_RXENABLE_MASK    0x1\n\n#define    RTL8367C_REG_NIC_TXCR    0x1a16\n#define    RTL8367C_NIC_LBE_OFFSET    2\n#define    RTL8367C_NIC_LBE_MASK    0x4\n#define    RTL8367C_NIC_TXMFM_OFFSET    1\n#define    RTL8367C_NIC_TXMFM_MASK    0x2\n#define    RTL8367C_NIC_TXENABLE_OFFSET    0\n#define    RTL8367C_NIC_TXENABLE_MASK    0x1\n\n#define    RTL8367C_REG_NIC_GCR    0x1a17\n#define    RTL8367C_DUMMY_7_6_OFFSET    6\n#define    RTL8367C_DUMMY_7_6_MASK    0xC0\n#define    RTL8367C_NIC_RXMTU_OFFSET    4\n#define    RTL8367C_NIC_RXMTU_MASK    0x30\n#define    RTL8367C_NIC_GCR_DUMMY_0_OFFSET    0\n#define    RTL8367C_NIC_GCR_DUMMY_0_MASK    0x1\n\n#define    RTL8367C_REG_NIC_MHR0    0x1a24\n#define    RTL8367C_NIC_MHR0_OFFSET    0\n#define    RTL8367C_NIC_MHR0_MASK    0xFF\n\n#define    RTL8367C_REG_NIC_MHR1    0x1a25\n#define    RTL8367C_NIC_MHR1_OFFSET    0\n#define    RTL8367C_NIC_MHR1_MASK    0xFF\n\n#define    RTL8367C_REG_NIC_MHR2    0x1a26\n#define    RTL8367C_NIC_MHR2_OFFSET    0\n#define    RTL8367C_NIC_MHR2_MASK    0xFF\n\n#define    RTL8367C_REG_NIC_MHR3    0x1a27\n#define    RTL8367C_NIC_MHR3_OFFSET    0\n#define    RTL8367C_NIC_MHR3_MASK    0xFF\n\n#define    RTL8367C_REG_NIC_MHR4    0x1a28\n#define    RTL8367C_NIC_MHR4_OFFSET    0\n#define    RTL8367C_NIC_MHR4_MASK    0xFF\n\n#define    RTL8367C_REG_NIC_MHR5    0x1a29\n#define    RTL8367C_NIC_MHR5_OFFSET    0\n#define    RTL8367C_NIC_MHR5_MASK    0xFF\n\n#define    RTL8367C_REG_NIC_MHR6    0x1a2a\n#define    RTL8367C_NIC_MHR6_OFFSET    0\n#define    RTL8367C_NIC_MHR6_MASK    0xFF\n\n#define    RTL8367C_REG_NIC_MHR7    0x1a2b\n#define    RTL8367C_NIC_MHR7_OFFSET    0\n#define    RTL8367C_NIC_MHR7_MASK    0xFF\n\n#define    RTL8367C_REG_NIC_PAHR0    0x1a2c\n#define    RTL8367C_NIC_PAHR0_OFFSET    0\n#define    RTL8367C_NIC_PAHR0_MASK    0xFF\n\n#define    RTL8367C_REG_NIC_PAHR1    0x1a2d\n#define    RTL8367C_NIC_PAHR1_OFFSET    0\n#define    RTL8367C_NIC_PAHR1_MASK    0xFF\n\n#define    RTL8367C_REG_NIC_PAHR2    0x1a2e\n#define    RTL8367C_NIC_PAHR2_OFFSET    0\n#define    RTL8367C_NIC_PAHR2_MASK    0xFF\n\n#define    RTL8367C_REG_NIC_PAHR3    0x1a2f\n#define    RTL8367C_NIC_PAHR3_OFFSET    0\n#define    RTL8367C_NIC_PAHR3_MASK    0xFF\n\n#define    RTL8367C_REG_NIC_PAHR4    0x1a30\n#define    RTL8367C_NIC_PAHR4_OFFSET    0\n#define    RTL8367C_NIC_PAHR4_MASK    0xFF\n\n#define    RTL8367C_REG_NIC_PAHR5    0x1a31\n#define    RTL8367C_NIC_PAHR5_OFFSET    0\n#define    RTL8367C_NIC_PAHR5_MASK    0xFF\n\n#define    RTL8367C_REG_NIC_PAHR6    0x1a32\n#define    RTL8367C_NIC_PAHR6_OFFSET    0\n#define    RTL8367C_NIC_PAHR6_MASK    0xFF\n\n#define    RTL8367C_REG_NIC_PAHR7    0x1a33\n#define    RTL8367C_NIC_PAHR7_OFFSET    0\n#define    RTL8367C_NIC_PAHR7_MASK    0xFF\n\n#define    RTL8367C_REG_NIC_TXSTOPRL    0x1a44\n#define    RTL8367C_NIC_TXSTOPRL_OFFSET    0\n#define    RTL8367C_NIC_TXSTOPRL_MASK    0xFF\n\n#define    RTL8367C_REG_NIC_TXSTOPRH    0x1a45\n#define    RTL8367C_NIC_TXSTOPRH_OFFSET    0\n#define    RTL8367C_NIC_TXSTOPRH_MASK    0x3\n\n#define    RTL8367C_REG_NIC_RXSTOPRL    0x1a46\n#define    RTL8367C_NIC_RXSTOPRL_OFFSET    0\n#define    RTL8367C_NIC_RXSTOPRL_MASK    0xFF\n\n#define    RTL8367C_REG_NIC_RXSTOPRH    0x1a47\n#define    RTL8367C_NIC_RXSTOPRH_OFFSET    0\n#define    RTL8367C_NIC_RXSTOPRH_MASK    0x3\n\n#define    RTL8367C_REG_NIC_RXFSTR    0x1a48\n#define    RTL8367C_NIC_RXFSTR_OFFSET    0\n#define    RTL8367C_NIC_RXFSTR_MASK    0xFF\n\n#define    RTL8367C_REG_NIC_RXMBTRL    0x1a4c\n#define    RTL8367C_NIC_RXMBTRL_OFFSET    0\n#define    RTL8367C_NIC_RXMBTRL_MASK    0xFF\n\n#define    RTL8367C_REG_NIC_RXMBTRH    0x1a4d\n#define    RTL8367C_NIC_RXMBTRH_OFFSET    0\n#define    RTL8367C_NIC_RXMBTRH_MASK    0x7F\n\n#define    RTL8367C_REG_NIC_RXMPTR    0x1a4e\n#define    RTL8367C_NIC_RXMPTR_OFFSET    0\n#define    RTL8367C_NIC_RXMPTR_MASK    0xFF\n\n#define    RTL8367C_REG_NIC_T0TR    0x1a4f\n#define    RTL8367C_NIC_T0TR_OFFSET    0\n#define    RTL8367C_NIC_T0TR_MASK    0xFF\n\n#define    RTL8367C_REG_NIC_CRXCPRL    0x1a50\n#define    RTL8367C_NIC_CRXCPRL_OFFSET    0\n#define    RTL8367C_NIC_CRXCPRL_MASK    0xFF\n\n#define    RTL8367C_REG_NIC_CRXCPRH    0x1a51\n#define    RTL8367C_NIC_CRXCPRH_OFFSET    0\n#define    RTL8367C_NIC_CRXCPRH_MASK    0xFF\n\n#define    RTL8367C_REG_NIC_CTXCPRL    0x1a52\n#define    RTL8367C_NIC_CTXCPRL_OFFSET    0\n#define    RTL8367C_NIC_CTXCPRL_MASK    0xFF\n\n#define    RTL8367C_REG_NIC_CTXPCRH    0x1a53\n#define    RTL8367C_NIC_CTXPCRH_OFFSET    0\n#define    RTL8367C_NIC_CTXPCRH_MASK    0xFF\n\n#define    RTL8367C_REG_NIC_SRXCURPKTRL    0x1a54\n#define    RTL8367C_NIC_SRXCURPKTRL_OFFSET    0\n#define    RTL8367C_NIC_SRXCURPKTRL_MASK    0xFF\n\n#define    RTL8367C_REG_NIC_SRXCURPKTRH    0x1a55\n#define    RTL8367C_NIC_SRXCURPKTRH_OFFSET    0\n#define    RTL8367C_NIC_SRXCURPKTRH_MASK    0xFF\n\n#define    RTL8367C_REG_NIC_STXCURPKTRL    0x1a56\n#define    RTL8367C_NIC_STXCURPKTRL_OFFSET    0\n#define    RTL8367C_NIC_STXCURPKTRL_MASK    0xFF\n\n#define    RTL8367C_REG_NIC_STXCURPKTRH    0x1a57\n#define    RTL8367C_NIC_STXCURPKTRH_OFFSET    0\n#define    RTL8367C_NIC_STXCURPKTRH_MASK    0xFF\n\n#define    RTL8367C_REG_NIC_STXPKTLENRL    0x1a58\n#define    RTL8367C_NIC_STXPKTLENRL_OFFSET    0\n#define    RTL8367C_NIC_STXPKTLENRL_MASK    0xFF\n\n#define    RTL8367C_REG_NIC_STXPKTLENRH    0x1a59\n#define    RTL8367C_NIC_STXPKTLENRH_OFFSET    0\n#define    RTL8367C_NIC_STXPKTLENRH_MASK    0xFF\n\n#define    RTL8367C_REG_NIC_STXCURUNITRL    0x1a5a\n#define    RTL8367C_NIC_STXCURUNITRL_OFFSET    0\n#define    RTL8367C_NIC_STXCURUNITRL_MASK    0xFF\n\n#define    RTL8367C_REG_NIC_STXCURUNITRH    0x1a5b\n#define    RTL8367C_NIC_STXCURUNITRH_OFFSET    0\n#define    RTL8367C_NIC_STXCURUNITRH_MASK    0xFF\n\n#define    RTL8367C_REG_NIC_DROP_MODE    0x1a5c\n#define    RTL8367C_NIC_RXDV_MODE_OFFSET    1\n#define    RTL8367C_NIC_RXDV_MODE_MASK    0x2\n#define    RTL8367C_NIC_DROP_MODE_OFFSET    0\n#define    RTL8367C_NIC_DROP_MODE_MASK    0x1\n\n/* (16'h1b00)LED */\n\n#define    RTL8367C_REG_LED_SYS_CONFIG    0x1b00\n#define    RTL8367C_LED_SYS_CONFIG_DUMMY_15_OFFSET    15\n#define    RTL8367C_LED_SYS_CONFIG_DUMMY_15_MASK    0x8000\n#define    RTL8367C_LED_SERIAL_OUT_MODE_OFFSET    14\n#define    RTL8367C_LED_SERIAL_OUT_MODE_MASK    0x4000\n#define    RTL8367C_LED_EEE_LPI_MODE_OFFSET    13\n#define    RTL8367C_LED_EEE_LPI_MODE_MASK    0x2000\n#define    RTL8367C_LED_EEE_LPI_EN_OFFSET    12\n#define    RTL8367C_LED_EEE_LPI_EN_MASK    0x1000\n#define    RTL8367C_LED_EEE_LPI_10_OFFSET    11\n#define    RTL8367C_LED_EEE_LPI_10_MASK    0x800\n#define    RTL8367C_LED_EEE_CAP_10_OFFSET    10\n#define    RTL8367C_LED_EEE_CAP_10_MASK    0x400\n#define    RTL8367C_LED_LPI_SEL_OFFSET    8\n#define    RTL8367C_LED_LPI_SEL_MASK    0x300\n#define    RTL8367C_SERI_LED_ACT_LOW_OFFSET    7\n#define    RTL8367C_SERI_LED_ACT_LOW_MASK    0x80\n#define    RTL8367C_LED_POWERON_2_OFFSET    6\n#define    RTL8367C_LED_POWERON_2_MASK    0x40\n#define    RTL8367C_LED_POWERON_1_OFFSET    5\n#define    RTL8367C_LED_POWERON_1_MASK    0x20\n#define    RTL8367C_LED_POWERON_0_OFFSET    4\n#define    RTL8367C_LED_POWERON_0_MASK    0x10\n#define    RTL8367C_LED_IO_DISABLE_OFFSET    3\n#define    RTL8367C_LED_IO_DISABLE_MASK    0x8\n#define    RTL8367C_DUMMY_2_2_OFFSET    2\n#define    RTL8367C_DUMMY_2_2_MASK    0x4\n#define    RTL8367C_LED_SELECT_OFFSET    0\n#define    RTL8367C_LED_SELECT_MASK    0x3\n\n#define    RTL8367C_REG_LED_SYS_CONFIG2    0x1b01\n#define    RTL8367C_LED_SYS_CONFIG2_DUMMY_OFFSET    2\n#define    RTL8367C_LED_SYS_CONFIG2_DUMMY_MASK    0xFFFC\n#define    RTL8367C_GATE_LPTD_BYPASS_OFFSET    1\n#define    RTL8367C_GATE_LPTD_BYPASS_MASK    0x2\n#define    RTL8367C_LED_SPD_MODE_OFFSET    0\n#define    RTL8367C_LED_SPD_MODE_MASK    0x1\n\n#define    RTL8367C_REG_LED_MODE    0x1b02\n#define    RTL8367C_DLINK_TIME_OFFSET    15\n#define    RTL8367C_DLINK_TIME_MASK    0x8000\n#define    RTL8367C_LED_BUZZ_DUTY_OFFSET    14\n#define    RTL8367C_LED_BUZZ_DUTY_MASK    0x4000\n#define    RTL8367C_BUZZER_RATE_OFFSET    12\n#define    RTL8367C_BUZZER_RATE_MASK    0x3000\n#define    RTL8367C_LOOP_DETECT_MODE_OFFSET    11\n#define    RTL8367C_LOOP_DETECT_MODE_MASK    0x800\n#define    RTL8367C_SEL_PWRON_TIME_OFFSET    9\n#define    RTL8367C_SEL_PWRON_TIME_MASK    0x600\n#define    RTL8367C_EN_DLINK_LED_OFFSET    8\n#define    RTL8367C_EN_DLINK_LED_MASK    0x100\n#define    RTL8367C_LOOP_DETECT_RATE_OFFSET    6\n#define    RTL8367C_LOOP_DETECT_RATE_MASK    0xC0\n#define    RTL8367C_FORCE_RATE_OFFSET    4\n#define    RTL8367C_FORCE_RATE_MASK    0x30\n#define    RTL8367C_SEL_LEDRATE_OFFSET    1\n#define    RTL8367C_SEL_LEDRATE_MASK    0xE\n#define    RTL8367C_SPEED_UP_OFFSET    0\n#define    RTL8367C_SPEED_UP_MASK    0x1\n\n#define    RTL8367C_REG_LED_CONFIGURATION    0x1b03\n#define    RTL8367C_LED_CONFIGURATION_DUMMY_OFFSET    15\n#define    RTL8367C_LED_CONFIGURATION_DUMMY_MASK    0x8000\n#define    RTL8367C_LED_CONFIG_SEL_OFFSET    14\n#define    RTL8367C_LED_CONFIG_SEL_MASK    0x4000\n#define    RTL8367C_DATA_LED_OFFSET    12\n#define    RTL8367C_DATA_LED_MASK    0x3000\n#define    RTL8367C_LED2_CFG_OFFSET    8\n#define    RTL8367C_LED2_CFG_MASK    0xF00\n#define    RTL8367C_LED1_CFG_OFFSET    4\n#define    RTL8367C_LED1_CFG_MASK    0xF0\n#define    RTL8367C_LED0_CFG_OFFSET    0\n#define    RTL8367C_LED0_CFG_MASK    0xF\n\n#define    RTL8367C_REG_RTCT_RESULTS_CFG    0x1b04\n#define    RTL8367C_RTCT_2PAIR_FTT_OFFSET    15\n#define    RTL8367C_RTCT_2PAIR_FTT_MASK    0x8000\n#define    RTL8367C_RTCT_2PAIR_MODE_OFFSET    14\n#define    RTL8367C_RTCT_2PAIR_MODE_MASK    0x4000\n#define    RTL8367C_BLINK_EN_OFFSET    13\n#define    RTL8367C_BLINK_EN_MASK    0x2000\n#define    RTL8367C_TIMEOUT_OFFSET    12\n#define    RTL8367C_TIMEOUT_MASK    0x1000\n#define    RTL8367C_EN_CD_SAME_SHORT_OFFSET    11\n#define    RTL8367C_EN_CD_SAME_SHORT_MASK    0x800\n#define    RTL8367C_EN_CD_SAME_OPEN_OFFSET    10\n#define    RTL8367C_EN_CD_SAME_OPEN_MASK    0x400\n#define    RTL8367C_EN_CD_SAME_LINEDRIVER_OFFSET    9\n#define    RTL8367C_EN_CD_SAME_LINEDRIVER_MASK    0x200\n#define    RTL8367C_EN_CD_SAME_MISMATCH_OFFSET    8\n#define    RTL8367C_EN_CD_SAME_MISMATCH_MASK    0x100\n#define    RTL8367C_EN_CD_SHORT_OFFSET    7\n#define    RTL8367C_EN_CD_SHORT_MASK    0x80\n#define    RTL8367C_EN_AB_SHORT_OFFSET    6\n#define    RTL8367C_EN_AB_SHORT_MASK    0x40\n#define    RTL8367C_EN_CD_OPEN_OFFSET    5\n#define    RTL8367C_EN_CD_OPEN_MASK    0x20\n#define    RTL8367C_EN_AB_OPEN_OFFSET    4\n#define    RTL8367C_EN_AB_OPEN_MASK    0x10\n#define    RTL8367C_EN_CD_MISMATCH_OFFSET    3\n#define    RTL8367C_EN_CD_MISMATCH_MASK    0x8\n#define    RTL8367C_EN_AB_MISMATCH_OFFSET    2\n#define    RTL8367C_EN_AB_MISMATCH_MASK    0x4\n#define    RTL8367C_EN_CD_LINEDRIVER_OFFSET    1\n#define    RTL8367C_EN_CD_LINEDRIVER_MASK    0x2\n#define    RTL8367C_EN_AB_LINEDRIVER_OFFSET    0\n#define    RTL8367C_EN_AB_LINEDRIVER_MASK    0x1\n\n#define    RTL8367C_REG_RTCT_LED    0x1b05\n#define    RTL8367C_DUMMY_1b05a_OFFSET    12\n#define    RTL8367C_DUMMY_1b05a_MASK    0xF000\n#define    RTL8367C_RTCT_LED2_OFFSET    8\n#define    RTL8367C_RTCT_LED2_MASK    0xF00\n#define    RTL8367C_RTCT_LED1_OFFSET    4\n#define    RTL8367C_RTCT_LED1_MASK    0xF0\n#define    RTL8367C_RTCT_LED0_OFFSET    0\n#define    RTL8367C_RTCT_LED0_MASK    0xF\n\n#define    RTL8367C_REG_CPU_FORCE_LED_CFG    0x1b07\n#define    RTL8367C_DUMMY_1b07a_OFFSET    8\n#define    RTL8367C_DUMMY_1b07a_MASK    0xFF00\n#define    RTL8367C_LED_FORCE_MODE_OFFSET    2\n#define    RTL8367C_LED_FORCE_MODE_MASK    0xFC\n#define    RTL8367C_FORCE_MODE_OFFSET    0\n#define    RTL8367C_FORCE_MODE_MASK    0x3\n\n#define    RTL8367C_REG_CPU_FORCE_LED0_CFG0    0x1b08\n#define    RTL8367C_PORT7_LED0_MODE_OFFSET    14\n#define    RTL8367C_PORT7_LED0_MODE_MASK    0xC000\n#define    RTL8367C_PORT6_LED0_MODE_OFFSET    12\n#define    RTL8367C_PORT6_LED0_MODE_MASK    0x3000\n#define    RTL8367C_PORT5_LED0_MODE_OFFSET    10\n#define    RTL8367C_PORT5_LED0_MODE_MASK    0xC00\n#define    RTL8367C_PORT4_LED0_MODE_OFFSET    8\n#define    RTL8367C_PORT4_LED0_MODE_MASK    0x300\n#define    RTL8367C_PORT3_LED0_MODE_OFFSET    6\n#define    RTL8367C_PORT3_LED0_MODE_MASK    0xC0\n#define    RTL8367C_PORT2_LED0_MODE_OFFSET    4\n#define    RTL8367C_PORT2_LED0_MODE_MASK    0x30\n#define    RTL8367C_PORT1_LED0_MODE_OFFSET    2\n#define    RTL8367C_PORT1_LED0_MODE_MASK    0xC\n#define    RTL8367C_PORT0_LED0_MODE_OFFSET    0\n#define    RTL8367C_PORT0_LED0_MODE_MASK    0x3\n\n#define    RTL8367C_REG_CPU_FORCE_LED0_CFG1    0x1b09\n#define    RTL8367C_DUMMY_1b09a_OFFSET    4\n#define    RTL8367C_DUMMY_1b09a_MASK    0xFFF0\n#define    RTL8367C_PORT9_LED0_MODE_OFFSET    2\n#define    RTL8367C_PORT9_LED0_MODE_MASK    0xC\n#define    RTL8367C_PORT8_LED0_MODE_OFFSET    0\n#define    RTL8367C_PORT8_LED0_MODE_MASK    0x3\n\n#define    RTL8367C_REG_CPU_FORCE_LED1_CFG0    0x1b0a\n#define    RTL8367C_PORT7_LED1_MODE_OFFSET    14\n#define    RTL8367C_PORT7_LED1_MODE_MASK    0xC000\n#define    RTL8367C_PORT6_LED1_MODE_OFFSET    12\n#define    RTL8367C_PORT6_LED1_MODE_MASK    0x3000\n#define    RTL8367C_PORT5_LED1_MODE_OFFSET    10\n#define    RTL8367C_PORT5_LED1_MODE_MASK    0xC00\n#define    RTL8367C_PORT4_LED1_MODE_OFFSET    8\n#define    RTL8367C_PORT4_LED1_MODE_MASK    0x300\n#define    RTL8367C_PORT3_LED1_MODE_OFFSET    6\n#define    RTL8367C_PORT3_LED1_MODE_MASK    0xC0\n#define    RTL8367C_PORT2_LED1_MODE_OFFSET    4\n#define    RTL8367C_PORT2_LED1_MODE_MASK    0x30\n#define    RTL8367C_PORT1_LED1_MODE_OFFSET    2\n#define    RTL8367C_PORT1_LED1_MODE_MASK    0xC\n#define    RTL8367C_PORT0_LED1_MODE_OFFSET    0\n#define    RTL8367C_PORT0_LED1_MODE_MASK    0x3\n\n#define    RTL8367C_REG_CPU_FORCE_LED1_CFG1    0x1b0b\n#define    RTL8367C_DUMMY_1b0ba_OFFSET    4\n#define    RTL8367C_DUMMY_1b0ba_MASK    0xFFF0\n#define    RTL8367C_PORT9_LED1_MODE_OFFSET    2\n#define    RTL8367C_PORT9_LED1_MODE_MASK    0xC\n#define    RTL8367C_PORT8_LED1_MODE_OFFSET    0\n#define    RTL8367C_PORT8_LED1_MODE_MASK    0x3\n\n#define    RTL8367C_REG_CPU_FORCE_LED2_CFG0    0x1b0c\n#define    RTL8367C_PORT7_LED2_MODE_OFFSET    14\n#define    RTL8367C_PORT7_LED2_MODE_MASK    0xC000\n#define    RTL8367C_PORT6_LED2_MODE_OFFSET    12\n#define    RTL8367C_PORT6_LED2_MODE_MASK    0x3000\n#define    RTL8367C_PORT5_LED2_MODE_OFFSET    10\n#define    RTL8367C_PORT5_LED2_MODE_MASK    0xC00\n#define    RTL8367C_PORT4_LED2_MODE_OFFSET    8\n#define    RTL8367C_PORT4_LED2_MODE_MASK    0x300\n#define    RTL8367C_PORT3_LED2_MODE_OFFSET    6\n#define    RTL8367C_PORT3_LED2_MODE_MASK    0xC0\n#define    RTL8367C_PORT2_LED2_MODE_OFFSET    4\n#define    RTL8367C_PORT2_LED2_MODE_MASK    0x30\n#define    RTL8367C_PORT1_LED2_MODE_OFFSET    2\n#define    RTL8367C_PORT1_LED2_MODE_MASK    0xC\n#define    RTL8367C_PORT0_LED2_MODE_OFFSET    0\n#define    RTL8367C_PORT0_LED2_MODE_MASK    0x3\n\n#define    RTL8367C_REG_CPU_FORCE_LED2_CFG1    0x1b0d\n#define    RTL8367C_DUMMY_1b0da_OFFSET    4\n#define    RTL8367C_DUMMY_1b0da_MASK    0xFFF0\n#define    RTL8367C_PORT9_LED2_MODE_OFFSET    2\n#define    RTL8367C_PORT9_LED2_MODE_MASK    0xC\n#define    RTL8367C_PORT8_LED2_MODE_OFFSET    0\n#define    RTL8367C_PORT8_LED2_MODE_MASK    0x3\n\n#define    RTL8367C_REG_LED_ACTIVE_LOW_CFG0    0x1b0e\n#define    RTL8367C_LED_ACTIVE_LOW_CFG0_DUMMY_15_OFFSET    15\n#define    RTL8367C_LED_ACTIVE_LOW_CFG0_DUMMY_15_MASK    0x8000\n#define    RTL8367C_PORT3_LED_ACTIVE_LOW_OFFSET    12\n#define    RTL8367C_PORT3_LED_ACTIVE_LOW_MASK    0x7000\n#define    RTL8367C_LED_ACTIVE_LOW_CFG0_DUMMY_11_OFFSET    11\n#define    RTL8367C_LED_ACTIVE_LOW_CFG0_DUMMY_11_MASK    0x800\n#define    RTL8367C_PORT2_LED_ACTIVE_LOW_OFFSET    8\n#define    RTL8367C_PORT2_LED_ACTIVE_LOW_MASK    0x700\n#define    RTL8367C_DUMMY_7_OFFSET    7\n#define    RTL8367C_DUMMY_7_MASK    0x80\n#define    RTL8367C_PORT1_LED_ACTIVE_LOW_OFFSET    4\n#define    RTL8367C_PORT1_LED_ACTIVE_LOW_MASK    0x70\n#define    RTL8367C_DUMMY_3_OFFSET    3\n#define    RTL8367C_DUMMY_3_MASK    0x8\n#define    RTL8367C_PORT0_LED_ACTIVE_LOW_OFFSET    0\n#define    RTL8367C_PORT0_LED_ACTIVE_LOW_MASK    0x7\n\n#define    RTL8367C_REG_LED_ACTIVE_LOW_CFG1    0x1b0f\n#define    RTL8367C_LED_ACTIVE_LOW_CFG1_DUMMY_15_OFFSET    15\n#define    RTL8367C_LED_ACTIVE_LOW_CFG1_DUMMY_15_MASK    0x8000\n#define    RTL8367C_PORT7_LED_ACTIVE_LOW_OFFSET    12\n#define    RTL8367C_PORT7_LED_ACTIVE_LOW_MASK    0x7000\n#define    RTL8367C_LED_ACTIVE_LOW_CFG1_DUMMY_11_OFFSET    11\n#define    RTL8367C_LED_ACTIVE_LOW_CFG1_DUMMY_11_MASK    0x800\n#define    RTL8367C_PORT6_LED_ACTIVE_LOW_OFFSET    8\n#define    RTL8367C_PORT6_LED_ACTIVE_LOW_MASK    0x700\n#define    RTL8367C_DUMMY_1b0f_b_OFFSET    7\n#define    RTL8367C_DUMMY_1b0f_b_MASK    0x80\n#define    RTL8367C_PORT5_LED_ACTIVE_LOW_OFFSET    4\n#define    RTL8367C_PORT5_LED_ACTIVE_LOW_MASK    0x70\n#define    RTL8367C_DUMMY_1b0f_a_OFFSET    3\n#define    RTL8367C_DUMMY_1b0f_a_MASK    0x8\n#define    RTL8367C_PORT4_LED_ACTIVE_LOW_OFFSET    0\n#define    RTL8367C_PORT4_LED_ACTIVE_LOW_MASK    0x7\n\n#define    RTL8367C_REG_LED_ACTIVE_LOW_CFG2    0x1b10\n#define    RTL8367C_DUMMY_1b10_b_OFFSET    7\n#define    RTL8367C_DUMMY_1b10_b_MASK    0xFF80\n#define    RTL8367C_PORT9_LED_ACTIVE_LOW_OFFSET    4\n#define    RTL8367C_PORT9_LED_ACTIVE_LOW_MASK    0x70\n#define    RTL8367C_DUMMY_1b10_a_OFFSET    3\n#define    RTL8367C_DUMMY_1b10_a_MASK    0x8\n#define    RTL8367C_PORT8_LED_ACTIVE_LOW_OFFSET    0\n#define    RTL8367C_PORT8_LED_ACTIVE_LOW_MASK    0x7\n\n#define    RTL8367C_REG_SEL_RTCT_PARA    0x1b21\n#define    RTL8367C_DO_RTCT_COMMAND_OFFSET    15\n#define    RTL8367C_DO_RTCT_COMMAND_MASK    0x8000\n#define    RTL8367C_SEL_RTCT_PARA_DUMMY_OFFSET    12\n#define    RTL8367C_SEL_RTCT_PARA_DUMMY_MASK    0x7000\n#define    RTL8367C_SEL_RTCT_RLSTLED_TIME_OFFSET    10\n#define    RTL8367C_SEL_RTCT_RLSTLED_TIME_MASK    0xC00\n#define    RTL8367C_SEL_RTCT_TEST_LED_TIME_OFFSET    8\n#define    RTL8367C_SEL_RTCT_TEST_LED_TIME_MASK    0x300\n#define    RTL8367C_EN_SCAN_RTCT_OFFSET    7\n#define    RTL8367C_EN_SCAN_RTCT_MASK    0x80\n#define    RTL8367C_EN_RTCT_TIMOUT_OFFSET    6\n#define    RTL8367C_EN_RTCT_TIMOUT_MASK    0x40\n#define    RTL8367C_EN_ALL_RTCT_OFFSET    5\n#define    RTL8367C_EN_ALL_RTCT_MASK    0x20\n#define    RTL8367C_SEL_RTCT_PLE_WID_OFFSET    0\n#define    RTL8367C_SEL_RTCT_PLE_WID_MASK    0x1F\n\n#define    RTL8367C_REG_RTCT_ENABLE    0x1b22\n#define    RTL8367C_RTCT_ENABLE_DUMMY_OFFSET    8\n#define    RTL8367C_RTCT_ENABLE_DUMMY_MASK    0xFF00\n#define    RTL8367C_RTCT_ENABLE_PORT_MASK_OFFSET    0\n#define    RTL8367C_RTCT_ENABLE_PORT_MASK_MASK    0xFF\n\n#define    RTL8367C_REG_RTCT_TIMEOUT    0x1b23\n\n#define    RTL8367C_REG_PARA_LED_IO_EN1    0x1b24\n#define    RTL8367C_LED1_PARA_P07_00_OFFSET    8\n#define    RTL8367C_LED1_PARA_P07_00_MASK    0xFF00\n#define    RTL8367C_LED0_PARA_P07_00_OFFSET    0\n#define    RTL8367C_LED0_PARA_P07_00_MASK    0xFF\n\n#define    RTL8367C_REG_PARA_LED_IO_EN2    0x1b25\n#define    RTL8367C_DUMMY_15_8_OFFSET    8\n#define    RTL8367C_DUMMY_15_8_MASK    0xFF00\n#define    RTL8367C_LED2_PARA_P07_00_OFFSET    0\n#define    RTL8367C_LED2_PARA_P07_00_MASK    0xFF\n\n#define    RTL8367C_REG_SCAN0_LED_IO_EN1    0x1b26\n#define    RTL8367C_SCAN0_LED_IO_EN1_DUMMY_OFFSET    3\n#define    RTL8367C_SCAN0_LED_IO_EN1_DUMMY_MASK    0xFFF8\n#define    RTL8367C_LED_LOOP_DET_BUZZER_EN_OFFSET    2\n#define    RTL8367C_LED_LOOP_DET_BUZZER_EN_MASK    0x4\n#define    RTL8367C_LED_SERI_DATA_EN_OFFSET    1\n#define    RTL8367C_LED_SERI_DATA_EN_MASK    0x2\n#define    RTL8367C_LED_SERI_CLK_EN_OFFSET    0\n#define    RTL8367C_LED_SERI_CLK_EN_MASK    0x1\n\n#define    RTL8367C_REG_SCAN1_LED_IO_EN2    0x1b27\n#define    RTL8367C_LED_SCAN1_BI_PORT_EN_OFFSET    8\n#define    RTL8367C_LED_SCAN1_BI_PORT_EN_MASK    0xFF00\n#define    RTL8367C_LED_SCAN1_BI_STA_EN_OFFSET    7\n#define    RTL8367C_LED_SCAN1_BI_STA_EN_MASK    0x80\n#define    RTL8367C_SCAN1_LED_IO_EN2_DUMMY_0_OFFSET    6\n#define    RTL8367C_SCAN1_LED_IO_EN2_DUMMY_0_MASK    0x40\n#define    RTL8367C_LED_SCAN1_SI_PORT_EN_OFFSET    2\n#define    RTL8367C_LED_SCAN1_SI_PORT_EN_MASK    0x3C\n#define    RTL8367C_LED_SCAN1_SI_STA_EN_OFFSET    0\n#define    RTL8367C_LED_SCAN1_SI_STA_EN_MASK    0x3\n\n#define    RTL8367C_REG_LPI_LED_OPT1    0x1b28\n#define    RTL8367C_LPI_TAG4_OFFSET    12\n#define    RTL8367C_LPI_TAG4_MASK    0xF000\n#define    RTL8367C_LPI_TAG3_OFFSET    8\n#define    RTL8367C_LPI_TAG3_MASK    0xF00\n#define    RTL8367C_LPI_TAG2_OFFSET    4\n#define    RTL8367C_LPI_TAG2_MASK    0xF0\n#define    RTL8367C_LPI_TAG1_OFFSET    0\n#define    RTL8367C_LPI_TAG1_MASK    0xF\n\n#define    RTL8367C_REG_LPI_LED_OPT2    0x1b29\n#define    RTL8367C_LPI_LED_OPT2_DUMMY_OFFSET    15\n#define    RTL8367C_LPI_LED_OPT2_DUMMY_MASK    0x8000\n#define    RTL8367C_LPI_LED2_WEAK_OFFSET    14\n#define    RTL8367C_LPI_LED2_WEAK_MASK    0x4000\n#define    RTL8367C_LPI_LED1_WEAK_OFFSET    13\n#define    RTL8367C_LPI_LED1_WEAK_MASK    0x2000\n#define    RTL8367C_LPI_LED0_WEAK_OFFSET    12\n#define    RTL8367C_LPI_LED0_WEAK_MASK    0x1000\n#define    RTL8367C_LPI_LED2_OFFSET    11\n#define    RTL8367C_LPI_LED2_MASK    0x800\n#define    RTL8367C_LPI_LED1_OFFSET    10\n#define    RTL8367C_LPI_LED1_MASK    0x400\n#define    RTL8367C_LPI_LED0_OFFSET    9\n#define    RTL8367C_LPI_LED0_MASK    0x200\n#define    RTL8367C_LPI_TAG8_OFFSET    8\n#define    RTL8367C_LPI_TAG8_MASK    0x100\n#define    RTL8367C_LPI_TAG7_OFFSET    6\n#define    RTL8367C_LPI_TAG7_MASK    0xC0\n#define    RTL8367C_LPI_TAG6_OFFSET    4\n#define    RTL8367C_LPI_TAG6_MASK    0x30\n#define    RTL8367C_LPI_TAG5_OFFSET    0\n#define    RTL8367C_LPI_TAG5_MASK    0xF\n\n#define    RTL8367C_REG_LPI_LED_OPT3    0x1b2a\n#define    RTL8367C_LPI_LED_OPT3_DUMMY_OFFSET    3\n#define    RTL8367C_LPI_LED_OPT3_DUMMY_MASK    0xFFF8\n#define    RTL8367C_RESTORE_LED_RATE_SEL_OFFSET    1\n#define    RTL8367C_RESTORE_LED_RATE_SEL_MASK    0x6\n#define    RTL8367C_RESTORE_LED_SEL_OFFSET    0\n#define    RTL8367C_RESTORE_LED_SEL_MASK    0x1\n\n#define    RTL8367C_REG_P0_LED_MUX    0x1b2b\n#define    RTL8367C_CFG_P0_LED2_MUX_OFFSET    10\n#define    RTL8367C_CFG_P0_LED2_MUX_MASK    0x7C00\n#define    RTL8367C_CFG_P0_LED1_MUX_OFFSET    5\n#define    RTL8367C_CFG_P0_LED1_MUX_MASK    0x3E0\n#define    RTL8367C_CFG_P0_LED0_MUX_OFFSET    0\n#define    RTL8367C_CFG_P0_LED0_MUX_MASK    0x1F\n\n#define    RTL8367C_REG_P1_LED_MUX    0x1b2c\n#define    RTL8367C_CFG_P1_LED2_MUX_OFFSET    10\n#define    RTL8367C_CFG_P1_LED2_MUX_MASK    0x7C00\n#define    RTL8367C_CFG_P1_LED1_MUX_OFFSET    5\n#define    RTL8367C_CFG_P1_LED1_MUX_MASK    0x3E0\n#define    RTL8367C_CFG_P1_LED0_MUX_OFFSET    0\n#define    RTL8367C_CFG_P1_LED0_MUX_MASK    0x1F\n\n#define    RTL8367C_REG_P2_LED_MUX    0x1b2d\n#define    RTL8367C_CFG_P2_LED2_MUX_OFFSET    10\n#define    RTL8367C_CFG_P2_LED2_MUX_MASK    0x7C00\n#define    RTL8367C_CFG_P2_LED1_MUX_OFFSET    5\n#define    RTL8367C_CFG_P2_LED1_MUX_MASK    0x3E0\n#define    RTL8367C_CFG_P2_LED0_MUX_OFFSET    0\n#define    RTL8367C_CFG_P2_LED0_MUX_MASK    0x1F\n\n#define    RTL8367C_REG_P3_LED_MUX    0x1b2e\n#define    RTL8367C_CFG_P3_LED2_MUX_OFFSET    10\n#define    RTL8367C_CFG_P3_LED2_MUX_MASK    0x7C00\n#define    RTL8367C_CFG_P3_LED1_MUX_OFFSET    5\n#define    RTL8367C_CFG_P3_LED1_MUX_MASK    0x3E0\n#define    RTL8367C_CFG_P3_LED0_MUX_OFFSET    0\n#define    RTL8367C_CFG_P3_LED0_MUX_MASK    0x1F\n\n#define    RTL8367C_REG_P4_LED_MUX    0x1b2f\n#define    RTL8367C_CFG_P4_LED2_MUX_OFFSET    10\n#define    RTL8367C_CFG_P4_LED2_MUX_MASK    0x7C00\n#define    RTL8367C_CFG_P4_LED1_MUX_OFFSET    5\n#define    RTL8367C_CFG_P4_LED1_MUX_MASK    0x3E0\n#define    RTL8367C_CFG_P4_LED0_MUX_OFFSET    0\n#define    RTL8367C_CFG_P4_LED0_MUX_MASK    0x1F\n\n#define    RTL8367C_REG_LED0_DATA_CTRL    0x1b30\n#define    RTL8367C_CFG_DATA_LED0_SEL_OFFSET    6\n#define    RTL8367C_CFG_DATA_LED0_SEL_MASK    0x40\n#define    RTL8367C_CFG_DATA_LED0_ACT_OFFSET    4\n#define    RTL8367C_CFG_DATA_LED0_ACT_MASK    0x30\n#define    RTL8367C_CFG_DATA_LED0_SPD_OFFSET    0\n#define    RTL8367C_CFG_DATA_LED0_SPD_MASK    0xF\n\n#define    RTL8367C_REG_LED1_DATA_CTRL    0x1b31\n#define    RTL8367C_CFG_DATA_LED1_SEL_OFFSET    6\n#define    RTL8367C_CFG_DATA_LED1_SEL_MASK    0x40\n#define    RTL8367C_CFG_DATA_LED1_ACT_OFFSET    4\n#define    RTL8367C_CFG_DATA_LED1_ACT_MASK    0x30\n#define    RTL8367C_CFG_DATA_LED1_SPD_OFFSET    0\n#define    RTL8367C_CFG_DATA_LED1_SPD_MASK    0xF\n\n#define    RTL8367C_REG_LED2_DATA_CTRL    0x1b32\n#define    RTL8367C_CFG_DATA_LED2_SEL_OFFSET    6\n#define    RTL8367C_CFG_DATA_LED2_SEL_MASK    0x40\n#define    RTL8367C_CFG_DATA_LED2_ACT_OFFSET    4\n#define    RTL8367C_CFG_DATA_LED2_ACT_MASK    0x30\n#define    RTL8367C_CFG_DATA_LED2_SPD_OFFSET    0\n#define    RTL8367C_CFG_DATA_LED2_SPD_MASK    0xF\n\n#define    RTL8367C_REG_PARA_LED_IO_EN3    0x1b33\n#define    RTL8367C_dummy_1b33a_OFFSET    6\n#define    RTL8367C_dummy_1b33a_MASK    0xFFC0\n#define    RTL8367C_LED2_PARA_P09_08_OFFSET    4\n#define    RTL8367C_LED2_PARA_P09_08_MASK    0x30\n#define    RTL8367C_LED1_PARA_P09_08_OFFSET    2\n#define    RTL8367C_LED1_PARA_P09_08_MASK    0xC\n#define    RTL8367C_LED0_PARA_P09_08_OFFSET    0\n#define    RTL8367C_LED0_PARA_P09_08_MASK    0x3\n\n#define    RTL8367C_REG_SCAN1_LED_IO_EN3    0x1b34\n#define    RTL8367C_dummy_1b34a_OFFSET    3\n#define    RTL8367C_dummy_1b34a_MASK    0xFFF8\n#define    RTL8367C_LED_SCAN1_BI_PORT9_8_EN_OFFSET    1\n#define    RTL8367C_LED_SCAN1_BI_PORT9_8_EN_MASK    0x6\n#define    RTL8367C_LED_SCAN1_SI_PORT9_8_EN_OFFSET    0\n#define    RTL8367C_LED_SCAN1_SI_PORT9_8_EN_MASK    0x1\n\n#define    RTL8367C_REG_P5_LED_MUX    0x1b35\n#define    RTL8367C_CFG_P5_LED2_MUX_OFFSET    10\n#define    RTL8367C_CFG_P5_LED2_MUX_MASK    0x7C00\n#define    RTL8367C_CFG_P5_LED1_MUX_OFFSET    5\n#define    RTL8367C_CFG_P5_LED1_MUX_MASK    0x3E0\n#define    RTL8367C_CFG_P5_LED0_MUX_OFFSET    0\n#define    RTL8367C_CFG_P5_LED0_MUX_MASK    0x1F\n\n#define    RTL8367C_REG_P6_LED_MUX    0x1b36\n#define    RTL8367C_CFG_P6_LED2_MUX_OFFSET    10\n#define    RTL8367C_CFG_P6_LED2_MUX_MASK    0x7C00\n#define    RTL8367C_CFG_P6_LED1_MUX_OFFSET    5\n#define    RTL8367C_CFG_P6_LED1_MUX_MASK    0x3E0\n#define    RTL8367C_CFG_P6_LED0_MUX_OFFSET    0\n#define    RTL8367C_CFG_P6_LED0_MUX_MASK    0x1F\n\n#define    RTL8367C_REG_P7_LED_MUX    0x1b37\n#define    RTL8367C_CFG_P7_LED2_MUX_OFFSET    10\n#define    RTL8367C_CFG_P7_LED2_MUX_MASK    0x7C00\n#define    RTL8367C_CFG_P7_LED1_MUX_OFFSET    5\n#define    RTL8367C_CFG_P7_LED1_MUX_MASK    0x3E0\n#define    RTL8367C_CFG_P7_LED0_MUX_OFFSET    0\n#define    RTL8367C_CFG_P7_LED0_MUX_MASK    0x1F\n\n#define    RTL8367C_REG_P8_LED_MUX    0x1b38\n#define    RTL8367C_CFG_P8_LED2_MUX_OFFSET    10\n#define    RTL8367C_CFG_P8_LED2_MUX_MASK    0x7C00\n#define    RTL8367C_CFG_P8_LED1_MUX_OFFSET    5\n#define    RTL8367C_CFG_P8_LED1_MUX_MASK    0x3E0\n#define    RTL8367C_CFG_P8_LED0_MUX_OFFSET    0\n#define    RTL8367C_CFG_P8_LED0_MUX_MASK    0x1F\n\n#define    RTL8367C_REG_P9_LED_MUX    0x1b39\n#define    RTL8367C_CFG_P9_LED2_MUX_OFFSET    10\n#define    RTL8367C_CFG_P9_LED2_MUX_MASK    0x7C00\n#define    RTL8367C_CFG_P9_LED1_MUX_OFFSET    5\n#define    RTL8367C_CFG_P9_LED1_MUX_MASK    0x3E0\n#define    RTL8367C_CFG_P9_LED0_MUX_OFFSET    0\n#define    RTL8367C_CFG_P9_LED0_MUX_MASK    0x1F\n\n#define    RTL8367C_REG_SERIAL_LED_CTRL    0x1b3a\n#define    RTL8367C_SERIAL_LED_SHIFT_SEQUENCE_OFFSET    13\n#define    RTL8367C_SERIAL_LED_SHIFT_SEQUENCE_MASK    0x6000\n#define    RTL8367C_SERIAL_LED_SHIFT_SEQUENCE_EN_OFFSET    12\n#define    RTL8367C_SERIAL_LED_SHIFT_SEQUENCE_EN_MASK    0x1000\n#define    RTL8367C_SERIAL_LED_GROUP_NUM_OFFSET    10\n#define    RTL8367C_SERIAL_LED_GROUP_NUM_MASK    0xC00\n#define    RTL8367C_SERIAL_LED_PORT_EN_OFFSET    0\n#define    RTL8367C_SERIAL_LED_PORT_EN_MASK    0x3FF\n\n/* (16'h1c00)IGMP_EAV */\n\n#define    RTL8367C_REG_IGMP_MLD_CFG0    0x1c00\n#define    RTL8367C_IGMP_MLD_PORTISO_LEAKY_OFFSET    15\n#define    RTL8367C_IGMP_MLD_PORTISO_LEAKY_MASK    0x8000\n#define    RTL8367C_IGMP_MLD_VLAN_LEAKY_OFFSET    14\n#define    RTL8367C_IGMP_MLD_VLAN_LEAKY_MASK    0x4000\n#define    RTL8367C_IGMP_MLD_DISCARD_STORM_FILTER_OFFSET    13\n#define    RTL8367C_IGMP_MLD_DISCARD_STORM_FILTER_MASK    0x2000\n#define    RTL8367C_REPORT_FORWARD_OFFSET    12\n#define    RTL8367C_REPORT_FORWARD_MASK    0x1000\n#define    RTL8367C_ROBURSTNESS_VAR_OFFSET    9\n#define    RTL8367C_ROBURSTNESS_VAR_MASK    0xE00\n#define    RTL8367C_LEAVE_SUPPRESSION_OFFSET    8\n#define    RTL8367C_LEAVE_SUPPRESSION_MASK    0x100\n#define    RTL8367C_REPORT_SUPPRESSION_OFFSET    7\n#define    RTL8367C_REPORT_SUPPRESSION_MASK    0x80\n#define    RTL8367C_LEAVE_TIMER_OFFSET    4\n#define    RTL8367C_LEAVE_TIMER_MASK    0x70\n#define    RTL8367C_FAST_LEAVE_EN_OFFSET    3\n#define    RTL8367C_FAST_LEAVE_EN_MASK    0x8\n#define    RTL8367C_CKS_ERR_OP_OFFSET    1\n#define    RTL8367C_CKS_ERR_OP_MASK    0x6\n#define    RTL8367C_IGMP_MLD_EN_OFFSET    0\n#define    RTL8367C_IGMP_MLD_EN_MASK    0x1\n\n#define    RTL8367C_REG_IGMP_MLD_CFG1    0x1c01\n#define    RTL8367C_DROP_LEAVE_ZERO_OFFSET    2\n#define    RTL8367C_DROP_LEAVE_ZERO_MASK    0x4\n#define    RTL8367C_TABLE_FULL_OP_OFFSET    0\n#define    RTL8367C_TABLE_FULL_OP_MASK    0x3\n\n#define    RTL8367C_REG_IGMP_MLD_CFG2    0x1c02\n\n#define    RTL8367C_REG_IGMP_DYNAMIC_ROUTER_PORT    0x1c03\n#define    RTL8367C_D_ROUTER_PORT_2_OFFSET    11\n#define    RTL8367C_D_ROUTER_PORT_2_MASK    0x7800\n#define    RTL8367C_D_ROUTER_PORT_TMR_2_OFFSET    8\n#define    RTL8367C_D_ROUTER_PORT_TMR_2_MASK    0x700\n#define    RTL8367C_D_ROUTER_PORT_1_OFFSET    3\n#define    RTL8367C_D_ROUTER_PORT_1_MASK    0x78\n#define    RTL8367C_D_ROUTER_PORT_TMR_1_OFFSET    0\n#define    RTL8367C_D_ROUTER_PORT_TMR_1_MASK    0x7\n\n#define    RTL8367C_REG_IGMP_STATIC_ROUTER_PORT    0x1c04\n#define    RTL8367C_IGMP_STATIC_ROUTER_PORT_OFFSET    0\n#define    RTL8367C_IGMP_STATIC_ROUTER_PORT_MASK    0x7FF\n\n#define    RTL8367C_REG_IGMP_PORT0_CONTROL    0x1c05\n#define    RTL8367C_IGMP_PORT0_CONTROL_ALLOW_QUERY_OFFSET    14\n#define    RTL8367C_IGMP_PORT0_CONTROL_ALLOW_QUERY_MASK    0x4000\n#define    RTL8367C_IGMP_PORT0_CONTROL_ALLOW_REPORT_OFFSET    13\n#define    RTL8367C_IGMP_PORT0_CONTROL_ALLOW_REPORT_MASK    0x2000\n#define    RTL8367C_IGMP_PORT0_CONTROL_ALLOW_LEAVE_OFFSET    12\n#define    RTL8367C_IGMP_PORT0_CONTROL_ALLOW_LEAVE_MASK    0x1000\n#define    RTL8367C_IGMP_PORT0_CONTROL_ALLOW_MRP_OFFSET    11\n#define    RTL8367C_IGMP_PORT0_CONTROL_ALLOW_MRP_MASK    0x800\n#define    RTL8367C_IGMP_PORT0_CONTROL_ALLOW_MC_DATA_OFFSET    10\n#define    RTL8367C_IGMP_PORT0_CONTROL_ALLOW_MC_DATA_MASK    0x400\n#define    RTL8367C_IGMP_PORT0_CONTROL_MLDv2_OP_OFFSET    8\n#define    RTL8367C_IGMP_PORT0_CONTROL_MLDv2_OP_MASK    0x300\n#define    RTL8367C_IGMP_PORT0_CONTROL_MLDv1_OP_OFFSET    6\n#define    RTL8367C_IGMP_PORT0_CONTROL_MLDv1_OP_MASK    0xC0\n#define    RTL8367C_IGMP_PORT0_CONTROL_IGMPV3_OP_OFFSET    4\n#define    RTL8367C_IGMP_PORT0_CONTROL_IGMPV3_OP_MASK    0x30\n#define    RTL8367C_IGMP_PORT0_CONTROL_IGMPV2_OP_OFFSET    2\n#define    RTL8367C_IGMP_PORT0_CONTROL_IGMPV2_OP_MASK    0xC\n#define    RTL8367C_IGMP_PORT0_CONTROL_IGMPV1_OP_OFFSET    0\n#define    RTL8367C_IGMP_PORT0_CONTROL_IGMPV1_OP_MASK    0x3\n\n#define    RTL8367C_REG_IGMP_PORT1_CONTROL    0x1c06\n#define    RTL8367C_IGMP_PORT1_CONTROL_ALLOW_QUERY_OFFSET    14\n#define    RTL8367C_IGMP_PORT1_CONTROL_ALLOW_QUERY_MASK    0x4000\n#define    RTL8367C_IGMP_PORT1_CONTROL_ALLOW_REPORT_OFFSET    13\n#define    RTL8367C_IGMP_PORT1_CONTROL_ALLOW_REPORT_MASK    0x2000\n#define    RTL8367C_IGMP_PORT1_CONTROL_ALLOW_LEAVE_OFFSET    12\n#define    RTL8367C_IGMP_PORT1_CONTROL_ALLOW_LEAVE_MASK    0x1000\n#define    RTL8367C_IGMP_PORT1_CONTROL_ALLOW_MRP_OFFSET    11\n#define    RTL8367C_IGMP_PORT1_CONTROL_ALLOW_MRP_MASK    0x800\n#define    RTL8367C_IGMP_PORT1_CONTROL_ALLOW_MC_DATA_OFFSET    10\n#define    RTL8367C_IGMP_PORT1_CONTROL_ALLOW_MC_DATA_MASK    0x400\n#define    RTL8367C_IGMP_PORT1_CONTROL_MLDv2_OP_OFFSET    8\n#define    RTL8367C_IGMP_PORT1_CONTROL_MLDv2_OP_MASK    0x300\n#define    RTL8367C_IGMP_PORT1_CONTROL_MLDv1_OP_OFFSET    6\n#define    RTL8367C_IGMP_PORT1_CONTROL_MLDv1_OP_MASK    0xC0\n#define    RTL8367C_IGMP_PORT1_CONTROL_IGMPV3_OP_OFFSET    4\n#define    RTL8367C_IGMP_PORT1_CONTROL_IGMPV3_OP_MASK    0x30\n#define    RTL8367C_IGMP_PORT1_CONTROL_IGMPV2_OP_OFFSET    2\n#define    RTL8367C_IGMP_PORT1_CONTROL_IGMPV2_OP_MASK    0xC\n#define    RTL8367C_IGMP_PORT1_CONTROL_IGMPV1_OP_OFFSET    0\n#define    RTL8367C_IGMP_PORT1_CONTROL_IGMPV1_OP_MASK    0x3\n\n#define    RTL8367C_REG_IGMP_PORT2_CONTROL    0x1c07\n#define    RTL8367C_IGMP_PORT2_CONTROL_ALLOW_QUERY_OFFSET    14\n#define    RTL8367C_IGMP_PORT2_CONTROL_ALLOW_QUERY_MASK    0x4000\n#define    RTL8367C_IGMP_PORT2_CONTROL_ALLOW_REPORT_OFFSET    13\n#define    RTL8367C_IGMP_PORT2_CONTROL_ALLOW_REPORT_MASK    0x2000\n#define    RTL8367C_IGMP_PORT2_CONTROL_ALLOW_LEAVE_OFFSET    12\n#define    RTL8367C_IGMP_PORT2_CONTROL_ALLOW_LEAVE_MASK    0x1000\n#define    RTL8367C_IGMP_PORT2_CONTROL_ALLOW_MRP_OFFSET    11\n#define    RTL8367C_IGMP_PORT2_CONTROL_ALLOW_MRP_MASK    0x800\n#define    RTL8367C_IGMP_PORT2_CONTROL_ALLOW_MC_DATA_OFFSET    10\n#define    RTL8367C_IGMP_PORT2_CONTROL_ALLOW_MC_DATA_MASK    0x400\n#define    RTL8367C_IGMP_PORT2_CONTROL_MLDv2_OP_OFFSET    8\n#define    RTL8367C_IGMP_PORT2_CONTROL_MLDv2_OP_MASK    0x300\n#define    RTL8367C_IGMP_PORT2_CONTROL_MLDv1_OP_OFFSET    6\n#define    RTL8367C_IGMP_PORT2_CONTROL_MLDv1_OP_MASK    0xC0\n#define    RTL8367C_IGMP_PORT2_CONTROL_IGMPV3_OP_OFFSET    4\n#define    RTL8367C_IGMP_PORT2_CONTROL_IGMPV3_OP_MASK    0x30\n#define    RTL8367C_IGMP_PORT2_CONTROL_IGMPV2_OP_OFFSET    2\n#define    RTL8367C_IGMP_PORT2_CONTROL_IGMPV2_OP_MASK    0xC\n#define    RTL8367C_IGMP_PORT2_CONTROL_IGMPV1_OP_OFFSET    0\n#define    RTL8367C_IGMP_PORT2_CONTROL_IGMPV1_OP_MASK    0x3\n\n#define    RTL8367C_REG_IGMP_PORT3_CONTROL    0x1c08\n#define    RTL8367C_IGMP_PORT3_CONTROL_ALLOW_QUERY_OFFSET    14\n#define    RTL8367C_IGMP_PORT3_CONTROL_ALLOW_QUERY_MASK    0x4000\n#define    RTL8367C_IGMP_PORT3_CONTROL_ALLOW_REPORT_OFFSET    13\n#define    RTL8367C_IGMP_PORT3_CONTROL_ALLOW_REPORT_MASK    0x2000\n#define    RTL8367C_IGMP_PORT3_CONTROL_ALLOW_LEAVE_OFFSET    12\n#define    RTL8367C_IGMP_PORT3_CONTROL_ALLOW_LEAVE_MASK    0x1000\n#define    RTL8367C_IGMP_PORT3_CONTROL_ALLOW_MRP_OFFSET    11\n#define    RTL8367C_IGMP_PORT3_CONTROL_ALLOW_MRP_MASK    0x800\n#define    RTL8367C_IGMP_PORT3_CONTROL_ALLOW_MC_DATA_OFFSET    10\n#define    RTL8367C_IGMP_PORT3_CONTROL_ALLOW_MC_DATA_MASK    0x400\n#define    RTL8367C_IGMP_PORT3_CONTROL_MLDv2_OP_OFFSET    8\n#define    RTL8367C_IGMP_PORT3_CONTROL_MLDv2_OP_MASK    0x300\n#define    RTL8367C_IGMP_PORT3_CONTROL_MLDv1_OP_OFFSET    6\n#define    RTL8367C_IGMP_PORT3_CONTROL_MLDv1_OP_MASK    0xC0\n#define    RTL8367C_IGMP_PORT3_CONTROL_IGMPV3_OP_OFFSET    4\n#define    RTL8367C_IGMP_PORT3_CONTROL_IGMPV3_OP_MASK    0x30\n#define    RTL8367C_IGMP_PORT3_CONTROL_IGMPV2_OP_OFFSET    2\n#define    RTL8367C_IGMP_PORT3_CONTROL_IGMPV2_OP_MASK    0xC\n#define    RTL8367C_IGMP_PORT3_CONTROL_IGMPV1_OP_OFFSET    0\n#define    RTL8367C_IGMP_PORT3_CONTROL_IGMPV1_OP_MASK    0x3\n\n#define    RTL8367C_REG_IGMP_PORT4_CONTROL    0x1c09\n#define    RTL8367C_IGMP_PORT4_CONTROL_ALLOW_QUERY_OFFSET    14\n#define    RTL8367C_IGMP_PORT4_CONTROL_ALLOW_QUERY_MASK    0x4000\n#define    RTL8367C_IGMP_PORT4_CONTROL_ALLOW_REPORT_OFFSET    13\n#define    RTL8367C_IGMP_PORT4_CONTROL_ALLOW_REPORT_MASK    0x2000\n#define    RTL8367C_IGMP_PORT4_CONTROL_ALLOW_LEAVE_OFFSET    12\n#define    RTL8367C_IGMP_PORT4_CONTROL_ALLOW_LEAVE_MASK    0x1000\n#define    RTL8367C_IGMP_PORT4_CONTROL_ALLOW_MRP_OFFSET    11\n#define    RTL8367C_IGMP_PORT4_CONTROL_ALLOW_MRP_MASK    0x800\n#define    RTL8367C_IGMP_PORT4_CONTROL_ALLOW_MC_DATA_OFFSET    10\n#define    RTL8367C_IGMP_PORT4_CONTROL_ALLOW_MC_DATA_MASK    0x400\n#define    RTL8367C_IGMP_PORT4_CONTROL_MLDv2_OP_OFFSET    8\n#define    RTL8367C_IGMP_PORT4_CONTROL_MLDv2_OP_MASK    0x300\n#define    RTL8367C_IGMP_PORT4_CONTROL_MLDv1_OP_OFFSET    6\n#define    RTL8367C_IGMP_PORT4_CONTROL_MLDv1_OP_MASK    0xC0\n#define    RTL8367C_IGMP_PORT4_CONTROL_IGMPV3_OP_OFFSET    4\n#define    RTL8367C_IGMP_PORT4_CONTROL_IGMPV3_OP_MASK    0x30\n#define    RTL8367C_IGMP_PORT4_CONTROL_IGMPV2_OP_OFFSET    2\n#define    RTL8367C_IGMP_PORT4_CONTROL_IGMPV2_OP_MASK    0xC\n#define    RTL8367C_IGMP_PORT4_CONTROL_IGMPV1_OP_OFFSET    0\n#define    RTL8367C_IGMP_PORT4_CONTROL_IGMPV1_OP_MASK    0x3\n\n#define    RTL8367C_REG_IGMP_PORT5_CONTROL    0x1c0a\n#define    RTL8367C_IGMP_PORT5_CONTROL_ALLOW_QUERY_OFFSET    14\n#define    RTL8367C_IGMP_PORT5_CONTROL_ALLOW_QUERY_MASK    0x4000\n#define    RTL8367C_IGMP_PORT5_CONTROL_ALLOW_REPORT_OFFSET    13\n#define    RTL8367C_IGMP_PORT5_CONTROL_ALLOW_REPORT_MASK    0x2000\n#define    RTL8367C_IGMP_PORT5_CONTROL_ALLOW_LEAVE_OFFSET    12\n#define    RTL8367C_IGMP_PORT5_CONTROL_ALLOW_LEAVE_MASK    0x1000\n#define    RTL8367C_IGMP_PORT5_CONTROL_ALLOW_MRP_OFFSET    11\n#define    RTL8367C_IGMP_PORT5_CONTROL_ALLOW_MRP_MASK    0x800\n#define    RTL8367C_IGMP_PORT5_CONTROL_ALLOW_MC_DATA_OFFSET    10\n#define    RTL8367C_IGMP_PORT5_CONTROL_ALLOW_MC_DATA_MASK    0x400\n#define    RTL8367C_IGMP_PORT5_CONTROL_MLDv2_OP_OFFSET    8\n#define    RTL8367C_IGMP_PORT5_CONTROL_MLDv2_OP_MASK    0x300\n#define    RTL8367C_IGMP_PORT5_CONTROL_MLDv1_OP_OFFSET    6\n#define    RTL8367C_IGMP_PORT5_CONTROL_MLDv1_OP_MASK    0xC0\n#define    RTL8367C_IGMP_PORT5_CONTROL_IGMPV3_OP_OFFSET    4\n#define    RTL8367C_IGMP_PORT5_CONTROL_IGMPV3_OP_MASK    0x30\n#define    RTL8367C_IGMP_PORT5_CONTROL_IGMPV2_OP_OFFSET    2\n#define    RTL8367C_IGMP_PORT5_CONTROL_IGMPV2_OP_MASK    0xC\n#define    RTL8367C_IGMP_PORT5_CONTROL_IGMPV1_OP_OFFSET    0\n#define    RTL8367C_IGMP_PORT5_CONTROL_IGMPV1_OP_MASK    0x3\n\n#define    RTL8367C_REG_IGMP_PORT6_CONTROL    0x1c0b\n#define    RTL8367C_IGMP_PORT6_CONTROL_ALLOW_QUERY_OFFSET    14\n#define    RTL8367C_IGMP_PORT6_CONTROL_ALLOW_QUERY_MASK    0x4000\n#define    RTL8367C_IGMP_PORT6_CONTROL_ALLOW_REPORT_OFFSET    13\n#define    RTL8367C_IGMP_PORT6_CONTROL_ALLOW_REPORT_MASK    0x2000\n#define    RTL8367C_IGMP_PORT6_CONTROL_ALLOW_LEAVE_OFFSET    12\n#define    RTL8367C_IGMP_PORT6_CONTROL_ALLOW_LEAVE_MASK    0x1000\n#define    RTL8367C_IGMP_PORT6_CONTROL_ALLOW_MRP_OFFSET    11\n#define    RTL8367C_IGMP_PORT6_CONTROL_ALLOW_MRP_MASK    0x800\n#define    RTL8367C_IGMP_PORT6_CONTROL_ALLOW_MC_DATA_OFFSET    10\n#define    RTL8367C_IGMP_PORT6_CONTROL_ALLOW_MC_DATA_MASK    0x400\n#define    RTL8367C_IGMP_PORT6_CONTROL_MLDv2_OP_OFFSET    8\n#define    RTL8367C_IGMP_PORT6_CONTROL_MLDv2_OP_MASK    0x300\n#define    RTL8367C_IGMP_PORT6_CONTROL_MLDv1_OP_OFFSET    6\n#define    RTL8367C_IGMP_PORT6_CONTROL_MLDv1_OP_MASK    0xC0\n#define    RTL8367C_IGMP_PORT6_CONTROL_IGMPV3_OP_OFFSET    4\n#define    RTL8367C_IGMP_PORT6_CONTROL_IGMPV3_OP_MASK    0x30\n#define    RTL8367C_IGMP_PORT6_CONTROL_IGMPV2_OP_OFFSET    2\n#define    RTL8367C_IGMP_PORT6_CONTROL_IGMPV2_OP_MASK    0xC\n#define    RTL8367C_IGMP_PORT6_CONTROL_IGMPV1_OP_OFFSET    0\n#define    RTL8367C_IGMP_PORT6_CONTROL_IGMPV1_OP_MASK    0x3\n\n#define    RTL8367C_REG_IGMP_PORT7_CONTROL    0x1c0c\n#define    RTL8367C_IGMP_PORT7_CONTROL_ALLOW_QUERY_OFFSET    14\n#define    RTL8367C_IGMP_PORT7_CONTROL_ALLOW_QUERY_MASK    0x4000\n#define    RTL8367C_IGMP_PORT7_CONTROL_ALLOW_REPORT_OFFSET    13\n#define    RTL8367C_IGMP_PORT7_CONTROL_ALLOW_REPORT_MASK    0x2000\n#define    RTL8367C_IGMP_PORT7_CONTROL_ALLOW_LEAVE_OFFSET    12\n#define    RTL8367C_IGMP_PORT7_CONTROL_ALLOW_LEAVE_MASK    0x1000\n#define    RTL8367C_IGMP_PORT7_CONTROL_ALLOW_MRP_OFFSET    11\n#define    RTL8367C_IGMP_PORT7_CONTROL_ALLOW_MRP_MASK    0x800\n#define    RTL8367C_IGMP_PORT7_CONTROL_ALLOW_MC_DATA_OFFSET    10\n#define    RTL8367C_IGMP_PORT7_CONTROL_ALLOW_MC_DATA_MASK    0x400\n#define    RTL8367C_IGMP_PORT7_CONTROL_MLDv2_OP_OFFSET    8\n#define    RTL8367C_IGMP_PORT7_CONTROL_MLDv2_OP_MASK    0x300\n#define    RTL8367C_IGMP_PORT7_CONTROL_MLDv1_OP_OFFSET    6\n#define    RTL8367C_IGMP_PORT7_CONTROL_MLDv1_OP_MASK    0xC0\n#define    RTL8367C_IGMP_PORT7_CONTROL_IGMPV3_OP_OFFSET    4\n#define    RTL8367C_IGMP_PORT7_CONTROL_IGMPV3_OP_MASK    0x30\n#define    RTL8367C_IGMP_PORT7_CONTROL_IGMPV2_OP_OFFSET    2\n#define    RTL8367C_IGMP_PORT7_CONTROL_IGMPV2_OP_MASK    0xC\n#define    RTL8367C_IGMP_PORT7_CONTROL_IGMPV1_OP_OFFSET    0\n#define    RTL8367C_IGMP_PORT7_CONTROL_IGMPV1_OP_MASK    0x3\n\n#define    RTL8367C_REG_IGMP_PORT01_MAX_GROUP    0x1c0d\n#define    RTL8367C_PORT1_MAX_GROUP_OFFSET    8\n#define    RTL8367C_PORT1_MAX_GROUP_MASK    0xFF00\n#define    RTL8367C_PORT0_MAX_GROUP_OFFSET    0\n#define    RTL8367C_PORT0_MAX_GROUP_MASK    0xFF\n\n#define    RTL8367C_REG_IGMP_PORT23_MAX_GROUP    0x1c0e\n#define    RTL8367C_PORT3_MAX_GROUP_OFFSET    8\n#define    RTL8367C_PORT3_MAX_GROUP_MASK    0xFF00\n#define    RTL8367C_PORT2_MAX_GROUP_OFFSET    0\n#define    RTL8367C_PORT2_MAX_GROUP_MASK    0xFF\n\n#define    RTL8367C_REG_IGMP_PORT45_MAX_GROUP    0x1c0f\n#define    RTL8367C_PORT5_MAX_GROUP_OFFSET    8\n#define    RTL8367C_PORT5_MAX_GROUP_MASK    0xFF00\n#define    RTL8367C_PORT4_MAX_GROUP_OFFSET    0\n#define    RTL8367C_PORT4_MAX_GROUP_MASK    0xFF\n\n#define    RTL8367C_REG_IGMP_PORT67_MAX_GROUP    0x1c10\n#define    RTL8367C_PORT7_MAX_GROUP_OFFSET    8\n#define    RTL8367C_PORT7_MAX_GROUP_MASK    0xFF00\n#define    RTL8367C_PORT6_MAX_GROUP_OFFSET    0\n#define    RTL8367C_PORT6_MAX_GROUP_MASK    0xFF\n\n#define    RTL8367C_REG_IGMP_PORT01_CURRENT_GROUP    0x1c11\n#define    RTL8367C_PORT1_CURRENT_GROUP_OFFSET    8\n#define    RTL8367C_PORT1_CURRENT_GROUP_MASK    0xFF00\n#define    RTL8367C_PORT0_CURRENT_GROUP_OFFSET    0\n#define    RTL8367C_PORT0_CURRENT_GROUP_MASK    0xFF\n\n#define    RTL8367C_REG_IGMP_PORT23_CURRENT_GROUP    0x1c12\n#define    RTL8367C_PORT3_CURRENT_GROUP_OFFSET    8\n#define    RTL8367C_PORT3_CURRENT_GROUP_MASK    0xFF00\n#define    RTL8367C_PORT2_CURRENT_GROUP_OFFSET    0\n#define    RTL8367C_PORT2_CURRENT_GROUP_MASK    0xFF\n\n#define    RTL8367C_REG_IGMP_PORT45_CURRENT_GROUP    0x1c13\n#define    RTL8367C_PORT5_CURRENT_GROUP_OFFSET    8\n#define    RTL8367C_PORT5_CURRENT_GROUP_MASK    0xFF00\n#define    RTL8367C_PORT4_CURRENT_GROUP_OFFSET    0\n#define    RTL8367C_PORT4_CURRENT_GROUP_MASK    0xFF\n\n#define    RTL8367C_REG_IGMP_PORT67_CURRENT_GROUP    0x1c14\n#define    RTL8367C_PORT7_CURRENT_GROUP_OFFSET    8\n#define    RTL8367C_PORT7_CURRENT_GROUP_MASK    0xFF00\n#define    RTL8367C_PORT6_CURRENT_GROUP_OFFSET    0\n#define    RTL8367C_PORT6_CURRENT_GROUP_MASK    0xFF\n\n#define    RTL8367C_REG_IGMP_MLD_CFG3    0x1c15\n#define    RTL8367C_IGMP_MLD_IP6_BYPASS_OFFSET    5\n#define    RTL8367C_IGMP_MLD_IP6_BYPASS_MASK    0x20\n#define    RTL8367C_IGMP_MLD_IP4_BYPASS_239_255_255_OFFSET    4\n#define    RTL8367C_IGMP_MLD_IP4_BYPASS_239_255_255_MASK    0x10\n#define    RTL8367C_IGMP_MLD_IP4_BYPASS_224_0_1_OFFSET    3\n#define    RTL8367C_IGMP_MLD_IP4_BYPASS_224_0_1_MASK    0x8\n#define    RTL8367C_IGMP_MLD_IP4_BYPASS_224_0_0_OFFSET    2\n#define    RTL8367C_IGMP_MLD_IP4_BYPASS_224_0_0_MASK    0x4\n#define    RTL8367C_REPORT_LEAVE_FORWARD_OFFSET    0\n#define    RTL8367C_REPORT_LEAVE_FORWARD_MASK    0x3\n\n#define    RTL8367C_REG_IGMP_MLD_CFG4    0x1c16\n#define    RTL8367C_IGMP_MLD_CFG4_OFFSET    0\n#define    RTL8367C_IGMP_MLD_CFG4_MASK    0x7FF\n\n#define    RTL8367C_REG_IGMP_GROUP_USAGE_LIST0    0x1c20\n\n#define    RTL8367C_REG_IGMP_GROUP_USAGE_LIST1    0x1c21\n\n#define    RTL8367C_REG_IGMP_GROUP_USAGE_LIST2    0x1c22\n\n#define    RTL8367C_REG_IGMP_GROUP_USAGE_LIST3    0x1c23\n\n#define    RTL8367C_REG_IGMP_GROUP_USAGE_LIST4    0x1c24\n\n#define    RTL8367C_REG_IGMP_GROUP_USAGE_LIST5    0x1c25\n\n#define    RTL8367C_REG_IGMP_GROUP_USAGE_LIST6    0x1c26\n\n#define    RTL8367C_REG_IGMP_GROUP_USAGE_LIST7    0x1c27\n\n#define    RTL8367C_REG_IGMP_GROUP_USAGE_LIST8    0x1c28\n\n#define    RTL8367C_REG_IGMP_GROUP_USAGE_LIST9    0x1c29\n\n#define    RTL8367C_REG_IGMP_GROUP_USAGE_LIST10    0x1c2a\n\n#define    RTL8367C_REG_IGMP_GROUP_USAGE_LIST11    0x1c2b\n\n#define    RTL8367C_REG_IGMP_GROUP_USAGE_LIST12    0x1c2c\n\n#define    RTL8367C_REG_IGMP_GROUP_USAGE_LIST13    0x1c2d\n\n#define    RTL8367C_REG_IGMP_GROUP_USAGE_LIST14    0x1c2e\n\n#define    RTL8367C_REG_IGMP_GROUP_USAGE_LIST15    0x1c2f\n\n#define    RTL8367C_REG_EAV_CTRL0    0x1c30\n#define    RTL8367C_EAV_CTRL0_OFFSET    0\n#define    RTL8367C_EAV_CTRL0_MASK    0xFF\n\n#define    RTL8367C_REG_EAV_CTRL1    0x1c31\n#define    RTL8367C_REMAP_EAV_PRI3_REGEN_OFFSET    9\n#define    RTL8367C_REMAP_EAV_PRI3_REGEN_MASK    0xE00\n#define    RTL8367C_REMAP_EAV_PRI2_REGEN_OFFSET    6\n#define    RTL8367C_REMAP_EAV_PRI2_REGEN_MASK    0x1C0\n#define    RTL8367C_REMAP_EAV_PRI1_REGEN_OFFSET    3\n#define    RTL8367C_REMAP_EAV_PRI1_REGEN_MASK    0x38\n#define    RTL8367C_REMAP_EAV_PRI0_REGEN_OFFSET    0\n#define    RTL8367C_REMAP_EAV_PRI0_REGEN_MASK    0x7\n\n#define    RTL8367C_REG_EAV_CTRL2    0x1c32\n#define    RTL8367C_REMAP_EAV_PRI7_REGEN_OFFSET    9\n#define    RTL8367C_REMAP_EAV_PRI7_REGEN_MASK    0xE00\n#define    RTL8367C_REMAP_EAV_PRI6_REGEN_OFFSET    6\n#define    RTL8367C_REMAP_EAV_PRI6_REGEN_MASK    0x1C0\n#define    RTL8367C_REMAP_EAV_PRI5_REGEN_OFFSET    3\n#define    RTL8367C_REMAP_EAV_PRI5_REGEN_MASK    0x38\n#define    RTL8367C_REMAP_EAV_PRI4_REGEN_OFFSET    0\n#define    RTL8367C_REMAP_EAV_PRI4_REGEN_MASK    0x7\n\n#define    RTL8367C_REG_SYS_TIME_FREQ    0x1c43\n\n#define    RTL8367C_REG_SYS_TIME_OFFSET_L    0x1c44\n\n#define    RTL8367C_REG_SYS_TIME_OFFSET_H    0x1c45\n\n#define    RTL8367C_REG_SYS_TIME_OFFSET_512NS_L    0x1c46\n\n#define    RTL8367C_REG_SYS_TIME_OFFSET_512NS_H    0x1c47\n#define    RTL8367C_SYS_TIME_OFFSET_TUNE_OFFSET    5\n#define    RTL8367C_SYS_TIME_OFFSET_TUNE_MASK    0x20\n#define    RTL8367C_SYS_TIME_OFFSET_512NS_H_SYS_TIME_OFFSET_512NS_OFFSET    0\n#define    RTL8367C_SYS_TIME_OFFSET_512NS_H_SYS_TIME_OFFSET_512NS_MASK    0x1F\n\n#define    RTL8367C_REG_SYS_TIME_SEC_TRANSIT    0x1c48\n#define    RTL8367C_SYS_TIME_SEC_TRANSIT_OFFSET    0\n#define    RTL8367C_SYS_TIME_SEC_TRANSIT_MASK    0x1\n\n#define    RTL8367C_REG_SYS_TIME_SEC_HIGH_L    0x1c49\n\n#define    RTL8367C_REG_SYS_TIME_SEC_HIGH_H    0x1c4a\n\n#define    RTL8367C_REG_SYS_TIME_512NS_L    0x1c4b\n\n#define    RTL8367C_REG_SYS_TIME_512NS_H    0x1c4c\n#define    RTL8367C_SYS_TIME_512NS_H_OFFSET    0\n#define    RTL8367C_SYS_TIME_512NS_H_MASK    0x1F\n\n#define    RTL8367C_REG_FALLBACK_CTRL    0x1c70\n#define    RTL8367C_FALLBACK_PL_DEC_EN_OFFSET    15\n#define    RTL8367C_FALLBACK_PL_DEC_EN_MASK    0x8000\n#define    RTL8367C_FALLBACK_MONITOR_TIMEOUT_IGNORE_OFFSET    14\n#define    RTL8367C_FALLBACK_MONITOR_TIMEOUT_IGNORE_MASK    0x4000\n#define    RTL8367C_FALLBACK_ERROR_RATIO_THRESHOLD_OFFSET    11\n#define    RTL8367C_FALLBACK_ERROR_RATIO_THRESHOLD_MASK    0x3800\n#define    RTL8367C_FALLBACK_MONITORMAX_OFFSET    8\n#define    RTL8367C_FALLBACK_MONITORMAX_MASK    0x700\n#define    RTL8367C_FALLBACK_MONITOR_TIMEOUT_OFFSET    0\n#define    RTL8367C_FALLBACK_MONITOR_TIMEOUT_MASK    0xFF\n\n#define    RTL8367C_REG_FALLBACK_PORT0_CFG0    0x1c71\n#define    RTL8367C_FALLBACK_PORT0_CFG0_RESET_POWER_LEVEL_OFFSET    15\n#define    RTL8367C_FALLBACK_PORT0_CFG0_RESET_POWER_LEVEL_MASK    0x8000\n#define    RTL8367C_FALLBACK_PORT0_CFG0_ENABLE_OFFSET    14\n#define    RTL8367C_FALLBACK_PORT0_CFG0_ENABLE_MASK    0x4000\n\n#define    RTL8367C_REG_FALLBACK_PORT0_CFG1    0x1c72\n\n#define    RTL8367C_REG_FALLBACK_PORT0_CFG2    0x1c73\n#define    RTL8367C_FALLBACK_PORT0_CFG2_OFFSET    0\n#define    RTL8367C_FALLBACK_PORT0_CFG2_MASK    0xFFF\n\n#define    RTL8367C_REG_FALLBACK_PORT0_CFG3    0x1c74\n#define    RTL8367C_FALLBACK_PORT0_CFG3_OFFSET    0\n#define    RTL8367C_FALLBACK_PORT0_CFG3_MASK    0xFF\n\n#define    RTL8367C_REG_FALLBACK_PORT1_CFG0    0x1c75\n#define    RTL8367C_FALLBACK_PORT1_CFG0_RESET_POWER_LEVEL_OFFSET    15\n#define    RTL8367C_FALLBACK_PORT1_CFG0_RESET_POWER_LEVEL_MASK    0x8000\n#define    RTL8367C_FALLBACK_PORT1_CFG0_ENABLE_OFFSET    14\n#define    RTL8367C_FALLBACK_PORT1_CFG0_ENABLE_MASK    0x4000\n\n#define    RTL8367C_REG_FALLBACK_PORT1_CFG1    0x1c76\n\n#define    RTL8367C_REG_FALLBACK_PORT1_CFG2    0x1c77\n#define    RTL8367C_FALLBACK_PORT1_CFG2_OFFSET    0\n#define    RTL8367C_FALLBACK_PORT1_CFG2_MASK    0xFFF\n\n#define    RTL8367C_REG_FALLBACK_PORT1_CFG3    0x1c78\n#define    RTL8367C_FALLBACK_PORT1_CFG3_OFFSET    0\n#define    RTL8367C_FALLBACK_PORT1_CFG3_MASK    0xFF\n\n#define    RTL8367C_REG_FALLBACK_PORT2_CFG0    0x1c79\n#define    RTL8367C_FALLBACK_PORT2_CFG0_RESET_POWER_LEVEL_OFFSET    15\n#define    RTL8367C_FALLBACK_PORT2_CFG0_RESET_POWER_LEVEL_MASK    0x8000\n#define    RTL8367C_FALLBACK_PORT2_CFG0_ENABLE_OFFSET    14\n#define    RTL8367C_FALLBACK_PORT2_CFG0_ENABLE_MASK    0x4000\n\n#define    RTL8367C_REG_FALLBACK_PORT2_CFG1    0x1c7a\n\n#define    RTL8367C_REG_FALLBACK_PORT2_CFG2    0x1c7b\n#define    RTL8367C_FALLBACK_PORT2_CFG2_OFFSET    0\n#define    RTL8367C_FALLBACK_PORT2_CFG2_MASK    0xFFF\n\n#define    RTL8367C_REG_FALLBACK_PORT2_CFG3    0x1c7c\n#define    RTL8367C_FALLBACK_PORT2_CFG3_OFFSET    0\n#define    RTL8367C_FALLBACK_PORT2_CFG3_MASK    0xFF\n\n#define    RTL8367C_REG_FALLBACK_PORT3_CFG0    0x1c7d\n#define    RTL8367C_FALLBACK_PORT3_CFG0_RESET_POWER_LEVEL_OFFSET    15\n#define    RTL8367C_FALLBACK_PORT3_CFG0_RESET_POWER_LEVEL_MASK    0x8000\n#define    RTL8367C_FALLBACK_PORT3_CFG0_ENABLE_OFFSET    14\n#define    RTL8367C_FALLBACK_PORT3_CFG0_ENABLE_MASK    0x4000\n\n#define    RTL8367C_REG_FALLBACK_PORT3_CFG1    0x1c7e\n\n#define    RTL8367C_REG_FALLBACK_PORT3_CFG2    0x1c7f\n#define    RTL8367C_FALLBACK_PORT3_CFG2_OFFSET    0\n#define    RTL8367C_FALLBACK_PORT3_CFG2_MASK    0xFFF\n\n#define    RTL8367C_REG_FALLBACK_PORT3_CFG3    0x1c80\n#define    RTL8367C_FALLBACK_PORT3_CFG3_OFFSET    0\n#define    RTL8367C_FALLBACK_PORT3_CFG3_MASK    0xFF\n\n#define    RTL8367C_REG_FALLBACK_PORT4_CFG0    0x1c81\n#define    RTL8367C_FALLBACK_PORT4_CFG0_RESET_POWER_LEVEL_OFFSET    15\n#define    RTL8367C_FALLBACK_PORT4_CFG0_RESET_POWER_LEVEL_MASK    0x8000\n#define    RTL8367C_FALLBACK_PORT4_CFG0_ENABLE_OFFSET    14\n#define    RTL8367C_FALLBACK_PORT4_CFG0_ENABLE_MASK    0x4000\n\n#define    RTL8367C_REG_FALLBACK_PORT4_CFG1    0x1c82\n\n#define    RTL8367C_REG_FALLBACK_PORT4_CFG2    0x1c83\n#define    RTL8367C_FALLBACK_PORT4_CFG2_OFFSET    0\n#define    RTL8367C_FALLBACK_PORT4_CFG2_MASK    0xFFF\n\n#define    RTL8367C_REG_FALLBACK_PORT4_CFG3    0x1c84\n#define    RTL8367C_FALLBACK_PORT4_CFG3_OFFSET    0\n#define    RTL8367C_FALLBACK_PORT4_CFG3_MASK    0xFF\n\n#define    RTL8367C_REG_FALLBACK_CTRL1    0x1c85\n#define    RTL8367C_FALLBACK_VALIDFLOW_OFFSET    8\n#define    RTL8367C_FALLBACK_VALIDFLOW_MASK    0xFF00\n#define    RTL8367C_FALLBACK_STOP_TMR_OFFSET    0\n#define    RTL8367C_FALLBACK_STOP_TMR_MASK    0x1\n\n#define    RTL8367C_REG_FALLBACK_CPL    0x1c86\n#define    RTL8367C_PORT4_CPL_OFFSET    4\n#define    RTL8367C_PORT4_CPL_MASK    0x10\n#define    RTL8367C_PORT3_CPL_OFFSET    3\n#define    RTL8367C_PORT3_CPL_MASK    0x8\n#define    RTL8367C_PORT2_CPL_OFFSET    2\n#define    RTL8367C_PORT2_CPL_MASK    0x4\n#define    RTL8367C_PORT1_CPL_OFFSET    1\n#define    RTL8367C_PORT1_CPL_MASK    0x2\n#define    RTL8367C_PORT0_CPL_OFFSET    0\n#define    RTL8367C_PORT0_CPL_MASK    0x1\n\n#define    RTL8367C_REG_FALLBACK_PHY_PAGE    0x1c87\n#define    RTL8367C_FALLBACK_PHY_PAGE_OFFSET    0\n#define    RTL8367C_FALLBACK_PHY_PAGE_MASK    0xFFF\n\n#define    RTL8367C_REG_FALLBACK_PHY_REG    0x1c88\n#define    RTL8367C_FALLBACK_PHY_REG_OFFSET    0\n#define    RTL8367C_FALLBACK_PHY_REG_MASK    0x1F\n\n#define    RTL8367C_REG_AFBK_INFO_X0    0x1c89\n\n#define    RTL8367C_REG_AFBK_INFO_X1    0x1c8a\n\n#define    RTL8367C_REG_AFBK_INFO_X2    0x1c8b\n\n#define    RTL8367C_REG_AFBK_INFO_X3    0x1c8c\n\n#define    RTL8367C_REG_AFBK_INFO_X4    0x1c8d\n\n#define    RTL8367C_REG_AFBK_INFO_X5    0x1c8e\n\n#define    RTL8367C_REG_AFBK_INFO_X6    0x1c8f\n\n#define    RTL8367C_REG_AFBK_INFO_X7    0x1c90\n\n#define    RTL8367C_REG_AFBK_INFO_X8    0x1c91\n\n#define    RTL8367C_REG_AFBK_INFO_X9    0x1c92\n\n#define    RTL8367C_REG_AFBK_INFO_X10    0x1c93\n\n#define    RTL8367C_REG_AFBK_INFO_X11    0x1c94\n\n#define    RTL8367C_REG_FALLBACK_PORT5_CFG0    0x1ca0\n#define    RTL8367C_FALLBACK_PORT5_CFG0_RESET_POWER_LEVEL_OFFSET    15\n#define    RTL8367C_FALLBACK_PORT5_CFG0_RESET_POWER_LEVEL_MASK    0x8000\n#define    RTL8367C_FALLBACK_PORT5_CFG0_ENABLE_OFFSET    14\n#define    RTL8367C_FALLBACK_PORT5_CFG0_ENABLE_MASK    0x4000\n\n#define    RTL8367C_REG_FALLBACK_PORT5_CFG1    0x1ca1\n\n#define    RTL8367C_REG_FALLBACK_PORT5_CFG2    0x1ca2\n#define    RTL8367C_FALLBACK_PORT5_CFG2_OFFSET    0\n#define    RTL8367C_FALLBACK_PORT5_CFG2_MASK    0xFFF\n\n#define    RTL8367C_REG_FALLBACK_PORT5_CFG3    0x1ca3\n#define    RTL8367C_FALLBACK_PORT5_CFG3_OFFSET    0\n#define    RTL8367C_FALLBACK_PORT5_CFG3_MASK    0xFF\n\n#define    RTL8367C_REG_FALLBACK_PORT6_CFG0    0x1ca4\n#define    RTL8367C_FALLBACK_PORT6_CFG0_RESET_POWER_LEVEL_OFFSET    15\n#define    RTL8367C_FALLBACK_PORT6_CFG0_RESET_POWER_LEVEL_MASK    0x8000\n#define    RTL8367C_FALLBACK_PORT6_CFG0_ENABLE_OFFSET    14\n#define    RTL8367C_FALLBACK_PORT6_CFG0_ENABLE_MASK    0x4000\n\n#define    RTL8367C_REG_FALLBACK_PORT6_CFG1    0x1ca5\n\n#define    RTL8367C_REG_FALLBACK_PORT6_CFG2    0x1ca6\n#define    RTL8367C_FALLBACK_PORT6_CFG2_OFFSET    0\n#define    RTL8367C_FALLBACK_PORT6_CFG2_MASK    0xFFF\n\n#define    RTL8367C_REG_FALLBACK_PORT6_CFG3    0x1ca7\n#define    RTL8367C_FALLBACK_PORT6_CFG3_OFFSET    0\n#define    RTL8367C_FALLBACK_PORT6_CFG3_MASK    0xFF\n\n#define    RTL8367C_REG_FALLBACK_PORT7_CFG0    0x1ca8\n#define    RTL8367C_FALLBACK_PORT7_CFG0_RESET_POWER_LEVEL_OFFSET    15\n#define    RTL8367C_FALLBACK_PORT7_CFG0_RESET_POWER_LEVEL_MASK    0x8000\n#define    RTL8367C_FALLBACK_PORT7_CFG0_ENABLE_OFFSET    14\n#define    RTL8367C_FALLBACK_PORT7_CFG0_ENABLE_MASK    0x4000\n\n#define    RTL8367C_REG_FALLBACK_PORT7_CFG1    0x1ca9\n\n#define    RTL8367C_REG_FALLBACK_PORT7_CFG2    0x1caa\n#define    RTL8367C_FALLBACK_PORT7_CFG2_OFFSET    0\n#define    RTL8367C_FALLBACK_PORT7_CFG2_MASK    0xFFF\n\n#define    RTL8367C_REG_FALLBACK_PORT7_CFG3    0x1cab\n#define    RTL8367C_FALLBACK_PORT7_CFG3_OFFSET    0\n#define    RTL8367C_FALLBACK_PORT7_CFG3_MASK    0xFF\n\n#define    RTL8367C_REG_IGMP_PORT8_CONTROL    0x1cb0\n#define    RTL8367C_IGMP_PORT8_CONTROL_ALLOW_QUERY_OFFSET    14\n#define    RTL8367C_IGMP_PORT8_CONTROL_ALLOW_QUERY_MASK    0x4000\n#define    RTL8367C_IGMP_PORT8_CONTROL_ALLOW_REPORT_OFFSET    13\n#define    RTL8367C_IGMP_PORT8_CONTROL_ALLOW_REPORT_MASK    0x2000\n#define    RTL8367C_IGMP_PORT8_CONTROL_ALLOW_LEAVE_OFFSET    12\n#define    RTL8367C_IGMP_PORT8_CONTROL_ALLOW_LEAVE_MASK    0x1000\n#define    RTL8367C_IGMP_PORT8_CONTROL_ALLOW_MRP_OFFSET    11\n#define    RTL8367C_IGMP_PORT8_CONTROL_ALLOW_MRP_MASK    0x800\n#define    RTL8367C_IGMP_PORT8_CONTROL_ALLOW_MC_DATA_OFFSET    10\n#define    RTL8367C_IGMP_PORT8_CONTROL_ALLOW_MC_DATA_MASK    0x400\n#define    RTL8367C_IGMP_PORT8_CONTROL_MLDv2_OP_OFFSET    8\n#define    RTL8367C_IGMP_PORT8_CONTROL_MLDv2_OP_MASK    0x300\n#define    RTL8367C_IGMP_PORT8_CONTROL_MLDv1_OP_OFFSET    6\n#define    RTL8367C_IGMP_PORT8_CONTROL_MLDv1_OP_MASK    0xC0\n#define    RTL8367C_IGMP_PORT8_CONTROL_IGMPV3_OP_OFFSET    4\n#define    RTL8367C_IGMP_PORT8_CONTROL_IGMPV3_OP_MASK    0x30\n#define    RTL8367C_IGMP_PORT8_CONTROL_IGMPV2_OP_OFFSET    2\n#define    RTL8367C_IGMP_PORT8_CONTROL_IGMPV2_OP_MASK    0xC\n#define    RTL8367C_IGMP_PORT8_CONTROL_IGMPV1_OP_OFFSET    0\n#define    RTL8367C_IGMP_PORT8_CONTROL_IGMPV1_OP_MASK    0x3\n\n#define    RTL8367C_REG_IGMP_PORT9_CONTROL    0x1cb1\n#define    RTL8367C_IGMP_PORT9_CONTROL_ALLOW_QUERY_OFFSET    14\n#define    RTL8367C_IGMP_PORT9_CONTROL_ALLOW_QUERY_MASK    0x4000\n#define    RTL8367C_IGMP_PORT9_CONTROL_ALLOW_REPORT_OFFSET    13\n#define    RTL8367C_IGMP_PORT9_CONTROL_ALLOW_REPORT_MASK    0x2000\n#define    RTL8367C_IGMP_PORT9_CONTROL_ALLOW_LEAVE_OFFSET    12\n#define    RTL8367C_IGMP_PORT9_CONTROL_ALLOW_LEAVE_MASK    0x1000\n#define    RTL8367C_IGMP_PORT9_CONTROL_ALLOW_MRP_OFFSET    11\n#define    RTL8367C_IGMP_PORT9_CONTROL_ALLOW_MRP_MASK    0x800\n#define    RTL8367C_IGMP_PORT9_CONTROL_ALLOW_MC_DATA_OFFSET    10\n#define    RTL8367C_IGMP_PORT9_CONTROL_ALLOW_MC_DATA_MASK    0x400\n#define    RTL8367C_IGMP_PORT9_CONTROL_MLDv2_OP_OFFSET    8\n#define    RTL8367C_IGMP_PORT9_CONTROL_MLDv2_OP_MASK    0x300\n#define    RTL8367C_IGMP_PORT9_CONTROL_MLDv1_OP_OFFSET    6\n#define    RTL8367C_IGMP_PORT9_CONTROL_MLDv1_OP_MASK    0xC0\n#define    RTL8367C_IGMP_PORT9_CONTROL_IGMPV3_OP_OFFSET    4\n#define    RTL8367C_IGMP_PORT9_CONTROL_IGMPV3_OP_MASK    0x30\n#define    RTL8367C_IGMP_PORT9_CONTROL_IGMPV2_OP_OFFSET    2\n#define    RTL8367C_IGMP_PORT9_CONTROL_IGMPV2_OP_MASK    0xC\n#define    RTL8367C_IGMP_PORT9_CONTROL_IGMPV1_OP_OFFSET    0\n#define    RTL8367C_IGMP_PORT9_CONTROL_IGMPV1_OP_MASK    0x3\n\n#define    RTL8367C_REG_IGMP_PORT10_CONTROL    0x1cb2\n#define    RTL8367C_IGMP_PORT10_CONTROL_ALLOW_QUERY_OFFSET    14\n#define    RTL8367C_IGMP_PORT10_CONTROL_ALLOW_QUERY_MASK    0x4000\n#define    RTL8367C_IGMP_PORT10_CONTROL_ALLOW_REPORT_OFFSET    13\n#define    RTL8367C_IGMP_PORT10_CONTROL_ALLOW_REPORT_MASK    0x2000\n#define    RTL8367C_IGMP_PORT10_CONTROL_ALLOW_LEAVE_OFFSET    12\n#define    RTL8367C_IGMP_PORT10_CONTROL_ALLOW_LEAVE_MASK    0x1000\n#define    RTL8367C_IGMP_PORT10_CONTROL_ALLOW_MRP_OFFSET    11\n#define    RTL8367C_IGMP_PORT10_CONTROL_ALLOW_MRP_MASK    0x800\n#define    RTL8367C_IGMP_PORT10_CONTROL_ALLOW_MC_DATA_OFFSET    10\n#define    RTL8367C_IGMP_PORT10_CONTROL_ALLOW_MC_DATA_MASK    0x400\n#define    RTL8367C_IGMP_PORT10_CONTROL_MLDv2_OP_OFFSET    8\n#define    RTL8367C_IGMP_PORT10_CONTROL_MLDv2_OP_MASK    0x300\n#define    RTL8367C_IGMP_PORT10_CONTROL_MLDv1_OP_OFFSET    6\n#define    RTL8367C_IGMP_PORT10_CONTROL_MLDv1_OP_MASK    0xC0\n#define    RTL8367C_IGMP_PORT10_CONTROL_IGMPV3_OP_OFFSET    4\n#define    RTL8367C_IGMP_PORT10_CONTROL_IGMPV3_OP_MASK    0x30\n#define    RTL8367C_IGMP_PORT10_CONTROL_IGMPV2_OP_OFFSET    2\n#define    RTL8367C_IGMP_PORT10_CONTROL_IGMPV2_OP_MASK    0xC\n#define    RTL8367C_IGMP_PORT10_CONTROL_IGMPV1_OP_OFFSET    0\n#define    RTL8367C_IGMP_PORT10_CONTROL_IGMPV1_OP_MASK    0x3\n\n#define    RTL8367C_REG_IGMP_PORT89_MAX_GROUP    0x1cb3\n#define    RTL8367C_PORT9_MAX_GROUP_OFFSET    8\n#define    RTL8367C_PORT9_MAX_GROUP_MASK    0xFF00\n#define    RTL8367C_PORT8_MAX_GROUP_OFFSET    0\n#define    RTL8367C_PORT8_MAX_GROUP_MASK    0xFF\n\n#define    RTL8367C_REG_IGMP_PORT10_MAX_GROUP    0x1cb4\n#define    RTL8367C_IGMP_PORT10_MAX_GROUP_OFFSET    0\n#define    RTL8367C_IGMP_PORT10_MAX_GROUP_MASK    0xFF\n\n#define    RTL8367C_REG_IGMP_PORT89_CURRENT_GROUP    0x1cb5\n#define    RTL8367C_PORT9_CURRENT_GROUP_OFFSET    8\n#define    RTL8367C_PORT9_CURRENT_GROUP_MASK    0xFF00\n#define    RTL8367C_PORT8_CURRENT_GROUP_OFFSET    0\n#define    RTL8367C_PORT8_CURRENT_GROUP_MASK    0xFF\n\n#define    RTL8367C_REG_IGMP_PORT10_CURRENT_GROUP    0x1cb6\n#define    RTL8367C_IGMP_PORT10_CURRENT_GROUP_OFFSET    0\n#define    RTL8367C_IGMP_PORT10_CURRENT_GROUP_MASK    0xFF\n\n#define    RTL8367C_REG_IGMP_L3_CHECKSUM_CHECK    0x1cb7\n#define    RTL8367C_IGMP_L3_CHECKSUM_CHECK_OFFSET    0\n#define    RTL8367C_IGMP_L3_CHECKSUM_CHECK_MASK    0x1\n\n/* (16'h1d00)chip_70b_reg */\n\n#define    RTL8367C_REG_PCSXF_CFG    0x1d00\n#define    RTL8367C_PCSXF_CFG_Reserved_OFFSET    15\n#define    RTL8367C_PCSXF_CFG_Reserved_MASK    0x8000\n#define    RTL8367C_CFG_RST_RXFIFO_P7_5_OFFSET    12\n#define    RTL8367C_CFG_RST_RXFIFO_P7_5_MASK    0x7000\n#define    RTL8367C_CFG_PCSXF_OFFSET    8\n#define    RTL8367C_CFG_PCSXF_MASK    0xF00\n#define    RTL8367C_CFG_RST_RXFIFO_OFFSET    3\n#define    RTL8367C_CFG_RST_RXFIFO_MASK    0xF8\n#define    RTL8367C_CFG_COL2RXDV_OFFSET    2\n#define    RTL8367C_CFG_COL2RXDV_MASK    0x4\n#define    RTL8367C_CFG_PHY_SDET_OFFSET    0\n#define    RTL8367C_CFG_PHY_SDET_MASK    0x3\n\n#define    RTL8367C_REG_PHYID_CFG0    0x1d01\n#define    RTL8367C_CFG_PHY_BRD_MODE_P7_5_OFFSET    11\n#define    RTL8367C_CFG_PHY_BRD_MODE_P7_5_MASK    0x3800\n#define    RTL8367C_CFG_PHYAD_14C_OFFSET    10\n#define    RTL8367C_CFG_PHYAD_14C_MASK    0x400\n#define    RTL8367C_CFG_PHY_BRD_MODE_OFFSET    5\n#define    RTL8367C_CFG_PHY_BRD_MODE_MASK    0x3E0\n#define    RTL8367C_CFG_BRD_PHYAD_OFFSET    0\n#define    RTL8367C_CFG_BRD_PHYAD_MASK    0x1F\n\n#define    RTL8367C_REG_PHYID_CFG1    0x1d02\n#define    RTL8367C_CFG_MSK_MDI_OFFSET    5\n#define    RTL8367C_CFG_MSK_MDI_MASK    0x1FE0\n#define    RTL8367C_CFG_BASE_PHYAD_OFFSET    0\n#define    RTL8367C_CFG_BASE_PHYAD_MASK    0x1F\n\n#define    RTL8367C_REG_PHY_POLL_CFG0    0x1d03\n#define    RTL8367C_CFG_HOTCMD_PRD_EN_OFFSET    15\n#define    RTL8367C_CFG_HOTCMD_PRD_EN_MASK    0x8000\n#define    RTL8367C_CFG_HOTCMD_EN_OFFSET    12\n#define    RTL8367C_CFG_HOTCMD_EN_MASK    0x7000\n#define    RTL8367C_CFG_POLL_PERIOD_OFFSET    8\n#define    RTL8367C_CFG_POLL_PERIOD_MASK    0xF00\n#define    RTL8367C_CFG_PERI_CMDS_RD_OFFSET    4\n#define    RTL8367C_CFG_PERI_CMDS_RD_MASK    0xF0\n#define    RTL8367C_CFG_PERI_CMDS_WR_OFFSET    0\n#define    RTL8367C_CFG_PERI_CMDS_WR_MASK    0xF\n\n#define    RTL8367C_REG_PHY_POLL_CFG1    0x1d04\n\n#define    RTL8367C_REG_PHY_POLL_CFG2    0x1d05\n\n#define    RTL8367C_REG_PHY_POLL_CFG3    0x1d06\n\n#define    RTL8367C_REG_PHY_POLL_CFG4    0x1d07\n\n#define    RTL8367C_REG_PHY_POLL_CFG5    0x1d08\n\n#define    RTL8367C_REG_PHY_POLL_CFG6    0x1d09\n\n#define    RTL8367C_REG_PHY_POLL_CFG7    0x1d0a\n\n#define    RTL8367C_REG_PHY_POLL_CFG8    0x1d0b\n\n#define    RTL8367C_REG_PHY_POLL_CFG9    0x1d0c\n\n#define    RTL8367C_REG_PHY_POLL_CFG10    0x1d0d\n\n#define    RTL8367C_REG_PHY_POLL_CFG11    0x1d0e\n\n#define    RTL8367C_REG_PHY_POLL_CFG12    0x1d0f\n\n#define    RTL8367C_REG_EFUSE_MISC    0x1d10\n#define    RTL8367C_CFG_SA_SEL_OFFSET    5\n#define    RTL8367C_CFG_SA_SEL_MASK    0x20\n#define    RTL8367C_CFG_PHYAD00_OFFSET    0\n#define    RTL8367C_CFG_PHYAD00_MASK    0x1F\n\n#define    RTL8367C_REG_SDS_MISC    0x1d11\n#define    RTL8367C_CFG_SGMII_RXFC_OFFSET    14\n#define    RTL8367C_CFG_SGMII_RXFC_MASK    0x4000\n#define    RTL8367C_CFG_SGMII_TXFC_OFFSET    13\n#define    RTL8367C_CFG_SGMII_TXFC_MASK    0x2000\n#define    RTL8367C_INB_ARB_OFFSET    12\n#define    RTL8367C_INB_ARB_MASK    0x1000\n#define    RTL8367C_CFG_MAC8_SEL_HSGMII_OFFSET    11\n#define    RTL8367C_CFG_MAC8_SEL_HSGMII_MASK    0x800\n#define    RTL8367C_CFG_SGMII_FDUP_OFFSET    10\n#define    RTL8367C_CFG_SGMII_FDUP_MASK    0x400\n#define    RTL8367C_CFG_SGMII_LINK_OFFSET    9\n#define    RTL8367C_CFG_SGMII_LINK_MASK    0x200\n#define    RTL8367C_CFG_SGMII_SPD_OFFSET    7\n#define    RTL8367C_CFG_SGMII_SPD_MASK    0x180\n#define    RTL8367C_CFG_MAC8_SEL_SGMII_OFFSET    6\n#define    RTL8367C_CFG_MAC8_SEL_SGMII_MASK    0x40\n#define    RTL8367C_CFG_INB_SEL_OFFSET    3\n#define    RTL8367C_CFG_INB_SEL_MASK    0x38\n#define    RTL8367C_CFG_SDS_MODE_18C_OFFSET    0\n#define    RTL8367C_CFG_SDS_MODE_18C_MASK    0x7\n\n#define    RTL8367C_REG_FIFO_CTRL    0x1d12\n#define    RTL8367C_CFG_LINK_DOWN_CLR_FIFO_OFFSET    11\n#define    RTL8367C_CFG_LINK_DOWN_CLR_FIFO_MASK    0x800\n#define    RTL8367C_CFG_LPBK_OFFSET    10\n#define    RTL8367C_CFG_LPBK_MASK    0x400\n#define    RTL8367C_CFG_NOT_FF_OUT_OFFSET    9\n#define    RTL8367C_CFG_NOT_FF_OUT_MASK    0x200\n#define    RTL8367C_CFG_WATER_LEVEL_FD_OFFSET    6\n#define    RTL8367C_CFG_WATER_LEVEL_FD_MASK    0x1C0\n#define    RTL8367C_CFG_WATER_LEVEL_Y2X_OFFSET    3\n#define    RTL8367C_CFG_WATER_LEVEL_Y2X_MASK    0x38\n#define    RTL8367C_CFG_WATER_LEVEL_X2Y_OFFSET    0\n#define    RTL8367C_CFG_WATER_LEVEL_X2Y_MASK    0x7\n\n#define    RTL8367C_REG_BCAM_SETTING    0x1d13\n#define    RTL8367C_CFG_BCAM_MDS_OFFSET    3\n#define    RTL8367C_CFG_BCAM_MDS_MASK    0x18\n#define    RTL8367C_CFG_BCAM_RDS_OFFSET    0\n#define    RTL8367C_CFG_BCAM_RDS_MASK    0x7\n\n#define    RTL8367C_REG_GPHY_ACS_MISC    0x1d14\n#define    RTL8367C_CFG_SEL_GPHY_SMI_OFFSET    3\n#define    RTL8367C_CFG_SEL_GPHY_SMI_MASK    0x8\n#define    RTL8367C_CFG_BRD_PHYIDX_OFFSET    0\n#define    RTL8367C_CFG_BRD_PHYIDX_MASK    0x7\n\n#define    RTL8367C_REG_GPHY_OCP_MSB_0    0x1d15\n#define    RTL8367C_CFG_CPU_OCPADR_MSB_OFFSET    6\n#define    RTL8367C_CFG_CPU_OCPADR_MSB_MASK    0xFC0\n#define    RTL8367C_CFG_DW8051_OCPADR_MSB_OFFSET    0\n#define    RTL8367C_CFG_DW8051_OCPADR_MSB_MASK    0x3F\n\n#define    RTL8367C_REG_GPHY_OCP_MSB_1    0x1d16\n#define    RTL8367C_CFG_PATCH_OCPADR_MSB_OFFSET    6\n#define    RTL8367C_CFG_PATCH_OCPADR_MSB_MASK    0xFC0\n#define    RTL8367C_CFG_PHYSTS_OCPADR_MSB_OFFSET    0\n#define    RTL8367C_CFG_PHYSTS_OCPADR_MSB_MASK    0x3F\n\n#define    RTL8367C_REG_GPHY_OCP_MSB_2    0x1d17\n#define    RTL8367C_CFG_RRCP_OCPADR_MSB_OFFSET    6\n#define    RTL8367C_CFG_RRCP_OCPADR_MSB_MASK    0xFC0\n#define    RTL8367C_CFG_RTCT_OCPADR_MSB_OFFSET    0\n#define    RTL8367C_CFG_RTCT_OCPADR_MSB_MASK    0x3F\n\n#define    RTL8367C_REG_GPHY_OCP_MSB_3    0x1d18\n#define    RTL8367C_GPHY_OCP_MSB_3_OFFSET    0\n#define    RTL8367C_GPHY_OCP_MSB_3_MASK    0x3F\n\n#define    RTL8367C_REG_GPIO_67C_I_X0    0x1d19\n\n#define    RTL8367C_REG_GPIO_67C_I_X1    0x1d1a\n\n#define    RTL8367C_REG_GPIO_67C_I_X2    0x1d1b\n\n#define    RTL8367C_REG_GPIO_67C_I_X3    0x1d1c\n#define    RTL8367C_GPIO_67C_I_X3_OFFSET    0\n#define    RTL8367C_GPIO_67C_I_X3_MASK    0x3FFF\n\n#define    RTL8367C_REG_GPIO_67C_O_X0    0x1d1d\n\n#define    RTL8367C_REG_GPIO_67C_O_X1    0x1d1e\n\n#define    RTL8367C_REG_GPIO_67C_O_X2    0x1d1f\n\n#define    RTL8367C_REG_GPIO_67C_O_X3    0x1d20\n#define    RTL8367C_GPIO_67C_O_X3_OFFSET    0\n#define    RTL8367C_GPIO_67C_O_X3_MASK    0x3FFF\n\n#define    RTL8367C_REG_GPIO_67C_OE_X0    0x1d21\n\n#define    RTL8367C_REG_GPIO_67C_OE_X1    0x1d22\n\n#define    RTL8367C_REG_GPIO_67C_OE_X2    0x1d23\n\n#define    RTL8367C_REG_GPIO_67C_OE_X3    0x1d24\n#define    RTL8367C_GPIO_67C_OE_X3_OFFSET    0\n#define    RTL8367C_GPIO_67C_OE_X3_MASK    0x3FFF\n\n#define    RTL8367C_REG_GPIO_MODE_67C_X0    0x1d25\n\n#define    RTL8367C_REG_GPIO_MODE_67C_X1    0x1d26\n\n#define    RTL8367C_REG_GPIO_MODE_67C_X2    0x1d27\n\n#define    RTL8367C_REG_GPIO_MODE_67C_X3    0x1d28\n#define    RTL8367C_GPIO_MODE_67C_X3_OFFSET    0\n#define    RTL8367C_GPIO_MODE_67C_X3_MASK    0x3FFF\n\n#define    RTL8367C_REG_WGPHY_MISC_0    0x1d29\n#define    RTL8367C_CFG_INIPHY_DISGIGA_P7_5_OFFSET    13\n#define    RTL8367C_CFG_INIPHY_DISGIGA_P7_5_MASK    0xE000\n#define    RTL8367C_CFG_INIPHY_PWRUP_OFFSET    5\n#define    RTL8367C_CFG_INIPHY_PWRUP_MASK    0x1FE0\n#define    RTL8367C_CFG_INIPHY_DISGIGA_OFFSET    0\n#define    RTL8367C_CFG_INIPHY_DISGIGA_MASK    0x1F\n\n#define    RTL8367C_REG_WGPHY_MISC_1    0x1d2a\n#define    RTL8367C_WGPHY_MISC_1_OFFSET    0\n#define    RTL8367C_WGPHY_MISC_1_MASK    0xFF\n\n#define    RTL8367C_REG_WGPHY_MISC_2    0x1d2b\n#define    RTL8367C_WGPHY_MISC_2_OFFSET    0\n#define    RTL8367C_WGPHY_MISC_2_MASK    0x3FF\n\n#define    RTL8367C_REG_CFG_AFBK_GPHY_0    0x1d2c\n#define    RTL8367C_CFG_AFBK_GPHY_0_OFFSET    0\n#define    RTL8367C_CFG_AFBK_GPHY_0_MASK    0x1F\n\n#define    RTL8367C_REG_CFG_AFBK_GPHY_1    0x1d2d\n#define    RTL8367C_CFG_AFBK_GPHY_1_OFFSET    0\n#define    RTL8367C_CFG_AFBK_GPHY_1_MASK    0xFFF\n\n#define    RTL8367C_REG_EF_SLV_CTRL_0    0x1d2e\n#define    RTL8367C_EF_SLV_BUSY_OFFSET    11\n#define    RTL8367C_EF_SLV_BUSY_MASK    0x800\n#define    RTL8367C_EF_SLV_ACK_OFFSET    10\n#define    RTL8367C_EF_SLV_ACK_MASK    0x400\n#define    RTL8367C_EF_SLV_A_OFFSET    2\n#define    RTL8367C_EF_SLV_A_MASK    0x3FC\n#define    RTL8367C_EF_SLV_WE_OFFSET    1\n#define    RTL8367C_EF_SLV_WE_MASK    0x2\n#define    RTL8367C_EF_SLV_CE_OFFSET    0\n#define    RTL8367C_EF_SLV_CE_MASK    0x1\n\n#define    RTL8367C_REG_EF_SLV_CTRL_1    0x1d2f\n\n#define    RTL8367C_REG_EF_SLV_CTRL_2    0x1d30\n\n#define    RTL8367C_REG_EFUSE_MISC_1    0x1d31\n#define    RTL8367C_EF_EN_EFUSE_OFFSET    10\n#define    RTL8367C_EF_EN_EFUSE_MASK    0x400\n#define    RTL8367C_EF_MODEL_ID_OFFSET    6\n#define    RTL8367C_EF_MODEL_ID_MASK    0x3C0\n#define    RTL8367C_EF_RSVD_OFFSET    2\n#define    RTL8367C_EF_RSVD_MASK    0x3C\n#define    RTL8367C_EF_SYS_CLK_OFFSET    0\n#define    RTL8367C_EF_SYS_CLK_MASK    0x3\n\n#define    RTL8367C_REG_IO_MISC_FUNC    0x1d32\n#define    RTL8367C_TST_MODE_OFFSET    3\n#define    RTL8367C_TST_MODE_MASK    0x8\n#define    RTL8367C_UART_EN_OFFSET    2\n#define    RTL8367C_UART_EN_MASK    0x4\n#define    RTL8367C_INT_EN_OFFSET    1\n#define    RTL8367C_INT_EN_MASK    0x2\n#define    RTL8367C_BUZ_EN_OFFSET    0\n#define    RTL8367C_BUZ_EN_MASK    0x1\n\n#define    RTL8367C_REG_HTRAM_DVS    0x1d33\n#define    RTL8367C_HTRAM_DVS_OFFSET    0\n#define    RTL8367C_HTRAM_DVS_MASK    0x1\n\n#define    RTL8367C_REG_EF_SLV_CTRL_3    0x1d34\n#define    RTL8367C_EF_SLV_CTRL_3_OFFSET    0\n#define    RTL8367C_EF_SLV_CTRL_3_MASK    0x1\n\n#define    RTL8367C_REG_INBAND_EN14C    0x1d35\n#define    RTL8367C_INBAND_EN14C_OFFSET    0\n#define    RTL8367C_INBAND_EN14C_MASK    0x1\n\n#define    RTL8367C_REG_CFG_SWR_L    0x1d36\n#define    RTL8367C_ANARG_RDY_SWR_L_OFFSET    14\n#define    RTL8367C_ANARG_RDY_SWR_L_MASK    0x4000\n#define    RTL8367C_ANARG_VALID_SWR_L_OFFSET    13\n#define    RTL8367C_ANARG_VALID_SWR_L_MASK    0x2000\n#define    RTL8367C_SAW_SWR_L_OFFSET    9\n#define    RTL8367C_SAW_SWR_L_MASK    0x1E00\n#define    RTL8367C_SAW_VALID_SWR_L_OFFSET    8\n#define    RTL8367C_SAW_VALID_SWR_L_MASK    0x100\n#define    RTL8367C_UPS_DBGO_L_OFFSET    0\n#define    RTL8367C_UPS_DBGO_L_MASK    0xFF\n\n#define    RTL8367C_REG_BTCAM_CTRL    0x1d37\n#define    RTL8367C_TCAM_RDS_OFFSET    2\n#define    RTL8367C_TCAM_RDS_MASK    0x1C\n#define    RTL8367C_TCAM_MDS_OFFSET    0\n#define    RTL8367C_TCAM_MDS_MASK    0x3\n\n#define    RTL8367C_REG_PBRAM_BISR_CTRL    0x1d38\n#define    RTL8367C_HAS_HLDRMP_MD_OFFSET    9\n#define    RTL8367C_HAS_HLDRMP_MD_MASK    0x200\n#define    RTL8367C_PB_HLDRMP_MD_OFFSET    8\n#define    RTL8367C_PB_HLDRMP_MD_MASK    0x100\n#define    RTL8367C_HAS_BISR_BIRSTN_OFFSET    7\n#define    RTL8367C_HAS_BISR_BIRSTN_MASK    0x80\n#define    RTL8367C_SEC_RUN_HSA_OFFSET    6\n#define    RTL8367C_SEC_RUN_HSA_MASK    0x40\n#define    RTL8367C_HAS_HLDRMP_VAL_OFFSET    5\n#define    RTL8367C_HAS_HLDRMP_VAL_MASK    0x20\n#define    RTL8367C_HAS_BISR_PWRSTN_OFFSET    4\n#define    RTL8367C_HAS_BISR_PWRSTN_MASK    0x10\n#define    RTL8367C_SEC_RUN_PB_OFFSET    3\n#define    RTL8367C_SEC_RUN_PB_MASK    0x8\n#define    RTL8367C_PB_HLDRMP_VAL_OFFSET    2\n#define    RTL8367C_PB_HLDRMP_VAL_MASK    0x4\n#define    RTL8367C_PB_BISR_BIRSTN_OFFSET    1\n#define    RTL8367C_PB_BISR_BIRSTN_MASK    0x2\n#define    RTL8367C_PB_BISR_PWRSTN_OFFSET    0\n#define    RTL8367C_PB_BISR_PWRSTN_MASK    0x1\n\n#define    RTL8367C_REG_CVLANRAM_BISR_CTRL    0x1d39\n#define    RTL8367C_SEC_RUN_CVLAN_OFFSET    4\n#define    RTL8367C_SEC_RUN_CVLAN_MASK    0x10\n#define    RTL8367C_CVALN_HLDRMP_MD_OFFSET    3\n#define    RTL8367C_CVALN_HLDRMP_MD_MASK    0x8\n#define    RTL8367C_CVALN_HLDRMP_VAL_OFFSET    2\n#define    RTL8367C_CVALN_HLDRMP_VAL_MASK    0x4\n#define    RTL8367C_CVLAN_BISR_BIRSTN_OFFSET    1\n#define    RTL8367C_CVLAN_BISR_BIRSTN_MASK    0x2\n#define    RTL8367C_CVLAN_BISR_PWRSTN_OFFSET    0\n#define    RTL8367C_CVLAN_BISR_PWRSTN_MASK    0x1\n\n#define    RTL8367C_REG_CFG_1588_TIMER_EN_GPI    0x1d3a\n#define    RTL8367C_CFG_1588_TIMER_EN_GPI_OFFSET    0\n#define    RTL8367C_CFG_1588_TIMER_EN_GPI_MASK    0x1\n\n#define    RTL8367C_REG_MDIO_PRMB_SUPP    0x1d3b\n#define    RTL8367C_FIB_HIPRI_OFFSET    14\n#define    RTL8367C_FIB_HIPRI_MASK    0x4000\n#define    RTL8367C_SMT_EN_OFFSET    13\n#define    RTL8367C_SMT_EN_MASK    0x2000\n#define    RTL8367C_P4_FB_CPL_OFFSET    12\n#define    RTL8367C_P4_FB_CPL_MASK    0x1000\n#define    RTL8367C_P3_FB_CPL_OFFSET    11\n#define    RTL8367C_P3_FB_CPL_MASK    0x800\n#define    RTL8367C_P2_FB_CPL_OFFSET    10\n#define    RTL8367C_P2_FB_CPL_MASK    0x400\n#define    RTL8367C_P1_FB_CPL_OFFSET    9\n#define    RTL8367C_P1_FB_CPL_MASK    0x200\n#define    RTL8367C_P0_FB_CPL_OFFSET    8\n#define    RTL8367C_P0_FB_CPL_MASK    0x100\n#define    RTL8367C_DBG_PKG_8367N_OFFSET    7\n#define    RTL8367C_DBG_PKG_8367N_MASK    0x80\n#define    RTL8367C_DBG_PKG_8367VB_OFFSET    6\n#define    RTL8367C_DBG_PKG_8367VB_MASK    0x40\n#define    RTL8367C_CFG_DEBUG_EN_OFFSET    5\n#define    RTL8367C_CFG_DEBUG_EN_MASK    0x20\n#define    RTL8367C_CFG_TMR_ACK_OFFSET    1\n#define    RTL8367C_CFG_TMR_ACK_MASK    0x1E\n#define    RTL8367C_CFG_PRMB_SUPP_OFFSET    0\n#define    RTL8367C_CFG_PRMB_SUPP_MASK    0x1\n\n#define    RTL8367C_REG_BOND4READ    0x1d3c\n#define    RTL8367C_BOND_BOID0_OFFSET    8\n#define    RTL8367C_BOND_BOID0_MASK    0x100\n#define    RTL8367C_BOND_SYSCLK_OFFSET    7\n#define    RTL8367C_BOND_SYSCLK_MASK    0x80\n#define    RTL8367C_BOND_PHYMODE_OFFSET    6\n#define    RTL8367C_BOND_PHYMODE_MASK    0x40\n#define    RTL8367C_BOND_DIS_PON_BIST_OFFSET    5\n#define    RTL8367C_BOND_DIS_PON_BIST_MASK    0x20\n#define    RTL8367C_BOND_DIS_TABLE_INIT_OFFSET    4\n#define    RTL8367C_BOND_DIS_TABLE_INIT_MASK    0x10\n#define    RTL8367C_BOND_BYP_AFE_PLL_OFFSET    3\n#define    RTL8367C_BOND_BYP_AFE_PLL_MASK    0x8\n#define    RTL8367C_BOND_BYP_AFE_POR_OFFSET    2\n#define    RTL8367C_BOND_BYP_AFE_POR_MASK    0x4\n#define    RTL8367C_BOND_BISR_COND_OFFSET    1\n#define    RTL8367C_BOND_BISR_COND_MASK    0x2\n#define    RTL8367C_BOND_EF_EN_OFFSET    0\n#define    RTL8367C_BOND_EF_EN_MASK    0x1\n\n#define    RTL8367C_REG_REG_TO_ECO0    0x1d3d\n\n#define    RTL8367C_REG_REG_TO_ECO1    0x1d3e\n\n#define    RTL8367C_REG_REG_TO_ECO2    0x1d3f\n\n#define    RTL8367C_REG_REG_TO_ECO3    0x1d40\n\n#define    RTL8367C_REG_REG_TO_ECO4    0x1d41\n\n#define    RTL8367C_REG_PHYSTS_CTRL0    0x1d42\n#define    RTL8367C_MACRX_DUPDET_EN_OFFSET    5\n#define    RTL8367C_MACRX_DUPDET_EN_MASK    0x20\n#define    RTL8367C_LNKUP_DLY_EN_OFFSET    4\n#define    RTL8367C_LNKUP_DLY_EN_MASK    0x10\n#define    RTL8367C_GE_100M_LNKUP_DLY_OFFSET    2\n#define    RTL8367C_GE_100M_LNKUP_DLY_MASK    0xC\n#define    RTL8367C_PHYSTS_10M_LNKUP_DLY_OFFSET    0\n#define    RTL8367C_PHYSTS_10M_LNKUP_DLY_MASK    0x3\n\n#define    RTL8367C_REG_SSC_CTRL0_0    0x1d44\n#define    RTL8367C_SSC_CTRL0_0_SSC_TYPE_OFFSET    13\n#define    RTL8367C_SSC_CTRL0_0_SSC_TYPE_MASK    0x2000\n#define    RTL8367C_SSC_CTRL0_0_PHASE_LIM_SEL_OFFSET    5\n#define    RTL8367C_SSC_CTRL0_0_PHASE_LIM_SEL_MASK    0x1FE0\n#define    RTL8367C_SSC_CTRL0_0_PHASE_LIM_EN_OFFSET    4\n#define    RTL8367C_SSC_CTRL0_0_PHASE_LIM_EN_MASK    0x10\n#define    RTL8367C_SSC_CTRL0_0_DLL_MODE_OFFSET    2\n#define    RTL8367C_SSC_CTRL0_0_DLL_MODE_MASK    0xC\n#define    RTL8367C_SSC_CTRL0_0_SSC_EN_OFFSET    1\n#define    RTL8367C_SSC_CTRL0_0_SSC_EN_MASK    0x2\n#define    RTL8367C_SSC_CTRL0_0_SSC_MODE_OFFSET    0\n#define    RTL8367C_SSC_CTRL0_0_SSC_MODE_MASK    0x1\n\n#define    RTL8367C_REG_SSC_RDM_SEED    0x1d45\n\n#define    RTL8367C_REG_SSC_PN_POLY_SEL    0x1d46\n\n#define    RTL8367C_REG_SSC_CTRL0_3    0x1d47\n#define    RTL8367C_SSC_CTRL0_3_PHSFT_CNT_OFFSET    8\n#define    RTL8367C_SSC_CTRL0_3_PHSFT_CNT_MASK    0x7F00\n#define    RTL8367C_SSC_CTRL0_3_PHSFT_A_OFFSET    7\n#define    RTL8367C_SSC_CTRL0_3_PHSFT_A_MASK    0x80\n#define    RTL8367C_SSC_CTRL0_3_PHSFT_B_OFFSET    6\n#define    RTL8367C_SSC_CTRL0_3_PHSFT_B_MASK    0x40\n#define    RTL8367C_SSC_CTRL0_3_PHSFT_UPDN_OFFSET    5\n#define    RTL8367C_SSC_CTRL0_3_PHSFT_UPDN_MASK    0x20\n#define    RTL8367C_SSC_CTRL0_3_PHSFT_PRD_OFFSET    4\n#define    RTL8367C_SSC_CTRL0_3_PHSFT_PRD_MASK    0x10\n#define    RTL8367C_SSC_CTRL0_3_PN_POLY_DEG_OFFSET    0\n#define    RTL8367C_SSC_CTRL0_3_PN_POLY_DEG_MASK    0xF\n\n#define    RTL8367C_REG_SSC_CTRL0_4    0x1d48\n#define    RTL8367C_SSC_CTRL0_4_SSC_UP1DN0_OFFSET    15\n#define    RTL8367C_SSC_CTRL0_4_SSC_UP1DN0_MASK    0x8000\n#define    RTL8367C_SSC_CTRL0_4_SSC_PERIOD_OFFSET    8\n#define    RTL8367C_SSC_CTRL0_4_SSC_PERIOD_MASK    0x7F00\n#define    RTL8367C_SSC_CTRL0_4_SSC_OFFSET_OFFSET    0\n#define    RTL8367C_SSC_CTRL0_4_SSC_OFFSET_MASK    0xFF\n\n#define    RTL8367C_REG_SSC_CTRL0_5    0x1d49\n#define    RTL8367C_SSC_CTRL0_5_PH_OFS_TOG_OFFSET    15\n#define    RTL8367C_SSC_CTRL0_5_PH_OFS_TOG_MASK    0x8000\n#define    RTL8367C_SSC_CTRL0_5_PH_OFS_OFFSET    10\n#define    RTL8367C_SSC_CTRL0_5_PH_OFS_MASK    0x7C00\n#define    RTL8367C_SSC_CTRL0_5_SSC_STEP_OFFSET    4\n#define    RTL8367C_SSC_CTRL0_5_SSC_STEP_MASK    0x3F0\n#define    RTL8367C_SSC_CTRL0_5_SSC_TEST_MODE_OFFSET    2\n#define    RTL8367C_SSC_CTRL0_5_SSC_TEST_MODE_MASK    0xC\n#define    RTL8367C_SSC_CTRL0_5_SSC_PH_CFG_OFFSET    0\n#define    RTL8367C_SSC_CTRL0_5_SSC_PH_CFG_MASK    0x3\n\n#define    RTL8367C_REG_SSC_STS0    0x1d4a\n#define    RTL8367C_SSC_STS0_OFS_BUSY_OFFSET    13\n#define    RTL8367C_SSC_STS0_OFS_BUSY_MASK    0x2000\n#define    RTL8367C_SSC_STS0_OFS_TOTAL_R_OFFSET    8\n#define    RTL8367C_SSC_STS0_OFS_TOTAL_R_MASK    0x1F00\n#define    RTL8367C_SSC_STS0_CNT_GRY0_OFFSET    4\n#define    RTL8367C_SSC_STS0_CNT_GRY0_MASK    0xF0\n#define    RTL8367C_SSC_STS0_OFS_GRY0_OFFSET    0\n#define    RTL8367C_SSC_STS0_OFS_GRY0_MASK    0xF\n\n#define    RTL8367C_REG_SSC_CTRL1_0    0x1d4b\n#define    RTL8367C_SSC_CTRL1_0_SSC_TYPE_OFFSET    13\n#define    RTL8367C_SSC_CTRL1_0_SSC_TYPE_MASK    0x2000\n#define    RTL8367C_SSC_CTRL1_0_PHASE_LIM_SEL_OFFSET    5\n#define    RTL8367C_SSC_CTRL1_0_PHASE_LIM_SEL_MASK    0x1FE0\n#define    RTL8367C_SSC_CTRL1_0_PHASE_LIM_EN_OFFSET    4\n#define    RTL8367C_SSC_CTRL1_0_PHASE_LIM_EN_MASK    0x10\n#define    RTL8367C_SSC_CTRL1_0_DLL_MODE_OFFSET    2\n#define    RTL8367C_SSC_CTRL1_0_DLL_MODE_MASK    0xC\n#define    RTL8367C_SSC_CTRL1_0_SSC_EN_OFFSET    1\n#define    RTL8367C_SSC_CTRL1_0_SSC_EN_MASK    0x2\n#define    RTL8367C_SSC_CTRL1_0_SSC_MODE_OFFSET    0\n#define    RTL8367C_SSC_CTRL1_0_SSC_MODE_MASK    0x1\n\n#define    RTL8367C_REG_SSC_RDM_SEED1    0x1d4c\n\n#define    RTL8367C_REG_SSC_PN_POLY_SEL1    0x1d4d\n\n#define    RTL8367C_REG_SSC_CTRL1_3    0x1d4e\n#define    RTL8367C_SSC_CTRL1_3_PHSFT_CNT_OFFSET    8\n#define    RTL8367C_SSC_CTRL1_3_PHSFT_CNT_MASK    0x7F00\n#define    RTL8367C_SSC_CTRL1_3_PHSFT_A_OFFSET    7\n#define    RTL8367C_SSC_CTRL1_3_PHSFT_A_MASK    0x80\n#define    RTL8367C_SSC_CTRL1_3_PHSFT_B_OFFSET    6\n#define    RTL8367C_SSC_CTRL1_3_PHSFT_B_MASK    0x40\n#define    RTL8367C_SSC_CTRL1_3_PHSFT_UPDN_OFFSET    5\n#define    RTL8367C_SSC_CTRL1_3_PHSFT_UPDN_MASK    0x20\n#define    RTL8367C_SSC_CTRL1_3_PHSFT_PRD_OFFSET    4\n#define    RTL8367C_SSC_CTRL1_3_PHSFT_PRD_MASK    0x10\n#define    RTL8367C_SSC_CTRL1_3_PN_POLY_DEG_OFFSET    0\n#define    RTL8367C_SSC_CTRL1_3_PN_POLY_DEG_MASK    0xF\n\n#define    RTL8367C_REG_SSC_CTRL1_4    0x1d4f\n#define    RTL8367C_SSC_CTRL1_4_SSC_UP1DN0_OFFSET    15\n#define    RTL8367C_SSC_CTRL1_4_SSC_UP1DN0_MASK    0x8000\n#define    RTL8367C_SSC_CTRL1_4_SSC_PERIOD_OFFSET    8\n#define    RTL8367C_SSC_CTRL1_4_SSC_PERIOD_MASK    0x7F00\n#define    RTL8367C_SSC_CTRL1_4_SSC_OFFSET_OFFSET    0\n#define    RTL8367C_SSC_CTRL1_4_SSC_OFFSET_MASK    0xFF\n\n#define    RTL8367C_REG_SSC_CTRL1_5    0x1d50\n#define    RTL8367C_SSC_CTRL1_5_PH_OFS_TOG_OFFSET    15\n#define    RTL8367C_SSC_CTRL1_5_PH_OFS_TOG_MASK    0x8000\n#define    RTL8367C_SSC_CTRL1_5_PH_OFS_OFFSET    10\n#define    RTL8367C_SSC_CTRL1_5_PH_OFS_MASK    0x7C00\n#define    RTL8367C_SSC_CTRL1_5_SSC_STEP_OFFSET    4\n#define    RTL8367C_SSC_CTRL1_5_SSC_STEP_MASK    0x3F0\n#define    RTL8367C_SSC_CTRL1_5_SSC_TEST_MODE_OFFSET    2\n#define    RTL8367C_SSC_CTRL1_5_SSC_TEST_MODE_MASK    0xC\n#define    RTL8367C_SSC_CTRL1_5_SSC_PH_CFG_OFFSET    0\n#define    RTL8367C_SSC_CTRL1_5_SSC_PH_CFG_MASK    0x3\n\n#define    RTL8367C_REG_SSC_STS1    0x1d51\n#define    RTL8367C_SSC_STS1_OFS_BUSY_OFFSET    13\n#define    RTL8367C_SSC_STS1_OFS_BUSY_MASK    0x2000\n#define    RTL8367C_SSC_STS1_OFS_TOTAL_R_OFFSET    8\n#define    RTL8367C_SSC_STS1_OFS_TOTAL_R_MASK    0x1F00\n#define    RTL8367C_SSC_STS1_CNT_GRY0_OFFSET    4\n#define    RTL8367C_SSC_STS1_CNT_GRY0_MASK    0xF0\n#define    RTL8367C_SSC_STS1_OFS_GRY0_OFFSET    0\n#define    RTL8367C_SSC_STS1_OFS_GRY0_MASK    0xF\n\n#define    RTL8367C_REG_SSC_CTRL2_0    0x1d52\n#define    RTL8367C_SSC_CTRL2_0_SSC_TYPE_OFFSET    13\n#define    RTL8367C_SSC_CTRL2_0_SSC_TYPE_MASK    0x2000\n#define    RTL8367C_SSC_CTRL2_0_PHASE_LIM_SEL_OFFSET    5\n#define    RTL8367C_SSC_CTRL2_0_PHASE_LIM_SEL_MASK    0x1FE0\n#define    RTL8367C_SSC_CTRL2_0_PHASE_LIM_EN_OFFSET    4\n#define    RTL8367C_SSC_CTRL2_0_PHASE_LIM_EN_MASK    0x10\n#define    RTL8367C_SSC_CTRL2_0_DLL_MODE_OFFSET    2\n#define    RTL8367C_SSC_CTRL2_0_DLL_MODE_MASK    0xC\n#define    RTL8367C_SSC_CTRL2_0_SSC_EN_OFFSET    1\n#define    RTL8367C_SSC_CTRL2_0_SSC_EN_MASK    0x2\n#define    RTL8367C_SSC_CTRL2_0_SSC_MODE_OFFSET    0\n#define    RTL8367C_SSC_CTRL2_0_SSC_MODE_MASK    0x1\n\n#define    RTL8367C_REG_SSC_RDM_SEED2    0x1d53\n\n#define    RTL8367C_REG_SSC_PN_POLY_SEL2    0x1d54\n\n#define    RTL8367C_REG_SSC_CTRL2_3    0x1d55\n#define    RTL8367C_SSC_CTRL2_3_PHSFT_CNT_OFFSET    8\n#define    RTL8367C_SSC_CTRL2_3_PHSFT_CNT_MASK    0x7F00\n#define    RTL8367C_SSC_CTRL2_3_PHSFT_A_OFFSET    7\n#define    RTL8367C_SSC_CTRL2_3_PHSFT_A_MASK    0x80\n#define    RTL8367C_SSC_CTRL2_3_PHSFT_B_OFFSET    6\n#define    RTL8367C_SSC_CTRL2_3_PHSFT_B_MASK    0x40\n#define    RTL8367C_SSC_CTRL2_3_PHSFT_UPDN_OFFSET    5\n#define    RTL8367C_SSC_CTRL2_3_PHSFT_UPDN_MASK    0x20\n#define    RTL8367C_SSC_CTRL2_3_PHSFT_PRD_OFFSET    4\n#define    RTL8367C_SSC_CTRL2_3_PHSFT_PRD_MASK    0x10\n#define    RTL8367C_SSC_CTRL2_3_PN_POLY_DEG_OFFSET    0\n#define    RTL8367C_SSC_CTRL2_3_PN_POLY_DEG_MASK    0xF\n\n#define    RTL8367C_REG_SSC_CTRL2_4    0x1d56\n#define    RTL8367C_SSC_CTRL2_4_SSC_UP1DN0_OFFSET    15\n#define    RTL8367C_SSC_CTRL2_4_SSC_UP1DN0_MASK    0x8000\n#define    RTL8367C_SSC_CTRL2_4_SSC_PERIOD_OFFSET    8\n#define    RTL8367C_SSC_CTRL2_4_SSC_PERIOD_MASK    0x7F00\n#define    RTL8367C_SSC_CTRL2_4_SSC_OFFSET_OFFSET    0\n#define    RTL8367C_SSC_CTRL2_4_SSC_OFFSET_MASK    0xFF\n\n#define    RTL8367C_REG_SSC_CTRL2_5    0x1d57\n#define    RTL8367C_SSC_CTRL2_5_PH_OFS_TOG_OFFSET    15\n#define    RTL8367C_SSC_CTRL2_5_PH_OFS_TOG_MASK    0x8000\n#define    RTL8367C_SSC_CTRL2_5_PH_OFS_OFFSET    10\n#define    RTL8367C_SSC_CTRL2_5_PH_OFS_MASK    0x7C00\n#define    RTL8367C_SSC_CTRL2_5_SSC_STEP_OFFSET    4\n#define    RTL8367C_SSC_CTRL2_5_SSC_STEP_MASK    0x3F0\n#define    RTL8367C_SSC_CTRL2_5_SSC_TEST_MODE_OFFSET    2\n#define    RTL8367C_SSC_CTRL2_5_SSC_TEST_MODE_MASK    0xC\n#define    RTL8367C_SSC_CTRL2_5_SSC_PH_CFG_OFFSET    0\n#define    RTL8367C_SSC_CTRL2_5_SSC_PH_CFG_MASK    0x3\n\n#define    RTL8367C_REG_SSC_STS2    0x1d58\n#define    RTL8367C_SSC_STS2_OFS_BUSY_OFFSET    13\n#define    RTL8367C_SSC_STS2_OFS_BUSY_MASK    0x2000\n#define    RTL8367C_SSC_STS2_OFS_TOTAL_R_OFFSET    8\n#define    RTL8367C_SSC_STS2_OFS_TOTAL_R_MASK    0x1F00\n#define    RTL8367C_SSC_STS2_CNT_GRY0_OFFSET    4\n#define    RTL8367C_SSC_STS2_CNT_GRY0_MASK    0xF0\n#define    RTL8367C_SSC_STS2_OFS_GRY0_OFFSET    0\n#define    RTL8367C_SSC_STS2_OFS_GRY0_MASK    0xF\n\n#define    RTL8367C_REG_SSC_CTRL3_0    0x1d59\n#define    RTL8367C_SSC_CTRL3_0_SSC_TYPE_OFFSET    13\n#define    RTL8367C_SSC_CTRL3_0_SSC_TYPE_MASK    0x2000\n#define    RTL8367C_SSC_CTRL3_0_PHASE_LIM_SEL_OFFSET    5\n#define    RTL8367C_SSC_CTRL3_0_PHASE_LIM_SEL_MASK    0x1FE0\n#define    RTL8367C_SSC_CTRL3_0_PHASE_LIM_EN_OFFSET    4\n#define    RTL8367C_SSC_CTRL3_0_PHASE_LIM_EN_MASK    0x10\n#define    RTL8367C_SSC_CTRL3_0_DLL_MODE_OFFSET    2\n#define    RTL8367C_SSC_CTRL3_0_DLL_MODE_MASK    0xC\n#define    RTL8367C_SSC_CTRL3_0_SSC_EN_OFFSET    1\n#define    RTL8367C_SSC_CTRL3_0_SSC_EN_MASK    0x2\n#define    RTL8367C_SSC_CTRL3_0_SSC_MODE_OFFSET    0\n#define    RTL8367C_SSC_CTRL3_0_SSC_MODE_MASK    0x1\n\n#define    RTL8367C_REG_SSC_RDM_SEED3    0x1d5a\n\n#define    RTL8367C_REG_SSC_PN_POLY_SEL3    0x1d5b\n\n#define    RTL8367C_REG_SSC_CTRL3_3    0x1d5c\n#define    RTL8367C_SSC_CTRL3_3_PHSFT_CNT_OFFSET    8\n#define    RTL8367C_SSC_CTRL3_3_PHSFT_CNT_MASK    0x7F00\n#define    RTL8367C_SSC_CTRL3_3_PHSFT_A_OFFSET    7\n#define    RTL8367C_SSC_CTRL3_3_PHSFT_A_MASK    0x80\n#define    RTL8367C_SSC_CTRL3_3_PHSFT_B_OFFSET    6\n#define    RTL8367C_SSC_CTRL3_3_PHSFT_B_MASK    0x40\n#define    RTL8367C_SSC_CTRL3_3_PHSFT_UPDN_OFFSET    5\n#define    RTL8367C_SSC_CTRL3_3_PHSFT_UPDN_MASK    0x20\n#define    RTL8367C_SSC_CTRL3_3_PHSFT_PRD_OFFSET    4\n#define    RTL8367C_SSC_CTRL3_3_PHSFT_PRD_MASK    0x10\n#define    RTL8367C_SSC_CTRL3_3_PN_POLY_DEG_OFFSET    0\n#define    RTL8367C_SSC_CTRL3_3_PN_POLY_DEG_MASK    0xF\n\n#define    RTL8367C_REG_SSC_CTRL3_4    0x1d5d\n#define    RTL8367C_SSC_CTRL3_4_SSC_UP1DN0_OFFSET    15\n#define    RTL8367C_SSC_CTRL3_4_SSC_UP1DN0_MASK    0x8000\n#define    RTL8367C_SSC_CTRL3_4_SSC_PERIOD_OFFSET    8\n#define    RTL8367C_SSC_CTRL3_4_SSC_PERIOD_MASK    0x7F00\n#define    RTL8367C_SSC_CTRL3_4_SSC_OFFSET_OFFSET    0\n#define    RTL8367C_SSC_CTRL3_4_SSC_OFFSET_MASK    0xFF\n\n#define    RTL8367C_REG_SSC_CTRL3_5    0x1d5e\n#define    RTL8367C_SSC_CTRL3_5_PH_OFS_TOG_OFFSET    15\n#define    RTL8367C_SSC_CTRL3_5_PH_OFS_TOG_MASK    0x8000\n#define    RTL8367C_SSC_CTRL3_5_PH_OFS_OFFSET    10\n#define    RTL8367C_SSC_CTRL3_5_PH_OFS_MASK    0x7C00\n#define    RTL8367C_SSC_CTRL3_5_SSC_STEP_OFFSET    4\n#define    RTL8367C_SSC_CTRL3_5_SSC_STEP_MASK    0x3F0\n#define    RTL8367C_SSC_CTRL3_5_SSC_TEST_MODE_OFFSET    2\n#define    RTL8367C_SSC_CTRL3_5_SSC_TEST_MODE_MASK    0xC\n#define    RTL8367C_SSC_CTRL3_5_SSC_PH_CFG_OFFSET    0\n#define    RTL8367C_SSC_CTRL3_5_SSC_PH_CFG_MASK    0x3\n\n#define    RTL8367C_REG_SSC_STS3    0x1d5f\n#define    RTL8367C_SSC_STS3_OFS_BUSY_OFFSET    13\n#define    RTL8367C_SSC_STS3_OFS_BUSY_MASK    0x2000\n#define    RTL8367C_SSC_STS3_OFS_TOTAL_R_OFFSET    8\n#define    RTL8367C_SSC_STS3_OFS_TOTAL_R_MASK    0x1F00\n#define    RTL8367C_SSC_STS3_CNT_GRY0_OFFSET    4\n#define    RTL8367C_SSC_STS3_CNT_GRY0_MASK    0xF0\n#define    RTL8367C_SSC_STS3_OFS_GRY0_OFFSET    0\n#define    RTL8367C_SSC_STS3_OFS_GRY0_MASK    0xF\n\n#define    RTL8367C_REG_PHY_POLL_CFG13    0x1d60\n\n#define    RTL8367C_REG_PHY_POLL_CFG14    0x1d61\n\n#define    RTL8367C_REG_FRC_SYS_CLK    0x1d62\n#define    RTL8367C_SYSCLK_FRC_MD_OFFSET    1\n#define    RTL8367C_SYSCLK_FRC_MD_MASK    0x2\n#define    RTL8367C_SYSCLK_FRC_VAL_OFFSET    0\n#define    RTL8367C_SYSCLK_FRC_VAL_MASK    0x1\n\n#define    RTL8367C_REG_AFE_SSC_CTRL    0x1d63\n#define    RTL8367C_PH_RSTB_TXD1_OFFSET    9\n#define    RTL8367C_PH_RSTB_TXD1_MASK    0x200\n#define    RTL8367C_PH_RSTB_TXC1_OFFSET    8\n#define    RTL8367C_PH_RSTB_TXC1_MASK    0x100\n#define    RTL8367C_PH_RSTB_TXD0_OFFSET    7\n#define    RTL8367C_PH_RSTB_TXD0_MASK    0x80\n#define    RTL8367C_PH_RSTB_TXC0_OFFSET    6\n#define    RTL8367C_PH_RSTB_TXC0_MASK    0x40\n#define    RTL8367C_PH_RSTBSYS_OFFSET    5\n#define    RTL8367C_PH_RSTBSYS_MASK    0x20\n#define    RTL8367C_PH_RSTB8051_OFFSET    4\n#define    RTL8367C_PH_RSTB8051_MASK    0x10\n#define    RTL8367C_OREG_SSC_OFFSET    0\n#define    RTL8367C_OREG_SSC_MASK    0xF\n\n#define    RTL8367C_REG_BUFF_RST_CTRL0    0x1d64\n#define    RTL8367C_BUFFRST_TXESD_EN_OFFSET    13\n#define    RTL8367C_BUFFRST_TXESD_EN_MASK    0x2000\n#define    RTL8367C_BUFF_RST_TIME_LONG_OFFSET    8\n#define    RTL8367C_BUFF_RST_TIME_LONG_MASK    0x1F00\n#define    RTL8367C_BUFF_RST_TIME_SHORT_OFFSET    3\n#define    RTL8367C_BUFF_RST_TIME_SHORT_MASK    0xF8\n#define    RTL8367C_SW_BUFF_RST_OFFSET    2\n#define    RTL8367C_SW_BUFF_RST_MASK    0x4\n#define    RTL8367C_IMS_BUFF_RST_OFFSET    1\n#define    RTL8367C_IMS_BUFF_RST_MASK    0x2\n#define    RTL8367C_IMR_BUFF_RST_OFFSET    0\n#define    RTL8367C_IMR_BUFF_RST_MASK    0x1\n\n#define    RTL8367C_REG_BUFF_RST_CTRL1    0x1d65\n#define    RTL8367C_BUFFRST_SYSOVER_EN_OFFSET    10\n#define    RTL8367C_BUFFRST_SYSOVER_EN_MASK    0x400\n#define    RTL8367C_BUFFRST_SYSOVER_THR_OFFSET    0\n#define    RTL8367C_BUFFRST_SYSOVER_THR_MASK    0x3FF\n\n#define    RTL8367C_REG_BUFF_RST_CTRL2    0x1d66\n#define    RTL8367C_BUFFRST_QOVER_EN_OFFSET    10\n#define    RTL8367C_BUFFRST_QOVER_EN_MASK    0x400\n#define    RTL8367C_BUFFRST_QOVER_THR_OFFSET    0\n#define    RTL8367C_BUFFRST_QOVER_THR_MASK    0x3FF\n\n#define    RTL8367C_REG_BUFF_RST_CTRL3    0x1d67\n#define    RTL8367C_DSC_TIMER_OFFSET    11\n#define    RTL8367C_DSC_TIMER_MASK    0x7800\n#define    RTL8367C_BUFFRST_DSCOVER_THR_OFFSET    1\n#define    RTL8367C_BUFFRST_DSCOVER_THR_MASK    0x7FE\n#define    RTL8367C_BUFFRST_DSCOVER_EN_OFFSET    0\n#define    RTL8367C_BUFFRST_DSCOVER_EN_MASK    0x1\n\n#define    RTL8367C_REG_BUFF_RST_CTRL4    0x1d68\n#define    RTL8367C_INDSC_TIMER_OFFSET    11\n#define    RTL8367C_INDSC_TIMER_MASK    0x7800\n#define    RTL8367C_BUFFRST_INDSCOVER_THR_OFFSET    1\n#define    RTL8367C_BUFFRST_INDSCOVER_THR_MASK    0x7FE\n#define    RTL8367C_BUFFRST_INDSCOVER_EN_OFFSET    0\n#define    RTL8367C_BUFFRST_INDSCOVER_EN_MASK    0x1\n\n#define    RTL8367C_REG_BUFF_RST_CTRL5    0x1d69\n#define    RTL8367C_TX_ESD_MODE_OFFSET    8\n#define    RTL8367C_TX_ESD_MODE_MASK    0x100\n#define    RTL8367C_TX_ESD_LVL_OFFSET    0\n#define    RTL8367C_TX_ESD_LVL_MASK    0xFF\n\n#define    RTL8367C_REG_TOP_CON0    0x1d70\n#define    RTL8367C_TOP_CON0_SDS_PWR_ISO_1_OFFSET    15\n#define    RTL8367C_TOP_CON0_SDS_PWR_ISO_1_MASK    0x8000\n#define    RTL8367C_OCP_TIMEOUT_P7_5_OFFSET    12\n#define    RTL8367C_OCP_TIMEOUT_P7_5_MASK    0x7000\n#define    RTL8367C_FIB_EEE_AB_OFFSET    11\n#define    RTL8367C_FIB_EEE_AB_MASK    0x800\n#define    RTL8367C_ADCCKIEN_OFFSET    10\n#define    RTL8367C_ADCCKIEN_MASK    0x400\n#define    RTL8367C_OCP_TIMEOUT_OFFSET    5\n#define    RTL8367C_OCP_TIMEOUT_MASK    0x3E0\n#define    RTL8367C_TOP_CON0_SDS_PWR_ISO_OFFSET    4\n#define    RTL8367C_TOP_CON0_SDS_PWR_ISO_MASK    0x10\n#define    RTL8367C_RG2_TXC_SEL_OFFSET    3\n#define    RTL8367C_RG2_TXC_SEL_MASK    0x8\n#define    RTL8367C_RG1TXC_SEL_OFFSET    2\n#define    RTL8367C_RG1TXC_SEL_MASK    0x4\n#define    RTL8367C_SYNC_1588_EN_OFFSET    1\n#define    RTL8367C_SYNC_1588_EN_MASK    0x2\n#define    RTL8367C_LS_MODE_OFFSET    0\n#define    RTL8367C_LS_MODE_MASK    0x1\n\n#define    RTL8367C_REG_TOP_CON1    0x1d71\n#define    RTL8367C_TA_CHK_EN_OFFSET    2\n#define    RTL8367C_TA_CHK_EN_MASK    0x4\n#define    RTL8367C_SLV_EG_SEL_OFFSET    1\n#define    RTL8367C_SLV_EG_SEL_MASK    0x2\n#define    RTL8367C_IIC_OP_DRAIN_OFFSET    0\n#define    RTL8367C_IIC_OP_DRAIN_MASK    0x1\n\n#define    RTL8367C_REG_SWR_FPWM    0x1d72\n#define    RTL8367C_SWR_FPWM_OFFSET    0\n#define    RTL8367C_SWR_FPWM_MASK    0x1\n\n#define    RTL8367C_REG_EEEP_CTRL_500M    0x1d73\n\n#define    RTL8367C_REG_SHORT_PRMB    0x1d74\n#define    RTL8367C_SHORT_PRMB_OFFSET    0\n#define    RTL8367C_SHORT_PRMB_MASK    0x1\n\n#define    RTL8367C_REG_INDSC_THR_CTRL    0x1d75\n#define    RTL8367C_INDSC_THR_CTRL_OFFSET    0\n#define    RTL8367C_INDSC_THR_CTRL_MASK    0x7FF\n\n#define    RTL8367C_REG_SET_PAD_CTRL_NEW    0x1d80\n#define    RTL8367C_SET_PAD_CTRL_NEW_OFFSET    0\n#define    RTL8367C_SET_PAD_CTRL_NEW_MASK    0x1\n\n#define    RTL8367C_REG_SET_PAD_DRI_0    0x1d81\n\n#define    RTL8367C_REG_SET_PAD_DRI_1    0x1d82\n\n#define    RTL8367C_REG_SET_PAD_DRI_2    0x1d83\n\n#define    RTL8367C_REG_SET_PAD_SLEW_0    0x1d84\n\n#define    RTL8367C_REG_SET_PAD_SLEW_1    0x1d85\n\n#define    RTL8367C_REG_SET_PAD_SLEW_2    0x1d86\n\n#define    RTL8367C_REG_SET_PAD_SMT_0    0x1d87\n\n#define    RTL8367C_REG_SET_PAD_SMT_1    0x1d88\n\n#define    RTL8367C_REG_SET_PAD_SMT_2    0x1d89\n\n#define    RTL8367C_REG_M_I2C_CTL_STA_REG    0x1d8a\n#define    RTL8367C_TX_RX_DATA_OFFSET    8\n#define    RTL8367C_TX_RX_DATA_MASK    0xFF00\n#define    RTL8367C_DUMB_RW_ERR_OFFSET    7\n#define    RTL8367C_DUMB_RW_ERR_MASK    0x80\n#define    RTL8367C_SLV_ACK_FLAG_OFFSET    6\n#define    RTL8367C_SLV_ACK_FLAG_MASK    0x40\n#define    RTL8367C_M_I2C_BUS_IDLE_OFFSET    5\n#define    RTL8367C_M_I2C_BUS_IDLE_MASK    0x20\n#define    RTL8367C_I2C_CMD_TYPE_OFFSET    1\n#define    RTL8367C_I2C_CMD_TYPE_MASK    0x1E\n#define    RTL8367C_I2C_CMD_EXEC_OFFSET    0\n#define    RTL8367C_I2C_CMD_EXEC_MASK    0x1\n\n#define    RTL8367C_REG_M_I2C_DUMB_RW_ADDR_0    0x1d8b\n\n#define    RTL8367C_REG_M_I2C_DUMB_RW_ADDR_1    0x1d8c\n\n#define    RTL8367C_REG_M_I2C_DUMB_RW_DATA_0    0x1d8d\n\n#define    RTL8367C_REG_M_I2C_DUMB_RW_DATA_1    0x1d8e\n\n#define    RTL8367C_REG_M_I2C_DUMB_RW_CTL    0x1d8f\n#define    RTL8367C_DUMB_I2C_CTL_CODE_OFFSET    8\n#define    RTL8367C_DUMB_I2C_CTL_CODE_MASK    0x7F00\n#define    RTL8367C_DUMB_RW_I2C_FORMAT_OFFSET    4\n#define    RTL8367C_DUMB_RW_I2C_FORMAT_MASK    0x10\n#define    RTL8367C_DUMB_RW_DATA_MODE_OFFSET    2\n#define    RTL8367C_DUMB_RW_DATA_MODE_MASK    0xC\n#define    RTL8367C_DUMB_RW_ADDR_MODE_OFFSET    0\n#define    RTL8367C_DUMB_RW_ADDR_MODE_MASK    0x3\n\n#define    RTL8367C_REG_M_I2C_SYS_CTL    0x1d90\n#define    RTL8367C_M_I2C_SCL_IO_MUX_OFFSET    12\n#define    RTL8367C_M_I2C_SCL_IO_MUX_MASK    0x3000\n#define    RTL8367C_M_I2C_SDA_IO_MUX_OFFSET    10\n#define    RTL8367C_M_I2C_SDA_IO_MUX_MASK    0xC00\n#define    RTL8367C_M_I2C_SDA_OD_EN_OFFSET    9\n#define    RTL8367C_M_I2C_SDA_OD_EN_MASK    0x200\n#define    RTL8367C_M_I2C_SCL_OD_EN_OFFSET    8\n#define    RTL8367C_M_I2C_SCL_OD_EN_MASK    0x100\n#define    RTL8367C_M_I2C_SCL_F_DIV_OFFSET    0\n#define    RTL8367C_M_I2C_SCL_F_DIV_MASK    0xFF\n\n#define    RTL8367C_REG_HT_PB_SRAM_CTRL    0x1da0\n#define    RTL8367C_HTPB_RW_OFFSET    2\n#define    RTL8367C_HTPB_RW_MASK    0x4\n#define    RTL8367C_HTPB_SEL_OFFSET    1\n#define    RTL8367C_HTPB_SEL_MASK    0x2\n#define    RTL8367C_HTPB_CE_OFFSET    0\n#define    RTL8367C_HTPB_CE_MASK    0x1\n\n#define    RTL8367C_REG_HT_PB_SRAM_ADDR    0x1da1\n\n#define    RTL8367C_REG_HT_PB_SRAM_DIN0    0x1da2\n\n#define    RTL8367C_REG_HT_PB_SRAM_DIN1    0x1da3\n\n#define    RTL8367C_REG_HT_PB_SRAM_DOUT0    0x1da4\n\n#define    RTL8367C_REG_HT_PB_SRAM_DOUT1    0x1da5\n\n#define    RTL8367C_REG_PHY_STAT_0    0x1db0\n\n#define    RTL8367C_REG_PHY_STAT_1    0x1db1\n\n#define    RTL8367C_REG_PHY_STAT_2    0x1db2\n\n#define    RTL8367C_REG_PHY_STAT_3    0x1db3\n\n#define    RTL8367C_REG_PHY_STAT_4    0x1db4\n\n#define    RTL8367C_REG_PHY_STAT_5    0x1db5\n\n#define    RTL8367C_REG_PHY_STAT_6    0x1db6\n\n#define    RTL8367C_REG_PHY_STAT_7    0x1db7\n\n#define    RTL8367C_REG_SDS_STAT_0    0x1db8\n\n#define    RTL8367C_REG_SDS_STAT_1    0x1db9\n\n#define    RTL8367C_REG_MAC_LINK_STAT_0    0x1dba\n#define    RTL8367C_MAC_LINK_STAT_CUR_0_OFFSET    8\n#define    RTL8367C_MAC_LINK_STAT_CUR_0_MASK    0xFF00\n#define    RTL8367C_MAC_LINK_STAT_LATCH_0_OFFSET    0\n#define    RTL8367C_MAC_LINK_STAT_LATCH_0_MASK    0xFF\n\n#define    RTL8367C_REG_MAC_LINK_STAT_1    0x1dbb\n#define    RTL8367C_MAC_LINK_STAT_1_Reserved_OFFSET    6\n#define    RTL8367C_MAC_LINK_STAT_1_Reserved_MASK    0xFFC0\n#define    RTL8367C_MAC_LINK_STAT_CUR_1_OFFSET    3\n#define    RTL8367C_MAC_LINK_STAT_CUR_1_MASK    0x38\n#define    RTL8367C_MAC_LINK_STAT_LATCH_1_OFFSET    0\n#define    RTL8367C_MAC_LINK_STAT_LATCH_1_MASK    0x7\n\n#define    RTL8367C_REG_MISC_CONTROL_1    0x1dc0\n#define    RTL8367C_P7_FB_CPL_OFFSET    2\n#define    RTL8367C_P7_FB_CPL_MASK    0x4\n#define    RTL8367C_P6_FB_CPL_OFFSET    1\n#define    RTL8367C_P6_FB_CPL_MASK    0x2\n#define    RTL8367C_P5_FB_CPL_OFFSET    0\n#define    RTL8367C_P5_FB_CPL_MASK    0x1\n\n#define    RTL8367C_REG_SDS_MISC_1    0x1dc1\n#define    RTL8367C_CFG_SGMII_RXFC_1_OFFSET    14\n#define    RTL8367C_CFG_SGMII_RXFC_1_MASK    0x4000\n#define    RTL8367C_CFG_SGMII_TXFC_1_OFFSET    13\n#define    RTL8367C_CFG_SGMII_TXFC_1_MASK    0x2000\n#define    RTL8367C_CFG_MAC9_SEL_HSGMII_OFFSET    11\n#define    RTL8367C_CFG_MAC9_SEL_HSGMII_MASK    0x800\n#define    RTL8367C_CFG_SGMII_FDUP_1_OFFSET    10\n#define    RTL8367C_CFG_SGMII_FDUP_1_MASK    0x400\n#define    RTL8367C_CFG_SGMII_LINK_1_OFFSET    9\n#define    RTL8367C_CFG_SGMII_LINK_1_MASK    0x200\n#define    RTL8367C_CFG_SGMII_SPD_1_OFFSET    7\n#define    RTL8367C_CFG_SGMII_SPD_1_MASK    0x180\n#define    RTL8367C_CFG_MAC9_SEL_SGMII_OFFSET    6\n#define    RTL8367C_CFG_MAC9_SEL_SGMII_MASK    0x40\n#define    RTL8367C_CFG_SDS_MODE_14C_1_OFFSET    0\n#define    RTL8367C_CFG_SDS_MODE_14C_1_MASK    0x7\n\n#define    RTL8367C_REG_FIBER_CFG_2_1    0x1dc2\n#define    RTL8367C_SDS_RX_DISABLE_1_OFFSET    6\n#define    RTL8367C_SDS_RX_DISABLE_1_MASK    0xC0\n#define    RTL8367C_SDS_TX_DISABLE_1_OFFSET    4\n#define    RTL8367C_SDS_TX_DISABLE_1_MASK    0x30\n#define    RTL8367C_FIBER_CFG_2_1_SDS_PWR_ISO_1_OFFSET    2\n#define    RTL8367C_FIBER_CFG_2_1_SDS_PWR_ISO_1_MASK    0xC\n#define    RTL8367C_SDS_FRC_LD_1_OFFSET    0\n#define    RTL8367C_SDS_FRC_LD_1_MASK    0x3\n\n#define    RTL8367C_REG_FIBER_CFG_1_1    0x1dc3\n#define    RTL8367C_SDS_FRC_REG4_1_OFFSET    12\n#define    RTL8367C_SDS_FRC_REG4_1_MASK    0x1000\n#define    RTL8367C_SDS_FRC_REG4_FIB100_1_OFFSET    11\n#define    RTL8367C_SDS_FRC_REG4_FIB100_1_MASK    0x800\n#define    RTL8367C_SDS_FRC_MODE_1_OFFSET    3\n#define    RTL8367C_SDS_FRC_MODE_1_MASK    0x8\n#define    RTL8367C_SDS_MODE_1_OFFSET    0\n#define    RTL8367C_SDS_MODE_1_MASK    0x7\n\n#define    RTL8367C_REG_PHYSTS_CTRL0_1    0x1dc4\n#define    RTL8367C_LNKUP_DLY_EN_EXT2_OFFSET    9\n#define    RTL8367C_LNKUP_DLY_EN_EXT2_MASK    0x200\n#define    RTL8367C_GE_100M_LNKUP_DLY_EXT2_OFFSET    7\n#define    RTL8367C_GE_100M_LNKUP_DLY_EXT2_MASK    0x180\n#define    RTL8367C_PHYSTS_10M_LNKUP_DLY_EXT2_OFFSET    5\n#define    RTL8367C_PHYSTS_10M_LNKUP_DLY_EXT2_MASK    0x60\n#define    RTL8367C_LNKUP_DLY_EN_EXT1_OFFSET    4\n#define    RTL8367C_LNKUP_DLY_EN_EXT1_MASK    0x10\n#define    RTL8367C_GE_100M_LNKUP_DLY_EXT1_OFFSET    2\n#define    RTL8367C_GE_100M_LNKUP_DLY_EXT1_MASK    0xC\n#define    RTL8367C_PHYSTS_10M_LNKUP_DLY_EXT1_OFFSET    0\n#define    RTL8367C_PHYSTS_10M_LNKUP_DLY_EXT1_MASK    0x3\n\n#define    RTL8367C_REG_FIBER_CFG_3_1    0x1dc5\n#define    RTL8367C_FIBER_CFG_3_1_OFFSET    0\n#define    RTL8367C_FIBER_CFG_3_1_MASK    0xFFF\n\n#define    RTL8367C_REG_FIBER_CFG_4_1    0x1dc6\n\n#define    RTL8367C_REG_BUFF_RST_CTRL2_2    0x1dc7\n#define    RTL8367C_Cfg_buffrst_sysover_thr_1_OFFSET    3\n#define    RTL8367C_Cfg_buffrst_sysover_thr_1_MASK    0x8\n#define    RTL8367C_Cfg_buffrst_qover_thr_OFFSET    2\n#define    RTL8367C_Cfg_buffrst_qover_thr_MASK    0x4\n#define    RTL8367C_Cfg_buffrst_indscover_thr_1_OFFSET    1\n#define    RTL8367C_Cfg_buffrst_indscover_thr_1_MASK    0x2\n#define    RTL8367C_Cfg_buffrst_dscover_thr_1_OFFSET    0\n#define    RTL8367C_Cfg_buffrst_dscover_thr_1_MASK    0x1\n\n#define    RTL8367C_REG_PHY_DEBUG_CNT_CTRL    0x1dc8\n#define    RTL8367C_PHY_MIB_RST_7_OFFSET    15\n#define    RTL8367C_PHY_MIB_RST_7_MASK    0x8000\n#define    RTL8367C_PHY_MIB_RST_6_OFFSET    14\n#define    RTL8367C_PHY_MIB_RST_6_MASK    0x4000\n#define    RTL8367C_PHY_MIB_RST_5_OFFSET    13\n#define    RTL8367C_PHY_MIB_RST_5_MASK    0x2000\n#define    RTL8367C_PHY_MIB_RST_4_OFFSET    12\n#define    RTL8367C_PHY_MIB_RST_4_MASK    0x1000\n#define    RTL8367C_PHY_MIB_RST_3_OFFSET    11\n#define    RTL8367C_PHY_MIB_RST_3_MASK    0x800\n#define    RTL8367C_PHY_MIB_RST_2_OFFSET    10\n#define    RTL8367C_PHY_MIB_RST_2_MASK    0x400\n#define    RTL8367C_PHY_MIB_RST_1_OFFSET    9\n#define    RTL8367C_PHY_MIB_RST_1_MASK    0x200\n#define    RTL8367C_PHY_MIB_RST_0_OFFSET    8\n#define    RTL8367C_PHY_MIB_RST_0_MASK    0x100\n#define    RTL8367C_PHY_MIB_EN_7_OFFSET    7\n#define    RTL8367C_PHY_MIB_EN_7_MASK    0x80\n#define    RTL8367C_PHY_MIB_EN_6_OFFSET    6\n#define    RTL8367C_PHY_MIB_EN_6_MASK    0x40\n#define    RTL8367C_PHY_MIB_EN_5_OFFSET    5\n#define    RTL8367C_PHY_MIB_EN_5_MASK    0x20\n#define    RTL8367C_PHY_MIB_EN_4_OFFSET    4\n#define    RTL8367C_PHY_MIB_EN_4_MASK    0x10\n#define    RTL8367C_PHY_MIB_EN_3_OFFSET    3\n#define    RTL8367C_PHY_MIB_EN_3_MASK    0x8\n#define    RTL8367C_PHY_MIB_EN_2_OFFSET    2\n#define    RTL8367C_PHY_MIB_EN_2_MASK    0x4\n#define    RTL8367C_PHY_MIB_EN_1_OFFSET    1\n#define    RTL8367C_PHY_MIB_EN_1_MASK    0x2\n#define    RTL8367C_PHY_MIB_EN_0_OFFSET    0\n#define    RTL8367C_PHY_MIB_EN_0_MASK    0x1\n\n#define    RTL8367C_REG_TXPKT_CNT_L_0    0x1dc9\n\n#define    RTL8367C_REG_TXPKT_CNT_H_0    0x1dca\n\n#define    RTL8367C_REG_RXPKT_CNT_L_0    0x1dcb\n\n#define    RTL8367C_REG_RXPKT_CNT_H_0    0x1dcc\n\n#define    RTL8367C_REG_TX_CRC_0    0x1dcd\n\n#define    RTL8367C_REG_RX_CRC_0    0x1dce\n\n#define    RTL8367C_REG_TXPKT_CNT_L_1    0x1dcf\n\n#define    RTL8367C_REG_TXPKT_CNT_H_1    0x1dd0\n\n#define    RTL8367C_REG_RXPKT_CNT_L_1    0x1dd1\n\n#define    RTL8367C_REG_RXPKT_CNT_H_1    0x1dd2\n\n#define    RTL8367C_REG_TX_CRC_1    0x1dd3\n\n#define    RTL8367C_REG_RX_CRC_1    0x1dd4\n\n#define    RTL8367C_REG_TXPKT_CNT_L_2    0x1dd5\n\n#define    RTL8367C_REG_TXPKT_CNT_H_2    0x1dd6\n\n#define    RTL8367C_REG_RXPKT_CNT_L_2    0x1dd7\n\n#define    RTL8367C_REG_RXPKT_CNT_H_2    0x1dd8\n\n#define    RTL8367C_REG_TX_CRC_2    0x1dd9\n\n#define    RTL8367C_REG_RX_CRC_2    0x1dda\n\n#define    RTL8367C_REG_TXPKT_CNT_L_3    0x1ddb\n\n#define    RTL8367C_REG_TXPKT_CNT_H_3    0x1ddc\n\n#define    RTL8367C_REG_RXPKT_CNT_L_3    0x1ddd\n\n#define    RTL8367C_REG_RXPKT_CNT_H_3    0x1dde\n\n#define    RTL8367C_REG_TX_CRC_3    0x1ddf\n\n#define    RTL8367C_REG_RX_CRC_3    0x1de0\n\n#define    RTL8367C_REG_TXPKT_CNT_L_4    0x1de1\n\n#define    RTL8367C_REG_TXPKT_CNT_H_4    0x1de2\n\n#define    RTL8367C_REG_RXPKT_CNT_L_4    0x1de3\n\n#define    RTL8367C_REG_RXPKT_CNT_H_4    0x1de4\n\n#define    RTL8367C_REG_TX_CRC_4    0x1de5\n\n#define    RTL8367C_REG_RX_CRC_4    0x1de6\n\n#define    RTL8367C_REG_TXPKT_CNT_L_5    0x1de7\n\n#define    RTL8367C_REG_TXPKT_CNT_H_5    0x1de8\n\n#define    RTL8367C_REG_RXPKT_CNT_L_5    0x1de9\n\n#define    RTL8367C_REG_RXPKT_CNT_H_5    0x1dea\n\n#define    RTL8367C_REG_TX_CRC_5    0x1deb\n\n#define    RTL8367C_REG_RX_CRC_5    0x1dec\n\n#define    RTL8367C_REG_TXPKT_CNT_L_6    0x1ded\n\n#define    RTL8367C_REG_TXPKT_CNT_H_6    0x1dee\n\n#define    RTL8367C_REG_RXPKT_CNT_L_6    0x1def\n\n#define    RTL8367C_REG_RXPKT_CNT_H_6    0x1df0\n\n#define    RTL8367C_REG_TX_CRC_6    0x1df1\n\n#define    RTL8367C_REG_RX_CRC_6    0x1df2\n\n#define    RTL8367C_REG_TXPKT_CNT_L_7    0x1df3\n\n#define    RTL8367C_REG_TXPKT_CNT_H_7    0x1df4\n\n#define    RTL8367C_REG_RXPKT_CNT_L_7    0x1df5\n\n#define    RTL8367C_REG_RXPKT_CNT_H_7    0x1df6\n\n#define    RTL8367C_REG_TX_CRC_7    0x1df7\n\n#define    RTL8367C_REG_RX_CRC_7    0x1df8\n\n#define    RTL8367C_REG_BOND_DBG_0    0x1df9\n\n#define    RTL8367C_REG_BOND_DBG_1    0x1dfa\n\n#define    RTL8367C_REG_STRP_DBG_0    0x1dfb\n\n#define    RTL8367C_REG_STRP_DBG_1    0x1dfc\n\n#define    RTL8367C_REG_STRP_DBG_2    0x1dfd\n\n/* (16'h1f00)patch_reg */\n\n#define    RTL8367C_REG_INDRECT_ACCESS_CTRL    0x1f00\n#define    RTL8367C_RW_OFFSET    1\n#define    RTL8367C_RW_MASK    0x2\n#define    RTL8367C_CMD_OFFSET    0\n#define    RTL8367C_CMD_MASK    0x1\n\n#define    RTL8367C_REG_INDRECT_ACCESS_STATUS    0x1f01\n#define    RTL8367C_INDRECT_ACCESS_STATUS_OFFSET    2\n#define    RTL8367C_INDRECT_ACCESS_STATUS_MASK    0x7\n\n#define    RTL8367C_REG_INDRECT_ACCESS_ADDRESS    0x1f02\n\n#define    RTL8367C_REG_INDRECT_ACCESS_WRITE_DATA    0x1f03\n\n#define    RTL8367C_REG_INDRECT_ACCESS_READ_DATA    0x1f04\n\n/* (16'h6200)fib_page */\n\n#define    RTL8367C_REG_FIB0_CFG00    0x6200\n#define    RTL8367C_FIB0_CFG00_CFG_FIB_RST_OFFSET    15\n#define    RTL8367C_FIB0_CFG00_CFG_FIB_RST_MASK    0x8000\n#define    RTL8367C_FIB0_CFG00_CFG_FIB_LPK_OFFSET    14\n#define    RTL8367C_FIB0_CFG00_CFG_FIB_LPK_MASK    0x4000\n#define    RTL8367C_FIB0_CFG00_CFG_FIB_SPD_RD_0_OFFSET    13\n#define    RTL8367C_FIB0_CFG00_CFG_FIB_SPD_RD_0_MASK    0x2000\n#define    RTL8367C_FIB0_CFG00_CFG_FIB_ANEN_OFFSET    12\n#define    RTL8367C_FIB0_CFG00_CFG_FIB_ANEN_MASK    0x1000\n#define    RTL8367C_FIB0_CFG00_CFG_FIB_PDOWN_OFFSET    11\n#define    RTL8367C_FIB0_CFG00_CFG_FIB_PDOWN_MASK    0x800\n#define    RTL8367C_FIB0_CFG00_CFG_FIB_ISO_OFFSET    10\n#define    RTL8367C_FIB0_CFG00_CFG_FIB_ISO_MASK    0x400\n#define    RTL8367C_FIB0_CFG00_CFG_FIB_RESTART_OFFSET    9\n#define    RTL8367C_FIB0_CFG00_CFG_FIB_RESTART_MASK    0x200\n#define    RTL8367C_FIB0_CFG00_CFG_FIB_FULLDUP_OFFSET    8\n#define    RTL8367C_FIB0_CFG00_CFG_FIB_FULLDUP_MASK    0x100\n#define    RTL8367C_FIB0_CFG00_CFG_FIB_SPD_RD_1_OFFSET    6\n#define    RTL8367C_FIB0_CFG00_CFG_FIB_SPD_RD_1_MASK    0x40\n#define    RTL8367C_FIB0_CFG00_CFG_FIB_FRCTX_OFFSET    5\n#define    RTL8367C_FIB0_CFG00_CFG_FIB_FRCTX_MASK    0x20\n\n#define    RTL8367C_REG_FIB0_CFG01    0x6201\n#define    RTL8367C_FIB0_CFG01_CAPBILITY_OFFSET    6\n#define    RTL8367C_FIB0_CFG01_CAPBILITY_MASK    0xFFC0\n#define    RTL8367C_FIB0_CFG01_AN_COMPLETE_OFFSET    5\n#define    RTL8367C_FIB0_CFG01_AN_COMPLETE_MASK    0x20\n#define    RTL8367C_FIB0_CFG01_R_FAULT_OFFSET    4\n#define    RTL8367C_FIB0_CFG01_R_FAULT_MASK    0x10\n#define    RTL8367C_FIB0_CFG01_NWAY_ABILITY_OFFSET    3\n#define    RTL8367C_FIB0_CFG01_NWAY_ABILITY_MASK    0x8\n#define    RTL8367C_FIB0_CFG01_LINK_STATUS_OFFSET    2\n#define    RTL8367C_FIB0_CFG01_LINK_STATUS_MASK    0x4\n#define    RTL8367C_FIB0_CFG01_JABBER_DETECT_OFFSET    1\n#define    RTL8367C_FIB0_CFG01_JABBER_DETECT_MASK    0x2\n#define    RTL8367C_FIB0_CFG01_EXTENDED_CAPBILITY_OFFSET    0\n#define    RTL8367C_FIB0_CFG01_EXTENDED_CAPBILITY_MASK    0x1\n\n#define    RTL8367C_REG_FIB0_CFG02    0x6202\n\n#define    RTL8367C_REG_FIB0_CFG03    0x6203\n#define    RTL8367C_FIB0_CFG03_REALTEK_OUI5_0_OFFSET    10\n#define    RTL8367C_FIB0_CFG03_REALTEK_OUI5_0_MASK    0xFC00\n#define    RTL8367C_FIB0_CFG03_MODEL_NO_OFFSET    4\n#define    RTL8367C_FIB0_CFG03_MODEL_NO_MASK    0x3F0\n#define    RTL8367C_FIB0_CFG03_REVISION_NO_OFFSET    0\n#define    RTL8367C_FIB0_CFG03_REVISION_NO_MASK    0xF\n\n#define    RTL8367C_REG_FIB0_CFG04    0x6204\n\n#define    RTL8367C_REG_FIB0_CFG05    0x6205\n\n#define    RTL8367C_REG_FIB0_CFG06    0x6206\n#define    RTL8367C_FIB0_CFG06_FIB_NP_EN_OFFSET    2\n#define    RTL8367C_FIB0_CFG06_FIB_NP_EN_MASK    0x4\n#define    RTL8367C_FIB0_CFG06_RXPAGE_OFFSET    1\n#define    RTL8367C_FIB0_CFG06_RXPAGE_MASK    0x2\n\n#define    RTL8367C_REG_FIB0_CFG07    0x6207\n\n#define    RTL8367C_REG_FIB0_CFG08    0x6208\n\n#define    RTL8367C_REG_FIB0_CFG09    0x6209\n\n#define    RTL8367C_REG_FIB0_CFG10    0x620a\n\n#define    RTL8367C_REG_FIB0_CFG11    0x620b\n\n#define    RTL8367C_REG_FIB0_CFG12    0x620c\n\n#define    RTL8367C_REG_FIB0_CFG13    0x620d\n#define    RTL8367C_FIB0_CFG13_INDR_FUNC_OFFSET    14\n#define    RTL8367C_FIB0_CFG13_INDR_FUNC_MASK    0xC000\n#define    RTL8367C_FIB0_CFG13_DUMMY_OFFSET    5\n#define    RTL8367C_FIB0_CFG13_DUMMY_MASK    0x3FE0\n#define    RTL8367C_FIB0_CFG13_INDR_DEVAD_OFFSET    0\n#define    RTL8367C_FIB0_CFG13_INDR_DEVAD_MASK    0x1F\n\n#define    RTL8367C_REG_FIB0_CFG14    0x620e\n\n#define    RTL8367C_REG_FIB0_CFG15    0x620f\n\n#define    RTL8367C_REG_FIB1_CFG00    0x6210\n#define    RTL8367C_FIB1_CFG00_CFG_FIB_RST_OFFSET    15\n#define    RTL8367C_FIB1_CFG00_CFG_FIB_RST_MASK    0x8000\n#define    RTL8367C_FIB1_CFG00_CFG_FIB_LPK_OFFSET    14\n#define    RTL8367C_FIB1_CFG00_CFG_FIB_LPK_MASK    0x4000\n#define    RTL8367C_FIB1_CFG00_CFG_FIB_SPD_RD_0_OFFSET    13\n#define    RTL8367C_FIB1_CFG00_CFG_FIB_SPD_RD_0_MASK    0x2000\n#define    RTL8367C_FIB1_CFG00_CFG_FIB_ANEN_OFFSET    12\n#define    RTL8367C_FIB1_CFG00_CFG_FIB_ANEN_MASK    0x1000\n#define    RTL8367C_FIB1_CFG00_CFG_FIB_PDOWN_OFFSET    11\n#define    RTL8367C_FIB1_CFG00_CFG_FIB_PDOWN_MASK    0x800\n#define    RTL8367C_FIB1_CFG00_CFG_FIB_ISO_OFFSET    10\n#define    RTL8367C_FIB1_CFG00_CFG_FIB_ISO_MASK    0x400\n#define    RTL8367C_FIB1_CFG00_CFG_FIB_RESTART_OFFSET    9\n#define    RTL8367C_FIB1_CFG00_CFG_FIB_RESTART_MASK    0x200\n#define    RTL8367C_FIB1_CFG00_CFG_FIB_FULLDUP_OFFSET    8\n#define    RTL8367C_FIB1_CFG00_CFG_FIB_FULLDUP_MASK    0x100\n#define    RTL8367C_FIB1_CFG00_CFG_FIB_SPD_RD_1_OFFSET    6\n#define    RTL8367C_FIB1_CFG00_CFG_FIB_SPD_RD_1_MASK    0x40\n#define    RTL8367C_FIB1_CFG00_CFG_FIB_FRCTX_OFFSET    5\n#define    RTL8367C_FIB1_CFG00_CFG_FIB_FRCTX_MASK    0x20\n\n#define    RTL8367C_REG_FIB1_CFG01    0x6211\n#define    RTL8367C_FIB1_CFG01_CAPBILITY_OFFSET    6\n#define    RTL8367C_FIB1_CFG01_CAPBILITY_MASK    0xFFC0\n#define    RTL8367C_FIB1_CFG01_AN_COMPLETE_OFFSET    5\n#define    RTL8367C_FIB1_CFG01_AN_COMPLETE_MASK    0x20\n#define    RTL8367C_FIB1_CFG01_R_FAULT_OFFSET    4\n#define    RTL8367C_FIB1_CFG01_R_FAULT_MASK    0x10\n#define    RTL8367C_FIB1_CFG01_NWAY_ABILITY_OFFSET    3\n#define    RTL8367C_FIB1_CFG01_NWAY_ABILITY_MASK    0x8\n#define    RTL8367C_FIB1_CFG01_LINK_STATUS_OFFSET    2\n#define    RTL8367C_FIB1_CFG01_LINK_STATUS_MASK    0x4\n#define    RTL8367C_FIB1_CFG01_JABBER_DETECT_OFFSET    1\n#define    RTL8367C_FIB1_CFG01_JABBER_DETECT_MASK    0x2\n#define    RTL8367C_FIB1_CFG01_EXTENDED_CAPBILITY_OFFSET    0\n#define    RTL8367C_FIB1_CFG01_EXTENDED_CAPBILITY_MASK    0x1\n\n#define    RTL8367C_REG_FIB1_CFG02    0x6212\n\n#define    RTL8367C_REG_FIB1_CFG03    0x6213\n#define    RTL8367C_FIB1_CFG03_REALTEK_OUI5_0_OFFSET    10\n#define    RTL8367C_FIB1_CFG03_REALTEK_OUI5_0_MASK    0xFC00\n#define    RTL8367C_FIB1_CFG03_MODEL_NO_OFFSET    4\n#define    RTL8367C_FIB1_CFG03_MODEL_NO_MASK    0x3F0\n#define    RTL8367C_FIB1_CFG03_REVISION_NO_OFFSET    0\n#define    RTL8367C_FIB1_CFG03_REVISION_NO_MASK    0xF\n\n#define    RTL8367C_REG_FIB1_CFG04    0x6214\n\n#define    RTL8367C_REG_FIB1_CFG05    0x6215\n\n#define    RTL8367C_REG_FIB1_CFG06    0x6216\n#define    RTL8367C_FIB1_CFG06_FIB_NP_EN_OFFSET    2\n#define    RTL8367C_FIB1_CFG06_FIB_NP_EN_MASK    0x4\n#define    RTL8367C_FIB1_CFG06_RXPAGE_OFFSET    1\n#define    RTL8367C_FIB1_CFG06_RXPAGE_MASK    0x2\n\n#define    RTL8367C_REG_FIB1_CFG07    0x6217\n\n#define    RTL8367C_REG_FIB1_CFG08    0x6218\n\n#define    RTL8367C_REG_FIB1_CFG09    0x6219\n\n#define    RTL8367C_REG_FIB1_CFG10    0x621a\n\n#define    RTL8367C_REG_FIB1_CFG11    0x621b\n\n#define    RTL8367C_REG_FIB1_CFG12    0x621c\n\n#define    RTL8367C_REG_FIB1_CFG13    0x621d\n#define    RTL8367C_FIB1_CFG13_INDR_FUNC_OFFSET    14\n#define    RTL8367C_FIB1_CFG13_INDR_FUNC_MASK    0xC000\n#define    RTL8367C_FIB1_CFG13_DUMMY_OFFSET    5\n#define    RTL8367C_FIB1_CFG13_DUMMY_MASK    0x3FE0\n#define    RTL8367C_FIB1_CFG13_INDR_DEVAD_OFFSET    0\n#define    RTL8367C_FIB1_CFG13_INDR_DEVAD_MASK    0x1F\n\n#define    RTL8367C_REG_FIB1_CFG14    0x621e\n\n#define    RTL8367C_REG_FIB1_CFG15    0x621f\n\n/* (16'h6400)timer_1588 */\n\n#define    RTL8367C_REG_PTP_TIME_NSEC_L_NSEC    0x6400\n\n#define    RTL8367C_REG_PTP_TIME_NSEC_H_NSEC    0x6401\n#define    RTL8367C_PTP_TIME_NSEC_H_EXEC_OFFSET    15\n#define    RTL8367C_PTP_TIME_NSEC_H_EXEC_MASK    0x8000\n#define    RTL8367C_PTP_TIME_NSEC_H_CMD_OFFSET    12\n#define    RTL8367C_PTP_TIME_NSEC_H_CMD_MASK    0x3000\n#define    RTL8367C_PTP_TIME_NSEC_H_NSEC_OFFSET    0\n#define    RTL8367C_PTP_TIME_NSEC_H_NSEC_MASK    0x7FF\n\n#define    RTL8367C_REG_PTP_TIME_SEC_L_SEC    0x6402\n\n#define    RTL8367C_REG_PTP_TIME_SEC_H_SEC    0x6403\n\n#define    RTL8367C_REG_PTP_TIME_CFG    0x6404\n#define    RTL8367C_CFG_TIMER_EN_FRC_OFFSET    2\n#define    RTL8367C_CFG_TIMER_EN_FRC_MASK    0x4\n#define    RTL8367C_CFG_TIMER_1588_EN_OFFSET    1\n#define    RTL8367C_CFG_TIMER_1588_EN_MASK    0x2\n#define    RTL8367C_CFG_CLK_SRC_OFFSET    0\n#define    RTL8367C_CFG_CLK_SRC_MASK    0x1\n\n#define    RTL8367C_REG_OTAG_TPID    0x6405\n\n#define    RTL8367C_REG_ITAG_TPID    0x6406\n\n#define    RTL8367C_REG_MAC_ADDR_L    0x6407\n\n#define    RTL8367C_REG_MAC_ADDR_M    0x6408\n\n#define    RTL8367C_REG_MAC_ADDR_H    0x6409\n\n#define    RTL8367C_REG_PTP_TIME_NSEC_L_NSEC_RD    0x640a\n\n#define    RTL8367C_REG_PTP_TIME_NSEC_H_NSEC_RD    0x640b\n#define    RTL8367C_PTP_TIME_NSEC_H_NSEC_RD_OFFSET    0\n#define    RTL8367C_PTP_TIME_NSEC_H_NSEC_RD_MASK    0x7FF\n\n#define    RTL8367C_REG_PTP_TIME_SEC_L_SEC_RD    0x640c\n\n#define    RTL8367C_REG_PTP_TIME_SEC_H_SEC_RD    0x640d\n\n#define    RTL8367C_REG_PTP_TIME_CFG2    0x640e\n#define    RTL8367C_CFG_EN_OFFLOAD_OFFSET    9\n#define    RTL8367C_CFG_EN_OFFLOAD_MASK    0x200\n#define    RTL8367C_CFG_SAVE_OFF_TS_OFFSET    8\n#define    RTL8367C_CFG_SAVE_OFF_TS_MASK    0x100\n#define    RTL8367C_CFG_IMR_OFFSET    0\n#define    RTL8367C_CFG_IMR_MASK    0xFF\n\n#define    RTL8367C_REG_PTP_INTERRUPT_CFG    0x640f\n#define    RTL8367C_P9_INTERRUPT_OFFSET    9\n#define    RTL8367C_P9_INTERRUPT_MASK    0x200\n#define    RTL8367C_P8_INTERRUPT_OFFSET    8\n#define    RTL8367C_P8_INTERRUPT_MASK    0x100\n#define    RTL8367C_P7_INTERRUPT_OFFSET    7\n#define    RTL8367C_P7_INTERRUPT_MASK    0x80\n#define    RTL8367C_P6_INTERRUPT_OFFSET    6\n#define    RTL8367C_P6_INTERRUPT_MASK    0x40\n#define    RTL8367C_P5_INTERRUPT_OFFSET    5\n#define    RTL8367C_P5_INTERRUPT_MASK    0x20\n#define    RTL8367C_P4_INTERRUPT_OFFSET    4\n#define    RTL8367C_P4_INTERRUPT_MASK    0x10\n#define    RTL8367C_P3_INTERRUPT_OFFSET    3\n#define    RTL8367C_P3_INTERRUPT_MASK    0x8\n#define    RTL8367C_P2_INTERRUPT_OFFSET    2\n#define    RTL8367C_P2_INTERRUPT_MASK    0x4\n#define    RTL8367C_P1_INTERRUPT_OFFSET    1\n#define    RTL8367C_P1_INTERRUPT_MASK    0x2\n#define    RTL8367C_P0_INTERRUPT_OFFSET    0\n#define    RTL8367C_P0_INTERRUPT_MASK    0x1\n\n#define    RTL8367C_REG_P0_TX_SYNC_SEQ_ID    0x6410\n\n#define    RTL8367C_REG_P0_TX_DELAY_REQ_SEQ_ID    0x6411\n\n#define    RTL8367C_REG_P0_TX_PDELAY_REQ_SEQ_ID    0x6412\n\n#define    RTL8367C_REG_P0_TX_PDELAY_RESP_SEQ_ID    0x6413\n\n#define    RTL8367C_REG_P0_RX_SYNC_SEQ_ID    0x6414\n\n#define    RTL8367C_REG_P0_RX_DELAY_REQ_SEQ_ID    0x6415\n\n#define    RTL8367C_REG_P0_RX_PDELAY_REQ_SEQ_ID    0x6416\n\n#define    RTL8367C_REG_P0_RX_PDELAY_RESP_SEQ_ID    0x6417\n\n#define    RTL8367C_REG_P0_PORT_NSEC_15_0    0x6418\n\n#define    RTL8367C_REG_P0_PORT_NSEC_26_16    0x6419\n#define    RTL8367C_P0_PORT_NSEC_26_16_OFFSET    0\n#define    RTL8367C_P0_PORT_NSEC_26_16_MASK    0x7FF\n\n#define    RTL8367C_REG_P0_PORT_SEC_15_0    0x641a\n\n#define    RTL8367C_REG_P0_PORT_SEC_31_16    0x641b\n\n#define    RTL8367C_REG_P0_EAV_CFG    0x641c\n#define    RTL8367C_P0_EAV_CFG_PTP_PHY_EN_EN_OFFSET    8\n#define    RTL8367C_P0_EAV_CFG_PTP_PHY_EN_EN_MASK    0x100\n#define    RTL8367C_P0_EAV_CFG_RX_PDELAY_RESP_OFFSET    7\n#define    RTL8367C_P0_EAV_CFG_RX_PDELAY_RESP_MASK    0x80\n#define    RTL8367C_P0_EAV_CFG_RX_PDELAY_REQ_OFFSET    6\n#define    RTL8367C_P0_EAV_CFG_RX_PDELAY_REQ_MASK    0x40\n#define    RTL8367C_P0_EAV_CFG_RX_DELAY_REQ_OFFSET    5\n#define    RTL8367C_P0_EAV_CFG_RX_DELAY_REQ_MASK    0x20\n#define    RTL8367C_P0_EAV_CFG_RX_SYNC_OFFSET    4\n#define    RTL8367C_P0_EAV_CFG_RX_SYNC_MASK    0x10\n#define    RTL8367C_P0_EAV_CFG_TX_PDELAY_RESP_OFFSET    3\n#define    RTL8367C_P0_EAV_CFG_TX_PDELAY_RESP_MASK    0x8\n#define    RTL8367C_P0_EAV_CFG_TX_PDELAY_REQ_OFFSET    2\n#define    RTL8367C_P0_EAV_CFG_TX_PDELAY_REQ_MASK    0x4\n#define    RTL8367C_P0_EAV_CFG_TX_DELAY_REQ_OFFSET    1\n#define    RTL8367C_P0_EAV_CFG_TX_DELAY_REQ_MASK    0x2\n#define    RTL8367C_P0_EAV_CFG_TX_SYNC_OFFSET    0\n#define    RTL8367C_P0_EAV_CFG_TX_SYNC_MASK    0x1\n\n#define    RTL8367C_REG_P1_TX_SYNC_SEQ_ID    0x6420\n\n#define    RTL8367C_REG_P1_TX_DELAY_REQ_SEQ_ID    0x6421\n\n#define    RTL8367C_REG_P1_TX_PDELAY_REQ_SEQ_ID    0x6422\n\n#define    RTL8367C_REG_P1_TX_PDELAY_RESP_SEQ_ID    0x6423\n\n#define    RTL8367C_REG_P1_RX_SYNC_SEQ_ID    0x6424\n\n#define    RTL8367C_REG_P1_RX_DELAY_REQ_SEQ_ID    0x6425\n\n#define    RTL8367C_REG_P1_RX_PDELAY_REQ_SEQ_ID    0x6426\n\n#define    RTL8367C_REG_P1_RX_PDELAY_RESP_SEQ_ID    0x6427\n\n#define    RTL8367C_REG_P1_PORT_NSEC_15_0    0x6428\n\n#define    RTL8367C_REG_P1_PORT_NSEC_26_16    0x6429\n#define    RTL8367C_P1_PORT_NSEC_26_16_OFFSET    0\n#define    RTL8367C_P1_PORT_NSEC_26_16_MASK    0x7FF\n\n#define    RTL8367C_REG_P1_PORT_SEC_15_0    0x642a\n\n#define    RTL8367C_REG_P1_PORT_SEC_31_16    0x642b\n\n#define    RTL8367C_REG_P1_EAV_CFG    0x642c\n#define    RTL8367C_P1_EAV_CFG_PTP_PHY_EN_EN_OFFSET    8\n#define    RTL8367C_P1_EAV_CFG_PTP_PHY_EN_EN_MASK    0x100\n#define    RTL8367C_P1_EAV_CFG_RX_PDELAY_RESP_OFFSET    7\n#define    RTL8367C_P1_EAV_CFG_RX_PDELAY_RESP_MASK    0x80\n#define    RTL8367C_P1_EAV_CFG_RX_PDELAY_REQ_OFFSET    6\n#define    RTL8367C_P1_EAV_CFG_RX_PDELAY_REQ_MASK    0x40\n#define    RTL8367C_P1_EAV_CFG_RX_DELAY_REQ_OFFSET    5\n#define    RTL8367C_P1_EAV_CFG_RX_DELAY_REQ_MASK    0x20\n#define    RTL8367C_P1_EAV_CFG_RX_SYNC_OFFSET    4\n#define    RTL8367C_P1_EAV_CFG_RX_SYNC_MASK    0x10\n#define    RTL8367C_P1_EAV_CFG_TX_PDELAY_RESP_OFFSET    3\n#define    RTL8367C_P1_EAV_CFG_TX_PDELAY_RESP_MASK    0x8\n#define    RTL8367C_P1_EAV_CFG_TX_PDELAY_REQ_OFFSET    2\n#define    RTL8367C_P1_EAV_CFG_TX_PDELAY_REQ_MASK    0x4\n#define    RTL8367C_P1_EAV_CFG_TX_DELAY_REQ_OFFSET    1\n#define    RTL8367C_P1_EAV_CFG_TX_DELAY_REQ_MASK    0x2\n#define    RTL8367C_P1_EAV_CFG_TX_SYNC_OFFSET    0\n#define    RTL8367C_P1_EAV_CFG_TX_SYNC_MASK    0x1\n\n#define    RTL8367C_REG_P2_TX_SYNC_SEQ_ID    0x6430\n\n#define    RTL8367C_REG_P2_TX_DELAY_REQ_SEQ_ID    0x6431\n\n#define    RTL8367C_REG_P2_TX_PDELAY_REQ_SEQ_ID    0x6432\n\n#define    RTL8367C_REG_P2_TX_PDELAY_RESP_SEQ_ID    0x6433\n\n#define    RTL8367C_REG_P2_RX_SYNC_SEQ_ID    0x6434\n\n#define    RTL8367C_REG_P2_RX_DELAY_REQ_SEQ_ID    0x6435\n\n#define    RTL8367C_REG_P2_RX_PDELAY_REQ_SEQ_ID    0x6436\n\n#define    RTL8367C_REG_P2_RX_PDELAY_RESP_SEQ_ID    0x6437\n\n#define    RTL8367C_REG_P2_PORT_NSEC_15_0    0x6438\n\n#define    RTL8367C_REG_P2_PORT_NSEC_26_16    0x6439\n#define    RTL8367C_P2_PORT_NSEC_26_16_OFFSET    0\n#define    RTL8367C_P2_PORT_NSEC_26_16_MASK    0x7FF\n\n#define    RTL8367C_REG_P2_PORT_SEC_15_0    0x643a\n\n#define    RTL8367C_REG_P2_PORT_SEC_31_16    0x643b\n\n#define    RTL8367C_REG_P2_EAV_CFG    0x643c\n#define    RTL8367C_P2_EAV_CFG_PTP_PHY_EN_EN_OFFSET    8\n#define    RTL8367C_P2_EAV_CFG_PTP_PHY_EN_EN_MASK    0x100\n#define    RTL8367C_P2_EAV_CFG_RX_PDELAY_RESP_OFFSET    7\n#define    RTL8367C_P2_EAV_CFG_RX_PDELAY_RESP_MASK    0x80\n#define    RTL8367C_P2_EAV_CFG_RX_PDELAY_REQ_OFFSET    6\n#define    RTL8367C_P2_EAV_CFG_RX_PDELAY_REQ_MASK    0x40\n#define    RTL8367C_P2_EAV_CFG_RX_DELAY_REQ_OFFSET    5\n#define    RTL8367C_P2_EAV_CFG_RX_DELAY_REQ_MASK    0x20\n#define    RTL8367C_P2_EAV_CFG_RX_SYNC_OFFSET    4\n#define    RTL8367C_P2_EAV_CFG_RX_SYNC_MASK    0x10\n#define    RTL8367C_P2_EAV_CFG_TX_PDELAY_RESP_OFFSET    3\n#define    RTL8367C_P2_EAV_CFG_TX_PDELAY_RESP_MASK    0x8\n#define    RTL8367C_P2_EAV_CFG_TX_PDELAY_REQ_OFFSET    2\n#define    RTL8367C_P2_EAV_CFG_TX_PDELAY_REQ_MASK    0x4\n#define    RTL8367C_P2_EAV_CFG_TX_DELAY_REQ_OFFSET    1\n#define    RTL8367C_P2_EAV_CFG_TX_DELAY_REQ_MASK    0x2\n#define    RTL8367C_P2_EAV_CFG_TX_SYNC_OFFSET    0\n#define    RTL8367C_P2_EAV_CFG_TX_SYNC_MASK    0x1\n\n#define    RTL8367C_REG_P3_TX_SYNC_SEQ_ID    0x6440\n\n#define    RTL8367C_REG_P3_TX_DELAY_REQ_SEQ_ID    0x6441\n\n#define    RTL8367C_REG_P3_TX_PDELAY_REQ_SEQ_ID    0x6442\n\n#define    RTL8367C_REG_P3_TX_PDELAY_RESP_SEQ_ID    0x6443\n\n#define    RTL8367C_REG_P3_RX_SYNC_SEQ_ID    0x6444\n\n#define    RTL8367C_REG_P3_RX_DELAY_REQ_SEQ_ID    0x6445\n\n#define    RTL8367C_REG_P3_RX_PDELAY_REQ_SEQ_ID    0x6446\n\n#define    RTL8367C_REG_P3_RX_PDELAY_RESP_SEQ_ID    0x6447\n\n#define    RTL8367C_REG_P3_PORT_NSEC_15_0    0x6448\n\n#define    RTL8367C_REG_P3_PORT_NSEC_26_16    0x6449\n#define    RTL8367C_P3_PORT_NSEC_26_16_OFFSET    0\n#define    RTL8367C_P3_PORT_NSEC_26_16_MASK    0x7FF\n\n#define    RTL8367C_REG_P3_PORT_SEC_15_0    0x644a\n\n#define    RTL8367C_REG_P3_PORT_SEC_31_16    0x644b\n\n#define    RTL8367C_REG_P3_EAV_CFG    0x644c\n#define    RTL8367C_P3_EAV_CFG_PTP_PHY_EN_EN_OFFSET    8\n#define    RTL8367C_P3_EAV_CFG_PTP_PHY_EN_EN_MASK    0x100\n#define    RTL8367C_P3_EAV_CFG_RX_PDELAY_RESP_OFFSET    7\n#define    RTL8367C_P3_EAV_CFG_RX_PDELAY_RESP_MASK    0x80\n#define    RTL8367C_P3_EAV_CFG_RX_PDELAY_REQ_OFFSET    6\n#define    RTL8367C_P3_EAV_CFG_RX_PDELAY_REQ_MASK    0x40\n#define    RTL8367C_P3_EAV_CFG_RX_DELAY_REQ_OFFSET    5\n#define    RTL8367C_P3_EAV_CFG_RX_DELAY_REQ_MASK    0x20\n#define    RTL8367C_P3_EAV_CFG_RX_SYNC_OFFSET    4\n#define    RTL8367C_P3_EAV_CFG_RX_SYNC_MASK    0x10\n#define    RTL8367C_P3_EAV_CFG_TX_PDELAY_RESP_OFFSET    3\n#define    RTL8367C_P3_EAV_CFG_TX_PDELAY_RESP_MASK    0x8\n#define    RTL8367C_P3_EAV_CFG_TX_PDELAY_REQ_OFFSET    2\n#define    RTL8367C_P3_EAV_CFG_TX_PDELAY_REQ_MASK    0x4\n#define    RTL8367C_P3_EAV_CFG_TX_DELAY_REQ_OFFSET    1\n#define    RTL8367C_P3_EAV_CFG_TX_DELAY_REQ_MASK    0x2\n#define    RTL8367C_P3_EAV_CFG_TX_SYNC_OFFSET    0\n#define    RTL8367C_P3_EAV_CFG_TX_SYNC_MASK    0x1\n\n#define    RTL8367C_REG_P4_TX_SYNC_SEQ_ID    0x6450\n\n#define    RTL8367C_REG_P4_TX_DELAY_REQ_SEQ_ID    0x6451\n\n#define    RTL8367C_REG_P4_TX_PDELAY_REQ_SEQ_ID    0x6452\n\n#define    RTL8367C_REG_P4_TX_PDELAY_RESP_SEQ_ID    0x6453\n\n#define    RTL8367C_REG_P4_RX_SYNC_SEQ_ID    0x6454\n\n#define    RTL8367C_REG_P4_RX_DELAY_REQ_SEQ_ID    0x6455\n\n#define    RTL8367C_REG_P4_RX_PDELAY_REQ_SEQ_ID    0x6456\n\n#define    RTL8367C_REG_P4_RX_PDELAY_RESP_SEQ_ID    0x6457\n\n#define    RTL8367C_REG_P4_PORT_NSEC_15_0    0x6458\n\n#define    RTL8367C_REG_P4_PORT_NSEC_26_16    0x6459\n#define    RTL8367C_P4_PORT_NSEC_26_16_OFFSET    0\n#define    RTL8367C_P4_PORT_NSEC_26_16_MASK    0x7FF\n\n#define    RTL8367C_REG_P4_PORT_SEC_15_0    0x645a\n\n#define    RTL8367C_REG_P4_PORT_SEC_31_16    0x645b\n\n#define    RTL8367C_REG_P4_EAV_CFG    0x645c\n#define    RTL8367C_P4_EAV_CFG_PTP_PHY_EN_EN_OFFSET    8\n#define    RTL8367C_P4_EAV_CFG_PTP_PHY_EN_EN_MASK    0x100\n#define    RTL8367C_P4_EAV_CFG_RX_PDELAY_RESP_OFFSET    7\n#define    RTL8367C_P4_EAV_CFG_RX_PDELAY_RESP_MASK    0x80\n#define    RTL8367C_P4_EAV_CFG_RX_PDELAY_REQ_OFFSET    6\n#define    RTL8367C_P4_EAV_CFG_RX_PDELAY_REQ_MASK    0x40\n#define    RTL8367C_P4_EAV_CFG_RX_DELAY_REQ_OFFSET    5\n#define    RTL8367C_P4_EAV_CFG_RX_DELAY_REQ_MASK    0x20\n#define    RTL8367C_P4_EAV_CFG_RX_SYNC_OFFSET    4\n#define    RTL8367C_P4_EAV_CFG_RX_SYNC_MASK    0x10\n#define    RTL8367C_P4_EAV_CFG_TX_PDELAY_RESP_OFFSET    3\n#define    RTL8367C_P4_EAV_CFG_TX_PDELAY_RESP_MASK    0x8\n#define    RTL8367C_P4_EAV_CFG_TX_PDELAY_REQ_OFFSET    2\n#define    RTL8367C_P4_EAV_CFG_TX_PDELAY_REQ_MASK    0x4\n#define    RTL8367C_P4_EAV_CFG_TX_DELAY_REQ_OFFSET    1\n#define    RTL8367C_P4_EAV_CFG_TX_DELAY_REQ_MASK    0x2\n#define    RTL8367C_P4_EAV_CFG_TX_SYNC_OFFSET    0\n#define    RTL8367C_P4_EAV_CFG_TX_SYNC_MASK    0x1\n\n#define    RTL8367C_REG_P6_TX_SYNC_SEQ_ID    0x6460\n\n#define    RTL8367C_REG_P6_TX_DELAY_REQ_SEQ_ID    0x6461\n\n#define    RTL8367C_REG_P6_TX_PDELAY_REQ_SEQ_ID    0x6462\n\n#define    RTL8367C_REG_P6_TX_PDELAY_RESP_SEQ_ID    0x6463\n\n#define    RTL8367C_REG_P6_RX_SYNC_SEQ_ID    0x6464\n\n#define    RTL8367C_REG_P6_RX_DELAY_REQ_SEQ_ID    0x6465\n\n#define    RTL8367C_REG_P6_RX_PDELAY_REQ_SEQ_ID    0x6466\n\n#define    RTL8367C_REG_P6_RX_PDELAY_RESP_SEQ_ID    0x6467\n\n#define    RTL8367C_REG_P6_PORT_NSEC_15_0    0x6468\n\n#define    RTL8367C_REG_P6_PORT_NSEC_26_16    0x6469\n#define    RTL8367C_P6_PORT_NSEC_26_16_OFFSET    0\n#define    RTL8367C_P6_PORT_NSEC_26_16_MASK    0x7FF\n\n#define    RTL8367C_REG_P6_PORT_SEC_15_0    0x646a\n\n#define    RTL8367C_REG_P6_PORT_SEC_31_16    0x646b\n\n#define    RTL8367C_REG_P6_EAV_CFG    0x646c\n#define    RTL8367C_P6_EAV_CFG_PTP_PHY_EN_EN_OFFSET    8\n#define    RTL8367C_P6_EAV_CFG_PTP_PHY_EN_EN_MASK    0x100\n#define    RTL8367C_P6_EAV_CFG_RX_PDELAY_RESP_OFFSET    7\n#define    RTL8367C_P6_EAV_CFG_RX_PDELAY_RESP_MASK    0x80\n#define    RTL8367C_P6_EAV_CFG_RX_PDELAY_REQ_OFFSET    6\n#define    RTL8367C_P6_EAV_CFG_RX_PDELAY_REQ_MASK    0x40\n#define    RTL8367C_P6_EAV_CFG_RX_DELAY_REQ_OFFSET    5\n#define    RTL8367C_P6_EAV_CFG_RX_DELAY_REQ_MASK    0x20\n#define    RTL8367C_P6_EAV_CFG_RX_SYNC_OFFSET    4\n#define    RTL8367C_P6_EAV_CFG_RX_SYNC_MASK    0x10\n#define    RTL8367C_P6_EAV_CFG_TX_PDELAY_RESP_OFFSET    3\n#define    RTL8367C_P6_EAV_CFG_TX_PDELAY_RESP_MASK    0x8\n#define    RTL8367C_P6_EAV_CFG_TX_PDELAY_REQ_OFFSET    2\n#define    RTL8367C_P6_EAV_CFG_TX_PDELAY_REQ_MASK    0x4\n#define    RTL8367C_P6_EAV_CFG_TX_DELAY_REQ_OFFSET    1\n#define    RTL8367C_P6_EAV_CFG_TX_DELAY_REQ_MASK    0x2\n#define    RTL8367C_P6_EAV_CFG_TX_SYNC_OFFSET    0\n#define    RTL8367C_P6_EAV_CFG_TX_SYNC_MASK    0x1\n\n#define    RTL8367C_REG_P7_TX_SYNC_SEQ_ID    0x6470\n\n#define    RTL8367C_REG_P7_TX_DELAY_REQ_SEQ_ID    0x6471\n\n#define    RTL8367C_REG_P7_TX_PDELAY_REQ_SEQ_ID    0x6472\n\n#define    RTL8367C_REG_P7_TX_PDELAY_RESP_SEQ_ID    0x6473\n\n#define    RTL8367C_REG_P7_RX_SYNC_SEQ_ID    0x6474\n\n#define    RTL8367C_REG_P7_RX_DELAY_REQ_SEQ_ID    0x6475\n\n#define    RTL8367C_REG_P7_RX_PDELAY_REQ_SEQ_ID    0x6476\n\n#define    RTL8367C_REG_P7_RX_PDELAY_RESP_SEQ_ID    0x6477\n\n#define    RTL8367C_REG_P7_PORT_NSEC_15_0    0x6478\n\n#define    RTL8367C_REG_P7_PORT_NSEC_26_16    0x6479\n#define    RTL8367C_P7_PORT_NSEC_26_16_OFFSET    0\n#define    RTL8367C_P7_PORT_NSEC_26_16_MASK    0x7FF\n\n#define    RTL8367C_REG_P7_PORT_SEC_15_0    0x647a\n\n#define    RTL8367C_REG_P7_PORT_SEC_31_16    0x647b\n\n#define    RTL8367C_REG_P7_EAV_CFG    0x647c\n#define    RTL8367C_P7_EAV_CFG_PTP_PHY_EN_EN_OFFSET    8\n#define    RTL8367C_P7_EAV_CFG_PTP_PHY_EN_EN_MASK    0x100\n#define    RTL8367C_P7_EAV_CFG_RX_PDELAY_RESP_OFFSET    7\n#define    RTL8367C_P7_EAV_CFG_RX_PDELAY_RESP_MASK    0x80\n#define    RTL8367C_P7_EAV_CFG_RX_PDELAY_REQ_OFFSET    6\n#define    RTL8367C_P7_EAV_CFG_RX_PDELAY_REQ_MASK    0x40\n#define    RTL8367C_P7_EAV_CFG_RX_DELAY_REQ_OFFSET    5\n#define    RTL8367C_P7_EAV_CFG_RX_DELAY_REQ_MASK    0x20\n#define    RTL8367C_P7_EAV_CFG_RX_SYNC_OFFSET    4\n#define    RTL8367C_P7_EAV_CFG_RX_SYNC_MASK    0x10\n#define    RTL8367C_P7_EAV_CFG_TX_PDELAY_RESP_OFFSET    3\n#define    RTL8367C_P7_EAV_CFG_TX_PDELAY_RESP_MASK    0x8\n#define    RTL8367C_P7_EAV_CFG_TX_PDELAY_REQ_OFFSET    2\n#define    RTL8367C_P7_EAV_CFG_TX_PDELAY_REQ_MASK    0x4\n#define    RTL8367C_P7_EAV_CFG_TX_DELAY_REQ_OFFSET    1\n#define    RTL8367C_P7_EAV_CFG_TX_DELAY_REQ_MASK    0x2\n#define    RTL8367C_P7_EAV_CFG_TX_SYNC_OFFSET    0\n#define    RTL8367C_P7_EAV_CFG_TX_SYNC_MASK    0x1\n\n#define    RTL8367C_REG_P5_TX_SYNC_SEQ_ID    0x6480\n\n#define    RTL8367C_REG_P5_TX_DELAY_REQ_SEQ_ID    0x6481\n\n#define    RTL8367C_REG_P5_TX_PDELAY_REQ_SEQ_ID    0x6482\n\n#define    RTL8367C_REG_P5_TX_PDELAY_RESP_SEQ_ID    0x6483\n\n#define    RTL8367C_REG_P5_RX_SYNC_SEQ_ID    0x6484\n\n#define    RTL8367C_REG_P5_RX_DELAY_REQ_SEQ_ID    0x6485\n\n#define    RTL8367C_REG_P5_RX_PDELAY_REQ_SEQ_ID    0x6486\n\n#define    RTL8367C_REG_P5_RX_PDELAY_RESP_SEQ_ID    0x6487\n\n#define    RTL8367C_REG_P5_PORT_NSEC_15_0    0x6488\n\n#define    RTL8367C_REG_P5_PORT_NSEC_26_16    0x6489\n#define    RTL8367C_P5_PORT_NSEC_26_16_OFFSET    0\n#define    RTL8367C_P5_PORT_NSEC_26_16_MASK    0x7FF\n\n#define    RTL8367C_REG_P5_PORT_SEC_15_0    0x648a\n\n#define    RTL8367C_REG_P5_PORT_SEC_31_16    0x648b\n\n#define    RTL8367C_REG_P5_EAV_CFG    0x648c\n#define    RTL8367C_P5_EAV_CFG_PTP_PHY_EN_EN_OFFSET    8\n#define    RTL8367C_P5_EAV_CFG_PTP_PHY_EN_EN_MASK    0x100\n#define    RTL8367C_P5_EAV_CFG_RX_PDELAY_RESP_OFFSET    7\n#define    RTL8367C_P5_EAV_CFG_RX_PDELAY_RESP_MASK    0x80\n#define    RTL8367C_P5_EAV_CFG_RX_PDELAY_REQ_OFFSET    6\n#define    RTL8367C_P5_EAV_CFG_RX_PDELAY_REQ_MASK    0x40\n#define    RTL8367C_P5_EAV_CFG_RX_DELAY_REQ_OFFSET    5\n#define    RTL8367C_P5_EAV_CFG_RX_DELAY_REQ_MASK    0x20\n#define    RTL8367C_P5_EAV_CFG_RX_SYNC_OFFSET    4\n#define    RTL8367C_P5_EAV_CFG_RX_SYNC_MASK    0x10\n#define    RTL8367C_P5_EAV_CFG_TX_PDELAY_RESP_OFFSET    3\n#define    RTL8367C_P5_EAV_CFG_TX_PDELAY_RESP_MASK    0x8\n#define    RTL8367C_P5_EAV_CFG_TX_PDELAY_REQ_OFFSET    2\n#define    RTL8367C_P5_EAV_CFG_TX_PDELAY_REQ_MASK    0x4\n#define    RTL8367C_P5_EAV_CFG_TX_DELAY_REQ_OFFSET    1\n#define    RTL8367C_P5_EAV_CFG_TX_DELAY_REQ_MASK    0x2\n#define    RTL8367C_P5_EAV_CFG_TX_SYNC_OFFSET    0\n#define    RTL8367C_P5_EAV_CFG_TX_SYNC_MASK    0x1\n\n#define    RTL8367C_REG_P8_TX_SYNC_SEQ_ID    0x6490\n\n#define    RTL8367C_REG_P8_TX_DELAY_REQ_SEQ_ID    0x6491\n\n#define    RTL8367C_REG_P8_TX_PDELAY_REQ_SEQ_ID    0x6492\n\n#define    RTL8367C_REG_P8_TX_PDELAY_RESP_SEQ_ID    0x6493\n\n#define    RTL8367C_REG_P8_RX_SYNC_SEQ_ID    0x6494\n\n#define    RTL8367C_REG_P8_RX_DELAY_REQ_SEQ_ID    0x6495\n\n#define    RTL8367C_REG_P8_RX_PDELAY_REQ_SEQ_ID    0x6496\n\n#define    RTL8367C_REG_P8_RX_PDELAY_RESP_SEQ_ID    0x6497\n\n#define    RTL8367C_REG_P8_PORT_NSEC_15_0    0x6498\n\n#define    RTL8367C_REG_P8_PORT_NSEC_26_16    0x6499\n#define    RTL8367C_P8_PORT_NSEC_26_16_OFFSET    0\n#define    RTL8367C_P8_PORT_NSEC_26_16_MASK    0x7FF\n\n#define    RTL8367C_REG_P8_PORT_SEC_15_0    0x649a\n\n#define    RTL8367C_REG_P8_PORT_SEC_31_16    0x649b\n\n#define    RTL8367C_REG_P8_EAV_CFG    0x649c\n#define    RTL8367C_P8_EAV_CFG_PTP_PHY_EN_EN_OFFSET    8\n#define    RTL8367C_P8_EAV_CFG_PTP_PHY_EN_EN_MASK    0x100\n#define    RTL8367C_P8_EAV_CFG_RX_PDELAY_RESP_OFFSET    7\n#define    RTL8367C_P8_EAV_CFG_RX_PDELAY_RESP_MASK    0x80\n#define    RTL8367C_P8_EAV_CFG_RX_PDELAY_REQ_OFFSET    6\n#define    RTL8367C_P8_EAV_CFG_RX_PDELAY_REQ_MASK    0x40\n#define    RTL8367C_P8_EAV_CFG_RX_DELAY_REQ_OFFSET    5\n#define    RTL8367C_P8_EAV_CFG_RX_DELAY_REQ_MASK    0x20\n#define    RTL8367C_P8_EAV_CFG_RX_SYNC_OFFSET    4\n#define    RTL8367C_P8_EAV_CFG_RX_SYNC_MASK    0x10\n#define    RTL8367C_P8_EAV_CFG_TX_PDELAY_RESP_OFFSET    3\n#define    RTL8367C_P8_EAV_CFG_TX_PDELAY_RESP_MASK    0x8\n#define    RTL8367C_P8_EAV_CFG_TX_PDELAY_REQ_OFFSET    2\n#define    RTL8367C_P8_EAV_CFG_TX_PDELAY_REQ_MASK    0x4\n#define    RTL8367C_P8_EAV_CFG_TX_DELAY_REQ_OFFSET    1\n#define    RTL8367C_P8_EAV_CFG_TX_DELAY_REQ_MASK    0x2\n#define    RTL8367C_P8_EAV_CFG_TX_SYNC_OFFSET    0\n#define    RTL8367C_P8_EAV_CFG_TX_SYNC_MASK    0x1\n\n#define    RTL8367C_REG_P9_TX_SYNC_SEQ_ID    0x64a0\n\n#define    RTL8367C_REG_P9_TX_DELAY_REQ_SEQ_ID    0x64a1\n\n#define    RTL8367C_REG_P9_TX_PDELAY_REQ_SEQ_ID    0x64a2\n\n#define    RTL8367C_REG_P9_TX_PDELAY_RESP_SEQ_ID    0x64a3\n\n#define    RTL8367C_REG_P9_RX_SYNC_SEQ_ID    0x64a4\n\n#define    RTL8367C_REG_P9_RX_DELAY_REQ_SEQ_ID    0x64a5\n\n#define    RTL8367C_REG_P9_RX_PDELAY_REQ_SEQ_ID    0x64a6\n\n#define    RTL8367C_REG_P9_RX_PDELAY_RESP_SEQ_ID    0x64a7\n\n#define    RTL8367C_REG_P9_PORT_NSEC_15_0    0x64a8\n\n#define    RTL8367C_REG_P9_PORT_NSEC_26_16    0x64a9\n#define    RTL8367C_P9_PORT_NSEC_26_16_OFFSET    0\n#define    RTL8367C_P9_PORT_NSEC_26_16_MASK    0x7FF\n\n#define    RTL8367C_REG_P9_PORT_SEC_15_0    0x64aa\n\n#define    RTL8367C_REG_P9_PORT_SEC_31_16    0x64ab\n\n#define    RTL8367C_REG_P9_EAV_CFG    0x64ac\n#define    RTL8367C_P9_EAV_CFG_PTP_PHY_EN_EN_OFFSET    8\n#define    RTL8367C_P9_EAV_CFG_PTP_PHY_EN_EN_MASK    0x100\n#define    RTL8367C_P9_EAV_CFG_RX_PDELAY_RESP_OFFSET    7\n#define    RTL8367C_P9_EAV_CFG_RX_PDELAY_RESP_MASK    0x80\n#define    RTL8367C_P9_EAV_CFG_RX_PDELAY_REQ_OFFSET    6\n#define    RTL8367C_P9_EAV_CFG_RX_PDELAY_REQ_MASK    0x40\n#define    RTL8367C_P9_EAV_CFG_RX_DELAY_REQ_OFFSET    5\n#define    RTL8367C_P9_EAV_CFG_RX_DELAY_REQ_MASK    0x20\n#define    RTL8367C_P9_EAV_CFG_RX_SYNC_OFFSET    4\n#define    RTL8367C_P9_EAV_CFG_RX_SYNC_MASK    0x10\n#define    RTL8367C_P9_EAV_CFG_TX_PDELAY_RESP_OFFSET    3\n#define    RTL8367C_P9_EAV_CFG_TX_PDELAY_RESP_MASK    0x8\n#define    RTL8367C_P9_EAV_CFG_TX_PDELAY_REQ_OFFSET    2\n#define    RTL8367C_P9_EAV_CFG_TX_PDELAY_REQ_MASK    0x4\n#define    RTL8367C_P9_EAV_CFG_TX_DELAY_REQ_OFFSET    1\n#define    RTL8367C_P9_EAV_CFG_TX_DELAY_REQ_MASK    0x2\n#define    RTL8367C_P9_EAV_CFG_TX_SYNC_OFFSET    0\n#define    RTL8367C_P9_EAV_CFG_TX_SYNC_MASK    0x1\n\n/* (16'h6600)sds_indacs_reg */\n\n#define    RTL8367C_REG_SDS_INDACS_CMD    0x6600\n#define    RTL8367C_SDS_CMD_BUSY_OFFSET    8\n#define    RTL8367C_SDS_CMD_BUSY_MASK    0x100\n#define    RTL8367C_SDS_CMD_OFFSET    7\n#define    RTL8367C_SDS_CMD_MASK    0x80\n#define    RTL8367C_SDS_RWOP_OFFSET    6\n#define    RTL8367C_SDS_RWOP_MASK    0x40\n#define    RTL8367C_SDS_INDEX_OFFSET    0\n#define    RTL8367C_SDS_INDEX_MASK    0x3F\n\n#define    RTL8367C_REG_SDS_INDACS_ADR    0x6601\n#define    RTL8367C_SDS_PAGE_OFFSET    5\n#define    RTL8367C_SDS_PAGE_MASK    0x7E0\n#define    RTL8367C_SDS_REGAD_OFFSET    0\n#define    RTL8367C_SDS_REGAD_MASK    0x1F\n\n#define    RTL8367C_REG_SDS_INDACS_DATA    0x6602\n\n\n#endif /*#ifndef _RTL8367C_REG_H_*/\n\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/smi.h",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * Purpose : RTL8367C switch low-level function for access register\n * Feature : SMI related functions\n *\n */\n\n#ifndef __SMI_H__\n#define __SMI_H__\n\n#include <rtk_types.h>\n#include \"rtk_error.h\"\n\n#define MDC_MDIO_CTRL0_REG          31\n#define MDC_MDIO_START_REG          29\n#define MDC_MDIO_CTRL1_REG          21\n#define MDC_MDIO_ADDRESS_REG        23\n#define MDC_MDIO_DATA_WRITE_REG     24\n#define MDC_MDIO_DATA_READ_REG      25\n#define MDC_MDIO_PREAMBLE_LEN       32\n\n#define MDC_MDIO_START_OP          0xFFFF\n#define MDC_MDIO_ADDR_OP           0x000E\n#define MDC_MDIO_READ_OP           0x0001\n#define MDC_MDIO_WRITE_OP          0x0003\n\n#define SPI_READ_OP                 0x3\n#define SPI_WRITE_OP                0x2\n#define SPI_READ_OP_LEN             0x8\n#define SPI_WRITE_OP_LEN            0x8\n#define SPI_REG_LEN                 16\n#define SPI_DATA_LEN                16\n\n#define GPIO_DIR_IN                 1\n#define GPIO_DIR_OUT                0\n\n#define ack_timer                   5\n\n#define DELAY                        10000\n#define CLK_DURATION(clk)            { int i; for(i=0; i<clk; i++); }\n\nrtk_int32 smi_read(rtk_uint32 mAddrs, rtk_uint32 *rData);\nrtk_int32 smi_write(rtk_uint32 mAddrs, rtk_uint32 rData);\n\n#endif /* __SMI_H__ */\n\n\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/stat.h",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * Purpose : RTL8367/RTL8367C switch high-level API\n *\n * Feature : The file includes MIB module high-layer API defination\n *\n */\n\n#ifndef __RTK_API_STAT_H__\n#define __RTK_API_STAT_H__\n\n/*\n * Data Type Declaration\n */\ntypedef rtk_u_long_t rtk_stat_counter_t;\n\n/* global statistic counter structure */\ntypedef struct rtk_stat_global_cntr_s\n{\n    rtk_uint64 dot1dTpLearnedEntryDiscards;\n}rtk_stat_global_cntr_t;\n\ntypedef enum rtk_stat_global_type_e\n{\n    DOT1D_TP_LEARNED_ENTRY_DISCARDS_INDEX = 58,\n    MIB_GLOBAL_CNTR_END\n}rtk_stat_global_type_t;\n\n/* port statistic counter structure */\ntypedef struct rtk_stat_port_cntr_s\n{\n    rtk_uint64 ifInOctets;\n    rtk_uint32 dot3StatsFCSErrors;\n    rtk_uint32 dot3StatsSymbolErrors;\n    rtk_uint32 dot3InPauseFrames;\n    rtk_uint32 dot3ControlInUnknownOpcodes;\n    rtk_uint32 etherStatsFragments;\n    rtk_uint32 etherStatsJabbers;\n    rtk_uint32 ifInUcastPkts;\n    rtk_uint32 etherStatsDropEvents;\n    rtk_uint64 etherStatsOctets;\n    rtk_uint32 etherStatsUndersizePkts;\n    rtk_uint32 etherStatsOversizePkts;\n    rtk_uint32 etherStatsPkts64Octets;\n    rtk_uint32 etherStatsPkts65to127Octets;\n    rtk_uint32 etherStatsPkts128to255Octets;\n    rtk_uint32 etherStatsPkts256to511Octets;\n    rtk_uint32 etherStatsPkts512to1023Octets;\n    rtk_uint32 etherStatsPkts1024toMaxOctets;\n    rtk_uint32 etherStatsMcastPkts;\n    rtk_uint32 etherStatsBcastPkts;\n    rtk_uint64 ifOutOctets;\n    rtk_uint32 dot3StatsSingleCollisionFrames;\n    rtk_uint32 dot3StatsMultipleCollisionFrames;\n    rtk_uint32 dot3StatsDeferredTransmissions;\n    rtk_uint32 dot3StatsLateCollisions;\n    rtk_uint32 etherStatsCollisions;\n    rtk_uint32 dot3StatsExcessiveCollisions;\n    rtk_uint32 dot3OutPauseFrames;\n    rtk_uint32 dot1dBasePortDelayExceededDiscards;\n    rtk_uint32 dot1dTpPortInDiscards;\n    rtk_uint32 ifOutUcastPkts;\n    rtk_uint32 ifOutMulticastPkts;\n    rtk_uint32 ifOutBrocastPkts;\n    rtk_uint32 outOampduPkts;\n    rtk_uint32 inOampduPkts;\n    rtk_uint32 pktgenPkts;\n    rtk_uint32 inMldChecksumError;\n    rtk_uint32 inIgmpChecksumError;\n    rtk_uint32 inMldSpecificQuery;\n    rtk_uint32 inMldGeneralQuery;\n    rtk_uint32 inIgmpSpecificQuery;\n    rtk_uint32 inIgmpGeneralQuery;\n    rtk_uint32 inMldLeaves;\n    rtk_uint32 inIgmpLeaves;\n    rtk_uint32 inIgmpJoinsSuccess;\n    rtk_uint32 inIgmpJoinsFail;\n    rtk_uint32 inMldJoinsSuccess;\n    rtk_uint32 inMldJoinsFail;\n    rtk_uint32 inReportSuppressionDrop;\n    rtk_uint32 inLeaveSuppressionDrop;\n    rtk_uint32 outIgmpReports;\n    rtk_uint32 outIgmpLeaves;\n    rtk_uint32 outIgmpGeneralQuery;\n    rtk_uint32 outIgmpSpecificQuery;\n    rtk_uint32 outMldReports;\n    rtk_uint32 outMldLeaves;\n    rtk_uint32 outMldGeneralQuery;\n    rtk_uint32 outMldSpecificQuery;\n    rtk_uint32 inKnownMulticastPkts;\n    rtk_uint32 ifInMulticastPkts;\n    rtk_uint32 ifInBroadcastPkts;\n    rtk_uint32 ifOutDiscards;\n}rtk_stat_port_cntr_t;\n\n/* port statistic counter index */\ntypedef enum rtk_stat_port_type_e\n{\n    STAT_IfInOctets = 0,\n    STAT_Dot3StatsFCSErrors,\n    STAT_Dot3StatsSymbolErrors,\n    STAT_Dot3InPauseFrames,\n    STAT_Dot3ControlInUnknownOpcodes,\n    STAT_EtherStatsFragments,\n    STAT_EtherStatsJabbers,\n    STAT_IfInUcastPkts,\n    STAT_EtherStatsDropEvents,\n    STAT_EtherStatsOctets,\n    STAT_EtherStatsUnderSizePkts,\n    STAT_EtherOversizeStats,\n    STAT_EtherStatsPkts64Octets,\n    STAT_EtherStatsPkts65to127Octets,\n    STAT_EtherStatsPkts128to255Octets,\n    STAT_EtherStatsPkts256to511Octets,\n    STAT_EtherStatsPkts512to1023Octets,\n    STAT_EtherStatsPkts1024to1518Octets,\n    STAT_EtherStatsMulticastPkts,\n    STAT_EtherStatsBroadcastPkts,\n    STAT_IfOutOctets,\n    STAT_Dot3StatsSingleCollisionFrames,\n    STAT_Dot3StatsMultipleCollisionFrames,\n    STAT_Dot3StatsDeferredTransmissions,\n    STAT_Dot3StatsLateCollisions,\n    STAT_EtherStatsCollisions,\n    STAT_Dot3StatsExcessiveCollisions,\n    STAT_Dot3OutPauseFrames,\n    STAT_Dot1dBasePortDelayExceededDiscards,\n    STAT_Dot1dTpPortInDiscards,\n    STAT_IfOutUcastPkts,\n    STAT_IfOutMulticastPkts,\n    STAT_IfOutBroadcastPkts,\n    STAT_OutOampduPkts,\n    STAT_InOampduPkts,\n    STAT_PktgenPkts,\n    STAT_InMldChecksumError,\n    STAT_InIgmpChecksumError,\n    STAT_InMldSpecificQuery,\n    STAT_InMldGeneralQuery,\n    STAT_InIgmpSpecificQuery,\n    STAT_InIgmpGeneralQuery,\n    STAT_InMldLeaves,\n    STAT_InIgmpInterfaceLeaves,\n    STAT_InIgmpJoinsSuccess,\n    STAT_InIgmpJoinsFail,\n    STAT_InMldJoinsSuccess,\n    STAT_InMldJoinsFail,\n    STAT_InReportSuppressionDrop,\n    STAT_InLeaveSuppressionDrop,\n    STAT_OutIgmpReports,\n    STAT_OutIgmpLeaves,\n    STAT_OutIgmpGeneralQuery,\n    STAT_OutIgmpSpecificQuery,\n    STAT_OutMldReports,\n    STAT_OutMldLeaves,\n    STAT_OutMldGeneralQuery,\n    STAT_OutMldSpecificQuery,\n    STAT_InKnownMulticastPkts,\n    STAT_IfInMulticastPkts,\n    STAT_IfInBroadcastPkts,\n    STAT_IfOutDiscards,\n    STAT_PORT_CNTR_END\n}rtk_stat_port_type_t;\n\ntypedef enum rtk_logging_counter_mode_e\n{\n    LOGGING_MODE_32BIT = 0,\n    LOGGING_MODE_64BIT,\n    LOGGING_MODE_END\n}rtk_logging_counter_mode_t;\n\ntypedef enum rtk_logging_counter_type_e\n{\n    LOGGING_TYPE_PACKET = 0,\n    LOGGING_TYPE_BYTE,\n    LOGGING_TYPE_END\n}rtk_logging_counter_type_t;\n\ntypedef enum rtk_stat_lengthMode_e\n{\n    LENGTH_MODE_EXC_TAG = 0,\n    LENGTH_MODE_INC_TAG,\n    LENGTH_MODE_END\n}rtk_stat_lengthMode_t;\n\n\n\n/* Function Name:\n *      rtk_stat_global_reset\n * Description:\n *      Reset global MIB counter.\n * Input:\n *      None\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n * Note:\n *      Reset MIB counter of ports. API will use global reset while port mask is all-ports.\n */\nextern rtk_api_ret_t rtk_stat_global_reset(void);\n\n/* Function Name:\n *      rtk_stat_port_reset\n * Description:\n *      Reset per port MIB counter by port.\n * Input:\n *      port - port id.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n * Note:\n *\n */\nextern rtk_api_ret_t rtk_stat_port_reset(rtk_port_t port);\n\n/* Function Name:\n *      rtk_stat_queueManage_reset\n * Description:\n *      Reset queue manage MIB counter.\n * Input:\n *      None\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n * Note:\n *\n */\nextern rtk_api_ret_t rtk_stat_queueManage_reset(void);\n\n/* Function Name:\n *      rtk_stat_global_get\n * Description:\n *      Get global MIB counter\n * Input:\n *      cntr_idx - global counter index.\n * Output:\n *      pCntr - global counter value.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n * Note:\n *      Get global MIB counter by index definition.\n */\nextern rtk_api_ret_t rtk_stat_global_get(rtk_stat_global_type_t cntr_idx, rtk_stat_counter_t *pCntr);\n\n/* Function Name:\n *      rtk_stat_global_getAll\n * Description:\n *      Get all global MIB counter\n * Input:\n *      None\n * Output:\n *      pGlobal_cntrs - global counter structure.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n * Note:\n *      Get all global MIB counter by index definition.\n */\nextern rtk_api_ret_t rtk_stat_global_getAll(rtk_stat_global_cntr_t *pGlobal_cntrs);\n\n/* Function Name:\n *      rtk_stat_port_get\n * Description:\n *      Get per port MIB counter by index\n * Input:\n *      port        - port id.\n *      cntr_idx    - port counter index.\n * Output:\n *      pCntr - MIB retrived counter.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n * Note:\n *      Get per port MIB counter by index definition.\n */\nextern rtk_api_ret_t rtk_stat_port_get(rtk_port_t port, rtk_stat_port_type_t cntr_idx, rtk_stat_counter_t *pCntr);\n\n/* Function Name:\n *      rtk_stat_port_getAll\n * Description:\n *      Get all counters of one specified port in the specified device.\n * Input:\n *      port - port id.\n * Output:\n *      pPort_cntrs - buffer pointer of counter value.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n * Note:\n *      Get all MIB counters of one port.\n */\nextern rtk_api_ret_t rtk_stat_port_getAll(rtk_port_t port, rtk_stat_port_cntr_t *pPort_cntrs);\n\n/* Function Name:\n *      rtk_stat_logging_counterCfg_set\n * Description:\n *      Set the type and mode of Logging Counter\n * Input:\n *      idx     - The index of Logging Counter. Should be even number only.(0,2,4,6,8.....30)\n *      mode    - 32 bits or 64 bits mode\n *      type    - Packet counter or byte counter\n * Output:\n *      None.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_OUT_OF_RANGE - Out of range.\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n * Note:\n *      Set the type and mode of Logging Counter.\n */\nextern rtk_api_ret_t rtk_stat_logging_counterCfg_set(rtk_uint32 idx, rtk_logging_counter_mode_t mode, rtk_logging_counter_type_t type);\n\n/* Function Name:\n *      rtk_stat_logging_counterCfg_get\n * Description:\n *      Get the type and mode of Logging Counter\n * Input:\n *      idx     - The index of Logging Counter. Should be even number only.(0,2,4,6,8.....30)\n * Output:\n *      pMode   - 32 bits or 64 bits mode\n *      pType   - Packet counter or byte counter\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_OUT_OF_RANGE - Out of range.\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_NULL_POINTER - NULL Pointer\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n * Note:\n *      Get the type and mode of Logging Counter.\n */\nextern rtk_api_ret_t rtk_stat_logging_counterCfg_get(rtk_uint32 idx, rtk_logging_counter_mode_t *pMode, rtk_logging_counter_type_t *pType);\n\n/* Function Name:\n *      rtk_stat_logging_counter_reset\n * Description:\n *      Reset Logging Counter\n * Input:\n *      idx     - The index of Logging Counter. (0~31)\n * Output:\n *      None.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_OUT_OF_RANGE - Out of range.\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n * Note:\n *      Reset Logging Counter.\n */\nextern rtk_api_ret_t rtk_stat_logging_counter_reset(rtk_uint32 idx);\n\n/* Function Name:\n *      rtk_stat_logging_counter_get\n * Description:\n *      Get Logging Counter\n * Input:\n *      idx     - The index of Logging Counter. (0~31)\n * Output:\n *      pCnt    - Logging counter value\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_OUT_OF_RANGE - Out of range.\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n * Note:\n *      Get Logging Counter.\n */\nextern rtk_api_ret_t rtk_stat_logging_counter_get(rtk_uint32 idx, rtk_uint32 *pCnt);\n\n/* Function Name:\n *      rtk_stat_lengthMode_set\n * Description:\n *      Set Legnth mode.\n * Input:\n *      txMode     - The length counting mode\n *      rxMode     - The length counting mode\n * Output:\n *      None.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_INPUT        - Out of range.\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n * Note:\n *\n */\nextern rtk_api_ret_t rtk_stat_lengthMode_set(rtk_stat_lengthMode_t txMode, rtk_stat_lengthMode_t rxMode);\n\n/* Function Name:\n *      rtk_stat_lengthMode_get\n * Description:\n *      Get Legnth mode.\n * Input:\n *      None.\n * Output:\n *      pTxMode       - The length counting mode\n *      pRxMode       - The length counting mode\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_INPUT        - Out of range.\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n * Note:\n */\nextern rtk_api_ret_t rtk_stat_lengthMode_get(rtk_stat_lengthMode_t *pTxMode, rtk_stat_lengthMode_t *pRxMode);\n\n#endif /* __RTK_API_STAT_H__ */\n\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/storm.h",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * Purpose : RTL8367/RTL8367C switch high-level API\n *\n * Feature : The file includes Storm module high-layer API defination\n *\n */\n\n#ifndef __RTK_API_STORM_H__\n#define __RTK_API_STORM_H__\n\n#define STORM_UNUC_INDEX                            28\n#define STORM_UNMC_INDEX                            29\n#define STORM_MC_INDEX                              30\n#define STORM_BC_INDEX                              31\n\ntypedef enum rtk_rate_storm_group_e\n{\n    STORM_GROUP_UNKNOWN_UNICAST = 0,\n    STORM_GROUP_UNKNOWN_MULTICAST,\n    STORM_GROUP_MULTICAST,\n    STORM_GROUP_BROADCAST,\n    STORM_GROUP_END\n} rtk_rate_storm_group_t;\n\ntypedef enum rtk_storm_bypass_e\n{\n    BYPASS_BRG_GROUP = 0,\n    BYPASS_FD_PAUSE,\n    BYPASS_SP_MCAST,\n    BYPASS_1X_PAE,\n    BYPASS_UNDEF_BRG_04,\n    BYPASS_UNDEF_BRG_05,\n    BYPASS_UNDEF_BRG_06,\n    BYPASS_UNDEF_BRG_07,\n    BYPASS_PROVIDER_BRIDGE_GROUP_ADDRESS,\n    BYPASS_UNDEF_BRG_09,\n    BYPASS_UNDEF_BRG_0A,\n    BYPASS_UNDEF_BRG_0B,\n    BYPASS_UNDEF_BRG_0C,\n    BYPASS_PROVIDER_BRIDGE_GVRP_ADDRESS,\n    BYPASS_8021AB,\n    BYPASS_UNDEF_BRG_0F,\n    BYPASS_BRG_MNGEMENT,\n    BYPASS_UNDEFINED_11,\n    BYPASS_UNDEFINED_12,\n    BYPASS_UNDEFINED_13,\n    BYPASS_UNDEFINED_14,\n    BYPASS_UNDEFINED_15,\n    BYPASS_UNDEFINED_16,\n    BYPASS_UNDEFINED_17,\n    BYPASS_UNDEFINED_18,\n    BYPASS_UNDEFINED_19,\n    BYPASS_UNDEFINED_1A,\n    BYPASS_UNDEFINED_1B,\n    BYPASS_UNDEFINED_1C,\n    BYPASS_UNDEFINED_1D,\n    BYPASS_UNDEFINED_1E,\n    BYPASS_UNDEFINED_1F,\n    BYPASS_GMRP,\n    BYPASS_GVRP,\n    BYPASS_UNDEF_GARP_22,\n    BYPASS_UNDEF_GARP_23,\n    BYPASS_UNDEF_GARP_24,\n    BYPASS_UNDEF_GARP_25,\n    BYPASS_UNDEF_GARP_26,\n    BYPASS_UNDEF_GARP_27,\n    BYPASS_UNDEF_GARP_28,\n    BYPASS_UNDEF_GARP_29,\n    BYPASS_UNDEF_GARP_2A,\n    BYPASS_UNDEF_GARP_2B,\n    BYPASS_UNDEF_GARP_2C,\n    BYPASS_UNDEF_GARP_2D,\n    BYPASS_UNDEF_GARP_2E,\n    BYPASS_UNDEF_GARP_2F,\n    BYPASS_IGMP,\n    BYPASS_CDP,\n    BYPASS_CSSTP,\n    BYPASS_LLDP,\n    BYPASS_END,\n}rtk_storm_bypass_t;\n\n/* Function Name:\n *      rtk_rate_stormControlMeterIdx_set\n * Description:\n *      Set the storm control meter index.\n * Input:\n *      port       - port id\n *      storm_type - storm group type\n *      index       - storm control meter index.\n * Output:\n *      None.\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n *      RT_ERR_PORT_ID - Invalid port id\n *      RT_ERR_FILTER_METER_ID  - Invalid meter\n * Note:\n *\n */\nextern rtk_api_ret_t rtk_rate_stormControlMeterIdx_set(rtk_port_t port, rtk_rate_storm_group_t stormType, rtk_uint32 index);\n\n/* Function Name:\n *      rtk_rate_stormControlMeterIdx_get\n * Description:\n *      Get the storm control meter index.\n * Input:\n *      port       - port id\n *      storm_type - storm group type\n * Output:\n *      pIndex     - storm control meter index.\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n *      RT_ERR_PORT_ID - Invalid port id\n *      RT_ERR_FILTER_METER_ID  - Invalid meter\n * Note:\n *\n */\nextern rtk_api_ret_t rtk_rate_stormControlMeterIdx_get(rtk_port_t port, rtk_rate_storm_group_t stormType, rtk_uint32 *pIndex);\n\n/* Function Name:\n *      rtk_rate_stormControlPortEnable_set\n * Description:\n *      Set enable status of storm control on specified port.\n * Input:\n *      port       - port id\n *      stormType  - storm group type\n *      enable     - enable status of storm control\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n *      RT_ERR_NOT_INIT          - The module is not initial\n *      RT_ERR_PORT_ID           - invalid port id\n *      RT_ERR_INPUT             - invalid input parameter\n * Note:\n *\n */\nextern rtk_api_ret_t rtk_rate_stormControlPortEnable_set(rtk_port_t port, rtk_rate_storm_group_t stormType, rtk_enable_t enable);\n\n/* Function Name:\n *      rtk_rate_stormControlPortEnable_set\n * Description:\n *      Set enable status of storm control on specified port.\n * Input:\n *      port       - port id\n *      stormType  - storm group type\n * Output:\n *      pEnable     - enable status of storm control\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n *      RT_ERR_NOT_INIT          - The module is not initial\n *      RT_ERR_PORT_ID           - invalid port id\n *      RT_ERR_INPUT             - invalid input parameter\n * Note:\n *\n */\nextern rtk_api_ret_t rtk_rate_stormControlPortEnable_get(rtk_port_t port, rtk_rate_storm_group_t stormType, rtk_enable_t *pEnable);\n\n/* Function Name:\n *      rtk_storm_bypass_set\n * Description:\n *      Set bypass storm filter control configuration.\n * Input:\n *      type    - Bypass storm filter control type.\n *      enable  - Bypass status.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n *      RT_ERR_ENABLE       - Invalid IFG parameter\n * Note:\n *\n *      This API can set per-port bypass stomr filter control frame type including RMA and igmp.\n *      The bypass frame type is as following:\n *      - BYPASS_BRG_GROUP,\n *      - BYPASS_FD_PAUSE,\n *      - BYPASS_SP_MCAST,\n *      - BYPASS_1X_PAE,\n *      - BYPASS_UNDEF_BRG_04,\n *      - BYPASS_UNDEF_BRG_05,\n *      - BYPASS_UNDEF_BRG_06,\n *      - BYPASS_UNDEF_BRG_07,\n *      - BYPASS_PROVIDER_BRIDGE_GROUP_ADDRESS,\n *      - BYPASS_UNDEF_BRG_09,\n *      - BYPASS_UNDEF_BRG_0A,\n *      - BYPASS_UNDEF_BRG_0B,\n *      - BYPASS_UNDEF_BRG_0C,\n *      - BYPASS_PROVIDER_BRIDGE_GVRP_ADDRESS,\n *      - BYPASS_8021AB,\n *      - BYPASS_UNDEF_BRG_0F,\n *      - BYPASS_BRG_MNGEMENT,\n *      - BYPASS_UNDEFINED_11,\n *      - BYPASS_UNDEFINED_12,\n *      - BYPASS_UNDEFINED_13,\n *      - BYPASS_UNDEFINED_14,\n *      - BYPASS_UNDEFINED_15,\n *      - BYPASS_UNDEFINED_16,\n *      - BYPASS_UNDEFINED_17,\n *      - BYPASS_UNDEFINED_18,\n *      - BYPASS_UNDEFINED_19,\n *      - BYPASS_UNDEFINED_1A,\n *      - BYPASS_UNDEFINED_1B,\n *      - BYPASS_UNDEFINED_1C,\n *      - BYPASS_UNDEFINED_1D,\n *      - BYPASS_UNDEFINED_1E,\n *      - BYPASS_UNDEFINED_1F,\n *      - BYPASS_GMRP,\n *      - BYPASS_GVRP,\n *      - BYPASS_UNDEF_GARP_22,\n *      - BYPASS_UNDEF_GARP_23,\n *      - BYPASS_UNDEF_GARP_24,\n *      - BYPASS_UNDEF_GARP_25,\n *      - BYPASS_UNDEF_GARP_26,\n *      - BYPASS_UNDEF_GARP_27,\n *      - BYPASS_UNDEF_GARP_28,\n *      - BYPASS_UNDEF_GARP_29,\n *      - BYPASS_UNDEF_GARP_2A,\n *      - BYPASS_UNDEF_GARP_2B,\n *      - BYPASS_UNDEF_GARP_2C,\n *      - BYPASS_UNDEF_GARP_2D,\n *      - BYPASS_UNDEF_GARP_2E,\n *      - BYPASS_UNDEF_GARP_2F,\n *      - BYPASS_IGMP.\n */\nextern rtk_api_ret_t rtk_storm_bypass_set(rtk_storm_bypass_t type, rtk_enable_t enable);\n\n/* Function Name:\n *      rtk_storm_bypass_get\n * Description:\n *      Get bypass storm filter control configuration.\n * Input:\n *      type - Bypass storm filter control type.\n * Output:\n *      pEnable - Bypass status.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n * Note:\n *      This API can get per-port bypass stomr filter control frame type including RMA and igmp.\n *      The bypass frame type is as following:\n *      - BYPASS_BRG_GROUP,\n *      - BYPASS_FD_PAUSE,\n *      - BYPASS_SP_MCAST,\n *      - BYPASS_1X_PAE,\n *      - BYPASS_UNDEF_BRG_04,\n *      - BYPASS_UNDEF_BRG_05,\n *      - BYPASS_UNDEF_BRG_06,\n *      - BYPASS_UNDEF_BRG_07,\n *      - BYPASS_PROVIDER_BRIDGE_GROUP_ADDRESS,\n *      - BYPASS_UNDEF_BRG_09,\n *      - BYPASS_UNDEF_BRG_0A,\n *      - BYPASS_UNDEF_BRG_0B,\n *      - BYPASS_UNDEF_BRG_0C,\n *      - BYPASS_PROVIDER_BRIDGE_GVRP_ADDRESS,\n *      - BYPASS_8021AB,\n *      - BYPASS_UNDEF_BRG_0F,\n *      - BYPASS_BRG_MNGEMENT,\n *      - BYPASS_UNDEFINED_11,\n *      - BYPASS_UNDEFINED_12,\n *      - BYPASS_UNDEFINED_13,\n *      - BYPASS_UNDEFINED_14,\n *      - BYPASS_UNDEFINED_15,\n *      - BYPASS_UNDEFINED_16,\n *      - BYPASS_UNDEFINED_17,\n *      - BYPASS_UNDEFINED_18,\n *      - BYPASS_UNDEFINED_19,\n *      - BYPASS_UNDEFINED_1A,\n *      - BYPASS_UNDEFINED_1B,\n *      - BYPASS_UNDEFINED_1C,\n *      - BYPASS_UNDEFINED_1D,\n *      - BYPASS_UNDEFINED_1E,\n *      - BYPASS_UNDEFINED_1F,\n *      - BYPASS_GMRP,\n *      - BYPASS_GVRP,\n *      - BYPASS_UNDEF_GARP_22,\n *      - BYPASS_UNDEF_GARP_23,\n *      - BYPASS_UNDEF_GARP_24,\n *      - BYPASS_UNDEF_GARP_25,\n *      - BYPASS_UNDEF_GARP_26,\n *      - BYPASS_UNDEF_GARP_27,\n *      - BYPASS_UNDEF_GARP_28,\n *      - BYPASS_UNDEF_GARP_29,\n *      - BYPASS_UNDEF_GARP_2A,\n *      - BYPASS_UNDEF_GARP_2B,\n *      - BYPASS_UNDEF_GARP_2C,\n *      - BYPASS_UNDEF_GARP_2D,\n *      - BYPASS_UNDEF_GARP_2E,\n *      - BYPASS_UNDEF_GARP_2F,\n *      - BYPASS_IGMP.\n */\nextern rtk_api_ret_t rtk_storm_bypass_get(rtk_storm_bypass_t type, rtk_enable_t *pEnable);\n\n/* Function Name:\n *      rtk_rate_stormControlExtPortmask_set\n * Description:\n *      Set externsion storm control port mask\n * Input:\n *      pPortmask  - port mask\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n *      RT_ERR_NOT_INIT          - The module is not initial\n *      RT_ERR_INPUT             - invalid input parameter\n * Note:\n *\n */\nextern rtk_api_ret_t rtk_rate_stormControlExtPortmask_set(rtk_portmask_t *pPortmask);\n\n/* Function Name:\n *      rtk_rate_stormControlExtPortmask_get\n * Description:\n *      Set externsion storm control port mask\n * Input:\n *      None\n * Output:\n *      pPortmask  - port mask\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n *      RT_ERR_NOT_INIT          - The module is not initial\n *      RT_ERR_INPUT             - invalid input parameter\n * Note:\n *\n */\nextern rtk_api_ret_t rtk_rate_stormControlExtPortmask_get(rtk_portmask_t *pPortmask);\n\n/* Function Name:\n *      rtk_rate_stormControlExtEnable_set\n * Description:\n *      Set externsion storm control state\n * Input:\n *      stormType   - storm group type\n *      enable      - externsion storm control state\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n *      RT_ERR_NOT_INIT          - The module is not initial\n *      RT_ERR_INPUT             - invalid input parameter\n * Note:\n *\n */\nextern rtk_api_ret_t rtk_rate_stormControlExtEnable_set(rtk_rate_storm_group_t stormType, rtk_enable_t enable);\n\n/* Function Name:\n *      rtk_rate_stormControlExtEnable_get\n * Description:\n *      Get externsion storm control state\n * Input:\n *      stormType   - storm group type\n * Output:\n *      pEnable     - externsion storm control state\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n *      RT_ERR_NOT_INIT          - The module is not initial\n *      RT_ERR_INPUT             - invalid input parameter\n * Note:\n *\n */\nextern rtk_api_ret_t rtk_rate_stormControlExtEnable_get(rtk_rate_storm_group_t stormType, rtk_enable_t *pEnable);\n\n/* Function Name:\n *      rtk_rate_stormControlExtMeterIdx_set\n * Description:\n *      Set externsion storm control meter index\n * Input:\n *      stormType   - storm group type\n *      index       - externsion storm control state\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n *      RT_ERR_NOT_INIT          - The module is not initial\n *      RT_ERR_INPUT             - invalid input parameter\n * Note:\n *\n */\nextern rtk_api_ret_t rtk_rate_stormControlExtMeterIdx_set(rtk_rate_storm_group_t stormType, rtk_uint32 index);\n\n/* Function Name:\n *      rtk_rate_stormControlExtMeterIdx_get\n * Description:\n *      Get externsion storm control meter index\n * Input:\n *      stormType   - storm group type\n *      pIndex      - externsion storm control state\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n *      RT_ERR_NOT_INIT          - The module is not initial\n *      RT_ERR_INPUT             - invalid input parameter\n * Note:\n *\n */\nextern rtk_api_ret_t rtk_rate_stormControlExtMeterIdx_get(rtk_rate_storm_group_t stormType, rtk_uint32 *pIndex);\n\n\n\n#endif /* __RTK_API_STORM_H__ */\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/svlan.h",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * Purpose : RTL8367/RTL8367C switch high-level API\n *\n * Feature : The file includes SVLAN module high-layer API defination\n *\n */\n\n#ifndef __RTK_API_SVLAN_H__\n#define __RTK_API_SVLAN_H__\n\ntypedef rtk_uint32 rtk_svlan_index_t;\n\ntypedef struct rtk_svlan_memberCfg_s{\n    rtk_uint32 svid;\n    rtk_portmask_t memberport;\n    rtk_portmask_t untagport;\n    rtk_uint32 fiden;\n    rtk_uint32 fid;\n    rtk_uint32 priority;\n    rtk_uint32 efiden;\n    rtk_uint32 efid;\n}rtk_svlan_memberCfg_t;\n\ntypedef enum rtk_svlan_pri_ref_e\n{\n    REF_INTERNAL_PRI = 0,\n    REF_CTAG_PRI,\n    REF_SVLAN_PRI,\n    REF_PB_PRI,\n    REF_PRI_END\n} rtk_svlan_pri_ref_t;\n\n\ntypedef rtk_uint32 rtk_svlan_tpid_t;\n\ntypedef enum rtk_svlan_untag_action_e\n{\n    UNTAG_DROP = 0,\n    UNTAG_TRAP,\n    UNTAG_ASSIGN,\n    UNTAG_END\n} rtk_svlan_untag_action_t;\n\ntypedef enum rtk_svlan_unmatch_action_e\n{\n    UNMATCH_DROP = 0,\n    UNMATCH_TRAP,\n    UNMATCH_ASSIGN,\n    UNMATCH_END\n} rtk_svlan_unmatch_action_t;\n\ntypedef enum rtk_svlan_unassign_action_e\n{\n    UNASSIGN_PBSVID = 0,\n    UNASSIGN_TRAP,\n    UNASSIGN_END\n} rtk_svlan_unassign_action_t;\n\n\ntypedef enum rtk_svlan_lookupType_e\n{\n    SVLAN_LOOKUP_S64MBRCGF  = 0,\n    SVLAN_LOOKUP_C4KVLAN,\n    SVLAN_LOOKUP_END,\n\n} rtk_svlan_lookupType_t;\n\n/* Function Name:\n *      rtk_svlan_init\n * Description:\n *      Initialize SVLAN Configuration\n * Input:\n *      None\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n * Note:\n *      Ether type of S-tag in 802.1ad is 0x88a8 and there are existed ether type 0x9100 and 0x9200 for Q-in-Q SLAN design.\n *      User can set mathced ether type as service provider supported protocol.\n */\nextern rtk_api_ret_t rtk_svlan_init(void);\n\n/* Function Name:\n *      rtk_svlan_servicePort_add\n * Description:\n *      Add one service port in the specified device\n * Input:\n *      port - Port id.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number.\n *      RT_ERR_INPUT        - Invalid input parameters.\n * Note:\n *      This API is setting which port is connected to provider switch. All frames receiving from this port must\n *      contain accept SVID in S-tag field.\n */\nextern rtk_api_ret_t rtk_svlan_servicePort_add(rtk_port_t port);\n\n/* Function Name:\n *      rtk_svlan_servicePort_get\n * Description:\n *      Get service ports in the specified device.\n * Input:\n *      None\n * Output:\n *      pSvlan_portmask - pointer buffer of svlan ports.\n * Return:\n *      RT_ERR_OK          - OK\n *      RT_ERR_FAILED      - Failed\n *      RT_ERR_SMI         - SMI access error\n * Note:\n *      This API is setting which port is connected to provider switch. All frames receiving from this port must\n *      contain accept SVID in S-tag field.\n */\nextern rtk_api_ret_t rtk_svlan_servicePort_get(rtk_portmask_t *pSvlan_portmask);\n\n/* Function Name:\n *      rtk_svlan_servicePort_del\n * Description:\n *      Delete one service port in the specified device\n * Input:\n *      port - Port id.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number.\n * Note:\n *      This API is removing SVLAN service port in the specified device.\n */\nextern rtk_api_ret_t rtk_svlan_servicePort_del(rtk_port_t port);\n\n/* Function Name:\n *      rtk_svlan_tpidEntry_set\n * Description:\n *      Configure accepted S-VLAN ether type.\n * Input:\n *      svlan_tag_id - Ether type of S-tag frame parsing in uplink ports.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameter.\n * Note:\n *      Ether type of S-tag in 802.1ad is 0x88a8 and there are existed ether type 0x9100 and 0x9200 for Q-in-Q SLAN design.\n *      User can set mathced ether type as service provider supported protocol.\n */\nextern rtk_api_ret_t rtk_svlan_tpidEntry_set(rtk_uint32 svlan_tag_id);\n\n/* Function Name:\n *      rtk_svlan_tpidEntry_get\n * Description:\n *      Get accepted S-VLAN ether type setting.\n * Input:\n *      None\n * Output:\n *      pSvlan_tag_id -  Ether type of S-tag frame parsing in uplink ports.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n * Note:\n *      This API is setting which port is connected to provider switch. All frames receiving from this port must\n *      contain accept SVID in S-tag field.\n */\nextern rtk_api_ret_t rtk_svlan_tpidEntry_get(rtk_uint32 *pSvlan_tag_id);\n\n/* Function Name:\n *      rtk_svlan_priorityRef_set\n * Description:\n *      Set S-VLAN upstream priority reference setting.\n * Input:\n *      ref - reference selection parameter.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameter.\n * Note:\n *      The API can set the upstream SVLAN tag priority reference source. The related priority\n *      sources are as following:\n *      - REF_INTERNAL_PRI,\n *      - REF_CTAG_PRI,\n *      - REF_SVLAN_PRI,\n *      - REF_PB_PRI.\n */\nextern rtk_api_ret_t rtk_svlan_priorityRef_set(rtk_svlan_pri_ref_t ref);\n\n/* Function Name:\n *      rtk_svlan_priorityRef_get\n * Description:\n *      Get S-VLAN upstream priority reference setting.\n * Input:\n *      None\n * Output:\n *      pRef - reference selection parameter.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n * Note:\n *      The API can get the upstream SVLAN tag priority reference source. The related priority\n *      sources are as following:\n *      - REF_INTERNAL_PRI,\n *      - REF_CTAG_PRI,\n *      - REF_SVLAN_PRI,\n *      - REF_PB_PRI\n */\nextern rtk_api_ret_t rtk_svlan_priorityRef_get(rtk_svlan_pri_ref_t *pRef);\n\n/* Function Name:\n *      rtk_svlan_memberPortEntry_set\n * Description:\n *      Configure system SVLAN member content\n * Input:\n *      svid - SVLAN id\n *      psvlan_cfg - SVLAN member configuration\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - OK\n *      RT_ERR_FAILED           - Failed\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_INPUT            - Invalid input parameter.\n *      RT_ERR_SVLAN_VID        - Invalid SVLAN VID parameter.\n *      RT_ERR_PORT_MASK        - Invalid portmask.\n *      RT_ERR_SVLAN_TABLE_FULL - SVLAN configuration is full.\n * Note:\n *      The API can set system 64 accepted s-tag frame format. Only 64 SVID S-tag frame will be accpeted\n *      to receiving from uplink ports. Other SVID S-tag frame or S-untagged frame will be droped by default setup.\n *      - rtk_svlan_memberCfg_t->svid is SVID of SVLAN member configuration.\n *      - rtk_svlan_memberCfg_t->memberport is member port mask of SVLAN member configuration.\n *      - rtk_svlan_memberCfg_t->fid is filtering database of SVLAN member configuration.\n *      - rtk_svlan_memberCfg_t->priority is priority of SVLAN member configuration.\n */\nextern rtk_api_ret_t rtk_svlan_memberPortEntry_set(rtk_uint32 svid_idx, rtk_svlan_memberCfg_t *psvlan_cfg);\n\n/* Function Name:\n *      rtk_svlan_memberPortEntry_get\n * Description:\n *      Get SVLAN member Configure.\n * Input:\n *      svid - SVLAN id\n * Output:\n *      pSvlan_cfg - SVLAN member configuration\n * Return:\n *      RT_ERR_OK                       - OK\n *      RT_ERR_FAILED                   - Failed\n *      RT_ERR_SMI                      - SMI access error\n *      RT_ERR_SVLAN_ENTRY_NOT_FOUND    - specified svlan entry not found.\n *      RT_ERR_INPUT                    - Invalid input parameters.\n * Note:\n *      The API can get system 64 accepted s-tag frame format. Only 64 SVID S-tag frame will be accpeted\n *      to receiving from uplink ports. Other SVID S-tag frame or S-untagged frame will be droped.\n */\nextern rtk_api_ret_t rtk_svlan_memberPortEntry_get(rtk_uint32 svid_idx, rtk_svlan_memberCfg_t *pSvlan_cfg);\n\n/* Function Name:\n *      rtk_svlan_memberPortEntry_adv_set\n * Description:\n *      Configure system SVLAN member by index\n * Input:\n *      idx         - Index (0 ~ 63)\n *      psvlan_cfg  - SVLAN member configuration\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - OK\n *      RT_ERR_FAILED           - Failed\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_INPUT            - Invalid input parameter.\n *      RT_ERR_SVLAN_VID        - Invalid SVLAN VID parameter.\n *      RT_ERR_PORT_MASK        - Invalid portmask.\n *      RT_ERR_SVLAN_TABLE_FULL - SVLAN configuration is full.\n * Note:\n *      The API can set system 64 accepted s-tag frame format by index.\n *      - rtk_svlan_memberCfg_t->svid is SVID of SVLAN member configuration.\n *      - rtk_svlan_memberCfg_t->memberport is member port mask of SVLAN member configuration.\n *      - rtk_svlan_memberCfg_t->fid is filtering database of SVLAN member configuration.\n *      - rtk_svlan_memberCfg_t->priority is priority of SVLAN member configuration.\n */\nextern rtk_api_ret_t rtk_svlan_memberPortEntry_adv_set(rtk_uint32 idx, rtk_svlan_memberCfg_t *pSvlan_cfg);\n\n/* Function Name:\n *      rtk_svlan_memberPortEntry_adv_get\n * Description:\n *      Get SVLAN member Configure by index.\n * Input:\n *      idx         - Index (0 ~ 63)\n * Output:\n *      pSvlan_cfg  - SVLAN member configuration\n * Return:\n *      RT_ERR_OK                       - OK\n *      RT_ERR_FAILED                   - Failed\n *      RT_ERR_SMI                      - SMI access error\n *      RT_ERR_SVLAN_ENTRY_NOT_FOUND    - specified svlan entry not found.\n *      RT_ERR_INPUT                    - Invalid input parameters.\n * Note:\n *      The API can get system 64 accepted s-tag frame format. Only 64 SVID S-tag frame will be accpeted\n *      to receiving from uplink ports. Other SVID S-tag frame or S-untagged frame will be droped.\n */\nextern rtk_api_ret_t rtk_svlan_memberPortEntry_adv_get(rtk_uint32 idx, rtk_svlan_memberCfg_t *pSvlan_cfg);\n\n/* Function Name:\n *      rtk_svlan_defaultSvlan_set\n * Description:\n *      Configure default egress SVLAN.\n * Input:\n *      port - Source port\n *      svid - SVLAN id\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK                       - OK\n *      RT_ERR_FAILED                   - Failed\n *      RT_ERR_SMI                      - SMI access error\n *      RT_ERR_INPUT                    - Invalid input parameter.\n *      RT_ERR_SVLAN_VID                - Invalid SVLAN VID parameter.\n *      RT_ERR_SVLAN_ENTRY_NOT_FOUND    - specified svlan entry not found.\n * Note:\n *      The API can set port n S-tag format index while receiving frame from port n\n *      is transmit through uplink port with s-tag field\n */\nextern rtk_api_ret_t rtk_svlan_defaultSvlan_set(rtk_port_t port, rtk_vlan_t svid);\n\n/* Function Name:\n *      rtk_svlan_defaultSvlan_get\n * Description:\n *      Get the configure default egress SVLAN.\n * Input:\n *      port - Source port\n * Output:\n *      pSvid - SVLAN VID\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n * Note:\n *      The API can get port n S-tag format index while receiving frame from port n\n *      is transmit through uplink port with s-tag field\n */\nextern rtk_api_ret_t rtk_svlan_defaultSvlan_get(rtk_port_t port, rtk_vlan_t *pSvid);\n\n/* Function Name:\n *      rtk_svlan_c2s_add\n * Description:\n *      Configure SVLAN C2S table\n * Input:\n *      vid - VLAN ID\n *      src_port - Ingress Port\n *      svid - SVLAN VID\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port ID.\n *      RT_ERR_SVLAN_VID    - Invalid SVLAN VID parameter.\n *      RT_ERR_VLAN_VID     - Invalid VID parameter.\n *      RT_ERR_OUT_OF_RANGE - input out of range.\n *      RT_ERR_INPUT        - Invalid input parameters.\n * Note:\n *      The API can set system C2S configuration. ASIC will check upstream's VID and assign related\n *      SVID to mathed packet. There are 128 SVLAN C2S configurations.\n */\nextern rtk_api_ret_t rtk_svlan_c2s_add(rtk_vlan_t vid, rtk_port_t src_port, rtk_vlan_t svid);\n\n/* Function Name:\n *      rtk_svlan_c2s_del\n * Description:\n *      Delete one C2S entry\n * Input:\n *      vid - VLAN ID\n *      src_port - Ingress Port\n *      svid - SVLAN VID\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - OK\n *      RT_ERR_FAILED           - Failed\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_VLAN_VID         - Invalid VID parameter.\n *      RT_ERR_PORT_ID          - Invalid port ID.\n *      RT_ERR_OUT_OF_RANGE     - input out of range.\n * Note:\n *      The API can delete system C2S configuration. There are 128 SVLAN C2S configurations.\n */\nextern rtk_api_ret_t rtk_svlan_c2s_del(rtk_vlan_t vid, rtk_port_t src_port);\n\n/* Function Name:\n *      rtk_svlan_c2s_get\n * Description:\n *      Get configure SVLAN C2S table\n * Input:\n *      vid - VLAN ID\n *      src_port - Ingress Port\n * Output:\n *      pSvid - SVLAN ID\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n *      RT_ERR_PORT_ID      - Invalid port ID.\n *      RT_ERR_OUT_OF_RANGE - input out of range.\n * Note:\n *     The API can get system C2S configuration. There are 128 SVLAN C2S configurations.\n */\nextern rtk_api_ret_t rtk_svlan_c2s_get(rtk_vlan_t vid, rtk_port_t src_port, rtk_vlan_t *pSvid);\n\n/* Function Name:\n *      rtk_svlan_untag_action_set\n * Description:\n *      Configure Action of downstream Un-Stag packet\n * Input:\n *      action  - Action for UnStag\n *      svid    - The SVID assigned to UnStag packet\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK                       - OK\n *      RT_ERR_FAILED                   - Failed\n *      RT_ERR_SMI                      - SMI access error\n *      RT_ERR_SVLAN_VID                - Invalid SVLAN VID parameter.\n *      RT_ERR_SVLAN_ENTRY_NOT_FOUND    - specified svlan entry not found.\n *      RT_ERR_OUT_OF_RANGE             - input out of range.\n *      RT_ERR_INPUT                    - Invalid input parameters.\n * Note:\n *      The API can configure action of downstream Un-Stag packet. A SVID assigned\n *      to the un-stag is also supported by this API. The parameter of svid is\n *      only referenced when the action is set to UNTAG_ASSIGN\n */\nextern rtk_api_ret_t rtk_svlan_untag_action_set(rtk_svlan_untag_action_t action, rtk_vlan_t svid);\n\n/* Function Name:\n *      rtk_svlan_untag_action_get\n * Description:\n *      Get Action of downstream Un-Stag packet\n * Input:\n *      None\n * Output:\n *      pAction  - Action for UnStag\n *      pSvid    - The SVID assigned to UnStag packet\n * Return:\n *      RT_ERR_OK                       - OK\n *      RT_ERR_FAILED                   - Failed\n *      RT_ERR_SMI                      - SMI access error\n *      RT_ERR_SVLAN_VID                - Invalid SVLAN VID parameter.\n *      RT_ERR_SVLAN_ENTRY_NOT_FOUND    - specified svlan entry not found.\n *      RT_ERR_OUT_OF_RANGE             - input out of range.\n *      RT_ERR_INPUT                    - Invalid input parameters.\n * Note:\n *      The API can Get action of downstream Un-Stag packet. A SVID assigned\n *      to the un-stag is also retrieved by this API. The parameter pSvid is\n *      only refernced when the action is UNTAG_ASSIGN\n */\nextern rtk_api_ret_t rtk_svlan_untag_action_get(rtk_svlan_untag_action_t *pAction, rtk_vlan_t *pSvid);\n\n/* Function Name:\n *      rtk_svlan_unmatch_action_set\n * Description:\n *      Configure Action of downstream Unmatch packet\n * Input:\n *      action  - Action for Unmatch\n *      svid    - The SVID assigned to Unmatch packet\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK                       - OK\n *      RT_ERR_FAILED                   - Failed\n *      RT_ERR_SMI                      - SMI access error\n *      RT_ERR_SVLAN_VID                - Invalid SVLAN VID parameter.\n *      RT_ERR_SVLAN_ENTRY_NOT_FOUND    - specified svlan entry not found.\n *      RT_ERR_OUT_OF_RANGE             - input out of range.\n *      RT_ERR_INPUT                    - Invalid input parameters.\n * Note:\n *      The API can configure action of downstream Un-match packet. A SVID assigned\n *      to the un-match is also supported by this API. The parameter od svid is\n *      only refernced when the action is set to UNMATCH_ASSIGN\n */\nextern rtk_api_ret_t rtk_svlan_unmatch_action_set(rtk_svlan_unmatch_action_t action, rtk_vlan_t svid);\n\n/* Function Name:\n *      rtk_svlan_unmatch_action_get\n * Description:\n *      Get Action of downstream Unmatch packet\n * Input:\n *      None\n * Output:\n *      pAction  - Action for Unmatch\n *      pSvid    - The SVID assigned to Unmatch packet\n * Return:\n *      RT_ERR_OK                       - OK\n *      RT_ERR_FAILED                   - Failed\n *      RT_ERR_SMI                      - SMI access error\n *      RT_ERR_SVLAN_VID                - Invalid SVLAN VID parameter.\n *      RT_ERR_SVLAN_ENTRY_NOT_FOUND    - specified svlan entry not found.\n *      RT_ERR_OUT_OF_RANGE             - input out of range.\n *      RT_ERR_INPUT                    - Invalid input parameters.\n * Note:\n *      The API can Get action of downstream Un-match packet. A SVID assigned\n *      to the un-match is also retrieved by this API. The parameter pSvid is\n *      only refernced when the action is UNMATCH_ASSIGN\n */\nextern rtk_api_ret_t rtk_svlan_unmatch_action_get(rtk_svlan_unmatch_action_t *pAction, rtk_vlan_t *pSvid);\n\n/* Function Name:\n *      rtk_svlan_dmac_vidsel_set\n * Description:\n *      Set DMAC CVID selection\n * Input:\n *      port    - Port\n *      enable  - state of DMAC CVID Selection\n * Output:\n *      None.\n * Return:\n *      RT_ERR_OK                       - OK\n *      RT_ERR_FAILED                   - Failed\n *      RT_ERR_SMI                      - SMI access error\n *      RT_ERR_SVLAN_VID                - Invalid SVLAN VID parameter.\n *      RT_ERR_SVLAN_ENTRY_NOT_FOUND    - specified svlan entry not found.\n *      RT_ERR_OUT_OF_RANGE             - input out of range.\n *      RT_ERR_INPUT                    - Invalid input parameters.\n * Note:\n *      This API can set DMAC CVID Selection state\n */\nextern rtk_api_ret_t rtk_svlan_dmac_vidsel_set(rtk_port_t port, rtk_enable_t enable);\n\n/* Function Name:\n *      rtk_svlan_dmac_vidsel_get\n * Description:\n *      Get DMAC CVID selection\n * Input:\n *      port    - Port\n * Output:\n *      pEnable - state of DMAC CVID Selection\n * Return:\n *      RT_ERR_OK                       - OK\n *      RT_ERR_FAILED                   - Failed\n *      RT_ERR_SMI                      - SMI access error\n *      RT_ERR_SVLAN_VID                - Invalid SVLAN VID parameter.\n *      RT_ERR_SVLAN_ENTRY_NOT_FOUND    - specified svlan entry not found.\n *      RT_ERR_OUT_OF_RANGE             - input out of range.\n *      RT_ERR_INPUT                    - Invalid input parameters.\n * Note:\n *      This API can get DMAC CVID Selection state\n */\nextern rtk_api_ret_t rtk_svlan_dmac_vidsel_get(rtk_port_t port, rtk_enable_t *pEnable);\n\n/* Function Name:\n *      rtk_svlan_ipmc2s_add\n * Description:\n *      add ip multicast address to SVLAN\n * Input:\n *      svid    - SVLAN VID\n *      ipmc    - ip multicast address\n *      ipmcMsk - ip multicast mask\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK                       - OK\n *      RT_ERR_FAILED                   - Failed\n *      RT_ERR_SMI                      - SMI access error\n *      RT_ERR_SVLAN_VID                - Invalid SVLAN VID parameter.\n *      RT_ERR_SVLAN_ENTRY_NOT_FOUND    - specified svlan entry not found.\n *      RT_ERR_OUT_OF_RANGE             - input out of range.\n *      RT_ERR_INPUT                    - Invalid input parameters.\n * Note:\n *      The API can set IP mutlicast to SVID configuration. If upstream packet is IPv4 multicast\n *      packet and DIP is matched MC2S configuration, ASIC will assign egress SVID to the packet.\n *      There are 32 SVLAN multicast configurations for IP and L2 multicast.\n */\nextern rtk_api_ret_t rtk_svlan_ipmc2s_add(ipaddr_t ipmc, ipaddr_t ipmcMsk, rtk_vlan_t svid);\n\n/* Function Name:\n *      rtk_svlan_ipmc2s_del\n * Description:\n *      delete ip multicast address to SVLAN\n * Input:\n *      ipmc    - ip multicast address\n *      ipmcMsk - ip multicast mask\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - OK\n *      RT_ERR_FAILED           - Failed\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_SVLAN_VID        - Invalid SVLAN VID parameter.\n *      RT_ERR_OUT_OF_RANGE     - input out of range.\n * Note:\n *      The API can delete IP mutlicast to SVID configuration. There are 32 SVLAN multicast configurations for IP and L2 multicast.\n */\nextern rtk_api_ret_t rtk_svlan_ipmc2s_del(ipaddr_t ipmc, ipaddr_t ipmcMsk);\n\n/* Function Name:\n *      rtk_svlan_ipmc2s_get\n * Description:\n *      Get ip multicast address to SVLAN\n * Input:\n *      ipmc    - ip multicast address\n *      ipmcMsk - ip multicast mask\n * Output:\n *      pSvid - SVLAN VID\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n *      RT_ERR_OUT_OF_RANGE - input out of range.\n * Note:\n *      The API can get IP mutlicast to SVID configuration. There are 32 SVLAN multicast configurations for IP and L2 multicast.\n */\nextern rtk_api_ret_t rtk_svlan_ipmc2s_get(ipaddr_t ipmc, ipaddr_t ipmcMsk, rtk_vlan_t *pSvid);\n\n/* Function Name:\n *      rtk_svlan_l2mc2s_add\n * Description:\n *      Add L2 multicast address to SVLAN\n * Input:\n *      mac     - L2 multicast address\n *      macMsk  - L2 multicast address mask\n *      svid    - SVLAN VID\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK                       - OK\n *      RT_ERR_FAILED                   - Failed\n *      RT_ERR_SMI                      - SMI access error\n *      RT_ERR_SVLAN_VID                - Invalid SVLAN VID parameter.\n *      RT_ERR_SVLAN_ENTRY_NOT_FOUND    - specified svlan entry not found.\n *      RT_ERR_OUT_OF_RANGE             - input out of range.\n *      RT_ERR_INPUT                    - Invalid input parameters.\n * Note:\n *      The API can set L2 Mutlicast to SVID configuration. If upstream packet is L2 multicast\n *      packet and DMAC is matched, ASIC will assign egress SVID to the packet. There are 32\n *      SVLAN multicast configurations for IP and L2 multicast.\n */\nextern rtk_api_ret_t rtk_svlan_l2mc2s_add(rtk_mac_t mac, rtk_mac_t macMsk, rtk_vlan_t svid);\n\n/* Function Name:\n *      rtk_svlan_l2mc2s_del\n * Description:\n *      delete L2 multicast address to SVLAN\n * Input:\n *      mac     - L2 multicast address\n *      macMsk  - L2 multicast address mask\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - OK\n *      RT_ERR_FAILED           - Failed\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_SVLAN_VID        - Invalid SVLAN VID parameter.\n *      RT_ERR_OUT_OF_RANGE     - input out of range.\n * Note:\n *      The API can delete Mutlicast to SVID configuration. There are 32 SVLAN multicast configurations for IP and L2 multicast.\n */\nextern rtk_api_ret_t rtk_svlan_l2mc2s_del(rtk_mac_t mac, rtk_mac_t macMsk);\n\n/* Function Name:\n *      rtk_svlan_l2mc2s_get\n * Description:\n *      Get L2 multicast address to SVLAN\n * Input:\n *      mac     - L2 multicast address\n *      macMsk  - L2 multicast address mask\n * Output:\n *      pSvid   - SVLAN VID\n * Return:\n *      RT_ERR_OK               - OK\n *      RT_ERR_FAILED           - Failed\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_INPUT            - Invalid input parameters.\n *      RT_ERR_OUT_OF_RANGE     - input out of range.\n * Note:\n *      The API can get L2 mutlicast to SVID configuration. There are 32 SVLAN multicast configurations for IP and L2 multicast.\n */\nextern rtk_api_ret_t rtk_svlan_l2mc2s_get(rtk_mac_t mac, rtk_mac_t macMsk, rtk_vlan_t *pSvid);\n\n/* Function Name:\n *      rtk_svlan_sp2c_add\n * Description:\n *      Add system SP2C configuration\n * Input:\n *      cvid        - VLAN ID\n *      dst_port    - Destination port of SVLAN to CVLAN configuration\n *      svid        - SVLAN VID\n *\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number.\n *      RT_ERR_SVLAN_VID    - Invalid SVLAN VID parameter.\n *      RT_ERR_VLAN_VID     - Invalid VID parameter.\n *      RT_ERR_OUT_OF_RANGE - input out of range.\n *      RT_ERR_INPUT        - Invalid input parameters.\n * Note:\n *      The API can add SVID & Destination Port to CVLAN configuration. The downstream frames with assigned\n *      SVID will be add C-tag with assigned CVID if the output port is the assigned destination port.\n *      There are 128 SP2C configurations.\n */\nextern rtk_api_ret_t rtk_svlan_sp2c_add(rtk_vlan_t svid, rtk_port_t dst_port, rtk_vlan_t cvid);\n\n/* Function Name:\n *      rtk_svlan_sp2c_get\n * Description:\n *      Get configure system SP2C content\n * Input:\n *      svid        - SVLAN VID\n *      dst_port    - Destination port of SVLAN to CVLAN configuration\n * Output:\n *      pCvid - VLAN ID\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n *      RT_ERR_OUT_OF_RANGE - input out of range.\n *      RT_ERR_PORT_ID      - Invalid port number.\n *      RT_ERR_SVLAN_VID    - Invalid SVLAN VID parameter.\n * Note:\n *     The API can get SVID & Destination Port to CVLAN configuration. There are 128 SP2C configurations.\n */\nextern rtk_api_ret_t rtk_svlan_sp2c_get(rtk_vlan_t svid, rtk_port_t dst_port, rtk_vlan_t *pCvid);\n\n/* Function Name:\n *      rtk_svlan_sp2c_del\n * Description:\n *      Delete system SP2C configuration\n * Input:\n *      svid        - SVLAN VID\n *      dst_port    - Destination port of SVLAN to CVLAN configuration\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number.\n *      RT_ERR_SVLAN_VID    - Invalid SVLAN VID parameter.\n *      RT_ERR_OUT_OF_RANGE - input out of range.\n * Note:\n *      The API can delete SVID & Destination Port to CVLAN configuration. There are 128 SP2C configurations.\n */\nextern rtk_api_ret_t rtk_svlan_sp2c_del(rtk_vlan_t svid, rtk_port_t dst_port);\n\n\n/* Function Name:\n *      rtk_svlan_lookupType_set\n * Description:\n *      Set lookup type of SVLAN\n * Input:\n *      type        - lookup type\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n * Note:\n *      none\n */\nextern rtk_api_ret_t rtk_svlan_lookupType_set(rtk_svlan_lookupType_t type);\n\n/* Function Name:\n *      rtk_svlan_lookupType_get\n * Description:\n *      Get lookup type of SVLAN\n * Input:\n *      pType       - lookup type\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n * Note:\n *      none\n */\nextern rtk_api_ret_t rtk_svlan_lookupType_get(rtk_svlan_lookupType_t *pType);\n\n/* Function Name:\n *      rtk_svlan_trapPri_set\n * Description:\n *      Set svlan trap priority\n * Input:\n *      priority - priority for trap packets\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n *      RT_ERR_QOS_INT_PRIORITY\n * Note:\n *      None\n */\nextern rtk_api_ret_t rtk_svlan_trapPri_set(rtk_pri_t priority);\n\n/* Function Name:\n *      rtk_svlan_trapPri_get\n * Description:\n *      Get svlan trap priority\n * Input:\n *      None\n * Output:\n *      pPriority - priority for trap packets\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n *      RT_ERR_NULL_POINTER - input parameter may be null pointer\n * Note:\n *      None\n */\nextern rtk_api_ret_t rtk_svlan_trapPri_get(rtk_pri_t *pPriority);\n\n/* Function Name:\n *      rtk_svlan_unassign_action_set\n * Description:\n *      Configure Action of upstream without svid assign action\n * Input:\n *      action  - Action for Un-assign\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK                       - OK\n *      RT_ERR_FAILED                   - Failed\n *      RT_ERR_OUT_OF_RANGE             - input out of range.\n *      RT_ERR_INPUT                    - Invalid input parameters.\n * Note:\n *      The API can configure action of upstream Un-assign svid packet. If action is not\n *      trap to CPU, the port-based SVID sure be assign as system need\n */\nextern rtk_api_ret_t rtk_svlan_unassign_action_set(rtk_svlan_unassign_action_t action);\n\n/* Function Name:\n *      rtk_svlan_unassign_action_get\n * Description:\n *      Get action of upstream without svid assignment\n * Input:\n *      None\n * Output:\n *      pAction  - Action for Un-assign\n * Return:\n *      RT_ERR_OK                       - OK\n *      RT_ERR_FAILED                   - Failed\n * Note:\n *      None\n */\nextern rtk_api_ret_t rtk_svlan_unassign_action_get(rtk_svlan_unassign_action_t *pAction);\n\n\n/* Function Name:\n *      rtk_svlan_checkAndCreateMbr\n * Description:\n *      Check and create Member configuration and return index\n * Input:\n *      vid  - VLAN id.\n * Output:\n *      pIndex  - Member configuration index\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_VLAN_VID     - Invalid VLAN ID.\n *      RT_ERR_TBL_FULL     - Member Configuration table full\n * Note:\n *\n */\nextern rtk_api_ret_t rtk_svlan_checkAndCreateMbr(rtk_vlan_t vid, rtk_uint32 *pIndex);\n\n\n#endif /* __RTK_API_SVLAN_H__ */\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/trap.h",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * Purpose : RTL8367/RTL8367C switch high-level API\n *\n * Feature : The file includes Trap module high-layer API defination\n *\n */\n\n#ifndef __RTK_API_TRAP_H__\n#define __RTK_API_TRAP_H__\n\n\ntypedef enum rtk_trap_type_e\n{\n    TRAP_BRG_GROUP = 0,\n    TRAP_FD_PAUSE,\n    TRAP_SP_MCAST,\n    TRAP_1X_PAE,\n    TRAP_UNDEF_BRG_04,\n    TRAP_UNDEF_BRG_05,\n    TRAP_UNDEF_BRG_06,\n    TRAP_UNDEF_BRG_07,\n    TRAP_PROVIDER_BRIDGE_GROUP_ADDRESS,\n    TRAP_UNDEF_BRG_09,\n    TRAP_UNDEF_BRG_0A,\n    TRAP_UNDEF_BRG_0B,\n    TRAP_UNDEF_BRG_0C,\n    TRAP_PROVIDER_BRIDGE_GVRP_ADDRESS,\n    TRAP_8021AB,\n    TRAP_UNDEF_BRG_0F,\n    TRAP_BRG_MNGEMENT,\n    TRAP_UNDEFINED_11,\n    TRAP_UNDEFINED_12,\n    TRAP_UNDEFINED_13,\n    TRAP_UNDEFINED_14,\n    TRAP_UNDEFINED_15,\n    TRAP_UNDEFINED_16,\n    TRAP_UNDEFINED_17,\n    TRAP_UNDEFINED_18,\n    TRAP_UNDEFINED_19,\n    TRAP_UNDEFINED_1A,\n    TRAP_UNDEFINED_1B,\n    TRAP_UNDEFINED_1C,\n    TRAP_UNDEFINED_1D,\n    TRAP_UNDEFINED_1E,\n    TRAP_UNDEFINED_1F,\n    TRAP_GMRP,\n    TRAP_GVRP,\n    TRAP_UNDEF_GARP_22,\n    TRAP_UNDEF_GARP_23,\n    TRAP_UNDEF_GARP_24,\n    TRAP_UNDEF_GARP_25,\n    TRAP_UNDEF_GARP_26,\n    TRAP_UNDEF_GARP_27,\n    TRAP_UNDEF_GARP_28,\n    TRAP_UNDEF_GARP_29,\n    TRAP_UNDEF_GARP_2A,\n    TRAP_UNDEF_GARP_2B,\n    TRAP_UNDEF_GARP_2C,\n    TRAP_UNDEF_GARP_2D,\n    TRAP_UNDEF_GARP_2E,\n    TRAP_UNDEF_GARP_2F,\n    TRAP_CDP,\n    TRAP_CSSTP,\n    TRAP_LLDP,\n    TRAP_END,\n}rtk_trap_type_t;\n\n\ntypedef enum rtk_mcast_type_e\n{\n    MCAST_L2 = 0,\n    MCAST_IPV4,\n    MCAST_IPV6,\n    MCAST_END\n} rtk_mcast_type_t;\n\ntypedef enum rtk_trap_mcast_action_e\n{\n    MCAST_ACTION_FORWARD = 0,\n    MCAST_ACTION_DROP,\n    MCAST_ACTION_TRAP2CPU,\n    MCAST_ACTION_ROUTER_PORT,\n    MCAST_ACTION_DROP_EX_RMA,\n    MCAST_ACTION_END\n} rtk_trap_mcast_action_t;\n\ntypedef enum rtk_trap_rma_action_e\n{\n    RMA_ACTION_FORWARD = 0,\n    RMA_ACTION_TRAP2CPU,\n    RMA_ACTION_DROP,\n    RMA_ACTION_FORWARD_EXCLUDE_CPU,\n    RMA_ACTION_END\n} rtk_trap_rma_action_t;\n\ntypedef enum rtk_trap_ucast_action_e\n{\n    UCAST_ACTION_FORWARD_PMASK = 0,\n    UCAST_ACTION_DROP,\n    UCAST_ACTION_TRAP2CPU,\n    UCAST_ACTION_FLOODING,\n    UCAST_ACTION_END\n} rtk_trap_ucast_action_t;\n\ntypedef enum rtk_trap_ucast_type_e\n{\n    UCAST_UNKNOWNDA = 0,\n    UCAST_UNKNOWNSA,\n    UCAST_UNMATCHSA,\n    UCAST_END\n} rtk_trap_ucast_type_t;\n\ntypedef enum rtk_trap_reason_type_e\n{\n    TRAP_REASON_RMA = 0,\n    TRAP_REASON_OAM,\n    TRAP_REASON_1XUNAUTH,\n    TRAP_REASON_VLANSTACK,\n    TRAP_REASON_UNKNOWNMC,\n    TRAP_REASON_END,\n} rtk_trap_reason_type_t;\n\n\n/* Function Name:\n *      rtk_trap_unknownUnicastPktAction_set\n * Description:\n *      Set unknown unicast packet action configuration.\n * Input:\n *      port            - ingress port ID for unknown unicast packet\n *      ucast_action    - Unknown unicast action.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK                  - OK\n *      RT_ERR_FAILED              - Failed\n *      RT_ERR_SMI                 - SMI access error\n *      RT_ERR_NOT_ALLOWED         - Invalid action.\n *      RT_ERR_INPUT               - Invalid input parameters.\n * Note:\n *      This API can set unknown unicast packet action configuration.\n *      The unknown unicast action is as following:\n *          - UCAST_ACTION_FORWARD_PMASK\n *          - UCAST_ACTION_DROP\n *          - UCAST_ACTION_TRAP2CPU\n *          - UCAST_ACTION_FLOODING\n */\nrtk_api_ret_t rtk_trap_unknownUnicastPktAction_set(rtk_port_t port, rtk_trap_ucast_action_t ucast_action);\n\n/* Function Name:\n *      rtk_trap_unknownUnicastPktAction_get\n * Description:\n *      Get unknown unicast packet action configuration.\n * Input:\n *      port            - ingress port ID for unknown unicast packet\n * Output:\n *      pUcast_action   - Unknown unicast action.\n * Return:\n *      RT_ERR_OK                  - OK\n *      RT_ERR_FAILED              - Failed\n *      RT_ERR_SMI                 - SMI access error\n *      RT_ERR_NOT_ALLOWED         - Invalid action.\n *      RT_ERR_INPUT               - Invalid input parameters.\n *      RT_ERR_NULL_POINTER        - Null pointer\n * Note:\n *      This API can get unknown unicast packet action configuration.\n *      The unknown unicast action is as following:\n *          - UCAST_ACTION_FORWARD_PMASK\n *          - UCAST_ACTION_DROP\n *          - UCAST_ACTION_TRAP2CPU\n *          - UCAST_ACTION_FLOODING\n */\nrtk_api_ret_t rtk_trap_unknownUnicastPktAction_get(rtk_port_t port, rtk_trap_ucast_action_t *pUcast_action);\n\n/* Function Name:\n *      rtk_trap_unknownMacPktAction_set\n * Description:\n *      Set unknown source MAC packet action configuration.\n * Input:\n *      ucast_action    - Unknown source MAC action.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK                  - OK\n *      RT_ERR_FAILED              - Failed\n *      RT_ERR_SMI                 - SMI access error\n *      RT_ERR_NOT_ALLOWED         - Invalid action.\n *      RT_ERR_INPUT               - Invalid input parameters.\n * Note:\n *      This API can set unknown unicast packet action configuration.\n *      The unknown unicast action is as following:\n *          - UCAST_ACTION_FORWARD_PMASK\n *          - UCAST_ACTION_DROP\n *          - UCAST_ACTION_TRAP2CPU\n */\nextern rtk_api_ret_t rtk_trap_unknownMacPktAction_set(rtk_trap_ucast_action_t ucast_action);\n\n/* Function Name:\n *      rtk_trap_unknownMacPktAction_get\n * Description:\n *      Get unknown source MAC packet action configuration.\n * Input:\n *      None.\n * Output:\n *      pUcast_action   - Unknown source MAC action.\n * Return:\n *      RT_ERR_OK                  - OK\n *      RT_ERR_FAILED              - Failed\n *      RT_ERR_SMI                 - SMI access error\n *      RT_ERR_NULL_POINTER        - Null Pointer.\n *      RT_ERR_INPUT               - Invalid input parameters.\n * Note:\n *\n */\nextern rtk_api_ret_t rtk_trap_unknownMacPktAction_get(rtk_trap_ucast_action_t *pUcast_action);\n\n/* Function Name:\n *      rtk_trap_unmatchMacPktAction_set\n * Description:\n *      Set unmatch source MAC packet action configuration.\n * Input:\n *      ucast_action    - Unknown source MAC action.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK                  - OK\n *      RT_ERR_FAILED              - Failed\n *      RT_ERR_SMI                 - SMI access error\n *      RT_ERR_NOT_ALLOWED         - Invalid action.\n *      RT_ERR_INPUT               - Invalid input parameters.\n * Note:\n *      This API can set unknown unicast packet action configuration.\n *      The unknown unicast action is as following:\n *          - UCAST_ACTION_FORWARD_PMASK\n *          - UCAST_ACTION_DROP\n *          - UCAST_ACTION_TRAP2CPU\n */\nextern rtk_api_ret_t rtk_trap_unmatchMacPktAction_set(rtk_trap_ucast_action_t ucast_action);\n\n/* Function Name:\n *      rtk_trap_unmatchMacPktAction_get\n * Description:\n *      Get unmatch source MAC packet action configuration.\n * Input:\n *      None.\n * Output:\n *      pUcast_action   - Unknown source MAC action.\n * Return:\n *      RT_ERR_OK                  - OK\n *      RT_ERR_FAILED              - Failed\n *      RT_ERR_SMI                 - SMI access error\n *      RT_ERR_NOT_ALLOWED         - Invalid action.\n *      RT_ERR_INPUT               - Invalid input parameters.\n * Note:\n *      This API can set unknown unicast packet action configuration.\n *      The unknown unicast action is as following:\n *          - UCAST_ACTION_FORWARD_PMASK\n *          - UCAST_ACTION_DROP\n *          - UCAST_ACTION_TRAP2CPU\n */\nextern rtk_api_ret_t rtk_trap_unmatchMacPktAction_get(rtk_trap_ucast_action_t *pUcast_action);\n\n/* Function Name:\n *      rtk_trap_unmatchMacMoving_set\n * Description:\n *      Set unmatch source MAC packet moving state.\n * Input:\n *      port        - Port ID.\n *      enable      - ENABLED: allow SA moving, DISABLE: don't allow SA moving.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK                  - OK\n *      RT_ERR_FAILED              - Failed\n *      RT_ERR_SMI                 - SMI access error\n *      RT_ERR_NOT_ALLOWED         - Invalid action.\n *      RT_ERR_INPUT               - Invalid input parameters.\n * Note:\n */\nextern rtk_api_ret_t rtk_trap_unmatchMacMoving_set(rtk_port_t port, rtk_enable_t enable);\n\n/* Function Name:\n *      rtk_trap_unmatchMacMoving_get\n * Description:\n *      Set unmatch source MAC packet moving state.\n * Input:\n *      port        - Port ID.\n * Output:\n *      pEnable     - ENABLED: allow SA moving, DISABLE: don't allow SA moving.\n * Return:\n *      RT_ERR_OK                  - OK\n *      RT_ERR_FAILED              - Failed\n *      RT_ERR_SMI                 - SMI access error\n *      RT_ERR_NOT_ALLOWED         - Invalid action.\n *      RT_ERR_INPUT               - Invalid input parameters.\n * Note:\n */\nextern rtk_api_ret_t rtk_trap_unmatchMacMoving_get(rtk_port_t port, rtk_enable_t *pEnable);\n\n/* Function Name:\n *      rtk_trap_unknownMcastPktAction_set\n * Description:\n *      Set behavior of unknown multicast\n * Input:\n *      port            - Port id.\n *      type            - unknown multicast packet type.\n *      mcast_action    - unknown multicast action.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number.\n *      RT_ERR_NOT_ALLOWED  - Invalid action.\n *      RT_ERR_INPUT        - Invalid input parameters.\n * Note:\n *      When receives an unknown multicast packet, switch may trap, drop or flood this packet\n *      (1) The unknown multicast packet type is as following:\n *          - MCAST_L2\n *          - MCAST_IPV4\n *          - MCAST_IPV6\n *      (2) The unknown multicast action is as following:\n *          - MCAST_ACTION_FORWARD\n *          - MCAST_ACTION_DROP\n *          - MCAST_ACTION_TRAP2CPU\n */\nextern rtk_api_ret_t rtk_trap_unknownMcastPktAction_set(rtk_port_t port, rtk_mcast_type_t type, rtk_trap_mcast_action_t mcast_action);\n\n/* Function Name:\n *      rtk_trap_unknownMcastPktAction_get\n * Description:\n *      Get behavior of unknown multicast\n * Input:\n *      type - unknown multicast packet type.\n * Output:\n *      pMcast_action - unknown multicast action.\n * Return:\n *      RT_ERR_OK               - OK\n *      RT_ERR_FAILED           - Failed\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_PORT_ID          - Invalid port number.\n *      RT_ERR_NOT_ALLOWED      - Invalid operation.\n *      RT_ERR_INPUT            - Invalid input parameters.\n * Note:\n *      When receives an unknown multicast packet, switch may trap, drop or flood this packet\n *      (1) The unknown multicast packet type is as following:\n *          - MCAST_L2\n *          - MCAST_IPV4\n *          - MCAST_IPV6\n *      (2) The unknown multicast action is as following:\n *          - MCAST_ACTION_FORWARD\n *          - MCAST_ACTION_DROP\n *          - MCAST_ACTION_TRAP2CPU\n */\nextern rtk_api_ret_t rtk_trap_unknownMcastPktAction_get(rtk_port_t port, rtk_mcast_type_t type, rtk_trap_mcast_action_t *pMcast_action);\n\n/* Function Name:\n *      rtk_trap_lldpEnable_set\n * Description:\n *      Set LLDP enable.\n * Input:\n *      enabled - LLDP enable, 0: follow RMA, 1: use LLDP action.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - OK\n *      RT_ERR_FAILED           - Failed\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_NOT_ALLOWED      - Invalid action.\n *      RT_ERR_INPUT            - Invalid input parameters.\n * Note:\n *      - DMAC                                                 Assignment\n *      - 01:80:c2:00:00:0e ethertype = 0x88CC    LLDP\n *      - 01:80:c2:00:00:03 ethertype = 0x88CC\n *      - 01:80:c2:00:00:00 ethertype = 0x88CC\n\n */\nextern rtk_api_ret_t rtk_trap_lldpEnable_set(rtk_enable_t enabled);\n\n/* Function Name:\n *      rtk_trap_lldpEnable_get\n * Description:\n *      Get LLDP status.\n * Input:\n *      None\n * Output:\n *      pEnabled - LLDP enable, 0: follow RMA, 1: use LLDP action.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n * Note:\n *      LLDP is as following definition.\n *      - DMAC                                                 Assignment\n *      - 01:80:c2:00:00:0e ethertype = 0x88CC    LLDP\n *      - 01:80:c2:00:00:03 ethertype = 0x88CC\n *      - 01:80:c2:00:00:00 ethertype = 0x88CC\n */\nextern rtk_api_ret_t rtk_trap_lldpEnable_get(rtk_enable_t *pEnabled);\n\n/* Function Name:\n *      rtk_trap_reasonTrapToCpuPriority_set\n * Description:\n *      Set priority value of a packet that trapped to CPU port according to specific reason.\n * Input:\n *      type     - reason that trap to CPU port.\n *      priority - internal priority that is going to be set for specific trap reason.\n * Output:\n *      None.\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n *      RT_ERR_NOT_INIT - The module is not initial\n *      RT_ERR_INPUT    - Invalid input parameter\n * Note:\n *      Currently the trap reason that supported are listed as follows:\n *      - TRAP_REASON_RMA\n *      - TRAP_REASON_OAM\n *      - TRAP_REASON_1XUNAUTH\n *      - TRAP_REASON_VLANSTACK\n *      - TRAP_REASON_UNKNOWNMC\n */\nextern rtk_api_ret_t rtk_trap_reasonTrapToCpuPriority_set(rtk_trap_reason_type_t type, rtk_pri_t priority);\n\n/* Function Name:\n *      rtk_trap_reasonTrapToCpuPriority_get\n * Description:\n *      Get priority value of a packet that trapped to CPU port according to specific reason.\n * Input:\n *      type      - reason that trap to CPU port.\n * Output:\n *      pPriority - configured internal priority for such reason.\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n *      RT_ERR_NOT_INIT     - The module is not initial\n *      RT_ERR_INPUT        - Invalid input parameter\n *      RT_ERR_NULL_POINTER - NULL pointer\n * Note:\n *      Currently the trap reason that supported are listed as follows:\n *      - TRAP_REASON_RMA\n *      - TRAP_REASON_OAM\n *      - TRAP_REASON_1XUNAUTH\n *      - TRAP_REASON_VLANSTACK\n *      - TRAP_REASON_UNKNOWNMC\n */\nextern rtk_api_ret_t rtk_trap_reasonTrapToCpuPriority_get(rtk_trap_reason_type_t type, rtk_pri_t *pPriority);\n\n/* Function Name:\n *      rtk_trap_rmaAction_set\n * Description:\n *      Set Reserved multicast address action configuration.\n * Input:\n *      type    - rma type.\n *      rma_action - RMA action.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n *      RT_ERR_ENABLE       - Invalid IFG parameter\n * Note:\n *\n *      There are 48 types of Reserved Multicast Address frame for application usage.\n *      (1)They are as following definition.\n *      - TRAP_BRG_GROUP,\n *      - TRAP_FD_PAUSE,\n *      - TRAP_SP_MCAST,\n *      - TRAP_1X_PAE,\n *      - TRAP_UNDEF_BRG_04,\n *      - TRAP_UNDEF_BRG_05,\n *      - TRAP_UNDEF_BRG_06,\n *      - TRAP_UNDEF_BRG_07,\n *      - TRAP_PROVIDER_BRIDGE_GROUP_ADDRESS,\n *      - TRAP_UNDEF_BRG_09,\n *      - TRAP_UNDEF_BRG_0A,\n *      - TRAP_UNDEF_BRG_0B,\n *      - TRAP_UNDEF_BRG_0C,\n *      - TRAP_PROVIDER_BRIDGE_GVRP_ADDRESS,\n *      - TRAP_8021AB,\n *      - TRAP_UNDEF_BRG_0F,\n *      - TRAP_BRG_MNGEMENT,\n *      - TRAP_UNDEFINED_11,\n *      - TRAP_UNDEFINED_12,\n *      - TRAP_UNDEFINED_13,\n *      - TRAP_UNDEFINED_14,\n *      - TRAP_UNDEFINED_15,\n *      - TRAP_UNDEFINED_16,\n *      - TRAP_UNDEFINED_17,\n *      - TRAP_UNDEFINED_18,\n *      - TRAP_UNDEFINED_19,\n *      - TRAP_UNDEFINED_1A,\n *      - TRAP_UNDEFINED_1B,\n *      - TRAP_UNDEFINED_1C,\n *      - TRAP_UNDEFINED_1D,\n *      - TRAP_UNDEFINED_1E,\n *      - TRAP_UNDEFINED_1F,\n *      - TRAP_GMRP,\n *      - TRAP_GVRP,\n *      - TRAP_UNDEF_GARP_22,\n *      - TRAP_UNDEF_GARP_23,\n *      - TRAP_UNDEF_GARP_24,\n *      - TRAP_UNDEF_GARP_25,\n *      - TRAP_UNDEF_GARP_26,\n *      - TRAP_UNDEF_GARP_27,\n *      - TRAP_UNDEF_GARP_28,\n *      - TRAP_UNDEF_GARP_29,\n *      - TRAP_UNDEF_GARP_2A,\n *      - TRAP_UNDEF_GARP_2B,\n *      - TRAP_UNDEF_GARP_2C,\n *      - TRAP_UNDEF_GARP_2D,\n *      - TRAP_UNDEF_GARP_2E,\n *      - TRAP_UNDEF_GARP_2F,\n *      - TRAP_CDP.\n *      - TRAP_CSSTP.\n *      - TRAP_LLDP.\n *      (2) The RMA action is as following:\n *      - RMA_ACTION_FORWARD\n *      - RMA_ACTION_TRAP2CPU\n *      - RMA_ACTION_DROP\n *      - RMA_ACTION_FORWARD_EXCLUDE_CPU\n */\nextern rtk_api_ret_t rtk_trap_rmaAction_set(rtk_trap_type_t type, rtk_trap_rma_action_t rma_action);\n\n/* Function Name:\n *      rtk_trap_rmaAction_get\n * Description:\n *      Get Reserved multicast address action configuration.\n * Input:\n *      type - rma type.\n * Output:\n *      pRma_action - RMA action.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n * Note:\n *      There are 48 types of Reserved Multicast Address frame for application usage.\n *      (1)They are as following definition.\n *      - TRAP_BRG_GROUP,\n *      - TRAP_FD_PAUSE,\n *      - TRAP_SP_MCAST,\n *      - TRAP_1X_PAE,\n *      - TRAP_UNDEF_BRG_04,\n *      - TRAP_UNDEF_BRG_05,\n *      - TRAP_UNDEF_BRG_06,\n *      - TRAP_UNDEF_BRG_07,\n *      - TRAP_PROVIDER_BRIDGE_GROUP_ADDRESS,\n *      - TRAP_UNDEF_BRG_09,\n *      - TRAP_UNDEF_BRG_0A,\n *      - TRAP_UNDEF_BRG_0B,\n *      - TRAP_UNDEF_BRG_0C,\n *      - TRAP_PROVIDER_BRIDGE_GVRP_ADDRESS,\n *      - TRAP_8021AB,\n *      - TRAP_UNDEF_BRG_0F,\n *      - TRAP_BRG_MNGEMENT,\n *      - TRAP_UNDEFINED_11,\n *      - TRAP_UNDEFINED_12,\n *      - TRAP_UNDEFINED_13,\n *      - TRAP_UNDEFINED_14,\n *      - TRAP_UNDEFINED_15,\n *      - TRAP_UNDEFINED_16,\n *      - TRAP_UNDEFINED_17,\n *      - TRAP_UNDEFINED_18,\n *      - TRAP_UNDEFINED_19,\n *      - TRAP_UNDEFINED_1A,\n *      - TRAP_UNDEFINED_1B,\n *      - TRAP_UNDEFINED_1C,\n *      - TRAP_UNDEFINED_1D,\n *      - TRAP_UNDEFINED_1E,\n *      - TRAP_UNDEFINED_1F,\n *      - TRAP_GMRP,\n *      - TRAP_GVRP,\n *      - TRAP_UNDEF_GARP_22,\n *      - TRAP_UNDEF_GARP_23,\n *      - TRAP_UNDEF_GARP_24,\n *      - TRAP_UNDEF_GARP_25,\n *      - TRAP_UNDEF_GARP_26,\n *      - TRAP_UNDEF_GARP_27,\n *      - TRAP_UNDEF_GARP_28,\n *      - TRAP_UNDEF_GARP_29,\n *      - TRAP_UNDEF_GARP_2A,\n *      - TRAP_UNDEF_GARP_2B,\n *      - TRAP_UNDEF_GARP_2C,\n *      - TRAP_UNDEF_GARP_2D,\n *      - TRAP_UNDEF_GARP_2E,\n *      - TRAP_UNDEF_GARP_2F,\n *      - TRAP_CDP.\n *      - TRAP_CSSTP.\n *      - TRAP_LLDP.\n *      (2) The RMA action is as following:\n *      - RMA_ACTION_FORWARD\n *      - RMA_ACTION_TRAP2CPU\n *      - RMA_ACTION_DROP\n *      - RMA_ACTION_FORWARD_EXCLUDE_CPU\n */\nextern rtk_api_ret_t rtk_trap_rmaAction_get(rtk_trap_type_t type, rtk_trap_rma_action_t *pRma_action);\n\n/* Function Name:\n *      rtk_trap_rmaKeepFormat_set\n * Description:\n *      Set Reserved multicast address keep format configuration.\n * Input:\n *      type    - rma type.\n *      enable - enable keep format.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n *      RT_ERR_ENABLE       - Invalid IFG parameter\n * Note:\n *\n *      There are 48 types of Reserved Multicast Address frame for application usage.\n *      They are as following definition.\n *      - TRAP_BRG_GROUP,\n *      - TRAP_FD_PAUSE,\n *      - TRAP_SP_MCAST,\n *      - TRAP_1X_PAE,\n *      - TRAP_UNDEF_BRG_04,\n *      - TRAP_UNDEF_BRG_05,\n *      - TRAP_UNDEF_BRG_06,\n *      - TRAP_UNDEF_BRG_07,\n *      - TRAP_PROVIDER_BRIDGE_GROUP_ADDRESS,\n *      - TRAP_UNDEF_BRG_09,\n *      - TRAP_UNDEF_BRG_0A,\n *      - TRAP_UNDEF_BRG_0B,\n *      - TRAP_UNDEF_BRG_0C,\n *      - TRAP_PROVIDER_BRIDGE_GVRP_ADDRESS,\n *      - TRAP_8021AB,\n *      - TRAP_UNDEF_BRG_0F,\n *      - TRAP_BRG_MNGEMENT,\n *      - TRAP_UNDEFINED_11,\n *      - TRAP_UNDEFINED_12,\n *      - TRAP_UNDEFINED_13,\n *      - TRAP_UNDEFINED_14,\n *      - TRAP_UNDEFINED_15,\n *      - TRAP_UNDEFINED_16,\n *      - TRAP_UNDEFINED_17,\n *      - TRAP_UNDEFINED_18,\n *      - TRAP_UNDEFINED_19,\n *      - TRAP_UNDEFINED_1A,\n *      - TRAP_UNDEFINED_1B,\n *      - TRAP_UNDEFINED_1C,\n *      - TRAP_UNDEFINED_1D,\n *      - TRAP_UNDEFINED_1E,\n *      - TRAP_UNDEFINED_1F,\n *      - TRAP_GMRP,\n *      - TRAP_GVRP,\n *      - TRAP_UNDEF_GARP_22,\n *      - TRAP_UNDEF_GARP_23,\n *      - TRAP_UNDEF_GARP_24,\n *      - TRAP_UNDEF_GARP_25,\n *      - TRAP_UNDEF_GARP_26,\n *      - TRAP_UNDEF_GARP_27,\n *      - TRAP_UNDEF_GARP_28,\n *      - TRAP_UNDEF_GARP_29,\n *      - TRAP_UNDEF_GARP_2A,\n *      - TRAP_UNDEF_GARP_2B,\n *      - TRAP_UNDEF_GARP_2C,\n *      - TRAP_UNDEF_GARP_2D,\n *      - TRAP_UNDEF_GARP_2E,\n *      - TRAP_UNDEF_GARP_2F,\n *      - TRAP_CDP.\n *      - TRAP_CSSTP.\n *      - TRAP_LLDP.\n */\nextern rtk_api_ret_t rtk_trap_rmaKeepFormat_set(rtk_trap_type_t type, rtk_enable_t enable);\n\n/* Function Name:\n *      rtk_trap_rmaKeepFormat_get\n * Description:\n *      Get Reserved multicast address action configuration.\n * Input:\n *      type - rma type.\n * Output:\n *      pEnable - keep format status.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n * Note:\n *      There are 48 types of Reserved Multicast Address frame for application usage.\n *      They are as following definition.\n *      - TRAP_BRG_GROUP,\n *      - TRAP_FD_PAUSE,\n *      - TRAP_SP_MCAST,\n *      - TRAP_1X_PAE,\n *      - TRAP_UNDEF_BRG_04,\n *      - TRAP_UNDEF_BRG_05,\n *      - TRAP_UNDEF_BRG_06,\n *      - TRAP_UNDEF_BRG_07,\n *      - TRAP_PROVIDER_BRIDGE_GROUP_ADDRESS,\n *      - TRAP_UNDEF_BRG_09,\n *      - TRAP_UNDEF_BRG_0A,\n *      - TRAP_UNDEF_BRG_0B,\n *      - TRAP_UNDEF_BRG_0C,\n *      - TRAP_PROVIDER_BRIDGE_GVRP_ADDRESS,\n *      - TRAP_8021AB,\n *      - TRAP_UNDEF_BRG_0F,\n *      - TRAP_BRG_MNGEMENT,\n *      - TRAP_UNDEFINED_11,\n *      - TRAP_UNDEFINED_12,\n *      - TRAP_UNDEFINED_13,\n *      - TRAP_UNDEFINED_14,\n *      - TRAP_UNDEFINED_15,\n *      - TRAP_UNDEFINED_16,\n *      - TRAP_UNDEFINED_17,\n *      - TRAP_UNDEFINED_18,\n *      - TRAP_UNDEFINED_19,\n *      - TRAP_UNDEFINED_1A,\n *      - TRAP_UNDEFINED_1B,\n *      - TRAP_UNDEFINED_1C,\n *      - TRAP_UNDEFINED_1D,\n *      - TRAP_UNDEFINED_1E,\n *      - TRAP_UNDEFINED_1F,\n *      - TRAP_GMRP,\n *      - TRAP_GVRP,\n *      - TRAP_UNDEF_GARP_22,\n *      - TRAP_UNDEF_GARP_23,\n *      - TRAP_UNDEF_GARP_24,\n *      - TRAP_UNDEF_GARP_25,\n *      - TRAP_UNDEF_GARP_26,\n *      - TRAP_UNDEF_GARP_27,\n *      - TRAP_UNDEF_GARP_28,\n *      - TRAP_UNDEF_GARP_29,\n *      - TRAP_UNDEF_GARP_2A,\n *      - TRAP_UNDEF_GARP_2B,\n *      - TRAP_UNDEF_GARP_2C,\n *      - TRAP_UNDEF_GARP_2D,\n *      - TRAP_UNDEF_GARP_2E,\n *      - TRAP_UNDEF_GARP_2F,\n *      - TRAP_CDP.\n *      - TRAP_CSSTP.\n *      - TRAP_LLDP.\n */\nextern rtk_api_ret_t rtk_trap_rmaKeepFormat_get(rtk_trap_type_t type, rtk_enable_t *pEnable);\n\n\n#endif /* __RTK_API_TRAP_H__ */\n\n\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/trunk.h",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * Purpose : RTL8367/RTL8367C switch high-level API\n *\n * Feature : The file includes Trunk module high-layer TRUNK defination\n *\n */\n\n#ifndef __RTK_API_TRUNK_H__\n#define __RTK_API_TRUNK_H__\n\n/*\n * Data Type Declaration\n */\n#define    RTK_TRUNK_DPORT_HASH_MASK     0x40\n#define    RTK_TRUNK_SPORT_HASH_MASK     0x20\n#define    RTK_TRUNK_DIP_HASH_MASK       0x10\n#define    RTK_TRUNK_SIP_HASH_MASK       0x8\n#define    RTK_TRUNK_DMAC_HASH_MASK      0x4\n#define    RTK_TRUNK_SMAC_HASH_MASK      0x2\n#define    RTK_TRUNK_SPA_HASH_MASK       0x1\n\n\n#define RTK_MAX_NUM_OF_TRUNK_HASH_VAL               16\n\ntypedef struct  rtk_trunk_hashVal2Port_s\n{\n    rtk_uint8 value[RTK_MAX_NUM_OF_TRUNK_HASH_VAL];\n} rtk_trunk_hashVal2Port_t;\n\ntypedef enum rtk_trunk_group_e\n{\n    TRUNK_GROUP0 = 0,\n    TRUNK_GROUP1,\n    TRUNK_GROUP2,\n    TRUNK_GROUP3,\n    TRUNK_GROUP_END\n} rtk_trunk_group_t;\n\ntypedef enum rtk_trunk_separateType_e\n{\n    SEPARATE_NONE = 0,\n    SEPARATE_FLOOD,\n    SEPARATE_END\n\n} rtk_trunk_separateType_t;\n\ntypedef enum rtk_trunk_mode_e\n{\n    TRUNK_MODE_NORMAL = 0,\n    TRUNK_MODE_DUMB,\n    TRUNK_MODE_END\n} rtk_trunk_mode_t;\n\n/* Function Name:\n *      rtk_trunk_port_set\n * Description:\n *      Set trunking group available port mask\n * Input:\n *      trk_gid                 - trunk group id\n *      pTrunk_member_portmask  - Logic trunking member port mask\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_LA_TRUNK_ID  - Invalid trunking group\n *      RT_ERR_PORT_MASK    - Invalid portmask.\n * Note:\n *      The API can set port trunking group port mask. Each port trunking group has max 4 ports.\n *      If enabled port mask has less than 2 ports available setting, then this trunking group function is disabled.\n */\nextern rtk_api_ret_t rtk_trunk_port_set(rtk_trunk_group_t trk_gid, rtk_portmask_t *pTrunk_member_portmask);\n\n/* Function Name:\n *      rtk_trunk_port_get\n * Description:\n *      Get trunking group available port mask\n * Input:\n *      trk_gid - trunk group id\n * Output:\n *      pTrunk_member_portmask - Logic trunking member port mask\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_LA_TRUNK_ID  - Invalid trunking group\n * Note:\n *      The API can get 2 port trunking group.\n */\nextern rtk_api_ret_t rtk_trunk_port_get(rtk_trunk_group_t trk_gid, rtk_portmask_t *pTrunk_member_portmask);\n\n/* Function Name:\n *      rtk_trunk_distributionAlgorithm_set\n * Description:\n *      Set port trunking hash select sources\n * Input:\n *      trk_gid         - trunk group id\n *      algo_bitmask    - Bitmask of the distribution algorithm\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_LA_TRUNK_ID  - Invalid trunking group\n *      RT_ERR_LA_HASHMASK  - Hash algorithm selection error.\n *      RT_ERR_PORT_MASK    - Invalid portmask.\n * Note:\n *      The API can set port trunking hash algorithm sources.\n *      7 bits mask for link aggregation group0 hash parameter selection {DIP, SIP, DMAC, SMAC, SPA}\n *      - 0b0000001: SPA\n *      - 0b0000010: SMAC\n *      - 0b0000100: DMAC\n *      - 0b0001000: SIP\n *      - 0b0010000: DIP\n *      - 0b0100000: TCP/UDP Source Port\n *      - 0b1000000: TCP/UDP Destination Port\n *      Example:\n *      - 0b0000011: SMAC & SPA\n *      - Note that it could be an arbitrary combination or independent set\n */\nextern rtk_api_ret_t rtk_trunk_distributionAlgorithm_set(rtk_trunk_group_t trk_gid, rtk_uint32 algo_bitmask);\n\n/* Function Name:\n *      rtk_trunk_distributionAlgorithm_get\n * Description:\n *      Get port trunking hash select sources\n * Input:\n *      trk_gid - trunk group id\n * Output:\n *      pAlgo_bitmask -  Bitmask of the distribution algorithm\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_LA_TRUNK_ID  - Invalid trunking group\n * Note:\n *      The API can get port trunking hash algorithm sources.\n */\nextern rtk_api_ret_t rtk_trunk_distributionAlgorithm_get(rtk_trunk_group_t trk_gid, rtk_uint32 *pAlgo_bitmask);\n\n/* Function Name:\n *      rtk_trunk_trafficSeparate_set\n * Description:\n *      Set the traffic separation setting of a trunk group from the specified device.\n * Input:\n *      trk_gid      - trunk group id\n *      separateType     - traffic separation setting\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n *      RT_ERR_UNIT_ID     - invalid unit id\n *      RT_ERR_LA_TRUNK_ID - invalid trunk ID\n *      RT_ERR_LA_HASHMASK - invalid hash mask\n * Note:\n *      SEPARATE_NONE: disable traffic separation\n *      SEPARATE_FLOOD: trunk MSB link up port is dedicated to TX flooding (L2 lookup miss) traffic\n */\nextern rtk_api_ret_t rtk_trunk_trafficSeparate_set(rtk_trunk_group_t trk_gid, rtk_trunk_separateType_t separateType);\n\n/* Function Name:\n *      rtk_trunk_trafficSeparate_get\n * Description:\n *      Get the traffic separation setting of a trunk group from the specified device.\n * Input:\n *      trk_gid        - trunk group id\n * Output:\n *      pSeparateType   - pointer separated traffic type\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n *      RT_ERR_UNIT_ID      - invalid unit id\n *      RT_ERR_LA_TRUNK_ID  - invalid trunk ID\n *      RT_ERR_NULL_POINTER - input parameter may be null pointer\n * Note:\n *      SEPARATE_NONE: disable traffic separation\n *      SEPARATE_FLOOD: trunk MSB link up port is dedicated to TX flooding (L2 lookup miss) traffic\n */\nextern rtk_api_ret_t rtk_trunk_trafficSeparate_get(rtk_trunk_group_t trk_gid, rtk_trunk_separateType_t *pSeparateType);\n\n\n/* Function Name:\n *      rtk_trunk_mode_set\n * Description:\n *      Set the trunk mode to the specified device.\n * Input:\n *      mode - trunk mode\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n *      RT_ERR_INPUT   - invalid input parameter\n * Note:\n *      The enum of the trunk mode as following\n *      - TRUNK_MODE_NORMAL\n *      - TRUNK_MODE_DUMB\n */\nextern rtk_api_ret_t rtk_trunk_mode_set(rtk_trunk_mode_t mode);\n\n/* Function Name:\n *      rtk_trunk_mode_get\n * Description:\n *      Get the trunk mode from the specified device.\n * Input:\n *      None\n * Output:\n *      pMode - pointer buffer of trunk mode\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n *      RT_ERR_NULL_POINTER - input parameter may be null pointer\n * Note:\n *      The enum of the trunk mode as following\n *      - TRUNK_MODE_NORMAL\n *      - TRUNK_MODE_DUMB\n */\nextern rtk_api_ret_t rtk_trunk_mode_get(rtk_trunk_mode_t *pMode);\n\n/* Function Name:\n *      rtk_trunk_trafficPause_set\n * Description:\n *      Set the traffic pause setting of a trunk group.\n * Input:\n *      trk_gid      - trunk group id\n *      enable       - traffic pause state\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n *      RT_ERR_LA_TRUNK_ID - invalid trunk ID\n * Note:\n *      None.\n */\nextern rtk_api_ret_t rtk_trunk_trafficPause_set(rtk_trunk_group_t trk_gid, rtk_enable_t enable);\n\n/* Function Name:\n *      rtk_trunk_trafficPause_get\n * Description:\n *      Get the traffic pause setting of a trunk group.\n * Input:\n *      trk_gid        - trunk group id\n * Output:\n *      pEnable        - pointer of traffic pause state.\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n *      RT_ERR_LA_TRUNK_ID  - invalid trunk ID\n *      RT_ERR_NULL_POINTER - input parameter may be null pointer\n * Note:\n *      None.\n */\nextern rtk_api_ret_t rtk_trunk_trafficPause_get(rtk_trunk_group_t trk_gid, rtk_enable_t *pEnable);\n\n/* Function Name:\n *      rtk_trunk_hashMappingTable_set\n * Description:\n *      Set hash value to port array in the trunk group id from the specified device.\n * Input:\n *      trk_gid          - trunk group id\n *      pHash2Port_array - ports associate with the hash value\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n *      RT_ERR_UNIT_ID            - invalid unit id\n *      RT_ERR_LA_TRUNK_ID        - invalid trunk ID\n *      RT_ERR_NULL_POINTER       - input parameter may be null pointer\n *      RT_ERR_LA_TRUNK_NOT_EXIST - the trunk doesn't exist\n *      RT_ERR_LA_NOT_MEMBER_PORT - the port is not a member port of the trunk\n *      RT_ERR_LA_CPUPORT         - CPU port can not be aggregated port\n * Note:\n *      Trunk group 0 & 1 shares the same hash mapping table.\n *      Trunk group 2 uses a independent table.\n */\nextern rtk_api_ret_t rtk_trunk_hashMappingTable_set(rtk_trunk_group_t trk_gid, rtk_trunk_hashVal2Port_t *pHash2Port_array);\n\n/* Function Name:\n *      rtk_trunk_hashMappingTable_get\n * Description:\n *      Get hash value to port array in the trunk group id from the specified device.\n * Input:\n *      trk_gid          - trunk group id\n * Output:\n *      pHash2Port_array - pointer buffer of ports associate with the hash value\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n *      RT_ERR_UNIT_ID      - invalid unit id\n *      RT_ERR_LA_TRUNK_ID  - invalid trunk ID\n *      RT_ERR_NULL_POINTER - input parameter may be null pointer\n * Note:\n *      Trunk group 0 & 1 shares the same hash mapping table.\n *      Trunk group 2 uses a independent table.\n */\nextern rtk_api_ret_t rtk_trunk_hashMappingTable_get(rtk_trunk_group_t trk_gid, rtk_trunk_hashVal2Port_t *pHash2Port_array);\n\n/* Function Name:\n *      rtk_trunk_portQueueEmpty_get\n * Description:\n *      Get the port mask which all queues are empty.\n * Input:\n *      None.\n * Output:\n *      pEmpty_portmask   - pointer empty port mask\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n *      RT_ERR_NULL_POINTER - input parameter may be null pointer\n * Note:\n *      None.\n */\nextern rtk_api_ret_t rtk_trunk_portQueueEmpty_get(rtk_portmask_t *pEmpty_portmask);\n\n#endif /* __RTK_API_TRUNK_H__ */\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/include/vlan.h",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * Purpose : RTL8367/RTL8367C switch high-level API\n *\n * Feature : The file includes Trap module high-layer VLAN defination\n *\n */\n\n#ifndef __RTK_API_VLAN_H__\n#define __RTK_API_VLAN_H__\n\n\n/*\n * Data Type Declaration\n */\n#define RTK_MAX_NUM_OF_PROTO_TYPE                   0xFFFF\n#define RTK_MAX_NUM_OF_MSTI                         0xF\n#define RTK_FID_MAX                                 0xF\n\ntypedef struct  rtk_vlan_cfg_s\n{\n    rtk_portmask_t  mbr;\n    rtk_portmask_t  untag;\n    rtk_uint16      ivl_en;\n    rtk_uint16      fid_msti;\n    rtk_uint16      envlanpol;\n    rtk_uint16      meteridx;\n    rtk_uint16      vbpen;\n    rtk_uint16      vbpri;\n}rtk_vlan_cfg_t;\n\ntypedef struct  rtk_vlan_mbrcfg_s\n{\n    rtk_uint16      evid;\n    rtk_portmask_t  mbr;\n    rtk_uint16      fid_msti;\n    rtk_uint16      envlanpol;\n    rtk_uint16      meteridx;\n    rtk_uint16      vbpen;\n    rtk_uint16      vbpri;\n}rtk_vlan_mbrcfg_t;\n\ntypedef rtk_uint32  rtk_stp_msti_id_t;     /* MSTI ID  */\n\ntypedef enum rtk_stp_state_e\n{\n    STP_STATE_DISABLED = 0,\n    STP_STATE_BLOCKING,\n    STP_STATE_LEARNING,\n    STP_STATE_FORWARDING,\n    STP_STATE_END\n} rtk_stp_state_t;\n\ntypedef rtk_uint32  rtk_vlan_proto_type_t;     /* protocol and port based VLAN protocol type  */\n\n\ntypedef enum rtk_vlan_acceptFrameType_e\n{\n    ACCEPT_FRAME_TYPE_ALL = 0,             /* untagged, priority-tagged and tagged */\n    ACCEPT_FRAME_TYPE_TAG_ONLY,         /* tagged */\n    ACCEPT_FRAME_TYPE_UNTAG_ONLY,     /* untagged and priority-tagged */\n    ACCEPT_FRAME_TYPE_END\n} rtk_vlan_acceptFrameType_t;\n\n\n/* frame type of protocol vlan - reference 802.1v standard */\ntypedef enum rtk_vlan_protoVlan_frameType_e\n{\n    FRAME_TYPE_ETHERNET = 0,\n    FRAME_TYPE_LLCOTHER,\n    FRAME_TYPE_RFC1042,\n    FRAME_TYPE_END\n} rtk_vlan_protoVlan_frameType_t;\n\n/* Protocol-and-port-based Vlan structure */\ntypedef struct rtk_vlan_protoAndPortInfo_s\n{\n    rtk_uint32                         proto_type;\n    rtk_vlan_protoVlan_frameType_t frame_type;\n    rtk_vlan_t                     cvid;\n    rtk_pri_t                     cpri;\n}rtk_vlan_protoAndPortInfo_t;\n\n/* tagged mode of VLAN - reference realtek private specification */\ntypedef enum rtk_vlan_tagMode_e\n{\n    VLAN_TAG_MODE_ORIGINAL = 0,\n    VLAN_TAG_MODE_KEEP_FORMAT,\n    VLAN_TAG_MODE_PRI,\n    VLAN_TAG_MODE_REAL_KEEP_FORMAT,\n    VLAN_TAG_MODE_END\n} rtk_vlan_tagMode_t;\n\ntypedef enum rtk_vlan_resVidAction_e\n{\n    RESVID_ACTION_UNTAG = 0,\n    RESVID_ACTION_TAG,\n    RESVID_ACTION_END\n}\nrtk_vlan_resVidAction_t;\n\n/* Function Name:\n *      rtk_vlan_init\n * Description:\n *      Initialize VLAN.\n * Input:\n *      None\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n * Note:\n *      VLAN is disabled by default. User has to call this API to enable VLAN before\n *      using it. And It will set a default VLAN(vid 1) including all ports and set\n *      all ports PVID to the default VLAN.\n */\nextern rtk_api_ret_t rtk_vlan_init(void);\n\n/* Function Name:\n *      rtk_vlan_set\n * Description:\n *      Set a VLAN entry.\n * Input:\n *      vid - VLAN ID to configure.\n *      pVlanCfg - VLAN Configuration\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK                   - OK\n *      RT_ERR_FAILED               - Failed\n *      RT_ERR_SMI                  - SMI access error\n *      RT_ERR_INPUT                - Invalid input parameters.\n *      RT_ERR_L2_FID               - Invalid FID.\n *      RT_ERR_VLAN_PORT_MBR_EXIST  - Invalid member port mask.\n *      RT_ERR_VLAN_VID             - Invalid VID parameter.\n * Note:\n *\n */\nextern rtk_api_ret_t rtk_vlan_set(rtk_vlan_t vid, rtk_vlan_cfg_t *pVlanCfg);\n\n/* Function Name:\n *      rtk_vlan_get\n * Description:\n *      Get a VLAN entry.\n * Input:\n *      vid - VLAN ID to configure.\n * Output:\n *      pVlanCfg - VLAN Configuration\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n *      RT_ERR_VLAN_VID     - Invalid VID parameter.\n * Note:\n *\n */\nextern rtk_api_ret_t rtk_vlan_get(rtk_vlan_t vid, rtk_vlan_cfg_t *pVlanCfg);\n\n/* Function Name:\n *      rtk_vlan_egrFilterEnable_set\n * Description:\n *      Set VLAN egress filter.\n * Input:\n *      egrFilter - Egress filtering\n * Output:\n *      None.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_ENABLE       - Invalid input parameters.\n * Note:\n *\n */\nextern rtk_api_ret_t rtk_vlan_egrFilterEnable_set(rtk_enable_t egrFilter);\n\n/* Function Name:\n *      rtk_vlan_egrFilterEnable_get\n * Description:\n *      Get VLAN egress filter.\n * Input:\n *      pEgrFilter - Egress filtering\n * Output:\n *      None.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_NULL_POINTER - NULL Pointer.\n * Note:\n *\n */\nextern rtk_api_ret_t rtk_vlan_egrFilterEnable_get(rtk_enable_t *pEgrFilter);\n\n/* Function Name:\n *      rtk_vlan_mbrCfg_set\n * Description:\n *      Set a VLAN Member Configuration entry by index.\n * Input:\n *      idx     - Index of VLAN Member Configuration.\n *      pMbrcfg - VLAN member Configuration.\n * Output:\n *      None.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n *      RT_ERR_VLAN_VID     - Invalid VID parameter.\n * Note:\n *     Set a VLAN Member Configuration entry by index.\n */\nextern rtk_api_ret_t rtk_vlan_mbrCfg_set(rtk_uint32 idx, rtk_vlan_mbrcfg_t *pMbrcfg);\n\n/* Function Name:\n *      rtk_vlan_mbrCfg_get\n * Description:\n *      Get a VLAN Member Configuration entry by index.\n * Input:\n *      idx - Index of VLAN Member Configuration.\n * Output:\n *      pMbrcfg - VLAN member Configuration.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n *      RT_ERR_VLAN_VID     - Invalid VID parameter.\n * Note:\n *     Get a VLAN Member Configuration entry by index.\n */\nextern rtk_api_ret_t rtk_vlan_mbrCfg_get(rtk_uint32 idx, rtk_vlan_mbrcfg_t *pMbrcfg);\n\n/* Function Name:\n *     rtk_vlan_portPvid_set\n * Description:\n *      Set port to specified VLAN ID(PVID).\n * Input:\n *      port - Port id.\n *      pvid - Specified VLAN ID.\n *      priority - 802.1p priority for the PVID.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK                   - OK\n *      RT_ERR_FAILED               - Failed\n *      RT_ERR_SMI                  - SMI access error\n *      RT_ERR_PORT_ID              - Invalid port number.\n *      RT_ERR_VLAN_PRIORITY        - Invalid priority.\n *      RT_ERR_VLAN_ENTRY_NOT_FOUND - VLAN entry not found.\n *      RT_ERR_VLAN_VID             - Invalid VID parameter.\n * Note:\n *       The API is used for Port-based VLAN. The untagged frame received from the\n *       port will be classified to the specified VLAN and assigned to the specified priority.\n */\nextern rtk_api_ret_t rtk_vlan_portPvid_set(rtk_port_t port, rtk_vlan_t pvid, rtk_pri_t priority);\n\n/* Function Name:\n *      rtk_vlan_portPvid_get\n * Description:\n *      Get VLAN ID(PVID) on specified port.\n * Input:\n *      port - Port id.\n * Output:\n *      pPvid - Specified VLAN ID.\n *      pPriority - 802.1p priority for the PVID.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n *      RT_ERR_PORT_ID      - Invalid port number.\n * Note:\n *     The API can get the PVID and 802.1p priority for the PVID of Port-based VLAN.\n */\nextern rtk_api_ret_t rtk_vlan_portPvid_get(rtk_port_t port, rtk_vlan_t *pPvid, rtk_pri_t *pPriority);\n\n/* Function Name:\n *      rtk_vlan_portIgrFilterEnable_set\n * Description:\n *      Set VLAN ingress for each port.\n * Input:\n *      port - Port id.\n *      igr_filter - VLAN ingress function enable status.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number\n *      RT_ERR_ENABLE       - Invalid enable input\n * Note:\n *      The status of vlan ingress filter is as following:\n *      - DISABLED\n *      - ENABLED\n *      While VLAN function is enabled, ASIC will decide VLAN ID for each received frame and get belonged member\n *      ports from VLAN table. If received port is not belonged to VLAN member ports, ASIC will drop received frame if VLAN ingress function is enabled.\n */\nextern rtk_api_ret_t rtk_vlan_portIgrFilterEnable_set(rtk_port_t port, rtk_enable_t igr_filter);\n\n/* Function Name:\n *      rtk_vlan_portIgrFilterEnable_get\n * Description:\n *      Get VLAN Ingress Filter\n * Input:\n *      port        - Port id.\n * Output:\n *      pIgr_filter - VLAN ingress function enable status.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n *      RT_ERR_PORT_ID      - Invalid port number.\n * Note:\n *     The API can Get the VLAN ingress filter status.\n *     The status of vlan ingress filter is as following:\n *     - DISABLED\n *     - ENABLED\n */\nextern rtk_api_ret_t rtk_vlan_portIgrFilterEnable_get(rtk_port_t port, rtk_enable_t *pIgr_filter);\n\n/* Function Name:\n *      rtk_vlan_portAcceptFrameType_set\n * Description:\n *      Set VLAN accept_frame_type\n * Input:\n *      port                - Port id.\n *      accept_frame_type   - accept frame type\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK                       - OK\n *      RT_ERR_FAILED                   - Failed\n *      RT_ERR_SMI                      - SMI access error\n *      RT_ERR_PORT_ID                  - Invalid port number.\n *      RT_ERR_VLAN_ACCEPT_FRAME_TYPE   - Invalid frame type.\n * Note:\n *      The API is used for checking 802.1Q tagged frames.\n *      The accept frame type as following:\n *      - ACCEPT_FRAME_TYPE_ALL\n *      - ACCEPT_FRAME_TYPE_TAG_ONLY\n *      - ACCEPT_FRAME_TYPE_UNTAG_ONLY\n */\nextern rtk_api_ret_t rtk_vlan_portAcceptFrameType_set(rtk_port_t port, rtk_vlan_acceptFrameType_t accept_frame_type);\n\n/* Function Name:\n *      rtk_vlan_portAcceptFrameType_get\n * Description:\n *      Get VLAN accept_frame_type\n * Input:\n *      port - Port id.\n * Output:\n *      pAccept_frame_type - accept frame type\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n *      RT_ERR_PORT_ID      - Invalid port number.\n * Note:\n *     The API can Get the VLAN ingress filter.\n *     The accept frame type as following:\n *     - ACCEPT_FRAME_TYPE_ALL\n *     - ACCEPT_FRAME_TYPE_TAG_ONLY\n *     - ACCEPT_FRAME_TYPE_UNTAG_ONLY\n */\nextern rtk_api_ret_t rtk_vlan_portAcceptFrameType_get(rtk_port_t port, rtk_vlan_acceptFrameType_t *pAccept_frame_type);\n\n/* Function Name:\n *      rtk_vlan_tagMode_set\n * Description:\n *      Set CVLAN egress tag mode\n * Input:\n *      port        - Port id.\n *      tag_mode    - The egress tag mode.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number.\n *      RT_ERR_INPUT        - Invalid input parameter.\n *      RT_ERR_ENABLE       - Invalid enable input.\n * Note:\n *      The API can set Egress tag mode. There are 4 mode for egress tag:\n *      - VLAN_TAG_MODE_ORIGINAL,\n *      - VLAN_TAG_MODE_KEEP_FORMAT,\n *      - VLAN_TAG_MODE_PRI.\n *      - VLAN_TAG_MODE_REAL_KEEP_FORMAT,\n */\nextern rtk_api_ret_t rtk_vlan_tagMode_set(rtk_port_t port, rtk_vlan_tagMode_t tag_mode);\n\n/* Function Name:\n *      rtk_vlan_tagMode_get\n * Description:\n *      Get CVLAN egress tag mode\n * Input:\n *      port - Port id.\n * Output:\n *      pTag_mode - The egress tag mode.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n *      RT_ERR_PORT_ID      - Invalid port number.\n * Note:\n *      The API can get Egress tag mode. There are 4 mode for egress tag:\n *      - VLAN_TAG_MODE_ORIGINAL,\n *      - VLAN_TAG_MODE_KEEP_FORMAT,\n *      - VLAN_TAG_MODE_PRI.\n *      - VLAN_TAG_MODE_REAL_KEEP_FORMAT,\n */\nextern rtk_api_ret_t rtk_vlan_tagMode_get(rtk_port_t port, rtk_vlan_tagMode_t *pTag_mode);\n\n/* Function Name:\n *      rtk_vlan_transparent_set\n * Description:\n *      Set VLAN transparent mode\n * Input:\n *      egr_port        - Egress Port id.\n *      pIgr_pmask      - Ingress Port Mask.\n * Output:\n *      None.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n *      RT_ERR_PORT_ID      - Invalid port number.\n * Note:\n *      None.\n */\nextern rtk_api_ret_t rtk_vlan_transparent_set(rtk_port_t egr_port, rtk_portmask_t *pIgr_pmask);\n\n/* Function Name:\n *      rtk_vlan_transparent_get\n * Description:\n *      Get VLAN transparent mode\n * Input:\n *      egr_port        - Egress Port id.\n * Output:\n *      pIgr_pmask      - Ingress Port Mask\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n *      RT_ERR_PORT_ID      - Invalid port number.\n * Note:\n *      None.\n */\nextern rtk_api_ret_t rtk_vlan_transparent_get(rtk_port_t egr_port, rtk_portmask_t *pIgr_pmask);\n\n/* Function Name:\n *      rtk_vlan_keep_set\n * Description:\n *      Set VLAN egress keep mode\n * Input:\n *      egr_port        - Egress Port id.\n *      pIgr_pmask      - Ingress Port Mask.\n * Output:\n *      None.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n *      RT_ERR_PORT_ID      - Invalid port number.\n * Note:\n *      None.\n */\nextern rtk_api_ret_t rtk_vlan_keep_set(rtk_port_t egr_port, rtk_portmask_t *pIgr_pmask);\n\n/* Function Name:\n *      rtk_vlan_keep_get\n * Description:\n *      Get VLAN egress keep mode\n * Input:\n *      egr_port        - Egress Port id.\n * Output:\n *      pIgr_pmask      - Ingress Port Mask\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n *      RT_ERR_PORT_ID      - Invalid port number.\n * Note:\n *      None.\n */\nextern rtk_api_ret_t rtk_vlan_keep_get(rtk_port_t egr_port, rtk_portmask_t *pIgr_pmask);\n\n/* Function Name:\n *      rtk_vlan_stg_set\n * Description:\n *      Set spanning tree group instance of the vlan to the specified device\n * Input:\n *      vid - Specified VLAN ID.\n *      stg - spanning tree group instance.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_MSTI         - Invalid msti parameter\n *      RT_ERR_INPUT        - Invalid input parameter.\n *      RT_ERR_VLAN_VID     - Invalid VID parameter.\n * Note:\n *      The API can set spanning tree group instance of the vlan to the specified device.\n */\nextern rtk_api_ret_t rtk_vlan_stg_set(rtk_vlan_t vid, rtk_stp_msti_id_t stg);\n\n/* Function Name:\n *      rtk_vlan_stg_get\n * Description:\n *      Get spanning tree group instance of the vlan to the specified device\n * Input:\n *      vid - Specified VLAN ID.\n * Output:\n *      pStg - spanning tree group instance.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n *      RT_ERR_VLAN_VID     - Invalid VID parameter.\n * Note:\n *      The API can get spanning tree group instance of the vlan to the specified device.\n */\nextern rtk_api_ret_t rtk_vlan_stg_get(rtk_vlan_t vid, rtk_stp_msti_id_t *pStg);\n\n/* Function Name:\n *      rtk_vlan_protoAndPortBasedVlan_add\n * Description:\n *      Add the protocol-and-port-based vlan to the specified port of device.\n * Input:\n *      port  - Port id.\n *      pInfo - Protocol and port based VLAN configuration information.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - OK\n *      RT_ERR_FAILED           - Failed\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_PORT_ID          - Invalid port number.\n *      RT_ERR_VLAN_VID         - Invalid VID parameter.\n *      RT_ERR_VLAN_PRIORITY    - Invalid priority.\n *      RT_ERR_TBL_FULL         - Table is full.\n *      RT_ERR_OUT_OF_RANGE     - input out of range.\n * Note:\n *      The incoming packet which match the protocol-and-port-based vlan will use the configure vid for ingress pipeline\n *      The frame type is shown in the following:\n *      - FRAME_TYPE_ETHERNET\n *      - FRAME_TYPE_RFC1042\n *      - FRAME_TYPE_LLCOTHER\n */\nextern rtk_api_ret_t rtk_vlan_protoAndPortBasedVlan_add(rtk_port_t port, rtk_vlan_protoAndPortInfo_t *pInfo);\n\n/* Function Name:\n *      rtk_vlan_protoAndPortBasedVlan_get\n * Description:\n *      Get the protocol-and-port-based vlan to the specified port of device.\n * Input:\n *      port - Port id.\n *      proto_type - protocol-and-port-based vlan protocol type.\n *      frame_type - protocol-and-port-based vlan frame type.\n * Output:\n *      pInfo - Protocol and port based VLAN configuration information.\n * Return:\n *      RT_ERR_OK               - OK\n *      RT_ERR_FAILED           - Failed\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_PORT_ID          - Invalid port number.\n *      RT_ERR_OUT_OF_RANGE     - input out of range.\n *      RT_ERR_TBL_FULL         - Table is full.\n * Note:\n *     The incoming packet which match the protocol-and-port-based vlan will use the configure vid for ingress pipeline\n *     The frame type is shown in the following:\n *      - FRAME_TYPE_ETHERNET\n *      - FRAME_TYPE_RFC1042\n *      - FRAME_TYPE_LLCOTHER\n */\nextern rtk_api_ret_t rtk_vlan_protoAndPortBasedVlan_get(rtk_port_t port, rtk_vlan_proto_type_t proto_type, rtk_vlan_protoVlan_frameType_t frame_type, rtk_vlan_protoAndPortInfo_t *pInfo);\n\n/* Function Name:\n *      rtk_vlan_protoAndPortBasedVlan_del\n * Description:\n *      Delete the protocol-and-port-based vlan from the specified port of device.\n * Input:\n *      port        - Port id.\n *      proto_type  - protocol-and-port-based vlan protocol type.\n *      frame_type  - protocol-and-port-based vlan frame type.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - OK\n *      RT_ERR_FAILED           - Failed\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_PORT_ID          - Invalid port number.\n *      RT_ERR_OUT_OF_RANGE     - input out of range.\n *      RT_ERR_TBL_FULL         - Table is full.\n * Note:\n *     The incoming packet which match the protocol-and-port-based vlan will use the configure vid for ingress pipeline\n *     The frame type is shown in the following:\n *      - FRAME_TYPE_ETHERNET\n *      - FRAME_TYPE_RFC1042\n *      - FRAME_TYPE_LLCOTHER\n */\nextern rtk_api_ret_t rtk_vlan_protoAndPortBasedVlan_del(rtk_port_t port, rtk_vlan_proto_type_t proto_type, rtk_vlan_protoVlan_frameType_t frame_type);\n\n/* Function Name:\n *      rtk_vlan_protoAndPortBasedVlan_delAll\n * Description:\n *     Delete all protocol-and-port-based vlans from the specified port of device.\n * Input:\n *      port - Port id.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - OK\n *      RT_ERR_FAILED           - Failed\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_PORT_ID          - Invalid port number.\n *      RT_ERR_OUT_OF_RANGE     - input out of range.\n * Note:\n *     The incoming packet which match the protocol-and-port-based vlan will use the configure vid for ingress pipeline\n *     Delete all flow table protocol-and-port-based vlan entries.\n */\nextern rtk_api_ret_t rtk_vlan_protoAndPortBasedVlan_delAll(rtk_port_t port);\n\n/* Function Name:\n *      rtk_vlan_portFid_set\n * Description:\n *      Set port-based filtering database\n * Input:\n *      port - Port id.\n *      enable - ebable port-based FID\n *      fid - Specified filtering database.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n *      RT_ERR_L2_FID - Invalid fid.\n *      RT_ERR_INPUT - Invalid input parameter.\n *      RT_ERR_PORT_ID - Invalid port ID.\n * Note:\n *      The API can set port-based filtering database. If the function is enabled, all input\n *      packets will be assigned to the port-based fid regardless vlan tag.\n */\nextern rtk_api_ret_t rtk_vlan_portFid_set(rtk_port_t port, rtk_enable_t enable, rtk_fid_t fid);\n\n/* Function Name:\n *      rtk_vlan_portFid_get\n * Description:\n *      Get port-based filtering database\n * Input:\n *      port - Port id.\n * Output:\n *      pEnable - ebable port-based FID\n *      pFid - Specified filtering database.\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n *      RT_ERR_INPUT - Invalid input parameters.\n *      RT_ERR_PORT_ID - Invalid port ID.\n * Note:\n *      The API can get port-based filtering database status. If the function is enabled, all input\n *      packets will be assigned to the port-based fid regardless vlan tag.\n */\nextern rtk_api_ret_t rtk_vlan_portFid_get(rtk_port_t port, rtk_enable_t *pEnable, rtk_fid_t *pFid);\n\n/* Function Name:\n *      rtk_vlan_UntagDscpPriorityEnable_set\n * Description:\n *      Set Untag DSCP priority assign\n * Input:\n *      enable - state of Untag DSCP priority assign\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n *      RT_ERR_ENABLE          - Invalid input parameters.\n * Note:\n *\n */\nextern rtk_api_ret_t rtk_vlan_UntagDscpPriorityEnable_set(rtk_enable_t enable);\n\n/* Function Name:\n *      rtk_vlan_UntagDscpPriorityEnable_get\n * Description:\n *      Get Untag DSCP priority assign\n * Input:\n *      None\n * Output:\n *      pEnable - state of Untag DSCP priority assign\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n *      RT_ERR_NULL_POINTER    - Null pointer\n * Note:\n *\n */\nextern rtk_api_ret_t rtk_vlan_UntagDscpPriorityEnable_get(rtk_enable_t *pEnable);\n\n\n/*Spanning Tree*/\n/* Function Name:\n *      rtk_stp_mstpState_set\n * Description:\n *      Configure spanning tree state per each port.\n * Input:\n *      port - Port id\n *      msti - Multiple spanning tree instance.\n *      stp_state - Spanning tree state for msti\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number.\n *      RT_ERR_MSTI         - Invalid msti parameter.\n *      RT_ERR_MSTP_STATE   - Invalid STP state.\n * Note:\n *      System supports per-port multiple spanning tree state for each msti.\n *      There are four states supported by ASIC.\n *      - STP_STATE_DISABLED\n *      - STP_STATE_BLOCKING\n *      - STP_STATE_LEARNING\n *      - STP_STATE_FORWARDING\n */\nextern rtk_api_ret_t rtk_stp_mstpState_set(rtk_stp_msti_id_t msti, rtk_port_t port, rtk_stp_state_t stp_state);\n\n/* Function Name:\n *      rtk_stp_mstpState_get\n * Description:\n *      Get spanning tree state per each port.\n * Input:\n *      port - Port id.\n *      msti - Multiple spanning tree instance.\n * Output:\n *      pStp_state - Spanning tree state for msti\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number.\n *      RT_ERR_MSTI         - Invalid msti parameter.\n * Note:\n *      System supports per-port multiple spanning tree state for each msti.\n *      There are four states supported by ASIC.\n *      - STP_STATE_DISABLED\n *      - STP_STATE_BLOCKING\n *      - STP_STATE_LEARNING\n *      - STP_STATE_FORWARDING\n */\nextern rtk_api_ret_t rtk_stp_mstpState_get(rtk_stp_msti_id_t msti, rtk_port_t port, rtk_stp_state_t *pStp_state);\n\n/* Function Name:\n *      rtk_vlan_checkAndCreateMbr\n * Description:\n *      Check and create Member configuration and return index\n * Input:\n *      vid  - VLAN id.\n * Output:\n *      pIndex  - Member configuration index\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_VLAN_VID     - Invalid VLAN ID.\n *      RT_ERR_VLAN_ENTRY_NOT_FOUND - VLAN not found\n *      RT_ERR_TBL_FULL     - Member Configuration table full\n * Note:\n *\n */\nextern rtk_api_ret_t rtk_vlan_checkAndCreateMbr(rtk_vlan_t vid, rtk_uint32 *pIndex);\n\n/* Function Name:\n *      rtk_vlan_reservedVidAction_set\n * Description:\n *      Set Action of VLAN ID = 0 & 4095 tagged packet\n * Input:\n *      action_vid0     - Action for VID 0.\n *      action_vid4095  - Action for VID 4095.\n * Output:\n *      None.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Error Input\n * Note:\n *\n */\nextern rtk_api_ret_t rtk_vlan_reservedVidAction_set(rtk_vlan_resVidAction_t action_vid0, rtk_vlan_resVidAction_t action_vid4095);\n\n/* Function Name:\n *      rtk_vlan_reservedVidAction_get\n * Description:\n *      Get Action of VLAN ID = 0 & 4095 tagged packet\n * Input:\n *      pAction_vid0     - Action for VID 0.\n *      pAction_vid4095  - Action for VID 4095.\n * Output:\n *      None.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_NULL_POINTER - NULL Pointer\n * Note:\n *\n */\nextern rtk_api_ret_t rtk_vlan_reservedVidAction_get(rtk_vlan_resVidAction_t *pAction_vid0, rtk_vlan_resVidAction_t *pAction_vid4095);\n\n/* Function Name:\n *      rtk_vlan_realKeepRemarkEnable_set\n * Description:\n *      Set Real keep 1p remarking feature\n * Input:\n *      enabled     - State of 1p remarking at real keep packet\n * Output:\n *      None.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Error Input\n * Note:\n *\n */\nextern rtk_api_ret_t rtk_vlan_realKeepRemarkEnable_set(rtk_enable_t enabled);\n\n/* Function Name:\n *      rtk_vlan_realKeepRemarkEnable_get\n * Description:\n *      Get Real keep 1p remarking feature\n * Input:\n *      None.\n * Output:\n *      pEnabled     - State of 1p remarking at real keep packet\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Error Input\n * Note:\n *\n */\nextern rtk_api_ret_t rtk_vlan_realKeepRemarkEnable_get(rtk_enable_t *pEnabled);\n\n/* Function Name:\n *      rtk_vlan_reset\n * Description:\n *      Reset VLAN\n * Input:\n *      None.\n * Output:\n *      pEnabled     - State of 1p remarking at real keep packet\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Error Input\n * Note:\n *\n */\nrtk_api_ret_t rtk_vlan_reset(void);\n\n#endif /* __RTK_API_VLAN_H__ */\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/interrupt.c",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * $Revision: 76306 $\n * $Date: 2017-03-08 15:13:58 +0800 (週三, 08 三月 2017) $\n *\n * Purpose : RTK switch high-level API for RTL8367/RTL8367C\n * Feature : Here is a list of all functions and variables in Interrupt module.\n *\n */\n\n#include <rtk_switch.h>\n#include <rtk_error.h>\n#include <interrupt.h>\n#include <string.h>\n\n#include <rtl8367c_asicdrv.h>\n#include <rtl8367c_asicdrv_interrupt.h>\n\n/* Function Name:\n *      rtk_int_polarity_set\n * Description:\n *      Set interrupt polarity configuration.\n * Input:\n *      type - Interruptpolarity type.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n * Note:\n *      The API can set interrupt polarity configuration.\n */\nrtk_api_ret_t rtk_int_polarity_set(rtk_int_polarity_t type)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(type >= INT_POLAR_END)\n        return RT_ERR_INPUT;\n\n    if ((retVal = rtl8367c_setAsicInterruptPolarity(type)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_int_polarity_get\n * Description:\n *      Get interrupt polarity configuration.\n * Input:\n *      None\n * Output:\n *      pType - Interruptpolarity type.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n * Note:\n *      The API can get interrupt polarity configuration.\n */\nrtk_api_ret_t rtk_int_polarity_get(rtk_int_polarity_t *pType)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(NULL == pType)\n        return RT_ERR_NULL_POINTER;\n\n    if ((retVal = rtl8367c_getAsicInterruptPolarity(pType)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_int_control_set\n * Description:\n *      Set interrupt trigger status configuration.\n * Input:\n *      type - Interrupt type.\n *      enable - Interrupt status.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n *      RT_ERR_ENABLE       - Invalid enable input.\n * Note:\n *      The API can set interrupt status configuration.\n *      The interrupt trigger status is shown in the following:\n *      - INT_TYPE_LINK_STATUS\n *      - INT_TYPE_METER_EXCEED\n *      - INT_TYPE_LEARN_LIMIT\n *      - INT_TYPE_LINK_SPEED\n *      - INT_TYPE_CONGEST\n *      - INT_TYPE_GREEN_FEATURE\n *      - INT_TYPE_LOOP_DETECT\n *      - INT_TYPE_8051,\n *      - INT_TYPE_CABLE_DIAG,\n *      - INT_TYPE_ACL,\n *      - INT_TYPE_SLIENT\n */\nrtk_api_ret_t rtk_int_control_set(rtk_int_type_t type, rtk_enable_t enable)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32 mask;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if (type >= INT_TYPE_END)\n        return RT_ERR_INPUT;\n\n    if (type == INT_TYPE_RESERVED)\n        return RT_ERR_INPUT;\n\n    if ((retVal = rtl8367c_getAsicInterruptMask(&mask)) != RT_ERR_OK)\n        return retVal;\n\n    if (ENABLED == enable)\n        mask = mask | (1<<type);\n    else if (DISABLED == enable)\n        mask = mask & ~(1<<type);\n    else\n        return RT_ERR_INPUT;\n\n    if ((retVal = rtl8367c_setAsicInterruptMask(mask)) != RT_ERR_OK)\n        return retVal;\n\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_int_control_get\n * Description:\n *      Get interrupt trigger status configuration.\n * Input:\n *      type - Interrupt type.\n * Output:\n *      pEnable - Interrupt status.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n * Note:\n *      The API can get interrupt status configuration.\n *      The interrupt trigger status is shown in the following:\n *      - INT_TYPE_LINK_STATUS\n *      - INT_TYPE_METER_EXCEED\n *      - INT_TYPE_LEARN_LIMIT\n *      - INT_TYPE_LINK_SPEED\n *      - INT_TYPE_CONGEST\n *      - INT_TYPE_GREEN_FEATURE\n *      - INT_TYPE_LOOP_DETECT\n *      - INT_TYPE_8051,\n *      - INT_TYPE_CABLE_DIAG,\n *      - INT_TYPE_ACL,\n *      - INT_TYPE_UPS,\n *      - INT_TYPE_SLIENT\n */\nrtk_api_ret_t rtk_int_control_get(rtk_int_type_t type, rtk_enable_t *pEnable)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32 mask;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(NULL == pEnable)\n        return RT_ERR_NULL_POINTER;\n\n    if ((retVal = rtl8367c_getAsicInterruptMask(&mask)) != RT_ERR_OK)\n        return retVal;\n\n    if (0 == (mask&(1<<type)))\n        *pEnable=DISABLED;\n    else\n        *pEnable=ENABLED;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_int_status_set\n * Description:\n *      Set interrupt trigger status to clean.\n * Input:\n *      None\n * Output:\n *      pStatusMask - Interrupt status bit mask.\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n *      RT_ERR_INPUT - Invalid input parameters.\n * Note:\n *      The API can clean interrupt trigger status when interrupt happened.\n *      The interrupt trigger status is shown in the following:\n *      - INT_TYPE_LINK_STATUS    (value[0] (Bit0))\n *      - INT_TYPE_METER_EXCEED   (value[0] (Bit1))\n *      - INT_TYPE_LEARN_LIMIT    (value[0] (Bit2))\n *      - INT_TYPE_LINK_SPEED     (value[0] (Bit3))\n *      - INT_TYPE_CONGEST        (value[0] (Bit4))\n *      - INT_TYPE_GREEN_FEATURE  (value[0] (Bit5))\n *      - INT_TYPE_LOOP_DETECT    (value[0] (Bit6))\n *      - INT_TYPE_8051           (value[0] (Bit7))\n *      - INT_TYPE_CABLE_DIAG     (value[0] (Bit8))\n *      - INT_TYPE_ACL            (value[0] (Bit9))\n *      - INT_TYPE_SLIENT         (value[0] (Bit11))\n *      The status will be cleared after execute this API.\n */\nrtk_api_ret_t rtk_int_status_set(rtk_int_status_t *pStatusMask)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(NULL == pStatusMask)\n        return RT_ERR_NULL_POINTER;\n\n    if(pStatusMask->value[0] & (0x0001 << INT_TYPE_RESERVED))\n        return RT_ERR_INPUT;\n\n    if(pStatusMask->value[0] >= (0x0001 << INT_TYPE_END))\n        return RT_ERR_INPUT;\n\n    if ((retVal = rtl8367c_setAsicInterruptStatus((rtk_uint32)pStatusMask->value[0]))!=RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_int_status_get\n * Description:\n *      Get interrupt trigger status.\n * Input:\n *      None\n * Output:\n *      pStatusMask - Interrupt status bit mask.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n * Note:\n *      The API can get interrupt trigger status when interrupt happened.\n *      The interrupt trigger status is shown in the following:\n *      - INT_TYPE_LINK_STATUS    (value[0] (Bit0))\n *      - INT_TYPE_METER_EXCEED   (value[0] (Bit1))\n *      - INT_TYPE_LEARN_LIMIT    (value[0] (Bit2))\n *      - INT_TYPE_LINK_SPEED     (value[0] (Bit3))\n *      - INT_TYPE_CONGEST        (value[0] (Bit4))\n *      - INT_TYPE_GREEN_FEATURE  (value[0] (Bit5))\n *      - INT_TYPE_LOOP_DETECT    (value[0] (Bit6))\n *      - INT_TYPE_8051           (value[0] (Bit7))\n *      - INT_TYPE_CABLE_DIAG     (value[0] (Bit8))\n *      - INT_TYPE_ACL            (value[0] (Bit9))\n *      - INT_TYPE_SLIENT         (value[0] (Bit11))\n *\n */\nrtk_api_ret_t rtk_int_status_get(rtk_int_status_t* pStatusMask)\n{\n    rtk_api_ret_t   retVal;\n    rtk_uint32          ims_mask;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(NULL == pStatusMask)\n        return RT_ERR_NULL_POINTER;\n\n    if ((retVal = rtl8367c_getAsicInterruptStatus(&ims_mask)) != RT_ERR_OK)\n        return retVal;\n\n    pStatusMask->value[0] = (ims_mask & 0x00000FFF);\n    return RT_ERR_OK;\n}\n\n#define ADV_NOT_SUPPORT (0xFFFF)\nstatic rtk_api_ret_t _rtk_int_Advidx_get(rtk_int_advType_t adv_type, rtk_uint32 *pAsic_idx)\n{\n    rtk_uint32 asic_idx[ADV_END] =\n    {\n        INTRST_L2_LEARN,\n        INTRST_SPEED_CHANGE,\n        INTRST_SPECIAL_CONGESTION,\n        INTRST_PORT_LINKDOWN,\n        INTRST_PORT_LINKUP,\n        ADV_NOT_SUPPORT,\n        INTRST_RLDP_LOOPED,\n        INTRST_RLDP_RELEASED,\n    };\n\n    if(adv_type >= ADV_END)\n        return RT_ERR_INPUT;\n\n    if(asic_idx[adv_type] == ADV_NOT_SUPPORT)\n        return RT_ERR_CHIP_NOT_SUPPORTED;\n\n    *pAsic_idx = asic_idx[adv_type];\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_int_advanceInfo_get\n * Description:\n *      Get interrupt advanced information.\n * Input:\n *      adv_type - Advanced interrupt type.\n * Output:\n *      info - Information per type.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n * Note:\n *      This API can get advanced information when interrupt happened.\n *      The status will be cleared after execute this API.\n */\nrtk_api_ret_t rtk_int_advanceInfo_get(rtk_int_advType_t adv_type, rtk_int_info_t *pInfo)\n{\n    rtk_api_ret_t   retVal;\n    rtk_uint32      data;\n    rtk_uint32      intAdvType;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(adv_type >= ADV_END)\n        return RT_ERR_INPUT;\n\n    if(NULL == pInfo)\n        return RT_ERR_NULL_POINTER;\n\n    if(adv_type != ADV_METER_EXCEED_MASK)\n    {\n        if((retVal = _rtk_int_Advidx_get(adv_type, &intAdvType)) != RT_ERR_OK)\n            return retVal;\n    }\n\n    switch(adv_type)\n    {\n        case ADV_L2_LEARN_PORT_MASK:\n            /* Get physical portmask */\n            if((retVal = rtl8367c_getAsicInterruptRelatedStatus(intAdvType, &data)) != RT_ERR_OK)\n                return retVal;\n\n            /* Clear Advanced Info */\n            if((retVal = rtl8367c_setAsicInterruptRelatedStatus(intAdvType, 0xFFFF)) != RT_ERR_OK)\n                return retVal;\n\n            /* Translate to logical portmask */\n            if((retVal = rtk_switch_portmask_P2L_get(data, &(pInfo->portMask))) != RT_ERR_OK)\n                return retVal;\n\n            /* Get system learn */\n            if((retVal = rtl8367c_getAsicInterruptRelatedStatus(INTRST_SYS_LEARN, &data)) != RT_ERR_OK)\n                return retVal;\n\n            /* Clear system learn */\n            if((retVal = rtl8367c_setAsicInterruptRelatedStatus(INTRST_SYS_LEARN, 0x0001)) != RT_ERR_OK)\n                return retVal;\n\n            pInfo->systemLearnOver = data;\n            break;\n        case ADV_SPEED_CHANGE_PORT_MASK:\n        case ADV_SPECIAL_CONGESTION_PORT_MASK:\n        case ADV_PORT_LINKDOWN_PORT_MASK:\n        case ADV_PORT_LINKUP_PORT_MASK:\n        case ADV_RLDP_LOOPED:\n        case ADV_RLDP_RELEASED:\n            /* Get physical portmask */\n            if((retVal = rtl8367c_getAsicInterruptRelatedStatus(intAdvType, &data)) != RT_ERR_OK)\n                return retVal;\n\n            /* Clear Advanced Info */\n            if((retVal = rtl8367c_setAsicInterruptRelatedStatus(intAdvType, 0xFFFF)) != RT_ERR_OK)\n                return retVal;\n\n            /* Translate to logical portmask */\n            if((retVal = rtk_switch_portmask_P2L_get(data, &(pInfo->portMask))) != RT_ERR_OK)\n                return retVal;\n\n            break;\n        case ADV_METER_EXCEED_MASK:\n            /* Get Meter Mask */\n            if((retVal = rtl8367c_getAsicInterruptRelatedStatus(INTRST_METER0_15, &data)) != RT_ERR_OK)\n                return retVal;\n\n            /* Clear Advanced Info */\n            if((retVal = rtl8367c_setAsicInterruptRelatedStatus(INTRST_METER0_15, 0xFFFF)) != RT_ERR_OK)\n                return retVal;\n\n            pInfo->meterMask = data & 0xFFFF;\n\n            /* Get Meter Mask */\n            if((retVal = rtl8367c_getAsicInterruptRelatedStatus(INTRST_METER16_31, &data)) != RT_ERR_OK)\n                return retVal;\n\n            /* Clear Advanced Info */\n            if((retVal = rtl8367c_setAsicInterruptRelatedStatus(INTRST_METER16_31, 0xFFFF)) != RT_ERR_OK)\n                return retVal;\n\n            pInfo->meterMask = pInfo->meterMask | ((data << 16) & 0xFFFF0000);\n\n            break;\n        default:\n            return RT_ERR_INPUT;\n    }\n\n    return RT_ERR_OK;\n}\n\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/l2.c",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * $Revision: 76306 $\n * $Date: 2017-03-08 15:13:58 +0800 (週三, 08 三月 2017) $\n *\n * Purpose : RTK switch high-level API for RTL8367/RTL8367C\n * Feature : Here is a list of all functions and variables in L2 module.\n *\n */\n\n#include <rtk_switch.h>\n#include <rtk_error.h>\n#include <l2.h>\n#include <string.h>\n\n#include <rtl8367c_asicdrv.h>\n#include <rtl8367c_asicdrv_lut.h>\n#include <rtl8367c_asicdrv_port.h>\n\n/* Function Name:\n *      rtk_l2_init\n * Description:\n *      Initialize l2 module of the specified device.\n * Input:\n *      None\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK          - OK\n *      RT_ERR_FAILED      - Failed\n *      RT_ERR_SMI         - SMI access error\n * Note:\n *      Initialize l2 module before calling any l2 APIs.\n */\nrtk_api_ret_t rtk_l2_init(void)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32 port;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if ((retVal = rtl8367c_setAsicLutIpMulticastLookup(DISABLED)) != RT_ERR_OK)\n        return retVal;\n\n    /*Enable CAM Usage*/\n    if ((retVal = rtl8367c_setAsicLutCamTbUsage(ENABLED)) != RT_ERR_OK)\n        return retVal;\n\n    if ((retVal = rtl8367c_setAsicLutAgeTimerSpeed(6,2)) != RT_ERR_OK)\n        return retVal;\n\n    RTK_SCAN_ALL_LOG_PORT(port)\n    {\n        if ((retVal = rtl8367c_setAsicLutLearnLimitNo(rtk_switch_port_L2P_get(port), rtk_switch_maxLutAddrNumber_get())) != RT_ERR_OK)\n            return retVal;\n    }\n\n    return RT_ERR_OK;\n}\n\n\n/* Function Name:\n *      rtk_l2_addr_add\n * Description:\n *      Add LUT unicast entry.\n * Input:\n *      pMac - 6 bytes unicast(I/G bit is 0) mac address to be written into LUT.\n *      pL2_data - Unicast entry parameter\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - OK\n *      RT_ERR_FAILED           - Failed\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_PORT_ID          - Invalid port number.\n *      RT_ERR_MAC              - Invalid MAC address.\n *      RT_ERR_L2_FID           - Invalid FID .\n *      RT_ERR_L2_INDEXTBL_FULL - hashed index is full of entries.\n *      RT_ERR_INPUT            - Invalid input parameters.\n * Note:\n *      If the unicast mac address already existed in LUT, it will udpate the status of the entry.\n *      Otherwise, it will find an empty or asic auto learned entry to write. If all the entries\n *      with the same hash value can't be replaced, ASIC will return a RT_ERR_L2_INDEXTBL_FULL error.\n */\nrtk_api_ret_t rtk_l2_addr_add(rtk_mac_t *pMac, rtk_l2_ucastAddr_t *pL2_data)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32 method;\n    rtl8367c_luttb l2Table;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* must be unicast address */\n    if ((pMac == NULL) || (pMac->octet[0] & 0x1))\n        return RT_ERR_MAC;\n\n    if(pL2_data == NULL)\n        return RT_ERR_MAC;\n\n    RTK_CHK_PORT_VALID(pL2_data->port);\n\n    if (pL2_data->ivl >= RTK_ENABLE_END)\n        return RT_ERR_INPUT;\n\n    if (pL2_data->cvid > RTL8367C_VIDMAX)\n        return RT_ERR_L2_VID;\n\n    if (pL2_data->fid > RTL8367C_FIDMAX)\n        return RT_ERR_L2_FID;\n\n    if (pL2_data->is_static>= RTK_ENABLE_END)\n        return RT_ERR_INPUT;\n\n    if (pL2_data->sa_block>= RTK_ENABLE_END)\n        return RT_ERR_INPUT;\n\n    if (pL2_data->da_block>= RTK_ENABLE_END)\n        return RT_ERR_INPUT;\n\n    if (pL2_data->auth>= RTK_ENABLE_END)\n        return RT_ERR_INPUT;\n\n    if (pL2_data->efid> RTL8367C_EFIDMAX)\n        return RT_ERR_INPUT;\n\n    if (pL2_data->priority > RTL8367C_PRIMAX)\n        return RT_ERR_INPUT;\n\n    if (pL2_data->sa_pri_en >= RTK_ENABLE_END)\n        return RT_ERR_INPUT;\n\n    if (pL2_data->fwd_pri_en >= RTK_ENABLE_END)\n        return RT_ERR_INPUT;\n\n    memset(&l2Table, 0, sizeof(rtl8367c_luttb));\n\n    /* fill key (MAC,FID) to get L2 entry */\n    memcpy(l2Table.mac.octet, pMac->octet, ETHER_ADDR_LEN);\n    l2Table.ivl_svl     = pL2_data->ivl;\n    l2Table.fid         = pL2_data->fid;\n    l2Table.cvid_fid    = pL2_data->cvid;\n    l2Table.efid        = pL2_data->efid;\n    method = LUTREADMETHOD_MAC;\n    retVal = rtl8367c_getAsicL2LookupTb(method, &l2Table);\n    if (RT_ERR_OK == retVal )\n    {\n        memcpy(l2Table.mac.octet, pMac->octet, ETHER_ADDR_LEN);\n        l2Table.ivl_svl     = pL2_data->ivl;\n        l2Table.cvid_fid    = pL2_data->cvid;\n        l2Table.fid         = pL2_data->fid;\n        l2Table.efid        = pL2_data->efid;\n        l2Table.spa         = rtk_switch_port_L2P_get(pL2_data->port);\n        l2Table.nosalearn   = pL2_data->is_static;\n        l2Table.sa_block    = pL2_data->sa_block;\n        l2Table.da_block    = pL2_data->da_block;\n        l2Table.l3lookup    = 0;\n        l2Table.auth        = pL2_data->auth;\n        l2Table.age         = 6;\n        l2Table.lut_pri     = pL2_data->priority;\n        l2Table.sa_en       = pL2_data->sa_pri_en;\n        l2Table.fwd_en      = pL2_data->fwd_pri_en;\n        if((retVal = rtl8367c_setAsicL2LookupTb(&l2Table)) != RT_ERR_OK)\n            return retVal;\n\n        pL2_data->address = l2Table.address;\n        return RT_ERR_OK;\n    }\n    else if (RT_ERR_L2_ENTRY_NOTFOUND == retVal )\n    {\n        memset(&l2Table, 0, sizeof(rtl8367c_luttb));\n        memcpy(l2Table.mac.octet, pMac->octet, ETHER_ADDR_LEN);\n        l2Table.ivl_svl     = pL2_data->ivl;\n        l2Table.cvid_fid    = pL2_data->cvid;\n        l2Table.fid         = pL2_data->fid;\n        l2Table.efid        = pL2_data->efid;\n        l2Table.spa         = rtk_switch_port_L2P_get(pL2_data->port);\n        l2Table.nosalearn   = pL2_data->is_static;\n        l2Table.sa_block    = pL2_data->sa_block;\n        l2Table.da_block    = pL2_data->da_block;\n        l2Table.l3lookup    = 0;\n        l2Table.auth        = pL2_data->auth;\n        l2Table.age         = 6;\n        l2Table.lut_pri     = pL2_data->priority;\n        l2Table.sa_en       = pL2_data->sa_pri_en;\n        l2Table.fwd_en      = pL2_data->fwd_pri_en;\n\n        if ((retVal = rtl8367c_setAsicL2LookupTb(&l2Table)) != RT_ERR_OK)\n            return retVal;\n\n        pL2_data->address = l2Table.address;\n\n        method = LUTREADMETHOD_MAC;\n        retVal = rtl8367c_getAsicL2LookupTb(method, &l2Table);\n        if (RT_ERR_L2_ENTRY_NOTFOUND == retVal )\n            return RT_ERR_L2_INDEXTBL_FULL;\n        else\n            return retVal;\n    }\n    else\n        return retVal;\n\n}\n\n/* Function Name:\n *      rtk_l2_addr_get\n * Description:\n *      Get LUT unicast entry.\n * Input:\n *      pMac    - 6 bytes unicast(I/G bit is 0) mac address to be written into LUT.\n * Output:\n *      pL2_data - Unicast entry parameter\n * Return:\n *      RT_ERR_OK                   - OK\n *      RT_ERR_FAILED               - Failed\n *      RT_ERR_SMI                  - SMI access error\n *      RT_ERR_PORT_ID              - Invalid port number.\n *      RT_ERR_MAC                  - Invalid MAC address.\n *      RT_ERR_L2_FID               - Invalid FID .\n *      RT_ERR_L2_ENTRY_NOTFOUND    - No such LUT entry.\n *      RT_ERR_INPUT                - Invalid input parameters.\n * Note:\n *      If the unicast mac address existed in LUT, it will return the port and fid where\n *      the mac is learned. Otherwise, it will return a RT_ERR_L2_ENTRY_NOTFOUND error.\n */\nrtk_api_ret_t rtk_l2_addr_get(rtk_mac_t *pMac, rtk_l2_ucastAddr_t *pL2_data)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32 method;\n    rtl8367c_luttb l2Table;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* must be unicast address */\n    if ((pMac == NULL) || (pMac->octet[0] & 0x1))\n        return RT_ERR_MAC;\n\n    if (pL2_data->fid > RTL8367C_FIDMAX || pL2_data->efid > RTL8367C_EFIDMAX)\n        return RT_ERR_L2_FID;\n\n    memset(&l2Table, 0, sizeof(rtl8367c_luttb));\n\n    memcpy(l2Table.mac.octet, pMac->octet, ETHER_ADDR_LEN);\n    l2Table.ivl_svl     = pL2_data->ivl;\n    l2Table.cvid_fid    = pL2_data->cvid;\n    l2Table.fid         = pL2_data->fid;\n    l2Table.efid        = pL2_data->efid;\n    method = LUTREADMETHOD_MAC;\n\n    if ((retVal = rtl8367c_getAsicL2LookupTb(method, &l2Table)) != RT_ERR_OK)\n        return retVal;\n\n    memcpy(pL2_data->mac.octet, pMac->octet,ETHER_ADDR_LEN);\n    pL2_data->port      = rtk_switch_port_P2L_get(l2Table.spa);\n    pL2_data->fid       = l2Table.fid;\n    pL2_data->efid      = l2Table.efid;\n    pL2_data->ivl       = l2Table.ivl_svl;\n    pL2_data->cvid      = l2Table.cvid_fid;\n    pL2_data->is_static = l2Table.nosalearn;\n    pL2_data->auth      = l2Table.auth;\n    pL2_data->sa_block  = l2Table.sa_block;\n    pL2_data->da_block  = l2Table.da_block;\n    pL2_data->priority  = l2Table.lut_pri;\n    pL2_data->sa_pri_en = l2Table.sa_en;\n    pL2_data->fwd_pri_en= l2Table.fwd_en;\n    pL2_data->address   = l2Table.address;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_l2_addr_next_get\n * Description:\n *      Get Next LUT unicast entry.\n * Input:\n *      read_method     - The reading method.\n *      port            - The port number if the read_metohd is READMETHOD_NEXT_L2UCSPA\n *      pAddress        - The Address ID\n * Output:\n *      pL2_data - Unicast entry parameter\n * Return:\n *      RT_ERR_OK                   - OK\n *      RT_ERR_FAILED               - Failed\n *      RT_ERR_SMI                  - SMI access error\n *      RT_ERR_PORT_ID              - Invalid port number.\n *      RT_ERR_MAC                  - Invalid MAC address.\n *      RT_ERR_L2_FID               - Invalid FID .\n *      RT_ERR_L2_ENTRY_NOTFOUND    - No such LUT entry.\n *      RT_ERR_INPUT                - Invalid input parameters.\n * Note:\n *      Get the next unicast entry after the current entry pointed by pAddress.\n *      The address of next entry is returned by pAddress. User can use (address + 1)\n *      as pAddress to call this API again for dumping all entries is LUT.\n */\nrtk_api_ret_t rtk_l2_addr_next_get(rtk_l2_read_method_t read_method, rtk_port_t port, rtk_uint32 *pAddress, rtk_l2_ucastAddr_t *pL2_data)\n{\n    rtk_api_ret_t   retVal;\n    rtk_uint32      method;\n    rtl8367c_luttb  l2Table;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Error Checking */\n    if ((pL2_data == NULL) || (pAddress == NULL))\n        return RT_ERR_MAC;\n\n    if(read_method == READMETHOD_NEXT_L2UC)\n        method = LUTREADMETHOD_NEXT_L2UC;\n    else if(read_method == READMETHOD_NEXT_L2UCSPA)\n        method = LUTREADMETHOD_NEXT_L2UCSPA;\n    else\n        return RT_ERR_INPUT;\n\n    /* Check Port Valid */\n    RTK_CHK_PORT_VALID(port);\n\n    if(*pAddress > RTK_MAX_LUT_ADDR_ID )\n        return RT_ERR_L2_L2UNI_PARAM;\n\n    memset(&l2Table, 0, sizeof(rtl8367c_luttb));\n    l2Table.address = *pAddress;\n\n    if(read_method == READMETHOD_NEXT_L2UCSPA)\n        l2Table.spa = rtk_switch_port_L2P_get(port);\n\n    if ((retVal = rtl8367c_getAsicL2LookupTb(method, &l2Table)) != RT_ERR_OK)\n        return retVal;\n\n    if(l2Table.address < *pAddress)\n        return RT_ERR_L2_ENTRY_NOTFOUND;\n\n    memcpy(pL2_data->mac.octet, l2Table.mac.octet, ETHER_ADDR_LEN);\n    pL2_data->port      = rtk_switch_port_P2L_get(l2Table.spa);\n    pL2_data->fid       = l2Table.fid;\n    pL2_data->efid      = l2Table.efid;\n    pL2_data->ivl       = l2Table.ivl_svl;\n    pL2_data->cvid      = l2Table.cvid_fid;\n    pL2_data->is_static = l2Table.nosalearn;\n    pL2_data->auth      = l2Table.auth;\n    pL2_data->sa_block  = l2Table.sa_block;\n    pL2_data->da_block  = l2Table.da_block;\n    pL2_data->priority  = l2Table.lut_pri;\n    pL2_data->sa_pri_en = l2Table.sa_en;\n    pL2_data->fwd_pri_en= l2Table.fwd_en;\n    pL2_data->address   = l2Table.address;\n\n    *pAddress = l2Table.address;\n\n    return RT_ERR_OK;\n\n}\n\n/* Function Name:\n *      rtk_l2_addr_del\n * Description:\n *      Delete LUT unicast entry.\n * Input:\n *      pMac - 6 bytes unicast(I/G bit is 0) mac address to be written into LUT.\n *      fid - Filtering database\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK                   - OK\n *      RT_ERR_FAILED               - Failed\n *      RT_ERR_SMI                  - SMI access error\n *      RT_ERR_PORT_ID              - Invalid port number.\n *      RT_ERR_MAC                  - Invalid MAC address.\n *      RT_ERR_L2_FID               - Invalid FID .\n *      RT_ERR_L2_ENTRY_NOTFOUND    - No such LUT entry.\n *      RT_ERR_INPUT                - Invalid input parameters.\n * Note:\n *      If the mac has existed in the LUT, it will be deleted. Otherwise, it will return RT_ERR_L2_ENTRY_NOTFOUND.\n */\nrtk_api_ret_t rtk_l2_addr_del(rtk_mac_t *pMac, rtk_l2_ucastAddr_t *pL2_data)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32 method;\n    rtl8367c_luttb l2Table;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* must be unicast address */\n    if ((pMac == NULL) || (pMac->octet[0] & 0x1))\n        return RT_ERR_MAC;\n\n    if (pL2_data->fid > RTL8367C_FIDMAX || pL2_data->efid > RTL8367C_EFIDMAX)\n        return RT_ERR_L2_FID;\n\n    memset(&l2Table, 0, sizeof(rtl8367c_luttb));\n\n    /* fill key (MAC,FID) to get L2 entry */\n    memcpy(l2Table.mac.octet, pMac->octet, ETHER_ADDR_LEN);\n    l2Table.ivl_svl     = pL2_data->ivl;\n    l2Table.cvid_fid    = pL2_data->cvid;\n    l2Table.fid         = pL2_data->fid;\n    l2Table.efid        = pL2_data->efid;\n    method = LUTREADMETHOD_MAC;\n    retVal = rtl8367c_getAsicL2LookupTb(method, &l2Table);\n    if (RT_ERR_OK ==  retVal)\n    {\n        memcpy(l2Table.mac.octet, pMac->octet, ETHER_ADDR_LEN);\n        l2Table.ivl_svl     = pL2_data->ivl;\n        l2Table.cvid_fid    = pL2_data->cvid;\n        l2Table.fid = pL2_data->fid;\n        l2Table.efid = pL2_data->efid;\n        l2Table.spa = 0;\n        l2Table.nosalearn = 0;\n        l2Table.sa_block = 0;\n        l2Table.da_block = 0;\n        l2Table.auth = 0;\n        l2Table.age = 0;\n        l2Table.lut_pri = 0;\n        l2Table.sa_en = 0;\n        l2Table.fwd_en = 0;\n        if((retVal = rtl8367c_setAsicL2LookupTb(&l2Table)) != RT_ERR_OK)\n            return retVal;\n\n        pL2_data->address = l2Table.address;\n        return RT_ERR_OK;\n    }\n    else\n        return retVal;\n}\n\n/* Function Name:\n *      rtk_l2_mcastAddr_add\n * Description:\n *      Add LUT multicast entry.\n * Input:\n *      pMcastAddr  - L2 multicast entry structure\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - OK\n *      RT_ERR_FAILED           - Failed\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_PORT_ID          - Invalid port number.\n *      RT_ERR_MAC              - Invalid MAC address.\n *      RT_ERR_L2_FID           - Invalid FID .\n *      RT_ERR_L2_VID           - Invalid VID .\n *      RT_ERR_L2_INDEXTBL_FULL - hashed index is full of entries.\n *      RT_ERR_PORT_MASK        - Invalid portmask.\n *      RT_ERR_INPUT            - Invalid input parameters.\n * Note:\n *      If the multicast mac address already existed in the LUT, it will udpate the\n *      port mask of the entry. Otherwise, it will find an empty or asic auto learned\n *      entry to write. If all the entries with the same hash value can't be replaced,\n *      ASIC will return a RT_ERR_L2_INDEXTBL_FULL error.\n */\nrtk_api_ret_t rtk_l2_mcastAddr_add(rtk_l2_mcastAddr_t *pMcastAddr)\n{\n    rtk_api_ret_t   retVal;\n    rtk_uint32      method;\n    rtl8367c_luttb  l2Table;\n    rtk_uint32      pmask;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(NULL == pMcastAddr)\n        return RT_ERR_NULL_POINTER;\n\n    /* must be L2 multicast address */\n    if( (pMcastAddr->mac.octet[0] & 0x01) != 0x01)\n        return RT_ERR_MAC;\n\n    RTK_CHK_PORTMASK_VALID(&pMcastAddr->portmask);\n\n    if(pMcastAddr->ivl == 1)\n    {\n        if (pMcastAddr->vid > RTL8367C_VIDMAX)\n            return RT_ERR_L2_VID;\n    }\n    else if(pMcastAddr->ivl == 0)\n    {\n        if (pMcastAddr->fid > RTL8367C_FIDMAX)\n            return RT_ERR_L2_FID;\n    }\n    else\n        return RT_ERR_INPUT;\n\n    if(pMcastAddr->fwd_pri_en >= RTK_ENABLE_END)\n        return RT_ERR_INPUT;\n\n    if(pMcastAddr->priority > RTL8367C_PRIMAX)\n        return RT_ERR_INPUT;\n\n    /* Get physical port mask */\n    if ((retVal = rtk_switch_portmask_L2P_get(&pMcastAddr->portmask, &pmask)) != RT_ERR_OK)\n        return retVal;\n\n    memset(&l2Table, 0, sizeof(rtl8367c_luttb));\n\n    /* fill key (MAC,FID) to get L2 entry */\n    memcpy(l2Table.mac.octet, pMcastAddr->mac.octet, ETHER_ADDR_LEN);\n    l2Table.ivl_svl     = pMcastAddr->ivl;\n\n    if(pMcastAddr->ivl)\n        l2Table.cvid_fid    = pMcastAddr->vid;\n    else\n        l2Table.cvid_fid    = pMcastAddr->fid;\n\n    method = LUTREADMETHOD_MAC;\n    retVal = rtl8367c_getAsicL2LookupTb(method, &l2Table);\n    if (RT_ERR_OK == retVal)\n    {\n        memcpy(l2Table.mac.octet, pMcastAddr->mac.octet, ETHER_ADDR_LEN);\n        l2Table.ivl_svl     = pMcastAddr->ivl;\n\n        if(pMcastAddr->ivl)\n            l2Table.cvid_fid    = pMcastAddr->vid;\n        else\n            l2Table.cvid_fid    = pMcastAddr->fid;\n\n        l2Table.mbr         = pmask;\n        l2Table.nosalearn   = 1;\n        l2Table.l3lookup    = 0;\n        l2Table.lut_pri     = pMcastAddr->priority;\n        l2Table.fwd_en      = pMcastAddr->fwd_pri_en;\n        if((retVal = rtl8367c_setAsicL2LookupTb(&l2Table)) != RT_ERR_OK)\n            return retVal;\n\n        pMcastAddr->address = l2Table.address;\n        return RT_ERR_OK;\n    }\n    else if (RT_ERR_L2_ENTRY_NOTFOUND == retVal)\n    {\n        memset(&l2Table, 0, sizeof(rtl8367c_luttb));\n        memcpy(l2Table.mac.octet, pMcastAddr->mac.octet, ETHER_ADDR_LEN);\n        l2Table.ivl_svl     = pMcastAddr->ivl;\n        if(pMcastAddr->ivl)\n            l2Table.cvid_fid    = pMcastAddr->vid;\n        else\n            l2Table.cvid_fid    = pMcastAddr->fid;\n\n        l2Table.mbr         = pmask;\n        l2Table.nosalearn   = 1;\n        l2Table.l3lookup    = 0;\n        l2Table.lut_pri     = pMcastAddr->priority;\n        l2Table.fwd_en      = pMcastAddr->fwd_pri_en;\n        if ((retVal = rtl8367c_setAsicL2LookupTb(&l2Table)) != RT_ERR_OK)\n            return retVal;\n\n        pMcastAddr->address = l2Table.address;\n\n        method = LUTREADMETHOD_MAC;\n        retVal = rtl8367c_getAsicL2LookupTb(method, &l2Table);\n        if (RT_ERR_L2_ENTRY_NOTFOUND == retVal)\n            return     RT_ERR_L2_INDEXTBL_FULL;\n        else\n            return retVal;\n    }\n    else\n        return retVal;\n\n}\n\n/* Function Name:\n *      rtk_l2_mcastAddr_get\n * Description:\n *      Get LUT multicast entry.\n * Input:\n *      pMcastAddr  - L2 multicast entry structure\n * Output:\n *      pMcastAddr  - L2 multicast entry structure\n * Return:\n *      RT_ERR_OK                   - OK\n *      RT_ERR_FAILED               - Failed\n *      RT_ERR_SMI                  - SMI access error\n *      RT_ERR_MAC                  - Invalid MAC address.\n *      RT_ERR_L2_FID               - Invalid FID .\n *      RT_ERR_L2_VID               - Invalid VID .\n *      RT_ERR_L2_ENTRY_NOTFOUND    - No such LUT entry.\n *      RT_ERR_INPUT                - Invalid input parameters.\n * Note:\n *      If the multicast mac address existed in the LUT, it will return the port where\n *      the mac is learned. Otherwise, it will return a RT_ERR_L2_ENTRY_NOTFOUND error.\n */\nrtk_api_ret_t rtk_l2_mcastAddr_get(rtk_l2_mcastAddr_t *pMcastAddr)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32 method;\n    rtl8367c_luttb l2Table;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(NULL == pMcastAddr)\n        return RT_ERR_NULL_POINTER;\n\n    /* must be L2 multicast address */\n    if( (pMcastAddr->mac.octet[0] & 0x01) != 0x01)\n        return RT_ERR_MAC;\n\n    if(pMcastAddr->ivl == 1)\n    {\n        if (pMcastAddr->vid > RTL8367C_VIDMAX)\n            return RT_ERR_L2_VID;\n    }\n    else if(pMcastAddr->ivl == 0)\n    {\n        if (pMcastAddr->fid > RTL8367C_FIDMAX)\n            return RT_ERR_L2_FID;\n    }\n    else\n        return RT_ERR_INPUT;\n\n    memset(&l2Table, 0, sizeof(rtl8367c_luttb));\n    memcpy(l2Table.mac.octet, pMcastAddr->mac.octet, ETHER_ADDR_LEN);\n    l2Table.ivl_svl     = pMcastAddr->ivl;\n\n    if(pMcastAddr->ivl)\n        l2Table.cvid_fid    = pMcastAddr->vid;\n    else\n        l2Table.cvid_fid    = pMcastAddr->fid;\n\n    method = LUTREADMETHOD_MAC;\n\n    if ((retVal = rtl8367c_getAsicL2LookupTb(method, &l2Table)) != RT_ERR_OK)\n        return retVal;\n\n    pMcastAddr->priority    = l2Table.lut_pri;\n    pMcastAddr->fwd_pri_en  = l2Table.fwd_en;\n    pMcastAddr->igmp_asic   = l2Table.igmp_asic;\n    pMcastAddr->igmp_index  = l2Table.igmpidx;\n    pMcastAddr->address     = l2Table.address;\n\n    /* Get Logical port mask */\n    if ((retVal = rtk_switch_portmask_P2L_get(l2Table.mbr, &pMcastAddr->portmask)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_l2_mcastAddr_next_get\n * Description:\n *      Get Next L2 Multicast entry.\n * Input:\n *      pAddress        - The Address ID\n * Output:\n *      pMcastAddr  - L2 multicast entry structure\n * Return:\n *      RT_ERR_OK                   - OK\n *      RT_ERR_FAILED               - Failed\n *      RT_ERR_SMI                  - SMI access error\n *      RT_ERR_L2_ENTRY_NOTFOUND    - No such LUT entry.\n *      RT_ERR_INPUT                - Invalid input parameters.\n * Note:\n *      Get the next L2 multicast entry after the current entry pointed by pAddress.\n *      The address of next entry is returned by pAddress. User can use (address + 1)\n *      as pAddress to call this API again for dumping all multicast entries is LUT.\n */\nrtk_api_ret_t rtk_l2_mcastAddr_next_get(rtk_uint32 *pAddress, rtk_l2_mcastAddr_t *pMcastAddr)\n{\n    rtk_api_ret_t   retVal;\n    rtl8367c_luttb  l2Table;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Error Checking */\n    if ((pAddress == NULL) || (pMcastAddr == NULL))\n        return RT_ERR_INPUT;\n\n    if(*pAddress > RTK_MAX_LUT_ADDR_ID )\n        return RT_ERR_L2_L2UNI_PARAM;\n\n    memset(&l2Table, 0, sizeof(rtl8367c_luttb));\n    l2Table.address = *pAddress;\n\n    if ((retVal = rtl8367c_getAsicL2LookupTb(LUTREADMETHOD_NEXT_L2MC, &l2Table)) != RT_ERR_OK)\n        return retVal;\n\n    if(l2Table.address < *pAddress)\n        return RT_ERR_L2_ENTRY_NOTFOUND;\n\n    memcpy(pMcastAddr->mac.octet, l2Table.mac.octet, ETHER_ADDR_LEN);\n    pMcastAddr->ivl     = l2Table.ivl_svl;\n\n    if(pMcastAddr->ivl)\n        pMcastAddr->vid = l2Table.cvid_fid;\n    else\n        pMcastAddr->fid = l2Table.cvid_fid;\n\n    pMcastAddr->priority    = l2Table.lut_pri;\n    pMcastAddr->fwd_pri_en  = l2Table.fwd_en;\n    pMcastAddr->igmp_asic   = l2Table.igmp_asic;\n    pMcastAddr->igmp_index  = l2Table.igmpidx;\n    pMcastAddr->address     = l2Table.address;\n\n    /* Get Logical port mask */\n    if ((retVal = rtk_switch_portmask_P2L_get(l2Table.mbr, &pMcastAddr->portmask)) != RT_ERR_OK)\n        return retVal;\n\n    *pAddress = l2Table.address;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_l2_mcastAddr_del\n * Description:\n *      Delete LUT multicast entry.\n * Input:\n *      pMcastAddr  - L2 multicast entry structure\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK                   - OK\n *      RT_ERR_FAILED               - Failed\n *      RT_ERR_SMI                  - SMI access error\n *      RT_ERR_MAC                  - Invalid MAC address.\n *      RT_ERR_L2_FID               - Invalid FID .\n *      RT_ERR_L2_VID               - Invalid VID .\n *      RT_ERR_L2_ENTRY_NOTFOUND    - No such LUT entry.\n *      RT_ERR_INPUT                - Invalid input parameters.\n * Note:\n *      If the mac has existed in the LUT, it will be deleted. Otherwise, it will return RT_ERR_L2_ENTRY_NOTFOUND.\n */\nrtk_api_ret_t rtk_l2_mcastAddr_del(rtk_l2_mcastAddr_t *pMcastAddr)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32 method;\n    rtl8367c_luttb l2Table;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(NULL == pMcastAddr)\n        return RT_ERR_NULL_POINTER;\n\n    /* must be L2 multicast address */\n    if( (pMcastAddr->mac.octet[0] & 0x01) != 0x01)\n        return RT_ERR_MAC;\n\n    if(pMcastAddr->ivl == 1)\n    {\n        if (pMcastAddr->vid > RTL8367C_VIDMAX)\n            return RT_ERR_L2_VID;\n    }\n    else if(pMcastAddr->ivl == 0)\n    {\n        if (pMcastAddr->fid > RTL8367C_FIDMAX)\n            return RT_ERR_L2_FID;\n    }\n    else\n        return RT_ERR_INPUT;\n\n    memset(&l2Table, 0, sizeof(rtl8367c_luttb));\n\n    /* fill key (MAC,FID) to get L2 entry */\n    memcpy(l2Table.mac.octet, pMcastAddr->mac.octet, ETHER_ADDR_LEN);\n    l2Table.ivl_svl     = pMcastAddr->ivl;\n\n    if(pMcastAddr->ivl)\n        l2Table.cvid_fid    = pMcastAddr->vid;\n    else\n        l2Table.cvid_fid    = pMcastAddr->fid;\n\n    method = LUTREADMETHOD_MAC;\n    retVal = rtl8367c_getAsicL2LookupTb(method, &l2Table);\n    if (RT_ERR_OK == retVal)\n    {\n        memcpy(l2Table.mac.octet, pMcastAddr->mac.octet, ETHER_ADDR_LEN);\n        l2Table.ivl_svl     = pMcastAddr->ivl;\n\n        if(pMcastAddr->ivl)\n            l2Table.cvid_fid    = pMcastAddr->vid;\n        else\n            l2Table.cvid_fid    = pMcastAddr->fid;\n\n        l2Table.mbr         = 0;\n        l2Table.nosalearn   = 0;\n        l2Table.sa_block    = 0;\n        l2Table.l3lookup    = 0;\n        l2Table.lut_pri     = 0;\n        l2Table.fwd_en      = 0;\n        if((retVal = rtl8367c_setAsicL2LookupTb(&l2Table)) != RT_ERR_OK)\n            return retVal;\n\n        pMcastAddr->address = l2Table.address;\n        return RT_ERR_OK;\n    }\n    else\n        return retVal;\n}\n\n/* Function Name:\n *      rtk_l2_ipMcastAddr_add\n * Description:\n *      Add Lut IP multicast entry\n * Input:\n *      pIpMcastAddr    - IP Multicast entry\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - OK\n *      RT_ERR_FAILED           - Failed\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_PORT_ID          - Invalid port number.\n *      RT_ERR_L2_INDEXTBL_FULL - hashed index is full of entries.\n *      RT_ERR_PORT_MASK        - Invalid portmask.\n *      RT_ERR_INPUT            - Invalid input parameters.\n * Note:\n *      System supports L2 entry with IP multicast DIP/SIP to forward IP multicasting frame as user\n *      desired. If this function is enabled, then system will be looked up L2 IP multicast entry to\n *      forward IP multicast frame directly without flooding.\n */\nrtk_api_ret_t rtk_l2_ipMcastAddr_add(rtk_l2_ipMcastAddr_t *pIpMcastAddr)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32 method;\n    rtl8367c_luttb l2Table;\n    rtk_uint32 pmask;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(NULL == pIpMcastAddr)\n        return RT_ERR_NULL_POINTER;\n\n    /* check port mask */\n    RTK_CHK_PORTMASK_VALID(&pIpMcastAddr->portmask);\n\n    if( (pIpMcastAddr->dip & 0xF0000000) != 0xE0000000)\n        return RT_ERR_INPUT;\n\n    if(pIpMcastAddr->fwd_pri_en >= RTK_ENABLE_END)\n        return RT_ERR_ENABLE;\n\n    if(pIpMcastAddr->priority > RTL8367C_PRIMAX)\n        return RT_ERR_INPUT;\n\n    /* Get Physical port mask */\n    if ((retVal = rtk_switch_portmask_L2P_get(&pIpMcastAddr->portmask, &pmask)) != RT_ERR_OK)\n        return retVal;\n\n    memset(&l2Table, 0x00, sizeof(rtl8367c_luttb));\n    l2Table.sip = pIpMcastAddr->sip;\n    l2Table.dip = pIpMcastAddr->dip;\n    l2Table.l3lookup = 1;\n    l2Table.l3vidlookup = 0;\n    method = LUTREADMETHOD_MAC;\n    retVal = rtl8367c_getAsicL2LookupTb(method, &l2Table);\n    if (RT_ERR_OK == retVal)\n    {\n        l2Table.sip = pIpMcastAddr->sip;\n        l2Table.dip = pIpMcastAddr->dip;\n        l2Table.mbr = pmask;\n        l2Table.nosalearn = 1;\n        l2Table.l3lookup = 1;\n        l2Table.l3vidlookup = 0;\n        l2Table.lut_pri = pIpMcastAddr->priority;\n        l2Table.fwd_en  = pIpMcastAddr->fwd_pri_en;\n        if((retVal = rtl8367c_setAsicL2LookupTb(&l2Table)) != RT_ERR_OK)\n            return retVal;\n\n        pIpMcastAddr->address = l2Table.address;\n        return RT_ERR_OK;\n    }\n    else if (RT_ERR_L2_ENTRY_NOTFOUND == retVal)\n    {\n        memset(&l2Table, 0, sizeof(rtl8367c_luttb));\n        l2Table.sip = pIpMcastAddr->sip;\n        l2Table.dip = pIpMcastAddr->dip;\n        l2Table.mbr = pmask;\n        l2Table.nosalearn = 1;\n        l2Table.l3lookup = 1;\n        l2Table.l3vidlookup = 0;\n        l2Table.lut_pri = pIpMcastAddr->priority;\n        l2Table.fwd_en  = pIpMcastAddr->fwd_pri_en;\n        if ((retVal = rtl8367c_setAsicL2LookupTb(&l2Table)) != RT_ERR_OK)\n            return retVal;\n\n        pIpMcastAddr->address = l2Table.address;\n\n        method = LUTREADMETHOD_MAC;\n        retVal = rtl8367c_getAsicL2LookupTb(method, &l2Table);\n        if (RT_ERR_L2_ENTRY_NOTFOUND == retVal)\n            return     RT_ERR_L2_INDEXTBL_FULL;\n        else\n            return retVal;\n\n    }\n    else\n        return retVal;\n\n}\n\n/* Function Name:\n *      rtk_l2_ipMcastAddr_get\n * Description:\n *      Get LUT IP multicast entry.\n * Input:\n *      pIpMcastAddr    - IP Multicast entry\n * Output:\n *      pIpMcastAddr    - IP Multicast entry\n * Return:\n *      RT_ERR_OK                   - OK\n *      RT_ERR_FAILED               - Failed\n *      RT_ERR_SMI                  - SMI access error\n *      RT_ERR_L2_ENTRY_NOTFOUND    - No such LUT entry.\n *      RT_ERR_INPUT                - Invalid input parameters.\n * Note:\n *      The API can get Lut table of IP multicast entry.\n */\nrtk_api_ret_t rtk_l2_ipMcastAddr_get(rtk_l2_ipMcastAddr_t *pIpMcastAddr)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32 method;\n    rtl8367c_luttb l2Table;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(NULL == pIpMcastAddr)\n        return RT_ERR_NULL_POINTER;\n\n    if( (pIpMcastAddr->dip & 0xF0000000) != 0xE0000000)\n        return RT_ERR_INPUT;\n\n    memset(&l2Table, 0x00, sizeof(rtl8367c_luttb));\n    l2Table.sip = pIpMcastAddr->sip;\n    l2Table.dip = pIpMcastAddr->dip;\n    l2Table.l3lookup = 1;\n    l2Table.l3vidlookup = 0;\n    method = LUTREADMETHOD_MAC;\n    if ((retVal = rtl8367c_getAsicL2LookupTb(method, &l2Table)) != RT_ERR_OK)\n        return retVal;\n\n    /* Get Logical port mask */\n    if ((retVal = rtk_switch_portmask_P2L_get(l2Table.mbr, &pIpMcastAddr->portmask)) != RT_ERR_OK)\n        return retVal;\n\n    pIpMcastAddr->priority      = l2Table.lut_pri;\n    pIpMcastAddr->fwd_pri_en    = l2Table.fwd_en;\n    pIpMcastAddr->igmp_asic     = l2Table.igmp_asic;\n    pIpMcastAddr->igmp_index    = l2Table.igmpidx;\n    pIpMcastAddr->address       = l2Table.address;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_l2_ipMcastAddr_next_get\n * Description:\n *      Get Next IP Multicast entry.\n * Input:\n *      pAddress        - The Address ID\n * Output:\n *      pIpMcastAddr    - IP Multicast entry\n * Return:\n *      RT_ERR_OK                   - OK\n *      RT_ERR_FAILED               - Failed\n *      RT_ERR_SMI                  - SMI access error\n *      RT_ERR_L2_ENTRY_NOTFOUND    - No such LUT entry.\n *      RT_ERR_INPUT                - Invalid input parameters.\n * Note:\n *      Get the next IP multicast entry after the current entry pointed by pAddress.\n *      The address of next entry is returned by pAddress. User can use (address + 1)\n *      as pAddress to call this API again for dumping all IP multicast entries is LUT.\n */\nrtk_api_ret_t rtk_l2_ipMcastAddr_next_get(rtk_uint32 *pAddress, rtk_l2_ipMcastAddr_t *pIpMcastAddr)\n{\n    rtk_api_ret_t   retVal;\n    rtl8367c_luttb  l2Table;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Error Checking */\n    if ((pAddress == NULL) || (pIpMcastAddr == NULL) )\n        return RT_ERR_INPUT;\n\n    if(*pAddress > RTK_MAX_LUT_ADDR_ID )\n        return RT_ERR_L2_L2UNI_PARAM;\n\n    memset(&l2Table, 0, sizeof(rtl8367c_luttb));\n    l2Table.address = *pAddress;\n\n    do\n    {\n        if ((retVal = rtl8367c_getAsicL2LookupTb(LUTREADMETHOD_NEXT_L3MC, &l2Table)) != RT_ERR_OK)\n            return retVal;\n\n        if(l2Table.address < *pAddress)\n            return RT_ERR_L2_ENTRY_NOTFOUND;\n\n    }while(l2Table.l3vidlookup == 1);\n\n    pIpMcastAddr->sip = l2Table.sip;\n    pIpMcastAddr->dip = l2Table.dip;\n\n    /* Get Logical port mask */\n    if ((retVal = rtk_switch_portmask_P2L_get(l2Table.mbr, &pIpMcastAddr->portmask)) != RT_ERR_OK)\n        return retVal;\n\n    pIpMcastAddr->priority      = l2Table.lut_pri;\n    pIpMcastAddr->fwd_pri_en    = l2Table.fwd_en;\n    pIpMcastAddr->igmp_asic     = l2Table.igmp_asic;\n    pIpMcastAddr->igmp_index    = l2Table.igmpidx;\n    pIpMcastAddr->address       = l2Table.address;\n    *pAddress = l2Table.address;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_l2_ipMcastAddr_del\n * Description:\n *      Delete a ip multicast address entry from the specified device.\n * Input:\n *      pIpMcastAddr    - IP Multicast entry\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK                   - OK\n *      RT_ERR_FAILED               - Failed\n *      RT_ERR_SMI                  - SMI access error\n *      RT_ERR_L2_ENTRY_NOTFOUND    - No such LUT entry.\n *      RT_ERR_INPUT                - Invalid input parameters.\n * Note:\n *      The API can delete a IP multicast address entry from the specified device.\n */\nrtk_api_ret_t rtk_l2_ipMcastAddr_del(rtk_l2_ipMcastAddr_t *pIpMcastAddr)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32 method;\n    rtl8367c_luttb l2Table;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Error Checking */\n    if (pIpMcastAddr == NULL)\n        return RT_ERR_INPUT;\n\n    if( (pIpMcastAddr->dip & 0xF0000000) != 0xE0000000)\n        return RT_ERR_INPUT;\n\n    memset(&l2Table, 0x00, sizeof(rtl8367c_luttb));\n    l2Table.sip = pIpMcastAddr->sip;\n    l2Table.dip = pIpMcastAddr->dip;\n    l2Table.l3lookup = 1;\n    l2Table.l3vidlookup = 0;\n    method = LUTREADMETHOD_MAC;\n    retVal = rtl8367c_getAsicL2LookupTb(method, &l2Table);\n    if (RT_ERR_OK == retVal)\n    {\n        l2Table.sip = pIpMcastAddr->sip;\n        l2Table.dip = pIpMcastAddr->dip;\n        l2Table.mbr = 0;\n        l2Table.nosalearn = 0;\n        l2Table.l3lookup = 1;\n        l2Table.l3vidlookup = 0;\n        l2Table.lut_pri = 0;\n        l2Table.fwd_en  = 0;\n        if((retVal = rtl8367c_setAsicL2LookupTb(&l2Table)) != RT_ERR_OK)\n            return retVal;\n\n        pIpMcastAddr->address = l2Table.address;\n        return RT_ERR_OK;\n    }\n    else\n        return retVal;\n}\n\n/* Function Name:\n *      rtk_l2_ipVidMcastAddr_add\n * Description:\n *      Add Lut IP multicast+VID entry\n * Input:\n *      pIpVidMcastAddr - IP & VID multicast Entry\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - OK\n *      RT_ERR_FAILED           - Failed\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_PORT_ID          - Invalid port number.\n *      RT_ERR_L2_INDEXTBL_FULL - hashed index is full of entries.\n *      RT_ERR_PORT_MASK        - Invalid portmask.\n *      RT_ERR_INPUT            - Invalid input parameters.\n * Note:\n *\n */\nrtk_api_ret_t rtk_l2_ipVidMcastAddr_add(rtk_l2_ipVidMcastAddr_t *pIpVidMcastAddr)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32 method;\n    rtl8367c_luttb l2Table;\n    rtk_uint32 pmask;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(NULL == pIpVidMcastAddr)\n        return RT_ERR_NULL_POINTER;\n\n    /* check port mask */\n    RTK_CHK_PORTMASK_VALID(&pIpVidMcastAddr->portmask);\n\n    if (pIpVidMcastAddr->vid > RTL8367C_VIDMAX)\n        return RT_ERR_L2_VID;\n\n    if( (pIpVidMcastAddr->dip & 0xF0000000) != 0xE0000000)\n        return RT_ERR_INPUT;\n\n    /* Get Physical port mask */\n    if ((retVal = rtk_switch_portmask_L2P_get(&pIpVidMcastAddr->portmask, &pmask)) != RT_ERR_OK)\n        return retVal;\n\n    memset(&l2Table, 0x00, sizeof(rtl8367c_luttb));\n    l2Table.sip = pIpVidMcastAddr->sip;\n    l2Table.dip = pIpVidMcastAddr->dip;\n    l2Table.l3lookup = 1;\n    l2Table.l3vidlookup = 1;\n    l2Table.l3_vid = pIpVidMcastAddr->vid;\n    method = LUTREADMETHOD_MAC;\n    retVal = rtl8367c_getAsicL2LookupTb(method, &l2Table);\n    if (RT_ERR_OK == retVal)\n    {\n        l2Table.sip = pIpVidMcastAddr->sip;\n        l2Table.dip = pIpVidMcastAddr->dip;\n        l2Table.mbr = pmask;\n        l2Table.nosalearn = 1;\n        l2Table.l3lookup = 1;\n        l2Table.l3vidlookup = 1;\n        l2Table.l3_vid = pIpVidMcastAddr->vid;\n        if((retVal = rtl8367c_setAsicL2LookupTb(&l2Table)) != RT_ERR_OK)\n            return retVal;\n\n        pIpVidMcastAddr->address = l2Table.address;\n        return RT_ERR_OK;\n    }\n    else if (RT_ERR_L2_ENTRY_NOTFOUND == retVal)\n    {\n        memset(&l2Table, 0, sizeof(rtl8367c_luttb));\n        l2Table.sip = pIpVidMcastAddr->sip;\n        l2Table.dip = pIpVidMcastAddr->dip;\n        l2Table.mbr = pmask;\n        l2Table.nosalearn = 1;\n        l2Table.l3lookup = 1;\n        l2Table.l3vidlookup = 1;\n        l2Table.l3_vid = pIpVidMcastAddr->vid;\n        if ((retVal = rtl8367c_setAsicL2LookupTb(&l2Table)) != RT_ERR_OK)\n            return retVal;\n\n        pIpVidMcastAddr->address = l2Table.address;\n\n        method = LUTREADMETHOD_MAC;\n        retVal = rtl8367c_getAsicL2LookupTb(method, &l2Table);\n        if (RT_ERR_L2_ENTRY_NOTFOUND == retVal)\n            return     RT_ERR_L2_INDEXTBL_FULL;\n        else\n            return retVal;\n\n    }\n    else\n        return retVal;\n}\n\n/* Function Name:\n *      rtk_l2_ipVidMcastAddr_get\n * Description:\n *      Get LUT IP multicast+VID entry.\n * Input:\n *      pIpVidMcastAddr - IP & VID multicast Entry\n * Output:\n *      pIpVidMcastAddr - IP & VID multicast Entry\n * Return:\n *      RT_ERR_OK                   - OK\n *      RT_ERR_FAILED               - Failed\n *      RT_ERR_SMI                  - SMI access error\n *      RT_ERR_L2_ENTRY_NOTFOUND    - No such LUT entry.\n *      RT_ERR_INPUT                - Invalid input parameters.\n * Note:\n *\n */\nrtk_api_ret_t rtk_l2_ipVidMcastAddr_get(rtk_l2_ipVidMcastAddr_t *pIpVidMcastAddr)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32 method;\n    rtl8367c_luttb l2Table;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(NULL == pIpVidMcastAddr)\n        return RT_ERR_NULL_POINTER;\n\n    if (pIpVidMcastAddr->vid > RTL8367C_VIDMAX)\n        return RT_ERR_L2_VID;\n\n    if( (pIpVidMcastAddr->dip & 0xF0000000) != 0xE0000000)\n        return RT_ERR_INPUT;\n\n    memset(&l2Table, 0x00, sizeof(rtl8367c_luttb));\n    l2Table.sip = pIpVidMcastAddr->sip;\n    l2Table.dip = pIpVidMcastAddr->dip;\n    l2Table.l3lookup = 1;\n    l2Table.l3vidlookup = 1;\n    l2Table.l3_vid = pIpVidMcastAddr->vid;\n    method = LUTREADMETHOD_MAC;\n    if ((retVal = rtl8367c_getAsicL2LookupTb(method, &l2Table)) != RT_ERR_OK)\n        return retVal;\n\n    pIpVidMcastAddr->address = l2Table.address;\n\n     /* Get Logical port mask */\n    if ((retVal = rtk_switch_portmask_P2L_get(l2Table.mbr, &pIpVidMcastAddr->portmask)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_l2_ipVidMcastAddr_next_get\n * Description:\n *      Get Next IP Multicast+VID entry.\n * Input:\n *      pAddress        - The Address ID\n * Output:\n *      pIpVidMcastAddr - IP & VID multicast Entry\n * Return:\n *      RT_ERR_OK                   - OK\n *      RT_ERR_FAILED               - Failed\n *      RT_ERR_SMI                  - SMI access error\n *      RT_ERR_L2_ENTRY_NOTFOUND    - No such LUT entry.\n *      RT_ERR_INPUT                - Invalid input parameters.\n * Note:\n *      Get the next IP multicast entry after the current entry pointed by pAddress.\n *      The address of next entry is returned by pAddress. User can use (address + 1)\n *      as pAddress to call this API again for dumping all IP multicast entries is LUT.\n */\nrtk_api_ret_t rtk_l2_ipVidMcastAddr_next_get(rtk_uint32 *pAddress, rtk_l2_ipVidMcastAddr_t *pIpVidMcastAddr)\n{\n    rtk_api_ret_t   retVal;\n    rtl8367c_luttb  l2Table;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Error Checking */\n    if ((pAddress == NULL) || (pIpVidMcastAddr == NULL))\n        return RT_ERR_INPUT;\n\n    if(*pAddress > RTK_MAX_LUT_ADDR_ID )\n        return RT_ERR_L2_L2UNI_PARAM;\n\n    memset(&l2Table, 0, sizeof(rtl8367c_luttb));\n    l2Table.address = *pAddress;\n\n    do\n    {\n        if ((retVal = rtl8367c_getAsicL2LookupTb(LUTREADMETHOD_NEXT_L3MC, &l2Table)) != RT_ERR_OK)\n            return retVal;\n\n        if(l2Table.address < *pAddress)\n            return RT_ERR_L2_ENTRY_NOTFOUND;\n\n    }while(l2Table.l3vidlookup == 0);\n\n    pIpVidMcastAddr->sip        = l2Table.sip;\n    pIpVidMcastAddr->dip        = l2Table.dip;\n    pIpVidMcastAddr->vid        = l2Table.l3_vid;\n    pIpVidMcastAddr->address    = l2Table.address;\n\n    /* Get Logical port mask */\n    if ((retVal = rtk_switch_portmask_P2L_get(l2Table.mbr, &pIpVidMcastAddr->portmask)) != RT_ERR_OK)\n        return retVal;\n\n    *pAddress = l2Table.address;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_l2_ipVidMcastAddr_del\n * Description:\n *      Delete a ip multicast+VID address entry from the specified device.\n * Input:\n *      pIpVidMcastAddr - IP & VID multicast Entry\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK                   - OK\n *      RT_ERR_FAILED               - Failed\n *      RT_ERR_SMI                  - SMI access error\n *      RT_ERR_L2_ENTRY_NOTFOUND    - No such LUT entry.\n *      RT_ERR_INPUT                - Invalid input parameters.\n * Note:\n *\n */\nrtk_api_ret_t rtk_l2_ipVidMcastAddr_del(rtk_l2_ipVidMcastAddr_t *pIpVidMcastAddr)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32 method;\n    rtl8367c_luttb l2Table;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(NULL == pIpVidMcastAddr)\n        return RT_ERR_NULL_POINTER;\n\n    if (pIpVidMcastAddr->vid > RTL8367C_VIDMAX)\n        return RT_ERR_L2_VID;\n\n    if( (pIpVidMcastAddr->dip & 0xF0000000) != 0xE0000000)\n        return RT_ERR_INPUT;\n\n    memset(&l2Table, 0x00, sizeof(rtl8367c_luttb));\n    l2Table.sip = pIpVidMcastAddr->sip;\n    l2Table.dip = pIpVidMcastAddr->dip;\n    l2Table.l3lookup = 1;\n    l2Table.l3vidlookup = 1;\n    l2Table.l3_vid = pIpVidMcastAddr->vid;\n    method = LUTREADMETHOD_MAC;\n    retVal = rtl8367c_getAsicL2LookupTb(method, &l2Table);\n    if (RT_ERR_OK == retVal)\n    {\n        l2Table.sip = pIpVidMcastAddr->sip;\n        l2Table.dip = pIpVidMcastAddr->dip;\n        l2Table.mbr= 0;\n        l2Table.nosalearn = 0;\n        l2Table.l3lookup = 1;\n        l2Table.l3vidlookup = 1;\n        l2Table.l3_vid = pIpVidMcastAddr->vid;\n        if((retVal = rtl8367c_setAsicL2LookupTb(&l2Table)) != RT_ERR_OK)\n            return retVal;\n\n        pIpVidMcastAddr->address = l2Table.address;\n        return RT_ERR_OK;\n    }\n    else\n        return retVal;\n}\n\n/* Function Name:\n *      rtk_l2_ucastAddr_flush\n * Description:\n *      Flush L2 mac address by type in the specified device (both dynamic and static).\n * Input:\n *      pConfig - flush configuration\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number.\n *      RT_ERR_VLAN_VID     - Invalid VID parameter.\n *      RT_ERR_INPUT        - Invalid input parameters.\n * Note:\n *      flushByVid          - 1: Flush by VID, 0: Don't flush by VID\n *      vid                 - VID (0 ~ 4095)\n *      flushByFid          - 1: Flush by FID, 0: Don't flush by FID\n *      fid                 - FID (0 ~ 15)\n *      flushByPort         - 1: Flush by Port, 0: Don't flush by Port\n *      port                - Port ID\n *      flushByMac          - Not Supported\n *      ucastAddr           - Not Supported\n *      flushStaticAddr     - 1: Flush both Static and Dynamic entries, 0: Flush only Dynamic entries\n *      flushAddrOnAllPorts - 1: Flush VID-matched entries at all ports, 0: Flush VID-matched entries per port.\n */\nrtk_api_ret_t rtk_l2_ucastAddr_flush(rtk_l2_flushCfg_t *pConfig)\n{\n    rtk_api_ret_t   retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(pConfig == NULL)\n        return RT_ERR_NULL_POINTER;\n\n    if(pConfig->flushByVid >= RTK_ENABLE_END)\n        return RT_ERR_ENABLE;\n\n    if(pConfig->flushByFid >= RTK_ENABLE_END)\n        return RT_ERR_ENABLE;\n\n    if(pConfig->flushByPort >= RTK_ENABLE_END)\n        return RT_ERR_ENABLE;\n\n    if(pConfig->flushByMac >= RTK_ENABLE_END)\n        return RT_ERR_ENABLE;\n\n    if(pConfig->flushStaticAddr >= RTK_ENABLE_END)\n        return RT_ERR_ENABLE;\n\n    if(pConfig->flushAddrOnAllPorts >= RTK_ENABLE_END)\n        return RT_ERR_ENABLE;\n\n    if(pConfig->vid > RTL8367C_VIDMAX)\n        return RT_ERR_VLAN_VID;\n\n    if(pConfig->fid > RTL8367C_FIDMAX)\n        return RT_ERR_INPUT;\n\n    /* check port valid */\n    RTK_CHK_PORT_VALID(pConfig->port);\n\n    if(pConfig->flushByVid == ENABLED)\n    {\n        if ((retVal = rtl8367c_setAsicLutFlushMode(FLUSHMDOE_VID)) != RT_ERR_OK)\n            return retVal;\n\n        if ((retVal = rtl8367c_setAsicLutFlushVid(pConfig->vid)) != RT_ERR_OK)\n                return retVal;\n\n        if ((retVal = rtl8367c_setAsicLutFlushType((pConfig->flushStaticAddr == ENABLED) ? FLUSHTYPE_BOTH : FLUSHTYPE_DYNAMIC)) != RT_ERR_OK)\n            return retVal;\n\n        if(pConfig->flushAddrOnAllPorts == ENABLED)\n        {\n            if ((retVal = rtl8367c_setAsicLutForceFlush(RTL8367C_PORTMASK)) != RT_ERR_OK)\n                return retVal;\n        }\n        else if(pConfig->flushByPort == ENABLED)\n        {\n            if ((retVal = rtl8367c_setAsicLutForceFlush(1 << rtk_switch_port_L2P_get(pConfig->port))) != RT_ERR_OK)\n                return retVal;\n        }\n        else\n            return RT_ERR_INPUT;\n    }\n    else if(pConfig->flushByFid == ENABLED)\n    {\n        if ((retVal = rtl8367c_setAsicLutFlushMode(FLUSHMDOE_FID)) != RT_ERR_OK)\n            return retVal;\n\n        if ((retVal = rtl8367c_setAsicLutFlushFid(pConfig->fid)) != RT_ERR_OK)\n                return retVal;\n\n        if ((retVal = rtl8367c_setAsicLutFlushType((pConfig->flushStaticAddr == ENABLED) ? FLUSHTYPE_BOTH : FLUSHTYPE_DYNAMIC)) != RT_ERR_OK)\n            return retVal;\n\n        if(pConfig->flushAddrOnAllPorts == ENABLED)\n        {\n            if ((retVal = rtl8367c_setAsicLutForceFlush(RTL8367C_PORTMASK)) != RT_ERR_OK)\n                return retVal;\n        }\n        else if(pConfig->flushByPort == ENABLED)\n        {\n            if ((retVal = rtl8367c_setAsicLutForceFlush(1 << rtk_switch_port_L2P_get(pConfig->port))) != RT_ERR_OK)\n                return retVal;\n        }\n        else\n            return RT_ERR_INPUT;\n    }\n    else if(pConfig->flushByPort == ENABLED)\n    {\n        if ((retVal = rtl8367c_setAsicLutFlushType((pConfig->flushStaticAddr == ENABLED) ? FLUSHTYPE_BOTH : FLUSHTYPE_DYNAMIC)) != RT_ERR_OK)\n            return retVal;\n\n        if ((retVal = rtl8367c_setAsicLutFlushMode(FLUSHMDOE_PORT)) != RT_ERR_OK)\n            return retVal;\n\n        if ((retVal = rtl8367c_setAsicLutForceFlush(1 << rtk_switch_port_L2P_get(pConfig->port))) != RT_ERR_OK)\n            return retVal;\n    }\n    else if(pConfig->flushByMac == ENABLED)\n    {\n        /* Should use API \"rtk_l2_addr_del\" to remove a specified entry*/\n        return RT_ERR_CHIP_NOT_SUPPORTED;\n    }\n    else\n        return RT_ERR_INPUT;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_l2_table_clear\n * Description:\n *      Flush all static & dynamic entries in LUT.\n * Input:\n *      None\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n * Note:\n *\n */\nrtk_api_ret_t rtk_l2_table_clear(void)\n{\n    rtk_api_ret_t   retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if ((retVal = rtl8367c_setAsicLutFlushAll()) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_l2_table_clearStatus_get\n * Description:\n *      Get table clear status\n * Input:\n *      None\n * Output:\n *      pStatus - Clear status, 1:Busy, 0:finish\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n * Note:\n *\n */\nrtk_api_ret_t rtk_l2_table_clearStatus_get(rtk_l2_clearStatus_t *pStatus)\n{\n    rtk_api_ret_t   retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(NULL == pStatus)\n        return RT_ERR_NULL_POINTER;\n\n    if ((retVal = rtl8367c_getAsicLutFlushAllStatus((rtk_uint32 *)pStatus)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_l2_flushLinkDownPortAddrEnable_set\n * Description:\n *      Set HW flush linkdown port mac configuration of the specified device.\n * Input:\n *      port - Port id.\n *      enable - link down flush status\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number.\n *      RT_ERR_ENABLE       - Invalid enable input.\n * Note:\n *      The status of flush linkdown port address is as following:\n *      - DISABLED\n *      - ENABLED\n */\nrtk_api_ret_t rtk_l2_flushLinkDownPortAddrEnable_set(rtk_port_t port, rtk_enable_t enable)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if (port != RTK_WHOLE_SYSTEM)\n        return RT_ERR_PORT_ID;\n\n    if (enable >= RTK_ENABLE_END)\n        return RT_ERR_ENABLE;\n\n    if ((retVal = rtl8367c_setAsicLutLinkDownForceAging(enable)) != RT_ERR_OK)\n        return retVal;\n\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_l2_flushLinkDownPortAddrEnable_get\n * Description:\n *      Get HW flush linkdown port mac configuration of the specified device.\n * Input:\n *      port - Port id.\n * Output:\n *      pEnable - link down flush status\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number.\n * Note:\n *      The status of flush linkdown port address is as following:\n *      - DISABLED\n *      - ENABLED\n */\nrtk_api_ret_t rtk_l2_flushLinkDownPortAddrEnable_get(rtk_port_t port, rtk_enable_t *pEnable)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if (port != RTK_WHOLE_SYSTEM)\n        return RT_ERR_PORT_ID;\n\n    if(NULL == pEnable)\n        return RT_ERR_NULL_POINTER;\n\n    if ((retVal = rtl8367c_getAsicLutLinkDownForceAging(pEnable)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_l2_agingEnable_set\n * Description:\n *      Set L2 LUT aging status per port setting.\n * Input:\n *      port    - Port id.\n *      enable  - Aging status\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number.\n *      RT_ERR_ENABLE       - Invalid enable input.\n * Note:\n *      This API can be used to set L2 LUT aging status per port.\n */\nrtk_api_ret_t rtk_l2_agingEnable_set(rtk_port_t port, rtk_enable_t enable)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* check port valid */\n    RTK_CHK_PORT_VALID(port);\n\n    if (enable >= RTK_ENABLE_END)\n        return RT_ERR_ENABLE;\n\n    if(enable == 1)\n        enable = 0;\n    else\n        enable = 1;\n\n    if ((retVal = rtl8367c_setAsicLutDisableAging(rtk_switch_port_L2P_get(port), enable)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_l2_agingEnable_get\n * Description:\n *      Get L2 LUT aging status per port setting.\n * Input:\n *      port - Port id.\n * Output:\n *      pEnable - Aging status\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number.\n * Note:\n *      This API can be used to get L2 LUT aging function per port.\n */\nrtk_api_ret_t rtk_l2_agingEnable_get(rtk_port_t port, rtk_enable_t *pEnable)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* check port valid */\n    RTK_CHK_PORT_VALID(port);\n\n    if(NULL == pEnable)\n        return RT_ERR_NULL_POINTER;\n\n    if ((retVal = rtl8367c_getAsicLutDisableAging(rtk_switch_port_L2P_get(port), pEnable)) != RT_ERR_OK)\n        return retVal;\n\n    if(*pEnable == 1)\n        *pEnable = 0;\n    else\n        *pEnable = 1;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_l2_limitLearningCnt_set\n * Description:\n *      Set per-Port auto learning limit number\n * Input:\n *      port    - Port id.\n *      mac_cnt - Auto learning entries limit number\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK                   - OK\n *      RT_ERR_FAILED               - Failed\n *      RT_ERR_SMI                  - SMI access error\n *      RT_ERR_PORT_ID              - Invalid port number.\n *      RT_ERR_LIMITED_L2ENTRY_NUM  - Invalid auto learning limit number\n * Note:\n *      The API can set per-port ASIC auto learning limit number from 0(disable learning)\n *      to 2112.\n */\nrtk_api_ret_t rtk_l2_limitLearningCnt_set(rtk_port_t port, rtk_mac_cnt_t mac_cnt)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* check port valid */\n    RTK_CHK_PORT_VALID(port);\n\n    if (mac_cnt > rtk_switch_maxLutAddrNumber_get())\n        return RT_ERR_LIMITED_L2ENTRY_NUM;\n\n    if ((retVal = rtl8367c_setAsicLutLearnLimitNo(rtk_switch_port_L2P_get(port), mac_cnt)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_l2_limitLearningCnt_get\n * Description:\n *      Get per-Port auto learning limit number\n * Input:\n *      port - Port id.\n * Output:\n *      pMac_cnt - Auto learning entries limit number\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number.\n * Note:\n *      The API can get per-port ASIC auto learning limit number.\n */\nrtk_api_ret_t rtk_l2_limitLearningCnt_get(rtk_port_t port, rtk_mac_cnt_t *pMac_cnt)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* check port valid */\n    RTK_CHK_PORT_VALID(port);\n\n    if(NULL == pMac_cnt)\n        return RT_ERR_NULL_POINTER;\n\n    if ((retVal = rtl8367c_getAsicLutLearnLimitNo(rtk_switch_port_L2P_get(port), pMac_cnt)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_l2_limitSystemLearningCnt_set\n * Description:\n *      Set System auto learning limit number\n * Input:\n *      mac_cnt - Auto learning entries limit number\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK                   - OK\n *      RT_ERR_FAILED               - Failed\n *      RT_ERR_SMI                  - SMI access error\n *      RT_ERR_LIMITED_L2ENTRY_NUM  - Invalid auto learning limit number\n * Note:\n *      The API can set system ASIC auto learning limit number from 0(disable learning)\n *      to 2112.\n */\nrtk_api_ret_t rtk_l2_limitSystemLearningCnt_set(rtk_mac_cnt_t mac_cnt)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if (mac_cnt > rtk_switch_maxLutAddrNumber_get())\n        return RT_ERR_LIMITED_L2ENTRY_NUM;\n\n    if ((retVal = rtl8367c_setAsicSystemLutLearnLimitNo(mac_cnt)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_l2_limitSystemLearningCnt_get\n * Description:\n *      Get System auto learning limit number\n * Input:\n *      None\n * Output:\n *      pMac_cnt - Auto learning entries limit number\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number.\n * Note:\n *      The API can get system ASIC auto learning limit number.\n */\nrtk_api_ret_t rtk_l2_limitSystemLearningCnt_get(rtk_mac_cnt_t *pMac_cnt)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(NULL == pMac_cnt)\n        return RT_ERR_NULL_POINTER;\n\n    if ((retVal = rtl8367c_getAsicSystemLutLearnLimitNo(pMac_cnt)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_l2_limitLearningCntAction_set\n * Description:\n *      Configure auto learn over limit number action.\n * Input:\n *      port - Port id.\n *      action - Auto learning entries limit number\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number.\n *      RT_ERR_NOT_ALLOWED  - Invalid learn over action\n * Note:\n *      The API can set SA unknown packet action while auto learn limit number is over\n *      The action symbol as following:\n *      - LIMIT_LEARN_CNT_ACTION_DROP,\n *      - LIMIT_LEARN_CNT_ACTION_FORWARD,\n *      - LIMIT_LEARN_CNT_ACTION_TO_CPU,\n */\nrtk_api_ret_t rtk_l2_limitLearningCntAction_set(rtk_port_t port, rtk_l2_limitLearnCntAction_t action)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32 data;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if (port != RTK_WHOLE_SYSTEM)\n        return RT_ERR_PORT_ID;\n\n    if ( LIMIT_LEARN_CNT_ACTION_DROP == action )\n        data = 1;\n    else if ( LIMIT_LEARN_CNT_ACTION_FORWARD == action )\n        data = 0;\n    else if ( LIMIT_LEARN_CNT_ACTION_TO_CPU == action )\n        data = 2;\n    else\n        return RT_ERR_NOT_ALLOWED;\n\n    if ((retVal = rtl8367c_setAsicLutLearnOverAct(data)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_l2_limitLearningCntAction_get\n * Description:\n *      Get auto learn over limit number action.\n * Input:\n *      port - Port id.\n * Output:\n *      pAction - Learn over action\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number.\n * Note:\n *      The API can get SA unknown packet action while auto learn limit number is over\n *      The action symbol as following:\n *      - LIMIT_LEARN_CNT_ACTION_DROP,\n *      - LIMIT_LEARN_CNT_ACTION_FORWARD,\n *      - LIMIT_LEARN_CNT_ACTION_TO_CPU,\n */\nrtk_api_ret_t rtk_l2_limitLearningCntAction_get(rtk_port_t port, rtk_l2_limitLearnCntAction_t *pAction)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32 action;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if (port != RTK_WHOLE_SYSTEM)\n        return RT_ERR_PORT_ID;\n\n    if(NULL == pAction)\n        return RT_ERR_NULL_POINTER;\n\n    if ((retVal = rtl8367c_getAsicLutLearnOverAct(&action)) != RT_ERR_OK)\n        return retVal;\n\n    if ( 1 == action )\n        *pAction = LIMIT_LEARN_CNT_ACTION_DROP;\n    else if ( 0 == action )\n        *pAction = LIMIT_LEARN_CNT_ACTION_FORWARD;\n    else if ( 2 == action )\n        *pAction = LIMIT_LEARN_CNT_ACTION_TO_CPU;\n    else\n    *pAction = action;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_l2_limitSystemLearningCntAction_set\n * Description:\n *      Configure system auto learn over limit number action.\n * Input:\n *      port - Port id.\n *      action - Auto learning entries limit number\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number.\n *      RT_ERR_NOT_ALLOWED  - Invalid learn over action\n * Note:\n *      The API can set SA unknown packet action while auto learn limit number is over\n *      The action symbol as following:\n *      - LIMIT_LEARN_CNT_ACTION_DROP,\n *      - LIMIT_LEARN_CNT_ACTION_FORWARD,\n *      - LIMIT_LEARN_CNT_ACTION_TO_CPU,\n */\nrtk_api_ret_t rtk_l2_limitSystemLearningCntAction_set(rtk_l2_limitLearnCntAction_t action)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32 data;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if ( LIMIT_LEARN_CNT_ACTION_DROP == action )\n        data = 1;\n    else if ( LIMIT_LEARN_CNT_ACTION_FORWARD == action )\n        data = 0;\n    else if ( LIMIT_LEARN_CNT_ACTION_TO_CPU == action )\n        data = 2;\n    else\n        return RT_ERR_NOT_ALLOWED;\n\n    if ((retVal = rtl8367c_setAsicSystemLutLearnOverAct(data)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_l2_limitSystemLearningCntAction_get\n * Description:\n *      Get system auto learn over limit number action.\n * Input:\n *      None.\n * Output:\n *      pAction - Learn over action\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number.\n * Note:\n *      The API can get SA unknown packet action while auto learn limit number is over\n *      The action symbol as following:\n *      - LIMIT_LEARN_CNT_ACTION_DROP,\n *      - LIMIT_LEARN_CNT_ACTION_FORWARD,\n *      - LIMIT_LEARN_CNT_ACTION_TO_CPU,\n */\nrtk_api_ret_t rtk_l2_limitSystemLearningCntAction_get(rtk_l2_limitLearnCntAction_t *pAction)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32 action;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(NULL == pAction)\n        return RT_ERR_NULL_POINTER;\n\n    if ((retVal = rtl8367c_getAsicSystemLutLearnOverAct(&action)) != RT_ERR_OK)\n        return retVal;\n\n    if ( 1 == action )\n        *pAction = LIMIT_LEARN_CNT_ACTION_DROP;\n    else if ( 0 == action )\n        *pAction = LIMIT_LEARN_CNT_ACTION_FORWARD;\n    else if ( 2 == action )\n        *pAction = LIMIT_LEARN_CNT_ACTION_TO_CPU;\n    else\n    *pAction = action;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_l2_limitSystemLearningCntPortMask_set\n * Description:\n *      Configure system auto learn portmask\n * Input:\n *      pPortmask - Port Mask\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_MASK    - Invalid port mask.\n * Note:\n *\n */\nrtk_api_ret_t rtk_l2_limitSystemLearningCntPortMask_set(rtk_portmask_t *pPortmask)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32 pmask;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(NULL == pPortmask)\n        return RT_ERR_NULL_POINTER;\n\n    /* Check port mask */\n    RTK_CHK_PORTMASK_VALID(pPortmask);\n\n    if ((retVal = rtk_switch_portmask_L2P_get(pPortmask, &pmask)) != RT_ERR_OK)\n        return retVal;\n\n    if ((retVal = rtl8367c_setAsicSystemLutLearnPortMask(pmask)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_l2_limitSystemLearningCntPortMask_get\n * Description:\n *      get system auto learn portmask\n * Input:\n *      None\n * Output:\n *      pPortmask - Port Mask\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_NULL_POINTER - Null pointer.\n * Note:\n *\n */\nrtk_api_ret_t rtk_l2_limitSystemLearningCntPortMask_get(rtk_portmask_t *pPortmask)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32 pmask;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(NULL == pPortmask)\n        return RT_ERR_NULL_POINTER;\n\n    if ((retVal = rtl8367c_getAsicSystemLutLearnPortMask(&pmask)) != RT_ERR_OK)\n        return retVal;\n\n    if ((retVal = rtk_switch_portmask_P2L_get(pmask, pPortmask)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_l2_learningCnt_get\n * Description:\n *      Get per-Port current auto learning number\n * Input:\n *      port - Port id.\n * Output:\n *      pMac_cnt - ASIC auto learning entries number\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number.\n * Note:\n *      The API can get per-port ASIC auto learning number\n */\nrtk_api_ret_t rtk_l2_learningCnt_get(rtk_port_t port, rtk_mac_cnt_t *pMac_cnt)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* check port valid */\n    RTK_CHK_PORT_VALID(port);\n\n    if(NULL == pMac_cnt)\n        return RT_ERR_NULL_POINTER;\n\n    if ((retVal = rtl8367c_getAsicLutLearnNo(rtk_switch_port_L2P_get(port), pMac_cnt)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_l2_floodPortMask_set\n * Description:\n *      Set flooding portmask\n * Input:\n *      type - flooding type.\n *      pFlood_portmask - flooding porkmask\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_MASK    - Invalid portmask.\n *      RT_ERR_INPUT        - Invalid input parameters.\n * Note:\n *      This API can set the flooding mask.\n *      The flooding type is as following:\n *      - FLOOD_UNKNOWNDA\n *      - FLOOD_UNKNOWNMC\n *      - FLOOD_BC\n */\nrtk_api_ret_t rtk_l2_floodPortMask_set(rtk_l2_flood_type_t floood_type, rtk_portmask_t *pFlood_portmask)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32 pmask;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if (floood_type >= FLOOD_END)\n        return RT_ERR_INPUT;\n\n    /* check port valid */\n    RTK_CHK_PORTMASK_VALID(pFlood_portmask);\n\n    /* Get Physical port mask */\n    if ((retVal = rtk_switch_portmask_L2P_get(pFlood_portmask, &pmask))!=RT_ERR_OK)\n        return retVal;\n\n    switch (floood_type)\n    {\n        case FLOOD_UNKNOWNDA:\n            if ((retVal = rtl8367c_setAsicPortUnknownDaFloodingPortmask(pmask)) != RT_ERR_OK)\n                return retVal;\n            break;\n        case FLOOD_UNKNOWNMC:\n            if ((retVal = rtl8367c_setAsicPortUnknownMulticastFloodingPortmask(pmask)) != RT_ERR_OK)\n                return retVal;\n            break;\n        case FLOOD_BC:\n            if ((retVal = rtl8367c_setAsicPortBcastFloodingPortmask(pmask)) != RT_ERR_OK)\n                return retVal;\n            break;\n        default:\n            break;\n    }\n\n    return RT_ERR_OK;\n}\n/* Function Name:\n *      rtk_l2_floodPortMask_get\n * Description:\n *      Get flooding portmask\n * Input:\n *      type - flooding type.\n * Output:\n *      pFlood_portmask - flooding porkmask\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number.\n * Note:\n *      This API can get the flooding mask.\n *      The flooding type is as following:\n *      - FLOOD_UNKNOWNDA\n *      - FLOOD_UNKNOWNMC\n *      - FLOOD_BC\n */\nrtk_api_ret_t rtk_l2_floodPortMask_get(rtk_l2_flood_type_t floood_type, rtk_portmask_t *pFlood_portmask)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32 pmask;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if (floood_type >= FLOOD_END)\n        return RT_ERR_INPUT;\n\n    if(NULL == pFlood_portmask)\n        return RT_ERR_NULL_POINTER;\n\n    switch (floood_type)\n    {\n        case FLOOD_UNKNOWNDA:\n            if ((retVal = rtl8367c_getAsicPortUnknownDaFloodingPortmask(&pmask)) != RT_ERR_OK)\n                return retVal;\n            break;\n        case FLOOD_UNKNOWNMC:\n            if ((retVal = rtl8367c_getAsicPortUnknownMulticastFloodingPortmask(&pmask)) != RT_ERR_OK)\n                return retVal;\n            break;\n        case FLOOD_BC:\n            if ((retVal = rtl8367c_getAsicPortBcastFloodingPortmask(&pmask)) != RT_ERR_OK)\n                return retVal;\n            break;\n        default:\n            break;\n    }\n\n    /* Get Logical port mask */\n    if ((retVal = rtk_switch_portmask_P2L_get(pmask, pFlood_portmask))!=RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_l2_localPktPermit_set\n * Description:\n *      Set permittion of frames if source port and destination port are the same.\n * Input:\n *      port - Port id.\n *      permit - permittion status\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number.\n *      RT_ERR_ENABLE       - Invalid permit value.\n * Note:\n *      This API is setted to permit frame if its source port is equal to destination port.\n */\nrtk_api_ret_t rtk_l2_localPktPermit_set(rtk_port_t port, rtk_enable_t permit)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* check port valid */\n    RTK_CHK_PORT_VALID(port);\n\n    if (permit >= RTK_ENABLE_END)\n        return RT_ERR_ENABLE;\n\n    if ((retVal = rtl8367c_setAsicPortBlockSpa(rtk_switch_port_L2P_get(port), permit)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_l2_localPktPermit_get\n * Description:\n *      Get permittion of frames if source port and destination port are the same.\n * Input:\n *      port - Port id.\n * Output:\n *      pPermit - permittion status\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number.\n * Note:\n *      This API is to get permittion status for frames if its source port is equal to destination port.\n */\nrtk_api_ret_t rtk_l2_localPktPermit_get(rtk_port_t port, rtk_enable_t *pPermit)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* check port valid */\n    RTK_CHK_PORT_VALID(port);\n\n    if(NULL == pPermit)\n        return RT_ERR_NULL_POINTER;\n\n    if ((retVal = rtl8367c_getAsicPortBlockSpa(rtk_switch_port_L2P_get(port), pPermit)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_l2_aging_set\n * Description:\n *      Set LUT agging out speed\n * Input:\n *      aging_time - Agging out time.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - OK\n *      RT_ERR_FAILED           - Failed\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_OUT_OF_RANGE     - input out of range.\n * Note:\n *      The API can set LUT agging out period for each entry and the range is from 45s to 458s.\n */\nrtk_api_ret_t rtk_l2_aging_set(rtk_l2_age_time_t aging_time)\n{\n    rtk_uint32 i;\n    CONST_T rtk_uint32 agePara[10][3] = {\n        {45, 0, 1}, {88, 0, 2}, {133, 0, 3}, {177, 0, 4}, {221, 0, 5}, {266, 0, 6}, {310, 0, 7},\n        {354, 2, 6}, {413, 2, 7}, {458, 3, 7}};\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if (aging_time>agePara[9][0])\n        return RT_ERR_OUT_OF_RANGE;\n\n    for (i = 0; i<10; i++)\n    {\n        if (aging_time<=agePara[i][0])\n        {\n            return rtl8367c_setAsicLutAgeTimerSpeed(agePara[i][2], agePara[i][1]);\n        }\n    }\n\n    return RT_ERR_FAILED;\n}\n\n/* Function Name:\n *      rtk_l2_aging_get\n * Description:\n *      Get LUT agging out time\n * Input:\n *      None\n * Output:\n *      pEnable - Aging status\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number.\n * Note:\n *      The API can get LUT agging out period for each entry.\n */\nrtk_api_ret_t rtk_l2_aging_get(rtk_l2_age_time_t *pAging_time)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32 i,time, speed;\n    CONST_T rtk_uint32 agePara[10][3] = {\n        {45, 0, 1}, {88, 0, 2}, {133, 0, 3}, {177, 0, 4}, {221, 0, 5}, {266, 0, 6}, {310, 0, 7},\n        {354, 2, 6}, {413, 2, 7}, {458, 3, 7}};\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(NULL == pAging_time)\n        return RT_ERR_NULL_POINTER;\n\n    if ((retVal = rtl8367c_getAsicLutAgeTimerSpeed(&time, &speed)) != RT_ERR_OK)\n        return retVal;\n\n    for (i = 0; i<10; i++)\n    {\n        if (time==agePara[i][2]&&speed==agePara[i][1])\n        {\n            *pAging_time = agePara[i][0];\n            return RT_ERR_OK;\n        }\n    }\n\n    return RT_ERR_FAILED;\n}\n\n/* Function Name:\n *      rtk_l2_ipMcastAddrLookup_set\n * Description:\n *      Set Lut IP multicast lookup function\n * Input:\n *      type - Lookup type for IPMC packet.\n * Output:\n *      None.\n * Return:\n *      RT_ERR_OK          - OK\n *      RT_ERR_FAILED      - Failed\n *      RT_ERR_SMI         - SMI access error\n * Note:\n *      LOOKUP_MAC      - Lookup by MAC address\n *      LOOKUP_IP       - Lookup by IP address\n *      LOOKUP_IP_VID   - Lookup by IP address & VLAN ID\n */\nrtk_api_ret_t rtk_l2_ipMcastAddrLookup_set(rtk_l2_ipmc_lookup_type_t type)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(type == LOOKUP_MAC)\n    {\n        if((retVal = rtl8367c_setAsicLutIpMulticastLookup(DISABLED)) != RT_ERR_OK)\n            return retVal;\n    }\n    else if(type == LOOKUP_IP)\n    {\n        if((retVal = rtl8367c_setAsicLutIpMulticastLookup(ENABLED)) != RT_ERR_OK)\n            return retVal;\n\n        if ((retVal = rtl8367c_setAsicLutIpMulticastVidLookup(DISABLED))!=RT_ERR_OK)\n            return retVal;\n\n        if ((retVal = rtl8367c_setAsicLutIpLookupMethod(1))!=RT_ERR_OK)\n            return retVal;\n    }\n    else if(type == LOOKUP_IP_VID)\n    {\n        if((retVal = rtl8367c_setAsicLutIpMulticastLookup(ENABLED)) != RT_ERR_OK)\n            return retVal;\n\n        if ((retVal = rtl8367c_setAsicLutIpMulticastVidLookup(ENABLED))!=RT_ERR_OK)\n            return retVal;\n\n        if ((retVal = rtl8367c_setAsicLutIpLookupMethod(1))!=RT_ERR_OK)\n            return retVal;\n    }\n    else\n        return RT_ERR_INPUT;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_l2_ipMcastAddrLookup_get\n * Description:\n *      Get Lut IP multicast lookup function\n * Input:\n *      None.\n * Output:\n *      pType - Lookup type for IPMC packet.\n * Return:\n *      RT_ERR_OK          - OK\n *      RT_ERR_FAILED      - Failed\n *      RT_ERR_SMI         - SMI access error\n * Note:\n *      None.\n */\nrtk_api_ret_t rtk_l2_ipMcastAddrLookup_get(rtk_l2_ipmc_lookup_type_t *pType)\n{\n    rtk_api_ret_t       retVal;\n    rtk_uint32          enabled, vid_lookup;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(NULL == pType)\n        return RT_ERR_NULL_POINTER;\n\n    if((retVal = rtl8367c_getAsicLutIpMulticastLookup(&enabled)) != RT_ERR_OK)\n        return retVal;\n\n    if ((retVal = rtl8367c_getAsicLutIpMulticastVidLookup(&vid_lookup))!=RT_ERR_OK)\n        return retVal;\n\n    if(enabled == ENABLED)\n    {\n        if(vid_lookup == ENABLED)\n            *pType = LOOKUP_IP_VID;\n        else\n            *pType = LOOKUP_IP;\n    }\n    else\n        *pType = LOOKUP_MAC;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_l2_ipMcastForwardRouterPort_set\n * Description:\n *      Set IPMC packet forward to rounter port also or not\n * Input:\n *      enabled - 1: Inlcude router port, 0, exclude router port\n * Output:\n *      None.\n * Return:\n *      RT_ERR_OK          - OK\n *      RT_ERR_FAILED      - Failed\n *      RT_ERR_SMI         - SMI access error\n * Note:\n *\n */\nrtk_api_ret_t rtk_l2_ipMcastForwardRouterPort_set(rtk_enable_t enabled)\n{\n    rtk_api_ret_t       retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if (enabled >= RTK_ENABLE_END)\n        return RT_ERR_ENABLE;\n\n    if((retVal = rtl8367c_setAsicLutIpmcFwdRouterPort(enabled)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_l2_ipMcastForwardRouterPort_get\n * Description:\n *      Get IPMC packet forward to rounter port also or not\n * Input:\n *      None.\n * Output:\n *      pEnabled    - 1: Inlcude router port, 0, exclude router port\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_NULL_POINTER - Null pointer\n * Note:\n *\n */\nrtk_api_ret_t rtk_l2_ipMcastForwardRouterPort_get(rtk_enable_t *pEnabled)\n{\n    rtk_api_ret_t       retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if (NULL == pEnabled)\n        return RT_ERR_NULL_POINTER;\n\n    if((retVal = rtl8367c_getAsicLutIpmcFwdRouterPort(pEnabled)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_l2_ipMcastGroupEntry_add\n * Description:\n *      Add an IP Multicast entry to group table\n * Input:\n *      ip_addr     - IP address\n *      vid         - VLAN ID\n *      pPortmask   - portmask\n * Output:\n *      None.\n * Return:\n *      RT_ERR_OK          - OK\n *      RT_ERR_FAILED      - Failed\n *      RT_ERR_SMI         - SMI access error\n *      RT_ERR_TBL_FULL    - Table Full\n * Note:\n *      Add an entry to IP Multicast Group table.\n */\nrtk_api_ret_t rtk_l2_ipMcastGroupEntry_add(ipaddr_t ip_addr, rtk_uint32 vid, rtk_portmask_t *pPortmask)\n{\n    rtk_uint32      empty_idx = 0xFFFF;\n    rtk_int32       index;\n    ipaddr_t        group_addr;\n    rtk_uint32      group_vid;\n    rtk_uint32      pmask;\n    rtk_uint32      valid;\n    rtk_uint32      physicalPortmask;\n    rtk_api_ret_t   retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if (vid > RTL8367C_VIDMAX)\n        return RT_ERR_L2_VID;\n\n    if(NULL == pPortmask)\n        return RT_ERR_NULL_POINTER;\n\n    if((ip_addr & 0xF0000000) != 0xE0000000)\n        return RT_ERR_INPUT;\n\n    /* Get Physical port mask */\n    if ((retVal = rtk_switch_portmask_L2P_get(pPortmask, &physicalPortmask))!=RT_ERR_OK)\n        return retVal;\n\n    for(index = 0; index <= RTL8367C_LUT_IPMCGRP_TABLE_MAX; index++)\n    {\n        if ((retVal = rtl8367c_getAsicLutIPMCGroup((rtk_uint32)index, &group_addr, &group_vid, &pmask, &valid))!=RT_ERR_OK)\n            return retVal;\n\n        if( (valid == ENABLED) && (group_addr == ip_addr) && (group_vid == vid) )\n        {\n            if(pmask != physicalPortmask)\n            {\n                pmask = physicalPortmask;\n                if ((retVal = rtl8367c_setAsicLutIPMCGroup(index, ip_addr, vid, pmask, valid))!=RT_ERR_OK)\n                    return retVal;\n            }\n\n            return RT_ERR_OK;\n        }\n\n        if( (valid == DISABLED) && (empty_idx == 0xFFFF) ) /* Unused */\n            empty_idx = (rtk_uint32)index;\n    }\n\n    if(empty_idx == 0xFFFF)\n        return RT_ERR_TBL_FULL;\n\n    pmask = physicalPortmask;\n    if ((retVal = rtl8367c_setAsicLutIPMCGroup(empty_idx, ip_addr, vid, pmask, ENABLED))!=RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_l2_ipMcastGroupEntry_del\n * Description:\n *      Delete an entry from IP Multicast group table\n * Input:\n *      ip_addr     - IP address\n *      vid         - VLAN ID\n * Output:\n *      None.\n * Return:\n *      RT_ERR_OK          - OK\n *      RT_ERR_FAILED      - Failed\n *      RT_ERR_SMI         - SMI access error\n *      RT_ERR_TBL_FULL    - Table Full\n * Note:\n *      Delete an entry from IP Multicast group table.\n */\nrtk_api_ret_t rtk_l2_ipMcastGroupEntry_del(ipaddr_t ip_addr, rtk_uint32 vid)\n{\n    rtk_int32       index;\n    ipaddr_t        group_addr;\n    rtk_uint32      group_vid;\n    rtk_uint32      pmask;\n    rtk_uint32      valid;\n    rtk_api_ret_t   retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if (vid > RTL8367C_VIDMAX)\n        return RT_ERR_L2_VID;\n\n    if((ip_addr & 0xF0000000) != 0xE0000000)\n        return RT_ERR_INPUT;\n\n    for(index = 0; index <= RTL8367C_LUT_IPMCGRP_TABLE_MAX; index++)\n    {\n        if ((retVal = rtl8367c_getAsicLutIPMCGroup((rtk_uint32)index, &group_addr, &group_vid, &pmask, &valid))!=RT_ERR_OK)\n            return retVal;\n\n        if( (valid == ENABLED) && (group_addr == ip_addr) && (group_vid == vid) )\n        {\n            group_addr = 0xE0000000;\n            group_vid = 0;\n            pmask = 0;\n            if ((retVal = rtl8367c_setAsicLutIPMCGroup(index, group_addr, group_vid, pmask, DISABLED))!=RT_ERR_OK)\n                return retVal;\n\n            return RT_ERR_OK;\n        }\n    }\n\n    return RT_ERR_FAILED;\n}\n\n/* Function Name:\n *      rtk_l2_ipMcastGroupEntry_get\n * Description:\n *      get an entry from IP Multicast group table\n * Input:\n *      ip_addr     - IP address\n *      vid         - VLAN ID\n * Output:\n *      pPortmask   - member port mask\n * Return:\n *      RT_ERR_OK          - OK\n *      RT_ERR_FAILED      - Failed\n *      RT_ERR_SMI         - SMI access error\n *      RT_ERR_TBL_FULL    - Table Full\n * Note:\n *      Delete an entry from IP Multicast group table.\n */\nrtk_api_ret_t rtk_l2_ipMcastGroupEntry_get(ipaddr_t ip_addr, rtk_uint32 vid, rtk_portmask_t *pPortmask)\n{\n    rtk_int32       index;\n    ipaddr_t        group_addr;\n    rtk_uint32      group_vid;\n    rtk_uint32      valid;\n    rtk_uint32      pmask;\n    rtk_api_ret_t   retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if((ip_addr & 0xF0000000) != 0xE0000000)\n        return RT_ERR_INPUT;\n\n    if (vid > RTL8367C_VIDMAX)\n        return RT_ERR_L2_VID;\n\n    if(NULL == pPortmask)\n        return RT_ERR_NULL_POINTER;\n\n    for(index = 0; index <= RTL8367C_LUT_IPMCGRP_TABLE_MAX; index++)\n    {\n        if ((retVal = rtl8367c_getAsicLutIPMCGroup((rtk_uint32)index, &group_addr, &group_vid, &pmask, &valid))!=RT_ERR_OK)\n            return retVal;\n\n        if( (valid == ENABLED) && (group_addr == ip_addr) && (group_vid == vid) )\n        {\n            if ((retVal = rtk_switch_portmask_P2L_get(pmask, pPortmask))!=RT_ERR_OK)\n                return retVal;\n\n            return RT_ERR_OK;\n        }\n    }\n\n    return RT_ERR_FAILED;\n}\n\n/* Function Name:\n *      rtk_l2_entry_get\n * Description:\n *      Get LUT unicast entry.\n * Input:\n *      pL2_entry - Index field in the structure.\n * Output:\n *      pL2_entry - other fields such as MAC, port, age...\n * Return:\n *      RT_ERR_OK               - OK\n *      RT_ERR_FAILED           - Failed\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_L2_EMPTY_ENTRY   - Empty LUT entry.\n *      RT_ERR_INPUT            - Invalid input parameters.\n * Note:\n *      This API is used to get address by index from 0~2111.\n */\nrtk_api_ret_t rtk_l2_entry_get(rtk_l2_addr_table_t *pL2_entry)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32 method;\n    rtl8367c_luttb l2Table;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if (pL2_entry->index >= rtk_switch_maxLutAddrNumber_get())\n        return RT_ERR_INPUT;\n\n    memset(&l2Table, 0x00, sizeof(rtl8367c_luttb));\n    l2Table.address= pL2_entry->index;\n    method = LUTREADMETHOD_ADDRESS;\n    if ((retVal = rtl8367c_getAsicL2LookupTb(method, &l2Table)) != RT_ERR_OK)\n        return retVal;\n\n    if ((pL2_entry->index>0x800)&&(l2Table.lookup_hit==0))\n         return RT_ERR_L2_EMPTY_ENTRY;\n\n    if(l2Table.l3lookup)\n    {\n        if(l2Table.l3vidlookup)\n        {\n            memset(&pL2_entry->mac, 0, sizeof(rtk_mac_t));\n            pL2_entry->is_ipmul  = l2Table.l3lookup;\n            pL2_entry->sip       = l2Table.sip;\n            pL2_entry->dip       = l2Table.dip;\n            pL2_entry->is_static = l2Table.nosalearn;\n\n            /* Get Logical port mask */\n            if ((retVal = rtk_switch_portmask_P2L_get(l2Table.mbr, &(pL2_entry->portmask)))!=RT_ERR_OK)\n                return retVal;\n\n            pL2_entry->fid       = 0;\n            pL2_entry->age       = 0;\n            pL2_entry->auth      = 0;\n            pL2_entry->sa_block  = 0;\n            pL2_entry->is_ipvidmul = 1;\n            pL2_entry->l3_vid      = l2Table.l3_vid;\n        }\n        else\n        {\n            memset(&pL2_entry->mac, 0, sizeof(rtk_mac_t));\n            pL2_entry->is_ipmul  = l2Table.l3lookup;\n            pL2_entry->sip       = l2Table.sip;\n            pL2_entry->dip       = l2Table.dip;\n            pL2_entry->is_static = l2Table.nosalearn;\n\n            /* Get Logical port mask */\n            if ((retVal = rtk_switch_portmask_P2L_get(l2Table.mbr, &(pL2_entry->portmask)))!=RT_ERR_OK)\n                return retVal;\n\n            pL2_entry->fid       = 0;\n            pL2_entry->age       = 0;\n            pL2_entry->auth      = 0;\n            pL2_entry->sa_block  = 0;\n            pL2_entry->is_ipvidmul = 0;\n            pL2_entry->l3_vid      = 0;\n        }\n    }\n    else if(l2Table.mac.octet[0]&0x01)\n    {\n        memset(&pL2_entry->sip, 0, sizeof(ipaddr_t));\n        memset(&pL2_entry->dip, 0, sizeof(ipaddr_t));\n        pL2_entry->mac.octet[0] = l2Table.mac.octet[0];\n        pL2_entry->mac.octet[1] = l2Table.mac.octet[1];\n        pL2_entry->mac.octet[2] = l2Table.mac.octet[2];\n        pL2_entry->mac.octet[3] = l2Table.mac.octet[3];\n        pL2_entry->mac.octet[4] = l2Table.mac.octet[4];\n        pL2_entry->mac.octet[5] = l2Table.mac.octet[5];\n        pL2_entry->is_ipmul  = l2Table.l3lookup;\n        pL2_entry->is_static = l2Table.nosalearn;\n\n        /* Get Logical port mask */\n        if ((retVal = rtk_switch_portmask_P2L_get(l2Table.mbr, &(pL2_entry->portmask)))!=RT_ERR_OK)\n            return retVal;\n\n        pL2_entry->ivl       = l2Table.ivl_svl;\n        if(l2Table.ivl_svl == 1) /* IVL */\n        {\n            pL2_entry->cvid      = l2Table.cvid_fid;\n            pL2_entry->fid       = 0;\n        }\n        else /* SVL*/\n        {\n            pL2_entry->cvid      = 0;\n            pL2_entry->fid       = l2Table.cvid_fid;\n        }\n        pL2_entry->auth      = l2Table.auth;\n        pL2_entry->sa_block  = l2Table.sa_block;\n        pL2_entry->age       = 0;\n        pL2_entry->is_ipvidmul = 0;\n        pL2_entry->l3_vid      = 0;\n    }\n    else if((l2Table.age != 0)||(l2Table.nosalearn == 1))\n    {\n        memset(&pL2_entry->sip, 0, sizeof(ipaddr_t));\n        memset(&pL2_entry->dip, 0, sizeof(ipaddr_t));\n        pL2_entry->mac.octet[0] = l2Table.mac.octet[0];\n        pL2_entry->mac.octet[1] = l2Table.mac.octet[1];\n        pL2_entry->mac.octet[2] = l2Table.mac.octet[2];\n        pL2_entry->mac.octet[3] = l2Table.mac.octet[3];\n        pL2_entry->mac.octet[4] = l2Table.mac.octet[4];\n        pL2_entry->mac.octet[5] = l2Table.mac.octet[5];\n        pL2_entry->is_ipmul  = l2Table.l3lookup;\n        pL2_entry->is_static = l2Table.nosalearn;\n\n        /* Get Logical port mask */\n        if ((retVal = rtk_switch_portmask_P2L_get(1<<(l2Table.spa), &(pL2_entry->portmask)))!=RT_ERR_OK)\n            return retVal;\n\n        pL2_entry->ivl       = l2Table.ivl_svl;\n        pL2_entry->cvid      = l2Table.cvid_fid;\n        pL2_entry->fid       = l2Table.fid;\n        pL2_entry->auth      = l2Table.auth;\n        pL2_entry->sa_block  = l2Table.sa_block;\n        pL2_entry->age       = l2Table.age;\n        pL2_entry->is_ipvidmul = 0;\n        pL2_entry->l3_vid      = 0;\n    }\n    else\n       return RT_ERR_L2_EMPTY_ENTRY;\n\n    return RT_ERR_OK;\n}\n\n\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/leaky.c",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * $Revision: 76306 $\n * $Date: 2017-03-08 15:13:58 +0800 (週三, 08 三月 2017) $\n *\n * Purpose : RTK switch high-level API for RTL8367/RTL8367C\n * Feature : Here is a list of all functions and variables in Leaky module.\n *\n */\n\n#include <rtk_switch.h>\n#include <rtk_error.h>\n#include <leaky.h>\n#include <string.h>\n\n#include <rtl8367c_asicdrv.h>\n#include <rtl8367c_asicdrv_portIsolation.h>\n#include <rtl8367c_asicdrv_rma.h>\n#include <rtl8367c_asicdrv_igmp.h>\n\n\n/* Function Name:\n *      rtk_leaky_vlan_set\n * Description:\n *      Set VLAN leaky.\n * Input:\n *      type - Packet type for VLAN leaky.\n *      enable - Leaky status.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n *      RT_ERR_ENABLE       - Invalid enable input\n * Note:\n *      This API can set VLAN leaky for RMA ,IGMP/MLD, CDP, CSSTP, and LLDP packets.\n *      The leaky frame types are as following:\n *      - LEAKY_BRG_GROUP,\n *      - LEAKY_FD_PAUSE,\n *      - LEAKY_SP_MCAST,\n *      - LEAKY_1X_PAE,\n *      - LEAKY_UNDEF_BRG_04,\n *      - LEAKY_UNDEF_BRG_05,\n *      - LEAKY_UNDEF_BRG_06,\n *      - LEAKY_UNDEF_BRG_07,\n *      - LEAKY_PROVIDER_BRIDGE_GROUP_ADDRESS,\n *      - LEAKY_UNDEF_BRG_09,\n *      - LEAKY_UNDEF_BRG_0A,\n *      - LEAKY_UNDEF_BRG_0B,\n *      - LEAKY_UNDEF_BRG_0C,\n *      - LEAKY_PROVIDER_BRIDGE_GVRP_ADDRESS,\n *      - LEAKY_8021AB,\n *      - LEAKY_UNDEF_BRG_0F,\n *      - LEAKY_BRG_MNGEMENT,\n *      - LEAKY_UNDEFINED_11,\n *      - LEAKY_UNDEFINED_12,\n *      - LEAKY_UNDEFINED_13,\n *      - LEAKY_UNDEFINED_14,\n *      - LEAKY_UNDEFINED_15,\n *      - LEAKY_UNDEFINED_16,\n *      - LEAKY_UNDEFINED_17,\n *      - LEAKY_UNDEFINED_18,\n *      - LEAKY_UNDEFINED_19,\n *      - LEAKY_UNDEFINED_1A,\n *      - LEAKY_UNDEFINED_1B,\n *      - LEAKY_UNDEFINED_1C,\n *      - LEAKY_UNDEFINED_1D,\n *      - LEAKY_UNDEFINED_1E,\n *      - LEAKY_UNDEFINED_1F,\n *      - LEAKY_GMRP,\n *      - LEAKY_GVRP,\n *      - LEAKY_UNDEF_GARP_22,\n *      - LEAKY_UNDEF_GARP_23,\n *      - LEAKY_UNDEF_GARP_24,\n *      - LEAKY_UNDEF_GARP_25,\n *      - LEAKY_UNDEF_GARP_26,\n *      - LEAKY_UNDEF_GARP_27,\n *      - LEAKY_UNDEF_GARP_28,\n *      - LEAKY_UNDEF_GARP_29,\n *      - LEAKY_UNDEF_GARP_2A,\n *      - LEAKY_UNDEF_GARP_2B,\n *      - LEAKY_UNDEF_GARP_2C,\n *      - LEAKY_UNDEF_GARP_2D,\n *      - LEAKY_UNDEF_GARP_2E,\n *      - LEAKY_UNDEF_GARP_2F,\n *      - LEAKY_IGMP,\n *      - LEAKY_IPMULTICAST.\n *      - LEAKY_CDP,\n *      - LEAKY_CSSTP,\n *      - LEAKY_LLDP.\n */\nrtk_api_ret_t rtk_leaky_vlan_set(rtk_leaky_type_t type, rtk_enable_t enable)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32 port;\n    rtl8367c_rma_t rmacfg;\n    rtk_uint32 tmp;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if (type >= LEAKY_END)\n        return RT_ERR_INPUT;\n\n    if (enable >= RTK_ENABLE_END)\n        return RT_ERR_INPUT;\n\n    if (type >= 0 && type <= LEAKY_UNDEF_GARP_2F)\n    {\n        if ((retVal = rtl8367c_getAsicRma(type, &rmacfg)) != RT_ERR_OK)\n            return retVal;\n\n        rmacfg.vlan_leaky = enable;\n\n        if ((retVal = rtl8367c_setAsicRma(type, &rmacfg)) != RT_ERR_OK)\n            return retVal;\n    }\n    else if (LEAKY_IPMULTICAST == type)\n    {\n        for (port = 0; port <= RTK_PORT_ID_MAX; port++)\n        {\n            if ((retVal = rtl8367c_setAsicIpMulticastVlanLeaky(port,enable)) != RT_ERR_OK)\n                return retVal;\n        }\n    }\n    else if (LEAKY_IGMP == type)\n    {\n        if ((retVal = rtl8367c_setAsicIGMPVLANLeaky(enable)) != RT_ERR_OK)\n            return retVal;\n    }\n    else if (LEAKY_CDP == type)\n    {\n        if ((retVal = rtl8367c_getAsicRmaCdp(&rmacfg)) != RT_ERR_OK)\n            return retVal;\n\n        rmacfg.vlan_leaky = enable;\n\n        if ((retVal = rtl8367c_setAsicRmaCdp(&rmacfg)) != RT_ERR_OK)\n            return retVal;\n    }\n    else if (LEAKY_CSSTP == type)\n    {\n        if ((retVal = rtl8367c_getAsicRmaCsstp(&rmacfg)) != RT_ERR_OK)\n            return retVal;\n\n        rmacfg.vlan_leaky = enable;\n\n        if ((retVal = rtl8367c_setAsicRmaCsstp(&rmacfg)) != RT_ERR_OK)\n            return retVal;\n    }\n    else if (LEAKY_LLDP == type)\n    {\n        if ((retVal = rtl8367c_getAsicRmaLldp(&tmp,&rmacfg)) != RT_ERR_OK)\n            return retVal;\n\n        rmacfg.vlan_leaky = enable;\n\n        if ((retVal = rtl8367c_setAsicRmaLldp(tmp, &rmacfg)) != RT_ERR_OK)\n            return retVal;\n    }\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_leaky_vlan_get\n * Description:\n *      Get VLAN leaky.\n * Input:\n *      type - Packet type for VLAN leaky.\n * Output:\n *      pEnable - Leaky status.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n * Note:\n *      This API can get VLAN leaky status for RMA ,IGMP/MLD, CDP, CSSTP, and LLDP  packets.\n *      The leaky frame types are as following:\n *      - LEAKY_BRG_GROUP,\n *      - LEAKY_FD_PAUSE,\n *      - LEAKY_SP_MCAST,\n *      - LEAKY_1X_PAE,\n *      - LEAKY_UNDEF_BRG_04,\n *      - LEAKY_UNDEF_BRG_05,\n *      - LEAKY_UNDEF_BRG_06,\n *      - LEAKY_UNDEF_BRG_07,\n *      - LEAKY_PROVIDER_BRIDGE_GROUP_ADDRESS,\n *      - LEAKY_UNDEF_BRG_09,\n *      - LEAKY_UNDEF_BRG_0A,\n *      - LEAKY_UNDEF_BRG_0B,\n *      - LEAKY_UNDEF_BRG_0C,\n *      - LEAKY_PROVIDER_BRIDGE_GVRP_ADDRESS,\n *      - LEAKY_8021AB,\n *      - LEAKY_UNDEF_BRG_0F,\n *      - LEAKY_BRG_MNGEMENT,\n *      - LEAKY_UNDEFINED_11,\n *      - LEAKY_UNDEFINED_12,\n *      - LEAKY_UNDEFINED_13,\n *      - LEAKY_UNDEFINED_14,\n *      - LEAKY_UNDEFINED_15,\n *      - LEAKY_UNDEFINED_16,\n *      - LEAKY_UNDEFINED_17,\n *      - LEAKY_UNDEFINED_18,\n *      - LEAKY_UNDEFINED_19,\n *      - LEAKY_UNDEFINED_1A,\n *      - LEAKY_UNDEFINED_1B,\n *      - LEAKY_UNDEFINED_1C,\n *      - LEAKY_UNDEFINED_1D,\n *      - LEAKY_UNDEFINED_1E,\n *      - LEAKY_UNDEFINED_1F,\n *      - LEAKY_GMRP,\n *      - LEAKY_GVRP,\n *      - LEAKY_UNDEF_GARP_22,\n *      - LEAKY_UNDEF_GARP_23,\n *      - LEAKY_UNDEF_GARP_24,\n *      - LEAKY_UNDEF_GARP_25,\n *      - LEAKY_UNDEF_GARP_26,\n *      - LEAKY_UNDEF_GARP_27,\n *      - LEAKY_UNDEF_GARP_28,\n *      - LEAKY_UNDEF_GARP_29,\n *      - LEAKY_UNDEF_GARP_2A,\n *      - LEAKY_UNDEF_GARP_2B,\n *      - LEAKY_UNDEF_GARP_2C,\n *      - LEAKY_UNDEF_GARP_2D,\n *      - LEAKY_UNDEF_GARP_2E,\n *      - LEAKY_UNDEF_GARP_2F,\n *      - LEAKY_IGMP,\n *      - LEAKY_IPMULTICAST.\n *      - LEAKY_CDP,\n *      - LEAKY_CSSTP,\n *      - LEAKY_LLDP.\n */\nrtk_api_ret_t rtk_leaky_vlan_get(rtk_leaky_type_t type, rtk_enable_t *pEnable)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32 port,tmp;\n    rtl8367c_rma_t rmacfg;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if (type >= LEAKY_END)\n        return RT_ERR_INPUT;\n\n    if(NULL == pEnable)\n        return RT_ERR_NULL_POINTER;\n\n    if (type >= 0 && type <= LEAKY_UNDEF_GARP_2F)\n    {\n        if ((retVal = rtl8367c_getAsicRma(type, &rmacfg)) != RT_ERR_OK)\n            return retVal;\n\n        *pEnable = rmacfg.vlan_leaky;\n\n    }\n    else if (LEAKY_IPMULTICAST == type)\n    {\n        for (port = 0; port <= RTK_PORT_ID_MAX; port++)\n        {\n            if ((retVal = rtl8367c_getAsicIpMulticastVlanLeaky(port, &tmp)) != RT_ERR_OK)\n                return retVal;\n            if (port>0&&(tmp!=*pEnable))\n                return RT_ERR_FAILED;\n            *pEnable = tmp;\n        }\n    }\n    else if (LEAKY_IGMP == type)\n    {\n        if ((retVal = rtl8367c_getAsicIGMPVLANLeaky(&tmp)) != RT_ERR_OK)\n            return retVal;\n\n        *pEnable = tmp;\n    }\n    else if (LEAKY_CDP == type)\n    {\n        if ((retVal = rtl8367c_getAsicRmaCdp(&rmacfg)) != RT_ERR_OK)\n            return retVal;\n\n        *pEnable = rmacfg.vlan_leaky;\n    }\n    else if (LEAKY_CSSTP == type)\n    {\n        if ((retVal = rtl8367c_getAsicRmaCsstp(&rmacfg)) != RT_ERR_OK)\n            return retVal;\n\n        *pEnable = rmacfg.vlan_leaky;\n    }\n    else if (LEAKY_LLDP == type)\n    {\n        if ((retVal = rtl8367c_getAsicRmaLldp(&tmp, &rmacfg)) != RT_ERR_OK)\n            return retVal;\n\n        *pEnable = rmacfg.vlan_leaky;\n    }\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_leaky_portIsolation_set\n * Description:\n *      Set port isolation leaky.\n * Input:\n *      type - Packet type for port isolation leaky.\n *      enable - Leaky status.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n *      RT_ERR_ENABLE       - Invalid enable input\n * Note:\n *      This API can set port isolation leaky for RMA ,IGMP/MLD, CDP, CSSTP, and LLDP  packets.\n *      The leaky frame types are as following:\n *      - LEAKY_BRG_GROUP,\n *      - LEAKY_FD_PAUSE,\n *      - LEAKY_SP_MCAST,\n *      - LEAKY_1X_PAE,\n *      - LEAKY_UNDEF_BRG_04,\n *      - LEAKY_UNDEF_BRG_05,\n *      - LEAKY_UNDEF_BRG_06,\n *      - LEAKY_UNDEF_BRG_07,\n *      - LEAKY_PROVIDER_BRIDGE_GROUP_ADDRESS,\n *      - LEAKY_UNDEF_BRG_09,\n *      - LEAKY_UNDEF_BRG_0A,\n *      - LEAKY_UNDEF_BRG_0B,\n *      - LEAKY_UNDEF_BRG_0C,\n *      - LEAKY_PROVIDER_BRIDGE_GVRP_ADDRESS,\n *      - LEAKY_8021AB,\n *      - LEAKY_UNDEF_BRG_0F,\n *      - LEAKY_BRG_MNGEMENT,\n *      - LEAKY_UNDEFINED_11,\n *      - LEAKY_UNDEFINED_12,\n *      - LEAKY_UNDEFINED_13,\n *      - LEAKY_UNDEFINED_14,\n *      - LEAKY_UNDEFINED_15,\n *      - LEAKY_UNDEFINED_16,\n *      - LEAKY_UNDEFINED_17,\n *      - LEAKY_UNDEFINED_18,\n *      - LEAKY_UNDEFINED_19,\n *      - LEAKY_UNDEFINED_1A,\n *      - LEAKY_UNDEFINED_1B,\n *      - LEAKY_UNDEFINED_1C,\n *      - LEAKY_UNDEFINED_1D,\n *      - LEAKY_UNDEFINED_1E,\n *      - LEAKY_UNDEFINED_1F,\n *      - LEAKY_GMRP,\n *      - LEAKY_GVRP,\n *      - LEAKY_UNDEF_GARP_22,\n *      - LEAKY_UNDEF_GARP_23,\n *      - LEAKY_UNDEF_GARP_24,\n *      - LEAKY_UNDEF_GARP_25,\n *      - LEAKY_UNDEF_GARP_26,\n *      - LEAKY_UNDEF_GARP_27,\n *      - LEAKY_UNDEF_GARP_28,\n *      - LEAKY_UNDEF_GARP_29,\n *      - LEAKY_UNDEF_GARP_2A,\n *      - LEAKY_UNDEF_GARP_2B,\n *      - LEAKY_UNDEF_GARP_2C,\n *      - LEAKY_UNDEF_GARP_2D,\n *      - LEAKY_UNDEF_GARP_2E,\n *      - LEAKY_UNDEF_GARP_2F,\n *      - LEAKY_IGMP,\n *      - LEAKY_IPMULTICAST.\n *      - LEAKY_CDP,\n *      - LEAKY_CSSTP,\n *      - LEAKY_LLDP.\n */\nrtk_api_ret_t rtk_leaky_portIsolation_set(rtk_leaky_type_t type, rtk_enable_t enable)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32 port;\n    rtl8367c_rma_t rmacfg;\n    rtk_uint32 tmp;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if (type >= LEAKY_END)\n        return RT_ERR_INPUT;\n\n    if (enable >= RTK_ENABLE_END)\n        return RT_ERR_INPUT;\n\n    if (type >= 0 && type <= LEAKY_UNDEF_GARP_2F)\n    {\n        if ((retVal = rtl8367c_getAsicRma(type, &rmacfg)) != RT_ERR_OK)\n            return retVal;\n\n        rmacfg.portiso_leaky = enable;\n\n        if ((retVal = rtl8367c_setAsicRma(type, &rmacfg)) != RT_ERR_OK)\n            return retVal;\n    }\n    else if (LEAKY_IPMULTICAST == type)\n    {\n        for (port = 0; port < RTK_MAX_NUM_OF_PORT; port++)\n        {\n            if ((retVal = rtl8367c_setAsicIpMulticastPortIsoLeaky(port,enable)) != RT_ERR_OK)\n                return retVal;\n        }\n    }\n    else if (LEAKY_IGMP == type)\n    {\n        if ((retVal = rtl8367c_setAsicIGMPIsoLeaky(enable)) != RT_ERR_OK)\n            return retVal;\n    }\n    else if (LEAKY_CDP == type)\n    {\n        if ((retVal = rtl8367c_getAsicRmaCdp(&rmacfg)) != RT_ERR_OK)\n            return retVal;\n\n        rmacfg.portiso_leaky = enable;\n\n        if ((retVal = rtl8367c_setAsicRmaCdp(&rmacfg)) != RT_ERR_OK)\n            return retVal;\n    }\n    else if (LEAKY_CSSTP == type)\n    {\n        if ((retVal = rtl8367c_getAsicRmaCsstp(&rmacfg)) != RT_ERR_OK)\n            return retVal;\n\n        rmacfg.portiso_leaky = enable;\n\n        if ((retVal = rtl8367c_setAsicRmaCsstp(&rmacfg)) != RT_ERR_OK)\n            return retVal;\n    }\n    else if (LEAKY_LLDP == type)\n    {\n        if ((retVal = rtl8367c_getAsicRmaLldp(&tmp, &rmacfg)) != RT_ERR_OK)\n            return retVal;\n\n        rmacfg.portiso_leaky = enable;\n\n        if ((retVal = rtl8367c_setAsicRmaLldp(tmp, &rmacfg)) != RT_ERR_OK)\n            return retVal;\n    }\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_leaky_portIsolation_get\n * Description:\n *      Get port isolation leaky.\n * Input:\n *      type - Packet type for port isolation leaky.\n * Output:\n *      pEnable - Leaky status.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n * Note:\n *      This API can get port isolation leaky status for RMA ,IGMP/MLD, CDP, CSSTP, and LLDP  packets.\n *      The leaky frame types are as following:\n *      - LEAKY_BRG_GROUP,\n *      - LEAKY_FD_PAUSE,\n *      - LEAKY_SP_MCAST,\n *      - LEAKY_1X_PAE,\n *      - LEAKY_UNDEF_BRG_04,\n *      - LEAKY_UNDEF_BRG_05,\n *      - LEAKY_UNDEF_BRG_06,\n *      - LEAKY_UNDEF_BRG_07,\n *      - LEAKY_PROVIDER_BRIDGE_GROUP_ADDRESS,\n *      - LEAKY_UNDEF_BRG_09,\n *      - LEAKY_UNDEF_BRG_0A,\n *      - LEAKY_UNDEF_BRG_0B,\n *      - LEAKY_UNDEF_BRG_0C,\n *      - LEAKY_PROVIDER_BRIDGE_GVRP_ADDRESS,\n *      - LEAKY_8021AB,\n *      - LEAKY_UNDEF_BRG_0F,\n *      - LEAKY_BRG_MNGEMENT,\n *      - LEAKY_UNDEFINED_11,\n *      - LEAKY_UNDEFINED_12,\n *      - LEAKY_UNDEFINED_13,\n *      - LEAKY_UNDEFINED_14,\n *      - LEAKY_UNDEFINED_15,\n *      - LEAKY_UNDEFINED_16,\n *      - LEAKY_UNDEFINED_17,\n *      - LEAKY_UNDEFINED_18,\n *      - LEAKY_UNDEFINED_19,\n *      - LEAKY_UNDEFINED_1A,\n *      - LEAKY_UNDEFINED_1B,\n *      - LEAKY_UNDEFINED_1C,\n *      - LEAKY_UNDEFINED_1D,\n *      - LEAKY_UNDEFINED_1E,\n *      - LEAKY_UNDEFINED_1F,\n *      - LEAKY_GMRP,\n *      - LEAKY_GVRP,\n *      - LEAKY_UNDEF_GARP_22,\n *      - LEAKY_UNDEF_GARP_23,\n *      - LEAKY_UNDEF_GARP_24,\n *      - LEAKY_UNDEF_GARP_25,\n *      - LEAKY_UNDEF_GARP_26,\n *      - LEAKY_UNDEF_GARP_27,\n *      - LEAKY_UNDEF_GARP_28,\n *      - LEAKY_UNDEF_GARP_29,\n *      - LEAKY_UNDEF_GARP_2A,\n *      - LEAKY_UNDEF_GARP_2B,\n *      - LEAKY_UNDEF_GARP_2C,\n *      - LEAKY_UNDEF_GARP_2D,\n *      - LEAKY_UNDEF_GARP_2E,\n *      - LEAKY_UNDEF_GARP_2F,\n *      - LEAKY_IGMP,\n *      - LEAKY_IPMULTICAST.\n *      - LEAKY_CDP,\n *      - LEAKY_CSSTP,\n *      - LEAKY_LLDP.\n */\nrtk_api_ret_t rtk_leaky_portIsolation_get(rtk_leaky_type_t type, rtk_enable_t *pEnable)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32 port, tmp;\n    rtl8367c_rma_t rmacfg;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if (type >= LEAKY_END)\n        return RT_ERR_INPUT;\n\n    if(NULL == pEnable)\n        return RT_ERR_NULL_POINTER;\n\n    if (type >= 0 && type <= LEAKY_UNDEF_GARP_2F)\n    {\n        if ((retVal = rtl8367c_getAsicRma(type, &rmacfg)) != RT_ERR_OK)\n            return retVal;\n\n        *pEnable = rmacfg.portiso_leaky;\n\n    }\n    else if (LEAKY_IPMULTICAST == type)\n    {\n        for (port = 0; port < RTK_MAX_NUM_OF_PORT; port++)\n        {\n            if ((retVal = rtl8367c_getAsicIpMulticastPortIsoLeaky(port, &tmp)) != RT_ERR_OK)\n                return retVal;\n            if (port > 0 &&(tmp != *pEnable))\n                return RT_ERR_FAILED;\n            *pEnable = tmp;\n        }\n    }\n    else if (LEAKY_IGMP == type)\n    {\n        if ((retVal = rtl8367c_getAsicIGMPIsoLeaky(&tmp)) != RT_ERR_OK)\n            return retVal;\n\n        *pEnable = tmp;\n    }\n    else if (LEAKY_CDP == type)\n    {\n        if ((retVal = rtl8367c_getAsicRmaCdp(&rmacfg)) != RT_ERR_OK)\n            return retVal;\n\n        *pEnable = rmacfg.portiso_leaky;\n    }\n    else if (LEAKY_CSSTP == type)\n    {\n        if ((retVal = rtl8367c_getAsicRmaCsstp(&rmacfg)) != RT_ERR_OK)\n            return retVal;\n\n        *pEnable = rmacfg.portiso_leaky;\n    }\n    else if (LEAKY_LLDP == type)\n    {\n        if ((retVal = rtl8367c_getAsicRmaLldp(&tmp, &rmacfg)) != RT_ERR_OK)\n            return retVal;\n\n        *pEnable = rmacfg.portiso_leaky;\n    }\n\n\n    return RT_ERR_OK;\n}\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/led.c",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * $Revision: 76306 $\n * $Date: 2017-03-08 15:13:58 +0800 (週三, 08 三月 2017) $\n *\n * Purpose : RTK switch high-level API for RTL8367/RTL8367C\n * Feature : Here is a list of all functions and variables in LED module.\n *\n */\n\n#include <rtk_switch.h>\n#include <rtk_error.h>\n#include <led.h>\n#include <string.h>\n\n#include <rtl8367c_asicdrv.h>\n#include <rtl8367c_asicdrv_led.h>\n\n\n/* Function Name:\n *      rtk_led_enable_set\n * Description:\n *      Set Led enable congiuration\n * Input:\n *      group       - LED group id.\n *      pPortmask   - LED enable port mask.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n *      RT_ERR_PORT_MASK    - Error portmask\n * Note:\n *      The API can be used to enable LED per port per group.\n */\nrtk_api_ret_t rtk_led_enable_set(rtk_led_group_t group, rtk_portmask_t *pPortmask)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32 pmask;\n    rtk_port_t port;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if (group >= LED_GROUP_END)\n        return RT_ERR_INPUT;\n\n    RTK_CHK_PORTMASK_VALID(pPortmask);\n\n    RTK_PORTMASK_SCAN((*pPortmask), port)\n    {\n        if(rtk_switch_isCPUPort(port) == RT_ERR_OK)\n            return RT_ERR_PORT_MASK;\n    }\n\n    if((retVal = rtk_switch_portmask_L2P_get(pPortmask, &pmask)) != RT_ERR_OK)\n        return retVal;\n\n    if ((retVal = rtl8367c_setAsicLedGroupEnable(group, pmask)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_led_enable_get\n * Description:\n *      Get Led enable congiuration\n * Input:\n *      group - LED group id.\n * Output:\n *      pPortmask - LED enable port mask.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n * Note:\n *      The API can be used to get LED enable status.\n */\nrtk_api_ret_t rtk_led_enable_get(rtk_led_group_t group, rtk_portmask_t *pPortmask)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32 pmask;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if (group >= LED_GROUP_END)\n        return RT_ERR_INPUT;\n\n    if ((retVal = rtl8367c_getAsicLedGroupEnable(group, &pmask)) != RT_ERR_OK)\n        return retVal;\n\n    if((retVal = rtk_switch_portmask_P2L_get(pmask, pPortmask)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n\n}\n\n/* Function Name:\n *      rtk_led_operation_set\n * Description:\n *      Set Led operation mode\n * Input:\n *      mode - LED operation mode.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n * Note:\n *      The API can set Led operation mode.\n *      The modes that can be set are as following:\n *      - LED_OP_SCAN,\n *      - LED_OP_PARALLEL,\n *      - LED_OP_SERIAL,\n */\nrtk_api_ret_t rtk_led_operation_set(rtk_led_operation_t mode)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32 regData;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if ( mode >= LED_OP_END)\n      return RT_ERR_INPUT;\n\n    switch (mode)\n    {\n        case LED_OP_PARALLEL:\n            regData = LEDOP_PARALLEL;\n            break;\n        case LED_OP_SERIAL:\n            regData = LEDOP_SERIAL;\n            break;\n        default:\n            return RT_ERR_CHIP_NOT_SUPPORTED;\n            break;\n    }\n\n    if ((retVal = rtl8367c_setAsicLedOperationMode(regData)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_led_operation_get\n * Description:\n *      Get Led operation mode\n * Input:\n *      None\n * Output:\n *      pMode - Support LED operation mode.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n * Note:\n *      The API can get Led operation mode.\n *      The modes that can be set are as following:\n *      - LED_OP_SCAN,\n *      - LED_OP_PARALLEL,\n *      - LED_OP_SERIAL,\n */\nrtk_api_ret_t rtk_led_operation_get(rtk_led_operation_t *pMode)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32 regData;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(NULL == pMode)\n        return RT_ERR_NULL_POINTER;\n\n    if ((retVal = rtl8367c_getAsicLedOperationMode(&regData)) != RT_ERR_OK)\n        return retVal;\n\n    if (regData == LEDOP_SERIAL)\n        *pMode = LED_OP_SERIAL;\n    else if (regData ==LEDOP_PARALLEL)\n        *pMode = LED_OP_PARALLEL;\n    else\n       return RT_ERR_FAILED;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_led_modeForce_set\n * Description:\n *      Set Led group to congiuration force mode\n * Input:\n *      port    - port ID\n *      group   - Support LED group id.\n *      mode    - Support LED force mode.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n *      RT_ERR_PORT_ID      - Error Port ID\n * Note:\n *      The API can force to one force mode.\n *      The force modes that can be set are as following:\n *      - LED_FORCE_NORMAL,\n *      - LED_FORCE_BLINK,\n *      - LED_FORCE_OFF,\n *      - LED_FORCE_ON.\n */\nrtk_api_ret_t rtk_led_modeForce_set(rtk_port_t port, rtk_led_group_t group, rtk_led_force_mode_t mode)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check Port Valid */\n    RTK_CHK_PORT_VALID(port);\n\n    /* No LED for CPU port */\n    if(rtk_switch_isCPUPort(port) == RT_ERR_OK)\n        return RT_ERR_PORT_ID;\n\n    if (group >= LED_GROUP_END)\n        return RT_ERR_INPUT;\n\n    if (mode >= LED_FORCE_END)\n        return RT_ERR_NOT_ALLOWED;\n\n    if ((retVal = rtl8367c_setAsicForceLed(rtk_switch_port_L2P_get(port), group, mode)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_led_modeForce_get\n * Description:\n *      Get Led group to congiuration force mode\n * Input:\n *      port  - port ID\n *      group - Support LED group id.\n *      pMode - Support LED force mode.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n *      RT_ERR_PORT_ID      - Error Port ID\n * Note:\n *      The API can get forced Led group mode.\n *      The force modes that can be set are as following:\n *      - LED_FORCE_NORMAL,\n *      - LED_FORCE_BLINK,\n *      - LED_FORCE_OFF,\n *      - LED_FORCE_ON.\n */\nrtk_api_ret_t rtk_led_modeForce_get(rtk_port_t port, rtk_led_group_t group, rtk_led_force_mode_t *pMode)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check Port Valid */\n    RTK_CHK_PORT_VALID(port);\n\n    /* No LED for CPU port */\n    if(rtk_switch_isCPUPort(port) == RT_ERR_OK)\n        return RT_ERR_PORT_ID;\n\n    if (group >= LED_GROUP_END)\n        return RT_ERR_INPUT;\n\n    if (NULL == pMode)\n        return RT_ERR_NULL_POINTER;\n\n    if ((retVal = rtl8367c_getAsicForceLed(rtk_switch_port_L2P_get(port), group, pMode)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_led_blinkRate_set\n * Description:\n *      Set LED blinking rate\n * Input:\n *      blinkRate - blinking rate.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n * Note:\n *      ASIC support 6 types of LED blinking rates at 43ms, 84ms, 120ms, 170ms, 340ms and 670ms.\n */\nrtk_api_ret_t rtk_led_blinkRate_set(rtk_led_blink_rate_t blinkRate)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if (blinkRate >= LED_BLINKRATE_END)\n        return RT_ERR_FAILED;\n\n    if ((retVal = rtl8367c_setAsicLedBlinkRate(blinkRate)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_led_blinkRate_get\n * Description:\n *      Get LED blinking rate at mode 0 to mode 3\n * Input:\n *      None\n * Output:\n *      pBlinkRate - blinking rate.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n * Note:\n *      There are  6 types of LED blinking rates at 43ms, 84ms, 120ms, 170ms, 340ms and 670ms.\n */\nrtk_api_ret_t rtk_led_blinkRate_get(rtk_led_blink_rate_t *pBlinkRate)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(NULL == pBlinkRate)\n        return RT_ERR_NULL_POINTER;\n\n    if ((retVal = rtl8367c_getAsicLedBlinkRate(pBlinkRate)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_led_groupConfig_set\n * Description:\n *      Set per group Led to congiuration mode\n * Input:\n *      group   - LED group.\n *      config  - LED configuration\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n * Note:\n *      The API can set LED indicated information configuration for each LED group with 1 to 1 led mapping to each port.\n *      - Definition  LED Statuses      Description\n *      - 0000        LED_Off           LED pin Tri-State.\n *      - 0001        Dup/Col           Collision, Full duplex Indicator.\n *      - 0010        Link/Act          Link, Activity Indicator.\n *      - 0011        Spd1000           1000Mb/s Speed Indicator.\n *      - 0100        Spd100            100Mb/s Speed Indicator.\n *      - 0101        Spd10             10Mb/s Speed Indicator.\n *      - 0110        Spd1000/Act       1000Mb/s Speed/Activity Indicator.\n *      - 0111        Spd100/Act        100Mb/s Speed/Activity Indicator.\n *      - 1000        Spd10/Act         10Mb/s Speed/Activity Indicator.\n *      - 1001        Spd100 (10)/Act   10/100Mb/s Speed/Activity Indicator.\n *      - 1010        LoopDetect        LoopDetect Indicator.\n *      - 1011        EEE               EEE Indicator.\n *      - 1100        Link/Rx           Link, Activity Indicator.\n *      - 1101        Link/Tx           Link, Activity Indicator.\n *      - 1110        Master            Link on Master Indicator.\n *      - 1111        Act               Activity Indicator. Low for link established.\n */\nrtk_api_ret_t rtk_led_groupConfig_set(rtk_led_group_t group, rtk_led_congig_t config)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if (LED_GROUP_END <= group)\n        return RT_ERR_FAILED;\n\n    if (LED_CONFIG_END <= config)\n        return RT_ERR_FAILED;\n\n    if ((retVal = rtl8367c_setAsicLedIndicateInfoConfig(group, config)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_led_groupConfig_get\n * Description:\n *      Get Led group congiuration mode\n * Input:\n *      group - LED group.\n * Output:\n *      pConfig - LED configuration.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n * Note:\n *       The API can get LED indicated information configuration for each LED group.\n */\nrtk_api_ret_t rtk_led_groupConfig_get(rtk_led_group_t group, rtk_led_congig_t *pConfig)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if (LED_GROUP_END <= group)\n        return RT_ERR_FAILED;\n\n    if(NULL == pConfig)\n        return RT_ERR_NULL_POINTER;\n\n    if ((retVal = rtl8367c_getAsicLedIndicateInfoConfig(group, pConfig)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_led_groupAbility_set\n * Description:\n *      Configure per group Led ability\n * Input:\n *      group    - LED group.\n *      pAbility - LED ability\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n * Note:\n *      None.\n */\n\nrtk_api_ret_t rtk_led_groupAbility_set(rtk_led_group_t group, rtk_led_ability_t *pAbility)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32 regData;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if (LED_GROUP_END <= group)\n        return RT_ERR_FAILED;\n\n    if(pAbility == NULL)\n        return RT_ERR_NULL_POINTER;\n\n    if( (pAbility->link_10m >= RTK_ENABLE_END) || (pAbility->link_100m >= RTK_ENABLE_END)||\n        (pAbility->link_500m >= RTK_ENABLE_END) || (pAbility->link_1000m >= RTK_ENABLE_END)||\n        (pAbility->act_rx >= RTK_ENABLE_END) || (pAbility->act_tx >= RTK_ENABLE_END) )\n    {\n        return RT_ERR_INPUT;\n    }\n\n    if ((retVal = rtl8367c_getAsicReg(RTL8367C_REG_LED0_DATA_CTRL + (rtk_uint32)group, &regData)) != RT_ERR_OK)\n        return retVal;\n\n    if(pAbility->link_10m == ENABLED)\n        regData |= 0x0001;\n    else\n        regData &= ~0x0001;\n\n    if(pAbility->link_100m == ENABLED)\n        regData |= 0x0002;\n    else\n        regData &= ~0x0002;\n\n    if(pAbility->link_500m == ENABLED)\n        regData |= 0x0004;\n    else\n        regData &= ~0x0004;\n\n    if(pAbility->link_1000m == ENABLED)\n        regData |= 0x0008;\n    else\n        regData &= ~0x0008;\n\n    if(pAbility->act_rx == ENABLED)\n        regData |= 0x0010;\n    else\n        regData &= ~0x0010;\n\n    if(pAbility->act_tx == ENABLED)\n        regData |= 0x0020;\n    else\n        regData &= ~0x0020;\n\n    regData |= (0x0001 << 6);\n\n    if ((retVal = rtl8367c_setAsicReg(RTL8367C_REG_LED0_DATA_CTRL + (rtk_uint32)group, regData)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_led_groupAbility_get\n * Description:\n *      Get per group Led ability\n * Input:\n *      group    - LED group.\n *      pAbility - LED ability\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n * Note:\n *      None.\n */\n\nrtk_api_ret_t rtk_led_groupAbility_get(rtk_led_group_t group, rtk_led_ability_t *pAbility)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32 regData;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if (LED_GROUP_END <= group)\n        return RT_ERR_FAILED;\n\n    if(pAbility == NULL)\n        return RT_ERR_NULL_POINTER;\n\n    if ((retVal = rtl8367c_getAsicReg(RTL8367C_REG_LED0_DATA_CTRL + (rtk_uint32)group, &regData)) != RT_ERR_OK)\n        return retVal;\n\n    pAbility->link_10m = (regData & 0x0001) ? ENABLED : DISABLED;\n    pAbility->link_100m = (regData & 0x0002) ? ENABLED : DISABLED;\n    pAbility->link_500m = (regData & 0x0004) ? ENABLED : DISABLED;\n    pAbility->link_1000m = (regData & 0x0008) ? ENABLED : DISABLED;\n    pAbility->act_rx = (regData & 0x0010) ? ENABLED : DISABLED;\n    pAbility->act_tx = (regData & 0x0020) ? ENABLED : DISABLED;\n\n    return RT_ERR_OK;\n}\n\n\n/* Function Name:\n *      rtk_led_serialMode_set\n * Description:\n *      Set Led serial mode active congiuration\n * Input:\n *      active - LED group.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n * Note:\n *      The API can set LED serial mode active congiuration.\n */\nrtk_api_ret_t rtk_led_serialMode_set(rtk_led_active_t active)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if ( active >= LED_ACTIVE_END)\n        return RT_ERR_INPUT;\n\n     if ((retVal = rtl8367c_setAsicLedSerialModeConfig(active,1))!=RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_led_serialMode_get\n * Description:\n *      Get Led group congiuration mode\n * Input:\n *      group - LED group.\n * Output:\n *      pConfig - LED configuration.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n * Note:\n *       The API can get LED serial mode active configuration.\n */\nrtk_api_ret_t rtk_led_serialMode_get(rtk_led_active_t *pActive)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32 regData;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(NULL == pActive)\n        return RT_ERR_NULL_POINTER;\n\n    if ((retVal = rtl8367c_getAsicLedSerialModeConfig(pActive,&regData))!=RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_led_OutputEnable_set\n * Description:\n *      This API set LED I/O state.\n * Input:\n *      enabled     - LED I/O state\n * Output:\n *      None.\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n *      RT_ERR_INPUT           - Error parameter\n * Note:\n *      This API set LED I/O state.\n */\nrtk_api_ret_t rtk_led_OutputEnable_set(rtk_enable_t state)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if (state >= RTK_ENABLE_END)\n        return RT_ERR_INPUT;\n\n    if ((retVal = rtl8367c_setAsicLedOutputEnable(state))!=RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_led_OutputEnable_get\n * Description:\n *      This API get LED I/O state.\n * Input:\n *      None.\n * Output:\n *      pEnabled        - LED I/O state\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n *      RT_ERR_INPUT           - Error parameter\n * Note:\n *      This API set current LED I/O  state.\n */\nrtk_api_ret_t rtk_led_OutputEnable_get(rtk_enable_t *pState)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(pState == NULL)\n        return RT_ERR_NULL_POINTER;\n\n    if ((retVal = rtl8367c_getAsicLedOutputEnable(pState))!=RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n\n}\n\n/* Function Name:\n *      rtk_led_serialModePortmask_set\n * Description:\n *      This API configure Serial LED output Group and portmask\n * Input:\n *      output          - output group\n *      pPortmask       - output portmask\n * Output:\n *      None.\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n *      RT_ERR_INPUT           - Error parameter\n * Note:\n *      None.\n */\nrtk_api_ret_t rtk_led_serialModePortmask_set(rtk_led_serialOutput_t output, rtk_portmask_t *pPortmask)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32 pmask;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(output >= SERIAL_LED_END)\n        return RT_ERR_INPUT;\n\n    if(pPortmask == NULL)\n        return RT_ERR_NULL_POINTER;\n\n    if ((retVal = rtk_switch_portmask_L2P_get(pPortmask, &pmask)) != RT_ERR_OK)\n        return retVal;\n\n    if ((retVal = rtl8367c_setAsicLedSerialOutput((rtk_uint32)output, pmask))!=RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_led_serialModePortmask_get\n * Description:\n *      This API get Serial LED output Group and portmask\n * Input:\n *      None.\n * Output:\n *      pOutput         - output group\n *      pPortmask       - output portmask\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n *      RT_ERR_INPUT           - Error parameter\n * Note:\n *      None.\n */\nrtk_api_ret_t rtk_led_serialModePortmask_get(rtk_led_serialOutput_t *pOutput, rtk_portmask_t *pPortmask)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32 pmask;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(pOutput == NULL)\n        return RT_ERR_NULL_POINTER;\n\n    if(pPortmask == NULL)\n        return RT_ERR_NULL_POINTER;\n\n    if ((retVal = rtl8367c_getAsicLedSerialOutput((rtk_uint32 *)pOutput, &pmask))!=RT_ERR_OK)\n        return retVal;\n\n    if((retVal = rtk_switch_portmask_P2L_get(pmask, pPortmask)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/mirror.c",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * $Revision: 76306 $\n * $Date: 2017-03-08 15:13:58 +0800 (週三, 08 三月 2017) $\n *\n * Purpose : RTK switch high-level API for RTL8367/RTL8367C\n * Feature : Here is a list of all functions and variables in Mirror module.\n *\n */\n\n#include <rtk_switch.h>\n#include <rtk_error.h>\n#include <mirror.h>\n#include <string.h>\n#include <rtl8367c_asicdrv.h>\n#include <rtl8367c_asicdrv_mirror.h>\n\n/* Function Name:\n *      rtk_mirror_portBased_set\n * Description:\n *      Set port mirror function.\n * Input:\n *      mirroring_port          - Monitor port.\n *      pMirrored_rx_portmask   - Rx mirror port mask.\n *      pMirrored_tx_portmask   - Tx mirror port mask.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number\n *      RT_ERR_PORT_MASK    - Invalid portmask.\n * Note:\n *      The API is to set mirror function of source port and mirror port.\n *      The mirror port can only be set to one port and the TX and RX mirror ports\n *      should be identical.\n */\nrtk_api_ret_t rtk_mirror_portBased_set(rtk_port_t mirroring_port, rtk_portmask_t *pMirrored_rx_portmask, rtk_portmask_t *pMirrored_tx_portmask)\n{\n    rtk_api_ret_t retVal;\n    rtk_enable_t mirRx, mirTx;\n    rtk_uint32 i, pmask;\n    rtk_port_t source_port;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check port valid */\n    RTK_CHK_PORT_VALID(mirroring_port);\n\n    if(NULL == pMirrored_rx_portmask)\n        return RT_ERR_NULL_POINTER;\n\n    if(NULL == pMirrored_tx_portmask)\n        return RT_ERR_NULL_POINTER;\n\n    RTK_CHK_PORTMASK_VALID(pMirrored_rx_portmask);\n\n    RTK_CHK_PORTMASK_VALID(pMirrored_tx_portmask);\n\n    /*Mirror Sorce Port Mask Check*/\n    if (pMirrored_tx_portmask->bits[0]!=pMirrored_rx_portmask->bits[0]&&pMirrored_tx_portmask->bits[0]!=0&&pMirrored_rx_portmask->bits[0]!=0)\n        return RT_ERR_PORT_MASK;\n\n     /*mirror port != source port*/\n    if(RTK_PORTMASK_IS_PORT_SET((*pMirrored_tx_portmask), mirroring_port) || RTK_PORTMASK_IS_PORT_SET((*pMirrored_rx_portmask), mirroring_port))\n        return RT_ERR_PORT_MASK;\n\n    source_port = rtk_switch_maxLogicalPort_get();\n\n    RTK_SCAN_ALL_LOG_PORT(i)\n    {\n        if (pMirrored_tx_portmask->bits[0]&(1<<i))\n        {\n            source_port = i;\n            break;\n        }\n\n        if (pMirrored_rx_portmask->bits[0]&(1<<i))\n        {\n            source_port = i;\n            break;\n        }\n    }\n\n    if ((retVal = rtl8367c_setAsicPortMirror(rtk_switch_port_L2P_get(source_port), rtk_switch_port_L2P_get(mirroring_port))) != RT_ERR_OK)\n        return retVal;\n    if(pMirrored_rx_portmask->bits[0] != 0)\n    {\n        if ((retVal = rtk_switch_portmask_L2P_get(pMirrored_rx_portmask, &pmask)) != RT_ERR_OK)\n            return retVal;\n        if ((retVal = rtl8367c_setAsicPortMirrorMask(pmask)) != RT_ERR_OK)\n            return retVal;\n    }\n    else\n    {\n        if ((retVal = rtk_switch_portmask_L2P_get(pMirrored_tx_portmask, &pmask)) != RT_ERR_OK)\n            return retVal;\n        if ((retVal = rtl8367c_setAsicPortMirrorMask(pmask)) != RT_ERR_OK)\n            return retVal;\n    }\n\n\n    if (pMirrored_rx_portmask->bits[0])\n        mirRx = ENABLED;\n    else\n        mirRx = DISABLED;\n\n    if ((retVal = rtl8367c_setAsicPortMirrorRxFunction(mirRx)) != RT_ERR_OK)\n        return retVal;\n\n    if (pMirrored_tx_portmask->bits[0])\n        mirTx = ENABLED;\n    else\n        mirTx = DISABLED;\n\n    if ((retVal = rtl8367c_setAsicPortMirrorTxFunction(mirTx)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n\n}\n\n/* Function Name:\n *      rtk_mirror_portBased_get\n * Description:\n *      Get port mirror function.\n * Input:\n *      None\n * Output:\n *      pMirroring_port         - Monitor port.\n *      pMirrored_rx_portmask   - Rx mirror port mask.\n *      pMirrored_tx_portmask   - Tx mirror port mask.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n * Note:\n *      The API is to get mirror function of source port and mirror port.\n */\nrtk_api_ret_t rtk_mirror_portBased_get(rtk_port_t *pMirroring_port, rtk_portmask_t *pMirrored_rx_portmask, rtk_portmask_t *pMirrored_tx_portmask)\n{\n    rtk_api_ret_t retVal;\n    rtk_port_t source_port;\n    rtk_enable_t mirRx, mirTx;\n    rtk_uint32 sport, mport, pmask;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(NULL == pMirrored_rx_portmask)\n        return RT_ERR_NULL_POINTER;\n\n    if(NULL == pMirrored_tx_portmask)\n        return RT_ERR_NULL_POINTER;\n\n    if(NULL == pMirroring_port)\n        return RT_ERR_NULL_POINTER;\n\n    if ((retVal = rtl8367c_getAsicPortMirror(&sport, &mport)) != RT_ERR_OK)\n        return retVal;\n    source_port = rtk_switch_port_P2L_get(sport);\n    *pMirroring_port = rtk_switch_port_P2L_get(mport);\n\n    if ((retVal = rtl8367c_getAsicPortMirrorRxFunction((rtk_uint32*)&mirRx)) != RT_ERR_OK)\n        return retVal;\n\n    if ((retVal = rtl8367c_getAsicPortMirrorTxFunction((rtk_uint32*)&mirTx)) != RT_ERR_OK)\n        return retVal;\n\n    if ((retVal = rtl8367c_getAsicPortMirrorMask(&pmask)) != RT_ERR_OK)\n        return retVal;\n\n    if (DISABLED == mirRx)\n        pMirrored_rx_portmask->bits[0]=0;\n    else\n    {\n        if ((retVal = rtk_switch_portmask_P2L_get(pmask, pMirrored_rx_portmask)) != RT_ERR_OK)\n            return retVal;\n        pMirrored_rx_portmask->bits[0] |= 1<<source_port;\n    }\n\n     if (DISABLED == mirTx)\n        pMirrored_tx_portmask->bits[0]=0;\n    else\n    {\n        if ((retVal = rtk_switch_portmask_P2L_get(pmask, pMirrored_tx_portmask)) != RT_ERR_OK)\n            return retVal;\n        pMirrored_tx_portmask->bits[0] |= 1<<source_port;\n    }\n\n    return RT_ERR_OK;\n\n}\n\n/* Function Name:\n *      rtk_mirror_portIso_set\n * Description:\n *      Set mirror port isolation.\n * Input:\n *      enable |Mirror isolation status.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_ENABLE       - Invalid enable input\n * Note:\n *      The API is to set mirror isolation function that prevent normal forwarding packets to miror port.\n */\nrtk_api_ret_t rtk_mirror_portIso_set(rtk_enable_t enable)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if (enable >= RTK_ENABLE_END)\n        return RT_ERR_ENABLE;\n\n    if ((retVal = rtl8367c_setAsicPortMirrorIsolation(enable)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_mirror_portIso_get\n * Description:\n *      Get mirror port isolation.\n * Input:\n *      None\n * Output:\n *      pEnable |Mirror isolation status.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n * Note:\n *      The API is to get mirror isolation status.\n */\nrtk_api_ret_t rtk_mirror_portIso_get(rtk_enable_t *pEnable)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(NULL == pEnable)\n        return RT_ERR_NULL_POINTER;\n\n    if ((retVal = rtl8367c_getAsicPortMirrorIsolation(pEnable)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_mirror_vlanLeaky_set\n * Description:\n *      Set mirror VLAN leaky.\n * Input:\n *      txenable -TX leaky enable.\n *      rxenable - RX leaky enable.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_ENABLE       - Invalid enable input\n * Note:\n *      The API is to set mirror VLAN leaky function forwarding packets to miror port.\n */\nrtk_api_ret_t rtk_mirror_vlanLeaky_set(rtk_enable_t txenable, rtk_enable_t rxenable)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if ((txenable >= RTK_ENABLE_END) ||(rxenable >= RTK_ENABLE_END))\n        return RT_ERR_ENABLE;\n\n    if ((retVal = rtl8367c_setAsicPortMirrorVlanTxLeaky(txenable)) != RT_ERR_OK)\n        return retVal;\n\n    if ((retVal = rtl8367c_setAsicPortMirrorVlanRxLeaky(rxenable)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_mirror_vlanLeaky_get\n * Description:\n *      Get mirror VLAN leaky.\n * Input:\n *      None\n * Output:\n *      pTxenable - TX leaky enable.\n *      pRxenable - RX leaky enable.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n * Note:\n *      The API is to get mirror VLAN leaky status.\n */\nrtk_api_ret_t rtk_mirror_vlanLeaky_get(rtk_enable_t *pTxenable, rtk_enable_t *pRxenable)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if( (NULL == pTxenable) || (NULL == pRxenable) )\n        return RT_ERR_NULL_POINTER;\n\n    if ((retVal = rtl8367c_getAsicPortMirrorVlanTxLeaky(pTxenable)) != RT_ERR_OK)\n        return retVal;\n\n    if ((retVal = rtl8367c_getAsicPortMirrorVlanRxLeaky(pRxenable)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_mirror_isolationLeaky_set\n * Description:\n *      Set mirror Isolation leaky.\n * Input:\n *      txenable -TX leaky enable.\n *      rxenable - RX leaky enable.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_ENABLE       - Invalid enable input\n * Note:\n *      The API is to set mirror VLAN leaky function forwarding packets to miror port.\n */\nrtk_api_ret_t rtk_mirror_isolationLeaky_set(rtk_enable_t txenable, rtk_enable_t rxenable)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if ((txenable >= RTK_ENABLE_END) ||(rxenable >= RTK_ENABLE_END))\n        return RT_ERR_ENABLE;\n\n    if ((retVal = rtl8367c_setAsicPortMirrorIsolationTxLeaky(txenable)) != RT_ERR_OK)\n        return retVal;\n\n    if ((retVal = rtl8367c_setAsicPortMirrorIsolationRxLeaky(rxenable)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_mirror_isolationLeaky_get\n * Description:\n *      Get mirror isolation leaky.\n * Input:\n *      None\n * Output:\n *      pTxenable - TX leaky enable.\n *      pRxenable - RX leaky enable.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n * Note:\n *      The API is to get mirror isolation leaky status.\n */\nrtk_api_ret_t rtk_mirror_isolationLeaky_get(rtk_enable_t *pTxenable, rtk_enable_t *pRxenable)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if( (NULL == pTxenable) || (NULL == pRxenable) )\n        return RT_ERR_NULL_POINTER;\n\n    if ((retVal = rtl8367c_getAsicPortMirrorIsolationTxLeaky(pTxenable)) != RT_ERR_OK)\n        return retVal;\n\n    if ((retVal = rtl8367c_getAsicPortMirrorIsolationRxLeaky(pRxenable)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_mirror_keep_set\n * Description:\n *      Set mirror packet format keep.\n * Input:\n *      mode - -mirror keep mode.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_ENABLE       - Invalid enable input\n * Note:\n *      The API is to set  -mirror keep mode.\n *      The mirror keep mode is as following:\n *      - MIRROR_FOLLOW_VLAN\n *      - MIRROR_KEEP_ORIGINAL\n *      - MIRROR_KEEP_END\n */\nrtk_api_ret_t rtk_mirror_keep_set(rtk_mirror_keep_t mode)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if (mode >= MIRROR_KEEP_END)\n        return RT_ERR_ENABLE;\n\n    if ((retVal = rtl8367c_setAsicPortMirrorRealKeep(mode)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_mirror_keep_get\n * Description:\n *      Get mirror packet format keep.\n * Input:\n *      None\n * Output:\n *      pMode -mirror keep mode.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n * Note:\n *      The API is to get mirror keep mode.\n  *      The mirror keep mode is as following:\n *      - MIRROR_FOLLOW_VLAN\n *      - MIRROR_KEEP_ORIGINAL\n *      - MIRROR_KEEP_END\n */\nrtk_api_ret_t rtk_mirror_keep_get(rtk_mirror_keep_t *pMode)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(NULL == pMode)\n        return RT_ERR_NULL_POINTER;\n\n    if ((retVal = rtl8367c_getAsicPortMirrorRealKeep(pMode)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_mirror_override_set\n * Description:\n *      Set port mirror override function.\n * Input:\n *      rxMirror        - 1: output mirrored packet, 0: output normal forward packet\n *      txMirror        - 1: output mirrored packet, 0: output normal forward packet\n *      aclMirror       - 1: output mirrored packet, 0: output normal forward packet\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n * Note:\n *      The API is to set mirror override function.\n *      This function control the output format when a port output\n *      normal forward & mirrored packet at the same time.\n */\nrtk_api_ret_t rtk_mirror_override_set(rtk_enable_t rxMirror, rtk_enable_t txMirror, rtk_enable_t aclMirror)\n{\n    rtk_api_ret_t retVal;\n\n    if( (rxMirror >= RTK_ENABLE_END) || (txMirror >= RTK_ENABLE_END) || (aclMirror >= RTK_ENABLE_END))\n        return RT_ERR_ENABLE;\n\n    if ((retVal = rtl8367c_setAsicPortMirrorOverride((rtk_uint32)rxMirror, (rtk_uint32)txMirror, (rtk_uint32)aclMirror)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_mirror_override_get\n * Description:\n *      Get port mirror override function.\n * Input:\n *      None\n * Output:\n *      pRxMirror       - 1: output mirrored packet, 0: output normal forward packet\n *      pTxMirror       - 1: output mirrored packet, 0: output normal forward packet\n *      pAclMirror      - 1: output mirrored packet, 0: output normal forward packet\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_NULL_POINTER - Null Pointer\n * Note:\n *      The API is to Get mirror override function.\n *      This function control the output format when a port output\n *      normal forward & mirrored packet at the same time.\n */\nrtk_api_ret_t rtk_mirror_override_get(rtk_enable_t *pRxMirror, rtk_enable_t *pTxMirror, rtk_enable_t *pAclMirror)\n{\n    rtk_api_ret_t retVal;\n\n    if( (pRxMirror == NULL) || (pTxMirror == NULL) || (pAclMirror == NULL))\n        return RT_ERR_ENABLE;\n\n    if ((retVal = rtl8367c_getAsicPortMirrorOverride((rtk_uint32 *)pRxMirror, (rtk_uint32 *)pTxMirror, (rtk_uint32 *)pAclMirror)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/oam.c",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * $Revision: 76306 $\n * $Date: 2017-03-08 15:13:58 +0800 (週三, 08 三月 2017) $\n *\n * Purpose : RTK switch high-level API for RTL8367/RTL8367C\n * Feature : Here is a list of all functions and variables in OAM(802.3ah)  module.\n *\n */\n\n#include <rtk_switch.h>\n#include <rtk_error.h>\n#include <oam.h>\n#include <string.h>\n\n#include <rtl8367c_asicdrv.h>\n#include <rtl8367c_asicdrv_oam.h>\n\n\n/* Module Name : OAM */\n\n/* Function Name:\n *      rtk_oam_init\n * Description:\n *      Initialize oam module.\n * Input:\n *      None\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n * Note:\n *      Must initialize oam module before calling any oam APIs.\n */\nrtk_api_ret_t rtk_oam_init(void)\n{\n    return RT_ERR_OK;\n} /* end of rtk_oam_init */\n\n\n/* Function Name:\n *      rtk_oam_state_set\n * Description:\n *      This API set OAM state.\n * Input:\n *      enabled     -OAMstate\n * Output:\n *      None.\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n *      RT_ERR_INPUT           - Error parameter\n * Note:\n *      This API set OAM state.\n */\nrtk_api_ret_t rtk_oam_state_set(rtk_enable_t enabled)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if (enabled >= RTK_ENABLE_END)\n        return RT_ERR_INPUT;\n\n    if ((retVal = rtl8367c_setAsicOamEnable(enabled))!=RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_oam_state_get\n * Description:\n *      This API get OAM state.\n * Input:\n *      None.\n * Output:\n *      pEnabled        - H/W IGMP state\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n *      RT_ERR_INPUT           - Error parameter\n * Note:\n *      This API set current OAM state.\n */\nrtk_api_ret_t rtk_oam_state_get(rtk_enable_t *pEnabled)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if ((retVal = rtl8367c_getAsicOamEnable(pEnabled))!=RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n\n\n/* Function Name:\n *      rtk_oam_parserAction_set\n * Description:\n *      Set OAM parser action\n * Input:\n *      port    - port id\n *      action  - parser action\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n *      RT_ERR_PORT_ID      - invalid port id\n * Note:\n *      None\n */\nrtk_api_ret_t  rtk_oam_parserAction_set(rtk_port_t port, rtk_oam_parser_act_t action)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check Port Valid */\n    RTK_CHK_PORT_VALID(port);\n\n    if (action >= OAM_PARSER_ACTION_END)\n        return RT_ERR_INPUT;\n\n    if ((retVal = rtl8367c_setAsicOamParser(rtk_switch_port_L2P_get(port), action))!=RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_oam_parserAction_set\n * Description:\n *      Get OAM parser action\n * Input:\n *      port    - port id\n * Output:\n *      pAction  - parser action\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n *      RT_ERR_PORT_ID      - invalid port id\n * Note:\n *      None\n */\nrtk_api_ret_t  rtk_oam_parserAction_get(rtk_port_t port, rtk_oam_parser_act_t *pAction)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check Port Valid */\n    RTK_CHK_PORT_VALID(port);\n\n    if ((retVal = rtl8367c_getAsicOamParser(rtk_switch_port_L2P_get(port), pAction))!=RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n\n/* Function Name:\n *      rtk_oam_multiplexerAction_set\n * Description:\n *      Set OAM multiplexer action\n * Input:\n *      port    - port id\n *      action  - parser action\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n *      RT_ERR_PORT_ID      - invalid port id\n * Note:\n *      None\n */\nrtk_api_ret_t  rtk_oam_multiplexerAction_set(rtk_port_t port, rtk_oam_multiplexer_act_t action)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check Port Valid */\n    RTK_CHK_PORT_VALID(port);\n\n    if (action >= OAM_MULTIPLEXER_ACTION_END)\n        return RT_ERR_INPUT;\n\n    if ((retVal = rtl8367c_setAsicOamMultiplexer(rtk_switch_port_L2P_get(port), action))!=RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_oam_parserAction_set\n * Description:\n *      Get OAM multiplexer action\n * Input:\n *      port    - port id\n * Output:\n *      pAction  - parser action\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n *      RT_ERR_PORT_ID      - invalid port id\n * Note:\n *      None\n */\nrtk_api_ret_t  rtk_oam_multiplexerAction_get(rtk_port_t port, rtk_oam_multiplexer_act_t *pAction)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check Port Valid */\n    RTK_CHK_PORT_VALID(port);\n\n    if ((retVal = rtl8367c_getAsicOamMultiplexer(rtk_switch_port_L2P_get(port), pAction))!=RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/port.c",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * $Revision: 76306 $\n * $Date: 2017-03-08 15:13:58 +0800 (週三, 08 三月 2017) $\n *\n * Purpose : RTK switch high-level API for RTL8367/RTL8367C\n * Feature : Here is a list of all functions and variables in Port module.\n *\n */\n\n#include <rtk_switch.h>\n#include <rtk_error.h>\n#include <port.h>\n#include <string.h>\n\n#include <rtl8367c_asicdrv.h>\n#include <rtl8367c_asicdrv_port.h>\n#include <rtl8367c_asicdrv_misc.h>\n#include <rtl8367c_asicdrv_portIsolation.h>\n\n#define FIBER_INIT_SIZE 1507\nCONST_T rtk_uint8 Fiber[FIBER_INIT_SIZE] = {\n0x02,0x04,0x41,0xE4,0xF5,0xA8,0xD2,0xAF,\n0x22,0x00,0x00,0x02,0x05,0x2D,0xE4,0x90,\n0x06,0x2A,0xF0,0xFD,0x7C,0x01,0x7F,0x3F,\n0x7E,0x1D,0x12,0x05,0xAF,0x7D,0x40,0x12,\n0x02,0x5F,0xE4,0xFF,0xFE,0xFD,0x80,0x08,\n0x12,0x05,0x9E,0x50,0x0C,0x12,0x05,0x8B,\n0xFC,0x90,0x06,0x24,0x12,0x03,0x76,0x80,\n0xEF,0xE4,0xF5,0xA8,0xD2,0xAF,0x7D,0x1F,\n0xFC,0x7F,0x49,0x7E,0x13,0x12,0x05,0xAF,\n0x12,0x05,0xD6,0x7D,0xD7,0x12,0x02,0x1E,\n0x7D,0x80,0x12,0x01,0xCA,0x7D,0x94,0x7C,\n0xF9,0x12,0x02,0x3B,0x7D,0x81,0x12,0x01,\n0xCA,0x7D,0xA2,0x7C,0x31,0x12,0x02,0x3B,\n0x7D,0x82,0x12,0x01,0xDF,0x7D,0x60,0x7C,\n0x69,0x12,0x02,0x43,0x7D,0x83,0x12,0x01,\n0xDF,0x7D,0x28,0x7C,0x97,0x12,0x02,0x43,\n0x7D,0x84,0x12,0x01,0xF4,0x7D,0x85,0x7C,\n0x9D,0x12,0x02,0x57,0x7D,0x23,0x12,0x01,\n0xF4,0x7D,0x10,0x7C,0xD8,0x12,0x02,0x57,\n0x7D,0x24,0x7C,0x04,0x12,0x02,0x28,0x7D,\n0x00,0x12,0x02,0x1E,0x7D,0x2F,0x12,0x02,\n0x09,0x7D,0x20,0x7C,0x0F,0x7F,0x02,0x7E,\n0x66,0x12,0x05,0xAF,0x7D,0x01,0x12,0x02,\n0x09,0x7D,0x04,0x7C,0x00,0x7F,0x01,0x7E,\n0x66,0x12,0x05,0xAF,0x7D,0x80,0x7C,0x00,\n0x7F,0x00,0x7E,0x66,0x12,0x05,0xAF,0x7F,\n0x02,0x7E,0x66,0x12,0x02,0x4B,0x44,0x02,\n0xFF,0x90,0x06,0x28,0xEE,0xF0,0xA3,0xEF,\n0xF0,0x44,0x04,0xFF,0x90,0x06,0x28,0xEE,\n0xF0,0xFC,0xA3,0xEF,0xF0,0xFD,0x7F,0x02,\n0x7E,0x66,0x12,0x05,0xAF,0x7D,0x04,0x7C,\n0x00,0x12,0x02,0x28,0x7D,0xB9,0x7C,0x15,\n0x7F,0xEB,0x7E,0x13,0x12,0x05,0xAF,0x7D,\n0x07,0x7C,0x00,0x7F,0xE7,0x7E,0x13,0x12,\n0x05,0xAF,0x7D,0x40,0x7C,0x11,0x7F,0x00,\n0x7E,0x62,0x12,0x05,0xAF,0x12,0x03,0x82,\n0x7D,0x41,0x12,0x02,0x5F,0xE4,0xFF,0xFE,\n0xFD,0x80,0x08,0x12,0x05,0x9E,0x50,0x0C,\n0x12,0x05,0x8B,0xFC,0x90,0x06,0x24,0x12,\n0x03,0x76,0x80,0xEF,0xC2,0x00,0xC2,0x01,\n0xD2,0xA9,0xD2,0x8C,0x7F,0x01,0x7E,0x62,\n0x12,0x02,0x4B,0x30,0xE2,0x05,0xE4,0xA3,\n0xF0,0x80,0xF1,0x90,0x06,0x2A,0xE0,0x70,\n0x12,0x12,0x01,0x89,0x90,0x06,0x2A,0x74,\n0x01,0xF0,0xE4,0x90,0x06,0x2D,0xF0,0xA3,\n0xF0,0x80,0xD9,0xC3,0x90,0x06,0x2E,0xE0,\n0x94,0x64,0x90,0x06,0x2D,0xE0,0x94,0x00,\n0x40,0xCA,0xE4,0xF0,0xA3,0xF0,0x12,0x01,\n0x89,0x90,0x06,0x2A,0x74,0x01,0xF0,0x80,\n0xBB,0x7D,0x04,0xFC,0x7F,0x02,0x7E,0x66,\n0x12,0x05,0xAF,0x7D,0x00,0x7C,0x04,0x7F,\n0x01,0x7E,0x66,0x12,0x05,0xAF,0x7D,0xC0,\n0x7C,0x00,0x7F,0x00,0x7E,0x66,0x12,0x05,\n0xAF,0xE4,0xFD,0xFC,0x7F,0x02,0x7E,0x66,\n0x12,0x05,0xAF,0x7D,0x00,0x7C,0x04,0x7F,\n0x01,0x7E,0x66,0x12,0x05,0xAF,0x7D,0xC0,\n0x7C,0x00,0x7F,0x00,0x7E,0x66,0x12,0x05,\n0xAF,0x22,0x7C,0x04,0x7F,0x01,0x7E,0x66,\n0x12,0x05,0xAF,0x7D,0xC0,0x7C,0x00,0x7F,\n0x00,0x7E,0x66,0x12,0x05,0xAF,0x22,0x7C,\n0x04,0x7F,0x01,0x7E,0x66,0x12,0x05,0xAF,\n0x7D,0xC0,0x7C,0x00,0x7F,0x00,0x7E,0x66,\n0x12,0x05,0xAF,0x22,0x7C,0x04,0x7F,0x01,\n0x7E,0x66,0x12,0x05,0xAF,0x7D,0xC0,0x7C,\n0x00,0x7F,0x00,0x7E,0x66,0x12,0x05,0xAF,\n0x22,0x7C,0x00,0x7F,0x01,0x7E,0x66,0x12,\n0x05,0xAF,0x7D,0xC0,0x7C,0x00,0x7F,0x00,\n0x7E,0x66,0x12,0x05,0xAF,0x22,0x7C,0x04,\n0x7F,0x02,0x7E,0x66,0x12,0x05,0xAF,0x22,\n0x7F,0x01,0x7E,0x66,0x12,0x05,0xAF,0x7D,\n0xC0,0x7C,0x00,0x7F,0x00,0x7E,0x66,0x12,\n0x05,0xAF,0x22,0x7F,0x02,0x7E,0x66,0x12,\n0x05,0xAF,0x22,0x7F,0x02,0x7E,0x66,0x12,\n0x05,0xAF,0x22,0x12,0x05,0x67,0x90,0x06,\n0x28,0xEE,0xF0,0xA3,0xEF,0xF0,0x22,0x7F,\n0x02,0x7E,0x66,0x12,0x05,0xAF,0x22,0x7C,\n0x00,0x7F,0x36,0x7E,0x13,0x12,0x05,0xAF,\n0x22,0xC5,0xF0,0xF8,0xA3,0xE0,0x28,0xF0,\n0xC5,0xF0,0xF8,0xE5,0x82,0x15,0x82,0x70,\n0x02,0x15,0x83,0xE0,0x38,0xF0,0x22,0x75,\n0xF0,0x08,0x75,0x82,0x00,0xEF,0x2F,0xFF,\n0xEE,0x33,0xFE,0xCD,0x33,0xCD,0xCC,0x33,\n0xCC,0xC5,0x82,0x33,0xC5,0x82,0x9B,0xED,\n0x9A,0xEC,0x99,0xE5,0x82,0x98,0x40,0x0C,\n0xF5,0x82,0xEE,0x9B,0xFE,0xED,0x9A,0xFD,\n0xEC,0x99,0xFC,0x0F,0xD5,0xF0,0xD6,0xE4,\n0xCE,0xFB,0xE4,0xCD,0xFA,0xE4,0xCC,0xF9,\n0xA8,0x82,0x22,0xB8,0x00,0xC1,0xB9,0x00,\n0x59,0xBA,0x00,0x2D,0xEC,0x8B,0xF0,0x84,\n0xCF,0xCE,0xCD,0xFC,0xE5,0xF0,0xCB,0xF9,\n0x78,0x18,0xEF,0x2F,0xFF,0xEE,0x33,0xFE,\n0xED,0x33,0xFD,0xEC,0x33,0xFC,0xEB,0x33,\n0xFB,0x10,0xD7,0x03,0x99,0x40,0x04,0xEB,\n0x99,0xFB,0x0F,0xD8,0xE5,0xE4,0xF9,0xFA,\n0x22,0x78,0x18,0xEF,0x2F,0xFF,0xEE,0x33,\n0xFE,0xED,0x33,0xFD,0xEC,0x33,0xFC,0xC9,\n0x33,0xC9,0x10,0xD7,0x05,0x9B,0xE9,0x9A,\n0x40,0x07,0xEC,0x9B,0xFC,0xE9,0x9A,0xF9,\n0x0F,0xD8,0xE0,0xE4,0xC9,0xFA,0xE4,0xCC,\n0xFB,0x22,0x75,0xF0,0x10,0xEF,0x2F,0xFF,\n0xEE,0x33,0xFE,0xED,0x33,0xFD,0xCC,0x33,\n0xCC,0xC8,0x33,0xC8,0x10,0xD7,0x07,0x9B,\n0xEC,0x9A,0xE8,0x99,0x40,0x0A,0xED,0x9B,\n0xFD,0xEC,0x9A,0xFC,0xE8,0x99,0xF8,0x0F,\n0xD5,0xF0,0xDA,0xE4,0xCD,0xFB,0xE4,0xCC,\n0xFA,0xE4,0xC8,0xF9,0x22,0xEB,0x9F,0xF5,\n0xF0,0xEA,0x9E,0x42,0xF0,0xE9,0x9D,0x42,\n0xF0,0xE8,0x9C,0x45,0xF0,0x22,0xE0,0xFC,\n0xA3,0xE0,0xFD,0xA3,0xE0,0xFE,0xA3,0xE0,\n0xFF,0x22,0xE0,0xF8,0xA3,0xE0,0xF9,0xA3,\n0xE0,0xFA,0xA3,0xE0,0xFB,0x22,0xEC,0xF0,\n0xA3,0xED,0xF0,0xA3,0xEE,0xF0,0xA3,0xEF,\n0xF0,0x22,0x12,0x03,0xF8,0x12,0x04,0x1A,\n0x44,0x40,0x12,0x04,0x0F,0x7D,0x03,0x7C,\n0x00,0x12,0x04,0x23,0x12,0x05,0xAF,0x12,\n0x03,0xF8,0x12,0x04,0x1A,0x54,0xBF,0x12,\n0x04,0x0F,0x7D,0x03,0x7C,0x00,0x12,0x03,\n0xD0,0x7F,0x02,0x7E,0x66,0x12,0x05,0x67,\n0xEF,0x54,0xFD,0x54,0xFE,0x12,0x04,0x33,\n0x12,0x03,0xD0,0x7F,0x02,0x7E,0x66,0x12,\n0x05,0x67,0xEF,0x44,0x02,0x44,0x01,0x12,\n0x04,0x33,0x12,0x04,0x23,0x02,0x05,0xAF,\n0x7F,0x01,0x7E,0x66,0x12,0x05,0xAF,0x7D,\n0xC0,0x7C,0x00,0x7F,0x00,0x7E,0x66,0x12,\n0x05,0xAF,0xE4,0xFD,0xFC,0x7F,0x01,0x7E,\n0x66,0x12,0x05,0xAF,0x7D,0x80,0x7C,0x00,\n0x7F,0x00,0x7E,0x66,0x12,0x05,0xAF,0x22,\n0x7D,0x03,0x7C,0x00,0x7F,0x01,0x7E,0x66,\n0x12,0x05,0xAF,0x7D,0x80,0x7C,0x00,0x7F,\n0x00,0x7E,0x66,0x12,0x05,0xAF,0x22,0xFD,\n0xAC,0x06,0x7F,0x02,0x7E,0x66,0x12,0x05,\n0xAF,0x22,0x7F,0x02,0x7E,0x66,0x12,0x05,\n0x67,0xEF,0x22,0x7F,0x01,0x7E,0x66,0x12,\n0x05,0xAF,0x7D,0xC0,0x7C,0x00,0x7F,0x00,\n0x7E,0x66,0x22,0xFD,0xAC,0x06,0x7F,0x02,\n0x7E,0x66,0x12,0x05,0xAF,0xE4,0xFD,0xFC,\n0x22,0x78,0x7F,0xE4,0xF6,0xD8,0xFD,0x75,\n0x81,0x3C,0x02,0x04,0x88,0x02,0x00,0x0E,\n0xE4,0x93,0xA3,0xF8,0xE4,0x93,0xA3,0x40,\n0x03,0xF6,0x80,0x01,0xF2,0x08,0xDF,0xF4,\n0x80,0x29,0xE4,0x93,0xA3,0xF8,0x54,0x07,\n0x24,0x0C,0xC8,0xC3,0x33,0xC4,0x54,0x0F,\n0x44,0x20,0xC8,0x83,0x40,0x04,0xF4,0x56,\n0x80,0x01,0x46,0xF6,0xDF,0xE4,0x80,0x0B,\n0x01,0x02,0x04,0x08,0x10,0x20,0x40,0x80,\n0x90,0x05,0xCB,0xE4,0x7E,0x01,0x93,0x60,\n0xBC,0xA3,0xFF,0x54,0x3F,0x30,0xE5,0x09,\n0x54,0x1F,0xFE,0xE4,0x93,0xA3,0x60,0x01,\n0x0E,0xCF,0x54,0xC0,0x25,0xE0,0x60,0xA8,\n0x40,0xB8,0xE4,0x93,0xA3,0xFA,0xE4,0x93,\n0xA3,0xF8,0xE4,0x93,0xA3,0xC8,0xC5,0x82,\n0xC8,0xCA,0xC5,0x83,0xCA,0xF0,0xA3,0xC8,\n0xC5,0x82,0xC8,0xCA,0xC5,0x83,0xCA,0xDF,\n0xE9,0xDE,0xE7,0x80,0xBE,0x75,0x0F,0x80,\n0x75,0x0E,0x7E,0x75,0x0D,0xAA,0x75,0x0C,\n0x83,0xE4,0xF5,0x10,0x75,0x0B,0xA0,0x75,\n0x0A,0xAC,0x75,0x09,0xB9,0x75,0x08,0x03,\n0x75,0x89,0x11,0x7B,0x60,0x7A,0x09,0xF9,\n0xF8,0xAF,0x0B,0xAE,0x0A,0xAD,0x09,0xAC,\n0x08,0x12,0x02,0xBB,0xAD,0x07,0xAC,0x06,\n0xC3,0xE4,0x9D,0xFD,0xE4,0x9C,0xFC,0x78,\n0x17,0xF6,0xAF,0x05,0xEF,0x08,0xF6,0x18,\n0xE6,0xF5,0x8C,0x08,0xE6,0xF5,0x8A,0x74,\n0x0D,0x2D,0xFD,0xE4,0x3C,0x18,0xF6,0xAF,\n0x05,0xEF,0x08,0xF6,0x75,0x88,0x10,0x53,\n0x8E,0xC7,0xD2,0xA9,0x22,0xC0,0xE0,0xC0,\n0xF0,0xC0,0x83,0xC0,0x82,0xC0,0xD0,0x75,\n0xD0,0x00,0xC0,0x00,0x78,0x17,0xE6,0xF5,\n0x8C,0x78,0x18,0xE6,0xF5,0x8A,0x90,0x06,\n0x2B,0xE4,0x75,0xF0,0x01,0x12,0x02,0x69,\n0x90,0x06,0x2D,0xE4,0x75,0xF0,0x01,0x12,\n0x02,0x69,0xD0,0x00,0xD0,0xD0,0xD0,0x82,\n0xD0,0x83,0xD0,0xF0,0xD0,0xE0,0x32,0xC2,\n0xAF,0xAD,0x07,0xAC,0x06,0x8C,0xA2,0x8D,\n0xA3,0x75,0xA0,0x01,0x00,0x00,0x00,0x00,\n0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xAE,\n0xA1,0xBE,0x00,0xF0,0xAE,0xA6,0xAF,0xA7,\n0xD2,0xAF,0x22,0x90,0x06,0x24,0x12,0x03,\n0x5E,0xEF,0x24,0x01,0xFF,0xE4,0x3E,0xFE,\n0xE4,0x3D,0xFD,0xE4,0x3C,0x22,0xE4,0x7F,\n0x20,0x7E,0x4E,0xFD,0xFC,0x90,0x06,0x24,\n0x12,0x03,0x6A,0xC3,0x02,0x03,0x4D,0xC2,\n0xAF,0xAB,0x07,0xAA,0x06,0x8A,0xA2,0x8B,\n0xA3,0x8C,0xA4,0x8D,0xA5,0x75,0xA0,0x03,\n0x00,0x00,0x00,0xAA,0xA1,0xBA,0x00,0xF8,\n0xD2,0xAF,0x22,0x42,0x06,0x2D,0x00,0x00,\n0x42,0x06,0x2B,0x00,0x00,0x00,0x12,0x05,\n0xDF,0x12,0x04,0xCD,0x02,0x00,0x03,0xE4,\n0xF5,0x8E,0x22};\n\nstatic rtk_api_ret_t _rtk_port_FiberModeAbility_set(rtk_port_t port, rtk_port_phy_ability_t *pAbility)\n{\n    rtk_api_ret_t   retVal;\n    rtk_uint32      regData;\n\n    /* Check Combo port or not */\n    RTK_CHK_PORT_IS_COMBO(port);\n\n    /* Flow Control */\n    if ((retVal = rtl8367c_getAsicReg(RTL8367C_REG_FIB0_CFG04, &regData)) != RT_ERR_OK)\n        return retVal;\n\n    if (pAbility->AsyFC == 1)\n        regData |= (0x0001 << 8);\n    else\n        regData &= ~(0x0001 << 8);\n\n    if (pAbility->FC == 1)\n        regData |= (0x0001 << 7);\n    else\n        regData &= ~(0x0001 << 7);\n\n    if ((retVal = rtl8367c_setAsicReg(RTL8367C_REG_FIB0_CFG04, regData)) != RT_ERR_OK)\n        return retVal;\n\n    /* Speed ability */\n    if( (pAbility->Full_1000 == 1) && (pAbility->Full_100 == 1) && (pAbility->AutoNegotiation == 1) )\n    {\n        if ((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_FIBER_CFG_1, RTL8367C_SDS_FRC_MODE_OFFSET, 0)) != RT_ERR_OK)\n            return retVal;\n\n        if ((retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_FIBER_CFG_1, RTL8367C_SDS_MODE_MASK, 7)) != RT_ERR_OK)\n            return retVal;\n\n        if ((retVal = rtl8367c_setAsicReg(RTL8367C_REG_FIB0_CFG00, 0x1140)) != RT_ERR_OK)\n            return retVal;\n    }\n    else if(pAbility->Full_1000 == 1)\n    {\n        if ((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_FIBER_CFG_1, RTL8367C_SDS_FRC_MODE_OFFSET, 1)) != RT_ERR_OK)\n            return retVal;\n\n        if ((retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_FIBER_CFG_1, RTL8367C_SDS_MODE_MASK, 4)) != RT_ERR_OK)\n            return retVal;\n\n        if(pAbility->AutoNegotiation == 1)\n        {\n            if ((retVal = rtl8367c_setAsicReg(RTL8367C_REG_FIB0_CFG00, 0x1140)) != RT_ERR_OK)\n                return retVal;\n        }\n        else\n        {\n            if ((retVal = rtl8367c_setAsicReg(RTL8367C_REG_FIB0_CFG00, 0x0140)) != RT_ERR_OK)\n                return retVal;\n        }\n    }\n    else if(pAbility->Full_100 == 1)\n    {\n        if ((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_FIBER_CFG_1, RTL8367C_SDS_FRC_MODE_OFFSET, 1)) != RT_ERR_OK)\n            return retVal;\n\n        if ((retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_FIBER_CFG_1, RTL8367C_SDS_MODE_MASK, 5)) != RT_ERR_OK)\n            return retVal;\n\n        if ((retVal = rtl8367c_setAsicReg(RTL8367C_REG_FIB0_CFG00, 0x2100)) != RT_ERR_OK)\n            return retVal;\n    }\n\n    /* Digital software reset */\n    if ((retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_ADR, 0x0003)) != RT_ERR_OK)\n        return retVal;\n\n    if ((retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_CMD, 0x0080)) != RT_ERR_OK)\n        return retVal;\n\n    if ((retVal = rtl8367c_getAsicReg(RTL8367C_REG_SDS_INDACS_DATA, &regData)) != RT_ERR_OK)\n        return retVal;\n\n    regData |= (0x0001 << 6);\n\n    if ((retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_DATA, regData)) != RT_ERR_OK)\n        return retVal;\n\n    if ((retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_ADR, 0x0003)) != RT_ERR_OK)\n        return retVal;\n\n    if ((retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_CMD, 0x00C0)) != RT_ERR_OK)\n        return retVal;\n\n    regData &= ~(0x0001 << 6);\n\n    if ((retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_DATA, regData)) != RT_ERR_OK)\n        return retVal;\n\n    if ((retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_ADR, 0x0003)) != RT_ERR_OK)\n        return retVal;\n\n    if ((retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_CMD, 0x00C0)) != RT_ERR_OK)\n        return retVal;\n\n    /* CDR reset */\n    if ((retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_DATA, 0x1401))!=RT_ERR_OK)\n        return retVal;\n\n    if ((retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_ADR, 0x0000))!=RT_ERR_OK)\n        return retVal;\n\n    if ((retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_CMD, 0x00C0))!=RT_ERR_OK)\n        return retVal;\n\n    if ((retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_DATA, 0x1403))!=RT_ERR_OK)\n        return retVal;\n\n    if ((retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_ADR, 0x0000))!=RT_ERR_OK)\n        return retVal;\n\n    if ((retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_CMD, 0x00C0))!=RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\nstatic rtk_api_ret_t _rtk_port_FiberModeAbility_get(rtk_port_t port, rtk_port_phy_ability_t *pAbility)\n{\n    rtk_api_ret_t   retVal;\n    rtk_uint32      data, regData;\n\n    /* Check Combo port or not */\n    RTK_CHK_PORT_IS_COMBO(port);\n\n    memset(pAbility, 0x00, sizeof(rtk_port_phy_ability_t));\n\n    /* Flow Control */\n    if ((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_FIBER_CFG_1, RTL8367C_SDS_FRC_REG4_OFFSET, 1)) != RT_ERR_OK)\n        return retVal;\n\n    if ((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_FIBER_CFG_1, RTL8367C_SDS_FRC_REG4_FIB100_OFFSET, 0)) != RT_ERR_OK)\n        return retVal;\n\n    if ((retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_ADR, 0x0044)) != RT_ERR_OK)\n        return retVal;\n\n    if ((retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_CMD, 0x0080)) != RT_ERR_OK)\n        return retVal;\n\n    if ((retVal = rtl8367c_getAsicReg(RTL8367C_REG_SDS_INDACS_DATA, &regData)) != RT_ERR_OK)\n        return retVal;\n\n    if(regData & (0x0001 << 8))\n        pAbility->AsyFC = 1;\n\n    if(regData & (0x0001 << 7))\n        pAbility->FC = 1;\n\n    /* Speed ability */\n    if ((retVal = rtl8367c_getAsicRegBit(RTL8367C_REG_FIBER_CFG_1, RTL8367C_SDS_FRC_MODE_OFFSET, &data)) != RT_ERR_OK)\n            return retVal;\n\n    if(data == 0)\n    {\n        pAbility->AutoNegotiation = 1;\n        pAbility->Full_1000 = 1;\n        pAbility->Full_100 = 1;\n    }\n    else\n    {\n        if ((retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_FIBER_CFG_1, RTL8367C_SDS_MODE_MASK, &data)) != RT_ERR_OK)\n            return retVal;\n\n        if(data == 4)\n        {\n            pAbility->Full_1000 = 1;\n\n            if ((retVal = rtl8367c_getAsicReg(RTL8367C_REG_FIB0_CFG00, &data)) != RT_ERR_OK)\n                return retVal;\n\n            if(data & 0x1000)\n                pAbility->AutoNegotiation = 1;\n            else\n                pAbility->AutoNegotiation = 0;\n        }\n        else if(data == 5)\n            pAbility->Full_100 = 1;\n        else\n            return RT_ERR_FAILED;\n    }\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_port_phyAutoNegoAbility_set\n * Description:\n *      Set ethernet PHY auto-negotiation desired ability.\n * Input:\n *      port        - port id.\n *      pAbility    - Ability structure\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - OK\n *      RT_ERR_FAILED           - Failed\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_PORT_ID          - Invalid port number.\n *      RT_ERR_PHY_REG_ID       - Invalid PHY address\n *      RT_ERR_INPUT            - Invalid input parameters.\n *      RT_ERR_BUSYWAIT_TIMEOUT - PHY access busy\n * Note:\n *      If Full_1000 bit is set to 1, the AutoNegotiation will be automatic set to 1. While both AutoNegotiation and Full_1000 are set to 0, the PHY speed and duplex selection will\n *      be set as following 100F > 100H > 10F > 10H priority sequence.\n */\nrtk_api_ret_t rtk_port_phyAutoNegoAbility_set(rtk_port_t port, rtk_port_phy_ability_t *pAbility)\n{\n    rtk_api_ret_t       retVal;\n    rtk_uint32          phyData;\n    rtk_uint32          phyEnMsk0;\n    rtk_uint32          phyEnMsk4;\n    rtk_uint32          phyEnMsk9;\n    rtk_port_media_t    media_type;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check Port Valid */\n    RTK_CHK_PORT_IS_UTP(port);\n\n    if(NULL == pAbility)\n        return RT_ERR_NULL_POINTER;\n\n    if (pAbility->Half_10 >= RTK_ENABLE_END || pAbility->Full_10 >= RTK_ENABLE_END ||\n       pAbility->Half_100 >= RTK_ENABLE_END || pAbility->Full_100 >= RTK_ENABLE_END ||\n       pAbility->Full_1000 >= RTK_ENABLE_END || pAbility->AutoNegotiation >= RTK_ENABLE_END ||\n       pAbility->AsyFC >= RTK_ENABLE_END || pAbility->FC >= RTK_ENABLE_END)\n        return RT_ERR_INPUT;\n\n    if (rtk_switch_isComboPort(port) == RT_ERR_OK)\n    {\n        if ((retVal = rtk_port_phyComboPortMedia_get(port, &media_type)) != RT_ERR_OK)\n            return retVal;\n\n        if(media_type == PORT_MEDIA_FIBER)\n        {\n            return _rtk_port_FiberModeAbility_set(port, pAbility);\n        }\n    }\n\n    /*for PHY auto mode setup*/\n    pAbility->AutoNegotiation = 1;\n\n    phyEnMsk0 = 0;\n    phyEnMsk4 = 0;\n    phyEnMsk9 = 0;\n\n    if (1 == pAbility->Half_10)\n    {\n        /*10BASE-TX half duplex capable in reg 4.5*/\n        phyEnMsk4 = phyEnMsk4 | (1 << 5);\n\n        /*Speed selection [1:0] */\n        /* 11=Reserved*/\n        /* 10= 1000Mpbs*/\n        /* 01= 100Mpbs*/\n        /* 00= 10Mpbs*/\n        phyEnMsk0 = phyEnMsk0 & (~(1 << 6));\n        phyEnMsk0 = phyEnMsk0 & (~(1 << 13));\n    }\n\n    if (1 == pAbility->Full_10)\n    {\n        /*10BASE-TX full duplex capable in reg 4.6*/\n        phyEnMsk4 = phyEnMsk4 | (1 << 6);\n        /*Speed selection [1:0] */\n        /* 11=Reserved*/\n        /* 10= 1000Mpbs*/\n        /* 01= 100Mpbs*/\n        /* 00= 10Mpbs*/\n        phyEnMsk0 = phyEnMsk0 & (~(1 << 6));\n        phyEnMsk0 = phyEnMsk0 & (~(1 << 13));\n\n        /*Full duplex mode in reg 0.8*/\n        phyEnMsk0 = phyEnMsk0 | (1 << 8);\n\n    }\n\n    if (1 == pAbility->Half_100)\n    {\n        /*100BASE-TX half duplex capable in reg 4.7*/\n        phyEnMsk4 = phyEnMsk4 | (1 << 7);\n        /*Speed selection [1:0] */\n        /* 11=Reserved*/\n        /* 10= 1000Mpbs*/\n        /* 01= 100Mpbs*/\n        /* 00= 10Mpbs*/\n        phyEnMsk0 = phyEnMsk0 & (~(1 << 6));\n        phyEnMsk0 = phyEnMsk0 | (1 << 13);\n    }\n\n\n    if (1 == pAbility->Full_100)\n    {\n        /*100BASE-TX full duplex capable in reg 4.8*/\n        phyEnMsk4 = phyEnMsk4 | (1 << 8);\n        /*Speed selection [1:0] */\n        /* 11=Reserved*/\n        /* 10= 1000Mpbs*/\n        /* 01= 100Mpbs*/\n        /* 00= 10Mpbs*/\n        phyEnMsk0 = phyEnMsk0 & (~(1 << 6));\n        phyEnMsk0 = phyEnMsk0 | (1 << 13);\n        /*Full duplex mode in reg 0.8*/\n        phyEnMsk0 = phyEnMsk0 | (1 << 8);\n    }\n\n\n    if (1 == pAbility->Full_1000)\n    {\n        /*1000 BASE-T FULL duplex capable setting in reg 9.9*/\n        phyEnMsk9 = phyEnMsk9 | (1 << 9);\n\n        /*Speed selection [1:0] */\n        /* 11=Reserved*/\n        /* 10= 1000Mpbs*/\n        /* 01= 100Mpbs*/\n        /* 00= 10Mpbs*/\n        phyEnMsk0 = phyEnMsk0 | (1 << 6);\n        phyEnMsk0 = phyEnMsk0 & (~(1 << 13));\n\n\n        /*Auto-Negotiation setting in reg 0.12*/\n        phyEnMsk0 = phyEnMsk0 | (1 << 12);\n\n     }\n\n    if (1 == pAbility->AutoNegotiation)\n    {\n        /*Auto-Negotiation setting in reg 0.12*/\n        phyEnMsk0 = phyEnMsk0 | (1 << 12);\n    }\n\n    if (1 == pAbility->AsyFC)\n    {\n        /*Asymetric flow control in reg 4.11*/\n        phyEnMsk4 = phyEnMsk4 | (1 << 11);\n    }\n    if (1 == pAbility->FC)\n    {\n        /*Flow control in reg 4.10*/\n        phyEnMsk4 = phyEnMsk4 | (1 << 10);\n    }\n\n    /*1000 BASE-T control register setting*/\n    if ((retVal = rtl8367c_getAsicPHYReg(rtk_switch_port_L2P_get(port), PHY_1000_BASET_CONTROL_REG, &phyData)) != RT_ERR_OK)\n        return retVal;\n\n    phyData = (phyData & (~0x0200)) | phyEnMsk9 ;\n\n    if ((retVal = rtl8367c_setAsicPHYReg(rtk_switch_port_L2P_get(port), PHY_1000_BASET_CONTROL_REG, phyData)) != RT_ERR_OK)\n        return retVal;\n\n    /*Auto-Negotiation control register setting*/\n    if ((retVal = rtl8367c_getAsicPHYReg(rtk_switch_port_L2P_get(port), PHY_AN_ADVERTISEMENT_REG, &phyData)) != RT_ERR_OK)\n        return retVal;\n\n    phyData = (phyData & (~0x0DE0)) | phyEnMsk4;\n    if ((retVal = rtl8367c_setAsicPHYReg(rtk_switch_port_L2P_get(port), PHY_AN_ADVERTISEMENT_REG, phyData)) != RT_ERR_OK)\n        return retVal;\n\n    /*Control register setting and restart auto*/\n    if ((retVal = rtl8367c_getAsicPHYReg(rtk_switch_port_L2P_get(port), PHY_CONTROL_REG, &phyData)) != RT_ERR_OK)\n        return retVal;\n\n    phyData = (phyData & (~0x3140)) | phyEnMsk0;\n    /*If have auto-negotiation capable, then restart auto negotiation*/\n    if (1 == pAbility->AutoNegotiation)\n    {\n        phyData = phyData | (1 << 9);\n    }\n\n    if ((retVal = rtl8367c_setAsicPHYReg(rtk_switch_port_L2P_get(port), PHY_CONTROL_REG, phyData)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_port_phyAutoNegoAbility_get\n * Description:\n *      Get PHY ability through PHY registers.\n * Input:\n *      port - Port id.\n * Output:\n *      pAbility - Ability structure\n * Return:\n *      RT_ERR_OK               - OK\n *      RT_ERR_FAILED           - Failed\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_PORT_ID          - Invalid port number.\n *      RT_ERR_PHY_REG_ID       - Invalid PHY address\n *      RT_ERR_INPUT            - Invalid input parameters.\n *      RT_ERR_BUSYWAIT_TIMEOUT - PHY access busy\n * Note:\n *      Get the capablity of specified PHY.\n */\nrtk_api_ret_t rtk_port_phyAutoNegoAbility_get(rtk_port_t port, rtk_port_phy_ability_t *pAbility)\n{\n    rtk_api_ret_t       retVal;\n    rtk_uint32          phyData0;\n    rtk_uint32          phyData4;\n    rtk_uint32          phyData9;\n    rtk_port_media_t    media_type;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check Port Valid */\n    RTK_CHK_PORT_IS_UTP(port);\n\n    if(NULL == pAbility)\n        return RT_ERR_NULL_POINTER;\n\n    if (rtk_switch_isComboPort(port) == RT_ERR_OK)\n    {\n        if ((retVal = rtk_port_phyComboPortMedia_get(port, &media_type)) != RT_ERR_OK)\n            return retVal;\n\n        if(media_type == PORT_MEDIA_FIBER)\n        {\n            return _rtk_port_FiberModeAbility_get(port, pAbility);\n        }\n    }\n\n    /*Control register setting and restart auto*/\n    if ((retVal = rtl8367c_getAsicPHYReg(rtk_switch_port_L2P_get(port), PHY_CONTROL_REG, &phyData0)) != RT_ERR_OK)\n        return retVal;\n\n    /*Auto-Negotiation control register setting*/\n    if ((retVal = rtl8367c_getAsicPHYReg(rtk_switch_port_L2P_get(port), PHY_AN_ADVERTISEMENT_REG, &phyData4)) != RT_ERR_OK)\n        return retVal;\n\n    /*1000 BASE-T control register setting*/\n    if ((retVal = rtl8367c_getAsicPHYReg(rtk_switch_port_L2P_get(port), PHY_1000_BASET_CONTROL_REG, &phyData9)) != RT_ERR_OK)\n        return retVal;\n\n    if (phyData9 & (1 << 9))\n        pAbility->Full_1000 = 1;\n    else\n        pAbility->Full_1000 = 0;\n\n    if (phyData4 & (1 << 11))\n        pAbility->AsyFC = 1;\n    else\n        pAbility->AsyFC = 0;\n\n    if (phyData4 & (1 << 10))\n        pAbility->FC = 1;\n    else\n        pAbility->FC = 0;\n\n\n    if (phyData4 & (1 << 8))\n        pAbility->Full_100 = 1;\n    else\n        pAbility->Full_100 = 0;\n\n    if (phyData4 & (1 << 7))\n        pAbility->Half_100 = 1;\n    else\n        pAbility->Half_100 = 0;\n\n    if (phyData4 & (1 << 6))\n        pAbility->Full_10 = 1;\n    else\n        pAbility->Full_10 = 0;\n\n    if (phyData4 & (1 << 5))\n        pAbility->Half_10 = 1;\n    else\n        pAbility->Half_10 = 0;\n\n\n    if (phyData0 & (1 << 12))\n        pAbility->AutoNegotiation = 1;\n    else\n        pAbility->AutoNegotiation = 0;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_port_phyForceModeAbility_set\n * Description:\n *      Set the port speed/duplex mode/pause/asy_pause in the PHY force mode.\n * Input:\n *      port        - port id.\n *      pAbility    - Ability structure\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - OK\n *      RT_ERR_FAILED           - Failed\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_PORT_ID          - Invalid port number.\n *      RT_ERR_PHY_REG_ID       - Invalid PHY address\n *      RT_ERR_INPUT            - Invalid input parameters.\n *      RT_ERR_BUSYWAIT_TIMEOUT - PHY access busy\n * Note:\n *      While both AutoNegotiation and Full_1000 are set to 0, the PHY speed and duplex selection will\n *      be set as following 100F > 100H > 10F > 10H priority sequence.\n *      This API can be used to configure combo port in fiber mode.\n *      The possible parameters in fiber mode are Full_1000 and Full 100.\n *      All the other fields in rtk_port_phy_ability_t will be ignored in fiber port.\n */\nrtk_api_ret_t rtk_port_phyForceModeAbility_set(rtk_port_t port, rtk_port_phy_ability_t *pAbility)\n{\n     rtk_api_ret_t      retVal;\n     rtk_uint32         phyData;\n     rtk_uint32         phyEnMsk0;\n     rtk_uint32         phyEnMsk4;\n     rtk_uint32         phyEnMsk9;\n     rtk_port_media_t   media_type;\n\n     /* Check initialization state */\n     RTK_CHK_INIT_STATE();\n\n     /* Check Port Valid */\n     RTK_CHK_PORT_IS_UTP(port);\n\n     if(NULL == pAbility)\n        return RT_ERR_NULL_POINTER;\n\n     if (pAbility->Half_10 >= RTK_ENABLE_END || pAbility->Full_10 >= RTK_ENABLE_END ||\n        pAbility->Half_100 >= RTK_ENABLE_END || pAbility->Full_100 >= RTK_ENABLE_END ||\n        pAbility->Full_1000 >= RTK_ENABLE_END || pAbility->AutoNegotiation >= RTK_ENABLE_END ||\n        pAbility->AsyFC >= RTK_ENABLE_END || pAbility->FC >= RTK_ENABLE_END)\n         return RT_ERR_INPUT;\n\n     if (rtk_switch_isComboPort(port) == RT_ERR_OK)\n     {\n         if ((retVal = rtk_port_phyComboPortMedia_get(port, &media_type)) != RT_ERR_OK)\n             return retVal;\n\n         if(media_type == PORT_MEDIA_FIBER)\n         {\n             return _rtk_port_FiberModeAbility_set(port, pAbility);\n         }\n     }\n\n     if (1 == pAbility->Full_1000)\n         return RT_ERR_INPUT;\n\n     /*for PHY force mode setup*/\n     pAbility->AutoNegotiation = 0;\n\n     phyEnMsk0 = 0;\n     phyEnMsk4 = 0;\n     phyEnMsk9 = 0;\n\n     if (1 == pAbility->Half_10)\n     {\n         /*10BASE-TX half duplex capable in reg 4.5*/\n         phyEnMsk4 = phyEnMsk4 | (1 << 5);\n\n         /*Speed selection [1:0] */\n         /* 11=Reserved*/\n         /* 10= 1000Mpbs*/\n         /* 01= 100Mpbs*/\n         /* 00= 10Mpbs*/\n         phyEnMsk0 = phyEnMsk0 & (~(1 << 6));\n         phyEnMsk0 = phyEnMsk0 & (~(1 << 13));\n     }\n\n     if (1 == pAbility->Full_10)\n     {\n         /*10BASE-TX full duplex capable in reg 4.6*/\n         phyEnMsk4 = phyEnMsk4 | (1 << 6);\n         /*Speed selection [1:0] */\n         /* 11=Reserved*/\n         /* 10= 1000Mpbs*/\n         /* 01= 100Mpbs*/\n         /* 00= 10Mpbs*/\n         phyEnMsk0 = phyEnMsk0 & (~(1 << 6));\n         phyEnMsk0 = phyEnMsk0 & (~(1 << 13));\n\n         /*Full duplex mode in reg 0.8*/\n         phyEnMsk0 = phyEnMsk0 | (1 << 8);\n\n     }\n\n     if (1 == pAbility->Half_100)\n     {\n         /*100BASE-TX half duplex capable in reg 4.7*/\n         phyEnMsk4 = phyEnMsk4 | (1 << 7);\n         /*Speed selection [1:0] */\n         /* 11=Reserved*/\n         /* 10= 1000Mpbs*/\n         /* 01= 100Mpbs*/\n         /* 00= 10Mpbs*/\n         phyEnMsk0 = phyEnMsk0 & (~(1 << 6));\n         phyEnMsk0 = phyEnMsk0 | (1 << 13);\n     }\n\n\n     if (1 == pAbility->Full_100)\n     {\n         /*100BASE-TX full duplex capable in reg 4.8*/\n         phyEnMsk4 = phyEnMsk4 | (1 << 8);\n         /*Speed selection [1:0] */\n         /* 11=Reserved*/\n         /* 10= 1000Mpbs*/\n         /* 01= 100Mpbs*/\n         /* 00= 10Mpbs*/\n         phyEnMsk0 = phyEnMsk0 & (~(1 << 6));\n         phyEnMsk0 = phyEnMsk0 | (1 << 13);\n         /*Full duplex mode in reg 0.8*/\n         phyEnMsk0 = phyEnMsk0 | (1 << 8);\n     }\n\n     if (1 == pAbility->AsyFC)\n     {\n         /*Asymetric flow control in reg 4.11*/\n         phyEnMsk4 = phyEnMsk4 | (1 << 11);\n     }\n     if (1 == pAbility->FC)\n     {\n         /*Flow control in reg 4.10*/\n         phyEnMsk4 = phyEnMsk4 | ((1 << 10));\n     }\n\n     /*1000 BASE-T control register setting*/\n     if ((retVal = rtl8367c_getAsicPHYReg(rtk_switch_port_L2P_get(port), PHY_1000_BASET_CONTROL_REG, &phyData)) != RT_ERR_OK)\n         return retVal;\n\n     phyData = (phyData & (~0x0200)) | phyEnMsk9 ;\n\n     if ((retVal = rtl8367c_setAsicPHYReg(rtk_switch_port_L2P_get(port), PHY_1000_BASET_CONTROL_REG, phyData)) != RT_ERR_OK)\n         return retVal;\n\n     /*Auto-Negotiation control register setting*/\n     if ((retVal = rtl8367c_getAsicPHYReg(rtk_switch_port_L2P_get(port), PHY_AN_ADVERTISEMENT_REG, &phyData)) != RT_ERR_OK)\n         return retVal;\n\n     phyData = (phyData & (~0x0DE0)) | phyEnMsk4;\n     if ((retVal = rtl8367c_setAsicPHYReg(rtk_switch_port_L2P_get(port), PHY_AN_ADVERTISEMENT_REG, phyData)) != RT_ERR_OK)\n         return retVal;\n\n     /*Control register setting and power off/on*/\n     phyData = phyEnMsk0 & (~(1 << 12));\n     phyData |= (1 << 11);   /* power down PHY, bit 11 should be set to 1 */\n     if ((retVal = rtl8367c_setAsicPHYReg(rtk_switch_port_L2P_get(port), PHY_CONTROL_REG, phyData)) != RT_ERR_OK)\n         return retVal;\n\n     phyData = phyData & (~(1 << 11));   /* power on PHY, bit 11 should be set to 0*/\n     if ((retVal = rtl8367c_setAsicPHYReg(rtk_switch_port_L2P_get(port), PHY_CONTROL_REG, phyData)) != RT_ERR_OK)\n         return retVal;\n\n     return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_port_phyForceModeAbility_get\n * Description:\n *      Get PHY ability through PHY registers.\n * Input:\n *      port - Port id.\n * Output:\n *      pAbility - Ability structure\n * Return:\n *      RT_ERR_OK               - OK\n *      RT_ERR_FAILED           - Failed\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_PORT_ID          - Invalid port number.\n *      RT_ERR_PHY_REG_ID       - Invalid PHY address\n *      RT_ERR_INPUT            - Invalid input parameters.\n *      RT_ERR_BUSYWAIT_TIMEOUT - PHY access busy\n * Note:\n *      Get the capablity of specified PHY.\n */\nrtk_api_ret_t rtk_port_phyForceModeAbility_get(rtk_port_t port, rtk_port_phy_ability_t *pAbility)\n{\n    rtk_api_ret_t       retVal;\n    rtk_uint32          phyData0;\n    rtk_uint32          phyData4;\n    rtk_uint32          phyData9;\n    rtk_port_media_t    media_type;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check Port Valid */\n     RTK_CHK_PORT_IS_UTP(port);\n\n     if(NULL == pAbility)\n        return RT_ERR_NULL_POINTER;\n\n     if (rtk_switch_isComboPort(port) == RT_ERR_OK)\n     {\n         if ((retVal = rtk_port_phyComboPortMedia_get(port, &media_type)) != RT_ERR_OK)\n             return retVal;\n\n         if(media_type == PORT_MEDIA_FIBER)\n         {\n             return _rtk_port_FiberModeAbility_get(port, pAbility);\n         }\n     }\n\n    /*Control register setting and restart auto*/\n    if ((retVal = rtl8367c_getAsicPHYReg(rtk_switch_port_L2P_get(port), PHY_CONTROL_REG, &phyData0)) != RT_ERR_OK)\n        return retVal;\n\n    /*Auto-Negotiation control register setting*/\n    if ((retVal = rtl8367c_getAsicPHYReg(rtk_switch_port_L2P_get(port), PHY_AN_ADVERTISEMENT_REG, &phyData4)) != RT_ERR_OK)\n        return retVal;\n\n    /*1000 BASE-T control register setting*/\n    if ((retVal = rtl8367c_getAsicPHYReg(rtk_switch_port_L2P_get(port), PHY_1000_BASET_CONTROL_REG, &phyData9)) != RT_ERR_OK)\n        return retVal;\n\n    if (phyData9 & (1 << 9))\n        pAbility->Full_1000 = 1;\n    else\n        pAbility->Full_1000 = 0;\n\n    if (phyData4 & (1 << 11))\n        pAbility->AsyFC = 1;\n    else\n        pAbility->AsyFC = 0;\n\n    if (phyData4 & ((1 << 10)))\n        pAbility->FC = 1;\n    else\n        pAbility->FC = 0;\n\n\n    if (phyData4 & (1 << 8))\n        pAbility->Full_100 = 1;\n    else\n        pAbility->Full_100 = 0;\n\n    if (phyData4 & (1 << 7))\n        pAbility->Half_100 = 1;\n    else\n        pAbility->Half_100 = 0;\n\n    if (phyData4 & (1 << 6))\n        pAbility->Full_10 = 1;\n    else\n        pAbility->Full_10 = 0;\n\n    if (phyData4 & (1 << 5))\n        pAbility->Half_10 = 1;\n    else\n        pAbility->Half_10 = 0;\n\n\n    if (phyData0 & (1 << 12))\n        pAbility->AutoNegotiation = 1;\n    else\n        pAbility->AutoNegotiation = 0;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_port_phyStatus_get\n * Description:\n *      Get ethernet PHY linking status\n * Input:\n *      port - Port id.\n * Output:\n *      linkStatus  - PHY link status\n *      speed       - PHY link speed\n *      duplex      - PHY duplex mode\n * Return:\n *      RT_ERR_OK               - OK\n *      RT_ERR_FAILED           - Failed\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_PORT_ID          - Invalid port number.\n *      RT_ERR_PHY_REG_ID       - Invalid PHY address\n *      RT_ERR_INPUT            - Invalid input parameters.\n *      RT_ERR_BUSYWAIT_TIMEOUT - PHY access busy\n * Note:\n *      API will return auto negotiation status of phy.\n */\nrtk_api_ret_t rtk_port_phyStatus_get(rtk_port_t port, rtk_port_linkStatus_t *pLinkStatus, rtk_port_speed_t *pSpeed, rtk_port_duplex_t *pDuplex)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32 phyData;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check Port Valid */\n    RTK_CHK_PORT_IS_UTP(port);\n\n    if( (NULL == pLinkStatus) || (NULL == pSpeed) || (NULL == pDuplex) )\n        return RT_ERR_NULL_POINTER;\n\n    /*Get PHY resolved register*/\n    if ((retVal = rtl8367c_getAsicPHYReg(rtk_switch_port_L2P_get(port), PHY_RESOLVED_REG, &phyData)) != RT_ERR_OK)\n        return retVal;\n\n    /*check link status*/\n    if (phyData & (1<<2))\n    {\n        *pLinkStatus = 1;\n\n        /*check link speed*/\n        *pSpeed = (phyData&0x0030) >> 4;\n\n        /*check link duplex*/\n        *pDuplex = (phyData&0x0008) >> 3;\n    }\n    else\n    {\n        *pLinkStatus = 0;\n        *pSpeed = 0;\n        *pDuplex = 0;\n    }\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_port_macForceLink_set\n * Description:\n *      Set port force linking configuration.\n * Input:\n *      port            - port id.\n *      pPortability    - port ability configuration\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number.\n * Note:\n *      This API can set Port/MAC force mode properties.\n */\nrtk_api_ret_t rtk_port_macForceLink_set(rtk_port_t port, rtk_port_mac_ability_t *pPortability)\n{\n    rtk_api_ret_t retVal;\n    rtl8367c_port_ability_t ability;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check Port Valid */\n    RTK_CHK_PORT_IS_UTP(port);\n\n    if(NULL == pPortability)\n        return RT_ERR_NULL_POINTER;\n\n    if (pPortability->forcemode >1|| pPortability->speed > 2 || pPortability->duplex > 1 ||\n       pPortability->link > 1 || pPortability->nway > 1 || pPortability->txpause > 1 || pPortability->rxpause > 1)\n        return RT_ERR_INPUT;\n\n    if ((retVal = rtl8367c_getAsicPortForceLink(rtk_switch_port_L2P_get(port), &ability)) != RT_ERR_OK)\n        return retVal;\n\n    ability.forcemode = pPortability->forcemode;\n    ability.speed     = pPortability->speed;\n    ability.duplex    = pPortability->duplex;\n    ability.link      = pPortability->link;\n    ability.nway      = pPortability->nway;\n    ability.txpause   = pPortability->txpause;\n    ability.rxpause   = pPortability->rxpause;\n\n    if ((retVal = rtl8367c_setAsicPortForceLink(rtk_switch_port_L2P_get(port), &ability)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_port_macForceLink_get\n * Description:\n *      Get port force linking configuration.\n * Input:\n *      port - Port id.\n * Output:\n *      pPortability - port ability configuration\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number.\n *      RT_ERR_INPUT        - Invalid input parameters.\n * Note:\n *      This API can get Port/MAC force mode properties.\n */\nrtk_api_ret_t rtk_port_macForceLink_get(rtk_port_t port, rtk_port_mac_ability_t *pPortability)\n{\n    rtk_api_ret_t retVal;\n    rtl8367c_port_ability_t ability;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check Port Valid */\n    RTK_CHK_PORT_IS_UTP(port);\n\n    if(NULL == pPortability)\n        return RT_ERR_NULL_POINTER;\n\n    if ((retVal = rtl8367c_getAsicPortForceLink(rtk_switch_port_L2P_get(port), &ability)) != RT_ERR_OK)\n        return retVal;\n\n    pPortability->forcemode = ability.forcemode;\n    pPortability->speed     = ability.speed;\n    pPortability->duplex    = ability.duplex;\n    pPortability->link      = ability.link;\n    pPortability->nway      = ability.nway;\n    pPortability->txpause   = ability.txpause;\n    pPortability->rxpause   = ability.rxpause;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_port_macForceLinkExt_set\n * Description:\n *      Set external interface force linking configuration.\n * Input:\n *      port            - external port ID\n *      mode            - external interface mode\n *      pPortability    - port ability configuration\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n * Note:\n *      This API can set external interface force mode properties.\n *      The external interface can be set to:\n *      - MODE_EXT_DISABLE,\n *      - MODE_EXT_RGMII,\n *      - MODE_EXT_MII_MAC,\n *      - MODE_EXT_MII_PHY,\n *      - MODE_EXT_TMII_MAC,\n *      - MODE_EXT_TMII_PHY,\n *      - MODE_EXT_GMII,\n *      - MODE_EXT_RMII_MAC,\n *      - MODE_EXT_RMII_PHY,\n *      - MODE_EXT_SGMII,\n *      - MODE_EXT_HSGMII,\n *      - MODE_EXT_1000X_100FX,\n *      - MODE_EXT_1000X,\n *      - MODE_EXT_100FX,\n */\nrtk_api_ret_t rtk_port_macForceLinkExt_set(rtk_port_t port, rtk_mode_ext_t mode, rtk_port_mac_ability_t *pPortability)\n{\n    rtk_api_ret_t retVal;\n    rtl8367c_port_ability_t ability;\n    rtk_uint32 ext_id;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check Port Valid */\n    RTK_CHK_PORT_IS_EXT(port);\n\n    if(NULL == pPortability)\n        return RT_ERR_NULL_POINTER;\n\n    if (mode >=MODE_EXT_END)\n        return RT_ERR_INPUT;\n\n    if(mode == MODE_EXT_HSGMII)\n    {\n        if (pPortability->forcemode > 1 || pPortability->speed != PORT_SPEED_2500M || pPortability->duplex != PORT_FULL_DUPLEX ||\n           pPortability->link >= PORT_LINKSTATUS_END || pPortability->nway > 1 || pPortability->txpause > 1 || pPortability->rxpause > 1)\n            return RT_ERR_INPUT;\n\n        if(rtk_switch_isHsgPort(port) != RT_ERR_OK)\n            return RT_ERR_PORT_ID;\n    }\n    else\n    {\n        if (pPortability->forcemode > 1 || pPortability->speed > PORT_SPEED_1000M || pPortability->duplex >= PORT_DUPLEX_END ||\n           pPortability->link >= PORT_LINKSTATUS_END || pPortability->nway > 1 || pPortability->txpause > 1 || pPortability->rxpause > 1)\n            return RT_ERR_INPUT;\n    }\n\n    ext_id = port - 15;\n\n    if(mode == MODE_EXT_DISABLE)\n    {\n        memset(&ability, 0x00, sizeof(rtl8367c_port_ability_t));\n        if ((retVal = rtl8367c_setAsicPortForceLinkExt(ext_id, &ability)) != RT_ERR_OK)\n            return retVal;\n\n        if ((retVal = rtl8367c_setAsicPortExtMode(ext_id, mode)) != RT_ERR_OK)\n            return retVal;\n    }\n    else\n    {\n        if ((retVal = rtl8367c_setAsicPortExtMode(ext_id, mode)) != RT_ERR_OK)\n            return retVal;\n\n        if ((retVal = rtl8367c_getAsicPortForceLinkExt(ext_id, &ability)) != RT_ERR_OK)\n            return retVal;\n\n        ability.forcemode = pPortability->forcemode;\n        ability.speed     = (mode == MODE_EXT_HSGMII) ? PORT_SPEED_1000M : pPortability->speed;\n        ability.duplex    = pPortability->duplex;\n        ability.link      = pPortability->link;\n        ability.nway      = pPortability->nway;\n        ability.txpause   = pPortability->txpause;\n        ability.rxpause   = pPortability->rxpause;\n\n        if ((retVal = rtl8367c_setAsicPortForceLinkExt(ext_id, &ability)) != RT_ERR_OK)\n            return retVal;\n    }\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_port_macForceLinkExt_get\n * Description:\n *      Set external interface force linking configuration.\n * Input:\n *      port            - external port ID\n * Output:\n *      pMode           - external interface mode\n *      pPortability    - port ability configuration\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n * Note:\n *      This API can get external interface force mode properties.\n */\nrtk_api_ret_t rtk_port_macForceLinkExt_get(rtk_port_t port, rtk_mode_ext_t *pMode, rtk_port_mac_ability_t *pPortability)\n{\n    rtk_api_ret_t retVal;\n    rtl8367c_port_ability_t ability;\n    rtk_uint32 ext_id;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check Port Valid */\n    RTK_CHK_PORT_IS_EXT(port);\n\n    if(NULL == pMode)\n        return RT_ERR_NULL_POINTER;\n\n    if(NULL == pPortability)\n        return RT_ERR_NULL_POINTER;\n\n    ext_id = port - 15;\n\n    if ((retVal = rtl8367c_getAsicPortExtMode(ext_id, (rtk_uint32 *)pMode)) != RT_ERR_OK)\n        return retVal;\n\n    if ((retVal = rtl8367c_getAsicPortForceLinkExt(ext_id, &ability)) != RT_ERR_OK)\n        return retVal;\n\n    pPortability->forcemode = ability.forcemode;\n    pPortability->speed     = (*pMode == MODE_EXT_HSGMII) ? PORT_SPEED_2500M : ability.speed;\n    pPortability->duplex    = ability.duplex;\n    pPortability->link      = ability.link;\n    pPortability->nway      = ability.nway;\n    pPortability->txpause   = ability.txpause;\n    pPortability->rxpause   = ability.rxpause;\n\n    return RT_ERR_OK;\n\n}\n\n/* Function Name:\n *      rtk_port_macStatus_get\n * Description:\n *      Get port link status.\n * Input:\n *      port - Port id.\n * Output:\n *      pPortstatus - port ability configuration\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number.\n * Note:\n *      This API can get Port/PHY properties.\n */\nrtk_api_ret_t rtk_port_macStatus_get(rtk_port_t port, rtk_port_mac_ability_t *pPortstatus)\n{\n    rtk_api_ret_t retVal;\n    rtl8367c_port_status_t status;\n    rtk_uint32 hsgsel;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check Port Valid */\n    RTK_CHK_PORT_VALID(port);\n\n    if(NULL == pPortstatus)\n        return RT_ERR_NULL_POINTER;\n\n    if ((retVal = rtl8367c_getAsicPortStatus(rtk_switch_port_L2P_get(port), &status)) != RT_ERR_OK)\n        return retVal;\n\n\n    pPortstatus->duplex    = status.duplex;\n    pPortstatus->link      = status.link;\n    pPortstatus->nway      = status.nway;\n    pPortstatus->txpause   = status.txpause;\n    pPortstatus->rxpause   = status.rxpause;\n\n    if( (retVal = rtl8367c_getAsicRegBit(RTL8367C_REG_SDS_MISC, RTL8367C_CFG_MAC8_SEL_HSGMII_OFFSET, &hsgsel)) != RT_ERR_OK)\n            return retVal;\n\n    if( (rtk_switch_isHsgPort(port) == RT_ERR_OK) && (hsgsel == 1) )\n        pPortstatus->speed = PORT_SPEED_2500M;\n    else\n        pPortstatus->speed = status.speed;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_port_macLocalLoopbackEnable_set\n * Description:\n *      Set Port Local Loopback. (Redirect TX to RX.)\n * Input:\n *      port    - Port id.\n *      enable  - Loopback state, 0:disable, 1:enable\n * Output:\n *      None.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number.\n * Note:\n *      This API can enable/disable Local loopback in MAC.\n *      For UTP port, This API will also enable the digital\n *      loopback bit in PHY register for sync of speed between\n *      PHY and MAC. For EXT port, users need to force the\n *      link state by themself.\n */\nrtk_api_ret_t rtk_port_macLocalLoopbackEnable_set(rtk_port_t port, rtk_enable_t enable)\n{\n    rtk_api_ret_t   retVal;\n    rtk_uint32      data;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check Port Valid */\n    RTK_CHK_PORT_VALID(port);\n\n    if(enable >= RTK_ENABLE_END)\n        return RT_ERR_INPUT;\n\n    if ((retVal = rtl8367c_setAsicPortLoopback(rtk_switch_port_L2P_get(port), enable)) != RT_ERR_OK)\n        return retVal;\n\n    if(rtk_switch_isUtpPort(port) == RT_ERR_OK)\n    {\n        if ((retVal = rtl8367c_getAsicPHYReg(rtk_switch_port_L2P_get(port), PHY_CONTROL_REG, &data)) != RT_ERR_OK)\n            return retVal;\n\n        if(enable == ENABLED)\n            data |= (0x0001 << 14);\n        else\n            data &= ~(0x0001 << 14);\n\n        if ((retVal = rtl8367c_setAsicPHYReg(rtk_switch_port_L2P_get(port), PHY_CONTROL_REG, data)) != RT_ERR_OK)\n            return retVal;\n    }\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_port_macLocalLoopbackEnable_get\n * Description:\n *      Get Port Local Loopback. (Redirect TX to RX.)\n * Input:\n *      port    - Port id.\n * Output:\n *      pEnable  - Loopback state, 0:disable, 1:enable\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number.\n * Note:\n *      None.\n */\nrtk_api_ret_t rtk_port_macLocalLoopbackEnable_get(rtk_port_t port, rtk_enable_t *pEnable)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check Port Valid */\n    RTK_CHK_PORT_VALID(port);\n\n    if(NULL == pEnable)\n        return RT_ERR_NULL_POINTER;\n\n    if ((retVal = rtl8367c_getAsicPortLoopback(rtk_switch_port_L2P_get(port), pEnable)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_port_phyReg_set\n * Description:\n *      Set PHY register data of the specific port.\n * Input:\n *      port    - port id.\n *      reg     - Register id\n *      regData - Register data\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - OK\n *      RT_ERR_FAILED           - Failed\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_PORT_ID          - Invalid port number.\n *      RT_ERR_PHY_REG_ID       - Invalid PHY address\n *      RT_ERR_BUSYWAIT_TIMEOUT - PHY access busy\n * Note:\n *      This API can set PHY register data of the specific port.\n */\nrtk_api_ret_t rtk_port_phyReg_set(rtk_port_t port, rtk_port_phy_reg_t reg, rtk_port_phy_data_t regData)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check Port Valid */\n    RTK_CHK_PORT_IS_UTP(port);\n\n    if ((retVal = rtl8367c_setAsicPHYReg(rtk_switch_port_L2P_get(port), reg, regData)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_port_phyReg_get\n * Description:\n *      Get PHY register data of the specific port.\n * Input:\n *      port    - Port id.\n *      reg     - Register id\n * Output:\n *      pData   - Register data\n * Return:\n *      RT_ERR_OK               - OK\n *      RT_ERR_FAILED           - Failed\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_PORT_ID          - Invalid port number.\n *      RT_ERR_PHY_REG_ID       - Invalid PHY address\n *      RT_ERR_BUSYWAIT_TIMEOUT - PHY access busy\n * Note:\n *      This API can get PHY register data of the specific port.\n */\nrtk_api_ret_t rtk_port_phyReg_get(rtk_port_t port, rtk_port_phy_reg_t reg, rtk_port_phy_data_t *pData)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check Port Valid */\n    RTK_CHK_PORT_IS_UTP(port);\n\n    if ((retVal = rtl8367c_getAsicPHYReg(rtk_switch_port_L2P_get(port), reg, pData)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_port_backpressureEnable_set\n * Description:\n *      Set the half duplex backpressure enable status of the specific port.\n * Input:\n *      port    - port id.\n *      enable  - Back pressure status.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number.\n *      RT_ERR_ENABLE       - Invalid enable input.\n * Note:\n *      This API can set the half duplex backpressure enable status of the specific port.\n *      The half duplex backpressure enable status of the port is as following:\n *      - DISABLE(Defer)\n *      - ENABLE (Backpressure)\n */\nrtk_api_ret_t rtk_port_backpressureEnable_set(rtk_port_t port, rtk_enable_t enable)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if (port != RTK_WHOLE_SYSTEM)\n        return RT_ERR_PORT_ID;\n\n    if (enable >= RTK_ENABLE_END)\n        return RT_ERR_INPUT;\n\n    if ((retVal = rtl8367c_setAsicPortJamMode(!enable)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_port_backpressureEnable_get\n * Description:\n *      Get the half duplex backpressure enable status of the specific port.\n * Input:\n *      port - Port id.\n * Output:\n *      pEnable - Back pressure status.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number.\n * Note:\n *      This API can get the half duplex backpressure enable status of the specific port.\n *      The half duplex backpressure enable status of the port is as following:\n *      - DISABLE(Defer)\n *      - ENABLE (Backpressure)\n */\nrtk_api_ret_t rtk_port_backpressureEnable_get(rtk_port_t port, rtk_enable_t *pEnable)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32 regData;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if (port != RTK_WHOLE_SYSTEM)\n        return RT_ERR_PORT_ID;\n\n    if(NULL == pEnable)\n        return RT_ERR_NULL_POINTER;\n\n    if ((retVal = rtl8367c_getAsicPortJamMode(&regData)) != RT_ERR_OK)\n        return retVal;\n\n    *pEnable = !regData;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_port_adminEnable_set\n * Description:\n *      Set port admin configuration of the specific port.\n * Input:\n *      port    - port id.\n *      enable  - Back pressure status.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number.\n *      RT_ERR_ENABLE       - Invalid enable input.\n * Note:\n *      This API can set port admin configuration of the specific port.\n *      The port admin configuration of the port is as following:\n *      - DISABLE\n *      - ENABLE\n */\nrtk_api_ret_t rtk_port_adminEnable_set(rtk_port_t port, rtk_enable_t enable)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32      data;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check Port Valid */\n    RTK_CHK_PORT_IS_UTP(port);\n\n    if (enable >= RTK_ENABLE_END)\n        return RT_ERR_INPUT;\n\n    if ((retVal = rtk_port_phyReg_get(port, PHY_CONTROL_REG, &data)) != RT_ERR_OK)\n        return retVal;\n\n    if (ENABLED == enable)\n    {\n        data &= 0xF7FF;\n        data |= 0x0200;\n    }\n    else if (DISABLED == enable)\n    {\n        data |= 0x0800;\n    }\n\n    if ((retVal = rtk_port_phyReg_set(port, PHY_CONTROL_REG, data)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_port_adminEnable_get\n * Description:\n *      Get port admin configurationof the specific port.\n * Input:\n *      port - Port id.\n * Output:\n *      pEnable - Back pressure status.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number.\n * Note:\n *      This API can get port admin configuration of the specific port.\n *      The port admin configuration of the port is as following:\n *      - DISABLE\n *      - ENABLE\n */\nrtk_api_ret_t rtk_port_adminEnable_get(rtk_port_t port, rtk_enable_t *pEnable)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32      data;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check Port Valid */\n    RTK_CHK_PORT_IS_UTP(port);\n\n    if(NULL == pEnable)\n        return RT_ERR_NULL_POINTER;\n\n    if ((retVal = rtk_port_phyReg_get(port, PHY_CONTROL_REG, &data)) != RT_ERR_OK)\n        return retVal;\n\n    if ( (data & 0x0800) == 0x0800)\n    {\n        *pEnable = DISABLED;\n    }\n    else\n    {\n        *pEnable = ENABLED;\n    }\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_port_isolation_set\n * Description:\n *      Set permitted port isolation portmask\n * Input:\n *      port         - port id.\n *      pPortmask    - Permit port mask\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number.\n *      RT_ERR_PORT_MASK    - Invalid portmask.\n * Note:\n *      This API set the port mask that a port can trasmit packet to of each port\n *      A port can only transmit packet to ports included in permitted portmask\n */\nrtk_api_ret_t rtk_port_isolation_set(rtk_port_t port, rtk_portmask_t *pPortmask)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32 pmask;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check Port Valid */\n    RTK_CHK_PORT_VALID(port);\n\n    if(NULL == pPortmask)\n        return RT_ERR_NULL_POINTER;\n\n    /* check port mask */\n    RTK_CHK_PORTMASK_VALID(pPortmask);\n\n    if ((retVal = rtk_switch_portmask_L2P_get(pPortmask, &pmask)) != RT_ERR_OK)\n        return retVal;\n\n    if ((retVal = rtl8367c_setAsicPortIsolationPermittedPortmask(rtk_switch_port_L2P_get(port), pmask)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_port_isolation_get\n * Description:\n *      Get permitted port isolation portmask\n * Input:\n *      port - Port id.\n * Output:\n *      pPortmask - Permit port mask\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number.\n * Note:\n *      This API get the port mask that a port can trasmit packet to of each port\n *      A port can only transmit packet to ports included in permitted portmask\n */\nrtk_api_ret_t rtk_port_isolation_get(rtk_port_t port, rtk_portmask_t *pPortmask)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32 pmask;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check Port Valid */\n    RTK_CHK_PORT_VALID(port);\n\n    if(NULL == pPortmask)\n        return RT_ERR_NULL_POINTER;\n\n    if ((retVal = rtl8367c_getAsicPortIsolationPermittedPortmask(rtk_switch_port_L2P_get(port), &pmask)) != RT_ERR_OK)\n        return retVal;\n\n    if ((retVal = rtk_switch_portmask_P2L_get(pmask, pPortmask)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_port_rgmiiDelayExt_set\n * Description:\n *      Set RGMII interface delay value for TX and RX.\n * Input:\n *      txDelay - TX delay value, 1 for delay 2ns and 0 for no-delay\n *      rxDelay - RX delay value, 0~7 for delay setup.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n * Note:\n *      This API can set external interface 2 RGMII delay.\n *      In TX delay, there are 2 selection: no-delay and 2ns delay.\n *      In RX dekay, there are 8 steps for delay tunning. 0 for no-delay, and 7 for maximum delay.\n */\nrtk_api_ret_t rtk_port_rgmiiDelayExt_set(rtk_port_t port, rtk_data_t txDelay, rtk_data_t rxDelay)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32 regAddr, regData;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check Port Valid */\n    RTK_CHK_PORT_IS_EXT(port);\n\n    if ((txDelay > 1) || (rxDelay > 7))\n        return RT_ERR_INPUT;\n\n    if(port == EXT_PORT0)\n        regAddr = RTL8367C_REG_EXT1_RGMXF;\n    else if(port == EXT_PORT1)\n        regAddr = RTL8367C_REG_EXT2_RGMXF;\n    else\n        return RT_ERR_INPUT;\n\n    if ((retVal = rtl8367c_getAsicReg(regAddr, &regData)) != RT_ERR_OK)\n        return retVal;\n\n    regData = (regData & 0xFFF0) | ((txDelay << 3) & 0x0008) | (rxDelay & 0x0007);\n\n    if ((retVal = rtl8367c_setAsicReg(regAddr, regData)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_port_rgmiiDelayExt_get\n * Description:\n *      Get RGMII interface delay value for TX and RX.\n * Input:\n *      None\n * Output:\n *      pTxDelay - TX delay value\n *      pRxDelay - RX delay value\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n * Note:\n *      This API can set external interface 2 RGMII delay.\n *      In TX delay, there are 2 selection: no-delay and 2ns delay.\n *      In RX dekay, there are 8 steps for delay tunning. 0 for n0-delay, and 7 for maximum delay.\n */\nrtk_api_ret_t rtk_port_rgmiiDelayExt_get(rtk_port_t port, rtk_data_t *pTxDelay, rtk_data_t *pRxDelay)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32 regAddr, regData;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check Port Valid */\n    RTK_CHK_PORT_IS_EXT(port);\n\n    if( (NULL == pTxDelay) || (NULL == pRxDelay) )\n        return RT_ERR_NULL_POINTER;\n\n    if(port == EXT_PORT0)\n        regAddr = RTL8367C_REG_EXT1_RGMXF;\n    else if(port == EXT_PORT1)\n        regAddr = RTL8367C_REG_EXT2_RGMXF;\n    else\n        return RT_ERR_INPUT;\n\n    if ((retVal = rtl8367c_getAsicReg(regAddr, &regData)) != RT_ERR_OK)\n        return retVal;\n\n    *pTxDelay = (regData & 0x0008) >> 3;\n    *pRxDelay = regData & 0x0007;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_port_phyEnableAll_set\n * Description:\n *      Set all PHY enable status.\n * Input:\n *      enable - PHY Enable State.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_ENABLE       - Invalid enable input.\n * Note:\n *      This API can set all PHY status.\n *      The configuration of all PHY is as following:\n *      - DISABLE\n *      - ENABLE\n */\nrtk_api_ret_t rtk_port_phyEnableAll_set(rtk_enable_t enable)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32 data;\n    rtk_uint32 port;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if (enable >= RTK_ENABLE_END)\n        return RT_ERR_ENABLE;\n\n    if ((retVal = rtl8367c_setAsicPortEnableAll(enable)) != RT_ERR_OK)\n        return retVal;\n\n    RTK_SCAN_ALL_LOG_PORT(port)\n    {\n        if(rtk_switch_isUtpPort(port) == RT_ERR_OK)\n        {\n            if ((retVal = rtk_port_phyReg_get(port, PHY_CONTROL_REG, &data)) != RT_ERR_OK)\n                return retVal;\n\n            if (ENABLED == enable)\n            {\n                data &= 0xF7FF;\n                data |= 0x0200;\n            }\n            else\n            {\n                data |= 0x0800;\n            }\n\n            if ((retVal = rtk_port_phyReg_set(port, PHY_CONTROL_REG, data)) != RT_ERR_OK)\n                return retVal;\n        }\n    }\n\n    return RT_ERR_OK;\n\n}\n\n/* Function Name:\n *      rtk_port_phyEnableAll_get\n * Description:\n *      Get all PHY enable status.\n * Input:\n *      None\n * Output:\n *      pEnable - PHY Enable State.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n * Note:\n *      This API can set all PHY status.\n *      The configuration of all PHY is as following:\n *      - DISABLE\n *      - ENABLE\n */\nrtk_api_ret_t rtk_port_phyEnableAll_get(rtk_enable_t *pEnable)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(NULL == pEnable)\n        return RT_ERR_NULL_POINTER;\n\n    if ((retVal = rtl8367c_getAsicPortEnableAll(pEnable)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_port_efid_set\n * Description:\n *      Set port-based enhanced filtering database\n * Input:\n *      port - Port id.\n *      efid - Specified enhanced filtering database.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n *      RT_ERR_L2_FID - Invalid fid.\n *      RT_ERR_INPUT - Invalid input parameter.\n *      RT_ERR_PORT_ID - Invalid port ID.\n * Note:\n *      The API can set port-based enhanced filtering database.\n */\nrtk_api_ret_t rtk_port_efid_set(rtk_port_t port, rtk_data_t efid)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check Port Valid */\n    RTK_CHK_PORT_VALID(port);\n\n    /* efid must be 0~7 */\n    if (efid > RTK_EFID_MAX)\n        return RT_ERR_INPUT;\n\n    if ((retVal = rtl8367c_setAsicPortIsolationEfid(rtk_switch_port_L2P_get(port), efid))!=RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_port_efid_get\n * Description:\n *      Get port-based enhanced filtering database\n * Input:\n *      port - Port id.\n * Output:\n *      pEfid - Specified enhanced filtering database.\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n *      RT_ERR_INPUT - Invalid input parameters.\n *      RT_ERR_PORT_ID - Invalid port ID.\n * Note:\n *      The API can get port-based enhanced filtering database status.\n */\nrtk_api_ret_t rtk_port_efid_get(rtk_port_t port, rtk_data_t *pEfid)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check Port Valid */\n    RTK_CHK_PORT_VALID(port);\n\n    if(NULL == pEfid)\n        return RT_ERR_NULL_POINTER;\n\n    if ((retVal = rtl8367c_getAsicPortIsolationEfid(rtk_switch_port_L2P_get(port), pEfid))!=RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_port_phyComboPortMedia_set\n * Description:\n *      Set Combo port media type\n * Input:\n *      port    - Port id.\n *      media   - Media (COPPER or FIBER)\n * Output:\n *      None.\n * Return:\n *      RT_ERR_OK               - OK\n *      RT_ERR_FAILED           - Failed\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_INPUT            - Invalid input parameters.\n *      RT_ERR_PORT_ID          - Invalid port ID.\n * Note:\n *      The API can Set Combo port media type.\n */\nrtk_api_ret_t rtk_port_phyComboPortMedia_set(rtk_port_t port, rtk_port_media_t media)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32 regData;\n    rtk_uint32 idx;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check Port Valid */\n    RTK_CHK_PORT_IS_UTP(port);\n\n    /* Check Combo Port ID */\n    RTK_CHK_PORT_IS_COMBO(port);\n\n    if (media >= PORT_MEDIA_END)\n        return RT_ERR_INPUT;\n\n    if((retVal = rtl8367c_setAsicReg(0x13C2, 0x0249)) != RT_ERR_OK)\n        return retVal;\n\n    if((retVal = rtl8367c_getAsicReg(0x1300, &regData)) != RT_ERR_OK)\n        return retVal;\n\n    if((retVal = rtl8367c_setAsicReg(0x13C2, 0x0000)) != RT_ERR_OK)\n        return retVal;\n\n    if(regData != 0x6367)\n        return RT_ERR_CHIP_NOT_SUPPORTED;\n\n    if(media == PORT_MEDIA_FIBER)\n    {\n        /* software init */\n        if ((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_CHIP_RESET, RTL8367C_DW8051_RST_OFFSET, 1)) != RT_ERR_OK)\n            return retVal;\n\n        if ((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_MISCELLANEOUS_CONFIGURE0, RTL8367C_DW8051_EN_OFFSET, 1)) != RT_ERR_OK)\n            return retVal;\n\n        if ((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_DW8051_RDY, RTL8367C_ACS_IROM_ENABLE_OFFSET, 1)) != RT_ERR_OK)\n            return retVal;\n\n        if ((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_DW8051_RDY, RTL8367C_IROM_MSB_OFFSET, 0)) != RT_ERR_OK)\n            return retVal;\n\n        for(idx = 0; idx < FIBER_INIT_SIZE; idx++)\n        {\n            if ((retVal = rtl8367c_setAsicReg(0xE000 + idx, (rtk_uint32)Fiber[idx])) != RT_ERR_OK)\n                return retVal;\n        }\n\n        if ((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_DW8051_RDY, RTL8367C_IROM_MSB_OFFSET, 0)) != RT_ERR_OK)\n            return retVal;\n\n        if ((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_DW8051_RDY, RTL8367C_ACS_IROM_ENABLE_OFFSET, 0)) != RT_ERR_OK)\n            return retVal;\n\n        if ((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_CHIP_RESET, RTL8367C_DW8051_RST_OFFSET, 0)) != RT_ERR_OK)\n            return retVal;\n    }\n    else\n    {\n        if ((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_UTP_FIB_DET, RTL8367C_UTP_FIRST_OFFSET, 1))!=RT_ERR_OK)\n            return retVal;\n\n        if ((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_DW8051_RDY, RTL8367C_DW8051_READY_OFFSET, 0)) != RT_ERR_OK)\n            return retVal;\n    }\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_port_phyComboPortMedia_get\n * Description:\n *      Get Combo port media type\n * Input:\n *      port    - Port id.\n * Output:\n *      pMedia  - Media (COPPER or FIBER)\n * Return:\n *      RT_ERR_OK               - OK\n *      RT_ERR_FAILED           - Failed\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_INPUT            - Invalid input parameters.\n *      RT_ERR_PORT_ID          - Invalid port ID.\n * Note:\n *      The API can Set Combo port media type.\n */\nrtk_api_ret_t rtk_port_phyComboPortMedia_get(rtk_port_t port, rtk_port_media_t *pMedia)\n{\n    rtk_api_ret_t   retVal;\n    rtk_uint32      regData;\n    rtk_uint32      data;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check Port Valid */\n    RTK_CHK_PORT_IS_UTP(port);\n\n    /* Check Combo Port ID */\n    RTK_CHK_PORT_IS_COMBO(port);\n\n    if((retVal = rtl8367c_setAsicReg(0x13C2, 0x0249)) != RT_ERR_OK)\n        return retVal;\n\n    if((retVal = rtl8367c_getAsicReg(0x1300, &regData)) != RT_ERR_OK)\n        return retVal;\n\n    if((retVal = rtl8367c_setAsicReg(0x13C2, 0x0000)) != RT_ERR_OK)\n        return retVal;\n\n    if(regData != 0x6367)\n    {\n        *pMedia = PORT_MEDIA_COPPER;\n    }\n    else\n    {\n        if ((retVal = rtl8367c_getAsicRegBit(RTL8367C_REG_UTP_FIB_DET, RTL8367C_UTP_FIRST_OFFSET, &data))!=RT_ERR_OK)\n                return retVal;\n\n        if(data == 1)\n            *pMedia = PORT_MEDIA_COPPER;\n        else\n            *pMedia = PORT_MEDIA_FIBER;\n    }\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_port_rtctEnable_set\n * Description:\n *      Enable RTCT test\n * Input:\n *      pPortmask    - Port mask of RTCT enabled port\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - OK\n *      RT_ERR_FAILED           - Failed\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_PORT_MASK        - Invalid port mask.\n * Note:\n *      The API can enable RTCT Test\n */\nrtk_api_ret_t rtk_port_rtctEnable_set(rtk_portmask_t *pPortmask)\n{\n    rtk_api_ret_t   retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check Port Mask Valid */\n    RTK_CHK_PORTMASK_VALID_ONLY_UTP(pPortmask);\n\n    if ((retVal = rtl8367c_setAsicPortRTCTEnable(pPortmask->bits[0]))!=RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_port_rtctDisable_set\n * Description:\n *      Disable RTCT test\n * Input:\n *      pPortmask    - Port mask of RTCT disabled port\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - OK\n *      RT_ERR_FAILED           - Failed\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_PORT_MASK        - Invalid port mask.\n * Note:\n *      The API can disable RTCT Test\n */\nrtk_api_ret_t rtk_port_rtctDisable_set(rtk_portmask_t *pPortmask)\n{\n    rtk_api_ret_t   retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check Port Mask Valid */\n    RTK_CHK_PORTMASK_VALID_ONLY_UTP(pPortmask);\n\n    if ((retVal = rtl8367c_setAsicPortRTCTDisable(pPortmask->bits[0]))!=RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n\n/* Function Name:\n *      rtk_port_rtctResult_get\n * Description:\n *      Get the result of RTCT test\n * Input:\n *      port        - Port ID\n * Output:\n *      pRtctResult - The result of RTCT result\n * Return:\n *      RT_ERR_OK                   - OK\n *      RT_ERR_FAILED               - Failed\n *      RT_ERR_SMI                  - SMI access error\n *      RT_ERR_PORT_ID              - Invalid port ID.\n *      RT_ERR_PHY_RTCT_NOT_FINISH  - Testing does not finish.\n * Note:\n *      The API can get RTCT test result.\n *      RTCT test may takes 4.8 seconds to finish its test at most.\n *      Thus, if this API return RT_ERR_PHY_RTCT_NOT_FINISH or\n *      other error code, the result can not be referenced and\n *      user should call this API again until this API returns\n *      a RT_ERR_OK.\n *      The result is stored at pRtctResult->ge_result\n *      pRtctResult->linkType is unused.\n *      The unit of channel length is 2.5cm. Ex. 300 means 300 * 2.5 = 750cm = 7.5M\n */\nrtk_api_ret_t rtk_port_rtctResult_get(rtk_port_t port, rtk_rtctResult_t *pRtctResult)\n{\n    rtk_api_ret_t               retVal;\n    rtl8367c_port_rtct_result_t result;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check Port Valid */\n    RTK_CHK_PORT_IS_UTP(port);\n\n    memset(pRtctResult, 0x00, sizeof(rtk_rtctResult_t));\n    if ((retVal = rtl8367c_getAsicPortRTCTResult(port, &result))!=RT_ERR_OK)\n        return retVal;\n\n    pRtctResult->result.ge_result.channelALen = result.channelALen;\n    pRtctResult->result.ge_result.channelBLen = result.channelBLen;\n    pRtctResult->result.ge_result.channelCLen = result.channelCLen;\n    pRtctResult->result.ge_result.channelDLen = result.channelDLen;\n\n    pRtctResult->result.ge_result.channelALinedriver = result.channelALinedriver;\n    pRtctResult->result.ge_result.channelBLinedriver = result.channelBLinedriver;\n    pRtctResult->result.ge_result.channelCLinedriver = result.channelCLinedriver;\n    pRtctResult->result.ge_result.channelDLinedriver = result.channelDLinedriver;\n\n    pRtctResult->result.ge_result.channelAMismatch = result.channelAMismatch;\n    pRtctResult->result.ge_result.channelBMismatch = result.channelBMismatch;\n    pRtctResult->result.ge_result.channelCMismatch = result.channelCMismatch;\n    pRtctResult->result.ge_result.channelDMismatch = result.channelDMismatch;\n\n    pRtctResult->result.ge_result.channelAOpen = result.channelAOpen;\n    pRtctResult->result.ge_result.channelBOpen = result.channelBOpen;\n    pRtctResult->result.ge_result.channelCOpen = result.channelCOpen;\n    pRtctResult->result.ge_result.channelDOpen = result.channelDOpen;\n\n    pRtctResult->result.ge_result.channelAShort = result.channelAShort;\n    pRtctResult->result.ge_result.channelBShort = result.channelBShort;\n    pRtctResult->result.ge_result.channelCShort = result.channelCShort;\n    pRtctResult->result.ge_result.channelDShort = result.channelDShort;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_port_sds_reset\n * Description:\n *      Reset Serdes\n * Input:\n *      port        - Port ID\n * Output:\n *      None.\n * Return:\n *      RT_ERR_OK                   - OK\n *      RT_ERR_FAILED               - Failed\n *      RT_ERR_SMI                  - SMI access error\n *      RT_ERR_PORT_ID              - Invalid port ID.\n * Note:\n *      The API can reset Serdes\n */\nrtk_api_ret_t rtk_port_sds_reset(rtk_port_t port)\n{\n    rtk_uint32 ext_id;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check Port Valid */\n    if(rtk_switch_isSgmiiPort(port) != RT_ERR_OK)\n        return RT_ERR_PORT_ID;\n\n    ext_id = port - 15;\n    return rtl8367c_sdsReset(ext_id);\n}\n\n/* Function Name:\n *      rtk_port_sgmiiLinkStatus_get\n * Description:\n *      Get SGMII status\n * Input:\n *      port        - Port ID\n * Output:\n *      pSignalDetect   - Signal detect\n *      pSync           - Sync\n *      pLink           - Link\n * Return:\n *      RT_ERR_OK                   - OK\n *      RT_ERR_FAILED               - Failed\n *      RT_ERR_SMI                  - SMI access error\n *      RT_ERR_PORT_ID              - Invalid port ID.\n * Note:\n *      The API can reset Serdes\n */\nrtk_api_ret_t rtk_port_sgmiiLinkStatus_get(rtk_port_t port, rtk_data_t *pSignalDetect, rtk_data_t *pSync, rtk_port_linkStatus_t *pLink)\n{\n    rtk_uint32 ext_id;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check Port Valid */\n    if(rtk_switch_isSgmiiPort(port) != RT_ERR_OK)\n        return RT_ERR_PORT_ID;\n\n    if(NULL == pSignalDetect)\n        return RT_ERR_NULL_POINTER;\n\n    if(NULL == pSync)\n        return RT_ERR_NULL_POINTER;\n\n    if(NULL == pLink)\n        return RT_ERR_NULL_POINTER;\n\n    ext_id = port - 15;\n    return rtl8367c_getSdsLinkStatus(ext_id, (rtk_uint32 *)pSignalDetect, (rtk_uint32 *)pSync, (rtk_uint32 *)pLink);\n}\n\n/* Function Name:\n *      rtk_port_sgmiiNway_set\n * Description:\n *      Configure SGMII/HSGMII port Nway state\n * Input:\n *      port        - Port ID\n *      state       - Nway state\n * Output:\n *      None.\n * Return:\n *      RT_ERR_OK                   - OK\n *      RT_ERR_FAILED               - Failed\n *      RT_ERR_SMI                  - SMI access error\n *      RT_ERR_PORT_ID              - Invalid port ID.\n * Note:\n *      The API configure SGMII/HSGMII port Nway state\n */\nrtk_api_ret_t rtk_port_sgmiiNway_set(rtk_port_t port, rtk_enable_t state)\n{\n    rtk_uint32 ext_id;\n\n     /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check Port Valid */\n    if(rtk_switch_isSgmiiPort(port) != RT_ERR_OK)\n        return RT_ERR_PORT_ID;\n\n    if(state >= RTK_ENABLE_END)\n        return RT_ERR_INPUT;\n\n    ext_id = port - 15;\n    return rtl8367c_setSgmiiNway(ext_id, (rtk_uint32)state);\n}\n\n/* Function Name:\n *      rtk_port_sgmiiNway_get\n * Description:\n *      Get SGMII/HSGMII port Nway state\n * Input:\n *      port        - Port ID\n * Output:\n *      pState      - Nway state\n * Return:\n *      RT_ERR_OK                   - OK\n *      RT_ERR_FAILED               - Failed\n *      RT_ERR_SMI                  - SMI access error\n *      RT_ERR_PORT_ID              - Invalid port ID.\n * Note:\n *      The API can get SGMII/HSGMII port Nway state\n */\nrtk_api_ret_t rtk_port_sgmiiNway_get(rtk_port_t port, rtk_enable_t *pState)\n{\n    rtk_uint32 ext_id;\n\n     /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check Port Valid */\n    if(rtk_switch_isSgmiiPort(port) != RT_ERR_OK)\n        return RT_ERR_PORT_ID;\n\n    if(NULL == pState)\n        return RT_ERR_NULL_POINTER;\n\n    ext_id = port - 15;\n    return rtl8367c_getSgmiiNway(ext_id, (rtk_uint32 *)pState);\n}\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/ptp.c",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * $Revision: 39583 $\n * $Date: 2013-05-20 16:59:23 +0800 (星期一, 20 五月 2013) $\n *\n * Purpose : RTK switch high-level API for RTL8367/RTL8367C\n * Feature : Here is a list of all functions and variables in time module.\n *\n */\n\n#include <rtk_switch.h>\n#include <rtk_error.h>\n#include <ptp.h>\n#include <string.h>\n\n#include <rtl8367c_asicdrv.h>\n#include <rtl8367c_asicdrv_eav.h>\n\n/* Function Name:\n *      rtk_ptp_init\n * Description:\n *      PTP function initialization.\n * Input:\n *      None\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n * Note:\n *      This API is used to initialize PTP status.\n */\nrtk_api_ret_t rtk_ptp_init(void)\n{\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_ptp_mac_set\n * Description:\n *      Configure PTP mac address.\n * Input:\n *      mac - mac address to parser PTP packets.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameter.\n * Note:\n *      None\n */\nrtk_api_ret_t rtk_ptp_mac_set(rtk_mac_t mac)\n{\n    rtk_api_ret_t retVal;\n    ether_addr_t sw_mac;\n\n    memcpy(sw_mac.octet, mac.octet, ETHER_ADDR_LEN);\n\n    if((retVal=rtl8367c_setAsicEavMacAddress(sw_mac))!=RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_ptp_mac_get\n * Description:\n *      Get PTP mac address.\n * Input:\n *      None\n * Output:\n *      pMac - mac address to parser PTP packets.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameter.\n * Note:\n *      None\n */\nrtk_api_ret_t rtk_ptp_mac_get(rtk_mac_t *pMac)\n{\n    rtk_api_ret_t retVal;\n    ether_addr_t sw_mac;\n\n    if((retVal=rtl8367c_getAsicEavMacAddress(&sw_mac))!=RT_ERR_OK)\n        return retVal;\n\n    memcpy(pMac->octet, sw_mac.octet, ETHER_ADDR_LEN);\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_ptp_tpid_set\n * Description:\n *      Configure PTP accepted outer & inner tag TPID.\n * Input:\n *      outerId - Ether type of S-tag frame parsing in PTP ports.\n *      innerId - Ether type of C-tag frame parsing in PTP ports.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameter.\n * Note:\n *      None\n */\nrtk_api_ret_t rtk_ptp_tpid_set(rtk_ptp_tpid_t outerId, rtk_ptp_tpid_t innerId)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if ((outerId>RTK_MAX_NUM_OF_TPID) ||(innerId>RTK_MAX_NUM_OF_TPID))\n        return RT_ERR_INPUT;\n\n    if ((retVal = rtl8367c_setAsicEavTpid(outerId, innerId)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_ptp_tpid_get\n * Description:\n *      Get PTP accepted outer & inner tag TPID.\n * Input:\n *      None\n * Output:\n *      pOuterId - Ether type of S-tag frame parsing in PTP ports.\n *      pInnerId - Ether type of C-tag frame parsing in PTP ports.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n * Note:\n *      None\n */\nrtk_api_ret_t rtk_ptp_tpid_get(rtk_ptp_tpid_t *pOuterId, rtk_ptp_tpid_t *pInnerId)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if ((retVal = rtl8367c_getAsicEavTpid(pOuterId, pInnerId)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_ptp_refTime_set\n * Description:\n *      Set the reference time of the specified device.\n * Input:\n *      timeStamp - reference timestamp value\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n *      RT_ERR_INPUT    - invalid input parameter\n * Applicable:\n *      8390, 8380\n * Note:\n *      None\n */\nrtk_api_ret_t rtk_ptp_refTime_set(rtk_ptp_timeStamp_t timeStamp)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if (timeStamp.nsec > RTK_MAX_NUM_OF_NANO_SECOND)\n        return RT_ERR_INPUT;\n\n    if ((retVal = rtl8367c_setAsicEavSysTime(timeStamp.sec, timeStamp.nsec))!=RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_ptp_refTime_get\n * Description:\n *      Get the reference time of the specified device.\n * Input:\n * Output:\n *      pTimeStamp - pointer buffer of the reference time\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n *      RT_ERR_UNIT_ID      - invalid unit id\n *      RT_ERR_NOT_INIT     - The module is not initial\n *      RT_ERR_NULL_POINTER - input parameter may be null pointer\n * Applicable:\n *      8390, 8380\n * Note:\n *      None\n */\nrtk_api_ret_t rtk_ptp_refTime_get(rtk_ptp_timeStamp_t *pTimeStamp)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if ((retVal = rtl8367c_getAsicEavSysTime(&pTimeStamp->sec, &pTimeStamp->nsec))!=RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_ptp_refTimeAdjust_set\n * Description:\n *      Adjust the reference time.\n * Input:\n *      unit      - unit id\n *      sign      - significant\n *      timeStamp - reference timestamp value\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n *      RT_ERR_UNIT_ID  - invalid unit id\n *      RT_ERR_NOT_INIT - The module is not initial\n *      RT_ERR_INPUT    - invalid input parameter\n * Note:\n *      sign=0 for positive adjustment, sign=1 for negative adjustment.\n */\nrtk_api_ret_t rtk_ptp_refTimeAdjust_set(rtk_ptp_sys_adjust_t sign, rtk_ptp_timeStamp_t timeStamp)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if (timeStamp.nsec > RTK_MAX_NUM_OF_NANO_SECOND)\n        return RT_ERR_INPUT;\n\n    if ((retVal = rtl8367c_setAsicEavSysTimeAdjust(sign, timeStamp.sec, timeStamp.nsec))!=RT_ERR_OK)\n        return retVal;\n\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_ptp_refTimeEnable_set\n * Description:\n *      Set the enable state of reference time of the specified device.\n * Input:\n *      enable - status\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n *      RT_ERR_INPUT    - invalid input parameter\n * Note:\n *      None\n */\nrtk_api_ret_t rtk_ptp_refTimeEnable_set(rtk_enable_t enable)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if (enable >= RTK_ENABLE_END)\n        return RT_ERR_ENABLE;\n\n    if ((retVal = rtl8367c_setAsicEavSysTimeCtrl(enable))!=RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_ptp_refTimeEnable_get\n * Description:\n *      Get the enable state of reference time of the specified device.\n * Input:\n * Output:\n *      pEnable - status\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n *      RT_ERR_UNIT_ID      - invalid unit id\n *      RT_ERR_NOT_INIT     - The module is not initial\n *      RT_ERR_NULL_POINTER - input parameter may be null pointer\n * Applicable:\n *      8390, 8380\n * Note:\n *      None\n */\nrtk_api_ret_t rtk_ptp_refTimeEnable_get(rtk_enable_t *pEnable)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if ((retVal = rtl8367c_getAsicEavSysTimeCtrl(pEnable))!=RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_ptp_portEnable_set\n * Description:\n *      Set PTP status of the specified port.\n * Input:\n *      port   - port id\n *      enable - status\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n *      RT_ERR_PORT     - invalid port id\n *      RT_ERR_INPUT    - invalid input parameter\n * Note:\n *      None\n */\nrtk_api_ret_t rtk_ptp_portEnable_set(rtk_port_t port, rtk_enable_t enable)\n{\n    rtk_api_ret_t   retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check port is PTP port */\n    RTK_CHK_PORT_IS_PTP(port);\n\n    if (enable>=RTK_ENABLE_END)\n        return RT_ERR_INPUT;\n\n    if ((retVal = rtl8367c_setAsicEavPortEnable(rtk_switch_port_L2P_get(port), enable)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_ptp_portEnable_get\n * Description:\n *      Get PTP status of the specified port.\n * Input:\n *      port    - port id\n * Output:\n *      pEnable - status\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n *      RT_ERR_PORT         - invalid port id\n *      RT_ERR_NULL_POINTER - input parameter may be null pointer\n * Note:\n *      None\n */\nrtk_api_ret_t rtk_ptp_portEnable_get(rtk_port_t port, rtk_enable_t *pEnable)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check port is PTP port */\n    RTK_CHK_PORT_IS_PTP(port);\n\n    if ((retVal = rtl8367c_getAsicEavPortEnable(rtk_switch_port_L2P_get(port), pEnable)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n\n/* Function Name:\n *      rtk_ptp_portTimestamp_get\n * Description:\n *      Get PTP timstamp according to the PTP identifier on the dedicated port from the specified device.\n * Input:\n *      unit       - unit id\n *      port       - port id\n *      type       - PTP message type\n * Output:\n *      pInfo      - pointer buffer of sequence ID and timestamp\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n *      RT_ERR_PORT_ID      - invalid port id\n *      RT_ERR_INPUT        - invalid input parameter\n *      RT_ERR_NULL_POINTER - input parameter may be null pointer\n * Applicable:\n *      8390, 8380\n * Note:\n *      None\n */\nrtk_api_ret_t rtk_ptp_portTimestamp_get( rtk_port_t port, rtk_ptp_msgType_t type, rtk_ptp_info_t *pInfo)\n{\n    rtk_api_ret_t retVal;\n    rtl8367c_ptp_time_stamp_t time;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check port is PTP port */\n    RTK_CHK_PORT_IS_PTP(port);\n\n    if ((retVal = rtl8367c_getAsicEavPortTimeStamp(rtk_switch_port_L2P_get(port), type, &time)) != RT_ERR_OK)\n        return retVal;\n\n    pInfo->sequenceId = time.sequence_id;\n    pInfo->timeStamp.sec = time.second;\n    pInfo->timeStamp.nsec = time.nano_second;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_ptp_intControl_set\n * Description:\n *      Set PTP interrupt trigger status configuration.\n * Input:\n *      type - Interrupt type.\n *      enable - Interrupt status.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n *      RT_ERR_ENABLE       - Invalid enable input.\n * Note:\n *      The API can set PTP interrupt status configuration.\n *      The interrupt trigger status is shown in the following:\n *          PTP_INT_TYPE_TX_SYNC = 0,\n *          PTP_INT_TYPE_TX_DELAY_REQ,\n *          PTP_INT_TYPE_TX_PDELAY_REQ,\n *          PTP_INT_TYPE_TX_PDELAY_RESP,\n *          PTP_INT_TYPE_RX_SYNC,\n *          PTP_INT_TYPE_RX_DELAY_REQ,\n *          PTP_INT_TYPE_RX_PDELAY_REQ,\n *          PTP_INT_TYPE_RX_PDELAY_RESP,\n *          PTP_INT_TYPE_ALL,\n */\nrtk_api_ret_t rtk_ptp_intControl_set(rtk_ptp_intType_t type, rtk_enable_t enable)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32 mask;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if (type>=PTP_INT_TYPE_END)\n        return RT_ERR_INPUT;\n\n    if (PTP_INT_TYPE_ALL!=type)\n    {\n        if ((retVal = rtl8367c_getAsicEavInterruptMask(&mask)) != RT_ERR_OK)\n            return retVal;\n\n        if (ENABLED == enable)\n            mask = mask | (1<<type);\n        else if (DISABLED == enable)\n            mask = mask & ~(1<<type);\n        else\n            return RT_ERR_INPUT;\n\n        if ((retVal = rtl8367c_setAsicEavInterruptMask(mask)) != RT_ERR_OK)\n            return retVal;\n    }\n    else\n    {\n        if (ENABLED == enable)\n            mask = RTK_PTP_INTR_MASK;\n        else if (DISABLED == enable)\n            mask = 0;\n        else\n            return RT_ERR_INPUT;\n\n        if ((retVal = rtl8367c_setAsicEavInterruptMask(mask)) != RT_ERR_OK)\n            return retVal;\n    }\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_ptp_intControl_get\n * Description:\n *      Get PTP interrupt trigger status configuration.\n * Input:\n *      type - Interrupt type.\n * Output:\n *      pEnable - Interrupt status.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n * Note:\n *      The API can get interrupt status configuration.\n *      The interrupt trigger status is shown in the following:\n *          PTP_INT_TYPE_TX_SYNC = 0,\n *          PTP_INT_TYPE_TX_DELAY_REQ,\n *          PTP_INT_TYPE_TX_PDELAY_REQ,\n *          PTP_INT_TYPE_TX_PDELAY_RESP,\n *          PTP_INT_TYPE_RX_SYNC,\n *          PTP_INT_TYPE_RX_DELAY_REQ,\n *          PTP_INT_TYPE_RX_PDELAY_REQ,\n *          PTP_INT_TYPE_RX_PDELAY_RESP,\n */\nrtk_api_ret_t rtk_ptp_intControl_get(rtk_ptp_intType_t type, rtk_enable_t *pEnable)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32 mask;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if (type>=PTP_INT_TYPE_ALL)\n        return RT_ERR_INPUT;\n\n    if ((retVal = rtl8367c_getAsicEavInterruptMask(&mask)) != RT_ERR_OK)\n        return retVal;\n\n    if (0 == (mask&(1<<type)))\n        *pEnable=DISABLED;\n    else\n        *pEnable=ENABLED;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_ptp_intStatus_get\n * Description:\n *      Get PTP port interrupt trigger status.\n * Input:\n *      port           - physical port\n * Output:\n *      pStatusMask - Interrupt status bit mask.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n * Note:\n *      The API can get interrupt trigger status when interrupt happened.\n *      The interrupt trigger status is shown in the following:\n *      - PORT 0  INT    (value[0] (Bit0))\n *      - PORT 1  INT    (value[0] (Bit1))\n *      - PORT 2  INT    (value[0] (Bit2))\n *      - PORT 3  INT    (value[0] (Bit3))\n *      - PORT 4  INT   (value[0] (Bit4))\n\n *\n */\nrtk_api_ret_t rtk_ptp_intStatus_get(rtk_ptp_intStatus_t *pStatusMask)\n{\n    rtk_api_ret_t   retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(NULL == pStatusMask)\n        return RT_ERR_NULL_POINTER;\n\n    if ((retVal = rtl8367c_getAsicEavInterruptStatus(pStatusMask)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n\n\n/* Function Name:\n *      rtk_ptp_portIntStatus_set\n * Description:\n *      Set PTP port interrupt trigger status to clean.\n * Input:\n *      port           - physical port\n *      statusMask - Interrupt status bit mask.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n *      RT_ERR_INPUT - Invalid input parameters.\n * Note:\n *      The API can clean interrupt trigger status when interrupt happened.\n *      The interrupt trigger status is shown in the following:\n *      - PTP_INT_TYPE_TX_SYNC              (value[0] (Bit0))\n *      - PTP_INT_TYPE_TX_DELAY_REQ      (value[0] (Bit1))\n *      - PTP_INT_TYPE_TX_PDELAY_REQ    (value[0] (Bit2))\n *      - PTP_INT_TYPE_TX_PDELAY_RESP   (value[0] (Bit3))\n *      - PTP_INT_TYPE_RX_SYNC              (value[0] (Bit4))\n *      - PTP_INT_TYPE_RX_DELAY_REQ      (value[0] (Bit5))\n *      - PTP_INT_TYPE_RX_PDELAY_REQ    (value[0] (Bit6))\n *      - PTP_INT_TYPE_RX_PDELAY_RESP   (value[0] (Bit7))\n *      The status will be cleared after execute this API.\n */\nrtk_api_ret_t rtk_ptp_portIntStatus_set(rtk_port_t port, rtk_ptp_intStatus_t statusMask)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check port is PTP port */\n    RTK_CHK_PORT_IS_PTP(port);\n\n    if ((retVal = rtl8367c_setAsicEavPortInterruptStatus(rtk_switch_port_L2P_get(port), statusMask))!=RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_ptp_portIntStatus_get\n * Description:\n *      Get PTP port interrupt trigger status.\n * Input:\n *      port           - physical port\n * Output:\n *      pStatusMask - Interrupt status bit mask.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n * Note:\n *      The API can get interrupt trigger status when interrupt happened.\n *      The interrupt trigger status is shown in the following:\n *      - PTP_INT_TYPE_TX_SYNC              (value[0] (Bit0))\n *      - PTP_INT_TYPE_TX_DELAY_REQ      (value[0] (Bit1))\n *      - PTP_INT_TYPE_TX_PDELAY_REQ    (value[0] (Bit2))\n *      - PTP_INT_TYPE_TX_PDELAY_RESP   (value[0] (Bit3))\n *      - PTP_INT_TYPE_RX_SYNC              (value[0] (Bit4))\n *      - PTP_INT_TYPE_RX_DELAY_REQ      (value[0] (Bit5))\n *      - PTP_INT_TYPE_RX_PDELAY_REQ    (value[0] (Bit6))\n *      - PTP_INT_TYPE_RX_PDELAY_RESP   (value[0] (Bit7))\n *\n */\nrtk_api_ret_t rtk_ptp_portIntStatus_get(rtk_port_t port, rtk_ptp_intStatus_t *pStatusMask)\n{\n    rtk_api_ret_t   retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check port is PTP port */\n    RTK_CHK_PORT_IS_PTP(port);\n\n    if(NULL == pStatusMask)\n        return RT_ERR_NULL_POINTER;\n\n    if ((retVal = rtl8367c_getAsicEavPortInterruptStatus(rtk_switch_port_L2P_get(port), pStatusMask)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_ptp_portPtpTrap_set\n * Description:\n *      Set PTP packet trap of the specified port.\n * Input:\n *      port   - port id\n *      enable - status\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n *      RT_ERR_PORT     - invalid port id\n *      RT_ERR_INPUT    - invalid input parameter\n * Note:\n *      None\n */\nrtk_api_ret_t rtk_ptp_portTrap_set(rtk_port_t port, rtk_enable_t enable)\n{\n    rtk_api_ret_t   retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check Port Valid */\n    RTK_CHK_PORT_VALID(port);\n\n    if (enable>=RTK_ENABLE_END)\n        return RT_ERR_INPUT;\n\n    if ((retVal = rtl8367c_setAsicEavTrap(rtk_switch_port_L2P_get(port), enable)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_ptp_portPtpEnable_get\n * Description:\n *      Get PTP packet trap of the specified port.\n * Input:\n *      port    - port id\n * Output:\n *      pEnable - status\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n *      RT_ERR_PORT         - invalid port id\n *      RT_ERR_NULL_POINTER - input parameter may be null pointer\n * Note:\n *      None\n */\nrtk_api_ret_t rtk_ptp_portTrap_get(rtk_port_t port, rtk_enable_t *pEnable)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check Port Valid */\n    RTK_CHK_PORT_VALID(port);\n\n    if ((retVal = rtl8367c_getAsicEavTrap(rtk_switch_port_L2P_get(port), pEnable)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n\n\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/qos.c",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * $Revision: 76306 $\n * $Date: 2017-03-08 15:13:58 +0800 (週三, 08 三月 2017) $\n *\n * Purpose : RTK switch high-level API for RTL8367/RTL8367C\n * Feature : Here is a list of all functions and variables in QoS module.\n *\n */\n\n#include <rtk_switch.h>\n#include <rtk_error.h>\n#include <qos.h>\n#include <string.h>\n\n#include <rtl8367c_asicdrv.h>\n#include <rtl8367c_asicdrv_qos.h>\n#include <rtl8367c_asicdrv_fc.h>\n#include <rtl8367c_asicdrv_scheduling.h>\n\n/* Function Name:\n *      rtk_qos_init\n * Description:\n *      Configure Qos default settings with queue number assigment to each port.\n * Input:\n *      queueNum - Queue number of each port.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_QUEUE_NUM    - Invalid queue number.\n *      RT_ERR_INPUT        - Invalid input parameters.\n * Note:\n *      This API will initialize related Qos setting with queue number assigment.\n *      The queue number is from 1 to 8.\n */\nrtk_api_ret_t rtk_qos_init(rtk_queue_num_t queueNum)\n{\n    CONST_T rtk_uint16 g_prioritytToQid[8][8]= {\n            {0, 0,0,0,0,0,0,0},\n            {0, 0,0,0,7,7,7,7},\n            {0, 0,0,0,1,1,7,7},\n            {0, 0,1,1,2,2,7,7},\n            {0, 0,1,1,2,3,7,7},\n            {0, 0,1,2,3,4,7,7},\n            {0, 0,1,2,3,4,5,7},\n            {0,1,2,3,4,5,6,7}\n    };\n\n    CONST_T rtk_uint32 g_priorityDecision[8] = {0x01, 0x80,0x04,0x02,0x20,0x40,0x10,0x08};\n    CONST_T rtk_uint32 g_prioritytRemap[8] = {0,1,2,3,4,5,6,7};\n\n    rtk_api_ret_t retVal;\n    rtk_uint32 qmapidx;\n    rtk_uint32 priority;\n    rtk_uint32 priDec;\n    rtk_uint32 port;\n    rtk_uint32 dscp;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if (queueNum <= 0 || queueNum > RTK_MAX_NUM_OF_QUEUE)\n        return RT_ERR_QUEUE_NUM;\n\n    /*Set Output Queue Number*/\n    if (RTK_MAX_NUM_OF_QUEUE == queueNum)\n        qmapidx = 0;\n    else\n        qmapidx = queueNum;\n\n    RTK_SCAN_ALL_PHY_PORTMASK(port)\n    {\n        if ((retVal = rtl8367c_setAsicOutputQueueMappingIndex(port, qmapidx)) != RT_ERR_OK)\n            return retVal;\n    }\n\n    /*Set Priority to Qid*/\n    for (priority = 0; priority <= RTK_PRIMAX; priority++)\n    {\n        if ((retVal = rtl8367c_setAsicPriorityToQIDMappingTable(queueNum - 1, priority, g_prioritytToQid[queueNum - 1][priority])) != RT_ERR_OK)\n            return retVal;\n    }\n\n    /*Set Flow Control Type to Ingress Flow Control*/\n    if ((retVal = rtl8367c_setAsicFlowControlSelect(FC_INGRESS)) != RT_ERR_OK)\n        return retVal;\n\n\n    /*Priority Decision Order*/\n    for (priDec = 0;priDec < PRIDEC_END;priDec++)\n    {\n        if ((retVal = rtl8367c_setAsicPriorityDecision(PRIDECTBL_IDX0, priDec, g_priorityDecision[priDec])) != RT_ERR_OK)\n            return retVal;\n        if ((retVal = rtl8367c_setAsicPriorityDecision(PRIDECTBL_IDX1, priDec, g_priorityDecision[priDec])) != RT_ERR_OK)\n            return retVal;\n    }\n\n    /*Set Port-based Priority to 0*/\n    RTK_SCAN_ALL_PHY_PORTMASK(port)\n    {\n        if ((retVal = rtl8367c_setAsicPriorityPortBased(port, 0)) != RT_ERR_OK)\n            return retVal;\n    }\n\n    /*Disable 1p Remarking*/\n    RTK_SCAN_ALL_PHY_PORTMASK(port)\n    {\n        if ((retVal = rtl8367c_setAsicRemarkingDot1pAbility(port, DISABLED)) != RT_ERR_OK)\n            return retVal;\n    }\n\n    /*Disable DSCP Remarking*/\n    if ((retVal = rtl8367c_setAsicRemarkingDscpAbility(DISABLED)) != RT_ERR_OK)\n        return retVal;\n\n    /*Set 1p & DSCP  Priority Remapping & Remarking*/\n    for (priority = 0; priority <= RTL8367C_PRIMAX; priority++)\n    {\n        if ((retVal = rtl8367c_setAsicPriorityDot1qRemapping(priority, g_prioritytRemap[priority])) != RT_ERR_OK)\n            return retVal;\n\n        if ((retVal = rtl8367c_setAsicRemarkingDot1pParameter(priority, 0)) != RT_ERR_OK)\n            return retVal;\n\n        if ((retVal = rtl8367c_setAsicRemarkingDscpParameter(priority, 0)) != RT_ERR_OK)\n            return retVal;\n    }\n\n    /*Set DSCP Priority*/\n    for (dscp = 0; dscp <= 63; dscp++)\n    {\n        if ((retVal = rtl8367c_setAsicPriorityDscpBased(dscp, 0)) != RT_ERR_OK)\n            return retVal;\n    }\n\n    /* Finetune B/T value */\n    if((retVal = rtl8367c_setAsicReg(0x1722, 0x1158)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_qos_priSel_set\n * Description:\n *      Configure the priority order among different priority mechanism.\n * Input:\n *      index - Priority decision table index (0~1)\n *      pPriDec - Priority assign for port, dscp, 802.1p, cvlan, svlan, acl based priority decision.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK                   - OK\n *      RT_ERR_FAILED               - Failed\n *      RT_ERR_SMI                  - SMI access error\n *      RT_ERR_QOS_SEL_PRI_SOURCE   - Invalid priority decision source parameter.\n * Note:\n *      ASIC will follow user priority setting of mechanisms to select mapped queue priority for receiving frame.\n *      If two priority mechanisms are the same, the ASIC will chose the highest priority from mechanisms to\n *      assign queue priority to receiving frame.\n *      The priority sources are:\n *      - PRIDEC_PORT\n *      - PRIDEC_ACL\n *      - PRIDEC_DSCP\n *      - PRIDEC_1Q\n *      - PRIDEC_1AD\n *      - PRIDEC_CVLAN\n *      - PRIDEC_DA\n *      - PRIDEC_SA\n */\nrtk_api_ret_t rtk_qos_priSel_set(rtk_qos_priDecTbl_t index, rtk_priority_select_t *pPriDec)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32 port_pow;\n    rtk_uint32 dot1q_pow;\n    rtk_uint32 dscp_pow;\n    rtk_uint32 acl_pow;\n    rtk_uint32 svlan_pow;\n    rtk_uint32 cvlan_pow;\n    rtk_uint32 smac_pow;\n    rtk_uint32 dmac_pow;\n    rtk_uint32 i;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if (index < 0 || index >= PRIDECTBL_END)\n        return RT_ERR_ENTRY_INDEX;\n\n    if (pPriDec->port_pri >= 8 || pPriDec->dot1q_pri >= 8 || pPriDec->acl_pri >= 8 || pPriDec->dscp_pri >= 8 ||\n       pPriDec->cvlan_pri >= 8 || pPriDec->svlan_pri >= 8 || pPriDec->dmac_pri >= 8 || pPriDec->smac_pri >= 8)\n        return RT_ERR_QOS_SEL_PRI_SOURCE;\n\n    port_pow = 1;\n    for (i = pPriDec->port_pri; i > 0; i--)\n        port_pow = (port_pow)*2;\n\n    dot1q_pow = 1;\n    for (i = pPriDec->dot1q_pri; i > 0; i--)\n        dot1q_pow = (dot1q_pow)*2;\n\n    acl_pow = 1;\n    for (i = pPriDec->acl_pri; i > 0; i--)\n        acl_pow = (acl_pow)*2;\n\n    dscp_pow = 1;\n    for (i = pPriDec->dscp_pri; i > 0; i--)\n        dscp_pow = (dscp_pow)*2;\n\n    svlan_pow = 1;\n    for (i = pPriDec->svlan_pri; i > 0; i--)\n        svlan_pow = (svlan_pow)*2;\n\n    cvlan_pow = 1;\n    for (i = pPriDec->cvlan_pri; i > 0; i--)\n        cvlan_pow = (cvlan_pow)*2;\n\n    dmac_pow = 1;\n    for (i = pPriDec->dmac_pri; i > 0; i--)\n        dmac_pow = (dmac_pow)*2;\n\n    smac_pow = 1;\n    for (i = pPriDec->smac_pri; i > 0; i--)\n        smac_pow = (smac_pow)*2;\n\n    if ((retVal = rtl8367c_setAsicPriorityDecision(index, PRIDEC_PORT, port_pow)) != RT_ERR_OK)\n        return retVal;\n\n    if ((retVal = rtl8367c_setAsicPriorityDecision(index, PRIDEC_ACL, acl_pow)) != RT_ERR_OK)\n        return retVal;\n\n    if ((retVal = rtl8367c_setAsicPriorityDecision(index, PRIDEC_DSCP, dscp_pow)) != RT_ERR_OK)\n        return retVal;\n\n    if ((retVal = rtl8367c_setAsicPriorityDecision(index, PRIDEC_1Q, dot1q_pow)) != RT_ERR_OK)\n        return retVal;\n\n    if ((retVal = rtl8367c_setAsicPriorityDecision(index, PRIDEC_1AD, svlan_pow)) != RT_ERR_OK)\n        return retVal;\n\n    if ((retVal = rtl8367c_setAsicPriorityDecision(index, PRIDEC_CVLAN, cvlan_pow)) != RT_ERR_OK)\n        return retVal;\n\n    if ((retVal = rtl8367c_setAsicPriorityDecision(index, PRIDEC_DA, dmac_pow)) != RT_ERR_OK)\n        return retVal;\n\n    if ((retVal = rtl8367c_setAsicPriorityDecision(index, PRIDEC_SA, smac_pow)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_qos_priSel_get\n * Description:\n *      Get the priority order configuration among different priority mechanism.\n * Input:\n *      index - Priority decision table index (0~1)\n * Output:\n *      pPriDec - Priority assign for port, dscp, 802.1p, cvlan, svlan, acl based priority decision .\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n * Note:\n *      ASIC will follow user priority setting of mechanisms to select mapped queue priority for receiving frame.\n *      If two priority mechanisms are the same, the ASIC will chose the highest priority from mechanisms to\n *      assign queue priority to receiving frame.\n *      The priority sources are:\n *      - PRIDEC_PORT,\n *      - PRIDEC_ACL,\n *      - PRIDEC_DSCP,\n *      - PRIDEC_1Q,\n *      - PRIDEC_1AD,\n *      - PRIDEC_CVLAN,\n *      - PRIDEC_DA,\n *      - PRIDEC_SA,\n */\nrtk_api_ret_t rtk_qos_priSel_get(rtk_qos_priDecTbl_t index, rtk_priority_select_t *pPriDec)\n{\n\n    rtk_api_ret_t retVal;\n    rtk_int32 i;\n    rtk_uint32 port_pow;\n    rtk_uint32 dot1q_pow;\n    rtk_uint32 dscp_pow;\n    rtk_uint32 acl_pow;\n    rtk_uint32 svlan_pow;\n    rtk_uint32 cvlan_pow;\n    rtk_uint32 smac_pow;\n    rtk_uint32 dmac_pow;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if (index < 0 || index >= PRIDECTBL_END)\n        return RT_ERR_ENTRY_INDEX;\n\n    if ((retVal = rtl8367c_getAsicPriorityDecision(index, PRIDEC_PORT, &port_pow)) != RT_ERR_OK)\n        return retVal;\n\n    if ((retVal = rtl8367c_getAsicPriorityDecision(index, PRIDEC_ACL, &acl_pow)) != RT_ERR_OK)\n        return retVal;\n\n    if ((retVal = rtl8367c_getAsicPriorityDecision(index, PRIDEC_DSCP, &dscp_pow)) != RT_ERR_OK)\n        return retVal;\n\n    if ((retVal = rtl8367c_getAsicPriorityDecision(index, PRIDEC_1Q, &dot1q_pow)) != RT_ERR_OK)\n        return retVal;\n\n    if ((retVal = rtl8367c_getAsicPriorityDecision(index, PRIDEC_1AD, &svlan_pow)) != RT_ERR_OK)\n        return retVal;\n\n    if ((retVal = rtl8367c_getAsicPriorityDecision(index, PRIDEC_CVLAN, &cvlan_pow)) != RT_ERR_OK)\n        return retVal;\n\n    if ((retVal = rtl8367c_getAsicPriorityDecision(index, PRIDEC_DA, &dmac_pow)) != RT_ERR_OK)\n        return retVal;\n\n    if ((retVal = rtl8367c_getAsicPriorityDecision(index, PRIDEC_SA, &smac_pow)) != RT_ERR_OK)\n        return retVal;\n\n    for (i = 31; i >= 0; i--)\n    {\n        if (port_pow & (1 << i))\n        {\n            pPriDec->port_pri = i;\n            break;\n        }\n    }\n\n    for (i = 31; i >= 0; i--)\n    {\n        if (dot1q_pow & (1 << i))\n        {\n            pPriDec->dot1q_pri = i;\n            break;\n        }\n    }\n\n    for (i = 31; i >= 0; i--)\n    {\n        if (acl_pow & (1 << i))\n        {\n            pPriDec->acl_pri = i;\n            break;\n        }\n    }\n\n    for (i = 31; i >= 0; i--)\n    {\n        if (dscp_pow & (1 << i))\n        {\n            pPriDec->dscp_pri = i;\n            break;\n        }\n    }\n\n    for (i = 31; i >= 0; i--)\n    {\n        if (svlan_pow & (1 << i))\n        {\n            pPriDec->svlan_pri = i;\n            break;\n        }\n    }\n\n    for (i = 31;i  >= 0; i--)\n    {\n        if (cvlan_pow & (1 << i))\n        {\n            pPriDec->cvlan_pri = i;\n            break;\n        }\n    }\n\n    for (i = 31; i >= 0; i--)\n    {\n        if (dmac_pow&(1<<i))\n        {\n            pPriDec->dmac_pri = i;\n            break;\n        }\n    }\n\n    for (i = 31; i >= 0; i--)\n    {\n        if (smac_pow & (1 << i))\n        {\n            pPriDec->smac_pri = i;\n            break;\n        }\n    }\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_qos_1pPriRemap_set\n * Description:\n *      Configure 1Q priorities mapping to internal absolute priority.\n * Input:\n *      dot1p_pri   - 802.1p priority value.\n *      int_pri     - internal priority value.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - OK\n *      RT_ERR_FAILED           - Failed\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_INPUT            - Invalid input parameters.\n *      RT_ERR_VLAN_PRIORITY    - Invalid 1p priority.\n *      RT_ERR_QOS_INT_PRIORITY - Invalid priority.\n * Note:\n *      Priority of 802.1Q assignment for internal asic priority, and it is used for queue usage and packet scheduling.\n */\nrtk_api_ret_t rtk_qos_1pPriRemap_set(rtk_pri_t dot1p_pri, rtk_pri_t int_pri)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if (dot1p_pri > RTL8367C_PRIMAX || int_pri > RTL8367C_PRIMAX)\n        return  RT_ERR_VLAN_PRIORITY;\n\n    if ((retVal = rtl8367c_setAsicPriorityDot1qRemapping(dot1p_pri, int_pri)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_qos_1pPriRemap_get\n * Description:\n *      Get 1Q priorities mapping to internal absolute priority.\n * Input:\n *      dot1p_pri - 802.1p priority value .\n * Output:\n *      pInt_pri - internal priority value.\n * Return:\n *      RT_ERR_OK               - OK\n *      RT_ERR_FAILED           - Failed\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_VLAN_PRIORITY    - Invalid priority.\n *      RT_ERR_QOS_INT_PRIORITY - Invalid priority.\n * Note:\n *      Priority of 802.1Q assigment for internal asic priority, and it is uesed for queue usage and packet scheduling.\n */\nrtk_api_ret_t rtk_qos_1pPriRemap_get(rtk_pri_t dot1p_pri, rtk_pri_t *pInt_pri)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if (dot1p_pri > RTL8367C_PRIMAX)\n        return  RT_ERR_QOS_INT_PRIORITY;\n\n    if ((retVal = rtl8367c_getAsicPriorityDot1qRemapping(dot1p_pri, pInt_pri)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_qos_dscpPriRemap_set\n * Description:\n *      Map dscp value to internal priority.\n * Input:\n *      dscp    - Dscp value of receiving frame\n *      int_pri - internal priority value .\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - OK\n *      RT_ERR_FAILED           - Failed\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_INPUT            - Invalid input parameters.\n *      RT_ERR_QOS_DSCP_VALUE   - Invalid DSCP value.\n *      RT_ERR_QOS_INT_PRIORITY - Invalid priority.\n * Note:\n *      The Differentiated Service Code Point is a selector for router's per-hop behaviors. As a selector, there is no implication that a numerically\n *      greater DSCP implies a better network service. As can be seen, the DSCP totally overlaps the old precedence field of TOS. So if values of\n *      DSCP are carefully chosen then backward compatibility can be achieved.\n */\nrtk_api_ret_t rtk_qos_dscpPriRemap_set(rtk_dscp_t dscp, rtk_pri_t int_pri)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if (int_pri > RTL8367C_PRIMAX )\n        return RT_ERR_QOS_INT_PRIORITY;\n\n    if (dscp > RTL8367C_DSCPMAX)\n        return RT_ERR_QOS_DSCP_VALUE;\n\n    if ((retVal = rtl8367c_setAsicPriorityDscpBased(dscp, int_pri)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_qos_dscpPriRemap_get\n * Description:\n *      Get dscp value to internal priority.\n * Input:\n *      dscp - Dscp value of receiving frame\n * Output:\n *      pInt_pri - internal priority value.\n * Return:\n *      RT_ERR_OK               - OK\n *      RT_ERR_FAILED           - Failed\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_QOS_DSCP_VALUE   - Invalid DSCP value.\n * Note:\n *      The Differentiated Service Code Point is a selector for router's per-hop behaviors. As a selector, there is no implication that a numerically\n *      greater DSCP implies a better network service. As can be seen, the DSCP totally overlaps the old precedence field of TOS. So if values of\n *      DSCP are carefully chosen then backward compatibility can be achieved.\n */\nrtk_api_ret_t rtk_qos_dscpPriRemap_get(rtk_dscp_t dscp, rtk_pri_t *pInt_pri)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if (dscp > RTL8367C_DSCPMAX)\n        return RT_ERR_QOS_DSCP_VALUE;\n\n    if ((retVal = rtl8367c_getAsicPriorityDscpBased(dscp, pInt_pri)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_qos_portPri_set\n * Description:\n *      Configure priority usage to each port.\n * Input:\n *      port - Port id.\n *      int_pri - internal priority value.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - OK\n *      RT_ERR_FAILED           - Failed\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_PORT_ID          - Invalid port number.\n *      RT_ERR_QOS_SEL_PORT_PRI - Invalid port priority.\n *      RT_ERR_QOS_INT_PRIORITY - Invalid priority.\n * Note:\n *      The API can set priority of port assignments for queue usage and packet scheduling.\n */\nrtk_api_ret_t rtk_qos_portPri_set(rtk_port_t port, rtk_pri_t int_pri)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check Port Valid */\n    RTK_CHK_PORT_VALID(port);\n\n    if (int_pri > RTL8367C_PRIMAX )\n        return RT_ERR_QOS_INT_PRIORITY;\n\n    if ((retVal = rtl8367c_setAsicPriorityPortBased(rtk_switch_port_L2P_get(port), int_pri)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_qos_portPri_get\n * Description:\n *      Get priority usage to each port.\n * Input:\n *      port - Port id.\n * Output:\n *      pInt_pri - internal priority value.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number.\n *      RT_ERR_INPUT        - Invalid input parameters.\n * Note:\n *      The API can get priority of port assignments for queue usage and packet scheduling.\n */\nrtk_api_ret_t rtk_qos_portPri_get(rtk_port_t port, rtk_pri_t *pInt_pri)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check Port Valid */\n    RTK_CHK_PORT_VALID(port);\n\n    if ((retVal = rtl8367c_getAsicPriorityPortBased(rtk_switch_port_L2P_get(port), pInt_pri)) != RT_ERR_OK)\n        return retVal;\n\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_qos_queueNum_set\n * Description:\n *      Set output queue number for each port.\n * Input:\n *      port    - Port id.\n *      index   - Mapping queue number (1~8)\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number.\n *      RT_ERR_QUEUE_NUM    - Invalid queue number.\n * Note:\n *      The API can set the output queue number of the specified port. The queue number is from 1 to 8.\n */\nrtk_api_ret_t rtk_qos_queueNum_set(rtk_port_t port, rtk_queue_num_t queue_num)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check Port Valid */\n    RTK_CHK_PORT_VALID(port);\n\n    if ((0 == queue_num) || (queue_num > RTK_MAX_NUM_OF_QUEUE))\n        return RT_ERR_FAILED;\n\n    if (RTK_MAX_NUM_OF_QUEUE == queue_num)\n        queue_num = 0;\n\n    if ((retVal = rtl8367c_setAsicOutputQueueMappingIndex(rtk_switch_port_L2P_get(port), queue_num)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_qos_queueNum_get\n * Description:\n *      Get output queue number.\n * Input:\n *      port - Port id.\n * Output:\n *      pQueue_num - Mapping queue number\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number.\n * Note:\n *      The API will return the output queue number of the specified port. The queue number is from 1 to 8.\n */\nrtk_api_ret_t rtk_qos_queueNum_get(rtk_port_t port, rtk_queue_num_t *pQueue_num)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32 qidx;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check Port Valid */\n    RTK_CHK_PORT_VALID(port);\n\n    if ((retVal = rtl8367c_getAsicOutputQueueMappingIndex(rtk_switch_port_L2P_get(port), &qidx)) != RT_ERR_OK)\n        return retVal;\n\n    if (0 == qidx)\n        *pQueue_num = 8;\n    else\n        *pQueue_num = qidx;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_qos_priMap_set\n * Description:\n *      Set output queue number for each port.\n * Input:\n *      queue_num   - Queue number usage.\n *      pPri2qid    - Priority mapping to queue ID.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - OK\n *      RT_ERR_FAILED           - Failed\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_INPUT            - Invalid input parameters.\n *      RT_ERR_QUEUE_NUM        - Invalid queue number.\n *      RT_ERR_QUEUE_ID         - Invalid queue id.\n *      RT_ERR_PORT_ID          - Invalid port number.\n *      RT_ERR_QOS_INT_PRIORITY - Invalid priority.\n * Note:\n *      ASIC supports priority mapping to queue with different queue number from 1 to 8.\n *      For different queue numbers usage, ASIC supports different internal available queue IDs.\n */\nrtk_api_ret_t rtk_qos_priMap_set(rtk_queue_num_t queue_num, rtk_qos_pri2queue_t *pPri2qid)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32 pri;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if ((0 == queue_num) || (queue_num > RTK_MAX_NUM_OF_QUEUE))\n        return RT_ERR_QUEUE_NUM;\n\n    for (pri = 0; pri <= RTK_PRIMAX; pri++)\n    {\n        if (pPri2qid->pri2queue[pri] > RTK_QIDMAX)\n            return RT_ERR_QUEUE_ID;\n\n        if ((retVal = rtl8367c_setAsicPriorityToQIDMappingTable(queue_num - 1, pri, pPri2qid->pri2queue[pri])) != RT_ERR_OK)\n            return retVal;\n    }\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_qos_priMap_get\n * Description:\n *      Get priority to queue ID mapping table parameters.\n * Input:\n *      queue_num - Queue number usage.\n * Output:\n *      pPri2qid - Priority mapping to queue ID.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n *      RT_ERR_QUEUE_NUM    - Invalid queue number.\n * Note:\n *      The API can return the mapping queue id of the specified priority and queue number.\n *      The queue number is from 1 to 8.\n */\nrtk_api_ret_t rtk_qos_priMap_get(rtk_queue_num_t queue_num, rtk_qos_pri2queue_t *pPri2qid)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32 pri;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if ((0 == queue_num) || (queue_num > RTK_MAX_NUM_OF_QUEUE))\n        return RT_ERR_QUEUE_NUM;\n\n    for (pri = 0; pri <= RTK_PRIMAX; pri++)\n    {\n        if ((retVal = rtl8367c_getAsicPriorityToQIDMappingTable(queue_num-1, pri, &pPri2qid->pri2queue[pri])) != RT_ERR_OK)\n            return retVal;\n    }\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_qos_schedulingQueue_set\n * Description:\n *      Set weight and type of queues in dedicated port.\n * Input:\n *      port        - Port id.\n *      pQweights   - The array of weights for WRR/WFQ queue (0 for STRICT_PRIORITY queue).\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - OK\n *      RT_ERR_FAILED           - Failed\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_PORT_ID          - Invalid port number.\n *      RT_ERR_QOS_QUEUE_WEIGHT - Invalid queue weight.\n * Note:\n *      The API can set weight and type, strict priority or weight fair queue (WFQ) for\n *      dedicated port for using queues. If queue id is not included in queue usage,\n *      then its type and weight setting in dummy for setting. There are priorities\n *      as queue id in strict queues. It means strict queue id 5 carrying higher priority\n *      than strict queue id 4. The WFQ queue weight is from 1 to 127, and weight 0 is\n *      for strict priority queue type.\n */\nrtk_api_ret_t rtk_qos_schedulingQueue_set(rtk_port_t port, rtk_qos_queue_weights_t *pQweights)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32 qid;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check Port Valid */\n    RTK_CHK_PORT_VALID(port);\n\n    for (qid = 0; qid < RTL8367C_QUEUENO; qid ++)\n    {\n\n        if (pQweights->weights[qid] > QOS_WEIGHT_MAX)\n            return RT_ERR_QOS_QUEUE_WEIGHT;\n\n        if (0 == pQweights->weights[qid])\n        {\n            if ((retVal = rtl8367c_setAsicQueueType(rtk_switch_port_L2P_get(port), qid, QTYPE_STRICT)) != RT_ERR_OK)\n                return retVal;\n        }\n        else\n        {\n            if ((retVal = rtl8367c_setAsicQueueType(rtk_switch_port_L2P_get(port), qid, QTYPE_WFQ)) != RT_ERR_OK)\n                return retVal;\n\n            if ((retVal = rtl8367c_setAsicWFQWeight(rtk_switch_port_L2P_get(port),qid, pQweights->weights[qid])) != RT_ERR_OK)\n                return retVal;\n        }\n    }\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_qos_schedulingQueue_get\n * Description:\n *      Get weight and type of queues in dedicated port.\n * Input:\n *      port - Port id.\n * Output:\n *      pQweights - The array of weights for WRR/WFQ queue (0 for STRICT_PRIORITY queue).\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n *      RT_ERR_PORT_ID      - Invalid port number.\n * Note:\n *      The API can get weight and type, strict priority or weight fair queue (WFQ) for dedicated port for using queues.\n *      The WFQ queue weight is from 1 to 127, and weight 0 is for strict priority queue type.\n */\nrtk_api_ret_t rtk_qos_schedulingQueue_get(rtk_port_t port, rtk_qos_queue_weights_t *pQweights)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32 qid,qtype,qweight;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check Port Valid */\n    RTK_CHK_PORT_VALID(port);\n\n    for (qid = 0; qid < RTL8367C_QUEUENO; qid++)\n    {\n        if ((retVal = rtl8367c_getAsicQueueType(rtk_switch_port_L2P_get(port), qid, &qtype)) != RT_ERR_OK)\n            return retVal;\n\n        if (QTYPE_STRICT == qtype)\n        {\n            pQweights->weights[qid] = 0;\n        }\n        else if (QTYPE_WFQ == qtype)\n        {\n            if ((retVal = rtl8367c_getAsicWFQWeight(rtk_switch_port_L2P_get(port), qid, &qweight)) != RT_ERR_OK)\n                return retVal;\n            pQweights->weights[qid] = qweight;\n        }\n    }\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_qos_1pRemarkEnable_set\n * Description:\n *      Set 1p Remarking state\n * Input:\n *      port        - Port id.\n *      enable      - State of per-port 1p Remarking\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number.\n *      RT_ERR_ENABLE       - Invalid enable parameter.\n * Note:\n *      The API can enable or disable 802.1p remarking ability for whole system.\n *      The status of 802.1p remark:\n *      - DISABLED\n *      - ENABLED\n */\nrtk_api_ret_t rtk_qos_1pRemarkEnable_set(rtk_port_t port, rtk_enable_t enable)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check Port Valid */\n    RTK_CHK_PORT_VALID(port);\n\n    if (enable >= RTK_ENABLE_END)\n        return RT_ERR_INPUT;\n\n    if ((retVal = rtl8367c_setAsicRemarkingDot1pAbility(rtk_switch_port_L2P_get(port), enable)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_qos_1pRemarkEnable_get\n * Description:\n *      Get 802.1p remarking ability.\n * Input:\n *      port - Port id.\n * Output:\n *      pEnable - Status of 802.1p remark.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number.\n * Note:\n *      The API can get 802.1p remarking ability.\n *      The status of 802.1p remark:\n *      - DISABLED\n *      - ENABLED\n */\nrtk_api_ret_t rtk_qos_1pRemarkEnable_get(rtk_port_t port, rtk_enable_t *pEnable)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check Port Valid */\n    RTK_CHK_PORT_VALID(port);\n\n    if ((retVal = rtl8367c_getAsicRemarkingDot1pAbility(rtk_switch_port_L2P_get(port), pEnable)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_qos_1pRemark_set\n * Description:\n *      Set 802.1p remarking parameter.\n * Input:\n *      int_pri     - Internal priority value.\n *      dot1p_pri   - 802.1p priority value.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - OK\n *      RT_ERR_FAILED           - Failed\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_VLAN_PRIORITY    - Invalid 1p priority.\n *      RT_ERR_QOS_INT_PRIORITY - Invalid priority.\n * Note:\n *      The API can set 802.1p parameters source priority and new priority.\n */\nrtk_api_ret_t rtk_qos_1pRemark_set(rtk_pri_t int_pri, rtk_pri_t dot1p_pri)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if (int_pri > RTL8367C_PRIMAX )\n        return RT_ERR_QOS_INT_PRIORITY;\n\n    if (dot1p_pri > RTL8367C_PRIMAX)\n        return RT_ERR_VLAN_PRIORITY;\n\n    if ((retVal = rtl8367c_setAsicRemarkingDot1pParameter(int_pri, dot1p_pri)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_qos_1pRemark_get\n * Description:\n *      Get 802.1p remarking parameter.\n * Input:\n *      int_pri - Internal priority value.\n * Output:\n *      pDot1p_pri - 802.1p priority value.\n * Return:\n *      RT_ERR_OK               - OK\n *      RT_ERR_FAILED           - Failed\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_QOS_INT_PRIORITY - Invalid priority.\n * Note:\n *      The API can get 802.1p remarking parameters. It would return new priority of ingress priority.\n */\nrtk_api_ret_t rtk_qos_1pRemark_get(rtk_pri_t int_pri, rtk_pri_t *pDot1p_pri)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if (int_pri > RTL8367C_PRIMAX )\n        return RT_ERR_QOS_INT_PRIORITY;\n\n    if ((retVal = rtl8367c_getAsicRemarkingDot1pParameter(int_pri, pDot1p_pri)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_qos_1pRemarkSrcSel_set\n * Description:\n *      Set remarking source of 802.1p remarking.\n * Input:\n *      type      - remarking source\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n *      RT_ERR_NOT_INIT         - The module is not initial\n *      RT_ERR_PORT_ID  - invalid port id\n *      RT_ERR_INPUT            - invalid input parameter\n\n * Note:\n *      The API can configure 802.1p remark functionality to map original 802.1p value or internal\n *      priority to TX DSCP value.\n */\nrtk_api_ret_t rtk_qos_1pRemarkSrcSel_set(rtk_qos_1pRmkSrc_t type)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if (type >= DOT1P_RMK_SRC_END )\n        return RT_ERR_QOS_INT_PRIORITY;\n\n    if ((retVal = rtl8367c_setAsicRemarkingDot1pSrc(type)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_qos_1pRemarkSrcSel_get\n * Description:\n *      Get remarking source of 802.1p remarking.\n * Input:\n *      none\n * Output:\n *      pType      - remarking source\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n *      RT_ERR_NOT_INIT         - The module is not initial\n *      RT_ERR_PORT_ID          - invalid port id\n *      RT_ERR_INPUT            - invalid input parameter\n *      RT_ERR_NULL_POINTER     - input parameter may be null pointer\n\n * Note:\n *      None\n */\nrtk_api_ret_t rtk_qos_1pRemarkSrcSel_get(rtk_qos_1pRmkSrc_t *pType)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if ((retVal = rtl8367c_getAsicRemarkingDot1pSrc(pType)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n\n/* Function Name:\n *      rtk_qos_dscpRemarkEnable_set\n * Description:\n *      Set DSCP remarking ability.\n * Input:\n *      port    - Port id.\n *      enable  - status of DSCP remark.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - OK\n *      RT_ERR_FAILED           - Failed\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_PORT_ID          - Invalid port number.\n *      RT_ERR_QOS_INT_PRIORITY - Invalid priority.\n *      RT_ERR_ENABLE           - Invalid enable parameter.\n * Note:\n *      The API can enable or disable DSCP remarking ability for whole system.\n *      The status of DSCP remark:\n *      - DISABLED\n *      - ENABLED\n */\nrtk_api_ret_t rtk_qos_dscpRemarkEnable_set(rtk_port_t port, rtk_enable_t enable)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /*for whole system function, the port value should be 0xFF*/\n    if (port != RTK_WHOLE_SYSTEM)\n        return RT_ERR_PORT_ID;\n\n    if (enable >= RTK_ENABLE_END)\n        return RT_ERR_INPUT;\n\n    if ((retVal = rtl8367c_setAsicRemarkingDscpAbility(enable)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_qos_dscpRemarkEnable_get\n * Description:\n *      Get DSCP remarking ability.\n * Input:\n *      port - Port id.\n * Output:\n *      pEnable - status of DSCP remarking.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number.\n * Note:\n *      The API can get DSCP remarking ability.\n *      The status of DSCP remark:\n *      - DISABLED\n *      - ENABLED\n */\nrtk_api_ret_t rtk_qos_dscpRemarkEnable_get(rtk_port_t port, rtk_enable_t *pEnable)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /*for whole system function, the port value should be 0xFF*/\n    if (port != RTK_WHOLE_SYSTEM)\n        return RT_ERR_PORT_ID;\n\n    if ((retVal = rtl8367c_getAsicRemarkingDscpAbility(pEnable)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_qos_dscpRemark_set\n * Description:\n *      Set DSCP remarking parameter.\n * Input:\n *      int_pri - Internal priority value.\n *      dscp    - DSCP value.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - OK\n *      RT_ERR_FAILED           - Failed\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_QOS_INT_PRIORITY - Invalid priority.\n *      RT_ERR_QOS_DSCP_VALUE   - Invalid DSCP value.\n * Note:\n *      The API can set DSCP value and mapping priority.\n */\nrtk_api_ret_t rtk_qos_dscpRemark_set(rtk_pri_t int_pri, rtk_dscp_t dscp)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if (int_pri > RTK_PRIMAX )\n        return RT_ERR_QOS_INT_PRIORITY;\n\n    if (dscp > RTK_DSCPMAX)\n        return RT_ERR_QOS_DSCP_VALUE;\n\n    if ((retVal = rtl8367c_setAsicRemarkingDscpParameter(int_pri, dscp)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n\n/* Function Name:\n *      rtk_qos_dscpRemark_get\n * Description:\n *      Get DSCP remarking parameter.\n * Input:\n *      int_pri - Internal priority value.\n * Output:\n *      Dscp - DSCP value.\n * Return:\n *      RT_ERR_OK               - OK\n *      RT_ERR_FAILED           - Failed\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_QOS_INT_PRIORITY - Invalid priority.\n * Note:\n *      The API can get DSCP parameters. It would return DSCP value for mapping priority.\n */\nrtk_api_ret_t rtk_qos_dscpRemark_get(rtk_pri_t int_pri, rtk_dscp_t *pDscp)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if (int_pri > RTK_PRIMAX )\n        return RT_ERR_QOS_INT_PRIORITY;\n\n    if ((retVal = rtl8367c_getAsicRemarkingDscpParameter(int_pri, pDscp)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_qos_dscpRemarkSrcSel_set\n * Description:\n *      Set remarking source of DSCP remarking.\n * Input:\n *      type      - remarking source\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n *      RT_ERR_NOT_INIT         - The module is not initial\n *      RT_ERR_PORT_ID  - invalid port id\n *      RT_ERR_INPUT            - invalid input parameter\n\n * Note:\n *      The API can configure DSCP remark functionality to map original DSCP value or internal\n *      priority to TX DSCP value.\n */\nrtk_api_ret_t rtk_qos_dscpRemarkSrcSel_set(rtk_qos_dscpRmkSrc_t type)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if (type >= DSCP_RMK_SRC_END )\n        return RT_ERR_QOS_INT_PRIORITY;\n\n    if ((retVal = rtl8367c_setAsicRemarkingDscpSrc(type)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_qos_dcpRemarkSrcSel_get\n * Description:\n *      Get remarking source of DSCP remarking.\n * Input:\n *      none\n * Output:\n *      pType      - remarking source\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n *      RT_ERR_NOT_INIT         - The module is not initial\n *      RT_ERR_PORT_ID          - invalid port id\n *      RT_ERR_INPUT            - invalid input parameter\n *      RT_ERR_NULL_POINTER     - input parameter may be null pointer\n\n * Note:\n *      None\n */\nrtk_api_ret_t rtk_qos_dscpRemarkSrcSel_get(rtk_qos_dscpRmkSrc_t *pType)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if ((retVal = rtl8367c_getAsicRemarkingDscpSrc(pType)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_qos_dscpRemark2Dscp_set\n * Description:\n *      Set DSCP to remarked DSCP mapping.\n * Input:\n *      dscp    - DSCP value\n *      rmkDscp - remarked DSCP value\n * Output:\n *      None.\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n *      RT_ERR_QOS_DSCP_VALUE   - Invalid dscp value\n * Note:\n *      dscp parameter can be DSCP value or internal priority according to configuration of API\n *      dal_apollomp_qos_dscpRemarkSrcSel_set(), because DSCP remark functionality can map original DSCP\n *      value or internal priority to TX DSCP value.\n */\nrtk_api_ret_t rtk_qos_dscpRemark2Dscp_set(rtk_dscp_t dscp, rtk_dscp_t rmkDscp)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if ((dscp > RTK_DSCPMAX) || (rmkDscp > RTK_DSCPMAX))\n        return RT_ERR_QOS_DSCP_VALUE;\n\n    if ((retVal = rtl8367c_setAsicRemarkingDscp2Dscp(dscp, rmkDscp)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_qos_dscpRemark2Dscp_get\n * Description:\n *      Get DSCP to remarked DSCP mapping.\n * Input:\n *      dscp    - DSCP value\n * Output:\n *      pDscp   - remarked DSCP value\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n *      RT_ERR_QOS_DSCP_VALUE   - Invalid dscp value\n *      RT_ERR_NULL_POINTER     - NULL pointer\n * Note:\n *      None.\n */\nrtk_api_ret_t rtk_qos_dscpRemark2Dscp_get(rtk_dscp_t dscp, rtk_dscp_t *pDscp)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if (dscp > RTK_DSCPMAX)\n        return RT_ERR_QOS_DSCP_VALUE;\n\n    if ((retVal = rtl8367c_getAsicRemarkingDscp2Dscp(dscp, pDscp)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_qos_portPriSelIndex_set\n * Description:\n *      Configure priority decision index to each port.\n * Input:\n *      port - Port id.\n *      index - priority decision index.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - OK\n *      RT_ERR_FAILED           - Failed\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_PORT_ID          - Invalid port number.\n *      RT_ERR_ENTRY_INDEX - Invalid entry index.\n * Note:\n *      The API can set priority of port assignments for queue usage and packet scheduling.\n */\nrtk_api_ret_t rtk_qos_portPriSelIndex_set(rtk_port_t port, rtk_qos_priDecTbl_t index)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check Port Valid */\n    RTK_CHK_PORT_VALID(port);\n\n    if (index >= PRIDECTBL_END )\n        return RT_ERR_ENTRY_INDEX;\n\n    if ((retVal = rtl8367c_setAsicPortPriorityDecisionIndex(rtk_switch_port_L2P_get(port), index)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_qos_portPriSelIndex_get\n * Description:\n *      Get priority decision index from each port.\n * Input:\n *      port - Port id.\n * Output:\n *      pIndex - priority decision index.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number.\n * Note:\n *      The API can get priority of port assignments for queue usage and packet scheduling.\n */\nrtk_api_ret_t rtk_qos_portPriSelIndex_get(rtk_port_t port, rtk_qos_priDecTbl_t *pIndex)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check Port Valid */\n    RTK_CHK_PORT_VALID(port);\n\n    if ((retVal = rtl8367c_getAsicPortPriorityDecisionIndex(rtk_switch_port_L2P_get(port), pIndex)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n\n\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rate.c",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * $Revision: 76306 $\n * $Date: 2017-03-08 15:13:58 +0800 (週三, 08 三月 2017) $\n *\n * Purpose : RTK switch high-level API for RTL8367/RTL8367C\n * Feature : Here is a list of all functions and variables in rate module.\n *\n */\n\n#include <rtk_switch.h>\n#include <rtk_error.h>\n#include <rate.h>\n#include <qos.h>\n#include <string.h>\n\n#include <rtl8367c_asicdrv.h>\n#include <rtl8367c_asicdrv_meter.h>\n#include <rtl8367c_asicdrv_inbwctrl.h>\n#include <rtl8367c_asicdrv_scheduling.h>\n\n/* Function Name:\n *      rtk_rate_shareMeter_set\n * Description:\n *      Set meter configuration\n * Input:\n *      index       - shared meter index\n *      type        - shared meter type\n *      rate        - rate of share meter\n *      ifg_include - include IFG or not, ENABLE:include DISABLE:exclude\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - OK\n *      RT_ERR_FAILED           - Failed\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_FILTER_METER_ID  - Invalid meter\n *      RT_ERR_RATE             - Invalid rate\n *      RT_ERR_INPUT            - Invalid input parameters\n * Note:\n *      The API can set shared meter rate and ifg include for each meter.\n *      The rate unit is 1 kbps and the range is from 8k to 1048568k if type is METER_TYPE_KBPS and\n *      the granularity of rate is 8 kbps.\n *      The rate unit is packets per second and the range is 1 ~ 0x1FFF if type is METER_TYPE_PPS.\n *      The ifg_include parameter is used\n *      for rate calculation with/without inter-frame-gap and preamble.\n */\nrtk_api_ret_t rtk_rate_shareMeter_set(rtk_meter_id_t index, rtk_meter_type_t type, rtk_rate_t rate, rtk_enable_t ifg_include)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if (index > RTK_MAX_METER_ID)\n        return RT_ERR_FILTER_METER_ID;\n\n    if (type >= METER_TYPE_END)\n        return RT_ERR_INPUT;\n\n    if (ifg_include >= RTK_ENABLE_END)\n        return RT_ERR_INPUT;\n\n    switch (type)\n    {\n        case METER_TYPE_KBPS:\n            if (rate > RTL8367C_QOS_RATE_INPUT_MAX_HSG || rate < RTL8367C_QOS_RATE_INPUT_MIN)\n                return RT_ERR_RATE ;\n\n            if ((retVal = rtl8367c_setAsicShareMeter(index, rate >> 3, ifg_include)) != RT_ERR_OK)\n                return retVal;\n\n            break;\n        case METER_TYPE_PPS:\n            if (rate > RTL8367C_QOS_PPS_INPUT_MAX || rate < RTL8367C_QOS_PPS_INPUT_MIN)\n                return RT_ERR_RATE ;\n\n            if ((retVal = rtl8367c_setAsicShareMeter(index, rate, ifg_include)) != RT_ERR_OK)\n                return retVal;\n\n            break;\n        default:\n            return RT_ERR_INPUT;\n    }\n\n    /* Set Type */\n    if ((retVal = rtl8367c_setAsicShareMeterType(index, (rtk_uint32)type)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_rate_shareMeter_get\n * Description:\n *      Get meter configuration\n * Input:\n *      index        - shared meter index\n * Output:\n *      pType        - Meter Type\n *      pRate        - pointer of rate of share meter\n *      pIfg_include - include IFG or not, ENABLE:include DISABLE:exclude\n * Return:\n *      RT_ERR_OK               - OK\n *      RT_ERR_FAILED           - Failed\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_FILTER_METER_ID  - Invalid meter\n * Note:\n *\n */\nrtk_api_ret_t rtk_rate_shareMeter_get(rtk_meter_id_t index, rtk_meter_type_t *pType, rtk_rate_t *pRate, rtk_enable_t *pIfg_include)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32 regData;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if (index > RTK_MAX_METER_ID)\n        return RT_ERR_FILTER_METER_ID;\n\n    if(NULL == pType)\n        return RT_ERR_NULL_POINTER;\n\n    if(NULL == pRate)\n        return RT_ERR_NULL_POINTER;\n\n    if(NULL == pIfg_include)\n        return RT_ERR_NULL_POINTER;\n\n    if ((retVal = rtl8367c_getAsicShareMeter(index, &regData, pIfg_include)) != RT_ERR_OK)\n        return retVal;\n\n    if ((retVal = rtl8367c_getAsicShareMeterType(index, (rtk_uint32 *)pType)) != RT_ERR_OK)\n        return retVal;\n\n    if(*pType == METER_TYPE_KBPS)\n        *pRate = regData<<3;\n    else\n        *pRate = regData;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_rate_shareMeterBucket_set\n * Description:\n *      Set meter Bucket Size\n * Input:\n *      index        - shared meter index\n *      bucket_size  - Bucket Size\n * Output:\n *      None.\n * Return:\n *      RT_ERR_OK               - OK\n *      RT_ERR_FAILED           - Failed\n *      RT_ERR_INPUT            - Error Input\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_FILTER_METER_ID  - Invalid meter\n * Note:\n *      The API can set shared meter bucket size.\n */\nrtk_api_ret_t rtk_rate_shareMeterBucket_set(rtk_meter_id_t index, rtk_uint32 bucket_size)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if (index > RTK_MAX_METER_ID)\n        return RT_ERR_FILTER_METER_ID;\n\n    if(bucket_size > RTL8367C_METERBUCKETSIZEMAX)\n        return RT_ERR_INPUT;\n\n    if ((retVal = rtl8367c_setAsicShareMeterBucketSize(index, bucket_size)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_rate_shareMeterBucket_get\n * Description:\n *      Get meter Bucket Size\n * Input:\n *      index        - shared meter index\n * Output:\n *      pBucket_size - Bucket Size\n * Return:\n *      RT_ERR_OK               - OK\n *      RT_ERR_FAILED           - Failed\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_FILTER_METER_ID  - Invalid meter\n * Note:\n *      The API can get shared meter bucket size.\n */\nrtk_api_ret_t rtk_rate_shareMeterBucket_get(rtk_meter_id_t index, rtk_uint32 *pBucket_size)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if (index > RTK_MAX_METER_ID)\n        return RT_ERR_FILTER_METER_ID;\n\n    if(NULL == pBucket_size)\n        return RT_ERR_NULL_POINTER;\n\n    if ((retVal = rtl8367c_getAsicShareMeterBucketSize(index, pBucket_size)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_rate_igrBandwidthCtrlRate_set\n * Description:\n *      Set port ingress bandwidth control\n * Input:\n *      port        - Port id\n *      rate        - Rate of share meter\n *      ifg_include - include IFG or not, ENABLE:include DISABLE:exclude\n *      fc_enable   - enable flow control or not, ENABLE:use flow control DISABLE:drop\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number.\n *      RT_ERR_ENABLE       - Invalid IFG parameter.\n *      RT_ERR_INBW_RATE    - Invalid ingress rate parameter.\n * Note:\n *      The rate unit is 1 kbps and the range is from 8k to 1048568k. The granularity of rate is 8 kbps.\n *      The ifg_include parameter is used for rate calculation with/without inter-frame-gap and preamble.\n */\nrtk_api_ret_t rtk_rate_igrBandwidthCtrlRate_set(rtk_port_t port, rtk_rate_t rate, rtk_enable_t ifg_include, rtk_enable_t fc_enable)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check Port Valid */\n    RTK_CHK_PORT_VALID(port);\n\n    if(ifg_include >= RTK_ENABLE_END)\n        return RT_ERR_INPUT;\n\n    if(fc_enable >= RTK_ENABLE_END)\n        return RT_ERR_INPUT;\n\n    if(rtk_switch_isHsgPort(port) == RT_ERR_OK)\n    {\n        if ((rate > RTL8367C_QOS_RATE_INPUT_MAX_HSG) || (rate < RTL8367C_QOS_RATE_INPUT_MIN))\n            return RT_ERR_QOS_EBW_RATE ;\n    }\n    else\n    {\n        if ((rate > RTL8367C_QOS_RATE_INPUT_MAX) || (rate < RTL8367C_QOS_RATE_INPUT_MIN))\n            return RT_ERR_QOS_EBW_RATE ;\n    }\n\n    if ((retVal = rtl8367c_setAsicPortIngressBandwidth(rtk_switch_port_L2P_get(port), rate>>3, ifg_include,fc_enable)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_rate_igrBandwidthCtrlRate_get\n * Description:\n *      Get port ingress bandwidth control\n * Input:\n *      port - Port id\n * Output:\n *      pRate           - Rate of share meter\n *      pIfg_include    - Rate's calculation including IFG, ENABLE:include DISABLE:exclude\n *      pFc_enable      - enable flow control or not, ENABLE:use flow control DISABLE:drop\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number.\n *      RT_ERR_INPUT        - Invalid input parameters.\n * Note:\n *     The rate unit is 1 kbps and the range is from 8k to 1048568k. The granularity of rate is 8 kbps.\n *     The ifg_include parameter is used for rate calculation with/without inter-frame-gap and preamble.\n */\nrtk_api_ret_t rtk_rate_igrBandwidthCtrlRate_get(rtk_port_t port, rtk_rate_t *pRate, rtk_enable_t *pIfg_include, rtk_enable_t *pFc_enable)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32 regData;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check Port Valid */\n    RTK_CHK_PORT_VALID(port);\n\n    if(NULL == pIfg_include)\n        return RT_ERR_NULL_POINTER;\n\n    if(NULL == pFc_enable)\n        return RT_ERR_NULL_POINTER;\n\n    if ((retVal = rtl8367c_getAsicPortIngressBandwidth(rtk_switch_port_L2P_get(port), &regData, pIfg_include, pFc_enable)) != RT_ERR_OK)\n        return retVal;\n\n    *pRate = regData<<3;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_rate_egrBandwidthCtrlRate_set\n * Description:\n *      Set port egress bandwidth control\n * Input:\n *      port        - Port id\n *      rate        - Rate of egress bandwidth\n *      ifg_include - include IFG or not, ENABLE:include DISABLE:exclude\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number.\n *      RT_ERR_INPUT        - Invalid input parameters.\n *      RT_ERR_QOS_EBW_RATE - Invalid egress bandwidth/rate\n * Note:\n *     The rate unit is 1 kbps and the range is from 8k to 1048568k. The granularity of rate is 8 kbps.\n *     The ifg_include parameter is used for rate calculation with/without inter-frame-gap and preamble.\n */\nrtk_api_ret_t rtk_rate_egrBandwidthCtrlRate_set( rtk_port_t port, rtk_rate_t rate,  rtk_enable_t ifg_include)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check Port Valid */\n    RTK_CHK_PORT_VALID(port);\n\n    if(rtk_switch_isHsgPort(port) == RT_ERR_OK)\n    {\n        if ((rate > RTL8367C_QOS_RATE_INPUT_MAX_HSG) || (rate < RTL8367C_QOS_RATE_INPUT_MIN))\n            return RT_ERR_QOS_EBW_RATE ;\n    }\n    else\n    {\n        if ((rate > RTL8367C_QOS_RATE_INPUT_MAX) || (rate < RTL8367C_QOS_RATE_INPUT_MIN))\n            return RT_ERR_QOS_EBW_RATE ;\n    }\n\n    if (ifg_include >= RTK_ENABLE_END)\n        return RT_ERR_ENABLE;\n\n    if ((retVal = rtl8367c_setAsicPortEgressRate(rtk_switch_port_L2P_get(port), rate>>3)) != RT_ERR_OK)\n        return retVal;\n\n    if ((retVal = rtl8367c_setAsicPortEgressRateIfg(ifg_include)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_rate_egrBandwidthCtrlRate_get\n * Description:\n *      Get port egress bandwidth control\n * Input:\n *      port - Port id\n * Output:\n *      pRate           - Rate of egress bandwidth\n *      pIfg_include    - Rate's calculation including IFG, ENABLE:include DISABLE:exclude\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number.\n *      RT_ERR_INPUT        - Invalid input parameters.\n * Note:\n *     The rate unit is 1 kbps and the range is from 8k to 1048568k. The granularity of rate is 8 kbps.\n *     The ifg_include parameter is used for rate calculation with/without inter-frame-gap and preamble.\n */\nrtk_api_ret_t rtk_rate_egrBandwidthCtrlRate_get(rtk_port_t port, rtk_rate_t *pRate, rtk_enable_t *pIfg_include)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32 regData;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check Port Valid */\n    RTK_CHK_PORT_VALID(port);\n\n    if(NULL == pRate)\n        return RT_ERR_NULL_POINTER;\n\n    if(NULL == pIfg_include)\n        return RT_ERR_NULL_POINTER;\n\n    if ((retVal = rtl8367c_getAsicPortEgressRate(rtk_switch_port_L2P_get(port), &regData)) != RT_ERR_OK)\n        return retVal;\n\n    *pRate = regData << 3;\n\n    if ((retVal = rtl8367c_getAsicPortEgressRateIfg((rtk_uint32*)pIfg_include)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n\n/* Function Name:\n *      rtk_rate_egrQueueBwCtrlEnable_get\n * Description:\n *      Get enable status of egress bandwidth control on specified queue.\n * Input:\n *      unit    - unit id\n *      port    - port id\n *      queue   - queue id\n * Output:\n *      pEnable - Pointer to enable status of egress queue bandwidth control\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n *      RT_ERR_PORT_ID          - invalid port id\n *      RT_ERR_QUEUE_ID         - invalid queue id\n *      RT_ERR_NULL_POINTER     - input parameter may be null pointer\n * Note:\n *      None\n */\nrtk_api_ret_t rtk_rate_egrQueueBwCtrlEnable_get(rtk_port_t port, rtk_qid_t queue, rtk_enable_t *pEnable)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check Port Valid */\n    RTK_CHK_PORT_VALID(port);\n\n    /*for whole port function, the queue value should be 0xFF*/\n    if (queue != RTK_WHOLE_SYSTEM)\n        return RT_ERR_QUEUE_ID;\n\n    if(NULL == pEnable)\n        return RT_ERR_NULL_POINTER;\n\n    if ((retVal = rtl8367c_getAsicAprEnable(rtk_switch_port_L2P_get(port),pEnable))!=RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_rate_egrQueueBwCtrlEnable_set\n * Description:\n *      Set enable status of egress bandwidth control on specified queue.\n * Input:\n *      port   - port id\n *      queue  - queue id\n *      enable - enable status of egress queue bandwidth control\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n *      RT_ERR_PORT_ID          - invalid port id\n *      RT_ERR_QUEUE_ID         - invalid queue id\n *      RT_ERR_INPUT            - invalid input parameter\n * Note:\n *      None\n */\nrtk_api_ret_t rtk_rate_egrQueueBwCtrlEnable_set(rtk_port_t port, rtk_qid_t queue, rtk_enable_t enable)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check Port Valid */\n    RTK_CHK_PORT_VALID(port);\n\n    /*for whole port function, the queue value should be 0xFF*/\n    if (queue != RTK_WHOLE_SYSTEM)\n        return RT_ERR_QUEUE_ID;\n\n    if (enable>=RTK_ENABLE_END)\n        return RT_ERR_INPUT;\n\n    if ((retVal = rtl8367c_setAsicAprEnable(rtk_switch_port_L2P_get(port), enable))!=RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_rate_egrQueueBwCtrlRate_get\n * Description:\n *      Get rate of egress bandwidth control on specified queue.\n * Input:\n *      port  - port id\n *      queue - queue id\n *      pIndex - shared meter index\n * Output:\n *      pRate - pointer to rate of egress queue bandwidth control\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n *      RT_ERR_PORT_ID          - invalid port id\n *      RT_ERR_QUEUE_ID         - invalid queue id\n *      RT_ERR_FILTER_METER_ID  - Invalid meter id\n * Note:\n *    The actual rate control is set in shared meters.\n *    The unit of granularity is 8Kbps.\n */\nrtk_api_ret_t rtk_rate_egrQueueBwCtrlRate_get(rtk_port_t port, rtk_qid_t queue, rtk_meter_id_t *pIndex)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32 offset_idx;\n    rtk_uint32 phy_port;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check Port Valid */\n    RTK_CHK_PORT_VALID(port);\n\n    if (queue >= RTK_MAX_NUM_OF_QUEUE)\n        return RT_ERR_QUEUE_ID;\n\n    if(NULL == pIndex)\n        return RT_ERR_NULL_POINTER;\n\n    phy_port = rtk_switch_port_L2P_get(port);\n    if ((retVal=rtl8367c_getAsicAprMeter(phy_port, queue,&offset_idx))!=RT_ERR_OK)\n        return retVal;\n\n    *pIndex = offset_idx + ((phy_port%4)*8);\n\n     return RT_ERR_OK;\n}\n\n\n/* Function Name:\n *      rtk_rate_egrQueueBwCtrlRate_set\n * Description:\n *      Set rate of egress bandwidth control on specified queue.\n * Input:\n *      port  - port id\n *      queue - queue id\n *      index - shared meter index\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n *      RT_ERR_PORT_ID          - invalid port id\n *      RT_ERR_QUEUE_ID         - invalid queue id\n *      RT_ERR_FILTER_METER_ID  - Invalid meter id\n * Note:\n *    The actual rate control is set in shared meters.\n *    The unit of granularity is 8Kbps.\n */\nrtk_api_ret_t rtk_rate_egrQueueBwCtrlRate_set(rtk_port_t port, rtk_qid_t queue, rtk_meter_id_t index)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32 offset_idx;\n    rtk_uint32 phy_port;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check Port Valid */\n    RTK_CHK_PORT_VALID(port);\n\n    if (queue >= RTK_MAX_NUM_OF_QUEUE)\n        return RT_ERR_QUEUE_ID;\n\n    if (index > RTK_MAX_METER_ID)\n        return RT_ERR_FILTER_METER_ID;\n\n    phy_port = rtk_switch_port_L2P_get(port);\n    if (index < ((phy_port%4)*8) ||  index > (7 + (phy_port%4)*8))\n        return RT_ERR_FILTER_METER_ID;\n\n    offset_idx = index - ((phy_port%4)*8);\n\n    if ((retVal=rtl8367c_setAsicAprMeter(phy_port,queue,offset_idx))!=RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rldp.c",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * $Revision: 76306 $\n * $Date: 2017-03-08 15:13:58 +0800 (gT, 08 T 2017) $\n *\n * Purpose : Declaration of RLDP and RLPP API\n *\n * Feature : The file have include the following module and sub-modules\n *           1) RLDP and RLPP configuration and status\n *\n */\n\n\n/*\n * Include Files\n */\n#include <rtk_switch.h>\n#include <rtk_error.h>\n//#include <rtk_types.h>\n#include <rldp.h>\n\n#include <rtl8367c_asicdrv.h>\n#include <rtl8367c_asicdrv_rldp.h>\n\n/*\n * Symbol Definition\n */\n\n\n/*\n * Data Declaration\n */\n\n\n/*\n * Macro Declaration\n */\n\n\n/*\n * Function Declaration\n */\n\n/* Module Name : RLDP */\n\n/* Function Name:\n *      rtk_rldp_config_set\n * Description:\n *      Set RLDP module configuration\n * Input:\n *      pConfig - configuration structure of RLDP\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n *      RT_ERR_INPUT\n *      RT_ERR_NULL_POINTER\n * Note:\n *      None\n */\nrtk_api_ret_t rtk_rldp_config_set(rtk_rldp_config_t *pConfig)\n{\n    rtk_api_ret_t retVal;\n    ether_addr_t magic;\n    rtk_uint32 pmsk;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if (pConfig->rldp_enable >= RTK_ENABLE_END)\n        return RT_ERR_INPUT;\n\n    if (pConfig->trigger_mode >= RTK_RLDP_TRIGGER_END)\n        return RT_ERR_INPUT;\n\n    if (pConfig->compare_type >= RTK_RLDP_CMPTYPE_END)\n        return RT_ERR_INPUT;\n\n    if (pConfig->num_check >= RTK_RLDP_NUM_MAX)\n        return RT_ERR_INPUT;\n\n    if (pConfig->interval_check >= RTK_RLDP_INTERVAL_MAX)\n        return RT_ERR_INPUT;\n\n    if (pConfig->num_loop >= RTK_RLDP_NUM_MAX)\n        return RT_ERR_INPUT;\n\n    if (pConfig->interval_loop >= RTK_RLDP_INTERVAL_MAX)\n        return RT_ERR_INPUT;\n\n    if ((retVal = rtl8367c_getAsicRldpTxPortmask(&pmsk))!=RT_ERR_OK)\n        return retVal;\n\n    if ((retVal = rtl8367c_setAsicRldpTxPortmask(0x00))!=RT_ERR_OK)\n        return retVal;\n\n    if ((retVal = rtl8367c_setAsicRldpTxPortmask(pmsk))!=RT_ERR_OK)\n        return retVal;\n\n    if ((retVal = rtl8367c_setAsicRldp(pConfig->rldp_enable))!=RT_ERR_OK)\n        return retVal;\n\n    if ((retVal = rtl8367c_setAsicRldpTriggerMode(pConfig->trigger_mode))!=RT_ERR_OK)\n        return retVal;\n\n    memcpy(&magic, &pConfig->magic, sizeof(ether_addr_t));\n    if ((retVal = rtl8367c_setAsicRldpMagicNum(magic))!=RT_ERR_OK)\n        return retVal;\n\n    if ((retVal = rtl8367c_setAsicRldpCompareRandomNumber(pConfig->compare_type))!=RT_ERR_OK)\n        return retVal;\n\n    if ((retVal = rtl8367c_setAsicRldpCompareRandomNumber(pConfig->compare_type))!=RT_ERR_OK)\n        return retVal;\n\n    if ((retVal = rtl8367c_setAsicRldpCheckingStatePara(pConfig->num_check, pConfig->interval_check))!=RT_ERR_OK)\n        return retVal;\n\n    if ((retVal = rtl8367c_setAsicRldpLoopStatePara(pConfig->num_loop, pConfig->interval_loop))!=RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n\n/* Function Name:\n *      rtk_rldp_config_get\n * Description:\n *      Get RLDP module configuration\n * Input:\n *      None\n * Output:\n *      pConfig - configuration structure of RLDP\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n *      RT_ERR_INPUT\n *      RT_ERR_NULL_POINTER\n * Note:\n *      None\n */\nrtk_api_ret_t rtk_rldp_config_get(rtk_rldp_config_t *pConfig)\n{\n    rtk_api_ret_t retVal;\n    ether_addr_t magic;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if ((retVal = rtl8367c_getAsicRldp(&pConfig->rldp_enable))!=RT_ERR_OK)\n        return retVal;\n\n    if ((retVal = rtl8367c_getAsicRldpTriggerMode(&pConfig->trigger_mode))!=RT_ERR_OK)\n        return retVal;\n\n    if ((retVal = rtl8367c_getAsicRldpMagicNum(&magic))!=RT_ERR_OK)\n        return retVal;\n    memcpy(&pConfig->magic, &magic, sizeof(ether_addr_t));\n\n    if ((retVal = rtl8367c_getAsicRldpCompareRandomNumber(&pConfig->compare_type))!=RT_ERR_OK)\n        return retVal;\n\n    if ((retVal = rtl8367c_getAsicRldpCompareRandomNumber(&pConfig->compare_type))!=RT_ERR_OK)\n        return retVal;\n\n    if ((retVal = rtl8367c_getAsicRldpCheckingStatePara(&pConfig->num_check, &pConfig->interval_check))!=RT_ERR_OK)\n        return retVal;\n\n    if ((retVal = rtl8367c_getAsicRldpLoopStatePara(&pConfig->num_loop, &pConfig->interval_loop))!=RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n\n/* Function Name:\n *      rtk_rldp_portConfig_set\n * Description:\n *      Set per port RLDP module configuration\n * Input:\n *      port   - port number to be configured\n *      pPortConfig - per port configuration structure of RLDP\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n *      RT_ERR_INPUT\n *      RT_ERR_NULL_POINTER\n * Note:\n *      None\n */\nrtk_api_ret_t rtk_rldp_portConfig_set(rtk_port_t port, rtk_rldp_portConfig_t *pPortConfig)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32 pmsk;\n    rtk_uint32 phy_port;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check Port Valid */\n    RTK_CHK_PORT_VALID(port);\n\n    if (pPortConfig->tx_enable>= RTK_ENABLE_END)\n        return RT_ERR_INPUT;\n\n    phy_port = rtk_switch_port_L2P_get(port);\n\n    if ((retVal = rtl8367c_getAsicRldpTxPortmask(&pmsk))!=RT_ERR_OK)\n        return retVal;\n\n    if (pPortConfig->tx_enable)\n    {\n         pmsk |=(1<<phy_port);\n    }\n    else\n    {\n         pmsk &= ~(1<<phy_port);\n    }\n\n    if ((retVal = rtl8367c_setAsicRldpTxPortmask(pmsk))!=RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n\n} /* end of rtk_rldp_portConfig_set */\n\n\n/* Function Name:\n *      rtk_rldp_portConfig_get\n * Description:\n *      Get per port RLDP module configuration\n * Input:\n *      port    - port number to be get\n * Output:\n *      pPortConfig - per port configuration structure of RLDP\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n *      RT_ERR_INPUT\n *      RT_ERR_NULL_POINTER\n * Note:\n *      None\n */\nrtk_api_ret_t rtk_rldp_portConfig_get(rtk_port_t port, rtk_rldp_portConfig_t *pPortConfig)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32 pmsk;\n    rtk_portmask_t logicalPmask;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check Port Valid */\n    RTK_CHK_PORT_VALID(port);\n\n    if ((retVal = rtl8367c_getAsicRldpTxPortmask(&pmsk))!=RT_ERR_OK)\n        return retVal;\n\n    if ((retVal = rtk_switch_portmask_P2L_get(pmsk, &logicalPmask)) != RT_ERR_OK)\n        return retVal;\n\n\n    if (logicalPmask.bits[0] & (1<<port))\n    {\n         pPortConfig->tx_enable = ENABLED;\n    }\n    else\n    {\n         pPortConfig->tx_enable = DISABLED;\n    }\n\n    return RT_ERR_OK;\n} /* end of rtk_rldp_portConfig_get */\n\n\n/* Function Name:\n *      rtk_rldp_status_get\n * Description:\n *      Get RLDP module status\n * Input:\n *      None\n * Output:\n *      pStatus - status structure of RLDP\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n *      RT_ERR_NULL_POINTER\n * Note:\n *      None\n */\nrtk_api_ret_t rtk_rldp_status_get(rtk_rldp_status_t *pStatus)\n{\n    rtk_api_ret_t retVal;\n    ether_addr_t seed;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if ((retVal = rtl8367c_getAsicRldpRandomNumber(&seed))!=RT_ERR_OK)\n        return retVal;\n    memcpy(&pStatus->id, &seed, sizeof(ether_addr_t));\n\n    return RT_ERR_OK;\n} /* end of rtk_rldp_status_get */\n\n\n/* Function Name:\n *      rtk_rldp_portStatus_get\n * Description:\n *      Get RLDP module status\n * Input:\n *      port    - port number to be get\n * Output:\n *      pPortStatus - per port status structure of RLDP\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n *      RT_ERR_INPUT\n *      RT_ERR_NULL_POINTER\n * Note:\n *      None\n */\nrtk_api_ret_t rtk_rldp_portStatus_get(rtk_port_t port, rtk_rldp_portStatus_t *pPortStatus)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32 pmsk;\n    rtk_portmask_t logicalPmask;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check Port Valid */\n    RTK_CHK_PORT_VALID(port);\n\n    if ((retVal = rtl8367c_getAsicRldpLoopedPortmask(&pmsk))!=RT_ERR_OK)\n        return retVal;\n    if ((retVal = rtk_switch_portmask_P2L_get(pmsk, &logicalPmask)) != RT_ERR_OK)\n        return retVal;\n\n    if (logicalPmask.bits[0] & (1<<port))\n    {\n         pPortStatus->loop_status = RTK_RLDP_LOOPSTS_LOOPING;\n    }\n    else\n    {\n         pPortStatus->loop_status  = RTK_RLDP_LOOPSTS_NONE;\n    }\n\n    if ((retVal = rtl8367c_getAsicRldpEnterLoopedPortmask(&pmsk))!=RT_ERR_OK)\n        return retVal;\n    if ((retVal = rtk_switch_portmask_P2L_get(pmsk, &logicalPmask)) != RT_ERR_OK)\n        return retVal;\n\n    if (logicalPmask.bits[0] & (1<<port))\n    {\n         pPortStatus->loop_enter = RTK_RLDP_LOOPSTS_LOOPING;\n    }\n    else\n    {\n         pPortStatus->loop_enter  = RTK_RLDP_LOOPSTS_NONE;\n    }\n\n    if ((retVal = rtl8367c_getAsicRldpLeaveLoopedPortmask(&pmsk))!=RT_ERR_OK)\n        return retVal;\n    if ((retVal = rtk_switch_portmask_P2L_get(pmsk, &logicalPmask)) != RT_ERR_OK)\n        return retVal;\n\n    if (logicalPmask.bits[0] & (1<<port))\n    {\n         pPortStatus->loop_leave = RTK_RLDP_LOOPSTS_LOOPING;\n    }\n    else\n    {\n         pPortStatus->loop_leave  = RTK_RLDP_LOOPSTS_NONE;\n    }\n\n    return RT_ERR_OK;\n}\n\n\n/* Function Name:\n *      rtk_rldp_portStatus_clear\n * Description:\n *      Clear RLDP module status\n * Input:\n *      port    - port number to be clear\n *      pPortStatus - per port status structure of RLDP\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n *      RT_ERR_INPUT\n *      RT_ERR_NULL_POINTER\n * Note:\n *      Clear operation effect loop_enter and loop_leave only, other field in\n *      the structure are don't care. Loop status cab't be clean.\n */\nrtk_api_ret_t rtk_rldp_portStatus_set(rtk_port_t port, rtk_rldp_portStatus_t *pPortStatus)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32 pmsk;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check Port Valid */\n    RTK_CHK_PORT_VALID(port);\n\n    pmsk = (pPortStatus->loop_enter)<<rtk_switch_port_L2P_get(port);\n    if ((retVal = rtl8367c_setAsicRldpEnterLoopedPortmask(pmsk))!=RT_ERR_OK)\n        return retVal;\n\n    pmsk = (pPortStatus->loop_leave)<<rtk_switch_port_L2P_get(port);\n    if ((retVal = rtl8367c_setAsicRldpLeaveLoopedPortmask(pmsk))!=RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_rldp_portLoopPair_get\n * Description:\n *      Get RLDP port loop pairs\n * Input:\n *      port    - port number to be get\n * Output:\n *      pPortmask - per port related loop ports\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n *      RT_ERR_INPUT\n *      RT_ERR_NULL_POINTER\n * Note:\n *      None\n */\nrtk_api_ret_t rtk_rldp_portLoopPair_get(rtk_port_t port, rtk_portmask_t *pPortmask)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32 pmsk;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check Port Valid */\n    RTK_CHK_PORT_VALID(port);\n\n    if ((retVal = rtl8367c_getAsicRldpLoopedPortPair(rtk_switch_port_L2P_get(port), &pmsk))!=RT_ERR_OK)\n        return retVal;\n\n    if ((retVal = rtk_switch_portmask_P2L_get(pmsk, pPortmask)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n\n\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtk_hal.c",
    "content": "#include <linux/kernel.h>\n#include <linux/delay.h>\n#include  \"./include/rtk_switch.h\"\n#include  \"./include/vlan.h\"\n#include  \"./include/port.h\"\n#include  \"./include/rate.h\"\n#include  \"./include/rtk_hal.h\"\n#include  \"./include/l2.h\"\n#include  \"./include/stat.h\"\n#include  \"./include/igmp.h\"\n#include  \"./include/trap.h\"\n#include  \"./include/leaky.h\"\n#include  \"./include/mirror.h\"\n#include  \"./include/rtl8367c_asicdrv_port.h\"\n#include  \"./include/rtl8367c_asicdrv_mib.h\"\n#include  \"./include/smi.h\"\n#include  \"./include/qos.h\"\n#include  \"./include/trunk.h\"\n\nvoid rtk_hal_switch_init(void)\n{\n\tif(rtk_switch_init() != 0)\n        printk(\"rtk_switch_init failed\\n\");\n\tmdelay(500);\n\t/*vlan init */\n\tif (rtk_vlan_init() != 0)\n        printk(\"rtk_vlan_init failed\\n\");\n}\n\nvoid rtk_hal_dump_full_mib(void)\n{\n\trtk_port_t port;\n\trtk_stat_counter_t Cntr;\n\trtk_stat_port_type_t cntr_idx;\n\n\tfor (port = UTP_PORT0; port < (UTP_PORT0 + 5); port++) {\n\t\tprintk(\"\\nPort%d\\n\", port);\n\t\tfor (cntr_idx = STAT_IfInOctets; cntr_idx < STAT_PORT_CNTR_END; cntr_idx ++) {\n\t\t\trtk_stat_port_get(port, cntr_idx, &Cntr);\n\t\t\tprintk(\"%8llu \", Cntr);\n\t\t\tif (((cntr_idx%10) == 9))\n\t\t\t\tprintk(\"\\n\");\n\t\t}\n\t}\n\n\tfor (port = EXT_PORT0; port < (EXT_PORT0 + 2); port++) {\n\t\tprintk(\"\\nPort%d\\n\", port);\n\t\tfor (cntr_idx = STAT_IfInOctets; cntr_idx < STAT_PORT_CNTR_END; cntr_idx ++) {\n\t\t\trtk_stat_port_get(port, cntr_idx, &Cntr);\n\t\t\tprintk(\"%8llu \", Cntr);\n\t\t\tif (((cntr_idx%10) == 9))\n\t\t\t\tprintk(\"\\n\");\n\t\t}\n\t}\n\trtk_stat_global_reset();\n}\nvoid rtk_dump_mib_type(rtk_stat_port_type_t cntr_idx)\n{\n\trtk_port_t port;\n\trtk_stat_counter_t Cntr;\n\n\tfor (port = UTP_PORT0; port < (UTP_PORT0 + 5); port++) {\n\t\trtk_stat_port_get(port, cntr_idx, &Cntr);\n\t\tprintk(\"%8llu\", Cntr);\n\t}\n\tfor (port = EXT_PORT0; port < (EXT_PORT0 + 2); port++) {\n\t\trtk_stat_port_get(port, cntr_idx, &Cntr);\n\t\tprintk(\"%8llu\", Cntr);\n\t}\n\tprintk(\"\\n\");\n}\n\nvoid rtk_hal_dump_mib(void)\n{\n\n\tprintk(\"==================%8s%8s%8s%8s%8s%8s%8s\\n\", \"Port0\", \"Port1\",\n\t       \"Port2\", \"Port3\", \"Port4\", \"Port16\", \"Port17\");\n\t/* Get TX Unicast Pkts */\n\tprintk(\"TX Unicast Pkts  :\");\n\trtk_dump_mib_type(STAT_IfOutUcastPkts);\n\t/* Get TX Multicast Pkts */\n\tprintk(\"TX Multicast Pkts:\");\n\trtk_dump_mib_type(STAT_IfOutMulticastPkts);\n\t/* Get TX BroadCast Pkts */\n\tprintk(\"TX BroadCast Pkts:\");\n\trtk_dump_mib_type(STAT_IfOutBroadcastPkts);\n\t/* Get TX Collisions */\n\t/* Get TX Puase Frames */\n\tprintk(\"TX Pause Frames  :\");\n\trtk_dump_mib_type(STAT_Dot3OutPauseFrames);\n\t/* Get TX Drop Events */\n\t/* Get RX Unicast Pkts */\n\tprintk(\"RX Unicast Pkts  :\");\n\trtk_dump_mib_type(STAT_IfInUcastPkts);\n\t/* Get RX Multicast Pkts */\n\tprintk(\"RX Multicast Pkts:\");\n\trtk_dump_mib_type(STAT_IfInMulticastPkts);\n\t/* Get RX Broadcast Pkts */\n\tprintk(\"RX Broadcast Pkts:\");\n\trtk_dump_mib_type(STAT_IfInBroadcastPkts);\n\t/* Get RX FCS Erros */\n\tprintk(\"RX FCS Errors    :\");\n\trtk_dump_mib_type(STAT_Dot3StatsFCSErrors);\n\t/* Get RX Undersize Pkts */\n\tprintk(\"RX Undersize Pkts:\");\n\trtk_dump_mib_type(STAT_EtherStatsUnderSizePkts);\n\t/* Get RX Discard Pkts */\n\tprintk(\"RX Discard Pkts  :\");\n\trtk_dump_mib_type(STAT_Dot1dTpPortInDiscards);\n\t/* Get RX Fragments */\n\tprintk(\"RX Fragments     :\");\n\trtk_dump_mib_type(STAT_EtherStatsFragments);\n\t/* Get RX Oversize Pkts */\n\tprintk(\"RX Oversize Pkts :\");\n\trtk_dump_mib_type(STAT_EtherOversizeStats);\n\t/* Get RX Jabbers */\n\tprintk(\"RX Jabbers       :\");\n\trtk_dump_mib_type(STAT_EtherStatsJabbers);\n\t/* Get RX Pause Frames */\n\tprintk(\"RX Pause Frames  :\");\n\trtk_dump_mib_type(STAT_Dot3InPauseFrames);\n\t/* clear MIB */\n\trtk_stat_global_reset();\n}\nEXPORT_SYMBOL(rtk_hal_dump_mib);\n\nint rtk_hal_dump_vlan(void)\n{\n\trtk_vlan_cfg_t vlan;\n\tint i;\n\n\tprintk(\"vid    portmap\\n\");\n\tfor (i = 0; i < RTK_SW_VID_RANGE; i++) {\n\t\trtk_vlan_get(i, &vlan);\n\t\tprintk(\"%3d    \", i);\n\t\tprintk(\"%c\",\n\t\t       RTK_PORTMASK_IS_PORT_SET(vlan.mbr,\n\t\t\t\t\t\tUTP_PORT0) ? '1' : '-');\n\t\tprintk(\"%c\",\n\t\t       RTK_PORTMASK_IS_PORT_SET(vlan.mbr,\n\t\t\t\t\t\tUTP_PORT1) ? '1' : '-');\n\t\tprintk(\"%c\",\n\t\t       RTK_PORTMASK_IS_PORT_SET(vlan.mbr,\n\t\t\t\t\t\tUTP_PORT2) ? '1' : '-');\n\t\tprintk(\"%c\",\n\t\t       RTK_PORTMASK_IS_PORT_SET(vlan.mbr,\n\t\t\t\t\t\tUTP_PORT3) ? '1' : '-');\n\t\tprintk(\"%c\",\n\t\t       RTK_PORTMASK_IS_PORT_SET(vlan.mbr,\n\t\t\t\t\t\tUTP_PORT4) ? '1' : '-');\n\t\tprintk(\"%c\",\n\t\t       RTK_PORTMASK_IS_PORT_SET(vlan.mbr,\n\t\t\t\t\t\tEXT_PORT0) ? '1' : '-');\n\t\tprintk(\"%c\",\n\t\t       RTK_PORTMASK_IS_PORT_SET(vlan.mbr,\n\t\t\t\t\t\tEXT_PORT1) ? '1' : '-');\n\t\tprintk(\"\\n\");\n\t}\n\treturn 0;\n}\n\nvoid rtk_hal_clear_vlan(void)\n{\n\trtk_api_ret_t ret;\n\n\tret =  rtk_vlan_reset();\n    if (ret != RT_ERR_OK)\n        printk(\"rtk_vlan_reset failed\\n\");\n}\n\nint rtk_hal_set_vlan(struct ra_switch_ioctl_data *data)\n{\n\trtk_vlan_cfg_t vlan;\n\trtk_api_ret_t ret;\n\tint i;\n\n\t/* clear vlan entry first */\n\tmemset(&vlan, 0x00, sizeof(rtk_vlan_cfg_t));\n\tRTK_PORTMASK_CLEAR(vlan.mbr);\n\tRTK_PORTMASK_CLEAR(vlan.untag);\n\trtk_vlan_set(data->vid, &vlan);\n\n\tmemset(&vlan, 0x00, sizeof(rtk_vlan_cfg_t));\n\tfor (i = 0; i < 5; i++) {\n\t\tif (data->port_map & (1 << i)) {\n\t\t\tRTK_PORTMASK_PORT_SET(vlan.mbr, i);\n\t\t\tRTK_PORTMASK_PORT_SET(vlan.untag, i);\n\t\t\trtk_vlan_portPvid_set(i, data->vid, 0);\n\t\t}\n\t}\n\tfor (i = 0; i < 2; i++) {\n\t\tif (data->port_map & (1 << (i + 5))) {\n\t\t\tRTK_PORTMASK_PORT_SET(vlan.mbr, (i + EXT_PORT0));\n\t\t\tRTK_PORTMASK_PORT_SET(vlan.untag, (i + EXT_PORT0));\n\t\t\trtk_vlan_portPvid_set((i + EXT_PORT0), data->vid, 0);\n\t\t}\n\t}\n\tvlan.ivl_en = 1;\n\tret = rtk_vlan_set(data->vid, &vlan);\n\n\treturn 0;\n}\n\nvoid rtk_hal_vlan_portpvid_set(rtk_port_t port, rtk_vlan_t pvid, rtk_pri_t priority)\n{\n\trtk_vlan_portPvid_set(port, pvid, priority);\n}\n\nint rtk_hal_set_ingress_rate(struct ra_switch_ioctl_data *data)\n{\n\trtk_api_ret_t ret;\n\n\tif (data->on_off == 1)\n\t\tret =\n\t\t    rtk_rate_igrBandwidthCtrlRate_set(data->port, data->bw, 0,\n\t\t\t\t\t\t      1);\n\telse\n\t\tret =\n\t\t    rtk_rate_igrBandwidthCtrlRate_set(data->port, 1048568, 0,\n\t\t\t\t\t\t      1);\n\n\treturn ret;\n}\n\nint rtk_hal_set_egress_rate(struct ra_switch_ioctl_data *data)\n{\n\trtk_api_ret_t ret;\n\n\tif (data->on_off == 1)\n\t\tret =\n\t\t    rtk_rate_egrBandwidthCtrlRate_set(data->port, data->bw, 1);\n\telse\n\t\tret = rtk_rate_egrBandwidthCtrlRate_set(data->port, 1048568, 1);\n\n\treturn ret;\n}\n\nvoid rtk_hal_dump_table(void)\n{\n\trtk_uint32 i;\n\trtk_uint32 address = 0;\n\trtk_l2_ucastAddr_t l2_data;\n\trtk_l2_ipMcastAddr_t ipMcastAddr;\n\n\tprintk(\"hash  port(0:17)   fid   vid  mac-address\\n\");\n\twhile (1) {\n\t\tif (rtk_l2_addr_next_get(READMETHOD_NEXT_L2UC, UTP_PORT0, &address, &l2_data) != RT_ERR_OK) {\n\t\t\tbreak;\n\t\t} else {\n\t\t\tprintk(\"%03x   \", l2_data.address);\n\t\t\tfor (i = 0; i < 5; i++)\n\t\t\t\tif ( l2_data.port == i)\n\t\t\t\t\tprintk(\"1\");\n\t\t\t\telse\n\t\t\t\t\tprintk(\"-\");\n\t\t\tfor (i = 16; i < 18; i++)\n\t\t\t\tif ( l2_data.port == i)\n\t\t\t\t\tprintk(\"1\");\n\t\t\t\telse\n\t\t\t\t\tprintk(\"-\");\n\n\t\t\tprintk(\"      %2d\", l2_data.fid);\n\t\t\tprintk(\"  %4d\", l2_data.cvid);\n\t\t\tprintk(\"  %02x%02x%02x%02x%02x%02x\\n\", l2_data.mac.octet[0],\n\t\t\tl2_data.mac.octet[1], l2_data.mac.octet[2], l2_data.mac.octet[3], \n\t\t\tl2_data.mac.octet[4], l2_data.mac.octet[5]);\n\t\t\taddress ++;\n\t\t\t}\n\t}\n\n\taddress = 0;\n\twhile (1) {\n        if (rtk_l2_ipMcastAddr_next_get(&address, &ipMcastAddr) != RT_ERR_OK) {\n            break;\n        } else {\n            printk(\"%03x   \", ipMcastAddr.address);\n            for (i = 0; i < 5; i++)\n                printk(\"%c\", RTK_PORTMASK_IS_PORT_SET(ipMcastAddr.portmask, i) ? '1' : '-');\n            for (i = 16; i < 18; i++)\n                printk(\"%c\", RTK_PORTMASK_IS_PORT_SET(ipMcastAddr.portmask, i) ? '1' : '-');\n\t\t\tprintk(\"                \");\n\t\t\tprintk(\"01005E%06x\\n\", (ipMcastAddr.dip & 0xefffff));\n            address ++;\n            }\n    }\n}\n\nvoid rtk_hal_clear_table(void)\n{\n\trtk_api_ret_t ret;\n\n\tret = rtk_l2_table_clear();\n\tif (ret != RT_ERR_OK)\n\t\tprintk(\"rtk_l2_table_clear failed\\n\");\n}\n\nvoid rtk_hal_add_table(struct ra_switch_ioctl_data *data)\n{\n\trtk_api_ret_t ret;\n\trtk_l2_ucastAddr_t l2_entry;\n\trtk_mac_t mac;\n\n\tmac.octet[0] =data->mac[0];\n\tmac.octet[1] =data->mac[1];\n\tmac.octet[2] =data->mac[2];\n\tmac.octet[3] =data->mac[3];\n\tmac.octet[4] =data->mac[4];\n\tmac.octet[5] =data->mac[5];\n\n\tmemset(&l2_entry, 0x00, sizeof(rtk_l2_ucastAddr_t));\n\tl2_entry.port = data->port;\n\tl2_entry.ivl = 1;\n\tl2_entry.cvid = data->vid;\n\tl2_entry.fid = 0;\n\tl2_entry.efid = 0;\n\tl2_entry.is_static = 1;\n\tret = rtk_l2_addr_add(&mac, &l2_entry);\n\tif (ret != RT_ERR_OK)\n\t\tprintk(\"rtk_hal_add_table failed\\n\");\n}\n\nvoid rtk_hal_del_table(struct ra_switch_ioctl_data *data)\n{\n\trtk_api_ret_t ret;\n\trtk_l2_ucastAddr_t l2_entry;\n\trtk_mac_t mac;\n\n\tmac.octet[0] =data->mac[0];\n\tmac.octet[1] =data->mac[1];\n\tmac.octet[2] =data->mac[2];\n\tmac.octet[3] =data->mac[3];\n\tmac.octet[4] =data->mac[4];\n\tmac.octet[5] =data->mac[5];\n\n\tmemset(&l2_entry, 0x00, sizeof(rtk_l2_ucastAddr_t));\n\tl2_entry.port = data->port;\n\tl2_entry.ivl = 1;\n\tl2_entry.cvid = data->vid;\n\tl2_entry.fid = 0;\n\tl2_entry.efid = 0;\n\tret = rtk_l2_addr_del(&mac, &l2_entry);\n\tif (ret != RT_ERR_OK)\n\t\tprintk(\"rtk_hal_add_table failed\\n\");\n}\nvoid rtk_hal_get_phy_status(struct ra_switch_ioctl_data *data)\n{\n\trtk_port_linkStatus_t linkStatus;\n\trtk_port_speed_t speed;\n\trtk_port_duplex_t duplex;\n\n    rtk_port_phyStatus_get(data->port, &linkStatus, &speed, &duplex);\n    printk(\"Port%d Status:\\n\", data->port);\n\tif (linkStatus == 1) {\n        printk(\"Link Up\");\n        if (speed == 0)\n\t\t\tprintk(\" 10M\");\n\t\telse if (speed == 1)\n\t\t\tprintk(\" 100M\");\n\t\telse if (speed == 2)\n            printk(\" 1000M\");\n        if (duplex == 0)\n\t\t\tprintk(\" Half Duplex\\n\");\n\t\telse\n\t\t\tprintk(\" Full Duplex\\n\");\n\t} else\n\t\tprintk(\"Link Down\\n\");\n\n}\n\nvoid rtk_hal_set_port_mirror(struct ra_switch_ioctl_data *data)\n{\n\trtk_portmask_t rx_portmask;\n\trtk_portmask_t tx_portmask;\n\trtk_api_ret_t ret;\n\tint i;\n\n\trtk_mirror_portIso_set(ENABLED);\n\tRTK_PORTMASK_CLEAR(rx_portmask);\n\tRTK_PORTMASK_CLEAR(tx_portmask);\n    for (i = 0; i < 5; i++)\n\t\tif (data->rx_port_map & (1 << i))\n\t\t\tRTK_PORTMASK_PORT_SET(rx_portmask, i);\n\tfor (i = 0; i < 2; i++)\n\t\tif (data->rx_port_map & (1 << (i + 5)))\n\t\t\tRTK_PORTMASK_PORT_SET(rx_portmask, (i + EXT_PORT0));\n\n\tRTK_PORTMASK_CLEAR(tx_portmask);\n    for (i = 0; i < 5; i++)\n        if (data->tx_port_map & (1 << i))\n            RTK_PORTMASK_PORT_SET(tx_portmask, i);\n    for (i = 0; i < 2; i++)\n        if (data->tx_port_map & (1 << (i + 5)))\n            RTK_PORTMASK_PORT_SET(tx_portmask, (i + EXT_PORT0));\n\n    ret = rtk_mirror_portBased_set(data->port, &rx_portmask, &tx_portmask);\n\tif (!ret)\n\t\tprintk(\"rtk_mirror_portBased_set success\\n\");\n}\n\nvoid rtk_hal_read_reg(struct ra_switch_ioctl_data *data)\n{\n\tret_t retVal;\n\n\tretVal = smi_read(data->reg_addr, &data->reg_val);\n\tif(retVal != RT_ERR_OK)\n\t\tprintk(\"switch reg read failed\\n\");\n\telse\n\t\tprintk(\"reg0x%x = 0x%x\\n\", data->reg_addr, data->reg_val);\n}\n\nvoid rtk_hal_write_reg(struct ra_switch_ioctl_data *data)\n{\n\tret_t retVal;\n\n    retVal = smi_write(data->reg_addr, data->reg_val);\n    if(retVal != RT_ERR_OK)\n        printk(\"switch reg write failed\\n\");\n    else\n        printk(\"write switch reg0x%x 0x%x success\\n\", data->reg_addr, data->reg_val);\n}\n\nvoid rtk_hal_get_phy_reg(struct ra_switch_ioctl_data *data)\n{\n\tret_t retVal;\n\trtk_port_phy_data_t Data;\n\n\tretVal = rtk_port_phyReg_get(data->port, data->reg_addr, &Data);\n\tif (retVal == RT_ERR_OK)\n\t\tprintk(\"Get: phy[%d].reg[%d] = 0x%04x\\n\", data->port, data->reg_addr, Data);\n\telse\n\t\tprintk(\"read phy reg failed\\n\");\n}\n\nvoid rtk_hal_set_phy_reg(struct ra_switch_ioctl_data *data)\n{\n\tret_t retVal;\n\n\tretVal = rtk_port_phyReg_set(data->port, data->reg_addr, data->reg_val);\n\tif (retVal == RT_ERR_OK)\n\t\tprintk(\"Set: phy[%d].reg[%d] = 0x%04x\\n\", data->port, data->reg_addr, data->reg_val);\n\telse\n\t\tprintk(\"write phy reg failed\\n\");\n}\nvoid rtk_hal_qos_en(struct ra_switch_ioctl_data *data)\n{\n\n\tif (data->on_off == 1) {\n\t\tif (rtk_qos_init(8) != 0)\n\t\t\tprintk(\"rtk_qos_init(8) failed\\n\");\n\t}\n\telse {\n\t\tif (rtk_qos_init(1) != 0)\n            printk(\"rtk_qos_init(1) failed\\n\");\n\t}\n}\n\nvoid rtk_hal_qos_set_table2type(struct ra_switch_ioctl_data *data)\n{\n\trtk_api_ret_t ret;\n\trtk_priority_select_t PriDec;\n\n\t/* write all pri to 0 */\n\tPriDec.port_pri = 0;\n    PriDec.dot1q_pri = 0;\n    PriDec.acl_pri = 0;\n    PriDec.cvlan_pri = 0;\n    PriDec.svlan_pri = 0;\n    PriDec.dscp_pri = 0;\n    PriDec.dmac_pri = 0;\n    PriDec.smac_pri = 0;\n\n\tif (data->qos_type == 0)\n\t\tPriDec.port_pri = 1;\n\telse if (data->qos_type == 1)\n\t\tPriDec.dot1q_pri = 1;\n\telse if (data->qos_type == 2)\n\t\tPriDec.acl_pri = 1;\n\telse if (data->qos_type == 3)\n\t\tPriDec.dscp_pri = 1;\n\telse if (data->qos_type == 4)\n\t\tPriDec.cvlan_pri = 1;\n\telse if (data->qos_type == 5)\n\t\tPriDec.svlan_pri = 1;\n\telse if (data->qos_type == 6)\n\t\tPriDec.dmac_pri = 1;\n\telse if (data->qos_type == 7)\n\t\tPriDec.smac_pri = 1;\n\n\tif (data->qos_table_idx == 0)\n\t\tret = rtk_qos_priSel_set(PRIDECTBL_IDX0, &PriDec);\n\telse\n\t\tret = rtk_qos_priSel_set(PRIDECTBL_IDX1, &PriDec);\n\n\tif (ret != 0)\n\t\tprintk(\"rtk_qos_priSel_set failed\\n\");\n\n}\n\nvoid rtk_hal_qos_get_table2type(struct ra_switch_ioctl_data *data)\n{\n\trtk_api_ret_t ret;\n\trtk_priority_select_t PriDec;\n\n\tif (data->qos_table_idx == 0)\n        ret = rtk_qos_priSel_get(PRIDECTBL_IDX0, &PriDec);\n    else\n        ret = rtk_qos_priSel_get(PRIDECTBL_IDX1, &PriDec);\n\n\tif (ret != 0)\n        printk(\"rtk_qos_priSel_set failed\\n\");\n    else {\n\t\tprintk(\"port_pri  = %d\\n\", PriDec.port_pri);\n\t\tprintk(\"dot1q_pri = %d\\n\", PriDec.dot1q_pri);\n\t\tprintk(\"acl_pri   = %d\\n\", PriDec.acl_pri);\n\t\tprintk(\"dscp_pri  = %d\\n\", PriDec.dscp_pri);\n\t\tprintk(\"cvlan_pri = %d\\n\", PriDec.cvlan_pri);\n\t\tprintk(\"svlan_pri = %d\\n\", PriDec.svlan_pri);\n\t\tprintk(\"dmac_pri  = %d\\n\", PriDec.dmac_pri);\n\t\tprintk(\"smac_pri  = %d\\n\", PriDec.smac_pri);\n\t}\n}\n\nvoid rtk_hal_qos_set_port2table(struct ra_switch_ioctl_data *data)\n{\n\trtk_api_ret_t ret;\n\t\n\tret = rtk_qos_portPriSelIndex_set(data->port, data->qos_table_idx);\n\tif (ret != 0)\n\t\tprintk(\"rtk_qos_portPriSelIndex_set failed\\n\");\n}\n\nvoid rtk_hal_qos_get_port2table(struct ra_switch_ioctl_data *data)\n{\n\trtk_api_ret_t ret;\n\trtk_qos_priDecTbl_t Index;\n\t\n\tret = rtk_qos_portPriSelIndex_get(data->port, &Index);\n\tif (ret != 0)\n\t\tprintk(\"rtk_qos_portPriSelIndex_set failed\\n\");\n\telse\n\t\tprintk(\"port%d belongs to table%d\\n\", data->port, Index);\n}\n\nvoid rtk_hal_qos_set_port2pri(struct ra_switch_ioctl_data *data)\n{\n\trtk_api_ret_t ret;\n\n\tret = rtk_qos_portPri_set(data->port, data->qos_pri);\n\tif (ret != 0)\n\t\tprintk(\"rtk_qos_portPri_set failed\\n\");\n}\n\nvoid rtk_hal_qos_get_port2pri(struct ra_switch_ioctl_data *data)\n{\n\trtk_api_ret_t ret;\n\trtk_pri_t Int_pri;\n\n\tret = rtk_qos_portPri_get(data->port, &Int_pri);\n\tif (ret != 0)\n\t\tprintk(\"rtk_qos_portPri_set failed\\n\");\n\telse\n\t\tprintk(\"port%d priority = %d\\n\", data->port, Int_pri);\n}\n\nvoid rtk_hal_qos_set_dscp2pri(struct ra_switch_ioctl_data *data)\n{\n\trtk_api_ret_t ret;\n\n\tret = rtk_qos_dscpPriRemap_set(data->qos_dscp, data->qos_pri);\n\tif (ret != 0)\n\t\tprintk(\"rtk_qos_dscpPriRemap_set failed\\n\");\n}\n\nvoid rtk_hal_qos_get_dscp2pri(struct ra_switch_ioctl_data *data)\n{\n\trtk_api_ret_t ret;\n\trtk_pri_t Int_pri;\n\n\tret = rtk_qos_dscpPriRemap_get(data->qos_dscp, &Int_pri);\n\tif (ret != 0)\n\t\tprintk(\"rtk_qos_dscpPriRemap_set failed\\n\");\n\telse\n\t\tprintk(\"dscp%d priority is %d\\n\", data->qos_dscp, Int_pri);\n}\n\nvoid rtk_hal_qos_set_pri2queue(struct ra_switch_ioctl_data *data)\n{\n\trtk_api_ret_t ret;\n\trtk_qos_pri2queue_t pri2qid;\n\n\tret = rtk_qos_priMap_get(8, &pri2qid);\n\tpri2qid.pri2queue[data->qos_queue_num] = data->qos_pri;\n\tret = rtk_qos_priMap_set(8, &pri2qid);\n\tif (ret != 0)\n\t\tprintk(\"rtk_qos_priMap_set failed\\n\");\n}\n\nvoid rtk_hal_qos_get_pri2queue(struct ra_switch_ioctl_data *data)\n{\n\tint i;\n\trtk_api_ret_t ret;\n\trtk_qos_pri2queue_t pri2qid;\n\n\tret = rtk_qos_priMap_get(8, &pri2qid);\n\tif (ret != 0)\n\t\tprintk(\"rtk_qos_priMap_get failed\\n\");\n\telse {\n\t\tfor (i = 0; i < 8; i++)\n\t\t\tprintk(\"pri2qid.pri2queue[%d] = %d\\n\", i, pri2qid.pri2queue[i]);\n\t}\n}\n\nvoid rtk_hal_qos_set_queue_weight(struct ra_switch_ioctl_data *data)\n{\n\trtk_api_ret_t ret;\n\trtk_qos_queue_weights_t qweights;\n\n\tret = rtk_qos_schedulingQueue_get(data->port, &qweights);\n\tqweights.weights[data->qos_queue_num] = data->qos_weight;\n\tret = rtk_qos_schedulingQueue_set(data->port, &qweights);\n\tif (ret != 0)\n\t\tprintk(\"rtk_qos_schedulingQueue_set failed\\n\");\n}\n\nvoid rtk_hal_qos_get_queue_weight(struct ra_switch_ioctl_data *data)\n{\n\tint i;\n\trtk_api_ret_t ret;\n\trtk_qos_queue_weights_t qweights;\n\n\tret = rtk_qos_schedulingQueue_get(data->port, &qweights);\n\tif (ret != 0)\n\t\tprintk(\"rtk_qos_schedulingQueue_get failed\\n\");\n\telse {\n\t\tprintk(\"=== Port%d queue weight ===\\n\", data->port);\n\t\tfor (i = 0; i < 8; i++)\n\t\t\tprintk(\"qweights.weights[%d] = %d\\n\",i ,qweights.weights[i]);\n\t}\n}\n\nvoid rtk_hal_enable_igmpsnoop(struct ra_switch_ioctl_data *data)\n{\n\trtk_api_ret_t ret;\n\trtk_portmask_t pmask;\n\t\n\n\tret = rtk_igmp_init();\n\tif (data->on_off == 1) {\n\t\tRTK_PORTMASK_CLEAR(pmask);\n\t\tRTK_PORTMASK_PORT_SET(pmask, EXT_PORT0);\n\t\tret |= rtk_igmp_static_router_port_set(&pmask);\n\t\tret |= rtk_igmp_protocol_set(UTP_PORT4, PROTOCOL_IGMPv1, IGMP_ACTION_FORWARD);\n\t\tret |= rtk_igmp_protocol_set(UTP_PORT4, PROTOCOL_IGMPv2, IGMP_ACTION_FORWARD);\n\t\tret |= rtk_igmp_protocol_set(UTP_PORT4, PROTOCOL_MLDv1, IGMP_ACTION_FORWARD);\n\t\tret |= rtk_igmp_protocol_set(EXT_PORT1, PROTOCOL_IGMPv1, IGMP_ACTION_FORWARD);\n\t\tret |= rtk_igmp_protocol_set(EXT_PORT1, PROTOCOL_IGMPv2, IGMP_ACTION_FORWARD);\n\t\tret |= rtk_igmp_protocol_set(EXT_PORT1, PROTOCOL_MLDv1, IGMP_ACTION_FORWARD);\n\t\tret |= rtk_igmp_protocol_set(UTP_PORT0, PROTOCOL_IGMPv3, IGMP_ACTION_ASIC);\n\t\tret |= rtk_igmp_protocol_set(UTP_PORT1, PROTOCOL_IGMPv3, IGMP_ACTION_ASIC);\n\t\tret |= rtk_igmp_protocol_set(UTP_PORT2, PROTOCOL_IGMPv3, IGMP_ACTION_ASIC);\n\t\tret |= rtk_igmp_protocol_set(UTP_PORT3, PROTOCOL_IGMPv3, IGMP_ACTION_ASIC);\n\t\tret |= rtk_igmp_protocol_set(EXT_PORT0, PROTOCOL_IGMPv3, IGMP_ACTION_ASIC);\n\n\t\tret |= rtk_leaky_vlan_set(LEAKY_IPMULTICAST, ENABLED);\n\t\tret |= rtk_l2_ipMcastForwardRouterPort_set(DISABLED);\n\t\t/* drop unknown multicast packets*/\n\t\t/* ret |= rtk_trap_unknownMcastPktAction_set(UTP_PORT4, MCAST_IPV4, MCAST_ACTION_DROP);*/\n\t} else {\n\t\tRTK_PORTMASK_CLEAR(pmask);\n        RTK_PORTMASK_PORT_SET(pmask, EXT_PORT0);\n        RTK_PORTMASK_PORT_SET(pmask, EXT_PORT1);\n\t\tret |= rtk_igmp_protocol_set(UTP_PORT0, PROTOCOL_IGMPv3, IGMP_ACTION_ASIC);\n\t\tret |= rtk_igmp_protocol_set(UTP_PORT1, PROTOCOL_IGMPv3, IGMP_ACTION_ASIC);\n\t\tret |= rtk_igmp_protocol_set(UTP_PORT2, PROTOCOL_IGMPv3, IGMP_ACTION_ASIC);\n\t\tret |= rtk_igmp_protocol_set(UTP_PORT3, PROTOCOL_IGMPv3, IGMP_ACTION_ASIC);\n\t\tret |= rtk_igmp_protocol_set(EXT_PORT0, PROTOCOL_IGMPv3, IGMP_ACTION_ASIC);\n\n\t\tret |= rtk_igmp_static_router_port_set(&pmask);\n\t}\n\tif(ret != RT_ERR_OK)\n\t\tprintk(\"enable switch igmpsnoop failed\\n\");\n}\n\nvoid rtk_hal_disable_igmpsnoop(void)\n{\n\tif (rtk_igmp_state_set(DISABLED) != RT_ERR_OK)\n\t\tprintk(\"Disable IGMP SNOOPING failed\\n\");\n}\n\nrtk_api_ret_t rtk_port_phyTestMode_set(rtk_port_t port, rtk_port_phy_test_mode_t mode)\n{\n    rtk_uint32          data, regData, i;\n    rtk_api_ret_t       retVal;\n\n    RTK_CHK_PORT_IS_UTP(port);\n\n    if(mode >= PHY_TEST_MODE_END)\n        return RT_ERR_INPUT;\n\n    if( (mode == PHY_TEST_MODE_2) || (mode == PHY_TEST_MODE_3) )\n        return RT_ERR_INPUT;\n\n    if (PHY_TEST_MODE_NORMAL != mode)\n    {\n        /* Other port should be Normal mode */\n        RTK_SCAN_ALL_LOG_PORT(i)\n        {\n            if(rtk_switch_isUtpPort(i) == RT_ERR_OK)\n            {\n                if(i != port)\n                {\n                    if ((retVal = rtl8367c_getAsicPHYReg(rtk_switch_port_L2P_get(i), 9, &data)) != RT_ERR_OK)\n                        return retVal;\n\n                    if((data & 0xE000) != 0)\n                        return RT_ERR_NOT_ALLOWED;\n                }\n            }\n        }\n    }\n\n    if ((retVal = rtl8367c_getAsicPHYReg(rtk_switch_port_L2P_get(port), 9, &data)) != RT_ERR_OK)\n        return retVal;\n\n    data &= ~0xE000;\n    data |= (mode << 13);\n    if ((retVal = rtl8367c_setAsicPHYReg(rtk_switch_port_L2P_get(port), 9, data)) != RT_ERR_OK)\n        return retVal;\n\n    if (PHY_TEST_MODE_4 == mode)\n    {\n        if((retVal = rtl8367c_setAsicReg(0x13C2, 0x0249)) != RT_ERR_OK)\n            return retVal;\n\n        if((retVal = rtl8367c_getAsicReg(0x1300, &regData)) != RT_ERR_OK)\n            return retVal;\n\n        if( (regData == 0x0276) || (regData == 0x0597) )\n        {\n            if ((retVal = rtl8367c_setAsicPHYOCPReg(rtk_switch_port_L2P_get(port), 0xbcc2, 0xF4F4)) != RT_ERR_OK)\n                return retVal;\n        }\n\n        if( (regData == 0x6367) )\n        {\n            if ((retVal = rtl8367c_setAsicPHYOCPReg(rtk_switch_port_L2P_get(port), 0xa436, 0x80c1)) != RT_ERR_OK)\n                return retVal;\n\n            if ((retVal = rtl8367c_setAsicPHYOCPReg(rtk_switch_port_L2P_get(port), 0xa438, 0xfe00)) != RT_ERR_OK)\n                return retVal;\n        }\n    }\n\n    return RT_ERR_OK;\n}\n\nvoid rtk_hal_set_phy_test_mode(struct ra_switch_ioctl_data *data)\n{\n\trtk_api_ret_t ret;\n\n    ret = rtk_port_phyTestMode_set(data->port, data->mode);\n\tif (ret != RT_ERR_OK)\n\t\tprintk(\"rtk_port_phyTestMode_set failed\\n\");\n\telse\n\t\tprintk(\"set port%d in test mode %d.\\n\", data->port, data->mode);\n}\n\nvoid rtk_hal_set_port_trunk(struct ra_switch_ioctl_data *data)\n{\n\n\trtk_api_ret_t ret;\n\trtk_portmask_t member;\n\tint i;\n\n\tRTK_PORTMASK_CLEAR(member);\n\tfor (i = 0; i < 4; i++) {\n\t\tif (data->port_map & (1 << i))\n\t\t\tRTK_PORTMASK_PORT_SET(member, i);\n    }\n\n\tret = rtk_trunk_port_set(TRUNK_GROUP0, &member);\n\tif (ret != RT_ERR_OK)\n\t\tprintk(\"rtk_trunk_port_set failed\\n\");\n\n\tret = rtk_trunk_distributionAlgorithm_set(RTK_WHOLE_SYSTEM, 0x7F);\n\tif (ret != RT_ERR_OK)\n\t\tprintk(\"rtk_trunk_distributionAlgorithm_set failed\\n\");\n}\n\nvoid rtk_hal_vlan_tag(struct ra_switch_ioctl_data *data)\n{\n\trtk_api_ret_t ret;\n\trtk_vlan_cfg_t vlan;\n\n    ret = rtk_vlan_get(data->vid, &vlan);\n\tif (ret != RT_ERR_OK)\n\t\tprintk(\"rtk_vlan_get failed\\n\");\n\telse {\n\t\tif (data->on_off == 0)\n\t\t\tRTK_PORTMASK_PORT_SET(vlan.untag, data->port);\n\t\telse\n\t\t\tRTK_PORTMASK_PORT_CLEAR(vlan.untag, data->port);\n\t\t\n\t\tret = rtk_vlan_set(data->vid, &vlan);\n\t\tif (ret != RT_ERR_OK)\n\t\t\tprintk(\"rtk_vlan_set failed\\n\");\n\t}\n}\n\nvoid rtk_hal_vlan_mode(struct ra_switch_ioctl_data *data)\n{\n\trtk_vlan_cfg_t vlan1, vlan2;\n\trtk_api_ret_t ret;\n\n\tret = rtk_vlan_get(1, &vlan1);\n\tif (ret != RT_ERR_OK)\n\t\tprintk(\"rtk_vlan_get failed\\n\");\n\n\tret = rtk_vlan_get(2, &vlan2);\n\tif (ret != RT_ERR_OK)\n\t\tprintk(\"rtk_vlan_get failed\\n\");\n\n\tif (data->mode == 0) { //ivl\n\t\tvlan1.ivl_en = 1;\n\t\tvlan1.fid_msti = 0;\n\t\trtk_vlan_set(1, &vlan1);\n\t\tvlan2.ivl_en = 1;\n\t\tvlan2.fid_msti = 0;\n\t\trtk_vlan_set(2, &vlan2);\n\t} else if(data->mode == 1) {//svl\n\t\tvlan1.ivl_en = 0;\n\t\tvlan1.fid_msti = 0;\n\t\trtk_vlan_set(1, &vlan1);\n\t\tvlan2.ivl_en = 0;\n\t\tvlan2.fid_msti = 1;\n\t\trtk_vlan_set(2, &vlan2);\n\t} else\n\t\tprintk(\"mode not supported\\n\");\n}\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtk_switch.c",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * $Revision: 76336 $\n * $Date: 2017-03-09 10:41:21 +0800 (週四, 09 三月 2017) $\n *\n * Purpose : RTK switch high-level API\n * Feature : Here is a list of all functions and variables in this module.\n *\n */\n#include <rtk_switch.h>\n#include <rtk_error.h>\n#include <string.h>\n\n#include <rate.h>\n#include <rtl8367c_asicdrv.h>\n#include <rtl8367c_asicdrv_misc.h>\n#include <rtl8367c_asicdrv_green.h>\n#include <rtl8367c_asicdrv_lut.h>\n#include <rtl8367c_asicdrv_rma.h>\n#include <rtl8367c_asicdrv_mirror.h>\n\n#if defined(FORCE_PROBE_RTL8367C)\nstatic init_state_t    init_state = INIT_COMPLETED;\n#elif defined(FORCE_PROBE_RTL8370B)\nstatic init_state_t    init_state = INIT_COMPLETED;\n#elif defined(FORCE_PROBE_RTL8364B)\nstatic init_state_t    init_state = INIT_COMPLETED;\n#elif defined(FORCE_PROBE_RTL8363SC_VB)\nstatic init_state_t    init_state = INIT_COMPLETED;\n#else\nstatic init_state_t    init_state = INIT_NOT_COMPLETED;\n#endif\n\n#define AUTO_PROBE (!defined(FORCE_PROBE_RTL8367C) && !defined(FORCE_PROBE_RTL8370B) && !defined(FORCE_PROBE_RTL8364B) && !defined(FORCE_PROBE_RTL8363SC_VB))\n\n#if (AUTO_PROBE || defined(FORCE_PROBE_RTL8367C))\nstatic rtk_switch_halCtrl_t rtl8367c_hal_Ctrl =\n{\n    /* Switch Chip */\n    CHIP_RTL8367C,\n\n    /* Logical to Physical */\n    {0, 1, 2, 3, 4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,\n     6, 7, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },\n\n    /* Physical to Logical */\n    {UTP_PORT0, UTP_PORT1, UTP_PORT2, UTP_PORT3, UTP_PORT4, UNDEFINE_PORT, EXT_PORT0, EXT_PORT1,\n     UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT,\n     UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT,\n     UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT},\n\n    /* Port Type */\n    {UTP_PORT, UTP_PORT, UTP_PORT, UTP_PORT, UTP_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT,\n     UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT,\n     EXT_PORT, EXT_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT,\n     UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT},\n\n    /* PTP port */\n    {1, 1, 1, 1, 1, 0, 0, 0,\n     0, 0, 0, 0, 0, 0, 0, 0,\n     0, 0, 0, 0, 0, 0, 0, 0,\n     0, 0, 0, 0, 0, 0, 0, 0 },\n\n    /* Valid port mask */\n    ( (0x1 << UTP_PORT0) | (0x1 << UTP_PORT1) | (0x1 << UTP_PORT2) | (0x1 << UTP_PORT3) | (0x1 << UTP_PORT4) | (0x1 << EXT_PORT0) | (0x1 << EXT_PORT1) ),\n\n    /* Valid UTP port mask */\n    ( (0x1 << UTP_PORT0) | (0x1 << UTP_PORT1) | (0x1 << UTP_PORT2) | (0x1 << UTP_PORT3) | (0x1 << UTP_PORT4) ),\n\n    /* Valid EXT port mask */\n    ( (0x1 << EXT_PORT0) | (0x1 << EXT_PORT1) ),\n\n    /* Valid CPU port mask */\n    0x00,\n\n    /* Minimum physical port number */\n    0,\n\n    /* Maxmum physical port number */\n    7,\n\n    /* Physical port mask */\n    0xDF,\n\n    /* Combo Logical port ID */\n    4,\n\n    /* HSG Logical port ID */\n    EXT_PORT0,\n\n    /* SGMII Logical portmask */\n    (0x1 << EXT_PORT0),\n\n    /* Max Meter ID */\n    31,\n\n    /* MAX LUT Address Number */\n    2112,\n\n    /* Trunk Group Mask */\n    0x03\n};\n#endif\n\n#if (AUTO_PROBE || defined(FORCE_PROBE_RTL8370B))\nstatic rtk_switch_halCtrl_t rtl8370b_hal_Ctrl =\n{\n    /* Switch Chip */\n    CHIP_RTL8370B,\n\n    /* Logical to Physical */\n    {0, 1, 2, 3, 4, 5, 6, 7, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,\n     8, 9, 10, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },\n\n    /* Physical to Logical */\n    {UTP_PORT0, UTP_PORT1, UTP_PORT2, UTP_PORT3, UTP_PORT4, UTP_PORT5, UTP_PORT6, UTP_PORT7,\n     EXT_PORT0, EXT_PORT1, EXT_PORT2, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT,\n     UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT,\n     UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT},\n\n    /* Port Type */\n    {UTP_PORT, UTP_PORT, UTP_PORT, UTP_PORT, UTP_PORT, UTP_PORT, UTP_PORT, UTP_PORT,\n     UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT,\n     EXT_PORT, EXT_PORT, EXT_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT,\n     UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT},\n\n    /* PTP port */\n    {1, 1, 1, 1, 1, 1, 1, 1,\n     0, 0, 0, 0, 0, 0, 0, 0,\n     1, 1, 0, 0, 0, 0, 0, 0,\n     0, 0, 0, 0, 0, 0, 0, 0 },\n\n    /* Valid port mask */\n    ( (0x1 << UTP_PORT0) | (0x1 << UTP_PORT1) | (0x1 << UTP_PORT2) | (0x1 << UTP_PORT3) | (0x1 << UTP_PORT4) | (0x1 << UTP_PORT5) | (0x1 << UTP_PORT6) | (0x1 << UTP_PORT7) | (0x1 << EXT_PORT0) | (0x1 << EXT_PORT1) | (0x1 << EXT_PORT2) ),\n\n    /* Valid UTP port mask */\n    ( (0x1 << UTP_PORT0) | (0x1 << UTP_PORT1) | (0x1 << UTP_PORT2) | (0x1 << UTP_PORT3) | (0x1 << UTP_PORT4) | (0x1 << UTP_PORT5) | (0x1 << UTP_PORT6) | (0x1 << UTP_PORT7) ),\n\n    /* Valid EXT port mask */\n    ( (0x1 << EXT_PORT0) | (0x1 << EXT_PORT1) | (0x1 << EXT_PORT2) ),\n\n    /* Valid CPU port mask */\n    (0x1 << EXT_PORT2),\n\n    /* Minimum physical port number */\n    0,\n\n    /* Maxmum physical port number */\n    10,\n\n    /* Physical port mask */\n    0x7FF,\n\n    /* Combo Logical port ID */\n    7,\n\n    /* HSG Logical port ID */\n    EXT_PORT1,\n\n    /* SGMII Logical portmask */\n    ( (0x1 << EXT_PORT0) | (0x1 << EXT_PORT1) ),\n\n    /* Max Meter ID */\n    63,\n\n    /* MAX LUT Address Number 4096 + 64*/\n    4160,\n\n    /* Trunk Group Mask */\n    0x07\n};\n#endif\n\n#if (AUTO_PROBE || defined(FORCE_PROBE_RTL8364B))\nstatic rtk_switch_halCtrl_t rtl8364b_hal_Ctrl =\n{\n    /* Switch Chip */\n    CHIP_RTL8364B,\n\n    /* Logical to Physical */\n    {0xFF, 1, 0xFF, 3, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,\n     6, 7, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },\n\n    /* Physical to Logical */\n    {UNDEFINE_PORT, UTP_PORT1, UNDEFINE_PORT, UTP_PORT3, UNDEFINE_PORT, UNDEFINE_PORT, EXT_PORT0, EXT_PORT1,\n     UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT,\n     UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT,\n     UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT},\n\n    /* Port Type */\n    {UNKNOWN_PORT, UTP_PORT, UNKNOWN_PORT, UTP_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT,\n     UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT,\n     EXT_PORT, EXT_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT,\n     UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT},\n\n    /* PTP port */\n    {0, 0, 0, 0, 0, 0, 0, 0,\n     0, 0, 0, 0, 0, 0, 0, 0,\n     0, 0, 0, 0, 0, 0, 0, 0,\n     0, 0, 0, 0, 0, 0, 0, 0 },\n\n    /* Valid port mask */\n    ( (0x1 << UTP_PORT1) | (0x1 << UTP_PORT3) | (0x1 << EXT_PORT0) | (0x1 << EXT_PORT1) ),\n\n    /* Valid UTP port mask */\n    ( (0x1 << UTP_PORT1) | (0x1 << UTP_PORT3) ),\n\n    /* Valid EXT port mask */\n    ( (0x1 << EXT_PORT0) | (0x1 << EXT_PORT1) ),\n\n    /* Valid CPU port mask */\n    0x00,\n\n    /* Minimum physical port number */\n    0,\n\n    /* Maxmum physical port number */\n    7,\n\n    /* Physical port mask */\n    0xCA,\n\n    /* Combo Logical port ID */\n    4,\n\n    /* HSG Logical port ID */\n    EXT_PORT0,\n\n    /* SGMII Logical portmask */\n    ( (0x1 << EXT_PORT0) | (0x1 << EXT_PORT1) ),\n\n    /* Max Meter ID */\n    32,\n\n    /* MAX LUT Address Number */\n    2112,\n\n    /* Trunk Group Mask */\n    0x01\n};\n#endif\n\n#if (AUTO_PROBE || defined(FORCE_PROBE_RTL8363SC_VB))\nstatic rtk_switch_halCtrl_t rtl8363sc_vb_hal_Ctrl =\n{\n    /* Switch Chip */\n    CHIP_RTL8363SC_VB,\n\n    /* Logical to Physical */\n    {0xFF, 0xFF, 1, 3, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,\n     6, 7, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },\n\n    /* Physical to Logical */\n    {UNDEFINE_PORT, UTP_PORT2, UNDEFINE_PORT, UTP_PORT3, UNDEFINE_PORT, UNDEFINE_PORT, EXT_PORT0, EXT_PORT1,\n     UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT,\n     UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT,\n     UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT, UNDEFINE_PORT},\n\n    /* Port Type */\n    {UNKNOWN_PORT, UNKNOWN_PORT, UTP_PORT, UTP_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT,\n     UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT,\n     EXT_PORT, EXT_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT,\n     UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT, UNKNOWN_PORT},\n\n    /* PTP port */\n    {0, 0, 0, 0, 0, 0, 0, 0,\n     0, 0, 0, 0, 0, 0, 0, 0,\n     0, 0, 0, 0, 0, 0, 0, 0,\n     0, 0, 0, 0, 0, 0, 0, 0 },\n\n    /* Valid port mask */\n    ( (0x1 << UTP_PORT2) | (0x1 << UTP_PORT3) | (0x1 << EXT_PORT0) | (0x1 << EXT_PORT1) ),\n\n    /* Valid UTP port mask */\n    ( (0x1 << UTP_PORT2) | (0x1 << UTP_PORT3) ),\n\n    /* Valid EXT port mask */\n    ( (0x1 << EXT_PORT0) | (0x1 << EXT_PORT1) ),\n\n    /* Valid CPU port mask */\n    0x00,\n\n    /* Minimum physical port number */\n    0,\n\n    /* Maxmum physical port number */\n    7,\n\n    /* Physical port mask */\n    0xCA,\n\n    /* Combo Logical port ID */\n    4,\n\n    /* HSG Logical port ID */\n    EXT_PORT0,\n\n    /* SGMII Logical portmask */\n    ( (0x1 << EXT_PORT0) | (0x1 << EXT_PORT1) ),\n\n    /* Max Meter ID */\n    32,\n\n    /* MAX LUT Address Number */\n    2112,\n\n    /* Trunk Group Mask */\n    0x01\n};\n#endif\n\n#if defined(FORCE_PROBE_RTL8367C)\nstatic rtk_switch_halCtrl_t *halCtrl = &rtl8367c_hal_Ctrl;\n#elif defined(FORCE_PROBE_RTL8370B)\nstatic rtk_switch_halCtrl_t *halCtrl = &rtl8370b_hal_Ctrl;\n#elif defined(FORCE_PROBE_RTL8364B)\nstatic rtk_switch_halCtrl_t *halCtrl = &rtl8364b_hal_Ctrl;\n#elif defined(FORCE_PROBE_RTL8363SC_VB)\nstatic rtk_switch_halCtrl_t *halCtrl = &rtl8363sc_vb_hal_Ctrl;\n#else\nstatic rtk_switch_halCtrl_t *halCtrl = NULL;\n#endif\n\nstatic rtk_uint32 PatchChipData[210][2] =\n{\n        {0xa436, 0x8028}, {0xa438, 0x6800}, {0xb82e, 0x0001}, {0xa436, 0xb820}, {0xa438, 0x0090}, {0xa436, 0xa012}, {0xa438, 0x0000}, {0xa436, 0xa014}, {0xa438, 0x2c04}, {0xa438, 0x2c6c},\n        {0xa438, 0x2c75}, {0xa438, 0x2c77}, {0xa438, 0x1414}, {0xa438, 0x1579}, {0xa438, 0x1536}, {0xa438, 0xc432}, {0xa438, 0x32c0}, {0xa438, 0x42d6}, {0xa438, 0x32b5}, {0xa438, 0x003e},\n        {0xa438, 0x614c}, {0xa438, 0x1569}, {0xa438, 0xd705}, {0xa438, 0x318c}, {0xa438, 0x42d6}, {0xa438, 0xd702}, {0xa438, 0x31ef}, {0xa438, 0x42d6}, {0xa438, 0x629c}, {0xa438, 0x2c04},\n        {0xa438, 0x653c}, {0xa438, 0x422a}, {0xa438, 0x5d83}, {0xa438, 0xd06a}, {0xa438, 0xd1b0}, {0xa438, 0x1536}, {0xa438, 0xc43a}, {0xa438, 0x32c0}, {0xa438, 0x42d6}, {0xa438, 0x32b5},\n        {0xa438, 0x003e}, {0xa438, 0x314a}, {0xa438, 0x42fe}, {0xa438, 0x337b}, {0xa438, 0x02d6}, {0xa438, 0x3063}, {0xa438, 0x0c1b}, {0xa438, 0x22fe}, {0xa438, 0xc435}, {0xa438, 0xd0be},\n        {0xa438, 0xd1f7}, {0xa438, 0xe0f0}, {0xa438, 0x1a40}, {0xa438, 0xa320}, {0xa438, 0xd702}, {0xa438, 0x154a}, {0xa438, 0xc434}, {0xa438, 0x32c0}, {0xa438, 0x42d6}, {0xa438, 0x32b5},\n        {0xa438, 0x003e}, {0xa438, 0x60ec}, {0xa438, 0x1569}, {0xa438, 0xd705}, {0xa438, 0x619f}, {0xa438, 0xd702}, {0xa438, 0x414f}, {0xa438, 0x2c2e}, {0xa438, 0x610a}, {0xa438, 0xd705},\n        {0xa438, 0x5e1f}, {0xa438, 0xc43f}, {0xa438, 0xc88b}, {0xa438, 0xd702}, {0xa438, 0x7fe0}, {0xa438, 0x22f3}, {0xa438, 0xd0a0}, {0xa438, 0xd1b2}, {0xa438, 0xd0c3}, {0xa438, 0xd1c3},\n        {0xa438, 0x8d01}, {0xa438, 0x1536}, {0xa438, 0xc438}, {0xa438, 0xe0f0}, {0xa438, 0x1a80}, {0xa438, 0xd706}, {0xa438, 0x60c0}, {0xa438, 0xd710}, {0xa438, 0x409e}, {0xa438, 0xa804},\n        {0xa438, 0xad01}, {0xa438, 0x8804}, {0xa438, 0xd702}, {0xa438, 0x32c0}, {0xa438, 0x42d6}, {0xa438, 0x32b5}, {0xa438, 0x003e}, {0xa438, 0x405b}, {0xa438, 0x1576}, {0xa438, 0x7c9c},\n        {0xa438, 0x60ec}, {0xa438, 0x1569}, {0xa438, 0xd702}, {0xa438, 0x5d43}, {0xa438, 0x31ef}, {0xa438, 0x02fe}, {0xa438, 0x22d6}, {0xa438, 0x590a}, {0xa438, 0xd706}, {0xa438, 0x5c80},\n        {0xa438, 0xd702}, {0xa438, 0x5c44}, {0xa438, 0x3063}, {0xa438, 0x02d6}, {0xa438, 0x5be2}, {0xa438, 0x22fb}, {0xa438, 0xa240}, {0xa438, 0xa104}, {0xa438, 0x8c03}, {0xa438, 0x8178},\n        {0xa438, 0xd701}, {0xa438, 0x31ad}, {0xa438, 0x4917}, {0xa438, 0x8102}, {0xa438, 0x2917}, {0xa438, 0xc302}, {0xa438, 0x268a}, {0xa436, 0xA01A}, {0xa438, 0x0000}, {0xa436, 0xA006},\n        {0xa438, 0x0fff}, {0xa436, 0xA004}, {0xa438, 0x0689}, {0xa436, 0xA002}, {0xa438, 0x0911}, {0xa436, 0xA000}, {0xa438, 0x7302}, {0xa436, 0xB820}, {0xa438, 0x0010}, {0xa436, 0x8412},\n        {0xa438, 0xaf84}, {0xa438, 0x1eaf}, {0xa438, 0x8427}, {0xa438, 0xaf84}, {0xa438, 0x27af}, {0xa438, 0x8427}, {0xa438, 0x0251}, {0xa438, 0x6802}, {0xa438, 0x8427}, {0xa438, 0xaf04},\n        {0xa438, 0x0af8}, {0xa438, 0xf9bf}, {0xa438, 0x5581}, {0xa438, 0x0255}, {0xa438, 0x27ef}, {0xa438, 0x310d}, {0xa438, 0x345b}, {0xa438, 0x0fa3}, {0xa438, 0x032a}, {0xa438, 0xe087},\n        {0xa438, 0xffac}, {0xa438, 0x2040}, {0xa438, 0xbf56}, {0xa438, 0x7402}, {0xa438, 0x5527}, {0xa438, 0xef31}, {0xa438, 0xef20}, {0xa438, 0xe787}, {0xa438, 0xfee6}, {0xa438, 0x87fd},\n        {0xa438, 0xd488}, {0xa438, 0x88bf}, {0xa438, 0x5674}, {0xa438, 0x0254}, {0xa438, 0xe3e0}, {0xa438, 0x87ff}, {0xa438, 0xf720}, {0xa438, 0xe487}, {0xa438, 0xffaf}, {0xa438, 0x847e},\n        {0xa438, 0xe087}, {0xa438, 0xffad}, {0xa438, 0x2016}, {0xa438, 0xe387}, {0xa438, 0xfee2}, {0xa438, 0x87fd}, {0xa438, 0xef45}, {0xa438, 0xbf56}, {0xa438, 0x7402}, {0xa438, 0x54e3},\n        {0xa438, 0xe087}, {0xa438, 0xfff6}, {0xa438, 0x20e4}, {0xa438, 0x87ff}, {0xa438, 0xfdfc}, {0xa438, 0x0400}, {0xa436, 0xb818}, {0xa438, 0x0407}, {0xa436, 0xb81a}, {0xa438, 0xfffd},\n        {0xa436, 0xb81c}, {0xa438, 0xfffd}, {0xa436, 0xb81e}, {0xa438, 0xfffd}, {0xa436, 0xb832}, {0xa438, 0x0001}, {0xb820, 0x0000}, {0xb82e, 0x0000}, {0xa436, 0x8028}, {0xa438, 0x0000}\n};\n\nstatic rtk_api_ret_t _rtk_switch_init_8367c(void)\n{\n    rtk_port_t port;\n    rtk_uint32 retVal;\n    rtk_uint32 regData;\n    rtk_uint32 regValue;\n\n    if( (retVal = rtl8367c_setAsicReg(0x13c2, 0x0249)) != RT_ERR_OK)\n        return retVal;\n\n    if( (retVal = rtl8367c_getAsicReg(0x1301, &regValue)) != RT_ERR_OK)\n        return retVal;\n\n    if( (retVal = rtl8367c_setAsicReg(0x13c2, 0x0000)) != RT_ERR_OK)\n        return retVal;\n\n    RTK_SCAN_ALL_LOG_PORT(port)\n    {\n         if(rtk_switch_isUtpPort(port) == RT_ERR_OK)\n         {\n             if((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_PORT0_EEECFG + (0x20 * port), RTL8367C_PORT0_EEECFG_EEE_100M_OFFSET, 1)) != RT_ERR_OK)\n                 return retVal;\n\n             if((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_PORT0_EEECFG + (0x20 * port), RTL8367C_PORT0_EEECFG_EEE_GIGA_500M_OFFSET, 1)) != RT_ERR_OK)\n                 return retVal;\n\n             if((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_PORT0_EEECFG + (0x20 * port), RTL8367C_PORT0_EEECFG_EEE_TX_OFFSET, 1)) != RT_ERR_OK)\n                 return retVal;\n\n             if((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_PORT0_EEECFG + (0x20 * port), RTL8367C_PORT0_EEECFG_EEE_RX_OFFSET, 1)) != RT_ERR_OK)\n                 return retVal;\n\n             if((retVal = rtl8367c_getAsicPHYOCPReg(port, 0xA428, &regData)) != RT_ERR_OK)\n                return retVal;\n\n             regData &= ~(0x0200);\n             if((retVal = rtl8367c_setAsicPHYOCPReg(port, 0xA428, regData)) != RT_ERR_OK)\n                 return retVal;\n\n             if((regValue & 0x00F0) == 0x00A0)\n             {\n                 if((retVal = rtl8367c_getAsicPHYOCPReg(port, 0xA5D0, &regData)) != RT_ERR_OK)\n                     return retVal;\n\n                 regData |= 0x0006;\n                 if((retVal = rtl8367c_setAsicPHYOCPReg(port, 0xA5D0, regData)) != RT_ERR_OK)\n                     return retVal;\n             }\n         }\n    }\n\n    if((retVal = rtl8367c_setAsicReg(RTL8367C_REG_UTP_FIB_DET, 0x15BB)) != RT_ERR_OK)\n        return retVal;\n\n    if((retVal = rtl8367c_setAsicReg(0x1303, 0x06D6)) != RT_ERR_OK)\n        return retVal;\n\n    if((retVal = rtl8367c_setAsicReg(0x1304, 0x0700)) != RT_ERR_OK)\n        return retVal;\n\n    if((retVal = rtl8367c_setAsicReg(0x13E2, 0x003F)) != RT_ERR_OK)\n        return retVal;\n\n    if((retVal = rtl8367c_setAsicReg(0x13F9, 0x0090)) != RT_ERR_OK)\n        return retVal;\n\n    if((retVal = rtl8367c_setAsicReg(0x121e, 0x03CA)) != RT_ERR_OK)\n        return retVal;\n\n    if((retVal = rtl8367c_setAsicReg(0x1233, 0x0352)) != RT_ERR_OK)\n        return retVal;\n\n    if((retVal = rtl8367c_setAsicReg(0x1237, 0x00a0)) != RT_ERR_OK)\n        return retVal;\n\n    if((retVal = rtl8367c_setAsicReg(0x123a, 0x0030)) != RT_ERR_OK)\n        return retVal;\n\n    if((retVal = rtl8367c_setAsicReg(0x1239, 0x0084)) != RT_ERR_OK)\n        return retVal;\n\n    if((retVal = rtl8367c_setAsicReg(0x0301, 0x1000)) != RT_ERR_OK)\n        return retVal;\n\n    if((retVal = rtl8367c_setAsicReg(0x1349, 0x001F)) != RT_ERR_OK)\n        return retVal;\n\n    if((retVal = rtl8367c_setAsicRegBit(0x18e0, 0, 0)) != RT_ERR_OK)\n        return retVal;\n\n    if((retVal = rtl8367c_setAsicRegBit(0x122b, 14, 1)) != RT_ERR_OK)\n        return retVal;\n\n    if((retVal = rtl8367c_setAsicRegBits(0x1305, 0xC000, 3)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\nstatic rtk_api_ret_t _rtk_switch_init_8370b(void)\n{\n    ret_t retVal;\n    rtk_uint32 regData, tmp = 0;\n    rtk_uint32 i, prf, counter;\n    rtk_uint32 long_link[8] = {0x0210, 0x03e8, 0x0218, 0x03f0, 0x0220, 0x03f8, 0x0208, 0x03e0 };\n\n    if((retVal = rtl8367c_setAsicRegBits(0x1205, 0x0300, 3)) != RT_ERR_OK)\n        return retVal;\n\n\n    for(i=0; i<8; i++)\n    {\n      if ((retVal = rtl8367c_getAsicPHYOCPReg(i, 0xa420, &regData)) != RT_ERR_OK)\n          return retVal;\n        tmp = regData & 0x7 ;\n       if(tmp == 0x3)\n       {\n           prf = 1;\n           if((retVal = rtl8367c_setAsicPHYOCPReg(i, 0xb83e, 0x6fa9)) != RT_ERR_OK)\n              return retVal;\n           if((retVal = rtl8367c_setAsicPHYOCPReg(i, 0xb840, 0xa9)) != RT_ERR_OK)\n               return retVal;\n           for(counter = 0; counter < 10000; counter++); //delay\n\n           if ((retVal = rtl8367c_getAsicPHYOCPReg(i, 0xb820, &regData)) != RT_ERR_OK)\n               return retVal;\n           tmp = regData | 0x10;\n           if ((retVal = rtl8367c_setAsicPHYOCPReg(i, 0xb820, tmp)) != RT_ERR_OK)\n               return retVal;\n           for(counter = 0; counter < 10000; counter++); //delay\n           counter = 0;\n           do{\n              counter = counter + 1;\n              if ((retVal = rtl8367c_getAsicPHYOCPReg(i, 0xb800, &regData)) != RT_ERR_OK)\n                   return retVal;\n              tmp = regData & 0x40;\n              if(tmp != 0)\n                break;\n           } while (counter < 20);   //Wait for patch ready = 1...\n       }\n   }\n    if ((retVal = rtl8367c_getAsicReg(0x1d01, &regData)) != RT_ERR_OK)\n        return retVal;\n    tmp = regData;\n    tmp = tmp | 0x3BE0; /*Broadcast port enable*/\n    tmp = tmp & 0xFFE0; /*Phy_id = 0 */\n    if((retVal = rtl8367c_setAsicReg(0x1d01, tmp)) != RT_ERR_OK)\n        return retVal;\n\n    for(i=0;i < 210; i++)\n    {\n        if((retVal = rtl8367c_setAsicPHYOCPReg(0, PatchChipData[i][0], PatchChipData[i][1])) != RT_ERR_OK)\n             return retVal;\n    }\n\n   if((retVal = rtl8367c_setAsicReg(0x1d01, regData)) != RT_ERR_OK)\n        return retVal;\n\n    for(i=0; i < 8; i++)\n    {\n        if((retVal = rtl8367c_setAsicPHYOCPReg(i, 0xa4b4, long_link[i])) != RT_ERR_OK)\n             return retVal;\n    }\n\n  if (prf == 0x1)\n     {\n        for(i=0; i<8; i++)\n        {\n         if ((retVal = rtl8367c_getAsicPHYOCPReg(i, 0xb820, &regData)) != RT_ERR_OK)\n             return retVal;\n       tmp = regData & 0xFFEF;\n       if ((retVal = rtl8367c_setAsicPHYOCPReg(i, 0xb820, tmp)) != RT_ERR_OK)\n             return retVal;\n\n       for(counter = 0; counter < 10000; counter++); //delay\n\n       counter = 0;\n       do{\n            counter = counter + 1;\n            if ((retVal = rtl8367c_getAsicPHYOCPReg(i, 0xb800, &regData)) != RT_ERR_OK)\n              return retVal;\n            tmp = regData & 0x40;\n            if( tmp == 0 )\n               break;\n       } while (counter < 20);   //Wait for patch ready = 1...\n      if ((retVal = rtl8367c_setAsicPHYOCPReg(i, 0xb83e, 0x6f48)) != RT_ERR_OK)\n          return retVal;\n      if ((retVal = rtl8367c_setAsicPHYOCPReg(i, 0xb840, 0xfa)) != RT_ERR_OK)\n          return retVal;\n          }\n   }\n\n    /*Check phy link status*/\n    for(i=0; i<8; i++)\n    {\n      if ((retVal = rtl8367c_getAsicPHYOCPReg(i, 0xa400, &regData)) != RT_ERR_OK)\n          return retVal;\n      tmp = regData & 0x800;\n        if(tmp == 0x0)\n            {\n              tmp = regData | 0x200;\n          if ((retVal = rtl8367c_setAsicPHYOCPReg(i, 0xa400, tmp)) != RT_ERR_OK)\n             return retVal;\n            }\n    }\n\n  for(counter = 0; counter < 10000; counter++); //delay\n\n  return RT_ERR_OK;\n}\n\nstatic rtk_api_ret_t _rtk_switch_init_8364b(void)\n{\n    ret_t retVal;\n    rtk_uint32 regData;\n\n    /*enable EEE, include mac & phy*/\n\n    if ((retVal = rtl8367c_setAsicRegBits(0x38, 0x300, 3)) != RT_ERR_OK)\n        return retVal;\n    if ((retVal = rtl8367c_setAsicRegBits(0x78, 0x300, 3)) != RT_ERR_OK)\n        return retVal;\n    if ((retVal = rtl8367c_setAsicRegBits(0xd8, 0x300, 0)) != RT_ERR_OK)\n        return retVal;\n    if ((retVal = rtl8367c_setAsicRegBits(0xf8, 0x300, 0)) != RT_ERR_OK)\n        return retVal;\n\n    if ((retVal = rtl8367c_setAsicPHYOCPReg(1, 0xa5d0, 6)) != RT_ERR_OK)\n        return retVal;\n    if ((retVal = rtl8367c_setAsicPHYOCPReg(3, 0xa5d0, 6)) != RT_ERR_OK)\n        return retVal;\n\n    /*PAD para*/\n\n    /*EXT1 PAD Para*/\n    if ((retVal = rtl8367c_getAsicReg(0x1303, &regData)) != RT_ERR_OK)\n        return retVal;\n    regData &= 0xFFFFFFFE;\n    regData |= 0x250;\n    if((retVal = rtl8367c_setAsicReg(0x1303, regData)) != RT_ERR_OK)\n        return retVal;\n\n    if ((retVal = rtl8367c_setAsicRegBits(0x1304, 0x7000, 0)) != RT_ERR_OK)\n        return retVal;\n    if ((retVal = rtl8367c_setAsicRegBits(0x1304, 0x700, 7)) != RT_ERR_OK)\n        return retVal;\n    if ((retVal = rtl8367c_setAsicRegBits(0x13f9, 0x38, 0)) != RT_ERR_OK)\n        return retVal;\n\n    /*EXT2 PAD Para*/\n    if ((retVal = rtl8367c_setAsicRegBit(0x1303, 10, 1)) != RT_ERR_OK)\n        return retVal;\n    if ((retVal = rtl8367c_setAsicRegBits(0x13E2, 0x1ff, 0x26)) != RT_ERR_OK)\n        return retVal;\n    if ((retVal = rtl8367c_setAsicRegBits(0x13f9, 0x1c0, 0)) != RT_ERR_OK)\n        return retVal;\n\n\n    /*SDS PATCH*/\n    /*SP_CFG_EN_LINK_FIB1G*/\n    if((retVal = rtl8367c_getAsicSdsReg(0, 4, 0, &regData)) != RT_ERR_OK)\n        return retVal;\n    regData |= 0x4;\n    if((retVal = rtl8367c_setAsicSdsReg(0,4,0, regData)) != RT_ERR_OK)\n        return retVal;\n\n    /*FIB100 Down-speed*/\n    if((retVal = rtl8367c_getAsicSdsReg(0, 1, 0, &regData)) != RT_ERR_OK)\n        return retVal;\n    regData |= 0x20;\n    if((retVal = rtl8367c_setAsicSdsReg(0,1,0, regData)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\nstatic rtk_api_ret_t _rtk_switch_init_8363sc_vb(void)\n{\n\n    ret_t retVal;\n    rtk_uint32 regData;\n\n    /*enable EEE, include mac & phy*/\n\n    if ((retVal = rtl8367c_setAsicRegBits(0x38, 0x300, 3)) != RT_ERR_OK)\n        return retVal;\n    if ((retVal = rtl8367c_setAsicRegBits(0x78, 0x300, 3)) != RT_ERR_OK)\n        return retVal;\n    if ((retVal = rtl8367c_setAsicRegBits(0xd8, 0x300, 0)) != RT_ERR_OK)\n        return retVal;\n    if ((retVal = rtl8367c_setAsicRegBits(0xf8, 0x300, 0)) != RT_ERR_OK)\n        return retVal;\n\n    if ((retVal = rtl8367c_setAsicPHYOCPReg(1, 0xa5d0, 6)) != RT_ERR_OK)\n        return retVal;\n    if ((retVal = rtl8367c_setAsicPHYOCPReg(3, 0xa5d0, 6)) != RT_ERR_OK)\n        return retVal;\n\n    /*PAD para*/\n\n    /*EXT1 PAD Para*/\n    if ((retVal = rtl8367c_getAsicReg(0x1303, &regData)) != RT_ERR_OK)\n        return retVal;\n    regData &= 0xFFFFFFFE;\n    regData |= 0x250;\n    if((retVal = rtl8367c_setAsicReg(0x1303, regData)) != RT_ERR_OK)\n        return retVal;\n\n    if ((retVal = rtl8367c_setAsicRegBits(0x1304, 0x7000, 0)) != RT_ERR_OK)\n        return retVal;\n    if ((retVal = rtl8367c_setAsicRegBits(0x1304, 0x700, 7)) != RT_ERR_OK)\n        return retVal;\n    if ((retVal = rtl8367c_setAsicRegBits(0x13f9, 0x38, 0)) != RT_ERR_OK)\n        return retVal;\n\n    /*EXT2 PAD Para*/\n    if ((retVal = rtl8367c_setAsicRegBit(0x1303, 10, 1)) != RT_ERR_OK)\n        return retVal;\n    if ((retVal = rtl8367c_setAsicRegBits(0x13E2, 0x1ff, 0x26)) != RT_ERR_OK)\n        return retVal;\n    if ((retVal = rtl8367c_setAsicRegBits(0x13f9, 0x1c0, 0)) != RT_ERR_OK)\n        return retVal;\n\n\n    /*SDS PATCH*/\n    /*SP_CFG_EN_LINK_FIB1G*/\n    if((retVal = rtl8367c_getAsicSdsReg(0, 4, 0, &regData)) != RT_ERR_OK)\n        return retVal;\n    regData |= 0x4;\n    if((retVal = rtl8367c_setAsicSdsReg(0,4,0, regData)) != RT_ERR_OK)\n        return retVal;\n\n    /*FIB100 Down-speed*/\n    if((retVal = rtl8367c_getAsicSdsReg(0, 1, 0, &regData)) != RT_ERR_OK)\n        return retVal;\n    regData |= 0x20;\n    if((retVal = rtl8367c_setAsicSdsReg(0,1,0, regData)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_switch_probe\n * Description:\n *      Probe switch\n * Input:\n *      None\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Switch probed\n *      RT_ERR_FAILED   - Switch Unprobed.\n * Note:\n *\n */\nrtk_api_ret_t rtk_switch_probe(switch_chip_t *pSwitchChip)\n{\n#if defined(FORCE_PROBE_RTL8367C)\n\n    *pSwitchChip = CHIP_RTL8367C;\n    halCtrl = &rtl8367c_hal_Ctrl;\n\n#elif defined(FORCE_PROBE_RTL8370B)\n\n    *pSwitchChip = CHIP_RTL8370B;\n    halCtrl = &rtl8370b_hal_Ctrl;\n\n#elif defined(FORCE_PROBE_RTL8364B)\n\n    *pSwitchChip = CHIP_RTL8364B;\n    halCtrl = &rtl8364b_hal_Ctrl;\n\n#elif defined(FORCE_PROBE_RTL8363SC_VB)\n\n    *pSwitchChip = CHIP_RTL8363SC_VB;\n    halCtrl = &rtl8363sc_vb_hal_Ctrl;\n\n#else\n    rtk_uint32 retVal;\n    rtk_uint32 data, regValue;\n\n    if((retVal = rtl8367c_setAsicReg(0x13C2, 0x0249)) != RT_ERR_OK)\n        return retVal;\n\n    if((retVal = rtl8367c_getAsicReg(0x1300, &data)) != RT_ERR_OK)\n        return retVal;\n\n    if((retVal = rtl8367c_getAsicReg(0x1301, &regValue)) != RT_ERR_OK)\n        return retVal;\n\n    if((retVal = rtl8367c_setAsicReg(0x13C2, 0x0000)) != RT_ERR_OK)\n        return retVal;\n\n    switch (data)\n    {\n        case 0x0276:\n        case 0x0597:\n        case 0x6367:\n            *pSwitchChip = CHIP_RTL8367C;\n            halCtrl = &rtl8367c_hal_Ctrl;\n            break;\n        case 0x0652:\n        case 0x6368:\n            *pSwitchChip = CHIP_RTL8370B;\n            halCtrl = &rtl8370b_hal_Ctrl;\n            break;\n        case 0x0801:\n        case 0x6511:\n            if( (regValue & 0x00F0) == 0x0080)\n            {\n                *pSwitchChip = CHIP_RTL8363SC_VB;\n                halCtrl = &rtl8363sc_vb_hal_Ctrl;\n            }\n            else\n            {\n                *pSwitchChip = CHIP_RTL8364B;\n                halCtrl = &rtl8364b_hal_Ctrl;\n            }\n            break;\n        default:\n            return RT_ERR_FAILED;\n    }\n#endif\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_switch_initialState_set\n * Description:\n *      Set initial status\n * Input:\n *      state   - Initial state;\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Initialized\n *      RT_ERR_FAILED   - Uninitialized\n * Note:\n *\n */\nrtk_api_ret_t rtk_switch_initialState_set(init_state_t state)\n{\n    if(state >= INIT_STATE_END)\n        return RT_ERR_FAILED;\n\n    init_state = state;\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_switch_initialState_get\n * Description:\n *      Get initial status\n * Input:\n *      None\n * Output:\n *      None\n * Return:\n *      INIT_COMPLETED     - Initialized\n *      INIT_NOT_COMPLETED - Uninitialized\n * Note:\n *\n */\ninit_state_t rtk_switch_initialState_get(void)\n{\n    return init_state;\n}\n\n/* Function Name:\n *      rtk_switch_logicalPortCheck\n * Description:\n *      Check logical port ID.\n * Input:\n *      logicalPort     - logical port ID\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Port ID is correct\n *      RT_ERR_FAILED   - Port ID is not correct\n *      RT_ERR_NOT_INIT - Not Initialize\n * Note:\n *\n */\nrtk_api_ret_t rtk_switch_logicalPortCheck(rtk_port_t logicalPort)\n{\n    if(init_state != INIT_COMPLETED)\n        return RT_ERR_NOT_INIT;\n\n    if(logicalPort >= RTK_SWITCH_PORT_NUM)\n        return RT_ERR_FAILED;\n\n    if(halCtrl->l2p_port[logicalPort] == 0xFF)\n        return RT_ERR_FAILED;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_switch_isUtpPort\n * Description:\n *      Check is logical port a UTP port\n * Input:\n *      logicalPort     - logical port ID\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Port ID is a UTP port\n *      RT_ERR_FAILED   - Port ID is not a UTP port\n *      RT_ERR_NOT_INIT - Not Initialize\n * Note:\n *\n */\nrtk_api_ret_t rtk_switch_isUtpPort(rtk_port_t logicalPort)\n{\n    if(init_state != INIT_COMPLETED)\n        return RT_ERR_NOT_INIT;\n\n    if(logicalPort >= RTK_SWITCH_PORT_NUM)\n        return RT_ERR_FAILED;\n\n    if(halCtrl->log_port_type[logicalPort] == UTP_PORT)\n        return RT_ERR_OK;\n    else\n        return RT_ERR_FAILED;\n}\n\n/* Function Name:\n *      rtk_switch_isExtPort\n * Description:\n *      Check is logical port a Extension port\n * Input:\n *      logicalPort     - logical port ID\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Port ID is a EXT port\n *      RT_ERR_FAILED   - Port ID is not a EXT port\n *      RT_ERR_NOT_INIT - Not Initialize\n * Note:\n *\n */\nrtk_api_ret_t rtk_switch_isExtPort(rtk_port_t logicalPort)\n{\n    if(init_state != INIT_COMPLETED)\n        return RT_ERR_NOT_INIT;\n\n    if(logicalPort >= RTK_SWITCH_PORT_NUM)\n        return RT_ERR_FAILED;\n\n    if(halCtrl->log_port_type[logicalPort] == EXT_PORT)\n        return RT_ERR_OK;\n    else\n        return RT_ERR_FAILED;\n}\n\n\n/* Function Name:\n *      rtk_switch_isHsgPort\n * Description:\n *      Check is logical port a HSG port\n * Input:\n *      logicalPort     - logical port ID\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Port ID is a HSG port\n *      RT_ERR_FAILED   - Port ID is not a HSG port\n *      RT_ERR_NOT_INIT - Not Initialize\n * Note:\n *\n */\nrtk_api_ret_t rtk_switch_isHsgPort(rtk_port_t logicalPort)\n{\n    if(init_state != INIT_COMPLETED)\n        return RT_ERR_NOT_INIT;\n\n    if(logicalPort >= RTK_SWITCH_PORT_NUM)\n        return RT_ERR_FAILED;\n\n    if(logicalPort == halCtrl->hsg_logical_port)\n        return RT_ERR_OK;\n    else\n        return RT_ERR_FAILED;\n}\n\n/* Function Name:\n *      rtk_switch_isSgmiiPort\n * Description:\n *      Check is logical port a SGMII port\n * Input:\n *      logicalPort     - logical port ID\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Port ID is a SGMII port\n *      RT_ERR_FAILED   - Port ID is not a SGMII port\n *      RT_ERR_NOT_INIT - Not Initialize\n * Note:\n *\n */\nrtk_api_ret_t rtk_switch_isSgmiiPort(rtk_port_t logicalPort)\n{\n    if(init_state != INIT_COMPLETED)\n        return RT_ERR_NOT_INIT;\n\n    if(logicalPort >= RTK_SWITCH_PORT_NUM)\n        return RT_ERR_FAILED;\n\n    if( ((0x01 << logicalPort) & halCtrl->sg_logical_portmask) != 0)\n        return RT_ERR_OK;\n    else\n        return RT_ERR_FAILED;\n}\n\n/* Function Name:\n *      rtk_switch_isCPUPort\n * Description:\n *      Check is logical port a CPU port\n * Input:\n *      logicalPort     - logical port ID\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Port ID is a CPU port\n *      RT_ERR_FAILED   - Port ID is not a CPU port\n *      RT_ERR_NOT_INIT - Not Initialize\n * Note:\n *\n */\nrtk_api_ret_t rtk_switch_isCPUPort(rtk_port_t logicalPort)\n{\n    if(init_state != INIT_COMPLETED)\n        return RT_ERR_NOT_INIT;\n\n    if(logicalPort >= RTK_SWITCH_PORT_NUM)\n        return RT_ERR_FAILED;\n\n    if( ((0x01 << logicalPort) & halCtrl->valid_cpu_portmask) != 0)\n        return RT_ERR_OK;\n    else\n        return RT_ERR_FAILED;\n}\n\n/* Function Name:\n *      rtk_switch_isComboPort\n * Description:\n *      Check is logical port a Combo port\n * Input:\n *      logicalPort     - logical port ID\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Port ID is a combo port\n *      RT_ERR_FAILED   - Port ID is not a combo port\n *      RT_ERR_NOT_INIT - Not Initialize\n * Note:\n *\n */\nrtk_api_ret_t rtk_switch_isComboPort(rtk_port_t logicalPort)\n{\n    if(init_state != INIT_COMPLETED)\n        return RT_ERR_NOT_INIT;\n\n    if(logicalPort >= RTK_SWITCH_PORT_NUM)\n        return RT_ERR_FAILED;\n\n    if(halCtrl->combo_logical_port == logicalPort)\n        return RT_ERR_OK;\n    else\n        return RT_ERR_FAILED;\n}\n\n/* Function Name:\n *      rtk_switch_ComboPort_get\n * Description:\n *      Get Combo port ID\n * Input:\n *      None\n * Output:\n *      None\n * Return:\n *      Port ID of combo port\n * Note:\n *\n */\nrtk_uint32 rtk_switch_ComboPort_get(void)\n{\n    return halCtrl->combo_logical_port;\n}\n\n/* Function Name:\n *      rtk_switch_isPtpPort\n * Description:\n *      Check is logical port a PTP port\n * Input:\n *      logicalPort     - logical port ID\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Port ID is a PTP port\n *      RT_ERR_FAILED   - Port ID is not a PTP port\n *      RT_ERR_NOT_INIT - Not Initialize\n * Note:\n *\n */\nrtk_api_ret_t rtk_switch_isPtpPort(rtk_port_t logicalPort)\n{\n    if(init_state != INIT_COMPLETED)\n        return RT_ERR_NOT_INIT;\n\n    if(logicalPort >= RTK_SWITCH_PORT_NUM)\n        return RT_ERR_FAILED;\n\n    if(halCtrl->ptp_port[logicalPort] == 1)\n        return RT_ERR_OK;\n    else\n        return RT_ERR_FAILED;\n}\n\n/* Function Name:\n *      rtk_switch_port_L2P_get\n * Description:\n *      Get physical port ID\n * Input:\n *      logicalPort       - logical port ID\n * Output:\n *      None\n * Return:\n *      Physical port ID\n * Note:\n *\n */\nrtk_uint32 rtk_switch_port_L2P_get(rtk_port_t logicalPort)\n{\n    if(init_state != INIT_COMPLETED)\n        return UNDEFINE_PHY_PORT;\n\n    if(logicalPort >= RTK_SWITCH_PORT_NUM)\n        return UNDEFINE_PHY_PORT;\n\n    return (halCtrl->l2p_port[logicalPort]);\n}\n\n/* Function Name:\n *      rtk_switch_port_P2L_get\n * Description:\n *      Get logical port ID\n * Input:\n *      physicalPort       - physical port ID\n * Output:\n *      None\n * Return:\n *      logical port ID\n * Note:\n *\n */\nrtk_port_t rtk_switch_port_P2L_get(rtk_uint32 physicalPort)\n{\n    if(init_state != INIT_COMPLETED)\n        return UNDEFINE_PORT;\n\n    if(physicalPort >= RTK_SWITCH_PORT_NUM)\n        return UNDEFINE_PORT;\n\n    return (halCtrl->p2l_port[physicalPort]);\n}\n\n/* Function Name:\n *      rtk_switch_isPortMaskValid\n * Description:\n *      Check portmask is valid or not\n * Input:\n *      pPmask       - logical port mask\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - port mask is valid\n *      RT_ERR_FAILED       - port mask is not valid\n *      RT_ERR_NOT_INIT     - Not Initialize\n *      RT_ERR_NULL_POINTER - Null pointer\n * Note:\n *\n */\nrtk_api_ret_t rtk_switch_isPortMaskValid(rtk_portmask_t *pPmask)\n{\n    if(init_state != INIT_COMPLETED)\n        return RT_ERR_NOT_INIT;\n\n    if(NULL == pPmask)\n        return RT_ERR_NULL_POINTER;\n\n    if( (pPmask->bits[0] | halCtrl->valid_portmask) != halCtrl->valid_portmask )\n        return RT_ERR_FAILED;\n    else\n        return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_switch_isPortMaskUtp\n * Description:\n *      Check all ports in portmask are only UTP port\n * Input:\n *      pPmask       - logical port mask\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Only UTP port in port mask\n *      RT_ERR_FAILED       - Not only UTP port in port mask\n *      RT_ERR_NOT_INIT     - Not Initialize\n *      RT_ERR_NULL_POINTER - Null pointer\n * Note:\n *\n */\nrtk_api_ret_t rtk_switch_isPortMaskUtp(rtk_portmask_t *pPmask)\n{\n    if(init_state != INIT_COMPLETED)\n        return RT_ERR_NOT_INIT;\n\n    if(NULL == pPmask)\n        return RT_ERR_NULL_POINTER;\n\n    if( (pPmask->bits[0] | halCtrl->valid_utp_portmask) != halCtrl->valid_utp_portmask )\n        return RT_ERR_FAILED;\n    else\n        return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_switch_isPortMaskExt\n * Description:\n *      Check all ports in portmask are only EXT port\n * Input:\n *      pPmask       - logical port mask\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Only EXT port in port mask\n *      RT_ERR_FAILED       - Not only EXT port in port mask\n *      RT_ERR_NOT_INIT     - Not Initialize\n *      RT_ERR_NULL_POINTER - Null pointer\n * Note:\n *\n */\nrtk_api_ret_t rtk_switch_isPortMaskExt(rtk_portmask_t *pPmask)\n{\n    if(init_state != INIT_COMPLETED)\n        return RT_ERR_NOT_INIT;\n\n    if(NULL == pPmask)\n        return RT_ERR_NULL_POINTER;\n\n    if( (pPmask->bits[0] | halCtrl->valid_ext_portmask) != halCtrl->valid_ext_portmask )\n        return RT_ERR_FAILED;\n    else\n        return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_switch_portmask_L2P_get\n * Description:\n *      Get physicl portmask from logical portmask\n * Input:\n *      pLogicalPmask       - logical port mask\n * Output:\n *      pPhysicalPortmask   - physical port mask\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_NOT_INIT     - Not Initialize\n *      RT_ERR_NULL_POINTER - Null pointer\n *      RT_ERR_PORT_MASK    - Error port mask\n * Note:\n *\n */\nrtk_api_ret_t rtk_switch_portmask_L2P_get(rtk_portmask_t *pLogicalPmask, rtk_uint32 *pPhysicalPortmask)\n{\n    rtk_uint32 log_port, phy_port;\n\n    if(init_state != INIT_COMPLETED)\n        return RT_ERR_NOT_INIT;\n\n    if(NULL == pLogicalPmask)\n        return RT_ERR_NULL_POINTER;\n\n    if(NULL == pPhysicalPortmask)\n        return RT_ERR_NULL_POINTER;\n\n    if(rtk_switch_isPortMaskValid(pLogicalPmask) != RT_ERR_OK)\n        return RT_ERR_PORT_MASK;\n\n    /* reset physical port mask */\n    *pPhysicalPortmask = 0;\n\n    RTK_PORTMASK_SCAN((*pLogicalPmask), log_port)\n    {\n        phy_port = rtk_switch_port_L2P_get((rtk_port_t)log_port);\n        *pPhysicalPortmask |= (0x0001 << phy_port);\n    }\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_switch_portmask_P2L_get\n * Description:\n *      Get logical portmask from physical portmask\n * Input:\n *      physicalPortmask    - physical port mask\n * Output:\n *      pLogicalPmask       - logical port mask\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_NOT_INIT     - Not Initialize\n *      RT_ERR_NULL_POINTER - Null pointer\n *      RT_ERR_PORT_MASK    - Error port mask\n * Note:\n *\n */\nrtk_api_ret_t rtk_switch_portmask_P2L_get(rtk_uint32 physicalPortmask, rtk_portmask_t *pLogicalPmask)\n{\n    rtk_uint32 log_port, phy_port;\n\n    if(init_state != INIT_COMPLETED)\n        return RT_ERR_NOT_INIT;\n\n    if(NULL == pLogicalPmask)\n        return RT_ERR_NULL_POINTER;\n\n    RTK_PORTMASK_CLEAR(*pLogicalPmask);\n\n    for(phy_port = halCtrl->min_phy_port; phy_port <= halCtrl->max_phy_port; phy_port++)\n    {\n        if(physicalPortmask & (0x0001 << phy_port))\n        {\n            log_port = rtk_switch_port_P2L_get(phy_port);\n            if(log_port != UNDEFINE_PORT)\n            {\n                RTK_PORTMASK_PORT_SET(*pLogicalPmask, log_port);\n            }\n        }\n    }\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_switch_phyPortMask_get\n * Description:\n *      Get physical portmask\n * Input:\n *      None\n * Output:\n *      None\n * Return:\n *      0x00                - Not Initialize\n *      Other value         - Physical port mask\n * Note:\n *\n */\nrtk_uint32 rtk_switch_phyPortMask_get(void)\n{\n    if(init_state != INIT_COMPLETED)\n        return 0x00; /* No port in portmask */\n\n    return (halCtrl->phy_portmask);\n}\n\n/* Function Name:\n *      rtk_switch_logPortMask_get\n * Description:\n *      Get Logical portmask\n * Input:\n *      None\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_NOT_INIT     - Not Initialize\n *      RT_ERR_NULL_POINTER - Null pointer\n * Note:\n *\n */\nrtk_api_ret_t rtk_switch_logPortMask_get(rtk_portmask_t *pPortmask)\n{\n    if(init_state != INIT_COMPLETED)\n        return RT_ERR_FAILED;\n\n    if(NULL == pPortmask)\n        return RT_ERR_NULL_POINTER;\n\n    pPortmask->bits[0] = halCtrl->valid_portmask;\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_switch_init\n * Description:\n *      Set chip to default configuration enviroment\n * Input:\n *      None\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n * Note:\n *      The API can set chip registers to default configuration for different release chip model.\n */\nrtk_api_ret_t rtk_switch_init(void)\n{\n    rtk_uint32  retVal;\n    rtl8367c_rma_t rmaCfg;\n    switch_chip_t   switchChip;\n\n    /* probe switch */\n    if((retVal = rtk_switch_probe(&switchChip)) != RT_ERR_OK)\n        return retVal;\n\n    /* Set initial state */\n\n    if((retVal = rtk_switch_initialState_set(INIT_COMPLETED)) != RT_ERR_OK)\n        return retVal;\n\n    /* Initial */\n    switch(switchChip)\n    {\n        case CHIP_RTL8367C:\n            if((retVal = _rtk_switch_init_8367c()) != RT_ERR_OK)\n                return retVal;\n            break;\n        case CHIP_RTL8370B:\n            if((retVal = _rtk_switch_init_8370b()) != RT_ERR_OK)\n                return retVal;\n            break;\n        case CHIP_RTL8364B:\n            if((retVal = _rtk_switch_init_8364b()) != RT_ERR_OK)\n                return retVal;\n            break;\n        case CHIP_RTL8363SC_VB:\n            if((retVal = _rtk_switch_init_8363sc_vb()) != RT_ERR_OK)\n                return retVal;\n            break;\n        default:\n            return RT_ERR_CHIP_NOT_FOUND;\n    }\n\n    /* Set Old max packet length to 16K */\n    if((retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_MAX_LENGTH_LIMINT_IPG, RTL8367C_MAX_LENTH_CTRL_MASK, 3)) != RT_ERR_OK)\n        return retVal;\n\n    if((retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_MAX_LEN_RX_TX, RTL8367C_MAX_LEN_RX_TX_MASK, 3)) != RT_ERR_OK)\n        return retVal;\n\n    /* ACL Mode */\n    if((retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_ACL_ACCESS_MODE, RTL8367C_ACL_ACCESS_MODE_MASK, 1)) != RT_ERR_OK)\n        return retVal;\n\n    /* Max rate */\n    if((retVal = rtk_rate_igrBandwidthCtrlRate_set(halCtrl->hsg_logical_port, RTL8367C_QOS_RATE_INPUT_MAX_HSG, DISABLED, ENABLED)) != RT_ERR_OK)\n        return retVal;\n\n    if((retVal = rtk_rate_egrBandwidthCtrlRate_set(halCtrl->hsg_logical_port, RTL8367C_QOS_RATE_INPUT_MAX_HSG, ENABLED)) != RT_ERR_OK)\n        return retVal;\n\n    if((retVal = rtl8367c_setAsicReg(0x03fa, 0x0007)) != RT_ERR_OK)\n        return retVal;\n\n    /* Change unknown DA to per port setting */\n    if((retVal = rtl8367c_setAsicRegBits(RTL8367C_PORT_SECURIT_CTRL_REG, RTL8367C_UNKNOWN_UNICAST_DA_BEHAVE_MASK, 3)) != RT_ERR_OK)\n        return retVal;\n\n    /* LUT lookup OP = 1 */\n    if ((retVal = rtl8367c_setAsicLutIpLookupMethod(1))!=RT_ERR_OK)\n        return retVal;\n\n    /* Set RMA */\n    rmaCfg.portiso_leaky = 0;\n    rmaCfg.vlan_leaky = 0;\n    rmaCfg.keep_format = 0;\n    rmaCfg.trap_priority = 0;\n    rmaCfg.discard_storm_filter = 0;\n    rmaCfg.operation = 0;\n    if ((retVal = rtl8367c_setAsicRma(2, &rmaCfg))!=RT_ERR_OK)\n        return retVal;\n\n    /* Enable TX Mirror isolation leaky */\n    if ((retVal = rtl8367c_setAsicPortMirrorIsolationTxLeaky(ENABLED)) != RT_ERR_OK)\n        return retVal;\n\n    /* INT EN */\n    if((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_IO_MISC_FUNC, RTL8367C_INT_EN_OFFSET, 1)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_switch_portMaxPktLen_set\n * Description:\n *      Set Max packet length\n * Input:\n *      port    - Port ID\n *      speed   - Speed\n *      cfgId   - Configuration ID\n * Output:\n *      None.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Error Input\n * Note:\n */\nrtk_api_ret_t rtk_switch_portMaxPktLen_set(rtk_port_t port, rtk_switch_maxPktLen_linkSpeed_t speed, rtk_uint32 cfgId)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check Port Valid */\n    RTK_CHK_PORT_VALID(port);\n\n    if(speed >= MAXPKTLEN_LINK_SPEED_END)\n        return RT_ERR_INPUT;\n\n    if(cfgId > MAXPKTLEN_CFG_ID_MAX)\n        return RT_ERR_INPUT;\n\n    if((retVal = rtl8367c_setAsicMaxLength(rtk_switch_port_L2P_get(port), (rtk_uint32)speed, cfgId)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_switch_portMaxPktLen_get\n * Description:\n *      Get Max packet length\n * Input:\n *      port    - Port ID\n *      speed   - Speed\n * Output:\n *      pCfgId  - Configuration ID\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Error Input\n * Note:\n */\nrtk_api_ret_t rtk_switch_portMaxPktLen_get(rtk_port_t port, rtk_switch_maxPktLen_linkSpeed_t speed, rtk_uint32 *pCfgId)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check Port Valid */\n    RTK_CHK_PORT_VALID(port);\n\n    if(speed >= MAXPKTLEN_LINK_SPEED_END)\n        return RT_ERR_INPUT;\n\n    if(NULL == pCfgId)\n        return RT_ERR_NULL_POINTER;\n\n    if((retVal = rtl8367c_getAsicMaxLength(rtk_switch_port_L2P_get(port), (rtk_uint32)speed, pCfgId)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_switch_maxPktLenCfg_set\n * Description:\n *      Set Max packet length configuration\n * Input:\n *      cfgId   - Configuration ID\n *      pktLen  - Max packet length\n * Output:\n *      None.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Error Input\n * Note:\n */\nrtk_api_ret_t rtk_switch_maxPktLenCfg_set(rtk_uint32 cfgId, rtk_uint32 pktLen)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(cfgId > MAXPKTLEN_CFG_ID_MAX)\n        return RT_ERR_INPUT;\n\n    if(pktLen > RTK_SWITCH_MAX_PKTLEN)\n        return RT_ERR_INPUT;\n\n    if((retVal = rtl8367c_setAsicMaxLengthCfg(cfgId, pktLen)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_switch_maxPktLenCfg_get\n * Description:\n *      Get Max packet length configuration\n * Input:\n *      cfgId   - Configuration ID\n *      pPktLen - Max packet length\n * Output:\n *      None.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Error Input\n * Note:\n */\nrtk_api_ret_t rtk_switch_maxPktLenCfg_get(rtk_uint32 cfgId, rtk_uint32 *pPktLen)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(cfgId > MAXPKTLEN_CFG_ID_MAX)\n        return RT_ERR_INPUT;\n\n    if(NULL == pPktLen)\n        return RT_ERR_NULL_POINTER;\n\n    if((retVal = rtl8367c_getAsicMaxLengthCfg(cfgId, pPktLen)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_switch_greenEthernet_set\n * Description:\n *      Set all Ports Green Ethernet state.\n * Input:\n *      enable - Green Ethernet state.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - OK\n *      RT_ERR_FAILED   - Failed\n *      RT_ERR_SMI      - SMI access error\n *      RT_ERR_ENABLE   - Invalid enable input.\n * Note:\n *      This API can set all Ports Green Ethernet state.\n *      The configuration is as following:\n *      - DISABLE\n *      - ENABLE\n */\nrtk_api_ret_t rtk_switch_greenEthernet_set(rtk_enable_t enable)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32 port;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    RTK_SCAN_ALL_LOG_PORT(port)\n    {\n        if(rtk_switch_isUtpPort(port) == RT_ERR_OK)\n        {\n            if ((retVal = rtl8367c_setAsicPowerSaving(rtk_switch_port_L2P_get(port),enable))!=RT_ERR_OK)\n                return retVal;\n\n            if ((retVal = rtl8367c_setAsicGreenEthernet(rtk_switch_port_L2P_get(port), enable))!=RT_ERR_OK)\n                return retVal;\n        }\n    }\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_switch_greenEthernet_get\n * Description:\n *      Get all Ports Green Ethernet state.\n * Input:\n *      None\n * Output:\n *      pEnable - Green Ethernet state.\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n * Note:\n *      This API can get Green Ethernet state.\n */\nrtk_api_ret_t rtk_switch_greenEthernet_get(rtk_enable_t *pEnable)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32 port;\n    rtk_uint32 state;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    RTK_SCAN_ALL_LOG_PORT(port)\n    {\n        if(rtk_switch_isUtpPort(port) == RT_ERR_OK)\n        {\n            if ((retVal = rtl8367c_getAsicPowerSaving(rtk_switch_port_L2P_get(port), &state))!=RT_ERR_OK)\n                return retVal;\n\n            if(state == DISABLED)\n            {\n                *pEnable = DISABLED;\n                return RT_ERR_OK;\n            }\n\n            if ((retVal = rtl8367c_getAsicGreenEthernet(rtk_switch_port_L2P_get(port), &state))!=RT_ERR_OK)\n                return retVal;\n\n            if(state == DISABLED)\n            {\n                *pEnable = DISABLED;\n                return RT_ERR_OK;\n            }\n        }\n    }\n\n    *pEnable = ENABLED;\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_switch_maxLogicalPort_get\n * Description:\n *      Get Max logical port ID\n * Input:\n *      None\n * Output:\n *      None\n * Return:\n *      Max logical port\n * Note:\n *      This API can get max logical port\n */\nrtk_port_t rtk_switch_maxLogicalPort_get(void)\n{\n    rtk_port_t port, maxLogicalPort = 0;\n\n    /* Check initialization state */\n    if(rtk_switch_initialState_get() != INIT_COMPLETED)\n    {\n        return UNDEFINE_PORT;\n    }\n\n    for(port = 0; port < RTK_SWITCH_PORT_NUM; port++)\n    {\n        if( (halCtrl->log_port_type[port] == UTP_PORT) || (halCtrl->log_port_type[port] == EXT_PORT) )\n            maxLogicalPort = port;\n    }\n\n    return maxLogicalPort;\n}\n\n/* Function Name:\n *      rtk_switch_maxMeterId_get\n * Description:\n *      Get Max Meter ID\n * Input:\n *      None\n * Output:\n *      None\n * Return:\n *      0x00                - Not Initialize\n *      Other value         - Max Meter ID\n * Note:\n *\n */\nrtk_uint32 rtk_switch_maxMeterId_get(void)\n{\n    if(init_state != INIT_COMPLETED)\n        return 0x00;\n\n    return (halCtrl->max_meter_id);\n}\n\n/* Function Name:\n *      rtk_switch_maxLutAddrNumber_get\n * Description:\n *      Get Max LUT Address number\n * Input:\n *      None\n * Output:\n *      None\n * Return:\n *      0x00                - Not Initialize\n *      Other value         - Max LUT Address number\n * Note:\n *\n */\nrtk_uint32 rtk_switch_maxLutAddrNumber_get(void)\n{\n    if(init_state != INIT_COMPLETED)\n        return 0x00;\n\n    return (halCtrl->max_lut_addr_num);\n}\n\n/* Function Name:\n *      rtk_switch_isValidTrunkGrpId\n * Description:\n *      Check if trunk group is valid or not\n * Input:\n *      grpId       - Group ID\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Trunk Group ID is valid\n *      RT_ERR_LA_TRUNK_ID  - Trunk Group ID is not valid\n * Note:\n *\n */\nrtk_uint32 rtk_switch_isValidTrunkGrpId(rtk_uint32 grpId)\n{\n    if(init_state != INIT_COMPLETED)\n        return 0x00;\n\n    if( (halCtrl->trunk_group_mask & (0x01 << grpId) ) != 0)\n        return RT_ERR_OK;\n    else\n        return RT_ERR_LA_TRUNK_ID;\n\n}\n\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv.c",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * $Revision: 76306 $\n * $Date: 2017-03-08 15:13:58 +0800 (週三, 08 三月 2017) $\n *\n * Purpose : RTL8367C switch high-level API for RTL8367C\n * Feature :\n *\n */\n\n#include <rtl8367c_asicdrv.h>\n\n#if defined(RTK_X86_ASICDRV)\n#include <I2Clib.h>\n#else\n#include <smi.h>\n#endif\n\n/*for driver verify testing only*/\n#ifdef CONFIG_RTL8367C_ASICDRV_TEST\n#define CLE_VIRTUAL_REG_SIZE        0x10000\nrtk_uint16 CleVirtualReg[CLE_VIRTUAL_REG_SIZE];\n#endif\n\n#if defined(CONFIG_RTL865X_CLE) || defined (RTK_X86_CLE)\nrtk_uint32 cleDebuggingDisplay;\n#endif\n\n#ifdef EMBEDDED_SUPPORT\nextern void setReg(rtk_uint16, rtk_uint16);\nextern rtk_uint16 getReg(rtk_uint16);\n#endif\n\n/* Function Name:\n *      rtl8367c_setAsicRegBit\n * Description:\n *      Set a bit value of a specified register\n * Input:\n *      reg     - register's address\n *      bit     - bit location\n *      value   - value to set. It can be value 0 or 1.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n *      RT_ERR_INPUT    - Invalid input parameter\n * Note:\n *      Set a bit of a specified register to 1 or 0.\n */\nret_t rtl8367c_setAsicRegBit(rtk_uint32 reg, rtk_uint32 bit, rtk_uint32 value)\n{\n\n#if defined(RTK_X86_ASICDRV)\n    rtk_uint32 regData;\n    ret_t retVal;\n\n    if(bit >= RTL8367C_REGBITLENGTH)\n        return RT_ERR_INPUT;\n\n    retVal = Access_Read(reg, 2, &regData);\n    if(TRUE != retVal)\n        return RT_ERR_SMI;\n\n    if(0x8367B == cleDebuggingDisplay)\n        PRINT(\"R[0x%4.4x]=0x%4.4x\\n\", reg, regData);\n\n    if(value)\n        regData = regData | (1 << bit);\n    else\n        regData = regData & (~(1 << bit));\n\n    retVal = Access_Write(reg,2, regData);\n    if(TRUE != retVal)\n        return RT_ERR_SMI;\n\n    if(0x8367B == cleDebuggingDisplay)\n        PRINT(\"W[0x%4.4x]=0x%4.4x\\n\", reg, regData);\n\n\n#elif defined(CONFIG_RTL8367C_ASICDRV_TEST)\n\n    if(bit >= RTL8367C_REGBITLENGTH)\n        return RT_ERR_INPUT;\n\n    else if(reg >= CLE_VIRTUAL_REG_SIZE)\n        return RT_ERR_OUT_OF_RANGE;\n\n    if(value)\n    {\n        CleVirtualReg[reg] =  CleVirtualReg[reg] | (1 << bit);\n    }\n    else\n    {\n        CleVirtualReg[reg] =  CleVirtualReg[reg] & (~(1 << bit));\n    }\n\n    if(0x8367B == cleDebuggingDisplay)\n        PRINT(\"W[0x%4.4x]=0x%4.4x\\n\", reg, CleVirtualReg[reg]);\n\n#elif defined(EMBEDDED_SUPPORT)\n    rtk_uint16 tmp;\n\n    if(reg > RTL8367C_REGDATAMAX || value > 1)\n        return RT_ERR_INPUT;\n\n    tmp = getReg(reg);\n    tmp &= (1 << bitIdx);\n    tmp |= (value << bitIdx);\n    setReg(reg, tmp);\n\n#else\n    rtk_uint32 regData;\n    ret_t retVal;\n\n    if(bit >= RTL8367C_REGBITLENGTH)\n        return RT_ERR_INPUT;\n\n    retVal = smi_read(reg, &regData);\n    if(retVal != RT_ERR_OK)\n        return RT_ERR_SMI;\n\n  #ifdef CONFIG_RTL865X_CLE\n    if(0x8367B == cleDebuggingDisplay)\n        PRINT(\"R[0x%4.4x]=0x%4.4x\\n\", reg, regData);\n  #endif\n    if(value)\n        regData = regData | (1 << bit);\n    else\n        regData = regData & (~(1 << bit));\n\n    retVal = smi_write(reg, regData);\n    if(retVal != RT_ERR_OK)\n        return RT_ERR_SMI;\n\n  #ifdef CONFIG_RTL865X_CLE\n    if(0x8367B == cleDebuggingDisplay)\n        PRINT(\"W[0x%4.4x]=0x%4.4x\\n\", reg, regData);\n  #endif\n\n#endif\n    return RT_ERR_OK;\n}\n/* Function Name:\n *      rtl8367c_getAsicRegBit\n * Description:\n *      Get a bit value of a specified register\n * Input:\n *      reg     - register's address\n *      bit     - bit location\n *      value   - value to get.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n *      RT_ERR_INPUT    - Invalid input parameter\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicRegBit(rtk_uint32 reg, rtk_uint32 bit, rtk_uint32 *pValue)\n{\n\n#if defined(RTK_X86_ASICDRV)\n\n    rtk_uint32 regData;\n    ret_t retVal;\n\n    if(bit >= RTL8367C_REGBITLENGTH)\n        return RT_ERR_INPUT;\n\n    retVal = Access_Read(reg, 2, &regData);\n    if(TRUE != retVal)\n        return RT_ERR_SMI;\n\n    *pValue = (regData & (0x1 << bit)) >> bit;\n\n    if(0x8367B == cleDebuggingDisplay)\n        PRINT(\"R[0x%4.4x]=0x%4.4x\\n\", reg, regData);\n\n#elif defined(CONFIG_RTL8367C_ASICDRV_TEST)\n\n    if(bit >= RTL8367C_REGBITLENGTH)\n        return RT_ERR_INPUT;\n\n    if(reg >= CLE_VIRTUAL_REG_SIZE)\n        return RT_ERR_OUT_OF_RANGE;\n\n    *pValue = (CleVirtualReg[reg] & (0x1 << bit)) >> bit;\n\n    if(0x8367B == cleDebuggingDisplay)\n        PRINT(\"R[0x%4.4x]=0x%4.4x\\n\", reg, CleVirtualReg[reg]);\n\n#elif defined(EMBEDDED_SUPPORT)\n    rtk_uint16 tmp;\n\n    if(reg > RTL8367C_REGDATAMAX )\n        return RT_ERR_INPUT;\n\n    tmp = getReg(reg);\n    tmp = tmp >> bitIdx;\n    tmp &= 1;\n    *value = tmp;\n#else\n    rtk_uint32 regData;\n    ret_t retVal;\n\n    retVal = smi_read(reg, &regData);\n    if(retVal != RT_ERR_OK)\n        return RT_ERR_SMI;\n\n  #ifdef CONFIG_RTL865X_CLE\n    if(0x8367B == cleDebuggingDisplay)\n        PRINT(\"R[0x%4.4x]=0x%4.4x\\n\", reg, regData);\n  #endif\n\n    *pValue = (regData & (0x1 << bit)) >> bit;\n\n#endif\n    return RT_ERR_OK;\n}\n/* Function Name:\n *      rtl8367c_setAsicRegBits\n * Description:\n *      Set bits value of a specified register\n * Input:\n *      reg     - register's address\n *      bits    - bits mask for setting\n *      value   - bits value for setting\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n *      RT_ERR_INPUT    - Invalid input parameter\n * Note:\n *      Set bits of a specified register to value. Both bits and value are be treated as bit-mask\n */\nret_t rtl8367c_setAsicRegBits(rtk_uint32 reg, rtk_uint32 bits, rtk_uint32 value)\n{\n\n#if defined(RTK_X86_ASICDRV)\n\n    rtk_uint32 regData;\n    ret_t retVal;\n    rtk_uint32 bitsShift;\n    rtk_uint32 valueShifted;\n\n    if(bits >= (1 << RTL8367C_REGBITLENGTH) )\n        return RT_ERR_INPUT;\n\n    bitsShift = 0;\n    while(!(bits & (1 << bitsShift)))\n    {\n        bitsShift++;\n        if(bitsShift >= RTL8367C_REGBITLENGTH)\n            return RT_ERR_INPUT;\n    }\n\n    valueShifted = value << bitsShift;\n    if(valueShifted > RTL8367C_REGDATAMAX)\n        return RT_ERR_INPUT;\n\n    retVal = Access_Read(reg, 2, &regData);\n    if(TRUE != retVal)\n        return RT_ERR_SMI;\n\n    if(0x8367B == cleDebuggingDisplay)\n        PRINT(\"R[0x%4.4x]=0x%4.4x\\n\", reg, regData);\n\n    regData = regData & (~bits);\n    regData = regData | (valueShifted & bits);\n\n    retVal = Access_Write(reg,2, regData);\n    if(TRUE != retVal)\n        return RT_ERR_SMI;\n\n    if(0x8367B == cleDebuggingDisplay)\n        PRINT(\"W[0x%4.4x]=0x%4.4x\\n\", reg, regData);\n\n#elif defined(CONFIG_RTL8367C_ASICDRV_TEST)\n    rtk_uint32 regData;\n    rtk_uint32 bitsShift;\n    rtk_uint32 valueShifted;\n\n    if(bits >= (1 << RTL8367C_REGBITLENGTH) )\n        return RT_ERR_INPUT;\n\n    bitsShift = 0;\n    while(!(bits & (1 << bitsShift)))\n    {\n        bitsShift++;\n        if(bitsShift >= RTL8367C_REGBITLENGTH)\n            return RT_ERR_INPUT;\n    }\n    valueShifted = value << bitsShift;\n\n    if(valueShifted > RTL8367C_REGDATAMAX)\n        return RT_ERR_INPUT;\n\n    if(reg >= CLE_VIRTUAL_REG_SIZE)\n        return RT_ERR_OUT_OF_RANGE;\n\n    regData = CleVirtualReg[reg] & (~bits);\n    regData = regData | (valueShifted & bits);\n\n    CleVirtualReg[reg] = regData;\n\n    if(0x8367B == cleDebuggingDisplay)\n        PRINT(\"W[0x%4.4x]=0x%4.4x\\n\", reg, regData);\n\n#elif defined(EMBEDDED_SUPPORT)\n    rtk_uint32 regData;\n    rtk_uint32 bitsShift;\n    rtk_uint32 valueShifted;\n\n    if(reg > RTL8367C_REGDATAMAX )\n        return RT_ERR_INPUT;\n\n    if(bits >= (1 << RTL8367C_REGBITLENGTH) )\n        return RT_ERR_INPUT;\n\n    bitsShift = 0;\n    while(!(bits & (1 << bitsShift)))\n    {\n        bitsShift++;\n        if(bitsShift >= RTL8367C_REGBITLENGTH)\n            return RT_ERR_INPUT;\n    }\n\n    valueShifted = value << bitsShift;\n    if(valueShifted > RTL8367C_REGDATAMAX)\n        return RT_ERR_INPUT;\n\n    regData = getReg(reg);\n    regData = regData & (~bits);\n    regData = regData | (valueShifted & bits);\n\n    setReg(reg, regData);\n\n#else\n    rtk_uint32 regData;\n    ret_t retVal;\n    rtk_uint32 bitsShift;\n    rtk_uint32 valueShifted;\n\n    if(bits >= (1 << RTL8367C_REGBITLENGTH) )\n        return RT_ERR_INPUT;\n\n    bitsShift = 0;\n    while(!(bits & (1 << bitsShift)))\n    {\n        bitsShift++;\n        if(bitsShift >= RTL8367C_REGBITLENGTH)\n            return RT_ERR_INPUT;\n    }\n    valueShifted = value << bitsShift;\n\n    if(valueShifted > RTL8367C_REGDATAMAX)\n        return RT_ERR_INPUT;\n\n    retVal = smi_read(reg, &regData);\n    if(retVal != RT_ERR_OK)\n        return RT_ERR_SMI;\n  #ifdef CONFIG_RTL865X_CLE\n    if(0x8367B == cleDebuggingDisplay)\n        PRINT(\"R[0x%4.4x]=0x%4.4x\\n\", reg, regData);\n  #endif\n\n    regData = regData & (~bits);\n    regData = regData | (valueShifted & bits);\n\n    retVal = smi_write(reg, regData);\n    if(retVal != RT_ERR_OK)\n        return RT_ERR_SMI;\n  #ifdef CONFIG_RTL865X_CLE\n    if(0x8367B == cleDebuggingDisplay)\n        PRINT(\"W[0x%4.4x]=0x%4.4x\\n\", reg, regData);\n  #endif\n#endif\n    return RT_ERR_OK;\n}\n/* Function Name:\n *      rtl8367c_getAsicRegBits\n * Description:\n *      Get bits value of a specified register\n * Input:\n *      reg     - register's address\n *      bits    - bits mask for setting\n *      value   - bits value for setting\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n *      RT_ERR_INPUT    - Invalid input parameter\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicRegBits(rtk_uint32 reg, rtk_uint32 bits, rtk_uint32 *pValue)\n{\n\n#if defined(RTK_X86_ASICDRV)\n\n    rtk_uint32 regData;\n    ret_t retVal;\n    rtk_uint32 bitsShift;\n\n    if(bits >= (1 << RTL8367C_REGBITLENGTH) )\n        return RT_ERR_INPUT;\n\n    bitsShift = 0;\n    while(!(bits & (1 << bitsShift)))\n    {\n        bitsShift++;\n        if(bitsShift >= RTL8367C_REGBITLENGTH)\n            return RT_ERR_INPUT;\n    }\n\n    retVal = Access_Read(reg, 2, &regData);\n    if(TRUE != retVal)\n        return RT_ERR_SMI;\n\n    *pValue = (regData & bits) >> bitsShift;\n\n    if(0x8367B == cleDebuggingDisplay)\n        PRINT(\"R[0x%4.4x]=0x%4.4x\\n\", reg, regData);\n\n#elif defined(CONFIG_RTL8367C_ASICDRV_TEST)\n    rtk_uint32 bitsShift;\n\n    if(bits >= (1 << RTL8367C_REGBITLENGTH) )\n        return RT_ERR_INPUT;\n\n    bitsShift = 0;\n    while(!(bits & (1 << bitsShift)))\n    {\n        bitsShift++;\n        if(bitsShift >= RTL8367C_REGBITLENGTH)\n            return RT_ERR_INPUT;\n    }\n\n    if(reg >= CLE_VIRTUAL_REG_SIZE)\n        return RT_ERR_OUT_OF_RANGE;\n\n     *pValue = (CleVirtualReg[reg] & bits) >> bitsShift;\n\n    if(0x8367B == cleDebuggingDisplay)\n        PRINT(\"R[0x%4.4x]=0x%4.4x\\n\", reg, CleVirtualReg[reg]);\n\n#elif defined(EMBEDDED_SUPPORT)\n    rtk_uint32 regData;\n    rtk_uint32 bitsShift;\n\n    if(reg > RTL8367C_REGDATAMAX )\n        return RT_ERR_INPUT;\n\n    if(bits >= (1UL << RTL8367C_REGBITLENGTH) )\n        return RT_ERR_INPUT;\n\n    bitsShift = 0;\n    while(!(bits & (1UL << bitsShift)))\n    {\n        bitsShift++;\n        if(bitsShift >= RTL8367C_REGBITLENGTH)\n            return RT_ERR_INPUT;\n    }\n\n    regData = getReg(reg);\n    *value = (regData & bits) >> bitsShift;\n\n#else\n    rtk_uint32 regData;\n    ret_t retVal;\n    rtk_uint32 bitsShift;\n\n    if(bits>= (1<<RTL8367C_REGBITLENGTH) )\n        return RT_ERR_INPUT;\n\n    bitsShift = 0;\n    while(!(bits & (1 << bitsShift)))\n    {\n        bitsShift++;\n        if(bitsShift >= RTL8367C_REGBITLENGTH)\n            return RT_ERR_INPUT;\n    }\n\n    retVal = smi_read(reg, &regData);\n    if(retVal != RT_ERR_OK) return RT_ERR_SMI;\n\n    *pValue = (regData & bits) >> bitsShift;\n  #ifdef CONFIG_RTL865X_CLE\n    if(0x8367B == cleDebuggingDisplay)\n        PRINT(\"R[0x%4.4x]=0x%4.4x\\n\",reg, regData);\n  #endif\n\n#endif\n    return RT_ERR_OK;\n}\n/* Function Name:\n *      rtl8367c_setAsicReg\n * Description:\n *      Set content of asic register\n * Input:\n *      reg     - register's address\n *      value   - Value setting to register\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n * Note:\n *      The value will be set to ASIC mapping address only and it is always return RT_ERR_OK while setting un-mapping address registers\n */\nret_t rtl8367c_setAsicReg(rtk_uint32 reg, rtk_uint32 value)\n{\n#if defined(RTK_X86_ASICDRV)/*RTK-CNSD2-NickWu-20061222: for x86 compile*/\n\n    ret_t retVal;\n\n    retVal = Access_Write(reg,2,value);\n    if(TRUE != retVal) return RT_ERR_SMI;\n\n    if(0x8367B == cleDebuggingDisplay)\n        PRINT(\"W[0x%4.4x]=0x%4.4x\\n\",reg,value);\n\n#elif defined(CONFIG_RTL8367C_ASICDRV_TEST)\n\n    /*MIBs emulating*/\n    if(reg == RTL8367C_REG_MIB_ADDRESS)\n    {\n        CleVirtualReg[RTL8367C_MIB_COUNTER_BASE_REG] = 0x1;\n        CleVirtualReg[RTL8367C_MIB_COUNTER_BASE_REG+1] = 0x2;\n        CleVirtualReg[RTL8367C_MIB_COUNTER_BASE_REG+2] = 0x3;\n        CleVirtualReg[RTL8367C_MIB_COUNTER_BASE_REG+3] = 0x4;\n    }\n\n    if(reg >= CLE_VIRTUAL_REG_SIZE)\n        return RT_ERR_OUT_OF_RANGE;\n\n    CleVirtualReg[reg] = value;\n\n    if(0x8367B == cleDebuggingDisplay)\n        PRINT(\"W[0x%4.4x]=0x%4.4x\\n\",reg,CleVirtualReg[reg]);\n\n#elif defined(EMBEDDED_SUPPORT)\n    if(reg > RTL8367C_REGDATAMAX || value > RTL8367C_REGDATAMAX )\n        return RT_ERR_INPUT;\n\n    setReg(reg, value);\n\n#else\n    ret_t retVal;\n\n    retVal = smi_write(reg, value);\n    if(retVal != RT_ERR_OK)\n        return RT_ERR_SMI;\n  #ifdef CONFIG_RTL865X_CLE\n    if(0x8367B == cleDebuggingDisplay)\n        PRINT(\"W[0x%4.4x]=0x%4.4x\\n\",reg,value);\n  #endif\n\n#endif\n\n    return RT_ERR_OK;\n}\n/* Function Name:\n *      rtl8367c_getAsicReg\n * Description:\n *      Get content of asic register\n * Input:\n *      reg     - register's address\n *      value   - Value setting to register\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n * Note:\n *      Value 0x0000 will be returned for ASIC un-mapping address\n */\nret_t rtl8367c_getAsicReg(rtk_uint32 reg, rtk_uint32 *pValue)\n{\n\n#if defined(RTK_X86_ASICDRV)\n\n    rtk_uint32 regData;\n    ret_t retVal;\n\n    retVal = Access_Read(reg, 2, &regData);\n    if(TRUE != retVal)\n        return RT_ERR_SMI;\n\n    *pValue = regData;\n\n    if(0x8367B == cleDebuggingDisplay)\n        PRINT(\"R[0x%4.4x]=0x%4.4x\\n\", reg, regData);\n\n#elif defined(CONFIG_RTL8367C_ASICDRV_TEST)\n    if(reg >= CLE_VIRTUAL_REG_SIZE)\n        return RT_ERR_OUT_OF_RANGE;\n\n    *pValue = CleVirtualReg[reg];\n\n    if(0x8367B == cleDebuggingDisplay)\n        PRINT(\"R[0x%4.4x]=0x%4.4x\\n\", reg, CleVirtualReg[reg]);\n\n#elif defined(EMBEDDED_SUPPORT)\n    if(reg > RTL8367C_REGDATAMAX  )\n        return RT_ERR_INPUT;\n\n    *value = getReg(reg);\n\n#else\n    rtk_uint32 regData;\n    ret_t retVal;\n\n    retVal = smi_read(reg, &regData);\n    if(retVal != RT_ERR_OK)\n        return RT_ERR_SMI;\n\n    *pValue = regData;\n  #ifdef CONFIG_RTL865X_CLE\n    if(0x8367B == cleDebuggingDisplay)\n        PRINT(\"R[0x%4.4x]=0x%4.4x\\n\", reg, regData);\n  #endif\n\n#endif\n\n    return RT_ERR_OK;\n}\n\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_acl.c",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * $Revision: 76306 $\n * $Date: 2017-03-08 15:13:58 +0800 (週三, 08 三月 2017) $\n *\n * Purpose : RTL8367C switch high-level API for RTL8367C\n * Feature : ACL related function drivers\n *\n */\n#include <rtl8367c_asicdrv_acl.h>\n\n#include <string.h>\n\n#if defined(CONFIG_RTL8367C_ASICDRV_TEST)\nrtl8367c_aclrulesmi Rtl8370sVirtualAclRuleTable[RTL8367C_ACLRULENO];\nrtk_uint16 Rtl8370sVirtualAclActTable[RTL8367C_ACLRULENO][RTL8367C_ACL_ACT_TABLE_LEN];\n#endif\n\n/*\n    Exchange structure type define with MMI and SMI\n*/\nstatic void _rtl8367c_aclRuleStSmi2User( rtl8367c_aclrule *pAclUser, rtl8367c_aclrulesmi *pAclSmi)\n{\n    rtk_uint8 *care_ptr, *data_ptr;\n    rtk_uint8 care_tmp, data_tmp;\n    rtk_uint32 i;\n\n    pAclUser->data_bits.active_portmsk = (((pAclSmi->data_bits_ext.rule_info >> 1) & 0x0007) << 8) | ((pAclSmi->data_bits.rule_info >> 8) & 0x00FF);\n    pAclUser->data_bits.type = (pAclSmi->data_bits.rule_info & 0x0007);\n    pAclUser->data_bits.tag_exist = (pAclSmi->data_bits.rule_info & 0x00F8) >> 3;\n\n    care_ptr = (rtk_uint8*)&pAclSmi->care_bits;\n    data_ptr = (rtk_uint8*)&pAclSmi->data_bits;\n\n    for ( i = 0; i < sizeof(struct acl_rule_smi_st); i++)\n    {\n        care_tmp = *(care_ptr + i) ^ (*(data_ptr + i));\n        data_tmp = *(data_ptr + i);\n\n        *(care_ptr + i) = care_tmp;\n        *(data_ptr + i) = data_tmp;\n    }\n\n    care_ptr = (rtk_uint8*)&pAclSmi->care_bits_ext;\n    data_ptr = (rtk_uint8*)&pAclSmi->data_bits_ext;\n    care_tmp = (*care_ptr) ^ (*data_ptr);\n    data_tmp = (*data_ptr);\n    *care_ptr = care_tmp;\n    *data_ptr = data_tmp;\n\n    for(i = 0; i < RTL8367C_ACLRULEFIELDNO; i++)\n        pAclUser->data_bits.field[i] = pAclSmi->data_bits.field[i];\n\n    pAclUser->valid = pAclSmi->valid;\n\n    pAclUser->care_bits.active_portmsk = (((pAclSmi->care_bits_ext.rule_info >> 1) & 0x0007) << 8) | ((pAclSmi->care_bits.rule_info >> 8) & 0x00FF);\n    pAclUser->care_bits.type = (pAclSmi->care_bits.rule_info & 0x0007);\n    pAclUser->care_bits.tag_exist = (pAclSmi->care_bits.rule_info & 0x00F8) >> 3;\n\n    for(i = 0; i < RTL8367C_ACLRULEFIELDNO; i++)\n        pAclUser->care_bits.field[i] = pAclSmi->care_bits.field[i];\n}\n\n/*\n    Exchange structure type define with MMI and SMI\n*/\nstatic void _rtl8367c_aclRuleStUser2Smi(rtl8367c_aclrule *pAclUser, rtl8367c_aclrulesmi *pAclSmi)\n{\n    rtk_uint8 *care_ptr, *data_ptr;\n    rtk_uint8 care_tmp, data_tmp;\n    rtk_uint32 i;\n\n    pAclSmi->data_bits_ext.rule_info = ((pAclUser->data_bits.active_portmsk >> 8) & 0x7) << 1;\n    pAclSmi->data_bits.rule_info = ((pAclUser->data_bits.active_portmsk & 0xff) << 8) | ((pAclUser->data_bits.tag_exist & 0x1F) << 3) | (pAclUser->data_bits.type & 0x07);\n\n    for(i = 0;i < RTL8367C_ACLRULEFIELDNO; i++)\n        pAclSmi->data_bits.field[i] = pAclUser->data_bits.field[i];\n\n    pAclSmi->valid = pAclUser->valid;\n\n    pAclSmi->care_bits_ext.rule_info = ((pAclUser->care_bits.active_portmsk >> 8) & 0x7) << 1;\n    pAclSmi->care_bits.rule_info = ((pAclUser->care_bits.active_portmsk & 0xff) << 8) | ((pAclUser->care_bits.tag_exist & 0x1F) << 3) | (pAclUser->care_bits.type & 0x07);\n\n    for(i = 0; i < RTL8367C_ACLRULEFIELDNO; i++)\n        pAclSmi->care_bits.field[i] = pAclUser->care_bits.field[i];\n\n    care_ptr = (rtk_uint8*)&pAclSmi->care_bits;\n    data_ptr = (rtk_uint8*)&pAclSmi->data_bits;\n\n    for ( i = 0; i < sizeof(struct acl_rule_smi_st); i++)\n    {\n        care_tmp = *(care_ptr + i) & ~(*(data_ptr + i));\n        data_tmp = *(care_ptr + i) & *(data_ptr + i);\n\n        *(care_ptr + i) = care_tmp;\n        *(data_ptr + i) = data_tmp;\n    }\n\n    care_ptr = (rtk_uint8*)&pAclSmi->care_bits_ext;\n    data_ptr = (rtk_uint8*)&pAclSmi->data_bits_ext;\n    care_tmp = *care_ptr & ~(*data_ptr);\n    data_tmp = *care_ptr & *data_ptr;\n\n    *care_ptr = care_tmp;\n    *data_ptr = data_tmp;\n}\n\n/*\n    Exchange structure type define with MMI and SMI\n*/\nstatic void _rtl8367c_aclActStSmi2User(rtl8367c_acl_act_t *pAclUser, rtk_uint16 *pAclSmi)\n{\n    pAclUser->cact = (pAclSmi[0] & 0x00C0) >> 6;\n    pAclUser->cvidx_cact = (pAclSmi[0] & 0x003F) | (((pAclSmi[3] & 0x0008) >> 3) << 6);\n\n    pAclUser->sact = (pAclSmi[0] & 0xC000) >> 14;\n    pAclUser->svidx_sact = ((pAclSmi[0] & 0x3F00) >> 8) | (((pAclSmi[3] & 0x0010) >> 4) << 6);\n\n    pAclUser->aclmeteridx = (pAclSmi[1] & 0x003F) | (((pAclSmi[3] & 0x0020) >> 5) << 6);\n\n    pAclUser->fwdact = (pAclSmi[1] & 0xC000) >> 14;\n    pAclUser->fwdpmask = ((pAclSmi[1] & 0x3FC0) >> 6) | (((pAclSmi[3] & 0x01C0) >> 6) << 8);\n\n    pAclUser->priact = (pAclSmi[2] & 0x00C0) >> 6;\n    pAclUser->pridx = (pAclSmi[2] & 0x003F) | (((pAclSmi[3] & 0x0200) >> 9) << 6);\n\n    pAclUser->aclint = (pAclSmi[2] & 0x2000) >> 13;\n    pAclUser->gpio_en = (pAclSmi[2] & 0x1000) >> 12;\n    pAclUser->gpio_pin = (pAclSmi[2] & 0x0F00) >> 8;\n\n    pAclUser->cact_ext = (pAclSmi[2] & 0xC000) >> 14;\n    pAclUser->tag_fmt = (pAclSmi[3] & 0x0003);\n    pAclUser->fwdact_ext = (pAclSmi[3] & 0x0004) >> 2;\n}\n\n/*\n    Exchange structure type define with MMI and SMI\n*/\nstatic void _rtl8367c_aclActStUser2Smi(rtl8367c_acl_act_t *pAclUser, rtk_uint16 *pAclSmi)\n{\n    pAclSmi[0] |= (pAclUser->cvidx_cact & 0x003F);\n    pAclSmi[0] |= (pAclUser->cact & 0x0003) << 6;\n    pAclSmi[0] |= (pAclUser->svidx_sact & 0x003F) << 8;\n    pAclSmi[0] |= (pAclUser->sact & 0x0003) << 14;\n\n    pAclSmi[1] |= (pAclUser->aclmeteridx & 0x003F);\n    pAclSmi[1] |= (pAclUser->fwdpmask & 0x00FF) << 6;\n    pAclSmi[1] |= (pAclUser->fwdact & 0x0003) << 14;\n\n    pAclSmi[2] |= (pAclUser->pridx & 0x003F);\n    pAclSmi[2] |= (pAclUser->priact & 0x0003) << 6;\n    pAclSmi[2] |= (pAclUser->gpio_pin & 0x000F) << 8;\n    pAclSmi[2] |= (pAclUser->gpio_en & 0x0001) << 12;\n    pAclSmi[2] |= (pAclUser->aclint & 0x0001) << 13;\n    pAclSmi[2] |= (pAclUser->cact_ext & 0x0003) << 14;\n\n    pAclSmi[3] |= (pAclUser->tag_fmt & 0x0003);\n    pAclSmi[3] |= (pAclUser->fwdact_ext & 0x0001) << 2;\n    pAclSmi[3] |= ((pAclUser->cvidx_cact & 0x0040) >> 6) << 3;\n    pAclSmi[3] |= ((pAclUser->svidx_sact & 0x0040) >> 6) << 4;\n    pAclSmi[3] |= ((pAclUser->aclmeteridx & 0x0040) >> 6) << 5;\n    pAclSmi[3] |= ((pAclUser->fwdpmask & 0x0700) >> 8) << 6;\n    pAclSmi[3] |= ((pAclUser->pridx & 0x0040) >> 6) << 9;\n}\n\n/* Function Name:\n *      rtl8367c_setAsicAcl\n * Description:\n *      Set port acl function enable/disable\n * Input:\n *      port    - Physical port number (0~10)\n *      enabled - 1: enabled, 0: disabled\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n *      RT_ERR_PORT_ID  - Invalid port number\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicAcl(rtk_uint32 port, rtk_uint32 enabled)\n{\n    if(port > RTL8367C_PORTIDMAX)\n        return RT_ERR_PORT_ID;\n\n    return rtl8367c_setAsicRegBit(RTL8367C_ACL_ENABLE_REG, port, enabled);\n}\n/* Function Name:\n *      rtl8367c_getAsicAcl\n * Description:\n *      Get port acl function enable/disable\n * Input:\n *      port    - Physical port number (0~10)\n *      enabled - 1: enabled, 0: disabled\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n *      RT_ERR_PORT_ID  - Invalid port number\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicAcl(rtk_uint32 port, rtk_uint32* pEnabled)\n{\n    if(port > RTL8367C_PORTIDMAX)\n        return RT_ERR_PORT_ID;\n\n    return rtl8367c_getAsicRegBit(RTL8367C_ACL_ENABLE_REG, port, pEnabled);\n}\n/* Function Name:\n *      rtl8367c_setAsicAclUnmatchedPermit\n * Description:\n *      Set port acl function unmatched permit action\n * Input:\n *      port    - Physical port number (0~10)\n *      enabled - 1: enabled, 0: disabled\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n *      RT_ERR_PORT_ID  - Invalid port number\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicAclUnmatchedPermit(rtk_uint32 port, rtk_uint32 enabled)\n{\n    if(port > RTL8367C_PORTIDMAX)\n        return RT_ERR_PORT_ID;\n\n    return rtl8367c_setAsicRegBit(RTL8367C_ACL_UNMATCH_PERMIT_REG, port, enabled);\n}\n/* Function Name:\n *      rtl8367c_getAsicAclUnmatchedPermit\n * Description:\n *      Get port acl function unmatched permit action\n * Input:\n *      port    - Physical port number (0~10)\n *      enabled - 1: enabled, 0: disabled\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n *      RT_ERR_PORT_ID  - Invalid port number\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicAclUnmatchedPermit(rtk_uint32 port, rtk_uint32* pEnabled)\n{\n    if(port > RTL8367C_PORTIDMAX)\n        return RT_ERR_PORT_ID;\n\n    return rtl8367c_getAsicRegBit(RTL8367C_ACL_UNMATCH_PERMIT_REG, port, pEnabled);\n}\n\n/* Function Name:\n *      rtl8367c_setAsicAclRule\n * Description:\n *      Set acl rule content\n * Input:\n *      index   - ACL rule index (0-95) of 96 ACL rules\n *      pAclRule - ACL rule stucture for setting\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - Success\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_OUT_OF_RANGE     - Invalid ACL rule index (0-95)\n * Note:\n *      System supported 95 shared 289-bit ACL ingress rule. Index was available at range 0-95 only.\n *      If software want to modify ACL rule, the ACL function should be disable at first or unspecify\n *      acl action will be executed.\n *      One ACL rule structure has three parts setting:\n *      Bit 0-147       Data Bits of this Rule\n *      Bit 148     Valid Bit\n *      Bit 149-296 Care Bits of this Rule\n *      There are four kinds of field in Data Bits and Care Bits: Active Portmask, Type, Tag Exist, and 8 fields\n */\nret_t rtl8367c_setAsicAclRule(rtk_uint32 index, rtl8367c_aclrule* pAclRule)\n{\n    rtl8367c_aclrulesmi aclRuleSmi;\n    rtk_uint16* tableAddr;\n    rtk_uint32 regAddr;\n    rtk_uint32  regData;\n    rtk_uint32 i;\n    ret_t retVal;\n\n    if(index > RTL8367C_ACLRULEMAX)\n        return RT_ERR_OUT_OF_RANGE;\n\n    memset(&aclRuleSmi, 0x00, sizeof(rtl8367c_aclrulesmi));\n\n    _rtl8367c_aclRuleStUser2Smi(pAclRule, &aclRuleSmi);\n\n    /* Write valid bit = 0 */\n    regAddr = RTL8367C_TABLE_ACCESS_ADDR_REG;\n    if(index >= 64)\n        regData = RTL8367C_ACLRULETBADDR2(DATABITS, index);\n    else\n        regData = RTL8367C_ACLRULETBADDR(DATABITS, index);\n    retVal = rtl8367c_setAsicReg(regAddr,regData);\n    if(retVal !=RT_ERR_OK)\n        return retVal;\n\n    retVal = rtl8367c_setAsicRegBits(RTL8367C_TABLE_ACCESS_WRDATA_REG(RTL8367C_ACLRULETBLEN), 0x1, 0);\n    if(retVal !=RT_ERR_OK)\n        return retVal;\n\n    regAddr = RTL8367C_TABLE_ACCESS_CTRL_REG;\n    regData = RTL8367C_TABLE_ACCESS_REG_DATA(TB_OP_WRITE, TB_TARGET_ACLRULE);\n    retVal = rtl8367c_setAsicReg(regAddr, regData);\n    if(retVal !=RT_ERR_OK)\n        return retVal;\n\n\n\n    /* Write ACS_ADR register */\n    regAddr = RTL8367C_TABLE_ACCESS_ADDR_REG;\n    if(index >= 64)\n        regData = RTL8367C_ACLRULETBADDR2(CAREBITS, index);\n    else\n        regData = RTL8367C_ACLRULETBADDR(CAREBITS, index);\n    retVal = rtl8367c_setAsicReg(regAddr, regData);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    /* Write Care Bits to ACS_DATA registers */\n     tableAddr = (rtk_uint16*)&aclRuleSmi.care_bits;\n     regAddr = RTL8367C_TABLE_ACCESS_WRDATA_BASE;\n\n    for(i = 0; i < RTL8367C_ACLRULETBLEN; i++)\n    {\n        regData = *tableAddr;\n        retVal = rtl8367c_setAsicReg(regAddr, regData);\n        if(retVal != RT_ERR_OK)\n            return retVal;\n\n        regAddr++;\n        tableAddr++;\n    }\n    retVal = rtl8367c_setAsicRegBits(RTL8367C_TABLE_ACCESS_WRDATA_REG(RTL8367C_ACLRULETBLEN), (0x0007 << 1), (aclRuleSmi.care_bits_ext.rule_info >> 1) & 0x0007);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    /* Write ACS_CMD register */\n    regAddr = RTL8367C_TABLE_ACCESS_CTRL_REG;\n    regData = RTL8367C_TABLE_ACCESS_REG_DATA(TB_OP_WRITE, TB_TARGET_ACLRULE);\n    retVal = rtl8367c_setAsicRegBits(regAddr, RTL8367C_TABLE_TYPE_MASK | RTL8367C_COMMAND_TYPE_MASK,regData);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n\n\n    /* Write ACS_ADR register for data bits */\n    regAddr = RTL8367C_TABLE_ACCESS_ADDR_REG;\n    if(index >= 64)\n        regData = RTL8367C_ACLRULETBADDR2(DATABITS, index);\n    else\n        regData = RTL8367C_ACLRULETBADDR(DATABITS, index);\n\n    retVal = rtl8367c_setAsicReg(regAddr, regData);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    /* Write Data Bits to ACS_DATA registers */\n     tableAddr = (rtk_uint16*)&aclRuleSmi.data_bits;\n     regAddr = RTL8367C_TABLE_ACCESS_WRDATA_BASE;\n\n    for(i = 0; i < RTL8367C_ACLRULETBLEN; i++)\n    {\n        regData = *tableAddr;\n        retVal = rtl8367c_setAsicReg(regAddr, regData);\n        if(retVal != RT_ERR_OK)\n            return retVal;\n\n        regAddr++;\n        tableAddr++;\n    }\n\n    retVal = rtl8367c_setAsicRegBit(RTL8367C_TABLE_ACCESS_WRDATA_REG(RTL8367C_ACLRULETBLEN), 0, aclRuleSmi.valid);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n    retVal = rtl8367c_setAsicRegBits(RTL8367C_TABLE_ACCESS_WRDATA_REG(RTL8367C_ACLRULETBLEN), (0x0007 << 1), (aclRuleSmi.data_bits_ext.rule_info >> 1) & 0x0007);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    /* Write ACS_CMD register for care bits*/\n    regAddr = RTL8367C_TABLE_ACCESS_CTRL_REG;\n    regData = RTL8367C_TABLE_ACCESS_REG_DATA(TB_OP_WRITE, TB_TARGET_ACLRULE);\n    retVal = rtl8367c_setAsicRegBits(regAddr, RTL8367C_TABLE_TYPE_MASK | RTL8367C_COMMAND_TYPE_MASK, regData);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n#ifdef CONFIG_RTL8367C_ASICDRV_TEST\n    memcpy(&Rtl8370sVirtualAclRuleTable[index], &aclRuleSmi, sizeof(rtl8367c_aclrulesmi));\n#endif\n\n    return RT_ERR_OK;\n}\n/* Function Name:\n *      rtl8367c_getAsicAclRule\n * Description:\n *      Get acl rule content\n * Input:\n *      index   - ACL rule index (0-63) of 64 ACL rules\n *      pAclRule - ACL rule stucture for setting\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - Success\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_OUT_OF_RANGE     - Invalid ACL rule index (0-63)\n  * Note:\n *      None\n */\nret_t rtl8367c_getAsicAclRule(rtk_uint32 index, rtl8367c_aclrule *pAclRule)\n{\n    rtl8367c_aclrulesmi aclRuleSmi;\n    rtk_uint32 regAddr, regData;\n    ret_t retVal;\n    rtk_uint16* tableAddr;\n    rtk_uint32 i;\n\n    if(index > RTL8367C_ACLRULEMAX)\n        return RT_ERR_OUT_OF_RANGE;\n\n    memset(&aclRuleSmi, 0x00, sizeof(rtl8367c_aclrulesmi));\n\n    /* Write ACS_ADR register for data bits */\n    regAddr = RTL8367C_TABLE_ACCESS_ADDR_REG;\n    if(index >= 64)\n        regData = RTL8367C_ACLRULETBADDR2(DATABITS, index);\n    else\n        regData = RTL8367C_ACLRULETBADDR(DATABITS, index);\n\n    retVal = rtl8367c_setAsicReg(regAddr, regData);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n\n    /* Write ACS_CMD register */\n    regAddr = RTL8367C_TABLE_ACCESS_CTRL_REG;\n    regData = RTL8367C_TABLE_ACCESS_REG_DATA(TB_OP_READ, TB_TARGET_ACLRULE);\n    retVal = rtl8367c_setAsicRegBits(regAddr, RTL8367C_TABLE_TYPE_MASK | RTL8367C_COMMAND_TYPE_MASK, regData);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    /* Read Data Bits */\n    regAddr = RTL8367C_TABLE_ACCESS_RDDATA_BASE;\n    tableAddr = (rtk_uint16*)&aclRuleSmi.data_bits;\n    for(i = 0; i < RTL8367C_ACLRULETBLEN; i++)\n    {\n        retVal = rtl8367c_getAsicReg(regAddr, &regData);\n        if(retVal != RT_ERR_OK)\n            return retVal;\n\n        *tableAddr = regData;\n\n        regAddr ++;\n        tableAddr ++;\n    }\n\n    /* Read Valid Bit */\n    retVal = rtl8367c_getAsicRegBit(RTL8367C_TABLE_ACCESS_RDDATA_REG(RTL8367C_ACLRULETBLEN), 0, &regData);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n    aclRuleSmi.valid = regData & 0x1;\n    /* Read active_portmsk_ext Bits */\n    retVal = rtl8367c_getAsicRegBits(RTL8367C_TABLE_ACCESS_RDDATA_REG(RTL8367C_ACLRULETBLEN), 0x7<<1, &regData);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n    aclRuleSmi.data_bits_ext.rule_info = (regData % 0x0007) << 1;\n\n\n    /* Write ACS_ADR register for carebits*/\n    regAddr = RTL8367C_TABLE_ACCESS_ADDR_REG;\n    if(index >= 64)\n        regData = RTL8367C_ACLRULETBADDR2(CAREBITS, index);\n    else\n        regData = RTL8367C_ACLRULETBADDR(CAREBITS, index);\n\n    retVal = rtl8367c_setAsicReg(regAddr, regData);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    /* Write ACS_CMD register */\n    regAddr = RTL8367C_TABLE_ACCESS_CTRL_REG;\n    regData = RTL8367C_TABLE_ACCESS_REG_DATA(TB_OP_READ, TB_TARGET_ACLRULE);\n    retVal = rtl8367c_setAsicRegBits(regAddr, RTL8367C_TABLE_TYPE_MASK | RTL8367C_COMMAND_TYPE_MASK, regData);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    /* Read Care Bits */\n    regAddr = RTL8367C_TABLE_ACCESS_RDDATA_BASE;\n    tableAddr = (rtk_uint16*)&aclRuleSmi.care_bits;\n    for(i = 0; i < RTL8367C_ACLRULETBLEN; i++)\n    {\n        retVal = rtl8367c_getAsicReg(regAddr, &regData);\n        if(retVal != RT_ERR_OK)\n            return retVal;\n\n        *tableAddr = regData;\n\n        regAddr ++;\n        tableAddr ++;\n    }\n    /* Read active_portmsk_ext care Bits */\n    retVal = rtl8367c_getAsicRegBits(RTL8367C_TABLE_ACCESS_RDDATA_REG(RTL8367C_ACLRULETBLEN), 0x7<<1, &regData);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n    aclRuleSmi.care_bits_ext.rule_info = (regData & 0x0007) << 1;\n\n#ifdef CONFIG_RTL8367C_ASICDRV_TEST\n    memcpy(&aclRuleSmi,&Rtl8370sVirtualAclRuleTable[index], sizeof(rtl8367c_aclrulesmi));\n#endif\n\n     _rtl8367c_aclRuleStSmi2User(pAclRule, &aclRuleSmi);\n\n    return RT_ERR_OK;\n}\n/* Function Name:\n *      rtl8367c_setAsicAclNot\n * Description:\n *      Set rule comparison result inversion / no inversion\n * Input:\n *      index   - ACL rule index (0-95) of 96 ACL rules\n *      not     - 1: inverse, 0: don't inverse\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - Success\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_OUT_OF_RANGE     - Invalid ACL rule index (0-95)\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicAclNot(rtk_uint32 index, rtk_uint32 not)\n{\n    if(index > RTL8367C_ACLRULEMAX)\n        return RT_ERR_OUT_OF_RANGE;\n\n    if(index < 64)\n        return rtl8367c_setAsicRegBit(RTL8367C_ACL_ACTION_CTRL_REG(index), RTL8367C_ACL_OP_NOT_OFFSET(index), not);\n    else\n        return rtl8367c_setAsicRegBit(RTL8367C_ACL_ACTION_CTRL2_REG(index), RTL8367C_ACL_OP_NOT_OFFSET(index), not);\n\n}\n/* Function Name:\n *      rtl8367c_getAsicAcl\n * Description:\n *      Get rule comparison result inversion / no inversion\n * Input:\n *      index   - ACL rule index (0-95) of 95 ACL rules\n *      pNot    - 1: inverse, 0: don't inverse\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - Success\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_OUT_OF_RANGE     - Invalid ACL rule index (0-95)\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicAclNot(rtk_uint32 index, rtk_uint32* pNot)\n{\n    if(index > RTL8367C_ACLRULEMAX)\n        return RT_ERR_OUT_OF_RANGE;\n\n    if(index < 64)\n        return rtl8367c_getAsicRegBit(RTL8367C_ACL_ACTION_CTRL_REG(index), RTL8367C_ACL_OP_NOT_OFFSET(index), pNot);\n    else\n        return rtl8367c_getAsicRegBit(RTL8367C_ACL_ACTION_CTRL2_REG(index), RTL8367C_ACL_OP_NOT_OFFSET(index), pNot);\n\n}\n/* Function Name:\n *      rtl8367c_setAsicAclTemplate\n * Description:\n *      Set fields of a ACL Template\n * Input:\n *      index   - ACL template index(0~4)\n *      pAclType - ACL type stucture for setting\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - Success\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_OUT_OF_RANGE     - Invalid ACL template index(0~4)\n * Note:\n *      The API can set type field of the 5 ACL rule templates.\n *      Each type has 8 fields. One field means what data in one field of a ACL rule means\n *      8 fields of ACL rule 0~95 is descripted by one type in ACL group\n */\nret_t rtl8367c_setAsicAclTemplate(rtk_uint32 index, rtl8367c_acltemplate_t* pAclType)\n{\n    ret_t retVal;\n    rtk_uint32 i;\n    rtk_uint32 regAddr, regData;\n\n    if(index >= RTL8367C_ACLTEMPLATENO)\n        return RT_ERR_OUT_OF_RANGE;\n\n    regAddr = RTL8367C_ACL_RULE_TEMPLATE_CTRL_REG(index);\n\n    for(i = 0; i < (RTL8367C_ACLRULEFIELDNO/2); i++)\n    {\n        regData = pAclType->field[i*2+1];\n        regData = regData << 8 | pAclType->field[i*2];\n\n        retVal = rtl8367c_setAsicReg(regAddr + i, regData);\n\n        if(retVal != RT_ERR_OK)\n            return retVal;\n    }\n\n    return retVal;\n}\n/* Function Name:\n *      rtl8367c_getAsicAclTemplate\n * Description:\n *      Get fields of a ACL Template\n * Input:\n *      index   - ACL template index(0~4)\n *      pAclType - ACL type stucture for setting\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - Success\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_OUT_OF_RANGE     - Invalid ACL template index(0~4)\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicAclTemplate(rtk_uint32 index, rtl8367c_acltemplate_t *pAclType)\n{\n    ret_t retVal;\n    rtk_uint32 i;\n    rtk_uint32 regData, regAddr;\n\n    if(index >= RTL8367C_ACLTEMPLATENO)\n        return RT_ERR_OUT_OF_RANGE;\n\n    regAddr = RTL8367C_ACL_RULE_TEMPLATE_CTRL_REG(index);\n\n    for(i = 0; i < (RTL8367C_ACLRULEFIELDNO/2); i++)\n    {\n        retVal = rtl8367c_getAsicReg(regAddr + i,&regData);\n        if(retVal != RT_ERR_OK)\n            return retVal;\n\n        pAclType->field[i*2] = regData & 0xFF;\n        pAclType->field[i*2 + 1] = (regData >> 8) & 0xFF;\n    }\n\n    return RT_ERR_OK;\n}\n/* Function Name:\n *      rtl8367c_setAsicAclAct\n * Description:\n *      Set ACL rule matched Action\n * Input:\n *      index   - ACL rule index (0-95) of 96 ACL rules\n *      pAclAct     - ACL action stucture for setting\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - Success\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_OUT_OF_RANGE     - Invalid ACL rule index (0-95)\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicAclAct(rtk_uint32 index, rtl8367c_acl_act_t* pAclAct)\n{\n    rtk_uint16 aclActSmi[RTL8367C_ACL_ACT_TABLE_LEN];\n    ret_t retVal;\n    rtk_uint32 regAddr, regData;\n    rtk_uint16* tableAddr;\n    rtk_uint32 i;\n\n    if(index > RTL8367C_ACLRULEMAX)\n        return RT_ERR_OUT_OF_RANGE;\n\n    memset(aclActSmi, 0x00, sizeof(rtk_uint16) * RTL8367C_ACL_ACT_TABLE_LEN);\n     _rtl8367c_aclActStUser2Smi(pAclAct, aclActSmi);\n\n    /* Write ACS_ADR register for data bits */\n    regAddr = RTL8367C_TABLE_ACCESS_ADDR_REG;\n    regData = index;\n    retVal = rtl8367c_setAsicReg(regAddr, regData);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    /* Write Data Bits to ACS_DATA registers */\n     tableAddr = aclActSmi;\n     regAddr = RTL8367C_TABLE_ACCESS_WRDATA_BASE;\n\n    for(i = 0; i < RTL8367C_ACLACTTBLEN; i++)\n    {\n        regData = *tableAddr;\n        retVal = rtl8367c_setAsicReg(regAddr, regData);\n        if(retVal != RT_ERR_OK)\n            return retVal;\n\n        regAddr++;\n        tableAddr++;\n    }\n\n    /* Write ACS_CMD register for care bits*/\n    regAddr = RTL8367C_TABLE_ACCESS_CTRL_REG;\n    regData = RTL8367C_TABLE_ACCESS_REG_DATA(TB_OP_WRITE, TB_TARGET_ACLACT);\n    retVal = rtl8367c_setAsicRegBits(regAddr, RTL8367C_TABLE_TYPE_MASK | RTL8367C_COMMAND_TYPE_MASK, regData);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n#ifdef CONFIG_RTL8367C_ASICDRV_TEST\n    memcpy(&Rtl8370sVirtualAclActTable[index][0], aclActSmi, sizeof(rtk_uint16) * RTL8367C_ACL_ACT_TABLE_LEN);\n#endif\n\n    return RT_ERR_OK;\n}\n/* Function Name:\n *      rtl8367c_getAsicAclAct\n * Description:\n *      Get ACL rule matched Action\n * Input:\n *      index   - ACL rule index (0-95) of 96 ACL rules\n *      pAclAct     - ACL action stucture for setting\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - Success\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_OUT_OF_RANGE     - Invalid ACL rule index (0-95)\n  * Note:\n *      None\n */\nret_t rtl8367c_getAsicAclAct(rtk_uint32 index, rtl8367c_acl_act_t *pAclAct)\n{\n    rtk_uint16 aclActSmi[RTL8367C_ACL_ACT_TABLE_LEN];\n    ret_t retVal;\n    rtk_uint32 regAddr, regData;\n    rtk_uint16 *tableAddr;\n    rtk_uint32 i;\n\n    if(index > RTL8367C_ACLRULEMAX)\n        return RT_ERR_OUT_OF_RANGE;\n\n    memset(aclActSmi, 0x00, sizeof(rtk_uint16) * RTL8367C_ACL_ACT_TABLE_LEN);\n\n    /* Write ACS_ADR register for data bits */\n    regAddr = RTL8367C_TABLE_ACCESS_ADDR_REG;\n    regData = index;\n    retVal = rtl8367c_setAsicReg(regAddr, regData);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    /* Write ACS_CMD register */\n    regAddr = RTL8367C_TABLE_ACCESS_CTRL_REG;\n    regData = RTL8367C_TABLE_ACCESS_REG_DATA(TB_OP_READ, TB_TARGET_ACLACT);\n    retVal = rtl8367c_setAsicRegBits(regAddr, RTL8367C_TABLE_TYPE_MASK | RTL8367C_COMMAND_TYPE_MASK, regData);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    /* Read Data Bits */\n    regAddr = RTL8367C_TABLE_ACCESS_RDDATA_BASE;\n    tableAddr = aclActSmi;\n    for(i = 0; i < RTL8367C_ACLACTTBLEN; i++)\n    {\n        retVal = rtl8367c_getAsicReg(regAddr, &regData);\n        if(retVal != RT_ERR_OK)\n            return retVal;\n\n        *tableAddr = regData;\n\n        regAddr ++;\n        tableAddr ++;\n    }\n\n#ifdef CONFIG_RTL8367C_ASICDRV_TEST\n    memcpy(aclActSmi, &Rtl8370sVirtualAclActTable[index][0], sizeof(rtk_uint16) * RTL8367C_ACL_ACT_TABLE_LEN);\n#endif\n\n     _rtl8367c_aclActStSmi2User(pAclAct, aclActSmi);\n\n    return RT_ERR_OK;\n}\n/* Function Name:\n *      rtl8367c_setAsicAclActCtrl\n * Description:\n *      Set ACL rule matched Action Control Bits\n * Input:\n *      index       - ACL rule index (0-95) of 96 ACL rules\n *      aclActCtrl  - 6 ACL Control Bits\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - Success\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_OUT_OF_RANGE     - Invalid ACL rule index (0-95)\n * Note:\n *      ACL Action Control Bits Indicate which actions will be take when a rule matches\n */\nret_t rtl8367c_setAsicAclActCtrl(rtk_uint32 index, rtk_uint32 aclActCtrl)\n{\n    ret_t retVal;\n\n    if(index > RTL8367C_ACLRULEMAX)\n        return RT_ERR_OUT_OF_RANGE;\n\n    if(index >= 64)\n        retVal = rtl8367c_setAsicRegBits(RTL8367C_ACL_ACTION_CTRL2_REG(index), RTL8367C_ACL_OP_ACTION_MASK(index), aclActCtrl);\n    else\n        retVal = rtl8367c_setAsicRegBits(RTL8367C_ACL_ACTION_CTRL_REG(index), RTL8367C_ACL_OP_ACTION_MASK(index), aclActCtrl);\n\n    return retVal;\n}\n/* Function Name:\n *      rtl8367c_getAsicAclActCtrl\n * Description:\n *      Get ACL rule matched Action Control Bits\n * Input:\n *      index       - ACL rule index (0-95) of 96 ACL rules\n *      pAclActCtrl     - 6 ACL Control Bits\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - Success\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_OUT_OF_RANGE     - Invalid ACL rule index (0-95)\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicAclActCtrl(rtk_uint32 index, rtk_uint32 *pAclActCtrl)\n{\n    ret_t retVal;\n    rtk_uint32 regData;\n\n    if(index > RTL8367C_ACLRULEMAX)\n        return RT_ERR_OUT_OF_RANGE;\n\n    if(index >= 64)\n        retVal = rtl8367c_getAsicRegBits(RTL8367C_ACL_ACTION_CTRL2_REG(index), RTL8367C_ACL_OP_ACTION_MASK(index), &regData);\n    else\n        retVal = rtl8367c_getAsicRegBits(RTL8367C_ACL_ACTION_CTRL_REG(index), RTL8367C_ACL_OP_ACTION_MASK(index), &regData);\n\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    *pAclActCtrl = regData;\n\n    return RT_ERR_OK;\n}\n/* Function Name:\n *      rtl8367c_setAsicAclPortRange\n * Description:\n *      Set ACL TCP/UDP range check\n * Input:\n *      index       - TCP/UDP port range check table index\n *      type        - Range check type\n *      upperPort   - TCP/UDP port range upper bound\n *      lowerPort   - TCP/UDP port range lower bound\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - Success\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_OUT_OF_RANGE     - Invalid TCP/UDP port range check table index\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicAclPortRange(rtk_uint32 index, rtk_uint32 type, rtk_uint32 upperPort, rtk_uint32 lowerPort)\n{\n    ret_t retVal;\n\n    if(index > RTL8367C_ACLRANGEMAX)\n        return RT_ERR_OUT_OF_RANGE;\n\n    retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY0_CTRL2 + index*3, RTL8367C_ACL_SDPORT_RANGE_ENTRY0_CTRL2_MASK, type);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    retVal = rtl8367c_setAsicReg(RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY0_CTRL1 + index*3, upperPort);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    retVal = rtl8367c_setAsicReg(RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY0_CTRL0 + index*3, lowerPort);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n/* Function Name:\n *      rtl8367c_getAsicAclPortRange\n * Description:\n *      Get ACL TCP/UDP range check\n * Input:\n *      index       - TCP/UDP port range check table index\n *      pType       - Range check type\n *      pUpperPort  - TCP/UDP port range upper bound\n *      pLowerPort  - TCP/UDP port range lower bound\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - Success\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_OUT_OF_RANGE     - Invalid TCP/UDP port range check table index\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicAclPortRange(rtk_uint32 index, rtk_uint32* pType, rtk_uint32* pUpperPort, rtk_uint32* pLowerPort)\n{\n    ret_t retVal;\n\n    if(index > RTL8367C_ACLRANGEMAX)\n        return RT_ERR_OUT_OF_RANGE;\n\n    retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY0_CTRL2 + index*3, RTL8367C_ACL_SDPORT_RANGE_ENTRY0_CTRL2_MASK, pType);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    retVal = rtl8367c_getAsicReg(RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY0_CTRL1 + index*3, pUpperPort);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    retVal = rtl8367c_getAsicReg(RTL8367C_REG_ACL_SDPORT_RANGE_ENTRY0_CTRL0 + index*3, pLowerPort);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n/* Function Name:\n *      rtl8367c_setAsicAclVidRange\n * Description:\n *      Set ACL VID range check\n * Input:\n *      index       - ACL VID range check index(0~15)\n *      type        - Range check type\n *      upperVid    - VID range upper bound\n *      lowerVid    - VID range lower bound\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - Success\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_OUT_OF_RANGE     - Invalid ACL  VID range check index(0~15)\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicAclVidRange(rtk_uint32 index, rtk_uint32 type, rtk_uint32 upperVid, rtk_uint32 lowerVid)\n{\n    ret_t retVal;\n    rtk_uint32 regData;\n\n    if(index > RTL8367C_ACLRANGEMAX)\n        return RT_ERR_OUT_OF_RANGE;\n\n    regData = ((type << RTL8367C_ACL_VID_RANGE_ENTRY0_CTRL1_CHECK0_TYPE_OFFSET) & RTL8367C_ACL_VID_RANGE_ENTRY0_CTRL1_CHECK0_TYPE_MASK) |\n                (upperVid & RTL8367C_ACL_VID_RANGE_ENTRY0_CTRL1_CHECK0_HIGH_MASK);\n\n    retVal = rtl8367c_setAsicReg(RTL8367C_REG_ACL_VID_RANGE_ENTRY0_CTRL1 + index*2, regData);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    retVal = rtl8367c_setAsicReg(RTL8367C_REG_ACL_VID_RANGE_ENTRY0_CTRL0 + index*2, lowerVid);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n/* Function Name:\n *      rtl8367c_getAsicAclVidRange\n * Description:\n *      Get ACL VID range check\n * Input:\n *      index       - ACL VID range check index(0~15)\n *      pType       - Range check type\n *      pUpperVid   - VID range upper bound\n *      pLowerVid   - VID range lower bound\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - Success\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_OUT_OF_RANGE     - Invalid ACL VID range check index(0~15)\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicAclVidRange(rtk_uint32 index, rtk_uint32* pType, rtk_uint32* pUpperVid, rtk_uint32* pLowerVid)\n{\n    ret_t retVal;\n    rtk_uint32 regData;\n\n    if(index > RTL8367C_ACLRANGEMAX)\n        return RT_ERR_OUT_OF_RANGE;\n\n    retVal = rtl8367c_getAsicReg(RTL8367C_REG_ACL_VID_RANGE_ENTRY0_CTRL1 + index*2, &regData);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    *pType = (regData & RTL8367C_ACL_VID_RANGE_ENTRY0_CTRL1_CHECK0_TYPE_MASK) >> RTL8367C_ACL_VID_RANGE_ENTRY0_CTRL1_CHECK0_TYPE_OFFSET;\n    *pUpperVid = regData & RTL8367C_ACL_VID_RANGE_ENTRY0_CTRL1_CHECK0_HIGH_MASK;\n\n    retVal = rtl8367c_getAsicReg(RTL8367C_REG_ACL_VID_RANGE_ENTRY0_CTRL0 + index*2, pLowerVid);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n/* Function Name:\n *      rtl8367c_setAsicAclIpRange\n * Description:\n *      Set ACL IP range check\n * Input:\n *      index       - ACL IP range check index(0~15)\n *      type        - Range check type\n *      upperIp     - IP range upper bound\n *      lowerIp     - IP range lower bound\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - Success\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_OUT_OF_RANGE     - Invalid ACL IP range check index(0~15)\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicAclIpRange(rtk_uint32 index, rtk_uint32 type, ipaddr_t upperIp, ipaddr_t lowerIp)\n{\n    ret_t retVal;\n    rtk_uint32 regData;\n    ipaddr_t ipData;\n\n    if(index > RTL8367C_ACLRANGEMAX)\n        return RT_ERR_OUT_OF_RANGE;\n\n    retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_ACL_IP_RANGE_ENTRY0_CTRL4 + index*5, RTL8367C_ACL_IP_RANGE_ENTRY0_CTRL4_MASK, type);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    ipData = upperIp;\n\n    regData = ipData & 0xFFFF;\n    retVal = rtl8367c_setAsicReg(RTL8367C_REG_ACL_IP_RANGE_ENTRY0_CTRL2 + index*5, regData);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    regData = (ipData>>16) & 0xFFFF;\n    retVal = rtl8367c_setAsicReg(RTL8367C_REG_ACL_IP_RANGE_ENTRY0_CTRL3 + index*5, regData);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    ipData = lowerIp;\n\n    regData = ipData & 0xFFFF;\n    retVal = rtl8367c_setAsicReg(RTL8367C_REG_ACL_IP_RANGE_ENTRY0_CTRL0 + index*5, regData);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    regData = (ipData>>16) & 0xFFFF;\n    retVal = rtl8367c_setAsicReg(RTL8367C_REG_ACL_IP_RANGE_ENTRY0_CTRL1 + index*5, regData);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n/* Function Name:\n *      rtl8367c_getAsicAclIpRange\n * Description:\n *      Get ACL IP range check\n * Input:\n *      index       - ACL IP range check index(0~15)\n *      pType       - Range check type\n *      pUpperIp    - IP range upper bound\n *      pLowerIp    - IP range lower bound\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - Success\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_OUT_OF_RANGE     - Invalid ACL IP range check index(0~15)\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicAclIpRange(rtk_uint32 index, rtk_uint32* pType, ipaddr_t* pUpperIp, ipaddr_t* pLowerIp)\n{\n    ret_t retVal;\n    rtk_uint32 regData;\n    ipaddr_t ipData;\n\n    if(index > RTL8367C_ACLRANGEMAX)\n        return RT_ERR_OUT_OF_RANGE;\n\n    retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_ACL_IP_RANGE_ENTRY0_CTRL4 + index*5, RTL8367C_ACL_IP_RANGE_ENTRY0_CTRL4_MASK, pType);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    retVal = rtl8367c_getAsicReg(RTL8367C_REG_ACL_IP_RANGE_ENTRY0_CTRL2 + index*5, &regData);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n    ipData = regData;\n\n\n    retVal = rtl8367c_getAsicReg(RTL8367C_REG_ACL_IP_RANGE_ENTRY0_CTRL3 + index*5, &regData);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    ipData = (regData <<16) | ipData;\n    *pUpperIp = ipData;\n\n\n    retVal = rtl8367c_getAsicReg(RTL8367C_REG_ACL_IP_RANGE_ENTRY0_CTRL0 + index*5, &regData);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n    ipData = regData;\n\n\n    retVal = rtl8367c_getAsicReg(RTL8367C_REG_ACL_IP_RANGE_ENTRY0_CTRL1 + index*5, &regData);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    ipData = (regData << 16) | ipData;\n    *pLowerIp = ipData;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtl8367c_setAsicAclGpioPolarity\n * Description:\n *      Set ACL Goip control palarity\n * Input:\n *      polarity - 1: High, 0: Low\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n * Note:\n *      none\n */\nret_t rtl8367c_setAsicAclGpioPolarity(rtk_uint32 polarity)\n{\n    return rtl8367c_setAsicRegBit(RTL8367C_REG_ACL_GPIO_POLARITY, RTL8367C_ACL_GPIO_POLARITY_OFFSET, polarity);\n}\n/* Function Name:\n *      rtl8367c_getAsicAclGpioPolarity\n * Description:\n *      Get ACL Goip control palarity\n * Input:\n *      pPolarity - 1: High, 0: Low\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n * Note:\n *      none\n */\nret_t rtl8367c_getAsicAclGpioPolarity(rtk_uint32* pPolarity)\n{\n    return rtl8367c_getAsicRegBit(RTL8367C_REG_ACL_GPIO_POLARITY, RTL8367C_ACL_GPIO_POLARITY_OFFSET, pPolarity);\n}\n\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_cputag.c",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * $Revision: 76306 $\n * $Date: 2017-03-08 15:13:58 +0800 (週三, 08 三月 2017) $\n *\n * Purpose : RTL8367C switch high-level API for RTL8367C\n * Feature : Proprietary CPU-tag related function drivers\n *\n */\n#include <rtl8367c_asicdrv_cputag.h>\n/* Function Name:\n *      rtl8367c_setAsicCputagEnable\n * Description:\n *      Set cpu tag function enable/disable\n * Input:\n *      enabled - 1: enabled, 0: disabled\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n *      RT_ERR_ENABLE   - Invalid enable/disable input\n * Note:\n *      If CPU tag function is disabled, CPU tag will not be added to frame\n *      forwarded to CPU port, and all ports cannot parse CPU tag.\n */\nret_t rtl8367c_setAsicCputagEnable(rtk_uint32 enabled)\n{\n    if(enabled > 1)\n        return RT_ERR_ENABLE;\n\n    return rtl8367c_setAsicRegBit(RTL8367C_REG_CPU_CTRL, RTL8367C_CPU_EN_OFFSET, enabled);\n}\n/* Function Name:\n *      rtl8367c_getAsicCputagEnable\n * Description:\n *      Get cpu tag function enable/disable\n * Input:\n *      pEnabled - 1: enabled, 0: disabled\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicCputagEnable(rtk_uint32 *pEnabled)\n{\n    return rtl8367c_getAsicRegBit(RTL8367C_REG_CPU_CTRL, RTL8367C_CPU_EN_OFFSET, pEnabled);\n}\n/* Function Name:\n *      rtl8367c_setAsicCputagTrapPort\n * Description:\n *      Set cpu tag trap port\n * Input:\n *      port - port number\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n *      RT_ERR_PORT_ID  - Invalid port number\n * Note:\n *     API can set destination port of trapping frame\n */\nret_t rtl8367c_setAsicCputagTrapPort(rtk_uint32 port)\n{\n    ret_t retVal;\n\n    if(port >= RTL8367C_PORTNO)\n        return RT_ERR_PORT_ID;\n\n    retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_CPU_CTRL, RTL8367C_CPU_TRAP_PORT_MASK, port & 7);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_CPU_CTRL, RTL8367C_CPU_TRAP_PORT_EXT_MASK, (port>>3) & 1);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n/* Function Name:\n *      rtl8367c_getAsicCputagTrapPort\n * Description:\n *      Get cpu tag trap port\n * Input:\n *      pPort - port number\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n * Note:\n *     None\n */\nret_t rtl8367c_getAsicCputagTrapPort(rtk_uint32 *pPort)\n{\n    ret_t retVal;\n    rtk_uint32 tmpPort;\n\n    retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_CPU_CTRL, RTL8367C_CPU_TRAP_PORT_MASK, &tmpPort);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n    *pPort = tmpPort;\n\n    retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_CPU_CTRL, RTL8367C_CPU_TRAP_PORT_EXT_MASK, &tmpPort);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n    *pPort |= (tmpPort & 1) << 3;\n\n    return RT_ERR_OK;\n}\n/* Function Name:\n *      rtl8367c_setAsicCputagPortmask\n * Description:\n *      Set ports that can parse CPU tag\n * Input:\n *      portmask - port mask\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_MASK    - Invalid portmask\n * Note:\n *     None\n */\nret_t rtl8367c_setAsicCputagPortmask(rtk_uint32 portmask)\n{\n    if(portmask > RTL8367C_PORTMASK)\n        return RT_ERR_PORT_MASK;\n\n    return rtl8367c_setAsicReg(RTL8367C_CPU_PORT_MASK_REG, portmask);\n}\n/* Function Name:\n *      rtl8367c_getAsicCputagPortmask\n * Description:\n *      Get ports that can parse CPU tag\n * Input:\n *      pPortmask - port mask\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n * Note:\n *     None\n */\nret_t rtl8367c_getAsicCputagPortmask(rtk_uint32 *pPortmask)\n{\n    return rtl8367c_getAsicReg(RTL8367C_CPU_PORT_MASK_REG, pPortmask);\n}\n/* Function Name:\n *      rtl8367c_setAsicCputagInsertMode\n * Description:\n *      Set CPU-tag insert mode\n * Input:\n *      mode - 0: insert to all packets; 1: insert to trapped packets; 2: don't insert\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_NOT_ALLOWED  - Actions not allowed by the function\n * Note:\n *     None\n */\nret_t rtl8367c_setAsicCputagInsertMode(rtk_uint32 mode)\n{\n    if(mode >= CPUTAG_INSERT_END)\n        return RT_ERR_NOT_ALLOWED;\n\n    return rtl8367c_setAsicRegBits(RTL8367C_REG_CPU_CTRL, RTL8367C_CPU_INSERTMODE_MASK, mode);\n}\n/* Function Name:\n *      rtl8367c_getAsicCputagInsertMode\n * Description:\n *      Get CPU-tag insert mode\n * Input:\n *      pMode - 0: insert to all packets; 1: insert to trapped packets; 2: don't insert\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n * Note:\n *     None\n */\nret_t rtl8367c_getAsicCputagInsertMode(rtk_uint32 *pMode)\n{\n    return rtl8367c_getAsicRegBits(RTL8367C_REG_CPU_CTRL, RTL8367C_CPU_INSERTMODE_MASK, pMode);\n}\n/* Function Name:\n *      rtl8367c_setAsicCputagPriorityRemapping\n * Description:\n *      Set queue assignment of CPU port\n * Input:\n *      srcPri - internal priority (0~7)\n *      newPri - internal priority after remapping (0~7)\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK                   - Success\n *      RT_ERR_SMI                  - SMI access error\n *      RT_ERR_QOS_INT_PRIORITY     - Invalid priority\n * Note:\n *     None\n */\nret_t rtl8367c_setAsicCputagPriorityRemapping(rtk_uint32 srcPri, rtk_uint32 newPri)\n{\n    if((srcPri > RTL8367C_PRIMAX) || (newPri > RTL8367C_PRIMAX))\n        return RT_ERR_QOS_INT_PRIORITY;\n\n    return rtl8367c_setAsicRegBits(RTL8367C_QOS_PRIPORITY_REMAPPING_IN_CPU_REG(srcPri), RTL8367C_QOS_PRIPORITY_REMAPPING_IN_CPU_MASK(srcPri), newPri);\n}\n/* Function Name:\n *      rtl8367c_getAsicCputagPriorityRemapping\n * Description:\n *      Get queue assignment of CPU port\n * Input:\n *      srcPri - internal priority (0~7)\n *      pNewPri - internal priority after remapping (0~7)\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK                   - Success\n *      RT_ERR_SMI                  - SMI access error\n *      RT_ERR_QOS_INT_PRIORITY     - Invalid priority\n * Note:\n *     None\n */\nret_t rtl8367c_getAsicCputagPriorityRemapping(rtk_uint32 srcPri, rtk_uint32 *pNewPri)\n{\n    if(srcPri > RTL8367C_PRIMAX)\n        return RT_ERR_QOS_INT_PRIORITY;\n\n    return rtl8367c_getAsicRegBits(RTL8367C_QOS_PRIPORITY_REMAPPING_IN_CPU_REG(srcPri), RTL8367C_QOS_PRIPORITY_REMAPPING_IN_CPU_MASK(srcPri), pNewPri);\n}\n/* Function Name:\n *      rtl8367c_setAsicCputagPosition\n * Description:\n *      Set cpu tag insert position\n * Input:\n *      postion - 1: After entire packet(before CRC field), 0: After MAC_SA (Default)\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK                   - Success\n *      RT_ERR_SMI                  - SMI access error\n * Note:\n *     None\n */\nret_t rtl8367c_setAsicCputagPosition(rtk_uint32 postion)\n{\n    return rtl8367c_setAsicRegBit(RTL8367C_REG_CPU_CTRL, RTL8367C_CPU_TAG_POSITION_OFFSET, postion);\n}\n/* Function Name:\n *      rtl8367c_getAsicCputagPosition\n * Description:\n *      Get cpu tag insert position\n * Input:\n *      pPostion - 1: After entire packet(before CRC field), 0: After MAC_SA (Default)\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK                   - Success\n *      RT_ERR_SMI                  - SMI access error\n * Note:\n *     None\n */\nret_t rtl8367c_getAsicCputagPosition(rtk_uint32* pPostion)\n{\n    return rtl8367c_getAsicRegBit(RTL8367C_REG_CPU_CTRL, RTL8367C_CPU_TAG_POSITION_OFFSET, pPostion);\n}\n\n/* Function Name:\n *      rtl8367c_setAsicCputagMode\n * Description:\n *      Set cpu tag mode\n * Input:\n *      mode - 1: 4bytes mode, 0: 8bytes mode\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n *      RT_ERR_INPUT    - Invalid input parameters\n * Note:\n *      If CPU tag function is disabled, CPU tag will not be added to frame\n *      forwarded to CPU port, and all ports cannot parse CPU tag.\n */\nret_t rtl8367c_setAsicCputagMode(rtk_uint32 mode)\n{\n    if(mode > 1)\n        return RT_ERR_INPUT;\n\n    return rtl8367c_setAsicRegBit(RTL8367C_REG_CPU_CTRL, RTL8367C_CPU_TAG_FORMAT_OFFSET, mode);\n}\n/* Function Name:\n *      rtl8367c_getAsicCputagMode\n * Description:\n *      Get cpu tag mode\n * Input:\n *      pMode - 1: 4bytes mode, 0: 8bytes mode\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicCputagMode(rtk_uint32 *pMode)\n{\n    return rtl8367c_getAsicRegBit(RTL8367C_REG_CPU_CTRL, RTL8367C_CPU_TAG_FORMAT_OFFSET, pMode);\n}\n/* Function Name:\n *      rtl8367c_setAsicCputagRxMinLength\n * Description:\n *      Set cpu tag mode\n * Input:\n *      mode - 1: 64bytes, 0: 72bytes\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n *      RT_ERR_INPUT    - Invalid input parameters\n * Note:\n *      If CPU tag function is disabled, CPU tag will not be added to frame\n *      forwarded to CPU port, and all ports cannot parse CPU tag.\n */\nret_t rtl8367c_setAsicCputagRxMinLength(rtk_uint32 mode)\n{\n    if(mode > 1)\n        return RT_ERR_INPUT;\n\n    return rtl8367c_setAsicRegBit(RTL8367C_REG_CPU_CTRL, RTL8367C_CPU_TAG_RXBYTECOUNT_OFFSET, mode);\n}\n/* Function Name:\n *      rtl8367c_getAsicCputagRxMinLength\n * Description:\n *      Get cpu tag mode\n * Input:\n *      pMode - 1: 64bytes, 0: 72bytes\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicCputagRxMinLength(rtk_uint32 *pMode)\n{\n    return rtl8367c_getAsicRegBit(RTL8367C_REG_CPU_CTRL, RTL8367C_CPU_TAG_RXBYTECOUNT_OFFSET, pMode);\n}\n\n\n\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_dot1x.c",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * $Revision: 76306 $\n * $Date: 2017-03-08 15:13:58 +0800 (週三, 08 三月 2017) $\n *\n * Purpose : RTL8367C switch high-level API for RTL8367C\n * Feature : 802.1X related functions\n *\n */\n#include <rtl8367c_asicdrv_dot1x.h>\n/* Function Name:\n *      rtl8367c_setAsic1xPBEnConfig\n * Description:\n *      Set 802.1x port-based port enable configuration\n * Input:\n *      port    - Physical port number (0~7)\n *      enabled - 1: enabled, 0: disabled\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n *      RT_ERR_PORT_ID  - Invalid port number\n * Note:\n *      None\n */\nret_t rtl8367c_setAsic1xPBEnConfig(rtk_uint32 port, rtk_uint32 enabled)\n{\n    if(port >= RTL8367C_PORTNO)\n        return RT_ERR_PORT_ID;\n\n    return rtl8367c_setAsicRegBit(RTL8367C_DOT1X_PORT_ENABLE_REG, port, enabled);\n}\n/* Function Name:\n *      rtl8367c_getAsic1xPBEnConfig\n * Description:\n *      Get 802.1x port-based port enable configuration\n * Input:\n *      port    - Physical port number (0~7)\n *      pEnabled - 1: enabled, 0: disabled\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n *      RT_ERR_PORT_ID  - Invalid port number\n * Note:\n *      None\n */\nret_t rtl8367c_getAsic1xPBEnConfig(rtk_uint32 port, rtk_uint32 *pEnabled)\n{\n    if(port >= RTL8367C_PORTNO)\n        return RT_ERR_PORT_ID;\n\n    return rtl8367c_getAsicRegBit(RTL8367C_DOT1X_PORT_ENABLE_REG, port, pEnabled);\n}\n/* Function Name:\n *      rtl8367c_setAsic1xPBAuthConfig\n * Description:\n *      Set 802.1x port-based authorised port configuration\n * Input:\n *      port    - Physical port number (0~7)\n *      auth    - 1: authorised, 0: non-authorised\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n *      RT_ERR_PORT_ID  - Invalid port number\n * Note:\n *      None\n */\nret_t rtl8367c_setAsic1xPBAuthConfig(rtk_uint32 port, rtk_uint32 auth)\n{\n    if(port >= RTL8367C_PORTNO)\n        return RT_ERR_PORT_ID;\n\n    return rtl8367c_setAsicRegBit(RTL8367C_DOT1X_PORT_AUTH_REG, port, auth);\n}\n/* Function Name:\n *      rtl8367c_getAsic1xPBAuthConfig\n * Description:\n *      Get 802.1x port-based authorised port configuration\n * Input:\n *      port    - Physical port number (0~7)\n *      pAuth   - 1: authorised, 0: non-authorised\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n *      RT_ERR_PORT_ID  - Invalid port number\n * Note:\n *      None\n */\nret_t rtl8367c_getAsic1xPBAuthConfig(rtk_uint32 port, rtk_uint32 *pAuth)\n{\n    if(port >= RTL8367C_PORTNO)\n        return RT_ERR_PORT_ID;\n\n    return rtl8367c_getAsicRegBit(RTL8367C_DOT1X_PORT_AUTH_REG, port, pAuth);\n}\n/* Function Name:\n *      rtl8367c_setAsic1xPBOpdirConfig\n * Description:\n *      Set 802.1x port-based operational direction\n * Input:\n *      port    - Physical port number (0~7)\n *      opdir   - Operation direction 1: IN, 0:BOTH\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n *      RT_ERR_PORT_ID  - Invalid port number\n * Note:\n *      None\n */\nret_t rtl8367c_setAsic1xPBOpdirConfig(rtk_uint32 port, rtk_uint32 opdir)\n{\n    if(port >= RTL8367C_PORTNO)\n        return RT_ERR_PORT_ID;\n\n    return rtl8367c_setAsicRegBit(RTL8367C_DOT1X_PORT_OPDIR_REG, port, opdir);\n}\n/* Function Name:\n *      rtl8367c_getAsic1xPBOpdirConfig\n * Description:\n *      Get 802.1x port-based operational direction\n * Input:\n *      port    - Physical port number (0~7)\n *      pOpdir  - Operation direction 1: IN, 0:BOTH\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n *      RT_ERR_PORT_ID  - Invalid port number\n * Note:\n *      None\n */\nret_t rtl8367c_getAsic1xPBOpdirConfig(rtk_uint32 port, rtk_uint32* pOpdir)\n{\n    if(port >= RTL8367C_PORTNO)\n        return RT_ERR_PORT_ID;\n\n    return rtl8367c_getAsicRegBit(RTL8367C_DOT1X_PORT_OPDIR_REG, port, pOpdir);\n}\n/* Function Name:\n *      rtl8367c_setAsic1xMBEnConfig\n * Description:\n *      Set 802.1x mac-based port enable configuration\n * Input:\n *      port    - Physical port number (0~7)\n *      enabled - 1: enabled, 0: disabled\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n *      RT_ERR_PORT_ID  - Invalid port number\n * Note:\n *      None\n */\nret_t rtl8367c_setAsic1xMBEnConfig(rtk_uint32 port, rtk_uint32 enabled)\n{\n    if(port >= RTL8367C_PORTNO)\n        return RT_ERR_PORT_ID;\n\n    return rtl8367c_setAsicRegBit(RTL8367C_DOT1X_MAC_ENABLE_REG, port, enabled);\n}\n/* Function Name:\n *      rtl8367c_getAsic1xMBEnConfig\n * Description:\n *      Get 802.1x mac-based port enable configuration\n * Input:\n *      port    - Physical port number (0~7)\n *      pEnabled - 1: enabled, 0: disabled\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n *      RT_ERR_PORT_ID  - Invalid port number\n * Note:\n *      None\n */\nret_t rtl8367c_getAsic1xMBEnConfig(rtk_uint32 port, rtk_uint32 *pEnabled)\n{\n    if(port >= RTL8367C_PORTNO)\n        return RT_ERR_PORT_ID;\n\n    return rtl8367c_getAsicRegBit(RTL8367C_DOT1X_MAC_ENABLE_REG, port, pEnabled);\n}\n/* Function Name:\n *      rtl8367c_setAsic1xMBOpdirConfig\n * Description:\n *      Set 802.1x mac-based operational direction\n * Input:\n *      opdir       - Operation direction 1: IN, 0:BOTH\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_setAsic1xMBOpdirConfig(rtk_uint32 opdir)\n{\n    return rtl8367c_setAsicRegBit(RTL8367C_DOT1X_CFG_REG, RTL8367C_DOT1X_MAC_OPDIR_OFFSET, opdir);\n}\n/* Function Name:\n *      rtl8367c_getAsic1xMBOpdirConfig\n * Description:\n *      Get 802.1x mac-based operational direction\n * Input:\n *      pOpdir      - Operation direction 1: IN, 0:BOTH\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsic1xMBOpdirConfig(rtk_uint32 *pOpdir)\n{\n    return rtl8367c_getAsicRegBit(RTL8367C_DOT1X_CFG_REG, RTL8367C_DOT1X_MAC_OPDIR_OFFSET, pOpdir);\n}\n/* Function Name:\n *      rtl8367c_setAsic1xProcConfig\n * Description:\n *      Set 802.1x unauth. behavior configuration\n * Input:\n *      port    - Physical port number (0~7)\n *      proc    - 802.1x unauth. behavior configuration 0:drop 1:trap to CPU 2:Guest VLAN\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number\n *      RT_ERR_DOT1X_PROC   - Unauthorized behavior error\n * Note:\n *      None\n */\nret_t rtl8367c_setAsic1xProcConfig(rtk_uint32 port, rtk_uint32 proc)\n{\n\n    if(port >= RTL8367C_PORTNO)\n        return RT_ERR_PORT_ID;\n\n    if(proc >= DOT1X_UNAUTH_END)\n        return RT_ERR_DOT1X_PROC;\n\n    if(port < 8)\n    {\n        return rtl8367c_setAsicRegBits(RTL8367C_DOT1X_UNAUTH_ACT_BASE, RTL8367C_DOT1X_UNAUTH_ACT_MASK(port),proc);\n    }\n    else\n    {\n        return rtl8367c_setAsicRegBits(RTL8367C_REG_DOT1X_UNAUTH_ACT_W1, RTL8367C_DOT1X_UNAUTH_ACT_MASK(port),proc);\n    }\n}\n/* Function Name:\n *      rtl8367c_getAsic1xProcConfig\n * Description:\n *      Get 802.1x unauth. behavior configuration\n * Input:\n *      port    - Physical port number (0~7)\n *      pProc   - 802.1x unauth. behavior configuration 0:drop 1:trap to CPU 2:Guest VLAN\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number\n * Note:\n *      None\n */\nret_t rtl8367c_getAsic1xProcConfig(rtk_uint32 port, rtk_uint32* pProc)\n{\n    if(port >= RTL8367C_PORTNO)\n        return RT_ERR_PORT_ID;\n\n    if(port < 8)\n    return rtl8367c_getAsicRegBits(RTL8367C_DOT1X_UNAUTH_ACT_BASE, RTL8367C_DOT1X_UNAUTH_ACT_MASK(port),pProc);\n    else\n        return rtl8367c_getAsicRegBits(RTL8367C_REG_DOT1X_UNAUTH_ACT_W1, RTL8367C_DOT1X_UNAUTH_ACT_MASK(port),pProc);\n}\n/* Function Name:\n *      rtl8367c_setAsic1xGuestVidx\n * Description:\n *      Set 802.1x guest vlan index\n * Input:\n *      index   - 802.1x guest vlan index (0~31)\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - Success\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_DOT1X_GVLANIDX   - Invalid cvid index\n * Note:\n *      None\n */\nret_t rtl8367c_setAsic1xGuestVidx(rtk_uint32 index)\n{\n    if(index >= RTL8367C_CVIDXNO)\n        return RT_ERR_DOT1X_GVLANIDX;\n\n    return rtl8367c_setAsicRegBits(RTL8367C_DOT1X_CFG_REG, RTL8367C_DOT1X_GVIDX_MASK, index);\n}\n/* Function Name:\n *      rtl8367c_getAsic1xGuestVidx\n * Description:\n *      Get 802.1x guest vlan index\n * Input:\n *      pIndex  - 802.1x guest vlan index (0~31)\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsic1xGuestVidx(rtk_uint32 *pIndex)\n{\n    return rtl8367c_getAsicRegBits(RTL8367C_DOT1X_CFG_REG, RTL8367C_DOT1X_GVIDX_MASK, pIndex);\n}\n/* Function Name:\n *      rtl8367c_setAsic1xGVOpdir\n * Description:\n *      Set 802.1x guest vlan talk to auth. DA\n * Input:\n *      enabled     - 0:disable 1:enable\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_setAsic1xGVOpdir(rtk_uint32 enabled)\n{\n    return rtl8367c_setAsicRegBit(RTL8367C_DOT1X_CFG_REG, RTL8367C_DOT1X_GVOPDIR_OFFSET, enabled);\n}\n/* Function Name:\n *      rtl8367c_getAsic1xGVOpdir\n * Description:\n *      Get 802.1x guest vlan talk to auth. DA\n * Input:\n *      pEnabled        - 0:disable 1:enable\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsic1xGVOpdir(rtk_uint32 *pEnabled)\n{\n    return rtl8367c_getAsicRegBit(RTL8367C_DOT1X_CFG_REG, RTL8367C_DOT1X_GVOPDIR_OFFSET, pEnabled);\n}\n/* Function Name:\n *      rtl8367c_setAsic1xTrapPriority\n * Description:\n *      Set 802.1x Trap priority\n * Input:\n *      priority    - priority (0~7)\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - Success\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_QOS_INT_PRIORITY - Invalid priority\n * Note:\n *      None\n */\nret_t rtl8367c_setAsic1xTrapPriority(rtk_uint32 priority)\n{\n    if(priority > RTL8367C_PRIMAX)\n        return RT_ERR_QOS_INT_PRIORITY;\n\n    return rtl8367c_setAsicRegBits(RTL8367C_REG_QOS_TRAP_PRIORITY0, RTL8367C_DOT1X_PRIORTY_MASK,priority);\n}\n/* Function Name:\n *      rtl8367c_getAsic1xTrapPriority\n * Description:\n *      Get 802.1x Trap priority\n * Input:\n *      pPriority   - priority (0~7)\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsic1xTrapPriority(rtk_uint32 *pPriority)\n{\n    return rtl8367c_getAsicRegBits(RTL8367C_REG_QOS_TRAP_PRIORITY0, RTL8367C_DOT1X_PRIORTY_MASK, pPriority);\n}\n\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_eav.c",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * $Revision: 76306 $\n * $Date: 2017-03-08 15:13:58 +0800 (週三, 08 三月 2017) $\n *\n * Purpose : RTL8367C switch high-level API for RTL8367C\n * Feature : Ethernet AV related functions\n *\n */\n\n#include <rtl8367c_asicdrv_eav.h>\n/* Function Name:\n *      rtl8367c_setAsicEavMacAddress\n * Description:\n *      Set PTP MAC address\n * Input:\n *      mac     - PTP mac\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK         - Success\n *      RT_ERR_SMI      - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicEavMacAddress(ether_addr_t mac)\n{\n    ret_t retVal;\n    rtk_uint32 regData;\n    rtk_uint8 *accessPtr;\n    rtk_uint32 i;\n\n    accessPtr =  (rtk_uint8*)&mac;\n\n    regData = *accessPtr;\n    accessPtr ++;\n    regData = (regData << 8) | *accessPtr;\n    accessPtr ++;\n    for(i = 0; i <=2; i++)\n    {\n        retVal = rtl8367c_setAsicReg(RTL8367C_REG_MAC_ADDR_H - i, regData);\n        if(retVal != RT_ERR_OK)\n            return retVal;\n\n        regData = *accessPtr;\n        accessPtr ++;\n        regData = (regData << 8) | *accessPtr;\n        accessPtr ++;\n    }\n\n    return retVal;\n}\n/* Function Name:\n *      rtl8367c_getAsicEavMacAddress\n * Description:\n *      Get PTP MAC address\n * Input:\n *      None\n * Output:\n *      pMac     - PTP  mac\n * Return:\n *      RT_ERR_OK         - Success\n *      RT_ERR_SMI      - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicEavMacAddress(ether_addr_t *pMac)\n{\n    ret_t retVal;\n    rtk_uint32 regData;\n    rtk_uint8 *accessPtr;\n    rtk_uint32 i;\n\n    accessPtr = (rtk_uint8*)pMac;\n\n    for(i = 0; i <= 2; i++)\n    {\n        retVal = rtl8367c_getAsicReg(RTL8367C_REG_MAC_ADDR_H - i, &regData);\n        if(retVal != RT_ERR_OK)\n            return retVal;\n\n        *accessPtr = (regData & 0xFF00) >> 8;\n        accessPtr ++;\n        *accessPtr = regData & 0xFF;\n        accessPtr ++;\n    }\n\n    return retVal;\n}\n\n/* Function Name:\n *      rtl8367c_setAsicEavTpid\n * Description:\n *      Set PTP parser tag TPID.\n * Input:\n *       outerTag - outter tag TPID\n *       innerTag  - inner tag TPID\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *     None\n */\nret_t rtl8367c_setAsicEavTpid(rtk_uint32 outerTag, rtk_uint32 innerTag)\n{\n    ret_t retVal;\n\n    if((retVal = rtl8367c_setAsicReg(RTL8367C_REG_OTAG_TPID, outerTag)) != RT_ERR_OK)\n        return retVal;\n    if((retVal = rtl8367c_setAsicReg(RTL8367C_REG_ITAG_TPID, innerTag)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n/* Function Name:\n *      rtl8367c_getAsicEavTpid\n * Description:\n *      Get PTP parser tag TPID.\n * Input:\n *      None\n * Output:\n *       pOuterTag - outter tag TPID\n *       pInnerTag  - inner tag TPID\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicEavTpid(rtk_uint32* pOuterTag, rtk_uint32* pInnerTag)\n{\n    ret_t retVal;\n\n    if((retVal = rtl8367c_getAsicReg(RTL8367C_REG_OTAG_TPID, pOuterTag)) != RT_ERR_OK)\n        return retVal;\n    if((retVal = rtl8367c_getAsicReg(RTL8367C_REG_ITAG_TPID, pInnerTag)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtl8367c_setAsicEavSysTime\n * Description:\n *      Set PTP system time\n * Input:\n *      second - seconds\n *      nanoSecond - nano seconds\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK     - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      The time granuality is 8 nano seconds.\n */\nret_t rtl8367c_setAsicEavSysTime(rtk_uint32 second, rtk_uint32 nanoSecond)\n{\n    ret_t retVal;\n    rtk_uint32 sec_h, sec_l, nsec8_h, nsec8_l;\n    rtk_uint32 nano_second_8;\n    rtk_uint32 regData, busyFlag, count;\n\n    if(nanoSecond > RTL8367C_EAV_NANOSECONDMAX)\n        return RT_ERR_INPUT;\n\n    regData = 0;\n    sec_h = second >>16;\n    sec_l = second & 0xFFFF;\n    nano_second_8 = nanoSecond >> 3;\n    nsec8_h = (nano_second_8 >>16) & RTL8367C_PTP_TIME_NSEC_H_NSEC_MASK;\n    nsec8_l = nano_second_8 &0xFFFF;\n\n    if((retVal = rtl8367c_setAsicReg(RTL8367C_REG_PTP_TIME_SEC_H_SEC, sec_h)) != RT_ERR_OK)\n        return retVal;\n    if((retVal = rtl8367c_setAsicReg(RTL8367C_REG_PTP_TIME_SEC_L_SEC, sec_l)) != RT_ERR_OK)\n        return retVal;\n    if((retVal = rtl8367c_setAsicReg(RTL8367C_REG_PTP_TIME_NSEC_L_NSEC, nsec8_l)) != RT_ERR_OK)\n        return retVal;\n\n    regData = nsec8_h | (PTP_TIME_WRITE<<RTL8367C_PTP_TIME_NSEC_H_CMD_OFFSET) | RTL8367C_PTP_TIME_NSEC_H_EXEC_MASK;\n\n    if((retVal = rtl8367c_setAsicReg(RTL8367C_REG_PTP_TIME_NSEC_H_NSEC, regData)) != RT_ERR_OK)\n        return retVal;\n\n    count = 0;\n    do {\n        if((retVal = rtl8367c_getAsicRegBit(RTL8367C_REG_PTP_TIME_NSEC_H_NSEC, RTL8367C_PTP_TIME_NSEC_H_EXEC_OFFSET, &busyFlag)) != RT_ERR_OK)\n            return retVal;\n        count++;\n    } while ((busyFlag != 0)&&(count<5));\n\n    if (busyFlag != 0)\n        return RT_ERR_BUSYWAIT_TIMEOUT;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtl8367c_getAsicEavSysTime\n * Description:\n *      Get PTP system time\n * Input:\n *      None\n * Output:\n *      second - seconds\n *      nanoSecond - nano seconds\n * Return:\n *      RT_ERR_OK     - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      The time granuality is 8 nano seconds.\n */\nret_t rtl8367c_getAsicEavSysTime(rtk_uint32* pSecond, rtk_uint32* pNanoSecond)\n{\n    ret_t retVal;\n    rtk_uint32 sec_h, sec_l, nsec8_h, nsec8_l;\n    rtk_uint32 nano_second_8;\n    rtk_uint32 regData, busyFlag, count;\n\n    regData = 0;\n    regData = (PTP_TIME_READ<<RTL8367C_PTP_TIME_NSEC_H_CMD_OFFSET) | RTL8367C_PTP_TIME_NSEC_H_EXEC_MASK;\n\n    if((retVal = rtl8367c_setAsicReg(RTL8367C_REG_PTP_TIME_NSEC_H_NSEC, regData)) != RT_ERR_OK)\n        return retVal;\n\n    count = 0;\n    do {\n        if((retVal = rtl8367c_getAsicRegBit(RTL8367C_REG_PTP_TIME_NSEC_H_NSEC, RTL8367C_PTP_TIME_NSEC_H_EXEC_OFFSET, &busyFlag)) != RT_ERR_OK)\n            return retVal;\n        count++;\n    } while ((busyFlag != 0)&&(count<5));\n\n    if (busyFlag != 0)\n        return RT_ERR_BUSYWAIT_TIMEOUT;\n\n    if((retVal = rtl8367c_getAsicReg(RTL8367C_REG_PTP_TIME_SEC_H_SEC_RD, &sec_h)) != RT_ERR_OK)\n        return retVal;\n    if((retVal = rtl8367c_getAsicReg(RTL8367C_REG_PTP_TIME_SEC_L_SEC_RD, &sec_l)) != RT_ERR_OK)\n        return retVal;\n    if((retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_PTP_TIME_NSEC_H_NSEC_RD, RTL8367C_PTP_TIME_NSEC_H_NSEC_RD_MASK,&nsec8_h)) != RT_ERR_OK)\n        return retVal;\n    if((retVal = rtl8367c_getAsicReg(RTL8367C_REG_PTP_TIME_NSEC_L_NSEC_RD, &nsec8_l)) != RT_ERR_OK)\n        return retVal;\n\n    *pSecond = (sec_h<<16) | sec_l;\n    nano_second_8 = (nsec8_h<<16) | nsec8_l;\n    *pNanoSecond = nano_second_8<<3;\n\n    return RT_ERR_OK;\n}\n\n\n/* Function Name:\n *      rtl8367c_setAsicEavSysTimeAdjust\n * Description:\n *      Set PTP system time adjust\n * Input:\n *      type - incresae or decrease\n *      second - seconds\n *      nanoSecond - nano seconds\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK     - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      Ethernet AV second offset of timer for tuning\n */\nret_t rtl8367c_setAsicEavSysTimeAdjust(rtk_uint32 type, rtk_uint32 second, rtk_uint32 nanoSecond)\n{\n    ret_t retVal;\n    rtk_uint32 sec_h, sec_l, nsec8_h, nsec8_l;\n    rtk_uint32 nano_second_8;\n    rtk_uint32 regData, busyFlag, count;\n\n    if (type >= PTP_TIME_ADJ_END)\n        return RT_ERR_INPUT;\n    if(nanoSecond > RTL8367C_EAV_NANOSECONDMAX)\n        return RT_ERR_INPUT;\n\n    regData = 0;\n    sec_h = second >>16;\n    sec_l = second & 0xFFFF;\n    nano_second_8 = nanoSecond >> 3;\n    nsec8_h = (nano_second_8 >>16) & RTL8367C_PTP_TIME_NSEC_H_NSEC_MASK;\n    nsec8_l = nano_second_8 &0xFFFF;\n\n    if((retVal = rtl8367c_setAsicReg(RTL8367C_REG_PTP_TIME_SEC_H_SEC, sec_h)) != RT_ERR_OK)\n        return retVal;\n    if((retVal = rtl8367c_setAsicReg(RTL8367C_REG_PTP_TIME_SEC_L_SEC, sec_l)) != RT_ERR_OK)\n        return retVal;\n    if((retVal = rtl8367c_setAsicReg(RTL8367C_REG_PTP_TIME_NSEC_L_NSEC, nsec8_l)) != RT_ERR_OK)\n        return retVal;\n\n    if (PTP_TIME_ADJ_INC == type)\n        regData = nsec8_h | (PTP_TIME_INC<<RTL8367C_PTP_TIME_NSEC_H_CMD_OFFSET) | RTL8367C_PTP_TIME_NSEC_H_EXEC_MASK;\n    else\n        regData = nsec8_h | (PTP_TIME_DEC<<RTL8367C_PTP_TIME_NSEC_H_CMD_OFFSET) | RTL8367C_PTP_TIME_NSEC_H_EXEC_MASK;\n\n    if((retVal = rtl8367c_setAsicReg(RTL8367C_REG_PTP_TIME_NSEC_H_NSEC, regData)) != RT_ERR_OK)\n        return retVal;\n\n    count = 0;\n    do {\n        if((retVal = rtl8367c_getAsicRegBit(RTL8367C_REG_PTP_TIME_NSEC_H_NSEC, RTL8367C_PTP_TIME_NSEC_H_EXEC_OFFSET, &busyFlag)) != RT_ERR_OK)\n            return retVal;\n        count++;\n    } while ((busyFlag != 0)&&(count<5));\n\n    if (busyFlag != 0)\n        return RT_ERR_BUSYWAIT_TIMEOUT;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtl8367c_setAsicEavSysTimeCtrl\n * Description:\n *      Set PTP system time control\n * Input:\n *      command - start or stop\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK     - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicEavSysTimeCtrl(rtk_uint32 control)\n{\n    ret_t  retVal;\n    rtk_uint32 regData;\n\n    if (control>=PTP_TIME_CTRL_END)\n         return RT_ERR_INPUT;\n\n    regData = 0;\n    if (PTP_TIME_CTRL_START == control)\n            regData = RTL8367C_CFG_TIMER_EN_FRC_MASK | RTL8367C_CFG_TIMER_1588_EN_MASK;\n    else\n        regData = 0;\n\n    if((retVal = rtl8367c_setAsicReg(RTL8367C_REG_PTP_TIME_CFG, regData)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtl8367c_getAsicEavSysTimeCtrl\n * Description:\n *      Get PTP system time control\n * Input:\n *      None\n * Output:\n *      pControl - start or stop\n * Return:\n *      RT_ERR_OK     - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicEavSysTimeCtrl(rtk_uint32* pControl)\n{\n    ret_t  retVal;\n    rtk_uint32 regData;\n    rtk_uint32 mask;\n\n    mask = RTL8367C_CFG_TIMER_EN_FRC_MASK | RTL8367C_CFG_TIMER_1588_EN_MASK;\n\n    if((retVal = rtl8367c_getAsicReg(RTL8367C_REG_PTP_TIME_CFG, &regData)) != RT_ERR_OK)\n        return retVal;\n\n    if( (regData & mask) == mask)\n        *pControl = PTP_TIME_CTRL_START;\n    else if( (regData & mask) == 0)\n        *pControl = PTP_TIME_CTRL_STOP;\n    else\n        return RT_ERR_NOT_ALLOWED;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtl8367c_setAsicEavInterruptMask\n * Description:\n *      Set PTP interrupt enable mask\n * Input:\n *      imr     - Interrupt mask\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      [0]:TX_SYNC,\n *      [1]:TX_DELAY,\n *      [2]:TX_PDELAY_REQ,\n *      [3]:TX_PDELAY_RESP,\n *      [4]:RX_SYNC,\n *      [5]:RX_DELAY,\n *      [6]:RX_PDELAY_REQ,\n *      [7]:RX_PDELAY_RESP,\n */\nret_t rtl8367c_setAsicEavInterruptMask(rtk_uint32 imr)\n{\n    if ((imr&(RTL8367C_PTP_INTR_MASK<<8))>0)\n         return RT_ERR_INPUT;\n\n    return rtl8367c_setAsicRegBits(RTL8367C_REG_PTP_TIME_CFG2, RTL8367C_PTP_INTR_MASK, imr);\n}\n/* Function Name:\n *      rtl8367c_getAsicEavInterruptMask\n * Description:\n *      Get PTP interrupt enable mask\n * Input:\n *      pImr    - Interrupt mask\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      [0]:TX_SYNC,\n *      [1]:TX_DELAY,\n *      [2]:TX_PDELAY_REQ,\n *      [3]:TX_PDELAY_RESP,\n *      [4]:RX_SYNC,\n *      [5]:RX_DELAY,\n *      [6]:RX_PDELAY_REQ,\n *      [7]:RX_PDELAY_RESP,\n */\nret_t rtl8367c_getAsicEavInterruptMask(rtk_uint32* pImr)\n{\n    return rtl8367c_getAsicRegBits(RTL8367C_REG_PTP_TIME_CFG2, RTL8367C_PTP_INTR_MASK, pImr);\n}\n\n/* Function Name:\n *      rtl8367c_getAsicEavInterruptStatus\n * Description:\n *      Get PTP interrupt port status mask\n * Input:\n *      pIms    - Interrupt mask\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      [0]:p0 interrupt,\n *      [1]:p1 interrupt,\n *      [2]:p2 interrupt,\n *      [3]:p3 interrupt,\n *      [4]:p4 interrupt,\n */\nret_t rtl8367c_getAsicEavInterruptStatus(rtk_uint32* pIms)\n{\n    return rtl8367c_getAsicRegBits(RTL8367C_REG_PTP_INTERRUPT_CFG, RTL8367C_PTP_PORT_MASK, pIms);\n}\n\n/* Function Name:\n *      rtl8367c_setAsicInterruptMask\n * Description:\n *      Clear interrupt enable mask\n * Input:\n *      ims     - Interrupt status mask\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      This API can be used to clear ASIC interrupt status and register will be cleared by writting 1.\n *      [0]:TX_SYNC,\n *      [1]:TX_DELAY,\n *      [2]:TX_PDELAY_REQ,\n *      [3]:TX_PDELAY_RESP,\n *      [4]:RX_SYNC,\n *      [5]:RX_DELAY,\n *      [6]:RX_PDELAY_REQ,\n *      [7]:RX_PDELAY_RESP,\n */\nret_t rtl8367c_setAsicEavPortInterruptStatus(rtk_uint32 port, rtk_uint32 ims)\n{\n\n    if(port > RTL8367C_PORTNO)\n        return RT_ERR_PORT_ID;\n\n    if(port < 5)\n        return rtl8367c_setAsicRegBits(RTL8367C_EAV_PORT_CFG_REG(port), RTL8367C_PTP_INTR_MASK,ims);\n    else if(port == 5)\n        return rtl8367c_setAsicRegBits(RTL8367C_REG_P5_EAV_CFG, RTL8367C_PTP_INTR_MASK,ims);\n    else if(port == 6)\n        return rtl8367c_setAsicRegBits(RTL8367C_REG_P6_EAV_CFG, RTL8367C_PTP_INTR_MASK,ims);\n    else if(port == 7)\n        return rtl8367c_setAsicRegBits(RTL8367C_REG_P7_EAV_CFG, RTL8367C_PTP_INTR_MASK,ims);\n    else if(port == 8)\n        return rtl8367c_setAsicRegBits(RTL8367C_REG_P8_EAV_CFG, RTL8367C_PTP_INTR_MASK,ims);\n    else if(port == 9)\n        return rtl8367c_setAsicRegBits(RTL8367C_REG_P9_EAV_CFG, RTL8367C_PTP_INTR_MASK,ims);\n\n    return RT_ERR_OK;\n}\n/* Function Name:\n *      rtl8367c_getAsicInterruptStatus\n * Description:\n *      Get interrupt enable mask\n * Input:\n *      pIms    - Interrupt status mask\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      [0]:TX_SYNC,\n *      [1]:TX_DELAY,\n *      [2]:TX_PDELAY_REQ,\n *      [3]:TX_PDELAY_RESP,\n *      [4]:RX_SYNC,\n *      [5]:RX_DELAY,\n *      [6]:RX_PDELAY_REQ,\n *      [7]:RX_PDELAY_RESP,\n */\nret_t rtl8367c_getAsicEavPortInterruptStatus(rtk_uint32 port, rtk_uint32* pIms)\n{\n\n    if(port > RTL8367C_PORTNO)\n        return RT_ERR_PORT_ID;\n    if(port < 5)\n        return rtl8367c_getAsicRegBits(RTL8367C_EAV_PORT_CFG_REG(port), RTL8367C_PTP_INTR_MASK, pIms);\n    else if(port == 5)\n        return rtl8367c_getAsicRegBits(RTL8367C_REG_P5_EAV_CFG, RTL8367C_PTP_INTR_MASK, pIms);\n    else if(port == 6)\n        return rtl8367c_getAsicRegBits(RTL8367C_REG_P6_EAV_CFG, RTL8367C_PTP_INTR_MASK,pIms);\n    else if(port == 7)\n        return rtl8367c_getAsicRegBits(RTL8367C_REG_P7_EAV_CFG, RTL8367C_PTP_INTR_MASK,pIms);\n    else if(port == 8)\n        return rtl8367c_getAsicRegBits(RTL8367C_REG_P8_EAV_CFG, RTL8367C_PTP_INTR_MASK,pIms);\n    else if(port == 9)\n        return rtl8367c_getAsicRegBits(RTL8367C_REG_P9_EAV_CFG, RTL8367C_PTP_INTR_MASK,pIms);\n\n    return RT_ERR_OK;\n\n}\n\n\n/* Function Name:\n *      rtl8367c_setAsicEavPortEnable\n * Description:\n *      Set per-port EAV function enable/disable\n * Input:\n *      port         - Physical port number (0~9)\n *      enabled     - 1: enabled, 0: disabled\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK         - Success\n *      RT_ERR_SMI      - SMI access error\n *      RT_ERR_PORT_ID  - Invalid port number\n * Note:\n *      If EAV function is enabled, PTP event messgae packet will be attached PTP timestamp for trapping\n */\nret_t rtl8367c_setAsicEavPortEnable(rtk_uint32 port, rtk_uint32 enabled)\n{\n    if(port > RTL8367C_PORTNO)\n        return RT_ERR_PORT_ID;\n\n    if(port < 5)\n        return rtl8367c_setAsicRegBit(RTL8367C_EAV_PORT_CFG_REG(port), RTL8367C_EAV_CFG_PTP_PHY_EN_EN_OFFSET, enabled);\n    else if(port == 5)\n        return rtl8367c_setAsicRegBit(RTL8367C_REG_P5_EAV_CFG, RTL8367C_EAV_CFG_PTP_PHY_EN_EN_OFFSET, enabled);\n    else if(port == 6)\n        return rtl8367c_setAsicRegBit(RTL8367C_REG_P6_EAV_CFG, RTL8367C_EAV_CFG_PTP_PHY_EN_EN_OFFSET, enabled);\n    else if(port == 7)\n        return rtl8367c_setAsicRegBit(RTL8367C_REG_P7_EAV_CFG, RTL8367C_EAV_CFG_PTP_PHY_EN_EN_OFFSET, enabled);\n    else if(port == 8)\n        return rtl8367c_setAsicRegBit(RTL8367C_REG_P8_EAV_CFG, RTL8367C_EAV_CFG_PTP_PHY_EN_EN_OFFSET, enabled);\n    else if(port == 9)\n        return rtl8367c_setAsicRegBit(RTL8367C_REG_P9_EAV_CFG, RTL8367C_EAV_CFG_PTP_PHY_EN_EN_OFFSET, enabled);\n\n\n    return RT_ERR_OK;\n}\n/* Function Name:\n *      rtl8367c_getAsicEavPortEnable\n * Description:\n *      Get per-port EAV function enable/disable\n * Input:\n *      port         - Physical port number (0~9)\n *      pEnabled     - 1: enabled, 0: disabled\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK         - Success\n *      RT_ERR_SMI      - SMI access error\n *      RT_ERR_PORT_ID  - Invalid port number\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicEavPortEnable(rtk_uint32 port, rtk_uint32 *pEnabled)\n{\n    if(port > RTL8367C_PORTNO)\n        return RT_ERR_PORT_ID;\n\n\n\n    if(port < 5)\n        return rtl8367c_getAsicRegBit(RTL8367C_EAV_PORT_CFG_REG(port), RTL8367C_EAV_CFG_PTP_PHY_EN_EN_OFFSET, pEnabled);\n    else if(port == 5)\n        return rtl8367c_getAsicRegBit(RTL8367C_REG_P5_EAV_CFG, RTL8367C_EAV_CFG_PTP_PHY_EN_EN_OFFSET, pEnabled);\n    else if(port == 6)\n        return rtl8367c_getAsicRegBit(RTL8367C_REG_P6_EAV_CFG, RTL8367C_EAV_CFG_PTP_PHY_EN_EN_OFFSET, pEnabled);\n    else if(port == 7)\n        return rtl8367c_getAsicRegBit(RTL8367C_REG_P7_EAV_CFG, RTL8367C_EAV_CFG_PTP_PHY_EN_EN_OFFSET, pEnabled);\n    else if(port == 8)\n        return rtl8367c_getAsicRegBit(RTL8367C_REG_P8_EAV_CFG, RTL8367C_EAV_CFG_PTP_PHY_EN_EN_OFFSET, pEnabled);\n    else if(port == 9)\n        return rtl8367c_getAsicRegBit(RTL8367C_REG_P9_EAV_CFG, RTL8367C_EAV_CFG_PTP_PHY_EN_EN_OFFSET, pEnabled);\n\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtl8367c_getAsicEavPortTimeStamp\n * Description:\n *      Get PTP port time stamp\n * Input:\n *      port         - Physical port number (0~9)\n *      type     -  PTP packet type\n * Output:\n *      timeStamp - seconds\n * Return:\n *      RT_ERR_OK     - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      The time granuality is 8 nano seconds.\n */\nret_t rtl8367c_getAsicEavPortTimeStamp(rtk_uint32 port, rtk_uint32 type, rtl8367c_ptp_time_stamp_t* timeStamp)\n{\n    ret_t retVal;\n    rtk_uint32 sec_h, sec_l, nsec8_h, nsec8_l;\n    rtk_uint32 nano_second_8;\n\n    if(port > 9)\n        return RT_ERR_PORT_ID;\n    if(type >= PTP_PKT_TYPE_END)\n        return RT_ERR_INPUT;\n\n    if(port < 5){\n        if((retVal = rtl8367c_getAsicReg(RTL8367C_REG_SEQ_ID(port, type), &timeStamp->sequence_id))!=  RT_ERR_OK)\n            return retVal;\n        if((retVal = rtl8367c_getAsicReg(RTL8367C_REG_PORT_SEC_H(port) , &sec_h)) != RT_ERR_OK)\n           return retVal;\n        if((retVal = rtl8367c_getAsicReg(RTL8367C_REG_PORT_SEC_L(port), &sec_l)) != RT_ERR_OK)\n           return retVal;\n        if((retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_PORT_NSEC_H(port) , RTL8367C_PORT_NSEC_H_MASK,&nsec8_h)) != RT_ERR_OK)\n           return retVal;\n        if((retVal = rtl8367c_getAsicReg(RTL8367C_REG_PORT_NSEC_L(port) , &nsec8_l)) != RT_ERR_OK)\n           return retVal;\n    }else if(port == 5){\n        if((retVal = rtl8367c_getAsicReg(RTL8367C_REG_P5_TX_SYNC_SEQ_ID+type, &timeStamp->sequence_id))!=  RT_ERR_OK)\n            return retVal;\n        if((retVal = rtl8367c_getAsicReg(RTL8367C_REG_P5_PORT_SEC_31_16, &sec_h)) != RT_ERR_OK)\n           return retVal;\n        if((retVal = rtl8367c_getAsicReg(RTL8367C_REG_P5_PORT_SEC_15_0, &sec_l)) != RT_ERR_OK)\n           return retVal;\n        if((retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_P5_PORT_NSEC_26_16 , RTL8367C_PORT_NSEC_H_MASK,&nsec8_h)) != RT_ERR_OK)\n           return retVal;\n        if((retVal = rtl8367c_getAsicReg(RTL8367C_REG_P5_PORT_NSEC_15_0, &nsec8_l)) != RT_ERR_OK)\n           return retVal;\n    }else if(port == 6){\n        if((retVal = rtl8367c_getAsicReg(RTL8367C_REG_P6_TX_SYNC_SEQ_ID+type, &timeStamp->sequence_id))!=  RT_ERR_OK)\n            return retVal;\n        if((retVal = rtl8367c_getAsicReg(RTL8367C_REG_P6_PORT_SEC_31_16, &sec_h)) != RT_ERR_OK)\n           return retVal;\n        if((retVal = rtl8367c_getAsicReg(RTL8367C_REG_P6_PORT_SEC_15_0, &sec_l)) != RT_ERR_OK)\n           return retVal;\n        if((retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_P6_PORT_NSEC_26_16 , RTL8367C_PORT_NSEC_H_MASK,&nsec8_h)) != RT_ERR_OK)\n           return retVal;\n        if((retVal = rtl8367c_getAsicReg(RTL8367C_REG_P6_PORT_NSEC_15_0, &nsec8_l)) != RT_ERR_OK)\n           return retVal;\n    }else if(port == 7){\n        if((retVal = rtl8367c_getAsicReg(RTL8367C_REG_P7_TX_SYNC_SEQ_ID+type, &timeStamp->sequence_id))!=  RT_ERR_OK)\n            return retVal;\n        if((retVal = rtl8367c_getAsicReg(RTL8367C_REG_P7_PORT_SEC_31_16, &sec_h)) != RT_ERR_OK)\n           return retVal;\n        if((retVal = rtl8367c_getAsicReg(RTL8367C_REG_P7_PORT_SEC_15_0, &sec_l)) != RT_ERR_OK)\n           return retVal;\n        if((retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_P7_PORT_NSEC_26_16 , RTL8367C_PORT_NSEC_H_MASK,&nsec8_h)) != RT_ERR_OK)\n           return retVal;\n        if((retVal = rtl8367c_getAsicReg(RTL8367C_REG_P7_PORT_NSEC_15_0, &nsec8_l)) != RT_ERR_OK)\n           return retVal;\n    }else if(port == 8){\n        if((retVal = rtl8367c_getAsicReg(RTL8367C_REG_P8_TX_SYNC_SEQ_ID+type, &timeStamp->sequence_id))!=  RT_ERR_OK)\n            return retVal;\n        if((retVal = rtl8367c_getAsicReg(RTL8367C_REG_P8_PORT_SEC_31_16, &sec_h)) != RT_ERR_OK)\n           return retVal;\n        if((retVal = rtl8367c_getAsicReg(RTL8367C_REG_P8_PORT_SEC_15_0, &sec_l)) != RT_ERR_OK)\n           return retVal;\n        if((retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_P8_PORT_NSEC_26_16 , RTL8367C_PORT_NSEC_H_MASK,&nsec8_h)) != RT_ERR_OK)\n           return retVal;\n        if((retVal = rtl8367c_getAsicReg(RTL8367C_REG_P8_PORT_NSEC_15_0, &nsec8_l)) != RT_ERR_OK)\n           return retVal;\n    }else if(port == 9){\n        if((retVal = rtl8367c_getAsicReg(RTL8367C_REG_P9_TX_SYNC_SEQ_ID+type, &timeStamp->sequence_id))!=  RT_ERR_OK)\n            return retVal;\n        if((retVal = rtl8367c_getAsicReg(RTL8367C_REG_P9_PORT_SEC_31_16, &sec_h)) != RT_ERR_OK)\n           return retVal;\n        if((retVal = rtl8367c_getAsicReg(RTL8367C_REG_P9_PORT_SEC_15_0, &sec_l)) != RT_ERR_OK)\n           return retVal;\n        if((retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_P9_PORT_NSEC_26_16 , RTL8367C_PORT_NSEC_H_MASK,&nsec8_h)) != RT_ERR_OK)\n           return retVal;\n        if((retVal = rtl8367c_getAsicReg(RTL8367C_REG_P9_PORT_NSEC_15_0, &nsec8_l)) != RT_ERR_OK)\n           return retVal;\n    }\n\n    timeStamp->second = (sec_h<<16) | sec_l;\n    nano_second_8 = (nsec8_h<<16) | nsec8_l;\n    timeStamp->nano_second = nano_second_8<<3;\n\n    return RT_ERR_OK;\n}\n\n\n/* Function Name:\n *      rtl8367c_setAsicEavTrap\n * Description:\n *      Set per-port PTP packet trap to CPU\n * Input:\n *      port         - Physical port number (0~5)\n *      enabled     - 1: enabled, 0: disabled\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK         - Success\n *      RT_ERR_SMI      - SMI access error\n *      RT_ERR_PORT_ID  - Invalid port number\n * Note:\n *      If EAV trap enabled, switch will trap PTP packet to CPU\n */\nret_t rtl8367c_setAsicEavTrap(rtk_uint32 port, rtk_uint32 enabled)\n{\n    if(port > RTL8367C_PORTNO)\n        return RT_ERR_PORT_ID;\n\n    return rtl8367c_setAsicRegBit(RTL8367C_REG_PTP_PORT0_CFG1 + (port * 0x20), RTL8367C_PTP_PORT0_CFG1_OFFSET, enabled);\n}\n/* Function Name:\n *      rtl8367c_getAsicEavTimeSyncEn\n * Description:\n *      Get per-port EPTP packet trap to CPU\n * Input:\n *      port         - Physical port number (0~5)\n *      pEnabled     - 1: enabled, 0: disabled\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK         - Success\n *      RT_ERR_SMI      - SMI access error\n *      RT_ERR_PORT_ID  - Invalid port number\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicEavTrap(rtk_uint32 port, rtk_uint32 *pEnabled)\n{\n    if(port > RTL8367C_PORTNO)\n        return RT_ERR_PORT_ID;\n\n    return rtl8367c_getAsicRegBit(RTL8367C_REG_PTP_PORT0_CFG1 + (port * 0x20), RTL8367C_PTP_PORT0_CFG1_OFFSET, pEnabled);\n}\n\n/* Function Name:\n *      rtl8367c_setAsicEavEnable\n * Description:\n *      Set per-port EAV function enable/disable\n * Input:\n *      port         - Physical port number (0~5)\n *      enabled     - 1: enabled, 0: disabled\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK         - Success\n *      RT_ERR_SMI      - SMI access error\n *      RT_ERR_PORT_ID  - Invalid port number\n * Note:\n *      If EAV function is enabled, PTP event messgae packet will be attached PTP timestamp for trapping\n */\nret_t rtl8367c_setAsicEavEnable(rtk_uint32 port, rtk_uint32 enabled)\n{\n    if(port > RTL8367C_PORTNO)\n        return RT_ERR_PORT_ID;\n\n    return rtl8367c_setAsicRegBit(RTL8367C_REG_EAV_CTRL0, port, enabled);\n}\n/* Function Name:\n *      rtl8367c_getAsicEavEnable\n * Description:\n *      Get per-port EAV function enable/disable\n * Input:\n *      port         - Physical port number (0~5)\n *      pEnabled     - 1: enabled, 0: disabled\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK         - Success\n *      RT_ERR_SMI      - SMI access error\n *      RT_ERR_PORT_ID  - Invalid port number\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicEavEnable(rtk_uint32 port, rtk_uint32 *pEnabled)\n{\n    if(port > RTL8367C_PORTNO)\n        return RT_ERR_PORT_ID;\n\n    return rtl8367c_getAsicRegBit(RTL8367C_REG_EAV_CTRL0, port, pEnabled);\n}\n/* Function Name:\n *      rtl8367c_setAsicEavPriRemapping\n * Description:\n *      Set non-EAV streaming priority remapping\n * Input:\n *      srcpriority - Priority value\n *      priority     - Absolute priority value\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK                     - Success\n *      RT_ERR_SMI                  - SMI access error\n *      RT_ERR_QOS_INT_PRIORITY      - Invalid priority\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicEavPriRemapping(rtk_uint32 srcpriority, rtk_uint32 priority)\n{\n    if(srcpriority > RTL8367C_PRIMAX || priority > RTL8367C_PRIMAX)\n        return RT_ERR_QOS_INT_PRIORITY;\n\n    return rtl8367c_setAsicRegBits(RTL8367C_EAV_PRIORITY_REMAPPING_REG(srcpriority), RTL8367C_EAV_PRIORITY_REMAPPING_MASK(srcpriority),priority);\n}\n/* Function Name:\n *      rtl8367c_getAsicEavPriRemapping\n * Description:\n *      Get non-EAV streaming priority remapping\n * Input:\n *      srcpriority - Priority value\n *      pPriority     - Absolute priority value\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK                     - Success\n *      RT_ERR_SMI                  - SMI access error\n *      RT_ERR_QOS_INT_PRIORITY      - Invalid priority\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicEavPriRemapping(rtk_uint32 srcpriority, rtk_uint32 *pPriority)\n{\n    if(srcpriority > RTL8367C_PRIMAX )\n        return RT_ERR_QOS_INT_PRIORITY;\n\n    return rtl8367c_getAsicRegBits(RTL8367C_EAV_PRIORITY_REMAPPING_REG(srcpriority), RTL8367C_EAV_PRIORITY_REMAPPING_MASK(srcpriority),pPriority);\n}\n\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_eee.c",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * $Revision: 48989 $\n * $Date: 2014-07-01 15:45:24 +0800 (週二, 01 七月 2014) $\n *\n * Purpose : RTL8370 switch high-level API for RTL8367C\n * Feature :\n *\n */\n\n#include <rtl8367c_asicdrv_eee.h>\n#include <rtl8367c_asicdrv_phy.h>\n\n/*\n@func ret_t | rtl8367c_setAsicEee100M | Set eee force mode function enable/disable.\n@parm rtk_uint32 | port | The port number.\n@parm rtk_uint32 | enabled | 1: enabled, 0: disabled.\n@rvalue RT_ERR_OK | Success.\n@rvalue RT_ERR_SMI | SMI access error.\n@rvalue RT_ERR_INPUT | Invalid input parameter.\n@comm\n    This API set the 100M EEE enable function.\n\n*/\nret_t rtl8367c_setAsicEee100M(rtk_uint32 port, rtk_uint32 enable)\n{\n    rtk_api_ret_t   retVal;\n    rtk_uint32      regData;\n\n    if(port >= RTL8367C_PORTNO)\n        return RT_ERR_PORT_ID;\n\n    if (enable > 1)\n        return RT_ERR_INPUT;\n\n    if((retVal = rtl8367c_getAsicPHYOCPReg(port, EEE_OCP_PHY_ADDR, &regData)) != RT_ERR_OK)\n        return retVal;\n\n    if(enable)\n        regData |= (0x0001 << 1);\n    else\n        regData &= ~(0x0001 << 1);\n\n    if((retVal = rtl8367c_setAsicPHYOCPReg(port, EEE_OCP_PHY_ADDR, regData)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/*\n@func ret_t | rtl8367c_getAsicEee100M | Get 100M eee enable/disable.\n@parm rtk_uint32 | port | The port number.\n@parm rtk_uint32* | enabled | 1: enabled, 0: disabled.\n@rvalue RT_ERR_OK | Success.\n@rvalue RT_ERR_SMI | SMI access error.\n@rvalue RT_ERR_INPUT | Invalid input parameter.\n@comm\n    This API get the 100M EEE function.\n*/\nret_t rtl8367c_getAsicEee100M(rtk_uint32 port, rtk_uint32 *enable)\n{\n    rtk_api_ret_t   retVal;\n    rtk_uint32      regData;\n\n    if(port >= RTL8367C_PORTNO)\n        return RT_ERR_PORT_ID;\n\n    if((retVal = rtl8367c_getAsicPHYOCPReg(port, EEE_OCP_PHY_ADDR, &regData)) != RT_ERR_OK)\n        return retVal;\n\n    *enable = (regData & (0x0001 << 1)) ? ENABLED : DISABLED;\n    return RT_ERR_OK;\n}\n\n/*\n@func ret_t | rtl8367c_setAsicEeeGiga | Set eee force mode function enable/disable.\n@parm rtk_uint32 | port | The port number.\n@parm rtk_uint32 | enabled | 1: enabled, 0: disabled.\n@rvalue RT_ERR_OK | Success.\n@rvalue RT_ERR_SMI | SMI access error.\n@rvalue RT_ERR_INPUT | Invalid input parameter.\n@comm\n    This API set the 100M EEE enable function.\n\n*/\nret_t rtl8367c_setAsicEeeGiga(rtk_uint32 port, rtk_uint32 enable)\n{\n    rtk_api_ret_t   retVal;\n    rtk_uint32      regData;\n\n    if(port >= RTL8367C_PORTNO)\n        return RT_ERR_PORT_ID;\n\n    if (enable > 1)\n        return RT_ERR_INPUT;\n\n    if((retVal = rtl8367c_getAsicPHYOCPReg(port, EEE_OCP_PHY_ADDR, &regData)) != RT_ERR_OK)\n        return retVal;\n\n    if(enable)\n        regData |= (0x0001 << 2);\n    else\n        regData &= ~(0x0001 << 2);\n\n    if((retVal = rtl8367c_setAsicPHYOCPReg(port, EEE_OCP_PHY_ADDR, regData)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/*\n@func ret_t | rtl8367c_getAsicEeeGiga | Get 100M eee enable/disable.\n@parm rtk_uint32 | port | The port number.\n@parm rtk_uint32* | enabled | 1: enabled, 0: disabled.\n@rvalue RT_ERR_OK | Success.\n@rvalue RT_ERR_SMI | SMI access error.\n@rvalue RT_ERR_INPUT | Invalid input parameter.\n@comm\n    This API get the 100M EEE function.\n*/\nret_t rtl8367c_getAsicEeeGiga(rtk_uint32 port, rtk_uint32 *enable)\n{\n    rtk_api_ret_t   retVal;\n    rtk_uint32      regData;\n\n    if(port >= RTL8367C_PORTNO)\n        return RT_ERR_PORT_ID;\n\n    if((retVal = rtl8367c_getAsicPHYOCPReg(port, EEE_OCP_PHY_ADDR, &regData)) != RT_ERR_OK)\n        return retVal;\n\n    *enable = (regData & (0x0001 << 2)) ? ENABLED : DISABLED;\n    return RT_ERR_OK;\n}\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_fc.c",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * $Revision: 76306 $\n * $Date: 2017-03-08 15:13:58 +0800 (週三, 08 三月 2017) $\n *\n * Purpose : RTL8367C switch high-level API for RTL8367C\n * Feature : Flow control related functions\n *\n */\n\n#include <rtl8367c_asicdrv_fc.h>\n/* Function Name:\n *      rtl8367c_setAsicFlowControlSelect\n * Description:\n *      Set system flow control type\n * Input:\n *      select      - System flow control type 1: Ingress flow control 0:Egress flow control\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicFlowControlSelect(rtk_uint32 select)\n{\n    return rtl8367c_setAsicRegBit(RTL8367C_REG_FLOWCTRL_CTRL0, RTL8367C_FLOWCTRL_TYPE_OFFSET, select);\n}\n/* Function Name:\n *      rtl8367c_getAsicFlowControlSelect\n * Description:\n *      Get system flow control type\n * Input:\n *      pSelect         - System flow control type 1: Ingress flow control 0:Egress flow control\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicFlowControlSelect(rtk_uint32 *pSelect)\n{\n    return rtl8367c_getAsicRegBit(RTL8367C_REG_FLOWCTRL_CTRL0, RTL8367C_FLOWCTRL_TYPE_OFFSET, pSelect);\n}\n/* Function Name:\n *      rtl8367c_setAsicFlowControlJumboMode\n * Description:\n *      Set Jumbo threhsold for flow control\n * Input:\n *      enabled         - Jumbo mode flow control 1: Enable 0:Disable\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicFlowControlJumboMode(rtk_uint32 enabled)\n{\n    return rtl8367c_setAsicRegBit(RTL8367C_REG_FLOWCTRL_JUMBO_SIZE, RTL8367C_JUMBO_MODE_OFFSET, enabled);\n}\n/* Function Name:\n *      rtl8367c_getAsicFlowControlJumboMode\n * Description:\n *      Get Jumbo threhsold for flow control\n * Input:\n *      pEnabled        - Jumbo mode flow control 1: Enable 0:Disable\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicFlowControlJumboMode(rtk_uint32* pEnabled)\n{\n    return rtl8367c_getAsicRegBit(RTL8367C_REG_FLOWCTRL_JUMBO_SIZE, RTL8367C_JUMBO_MODE_OFFSET, pEnabled);\n}\n/* Function Name:\n *      rtl8367c_setAsicFlowControlJumboModeSize\n * Description:\n *      Set Jumbo size for Jumbo mode flow control\n * Input:\n *      size        - Jumbo size 0:3Kbytes 1:4Kbytes 2:6Kbytes 3:9Kbytes\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_OUT_OF_RANGE - input parameter out of range\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicFlowControlJumboModeSize(rtk_uint32 size)\n{\n    if(size >= FC_JUMBO_SIZE_END)\n        return RT_ERR_OUT_OF_RANGE;\n\n    return rtl8367c_setAsicRegBits(RTL8367C_REG_FLOWCTRL_JUMBO_SIZE, RTL8367C_JUMBO_SIZE_MASK, size);\n}\n/* Function Name:\n *      rtl8367c_getAsicFlowControlJumboModeSize\n * Description:\n *      Get Jumbo size for Jumbo mode flow control\n * Input:\n *      pSize       - Jumbo size 0:3Kbytes 1:4Kbytes 2:6Kbytes 3:9Kbytes\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicFlowControlJumboModeSize(rtk_uint32* pSize)\n{\n    return rtl8367c_getAsicRegBits(RTL8367C_REG_FLOWCTRL_JUMBO_SIZE, RTL8367C_JUMBO_SIZE_MASK, pSize);\n}\n\n/* Function Name:\n *      rtl8367c_setAsicFlowControlQueueEgressEnable\n * Description:\n *      Set flow control ability for each queue\n * Input:\n *      port    - Physical port number (0~7)\n *      qid     - Queue id\n *      enabled - 1: enabled, 0: disabled\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n *      RT_ERR_PORT_ID  - Invalid port number\n *      RT_ERR_QUEUE_ID - Invalid queue id\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicFlowControlQueueEgressEnable(rtk_uint32 port, rtk_uint32 qid, rtk_uint32 enabled)\n{\n    if(port > RTL8367C_PORTIDMAX)\n        return RT_ERR_PORT_ID;\n\n    if(qid > RTL8367C_QIDMAX)\n        return RT_ERR_QUEUE_ID;\n\n    return rtl8367c_setAsicRegBit(RTL8367C_FLOWCRTL_EGRESS_QUEUE_ENABLE_REG(port), RTL8367C_FLOWCRTL_EGRESS_QUEUE_ENABLE_REG_OFFSET(port)+ qid, enabled);\n}\n/* Function Name:\n *      rtl8367c_getAsicFlowControlQueueEgressEnable\n * Description:\n *      Get flow control ability for each queue\n * Input:\n *      port    - Physical port number (0~7)\n *      qid     - Queue id\n *      pEnabled - 1: enabled, 0: disabled\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n *      RT_ERR_PORT_ID  - Invalid port number\n *      RT_ERR_QUEUE_ID - Invalid queue id\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicFlowControlQueueEgressEnable(rtk_uint32 port, rtk_uint32 qid, rtk_uint32* pEnabled)\n{\n    if(port > RTL8367C_PORTIDMAX)\n        return RT_ERR_PORT_ID;\n\n    if(qid > RTL8367C_QIDMAX)\n        return RT_ERR_QUEUE_ID;\n\n    return  rtl8367c_getAsicRegBit(RTL8367C_FLOWCRTL_EGRESS_QUEUE_ENABLE_REG(port), RTL8367C_FLOWCRTL_EGRESS_QUEUE_ENABLE_REG_OFFSET(port)+ qid, pEnabled);\n}\n/* Function Name:\n *      rtl8367c_setAsicFlowControlDropAll\n * Description:\n *      Set system-based drop parameters\n * Input:\n *      dropall     - Whole system drop threshold\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_OUT_OF_RANGE - input parameter out of range\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicFlowControlDropAll(rtk_uint32 dropall)\n{\n    if(dropall >= RTL8367C_PAGE_NUMBER)\n        return RT_ERR_OUT_OF_RANGE;\n\n    return rtl8367c_setAsicRegBits(RTL8367C_REG_FLOWCTRL_CTRL0, RTL8367C_DROP_ALL_THRESHOLD_MASK, dropall);\n}\n/* Function Name:\n *      rtl8367c_getAsicFlowControlDropAll\n * Description:\n *      Get system-based drop parameters\n * Input:\n *      pDropall    - Whole system drop threshold\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicFlowControlDropAll(rtk_uint32* pDropall)\n{\n    return rtl8367c_getAsicRegBits(RTL8367C_REG_FLOWCTRL_CTRL0, RTL8367C_DROP_ALL_THRESHOLD_MASK, pDropall);\n}\n/* Function Name:\n *      rtl8367c_setAsicFlowControlPauseAll\n * Description:\n *      Set system-based all ports enable flow control parameters\n * Input:\n *      threshold   - Whole system pause all threshold\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_OUT_OF_RANGE - input parameter out of range\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicFlowControlPauseAllThreshold(rtk_uint32 threshold)\n{\n    if(threshold >= RTL8367C_PAGE_NUMBER)\n        return RT_ERR_OUT_OF_RANGE;\n\n    return rtl8367c_setAsicRegBits(RTL8367C_REG_FLOWCTRL_ALL_ON, RTL8367C_FLOWCTRL_ALL_ON_THRESHOLD_MASK, threshold);\n}\n/* Function Name:\n *      rtl8367c_getAsicFlowControlPauseAllThreshold\n * Description:\n *      Get system-based all ports enable flow control parameters\n * Input:\n *      pThreshold  - Whole system pause all threshold\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicFlowControlPauseAllThreshold(rtk_uint32 *pThreshold)\n{\n    return rtl8367c_getAsicRegBits(RTL8367C_REG_FLOWCTRL_ALL_ON, RTL8367C_FLOWCTRL_ALL_ON_THRESHOLD_MASK, pThreshold);\n}\n/* Function Name:\n *      rtl8367c_setAsicFlowControlSystemThreshold\n * Description:\n *      Set system-based flow control parameters\n * Input:\n *      onThreshold     - Flow control turn ON threshold\n *      offThreshold    - Flow control turn OFF threshold\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_OUT_OF_RANGE - input parameter out of range\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicFlowControlSystemThreshold(rtk_uint32 onThreshold, rtk_uint32 offThreshold)\n{\n    ret_t retVal;\n\n    if((onThreshold >= RTL8367C_PAGE_NUMBER) || (offThreshold >= RTL8367C_PAGE_NUMBER))\n        return RT_ERR_OUT_OF_RANGE;\n\n    retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_FLOWCTRL_SYS_OFF, RTL8367C_FLOWCTRL_SYS_OFF_MASK, offThreshold);\n\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_FLOWCTRL_SYS_ON, RTL8367C_FLOWCTRL_SYS_ON_MASK, onThreshold);\n\n    return retVal;\n}\n/* Function Name:\n *      rtl8367c_getAsicFlowControlSystemThreshold\n * Description:\n *      Get system-based flow control parameters\n * Input:\n *      pOnThreshold    - Flow control turn ON threshold\n *      pOffThreshold   - Flow control turn OFF threshold\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicFlowControlSystemThreshold(rtk_uint32 *pOnThreshold, rtk_uint32 *pOffThreshold)\n{\n    ret_t retVal;\n\n    retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_FLOWCTRL_SYS_OFF, RTL8367C_FLOWCTRL_SYS_OFF_MASK, pOffThreshold);\n\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_FLOWCTRL_SYS_ON, RTL8367C_FLOWCTRL_SYS_ON_MASK, pOnThreshold);\n\n    return retVal;\n}\n/* Function Name:\n *      rtl8367c_setAsicFlowControlSharedThreshold\n * Description:\n *      Set share-based flow control parameters\n * Input:\n *      onThreshold     - Flow control turn ON threshold\n *      offThreshold    - Flow control turn OFF threshold\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_OUT_OF_RANGE - input parameter out of range\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicFlowControlSharedThreshold(rtk_uint32 onThreshold, rtk_uint32 offThreshold)\n{\n    ret_t retVal;\n\n    if((onThreshold >= RTL8367C_PAGE_NUMBER) || (offThreshold >= RTL8367C_PAGE_NUMBER))\n        return RT_ERR_OUT_OF_RANGE;\n\n    retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_FLOWCTRL_SHARE_OFF, RTL8367C_FLOWCTRL_SHARE_OFF_MASK, offThreshold);\n\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_FLOWCTRL_SHARE_ON, RTL8367C_FLOWCTRL_SHARE_ON_MASK, onThreshold);\n\n    return retVal;\n}\n/* Function Name:\n *      rtl8367c_getAsicFlowControlSharedThreshold\n * Description:\n *      Get share-based flow control parameters\n * Input:\n *      pOnThreshold    - Flow control turn ON threshold\n *      pOffThreshold   - Flow control turn OFF threshold\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicFlowControlSharedThreshold(rtk_uint32 *pOnThreshold, rtk_uint32 *pOffThreshold)\n{\n    ret_t retVal;\n\n    retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_FLOWCTRL_SHARE_OFF, RTL8367C_FLOWCTRL_SHARE_OFF_MASK, pOffThreshold);\n\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_FLOWCTRL_SHARE_ON, RTL8367C_FLOWCTRL_SHARE_ON_MASK, pOnThreshold);\n\n    return retVal;\n}\n/* Function Name:\n *      rtl8367c_setAsicFlowControlPortThreshold\n * Description:\n *      Set Port-based flow control parameters\n * Input:\n *      onThreshold     - Flow control turn ON threshold\n *      offThreshold    - Flow control turn OFF threshold\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_OUT_OF_RANGE - input parameter out of range\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicFlowControlPortThreshold(rtk_uint32 onThreshold, rtk_uint32 offThreshold)\n{\n    ret_t retVal;\n\n    if((onThreshold >= RTL8367C_PAGE_NUMBER) || (offThreshold >= RTL8367C_PAGE_NUMBER))\n        return RT_ERR_OUT_OF_RANGE;\n\n    retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_FLOWCTRL_PORT_OFF, RTL8367C_FLOWCTRL_PORT_OFF_MASK, offThreshold);\n\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_FLOWCTRL_PORT_ON, RTL8367C_FLOWCTRL_PORT_ON_MASK, onThreshold);\n\n    return retVal;\n}\n/* Function Name:\n *      rtl8367c_getAsicFlowControlPortThreshold\n * Description:\n *      Get Port-based flow control parameters\n * Input:\n *      pOnThreshold    - Flow control turn ON threshold\n *      pOffThreshold   - Flow control turn OFF threshold\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicFlowControlPortThreshold(rtk_uint32 *pOnThreshold, rtk_uint32 *pOffThreshold)\n{\n    ret_t retVal;\n\n    retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_FLOWCTRL_PORT_OFF, RTL8367C_FLOWCTRL_PORT_OFF_MASK, pOffThreshold);\n\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_FLOWCTRL_PORT_ON, RTL8367C_FLOWCTRL_PORT_ON_MASK, pOnThreshold);\n\n    return retVal;\n}\n/* Function Name:\n *      rtl8367c_setAsicFlowControlPortPrivateThreshold\n * Description:\n *      Set Port-private-based flow control parameters\n * Input:\n *      onThreshold     - Flow control turn ON threshold\n *      offThreshold    - Flow control turn OFF threshold\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_OUT_OF_RANGE - input parameter out of range\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicFlowControlPortPrivateThreshold(rtk_uint32 onThreshold, rtk_uint32 offThreshold)\n{\n    ret_t retVal;\n\n    if((onThreshold >= RTL8367C_PAGE_NUMBER) || (offThreshold >= RTL8367C_PAGE_NUMBER))\n        return RT_ERR_OUT_OF_RANGE;\n\n    retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_FLOWCTRL_PORT_PRIVATE_OFF, RTL8367C_FLOWCTRL_PORT_PRIVATE_OFF_MASK, offThreshold);\n\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_FLOWCTRL_PORT_PRIVATE_ON, RTL8367C_FLOWCTRL_PORT_PRIVATE_ON_MASK, onThreshold);\n\n    return retVal;\n}\n/* Function Name:\n *      rtl8367c_getAsicFlowControlPortPrivateThreshold\n * Description:\n *      Get Port-private-based flow control parameters\n * Input:\n *      pOnThreshold    - Flow control turn ON threshold\n *      pOffThreshold   - Flow control turn OFF threshold\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicFlowControlPortPrivateThreshold(rtk_uint32 *pOnThreshold, rtk_uint32 *pOffThreshold)\n{\n    ret_t retVal;\n\n    retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_FLOWCTRL_PORT_PRIVATE_OFF, RTL8367C_FLOWCTRL_PORT_PRIVATE_OFF_MASK, pOffThreshold);\n\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_FLOWCTRL_PORT_PRIVATE_ON, RTL8367C_FLOWCTRL_PORT_PRIVATE_ON_MASK, pOnThreshold);\n\n    return retVal;\n}\n/* Function Name:\n *      rtl8367c_setAsicFlowControlSystemDropThreshold\n * Description:\n *      Set system-based drop parameters\n * Input:\n *      onThreshold     - Drop turn ON threshold\n *      offThreshold    - Drop turn OFF threshold\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_OUT_OF_RANGE - input parameter out of range\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicFlowControlSystemDropThreshold(rtk_uint32 onThreshold, rtk_uint32 offThreshold)\n{\n    ret_t retVal;\n\n    if((onThreshold >= RTL8367C_PAGE_NUMBER) || (offThreshold >= RTL8367C_PAGE_NUMBER))\n        return RT_ERR_OUT_OF_RANGE;\n\n    retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_FLOWCTRL_FCOFF_SYS_OFF, RTL8367C_FLOWCTRL_FCOFF_SYS_OFF_MASK, offThreshold);\n\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_FLOWCTRL_FCOFF_SYS_ON, RTL8367C_FLOWCTRL_FCOFF_SYS_ON_MASK, onThreshold);\n\n    return retVal;\n}\n/* Function Name:\n *      rtl8367c_getAsicFlowControlSystemDropThreshold\n * Description:\n *      Get system-based drop parameters\n * Input:\n *      pOnThreshold    - Drop turn ON threshold\n *      pOffThreshold   - Drop turn OFF threshold\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicFlowControlSystemDropThreshold(rtk_uint32 *pOnThreshold, rtk_uint32 *pOffThreshold)\n{\n    ret_t retVal;\n\n    retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_FLOWCTRL_FCOFF_SYS_OFF, RTL8367C_FLOWCTRL_FCOFF_SYS_OFF_MASK, pOffThreshold);\n\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_FLOWCTRL_FCOFF_SYS_ON, RTL8367C_FLOWCTRL_FCOFF_SYS_ON_MASK, pOnThreshold);\n\n    return retVal;\n}\n/* Function Name:\n *      rtl8367c_setAsicFlowControlSharedDropThreshold\n * Description:\n *      Set share-based fdrop parameters\n * Input:\n *      onThreshold     - Drop turn ON threshold\n *      offThreshold    - Drop turn OFF threshold\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_OUT_OF_RANGE - input parameter out of range\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicFlowControlSharedDropThreshold(rtk_uint32 onThreshold, rtk_uint32 offThreshold)\n{\n    ret_t retVal;\n\n    if((onThreshold >= RTL8367C_PAGE_NUMBER) || (offThreshold >= RTL8367C_PAGE_NUMBER))\n        return RT_ERR_OUT_OF_RANGE;\n\n    retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_FLOWCTRL_FCOFF_SHARE_OFF, RTL8367C_FLOWCTRL_FCOFF_SHARE_OFF_MASK, offThreshold);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_FLOWCTRL_FCOFF_SHARE_ON, RTL8367C_FLOWCTRL_FCOFF_SHARE_ON_MASK, onThreshold);\n\n    return retVal;\n}\n/* Function Name:\n *      rtl8367c_getAsicFlowControlSharedDropThreshold\n * Description:\n *      Get share-based fdrop parameters\n * Input:\n *      pOnThreshold    - Drop turn ON threshold\n *      pOffThreshold   - Drop turn OFF threshold\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicFlowControlSharedDropThreshold(rtk_uint32 *pOnThreshold, rtk_uint32 *pOffThreshold)\n{\n    ret_t retVal;\n\n    retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_FLOWCTRL_FCOFF_SHARE_OFF, RTL8367C_FLOWCTRL_FCOFF_SHARE_OFF_MASK, pOffThreshold);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_FLOWCTRL_FCOFF_SHARE_ON, RTL8367C_FLOWCTRL_FCOFF_SHARE_ON_MASK, pOnThreshold);\n\n    return retVal;\n}\n/* Function Name:\n *      rtl8367c_setAsicFlowControlPortDropThreshold\n * Description:\n *      Set Port-based drop parameters\n * Input:\n *      onThreshold     - Drop turn ON threshold\n *      offThreshold    - Drop turn OFF threshold\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_OUT_OF_RANGE - input parameter out of range\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicFlowControlPortDropThreshold(rtk_uint32 onThreshold, rtk_uint32 offThreshold)\n{\n    ret_t retVal;\n\n    if((onThreshold >= RTL8367C_PAGE_NUMBER) || (offThreshold >= RTL8367C_PAGE_NUMBER))\n        return RT_ERR_OUT_OF_RANGE;\n\n    retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_FLOWCTRL_FCOFF_PORT_OFF, RTL8367C_FLOWCTRL_FCOFF_PORT_OFF_MASK, offThreshold);\n\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_FLOWCTRL_FCOFF_PORT_ON, RTL8367C_FLOWCTRL_FCOFF_PORT_ON_MASK, onThreshold);\n\n    return retVal;\n}\n/* Function Name:\n *      rtl8367c_getAsicFlowControlPortDropThreshold\n * Description:\n *      Get Port-based drop parameters\n * Input:\n *      pOnThreshold    - Drop turn ON threshold\n *      pOffThreshold   - Drop turn OFF threshold\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicFlowControlPortDropThreshold(rtk_uint32 *pOnThreshold, rtk_uint32 *pOffThreshold)\n{\n    ret_t retVal;\n\n    retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_FLOWCTRL_FCOFF_PORT_OFF, RTL8367C_FLOWCTRL_FCOFF_PORT_OFF_MASK, pOffThreshold);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_FLOWCTRL_FCOFF_PORT_ON, RTL8367C_FLOWCTRL_FCOFF_PORT_ON_MASK, pOnThreshold);\n\n    return retVal;\n}\n/* Function Name:\n *      rtl8367c_setAsicFlowControlPortPrivateDropThreshold\n * Description:\n *      Set Port-private-based drop parameters\n * Input:\n *      onThreshold     - Drop turn ON threshold\n *      offThreshold    - Drop turn OFF threshold\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_OUT_OF_RANGE - input parameter out of range\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicFlowControlPortPrivateDropThreshold(rtk_uint32 onThreshold, rtk_uint32 offThreshold)\n{\n    ret_t retVal;\n\n    if((onThreshold >= RTL8367C_PAGE_NUMBER) || (offThreshold >= RTL8367C_PAGE_NUMBER))\n        return RT_ERR_OUT_OF_RANGE;\n\n    retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_FLOWCTRL_FCOFF_PORT_PRIVATE_OFF, RTL8367C_FLOWCTRL_FCOFF_PORT_PRIVATE_OFF_MASK, offThreshold);\n\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_FLOWCTRL_FCOFF_PORT_PRIVATE_ON, RTL8367C_FLOWCTRL_FCOFF_PORT_PRIVATE_ON_MASK, onThreshold);\n\n    return retVal;\n}\n/* Function Name:\n *      rtl8367c_getAsicFlowControlPortPrivateDropThreshold\n * Description:\n *      Get Port-private-based drop parameters\n * Input:\n *      pOnThreshold    - Drop turn ON threshold\n *      pOffThreshold   - Drop turn OFF threshold\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicFlowControlPortPrivateDropThreshold(rtk_uint32 *pOnThreshold, rtk_uint32 *pOffThreshold)\n{\n    ret_t retVal;\n\n    retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_FLOWCTRL_FCOFF_PORT_PRIVATE_OFF, RTL8367C_FLOWCTRL_FCOFF_PORT_PRIVATE_OFF_MASK, pOffThreshold);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_FLOWCTRL_FCOFF_PORT_PRIVATE_ON, RTL8367C_FLOWCTRL_FCOFF_PORT_PRIVATE_ON_MASK, pOnThreshold);\n\n    return retVal;\n}\n/* Function Name:\n *      rtl8367c_setAsicFlowControlSystemJumboThreshold\n * Description:\n *      Set Jumbo system-based flow control parameters\n * Input:\n *      onThreshold     - Flow control turn ON threshold\n *      offThreshold    - Flow control turn OFF threshold\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_OUT_OF_RANGE - input parameter out of range\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicFlowControlSystemJumboThreshold(rtk_uint32 onThreshold, rtk_uint32 offThreshold)\n{\n    ret_t retVal;\n\n    if((onThreshold >= RTL8367C_PAGE_NUMBER) || (offThreshold >= RTL8367C_PAGE_NUMBER))\n        return RT_ERR_OUT_OF_RANGE;\n\n    retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_FLOWCTRL_JUMBO_SYS_OFF, RTL8367C_FLOWCTRL_JUMBO_SYS_OFF_MASK, offThreshold);\n\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_FLOWCTRL_JUMBO_SYS_ON, RTL8367C_FLOWCTRL_JUMBO_SYS_ON_MASK, onThreshold);\n\n    return retVal;\n}\n/* Function Name:\n *      rtl8367c_getAsicFlowControlSystemJumboThreshold\n * Description:\n *      Get Jumbo system-based flow control parameters\n * Input:\n *      pOnThreshold    - Flow control turn ON threshold\n *      pOffThreshold   - Flow control turn OFF threshold\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicFlowControlSystemJumboThreshold(rtk_uint32 *pOnThreshold, rtk_uint32 *pOffThreshold)\n{\n    ret_t retVal;\n\n    retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_FLOWCTRL_JUMBO_SYS_OFF, RTL8367C_FLOWCTRL_JUMBO_SYS_OFF_MASK, pOffThreshold);\n\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_FLOWCTRL_JUMBO_SYS_ON, RTL8367C_FLOWCTRL_JUMBO_SYS_ON_MASK, pOnThreshold);\n\n    return retVal;\n}\n/* Function Name:\n *      rtl8367c_setAsicFlowControlSharedJumboThreshold\n * Description:\n *      Set Jumbo share-based flow control parameters\n * Input:\n *      onThreshold     - Flow control turn ON threshold\n *      offThreshold    - Flow control turn OFF threshold\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_OUT_OF_RANGE - input parameter out of range\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicFlowControlSharedJumboThreshold(rtk_uint32 onThreshold, rtk_uint32 offThreshold)\n{\n    ret_t retVal;\n\n    if((onThreshold >= RTL8367C_PAGE_NUMBER) || (offThreshold >= RTL8367C_PAGE_NUMBER))\n        return RT_ERR_OUT_OF_RANGE;\n\n    retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_FLOWCTRL_JUMBO_SHARE_OFF, RTL8367C_FLOWCTRL_JUMBO_SHARE_OFF_MASK, offThreshold);\n\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_FLOWCTRL_JUMBO_SHARE_ON, RTL8367C_FLOWCTRL_JUMBO_SHARE_ON_MASK, onThreshold);\n\n    return retVal;\n}\n/* Function Name:\n *      rtl8367c_getAsicFlowControlSharedJumboThreshold\n * Description:\n *      Get Jumbo share-based flow control parameters\n * Input:\n *      pOnThreshold    - Flow control turn ON threshold\n *      pOffThreshold   - Flow control turn OFF threshold\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicFlowControlSharedJumboThreshold(rtk_uint32 *pOnThreshold, rtk_uint32 *pOffThreshold)\n{\n    ret_t retVal;\n\n    retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_FLOWCTRL_JUMBO_SHARE_OFF, RTL8367C_FLOWCTRL_JUMBO_SHARE_OFF_MASK, pOffThreshold);\n\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_FLOWCTRL_JUMBO_SHARE_ON, RTL8367C_FLOWCTRL_JUMBO_SHARE_ON_MASK, pOnThreshold);\n\n    return retVal;\n}\n/* Function Name:\n *      rtl8367c_setAsicFlowControlPortJumboThreshold\n * Description:\n *      Set Jumbo Port-based flow control parameters\n * Input:\n *      onThreshold     - Flow control turn ON threshold\n *      offThreshold    - Flow control turn OFF threshold\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_OUT_OF_RANGE - input parameter out of range\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicFlowControlPortJumboThreshold(rtk_uint32 onThreshold, rtk_uint32 offThreshold)\n{\n    ret_t retVal;\n\n    if((onThreshold >= RTL8367C_PAGE_NUMBER) || (offThreshold >= RTL8367C_PAGE_NUMBER))\n        return RT_ERR_OUT_OF_RANGE;\n\n    retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_FLOWCTRL_JUMBO_PORT_OFF, RTL8367C_FLOWCTRL_JUMBO_PORT_OFF_MASK, offThreshold);\n\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_FLOWCTRL_JUMBO_PORT_ON, RTL8367C_FLOWCTRL_JUMBO_PORT_ON_MASK, onThreshold);\n\n    return retVal;\n}\n/* Function Name:\n *      rtl8367c_getAsicFlowControlPortJumboThreshold\n * Description:\n *      Get Jumbo Port-based flow control parameters\n * Input:\n *      pOnThreshold    - Flow control turn ON threshold\n *      pOffThreshold   - Flow control turn OFF threshold\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicFlowControlPortJumboThreshold(rtk_uint32 *pOnThreshold, rtk_uint32 *pOffThreshold)\n{\n    ret_t retVal;\n\n    retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_FLOWCTRL_JUMBO_PORT_OFF, RTL8367C_FLOWCTRL_JUMBO_PORT_OFF_MASK, pOffThreshold);\n\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_FLOWCTRL_JUMBO_PORT_ON, RTL8367C_FLOWCTRL_JUMBO_PORT_ON_MASK, pOnThreshold);\n\n    return retVal;\n}\n/* Function Name:\n *      rtl8367c_setAsicFlowControlPortPrivateJumboThreshold\n * Description:\n *      Set Jumbo Port-private-based flow control parameters\n * Input:\n *      onThreshold     - Flow control turn ON threshold\n *      offThreshold    - Flow control turn OFF threshold\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_OUT_OF_RANGE - input parameter out of range\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicFlowControlPortPrivateJumboThreshold(rtk_uint32 onThreshold, rtk_uint32 offThreshold)\n{\n    ret_t retVal;\n\n    if((onThreshold >= RTL8367C_PAGE_NUMBER) || (offThreshold >= RTL8367C_PAGE_NUMBER))\n        return RT_ERR_OUT_OF_RANGE;\n\n    retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_FLOWCTRL_JUMBO_PORT_PRIVATE_OFF, RTL8367C_FLOWCTRL_JUMBO_PORT_PRIVATE_OFF_MASK, offThreshold);\n\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_FLOWCTRL_JUMBO_PORT_PRIVATE_ON, RTL8367C_FLOWCTRL_JUMBO_PORT_PRIVATE_ON_MASK, onThreshold);\n\n    return retVal;\n}\n/* Function Name:\n *      rtl8367c_getAsicFlowControlPortPrivateJumboThreshold\n * Description:\n *      Get Jumbo Port-private-based flow control parameters\n * Input:\n *      pOnThreshold    - Flow control turn ON threshold\n *      pOffThreshold   - Flow control turn OFF threshold\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicFlowControlPortPrivateJumboThreshold(rtk_uint32 *pOnThreshold, rtk_uint32 *pOffThreshold)\n{\n    ret_t retVal;\n\n    retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_FLOWCTRL_JUMBO_PORT_PRIVATE_OFF, RTL8367C_FLOWCTRL_JUMBO_PORT_PRIVATE_OFF_MASK, pOffThreshold);\n\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_FLOWCTRL_JUMBO_PORT_PRIVATE_ON, RTL8367C_FLOWCTRL_JUMBO_PORT_PRIVATE_ON_MASK, pOnThreshold);\n\n    return retVal;\n}\n\n\n\n/* Function Name:\n *      rtl8367c_setAsicEgressFlowControlQueueDropThreshold\n * Description:\n *      Set Queue-based egress flow control turn on or ingress flow control drop on threshold\n * Input:\n *      qid         - The queue id\n *      threshold   - Queue-based flown control/drop turn ON threshold\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_OUT_OF_RANGE - input parameter out of range\n *      RT_ERR_QUEUE_ID     - Invalid queue id\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicEgressFlowControlQueueDropThreshold(rtk_uint32 qid, rtk_uint32 threshold)\n{\n    if( threshold >= RTL8367C_PAGE_NUMBER)\n        return RT_ERR_OUT_OF_RANGE;\n\n    if(qid > RTL8367C_QIDMAX)\n        return RT_ERR_QUEUE_ID;\n\n    return rtl8367c_setAsicRegBits(RTL8367C_FLOWCTRL_QUEUE_DROP_ON_REG(qid), RTL8367C_FLOWCTRL_QUEUE_DROP_ON_MASK, threshold);\n}\n/* Function Name:\n *      rtl8367c_getAsicEgressFlowControlQueueDropThreshold\n * Description:\n *      Get Queue-based egress flow control turn on or ingress flow control drop on threshold\n * Input:\n *      qid         - The queue id\n *      pThreshold  - Queue-based flown control/drop turn ON threshold\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_QUEUE_ID     - Invalid queue id\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicEgressFlowControlQueueDropThreshold(rtk_uint32 qid, rtk_uint32 *pThreshold)\n{\n    if(qid > RTL8367C_QIDMAX)\n      return RT_ERR_QUEUE_ID;\n\n    return rtl8367c_getAsicRegBits(RTL8367C_FLOWCTRL_QUEUE_DROP_ON_REG(qid), RTL8367C_FLOWCTRL_QUEUE_DROP_ON_MASK, pThreshold);\n}\n/* Function Name:\n *      rtl8367c_setAsicEgressFlowControlPortDropThreshold\n * Description:\n *      Set port-based egress flow control turn on or ingress flow control drop on threshold\n * Input:\n *      port        - Physical port number (0~7)\n *      threshold   - Queue-based flown control/drop turn ON threshold\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number\n *      RT_ERR_OUT_OF_RANGE - input parameter out of range\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicEgressFlowControlPortDropThreshold(rtk_uint32 port, rtk_uint32 threshold)\n{\n    if(port > RTL8367C_PORTIDMAX)\n      return RT_ERR_PORT_ID;\n\n    if(threshold >= RTL8367C_PAGE_NUMBER)\n      return RT_ERR_OUT_OF_RANGE;\n\n    return rtl8367c_setAsicRegBits(RTL8367C_FLOWCTRL_PORT_DROP_ON_REG(port), RTL8367C_FLOWCTRL_PORT_DROP_ON_MASK, threshold);\n}\n/* Function Name:\n *      rtl8367c_setAsicEgressFlowControlPortDropThreshold\n * Description:\n *      Set port-based egress flow control turn on or ingress flow control drop on threshold\n * Input:\n *      port        - Physical port number (0~7)\n *      pThreshold  - Queue-based flown control/drop turn ON threshold\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicEgressFlowControlPortDropThreshold(rtk_uint32 port, rtk_uint32 *pThreshold)\n{\n    if(port > RTL8367C_PORTIDMAX)\n        return RT_ERR_PORT_ID;\n\n    return rtl8367c_getAsicRegBits(RTL8367C_FLOWCTRL_PORT_DROP_ON_REG(port), RTL8367C_FLOWCTRL_PORT_DROP_ON_MASK, pThreshold);\n}\n/* Function Name:\n *      rtl8367c_setAsicEgressFlowControlPortDropGap\n * Description:\n *      Set port-based egress flow control turn off or ingress flow control drop off gap\n * Input:\n *      gap     - Flow control/drop turn OFF threshold = turn ON threshold - gap\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_OUT_OF_RANGE - input parameter out of range\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicEgressFlowControlPortDropGap(rtk_uint32 gap)\n{\n    if(gap >= RTL8367C_PAGE_NUMBER)\n        return RT_ERR_OUT_OF_RANGE;\n\n    return rtl8367c_setAsicRegBits(RTL8367C_REG_FLOWCTRL_PORT_GAP, RTL8367C_FLOWCTRL_PORT_GAP_MASK, gap);\n}\n/* Function Name:\n *      rtl8367c_getAsicEgressFlowControlPortDropGap\n * Description:\n *      Get port-based egress flow control turn off or ingress flow control drop off gap\n * Input:\n *      pGap    - Flow control/drop turn OFF threshold = turn ON threshold - gap\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicEgressFlowControlPortDropGap(rtk_uint32 *pGap)\n{\n    return rtl8367c_getAsicRegBits(RTL8367C_REG_FLOWCTRL_PORT_GAP, RTL8367C_FLOWCTRL_PORT_GAP_MASK, pGap);\n}\n/* Function Name:\n *      rtl8367c_setAsicEgressFlowControlQueueDropGap\n * Description:\n *      Set Queue-based egress flow control turn off or ingress flow control drop off gap\n * Input:\n *      gap     - Flow control/drop turn OFF threshold = turn ON threshold - gap\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_OUT_OF_RANGE - input parameter out of range\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicEgressFlowControlQueueDropGap(rtk_uint32 gap)\n{\n    if(gap >= RTL8367C_PAGE_NUMBER)\n        return RT_ERR_OUT_OF_RANGE;\n\n    return rtl8367c_setAsicRegBits(RTL8367C_REG_FLOWCTRL_QUEUE_GAP, RTL8367C_FLOWCTRL_QUEUE_GAP_MASK, gap);\n}\n/* Function Name:\n *      rtl8367c_getAsicEgressFlowControlQueueDropGap\n * Description:\n *      Get Queue-based egress flow control turn off or ingress flow control drop off gap\n * Input:\n *      pGap    - Flow control/drop turn OFF threshold = turn ON threshold - gap\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicEgressFlowControlQueueDropGap(rtk_uint32 *pGap)\n{\n    return rtl8367c_getAsicRegBits(RTL8367C_REG_FLOWCTRL_QUEUE_GAP, RTL8367C_FLOWCTRL_QUEUE_GAP_MASK, pGap);\n}\n/* Function Name:\n *      rtl8367c_getAsicEgressQueueEmptyPortMask\n * Description:\n *      Get queue empty port mask\n * Input:\n *      pPortmask   -  Queue empty port mask\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicEgressQueueEmptyPortMask(rtk_uint32 *pPortmask)\n{\n    return rtl8367c_getAsicReg(RTL8367C_REG_PORT_QEMPTY, pPortmask);\n}\n/* Function Name:\n *      rtl8367c_getAsicTotalPage\n * Description:\n *      Get system total page usage number\n * Input:\n *      pPageCount  -  page usage number\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicTotalPage(rtk_uint32 *pPageCount)\n{\n    return rtl8367c_getAsicRegBits(RTL8367C_REG_FLOWCTRL_TOTAL_PAGE_COUNTER, RTL8367C_FLOWCTRL_TOTAL_PAGE_COUNTER_MASK, pPageCount);\n}\n/* Function Name:\n *      rtl8367c_getAsicPulbicPage\n * Description:\n *      Get system public page usage number\n * Input:\n *      pPageCount  -  page usage number\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicPulbicPage(rtk_uint32 *pPageCount)\n{\n    return rtl8367c_getAsicRegBits(RTL8367C_REG_FLOWCTRL_PUBLIC_PAGE_COUNTER, RTL8367C_FLOWCTRL_PUBLIC_PAGE_COUNTER_MASK, pPageCount);\n}\n/* Function Name:\n *      rtl8367c_getAsicMaxTotalPage\n * Description:\n *      Get system total page max usage number\n * Input:\n *      pPageCount  -  page usage number\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicMaxTotalPage(rtk_uint32 *pPageCount)\n{\n    return rtl8367c_getAsicRegBits(RTL8367C_REG_FLOWCTRL_TOTAL_PAGE_MAX, RTL8367C_FLOWCTRL_TOTAL_PAGE_MAX_MASK, pPageCount);\n}\n/* Function Name:\n *      rtl8367c_getAsicPulbicPage\n * Description:\n *      Get system public page max usage number\n * Input:\n *      pPageCount  -  page usage number\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicMaxPulbicPage(rtk_uint32 *pPageCount)\n{\n    return rtl8367c_getAsicRegBits(RTL8367C_REG_FLOWCTRL_PUBLIC_PAGE_MAX, RTL8367C_FLOWCTRL_PUBLIC_PAGE_MAX_MASK, pPageCount);\n}\n/* Function Name:\n *      rtl8367c_getAsicPortPage\n * Description:\n *      Get per-port page usage number\n * Input:\n *      port        -  Physical port number (0~7)\n *      pPageCount  -  page usage number\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n *      RT_ERR_PORT_ID  - Invalid port number\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicPortPage(rtk_uint32 port, rtk_uint32 *pPageCount)\n{\n    if(port > RTL8367C_PORTIDMAX)\n        return RT_ERR_PORT_ID;\n\n    if(port < 8)\n        return rtl8367c_getAsicRegBits(RTL8367C_FLOWCTRL_PORT_PAGE_COUNTER_REG(port), RTL8367C_FLOWCTRL_PORT_PAGE_COUNTER_MASK, pPageCount);\n    else\n        return rtl8367c_getAsicRegBits(RTL8367C_REG_FLOWCTRL_PORT8_PAGE_COUNTER+port - 8, RTL8367C_FLOWCTRL_PORT_PAGE_COUNTER_MASK, pPageCount);\n}\n/* Function Name:\n *      rtl8367c_getAsicPortPage\n * Description:\n *      Get per-port page max usage number\n * Input:\n *      port        -  Physical port number (0~7)\n *      pPageCount  -  page usage number\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n *      RT_ERR_PORT_ID  - Invalid port number\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicPortPageMax(rtk_uint32 port, rtk_uint32 *pPageCount)\n{\n    if(port > RTL8367C_PORTIDMAX)\n        return RT_ERR_PORT_ID;\n    if(port < 8)\n        return rtl8367c_getAsicRegBits(RTL8367C_FLOWCTRL_PORT_PAGE_MAX_REG(port), RTL8367C_FLOWCTRL_PORT_PAGE_MAX_MASK, pPageCount);\n    else\n        return rtl8367c_getAsicRegBits(RTL8367C_REG_FLOWCTRL_PORT0_PAGE_MAX+port-8, RTL8367C_FLOWCTRL_PORT_PAGE_MAX_MASK, pPageCount);\n\n\n}\n\n/* Function Name:\n *      rtl8367c_setAsicFlowControlEgressPortIndep\n * Description:\n *      Set per-port egress flow control independent\n * Input:\n *      port        - Physical port number (0~7)\n *      enabled     - Egress port flow control usage 1:enable 0:disable.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n *      RT_ERR_PORT_ID  - Invalid port number\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicFlowControlEgressPortIndep(rtk_uint32 port, rtk_uint32 enable)\n{\n    if(port > RTL8367C_PORTIDMAX)\n        return RT_ERR_PORT_ID;\n\n    return rtl8367c_setAsicRegBit(RTL8367C_REG_PORT0_MISC_CFG + (port *0x20), RTL8367C_PORT0_MISC_CFG_FLOWCTRL_INDEP_OFFSET,enable);\n}\n\n/* Function Name:\n *      rtl8367c_getAsicFlowControlEgressPortIndep\n * Description:\n *      Get per-port egress flow control independent\n * Input:\n *      port        - Physical port number (0~7)\n *      enabled     - Egress port flow control usage 1:enable 0:disable.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n *      RT_ERR_PORT_ID  - Invalid port number\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicFlowControlEgressPortIndep(rtk_uint32 port, rtk_uint32 *pEnable)\n{\n    return rtl8367c_getAsicRegBit(RTL8367C_REG_PORT0_MISC_CFG + (port *0x20),RTL8367C_PORT0_MISC_CFG_FLOWCTRL_INDEP_OFFSET,pEnable);\n}\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_green.c",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * $Revision: 76306 $\n * $Date: 2017-03-08 15:13:58 +0800 (週三, 08 三月 2017) $\n *\n * Purpose : RTL8367C switch high-level API for RTL8367C\n * Feature : Green ethernet related functions\n *\n */\n#include <rtl8367c_asicdrv_green.h>\n\n/* Function Name:\n *      rtl8367c_getAsicGreenPortPage\n * Description:\n *      Get per-Port ingress page usage per second\n * Input:\n *      port    - Physical port number (0~7)\n *      pPage   - page number of ingress packet occuping per second\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n *      RT_ERR_PORT_ID  - Invalid port number\n * Note:\n *      Ingress traffic occuping page number per second for high layer green feature usage\n */\nret_t rtl8367c_getAsicGreenPortPage(rtk_uint32 port, rtk_uint32* pPage)\n{\n    ret_t retVal;\n    rtk_uint32 regData;\n    rtk_uint32 pageMeter;\n\n    if(port > RTL8367C_PORTIDMAX)\n        return RT_ERR_PORT_ID;\n\n    retVal = rtl8367c_getAsicReg(RTL8367C_PAGEMETER_PORT_REG(port), &regData);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n   pageMeter = regData;\n\n    retVal = rtl8367c_getAsicReg(RTL8367C_PAGEMETER_PORT_REG(port) + 1, &regData);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    pageMeter = pageMeter + (regData << 16);\n\n    *pPage = pageMeter;\n    return RT_ERR_OK;\n}\n/* Function Name:\n *      rtl8367c_setAsicGreenTrafficType\n * Description:\n *      Set traffic type for each priority\n * Input:\n *      priority    - internal priority (0~7)\n *      traffictype - high/low traffic type, 1:high priority traffic type, 0:low priority traffic type\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - Success\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_QOS_INT_PRIORITY - Invalid priority\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicGreenTrafficType(rtk_uint32 priority, rtk_uint32 traffictype)\n{\n\n    if(priority > RTL8367C_PRIMAX)\n        return RT_ERR_QOS_INT_PRIORITY;\n\n    return rtl8367c_setAsicRegBit(RTL8367C_REG_HIGHPRI_CFG, priority, (traffictype?1:0));\n}\n/* Function Name:\n *      rtl8367c_getAsicGreenTrafficType\n * Description:\n *      Get traffic type for each priority\n * Input:\n *      priority    - internal priority (0~7)\n *      pTraffictype - high/low traffic type, 1:high priority traffic type, 0:low priority traffic type\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - Success\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_QOS_INT_PRIORITY - Invalid priority\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicGreenTrafficType(rtk_uint32 priority, rtk_uint32* pTraffictype)\n{\n    if(priority > RTL8367C_PRIMAX)\n        return RT_ERR_QOS_INT_PRIORITY;\n\n    return rtl8367c_getAsicRegBit(RTL8367C_REG_HIGHPRI_CFG, priority, pTraffictype);\n}\n\n/* Function Name:\n *      rtl8367c_setAsicGreenHighPriorityTraffic\n * Description:\n *      Set indicator which ASIC had received high priority traffic\n * Input:\n *      port            - Physical port number (0~7)\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n *      RT_ERR_PORT_ID  - Invalid port number\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicGreenHighPriorityTraffic(rtk_uint32 port)\n{\n    if(port > RTL8367C_PORTIDMAX)\n        return RT_ERR_PORT_ID;\n\n    return rtl8367c_setAsicRegBit(RTL8367C_REG_HIGHPRI_INDICATOR, port, 1);\n}\n\n\n/* Function Name:\n *      rtl8367c_getAsicGreenHighPriorityTraffic\n * Description:\n *      Get indicator which ASIC had received high priority traffic or not\n * Input:\n *      port        - Physical port number (0~7)\n *      pIndicator  - Have received high priority traffic indicator. If 1 means ASCI had received high priority in 1second checking priod\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n *      RT_ERR_PORT_ID  - Invalid port number\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicGreenHighPriorityTraffic(rtk_uint32 port, rtk_uint32* pIndicator)\n{\n    if(port > RTL8367C_PORTIDMAX)\n        return RT_ERR_PORT_ID;\n\n    return rtl8367c_getAsicRegBit(RTL8367C_REG_HIGHPRI_INDICATOR, port, pIndicator);\n}\n\n/*\n@func rtk_int32 | rtl8367c_setAsicGreenEthernet | Set green ethernet function.\n@parm rtk_uint32 | green | Green feature function usage 1:enable 0:disable.\n@rvalue RT_ERR_OK | Success.\n@rvalue RT_ERR_SMI | SMI access error.\n@comm\n    The API can set Green Ethernet function to reduce power consumption. While green feature is enabled, ASIC will automatic\n detect the cable length and then select different power mode for best performance with minimums power consumption. Link down\n ports will enter power savining mode in 10 seconds after the cable disconnected if power saving function is enabled.\n*/\nret_t rtl8367c_setAsicGreenEthernet(rtk_uint32 port, rtk_uint32 green)\n{\n    ret_t retVal;\n    rtk_uint32 checkCounter;\n    rtk_uint32 regData;\n    rtk_uint32 phy_status;\n    rtk_uint32 patchData[6][2] = { {0x809A, 0x8911}, {0x80A3, 0x9233}, {0x80AC, 0xA444}, {0x809F, 0x6B20}, {0x80A8, 0x6B22}, {0x80B1, 0x6B23} };\n    rtk_uint32 idx;\n    rtk_uint32 data;\n\n    if (green > 1)\n        return RT_ERR_INPUT;\n\n    /* 0xa420[2:0] */\n    if((retVal = rtl8367c_getAsicPHYOCPReg(port, 0xA420, &regData)) != RT_ERR_OK)\n        return retVal;\n    phy_status = (regData & 0x0007);\n\n    if(phy_status == 3)\n    {\n        /* 0xb820[4] = 1 */\n        if((retVal = rtl8367c_getAsicPHYOCPReg(port, 0xB820, &regData)) != RT_ERR_OK)\n            return retVal;\n\n        regData |= (0x0001 << 4);\n\n        if((retVal = rtl8367c_setAsicPHYOCPReg(port, 0xB820, regData)) != RT_ERR_OK)\n            return retVal;\n\n        /* wait 0xb800[6] = 1 */\n        checkCounter = 100;\n        while(checkCounter)\n        {\n            retVal = rtl8367c_getAsicPHYOCPReg(port, 0xB800, &regData);\n            if( (retVal != RT_ERR_OK) || ((regData & 0x0040) != 0x0040) )\n            {\n                checkCounter --;\n                if(0 == checkCounter)\n                    return RT_ERR_BUSYWAIT_TIMEOUT;\n            }\n            else\n                checkCounter = 0;\n        }\n    }\n\n    if((retVal = rtl8367c_setAsicReg(0x13C2, 0x0249)) != RT_ERR_OK)\n        return retVal;\n\n    if((retVal = rtl8367c_getAsicReg(0x1300, &data)) != RT_ERR_OK)\n        return retVal;\n\n    if((retVal = rtl8367c_setAsicReg(0x13C2, 0x0000)) != RT_ERR_OK)\n        return retVal;\n\n    switch (data)\n    {\n        case 0x0276:\n        case 0x0597:\n        case 0x6367:\n            if(green)\n            {\n                for(idx = 0; idx < 6; idx++ )\n                {\n                    if((retVal = rtl8367c_setAsicPHYOCPReg(port, 0xA436, patchData[idx][0])) != RT_ERR_OK)\n                        return retVal;\n\n                    if((retVal = rtl8367c_setAsicPHYOCPReg(port, 0xA438, patchData[idx][1])) != RT_ERR_OK)\n                        return retVal;\n                }\n            }\n            break;\n        default:\n            break;;\n    }\n\n\n\n    /* 0xa436 = 0x8011 */\n    if((retVal = rtl8367c_setAsicPHYOCPReg(port, 0xA436, 0x8011)) != RT_ERR_OK)\n        return retVal;\n\n    /* wr 0xa438[15] = 0: disable, 1: enable */\n    if((retVal = rtl8367c_getAsicPHYOCPReg(port, 0xA438, &regData)) != RT_ERR_OK)\n        return retVal;\n\n    if(green)\n        regData |= 0x8000;\n    else\n        regData &= 0x7FFF;\n\n    if((retVal = rtl8367c_setAsicPHYOCPReg(port, 0xA438, regData)) != RT_ERR_OK)\n        return retVal;\n\n    if(phy_status == 3)\n    {\n        /* 0xb820[4] = 0  */\n        if((retVal = rtl8367c_getAsicPHYOCPReg(port, 0xB820, &regData)) != RT_ERR_OK)\n            return retVal;\n\n        regData &= ~(0x0001 << 4);\n\n        if((retVal = rtl8367c_setAsicPHYOCPReg(port, 0xB820, regData)) != RT_ERR_OK)\n            return retVal;\n\n        /* wait 0xb800[6] = 0 */\n        checkCounter = 100;\n        while(checkCounter)\n        {\n            retVal = rtl8367c_getAsicPHYOCPReg(port, 0xB800, &regData);\n            if( (retVal != RT_ERR_OK) || ((regData & 0x0040) != 0x0000) )\n            {\n                checkCounter --;\n                if(0 == checkCounter)\n                    return RT_ERR_BUSYWAIT_TIMEOUT;\n            }\n            else\n                checkCounter = 0;\n        }\n    }\n\n    return RT_ERR_OK;\n}\n\n/*\n@func rtk_int32 | rtl8367c_getAsicGreenEthernet | Get green ethernet function.\n@parm rtk_uint32 | *green | Green feature function usage 1:enable 0:disable.\n@rvalue RT_ERR_OK | Success.\n@rvalue RT_ERR_SMI | SMI access error.\n@comm\n    The API can set Green Ethernet function to reduce power consumption. While green feature is enabled, ASIC will automatic\n detect the cable length and then select different power mode for best performance with minimums power consumption. Link down\n ports will enter power savining mode in 10 seconds after the cable disconnected if power saving function is enabled.\n*/\nret_t rtl8367c_getAsicGreenEthernet(rtk_uint32 port, rtk_uint32* green)\n{\n    ret_t retVal;\n    rtk_uint32 regData;\n\n    /* 0xa436 = 0x8011 */\n    if((retVal = rtl8367c_setAsicPHYOCPReg(port, 0xA436, 0x8011)) != RT_ERR_OK)\n        return retVal;\n\n    /* wr 0xa438[15] = 0: disable, 1: enable */\n    if((retVal = rtl8367c_getAsicPHYOCPReg(port, 0xA438, &regData)) != RT_ERR_OK)\n        return retVal;\n\n    if(regData & 0x8000)\n        *green = ENABLED;\n    else\n        *green = DISABLED;\n\n    return RT_ERR_OK;\n}\n\n\n/*\n@func ret_t | rtl8367c_setAsicPowerSaving | Set power saving mode\n@parm rtk_uint32 | phy | phy number\n@parm rtk_uint32 | enable | enable power saving mode.\n@rvalue RT_ERR_OK | Success.\n@rvalue RT_ERR_SMI | SMI access error.\n@rvalue RT_ERR_PORT_ID | Invalid port number.\n@comm\n    The API can set power saving mode per phy.\n*/\nret_t rtl8367c_setAsicPowerSaving(rtk_uint32 phy, rtk_uint32 enable)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32 phyData;\n    rtk_uint32 regData;\n    rtk_uint32 phy_status;\n    rtk_uint32 checkCounter;\n\n    if (enable > 1)\n        return RT_ERR_INPUT;\n\n    /* 0xa420[2:0] */\n    if((retVal = rtl8367c_getAsicPHYOCPReg(phy, 0xA420, &regData)) != RT_ERR_OK)\n        return retVal;\n\n    phy_status = (regData & 0x0007);\n\n    if(phy_status == 3)\n    {\n        /* 0xb820[4] = 1 */\n        if((retVal = rtl8367c_getAsicPHYOCPReg(phy, 0xB820, &regData)) != RT_ERR_OK)\n            return retVal;\n\n        regData |= (0x0001 << 4);\n\n        if((retVal = rtl8367c_setAsicPHYOCPReg(phy, 0xB820, regData)) != RT_ERR_OK)\n            return retVal;\n\n        /* wait 0xb800[6] = 1 */\n        checkCounter = 100;\n        while(checkCounter)\n        {\n            retVal = rtl8367c_getAsicPHYOCPReg(phy, 0xB800, &regData);\n            if( (retVal != RT_ERR_OK) || ((regData & 0x0040) != 0x0040) )\n            {\n                checkCounter --;\n                if(0 == checkCounter)\n                {\n                     return RT_ERR_BUSYWAIT_TIMEOUT;\n                }\n            }\n            else\n                checkCounter = 0;\n        }\n    }\n\n    if ((retVal = rtl8367c_getAsicPHYReg(phy,PHY_POWERSAVING_REG,&phyData))!=RT_ERR_OK)\n        return retVal;\n\n    phyData = phyData & ~(0x0001 << 2);\n    phyData = phyData | (enable << 2);\n\n    if ((retVal = rtl8367c_setAsicPHYReg(phy,PHY_POWERSAVING_REG,phyData))!=RT_ERR_OK)\n        return retVal;\n\n    if(phy_status == 3)\n    {\n        /* 0xb820[4] = 0  */\n        if((retVal = rtl8367c_getAsicPHYOCPReg(phy, 0xB820, &regData)) != RT_ERR_OK)\n            return retVal;\n\n        regData &= ~(0x0001 << 4);\n\n        if((retVal = rtl8367c_setAsicPHYOCPReg(phy, 0xB820, regData)) != RT_ERR_OK)\n            return retVal;\n\n        /* wait 0xb800[6] = 0 */\n        checkCounter = 100;\n        while(checkCounter)\n        {\n            retVal = rtl8367c_getAsicPHYOCPReg(phy, 0xB800, &regData);\n            if( (retVal != RT_ERR_OK) || ((regData & 0x0040) != 0x0000) )\n            {\n                checkCounter --;\n                if(0 == checkCounter)\n                {\n                    return RT_ERR_BUSYWAIT_TIMEOUT;\n                }\n            }\n            else\n                checkCounter = 0;\n        }\n    }\n\n    return RT_ERR_OK;\n}\n\n/*\n@func ret_t | rtl8367c_getAsicPowerSaving | Get power saving mode\n@parm rtk_uint32 | port | The port number\n@parm rtk_uint32* | enable | enable power saving mode.\n@rvalue RT_ERR_OK | Success.\n@rvalue RT_ERR_SMI | SMI access error.\n@rvalue RT_ERR_PORT_ID | Invalid port number.\n@comm\n    The API can get power saving mode per phy.\n*/\nret_t rtl8367c_getAsicPowerSaving(rtk_uint32 phy, rtk_uint32* enable)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32 phyData;\n\n    if(NULL == enable)\n        return RT_ERR_NULL_POINTER;\n\n    if ((retVal = rtl8367c_getAsicPHYReg(phy,PHY_POWERSAVING_REG,&phyData))!=RT_ERR_OK)\n        return retVal;\n\n    if ((phyData & 0x0004) > 0)\n        *enable = 1;\n    else\n        *enable = 0;\n\n    return RT_ERR_OK;\n}\n\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_hsb.c",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * $Revision: 76306 $\n * $Date: 2017-03-08 15:13:58 +0800 (週三, 08 三月 2017) $\n *\n * Purpose : RTL8367C switch high-level API for RTL8367C\n * Feature : Field selector related functions\n *\n */\n#include <rtl8367c_asicdrv_hsb.h>\n/* Function Name:\n *      rtl8367c_setAsicFieldSelector\n * Description:\n *      Set user defined field selectors in HSB\n * Input:\n *      index       - index of field selector 0-15\n *      format      - Format of field selector\n *      offset      - Retrieving data offset\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_OUT_OF_RANGE - input parameter out of range\n * Note:\n *      System support 16 user defined field selctors.\n *      Each selector can be enabled or disable. User can defined retrieving 16-bits in many predefiend\n *      standard l2/l3/l4 payload.\n */\nret_t rtl8367c_setAsicFieldSelector(rtk_uint32 index, rtk_uint32 format, rtk_uint32 offset)\n{\n    rtk_uint32 regData;\n\n    if(index > RTL8367C_FIELDSEL_FORMAT_NUMBER)\n        return RT_ERR_OUT_OF_RANGE;\n\n    if(format >= FIELDSEL_FORMAT_END)\n        return RT_ERR_OUT_OF_RANGE;\n\n    regData = (((format << RTL8367C_FIELD_SELECTOR_FORMAT_OFFSET) & RTL8367C_FIELD_SELECTOR_FORMAT_MASK ) |\n               ((offset << RTL8367C_FIELD_SELECTOR_OFFSET_OFFSET) & RTL8367C_FIELD_SELECTOR_OFFSET_MASK ));\n\n    return rtl8367c_setAsicReg(RTL8367C_FIELD_SELECTOR_REG(index), regData);\n}\n/* Function Name:\n *      rtl8367c_getAsicFieldSelector\n * Description:\n *      Get user defined field selectors in HSB\n * Input:\n *      index       - index of field selector 0-15\n *      pFormat     - Format of field selector\n *      pOffset     - Retrieving data offset\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicFieldSelector(rtk_uint32 index, rtk_uint32* pFormat, rtk_uint32* pOffset)\n{\n    ret_t retVal;\n    rtk_uint32 regData;\n\n    retVal = rtl8367c_getAsicReg(RTL8367C_FIELD_SELECTOR_REG(index), &regData);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    *pFormat    = ((regData & RTL8367C_FIELD_SELECTOR_FORMAT_MASK) >> RTL8367C_FIELD_SELECTOR_FORMAT_OFFSET);\n    *pOffset    = ((regData & RTL8367C_FIELD_SELECTOR_OFFSET_MASK) >> RTL8367C_FIELD_SELECTOR_OFFSET_OFFSET);\n\n    return RT_ERR_OK;\n}\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_i2c.c",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * $Revision: 38651 $\n * $Date: 2016-02-27 14:32:56 +0800 (周三, 17 四月 2016) $\n *\n * Purpose : RTL8367C switch high-level API for RTL8367C\n * Feature : I2C related functions\n *\n */\n\n\n#include <rtl8367c_asicdrv_i2c.h>\n#include <rtk_error.h>\n#include <rtk_types.h>\n\n\n\n/* Function Name:\n *      rtl8367c_setAsicI2C_checkBusIdle\n * Description:\n *      Check i2c bus status idle or not\n * Input:\n *      None\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK                - Success\n *      RT_ERR_BUSYWAIT_TIMEOUT  - i2c bus is busy\n * Note:\n *      This API can check i2c bus status.\n */\nret_t rtl8367c_setAsicI2C_checkBusIdle(void)\n{\n    rtk_uint32 regData;\n    ret_t retVal;\n\n    if ((retVal = rtl8367c_getAsicRegBit(RTL8367C_REG_M_I2C_CTL_STA_REG, RTL8367C_M_I2C_BUS_IDLE_OFFSET, &regData)) != RT_ERR_OK)\n        return retVal;\n\n    if(regData == 0x0001)\n        return RT_ERR_OK; /*i2c is idle*/\n    else\n        return RT_ERR_BUSYWAIT_TIMEOUT; /*i2c is busy*/\n}\n\n\n/* Function Name:\n *      rtl8367c_setAsicI2CStartCmd\n * Description:\n *      Set I2C start command\n * Input:\n *      None\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK                - Success\n * Note:\n *      This API can set i2c start command ,start a i2c traffic  .\n */\nret_t rtl8367c_setAsicI2CStartCmd(void)\n{\n    rtk_uint32 regData;\n    ret_t retVal;\n\n    /* Bits [4-1] = 0b0000, Start Command; Bit [0] = 1, Trigger the Command */\n    if ((retVal = rtl8367c_getAsicReg(RTL8367C_REG_M_I2C_CTL_STA_REG, &regData)) != RT_ERR_OK)\n        return retVal;\n    regData &= 0xFFE0;\n    regData |= 0x0001;\n\n    if ((retVal = rtl8367c_setAsicReg(RTL8367C_REG_M_I2C_CTL_STA_REG, regData)) != RT_ERR_OK)\n        return retVal;\n\n    /* wait for command finished */\n    do{\n       if ((retVal = rtl8367c_getAsicRegBit(RTL8367C_REG_M_I2C_CTL_STA_REG, RTL8367C_I2C_CMD_EXEC_OFFSET, &regData)) != RT_ERR_OK)\n            return retVal;\n    }while( regData != 0x0);\n\n    return RT_ERR_OK ;\n}\n\n/* Function Name:\n *      rtl8367c_setAsicI2CStopCmd\n * Description:\n *      Set I2C stop command\n * Input:\n *      None\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK                - Success\n * Note:\n *      This API can set i2c stop command ,stop a i2c traffic.\n */\nret_t rtl8367c_setAsicI2CStopCmd(void)\n{\n\n    rtk_uint32 regData;\n    ret_t retVal;\n\n    /* Bits [4-1] = 0b0001, Stop Command; Bit [0] = 1, Trigger the Command */\n    if ((retVal = rtl8367c_getAsicReg(RTL8367C_REG_M_I2C_CTL_STA_REG, &regData)) != RT_ERR_OK)\n        return retVal;\n    regData &= 0xFFE0;\n    regData |= 0x0003;\n\n    if ((retVal = rtl8367c_setAsicReg(RTL8367C_REG_M_I2C_CTL_STA_REG, regData)) != RT_ERR_OK)\n        return retVal;\n\n\n    /* wait for command finished */\n    do{\n       if ((retVal = rtl8367c_getAsicRegBit(RTL8367C_REG_M_I2C_CTL_STA_REG, RTL8367C_I2C_CMD_EXEC_OFFSET, &regData)) != RT_ERR_OK)\n            return retVal;\n    }while( regData != 0x0);\n\n    return RT_ERR_OK ;\n}\n\n/* Function Name:\n *      rtl8367c_setAsicI2CTxOneCharCmd\n * Description:\n *      Set I2C Tx a char command, with a 8-bit data\n * Input:\n *      oneChar - 8-bit data\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK                - Success\n * Note:\n *      This API can set i2c Tx command and with a 8-bit data.\n */\nret_t rtl8367c_setAsicI2CTxOneCharCmd(rtk_uint8 oneChar)\n{\n    rtk_uint32 regData;\n    ret_t retVal;\n\n    /* Bits [4-1] = 0b0010, tx one char; Bit [0] = 1, Trigger the Command */\n    if ((retVal = rtl8367c_getAsicReg(RTL8367C_REG_M_I2C_CTL_STA_REG, &regData)) != RT_ERR_OK)\n        return retVal;\n\n    regData &= 0xFFE0;\n    regData |= 0x0005;\n    regData &= 0x00FF;\n    regData |= (rtk_uint16) (oneChar << 8);\n\n    if ((retVal = rtl8367c_setAsicReg(RTL8367C_REG_M_I2C_CTL_STA_REG, regData)) != RT_ERR_OK)\n        return retVal;\n\n\n   /* wait for command finished */\n    do{\n       if ((retVal = rtl8367c_getAsicRegBit(RTL8367C_REG_M_I2C_CTL_STA_REG, RTL8367C_I2C_CMD_EXEC_OFFSET, &regData)) != RT_ERR_OK)\n            return retVal;\n    }while( regData != 0x0);\n\n    return RT_ERR_OK ;\n}\n\n\n/* Function Name:\n *      rtl8367c_setAsicI2CcheckRxAck\n * Description:\n *      Check if rx an Ack\n * Input:\n *      None\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK                - Success\n * Note:\n *      This API can check if rx an ack from i2c slave.\n */\nret_t rtl8367c_setAsicI2CcheckRxAck(void)\n{\n    rtk_uint32 regData;\n    ret_t retVal;\n    rtk_uint32 count = 0;\n\n    do{\n         count++;\n         if ((retVal = rtl8367c_getAsicRegBit(RTL8367C_REG_M_I2C_CTL_STA_REG, RTL8367C_SLV_ACK_FLAG_OFFSET, &regData)) != RT_ERR_OK)\n            return retVal;\n    }while( (regData != 0x1) && (count < TIMEROUT_FOR_MICROSEMI) );\n\n    if(regData != 0x1)\n        return RT_ERR_FAILED;\n    else\n        return RT_ERR_OK;\n}\n\n\n/* Function Name:\n *      rtl8367c_setAsicI2CRxOneCharCmd\n * Description:\n *      Set I2C Rx command and get 8-bit data\n * Input:\n *      None\n * Output:\n *      pValue - 8bit-data\n * Return:\n *      RT_ERR_OK                - Success\n * Note:\n *      This API can set I2C Rx command and get 8-bit data.\n */\nret_t rtl8367c_setAsicI2CRxOneCharCmd(rtk_uint8 *pValue)\n{\n    rtk_uint32 regData;\n    ret_t retVal;\n\n    /* Bits [4-1] = 0b0011, Rx one char; Bit [0] = 1, Trigger the Command */\n    if ((retVal = rtl8367c_getAsicReg(RTL8367C_REG_M_I2C_CTL_STA_REG, &regData)) != RT_ERR_OK)\n        return retVal;\n    regData &= 0xFFE0;\n    regData |= 0x0007;\n    if ((retVal = rtl8367c_setAsicReg(RTL8367C_REG_M_I2C_CTL_STA_REG, regData)) != RT_ERR_OK)\n        return retVal;\n\n    /* wait for command finished */\n     do{\n        if ((retVal = rtl8367c_getAsicReg(RTL8367C_REG_M_I2C_CTL_STA_REG, &regData)) != RT_ERR_OK)\n             return retVal;\n     }while( (regData & 0x1) != 0x0);\n\n    *pValue = (rtk_uint8)(regData >> 8);\n     return RT_ERR_OK ;\n\n}\n\n/* Function Name:\n *      rtl8367c_setAsicI2CTxAckCmd\n * Description:\n *      Set I2C Tx ACK command\n * Input:\n *      None\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK                - Success\n * Note:\n *      This API can set I2C Tx ack command.\n */\nret_t rtl8367c_setAsicI2CTxAckCmd(void)\n{\n    rtk_uint32 regData;\n    ret_t retVal;\n\n    /* Bits [4-1] = 0b0100, tx ACK Command; Bit [0] = 1, Trigger the Command */\n    if ((retVal = rtl8367c_getAsicReg(RTL8367C_REG_M_I2C_CTL_STA_REG, &regData)) != RT_ERR_OK)\n        return retVal;\n    regData &= 0xFFE0;\n    regData |= 0x0009;\n    if ((retVal = rtl8367c_setAsicReg(RTL8367C_REG_M_I2C_CTL_STA_REG, regData)) != RT_ERR_OK)\n        return retVal;\n\n     /* wait for command finished */\n    do{\n       if ((retVal = rtl8367c_getAsicRegBit(RTL8367C_REG_M_I2C_CTL_STA_REG, RTL8367C_I2C_CMD_EXEC_OFFSET, &regData)) != RT_ERR_OK)\n            return retVal;\n    }while( regData != 0x0);\n\n    return RT_ERR_OK ;\n\n}\n\n\n/* Function Name:\n *      rtl8367c_setAsicI2CTxNoAckCmd\n * Description:\n *      Set I2C master Tx noACK command\n * Input:\n *      None\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK                - Success\n * Note:\n *      This API can set I2C master Tx noACK command.\n */\nret_t rtl8367c_setAsicI2CTxNoAckCmd(void)\n{\n    rtk_uint32 regData;\n    ret_t retVal;\n\n    /* Bits [4-1] = 0b0101, tx noACK Command; Bit [0] = 1, Trigger the Command */\n    if ((retVal = rtl8367c_getAsicReg(RTL8367C_REG_M_I2C_CTL_STA_REG, &regData)) != RT_ERR_OK)\n        return retVal;\n    regData &= 0xFFE0;\n    regData |= 0x000b;\n    if ((retVal = rtl8367c_setAsicReg(RTL8367C_REG_M_I2C_CTL_STA_REG, regData)) != RT_ERR_OK)\n        return retVal;\n\n     /* wait for command finished */\n    do{\n       if ((retVal = rtl8367c_getAsicRegBit(RTL8367C_REG_M_I2C_CTL_STA_REG, RTL8367C_I2C_CMD_EXEC_OFFSET, &regData)) != RT_ERR_OK)\n            return retVal;\n    }while( regData != 0x0);\n\n    return RT_ERR_OK ;\n\n}\n\n/* Function Name:\n *      rtl8367c_setAsicI2CSoftRSTseqCmd\n * Description:\n *      set I2C master tx soft reset command\n * Input:\n *      None\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK                - Success\n * Note:\n *      This API can set I2C master tx soft reset command.\n */\nret_t rtl8367c_setAsicI2CSoftRSTseqCmd(void)\n{\n\n    rtk_uint32 regData;\n    ret_t retVal;\n\n    /*Bits [4-1] = 0b0110, tx soft reset Command;  Bit [0] = 1, Trigger the Command */\n    if ((retVal = rtl8367c_getAsicReg(RTL8367C_REG_M_I2C_CTL_STA_REG, &regData)) != RT_ERR_OK)\n        return retVal;\n    regData &= 0xFFE0;\n    regData |= 0x000d;\n\n    if ((retVal = rtl8367c_setAsicReg(RTL8367C_REG_M_I2C_CTL_STA_REG, regData)) != RT_ERR_OK)\n        return retVal;\n\n\n    /* wait for command finished */\n    do{\n       if ((retVal = rtl8367c_getAsicRegBit(RTL8367C_REG_M_I2C_CTL_STA_REG, RTL8367C_I2C_CMD_EXEC_OFFSET, &regData)) != RT_ERR_OK)\n            return retVal;\n    }while( regData != 0x0);\n\n    return RT_ERR_OK ;\n}\n\n\n/* Function Name:\n *      rtl8367c_setAsicI2CGpioPinGroup\n * Description:\n *      set I2C function used gpio pins\n * Input:\n *      pinGroup_ID - gpio pins group\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK                - Success\n *      RT_ERR_INPUT             _ Invalid input parameter\n * Note:\n *      This API can set I2C function used gpio pins.\n *      There are three group gpio pins\n */\nret_t rtl8367c_setAsicI2CGpioPinGroup(rtk_uint32 pinGroup_ID)\n{\n    rtk_uint32 regData;\n    ret_t retVal;\n\n    if ((retVal = rtl8367c_getAsicReg(RTL8367C_REG_M_I2C_SYS_CTL, &regData)) != RT_ERR_OK)\n         return retVal;\n    if( pinGroup_ID==0 )\n    {\n        regData &= 0x0FFF;\n        regData |= 0x5000;\n\n        if ((retVal = rtl8367c_setAsicReg(RTL8367C_REG_M_I2C_SYS_CTL, regData)) != RT_ERR_OK)\n             return retVal;\n    }\n\n    else if( pinGroup_ID==1 )\n    {\n        regData &= 0x0FFF;\n        regData |= 0xA000;\n\n        if ((retVal = rtl8367c_setAsicReg(RTL8367C_REG_M_I2C_SYS_CTL, regData)) != RT_ERR_OK)\n             return retVal;\n    }\n\n    else if( pinGroup_ID==2 )\n    {\n        regData &= 0x0FFF;\n        regData |= 0xF000;\n\n        if ((retVal = rtl8367c_setAsicReg(RTL8367C_REG_M_I2C_SYS_CTL, regData)) != RT_ERR_OK)\n             return retVal;\n    }\n    else\n        return RT_ERR_INPUT;\n\n    return RT_ERR_OK ;\n\n}\n\n/* Function Name:\n *      rtl8367c_setAsicI2CGpioPinGroup\n * Description:\n *      set I2C function used gpio pins\n * Input:\n *      pinGroup_ID - gpio pins group\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK                - Success\n *      RT_ERR_INPUT             _ Invalid input parameter\n * Note:\n *      This API can set I2C function used gpio pins.\n *      There are three group gpio pins\n */\nret_t rtl8367c_getAsicI2CGpioPinGroup(rtk_uint32 * pPinGroup_ID)\n{\n\n    rtk_uint32 regData;\n    ret_t retVal;\n    if( (retVal = rtl8367c_getAsicReg(RTL8367C_REG_M_I2C_SYS_CTL, &regData)) != RT_ERR_OK)\n        return retVal;\n    regData &= 0xF000 ;\n    regData = (regData >> 12);\n\n    if( regData == 0x5 )\n        *pPinGroup_ID = 0;\n    else if(regData == 0xA)\n        *pPinGroup_ID = 1;\n    else if(regData == 0xF)\n        *pPinGroup_ID = 2;\n    else\n       return RT_ERR_FAILED;\n    return RT_ERR_OK ;\n}\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_igmp.c",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * $Revision: 76306 $\n * $Date: 2017-03-08 15:13:58 +0800 (週三, 08 三月 2017) $\n *\n * Purpose : RTL8367C switch high-level API for RTL8367C\n * Feature : IGMP related functions\n *\n */\n#include <rtl8367c_asicdrv_igmp.h>\n/* Function Name:\n *      rtl8367c_setAsicIgmp\n * Description:\n *      Set IGMP/MLD state\n * Input:\n *      enabled     - 1: enabled, 0: disabled\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicIgmp(rtk_uint32 enabled)\n{\n    ret_t retVal;\n\n    /* Enable/Disable H/W IGMP/MLD */\n    retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_IGMP_MLD_CFG0, RTL8367C_IGMP_MLD_EN_OFFSET, enabled);\n\n    return retVal;\n}\n/* Function Name:\n *      rtl8367c_getAsicIgmp\n * Description:\n *      Get IGMP/MLD state\n * Input:\n *      enabled     - 1: enabled, 0: disabled\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicIgmp(rtk_uint32 *ptr_enabled)\n{\n    ret_t retVal;\n\n    retVal = rtl8367c_getAsicRegBit(RTL8367C_REG_IGMP_MLD_CFG0, RTL8367C_IGMP_MLD_EN_OFFSET, ptr_enabled);\n    return retVal;\n}\n/* Function Name:\n *      rtl8367c_setAsicIpMulticastVlanLeaky\n * Description:\n *      Set IP multicast VLAN Leaky function\n * Input:\n *      port        - Physical port number (0~7)\n *      enabled     - 1: enabled, 0: disabled\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n *      RT_ERR_PORT_ID  - Invalid port number\n * Note:\n *      When enabling this function,\n *      if the lookup result(forwarding portmap) of IP Multicast packet is over VLAN boundary,\n *      the packet can be forwarded across VLAN\n */\nret_t rtl8367c_setAsicIpMulticastVlanLeaky(rtk_uint32 port, rtk_uint32 enabled)\n{\n    ret_t  retVal;\n\n    if(port > RTL8367C_PORTIDMAX)\n        return RT_ERR_PORT_ID;\n\n    retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_IPMCAST_VLAN_LEAKY, port, enabled);\n\n    return retVal;\n}\n/* Function Name:\n *      rtl8367c_getAsicIpMulticastVlanLeaky\n * Description:\n *      Get IP multicast VLAN Leaky function\n * Input:\n *      port        - Physical port number (0~7)\n *      enabled     - 1: enabled, 0: disabled\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n *      RT_ERR_PORT_ID  - Invalid port number\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicIpMulticastVlanLeaky(rtk_uint32 port, rtk_uint32 *ptr_enabled)\n{\n    ret_t  retVal;\n\n    if(port > RTL8367C_PORTIDMAX)\n        return RT_ERR_PORT_ID;\n\n    retVal = rtl8367c_getAsicRegBit(RTL8367C_REG_IPMCAST_VLAN_LEAKY, port, ptr_enabled);\n\n    return retVal;\n}\n\n/* Function Name:\n *      rtl8367c_setAsicIGMPTableFullOP\n * Description:\n *      Set Table Full operation\n * Input:\n *      operation   - The operation should be taken when the IGMP table is full.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_OUT_OF_RANGE - input parameter is out of range\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicIGMPTableFullOP(rtk_uint32 operation)\n{\n    ret_t  retVal;\n\n    if(operation >= TABLE_FULL_OP_END)\n        return RT_ERR_OUT_OF_RANGE;\n\n    /* Table full Operation */\n    retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_IGMP_MLD_CFG1, RTL8367C_TABLE_FULL_OP_MASK, operation);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtl8367c_getAsicIGMPTableFullOP\n * Description:\n *      Get Table Full operation\n * Input:\n *      None\n * Output:\n *      poperation  - The operation should be taken when the IGMP table is full.\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicIGMPTableFullOP(rtk_uint32 *poperation)\n{\n    ret_t   retVal;\n    rtk_uint32  value;\n\n    /* Table full Operation */\n    retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_IGMP_MLD_CFG1, RTL8367C_TABLE_FULL_OP_MASK, &value);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    *poperation = value;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtl8367c_setAsicIGMPCRCErrOP\n * Description:\n *      Set the operation when ASIC receive a Checksum error packet\n * Input:\n *      operation   -The operation when ASIC receive a Checksum error packet\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_OUT_OF_RANGE - input parameter is out of range\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicIGMPCRCErrOP(rtk_uint32 operation)\n{\n    ret_t  retVal;\n\n    if(operation >= CRC_ERR_OP_END)\n        return RT_ERR_OUT_OF_RANGE;\n\n    /* CRC Error Operation */\n    retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_IGMP_MLD_CFG0, RTL8367C_CKS_ERR_OP_MASK, operation);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtl8367c_getAsicIGMPCRCErrOP\n * Description:\n *      Get the operation when ASIC receive a Checksum error packet\n * Input:\n *      None\n * Output:\n *      poperation  - The operation of Checksum error packet\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicIGMPCRCErrOP(rtk_uint32 *poperation)\n{\n    ret_t   retVal;\n    rtk_uint32  value;\n\n    /* CRC Error Operation */\n    retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_IGMP_MLD_CFG0, RTL8367C_CKS_ERR_OP_MASK, &value);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    *poperation = value;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtl8367c_setAsicIGMPFastLeaveEn\n * Description:\n *      Enable/Disable Fast Leave\n * Input:\n *      enabled - 1:enable Fast Leave; 0:disable Fast Leave\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicIGMPFastLeaveEn(rtk_uint32 enabled)\n{\n    ret_t  retVal;\n\n    /* Fast Leave */\n    retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_IGMP_MLD_CFG0, RTL8367C_FAST_LEAVE_EN_MASK, (enabled >= 1) ? 1 : 0);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtl8367c_getAsicIGMPFastLeaveEn\n * Description:\n *      Get Fast Leave state\n * Input:\n *      None\n * Output:\n *      penabled        - 1:enable Fast Leave; 0:disable Fast Leave\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicIGMPFastLeaveEn(rtk_uint32 *penabled)\n{\n    ret_t   retVal;\n    rtk_uint32  value;\n\n    /* Fast Leave */\n    retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_IGMP_MLD_CFG0, RTL8367C_FAST_LEAVE_EN_MASK, &value);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    *penabled = value;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtl8367c_setAsicIGMPLeaveTimer\n * Description:\n *      Set the Leave timer of IGMP/MLD\n * Input:\n *      leave_timer     - Leave timer\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_OUT_OF_RANGE - input parameter is out of range\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicIGMPLeaveTimer(rtk_uint32 leave_timer)\n{\n    ret_t  retVal;\n\n    if(leave_timer > RTL8367C_MAX_LEAVE_TIMER)\n        return RT_ERR_OUT_OF_RANGE;\n\n    /* Leave timer */\n    retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_IGMP_MLD_CFG0, RTL8367C_LEAVE_TIMER_MASK, leave_timer);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtl8367c_getAsicIGMPLeaveTimer\n * Description:\n *      Get the Leave timer of IGMP/MLD\n * Input:\n *      None\n * Output:\n *      pleave_timer    - Leave timer\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicIGMPLeaveTimer(rtk_uint32 *pleave_timer)\n{\n    ret_t   retVal;\n    rtk_uint32  value;\n\n    /* Leave timer */\n    retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_IGMP_MLD_CFG0, RTL8367C_LEAVE_TIMER_MASK, &value);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    *pleave_timer = value;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtl8367c_setAsicIGMPQueryInterval\n * Description:\n *      Set Query Interval of IGMP/MLD\n * Input:\n *      interval    - Query Interval\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_OUT_OF_RANGE - input parameter is out of range\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicIGMPQueryInterval(rtk_uint32 interval)\n{\n    ret_t  retVal;\n\n    if(interval > RTL8367C_MAX_QUERY_INT)\n        return RT_ERR_OUT_OF_RANGE;\n\n    /* Query Interval */\n    retVal = rtl8367c_setAsicReg(RTL8367C_REG_IGMP_MLD_CFG2, interval);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtl8367c_getAsicIGMPQueryInterval\n * Description:\n *      Get Query Interval of IGMP/MLD\n * Input:\n *      None\n * Output:\n *      pinterval       - Query Interval\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicIGMPQueryInterval(rtk_uint32 *pinterval)\n{\n    ret_t   retVal;\n    rtk_uint32  value;\n\n    /* Query Interval */\n    retVal = rtl8367c_getAsicReg(RTL8367C_REG_IGMP_MLD_CFG2, &value);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    *pinterval = value;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtl8367c_setAsicIGMPRobVar\n * Description:\n *      Set Robustness Variable of IGMP/MLD\n * Input:\n *      rob_var     - Robustness Variable\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_OUT_OF_RANGE - input parameter is out of range\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicIGMPRobVar(rtk_uint32 rob_var)\n{\n    ret_t  retVal;\n\n    if(rob_var > RTL8367C_MAX_ROB_VAR)\n        return RT_ERR_OUT_OF_RANGE;\n\n    /* Bourstness variable */\n    retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_IGMP_MLD_CFG0, RTL8367C_ROBURSTNESS_VAR_MASK, rob_var);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtl8367c_getAsicIGMPRobVar\n * Description:\n *      Get Robustness Variable of IGMP/MLD\n * Input:\n *      none\n * Output:\n *      prob_var     - Robustness Variable\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicIGMPRobVar(rtk_uint32 *prob_var)\n{\n    ret_t   retVal;\n    rtk_uint32  value;\n\n    /* Bourstness variable */\n    retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_IGMP_MLD_CFG0, RTL8367C_ROBURSTNESS_VAR_MASK, &value);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    *prob_var = value;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtl8367c_setAsicIGMPStaticRouterPort\n * Description:\n *      Set IGMP static router port mask\n * Input:\n *      pmsk    - Static portmask\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_MASK    - Invalid port mask\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicIGMPStaticRouterPort(rtk_uint32 pmsk)\n{\n    if(pmsk > RTL8367C_PORTMASK)\n        return RT_ERR_PORT_MASK;\n\n    return rtl8367c_setAsicRegBits(RTL8367C_REG_IGMP_STATIC_ROUTER_PORT, RTL8367C_IGMP_STATIC_ROUTER_PORT_MASK, pmsk);\n}\n\n/* Function Name:\n *      rtl8367c_getAsicIGMPStaticRouterPort\n * Description:\n *      Get IGMP static router port mask\n * Input:\n *      pmsk    - Static portmask\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicIGMPStaticRouterPort(rtk_uint32 *pmsk)\n{\n    return rtl8367c_getAsicRegBits(RTL8367C_REG_IGMP_STATIC_ROUTER_PORT, RTL8367C_IGMP_STATIC_ROUTER_PORT_MASK, pmsk);\n}\n\n/* Function Name:\n *      rtl8367c_setAsicIGMPAllowDynamicRouterPort\n * Description:\n *      Set IGMP dynamic router port allow mask\n * Input:\n *      pmsk    - Allow dynamic router port mask\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_MASK    - Invalid port mask\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicIGMPAllowDynamicRouterPort(rtk_uint32 pmsk)\n{\n    return rtl8367c_setAsicReg(RTL8367C_REG_IGMP_MLD_CFG4, pmsk);\n}\n\n/* Function Name:\n *      rtl8367c_getAsicIGMPAllowDynamicRouterPort\n * Description:\n *      Get IGMP dynamic router port allow mask\n * Input:\n *      None.\n * Output:\n *      pPmsk   - Allow dynamic router port mask\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_MASK    - Invalid port mask\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicIGMPAllowDynamicRouterPort(rtk_uint32 *pPmsk)\n{\n    return rtl8367c_getAsicReg(RTL8367C_REG_IGMP_MLD_CFG4, pPmsk);\n}\n\n/* Function Name:\n *      rtl8367c_getAsicIGMPdynamicRouterPort1\n * Description:\n *      Get 1st dynamic router port and timer\n * Input:\n *      port    - Physical port number (0~7)\n *      timer   - router port timer\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicIGMPdynamicRouterPort1(rtk_uint32 *port, rtk_uint32 *timer)\n{\n    ret_t   retVal;\n\n    retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_IGMP_DYNAMIC_ROUTER_PORT, RTL8367C_D_ROUTER_PORT_1_MASK, port);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_IGMP_DYNAMIC_ROUTER_PORT, RTL8367C_D_ROUTER_PORT_TMR_1_MASK, timer);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtl8367c_getAsicIGMPdynamicRouterPort2\n * Description:\n *      Get 2nd dynamic router port and timer\n * Input:\n *      port    - Physical port number (0~7)\n *      timer   - router port timer\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicIGMPdynamicRouterPort2(rtk_uint32 *port, rtk_uint32 *timer)\n{\n    ret_t   retVal;\n\n    retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_IGMP_DYNAMIC_ROUTER_PORT, RTL8367C_D_ROUTER_PORT_2_MASK, port);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_IGMP_DYNAMIC_ROUTER_PORT, RTL8367C_D_ROUTER_PORT_TMR_2_MASK, timer);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtl8367c_setAsicIGMPSuppression\n * Description:\n *      Set the suppression function\n * Input:\n *      report_supp_enabled     - Report suppression, 1:Enable, 0:disable\n *      leave_supp_enabled      - Leave suppression, 1:Enable, 0:disable\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicIGMPSuppression(rtk_uint32 report_supp_enabled, rtk_uint32 leave_supp_enabled)\n{\n    ret_t   retVal;\n\n    retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_IGMP_MLD_CFG0, RTL8367C_REPORT_SUPPRESSION_MASK, report_supp_enabled);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_IGMP_MLD_CFG0, RTL8367C_LEAVE_SUPPRESSION_MASK, leave_supp_enabled);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtl8367c_getAsicIGMPSuppression\n * Description:\n *      Get the suppression function\n * Input:\n *      report_supp_enabled     - Report suppression, 1:Enable, 0:disable\n *      leave_supp_enabled      - Leave suppression, 1:Enable, 0:disable\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicIGMPSuppression(rtk_uint32 *report_supp_enabled, rtk_uint32 *leave_supp_enabled)\n{\n    ret_t   retVal;\n\n    retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_IGMP_MLD_CFG0, RTL8367C_REPORT_SUPPRESSION_MASK, report_supp_enabled);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_IGMP_MLD_CFG0, RTL8367C_LEAVE_SUPPRESSION_MASK, leave_supp_enabled);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtl8367c_setAsicIGMPQueryRX\n * Description:\n *      Set port-based Query packet RX allowance\n * Input:\n *      port            - port number\n *      allow_query     - allowance of Query packet RX, 1:Allow, 0:Drop\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_PORT_ID  - Error PORT ID\n *      RT_ERR_SMI      - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicIGMPQueryRX(rtk_uint32 port, rtk_uint32 allow_query)\n{\n    ret_t   retVal;\n\n    if(port > RTL8367C_PORTIDMAX)\n        return RT_ERR_PORT_ID;\n\n    /* Allow Query */\n    if (port < 8)\n    {\n        retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_IGMP_PORT0_CONTROL + port, RTL8367C_IGMP_PORT0_CONTROL_ALLOW_QUERY_MASK, allow_query);\n        if(retVal != RT_ERR_OK)\n            return retVal;\n    }\n    else\n    {\n        retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_IGMP_PORT8_CONTROL + port - 8, RTL8367C_IGMP_PORT0_CONTROL_ALLOW_QUERY_MASK, allow_query);\n        if(retVal != RT_ERR_OK)\n            return retVal;\n    }\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtl8367c_getAsicIGMPQueryRX\n * Description:\n *      Get port-based Query packet RX allowance\n * Input:\n *      port            - port number\n * Output:\n *      allow_query     - allowance of Query packet RX, 1:Allow, 0:Drop\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_PORT_ID  - Error PORT ID\n *      RT_ERR_SMI      - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicIGMPQueryRX(rtk_uint32 port, rtk_uint32 *allow_query)\n{\n    ret_t   retVal;\n    rtk_uint32  value;\n\n    if(port > RTL8367C_PORTIDMAX)\n        return RT_ERR_PORT_ID;\n\n    /* Allow Query */\n    if (port < 8)\n    {\n        retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_IGMP_PORT0_CONTROL + port, RTL8367C_IGMP_PORT0_CONTROL_ALLOW_QUERY_MASK, &value);\n        if(retVal != RT_ERR_OK)\n            return retVal;\n    }\n    else\n    {\n        retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_IGMP_PORT8_CONTROL + port - 8, RTL8367C_IGMP_PORT0_CONTROL_ALLOW_QUERY_MASK, &value);\n        if(retVal != RT_ERR_OK)\n            return retVal;\n    }\n    *allow_query = value;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtl8367c_setAsicIGMPReportRX\n * Description:\n *      Set port-based Report packet RX allowance\n * Input:\n *      port            - port number\n *      allow_report    - allowance of Report packet RX, 1:Allow, 0:Drop\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_PORT_ID  - Error PORT ID\n *      RT_ERR_SMI      - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicIGMPReportRX(rtk_uint32 port, rtk_uint32 allow_report)\n{\n    ret_t   retVal;\n\n    if(port > RTL8367C_PORTIDMAX)\n        return RT_ERR_PORT_ID;\n\n    if(port < 8)\n    {\n    /* Allow Report */\n        retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_IGMP_PORT0_CONTROL + port, RTL8367C_IGMP_PORT0_CONTROL_ALLOW_REPORT_MASK, allow_report);\n        if(retVal != RT_ERR_OK)\n            return retVal;\n    }\n    else\n    {\n        retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_IGMP_PORT8_CONTROL + port - 8, RTL8367C_IGMP_PORT0_CONTROL_ALLOW_REPORT_MASK, allow_report);\n        if(retVal != RT_ERR_OK)\n            return retVal;\n    }\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtl8367c_getAsicIGMPReportRX\n * Description:\n *      Get port-based Report packet RX allowance\n * Input:\n *      port            - port number\n * Output:\n *      allow_report    - allowance of Report packet RX, 1:Allow, 0:Drop\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_PORT_ID  - Error PORT ID\n *      RT_ERR_SMI      - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicIGMPReportRX(rtk_uint32 port, rtk_uint32 *allow_report)\n{\n    ret_t   retVal;\n    rtk_uint32  value;\n\n    if(port > RTL8367C_PORTIDMAX)\n        return RT_ERR_PORT_ID;\n\n    if(port < 8)\n    {\n        /* Allow Report */\n        retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_IGMP_PORT0_CONTROL + port, RTL8367C_IGMP_PORT0_CONTROL_ALLOW_REPORT_MASK, &value);\n        if(retVal != RT_ERR_OK)\n            return retVal;\n    }\n    else\n    {\n        retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_IGMP_PORT8_CONTROL + port - 8, RTL8367C_IGMP_PORT0_CONTROL_ALLOW_REPORT_MASK, &value);\n        if(retVal != RT_ERR_OK)\n            return retVal;\n    }\n    *allow_report = value;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtl8367c_setAsicIGMPLeaveRX\n * Description:\n *      Set port-based Leave packet RX allowance\n * Input:\n *      port            - port number\n *      allow_leave     - allowance of Leave packet RX, 1:Allow, 0:Drop\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_PORT_ID  - Error PORT ID\n *      RT_ERR_SMI      - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicIGMPLeaveRX(rtk_uint32 port, rtk_uint32 allow_leave)\n{\n    ret_t   retVal;\n\n    if(port > RTL8367C_PORTIDMAX)\n        return RT_ERR_PORT_ID;\n\n    if(port < 8)\n    {\n        /* Allow Leave */\n        retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_IGMP_PORT0_CONTROL + port, RTL8367C_IGMP_PORT0_CONTROL_ALLOW_LEAVE_MASK, allow_leave);\n        if(retVal != RT_ERR_OK)\n            return retVal;\n    }\n    else\n    {\n        retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_IGMP_PORT8_CONTROL + port - 8, RTL8367C_IGMP_PORT0_CONTROL_ALLOW_LEAVE_MASK, allow_leave);\n        if(retVal != RT_ERR_OK)\n            return retVal;\n    }\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtl8367c_getAsicIGMPLeaveRX\n * Description:\n *      Get port-based Leave packet RX allowance\n * Input:\n *      port            - port number\n * Output:\n *      allow_leave     - allowance of Leave packet RX, 1:Allow, 0:Drop\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_PORT_ID  - Error PORT ID\n *      RT_ERR_SMI      - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicIGMPLeaveRX(rtk_uint32 port, rtk_uint32 *allow_leave)\n{\n    ret_t   retVal;\n    rtk_uint32  value;\n\n    if(port > RTL8367C_PORTIDMAX)\n        return RT_ERR_PORT_ID;\n\n    if(port < 8)\n    {\n    /* Allow Leave */\n        retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_IGMP_PORT0_CONTROL + port, RTL8367C_IGMP_PORT0_CONTROL_ALLOW_LEAVE_MASK, &value);\n        if(retVal != RT_ERR_OK)\n            return retVal;\n    }\n    else\n    {\n        retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_IGMP_PORT8_CONTROL + port - 8, RTL8367C_IGMP_PORT0_CONTROL_ALLOW_LEAVE_MASK, &value);\n        if(retVal != RT_ERR_OK)\n            return retVal;\n    }\n\n    *allow_leave = value;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtl8367c_setAsicIGMPMRPRX\n * Description:\n *      Set port-based Multicast Routing Protocol packet RX allowance\n * Input:\n *      port            - port number\n *      allow_mrp       - allowance of Multicast Routing Protocol packet RX, 1:Allow, 0:Drop\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_PORT_ID  - Error PORT ID\n *      RT_ERR_SMI      - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicIGMPMRPRX(rtk_uint32 port, rtk_uint32 allow_mrp)\n{\n    ret_t   retVal;\n\n    if(port > RTL8367C_PORTIDMAX)\n        return RT_ERR_PORT_ID;\n\n    if(port < 8)\n    {\n    /* Allow Multicast Routing Protocol */\n        retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_IGMP_PORT0_CONTROL + port, RTL8367C_IGMP_PORT0_CONTROL_ALLOW_MRP_MASK, allow_mrp);\n        if(retVal != RT_ERR_OK)\n            return retVal;\n    }\n    else\n    {\n        retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_IGMP_PORT8_CONTROL + port - 8, RTL8367C_IGMP_PORT0_CONTROL_ALLOW_MRP_MASK, allow_mrp);\n        if(retVal != RT_ERR_OK)\n            return retVal;\n    }\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtl8367c_getAsicIGMPMRPRX\n * Description:\n *      Get port-based Multicast Routing Protocol packet RX allowance\n * Input:\n *      port            - port number\n * Output:\n *      allow_mrp       - allowance of Multicast Routing Protocol packet RX, 1:Allow, 0:Drop\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_PORT_ID  - Error PORT ID\n *      RT_ERR_SMI      - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicIGMPMRPRX(rtk_uint32 port, rtk_uint32 *allow_mrp)\n{\n    ret_t   retVal;\n    rtk_uint32  value;\n\n    if(port > RTL8367C_PORTIDMAX)\n        return RT_ERR_PORT_ID;\n\n    /* Allow Multicast Routing Protocol */\n    if(port < 8)\n    {\n        retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_IGMP_PORT0_CONTROL + port, RTL8367C_IGMP_PORT0_CONTROL_ALLOW_MRP_MASK, &value);\n        if(retVal != RT_ERR_OK)\n            return retVal;\n    }\n    else\n    {\n        retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_IGMP_PORT8_CONTROL + port - 8, RTL8367C_IGMP_PORT0_CONTROL_ALLOW_MRP_MASK, &value);\n        if(retVal != RT_ERR_OK)\n            return retVal;\n    }\n    *allow_mrp = value;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtl8367c_setAsicIGMPMcDataRX\n * Description:\n *      Set port-based Multicast data packet RX allowance\n * Input:\n *      port            - port number\n *      allow_mcdata    - allowance of Multicast data packet RX, 1:Allow, 0:Drop\n * Output:\n *      none\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_PORT_ID  - Error PORT ID\n *      RT_ERR_SMI      - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicIGMPMcDataRX(rtk_uint32 port, rtk_uint32 allow_mcdata)\n{\n    ret_t   retVal;\n\n    if(port > RTL8367C_PORTIDMAX)\n        return RT_ERR_PORT_ID;\n\n    /* Allow Multicast Data */\n    if(port < 8)\n    {\n        retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_IGMP_PORT0_CONTROL + port, RTL8367C_IGMP_PORT0_CONTROL_ALLOW_MC_DATA_MASK, allow_mcdata);\n        if(retVal != RT_ERR_OK)\n            return retVal;\n    }\n    else\n    {\n        retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_IGMP_PORT8_CONTROL + port - 8, RTL8367C_IGMP_PORT0_CONTROL_ALLOW_MC_DATA_MASK, allow_mcdata);\n        if(retVal != RT_ERR_OK)\n            return retVal;\n    }\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtl8367c_getAsicIGMPMcDataRX\n * Description:\n *      Get port-based Multicast data packet RX allowance\n * Input:\n *      port            - port number\n * Output:\n *      allow_mcdata    - allowance of Multicast data packet RX, 1:Allow, 0:Drop\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_PORT_ID  - Error PORT ID\n *      RT_ERR_SMI      - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicIGMPMcDataRX(rtk_uint32 port, rtk_uint32 *allow_mcdata)\n{\n    ret_t   retVal;\n    rtk_uint32  value;\n\n    if(port > RTL8367C_PORTIDMAX)\n        return RT_ERR_PORT_ID;\n\n    /* Allow Multicast data */\n    if(port < 8)\n    {\n        retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_IGMP_PORT0_CONTROL + port, RTL8367C_IGMP_PORT0_CONTROL_ALLOW_MC_DATA_MASK, &value);\n        if(retVal != RT_ERR_OK)\n            return retVal;\n    }\n    else\n    {\n        retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_IGMP_PORT8_CONTROL + port - 8, RTL8367C_IGMP_PORT0_CONTROL_ALLOW_MC_DATA_MASK, &value);\n        if(retVal != RT_ERR_OK)\n            return retVal;\n    }\n\n    *allow_mcdata = value;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtl8367c_setAsicIGMPv1Opeartion\n * Description:\n *      Set port-based IGMPv1 Control packet action\n * Input:\n *      port            - port number\n *      igmpv1_op       - IGMPv1 control packet action\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_PORT_ID  - Error PORT ID\n *      RT_ERR_SMI      - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicIGMPv1Opeartion(rtk_uint32 port, rtk_uint32 igmpv1_op)\n{\n    ret_t   retVal;\n\n    if(port > RTL8367C_PORTIDMAX)\n        return RT_ERR_PORT_ID;\n\n    if(igmpv1_op >= PROTOCOL_OP_END)\n        return RT_ERR_INPUT;\n\n    /* IGMPv1 operation */\n    if(port < 8)\n    {\n        retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_IGMP_PORT0_CONTROL + port, RTL8367C_IGMP_PORT0_CONTROL_IGMPV1_OP_MASK, igmpv1_op);\n        if(retVal != RT_ERR_OK)\n            return retVal;\n    }\n    else\n    {\n        retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_IGMP_PORT8_CONTROL + port - 8, RTL8367C_IGMP_PORT0_CONTROL_IGMPV1_OP_MASK, igmpv1_op);\n        if(retVal != RT_ERR_OK)\n            return retVal;\n    }\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtl8367c_getAsicIGMPv1Opeartion\n * Description:\n *      Get port-based IGMPv1 Control packet action\n * Input:\n *      port            - port number\n * Output:\n *      igmpv1_op       - IGMPv1 control packet action\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_PORT_ID  - Error PORT ID\n *      RT_ERR_SMI      - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicIGMPv1Opeartion(rtk_uint32 port, rtk_uint32 *igmpv1_op)\n{\n    ret_t   retVal;\n    rtk_uint32  value;\n\n    if(port > RTL8367C_PORTIDMAX)\n        return RT_ERR_PORT_ID;\n\n    /* IGMPv1 operation */\n    if(port < 8)\n    {\n        retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_IGMP_PORT0_CONTROL + port, RTL8367C_IGMP_PORT0_CONTROL_IGMPV1_OP_MASK, &value);\n        if(retVal != RT_ERR_OK)\n            return retVal;\n    }\n    else\n    {\n        retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_IGMP_PORT8_CONTROL + port - 8, RTL8367C_IGMP_PORT0_CONTROL_IGMPV1_OP_MASK, &value);\n        if(retVal != RT_ERR_OK)\n            return retVal;\n    }\n\n    *igmpv1_op = value;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtl8367c_setAsicIGMPv2Opeartion\n * Description:\n *      Set port-based IGMPv2 Control packet action\n * Input:\n *      port            - port number\n *      igmpv2_op       - IGMPv2 control packet action\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_PORT_ID  - Error PORT ID\n *      RT_ERR_SMI      - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicIGMPv2Opeartion(rtk_uint32 port, rtk_uint32 igmpv2_op)\n{\n    ret_t   retVal;\n\n    if(port > RTL8367C_PORTIDMAX)\n        return RT_ERR_PORT_ID;\n\n    if(igmpv2_op >= PROTOCOL_OP_END)\n        return RT_ERR_INPUT;\n\n    /* IGMPv2 operation */\n    if(port < 8)\n    {\n        retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_IGMP_PORT0_CONTROL + port, RTL8367C_IGMP_PORT0_CONTROL_IGMPV2_OP_MASK, igmpv2_op);\n        if(retVal != RT_ERR_OK)\n            return retVal;\n    }\n    else\n    {\n        retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_IGMP_PORT8_CONTROL + port - 8, RTL8367C_IGMP_PORT0_CONTROL_IGMPV2_OP_MASK, igmpv2_op);\n        if(retVal != RT_ERR_OK)\n            return retVal;\n    }\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtl8367c_getAsicIGMPv2Opeartion\n * Description:\n *      Get port-based IGMPv2 Control packet action\n * Input:\n *      port            - port number\n * Output:\n *      igmpv2_op       - IGMPv2 control packet action\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_PORT_ID  - Error PORT ID\n *      RT_ERR_SMI      - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicIGMPv2Opeartion(rtk_uint32 port, rtk_uint32 *igmpv2_op)\n{\n    ret_t   retVal;\n    rtk_uint32  value;\n\n    if(port > RTL8367C_PORTIDMAX)\n        return RT_ERR_PORT_ID;\n\n    /* IGMPv2 operation */\n    if(port < 8)\n    {\n        retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_IGMP_PORT0_CONTROL + port, RTL8367C_IGMP_PORT0_CONTROL_IGMPV2_OP_MASK, &value);\n        if(retVal != RT_ERR_OK)\n            return retVal;\n    }\n    else\n    {\n        retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_IGMP_PORT8_CONTROL + port - 8, RTL8367C_IGMP_PORT0_CONTROL_IGMPV2_OP_MASK, &value);\n        if(retVal != RT_ERR_OK)\n            return retVal;\n    }\n\n    *igmpv2_op = value;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtl8367c_setAsicIGMPv3Opeartion\n * Description:\n *      Set port-based IGMPv3 Control packet action\n * Input:\n *      port            - port number\n *      igmpv3_op       - IGMPv3 control packet action\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_PORT_ID  - Error PORT ID\n *      RT_ERR_SMI      - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicIGMPv3Opeartion(rtk_uint32 port, rtk_uint32 igmpv3_op)\n{\n    ret_t   retVal;\n\n    if(port > RTL8367C_PORTIDMAX)\n        return RT_ERR_PORT_ID;\n\n    if(igmpv3_op >= PROTOCOL_OP_END)\n        return RT_ERR_INPUT;\n\n    /* IGMPv3 operation */\n    if(port < 8)\n    {\n        retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_IGMP_PORT0_CONTROL + port, RTL8367C_IGMP_PORT0_CONTROL_IGMPV3_OP_MASK, igmpv3_op);\n        if(retVal != RT_ERR_OK)\n            return retVal;\n    }\n    else\n    {\n        retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_IGMP_PORT8_CONTROL + port - 8, RTL8367C_IGMP_PORT0_CONTROL_IGMPV3_OP_MASK, igmpv3_op);\n        if(retVal != RT_ERR_OK)\n            return retVal;\n    }\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtl8367c_getAsicIGMPv3Opeartion\n * Description:\n *      Get port-based IGMPv3 Control packet action\n * Input:\n *      port            - port number\n * Output:\n *      igmpv3_op       - IGMPv3 control packet action\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_PORT_ID  - Error PORT ID\n *      RT_ERR_SMI      - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicIGMPv3Opeartion(rtk_uint32 port, rtk_uint32 *igmpv3_op)\n{\n    ret_t   retVal;\n    rtk_uint32  value;\n\n    if(port > RTL8367C_PORTIDMAX)\n        return RT_ERR_PORT_ID;\n\n    /* IGMPv3 operation */\n    if(port < 8)\n    {\n        retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_IGMP_PORT0_CONTROL + port, RTL8367C_IGMP_PORT0_CONTROL_IGMPV3_OP_MASK, &value);\n        if(retVal != RT_ERR_OK)\n            return retVal;\n    }\n    else\n    {\n        retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_IGMP_PORT8_CONTROL + port - 8, RTL8367C_IGMP_PORT0_CONTROL_IGMPV3_OP_MASK, &value);\n        if(retVal != RT_ERR_OK)\n            return retVal;\n    }\n\n    *igmpv3_op = value;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtl8367c_setAsicMLDv1Opeartion\n * Description:\n *      Set port-based MLDv1 Control packet action\n * Input:\n *      port            - port number\n *      mldv1_op        - MLDv1 control packet action\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_PORT_ID  - Error PORT ID\n *      RT_ERR_SMI      - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicMLDv1Opeartion(rtk_uint32 port, rtk_uint32 mldv1_op)\n{\n    ret_t   retVal;\n\n    if(port > RTL8367C_PORTIDMAX)\n        return RT_ERR_PORT_ID;\n\n    if(mldv1_op >= PROTOCOL_OP_END)\n        return RT_ERR_INPUT;\n\n    /* MLDv1 operation */\n    if(port < 8)\n    {\n        retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_IGMP_PORT0_CONTROL + port, RTL8367C_IGMP_PORT0_CONTROL_MLDv1_OP_MASK, mldv1_op);\n        if(retVal != RT_ERR_OK)\n            return retVal;\n    }\n    else\n    {\n        retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_IGMP_PORT8_CONTROL + port - 8, RTL8367C_IGMP_PORT0_CONTROL_MLDv1_OP_MASK, mldv1_op);\n        if(retVal != RT_ERR_OK)\n            return retVal;\n    }\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtl8367c_getAsicMLDv1Opeartion\n * Description:\n *      Get port-based MLDv1 Control packet action\n * Input:\n *      port            - port number\n * Output:\n *      mldv1_op        - MLDv1 control packet action\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_PORT_ID  - Error PORT ID\n *      RT_ERR_SMI      - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicMLDv1Opeartion(rtk_uint32 port, rtk_uint32 *mldv1_op)\n{\n    ret_t   retVal;\n    rtk_uint32  value;\n\n    if(port > RTL8367C_PORTIDMAX)\n        return RT_ERR_PORT_ID;\n\n    /* MLDv1 operation */\n    if(port < 8)\n    {\n        retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_IGMP_PORT0_CONTROL + port, RTL8367C_IGMP_PORT0_CONTROL_MLDv1_OP_MASK, &value);\n        if(retVal != RT_ERR_OK)\n            return retVal;\n    }\n    else\n    {\n        retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_IGMP_PORT8_CONTROL + port - 8, RTL8367C_IGMP_PORT0_CONTROL_MLDv1_OP_MASK, &value);\n        if(retVal != RT_ERR_OK)\n            return retVal;\n    }\n\n    *mldv1_op = value;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtl8367c_setAsicMLDv2Opeartion\n * Description:\n *      Set port-based MLDv2 Control packet action\n * Input:\n *      port            - port number\n *      mldv2_op        - MLDv2 control packet action\n * Output:\n *      none\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_PORT_ID  - Error PORT ID\n *      RT_ERR_SMI      - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicMLDv2Opeartion(rtk_uint32 port, rtk_uint32 mldv2_op)\n{\n    ret_t   retVal;\n\n    if(port > RTL8367C_PORTIDMAX)\n        return RT_ERR_PORT_ID;\n\n    if(mldv2_op >= PROTOCOL_OP_END)\n        return RT_ERR_INPUT;\n\n    /* MLDv2 operation */\n    if(port < 8)\n    {\n        retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_IGMP_PORT0_CONTROL + port, RTL8367C_IGMP_PORT0_CONTROL_MLDv2_OP_MASK, mldv2_op);\n        if(retVal != RT_ERR_OK)\n            return retVal;\n    }\n    else\n    {\n        retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_IGMP_PORT8_CONTROL + port - 8, RTL8367C_IGMP_PORT0_CONTROL_MLDv2_OP_MASK, mldv2_op);\n        if(retVal != RT_ERR_OK)\n            return retVal;\n    }\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtl8367c_getAsicMLDv2Opeartion\n * Description:\n *      Get port-based MLDv2 Control packet action\n * Input:\n *      port            - port number\n * Output:\n *      mldv2_op        - MLDv2 control packet action\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_PORT_ID  - Error PORT ID\n *      RT_ERR_SMI      - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicMLDv2Opeartion(rtk_uint32 port, rtk_uint32 *mldv2_op)\n{\n    ret_t   retVal;\n    rtk_uint32  value;\n\n    if(port > RTL8367C_PORTIDMAX)\n        return RT_ERR_PORT_ID;\n\n    /* MLDv2 operation */\n    if(port < 8)\n    {\n        retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_IGMP_PORT0_CONTROL + port, RTL8367C_IGMP_PORT0_CONTROL_MLDv2_OP_MASK, &value);\n        if(retVal != RT_ERR_OK)\n            return retVal;\n    }\n    else\n    {\n        retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_IGMP_PORT8_CONTROL + port - 8, RTL8367C_IGMP_PORT0_CONTROL_MLDv2_OP_MASK, &value);\n        if(retVal != RT_ERR_OK)\n            return retVal;\n    }\n\n    *mldv2_op = value;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtl8367c_setAsicIGMPPortMAXGroup\n * Description:\n *      Set per-port Max group number\n * Input:\n *      port        - Physical port number (0~7)\n *      max_group   - max IGMP group\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number\n *      RT_ERR_OUT_OF_RANGE - input parameter out of range\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicIGMPPortMAXGroup(rtk_uint32 port, rtk_uint32 max_group)\n{\n    ret_t retVal;\n\n    if(port > RTL8367C_PORTIDMAX)\n        return RT_ERR_PORT_ID;\n\n    if(max_group > RTL8367C_IGMP_MAX_GOUP)\n        return RT_ERR_OUT_OF_RANGE;\n\n    if(port < 8)\n    {\n        retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_IGMP_PORT01_MAX_GROUP + (port/2), RTL8367C_PORT0_MAX_GROUP_MASK << (RTL8367C_PORT1_MAX_GROUP_OFFSET * (port%2)), max_group);\n        if(retVal != RT_ERR_OK)\n            return retVal;\n    }\n    else\n    {\n        retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_IGMP_PORT89_MAX_GROUP + (port/2), RTL8367C_PORT0_MAX_GROUP_MASK << (RTL8367C_PORT1_MAX_GROUP_OFFSET * (port%2)), max_group);\n        if(retVal != RT_ERR_OK)\n            return retVal;\n    }\n\n    return RT_ERR_OK;\n}\n/* Function Name:\n *      rtl8367c_getAsicIGMPPortMAXGroup\n * Description:\n *      Get per-port Max group number\n * Input:\n *      port        - Physical port number (0~7)\n *      max_group   - max IGMP group\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicIGMPPortMAXGroup(rtk_uint32 port, rtk_uint32 *max_group)\n{\n    ret_t   retVal;\n    rtk_uint32  value;\n\n    if(port > RTL8367C_PORTIDMAX)\n        return RT_ERR_PORT_ID;\n\n    if(port < 8)\n    {\n        retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_IGMP_PORT01_MAX_GROUP + (port/2), RTL8367C_PORT0_MAX_GROUP_MASK << (RTL8367C_PORT1_MAX_GROUP_OFFSET * (port%2)), &value);\n        if(retVal != RT_ERR_OK)\n            return retVal;\n    }\n    else\n    {\n        retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_IGMP_PORT89_MAX_GROUP + (port/2), RTL8367C_PORT0_MAX_GROUP_MASK << (RTL8367C_PORT1_MAX_GROUP_OFFSET * (port%2)), &value);\n        if(retVal != RT_ERR_OK)\n            return retVal;\n    }\n\n    *max_group = value;\n    return RT_ERR_OK;\n}\n/* Function Name:\n *      rtl8367c_getAsicIGMPPortCurrentGroup\n * Description:\n *      Get per-port current group number\n * Input:\n *      port            - Physical port number (0~7)\n *      current_group   - current IGMP group\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicIGMPPortCurrentGroup(rtk_uint32 port, rtk_uint32 *current_group)\n{\n    ret_t   retVal;\n    rtk_uint32  value;\n\n    if(port > RTL8367C_PORTIDMAX)\n        return RT_ERR_PORT_ID;\n\n    if(port < 8)\n    {\n        retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_IGMP_PORT01_CURRENT_GROUP + (port/2), RTL8367C_PORT0_CURRENT_GROUP_MASK << (RTL8367C_PORT1_CURRENT_GROUP_OFFSET * (port%2)), &value);\n        if(retVal != RT_ERR_OK)\n            return retVal;\n    }\n    else\n    {\n        retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_IGMP_PORT89_CURRENT_GROUP + ((port - 8)/2), RTL8367C_PORT0_CURRENT_GROUP_MASK << (RTL8367C_PORT1_CURRENT_GROUP_OFFSET * (port%2)), &value);\n        if(retVal != RT_ERR_OK)\n            return retVal;\n    }\n\n    *current_group = value;\n    return RT_ERR_OK;\n}\n/* Function Name:\n *      rtl8367c_getAsicIGMPGroup\n * Description:\n *      Get IGMP group\n * Input:\n *      idx     - Group index (0~255)\n *      valid   - valid bit\n *      grp     - IGMP group\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - Success\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_OUT_OF_RANGE     - Group index is out of range\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicIGMPGroup(rtk_uint32 idx, rtk_uint32 *valid, rtl8367c_igmpgroup *grp)\n{\n    ret_t   retVal;\n    rtk_uint32  regAddr, regData;\n    rtk_uint32  i;\n    rtk_uint32  groupInfo = 0;\n\n    if(idx > RTL8367C_IGMP_MAX_GOUP)\n        return RT_ERR_OUT_OF_RANGE;\n\n    /* Write ACS_ADR register for data bits */\n    regAddr = RTL8367C_TABLE_ACCESS_ADDR_REG;\n    regData = idx;\n    retVal = rtl8367c_setAsicReg(regAddr, regData);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    /* Write ACS_CMD register */\n    regAddr = RTL8367C_TABLE_ACCESS_CTRL_REG;\n    regData = RTL8367C_TABLE_ACCESS_REG_DATA(TB_OP_READ, TB_TARGET_IGMP_GROUP);\n    retVal = rtl8367c_setAsicRegBits(regAddr, RTL8367C_TABLE_TYPE_MASK | RTL8367C_COMMAND_TYPE_MASK, regData);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    /* Read Data Bits */\n    regAddr = RTL8367C_TABLE_ACCESS_RDDATA_BASE;\n    for(i = 0 ;i <= 1; i++)\n    {\n        retVal = rtl8367c_getAsicReg(regAddr, &regData);\n        if(retVal != RT_ERR_OK)\n            return retVal;\n\n        groupInfo |= ((regData & 0xFFFF) << (i * 16));\n        regAddr ++;\n    }\n\n    grp->p0_timer = groupInfo & 0x00000007;\n    grp->p1_timer = (groupInfo >> 3) & 0x00000007;\n    grp->p2_timer = (groupInfo >> 6) & 0x00000007;\n    grp->p3_timer = (groupInfo >> 9) & 0x00000007;\n    grp->p4_timer = (groupInfo >> 12) & 0x00000007;\n    grp->p5_timer = (groupInfo >> 15) & 0x00000007;\n    grp->p6_timer = (groupInfo >> 18) & 0x00000007;\n    grp->p7_timer = (groupInfo >> 21) & 0x00000007;\n    grp->report_supp_flag = (groupInfo >> 24) & 0x00000001;\n    grp->p8_timer = (groupInfo >> 25) & 0x00000007;\n    grp->p9_timer = (groupInfo >> 28) & 0x00000007;\n    grp->p10_timer = (groupInfo >> 31) & 0x00000001;\n\n    regAddr = RTL8367C_TABLE_ACCESS_RDDATA_BASE + 2;\n    retVal = rtl8367c_getAsicReg(regAddr, &regData);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    grp->p10_timer |= (regData & 0x00000003) << 1;\n\n    /* Valid bit */\n    retVal = rtl8367c_getAsicReg(RTL8367C_IGMP_GROUP_USAGE_REG(idx), &regData);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    *valid = ((regData & (0x0001 << (idx %16))) != 0) ? 1 : 0;\n\n    return RT_ERR_OK;\n}\n/* Function Name:\n *      rtl8367c_setAsicIpMulticastPortIsoLeaky\n * Description:\n *      Set IP multicast Port Isolation leaky\n * Input:\n *      port        - Physical port number (0~7)\n *      enabled     - 1: enabled, 0: disabled\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n *      RT_ERR_PORT_ID  - Invalid port number\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicIpMulticastPortIsoLeaky(rtk_uint32 port, rtk_uint32 enabled)\n{\n    ret_t   retVal;\n\n    if(port > RTL8367C_PORTIDMAX)\n        return RT_ERR_PORT_ID;\n\n    retVal = rtl8367c_setAsicRegBits(RTL8367C_IPMCAST_PORTISO_LEAKY_REG, (0x0001 << port), enabled);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtl8367c_getAsicIpMulticastPortIsoLeaky\n * Description:\n *      Get IP multicast Port Isolation leaky\n * Input:\n *      port        - Physical port number (0~7)\n *      enabled     - 1: enabled, 0: disabled\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicIpMulticastPortIsoLeaky(rtk_uint32 port, rtk_uint32 *enabled)\n{\n    ret_t   retVal;\n    rtk_uint32  regData;\n\n    retVal = rtl8367c_getAsicRegBits(RTL8367C_IPMCAST_PORTISO_LEAKY_REG, (0x0001 << port), &regData);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    *enabled = regData;\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtl8367c_setAsicIGMPReportLeaveFlood\n * Description:\n *      Set IGMP/MLD Report/Leave flood\n * Input:\n *      flood   - 0: Reserved, 1: flooding to router ports, 2: flooding to all ports, 3: flooding to router port or to all ports if there is no router port\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicIGMPReportLeaveFlood(rtk_uint32 flood)\n{\n    ret_t   retVal;\n\n    retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_IGMP_MLD_CFG3, RTL8367C_REPORT_LEAVE_FORWARD_MASK, flood);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtl8367c_getAsicIGMPReportLeaveFlood\n * Description:\n *      Get IGMP/MLD Report/Leave flood\n * Input:\n *      None\n * Output:\n *      pflood  - 0: Reserved, 1: flooding to router ports, 2: flooding to all ports, 3: flooding to router port or to all ports if there is no router port\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicIGMPReportLeaveFlood(rtk_uint32 *pFlood)\n{\n    ret_t   retVal;\n    rtk_uint32  regData;\n\n    retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_IGMP_MLD_CFG3, RTL8367C_REPORT_LEAVE_FORWARD_MASK, &regData);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    *pFlood = regData;\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtl8367c_setAsicIGMPDropLeaveZero\n * Description:\n *      Set the function of droppping Leave packet with group IP = 0.0.0.0\n * Input:\n *      drop    - 1: Drop, 0:Bypass\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicIGMPDropLeaveZero(rtk_uint32 drop)\n{\n    ret_t   retVal;\n\n    retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_IGMP_MLD_CFG1, RTL8367C_DROP_LEAVE_ZERO_OFFSET, drop);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtl8367c_getAsicIGMPDropLeaveZero\n * Description:\n *      Get the function of droppping Leave packet with group IP = 0.0.0.0\n * Input:\n *      None\n * Output:\n *      pDrop    - 1: Drop, 0:Bypass\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicIGMPDropLeaveZero(rtk_uint32 *pDrop)\n{\n    ret_t   retVal;\n    rtk_uint32  regData;\n\n    retVal = rtl8367c_getAsicRegBit(RTL8367C_REG_IGMP_MLD_CFG1, RTL8367C_DROP_LEAVE_ZERO_OFFSET, &regData);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    *pDrop = regData;\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtl8367c_setAsicIGMPBypassStormCTRL\n * Description:\n *      Set the function of bypass strom control for IGMP/MLD packet\n * Input:\n *      bypass    - 1: Bypass, 0:not bypass\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicIGMPBypassStormCTRL(rtk_uint32 bypass)\n{\n    ret_t   retVal;\n\n    retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_IGMP_MLD_CFG0, RTL8367C_IGMP_MLD_DISCARD_STORM_FILTER_OFFSET, bypass);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtl8367c_getAsicIGMPBypassStormCTRL\n * Description:\n *      Set the function of bypass strom control for IGMP/MLD packet\n * Input:\n *      None\n * Output:\n *      pBypass    - 1: Bypass, 0:not bypass\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicIGMPBypassStormCTRL(rtk_uint32 *pBypass)\n{\n    ret_t   retVal;\n    rtk_uint32  regData;\n\n    retVal = rtl8367c_getAsicRegBit(RTL8367C_REG_IGMP_MLD_CFG0, RTL8367C_IGMP_MLD_DISCARD_STORM_FILTER_OFFSET, &regData);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    *pBypass = regData;\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtl8367c_setAsicIGMPIsoLeaky\n * Description:\n *      Set Port Isolation leaky for IGMP/MLD packet\n * Input:\n *      leaky    - 1: Leaky, 0:not leaky\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicIGMPIsoLeaky(rtk_uint32 leaky)\n{\n    ret_t   retVal;\n\n    retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_IGMP_MLD_CFG0, RTL8367C_IGMP_MLD_PORTISO_LEAKY_OFFSET, leaky);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtl8367c_getAsicIGMPIsoLeaky\n * Description:\n *      Get Port Isolation leaky for IGMP/MLD packet\n * Input:\n *      Noen\n * Output:\n *      pLeaky    - 1: Leaky, 0:not leaky\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicIGMPIsoLeaky(rtk_uint32 *pLeaky)\n{\n    ret_t   retVal;\n    rtk_uint32  regData;\n\n    retVal = rtl8367c_getAsicRegBit(RTL8367C_REG_IGMP_MLD_CFG0, RTL8367C_IGMP_MLD_PORTISO_LEAKY_OFFSET, &regData);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    *pLeaky = regData;\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtl8367c_setAsicIGMPVLANLeaky\n * Description:\n *      Set VLAN leaky for IGMP/MLD packet\n * Input:\n *      leaky    - 1: Leaky, 0:not leaky\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicIGMPVLANLeaky(rtk_uint32 leaky)\n{\n    ret_t   retVal;\n\n    retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_IGMP_MLD_CFG0, RTL8367C_IGMP_MLD_VLAN_LEAKY_OFFSET, leaky);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtl8367c_getAsicIGMPVLANLeaky\n * Description:\n *      Get VLAN leaky for IGMP/MLD packet\n * Input:\n *      Noen\n * Output:\n *      pLeaky    - 1: Leaky, 0:not leaky\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicIGMPVLANLeaky(rtk_uint32 *pLeaky)\n{\n    ret_t   retVal;\n    rtk_uint32  regData;\n\n    retVal = rtl8367c_getAsicRegBit(RTL8367C_REG_IGMP_MLD_CFG0, RTL8367C_IGMP_MLD_VLAN_LEAKY_OFFSET, &regData);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    *pLeaky = regData;\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtl8367c_setAsicIGMPBypassGroup\n * Description:\n *      Set IGMP/MLD Bypass group\n * Input:\n *      bypassType  - Bypass type\n *      enabled     - enabled\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicIGMPBypassGroup(rtk_uint32 bypassType, rtk_uint32 enabled)\n{\n    ret_t   retVal;\n    rtk_uint32 offset;\n\n    switch(bypassType)\n    {\n        case BYPASS_224_0_0_X:\n            offset = RTL8367C_IGMP_MLD_IP4_BYPASS_224_0_0_OFFSET;\n            break;\n        case BYPASS_224_0_1_X:\n            offset = RTL8367C_IGMP_MLD_IP4_BYPASS_224_0_1_OFFSET;\n            break;\n        case BYPASS_239_255_255_X:\n            offset = RTL8367C_IGMP_MLD_IP4_BYPASS_239_255_255_OFFSET;\n            break;\n        case BYPASS_IPV6_00XX:\n            offset = RTL8367C_IGMP_MLD_IP6_BYPASS_OFFSET;\n            break;\n        default:\n            return RT_ERR_INPUT;\n    }\n\n    retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_IGMP_MLD_CFG3, offset, enabled);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtl8367c_getAsicIGMPBypassGroup\n * Description:\n *      Get IGMP/MLD Bypass group\n * Input:\n *      bypassType  - Bypass type\n * Output:\n *      pEnabled    - enabled\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicIGMPBypassGroup(rtk_uint32 bypassType, rtk_uint32 *pEnabled)\n{\n    ret_t   retVal;\n    rtk_uint32 offset;\n\n    switch(bypassType)\n    {\n        case BYPASS_224_0_0_X:\n            offset = RTL8367C_IGMP_MLD_IP4_BYPASS_224_0_0_OFFSET;\n            break;\n        case BYPASS_224_0_1_X:\n            offset = RTL8367C_IGMP_MLD_IP4_BYPASS_224_0_1_OFFSET;\n            break;\n        case BYPASS_239_255_255_X:\n            offset = RTL8367C_IGMP_MLD_IP4_BYPASS_239_255_255_OFFSET;\n            break;\n        case BYPASS_IPV6_00XX:\n            offset = RTL8367C_IGMP_MLD_IP6_BYPASS_OFFSET;\n            break;\n        default:\n            return RT_ERR_INPUT;\n    }\n\n    retVal = rtl8367c_getAsicRegBit(RTL8367C_REG_IGMP_MLD_CFG3, offset, pEnabled);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_inbwctrl.c",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * $Revision: 76306 $\n * $Date: 2017-03-08 15:13:58 +0800 (週三, 08 三月 2017) $\n *\n * Purpose : RTL8367C switch high-level API for RTL8367C\n * Feature : Ingress bandwidth control related functions\n *\n */\n#include <rtl8367c_asicdrv_inbwctrl.h>\n/* Function Name:\n *      rtl8367c_setAsicPortIngressBandwidth\n * Description:\n *      Set per-port total ingress bandwidth\n * Input:\n *      port        - Physical port number (0~7)\n *      bandwidth   - The total ingress bandwidth (unit: 8Kbps), 0x1FFFF:disable\n *      preifg      - Include preamble and IFG, 0:Exclude, 1:Include\n *      enableFC    - Action when input rate exceeds. 0: Drop   1: Flow Control\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number\n *      RT_ERR_OUT_OF_RANGE - input parameter out of range\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicPortIngressBandwidth(rtk_uint32 port, rtk_uint32 bandwidth, rtk_uint32 preifg, rtk_uint32 enableFC)\n{\n    ret_t retVal;\n    rtk_uint32 regData;\n    rtk_uint32 regAddr;\n\n    /* Invalid input parameter */\n    if(port >= RTL8367C_PORTNO)\n        return RT_ERR_PORT_ID;\n\n    if(bandwidth > RTL8367C_QOS_GRANULARTY_MAX)\n        return RT_ERR_OUT_OF_RANGE;\n\n    regAddr = RTL8367C_INGRESSBW_PORT_RATE_LSB_REG(port);\n    regData = bandwidth & RTL8367C_QOS_GRANULARTY_LSB_MASK;\n    retVal = rtl8367c_setAsicReg(regAddr, regData);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    regAddr += 1;\n    regData = (bandwidth & RTL8367C_QOS_GRANULARTY_MSB_MASK) >> RTL8367C_QOS_GRANULARTY_MSB_OFFSET;\n    retVal = rtl8367c_setAsicRegBits(regAddr, RTL8367C_INGRESSBW_PORT0_RATE_CTRL1_INGRESSBW_RATE16_MASK, regData);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    regAddr = RTL8367C_PORT_MISC_CFG_REG(port);\n    retVal = rtl8367c_setAsicRegBit(regAddr, RTL8367C_PORT0_MISC_CFG_INGRESSBW_IFG_OFFSET, preifg);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    regAddr = RTL8367C_PORT_MISC_CFG_REG(port);\n    retVal = rtl8367c_setAsicRegBit(regAddr, RTL8367C_PORT0_MISC_CFG_INGRESSBW_FLOWCTRL_OFFSET, enableFC);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n/* Function Name:\n *      rtl8367c_getAsicPortIngressBandwidth\n * Description:\n *      Get per-port total ingress bandwidth\n * Input:\n *      port        - Physical port number (0~7)\n *      pBandwidth  - The total ingress bandwidth (unit: 8Kbps), 0x1FFFF:disable\n *      pPreifg         - Include preamble and IFG, 0:Exclude, 1:Include\n *      pEnableFC   - Action when input rate exceeds. 0: Drop   1: Flow Control\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicPortIngressBandwidth(rtk_uint32 port, rtk_uint32* pBandwidth, rtk_uint32* pPreifg, rtk_uint32* pEnableFC)\n{\n    ret_t retVal;\n    rtk_uint32 regData;\n    rtk_uint32 regAddr;\n\n    /* Invalid input parameter */\n    if(port >= RTL8367C_PORTNO)\n        return RT_ERR_PORT_ID;\n\n    regAddr = RTL8367C_INGRESSBW_PORT_RATE_LSB_REG(port);\n    retVal = rtl8367c_getAsicReg(regAddr, &regData);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    *pBandwidth = regData;\n\n    regAddr += 1;\n    retVal = rtl8367c_getAsicRegBits(regAddr, RTL8367C_INGRESSBW_PORT0_RATE_CTRL1_INGRESSBW_RATE16_MASK, &regData);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    *pBandwidth |= (regData << RTL8367C_QOS_GRANULARTY_MSB_OFFSET);\n\n    regAddr = RTL8367C_PORT_MISC_CFG_REG(port);\n    retVal = rtl8367c_getAsicRegBit(regAddr, RTL8367C_PORT0_MISC_CFG_INGRESSBW_IFG_OFFSET, pPreifg);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    regAddr = RTL8367C_PORT_MISC_CFG_REG(port);\n    retVal = rtl8367c_getAsicRegBit(regAddr, RTL8367C_PORT0_MISC_CFG_INGRESSBW_FLOWCTRL_OFFSET, pEnableFC);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n/* Function Name:\n *      rtl8367c_setAsicPortIngressBandwidthBypass\n * Description:\n *      Set ingress bandwidth control bypasss 8899, RMA 01-80-C2-00-00-xx and IGMP\n * Input:\n *      enabled - 1: enabled, 0: disabled\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicPortIngressBandwidthBypass(rtk_uint32 enabled)\n{\n    return rtl8367c_setAsicRegBit(RTL8367C_REG_SW_DUMMY0, RTL8367C_INGRESSBW_BYPASS_EN_OFFSET, enabled);\n}\n/* Function Name:\n *      rtl8367c_getAsicPortIngressBandwidthBypass\n * Description:\n *      Set ingress bandwidth control bypasss 8899, RMA 01-80-C2-00-00-xx and IGMP\n * Input:\n *      pEnabled - 1: enabled, 0: disabled\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicPortIngressBandwidthBypass(rtk_uint32* pEnabled)\n{\n    return rtl8367c_getAsicRegBit(RTL8367C_REG_SW_DUMMY0, RTL8367C_INGRESSBW_BYPASS_EN_OFFSET, pEnabled);\n}\n\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_interrupt.c",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * $Revision: 76306 $\n * $Date: 2017-03-08 15:13:58 +0800 (週三, 08 三月 2017) $\n *\n * Purpose : RTL8367C switch high-level API for RTL8367C\n * Feature : Interrupt related functions\n *\n */\n#include <rtl8367c_asicdrv_interrupt.h>\n/* Function Name:\n *      rtl8367c_setAsicInterruptPolarity\n * Description:\n *      Set interrupt trigger polarity\n * Input:\n *      polarity    - 0:pull high 1: pull low\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicInterruptPolarity(rtk_uint32 polarity)\n{\n    return rtl8367c_setAsicRegBit(RTL8367C_REG_INTR_CTRL, RTL8367C_INTR_CTRL_OFFSET, polarity);\n}\n/* Function Name:\n *      rtl8367c_getAsicInterruptPolarity\n * Description:\n *      Get interrupt trigger polarity\n * Input:\n *      pPolarity   - 0:pull high 1: pull low\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicInterruptPolarity(rtk_uint32* pPolarity)\n{\n    return rtl8367c_getAsicRegBit(RTL8367C_REG_INTR_CTRL, RTL8367C_INTR_CTRL_OFFSET, pPolarity);\n}\n/* Function Name:\n *      rtl8367c_setAsicInterruptMask\n * Description:\n *      Set interrupt enable mask\n * Input:\n *      imr     - Interrupt mask\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicInterruptMask(rtk_uint32 imr)\n{\n    return rtl8367c_setAsicReg(RTL8367C_REG_INTR_IMR, imr);\n}\n/* Function Name:\n *      rtl8367c_getAsicInterruptMask\n * Description:\n *      Get interrupt enable mask\n * Input:\n *      pImr    - Interrupt mask\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicInterruptMask(rtk_uint32* pImr)\n{\n    return rtl8367c_getAsicReg(RTL8367C_REG_INTR_IMR, pImr);\n}\n/* Function Name:\n *      rtl8367c_setAsicInterruptMask\n * Description:\n *      Clear interrupt enable mask\n * Input:\n *      ims     - Interrupt status mask\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      This API can be used to clear ASIC interrupt status and register will be cleared by writting 1.\n *      [0]:Link change,\n *      [1]:Share meter exceed,\n *      [2]:Learn number overed,\n *      [3]:Speed Change,\n *      [4]:Tx special congestion\n *      [5]:1 second green feature\n *      [6]:loop detection\n *      [7]:interrupt from 8051\n *      [8]:Cable diagnostic finish\n *      [9]:ACL action interrupt trigger\n *      [11]: Silent Start\n */\nret_t rtl8367c_setAsicInterruptStatus(rtk_uint32 ims)\n{\n    return rtl8367c_setAsicReg(RTL8367C_REG_INTR_IMS, ims);\n}\n/* Function Name:\n *      rtl8367c_getAsicInterruptStatus\n * Description:\n *      Get interrupt enable mask\n * Input:\n *      pIms    - Interrupt status mask\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicInterruptStatus(rtk_uint32* pIms)\n{\n    return rtl8367c_getAsicReg(RTL8367C_REG_INTR_IMS, pIms);\n}\n/* Function Name:\n *      rtl8367c_setAsicInterruptRelatedStatus\n * Description:\n *      Clear interrupt status\n * Input:\n *      type    - per port Learn over, per-port speed change, per-port special congest, share meter exceed status\n *      status  - exceed status, write 1 to clear\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_OUT_OF_RANGE - input parameter out of range\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicInterruptRelatedStatus(rtk_uint32 type, rtk_uint32 status)\n{\n    CONST rtk_uint32 indicatorAddress[INTRST_END] = {RTL8367C_REG_LEARN_OVER_INDICATOR,\n                                                    RTL8367C_REG_SPEED_CHANGE_INDICATOR,\n                                                    RTL8367C_REG_SPECIAL_CONGEST_INDICATOR,\n                                                    RTL8367C_REG_PORT_LINKDOWN_INDICATOR,\n                                                    RTL8367C_REG_PORT_LINKUP_INDICATOR,\n                                                    RTL8367C_REG_METER_OVERRATE_INDICATOR0,\n                                                    RTL8367C_REG_METER_OVERRATE_INDICATOR1,\n                                                    RTL8367C_REG_RLDP_LOOPED_INDICATOR,\n                                                    RTL8367C_REG_RLDP_RELEASED_INDICATOR,\n                                                    RTL8367C_REG_SYSTEM_LEARN_OVER_INDICATOR};\n\n    if(type >= INTRST_END )\n        return RT_ERR_OUT_OF_RANGE;\n\n    return rtl8367c_setAsicReg(indicatorAddress[type], status);\n}\n/* Function Name:\n *      rtl8367c_getAsicInterruptRelatedStatus\n * Description:\n *      Get interrupt status\n * Input:\n *      type    - per port Learn over, per-port speed change, per-port special congest, share meter exceed status\n *      pStatus     - exceed status, write 1 to clear\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_OUT_OF_RANGE - input parameter out of range\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicInterruptRelatedStatus(rtk_uint32 type, rtk_uint32* pStatus)\n{\n    CONST rtk_uint32 indicatorAddress[INTRST_END] = {RTL8367C_REG_LEARN_OVER_INDICATOR,\n                                                    RTL8367C_REG_SPEED_CHANGE_INDICATOR,\n                                                    RTL8367C_REG_SPECIAL_CONGEST_INDICATOR,\n                                                    RTL8367C_REG_PORT_LINKDOWN_INDICATOR,\n                                                    RTL8367C_REG_PORT_LINKUP_INDICATOR,\n                                                    RTL8367C_REG_METER_OVERRATE_INDICATOR0,\n                                                    RTL8367C_REG_METER_OVERRATE_INDICATOR1,\n                                                    RTL8367C_REG_RLDP_LOOPED_INDICATOR,\n                                                    RTL8367C_REG_RLDP_RELEASED_INDICATOR,\n                                                    RTL8367C_REG_SYSTEM_LEARN_OVER_INDICATOR};\n\n    if(type >= INTRST_END )\n        return RT_ERR_OUT_OF_RANGE;\n\n    return rtl8367c_getAsicReg(indicatorAddress[type], pStatus);\n}\n\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_led.c",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * $Revision: 76306 $\n * $Date: 2017-03-08 15:13:58 +0800 (週三, 08 三月 2017) $\n *\n * Purpose : RTL8367C switch high-level API for RTL8367C\n * Feature : LED related functions\n *\n */\n#include <rtl8367c_asicdrv_led.h>\n/* Function Name:\n *      rtl8367c_setAsicLedIndicateInfoConfig\n * Description:\n *      Set Leds indicated information mode\n * Input:\n *      ledno   - LED group number. There are 1 to 1 led mapping to each port in each led group\n *      config  - Support 16 types configuration\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_OUT_OF_RANGE - input parameter out of range\n * Note:\n *      The API can set LED indicated information configuration for each LED group with 1 to 1 led mapping to each port.\n *      Definition        LED Statuses            Description\n *      0000        LED_Off                LED pin Tri-State.\n *      0001        Dup/Col                Collision, Full duplex Indicator. Blinking every 43ms when collision happens. Low for full duplex, and high for half duplex mode.\n *      0010        Link/Act               Link, Activity Indicator. Low for link established. Link/Act Blinks every 43ms when the corresponding port is transmitting or receiving.\n *      0011        Spd1000                1000Mb/s Speed Indicator. Low for 1000Mb/s.\n *      0100        Spd100                 100Mb/s Speed Indicator. Low for 100Mb/s.\n *      0101        Spd10                  10Mb/s Speed Indicator. Low for 10Mb/s.\n *      0110        Spd1000/Act            1000Mb/s Speed/Activity Indicator. Low for 1000Mb/s. Blinks every 43ms when the corresponding port is transmitting or receiving.\n *      0111        Spd100/Act             100Mb/s Speed/Activity Indicator. Low for 100Mb/s. Blinks every 43ms when the corresponding port is transmitting or receiving.\n *      1000        Spd10/Act              10Mb/s Speed/Activity Indicator. Low for 10Mb/s. Blinks every 43ms when the corresponding port is transmitting or receiving.\n *      1001        Spd100 (10)/Act        10/100Mb/s Speed/Activity Indicator. Low for 10/100Mb/s. Blinks every 43ms when the corresponding port is transmitting or receiving.\n *      1010        Fiber                  Fiber link Indicator. Low for Fiber.\n *      1011        Fault                  Auto-negotiation     Fault Indicator. Low for Fault.\n *      1100        Link/Rx                Link, Activity Indicator. Low for link established. Link/Rx Blinks every 43ms when the corresponding port is transmitting.\n *      1101        Link/Tx                Link, Activity Indicator. Low for link established. Link/Tx Blinks every 43ms when the corresponding port is receiving.\n *      1110        Master                 Link on Master Indicator. Low for link Master established.\n *      1111        LED_Force              Force LED output, LED output value reference\n */\nret_t rtl8367c_setAsicLedIndicateInfoConfig(rtk_uint32 ledno, rtk_uint32 config)\n{\n    ret_t   retVal;\n    CONST rtk_uint16 bits[RTL8367C_LEDGROUPNO] = {RTL8367C_LED0_CFG_MASK, RTL8367C_LED1_CFG_MASK, RTL8367C_LED2_CFG_MASK};\n\n    if(ledno >= RTL8367C_LEDGROUPNO)\n        return RT_ERR_OUT_OF_RANGE;\n\n    if(config >= LEDCONF_END)\n        return RT_ERR_OUT_OF_RANGE;\n\n    retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_LED_CONFIGURATION, RTL8367C_LED_CONFIG_SEL_OFFSET, 0);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    return rtl8367c_setAsicRegBits(RTL8367C_REG_LED_CONFIGURATION, bits[ledno], config);\n}\n/* Function Name:\n *      rtl8367c_getAsicLedIndicateInfoConfig\n * Description:\n *      Get Leds indicated information mode\n * Input:\n *      ledno   - LED group number. There are 1 to 1 led mapping to each port in each led group\n *      pConfig     - Support 16 types configuration\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_OUT_OF_RANGE - input parameter out of range\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicLedIndicateInfoConfig(rtk_uint32 ledno, rtk_uint32* pConfig)\n{\n    CONST rtk_uint16 bits[RTL8367C_LEDGROUPNO]= {RTL8367C_LED0_CFG_MASK, RTL8367C_LED1_CFG_MASK, RTL8367C_LED2_CFG_MASK};\n\n    if(ledno >= RTL8367C_LEDGROUPNO)\n        return RT_ERR_OUT_OF_RANGE;\n\n    /* Get register value */\n    return rtl8367c_getAsicRegBits(RTL8367C_REG_LED_CONFIGURATION, bits[ledno], pConfig);\n}\n/* Function Name:\n *      rtl8367c_setAsicLedGroupMode\n * Description:\n *      Set Led Group mode\n * Input:\n *      mode    - LED mode\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_OUT_OF_RANGE - input parameter out of range\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicLedGroupMode(rtk_uint32 mode)\n{\n    ret_t retVal;\n\n    /* Invalid input parameter */\n    if(mode >= RTL8367C_LED_MODE_END)\n        return RT_ERR_OUT_OF_RANGE;\n\n    retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_LED_CONFIGURATION, RTL8367C_LED_CONFIG_SEL_OFFSET, 1);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    return rtl8367c_setAsicRegBits(RTL8367C_REG_LED_CONFIGURATION, RTL8367C_DATA_LED_MASK, mode);\n}\n/* Function Name:\n *      rtl8367c_getAsicLedGroupMode\n * Description:\n *      Get Led Group mode\n * Input:\n *      pMode   - LED mode\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicLedGroupMode(rtk_uint32* pMode)\n{\n    ret_t retVal;\n    rtk_uint32 regData;\n\n    retVal = rtl8367c_getAsicRegBit(RTL8367C_REG_LED_CONFIGURATION, RTL8367C_LED_CONFIG_SEL_OFFSET, &regData);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    if(regData!=1)\n        return RT_ERR_FAILED;\n\n    return rtl8367c_getAsicRegBits(RTL8367C_REG_LED_CONFIGURATION, RTL8367C_DATA_LED_MASK, pMode);\n}\n/* Function Name:\n *      rtl8367c_setAsicForceLeds\n * Description:\n *      Set group LED mode\n * Input:\n *      port    - Physical port number (0~7)\n *      group   - LED group number\n *      mode    - LED mode\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number\n *      RT_ERR_OUT_OF_RANGE - input parameter out of range\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicForceLed(rtk_uint32 port, rtk_uint32 group, rtk_uint32 mode)\n{\n    rtk_uint16 regAddr;\n    ret_t retVal;\n\n    /* Invalid input parameter */\n    if(port > RTL8367C_PORTIDMAX)\n        return RT_ERR_PORT_ID;\n\n    if(group >= RTL8367C_LEDGROUPNO)\n        return RT_ERR_OUT_OF_RANGE;\n\n    if(mode >= LEDFORCEMODE_END)\n        return RT_ERR_OUT_OF_RANGE;\n    /* Set Related Registers */\n    if(port < 8){\n        regAddr = RTL8367C_LED_FORCE_MODE_BASE + (group << 1);\n        if((retVal = rtl8367c_setAsicRegBits(regAddr, 0x3 << (port * 2), mode)) != RT_ERR_OK)\n            return retVal;\n    }else if(port >= 8){\n        regAddr = RTL8367C_REG_CPU_FORCE_LED0_CFG1 + (group << 1);\n        if((retVal = rtl8367c_setAsicRegBits(regAddr, 0x3 << ((port-8) * 2), mode)) != RT_ERR_OK)\n            return retVal;\n    }\n\n    return RT_ERR_OK;\n}\n/* Function Name:\n *      rtl8367c_getAsicForceLed\n * Description:\n *      Get group LED mode\n * Input:\n *      port    - Physical port number (0~7)\n *      group   - LED group number\n *      pMode   - LED mode\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number\n *      RT_ERR_OUT_OF_RANGE - input parameter out of range\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicForceLed(rtk_uint32 port, rtk_uint32 group, rtk_uint32* pMode)\n{\n    rtk_uint16 regAddr;\n    ret_t retVal;\n\n    /* Invalid input parameter */\n    if(port > RTL8367C_PORTIDMAX)\n        return RT_ERR_PORT_ID;\n\n    if(group >= RTL8367C_LEDGROUPNO)\n        return RT_ERR_INPUT;\n\n    /* Get Related Registers */\n    if(port < 8){\n        regAddr = RTL8367C_LED_FORCE_MODE_BASE + (group << 1);\n        if((retVal = rtl8367c_getAsicRegBits(regAddr, 0x3 << (port * 2), pMode)) != RT_ERR_OK)\n            return retVal;\n    }else if(port >= 8){\n        regAddr = RTL8367C_REG_CPU_FORCE_LED0_CFG1 + (group << 1);\n        if((retVal = rtl8367c_getAsicRegBits(regAddr, 0x3 << ((port-8) * 2), pMode)) != RT_ERR_OK)\n            return retVal;\n    }\n\n    return RT_ERR_OK;\n}\n/* Function Name:\n *      rtl8367c_setAsicForceGroupLed\n * Description:\n *      Turn on/off Led of all ports\n * Input:\n *      group   - LED group number\n *      mode    - 0b00:normal mode, 0b01:force blink, 0b10:force off, 0b11:force on\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_OUT_OF_RANGE - input parameter out of range\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicForceGroupLed(rtk_uint32 groupmask, rtk_uint32 mode)\n{\n    ret_t retVal;\n    rtk_uint32 i,bitmask;\n    CONST rtk_uint16 bits[3]= {0x0004,0x0010,0x0040};\n\n    /* Invalid input parameter */\n    if(groupmask > RTL8367C_LEDGROUPMASK)\n        return RT_ERR_OUT_OF_RANGE;\n\n    if(mode >= LEDFORCEMODE_END)\n        return RT_ERR_OUT_OF_RANGE;\n\n    bitmask = 0;\n    for(i = 0; i <  RTL8367C_LEDGROUPNO; i++)\n    {\n        if(groupmask & (1 << i))\n        {\n            bitmask = bitmask | bits[i];\n        }\n\n    }\n\n    retVal = rtl8367c_setAsicRegBits(RTL8367C_LED_FORCE_CTRL, RTL8367C_LED_FORCE_MODE_MASK, bitmask);\n\n    retVal = rtl8367c_setAsicRegBits(RTL8367C_LED_FORCE_CTRL, RTL8367C_FORCE_MODE_MASK, mode);\n\n    if(LEDFORCEMODE_NORMAL == mode)\n        retVal = rtl8367c_setAsicRegBits(RTL8367C_LED_FORCE_CTRL, RTL8367C_LED_FORCE_MODE_MASK, 0);\n\n    return retVal;\n}\n/* Function Name:\n *      rtl8367c_getAsicForceGroupLed\n * Description:\n *      Turn on/off Led of all ports\n * Input:\n *      group   - LED group number\n *      pMode   - 0b00:normal mode, 0b01:force blink, 0b10:force off, 0b11:force on\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicForceGroupLed(rtk_uint32* groupmask, rtk_uint32* pMode)\n{\n    ret_t retVal;\n    rtk_uint32 i,regData;\n    CONST rtk_uint16 bits[3] = {0x0004,0x0010,0x0040};\n\n    /* Get Related Registers */\n    if((retVal = rtl8367c_getAsicRegBits(RTL8367C_LED_FORCE_CTRL, RTL8367C_LED_FORCE_MODE_MASK, &regData)) != RT_ERR_OK)\n        return retVal;\n\n    for(i = 0; i< RTL8367C_LEDGROUPNO; i++)\n    {\n        if((regData & bits[i]) == bits[i])\n        {\n            *groupmask = *groupmask | (1 << i);\n        }\n    }\n\n    return rtl8367c_getAsicRegBits(RTL8367C_LED_FORCE_CTRL, RTL8367C_FORCE_MODE_MASK, pMode);\n}\n/* Function Name:\n *      rtl8367c_setAsicLedBlinkRate\n * Description:\n *      Set led blinking rate at mode 0 to mode 3\n * Input:\n *      blinkRate   - Support 6 blink rates\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_OUT_OF_RANGE - input parameter out of range\n * Note:\n *      LED blink rate can be at 43ms, 84ms, 120ms, 170ms, 340ms and 670ms\n */\nret_t rtl8367c_setAsicLedBlinkRate(rtk_uint32 blinkRate)\n{\n    if(blinkRate >= LEDBLINKRATE_END)\n        return RT_ERR_OUT_OF_RANGE;\n\n    return rtl8367c_setAsicRegBits(RTL8367C_REG_LED_MODE, RTL8367C_SEL_LEDRATE_MASK, blinkRate);\n}\n/* Function Name:\n *      rtl8367c_getAsicLedBlinkRate\n * Description:\n *      Get led blinking rate at mode 0 to mode 3\n * Input:\n *      pBlinkRate  - Support 6 blink rates\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicLedBlinkRate(rtk_uint32* pBlinkRate)\n{\n    return rtl8367c_getAsicRegBits(RTL8367C_REG_LED_MODE, RTL8367C_SEL_LEDRATE_MASK, pBlinkRate);\n}\n/* Function Name:\n *      rtl8367c_setAsicLedForceBlinkRate\n * Description:\n *      Set LEd blinking rate for force mode led\n * Input:\n *      blinkRate   - Support 6 blink rates\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_OUT_OF_RANGE - input parameter out of range\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicLedForceBlinkRate(rtk_uint32 blinkRate)\n{\n    if(blinkRate >= LEDFORCERATE_END)\n        return RT_ERR_OUT_OF_RANGE;\n\n    return rtl8367c_setAsicRegBits(RTL8367C_REG_LED_MODE, RTL8367C_FORCE_RATE_MASK, blinkRate);\n}\n/* Function Name:\n *      rtl8367c_getAsicLedForceBlinkRate\n * Description:\n *      Get LED blinking rate for force mode led\n * Input:\n *      pBlinkRate  - Support 6 blink rates\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicLedForceBlinkRate(rtk_uint32* pBlinkRate)\n{\n     return rtl8367c_getAsicRegBits(RTL8367C_REG_LED_MODE, RTL8367C_FORCE_RATE_MASK, pBlinkRate);\n}\n\n/*\n@func ret_t | rtl8367c_setAsicLedGroupEnable | Turn on/off Led of all system ports\n@parm rtk_uint32 | group | LED group id.\n@parm rtk_uint32 | portmask | LED port mask.\n@rvalue RT_ERR_OK | Success.\n@rvalue RT_ERR_SMI | SMI access error.\n@rvalue RT_ERR_PORT_ID | Invalid port number.\n@rvalue RT_ERR_INPUT | Invalid input value.\n@comm\n    The API can turn on/off leds of dedicated port while indicated information configuration of LED group is set to force mode.\n */\nret_t rtl8367c_setAsicLedGroupEnable(rtk_uint32 group, rtk_uint32 portmask)\n{\n    ret_t retVal;\n    rtk_uint32 regAddr;\n    rtk_uint32 regDataMask;\n\n    if ( group >= RTL8367C_LEDGROUPNO )\n        return RT_ERR_INPUT;\n\n    regAddr = RTL8367C_REG_PARA_LED_IO_EN1 + group/2;\n    regDataMask = 0xFF << ((group%2)*8);\n    retVal = rtl8367c_setAsicRegBits(regAddr, regDataMask, portmask&0xff);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    regAddr = RTL8367C_REG_PARA_LED_IO_EN3;\n    regDataMask = 0x3 << (group*2);\n    retVal = rtl8367c_setAsicRegBits(regAddr, regDataMask, (portmask>>8)&0x7);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n\n    return RT_ERR_OK;\n}\n\n/*\n@func ret_t | rtl8367c_getAsicLedGroupEnable | Get on/off status of Led of all system ports\n@parm rtk_uint32 | group | LED group id.\n@parm rtk_uint32 | *portmask | LED port mask.\n@rvalue RT_ERR_OK | Success.\n@rvalue RT_ERR_SMI | SMI access error.\n@rvalue RT_ERR_PORT_ID | Invalid port number.\n@rvalue RT_ERR_INPUT | Invalid input value.\n@comm\n    The API can turn on/off leds of dedicated port while indicated information configuration of LED group is set to force mode.\n */\nret_t rtl8367c_getAsicLedGroupEnable(rtk_uint32 group, rtk_uint32 *portmask)\n{\n    ret_t retVal;\n    rtk_uint32 regAddr;\n    rtk_uint32 regDataMask,regData;\n\n    if ( group >= RTL8367C_LEDGROUPNO )\n        return RT_ERR_INPUT;\n\n    regAddr = RTL8367C_REG_PARA_LED_IO_EN1 + group/2;\n    regDataMask = 0xFF << ((group%2)*8);\n    retVal = rtl8367c_getAsicRegBits(regAddr, regDataMask, portmask);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n\n    regAddr = RTL8367C_REG_PARA_LED_IO_EN3;\n    regDataMask = 0x3 << (group*2);\n    retVal = rtl8367c_getAsicRegBits(regAddr, regDataMask, &regData);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    *portmask = (regData << 8) | *portmask;\n\n    return RT_ERR_OK;\n}\n\n/*\n@func ret_t | rtl8367c_setAsicLedOperationMode | Set LED operation mode\n@parm rtk_uint32 | mode | LED mode. 1:scan mode 1, 2:parallel mode, 3:mdx mode (serial mode)\n@rvalue RT_ERR_OK | Success.\n@rvalue RT_ERR_SMI | SMI access error.\n@rvalue RT_ERR_INPUT | Invalid input value.\n@comm\n    The API can turn on/off led serial mode and set signal to active high/low.\n */\nret_t rtl8367c_setAsicLedOperationMode(rtk_uint32 mode)\n{\n    ret_t retVal;\n\n    /* Invalid input parameter */\n    if( mode >= LEDOP_END)\n        return RT_ERR_INPUT;\n\n    switch(mode)\n    {\n        case LEDOP_PARALLEL:\n            if((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_LED_SYS_CONFIG, RTL8367C_LED_SELECT_OFFSET, 0))!=  RT_ERR_OK)\n                return retVal;\n            /*Disable serial CLK mode*/\n            if((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_SCAN0_LED_IO_EN1,RTL8367C_LED_SERI_CLK_EN_OFFSET, 0))!=  RT_ERR_OK)\n                return retVal;\n            /*Disable serial DATA mode*/\n            if((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_SCAN0_LED_IO_EN1,RTL8367C_LED_SERI_DATA_EN_OFFSET, 0))!=  RT_ERR_OK)\n                return retVal;\n            break;\n        case LEDOP_SERIAL:\n            if((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_LED_SYS_CONFIG, RTL8367C_LED_SELECT_OFFSET, 1))!=  RT_ERR_OK)\n                return retVal;\n            /*Enable serial CLK mode*/\n            if((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_SCAN0_LED_IO_EN1,RTL8367C_LED_SERI_CLK_EN_OFFSET, 1))!=  RT_ERR_OK)\n                return retVal;\n            /*Enable serial DATA mode*/\n            if((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_SCAN0_LED_IO_EN1,RTL8367C_LED_SERI_DATA_EN_OFFSET, 1))!=  RT_ERR_OK)\n                return retVal;\n            break;\n        default:\n            return RT_ERR_INPUT;\n            break;\n    }\n\n    return RT_ERR_OK;\n}\n\n\n/*\n@func ret_t | rtl8367c_getAsicLedOperationMode | Get LED OP mode setup\n@parm rtk_uint32*| mode | LED mode. 1:scan mode 1, 2:parallel mode, 3:mdx mode (serial mode)\n@rvalue RT_ERR_OK | Success.\n@rvalue RT_ERR_SMI | SMI access error.\n@rvalue RT_ERR_INPUT | Invalid input value.\n@comm\n    The API can get LED serial mode setup and get signal active high/low.\n */\nret_t rtl8367c_getAsicLedOperationMode(rtk_uint32 *mode)\n{\n    ret_t retVal;\n    rtk_uint32 regData;\n\n    if((retVal = rtl8367c_getAsicRegBit(RTL8367C_REG_LED_SYS_CONFIG, RTL8367C_LED_SELECT_OFFSET, &regData))!=  RT_ERR_OK)\n        return retVal;\n\n    if (regData == 1)\n        *mode = LEDOP_SERIAL;\n    else if (regData == 0)\n        *mode = LEDOP_PARALLEL;\n    else\n        return RT_ERR_FAILED;\n\n    return RT_ERR_OK;\n}\n\n/*\n@func ret_t | rtl8367c_setAsicLedSerialModeConfig | Set LED serial mode\n@parm rtk_uint32 | active | Active High or Low.\n@rvalue RT_ERR_OK | Success.\n@rvalue RT_ERR_SMI | SMI access error.\n@rvalue RT_ERR_INPUT | Invalid input value.\n@comm\n    The API can turn on/off led serial mode and set signal to active high/low.\n */\nret_t rtl8367c_setAsicLedSerialModeConfig(rtk_uint32 active, rtk_uint32 serimode)\n{\n    ret_t retVal;\n\n    /* Invalid input parameter */\n    if( active >= LEDSERACT_MAX)\n        return RT_ERR_INPUT;\n    if( serimode >= LEDSER_MAX)\n        return RT_ERR_INPUT;\n\n    /* Set Active High or Low */\n    if((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_LED_SYS_CONFIG, RTL8367C_SERI_LED_ACT_LOW_OFFSET, active)) !=  RT_ERR_OK)\n        return retVal;\n\n    /*set to 8G mode (not 16G mode)*/\n    if((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_LED_MODE, RTL8367C_DLINK_TIME_OFFSET, serimode))!=  RT_ERR_OK)\n        return retVal;\n\n\n    return RT_ERR_OK;\n}\n\n\n/*\n@func ret_t | rtl8367c_getAsicLedSerialModeConfig | Get LED serial mode setup\n@parm rtk_uint32*| active | Active High or Low.\n@rvalue RT_ERR_OK | Success.\n@rvalue RT_ERR_SMI | SMI access error.\n@rvalue RT_ERR_INPUT | Invalid input value.\n@comm\n    The API can get LED serial mode setup and get signal active high/low.\n */\nret_t rtl8367c_getAsicLedSerialModeConfig(rtk_uint32 *active, rtk_uint32 *serimode)\n{\n    ret_t retVal;\n\n    if((retVal = rtl8367c_getAsicRegBit(RTL8367C_REG_LED_SYS_CONFIG, RTL8367C_SERI_LED_ACT_LOW_OFFSET, active))!=  RT_ERR_OK)\n        return retVal;\n\n    /*get to 8G mode (not 16G mode)*/\n    if((retVal = rtl8367c_getAsicRegBit(RTL8367C_REG_LED_MODE, RTL8367C_DLINK_TIME_OFFSET, serimode))!=  RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n\n/*\n@func ret_t | rtl8367c_setAsicLedOutputEnable | Set LED output enable\n@parm rtk_uint32 | enabled | enable or disalbe.\n@rvalue RT_ERR_OK | Success.\n@rvalue RT_ERR_SMI | SMI access error.\n@rvalue RT_ERR_INPUT | Invalid input value.\n@comm\n    The API can turn on/off LED output Enable\n */\nret_t rtl8367c_setAsicLedOutputEnable(rtk_uint32 enabled)\n{\n    ret_t retVal;\n    rtk_uint32 regdata;\n\n    if (enabled == 1)\n        regdata = 0;\n    else\n        regdata = 1;\n\n    /* Enable/Disable H/W IGMP/MLD */\n    retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_LED_SYS_CONFIG, RTL8367C_LED_IO_DISABLE_OFFSET, regdata);\n\n    return retVal;\n}\n\n\n/*\n@func ret_t | rtl8367c_getAsicLedOutputEnable | Get LED serial mode setup\n@parm rtk_uint32*| active | Active High or Low.\n@rvalue RT_ERR_OK | Success.\n@rvalue RT_ERR_SMI | SMI access error.\n@rvalue RT_ERR_INPUT | Invalid input value.\n@comm\n    The API can get LED serial mode setup and get signal active high/low.\n */\nret_t rtl8367c_getAsicLedOutputEnable(rtk_uint32 *ptr_enabled)\n{\n    ret_t retVal;\n    rtk_uint32 regdata;\n\n    retVal = rtl8367c_getAsicRegBit(RTL8367C_REG_LED_SYS_CONFIG, RTL8367C_LED_IO_DISABLE_OFFSET, &regdata);\n    if (retVal != RT_ERR_OK)\n        return retVal;\n\n    if (regdata == 1)\n        *ptr_enabled = 0;\n    else\n        *ptr_enabled = 1;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtl8367c_setAsicLedSerialOutput\n * Description:\n *      Set serial LED output group and portmask.\n * Input:\n *      output      - Serial LED output group\n *      pmask       - Serial LED output portmask\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_OUT_OF_RANGE - input parameter out of range\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicLedSerialOutput(rtk_uint32 output, rtk_uint32 pmask)\n{\n    ret_t retVal;\n\n    retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_SERIAL_LED_CTRL, RTL8367C_SERIAL_LED_GROUP_NUM_MASK, output);\n    if (retVal != RT_ERR_OK)\n        return retVal;\n\n    retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_SERIAL_LED_CTRL, RTL8367C_SERIAL_LED_PORT_EN_MASK, pmask);\n    if (retVal != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtl8367c_getAsicLedSerialOutput\n * Description:\n *      Get serial LED output group and portmask.\n * Input:\n *      None\n * Output:\n *      pOutput      - Serial LED output group\n *      pPmask       - Serial LED output portmask\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_OUT_OF_RANGE - input parameter out of range\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicLedSerialOutput(rtk_uint32 *pOutput, rtk_uint32 *pPmask)\n{\n    ret_t retVal;\n\n    if(pOutput == NULL)\n        return RT_ERR_NULL_POINTER;\n\n    if(pPmask == NULL)\n        return RT_ERR_NULL_POINTER;\n\n    retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_SERIAL_LED_CTRL, RTL8367C_SERIAL_LED_GROUP_NUM_MASK, pOutput);\n    if (retVal != RT_ERR_OK)\n        return retVal;\n\n    retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_SERIAL_LED_CTRL, RTL8367C_SERIAL_LED_PORT_EN_MASK, pPmask);\n    if (retVal != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_lut.c",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * $Revision: 76306 $\n * $Date: 2017-03-08 15:13:58 +0800 (週三, 08 三月 2017) $\n *\n * Purpose : RTL8367C switch high-level API for RTL8367C\n * Feature : LUT related functions\n *\n */\n\n#include <rtl8367c_asicdrv_lut.h>\n\n#include <string.h>\n\nstatic void _rtl8367c_fdbStUser2Smi( rtl8367c_luttb *pLutSt, rtk_uint16 *pFdbSmi)\n{\n    /* L3 lookup */\n    if(pLutSt->l3lookup)\n    {\n        if(pLutSt->l3vidlookup)\n        {\n            pFdbSmi[0] = (pLutSt->sip & 0x0000FFFF);\n            pFdbSmi[1] = (pLutSt->sip & 0xFFFF0000) >> 16;\n\n            pFdbSmi[2] = (pLutSt->dip & 0x0000FFFF);\n            pFdbSmi[3] = (pLutSt->dip & 0x0FFF0000) >> 16;\n\n            pFdbSmi[3] |= (pLutSt->l3lookup & 0x0001) << 12;\n            pFdbSmi[3] |= (pLutSt->l3vidlookup & 0x0001) << 13;\n            pFdbSmi[3] |= ((pLutSt->mbr & 0x0300) >> 8) << 14;\n\n            pFdbSmi[4] |= (pLutSt->mbr & 0x00FF);\n            pFdbSmi[4] |= (pLutSt->l3_vid & 0x00FF) << 8;\n\n            pFdbSmi[5] |= ((pLutSt->l3_vid & 0x0F00) >> 8);\n            pFdbSmi[5] |= (pLutSt->nosalearn & 0x0001) << 5;\n            pFdbSmi[5] |= ((pLutSt->mbr & 0x0400) >> 10) << 7;\n        }\n        else\n        {\n            pFdbSmi[0] = (pLutSt->sip & 0x0000FFFF);\n            pFdbSmi[1] = (pLutSt->sip & 0xFFFF0000) >> 16;\n\n            pFdbSmi[2] = (pLutSt->dip & 0x0000FFFF);\n            pFdbSmi[3] = (pLutSt->dip & 0x0FFF0000) >> 16;\n\n            pFdbSmi[3] |= (pLutSt->l3lookup & 0x0001) << 12;\n            pFdbSmi[3] |= (pLutSt->l3vidlookup & 0x0001) << 13;\n            pFdbSmi[3] |= ((pLutSt->mbr & 0x0300) >> 8) << 14;\n\n            pFdbSmi[4] |= (pLutSt->mbr & 0x00FF);\n            pFdbSmi[4] |= (pLutSt->igmpidx & 0x00FF) << 8;\n\n            pFdbSmi[5] |= (pLutSt->igmp_asic & 0x0001);\n            pFdbSmi[5] |= (pLutSt->lut_pri & 0x0007) << 1;\n            pFdbSmi[5] |= (pLutSt->fwd_en & 0x0001) << 4;\n            pFdbSmi[5] |= (pLutSt->nosalearn & 0x0001) << 5;\n            pFdbSmi[5] |= ((pLutSt->mbr & 0x0400) >> 10) << 7;\n        }\n    }\n    else if(pLutSt->mac.octet[0] & 0x01) /*Multicast L2 Lookup*/\n    {\n        pFdbSmi[0] |= pLutSt->mac.octet[5];\n        pFdbSmi[0] |= pLutSt->mac.octet[4] << 8;\n\n        pFdbSmi[1] |= pLutSt->mac.octet[3];\n        pFdbSmi[1] |= pLutSt->mac.octet[2] << 8;\n\n        pFdbSmi[2] |= pLutSt->mac.octet[1];\n        pFdbSmi[2] |= pLutSt->mac.octet[0] << 8;\n\n        pFdbSmi[3] |= pLutSt->cvid_fid;\n        pFdbSmi[3] |= (pLutSt->l3lookup & 0x0001) << 12;\n        pFdbSmi[3] |= (pLutSt->ivl_svl & 0x0001) << 13;\n        pFdbSmi[3] |= ((pLutSt->mbr & 0x0300) >> 8) << 14;\n\n        pFdbSmi[4] |= (pLutSt->mbr & 0x00FF);\n        pFdbSmi[4] |= (pLutSt->igmpidx & 0x00FF) << 8;\n\n        pFdbSmi[5] |= pLutSt->igmp_asic;\n        pFdbSmi[5] |= (pLutSt->lut_pri & 0x0007) << 1;\n        pFdbSmi[5] |= (pLutSt->fwd_en & 0x0001) << 4;\n        pFdbSmi[5] |= (pLutSt->nosalearn & 0x0001) << 5;\n        pFdbSmi[5] |= ((pLutSt->mbr & 0x0400) >> 10) << 7;\n    }\n    else /*Asic auto-learning*/\n    {\n        pFdbSmi[0] |= pLutSt->mac.octet[5];\n        pFdbSmi[0] |= pLutSt->mac.octet[4] << 8;\n\n        pFdbSmi[1] |= pLutSt->mac.octet[3];\n        pFdbSmi[1] |= pLutSt->mac.octet[2] << 8;\n\n        pFdbSmi[2] |= pLutSt->mac.octet[1];\n        pFdbSmi[2] |= pLutSt->mac.octet[0] << 8;\n\n        pFdbSmi[3] |= pLutSt->cvid_fid;\n        pFdbSmi[3] |= (pLutSt->l3lookup & 0x0001) << 12;\n        pFdbSmi[3] |= (pLutSt->ivl_svl & 0x0001) << 13;\n        pFdbSmi[3] |= ((pLutSt->spa & 0x0008) >> 3) << 15;\n\n        pFdbSmi[4] |= pLutSt->efid;\n        pFdbSmi[4] |= (pLutSt->fid & 0x000F) << 3;\n        pFdbSmi[4] |= (pLutSt->sa_en & 0x0001) << 7;\n        pFdbSmi[4] |= (pLutSt->spa & 0x0007) << 8;\n        pFdbSmi[4] |= (pLutSt->age & 0x0007) << 11;\n        pFdbSmi[4] |= (pLutSt->auth & 0x0001) << 14;\n        pFdbSmi[4] |= (pLutSt->sa_block & 0x0001) << 15;\n\n        pFdbSmi[5] |= pLutSt->da_block;\n        pFdbSmi[5] |= (pLutSt->lut_pri & 0x0007) << 1;\n        pFdbSmi[5] |= (pLutSt->fwd_en & 0x0001) << 4;\n        pFdbSmi[5] |= (pLutSt->nosalearn & 0x0001) << 5;\n    }\n}\n\n\nstatic void _rtl8367c_fdbStSmi2User( rtl8367c_luttb *pLutSt, rtk_uint16 *pFdbSmi)\n{\n    /*L3 lookup*/\n    if(pFdbSmi[3] & 0x1000)\n    {\n        if(pFdbSmi[3] & 0x2000)\n        {\n            pLutSt->sip             = pFdbSmi[0] | (pFdbSmi[1] << 16);\n            pLutSt->dip             = pFdbSmi[2] | ((pFdbSmi[3] & 0x0FFF) << 16);\n\n            pLutSt->mbr             = (pFdbSmi[4] & 0x00FF) | (((pFdbSmi[3] & 0xC000) >> 14) << 8) | (((pFdbSmi[5] & 0x0080) >> 7) << 10);\n            pLutSt->l3_vid          = ((pFdbSmi[4] & 0xFF00) >> 8) | (pFdbSmi[5] & 0x000F);\n\n            pLutSt->l3lookup        = (pFdbSmi[3] & 0x1000) >> 12;\n            pLutSt->l3vidlookup     = (pFdbSmi[3] & 0x2000) >> 13;\n            pLutSt->nosalearn       = (pFdbSmi[5] & 0x0020) >> 5;\n        }\n        else\n        {\n            pLutSt->sip             = pFdbSmi[0] | (pFdbSmi[1] << 16);\n            pLutSt->dip             = pFdbSmi[2] | ((pFdbSmi[3] & 0x0FFF) << 16);\n\n            pLutSt->lut_pri         = (pFdbSmi[5] & 0x000E) >> 1;\n            pLutSt->fwd_en          = (pFdbSmi[5] & 0x0010) >> 4;\n\n            pLutSt->mbr             = (pFdbSmi[4] & 0x00FF) | (((pFdbSmi[3] & 0xC000) >> 14) << 8) | (((pFdbSmi[5] & 0x0080) >> 7) << 10);\n            pLutSt->igmpidx         = (pFdbSmi[4] & 0xFF00) >> 8;\n\n            pLutSt->igmp_asic       = (pFdbSmi[5] & 0x0001);\n            pLutSt->l3lookup        = (pFdbSmi[3] & 0x1000) >> 12;\n            pLutSt->nosalearn       = (pFdbSmi[5] & 0x0020) >> 5;\n        }\n    }\n    else if(pFdbSmi[2] & 0x0100) /*Multicast L2 Lookup*/\n    {\n        pLutSt->mac.octet[0]    = (pFdbSmi[2] & 0xFF00) >> 8;\n        pLutSt->mac.octet[1]    = (pFdbSmi[2] & 0x00FF);\n        pLutSt->mac.octet[2]    = (pFdbSmi[1] & 0xFF00) >> 8;\n        pLutSt->mac.octet[3]    = (pFdbSmi[1] & 0x00FF);\n        pLutSt->mac.octet[4]    = (pFdbSmi[0] & 0xFF00) >> 8;\n        pLutSt->mac.octet[5]    = (pFdbSmi[0] & 0x00FF);\n\n        pLutSt->cvid_fid        = pFdbSmi[3] & 0x0FFF;\n        pLutSt->lut_pri         = (pFdbSmi[5] & 0x000E) >> 1;\n        pLutSt->fwd_en          = (pFdbSmi[5] & 0x0010) >> 4;\n\n        pLutSt->mbr             = (pFdbSmi[4] & 0x00FF) | (((pFdbSmi[3] & 0xC000) >> 14) << 8) | (((pFdbSmi[5] & 0x0080) >> 7) << 10);\n        pLutSt->igmpidx         = (pFdbSmi[4] & 0xFF00) >> 8;\n\n        pLutSt->igmp_asic       = (pFdbSmi[5] & 0x0001);\n        pLutSt->l3lookup        = (pFdbSmi[3] & 0x1000) >> 12;\n        pLutSt->ivl_svl         = (pFdbSmi[3] & 0x2000) >> 13;\n        pLutSt->nosalearn       = (pFdbSmi[5] & 0x0020) >> 5;\n    }\n    else /*Asic auto-learning*/\n    {\n        pLutSt->mac.octet[0]    = (pFdbSmi[2] & 0xFF00) >> 8;\n        pLutSt->mac.octet[1]    = (pFdbSmi[2] & 0x00FF);\n        pLutSt->mac.octet[2]    = (pFdbSmi[1] & 0xFF00) >> 8;\n        pLutSt->mac.octet[3]    = (pFdbSmi[1] & 0x00FF);\n        pLutSt->mac.octet[4]    = (pFdbSmi[0] & 0xFF00) >> 8;\n        pLutSt->mac.octet[5]    = (pFdbSmi[0] & 0x00FF);\n\n        pLutSt->cvid_fid        = pFdbSmi[3] & 0x0FFF;\n        pLutSt->lut_pri         = (pFdbSmi[5] & 0x000E) >> 1;\n        pLutSt->fwd_en          = (pFdbSmi[5] & 0x0010) >> 4;\n\n        pLutSt->sa_en           = (pFdbSmi[4] & 0x0080) >> 7;\n        pLutSt->auth            = (pFdbSmi[4] & 0x4000) >> 14;\n        pLutSt->spa             = ((pFdbSmi[4] & 0x0700) >> 8) | (((pFdbSmi[3] & 0x8000) >> 15) << 3);\n        pLutSt->age             = (pFdbSmi[4] & 0x3800) >> 11;\n        pLutSt->fid             = (pFdbSmi[4] & 0x0078) >> 3;\n        pLutSt->efid            = (pFdbSmi[4] & 0x0007);\n        pLutSt->sa_block        = (pFdbSmi[4] & 0x8000) >> 15;\n\n        pLutSt->da_block        = (pFdbSmi[5] & 0x0001);\n        pLutSt->l3lookup        = (pFdbSmi[3] & 0x1000) >> 12;\n        pLutSt->ivl_svl         = (pFdbSmi[3] & 0x2000) >> 13;\n        pLutSt->nosalearn       = (pFdbSmi[3] & 0x0020) >> 5;\n    }\n}\n\n/* Function Name:\n *      rtl8367c_setAsicLutIpMulticastLookup\n * Description:\n *      Set Lut IP multicast lookup function\n * Input:\n *      enabled - 1: enabled, 0: disabled\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicLutIpMulticastLookup(rtk_uint32 enabled)\n{\n    return rtl8367c_setAsicRegBit(RTL8367C_REG_LUT_CFG, RTL8367C_LUT_IPMC_HASH_OFFSET, enabled);\n}\n/* Function Name:\n *      rtl8367c_getAsicLutIpMulticastLookup\n * Description:\n *      Get Lut IP multicast lookup function\n * Input:\n *      pEnabled - 1: enabled, 0: disabled\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicLutIpMulticastLookup(rtk_uint32* pEnabled)\n{\n    return rtl8367c_getAsicRegBit(RTL8367C_REG_LUT_CFG, RTL8367C_LUT_IPMC_HASH_OFFSET, pEnabled);\n}\n\n/* Function Name:\n *      rtl8367c_setAsicLutIpMulticastLookup\n * Description:\n *      Set Lut IP multicast + VID lookup function\n * Input:\n *      enabled - 1: enabled, 0: disabled\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicLutIpMulticastVidLookup(rtk_uint32 enabled)\n{\n    return rtl8367c_setAsicRegBit(RTL8367C_REG_LUT_CFG2, RTL8367C_LUT_IPMC_VID_HASH_OFFSET, enabled);\n}\n\n/* Function Name:\n *      rtl8367c_getAsicLutIpMulticastVidLookup\n * Description:\n *      Get Lut IP multicast lookup function\n * Input:\n *      pEnabled - 1: enabled, 0: disabled\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicLutIpMulticastVidLookup(rtk_uint32* pEnabled)\n{\n    return rtl8367c_getAsicRegBit(RTL8367C_REG_LUT_CFG2, RTL8367C_LUT_IPMC_VID_HASH_OFFSET, pEnabled);\n}\n\n/* Function Name:\n *      rtl8367c_setAsicLutIpLookupMethod\n * Description:\n *      Set Lut IP lookup hash with DIP or {DIP,SIP} pair\n * Input:\n *      type - 1: When DIP can be found in IPMC_GROUP_TABLE, use DIP+SIP Hash, otherwise, use DIP+(SIP=0.0.0.0) Hash.\n *             0: When DIP can be found in IPMC_GROUP_TABLE, use DIP+(SIP=0.0.0.0) Hash, otherwise use DIP+SIP Hash.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicLutIpLookupMethod(rtk_uint32 type)\n{\n    return rtl8367c_setAsicRegBit(RTL8367C_REG_LUT_CFG, RTL8367C_LUT_IPMC_LOOKUP_OP_OFFSET, type);\n}\n/* Function Name:\n *      rtl8367c_getAsicLutIpLookupMethod\n * Description:\n *      Get Lut IP lookup hash with DIP or {DIP,SIP} pair\n * Input:\n *      pType - 1: When DIP can be found in IPMC_GROUP_TABLE, use DIP+SIP Hash, otherwise, use DIP+(SIP=0.0.0.0) Hash.\n *              0: When DIP can be found in IPMC_GROUP_TABLE, use DIP+(SIP=0.0.0.0) Hash, otherwise use DIP+SIP Hash.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicLutIpLookupMethod(rtk_uint32* pType)\n{\n    return rtl8367c_getAsicRegBit(RTL8367C_REG_LUT_CFG, RTL8367C_LUT_IPMC_LOOKUP_OP_OFFSET, pType);\n}\n/* Function Name:\n *      rtl8367c_setAsicLutAgeTimerSpeed\n * Description:\n *      Set LUT agging out speed\n * Input:\n *      timer - Agging out timer 0:Has been aged out\n *      speed - Agging out speed 0-fastest 3-slowest\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_OUT_OF_RANGE - input parameter out of range\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicLutAgeTimerSpeed(rtk_uint32 timer, rtk_uint32 speed)\n{\n    if(timer>RTL8367C_LUT_AGETIMERMAX)\n        return RT_ERR_OUT_OF_RANGE;\n\n    if(speed >RTL8367C_LUT_AGESPEEDMAX)\n        return RT_ERR_OUT_OF_RANGE;\n\n    return rtl8367c_setAsicRegBits(RTL8367C_REG_LUT_CFG, RTL8367C_AGE_TIMER_MASK | RTL8367C_AGE_SPEED_MASK, (timer << RTL8367C_AGE_TIMER_OFFSET) | (speed << RTL8367C_AGE_SPEED_OFFSET));\n}\n/* Function Name:\n *      rtl8367c_getAsicLutAgeTimerSpeed\n * Description:\n *      Get LUT agging out speed\n * Input:\n *      pTimer - Agging out timer 0:Has been aged out\n *      pSpeed - Agging out speed 0-fastest 3-slowest\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_OUT_OF_RANGE - input parameter out of range\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicLutAgeTimerSpeed(rtk_uint32* pTimer, rtk_uint32* pSpeed)\n{\n    rtk_uint32 regData;\n    ret_t retVal;\n\n    retVal = rtl8367c_getAsicReg(RTL8367C_REG_LUT_CFG, &regData);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    *pTimer =  (regData & RTL8367C_AGE_TIMER_MASK) >> RTL8367C_AGE_TIMER_OFFSET;\n\n    *pSpeed =  (regData & RTL8367C_AGE_SPEED_MASK) >> RTL8367C_AGE_SPEED_OFFSET;\n\n    return RT_ERR_OK;\n\n}\n/* Function Name:\n *      rtl8367c_setAsicLutCamTbUsage\n * Description:\n *      Configure Lut CAM table usage\n * Input:\n *      enabled - L2 CAM table usage 1: enabled, 0: disabled\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicLutCamTbUsage(rtk_uint32 enabled)\n{\n    ret_t retVal;\n\n    retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_LUT_CFG, RTL8367C_BCAM_DISABLE_OFFSET, enabled ? 0 : 1);\n\n    return retVal;\n}\n/* Function Name:\n *      rtl8367c_getAsicLutCamTbUsage\n * Description:\n *      Get Lut CAM table usage\n * Input:\n *      pEnabled - L2 CAM table usage 1: enabled, 0: disabled\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicLutCamTbUsage(rtk_uint32* pEnabled)\n{\n    ret_t       retVal;\n    rtk_uint32  regData;\n\n    if ((retVal = rtl8367c_getAsicRegBit(RTL8367C_REG_LUT_CFG, RTL8367C_BCAM_DISABLE_OFFSET, &regData)) != RT_ERR_OK)\n        return retVal;\n\n    *pEnabled = regData ? 0 : 1;\n    return RT_ERR_OK;\n}\n/* Function Name:\n *      rtl8367c_setAsicLutLearnLimitNo\n * Description:\n *      Set per-Port auto learning limit number\n * Input:\n *      port    - Physical port number (0~7)\n *      number  - ASIC auto learning entries limit number\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK                   - Success\n *      RT_ERR_SMI                  - SMI access error\n *      RT_ERR_PORT_ID              - Invalid port number\n *      RT_ERR_LIMITED_L2ENTRY_NUM  - Invalid auto learning limit number\n * Note:\n *      None\n */\n   /*޸: RTL8367C_PORTIDMAX, RTL8367C_LUT_LEARNLIMITMAX, RTL8367C_LUT_PORT_LEARN_LIMITNO_REG*/\nret_t rtl8367c_setAsicLutLearnLimitNo(rtk_uint32 port, rtk_uint32 number)\n{\n    if(port > RTL8367C_PORTIDMAX)\n        return RT_ERR_PORT_ID;\n\n    if(number > RTL8367C_LUT_LEARNLIMITMAX)\n        return RT_ERR_LIMITED_L2ENTRY_NUM;\n\n    if(port < 8)\n     return rtl8367c_setAsicReg(RTL8367C_LUT_PORT_LEARN_LIMITNO_REG(port), number);\n    else\n        return rtl8367c_setAsicReg(RTL8367C_REG_LUT_PORT8_LEARN_LIMITNO+port-8, number);\n\n}\n/* Function Name:\n *      rtl8367c_getAsicLutLearnLimitNo\n * Description:\n *      Get per-Port auto learning limit number\n * Input:\n *      port    - Physical port number (0~7)\n *      pNumber     - ASIC auto learning entries limit number\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n *      RT_ERR_PORT_ID  - Invalid port number\n * Note:\n *      None\n */\n  /*޸: RTL8367C_PORTIDMAX, RTL8367C_LUT_PORT_LEARN_LIMITNO_REG*/\nret_t rtl8367c_getAsicLutLearnLimitNo(rtk_uint32 port, rtk_uint32* pNumber)\n{\n    if(port > RTL8367C_PORTIDMAX)\n        return RT_ERR_PORT_ID;\n\n    if(port < 8)\n     return rtl8367c_getAsicReg(RTL8367C_LUT_PORT_LEARN_LIMITNO_REG(port), pNumber);\n    else\n        return rtl8367c_getAsicReg(RTL8367C_REG_LUT_PORT8_LEARN_LIMITNO+port-8, pNumber);\n}\n\n/* Function Name:\n *      rtl8367c_setAsicSystemLutLearnLimitNo\n * Description:\n *      Set system auto learning limit number\n * Input:\n *      number  - ASIC auto learning entries limit number\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK                   - Success\n *      RT_ERR_SMI                  - SMI access error\n *      RT_ERR_PORT_ID              - Invalid port number\n *      RT_ERR_LIMITED_L2ENTRY_NUM  - Invalid auto learning limit number\n * Note:\n *      None\n */\n  /*޸: RTL8367C_LUT_LEARNLIMITMAX*/\nret_t rtl8367c_setAsicSystemLutLearnLimitNo(rtk_uint32 number)\n{\n    if(number > RTL8367C_LUT_LEARNLIMITMAX)\n        return RT_ERR_LIMITED_L2ENTRY_NUM;\n\n    return rtl8367c_setAsicReg(RTL8367C_REG_LUT_SYS_LEARN_LIMITNO, number);\n}\n\n/* Function Name:\n *      rtl8367c_getAsicSystemLutLearnLimitNo\n * Description:\n *      Get system auto learning limit number\n * Input:\n *      port    - Physical port number (0~7)\n *      pNumber     - ASIC auto learning entries limit number\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n *      RT_ERR_PORT_ID  - Invalid port number\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicSystemLutLearnLimitNo(rtk_uint32 *pNumber)\n{\n    if(NULL == pNumber)\n        return RT_ERR_NULL_POINTER;\n\n    return rtl8367c_getAsicReg(RTL8367C_REG_LUT_SYS_LEARN_LIMITNO, pNumber);\n}\n\n/* Function Name:\n *      rtl8367c_setAsicLutLearnOverAct\n * Description:\n *      Set auto learn over limit number action\n * Input:\n *      action  - Learn over action 0:normal, 1:drop 2:trap\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_NOT_ALLOWED  - Invalid learn over action\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicLutLearnOverAct(rtk_uint32 action)\n{\n    if(action >= LRNOVERACT_END)\n        return RT_ERR_NOT_ALLOWED;\n\n    return rtl8367c_setAsicRegBits(RTL8367C_REG_PORT_SECURITY_CTRL, RTL8367C_LUT_LEARN_OVER_ACT_MASK, action);\n}\n/* Function Name:\n *      rtl8367c_getAsicLutLearnOverAct\n * Description:\n *      Get auto learn over limit number action\n * Input:\n *      pAction     - Learn over action 0:normal, 1:drop 2:trap\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicLutLearnOverAct(rtk_uint32* pAction)\n{\n    return rtl8367c_getAsicRegBits(RTL8367C_REG_PORT_SECURITY_CTRL, RTL8367C_LUT_LEARN_OVER_ACT_MASK, pAction);\n}\n\n/* Function Name:\n *      rtl8367c_setAsicSystemLutLearnOverAct\n * Description:\n *      Set system auto learn over limit number action\n * Input:\n *      action  - Learn over action 0:normal, 1:drop, 2:trap\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_NOT_ALLOWED  - Invalid learn over action\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicSystemLutLearnOverAct(rtk_uint32 action)\n{\n    if(action >= LRNOVERACT_END)\n        return RT_ERR_NOT_ALLOWED;\n\n    return rtl8367c_setAsicRegBits(RTL8367C_REG_LUT_LRN_SYS_LMT_CTRL, RTL8367C_LUT_SYSTEM_LEARN_OVER_ACT_MASK, action);\n}\n\n/* Function Name:\n *      rtl8367c_getAsicSystemLutLearnOverAct\n * Description:\n *      Get system auto learn over limit number action\n * Input:\n *      pAction     - Learn over action 0:normal, 1:drop 2:trap\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicSystemLutLearnOverAct(rtk_uint32 *pAction)\n{\n    if(NULL == pAction)\n        return RT_ERR_NULL_POINTER;\n\n    return rtl8367c_getAsicRegBits(RTL8367C_REG_LUT_LRN_SYS_LMT_CTRL, RTL8367C_LUT_SYSTEM_LEARN_OVER_ACT_MASK, pAction);\n}\n\n/* Function Name:\n *      rtl8367c_setAsicSystemLutLearnPortMask\n * Description:\n *      Set system auto learn limit port mask\n * Input:\n *      portmask    - port mask of system learning limit\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_MASK    - Error port mask\n * Note:\n *      None\n */\n  /*޸: RTL8367C_LUT_SYSTEM_LEARN_PMASK_MASK*/\nret_t rtl8367c_setAsicSystemLutLearnPortMask(rtk_uint32 portmask)\n{\n    ret_t retVal;\n\n    if(portmask > RTL8367C_PORTMASK)\n        return RT_ERR_PORT_MASK;\n\n    retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_LUT_LRN_SYS_LMT_CTRL, RTL8367C_LUT_SYSTEM_LEARN_PMASK_MASK, portmask & 0xff);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n    retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_LUT_LRN_SYS_LMT_CTRL, RTL8367C_LUT_SYSTEM_LEARN_PMASK1_MASK, (portmask>>8) & 0x7);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n\n}\n\n/* Function Name:\n *      rtl8367c_getAsicSystemLutLearnPortMask\n * Description:\n *      Get system auto learn limit port mask\n * Input:\n *      None\n * Output:\n *      pPortmask   - port mask of system learning limit\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_NULL_POINTER - NULL pointer\n * Note:\n *      None\n */\n /*޸: RTL8367C_LUT_SYSTEM_LEARN_PMASK_MASK*/\nret_t rtl8367c_getAsicSystemLutLearnPortMask(rtk_uint32 *pPortmask)\n{\n    rtk_uint32 tmpmask;\n    ret_t retVal;\n\n    if(NULL == pPortmask)\n        return RT_ERR_NULL_POINTER;\n\n    retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_LUT_LRN_SYS_LMT_CTRL, RTL8367C_LUT_SYSTEM_LEARN_PMASK_MASK, &tmpmask);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n    *pPortmask = tmpmask & 0xff;\n    retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_LUT_LRN_SYS_LMT_CTRL, RTL8367C_LUT_SYSTEM_LEARN_PMASK1_MASK, &tmpmask);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n    *pPortmask |= (tmpmask & 0x7) << 8;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtl8367c_setAsicL2LookupTb\n * Description:\n *      Set filtering database entry\n * Input:\n *      pL2Table    - L2 table entry writing to 8K+64 filtering database\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicL2LookupTb(rtl8367c_luttb *pL2Table)\n{\n    ret_t retVal;\n    rtk_uint32 regData;\n    rtk_uint16 *accessPtr;\n    rtk_uint32 i;\n    rtk_uint16 smil2Table[RTL8367C_LUT_TABLE_SIZE];\n    rtk_uint32 tblCmd;\n    rtk_uint32 busyCounter;\n\n    memset(smil2Table, 0x00, sizeof(rtk_uint16) * RTL8367C_LUT_TABLE_SIZE);\n    _rtl8367c_fdbStUser2Smi(pL2Table, smil2Table);\n\n    if(pL2Table->wait_time == 0)\n        busyCounter = RTL8367C_LUT_BUSY_CHECK_NO;\n    else\n        busyCounter = pL2Table->wait_time;\n\n    while(busyCounter)\n    {\n        retVal = rtl8367c_getAsicRegBit(RTL8367C_TABLE_ACCESS_STATUS_REG, RTL8367C_TABLE_LUT_ADDR_BUSY_FLAG_OFFSET,&regData);\n        if(retVal != RT_ERR_OK)\n            return retVal;\n\n        pL2Table->lookup_busy = regData;\n        if(!regData)\n            break;\n\n        busyCounter --;\n        if(busyCounter == 0)\n            return RT_ERR_BUSYWAIT_TIMEOUT;\n    }\n\n    accessPtr = smil2Table;\n    regData = *accessPtr;\n    for(i = 0; i < RTL8367C_LUT_ENTRY_SIZE; i++)\n    {\n        retVal = rtl8367c_setAsicReg(RTL8367C_TABLE_ACCESS_WRDATA_BASE + i, regData);\n        if(retVal != RT_ERR_OK)\n            return retVal;\n\n        accessPtr ++;\n        regData = *accessPtr;\n\n    }\n\n    tblCmd = (RTL8367C_TABLE_ACCESS_REG_DATA(TB_OP_WRITE,TB_TARGET_L2)) & (RTL8367C_TABLE_TYPE_MASK  | RTL8367C_COMMAND_TYPE_MASK);\n    /* Write Command */\n    retVal = rtl8367c_setAsicReg(RTL8367C_TABLE_ACCESS_CTRL_REG, tblCmd);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    if(pL2Table->wait_time == 0)\n        busyCounter = RTL8367C_LUT_BUSY_CHECK_NO;\n    else\n        busyCounter = pL2Table->wait_time;\n\n    while(busyCounter)\n    {\n        retVal = rtl8367c_getAsicRegBit(RTL8367C_TABLE_ACCESS_STATUS_REG, RTL8367C_TABLE_LUT_ADDR_BUSY_FLAG_OFFSET,&regData);\n        if(retVal != RT_ERR_OK)\n            return retVal;\n\n        pL2Table->lookup_busy = regData;\n        if(!regData)\n            break;\n\n        busyCounter --;\n        if(busyCounter == 0)\n            return RT_ERR_BUSYWAIT_TIMEOUT;\n    }\n\n    /*Read access status*/\n    retVal = rtl8367c_getAsicRegBit(RTL8367C_TABLE_ACCESS_STATUS_REG, RTL8367C_HIT_STATUS_OFFSET, &regData);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    pL2Table->lookup_hit = regData;\n    if(!pL2Table->lookup_hit)\n        return RT_ERR_FAILED;\n\n    /*Read access address*/\n    /*\n    retVal = rtl8367c_getAsicRegBits(RTL8367C_TABLE_ACCESS_STATUS_REG, RTL8367C_TABLE_LUT_ADDR_TYPE_MASK | RTL8367C_TABLE_LUT_ADDR_ADDRESS_MASK,&regData);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    pL2Table->address = regData;*/\n\n    retVal = rtl8367c_getAsicReg(RTL8367C_TABLE_ACCESS_STATUS_REG, &regData);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    pL2Table->address = (regData & 0x7ff) | ((regData & 0x4000) >> 3) | ((regData & 0x800) << 1);\n    pL2Table->lookup_busy = 0;\n\n    return RT_ERR_OK;\n}\n/* Function Name:\n *      rtl8367c_getAsicL2LookupTb\n * Description:\n *      Get filtering database entry\n * Input:\n *      pL2Table    - L2 table entry writing to 2K+64 filtering database\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - Success\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_INPUT            - Invalid input parameter\n *      RT_ERR_BUSYWAIT_TIMEOUT - LUT is busy at retrieving\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicL2LookupTb(rtk_uint32 method, rtl8367c_luttb *pL2Table)\n{\n    ret_t retVal;\n    rtk_uint32 regData;\n    rtk_uint16* accessPtr;\n    rtk_uint32 i;\n    rtk_uint16 smil2Table[RTL8367C_LUT_TABLE_SIZE];\n    rtk_uint32 busyCounter;\n    rtk_uint32 tblCmd;\n\n    if(pL2Table->wait_time == 0)\n        busyCounter = RTL8367C_LUT_BUSY_CHECK_NO;\n    else\n        busyCounter = pL2Table->wait_time;\n\n    while(busyCounter)\n    {\n        retVal = rtl8367c_getAsicRegBit(RTL8367C_TABLE_ACCESS_STATUS_REG, RTL8367C_TABLE_LUT_ADDR_BUSY_FLAG_OFFSET,&regData);\n        if(retVal != RT_ERR_OK)\n            return retVal;\n\n        pL2Table->lookup_busy = regData;\n        if(!pL2Table->lookup_busy)\n            break;\n\n        busyCounter --;\n        if(busyCounter == 0)\n            return RT_ERR_BUSYWAIT_TIMEOUT;\n    }\n\n\n    tblCmd = (method << RTL8367C_ACCESS_METHOD_OFFSET) & RTL8367C_ACCESS_METHOD_MASK;\n\n    switch(method)\n    {\n        case LUTREADMETHOD_ADDRESS:\n        case LUTREADMETHOD_NEXT_ADDRESS:\n        case LUTREADMETHOD_NEXT_L2UC:\n        case LUTREADMETHOD_NEXT_L2MC:\n        case LUTREADMETHOD_NEXT_L3MC:\n        case LUTREADMETHOD_NEXT_L2L3MC:\n            retVal = rtl8367c_setAsicReg(RTL8367C_TABLE_ACCESS_ADDR_REG, pL2Table->address);\n            if(retVal != RT_ERR_OK)\n                return retVal;\n            break;\n        case LUTREADMETHOD_MAC:\n            memset(smil2Table, 0x00, sizeof(rtk_uint16) * RTL8367C_LUT_TABLE_SIZE);\n            _rtl8367c_fdbStUser2Smi(pL2Table, smil2Table);\n\n            accessPtr = smil2Table;\n            regData = *accessPtr;\n            for(i=0; i<RTL8367C_LUT_ENTRY_SIZE; i++)\n            {\n                retVal = rtl8367c_setAsicReg(RTL8367C_TABLE_ACCESS_WRDATA_BASE + i, regData);\n                if(retVal != RT_ERR_OK)\n                    return retVal;\n\n                accessPtr ++;\n                regData = *accessPtr;\n\n            }\n            break;\n        case LUTREADMETHOD_NEXT_L2UCSPA:\n            retVal = rtl8367c_setAsicReg(RTL8367C_TABLE_ACCESS_ADDR_REG, pL2Table->address);\n            if(retVal != RT_ERR_OK)\n                return retVal;\n\n            tblCmd = tblCmd | ((pL2Table->spa << RTL8367C_TABLE_ACCESS_CTRL_SPA_OFFSET) & RTL8367C_TABLE_ACCESS_CTRL_SPA_MASK);\n\n            break;\n        default:\n            return RT_ERR_INPUT;\n    }\n\n    tblCmd = tblCmd | ((RTL8367C_TABLE_ACCESS_REG_DATA(TB_OP_READ,TB_TARGET_L2)) & (RTL8367C_TABLE_TYPE_MASK  | RTL8367C_COMMAND_TYPE_MASK));\n    /* Read Command */\n    retVal = rtl8367c_setAsicReg(RTL8367C_TABLE_ACCESS_CTRL_REG, tblCmd);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    if(pL2Table->wait_time == 0)\n        busyCounter = RTL8367C_LUT_BUSY_CHECK_NO;\n    else\n        busyCounter = pL2Table->wait_time;\n\n    while(busyCounter)\n    {\n        retVal = rtl8367c_getAsicRegBit(RTL8367C_TABLE_ACCESS_STATUS_REG, RTL8367C_TABLE_LUT_ADDR_BUSY_FLAG_OFFSET,&regData);\n        if(retVal != RT_ERR_OK)\n            return retVal;\n\n        pL2Table->lookup_busy = regData;\n        if(!pL2Table->lookup_busy)\n            break;\n\n        busyCounter --;\n        if(busyCounter == 0)\n            return RT_ERR_BUSYWAIT_TIMEOUT;\n    }\n\n    retVal = rtl8367c_getAsicRegBit(RTL8367C_TABLE_ACCESS_STATUS_REG, RTL8367C_HIT_STATUS_OFFSET,&regData);\n    if(retVal != RT_ERR_OK)\n            return retVal;\n    pL2Table->lookup_hit = regData;\n    if(!pL2Table->lookup_hit)\n        return RT_ERR_L2_ENTRY_NOTFOUND;\n\n    /*Read access address*/\n    //retVal = rtl8367c_getAsicRegBits(RTL8367C_TABLE_ACCESS_STATUS_REG, RTL8367C_TABLE_LUT_ADDR_TYPE_MASK | RTL8367C_TABLE_LUT_ADDR_ADDRESS_MASK,&regData);\n    retVal = rtl8367c_getAsicReg(RTL8367C_TABLE_ACCESS_STATUS_REG, &regData);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    pL2Table->address = (regData & 0x7ff) | ((regData & 0x4000) >> 3) | ((regData & 0x800) << 1);\n\n    /*read L2 entry */\n    memset(smil2Table, 0x00, sizeof(rtk_uint16) * RTL8367C_LUT_TABLE_SIZE);\n\n    accessPtr = smil2Table;\n\n    for(i = 0; i < RTL8367C_LUT_ENTRY_SIZE; i++)\n    {\n        retVal = rtl8367c_getAsicReg(RTL8367C_TABLE_ACCESS_RDDATA_BASE + i, &regData);\n        if(retVal != RT_ERR_OK)\n            return retVal;\n\n        *accessPtr = regData;\n\n        accessPtr ++;\n    }\n\n    _rtl8367c_fdbStSmi2User(pL2Table, smil2Table);\n\n    return RT_ERR_OK;\n}\n/* Function Name:\n *      rtl8367c_getAsicLutLearnNo\n * Description:\n *      Get per-Port auto learning number\n * Input:\n *      port    - Physical port number (0~7)\n *      pNumber     - ASIC auto learning entries number\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n *      RT_ERR_PORT_ID  - Invalid port number\n * Note:\n *      None\n */\n /*޸RTL8367C_PORTIDMAX, RTL8367C_REG_L2_LRN_CNT_REG, port10 reg is not contnious, wait for updating of base.h*/\nret_t rtl8367c_getAsicLutLearnNo(rtk_uint32 port, rtk_uint32* pNumber)\n{\n    ret_t retVal;\n\n    if(port > RTL8367C_PORTIDMAX)\n        return RT_ERR_PORT_ID;\n\n    if(port < 10)\n    {\n     retVal = rtl8367c_getAsicReg(RTL8367C_REG_L2_LRN_CNT_REG(port), pNumber);\n        if (retVal != RT_ERR_OK)\n         return retVal;\n    }\n    else\n    {\n        retVal = rtl8367c_getAsicReg(RTL8367C_REG_L2_LRN_CNT_CTRL10, pNumber);\n        if (retVal != RT_ERR_OK)\n         return retVal;\n    }\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtl8367c_setAsicLutFlushAll\n * Description:\n *      Flush all entries in LUT. Includes static & dynamic entries\n * Input:\n *      None\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicLutFlushAll(void)\n{\n    return rtl8367c_setAsicRegBit(RTL8367C_REG_L2_FLUSH_CTRL3, RTL8367C_L2_FLUSH_CTRL3_OFFSET, 1);\n}\n\n/* Function Name:\n *      rtl8367c_getAsicLutFlushAllStatus\n * Description:\n *      Get Flush all status, 1:Busy, 0 normal\n * Input:\n *      None\n * Output:\n *      pBusyStatus - Busy state\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_NULL_POINTER - Null pointer\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicLutFlushAllStatus(rtk_uint32 *pBusyStatus)\n{\n    if(NULL == pBusyStatus)\n        return RT_ERR_NULL_POINTER;\n\n    return rtl8367c_getAsicRegBit(RTL8367C_REG_L2_FLUSH_CTRL3, RTL8367C_L2_FLUSH_CTRL3_OFFSET, pBusyStatus);\n}\n\n/* Function Name:\n *      rtl8367c_setAsicLutForceFlush\n * Description:\n *      Set per port force flush setting\n * Input:\n *      portmask    - portmask(0~0xFF)\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_MASK    - Invalid portmask\n * Note:\n *      None\n */\n /*port8~port10һregister, wait for updating of base.h, reg.h*/\nret_t rtl8367c_setAsicLutForceFlush(rtk_uint32 portmask)\n{\n    ret_t retVal;\n\n    if(portmask > RTL8367C_PORTMASK)\n        return RT_ERR_PORT_MASK;\n\n    retVal = rtl8367c_setAsicRegBits(RTL8367C_FORCE_FLUSH_REG, RTL8367C_FORCE_FLUSH_PORTMASK_MASK, portmask & 0xff);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_FORCE_FLUSH1, RTL8367C_PORTMASK1_MASK, (portmask >> 8) & 0x7);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n/* Function Name:\n *      rtl8367c_getAsicLutForceFlushStatus\n * Description:\n *      Get per port force flush status\n * Input:\n *      pPortmask   - portmask(0~0xFF)\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\n /*port8~port10һregister, wait for updating of base.h, reg.h*/\nret_t rtl8367c_getAsicLutForceFlushStatus(rtk_uint32 *pPortmask)\n{\n    rtk_uint32 tmpMask;\n    ret_t retVal;\n\n    retVal = rtl8367c_getAsicRegBits(RTL8367C_FORCE_FLUSH_REG, RTL8367C_BUSY_STATUS_MASK,&tmpMask);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n    *pPortmask = tmpMask & 0xff;\n\n    retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_FORCE_FLUSH1, RTL8367C_BUSY_STATUS1_MASK,&tmpMask);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n    *pPortmask |= (tmpMask & 7) << 8;\n\n    return RT_ERR_OK;\n}\n/* Function Name:\n *      rtl8367c_setAsicLutFlushMode\n * Description:\n *      Set user force L2 pLutSt table flush mode\n * Input:\n *      mode    - 0:Port based 1: Port + VLAN based 2:Port + FID/MSTI based\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_NOT_ALLOWED  - Actions not allowed by the function\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicLutFlushMode(rtk_uint32 mode)\n{\n    if( mode >= FLUSHMDOE_END )\n        return RT_ERR_NOT_ALLOWED;\n\n    return rtl8367c_setAsicRegBits(RTL8367C_REG_L2_FLUSH_CTRL2, RTL8367C_LUT_FLUSH_MODE_MASK, mode);\n}\n/* Function Name:\n *      rtl8367c_getAsicLutFlushMode\n * Description:\n *      Get user force L2 pLutSt table flush mode\n * Input:\n *      pMode   - 0:Port based 1: Port + VLAN based 2:Port + FID/MSTI based\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicLutFlushMode(rtk_uint32* pMode)\n{\n    return rtl8367c_getAsicRegBits(RTL8367C_REG_L2_FLUSH_CTRL2, RTL8367C_LUT_FLUSH_MODE_MASK, pMode);\n}\n/* Function Name:\n *      rtl8367c_setAsicLutFlushType\n * Description:\n *      Get L2 LUT flush type\n * Input:\n *      type    - 0: dynamice unicast; 1: both dynamic and static unicast entry\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicLutFlushType(rtk_uint32 type)\n{\n    return rtl8367c_setAsicRegBit(RTL8367C_REG_L2_FLUSH_CTRL2, RTL8367C_LUT_FLUSH_TYPE_OFFSET,type);\n}\n/* Function Name:\n *      rtl8367c_getAsicLutFlushType\n * Description:\n *      Set L2 LUT flush type\n * Input:\n *      pType   - 0: dynamice unicast; 1: both dynamic and static unicast entry\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicLutFlushType(rtk_uint32* pType)\n{\n    return rtl8367c_getAsicRegBit(RTL8367C_REG_L2_FLUSH_CTRL2, RTL8367C_LUT_FLUSH_TYPE_OFFSET,pType);\n}\n\n\n/* Function Name:\n *      rtl8367c_setAsicLutFlushVid\n * Description:\n *      Set VID of Port + VID pLutSt flush mode\n * Input:\n *      vid     - Vid (0~4095)\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n *      RT_ERR_VLAN_VID - Invalid VID parameter (0~4095)\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicLutFlushVid(rtk_uint32 vid)\n{\n    if( vid > RTL8367C_VIDMAX )\n        return RT_ERR_VLAN_VID;\n\n    return rtl8367c_setAsicRegBits(RTL8367C_REG_L2_FLUSH_CTRL1, RTL8367C_LUT_FLUSH_VID_MASK, vid);\n}\n/* Function Name:\n *      rtl8367c_getAsicLutFlushVid\n * Description:\n *      Get VID of Port + VID pLutSt flush mode\n * Input:\n *      pVid    - Vid (0~4095)\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicLutFlushVid(rtk_uint32* pVid)\n{\n    return rtl8367c_getAsicRegBits(RTL8367C_REG_L2_FLUSH_CTRL1, RTL8367C_LUT_FLUSH_VID_MASK, pVid);\n}\n/* Function Name:\n *      rtl8367c_setAsicPortFlusdFid\n * Description:\n *      Set FID of Port + FID pLutSt flush mode\n * Input:\n *      fid     - FID/MSTI for force flush\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n *      RT_ERR_L2_FID   - Invalid FID (0~15)\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicLutFlushFid(rtk_uint32 fid)\n{\n    if( fid > RTL8367C_FIDMAX )\n        return RT_ERR_L2_FID;\n\n    return rtl8367c_setAsicRegBits(RTL8367C_REG_L2_FLUSH_CTRL1, RTL8367C_LUT_FLUSH_FID_MASK, fid);\n}\n/* Function Name:\n *      rtl8367c_getAsicLutFlushFid\n * Description:\n *      Get FID of Port + FID pLutSt flush mode\n * Input:\n *      pFid    - FID/MSTI for force flush\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicLutFlushFid(rtk_uint32* pFid)\n{\n    return rtl8367c_getAsicRegBits(RTL8367C_REG_L2_FLUSH_CTRL1, RTL8367C_LUT_FLUSH_FID_MASK, pFid);\n}\n/* Function Name:\n *      rtl8367c_setAsicLutDisableAging\n * Description:\n *      Set L2 LUT aging per port setting\n * Input:\n *      port    - Physical port number (0~7)\n *      disabled    - 0: enable aging; 1: disabling aging\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n *      RT_ERR_PORT_ID  - Invalid port number\n * Note:\n *      None\n */\n /*޸RTL8367C_PORTIDMAX*/\nret_t rtl8367c_setAsicLutDisableAging(rtk_uint32 port, rtk_uint32 disabled)\n{\n    if(port > RTL8367C_PORTIDMAX)\n        return RT_ERR_PORT_ID;\n\n    return rtl8367c_setAsicRegBit(RTL8367C_LUT_AGEOUT_CTRL_REG, port, disabled);\n}\n/* Function Name:\n *      rtl8367c_getAsicLutDisableAging\n * Description:\n *      Get L2 LUT aging per port setting\n * Input:\n *      port    - Physical port number (0~7)\n *      pDisabled - 0: enable aging; 1: disabling aging\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n *      RT_ERR_PORT_ID  - Invalid port number\n * Note:\n *      None\n */\n /*޸RTL8367C_PORTIDMAX*/\nret_t rtl8367c_getAsicLutDisableAging(rtk_uint32 port, rtk_uint32 *pDisabled)\n{\n    if(port > RTL8367C_PORTIDMAX)\n        return RT_ERR_PORT_ID;\n\n    return rtl8367c_getAsicRegBit(RTL8367C_LUT_AGEOUT_CTRL_REG, port, pDisabled);\n}\n\n/* Function Name:\n *      rtl8367c_setAsicLutIPMCGroup\n * Description:\n *      Set IPMC Group Table\n * Input:\n *      index       - the entry index in table (0 ~ 63)\n *      group_addr  - the multicast group address (224.0.0.0 ~ 239.255.255.255)\n *      vid         - VLAN ID\n *      pmask       - portmask\n *      valid       - valid bit\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n *      RT_ERR_INPUT    - Invalid parameter\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicLutIPMCGroup(rtk_uint32 index, ipaddr_t group_addr, rtk_uint32 vid, rtk_uint32 pmask, rtk_uint32 valid)\n{\n    rtk_uint32  regAddr, regData, bitoffset;\n    ipaddr_t    ipData;\n    ret_t       retVal;\n\n    if(index > RTL8367C_LUT_IPMCGRP_TABLE_MAX)\n        return RT_ERR_INPUT;\n\n    if (vid > RTL8367C_VIDMAX)\n        return RT_ERR_VLAN_VID;\n\n    ipData = group_addr;\n\n    if( (ipData & 0xF0000000) != 0xE0000000)    /* not in 224.0.0.0 ~ 239.255.255.255 */\n        return RT_ERR_INPUT;\n\n    /* Group Address */\n    regAddr = RTL8367C_REG_IPMC_GROUP_ENTRY0_H + (index * 2);\n    regData = ((ipData & 0x0FFFFFFF) >> 16);\n\n    if( (retVal = rtl8367c_setAsicReg(regAddr, regData)) != RT_ERR_OK)\n        return retVal;\n\n    regAddr++;\n    regData = (ipData & 0x0000FFFF);\n\n    if( (retVal = rtl8367c_setAsicReg(regAddr, regData)) != RT_ERR_OK)\n        return retVal;\n\n    /* VID */\n    regAddr = RTL8367C_REG_IPMC_GROUP_VID_00 + index;\n    regData = vid;\n\n    if( (retVal = rtl8367c_setAsicReg(regAddr, regData)) != RT_ERR_OK)\n        return retVal;\n\n    /* portmask */\n    regAddr = RTL8367C_REG_IPMC_GROUP_PMSK_00 + index;\n    regData = pmask;\n\n    if( (retVal = rtl8367c_setAsicReg(regAddr, regData)) != RT_ERR_OK)\n        return retVal;\n\n    /* valid */\n    regAddr = RTL8367C_REG_IPMC_GROUP_VALID_15_0 + (index / 16);\n    bitoffset = index % 16;\n    if( (retVal = rtl8367c_setAsicRegBit(regAddr, bitoffset, valid)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtl8367c_getAsicLutIPMCGroup\n * Description:\n *      Set IPMC Group Table\n * Input:\n *      index       - the entry index in table (0 ~ 63)\n * Output:\n *      pGroup_addr - the multicast group address (224.0.0.0 ~ 239.255.255.255)\n *      pVid        - VLAN ID\n *      pPmask      - portmask\n *      pValid      - Valid bit\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n *      RT_ERR_INPUT    - Invalid parameter\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicLutIPMCGroup(rtk_uint32 index, ipaddr_t *pGroup_addr, rtk_uint32 *pVid, rtk_uint32 *pPmask, rtk_uint32 *pValid)\n{\n    rtk_uint32      regAddr, regData, bitoffset;\n    ipaddr_t    ipData;\n    ret_t       retVal;\n\n    if(index > RTL8367C_LUT_IPMCGRP_TABLE_MAX)\n        return RT_ERR_INPUT;\n\n    if (NULL == pGroup_addr)\n        return RT_ERR_NULL_POINTER;\n\n    if (NULL == pVid)\n        return RT_ERR_NULL_POINTER;\n\n    if (NULL == pPmask)\n        return RT_ERR_NULL_POINTER;\n\n    /* Group address */\n    regAddr = RTL8367C_REG_IPMC_GROUP_ENTRY0_H + (index * 2);\n    if( (retVal = rtl8367c_getAsicReg(regAddr, &regData)) != RT_ERR_OK)\n        return retVal;\n\n    *pGroup_addr = (((regData & 0x00000FFF) << 16) | 0xE0000000);\n\n    regAddr++;\n    if( (retVal = rtl8367c_getAsicReg(regAddr, &regData)) != RT_ERR_OK)\n        return retVal;\n\n    ipData = (*pGroup_addr | (regData & 0x0000FFFF));\n    *pGroup_addr = ipData;\n\n    /* VID */\n    regAddr = RTL8367C_REG_IPMC_GROUP_VID_00 + index;\n    if( (retVal = rtl8367c_getAsicReg(regAddr, &regData)) != RT_ERR_OK)\n        return retVal;\n\n    *pVid = regData;\n\n    /* portmask */\n    regAddr = RTL8367C_REG_IPMC_GROUP_PMSK_00 + index;\n    if( (retVal = rtl8367c_getAsicReg(regAddr, &regData)) != RT_ERR_OK)\n        return retVal;\n\n    *pPmask = regData;\n\n    /* valid */\n    regAddr = RTL8367C_REG_IPMC_GROUP_VALID_15_0 + (index / 16);\n    bitoffset = index % 16;\n    if( (retVal = rtl8367c_getAsicRegBit(regAddr, bitoffset, &regData)) != RT_ERR_OK)\n        return retVal;\n\n    *pValid = regData;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtl8367c_setAsicLutLinkDownForceAging\n * Description:\n *       Set LUT link down aging setting.\n * Input:\n *      enable      - link down aging setting\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n *      RT_ERR_ENABLE    - Invalid parameter\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicLutLinkDownForceAging(rtk_uint32 enable)\n{\n    if(enable > 1)\n        return RT_ERR_ENABLE;\n\n    return rtl8367c_setAsicRegBit(RTL8367C_REG_LUT_CFG, RTL8367C_LINKDOWN_AGEOUT_OFFSET, enable ? 0 : 1);\n}\n\n/* Function Name:\n *      rtl8367c_getAsicLutLinkDownForceAging\n * Description:\n *       Get LUT link down aging setting.\n * Input:\n *      pEnable         - link down aging setting\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n *      RT_ERR_ENABLE    - Invalid parameter\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicLutLinkDownForceAging(rtk_uint32 *pEnable)\n{\n    rtk_uint32  value;\n    ret_t   retVal;\n\n    if ((retVal = rtl8367c_getAsicRegBit(RTL8367C_REG_LUT_CFG, RTL8367C_LINKDOWN_AGEOUT_OFFSET, &value)) != RT_ERR_OK)\n        return retVal;\n\n    *pEnable = value ? 0 : 1;\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtl8367c_setAsicLutIpmcFwdRouterPort\n * Description:\n *       Set IPMC packet forward to rounter port also or not\n * Input:\n *      enable      - 1: Inlcude router port, 0, exclude router port\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n *      RT_ERR_ENABLE     Invalid parameter\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicLutIpmcFwdRouterPort(rtk_uint32 enable)\n{\n    if(enable > 1)\n        return RT_ERR_ENABLE;\n\n    return rtl8367c_setAsicRegBit(RTL8367C_REG_LUT_CFG2, RTL8367C_LUT_IPMC_FWD_RPORT_OFFSET, enable);\n}\n\n/* Function Name:\n *      rtl8367c_getAsicLutIpmcFwdRouterPort\n * Description:\n *       Get IPMC packet forward to rounter port also or not\n * Input:\n *      None\n * Output:\n *      pEnable         - 1: Inlcude router port, 0, exclude router port\n * Return:\n *      RT_ERR_OK               - Success\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_NULL_POINTER     - Null pointer\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicLutIpmcFwdRouterPort(rtk_uint32 *pEnable)\n{\n    if(NULL == pEnable)\n        return RT_ERR_NULL_POINTER;\n\n    return rtl8367c_getAsicRegBit(RTL8367C_REG_LUT_CFG2, RTL8367C_LUT_IPMC_FWD_RPORT_OFFSET, pEnable);\n}\n\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_meter.c",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * $Revision: 76306 $\n * $Date: 2017-03-08 15:13:58 +0800 (週三, 08 三月 2017) $\n *\n * Purpose : RTL8367C switch high-level API for RTL8367C\n * Feature : Shared meter related functions\n *\n */\n#include <rtl8367c_asicdrv_meter.h>\n/* Function Name:\n *      rtl8367c_setAsicShareMeter\n * Description:\n *      Set meter configuration\n * Input:\n *      index   - hared meter index (0-31)\n *      rate    - 17-bits rate of share meter, unit is 8Kpbs\n *      ifg     - Including IFG in rate calculation, 1:include 0:exclude\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - Success\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_FILTER_METER_ID  - Invalid meter\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicShareMeter(rtk_uint32 index, rtk_uint32 rate, rtk_uint32 ifg)\n{\n    ret_t retVal;\n\n    if(index > RTL8367C_METERMAX)\n        return RT_ERR_FILTER_METER_ID;\n\n    if(index < 32)\n    {\n    /*19-bits Rate*/\n        retVal = rtl8367c_setAsicReg(RTL8367C_METER_RATE_REG(index), rate&0xFFFF);\n        if(retVal != RT_ERR_OK)\n            return retVal;\n\n        retVal = rtl8367c_setAsicReg(RTL8367C_METER_RATE_REG(index) + 1, (rate &0x70000) >> 16);\n        if(retVal != RT_ERR_OK)\n            return retVal;\n\n        retVal = rtl8367c_setAsicRegBit(RTL8367C_METER_IFG_CTRL_REG(index), RTL8367C_METER_IFG_OFFSET(index), ifg);\n        if(retVal != RT_ERR_OK)\n            return retVal;\n    }\n    else\n    {\n    /*19-bits Rate*/\n        retVal = rtl8367c_setAsicReg(RTL8367C_REG_METER32_RATE_CTRL0 + ((index-32) << 1), rate&0xFFFF);\n        if(retVal != RT_ERR_OK)\n            return retVal;\n\n        retVal = rtl8367c_setAsicReg(RTL8367C_REG_METER32_RATE_CTRL0 + ((index-32) << 1) + 1, (rate &0x70000) >> 16);\n        if(retVal != RT_ERR_OK)\n            return retVal;\n\n        retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_METER_IFG_CTRL2 + ((index-32) >> 4), RTL8367C_METER_IFG_OFFSET(index), ifg);\n        if(retVal != RT_ERR_OK)\n            return retVal;\n    }\n\n    return RT_ERR_OK;\n}\n/* Function Name:\n *      rtl8367c_getAsicShareMeter\n * Description:\n *      Get meter configuration\n * Input:\n *      index   - hared meter index (0-31)\n *      pRate   - 17-bits rate of share meter, unit is 8Kpbs\n *      pIfg    - Including IFG in rate calculation, 1:include 0:exclude\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - Success\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_FILTER_METER_ID  - Invalid meter\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicShareMeter(rtk_uint32 index, rtk_uint32 *pRate, rtk_uint32 *pIfg)\n{\n    rtk_uint32 regData;\n    rtk_uint32 regData2;\n    ret_t retVal;\n\n    if(index > RTL8367C_METERMAX)\n        return RT_ERR_FILTER_METER_ID;\n\n    if(index < 32)\n    {\n    /*17-bits Rate*/\n     retVal = rtl8367c_getAsicReg(RTL8367C_METER_RATE_REG(index), &regData);\n        if(retVal != RT_ERR_OK)\n            return retVal;\n\n     retVal = rtl8367c_getAsicReg(RTL8367C_METER_RATE_REG(index) + 1, &regData2);\n        if(retVal != RT_ERR_OK)\n            return retVal;\n\n    *pRate = ((regData2 << 16) & 0x70000) | regData;\n    /*IFG*/\n    retVal = rtl8367c_getAsicRegBit(RTL8367C_METER_IFG_CTRL_REG(index), RTL8367C_METER_IFG_OFFSET(index), pIfg);\n\n    return retVal;\n    }\n    else\n    {\n    /*17-bits Rate*/\n     retVal = rtl8367c_getAsicReg(RTL8367C_REG_METER32_RATE_CTRL0 + ((index-32) << 1), &regData);\n        if(retVal != RT_ERR_OK)\n            return retVal;\n\n     retVal = rtl8367c_getAsicReg(RTL8367C_REG_METER32_RATE_CTRL0 + ((index-32) << 1) + 1, &regData2);\n        if(retVal != RT_ERR_OK)\n            return retVal;\n\n    *pRate = ((regData2 << 16) & 0x70000) | regData;\n    /*IFG*/\n    retVal = rtl8367c_getAsicRegBit(RTL8367C_REG_METER_IFG_CTRL2 + ((index-32) >> 4), RTL8367C_METER_IFG_OFFSET(index), pIfg);\n\n    return retVal;\n    }\n}\n/* Function Name:\n *      rtl8367c_setAsicShareMeterBucketSize\n * Description:\n *      Set meter related leaky bucket threshold\n * Input:\n *      index       - hared meter index (0-31)\n *      lbthreshold - Leaky bucket threshold of meter\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - Success\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_FILTER_METER_ID  - Invalid meter\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicShareMeterBucketSize(rtk_uint32 index, rtk_uint32 lbthreshold)\n{\n\n    if(index > RTL8367C_METERMAX)\n        return RT_ERR_FILTER_METER_ID;\n\n    if(index < 32)\n    return rtl8367c_setAsicReg(RTL8367C_METER_BUCKET_SIZE_REG(index), lbthreshold);\n    else\n       return rtl8367c_setAsicReg(RTL8367C_REG_METER32_BUCKET_SIZE + index - 32, lbthreshold);\n}\n/* Function Name:\n *      rtl8367c_getAsicShareMeterBucketSize\n * Description:\n *      Get meter related leaky bucket threshold\n * Input:\n *      index       - hared meter index (0-31)\n *      pLbthreshold - Leaky bucket threshold of meter\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - Success\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_FILTER_METER_ID  - Invalid meter\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicShareMeterBucketSize(rtk_uint32 index, rtk_uint32 *pLbthreshold)\n{\n    if(index > RTL8367C_METERMAX)\n        return RT_ERR_FILTER_METER_ID;\n\n    if(index < 32)\n    return rtl8367c_getAsicReg(RTL8367C_METER_BUCKET_SIZE_REG(index), pLbthreshold);\n    else\n       return rtl8367c_getAsicReg(RTL8367C_REG_METER32_BUCKET_SIZE + index - 32, pLbthreshold);\n}\n\n/* Function Name:\n *      rtl8367c_setAsicShareMeterType\n * Description:\n *      Set meter Type\n * Input:\n *      index       - shared meter index (0-31)\n *      Type        - 0: kbps, 1: pps\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - Success\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_FILTER_METER_ID  - Invalid meter\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicShareMeterType(rtk_uint32 index, rtk_uint32 type)\n{\n    rtk_uint32 reg;\n\n    if(index > RTL8367C_METERMAX)\n        return RT_ERR_FILTER_METER_ID;\n\n    if(index < 32)\n        reg = RTL8367C_REG_METER_MODE_SETTING0 + (index / 16);\n    else\n        reg = RTL8367C_REG_METER_MODE_SETTING2 + ((index - 32) / 16);\n    return rtl8367c_setAsicRegBit(reg, index % 16, type);\n}\n\n/* Function Name:\n *      rtl8367c_getAsicShareMeterType\n * Description:\n *      Get meter Type\n * Input:\n *      index       - shared meter index (0-31)\n * Output:\n *      pType       - 0: kbps, 1: pps\n * Return:\n *      RT_ERR_OK               - Success\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_FILTER_METER_ID  - Invalid meter\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicShareMeterType(rtk_uint32 index, rtk_uint32 *pType)\n{\n    rtk_uint32 reg;\n\n    if(index > RTL8367C_METERMAX)\n        return RT_ERR_FILTER_METER_ID;\n\n    if(NULL == pType)\n        return RT_ERR_NULL_POINTER;\n\n    if(index < 32)\n        reg = RTL8367C_REG_METER_MODE_SETTING0 + (index / 16);\n    else\n        reg = RTL8367C_REG_METER_MODE_SETTING2 + ((index - 32) / 16);\n    return rtl8367c_getAsicRegBit(reg, index % 16, pType);\n}\n\n\n/* Function Name:\n *      rtl8367c_setAsicMeterExceedStatus\n * Description:\n *      Clear shared meter status\n * Input:\n *      index       - hared meter index (0-31)\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - Success\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_FILTER_METER_ID  - Invalid meter\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicMeterExceedStatus(rtk_uint32 index)\n{\n    if(index > RTL8367C_METERMAX)\n        return RT_ERR_FILTER_METER_ID;\n\n    if(index < 32)\n        return rtl8367c_setAsicRegBit(RTL8367C_METER_OVERRATE_INDICATOR_REG(index), RTL8367C_METER_EXCEED_OFFSET(index), 1);\n    else\n        return rtl8367c_setAsicRegBit(RTL8367C_REG_METER_OVERRATE_INDICATOR2 + ((index - 32) >> 4), RTL8367C_METER_EXCEED_OFFSET(index), 1);\n\n}\n/* Function Name:\n *      rtl8367c_getAsicMeterExceedStatus\n * Description:\n *      Get shared meter status\n * Input:\n *      index   - hared meter index (0-31)\n *      pStatus     - 0: rate doesn't exceed    1: rate exceeds\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - Success\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_FILTER_METER_ID  - Invalid meter\n * Note:\n *      If rate is over rate*8Kbps of a meter, the state bit of this meter is set to 1.\n */\nret_t rtl8367c_getAsicMeterExceedStatus(rtk_uint32 index, rtk_uint32* pStatus)\n{\n    if(index > RTL8367C_METERMAX)\n        return RT_ERR_FILTER_METER_ID;\n\n    if(index < 32)\n        return rtl8367c_getAsicRegBit(RTL8367C_METER_OVERRATE_INDICATOR_REG(index), RTL8367C_METER_EXCEED_OFFSET(index), pStatus);\n    else\n        return rtl8367c_getAsicRegBit(RTL8367C_REG_METER_OVERRATE_INDICATOR2 + ((index - 32) >> 4), RTL8367C_METER_EXCEED_OFFSET(index), pStatus);\n}\n\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_mib.c",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * $Revision: 76306 $\n * $Date: 2017-03-08 15:13:58 +0800 (週三, 08 三月 2017) $\n *\n * Purpose : RTL8367C switch high-level API for RTL8367C\n * Feature : MIB related functions\n *\n */\n\n#include <rtl8367c_asicdrv_mib.h>\n/* Function Name:\n *      rtl8367c_setAsicMIBsCounterReset\n * Description:\n *      Reset global/queue manage or per-port MIB counter\n * Input:\n *      greset  - Global reset\n *      qmreset - Queue maganement reset\n *      portmask    - Port reset mask\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - Success\n *      RT_ERR_SMI              - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicMIBsCounterReset(rtk_uint32 greset, rtk_uint32 qmreset, rtk_uint32 portmask)\n{\n    ret_t retVal;\n    rtk_uint32 regData;\n    rtk_uint32 regBits;\n\n    regBits = RTL8367C_GLOBAL_RESET_MASK |\n                RTL8367C_QM_RESET_MASK |\n                    RTL8367C_MIB_PORT07_MASK |\n                    ((rtk_uint32)0x7 << 13);\n    regData = ((greset << RTL8367C_GLOBAL_RESET_OFFSET) & RTL8367C_GLOBAL_RESET_MASK) |\n                ((qmreset << RTL8367C_QM_RESET_OFFSET) & RTL8367C_QM_RESET_MASK) |\n                (((portmask & 0xFF) << RTL8367C_PORT0_RESET_OFFSET) & RTL8367C_MIB_PORT07_MASK) |\n                (((portmask >> 8)&0x7) << 13);\n\n\n    retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_MIB_CTRL0, regBits, (regData >> RTL8367C_PORT0_RESET_OFFSET));\n\n    return retVal;\n}\n/* Function Name:\n *      rtl8367c_getAsicMIBsCounter\n * Description:\n *      Get MIBs counter\n * Input:\n *      port        - Physical port number (0~7)\n *      mibIdx      - MIB counter index\n *      pCounter    - MIB retrived counter\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - Success\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_PORT_ID          - Invalid port number\n *      RT_ERR_BUSYWAIT_TIMEOUT - MIB is busy at retrieving\n *      RT_ERR_STAT_CNTR_FAIL   - MIB is resetting\n * Note:\n *      Before MIBs counter retrieving, writting accessing address to ASIC at first and check the MIB\n *      control register status. If busy bit of MIB control is set, that means MIB counter have been\n *      waiting for preparing, then software must wait atfer this busy flag reset by ASIC. This driver\n *      did not recycle reading user desired counter. Software must use driver again to get MIB counter\n *      if return value is not RT_ERR_OK.\n */\nret_t rtl8367c_getAsicMIBsCounter(rtk_uint32 port, RTL8367C_MIBCOUNTER mibIdx, rtk_uint64* pCounter)\n{\n    ret_t retVal;\n    rtk_uint32 regAddr;\n    rtk_uint32 regData;\n    rtk_uint32 mibAddr;\n    rtk_uint32 mibOff=0;\n\n    /* address offset to MIBs counter */\n    CONST rtk_uint16 mibLength[RTL8367C_MIBS_NUMBER]= {\n        4,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,\n        4,2,2,2,2,2,2,2,2,\n        4,2,2,2,2,2,2,2,2,2,2,2,2,2,2,\n        2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2};\n\n    rtk_uint16 i;\n    rtk_uint64 mibCounter;\n\n\n    if(port > RTL8367C_PORTIDMAX)\n        return RT_ERR_PORT_ID;\n\n    if(mibIdx >= RTL8367C_MIBS_NUMBER)\n        return RT_ERR_STAT_INVALID_CNTR;\n\n    if(dot1dTpLearnedEntryDiscards == mibIdx)\n    {\n        mibAddr = RTL8367C_MIB_LEARNENTRYDISCARD_OFFSET;\n    }\n    else\n    {\n        i = 0;\n        mibOff = RTL8367C_MIB_PORT_OFFSET * port;\n\n        if(port > 7)\n            mibOff = mibOff + 68;\n\n        while(i < mibIdx)\n        {\n            mibOff += mibLength[i];\n            i++;\n        }\n\n        mibAddr = mibOff;\n    }\n\n\n    /*writing access counter address first*/\n    /*This address is SRAM address, and SRAM address = MIB register address >> 2*/\n    /*then ASIC will prepare 64bits counter wait for being retrived*/\n    /*Write Mib related address to access control register*/\n    retVal = rtl8367c_setAsicReg(RTL8367C_REG_MIB_ADDRESS, (mibAddr >> 2));\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n\n\n    /* polling busy flag */\n    i = 100;\n    while(i > 0)\n    {\n        /*read MIB control register*/\n        retVal = rtl8367c_getAsicReg(RTL8367C_MIB_CTRL_REG,&regData);\n        if(retVal != RT_ERR_OK)\n            return retVal;\n\n        if((regData & RTL8367C_MIB_CTRL0_BUSY_FLAG_MASK) == 0)\n        {\n            break;\n        }\n\n        i--;\n    }\n\n    if(regData & RTL8367C_MIB_CTRL0_BUSY_FLAG_MASK)\n        return RT_ERR_BUSYWAIT_TIMEOUT;\n\n    if(regData & RTL8367C_RESET_FLAG_MASK)\n        return RT_ERR_STAT_CNTR_FAIL;\n\n    mibCounter = 0;\n    i = mibLength[mibIdx];\n    if(4 == i)\n        regAddr = RTL8367C_MIB_COUNTER_BASE_REG + 3;\n    else\n        regAddr = RTL8367C_MIB_COUNTER_BASE_REG + ((mibOff + 1) % 4);\n\n    while(i)\n    {\n        retVal = rtl8367c_getAsicReg(regAddr, &regData);\n        if(retVal != RT_ERR_OK)\n            return retVal;\n\n        mibCounter = (mibCounter << 16) | (regData & 0xFFFF);\n\n        regAddr --;\n        i --;\n\n    }\n\n    *pCounter = mibCounter;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtl8367c_getAsicMIBsLogCounter\n * Description:\n *      Get MIBs Loggin counter\n * Input:\n *      index       - The index of 32 logging counter (0 ~ 31)\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - Success\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_ENTRY_INDEX      - Wrong index\n *      RT_ERR_BUSYWAIT_TIMEOUT - MIB is busy at retrieving\n *      RT_ERR_STAT_CNTR_FAIL   - MIB is resetting\n * Note:\n *      This API get 32 logging counter\n */\nret_t rtl8367c_getAsicMIBsLogCounter(rtk_uint32 index, rtk_uint32 *pCounter)\n{\n    ret_t retVal;\n    rtk_uint32 regAddr;\n    rtk_uint32 regData;\n    rtk_uint32 mibAddr;\n    rtk_uint16 i;\n    rtk_uint64 mibCounter;\n\n    if(index > RTL8367C_MIB_MAX_LOG_CNT_IDX)\n        return RT_ERR_ENTRY_INDEX;\n\n    mibAddr = RTL8367C_MIB_LOG_CNT_OFFSET + ((index / 2) * 4);\n\n    retVal = rtl8367c_setAsicReg(RTL8367C_REG_MIB_ADDRESS, (mibAddr >> 2));\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    /*read MIB control register*/\n    retVal = rtl8367c_getAsicReg(RTL8367C_MIB_CTRL_REG, &regData);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    if(regData & RTL8367C_MIB_CTRL0_BUSY_FLAG_MASK)\n        return RT_ERR_BUSYWAIT_TIMEOUT;\n\n    if(regData & RTL8367C_RESET_FLAG_MASK)\n        return RT_ERR_STAT_CNTR_FAIL;\n\n    mibCounter = 0;\n    if((index % 2) == 1)\n        regAddr = RTL8367C_MIB_COUNTER_BASE_REG + 3;\n    else\n        regAddr = RTL8367C_MIB_COUNTER_BASE_REG + 1;\n\n    for(i = 0; i <= 1; i++)\n    {\n        retVal = rtl8367c_getAsicReg(regAddr, &regData);\n\n        if(retVal != RT_ERR_OK)\n            return retVal;\n\n        mibCounter = (mibCounter << 16) | (regData & 0xFFFF);\n\n        regAddr --;\n    }\n\n    *pCounter = mibCounter;\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtl8367c_getAsicMIBsControl\n * Description:\n *      Get MIB control register\n * Input:\n *      pMask       - MIB control status mask bit[0]-busy bit[1]\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - Success\n *      RT_ERR_SMI              - SMI access error\n * Note:\n *      Software need to check this control register atfer doing port resetting or global resetting\n */\nret_t rtl8367c_getAsicMIBsControl(rtk_uint32* pMask)\n{\n    ret_t retVal;\n    rtk_uint32 regData;\n\n    retVal = rtl8367c_getAsicReg(RTL8367C_MIB_CTRL_REG, &regData);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    *pMask = regData & (RTL8367C_MIB_CTRL0_BUSY_FLAG_MASK | RTL8367C_RESET_FLAG_MASK);\n\n    return RT_ERR_OK;\n}\n/* Function Name:\n *      rtl8367c_setAsicMIBsResetValue\n * Description:\n *      Reset all counter to 0 or 1\n * Input:\n *      value           - Reset to value 0 or 1\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicMIBsResetValue(rtk_uint32 value)\n{\n    return rtl8367c_setAsicRegBit(RTL8367C_REG_MIB_CTRL0, RTL8367C_RESET_VALUE_OFFSET, value);\n}\n/* Function Name:\n *      rtl8367c_getAsicMIBsResetValue\n * Description:\n *      Reset all counter to 0 or 1\n * Input:\n *      value           - Reset to value 0 or 1\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicMIBsResetValue(rtk_uint32* value)\n{\n    return rtl8367c_getAsicRegBit(RTL8367C_REG_MIB_CTRL0, RTL8367C_RESET_VALUE_OFFSET, value);\n}\n\n/* Function Name:\n *      rtl8367c_setAsicMIBsUsageMode\n * Description:\n *      MIB update mode\n * Input:\n *      mode            - 1: latch all MIBs by timer 0:normal free run counting\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicMIBsUsageMode(rtk_uint32 mode)\n{\n    return rtl8367c_setAsicRegBit(RTL8367C_REG_MIB_CTRL4, RTL8367C_MIB_USAGE_MODE_OFFSET, mode);\n}\n/* Function Name:\n *      rtl8367c_getAsicMIBsUsageMode\n * Description:\n *      MIB update mode\n * Input:\n *      pMode           - 1: latch all MIBs by timer 0:normal free run counting\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicMIBsUsageMode(rtk_uint32* pMode)\n{\n    return rtl8367c_getAsicRegBit(RTL8367C_REG_MIB_CTRL4, RTL8367C_MIB_USAGE_MODE_OFFSET, pMode);\n}\n\n/* Function Name:\n *      rtl8367c_setAsicMIBsTimer\n * Description:\n *      MIB latching timer\n * Input:\n *      timer           - latch timer, unit 1 second\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicMIBsTimer(rtk_uint32 timer)\n{\n    return rtl8367c_setAsicRegBits(RTL8367C_REG_MIB_CTRL4, RTL8367C_MIB_TIMER_MASK, timer);\n}\n/* Function Name:\n *      rtl8367c_getAsicMIBsTimer\n * Description:\n *      MIB latching timer\n * Input:\n *      pTimer          - latch timer, unit 1 second\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicMIBsTimer(rtk_uint32* pTimer)\n{\n    return rtl8367c_getAsicRegBits(RTL8367C_REG_MIB_CTRL4, RTL8367C_MIB_TIMER_MASK, pTimer);\n}\n/* Function Name:\n *      rtl8367c_setAsicMIBsLoggingMode\n * Description:\n *      MIB logging counter mode\n * Input:\n *      index   - logging counter mode index (0~15)\n *      mode    - 0:32-bits mode 1:64-bits mode\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - Success\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_OUT_OF_RANGE     - input parameter out of range\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicMIBsLoggingMode(rtk_uint32 index, rtk_uint32 mode)\n{\n    if(index > RTL8367C_MIB_MAX_LOG_MODE_IDX)\n        return RT_ERR_OUT_OF_RANGE;\n\n    return rtl8367c_setAsicRegBit(RTL8367C_REG_MIB_CTRL3, index,mode);\n}\n/* Function Name:\n *      rtl8367c_getAsicMIBsLoggingMode\n * Description:\n *      MIB logging counter mode\n * Input:\n *      index   - logging counter mode index (0~15)\n *      pMode   - 0:32-bits mode 1:64-bits mode\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - Success\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_OUT_OF_RANGE     - input parameter out of range\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicMIBsLoggingMode(rtk_uint32 index, rtk_uint32* pMode)\n{\n    if(index > RTL8367C_MIB_MAX_LOG_MODE_IDX)\n        return RT_ERR_OUT_OF_RANGE;\n\n    return rtl8367c_getAsicRegBit(RTL8367C_REG_MIB_CTRL3, index,pMode);\n}\n\n/* Function Name:\n *      rtl8367c_setAsicMIBsLoggingType\n * Description:\n *      MIB logging counter type\n * Input:\n *      index   - logging counter mode index (0~15)\n *      type    - 0:Packet count 1:Byte count\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - Success\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_OUT_OF_RANGE     - input parameter out of range\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicMIBsLoggingType(rtk_uint32 index, rtk_uint32 type)\n{\n    if(index > RTL8367C_MIB_MAX_LOG_MODE_IDX)\n        return RT_ERR_OUT_OF_RANGE;\n\n    return rtl8367c_setAsicRegBit(RTL8367C_REG_MIB_CTRL5, index,type);\n}\n\n/* Function Name:\n *      rtl8367c_getAsicMIBsLoggingType\n * Description:\n *      MIB logging counter type\n * Input:\n *      index   - logging counter mode index (0~15)\n *      pType   - 0:Packet count 1:Byte count\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - Success\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_OUT_OF_RANGE     - input parameter out of range\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicMIBsLoggingType(rtk_uint32 index, rtk_uint32* pType)\n{\n    if(index > RTL8367C_MIB_MAX_LOG_MODE_IDX)\n        return RT_ERR_OUT_OF_RANGE;\n\n    return rtl8367c_getAsicRegBit(RTL8367C_REG_MIB_CTRL5, index,pType);\n}\n\n/* Function Name:\n *      rtl8367c_setAsicMIBsResetLoggingCounter\n * Description:\n *      MIB logging counter type\n * Input:\n *      index   - logging counter index (0~31)\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - Success\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_OUT_OF_RANGE     - input parameter out of range\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicMIBsResetLoggingCounter(rtk_uint32 index)\n{\n    ret_t retVal;\n\n    if(index > RTL8367C_MIB_MAX_LOG_CNT_IDX)\n        return RT_ERR_OUT_OF_RANGE;\n\n    if(index < 16)\n        retVal = rtl8367c_setAsicReg(RTL8367C_REG_MIB_CTRL1, 1<<index);\n    else\n        retVal = rtl8367c_setAsicReg(RTL8367C_REG_MIB_CTRL2, 1<<(index-16));\n\n    return retVal;\n}\n\n/* Function Name:\n *      rtl8367c_setAsicMIBsLength\n * Description:\n *      Set MIB length couting mode\n * Input:\n *      txLengthMode    - 0: tag length doesn't be counted. 1: tag length is counted.\n *      rxLengthMode    - 0: tag length doesn't be counted. 1: tag length is counted.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - Success\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_OUT_OF_RANGE     - input parameter out of range\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicMIBsLength(rtk_uint32 txLengthMode, rtk_uint32 rxLengthMode)\n{\n    ret_t retVal;\n\n    if( (retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_MIB_RMON_LEN_CTRL, RTL8367C_TX_LENGTH_CTRL_OFFSET, txLengthMode)) != RT_ERR_OK)\n        return retVal;\n\n    if( (retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_MIB_RMON_LEN_CTRL, RTL8367C_RX_LENGTH_CTRL_OFFSET, rxLengthMode)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtl8367c_setAsicMIBsLength\n * Description:\n *      Set MIB length couting mode\n * Input:\n *      None.\n * Output:\n *      pTxLengthMode - 0: tag length doesn't be counted. 1: tag length is counted.\n *      pRxLengthMode - 0: tag length doesn't be counted. 1: tag length is counted.\n * Return:\n *      RT_ERR_OK               - Success\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_OUT_OF_RANGE     - input parameter out of range\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicMIBsLength(rtk_uint32 *pTxLengthMode, rtk_uint32 *pRxLengthMode)\n{\n    ret_t retVal;\n\n    if( (retVal = rtl8367c_getAsicRegBit(RTL8367C_REG_MIB_RMON_LEN_CTRL, RTL8367C_TX_LENGTH_CTRL_OFFSET, pTxLengthMode)) != RT_ERR_OK)\n        return retVal;\n\n    if( (retVal = rtl8367c_getAsicRegBit(RTL8367C_REG_MIB_RMON_LEN_CTRL, RTL8367C_RX_LENGTH_CTRL_OFFSET, pRxLengthMode)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_mirror.c",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * $Revision: 76306 $\n * $Date: 2017-03-08 15:13:58 +0800 (週三, 08 三月 2017) $\n *\n * Purpose : RTL8367C switch high-level API for RTL8367C\n * Feature : Port mirror related functions\n *\n */\n#include <rtl8367c_asicdrv_mirror.h>\n/* Function Name:\n *      rtl8367c_setAsicPortMirror\n * Description:\n *      Set port mirror function\n * Input:\n *      source  - Source port\n *      monitor - Monitor (destination) port\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n *      RT_ERR_PORT_ID  - Invalid port number\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicPortMirror(rtk_uint32 source, rtk_uint32 monitor)\n{\n    ret_t retVal;\n\n    if((source > RTL8367C_PORTIDMAX) || (monitor > RTL8367C_PORTIDMAX))\n        return RT_ERR_PORT_ID;\n\n    retVal = rtl8367c_setAsicRegBits(RTL8367C_MIRROR_CTRL_REG, RTL8367C_MIRROR_SOURCE_PORT_MASK, source);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n\n    return rtl8367c_setAsicRegBits(RTL8367C_MIRROR_CTRL_REG, RTL8367C_MIRROR_MONITOR_PORT_MASK, monitor);\n}\n/* Function Name:\n *      rtl8367c_getAsicPortMirror\n * Description:\n *      Get port mirror function\n * Input:\n *      pSource     - Source port\n *      pMonitor - Monitor (destination) port\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicPortMirror(rtk_uint32 *pSource, rtk_uint32 *pMonitor)\n{\n    ret_t retVal;\n\n    retVal = rtl8367c_getAsicRegBits(RTL8367C_MIRROR_CTRL_REG, RTL8367C_MIRROR_SOURCE_PORT_MASK, pSource);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    return rtl8367c_getAsicRegBits(RTL8367C_MIRROR_CTRL_REG, RTL8367C_MIRROR_MONITOR_PORT_MASK, pMonitor);\n}\n/* Function Name:\n *      rtl8367c_setAsicPortMirrorRxFunction\n * Description:\n *      Set the mirror function on RX of the mirrored\n * Input:\n *      enabled     - 1: enabled, 0: disabled\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicPortMirrorRxFunction(rtk_uint32 enabled)\n{\n    return rtl8367c_setAsicRegBit(RTL8367C_MIRROR_CTRL_REG, RTL8367C_MIRROR_RX_OFFSET, enabled);\n}\n/* Function Name:\n *      rtl8367c_getAsicPortMirrorRxFunction\n * Description:\n *      Get the mirror function on RX of the mirrored\n * Input:\n *      pEnabled    - 1: enabled, 0: disabled\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicPortMirrorRxFunction(rtk_uint32* pEnabled)\n{\n    return rtl8367c_getAsicRegBit(RTL8367C_MIRROR_CTRL_REG, RTL8367C_MIRROR_RX_OFFSET, pEnabled);\n}\n/* Function Name:\n *      rtl8367c_setAsicPortMirrorTxFunction\n * Description:\n *      Set the mirror function on TX of the mirrored\n * Input:\n *      enabled     - 1: enabled, 0: disabled\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicPortMirrorTxFunction(rtk_uint32 enabled)\n{\n    return rtl8367c_setAsicRegBit(RTL8367C_MIRROR_CTRL_REG, RTL8367C_MIRROR_TX_OFFSET, enabled);\n}\n/* Function Name:\n *      rtl8367c_getAsicPortMirrorTxFunction\n * Description:\n *      Get the mirror function on TX of the mirrored\n * Input:\n *      pEnabled    - 1: enabled, 0: disabled\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicPortMirrorTxFunction(rtk_uint32* pEnabled)\n{\n    return rtl8367c_getAsicRegBit(RTL8367C_MIRROR_CTRL_REG, RTL8367C_MIRROR_TX_OFFSET, pEnabled);\n}\n/* Function Name:\n *      rtl8367c_setAsicPortMirrorIsolation\n * Description:\n *      Set the traffic isolation on monitor port\n * Input:\n *      enabled     - 1: enabled, 0: disabled\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicPortMirrorIsolation(rtk_uint32 enabled)\n{\n    return rtl8367c_setAsicRegBit(RTL8367C_MIRROR_CTRL_REG, RTL8367C_MIRROR_ISO_OFFSET, enabled);\n}\n/* Function Name:\n *      rtl8367c_getAsicPortMirrorIsolation\n * Description:\n *      Get the traffic isolation on monitor port\n * Input:\n *      pEnabled    - 1: enabled, 0: disabled\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicPortMirrorIsolation(rtk_uint32* pEnabled)\n{\n    return rtl8367c_getAsicRegBit(RTL8367C_MIRROR_CTRL_REG, RTL8367C_MIRROR_ISO_OFFSET, pEnabled);\n}\n\n/* Function Name:\n *      rtl8367c_setAsicPortMirrorMask\n * Description:\n *      Set mirror source port mask\n * Input:\n *      SourcePortmask  - Source Portmask\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n *      RT_ERR_PORT_MASK- Port Mask Error\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicPortMirrorMask(rtk_uint32 SourcePortmask)\n{\n    if( SourcePortmask > RTL8367C_PORTMASK)\n        return RT_ERR_PORT_MASK;\n\n    return rtl8367c_setAsicRegBits(RTL8367C_REG_MIRROR_SRC_PMSK, RTL8367C_MIRROR_SRC_PMSK_MASK, SourcePortmask);\n}\n\n/* Function Name:\n *      rtl8367c_getAsicPortMirrorMask\n * Description:\n *      Get mirror source port mask\n * Input:\n *      None\n * Output:\n *      pSourcePortmask     - Source Portmask\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n *      RT_ERR_PORT_MASK- Port Mask Error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicPortMirrorMask(rtk_uint32 *pSourcePortmask)\n{\n    return rtl8367c_getAsicRegBits(RTL8367C_REG_MIRROR_SRC_PMSK, RTL8367C_MIRROR_SRC_PMSK_MASK, pSourcePortmask);\n}\n\n/* Function Name:\n *      rtl8367c_setAsicPortMirrorVlanRxLeaky\n * Description:\n *      Set the mirror function of VLAN RX leaky\n * Input:\n *      enabled     - 1: enabled, 0: disabled\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicPortMirrorVlanRxLeaky(rtk_uint32 enabled)\n{\n    return rtl8367c_setAsicRegBit(RTL8367C_REG_MIRROR_CTRL2, RTL8367C_MIRROR_RX_VLAN_LEAKY_OFFSET, enabled);\n}\n/* Function Name:\n *      rtl8367c_getAsicPortMirrorVlanRxLeaky\n * Description:\n *      Get the mirror function of VLAN RX leaky\n * Input:\n *      pEnabled    - 1: enabled, 0: disabled\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicPortMirrorVlanRxLeaky(rtk_uint32* pEnabled)\n{\n    return rtl8367c_getAsicRegBit(RTL8367C_REG_MIRROR_CTRL2, RTL8367C_MIRROR_RX_VLAN_LEAKY_OFFSET, pEnabled);\n}\n\n/* Function Name:\n *      rtl8367c_setAsicPortMirrorVlanTxLeaky\n * Description:\n *      Set the mirror function of VLAN TX leaky\n * Input:\n *      enabled     - 1: enabled, 0: disabled\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicPortMirrorVlanTxLeaky(rtk_uint32 enabled)\n{\n    return rtl8367c_setAsicRegBit(RTL8367C_REG_MIRROR_CTRL2, RTL8367C_MIRROR_TX_VLAN_LEAKY_OFFSET, enabled);\n}\n/* Function Name:\n *      rtl8367c_getAsicPortMirrorVlanTxLeaky\n * Description:\n *      Get the mirror function of VLAN TX leaky\n * Input:\n *      pEnabled    - 1: enabled, 0: disabled\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicPortMirrorVlanTxLeaky(rtk_uint32* pEnabled)\n{\n    return rtl8367c_getAsicRegBit(RTL8367C_REG_MIRROR_CTRL2, RTL8367C_MIRROR_TX_VLAN_LEAKY_OFFSET, pEnabled);\n}\n\n/* Function Name:\n *      rtl8367c_setAsicPortMirrorIsolationRxLeaky\n * Description:\n *      Set the mirror function of  Isolation RX leaky\n * Input:\n *      enabled     - 1: enabled, 0: disabled\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicPortMirrorIsolationRxLeaky(rtk_uint32 enabled)\n{\n    return rtl8367c_setAsicRegBit(RTL8367C_REG_MIRROR_CTRL2, RTL8367C_MIRROR_RX_ISOLATION_LEAKY_OFFSET, enabled);\n}\n/* Function Name:\n *      rtl8367c_getAsicPortMirrorIsolationRxLeaky\n * Description:\n *      Get the mirror function of VLAN RX leaky\n * Input:\n *      pEnabled    - 1: enabled, 0: disabled\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicPortMirrorIsolationRxLeaky(rtk_uint32* pEnabled)\n{\n    return rtl8367c_getAsicRegBit(RTL8367C_REG_MIRROR_CTRL2, RTL8367C_MIRROR_RX_ISOLATION_LEAKY_OFFSET, pEnabled);\n}\n\n/* Function Name:\n *      rtl8367c_setAsicPortMirrorIsolationTxLeaky\n * Description:\n *      Set the mirror function of Isolation TX leaky\n * Input:\n *      enabled     - 1: enabled, 0: disabled\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicPortMirrorIsolationTxLeaky(rtk_uint32 enabled)\n{\n    return rtl8367c_setAsicRegBit(RTL8367C_REG_MIRROR_CTRL2, RTL8367C_MIRROR_TX_ISOLATION_LEAKY_OFFSET, enabled);\n}\n/* Function Name:\n *      rtl8367c_getAsicPortMirrorIsolationTxLeaky\n * Description:\n *      Get the mirror function of VLAN TX leaky\n * Input:\n *      pEnabled    - 1: enabled, 0: disabled\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicPortMirrorIsolationTxLeaky(rtk_uint32* pEnabled)\n{\n    return rtl8367c_getAsicRegBit(RTL8367C_REG_MIRROR_CTRL2, RTL8367C_MIRROR_TX_ISOLATION_LEAKY_OFFSET, pEnabled);\n}\n\n/* Function Name:\n *      rtl8367c_setAsicPortMirrorRealKeep\n * Description:\n *      Set the mirror function of keep format\n * Input:\n *      mode    - 1: keep original format, 0: follow VLAN config\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicPortMirrorRealKeep(rtk_uint32 mode)\n{\n    return rtl8367c_setAsicRegBit(RTL8367C_REG_MIRROR_CTRL2, RTL8367C_MIRROR_REALKEEP_EN_OFFSET, mode);\n}\n/* Function Name:\n *      rtl8367c_getAsicPortMirrorRealKeep\n * Description:\n *      Get the mirror function of keep format\n * Input:\n *      pMode   - 1: keep original format, 0: follow VLAN config\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicPortMirrorRealKeep(rtk_uint32* pMode)\n{\n    return rtl8367c_getAsicRegBit(RTL8367C_REG_MIRROR_CTRL2, RTL8367C_MIRROR_REALKEEP_EN_OFFSET, pMode);\n}\n\n/* Function Name:\n *      rtl8367c_setAsicPortMirrorOverride\n * Description:\n *      Set the mirror function of override\n * Input:\n *      rxMirror    - 1: output rx Mirror format, 0: output forward format\n *      txMirror    - 1: output tx Mirror format, 0: output forward format\n *      aclMirror   - 1: output ACL Mirror format, 0: output forward format\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicPortMirrorOverride(rtk_uint32 rxMirror, rtk_uint32 txMirror, rtk_uint32 aclMirror)\n{\n    ret_t retVal;\n\n    if((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_MIRROR_CTRL3, RTL8367C_MIRROR_RX_OVERRIDE_EN_OFFSET, rxMirror)) != RT_ERR_OK)\n        return retVal;\n\n    if((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_MIRROR_CTRL3, RTL8367C_MIRROR_TX_OVERRIDE_EN_OFFSET, txMirror)) != RT_ERR_OK)\n        return retVal;\n\n    if((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_MIRROR_CTRL3, RTL8367C_MIRROR_ACL_OVERRIDE_EN_OFFSET, aclMirror)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtl8367c_getAsicPortMirrorOverride\n * Description:\n *      Get the mirror function of override\n * Input:\n *      None\n * Output:\n *      pRxMirror   - 1: output rx Mirror format, 0: output forward format\n *      pTxMirror   - 1: output tx Mirror format, 0: output forward format\n *      pAclMirror  - 1: output ACL Mirror format, 0: output forward format\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicPortMirrorOverride(rtk_uint32 *pRxMirror, rtk_uint32 *pTxMirror, rtk_uint32 *pAclMirror)\n{\n    ret_t retVal;\n\n    if((retVal = rtl8367c_getAsicRegBit(RTL8367C_REG_MIRROR_CTRL3, RTL8367C_MIRROR_RX_OVERRIDE_EN_OFFSET, pRxMirror)) != RT_ERR_OK)\n        return retVal;\n\n    if((retVal = rtl8367c_getAsicRegBit(RTL8367C_REG_MIRROR_CTRL3, RTL8367C_MIRROR_TX_OVERRIDE_EN_OFFSET, pTxMirror)) != RT_ERR_OK)\n        return retVal;\n\n    if((retVal = rtl8367c_getAsicRegBit(RTL8367C_REG_MIRROR_CTRL3, RTL8367C_MIRROR_ACL_OVERRIDE_EN_OFFSET, pAclMirror)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_misc.c",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * $Revision: 76306 $\n * $Date: 2017-03-08 15:13:58 +0800 (週三, 08 三月 2017) $\n *\n * Purpose : RTL8367C switch high-level API for RTL8367C\n * Feature : Miscellaneous functions\n *\n */\n\n#include <rtl8367c_asicdrv_misc.h>\n/* Function Name:\n *      rtl8367c_setAsicMacAddress\n * Description:\n *      Set switch MAC address\n * Input:\n *      mac     - switch mac\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicMacAddress(ether_addr_t mac)\n{\n    ret_t retVal;\n    rtk_uint32 regData;\n    rtk_uint8 *accessPtr;\n    rtk_uint32 i;\n\n    accessPtr =  (rtk_uint8*)&mac;\n\n    regData = *accessPtr;\n    accessPtr ++;\n    regData = (regData << 8) | *accessPtr;\n    accessPtr ++;\n    for(i = 0; i <=2; i++)\n    {\n        retVal = rtl8367c_setAsicReg(RTL8367C_REG_SWITCH_MAC2 - i, regData);\n        if(retVal != RT_ERR_OK)\n            return retVal;\n\n        regData = *accessPtr;\n        accessPtr ++;\n        regData = (regData << 8) | *accessPtr;\n        accessPtr ++;\n    }\n\n    return retVal;\n}\n/* Function Name:\n *      rtl8367c_getAsicMacAddress\n * Description:\n *      Get switch MAC address\n * Input:\n *      pMac    - switch mac\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicMacAddress(ether_addr_t *pMac)\n{\n    ret_t retVal;\n    rtk_uint32 regData;\n    rtk_uint8 *accessPtr;\n    rtk_uint32 i;\n\n\n    accessPtr = (rtk_uint8*)pMac;\n\n    for(i = 0; i <= 2; i++)\n    {\n        retVal = rtl8367c_getAsicReg(RTL8367C_REG_SWITCH_MAC2 - i, &regData);\n        if(retVal != RT_ERR_OK)\n            return retVal;\n\n        *accessPtr = (regData & 0xFF00) >> 8;\n        accessPtr ++;\n        *accessPtr = regData & 0xFF;\n        accessPtr ++;\n    }\n\n    return retVal;\n}\n/* Function Name:\n *      rtl8367c_getAsicDebugInfo\n * Description:\n *      Get per-port packet forward debugging information\n * Input:\n *      port        - Physical port number (0~7)\n *      pDebugifo   - per-port packet trap/drop/forward reason\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n *      RT_ERR_PORT_ID  - Invalid port number\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicDebugInfo(rtk_uint32 port, rtk_uint32 *pDebugifo)\n{\n    if(port > RTL8367C_PORTIDMAX)\n        return RT_ERR_PORT_ID;\n\n    return rtl8367c_getAsicRegBits(RTL8367C_DEBUG_INFO_REG(port), RTL8367C_DEBUG_INFO_MASK(port), pDebugifo);\n}\n/* Function Name:\n *      rtl8367c_setAsicPortJamMode\n * Description:\n *      Set half duplex flow control setting\n * Input:\n *      mode    - 0: Back-Pressure 1: DEFER\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicPortJamMode(rtk_uint32 mode)\n{\n    return rtl8367c_setAsicRegBit(RTL8367C_REG_CFG_BACKPRESSURE, RTL8367C_LONGTXE_OFFSET,mode);\n}\n/* Function Name:\n *      rtl8367c_getAsicPortJamMode\n * Description:\n *      Get half duplex flow control setting\n * Input:\n *      pMode   - 0: Back-Pressure 1: DEFER\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicPortJamMode(rtk_uint32* pMode)\n{\n    return rtl8367c_getAsicRegBit(RTL8367C_REG_CFG_BACKPRESSURE, RTL8367C_LONGTXE_OFFSET, pMode);\n}\n\n/* Function Name:\n *      rtl8367c_setAsicMaxLengthCfg\n * Description:\n *      Set Max packet length configuration\n * Input:\n *      cfgId       - Configuration ID\n *      maxLength   - Max Length\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicMaxLengthCfg(rtk_uint32 cfgId, rtk_uint32 maxLength)\n{\n    return rtl8367c_setAsicRegBits(RTL8367C_REG_MAX_LEN_RX_TX_CFG0 + cfgId, RTL8367C_MAX_LEN_RX_TX_CFG0_MASK, maxLength);\n}\n\n/* Function Name:\n *      rtl8367c_getAsicMaxLengthCfg\n * Description:\n *      Get Max packet length configuration\n * Input:\n *      cfgId       - Configuration ID\n *      maxLength   - Max Length\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicMaxLengthCfg(rtk_uint32 cfgId, rtk_uint32 *pMaxLength)\n{\n    return rtl8367c_getAsicRegBits(RTL8367C_REG_MAX_LEN_RX_TX_CFG0 + cfgId, RTL8367C_MAX_LEN_RX_TX_CFG0_MASK, pMaxLength);\n}\n\n/* Function Name:\n *      rtl8367c_setAsicMaxLength\n * Description:\n *      Set Max packet length\n * Input:\n *      port        - port ID\n *      type        - 0: 10M/100M speed, 1: giga speed\n *      cfgId       - Configuration ID\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicMaxLength(rtk_uint32 port, rtk_uint32 type, rtk_uint32 cfgId)\n{\n    ret_t retVal;\n\n    if(port < 8)\n    {\n        retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_MAX_LENGTH_CFG, (type * 8) + port, cfgId);\n        if(retVal != RT_ERR_OK)\n            return retVal;\n    }\n    else\n    {\n        retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_MAX_LENGTH_CFG_EXT, (type * 3) + port - 8, cfgId);\n        if(retVal != RT_ERR_OK)\n            return retVal;\n    }\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtl8367c_getAsicMaxLength\n * Description:\n *      Get Max packet length\n * Input:\n *      port        - port ID\n *      type        - 0: 10M/100M speed, 1: giga speed\n *      cfgId       - Configuration ID\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicMaxLength(rtk_uint32 port, rtk_uint32 type, rtk_uint32 *pCfgId)\n{\n    ret_t retVal;\n\n    if(port < 8)\n    {\n        retVal = rtl8367c_getAsicRegBit(RTL8367C_REG_MAX_LENGTH_CFG, (type * 8) + port, pCfgId);\n        if(retVal != RT_ERR_OK)\n            return retVal;\n    }\n    else\n    {\n        retVal = rtl8367c_getAsicRegBit(RTL8367C_REG_MAX_LENGTH_CFG_EXT, (type * 3) + port - 8, pCfgId);\n        if(retVal != RT_ERR_OK)\n            return retVal;\n    }\n    return RT_ERR_OK;\n}\n\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_oam.c",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * $Revision: 42321 $\n * $Date: 2013-08-26 13:51:29 +0800 (週一, 26 八月 2013) $\n *\n * Purpose : RTL8367C switch high-level API for RTL8367C\n * Feature : OAM related functions\n *\n */\n\n#include <rtl8367c_asicdrv_oam.h>\n/* Function Name:\n *      rtl8367c_setAsicOamParser\n * Description:\n *      Set OAM parser state\n * Input:\n *      port    - Physical port number (0~7)\n *      parser  - Per-Port OAM parser state\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number\n *      RT_ERR_NOT_ALLOWED  - Invalid paser state\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicOamParser(rtk_uint32 port, rtk_uint32 parser)\n{\n    if(port >= RTL8367C_PORTNO)\n        return RT_ERR_PORT_ID;\n\n    if(parser > OAM_PARFWDCPU)\n        return RT_ERR_NOT_ALLOWED;\n\n    return rtl8367c_setAsicRegBits(RTL8367C_REG_OAM_PARSER_CTRL0 + port/8, RTL8367C_OAM_PARSER_MASK(port % 8), parser);\n}\n/* Function Name:\n *      rtl8367c_getAsicOamParser\n * Description:\n *      Get OAM parser state\n * Input:\n *      port    - Physical port number (0~7)\n *      pParser     - Per-Port OAM parser state\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n *      RT_ERR_PORT_ID  - Invalid port number\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicOamParser(rtk_uint32 port, rtk_uint32* pParser)\n{\n    if(port >= RTL8367C_PORTNO)\n        return RT_ERR_PORT_ID;\n\n    return rtl8367c_getAsicRegBits(RTL8367C_REG_OAM_PARSER_CTRL0 + port/8, RTL8367C_OAM_PARSER_MASK(port%8), pParser);\n}\n/* Function Name:\n *      rtl8367c_setAsicOamMultiplexer\n * Description:\n *      Set OAM multiplexer state\n * Input:\n *      port        - Physical port number (0~7)\n *      multiplexer - Per-Port OAM multiplexer state\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number\n *      RT_ERR_NOT_ALLOWED  - Invalid multiplexer state\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicOamMultiplexer(rtk_uint32 port, rtk_uint32 multiplexer)\n{\n    if(port >= RTL8367C_PORTNO)\n        return RT_ERR_PORT_ID;\n\n    if(multiplexer > OAM_MULCPU)\n        return RT_ERR_NOT_ALLOWED;\n\n    return rtl8367c_setAsicRegBits(RTL8367C_REG_OAM_MULTIPLEXER_CTRL0 + port/8, RTL8367C_OAM_MULTIPLEXER_MASK(port%8), multiplexer);\n}\n/* Function Name:\n *      rtl8367c_getAsicOamMultiplexer\n * Description:\n *      Get OAM multiplexer state\n * Input:\n *      port        - Physical port number (0~7)\n *      pMultiplexer - Per-Port OAM multiplexer state\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n *      RT_ERR_PORT_ID  - Invalid port number\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicOamMultiplexer(rtk_uint32 port, rtk_uint32* pMultiplexer)\n{\n    if(port >= RTL8367C_PORTNO)\n        return RT_ERR_PORT_ID;\n\n    return rtl8367c_getAsicRegBits(RTL8367C_REG_OAM_MULTIPLEXER_CTRL0 + port/8, RTL8367C_OAM_MULTIPLEXER_MASK(port%8), pMultiplexer);\n}\n/* Function Name:\n *      rtl8367c_setAsicOamCpuPri\n * Description:\n *      Set trap priority for OAM packet\n * Input:\n *      priority    - priority (0~7)\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK                   - Success\n *      RT_ERR_SMI                  - SMI access error\n *      RT_ERR_QOS_INT_PRIORITY     - Invalid priority\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicOamCpuPri(rtk_uint32 priority)\n{\n    if(priority > RTL8367C_PRIMAX)\n        return RT_ERR_QOS_INT_PRIORITY;\n\n    return rtl8367c_setAsicRegBits(RTL8367C_REG_QOS_TRAP_PRIORITY0, RTL8367C_OAM_PRIOIRTY_MASK, priority);\n}\n/* Function Name:\n *      rtl8367c_getAsicOamCpuPri\n * Description:\n *      Get trap priority for OAM packet\n * Input:\n *      pPriority   - priority (0~7)\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicOamCpuPri(rtk_uint32 *pPriority)\n{\n    return rtl8367c_getAsicRegBits(RTL8367C_REG_QOS_TRAP_PRIORITY0, RTL8367C_OAM_PRIOIRTY_MASK, pPriority);\n}\n/* Function Name:\n *      rtl8367c_setAsicOamEnable\n * Description:\n *      Set OAM function state\n * Input:\n *      enabled     - OAM function usage 1:enable, 0:disabled\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicOamEnable(rtk_uint32 enabled)\n{\n    return rtl8367c_setAsicRegBit(RTL8367C_REG_OAM_CTRL, RTL8367C_OAM_CTRL_OFFSET, enabled);\n}\n/* Function Name:\n *      rtl8367c_getAsicOamEnable\n * Description:\n *      Get OAM function state\n * Input:\n *      pEnabled    - OAM function usage 1:enable, 0:disabled\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicOamEnable(rtk_uint32 *pEnabled)\n{\n    return rtl8367c_getAsicRegBit(RTL8367C_REG_OAM_CTRL, RTL8367C_OAM_CTRL_OFFSET, pEnabled);\n}\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_phy.c",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * $Revision: 76306 $\n * $Date: 2017-03-08 15:13:58 +0800 (週三, 08 三月 2017) $\n *\n * Purpose : RTL8367C switch high-level API for RTL8367C\n * Feature : PHY related functions\n *\n */\n#include <rtl8367c_asicdrv_phy.h>\n\n#if defined(MDC_MDIO_OPERATION)\n/* Function Name:\n *      rtl8367c_setAsicPHYOCPReg\n * Description:\n *      Set PHY OCP registers\n * Input:\n *      phyNo   - Physical port number (0~7)\n *      ocpAddr - OCP address\n *      ocpData - Writing data\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - Success\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_PHY_REG_ID       - invalid PHY address\n *      RT_ERR_PHY_ID           - invalid PHY no\n *      RT_ERR_BUSYWAIT_TIMEOUT - PHY access busy\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicPHYOCPReg(rtk_uint32 phyNo, rtk_uint32 ocpAddr, rtk_uint32 ocpData )\n{\n    ret_t retVal;\n    rtk_uint32 regAddr;\n    rtk_uint32 ocpAddrPrefix, ocpAddr9_6, ocpAddr5_1;\n\n    /* OCP prefix */\n    ocpAddrPrefix = ((ocpAddr & 0xFC00) >> 10);\n    if((retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_GPHY_OCP_MSB_0, RTL8367C_CFG_CPU_OCPADR_MSB_MASK, ocpAddrPrefix)) != RT_ERR_OK)\n        return retVal;\n\n    /*prepare access address*/\n    ocpAddr9_6 = ((ocpAddr >> 6) & 0x000F);\n    ocpAddr5_1 = ((ocpAddr >> 1) & 0x001F);\n    regAddr = RTL8367C_PHY_BASE | (ocpAddr9_6 << 8) | (phyNo << RTL8367C_PHY_OFFSET) | ocpAddr5_1;\n    if((retVal = rtl8367c_setAsicReg(regAddr, ocpData)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtl8367c_getAsicPHYOCPReg\n * Description:\n *      Get PHY OCP registers\n * Input:\n *      phyNo   - Physical port number (0~7)\n *      ocpAddr - PHY address\n *      pRegData - read data\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - Success\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_PHY_REG_ID       - invalid PHY address\n *      RT_ERR_PHY_ID           - invalid PHY no\n *      RT_ERR_BUSYWAIT_TIMEOUT - PHY access busy\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicPHYOCPReg(rtk_uint32 phyNo, rtk_uint32 ocpAddr, rtk_uint32 *pRegData )\n{\n    ret_t retVal;\n    rtk_uint32 regAddr;\n    rtk_uint32 ocpAddrPrefix, ocpAddr9_6, ocpAddr5_1;\n    /* OCP prefix */\n    ocpAddrPrefix = ((ocpAddr & 0xFC00) >> 10);\n    if((retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_GPHY_OCP_MSB_0, RTL8367C_CFG_CPU_OCPADR_MSB_MASK, ocpAddrPrefix)) != RT_ERR_OK)\n        return retVal;\n\n    /*prepare access address*/\n    ocpAddr9_6 = ((ocpAddr >> 6) & 0x000F);\n    ocpAddr5_1 = ((ocpAddr >> 1) & 0x001F);\n    regAddr = RTL8367C_PHY_BASE | (ocpAddr9_6 << 8) | (phyNo << RTL8367C_PHY_OFFSET) | ocpAddr5_1;\n    if((retVal = rtl8367c_getAsicReg(regAddr, pRegData)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n#else\n\n/* Function Name:\n *      rtl8367c_setAsicPHYOCPReg\n * Description:\n *      Set PHY OCP registers\n * Input:\n *      phyNo   - Physical port number (0~7)\n *      ocpAddr - OCP address\n *      ocpData - Writing data\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - Success\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_PHY_REG_ID       - invalid PHY address\n *      RT_ERR_PHY_ID           - invalid PHY no\n *      RT_ERR_BUSYWAIT_TIMEOUT - PHY access busy\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicPHYOCPReg(rtk_uint32 phyNo, rtk_uint32 ocpAddr, rtk_uint32 ocpData )\n{\n    ret_t retVal;\n    rtk_uint32 regData;\n    rtk_uint32 busyFlag, checkCounter;\n    rtk_uint32 ocpAddrPrefix, ocpAddr9_6, ocpAddr5_1;\n\n    /*Check internal phy access busy or not*/\n    /*retVal = rtl8367c_getAsicRegBit(RTL8367C_REG_INDRECT_ACCESS_STATUS, RTL8367C_INDRECT_ACCESS_STATUS_OFFSET,&busyFlag);*/\n    retVal = rtl8367c_getAsicReg(RTL8367C_REG_INDRECT_ACCESS_STATUS,&busyFlag);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    if(busyFlag)\n        return RT_ERR_BUSYWAIT_TIMEOUT;\n\n    /* OCP prefix */\n    ocpAddrPrefix = ((ocpAddr & 0xFC00) >> 10);\n    if((retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_GPHY_OCP_MSB_0, RTL8367C_CFG_CPU_OCPADR_MSB_MASK, ocpAddrPrefix)) != RT_ERR_OK)\n        return retVal;\n\n    /*prepare access data*/\n    retVal = rtl8367c_setAsicReg(RTL8367C_REG_INDRECT_ACCESS_WRITE_DATA, ocpData);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    /*prepare access address*/\n    ocpAddr9_6 = ((ocpAddr >> 6) & 0x000F);\n    ocpAddr5_1 = ((ocpAddr >> 1) & 0x001F);\n    regData = RTL8367C_PHY_BASE | (ocpAddr9_6 << 8) | (phyNo << RTL8367C_PHY_OFFSET) | ocpAddr5_1;\n    retVal = rtl8367c_setAsicReg(RTL8367C_REG_INDRECT_ACCESS_ADDRESS, regData);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    /*Set WRITE Command*/\n    retVal = rtl8367c_setAsicReg(RTL8367C_REG_INDRECT_ACCESS_CTRL, RTL8367C_CMD_MASK | RTL8367C_RW_MASK);\n\n    checkCounter = 100;\n    while(checkCounter)\n    {\n        retVal = rtl8367c_getAsicReg(RTL8367C_REG_INDRECT_ACCESS_STATUS,&busyFlag);\n        if((retVal != RT_ERR_OK) || busyFlag)\n        {\n            checkCounter --;\n            if(0 == checkCounter)\n                return RT_ERR_BUSYWAIT_TIMEOUT;\n        }\n        else\n        {\n            checkCounter = 0;\n        }\n    }\n\n    return retVal;\n}\n/* Function Name:\n *      rtl8367c_getAsicPHYOCPReg\n * Description:\n *      Get PHY OCP registers\n * Input:\n *      phyNo   - Physical port number (0~7)\n *      ocpAddr - PHY address\n *      pRegData - read data\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - Success\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_PHY_REG_ID       - invalid PHY address\n *      RT_ERR_PHY_ID           - invalid PHY no\n *      RT_ERR_BUSYWAIT_TIMEOUT - PHY access busy\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicPHYOCPReg(rtk_uint32 phyNo, rtk_uint32 ocpAddr, rtk_uint32 *pRegData )\n{\n    ret_t retVal;\n    rtk_uint32 regData;\n    rtk_uint32 busyFlag,checkCounter;\n    rtk_uint32 ocpAddrPrefix, ocpAddr9_6, ocpAddr5_1;\n    /*Check internal phy access busy or not*/\n    /*retVal = rtl8367c_getAsicRegBit(RTL8367C_REG_INDRECT_ACCESS_STATUS, RTL8367C_INDRECT_ACCESS_STATUS_OFFSET,&busyFlag);*/\n    retVal = rtl8367c_getAsicReg(RTL8367C_REG_INDRECT_ACCESS_STATUS,&busyFlag);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    if(busyFlag)\n        return RT_ERR_BUSYWAIT_TIMEOUT;\n\n    /* OCP prefix */\n    ocpAddrPrefix = ((ocpAddr & 0xFC00) >> 10);\n    if((retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_GPHY_OCP_MSB_0, RTL8367C_CFG_CPU_OCPADR_MSB_MASK, ocpAddrPrefix)) != RT_ERR_OK)\n        return retVal;\n\n    /*prepare access address*/\n    ocpAddr9_6 = ((ocpAddr >> 6) & 0x000F);\n    ocpAddr5_1 = ((ocpAddr >> 1) & 0x001F);\n    regData = RTL8367C_PHY_BASE | (ocpAddr9_6 << 8) | (phyNo << RTL8367C_PHY_OFFSET) | ocpAddr5_1;\n    retVal = rtl8367c_setAsicReg(RTL8367C_REG_INDRECT_ACCESS_ADDRESS, regData);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    /*Set READ Command*/\n    retVal = rtl8367c_setAsicReg(RTL8367C_REG_INDRECT_ACCESS_CTRL, RTL8367C_CMD_MASK );\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    checkCounter = 100;\n    while(checkCounter)\n    {\n        retVal = rtl8367c_getAsicReg(RTL8367C_REG_INDRECT_ACCESS_STATUS,&busyFlag);\n        if((retVal != RT_ERR_OK) || busyFlag)\n        {\n            checkCounter --;\n            if(0 == checkCounter)\n                return RT_ERR_FAILED;\n        }\n        else\n        {\n            checkCounter = 0;\n        }\n    }\n\n    /*get PHY register*/\n    retVal = rtl8367c_getAsicReg(RTL8367C_REG_INDRECT_ACCESS_READ_DATA, &regData);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    *pRegData = regData;\n\n    return RT_ERR_OK;\n}\n\n#endif\n\n/* Function Name:\n *      rtl8367c_setAsicPHYReg\n * Description:\n *      Set PHY registers\n * Input:\n *      phyNo   - Physical port number (0~7)\n *      phyAddr - PHY address (0~31)\n *      phyData - Writing data\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - Success\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_PHY_REG_ID       - invalid PHY address\n *      RT_ERR_PHY_ID           - invalid PHY no\n *      RT_ERR_BUSYWAIT_TIMEOUT - PHY access busy\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicPHYReg(rtk_uint32 phyNo, rtk_uint32 phyAddr, rtk_uint32 phyData )\n{\n    rtk_uint32 ocp_addr;\n\n    if(phyAddr > RTL8367C_PHY_REGNOMAX)\n        return RT_ERR_PHY_REG_ID;\n\n    ocp_addr = 0xa400 + phyAddr*2;\n\n    return rtl8367c_setAsicPHYOCPReg(phyNo, ocp_addr, phyData);\n}\n/* Function Name:\n *      rtl8367c_getAsicPHYReg\n * Description:\n *      Get PHY registers\n * Input:\n *      phyNo   - Physical port number (0~7)\n *      phyAddr - PHY address (0~31)\n *      pRegData - Writing data\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - Success\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_PHY_REG_ID       - invalid PHY address\n *      RT_ERR_PHY_ID           - invalid PHY no\n *      RT_ERR_BUSYWAIT_TIMEOUT - PHY access busy\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicPHYReg(rtk_uint32 phyNo, rtk_uint32 phyAddr, rtk_uint32 *pRegData )\n{\n    rtk_uint32 ocp_addr;\n\n    if(phyAddr > RTL8367C_PHY_REGNOMAX)\n        return RT_ERR_PHY_REG_ID;\n\n    ocp_addr = 0xa400 + phyAddr*2;\n\n    return rtl8367c_getAsicPHYOCPReg(phyNo, ocp_addr, pRegData);\n}\n\n\n/* Function Name:\n *      rtl8367c_setAsicSdsReg\n * Description:\n *      Set Serdes registers\n * Input:\n *      sdsId   - sdsid (0~1)\n *      sdsReg - reg address (0~31)\n *      sdsPage - Writing data\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - Success\n\n * Note:\n *      None\n */\n\nret_t rtl8367c_setAsicSdsReg(rtk_uint32 sdsId, rtk_uint32 sdsReg, rtk_uint32 sdsPage,  rtk_uint32 value)\n{\n    rtk_uint32 retVal;\n\n    if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_DATA, value)) != RT_ERR_OK)\n        return retVal;\n\n    if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_ADR, (sdsPage<<5) | sdsReg)) != RT_ERR_OK)\n        return retVal;\n\n    if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_CMD, 0x00C0|sdsId)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n\n}\n\n/* Function Name:\n *      rtl8367c_getAiscSdsReg\n * Description:\n *      Get Serdes registers\n * Input:\n *      sdsId   - sdsid (0~1)\n *      sdsReg - reg address (0~31)\n *      sdsPage - Writing data\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - Success\n\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicSdsReg(rtk_uint32 sdsId, rtk_uint32 sdsReg, rtk_uint32 sdsPage, rtk_uint32 *value)\n{\n    rtk_uint32 retVal, busy;\n\n    if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_ADR, (sdsPage<<5) | sdsReg)) != RT_ERR_OK)\n        return retVal;\n\n    if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_CMD, 0x0080|sdsId)) != RT_ERR_OK)\n        return retVal;\n\n    while(1)\n    {\n        if ((retVal = rtl8367c_getAsicReg(RTL8367C_REG_SDS_INDACS_CMD, &busy))!=RT_ERR_OK)\n            return retVal;\n\n        if ((busy & 0x100) == 0)\n            break;\n    }\n\n    if ((retVal = rtl8367c_getAsicReg(RTL8367C_REG_SDS_INDACS_DATA, value))!=RT_ERR_OK)\n            return retVal;\n\n    return RT_ERR_OK;\n}\n\n\n\n\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_port.c",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * $Revision: 76333 $\n * $Date: 2017-03-09 09:33:15 +0800 (週四, 09 三月 2017) $\n *\n * Purpose : RTL8367C switch high-level API for RTL8367C\n * Feature : Port security related functions\n *\n */\n\n#include <rtl8367c_asicdrv_port.h>\n\n#include <string.h>\n\n\n#define FIBER2_AUTO_INIT_SIZE 2038\nrtk_uint8 Fiber2_Auto[FIBER2_AUTO_INIT_SIZE] = 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n0x01,0x0F,0xC3,0x12,0x00,0xF2,0x50,0x1B,\n0x90,0x06,0x24,0x12,0x01,0x03,0xEF,0x24,\n0x01,0xFF,0xE4,0x3E,0xFE,0xE4,0x3D,0xFD,\n0xE4,0x3C,0xFC,0x90,0x06,0x24,0x12,0x01,\n0x1B,0x80,0xD1,0xC2,0x00,0xC2,0x01,0xD2,\n0xA9,0xD2,0x8C,0x7F,0x01,0x7E,0x62,0x12,\n0x07,0x66,0xEF,0x30,0xE2,0x07,0xE4,0x90,\n0x06,0x2C,0xF0,0x80,0xEE,0x90,0x06,0x2C,\n0xE0,0x70,0x12,0x12,0x04,0xF0,0x90,0x06,\n0x2C,0x74,0x01,0xF0,0xE4,0x90,0x06,0x33,\n0xF0,0xA3,0xF0,0x80,0xD6,0xC3,0x90,0x06,\n0x34,0xE0,0x94,0x62,0x90,0x06,0x33,0xE0,\n0x94,0x00,0x40,0xC7,0xE4,0xF0,0xA3,0xF0,\n0x12,0x04,0xF0,0x90,0x06,0x2C,0x74,0x01,\n0xF0,0x80,0xB8,0x75,0x0F,0x80,0x75,0x0E,\n0x7E,0x75,0x0D,0xAA,0x75,0x0C,0x83,0xE4,\n0xF5,0x10,0x7F,0x36,0x7E,0x13,0x12,0x07,\n0x66,0xEE,0xC4,0xF8,0x54,0xF0,0xC8,0xEF,\n0xC4,0x54,0x0F,0x48,0x54,0x07,0xFB,0x7A,\n0x00,0xEA,0x70,0x4A,0xEB,0x14,0x60,0x1C,\n0x14,0x60,0x27,0x24,0xFE,0x60,0x31,0x14,\n0x60,0x3C,0x24,0x05,0x70,0x38,0x75,0x0B,\n0x00,0x75,0x0A,0xC2,0x75,0x09,0xEB,0x75,\n0x08,0x0B,0x80,0x36,0x75,0x0B,0x40,0x75,\n0x0A,0x59,0x75,0x09,0x73,0x75,0x08,0x07,\n0x80,0x28,0x75,0x0B,0x00,0x75,0x0A,0xE1,\n0x75,0x09,0xF5,0x75,0x08,0x05,0x80,0x1A,\n0x75,0x0B,0xA0,0x75,0x0A,0xAC,0x75,0x09,\n0xB9,0x75,0x08,0x03,0x80,0x0C,0x75,0x0B,\n0x00,0x75,0x0A,0x62,0x75,0x09,0x3D,0x75,\n0x08,0x01,0x75,0x89,0x11,0xE4,0x7B,0x60,\n0x7A,0x09,0xF9,0xF8,0xAF,0x0B,0xAE,0x0A,\n0xAD,0x09,0xAC,0x08,0x12,0x00,0x60,0xAA,\n0x06,0xAB,0x07,0xC3,0xE4,0x9B,0xFB,0xE4,\n0x9A,0xFA,0x78,0x17,0xF6,0xAF,0x03,0xEF,\n0x08,0xF6,0x18,0xE6,0xF5,0x8C,0x08,0xE6,\n0xF5,0x8A,0x74,0x0D,0x2B,0xFB,0xE4,0x3A,\n0x18,0xF6,0xAF,0x03,0xEF,0x08,0xF6,0x75,\n0x88,0x10,0x53,0x8E,0xC7,0xD2,0xA9,0x22,\n0x7F,0x10,0x7E,0x13,0x12,0x07,0x66,0x90,\n0x06,0x2D,0xEE,0xF0,0xA3,0xEF,0xF0,0xEE,\n0x44,0x10,0xFE,0x90,0x06,0x2D,0xF0,0xA3,\n0xEF,0xF0,0x54,0xEF,0xFF,0x90,0x06,0x2D,\n0xEE,0xF0,0xFC,0xA3,0xEF,0xF0,0xFD,0x7F,\n0x10,0x7E,0x13,0x12,0x07,0xAB,0xE4,0xFF,\n0xFE,0x0F,0xBF,0x00,0x01,0x0E,0xEF,0x64,\n0x64,0x4E,0x70,0xF5,0x7D,0x04,0x7C,0x00,\n0x7F,0x02,0x7E,0x66,0x12,0x07,0xAB,0x7D,\n0x00,0x7C,0x04,0x7F,0x01,0x7E,0x66,0x12,\n0x07,0xAB,0x7D,0xC0,0x7C,0x00,0x7F,0x00,\n0x7E,0x66,0x12,0x07,0xAB,0xE4,0xFD,0xFC,\n0x7F,0x02,0x7E,0x66,0x12,0x07,0xAB,0x7D,\n0x00,0x7C,0x04,0x7F,0x01,0x7E,0x66,0x12,\n0x07,0xAB,0x7D,0xC0,0x7C,0x00,0x7F,0x00,\n0x7E,0x66,0x12,0x07,0xAB,0x7F,0x10,0x7E,\n0x13,0x12,0x07,0x66,0x90,0x06,0x2D,0xEE,\n0xF0,0xA3,0xEF,0xF0,0xEE,0x54,0xEF,0x90,\n0x06,0x2D,0xF0,0xFC,0xA3,0xEF,0xF0,0xFD,\n0x7F,0x10,0x7E,0x13,0x02,0x07,0xAB,0x78,\n0x7F,0xE4,0xF6,0xD8,0xFD,0x75,0x81,0x3C,\n0x02,0x05,0xD6,0x02,0x03,0x2F,0xE4,0x93,\n0xA3,0xF8,0xE4,0x93,0xA3,0x40,0x03,0xF6,\n0x80,0x01,0xF2,0x08,0xDF,0xF4,0x80,0x29,\n0xE4,0x93,0xA3,0xF8,0x54,0x07,0x24,0x0C,\n0xC8,0xC3,0x33,0xC4,0x54,0x0F,0x44,0x20,\n0xC8,0x83,0x40,0x04,0xF4,0x56,0x80,0x01,\n0x46,0xF6,0xDF,0xE4,0x80,0x0B,0x01,0x02,\n0x04,0x08,0x10,0x20,0x40,0x80,0x90,0x07,\n0xE7,0xE4,0x7E,0x01,0x93,0x60,0xBC,0xA3,\n0xFF,0x54,0x3F,0x30,0xE5,0x09,0x54,0x1F,\n0xFE,0xE4,0x93,0xA3,0x60,0x01,0x0E,0xCF,\n0x54,0xC0,0x25,0xE0,0x60,0xA8,0x40,0xB8,\n0xE4,0x93,0xA3,0xFA,0xE4,0x93,0xA3,0xF8,\n0xE4,0x93,0xA3,0xC8,0xC5,0x82,0xC8,0xCA,\n0xC5,0x83,0xCA,0xF0,0xA3,0xC8,0xC5,0x82,\n0xC8,0xCA,0xC5,0x83,0xCA,0xDF,0xE9,0xDE,\n0xE7,0x80,0xBE,0x7D,0x40,0x7C,0x17,0x7F,\n0x11,0x7E,0x1D,0x12,0x07,0xAB,0x7F,0x41,\n0x7E,0x1D,0x12,0x07,0x66,0xEF,0x44,0x20,\n0x44,0x80,0xFD,0xAC,0x06,0x7F,0x41,0x7E,\n0x1D,0x12,0x07,0xAB,0x7D,0xBB,0x7C,0x15,\n0x7F,0xEB,0x7E,0x13,0x12,0x07,0xAB,0x7D,\n0x07,0x7C,0x00,0x7F,0xE7,0x7E,0x13,0x12,\n0x07,0xAB,0x7D,0x40,0x7C,0x11,0x7F,0x00,\n0x7E,0x62,0x12,0x07,0xAB,0x02,0x02,0x2F,\n0x7D,0xC0,0x7C,0x16,0x7F,0x11,0x7E,0x1D,\n0x12,0x07,0xAB,0x7D,0xBB,0x7C,0x15,0x7F,\n0xEB,0x7E,0x13,0x12,0x07,0xAB,0x7D,0x0D,\n0x7C,0x00,0x7F,0xE7,0x7E,0x13,0x12,0x07,\n0xAB,0x7F,0x41,0x7E,0x1D,0x12,0x07,0x66,\n0xEF,0x44,0x20,0x44,0x80,0xFD,0xAC,0x06,\n0x7F,0x41,0x7E,0x1D,0x12,0x07,0xAB,0x7D,\n0x00,0x7C,0x21,0x7F,0x00,0x7E,0x62,0x12,\n0x07,0xAB,0x02,0x02,0x2F,0x7D,0x40,0x7C,\n0x17,0x7F,0x11,0x7E,0x1D,0x12,0x07,0xAB,\n0x7D,0xBB,0x7C,0x15,0x7F,0xEB,0x7E,0x13,\n0x12,0x07,0xAB,0x7D,0x0C,0x7C,0x00,0x7F,\n0xE7,0x7E,0x13,0x12,0x07,0xAB,0x7F,0x41,\n0x7E,0x1D,0x12,0x07,0x66,0xEF,0x44,0x20,\n0x44,0x80,0xFD,0xAC,0x06,0x7F,0x41,0x7E,\n0x1D,0x12,0x07,0xAB,0x7D,0x40,0x7C,0x11,\n0x7F,0x00,0x7E,0x62,0x12,0x07,0xAB,0x02,\n0x02,0x2F,0x7D,0x04,0x7C,0x00,0x7F,0x01,\n0x7E,0x66,0x12,0x07,0xAB,0x7D,0x80,0x7C,\n0x00,0x7F,0x00,0x7E,0x66,0x12,0x07,0xAB,\n0x7F,0x02,0x7E,0x66,0x12,0x07,0x66,0xEF,\n0x44,0x02,0x44,0x04,0xFD,0xAC,0x06,0x7F,\n0x02,0x7E,0x66,0x12,0x07,0xAB,0x7D,0x04,\n0x7C,0x00,0x7F,0x01,0x7E,0x66,0x12,0x07,\n0xAB,0x7D,0xC0,0x7C,0x00,0x7F,0x00,0x7E,\n0x66,0x02,0x07,0xAB,0xC0,0xE0,0xC0,0xF0,\n0xC0,0x83,0xC0,0x82,0xC0,0xD0,0x75,0xD0,\n0x00,0xC0,0x00,0x78,0x17,0xE6,0xF5,0x8C,\n0x78,0x18,0xE6,0xF5,0x8A,0x90,0x06,0x31,\n0xE4,0x75,0xF0,0x01,0x12,0x00,0x0E,0x90,\n0x06,0x33,0xE4,0x75,0xF0,0x01,0x12,0x00,\n0x0E,0xD0,0x00,0xD0,0xD0,0xD0,0x82,0xD0,\n0x83,0xD0,0xF0,0xD0,0xE0,0x32,0xC2,0xAF,\n0xAD,0x07,0xAC,0x06,0x8C,0xA2,0x8D,0xA3,\n0x75,0xA0,0x01,0x00,0x00,0x00,0x00,0x00,\n0x00,0x00,0x00,0x00,0x00,0x00,0xAE,0xA1,\n0xBE,0x00,0xF0,0xAE,0xA6,0xAF,0xA7,0xD2,\n0xAF,0x22,0x7D,0x20,0x7C,0x0F,0x7F,0x02,\n0x7E,0x66,0x12,0x07,0xAB,0x7D,0x01,0x7C,\n0x00,0x7F,0x01,0x7E,0x66,0x12,0x07,0xAB,\n0x7D,0xC0,0x7C,0x00,0x7F,0x00,0x7E,0x66,\n0x02,0x07,0xAB,0xC2,0xAF,0xAB,0x07,0xAA,\n0x06,0x8A,0xA2,0x8B,0xA3,0x8C,0xA4,0x8D,\n0xA5,0x75,0xA0,0x03,0x00,0x00,0x00,0xAA,\n0xA1,0xBA,0x00,0xF8,0xD2,0xAF,0x22,0x7F,\n0x0C,0x7E,0x13,0x12,0x07,0x66,0xEF,0x44,\n0x50,0xFD,0xAC,0x06,0x7F,0x0C,0x7E,0x13,\n0x02,0x07,0xAB,0x12,0x07,0xC7,0x12,0x07,\n0xF2,0x12,0x04,0x2B,0x02,0x00,0x03,0x42,\n0x06,0x33,0x00,0x00,0x42,0x06,0x31,0x00,\n0x00,0x00,0xE4,0xF5,0x8E,0x22,};\n\n#define FIBER2_1G_INIT_SIZE 2032\nrtk_uint8 Fiber2_1G[FIBER2_1G_INIT_SIZE] = {\n0x02,0x05,0x89,0xE4,0xF5,0xA8,0xD2,0xAF,\n0x22,0x00,0x00,0x02,0x07,0x26,0xC5,0xF0,\n0xF8,0xA3,0xE0,0x28,0xF0,0xC5,0xF0,0xF8,\n0xE5,0x82,0x15,0x82,0x70,0x02,0x15,0x83,\n0xE0,0x38,0xF0,0x22,0x75,0xF0,0x08,0x75,\n0x82,0x00,0xEF,0x2F,0xFF,0xEE,0x33,0xFE,\n0xCD,0x33,0xCD,0xCC,0x33,0xCC,0xC5,0x82,\n0x33,0xC5,0x82,0x9B,0xED,0x9A,0xEC,0x99,\n0xE5,0x82,0x98,0x40,0x0C,0xF5,0x82,0xEE,\n0x9B,0xFE,0xED,0x9A,0xFD,0xEC,0x99,0xFC,\n0x0F,0xD5,0xF0,0xD6,0xE4,0xCE,0xFB,0xE4,\n0xCD,0xFA,0xE4,0xCC,0xF9,0xA8,0x82,0x22,\n0xB8,0x00,0xC1,0xB9,0x00,0x59,0xBA,0x00,\n0x2D,0xEC,0x8B,0xF0,0x84,0xCF,0xCE,0xCD,\n0xFC,0xE5,0xF0,0xCB,0xF9,0x78,0x18,0xEF,\n0x2F,0xFF,0xEE,0x33,0xFE,0xED,0x33,0xFD,\n0xEC,0x33,0xFC,0xEB,0x33,0xFB,0x10,0xD7,\n0x03,0x99,0x40,0x04,0xEB,0x99,0xFB,0x0F,\n0xD8,0xE5,0xE4,0xF9,0xFA,0x22,0x78,0x18,\n0xEF,0x2F,0xFF,0xEE,0x33,0xFE,0xED,0x33,\n0xFD,0xEC,0x33,0xFC,0xC9,0x33,0xC9,0x10,\n0xD7,0x05,0x9B,0xE9,0x9A,0x40,0x07,0xEC,\n0x9B,0xFC,0xE9,0x9A,0xF9,0x0F,0xD8,0xE0,\n0xE4,0xC9,0xFA,0xE4,0xCC,0xFB,0x22,0x75,\n0xF0,0x10,0xEF,0x2F,0xFF,0xEE,0x33,0xFE,\n0xED,0x33,0xFD,0xCC,0x33,0xCC,0xC8,0x33,\n0xC8,0x10,0xD7,0x07,0x9B,0xEC,0x9A,0xE8,\n0x99,0x40,0x0A,0xED,0x9B,0xFD,0xEC,0x9A,\n0xFC,0xE8,0x99,0xF8,0x0F,0xD5,0xF0,0xDA,\n0xE4,0xCD,0xFB,0xE4,0xCC,0xFA,0xE4,0xC8,\n0xF9,0x22,0xEB,0x9F,0xF5,0xF0,0xEA,0x9E,\n0x42,0xF0,0xE9,0x9D,0x42,0xF0,0xE8,0x9C,\n0x45,0xF0,0x22,0xE0,0xFC,0xA3,0xE0,0xFD,\n0xA3,0xE0,0xFE,0xA3,0xE0,0xFF,0x22,0xE0,\n0xF8,0xA3,0xE0,0xF9,0xA3,0xE0,0xFA,0xA3,\n0xE0,0xFB,0x22,0xEC,0xF0,0xA3,0xED,0xF0,\n0xA3,0xEE,0xF0,0xA3,0xEF,0xF0,0x22,0x7D,\n0xD7,0x7C,0x04,0x7F,0x02,0x7E,0x66,0x12,\n0x07,0xA5,0x7D,0x80,0x7C,0x04,0x7F,0x01,\n0x7E,0x66,0x12,0x07,0xA5,0x7D,0xC0,0x7C,\n0x00,0x7F,0x00,0x7E,0x66,0x12,0x07,0xA5,\n0x7D,0x94,0x7C,0xF9,0x7F,0x02,0x7E,0x66,\n0x12,0x07,0xA5,0x7D,0x81,0x7C,0x04,0x7F,\n0x01,0x7E,0x66,0x12,0x07,0xA5,0x7D,0xC0,\n0x7C,0x00,0x7F,0x00,0x7E,0x66,0x12,0x07,\n0xA5,0x7D,0xA2,0x7C,0x31,0x7F,0x02,0x7E,\n0x66,0x12,0x07,0xA5,0x7D,0x82,0x7C,0x04,\n0x7F,0x01,0x7E,0x66,0x12,0x07,0xA5,0x7D,\n0xC0,0x7C,0x00,0x7F,0x00,0x7E,0x66,0x12,\n0x07,0xA5,0x7D,0x60,0x7C,0x69,0x7F,0x02,\n0x7E,0x66,0x12,0x07,0xA5,0x7D,0x83,0x7C,\n0x04,0x7F,0x01,0x7E,0x66,0x12,0x07,0xA5,\n0x7D,0xC0,0x7C,0x00,0x7F,0x00,0x7E,0x66,\n0x12,0x07,0xA5,0x7D,0x28,0x7C,0x97,0x7F,\n0x02,0x7E,0x66,0x12,0x07,0xA5,0x7D,0x84,\n0x7C,0x04,0x7F,0x01,0x7E,0x66,0x12,0x07,\n0xA5,0x7D,0xC0,0x7C,0x00,0x7F,0x00,0x7E,\n0x66,0x12,0x07,0xA5,0x7D,0x85,0x7C,0x9D,\n0x7F,0x02,0x7E,0x66,0x12,0x07,0xA5,0x7D,\n0x23,0x7C,0x04,0x7F,0x01,0x7E,0x66,0x12,\n0x07,0xA5,0x7D,0xC0,0x7C,0x00,0x7F,0x00,\n0x7E,0x66,0x12,0x07,0xA5,0x7D,0x10,0x7C,\n0xD8,0x7F,0x02,0x7E,0x66,0x12,0x07,0xA5,\n0x7D,0x24,0x7C,0x04,0x7F,0x01,0x7E,0x66,\n0x12,0x07,0xA5,0x7D,0xC0,0x7C,0x00,0x7F,\n0x00,0x7E,0x66,0x12,0x07,0xA5,0x7D,0x00,\n0x7C,0x04,0x7F,0x02,0x7E,0x66,0x12,0x07,\n0xA5,0x7D,0x2F,0x7C,0x00,0x7F,0x01,0x7E,\n0x66,0x12,0x07,0xA5,0x7D,0xC0,0x7C,0x00,\n0x7F,0x00,0x7E,0x66,0x02,0x07,0xA5,0x7D,\n0x03,0x7C,0x00,0x7F,0x01,0x7E,0x66,0x12,\n0x07,0xA5,0x7D,0x80,0x7C,0x00,0x7F,0x00,\n0x7E,0x66,0x12,0x07,0xA5,0x7F,0x02,0x7E,\n0x66,0x12,0x07,0x60,0xEF,0x44,0x40,0xFD,\n0xAC,0x06,0x7F,0x02,0x7E,0x66,0x12,0x07,\n0xA5,0x7D,0x03,0x7C,0x00,0x7F,0x01,0x7E,\n0x66,0x12,0x07,0xA5,0x7D,0xC0,0x7C,0x00,\n0x7F,0x00,0x7E,0x66,0x12,0x07,0xA5,0x7D,\n0x03,0x7C,0x00,0x7F,0x01,0x7E,0x66,0x12,\n0x07,0xA5,0x7D,0x80,0x7C,0x00,0x7F,0x00,\n0x7E,0x66,0x12,0x07,0xA5,0x7F,0x02,0x7E,\n0x66,0x12,0x07,0x60,0xEF,0x54,0xBF,0xFD,\n0xAC,0x06,0x7F,0x02,0x7E,0x66,0x12,0x07,\n0xA5,0x7D,0x03,0x7C,0x00,0x7F,0x01,0x7E,\n0x66,0x12,0x07,0xA5,0x7D,0xC0,0x7C,0x00,\n0x7F,0x00,0x7E,0x66,0x12,0x07,0xA5,0xE4,\n0xFD,0xFC,0x7F,0x01,0x7E,0x66,0x12,0x07,\n0xA5,0x7D,0x80,0x7C,0x00,0x7F,0x00,0x7E,\n0x66,0x12,0x07,0xA5,0x7F,0x02,0x7E,0x66,\n0x12,0x07,0x60,0xEF,0x54,0xFD,0x54,0xFE,\n0xFD,0xAC,0x06,0x7F,0x02,0x7E,0x66,0x12,\n0x07,0xA5,0xE4,0xFD,0xFC,0x7F,0x01,0x7E,\n0x66,0x12,0x07,0xA5,0x7D,0xC0,0x7C,0x00,\n0x7F,0x00,0x7E,0x66,0x12,0x07,0xA5,0xE4,\n0xFD,0xFC,0x7F,0x01,0x7E,0x66,0x12,0x07,\n0xA5,0x7D,0x80,0x7C,0x00,0x7F,0x00,0x7E,\n0x66,0x12,0x07,0xA5,0x7F,0x02,0x7E,0x66,\n0x12,0x07,0x60,0xEF,0x44,0x02,0x44,0x01,\n0xFD,0xAC,0x06,0x7F,0x02,0x7E,0x66,0x12,\n0x07,0xA5,0xE4,0xFD,0xFC,0x7F,0x01,0x7E,\n0x66,0x12,0x07,0xA5,0x7D,0xC0,0x7C,0x00,\n0x7F,0x00,0x7E,0x66,0x02,0x07,0xA5,0xE4,\n0x90,0x06,0x2C,0xF0,0xFD,0x7C,0x01,0x7F,\n0x3F,0x7E,0x1D,0x12,0x07,0xA5,0x7D,0x40,\n0x7C,0x00,0x7F,0x36,0x7E,0x13,0x12,0x07,\n0xA5,0xE4,0xFF,0xFE,0xFD,0x80,0x25,0xE4,\n0x7F,0xFF,0x7E,0xFF,0xFD,0xFC,0x90,0x06,\n0x24,0x12,0x01,0x0F,0xC3,0x12,0x00,0xF2,\n0x50,0x1B,0x90,0x06,0x24,0x12,0x01,0x03,\n0xEF,0x24,0x01,0xFF,0xE4,0x3E,0xFE,0xE4,\n0x3D,0xFD,0xE4,0x3C,0xFC,0x90,0x06,0x24,\n0x12,0x01,0x1B,0x80,0xD2,0xE4,0xF5,0xA8,\n0xD2,0xAF,0x7D,0x1F,0xFC,0x7F,0x49,0x7E,\n0x13,0x12,0x07,0xA5,0x12,0x07,0xD5,0x12,\n0x01,0x27,0x12,0x06,0x9F,0x7D,0x41,0x7C,\n0x00,0x7F,0x36,0x7E,0x13,0x12,0x07,0xA5,\n0xE4,0xFF,0xFE,0xFD,0x80,0x26,0x7F,0xFF,\n0x7E,0xFF,0x7D,0x05,0x7C,0x00,0x90,0x06,\n0x24,0x12,0x01,0x0F,0xC3,0x12,0x00,0xF2,\n0x50,0x1B,0x90,0x06,0x24,0x12,0x01,0x03,\n0xEF,0x24,0x01,0xFF,0xE4,0x3E,0xFE,0xE4,\n0x3D,0xFD,0xE4,0x3C,0xFC,0x90,0x06,0x24,\n0x12,0x01,0x1B,0x80,0xD1,0xC2,0x00,0xC2,\n0x01,0xD2,0xA9,0xD2,0x8C,0x7F,0x01,0x7E,\n0x62,0x12,0x07,0x60,0xEF,0x30,0xE2,0x07,\n0xE4,0x90,0x06,0x2C,0xF0,0x80,0xEE,0x90,\n0x06,0x2C,0xE0,0x70,0x12,0x12,0x04,0xEA,\n0x90,0x06,0x2C,0x74,0x01,0xF0,0xE4,0x90,\n0x06,0x33,0xF0,0xA3,0xF0,0x80,0xD6,0xC3,\n0x90,0x06,0x34,0xE0,0x94,0x62,0x90,0x06,\n0x33,0xE0,0x94,0x00,0x40,0xC7,0xE4,0xF0,\n0xA3,0xF0,0x12,0x04,0xEA,0x90,0x06,0x2C,\n0x74,0x01,0xF0,0x80,0xB8,0x75,0x0F,0x80,\n0x75,0x0E,0x7E,0x75,0x0D,0xAA,0x75,0x0C,\n0x83,0xE4,0xF5,0x10,0x7F,0x36,0x7E,0x13,\n0x12,0x07,0x60,0xEE,0xC4,0xF8,0x54,0xF0,\n0xC8,0xEF,0xC4,0x54,0x0F,0x48,0x54,0x07,\n0xFB,0x7A,0x00,0xEA,0x70,0x4A,0xEB,0x14,\n0x60,0x1C,0x14,0x60,0x27,0x24,0xFE,0x60,\n0x31,0x14,0x60,0x3C,0x24,0x05,0x70,0x38,\n0x75,0x0B,0x00,0x75,0x0A,0xC2,0x75,0x09,\n0xEB,0x75,0x08,0x0B,0x80,0x36,0x75,0x0B,\n0x40,0x75,0x0A,0x59,0x75,0x09,0x73,0x75,\n0x08,0x07,0x80,0x28,0x75,0x0B,0x00,0x75,\n0x0A,0xE1,0x75,0x09,0xF5,0x75,0x08,0x05,\n0x80,0x1A,0x75,0x0B,0xA0,0x75,0x0A,0xAC,\n0x75,0x09,0xB9,0x75,0x08,0x03,0x80,0x0C,\n0x75,0x0B,0x00,0x75,0x0A,0x62,0x75,0x09,\n0x3D,0x75,0x08,0x01,0x75,0x89,0x11,0xE4,\n0x7B,0x60,0x7A,0x09,0xF9,0xF8,0xAF,0x0B,\n0xAE,0x0A,0xAD,0x09,0xAC,0x08,0x12,0x00,\n0x60,0xAA,0x06,0xAB,0x07,0xC3,0xE4,0x9B,\n0xFB,0xE4,0x9A,0xFA,0x78,0x17,0xF6,0xAF,\n0x03,0xEF,0x08,0xF6,0x18,0xE6,0xF5,0x8C,\n0x08,0xE6,0xF5,0x8A,0x74,0x0D,0x2B,0xFB,\n0xE4,0x3A,0x18,0xF6,0xAF,0x03,0xEF,0x08,\n0xF6,0x75,0x88,0x10,0x53,0x8E,0xC7,0xD2,\n0xA9,0x22,0x7F,0x10,0x7E,0x13,0x12,0x07,\n0x60,0x90,0x06,0x2D,0xEE,0xF0,0xA3,0xEF,\n0xF0,0xEE,0x44,0x10,0xFE,0x90,0x06,0x2D,\n0xF0,0xA3,0xEF,0xF0,0x54,0xEF,0xFF,0x90,\n0x06,0x2D,0xEE,0xF0,0xFC,0xA3,0xEF,0xF0,\n0xFD,0x7F,0x10,0x7E,0x13,0x12,0x07,0xA5,\n0xE4,0xFF,0xFE,0x0F,0xBF,0x00,0x01,0x0E,\n0xEF,0x64,0x64,0x4E,0x70,0xF5,0x7D,0x04,\n0x7C,0x00,0x7F,0x02,0x7E,0x66,0x12,0x07,\n0xA5,0x7D,0x00,0x7C,0x04,0x7F,0x01,0x7E,\n0x66,0x12,0x07,0xA5,0x7D,0xC0,0x7C,0x00,\n0x7F,0x00,0x7E,0x66,0x12,0x07,0xA5,0xE4,\n0xFD,0xFC,0x7F,0x02,0x7E,0x66,0x12,0x07,\n0xA5,0x7D,0x00,0x7C,0x04,0x7F,0x01,0x7E,\n0x66,0x12,0x07,0xA5,0x7D,0xC0,0x7C,0x00,\n0x7F,0x00,0x7E,0x66,0x12,0x07,0xA5,0x7F,\n0x10,0x7E,0x13,0x12,0x07,0x60,0x90,0x06,\n0x2D,0xEE,0xF0,0xA3,0xEF,0xF0,0xEE,0x54,\n0xEF,0x90,0x06,0x2D,0xF0,0xFC,0xA3,0xEF,\n0xF0,0xFD,0x7F,0x10,0x7E,0x13,0x02,0x07,\n0xA5,0x78,0x7F,0xE4,0xF6,0xD8,0xFD,0x75,\n0x81,0x3C,0x02,0x05,0xD0,0x02,0x03,0x2F,\n0xE4,0x93,0xA3,0xF8,0xE4,0x93,0xA3,0x40,\n0x03,0xF6,0x80,0x01,0xF2,0x08,0xDF,0xF4,\n0x80,0x29,0xE4,0x93,0xA3,0xF8,0x54,0x07,\n0x24,0x0C,0xC8,0xC3,0x33,0xC4,0x54,0x0F,\n0x44,0x20,0xC8,0x83,0x40,0x04,0xF4,0x56,\n0x80,0x01,0x46,0xF6,0xDF,0xE4,0x80,0x0B,\n0x01,0x02,0x04,0x08,0x10,0x20,0x40,0x80,\n0x90,0x07,0xE1,0xE4,0x7E,0x01,0x93,0x60,\n0xBC,0xA3,0xFF,0x54,0x3F,0x30,0xE5,0x09,\n0x54,0x1F,0xFE,0xE4,0x93,0xA3,0x60,0x01,\n0x0E,0xCF,0x54,0xC0,0x25,0xE0,0x60,0xA8,\n0x40,0xB8,0xE4,0x93,0xA3,0xFA,0xE4,0x93,\n0xA3,0xF8,0xE4,0x93,0xA3,0xC8,0xC5,0x82,\n0xC8,0xCA,0xC5,0x83,0xCA,0xF0,0xA3,0xC8,\n0xC5,0x82,0xC8,0xCA,0xC5,0x83,0xCA,0xDF,\n0xE9,0xDE,0xE7,0x80,0xBE,0x7D,0x40,0x7C,\n0x17,0x7F,0x11,0x7E,0x1D,0x12,0x07,0xA5,\n0x7F,0x41,0x7E,0x1D,0x12,0x07,0x60,0xEF,\n0x44,0x20,0x44,0x80,0xFD,0xAC,0x06,0x7F,\n0x41,0x7E,0x1D,0x12,0x07,0xA5,0x7D,0xBB,\n0x7C,0x15,0x7F,0xEB,0x7E,0x13,0x12,0x07,\n0xA5,0x7D,0x07,0x7C,0x00,0x7F,0xE7,0x7E,\n0x13,0x12,0x07,0xA5,0x7D,0x40,0x7C,0x11,\n0x7F,0x00,0x7E,0x62,0x12,0x07,0xA5,0x02,\n0x02,0x2F,0x7D,0xC0,0x7C,0x16,0x7F,0x11,\n0x7E,0x1D,0x12,0x07,0xA5,0x7D,0xBB,0x7C,\n0x15,0x7F,0xEB,0x7E,0x13,0x12,0x07,0xA5,\n0x7D,0x0D,0x7C,0x00,0x7F,0xE7,0x7E,0x13,\n0x12,0x07,0xA5,0x7F,0x41,0x7E,0x1D,0x12,\n0x07,0x60,0xEF,0x44,0x20,0x44,0x80,0xFD,\n0xAC,0x06,0x7F,0x41,0x7E,0x1D,0x12,0x07,\n0xA5,0x7D,0x00,0x7C,0x21,0x7F,0x00,0x7E,\n0x62,0x12,0x07,0xA5,0x02,0x02,0x2F,0x7D,\n0x40,0x7C,0x17,0x7F,0x11,0x7E,0x1D,0x12,\n0x07,0xA5,0x7D,0xBB,0x7C,0x15,0x7F,0xEB,\n0x7E,0x13,0x12,0x07,0xA5,0x7D,0x0C,0x7C,\n0x00,0x7F,0xE7,0x7E,0x13,0x12,0x07,0xA5,\n0x7F,0x41,0x7E,0x1D,0x12,0x07,0x60,0xEF,\n0x44,0x20,0x44,0x80,0xFD,0xAC,0x06,0x7F,\n0x41,0x7E,0x1D,0x12,0x07,0xA5,0x7D,0x40,\n0x7C,0x11,0x7F,0x00,0x7E,0x62,0x12,0x07,\n0xA5,0x02,0x02,0x2F,0x7D,0x04,0x7C,0x00,\n0x7F,0x01,0x7E,0x66,0x12,0x07,0xA5,0x7D,\n0x80,0x7C,0x00,0x7F,0x00,0x7E,0x66,0x12,\n0x07,0xA5,0x7F,0x02,0x7E,0x66,0x12,0x07,\n0x60,0xEF,0x44,0x02,0x44,0x04,0xFD,0xAC,\n0x06,0x7F,0x02,0x7E,0x66,0x12,0x07,0xA5,\n0x7D,0x04,0x7C,0x00,0x7F,0x01,0x7E,0x66,\n0x12,0x07,0xA5,0x7D,0xC0,0x7C,0x00,0x7F,\n0x00,0x7E,0x66,0x02,0x07,0xA5,0xC0,0xE0,\n0xC0,0xF0,0xC0,0x83,0xC0,0x82,0xC0,0xD0,\n0x75,0xD0,0x00,0xC0,0x00,0x78,0x17,0xE6,\n0xF5,0x8C,0x78,0x18,0xE6,0xF5,0x8A,0x90,\n0x06,0x31,0xE4,0x75,0xF0,0x01,0x12,0x00,\n0x0E,0x90,0x06,0x33,0xE4,0x75,0xF0,0x01,\n0x12,0x00,0x0E,0xD0,0x00,0xD0,0xD0,0xD0,\n0x82,0xD0,0x83,0xD0,0xF0,0xD0,0xE0,0x32,\n0xC2,0xAF,0xAD,0x07,0xAC,0x06,0x8C,0xA2,\n0x8D,0xA3,0x75,0xA0,0x01,0x00,0x00,0x00,\n0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,\n0xAE,0xA1,0xBE,0x00,0xF0,0xAE,0xA6,0xAF,\n0xA7,0xD2,0xAF,0x22,0x7D,0x20,0x7C,0x0F,\n0x7F,0x02,0x7E,0x66,0x12,0x07,0xA5,0x7D,\n0x01,0x7C,0x00,0x7F,0x01,0x7E,0x66,0x12,\n0x07,0xA5,0x7D,0xC0,0x7C,0x00,0x7F,0x00,\n0x7E,0x66,0x02,0x07,0xA5,0xC2,0xAF,0xAB,\n0x07,0xAA,0x06,0x8A,0xA2,0x8B,0xA3,0x8C,\n0xA4,0x8D,0xA5,0x75,0xA0,0x03,0x00,0x00,\n0x00,0xAA,0xA1,0xBA,0x00,0xF8,0xD2,0xAF,\n0x22,0x7F,0x0C,0x7E,0x13,0x12,0x07,0x60,\n0xEF,0x44,0x50,0xFD,0xAC,0x06,0x7F,0x0C,\n0x7E,0x13,0x02,0x07,0xA5,0x12,0x07,0xC1,\n0x12,0x07,0xEC,0x12,0x04,0x25,0x02,0x00,\n0x03,0x42,0x06,0x33,0x00,0x00,0x42,0x06,\n0x31,0x00,0x00,0x00,0xE4,0xF5,0x8E,0x22,};\n\n#define FIBER2_100M_INIT_SIZE 2032\nrtk_uint8 Fiber2_100M[FIBER2_100M_INIT_SIZE] = {\n0x02,0x05,0x89,0xE4,0xF5,0xA8,0xD2,0xAF,\n0x22,0x00,0x00,0x02,0x07,0x26,0xC5,0xF0,\n0xF8,0xA3,0xE0,0x28,0xF0,0xC5,0xF0,0xF8,\n0xE5,0x82,0x15,0x82,0x70,0x02,0x15,0x83,\n0xE0,0x38,0xF0,0x22,0x75,0xF0,0x08,0x75,\n0x82,0x00,0xEF,0x2F,0xFF,0xEE,0x33,0xFE,\n0xCD,0x33,0xCD,0xCC,0x33,0xCC,0xC5,0x82,\n0x33,0xC5,0x82,0x9B,0xED,0x9A,0xEC,0x99,\n0xE5,0x82,0x98,0x40,0x0C,0xF5,0x82,0xEE,\n0x9B,0xFE,0xED,0x9A,0xFD,0xEC,0x99,0xFC,\n0x0F,0xD5,0xF0,0xD6,0xE4,0xCE,0xFB,0xE4,\n0xCD,0xFA,0xE4,0xCC,0xF9,0xA8,0x82,0x22,\n0xB8,0x00,0xC1,0xB9,0x00,0x59,0xBA,0x00,\n0x2D,0xEC,0x8B,0xF0,0x84,0xCF,0xCE,0xCD,\n0xFC,0xE5,0xF0,0xCB,0xF9,0x78,0x18,0xEF,\n0x2F,0xFF,0xEE,0x33,0xFE,0xED,0x33,0xFD,\n0xEC,0x33,0xFC,0xEB,0x33,0xFB,0x10,0xD7,\n0x03,0x99,0x40,0x04,0xEB,0x99,0xFB,0x0F,\n0xD8,0xE5,0xE4,0xF9,0xFA,0x22,0x78,0x18,\n0xEF,0x2F,0xFF,0xEE,0x33,0xFE,0xED,0x33,\n0xFD,0xEC,0x33,0xFC,0xC9,0x33,0xC9,0x10,\n0xD7,0x05,0x9B,0xE9,0x9A,0x40,0x07,0xEC,\n0x9B,0xFC,0xE9,0x9A,0xF9,0x0F,0xD8,0xE0,\n0xE4,0xC9,0xFA,0xE4,0xCC,0xFB,0x22,0x75,\n0xF0,0x10,0xEF,0x2F,0xFF,0xEE,0x33,0xFE,\n0xED,0x33,0xFD,0xCC,0x33,0xCC,0xC8,0x33,\n0xC8,0x10,0xD7,0x07,0x9B,0xEC,0x9A,0xE8,\n0x99,0x40,0x0A,0xED,0x9B,0xFD,0xEC,0x9A,\n0xFC,0xE8,0x99,0xF8,0x0F,0xD5,0xF0,0xDA,\n0xE4,0xCD,0xFB,0xE4,0xCC,0xFA,0xE4,0xC8,\n0xF9,0x22,0xEB,0x9F,0xF5,0xF0,0xEA,0x9E,\n0x42,0xF0,0xE9,0x9D,0x42,0xF0,0xE8,0x9C,\n0x45,0xF0,0x22,0xE0,0xFC,0xA3,0xE0,0xFD,\n0xA3,0xE0,0xFE,0xA3,0xE0,0xFF,0x22,0xE0,\n0xF8,0xA3,0xE0,0xF9,0xA3,0xE0,0xFA,0xA3,\n0xE0,0xFB,0x22,0xEC,0xF0,0xA3,0xED,0xF0,\n0xA3,0xEE,0xF0,0xA3,0xEF,0xF0,0x22,0x7D,\n0xD7,0x7C,0x04,0x7F,0x02,0x7E,0x66,0x12,\n0x07,0xA5,0x7D,0x80,0x7C,0x04,0x7F,0x01,\n0x7E,0x66,0x12,0x07,0xA5,0x7D,0xC0,0x7C,\n0x00,0x7F,0x00,0x7E,0x66,0x12,0x07,0xA5,\n0x7D,0x94,0x7C,0xF9,0x7F,0x02,0x7E,0x66,\n0x12,0x07,0xA5,0x7D,0x81,0x7C,0x04,0x7F,\n0x01,0x7E,0x66,0x12,0x07,0xA5,0x7D,0xC0,\n0x7C,0x00,0x7F,0x00,0x7E,0x66,0x12,0x07,\n0xA5,0x7D,0xA2,0x7C,0x31,0x7F,0x02,0x7E,\n0x66,0x12,0x07,0xA5,0x7D,0x82,0x7C,0x04,\n0x7F,0x01,0x7E,0x66,0x12,0x07,0xA5,0x7D,\n0xC0,0x7C,0x00,0x7F,0x00,0x7E,0x66,0x12,\n0x07,0xA5,0x7D,0x60,0x7C,0x69,0x7F,0x02,\n0x7E,0x66,0x12,0x07,0xA5,0x7D,0x83,0x7C,\n0x04,0x7F,0x01,0x7E,0x66,0x12,0x07,0xA5,\n0x7D,0xC0,0x7C,0x00,0x7F,0x00,0x7E,0x66,\n0x12,0x07,0xA5,0x7D,0x28,0x7C,0x97,0x7F,\n0x02,0x7E,0x66,0x12,0x07,0xA5,0x7D,0x84,\n0x7C,0x04,0x7F,0x01,0x7E,0x66,0x12,0x07,\n0xA5,0x7D,0xC0,0x7C,0x00,0x7F,0x00,0x7E,\n0x66,0x12,0x07,0xA5,0x7D,0x85,0x7C,0x9D,\n0x7F,0x02,0x7E,0x66,0x12,0x07,0xA5,0x7D,\n0x23,0x7C,0x04,0x7F,0x01,0x7E,0x66,0x12,\n0x07,0xA5,0x7D,0xC0,0x7C,0x00,0x7F,0x00,\n0x7E,0x66,0x12,0x07,0xA5,0x7D,0x10,0x7C,\n0xD8,0x7F,0x02,0x7E,0x66,0x12,0x07,0xA5,\n0x7D,0x24,0x7C,0x04,0x7F,0x01,0x7E,0x66,\n0x12,0x07,0xA5,0x7D,0xC0,0x7C,0x00,0x7F,\n0x00,0x7E,0x66,0x12,0x07,0xA5,0x7D,0x00,\n0x7C,0x04,0x7F,0x02,0x7E,0x66,0x12,0x07,\n0xA5,0x7D,0x2F,0x7C,0x00,0x7F,0x01,0x7E,\n0x66,0x12,0x07,0xA5,0x7D,0xC0,0x7C,0x00,\n0x7F,0x00,0x7E,0x66,0x02,0x07,0xA5,0x7D,\n0x03,0x7C,0x00,0x7F,0x01,0x7E,0x66,0x12,\n0x07,0xA5,0x7D,0x80,0x7C,0x00,0x7F,0x00,\n0x7E,0x66,0x12,0x07,0xA5,0x7F,0x02,0x7E,\n0x66,0x12,0x07,0x60,0xEF,0x44,0x40,0xFD,\n0xAC,0x06,0x7F,0x02,0x7E,0x66,0x12,0x07,\n0xA5,0x7D,0x03,0x7C,0x00,0x7F,0x01,0x7E,\n0x66,0x12,0x07,0xA5,0x7D,0xC0,0x7C,0x00,\n0x7F,0x00,0x7E,0x66,0x12,0x07,0xA5,0x7D,\n0x03,0x7C,0x00,0x7F,0x01,0x7E,0x66,0x12,\n0x07,0xA5,0x7D,0x80,0x7C,0x00,0x7F,0x00,\n0x7E,0x66,0x12,0x07,0xA5,0x7F,0x02,0x7E,\n0x66,0x12,0x07,0x60,0xEF,0x54,0xBF,0xFD,\n0xAC,0x06,0x7F,0x02,0x7E,0x66,0x12,0x07,\n0xA5,0x7D,0x03,0x7C,0x00,0x7F,0x01,0x7E,\n0x66,0x12,0x07,0xA5,0x7D,0xC0,0x7C,0x00,\n0x7F,0x00,0x7E,0x66,0x12,0x07,0xA5,0xE4,\n0xFD,0xFC,0x7F,0x01,0x7E,0x66,0x12,0x07,\n0xA5,0x7D,0x80,0x7C,0x00,0x7F,0x00,0x7E,\n0x66,0x12,0x07,0xA5,0x7F,0x02,0x7E,0x66,\n0x12,0x07,0x60,0xEF,0x54,0xFD,0x54,0xFE,\n0xFD,0xAC,0x06,0x7F,0x02,0x7E,0x66,0x12,\n0x07,0xA5,0xE4,0xFD,0xFC,0x7F,0x01,0x7E,\n0x66,0x12,0x07,0xA5,0x7D,0xC0,0x7C,0x00,\n0x7F,0x00,0x7E,0x66,0x12,0x07,0xA5,0xE4,\n0xFD,0xFC,0x7F,0x01,0x7E,0x66,0x12,0x07,\n0xA5,0x7D,0x80,0x7C,0x00,0x7F,0x00,0x7E,\n0x66,0x12,0x07,0xA5,0x7F,0x02,0x7E,0x66,\n0x12,0x07,0x60,0xEF,0x44,0x02,0x44,0x01,\n0xFD,0xAC,0x06,0x7F,0x02,0x7E,0x66,0x12,\n0x07,0xA5,0xE4,0xFD,0xFC,0x7F,0x01,0x7E,\n0x66,0x12,0x07,0xA5,0x7D,0xC0,0x7C,0x00,\n0x7F,0x00,0x7E,0x66,0x02,0x07,0xA5,0xE4,\n0x90,0x06,0x2C,0xF0,0xFD,0x7C,0x01,0x7F,\n0x3F,0x7E,0x1D,0x12,0x07,0xA5,0x7D,0x40,\n0x7C,0x00,0x7F,0x36,0x7E,0x13,0x12,0x07,\n0xA5,0xE4,0xFF,0xFE,0xFD,0x80,0x25,0xE4,\n0x7F,0xFF,0x7E,0xFF,0xFD,0xFC,0x90,0x06,\n0x24,0x12,0x01,0x0F,0xC3,0x12,0x00,0xF2,\n0x50,0x1B,0x90,0x06,0x24,0x12,0x01,0x03,\n0xEF,0x24,0x01,0xFF,0xE4,0x3E,0xFE,0xE4,\n0x3D,0xFD,0xE4,0x3C,0xFC,0x90,0x06,0x24,\n0x12,0x01,0x1B,0x80,0xD2,0xE4,0xF5,0xA8,\n0xD2,0xAF,0x7D,0x1F,0xFC,0x7F,0x49,0x7E,\n0x13,0x12,0x07,0xA5,0x12,0x07,0xD5,0x12,\n0x01,0x27,0x12,0x06,0x5A,0x7D,0x41,0x7C,\n0x00,0x7F,0x36,0x7E,0x13,0x12,0x07,0xA5,\n0xE4,0xFF,0xFE,0xFD,0x80,0x26,0x7F,0xFF,\n0x7E,0xFF,0x7D,0x05,0x7C,0x00,0x90,0x06,\n0x24,0x12,0x01,0x0F,0xC3,0x12,0x00,0xF2,\n0x50,0x1B,0x90,0x06,0x24,0x12,0x01,0x03,\n0xEF,0x24,0x01,0xFF,0xE4,0x3E,0xFE,0xE4,\n0x3D,0xFD,0xE4,0x3C,0xFC,0x90,0x06,0x24,\n0x12,0x01,0x1B,0x80,0xD1,0xC2,0x00,0xC2,\n0x01,0xD2,0xA9,0xD2,0x8C,0x7F,0x01,0x7E,\n0x62,0x12,0x07,0x60,0xEF,0x30,0xE2,0x07,\n0xE4,0x90,0x06,0x2C,0xF0,0x80,0xEE,0x90,\n0x06,0x2C,0xE0,0x70,0x12,0x12,0x04,0xEA,\n0x90,0x06,0x2C,0x74,0x01,0xF0,0xE4,0x90,\n0x06,0x33,0xF0,0xA3,0xF0,0x80,0xD6,0xC3,\n0x90,0x06,0x34,0xE0,0x94,0x62,0x90,0x06,\n0x33,0xE0,0x94,0x00,0x40,0xC7,0xE4,0xF0,\n0xA3,0xF0,0x12,0x04,0xEA,0x90,0x06,0x2C,\n0x74,0x01,0xF0,0x80,0xB8,0x75,0x0F,0x80,\n0x75,0x0E,0x7E,0x75,0x0D,0xAA,0x75,0x0C,\n0x83,0xE4,0xF5,0x10,0x7F,0x36,0x7E,0x13,\n0x12,0x07,0x60,0xEE,0xC4,0xF8,0x54,0xF0,\n0xC8,0xEF,0xC4,0x54,0x0F,0x48,0x54,0x07,\n0xFB,0x7A,0x00,0xEA,0x70,0x4A,0xEB,0x14,\n0x60,0x1C,0x14,0x60,0x27,0x24,0xFE,0x60,\n0x31,0x14,0x60,0x3C,0x24,0x05,0x70,0x38,\n0x75,0x0B,0x00,0x75,0x0A,0xC2,0x75,0x09,\n0xEB,0x75,0x08,0x0B,0x80,0x36,0x75,0x0B,\n0x40,0x75,0x0A,0x59,0x75,0x09,0x73,0x75,\n0x08,0x07,0x80,0x28,0x75,0x0B,0x00,0x75,\n0x0A,0xE1,0x75,0x09,0xF5,0x75,0x08,0x05,\n0x80,0x1A,0x75,0x0B,0xA0,0x75,0x0A,0xAC,\n0x75,0x09,0xB9,0x75,0x08,0x03,0x80,0x0C,\n0x75,0x0B,0x00,0x75,0x0A,0x62,0x75,0x09,\n0x3D,0x75,0x08,0x01,0x75,0x89,0x11,0xE4,\n0x7B,0x60,0x7A,0x09,0xF9,0xF8,0xAF,0x0B,\n0xAE,0x0A,0xAD,0x09,0xAC,0x08,0x12,0x00,\n0x60,0xAA,0x06,0xAB,0x07,0xC3,0xE4,0x9B,\n0xFB,0xE4,0x9A,0xFA,0x78,0x17,0xF6,0xAF,\n0x03,0xEF,0x08,0xF6,0x18,0xE6,0xF5,0x8C,\n0x08,0xE6,0xF5,0x8A,0x74,0x0D,0x2B,0xFB,\n0xE4,0x3A,0x18,0xF6,0xAF,0x03,0xEF,0x08,\n0xF6,0x75,0x88,0x10,0x53,0x8E,0xC7,0xD2,\n0xA9,0x22,0x7F,0x10,0x7E,0x13,0x12,0x07,\n0x60,0x90,0x06,0x2D,0xEE,0xF0,0xA3,0xEF,\n0xF0,0xEE,0x44,0x10,0xFE,0x90,0x06,0x2D,\n0xF0,0xA3,0xEF,0xF0,0x54,0xEF,0xFF,0x90,\n0x06,0x2D,0xEE,0xF0,0xFC,0xA3,0xEF,0xF0,\n0xFD,0x7F,0x10,0x7E,0x13,0x12,0x07,0xA5,\n0xE4,0xFF,0xFE,0x0F,0xBF,0x00,0x01,0x0E,\n0xEF,0x64,0x64,0x4E,0x70,0xF5,0x7D,0x04,\n0x7C,0x00,0x7F,0x02,0x7E,0x66,0x12,0x07,\n0xA5,0x7D,0x00,0x7C,0x04,0x7F,0x01,0x7E,\n0x66,0x12,0x07,0xA5,0x7D,0xC0,0x7C,0x00,\n0x7F,0x00,0x7E,0x66,0x12,0x07,0xA5,0xE4,\n0xFD,0xFC,0x7F,0x02,0x7E,0x66,0x12,0x07,\n0xA5,0x7D,0x00,0x7C,0x04,0x7F,0x01,0x7E,\n0x66,0x12,0x07,0xA5,0x7D,0xC0,0x7C,0x00,\n0x7F,0x00,0x7E,0x66,0x12,0x07,0xA5,0x7F,\n0x10,0x7E,0x13,0x12,0x07,0x60,0x90,0x06,\n0x2D,0xEE,0xF0,0xA3,0xEF,0xF0,0xEE,0x54,\n0xEF,0x90,0x06,0x2D,0xF0,0xFC,0xA3,0xEF,\n0xF0,0xFD,0x7F,0x10,0x7E,0x13,0x02,0x07,\n0xA5,0x78,0x7F,0xE4,0xF6,0xD8,0xFD,0x75,\n0x81,0x3C,0x02,0x05,0xD0,0x02,0x03,0x2F,\n0xE4,0x93,0xA3,0xF8,0xE4,0x93,0xA3,0x40,\n0x03,0xF6,0x80,0x01,0xF2,0x08,0xDF,0xF4,\n0x80,0x29,0xE4,0x93,0xA3,0xF8,0x54,0x07,\n0x24,0x0C,0xC8,0xC3,0x33,0xC4,0x54,0x0F,\n0x44,0x20,0xC8,0x83,0x40,0x04,0xF4,0x56,\n0x80,0x01,0x46,0xF6,0xDF,0xE4,0x80,0x0B,\n0x01,0x02,0x04,0x08,0x10,0x20,0x40,0x80,\n0x90,0x07,0xE1,0xE4,0x7E,0x01,0x93,0x60,\n0xBC,0xA3,0xFF,0x54,0x3F,0x30,0xE5,0x09,\n0x54,0x1F,0xFE,0xE4,0x93,0xA3,0x60,0x01,\n0x0E,0xCF,0x54,0xC0,0x25,0xE0,0x60,0xA8,\n0x40,0xB8,0xE4,0x93,0xA3,0xFA,0xE4,0x93,\n0xA3,0xF8,0xE4,0x93,0xA3,0xC8,0xC5,0x82,\n0xC8,0xCA,0xC5,0x83,0xCA,0xF0,0xA3,0xC8,\n0xC5,0x82,0xC8,0xCA,0xC5,0x83,0xCA,0xDF,\n0xE9,0xDE,0xE7,0x80,0xBE,0x7D,0x40,0x7C,\n0x17,0x7F,0x11,0x7E,0x1D,0x12,0x07,0xA5,\n0x7F,0x41,0x7E,0x1D,0x12,0x07,0x60,0xEF,\n0x44,0x20,0x44,0x80,0xFD,0xAC,0x06,0x7F,\n0x41,0x7E,0x1D,0x12,0x07,0xA5,0x7D,0xBB,\n0x7C,0x15,0x7F,0xEB,0x7E,0x13,0x12,0x07,\n0xA5,0x7D,0x07,0x7C,0x00,0x7F,0xE7,0x7E,\n0x13,0x12,0x07,0xA5,0x7D,0x40,0x7C,0x11,\n0x7F,0x00,0x7E,0x62,0x12,0x07,0xA5,0x02,\n0x02,0x2F,0x7D,0xC0,0x7C,0x16,0x7F,0x11,\n0x7E,0x1D,0x12,0x07,0xA5,0x7D,0xBB,0x7C,\n0x15,0x7F,0xEB,0x7E,0x13,0x12,0x07,0xA5,\n0x7D,0x0D,0x7C,0x00,0x7F,0xE7,0x7E,0x13,\n0x12,0x07,0xA5,0x7F,0x41,0x7E,0x1D,0x12,\n0x07,0x60,0xEF,0x44,0x20,0x44,0x80,0xFD,\n0xAC,0x06,0x7F,0x41,0x7E,0x1D,0x12,0x07,\n0xA5,0x7D,0x00,0x7C,0x21,0x7F,0x00,0x7E,\n0x62,0x12,0x07,0xA5,0x02,0x02,0x2F,0x7D,\n0x40,0x7C,0x17,0x7F,0x11,0x7E,0x1D,0x12,\n0x07,0xA5,0x7D,0xBB,0x7C,0x15,0x7F,0xEB,\n0x7E,0x13,0x12,0x07,0xA5,0x7D,0x0C,0x7C,\n0x00,0x7F,0xE7,0x7E,0x13,0x12,0x07,0xA5,\n0x7F,0x41,0x7E,0x1D,0x12,0x07,0x60,0xEF,\n0x44,0x20,0x44,0x80,0xFD,0xAC,0x06,0x7F,\n0x41,0x7E,0x1D,0x12,0x07,0xA5,0x7D,0x40,\n0x7C,0x11,0x7F,0x00,0x7E,0x62,0x12,0x07,\n0xA5,0x02,0x02,0x2F,0x7D,0x04,0x7C,0x00,\n0x7F,0x01,0x7E,0x66,0x12,0x07,0xA5,0x7D,\n0x80,0x7C,0x00,0x7F,0x00,0x7E,0x66,0x12,\n0x07,0xA5,0x7F,0x02,0x7E,0x66,0x12,0x07,\n0x60,0xEF,0x44,0x02,0x44,0x04,0xFD,0xAC,\n0x06,0x7F,0x02,0x7E,0x66,0x12,0x07,0xA5,\n0x7D,0x04,0x7C,0x00,0x7F,0x01,0x7E,0x66,\n0x12,0x07,0xA5,0x7D,0xC0,0x7C,0x00,0x7F,\n0x00,0x7E,0x66,0x02,0x07,0xA5,0xC0,0xE0,\n0xC0,0xF0,0xC0,0x83,0xC0,0x82,0xC0,0xD0,\n0x75,0xD0,0x00,0xC0,0x00,0x78,0x17,0xE6,\n0xF5,0x8C,0x78,0x18,0xE6,0xF5,0x8A,0x90,\n0x06,0x31,0xE4,0x75,0xF0,0x01,0x12,0x00,\n0x0E,0x90,0x06,0x33,0xE4,0x75,0xF0,0x01,\n0x12,0x00,0x0E,0xD0,0x00,0xD0,0xD0,0xD0,\n0x82,0xD0,0x83,0xD0,0xF0,0xD0,0xE0,0x32,\n0xC2,0xAF,0xAD,0x07,0xAC,0x06,0x8C,0xA2,\n0x8D,0xA3,0x75,0xA0,0x01,0x00,0x00,0x00,\n0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,\n0xAE,0xA1,0xBE,0x00,0xF0,0xAE,0xA6,0xAF,\n0xA7,0xD2,0xAF,0x22,0x7D,0x20,0x7C,0x0F,\n0x7F,0x02,0x7E,0x66,0x12,0x07,0xA5,0x7D,\n0x01,0x7C,0x00,0x7F,0x01,0x7E,0x66,0x12,\n0x07,0xA5,0x7D,0xC0,0x7C,0x00,0x7F,0x00,\n0x7E,0x66,0x02,0x07,0xA5,0xC2,0xAF,0xAB,\n0x07,0xAA,0x06,0x8A,0xA2,0x8B,0xA3,0x8C,\n0xA4,0x8D,0xA5,0x75,0xA0,0x03,0x00,0x00,\n0x00,0xAA,0xA1,0xBA,0x00,0xF8,0xD2,0xAF,\n0x22,0x7F,0x0C,0x7E,0x13,0x12,0x07,0x60,\n0xEF,0x44,0x50,0xFD,0xAC,0x06,0x7F,0x0C,\n0x7E,0x13,0x02,0x07,0xA5,0x12,0x07,0xC1,\n0x12,0x07,0xEC,0x12,0x04,0x25,0x02,0x00,\n0x03,0x42,0x06,0x33,0x00,0x00,0x42,0x06,\n0x31,0x00,0x00,0x00,0xE4,0xF5,0x8E,0x22,};\n\n\n#define SGMII_INIT_SIZE 1183\nrtk_uint8 Sgmii_Init[SGMII_INIT_SIZE] = {\n0x02,0x03,0x81,0xE4,0xF5,0xA8,0xD2,0xAF,\n0x22,0x00,0x00,0x02,0x04,0x0D,0xC5,0xF0,\n0xF8,0xA3,0xE0,0x28,0xF0,0xC5,0xF0,0xF8,\n0xE5,0x82,0x15,0x82,0x70,0x02,0x15,0x83,\n0xE0,0x38,0xF0,0x22,0x75,0xF0,0x08,0x75,\n0x82,0x00,0xEF,0x2F,0xFF,0xEE,0x33,0xFE,\n0xCD,0x33,0xCD,0xCC,0x33,0xCC,0xC5,0x82,\n0x33,0xC5,0x82,0x9B,0xED,0x9A,0xEC,0x99,\n0xE5,0x82,0x98,0x40,0x0C,0xF5,0x82,0xEE,\n0x9B,0xFE,0xED,0x9A,0xFD,0xEC,0x99,0xFC,\n0x0F,0xD5,0xF0,0xD6,0xE4,0xCE,0xFB,0xE4,\n0xCD,0xFA,0xE4,0xCC,0xF9,0xA8,0x82,0x22,\n0xB8,0x00,0xC1,0xB9,0x00,0x59,0xBA,0x00,\n0x2D,0xEC,0x8B,0xF0,0x84,0xCF,0xCE,0xCD,\n0xFC,0xE5,0xF0,0xCB,0xF9,0x78,0x18,0xEF,\n0x2F,0xFF,0xEE,0x33,0xFE,0xED,0x33,0xFD,\n0xEC,0x33,0xFC,0xEB,0x33,0xFB,0x10,0xD7,\n0x03,0x99,0x40,0x04,0xEB,0x99,0xFB,0x0F,\n0xD8,0xE5,0xE4,0xF9,0xFA,0x22,0x78,0x18,\n0xEF,0x2F,0xFF,0xEE,0x33,0xFE,0xED,0x33,\n0xFD,0xEC,0x33,0xFC,0xC9,0x33,0xC9,0x10,\n0xD7,0x05,0x9B,0xE9,0x9A,0x40,0x07,0xEC,\n0x9B,0xFC,0xE9,0x9A,0xF9,0x0F,0xD8,0xE0,\n0xE4,0xC9,0xFA,0xE4,0xCC,0xFB,0x22,0x75,\n0xF0,0x10,0xEF,0x2F,0xFF,0xEE,0x33,0xFE,\n0xED,0x33,0xFD,0xCC,0x33,0xCC,0xC8,0x33,\n0xC8,0x10,0xD7,0x07,0x9B,0xEC,0x9A,0xE8,\n0x99,0x40,0x0A,0xED,0x9B,0xFD,0xEC,0x9A,\n0xFC,0xE8,0x99,0xF8,0x0F,0xD5,0xF0,0xDA,\n0xE4,0xCD,0xFB,0xE4,0xCC,0xFA,0xE4,0xC8,\n0xF9,0x22,0xEB,0x9F,0xF5,0xF0,0xEA,0x9E,\n0x42,0xF0,0xE9,0x9D,0x42,0xF0,0xE8,0x9C,\n0x45,0xF0,0x22,0xE0,0xFC,0xA3,0xE0,0xFD,\n0xA3,0xE0,0xFE,0xA3,0xE0,0xFF,0x22,0xE0,\n0xF8,0xA3,0xE0,0xF9,0xA3,0xE0,0xFA,0xA3,\n0xE0,0xFB,0x22,0xEC,0xF0,0xA3,0xED,0xF0,\n0xA3,0xEE,0xF0,0xA3,0xEF,0xF0,0x22,0xE4,\n0x90,0x06,0x2C,0xF0,0xFD,0x7C,0x01,0x7F,\n0x3F,0x7E,0x1D,0x12,0x04,0x6B,0x7D,0x40,\n0x7C,0x00,0x7F,0x36,0x7E,0x13,0x12,0x04,\n0x6B,0xE4,0xFF,0xFE,0xFD,0x80,0x25,0xE4,\n0x7F,0xFF,0x7E,0xFF,0xFD,0xFC,0x90,0x06,\n0x24,0x12,0x01,0x0F,0xC3,0x12,0x00,0xF2,\n0x50,0x1B,0x90,0x06,0x24,0x12,0x01,0x03,\n0xEF,0x24,0x01,0xFF,0xE4,0x3E,0xFE,0xE4,\n0x3D,0xFD,0xE4,0x3C,0xFC,0x90,0x06,0x24,\n0x12,0x01,0x1B,0x80,0xD2,0xE4,0xF5,0xA8,\n0xD2,0xAF,0x7D,0x1F,0xFC,0x7F,0x49,0x7E,\n0x13,0x12,0x04,0x6B,0x12,0x04,0x92,0x7D,\n0x41,0x7C,0x00,0x7F,0x36,0x7E,0x13,0x12,\n0x04,0x6B,0xE4,0xFF,0xFE,0xFD,0x80,0x25,\n0xE4,0x7F,0x20,0x7E,0x4E,0xFD,0xFC,0x90,\n0x06,0x24,0x12,0x01,0x0F,0xC3,0x12,0x00,\n0xF2,0x50,0x1B,0x90,0x06,0x24,0x12,0x01,\n0x03,0xEF,0x24,0x01,0xFF,0xE4,0x3E,0xFE,\n0xE4,0x3D,0xFD,0xE4,0x3C,0xFC,0x90,0x06,\n0x24,0x12,0x01,0x1B,0x80,0xD2,0xC2,0x00,\n0xC2,0x01,0xD2,0xA9,0xD2,0x8C,0x7F,0x01,\n0x7E,0x62,0x12,0x04,0x47,0xEF,0x30,0xE2,\n0x07,0xE4,0x90,0x06,0x2C,0xF0,0x80,0xEE,\n0x90,0x06,0x2C,0xE0,0x70,0x12,0x12,0x02,\n0xDB,0x90,0x06,0x2C,0x74,0x01,0xF0,0xE4,\n0x90,0x06,0x2F,0xF0,0xA3,0xF0,0x80,0xD6,\n0xC3,0x90,0x06,0x30,0xE0,0x94,0x62,0x90,\n0x06,0x2F,0xE0,0x94,0x00,0x40,0xC7,0xE4,\n0xF0,0xA3,0xF0,0x12,0x02,0xDB,0x90,0x06,\n0x2C,0x74,0x01,0xF0,0x80,0xB8,0x75,0x0F,\n0x80,0x75,0x0E,0x7E,0x75,0x0D,0xAA,0x75,\n0x0C,0x83,0xE4,0xF5,0x10,0x7F,0x36,0x7E,\n0x13,0x12,0x04,0x47,0xEE,0xC4,0xF8,0x54,\n0xF0,0xC8,0xEF,0xC4,0x54,0x0F,0x48,0x54,\n0x07,0xFB,0x7A,0x00,0xEA,0x70,0x4A,0xEB,\n0x14,0x60,0x1C,0x14,0x60,0x27,0x24,0xFE,\n0x60,0x31,0x14,0x60,0x3C,0x24,0x05,0x70,\n0x38,0x75,0x0B,0x00,0x75,0x0A,0xC2,0x75,\n0x09,0xEB,0x75,0x08,0x0B,0x80,0x36,0x75,\n0x0B,0x40,0x75,0x0A,0x59,0x75,0x09,0x73,\n0x75,0x08,0x07,0x80,0x28,0x75,0x0B,0x00,\n0x75,0x0A,0xE1,0x75,0x09,0xF5,0x75,0x08,\n0x05,0x80,0x1A,0x75,0x0B,0xA0,0x75,0x0A,\n0xAC,0x75,0x09,0xB9,0x75,0x08,0x03,0x80,\n0x0C,0x75,0x0B,0x00,0x75,0x0A,0x62,0x75,\n0x09,0x3D,0x75,0x08,0x01,0x75,0x89,0x11,\n0xE4,0x7B,0x60,0x7A,0x09,0xF9,0xF8,0xAF,\n0x0B,0xAE,0x0A,0xAD,0x09,0xAC,0x08,0x12,\n0x00,0x60,0xAA,0x06,0xAB,0x07,0xC3,0xE4,\n0x9B,0xFB,0xE4,0x9A,0xFA,0x78,0x17,0xF6,\n0xAF,0x03,0xEF,0x08,0xF6,0x18,0xE6,0xF5,\n0x8C,0x08,0xE6,0xF5,0x8A,0x74,0x0D,0x2B,\n0xFB,0xE4,0x3A,0x18,0xF6,0xAF,0x03,0xEF,\n0x08,0xF6,0x75,0x88,0x10,0x53,0x8E,0xC7,\n0xD2,0xA9,0x22,0x7D,0x02,0x7C,0x00,0x7F,\n0x4A,0x7E,0x13,0x12,0x04,0x6B,0x7D,0x46,\n0x7C,0x71,0x7F,0x02,0x7E,0x66,0x12,0x04,\n0x6B,0x7D,0x03,0x7C,0x00,0x7F,0x01,0x7E,\n0x66,0x12,0x04,0x6B,0x7D,0xC0,0x7C,0x00,\n0x7F,0x00,0x7E,0x66,0x12,0x04,0x6B,0xE4,\n0xFF,0xFE,0x0F,0xBF,0x00,0x01,0x0E,0xEF,\n0x64,0x64,0x4E,0x70,0xF5,0x7D,0x04,0x7C,\n0x00,0x7F,0x02,0x7E,0x66,0x12,0x04,0x6B,\n0x7D,0x00,0x7C,0x04,0x7F,0x01,0x7E,0x66,\n0x12,0x04,0x6B,0x7D,0xC0,0x7C,0x00,0x7F,\n0x00,0x7E,0x66,0x12,0x04,0x6B,0xE4,0xFD,\n0xFC,0x7F,0x02,0x7E,0x66,0x12,0x04,0x6B,\n0x7D,0x00,0x7C,0x04,0x7F,0x01,0x7E,0x66,\n0x12,0x04,0x6B,0x7D,0xC0,0x7C,0x00,0x7F,\n0x00,0x7E,0x66,0x12,0x04,0x6B,0xE4,0xFD,\n0xFC,0x7F,0x4A,0x7E,0x13,0x12,0x04,0x6B,\n0x7D,0x06,0x7C,0x71,0x7F,0x02,0x7E,0x66,\n0x12,0x04,0x6B,0x7D,0x03,0x7C,0x00,0x7F,\n0x01,0x7E,0x66,0x12,0x04,0x6B,0x7D,0xC0,\n0x7C,0x00,0x7F,0x00,0x7E,0x66,0x02,0x04,\n0x6B,0x78,0x7F,0xE4,0xF6,0xD8,0xFD,0x75,\n0x81,0x3C,0x02,0x03,0xC8,0x02,0x01,0x27,\n0xE4,0x93,0xA3,0xF8,0xE4,0x93,0xA3,0x40,\n0x03,0xF6,0x80,0x01,0xF2,0x08,0xDF,0xF4,\n0x80,0x29,0xE4,0x93,0xA3,0xF8,0x54,0x07,\n0x24,0x0C,0xC8,0xC3,0x33,0xC4,0x54,0x0F,\n0x44,0x20,0xC8,0x83,0x40,0x04,0xF4,0x56,\n0x80,0x01,0x46,0xF6,0xDF,0xE4,0x80,0x0B,\n0x01,0x02,0x04,0x08,0x10,0x20,0x40,0x80,\n0x90,0x04,0x87,0xE4,0x7E,0x01,0x93,0x60,\n0xBC,0xA3,0xFF,0x54,0x3F,0x30,0xE5,0x09,\n0x54,0x1F,0xFE,0xE4,0x93,0xA3,0x60,0x01,\n0x0E,0xCF,0x54,0xC0,0x25,0xE0,0x60,0xA8,\n0x40,0xB8,0xE4,0x93,0xA3,0xFA,0xE4,0x93,\n0xA3,0xF8,0xE4,0x93,0xA3,0xC8,0xC5,0x82,\n0xC8,0xCA,0xC5,0x83,0xCA,0xF0,0xA3,0xC8,\n0xC5,0x82,0xC8,0xCA,0xC5,0x83,0xCA,0xDF,\n0xE9,0xDE,0xE7,0x80,0xBE,0xC0,0xE0,0xC0,\n0xF0,0xC0,0x83,0xC0,0x82,0xC0,0xD0,0x75,\n0xD0,0x00,0xC0,0x00,0x78,0x17,0xE6,0xF5,\n0x8C,0x78,0x18,0xE6,0xF5,0x8A,0x90,0x06,\n0x2D,0xE4,0x75,0xF0,0x01,0x12,0x00,0x0E,\n0x90,0x06,0x2F,0xE4,0x75,0xF0,0x01,0x12,\n0x00,0x0E,0xD0,0x00,0xD0,0xD0,0xD0,0x82,\n0xD0,0x83,0xD0,0xF0,0xD0,0xE0,0x32,0xC2,\n0xAF,0xAD,0x07,0xAC,0x06,0x8C,0xA2,0x8D,\n0xA3,0x75,0xA0,0x01,0x00,0x00,0x00,0x00,\n0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xAE,\n0xA1,0xBE,0x00,0xF0,0xAE,0xA6,0xAF,0xA7,\n0xD2,0xAF,0x22,0xC2,0xAF,0xAB,0x07,0xAA,\n0x06,0x8A,0xA2,0x8B,0xA3,0x8C,0xA4,0x8D,\n0xA5,0x75,0xA0,0x03,0x00,0x00,0x00,0xAA,\n0xA1,0xBA,0x00,0xF8,0xD2,0xAF,0x22,0x42,\n0x06,0x2F,0x00,0x00,0x42,0x06,0x2D,0x00,\n0x00,0x00,0x12,0x04,0x9B,0x12,0x02,0x16,\n0x02,0x00,0x03,0xE4,0xF5,0x8E,0x22,};\n\n\n/* Function Name:\n *      rtl8367c_setAsicPortUnknownDaBehavior\n * Description:\n *      Set UNDA behavior\n * Input:\n *      port        - port ID\n *      behavior    - 0: flooding to unknwon DA portmask; 1: drop; 2:trap; 3: flooding\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_NOT_ALLOWED  - Invalid behavior\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicPortUnknownDaBehavior(rtk_uint32 port, rtk_uint32 behavior)\n{\n    if(port >= RTL8367C_PORTNO)\n        return RT_ERR_PORT_ID;\n\n    if(behavior >= L2_UNDA_BEHAVE_END)\n        return RT_ERR_NOT_ALLOWED;\n\n    if(port < 8)\n        return rtl8367c_setAsicRegBits(RTL8367C_REG_UNKNOWN_UNICAST_DA_PORT_BEHAVE, RTL8367C_Port0_ACTION_MASK << (port * 2), behavior);\n    else\n        return rtl8367c_setAsicRegBits(RTL8367C_REG_UNKNOWN_UNICAST_DA_PORT_BEHAVE_EXT, RTL8367C_PORT8_ACTION_MASK << ((port-8) * 2), behavior);\n}\n/* Function Name:\n *      rtl8367c_getAsicPortUnknownDaBehavior\n * Description:\n *      Get UNDA behavior\n * Input:\n *      port        - port ID\n * Output:\n *      pBehavior   - 0: flooding to unknwon DA portmask; 1: drop; 2:trap; 3: flooding\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicPortUnknownDaBehavior(rtk_uint32 port, rtk_uint32 *pBehavior)\n{\n    if(port >= RTL8367C_PORTNO)\n        return RT_ERR_PORT_ID;\n\n    if(port < 8)\n        return rtl8367c_getAsicRegBits(RTL8367C_REG_UNKNOWN_UNICAST_DA_PORT_BEHAVE, RTL8367C_Port0_ACTION_MASK << (port * 2), pBehavior);\n    else\n        return rtl8367c_getAsicRegBits(RTL8367C_REG_UNKNOWN_UNICAST_DA_PORT_BEHAVE_EXT, RTL8367C_PORT8_ACTION_MASK << ((port-8) * 2), pBehavior);\n}\n/* Function Name:\n *      rtl8367c_setAsicPortUnknownSaBehavior\n * Description:\n *      Set UNSA behavior\n * Input:\n *      behavior    - 0: flooding; 1: drop; 2:trap\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_NOT_ALLOWED  - Invalid behavior\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicPortUnknownSaBehavior(rtk_uint32 behavior)\n{\n    if(behavior >= L2_BEHAVE_SA_END)\n        return RT_ERR_NOT_ALLOWED;\n\n    return rtl8367c_setAsicRegBits(RTL8367C_PORT_SECURIT_CTRL_REG, RTL8367C_UNKNOWN_SA_BEHAVE_MASK, behavior);\n}\n/* Function Name:\n *      rtl8367c_getAsicPortUnknownSaBehavior\n * Description:\n *      Get UNSA behavior\n * Input:\n *      pBehavior   - 0: flooding; 1: drop; 2:trap\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicPortUnknownSaBehavior(rtk_uint32 *pBehavior)\n{\n    return rtl8367c_getAsicRegBits(RTL8367C_PORT_SECURIT_CTRL_REG, RTL8367C_UNKNOWN_SA_BEHAVE_MASK, pBehavior);\n}\n/* Function Name:\n *      rtl8367c_setAsicPortUnmatchedSaBehavior\n * Description:\n *      Set Unmatched SA behavior\n * Input:\n *      behavior    - 0: flooding; 1: drop; 2:trap\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_NOT_ALLOWED  - Invalid behavior\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicPortUnmatchedSaBehavior(rtk_uint32 behavior)\n{\n    if(behavior >= L2_BEHAVE_SA_END)\n        return RT_ERR_NOT_ALLOWED;\n\n    return rtl8367c_setAsicRegBits(RTL8367C_PORT_SECURIT_CTRL_REG, RTL8367C_UNMATCHED_SA_BEHAVE_MASK, behavior);\n}\n/* Function Name:\n *      rtl8367c_getAsicPortUnmatchedSaBehavior\n * Description:\n *      Get Unmatched SA behavior\n * Input:\n *      pBehavior   - 0: flooding; 1: drop; 2:trap\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicPortUnmatchedSaBehavior(rtk_uint32 *pBehavior)\n{\n    return rtl8367c_getAsicRegBits(RTL8367C_PORT_SECURIT_CTRL_REG, RTL8367C_UNMATCHED_SA_BEHAVE_MASK, pBehavior);\n}\n\n/* Function Name:\n *      rtl8367c_setAsicPortUnmatchedSaMoving\n * Description:\n *      Set Unmatched SA moving state\n * Input:\n *      port        - Port ID\n *      enabled     - 0: can't move to new port; 1: can move to new port\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Error Port ID\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicPortUnmatchedSaMoving(rtk_uint32 port, rtk_uint32 enabled)\n{\n    if(port >= RTL8367C_PORTNO)\n        return RT_ERR_PORT_ID;\n\n    return rtl8367c_setAsicRegBit(RTL8367C_REG_L2_SA_MOVING_FORBID, port, (enabled == 1) ? 0 : 1);\n}\n\n/* Function Name:\n *      rtl8367c_getAsicPortUnmatchedSaMoving\n * Description:\n *      Get Unmatched SA moving state\n * Input:\n *      port        - Port ID\n * Output:\n *      pEnabled    - 0: can't move to new port; 1: can move to new port\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Error Port ID\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicPortUnmatchedSaMoving(rtk_uint32 port, rtk_uint32 *pEnabled)\n{\n    rtk_uint32 data;\n    ret_t retVal;\n\n    if(port >= RTL8367C_PORTNO)\n        return RT_ERR_PORT_ID;\n\n    if((retVal = rtl8367c_getAsicRegBit(RTL8367C_REG_L2_SA_MOVING_FORBID, port, &data)) != RT_ERR_OK)\n        return retVal;\n\n    *pEnabled = (data == 1) ? 0 : 1;\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtl8367c_setAsicPortUnknownDaFloodingPortmask\n * Description:\n *      Set UNDA flooding portmask\n * Input:\n *      portmask    - portmask(0~0xFF)\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_MASK    - Invalid portmask\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicPortUnknownDaFloodingPortmask(rtk_uint32 portmask)\n{\n    if(portmask > RTL8367C_PORTMASK)\n        return RT_ERR_PORT_MASK;\n\n    return rtl8367c_setAsicReg(RTL8367C_UNUCAST_FLOADING_PMSK_REG, portmask);\n}\n/* Function Name:\n *      rtl8367c_getAsicPortUnknownDaFloodingPortmask\n * Description:\n *      Get UNDA flooding portmask\n * Input:\n *      pPortmask   - portmask(0~0xFF)\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicPortUnknownDaFloodingPortmask(rtk_uint32 *pPortmask)\n{\n    return rtl8367c_getAsicReg(RTL8367C_UNUCAST_FLOADING_PMSK_REG, pPortmask);\n}\n/* Function Name:\n *      rtl8367c_setAsicPortUnknownMulticastFloodingPortmask\n * Description:\n *      Set UNMC flooding portmask\n * Input:\n *      portmask    - portmask(0~0xFF)\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_MASK    - Invalid portmask\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicPortUnknownMulticastFloodingPortmask(rtk_uint32 portmask)\n{\n    if(portmask > RTL8367C_PORTMASK)\n        return RT_ERR_PORT_MASK;\n\n    return rtl8367c_setAsicReg(RTL8367C_UNMCAST_FLOADING_PMSK_REG, portmask);\n}\n/* Function Name:\n *      rtl8367c_getAsicPortUnknownMulticastFloodingPortmask\n * Description:\n *      Get UNMC flooding portmask\n * Input:\n *      pPortmask   - portmask(0~0xFF)\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicPortUnknownMulticastFloodingPortmask(rtk_uint32 *pPortmask)\n{\n    return rtl8367c_getAsicReg(RTL8367C_UNMCAST_FLOADING_PMSK_REG, pPortmask);\n}\n/* Function Name:\n *      rtl8367c_setAsicPortBcastFloodingPortmask\n * Description:\n *      Set Bcast flooding portmask\n * Input:\n *      portmask    - portmask(0~0xFF)\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_MASK    - Invalid portmask\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicPortBcastFloodingPortmask(rtk_uint32 portmask)\n{\n    if(portmask > RTL8367C_PORTMASK)\n        return RT_ERR_PORT_MASK;\n\n    return rtl8367c_setAsicReg(RTL8367C_BCAST_FLOADING_PMSK_REG, portmask);\n}\n/* Function Name:\n *      rtl8367c_getAsicPortBcastFloodingPortmask\n * Description:\n *      Get Bcast flooding portmask\n * Input:\n *      pPortmask   - portmask(0~0xFF)\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicPortBcastFloodingPortmask(rtk_uint32 *pPortmask)\n{\n    return rtl8367c_getAsicReg(RTL8367C_BCAST_FLOADING_PMSK_REG, pPortmask);\n}\n/* Function Name:\n *      rtl8367c_setAsicPortBlockSpa\n * Description:\n *      Set disabling blocking frame if source port and destination port are the same\n * Input:\n *      port    - Physical port number (0~7)\n *      permit  - 0: block; 1: permit\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n *      RT_ERR_PORT_ID  - Invalid port number\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicPortBlockSpa(rtk_uint32 port, rtk_uint32 permit)\n{\n    if(port >= RTL8367C_PORTNO)\n        return RT_ERR_PORT_ID;\n\n    return rtl8367c_setAsicRegBit(RTL8367C_SOURCE_PORT_BLOCK_REG, port, permit);\n}\n/* Function Name:\n *      rtl8367c_getAsicPortBlockSpa\n * Description:\n *      Get disabling blocking frame if source port and destination port are the same\n * Input:\n *      port    - Physical port number (0~7)\n *      pPermit     - 0: block; 1: permit\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n *      RT_ERR_PORT_ID  - Invalid port number\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicPortBlockSpa(rtk_uint32 port, rtk_uint32* pPermit)\n{\n    if(port >= RTL8367C_PORTNO)\n        return RT_ERR_PORT_ID;\n\n    return rtl8367c_getAsicRegBit(RTL8367C_SOURCE_PORT_BLOCK_REG, port, pPermit);\n}\n/* Function Name:\n *      rtl8367c_setAsicPortDos\n * Description:\n *      Set DOS function\n * Input:\n *      type    - DOS type\n *      drop    - 0: permit; 1: drop\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_OUT_OF_RANGE - Invalid payload index\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicPortDos(rtk_uint32 type, rtk_uint32 drop)\n{\n    if(type >= DOS_END)\n        return RT_ERR_OUT_OF_RANGE;\n\n    return rtl8367c_setAsicRegBit(RTL8367C_REG_DOS_CFG, RTL8367C_DROP_DAEQSA_OFFSET + type, drop);\n}\n/* Function Name:\n *      rtl8367c_getAsicPortDos\n * Description:\n *      Get DOS function\n * Input:\n *      type    - DOS type\n *      pDrop   - 0: permit; 1: drop\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_OUT_OF_RANGE - Invalid payload index\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicPortDos(rtk_uint32 type, rtk_uint32* pDrop)\n{\n    if(type >= DOS_END)\n        return RT_ERR_OUT_OF_RANGE;\n\n    return rtl8367c_getAsicRegBit(RTL8367C_REG_DOS_CFG, RTL8367C_DROP_DAEQSA_OFFSET + type,pDrop);\n}\n/* Function Name:\n *      rtl8367c_setAsicPortForceLink\n * Description:\n *      Set port force linking configuration\n * Input:\n *      port        - Physical port number (0~7)\n *      pPortAbility - port ability configuration\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n *      RT_ERR_PORT_ID  - Invalid port number\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicPortForceLink(rtk_uint32 port, rtl8367c_port_ability_t *pPortAbility)\n{\n    rtk_uint32 regData = 0;\n\n    /* Invalid input parameter */\n    if(port >= RTL8367C_PORTNO)\n        return RT_ERR_PORT_ID;\n\n    regData |= pPortAbility->forcemode << 12;\n    regData |= pPortAbility->mstfault << 9;\n    regData |= pPortAbility->mstmode << 8;\n    regData |= pPortAbility->nway << 7;\n    regData |= pPortAbility->txpause << 6;\n    regData |= pPortAbility->rxpause << 5;\n    regData |= pPortAbility->link << 4;\n    regData |= pPortAbility->duplex << 2;\n    regData |= pPortAbility->speed;\n\n    return rtl8367c_setAsicReg(RTL8367C_REG_MAC0_FORCE_SELECT+port, regData);\n}\n/* Function Name:\n *      rtl8367c_getAsicPortForceLink\n * Description:\n *      Get port force linking configuration\n * Input:\n *      port        - Physical port number (0~7)\n *      pPortAbility - port ability configuration\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n *      RT_ERR_PORT_ID  - Invalid port number\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicPortForceLink(rtk_uint32 port, rtl8367c_port_ability_t *pPortAbility)\n{\n    ret_t retVal;\n    rtk_uint32 regData;\n\n    /* Invalid input parameter */\n    if(port >= RTL8367C_PORTNO)\n        return RT_ERR_PORT_ID;\n\n    retVal = rtl8367c_getAsicReg(RTL8367C_REG_MAC0_FORCE_SELECT + port, &regData);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    pPortAbility->forcemode = (regData >> 12) & 0x0001;\n    pPortAbility->mstfault  = (regData >> 9) & 0x0001;\n    pPortAbility->mstmode   = (regData >> 8) & 0x0001;\n    pPortAbility->nway      = (regData >> 7) & 0x0001;\n    pPortAbility->txpause   = (regData >> 6) & 0x0001;\n    pPortAbility->rxpause   = (regData >> 5) & 0x0001;\n    pPortAbility->link      = (regData >> 4) & 0x0001;\n    pPortAbility->duplex    = (regData >> 2) & 0x0001;\n    pPortAbility->speed     = regData & 0x0003;\n\n    return RT_ERR_OK;\n}\n/* Function Name:\n *      rtl8367c_getAsicPortStatus\n * Description:\n *      Get port link status\n * Input:\n *      port        - Physical port number (0~7)\n *      pPortAbility - port ability configuration\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n *      RT_ERR_PORT_ID  - Invalid port number\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicPortStatus(rtk_uint32 port, rtl8367c_port_status_t *pPortStatus)\n{\n    ret_t retVal;\n    rtk_uint32 regData;\n\n    /* Invalid input parameter */\n    if(port >= RTL8367C_PORTNO)\n        return RT_ERR_PORT_ID;\n\n    retVal = rtl8367c_getAsicReg(RTL8367C_REG_PORT0_STATUS+port,&regData);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    pPortStatus->lpi1000  = (regData >> 11) & 0x0001;\n    pPortStatus->lpi100   = (regData >> 10) & 0x0001;\n    pPortStatus->mstfault = (regData >> 9) & 0x0001;\n    pPortStatus->mstmode  = (regData >> 8) & 0x0001;\n    pPortStatus->nway     = (regData >> 7) & 0x0001;\n    pPortStatus->txpause  = (regData >> 6) & 0x0001;\n    pPortStatus->rxpause  = (regData >> 5) & 0x0001;\n    pPortStatus->link     = (regData >> 4) & 0x0001;\n    pPortStatus->duplex   = (regData >> 2) & 0x0001;\n    pPortStatus->speed    = regData  & 0x0003;\n\n    return RT_ERR_OK;\n}\n/* Function Name:\n *      rtl8367c_setAsicPortForceLinkExt\n * Description:\n *      Set external interface force linking configuration\n * Input:\n *      id          - external interface id (0~2)\n *      portAbility - port ability configuration\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_OUT_OF_RANGE - input parameter out of range\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicPortForceLinkExt(rtk_uint32 id, rtl8367c_port_ability_t *pPortAbility)\n{\n    rtk_uint32 retVal, regValue, regValue2, type, sgmiibit, hisgmiibit;\n    rtk_uint32 reg_data = 0;\n    rtk_uint32 i = 0;\n\n    /* Invalid input parameter */\n    if(id >= RTL8367C_EXTNO)\n        return RT_ERR_OUT_OF_RANGE;\n\n    reg_data |= pPortAbility->forcemode << 12;\n    reg_data |= pPortAbility->mstfault << 9;\n    reg_data |= pPortAbility->mstmode << 8;\n    reg_data |= pPortAbility->nway << 7;\n    reg_data |= pPortAbility->txpause << 6;\n    reg_data |= pPortAbility->rxpause << 5;\n    reg_data |= pPortAbility->link << 4;\n    reg_data |= pPortAbility->duplex << 2;\n    reg_data |= pPortAbility->speed;\n\n    if((retVal = rtl8367c_setAsicReg(0x13C2, 0x0249)) != RT_ERR_OK)\n        return retVal;\n    /*get chip ID */\n    if((retVal = rtl8367c_getAsicReg(0x1300, &regValue)) != RT_ERR_OK)\n        return retVal;\n\n    if((retVal = rtl8367c_setAsicReg(0x13C2, 0x0000)) != RT_ERR_OK)\n        return retVal;\n\n    type = 0;\n\n    switch (regValue)\n    {\n        case 0x0276:\n        case 0x0597:\n        case 0x6367:\n            type = 1;\n            break;\n        case 0x0652:\n        case 0x6368:\n            type = 2;\n            break;\n        case 0x0801:\n        case 0x6511:\n            type = 3;\n            break;\n        default:\n            return RT_ERR_FAILED;\n    }\n\n    if (1 == type)\n    {\n        if(1 == id)\n        {\n            if ((retVal = rtl8367c_getAsicReg(RTL8367C_REG_REG_TO_ECO4, &regValue)) != RT_ERR_OK)\n                return retVal;\n\n            if((regValue & (0x0001 << 5)) && (regValue & (0x0001 << 7)))\n            {\n                return RT_ERR_OK;\n            }\n\n            if((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_SDS_MISC, RTL8367C_CFG_SGMII_FDUP_OFFSET, pPortAbility->duplex)) != RT_ERR_OK)\n                return retVal;\n\n            if((retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_SDS_MISC, RTL8367C_CFG_SGMII_SPD_MASK, pPortAbility->speed)) != RT_ERR_OK)\n                return retVal;\n\n            if((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_SDS_MISC, RTL8367C_CFG_SGMII_LINK_OFFSET, pPortAbility->link)) != RT_ERR_OK)\n                return retVal;\n\n            if((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_SDS_MISC, RTL8367C_CFG_SGMII_TXFC_OFFSET, pPortAbility->txpause)) != RT_ERR_OK)\n                return retVal;\n\n            if((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_SDS_MISC, RTL8367C_CFG_SGMII_RXFC_OFFSET, pPortAbility->rxpause)) != RT_ERR_OK)\n                return retVal;\n        }\n\n        if(0 == id || 1 == id)\n            return rtl8367c_setAsicReg(RTL8367C_REG_DIGITAL_INTERFACE0_FORCE + id, reg_data);\n        else\n            return rtl8367c_setAsicReg(RTL8367C_REG_DIGITAL_INTERFACE2_FORCE, reg_data);\n    }\n    else if (2 == type)\n    {\n        if (1 == id)\n        {\n             if((retVal = rtl8367c_setAsicRegBit(0x1311, 2, pPortAbility->duplex)) != RT_ERR_OK)\n                return retVal;\n\n            if((retVal = rtl8367c_setAsicRegBits(0x1311, 0x3, pPortAbility->speed)) != RT_ERR_OK)\n                return retVal;\n\n            if((retVal = rtl8367c_setAsicRegBit(0x1311, 4, pPortAbility->link)) != RT_ERR_OK)\n                return retVal;\n\n            if((retVal = rtl8367c_setAsicRegBit(0x1311, 6, pPortAbility->txpause)) != RT_ERR_OK)\n                return retVal;\n\n            if((retVal = rtl8367c_setAsicRegBit(0x1311, 5, pPortAbility->rxpause)) != RT_ERR_OK)\n                return retVal;\n\n            if((retVal = rtl8367c_setAsicRegBit(0x1311, 12, pPortAbility->forcemode)) != RT_ERR_OK)\n                return retVal;\n\n            if (pPortAbility->link == 1)\n            {\n                if((retVal = rtl8367c_setAsicRegBit(0x1311, 4, 0)) != RT_ERR_OK)\n                    return retVal;\n\n                if((retVal = rtl8367c_setAsicRegBit(0x1311, 4, 1)) != RT_ERR_OK)\n                    return retVal;\n            }\n            else\n            {\n                if((retVal = rtl8367c_setAsicRegBits(0x1311, 0x3, 2)) != RT_ERR_OK)\n                    return retVal;\n            }\n\n\n            if((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_SDS_MISC, RTL8367C_CFG_SGMII_FDUP_OFFSET, pPortAbility->duplex)) != RT_ERR_OK)\n                return retVal;\n\n            if((retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_SDS_MISC, RTL8367C_CFG_SGMII_SPD_MASK, pPortAbility->speed)) != RT_ERR_OK)\n                return retVal;\n\n            if((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_SDS_MISC, RTL8367C_CFG_SGMII_LINK_OFFSET, pPortAbility->link)) != RT_ERR_OK)\n                return retVal;\n\n            if((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_SDS_MISC, RTL8367C_CFG_SGMII_TXFC_OFFSET, pPortAbility->txpause)) != RT_ERR_OK)\n                return retVal;\n\n            if((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_SDS_MISC, RTL8367C_CFG_SGMII_RXFC_OFFSET, pPortAbility->rxpause)) != RT_ERR_OK)\n                return retVal;\n        }\n        else if (2 == id)\n        {\n            if((retVal = rtl8367c_setAsicRegBit(0x13c4, 2, pPortAbility->duplex)) != RT_ERR_OK)\n                return retVal;\n\n            if((retVal = rtl8367c_setAsicRegBits(0x13c4, 0x3, pPortAbility->speed)) != RT_ERR_OK)\n                return retVal;\n\n            if((retVal = rtl8367c_setAsicRegBit(0x13c4, 4, pPortAbility->link)) != RT_ERR_OK)\n                return retVal;\n\n            if((retVal = rtl8367c_setAsicRegBit(0x13c4, 6, pPortAbility->txpause)) != RT_ERR_OK)\n                return retVal;\n\n            if((retVal = rtl8367c_setAsicRegBit(0x13c4, 5, pPortAbility->rxpause)) != RT_ERR_OK)\n                return retVal;\n\n            if((retVal = rtl8367c_setAsicRegBit(0x13c4, 12, pPortAbility->forcemode)) != RT_ERR_OK)\n                return retVal;\n\n            if (pPortAbility->link == 1)\n            {\n                if((retVal = rtl8367c_setAsicRegBit(0x13c4, 4, 0)) != RT_ERR_OK)\n                    return retVal;\n\n                if((retVal = rtl8367c_setAsicRegBit(0x13c4, 4, 1)) != RT_ERR_OK)\n                    return retVal;\n            }\n            else\n            {\n                if((retVal = rtl8367c_setAsicRegBits(0x13c4, 0x3, 2)) != RT_ERR_OK)\n                    return retVal;\n            }\n\n            if((retVal = rtl8367c_setAsicRegBit(0x1dc1, RTL8367C_CFG_SGMII_FDUP_OFFSET, pPortAbility->duplex)) != RT_ERR_OK)\n                return retVal;\n\n            if((retVal = rtl8367c_setAsicRegBits(0x1dc1, RTL8367C_CFG_SGMII_SPD_MASK, pPortAbility->speed)) != RT_ERR_OK)\n                return retVal;\n\n            if((retVal = rtl8367c_setAsicRegBit(0x1dc1, RTL8367C_CFG_SGMII_LINK_OFFSET, pPortAbility->link)) != RT_ERR_OK)\n                return retVal;\n\n            if((retVal = rtl8367c_setAsicRegBit(0x1dc1, RTL8367C_CFG_SGMII_TXFC_OFFSET, pPortAbility->txpause)) != RT_ERR_OK)\n                return retVal;\n\n            if((retVal = rtl8367c_setAsicRegBit(0x1dc1, RTL8367C_CFG_SGMII_RXFC_OFFSET, pPortAbility->rxpause)) != RT_ERR_OK)\n                return retVal;\n        }\n\n    }\n    else if(3 == type)\n    {\n        if(1 == id)\n        {\n            if((retVal = rtl8367c_getAsicRegBit(0x1d11, 6, &sgmiibit)) != RT_ERR_OK)\n                return retVal;\n            if((retVal = rtl8367c_getAsicRegBit(0x1d11, 11, &hisgmiibit)) != RT_ERR_OK)\n                return retVal;\n\n            if ((sgmiibit == 1) || (hisgmiibit == 1))\n            {\n                /*for 1000x/100fx/1000x_100fx, param has to be set to serdes registers*/\n                if((retVal = rtl8367c_getAsicReg(0x1d41, &regValue)) != RT_ERR_OK)\n                    return retVal;\n\n                /*bit5: cfg_mac6_fib =1,  bit7: cfg_mac6_fib2=1*/\n                if((regValue & 0xa0) == 0xa0)\n                {\n                     /* new_cfg_sds_mode */\n                    if((retVal = rtl8367c_getAsicRegBits(0x1d95, 0x1f00, &regValue2)) != RT_ERR_OK)\n                        return retVal;\n\n                     /*1000X*/\n                    if(regValue2 == 0x4)\n                    {\n#if 0\n                        /* new_cfg_sds_mode:reset mode */\n                        if((retVal = rtl8367c_setAsicRegBits(0x1d95, 0x1f00, 0x1f)) != RT_ERR_OK)\n                            return retVal;\n#endif\n                        /* Enable new sds mode config */\n                        if((retVal = rtl8367c_setAsicRegBit(0x1d95, 13, 1)) != RT_ERR_OK)\n                            return retVal;\n\n                        /* 0 4 0  bit 12  set 1,  bit15~13 = 4*/\n                        if((retVal = rtl8367c_getAsicSdsReg(0, 4, 0, &reg_data)) != RT_ERR_OK)\n                            return retVal;\n                        reg_data &= 0xFFFF0FFF;\n                        reg_data |= 0x9000;\n                        if((retVal = rtl8367c_setAsicSdsReg(0,4,0, reg_data)) != RT_ERR_OK)\n                            return retVal;\n\n                        /* 0 0 2  bit 6  set 1,  bit13 set to 0, bit12 nway_en*/\n                        if((retVal = rtl8367c_getAsicSdsReg(0, 0, 2, &reg_data)) != RT_ERR_OK)\n                            return retVal;\n                        reg_data &= 0xFFFFDFFF;\n                        reg_data |= 0x40;\n                        if(pPortAbility->forcemode)\n                            reg_data &= 0xffffefff;\n                        else\n                            reg_data |= 0x1000;\n\n                        if((retVal = rtl8367c_setAsicSdsReg(0,0,2, reg_data)) != RT_ERR_OK)\n                            return retVal;\n\n                        /* 0 4 2  bit 8  rx pause,  bit7 tx pause*/\n                        if((retVal = rtl8367c_getAsicSdsReg(0, 4, 2, &reg_data)) != RT_ERR_OK)\n                            return retVal;\n\n                        if (pPortAbility->txpause)\n                            reg_data |= 0x80;\n                        else\n                            reg_data &= (~0x80);\n\n                        if (pPortAbility->rxpause)\n                            reg_data |= 0x100;\n                        else\n                            reg_data &= (~0x100);\n\n                        if((retVal = rtl8367c_setAsicSdsReg(0,4,2, reg_data)) != RT_ERR_OK)\n                            return retVal;\n\n                         /* 0 4 0  bit 12  set 0*/\n                        if((retVal = rtl8367c_getAsicSdsReg(0, 4, 0, &reg_data)) != RT_ERR_OK)\n                            return retVal;\n                        reg_data &= 0xFFFFEFFF;\n                        if((retVal = rtl8367c_setAsicSdsReg(0,4,0, reg_data)) != RT_ERR_OK)\n                            return retVal;\n\n                        /*new_cfg_sds_mode=1000x*/\n                        if((retVal = rtl8367c_setAsicRegBits(0x1d95, 0x1f00, 0x4)) != RT_ERR_OK)\n                            return retVal;\n\n                    }\n                    else if(regValue2 == 0x5)\n                    {\n#if 0\n                        /*100FX*/\n                        if((retVal = rtl8367c_setAsicRegBits(0x1d95, 0x1f00, 0x1f)) != RT_ERR_OK)\n                            return retVal;\n#endif\n                        /*cfg_sds_mode_sel_new=1  */\n                        if((retVal = rtl8367c_setAsicRegBit(0x1d95, 13, 1)) != RT_ERR_OK)\n                            return retVal;\n\n                        /* 0 4 0  bit 12  set 1,  bit15~13 = 5*/\n                        if((retVal = rtl8367c_getAsicSdsReg(0, 4, 0, &reg_data)) != RT_ERR_OK)\n                            return retVal;\n                        reg_data &= 0xFFFF0FFF;\n                        reg_data |= 0xB000;\n                        if((retVal = rtl8367c_setAsicSdsReg(0,4,0, reg_data)) != RT_ERR_OK)\n                            return retVal;\n\n                        /* 0 0 2  bit 6  set 0,  bit13 set to 1, bit12 0*/\n                        if((retVal = rtl8367c_getAsicSdsReg(0, 0, 2, &reg_data)) != RT_ERR_OK)\n                            return retVal;\n                        reg_data &= 0xFFFFFFBF;\n                        reg_data |= 0x2000;\n                        reg_data &= 0xffffefff;\n\n                        if((retVal = rtl8367c_setAsicSdsReg(0,0,2, reg_data)) != RT_ERR_OK)\n                            return retVal;\n\n                        /* 0 4 2  bit 8  rx pause,  bit7 tx pause*/\n                        if((retVal = rtl8367c_getAsicSdsReg(0, 4, 2, &reg_data)) != RT_ERR_OK)\n                            return retVal;\n                        if (pPortAbility->txpause)\n                            reg_data |= 0x80;\n                        else\n                            reg_data &= (~0x80);\n                        if (pPortAbility->rxpause)\n                            reg_data |= 0x100;\n                        else\n                            reg_data &= (~0x100);\n                        if((retVal = rtl8367c_setAsicSdsReg(0,4,2, reg_data)) != RT_ERR_OK)\n                            return retVal;\n\n                         /* 0 4 0  bit 12  set 0*/\n                        if((retVal = rtl8367c_getAsicSdsReg(0, 4, 0, &reg_data)) != RT_ERR_OK)\n                            return retVal;\n                        reg_data &= 0xFFFFEFFF;\n                        if((retVal = rtl8367c_setAsicSdsReg(0,4,0, reg_data)) != RT_ERR_OK)\n                            return retVal;\n                       /* new_cfg_sds_mode=1000x */\n                        if((retVal = rtl8367c_setAsicRegBits(0x1d95, 0x1f00, 0x5)) != RT_ERR_OK)\n                            return retVal;\n\n                    }\n                    else if(regValue2 == 0x7)\n                    {\n#if 0\n                        /*100FX*/\n                        if((retVal = rtl8367c_setAsicRegBits(0x1d95, 0x1f00, 0x1f)) != RT_ERR_OK)\n                            return retVal;\n#endif\n                        if((retVal = rtl8367c_setAsicRegBit(0x1d95, 13, 1)) != RT_ERR_OK)\n                            return retVal;\n\n                        /* 0 4 0  bit 12  set 1,  bit15~13 = 4*/\n                        if((retVal = rtl8367c_getAsicSdsReg(0, 4, 0, &reg_data)) != RT_ERR_OK)\n                            return retVal;\n                        reg_data &= 0xFFFF0FFF;\n                        reg_data |= 0x9000;\n                        if((retVal = rtl8367c_setAsicSdsReg(0,4,0, reg_data)) != RT_ERR_OK)\n                            return retVal;\n\n                        /* 0 0 2  bit 6  set 1,  bit13 set to 0, bit12 nway_en*/\n                        if((retVal = rtl8367c_getAsicSdsReg(0, 0, 2, &reg_data)) != RT_ERR_OK)\n                            return retVal;\n                        reg_data &= 0xFFFFDFFF;\n                        reg_data |= 0x40;\n                        if(pPortAbility->forcemode)\n                            reg_data &= 0xffffefff;\n                        else\n                            reg_data |= 0x1000;\n\n                        if((retVal = rtl8367c_setAsicSdsReg(0,0,2, reg_data)) != RT_ERR_OK)\n                            return retVal;\n\n                        /* 0 4 2  bit 8  rx pause,  bit7 tx pause*/\n                        if((retVal = rtl8367c_getAsicSdsReg(0, 4, 2, &reg_data)) != RT_ERR_OK)\n                            return retVal;\n                        if (pPortAbility->txpause)\n                            reg_data |= 0x80;\n                        else\n                            reg_data &= (~0x80);\n                        if (pPortAbility->rxpause)\n                            reg_data |= 0x100;\n                        else\n                            reg_data &=(~0x100);\n                        if((retVal = rtl8367c_setAsicSdsReg(0,4,2, reg_data)) != RT_ERR_OK)\n                            return retVal;\n\n                         /* 0 4 0  bit 12  set 0*/\n                        if((retVal = rtl8367c_getAsicSdsReg(0, 4, 0, &reg_data)) != RT_ERR_OK)\n                            return retVal;\n                        reg_data &= 0xFFFFEFFF;\n                        if((retVal = rtl8367c_setAsicSdsReg(0,4,0, reg_data)) != RT_ERR_OK)\n                            return retVal;\n\n                        /* 0 4 0  bit 12  set 1,  bit15~13 = 5*/\n                        if((retVal = rtl8367c_getAsicSdsReg(0, 4, 0, &reg_data)) != RT_ERR_OK)\n                            return retVal;\n                        reg_data &= 0xFFFF0FFF;\n                        reg_data |= 0xB000;\n                        if((retVal = rtl8367c_setAsicSdsReg(0,4,0, reg_data)) != RT_ERR_OK)\n                            return retVal;\n\n                        /* 0 0 2  bit 6  set 0,  bit13 set to 1, bit12 0*/\n                        if((retVal = rtl8367c_getAsicSdsReg(0, 0, 2, &reg_data)) != RT_ERR_OK)\n                            return retVal;\n                        reg_data &= 0xFFFFFFBF;\n                        reg_data |= 0x2000;\n                        reg_data &= 0xffffefff;\n\n                        if((retVal = rtl8367c_setAsicSdsReg(0,0,2, reg_data)) != RT_ERR_OK)\n                            return retVal;\n\n                        /* 0 4 2  bit 8  rx pause,  bit7 tx pause*/\n                        if((retVal = rtl8367c_getAsicSdsReg(0, 4, 2, &reg_data)) != RT_ERR_OK)\n                            return retVal;\n                        if (pPortAbility->txpause)\n                            reg_data |= 0x80;\n                        else\n                            reg_data &= 0xffffff7f;\n                        if (pPortAbility->rxpause)\n                            reg_data |= 0x100;\n                        else\n                            reg_data &= 0xfffffeff;\n                        if((retVal = rtl8367c_setAsicSdsReg(0,4,2, reg_data)) != RT_ERR_OK)\n                            return retVal;\n\n                         /* 0 4 0  bit 12  set 0*/\n                        if((retVal = rtl8367c_getAsicSdsReg(0, 4, 0, &reg_data)) != RT_ERR_OK)\n                            return retVal;\n                        reg_data &= 0xFFFFEFFF;\n                        if((retVal = rtl8367c_setAsicSdsReg(0,4,0, reg_data)) != RT_ERR_OK)\n                            return retVal;\n                        /*sds_mode:*/\n                        if((retVal = rtl8367c_setAsicRegBits(0x1d95, 0x1f00, 0x7)) != RT_ERR_OK)\n                            return retVal;\n\n                    }\n\n                    /*disable force ability   ---      */\n                    if((retVal = rtl8367c_setAsicRegBit(0x137c, 12, 0)) != RT_ERR_OK)\n                        return retVal;\n                    return RT_ERR_OK;\n\n                }\n\n                /* new_cfg_sds_mode */\n                if((retVal = rtl8367c_getAsicRegBits(0x1d95, 0x1f00, &regValue2)) != RT_ERR_OK)\n                    return retVal;\n                if(regValue2 == 0x2)\n                {\n#if 0\n                    /*SGMII*/\n                    if((retVal = rtl8367c_setAsicRegBits(0x1d95, 0x1f00, 0x1f)) != RT_ERR_OK)\n                        return retVal;\n#endif\n                    if((retVal = rtl8367c_setAsicRegBit(0x1d95, 13, 1)) != RT_ERR_OK)\n                        return retVal;\n\n                    for(i=0;i<0xfff; i++);\n\n                    /* 0 2 0  bit 8-9  nway*/\n                    if((retVal = rtl8367c_getAsicSdsReg(0, 2, 0, &reg_data)) != RT_ERR_OK)\n                        return retVal;\n                    reg_data &= 0xfffffcff;\n                    if (pPortAbility->nway)\n                        reg_data &= 0xfffffcff;\n                    else\n                        reg_data |= 0x100;\n                    if((retVal = rtl8367c_setAsicSdsReg(0,2,0, reg_data)) != RT_ERR_OK)\n                        return retVal;\n\n                    if((retVal = rtl8367c_setAsicRegBits(0x1d95, 0x1f00, 0x2)) != RT_ERR_OK)\n                        return retVal;\n\n                    for(i=0;i<0xfff; i++);\n\n                    if((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_SDS_MISC, RTL8367C_CFG_SGMII_FDUP_OFFSET, pPortAbility->duplex)) != RT_ERR_OK)\n                        return retVal;\n\n                    if((retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_SDS_MISC, RTL8367C_CFG_SGMII_SPD_MASK, pPortAbility->speed)) != RT_ERR_OK)\n                        return retVal;\n\n                    if((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_SDS_MISC, RTL8367C_CFG_SGMII_TXFC_OFFSET, pPortAbility->txpause)) != RT_ERR_OK)\n                        return retVal;\n\n                    if((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_SDS_MISC, RTL8367C_CFG_SGMII_RXFC_OFFSET, pPortAbility->rxpause)) != RT_ERR_OK)\n                        return retVal;\n\n                    if((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_SDS_MISC, RTL8367C_CFG_SGMII_LINK_OFFSET, pPortAbility->link)) != RT_ERR_OK)\n                        return retVal;\n\n                    /*disable force ability   ---      */\n                    if((retVal = rtl8367c_setAsicRegBit(0x137c, 12, 0)) != RT_ERR_OK)\n                        return retVal;\n                    return RT_ERR_OK;\n                }\n                else if(regValue2 == 0x12)\n                {\n#if 0\n                    /*HiSGMII*/\n                    if((retVal = rtl8367c_setAsicRegBits(0x1d95, 0x1f00, 0x1f)) != RT_ERR_OK)\n                        return retVal;\n#endif\n                    if((retVal = rtl8367c_setAsicRegBit(0x1d95, 13, 1)) != RT_ERR_OK)\n                        return retVal;\n\n                    for(i=0;i<0xfff; i++);\n\n                    /* 0 2 0  bit 8-9  nway*/\n                    if((retVal = rtl8367c_getAsicSdsReg(0, 2, 0, &reg_data)) != RT_ERR_OK)\n                        return retVal;\n                    reg_data &= 0xfffffcff;\n                    if (pPortAbility->nway)\n                        reg_data &= 0xfffffcff;\n                    else\n                        reg_data |= 0x100;\n                    if((retVal = rtl8367c_setAsicSdsReg(0,2,0, reg_data)) != RT_ERR_OK)\n                        return retVal;\n\n\n                    if((retVal = rtl8367c_setAsicRegBits(0x1d95, 0x1f00, 0x12)) != RT_ERR_OK)\n                        return retVal;\n\n                    for(i=0;i<0xfff; i++);\n\n                    if((retVal = rtl8367c_setAsicRegBit(0x1d11, 11, 0x1)) != RT_ERR_OK)\n                        return retVal;\n\n                    if((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_SDS_MISC, RTL8367C_CFG_SGMII_FDUP_OFFSET, pPortAbility->duplex)) != RT_ERR_OK)\n                        return retVal;\n\n                    if((retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_SDS_MISC, RTL8367C_CFG_SGMII_SPD_MASK, pPortAbility->speed)) != RT_ERR_OK)\n                        return retVal;\n\n                    if((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_SDS_MISC, RTL8367C_CFG_SGMII_TXFC_OFFSET, pPortAbility->txpause)) != RT_ERR_OK)\n                        return retVal;\n\n                    if((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_SDS_MISC, RTL8367C_CFG_SGMII_RXFC_OFFSET, pPortAbility->rxpause)) != RT_ERR_OK)\n                        return retVal;\n\n                    if((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_SDS_MISC, RTL8367C_CFG_SGMII_LINK_OFFSET, pPortAbility->link)) != RT_ERR_OK)\n                        return retVal;\n\n                    /*disable force ability   ---      */\n                    if((retVal = rtl8367c_setAsicRegBit(0x137c, 12, 0)) != RT_ERR_OK)\n                        return retVal;\n                    return RT_ERR_OK;\n\n                }\n            }\n            else\n            {\n                if((retVal = rtl8367c_getAsicRegBits(0x1d3d, 10, &regValue2)) != RT_ERR_OK)\n                    return retVal;\n                if (regValue2 == 0)\n                {\n                    /*ext1_force_ablty*/\n                    if((retVal = rtl8367c_setAsicRegBit(0x1311, 2, pPortAbility->duplex)) != RT_ERR_OK)\n                        return retVal;\n\n                    if((retVal = rtl8367c_setAsicRegBits(0x1311, 0x3, pPortAbility->speed)) != RT_ERR_OK)\n                        return retVal;\n\n                    if((retVal = rtl8367c_setAsicRegBit(0x1311, 4, pPortAbility->link)) != RT_ERR_OK)\n                        return retVal;\n\n                    if((retVal = rtl8367c_setAsicRegBit(0x1311, 6, pPortAbility->txpause)) != RT_ERR_OK)\n                        return retVal;\n\n                    if((retVal = rtl8367c_setAsicRegBit(0x1311, 5, pPortAbility->rxpause)) != RT_ERR_OK)\n                        return retVal;\n\n                    /*force mode for ext1*/\n                    if((retVal = rtl8367c_setAsicRegBit(0x1311, 12, pPortAbility->forcemode)) != RT_ERR_OK)\n                        return retVal;\n\n                    if (pPortAbility->link == 1)\n                    {\n                        if((retVal = rtl8367c_setAsicRegBit(0x1311, 4, 0)) != RT_ERR_OK)\n                            return retVal;\n\n                        if((retVal = rtl8367c_setAsicRegBit(0x1311, 4, 1)) != RT_ERR_OK)\n                            return retVal;\n                    }\n                    else\n                    {\n                        if((retVal = rtl8367c_setAsicRegBits(0x1311, 0x3, 2)) != RT_ERR_OK)\n                            return retVal;\n                    }\n\n                    /*disable force ability   ---      */\n                    if((retVal = rtl8367c_setAsicRegBit(0x137c, 12, 0)) != RT_ERR_OK)\n                        return retVal;\n                    return RT_ERR_OK;\n                }\n            }\n\n\n        }\n        else if (2 == id)\n        {\n\n            if((retVal = rtl8367c_getAsicRegBit(0x1d95, 0, &sgmiibit)) != RT_ERR_OK)\n                    return retVal;\n            if (sgmiibit == 1)\n            {\n                /*for 1000x/100fx/1000x_100fx, param has to bet set to serdes registers*/\n                if((retVal = rtl8367c_getAsicReg(0x1d95, &regValue)) != RT_ERR_OK)\n                    return retVal;\n                /*cfg_mac7_sel_sgmii=1 & cfg_mac7_fib =1*/\n                if((regValue & 0x3) == 0x3)\n                {\n                    if((retVal = rtl8367c_getAsicRegBits(0x1d95, 0x1f00, &regValue2)) != RT_ERR_OK)\n                        return retVal;\n\n                    if(regValue2 == 0x4)\n                    {\n                        /*1000X*/\n#if 0\n                        if((retVal = rtl8367c_setAsicRegBits(0x1d95, 0x1f00, 0x1f)) != RT_ERR_OK)\n                            return retVal;\n#endif\n                        if((retVal = rtl8367c_setAsicRegBit(0x1d95, 13, 1)) != RT_ERR_OK)\n                            return retVal;\n\n                        /* 0 4 0  bit 12  set 1,  bit15~13 = 4*/\n                        if((retVal = rtl8367c_getAsicSdsReg(0, 4, 0, &reg_data)) != RT_ERR_OK)\n                            return retVal;\n                        reg_data &= 0xFFFF0FFF;\n                        reg_data |= 0x9000;\n                        if((retVal = rtl8367c_setAsicSdsReg(0,4,0, reg_data)) != RT_ERR_OK)\n                            return retVal;\n\n                        /* 0 0 2  bit 6  set 1,  bit13 set to 0, bit12 nway_en*/\n                        if((retVal = rtl8367c_getAsicSdsReg(0, 0, 2, &reg_data)) != RT_ERR_OK)\n                            return retVal;\n                        reg_data &= 0xFFFFDFFF;\n                        reg_data |= 0x40;\n                        if(pPortAbility->forcemode)\n                            reg_data &= 0xffffefff;\n                        else\n                            reg_data |= 0x1000;\n\n                        if((retVal = rtl8367c_setAsicSdsReg(0,0,2, reg_data)) != RT_ERR_OK)\n                            return retVal;\n\n                        /* 0 4 2  bit 8  rx pause,  bit7 tx pause*/\n                        if((retVal = rtl8367c_getAsicSdsReg(0, 4, 2, &reg_data)) != RT_ERR_OK)\n                            return retVal;\n                        if (pPortAbility->txpause)\n                            reg_data |= 0x80;\n                        else\n                            reg_data &= 0xffffff7f;\n                        if (pPortAbility->rxpause)\n                            reg_data |= 0x100;\n                        else\n                            reg_data &= 0xfffffeff;\n                        if((retVal = rtl8367c_setAsicSdsReg(0,4,2, reg_data)) != RT_ERR_OK)\n                            return retVal;\n\n                         /* 0 4 0  bit 12  set 0*/\n                        if((retVal = rtl8367c_getAsicSdsReg(0, 4, 0, &reg_data)) != RT_ERR_OK)\n                            return retVal;\n                        reg_data &= 0xFFFFEFFF;\n                        if((retVal = rtl8367c_setAsicSdsReg(0,4,0, reg_data)) != RT_ERR_OK)\n                            return retVal;\n\n                        if((retVal = rtl8367c_setAsicRegBits(0x1d95, 0x1f00, 0x4)) != RT_ERR_OK)\n                            return retVal;\n\n                    }\n                    else if(regValue2 == 0x5)\n                    {\n                        /*100FX*/\n#if 0\n                        if((retVal = rtl8367c_setAsicRegBits(0x1d95, 0x1f00, 0x1f)) != RT_ERR_OK)\n                            return retVal;\n#endif\n                        if((retVal = rtl8367c_setAsicRegBit(0x1d95, 13, 1)) != RT_ERR_OK)\n                            return retVal;\n\n                        /* 0 4 0  bit 12  set 1,  bit15~13 = 5*/\n                        if((retVal = rtl8367c_getAsicSdsReg(0, 4, 0, &reg_data)) != RT_ERR_OK)\n                            return retVal;\n                        reg_data &= 0xFFFF0FFF;\n                        reg_data |= 0xB000;\n                        if((retVal = rtl8367c_setAsicSdsReg(0,4,0, reg_data)) != RT_ERR_OK)\n                            return retVal;\n\n                        /* 0 0 2  bit 6  set 0,  bit13 set to 1, bit12 0*/\n                        if((retVal = rtl8367c_getAsicSdsReg(0, 0, 2, &reg_data)) != RT_ERR_OK)\n                            return retVal;\n                        reg_data &= 0xFFFFFFBF;\n                        reg_data |= 0x2000;\n                        reg_data &= 0xffffefff;\n\n                        if((retVal = rtl8367c_setAsicSdsReg(0,0,2, reg_data)) != RT_ERR_OK)\n                            return retVal;\n\n                        /* 0 4 2  bit 8  rx pause,  bit7 tx pause*/\n                        if((retVal = rtl8367c_getAsicSdsReg(0, 4, 2, &reg_data)) != RT_ERR_OK)\n                            return retVal;\n                        if (pPortAbility->txpause)\n                            reg_data |= 0x80;\n                        else\n                            reg_data &= 0xffffff7f;\n                        if (pPortAbility->rxpause)\n                            reg_data |= 0x100;\n                        else\n                            reg_data &= 0xfffffeff;\n                        if((retVal = rtl8367c_setAsicSdsReg(0,4,2, reg_data)) != RT_ERR_OK)\n                            return retVal;\n\n                         /* 0 4 0  bit 12  set 0*/\n                        if((retVal = rtl8367c_getAsicSdsReg(0, 4, 0, &reg_data)) != RT_ERR_OK)\n                            return retVal;\n                        reg_data &= 0xFFFFEFFF;\n                        if((retVal = rtl8367c_setAsicSdsReg(0,4,0, reg_data)) != RT_ERR_OK)\n                            return retVal;\n\n                        if((retVal = rtl8367c_setAsicRegBits(0x1d95, 0x1f00, 0x5)) != RT_ERR_OK)\n                            return retVal;\n\n                    }\n                    else if(regValue2 == 0x7)\n                    {\n                        /*100FX*/\n#if 0\n                        if((retVal = rtl8367c_setAsicRegBits(0x1d95, 0x1f00, 0x1f)) != RT_ERR_OK)\n                            return retVal;\n#endif\n                        if((retVal = rtl8367c_setAsicRegBit(0x1d95, 13, 1)) != RT_ERR_OK)\n                            return retVal;\n\n                        /* 0 4 0  bit 12  set 1,  bit15~13 = 4*/\n                        if((retVal = rtl8367c_getAsicSdsReg(0, 4, 0, &reg_data)) != RT_ERR_OK)\n                            return retVal;\n                        reg_data &= 0xFFFF0FFF;\n                        reg_data |= 0x9000;\n                        if((retVal = rtl8367c_setAsicSdsReg(0,4,0, reg_data)) != RT_ERR_OK)\n                            return retVal;\n\n                        /* 0 0 2  bit 6  set 1,  bit13 set to 0, bit12 nway_en*/\n                        if((retVal = rtl8367c_getAsicSdsReg(0, 0, 2, &reg_data)) != RT_ERR_OK)\n                            return retVal;\n                        reg_data &= 0xFFFFDFFF;\n                        reg_data |= 0x40;\n                        if(pPortAbility->forcemode)\n                            reg_data &= 0xffffefff;\n                        else\n                            reg_data |= 0x1000;\n\n                        if((retVal = rtl8367c_setAsicSdsReg(0,0,2, reg_data)) != RT_ERR_OK)\n                            return retVal;\n\n                        /* 0 4 2  bit 8  rx pause,  bit7 tx pause*/\n                        if((retVal = rtl8367c_getAsicSdsReg(0, 4, 2, &reg_data)) != RT_ERR_OK)\n                            return retVal;\n                        if (pPortAbility->txpause)\n                            reg_data |= 0x80;\n                        else\n                            reg_data &= 0xffffff7f;\n                        if (pPortAbility->rxpause)\n                            reg_data |= 0x100;\n                        else\n                            reg_data &= 0xfffffeff;\n                        if((retVal = rtl8367c_setAsicSdsReg(0,4,2, reg_data)) != RT_ERR_OK)\n                            return retVal;\n\n                         /* 0 4 0  bit 12  set 0*/\n                        if((retVal = rtl8367c_getAsicSdsReg(0, 4, 0, &reg_data)) != RT_ERR_OK)\n                            return retVal;\n                        reg_data &= 0xFFFFEFFF;\n                        if((retVal = rtl8367c_setAsicSdsReg(0,4,0, reg_data)) != RT_ERR_OK)\n                            return retVal;\n\n                        /* 0 4 0  bit 12  set 1,  bit15~13 = 5*/\n                        if((retVal = rtl8367c_getAsicSdsReg(0, 4, 0, &reg_data)) != RT_ERR_OK)\n                            return retVal;\n                        reg_data &= 0xFFFF0FFF;\n                        reg_data |= 0xB000;\n                        if((retVal = rtl8367c_setAsicSdsReg(0,4,0, reg_data)) != RT_ERR_OK)\n                            return retVal;\n\n                        /* 0 0 2  bit 6  set 0,  bit13 set to 1, bit12 0*/\n                        if((retVal = rtl8367c_getAsicSdsReg(0, 0, 2, &reg_data)) != RT_ERR_OK)\n                            return retVal;\n                        reg_data &= 0xFFFFFFBF;\n                        reg_data |= 0x2000;\n                        reg_data &= 0xffffefff;\n\n                        if((retVal = rtl8367c_setAsicSdsReg(0,0,2, reg_data)) != RT_ERR_OK)\n                            return retVal;\n\n                        /* 0 4 2  bit 8  rx pause,  bit7 tx pause*/\n                        if((retVal = rtl8367c_getAsicSdsReg(0, 4, 2, &reg_data)) != RT_ERR_OK)\n                            return retVal;\n                        if (pPortAbility->txpause)\n                            reg_data |= 0x80;\n                        else\n                            reg_data  &= 0xffffff7f;\n                        if (pPortAbility->rxpause)\n                            reg_data |= 0x100;\n                        else\n                            reg_data &= 0xfffffeff;\n                        if((retVal = rtl8367c_setAsicSdsReg(0,4,2, reg_data)) != RT_ERR_OK)\n                            return retVal;\n\n                         /* 0 4 0  bit 12  set 0*/\n                        if((retVal = rtl8367c_getAsicSdsReg(0, 4, 0, &reg_data)) != RT_ERR_OK)\n                            return retVal;\n                        reg_data &= 0xFFFFEFFF;\n                        if((retVal = rtl8367c_setAsicSdsReg(0,4,0, reg_data)) != RT_ERR_OK)\n                            return retVal;\n\n                        if((retVal = rtl8367c_setAsicRegBits(0x1d95, 0x1f00, 0x7)) != RT_ERR_OK)\n                            return retVal;\n\n                    }\n\n                    if((retVal = rtl8367c_setAsicRegBit(0x137d, 12, 0)) != RT_ERR_OK)\n                        return retVal;\n                    return RT_ERR_OK;\n\n                }\n                /* new_cfg_sds_mode */\n                if((retVal = rtl8367c_getAsicRegBits(0x1d95, 0x1f00, &regValue2)) != RT_ERR_OK)\n                        return retVal;\n                if(regValue2 == 0x2)\n                {\n                    /*SGMII*/\n#if 0\n                    if((retVal = rtl8367c_setAsicRegBits(0x1d95, 0x1f00, 0x1f)) != RT_ERR_OK)\n                        return retVal;\n#endif\n                    if((retVal = rtl8367c_setAsicRegBit(0x1d95, 13, 1)) != RT_ERR_OK)\n                        return retVal;\n\n                    for(i=0;i<0xfff; i++);\n\n                    /* 0 2 0  bit 8-9  nway*/\n                    if((retVal = rtl8367c_getAsicSdsReg(0, 2, 0, &reg_data)) != RT_ERR_OK)\n                        return retVal;\n                    reg_data &= 0xfffffcff;\n                    if (pPortAbility->nway)\n                        reg_data &= 0xfffffcff;\n                    else\n                        reg_data |= 0x100;\n                    if((retVal = rtl8367c_setAsicSdsReg(0,2,0, reg_data)) != RT_ERR_OK)\n                        return retVal;\n\n                    if((retVal = rtl8367c_setAsicRegBits(0x1d95, 0x1f00, 0x2)) != RT_ERR_OK)\n                        return retVal;\n\n                    for(i=0;i<0xfff; i++);\n\n                    if((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_SDS_MISC, RTL8367C_CFG_SGMII_FDUP_OFFSET, pPortAbility->duplex)) != RT_ERR_OK)\n                        return retVal;\n\n                    if((retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_SDS_MISC, RTL8367C_CFG_SGMII_SPD_MASK, pPortAbility->speed)) != RT_ERR_OK)\n                        return retVal;\n\n                    if((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_SDS_MISC, RTL8367C_CFG_SGMII_TXFC_OFFSET, pPortAbility->txpause)) != RT_ERR_OK)\n                        return retVal;\n\n                    if((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_SDS_MISC, RTL8367C_CFG_SGMII_RXFC_OFFSET, pPortAbility->rxpause)) != RT_ERR_OK)\n                        return retVal;\n\n                    if((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_SDS_MISC, RTL8367C_CFG_SGMII_LINK_OFFSET, pPortAbility->link)) != RT_ERR_OK)\n                        return retVal;\n\n                    if((retVal = rtl8367c_setAsicRegBit(0x137d, 12, 0)) != RT_ERR_OK)\n                        return retVal;\n                    return RT_ERR_OK;\n                }\n            }\n            else\n            {\n\n                /*ext2_force_ablty*/\n                if((retVal = rtl8367c_setAsicRegBit(0x13c4, 2, pPortAbility->duplex)) != RT_ERR_OK)\n                    return retVal;\n\n                if((retVal = rtl8367c_setAsicRegBits(0x13c4, 0x3, pPortAbility->speed)) != RT_ERR_OK)\n                    return retVal;\n\n                if((retVal = rtl8367c_setAsicRegBit(0x13c4, 4, pPortAbility->link)) != RT_ERR_OK)\n                    return retVal;\n\n                if((retVal = rtl8367c_setAsicRegBit(0x13c4, 6, pPortAbility->txpause)) != RT_ERR_OK)\n                    return retVal;\n\n                if((retVal = rtl8367c_setAsicRegBit(0x13c4, 5, pPortAbility->rxpause)) != RT_ERR_OK)\n                    return retVal;\n\n                /*force mode for ext2*/\n                if((retVal = rtl8367c_setAsicRegBit(0x13c4, 12, pPortAbility->forcemode)) != RT_ERR_OK)\n                    return retVal;\n\n                if (pPortAbility->link == 1)\n                {\n                    if((retVal = rtl8367c_setAsicRegBit(0x13c4, 4, 0)) != RT_ERR_OK)\n                        return retVal;\n\n                    if((retVal = rtl8367c_setAsicRegBit(0x13c4, 4, 1)) != RT_ERR_OK)\n                        return retVal;\n                }\n                else\n                {\n                    if((retVal = rtl8367c_setAsicRegBits(0x13c4, 0x3, 2)) != RT_ERR_OK)\n                        return retVal;\n                }\n\n\n                if((retVal = rtl8367c_getAsicRegBit(0x1d3d, 10, &reg_data)) != RT_ERR_OK)\n                        return retVal;\n                if(reg_data == 1)\n                {\n                if((retVal = rtl8367c_setAsicRegBit(0x1311, 2, pPortAbility->duplex)) != RT_ERR_OK)\n                        return retVal;\n\n                    if((retVal = rtl8367c_setAsicRegBits(0x1311, 0x3, pPortAbility->speed)) != RT_ERR_OK)\n                        return retVal;\n\n                    if((retVal = rtl8367c_setAsicRegBit(0x1311, 4, pPortAbility->link)) != RT_ERR_OK)\n                        return retVal;\n\n                    if((retVal = rtl8367c_setAsicRegBit(0x1311, 6, pPortAbility->txpause)) != RT_ERR_OK)\n                        return retVal;\n\n                    if((retVal = rtl8367c_setAsicRegBit(0x1311, 5, pPortAbility->rxpause)) != RT_ERR_OK)\n                        return retVal;\n\n                    /*force mode for ext1*/\n                    if((retVal = rtl8367c_setAsicRegBit(0x1311, 12, pPortAbility->forcemode)) != RT_ERR_OK)\n                        return retVal;\n\n                    if (pPortAbility->link == 1)\n                    {\n                        if((retVal = rtl8367c_setAsicRegBit(0x1311, 4, 0)) != RT_ERR_OK)\n                            return retVal;\n\n                        if((retVal = rtl8367c_setAsicRegBit(0x1311, 4, 1)) != RT_ERR_OK)\n                            return retVal;\n                    }\n                    else\n                    {\n                        if((retVal = rtl8367c_setAsicRegBits(0x1311, 0x3, 2)) != RT_ERR_OK)\n                            return retVal;\n                    }\n                }\n\n\n            }\n\n            /*disable force ability   ---      */\n            if((retVal = rtl8367c_setAsicRegBit(0x137d, 12, 0)) != RT_ERR_OK)\n                return retVal;\n        }\n#if 0\n        if((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_SDS_MISC, RTL8367C_CFG_SGMII_FDUP_OFFSET, pPortAbility->duplex)) != RT_ERR_OK)\n            return retVal;\n\n        if((retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_SDS_MISC, RTL8367C_CFG_SGMII_SPD_MASK, pPortAbility->speed)) != RT_ERR_OK)\n            return retVal;\n\n        if((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_SDS_MISC, RTL8367C_CFG_SGMII_TXFC_OFFSET, pPortAbility->txpause)) != RT_ERR_OK)\n            return retVal;\n\n        if((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_SDS_MISC, RTL8367C_CFG_SGMII_RXFC_OFFSET, pPortAbility->rxpause)) != RT_ERR_OK)\n            return retVal;\n\n        if((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_SDS_MISC, RTL8367C_CFG_SGMII_LINK_OFFSET, pPortAbility->link)) != RT_ERR_OK)\n            return retVal;\n#endif\n    }\n\n    return RT_ERR_OK;\n}\n/* Function Name:\n *      rtl8367c_getAsicPortForceLinkExt\n * Description:\n *      Get external interface force linking configuration\n * Input:\n *      id          - external interface id (0~1)\n *      pPortAbility - port ability configuration\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_OUT_OF_RANGE - input parameter out of range\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicPortForceLinkExt(rtk_uint32 id, rtl8367c_port_ability_t *pPortAbility)\n{\n    rtk_uint32  reg_data, regValue, type;\n    rtk_uint32  sgmiiSel;\n    rtk_uint32  hsgmiiSel;\n    ret_t       retVal;\n\n    /* Invalid input parameter */\n    if(id >= RTL8367C_EXTNO)\n        return RT_ERR_OUT_OF_RANGE;\n    /*cfg_magic_id  &  get chip_id*/\n    if((retVal = rtl8367c_setAsicReg(0x13C2, 0x0249)) != RT_ERR_OK)\n        return retVal;\n\n    if((retVal = rtl8367c_getAsicReg(0x1300, &regValue)) != RT_ERR_OK)\n        return retVal;\n\n    if((retVal = rtl8367c_setAsicReg(0x13C2, 0x0000)) != RT_ERR_OK)\n        return retVal;\n\n    type = 0;\n\n    switch (regValue)\n    {\n        case 0x0276:\n        case 0x0597:\n        case 0x6367:\n            type = 1;\n            break;\n        case 0x0652:\n        case 0x6368:\n            type = 2;\n            break;\n        case 0x0801:\n        case 0x6511:\n            type = 3;\n            break;\n        default:\n            return RT_ERR_FAILED;\n    }\n\n    if (1 == type)\n    {\n        if(1 == id)\n        {\n            if((retVal = rtl8367c_getAsicRegBit(RTL8367C_REG_SDS_MISC, RTL8367C_CFG_MAC8_SEL_SGMII_OFFSET, &sgmiiSel)) != RT_ERR_OK)\n                return retVal;\n\n            if((retVal = rtl8367c_getAsicRegBit(RTL8367C_REG_SDS_MISC, RTL8367C_CFG_MAC8_SEL_HSGMII_OFFSET, &hsgmiiSel)) != RT_ERR_OK)\n                return retVal;\n\n            if( (sgmiiSel == 1) || (hsgmiiSel == 1) )\n            {\n                memset(pPortAbility, 0x00, sizeof(rtl8367c_port_ability_t));\n                pPortAbility->forcemode = 1;\n\n                if((retVal = rtl8367c_getAsicRegBit(RTL8367C_REG_SDS_MISC, RTL8367C_CFG_SGMII_FDUP_OFFSET, &reg_data)) != RT_ERR_OK)\n                    return retVal;\n\n                pPortAbility->duplex = reg_data;\n\n                if((retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_SDS_MISC, RTL8367C_CFG_SGMII_SPD_MASK, &reg_data)) != RT_ERR_OK)\n                    return retVal;\n\n                pPortAbility->speed = reg_data;\n\n                if((retVal = rtl8367c_getAsicRegBit(RTL8367C_REG_SDS_MISC, RTL8367C_CFG_SGMII_LINK_OFFSET, &reg_data)) != RT_ERR_OK)\n                    return retVal;\n\n                pPortAbility->link = reg_data;\n\n                if((retVal = rtl8367c_getAsicRegBit(RTL8367C_REG_SDS_MISC, RTL8367C_CFG_SGMII_TXFC_OFFSET, &reg_data)) != RT_ERR_OK)\n                    return retVal;\n\n                pPortAbility->txpause = reg_data;\n\n                if((retVal = rtl8367c_getAsicRegBit(RTL8367C_REG_SDS_MISC, RTL8367C_CFG_SGMII_RXFC_OFFSET, &reg_data)) != RT_ERR_OK)\n                    return retVal;\n\n                pPortAbility->rxpause = reg_data;\n\n                return RT_ERR_OK;\n            }\n        }\n\n        if(0 == id || 1 == id)\n            retVal = rtl8367c_getAsicReg(RTL8367C_REG_DIGITAL_INTERFACE0_FORCE+id, &reg_data);\n        else\n            retVal = rtl8367c_getAsicReg(RTL8367C_REG_DIGITAL_INTERFACE2_FORCE, &reg_data);\n\n        if(retVal != RT_ERR_OK)\n            return retVal;\n\n        pPortAbility->forcemode = (reg_data >> 12) & 0x0001;\n        pPortAbility->mstfault  = (reg_data >> 9) & 0x0001;\n        pPortAbility->mstmode   = (reg_data >> 8) & 0x0001;\n        pPortAbility->nway      = (reg_data >> 7) & 0x0001;\n        pPortAbility->txpause   = (reg_data >> 6) & 0x0001;\n        pPortAbility->rxpause   = (reg_data >> 5) & 0x0001;\n        pPortAbility->link      = (reg_data >> 4) & 0x0001;\n        pPortAbility->duplex    = (reg_data >> 2) & 0x0001;\n        pPortAbility->speed     = reg_data & 0x0003;\n    }\n    else if (2 == type)\n    {\n        if (id == 1)\n        {\n            if ((retVal = rtl8367c_getAsicReg(0x1311, &reg_data))!=RT_ERR_OK)\n                return retVal;\n\n            pPortAbility->forcemode = (reg_data >> 12) & 1;\n            pPortAbility->duplex = (reg_data >> 2) & 1;\n            pPortAbility->link = (reg_data >> 4) & 1;\n            pPortAbility->speed = reg_data & 3;\n            pPortAbility->rxpause = (reg_data >> 5) & 1;\n            pPortAbility->txpause = (reg_data >> 6) & 1;\n        }\n        else if (2 == id)\n        {\n            if ((retVal = rtl8367c_getAsicReg(0x13c4, &reg_data))!=RT_ERR_OK)\n                return retVal;\n\n            pPortAbility->forcemode = (reg_data >> 12) & 1;\n            pPortAbility->duplex = (reg_data >> 2) & 1;\n            pPortAbility->link = (reg_data >> 4) & 1;\n            pPortAbility->speed = reg_data & 3;\n            pPortAbility->rxpause = (reg_data >> 5) & 1;\n            pPortAbility->txpause = (reg_data >> 6) & 1;\n        }\n    }\n    else if (3 == type)\n    {\n        if (id == 1)\n        {\n            if ((retVal = rtl8367c_getAsicReg(0x1311, &reg_data))!=RT_ERR_OK)\n                return retVal;\n\n            pPortAbility->forcemode = (reg_data >> 12) & 1;\n            pPortAbility->duplex = (reg_data >> 2) & 1;\n            pPortAbility->link = (reg_data >> 4) & 1;\n            pPortAbility->speed = reg_data & 3;\n            pPortAbility->rxpause = (reg_data >> 5) & 1;\n            pPortAbility->txpause = (reg_data >> 6) & 1;\n        }\n        else if (2 == id)\n        {\n            if ((retVal = rtl8367c_getAsicReg(0x13c4, &reg_data))!=RT_ERR_OK)\n                return retVal;\n\n            pPortAbility->forcemode = (reg_data >> 12) & 1;\n            pPortAbility->duplex = (reg_data >> 2) & 1;\n            pPortAbility->link = (reg_data >> 4) & 1;\n            pPortAbility->speed = reg_data & 3;\n            pPortAbility->rxpause = (reg_data >> 5) & 1;\n            pPortAbility->txpause = (reg_data >> 6) & 1;\n        }\n    }\n    return RT_ERR_OK;\n}\n/* Function Name:\n *      rtl8367c_setAsicPortExtMode\n * Description:\n *      Set external interface mode configuration\n * Input:\n *      id      - external interface id (0~2)\n *      mode    - external interface mode\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_OUT_OF_RANGE - input parameter out of range\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicPortExtMode(rtk_uint32 id, rtk_uint32 mode)\n{\n    ret_t   retVal;\n    rtk_uint32 i, regValue, type, option,reg_data;\n    rtk_uint32 idx;\n    rtk_uint32 redData[][2] =   { {0x04D7, 0x0480}, {0xF994, 0x0481}, {0x21A2, 0x0482}, {0x6960, 0x0483}, {0x9728, 0x0484}, {0x9D85, 0x0423}, {0xD810, 0x0424}, {0x83F2, 0x002E} };\n    rtk_uint32 redDataSB[][2] = { {0x04D7, 0x0480}, {0xF994, 0x0481}, {0x31A2, 0x0482}, {0x6960, 0x0483}, {0x9728, 0x0484}, {0x9D85, 0x0423}, {0xD810, 0x0424}, {0x83F2, 0x002E} };\n    rtk_uint32 redData1[][2] =  { {0x82F1, 0x0500}, {0xF195, 0x0501}, {0x31A2, 0x0502}, {0x796C, 0x0503}, {0x9728, 0x0504}, {0x9D85, 0x0423}, {0xD810, 0x0424}, {0x0F80, 0x0001}, {0x83F2, 0x002E} };\n    rtk_uint32 redData5[][2] =  { {0x82F1, 0x0500}, {0xF195, 0x0501}, {0x31A2, 0x0502}, {0x796C, 0x0503}, {0x9728, 0x0504}, {0x9D85, 0x0423}, {0xD810, 0x0424}, {0x0F80, 0x0001}, {0x83F2, 0x002E} };\n    rtk_uint32 redData6[][2] =  { {0x82F1, 0x0500}, {0xF195, 0x0501}, {0x31A2, 0x0502}, {0x796C, 0x0503}, {0x9728, 0x0504}, {0x9D85, 0x0423}, {0xD810, 0x0424}, {0x0F80, 0x0001}, {0x83F2, 0x002E} };\n    rtk_uint32 redData8[][2] =  { {0x82F1, 0x0500}, {0xF995, 0x0501}, {0x31A2, 0x0502}, {0x796C, 0x0503}, {0x9728, 0x0504}, {0x9D85, 0x0423}, {0xD810, 0x0424}, {0x0F80, 0x0001}, {0x83F2, 0x002E} };\n    rtk_uint32 redData9[][2] =  { {0x82F1, 0x0500}, {0xF995, 0x0501}, {0x31A2, 0x0502}, {0x796C, 0x0503}, {0x9728, 0x0504}, {0x9D85, 0x0423}, {0xD810, 0x0424}, {0x0F80, 0x0001}, {0x83F2, 0x002E} };\n    rtk_uint32 redDataHB[][2] = { {0x82F0, 0x0500}, {0xF195, 0x0501}, {0x31A2, 0x0502}, {0x7960, 0x0503}, {0x9728, 0x0504}, {0x9D85, 0x0423}, {0xD810, 0x0424}, {0x0F80, 0x0001}, {0x83F2, 0x002E} };\n\n    if(id >= RTL8367C_EXTNO)\n        return RT_ERR_OUT_OF_RANGE;\n\n    if(mode >= EXT_END)\n        return RT_ERR_OUT_OF_RANGE;\n\n    /* magic number*/\n    if((retVal = rtl8367c_setAsicReg(0x13C2, 0x0249)) != RT_ERR_OK)\n        return retVal;\n    /* Chip num */\n    if((retVal = rtl8367c_getAsicReg(0x1300, &regValue)) != RT_ERR_OK)\n        return retVal;\n\n    if((retVal = rtl8367c_setAsicReg(0x13C2, 0x0000)) != RT_ERR_OK)\n        return retVal;\n\n    type = 0;\n\n    switch (regValue)\n    {\n        case 0x0276:\n        case 0x0597:\n        case 0x6367:\n            type = 1;\n            break;\n        case 0x0652:\n        case 0x6368:\n            type = 2;\n            break;\n        case 0x0801:\n        case 0x6511:\n            type = 3;\n            break;\n        default:\n            return RT_ERR_FAILED;\n    }\n\n\n    if (1==type)\n    {\n        if((mode == EXT_1000X_100FX) || (mode == EXT_1000X) || (mode == EXT_100FX))\n        {\n            if((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_REG_TO_ECO4, 5, 1)) != RT_ERR_OK)\n                return retVal;\n\n            if((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_REG_TO_ECO4, 7, 1)) != RT_ERR_OK)\n                return retVal;\n\n            if ((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_CHIP_RESET, RTL8367C_DW8051_RST_OFFSET, 1)) != RT_ERR_OK)\n                return retVal;\n\n            if ((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_MISCELLANEOUS_CONFIGURE0, RTL8367C_DW8051_EN_OFFSET, 1)) != RT_ERR_OK)\n                return retVal;\n\n            if ((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_DW8051_RDY, RTL8367C_ACS_IROM_ENABLE_OFFSET, 1)) != RT_ERR_OK)\n                return retVal;\n\n            if ((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_DW8051_RDY, RTL8367C_IROM_MSB_OFFSET, 0)) != RT_ERR_OK)\n                return retVal;\n\n            if(mode == EXT_1000X_100FX)\n            {\n                for(idx = 0; idx < FIBER2_AUTO_INIT_SIZE; idx++)\n                {\n                    if ((retVal = rtl8367c_setAsicReg(0xE000 + idx, (rtk_uint32)Fiber2_Auto[idx])) != RT_ERR_OK)\n                        return retVal;\n                }\n            }\n\n            if(mode == EXT_1000X)\n            {\n                for(idx = 0; idx < FIBER2_1G_INIT_SIZE; idx++)\n                {\n                    if ((retVal = rtl8367c_setAsicReg(0xE000 + idx, (rtk_uint32)Fiber2_1G[idx])) != RT_ERR_OK)\n                        return retVal;\n                }\n            }\n\n            if(mode == EXT_100FX)\n            {\n                for(idx = 0; idx < FIBER2_100M_INIT_SIZE; idx++)\n                {\n                    if ((retVal = rtl8367c_setAsicReg(0xE000 + idx, (rtk_uint32)Fiber2_100M[idx])) != RT_ERR_OK)\n                        return retVal;\n                }\n            }\n\n            if ((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_DW8051_RDY, RTL8367C_IROM_MSB_OFFSET, 0)) != RT_ERR_OK)\n                return retVal;\n\n            if ((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_DW8051_RDY, RTL8367C_ACS_IROM_ENABLE_OFFSET, 0)) != RT_ERR_OK)\n                return retVal;\n\n            if ((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_CHIP_RESET, RTL8367C_DW8051_RST_OFFSET, 0)) != RT_ERR_OK)\n                return retVal;\n        }\n\n        if(mode == EXT_GMII)\n        {\n            if( (retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_EXT0_RGMXF, RTL8367C_EXT0_RGTX_INV_OFFSET, 1)) != RT_ERR_OK)\n                return retVal;\n\n            if( (retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_EXT1_RGMXF, RTL8367C_EXT1_RGTX_INV_OFFSET, 1)) != RT_ERR_OK)\n                return retVal;\n\n            if( (retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_EXT_TXC_DLY, RTL8367C_EXT1_GMII_TX_DELAY_MASK, 5)) != RT_ERR_OK)\n                return retVal;\n\n            if( (retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_EXT_TXC_DLY, RTL8367C_EXT0_GMII_TX_DELAY_MASK, 6)) != RT_ERR_OK)\n                return retVal;\n        }\n\n        /* Serdes reset */\n        if( (mode == EXT_TMII_MAC) || (mode == EXT_TMII_PHY) )\n        {\n            if( (retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_BYPASS_LINE_RATE, id, 1)) != RT_ERR_OK)\n                return retVal;\n        }\n        else\n        {\n            if( (retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_BYPASS_LINE_RATE, id, 0)) != RT_ERR_OK)\n                return retVal;\n        }\n\n        if( (mode == EXT_SGMII) || (mode == EXT_HSGMII) )\n        {\n            if(id != 1)\n                return RT_ERR_PORT_ID;\n\n            if((retVal = rtl8367c_setAsicReg(0x13C0, 0x0249)) != RT_ERR_OK)\n                return retVal;\n\n            if((retVal = rtl8367c_getAsicReg(0x13C1, &option)) != RT_ERR_OK)\n                return retVal;\n\n            if((retVal = rtl8367c_setAsicReg(0x13C0, 0x0000)) != RT_ERR_OK)\n                return retVal;\n        }\n\n        if(mode == EXT_SGMII)\n        {\n            if(option == 0)\n            {\n                for(i = 0; i <= 7; i++)\n                {\n                    if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_DATA, redData[i][0])) != RT_ERR_OK)\n                        return retVal;\n\n                    if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_ADR, redData[i][1])) != RT_ERR_OK)\n                        return retVal;\n\n                    if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_CMD, 0x00C0)) != RT_ERR_OK)\n                        return retVal;\n                }\n            }\n            else\n            {\n                for(i = 0; i <= 7; i++)\n                {\n                    if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_DATA, redDataSB[i][0])) != RT_ERR_OK)\n                        return retVal;\n\n                    if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_ADR, redDataSB[i][1])) != RT_ERR_OK)\n                        return retVal;\n\n                    if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_CMD, 0x00C0)) != RT_ERR_OK)\n                        return retVal;\n                }\n            }\n        }\n\n        if(mode == EXT_HSGMII)\n        {\n            if(option == 0)\n            {\n                if( (retVal = rtl8367c_setAsicReg(0x13c2, 0x0249)) != RT_ERR_OK)\n                    return retVal;\n\n                if( (retVal = rtl8367c_getAsicReg(0x1301, &regValue)) != RT_ERR_OK)\n                    return retVal;\n\n                if( (retVal = rtl8367c_setAsicReg(0x13c2, 0x0000)) != RT_ERR_OK)\n                    return retVal;\n\n                if ( ((regValue & 0x00F0) >> 4) == 0x0001)\n                {\n                    for(i = 0; i <= 8; i++)\n                    {\n                        if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_DATA, redData1[i][0])) != RT_ERR_OK)\n                            return retVal;\n\n                        if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_ADR, redData1[i][1])) != RT_ERR_OK)\n                            return retVal;\n\n                        if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_CMD, 0x00C0)) != RT_ERR_OK)\n                            return retVal;\n                    }\n                }\n                else if ( ((regValue & 0x00F0) >> 4) == 0x0005)\n                {\n                    for(i = 0; i <= 8; i++)\n                    {\n                        if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_DATA, redData5[i][0])) != RT_ERR_OK)\n                            return retVal;\n\n                        if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_ADR, redData5[i][1])) != RT_ERR_OK)\n                            return retVal;\n\n                        if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_CMD, 0x00C0)) != RT_ERR_OK)\n                            return retVal;\n                    }\n                }\n                else if ( ((regValue & 0x00F0) >> 4) == 0x0006)\n                {\n                    for(i = 0; i <= 8; i++)\n                    {\n                        if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_DATA, redData6[i][0])) != RT_ERR_OK)\n                            return retVal;\n\n                        if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_ADR, redData6[i][1])) != RT_ERR_OK)\n                            return retVal;\n\n                        if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_CMD, 0x00C0)) != RT_ERR_OK)\n                            return retVal;\n                    }\n                }\n                else if ( ((regValue & 0x00F0) >> 4) == 0x0008)\n                {\n                    for(i = 0; i <= 8; i++)\n                    {\n                        if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_DATA, redData8[i][0])) != RT_ERR_OK)\n                            return retVal;\n\n                        if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_ADR, redData8[i][1])) != RT_ERR_OK)\n                            return retVal;\n\n                        if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_CMD, 0x00C0)) != RT_ERR_OK)\n                            return retVal;\n                    }\n                }\n                else if ( ((regValue & 0x00F0) >> 4) == 0x0009)\n                {\n                    for(i = 0; i <= 8; i++)\n                    {\n                        if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_DATA, redData9[i][0])) != RT_ERR_OK)\n                            return retVal;\n\n                        if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_ADR, redData9[i][1])) != RT_ERR_OK)\n                            return retVal;\n\n                        if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_CMD, 0x00C0)) != RT_ERR_OK)\n                            return retVal;\n                    }\n                }\n            }\n            else\n            {\n                for(i = 0; i <= 8; i++)\n                {\n                    if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_DATA, redDataHB[i][0])) != RT_ERR_OK)\n                        return retVal;\n\n                    if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_ADR, redDataHB[i][1])) != RT_ERR_OK)\n                        return retVal;\n\n                    if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_CMD, 0x00C0)) != RT_ERR_OK)\n                        return retVal;\n                }\n            }\n        }\n\n        /* Only one ext port should care SGMII setting */\n        if(id == 1)\n        {\n\n            if(mode == EXT_SGMII)\n            {\n                if( (retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_SDS_MISC, RTL8367C_CFG_MAC8_SEL_SGMII_OFFSET, 1)) != RT_ERR_OK)\n                    return retVal;\n\n                if( (retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_SDS_MISC, RTL8367C_CFG_MAC8_SEL_HSGMII_OFFSET, 0)) != RT_ERR_OK)\n                    return retVal;\n            }\n            else if(mode == EXT_HSGMII)\n            {\n                if( (retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_SDS_MISC, RTL8367C_CFG_MAC8_SEL_SGMII_OFFSET, 0)) != RT_ERR_OK)\n                    return retVal;\n\n                if( (retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_SDS_MISC, RTL8367C_CFG_MAC8_SEL_HSGMII_OFFSET, 1)) != RT_ERR_OK)\n                    return retVal;\n            }\n            else\n            {\n\n                if((mode != EXT_1000X_100FX) && (mode != EXT_1000X) && (mode != EXT_100FX))\n                {\n                    if( (retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_SDS_MISC, RTL8367C_CFG_MAC8_SEL_SGMII_OFFSET, 0)) != RT_ERR_OK)\n                        return retVal;\n\n                    if( (retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_SDS_MISC, RTL8367C_CFG_MAC8_SEL_HSGMII_OFFSET, 0)) != RT_ERR_OK)\n                        return retVal;\n                }\n            }\n        }\n\n        if(0 == id || 1 == id)\n        {\n            if((retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_DIGITAL_INTERFACE_SELECT, RTL8367C_SELECT_GMII_0_MASK << (id * RTL8367C_SELECT_GMII_1_OFFSET), mode)) != RT_ERR_OK)\n                return retVal;\n        }\n        else\n        {\n            if((retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_DIGITAL_INTERFACE_SELECT_1, RTL8367C_SELECT_GMII_2_MASK, mode)) != RT_ERR_OK)\n                return retVal;\n        }\n\n        /* Serdes not reset */\n        if( (mode == EXT_SGMII) || (mode == EXT_HSGMII) )\n        {\n            if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_DATA, 0x7106)) != RT_ERR_OK)\n                return retVal;\n\n            if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_ADR, 0x0003)) != RT_ERR_OK)\n                return retVal;\n\n            if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_CMD, 0x00C0)) != RT_ERR_OK)\n                return retVal;\n        }\n\n        if( (mode == EXT_SGMII) || (mode == EXT_HSGMII) )\n        {\n            if ((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_CHIP_RESET, RTL8367C_DW8051_RST_OFFSET, 1)) != RT_ERR_OK)\n                return retVal;\n\n            if ((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_MISCELLANEOUS_CONFIGURE0, RTL8367C_DW8051_EN_OFFSET, 1)) != RT_ERR_OK)\n                return retVal;\n\n            if ((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_DW8051_RDY, RTL8367C_ACS_IROM_ENABLE_OFFSET, 1)) != RT_ERR_OK)\n                return retVal;\n\n            if ((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_DW8051_RDY, RTL8367C_IROM_MSB_OFFSET, 0)) != RT_ERR_OK)\n                return retVal;\n\n            for(idx = 0; idx < SGMII_INIT_SIZE; idx++)\n            {\n                if ((retVal = rtl8367c_setAsicReg(0xE000 + idx, (rtk_uint32)Sgmii_Init[idx])) != RT_ERR_OK)\n                    return retVal;\n            }\n\n            if ((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_DW8051_RDY, RTL8367C_IROM_MSB_OFFSET, 0)) != RT_ERR_OK)\n                return retVal;\n\n            if ((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_DW8051_RDY, RTL8367C_ACS_IROM_ENABLE_OFFSET, 0)) != RT_ERR_OK)\n                return retVal;\n\n            if ((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_CHIP_RESET, RTL8367C_DW8051_RST_OFFSET, 0)) != RT_ERR_OK)\n                return retVal;\n        }\n    }\n    else if (2 == type)\n    {\n        /* Serdes reset */\n        if( (mode == EXT_TMII_MAC) || (mode == EXT_TMII_PHY) )\n        {\n            if( (retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_BYPASS_LINE_RATE, id+2, 1)) != RT_ERR_OK)\n                return retVal;\n        }\n        else\n        {\n            if( (retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_BYPASS_LINE_RATE, id+2, 0)) != RT_ERR_OK)\n                return retVal;\n        }\n\n        /*set MAC mode*/\n        if (id == 1)\n        {\n            if(mode == EXT_HSGMII)\n                return RT_ERR_PORT_ID;\n\n            if (mode == EXT_SGMII)\n            {\n                /*cfg port8 with MII mac mode*/\n                if ((retVal = rtl8367c_setAsicRegBits(0x1305, 0xf0, 0)) != RT_ERR_OK)\n                    return retVal;\n\n                /*enable port8 SGMII*/\n                if ((retVal = rtl8367c_setAsicRegBit(0x1d92, 14, 1)) != RT_ERR_OK)\n                    return retVal;\n            }\n            else if (mode == EXT_1000X || mode == EXT_100FX || mode == EXT_1000X_100FX)\n            {\n                /*cfg port8 with MII mac mode*/\n                if ((retVal = rtl8367c_setAsicRegBits(0x1305, 0xf0, 0)) != RT_ERR_OK)\n                    return retVal;\n\n                /*disable port8 SGMII*/\n                if ((retVal = rtl8367c_setAsicRegBit(0x1d92, 14, 0)) != RT_ERR_OK)\n                    return retVal;\n\n                /*set fiber link up*/\n                if((retVal = rtl8367c_setAsicRegBit(0x6210, 11, 0)) != RT_ERR_OK)\n                    return retVal;\n            }\n            else\n            {\n                /*cfg port8 with MII mac mode*/\n                if ((retVal = rtl8367c_setAsicRegBits(0x1305, 0xf0, mode)) != RT_ERR_OK)\n                    return retVal;\n\n                /*disable port8 SGMII*/\n                if ((retVal = rtl8367c_setAsicRegBit(0x1d92, 14, 0)) != RT_ERR_OK)\n                    return retVal;\n            }\n            /*disable SDS 1*/\n            if ((retVal = rtl8367c_setAsicRegBits(0x1d92, 0x1f00, 0x1f)) != RT_ERR_OK)\n                return retVal;\n        }\n        else if(id == 2)\n        {\n            if (mode == EXT_HSGMII)\n            {\n                if ((retVal = rtl8367c_setAsicReg(0x130, 7)) != RT_ERR_OK)\n                    return retVal;\n\n                if ((retVal = rtl8367c_setAsicReg(0x39f, 7)) != RT_ERR_OK)\n                    return retVal;\n\n                if ((retVal = rtl8367c_setAsicReg(0x3fa, 7)) != RT_ERR_OK)\n                    return retVal;\n            }\n            else\n            {\n                if ((retVal = rtl8367c_setAsicReg(0x130, 1)) != RT_ERR_OK)\n                    return retVal;\n\n                if ((retVal = rtl8367c_setAsicReg(0x39f, 1)) != RT_ERR_OK)\n                    return retVal;\n\n                if ((retVal = rtl8367c_setAsicReg(0x3fa, 4)) != RT_ERR_OK)\n                    return retVal;\n\n            }\n\n\n            if (mode == EXT_SGMII)\n            {\n                /*cfg port9 with MII mac mode*/\n                if ((retVal = rtl8367c_setAsicRegBits(0x13c3, 0xf, 0)) != RT_ERR_OK)\n                    return retVal;\n\n                /*enable port9 SGMII*/\n                if ((retVal = rtl8367c_setAsicRegBit(0x1d92, 6, 1)) != RT_ERR_OK)\n                    return retVal;\n\n                /*disable port9 HSGMII*/\n                if ((retVal = rtl8367c_setAsicRegBit(0x1d92, 7, 0)) != RT_ERR_OK)\n                    return retVal;\n            }\n            else if (mode == EXT_HSGMII)\n            {\n                /*cfg port9 with MII mac mode*/\n                if ((retVal = rtl8367c_setAsicRegBits(0x13c3, 0xf, 0)) != RT_ERR_OK)\n                    return retVal;\n\n                /*disable port9 SGMII*/\n                if ((retVal = rtl8367c_setAsicRegBit(0x1d92, 6, 0)) != RT_ERR_OK)\n                    return retVal;\n\n                /*enable port9 HSGMII*/\n                if ((retVal = rtl8367c_setAsicRegBit(0x1d92, 7, 1)) != RT_ERR_OK)\n                    return retVal;\n            }\n            else if (mode == EXT_1000X || mode == EXT_100FX || mode == EXT_1000X_100FX)\n            {\n                /*cfg port9 with MII mac mode*/\n                if ((retVal = rtl8367c_setAsicRegBits(0x13c3, 0xf, 0)) != RT_ERR_OK)\n                    return retVal;\n\n                /*disable port9 SGMII*/\n                if ((retVal = rtl8367c_setAsicRegBit(0x1d92, 6, 0)) != RT_ERR_OK)\n                    return retVal;\n\n                /*disable port9 HSGMII*/\n                if ((retVal = rtl8367c_setAsicRegBit(0x1d92, 7, 0)) != RT_ERR_OK)\n                    return retVal;\n\n                /*set fiber link up*/\n                if((retVal = rtl8367c_setAsicRegBit(0x6200, 11, 0)) != RT_ERR_OK)\n                    return retVal;\n            }\n            else\n            {\n                /*cfg port9 with MII mac mode*/\n                if ((retVal = rtl8367c_setAsicRegBits(0x13c3, 0xf, mode)) != RT_ERR_OK)\n                    return retVal;\n\n                /*disable port9 SGMII*/\n                if ((retVal = rtl8367c_setAsicRegBit(0x1d92, 6, 0)) != RT_ERR_OK)\n                    return retVal;\n\n                /*disable port9 HSGMII*/\n                if ((retVal = rtl8367c_setAsicRegBit(0x1d92, 7, 0)) != RT_ERR_OK)\n                    return retVal;\n            }\n            /*disable SDS 0*/\n            if ((retVal = rtl8367c_setAsicRegBits(0x1d92, 0x1f, 0x1f)) != RT_ERR_OK)\n                return retVal;\n        }\n\n        /*SET TO RGMII MODE*/\n        if (mode == EXT_RGMII)\n        {\n            /*disable paral led pad*/\n            if ((retVal = rtl8367c_setAsicReg(RTL8367C_REG_PARA_LED_IO_EN3, 0)) != RT_ERR_OK)\n                return retVal;\n\n            if ((retVal = rtl8367c_setAsicReg(RTL8367C_REG_PARA_LED_IO_EN1, 0)) != RT_ERR_OK)\n                return retVal;\n\n            if ((retVal = rtl8367c_setAsicReg(RTL8367C_REG_PARA_LED_IO_EN2, 0)) != RT_ERR_OK)\n                return retVal;\n\n            /*set MAC8 mode*/\n            if (id == 1)\n            {\n                /*1: RGMII1 bias work at 3.3V, 0: RGMII1 bias work at 2.5V*/\n                if ((retVal = rtl8367c_setAsicRegBit(0x1303, 9, 1)) != RT_ERR_OK)\n                    return retVal;\n\n                /*drving 1*/\n                if ((retVal = rtl8367c_setAsicRegBit(0x1303, 6, 1)) != RT_ERR_OK)\n                    return retVal;\n\n                /*drving 1*/\n                if ((retVal = rtl8367c_setAsicRegBit(0x1303, 4, 1)) != RT_ERR_OK)\n                    return retVal;\n\n                /*show rate = 0*/\n                if ((retVal = rtl8367c_setAsicRegBit(0x1303, 1, 0)) != RT_ERR_OK)\n                    return retVal;\n\n                /*EXT1 RGMII TXC delay 2ns*/\n                if ((retVal = rtl8367c_setAsicRegBit(0x1307, 3, 1)) != RT_ERR_OK)\n                    return retVal;\n\n                /*cfg_Ext1_rgtxc_dly = 0*/\n                if ((retVal = rtl8367c_setAsicRegBits(0x13f9, 0x38, 0)) != RT_ERR_OK)\n                    return retVal;\n\n                /*RXDLY = 0*/\n                if ((retVal = rtl8367c_setAsicRegBits(0x1307, 0x7, 0)) != RT_ERR_OK)\n                    return retVal;\n\n                /*cfg_rg1_dn = 4*/\n                if ((retVal = rtl8367c_setAsicRegBits(0x1304, 0x7000, 4)) != RT_ERR_OK)\n                    return retVal;\n\n                /*cfg_rg1_dp = 4*/\n                if ((retVal = rtl8367c_setAsicRegBits(0x13f9, 0x700, 4)) != RT_ERR_OK)\n                    return retVal;\n            }\n            else if (id == 2)\n            {\n                /*1: RGMII1 bias work at 3.3V, 0: RGMII1 bias work at 2.5V*/\n                if ((retVal = rtl8367c_setAsicRegBit(0x1303, 10, 1)) != RT_ERR_OK)\n                    return retVal;\n\n                /*drving 1*/\n                if ((retVal = rtl8367c_setAsicRegBit(0x13e2, 2, 1)) != RT_ERR_OK)\n                    return retVal;\n\n                /*drving 1*/\n                if ((retVal = rtl8367c_setAsicRegBit(0x13e2, 1, 1)) != RT_ERR_OK)\n                    return retVal;\n\n                /*show rate = 0*/\n                if ((retVal = rtl8367c_setAsicRegBit(0x13e2, 0, 0)) != RT_ERR_OK)\n                    return retVal;\n\n                /*EXT1 RGMII TXC delay 2ns*/\n                if ((retVal = rtl8367c_setAsicRegBit(0x13c5, 3, 1)) != RT_ERR_OK)\n                    return retVal;\n\n                /*cfg_Ext1_rgtxc_dly = 0*/\n                if ((retVal = rtl8367c_setAsicRegBits(0x13f9, 0x1c0, 0)) != RT_ERR_OK)\n                    return retVal;\n\n                /*RXDLY = 0*/\n                if ((retVal = rtl8367c_setAsicRegBits(0x13c5, 0x7, 0)) != RT_ERR_OK)\n                    return retVal;\n\n                /*cfg_rg1_dn = 4*/\n                if ((retVal = rtl8367c_setAsicRegBits(0x13e2, 0x1c0, 4)) != RT_ERR_OK)\n                    return retVal;\n\n                /*cfg_rg1_dp = 4*/\n                if ((retVal = rtl8367c_setAsicRegBits(0x13e2, 0x38, 4)) != RT_ERR_OK)\n                    return retVal;\n            }\n        }\n        else if (mode == EXT_SGMII)\n        {\n            if (id == 1)\n            {\n                /*sds 1     reg 1    page 0x21     write value  0xec91*/\n                if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_DATA, 0xec91)) != RT_ERR_OK)\n                    return retVal;\n\n                if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_ADR, (0x21<<5) | 1)) != RT_ERR_OK)\n                    return retVal;\n\n                if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_CMD, 0x00C1)) != RT_ERR_OK)\n                    return retVal;\n\n                /*sds 1     reg 5    page 0x24     write value  0x5825*/\n                if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_DATA, 0x5825)) != RT_ERR_OK)\n                    return retVal;\n\n                if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_ADR, (0x24<<5) | 5)) != RT_ERR_OK)\n                    return retVal;\n\n                if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_CMD, 0x00C1)) != RT_ERR_OK)\n                    return retVal;\n\n                if ((retVal = rtl8367c_setAsicRegBits(0x1d92, 0x1f00, 2)) != RT_ERR_OK)\n                    return retVal;\n\n                /*?????????????????*/\n\n            }\n            else if (id == 2)\n            {\n                /*sds 0     reg 0    page 0x28     write value  0x942c*/\n                if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_DATA, 0x942c)) != RT_ERR_OK)\n                    return retVal;\n\n                if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_ADR, (0x28<<5) | 0)) != RT_ERR_OK)\n                    return retVal;\n\n                if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_CMD, 0x00C0)) != RT_ERR_OK)\n                    return retVal;\n\n                /*sds 0     reg 0    page 0x24     write value  0x942c*/\n                if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_DATA, 0x942c)) != RT_ERR_OK)\n                    return retVal;\n\n                if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_ADR, (0x24<<5) | 0)) != RT_ERR_OK)\n                    return retVal;\n\n                if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_CMD, 0x00C0)) != RT_ERR_OK)\n                    return retVal;\n\n                /*sds 0     reg 5    page 0x21     write value  0x8dc3*/\n                if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_DATA, 0x8dc3)) != RT_ERR_OK)\n                    return retVal;\n\n                if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_ADR, (0x21<<5) | 5)) != RT_ERR_OK)\n                    return retVal;\n\n                if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_CMD, 0x00C0)) != RT_ERR_OK)\n                    return retVal;\n\n                if ((retVal = rtl8367c_setAsicRegBits(0x1d92, 0x1f, 2)) != RT_ERR_OK)\n                    return retVal;\n\n                /*?????????????????*/\n            }\n        }\n        else if (mode == EXT_HSGMII)\n        {\n            if (id == 2)\n            {\n                /*sds 0     reg 0    page 0x28     write value  0x942c*/\n                if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_DATA, 0x942c)) != RT_ERR_OK)\n                    return retVal;\n\n                if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_ADR, (0x28<<5) | 0)) != RT_ERR_OK)\n                    return retVal;\n\n                if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_CMD, 0x00C0)) != RT_ERR_OK)\n                    return retVal;\n\n                /*sds 0     reg 0    page 0x24     write value  0x942c*/\n                if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_DATA, 0x942c)) != RT_ERR_OK)\n                    return retVal;\n\n                if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_ADR, (0x24<<5) | 0)) != RT_ERR_OK)\n                    return retVal;\n\n                if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_CMD, 0x00C0)) != RT_ERR_OK)\n                    return retVal;\n\n                /*sds 0     reg 5    page 0x21     write value  0x8dc3*/\n                if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_DATA, 0x8dc3)) != RT_ERR_OK)\n                    return retVal;\n\n                if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_ADR, (0x21<<5) | 5)) != RT_ERR_OK)\n                    return retVal;\n\n                if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_CMD, 0x00C0)) != RT_ERR_OK)\n                    return retVal;\n\n\n                /* optimizing HISGMII performance while RGMII used & */\n                /*sds 0     reg 9     page 0x21     write value 0x3931*/\n                if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_DATA, 0x3931)) != RT_ERR_OK)\n                        return retVal;\n\n                if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_ADR, (0x21<<5)|9) ) != RT_ERR_OK)\n                        return retVal;\n\n                if( (retVal = rtl8367c_setAsicReg(RTL8367C_REG_SDS_INDACS_CMD, 0x00C0)) != RT_ERR_OK)\n                        return retVal;\n\n\n                if ((retVal = rtl8367c_setAsicRegBits(0x1d92, 0x1f, 0x12)) != RT_ERR_OK)\n                    return retVal;\n\n                /*?????????????????*/\n            }\n        }\n        else if (mode == EXT_1000X)\n        {\n            if (id == 1)\n            {\n\n                if( (retVal = rtl8367c_setAsicSdsReg(1, 1, 0x21, 0xec91)) != RT_ERR_OK)\n                    return retVal;\n                if( (retVal = rtl8367c_setAsicSdsReg(1, 5, 0x24, 0x5825)) != RT_ERR_OK)\n                    return retVal;\n                if ((retVal = rtl8367c_setAsicRegBits(0x1d92, 0x1f00, 4)) != RT_ERR_OK)\n                    return retVal;\n\n                if ((retVal = rtl8367c_setAsicRegBits(0x1d92, 0x1f00, 0x1f)) != RT_ERR_OK)\n                    return retVal;\n\n                /*patch speed change sds1 1000M*/\n                if( (retVal = rtl8367c_getAsicSdsReg(1, 4, 0, &regValue)) != RT_ERR_OK)\n                    return retVal;\n                regValue &= 0xFFFF0FFF;\n                regValue |= 0x9000;\n                if( (retVal = rtl8367c_setAsicSdsReg(1, 4, 0, regValue)) != RT_ERR_OK)\n                    return retVal;\n\n                if( (retVal = rtl8367c_getAsicSdsReg(1, 0, 2, &regValue)) != RT_ERR_OK)\n                    return retVal;\n                regValue &= 0xFFFFdFFF;\n                regValue |= 0x40;\n                if( (retVal = rtl8367c_setAsicSdsReg(1, 0, 2, regValue)) != RT_ERR_OK)\n                    return retVal;\n\n\n                if( (retVal = rtl8367c_getAsicSdsReg(1, 4, 0, &regValue)) != RT_ERR_OK)\n                    return retVal;\n                regValue &= 0xFFFFEFFF;\n                if( (retVal = rtl8367c_setAsicSdsReg(1, 4, 0, regValue)) != RT_ERR_OK)\n                    return retVal;\n\n                if ((retVal = rtl8367c_setAsicRegBits(0x1d92, 0x1f00, 4)) != RT_ERR_OK)\n                    return retVal;\n                if ((retVal = rtl8367c_setAsicRegBits(0x1d92, 0x6000, 0)) != RT_ERR_OK)\n                    return retVal;\n\n            }\n            else if (id == 2)\n            {\n                if( (retVal = rtl8367c_setAsicSdsReg(0, 0, 0x28, 0x942c)) != RT_ERR_OK)\n                    return retVal;\n                if( (retVal = rtl8367c_setAsicSdsReg(0, 0, 0x24, 0x942c)) != RT_ERR_OK)\n                    return retVal;\n                if( (retVal = rtl8367c_setAsicSdsReg(0, 5, 0x21, 0x8dc3)) != RT_ERR_OK)\n                    return retVal;\n\n                if ((retVal = rtl8367c_setAsicRegBits(0x1d92, 0x1f, 4)) != RT_ERR_OK)\n                    return retVal;\n\n                /*patch speed change sds0 1000M*/\n                if ((retVal = rtl8367c_setAsicRegBits(0x1d92, 0x1f, 0x1f)) != RT_ERR_OK)\n                    return retVal;\n\n                if( (retVal = rtl8367c_getAsicSdsReg(0, 4, 0, &regValue)) != RT_ERR_OK)\n                    return retVal;\n                regValue &= 0xFFFF0FFF;\n                regValue |= 0x9000;\n                if( (retVal = rtl8367c_setAsicSdsReg(0, 4, 0, regValue)) != RT_ERR_OK)\n                    return retVal;\n\n                if( (retVal = rtl8367c_getAsicSdsReg(0, 0, 2, &regValue)) != RT_ERR_OK)\n                    return retVal;\n                regValue &= 0xFFFFDFFF;\n                regValue |= 0x40;\n                if( (retVal = rtl8367c_setAsicSdsReg(0, 0, 2, regValue)) != RT_ERR_OK)\n                    return retVal;\n\n                if( (retVal = rtl8367c_getAsicSdsReg(0, 4, 0, &regValue)) != RT_ERR_OK)\n                    return retVal;\n                regValue &= 0xFFFFEFFF;\n                if( (retVal = rtl8367c_setAsicSdsReg(0, 4, 0, regValue)) != RT_ERR_OK)\n                    return retVal;\n\n                if ((retVal = rtl8367c_setAsicRegBits(0x1d92, 0x1f, 4)) != RT_ERR_OK)\n                    return retVal;\n                if ((retVal = rtl8367c_setAsicRegBits(0x1d92, 0xe0, 0)) != RT_ERR_OK)\n                    return retVal;\n\n            }\n        }\n        else if (mode == EXT_100FX)\n        {\n            if (id == 1)\n            {\n                if( (retVal = rtl8367c_setAsicSdsReg(1, 1, 0x21, 0xec91)) != RT_ERR_OK)\n                    return retVal;\n                if( (retVal = rtl8367c_setAsicSdsReg(1, 5, 0x24, 0x5825)) != RT_ERR_OK)\n                    return retVal;\n                if ((retVal = rtl8367c_setAsicRegBits(0x1d92, 0x1f00, 5)) != RT_ERR_OK)\n                    return retVal;\n\n                /*patch speed change sds1 100M*/\n                if ((retVal = rtl8367c_setAsicRegBits(0x1d92, 0x1f00, 0x1f)) != RT_ERR_OK)\n                    return retVal;\n                if( (retVal = rtl8367c_getAsicSdsReg(1, 4, 0, &regValue)) != RT_ERR_OK)\n                    return retVal;\n                regValue &= 0xFFFF0FFF;\n                regValue |= 0xb000;\n                if( (retVal = rtl8367c_setAsicSdsReg(1, 4, 0, regValue)) != RT_ERR_OK)\n                    return retVal;\n\n                if( (retVal = rtl8367c_getAsicSdsReg(1, 0, 2, &regValue)) != RT_ERR_OK)\n                    return retVal;\n                regValue &= 0xFFFFFFBF;\n                regValue |= 0x2000;\n                if( (retVal = rtl8367c_setAsicSdsReg(1, 0, 2, regValue)) != RT_ERR_OK)\n                    return retVal;\n#if 0\n                if( (retVal = rtl8367c_setAsicReg(0x6214, 0x1a0)) != RT_ERR_OK)\n                    return retVal;\n#endif\n                if( (retVal = rtl8367c_getAsicSdsReg(1, 4, 0, &regValue)) != RT_ERR_OK)\n                    return retVal;\n                regValue &= 0xFFFFEFFF;\n                if( (retVal = rtl8367c_setAsicSdsReg(1, 4, 0, regValue)) != RT_ERR_OK)\n                    return retVal;\n\n                if ((retVal = rtl8367c_setAsicRegBits(0x1d92, 0x1f00, 5)) != RT_ERR_OK)\n                    return retVal;\n                if ((retVal = rtl8367c_setAsicRegBits(0x1d92, 0x6000, 0)) != RT_ERR_OK)\n                    return retVal;\n            }\n            else if (id == 2)\n            {\n                if( (retVal = rtl8367c_setAsicSdsReg(0, 0, 0x28, 0x942c)) != RT_ERR_OK)\n                    return retVal;\n                if( (retVal = rtl8367c_setAsicSdsReg(0, 0, 0x24, 0x942c)) != RT_ERR_OK)\n                    return retVal;\n                if( (retVal = rtl8367c_setAsicSdsReg(0, 5, 0x21, 0x8dc3)) != RT_ERR_OK)\n                    return retVal;\n                if ((retVal = rtl8367c_setAsicRegBits(0x1d92, 0x1f, 5)) != RT_ERR_OK)\n                    return retVal;\n\n                /*patch speed change sds0 100M*/\n                if ((retVal = rtl8367c_setAsicRegBits(0x1d92, 0x1f, 0x1f)) != RT_ERR_OK)\n                    return retVal;\n\n                if( (retVal = rtl8367c_getAsicSdsReg(0, 4, 0, &regValue)) != RT_ERR_OK)\n                    return retVal;\n                regValue &= 0xFFFF0FFF;\n                regValue |= 0xb000;\n                if( (retVal = rtl8367c_setAsicSdsReg(0, 4, 0, regValue)) != RT_ERR_OK)\n                    return retVal;\n\n                if( (retVal = rtl8367c_getAsicSdsReg(0, 0, 2, &regValue)) != RT_ERR_OK)\n                    return retVal;\n                regValue &= 0xFFFFFFBF;\n                regValue |= 0x2000;\n                if( (retVal = rtl8367c_setAsicSdsReg(0, 0, 2, regValue)) != RT_ERR_OK)\n                    return retVal;\n\n                if( (retVal = rtl8367c_getAsicSdsReg(0, 4, 0, &regValue)) != RT_ERR_OK)\n                    return retVal;\n                regValue &= 0xFFFFEFFF;\n                if( (retVal = rtl8367c_setAsicSdsReg(0, 4, 0, regValue)) != RT_ERR_OK)\n                    return retVal;\n\n                if ((retVal = rtl8367c_setAsicRegBits(0x1d92, 0x1f, 5)) != RT_ERR_OK)\n                    return retVal;\n                if ((retVal = rtl8367c_setAsicRegBits(0x1d92, 0xe0, 0)) != RT_ERR_OK)\n                    return retVal;\n            }\n        }\n        else if (mode == EXT_1000X_100FX)\n        {\n            if (id == 1)\n            {\n                if( (retVal = rtl8367c_setAsicSdsReg(1, 1, 0x21, 0xec91)) != RT_ERR_OK)\n                    return retVal;\n                if( (retVal = rtl8367c_setAsicSdsReg(1, 5, 0x24, 0x5825)) != RT_ERR_OK)\n                    return retVal;\n                if( (retVal = rtl8367c_setAsicSdsReg(1, 13, 0, 0x4616)) != RT_ERR_OK)\n                    return retVal;\n                if( (retVal = rtl8367c_setAsicSdsReg(1, 1, 0, 0xf20)) != RT_ERR_OK)\n                    return retVal;\n                if ((retVal = rtl8367c_setAsicRegBits(0x1d92, 0x1f00, 7)) != RT_ERR_OK)\n                    return retVal;\n            }\n            else if (id == 2)\n            {\n                if( (retVal = rtl8367c_setAsicSdsReg(0, 0, 0x28, 0x942c)) != RT_ERR_OK)\n                    return retVal;\n                if( (retVal = rtl8367c_setAsicSdsReg(0, 0, 0x24, 0x942c)) != RT_ERR_OK)\n                    return retVal;\n                if( (retVal = rtl8367c_setAsicSdsReg(0, 5, 0x21, 0x8dc3)) != RT_ERR_OK)\n                    return retVal;\n                if( (retVal = rtl8367c_setAsicSdsReg(0, 13, 0, 0x4616)) != RT_ERR_OK)\n                    return retVal;\n                if( (retVal = rtl8367c_setAsicSdsReg(0, 1, 0, 0xf20)) != RT_ERR_OK)\n                    return retVal;\n                if ((retVal = rtl8367c_setAsicRegBits(0x1d92, 0x1f, 7)) != RT_ERR_OK)\n                    return retVal;\n            }\n        }\n\n    }\n    else if (3 == type)\n    {\n\n        /*restore patch, by designer. patch Tx FIFO issue, when not HSGMII 2.5G mode\n         #sds0, page 1, reg 1, bit4=0*/\n        if( (retVal = rtl8367c_getAsicSdsReg(0, 1, 1, &regValue)) != RT_ERR_OK)\n            return retVal;\n        regValue &= 0xFFFFFFEF;\n        if( (retVal = rtl8367c_setAsicSdsReg(0, 1, 1, regValue)) != RT_ERR_OK)\n            return retVal;\n\n        /*set for mac 6*/\n        if (1 == id)\n        {\n            /*force port6 linkdown*/\n            if ((retVal = rtl8367c_setAsicReg(0x137c, 0x1000)) != RT_ERR_OK)\n                    return retVal;\n\n            if ((retVal = rtl8367c_getAsicRegBit(0x1d9d, 6, &reg_data)) != RT_ERR_OK)\n                    return retVal;\n            while(reg_data == 0)\n            {\n                if ((retVal = rtl8367c_getAsicRegBit(0x1d9d, 6, &reg_data)) != RT_ERR_OK)\n                    return retVal;\n            }\n\n            if (mode == EXT_SGMII)\n            {\n                /* disable mac6 mode_ext1  mode*/\n                if ((retVal = rtl8367c_getAsicRegBit(0x1d3d, 10, &reg_data)) != RT_ERR_OK)\n                    return retVal;\n                if(reg_data == 0)\n                {\n                    if ((retVal = rtl8367c_setAsicRegBits(0x1305, 0xf0, 0)) != RT_ERR_OK)\n                        return retVal;\n                }\n                /*cfg_bypass_line_rate[1]=0*/\n                if ((retVal = rtl8367c_setAsicRegBit(0x3f7, 1, 0)) != RT_ERR_OK)\n                    return retVal;\n\n\n\n                /*bit5: cfg_mac6_fib=0    &   bit7: cfg_mac6_fib2=0*/\n                if ((retVal = rtl8367c_setAsicRegBit(0x1d41, 5, 0)) != RT_ERR_OK)\n                    return retVal;\n                if ((retVal = rtl8367c_setAsicRegBit(0x1d41, 7, 0)) != RT_ERR_OK)\n                    return retVal;\n\n                /*cfg_mac7_fib=0*/\n                if ((retVal = rtl8367c_setAsicRegBit(0x1d95, 1, 0)) != RT_ERR_OK)\n                    return retVal;\n\n                /*cfg_mac7_sel_sgmii= 0: MAC7 is not SGMII mode*/\n                if ((retVal = rtl8367c_setAsicRegBit(0x1d95, 0, 0)) != RT_ERR_OK)\n                    return retVal;\n\n                /*#cfg_sgmii_link=0*/\n                if ((retVal = rtl8367c_setAsicRegBit(0x1d11, 9, 0)) != RT_ERR_OK)\n                    return retVal;\n\n                /*cfg_mac6_sel_hsgmii=0*/\n                if ((retVal = rtl8367c_setAsicRegBit(0x1d11, 11, 0)) != RT_ERR_OK)\n                    return retVal;\n\n\n                /*bit13: cfg_sds_mode_sel_new=1 :Enable new sds mode config method*/\n                if ((retVal = rtl8367c_setAsicRegBit(0x1d95, 13, 1)) != RT_ERR_OK)\n                    return retVal;\n\n                /*  bit[12:8]: Only valid when cfg_sds_mode_sel_new=1\n                    new_cfg_sds_mode=0x1F (reset mode) */\n                if ((retVal = rtl8367c_setAsicRegBits(0x1d95, 0x1f00, 0x1f)) != RT_ERR_OK)\n                    return retVal;\n\n                /*cfg_mac6_sel_sgmii= 1*/\n                if ((retVal = rtl8367c_setAsicRegBit(0x1d11, 6, 1)) != RT_ERR_OK)\n                    return retVal;\n\n                /* bit[12:8]: Only valid when cfg_sds_mode_sel_new=1\n                   new_cfg_sds_mode=0x12  */\n                if ((retVal = rtl8367c_setAsicRegBits(0x1d95, 0x1f00, 0x2)) != RT_ERR_OK)\n                    return retVal;\n\n                /* MAC link source*/\n                if ((retVal = rtl8367c_setAsicRegBit(0x1d95, 2, 0)) != RT_ERR_OK)\n                    return retVal;\n\n\n            }\n            else if (mode == EXT_HSGMII)\n            {\n\n                /*restore patch, by designer. patch Tx FIFO issue, when  HSGMII 2.5G mode\n                 #sds0, page 1, reg 1, bit4=1*/\n                if( (retVal = rtl8367c_getAsicSdsReg(0, 1, 1, &regValue)) != RT_ERR_OK)\n                    return retVal;\n                regValue |= 0x10;\n                if( (retVal = rtl8367c_setAsicSdsReg(0, 1, 1, regValue)) != RT_ERR_OK)\n                    return retVal;\n\n                 /* mode_ext1 = disable*/\n                /* disable mac6 mode_ext1  mode*/\n                if ((retVal = rtl8367c_getAsicRegBit(0x1d3d, 10, &reg_data)) != RT_ERR_OK)\n                    return retVal;\n                if(reg_data == 0)\n                {\n                    if ((retVal = rtl8367c_setAsicRegBits(0x1305, 0xf0, 0)) != RT_ERR_OK)\n                        return retVal;\n                }\n\n                if ((retVal = rtl8367c_setAsicRegBit(0x3f7, 1, 0)) != RT_ERR_OK)\n                    return retVal;\n\n                /*bit5: cfg_mac6_fib=0   &   bit7: cfg_mac6_fib2=0*/\n                if ((retVal = rtl8367c_setAsicRegBit(0x1d41, 5, 0)) != RT_ERR_OK)\n                    return retVal;\n                if ((retVal = rtl8367c_setAsicRegBit(0x1d41, 7, 0)) != RT_ERR_OK)\n                    return retVal;\n\n                /*cfg_mac7_fib=0*/\n                if ((retVal = rtl8367c_setAsicRegBit(0x1d95, 1, 0)) != RT_ERR_OK)\n                    return retVal;\n\n                /*cfg_mac7_sel_sgmii= 0*/\n                if ((retVal = rtl8367c_setAsicRegBit(0x1d95, 0, 0)) != RT_ERR_OK)\n                    return retVal;\n\n                /*cfg_mac6_sel_sgmii=0*/\n                if ((retVal = rtl8367c_setAsicRegBit(0x1d11, 9, 0)) != RT_ERR_OK)\n                    return retVal;\n\n                /*cfg_mac6_sel_hsgmii=1*/\n                if ((retVal = rtl8367c_setAsicRegBit(0x1d11, 11, 1)) != RT_ERR_OK)\n                    return retVal;\n\n                /*cfg_mac6_sel_sgmii= 0*/\n                if ((retVal = rtl8367c_setAsicRegBit(0x1d11, 6, 0)) != RT_ERR_OK)\n                    return retVal;\n\n                if ((retVal = rtl8367c_setAsicReg(0xd0,7)) != RT_ERR_OK)\n                    return retVal;\n                if ((retVal = rtl8367c_setAsicReg(0x399, 7)) != RT_ERR_OK)\n                    return retVal;\n                if ((retVal = rtl8367c_setAsicReg(0x3fa, 7)) != RT_ERR_OK)\n                    return retVal;\n\n                /*bit13: cfg_sds_mode_sel_new=1 :Enable new sds mode config method*/\n                if ((retVal = rtl8367c_setAsicRegBit(0x1d95, 13, 1)) != RT_ERR_OK)\n                    return retVal;\n                /* bit[12:8]: Only valid when cfg_sds_mode_sel_new=1\n                   new_cfg_sds_mode=0x12  */\n                if ((retVal = rtl8367c_setAsicRegBits(0x1d95, 0x1f00, 0x12)) != RT_ERR_OK)\n                    return retVal;\n                /*\n                1: MAC link = SGMII SerDes link\n                0: MAC link = SGMII config link cfg_sgmii_link\n                */\n                if ((retVal = rtl8367c_setAsicRegBit(0x1d95, 2, 0)) != RT_ERR_OK)\n                    return retVal;\n\n            }\n            else if(mode == EXT_1000X)\n            {\n                /* 0 2 0  bit 8~9  set 0, force n-way*/\n                if((retVal = rtl8367c_getAsicSdsReg(0, 2, 0, &reg_data)) != RT_ERR_OK)\n                    return retVal;\n                reg_data &= 0xFFFFFCFF;\n                if((retVal = rtl8367c_setAsicSdsReg(0,2,0, reg_data)) != RT_ERR_OK)\n                        return retVal;\n\n                /* disable mac6 mode_ext1  mode*/\n                if ((retVal = rtl8367c_getAsicRegBit(0x1d3d, 10, &reg_data)) != RT_ERR_OK)\n                    return retVal;\n                if(reg_data == 0)\n                {\n                    if ((retVal = rtl8367c_setAsicRegBits(0x1305, 0xf0, 0)) != RT_ERR_OK)\n                        return retVal;\n                }\n\n                if ((retVal = rtl8367c_setAsicRegBit(0x3f7, 1, 0)) != RT_ERR_OK)\n                    return retVal;\n\n                if ((retVal = rtl8367c_setAsicReg(0x1d11, 0x1500)) != RT_ERR_OK)\n                    return retVal;\n\n                /*bit13: cfg_sds_mode_sel_new=1 :Enable new sds mode config method\n                  bit[1:0]:cfg_mac7_fib= 0  &  cfg_mac7_sel_sgmii=0\n                */\n                if ((retVal = rtl8367c_setAsicRegBits(0x1d95, 0x1f00, 0x1f)) != RT_ERR_OK)\n                    return retVal;\n                if ((retVal = rtl8367c_setAsicRegBit(0x1d95, 13, 1)) != RT_ERR_OK)\n                    return retVal;\n                if ((retVal = rtl8367c_setAsicRegBits(0x1d95, 3, 0)) != RT_ERR_OK)\n                    return retVal;\n\n                /* bit0 :UTP/Fiber auto detect function enable or not, cfg_dis_det=1:disable\n                   bit3:Force UTP/Fiber auto detect function enable or not, cfg_force_auto-detect=1 */\n                if ((retVal = rtl8367c_setAsicReg(0x13eb, 0x15bb)) != RT_ERR_OK)\n                    return retVal;\n\n                /*bit3:  Serdes force mode:cfg_sds_frc_mode=1\n                  bit[2:0]: Serdes chip mode, cfg_sds_mode=3b'100 (force sds FIB1G mode) */\n                if ((retVal = rtl8367c_setAsicReg(0x13e7, 0xc)) != RT_ERR_OK)\n                    return retVal;\n\n\n                /*bit5: cfg_mac6_fib=1 & bit7: cfg_mac6_fib2=1*/\n                if ((retVal = rtl8367c_setAsicRegBit(0x1d41, 5, 1)) != RT_ERR_OK)\n                    return retVal;\n                if ((retVal = rtl8367c_setAsicRegBit(0x1d41, 7, 1)) != RT_ERR_OK)\n                    return retVal;\n\n                /*cfg_mac6_sel_hsgmii=0*/\n                if ((retVal = rtl8367c_setAsicRegBit(0x1d11, 11, 0)) != RT_ERR_OK)\n                    return retVal;\n\n                /*cfg_mac6_sel_sgmii= 1*/\n                if ((retVal = rtl8367c_setAsicRegBit(0x1d11, 6, 1)) != RT_ERR_OK)\n                    return retVal;\n\n                /* bit[12:8]: Only valid when cfg_sds_mode_sel_new=1\n                   new_cfg_sds_mode=0x4  */\n                if ((retVal = rtl8367c_setAsicRegBits(0x1d95, 0x1f00, 0x4)) != RT_ERR_OK)\n                    return retVal;\n            }\n            else if(mode == EXT_100FX)\n            {\n                /* 0 2 0  bit 8~9  set 0, force n-way*/\n                if((retVal = rtl8367c_getAsicSdsReg(0, 2, 0, &reg_data)) != RT_ERR_OK)\n                    return retVal;\n                reg_data &= 0xFFFFFCFF;\n                if((retVal = rtl8367c_setAsicSdsReg(0,2,0, reg_data)) != RT_ERR_OK)\n                        return retVal;\n\n                /* disable mac6 mode_ext1  mode*/\n                if ((retVal = rtl8367c_getAsicRegBit(0x1d3d, 10, &reg_data)) != RT_ERR_OK)\n                    return retVal;\n                if(reg_data == 0)\n                {\n                    if ((retVal = rtl8367c_setAsicRegBits(0x1305, 0xf0, 0)) != RT_ERR_OK)\n                        return retVal;\n                }\n\n                if ((retVal = rtl8367c_setAsicRegBit(0x3f7, 1, 0)) != RT_ERR_OK)\n                    return retVal;\n\n                if ((retVal = rtl8367c_setAsicReg(0x1d11, 0x1500)) != RT_ERR_OK)\n                    return retVal;\n\n                /*bit13: cfg_sds_mode_sel_new=1 :Enable new sds mode config method\n                  bit[1:0]:cfg_mac7_fib= 0  &  cfg_mac7_sel_sgmii=0\n                */\n                if ((retVal = rtl8367c_setAsicRegBits(0x1d95, 0x1f00, 0x1f)) != RT_ERR_OK)\n                    return retVal;\n                if ((retVal = rtl8367c_setAsicRegBit(0x1d95, 13, 1)) != RT_ERR_OK)\n                    return retVal;\n                if ((retVal = rtl8367c_setAsicRegBits(0x1d95, 3, 0)) != RT_ERR_OK)\n                    return retVal;\n\n                /* bit0 :UTP/Fiber auto detect function enable or not, cfg_dis_det=1:disable\n                   bit3:Force UTP/Fiber auto detect function enable or not, cfg_force_auto-detect=1 */\n                if ((retVal = rtl8367c_setAsicReg(0x13eb, 0x15bb)) != RT_ERR_OK)\n                    return retVal;\n\n                /*!!!!! cfg_sds_frc_mode=1 &  cfg_sds_mode=3b'101 (force sds fib100M mode)*/\n                if ((retVal = rtl8367c_setAsicReg(0x13e7, 0xc)) != RT_ERR_OK)\n                    return retVal;\n\n\n                /*bit5: cfg_mac6_fib=1 & bit7: cfg_mac6_fib2=1*/\n                if ((retVal = rtl8367c_setAsicRegBit(0x1d41, 5, 1)) != RT_ERR_OK)\n                    return retVal;\n                if ((retVal = rtl8367c_setAsicRegBit(0x1d41, 7, 1)) != RT_ERR_OK)\n                    return retVal;\n\n                /*cfg_mac6_sel_hsgmii=0*/\n                if ((retVal = rtl8367c_setAsicRegBit(0x1d11, 11, 0)) != RT_ERR_OK)\n                    return retVal;\n\n                /*cfg_mac6_sel_sgmii= 1*/\n                if ((retVal = rtl8367c_setAsicRegBit(0x1d11, 6, 1)) != RT_ERR_OK)\n                    return retVal;\n\n                /*  bit[12:8]: Only valid when cfg_sds_mode_sel_new=1\n                    new_cfg_sds_mode=0x5 */\n                if ((retVal = rtl8367c_setAsicRegBits(0x1d95, 0x1f00, 0x5)) != RT_ERR_OK)\n                    return retVal;\n            }\n            else if(mode == EXT_1000X_100FX)\n            {\n                /* 0 2 0  bit 8~9  set 0, force n-way*/\n                if((retVal = rtl8367c_getAsicSdsReg(0, 2, 0, &reg_data)) != RT_ERR_OK)\n                    return retVal;\n                reg_data &= 0xFFFFFCFF;\n                if((retVal = rtl8367c_setAsicSdsReg(0,2,0, reg_data)) != RT_ERR_OK)\n                        return retVal;\n\n                /* disable mac6 mode_ext1  mode*/\n                if ((retVal = rtl8367c_getAsicRegBit(0x1d3d, 10, &reg_data)) != RT_ERR_OK)\n                    return retVal;\n                if(reg_data == 0)\n                {\n                    if ((retVal = rtl8367c_setAsicRegBits(0x1305, 0xf0, 0)) != RT_ERR_OK)\n                        return retVal;\n                }\n\n                if ((retVal = rtl8367c_setAsicRegBit(0x3f7, 1, 0)) != RT_ERR_OK)\n                    return retVal;\n\n                if ((retVal = rtl8367c_setAsicReg(0x1d11, 0x1500)) != RT_ERR_OK)\n                    return retVal;\n\n                /*bit13: cfg_sds_mode_sel_new=1 :Enable new sds mode config method\n                  bit[1:0]:cfg_mac7_fib= 0  &  cfg_mac7_sel_sgmii=0\n                */\n                if ((retVal = rtl8367c_setAsicRegBits(0x1d95, 0x1f00, 0x1f)) != RT_ERR_OK)\n                    return retVal;\n                if ((retVal = rtl8367c_setAsicRegBit(0x1d95, 13, 0)) != RT_ERR_OK)\n                    return retVal;\n                if ((retVal = rtl8367c_setAsicRegBits(0x1d95, 3, 0)) != RT_ERR_OK)\n                    return retVal;\n\n                /* bit0 :UTP/Fiber auto detect function enable or not, cfg_dis_det=1:disable\n                   bit3:Force UTP/Fiber auto detect function enable or not, cfg_force_auto-detect=1 */\n                if ((retVal = rtl8367c_setAsicReg(0x13eb, 0x15bb)) != RT_ERR_OK)\n                    return retVal;\n\n                /*!!!!!! cfg_sds_frc_mode=1 &  cfg_sds_mode=3'b111: Fib1G/Fib100M auto detect */\n                if ((retVal = rtl8367c_setAsicReg(0x13e7, 0xc)) != RT_ERR_OK)\n                    return retVal;\n\n\n                /*bit5: cfg_mac6_fib=1 & bit7: cfg_mac6_fib2=1*/\n                if ((retVal = rtl8367c_setAsicRegBit(0x1d41, 5, 1)) != RT_ERR_OK)\n                    return retVal;\n                if ((retVal = rtl8367c_setAsicRegBit(0x1d41, 7, 1)) != RT_ERR_OK)\n                    return retVal;\n\n                /*cfg_mac6_sel_hsgmii=0*/\n                if ((retVal = rtl8367c_setAsicRegBit(0x1d11, 11, 0)) != RT_ERR_OK)\n                    return retVal;\n\n                /*cfg_mac6_sel_sgmii= 1*/\n                if ((retVal = rtl8367c_setAsicRegBit(0x1d11, 6, 1)) != RT_ERR_OK)\n                    return retVal;\n\n                /*  bit[12:8]: Only valid when cfg_sds_mode_sel_new=1\n                    new_cfg_sds_mode=0x7 */\n                if ((retVal = rtl8367c_setAsicRegBits(0x1d95, 0x1f00, 0x7)) != RT_ERR_OK)\n                    return retVal;\n            }\n            else if(mode < EXT_SGMII)\n            {\n                if ((retVal = rtl8367c_setAsicRegBit(0x1d3d, 10, 0)) != RT_ERR_OK)\n                    return retVal;\n\n                if ((retVal = rtl8367c_setAsicRegBit(0x3f7, 1, 0)) != RT_ERR_OK)\n                    return retVal;\n\n                /* keep default setting, disable mac6 sel SerDes mode,*/\n                if ((retVal = rtl8367c_setAsicRegBit(0x1d11, 11, 0)) != RT_ERR_OK)\n                    return retVal;\n                if ((retVal = rtl8367c_setAsicRegBit(0x1d11, 6, 0)) != RT_ERR_OK)\n                    return retVal;\n\n                /*bit5: cfg_mac6_fib=0       &        bit7: cfg_mac6_fib2=0*/\n                if ((retVal = rtl8367c_setAsicRegBit(0x1d41, 5, 0)) != RT_ERR_OK)\n                    return retVal;\n                if ((retVal = rtl8367c_setAsicRegBit(0x1d41, 7, 0)) != RT_ERR_OK)\n                    return retVal;\n\n                if (mode < EXT_GMII)\n                {\n                    /* set mac6 mode*/\n                    if ((retVal = rtl8367c_setAsicRegBits(0x1305, 0xf0, mode)) != RT_ERR_OK)\n                        return retVal;\n                }\n                else if(mode == EXT_RMII_MAC)\n                {\n                    /*!!!!!!*/\n                    if ((retVal = rtl8367c_setAsicRegBits(0x1305, 0xf0, 7)) != RT_ERR_OK)\n                        return retVal;\n                }\n                else if(mode == EXT_RMII_PHY)\n                {\n                    if ((retVal = rtl8367c_setAsicRegBits(0x1305, 0xf0, 8)) != RT_ERR_OK)\n                        return retVal;\n                }\n\n                if ((mode == EXT_TMII_MAC) || (mode == EXT_TMII_PHY))\n                {\n                    if ((retVal = rtl8367c_setAsicRegBit(0x3f7, 1, 1)) != RT_ERR_OK)\n                        return retVal;\n                }\n            }\n\n        }\n        else if (2 == id)\n        {\n\n            /*force port7 linkdown*/\n            if ((retVal = rtl8367c_setAsicReg(0x137d, 0x1000)) != RT_ERR_OK)\n                    return retVal;\n\n            if ((retVal = rtl8367c_getAsicRegBit(0x1d9d, 7, &reg_data)) != RT_ERR_OK)\n                    return retVal;\n            while(reg_data == 0)\n            {\n                if ((retVal = rtl8367c_getAsicRegBit(0x1d9d, 7, &reg_data)) != RT_ERR_OK)\n                    return retVal;\n            }\n\n            if (mode == EXT_SGMII)\n            {\n                /*disable mac7 sel ext2 xMII mode*/\n                if ((retVal = rtl8367c_setAsicRegBits(0x13c3, 0xf,0)) != RT_ERR_OK)\n                    return retVal;\n\n                /*restore ext2 ability*/\n                if ((retVal = rtl8367c_setAsicReg(0x13c4, 0)) != RT_ERR_OK)\n                    return retVal;\n                /*  disable mac7  mode_ext2  */\n                if ((retVal = rtl8367c_setAsicRegBit(0x3f7, 2, 0)) != RT_ERR_OK)\n                    return retVal;\n\n                /*bit5: cfg_mac6_fib=0 & bit7: cfg_mac6_fib2=0*/\n                if ((retVal = rtl8367c_setAsicRegBit(0x1d41, 5, 0)) != RT_ERR_OK)\n                    return retVal;\n                if ((retVal = rtl8367c_setAsicRegBit(0x1d41, 7, 0)) != RT_ERR_OK)\n                    return retVal;\n\n                /*\n                   bit0:cfg_mac7_sel_sgmii=0,MAC7 is not SGMII mode\n                   bit1:cfg_mac7_fib= 0  */\n                if ((retVal = rtl8367c_setAsicRegBits(0x1d95, 3, 0)) != RT_ERR_OK)\n                    return retVal;\n\n                /*cfg_mac6_sel_hsgmii=0*/\n                if ((retVal = rtl8367c_setAsicRegBit(0x1d11, 11, 0)) != RT_ERR_OK)\n                    return retVal;\n\n                /*cfg_mac6_sel_sgmii= 1*/\n                if ((retVal = rtl8367c_setAsicRegBit(0x1d11, 6, 0)) != RT_ERR_OK)\n                    return retVal;\n\n                /*Enable new sds mode config method, cfg_sds_mode_sel_new=1*/\n                if ((retVal = rtl8367c_setAsicRegBit(0x1d95, 13, 1)) != RT_ERR_OK)\n                    return retVal;\n\n                /*  bit[12:8]: Only valid when cfg_sds_mode_sel_new=1\n                    new_cfg_sds_mode=0x1F (reset mode) */\n                if ((retVal = rtl8367c_setAsicRegBits(0x1d95, 0x1f00, 0x1f)) != RT_ERR_OK)\n                    return retVal;\n\n                /*cfg_mac7_sel_sgmii= 1*/\n                if ((retVal = rtl8367c_setAsicRegBit(0x1d95, 0, 1)) != RT_ERR_OK)\n                    return retVal;\n\n                /*  bit[12:8]: Only valid when cfg_sds_mode_sel_new=1\n                    new_cfg_sds_mode=0x2 (SGMII mode)*/\n                if ((retVal = rtl8367c_setAsicRegBits(0x1d95, 0x1f00, 0x2)) != RT_ERR_OK)\n                    return retVal;\n\n                /*select MAC link source when port6/7 be set sgmii mode cfg_sgmii_link*/\n                if ((retVal = rtl8367c_setAsicRegBit(0x1d95, 2, 0)) != RT_ERR_OK)\n                    return retVal;\n            }\n            else if (mode == EXT_1000X)\n            {\n                /*  disable mac7 MII/TMM/RMII/GMII/RGMII mode, mode_ext2 = disable */\n                if ((retVal = rtl8367c_setAsicRegBits(0x13c3, 0xf, 0)) != RT_ERR_OK)\n                    return retVal;\n\n                /*restore ext2 ability*/\n                if ((retVal = rtl8367c_setAsicReg(0x13c4, 0)) != RT_ERR_OK)\n                    return retVal;\n\n                /* 0 2 0  bit 8~9  set 0, force n-way*/\n                if((retVal = rtl8367c_getAsicSdsReg(0, 2, 0, &reg_data)) != RT_ERR_OK)\n                    return retVal;\n                reg_data &= 0xFFFFFCFF;\n                if((retVal = rtl8367c_setAsicSdsReg(0,2,0, reg_data)) != RT_ERR_OK)\n                        return retVal;\n\n                /*restore ext2 ability*/\n                if ((retVal = rtl8367c_setAsicRegBit(0x3f7, 2, 0)) != RT_ERR_OK)\n                    return retVal;\n\n                /*  keep default setting, disable mac6 sel serdes*/\n                if ((retVal = rtl8367c_setAsicReg(0x1d11, 0x1500)) != RT_ERR_OK)\n                    return retVal;\n\n                /*Enable new sds mode config method, cfg_sds_mode_sel_new=1*/\n                if ((retVal = rtl8367c_setAsicRegBit(0x1d95, 13, 1)) != RT_ERR_OK)\n                    return retVal;\n\n                /*  bit[12:8]: Only valid when cfg_sds_mode_sel_new=1\n                    new_cfg_sds_mode=0x1F (reset mode) */\n                if ((retVal = rtl8367c_setAsicRegBits(0x1d95, 0x1f00, 0x1f)) != RT_ERR_OK)\n                    return retVal;\n\n                /*bit5: cfg_mac6_fib=0         &        bit7: cfg_mac6_fib2=0*/\n                if ((retVal = rtl8367c_setAsicRegBit(0x1d41, 5, 0)) != RT_ERR_OK)\n                    return retVal;\n                if ((retVal = rtl8367c_setAsicRegBit(0x1d41, 7, 0)) != RT_ERR_OK)\n                    return retVal;\n\n                /*cfg_mac7_sel_sgmii= 1 & cfg_mac7_fib=1*/\n                if ((retVal = rtl8367c_setAsicRegBits(0x1d95, 3, 3)) != RT_ERR_OK)\n                    return retVal;\n\n                /*new_cfg_sds_mode=0x4 (FIB1000 mode)*/\n                if ((retVal = rtl8367c_setAsicRegBits(0x1d95, 0x1f00, 0x4)) != RT_ERR_OK)\n                    return retVal;\n\n            }\n            else if (mode == EXT_100FX)\n            {\n                /*  disable mac7 MII/TMM/RMII/GMII/RGMII mode, mode_ext2 = disable  */\n                if ((retVal = rtl8367c_setAsicRegBits(0x13c3, 0xf, 0)) != RT_ERR_OK)\n                    return retVal;\n\n                /*restore ext2 ability*/\n                if ((retVal = rtl8367c_setAsicReg(0x13c4, 0)) != RT_ERR_OK)\n                    return retVal;\n\n                /* 0 2 0  bit 8~9  set 0, force n-way*/\n                if((retVal = rtl8367c_getAsicSdsReg(0, 2, 0, &reg_data)) != RT_ERR_OK)\n                    return retVal;\n                reg_data &= 0xFFFFFCFF;\n                if((retVal = rtl8367c_setAsicSdsReg(0,2,0, reg_data)) != RT_ERR_OK)\n                        return retVal;\n\n                /*restore ext2 ability*/\n                if ((retVal = rtl8367c_setAsicRegBit(0x3f7, 2, 0)) != RT_ERR_OK)\n                    return retVal;\n\n                /* keep default setting, disable mac6 sel serdes*/\n                if ((retVal = rtl8367c_setAsicReg(0x1d11, 0x1500)) != RT_ERR_OK)\n                    return retVal;\n\n                /*Enable new sds mode config method, cfg_sds_mode_sel_new=1*/\n                if ((retVal = rtl8367c_setAsicRegBit(0x1d95, 13, 1)) != RT_ERR_OK)\n                    return retVal;\n\n                /*  bit[12:8]: Only valid when cfg_sds_mode_sel_new=1\n                    new_cfg_sds_mode=0x1F (reset mode) */\n                if ((retVal = rtl8367c_setAsicRegBits(0x1d95, 0x1f00, 0x1f)) != RT_ERR_OK)\n                    return retVal;\n\n                /*bit5: cfg_mac6_fib=0       &       bit7: cfg_mac6_fib2=0*/\n                if ((retVal = rtl8367c_setAsicRegBit(0x1d41, 5, 0)) != RT_ERR_OK)\n                    return retVal;\n                if ((retVal = rtl8367c_setAsicRegBit(0x1d41, 7, 0)) != RT_ERR_OK)\n                    return retVal;\n\n                /*cfg_mac7_sel_sgmii= 1 & cfg_mac7_fib=1*/\n                if ((retVal = rtl8367c_setAsicRegBits(0x1d95, 3, 3)) != RT_ERR_OK)\n                    return retVal;\n\n                /*  bit[12:8]: Only valid when cfg_sds_mode_sel_new=1\n                    new_cfg_sds_mode=0x5  */\n                if ((retVal = rtl8367c_setAsicRegBits(0x1d95, 0x1f00, 0x5)) != RT_ERR_OK)\n                    return retVal;\n            }\n            else if (mode == EXT_1000X_100FX)\n            {\n                /*  disable mac7 MII/TMM/RMII/GMII/RGMII mode, mode_ext2 = disable  */\n                if ((retVal = rtl8367c_setAsicRegBits(0x13c3, 0xf, 0)) != RT_ERR_OK)\n                    return retVal;\n\n                /*restore ext2 ability*/\n                if ((retVal = rtl8367c_setAsicReg(0x13c4, 0)) != RT_ERR_OK)\n                    return retVal;\n\n                /* 0 2 0  bit 8~9  set 0, force n-way*/\n                if((retVal = rtl8367c_getAsicSdsReg(0, 2, 0, &reg_data)) != RT_ERR_OK)\n                    return retVal;\n                reg_data &= 0xFFFFFCFF;\n                if((retVal = rtl8367c_setAsicSdsReg(0,2,0, reg_data)) != RT_ERR_OK)\n                        return retVal;\n\n                /*restore ext2 ability*/\n                if ((retVal = rtl8367c_setAsicRegBit(0x3f7, 2, 0)) != RT_ERR_OK)\n                    return retVal;\n\n                /* keep default setting, disable mac6 sel serdes*/\n                if ((retVal = rtl8367c_setAsicReg(0x1d11, 0x1500)) != RT_ERR_OK)\n                    return retVal;\n\n                /*Enable new sds mode config method, cfg_sds_mode_sel_new=1*/\n                if ((retVal = rtl8367c_setAsicRegBit(0x1d95, 13, 1)) != RT_ERR_OK)\n                    return retVal;\n\n                /*  bit[12:8]: Only valid when cfg_sds_mode_sel_new=1\n                    new_cfg_sds_mode=0x1F (reset mode) */\n                if ((retVal = rtl8367c_setAsicRegBits(0x1d95, 0x1f00, 0x1f)) != RT_ERR_OK)\n                    return retVal;\n\n                /*bit5: cfg_mac6_fib=0    &    bit7: cfg_mac6_fib2=0*/\n                if ((retVal = rtl8367c_setAsicRegBit(0x1d41, 5, 0)) != RT_ERR_OK)\n                    return retVal;\n                if ((retVal = rtl8367c_setAsicRegBit(0x1d41, 7, 0)) != RT_ERR_OK)\n                    return retVal;\n\n                /*cfg_mac7_sel_sgmii= 1 & cfg_mac7_fib=1*/\n                if ((retVal = rtl8367c_setAsicRegBits(0x1d95, 3, 3)) != RT_ERR_OK)\n                    return retVal;\n\n                /*  bit[12:8]: Only valid when cfg_sds_mode_sel_new=1\n                    new_cfg_sds_mode=0x7  */\n                if ((retVal = rtl8367c_setAsicRegBits(0x1d95, 0x1f00, 0x7)) != RT_ERR_OK)\n                    return retVal;\n            }\n            else if (mode < EXT_SGMII)\n            {\n                if ((retVal = rtl8367c_setAsicRegBit(0x1d3d, 10, 0)) != RT_ERR_OK)\n                    return retVal;\n\n                if ((retVal = rtl8367c_setAsicRegBit(0x3f7, 2, 0)) != RT_ERR_OK)\n                    return retVal;\n\n                /* keep default setting, disable mac7 sel SerDes mode*/\n                if ((retVal = rtl8367c_setAsicReg(0x1d95, 0x1f00)) != RT_ERR_OK)\n                    return retVal;\n\n                /*cfg_mac7_sel_sgmii= 0 & cfg_mac7_fib=0*/\n                if ((retVal = rtl8367c_setAsicRegBits(0x1d95, 3, 0)) != RT_ERR_OK)\n                    return retVal;\n\n                /* set port7 mode*/\n                if ((retVal = rtl8367c_setAsicRegBits(0x13c3, 0xf, mode)) != RT_ERR_OK)\n                    return retVal;\n\n                if ((mode == EXT_TMII_MAC) || (mode == EXT_TMII_PHY))\n                {\n                    if ((retVal = rtl8367c_setAsicRegBit(0x3f7, 2, 1)) != RT_ERR_OK)\n                        return retVal;\n                }\n\n            }\n            else if ((mode < EXT_END) && (mode > EXT_100FX))\n            {\n                if ((retVal = rtl8367c_setAsicRegBits(0x13C3, 0xf, 0)) != RT_ERR_OK)\n                    return retVal;\n\n                if ((retVal = rtl8367c_setAsicRegBit(0x3f7, 2, 0)) != RT_ERR_OK)\n                    return retVal;\n\n                /*cfg_mac7_sel_sgmii= 0 & cfg_mac7_fib=0*/\n                if ((retVal = rtl8367c_setAsicRegBits(0x1d95, 3, 0)) != RT_ERR_OK)\n                    return retVal;\n\n                if ((retVal = rtl8367c_setAsicRegBit(0x1d3d, 10, 1)) != RT_ERR_OK)\n                    return retVal;\n\n                if ((retVal = rtl8367c_getAsicRegBit(0x1d11, 11, &reg_data)) != RT_ERR_OK)\n                    return retVal;\n                if(reg_data == 0)\n                {\n                    if ((retVal = rtl8367c_setAsicRegBit(0x1d11, 6, 1)) != RT_ERR_OK)\n                        return retVal;\n                }\n\n                /* set port7 mode*/\n                if (mode < EXT_RMII_MAC_2)\n                {\n                    if ((retVal = rtl8367c_setAsicRegBits(0x1305, 0xf0, (mode-13))) != RT_ERR_OK)\n                        return retVal;\n                }\n                else\n                {\n                    if ((retVal = rtl8367c_setAsicRegBits(0x1305, 0xf0, (mode-12))) != RT_ERR_OK)\n                        return retVal;\n                }\n\n                if ((mode == EXT_TMII_MAC_2) || (mode == EXT_TMII_PHY_2))\n                {\n                    if ((retVal = rtl8367c_setAsicRegBit(0x3f7, 2, 1)) != RT_ERR_OK)\n                        return retVal;\n                }\n            }\n\n        }\n\n    }\n    return RT_ERR_OK;\n}\n/* Function Name:\n *      rtl8367c_getAsicPortExtMode\n * Description:\n *      Get external interface mode configuration\n * Input:\n *      id      - external interface id (0~1)\n *      pMode   - external interface mode\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_OUT_OF_RANGE - input parameter out of range\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicPortExtMode(rtk_uint32 id, rtk_uint32 *pMode)\n{\n    ret_t   retVal;\n    rtk_uint32 regData, regValue, type;\n\n    if(id >= RTL8367C_EXTNO)\n        return RT_ERR_OUT_OF_RANGE;\n    /*cfg_magic_id  &  get chip_id*/\n    if((retVal = rtl8367c_setAsicReg(0x13C2, 0x0249)) != RT_ERR_OK)\n        return retVal;\n\n    if((retVal = rtl8367c_getAsicReg(0x1300, &regValue)) != RT_ERR_OK)\n        return retVal;\n\n    if((retVal = rtl8367c_setAsicReg(0x13C2, 0x0000)) != RT_ERR_OK)\n        return retVal;\n\n    type = 0;\n\n    switch (regValue)\n    {\n        case 0x0276:\n        case 0x0597:\n        case 0x6367:\n            type = 1;\n            break;\n        case 0x0652:\n        case 0x6368:\n            type = 2;\n            break;\n        case 0x0801:\n        case 0x6511:\n            type = 3;\n            break;\n        default:\n            return RT_ERR_FAILED;\n    }\n\n\n    if (1 == type)\n    {\n\n        if (1 == id)\n        {\n            if( (retVal = rtl8367c_getAsicRegBit(RTL8367C_REG_SDS_MISC, RTL8367C_CFG_MAC8_SEL_SGMII_OFFSET, &regData)) != RT_ERR_OK)\n                return retVal;\n\n            if(1 == regData)\n            {\n                *pMode = EXT_SGMII;\n                return RT_ERR_OK;\n            }\n\n            if( (retVal = rtl8367c_getAsicRegBit(RTL8367C_REG_SDS_MISC, RTL8367C_CFG_MAC8_SEL_HSGMII_OFFSET, &regData)) != RT_ERR_OK)\n                return retVal;\n\n            if(1 == regData)\n            {\n                *pMode = EXT_HSGMII;\n                return RT_ERR_OK;\n            }\n        }\n\n        if(0 == id || 1 == id)\n            return rtl8367c_getAsicRegBits(RTL8367C_REG_DIGITAL_INTERFACE_SELECT, RTL8367C_SELECT_GMII_0_MASK << (id * RTL8367C_SELECT_GMII_1_OFFSET), pMode);\n        else\n           return rtl8367c_getAsicRegBits(RTL8367C_REG_DIGITAL_INTERFACE_SELECT_1, RTL8367C_SELECT_GMII_2_MASK, pMode);\n\n    }\n    else if (2 == type)\n    {\n        if (1 == id)\n        {\n            if ((retVal = rtl8367c_getAsicReg(0x1d92, &regData))!=RT_ERR_OK)\n                return retVal;\n\n            if (regData & 0x4000)\n            {\n                *pMode = EXT_SGMII;\n                return RT_ERR_OK;\n            }\n\n            else if (((regData >> 8) & 0x1f) == 4)\n            {\n                *pMode = EXT_1000X;\n                return RT_ERR_OK;\n            }\n            else if (((regData >> 8) & 0x1f) == 5)\n            {\n                *pMode = EXT_100FX;\n                return RT_ERR_OK;\n            }\n            else if (((regData >> 8) & 0x1f) == 7)\n            {\n                *pMode = EXT_1000X_100FX;\n                return RT_ERR_OK;\n            }\n\n            return rtl8367c_getAsicRegBits(0x1305, 0xf0, pMode);\n        }\n        else if (2 == id)\n        {\n#if 0\n            if ((retVal = rtl8367c_getAsicRegBit(0x1d92, 6, &regData))!=RT_ERR_OK)\n                return retVal;\n\n            if (regData == 1)\n            {\n                *pMode = EXT_SGMII;\n                return RT_ERR_OK;\n            }\n\n            if ((retVal = rtl8367c_getAsicRegBit(0x1d92, 7, &regData))!=RT_ERR_OK)\n                return retVal;\n\n            if (regData == 1)\n            {\n                *pMode = EXT_HSGMII;\n                return RT_ERR_OK;\n            }\n#endif\n            if ((retVal = rtl8367c_getAsicReg(0x1d92, &regData))!=RT_ERR_OK)\n                return retVal;\n\n            if (regData & 0x40)\n            {\n                *pMode = EXT_SGMII;\n                return RT_ERR_OK;\n            }\n            else if (regData & 0x80)\n            {\n                *pMode = EXT_HSGMII;\n                return RT_ERR_OK;\n            }\n            else if ((regData & 0x1f) == 4)\n            {\n                *pMode = EXT_1000X;\n                return RT_ERR_OK;\n            }\n            else if ((regData & 0x1f) == 5)\n            {\n                *pMode = EXT_100FX;\n                return RT_ERR_OK;\n            }\n            else if ((regData & 0x1f) == 7)\n            {\n                *pMode = EXT_1000X_100FX;\n                return RT_ERR_OK;\n            }\n\n            return rtl8367c_getAsicRegBits(0x1305, 0xf, pMode);\n        }\n    }\n    else if(3 == type)\n    {\n        if (1 == id)\n        {\n            /* SDS_CFG_NEW */\n            if ((retVal = rtl8367c_getAsicReg(0x1d95, &regData))!=RT_ERR_OK)\n                return retVal;\n\n            if ((retVal = rtl8367c_getAsicReg(0x1d41, &regValue))!=RT_ERR_OK)\n                return retVal;\n\n            /* bit5: cfg_mac6_fib=1  &&  bit7: cfg_mac6_fib2 =1 */\n            if((regValue & 0xa0)  == 0xa0 )\n            {\n                /* new_cfg_sds_mode */\n                regData = regData >> 8;\n                if((regData & 0x1f) == 4)\n                {\n                    *pMode = EXT_1000X;\n                     return RT_ERR_OK;\n                }\n                else if((regData & 0x1f) == 5)\n                {\n                    *pMode = EXT_100FX;\n                     return RT_ERR_OK;\n                }\n                else if((regData & 0x1f) == 7)\n                {\n                    *pMode = EXT_1000X_100FX;\n                     return RT_ERR_OK;\n                }\n\n            }\n\n\n            if ((retVal = rtl8367c_getAsicReg(0x1d11, &regData))!=RT_ERR_OK)\n                return retVal;\n\n            /* check cfg_mac6_sel_sgmii */\n            if((regData >> 6) & 1)\n            {\n                *pMode = EXT_SGMII;\n                return RT_ERR_OK;\n            }\n            else if((regData >> 11) & 1)\n            {\n                *pMode = EXT_HSGMII;\n                return RT_ERR_OK;\n            }\n            else\n            {\n                /* check port6 MAC mode */\n                if ((retVal = rtl8367c_getAsicRegBits(0x1305, 0xf0, &regData))!=RT_ERR_OK)\n                    return retVal;\n\n                if(regData < 6)\n                    *pMode = regData;\n                else if(regData == 6)\n                    *pMode = EXT_RMII_MAC;\n                else if(regData == 7)\n                    *pMode = EXT_RMII_PHY;\n\n                return RT_ERR_OK;\n            }\n        }\n        else if (2 == id)\n        {\n            if ((retVal = rtl8367c_getAsicReg(0x1d95, &regData))!=RT_ERR_OK)\n                return retVal;\n\n            /* bit0: cfg_mac7_sel_sgmii\n               bit1: cfg_mac7_fib\n               bit[12:8]: new_cfg_sds_mode*/\n            if(((regData & 0x3) == 3) && (((regData >> 8) & 0x1f) == 0x4))\n            {\n                *pMode = EXT_1000X;\n                    return RT_ERR_OK;\n            }\n            else if (((regData & 0x3) == 3) && (((regData >> 8) & 0x1f) == 0x5))\n            {\n                *pMode = EXT_100FX;\n                    return RT_ERR_OK;\n            }\n            else if (((regData & 0x3) == 3) && (((regData >> 8) & 0x1f) == 0x7))\n            {\n                *pMode = EXT_1000X_100FX;\n                    return RT_ERR_OK;\n            }\n            else if(regData & 1)\n            {\n                *pMode = EXT_SGMII;\n                return RT_ERR_OK;\n            }\n            else\n            {\n            /* check port7 MAC mode */\n                if ((retVal = rtl8367c_getAsicRegBits(0x13c3, 0xf, &regData))!=RT_ERR_OK)\n                    return retVal;\n\n                *pMode = regData;\n\n                return RT_ERR_OK;\n            }\n        }\n    }\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtl8370_setAsicPortEnableAll\n * Description:\n *      Set ALL ports enable.\n * Input:\n *      enable - enable all ports.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicPortEnableAll(rtk_uint32 enable)\n{\n    if(enable >= 2)\n        return RT_ERR_INPUT;\n\n    return rtl8367c_setAsicRegBit(RTL8367C_REG_PHY_AD, RTL8367C_PDNPHY_OFFSET, !enable);\n}\n\n/* Function Name:\n *      rtl8367c_getAsicPortEnableAll\n * Description:\n *      Set ALL ports enable.\n * Input:\n *      enable - enable all ports.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicPortEnableAll(rtk_uint32 *pEnable)\n{\n    ret_t retVal;\n    rtk_uint32 regData;\n\n    retVal = rtl8367c_getAsicRegBit(RTL8367C_REG_PHY_AD, RTL8367C_PDNPHY_OFFSET, &regData);\n    if(retVal !=  RT_ERR_OK)\n        return retVal;\n\n    if (regData==0)\n        *pEnable = 1;\n    else\n        *pEnable = 0;\n\n    return RT_ERR_OK;\n}\n/* Function Name:\n *      rtl8367c_setAsicPortSmallIpg\n * Description:\n *      Set small ipg egress mode\n * Input:\n *      port    - Physical port number (0~7)\n *      enable  - 0: normal, 1: small\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n *      RT_ERR_PORT_ID  - Invalid port number\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicPortSmallIpg(rtk_uint32 port, rtk_uint32 enable)\n{\n    if(port >= RTL8367C_PORTNO)\n        return RT_ERR_PORT_ID;\n\n    return rtl8367c_setAsicRegBit(RTL8367C_PORT_SMALL_IPG_REG(port), RTL8367C_PORT0_MISC_CFG_SMALL_TAG_IPG_OFFSET, enable);\n}\n\n/* Function Name:\n *      rtl8367c_getAsicPortSmallIpg\n * Description:\n *      Get small ipg egress mode\n * Input:\n *      port    - Physical port number (0~7)\n *      pEnable     - 0: normal, 1: small\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n *      RT_ERR_PORT_ID  - Invalid port number\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicPortSmallIpg(rtk_uint32 port, rtk_uint32* pEnable)\n{\n    if(port >= RTL8367C_PORTNO)\n        return RT_ERR_PORT_ID;\n\n    return rtl8367c_getAsicRegBit(RTL8367C_PORT_SMALL_IPG_REG(port), RTL8367C_PORT0_MISC_CFG_SMALL_TAG_IPG_OFFSET, pEnable);\n}\n\n/* Function Name:\n *      rtl8367c_setAsicPortLoopback\n * Description:\n *      Set MAC loopback\n * Input:\n *      port    - Physical port number (0~7)\n *      enable  - 0: Disable, 1: enable\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n *      RT_ERR_PORT_ID  - Invalid port number\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicPortLoopback(rtk_uint32 port, rtk_uint32 enable)\n{\n    if(port >= RTL8367C_PORTNO)\n        return RT_ERR_PORT_ID;\n\n    return rtl8367c_setAsicRegBit(RTL8367C_PORT_MISC_CFG_REG(port), RTL8367C_PORT0_MISC_CFG_MAC_LOOPBACK_OFFSET, enable);\n}\n\n/* Function Name:\n *      rtl8367c_getAsicPortLoopback\n * Description:\n *      Set MAC loopback\n * Input:\n *      port    - Physical port number (0~7)\n * Output:\n *      pEnable - 0: Disable, 1: enable\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n *      RT_ERR_PORT_ID  - Invalid port number\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicPortLoopback(rtk_uint32 port, rtk_uint32 *pEnable)\n{\n    if(port >= RTL8367C_PORTNO)\n        return RT_ERR_PORT_ID;\n\n    return rtl8367c_getAsicRegBit(RTL8367C_PORT_MISC_CFG_REG(port), RTL8367C_PORT0_MISC_CFG_MAC_LOOPBACK_OFFSET, pEnable);\n}\n\n/* Function Name:\n *      rtl8367c_setAsicPortRTCTEnable\n * Description:\n *      Set RTCT Enable echo response mode\n * Input:\n *      portmask    - Port mask of RTCT enabled (0-4)\n * Output:\n *      None.\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_MASK    - Invalid port mask\n * Note:\n *      RTCT test takes 4.8 seconds at most.\n */\nret_t rtl8367c_setAsicPortRTCTEnable(rtk_uint32 portmask)\n{\n    ret_t       retVal;\n    rtk_uint32  regData;\n    rtk_uint32  port;\n\n    if((retVal = rtl8367c_setAsicReg(0x13C2, 0x0249)) != RT_ERR_OK)\n        return retVal;\n\n    if((retVal = rtl8367c_getAsicReg(0x1300, &regData)) != RT_ERR_OK)\n        return retVal;\n\n    if( (regData == 0x0276) || (regData == 0x0597) )\n        return RT_ERR_CHIP_NOT_SUPPORTED;\n\n    for(port = 0; port <= 10 ; port++)\n    {\n        if(portmask & (0x0001 << port))\n        {\n             if((retVal = rtl8367c_getAsicPHYOCPReg(port, 0xa422, &regData)) != RT_ERR_OK)\n                 return retVal;\n\n             regData &= 0x7FFF;\n             if((retVal = rtl8367c_setAsicPHYOCPReg(port, 0xa422, regData)) != RT_ERR_OK)\n                 return retVal;\n\n             regData |= 0x00F2;/*RTCT set to  echo response mode*/\n             if((retVal = rtl8367c_setAsicPHYOCPReg(port, 0xa422, regData)) != RT_ERR_OK)\n                 return retVal;\n\n             regData |= 0x0001;\n             if((retVal = rtl8367c_setAsicPHYOCPReg(port, 0xa422, regData)) != RT_ERR_OK)\n                 return retVal;\n        }\n    }\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtl8367c_setAsicPortRTCTDisable\n * Description:\n *      Set RTCT Disable\n * Input:\n *      portmask    - Port mask of RTCT enabled (0-4)\n * Output:\n *      None.\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_MASK    - Invalid port mask\n * Note:\n *      RTCT test takes 4.8 seconds at most.\n */\nret_t rtl8367c_setAsicPortRTCTDisable(rtk_uint32 portmask)\n{\n    ret_t       retVal;\n    rtk_uint32  regData;\n    rtk_uint32  port;\n\n    if((retVal = rtl8367c_setAsicReg(0x13C2, 0x0249)) != RT_ERR_OK)\n        return retVal;\n\n    if((retVal = rtl8367c_getAsicReg(0x1300, &regData)) != RT_ERR_OK)\n        return retVal;\n\n    if( (regData == 0x0276) || (regData == 0x0597) )\n        return RT_ERR_CHIP_NOT_SUPPORTED;\n\n    for(port = 0; port <= 10 ; port++)\n    {\n        if(portmask & (0x0001 << port))\n        {\n             if((retVal = rtl8367c_getAsicPHYOCPReg(port, 0xa422, &regData)) != RT_ERR_OK)\n                 return retVal;\n\n             regData &= 0x7FFF;\n             if((retVal = rtl8367c_setAsicPHYOCPReg(port, 0xa422, regData)) != RT_ERR_OK)\n                 return retVal;\n\n             regData |= 0x00F0;\n             if((retVal = rtl8367c_setAsicPHYOCPReg(port, 0xa422, regData)) != RT_ERR_OK)\n                 return retVal;\n\n             regData &= ~0x0001;\n             if((retVal = rtl8367c_setAsicPHYOCPReg(port, 0xa422, regData)) != RT_ERR_OK)\n                 return retVal;\n        }\n    }\n\n    return RT_ERR_OK;\n}\n\n\n/* Function Name:\n *      rtl8367c_getAsicPortRTCTResult\n * Description:\n *      Get RTCT result\n * Input:\n *      port    - Port ID of RTCT result\n * Output:\n *      pResult - The result of port ID\n * Return:\n *      RT_ERR_OK                   - Success\n *      RT_ERR_SMI                  - SMI access error\n *      RT_ERR_PORT_MASK            - Invalid port mask\n *      RT_ERR_PHY_RTCT_NOT_FINISH  - RTCT test doesn't finish.\n * Note:\n *      RTCT test takes 4.8 seconds at most.\n *      If this API returns RT_ERR_PHY_RTCT_NOT_FINISH,\n *      users should wait a whole then read it again.\n */\nret_t rtl8367c_getAsicPortRTCTResult(rtk_uint32 port, rtl8367c_port_rtct_result_t *pResult)\n{\n    ret_t       retVal;\n    rtk_uint32  regData, finish = 1;\n\n    if((retVal = rtl8367c_setAsicReg(0x13C2, 0x0249)) != RT_ERR_OK)\n        return retVal;\n\n    if((retVal = rtl8367c_getAsicReg(0x1300, &regData)) != RT_ERR_OK)\n        return retVal;\n\n    if( (regData == 0x6367) )\n    {\n        if((retVal = rtl8367c_getAsicPHYOCPReg(port, 0xa422, &regData)) != RT_ERR_OK)\n            return retVal;\n\n        if((regData & 0x8000) == 0x8000)\n        {\n            /* Channel A */\n            if((retVal = rtl8367c_setAsicPHYOCPReg(port, 0xa436, 0x802a)) != RT_ERR_OK)\n                return retVal;\n\n            if((retVal = rtl8367c_getAsicPHYOCPReg(port, 0xa438, &regData)) != RT_ERR_OK)\n                return retVal;\n\n            pResult->channelAOpen       = (regData == 0x0048) ? 1 : 0;\n            pResult->channelAShort      = (regData == 0x0050) ? 1 : 0;\n            pResult->channelAMismatch   = ((regData == 0x0042) || (regData == 0x0044)) ? 1 : 0;\n            pResult->channelALinedriver = (regData == 0x0041) ? 1 : 0;\n\n            /* Channel B */\n            if((retVal = rtl8367c_setAsicPHYOCPReg(port, 0xa436, 0x802e)) != RT_ERR_OK)\n                return retVal;\n\n            if((retVal = rtl8367c_getAsicPHYOCPReg(port, 0xa438, &regData)) != RT_ERR_OK)\n                return retVal;\n\n            pResult->channelBOpen       = (regData == 0x0048) ? 1 : 0;\n            pResult->channelBShort      = (regData == 0x0050) ? 1 : 0;\n            pResult->channelBMismatch   = ((regData == 0x0042) || (regData == 0x0044)) ? 1 : 0;\n            pResult->channelBLinedriver = (regData == 0x0041) ? 1 : 0;\n\n            /* Channel C */\n            if((retVal = rtl8367c_setAsicPHYOCPReg(port, 0xa436, 0x8032)) != RT_ERR_OK)\n                return retVal;\n\n            if((retVal = rtl8367c_getAsicPHYOCPReg(port, 0xa438, &regData)) != RT_ERR_OK)\n                return retVal;\n\n            pResult->channelCOpen       = (regData == 0x0048) ? 1 : 0;\n            pResult->channelCShort      = (regData == 0x0050) ? 1 : 0;\n            pResult->channelCMismatch   = ((regData == 0x0042) || (regData == 0x0044)) ? 1 : 0;\n            pResult->channelCLinedriver = (regData == 0x0041) ? 1 : 0;\n\n            /* Channel D */\n            if((retVal = rtl8367c_setAsicPHYOCPReg(port, 0xa436, 0x8036)) != RT_ERR_OK)\n                return retVal;\n\n            if((retVal = rtl8367c_getAsicPHYOCPReg(port, 0xa438, &regData)) != RT_ERR_OK)\n                return retVal;\n\n            pResult->channelDOpen       = (regData == 0x0048) ? 1 : 0;\n            pResult->channelDShort      = (regData == 0x0050) ? 1 : 0;\n            pResult->channelDMismatch   = ((regData == 0x0042) || (regData == 0x0044)) ? 1 : 0;\n            pResult->channelDLinedriver = (regData == 0x0041) ? 1 : 0;\n\n            /* Channel A Length */\n            if((retVal = rtl8367c_setAsicPHYOCPReg(port, 0xa436, 0x802c)) != RT_ERR_OK)\n                return retVal;\n\n            if((retVal = rtl8367c_getAsicPHYOCPReg(port, 0xa438, &regData)) != RT_ERR_OK)\n                return retVal;\n\n            pResult->channelALen = (regData / 2);\n\n            /* Channel B Length */\n            if((retVal = rtl8367c_setAsicPHYOCPReg(port, 0xa436, 0x8030)) != RT_ERR_OK)\n                return retVal;\n\n            if((retVal = rtl8367c_getAsicPHYOCPReg(port, 0xa438, &regData)) != RT_ERR_OK)\n                return retVal;\n\n            pResult->channelBLen = (regData / 2);\n\n            /* Channel C Length */\n            if((retVal = rtl8367c_setAsicPHYOCPReg(port, 0xa436, 0x8034)) != RT_ERR_OK)\n                return retVal;\n\n            if((retVal = rtl8367c_getAsicPHYOCPReg(port, 0xa438, &regData)) != RT_ERR_OK)\n                return retVal;\n\n            pResult->channelCLen = (regData / 2);\n\n            /* Channel D Length */\n            if((retVal = rtl8367c_setAsicPHYOCPReg(port, 0xa436, 0x8038)) != RT_ERR_OK)\n                return retVal;\n\n            if((retVal = rtl8367c_getAsicPHYOCPReg(port, 0xa438, &regData)) != RT_ERR_OK)\n                return retVal;\n\n            pResult->channelDLen = (regData / 2);\n        }\n        else\n            finish = 0;\n    }\n    else if(regData == 0x6368)\n    {\n        if((retVal = rtl8367c_getAsicPHYOCPReg(port, 0xa422, &regData)) != RT_ERR_OK)\n            return retVal;\n\n        if((regData & 0x8000) == 0x8000)\n        {\n            /* Channel A */\n            if((retVal = rtl8367c_setAsicPHYOCPReg(port, 0xa436, 0x802b)) != RT_ERR_OK)\n                return retVal;\n\n            if((retVal = rtl8367c_getAsicPHYOCPReg(port, 0xa438, &regData)) != RT_ERR_OK)\n                return retVal;\n\n            pResult->channelAOpen       = (regData == 0x0048) ? 1 : 0;\n            pResult->channelAShort      = (regData == 0x0050) ? 1 : 0;\n            pResult->channelAMismatch   = ((regData == 0x0042) || (regData == 0x0044)) ? 1 : 0;\n            pResult->channelALinedriver = (regData == 0x0041) ? 1 : 0;\n\n            /* Channel B */\n            if((retVal = rtl8367c_setAsicPHYOCPReg(port, 0xa436, 0x802f)) != RT_ERR_OK)\n                return retVal;\n\n            if((retVal = rtl8367c_getAsicPHYOCPReg(port, 0xa438, &regData)) != RT_ERR_OK)\n                return retVal;\n\n            pResult->channelBOpen       = (regData == 0x0048) ? 1 : 0;\n            pResult->channelBShort      = (regData == 0x0050) ? 1 : 0;\n            pResult->channelBMismatch   = ((regData == 0x0042) || (regData == 0x0044)) ? 1 : 0;\n            pResult->channelBLinedriver = (regData == 0x0041) ? 1 : 0;\n\n            /* Channel C */\n            if((retVal = rtl8367c_setAsicPHYOCPReg(port, 0xa436, 0x8033)) != RT_ERR_OK)\n                return retVal;\n\n            if((retVal = rtl8367c_getAsicPHYOCPReg(port, 0xa438, &regData)) != RT_ERR_OK)\n                return retVal;\n\n            pResult->channelCOpen       = (regData == 0x0048) ? 1 : 0;\n            pResult->channelCShort      = (regData == 0x0050) ? 1 : 0;\n            pResult->channelCMismatch   = ((regData == 0x0042) || (regData == 0x0044)) ? 1 : 0;\n            pResult->channelCLinedriver = (regData == 0x0041) ? 1 : 0;\n\n            /* Channel D */\n            if((retVal = rtl8367c_setAsicPHYOCPReg(port, 0xa436, 0x8037)) != RT_ERR_OK)\n                return retVal;\n\n            if((retVal = rtl8367c_getAsicPHYOCPReg(port, 0xa438, &regData)) != RT_ERR_OK)\n                return retVal;\n\n            pResult->channelDOpen       = (regData == 0x0048) ? 1 : 0;\n            pResult->channelDShort      = (regData == 0x0050) ? 1 : 0;\n            pResult->channelDMismatch   = ((regData == 0x0042) || (regData == 0x0044)) ? 1 : 0;\n            pResult->channelDLinedriver = (regData == 0x0041) ? 1 : 0;\n\n            /* Channel A Length */\n            if((retVal = rtl8367c_setAsicPHYOCPReg(port, 0xa436, 0x802d)) != RT_ERR_OK)\n                return retVal;\n\n            if((retVal = rtl8367c_getAsicPHYOCPReg(port, 0xa438, &regData)) != RT_ERR_OK)\n                return retVal;\n\n            pResult->channelALen = (regData / 2);\n\n            /* Channel B Length */\n            if((retVal = rtl8367c_setAsicPHYOCPReg(port, 0xa436, 0x8031)) != RT_ERR_OK)\n                return retVal;\n\n            if((retVal = rtl8367c_getAsicPHYOCPReg(port, 0xa438, &regData)) != RT_ERR_OK)\n                return retVal;\n\n            pResult->channelBLen = (regData / 2);\n\n            /* Channel C Length */\n            if((retVal = rtl8367c_setAsicPHYOCPReg(port, 0xa436, 0x8035)) != RT_ERR_OK)\n                return retVal;\n\n            if((retVal = rtl8367c_getAsicPHYOCPReg(port, 0xa438, &regData)) != RT_ERR_OK)\n                return retVal;\n\n            pResult->channelCLen = (regData / 2);\n\n            /* Channel D Length */\n            if((retVal = rtl8367c_setAsicPHYOCPReg(port, 0xa436, 0x8039)) != RT_ERR_OK)\n                return retVal;\n\n            if((retVal = rtl8367c_getAsicPHYOCPReg(port, 0xa438, &regData)) != RT_ERR_OK)\n                return retVal;\n\n            pResult->channelDLen = (regData / 2);\n        }\n        else\n            finish = 0;\n\n    }\n    else if((regData == 0x6511) || (regData == 0x0801))\n    {\n        if((retVal = rtl8367c_getAsicPHYOCPReg(port, 0xa422, &regData)) != RT_ERR_OK)\n            return retVal;\n\n        if((regData & 0x8000) == 0x8000)\n        {\n            /* Channel A */\n            if((retVal = rtl8367c_setAsicPHYOCPReg(port, 0xa436, 0x802a)) != RT_ERR_OK)\n                return retVal;\n\n            if((retVal = rtl8367c_getAsicPHYOCPReg(port, 0xa438, &regData)) != RT_ERR_OK)\n                return retVal;\n\n            pResult->channelAOpen       = (regData == 0x0048) ? 1 : 0;\n            pResult->channelAShort      = (regData == 0x0050) ? 1 : 0;\n            pResult->channelAMismatch   = ((regData == 0x0042) || (regData == 0x0044)) ? 1 : 0;\n            pResult->channelALinedriver = (regData == 0x0041) ? 1 : 0;\n\n            /* Channel B */\n            if((retVal = rtl8367c_setAsicPHYOCPReg(port, 0xa436, 0x802e)) != RT_ERR_OK)\n                return retVal;\n\n            if((retVal = rtl8367c_getAsicPHYOCPReg(port, 0xa438, &regData)) != RT_ERR_OK)\n                return retVal;\n\n            pResult->channelBOpen       = (regData == 0x0048) ? 1 : 0;\n            pResult->channelBShort      = (regData == 0x0050) ? 1 : 0;\n            pResult->channelBMismatch   = ((regData == 0x0042) || (regData == 0x0044)) ? 1 : 0;\n            pResult->channelBLinedriver = (regData == 0x0041) ? 1 : 0;\n\n            /* Channel C */\n            if((retVal = rtl8367c_setAsicPHYOCPReg(port, 0xa436, 0x8032)) != RT_ERR_OK)\n                return retVal;\n\n            if((retVal = rtl8367c_getAsicPHYOCPReg(port, 0xa438, &regData)) != RT_ERR_OK)\n                return retVal;\n\n            pResult->channelCOpen       = (regData == 0x0048) ? 1 : 0;\n            pResult->channelCShort      = (regData == 0x0050) ? 1 : 0;\n            pResult->channelCMismatch   = ((regData == 0x0042) || (regData == 0x0044)) ? 1 : 0;\n            pResult->channelCLinedriver = (regData == 0x0041) ? 1 : 0;\n\n            /* Channel D */\n            if((retVal = rtl8367c_setAsicPHYOCPReg(port, 0xa436, 0x8036)) != RT_ERR_OK)\n                return retVal;\n\n            if((retVal = rtl8367c_getAsicPHYOCPReg(port, 0xa438, &regData)) != RT_ERR_OK)\n                return retVal;\n\n            pResult->channelDOpen       = (regData == 0x0048) ? 1 : 0;\n            pResult->channelDShort      = (regData == 0x0050) ? 1 : 0;\n            pResult->channelDMismatch   = ((regData == 0x0042) || (regData == 0x0044)) ? 1 : 0;\n            pResult->channelDLinedriver = (regData == 0x0041) ? 1 : 0;\n\n            /* Channel A Length */\n            if((retVal = rtl8367c_setAsicPHYOCPReg(port, 0xa436, 0x802c)) != RT_ERR_OK)\n                return retVal;\n\n            if((retVal = rtl8367c_getAsicPHYOCPReg(port, 0xa438, &regData)) != RT_ERR_OK)\n                return retVal;\n\n            pResult->channelALen = (regData / 2);\n\n            /* Channel B Length */\n            if((retVal = rtl8367c_setAsicPHYOCPReg(port, 0xa436, 0x8030)) != RT_ERR_OK)\n                return retVal;\n\n            if((retVal = rtl8367c_getAsicPHYOCPReg(port, 0xa438, &regData)) != RT_ERR_OK)\n                return retVal;\n\n            pResult->channelBLen = (regData / 2);\n\n            /* Channel C Length */\n            if((retVal = rtl8367c_setAsicPHYOCPReg(port, 0xa436, 0x8034)) != RT_ERR_OK)\n                return retVal;\n\n            if((retVal = rtl8367c_getAsicPHYOCPReg(port, 0xa438, &regData)) != RT_ERR_OK)\n                return retVal;\n\n            pResult->channelCLen = (regData / 2);\n\n            /* Channel D Length */\n            if((retVal = rtl8367c_setAsicPHYOCPReg(port, 0xa436, 0x8038)) != RT_ERR_OK)\n                return retVal;\n\n            if((retVal = rtl8367c_getAsicPHYOCPReg(port, 0xa438, &regData)) != RT_ERR_OK)\n                return retVal;\n\n            pResult->channelDLen = (regData / 2);\n        }\n        else\n            finish = 0;\n\n    }\n    else\n        return RT_ERR_CHIP_NOT_SUPPORTED;\n\n    if(finish == 0)\n        return RT_ERR_PHY_RTCT_NOT_FINISH;\n    else\n        return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtl8367c_sdsReset\n * Description:\n *      Reset Serdes\n * Input:\n *      id  - EXT ID\n * Output:\n *      None.\n * Return:\n *      RT_ERR_OK                   - Success\n *      RT_ERR_SMI                  - SMI access error\n * Note:\n *      None.\n */\nret_t rtl8367c_sdsReset(rtk_uint32 id)\n{\n    rtk_uint32 retVal, regValue, state, i, option, running = 0, retVal2;\n\n    if((retVal = rtl8367c_setAsicReg(0x13C2, 0x0249)) != RT_ERR_OK)\n        return retVal;\n\n    if((retVal = rtl8367c_getAsicReg(0x1300, &regValue)) != RT_ERR_OK)\n        return retVal;\n\n    if((retVal = rtl8367c_setAsicReg(0x13C2, 0x0000)) != RT_ERR_OK)\n        return retVal;\n\n    switch (regValue)\n    {\n        case 0x0276:\n        case 0x0597:\n        case 0x6367:\n            option = 0;\n            break;\n        case 0x0652:\n        case 0x6368:\n            option = 1;\n            break;\n        case 0x0801:\n        case 0x6511:\n            option = 2;\n            break;\n        default:\n            return RT_ERR_FAILED;\n    }\n\n    if(option == 0)\n    {\n        if (1 == id)\n        {\n            if ((retVal = rtl8367c_getAsicRegBit(0x130c, 5, &running))!=RT_ERR_OK)\n                return retVal;\n\n            if(running == 1)\n            {\n                if ((retVal = rtl8367c_setAsicRegBit(0x130c, 5, 0))!=RT_ERR_OK)\n                    return retVal;\n            }\n\n            retVal = rtl8367c_setAsicReg(0x6601, 0x0000);\n\n            if(retVal == RT_ERR_OK)\n                retVal = rtl8367c_setAsicReg(0x6602, 0x1401);\n\n            if(retVal == RT_ERR_OK)\n                retVal = rtl8367c_setAsicReg(0x6600, 0x00C0);\n\n            if(retVal == RT_ERR_OK)\n                retVal = rtl8367c_setAsicReg(0x6601, 0x0000);\n\n            if(retVal == RT_ERR_OK)\n                retVal = rtl8367c_setAsicReg(0x6602, 0x1403);\n\n            if(retVal == RT_ERR_OK)\n                retVal = rtl8367c_setAsicReg(0x6600, 0x00C0);\n\n            if(running == 1)\n            {\n                if ((retVal2 = rtl8367c_setAsicRegBit(0x130c, 5, 1))!=RT_ERR_OK)\n                    return retVal2;\n            }\n\n            if(retVal != RT_ERR_OK)\n                return retVal;\n        }\n        else\n            return RT_ERR_PORT_ID;\n    }\n    else if(option == 1)\n    {\n        if (1 == id)\n        {\n            if((retVal = rtl8367c_getAsicReg(0x1311, &state)) != RT_ERR_OK)\n                return retVal;\n\n            if((retVal = rtl8367c_setAsicReg(0x1311, 0x66)) != RT_ERR_OK)\n                return retVal;\n\n            if((retVal = rtl8367c_setAsicReg(0x1311, 0x1066)) != RT_ERR_OK)\n                return retVal;\n\n            while(1)\n            {\n                if((retVal = rtl8367c_getAsicReg(0x1d9d, &regValue)) != RT_ERR_OK)\n                    return retVal;\n                if((regValue >> 8) & 1)\n                    break;\n            }\n\n            for (i=0; i<0xffff; i++);\n\n            if((retVal = rtl8367c_setAsicReg(0x133d, 0x2)) != RT_ERR_OK)\n                return retVal;\n\n            for (i=0; i<0xffff; i++);\n\n            if((retVal = rtl8367c_setAsicReg(0x6601, 0x0)) != RT_ERR_OK)\n                return retVal;\n            if((retVal = rtl8367c_setAsicReg(0x6602, 0x1401)) != RT_ERR_OK)\n                return retVal;\n            if((retVal = rtl8367c_setAsicReg(0x6600, 0xc1)) != RT_ERR_OK)\n                return retVal;\n            if((retVal = rtl8367c_setAsicReg(0x6601, 0x0)) != RT_ERR_OK)\n                return retVal;\n            if((retVal = rtl8367c_setAsicReg(0x6602, 0x1403)) != RT_ERR_OK)\n                return retVal;\n            if((retVal = rtl8367c_setAsicReg(0x6600, 0xc1)) != RT_ERR_OK)\n                return retVal;\n\n            if((retVal = rtl8367c_setAsicReg(0x133d, 0x0)) != RT_ERR_OK)\n                return retVal;\n\n            for (i=0; i<0xffff; i++);\n\n            if((retVal = rtl8367c_setAsicReg(0x1311, state)) != RT_ERR_OK)\n                return retVal;\n\n\n        }\n        else if (2== id)\n        {\n            if((retVal = rtl8367c_getAsicReg(0x13c4, &state)) != RT_ERR_OK)\n                return retVal;\n\n            if((retVal = rtl8367c_setAsicReg(0x13c4, 0x66)) != RT_ERR_OK)\n                return retVal;\n\n            if((retVal = rtl8367c_setAsicReg(0x13c4, 0x1066)) != RT_ERR_OK)\n                return retVal;\n\n            while(1)\n            {\n                if((retVal = rtl8367c_getAsicReg(0x1d9d, &regValue)) != RT_ERR_OK)\n                    return retVal;\n                if((regValue >> 9) & 1)\n                    break;\n            }\n\n            for (i=0; i<0xffff; i++);\n\n            if((retVal = rtl8367c_setAsicReg(0x133d, 0x2)) != RT_ERR_OK)\n                return retVal;\n\n            for (i=0; i<0xffff; i++);\n\n            if((retVal = rtl8367c_setAsicReg(0x6601, 0x0)) != RT_ERR_OK)\n                return retVal;\n            if((retVal = rtl8367c_setAsicReg(0x6602, 0x1401)) != RT_ERR_OK)\n                return retVal;\n            if((retVal = rtl8367c_setAsicReg(0x6600, 0xc0)) != RT_ERR_OK)\n                return retVal;\n            if((retVal = rtl8367c_setAsicReg(0x6601, 0x0)) != RT_ERR_OK)\n                return retVal;\n            if((retVal = rtl8367c_setAsicReg(0x6602, 0x1403)) != RT_ERR_OK)\n                return retVal;\n            if((retVal = rtl8367c_setAsicReg(0x6600, 0xc0)) != RT_ERR_OK)\n                return retVal;\n\n            if((retVal = rtl8367c_setAsicReg(0x133d, 0x0)) != RT_ERR_OK)\n                return retVal;\n\n            for (i=0; i<0xffff; i++);\n\n            if((retVal = rtl8367c_setAsicReg(0x13c4, state)) != RT_ERR_OK)\n                return retVal;\n        }\n        else\n            return RT_ERR_PORT_ID;\n    }\n    else if(option == 2)\n    {\n        if ((retVal = rtl8367c_getAsicSdsReg(0, 3, 0, &regValue))!=RT_ERR_OK)\n                  return retVal;\n              regValue |= 0x40;\n              if ((retVal = rtl8367c_setAsicSdsReg(0, 3, 0, regValue))!=RT_ERR_OK)\n                  return retVal;\n\n              for (i=0; i<0xffff; i++);\n\n              regValue &= ~(0x40);\n              if ((retVal = rtl8367c_setAsicSdsReg(0, 3, 0, regValue))!=RT_ERR_OK)\n                  return retVal;\n\n    }\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtl8367c_getSdsLinkStatus\n * Description:\n *      Get SGMII status\n * Input:\n *      id  - EXT ID\n * Output:\n *      None.\n * Return:\n *      RT_ERR_OK                   - Success\n *      RT_ERR_SMI                  - SMI access error\n * Note:\n *      None.\n */\nret_t rtl8367c_getSdsLinkStatus(rtk_uint32 ext_id, rtk_uint32 *pSignalDetect, rtk_uint32 *pSync, rtk_uint32 *pLink)\n{\n    rtk_uint32 retVal, regValue, type, running = 0, retVal2;\n\n\n    if((retVal = rtl8367c_setAsicReg(0x13C2, 0x0249)) != RT_ERR_OK)\n        return retVal;\n\n    if((retVal = rtl8367c_getAsicReg(0x1300, &regValue)) != RT_ERR_OK)\n        return retVal;\n\n    if((retVal = rtl8367c_setAsicReg(0x13C2, 0x0000)) != RT_ERR_OK)\n        return retVal;\n\n    switch (regValue)\n    {\n        case 0x0276:\n        case 0x0597:\n        case 0x6367:\n            type = 0;\n            break;\n        case 0x0652:\n        case 0x6368:\n            type = 1;\n            break;\n        case 0x0801:\n        case 0x6511:\n            type = 2;\n            break;\n        default:\n            return RT_ERR_FAILED;\n    }\n\n    if(type == 0)\n    {\n        if (1 == ext_id)\n        {\n            if ((retVal = rtl8367c_getAsicRegBit(0x130c, 5, &running))!=RT_ERR_OK)\n                return retVal;\n\n            if(running == 1)\n            {\n                if ((retVal = rtl8367c_setAsicRegBit(0x130c, 5, 0))!=RT_ERR_OK)\n                    return retVal;\n            }\n\n            retVal = rtl8367c_setAsicReg(0x6601, 0x003D);\n\n            if(retVal == RT_ERR_OK)\n                retVal = rtl8367c_setAsicReg(0x6600, 0x0080);\n\n            if(retVal == RT_ERR_OK)\n                retVal = rtl8367c_getAsicReg(0x6602, &regValue);\n\n            if(running == 1)\n            {\n                if ((retVal2 = rtl8367c_setAsicRegBit(0x130c, 5, 1))!=RT_ERR_OK)\n                    return retVal2;\n            }\n\n            if(retVal != RT_ERR_OK)\n                return retVal;\n\n            *pSignalDetect = (regValue & 0x0100) ? 1 : 0;\n            *pSync = (regValue & 0x0001) ? 1 : 0;\n            *pLink = (regValue & 0x0010) ? 1 : 0;\n        }\n        else\n            return RT_ERR_PORT_ID;\n    }\n    else if(type == 1)\n    {\n        if (1 == ext_id)\n        {\n            if ((retVal = rtl8367c_setAsicReg(0x6601, 0x003D))!=RT_ERR_OK)\n                return retVal;\n            if ((retVal = rtl8367c_setAsicReg(0x6600, 0x0081))!=RT_ERR_OK)\n                return retVal;\n            if ((retVal = rtl8367c_getAsicReg(0x6602, &regValue))!=RT_ERR_OK)\n                return retVal;\n\n            *pSignalDetect = (regValue & 0x0100) ? 1 : 0;\n            *pSync = (regValue & 0x0001) ? 1 : 0;\n            *pLink = (regValue & 0x0010) ? 1 : 0;\n        }\n        else if (2 == ext_id)\n        {\n            if ((retVal = rtl8367c_setAsicReg(0x6601, 0x003D))!=RT_ERR_OK)\n                return retVal;\n            if ((retVal = rtl8367c_setAsicReg(0x6600, 0x0080))!=RT_ERR_OK)\n                return retVal;\n            if ((retVal = rtl8367c_getAsicReg(0x6602, &regValue))!=RT_ERR_OK)\n                return retVal;\n\n            *pSignalDetect = (regValue & 0x0100) ? 1 : 0;\n            *pSync = (regValue & 0x0001) ? 1 : 0;\n            *pLink = (regValue & 0x0010) ? 1 : 0;\n        }\n        else\n            return RT_ERR_PORT_ID;\n    }\n    else if(type == 2)\n    {\n        if((retVal = rtl8367c_getAsicSdsReg(0, 30, 1, &regValue)) != RT_ERR_OK)\n            return retVal;\n        if((retVal = rtl8367c_getAsicSdsReg(0, 30, 1, &regValue)) != RT_ERR_OK)\n            return retVal;\n\n        *pSignalDetect = (regValue & 0x0100) ? 1 : 0;\n        *pSync = (regValue & 0x0001) ? 1 : 0;\n        *pLink = (regValue & 0x0010) ? 1 : 0;\n\n    }\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtl8367c_setSgmiiNway\n * Description:\n *      Set SGMII Nway\n * Input:\n *      ext_id      - EXT ID\n *      state       - SGMII Nway state\n * Output:\n *      None.\n * Return:\n *      RT_ERR_OK                   - Success\n *      RT_ERR_SMI                  - SMI access error\n * Note:\n *      None.\n */\nret_t rtl8367c_setSgmiiNway(rtk_uint32 ext_id, rtk_uint32 state)\n{\n    rtk_uint32 retVal, regValue, type, running = 0, retVal2;\n\n    if((retVal = rtl8367c_setAsicReg(0x13C2, 0x0249)) != RT_ERR_OK)\n        return retVal;\n\n    if((retVal = rtl8367c_getAsicReg(0x1300, &regValue)) != RT_ERR_OK)\n        return retVal;\n\n    if((retVal = rtl8367c_setAsicReg(0x13C2, 0x0000)) != RT_ERR_OK)\n        return retVal;\n\n    switch (regValue)\n    {\n        case 0x0276:\n        case 0x0597:\n        case 0x6367:\n            type = 0;\n            break;\n        case 0x0652:\n        case 0x6368:\n            type = 1;\n            break;\n        case 0x0801:\n        case 0x6511:\n            type = 2;\n            break;\n        default:\n            return RT_ERR_FAILED;\n    }\n\n    if(type == 0)\n    {\n        if (1 == ext_id)\n        {\n            if ((retVal = rtl8367c_getAsicRegBit(0x130c, 5, &running))!=RT_ERR_OK)\n                return retVal;\n\n            if(running == 1)\n            {\n                if ((retVal = rtl8367c_setAsicRegBit(0x130c, 5, 0))!=RT_ERR_OK)\n                    return retVal;\n            }\n\n            retVal = rtl8367c_setAsicReg(0x6601, 0x0002);\n\n            if(retVal == RT_ERR_OK)\n                retVal = rtl8367c_setAsicReg(0x6600, 0x0080);\n\n            if(retVal == RT_ERR_OK)\n                retVal = rtl8367c_getAsicReg(0x6602, &regValue);\n\n            if(retVal == RT_ERR_OK)\n            {\n                if(state)\n                      regValue |= 0x0200;\n                else\n                      regValue &= ~0x0200;\n\n                regValue |= 0x0100;\n            }\n\n            if(retVal == RT_ERR_OK)\n                retVal = rtl8367c_setAsicReg(0x6602, regValue);\n\n            if(retVal == RT_ERR_OK)\n                retVal = rtl8367c_setAsicReg(0x6601, 0x0002);\n\n            if(retVal == RT_ERR_OK)\n                retVal = rtl8367c_setAsicReg(0x6600, 0x00C0);\n\n            if(running == 1)\n            {\n                if ((retVal2 = rtl8367c_setAsicRegBit(0x130c, 5, 1))!=RT_ERR_OK)\n                    return retVal2;\n            }\n\n            if(retVal != RT_ERR_OK)\n                return retVal;\n        }\n        else\n            return RT_ERR_PORT_ID;\n    }\n    else if(type == 1)\n    {\n        if (1 == ext_id)\n        {\n            if ((retVal = rtl8367c_setAsicReg(0x6601, 0x0002))!=RT_ERR_OK)\n                   return retVal;\n            if ((retVal = rtl8367c_setAsicReg(0x6600, 0x0081))!=RT_ERR_OK)\n                   return retVal;\n            if ((retVal = rtl8367c_getAsicReg(0x6602, &regValue))!=RT_ERR_OK)\n                   return retVal;\n\n            if(state)\n                  regValue |= 0x0200;\n            else\n                  regValue &= ~0x0200;\n\n            regValue |= 0x0100;\n\n            if ((retVal = rtl8367c_setAsicReg(0x6602, regValue))!=RT_ERR_OK)\n                   return retVal;\n            if ((retVal = rtl8367c_setAsicReg(0x6601, 0x0002))!=RT_ERR_OK)\n                   return retVal;\n            if ((retVal = rtl8367c_setAsicReg(0x6600, 0x00C1))!=RT_ERR_OK)\n                   return retVal;\n        }\n        else if (2 == ext_id)\n        {\n            if ((retVal = rtl8367c_setAsicReg(0x6601, 0x0002))!=RT_ERR_OK)\n                return retVal;\n            if ((retVal = rtl8367c_setAsicReg(0x6600, 0x0080))!=RT_ERR_OK)\n                return retVal;\n            if ((retVal = rtl8367c_getAsicReg(0x6602, &regValue))!=RT_ERR_OK)\n                return retVal;\n\n            if(state)\n                regValue |= 0x0200;\n            else\n                regValue &= ~0x0200;\n\n            regValue |= 0x0100;\n\n            if ((retVal = rtl8367c_setAsicReg(0x6602, regValue))!=RT_ERR_OK)\n                return retVal;\n            if ((retVal = rtl8367c_setAsicReg(0x6601, 0x0002))!=RT_ERR_OK)\n                return retVal;\n            if ((retVal = rtl8367c_setAsicReg(0x6600, 0x00C0))!=RT_ERR_OK)\n                return retVal;\n        }\n        else\n            return RT_ERR_PORT_ID;\n    }\n    else if(type == 2)\n    {\n        if ((retVal = rtl8367c_getAsicSdsReg(0, 2, 0, &regValue))!=RT_ERR_OK)\n            return retVal;\n\n        if(state & 1)\n            regValue &= ~0x100;\n        else\n            regValue |= 0x100;\n\n        if ((retVal = rtl8367c_setAsicSdsReg(0, 2, 0, regValue))!=RT_ERR_OK)\n            return retVal;\n    }\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtl8367c_getSgmiiNway\n * Description:\n *      Get SGMII Nway\n * Input:\n *      ext_id      - EXT ID\n *      state       - SGMII Nway state\n * Output:\n *      None.\n * Return:\n *      RT_ERR_OK                   - Success\n *      RT_ERR_SMI                  - SMI access error\n * Note:\n *      None.\n */\nret_t rtl8367c_getSgmiiNway(rtk_uint32 ext_id, rtk_uint32 *pState)\n{\n    rtk_uint32 retVal, regValue, type, running = 0, retVal2;\n\n    if((retVal = rtl8367c_setAsicReg(0x13C2, 0x0249)) != RT_ERR_OK)\n        return retVal;\n\n    if((retVal = rtl8367c_getAsicReg(0x1300, &regValue)) != RT_ERR_OK)\n        return retVal;\n\n    if((retVal = rtl8367c_setAsicReg(0x13C2, 0x0000)) != RT_ERR_OK)\n        return retVal;\n\n    switch (regValue)\n    {\n        case 0x0276:\n        case 0x0597:\n        case 0x6367:\n            type = 0;\n            break;\n        case 0x0652:\n        case 0x6368:\n            type = 1;\n            break;\n        case 0x0801:\n        case 0x6511:\n            type = 2;\n            break;\n        default:\n            return RT_ERR_FAILED;\n    }\n\n    if(type == 0)\n    {\n        if (1 == ext_id)\n        {\n            if ((retVal = rtl8367c_getAsicRegBit(0x130c, 5, &running))!=RT_ERR_OK)\n                return retVal;\n\n            if(running == 1)\n            {\n                if ((retVal = rtl8367c_setAsicRegBit(0x130c, 5, 0))!=RT_ERR_OK)\n                    return retVal;\n            }\n\n            retVal = rtl8367c_setAsicReg(0x6601, 0x0002);\n\n            if(retVal == RT_ERR_OK)\n                retVal = rtl8367c_setAsicReg(0x6600, 0x0080);\n\n            if(retVal == RT_ERR_OK)\n                retVal = rtl8367c_getAsicReg(0x6602, &regValue);\n\n            if(running == 1)\n            {\n                if ((retVal2 = rtl8367c_setAsicRegBit(0x130c, 5, 1))!=RT_ERR_OK)\n                    return retVal2;\n            }\n\n            if(retVal != RT_ERR_OK)\n                return retVal;\n\n            if(regValue & 0x0200)\n                *pState = 1;\n            else\n                *pState = 0;\n        }\n        else\n            return RT_ERR_PORT_ID;\n    }\n    else if(type == 1)\n    {\n        if (1 == ext_id)\n        {\n                if ((retVal = rtl8367c_setAsicReg(0x6601, 0x0002))!=RT_ERR_OK)\n                    return retVal;\n                if ((retVal = rtl8367c_setAsicReg(0x6600, 0x0081))!=RT_ERR_OK)\n                    return retVal;\n                if ((retVal = rtl8367c_getAsicReg(0x6602, &regValue))!=RT_ERR_OK)\n                    return retVal;\n\n                if(regValue & 0x0200)\n                    *pState = 1;\n                else\n                    *pState = 0;\n        }\n        else if (2 == ext_id)\n        {\n            if ((retVal = rtl8367c_setAsicReg(0x6601, 0x0002))!=RT_ERR_OK)\n                return retVal;\n            if ((retVal = rtl8367c_setAsicReg(0x6600, 0x0080))!=RT_ERR_OK)\n                return retVal;\n            if ((retVal = rtl8367c_getAsicReg(0x6602, &regValue))!=RT_ERR_OK)\n                return retVal;\n\n            if(regValue & 0x0200)\n                *pState = 1;\n            else\n                *pState = 0;\n        }\n        else\n            return RT_ERR_PORT_ID;\n    }\n    else if(type == 2)\n    {\n        if ((retVal = rtl8367c_getAsicSdsReg(0, 2, 0, &regValue))!=RT_ERR_OK)\n            return retVal;\n\n        if(regValue & 0x100)\n            *pState = 0;\n        else\n            *pState = 1;\n    }\n\n    return RT_ERR_OK;\n}\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_portIsolation.c",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * $Revision: 76306 $\n * $Date: 2017-03-08 15:13:58 +0800 (週三, 08 三月 2017) $\n *\n * Purpose : RTL8367C switch high-level API for RTL8367C\n * Feature : Port isolation related functions\n *\n */\n\n#include <rtl8367c_asicdrv_portIsolation.h>\n/* Function Name:\n *      rtl8367c_setAsicPortIsolationPermittedPortmask\n * Description:\n *      Set permitted port isolation portmask\n * Input:\n *      port            - Physical port number (0~10)\n *      permitPortmask  - port mask\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number\n *      RT_ERR_PORT_MASK    - Invalid portmask\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicPortIsolationPermittedPortmask(rtk_uint32 port, rtk_uint32 permitPortmask)\n{\n    if(port >= RTL8367C_PORTNO)\n        return RT_ERR_PORT_ID;\n\n    if( permitPortmask > RTL8367C_PORTMASK)\n        return RT_ERR_PORT_MASK;\n\n    return rtl8367c_setAsicReg(RTL8367C_PORT_ISOLATION_PORT_MASK_REG(port), permitPortmask);\n}\n/* Function Name:\n *      rtl8367c_getAsicPortIsolationPermittedPortmask\n * Description:\n *      Get permitted port isolation portmask\n * Input:\n *      port                - Physical port number (0~10)\n *      pPermitPortmask     - port mask\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicPortIsolationPermittedPortmask(rtk_uint32 port, rtk_uint32 *pPermitPortmask)\n{\n    if(port >= RTL8367C_PORTNO)\n        return RT_ERR_PORT_ID;\n\n    return rtl8367c_getAsicReg(RTL8367C_PORT_ISOLATION_PORT_MASK_REG(port), pPermitPortmask);\n}\n/* Function Name:\n *      rtl8367c_setAsicPortIsolationEfid\n * Description:\n *      Set port isolation EFID\n * Input:\n *      port    - Physical port number (0~10)\n *      efid    - EFID (0~7)\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number\n *      RT_ERR_OUT_OF_RANGE - Input parameter out of range\n * Note:\n *      EFID is used in individual learning in filtering database\n */\nret_t rtl8367c_setAsicPortIsolationEfid(rtk_uint32 port, rtk_uint32 efid)\n{\n    if(port >= RTL8367C_PORTNO)\n        return RT_ERR_PORT_ID;\n\n    if( efid > RTL8367C_EFIDMAX)\n        return RT_ERR_OUT_OF_RANGE;\n\n    return rtl8367c_setAsicRegBits(RTL8367C_PORT_EFID_REG(port), RTL8367C_PORT_EFID_MASK(port), efid);\n}\n/* Function Name:\n *      rtl8367c_getAsicPortIsolationEfid\n * Description:\n *      Get port isolation EFID\n * Input:\n *      port    - Physical port number (0~10)\n *      pEfid   - EFID (0~7)\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicPortIsolationEfid(rtk_uint32 port, rtk_uint32 *pEfid)\n{\n    if(port >= RTL8367C_PORTNO)\n        return RT_ERR_PORT_ID;\n\n    return rtl8367c_getAsicRegBits(RTL8367C_PORT_EFID_REG(port), RTL8367C_PORT_EFID_MASK(port), pEfid);\n}\n\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_qos.c",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * $Revision: 76306 $\n * $Date: 2017-03-08 15:13:58 +0800 (週三, 08 三月 2017) $\n *\n * Purpose : RTL8367C switch high-level API for RTL8367C\n * Feature : Qos related functions\n *\n */\n\n#include <rtl8367c_asicdrv_qos.h>\n/* Function Name:\n *      rtl8367c_setAsicPriorityDot1qRemapping\n * Description:\n *      Set 802.1Q absolutely priority\n * Input:\n *      srcpriority - Priority value\n *      priority     - Absolute priority value\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK                 - Success\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_QOS_INT_PRIORITY    - Invalid priority\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicPriorityDot1qRemapping(rtk_uint32 srcpriority, rtk_uint32 priority )\n{\n    if((srcpriority > RTL8367C_PRIMAX) || (priority > RTL8367C_PRIMAX))\n        return RT_ERR_QOS_INT_PRIORITY;\n\n    return rtl8367c_setAsicRegBits(RTL8367C_QOS_1Q_PRIORITY_REMAPPING_REG(srcpriority), RTL8367C_QOS_1Q_PRIORITY_REMAPPING_MASK(srcpriority),priority);\n}\n/* Function Name:\n *      rtl8367c_getAsicPriorityDot1qRemapping\n * Description:\n *      Get 802.1Q absolutely priority\n * Input:\n *      srcpriority - Priority value\n *      pPriority     - Absolute priority value\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK     - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicPriorityDot1qRemapping(rtk_uint32 srcpriority, rtk_uint32 *pPriority )\n{\n    if(srcpriority > RTL8367C_PRIMAX )\n        return RT_ERR_QOS_INT_PRIORITY;\n\n    return rtl8367c_getAsicRegBits(RTL8367C_QOS_1Q_PRIORITY_REMAPPING_REG(srcpriority), RTL8367C_QOS_1Q_PRIORITY_REMAPPING_MASK(srcpriority), pPriority);\n}\n/* Function Name:\n *      rtl8367c_setAsicPriorityPortBased\n * Description:\n *      Set port based priority\n * Input:\n *      port         - Physical port number (0~7)\n *      priority     - Priority value\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK                 - Success\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_PORT_ID          - Invalid port number\n *      RT_ERR_QOS_INT_PRIORITY    - Invalid priority\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicPriorityPortBased(rtk_uint32 port, rtk_uint32 priority )\n{\n    ret_t retVal;\n\n    if(port > RTL8367C_PORTIDMAX)\n        return RT_ERR_PORT_ID;\n\n    if(priority > RTL8367C_PRIMAX )\n        return RT_ERR_QOS_INT_PRIORITY;\n\n    if(port < 8)\n    {\n        retVal = rtl8367c_setAsicRegBits(RTL8367C_QOS_PORTBASED_PRIORITY_REG(port), RTL8367C_QOS_PORTBASED_PRIORITY_MASK(port), priority);\n        if(retVal != RT_ERR_OK)\n            return retVal;\n    }\n    else\n    {\n        retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_QOS_PORTBASED_PRIORITY_CTRL2, 0x7 << ((port - 8) << 2), priority);\n        if(retVal != RT_ERR_OK)\n            return retVal;\n    }\n\n    return RT_ERR_OK;\n}\n/* Function Name:\n *      rtl8367c_getAsicPriorityPortBased\n * Description:\n *      Get port based priority\n * Input:\n *      port         - Physical port number (0~7)\n *      pPriority     - Priority value\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK         - Success\n *      RT_ERR_SMI      - SMI access error\n *      RT_ERR_PORT_ID  - Invalid port number\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicPriorityPortBased(rtk_uint32 port, rtk_uint32 *pPriority )\n{\n    ret_t retVal;\n\n    if(port > RTL8367C_PORTIDMAX)\n        return RT_ERR_PORT_ID;\n\n    if(port < 8)\n    {\n        retVal = rtl8367c_getAsicRegBits(RTL8367C_QOS_PORTBASED_PRIORITY_REG(port), RTL8367C_QOS_PORTBASED_PRIORITY_MASK(port), pPriority);\n        if(retVal != RT_ERR_OK)\n            return retVal;\n    }\n    else\n    {\n        retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_QOS_PORTBASED_PRIORITY_CTRL2, 0x7 << ((port - 8) << 2), pPriority);\n        if(retVal != RT_ERR_OK)\n            return retVal;\n    }\n\n    return RT_ERR_OK;\n}\n/* Function Name:\n *      rtl8367c_setAsicPriorityDscpBased\n * Description:\n *      Set DSCP-based priority\n * Input:\n *      dscp         - DSCP value\n *      priority     - Priority value\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK                 - Success\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_QOS_DSCP_VALUE    - Invalid DSCP value\n *      RT_ERR_QOS_INT_PRIORITY    - Invalid priority\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicPriorityDscpBased(rtk_uint32 dscp, rtk_uint32 priority )\n{\n    if(priority > RTL8367C_PRIMAX )\n        return RT_ERR_QOS_INT_PRIORITY;\n\n    if(dscp > RTL8367C_DSCPMAX)\n        return RT_ERR_QOS_DSCP_VALUE;\n\n    return rtl8367c_setAsicRegBits(RTL8367C_QOS_DSCP_TO_PRIORITY_REG(dscp), RTL8367C_QOS_DSCP_TO_PRIORITY_MASK(dscp), priority);\n}\n/* Function Name:\n *      rtl8367c_getAsicPriorityDscpBased\n * Description:\n *      Get DSCP-based priority\n * Input:\n *      dscp         - DSCP value\n *      pPriority     - Priority value\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK                 - Success\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_QOS_INT_PRIORITY    - Invalid priority\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicPriorityDscpBased(rtk_uint32 dscp, rtk_uint32 *pPriority )\n{\n    if(dscp > RTL8367C_DSCPMAX)\n        return RT_ERR_QOS_DSCP_VALUE;\n\n    return rtl8367c_getAsicRegBits(RTL8367C_QOS_DSCP_TO_PRIORITY_REG(dscp), RTL8367C_QOS_DSCP_TO_PRIORITY_MASK(dscp), pPriority);\n}\n/* Function Name:\n *      rtl8367c_setAsicPriorityDecision\n * Description:\n *      Set priority decision table\n * Input:\n *      prisrc         - Priority decision source\n *      decisionPri - Decision priority assignment\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK                     - Success\n *      RT_ERR_SMI                  - SMI access error\n *      RT_ERR_QOS_INT_PRIORITY        - Invalid priority\n *      RT_ERR_QOS_SEL_PRI_SOURCE    - Invalid priority decision source parameter\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicPriorityDecision(rtk_uint32 index, rtk_uint32 prisrc, rtk_uint32 decisionPri)\n{\n    ret_t retVal;\n\n    if(index >= PRIDEC_IDX_END )\n        return RT_ERR_ENTRY_INDEX;\n\n    if(prisrc >= PRIDEC_END )\n        return RT_ERR_QOS_SEL_PRI_SOURCE;\n\n    if(decisionPri > RTL8367C_DECISIONPRIMAX )\n        return RT_ERR_QOS_INT_PRIORITY;\n\n    switch(index)\n    {\n        case PRIDEC_IDX0:\n            if((retVal = rtl8367c_setAsicRegBits(RTL8367C_QOS_INTERNAL_PRIORITY_DECISION_REG(prisrc), RTL8367C_QOS_INTERNAL_PRIORITY_DECISION_MASK(prisrc), decisionPri))!=  RT_ERR_OK)\n                return retVal;\n            break;\n        case PRIDEC_IDX1:\n            if((retVal = rtl8367c_setAsicRegBits(RTL8367C_QOS_INTERNAL_PRIORITY_DECISION2_REG(prisrc), RTL8367C_QOS_INTERNAL_PRIORITY_DECISION2_MASK(prisrc), decisionPri))!=  RT_ERR_OK)\n                return retVal;\n            break;\n        default:\n            break;\n    };\n\n    return RT_ERR_OK;\n\n\n}\n\n/* Function Name:\n *      rtl8367c_getAsicPriorityDecision\n * Description:\n *      Get priority decision table\n * Input:\n *      prisrc         - Priority decision source\n *      pDecisionPri - Decision priority assignment\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK                     - Success\n *      RT_ERR_SMI                  - SMI access error\n *      RT_ERR_QOS_SEL_PRI_SOURCE    - Invalid priority decision source parameter\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicPriorityDecision(rtk_uint32 index, rtk_uint32 prisrc, rtk_uint32* pDecisionPri)\n{\n    ret_t retVal;\n\n    if(index >= PRIDEC_IDX_END )\n        return RT_ERR_ENTRY_INDEX;\n\n    if(prisrc >= PRIDEC_END )\n        return RT_ERR_QOS_SEL_PRI_SOURCE;\n\n    switch(index)\n    {\n        case PRIDEC_IDX0:\n            if((retVal = rtl8367c_getAsicRegBits(RTL8367C_QOS_INTERNAL_PRIORITY_DECISION_REG(prisrc), RTL8367C_QOS_INTERNAL_PRIORITY_DECISION_MASK(prisrc), pDecisionPri))!=  RT_ERR_OK)\n                return retVal;\n            break;\n        case PRIDEC_IDX1:\n            if((retVal = rtl8367c_getAsicRegBits(RTL8367C_QOS_INTERNAL_PRIORITY_DECISION2_REG(prisrc), RTL8367C_QOS_INTERNAL_PRIORITY_DECISION2_MASK(prisrc), pDecisionPri))!=  RT_ERR_OK)\n                return retVal;\n            break;\n        default:\n            break;\n    };\n\n    return RT_ERR_OK;\n\n}\n\n/* Function Name:\n *      rtl8367c_setAsicPortPriorityDecisionIndex\n * Description:\n *      Set priority decision index for each port\n * Input:\n *      port     - Physical port number (0~7)\n *      index     - Table index\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK             - Success\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number\n *      RT_ERR_QUEUE_NUM      - Invalid queue number\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicPortPriorityDecisionIndex(rtk_uint32 port, rtk_uint32 index )\n{\n    if(port > RTL8367C_PORTIDMAX)\n        return RT_ERR_PORT_ID;\n\n    if(index >= PRIDEC_IDX_END)\n        return RT_ERR_ENTRY_INDEX;\n\n    return rtl8367c_setAsicRegBit(RTL8367C_QOS_INTERNAL_PRIORITY_DECISION_IDX_CTRL, port, index);\n}\n/* Function Name:\n *      rtl8367c_getAsicPortPriorityDecisionIndex\n * Description:\n *      Get priority decision index  for each port\n * Input:\n *      port     - Physical port number (0~7)\n *      pIndex     - Table index\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK             - Success\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicPortPriorityDecisionIndex(rtk_uint32 port, rtk_uint32 *pIndex )\n{\n    if(port > RTL8367C_PORTIDMAX)\n        return RT_ERR_PORT_ID;\n\n    return rtl8367c_getAsicRegBit(RTL8367C_QOS_INTERNAL_PRIORITY_DECISION_IDX_CTRL, port, pIndex);\n}\n\n/* Function Name:\n *      rtl8367c_setAsicOutputQueueMappingIndex\n * Description:\n *      Set output queue number for each port\n * Input:\n *      port     - Physical port number (0~7)\n *      index     - Mapping table index\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK             - Success\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number\n *      RT_ERR_QUEUE_NUM      - Invalid queue number\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicOutputQueueMappingIndex(rtk_uint32 port, rtk_uint32 index )\n{\n    if(port > RTL8367C_PORTIDMAX)\n        return RT_ERR_PORT_ID;\n\n    if(index >= RTL8367C_QUEUENO)\n        return RT_ERR_QUEUE_NUM;\n\n    return rtl8367c_setAsicRegBits(RTL8367C_QOS_PORT_QUEUE_NUMBER_REG(port), RTL8367C_QOS_PORT_QUEUE_NUMBER_MASK(port), index);\n}\n/* Function Name:\n *      rtl8367c_getAsicOutputQueueMappingIndex\n * Description:\n *      Get output queue number for each port\n * Input:\n *      port     - Physical port number (0~7)\n *      pIndex     - Mapping table index\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK             - Success\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicOutputQueueMappingIndex(rtk_uint32 port, rtk_uint32 *pIndex )\n{\n    if(port > RTL8367C_PORTIDMAX)\n        return RT_ERR_PORT_ID;\n\n    return rtl8367c_getAsicRegBits(RTL8367C_QOS_PORT_QUEUE_NUMBER_REG(port), RTL8367C_QOS_PORT_QUEUE_NUMBER_MASK(port), pIndex);\n}\n/* Function Name:\n *      rtl8367c_setAsicPriorityToQIDMappingTable\n * Description:\n *      Set priority to QID mapping table parameters\n * Input:\n *      index         - Mapping table index\n *      priority     - The priority value\n *      qid         - Queue id\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK                 - Success\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_QUEUE_ID          - Invalid queue id\n *      RT_ERR_QUEUE_NUM          - Invalid queue number\n *      RT_ERR_QOS_INT_PRIORITY - Invalid priority\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicPriorityToQIDMappingTable(rtk_uint32 index, rtk_uint32 priority, rtk_uint32 qid )\n{\n    if(index >= RTL8367C_QUEUENO)\n        return RT_ERR_QUEUE_NUM;\n\n    if(priority > RTL8367C_PRIMAX)\n        return RT_ERR_QOS_INT_PRIORITY;\n\n    if(qid > RTL8367C_QIDMAX)\n        return RT_ERR_QUEUE_ID;\n\n    return rtl8367c_setAsicRegBits(RTL8367C_QOS_1Q_PRIORITY_TO_QID_REG(index, priority), RTL8367C_QOS_1Q_PRIORITY_TO_QID_MASK(priority), qid);\n}\n/* Function Name:\n *      rtl8367c_getAsicPriorityToQIDMappingTable\n * Description:\n *      Get priority to QID mapping table parameters\n * Input:\n *      index         - Mapping table index\n *      priority     - The priority value\n *      pQid         - Queue id\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK                 - Success\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_QUEUE_NUM          - Invalid queue number\n *      RT_ERR_QOS_INT_PRIORITY - Invalid priority\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicPriorityToQIDMappingTable(rtk_uint32 index, rtk_uint32 priority, rtk_uint32* pQid)\n{\n    if(index >= RTL8367C_QUEUENO)\n        return RT_ERR_QUEUE_NUM;\n\n    if(priority > RTL8367C_PRIMAX)\n        return RT_ERR_QOS_INT_PRIORITY;\n\n    return rtl8367c_getAsicRegBits(RTL8367C_QOS_1Q_PRIORITY_TO_QID_REG(index, priority), RTL8367C_QOS_1Q_PRIORITY_TO_QID_MASK(priority), pQid);\n}\n/* Function Name:\n *      rtl8367c_setAsicRemarkingDot1pAbility\n * Description:\n *      Set 802.1p remarking ability\n * Input:\n *      port     - Physical port number (0~7)\n *      enabled - 1: enabled, 0: disabled\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK             - Success\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicRemarkingDot1pAbility(rtk_uint32 port, rtk_uint32 enabled)\n{\n    return rtl8367c_setAsicRegBit(RTL8367C_PORT_MISC_CFG_REG(port), RTL8367C_1QREMARK_ENABLE_OFFSET, enabled);\n}\n/* Function Name:\n *      rtl8367c_getAsicRemarkingDot1pAbility\n * Description:\n *      Get 802.1p remarking ability\n * Input:\n *      port     - Physical port number (0~7)\n *      pEnabled - 1: enabled, 0: disabled\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK     - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicRemarkingDot1pAbility(rtk_uint32 port, rtk_uint32* pEnabled)\n{\n    return rtl8367c_getAsicRegBit(RTL8367C_PORT_MISC_CFG_REG(port), RTL8367C_1QREMARK_ENABLE_OFFSET, pEnabled);\n}\n/* Function Name:\n *      rtl8367c_setAsicRemarkingDot1pParameter\n * Description:\n *      Set 802.1p remarking parameter\n * Input:\n *      priority     - Priority value\n *      newPriority - New priority value\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK                 - Success\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_QOS_INT_PRIORITY - Invalid priority\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicRemarkingDot1pParameter(rtk_uint32 priority, rtk_uint32 newPriority )\n{\n    if(priority > RTL8367C_PRIMAX || newPriority > RTL8367C_PRIMAX)\n        return RT_ERR_QOS_INT_PRIORITY;\n\n    return rtl8367c_setAsicRegBits(RTL8367C_QOS_1Q_REMARK_REG(priority), RTL8367C_QOS_1Q_REMARK_MASK(priority), newPriority);\n}\n/* Function Name:\n *      rtl8367c_getAsicRemarkingDot1pParameter\n * Description:\n *      Get 802.1p remarking parameter\n * Input:\n *      priority     - Priority value\n *      pNewPriority - New priority value\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK                 - Success\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_QOS_INT_PRIORITY - Invalid priority\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicRemarkingDot1pParameter(rtk_uint32 priority, rtk_uint32 *pNewPriority )\n{\n    if(priority > RTL8367C_PRIMAX )\n        return RT_ERR_QOS_INT_PRIORITY;\n\n    return rtl8367c_getAsicRegBits(RTL8367C_QOS_1Q_REMARK_REG(priority), RTL8367C_QOS_1Q_REMARK_MASK(priority), pNewPriority);\n}\n\n/* Function Name:\n *      rtl8367c_setAsicRemarkingDot1pSrc\n * Description:\n *      Set remarking source of 802.1p remarking.\n * Input:\n *      type      - remarking source\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n *      RT_ERR_NOT_INIT         - The module is not initial\n *      RT_ERR_PORT_ID  - invalid port id\n *      RT_ERR_INPUT            - invalid input parameter\n\n * Note:\n *      The API can configure 802.1p remark functionality to map original DSCP value or internal\n *      priority to TX DSCP value.\n */\nret_t rtl8367c_setAsicRemarkingDot1pSrc(rtk_uint32 type)\n{\n\n    if(type >= DOT1P_PRISEL_END )\n        return RT_ERR_QOS_SEL_PRI_SOURCE;\n\n    return rtl8367c_setAsicRegBit(RTL8367C_REG_RMK_CFG_SEL_CTRL, RTL8367C_RMK_1Q_CFG_SEL_OFFSET, type);\n}\n\n\n/* Function Name:\n *      rtl8367c_getAsicRemarkingDot1pSrc\n * Description:\n *      Get remarking source of 802.1p remarking.\n * Output:\n *      pType      - remarking source\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n *      RT_ERR_NOT_INIT         - The module is not initial\n *      RT_ERR_PORT_ID          - invalid port id\n *      RT_ERR_INPUT            - invalid input parameter\n *      RT_ERR_NULL_POINTER     - input parameter may be null pointer\n\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicRemarkingDot1pSrc(rtk_uint32 *pType)\n{\n    return rtl8367c_getAsicRegBit(RTL8367C_REG_RMK_CFG_SEL_CTRL, RTL8367C_RMK_1Q_CFG_SEL_OFFSET, pType);\n}\n\n\n\n\n\n/* Function Name:\n *      rtl8367c_setAsicRemarkingDscpAbility\n * Description:\n *      Set DSCP remarking ability\n * Input:\n *      enabled     - 1: enabled, 0: disabled\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK     - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicRemarkingDscpAbility(rtk_uint32 enabled)\n{\n    return rtl8367c_setAsicRegBit(RTL8367C_REMARKING_CTRL_REG, RTL8367C_REMARKING_DSCP_ENABLE_OFFSET, enabled);\n}\n/* Function Name:\n *      rtl8367c_getAsicRemarkingDscpAbility\n * Description:\n *      Get DSCP remarking ability\n * Input:\n *      enabled     - 1: enabled, 0: disabled\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK     - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicRemarkingDscpAbility(rtk_uint32* pEnabled)\n{\n    return rtl8367c_getAsicRegBit(RTL8367C_REMARKING_CTRL_REG, RTL8367C_REMARKING_DSCP_ENABLE_OFFSET, pEnabled);\n}\n/* Function Name:\n *      rtl8367c_setAsicRemarkingDscpParameter\n * Description:\n *      Set DSCP remarking parameter\n * Input:\n *      priority     - Priority value\n *      newDscp     - New DSCP value\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK                 - Success\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_QOS_DSCP_VALUE    - Invalid DSCP value\n *      RT_ERR_QOS_INT_PRIORITY    - Invalid priority\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicRemarkingDscpParameter(rtk_uint32 priority, rtk_uint32 newDscp )\n{\n    if(priority > RTL8367C_PRIMAX )\n        return RT_ERR_QOS_INT_PRIORITY;\n\n    if(newDscp > RTL8367C_DSCPMAX)\n        return RT_ERR_QOS_DSCP_VALUE;\n\n    return rtl8367c_setAsicRegBits(RTL8367C_QOS_DSCP_REMARK_REG(priority), RTL8367C_QOS_DSCP_REMARK_MASK(priority), newDscp);\n}\n/* Function Name:\n *      rtl8367c_getAsicRemarkingDscpParameter\n * Description:\n *      Get DSCP remarking parameter\n * Input:\n *      priority     - Priority value\n *      pNewDscp     - New DSCP value\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK                 - Success\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_QOS_INT_PRIORITY    - Invalid priority\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicRemarkingDscpParameter(rtk_uint32 priority, rtk_uint32* pNewDscp )\n{\n    if(priority > RTL8367C_PRIMAX )\n        return RT_ERR_QOS_INT_PRIORITY;\n\n    return rtl8367c_getAsicRegBits(RTL8367C_QOS_DSCP_REMARK_REG(priority), RTL8367C_QOS_DSCP_REMARK_MASK(priority), pNewDscp);\n}\n\n/* Function Name:\n *      rtl8367c_setAsicRemarkingDscpSrc\n * Description:\n *      Set remarking source of DSCP remarking.\n * Input:\n *      type      - remarking source\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n *      RT_ERR_NOT_INIT         - The module is not initial\n *      RT_ERR_PORT_ID  - invalid port id\n *      RT_ERR_INPUT            - invalid input parameter\n\n * Note:\n *      The API can configure DSCP remark functionality to map original DSCP value or internal\n *      priority to TX DSCP value.\n */\nret_t rtl8367c_setAsicRemarkingDscpSrc(rtk_uint32 type)\n{\n\n    if(type >= DSCP_PRISEL_END )\n        return RT_ERR_QOS_SEL_PRI_SOURCE;\n\n    return rtl8367c_setAsicRegBits(RTL8367C_REG_RMK_CFG_SEL_CTRL, RTL8367C_RMK_DSCP_CFG_SEL_MASK, type);\n}\n\n\n/* Function Name:\n *      rtl8367c_getAsicRemarkingDscpSrc\n * Description:\n *      Get remarking source of DSCP remarking.\n * Output:\n *      pType      - remarking source\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n *      RT_ERR_NOT_INIT         - The module is not initial\n *      RT_ERR_PORT_ID          - invalid port id\n *      RT_ERR_INPUT            - invalid input parameter\n *      RT_ERR_NULL_POINTER     - input parameter may be null pointer\n\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicRemarkingDscpSrc(rtk_uint32 *pType)\n{\n    return rtl8367c_getAsicRegBits(RTL8367C_REG_RMK_CFG_SEL_CTRL, RTL8367C_RMK_DSCP_CFG_SEL_MASK, pType);\n}\n\n/* Function Name:\n *      rtl8367c_setAsicRemarkingDscp2Dscp\n * Description:\n *      Set DSCP to remarked DSCP mapping.\n * Input:\n *      dscp    - DSCP value\n *      rmkDscp - remarked DSCP value\n * Output:\n *      None.\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n *      RT_ERR_UNIT_ID          - Invalid unit id\n *      RT_ERR_QOS_DSCP_VALUE   - Invalid dscp value\n * Note:\n *      dscp parameter can be DSCP value or internal priority according to configuration of API\n *      dal_apollomp_qos_dscpRemarkSrcSel_set(), because DSCP remark functionality can map original DSCP\n *      value or internal priority to TX DSCP value.\n */\nret_t rtl8367c_setAsicRemarkingDscp2Dscp(rtk_uint32 dscp, rtk_uint32 rmkDscp)\n{\n    if((dscp > RTL8367C_DSCPMAX ) || (rmkDscp > RTL8367C_DSCPMAX))\n        return RT_ERR_QOS_INT_PRIORITY;\n\n    return rtl8367c_setAsicRegBits(RTL8367C_QOS_DSCP_TO_DSCP_REG(dscp), RTL8367C_QOS_DSCP_TO_DSCP_MASK(dscp), rmkDscp);\n}\n\n/* Function Name:\n *      rtl8367c_getAsicRemarkingDscp2Dscp\n * Description:\n *      Get DSCP to remarked DSCP mapping.\n * Input:\n *      dscp    - DSCP value\n * Output:\n *      pRmkDscp   - remarked DSCP value\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n *      RT_ERR_QOS_DSCP_VALUE   - Invalid dscp value\n *      RT_ERR_NULL_POINTER     - NULL pointer\n * Note:\n *      None.\n */\nret_t rtl8367c_getAsicRemarkingDscp2Dscp(rtk_uint32 dscp, rtk_uint32 *pRmkDscp)\n{\n    if(dscp > RTL8367C_DSCPMAX)\n        return RT_ERR_QOS_DSCP_VALUE;\n\n    return rtl8367c_getAsicRegBits(RTL8367C_QOS_DSCP_TO_DSCP_REG(dscp), RTL8367C_QOS_DSCP_TO_DSCP_MASK(dscp), pRmkDscp);\n\n}\n\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_rldp.c",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * $Revision: 42321 $\n * $Date: 2013-08-26 13:51:29 +0800 (週一, 26 八月 2013) $\n *\n * Purpose : RTL8367C switch high-level API for RTL8367C\n * Feature : RLDP related functions\n *\n */\n\n#include <rtl8367c_asicdrv_rldp.h>\n/* Function Name:\n *      rtl8367c_setAsicRldp\n * Description:\n *      Set RLDP function enable/disable\n * Input:\n *      enabled     - 1: enabled, 0: disabled\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicRldp(rtk_uint32 enabled)\n{\n    return rtl8367c_setAsicRegBit(RTL8367C_REG_RLDP_CTRL0, RTL8367C_RLDP_ENABLE_OFFSET, enabled);\n}\n/* Function Name:\n *      rtl8367c_getAsicRldp\n * Description:\n *      Get RLDP function enable/disable\n * Input:\n *      pEnabled    - 1: enabled, 0: disabled\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicRldp(rtk_uint32 *pEnabled)\n{\n    return rtl8367c_getAsicRegBit(RTL8367C_REG_RLDP_CTRL0, RTL8367C_RLDP_ENABLE_OFFSET, pEnabled);\n}\n/* Function Name:\n *      rtl8367c_setAsicRldpEnable8051\n * Description:\n *      Set RLDP function handled by ASIC or 8051\n * Input:\n *      enabled     - 1: enabled 8051, 0: disabled 8051 (RLDP is handled by ASIC)\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicRldpEnable8051(rtk_uint32 enabled)\n{\n    return rtl8367c_setAsicRegBit(RTL8367C_REG_RLDP_CTRL0, RTL8367C_RLDP_8051_ENABLE_OFFSET, enabled);\n}\n/* Function Name:\n *      rtl8367c_setAsicRldrtl8367c_getAsicRldpEnable8051pEnable8051\n * Description:\n *      Get RLDP function handled by ASIC or 8051\n * Input:\n *      pEnabled    - 1: enabled 8051, 0: disabled 8051 (RLDP is handled by ASIC)\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicRldpEnable8051(rtk_uint32 *pEnabled)\n{\n    return rtl8367c_getAsicRegBit(RTL8367C_REG_RLDP_CTRL0, RTL8367C_RLDP_8051_ENABLE_OFFSET, pEnabled);\n}\n/* Function Name:\n *      rtl8367c_setAsicRldpCompareRandomNumber\n * Description:\n *      Set enable compare the random number field and seed field of RLDP frame\n * Input:\n *      enabled     - 1: enabled comparing random number, 0: disabled comparing random number\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicRldpCompareRandomNumber(rtk_uint32 enabled)\n{\n    return rtl8367c_setAsicRegBit(RTL8367C_REG_RLDP_CTRL0, RTL8367C_RLDP_COMP_ID_OFFSET, enabled);\n}\n/* Function Name:\n *      rtl8367c_getAsicRldpCompareRandomNumber\n * Description:\n *      Get enable compare the random number field and seed field of RLDP frame\n * Input:\n *      pEnabled    - 1: enabled comparing random number, 0: disabled comparing random number\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicRldpCompareRandomNumber(rtk_uint32 *pEnabled)\n{\n    return rtl8367c_getAsicRegBit(RTL8367C_REG_RLDP_CTRL0, RTL8367C_RLDP_COMP_ID_OFFSET, pEnabled);\n}\n/* Function Name:\n *      rtl8367c_setAsicRldpIndicatorSource\n * Description:\n *      Set buzzer and LED source when detecting a loop\n * Input:\n *      src     - 0: ASIC, 1: 8051\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicRldpIndicatorSource(rtk_uint32 src)\n{\n    return rtl8367c_setAsicRegBit(RTL8367C_REG_RLDP_CTRL0, RTL8367C_RLDP_INDICATOR_SOURCE_OFFSET, src);\n}\n/* Function Name:\n *      rtl8367c_getAsicRldpIndicatorSource\n * Description:\n *      Get buzzer and LED source when detecting a loop\n * Input:\n *      pSrc    - 0: ASIC, 1: 8051\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicRldpIndicatorSource(rtk_uint32 *pSrc)\n{\n    return rtl8367c_getAsicRegBit(RTL8367C_REG_RLDP_CTRL0, RTL8367C_RLDP_INDICATOR_SOURCE_OFFSET, pSrc);\n}\n/* Function Name:\n *      rtl8367c_setAsicRldpCheckingStatePara\n * Description:\n *      Set retry count and retry period of checking state\n * Input:\n *      retryCount  - 0~0xFF (times)\n *      retryPeriod - 0~0xFFFF (ms)\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_OUT_OF_RANGE - input parameter out of range\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicRldpCheckingStatePara(rtk_uint32 retryCount, rtk_uint32 retryPeriod)\n{\n    ret_t retVal;\n\n    if(retryCount > 0xFF)\n        return RT_ERR_OUT_OF_RANGE;\n    if(retryPeriod > RTL8367C_REGDATAMAX)\n        return RT_ERR_OUT_OF_RANGE;\n\n    retVal = rtl8367c_setAsicRegBits(RTL8367C_RLDP_RETRY_COUNT_REG, RTL8367C_RLDP_RETRY_COUNT_CHKSTATE_MASK, retryCount);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    return rtl8367c_setAsicReg(RTL8367C_RLDP_RETRY_PERIOD_CHKSTATE_REG, retryPeriod);\n}\n/* Function Name:\n *      rtl8367c_getAsicRldpCheckingStatePara\n * Description:\n *      Get retry count and retry period of checking state\n * Input:\n *      pRetryCount     - 0~0xFF (times)\n *      pRetryPeriod    - 0~0xFFFF (ms)\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_OUT_OF_RANGE - input parameter out of range\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicRldpCheckingStatePara(rtk_uint32 *pRetryCount, rtk_uint32 *pRetryPeriod)\n{\n    ret_t retVal;\n\n    retVal = rtl8367c_getAsicRegBits(RTL8367C_RLDP_RETRY_COUNT_REG, RTL8367C_RLDP_RETRY_COUNT_CHKSTATE_MASK, pRetryCount);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    return rtl8367c_getAsicReg(RTL8367C_RLDP_RETRY_PERIOD_CHKSTATE_REG, pRetryPeriod);\n}\n/* Function Name:\n *      rtl8367c_setAsicRldpLoopStatePara\n * Description:\n *      Set retry count and retry period of loop state\n * Input:\n *      retryCount  - 0~0xFF (times)\n *      retryPeriod - 0~0xFFFF (ms)\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_OUT_OF_RANGE - input parameter out of range\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicRldpLoopStatePara(rtk_uint32 retryCount, rtk_uint32 retryPeriod)\n{\n    ret_t retVal;\n\n    if(retryCount > 0xFF)\n        return RT_ERR_OUT_OF_RANGE;\n\n    if(retryPeriod > RTL8367C_REGDATAMAX)\n        return RT_ERR_OUT_OF_RANGE;\n\n    retVal = rtl8367c_setAsicRegBits(RTL8367C_RLDP_RETRY_COUNT_REG, RTL8367C_RLDP_RETRY_COUNT_LOOPSTATE_MASK, retryCount);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    return rtl8367c_setAsicReg(RTL8367C_RLDP_RETRY_PERIOD_LOOPSTATE_REG, retryPeriod);\n}\n/* Function Name:\n *      rtl8367c_getAsicRldpLoopStatePara\n * Description:\n *      Get retry count and retry period of loop state\n * Input:\n *      pRetryCount     - 0~0xFF (times)\n *      pRetryPeriod    - 0~0xFFFF (ms)\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_OUT_OF_RANGE - input parameter out of range\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicRldpLoopStatePara(rtk_uint32 *pRetryCount, rtk_uint32 *pRetryPeriod)\n{\n    ret_t retVal;\n\n    retVal = rtl8367c_getAsicRegBits(RTL8367C_RLDP_RETRY_COUNT_REG, RTL8367C_RLDP_RETRY_COUNT_LOOPSTATE_MASK, pRetryCount);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    return rtl8367c_getAsicReg(RTL8367C_RLDP_RETRY_PERIOD_LOOPSTATE_REG, pRetryPeriod);\n}\n/* Function Name:\n *      rtl8367c_setAsicRldpTxPortmask\n * Description:\n *      Set portmask that send/forward RLDP frame\n * Input:\n *      portmask    - 0~0xFF\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_MASK    - Invalid portmask\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicRldpTxPortmask(rtk_uint32 portmask)\n{\n    if(portmask > RTL8367C_PORTMASK)\n        return RT_ERR_PORT_MASK;\n\n    return rtl8367c_setAsicReg(RTL8367C_RLDP_TX_PMSK_REG, portmask);\n}\n/* Function Name:\n *      rtl8367c_getAsicRldpTxPortmask\n * Description:\n *      Get portmask that send/forward RLDP frame\n * Input:\n *      pPortmask   - 0~0xFF\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicRldpTxPortmask(rtk_uint32 *pPortmask)\n{\n    return rtl8367c_getAsicReg(RTL8367C_RLDP_TX_PMSK_REG, pPortmask);\n}\n/* Function Name:\n *      rtl8367c_setAsicRldpMagicNum\n * Description:\n *      Set Random seed of RLDP\n * Input:\n *      seed    - MAC\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicRldpMagicNum(ether_addr_t seed)\n{\n    ret_t retVal;\n    rtk_uint32 regData;\n    rtk_uint16 *accessPtr;\n    rtk_uint32 i;\n\n    accessPtr = (rtk_uint16*)&seed;\n\n    for (i = 0; i < 3; i++)\n    {\n        regData = *accessPtr;\n        retVal = rtl8367c_setAsicReg(RTL8367C_RLDP_MAGIC_NUM_REG_BASE + i, regData);\n        if(retVal != RT_ERR_OK)\n            return retVal;\n\n        accessPtr++;\n    }\n\n    return retVal;\n}\n/* Function Name:\n *      rtl8367c_getAsicRldpMagicNum\n * Description:\n *      Get Random seed of RLDP\n * Input:\n *      pSeed   - MAC\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicRldpMagicNum(ether_addr_t *pSeed)\n{\n    ret_t retVal;\n    rtk_uint32 regData;\n    rtk_uint16 *accessPtr;\n    rtk_uint32 i;\n\n    accessPtr = (rtk_uint16*)pSeed;\n\n    for(i = 0; i < 3; i++)\n    {\n        retVal = rtl8367c_getAsicReg(RTL8367C_RLDP_MAGIC_NUM_REG_BASE + i, &regData);\n        if(retVal != RT_ERR_OK)\n            return retVal;\n\n        *accessPtr = regData;\n        accessPtr++;\n    }\n\n    return retVal;\n}\n\n/* Function Name:\n *      rtl8367c_getAsicRldpLoopedPortmask\n * Description:\n *      Get looped portmask\n * Input:\n *      pPortmask   - 0~0xFF\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicRldpLoopedPortmask(rtk_uint32 *pPortmask)\n{\n    return rtl8367c_getAsicReg(RTL8367C_RLDP_LOOP_PMSK_REG, pPortmask);\n}\n/* Function Name:\n *      rtl8367c_getAsicRldpRandomNumber\n * Description:\n *      Get Random number of RLDP\n * Input:\n *      pRandNumber     - MAC\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicRldpRandomNumber(ether_addr_t *pRandNumber)\n{\n    ret_t retVal;\n    rtk_uint32 regData;\n    rtk_int16 accessPtr[3];\n    rtk_uint32 i;\n\n    for(i = 0; i < 3; i++)\n    {\n        retVal = rtl8367c_getAsicReg(RTL8367C_RLDP_RAND_NUM_REG_BASE+ i, &regData);\n        if(retVal != RT_ERR_OK)\n            return retVal;\n\n        accessPtr[i] = regData;\n    }\n\n    memcpy(pRandNumber, accessPtr, 6);\n    return retVal;\n}\n/* Function Name:\n *      rtl8367c_getAsicRldpLoopedPortmask\n * Description:\n *      Get port number of looped pair\n * Input:\n *      port        - Physical port number (0~7)\n *      pLoopedPair     - port (0~7)\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n *      RT_ERR_PORT_ID  - Invalid port number\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicRldpLoopedPortPair(rtk_uint32 port, rtk_uint32 *pLoopedPair)\n{\n    if(port > RTL8367C_PORTIDMAX)\n        return RT_ERR_PORT_ID;\n\n    if(port < 8)\n        return rtl8367c_getAsicRegBits(RTL8367C_RLDP_LOOP_PORT_REG(port), RTL8367C_RLDP_LOOP_PORT_MASK(port), pLoopedPair);\n    else\n        return rtl8367c_getAsicRegBits(RTL8367C_REG_RLDP_LOOP_PORT_REG4 + ((port - 8) >> 1), RTL8367C_RLDP_LOOP_PORT_MASK(port), pLoopedPair);\n}\n/* Function Name:\n *      rtl8367c_setAsicRlppTrap8051\n * Description:\n *      Set trap RLPP packet to 8051\n * Input:\n *      enabled     - 1: enabled, 0: disabled\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicRlppTrap8051(rtk_uint32 enabled)\n{\n    return rtl8367c_setAsicRegBit(RTL8367C_REG_RLDP_CTRL0, RTL8367C_RLPP_8051_TRAP_OFFSET, enabled);\n}\n/* Function Name:\n *      rtl8367c_getAsicRlppTrap8051\n * Description:\n *      Get trap RLPP packet to 8051\n * Input:\n *      pEnabled    - 1: enabled, 0: disabled\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicRlppTrap8051(rtk_uint32 *pEnabled)\n{\n    return rtl8367c_getAsicRegBit(RTL8367C_REG_RLDP_CTRL0, RTL8367C_RLPP_8051_TRAP_OFFSET, pEnabled);\n}\n/* Function Name:\n *      rtl8367c_setAsicRldpLeaveLoopedPortmask\n * Description:\n *      Clear leaved looped portmask\n * Input:\n *      portmask    - 0~0xFF\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicRldpLeaveLoopedPortmask(rtk_uint32 portmask)\n{\n    return rtl8367c_setAsicReg(RTL8367C_REG_RLDP_RELEASED_INDICATOR, portmask);\n}\n/* Function Name:\n *      rtl8367c_getAsicRldpLeaveLoopedPortmask\n * Description:\n *      Get leaved looped portmask\n * Input:\n *      pPortmask   - 0~0xFF\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicRldpLeaveLoopedPortmask(rtk_uint32 *pPortmask)\n{\n    return rtl8367c_getAsicReg(RTL8367C_REG_RLDP_RELEASED_INDICATOR, pPortmask);\n}\n/* Function Name:\n *      rtl8367c_setAsicRldpEnterLoopedPortmask\n * Description:\n *      Clear enter loop portmask\n * Input:\n *      portmask    - 0~0xFF\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicRldpEnterLoopedPortmask(rtk_uint32 portmask)\n{\n    return rtl8367c_setAsicReg(RTL8367C_REG_RLDP_LOOPED_INDICATOR, portmask);\n}\n/* Function Name:\n *      rtl8367c_getAsicRldpEnterLoopedPortmask\n * Description:\n *      Get enter loop portmask\n * Input:\n *      pPortmask   - 0~0xFF\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicRldpEnterLoopedPortmask(rtk_uint32 *pPortmask)\n{\n    return rtl8367c_getAsicReg(RTL8367C_REG_RLDP_LOOPED_INDICATOR, pPortmask);\n}\n\n/* Function Name:\n *      rtl8367c_setAsicRldpTriggerMode\n * Description:\n *      Set trigger RLDP mode\n * Input:\n *      mode    - 1: Periodically, 0: SA moving\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicRldpTriggerMode(rtk_uint32 enabled)\n{\n    return rtl8367c_setAsicRegBit(RTL8367C_REG_RLDP_CTRL0, RTL8367C_RLDP_TRIGGER_MODE_OFFSET, enabled);\n}\n/* Function Name:\n *      rtl8367c_getAsicRldpTriggerMode\n * Description:\n *      Get trigger RLDP mode\n * Input:\n *      pMode   - - 1: Periodically, 0: SA moving\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicRldpTriggerMode(rtk_uint32 *pEnabled)\n{\n    return rtl8367c_getAsicRegBit(RTL8367C_REG_RLDP_CTRL0, RTL8367C_RLDP_TRIGGER_MODE_OFFSET, pEnabled);\n}\n\n/* Function Name:\n *      rtl8367c_setAsicRldp8051Portmask\n * Description:\n *      Set 8051/CPU configured looped portmask\n * Input:\n *      portmask    - 0~0xFF\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_MASK    - Invalid portmask\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicRldp8051Portmask(rtk_uint32 portmask)\n{\n    ret_t retVal;\n    if(portmask > RTL8367C_PORTMASK)\n        return RT_ERR_PORT_MASK;\n\n    retVal = rtl8367c_setAsicRegBits(RTL8367C_RLDP_CTRL0_REG,RTL8367C_RLDP_8051_LOOP_PORTMSK_MASK,portmask & 0xff);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_RLDP_CTRL5,RTL8367C_RLDP_CTRL5_MASK,(portmask >> 8) & 7);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n/* Function Name:\n *      rtl8367c_getAsicRldp8051Portmask\n * Description:\n *      Get 8051/CPU configured looped portmask\n * Input:\n *      pPortmask   - 0~0xFF\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicRldp8051Portmask(rtk_uint32 *pPortmask)\n{\n    rtk_uint32 tmpPmsk;\n    ret_t retVal;\n\n    retVal = rtl8367c_getAsicRegBits(RTL8367C_RLDP_CTRL0_REG,RTL8367C_RLDP_8051_LOOP_PORTMSK_MASK,&tmpPmsk);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n    *pPortmask = tmpPmsk & 0xff;\n\n    retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_RLDP_CTRL5,RTL8367C_RLDP_CTRL5_MASK,&tmpPmsk);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n    *pPortmask |= (tmpPmsk & 7) <<8;\n\n    return RT_ERR_OK;\n}\n\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_rma.c",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * $Revision: 64716 $\n * $Date: 2015-12-31 16:31:55 +0800 (週四, 31 十二月 2015) $\n *\n * Purpose : RTL8367C switch high-level API for RTL8367C\n * Feature : RMA related functions\n *\n */\n\n#include <rtl8367c_asicdrv_rma.h>\n/* Function Name:\n *      rtl8367c_setAsicRma\n * Description:\n *      Set reserved multicast address for CPU trapping\n * Input:\n *      index     - reserved multicast LSB byte, 0x00~0x2F is available value\n *      pRmacfg     - type of RMA for trapping frame type setting\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK         - Success\n *      RT_ERR_SMI      - SMI access error\n *      RT_ERR_RMA_ADDR - Invalid RMA address index\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicRma(rtk_uint32 index, rtl8367c_rma_t* pRmacfg)\n{\n    rtk_uint32 regData = 0;\n    ret_t retVal;\n\n    if(index > RTL8367C_RMAMAX)\n        return RT_ERR_RMA_ADDR;\n\n    regData |= (pRmacfg->portiso_leaky & 0x0001);\n    regData |= ((pRmacfg->vlan_leaky & 0x0001) << 1);\n    regData |= ((pRmacfg->keep_format & 0x0001) << 2);\n    regData |= ((pRmacfg->trap_priority & 0x0007) << 3);\n    regData |= ((pRmacfg->discard_storm_filter & 0x0001) << 6);\n    regData |= ((pRmacfg->operation & 0x0003) << 7);\n\n    if( (index >= 0x4 && index <= 0x7) || (index >= 0x9 && index <= 0x0C) || (0x0F == index))\n        index = 0x04;\n    else if((index >= 0x13 && index <= 0x17) || (0x19 == index) || (index >= 0x1B && index <= 0x1f))\n        index = 0x13;\n    else if(index >= 0x22 && index <= 0x2F)\n        index = 0x22;\n\n    retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_RMA_CTRL00, RTL8367C_TRAP_PRIORITY_MASK, pRmacfg->trap_priority);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    return rtl8367c_setAsicReg(RTL8367C_REG_RMA_CTRL00+index, regData);\n}\n/* Function Name:\n *      rtl8367c_getAsicRma\n * Description:\n *      Get reserved multicast address for CPU trapping\n * Input:\n *      index     - reserved multicast LSB byte, 0x00~0x2F is available value\n *      rmacfg     - type of RMA for trapping frame type setting\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK         - Success\n *      RT_ERR_SMI      - SMI access error\n *      RT_ERR_RMA_ADDR - Invalid RMA address index\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicRma(rtk_uint32 index, rtl8367c_rma_t* pRmacfg)\n{\n    ret_t retVal;\n    rtk_uint32 regData;\n\n    if(index > RTL8367C_RMAMAX)\n        return RT_ERR_RMA_ADDR;\n\n    if( (index >= 0x4 && index <= 0x7) || (index >= 0x9 && index <= 0x0C) || (0x0F == index))\n        index = 0x04;\n    else if((index >= 0x13 && index <= 0x17) || (0x19 == index) || (index >= 0x1B && index <= 0x1f))\n        index = 0x13;\n    else if(index >= 0x22 && index <= 0x2F)\n        index = 0x22;\n\n    retVal = rtl8367c_getAsicReg(RTL8367C_REG_RMA_CTRL00+index, &regData);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    pRmacfg->operation = ((regData >> 7) & 0x0003);\n    pRmacfg->discard_storm_filter = ((regData >> 6) & 0x0001);\n    pRmacfg->trap_priority = ((regData >> 3) & 0x0007);\n    pRmacfg->keep_format = ((regData >> 2) & 0x0001);\n    pRmacfg->vlan_leaky = ((regData >> 1) & 0x0001);\n    pRmacfg->portiso_leaky = (regData & 0x0001);\n\n\n    retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_RMA_CTRL00, RTL8367C_TRAP_PRIORITY_MASK, &regData);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    pRmacfg->trap_priority = regData;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtl8367c_setAsicRmaCdp\n * Description:\n *      Set CDP(Cisco Discovery Protocol) for CPU trapping\n * Input:\n *      pRmacfg     - type of RMA for trapping frame type setting\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK         - Success\n *      RT_ERR_SMI      - SMI access error\n *      RT_ERR_RMA_ADDR - Invalid RMA address index\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicRmaCdp(rtl8367c_rma_t* pRmacfg)\n{\n    rtk_uint32 regData = 0;\n    ret_t retVal;\n\n    if(pRmacfg->operation >= RMAOP_END)\n        return RT_ERR_RMA_ACTION;\n\n    if(pRmacfg->trap_priority > RTL8367C_PRIMAX)\n        return RT_ERR_QOS_INT_PRIORITY;\n\n    regData |= (pRmacfg->portiso_leaky & 0x0001);\n    regData |= ((pRmacfg->vlan_leaky & 0x0001) << 1);\n    regData |= ((pRmacfg->keep_format & 0x0001) << 2);\n    regData |= ((pRmacfg->trap_priority & 0x0007) << 3);\n    regData |= ((pRmacfg->discard_storm_filter & 0x0001) << 6);\n    regData |= ((pRmacfg->operation & 0x0003) << 7);\n\n    retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_RMA_CTRL00, RTL8367C_TRAP_PRIORITY_MASK, pRmacfg->trap_priority);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    return rtl8367c_setAsicReg(RTL8367C_REG_RMA_CTRL_CDP, regData);\n}\n/* Function Name:\n *      rtl8367c_getAsicRmaCdp\n * Description:\n *      Get CDP(Cisco Discovery Protocol) for CPU trapping\n * Input:\n *      None\n * Output:\n *      pRmacfg     - type of RMA for trapping frame type setting\n * Return:\n *      RT_ERR_OK         - Success\n *      RT_ERR_SMI      - SMI access error\n *      RT_ERR_RMA_ADDR - Invalid RMA address index\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicRmaCdp(rtl8367c_rma_t* pRmacfg)\n{\n    ret_t retVal;\n    rtk_uint32 regData;\n\n    retVal = rtl8367c_getAsicReg(RTL8367C_REG_RMA_CTRL_CDP, &regData);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    pRmacfg->operation = ((regData >> 7) & 0x0003);\n    pRmacfg->discard_storm_filter = ((regData >> 6) & 0x0001);\n    pRmacfg->trap_priority = ((regData >> 3) & 0x0007);\n    pRmacfg->keep_format = ((regData >> 2) & 0x0001);\n    pRmacfg->vlan_leaky = ((regData >> 1) & 0x0001);\n    pRmacfg->portiso_leaky = (regData & 0x0001);\n\n    retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_RMA_CTRL00, RTL8367C_TRAP_PRIORITY_MASK, &regData);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    pRmacfg->trap_priority = regData;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtl8367c_setAsicRmaCsstp\n * Description:\n *      Set CSSTP(Cisco Shared Spanning Tree Protocol) for CPU trapping\n * Input:\n *      pRmacfg     - type of RMA for trapping frame type setting\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK         - Success\n *      RT_ERR_SMI      - SMI access error\n *      RT_ERR_RMA_ADDR - Invalid RMA address index\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicRmaCsstp(rtl8367c_rma_t* pRmacfg)\n{\n    rtk_uint32 regData = 0;\n    ret_t retVal;\n\n    if(pRmacfg->operation >= RMAOP_END)\n        return RT_ERR_RMA_ACTION;\n\n    if(pRmacfg->trap_priority > RTL8367C_PRIMAX)\n        return RT_ERR_QOS_INT_PRIORITY;\n\n    regData |= (pRmacfg->portiso_leaky & 0x0001);\n    regData |= ((pRmacfg->vlan_leaky & 0x0001) << 1);\n    regData |= ((pRmacfg->keep_format & 0x0001) << 2);\n    regData |= ((pRmacfg->trap_priority & 0x0007) << 3);\n    regData |= ((pRmacfg->discard_storm_filter & 0x0001) << 6);\n    regData |= ((pRmacfg->operation & 0x0003) << 7);\n\n    retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_RMA_CTRL00, RTL8367C_TRAP_PRIORITY_MASK, pRmacfg->trap_priority);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    return rtl8367c_setAsicReg(RTL8367C_REG_RMA_CTRL_CSSTP, regData);\n}\n/* Function Name:\n *      rtl8367c_getAsicRmaCsstp\n * Description:\n *      Get CSSTP(Cisco Shared Spanning Tree Protocol) for CPU trapping\n * Input:\n *      None\n * Output:\n *      pRmacfg     - type of RMA for trapping frame type setting\n * Return:\n *      RT_ERR_OK         - Success\n *      RT_ERR_SMI      - SMI access error\n *      RT_ERR_RMA_ADDR - Invalid RMA address index\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicRmaCsstp(rtl8367c_rma_t* pRmacfg)\n{\n    ret_t retVal;\n    rtk_uint32 regData;\n\n    retVal = rtl8367c_getAsicReg(RTL8367C_REG_RMA_CTRL_CSSTP, &regData);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    pRmacfg->operation = ((regData >> 7) & 0x0003);\n    pRmacfg->discard_storm_filter = ((regData >> 6) & 0x0001);\n    pRmacfg->trap_priority = ((regData >> 3) & 0x0007);\n    pRmacfg->keep_format = ((regData >> 2) & 0x0001);\n    pRmacfg->vlan_leaky = ((regData >> 1) & 0x0001);\n    pRmacfg->portiso_leaky = (regData & 0x0001);\n\n    retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_RMA_CTRL00, RTL8367C_TRAP_PRIORITY_MASK, &regData);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    pRmacfg->trap_priority = regData;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtl8367c_setAsicRmaLldp\n * Description:\n *      Set LLDP for CPU trapping\n * Input:\n *      pRmacfg     - type of RMA for trapping frame type setting\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK         - Success\n *      RT_ERR_SMI      - SMI access error\n *      RT_ERR_RMA_ADDR - Invalid RMA address index\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicRmaLldp(rtk_uint32 enabled, rtl8367c_rma_t* pRmacfg)\n{\n    rtk_uint32 regData = 0;\n    ret_t retVal;\n\n    if(enabled > 1)\n        return RT_ERR_ENABLE;\n\n    if(pRmacfg->operation >= RMAOP_END)\n        return RT_ERR_RMA_ACTION;\n\n    if(pRmacfg->trap_priority > RTL8367C_PRIMAX)\n        return RT_ERR_QOS_INT_PRIORITY;\n\n    retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_RMA_LLDP_EN, RTL8367C_RMA_LLDP_EN_OFFSET,enabled);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    regData |= (pRmacfg->portiso_leaky & 0x0001);\n    regData |= ((pRmacfg->vlan_leaky & 0x0001) << 1);\n    regData |= ((pRmacfg->keep_format & 0x0001) << 2);\n    regData |= ((pRmacfg->trap_priority & 0x0007) << 3);\n    regData |= ((pRmacfg->discard_storm_filter & 0x0001) << 6);\n    regData |= ((pRmacfg->operation & 0x0003) << 7);\n\n    retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_RMA_CTRL00, RTL8367C_TRAP_PRIORITY_MASK, pRmacfg->trap_priority);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    return rtl8367c_setAsicReg(RTL8367C_REG_RMA_CTRL_LLDP, regData);\n}\n/* Function Name:\n *      rtl8367c_getAsicRmaLldp\n * Description:\n *      Get LLDP for CPU trapping\n * Input:\n *      None\n * Output:\n *      pRmacfg     - type of RMA for trapping frame type setting\n * Return:\n *      RT_ERR_OK         - Success\n *      RT_ERR_SMI      - SMI access error\n *      RT_ERR_RMA_ADDR - Invalid RMA address index\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicRmaLldp(rtk_uint32 *pEnabled, rtl8367c_rma_t* pRmacfg)\n{\n    ret_t retVal;\n    rtk_uint32 regData;\n\n    retVal = rtl8367c_getAsicRegBit(RTL8367C_REG_RMA_LLDP_EN, RTL8367C_RMA_LLDP_EN_OFFSET,pEnabled);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    retVal = rtl8367c_getAsicReg(RTL8367C_REG_RMA_CTRL_LLDP, &regData);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    pRmacfg->operation = ((regData >> 7) & 0x0003);\n    pRmacfg->discard_storm_filter = ((regData >> 6) & 0x0001);\n    pRmacfg->trap_priority = ((regData >> 3) & 0x0007);\n    pRmacfg->keep_format = ((regData >> 2) & 0x0001);\n    pRmacfg->vlan_leaky = ((regData >> 1) & 0x0001);\n    pRmacfg->portiso_leaky = (regData & 0x0001);\n\n    retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_RMA_CTRL00, RTL8367C_TRAP_PRIORITY_MASK, &regData);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    pRmacfg->trap_priority = regData;\n\n    return RT_ERR_OK;\n}\n\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_scheduling.c",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * $Revision: 76306 $\n * $Date: 2017-03-08 15:13:58 +0800 (週三, 08 三月 2017) $\n *\n * Purpose : RTL8367C switch high-level API for RTL8367C\n * Feature : Packet Scheduling related functions\n *\n */\n\n#include <rtl8367c_asicdrv_scheduling.h>\n/* Function Name:\n *      rtl8367c_setAsicLeakyBucketParameter\n * Description:\n *      Set Leaky Bucket Paramters\n * Input:\n *      tick    - Tick is used for time slot size unit\n *      token   - Token is used for adding budget in each time slot\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n *      RT_ERR_TICK     - Invalid TICK\n *      RT_ERR_TOKEN    - Invalid TOKEN\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicLeakyBucketParameter(rtk_uint32 tick, rtk_uint32 token)\n{\n    ret_t retVal;\n\n    if(tick > 0xFF)\n        return RT_ERR_TICK;\n\n    if(token > 0xFF)\n        return RT_ERR_TOKEN;\n\n    retVal = rtl8367c_setAsicRegBits(RTL8367C_LEAKY_BUCKET_TICK_REG, RTL8367C_LEAKY_BUCKET_TICK_MASK, tick);\n\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    retVal = rtl8367c_setAsicRegBits(RTL8367C_LEAKY_BUCKET_TOKEN_REG, RTL8367C_LEAKY_BUCKET_TOKEN_MASK, token);\n\n    return retVal;\n}\n/* Function Name:\n *      rtl8367c_getAsicLeakyBucketParameter\n * Description:\n *      Get Leaky Bucket Paramters\n * Input:\n *      tick    - Tick is used for time slot size unit\n *      token   - Token is used for adding budget in each time slot\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicLeakyBucketParameter(rtk_uint32 *tick, rtk_uint32 *token)\n{\n    ret_t retVal;\n\n    retVal = rtl8367c_getAsicRegBits(RTL8367C_LEAKY_BUCKET_TICK_REG, RTL8367C_LEAKY_BUCKET_TICK_MASK, tick);\n\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    retVal = rtl8367c_getAsicRegBits(RTL8367C_LEAKY_BUCKET_TOKEN_REG, RTL8367C_LEAKY_BUCKET_TOKEN_MASK, token);\n\n    return retVal;\n}\n/* Function Name:\n *      rtl8367c_setAsicAprMeter\n * Description:\n *      Set per-port per-queue APR shared meter index\n * Input:\n *      port    - Physical port number (0~10)\n *      qid     - Queue id\n *      apridx  - dedicated shared meter index for APR (0~7)\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - Success\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_PORT_ID          - Invalid port number\n *      RT_ERR_QUEUE_ID         - Invalid queue id\n *      RT_ERR_FILTER_METER_ID  - Invalid meter\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicAprMeter(rtk_uint32 port, rtk_uint32 qid, rtk_uint32 apridx)\n{\n    ret_t retVal;\n    rtk_uint32 regAddr;\n\n    if(port > RTL8367C_PORTIDMAX)\n        return RT_ERR_PORT_ID;\n\n    if(qid > RTL8367C_QIDMAX)\n        return RT_ERR_QUEUE_ID;\n\n    if(apridx > RTL8367C_PORT_QUEUE_METER_INDEX_MAX)\n        return RT_ERR_FILTER_METER_ID;\n\n    if(port < 8)\n        retVal = rtl8367c_setAsicRegBits(RTL8367C_SCHEDULE_PORT_APR_METER_REG(port, qid), RTL8367C_SCHEDULE_PORT_APR_METER_MASK(qid), apridx);\n    else {\n        regAddr = RTL8367C_REG_SCHEDULE_PORT8_APR_METER_CTRL0 + ((port-8) << 1) + (qid / 5);\n        retVal = rtl8367c_setAsicRegBits(regAddr, RTL8367C_SCHEDULE_PORT_APR_METER_MASK(qid), apridx);\n    }\n\n    return retVal;\n}\n/* Function Name:\n *      rtl8367c_getAsicAprMeter\n * Description:\n *      Get per-port per-queue APR shared meter index\n * Input:\n *      port    - Physical port number (0~10)\n *      qid     - Queue id\n *      apridx  - dedicated shared meter index for APR (0~7)\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n *      RT_ERR_PORT_ID  - Invalid port number\n *      RT_ERR_QUEUE_ID - Invalid queue id\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicAprMeter(rtk_uint32 port, rtk_uint32 qid, rtk_uint32 *apridx)\n{\n    ret_t retVal;\n    rtk_uint32 regAddr;\n\n    if(port > RTL8367C_PORTIDMAX)\n        return RT_ERR_PORT_ID;\n\n    if(qid > RTL8367C_QIDMAX)\n        return RT_ERR_QUEUE_ID;\n\n    if(port < 8)\n        retVal = rtl8367c_getAsicRegBits(RTL8367C_SCHEDULE_PORT_APR_METER_REG(port, qid), RTL8367C_SCHEDULE_PORT_APR_METER_MASK(qid), apridx);\n    else {\n        regAddr = RTL8367C_REG_SCHEDULE_PORT8_APR_METER_CTRL0 + ((port-8) << 1) + (qid / 5);\n        retVal = rtl8367c_getAsicRegBits(regAddr, RTL8367C_SCHEDULE_PORT_APR_METER_MASK(qid), apridx);\n    }\n\n    return retVal;\n}\n/* Function Name:\n *      rtl8367c_setAsicAprEnable\n * Description:\n *      Set per-port APR enable\n * Input:\n *      port        - Physical port number (0~7)\n *      aprEnable   - APR enable seting 1:enable 0:disable\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n *      RT_ERR_PORT_ID  - Invalid port number\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicAprEnable(rtk_uint32 port, rtk_uint32 aprEnable)\n{\n    ret_t retVal;\n\n    if(port > RTL8367C_PORTIDMAX)\n        return RT_ERR_PORT_ID;\n\n    retVal = rtl8367c_setAsicRegBit(RTL8367C_SCHEDULE_APR_CTRL_REG, RTL8367C_SCHEDULE_APR_CTRL_OFFSET(port), aprEnable);\n\n    return retVal;\n}\n/* Function Name:\n *      rtl8367c_getAsicAprEnable\n * Description:\n *      Get per-port APR enable\n * Input:\n *      port        - Physical port number (0~7)\n *      aprEnable   - APR enable seting 1:enable 0:disable\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n *      RT_ERR_PORT_ID  - Invalid port number\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicAprEnable(rtk_uint32 port, rtk_uint32 *aprEnable)\n{\n    ret_t retVal;\n\n    if(port > RTL8367C_PORTIDMAX)\n        return RT_ERR_PORT_ID;\n\n    retVal = rtl8367c_getAsicRegBit(RTL8367C_SCHEDULE_APR_CTRL_REG, RTL8367C_SCHEDULE_APR_CTRL_OFFSET(port), aprEnable);\n\n    return retVal;\n}\n/* Function Name:\n *      rtl8367c_setAsicWFQWeight\n * Description:\n *      Set weight  of a queue\n * Input:\n *      port    - Physical port number (0~10)\n *      qid     - The queue ID wanted to set\n *      qWeight - The weight value wanted to set (valid:0~127)\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - Success\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_PORT_ID          - Invalid port number\n *      RT_ERR_QUEUE_ID         - Invalid queue id\n *      RT_ERR_QOS_QUEUE_WEIGHT - Invalid queue weight\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicWFQWeight(rtk_uint32 port, rtk_uint32 qid, rtk_uint32 qWeight)\n{\n    ret_t retVal;\n\n    /* Invalid input parameter */\n    if(port > RTL8367C_PORTIDMAX)\n        return RT_ERR_PORT_ID;\n\n    if(qid > RTL8367C_QIDMAX)\n        return RT_ERR_QUEUE_ID;\n\n    if(qWeight > RTL8367C_QWEIGHTMAX && qid > 0)\n        return RT_ERR_QOS_QUEUE_WEIGHT;\n\n    retVal = rtl8367c_setAsicReg(RTL8367C_SCHEDULE_PORT_QUEUE_WFQ_WEIGHT_REG(port, qid), qWeight);\n\n    return retVal;\n}\n/* Function Name:\n *      rtl8367c_getAsicWFQWeight\n * Description:\n *      Get weight  of a queue\n * Input:\n *      port    - Physical port number (0~10)\n *      qid     - The queue ID wanted to set\n *      qWeight - The weight value wanted to set (valid:0~127)\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - Success\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_PORT_ID          - Invalid port number\n *      RT_ERR_QUEUE_ID         - Invalid queue id\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicWFQWeight(rtk_uint32 port, rtk_uint32 qid, rtk_uint32 *qWeight)\n{\n    ret_t retVal;\n\n\n    /* Invalid input parameter */\n    if(port  > RTL8367C_PORTIDMAX)\n        return RT_ERR_PORT_ID;\n\n    if(qid > RTL8367C_QIDMAX)\n        return RT_ERR_QUEUE_ID;\n\n\n    retVal = rtl8367c_getAsicReg(RTL8367C_SCHEDULE_PORT_QUEUE_WFQ_WEIGHT_REG(port, qid), qWeight);\n\n    return retVal;\n}\n/* Function Name:\n *      rtl8367c_setAsicWFQBurstSize\n * Description:\n *      Set WFQ leaky bucket burst size\n * Input:\n *      burstsize   - Leaky bucket burst size, unit byte\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicWFQBurstSize(rtk_uint32 burstsize)\n{\n    ret_t retVal;\n\n    retVal = rtl8367c_setAsicReg(RTL8367C_SCHEDULE_WFQ_BURST_SIZE_REG, burstsize);\n\n    return retVal;\n}\n/* Function Name:\n *      rtl8367c_getAsicWFQBurstSize\n * Description:\n *      Get WFQ leaky bucket burst size\n * Input:\n *      burstsize   - Leaky bucket burst size, unit byte\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicWFQBurstSize(rtk_uint32 *burstsize)\n{\n    ret_t retVal;\n\n    retVal = rtl8367c_getAsicReg(RTL8367C_SCHEDULE_WFQ_BURST_SIZE_REG, burstsize);\n\n    return retVal;\n}\n/* Function Name:\n *      rtl8367c_setAsicQueueType\n * Description:\n *      Set type of a queue\n * Input:\n *      port        - Physical port number (0~10)\n *      qid         - The queue ID wanted to set\n *      queueType   - The specified queue type. 0b0: Strict priority, 0b1: WFQ\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n *      RT_ERR_PORT_ID  - Invalid port number\n *      RT_ERR_QUEUE_ID - Invalid queue id\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicQueueType(rtk_uint32 port, rtk_uint32 qid, rtk_uint32 queueType)\n{\n    ret_t retVal;\n\n    /* Invalid input parameter */\n    if(port > RTL8367C_PORTIDMAX)\n        return RT_ERR_PORT_ID;\n\n    if(qid > RTL8367C_QIDMAX)\n        return RT_ERR_QUEUE_ID;\n\n    /* Set Related Registers */\n    retVal = rtl8367c_setAsicRegBit(RTL8367C_SCHEDULE_QUEUE_TYPE_REG(port), RTL8367C_SCHEDULE_QUEUE_TYPE_OFFSET(port, qid),queueType);\n\n    return retVal;\n}\n/* Function Name:\n *      rtl8367c_getAsicQueueType\n * Description:\n *      Get type of a queue\n * Input:\n *      port        - Physical port number (0~7)\n *      qid         - The queue ID wanted to set\n *      queueType   - The specified queue type. 0b0: Strict priority, 0b1: WFQ\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n *      RT_ERR_PORT_ID  - Invalid port number\n *      RT_ERR_QUEUE_ID - Invalid queue id\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicQueueType(rtk_uint32 port, rtk_uint32 qid, rtk_uint32 *queueType)\n{\n    ret_t retVal;\n\n    /* Invalid input parameter */\n    if(port  > RTL8367C_PORTIDMAX)\n        return RT_ERR_PORT_ID;\n\n    if(qid > RTL8367C_QIDMAX)\n        return RT_ERR_QUEUE_ID;\n\n    retVal = rtl8367c_getAsicRegBit(RTL8367C_SCHEDULE_QUEUE_TYPE_REG(port), RTL8367C_SCHEDULE_QUEUE_TYPE_OFFSET(port, qid),queueType);\n\n    return retVal;\n}\n/* Function Name:\n *      rtl8367c_setAsicPortEgressRate\n * Description:\n *      Set per-port egress rate\n * Input:\n *      port        - Physical port number (0~10)\n *      rate        - Egress rate\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number\n *      RT_ERR_QOS_EBW_RATE - Invalid bandwidth/rate\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicPortEgressRate(rtk_uint32 port, rtk_uint32 rate)\n{\n    ret_t retVal;\n    rtk_uint32 regAddr, regData;\n\n    if(port > RTL8367C_PORTIDMAX)\n        return RT_ERR_PORT_ID;\n\n    if(rate > RTL8367C_QOS_GRANULARTY_MAX)\n        return RT_ERR_QOS_EBW_RATE;\n\n    regAddr = RTL8367C_PORT_EGRESSBW_LSB_REG(port);\n    regData = RTL8367C_QOS_GRANULARTY_LSB_MASK & rate;\n\n    retVal = rtl8367c_setAsicReg(regAddr, regData);\n\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    regAddr = RTL8367C_PORT_EGRESSBW_MSB_REG(port);\n    regData = (RTL8367C_QOS_GRANULARTY_MSB_MASK & rate) >> RTL8367C_QOS_GRANULARTY_MSB_OFFSET;\n\n    retVal = rtl8367c_setAsicRegBits(regAddr, RTL8367C_PORT6_EGRESSBW_CTRL1_MASK, regData);\n\n    return retVal;\n}\n/* Function Name:\n *      rtl8367c_getAsicPortEgressRate\n * Description:\n *      Get per-port egress rate\n * Input:\n *      port        - Physical port number (0~10)\n *      rate        - Egress rate\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicPortEgressRate(rtk_uint32 port, rtk_uint32 *rate)\n{\n    ret_t retVal;\n    rtk_uint32 regAddr, regData,regData2;\n\n    if(port > RTL8367C_PORTIDMAX)\n        return RT_ERR_PORT_ID;\n\n    regAddr = RTL8367C_PORT_EGRESSBW_LSB_REG(port);\n\n    retVal = rtl8367c_getAsicReg(regAddr, &regData);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    regAddr = RTL8367C_PORT_EGRESSBW_MSB_REG(port);\n    retVal = rtl8367c_getAsicRegBits(regAddr, RTL8367C_PORT6_EGRESSBW_CTRL1_MASK, &regData2);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    *rate = regData | (regData2 << RTL8367C_QOS_GRANULARTY_MSB_OFFSET);\n\n    return RT_ERR_OK;\n}\n/* Function Name:\n *      rtl8367c_setAsicPortEgressRateIfg\n * Description:\n *      Set per-port egress rate calculate include/exclude IFG\n * Input:\n *      ifg     - 1:include IFG 0:exclude IFG\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicPortEgressRateIfg(rtk_uint32 ifg)\n{\n    ret_t retVal;\n\n    retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_SCHEDULE_WFQ_CTRL, RTL8367C_SCHEDULE_WFQ_CTRL_OFFSET, ifg);\n\n    return retVal;\n}\n/* Function Name:\n *      rtl8367c_getAsicPortEgressRateIfg\n * Description:\n *      Get per-port egress rate calculate include/exclude IFG\n * Input:\n *      ifg     - 1:include IFG 0:exclude IFG\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicPortEgressRateIfg(rtk_uint32 *ifg)\n{\n    ret_t retVal;\n\n    retVal = rtl8367c_getAsicRegBit(RTL8367C_REG_SCHEDULE_WFQ_CTRL, RTL8367C_SCHEDULE_WFQ_CTRL_OFFSET, ifg);\n\n    return retVal;\n}\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_storm.c",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * $Revision: 76306 $\n * $Date: 2017-03-08 15:13:58 +0800 (週三, 08 三月 2017) $\n *\n * Purpose : RTL8367C switch high-level API for RTL8367C\n * Feature : Storm control filtering related functions\n *\n */\n\n#include <rtl8367c_asicdrv_storm.h>\n/* Function Name:\n *      rtl8367c_setAsicStormFilterBroadcastEnable\n * Description:\n *      Set per-port broadcast storm filter enable/disable\n * Input:\n *      port    - Physical port number (0~7)\n *      enabled - 1: enabled, 0: disabled\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n *      RT_ERR_PORT_ID  - Invalid port number\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicStormFilterBroadcastEnable(rtk_uint32 port, rtk_uint32 enabled)\n{\n    if(port >= RTL8367C_PORTNO)\n        return RT_ERR_PORT_ID;\n\n    return rtl8367c_setAsicRegBit(RTL8367C_STORM_BCAST_REG, port, enabled);\n}\n/* Function Name:\n *      rtl8367c_getAsicStormFilterBroadcastEnable\n * Description:\n *      Get per-port broadcast storm filter enable/disable\n * Input:\n *      port    - Physical port number (0~7)\n *      pEnabled - 1: enabled, 0: disabled\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n *      RT_ERR_PORT_ID  - Invalid port number\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicStormFilterBroadcastEnable(rtk_uint32 port, rtk_uint32 *pEnabled)\n{\n    if(port >= RTL8367C_PORTNO)\n        return RT_ERR_PORT_ID;\n\n    return rtl8367c_getAsicRegBit(RTL8367C_STORM_BCAST_REG, port, pEnabled);\n}\n/* Function Name:\n *      rtl8367c_setAsicStormFilterBroadcastMeter\n * Description:\n *      Set per-port broadcast storm filter meter\n * Input:\n *      port    - Physical port number (0~7)\n *      meter   - meter index (0~31)\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - Success\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_PORT_ID          - Invalid port number\n *      RT_ERR_FILTER_METER_ID  - Invalid meter index\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicStormFilterBroadcastMeter(rtk_uint32 port, rtk_uint32 meter)\n{\n    if(port >= RTL8367C_PORTNO)\n        return RT_ERR_PORT_ID;\n\n    if(meter > RTL8367C_METERMAX)\n        return RT_ERR_FILTER_METER_ID;\n\n    return rtl8367c_setAsicRegBits(RTL8367C_STORM_BCAST_METER_CTRL_REG(port), RTL8367C_STORM_BCAST_METER_CTRL_MASK(port), meter);\n}\n/* Function Name:\n *      rtl8367c_getAsicStormFilterBroadcastMeter\n * Description:\n *      Get per-port broadcast storm filter meter\n * Input:\n *      port    - Physical port number (0~7)\n *      pMeter  - meter index (0~31)\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n *      RT_ERR_PORT_ID  - Invalid port number\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicStormFilterBroadcastMeter(rtk_uint32 port, rtk_uint32 *pMeter)\n{\n    if(port >= RTL8367C_PORTNO)\n        return RT_ERR_PORT_ID;\n\n    return rtl8367c_getAsicRegBits(RTL8367C_STORM_BCAST_METER_CTRL_REG(port), RTL8367C_STORM_BCAST_METER_CTRL_MASK(port), pMeter);\n}\n/* Function Name:\n *      rtl8367c_setAsicStormFilterMulticastEnable\n * Description:\n *      Set per-port multicast storm filter enable/disable\n * Input:\n *      port    - Physical port number (0~7)\n *      enabled - 1: enabled, 0: disabled\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n *      RT_ERR_PORT_ID  - Invalid port number\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicStormFilterMulticastEnable(rtk_uint32 port, rtk_uint32 enabled)\n{\n    if(port >= RTL8367C_PORTNO)\n        return RT_ERR_PORT_ID;\n\n    return rtl8367c_setAsicRegBit(RTL8367C_STORM_MCAST_REG, port, enabled);\n}\n/* Function Name:\n *      rtl8367c_getAsicStormFilterMulticastEnable\n * Description:\n *      Get per-port multicast storm filter enable/disable\n * Input:\n *      port    - Physical port number (0~7)\n *      pEnabled - 1: enabled, 0: disabled\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n *      RT_ERR_PORT_ID  - Invalid port number\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicStormFilterMulticastEnable(rtk_uint32 port, rtk_uint32 *pEnabled)\n{\n    if(port >= RTL8367C_PORTNO)\n        return RT_ERR_PORT_ID;\n\n    return rtl8367c_getAsicRegBit(RTL8367C_STORM_MCAST_REG, port, pEnabled);\n}\n/* Function Name:\n *      rtl8367c_setAsicStormFilterMulticastMeter\n * Description:\n *      Set per-port multicast storm filter meter\n * Input:\n *      port    - Physical port number (0~7)\n *      meter   - meter index (0~31)\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - Success\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_PORT_ID          - Invalid port number\n *      RT_ERR_FILTER_METER_ID  - Invalid meter index\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicStormFilterMulticastMeter(rtk_uint32 port, rtk_uint32 meter)\n{\n    if(port >= RTL8367C_PORTNO)\n        return RT_ERR_PORT_ID;\n\n    if(meter > RTL8367C_METERMAX)\n        return RT_ERR_FILTER_METER_ID;\n\n    return rtl8367c_setAsicRegBits(RTL8367C_STORM_MCAST_METER_CTRL_REG(port), RTL8367C_STORM_MCAST_METER_CTRL_MASK(port), meter);\n}\n/* Function Name:\n *      rtl8367c_getAsicStormFilterMulticastMeter\n * Description:\n *      Get per-port multicast storm filter meter\n * Input:\n *      port    - Physical port number (0~7)\n *      pMeter  - meter index (0~31)\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n *      RT_ERR_PORT_ID  - Invalid port number\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicStormFilterMulticastMeter(rtk_uint32 port, rtk_uint32 *pMeter)\n{\n    if(port >= RTL8367C_PORTNO)\n        return RT_ERR_PORT_ID;\n\n    return rtl8367c_getAsicRegBits(RTL8367C_STORM_MCAST_METER_CTRL_REG(port), RTL8367C_STORM_MCAST_METER_CTRL_MASK(port), pMeter);\n}\n/* Function Name:\n *      rtl8367c_setAsicStormFilterUnknownMulticastEnable\n * Description:\n *      Set per-port unknown multicast storm filter enable/disable\n * Input:\n *      port    - Physical port number (0~7)\n *      enabled - 1: enabled, 0: disabled\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n *      RT_ERR_PORT_ID  - Invalid port number\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicStormFilterUnknownMulticastEnable(rtk_uint32 port, rtk_uint32 enabled)\n{\n    if(port >= RTL8367C_PORTNO)\n        return RT_ERR_PORT_ID;\n\n    return rtl8367c_setAsicRegBit(RTL8367C_STORM_UNKNOWN_MCAST_REG, port, enabled);\n}\n/* Function Name:\n *      rtl8367c_getAsicStormFilterUnknownMulticastEnable\n * Description:\n *      Get per-port unknown multicast storm filter enable/disable\n * Input:\n *      port    - Physical port number (0~7)\n *      pEnabled - 1: enabled, 0: disabled\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n *      RT_ERR_PORT_ID  - Invalid port number\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicStormFilterUnknownMulticastEnable(rtk_uint32 port, rtk_uint32 *pEnabled)\n{\n    if(port >= RTL8367C_PORTNO)\n        return RT_ERR_PORT_ID;\n\n    return rtl8367c_getAsicRegBit(RTL8367C_STORM_UNKNOWN_MCAST_REG, port, pEnabled);\n}\n/* Function Name:\n *      rtl8367c_setAsicStormFilterUnknownMulticastMeter\n * Description:\n *      Set per-port unknown multicast storm filter meter\n * Input:\n *      port    - Physical port number (0~7)\n *      meter   - meter index (0~31)\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - Success\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_PORT_ID          - Invalid port number\n *      RT_ERR_FILTER_METER_ID  - Invalid meter index\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicStormFilterUnknownMulticastMeter(rtk_uint32 port, rtk_uint32 meter)\n{\n    ret_t retVal;\n\n    if(port >= RTL8367C_PORTNO)\n        return RT_ERR_PORT_ID;\n\n    if(meter > RTL8367C_METERMAX)\n        return RT_ERR_FILTER_METER_ID;\n\n    if(port < 8)\n    {\n        retVal = rtl8367c_setAsicRegBits(RTL8367C_STORM_UNMC_METER_CTRL_REG(port), RTL8367C_STORM_UNMC_METER_CTRL_MASK(port), meter);\n        if(retVal != RT_ERR_OK)\n            return retVal;\n    }\n    else\n    {\n        retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_STORM_UNMC_METER_CTRL4 + ((port - 8) >> 1), RTL8367C_STORM_UNMC_METER_CTRL_MASK(port), meter);\n        if(retVal != RT_ERR_OK)\n            return retVal;\n    }\n\n    return RT_ERR_OK;\n}\n/* Function Name:\n *      rtl8367c_getAsicStormFilterUnknownMulticastMeter\n * Description:\n *      Get per-port unknown multicast storm filter meter\n * Input:\n *      port    - Physical port number (0~7)\n *      pMeter  - meter index (0~31)\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n *      RT_ERR_PORT_ID  - Invalid port number\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicStormFilterUnknownMulticastMeter(rtk_uint32 port, rtk_uint32 *pMeter)\n{\n    ret_t retVal;\n\n    if(port >= RTL8367C_PORTNO)\n        return RT_ERR_PORT_ID;\n\n    if(port < 8)\n    {\n        retVal = rtl8367c_getAsicRegBits(RTL8367C_STORM_UNMC_METER_CTRL_REG(port), RTL8367C_STORM_UNMC_METER_CTRL_MASK(port), pMeter);\n        if(retVal != RT_ERR_OK)\n            return retVal;\n    }\n    else\n    {\n        retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_STORM_UNMC_METER_CTRL4 + ((port - 8) >> 1), RTL8367C_STORM_UNMC_METER_CTRL_MASK(port), pMeter);\n        if(retVal != RT_ERR_OK)\n            return retVal;\n    }\n\n    return RT_ERR_OK;\n}\n/* Function Name:\n *      rtl8367c_setAsicStormFilterUnknownUnicastEnable\n * Description:\n *      Set per-port unknown unicast storm filter enable/disable\n * Input:\n *      port    - Physical port number (0~7)\n *      enabled - 1: enabled, 0: disabled\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n *      RT_ERR_PORT_ID  - Invalid port number\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicStormFilterUnknownUnicastEnable(rtk_uint32 port, rtk_uint32 enabled)\n{\n    if(port >= RTL8367C_PORTNO)\n        return RT_ERR_PORT_ID;\n\n    return rtl8367c_setAsicRegBit(RTL8367C_STORM_UNKNOWN_UCAST_REG, port, enabled);\n}\n/* Function Name:\n *      rtl8367c_getAsicStormFilterUnknownUnicastEnable\n * Description:\n *      get per-port unknown unicast storm filter enable/disable\n * Input:\n *      port    - Physical port number (0~7)\n *      pEnabled - 1: enabled, 0: disabled\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n *      RT_ERR_PORT_ID  - Invalid port number\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicStormFilterUnknownUnicastEnable(rtk_uint32 port, rtk_uint32 *pEnabled)\n{\n    if(port >= RTL8367C_PORTNO)\n        return RT_ERR_PORT_ID;\n\n    return rtl8367c_getAsicRegBit(RTL8367C_STORM_UNKNOWN_UCAST_REG, port, pEnabled);\n}\n/* Function Name:\n *      rtl8367c_setAsicStormFilterUnknownUnicastMeter\n * Description:\n *      Set per-port unknown unicast storm filter meter\n * Input:\n *      port    - Physical port number (0~7)\n *      meter   - meter index (0~31)\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - Success\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_PORT_ID          - Invalid port number\n *      RT_ERR_FILTER_METER_ID  - Invalid meter index\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicStormFilterUnknownUnicastMeter(rtk_uint32 port, rtk_uint32 meter)\n{\n    if(port >= RTL8367C_PORTNO)\n        return RT_ERR_PORT_ID;\n\n    if(meter > RTL8367C_METERMAX)\n        return RT_ERR_FILTER_METER_ID;\n\n    return rtl8367c_setAsicRegBits(RTL8367C_STORM_UNDA_METER_CTRL_REG(port), RTL8367C_STORM_UNDA_METER_CTRL_MASK(port), meter);\n}\n/* Function Name:\n *      rtl8367c_getAsicStormFilterUnknownUnicastMeter\n * Description:\n *      Get per-port unknown unicast storm filter meter\n * Input:\n *      port    - Physical port number (0~7)\n *      pMeter  - meter index (0~31)\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n *      RT_ERR_PORT_ID  - Invalid port number\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicStormFilterUnknownUnicastMeter(rtk_uint32 port, rtk_uint32 *pMeter)\n{\n    if(port >= RTL8367C_PORTNO)\n        return RT_ERR_PORT_ID;\n\n    return rtl8367c_getAsicRegBits(RTL8367C_STORM_UNDA_METER_CTRL_REG(port), RTL8367C_STORM_UNDA_METER_CTRL_MASK(port), pMeter);\n}\n\n/* Function Name:\n *      rtl8367c_setAsicStormFilterExtBroadcastMeter\n * Description:\n *      Set extension broadcast storm filter meter\n * Input:\n *      meter   - meter index (0~31)\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - Success\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_FILTER_METER_ID  - Invalid meter index\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicStormFilterExtBroadcastMeter(rtk_uint32 meter)\n{\n    if(meter > RTL8367C_METERMAX)\n        return RT_ERR_FILTER_METER_ID;\n\n    return rtl8367c_setAsicRegBits(RTL8367C_REG_STORM_EXT_MTRIDX_CFG0, RTL8367C_BC_STORM_EXT_METERIDX_MASK, meter);\n}\n\n/* Function Name:\n *      rtl8367c_getAsicStormFilterExtBroadcastMeter\n * Description:\n *      get extension broadcast storm filter meter\n * Input:\n *      None\n * Output:\n *      pMeter  - meter index (0~31)\n * Return:\n *      RT_ERR_OK               - Success\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_NULL_POINTER     - Invalid meter index\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicStormFilterExtBroadcastMeter(rtk_uint32 *pMeter)\n{\n    if(NULL == pMeter)\n        return RT_ERR_NULL_POINTER;\n\n    return rtl8367c_getAsicRegBits(RTL8367C_REG_STORM_EXT_MTRIDX_CFG0, RTL8367C_BC_STORM_EXT_METERIDX_MASK, pMeter);\n}\n\n/* Function Name:\n *      rtl8367c_setAsicStormFilterExtMulticastMeter\n * Description:\n *      Set extension multicast storm filter meter\n * Input:\n *      meter   - meter index (0~31)\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - Success\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_FILTER_METER_ID  - Invalid meter index\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicStormFilterExtMulticastMeter(rtk_uint32 meter)\n{\n    if(meter > RTL8367C_METERMAX)\n        return RT_ERR_FILTER_METER_ID;\n\n    return rtl8367c_setAsicRegBits(RTL8367C_REG_STORM_EXT_MTRIDX_CFG0, RTL8367C_MC_STORM_EXT_METERIDX_MASK, meter);\n}\n\n/* Function Name:\n *      rtl8367c_getAsicStormFilterExtMulticastMeter\n * Description:\n *      get extension multicast storm filter meter\n * Input:\n *      None\n * Output:\n *      pMeter  - meter index (0~31)\n * Return:\n *      RT_ERR_OK               - Success\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_NULL_POINTER     - Invalid meter index\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicStormFilterExtMulticastMeter(rtk_uint32 *pMeter)\n{\n    if(NULL == pMeter)\n        return RT_ERR_NULL_POINTER;\n\n    return rtl8367c_getAsicRegBits(RTL8367C_REG_STORM_EXT_MTRIDX_CFG0, RTL8367C_MC_STORM_EXT_METERIDX_MASK, pMeter);\n}\n\n/* Function Name:\n *      rtl8367c_setAsicStormFilterExtUnknownMulticastMeter\n * Description:\n *      Set extension unknown multicast storm filter meter\n * Input:\n *      meter   - meter index (0~31)\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - Success\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_FILTER_METER_ID  - Invalid meter index\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicStormFilterExtUnknownMulticastMeter(rtk_uint32 meter)\n{\n    if(meter > RTL8367C_METERMAX)\n        return RT_ERR_FILTER_METER_ID;\n\n    return rtl8367c_setAsicRegBits(RTL8367C_REG_STORM_EXT_MTRIDX_CFG1, RTL8367C_UNMC_STORM_EXT_METERIDX_MASK, meter);\n}\n\n/* Function Name:\n *      rtl8367c_getAsicStormFilterExtUnknownMulticastMeter\n * Description:\n *      get extension unknown multicast storm filter meter\n * Input:\n *      None\n * Output:\n *      pMeter  - meter index (0~31)\n * Return:\n *      RT_ERR_OK               - Success\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_NULL_POINTER     - Invalid meter index\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicStormFilterExtUnknownMulticastMeter(rtk_uint32 *pMeter)\n{\n    if(NULL == pMeter)\n        return RT_ERR_NULL_POINTER;\n\n    return rtl8367c_getAsicRegBits(RTL8367C_REG_STORM_EXT_MTRIDX_CFG1, RTL8367C_UNMC_STORM_EXT_METERIDX_MASK, pMeter);\n}\n\n/* Function Name:\n *      rtl8367c_setAsicStormFilterExtUnknownUnicastMeter\n * Description:\n *      Set extension unknown unicast storm filter meter\n * Input:\n *      meter   - meter index (0~31)\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - Success\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_FILTER_METER_ID  - Invalid meter index\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicStormFilterExtUnknownUnicastMeter(rtk_uint32 meter)\n{\n    if(meter > RTL8367C_METERMAX)\n        return RT_ERR_FILTER_METER_ID;\n\n    return rtl8367c_setAsicRegBits(RTL8367C_REG_STORM_EXT_MTRIDX_CFG1, RTL8367C_UNUC_STORM_EXT_METERIDX_MASK, meter);\n}\n\n/* Function Name:\n *      rtl8367c_getAsicStormFilterExtUnknownUnicastMeter\n * Description:\n *      get extension unknown unicast storm filter meter\n * Input:\n *      None\n * Output:\n *      pMeter  - meter index (0~31)\n * Return:\n *      RT_ERR_OK               - Success\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_NULL_POINTER     - Invalid meter index\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicStormFilterExtUnknownUnicastMeter(rtk_uint32 *pMeter)\n{\n    if(NULL == pMeter)\n        return RT_ERR_NULL_POINTER;\n\n    return rtl8367c_getAsicRegBits(RTL8367C_REG_STORM_EXT_MTRIDX_CFG1, RTL8367C_UNUC_STORM_EXT_METERIDX_MASK, pMeter);\n}\n\n/* Function Name:\n *      rtl8367c_setAsicStormFilterExtBroadcastEnable\n * Description:\n *      Set extension broadcast storm filter state\n * Input:\n *      enabled     - state\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - Success\n *      RT_ERR_SMI              - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicStormFilterExtBroadcastEnable(rtk_uint32 enabled)\n{\n    return rtl8367c_setAsicRegBit(RTL8367C_REG_STORM_EXT_CFG, RTL8367C_STORM_BCAST_EXT_EN_OFFSET, enabled);\n}\n\n/* Function Name:\n *      rtl8367c_getAsicStormFilterExtBroadcastEnable\n * Description:\n *      Get extension broadcast storm filter state\n * Input:\n *      None\n * Output:\n *      pEnabled    - state\n * Return:\n *      RT_ERR_OK               - Success\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_NULL_POINTER     - Null pointer\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicStormFilterExtBroadcastEnable(rtk_uint32 *pEnabled)\n{\n    if(NULL == pEnabled)\n        return RT_ERR_NULL_POINTER;\n\n    return rtl8367c_getAsicRegBit(RTL8367C_REG_STORM_EXT_CFG, RTL8367C_STORM_BCAST_EXT_EN_OFFSET, pEnabled);\n}\n\n/* Function Name:\n *      rtl8367c_setAsicStormFilterExtMulticastEnable\n * Description:\n *      Set extension multicast storm filter state\n * Input:\n *      enabled     - state\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - Success\n *      RT_ERR_SMI              - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicStormFilterExtMulticastEnable(rtk_uint32 enabled)\n{\n    return rtl8367c_setAsicRegBit(RTL8367C_REG_STORM_EXT_CFG, RTL8367C_STORM_MCAST_EXT_EN_OFFSET, enabled);\n}\n\n/* Function Name:\n *      rtl8367c_getAsicStormFilterExtMulticastEnable\n * Description:\n *      Get extension multicast storm filter state\n * Input:\n *      None\n * Output:\n *      pEnabled    - state\n * Return:\n *      RT_ERR_OK               - Success\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_NULL_POINTER     - Null pointer\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicStormFilterExtMulticastEnable(rtk_uint32 *pEnabled)\n{\n    if(NULL == pEnabled)\n        return RT_ERR_NULL_POINTER;\n\n    return rtl8367c_getAsicRegBit(RTL8367C_REG_STORM_EXT_CFG, RTL8367C_STORM_MCAST_EXT_EN_OFFSET, pEnabled);\n}\n\n/* Function Name:\n *      rtl8367c_setAsicStormFilterExtUnknownMulticastEnable\n * Description:\n *      Set extension unknown multicast storm filter state\n * Input:\n *      enabled     - state\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - Success\n *      RT_ERR_SMI              - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicStormFilterExtUnknownMulticastEnable(rtk_uint32 enabled)\n{\n    return rtl8367c_setAsicRegBit(RTL8367C_REG_STORM_EXT_CFG, RTL8367C_STORM_UNKNOWN_MCAST_EXT_EN_OFFSET, enabled);\n}\n\n/* Function Name:\n *      rtl8367c_getAsicStormFilterExtUnknownMulticastEnable\n * Description:\n *      Get extension unknown multicast storm filter state\n * Input:\n *      None\n * Output:\n *      pEnabled    - state\n * Return:\n *      RT_ERR_OK               - Success\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_NULL_POINTER     - Null pointer\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicStormFilterExtUnknownMulticastEnable(rtk_uint32 *pEnabled)\n{\n    if(NULL == pEnabled)\n        return RT_ERR_NULL_POINTER;\n\n    return rtl8367c_getAsicRegBit(RTL8367C_REG_STORM_EXT_CFG, RTL8367C_STORM_UNKNOWN_MCAST_EXT_EN_OFFSET, pEnabled);\n}\n\n/* Function Name:\n *      rtl8367c_setAsicStormFilterExtUnknownUnicastEnable\n * Description:\n *      Set extension unknown unicast storm filter state\n * Input:\n *      enabled     - state\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - Success\n *      RT_ERR_SMI              - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicStormFilterExtUnknownUnicastEnable(rtk_uint32 enabled)\n{\n    return rtl8367c_setAsicRegBit(RTL8367C_REG_STORM_EXT_CFG, RTL8367C_STORM_UNKNOWN_UCAST_EXT_EN_OFFSET, enabled);\n}\n\n/* Function Name:\n *      rtl8367c_getAsicStormFilterExtUnknownUnicastEnable\n * Description:\n *      Get extension unknown unicast storm filter state\n * Input:\n *      None\n * Output:\n *      pEnabled    - state\n * Return:\n *      RT_ERR_OK               - Success\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_NULL_POINTER     - Null pointer\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicStormFilterExtUnknownUnicastEnable(rtk_uint32 *pEnabled)\n{\n    if(NULL == pEnabled)\n        return RT_ERR_NULL_POINTER;\n\n    return rtl8367c_getAsicRegBit(RTL8367C_REG_STORM_EXT_CFG, RTL8367C_STORM_UNKNOWN_UCAST_EXT_EN_OFFSET, pEnabled);\n}\n\n/* Function Name:\n *      rtl8367c_setAsicStormFilterExtEnablePortMask\n * Description:\n *      Set extension storm filter port mask\n * Input:\n *      portmask    - port mask\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - Success\n *      RT_ERR_SMI              - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicStormFilterExtEnablePortMask(rtk_uint32 portmask)\n{\n    ret_t retVal;\n\n    retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_STORM_EXT_CFG, RTL8367C_STORM_EXT_EN_PORTMASK_MASK, portmask & 0x3FF);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_STORM_EXT_CFG, RTL8367C_STORM_EXT_EN_PORTMASK_EXT_MASK, (portmask >> 10)&1);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtl8367c_getAsicStormFilterExtEnablePortMask\n * Description:\n *      Get extension storm filter port mask\n * Input:\n *      portmask    - port mask\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - Success\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_NULL_POINTER     - Null pointer\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicStormFilterExtEnablePortMask(rtk_uint32 *pPortmask)\n{\n    rtk_uint32 tmpPmsk;\n    ret_t retVal;\n\n    if(NULL == pPortmask)\n        return RT_ERR_NULL_POINTER;\n\n    retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_STORM_EXT_CFG, RTL8367C_STORM_EXT_EN_PORTMASK_MASK, &tmpPmsk);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n    *pPortmask = tmpPmsk & 0x3ff;\n\n    retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_STORM_EXT_CFG, RTL8367C_STORM_EXT_EN_PORTMASK_EXT_MASK, &tmpPmsk);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n    *pPortmask |= (tmpPmsk & 1) << 10;\n\n    return RT_ERR_OK;\n}\n\n\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_svlan.c",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * $Revision: 76306 $\n * $Date: 2017-03-08 15:13:58 +0800 (週三, 08 三月 2017) $\n *\n * Purpose : RTL8367C switch high-level API for RTL8367C\n * Feature : SVLAN related functions\n *\n */\n#include <rtl8367c_asicdrv_svlan.h>\n\n#include <string.h>\n\nstatic void _rtl8367c_svlanConfStUser2Smi( rtl8367c_svlan_memconf_t *pUserSt, rtk_uint16 *pSmiSt)\n{\n    pSmiSt[0] |= (pUserSt->vs_member & 0x00FF);\n    pSmiSt[0] |= (pUserSt->vs_untag & 0x00FF) << 8;\n\n    pSmiSt[1] |= (pUserSt->vs_fid_msti & 0x000F);\n    pSmiSt[1] |= (pUserSt->vs_priority & 0x0007) << 4;\n    pSmiSt[1] |= (pUserSt->vs_force_fid & 0x0001) << 7;\n\n    pSmiSt[2] |= (pUserSt->vs_svid & 0x0FFF);\n    pSmiSt[2] |= (pUserSt->vs_efiden & 0x0001) << 12;\n    pSmiSt[2] |= (pUserSt->vs_efid & 0x0007) << 13;\n\n    pSmiSt[3] |= ((pUserSt->vs_member & 0x0700) >> 8);\n    pSmiSt[3] |= ((pUserSt->vs_untag & 0x0700) >> 8) << 3;\n}\n\nstatic void _rtl8367c_svlanConfStSmi2User( rtl8367c_svlan_memconf_t *pUserSt, rtk_uint16 *pSmiSt)\n{\n\n    pUserSt->vs_member = (pSmiSt[0] & 0x00FF) | ((pSmiSt[3] & 0x0007) << 8);\n    pUserSt->vs_untag = ((pSmiSt[0] & 0xFF00) >> 8) | (((pSmiSt[3] & 0x0038) >> 3) << 8);\n\n    pUserSt->vs_fid_msti = (pSmiSt[1] & 0x000F);\n    pUserSt->vs_priority = (pSmiSt[1] & 0x0070) >> 4;\n    pUserSt->vs_force_fid = (pSmiSt[1] & 0x0080) >> 7;\n\n    pUserSt->vs_svid = (pSmiSt[2] & 0x0FFF);\n    pUserSt->vs_efiden = (pSmiSt[2] & 0x1000) >> 12;\n    pUserSt->vs_efid = (pSmiSt[2] & 0xE000) >> 13;\n}\n\nstatic void _rtl8367c_svlanMc2sStUser2Smi(rtl8367c_svlan_mc2s_t *pUserSt, rtk_uint16 *pSmiSt)\n{\n    pSmiSt[0] |= (pUserSt->svidx & 0x003F);\n    pSmiSt[0] |= (pUserSt->format & 0x0001) << 6;\n    pSmiSt[0] |= (pUserSt->valid & 0x0001) << 7;\n\n    pSmiSt[1] = (rtk_uint16)(pUserSt->smask & 0x0000FFFF);\n    pSmiSt[2] = (rtk_uint16)((pUserSt->smask & 0xFFFF0000) >> 16);\n\n    pSmiSt[3] = (rtk_uint16)(pUserSt->sdata & 0x0000FFFF);\n    pSmiSt[4] = (rtk_uint16)((pUserSt->sdata & 0xFFFF0000) >> 16);\n}\n\nstatic void _rtl8367c_svlanMc2sStSmi2User(rtl8367c_svlan_mc2s_t *pUserSt, rtk_uint16 *pSmiSt)\n{\n    pUserSt->svidx = (pSmiSt[0] & 0x003F);\n    pUserSt->format = (pSmiSt[0] & 0x0040) >> 6;\n    pUserSt->valid = (pSmiSt[0] & 0x0080) >> 7;\n\n    pUserSt->smask = pSmiSt[1] | (pSmiSt[2] << 16);\n    pUserSt->sdata = pSmiSt[3] | (pSmiSt[4] << 16);\n}\n\nstatic void _rtl8367c_svlanSp2cStUser2Smi(rtl8367c_svlan_s2c_t *pUserSt, rtk_uint16 *pSmiSt)\n{\n    pSmiSt[0] |= (pUserSt->dstport & 0x0007);\n    pSmiSt[0] |= (pUserSt->svidx & 0x003F) << 3;\n    pSmiSt[0] |= ((pUserSt->dstport & 0x0008) >> 3) << 9;\n\n    pSmiSt[1] |= (pUserSt->vid & 0x0FFF);\n    pSmiSt[1] |= (pUserSt->valid & 0x0001) << 12;\n}\n\nstatic void _rtl8367c_svlanSp2cStSmi2User(rtl8367c_svlan_s2c_t *pUserSt, rtk_uint16 *pSmiSt)\n{\n    pUserSt->dstport = (((pSmiSt[0] & 0x0200) >> 9) << 3) | (pSmiSt[0] & 0x0007);\n    pUserSt->svidx   = (pSmiSt[0] & 0x01F8) >> 3;\n    pUserSt->vid     = (pSmiSt[1] & 0x0FFF);\n    pUserSt->valid   = (pSmiSt[1] & 0x1000) >> 12;\n}\n\n/* Function Name:\n *      rtl8367c_setAsicSvlanUplinkPortMask\n * Description:\n *      Set uplink ports mask\n * Input:\n *      portMask    - Uplink port mask setting\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicSvlanUplinkPortMask(rtk_uint32 portMask)\n{\n    return rtl8367c_setAsicReg(RTL8367C_REG_SVLAN_UPLINK_PORTMASK, portMask);\n}\n/* Function Name:\n *      rtl8367c_getAsicSvlanUplinkPortMask\n * Description:\n *      Get uplink ports mask\n * Input:\n *      pPortmask   - Uplink port mask setting\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicSvlanUplinkPortMask(rtk_uint32* pPortmask)\n{\n    return rtl8367c_getAsicReg(RTL8367C_REG_SVLAN_UPLINK_PORTMASK, pPortmask);\n}\n/* Function Name:\n *      rtl8367c_setAsicSvlanTpid\n * Description:\n *      Set accepted S-VLAN ether type. The default ether type of S-VLAN is 0x88a8\n * Input:\n *      protocolType    - Ether type of S-tag frame parsing in uplink ports\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      Ether type of S-tag in 802.1ad is 0x88a8 and there are existed ether type 0x9100 and 0x9200\n *      for Q-in-Q SLAN design. User can set mathced ether type as service provider supported protocol\n */\nret_t rtl8367c_setAsicSvlanTpid(rtk_uint32 protocolType)\n{\n    return rtl8367c_setAsicReg(RTL8367C_REG_VS_TPID, protocolType);\n}\n/* Function Name:\n *      rtl8367c_getAsicReg\n * Description:\n *      Get accepted S-VLAN ether type. The default ether type of S-VLAN is 0x88a8\n * Input:\n *      pProtocolType   - Ether type of S-tag frame parsing in uplink ports\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicSvlanTpid(rtk_uint32* pProtocolType)\n{\n    return rtl8367c_getAsicReg(RTL8367C_REG_VS_TPID, pProtocolType);\n}\n/* Function Name:\n *      rtl8367c_setAsicSvlanPrioritySel\n * Description:\n *      Set SVLAN priority field setting\n * Input:\n *      priSel  - S-priority assignment method, 0:internal priority 1:C-tag priority 2:using Svlan member configuration\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n *      RT_ERR_INPUT    - Invalid input parameter\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicSvlanPrioritySel(rtk_uint32 priSel)\n{\n    if(priSel >= SPRISEL_END)\n        return RT_ERR_QOS_INT_PRIORITY;\n\n    return rtl8367c_setAsicRegBits(RTL8367C_REG_SVLAN_CFG, RTL8367C_VS_SPRISEL_MASK, priSel);\n}\n/* Function Name:\n *      rtl8367c_getAsicSvlanPrioritySel\n * Description:\n *      Get SVLAN priority field setting\n * Input:\n *      pPriSel     - S-priority assignment method, 0:internal priority 1:C-tag priority 2:using Svlan member configuration\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicSvlanPrioritySel(rtk_uint32* pPriSel)\n{\n    return rtl8367c_getAsicRegBits(RTL8367C_REG_SVLAN_CFG, RTL8367C_VS_SPRISEL_MASK, pPriSel);\n}\n/* Function Name:\n *      rtl8367c_setAsicSvlanTrapPriority\n * Description:\n *      Set trap to CPU priority assignment\n * Input:\n *      priority    - Priority assignment\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - Success\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_QOS_INT_PRIORITY - Invalid priority\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicSvlanTrapPriority(rtk_uint32 priority)\n{\n    if(priority > RTL8367C_PRIMAX)\n        return RT_ERR_QOS_INT_PRIORITY;\n\n    return rtl8367c_setAsicRegBits(RTL8367C_REG_QOS_TRAP_PRIORITY0, RTL8367C_SVLAN_PRIOIRTY_MASK, priority);\n}\n/* Function Name:\n *      rtl8367c_getAsicSvlanTrapPriority\n * Description:\n *      Get trap to CPU priority assignment\n * Input:\n *      pPriority   - Priority assignment\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicSvlanTrapPriority(rtk_uint32* pPriority)\n{\n    return rtl8367c_getAsicRegBits(RTL8367C_REG_QOS_TRAP_PRIORITY0, RTL8367C_SVLAN_PRIOIRTY_MASK, pPriority);\n}\n/* Function Name:\n *      rtl8367c_setAsicSvlanDefaultVlan\n * Description:\n *      Set default egress SVLAN\n * Input:\n *      port    - Physical port number (0~10)\n *      index   - index SVLAN member configuration\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK                   - Success\n *      RT_ERR_SMI                  - SMI access error\n *      RT_ERR_PORT_ID              - Invalid port number\n *      RT_ERR_SVLAN_ENTRY_INDEX    - Invalid SVLAN index parameter\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicSvlanDefaultVlan(rtk_uint32 port, rtk_uint32 index)\n{\n    ret_t retVal;\n\n    if(port > RTL8367C_PORTIDMAX)\n        return RT_ERR_PORT_ID;\n\n    if(index > RTL8367C_SVIDXMAX)\n        return RT_ERR_SVLAN_ENTRY_INDEX;\n\n    if(port < 8){\n        if(port & 1)\n            retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_SVLAN_PORTBASED_SVIDX_CTRL0 + (port >> 1), RTL8367C_VS_PORT1_SVIDX_MASK,index);\n        else\n            retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_SVLAN_PORTBASED_SVIDX_CTRL0 + (port >> 1), RTL8367C_VS_PORT0_SVIDX_MASK,index);\n    }else{\n        switch(port){\n            case 8:\n                retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_SVLAN_PORTBASED_SVIDX_CTRL4, RTL8367C_VS_PORT8_SVIDX_MASK,index);\n                break;\n\n            case 9:\n                retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_SVLAN_PORTBASED_SVIDX_CTRL4, RTL8367C_VS_PORT9_SVIDX_MASK,index);\n                break;\n\n            case 10:\n                retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_SVLAN_PORTBASED_SVIDX_CTRL5, RTL8367C_SVLAN_PORTBASED_SVIDX_CTRL5_MASK,index);\n                break;\n        }\n    }\n\n    return retVal;\n}\n/* Function Name:\n *      rtl8367c_getAsicSvlanDefaultVlan\n * Description:\n *      Get default egress SVLAN\n * Input:\n *      port    - Physical port number (0~7)\n *      pIndex  - index SVLAN member configuration\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n *      RT_ERR_PORT_ID  - Invalid port number\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicSvlanDefaultVlan(rtk_uint32 port, rtk_uint32* pIndex)\n{\n    ret_t retVal;\n\n    if(port > RTL8367C_PORTIDMAX)\n        return RT_ERR_PORT_ID;\n\n    if(port < 8){\n        if(port & 1)\n            retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_SVLAN_PORTBASED_SVIDX_CTRL0 + (port >> 1), RTL8367C_VS_PORT1_SVIDX_MASK,pIndex);\n        else\n            retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_SVLAN_PORTBASED_SVIDX_CTRL0 + (port >> 1), RTL8367C_VS_PORT0_SVIDX_MASK,pIndex);\n    }else{\n        switch(port){\n            case 8:\n                retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_SVLAN_PORTBASED_SVIDX_CTRL4, RTL8367C_VS_PORT8_SVIDX_MASK,pIndex);\n                break;\n\n            case 9:\n                retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_SVLAN_PORTBASED_SVIDX_CTRL4, RTL8367C_VS_PORT9_SVIDX_MASK,pIndex);\n                break;\n\n            case 10:\n                retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_SVLAN_PORTBASED_SVIDX_CTRL5, RTL8367C_SVLAN_PORTBASED_SVIDX_CTRL5_MASK,pIndex);\n                break;\n        }\n    }\n\n    return retVal;\n\n}\n/* Function Name:\n *      rtl8367c_setAsicSvlanIngressUntag\n * Description:\n *      Set action received un-Stag frame from unplink port\n * Input:\n *      mode        - 0:Drop 1:Trap 2:Assign SVLAN\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicSvlanIngressUntag(rtk_uint32 mode)\n{\n    return rtl8367c_setAsicRegBits(RTL8367C_REG_SVLAN_CFG, RTL8367C_VS_UNTAG_MASK, mode);\n}\n/* Function Name:\n *      rtl8367c_getAsicSvlanIngressUntag\n * Description:\n *      Get action received un-Stag frame from unplink port\n * Input:\n *      pMode       - 0:Drop 1:Trap 2:Assign SVLAN\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicSvlanIngressUntag(rtk_uint32* pMode)\n{\n    return rtl8367c_getAsicRegBits(RTL8367C_REG_SVLAN_CFG, RTL8367C_VS_UNTAG_MASK, pMode);\n}\n/* Function Name:\n *      rtl8367c_setAsicSvlanIngressUnmatch\n * Description:\n *      Set action received unmatched Stag frame from unplink port\n * Input:\n *      mode        - 0:Drop 1:Trap 2:Assign SVLAN\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicSvlanIngressUnmatch(rtk_uint32 mode)\n{\n    return rtl8367c_setAsicRegBits(RTL8367C_REG_SVLAN_CFG, RTL8367C_VS_UNMAT_MASK, mode);\n}\n/* Function Name:\n *      rtl8367c_getAsicSvlanIngressUnmatch\n * Description:\n *      Get action received unmatched Stag frame from unplink port\n * Input:\n *      pMode       - 0:Drop 1:Trap 2:Assign SVLAN\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicSvlanIngressUnmatch(rtk_uint32* pMode)\n{\n    return rtl8367c_getAsicRegBits(RTL8367C_REG_SVLAN_CFG, RTL8367C_VS_UNMAT_MASK, pMode);\n\n}\n/* Function Name:\n *      rtl8367c_setAsicSvlanEgressUnassign\n * Description:\n *      Set unplink stream without egress SVID action\n * Input:\n *      enabled     - 1:Trap egress unassigned frames to CPU, 0: Use SVLAN setup in VS_CPSVIDX as egress SVID\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicSvlanEgressUnassign(rtk_uint32 enabled)\n{\n    return rtl8367c_setAsicRegBit(RTL8367C_REG_SVLAN_CFG, RTL8367C_VS_UIFSEG_OFFSET, enabled);\n}\n/* Function Name:\n *      rtl8367c_getAsicSvlanEgressUnassign\n * Description:\n *      Get unplink stream without egress SVID action\n * Input:\n *      pEnabled    - 1:Trap egress unassigned frames to CPU, 0: Use SVLAN setup in VS_CPSVIDX as egress SVID\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicSvlanEgressUnassign(rtk_uint32* pEnabled)\n{\n    return rtl8367c_getAsicRegBit(RTL8367C_REG_SVLAN_CFG, RTL8367C_VS_UIFSEG_OFFSET, pEnabled);\n}\n\n\n/* Function Name:\n *      rtl8367c_setAsicSvlanMemberConfiguration\n * Description:\n *      Set system 64 S-tag content\n * Input:\n *      index           - index of 64 s-tag configuration\n *      pSvlanMemCfg    - SVLAN member configuration\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK                   - Success\n *      RT_ERR_SMI                  - SMI access error\n *      RT_ERR_SVLAN_ENTRY_INDEX    - Invalid SVLAN index parameter\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicSvlanMemberConfiguration(rtk_uint32 index, rtl8367c_svlan_memconf_t* pSvlanMemCfg)\n{\n    ret_t retVal;\n    rtk_uint32 regAddr, regData;\n    rtk_uint16 *accessPtr;\n    rtk_uint32 i;\n    rtk_uint16 smiSvlanMemConf[RTL8367C_SVLAN_MEMCONF_LEN];\n\n    if(index > RTL8367C_SVIDXMAX)\n        return RT_ERR_SVLAN_ENTRY_INDEX;\n\n    memset(smiSvlanMemConf, 0x00, sizeof(rtk_uint16) * RTL8367C_SVLAN_MEMCONF_LEN);\n    _rtl8367c_svlanConfStUser2Smi(pSvlanMemCfg, smiSvlanMemConf);\n\n    accessPtr = smiSvlanMemConf;\n\n    regData = *accessPtr;\n    for(i = 0; i < 3; i++)\n    {\n        retVal = rtl8367c_setAsicReg(RTL8367C_SVLAN_MEMBERCFG_BASE_REG(index) + i, regData);\n        if(retVal != RT_ERR_OK)\n            return retVal;\n\n        accessPtr ++;\n        regData = *accessPtr;\n    }\n\n    if(index < 63)\n        regAddr = RTL8367C_REG_SVLAN_MEMBERCFG0_CTRL4+index;\n    else if(index == 63)\n        regAddr = RTL8367C_REG_SVLAN_MEMBERCFG63_CTRL4;\n\n    retVal = rtl8367c_setAsicReg(regAddr, regData);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n\n}\n/* Function Name:\n *      rtl8367c_getAsicSvlanMemberConfiguration\n * Description:\n *      Get system 64 S-tag content\n * Input:\n *      index           - index of 64 s-tag configuration\n *      pSvlanMemCfg    - SVLAN member configuration\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK                   - Success\n *      RT_ERR_SMI                  - SMI access error\n *      RT_ERR_SVLAN_ENTRY_INDEX    - Invalid SVLAN index parameter\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicSvlanMemberConfiguration(rtk_uint32 index,rtl8367c_svlan_memconf_t* pSvlanMemCfg)\n{\n    ret_t retVal;\n    rtk_uint32 regAddr,regData;\n    rtk_uint16 *accessPtr;\n    rtk_uint32 i;\n    rtk_uint16 smiSvlanMemConf[RTL8367C_SVLAN_MEMCONF_LEN];\n\n    if(index > RTL8367C_SVIDXMAX)\n        return RT_ERR_SVLAN_ENTRY_INDEX;\n\n    memset(smiSvlanMemConf, 0x00, sizeof(rtk_uint16) * RTL8367C_SVLAN_MEMCONF_LEN);\n\n    accessPtr = smiSvlanMemConf;\n\n    for(i = 0; i < 3; i++)\n    {\n        retVal = rtl8367c_getAsicReg(RTL8367C_SVLAN_MEMBERCFG_BASE_REG(index) + i, &regData);\n        if(retVal != RT_ERR_OK)\n            return retVal;\n\n        *accessPtr = regData;\n\n        accessPtr ++;\n    }\n\n    if(index < 63)\n        regAddr = RTL8367C_REG_SVLAN_MEMBERCFG0_CTRL4+index;\n    else if(index == 63)\n        regAddr = RTL8367C_REG_SVLAN_MEMBERCFG63_CTRL4;\n\n    retVal = rtl8367c_getAsicReg(regAddr, &regData);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    *accessPtr = regData;\n\n    _rtl8367c_svlanConfStSmi2User(pSvlanMemCfg, smiSvlanMemConf);\n\n    return RT_ERR_OK;\n}\n/* Function Name:\n *      rtl8367c_setAsicSvlanC2SConf\n * Description:\n *      Set SVLAN C2S table\n * Input:\n *      index   - index of 128 Svlan C2S configuration\n *      evid    - Enhanced VID\n *      portmask    - available c2s port mask\n *      svidx   - index of 64 Svlan member configuration\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_ENTRY_INDEX  - Invalid entry index\n * Note:\n *      ASIC will check upstream's VID and assign related SVID to mathed packet\n */\nret_t rtl8367c_setAsicSvlanC2SConf(rtk_uint32 index, rtk_uint32 evid, rtk_uint32 portmask, rtk_uint32 svidx)\n{\n    ret_t retVal;\n\n    if(index > RTL8367C_C2SIDXMAX)\n        return RT_ERR_ENTRY_INDEX;\n\n    retVal = rtl8367c_setAsicReg(RTL8367C_SVLAN_C2SCFG_BASE_REG(index), svidx);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    retVal = rtl8367c_setAsicReg(RTL8367C_SVLAN_C2SCFG_BASE_REG(index) + 1, portmask);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    retVal = rtl8367c_setAsicReg(RTL8367C_SVLAN_C2SCFG_BASE_REG(index) + 2, evid);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n/* Function Name:\n *      rtl8367c_getAsicSvlanC2SConf\n * Description:\n *      Get SVLAN C2S table\n * Input:\n *      index   - index of 128 Svlan C2S configuration\n *      pEvid   - Enhanced VID\n *      pPortmask   - available c2s port mask\n *      pSvidx  - index of 64 Svlan member configuration\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_ENTRY_INDEX  - Invalid entry index\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicSvlanC2SConf(rtk_uint32 index, rtk_uint32* pEvid, rtk_uint32* pPortmask, rtk_uint32* pSvidx)\n{\n    ret_t retVal;\n\n    if(index > RTL8367C_C2SIDXMAX)\n        return RT_ERR_ENTRY_INDEX;\n\n    retVal = rtl8367c_getAsicReg(RTL8367C_SVLAN_C2SCFG_BASE_REG(index), pSvidx);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    retVal = rtl8367c_getAsicReg(RTL8367C_SVLAN_C2SCFG_BASE_REG(index) + 1, pPortmask);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    retVal = rtl8367c_getAsicReg(RTL8367C_SVLAN_C2SCFG_BASE_REG(index) + 2, pEvid);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtl8367c_setAsicSvlanMC2SConf\n * Description:\n *      Set system MC2S content\n * Input:\n *      index           - index of 32 SVLAN 32 MC2S configuration\n *      pSvlanMc2sCfg   - SVLAN Multicast to SVLAN member configuration\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_ENTRY_INDEX  - Invalid entry index\n * Note:\n *      If upstream packet is L2 multicast or IPv4 multicast packet and DMAC/DIP is matched MC2S\n *      configuration, ASIC will assign egress SVID to the packet\n */\nret_t rtl8367c_setAsicSvlanMC2SConf(rtk_uint32 index,rtl8367c_svlan_mc2s_t* pSvlanMc2sCfg)\n{\n    ret_t retVal;\n    rtk_uint32 regData;\n    rtk_uint16 *accessPtr;\n    rtk_uint32 i;\n    rtk_uint16 smiSvlanMC2S[RTL8367C_SVLAN_MC2S_LEN];\n\n    if(index > RTL8367C_MC2SIDXMAX)\n        return RT_ERR_ENTRY_INDEX;\n\n    memset(smiSvlanMC2S, 0x00, sizeof(rtk_uint16) * RTL8367C_SVLAN_MC2S_LEN);\n    _rtl8367c_svlanMc2sStUser2Smi(pSvlanMc2sCfg, smiSvlanMC2S);\n\n    accessPtr = smiSvlanMC2S;\n\n    regData = *accessPtr;\n    for(i = 0; i < 5; i++)\n    {\n        retVal = rtl8367c_setAsicReg(RTL8367C_SVLAN_MCAST2S_ENTRY_BASE_REG(index) + i, regData);\n        if(retVal != RT_ERR_OK)\n            return retVal;\n\n        accessPtr ++;\n        regData = *accessPtr;\n    }\n\n    return retVal;\n}\n/* Function Name:\n *      rtl8367c_getAsicSvlanMC2SConf\n * Description:\n *      Get system MC2S content\n * Input:\n *      index           - index of 32 SVLAN 32 MC2S configuration\n *      pSvlanMc2sCfg   - SVLAN Multicast to SVLAN member configuration\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_ENTRY_INDEX  - Invalid entry index\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicSvlanMC2SConf(rtk_uint32 index, rtl8367c_svlan_mc2s_t* pSvlanMc2sCfg)\n{\n    ret_t retVal;\n    rtk_uint32 regData;\n    rtk_uint16 *accessPtr;\n    rtk_uint32 i;\n    rtk_uint16 smiSvlanMC2S[RTL8367C_SVLAN_MC2S_LEN];\n\n    if(index > RTL8367C_MC2SIDXMAX)\n        return RT_ERR_ENTRY_INDEX;\n\n    memset(smiSvlanMC2S, 0x00, sizeof(rtk_uint16) * RTL8367C_SVLAN_MC2S_LEN);\n\n    accessPtr = smiSvlanMC2S;\n\n    for(i = 0; i < 5; i++)\n    {\n        retVal = rtl8367c_getAsicReg(RTL8367C_SVLAN_MCAST2S_ENTRY_BASE_REG(index) + i, &regData);\n        if(retVal != RT_ERR_OK)\n            return retVal;\n\n        *accessPtr = regData;\n        accessPtr ++;\n    }\n\n\n    _rtl8367c_svlanMc2sStSmi2User(pSvlanMc2sCfg, smiSvlanMC2S);\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtl8367c_setAsicSvlanSP2CConf\n * Description:\n *      Set system 128 SP2C content\n * Input:\n *      index           - index of 128 SVLAN & Port to CVLAN configuration\n *      pSvlanSp2cCfg   - SVLAN & Port to CVLAN configuration\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_ENTRY_INDEX  - Invalid entry index\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicSvlanSP2CConf(rtk_uint32 index, rtl8367c_svlan_s2c_t* pSvlanSp2cCfg)\n{\n    ret_t retVal;\n    rtk_uint32 regData;\n    rtk_uint16 *accessPtr;\n    rtk_uint32 i;\n    rtk_uint16 smiSvlanSP2C[RTL8367C_SVLAN_SP2C_LEN];\n\n    if(index > RTL8367C_SP2CMAX)\n        return RT_ERR_ENTRY_INDEX;\n\n    memset(smiSvlanSP2C, 0x00, sizeof(rtk_uint16) * RTL8367C_SVLAN_SP2C_LEN);\n    _rtl8367c_svlanSp2cStUser2Smi(pSvlanSp2cCfg,smiSvlanSP2C);\n\n    accessPtr = smiSvlanSP2C;\n\n    regData = *accessPtr;\n    for(i = 0; i < 2; i++)\n    {\n        retVal = rtl8367c_setAsicReg(RTL8367C_SVLAN_S2C_ENTRY_BASE_REG(index) + i, regData);\n        if(retVal != RT_ERR_OK)\n            return retVal;\n\n        accessPtr ++;\n        regData = *accessPtr;\n    }\n\n    return retVal;\n}\n/* Function Name:\n *      rtl8367c_getAsicSvlanSP2CConf\n * Description:\n *      Get system 128 SP2C content\n * Input:\n *      index           - index of 128 SVLAN & Port to CVLAN configuration\n *      pSvlanSp2cCfg   - SVLAN & Port to CVLAN configuration\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_ENTRY_INDEX  - Invalid entry index\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicSvlanSP2CConf(rtk_uint32 index,rtl8367c_svlan_s2c_t* pSvlanSp2cCfg)\n{\n    ret_t retVal;\n    rtk_uint32 regData;\n    rtk_uint16 *accessPtr;\n    rtk_uint32 i;\n    rtk_uint16 smiSvlanSP2C[RTL8367C_SVLAN_SP2C_LEN];\n\n    if(index > RTL8367C_SP2CMAX)\n        return RT_ERR_ENTRY_INDEX;\n\n    memset(smiSvlanSP2C, 0x00, sizeof(rtk_uint16) * RTL8367C_SVLAN_SP2C_LEN);\n\n    accessPtr = smiSvlanSP2C;\n\n    for(i = 0; i < 2; i++)\n    {\n        retVal = rtl8367c_getAsicReg(RTL8367C_SVLAN_S2C_ENTRY_BASE_REG(index) + i, &regData);\n        if(retVal != RT_ERR_OK)\n            return retVal;\n\n        *accessPtr = regData;\n\n        accessPtr ++;\n    }\n\n    _rtl8367c_svlanSp2cStSmi2User(pSvlanSp2cCfg, smiSvlanSP2C);\n\n    return RT_ERR_OK;\n}\n/* Function Name:\n *      rtl8367c_setAsicSvlanDmacCvidSel\n * Description:\n *      Set downstream CVID decision by DMAC\n * Input:\n *      port        - Physical port number (0~7)\n *      enabled     - 0:disabled, 1:enabled\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n *      RT_ERR_PORT_ID  - Invalid port number\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicSvlanDmacCvidSel(rtk_uint32 port, rtk_uint32 enabled)\n{\n    if(port > RTL8367C_PORTIDMAX)\n        return RT_ERR_PORT_ID;\n\n    if(port < 8)\n        return rtl8367c_setAsicRegBit(RTL8367C_REG_SVLAN_CFG, RTL8367C_VS_PORT0_DMACVIDSEL_OFFSET + port, enabled);\n    else\n        return rtl8367c_setAsicRegBit(RTL8367C_REG_SVLAN_CFG_EXT, RTL8367C_VS_PORT8_DMACVIDSEL_OFFSET + (port-8), enabled);\n}\n/* Function Name:\n *      rtl8367c_getAsicSvlanDmacCvidSel\n * Description:\n *      Get downstream CVID decision by DMAC\n * Input:\n *      port        - Physical port number (0~7)\n *      pEnabled    - 0:disabled, 1:enabled\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n *      RT_ERR_PORT_ID  - Invalid port number\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicSvlanDmacCvidSel(rtk_uint32 port, rtk_uint32* pEnabled)\n{\n    if(port > RTL8367C_PORTIDMAX)\n        return RT_ERR_PORT_ID;\n\n    if(port < 8)\n        return rtl8367c_getAsicRegBit(RTL8367C_REG_SVLAN_CFG, RTL8367C_VS_PORT0_DMACVIDSEL_OFFSET + port, pEnabled);\n    else\n        return rtl8367c_getAsicRegBit(RTL8367C_REG_SVLAN_CFG_EXT, RTL8367C_VS_PORT8_DMACVIDSEL_OFFSET + (port-8), pEnabled);\n}\n/* Function Name:\n *      rtl8367c_setAsicSvlanUntagVlan\n * Description:\n *      Set default ingress untag SVLAN\n * Input:\n *      index   - index SVLAN member configuration\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK                   - Success\n *      RT_ERR_SMI                  - SMI access error\n *      RT_ERR_SVLAN_ENTRY_INDEX    - Invalid SVLAN index parameter\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicSvlanUntagVlan(rtk_uint32 index)\n{\n    if(index > RTL8367C_SVIDXMAX)\n        return RT_ERR_SVLAN_ENTRY_INDEX;\n\n    return rtl8367c_setAsicRegBits(RTL8367C_REG_SVLAN_UNTAG_UNMAT_CFG, RTL8367C_VS_UNTAG_SVIDX_MASK, index);\n}\n/* Function Name:\n *      rtl8367c_getAsicSvlanUntagVlan\n * Description:\n *      Get default ingress untag SVLAN\n * Input:\n *      pIndex  - index SVLAN member configuration\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicSvlanUntagVlan(rtk_uint32* pIndex)\n{\n    return rtl8367c_getAsicRegBits(RTL8367C_REG_SVLAN_UNTAG_UNMAT_CFG, RTL8367C_VS_UNTAG_SVIDX_MASK, pIndex);\n}\n\n/* Function Name:\n *      rtl8367c_setAsicSvlanUnmatchVlan\n * Description:\n *      Set default ingress unmatch SVLAN\n * Input:\n *      index   - index SVLAN member configuration\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK                   - Success\n *      RT_ERR_SMI                  - SMI access error\n *      RT_ERR_SVLAN_ENTRY_INDEX    - Invalid SVLAN index parameter\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicSvlanUnmatchVlan(rtk_uint32 index)\n{\n    if(index > RTL8367C_SVIDXMAX)\n        return RT_ERR_SVLAN_ENTRY_INDEX;\n\n    return rtl8367c_setAsicRegBits(RTL8367C_REG_SVLAN_UNTAG_UNMAT_CFG, RTL8367C_VS_UNMAT_SVIDX_MASK, index);\n}\n/* Function Name:\n *      rtl8367c_getAsicSvlanUnmatchVlan\n * Description:\n *      Get default ingress unmatch SVLAN\n * Input:\n *      pIndex  - index SVLAN member configuration\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicSvlanUnmatchVlan(rtk_uint32* pIndex)\n{\n    return rtl8367c_getAsicRegBits(RTL8367C_REG_SVLAN_UNTAG_UNMAT_CFG, RTL8367C_VS_UNMAT_SVIDX_MASK, pIndex);\n}\n\n\n/* Function Name:\n *      rtl8367c_setAsicSvlanLookupType\n * Description:\n *      Set svlan lookup table selection\n * Input:\n *      type    - lookup type\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK                   - Success\n *      RT_ERR_SMI                  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicSvlanLookupType(rtk_uint32 type)\n{\n    return rtl8367c_setAsicRegBit(RTL8367C_REG_SVLAN_LOOKUP_TYPE, RTL8367C_SVLAN_LOOKUP_TYPE_OFFSET, type);\n}\n\n/* Function Name:\n *      rtl8367c_getAsicSvlanLookupType\n * Description:\n *      Get svlan lookup table selection\n * Input:\n *      pType   - lookup type\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK                   - Success\n *      RT_ERR_SMI                  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicSvlanLookupType(rtk_uint32* pType)\n{\n    return rtl8367c_getAsicRegBit(RTL8367C_REG_SVLAN_LOOKUP_TYPE, RTL8367C_SVLAN_LOOKUP_TYPE_OFFSET, pType);\n}\n\n\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_trunking.c",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * $Revision: 76306 $\n * $Date: 2017-03-08 15:13:58 +0800 (週三, 08 三月 2017) $\n *\n * Purpose : RTL8367C switch high-level API for RTL8367C\n * Feature : Port trunking related functions\n *\n */\n\n#include <rtl8367c_asicdrv_trunking.h>\n/* Function Name:\n *      rtl8367c_setAsicTrunkingMode\n * Description:\n *      Set port trunking mode\n * Input:\n *      mode    - 1:dumb 0:user defined\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicTrunkingMode(rtk_uint32 mode)\n{\n    return rtl8367c_setAsicRegBit(RTL8367C_REG_PORT_TRUNK_CTRL, RTL8367C_PORT_TRUNK_DUMB_OFFSET, mode);\n}\n/* Function Name:\n *      rtl8367c_getAsicTrunkingMode\n * Description:\n *      Get port trunking mode\n * Input:\n *      pMode   - 1:dumb 0:user defined\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicTrunkingMode(rtk_uint32* pMode)\n{\n    return rtl8367c_getAsicRegBit(RTL8367C_REG_PORT_TRUNK_CTRL, RTL8367C_PORT_TRUNK_DUMB_OFFSET, pMode);\n}\n/* Function Name:\n *      rtl8367c_setAsicTrunkingFc\n * Description:\n *      Set port trunking flow control\n * Input:\n *      group       - Trunk Group ID\n *      enabled     - 0:disable, 1:enable\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicTrunkingFc(rtk_uint32 group, rtk_uint32 enabled)\n{\n    ret_t       retVal;\n\n    if(group > RTL8367C_MAX_TRUNK_GID)\n        return RT_ERR_LA_TRUNK_ID;\n\n    if((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_PORT_TRUNK_DROP_CTRL, RTL8367C_PORT_TRUNK_DROP_CTRL_OFFSET, ENABLED)) != RT_ERR_OK)\n        return retVal;\n\n    return rtl8367c_setAsicRegBit(RTL8367C_REG_PORT_TRUNK_FLOWCTRL, (RTL8367C_EN_FLOWCTRL_TG0_OFFSET + group), enabled);\n}\n/* Function Name:\n *      rtl8367c_getAsicTrunkingFc\n * Description:\n *      Get port trunking flow control\n * Input:\n *      group       - Trunk Group ID\n *      pEnabled    - 0:disable, 1:enable\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicTrunkingFc(rtk_uint32 group, rtk_uint32* pEnabled)\n{\n    if(group > RTL8367C_MAX_TRUNK_GID)\n        return RT_ERR_LA_TRUNK_ID;\n\n    return rtl8367c_getAsicRegBit(RTL8367C_REG_PORT_TRUNK_FLOWCTRL, (RTL8367C_EN_FLOWCTRL_TG0_OFFSET + group), pEnabled);\n}\n/* Function Name:\n *      rtl8367c_setAsicTrunkingGroup\n * Description:\n *      Set trunking group available port mask\n * Input:\n *      group       - Trunk Group ID\n *      portmask    - Logic trunking enable port mask, max 4 ports\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicTrunkingGroup(rtk_uint32 group, rtk_uint32 portmask)\n{\n    if(group > RTL8367C_MAX_TRUNK_GID)\n        return RT_ERR_LA_TRUNK_ID;\n    return rtl8367c_setAsicRegBits(RTL8367C_REG_PORT_TRUNK_GROUP_MASK, RTL8367C_PORT_TRUNK_GROUP0_MASK_MASK << (group * 4), portmask);\n}\n/* Function Name:\n *      rtl8367c_getAsicTrunkingGroup\n * Description:\n *      Get trunking group available port mask\n * Input:\n *      group       - Trunk Group ID\n * Output:\n *      pPortmask   - Logic trunking enable port mask, max 4 ports\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicTrunkingGroup(rtk_uint32 group, rtk_uint32* pPortmask)\n{\n    if(group > RTL8367C_MAX_TRUNK_GID)\n        return RT_ERR_LA_TRUNK_ID;\n\n    return rtl8367c_getAsicRegBits(RTL8367C_REG_PORT_TRUNK_GROUP_MASK, RTL8367C_PORT_TRUNK_GROUP0_MASK_MASK << (group * 4), pPortmask);\n}\n/* Function Name:\n *      rtl8367c_setAsicTrunkingFlood\n * Description:\n *      Set port trunking flood function\n * Input:\n *      enabled     - Port trunking flooding function 0:disable 1:enable\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicTrunkingFlood(rtk_uint32 enabled)\n{\n    return rtl8367c_setAsicRegBit(RTL8367C_REG_PORT_TRUNK_CTRL, RTL8367C_PORT_TRUNK_FLOOD_OFFSET, enabled);\n}\n/* Function Name:\n *      rtl8367c_getAsicTrunkingFlood\n * Description:\n *      Get port trunking flood function\n * Input:\n *      pEnabled    - Port trunking flooding function 0:disable 1:enable\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicTrunkingFlood(rtk_uint32* pEnabled)\n{\n    return rtl8367c_getAsicRegBit(RTL8367C_REG_PORT_TRUNK_CTRL, RTL8367C_PORT_TRUNK_FLOOD_OFFSET, pEnabled);\n}\n/* Function Name:\n *      rtl8367c_setAsicTrunkingHashSelect\n * Description:\n *      Set port trunking hash select sources\n * Input:\n *      hashsel     - hash sources mask\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      7 bits mask for link aggregation group0 hash parameter selection {DIP, SIP, DMAC, SMAC, SPA}\n *      0b0000001: SPA\n *      0b0000010: SMAC\n *      0b0000100: DMAC\n *      0b0001000: SIP\n *      0b0010000: DIP\n *      0b0100000: TCP/UDP Source Port\n *      0b1000000: TCP/UDP Destination Port\n */\nret_t rtl8367c_setAsicTrunkingHashSelect(rtk_uint32 hashsel)\n{\n    return rtl8367c_setAsicRegBits(RTL8367C_REG_PORT_TRUNK_CTRL, RTL8367C_PORT_TRUNK_HASH_MASK, hashsel);\n}\n/* Function Name:\n *      rtl8367c_getAsicTrunkingHashSelect\n * Description:\n *      Get port trunking hash select sources\n * Input:\n *      pHashsel    - hash sources mask\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicTrunkingHashSelect(rtk_uint32* pHashsel)\n{\n    return rtl8367c_getAsicRegBits(RTL8367C_REG_PORT_TRUNK_CTRL, RTL8367C_PORT_TRUNK_HASH_MASK, pHashsel);\n}\n/* Function Name:\n *      rtl8367c_getAsicQeueuEmptyStatus\n * Description:\n *      Get current output queue if empty status\n * Input:\n *      portmask    - queue empty port mask\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicQeueuEmptyStatus(rtk_uint32* portmask)\n{\n    return rtl8367c_getAsicReg(RTL8367C_REG_PORT_QEMPTY, portmask);\n}\n/* Function Name:\n *      rtl8367c_setAsicTrunkingHashTable\n * Description:\n *      Set port trunking hash value mapping table\n * Input:\n *      hashval     - hashing value 0-15\n *      portId      - trunking port id 0-3\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number\n *      RT_ERR_OUT_OF_RANGE - Invalid hashing value (0-15)\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicTrunkingHashTable(rtk_uint32 hashval, rtk_uint32 portId)\n{\n    if(hashval > RTL8367C_TRUNKING_HASHVALUE_MAX)\n        return RT_ERR_OUT_OF_RANGE;\n\n    if(portId >= RTL8367C_TRUNKING_PORTNO)\n        return RT_ERR_PORT_ID;\n\n    if(hashval >= 8)\n        return rtl8367c_setAsicRegBits(RTL8367C_REG_PORT_TRUNK_HASH_MAPPING_CTRL1, RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL1_HASH8_MASK<<((hashval-8)*2), portId);\n    else\n        return rtl8367c_setAsicRegBits(RTL8367C_REG_PORT_TRUNK_HASH_MAPPING_CTRL0, RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL0_HASH0_MASK<<(hashval*2), portId);\n}\n/* Function Name:\n *      rtl8367c_getAsicTrunkingHashTable\n * Description:\n *      Get port trunking hash value mapping table\n * Input:\n *      hashval     - hashing value 0-15\n *      pPortId         - trunking port id 0-3\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_OUT_OF_RANGE - Invalid hashing value (0-15)\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicTrunkingHashTable(rtk_uint32 hashval, rtk_uint32* pPortId)\n{\n    if(hashval > RTL8367C_TRUNKING_HASHVALUE_MAX)\n        return RT_ERR_OUT_OF_RANGE;\n\n    if(hashval >= 8)\n        return rtl8367c_getAsicRegBits(RTL8367C_REG_PORT_TRUNK_HASH_MAPPING_CTRL1, RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL1_HASH8_MASK<<((hashval-8)*2), pPortId);\n    else\n        return rtl8367c_getAsicRegBits(RTL8367C_REG_PORT_TRUNK_HASH_MAPPING_CTRL0, RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL0_HASH0_MASK<<(hashval*2), pPortId);\n}\n\n/* Function Name:\n *      rtl8367c_setAsicTrunkingHashTable1\n * Description:\n *      Set port trunking hash value mapping table\n * Input:\n *      hashval     - hashing value 0-15\n *      portId      - trunking port id 0-3\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number\n *      RT_ERR_OUT_OF_RANGE - Invalid hashing value (0-15)\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicTrunkingHashTable1(rtk_uint32 hashval, rtk_uint32 portId)\n{\n    if(hashval > RTL8367C_TRUNKING_HASHVALUE_MAX)\n        return RT_ERR_OUT_OF_RANGE;\n\n    if(portId >= RTL8367C_TRUNKING1_PORTN0)\n        return RT_ERR_PORT_ID;\n\n    if(hashval >= 8)\n        return rtl8367c_setAsicRegBits(RTL8367C_REG_PORT_TRUNK_HASH_MAPPING_CTRL3, RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL3_HASH8_MASK<<((hashval-8)*2), portId);\n    else\n        return rtl8367c_setAsicRegBits(RTL8367C_REG_PORT_TRUNK_HASH_MAPPING_CTRL2, RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL2_HASH0_MASK<<(hashval*2), portId);\n}\n/* Function Name:\n *      rtl8367c_getAsicTrunkingHashTable1\n * Description:\n *      Get port trunking hash value mapping table\n * Input:\n *      hashval     - hashing value 0-15\n *      pPortId         - trunking port id 0-3\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_OUT_OF_RANGE - Invalid hashing value (0-15)\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicTrunkingHashTable1(rtk_uint32 hashval, rtk_uint32* pPortId)\n{\n    if(hashval > RTL8367C_TRUNKING_HASHVALUE_MAX)\n        return RT_ERR_OUT_OF_RANGE;\n\n    if(hashval >= 8)\n        return rtl8367c_getAsicRegBits(RTL8367C_REG_PORT_TRUNK_HASH_MAPPING_CTRL3, RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL3_HASH8_MASK<<((hashval-8)*2), pPortId);\n    else\n        return rtl8367c_getAsicRegBits(RTL8367C_REG_PORT_TRUNK_HASH_MAPPING_CTRL2, RTL8367C_PORT_TRUNK_HASH_MAPPING_CTRL2_HASH0_MASK<<(hashval*2), pPortId);\n}\n\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_unknownMulticast.c",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * $Revision: 76306 $\n * $Date: 2017-03-08 15:13:58 +0800 (週三, 08 三月 2017) $\n *\n * Purpose : RTL8367C switch high-level API for RTL8367C\n * Feature : Unkown multicast related functions\n *\n */\n\n#include <rtl8367c_asicdrv_unknownMulticast.h>\n\n/* Function Name:\n *      rtl8367c_setAsicUnknownL2MulticastBehavior\n * Description:\n *      Set behavior of L2 multicast\n * Input:\n *      port    - Physical port number (0~7)\n *      behave  - 0: flooding, 1: drop, 2: trap\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number\n *      RT_ERR_NOT_ALLOWED  - Invalid operation\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicUnknownL2MulticastBehavior(rtk_uint32 port, rtk_uint32 behave)\n{\n    ret_t retVal;\n\n    if(port >  RTL8367C_PORTIDMAX)\n        return RT_ERR_PORT_ID;\n\n    if(behave >= L2_UNKOWN_MULTICAST_END)\n        return RT_ERR_NOT_ALLOWED;\n    if(port < 8)\n    {\n        retVal = rtl8367c_setAsicRegBits(RTL8367C_UNKNOWN_L2_MULTICAST_REG(port), RTL8367C_UNKNOWN_L2_MULTICAST_MASK(port), behave);\n        if(retVal != RT_ERR_OK)\n            return retVal;\n    }\n    else\n    {\n        retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_UNKNOWN_L2_MULTICAST_CTRL1, 3 << ((port - 8) << 1), behave);\n        if(retVal != RT_ERR_OK)\n            return retVal;\n    }\n\n    return RT_ERR_OK;\n}\n/* Function Name:\n *      rtl8367c_getAsicUnknownL2MulticastBehavior\n * Description:\n *      Get behavior of L2 multicast\n * Input:\n *      port    - Physical port number (0~7)\n *      pBehave     - 0: flooding, 1: drop, 2: trap\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n *      RT_ERR_PORT_ID  - Invalid port number\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicUnknownL2MulticastBehavior(rtk_uint32 port, rtk_uint32 *pBehave)\n{\n    ret_t retVal;\n\n    if(port >  RTL8367C_PORTIDMAX)\n        return RT_ERR_PORT_ID;\n\n    if(port < 8)\n    {\n        retVal = rtl8367c_getAsicRegBits(RTL8367C_UNKNOWN_L2_MULTICAST_REG(port), RTL8367C_UNKNOWN_L2_MULTICAST_MASK(port), pBehave);\n        if (retVal != RT_ERR_OK)\n            return retVal;\n    }\n    else\n    {\n        retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_UNKNOWN_L2_MULTICAST_CTRL1, 3 << ((port - 8) << 1), pBehave);\n        if (retVal != RT_ERR_OK)\n            return retVal;\n    }\n\n    return RT_ERR_OK;\n}\n/* Function Name:\n *      rtl8367c_setAsicUnknownIPv4MulticastBehavior\n * Description:\n *      Set behavior of IPv4 multicast\n * Input:\n *      port    - Physical port number (0~7)\n *      behave  - 0: flooding, 1: drop, 2: trap\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number\n *      RT_ERR_NOT_ALLOWED  - Invalid operation\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicUnknownIPv4MulticastBehavior(rtk_uint32 port, rtk_uint32 behave)\n{\n    if(port >  RTL8367C_PORTIDMAX)\n        return RT_ERR_PORT_ID;\n\n    if(behave >= L3_UNKOWN_MULTICAST_END)\n        return RT_ERR_NOT_ALLOWED;\n\n    return rtl8367c_setAsicRegBits(RTL8367C_UNKNOWN_IPV4_MULTICAST_REG(port), RTL8367C_UNKNOWN_IPV4_MULTICAST_MASK(port), behave);\n}\n/* Function Name:\n *      rtl8367c_getAsicUnknownIPv4MulticastBehavior\n * Description:\n *      Get behavior of IPv4 multicast\n * Input:\n *      port    - Physical port number (0~7)\n *      pBehave     - 0: flooding, 1: drop, 2: trap\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n *      RT_ERR_PORT_ID  - Invalid port number\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicUnknownIPv4MulticastBehavior(rtk_uint32 port, rtk_uint32 *pBehave)\n{\n    if(port >  RTL8367C_PORTIDMAX)\n        return RT_ERR_PORT_ID;\n\n    return rtl8367c_getAsicRegBits(RTL8367C_UNKNOWN_IPV4_MULTICAST_REG(port), RTL8367C_UNKNOWN_IPV4_MULTICAST_MASK(port), pBehave);\n}\n/* Function Name:\n *      rtl8367c_setAsicUnknownIPv6MulticastBehavior\n * Description:\n *      Set behavior of IPv6 multicast\n * Input:\n *      port    - Physical port number (0~7)\n *      behave  - 0: flooding, 1: drop, 2: trap\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number\n *      RT_ERR_NOT_ALLOWED  - Invalid operation\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicUnknownIPv6MulticastBehavior(rtk_uint32 port, rtk_uint32 behave)\n{\n    if(port >  RTL8367C_PORTIDMAX)\n        return RT_ERR_PORT_ID;\n\n    if(behave >= L3_UNKOWN_MULTICAST_END)\n        return RT_ERR_NOT_ALLOWED;\n\n    return rtl8367c_setAsicRegBits(RTL8367C_UNKNOWN_IPV6_MULTICAST_REG(port), RTL8367C_UNKNOWN_IPV6_MULTICAST_MASK(port), behave);\n}\n/* Function Name:\n *      rtl8367c_getAsicUnknownIPv6MulticastBehavior\n * Description:\n *      Get behavior of IPv6 multicast\n * Input:\n *      port    - Physical port number (0~7)\n *      pBehave     - 0: flooding, 1: drop, 2: trap\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n *      RT_ERR_PORT_ID  - Invalid port number\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicUnknownIPv6MulticastBehavior(rtk_uint32 port, rtk_uint32 *pBehave)\n{\n    if(port >  RTL8367C_PORTIDMAX)\n        return RT_ERR_PORT_ID;\n\n    return rtl8367c_getAsicRegBits(RTL8367C_UNKNOWN_IPV6_MULTICAST_REG(port), RTL8367C_UNKNOWN_IPV6_MULTICAST_MASK(port), pBehave);\n}\n/* Function Name:\n *      rtl8367c_setAsicUnknownMulticastTrapPriority\n * Description:\n *      Set trap priority of unknown multicast frame\n * Input:\n *      priority    - priority (0~7)\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - Success\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_QOS_INT_PRIORITY - Invalid priority\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicUnknownMulticastTrapPriority(rtk_uint32 priority)\n{\n    if(priority > RTL8367C_PRIMAX)\n        return RT_ERR_QOS_INT_PRIORITY;\n\n    return rtl8367c_setAsicRegBits(RTL8367C_QOS_TRAP_PRIORITY_CTRL0_REG, RTL8367C_UNKNOWN_MC_PRIORTY_MASK, priority);\n}\n/* Function Name:\n *      rtl8367c_getAsicUnknownMulticastTrapPriority\n * Description:\n *      Get trap priority of unknown multicast frame\n * Input:\n *      pPriority   - priority (0~7)\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK   - Success\n *      RT_ERR_SMI  - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicUnknownMulticastTrapPriority(rtk_uint32 *pPriority)\n{\n    return rtl8367c_getAsicRegBits(RTL8367C_QOS_TRAP_PRIORITY_CTRL0_REG, RTL8367C_UNKNOWN_MC_PRIORTY_MASK, pPriority);\n}\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/rtl8367c_asicdrv_vlan.c",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * $Revision: 76306 $\n * $Date: 2017-03-08 15:13:58 +0800 (週三, 08 三月 2017) $\n *\n * Purpose : RTL8367C switch high-level API for RTL8367C\n * Feature : VLAN related functions\n *\n */\n#include <rtl8367c_asicdrv_vlan.h>\n\n#include <string.h>\n\n#if defined(CONFIG_RTL8367C_ASICDRV_TEST)\nrtl8367c_user_vlan4kentry Rtl8370sVirtualVlanTable[RTL8367C_VIDMAX + 1];\n#endif\n\nstatic void _rtl8367c_VlanMCStUser2Smi(rtl8367c_vlanconfiguser *pVlanCg, rtk_uint16 *pSmiVlanCfg)\n{\n    pSmiVlanCfg[0] |= pVlanCg->mbr & 0x07FF;\n\n    pSmiVlanCfg[1] |= pVlanCg->fid_msti & 0x000F;\n\n    pSmiVlanCfg[2] |= pVlanCg->vbpen & 0x0001;\n    pSmiVlanCfg[2] |= (pVlanCg->vbpri & 0x0007) << 1;\n    pSmiVlanCfg[2] |= (pVlanCg->envlanpol & 0x0001) << 4;\n    pSmiVlanCfg[2] |= (pVlanCg->meteridx & 0x003F) << 5;\n\n    pSmiVlanCfg[3] |= pVlanCg->evid & 0x1FFF;\n}\n\nstatic void _rtl8367c_VlanMCStSmi2User(rtk_uint16 *pSmiVlanCfg, rtl8367c_vlanconfiguser *pVlanCg)\n{\n    pVlanCg->mbr            = pSmiVlanCfg[0] & 0x07FF;\n    pVlanCg->fid_msti       = pSmiVlanCfg[1] & 0x000F;\n    pVlanCg->meteridx       = (pSmiVlanCfg[2] >> 5) & 0x003F;\n    pVlanCg->envlanpol      = (pSmiVlanCfg[2] >> 4) & 0x0001;\n    pVlanCg->vbpri          = (pSmiVlanCfg[2] >> 1) & 0x0007;\n    pVlanCg->vbpen          = pSmiVlanCfg[2] & 0x0001;\n    pVlanCg->evid           = pSmiVlanCfg[3] & 0x1FFF;\n}\n\nstatic void _rtl8367c_Vlan4kStUser2Smi(rtl8367c_user_vlan4kentry *pUserVlan4kEntry, rtk_uint16 *pSmiVlan4kEntry)\n{\n    pSmiVlan4kEntry[0] |= (pUserVlan4kEntry->mbr & 0x00FF);\n    pSmiVlan4kEntry[0] |= (pUserVlan4kEntry->untag & 0x00FF) << 8;\n\n    pSmiVlan4kEntry[1] |= (pUserVlan4kEntry->fid_msti & 0x000F);\n    pSmiVlan4kEntry[1] |= (pUserVlan4kEntry->vbpen & 0x0001) << 4;\n    pSmiVlan4kEntry[1] |= (pUserVlan4kEntry->vbpri & 0x0007) << 5;\n    pSmiVlan4kEntry[1] |= (pUserVlan4kEntry->envlanpol & 0x0001) << 8;\n    pSmiVlan4kEntry[1] |= (pUserVlan4kEntry->meteridx & 0x001F) << 9;\n    pSmiVlan4kEntry[1] |= (pUserVlan4kEntry->ivl_svl & 0x0001) << 14;\n\n    pSmiVlan4kEntry[2] |= ((pUserVlan4kEntry->mbr & 0x0700) >> 8);\n    pSmiVlan4kEntry[2] |= ((pUserVlan4kEntry->untag & 0x0700) >> 8) << 3;\n    pSmiVlan4kEntry[2] |= ((pUserVlan4kEntry->meteridx & 0x0020) >> 5) << 6;\n}\n\n\nstatic void _rtl8367c_Vlan4kStSmi2User(rtk_uint16 *pSmiVlan4kEntry, rtl8367c_user_vlan4kentry *pUserVlan4kEntry)\n{\n    pUserVlan4kEntry->mbr = (pSmiVlan4kEntry[0] & 0x00FF) | ((pSmiVlan4kEntry[2] & 0x0007) << 8);\n    pUserVlan4kEntry->untag = ((pSmiVlan4kEntry[0] & 0xFF00) >> 8) | (((pSmiVlan4kEntry[2] & 0x0038) >> 3) << 8);\n    pUserVlan4kEntry->fid_msti = pSmiVlan4kEntry[1] & 0x000F;\n    pUserVlan4kEntry->vbpen = (pSmiVlan4kEntry[1] & 0x0010) >> 4;\n    pUserVlan4kEntry->vbpri = (pSmiVlan4kEntry[1] & 0x00E0) >> 5;\n    pUserVlan4kEntry->envlanpol = (pSmiVlan4kEntry[1] & 0x0100) >> 8;\n    pUserVlan4kEntry->meteridx = ((pSmiVlan4kEntry[1] & 0x3E00) >> 9) | (((pSmiVlan4kEntry[2] & 0x0040) >> 6) << 5);\n    pUserVlan4kEntry->ivl_svl = (pSmiVlan4kEntry[1] & 0x4000) >> 14;\n}\n\n/* Function Name:\n *      rtl8367c_setAsicVlanMemberConfig\n * Description:\n *      Set 32 VLAN member configurations\n * Input:\n *      index       - VLAN member configuration index (0~31)\n *      pVlanCg - VLAN member configuration\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK                   - Success\n *      RT_ERR_SMI                  - SMI access error\n *      RT_ERR_INPUT                - Invalid input parameter\n *      RT_ERR_L2_FID               - Invalid FID\n *      RT_ERR_PORT_MASK            - Invalid portmask\n *      RT_ERR_FILTER_METER_ID      - Invalid meter\n *      RT_ERR_QOS_INT_PRIORITY     - Invalid priority\n *      RT_ERR_VLAN_ENTRY_NOT_FOUND - Invalid VLAN member configuration index\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicVlanMemberConfig(rtk_uint32 index, rtl8367c_vlanconfiguser *pVlanCg)\n{\n    ret_t  retVal;\n    rtk_uint32 regAddr;\n    rtk_uint32 regData;\n    rtk_uint16 *tableAddr;\n    rtk_uint32 page_idx;\n    rtk_uint16 smi_vlancfg[RTL8367C_VLAN_MBRCFG_LEN];\n\n    /* Error Checking  */\n    if(index > RTL8367C_CVIDXMAX)\n        return RT_ERR_VLAN_ENTRY_NOT_FOUND;\n\n    if(pVlanCg->evid > RTL8367C_EVIDMAX)\n        return RT_ERR_INPUT;\n\n\n    if(pVlanCg->mbr > RTL8367C_PORTMASK)\n        return RT_ERR_PORT_MASK;\n\n    if(pVlanCg->fid_msti > RTL8367C_FIDMAX)\n        return RT_ERR_L2_FID;\n\n    if(pVlanCg->meteridx > RTL8367C_METERMAX)\n        return RT_ERR_FILTER_METER_ID;\n\n    if(pVlanCg->vbpri > RTL8367C_PRIMAX)\n        return RT_ERR_QOS_INT_PRIORITY;\n\n    memset(smi_vlancfg, 0x00, sizeof(rtk_uint16) * RTL8367C_VLAN_MBRCFG_LEN);\n    _rtl8367c_VlanMCStUser2Smi(pVlanCg, smi_vlancfg);\n    tableAddr = smi_vlancfg;\n\n    for(page_idx = 0; page_idx < 4; page_idx++)  /* 4 pages per VLAN Member Config */\n    {\n        regAddr = RTL8367C_VLAN_MEMBER_CONFIGURATION_BASE + (index * 4) + page_idx;\n        regData = *tableAddr;\n\n        retVal = rtl8367c_setAsicReg(regAddr, regData);\n        if(retVal != RT_ERR_OK)\n            return retVal;\n\n        tableAddr++;\n    }\n\n    return RT_ERR_OK;\n}\n/* Function Name:\n *      rtl8367c_getAsicVlanMemberConfig\n * Description:\n *      Get 32 VLAN member configurations\n * Input:\n *      index       - VLAN member configuration index (0~31)\n *      pVlanCg - VLAN member configuration\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK                   - Success\n *      RT_ERR_SMI                  - SMI access error\n *      RT_ERR_INPUT                - Invalid input parameter\n *      RT_ERR_VLAN_ENTRY_NOT_FOUND - Invalid VLAN member configuration index\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicVlanMemberConfig(rtk_uint32 index, rtl8367c_vlanconfiguser *pVlanCg)\n{\n    ret_t  retVal;\n    rtk_uint32 page_idx;\n    rtk_uint32 regAddr;\n    rtk_uint32 regData;\n    rtk_uint16 *tableAddr;\n    rtk_uint16 smi_vlancfg[RTL8367C_VLAN_MBRCFG_LEN];\n\n    if(index > RTL8367C_CVIDXMAX)\n        return RT_ERR_VLAN_ENTRY_NOT_FOUND;\n\n    memset(smi_vlancfg, 0x00, sizeof(rtk_uint16) * RTL8367C_VLAN_MBRCFG_LEN);\n    tableAddr  = smi_vlancfg;\n\n    for(page_idx = 0; page_idx < 4; page_idx++)  /* 4 pages per VLAN Member Config */\n    {\n        regAddr = RTL8367C_VLAN_MEMBER_CONFIGURATION_BASE + (index * 4) + page_idx;\n\n        retVal = rtl8367c_getAsicReg(regAddr, &regData);\n        if(retVal != RT_ERR_OK)\n            return retVal;\n\n        *tableAddr = (rtk_uint16)regData;\n        tableAddr++;\n    }\n\n    _rtl8367c_VlanMCStSmi2User(smi_vlancfg, pVlanCg);\n    return RT_ERR_OK;\n}\n/* Function Name:\n *      rtl8367c_setAsicVlan4kEntry\n * Description:\n *      Set VID mapped entry to 4K VLAN table\n * Input:\n *      pVlan4kEntry - 4K VLAN configuration\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK                   - Success\n *      RT_ERR_SMI                  - SMI access error\n *      RT_ERR_INPUT                - Invalid input parameter\n *      RT_ERR_L2_FID               - Invalid FID\n *      RT_ERR_VLAN_VID             - Invalid VID parameter (0~4095)\n *      RT_ERR_PORT_MASK            - Invalid portmask\n *      RT_ERR_FILTER_METER_ID      - Invalid meter\n *      RT_ERR_QOS_INT_PRIORITY     - Invalid priority\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicVlan4kEntry(rtl8367c_user_vlan4kentry *pVlan4kEntry )\n{\n    rtk_uint16              vlan_4k_entry[RTL8367C_VLAN_4KTABLE_LEN];\n    rtk_uint32                  page_idx;\n    rtk_uint16                  *tableAddr;\n    ret_t                   retVal;\n    rtk_uint32                  regData;\n\n    if(pVlan4kEntry->vid > RTL8367C_VIDMAX)\n        return RT_ERR_VLAN_VID;\n\n    if(pVlan4kEntry->mbr > RTL8367C_PORTMASK)\n        return RT_ERR_PORT_MASK;\n\n    if(pVlan4kEntry->untag > RTL8367C_PORTMASK)\n        return RT_ERR_PORT_MASK;\n\n    if(pVlan4kEntry->fid_msti > RTL8367C_FIDMAX)\n        return RT_ERR_L2_FID;\n\n    if(pVlan4kEntry->meteridx > RTL8367C_METERMAX)\n        return RT_ERR_FILTER_METER_ID;\n\n    if(pVlan4kEntry->vbpri > RTL8367C_PRIMAX)\n        return RT_ERR_QOS_INT_PRIORITY;\n\n    memset(vlan_4k_entry, 0x00, sizeof(rtk_uint16) * RTL8367C_VLAN_4KTABLE_LEN);\n    _rtl8367c_Vlan4kStUser2Smi(pVlan4kEntry, vlan_4k_entry);\n\n    /* Prepare Data */\n    tableAddr = vlan_4k_entry;\n    for(page_idx = 0; page_idx < RTL8367C_VLAN_4KTABLE_LEN; page_idx++)\n    {\n        regData = *tableAddr;\n        retVal = rtl8367c_setAsicReg(RTL8367C_TABLE_ACCESS_WRDATA_BASE + page_idx, regData);\n        if(retVal != RT_ERR_OK)\n            return retVal;\n\n        tableAddr++;\n    }\n\n    /* Write Address (VLAN_ID) */\n    regData = pVlan4kEntry->vid;\n    retVal = rtl8367c_setAsicReg(RTL8367C_TABLE_ACCESS_ADDR_REG, regData);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    /* Write Command */\n    retVal = rtl8367c_setAsicRegBits(RTL8367C_TABLE_ACCESS_CTRL_REG, RTL8367C_TABLE_TYPE_MASK | RTL8367C_COMMAND_TYPE_MASK,RTL8367C_TABLE_ACCESS_REG_DATA(TB_OP_WRITE,TB_TARGET_CVLAN));\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n#if defined(CONFIG_RTL8367C_ASICDRV_TEST)\n    memcpy(&Rtl8370sVirtualVlanTable[pVlan4kEntry->vid], pVlan4kEntry, sizeof(rtl8367c_user_vlan4kentry));\n#endif\n\n    return RT_ERR_OK;\n}\n/* Function Name:\n *      rtl8367c_getAsicVlan4kEntry\n * Description:\n *      Get VID mapped entry to 4K VLAN table\n * Input:\n *      pVlan4kEntry - 4K VLAN configuration\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - Success\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_VLAN_VID         - Invalid VID parameter (0~4095)\n *      RT_ERR_BUSYWAIT_TIMEOUT - LUT is busy at retrieving\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicVlan4kEntry(rtl8367c_user_vlan4kentry *pVlan4kEntry )\n{\n    rtk_uint16                  vlan_4k_entry[RTL8367C_VLAN_4KTABLE_LEN];\n    rtk_uint32                  page_idx;\n    rtk_uint16                  *tableAddr;\n    ret_t                       retVal;\n    rtk_uint32                  regData;\n    rtk_uint32                  busyCounter;\n\n    if(pVlan4kEntry->vid > RTL8367C_VIDMAX)\n        return RT_ERR_VLAN_VID;\n\n    /* Polling status */\n    busyCounter = RTL8367C_VLAN_BUSY_CHECK_NO;\n    while(busyCounter)\n    {\n        retVal = rtl8367c_getAsicRegBit(RTL8367C_TABLE_ACCESS_STATUS_REG, RTL8367C_TABLE_LUT_ADDR_BUSY_FLAG_OFFSET,&regData);\n        if(retVal != RT_ERR_OK)\n            return retVal;\n\n        if(regData == 0)\n            break;\n\n        busyCounter --;\n        if(busyCounter == 0)\n            return RT_ERR_BUSYWAIT_TIMEOUT;\n    }\n\n    /* Write Address (VLAN_ID) */\n    regData = pVlan4kEntry->vid;\n    retVal = rtl8367c_setAsicReg(RTL8367C_TABLE_ACCESS_ADDR_REG, regData);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    /* Read Command */\n    retVal = rtl8367c_setAsicRegBits(RTL8367C_TABLE_ACCESS_CTRL_REG, RTL8367C_TABLE_TYPE_MASK | RTL8367C_COMMAND_TYPE_MASK, RTL8367C_TABLE_ACCESS_REG_DATA(TB_OP_READ,TB_TARGET_CVLAN));\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    /* Polling status */\n    busyCounter = RTL8367C_VLAN_BUSY_CHECK_NO;\n    while(busyCounter)\n    {\n        retVal = rtl8367c_getAsicRegBit(RTL8367C_TABLE_ACCESS_STATUS_REG, RTL8367C_TABLE_LUT_ADDR_BUSY_FLAG_OFFSET,&regData);\n        if(retVal != RT_ERR_OK)\n            return retVal;\n\n        if(regData == 0)\n            break;\n\n        busyCounter --;\n        if(busyCounter == 0)\n            return RT_ERR_BUSYWAIT_TIMEOUT;\n    }\n\n    /* Read VLAN data from register */\n    tableAddr = vlan_4k_entry;\n    for(page_idx = 0; page_idx < RTL8367C_VLAN_4KTABLE_LEN; page_idx++)\n    {\n        retVal = rtl8367c_getAsicReg(RTL8367C_TABLE_ACCESS_RDDATA_BASE + page_idx, &regData);\n        if(retVal != RT_ERR_OK)\n            return retVal;\n\n        *tableAddr = regData;\n        tableAddr++;\n    }\n\n    _rtl8367c_Vlan4kStSmi2User(vlan_4k_entry, pVlan4kEntry);\n\n#if defined(CONFIG_RTL8367C_ASICDRV_TEST)\n    memcpy(pVlan4kEntry, &Rtl8370sVirtualVlanTable[pVlan4kEntry->vid], sizeof(rtl8367c_user_vlan4kentry));\n#endif\n\n    return RT_ERR_OK;\n}\n/* Function Name:\n *      rtl8367c_setAsicVlanAccpetFrameType\n * Description:\n *      Set per-port acceptable frame type\n * Input:\n *      port        - Physical port number (0~10)\n *      frameType   - The acceptable frame type\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK                       - Success\n *      RT_ERR_SMI                      - SMI access error\n *      RT_ERR_PORT_ID                  - Invalid port number\n *      RT_ERR_VLAN_ACCEPT_FRAME_TYPE   - Invalid frame type\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicVlanAccpetFrameType(rtk_uint32 port, rtl8367c_accframetype frameType)\n{\n    if(port > RTL8367C_PORTIDMAX)\n        return RT_ERR_PORT_ID;\n\n    if(frameType >= FRAME_TYPE_MAX_BOUND)\n        return RT_ERR_VLAN_ACCEPT_FRAME_TYPE;\n\n    return rtl8367c_setAsicRegBits(RTL8367C_VLAN_ACCEPT_FRAME_TYPE_REG(port), RTL8367C_VLAN_ACCEPT_FRAME_TYPE_MASK(port), frameType);\n}\n/* Function Name:\n *      rtl8367c_getAsicVlanAccpetFrameType\n * Description:\n *      Get per-port acceptable frame type\n * Input:\n *      port        - Physical port number (0~10)\n *      pFrameType  - The acceptable frame type\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK                       - Success\n *      RT_ERR_SMI                      - SMI access error\n *      RT_ERR_PORT_ID                  - Invalid port number\n *      RT_ERR_VLAN_ACCEPT_FRAME_TYPE   - Invalid frame type\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicVlanAccpetFrameType(rtk_uint32 port, rtl8367c_accframetype *pFrameType)\n{\n    rtk_uint32 regData;\n    ret_t  retVal;\n\n    if(port > RTL8367C_PORTIDMAX)\n        return RT_ERR_PORT_ID;\n\n    if((retVal = rtl8367c_getAsicRegBits(RTL8367C_VLAN_ACCEPT_FRAME_TYPE_REG(port), RTL8367C_VLAN_ACCEPT_FRAME_TYPE_MASK(port), &regData)) != RT_ERR_OK)\n        return retVal;\n\n    *pFrameType = (rtl8367c_accframetype)regData;\n    return RT_ERR_OK;\n}\n/* Function Name:\n *      rtl8367c_setAsicVlanIngressFilter\n * Description:\n *      Set VLAN Ingress Filter\n * Input:\n *      port        - Physical port number (0~10)\n *      enabled     - Enable or disable Ingress filter\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n *      RT_ERR_PORT_ID  - Invalid port number\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicVlanIngressFilter(rtk_uint32 port, rtk_uint32 enabled)\n{\n    if(port > RTL8367C_PORTIDMAX)\n        return RT_ERR_PORT_ID;\n\n    return rtl8367c_setAsicRegBit(RTL8367C_VLAN_INGRESS_REG, port, enabled);\n}\n/* Function Name:\n *      rtl8367c_getAsicVlanIngressFilter\n * Description:\n *      Get VLAN Ingress Filter\n * Input:\n *      port        - Physical port number (0~10)\n *      pEnable     - Enable or disable Ingress filter\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n *      RT_ERR_PORT_ID  - Invalid port number\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicVlanIngressFilter(rtk_uint32 port, rtk_uint32 *pEnable)\n{\n    if(port > RTL8367C_PORTIDMAX)\n        return RT_ERR_PORT_ID;\n\n    return rtl8367c_getAsicRegBit(RTL8367C_VLAN_INGRESS_REG, port, pEnable);\n}\n/* Function Name:\n *      rtl8367c_setAsicVlanEgressTagMode\n * Description:\n *      Set CVLAN egress tag mode\n * Input:\n *      port        - Physical port number (0~10)\n *      tagMode     - The egress tag mode. Including Original mode, Keep tag mode and Priority tag mode\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n *      RT_ERR_INPUT    - Invalid input parameter\n *      RT_ERR_PORT_ID  - Invalid port number\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicVlanEgressTagMode(rtk_uint32 port, rtl8367c_egtagmode tagMode)\n{\n    if(port > RTL8367C_PORTIDMAX)\n        return RT_ERR_PORT_ID;\n\n    if(tagMode >= EG_TAG_MODE_END)\n        return RT_ERR_INPUT;\n\n    return rtl8367c_setAsicRegBits(RTL8367C_PORT_MISC_CFG_REG(port), RTL8367C_VLAN_EGRESS_MDOE_MASK, tagMode);\n}\n/* Function Name:\n *      rtl8367c_getAsicVlanEgressTagMode\n * Description:\n *      Get CVLAN egress tag mode\n * Input:\n *      port        - Physical port number (0~10)\n *      pTagMode    - The egress tag mode. Including Original mode, Keep tag mode and Priority tag mode\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n *      RT_ERR_PORT_ID  - Invalid port number\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicVlanEgressTagMode(rtk_uint32 port, rtl8367c_egtagmode *pTagMode)\n{\n    rtk_uint32 regData;\n    ret_t  retVal;\n\n    if(port > RTL8367C_PORTIDMAX)\n        return RT_ERR_PORT_ID;\n\n    if((retVal = rtl8367c_getAsicRegBits(RTL8367C_PORT_MISC_CFG_REG(port), RTL8367C_VLAN_EGRESS_MDOE_MASK, &regData)) != RT_ERR_OK)\n        return retVal;\n\n    *pTagMode = (rtl8367c_egtagmode)regData;\n    return RT_ERR_OK;\n}\n/* Function Name:\n *      rtl8367c_setAsicVlanPortBasedVID\n * Description:\n *      Set port based VID which is indexed to 32 VLAN member configurations\n * Input:\n *      port    - Physical port number (0~10)\n *      index   - Index to VLAN member configuration\n *      pri     - 1Q Port based VLAN priority\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK                   - Success\n *      RT_ERR_SMI                  - SMI access error\n *      RT_ERR_PORT_ID              - Invalid port number\n *      RT_ERR_QOS_INT_PRIORITY     - Invalid priority\n *      RT_ERR_VLAN_ENTRY_NOT_FOUND - Invalid VLAN member configuration index\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicVlanPortBasedVID(rtk_uint32 port, rtk_uint32 index, rtk_uint32 pri)\n{\n    rtk_uint32 regAddr, bit_mask;\n    ret_t  retVal;\n\n    if(port > RTL8367C_PORTIDMAX)\n        return RT_ERR_PORT_ID;\n\n    if(index > RTL8367C_CVIDXMAX)\n        return RT_ERR_VLAN_ENTRY_NOT_FOUND;\n\n    if(pri > RTL8367C_PRIMAX)\n        return RT_ERR_QOS_INT_PRIORITY;\n\n    regAddr = RTL8367C_VLAN_PVID_CTRL_REG(port);\n    bit_mask = RTL8367C_PORT_VIDX_MASK(port);\n    retVal = rtl8367c_setAsicRegBits(regAddr, bit_mask, index);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    regAddr = RTL8367C_VLAN_PORTBASED_PRIORITY_REG(port);\n    bit_mask = RTL8367C_VLAN_PORTBASED_PRIORITY_MASK(port);\n    retVal = rtl8367c_setAsicRegBits(regAddr, bit_mask, pri);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n/* Function Name:\n *      rtl8367c_getAsicVlanPortBasedVID\n * Description:\n *      Get port based VID which is indexed to 32 VLAN member configurations\n * Input:\n *      port    - Physical port number (0~10)\n *      pIndex  - Index to VLAN member configuration\n *      pPri    - 1Q Port based VLAN priority\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n *      RT_ERR_PORT_ID  - Invalid port number\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicVlanPortBasedVID(rtk_uint32 port, rtk_uint32 *pIndex, rtk_uint32 *pPri)\n{\n    rtk_uint32 regAddr,bit_mask;\n    ret_t  retVal;\n\n    if(port > RTL8367C_PORTIDMAX)\n        return RT_ERR_PORT_ID;\n\n    regAddr = RTL8367C_VLAN_PVID_CTRL_REG(port);\n    bit_mask = RTL8367C_PORT_VIDX_MASK(port);\n    retVal = rtl8367c_getAsicRegBits(regAddr, bit_mask, pIndex);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    regAddr = RTL8367C_VLAN_PORTBASED_PRIORITY_REG(port);\n    bit_mask = RTL8367C_VLAN_PORTBASED_PRIORITY_MASK(port);\n    retVal = rtl8367c_getAsicRegBits(regAddr, bit_mask, pPri);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n/* Function Name:\n *      rtl8367c_setAsicVlanProtocolBasedGroupData\n * Description:\n *      Set protocol and port based group database\n * Input:\n *      index       - Index to VLAN member configuration\n *      pPbCfg  - Protocol and port based group database entry\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK                   - Success\n *      RT_ERR_SMI                  - SMI access error\n *      RT_ERR_INPUT                - Invalid input parameter\n *      RT_ERR_VLAN_PROTO_AND_PORT  - Invalid protocol base group database index\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicVlanProtocolBasedGroupData(rtk_uint32 index, rtl8367c_protocolgdatacfg *pPbCfg)\n{\n    rtk_uint32  frameType;\n    rtk_uint32  etherType;\n    ret_t   retVal;\n\n    /* Error Checking */\n    if(index > RTL8367C_PROTOVLAN_GIDX_MAX)\n        return RT_ERR_VLAN_PROTO_AND_PORT;\n\n    if(pPbCfg->frameType >= PPVLAN_FRAME_TYPE_END )\n        return RT_ERR_INPUT;\n\n    frameType = pPbCfg->frameType;\n    etherType = pPbCfg->etherType;\n\n    /* Frame type */\n    retVal = rtl8367c_setAsicRegBits(RTL8367C_VLAN_PPB_FRAMETYPE_REG(index), RTL8367C_VLAN_PPB_FRAMETYPE_MASK, frameType);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    /* Ether type */\n    retVal = rtl8367c_setAsicReg(RTL8367C_VLAN_PPB_ETHERTYPR_REG(index), etherType);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n/* Function Name:\n *      rtl8367c_getAsicVlanProtocolBasedGroupData\n * Description:\n *      Get protocol and port based group database\n * Input:\n *      index       - Index to VLAN member configuration\n *      pPbCfg  - Protocol and port based group database entry\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK                   - Success\n *      RT_ERR_SMI                  - SMI access error\n *      RT_ERR_INPUT                - Invalid input parameter\n *      RT_ERR_VLAN_PROTO_AND_PORT  - Invalid protocol base group database index\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicVlanProtocolBasedGroupData(rtk_uint32 index, rtl8367c_protocolgdatacfg *pPbCfg)\n{\n    rtk_uint32  frameType;\n    rtk_uint32  etherType;\n    ret_t   retVal;\n\n    /* Error Checking */\n    if(index > RTL8367C_PROTOVLAN_GIDX_MAX)\n        return RT_ERR_VLAN_PROTO_AND_PORT;\n\n    /* Read Frame type */\n    retVal = rtl8367c_getAsicRegBits(RTL8367C_VLAN_PPB_FRAMETYPE_REG(index), RTL8367C_VLAN_PPB_FRAMETYPE_MASK, &frameType);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    /* Read Ether type */\n    retVal = rtl8367c_getAsicReg(RTL8367C_VLAN_PPB_ETHERTYPR_REG(index), &etherType);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n\n    pPbCfg->frameType = frameType;\n    pPbCfg->etherType = etherType;\n    return RT_ERR_OK;\n}\n/* Function Name:\n *      rtl8367c_setAsicVlanPortAndProtocolBased\n * Description:\n *      Set protocol and port based VLAN configuration\n * Input:\n *      port        - Physical port number (0~10)\n *      index       - Index of protocol and port based database index\n *      pPpbCfg     - Protocol and port based VLAN configuration\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK                   - Success\n *      RT_ERR_SMI                  - SMI access error\n *      RT_ERR_INPUT                - Invalid input parameter\n *      RT_ERR_PORT_ID              - Invalid port number\n *      RT_ERR_QOS_INT_PRIORITY     - Invalid priority\n *      RT_ERR_VLAN_PROTO_AND_PORT  - Invalid protocol base group database index\n *      RT_ERR_VLAN_ENTRY_NOT_FOUND - Invalid VLAN member configuration index\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicVlanPortAndProtocolBased(rtk_uint32 port, rtk_uint32 index, rtl8367c_protocolvlancfg *pPpbCfg)\n{\n    rtk_uint32  reg_addr, bit_mask, bit_value;\n    ret_t   retVal;\n\n    /* Error Checking */\n    if(port > RTL8367C_PORTIDMAX)\n        return RT_ERR_PORT_ID;\n\n    if(index > RTL8367C_PROTOVLAN_GIDX_MAX)\n        return RT_ERR_VLAN_PROTO_AND_PORT;\n\n    if( (pPpbCfg->valid != FALSE) && (pPpbCfg->valid != TRUE) )\n        return RT_ERR_INPUT;\n\n    if(pPpbCfg->vlan_idx > RTL8367C_CVIDXMAX)\n        return RT_ERR_VLAN_ENTRY_NOT_FOUND;\n\n    if(pPpbCfg->priority > RTL8367C_PRIMAX)\n        return RT_ERR_QOS_INT_PRIORITY;\n\n    /* Valid bit */\n    reg_addr  = RTL8367C_VLAN_PPB_VALID_REG(index);\n    bit_mask  = 0x0001 << port;\n    bit_value = ((TRUE == pPpbCfg->valid) ? 0x1 : 0x0);\n    retVal    = rtl8367c_setAsicRegBits(reg_addr, bit_mask, bit_value);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    /* Calculate the actual register address for CVLAN index*/\n    if(port < 8)\n    {\n        reg_addr = RTL8367C_VLAN_PPB_CTRL_REG(index, port);\n        bit_mask = RTL8367C_VLAN_PPB_CTRL_MASK(port);\n    }\n    else if(port == 8)\n    {\n        reg_addr = RTL8367C_REG_VLAN_PPB0_CTRL4;\n        bit_mask = RTL8367C_VLAN_PPB0_CTRL4_PORT8_INDEX_MASK;\n    }\n    else if(port == 9)\n    {\n        reg_addr = RTL8367C_REG_VLAN_PPB0_CTRL4;\n        bit_mask = RTL8367C_VLAN_PPB0_CTRL4_PORT9_INDEX_MASK;\n    }\n    else if(port == 10)\n    {\n        reg_addr = RTL8367C_REG_VLAN_PPB0_CTRL4;\n        bit_mask = RTL8367C_VLAN_PPB0_CTRL4_PORT10_INDEX_MASK;\n    }\n\n    bit_value = pPpbCfg->vlan_idx;\n    retVal  = rtl8367c_setAsicRegBits(reg_addr, bit_mask, bit_value);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    /* write priority */\n    reg_addr  = RTL8367C_VLAN_PPB_PRIORITY_ITEM_REG(port, index);\n    bit_mask  = RTL8367C_VLAN_PPB_PRIORITY_ITEM_MASK(port);\n    bit_value = pPpbCfg->priority;\n    retVal    = rtl8367c_setAsicRegBits(reg_addr, bit_mask, bit_value);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n/* Function Name:\n *      rtl8367c_getAsicVlanPortAndProtocolBased\n * Description:\n *      Get protocol and port based VLAN configuration\n * Input:\n *      port        - Physical port number (0~7)\n *      index       - Index of protocol and port based database index\n *      pPpbCfg     - Protocol and port based VLAN configuration\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK                   - Success\n *      RT_ERR_SMI                  - SMI access error\n *      RT_ERR_INPUT                - Invalid input parameter\n *      RT_ERR_PORT_ID              - Invalid port number\n *      RT_ERR_VLAN_PROTO_AND_PORT  - Invalid protocol base group database index\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicVlanPortAndProtocolBased(rtk_uint32 port, rtk_uint32 index, rtl8367c_protocolvlancfg *pPpbCfg)\n{\n    rtk_uint32  reg_addr, bit_mask, bit_value;\n    ret_t   retVal;\n\n    /* Error Checking */\n    if(port > RTL8367C_PORTIDMAX)\n        return RT_ERR_PORT_ID;\n\n    if(index > RTL8367C_PROTOVLAN_GIDX_MAX)\n        return RT_ERR_VLAN_PROTO_AND_PORT;\n\n    if(pPpbCfg == NULL)\n        return RT_ERR_INPUT;\n\n    /* Valid bit */\n    reg_addr  = RTL8367C_VLAN_PPB_VALID_REG(index);\n    bit_mask  = 0x0001 << port;\n    retVal    = rtl8367c_getAsicRegBits(reg_addr, bit_mask, &bit_value);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    pPpbCfg->valid = bit_value;\n\n    /* CVLAN index */\n    if(port < 8)\n    {\n        reg_addr = RTL8367C_VLAN_PPB_CTRL_REG(index, port);\n        bit_mask = RTL8367C_VLAN_PPB_CTRL_MASK(port);\n    }\n    else if(port == 8)\n    {\n        reg_addr = RTL8367C_REG_VLAN_PPB0_CTRL4;\n        bit_mask = RTL8367C_VLAN_PPB0_CTRL4_PORT8_INDEX_MASK;\n    }\n    else if(port == 9)\n    {\n        reg_addr = RTL8367C_REG_VLAN_PPB0_CTRL4;\n        bit_mask = RTL8367C_VLAN_PPB0_CTRL4_PORT9_INDEX_MASK;\n    }\n    else if(port == 10)\n    {\n        reg_addr = RTL8367C_REG_VLAN_PPB0_CTRL4;\n        bit_mask = RTL8367C_VLAN_PPB0_CTRL4_PORT10_INDEX_MASK;\n    }\n\n    retVal = rtl8367c_getAsicRegBits(reg_addr, bit_mask, &bit_value);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    pPpbCfg->vlan_idx = bit_value;\n\n\n    /* priority */\n    reg_addr = RTL8367C_VLAN_PPB_PRIORITY_ITEM_REG(port,index);\n    bit_mask = RTL8367C_VLAN_PPB_PRIORITY_ITEM_MASK(port);\n    retVal = rtl8367c_getAsicRegBits(reg_addr, bit_mask, &bit_value);\n    if(retVal != RT_ERR_OK)\n        return retVal;\n\n    pPpbCfg->priority = bit_value;\n    return RT_ERR_OK;\n}\n/* Function Name:\n *      rtl8367c_setAsicVlanFilter\n * Description:\n *      Set enable CVLAN filtering function\n * Input:\n *      enabled - 1: enabled, 0: disabled\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicVlanFilter(rtk_uint32 enabled)\n{\n    return rtl8367c_setAsicRegBit(RTL8367C_REG_VLAN_CTRL, RTL8367C_VLAN_CTRL_OFFSET, enabled);\n}\n/* Function Name:\n *      rtl8367c_getAsicVlanFilter\n * Description:\n *      Get enable CVLAN filtering function\n * Input:\n *      pEnabled - 1: enabled, 0: disabled\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicVlanFilter(rtk_uint32* pEnabled)\n{\n    return rtl8367c_getAsicRegBit(RTL8367C_REG_VLAN_CTRL, RTL8367C_VLAN_CTRL_OFFSET, pEnabled);\n}\n/* Function Name:\n *      rtl8367c_setAsicVlanUntagDscpPriorityEn\n * Description:\n *      Set enable Dscp to untag 1Q priority\n * Input:\n *      enabled - 1: enabled, 0: disabled\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicVlanUntagDscpPriorityEn(rtk_uint32 enabled)\n{\n    return rtl8367c_setAsicRegBit(RTL8367C_REG_UNTAG_DSCP_PRI_CFG, RTL8367C_UNTAG_DSCP_PRI_CFG_OFFSET, enabled);\n}\n/* Function Name:\n *      rtl8367c_getAsicVlanUntagDscpPriorityEn\n * Description:\n *      Get enable Dscp to untag 1Q priority\n * Input:\n *      enabled - 1: enabled, 0: disabled\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicVlanUntagDscpPriorityEn(rtk_uint32* enabled)\n{\n    return rtl8367c_getAsicRegBit(RTL8367C_REG_UNTAG_DSCP_PRI_CFG, RTL8367C_UNTAG_DSCP_PRI_CFG_OFFSET, enabled);\n}\n/* Function Name:\n *      rtl8367c_setAsicPortBasedFid\n * Description:\n *      Set port based FID\n * Input:\n *      port    - Physical port number (0~10)\n *      fid     - Port based fid\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n *      RT_ERR_L2_FID   - Invalid FID\n *      RT_ERR_PORT_ID  - Invalid port number\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicPortBasedFid(rtk_uint32 port, rtk_uint32 fid)\n{\n    rtk_uint32  reg_addr;\n\n    if(port > RTL8367C_PORTIDMAX)\n        return RT_ERR_PORT_ID;\n\n    if(fid > RTL8367C_FIDMAX)\n        return RT_ERR_L2_FID;\n\n    if(port < 8)\n        return rtl8367c_setAsicReg(RTL8367C_PORT_PBFID_REG(port),fid);\n    else {\n        reg_addr = RTL8367C_REG_PORT8_PBFID + port-8;\n        return rtl8367c_setAsicReg(reg_addr, fid);\n    }\n\n}\n/* Function Name:\n *      rtl8367c_getAsicPortBasedFid\n * Description:\n *      Get port based FID\n * Input:\n *      port    - Physical port number (0~7)\n *      pFid    - Port based fid\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n *      RT_ERR_PORT_ID  - Invalid port number\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicPortBasedFid(rtk_uint32 port, rtk_uint32* pFid)\n{\n    rtk_uint32  reg_addr;\n\n    if(port > RTL8367C_PORTIDMAX)\n        return RT_ERR_PORT_ID;\n\n    if(port < 8)\n        return rtl8367c_getAsicReg(RTL8367C_PORT_PBFID_REG(port), pFid);\n    else{\n        reg_addr = RTL8367C_REG_PORT8_PBFID + port-8;\n        return rtl8367c_getAsicReg(reg_addr, pFid);\n    }\n}\n/* Function Name:\n *      rtl8367c_setAsicPortBasedFidEn\n * Description:\n *      Set port based FID selection enable\n * Input:\n *      port    - Physical port number (0~10)\n *      enabled - 1: enabled, 0: disabled\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n *      RT_ERR_PORT_ID  - Invalid port number\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicPortBasedFidEn(rtk_uint32 port, rtk_uint32 enabled)\n{\n    if(port > RTL8367C_PORTIDMAX)\n        return RT_ERR_PORT_ID;\n\n    return rtl8367c_setAsicRegBit(RTL8367C_REG_PORT_PBFIDEN,port, enabled);\n}\n/* Function Name:\n *      rtl8367c_getAsicPortBasedFidEn\n * Description:\n *      Get port based FID selection enable\n * Input:\n *      port    - Physical port number (0~10)\n *      pEnabled - 1: enabled, 0: disabled\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n *      RT_ERR_PORT_ID  - Invalid port number\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicPortBasedFidEn(rtk_uint32 port, rtk_uint32* pEnabled)\n{\n    if(port > RTL8367C_PORTIDMAX)\n        return RT_ERR_PORT_ID;\n\n    return rtl8367c_getAsicRegBit(RTL8367C_REG_PORT_PBFIDEN,port, pEnabled);\n}\n/* Function Name:\n *      rtl8367c_setAsicSpanningTreeStatus\n * Description:\n *      Set spanning tree state per each port\n * Input:\n *      port    - Physical port number (0~10)\n *      msti    - Multiple spanning tree instance\n *      state   - Spanning tree state for msti\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_MSTI         - Invalid msti parameter\n *      RT_ERR_PORT_ID      - Invalid port number\n *      RT_ERR_MSTP_STATE   - Invalid port number\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicSpanningTreeStatus(rtk_uint32 port, rtk_uint32 msti, rtk_uint32 state)\n{\n    rtk_uint32  reg_addr,bits_msk;\n\n    if(port > RTL8367C_PORTIDMAX)\n        return RT_ERR_PORT_ID;\n\n    if(msti > RTL8367C_MSTIMAX)\n        return RT_ERR_MSTI;\n\n    if(state > STPST_FORWARDING)\n        return RT_ERR_MSTP_STATE;\n\n    if(port < 8)\n        return rtl8367c_setAsicRegBits(RTL8367C_VLAN_MSTI_REG(msti,port), RTL8367C_VLAN_MSTI_MASK(port),state);\n    else{\n        reg_addr = RTL8367C_VLAN_MSTI_REG(msti,port);\n        switch(port){\n            case 8: bits_msk = RTL8367C_VLAN_MSTI0_CTRL1_PORT8_STATE_MASK;break;\n            case 9: bits_msk = RTL8367C_VLAN_MSTI0_CTRL1_PORT9_STATE_MASK;break;\n            case 10: bits_msk = RTL8367C_VLAN_MSTI0_CTRL1_PORT10_STATE_MASK;break;\n        }\n        return rtl8367c_setAsicRegBits(reg_addr, bits_msk,state);\n    }\n}\n/* Function Name:\n *      rtl8367c_getAsicSpanningTreeStatus\n * Description:\n *      Set spanning tree state per each port\n * Input:\n *      port    - Physical port number (0~10)\n *      msti    - Multiple spanning tree instance\n *      pState  - Spanning tree state for msti\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_MSTI         - Invalid msti parameter\n *      RT_ERR_PORT_ID      - Invalid port number\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicSpanningTreeStatus(rtk_uint32 port, rtk_uint32 msti, rtk_uint32* pState)\n{\n    rtk_uint32  reg_addr,bits_msk;\n\n    if(port > RTL8367C_PORTIDMAX)\n        return RT_ERR_PORT_ID;\n\n    if(msti > RTL8367C_MSTIMAX)\n        return RT_ERR_MSTI;\n\n    if(port < 8)\n        return rtl8367c_getAsicRegBits(RTL8367C_VLAN_MSTI_REG(msti,port), RTL8367C_VLAN_MSTI_MASK(port), pState);\n    else{\n        reg_addr = RTL8367C_VLAN_MSTI_REG(msti,port);\n        switch(port){\n            case 8: bits_msk = RTL8367C_VLAN_MSTI0_CTRL1_PORT8_STATE_MASK;break;\n            case 9: bits_msk = RTL8367C_VLAN_MSTI0_CTRL1_PORT9_STATE_MASK;break;\n            case 10: bits_msk = RTL8367C_VLAN_MSTI0_CTRL1_PORT10_STATE_MASK;break;\n        }\n        return rtl8367c_getAsicRegBits(reg_addr, bits_msk, pState);\n    }\n\n}\n\n/* Function Name:\n *      rtl8367c_setAsicVlanTransparent\n * Description:\n *      Set VLAN transparent\n * Input:\n *      port        - Physical port number (0~10)\n *      portmask    - portmask(0~0xFF)\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_MASK    - Invalid portmask\n *      RT_ERR_PORT_ID      - Invalid port number\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicVlanTransparent(rtk_uint32 port, rtk_uint32 portmask)\n{\n    if(port > RTL8367C_PORTIDMAX)\n        return RT_ERR_PORT_ID;\n\n    if(portmask > RTL8367C_PORTMASK)\n        return RT_ERR_PORT_MASK;\n\n    return rtl8367c_setAsicRegBits(RTL8367C_REG_VLAN_EGRESS_TRANS_CTRL0 + port, RTL8367C_VLAN_EGRESS_TRANS_CTRL0_MASK, portmask);\n}\n\n/* Function Name:\n *      rtl8367c_getAsicVlanTransparent\n * Description:\n *      Get VLAN transparent\n * Input:\n *      port        - Physical port number (0~10)\n * Output:\n *      pPortmask   - Ingress port mask\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_MASK    - Invalid portmask\n *      RT_ERR_PORT_ID      - Invalid port number\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicVlanTransparent(rtk_uint32 port, rtk_uint32 *pPortmask)\n{\n    if(port > RTL8367C_PORTIDMAX)\n        return RT_ERR_PORT_ID;\n\n    return rtl8367c_getAsicRegBits(RTL8367C_REG_VLAN_EGRESS_TRANS_CTRL0 + port, RTL8367C_VLAN_EGRESS_TRANS_CTRL0_MASK, pPortmask);\n}\n\n/* Function Name:\n *      rtl8367c_setAsicVlanEgressKeep\n * Description:\n *      Set per egress port VLAN keep mode\n * Input:\n *      port        - Physical port number (0~10)\n *      portmask    - portmask(0~0xFF)\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_MASK    - Invalid portmask\n *      RT_ERR_PORT_ID      - Invalid port number\n * Note:\n *      None\n */\nret_t rtl8367c_setAsicVlanEgressKeep(rtk_uint32 port, rtk_uint32 portmask)\n{\n    rtk_uint32 regAddr, bit_mask;\n    ret_t  retVal;\n\n    if(port > RTL8367C_PORTIDMAX)\n        return RT_ERR_PORT_ID;\n\n    if(portmask > RTL8367C_PORTMASK)\n        return RT_ERR_PORT_MASK;\n\n    if(port < 8){\n        retVal = rtl8367c_setAsicRegBits(RTL8367C_REG_VLAN_EGRESS_KEEP_CTRL0 + (port>>1),RTL8367C_PORT0_VLAN_KEEP_MASK_MASK<<((port&1)*8),portmask & 0xff);\n        if(retVal != RT_ERR_OK)\n            return retVal;\n        regAddr = RTL8367C_REG_VLAN_EGRESS_KEEP_CTRL0_EXT + (port>>1);\n        bit_mask = RTL8367C_PORT0_VLAN_KEEP_MASK_EXT_MASK;\n        bit_mask <<= (port&1)*3;\n        retVal = rtl8367c_setAsicRegBits(regAddr, bit_mask, (portmask>>8)&0x7);\n        if(retVal != RT_ERR_OK)\n            return retVal;\n    }\n    else{\n        switch(port){\n            case 8:\n                regAddr = RTL8367C_REG_VLAN_EGRESS_KEEP_CTRL4;\n                bit_mask = RTL8367C_PORT8_VLAN_KEEP_MASK_MASK;\n                retVal = rtl8367c_setAsicRegBits(regAddr, bit_mask, portmask & 0xff);\n                if(retVal != RT_ERR_OK)\n                    return retVal;\n                regAddr = RTL8367C_REG_VLAN_EGRESS_KEEP_CTRL4_EXT;\n                bit_mask = RTL8367C_PORT8_VLAN_KEEP_MASK_EXT_MASK;\n                retVal = rtl8367c_setAsicRegBits(regAddr, bit_mask, (portmask>>8)&0x7);\n                if(retVal != RT_ERR_OK)\n                    return retVal;\n                break;\n\n            case 9:\n                regAddr = RTL8367C_REG_VLAN_EGRESS_KEEP_CTRL4;\n                bit_mask = RTL8367C_PORT9_VLAN_KEEP_MASK_MASK;\n                retVal = rtl8367c_setAsicRegBits(regAddr, bit_mask, portmask & 0xff);\n                if(retVal != RT_ERR_OK)\n                    return retVal;\n                regAddr = RTL8367C_REG_VLAN_EGRESS_KEEP_CTRL4_EXT;\n                bit_mask = RTL8367C_PORT9_VLAN_KEEP_MASK_EXT_MASK;\n                retVal = rtl8367c_setAsicRegBits(regAddr, bit_mask, (portmask>>8)&0x7);\n                if(retVal != RT_ERR_OK)\n                    return retVal;\n                break;\n\n            case 10:\n                regAddr = RTL8367C_REG_VLAN_EGRESS_KEEP_CTRL5;\n                bit_mask = RTL8367C_VLAN_EGRESS_KEEP_CTRL5_MASK;\n                retVal = rtl8367c_setAsicRegBits(regAddr, bit_mask, portmask & 0xff);\n                if(retVal != RT_ERR_OK)\n                    return retVal;\n                regAddr = RTL8367C_REG_VLAN_EGRESS_KEEP_CTRL5_EXT;\n                bit_mask = RTL8367C_VLAN_EGRESS_KEEP_CTRL5_EXT_MASK;\n                retVal = rtl8367c_setAsicRegBits(regAddr, bit_mask, (portmask>>8)&0x7);\n                if(retVal != RT_ERR_OK)\n                    return retVal;\n                break;\n        }\n    }\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtl8367c_getAsicVlanEgressKeep\n * Description:\n *      Get per egress port VLAN keep mode\n * Input:\n *      port        - Physical port number (0~7)\n *      pPortmask   - portmask(0~0xFF)\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n *      RT_ERR_PORT_ID  - Invalid port number\n * Note:\n *      None\n */\nret_t rtl8367c_getAsicVlanEgressKeep(rtk_uint32 port, rtk_uint32* pPortmask)\n{\n    rtk_uint32 regAddr, bit_mask, regval_l, regval_h;\n    ret_t  retVal;\n\n    if(port > RTL8367C_PORTIDMAX)\n        return RT_ERR_PORT_ID;\n\n    if(port < 8){\n        retVal = rtl8367c_getAsicRegBits(RTL8367C_REG_VLAN_EGRESS_KEEP_CTRL0 + (port>>1),RTL8367C_PORT0_VLAN_KEEP_MASK_MASK<<((port&1)*8),&regval_l);\n        if(retVal != RT_ERR_OK)\n            return retVal;\n        regAddr = RTL8367C_REG_VLAN_EGRESS_KEEP_CTRL0_EXT + (port>>1);\n        bit_mask = RTL8367C_PORT0_VLAN_KEEP_MASK_EXT_MASK;\n        bit_mask <<= (port&1)*3;\n        retVal = rtl8367c_getAsicRegBits(regAddr, bit_mask, &regval_h);\n        if(retVal != RT_ERR_OK)\n            return retVal;\n        *pPortmask = (regval_h << 8) | regval_l;\n    }\n    else{\n        switch(port){\n            case 8:\n                regAddr = RTL8367C_REG_VLAN_EGRESS_KEEP_CTRL4;\n                bit_mask = RTL8367C_PORT8_VLAN_KEEP_MASK_MASK;\n                retVal = rtl8367c_getAsicRegBits(regAddr, bit_mask, &regval_l);\n                if(retVal != RT_ERR_OK)\n                    return retVal;\n                regAddr = RTL8367C_REG_VLAN_EGRESS_KEEP_CTRL4_EXT;\n                bit_mask = RTL8367C_PORT8_VLAN_KEEP_MASK_EXT_MASK;\n                retVal = rtl8367c_getAsicRegBits(regAddr, bit_mask, &regval_h);\n                if(retVal != RT_ERR_OK)\n                    return retVal;\n\n                *pPortmask = (regval_h << 8) | regval_l;\n                break;\n\n            case 9:\n                regAddr = RTL8367C_REG_VLAN_EGRESS_KEEP_CTRL4;\n                bit_mask = RTL8367C_PORT9_VLAN_KEEP_MASK_MASK;\n                retVal = rtl8367c_getAsicRegBits(regAddr, bit_mask, &regval_l);\n                if(retVal != RT_ERR_OK)\n                    return retVal;\n                regAddr = RTL8367C_REG_VLAN_EGRESS_KEEP_CTRL4_EXT;\n                bit_mask = RTL8367C_PORT9_VLAN_KEEP_MASK_EXT_MASK;\n                retVal = rtl8367c_getAsicRegBits(regAddr, bit_mask, &regval_h);\n                if(retVal != RT_ERR_OK)\n                    return retVal;\n\n                *pPortmask = (regval_h << 8) | regval_l;\n                break;\n\n            case 10:\n                regAddr = RTL8367C_REG_VLAN_EGRESS_KEEP_CTRL5;\n                bit_mask = RTL8367C_VLAN_EGRESS_KEEP_CTRL5_MASK;\n                retVal = rtl8367c_getAsicRegBits(regAddr, bit_mask, &regval_l);\n                if(retVal != RT_ERR_OK)\n                    return retVal;\n                regAddr = RTL8367C_REG_VLAN_EGRESS_KEEP_CTRL5_EXT;\n                bit_mask = RTL8367C_VLAN_EGRESS_KEEP_CTRL5_EXT_MASK;\n                retVal = rtl8367c_getAsicRegBits(regAddr, bit_mask, &regval_h);\n                if(retVal != RT_ERR_OK)\n                    return retVal;\n\n                *pPortmask = (regval_h << 8) | regval_l;\n                break;\n        }\n    }\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtl8367c_setReservedVidAction\n * Description:\n *      Set reserved VID action\n * Input:\n *      vid0Action      - VID 0 action\n *      vid4095Action   - VID 4095 action\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n *      RT_ERR_INPUT    - Error input\n * Note:\n *      None\n */\nret_t rtl8367c_setReservedVidAction(rtk_uint32 vid0Action, rtk_uint32 vid4095Action)\n{\n    ret_t   retVal;\n\n    if(vid0Action >= RES_VID_ACT_END)\n        return RT_ERR_INPUT;\n\n    if(vid4095Action >= RES_VID_ACT_END)\n        return RT_ERR_INPUT;\n\n    if((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_VLAN_EXT_CTRL, RTL8367C_VLAN_VID0_TYPE_OFFSET, vid0Action)) != RT_ERR_OK)\n        return retVal;\n\n    if((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_VLAN_EXT_CTRL, RTL8367C_VLAN_VID4095_TYPE_OFFSET, vid4095Action)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtl8367c_getReservedVidAction\n * Description:\n *      Get reserved VID action\n * Input:\n *      pVid0Action     - VID 0 action\n *      pVid4095Action  - VID 4095 action\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - Success\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_NULL_POINTER - Null pointer\n * Note:\n *      None\n */\nret_t rtl8367c_getReservedVidAction(rtk_uint32 *pVid0Action, rtk_uint32 *pVid4095Action)\n{\n    ret_t   retVal;\n\n    if(pVid0Action == NULL)\n        return RT_ERR_NULL_POINTER;\n\n    if(pVid4095Action == NULL)\n        return RT_ERR_NULL_POINTER;\n\n    if((retVal = rtl8367c_getAsicRegBit(RTL8367C_REG_VLAN_EXT_CTRL, RTL8367C_VLAN_VID0_TYPE_OFFSET, pVid0Action)) != RT_ERR_OK)\n        return retVal;\n\n    if((retVal = rtl8367c_getAsicRegBit(RTL8367C_REG_VLAN_EXT_CTRL, RTL8367C_VLAN_VID4095_TYPE_OFFSET, pVid4095Action)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n\n}\n\n/* Function Name:\n *      rtl8367c_setRealKeepRemarkEn\n * Description:\n *      Set Real Keep Remark\n * Input:\n *      enabled         - 0: 1P remarking is forbidden at real keep packet, 1: 1P remarking is enabled at real keep packet\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n *      RT_ERR_INPUT    - Error input\n * Note:\n *      None\n */\nret_t rtl8367c_setRealKeepRemarkEn(rtk_uint32 enabled)\n{\n    ret_t   retVal;\n\n    if((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_VLAN_EXT_CTRL, RTL8367C_VLAN_1P_REMARK_BYPASS_REALKEEP_OFFSET, enabled)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtl8367c_getRealKeepRemarkEn\n * Description:\n *      Get Real Keep Remark\n * Input:\n *      None\n * Output:\n *      pEnabled        - 0: 1P remarking is forbidden at real keep packet, 1: 1P remarking is enabled at real keep packet\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n *      RT_ERR_INPUT    - Error input\n * Note:\n *      None\n */\nret_t rtl8367c_getRealKeepRemarkEn(rtk_uint32 *pEnabled)\n{\n    ret_t   retVal;\n\n    if((retVal = rtl8367c_getAsicRegBit(RTL8367C_REG_VLAN_EXT_CTRL, RTL8367C_VLAN_1P_REMARK_BYPASS_REALKEEP_OFFSET, pEnabled)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtl8367c_resetVlan\n * Description:\n *      Reset VLAN table\n * Input:\n *      None.\n * Output:\n *      None.\n * Return:\n *      RT_ERR_OK       - Success\n *      RT_ERR_SMI      - SMI access error\n * Note:\n *      None\n */\nret_t rtl8367c_resetVlan(void)\n{\n    ret_t   retVal;\n\n    if((retVal = rtl8367c_setAsicRegBit(RTL8367C_REG_VLAN_EXT_CTRL2, RTL8367C_VLAN_EXT_CTRL2_OFFSET, 1)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/smi.c",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * Purpose : RTL8367C switch low-level function for access register\n * Feature : SMI related functions\n *\n */\n\n\n#include <rtk_types.h>\n#include <smi.h>\n#include \"rtk_error.h\"\n\n\n#if defined(MDC_MDIO_OPERATION)\n/*******************************************************************************/\n/*  MDC/MDIO porting                                                           */\n/*******************************************************************************/\n/* define the PHY ID currently used */\n/* carlos */\n#if 0\n#define MDC_MDIO_PHY_ID     0  /* PHY ID 0 or 29 */\n#else\n#define MDC_MDIO_PHY_ID     29  /* PHY ID 0 or 29 */\n#endif\n\n/* MDC/MDIO, redefine/implement the following Macro */ /*carlos*/\n#if 0\n#define MDC_MDIO_WRITE(preamableLength, phyID, regID, data)\n#define MDC_MDIO_READ(preamableLength, phyID, regID, pData)\n#else\n#define u32      unsigned int\nextern u32 mii_mgr_read(u32 phy_addr, u32 phy_register, u32 *read_data);\nextern u32 mii_mgr_write(u32 phy_addr, u32 phy_register, u32 write_data);\n\n#define MDC_MDIO_WRITE(preamableLength, phyID, regID, data) mii_mgr_write(phyID, regID, data)\n#define MDC_MDIO_READ(preamableLength, phyID, regID, pData) mii_mgr_read(phyID, regID, pData)\n#endif\n\n\n\n\n\n#elif defined(SPI_OPERATION)\n/*******************************************************************************/\n/*  SPI porting                                                                */\n/*******************************************************************************/\n/* SPI, redefine/implement the following Macro */\n#define SPI_WRITE(data, length)\n#define SPI_READ(pData, length)\n\n\n\n\n\n#else\n/*******************************************************************************/\n/*  I2C porting                                                                */\n/*******************************************************************************/\n/* Define the GPIO ID for SCK & SDA */\nrtk_uint32  smi_SCK = 1;    /* GPIO used for SMI Clock Generation */\nrtk_uint32  smi_SDA = 2;    /* GPIO used for SMI Data signal */\n\n/* I2C, redefine/implement the following Macro */\n#define GPIO_DIRECTION_SET(gpioID, direction)\n#define GPIO_DATA_SET(gpioID, data)\n#define GPIO_DATA_GET(gpioID, pData)\n\n\n\n\n\n#endif\n\nstatic void rtlglue_drvMutexLock(void)\n{\n    /* It is empty currently. Implement this function if Lock/Unlock function is needed */\n    return;\n}\n\nstatic void rtlglue_drvMutexUnlock(void)\n{\n    /* It is empty currently. Implement this function if Lock/Unlock function is needed */\n    return;\n}\n\n\n\n#if defined(MDC_MDIO_OPERATION) || defined(SPI_OPERATION)\n    /* No local function in MDC/MDIO & SPI mode */\n#else\nstatic void _smi_start(void)\n{\n\n    /* change GPIO pin to Output only */\n    GPIO_DIRECTION_SET(smi_SCK, GPIO_DIR_OUT);\n    GPIO_DIRECTION_SET(smi_SDA, GPIO_DIR_OUT);\n\n    /* Initial state: SCK: 0, SDA: 1 */\n    GPIO_DATA_SET(smi_SCK, 0);\n    GPIO_DATA_SET(smi_SDA, 1);\n    CLK_DURATION(DELAY);\n\n    /* CLK 1: 0 -> 1, 1 -> 0 */\n    GPIO_DATA_SET(smi_SCK, 1);\n    CLK_DURATION(DELAY);\n    GPIO_DATA_SET(smi_SCK, 0);\n    CLK_DURATION(DELAY);\n\n    /* CLK 2: */\n    GPIO_DATA_SET(smi_SCK, 1);\n    CLK_DURATION(DELAY);\n    GPIO_DATA_SET(smi_SDA, 0);\n    CLK_DURATION(DELAY);\n    GPIO_DATA_SET(smi_SCK, 0);\n    CLK_DURATION(DELAY);\n    GPIO_DATA_SET(smi_SDA, 1);\n\n}\n\n\n\nstatic void _smi_writeBit(rtk_uint16 signal, rtk_uint32 bitLen)\n{\n    for( ; bitLen > 0; bitLen--)\n    {\n        CLK_DURATION(DELAY);\n\n        /* prepare data */\n        if ( signal & (1<<(bitLen-1)) )\n        {\n            GPIO_DATA_SET(smi_SDA, 1);\n        }\n        else\n        {\n            GPIO_DATA_SET(smi_SDA, 0);\n        }\n        CLK_DURATION(DELAY);\n\n        /* clocking */\n        GPIO_DATA_SET(smi_SCK, 1);\n        CLK_DURATION(DELAY);\n        GPIO_DATA_SET(smi_SCK, 0);\n    }\n}\n\n\n\nstatic void _smi_readBit(rtk_uint32 bitLen, rtk_uint32 *rData)\n{\n    rtk_uint32 u = 0;\n\n    /* change GPIO pin to Input only */\n    GPIO_DIRECTION_SET(smi_SDA, GPIO_DIR_IN);\n\n    for (*rData = 0; bitLen > 0; bitLen--)\n    {\n        CLK_DURATION(DELAY);\n\n        /* clocking */\n        GPIO_DATA_SET(smi_SCK, 1);\n        CLK_DURATION(DELAY);\n        GPIO_DATA_GET(smi_SDA, &u);\n        GPIO_DATA_SET(smi_SCK, 0);\n\n        *rData |= (u << (bitLen - 1));\n    }\n\n    /* change GPIO pin to Output only */\n    GPIO_DIRECTION_SET(smi_SDA, GPIO_DIR_OUT);\n}\n\n\n\nstatic void _smi_stop(void)\n{\n\n    CLK_DURATION(DELAY);\n    GPIO_DATA_SET(smi_SDA, 0);\n    GPIO_DATA_SET(smi_SCK, 1);\n    CLK_DURATION(DELAY);\n    GPIO_DATA_SET(smi_SDA, 1);\n    CLK_DURATION(DELAY);\n    GPIO_DATA_SET(smi_SCK, 1);\n    CLK_DURATION(DELAY);\n    GPIO_DATA_SET(smi_SCK, 0);\n    CLK_DURATION(DELAY);\n    GPIO_DATA_SET(smi_SCK, 1);\n\n    /* add a click */\n    CLK_DURATION(DELAY);\n    GPIO_DATA_SET(smi_SCK, 0);\n    CLK_DURATION(DELAY);\n    GPIO_DATA_SET(smi_SCK, 1);\n\n\n    /* change GPIO pin to Input only */\n    GPIO_DIRECTION_SET(smi_SDA, GPIO_DIR_IN);\n    GPIO_DIRECTION_SET(smi_SCK, GPIO_DIR_IN);\n}\n\n#endif /* End of #if defined(MDC_MDIO_OPERATION) || defined(SPI_OPERATION) */\n\nrtk_int32 smi_read(rtk_uint32 mAddrs, rtk_uint32 *rData)\n{\n#if (!defined(MDC_MDIO_OPERATION) && !defined(SPI_OPERATION))\n    rtk_uint32 rawData=0, ACK;\n    rtk_uint8  con;\n    rtk_uint32 ret = RT_ERR_OK;\n#endif\n\n    if(mAddrs > 0xFFFF)\n        return RT_ERR_INPUT;\n\n    if(rData == NULL)\n        return RT_ERR_NULL_POINTER;\n\n#if defined(MDC_MDIO_OPERATION)\n\n    /* Lock */\n    rtlglue_drvMutexLock();\n\n    /* Write address control code to register 31 */\n    MDC_MDIO_WRITE(MDC_MDIO_PREAMBLE_LEN, MDC_MDIO_PHY_ID, MDC_MDIO_CTRL0_REG, MDC_MDIO_ADDR_OP);\n\n    /* Write address to register 23 */\n    MDC_MDIO_WRITE(MDC_MDIO_PREAMBLE_LEN, MDC_MDIO_PHY_ID, MDC_MDIO_ADDRESS_REG, mAddrs);\n\n    /* Write read control code to register 21 */\n    MDC_MDIO_WRITE(MDC_MDIO_PREAMBLE_LEN, MDC_MDIO_PHY_ID, MDC_MDIO_CTRL1_REG, MDC_MDIO_READ_OP);\n\n    /* Read data from register 25 */\n    MDC_MDIO_READ(MDC_MDIO_PREAMBLE_LEN, MDC_MDIO_PHY_ID, MDC_MDIO_DATA_READ_REG, rData);\n\n    /* Unlock */\n    rtlglue_drvMutexUnlock();\n\n    return RT_ERR_OK;\n\n#elif defined(SPI_OPERATION)\n\n    /* Lock */\n    rtlglue_drvMutexLock();\n\n    /* Write 8 bits READ OP_CODE */\n    SPI_WRITE(SPI_READ_OP, SPI_READ_OP_LEN);\n\n    /* Write 16 bits register address */\n    SPI_WRITE(mAddrs, SPI_REG_LEN);\n\n    /* Read 16 bits data */\n    SPI_READ(rData, SPI_DATA_LEN);\n\n    /* Unlock */\n    rtlglue_drvMutexUnlock();\n\n    return RT_ERR_OK;\n\n#else\n\n    /*Disable CPU interrupt to ensure that the SMI operation is atomic.\n      The API is based on RTL865X, rewrite the API if porting to other platform.*/\n    rtlglue_drvMutexLock();\n\n    _smi_start();                                /* Start SMI */\n\n    _smi_writeBit(0x0b, 4);                     /* CTRL code: 4'b1011 for RTL8370 */\n\n    _smi_writeBit(0x4, 3);                        /* CTRL code: 3'b100 */\n\n    _smi_writeBit(0x1, 1);                        /* 1: issue READ command */\n\n    con = 0;\n    do {\n        con++;\n        _smi_readBit(1, &ACK);                    /* ACK for issuing READ command*/\n    } while ((ACK != 0) && (con < ack_timer));\n\n    if (ACK != 0) ret = RT_ERR_FAILED;\n\n    _smi_writeBit((mAddrs&0xff), 8);             /* Set reg_addr[7:0] */\n\n    con = 0;\n    do {\n        con++;\n        _smi_readBit(1, &ACK);                    /* ACK for setting reg_addr[7:0] */\n    } while ((ACK != 0) && (con < ack_timer));\n\n    if (ACK != 0) ret = RT_ERR_FAILED;\n\n    _smi_writeBit((mAddrs>>8), 8);                 /* Set reg_addr[15:8] */\n\n    con = 0;\n    do {\n        con++;\n        _smi_readBit(1, &ACK);                    /* ACK by RTL8369 */\n    } while ((ACK != 0) && (con < ack_timer));\n    if (ACK != 0) ret = RT_ERR_FAILED;\n\n    _smi_readBit(8, &rawData);                    /* Read DATA [7:0] */\n    *rData = rawData&0xff;\n\n    _smi_writeBit(0x00, 1);                        /* ACK by CPU */\n\n    _smi_readBit(8, &rawData);                    /* Read DATA [15: 8] */\n\n    _smi_writeBit(0x01, 1);                        /* ACK by CPU */\n    *rData |= (rawData<<8);\n\n    _smi_stop();\n\n    rtlglue_drvMutexUnlock();/*enable CPU interrupt*/\n\n    return ret;\n#endif /* end of #if defined(MDC_MDIO_OPERATION) */\n}\n\n\n\nrtk_int32 smi_write(rtk_uint32 mAddrs, rtk_uint32 rData)\n{\n#if (!defined(MDC_MDIO_OPERATION) && !defined(SPI_OPERATION))\n    rtk_int8 con;\n    rtk_uint32 ACK;\n    rtk_uint32 ret = RT_ERR_OK;\n#endif\n\n    if(mAddrs > 0xFFFF)\n        return RT_ERR_INPUT;\n\n    if(rData > 0xFFFF)\n        return RT_ERR_INPUT;\n\n#if defined(MDC_MDIO_OPERATION)\n\n    /* Lock */\n    rtlglue_drvMutexLock();\n\n    /* Write address control code to register 31 */\n    MDC_MDIO_WRITE(MDC_MDIO_PREAMBLE_LEN, MDC_MDIO_PHY_ID, MDC_MDIO_CTRL0_REG, MDC_MDIO_ADDR_OP);\n\n    /* Write address to register 23 */\n    MDC_MDIO_WRITE(MDC_MDIO_PREAMBLE_LEN, MDC_MDIO_PHY_ID, MDC_MDIO_ADDRESS_REG, mAddrs);\n\n    /* Write data to register 24 */\n    MDC_MDIO_WRITE(MDC_MDIO_PREAMBLE_LEN, MDC_MDIO_PHY_ID, MDC_MDIO_DATA_WRITE_REG, rData);\n\n    /* Write data control code to register 21 */\n    MDC_MDIO_WRITE(MDC_MDIO_PREAMBLE_LEN, MDC_MDIO_PHY_ID, MDC_MDIO_CTRL1_REG, MDC_MDIO_WRITE_OP);\n\n    /* Unlock */\n    rtlglue_drvMutexUnlock();\n\n    return RT_ERR_OK;\n\n#elif defined(SPI_OPERATION)\n\n    /* Lock */\n    rtlglue_drvMutexLock();\n\n    /* Write 8 bits WRITE OP_CODE */\n    SPI_WRITE(SPI_WRITE_OP, SPI_WRITE_OP_LEN);\n\n    /* Write 16 bits register address */\n    SPI_WRITE(mAddrs, SPI_REG_LEN);\n\n    /* Write 16 bits data */\n    SPI_WRITE(rData, SPI_DATA_LEN);\n\n    /* Unlock */\n    rtlglue_drvMutexUnlock();\n\n    return RT_ERR_OK;\n#else\n\n    /*Disable CPU interrupt to ensure that the SMI operation is atomic.\n      The API is based on RTL865X, rewrite the API if porting to other platform.*/\n    rtlglue_drvMutexLock();\n\n    _smi_start();                                /* Start SMI */\n\n    _smi_writeBit(0x0b, 4);                     /* CTRL code: 4'b1011 for RTL8370*/\n\n    _smi_writeBit(0x4, 3);                        /* CTRL code: 3'b100 */\n\n    _smi_writeBit(0x0, 1);                        /* 0: issue WRITE command */\n\n    con = 0;\n    do {\n        con++;\n        _smi_readBit(1, &ACK);                    /* ACK for issuing WRITE command*/\n    } while ((ACK != 0) && (con < ack_timer));\n    if (ACK != 0) ret = RT_ERR_FAILED;\n\n    _smi_writeBit((mAddrs&0xff), 8);             /* Set reg_addr[7:0] */\n\n    con = 0;\n    do {\n        con++;\n        _smi_readBit(1, &ACK);                    /* ACK for setting reg_addr[7:0] */\n    } while ((ACK != 0) && (con < ack_timer));\n    if (ACK != 0) ret = RT_ERR_FAILED;\n\n    _smi_writeBit((mAddrs>>8), 8);                 /* Set reg_addr[15:8] */\n\n    con = 0;\n    do {\n        con++;\n        _smi_readBit(1, &ACK);                    /* ACK for setting reg_addr[15:8] */\n    } while ((ACK != 0) && (con < ack_timer));\n    if (ACK != 0) ret = RT_ERR_FAILED;\n\n    _smi_writeBit(rData&0xff, 8);                /* Write Data [7:0] out */\n\n    con = 0;\n    do {\n        con++;\n        _smi_readBit(1, &ACK);                    /* ACK for writting data [7:0] */\n    } while ((ACK != 0) && (con < ack_timer));\n    if (ACK != 0) ret = RT_ERR_FAILED;\n\n    _smi_writeBit(rData>>8, 8);                    /* Write Data [15:8] out */\n\n    con = 0;\n    do {\n        con++;\n        _smi_readBit(1, &ACK);                        /* ACK for writting data [15:8] */\n    } while ((ACK != 0) && (con < ack_timer));\n    if (ACK != 0) ret = RT_ERR_FAILED;\n\n    _smi_stop();\n\n    rtlglue_drvMutexUnlock();/*enable CPU interrupt*/\n\n    return ret;\n#endif /* end of #if defined(MDC_MDIO_OPERATION) */\n}\n\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/stat.c",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * $Revision: 76306 $\n * $Date: 2017-03-08 15:13:58 +0800 (週三, 08 三月 2017) $\n *\n * Purpose : RTK switch high-level API for RTL8367/RTL8367C\n * Feature : Here is a list of all functions and variables in MIB module.\n *\n */\n\n#include <rtk_switch.h>\n#include <rtk_error.h>\n#include <stat.h>\n#include <string.h>\n\n#include <rtl8367c_asicdrv.h>\n#include <rtl8367c_asicdrv_mib.h>\n\n/* Function Name:\n *      rtk_stat_global_reset\n * Description:\n *      Reset global MIB counter.\n * Input:\n *      None\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n * Note:\n *      Reset MIB counter of ports. API will use global reset while port mask is all-ports.\n */\nrtk_api_ret_t rtk_stat_global_reset(void)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if ((retVal = rtl8367c_setAsicMIBsCounterReset(TRUE,FALSE, 0)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_stat_port_reset\n * Description:\n *      Reset per port MIB counter by port.\n * Input:\n *      port - port id.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n * Note:\n *\n */\nrtk_api_ret_t rtk_stat_port_reset(rtk_port_t port)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check port valid */\n    RTK_CHK_PORT_VALID(port);\n\n    if ((retVal = rtl8367c_setAsicMIBsCounterReset(FALSE,FALSE,1 << rtk_switch_port_L2P_get(port))) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_stat_queueManage_reset\n * Description:\n *      Reset queue manage MIB counter.\n * Input:\n *      None\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n * Note:\n *\n */\nrtk_api_ret_t rtk_stat_queueManage_reset(void)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if ((retVal = rtl8367c_setAsicMIBsCounterReset(FALSE,TRUE,0)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n\n/* Function Name:\n *      rtk_stat_global_get\n * Description:\n *      Get global MIB counter\n * Input:\n *      cntr_idx - global counter index.\n * Output:\n *      pCntr - global counter value.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n * Note:\n *      Get global MIB counter by index definition.\n */\nrtk_api_ret_t rtk_stat_global_get(rtk_stat_global_type_t cntr_idx, rtk_stat_counter_t *pCntr)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(NULL == pCntr)\n        return RT_ERR_NULL_POINTER;\n\n    if (cntr_idx!=DOT1D_TP_LEARNED_ENTRY_DISCARDS_INDEX)\n        return RT_ERR_STAT_INVALID_GLOBAL_CNTR;\n\n    if ((retVal = rtl8367c_getAsicMIBsCounter(0, cntr_idx, pCntr)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_stat_global_getAll\n * Description:\n *      Get all global MIB counter\n * Input:\n *      None\n * Output:\n *      pGlobal_cntrs - global counter structure.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n * Note:\n *      Get all global MIB counter by index definition.\n */\nrtk_api_ret_t rtk_stat_global_getAll(rtk_stat_global_cntr_t *pGlobal_cntrs)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(NULL == pGlobal_cntrs)\n        return RT_ERR_NULL_POINTER;\n\n    if ((retVal = rtl8367c_getAsicMIBsCounter(0,DOT1D_TP_LEARNED_ENTRY_DISCARDS_INDEX, &pGlobal_cntrs->dot1dTpLearnedEntryDiscards)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n#define MIB_NOT_SUPPORT     (0xFFFF)\nstatic rtk_api_ret_t _get_asic_mib_idx(rtk_stat_port_type_t cnt_idx, RTL8367C_MIBCOUNTER *pMib_idx)\n{\n    RTL8367C_MIBCOUNTER mib_asic_idx[STAT_PORT_CNTR_END]=\n    {\n        ifInOctets,                     /* STAT_IfInOctets */\n        dot3StatsFCSErrors,             /* STAT_Dot3StatsFCSErrors */\n        dot3StatsSymbolErrors,          /* STAT_Dot3StatsSymbolErrors */\n        dot3InPauseFrames,              /* STAT_Dot3InPauseFrames */\n        dot3ControlInUnknownOpcodes,    /* STAT_Dot3ControlInUnknownOpcodes */\n        etherStatsFragments,            /* STAT_EtherStatsFragments */\n        etherStatsJabbers,              /* STAT_EtherStatsJabbers */\n        ifInUcastPkts,                  /* STAT_IfInUcastPkts */\n        etherStatsDropEvents,           /* STAT_EtherStatsDropEvents */\n        etherStatsOctets,               /* STAT_EtherStatsOctets */\n        etherStatsUnderSizePkts,        /* STAT_EtherStatsUnderSizePkts */\n        etherOversizeStats,             /* STAT_EtherOversizeStats */\n        etherStatsPkts64Octets,         /* STAT_EtherStatsPkts64Octets */\n        etherStatsPkts65to127Octets,    /* STAT_EtherStatsPkts65to127Octets */\n        etherStatsPkts128to255Octets,   /* STAT_EtherStatsPkts128to255Octets */\n        etherStatsPkts256to511Octets,   /* STAT_EtherStatsPkts256to511Octets */\n        etherStatsPkts512to1023Octets,  /* STAT_EtherStatsPkts512to1023Octets */\n        etherStatsPkts1024to1518Octets, /* STAT_EtherStatsPkts1024to1518Octets */\n        ifInMulticastPkts,              /* STAT_EtherStatsMulticastPkts */\n        ifInBroadcastPkts,              /* STAT_EtherStatsBroadcastPkts */\n        ifOutOctets,                    /* STAT_IfOutOctets */\n        dot3StatsSingleCollisionFrames, /* STAT_Dot3StatsSingleCollisionFrames */\n        dot3StatMultipleCollisionFrames,/* STAT_Dot3StatsMultipleCollisionFrames */\n        dot3sDeferredTransmissions,     /* STAT_Dot3StatsDeferredTransmissions */\n        dot3StatsLateCollisions,        /* STAT_Dot3StatsLateCollisions */\n        etherStatsCollisions,           /* STAT_EtherStatsCollisions */\n        dot3StatsExcessiveCollisions,   /* STAT_Dot3StatsExcessiveCollisions */\n        dot3OutPauseFrames,             /* STAT_Dot3OutPauseFrames */\n        MIB_NOT_SUPPORT,                /* STAT_Dot1dBasePortDelayExceededDiscards */\n        dot1dTpPortInDiscards,          /* STAT_Dot1dTpPortInDiscards */\n        ifOutUcastPkts,                 /* STAT_IfOutUcastPkts */\n        ifOutMulticastPkts,             /* STAT_IfOutMulticastPkts */\n        ifOutBroadcastPkts,             /* STAT_IfOutBroadcastPkts */\n        outOampduPkts,                  /* STAT_OutOampduPkts */\n        inOampduPkts,                   /* STAT_InOampduPkts */\n        MIB_NOT_SUPPORT,                /* STAT_PktgenPkts */\n        inMldChecksumError,             /* STAT_InMldChecksumError */\n        inIgmpChecksumError,            /* STAT_InIgmpChecksumError */\n        inMldSpecificQuery,             /* STAT_InMldSpecificQuery */\n        inMldGeneralQuery,              /* STAT_InMldGeneralQuery */\n        inIgmpSpecificQuery,            /* STAT_InIgmpSpecificQuery */\n        inIgmpGeneralQuery,             /* STAT_InIgmpGeneralQuery */\n        inMldLeaves,                    /* STAT_InMldLeaves */\n        inIgmpLeaves,                   /* STAT_InIgmpInterfaceLeaves */\n        inIgmpJoinsSuccess,             /* STAT_InIgmpJoinsSuccess */\n        inIgmpJoinsFail,                /* STAT_InIgmpJoinsFail */\n        inMldJoinsSuccess,              /* STAT_InMldJoinsSuccess */\n        inMldJoinsFail,                 /* STAT_InMldJoinsFail */\n        inReportSuppressionDrop,        /* STAT_InReportSuppressionDrop */\n        inLeaveSuppressionDrop,         /* STAT_InLeaveSuppressionDrop */\n        outIgmpReports,                 /* STAT_OutIgmpReports */\n        outIgmpLeaves,                  /* STAT_OutIgmpLeaves */\n        outIgmpGeneralQuery,            /* STAT_OutIgmpGeneralQuery */\n        outIgmpSpecificQuery,           /* STAT_OutIgmpSpecificQuery */\n        outMldReports,                  /* STAT_OutMldReports */\n        outMldLeaves,                   /* STAT_OutMldLeaves */\n        outMldGeneralQuery,             /* STAT_OutMldGeneralQuery */\n        outMldSpecificQuery,            /* STAT_OutMldSpecificQuery */\n        inKnownMulticastPkts,           /* STAT_InKnownMulticastPkts */\n        ifInMulticastPkts,              /* STAT_IfInMulticastPkts */\n        ifInBroadcastPkts,              /* STAT_IfInBroadcastPkts */\n        ifOutDiscards                   /* STAT_IfOutDiscards */\n    };\n\n    if(cnt_idx >= STAT_PORT_CNTR_END)\n        return RT_ERR_STAT_INVALID_PORT_CNTR;\n\n    if(mib_asic_idx[cnt_idx] == MIB_NOT_SUPPORT)\n        return RT_ERR_CHIP_NOT_SUPPORTED;\n\n    *pMib_idx = mib_asic_idx[cnt_idx];\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_stat_port_get\n * Description:\n *      Get per port MIB counter by index\n * Input:\n *      port        - port id.\n *      cntr_idx    - port counter index.\n * Output:\n *      pCntr - MIB retrived counter.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n * Note:\n *      Get per port MIB counter by index definition.\n */\nrtk_api_ret_t rtk_stat_port_get(rtk_port_t port, rtk_stat_port_type_t cntr_idx, rtk_stat_counter_t *pCntr)\n{\n    rtk_api_ret_t       retVal;\n    RTL8367C_MIBCOUNTER mib_idx;\n    rtk_stat_counter_t  second_cnt;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(NULL == pCntr)\n        return RT_ERR_NULL_POINTER;\n\n    /* Check port valid */\n    RTK_CHK_PORT_VALID(port);\n\n    if (cntr_idx>=STAT_PORT_CNTR_END)\n        return RT_ERR_STAT_INVALID_PORT_CNTR;\n\n    if((retVal = _get_asic_mib_idx(cntr_idx, &mib_idx)) != RT_ERR_OK)\n        return retVal;\n\n    if(mib_idx == MIB_NOT_SUPPORT)\n        return RT_ERR_CHIP_NOT_SUPPORTED;\n\n    if ((retVal = rtl8367c_getAsicMIBsCounter(rtk_switch_port_L2P_get(port), mib_idx, pCntr)) != RT_ERR_OK)\n        return retVal;\n\n    if(cntr_idx == STAT_EtherStatsMulticastPkts)\n    {\n        if((retVal = _get_asic_mib_idx(STAT_IfOutMulticastPkts, &mib_idx)) != RT_ERR_OK)\n            return retVal;\n\n        if((retVal = rtl8367c_getAsicMIBsCounter(rtk_switch_port_L2P_get(port), mib_idx, &second_cnt)) != RT_ERR_OK)\n            return retVal;\n\n        *pCntr += second_cnt;\n    }\n\n    if(cntr_idx == STAT_EtherStatsBroadcastPkts)\n    {\n        if((retVal = _get_asic_mib_idx(STAT_IfOutBroadcastPkts, &mib_idx)) != RT_ERR_OK)\n            return retVal;\n\n        if((retVal = rtl8367c_getAsicMIBsCounter(rtk_switch_port_L2P_get(port), mib_idx, &second_cnt)) != RT_ERR_OK)\n            return retVal;\n\n        *pCntr += second_cnt;\n    }\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_stat_port_getAll\n * Description:\n *      Get all counters of one specified port in the specified device.\n * Input:\n *      port - port id.\n * Output:\n *      pPort_cntrs - buffer pointer of counter value.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n * Note:\n *      Get all MIB counters of one port.\n */\nrtk_api_ret_t rtk_stat_port_getAll(rtk_port_t port, rtk_stat_port_cntr_t *pPort_cntrs)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32 mibIndex;\n    rtk_uint64 mibCounter;\n    rtk_uint32 *accessPtr;\n    /* address offset to MIBs counter */\n    CONST_T rtk_uint16 mibLength[STAT_PORT_CNTR_END]= {\n        2,1,1,1,1,1,1,1,1,\n        2,1,1,1,1,1,1,1,1,1,1,\n        2,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,\n        1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1};\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(NULL == pPort_cntrs)\n        return RT_ERR_NULL_POINTER;\n\n    /* Check port valid */\n    RTK_CHK_PORT_VALID(port);\n\n    accessPtr = (rtk_uint32*)pPort_cntrs;\n    for (mibIndex=0;mibIndex<STAT_PORT_CNTR_END;mibIndex++)\n    {\n        if ((retVal = rtk_stat_port_get(port, mibIndex, &mibCounter)) != RT_ERR_OK)\n        {\n            if (retVal == RT_ERR_CHIP_NOT_SUPPORTED)\n                mibCounter = 0;\n            else\n                return retVal;\n        }\n\n        if (2 == mibLength[mibIndex])\n            *(rtk_uint64*)accessPtr = mibCounter;\n        else if (1 == mibLength[mibIndex])\n            *accessPtr = mibCounter;\n        else\n            return RT_ERR_FAILED;\n\n        accessPtr+=mibLength[mibIndex];\n    }\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_stat_logging_counterCfg_set\n * Description:\n *      Set the type and mode of Logging Counter\n * Input:\n *      idx     - The index of Logging Counter. Should be even number only.(0,2,4,6,8.....30)\n *      mode    - 32 bits or 64 bits mode\n *      type    - Packet counter or byte counter\n * Output:\n *      None.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_OUT_OF_RANGE - Out of range.\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n * Note:\n *      Set the type and mode of Logging Counter.\n */\nrtk_api_ret_t rtk_stat_logging_counterCfg_set(rtk_uint32 idx, rtk_logging_counter_mode_t mode, rtk_logging_counter_type_t type)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(idx > RTL8367C_MIB_MAX_LOG_CNT_IDX)\n        return RT_ERR_OUT_OF_RANGE;\n\n    if((idx % 2) == 1)\n        return RT_ERR_INPUT;\n\n    if(mode >= LOGGING_MODE_END)\n        return RT_ERR_OUT_OF_RANGE;\n\n    if(type >= LOGGING_TYPE_END)\n        return RT_ERR_OUT_OF_RANGE;\n\n    if((retVal = rtl8367c_setAsicMIBsLoggingType((idx / 2), (rtk_uint32)type)) != RT_ERR_OK)\n        return retVal;\n\n    if((retVal = rtl8367c_setAsicMIBsLoggingMode((idx / 2), (rtk_uint32)mode)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_stat_logging_counterCfg_get\n * Description:\n *      Get the type and mode of Logging Counter\n * Input:\n *      idx     - The index of Logging Counter. Should be even number only.(0,2,4,6,8.....30)\n * Output:\n *      pMode   - 32 bits or 64 bits mode\n *      pType   - Packet counter or byte counter\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_OUT_OF_RANGE - Out of range.\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_NULL_POINTER - NULL Pointer\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n * Note:\n *      Get the type and mode of Logging Counter.\n */\nrtk_api_ret_t rtk_stat_logging_counterCfg_get(rtk_uint32 idx, rtk_logging_counter_mode_t *pMode, rtk_logging_counter_type_t *pType)\n{\n    rtk_api_ret_t   retVal;\n    rtk_uint32      type, mode;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(idx > RTL8367C_MIB_MAX_LOG_CNT_IDX)\n        return RT_ERR_OUT_OF_RANGE;\n\n    if((idx % 2) == 1)\n        return RT_ERR_INPUT;\n\n    if(pMode == NULL)\n        return RT_ERR_NULL_POINTER;\n\n    if(pType == NULL)\n        return RT_ERR_NULL_POINTER;\n\n    if((retVal = rtl8367c_getAsicMIBsLoggingType((idx / 2), &type)) != RT_ERR_OK)\n        return retVal;\n\n    if((retVal = rtl8367c_getAsicMIBsLoggingMode((idx / 2), &mode)) != RT_ERR_OK)\n        return retVal;\n\n    *pMode = (rtk_logging_counter_mode_t)mode;\n    *pType = (rtk_logging_counter_type_t)type;\n\n    return RT_ERR_OK;\n}\n\n\n/* Function Name:\n *      rtk_stat_logging_counter_reset\n * Description:\n *      Reset Logging Counter\n * Input:\n *      idx     - The index of Logging Counter. (0~31)\n * Output:\n *      None.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_OUT_OF_RANGE - Out of range.\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n * Note:\n *      Reset Logging Counter.\n */\nrtk_api_ret_t rtk_stat_logging_counter_reset(rtk_uint32 idx)\n{\n    rtk_api_ret_t   retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(idx > RTL8367C_MIB_MAX_LOG_CNT_IDX)\n        return RT_ERR_OUT_OF_RANGE;\n\n    if((retVal = rtl8367c_setAsicMIBsResetLoggingCounter(idx)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_stat_logging_counter_get\n * Description:\n *      Get Logging Counter\n * Input:\n *      idx     - The index of Logging Counter. (0~31)\n * Output:\n *      pCnt    - Logging counter value\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_OUT_OF_RANGE - Out of range.\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n * Note:\n *      Get Logging Counter.\n */\nrtk_api_ret_t rtk_stat_logging_counter_get(rtk_uint32 idx, rtk_uint32 *pCnt)\n{\n    rtk_api_ret_t   retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(NULL == pCnt)\n        return RT_ERR_NULL_POINTER;\n\n    if(idx > RTL8367C_MIB_MAX_LOG_CNT_IDX)\n        return RT_ERR_OUT_OF_RANGE;\n\n    if((retVal = rtl8367c_getAsicMIBsLogCounter(idx, pCnt)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_stat_lengthMode_set\n * Description:\n *      Set Legnth mode.\n * Input:\n *      txMode     - The length counting mode\n *      rxMode     - The length counting mode\n * Output:\n *      None.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_INPUT        - Out of range.\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n * Note:\n *\n */\nrtk_api_ret_t rtk_stat_lengthMode_set(rtk_stat_lengthMode_t txMode, rtk_stat_lengthMode_t rxMode)\n{\n    rtk_api_ret_t   retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(txMode >= LENGTH_MODE_END)\n        return RT_ERR_INPUT;\n\n    if(rxMode >= LENGTH_MODE_END)\n        return RT_ERR_INPUT;\n\n    if((retVal = rtl8367c_setAsicMIBsLength((rtk_uint32)txMode, (rtk_uint32)rxMode)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_stat_lengthMode_get\n * Description:\n *      Get Legnth mode.\n * Input:\n *      None.\n * Output:\n *      pTxMode       - The length counting mode\n *      pRxMode       - The length counting mode\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_INPUT        - Out of range.\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n * Note:\n */\nrtk_api_ret_t rtk_stat_lengthMode_get(rtk_stat_lengthMode_t *pTxMode, rtk_stat_lengthMode_t *pRxMode)\n{\n    rtk_api_ret_t   retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(NULL == pTxMode)\n        return RT_ERR_NULL_POINTER;\n\n    if(NULL == pRxMode)\n        return RT_ERR_NULL_POINTER;\n\n    if((retVal = rtl8367c_getAsicMIBsLength((rtk_uint32 *)pTxMode, (rtk_uint32 *)pRxMode)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/storm.c",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * $Revision: 76306 $\n * $Date: 2017-03-08 15:13:58 +0800 (週三, 08 三月 2017) $\n *\n * Purpose : RTK switch high-level API for RTL8367/RTL8367C\n * Feature : Here is a list of all functions and variables in Storm module.\n *\n */\n\n#include <rtk_switch.h>\n#include <rtk_error.h>\n#include <storm.h>\n#include <rate.h>\n#include <string.h>\n#include <rtl8367c_asicdrv.h>\n#include <rtl8367c_asicdrv_storm.h>\n#include <rtl8367c_asicdrv_meter.h>\n#include <rtl8367c_asicdrv_rma.h>\n#include <rtl8367c_asicdrv_igmp.h>\n\n/* Function Name:\n *      rtk_rate_stormControlMeterIdx_set\n * Description:\n *      Set the storm control meter index.\n * Input:\n *      port       - port id\n *      storm_type - storm group type\n *      index       - storm control meter index.\n * Output:\n *      None.\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n *      RT_ERR_PORT_ID - Invalid port id\n *      RT_ERR_FILTER_METER_ID  - Invalid meter\n * Note:\n *\n */\nrtk_api_ret_t rtk_rate_stormControlMeterIdx_set(rtk_port_t port, rtk_rate_storm_group_t stormType, rtk_uint32 index)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check Port Valid */\n    RTK_CHK_PORT_VALID(port);\n\n    if (stormType >= STORM_GROUP_END)\n        return RT_ERR_SFC_UNKNOWN_GROUP;\n\n    if (index > RTK_MAX_METER_ID)\n        return RT_ERR_FILTER_METER_ID;\n\n    switch (stormType)\n    {\n        case STORM_GROUP_UNKNOWN_UNICAST:\n            if ((retVal = rtl8367c_setAsicStormFilterUnknownUnicastMeter(rtk_switch_port_L2P_get(port), index))!=RT_ERR_OK)\n                return retVal;\n            break;\n        case STORM_GROUP_UNKNOWN_MULTICAST:\n            if ((retVal = rtl8367c_setAsicStormFilterUnknownMulticastMeter(rtk_switch_port_L2P_get(port), index))!=RT_ERR_OK)\n                return retVal;\n            break;\n        case STORM_GROUP_MULTICAST:\n            if ((retVal = rtl8367c_setAsicStormFilterMulticastMeter(rtk_switch_port_L2P_get(port), index))!=RT_ERR_OK)\n                return retVal;\n            break;\n        case STORM_GROUP_BROADCAST:\n            if ((retVal = rtl8367c_setAsicStormFilterBroadcastMeter(rtk_switch_port_L2P_get(port), index))!=RT_ERR_OK)\n                return retVal;\n            break;\n        default:\n            break;\n    }\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_rate_stormControlMeterIdx_get\n * Description:\n *      Get the storm control meter index.\n * Input:\n *      port       - port id\n *      storm_type - storm group type\n * Output:\n *      pIndex     - storm control meter index.\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n *      RT_ERR_PORT_ID - Invalid port id\n *      RT_ERR_FILTER_METER_ID  - Invalid meter\n * Note:\n *\n */\nrtk_api_ret_t rtk_rate_stormControlMeterIdx_get(rtk_port_t port, rtk_rate_storm_group_t stormType, rtk_uint32 *pIndex)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check Port Valid */\n    RTK_CHK_PORT_VALID(port);\n\n    if (stormType >= STORM_GROUP_END)\n        return RT_ERR_SFC_UNKNOWN_GROUP;\n\n    if (NULL == pIndex )\n        return RT_ERR_NULL_POINTER;\n\n    switch (stormType)\n    {\n        case STORM_GROUP_UNKNOWN_UNICAST:\n            if ((retVal = rtl8367c_getAsicStormFilterUnknownUnicastMeter(rtk_switch_port_L2P_get(port), pIndex))!=RT_ERR_OK)\n                return retVal;\n            break;\n        case STORM_GROUP_UNKNOWN_MULTICAST:\n            if ((retVal = rtl8367c_getAsicStormFilterUnknownMulticastMeter(rtk_switch_port_L2P_get(port), pIndex))!=RT_ERR_OK)\n                return retVal;\n            break;\n        case STORM_GROUP_MULTICAST:\n            if ((retVal = rtl8367c_getAsicStormFilterMulticastMeter(rtk_switch_port_L2P_get(port), pIndex))!=RT_ERR_OK)\n                return retVal;\n            break;\n        case STORM_GROUP_BROADCAST:\n            if ((retVal = rtl8367c_getAsicStormFilterBroadcastMeter(rtk_switch_port_L2P_get(port), pIndex))!=RT_ERR_OK)\n                return retVal;\n            break;\n        default:\n            break;\n    }\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_rate_stormControlPortEnable_set\n * Description:\n *      Set enable status of storm control on specified port.\n * Input:\n *      port       - port id\n *      stormType  - storm group type\n *      enable     - enable status of storm control\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n *      RT_ERR_NOT_INIT          - The module is not initial\n *      RT_ERR_PORT_ID           - invalid port id\n *      RT_ERR_INPUT             - invalid input parameter\n * Note:\n *\n */\nrtk_api_ret_t rtk_rate_stormControlPortEnable_set(rtk_port_t port, rtk_rate_storm_group_t stormType, rtk_enable_t enable)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check Port Valid */\n    RTK_CHK_PORT_VALID(port);\n\n    if (stormType >= STORM_GROUP_END)\n        return RT_ERR_SFC_UNKNOWN_GROUP;\n\n    if (enable >= RTK_ENABLE_END)\n        return RT_ERR_ENABLE;\n\n    switch (stormType)\n    {\n        case STORM_GROUP_UNKNOWN_UNICAST:\n            if ((retVal = rtl8367c_setAsicStormFilterUnknownUnicastEnable(rtk_switch_port_L2P_get(port), enable)) != RT_ERR_OK)\n                return retVal;\n            break;\n        case STORM_GROUP_UNKNOWN_MULTICAST:\n            if ((retVal = rtl8367c_setAsicStormFilterUnknownMulticastEnable(rtk_switch_port_L2P_get(port), enable)) != RT_ERR_OK)\n                return retVal;\n            break;\n        case STORM_GROUP_MULTICAST:\n            if ((retVal = rtl8367c_setAsicStormFilterMulticastEnable(rtk_switch_port_L2P_get(port), enable)) != RT_ERR_OK)\n                return retVal;\n            break;\n        case STORM_GROUP_BROADCAST:\n            if ((retVal = rtl8367c_setAsicStormFilterBroadcastEnable(rtk_switch_port_L2P_get(port), enable)) != RT_ERR_OK)\n                return retVal;\n            break;\n        default:\n            break;\n    }\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_rate_stormControlPortEnable_set\n * Description:\n *      Set enable status of storm control on specified port.\n * Input:\n *      port       - port id\n *      stormType  - storm group type\n * Output:\n *      pEnable     - enable status of storm control\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n *      RT_ERR_NOT_INIT          - The module is not initial\n *      RT_ERR_PORT_ID           - invalid port id\n *      RT_ERR_INPUT             - invalid input parameter\n * Note:\n *\n */\nrtk_api_ret_t rtk_rate_stormControlPortEnable_get(rtk_port_t port, rtk_rate_storm_group_t stormType, rtk_enable_t *pEnable)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check Port Valid */\n    RTK_CHK_PORT_VALID(port);\n\n    if (stormType >= STORM_GROUP_END)\n        return RT_ERR_SFC_UNKNOWN_GROUP;\n\n    if (NULL == pEnable)\n        return RT_ERR_ENABLE;\n\n    switch (stormType)\n    {\n        case STORM_GROUP_UNKNOWN_UNICAST:\n            if ((retVal = rtl8367c_getAsicStormFilterUnknownUnicastEnable(rtk_switch_port_L2P_get(port), pEnable)) != RT_ERR_OK)\n                return retVal;\n            break;\n        case STORM_GROUP_UNKNOWN_MULTICAST:\n            if ((retVal = rtl8367c_getAsicStormFilterUnknownMulticastEnable(rtk_switch_port_L2P_get(port), pEnable)) != RT_ERR_OK)\n                return retVal;\n            break;\n        case STORM_GROUP_MULTICAST:\n            if ((retVal = rtl8367c_getAsicStormFilterMulticastEnable(rtk_switch_port_L2P_get(port), pEnable)) != RT_ERR_OK)\n                return retVal;\n            break;\n        case STORM_GROUP_BROADCAST:\n            if ((retVal = rtl8367c_getAsicStormFilterBroadcastEnable(rtk_switch_port_L2P_get(port), pEnable)) != RT_ERR_OK)\n                return retVal;\n            break;\n        default:\n            break;\n    }\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_storm_bypass_set\n * Description:\n *      Set bypass storm filter control configuration.\n * Input:\n *      type    - Bypass storm filter control type.\n *      enable  - Bypass status.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n *      RT_ERR_ENABLE       - Invalid IFG parameter\n * Note:\n *\n *      This API can set per-port bypass stomr filter control frame type including RMA and igmp.\n *      The bypass frame type is as following:\n *      - BYPASS_BRG_GROUP,\n *      - BYPASS_FD_PAUSE,\n *      - BYPASS_SP_MCAST,\n *      - BYPASS_1X_PAE,\n *      - BYPASS_UNDEF_BRG_04,\n *      - BYPASS_UNDEF_BRG_05,\n *      - BYPASS_UNDEF_BRG_06,\n *      - BYPASS_UNDEF_BRG_07,\n *      - BYPASS_PROVIDER_BRIDGE_GROUP_ADDRESS,\n *      - BYPASS_UNDEF_BRG_09,\n *      - BYPASS_UNDEF_BRG_0A,\n *      - BYPASS_UNDEF_BRG_0B,\n *      - BYPASS_UNDEF_BRG_0C,\n *      - BYPASS_PROVIDER_BRIDGE_GVRP_ADDRESS,\n *      - BYPASS_8021AB,\n *      - BYPASS_UNDEF_BRG_0F,\n *      - BYPASS_BRG_MNGEMENT,\n *      - BYPASS_UNDEFINED_11,\n *      - BYPASS_UNDEFINED_12,\n *      - BYPASS_UNDEFINED_13,\n *      - BYPASS_UNDEFINED_14,\n *      - BYPASS_UNDEFINED_15,\n *      - BYPASS_UNDEFINED_16,\n *      - BYPASS_UNDEFINED_17,\n *      - BYPASS_UNDEFINED_18,\n *      - BYPASS_UNDEFINED_19,\n *      - BYPASS_UNDEFINED_1A,\n *      - BYPASS_UNDEFINED_1B,\n *      - BYPASS_UNDEFINED_1C,\n *      - BYPASS_UNDEFINED_1D,\n *      - BYPASS_UNDEFINED_1E,\n *      - BYPASS_UNDEFINED_1F,\n *      - BYPASS_GMRP,\n *      - BYPASS_GVRP,\n *      - BYPASS_UNDEF_GARP_22,\n *      - BYPASS_UNDEF_GARP_23,\n *      - BYPASS_UNDEF_GARP_24,\n *      - BYPASS_UNDEF_GARP_25,\n *      - BYPASS_UNDEF_GARP_26,\n *      - BYPASS_UNDEF_GARP_27,\n *      - BYPASS_UNDEF_GARP_28,\n *      - BYPASS_UNDEF_GARP_29,\n *      - BYPASS_UNDEF_GARP_2A,\n *      - BYPASS_UNDEF_GARP_2B,\n *      - BYPASS_UNDEF_GARP_2C,\n *      - BYPASS_UNDEF_GARP_2D,\n *      - BYPASS_UNDEF_GARP_2E,\n *      - BYPASS_UNDEF_GARP_2F,\n *      - BYPASS_IGMP.\n *      - BYPASS_CDP.\n *      - BYPASS_CSSTP.\n *      - BYPASS_LLDP.\n */\nrtk_api_ret_t rtk_storm_bypass_set(rtk_storm_bypass_t type, rtk_enable_t enable)\n{\n    rtk_api_ret_t retVal;\n    rtl8367c_rma_t rmacfg;\n    rtk_uint32 tmp;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if (type >= BYPASS_END)\n        return RT_ERR_INPUT;\n\n    if (enable >= RTK_ENABLE_END)\n        return RT_ERR_INPUT;\n\n    if (type >= 0 && type <= BYPASS_UNDEF_GARP_2F)\n    {\n        if ((retVal = rtl8367c_getAsicRma(type, &rmacfg)) != RT_ERR_OK)\n            return retVal;\n\n        rmacfg.discard_storm_filter = enable;\n\n        if ((retVal = rtl8367c_setAsicRma(type, &rmacfg)) != RT_ERR_OK)\n            return retVal;\n    }\n    else if(type == BYPASS_IGMP)\n    {\n        if ((retVal = rtl8367c_setAsicIGMPBypassStormCTRL(enable)) != RT_ERR_OK)\n            return retVal;\n    }\n    else if (type == BYPASS_CDP)\n    {\n        if ((retVal = rtl8367c_getAsicRmaCdp(&rmacfg)) != RT_ERR_OK)\n            return retVal;\n\n        rmacfg.discard_storm_filter = enable;\n\n        if ((retVal = rtl8367c_setAsicRmaCdp(&rmacfg)) != RT_ERR_OK)\n            return retVal;\n    }\n    else if (type  == BYPASS_CSSTP)\n    {\n        if ((retVal = rtl8367c_getAsicRmaCsstp(&rmacfg)) != RT_ERR_OK)\n            return retVal;\n\n        rmacfg.discard_storm_filter = enable;\n\n        if ((retVal = rtl8367c_setAsicRmaCsstp(&rmacfg)) != RT_ERR_OK)\n            return retVal;\n    }\n    else if (type  == BYPASS_LLDP)\n    {\n        if ((retVal = rtl8367c_getAsicRmaLldp(&tmp, &rmacfg)) != RT_ERR_OK)\n            return retVal;\n\n        rmacfg.discard_storm_filter = enable;\n\n        if ((retVal = rtl8367c_setAsicRmaLldp(tmp, &rmacfg)) != RT_ERR_OK)\n            return retVal;\n    }\n    else\n        return RT_ERR_INPUT;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_storm_bypass_get\n * Description:\n *      Get bypass storm filter control configuration.\n * Input:\n *      type - Bypass storm filter control type.\n * Output:\n *      pEnable - Bypass status.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n * Note:\n *      This API can get per-port bypass stomr filter control frame type including RMA and igmp.\n *      The bypass frame type is as following:\n *      - BYPASS_BRG_GROUP,\n *      - BYPASS_FD_PAUSE,\n *      - BYPASS_SP_MCAST,\n *      - BYPASS_1X_PAE,\n *      - BYPASS_UNDEF_BRG_04,\n *      - BYPASS_UNDEF_BRG_05,\n *      - BYPASS_UNDEF_BRG_06,\n *      - BYPASS_UNDEF_BRG_07,\n *      - BYPASS_PROVIDER_BRIDGE_GROUP_ADDRESS,\n *      - BYPASS_UNDEF_BRG_09,\n *      - BYPASS_UNDEF_BRG_0A,\n *      - BYPASS_UNDEF_BRG_0B,\n *      - BYPASS_UNDEF_BRG_0C,\n *      - BYPASS_PROVIDER_BRIDGE_GVRP_ADDRESS,\n *      - BYPASS_8021AB,\n *      - BYPASS_UNDEF_BRG_0F,\n *      - BYPASS_BRG_MNGEMENT,\n *      - BYPASS_UNDEFINED_11,\n *      - BYPASS_UNDEFINED_12,\n *      - BYPASS_UNDEFINED_13,\n *      - BYPASS_UNDEFINED_14,\n *      - BYPASS_UNDEFINED_15,\n *      - BYPASS_UNDEFINED_16,\n *      - BYPASS_UNDEFINED_17,\n *      - BYPASS_UNDEFINED_18,\n *      - BYPASS_UNDEFINED_19,\n *      - BYPASS_UNDEFINED_1A,\n *      - BYPASS_UNDEFINED_1B,\n *      - BYPASS_UNDEFINED_1C,\n *      - BYPASS_UNDEFINED_1D,\n *      - BYPASS_UNDEFINED_1E,\n *      - BYPASS_UNDEFINED_1F,\n *      - BYPASS_GMRP,\n *      - BYPASS_GVRP,\n *      - BYPASS_UNDEF_GARP_22,\n *      - BYPASS_UNDEF_GARP_23,\n *      - BYPASS_UNDEF_GARP_24,\n *      - BYPASS_UNDEF_GARP_25,\n *      - BYPASS_UNDEF_GARP_26,\n *      - BYPASS_UNDEF_GARP_27,\n *      - BYPASS_UNDEF_GARP_28,\n *      - BYPASS_UNDEF_GARP_29,\n *      - BYPASS_UNDEF_GARP_2A,\n *      - BYPASS_UNDEF_GARP_2B,\n *      - BYPASS_UNDEF_GARP_2C,\n *      - BYPASS_UNDEF_GARP_2D,\n *      - BYPASS_UNDEF_GARP_2E,\n *      - BYPASS_UNDEF_GARP_2F,\n *      - BYPASS_IGMP.\n *      - BYPASS_CDP.\n *      - BYPASS_CSSTP.\n *      - BYPASS_LLDP.\n */\nrtk_api_ret_t rtk_storm_bypass_get(rtk_storm_bypass_t type, rtk_enable_t *pEnable)\n{\n    rtk_api_ret_t retVal;\n    rtl8367c_rma_t rmacfg;\n    rtk_uint32 tmp;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if (type >= BYPASS_END)\n        return RT_ERR_INPUT;\n\n    if(NULL == pEnable)\n        return RT_ERR_NULL_POINTER;\n\n    if (type >= 0 && type <= BYPASS_UNDEF_GARP_2F)\n    {\n        if ((retVal = rtl8367c_getAsicRma(type, &rmacfg)) != RT_ERR_OK)\n            return retVal;\n\n        *pEnable = rmacfg.discard_storm_filter;\n    }\n    else if(type == BYPASS_IGMP)\n    {\n        if ((retVal = rtl8367c_getAsicIGMPBypassStormCTRL(pEnable)) != RT_ERR_OK)\n            return retVal;\n    }\n    else if (type == BYPASS_CDP)\n    {\n        if ((retVal = rtl8367c_getAsicRmaCdp(&rmacfg)) != RT_ERR_OK)\n            return retVal;\n\n        *pEnable = rmacfg.discard_storm_filter;\n    }\n    else if (type == BYPASS_CSSTP)\n    {\n        if ((retVal = rtl8367c_getAsicRmaCsstp(&rmacfg)) != RT_ERR_OK)\n            return retVal;\n\n        *pEnable = rmacfg.discard_storm_filter;\n    }\n    else if (type == BYPASS_LLDP)\n    {\n        if ((retVal = rtl8367c_getAsicRmaLldp(&tmp,&rmacfg)) != RT_ERR_OK)\n            return retVal;\n\n        *pEnable = rmacfg.discard_storm_filter;\n    }\n    else\n        return RT_ERR_INPUT;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_rate_stormControlExtPortmask_set\n * Description:\n *      Set externsion storm control port mask\n * Input:\n *      pPortmask  - port mask\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n *      RT_ERR_NOT_INIT          - The module is not initial\n *      RT_ERR_INPUT             - invalid input parameter\n * Note:\n *\n */\nrtk_api_ret_t rtk_rate_stormControlExtPortmask_set(rtk_portmask_t *pPortmask)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32 pmask;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(NULL == pPortmask)\n        return RT_ERR_NULL_POINTER;\n\n    if ((retVal = rtk_switch_portmask_L2P_get(pPortmask, &pmask)) != RT_ERR_OK)\n        return retVal;\n\n    if ((retVal = rtl8367c_setAsicStormFilterExtEnablePortMask(pmask)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_rate_stormControlExtPortmask_get\n * Description:\n *      Set externsion storm control port mask\n * Input:\n *      None\n * Output:\n *      pPortmask  - port mask\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n *      RT_ERR_NOT_INIT          - The module is not initial\n *      RT_ERR_INPUT             - invalid input parameter\n * Note:\n *\n */\nrtk_api_ret_t rtk_rate_stormControlExtPortmask_get(rtk_portmask_t *pPortmask)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32 pmask;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(NULL == pPortmask)\n        return RT_ERR_NULL_POINTER;\n\n    if ((retVal = rtl8367c_getAsicStormFilterExtEnablePortMask(&pmask)) != RT_ERR_OK)\n        return retVal;\n\n    if ((retVal = rtk_switch_portmask_P2L_get(pmask, pPortmask)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_rate_stormControlExtEnable_set\n * Description:\n *      Set externsion storm control state\n * Input:\n *      stormType   - storm group type\n *      enable      - externsion storm control state\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n *      RT_ERR_NOT_INIT          - The module is not initial\n *      RT_ERR_INPUT             - invalid input parameter\n * Note:\n *\n */\nrtk_api_ret_t rtk_rate_stormControlExtEnable_set(rtk_rate_storm_group_t stormType, rtk_enable_t enable)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if (stormType >= STORM_GROUP_END)\n        return RT_ERR_SFC_UNKNOWN_GROUP;\n\n    if (enable >= RTK_ENABLE_END)\n        return RT_ERR_ENABLE;\n\n    switch (stormType)\n    {\n        case STORM_GROUP_UNKNOWN_UNICAST:\n            if ((retVal = rtl8367c_setAsicStormFilterExtUnknownUnicastEnable(enable)) != RT_ERR_OK)\n                return retVal;\n            break;\n        case STORM_GROUP_UNKNOWN_MULTICAST:\n            if ((retVal = rtl8367c_setAsicStormFilterExtUnknownMulticastEnable(enable)) != RT_ERR_OK)\n                return retVal;\n            break;\n        case STORM_GROUP_MULTICAST:\n            if ((retVal = rtl8367c_setAsicStormFilterExtMulticastEnable(enable)) != RT_ERR_OK)\n                return retVal;\n            break;\n        case STORM_GROUP_BROADCAST:\n            if ((retVal = rtl8367c_setAsicStormFilterExtBroadcastEnable(enable)) != RT_ERR_OK)\n                return retVal;\n            break;\n        default:\n            break;\n    }\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_rate_stormControlExtEnable_get\n * Description:\n *      Get externsion storm control state\n * Input:\n *      stormType   - storm group type\n * Output:\n *      pEnable     - externsion storm control state\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n *      RT_ERR_NOT_INIT          - The module is not initial\n *      RT_ERR_INPUT             - invalid input parameter\n * Note:\n *\n */\nrtk_api_ret_t rtk_rate_stormControlExtEnable_get(rtk_rate_storm_group_t stormType, rtk_enable_t *pEnable)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if (stormType >= STORM_GROUP_END)\n        return RT_ERR_SFC_UNKNOWN_GROUP;\n\n    if (NULL == pEnable)\n        return RT_ERR_NULL_POINTER;\n\n    switch (stormType)\n    {\n        case STORM_GROUP_UNKNOWN_UNICAST:\n            if ((retVal = rtl8367c_getAsicStormFilterExtUnknownUnicastEnable((rtk_uint32 *)pEnable)) != RT_ERR_OK)\n                return retVal;\n            break;\n        case STORM_GROUP_UNKNOWN_MULTICAST:\n            if ((retVal = rtl8367c_getAsicStormFilterExtUnknownMulticastEnable((rtk_uint32 *)pEnable)) != RT_ERR_OK)\n                return retVal;\n            break;\n        case STORM_GROUP_MULTICAST:\n            if ((retVal = rtl8367c_getAsicStormFilterExtMulticastEnable((rtk_uint32 *)pEnable)) != RT_ERR_OK)\n                return retVal;\n            break;\n        case STORM_GROUP_BROADCAST:\n            if ((retVal = rtl8367c_getAsicStormFilterExtBroadcastEnable((rtk_uint32 *)pEnable)) != RT_ERR_OK)\n                return retVal;\n            break;\n        default:\n            break;\n    }\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_rate_stormControlExtMeterIdx_set\n * Description:\n *      Set externsion storm control meter index\n * Input:\n *      stormType   - storm group type\n *      index       - externsion storm control state\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n *      RT_ERR_NOT_INIT          - The module is not initial\n *      RT_ERR_INPUT             - invalid input parameter\n * Note:\n *\n */\nrtk_api_ret_t rtk_rate_stormControlExtMeterIdx_set(rtk_rate_storm_group_t stormType, rtk_uint32 index)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if (stormType >= STORM_GROUP_END)\n        return RT_ERR_SFC_UNKNOWN_GROUP;\n\n    if (index > RTK_MAX_METER_ID)\n        return RT_ERR_FILTER_METER_ID;\n\n    switch (stormType)\n    {\n        case STORM_GROUP_UNKNOWN_UNICAST:\n            if ((retVal = rtl8367c_setAsicStormFilterExtUnknownUnicastMeter(index))!=RT_ERR_OK)\n                return retVal;\n            break;\n        case STORM_GROUP_UNKNOWN_MULTICAST:\n            if ((retVal = rtl8367c_setAsicStormFilterExtUnknownMulticastMeter(index))!=RT_ERR_OK)\n                return retVal;\n            break;\n        case STORM_GROUP_MULTICAST:\n            if ((retVal = rtl8367c_setAsicStormFilterExtMulticastMeter(index))!=RT_ERR_OK)\n                return retVal;\n            break;\n        case STORM_GROUP_BROADCAST:\n            if ((retVal = rtl8367c_setAsicStormFilterExtBroadcastMeter(index))!=RT_ERR_OK)\n                return retVal;\n            break;\n        default:\n            break;\n    }\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_rate_stormControlExtMeterIdx_get\n * Description:\n *      Get externsion storm control meter index\n * Input:\n *      stormType   - storm group type\n *      pIndex      - externsion storm control state\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n *      RT_ERR_NOT_INIT          - The module is not initial\n *      RT_ERR_INPUT             - invalid input parameter\n * Note:\n *\n */\nrtk_api_ret_t rtk_rate_stormControlExtMeterIdx_get(rtk_rate_storm_group_t stormType, rtk_uint32 *pIndex)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if (stormType >= STORM_GROUP_END)\n        return RT_ERR_SFC_UNKNOWN_GROUP;\n\n    if(NULL == pIndex)\n        return RT_ERR_NULL_POINTER;\n\n    switch (stormType)\n    {\n        case STORM_GROUP_UNKNOWN_UNICAST:\n            if ((retVal = rtl8367c_getAsicStormFilterExtUnknownUnicastMeter(pIndex))!=RT_ERR_OK)\n                return retVal;\n            break;\n        case STORM_GROUP_UNKNOWN_MULTICAST:\n            if ((retVal = rtl8367c_getAsicStormFilterExtUnknownMulticastMeter(pIndex))!=RT_ERR_OK)\n                return retVal;\n            break;\n        case STORM_GROUP_MULTICAST:\n            if ((retVal = rtl8367c_getAsicStormFilterExtMulticastMeter(pIndex))!=RT_ERR_OK)\n                return retVal;\n            break;\n        case STORM_GROUP_BROADCAST:\n            if ((retVal = rtl8367c_getAsicStormFilterExtBroadcastMeter(pIndex))!=RT_ERR_OK)\n                return retVal;\n            break;\n        default:\n            break;\n    }\n\n    return RT_ERR_OK;\n}\n\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/svlan.c",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * $Revision: 76306 $\n * $Date: 2017-03-08 15:13:58 +0800 (週三, 08 三月 2017) $\n *\n * Purpose : RTK switch high-level API for RTL8367/RTL8367C\n * Feature : Here is a list of all functions and variables in SVLAN module.\n *\n */\n\n#include <rtk_switch.h>\n#include <rtk_error.h>\n#include <svlan.h>\n#include <vlan.h>\n#include <string.h>\n\n#include <rtl8367c_asicdrv.h>\n#include <rtl8367c_asicdrv_svlan.h>\n\nrtk_uint8               svlan_mbrCfgUsage[RTL8367C_SVIDXNO];\nrtk_uint16              svlan_mbrCfgVid[RTL8367C_SVIDXNO];\nrtk_svlan_lookupType_t  svlan_lookupType;\n/* Function Name:\n *      rtk_svlan_init\n * Description:\n *      Initialize SVLAN Configuration\n * Input:\n *      None\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n * Note:\n *      Ether type of S-tag in 802.1ad is 0x88a8 and there are existed ether type 0x9100 and 0x9200 for Q-in-Q SLAN design.\n *      User can set mathced ether type as service provider supported protocol.\n */\nrtk_api_ret_t rtk_svlan_init(void)\n{\n    rtk_uint32 i;\n    rtk_api_ret_t retVal;\n    rtl8367c_svlan_memconf_t svlanMemConf;\n    rtl8367c_svlan_s2c_t svlanSP2CConf;\n    rtl8367c_svlan_mc2s_t svlanMC2SConf;\n    rtk_uint32 svidx;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /*default use C-priority*/\n    if ((retVal = rtl8367c_setAsicSvlanPrioritySel(SPRISEL_CTAGPRI)) != RT_ERR_OK)\n        return retVal;\n\n    /*Drop SVLAN untag frame*/\n    if ((retVal = rtl8367c_setAsicSvlanIngressUntag(UNTAG_DROP)) != RT_ERR_OK)\n        return retVal;\n\n    /*Drop SVLAN unmatch frame*/\n    if ((retVal = rtl8367c_setAsicSvlanIngressUnmatch(UNMATCH_DROP)) != RT_ERR_OK)\n        return retVal;\n\n    /*Set TPID to 0x88a8*/\n    if ((retVal = rtl8367c_setAsicSvlanTpid(0x88a8)) != RT_ERR_OK)\n        return retVal;\n\n    /*Clean Uplink Port Mask to none*/\n    if ((retVal = rtl8367c_setAsicSvlanUplinkPortMask(0)) != RT_ERR_OK)\n        return retVal;\n\n    /*Clean SVLAN Member Configuration*/\n    for (i=0; i<= RTL8367C_SVIDXMAX; i++)\n    {\n        memset(&svlanMemConf, 0, sizeof(rtl8367c_svlan_memconf_t));\n        if ((retVal = rtl8367c_setAsicSvlanMemberConfiguration(i, &svlanMemConf)) != RT_ERR_OK)\n            return retVal;\n    }\n\n    /*Clean C2S Configuration*/\n    for (i=0; i<= RTL8367C_C2SIDXMAX; i++)\n    {\n        if ((retVal = rtl8367c_setAsicSvlanC2SConf(i, 0,0,0)) != RT_ERR_OK)\n            return retVal;\n    }\n\n    /*Clean SP2C Configuration*/\n    for (i=0; i <= RTL8367C_SP2CMAX ; i++)\n    {\n        memset(&svlanSP2CConf, 0, sizeof(rtl8367c_svlan_s2c_t));\n        if ((retVal = rtl8367c_setAsicSvlanSP2CConf(i, &svlanSP2CConf)) != RT_ERR_OK)\n            return retVal;\n    }\n\n    /*Clean MC2S Configuration*/\n    for (i=0 ; i<= RTL8367C_MC2SIDXMAX; i++)\n    {\n        memset(&svlanMC2SConf, 0, sizeof(rtl8367c_svlan_mc2s_t));\n        if ((retVal = rtl8367c_setAsicSvlanMC2SConf(i, &svlanMC2SConf)) != RT_ERR_OK)\n            return retVal;\n    }\n\n\n    if ((retVal = rtk_svlan_lookupType_set(SVLAN_LOOKUP_S64MBRCGF)) != RT_ERR_OK)\n        return retVal;\n\n\n    for (svidx = 0; svidx <= RTL8367C_SVIDXMAX; svidx++)\n    {\n        svlan_mbrCfgUsage[svidx] = FALSE;\n    }\n\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_svlan_servicePort_add\n * Description:\n *      Add one service port in the specified device\n * Input:\n *      port - Port id.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number.\n *      RT_ERR_INPUT        - Invalid input parameters.\n * Note:\n *      This API is setting which port is connected to provider switch. All frames receiving from this port must\n *      contain accept SVID in S-tag field.\n */\nrtk_api_ret_t rtk_svlan_servicePort_add(rtk_port_t port)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32 pmsk;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* check port valid */\n    RTK_CHK_PORT_VALID(port);\n\n    if ((retVal = rtl8367c_getAsicSvlanUplinkPortMask(&pmsk)) != RT_ERR_OK)\n        return retVal;\n\n    pmsk = pmsk | (1<<rtk_switch_port_L2P_get(port));\n\n    if ((retVal = rtl8367c_setAsicSvlanUplinkPortMask(pmsk)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_svlan_servicePort_get\n * Description:\n *      Get service ports in the specified device.\n * Input:\n *      None\n * Output:\n *      pSvlan_portmask - pointer buffer of svlan ports.\n * Return:\n *      RT_ERR_OK          - OK\n *      RT_ERR_FAILED      - Failed\n *      RT_ERR_SMI         - SMI access error\n * Note:\n *      This API is setting which port is connected to provider switch. All frames receiving from this port must\n *      contain accept SVID in S-tag field.\n */\nrtk_api_ret_t rtk_svlan_servicePort_get(rtk_portmask_t *pSvlan_portmask)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32 phyMbrPmask;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(NULL == pSvlan_portmask)\n        return RT_ERR_NULL_POINTER;\n\n    if ((retVal = rtl8367c_getAsicSvlanUplinkPortMask(&phyMbrPmask)) != RT_ERR_OK)\n        return retVal;\n\n    if(rtk_switch_portmask_P2L_get(phyMbrPmask, pSvlan_portmask) != RT_ERR_OK)\n        return RT_ERR_FAILED;\n\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_svlan_servicePort_del\n * Description:\n *      Delete one service port in the specified device\n * Input:\n *      port - Port id.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number.\n * Note:\n *      This API is removing SVLAN service port in the specified device.\n */\nrtk_api_ret_t rtk_svlan_servicePort_del(rtk_port_t port)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32 pmsk;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* check port valid */\n    RTK_CHK_PORT_VALID(port);\n\n    if ((retVal = rtl8367c_getAsicSvlanUplinkPortMask(&pmsk)) != RT_ERR_OK)\n        return retVal;\n\n    pmsk = pmsk & ~(1<<rtk_switch_port_L2P_get(port));\n\n    if ((retVal = rtl8367c_setAsicSvlanUplinkPortMask(pmsk)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_svlan_tpidEntry_set\n * Description:\n *      Configure accepted S-VLAN ether type.\n * Input:\n *      svlan_tag_id - Ether type of S-tag frame parsing in uplink ports.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameter.\n * Note:\n *      Ether type of S-tag in 802.1ad is 0x88a8 and there are existed ether type 0x9100 and 0x9200 for Q-in-Q SLAN design.\n *      User can set mathced ether type as service provider supported protocol.\n */\nrtk_api_ret_t rtk_svlan_tpidEntry_set(rtk_svlan_tpid_t svlan_tag_id)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if (svlan_tag_id>RTK_MAX_NUM_OF_PROTO_TYPE)\n        return RT_ERR_INPUT;\n\n    if ((retVal = rtl8367c_setAsicSvlanTpid(svlan_tag_id)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_svlan_tpidEntry_get\n * Description:\n *      Get accepted S-VLAN ether type setting.\n * Input:\n *      None\n * Output:\n *      pSvlan_tag_id -  Ether type of S-tag frame parsing in uplink ports.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n * Note:\n *      This API is setting which port is connected to provider switch. All frames receiving from this port must\n *      contain accept SVID in S-tag field.\n */\nrtk_api_ret_t rtk_svlan_tpidEntry_get(rtk_svlan_tpid_t *pSvlan_tag_id)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(NULL == pSvlan_tag_id)\n        return RT_ERR_NULL_POINTER;\n\n    if ((retVal = rtl8367c_getAsicSvlanTpid(pSvlan_tag_id)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_svlan_priorityRef_set\n * Description:\n *      Set S-VLAN upstream priority reference setting.\n * Input:\n *      ref - reference selection parameter.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameter.\n * Note:\n *      The API can set the upstream SVLAN tag priority reference source. The related priority\n *      sources are as following:\n *      - REF_INTERNAL_PRI,\n *      - REF_CTAG_PRI,\n *      - REF_SVLAN_PRI,\n *      - REF_PB_PRI.\n */\nrtk_api_ret_t rtk_svlan_priorityRef_set(rtk_svlan_pri_ref_t ref)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if (ref >= REF_PRI_END)\n        return RT_ERR_INPUT;\n\n    if ((retVal = rtl8367c_setAsicSvlanPrioritySel(ref)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_svlan_priorityRef_get\n * Description:\n *      Get S-VLAN upstream priority reference setting.\n * Input:\n *      None\n * Output:\n *      pRef - reference selection parameter.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n * Note:\n *      The API can get the upstream SVLAN tag priority reference source. The related priority\n *      sources are as following:\n *      - REF_INTERNAL_PRI,\n *      - REF_CTAG_PRI,\n *      - REF_SVLAN_PRI,\n *      - REF_PB_PRI\n */\nrtk_api_ret_t rtk_svlan_priorityRef_get(rtk_svlan_pri_ref_t *pRef)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(NULL == pRef)\n        return RT_ERR_NULL_POINTER;\n\n    if ((retVal = rtl8367c_getAsicSvlanPrioritySel(pRef)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_svlan_memberPortEntry_set\n * Description:\n *      Configure system SVLAN member content\n * Input:\n *      svid - SVLAN id\n *      psvlan_cfg - SVLAN member configuration\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - OK\n *      RT_ERR_FAILED           - Failed\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_INPUT            - Invalid input parameter.\n *      RT_ERR_SVLAN_VID        - Invalid SVLAN VID parameter.\n *      RT_ERR_PORT_MASK        - Invalid portmask.\n *      RT_ERR_SVLAN_TABLE_FULL - SVLAN configuration is full.\n * Note:\n *      The API can set system 64 accepted s-tag frame format. Only 64 SVID S-tag frame will be accpeted\n *      to receiving from uplink ports. Other SVID S-tag frame or S-untagged frame will be droped by default setup.\n *      - rtk_svlan_memberCfg_t->svid is SVID of SVLAN member configuration.\n *      - rtk_svlan_memberCfg_t->memberport is member port mask of SVLAN member configuration.\n *      - rtk_svlan_memberCfg_t->fid is filtering database of SVLAN member configuration.\n *      - rtk_svlan_memberCfg_t->priority is priority of SVLAN member configuration.\n */\nrtk_api_ret_t rtk_svlan_memberPortEntry_set(rtk_vlan_t svid, rtk_svlan_memberCfg_t *pSvlan_cfg)\n{\n    rtk_api_ret_t retVal;\n    rtk_int32 i;\n    rtk_uint32 empty_idx;\n    rtl8367c_svlan_memconf_t svlanMemConf;\n    rtk_uint32 phyMbrPmask;\n    rtk_vlan_cfg_t vlanCfg;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(NULL == pSvlan_cfg)\n        return RT_ERR_NULL_POINTER;\n\n    if(svid > RTL8367C_VIDMAX)\n        return RT_ERR_SVLAN_VID;\n\n    RTK_CHK_PORTMASK_VALID(&(pSvlan_cfg->memberport));\n\n    RTK_CHK_PORTMASK_VALID(&(pSvlan_cfg->untagport));\n\n    if (pSvlan_cfg->fiden > ENABLED)\n        return RT_ERR_ENABLE;\n\n    if (pSvlan_cfg->fid > RTL8367C_FIDMAX)\n        return RT_ERR_L2_FID;\n\n    if (pSvlan_cfg->priority > RTL8367C_PRIMAX)\n        return RT_ERR_VLAN_PRIORITY;\n\n    if (pSvlan_cfg->efiden > ENABLED)\n        return RT_ERR_ENABLE;\n\n    if (pSvlan_cfg->efid > RTL8367C_EFIDMAX)\n        return RT_ERR_L2_FID;\n\n    if(SVLAN_LOOKUP_C4KVLAN == svlan_lookupType)\n    {\n        if ((retVal = rtk_vlan_get(svid, &vlanCfg)) != RT_ERR_OK)\n            return retVal;\n\n        vlanCfg.mbr = pSvlan_cfg->memberport;\n        vlanCfg.untag = pSvlan_cfg->untagport;\n\n        if ((retVal = rtk_vlan_set(svid, &vlanCfg)) != RT_ERR_OK)\n            return retVal;\n\n        empty_idx = 0xFF;\n\n        for (i = 0; i<= RTL8367C_SVIDXMAX; i++)\n        {\n            if (svid == svlan_mbrCfgVid[i] && TRUE == svlan_mbrCfgUsage[i])\n            {\n                memset(&svlanMemConf, 0, sizeof(rtl8367c_svlan_memconf_t));\n                svlanMemConf.vs_svid        = svid;\n                svlanMemConf.vs_efiden      = pSvlan_cfg->efiden;\n                svlanMemConf.vs_efid        = pSvlan_cfg->efid;\n                svlanMemConf.vs_priority    = pSvlan_cfg->priority;\n\n                /*for create check*/\n                if(0 == svlanMemConf.vs_efiden && 0 == svlanMemConf.vs_efid)\n                    svlanMemConf.vs_efid = 1;\n\n                if ((retVal = rtl8367c_setAsicSvlanMemberConfiguration(i, &svlanMemConf)) != RT_ERR_OK)\n                    return retVal;\n\n                return RT_ERR_OK;\n            }\n            else if (FALSE == svlan_mbrCfgUsage[i] && 0xFF == empty_idx)\n            {\n                empty_idx = i;\n            }\n        }\n\n        if (empty_idx != 0xFF)\n        {\n            svlan_mbrCfgUsage[empty_idx] = TRUE;\n            svlan_mbrCfgVid[empty_idx] = svid;\n\n            memset(&svlanMemConf, 0, sizeof(rtl8367c_svlan_memconf_t));\n            svlanMemConf.vs_svid        = svid;\n            svlanMemConf.vs_efiden      = pSvlan_cfg->efiden;\n            svlanMemConf.vs_efid        = pSvlan_cfg->efid;\n            svlanMemConf.vs_priority    = pSvlan_cfg->priority;\n\n            /*for create check*/\n            if(0 == svlanMemConf.vs_efiden && 0 == svlanMemConf.vs_efid)\n                svlanMemConf.vs_efid = 1;\n\n            if ((retVal = rtl8367c_setAsicSvlanMemberConfiguration(empty_idx, &svlanMemConf)) != RT_ERR_OK)\n                return retVal;\n\n        }\n\n        return RT_ERR_OK;\n    }\n\n\n    empty_idx = 0xFF;\n\n    for (i = 0; i<= RTL8367C_SVIDXMAX; i++)\n    {\n        /*\n        if ((retVal = rtl8367c_getAsicSvlanMemberConfiguration(i, &svlanMemConf)) != RT_ERR_OK)\n            return retVal;\n        */\n        if (svid == svlan_mbrCfgVid[i] && TRUE == svlan_mbrCfgUsage[i])\n        {\n            svlanMemConf.vs_svid = svid;\n\n            if(rtk_switch_portmask_L2P_get(&(pSvlan_cfg->memberport), &phyMbrPmask) != RT_ERR_OK)\n                return RT_ERR_FAILED;\n\n            svlanMemConf.vs_member = phyMbrPmask;\n\n            if(rtk_switch_portmask_L2P_get(&(pSvlan_cfg->untagport), &phyMbrPmask) != RT_ERR_OK)\n                return RT_ERR_FAILED;\n\n            svlanMemConf.vs_untag = phyMbrPmask;\n\n            svlanMemConf.vs_force_fid   = pSvlan_cfg->fiden;\n            svlanMemConf.vs_fid_msti    = pSvlan_cfg->fid;\n            svlanMemConf.vs_priority    = pSvlan_cfg->priority;\n            svlanMemConf.vs_efiden      = pSvlan_cfg->efiden;\n            svlanMemConf.vs_efid        = pSvlan_cfg->efid;\n\n            /*all items are reset means deleting*/\n            if( 0 == svlanMemConf.vs_member &&\n                0 == svlanMemConf.vs_untag &&\n                0 == svlanMemConf.vs_force_fid &&\n                0 == svlanMemConf.vs_fid_msti &&\n                0 == svlanMemConf.vs_priority &&\n                0 == svlanMemConf.vs_efiden &&\n                0 == svlanMemConf.vs_efid)\n            {\n                svlan_mbrCfgUsage[i] = FALSE;\n                svlan_mbrCfgVid[i] = 0;\n\n                /* Clear SVID also */\n                svlanMemConf.vs_svid = 0;\n            }\n            else\n            {\n                svlan_mbrCfgUsage[i] = TRUE;\n                svlan_mbrCfgVid[i] = svlanMemConf.vs_svid;\n\n                if(0 == svlanMemConf.vs_svid)\n                {\n                    /*for create check*/\n                    if(0 == svlanMemConf.vs_efiden && 0 == svlanMemConf.vs_efid)\n                    {\n                        svlanMemConf.vs_efid = 1;\n                    }\n                }\n            }\n\n            if ((retVal = rtl8367c_setAsicSvlanMemberConfiguration(i, &svlanMemConf)) != RT_ERR_OK)\n                return retVal;\n\n            return RT_ERR_OK;\n        }\n        else if (FALSE == svlan_mbrCfgUsage[i] && 0xFF == empty_idx)\n        {\n            empty_idx = i;\n        }\n    }\n\n    if (empty_idx != 0xFF)\n    {\n        memset(&svlanMemConf, 0, sizeof(rtl8367c_svlan_memconf_t));\n        svlanMemConf.vs_svid = svid;\n\n        if(rtk_switch_portmask_L2P_get(&(pSvlan_cfg->memberport), &phyMbrPmask) != RT_ERR_OK)\n            return RT_ERR_FAILED;\n\n        svlanMemConf.vs_member = phyMbrPmask;\n\n        if(rtk_switch_portmask_L2P_get(&(pSvlan_cfg->untagport), &phyMbrPmask) != RT_ERR_OK)\n            return RT_ERR_FAILED;\n\n        svlanMemConf.vs_untag = phyMbrPmask;\n\n        svlanMemConf.vs_force_fid   = pSvlan_cfg->fiden;\n        svlanMemConf.vs_fid_msti    = pSvlan_cfg->fid;\n        svlanMemConf.vs_priority    = pSvlan_cfg->priority;\n\n        svlanMemConf.vs_efiden      = pSvlan_cfg->efiden;\n        svlanMemConf.vs_efid        = pSvlan_cfg->efid;\n\n        /*change efid for empty svid 0*/\n        if(0 == svlanMemConf.vs_svid)\n        {   /*for create check*/\n            if(0 == svlanMemConf.vs_efiden && 0 == svlanMemConf.vs_efid)\n            {\n                svlanMemConf.vs_efid = 1;\n            }\n        }\n\n        svlan_mbrCfgUsage[empty_idx] = TRUE;\n        svlan_mbrCfgVid[empty_idx] = svlanMemConf.vs_svid;\n\n        if ((retVal = rtl8367c_setAsicSvlanMemberConfiguration(empty_idx, &svlanMemConf)) != RT_ERR_OK)\n        {\n            return retVal;\n        }\n\n        return RT_ERR_OK;\n    }\n\n    return RT_ERR_SVLAN_TABLE_FULL;\n}\n\n/* Function Name:\n *      rtk_svlan_memberPortEntry_get\n * Description:\n *      Get SVLAN member Configure.\n * Input:\n *      svid - SVLAN id\n * Output:\n *      pSvlan_cfg - SVLAN member configuration\n * Return:\n *      RT_ERR_OK                       - OK\n *      RT_ERR_FAILED                   - Failed\n *      RT_ERR_SMI                      - SMI access error\n *      RT_ERR_SVLAN_ENTRY_NOT_FOUND    - specified svlan entry not found.\n *      RT_ERR_INPUT                    - Invalid input parameters.\n * Note:\n *      The API can get system 64 accepted s-tag frame format. Only 64 SVID S-tag frame will be accpeted\n *      to receiving from uplink ports. Other SVID S-tag frame or S-untagged frame will be droped.\n */\nrtk_api_ret_t rtk_svlan_memberPortEntry_get(rtk_vlan_t svid, rtk_svlan_memberCfg_t *pSvlan_cfg)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32 i;\n    rtl8367c_svlan_memconf_t svlanMemConf;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(NULL == pSvlan_cfg)\n        return RT_ERR_NULL_POINTER;\n\n    if (svid > RTL8367C_VIDMAX)\n        return RT_ERR_SVLAN_VID;\n\n\n    for (i = 0; i<= RTL8367C_SVIDXMAX; i++)\n    {\n        if ((retVal = rtl8367c_getAsicSvlanMemberConfiguration(i, &svlanMemConf)) != RT_ERR_OK)\n            return retVal;\n\n        if (svid == svlanMemConf.vs_svid)\n        {\n            pSvlan_cfg->svid        = svlanMemConf.vs_svid;\n\n            if(rtk_switch_portmask_P2L_get(svlanMemConf.vs_member,&(pSvlan_cfg->memberport)) != RT_ERR_OK)\n                return RT_ERR_FAILED;\n\n            if(rtk_switch_portmask_P2L_get(svlanMemConf.vs_untag,&(pSvlan_cfg->untagport)) != RT_ERR_OK)\n                return RT_ERR_FAILED;\n\n            pSvlan_cfg->fiden       = svlanMemConf.vs_force_fid;\n            pSvlan_cfg->fid         = svlanMemConf.vs_fid_msti;\n            pSvlan_cfg->priority    = svlanMemConf.vs_priority;\n            pSvlan_cfg->efiden      = svlanMemConf.vs_efiden;\n            pSvlan_cfg->efid        = svlanMemConf.vs_efid;\n\n            return RT_ERR_OK;\n        }\n    }\n\n    return RT_ERR_SVLAN_ENTRY_NOT_FOUND;\n\n}\n\n/* Function Name:\n *      rtk_svlan_memberPortEntry_adv_set\n * Description:\n *      Configure system SVLAN member by index\n * Input:\n *      idx         - Index (0 ~ 63)\n *      psvlan_cfg  - SVLAN member configuration\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - OK\n *      RT_ERR_FAILED           - Failed\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_INPUT            - Invalid input parameter.\n *      RT_ERR_SVLAN_VID        - Invalid SVLAN VID parameter.\n *      RT_ERR_PORT_MASK        - Invalid portmask.\n *      RT_ERR_SVLAN_TABLE_FULL - SVLAN configuration is full.\n * Note:\n *      The API can set system 64 accepted s-tag frame format by index.\n *      - rtk_svlan_memberCfg_t->svid is SVID of SVLAN member configuration.\n *      - rtk_svlan_memberCfg_t->memberport is member port mask of SVLAN member configuration.\n *      - rtk_svlan_memberCfg_t->fid is filtering database of SVLAN member configuration.\n *      - rtk_svlan_memberCfg_t->priority is priority of SVLAN member configuration.\n */\nrtk_api_ret_t rtk_svlan_memberPortEntry_adv_set(rtk_uint32 idx, rtk_svlan_memberCfg_t *pSvlan_cfg)\n{\n    rtk_api_ret_t retVal;\n    rtl8367c_svlan_memconf_t svlanMemConf;\n    rtk_uint32 phyMbrPmask;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(NULL == pSvlan_cfg)\n        return RT_ERR_NULL_POINTER;\n\n    if (idx > RTL8367C_SVIDXMAX)\n        return RT_ERR_SVLAN_ENTRY_INDEX;\n\n    if (pSvlan_cfg->svid>RTL8367C_VIDMAX)\n        return RT_ERR_SVLAN_VID;\n\n    RTK_CHK_PORTMASK_VALID(&(pSvlan_cfg->memberport));\n\n    RTK_CHK_PORTMASK_VALID(&(pSvlan_cfg->untagport));\n\n    if (pSvlan_cfg->fiden > ENABLED)\n        return RT_ERR_ENABLE;\n\n    if (pSvlan_cfg->fid > RTL8367C_FIDMAX)\n        return RT_ERR_L2_FID;\n\n    if (pSvlan_cfg->priority > RTL8367C_PRIMAX)\n        return RT_ERR_VLAN_PRIORITY;\n\n    if (pSvlan_cfg->efiden > ENABLED)\n        return RT_ERR_ENABLE;\n\n    if (pSvlan_cfg->efid > RTL8367C_EFIDMAX)\n        return RT_ERR_L2_FID;\n\n    memset(&svlanMemConf, 0, sizeof(rtl8367c_svlan_memconf_t));\n    svlanMemConf.vs_svid        = pSvlan_cfg->svid;\n    if(rtk_switch_portmask_L2P_get(&(pSvlan_cfg->memberport), &phyMbrPmask) != RT_ERR_OK)\n        return RT_ERR_FAILED;\n\n    svlanMemConf.vs_member = phyMbrPmask;\n\n    if(rtk_switch_portmask_L2P_get(&(pSvlan_cfg->untagport), &phyMbrPmask) != RT_ERR_OK)\n        return RT_ERR_FAILED;\n\n    svlanMemConf.vs_untag = phyMbrPmask;\n\n\n    svlanMemConf.vs_force_fid   = pSvlan_cfg->fiden;\n    svlanMemConf.vs_fid_msti    = pSvlan_cfg->fid;\n    svlanMemConf.vs_priority    = pSvlan_cfg->priority;\n    svlanMemConf.vs_efiden      = pSvlan_cfg->efiden;\n    svlanMemConf.vs_efid        = pSvlan_cfg->efid;\n\n    if(0 == svlanMemConf.vs_svid &&\n        0 == svlanMemConf.vs_member &&\n        0 == svlanMemConf.vs_untag &&\n        0 == svlanMemConf.vs_force_fid &&\n        0 == svlanMemConf.vs_fid_msti &&\n        0 == svlanMemConf.vs_priority &&\n        0 == svlanMemConf.vs_efiden &&\n        0 == svlanMemConf.vs_efid)\n    {\n        svlan_mbrCfgUsage[idx] = FALSE;\n        svlan_mbrCfgVid[idx] = 0;\n    }\n    else\n    {\n        svlan_mbrCfgUsage[idx] = TRUE;\n        svlan_mbrCfgVid[idx] = svlanMemConf.vs_svid;\n    }\n\n    if ((retVal = rtl8367c_setAsicSvlanMemberConfiguration(idx, &svlanMemConf)) != RT_ERR_OK)\n        return retVal;\n\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_svlan_memberPortEntry_adv_get\n * Description:\n *      Get SVLAN member Configure by index.\n * Input:\n *      idx         - Index (0 ~ 63)\n * Output:\n *      pSvlan_cfg  - SVLAN member configuration\n * Return:\n *      RT_ERR_OK                       - OK\n *      RT_ERR_FAILED                   - Failed\n *      RT_ERR_SMI                      - SMI access error\n *      RT_ERR_SVLAN_ENTRY_NOT_FOUND    - specified svlan entry not found.\n *      RT_ERR_INPUT                    - Invalid input parameters.\n * Note:\n *      The API can get system 64 accepted s-tag frame format. Only 64 SVID S-tag frame will be accpeted\n *      to receiving from uplink ports. Other SVID S-tag frame or S-untagged frame will be droped.\n */\nrtk_api_ret_t rtk_svlan_memberPortEntry_adv_get(rtk_uint32 idx, rtk_svlan_memberCfg_t *pSvlan_cfg)\n{\n    rtk_api_ret_t retVal;\n    rtl8367c_svlan_memconf_t svlanMemConf;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(NULL == pSvlan_cfg)\n        return RT_ERR_NULL_POINTER;\n\n    if (idx > RTL8367C_SVIDXMAX)\n        return RT_ERR_SVLAN_ENTRY_INDEX;\n\n    if ((retVal = rtl8367c_getAsicSvlanMemberConfiguration(idx, &svlanMemConf)) != RT_ERR_OK)\n        return retVal;\n\n    pSvlan_cfg->svid        = svlanMemConf.vs_svid;\n    if(rtk_switch_portmask_P2L_get(svlanMemConf.vs_member,&(pSvlan_cfg->memberport)) != RT_ERR_OK)\n        return RT_ERR_FAILED;\n\n    if(rtk_switch_portmask_P2L_get(svlanMemConf.vs_untag,&(pSvlan_cfg->untagport)) != RT_ERR_OK)\n        return RT_ERR_FAILED;\n\n    pSvlan_cfg->fiden       = svlanMemConf.vs_force_fid;\n    pSvlan_cfg->fid         = svlanMemConf.vs_fid_msti;\n    pSvlan_cfg->priority    = svlanMemConf.vs_priority;\n    pSvlan_cfg->efiden      = svlanMemConf.vs_efiden;\n    pSvlan_cfg->efid        = svlanMemConf.vs_efid;\n\n    return RT_ERR_OK;\n\n}\n\n/* Function Name:\n *      rtk_svlan_defaultSvlan_set\n * Description:\n *      Configure default egress SVLAN.\n * Input:\n *      port - Source port\n *      svid - SVLAN id\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK                       - OK\n *      RT_ERR_FAILED                   - Failed\n *      RT_ERR_SMI                      - SMI access error\n *      RT_ERR_INPUT                    - Invalid input parameter.\n *      RT_ERR_SVLAN_VID                - Invalid SVLAN VID parameter.\n *      RT_ERR_SVLAN_ENTRY_NOT_FOUND    - specified svlan entry not found.\n * Note:\n *      The API can set port n S-tag format index while receiving frame from port n\n *      is transmit through uplink port with s-tag field\n */\nrtk_api_ret_t rtk_svlan_defaultSvlan_set(rtk_port_t port, rtk_vlan_t svid)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32 i;\n    rtl8367c_svlan_memconf_t svlanMemConf;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check port Valid */\n    RTK_CHK_PORT_VALID(port);\n\n    /* svid must be 0~4095 */\n    if (svid > RTL8367C_VIDMAX)\n        return RT_ERR_SVLAN_VID;\n\n    for (i = 0; i < RTL8367C_SVIDXNO; i++)\n    {\n        if ((retVal = rtl8367c_getAsicSvlanMemberConfiguration(i, &svlanMemConf)) != RT_ERR_OK)\n            return retVal;\n\n        if (svid == svlanMemConf.vs_svid)\n        {\n            if ((retVal = rtl8367c_setAsicSvlanDefaultVlan(rtk_switch_port_L2P_get(port), i)) != RT_ERR_OK)\n                return retVal;\n\n            return RT_ERR_OK;\n        }\n    }\n\n    return RT_ERR_SVLAN_ENTRY_NOT_FOUND;\n}\n\n/* Function Name:\n *      rtk_svlan_defaultSvlan_get\n * Description:\n *      Get the configure default egress SVLAN.\n * Input:\n *      port - Source port\n * Output:\n *      pSvid - SVLAN VID\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n * Note:\n *      The API can get port n S-tag format index while receiving frame from port n\n *      is transmit through uplink port with s-tag field\n */\nrtk_api_ret_t rtk_svlan_defaultSvlan_get(rtk_port_t port, rtk_vlan_t *pSvid)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32 idx;\n    rtl8367c_svlan_memconf_t svlanMemConf;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(NULL == pSvid)\n        return RT_ERR_NULL_POINTER;\n\n    /* Check port Valid */\n    RTK_CHK_PORT_VALID(port);\n\n    if ((retVal = rtl8367c_getAsicSvlanDefaultVlan(rtk_switch_port_L2P_get(port), &idx)) != RT_ERR_OK)\n        return retVal;\n\n    if ((retVal = rtl8367c_getAsicSvlanMemberConfiguration(idx, &svlanMemConf)) != RT_ERR_OK)\n        return retVal;\n\n    *pSvid = svlanMemConf.vs_svid;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_svlan_c2s_add\n * Description:\n *      Configure SVLAN C2S table\n * Input:\n *      vid - VLAN ID\n *      src_port - Ingress Port\n *      svid - SVLAN VID\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port ID.\n *      RT_ERR_SVLAN_VID    - Invalid SVLAN VID parameter.\n *      RT_ERR_VLAN_VID     - Invalid VID parameter.\n *      RT_ERR_OUT_OF_RANGE - input out of range.\n *      RT_ERR_INPUT        - Invalid input parameters.\n * Note:\n *      The API can set system C2S configuration. ASIC will check upstream's VID and assign related\n *      SVID to mathed packet. There are 128 SVLAN C2S configurations.\n */\nrtk_api_ret_t rtk_svlan_c2s_add(rtk_vlan_t vid, rtk_port_t src_port, rtk_vlan_t svid)\n{\n    rtk_api_ret_t retVal, i;\n    rtk_uint32 empty_idx;\n    rtk_uint32 evid, pmsk, svidx, c2s_svidx;\n    rtl8367c_svlan_memconf_t svlanMemConf;\n    rtk_port_t phyPort;\n    rtk_uint16 doneFlag;\n\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n\n    if (vid > RTL8367C_VIDMAX)\n        return RT_ERR_VLAN_VID;\n\n    if (svid > RTL8367C_VIDMAX)\n        return RT_ERR_SVLAN_VID;\n\n    /* Check port Valid */\n    RTK_CHK_PORT_VALID(src_port);\n\n    phyPort = rtk_switch_port_L2P_get(src_port);\n\n    empty_idx = 0xFFFF;\n    svidx = 0xFFFF;\n    doneFlag = FALSE;\n\n    for (i = 0; i<= RTL8367C_SVIDXMAX; i++)\n    {\n        if ((retVal = rtl8367c_getAsicSvlanMemberConfiguration(i, &svlanMemConf)) != RT_ERR_OK)\n            return retVal;\n\n        if (svid == svlanMemConf.vs_svid)\n        {\n            svidx = i;\n            break;\n        }\n    }\n\n    if (0xFFFF == svidx)\n        return RT_ERR_SVLAN_VID;\n\n    for (i=RTL8367C_C2SIDXMAX; i>=0; i--)\n    {\n        if ((retVal = rtl8367c_getAsicSvlanC2SConf(i, &evid, &pmsk, &c2s_svidx)) != RT_ERR_OK)\n                return retVal;\n\n        if (evid == vid)\n        {\n            /* Check Src_port */\n            if(pmsk & (1 << phyPort))\n            {\n                /* Check SVIDX */\n                if(c2s_svidx == svidx)\n                {\n                    /* All the same, do nothing */\n                }\n                else\n                {\n                    /* New svidx, remove src_port and find a new slot to add a new enrty */\n                    pmsk = pmsk & ~(1 << phyPort);\n                    if(pmsk == 0)\n                        c2s_svidx = 0;\n\n                    if ((retVal = rtl8367c_setAsicSvlanC2SConf(i, vid, pmsk, c2s_svidx)) != RT_ERR_OK)\n                        return retVal;\n                }\n            }\n            else\n            {\n                if(c2s_svidx == svidx && doneFlag == FALSE)\n                {\n                    pmsk = pmsk | (1 << phyPort);\n                    if ((retVal = rtl8367c_setAsicSvlanC2SConf(i, vid, pmsk, svidx)) != RT_ERR_OK)\n                        return retVal;\n\n                    doneFlag = TRUE;\n                }\n            }\n        }\n        else if (evid==0&&pmsk==0)\n        {\n            empty_idx = i;\n        }\n    }\n\n    if (0xFFFF != empty_idx && doneFlag ==FALSE)\n    {\n       if ((retVal = rtl8367c_setAsicSvlanC2SConf(empty_idx, vid, (1<<phyPort), svidx)) != RT_ERR_OK)\n           return retVal;\n\n       return RT_ERR_OK;\n    }\n    else if(doneFlag == TRUE)\n    {\n        return RT_ERR_OK;\n    }\n\n    return RT_ERR_OUT_OF_RANGE;\n}\n\n/* Function Name:\n *      rtk_svlan_c2s_del\n * Description:\n *      Delete one C2S entry\n * Input:\n *      vid - VLAN ID\n *      src_port - Ingress Port\n *      svid - SVLAN VID\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - OK\n *      RT_ERR_FAILED           - Failed\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_VLAN_VID         - Invalid VID parameter.\n *      RT_ERR_PORT_ID          - Invalid port ID.\n *      RT_ERR_OUT_OF_RANGE     - input out of range.\n * Note:\n *      The API can delete system C2S configuration. There are 128 SVLAN C2S configurations.\n */\nrtk_api_ret_t rtk_svlan_c2s_del(rtk_vlan_t vid, rtk_port_t src_port)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32 i;\n    rtk_uint32 evid, pmsk, svidx;\n    rtk_port_t phyPort;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if (vid > RTL8367C_EVIDMAX)\n        return RT_ERR_VLAN_VID;\n\n    /* Check port Valid */\n    RTK_CHK_PORT_VALID(src_port);\n    phyPort = rtk_switch_port_L2P_get(src_port);\n\n    for (i = 0; i <= RTL8367C_C2SIDXMAX; i++)\n    {\n        if ((retVal = rtl8367c_getAsicSvlanC2SConf(i, &evid, &pmsk, &svidx)) != RT_ERR_OK)\n            return retVal;\n\n        if (evid == vid)\n        {\n            if(pmsk & (1 << phyPort))\n            {\n                pmsk = pmsk & ~(1 << phyPort);\n                if(pmsk == 0)\n                {\n                    vid = 0;\n                    svidx = 0;\n                }\n\n                if ((retVal = rtl8367c_setAsicSvlanC2SConf(i, vid, pmsk, svidx)) != RT_ERR_OK)\n                    return retVal;\n\n                return RT_ERR_OK;\n            }\n        }\n    }\n\n    return RT_ERR_OUT_OF_RANGE;\n}\n\n/* Function Name:\n *      rtk_svlan_c2s_get\n * Description:\n *      Get configure SVLAN C2S table\n * Input:\n *      vid - VLAN ID\n *      src_port - Ingress Port\n * Output:\n *      pSvid - SVLAN ID\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n *      RT_ERR_PORT_ID      - Invalid port ID.\n *      RT_ERR_OUT_OF_RANGE - input out of range.\n * Note:\n *     The API can get system C2S configuration. There are 128 SVLAN C2S configurations.\n */\nrtk_api_ret_t rtk_svlan_c2s_get(rtk_vlan_t vid, rtk_port_t src_port, rtk_vlan_t *pSvid)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32 i;\n    rtk_uint32 evid, pmsk, svidx;\n    rtl8367c_svlan_memconf_t svlanMemConf;\n    rtk_port_t phyPort;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(NULL == pSvid)\n        return RT_ERR_NULL_POINTER;\n\n    if (vid > RTL8367C_VIDMAX)\n        return RT_ERR_VLAN_VID;\n\n    /* Check port Valid */\n    RTK_CHK_PORT_VALID(src_port);\n    phyPort = rtk_switch_port_L2P_get(src_port);\n\n    for (i = 0; i <= RTL8367C_C2SIDXMAX; i++)\n    {\n        if ((retVal = rtl8367c_getAsicSvlanC2SConf(i, &evid, &pmsk, &svidx)) != RT_ERR_OK)\n            return retVal;\n\n        if (evid == vid)\n        {\n            if(pmsk & (1 << phyPort))\n            {\n                if ((retVal = rtl8367c_getAsicSvlanMemberConfiguration(svidx, &svlanMemConf)) != RT_ERR_OK)\n                    return retVal;\n\n                *pSvid = svlanMemConf.vs_svid;\n                return RT_ERR_OK;\n            }\n        }\n    }\n\n    return RT_ERR_OUT_OF_RANGE;\n}\n\n/* Function Name:\n *      rtk_svlan_untag_action_set\n * Description:\n *      Configure Action of downstream UnStag packet\n * Input:\n *      action  - Action for UnStag\n *      svid    - The SVID assigned to UnStag packet\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK                       - OK\n *      RT_ERR_FAILED                   - Failed\n *      RT_ERR_SMI                      - SMI access error\n *      RT_ERR_SVLAN_VID                - Invalid SVLAN VID parameter.\n *      RT_ERR_SVLAN_ENTRY_NOT_FOUND    - specified svlan entry not found.\n *      RT_ERR_OUT_OF_RANGE             - input out of range.\n *      RT_ERR_INPUT                    - Invalid input parameters.\n * Note:\n *      The API can configure action of downstream Un-Stag packet. A SVID assigned\n *      to the un-stag is also supported by this API. The parameter of svid is\n *      only referenced when the action is set to UNTAG_ASSIGN\n */\nrtk_api_ret_t rtk_svlan_untag_action_set(rtk_svlan_untag_action_t action, rtk_vlan_t svid)\n{\n    rtk_api_ret_t   retVal;\n    rtk_uint32      i;\n    rtl8367c_svlan_memconf_t svlanMemConf;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if (action >= UNTAG_END)\n        return RT_ERR_OUT_OF_RANGE;\n\n    if(action == UNTAG_ASSIGN)\n    {\n        if (svid > RTL8367C_VIDMAX)\n            return RT_ERR_SVLAN_VID;\n    }\n\n    if ((retVal = rtl8367c_setAsicSvlanIngressUntag((rtk_uint32)action)) != RT_ERR_OK)\n        return retVal;\n\n    if(action == UNTAG_ASSIGN)\n    {\n        for (i = 0; i < RTL8367C_SVIDXNO; i++)\n        {\n            if ((retVal = rtl8367c_getAsicSvlanMemberConfiguration(i, &svlanMemConf)) != RT_ERR_OK)\n                return retVal;\n\n            if (svid == svlanMemConf.vs_svid)\n            {\n                if ((retVal = rtl8367c_setAsicSvlanUntagVlan(i)) != RT_ERR_OK)\n                    return retVal;\n\n                return RT_ERR_OK;\n            }\n        }\n\n        return RT_ERR_SVLAN_ENTRY_NOT_FOUND;\n    }\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_svlan_untag_action_get\n * Description:\n *      Get Action of downstream UnStag packet\n * Input:\n *      None\n * Output:\n *      pAction  - Action for UnStag\n *      pSvid    - The SVID assigned to UnStag packet\n * Return:\n *      RT_ERR_OK                       - OK\n *      RT_ERR_FAILED                   - Failed\n *      RT_ERR_SMI                      - SMI access error\n *      RT_ERR_SVLAN_VID                - Invalid SVLAN VID parameter.\n *      RT_ERR_SVLAN_ENTRY_NOT_FOUND    - specified svlan entry not found.\n *      RT_ERR_OUT_OF_RANGE             - input out of range.\n *      RT_ERR_INPUT                    - Invalid input parameters.\n * Note:\n *      The API can Get action of downstream Un-Stag packet. A SVID assigned\n *      to the un-stag is also retrieved by this API. The parameter pSvid is\n *      only refernced when the action is UNTAG_ASSIGN\n */\nrtk_api_ret_t rtk_svlan_untag_action_get(rtk_svlan_untag_action_t *pAction, rtk_vlan_t *pSvid)\n{\n    rtk_api_ret_t   retVal;\n    rtk_uint32      svidx;\n    rtl8367c_svlan_memconf_t svlanMemConf;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(NULL == pAction || NULL == pSvid)\n        return RT_ERR_NULL_POINTER;\n\n    if ((retVal = rtl8367c_getAsicSvlanIngressUntag(pAction)) != RT_ERR_OK)\n        return retVal;\n\n    if(*pAction == UNTAG_ASSIGN)\n    {\n        if ((retVal = rtl8367c_getAsicSvlanUntagVlan(&svidx)) != RT_ERR_OK)\n            return retVal;\n\n        if ((retVal = rtl8367c_getAsicSvlanMemberConfiguration(svidx, &svlanMemConf)) != RT_ERR_OK)\n            return retVal;\n\n        *pSvid = svlanMemConf.vs_svid;\n    }\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_svlan_unmatch_action_set\n * Description:\n *      Configure Action of downstream Unmatch packet\n * Input:\n *      action  - Action for Unmatch\n *      svid    - The SVID assigned to Unmatch packet\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK                       - OK\n *      RT_ERR_FAILED                   - Failed\n *      RT_ERR_SMI                      - SMI access error\n *      RT_ERR_SVLAN_VID                - Invalid SVLAN VID parameter.\n *      RT_ERR_SVLAN_ENTRY_NOT_FOUND    - specified svlan entry not found.\n *      RT_ERR_OUT_OF_RANGE             - input out of range.\n *      RT_ERR_INPUT                    - Invalid input parameters.\n * Note:\n *      The API can configure action of downstream Un-match packet. A SVID assigned\n *      to the un-match is also supported by this API. The parameter od svid is\n *      only refernced when the action is set to UNMATCH_ASSIGN\n */\nrtk_api_ret_t rtk_svlan_unmatch_action_set(rtk_svlan_unmatch_action_t action, rtk_vlan_t svid)\n{\n    rtk_api_ret_t   retVal;\n    rtk_uint32      i;\n    rtl8367c_svlan_memconf_t svlanMemConf;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if (action >= UNMATCH_END)\n        return RT_ERR_OUT_OF_RANGE;\n\n    if (action == UNMATCH_ASSIGN)\n    {\n        if (svid > RTL8367C_VIDMAX)\n            return RT_ERR_SVLAN_VID;\n    }\n\n    if ((retVal = rtl8367c_setAsicSvlanIngressUnmatch((rtk_uint32)action)) != RT_ERR_OK)\n        return retVal;\n\n    if(action == UNMATCH_ASSIGN)\n    {\n        for (i = 0; i < RTL8367C_SVIDXNO; i++)\n        {\n            if ((retVal = rtl8367c_getAsicSvlanMemberConfiguration(i, &svlanMemConf)) != RT_ERR_OK)\n                return retVal;\n\n            if (svid == svlanMemConf.vs_svid)\n            {\n                if ((retVal = rtl8367c_setAsicSvlanUnmatchVlan(i)) != RT_ERR_OK)\n                    return retVal;\n\n                return RT_ERR_OK;\n            }\n        }\n\n        return RT_ERR_SVLAN_ENTRY_NOT_FOUND;\n    }\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_svlan_unmatch_action_get\n * Description:\n *      Get Action of downstream Unmatch packet\n * Input:\n *      None\n * Output:\n *      pAction  - Action for Unmatch\n *      pSvid    - The SVID assigned to Unmatch packet\n * Return:\n *      RT_ERR_OK                       - OK\n *      RT_ERR_FAILED                   - Failed\n *      RT_ERR_SMI                      - SMI access error\n *      RT_ERR_SVLAN_VID                - Invalid SVLAN VID parameter.\n *      RT_ERR_SVLAN_ENTRY_NOT_FOUND    - specified svlan entry not found.\n *      RT_ERR_OUT_OF_RANGE             - input out of range.\n *      RT_ERR_INPUT                    - Invalid input parameters.\n * Note:\n *      The API can Get action of downstream Un-match packet. A SVID assigned\n *      to the un-match is also retrieved by this API. The parameter pSvid is\n *      only refernced when the action is UNMATCH_ASSIGN\n */\nrtk_api_ret_t rtk_svlan_unmatch_action_get(rtk_svlan_unmatch_action_t *pAction, rtk_vlan_t *pSvid)\n{\n    rtk_api_ret_t   retVal;\n    rtk_uint32      svidx;\n    rtl8367c_svlan_memconf_t svlanMemConf;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(NULL == pAction || NULL == pSvid)\n        return RT_ERR_NULL_POINTER;\n\n    if ((retVal = rtl8367c_getAsicSvlanIngressUnmatch(pAction)) != RT_ERR_OK)\n        return retVal;\n\n    if(*pAction == UNMATCH_ASSIGN)\n    {\n        if ((retVal = rtl8367c_getAsicSvlanUnmatchVlan(&svidx)) != RT_ERR_OK)\n            return retVal;\n\n        if ((retVal = rtl8367c_getAsicSvlanMemberConfiguration(svidx, &svlanMemConf)) != RT_ERR_OK)\n            return retVal;\n\n        *pSvid = svlanMemConf.vs_svid;\n    }\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_svlan_unassign_action_set\n * Description:\n *      Configure Action of upstream without svid assign action\n * Input:\n *      action  - Action for Un-assign\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK                       - OK\n *      RT_ERR_FAILED                   - Failed\n *      RT_ERR_OUT_OF_RANGE             - input out of range.\n *      RT_ERR_INPUT                    - Invalid input parameters.\n * Note:\n *      The API can configure action of upstream Un-assign svid packet. If action is not\n *      trap to CPU, the port-based SVID sure be assign as system need\n */\nrtk_api_ret_t rtk_svlan_unassign_action_set(rtk_svlan_unassign_action_t action)\n{\n    rtk_api_ret_t   retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if (action >= UNASSIGN_END)\n        return RT_ERR_OUT_OF_RANGE;\n\n    retVal = rtl8367c_setAsicSvlanEgressUnassign((rtk_uint32)action);\n\n    return retVal;\n}\n\n/* Function Name:\n *      rtk_svlan_unassign_action_get\n * Description:\n *      Get action of upstream without svid assignment\n * Input:\n *      None\n * Output:\n *      pAction  - Action for Un-assign\n * Return:\n *      RT_ERR_OK                       - OK\n *      RT_ERR_FAILED                   - Failed\n * Note:\n *      None\n */\nrtk_api_ret_t rtk_svlan_unassign_action_get(rtk_svlan_unassign_action_t *pAction)\n{\n    rtk_api_ret_t   retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(NULL == pAction)\n        return RT_ERR_NULL_POINTER;\n\n    retVal = rtl8367c_getAsicSvlanEgressUnassign(pAction);\n\n    return retVal;\n}\n\n/* Function Name:\n *      rtk_svlan_dmac_vidsel_set\n * Description:\n *      Set DMAC CVID selection\n * Input:\n *      port    - Port\n *      enable  - state of DMAC CVID Selection\n * Output:\n *      None.\n * Return:\n *      RT_ERR_OK                       - OK\n *      RT_ERR_FAILED                   - Failed\n *      RT_ERR_SMI                      - SMI access error\n *      RT_ERR_SVLAN_VID                - Invalid SVLAN VID parameter.\n *      RT_ERR_SVLAN_ENTRY_NOT_FOUND    - specified svlan entry not found.\n *      RT_ERR_OUT_OF_RANGE             - input out of range.\n *      RT_ERR_INPUT                    - Invalid input parameters.\n * Note:\n *      This API can set DMAC CVID Selection state\n */\nrtk_api_ret_t rtk_svlan_dmac_vidsel_set(rtk_port_t port, rtk_enable_t enable)\n{\n    rtk_api_ret_t   retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check port Valid */\n    RTK_CHK_PORT_VALID(port);\n\n    if (enable >= RTK_ENABLE_END)\n        return RT_ERR_ENABLE;\n\n    if ((retVal = rtl8367c_setAsicSvlanDmacCvidSel(rtk_switch_port_L2P_get(port), enable)) != RT_ERR_OK)\n            return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_svlan_dmac_vidsel_get\n * Description:\n *      Get DMAC CVID selection\n * Input:\n *      port    - Port\n * Output:\n *      pEnable - state of DMAC CVID Selection\n * Return:\n *      RT_ERR_OK                       - OK\n *      RT_ERR_FAILED                   - Failed\n *      RT_ERR_SMI                      - SMI access error\n *      RT_ERR_SVLAN_VID                - Invalid SVLAN VID parameter.\n *      RT_ERR_SVLAN_ENTRY_NOT_FOUND    - specified svlan entry not found.\n *      RT_ERR_OUT_OF_RANGE             - input out of range.\n *      RT_ERR_INPUT                    - Invalid input parameters.\n * Note:\n *      This API can get DMAC CVID Selection state\n */\nrtk_api_ret_t rtk_svlan_dmac_vidsel_get(rtk_port_t port, rtk_enable_t *pEnable)\n{\n    rtk_api_ret_t   retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(NULL == pEnable)\n        return RT_ERR_NULL_POINTER;\n\n    /* Check port Valid */\n    RTK_CHK_PORT_VALID(port);\n\n    if ((retVal = rtl8367c_getAsicSvlanDmacCvidSel(rtk_switch_port_L2P_get(port), pEnable)) != RT_ERR_OK)\n            return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_svlan_ipmc2s_add\n * Description:\n *      add ip multicast address to SVLAN\n * Input:\n *      svid    - SVLAN VID\n *      ipmc    - ip multicast address\n *      ipmcMsk - ip multicast mask\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK                       - OK\n *      RT_ERR_FAILED                   - Failed\n *      RT_ERR_SMI                      - SMI access error\n *      RT_ERR_SVLAN_VID                - Invalid SVLAN VID parameter.\n *      RT_ERR_SVLAN_ENTRY_NOT_FOUND    - specified svlan entry not found.\n *      RT_ERR_OUT_OF_RANGE             - input out of range.\n *      RT_ERR_INPUT                    - Invalid input parameters.\n * Note:\n *      The API can set IP mutlicast to SVID configuration. If upstream packet is IPv4 multicast\n *      packet and DIP is matched MC2S configuration, ASIC will assign egress SVID to the packet.\n *      There are 32 SVLAN multicast configurations for IP and L2 multicast.\n */\nrtk_api_ret_t rtk_svlan_ipmc2s_add(ipaddr_t ipmc, ipaddr_t ipmcMsk,rtk_vlan_t svid)\n{\n    rtk_api_ret_t retVal, i;\n    rtk_uint32 empty_idx;\n    rtk_uint32 svidx;\n    rtl8367c_svlan_memconf_t svlanMemConf;\n    rtl8367c_svlan_mc2s_t svlanMC2SConf;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if (svid > RTL8367C_VIDMAX)\n        return RT_ERR_SVLAN_VID;\n\n    if ((ipmc&0xF0000000)!=0xE0000000)\n        return RT_ERR_INPUT;\n\n    svidx = 0xFFFF;\n\n    for (i = 0; i < RTL8367C_SVIDXNO; i++)\n    {\n        if ((retVal = rtl8367c_getAsicSvlanMemberConfiguration(i, &svlanMemConf)) != RT_ERR_OK)\n            return retVal;\n\n        if (svid == svlanMemConf.vs_svid)\n        {\n            svidx = i;\n            break;\n        }\n    }\n\n    if (0xFFFF == svidx)\n            return RT_ERR_SVLAN_ENTRY_NOT_FOUND;\n\n\n    empty_idx = 0xFFFF;\n\n    for (i = RTL8367C_MC2SIDXMAX; i >= 0; i--)\n    {\n        if ((retVal = rtl8367c_getAsicSvlanMC2SConf(i, &svlanMC2SConf)) != RT_ERR_OK)\n            return retVal;\n\n        if (TRUE == svlanMC2SConf.valid)\n        {\n            if (svlanMC2SConf.format == SVLAN_MC2S_MODE_IP &&\n                svlanMC2SConf.sdata==ipmc&&\n                svlanMC2SConf.smask==ipmcMsk)\n            {\n                svlanMC2SConf.svidx = svidx;\n                if ((retVal = rtl8367c_setAsicSvlanMC2SConf(i, &svlanMC2SConf)) != RT_ERR_OK)\n                    return retVal;\n            }\n        }\n        else\n        {\n            empty_idx = i;\n        }\n    }\n\n    if (empty_idx!=0xFFFF)\n    {\n        svlanMC2SConf.valid = TRUE;\n        svlanMC2SConf.svidx = svidx;\n        svlanMC2SConf.format = SVLAN_MC2S_MODE_IP;\n        svlanMC2SConf.sdata = ipmc;\n        svlanMC2SConf.smask = ipmcMsk;\n        if ((retVal = rtl8367c_setAsicSvlanMC2SConf(empty_idx, &svlanMC2SConf)) != RT_ERR_OK)\n            return retVal;\n        return RT_ERR_OK;\n    }\n\n    return RT_ERR_OUT_OF_RANGE;\n\n}\n\n/* Function Name:\n *      rtk_svlan_ipmc2s_del\n * Description:\n *      delete ip multicast address to SVLAN\n * Input:\n *      ipmc    - ip multicast address\n *      ipmcMsk - ip multicast mask\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - OK\n *      RT_ERR_FAILED           - Failed\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_SVLAN_VID        - Invalid SVLAN VID parameter.\n *      RT_ERR_OUT_OF_RANGE     - input out of range.\n * Note:\n *      The API can delete IP mutlicast to SVID configuration. There are 32 SVLAN multicast configurations for IP and L2 multicast.\n */\nrtk_api_ret_t rtk_svlan_ipmc2s_del(ipaddr_t ipmc, ipaddr_t ipmcMsk)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32 i;\n    rtl8367c_svlan_mc2s_t svlanMC2SConf;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if ((ipmc&0xF0000000)!=0xE0000000)\n        return RT_ERR_INPUT;\n\n    for (i = 0; i <= RTL8367C_MC2SIDXMAX; i++)\n    {\n        if ((retVal = rtl8367c_getAsicSvlanMC2SConf(i, &svlanMC2SConf)) != RT_ERR_OK)\n            return retVal;\n\n        if (TRUE == svlanMC2SConf.valid)\n        {\n            if (svlanMC2SConf.format == SVLAN_MC2S_MODE_IP &&\n                svlanMC2SConf.sdata==ipmc&&\n                svlanMC2SConf.smask==ipmcMsk)\n            {\n                memset(&svlanMC2SConf, 0, sizeof(rtl8367c_svlan_mc2s_t));\n                if ((retVal = rtl8367c_setAsicSvlanMC2SConf(i, &svlanMC2SConf)) != RT_ERR_OK)\n                    return retVal;\n                return RT_ERR_OK;\n            }\n        }\n    }\n\n    return RT_ERR_OUT_OF_RANGE;\n}\n\n/* Function Name:\n *      rtk_svlan_ipmc2s_get\n * Description:\n *      Get ip multicast address to SVLAN\n * Input:\n *      ipmc    - ip multicast address\n *      ipmcMsk - ip multicast mask\n * Output:\n *      pSvid - SVLAN VID\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n *      RT_ERR_OUT_OF_RANGE - input out of range.\n * Note:\n *      The API can get IP mutlicast to SVID configuration. There are 32 SVLAN multicast configurations for IP and L2 multicast.\n */\nrtk_api_ret_t rtk_svlan_ipmc2s_get(ipaddr_t ipmc, ipaddr_t ipmcMsk, rtk_vlan_t *pSvid)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32 i;\n    rtl8367c_svlan_memconf_t svlanMemConf;\n    rtl8367c_svlan_mc2s_t svlanMC2SConf;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(NULL == pSvid)\n        return RT_ERR_NULL_POINTER;\n\n    if ((ipmc&0xF0000000)!=0xE0000000)\n        return RT_ERR_INPUT;\n\n    for (i = 0; i <= RTL8367C_MC2SIDXMAX; i++)\n    {\n        if ((retVal = rtl8367c_getAsicSvlanMC2SConf(i, &svlanMC2SConf)) != RT_ERR_OK)\n            return retVal;\n\n        if (TRUE == svlanMC2SConf.valid &&\n            svlanMC2SConf.format == SVLAN_MC2S_MODE_IP &&\n            svlanMC2SConf.sdata == ipmc &&\n            svlanMC2SConf.smask == ipmcMsk)\n        {\n            if ((retVal = rtl8367c_getAsicSvlanMemberConfiguration(svlanMC2SConf.svidx, &svlanMemConf)) != RT_ERR_OK)\n                return retVal;\n            *pSvid = svlanMemConf.vs_svid;\n            return RT_ERR_OK;\n        }\n    }\n\n    return RT_ERR_OUT_OF_RANGE;\n}\n\n/* Function Name:\n *      rtk_svlan_l2mc2s_add\n * Description:\n *      Add L2 multicast address to SVLAN\n * Input:\n *      mac     - L2 multicast address\n *      macMsk  - L2 multicast address mask\n *      svid    - SVLAN VID\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK                       - OK\n *      RT_ERR_FAILED                   - Failed\n *      RT_ERR_SMI                      - SMI access error\n *      RT_ERR_SVLAN_VID                - Invalid SVLAN VID parameter.\n *      RT_ERR_SVLAN_ENTRY_NOT_FOUND    - specified svlan entry not found.\n *      RT_ERR_OUT_OF_RANGE             - input out of range.\n *      RT_ERR_INPUT                    - Invalid input parameters.\n * Note:\n *      The API can set L2 Mutlicast to SVID configuration. If upstream packet is L2 multicast\n *      packet and DMAC is matched, ASIC will assign egress SVID to the packet. There are 32\n *      SVLAN multicast configurations for IP and L2 multicast.\n */\nrtk_api_ret_t rtk_svlan_l2mc2s_add(rtk_mac_t mac, rtk_mac_t macMsk, rtk_vlan_t svid)\n{\n    rtk_api_ret_t retVal, i;\n    rtk_uint32 empty_idx;\n    rtk_uint32 svidx, l2add, l2Mask;\n    rtl8367c_svlan_memconf_t svlanMemConf;\n    rtl8367c_svlan_mc2s_t svlanMC2SConf;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if (svid > RTL8367C_VIDMAX)\n        return RT_ERR_SVLAN_VID;\n\n    if (mac.octet[0]!= 1&&mac.octet[1]!=0)\n        return RT_ERR_INPUT;\n\n    l2add = (mac.octet[2] << 24) | (mac.octet[3] << 16) | (mac.octet[4] << 8) | mac.octet[5];\n    l2Mask = (macMsk.octet[2] << 24) | (macMsk.octet[3] << 16) | (macMsk.octet[4] << 8) | macMsk.octet[5];\n\n    svidx = 0xFFFF;\n\n    for (i = 0; i < RTL8367C_SVIDXNO; i++)\n    {\n        if ((retVal = rtl8367c_getAsicSvlanMemberConfiguration(i, &svlanMemConf)) != RT_ERR_OK)\n            return retVal;\n\n        if (svid == svlanMemConf.vs_svid)\n        {\n            svidx = i;\n            break;\n        }\n    }\n\n    if (0xFFFF == svidx)\n        return RT_ERR_SVLAN_ENTRY_NOT_FOUND;\n\n    empty_idx = 0xFFFF;\n\n    for (i = RTL8367C_MC2SIDXMAX; i >=0; i--)\n    {\n        if ((retVal = rtl8367c_getAsicSvlanMC2SConf(i, &svlanMC2SConf)) != RT_ERR_OK)\n            return retVal;\n\n        if (TRUE == svlanMC2SConf.valid)\n        {\n            if (svlanMC2SConf.format == SVLAN_MC2S_MODE_MAC &&\n                svlanMC2SConf.sdata==l2add&&\n                svlanMC2SConf.smask==l2Mask)\n            {\n                svlanMC2SConf.svidx = svidx;\n                if ((retVal = rtl8367c_setAsicSvlanMC2SConf(i, &svlanMC2SConf)) != RT_ERR_OK)\n                    return retVal;\n            }\n        }\n        else\n        {\n            empty_idx = i;\n        }\n    }\n\n    if (empty_idx!=0xFFFF)\n    {\n        svlanMC2SConf.valid = TRUE;\n        svlanMC2SConf.svidx = svidx;\n        svlanMC2SConf.format = SVLAN_MC2S_MODE_MAC;\n        svlanMC2SConf.sdata = l2add;\n        svlanMC2SConf.smask = l2Mask;\n\n        if ((retVal = rtl8367c_setAsicSvlanMC2SConf(empty_idx, &svlanMC2SConf)) != RT_ERR_OK)\n            return retVal;\n        return RT_ERR_OK;\n    }\n\n    return RT_ERR_OUT_OF_RANGE;\n}\n\n/* Function Name:\n *      rtk_svlan_l2mc2s_del\n * Description:\n *      delete L2 multicast address to SVLAN\n * Input:\n *      mac     - L2 multicast address\n *      macMsk  - L2 multicast address mask\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - OK\n *      RT_ERR_FAILED           - Failed\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_SVLAN_VID        - Invalid SVLAN VID parameter.\n *      RT_ERR_OUT_OF_RANGE     - input out of range.\n * Note:\n *      The API can delete Mutlicast to SVID configuration. There are 32 SVLAN multicast configurations for IP and L2 multicast.\n */\nrtk_api_ret_t rtk_svlan_l2mc2s_del(rtk_mac_t mac, rtk_mac_t macMsk)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32 i;\n    rtk_uint32 l2add, l2Mask;\n    rtl8367c_svlan_mc2s_t svlanMC2SConf;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if (mac.octet[0]!= 1&&mac.octet[1]!=0)\n        return RT_ERR_INPUT;\n\n    l2add = (mac.octet[2] << 24) | (mac.octet[3] << 16) | (mac.octet[4] << 8) | mac.octet[5];\n    l2Mask = (macMsk.octet[2] << 24) | (macMsk.octet[3] << 16) | (macMsk.octet[4] << 8) | macMsk.octet[5];\n\n    for (i = 0; i <= RTL8367C_MC2SIDXMAX; i++)\n    {\n        if ((retVal = rtl8367c_getAsicSvlanMC2SConf(i, &svlanMC2SConf)) != RT_ERR_OK)\n            return retVal;\n\n        if (TRUE == svlanMC2SConf.valid)\n        {\n            if (svlanMC2SConf.format == SVLAN_MC2S_MODE_MAC &&\n                svlanMC2SConf.sdata==l2add&&\n                svlanMC2SConf.smask==l2Mask)\n            {\n                memset(&svlanMC2SConf, 0, sizeof(rtl8367c_svlan_mc2s_t));\n                if ((retVal = rtl8367c_setAsicSvlanMC2SConf(i, &svlanMC2SConf)) != RT_ERR_OK)\n                    return retVal;\n                return RT_ERR_OK;\n            }\n        }\n    }\n\n    return RT_ERR_OUT_OF_RANGE;\n}\n\n/* Function Name:\n *      rtk_svlan_l2mc2s_get\n * Description:\n *      Get L2 multicast address to SVLAN\n * Input:\n *      mac     - L2 multicast address\n *      macMsk  - L2 multicast address mask\n * Output:\n *      pSvid - SVLAN VID\n * Return:\n *      RT_ERR_OK               - OK\n *      RT_ERR_FAILED           - Failed\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_INPUT            - Invalid input parameters.\n *      RT_ERR_OUT_OF_RANGE     - input out of range.\n * Note:\n *      The API can get L2 mutlicast to SVID configuration. There are 32 SVLAN multicast configurations for IP and L2 multicast.\n */\nrtk_api_ret_t rtk_svlan_l2mc2s_get(rtk_mac_t mac, rtk_mac_t macMsk, rtk_vlan_t *pSvid)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32 i;\n    rtk_uint32 l2add,l2Mask;\n    rtl8367c_svlan_memconf_t svlanMemConf;\n    rtl8367c_svlan_mc2s_t svlanMC2SConf;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(NULL == pSvid)\n        return RT_ERR_NULL_POINTER;\n\n    if (mac.octet[0]!= 1&&mac.octet[1]!=0)\n        return RT_ERR_INPUT;\n\n    l2add = (mac.octet[2] << 24) | (mac.octet[3] << 16) | (mac.octet[4] << 8) | mac.octet[5];\n    l2Mask = (macMsk.octet[2] << 24) | (macMsk.octet[3] << 16) | (macMsk.octet[4] << 8) | macMsk.octet[5];\n\n    for (i = 0; i <= RTL8367C_MC2SIDXMAX; i++)\n    {\n        if ((retVal = rtl8367c_getAsicSvlanMC2SConf(i, &svlanMC2SConf)) != RT_ERR_OK)\n            return retVal;\n\n        if (TRUE == svlanMC2SConf.valid)\n        {\n            if (svlanMC2SConf.format == SVLAN_MC2S_MODE_MAC &&\n                svlanMC2SConf.sdata==l2add&&\n                svlanMC2SConf.smask==l2Mask)\n            {\n                if ((retVal = rtl8367c_getAsicSvlanMemberConfiguration(svlanMC2SConf.svidx, &svlanMemConf)) != RT_ERR_OK)\n                    return retVal;\n                *pSvid = svlanMemConf.vs_svid;\n\n                return RT_ERR_OK;\n            }\n        }\n    }\n\n    return RT_ERR_OUT_OF_RANGE;\n}\n\n/* Function Name:\n *      rtk_svlan_sp2c_add\n * Description:\n *      Add system SP2C configuration\n * Input:\n *      cvid        - VLAN ID\n *      dst_port    - Destination port of SVLAN to CVLAN configuration\n *      svid        - SVLAN VID\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number.\n *      RT_ERR_SVLAN_VID    - Invalid SVLAN VID parameter.\n *      RT_ERR_VLAN_VID     - Invalid VID parameter.\n *      RT_ERR_OUT_OF_RANGE - input out of range.\n *      RT_ERR_INPUT        - Invalid input parameters.\n * Note:\n *      The API can add SVID & Destination Port to CVLAN configuration. The downstream frames with assigned\n *      SVID will be add C-tag with assigned CVID if the output port is the assigned destination port.\n *      There are 128 SP2C configurations.\n */\nrtk_api_ret_t rtk_svlan_sp2c_add(rtk_vlan_t svid, rtk_port_t dst_port, rtk_vlan_t cvid)\n{\n    rtk_api_ret_t retVal, i;\n    rtk_uint32 empty_idx, svidx;\n    rtl8367c_svlan_memconf_t svlanMemConf;\n    rtl8367c_svlan_s2c_t svlanSP2CConf;\n    rtk_port_t port;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if (svid > RTL8367C_VIDMAX)\n        return RT_ERR_SVLAN_VID;\n\n    if (cvid > RTL8367C_VIDMAX)\n        return RT_ERR_VLAN_VID;\n\n    /* Check port Valid */\n    RTK_CHK_PORT_VALID(dst_port);\n    port = rtk_switch_port_L2P_get(dst_port);\n\n    svidx = 0xFFFF;\n\n    for (i = 0; i < RTL8367C_SVIDXNO; i++)\n    {\n        if ((retVal = rtl8367c_getAsicSvlanMemberConfiguration(i, &svlanMemConf)) != RT_ERR_OK)\n            return retVal;\n\n        if (svid == svlanMemConf.vs_svid)\n        {\n            svidx = i;\n            break;\n        }\n    }\n\n    if (0xFFFF == svidx)\n        return RT_ERR_SVLAN_ENTRY_NOT_FOUND;\n\n    empty_idx = 0xFFFF;\n\n    for (i=RTL8367C_SP2CMAX; i >=0 ; i--)\n    {\n        if ((retVal = rtl8367c_getAsicSvlanSP2CConf(i, &svlanSP2CConf)) != RT_ERR_OK)\n            return retVal;\n\n        if ( (svlanSP2CConf.svidx == svidx) && (svlanSP2CConf.dstport == port) && (svlanSP2CConf.valid == 1))\n        {\n            empty_idx = i;\n            break;\n        }\n        else if (svlanSP2CConf.valid == 0)\n        {\n            empty_idx = i;\n        }\n    }\n\n    if (empty_idx!=0xFFFF)\n    {\n        svlanSP2CConf.valid     = 1;\n        svlanSP2CConf.vid       = cvid;\n        svlanSP2CConf.svidx     = svidx;\n        svlanSP2CConf.dstport   = port;\n\n        if ((retVal = rtl8367c_setAsicSvlanSP2CConf(empty_idx, &svlanSP2CConf)) != RT_ERR_OK)\n            return retVal;\n        return RT_ERR_OK;\n    }\n\n    return RT_ERR_OUT_OF_RANGE;\n\n}\n\n/* Function Name:\n *      rtk_svlan_sp2c_get\n * Description:\n *      Get configure system SP2C content\n * Input:\n *      svid        - SVLAN VID\n *      dst_port    - Destination port of SVLAN to CVLAN configuration\n * Output:\n *      pCvid - VLAN ID\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n *      RT_ERR_OUT_OF_RANGE - input out of range.\n *      RT_ERR_PORT_ID      - Invalid port number.\n *      RT_ERR_SVLAN_VID    - Invalid SVLAN VID parameter.\n * Note:\n *     The API can get SVID & Destination Port to CVLAN configuration. There are 128 SP2C configurations.\n */\nrtk_api_ret_t rtk_svlan_sp2c_get(rtk_vlan_t svid, rtk_port_t dst_port, rtk_vlan_t *pCvid)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32 i, svidx;\n    rtl8367c_svlan_memconf_t svlanMemConf;\n    rtl8367c_svlan_s2c_t svlanSP2CConf;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(NULL == pCvid)\n        return RT_ERR_NULL_POINTER;\n\n    if (svid > RTL8367C_VIDMAX)\n        return RT_ERR_SVLAN_VID;\n\n    /* Check port Valid */\n    RTK_CHK_PORT_VALID(dst_port);\n    dst_port = rtk_switch_port_L2P_get(dst_port);\n\n    svidx = 0xFFFF;\n\n    for (i = 0; i < RTL8367C_SVIDXNO; i++)\n    {\n        if ((retVal = rtl8367c_getAsicSvlanMemberConfiguration(i, &svlanMemConf)) != RT_ERR_OK)\n            return retVal;\n\n        if (svid == svlanMemConf.vs_svid)\n        {\n            svidx = i;\n            break;\n        }\n    }\n\n    if (0xFFFF == svidx)\n        return RT_ERR_SVLAN_ENTRY_NOT_FOUND;\n\n    for (i = 0; i <= RTL8367C_SP2CMAX; i++)\n    {\n        if ((retVal = rtl8367c_getAsicSvlanSP2CConf(i, &svlanSP2CConf)) != RT_ERR_OK)\n            return retVal;\n\n        if ( (svlanSP2CConf.svidx == svidx) && (svlanSP2CConf.dstport == dst_port) && (svlanSP2CConf.valid == 1) )\n        {\n            *pCvid = svlanSP2CConf.vid;\n            return RT_ERR_OK;\n        }\n    }\n\n    return RT_ERR_OUT_OF_RANGE;\n}\n\n/* Function Name:\n *      rtk_svlan_sp2c_del\n * Description:\n *      Delete system SP2C configuration\n * Input:\n *      svid        - SVLAN VID\n *      dst_port    - Destination port of SVLAN to CVLAN configuration\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number.\n *      RT_ERR_SVLAN_VID    - Invalid SVLAN VID parameter.\n *      RT_ERR_OUT_OF_RANGE - input out of range.\n * Note:\n *      The API can delete SVID & Destination Port to CVLAN configuration. There are 128 SP2C configurations.\n */\nrtk_api_ret_t rtk_svlan_sp2c_del(rtk_vlan_t svid, rtk_port_t dst_port)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32 i, svidx;\n    rtl8367c_svlan_memconf_t svlanMemConf;\n    rtl8367c_svlan_s2c_t svlanSP2CConf;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if (svid > RTL8367C_VIDMAX)\n        return RT_ERR_SVLAN_VID;\n\n    /* Check port Valid */\n    RTK_CHK_PORT_VALID(dst_port);\n    dst_port = rtk_switch_port_L2P_get(dst_port);\n\n    svidx = 0xFFFF;\n\n    for (i = 0; i < RTL8367C_SVIDXNO; i++)\n    {\n        if ((retVal = rtl8367c_getAsicSvlanMemberConfiguration(i, &svlanMemConf)) != RT_ERR_OK)\n            return retVal;\n\n        if (svid == svlanMemConf.vs_svid)\n        {\n            svidx = i;\n            break;\n        }\n    }\n\n    if (0xFFFF == svidx)\n        return RT_ERR_SVLAN_ENTRY_NOT_FOUND;\n\n    for (i = 0; i <= RTL8367C_SP2CMAX; i++)\n    {\n        if ((retVal = rtl8367c_getAsicSvlanSP2CConf(i, &svlanSP2CConf)) != RT_ERR_OK)\n            return retVal;\n\n        if ( (svlanSP2CConf.svidx == svidx) && (svlanSP2CConf.dstport == dst_port) && (svlanSP2CConf.valid == 1) )\n        {\n            svlanSP2CConf.valid     = 0;\n            svlanSP2CConf.vid       = 0;\n            svlanSP2CConf.svidx     = 0;\n            svlanSP2CConf.dstport   = 0;\n\n            if ((retVal = rtl8367c_setAsicSvlanSP2CConf(i, &svlanSP2CConf)) != RT_ERR_OK)\n                return retVal;\n            return RT_ERR_OK;\n        }\n\n    }\n\n    return RT_ERR_OUT_OF_RANGE;\n}\n\n/* Function Name:\n *      rtk_svlan_lookupType_set\n * Description:\n *      Set lookup type of SVLAN\n * Input:\n *      type        - lookup type\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n * Note:\n *      none\n */\nrtk_api_ret_t rtk_svlan_lookupType_set(rtk_svlan_lookupType_t type)\n{\n    rtk_api_ret_t   retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if (type >= SVLAN_LOOKUP_END)\n        return RT_ERR_CHIP_NOT_SUPPORTED;\n\n\n    svlan_lookupType = type;\n\n    retVal = rtl8367c_setAsicSvlanLookupType((rtk_uint32)type);\n\n    return retVal;\n}\n\n/* Function Name:\n *      rtk_svlan_lookupType_get\n * Description:\n *      Get lookup type of SVLAN\n * Input:\n *      pType       - lookup type\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n * Note:\n *      none\n */\nrtk_api_ret_t rtk_svlan_lookupType_get(rtk_svlan_lookupType_t *pType)\n{\n    rtk_api_ret_t   retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(NULL == pType)\n        return RT_ERR_NULL_POINTER;\n\n    retVal = rtl8367c_getAsicSvlanLookupType(pType);\n\n    svlan_lookupType = *pType;\n\n    return retVal;\n}\n\n/* Function Name:\n *      rtk_svlan_trapPri_set\n * Description:\n *      Set svlan trap priority\n * Input:\n *      priority - priority for trap packets\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n *      RT_ERR_QOS_INT_PRIORITY\n * Note:\n *      None\n */\nrtk_api_ret_t rtk_svlan_trapPri_set(rtk_pri_t priority)\n{\n    rtk_api_ret_t   retVal;\n\n    RTK_CHK_INIT_STATE();\n\n    if(priority > RTL8367C_PRIMAX)\n        return RT_ERR_OUT_OF_RANGE;\n\n    retVal = rtl8367c_setAsicSvlanTrapPriority(priority);\n\n    return retVal;\n}   /* end of rtk_svlan_trapPri_set */\n\n/* Function Name:\n *      rtk_svlan_trapPri_get\n * Description:\n *      Get svlan trap priority\n * Input:\n *      None\n * Output:\n *      pPriority - priority for trap packets\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n *      RT_ERR_NULL_POINTER - input parameter may be null pointer\n * Note:\n *      None\n */\nrtk_api_ret_t rtk_svlan_trapPri_get(rtk_pri_t *pPriority)\n{\n    rtk_api_ret_t   retVal;\n\n    RTK_CHK_INIT_STATE();\n\n    if(NULL == pPriority)\n        return RT_ERR_NULL_POINTER;\n\n    retVal = rtl8367c_getAsicSvlanTrapPriority(pPriority);\n\n    return retVal;\n}   /* end of rtk_svlan_trapPri_get */\n\n\n/* Function Name:\n *      rtk_svlan_checkAndCreateMbr\n * Description:\n *      Check and create Member configuration and return index\n * Input:\n *      vid  - VLAN id.\n * Output:\n *      pIndex  - Member configuration index\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_VLAN_VID     - Invalid VLAN ID.\n *      RT_ERR_TBL_FULL     - Member Configuration table full\n * Note:\n *\n */\nrtk_api_ret_t rtk_svlan_checkAndCreateMbr(rtk_vlan_t vid, rtk_uint32 *pIndex)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32 svidx;\n    rtk_uint32 empty_idx = 0xFFFF;\n    rtl8367c_svlan_memconf_t svlan_cfg;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* vid must be 0~4095 */\n    if (vid > RTL8367C_VIDMAX)\n        return RT_ERR_VLAN_VID;\n\n    /* Null pointer check */\n    if(NULL == pIndex)\n        return RT_ERR_NULL_POINTER;\n\n    /* Search exist entry */\n    for (svidx = 0; svidx <= RTL8367C_SVIDXMAX; svidx++)\n    {\n        if(svlan_mbrCfgUsage[svidx] == TRUE)\n        {\n            if(svlan_mbrCfgVid[svidx] == vid)\n            {\n                /* Found! return index */\n                *pIndex = svidx;\n                return RT_ERR_OK;\n            }\n        }\n        else if(empty_idx == 0xFFFF)\n        {\n            empty_idx = svidx;\n        }\n\n    }\n\n    if(empty_idx == 0xFFFF)\n    {\n        /* No empty index */\n        return RT_ERR_TBL_FULL;\n    }\n\n    svlan_mbrCfgUsage[empty_idx] = TRUE;\n    svlan_mbrCfgVid[empty_idx] = vid;\n\n    memset(&svlan_cfg, 0, sizeof(rtl8367c_svlan_memconf_t));\n\n    svlan_cfg.vs_svid = vid;\n    /*for create check*/\n    if(vid == 0)\n    {\n        svlan_cfg.vs_efid = 1;\n    }\n\n    if((retVal = rtl8367c_setAsicSvlanMemberConfiguration(empty_idx, &svlan_cfg)) != RT_ERR_OK)\n        return retVal;\n\n    *pIndex = empty_idx;\n    return RT_ERR_OK;\n}\n\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/trap.c",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * $Revision: 76306 $\n * $Date: 2017-03-08 15:13:58 +0800 (週三, 08 三月 2017) $\n *\n * Purpose : RTK switch high-level API for RTL8367/RTL8367C\n * Feature : Here is a list of all functions and variables in Trap module.\n *\n */\n\n#include <rtk_switch.h>\n#include <rtk_error.h>\n#include <trap.h>\n#include <string.h>\n\n#include <rtl8367c_asicdrv.h>\n#include <rtl8367c_asicdrv_port.h>\n#include <rtl8367c_asicdrv_igmp.h>\n#include <rtl8367c_asicdrv_rma.h>\n#include <rtl8367c_asicdrv_eav.h>\n#include <rtl8367c_asicdrv_oam.h>\n#include <rtl8367c_asicdrv_svlan.h>\n#include <rtl8367c_asicdrv_unknownMulticast.h>\n#include <rtl8367c_asicdrv_dot1x.h>\n\n/* Function Name:\n *      rtk_trap_unknownUnicastPktAction_set\n * Description:\n *      Set unknown unicast packet action configuration.\n * Input:\n *      port            - ingress port ID for unknown unicast packet\n *      ucast_action    - Unknown unicast action.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK                  - OK\n *      RT_ERR_FAILED              - Failed\n *      RT_ERR_SMI                 - SMI access error\n *      RT_ERR_NOT_ALLOWED         - Invalid action.\n *      RT_ERR_INPUT               - Invalid input parameters.\n * Note:\n *      This API can set unknown unicast packet action configuration.\n *      The unknown unicast action is as following:\n *          - UCAST_ACTION_FORWARD_PMASK\n *          - UCAST_ACTION_DROP\n *          - UCAST_ACTION_TRAP2CPU\n *          - UCAST_ACTION_FLOODING\n */\nrtk_api_ret_t rtk_trap_unknownUnicastPktAction_set(rtk_port_t port, rtk_trap_ucast_action_t ucast_action)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* check port valid */\n    RTK_CHK_PORT_VALID(port);\n\n    if (ucast_action >= UCAST_ACTION_END)\n        return RT_ERR_INPUT;\n\n    if ((retVal = rtl8367c_setAsicPortUnknownDaBehavior(rtk_switch_port_L2P_get(port), ucast_action)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_trap_unknownUnicastPktAction_get\n * Description:\n *      Get unknown unicast packet action configuration.\n * Input:\n *      port            - ingress port ID for unknown unicast packet\n * Output:\n *      pUcast_action   - Unknown unicast action.\n * Return:\n *      RT_ERR_OK                  - OK\n *      RT_ERR_FAILED              - Failed\n *      RT_ERR_SMI                 - SMI access error\n *      RT_ERR_NOT_ALLOWED         - Invalid action.\n *      RT_ERR_INPUT               - Invalid input parameters.\n *      RT_ERR_NULL_POINTER        - Null pointer\n * Note:\n *      This API can get unknown unicast packet action configuration.\n *      The unknown unicast action is as following:\n *          - UCAST_ACTION_FORWARD_PMASK\n *          - UCAST_ACTION_DROP\n *          - UCAST_ACTION_TRAP2CPU\n *          - UCAST_ACTION_FLOODING\n */\nrtk_api_ret_t rtk_trap_unknownUnicastPktAction_get(rtk_port_t port, rtk_trap_ucast_action_t *pUcast_action)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* check port valid */\n    RTK_CHK_PORT_VALID(port);\n\n    if (NULL == pUcast_action)\n        return RT_ERR_NULL_POINTER;\n\n    if ((retVal = rtl8367c_getAsicPortUnknownDaBehavior(rtk_switch_port_L2P_get(port), pUcast_action)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_trap_unknownMacPktAction_set\n * Description:\n *      Set unknown source MAC packet action configuration.\n * Input:\n *      ucast_action    - Unknown source MAC action.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK                  - OK\n *      RT_ERR_FAILED              - Failed\n *      RT_ERR_SMI                 - SMI access error\n *      RT_ERR_NOT_ALLOWED         - Invalid action.\n *      RT_ERR_INPUT               - Invalid input parameters.\n * Note:\n *      This API can set unknown unicast packet action configuration.\n *      The unknown unicast action is as following:\n *          - UCAST_ACTION_FORWARD_PMASK\n *          - UCAST_ACTION_DROP\n *          - UCAST_ACTION_TRAP2CPU\n */\nrtk_api_ret_t rtk_trap_unknownMacPktAction_set(rtk_trap_ucast_action_t ucast_action)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if (ucast_action >= UCAST_ACTION_FLOODING)\n        return RT_ERR_INPUT;\n\n    if ((retVal = rtl8367c_setAsicPortUnknownSaBehavior(ucast_action)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_trap_unknownMacPktAction_get\n * Description:\n *      Get unknown source MAC packet action configuration.\n * Input:\n *      None.\n * Output:\n *      pUcast_action   - Unknown source MAC action.\n * Return:\n *      RT_ERR_OK                  - OK\n *      RT_ERR_FAILED              - Failed\n *      RT_ERR_SMI                 - SMI access error\n *      RT_ERR_NULL_POINTER        - Null Pointer.\n *      RT_ERR_INPUT               - Invalid input parameters.\n * Note:\n *\n */\nrtk_api_ret_t rtk_trap_unknownMacPktAction_get(rtk_trap_ucast_action_t *pUcast_action)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(NULL == pUcast_action)\n        return RT_ERR_NULL_POINTER;\n\n    if ((retVal = rtl8367c_getAsicPortUnknownSaBehavior(pUcast_action)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_trap_unmatchMacPktAction_set\n * Description:\n *      Set unmatch source MAC packet action configuration.\n * Input:\n *      ucast_action    - Unknown source MAC action.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK                  - OK\n *      RT_ERR_FAILED              - Failed\n *      RT_ERR_SMI                 - SMI access error\n *      RT_ERR_NOT_ALLOWED         - Invalid action.\n *      RT_ERR_INPUT               - Invalid input parameters.\n * Note:\n *      This API can set unknown unicast packet action configuration.\n *      The unknown unicast action is as following:\n *          - UCAST_ACTION_FORWARD_PMASK\n *          - UCAST_ACTION_DROP\n *          - UCAST_ACTION_TRAP2CPU\n */\nrtk_api_ret_t rtk_trap_unmatchMacPktAction_set(rtk_trap_ucast_action_t ucast_action)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if (ucast_action >= UCAST_ACTION_FLOODING)\n        return RT_ERR_INPUT;\n\n    if ((retVal = rtl8367c_setAsicPortUnmatchedSaBehavior(ucast_action)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_trap_unmatchMacPktAction_get\n * Description:\n *      Get unmatch source MAC packet action configuration.\n * Input:\n *      None.\n * Output:\n *      pUcast_action   - Unknown source MAC action.\n * Return:\n *      RT_ERR_OK                  - OK\n *      RT_ERR_FAILED              - Failed\n *      RT_ERR_SMI                 - SMI access error\n *      RT_ERR_NOT_ALLOWED         - Invalid action.\n *      RT_ERR_INPUT               - Invalid input parameters.\n * Note:\n *      This API can set unknown unicast packet action configuration.\n *      The unknown unicast action is as following:\n *          - UCAST_ACTION_FORWARD_PMASK\n *          - UCAST_ACTION_DROP\n *          - UCAST_ACTION_TRAP2CPU\n */\nrtk_api_ret_t rtk_trap_unmatchMacPktAction_get(rtk_trap_ucast_action_t *pUcast_action)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(NULL == pUcast_action)\n        return RT_ERR_NULL_POINTER;\n\n    if ((retVal = rtl8367c_getAsicPortUnmatchedSaBehavior(pUcast_action)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_trap_unmatchMacMoving_set\n * Description:\n *      Set unmatch source MAC packet moving state.\n * Input:\n *      port        - Port ID.\n *      enable      - ENABLED: allow SA moving, DISABLE: don't allow SA moving.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK                  - OK\n *      RT_ERR_FAILED              - Failed\n *      RT_ERR_SMI                 - SMI access error\n *      RT_ERR_NOT_ALLOWED         - Invalid action.\n *      RT_ERR_INPUT               - Invalid input parameters.\n * Note:\n */\nrtk_api_ret_t rtk_trap_unmatchMacMoving_set(rtk_port_t port, rtk_enable_t enable)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* check port valid */\n    RTK_CHK_PORT_VALID(port);\n\n    if(enable >= RTK_ENABLE_END)\n        return RT_ERR_INPUT;\n\n    if ((retVal = rtl8367c_setAsicPortUnmatchedSaMoving(rtk_switch_port_L2P_get(port), enable)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_trap_unmatchMacMoving_get\n * Description:\n *      Set unmatch source MAC packet moving state.\n * Input:\n *      port        - Port ID.\n * Output:\n *      pEnable     - ENABLED: allow SA moving, DISABLE: don't allow SA moving.\n * Return:\n *      RT_ERR_OK                  - OK\n *      RT_ERR_FAILED              - Failed\n *      RT_ERR_SMI                 - SMI access error\n *      RT_ERR_NOT_ALLOWED         - Invalid action.\n *      RT_ERR_INPUT               - Invalid input parameters.\n * Note:\n */\nrtk_api_ret_t rtk_trap_unmatchMacMoving_get(rtk_port_t port, rtk_enable_t *pEnable)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* check port valid */\n    RTK_CHK_PORT_VALID(port);\n\n    if(NULL == pEnable)\n        return RT_ERR_NULL_POINTER;\n\n    if ((retVal = rtl8367c_getAsicPortUnmatchedSaMoving(rtk_switch_port_L2P_get(port), pEnable)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_trap_unknownMcastPktAction_set\n * Description:\n *      Set behavior of unknown multicast\n * Input:\n *      port            - Port id.\n *      type            - unknown multicast packet type.\n *      mcast_action    - unknown multicast action.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID         - Invalid port number.\n *      RT_ERR_NOT_ALLOWED     - Invalid action.\n *      RT_ERR_INPUT         - Invalid input parameters.\n * Note:\n *      When receives an unknown multicast packet, switch may trap, drop or flood this packet\n *      (1) The unknown multicast packet type is as following:\n *          - MCAST_L2\n *          - MCAST_IPV4\n *          - MCAST_IPV6\n *      (2) The unknown multicast action is as following:\n *          - MCAST_ACTION_FORWARD\n *          - MCAST_ACTION_DROP\n *          - MCAST_ACTION_TRAP2CPU\n */\nrtk_api_ret_t rtk_trap_unknownMcastPktAction_set(rtk_port_t port, rtk_mcast_type_t type, rtk_trap_mcast_action_t mcast_action)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32 rawAction;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check Port Valid */\n    RTK_CHK_PORT_VALID(port);\n\n    if (type >= MCAST_END)\n        return RT_ERR_INPUT;\n\n    if (mcast_action >= MCAST_ACTION_END)\n        return RT_ERR_INPUT;\n\n\n    switch (type)\n    {\n        case MCAST_L2:\n            if (MCAST_ACTION_ROUTER_PORT == mcast_action)\n                return RT_ERR_INPUT;\n            else if(MCAST_ACTION_DROP_EX_RMA == mcast_action)\n                rawAction = L2_UNKOWN_MULTICAST_DROP_EXCLUDE_RMA;\n            else\n                rawAction = (rtk_uint32)mcast_action;\n\n            if ((retVal = rtl8367c_setAsicUnknownL2MulticastBehavior(rtk_switch_port_L2P_get(port), rawAction)) != RT_ERR_OK)\n                return retVal;\n\n            break;\n        case MCAST_IPV4:\n            if (MCAST_ACTION_DROP_EX_RMA == mcast_action)\n                return RT_ERR_INPUT;\n            else\n                rawAction = (rtk_uint32)mcast_action;\n\n            if ((retVal = rtl8367c_setAsicUnknownIPv4MulticastBehavior(rtk_switch_port_L2P_get(port), rawAction)) != RT_ERR_OK)\n                return retVal;\n\n            break;\n        case MCAST_IPV6:\n            if (MCAST_ACTION_DROP_EX_RMA == mcast_action)\n                return RT_ERR_INPUT;\n            else\n                rawAction = (rtk_uint32)mcast_action;\n\n            if ((retVal = rtl8367c_setAsicUnknownIPv6MulticastBehavior(rtk_switch_port_L2P_get(port), rawAction)) != RT_ERR_OK)\n                return retVal;\n\n            break;\n        default:\n            break;\n    }\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_trap_unknownMcastPktAction_get\n * Description:\n *      Get behavior of unknown multicast\n * Input:\n *      type - unknown multicast packet type.\n * Output:\n *      pMcast_action - unknown multicast action.\n * Return:\n *      RT_ERR_OK                  - OK\n *      RT_ERR_FAILED              - Failed\n *      RT_ERR_SMI                 - SMI access error\n *      RT_ERR_PORT_ID             - Invalid port number.\n *      RT_ERR_NOT_ALLOWED         - Invalid operation.\n *      RT_ERR_INPUT             - Invalid input parameters.\n * Note:\n *      When receives an unknown multicast packet, switch may trap, drop or flood this packet\n *      (1) The unknown multicast packet type is as following:\n *          - MCAST_L2\n *          - MCAST_IPV4\n *          - MCAST_IPV6\n *      (2) The unknown multicast action is as following:\n *          - MCAST_ACTION_FORWARD\n *          - MCAST_ACTION_DROP\n *          - MCAST_ACTION_TRAP2CPU\n */\nrtk_api_ret_t rtk_trap_unknownMcastPktAction_get(rtk_port_t port, rtk_mcast_type_t type, rtk_trap_mcast_action_t *pMcast_action)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32 rawAction;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check Port Valid */\n    RTK_CHK_PORT_VALID(port);\n\n    if (type >= MCAST_END)\n        return RT_ERR_INPUT;\n\n    if(NULL == pMcast_action)\n        return RT_ERR_NULL_POINTER;\n\n    switch (type)\n    {\n        case MCAST_L2:\n            if ((retVal = rtl8367c_getAsicUnknownL2MulticastBehavior(rtk_switch_port_L2P_get(port), &rawAction)) != RT_ERR_OK)\n                return retVal;\n\n            if(L2_UNKOWN_MULTICAST_DROP_EXCLUDE_RMA == rawAction)\n                *pMcast_action = MCAST_ACTION_DROP_EX_RMA;\n            else\n                *pMcast_action = (rtk_trap_mcast_action_t)rawAction;\n\n            break;\n        case MCAST_IPV4:\n            if ((retVal = rtl8367c_getAsicUnknownIPv4MulticastBehavior(rtk_switch_port_L2P_get(port), &rawAction)) != RT_ERR_OK)\n                return retVal;\n\n            *pMcast_action = (rtk_trap_mcast_action_t)rawAction;\n            break;\n        case MCAST_IPV6:\n            if ((retVal = rtl8367c_getAsicUnknownIPv6MulticastBehavior(rtk_switch_port_L2P_get(port), &rawAction)) != RT_ERR_OK)\n                return retVal;\n\n            *pMcast_action = (rtk_trap_mcast_action_t)rawAction;\n            break;\n        default:\n            break;\n    }\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_trap_lldpEnable_set\n * Description:\n *      Set LLDP enable.\n * Input:\n *      enabled - LLDP enable, 0: follow RMA, 1: use LLDP action.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK                  - OK\n *      RT_ERR_FAILED              - Failed\n *      RT_ERR_SMI                 - SMI access error\n *      RT_ERR_NOT_ALLOWED         - Invalid action.\n *      RT_ERR_INPUT             - Invalid input parameters.\n * Note:\n *      - DMAC                                                 Assignment\n *      - 01:80:c2:00:00:0e ethertype = 0x88CC    LLDP\n *      - 01:80:c2:00:00:03 ethertype = 0x88CC\n *      - 01:80:c2:00:00:00 ethertype = 0x88CC\n\n */\nrtk_api_ret_t rtk_trap_lldpEnable_set(rtk_enable_t enabled)\n{\n    rtk_api_ret_t retVal;\n    rtl8367c_rma_t rmacfg;\n    rtk_enable_t tmp;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if (enabled >= RTK_ENABLE_END)\n        return RT_ERR_ENABLE;\n\n    if ((retVal = rtl8367c_getAsicRmaLldp(&tmp, &rmacfg)) != RT_ERR_OK)\n        return retVal;\n\n    if ((retVal = rtl8367c_setAsicRmaLldp(enabled, &rmacfg)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_trap_lldpEnable_get\n * Description:\n *      Get LLDP status.\n * Input:\n *      None\n * Output:\n *      pEnabled - LLDP enable, 0: follow RMA, 1: use LLDP action.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT         - Invalid input parameters.\n * Note:\n *      LLDP is as following definition.\n *      - DMAC                                                 Assignment\n *      - 01:80:c2:00:00:0e ethertype = 0x88CC    LLDP\n *      - 01:80:c2:00:00:03 ethertype = 0x88CC\n *      - 01:80:c2:00:00:00 ethertype = 0x88CC\n */\nrtk_api_ret_t rtk_trap_lldpEnable_get(rtk_enable_t *pEnabled)\n{\n    rtk_api_ret_t retVal;\n    rtl8367c_rma_t rmacfg;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(NULL == pEnabled)\n        return RT_ERR_NULL_POINTER;\n\n    if ((retVal = rtl8367c_getAsicRmaLldp(pEnabled, &rmacfg)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_trap_reasonTrapToCpuPriority_set\n * Description:\n *      Set priority value of a packet that trapped to CPU port according to specific reason.\n * Input:\n *      type     - reason that trap to CPU port.\n *      priority - internal priority that is going to be set for specific trap reason.\n * Output:\n *      None.\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n *      RT_ERR_NOT_INIT - The module is not initial\n *      RT_ERR_INPUT    - Invalid input parameter\n * Note:\n *      Currently the trap reason that supported are listed as follows:\n *      - TRAP_REASON_RMA\n *      - TRAP_REASON_OAM\n *      - TRAP_REASON_1XUNAUTH\n *      - TRAP_REASON_VLANSTACK\n *      - TRAP_REASON_UNKNOWNMC\n */\nrtk_api_ret_t rtk_trap_reasonTrapToCpuPriority_set(rtk_trap_reason_type_t type, rtk_pri_t priority)\n{\n    rtk_api_ret_t retVal;\n    rtl8367c_rma_t rmacfg;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if (type >= TRAP_REASON_END)\n        return RT_ERR_INPUT;\n\n    if (priority > RTL8367C_PRIMAX)\n        return  RT_ERR_QOS_INT_PRIORITY;\n\n    switch (type)\n    {\n        case TRAP_REASON_RMA:\n            if ((retVal = rtl8367c_getAsicRma(0, &rmacfg)) != RT_ERR_OK)\n                return retVal;\n            rmacfg.trap_priority= priority;\n            if ((retVal = rtl8367c_setAsicRma(0, &rmacfg)) != RT_ERR_OK)\n                return retVal;\n\n            break;\n        case TRAP_REASON_OAM:\n            if ((retVal = rtl8367c_setAsicOamCpuPri(priority)) != RT_ERR_OK)\n                return retVal;\n\n            break;\n        case TRAP_REASON_1XUNAUTH:\n            if ((retVal = rtl8367c_setAsic1xTrapPriority(priority)) != RT_ERR_OK)\n                return retVal;\n\n            break;\n        case TRAP_REASON_VLANSTACK:\n            if ((retVal = rtl8367c_setAsicSvlanTrapPriority(priority)) != RT_ERR_OK)\n                return retVal;\n\n            break;\n        case TRAP_REASON_UNKNOWNMC:\n            if ((retVal = rtl8367c_setAsicUnknownMulticastTrapPriority(priority)) != RT_ERR_OK)\n                return retVal;\n\n            break;\n        default:\n            return RT_ERR_CHIP_NOT_SUPPORTED;\n    }\n\n\n    return RT_ERR_OK;\n}\n\n\n/* Function Name:\n *      rtk_trap_reasonTrapToCpuPriority_get\n * Description:\n *      Get priority value of a packet that trapped to CPU port according to specific reason.\n * Input:\n *      type      - reason that trap to CPU port.\n * Output:\n *      pPriority - configured internal priority for such reason.\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n *      RT_ERR_NOT_INIT     - The module is not initial\n *      RT_ERR_INPUT        - Invalid input parameter\n *      RT_ERR_NULL_POINTER - NULL pointer\n * Note:\n *      Currently the trap reason that supported are listed as follows:\n *      - TRAP_REASON_RMA\n *      - TRAP_REASON_OAM\n *      - TRAP_REASON_1XUNAUTH\n *      - TRAP_REASON_VLANSTACK\n *      - TRAP_REASON_UNKNOWNMC\n */\nrtk_api_ret_t rtk_trap_reasonTrapToCpuPriority_get(rtk_trap_reason_type_t type, rtk_pri_t *pPriority)\n{\n    rtk_api_ret_t retVal;\n    rtl8367c_rma_t rmacfg;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if (type >= TRAP_REASON_END)\n        return RT_ERR_INPUT;\n\n    if(NULL == pPriority)\n        return RT_ERR_NULL_POINTER;\n\n    switch (type)\n    {\n        case TRAP_REASON_RMA:\n            if ((retVal = rtl8367c_getAsicRma(0, &rmacfg)) != RT_ERR_OK)\n                return retVal;\n            *pPriority = rmacfg.trap_priority;\n\n            break;\n        case TRAP_REASON_OAM:\n            if ((retVal = rtl8367c_getAsicOamCpuPri(pPriority)) != RT_ERR_OK)\n                return retVal;\n\n            break;\n        case TRAP_REASON_1XUNAUTH:\n            if ((retVal = rtl8367c_getAsic1xTrapPriority(pPriority)) != RT_ERR_OK)\n                return retVal;\n\n            break;\n        case TRAP_REASON_VLANSTACK:\n            if ((retVal = rtl8367c_getAsicSvlanTrapPriority(pPriority)) != RT_ERR_OK)\n                return retVal;\n\n            break;\n        case TRAP_REASON_UNKNOWNMC:\n            if ((retVal = rtl8367c_getAsicUnknownMulticastTrapPriority(pPriority)) != RT_ERR_OK)\n                return retVal;\n\n            break;\n        default:\n            return RT_ERR_CHIP_NOT_SUPPORTED;\n\n    }\n\n    return RT_ERR_OK;\n}\n\n\n\n/* Function Name:\n *      rtk_trap_rmaAction_set\n * Description:\n *      Set Reserved multicast address action configuration.\n * Input:\n *      type    - rma type.\n *      rma_action - RMA action.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n * Note:\n *\n *      There are 48 types of Reserved Multicast Address frame for application usage.\n *      (1)They are as following definition.\n *      - TRAP_BRG_GROUP,\n *      - TRAP_FD_PAUSE,\n *      - TRAP_SP_MCAST,\n *      - TRAP_1X_PAE,\n *      - TRAP_UNDEF_BRG_04,\n *      - TRAP_UNDEF_BRG_05,\n *      - TRAP_UNDEF_BRG_06,\n *      - TRAP_UNDEF_BRG_07,\n *      - TRAP_PROVIDER_BRIDGE_GROUP_ADDRESS,\n *      - TRAP_UNDEF_BRG_09,\n *      - TRAP_UNDEF_BRG_0A,\n *      - TRAP_UNDEF_BRG_0B,\n *      - TRAP_UNDEF_BRG_0C,\n *      - TRAP_PROVIDER_BRIDGE_GVRP_ADDRESS,\n *      - TRAP_8021AB,\n *      - TRAP_UNDEF_BRG_0F,\n *      - TRAP_BRG_MNGEMENT,\n *      - TRAP_UNDEFINED_11,\n *      - TRAP_UNDEFINED_12,\n *      - TRAP_UNDEFINED_13,\n *      - TRAP_UNDEFINED_14,\n *      - TRAP_UNDEFINED_15,\n *      - TRAP_UNDEFINED_16,\n *      - TRAP_UNDEFINED_17,\n *      - TRAP_UNDEFINED_18,\n *      - TRAP_UNDEFINED_19,\n *      - TRAP_UNDEFINED_1A,\n *      - TRAP_UNDEFINED_1B,\n *      - TRAP_UNDEFINED_1C,\n *      - TRAP_UNDEFINED_1D,\n *      - TRAP_UNDEFINED_1E,\n *      - TRAP_UNDEFINED_1F,\n *      - TRAP_GMRP,\n *      - TRAP_GVRP,\n *      - TRAP_UNDEF_GARP_22,\n *      - TRAP_UNDEF_GARP_23,\n *      - TRAP_UNDEF_GARP_24,\n *      - TRAP_UNDEF_GARP_25,\n *      - TRAP_UNDEF_GARP_26,\n *      - TRAP_UNDEF_GARP_27,\n *      - TRAP_UNDEF_GARP_28,\n *      - TRAP_UNDEF_GARP_29,\n *      - TRAP_UNDEF_GARP_2A,\n *      - TRAP_UNDEF_GARP_2B,\n *      - TRAP_UNDEF_GARP_2C,\n *      - TRAP_UNDEF_GARP_2D,\n *      - TRAP_UNDEF_GARP_2E,\n *      - TRAP_UNDEF_GARP_2F,\n *      - TRAP_CDP.\n *      - TRAP_CSSTP.\n *      - TRAP_LLDP.\n *      (2) The RMA action is as following:\n *      - RMA_ACTION_FORWARD\n *      - RMA_ACTION_TRAP2CPU\n *      - RMA_ACTION_DROP\n *      - RMA_ACTION_FORWARD_EXCLUDE_CPU\n */\nrtk_api_ret_t rtk_trap_rmaAction_set(rtk_trap_type_t type, rtk_trap_rma_action_t rma_action)\n{\n    rtk_api_ret_t retVal;\n    rtl8367c_rma_t rmacfg;\n    rtk_uint32 tmp;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if (type >= TRAP_END)\n        return RT_ERR_INPUT;\n\n    if (rma_action >= RMA_ACTION_END)\n        return RT_ERR_RMA_ACTION;\n\n    if (type >= 0 && type <= TRAP_UNDEF_GARP_2F)\n    {\n        if ((retVal = rtl8367c_getAsicRma(type, &rmacfg)) != RT_ERR_OK)\n            return retVal;\n\n        rmacfg.operation = rma_action;\n\n        if ((retVal = rtl8367c_setAsicRma(type, &rmacfg)) != RT_ERR_OK)\n            return retVal;\n    }\n    else if (type == TRAP_CDP)\n    {\n        if ((retVal = rtl8367c_getAsicRmaCdp(&rmacfg)) != RT_ERR_OK)\n            return retVal;\n\n        rmacfg.operation = rma_action;\n\n        if ((retVal = rtl8367c_setAsicRmaCdp(&rmacfg)) != RT_ERR_OK)\n            return retVal;\n    }\n    else if (type  == TRAP_CSSTP)\n    {\n        if ((retVal = rtl8367c_getAsicRmaCsstp(&rmacfg)) != RT_ERR_OK)\n            return retVal;\n\n        rmacfg.operation = rma_action;\n\n        if ((retVal = rtl8367c_setAsicRmaCsstp(&rmacfg)) != RT_ERR_OK)\n            return retVal;\n    }\n    else if (type  == TRAP_LLDP)\n    {\n        if ((retVal = rtl8367c_getAsicRmaLldp(&tmp, &rmacfg)) != RT_ERR_OK)\n            return retVal;\n\n        rmacfg.operation = rma_action;\n\n        if ((retVal = rtl8367c_setAsicRmaLldp(tmp, &rmacfg)) != RT_ERR_OK)\n            return retVal;\n    }\n    else\n        return RT_ERR_INPUT;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_trap_rmaAction_get\n * Description:\n *      Get Reserved multicast address action configuration.\n * Input:\n *      type - rma type.\n * Output:\n *      pRma_action - RMA action.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n * Note:\n *      There are 48 types of Reserved Multicast Address frame for application usage.\n *      (1)They are as following definition.\n *      - TRAP_BRG_GROUP,\n *      - TRAP_FD_PAUSE,\n *      - TRAP_SP_MCAST,\n *      - TRAP_1X_PAE,\n *      - TRAP_UNDEF_BRG_04,\n *      - TRAP_UNDEF_BRG_05,\n *      - TRAP_UNDEF_BRG_06,\n *      - TRAP_UNDEF_BRG_07,\n *      - TRAP_PROVIDER_BRIDGE_GROUP_ADDRESS,\n *      - TRAP_UNDEF_BRG_09,\n *      - TRAP_UNDEF_BRG_0A,\n *      - TRAP_UNDEF_BRG_0B,\n *      - TRAP_UNDEF_BRG_0C,\n *      - TRAP_PROVIDER_BRIDGE_GVRP_ADDRESS,\n *      - TRAP_8021AB,\n *      - TRAP_UNDEF_BRG_0F,\n *      - TRAP_BRG_MNGEMENT,\n *      - TRAP_UNDEFINED_11,\n *      - TRAP_UNDEFINED_12,\n *      - TRAP_UNDEFINED_13,\n *      - TRAP_UNDEFINED_14,\n *      - TRAP_UNDEFINED_15,\n *      - TRAP_UNDEFINED_16,\n *      - TRAP_UNDEFINED_17,\n *      - TRAP_UNDEFINED_18,\n *      - TRAP_UNDEFINED_19,\n *      - TRAP_UNDEFINED_1A,\n *      - TRAP_UNDEFINED_1B,\n *      - TRAP_UNDEFINED_1C,\n *      - TRAP_UNDEFINED_1D,\n *      - TRAP_UNDEFINED_1E,\n *      - TRAP_UNDEFINED_1F,\n *      - TRAP_GMRP,\n *      - TRAP_GVRP,\n *      - TRAP_UNDEF_GARP_22,\n *      - TRAP_UNDEF_GARP_23,\n *      - TRAP_UNDEF_GARP_24,\n *      - TRAP_UNDEF_GARP_25,\n *      - TRAP_UNDEF_GARP_26,\n *      - TRAP_UNDEF_GARP_27,\n *      - TRAP_UNDEF_GARP_28,\n *      - TRAP_UNDEF_GARP_29,\n *      - TRAP_UNDEF_GARP_2A,\n *      - TRAP_UNDEF_GARP_2B,\n *      - TRAP_UNDEF_GARP_2C,\n *      - TRAP_UNDEF_GARP_2D,\n *      - TRAP_UNDEF_GARP_2E,\n *      - TRAP_UNDEF_GARP_2F,\n *      - TRAP_CDP.\n *      - TRAP_CSSTP.\n *      - TRAP_LLDP.\n *      (2) The RMA action is as following:\n *      - RMA_ACTION_FORWARD\n *      - RMA_ACTION_TRAP2CPU\n *      - RMA_ACTION_DROP\n *      - RMA_ACTION_FORWARD_EXCLUDE_CPU\n */\nrtk_api_ret_t rtk_trap_rmaAction_get(rtk_trap_type_t type, rtk_trap_rma_action_t *pRma_action)\n{\n    rtk_api_ret_t retVal;\n    rtl8367c_rma_t rmacfg;\n    rtk_uint32 tmp;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if (type >= TRAP_END)\n        return RT_ERR_INPUT;\n\n    if(NULL == pRma_action)\n        return RT_ERR_NULL_POINTER;\n\n    if (type >= 0 && type <= TRAP_UNDEF_GARP_2F)\n    {\n        if ((retVal = rtl8367c_getAsicRma(type, &rmacfg)) != RT_ERR_OK)\n            return retVal;\n\n        *pRma_action = rmacfg.operation;\n    }\n    else if (type == TRAP_CDP)\n    {\n        if ((retVal = rtl8367c_getAsicRmaCdp(&rmacfg)) != RT_ERR_OK)\n            return retVal;\n\n        *pRma_action = rmacfg.operation;\n    }\n    else if (type == TRAP_CSSTP)\n    {\n        if ((retVal = rtl8367c_getAsicRmaCsstp(&rmacfg)) != RT_ERR_OK)\n            return retVal;\n\n        *pRma_action = rmacfg.operation;\n    }\n    else if (type == TRAP_LLDP)\n    {\n        if ((retVal = rtl8367c_getAsicRmaLldp(&tmp,&rmacfg)) != RT_ERR_OK)\n            return retVal;\n\n        *pRma_action = rmacfg.operation;\n    }\n    else\n        return RT_ERR_INPUT;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_trap_rmaKeepFormat_set\n * Description:\n *      Set Reserved multicast address keep format configuration.\n * Input:\n *      type    - rma type.\n *      enable - enable keep format.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n *      RT_ERR_ENABLE       - Invalid IFG parameter\n * Note:\n *\n *      There are 48 types of Reserved Multicast Address frame for application usage.\n *      They are as following definition.\n *      - TRAP_BRG_GROUP,\n *      - TRAP_FD_PAUSE,\n *      - TRAP_SP_MCAST,\n *      - TRAP_1X_PAE,\n *      - TRAP_UNDEF_BRG_04,\n *      - TRAP_UNDEF_BRG_05,\n *      - TRAP_UNDEF_BRG_06,\n *      - TRAP_UNDEF_BRG_07,\n *      - TRAP_PROVIDER_BRIDGE_GROUP_ADDRESS,\n *      - TRAP_UNDEF_BRG_09,\n *      - TRAP_UNDEF_BRG_0A,\n *      - TRAP_UNDEF_BRG_0B,\n *      - TRAP_UNDEF_BRG_0C,\n *      - TRAP_PROVIDER_BRIDGE_GVRP_ADDRESS,\n *      - TRAP_8021AB,\n *      - TRAP_UNDEF_BRG_0F,\n *      - TRAP_BRG_MNGEMENT,\n *      - TRAP_UNDEFINED_11,\n *      - TRAP_UNDEFINED_12,\n *      - TRAP_UNDEFINED_13,\n *      - TRAP_UNDEFINED_14,\n *      - TRAP_UNDEFINED_15,\n *      - TRAP_UNDEFINED_16,\n *      - TRAP_UNDEFINED_17,\n *      - TRAP_UNDEFINED_18,\n *      - TRAP_UNDEFINED_19,\n *      - TRAP_UNDEFINED_1A,\n *      - TRAP_UNDEFINED_1B,\n *      - TRAP_UNDEFINED_1C,\n *      - TRAP_UNDEFINED_1D,\n *      - TRAP_UNDEFINED_1E,\n *      - TRAP_UNDEFINED_1F,\n *      - TRAP_GMRP,\n *      - TRAP_GVRP,\n *      - TRAP_UNDEF_GARP_22,\n *      - TRAP_UNDEF_GARP_23,\n *      - TRAP_UNDEF_GARP_24,\n *      - TRAP_UNDEF_GARP_25,\n *      - TRAP_UNDEF_GARP_26,\n *      - TRAP_UNDEF_GARP_27,\n *      - TRAP_UNDEF_GARP_28,\n *      - TRAP_UNDEF_GARP_29,\n *      - TRAP_UNDEF_GARP_2A,\n *      - TRAP_UNDEF_GARP_2B,\n *      - TRAP_UNDEF_GARP_2C,\n *      - TRAP_UNDEF_GARP_2D,\n *      - TRAP_UNDEF_GARP_2E,\n *      - TRAP_UNDEF_GARP_2F,\n *      - TRAP_CDP.\n *      - TRAP_CSSTP.\n *      - TRAP_LLDP.\n */\nrtk_api_ret_t rtk_trap_rmaKeepFormat_set(rtk_trap_type_t type, rtk_enable_t enable)\n{\n    rtk_api_ret_t retVal;\n    rtl8367c_rma_t rmacfg;\n    rtk_uint32 tmp;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if (type >= TRAP_END)\n        return RT_ERR_INPUT;\n\n    if (enable >= RTK_ENABLE_END)\n        return RT_ERR_INPUT;\n\n    if (type >= 0 && type <= TRAP_UNDEF_GARP_2F)\n    {\n        if ((retVal = rtl8367c_getAsicRma(type, &rmacfg)) != RT_ERR_OK)\n            return retVal;\n\n        rmacfg.keep_format = enable;\n\n        if ((retVal = rtl8367c_setAsicRma(type, &rmacfg)) != RT_ERR_OK)\n            return retVal;\n    }\n    else if (type == TRAP_CDP)\n    {\n        if ((retVal = rtl8367c_getAsicRmaCdp(&rmacfg)) != RT_ERR_OK)\n            return retVal;\n\n        rmacfg.keep_format = enable;\n\n        if ((retVal = rtl8367c_setAsicRmaCdp(&rmacfg)) != RT_ERR_OK)\n            return retVal;\n    }\n    else if (type  == TRAP_CSSTP)\n    {\n        if ((retVal = rtl8367c_getAsicRmaCsstp(&rmacfg)) != RT_ERR_OK)\n            return retVal;\n\n        rmacfg.keep_format = enable;\n\n        if ((retVal = rtl8367c_setAsicRmaCsstp(&rmacfg)) != RT_ERR_OK)\n            return retVal;\n    }\n    else if (type  == TRAP_LLDP)\n    {\n        if ((retVal = rtl8367c_getAsicRmaLldp(&tmp, &rmacfg)) != RT_ERR_OK)\n            return retVal;\n\n        rmacfg.keep_format = enable;\n\n        if ((retVal = rtl8367c_setAsicRmaLldp(tmp, &rmacfg)) != RT_ERR_OK)\n            return retVal;\n    }\n    else\n        return RT_ERR_INPUT;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_trap_rmaKeepFormat_get\n * Description:\n *      Get Reserved multicast address action configuration.\n * Input:\n *      type - rma type.\n * Output:\n *      pEnable - keep format status.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n * Note:\n *      There are 48 types of Reserved Multicast Address frame for application usage.\n *      They are as following definition.\n *      - TRAP_BRG_GROUP,\n *      - TRAP_FD_PAUSE,\n *      - TRAP_SP_MCAST,\n *      - TRAP_1X_PAE,\n *      - TRAP_UNDEF_BRG_04,\n *      - TRAP_UNDEF_BRG_05,\n *      - TRAP_UNDEF_BRG_06,\n *      - TRAP_UNDEF_BRG_07,\n *      - TRAP_PROVIDER_BRIDGE_GROUP_ADDRESS,\n *      - TRAP_UNDEF_BRG_09,\n *      - TRAP_UNDEF_BRG_0A,\n *      - TRAP_UNDEF_BRG_0B,\n *      - TRAP_UNDEF_BRG_0C,\n *      - TRAP_PROVIDER_BRIDGE_GVRP_ADDRESS,\n *      - TRAP_8021AB,\n *      - TRAP_UNDEF_BRG_0F,\n *      - TRAP_BRG_MNGEMENT,\n *      - TRAP_UNDEFINED_11,\n *      - TRAP_UNDEFINED_12,\n *      - TRAP_UNDEFINED_13,\n *      - TRAP_UNDEFINED_14,\n *      - TRAP_UNDEFINED_15,\n *      - TRAP_UNDEFINED_16,\n *      - TRAP_UNDEFINED_17,\n *      - TRAP_UNDEFINED_18,\n *      - TRAP_UNDEFINED_19,\n *      - TRAP_UNDEFINED_1A,\n *      - TRAP_UNDEFINED_1B,\n *      - TRAP_UNDEFINED_1C,\n *      - TRAP_UNDEFINED_1D,\n *      - TRAP_UNDEFINED_1E,\n *      - TRAP_UNDEFINED_1F,\n *      - TRAP_GMRP,\n *      - TRAP_GVRP,\n *      - TRAP_UNDEF_GARP_22,\n *      - TRAP_UNDEF_GARP_23,\n *      - TRAP_UNDEF_GARP_24,\n *      - TRAP_UNDEF_GARP_25,\n *      - TRAP_UNDEF_GARP_26,\n *      - TRAP_UNDEF_GARP_27,\n *      - TRAP_UNDEF_GARP_28,\n *      - TRAP_UNDEF_GARP_29,\n *      - TRAP_UNDEF_GARP_2A,\n *      - TRAP_UNDEF_GARP_2B,\n *      - TRAP_UNDEF_GARP_2C,\n *      - TRAP_UNDEF_GARP_2D,\n *      - TRAP_UNDEF_GARP_2E,\n *      - TRAP_UNDEF_GARP_2F,\n *      - TRAP_CDP.\n *      - TRAP_CSSTP.\n *      - TRAP_LLDP.\n */\nrtk_api_ret_t rtk_trap_rmaKeepFormat_get(rtk_trap_type_t type, rtk_enable_t *pEnable)\n{\n    rtk_api_ret_t retVal;\n    rtl8367c_rma_t rmacfg;\n    rtk_uint32 tmp;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if (type >= TRAP_END)\n        return RT_ERR_INPUT;\n\n    if(NULL == pEnable)\n        return RT_ERR_NULL_POINTER;\n\n    if (type >= 0 && type <= TRAP_UNDEF_GARP_2F)\n    {\n        if ((retVal = rtl8367c_getAsicRma(type, &rmacfg)) != RT_ERR_OK)\n            return retVal;\n\n        *pEnable = rmacfg.keep_format;\n    }\n    else if (type == TRAP_CDP)\n    {\n        if ((retVal = rtl8367c_getAsicRmaCdp(&rmacfg)) != RT_ERR_OK)\n            return retVal;\n\n        *pEnable = rmacfg.keep_format;\n    }\n    else if (type == TRAP_CSSTP)\n    {\n        if ((retVal = rtl8367c_getAsicRmaCsstp(&rmacfg)) != RT_ERR_OK)\n            return retVal;\n\n        *pEnable = rmacfg.keep_format;\n    }\n    else if (type == TRAP_LLDP)\n    {\n        if ((retVal = rtl8367c_getAsicRmaLldp(&tmp,&rmacfg)) != RT_ERR_OK)\n            return retVal;\n\n        *pEnable = rmacfg.keep_format;\n    }\n    else\n        return RT_ERR_INPUT;\n\n    return RT_ERR_OK;\n}\n\n\n\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/trunk.c",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * $Revision: 76306 $\n * $Date: 2017-03-08 15:13:58 +0800 (週三, 08 三月 2017) $\n *\n * Purpose : RTK switch high-level API for RTL8367/RTL8367C\n * Feature : Here is a list of all functions and variables in Trunk module.\n *\n */\n\n#include <rtk_switch.h>\n#include <rtk_error.h>\n#include <trunk.h>\n#include <string.h>\n\n#include <rtl8367c_asicdrv.h>\n#include <rtl8367c_asicdrv_trunking.h>\n\n/* Function Name:\n *      rtk_trunk_port_set\n * Description:\n *      Set trunking group available port mask\n * Input:\n *      trk_gid                 - trunk group id\n *      pTrunk_member_portmask  - Logic trunking member port mask\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_LA_TRUNK_ID  - Invalid trunking group\n *      RT_ERR_PORT_MASK    - Invalid portmask.\n * Note:\n *      The API can set port trunking group port mask. Each port trunking group has max 4 ports.\n *      If enabled port mask has less than 2 ports available setting, then this trunking group function is disabled.\n */\nrtk_api_ret_t rtk_trunk_port_set(rtk_trunk_group_t trk_gid, rtk_portmask_t *pTrunk_member_portmask)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32 pmsk;\n    rtk_uint32 regValue, type, tmp;\n\n\n    if((retVal = rtl8367c_setAsicReg(0x13C2, 0x0249)) != RT_ERR_OK)\n        return retVal;\n\n    if((retVal = rtl8367c_getAsicReg(0x1300, &regValue)) != RT_ERR_OK)\n        return retVal;\n\n    if((retVal = rtl8367c_setAsicReg(0x13C2, 0x0000)) != RT_ERR_OK)\n        return retVal;\n\n    switch (regValue)\n    {\n        case 0x0276:\n        case 0x0597:\n        case 0x6367:\n            type = 0;\n            break;\n        case 0x0652:\n        case 0x6368:\n            type = 1;\n            break;\n        case 0x0801:\n        case 0x6511:\n            type = 2;\n            break;\n        default:\n            return RT_ERR_FAILED;\n    }\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check Trunk Group Valid */\n    RTK_CHK_TRUNK_GROUP_VALID(trk_gid);\n\n    if(NULL == pTrunk_member_portmask)\n        return RT_ERR_NULL_POINTER;\n\n    RTK_CHK_PORTMASK_VALID(pTrunk_member_portmask);\n\n    if((retVal = rtk_switch_portmask_L2P_get(pTrunk_member_portmask, &pmsk)) != RT_ERR_OK)\n        return retVal;\n\n    if((type == 0) || (type == 1))\n    {\n        if ((pmsk | RTL8367C_PORT_TRUNK_GROUP_MASK_MASK(trk_gid)) != (rtk_uint32)RTL8367C_PORT_TRUNK_GROUP_MASK_MASK(trk_gid))\n            return RT_ERR_PORT_MASK;\n\n        pmsk = (pmsk & RTL8367C_PORT_TRUNK_GROUP_MASK_MASK(trk_gid)) >> RTL8367C_PORT_TRUNK_GROUP_MASK_OFFSET(trk_gid);\n    }\n    else if(type == 2)\n    {\n        tmp = 0;\n\n        if(pmsk & 0x2)\n            tmp |= 1;\n        if(pmsk & 0x8)\n            tmp |=2;\n        if(pmsk & 0x80)\n            tmp |=8;\n\n        pmsk = tmp;\n    }\n\n    if ((retVal = rtl8367c_setAsicTrunkingGroup(trk_gid, pmsk)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_trunk_port_get\n * Description:\n *      Get trunking group available port mask\n * Input:\n *      trk_gid - trunk group id\n * Output:\n *      pTrunk_member_portmask - Logic trunking member port mask\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_LA_TRUNK_ID  - Invalid trunking group\n * Note:\n *      The API can get 2 port trunking group.\n */\nrtk_api_ret_t rtk_trunk_port_get(rtk_trunk_group_t trk_gid, rtk_portmask_t *pTrunk_member_portmask)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32 pmsk;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check Trunk Group Valid */\n    RTK_CHK_TRUNK_GROUP_VALID(trk_gid);\n\n    if ((retVal = rtl8367c_getAsicTrunkingGroup(trk_gid, &pmsk)) != RT_ERR_OK)\n        return retVal;\n\n    pmsk = pmsk << RTL8367C_PORT_TRUNK_GROUP_MASK_OFFSET(trk_gid);\n\n    if((retVal = rtk_switch_portmask_P2L_get(pmsk, pTrunk_member_portmask)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_trunk_distributionAlgorithm_set\n * Description:\n *      Set port trunking hash select sources\n * Input:\n *      trk_gid         - trunk group id\n *      algo_bitmask   - Bitmask of the distribution algorithm\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_LA_TRUNK_ID  - Invalid trunking group\n *      RT_ERR_LA_HASHMASK  - Hash algorithm selection error.\n *      RT_ERR_PORT_MASK    - Invalid portmask.\n * Note:\n *      The API can set port trunking hash algorithm sources.\n *      7 bits mask for link aggregation group0 hash parameter selection {DIP, SIP, DMAC, SMAC, SPA}\n *      - 0b0000001: SPA\n *      - 0b0000010: SMAC\n *      - 0b0000100: DMAC\n *      - 0b0001000: SIP\n *      - 0b0010000: DIP\n *      - 0b0100000: TCP/UDP Source Port\n *      - 0b1000000: TCP/UDP Destination Port\n *      Example:\n *      - 0b0000011: SMAC & SPA\n *      - Note that it could be an arbitrary combination or independent set\n */\nrtk_api_ret_t rtk_trunk_distributionAlgorithm_set(rtk_trunk_group_t trk_gid, rtk_uint32 algo_bitmask)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if (trk_gid != RTK_WHOLE_SYSTEM)\n        return RT_ERR_LA_TRUNK_ID;\n\n    if (algo_bitmask >= 128)\n        return RT_ERR_LA_HASHMASK;\n\n    if ((retVal = rtl8367c_setAsicTrunkingHashSelect(algo_bitmask)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_trunk_distributionAlgorithm_get\n * Description:\n *      Get port trunking hash select sources\n * Input:\n *      trk_gid - trunk group id\n * Output:\n *      pAlgo_bitmask -  Bitmask of the distribution algorithm\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_LA_TRUNK_ID  - Invalid trunking group\n * Note:\n *      The API can get port trunking hash algorithm sources.\n */\nrtk_api_ret_t rtk_trunk_distributionAlgorithm_get(rtk_trunk_group_t trk_gid, rtk_uint32 *pAlgo_bitmask)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if (trk_gid != RTK_WHOLE_SYSTEM)\n        return RT_ERR_LA_TRUNK_ID;\n\n    if(NULL == pAlgo_bitmask)\n        return RT_ERR_NULL_POINTER;\n\n    if ((retVal = rtl8367c_getAsicTrunkingHashSelect((rtk_uint32 *)pAlgo_bitmask)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_trunk_trafficSeparate_set\n * Description:\n *      Set the traffic separation setting of a trunk group from the specified device.\n * Input:\n *      trk_gid      - trunk group id\n *      separateType     - traffic separation setting\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n *      RT_ERR_UNIT_ID     - invalid unit id\n *      RT_ERR_LA_TRUNK_ID - invalid trunk ID\n *      RT_ERR_LA_HASHMASK - invalid hash mask\n * Note:\n *      SEPARATE_NONE: disable traffic separation\n *      SEPARATE_FLOOD: trunk MSB link up port is dedicated to TX flooding (L2 lookup miss) traffic\n */\nrtk_api_ret_t rtk_trunk_trafficSeparate_set(rtk_trunk_group_t trk_gid, rtk_trunk_separateType_t separateType)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32 enabled;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if (trk_gid != RTK_WHOLE_SYSTEM)\n        return RT_ERR_LA_TRUNK_ID;\n\n    if(separateType >= SEPARATE_END)\n        return RT_ERR_INPUT;\n\n    enabled = (separateType == SEPARATE_FLOOD) ? ENABLED : DISABLED;\n    if ((retVal = rtl8367c_setAsicTrunkingFlood(enabled)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_trunk_trafficSeparate_get\n * Description:\n *      Get the traffic separation setting of a trunk group from the specified device.\n * Input:\n *      trk_gid        - trunk group id\n * Output:\n *      pSeparateType   - pointer separated traffic type\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n *      RT_ERR_UNIT_ID      - invalid unit id\n *      RT_ERR_LA_TRUNK_ID  - invalid trunk ID\n *      RT_ERR_NULL_POINTER - input parameter may be null pointer\n * Note:\n *      SEPARATE_NONE: disable traffic separation\n *      SEPARATE_FLOOD: trunk MSB link up port is dedicated to TX flooding (L2 lookup miss) traffic\n */\nrtk_api_ret_t rtk_trunk_trafficSeparate_get(rtk_trunk_group_t trk_gid, rtk_trunk_separateType_t *pSeparateType)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32 enabled;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if (trk_gid != RTK_WHOLE_SYSTEM)\n        return RT_ERR_LA_TRUNK_ID;\n\n    if(NULL == pSeparateType)\n        return RT_ERR_NULL_POINTER;\n\n    if ((retVal = rtl8367c_getAsicTrunkingFlood(&enabled)) != RT_ERR_OK)\n        return retVal;\n\n    *pSeparateType = (enabled == ENABLED) ? SEPARATE_FLOOD : SEPARATE_NONE;\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_trunk_mode_set\n * Description:\n *      Set the trunk mode to the specified device.\n * Input:\n *      mode - trunk mode\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n *      RT_ERR_INPUT   - invalid input parameter\n * Note:\n *      The enum of the trunk mode as following\n *      - TRUNK_MODE_NORMAL\n *      - TRUNK_MODE_DUMB\n */\nrtk_api_ret_t rtk_trunk_mode_set(rtk_trunk_mode_t mode)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(mode >= TRUNK_MODE_END)\n        return RT_ERR_INPUT;\n\n    if ((retVal = rtl8367c_setAsicTrunkingMode((rtk_uint32)mode)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_trunk_mode_get\n * Description:\n *      Get the trunk mode from the specified device.\n * Input:\n *      None\n * Output:\n *      pMode - pointer buffer of trunk mode\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n *      RT_ERR_NULL_POINTER - input parameter may be null pointer\n * Note:\n *      The enum of the trunk mode as following\n *      - TRUNK_MODE_NORMAL\n *      - TRUNK_MODE_DUMB\n */\nrtk_api_ret_t rtk_trunk_mode_get(rtk_trunk_mode_t *pMode)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(NULL == pMode)\n        return RT_ERR_NULL_POINTER;\n\n    if ((retVal = rtl8367c_getAsicTrunkingMode((rtk_uint32 *)pMode)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_trunk_trafficPause_set\n * Description:\n *      Set the traffic pause setting of a trunk group.\n * Input:\n *      trk_gid      - trunk group id\n *      enable       - traffic pause state\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n *      RT_ERR_LA_TRUNK_ID - invalid trunk ID\n * Note:\n *      None.\n */\nrtk_api_ret_t rtk_trunk_trafficPause_set(rtk_trunk_group_t trk_gid, rtk_enable_t enable)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check Trunk Group Valid */\n    RTK_CHK_TRUNK_GROUP_VALID(trk_gid);\n\n    if(enable >= RTK_ENABLE_END)\n        return RT_ERR_INPUT;\n\n    if ((retVal = rtl8367c_setAsicTrunkingFc((rtk_uint32)trk_gid, (rtk_uint32)enable)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_trunk_trafficPause_get\n * Description:\n *      Get the traffic pause setting of a trunk group.\n * Input:\n *      trk_gid        - trunk group id\n * Output:\n *      pEnable        - pointer of traffic pause state.\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n *      RT_ERR_LA_TRUNK_ID  - invalid trunk ID\n *      RT_ERR_NULL_POINTER - input parameter may be null pointer\n * Note:\n *      None.\n */\nrtk_api_ret_t rtk_trunk_trafficPause_get(rtk_trunk_group_t trk_gid, rtk_enable_t *pEnable)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check Trunk Group Valid */\n    RTK_CHK_TRUNK_GROUP_VALID(trk_gid);\n\n    if(NULL == pEnable)\n        return RT_ERR_NULL_POINTER;\n\n    if ((retVal = rtl8367c_getAsicTrunkingFc((rtk_uint32)trk_gid, (rtk_uint32 *)pEnable)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_trunk_hashMappingTable_set\n * Description:\n *      Set hash value to port array in the trunk group id from the specified device.\n * Input:\n *      trk_gid          - trunk group id\n *      pHash2Port_array - ports associate with the hash value\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n *      RT_ERR_UNIT_ID            - invalid unit id\n *      RT_ERR_LA_TRUNK_ID        - invalid trunk ID\n *      RT_ERR_NULL_POINTER       - input parameter may be null pointer\n *      RT_ERR_LA_TRUNK_NOT_EXIST - the trunk doesn't exist\n *      RT_ERR_LA_NOT_MEMBER_PORT - the port is not a member port of the trunk\n *      RT_ERR_LA_CPUPORT         - CPU port can not be aggregated port\n * Note:\n *      Trunk group 0 & 1 shares the same hash mapping table.\n *      Trunk group 2 uses a independent table.\n */\nrtk_api_ret_t rtk_trunk_hashMappingTable_set(rtk_trunk_group_t trk_gid, rtk_trunk_hashVal2Port_t *pHash2Port_array)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32 hashValue;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check Trunk Group Valid */\n    RTK_CHK_TRUNK_GROUP_VALID(trk_gid);\n\n    if(NULL == pHash2Port_array)\n        return RT_ERR_NULL_POINTER;\n\n    if(trk_gid <= TRUNK_GROUP1)\n    {\n        for(hashValue = 0; hashValue < RTK_MAX_NUM_OF_TRUNK_HASH_VAL; hashValue++)\n        {\n            if ((retVal = rtl8367c_setAsicTrunkingHashTable(hashValue, pHash2Port_array->value[hashValue])) != RT_ERR_OK)\n                return retVal;\n        }\n    }\n    else\n    {\n        for(hashValue = 0; hashValue < RTK_MAX_NUM_OF_TRUNK_HASH_VAL; hashValue++)\n        {\n            if ((retVal = rtl8367c_setAsicTrunkingHashTable1(hashValue, pHash2Port_array->value[hashValue])) != RT_ERR_OK)\n                return retVal;\n        }\n    }\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_trunk_hashMappingTable_get\n * Description:\n *      Get hash value to port array in the trunk group id from the specified device.\n * Input:\n *      trk_gid          - trunk group id\n * Output:\n *      pHash2Port_array - pointer buffer of ports associate with the hash value\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n *      RT_ERR_UNIT_ID      - invalid unit id\n *      RT_ERR_LA_TRUNK_ID  - invalid trunk ID\n *      RT_ERR_NULL_POINTER - input parameter may be null pointer\n * Note:\n *      Trunk group 0 & 1 shares the same hash mapping table.\n *      Trunk group 2 uses a independent table.\n */\nrtk_api_ret_t rtk_trunk_hashMappingTable_get(rtk_trunk_group_t trk_gid, rtk_trunk_hashVal2Port_t *pHash2Port_array)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32 hashValue;\n    rtk_uint32 hashPort;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check Trunk Group Valid */\n    RTK_CHK_TRUNK_GROUP_VALID(trk_gid);\n\n    if(NULL == pHash2Port_array)\n        return RT_ERR_NULL_POINTER;\n\n    if(trk_gid <= TRUNK_GROUP1)\n    {\n        for(hashValue = 0; hashValue < RTK_MAX_NUM_OF_TRUNK_HASH_VAL; hashValue++)\n        {\n            if ((retVal = rtl8367c_getAsicTrunkingHashTable(hashValue, &hashPort)) != RT_ERR_OK)\n                return retVal;\n\n            pHash2Port_array->value[hashValue] = hashPort;\n        }\n    }\n    else\n    {\n        for(hashValue = 0; hashValue < RTK_MAX_NUM_OF_TRUNK_HASH_VAL; hashValue++)\n        {\n            if ((retVal = rtl8367c_getAsicTrunkingHashTable1(hashValue, &hashPort)) != RT_ERR_OK)\n                return retVal;\n\n            pHash2Port_array->value[hashValue] = hashPort;\n        }\n    }\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_trunk_portQueueEmpty_get\n * Description:\n *      Get the port mask which all queues are empty.\n * Input:\n *      None.\n * Output:\n *      pEmpty_portmask   - pointer empty port mask\n * Return:\n *      RT_ERR_OK\n *      RT_ERR_FAILED\n *      RT_ERR_NULL_POINTER - input parameter may be null pointer\n * Note:\n *      None.\n */\nrtk_api_ret_t rtk_trunk_portQueueEmpty_get(rtk_portmask_t *pEmpty_portmask)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32 pmask;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(NULL == pEmpty_portmask)\n        return RT_ERR_NULL_POINTER;\n\n    if ((retVal = rtl8367c_getAsicQeueuEmptyStatus(&pmask)) != RT_ERR_OK)\n        return retVal;\n\n    if ((retVal = rtk_switch_portmask_P2L_get(pmask, pEmpty_portmask)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367c/vlan.c",
    "content": "/*\n * Copyright (C) 2013 Realtek Semiconductor Corp.\n * All Rights Reserved.\n *\n * Unless you and Realtek execute a separate written software license\n * agreement governing use of this software, this software is licensed\n * to you under the terms of the GNU General Public License version 2,\n * available at https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt\n *\n * $Revision: 76306 $\n * $Date: 2017-03-08 15:13:58 +0800 (週三, 08 三月 2017) $\n *\n * Purpose : RTK switch high-level API for RTL8367/RTL8367C\n * Feature : Here is a list of all functions and variables in VLAN module.\n *\n */\n\n#include <rtk_switch.h>\n#include <rtk_error.h>\n#include <vlan.h>\n#include <rate.h>\n#include <string.h>\n\n#include <rtl8367c_asicdrv.h>\n#include <rtl8367c_asicdrv_vlan.h>\n#include <rtl8367c_asicdrv_dot1x.h>\n\ntypedef enum vlan_mbrCfgType_e\n{\n    MBRCFG_UNUSED = 0,\n    MBRCFG_USED_BY_VLAN,\n    MBRCFG_END\n}vlan_mbrCfgType_t;\n\nstatic rtk_vlan_t           vlan_mbrCfgVid[RTL8367C_CVIDXNO];\nstatic vlan_mbrCfgType_t    vlan_mbrCfgUsage[RTL8367C_CVIDXNO];\n\n/* Function Name:\n *      rtk_vlan_init\n * Description:\n *      Initialize VLAN.\n * Input:\n *      None\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n * Note:\n *      VLAN is disabled by default. User has to call this API to enable VLAN before\n *      using it. And It will set a default VLAN(vid 1) including all ports and set\n *      all ports PVID to the default VLAN.\n */\nrtk_api_ret_t rtk_vlan_init(void)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32 i;\n    rtl8367c_user_vlan4kentry vlan4K;\n    rtl8367c_vlanconfiguser vlanMC;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Clean Database */\n    memset(vlan_mbrCfgVid, 0x00, sizeof(rtk_vlan_t) * RTL8367C_CVIDXNO);\n    memset(vlan_mbrCfgUsage, 0x00, sizeof(vlan_mbrCfgType_t) * RTL8367C_CVIDXNO);\n\n    /* clean 32 VLAN member configuration */\n    for (i = 0; i <= RTL8367C_CVIDXMAX; i++)\n    {\n        vlanMC.evid = 0;\n        vlanMC.mbr = 0;\n        vlanMC.fid_msti = 0;\n        vlanMC.envlanpol = 0;\n        vlanMC.meteridx = 0;\n        vlanMC.vbpen = 0;\n        vlanMC.vbpri = 0;\n        if ((retVal = rtl8367c_setAsicVlanMemberConfig(i, &vlanMC)) != RT_ERR_OK)\n            return retVal;\n    }\n\n    /* Set a default VLAN with vid 1 to 4K table for all ports */\n    memset(&vlan4K, 0, sizeof(rtl8367c_user_vlan4kentry));\n    vlan4K.vid = 1;\n    vlan4K.mbr = RTK_PHY_PORTMASK_ALL;\n    vlan4K.untag = RTK_PHY_PORTMASK_ALL;\n    vlan4K.fid_msti = 0;\n    if ((retVal = rtl8367c_setAsicVlan4kEntry(&vlan4K)) != RT_ERR_OK)\n        return retVal;\n\n    /* Also set the default VLAN to 32 member configuration index 0 */\n    memset(&vlanMC, 0, sizeof(rtl8367c_vlanconfiguser));\n    vlanMC.evid = 1;\n    vlanMC.mbr = RTK_PHY_PORTMASK_ALL;\n    vlanMC.fid_msti = 0;\n    if ((retVal = rtl8367c_setAsicVlanMemberConfig(0, &vlanMC)) != RT_ERR_OK)\n            return retVal;\n\n    /* Set all ports PVID to default VLAN and tag-mode to original */\n    RTK_SCAN_ALL_PHY_PORTMASK(i)\n    {\n        if ((retVal = rtl8367c_setAsicVlanPortBasedVID(i, 0, 0)) != RT_ERR_OK)\n            return retVal;\n        if ((retVal = rtl8367c_setAsicVlanEgressTagMode(i, EG_TAG_MODE_ORI)) != RT_ERR_OK)\n            return retVal;\n    }\n\n    /* Updata Databse */\n    vlan_mbrCfgUsage[0] = MBRCFG_USED_BY_VLAN;\n    vlan_mbrCfgVid[0] = 1;\n\n    /* Enable Ingress filter */\n    RTK_SCAN_ALL_PHY_PORTMASK(i)\n    {\n        if ((retVal = rtl8367c_setAsicVlanIngressFilter(i, ENABLED)) != RT_ERR_OK)\n            return retVal;\n    }\n\n    /* enable VLAN */\n    if ((retVal = rtl8367c_setAsicVlanFilter(ENABLED)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_vlan_set\n * Description:\n *      Set a VLAN entry.\n * Input:\n *      vid - VLAN ID to configure.\n *      pVlanCfg - VLAN Configuration\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK                   - OK\n *      RT_ERR_FAILED               - Failed\n *      RT_ERR_SMI                  - SMI access error\n *      RT_ERR_INPUT                - Invalid input parameters.\n *      RT_ERR_L2_FID               - Invalid FID.\n *      RT_ERR_VLAN_PORT_MBR_EXIST  - Invalid member port mask.\n *      RT_ERR_VLAN_VID             - Invalid VID parameter.\n * Note:\n *\n */\nrtk_api_ret_t rtk_vlan_set(rtk_vlan_t vid, rtk_vlan_cfg_t *pVlanCfg)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32 phyMbrPmask;\n    rtk_uint32 phyUntagPmask;\n    rtl8367c_user_vlan4kentry vlan4K;\n    rtl8367c_vlanconfiguser vlanMC;\n    rtk_uint32 idx;\n    rtk_uint32 empty_index = 0xffff;\n    rtk_uint32 update_evid = 0;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* vid must be 0~8191 */\n    if (vid > RTL8367C_EVIDMAX)\n        return RT_ERR_VLAN_VID;\n\n    /* Null pointer check */\n    if(NULL == pVlanCfg)\n        return RT_ERR_NULL_POINTER;\n\n    /* Check port mask valid */\n    RTK_CHK_PORTMASK_VALID(&(pVlanCfg->mbr));\n\n    if (vid <= RTL8367C_VIDMAX)\n    {\n        /* Check untag port mask valid */\n        RTK_CHK_PORTMASK_VALID(&(pVlanCfg->untag));\n    }\n\n    /* IVL_EN */\n    if(pVlanCfg->ivl_en >= RTK_ENABLE_END)\n        return RT_ERR_ENABLE;\n\n    /* fid must be 0~15 */\n    if(pVlanCfg->fid_msti > RTL8367C_FIDMAX)\n        return RT_ERR_L2_FID;\n\n    /* Policing */\n    if(pVlanCfg->envlanpol >= RTK_ENABLE_END)\n        return RT_ERR_ENABLE;\n\n    /* Meter ID */\n    if(pVlanCfg->meteridx > RTK_MAX_METER_ID)\n        return RT_ERR_INPUT;\n\n    /* VLAN based priority */\n    if(pVlanCfg->vbpen >= RTK_ENABLE_END)\n        return RT_ERR_ENABLE;\n\n    /* Priority */\n    if(pVlanCfg->vbpri > RTL8367C_PRIMAX)\n        return RT_ERR_INPUT;\n\n    /* Get physical port mask */\n    if(rtk_switch_portmask_L2P_get(&(pVlanCfg->mbr), &phyMbrPmask) != RT_ERR_OK)\n        return RT_ERR_FAILED;\n\n    if(rtk_switch_portmask_L2P_get(&(pVlanCfg->untag), &phyUntagPmask) != RT_ERR_OK)\n        return RT_ERR_FAILED;\n\n    if (vid <= RTL8367C_VIDMAX)\n    {\n        /* update 4K table */\n        memset(&vlan4K, 0, sizeof(rtl8367c_user_vlan4kentry));\n        vlan4K.vid = vid;\n\n        vlan4K.mbr    = (phyMbrPmask & 0xFFFF);\n        vlan4K.untag  = (phyUntagPmask & 0xFFFF);\n\n        vlan4K.ivl_svl      = pVlanCfg->ivl_en;\n        vlan4K.fid_msti     = pVlanCfg->fid_msti;\n        vlan4K.envlanpol    = pVlanCfg->envlanpol;\n        vlan4K.meteridx     = pVlanCfg->meteridx;\n        vlan4K.vbpen        = pVlanCfg->vbpen;\n        vlan4K.vbpri        = pVlanCfg->vbpri;\n\n        if ((retVal = rtl8367c_setAsicVlan4kEntry(&vlan4K)) != RT_ERR_OK)\n            return retVal;\n\n        /* Update Member configuration if exist */\n        for (idx = 0; idx <= RTL8367C_CVIDXMAX; idx++)\n        {\n            if(vlan_mbrCfgUsage[idx] == MBRCFG_USED_BY_VLAN)\n            {\n                if(vlan_mbrCfgVid[idx] == vid)\n                {\n                    /* Found! Update */\n                    if(phyMbrPmask == 0x00)\n                    {\n                        /* Member port = 0x00, delete this VLAN from Member Configuration */\n                        memset(&vlanMC, 0x00, sizeof(rtl8367c_vlanconfiguser));\n                        if ((retVal = rtl8367c_setAsicVlanMemberConfig(idx, &vlanMC)) != RT_ERR_OK)\n                            return retVal;\n\n                        /* Clear Database */\n                        vlan_mbrCfgUsage[idx] = MBRCFG_UNUSED;\n                        vlan_mbrCfgVid[idx]   = 0;\n                    }\n                    else\n                    {\n                        /* Normal VLAN config, update to member configuration */\n                        vlanMC.evid = vid;\n                        vlanMC.mbr = vlan4K.mbr;\n                        vlanMC.fid_msti = vlan4K.fid_msti;\n                        vlanMC.meteridx = vlan4K.meteridx;\n                        vlanMC.envlanpol= vlan4K.envlanpol;\n                        vlanMC.vbpen = vlan4K.vbpen;\n                        vlanMC.vbpri = vlan4K.vbpri;\n                        if ((retVal = rtl8367c_setAsicVlanMemberConfig(idx, &vlanMC)) != RT_ERR_OK)\n                            return retVal;\n                    }\n\n                    break;\n                }\n            }\n        }\n    }\n    else\n    {\n        /* vid > 4095 */\n        for (idx = 0; idx <= RTL8367C_CVIDXMAX; idx++)\n        {\n            if(vlan_mbrCfgUsage[idx] == MBRCFG_USED_BY_VLAN)\n            {\n                if(vlan_mbrCfgVid[idx] == vid)\n                {\n                    /* Found! Update */\n                    if(phyMbrPmask == 0x00)\n                    {\n                        /* Member port = 0x00, delete this VLAN from Member Configuration */\n                        memset(&vlanMC, 0x00, sizeof(rtl8367c_vlanconfiguser));\n                        if ((retVal = rtl8367c_setAsicVlanMemberConfig(idx, &vlanMC)) != RT_ERR_OK)\n                            return retVal;\n\n                        /* Clear Database */\n                        vlan_mbrCfgUsage[idx] = MBRCFG_UNUSED;\n                        vlan_mbrCfgVid[idx]   = 0;\n                    }\n                    else\n                    {\n                        /* Normal VLAN config, update to member configuration */\n                        vlanMC.evid = vid;\n                        vlanMC.mbr = phyMbrPmask;\n                        vlanMC.fid_msti = pVlanCfg->fid_msti;\n                        vlanMC.meteridx = pVlanCfg->meteridx;\n                        vlanMC.envlanpol= pVlanCfg->envlanpol;\n                        vlanMC.vbpen = pVlanCfg->vbpen;\n                        vlanMC.vbpri = pVlanCfg->vbpri;\n                        if ((retVal = rtl8367c_setAsicVlanMemberConfig(idx, &vlanMC)) != RT_ERR_OK)\n                            return retVal;\n\n                        break;\n                    }\n\n                    update_evid = 1;\n                }\n            }\n\n            if(vlan_mbrCfgUsage[idx] == MBRCFG_UNUSED)\n            {\n                if(0xffff == empty_index)\n                    empty_index = idx;\n            }\n        }\n\n        /* doesn't find out same EVID entry and there is empty index in member configuration */\n        if( (phyMbrPmask != 0x00) && (update_evid == 0) && (empty_index != 0xFFFF) )\n        {\n            vlanMC.evid = vid;\n            vlanMC.mbr = phyMbrPmask;\n            vlanMC.fid_msti = pVlanCfg->fid_msti;\n            vlanMC.meteridx = pVlanCfg->meteridx;\n            vlanMC.envlanpol= pVlanCfg->envlanpol;\n            vlanMC.vbpen = pVlanCfg->vbpen;\n            vlanMC.vbpri = pVlanCfg->vbpri;\n            if ((retVal = rtl8367c_setAsicVlanMemberConfig(empty_index, &vlanMC)) != RT_ERR_OK)\n                return retVal;\n\n            vlan_mbrCfgUsage[empty_index] = MBRCFG_USED_BY_VLAN;\n            vlan_mbrCfgVid[empty_index] = vid;\n\n        }\n    }\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_vlan_get\n * Description:\n *      Get a VLAN entry.\n * Input:\n *      vid - VLAN ID to configure.\n * Output:\n *      pVlanCfg - VLAN Configuration\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n *      RT_ERR_VLAN_VID     - Invalid VID parameter.\n * Note:\n *\n */\nrtk_api_ret_t rtk_vlan_get(rtk_vlan_t vid, rtk_vlan_cfg_t *pVlanCfg)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32 phyMbrPmask;\n    rtk_uint32 phyUntagPmask;\n    rtl8367c_user_vlan4kentry vlan4K;\n    rtl8367c_vlanconfiguser vlanMC;\n    rtk_uint32 idx;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* vid must be 0~8191 */\n    if (vid > RTL8367C_EVIDMAX)\n        return RT_ERR_VLAN_VID;\n\n    /* Null pointer check */\n    if(NULL == pVlanCfg)\n        return RT_ERR_NULL_POINTER;\n\n    if (vid <= RTL8367C_VIDMAX)\n    {\n        vlan4K.vid = vid;\n\n        if ((retVal = rtl8367c_getAsicVlan4kEntry(&vlan4K)) != RT_ERR_OK)\n            return retVal;\n\n        phyMbrPmask   = vlan4K.mbr;\n        phyUntagPmask = vlan4K.untag;\n        if(rtk_switch_portmask_P2L_get(phyMbrPmask, &(pVlanCfg->mbr)) != RT_ERR_OK)\n            return RT_ERR_FAILED;\n\n        if(rtk_switch_portmask_P2L_get(phyUntagPmask, &(pVlanCfg->untag)) != RT_ERR_OK)\n            return RT_ERR_FAILED;\n\n        pVlanCfg->ivl_en    = vlan4K.ivl_svl;\n        pVlanCfg->fid_msti  = vlan4K.fid_msti;\n        pVlanCfg->envlanpol = vlan4K.envlanpol;\n        pVlanCfg->meteridx  = vlan4K.meteridx;\n        pVlanCfg->vbpen     = vlan4K.vbpen;\n        pVlanCfg->vbpri     = vlan4K.vbpri;\n    }\n    else\n    {\n        for (idx = 0; idx <= RTL8367C_CVIDXMAX; idx++)\n        {\n            if(vlan_mbrCfgUsage[idx] == MBRCFG_USED_BY_VLAN)\n            {\n                if(vlan_mbrCfgVid[idx] == vid)\n                {\n                    if ((retVal = rtl8367c_getAsicVlanMemberConfig(idx, &vlanMC)) != RT_ERR_OK)\n                        return retVal;\n\n                    phyMbrPmask   = vlanMC.mbr;\n                    if(rtk_switch_portmask_P2L_get(phyMbrPmask, &(pVlanCfg->mbr)) != RT_ERR_OK)\n                        return RT_ERR_FAILED;\n\n                    pVlanCfg->untag.bits[0] = 0;\n                    pVlanCfg->ivl_en    = 0;\n                    pVlanCfg->fid_msti  = vlanMC.fid_msti;\n                    pVlanCfg->envlanpol = vlanMC.envlanpol;\n                    pVlanCfg->meteridx  = vlanMC.meteridx;\n                    pVlanCfg->vbpen     = vlanMC.vbpen;\n                    pVlanCfg->vbpri     = vlanMC.vbpri;\n                }\n            }\n        }\n    }\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_vlan_egrFilterEnable_set\n * Description:\n *      Set VLAN egress filter.\n * Input:\n *      egrFilter - Egress filtering\n * Output:\n *      None.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_ENABLE       - Invalid input parameters.\n * Note:\n *\n */\nrtk_api_ret_t rtk_vlan_egrFilterEnable_set(rtk_enable_t egrFilter)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(egrFilter >= RTK_ENABLE_END)\n        return RT_ERR_ENABLE;\n\n    /* enable VLAN */\n    if ((retVal = rtl8367c_setAsicVlanFilter((rtk_uint32)egrFilter)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_vlan_egrFilterEnable_get\n * Description:\n *      Get VLAN egress filter.\n * Input:\n *      pEgrFilter - Egress filtering\n * Output:\n *      None.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_NULL_POINTER - NULL Pointer.\n * Note:\n *\n */\nrtk_api_ret_t rtk_vlan_egrFilterEnable_get(rtk_enable_t *pEgrFilter)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32 state;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(NULL == pEgrFilter)\n        return RT_ERR_NULL_POINTER;\n\n    /* enable VLAN */\n    if ((retVal = rtl8367c_getAsicVlanFilter(&state)) != RT_ERR_OK)\n        return retVal;\n\n    *pEgrFilter = (rtk_enable_t)state;\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_vlan_mbrCfg_set\n * Description:\n *      Set a VLAN Member Configuration entry by index.\n * Input:\n *      idx     - Index of VLAN Member Configuration.\n *      pMbrcfg - VLAN member Configuration.\n * Output:\n *      None.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n *      RT_ERR_VLAN_VID     - Invalid VID parameter.\n * Note:\n *     Set a VLAN Member Configuration entry by index.\n */\nrtk_api_ret_t rtk_vlan_mbrCfg_set(rtk_uint32 idx, rtk_vlan_mbrcfg_t *pMbrcfg)\n{\n    rtk_api_ret_t           retVal;\n    rtk_uint32              phyMbrPmask;\n    rtl8367c_vlanconfiguser mbrCfg;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Error check */\n    if(pMbrcfg == NULL)\n        return RT_ERR_NULL_POINTER;\n\n    if(idx > RTL8367C_CVIDXMAX)\n        return RT_ERR_INPUT;\n\n    if(pMbrcfg->evid > RTL8367C_EVIDMAX)\n        return RT_ERR_INPUT;\n\n    if(pMbrcfg->fid_msti > RTL8367C_FIDMAX)\n        return RT_ERR_L2_FID;\n\n    if(pMbrcfg->envlanpol >= RTK_ENABLE_END)\n        return RT_ERR_ENABLE;\n\n    if(pMbrcfg->meteridx > RTK_MAX_METER_ID)\n        return RT_ERR_FILTER_METER_ID;\n\n    if(pMbrcfg->vbpen >= RTK_ENABLE_END)\n        return RT_ERR_ENABLE;\n\n    if(pMbrcfg->vbpri > RTL8367C_PRIMAX)\n        return RT_ERR_QOS_INT_PRIORITY;\n\n    /* Check port mask valid */\n    RTK_CHK_PORTMASK_VALID(&(pMbrcfg->mbr));\n\n    mbrCfg.evid         = pMbrcfg->evid;\n    mbrCfg.fid_msti     = pMbrcfg->fid_msti;\n    mbrCfg.envlanpol    = pMbrcfg->envlanpol;\n    mbrCfg.meteridx     = pMbrcfg->meteridx;\n    mbrCfg.vbpen        = pMbrcfg->vbpen;\n    mbrCfg.vbpri        = pMbrcfg->vbpri;\n\n    if(rtk_switch_portmask_L2P_get(&(pMbrcfg->mbr), &phyMbrPmask) != RT_ERR_OK)\n        return RT_ERR_FAILED;\n\n    mbrCfg.mbr = phyMbrPmask;\n\n    if ((retVal = rtl8367c_setAsicVlanMemberConfig(idx, &mbrCfg)) != RT_ERR_OK)\n        return retVal;\n\n    /* Update Database */\n    if( (mbrCfg.evid == 0) && (mbrCfg.mbr == 0) )\n    {\n        vlan_mbrCfgUsage[idx] = MBRCFG_UNUSED;\n        vlan_mbrCfgVid[idx] = 0;\n    }\n    else\n    {\n        vlan_mbrCfgUsage[idx] = MBRCFG_USED_BY_VLAN;\n        vlan_mbrCfgVid[idx] = mbrCfg.evid;\n    }\n\n    return RT_ERR_OK;\n\n}\n\n/* Function Name:\n *      rtk_vlan_mbrCfg_get\n * Description:\n *      Get a VLAN Member Configuration entry by index.\n * Input:\n *      idx - Index of VLAN Member Configuration.\n * Output:\n *      pMbrcfg - VLAN member Configuration.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n *      RT_ERR_VLAN_VID     - Invalid VID parameter.\n * Note:\n *     Get a VLAN Member Configuration entry by index.\n */\nrtk_api_ret_t rtk_vlan_mbrCfg_get(rtk_uint32 idx, rtk_vlan_mbrcfg_t *pMbrcfg)\n{\n    rtk_api_ret_t           retVal;\n    rtk_uint32              phyMbrPmask;\n    rtl8367c_vlanconfiguser mbrCfg;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Error check */\n    if(pMbrcfg == NULL)\n        return RT_ERR_NULL_POINTER;\n\n    if(idx > RTL8367C_CVIDXMAX)\n        return RT_ERR_INPUT;\n\n    memset(&mbrCfg, 0x00, sizeof(rtl8367c_vlanconfiguser));\n    if ((retVal = rtl8367c_getAsicVlanMemberConfig(idx, &mbrCfg)) != RT_ERR_OK)\n        return retVal;\n\n    pMbrcfg->evid       = mbrCfg.evid;\n    pMbrcfg->fid_msti   = mbrCfg.fid_msti;\n    pMbrcfg->envlanpol  = mbrCfg.envlanpol;\n    pMbrcfg->meteridx   = mbrCfg.meteridx;\n    pMbrcfg->vbpen      = mbrCfg.vbpen;\n    pMbrcfg->vbpri      = mbrCfg.vbpri;\n\n    phyMbrPmask = mbrCfg.mbr;\n    if(rtk_switch_portmask_P2L_get(phyMbrPmask, &(pMbrcfg->mbr)) != RT_ERR_OK)\n        return RT_ERR_FAILED;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *     rtk_vlan_portPvid_set\n * Description:\n *      Set port to specified VLAN ID(PVID).\n * Input:\n *      port - Port id.\n *      pvid - Specified VLAN ID.\n *      priority - 802.1p priority for the PVID.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK                   - OK\n *      RT_ERR_FAILED               - Failed\n *      RT_ERR_SMI                  - SMI access error\n *      RT_ERR_PORT_ID              - Invalid port number.\n *      RT_ERR_VLAN_PRIORITY        - Invalid priority.\n *      RT_ERR_VLAN_ENTRY_NOT_FOUND - VLAN entry not found.\n *      RT_ERR_VLAN_VID             - Invalid VID parameter.\n * Note:\n *       The API is used for Port-based VLAN. The untagged frame received from the\n *       port will be classified to the specified VLAN and assigned to the specified priority.\n */\nrtk_api_ret_t rtk_vlan_portPvid_set(rtk_port_t port, rtk_vlan_t pvid, rtk_pri_t priority)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32 index;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check Port Valid */\n    RTK_CHK_PORT_VALID(port);\n\n    /* vid must be 0~8191 */\n    if (pvid > RTL8367C_EVIDMAX)\n        return RT_ERR_VLAN_VID;\n\n    /* priority must be 0~7 */\n    if (priority > RTL8367C_PRIMAX)\n        return RT_ERR_VLAN_PRIORITY;\n\n    if((retVal = rtk_vlan_checkAndCreateMbr(pvid, &index)) != RT_ERR_OK)\n        return retVal;\n\n    if ((retVal = rtl8367c_setAsicVlanPortBasedVID(rtk_switch_port_L2P_get(port), index, priority)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_vlan_portPvid_get\n * Description:\n *      Get VLAN ID(PVID) on specified port.\n * Input:\n *      port - Port id.\n * Output:\n *      pPvid - Specified VLAN ID.\n *      pPriority - 802.1p priority for the PVID.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n *      RT_ERR_PORT_ID      - Invalid port number.\n * Note:\n *     The API can get the PVID and 802.1p priority for the PVID of Port-based VLAN.\n */\nrtk_api_ret_t rtk_vlan_portPvid_get(rtk_port_t port, rtk_vlan_t *pPvid, rtk_pri_t *pPriority)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32 index, pri;\n    rtl8367c_vlanconfiguser mbrCfg;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check Port Valid */\n    RTK_CHK_PORT_VALID(port);\n\n    if(NULL == pPvid)\n        return RT_ERR_NULL_POINTER;\n\n    if(NULL == pPriority)\n        return RT_ERR_NULL_POINTER;\n\n    if ((retVal = rtl8367c_getAsicVlanPortBasedVID(rtk_switch_port_L2P_get(port), &index, &pri)) != RT_ERR_OK)\n        return retVal;\n\n    memset(&mbrCfg, 0x00, sizeof(rtl8367c_vlanconfiguser));\n    if ((retVal = rtl8367c_getAsicVlanMemberConfig(index, &mbrCfg)) != RT_ERR_OK)\n        return retVal;\n\n    *pPvid = mbrCfg.evid;\n    *pPriority = pri;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_vlan_portIgrFilterEnable_set\n * Description:\n *      Set VLAN ingress for each port.\n * Input:\n *      port - Port id.\n *      igr_filter - VLAN ingress function enable status.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number\n *      RT_ERR_ENABLE       - Invalid enable input\n * Note:\n *      The status of vlan ingress filter is as following:\n *      - DISABLED\n *      - ENABLED\n *      While VLAN function is enabled, ASIC will decide VLAN ID for each received frame and get belonged member\n *      ports from VLAN table. If received port is not belonged to VLAN member ports, ASIC will drop received frame if VLAN ingress function is enabled.\n */\nrtk_api_ret_t rtk_vlan_portIgrFilterEnable_set(rtk_port_t port, rtk_enable_t igr_filter)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check Port Valid */\n    RTK_CHK_PORT_VALID(port);\n\n    if (igr_filter >= RTK_ENABLE_END)\n        return RT_ERR_ENABLE;\n\n    if ((retVal = rtl8367c_setAsicVlanIngressFilter(rtk_switch_port_L2P_get(port), igr_filter)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_vlan_portIgrFilterEnable_get\n * Description:\n *      Get VLAN Ingress Filter\n * Input:\n *      port        - Port id.\n * Output:\n *      pIgr_filter - VLAN ingress function enable status.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n *      RT_ERR_PORT_ID      - Invalid port number.\n * Note:\n *     The API can Get the VLAN ingress filter status.\n *     The status of vlan ingress filter is as following:\n *     - DISABLED\n *     - ENABLED\n */\nrtk_api_ret_t rtk_vlan_portIgrFilterEnable_get(rtk_port_t port, rtk_enable_t *pIgr_filter)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check Port Valid */\n    RTK_CHK_PORT_VALID(port);\n\n    if(NULL == pIgr_filter)\n        return RT_ERR_NULL_POINTER;\n\n    if ((retVal = rtl8367c_getAsicVlanIngressFilter(rtk_switch_port_L2P_get(port), pIgr_filter)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_vlan_portAcceptFrameType_set\n * Description:\n *      Set VLAN accept_frame_type\n * Input:\n *      port                - Port id.\n *      accept_frame_type   - accept frame type\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK                       - OK\n *      RT_ERR_FAILED                   - Failed\n *      RT_ERR_SMI                      - SMI access error\n *      RT_ERR_PORT_ID                  - Invalid port number.\n *      RT_ERR_VLAN_ACCEPT_FRAME_TYPE   - Invalid frame type.\n * Note:\n *      The API is used for checking 802.1Q tagged frames.\n *      The accept frame type as following:\n *      - ACCEPT_FRAME_TYPE_ALL\n *      - ACCEPT_FRAME_TYPE_TAG_ONLY\n *      - ACCEPT_FRAME_TYPE_UNTAG_ONLY\n */\nrtk_api_ret_t rtk_vlan_portAcceptFrameType_set(rtk_port_t port, rtk_vlan_acceptFrameType_t accept_frame_type)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check Port Valid */\n    RTK_CHK_PORT_VALID(port);\n\n    if (accept_frame_type >= ACCEPT_FRAME_TYPE_END)\n        return RT_ERR_VLAN_ACCEPT_FRAME_TYPE;\n\n    if ((retVal = rtl8367c_setAsicVlanAccpetFrameType(rtk_switch_port_L2P_get(port), (rtl8367c_accframetype)accept_frame_type)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_vlan_portAcceptFrameType_get\n * Description:\n *      Get VLAN accept_frame_type\n * Input:\n *      port - Port id.\n * Output:\n *      pAccept_frame_type - accept frame type\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n *      RT_ERR_PORT_ID      - Invalid port number.\n * Note:\n *     The API can Get the VLAN ingress filter.\n *     The accept frame type as following:\n *     - ACCEPT_FRAME_TYPE_ALL\n *     - ACCEPT_FRAME_TYPE_TAG_ONLY\n *     - ACCEPT_FRAME_TYPE_UNTAG_ONLY\n */\nrtk_api_ret_t rtk_vlan_portAcceptFrameType_get(rtk_port_t port, rtk_vlan_acceptFrameType_t *pAccept_frame_type)\n{\n    rtk_api_ret_t retVal;\n    rtl8367c_accframetype   acc_frm_type;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check Port Valid */\n    RTK_CHK_PORT_VALID(port);\n\n    if(NULL == pAccept_frame_type)\n        return RT_ERR_NULL_POINTER;\n\n    if ((retVal = rtl8367c_getAsicVlanAccpetFrameType(rtk_switch_port_L2P_get(port), &acc_frm_type)) != RT_ERR_OK)\n        return retVal;\n\n    *pAccept_frame_type = (rtk_vlan_acceptFrameType_t)acc_frm_type;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_vlan_protoAndPortBasedVlan_add\n * Description:\n *      Add the protocol-and-port-based vlan to the specified port of device.\n * Input:\n *      port  - Port id.\n *      pInfo - Protocol and port based VLAN configuration information.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - OK\n *      RT_ERR_FAILED           - Failed\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_PORT_ID          - Invalid port number.\n *      RT_ERR_VLAN_VID         - Invalid VID parameter.\n *      RT_ERR_VLAN_PRIORITY    - Invalid priority.\n *      RT_ERR_TBL_FULL         - Table is full.\n *      RT_ERR_OUT_OF_RANGE     - input out of range.\n * Note:\n *      The incoming packet which match the protocol-and-port-based vlan will use the configure vid for ingress pipeline\n *      The frame type is shown in the following:\n *      - FRAME_TYPE_ETHERNET\n *      - FRAME_TYPE_RFC1042\n *      - FRAME_TYPE_LLCOTHER\n */\nrtk_api_ret_t rtk_vlan_protoAndPortBasedVlan_add(rtk_port_t port, rtk_vlan_protoAndPortInfo_t *pInfo)\n{\n    rtk_api_ret_t retVal, i;\n    rtk_uint32 exist, empty, used, index;\n    rtl8367c_protocolgdatacfg ppb_data_cfg;\n    rtl8367c_protocolvlancfg ppb_vlan_cfg;\n    rtl8367c_provlan_frametype tmp;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check Port Valid */\n    RTK_CHK_PORT_VALID(port);\n\n    if(NULL == pInfo)\n        return RT_ERR_NULL_POINTER;\n\n    if (pInfo->proto_type > RTK_MAX_NUM_OF_PROTO_TYPE)\n        return RT_ERR_OUT_OF_RANGE;\n\n    if (pInfo->frame_type >= FRAME_TYPE_END)\n        return RT_ERR_OUT_OF_RANGE;\n\n    if (pInfo->cvid > RTL8367C_VIDMAX)\n        return RT_ERR_VLAN_VID;\n\n    if (pInfo->cpri > RTL8367C_PRIMAX)\n        return RT_ERR_VLAN_PRIORITY;\n\n    exist = 0xFF;\n    empty = 0xFF;\n    for (i = RTL8367C_PROTOVLAN_GIDX_MAX; i >= 0; i--)\n    {\n        if ((retVal = rtl8367c_getAsicVlanProtocolBasedGroupData(i, &ppb_data_cfg)) != RT_ERR_OK)\n            return retVal;\n        tmp = pInfo->frame_type;\n        if (ppb_data_cfg.etherType == pInfo->proto_type && ppb_data_cfg.frameType == tmp)\n        {\n            /*Already exist*/\n            exist = i;\n            break;\n        }\n        else if (ppb_data_cfg.etherType == 0 && ppb_data_cfg.frameType == 0)\n        {\n            /*find empty index*/\n            empty = i;\n        }\n    }\n\n    used = 0xFF;\n    /*No empty and exist index*/\n    if (0xFF == exist && 0xFF == empty)\n        return RT_ERR_TBL_FULL;\n    else if (exist<RTL8367C_PROTOVLAN_GROUPNO)\n    {\n       /*exist index*/\n       used = exist;\n    }\n    else if (empty<RTL8367C_PROTOVLAN_GROUPNO)\n    {\n        /*No exist index, but have empty index*/\n        ppb_data_cfg.frameType = pInfo->frame_type;\n        ppb_data_cfg.etherType = pInfo->proto_type;\n        if ((retVal = rtl8367c_setAsicVlanProtocolBasedGroupData(empty, &ppb_data_cfg)) != RT_ERR_OK)\n            return retVal;\n        used = empty;\n    }\n    else\n        return RT_ERR_FAILED;\n\n    if((retVal = rtk_vlan_checkAndCreateMbr(pInfo->cvid, &index)) != RT_ERR_OK)\n        return retVal;\n\n    ppb_vlan_cfg.vlan_idx = index;\n    ppb_vlan_cfg.valid = TRUE;\n    ppb_vlan_cfg.priority = pInfo->cpri;\n    if ((retVal = rtl8367c_setAsicVlanPortAndProtocolBased(rtk_switch_port_L2P_get(port), used, &ppb_vlan_cfg)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_vlan_protoAndPortBasedVlan_get\n * Description:\n *      Get the protocol-and-port-based vlan to the specified port of device.\n * Input:\n *      port - Port id.\n *      proto_type - protocol-and-port-based vlan protocol type.\n *      frame_type - protocol-and-port-based vlan frame type.\n * Output:\n *      pInfo - Protocol and port based VLAN configuration information.\n * Return:\n *      RT_ERR_OK               - OK\n *      RT_ERR_FAILED           - Failed\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_PORT_ID          - Invalid port number.\n *      RT_ERR_OUT_OF_RANGE     - input out of range.\n *      RT_ERR_TBL_FULL         - Table is full.\n * Note:\n *     The incoming packet which match the protocol-and-port-based vlan will use the configure vid for ingress pipeline\n *     The frame type is shown in the following:\n *      - FRAME_TYPE_ETHERNET\n *      - FRAME_TYPE_RFC1042\n *      - FRAME_TYPE_LLCOTHER\n */\nrtk_api_ret_t rtk_vlan_protoAndPortBasedVlan_get(rtk_port_t port, rtk_vlan_proto_type_t proto_type, rtk_vlan_protoVlan_frameType_t frame_type, rtk_vlan_protoAndPortInfo_t *pInfo)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32 i;\n    rtk_uint32 ppb_idx;\n    rtl8367c_protocolgdatacfg ppb_data_cfg;\n    rtl8367c_protocolvlancfg ppb_vlan_cfg;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check Port Valid */\n    RTK_CHK_PORT_VALID(port);\n\n    if (proto_type > RTK_MAX_NUM_OF_PROTO_TYPE)\n        return RT_ERR_OUT_OF_RANGE;\n\n    if (frame_type >= FRAME_TYPE_END)\n        return RT_ERR_OUT_OF_RANGE;\n\n   ppb_idx = 0;\n\n    for (i = 0; i<= RTL8367C_PROTOVLAN_GIDX_MAX; i++)\n    {\n        if ((retVal = rtl8367c_getAsicVlanProtocolBasedGroupData(i, &ppb_data_cfg)) != RT_ERR_OK)\n            return retVal;\n\n        if ( (ppb_data_cfg.frameType == (rtl8367c_provlan_frametype)frame_type) && (ppb_data_cfg.etherType == proto_type) )\n        {\n            ppb_idx = i;\n            break;\n        }\n        else if (RTL8367C_PROTOVLAN_GIDX_MAX == i)\n            return RT_ERR_TBL_FULL;\n    }\n\n    if ((retVal = rtl8367c_getAsicVlanPortAndProtocolBased(rtk_switch_port_L2P_get(port), ppb_idx, &ppb_vlan_cfg)) != RT_ERR_OK)\n        return retVal;\n\n    if (FALSE == ppb_vlan_cfg.valid)\n        return RT_ERR_FAILED;\n\n    pInfo->frame_type = frame_type;\n    pInfo->proto_type = proto_type;\n    pInfo->cvid = vlan_mbrCfgVid[ppb_vlan_cfg.vlan_idx];\n    pInfo->cpri = ppb_vlan_cfg.priority;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_vlan_protoAndPortBasedVlan_del\n * Description:\n *      Delete the protocol-and-port-based vlan from the specified port of device.\n * Input:\n *      port        - Port id.\n *      proto_type  - protocol-and-port-based vlan protocol type.\n *      frame_type  - protocol-and-port-based vlan frame type.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - OK\n *      RT_ERR_FAILED           - Failed\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_PORT_ID          - Invalid port number.\n *      RT_ERR_OUT_OF_RANGE     - input out of range.\n *      RT_ERR_TBL_FULL         - Table is full.\n * Note:\n *     The incoming packet which match the protocol-and-port-based vlan will use the configure vid for ingress pipeline\n *     The frame type is shown in the following:\n *      - FRAME_TYPE_ETHERNET\n *      - FRAME_TYPE_RFC1042\n *      - FRAME_TYPE_LLCOTHER\n */\nrtk_api_ret_t rtk_vlan_protoAndPortBasedVlan_del(rtk_port_t port, rtk_vlan_proto_type_t proto_type, rtk_vlan_protoVlan_frameType_t frame_type)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32 i, bUsed;\n    rtk_uint32 ppb_idx;\n    rtl8367c_protocolgdatacfg ppb_data_cfg;\n    rtl8367c_protocolvlancfg ppb_vlan_cfg;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check Port Valid */\n    RTK_CHK_PORT_VALID(port);\n\n    if (proto_type > RTK_MAX_NUM_OF_PROTO_TYPE)\n        return RT_ERR_OUT_OF_RANGE;\n\n    if (frame_type >= FRAME_TYPE_END)\n        return RT_ERR_OUT_OF_RANGE;\n\n   ppb_idx = 0;\n\n    for (i = 0; i<= RTL8367C_PROTOVLAN_GIDX_MAX; i++)\n    {\n        if ((retVal = rtl8367c_getAsicVlanProtocolBasedGroupData(i, &ppb_data_cfg)) != RT_ERR_OK)\n            return retVal;\n\n        if ( (ppb_data_cfg.frameType == (rtl8367c_provlan_frametype)frame_type) && (ppb_data_cfg.etherType == proto_type) )\n        {\n            ppb_idx = i;\n            ppb_vlan_cfg.valid = FALSE;\n            ppb_vlan_cfg.vlan_idx = 0;\n            ppb_vlan_cfg.priority = 0;\n            if ((retVal = rtl8367c_setAsicVlanPortAndProtocolBased(rtk_switch_port_L2P_get(port), ppb_idx, &ppb_vlan_cfg)) != RT_ERR_OK)\n                return retVal;\n        }\n    }\n\n    bUsed = FALSE;\n    RTK_SCAN_ALL_PHY_PORTMASK(i)\n    {\n        if ((retVal = rtl8367c_getAsicVlanPortAndProtocolBased(i, ppb_idx, &ppb_vlan_cfg)) != RT_ERR_OK)\n            return retVal;\n\n        if (TRUE == ppb_vlan_cfg.valid)\n        {\n            bUsed = TRUE;\n                break;\n        }\n    }\n\n    if (FALSE == bUsed) /*No Port use this PPB Index, Delete it*/\n    {\n        ppb_data_cfg.etherType=0;\n        ppb_data_cfg.frameType=0;\n        if ((retVal = rtl8367c_setAsicVlanProtocolBasedGroupData(ppb_idx, &ppb_data_cfg)) != RT_ERR_OK)\n            return retVal;\n    }\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_vlan_protoAndPortBasedVlan_delAll\n * Description:\n *     Delete all protocol-and-port-based vlans from the specified port of device.\n * Input:\n *      port - Port id.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK               - OK\n *      RT_ERR_FAILED           - Failed\n *      RT_ERR_SMI              - SMI access error\n *      RT_ERR_PORT_ID          - Invalid port number.\n *      RT_ERR_OUT_OF_RANGE     - input out of range.\n * Note:\n *     The incoming packet which match the protocol-and-port-based vlan will use the configure vid for ingress pipeline\n *     Delete all flow table protocol-and-port-based vlan entries.\n */\nrtk_api_ret_t rtk_vlan_protoAndPortBasedVlan_delAll(rtk_port_t port)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32 i, j, bUsed[4];\n    rtl8367c_protocolgdatacfg ppb_data_cfg;\n    rtl8367c_protocolvlancfg ppb_vlan_cfg;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check Port Valid */\n    RTK_CHK_PORT_VALID(port);\n\n    for (i = 0; i<= RTL8367C_PROTOVLAN_GIDX_MAX; i++)\n    {\n        ppb_vlan_cfg.valid = FALSE;\n        ppb_vlan_cfg.vlan_idx = 0;\n        ppb_vlan_cfg.priority = 0;\n        if ((retVal = rtl8367c_setAsicVlanPortAndProtocolBased(rtk_switch_port_L2P_get(port), i, &ppb_vlan_cfg)) != RT_ERR_OK)\n            return retVal;\n    }\n\n    bUsed[0] = FALSE;\n    bUsed[1] = FALSE;\n    bUsed[2] = FALSE;\n    bUsed[3] = FALSE;\n    RTK_SCAN_ALL_PHY_PORTMASK(i)\n    {\n        for (j = 0; j <= RTL8367C_PROTOVLAN_GIDX_MAX; j++)\n        {\n            if ((retVal = rtl8367c_getAsicVlanPortAndProtocolBased(i,j, &ppb_vlan_cfg)) != RT_ERR_OK)\n                return retVal;\n\n            if (TRUE == ppb_vlan_cfg.valid)\n            {\n                bUsed[j] = TRUE;\n            }\n        }\n    }\n\n    for (i = 0; i<= RTL8367C_PROTOVLAN_GIDX_MAX; i++)\n    {\n        if (FALSE == bUsed[i]) /*No Port use this PPB Index, Delete it*/\n        {\n            ppb_data_cfg.etherType=0;\n            ppb_data_cfg.frameType=0;\n            if ((retVal = rtl8367c_setAsicVlanProtocolBasedGroupData(i, &ppb_data_cfg)) != RT_ERR_OK)\n                return retVal;\n        }\n    }\n\n\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_vlan_tagMode_set\n * Description:\n *      Set CVLAN egress tag mode\n * Input:\n *      port        - Port id.\n *      tag_mode    - The egress tag mode.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number.\n *      RT_ERR_INPUT        - Invalid input parameter.\n *      RT_ERR_ENABLE       - Invalid enable input.\n * Note:\n *      The API can set Egress tag mode. There are 4 mode for egress tag:\n *      - VLAN_TAG_MODE_ORIGINAL,\n *      - VLAN_TAG_MODE_KEEP_FORMAT,\n *      - VLAN_TAG_MODE_PRI.\n *      - VLAN_TAG_MODE_REAL_KEEP_FORMAT,\n */\nrtk_api_ret_t rtk_vlan_tagMode_set(rtk_port_t port, rtk_vlan_tagMode_t tag_mode)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check Port Valid */\n    RTK_CHK_PORT_VALID(port);\n\n    if (tag_mode >= VLAN_TAG_MODE_END)\n        return RT_ERR_PORT_ID;\n\n    if ((retVal = rtl8367c_setAsicVlanEgressTagMode(rtk_switch_port_L2P_get(port), tag_mode)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_vlan_tagMode_get\n * Description:\n *      Get CVLAN egress tag mode\n * Input:\n *      port - Port id.\n * Output:\n *      pTag_mode - The egress tag mode.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n *      RT_ERR_PORT_ID      - Invalid port number.\n * Note:\n *      The API can get Egress tag mode. There are 4 mode for egress tag:\n *      - VLAN_TAG_MODE_ORIGINAL,\n *      - VLAN_TAG_MODE_KEEP_FORMAT,\n *      - VLAN_TAG_MODE_PRI.\n *      - VLAN_TAG_MODE_REAL_KEEP_FORMAT,\n */\nrtk_api_ret_t rtk_vlan_tagMode_get(rtk_port_t port, rtk_vlan_tagMode_t *pTag_mode)\n{\n    rtk_api_ret_t retVal;\n    rtl8367c_egtagmode  mode;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check Port Valid */\n    RTK_CHK_PORT_VALID(port);\n\n    if(NULL == pTag_mode)\n        return RT_ERR_NULL_POINTER;\n\n    if ((retVal = rtl8367c_getAsicVlanEgressTagMode(rtk_switch_port_L2P_get(port), &mode)) != RT_ERR_OK)\n        return retVal;\n\n    *pTag_mode = (rtk_vlan_tagMode_t)mode;\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_vlan_transparent_set\n * Description:\n *      Set VLAN transparent mode\n * Input:\n *      egr_port        - Egress Port id.\n *      pIgr_pmask      - Ingress Port Mask.\n * Output:\n *      None.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n *      RT_ERR_PORT_ID      - Invalid port number.\n * Note:\n *      None.\n */\nrtk_api_ret_t rtk_vlan_transparent_set(rtk_port_t egr_port, rtk_portmask_t *pIgr_pmask)\n{\n     rtk_api_ret_t retVal;\n     rtk_uint32    pmask;\n\n     /* Check initialization state */\n     RTK_CHK_INIT_STATE();\n\n     /* Check Port Valid */\n     RTK_CHK_PORT_VALID(egr_port);\n\n     if(NULL == pIgr_pmask)\n        return RT_ERR_NULL_POINTER;\n\n     RTK_CHK_PORTMASK_VALID(pIgr_pmask);\n\n     if(rtk_switch_portmask_L2P_get(pIgr_pmask, &pmask) != RT_ERR_OK)\n        return RT_ERR_FAILED;\n\n     if ((retVal = rtl8367c_setAsicVlanTransparent(rtk_switch_port_L2P_get(egr_port), pmask)) != RT_ERR_OK)\n         return retVal;\n\n     return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_vlan_transparent_get\n * Description:\n *      Get VLAN transparent mode\n * Input:\n *      egr_port        - Egress Port id.\n * Output:\n *      pIgr_pmask      - Ingress Port Mask\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n *      RT_ERR_PORT_ID      - Invalid port number.\n * Note:\n *      None.\n */\nrtk_api_ret_t rtk_vlan_transparent_get(rtk_port_t egr_port, rtk_portmask_t *pIgr_pmask)\n{\n     rtk_api_ret_t retVal;\n     rtk_uint32    pmask;\n\n     /* Check initialization state */\n     RTK_CHK_INIT_STATE();\n\n     /* Check Port Valid */\n     RTK_CHK_PORT_VALID(egr_port);\n\n     if(NULL == pIgr_pmask)\n        return RT_ERR_NULL_POINTER;\n\n     if ((retVal = rtl8367c_getAsicVlanTransparent(rtk_switch_port_L2P_get(egr_port), &pmask)) != RT_ERR_OK)\n         return retVal;\n\n     if(rtk_switch_portmask_P2L_get(pmask, pIgr_pmask) != RT_ERR_OK)\n        return RT_ERR_FAILED;\n\n     return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_vlan_keep_set\n * Description:\n *      Set VLAN egress keep mode\n * Input:\n *      egr_port        - Egress Port id.\n *      pIgr_pmask      - Ingress Port Mask.\n * Output:\n *      None.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n *      RT_ERR_PORT_ID      - Invalid port number.\n * Note:\n *      None.\n */\nrtk_api_ret_t rtk_vlan_keep_set(rtk_port_t egr_port, rtk_portmask_t *pIgr_pmask)\n{\n     rtk_api_ret_t retVal;\n     rtk_uint32    pmask;\n\n     /* Check initialization state */\n     RTK_CHK_INIT_STATE();\n\n     /* Check Port Valid */\n     RTK_CHK_PORT_VALID(egr_port);\n\n     if(NULL == pIgr_pmask)\n        return RT_ERR_NULL_POINTER;\n\n     RTK_CHK_PORTMASK_VALID(pIgr_pmask);\n\n     if(rtk_switch_portmask_L2P_get(pIgr_pmask, &pmask) != RT_ERR_OK)\n        return RT_ERR_FAILED;\n\n     if ((retVal = rtl8367c_setAsicVlanEgressKeep(rtk_switch_port_L2P_get(egr_port), pmask)) != RT_ERR_OK)\n         return retVal;\n\n     return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_vlan_keep_get\n * Description:\n *      Get VLAN egress keep mode\n * Input:\n *      egr_port        - Egress Port id.\n * Output:\n *      pIgr_pmask      - Ingress Port Mask\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n *      RT_ERR_PORT_ID      - Invalid port number.\n * Note:\n *      None.\n */\nrtk_api_ret_t rtk_vlan_keep_get(rtk_port_t egr_port, rtk_portmask_t *pIgr_pmask)\n{\n     rtk_api_ret_t retVal;\n     rtk_uint32    pmask;\n\n     /* Check initialization state */\n     RTK_CHK_INIT_STATE();\n\n     /* Check Port Valid */\n     RTK_CHK_PORT_VALID(egr_port);\n\n     if(NULL == pIgr_pmask)\n        return RT_ERR_NULL_POINTER;\n\n     if ((retVal = rtl8367c_getAsicVlanEgressKeep(rtk_switch_port_L2P_get(egr_port), &pmask)) != RT_ERR_OK)\n         return retVal;\n\n     if(rtk_switch_portmask_P2L_get(pmask, pIgr_pmask) != RT_ERR_OK)\n        return RT_ERR_FAILED;\n\n     return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_vlan_stg_set\n * Description:\n *      Set spanning tree group instance of the vlan to the specified device\n * Input:\n *      vid - Specified VLAN ID.\n *      stg - spanning tree group instance.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_MSTI         - Invalid msti parameter\n *      RT_ERR_INPUT        - Invalid input parameter.\n *      RT_ERR_VLAN_VID     - Invalid VID parameter.\n * Note:\n *      The API can set spanning tree group instance of the vlan to the specified device.\n */\nrtk_api_ret_t rtk_vlan_stg_set(rtk_vlan_t vid, rtk_stp_msti_id_t stg)\n{\n    rtk_api_ret_t retVal;\n    rtl8367c_user_vlan4kentry vlan4K;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* vid must be 0~4095 */\n    if (vid > RTL8367C_VIDMAX)\n        return RT_ERR_VLAN_VID;\n\n    /* priority must be 0~15 */\n    if (stg > RTL8367C_MSTIMAX)\n        return RT_ERR_MSTI;\n\n    /* update 4K table */\n    vlan4K.vid = vid;\n    if ((retVal = rtl8367c_getAsicVlan4kEntry(&vlan4K)) != RT_ERR_OK)\n        return retVal;\n\n    vlan4K.fid_msti= stg;\n    if ((retVal = rtl8367c_setAsicVlan4kEntry(&vlan4K)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_vlan_stg_get\n * Description:\n *      Get spanning tree group instance of the vlan to the specified device\n * Input:\n *      vid - Specified VLAN ID.\n * Output:\n *      pStg - spanning tree group instance.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Invalid input parameters.\n *      RT_ERR_VLAN_VID     - Invalid VID parameter.\n * Note:\n *      The API can get spanning tree group instance of the vlan to the specified device.\n */\nrtk_api_ret_t rtk_vlan_stg_get(rtk_vlan_t vid, rtk_stp_msti_id_t *pStg)\n{\n    rtk_api_ret_t retVal;\n    rtl8367c_user_vlan4kentry vlan4K;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* vid must be 0~4095 */\n    if (vid > RTL8367C_VIDMAX)\n        return RT_ERR_VLAN_VID;\n\n    if(NULL == pStg)\n        return RT_ERR_NULL_POINTER;\n\n    /* update 4K table */\n    vlan4K.vid = vid;\n    if ((retVal = rtl8367c_getAsicVlan4kEntry(&vlan4K)) != RT_ERR_OK)\n        return retVal;\n\n    *pStg = vlan4K.fid_msti;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_vlan_portFid_set\n * Description:\n *      Set port-based filtering database\n * Input:\n *      port - Port id.\n *      enable - ebable port-based FID\n *      fid - Specified filtering database.\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n *      RT_ERR_L2_FID - Invalid fid.\n *      RT_ERR_INPUT - Invalid input parameter.\n *      RT_ERR_PORT_ID - Invalid port ID.\n * Note:\n *      The API can set port-based filtering database. If the function is enabled, all input\n *      packets will be assigned to the port-based fid regardless vlan tag.\n */\nrtk_api_ret_t rtk_vlan_portFid_set(rtk_port_t port, rtk_enable_t enable, rtk_fid_t fid)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check Port Valid */\n    RTK_CHK_PORT_VALID(port);\n\n    if (enable>=RTK_ENABLE_END)\n        return RT_ERR_ENABLE;\n\n    /* fid must be 0~4095 */\n    if (fid > RTK_FID_MAX)\n        return RT_ERR_L2_FID;\n\n    if ((retVal = rtl8367c_setAsicPortBasedFidEn(rtk_switch_port_L2P_get(port), enable))!=RT_ERR_OK)\n        return retVal;\n\n    if ((retVal = rtl8367c_setAsicPortBasedFid(rtk_switch_port_L2P_get(port), fid))!=RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_vlan_portFid_get\n * Description:\n *      Get port-based filtering database\n * Input:\n *      port - Port id.\n * Output:\n *      pEnable - ebable port-based FID\n *      pFid - Specified filtering database.\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n *      RT_ERR_INPUT - Invalid input parameters.\n *      RT_ERR_PORT_ID - Invalid port ID.\n * Note:\n *      The API can get port-based filtering database status. If the function is enabled, all input\n *      packets will be assigned to the port-based fid regardless vlan tag.\n */\nrtk_api_ret_t rtk_vlan_portFid_get(rtk_port_t port, rtk_enable_t *pEnable, rtk_fid_t *pFid)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check Port Valid */\n    RTK_CHK_PORT_VALID(port);\n\n    if(NULL == pEnable)\n        return RT_ERR_NULL_POINTER;\n\n    if(NULL == pFid)\n        return RT_ERR_NULL_POINTER;\n\n    if ((retVal = rtl8367c_getAsicPortBasedFidEn(rtk_switch_port_L2P_get(port), pEnable))!=RT_ERR_OK)\n        return retVal;\n\n    if ((retVal = rtl8367c_getAsicPortBasedFid(rtk_switch_port_L2P_get(port), pFid))!=RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_vlan_UntagDscpPriorityEnable_set\n * Description:\n *      Set Untag DSCP priority assign\n * Input:\n *      enable - state of Untag DSCP priority assign\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n *      RT_ERR_ENABLE          - Invalid input parameters.\n * Note:\n *\n */\nrtk_api_ret_t rtk_vlan_UntagDscpPriorityEnable_set(rtk_enable_t enable)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(enable >= RTK_ENABLE_END)\n        return RT_ERR_ENABLE;\n\n    if ((retVal = rtl8367c_setAsicVlanUntagDscpPriorityEn((rtk_uint32)enable)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_vlan_UntagDscpPriorityEnable_get\n * Description:\n *      Get Untag DSCP priority assign\n * Input:\n *      None\n * Output:\n *      pEnable - state of Untag DSCP priority assign\n * Return:\n *      RT_ERR_OK              - OK\n *      RT_ERR_FAILED          - Failed\n *      RT_ERR_SMI             - SMI access error\n *      RT_ERR_NULL_POINTER    - Null pointer\n * Note:\n *\n */\nrtk_api_ret_t rtk_vlan_UntagDscpPriorityEnable_get(rtk_enable_t *pEnable)\n{\n    rtk_api_ret_t retVal;\n    rtk_uint32  value;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(NULL == pEnable)\n        return RT_ERR_NULL_POINTER;\n\n    if ((retVal = rtl8367c_getAsicVlanUntagDscpPriorityEn(&value)) != RT_ERR_OK)\n        return retVal;\n\n    *pEnable = (rtk_enable_t)value;\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_stp_mstpState_set\n * Description:\n *      Configure spanning tree state per each port.\n * Input:\n *      port - Port id\n *      msti - Multiple spanning tree instance.\n *      stp_state - Spanning tree state for msti\n * Output:\n *      None\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number.\n *      RT_ERR_MSTI         - Invalid msti parameter.\n *      RT_ERR_MSTP_STATE   - Invalid STP state.\n * Note:\n *      System supports per-port multiple spanning tree state for each msti.\n *      There are four states supported by ASIC.\n *      - STP_STATE_DISABLED\n *      - STP_STATE_BLOCKING\n *      - STP_STATE_LEARNING\n *      - STP_STATE_FORWARDING\n */\nrtk_api_ret_t rtk_stp_mstpState_set(rtk_stp_msti_id_t msti, rtk_port_t port, rtk_stp_state_t stp_state)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check Port Valid */\n    RTK_CHK_PORT_VALID(port);\n\n    if (msti > RTK_MAX_NUM_OF_MSTI)\n        return RT_ERR_MSTI;\n\n    if (stp_state >= STP_STATE_END)\n        return RT_ERR_MSTP_STATE;\n\n    if ((retVal = rtl8367c_setAsicSpanningTreeStatus(rtk_switch_port_L2P_get(port), msti, stp_state)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_stp_mstpState_get\n * Description:\n *      Get spanning tree state per each port.\n * Input:\n *      port - Port id.\n *      msti - Multiple spanning tree instance.\n * Output:\n *      pStp_state - Spanning tree state for msti\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_PORT_ID      - Invalid port number.\n *      RT_ERR_MSTI         - Invalid msti parameter.\n * Note:\n *      System supports per-port multiple spanning tree state for each msti.\n *      There are four states supported by ASIC.\n *      - STP_STATE_DISABLED\n *      - STP_STATE_BLOCKING\n *      - STP_STATE_LEARNING\n *      - STP_STATE_FORWARDING\n */\nrtk_api_ret_t rtk_stp_mstpState_get(rtk_stp_msti_id_t msti, rtk_port_t port, rtk_stp_state_t *pStp_state)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* Check Port Valid */\n    RTK_CHK_PORT_VALID(port);\n\n    if (msti > RTK_MAX_NUM_OF_MSTI)\n        return RT_ERR_MSTI;\n\n    if(NULL == pStp_state)\n        return RT_ERR_NULL_POINTER;\n\n    if ((retVal = rtl8367c_getAsicSpanningTreeStatus(rtk_switch_port_L2P_get(port), msti, pStp_state)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_vlan_checkAndCreateMbr\n * Description:\n *      Check and create Member configuration and return index\n * Input:\n *      vid  - VLAN id.\n * Output:\n *      pIndex  - Member configuration index\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_VLAN_VID     - Invalid VLAN ID.\n *      RT_ERR_VLAN_ENTRY_NOT_FOUND - VLAN not found\n *      RT_ERR_TBL_FULL     - Member Configuration table full\n * Note:\n *\n */\nrtk_api_ret_t rtk_vlan_checkAndCreateMbr(rtk_vlan_t vid, rtk_uint32 *pIndex)\n{\n    rtk_api_ret_t retVal;\n    rtl8367c_user_vlan4kentry vlan4K;\n    rtl8367c_vlanconfiguser vlanMC;\n    rtk_uint32 idx;\n    rtk_uint32 empty_idx = 0xFFFF;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    /* vid must be 0~8191 */\n    if (vid > RTL8367C_EVIDMAX)\n        return RT_ERR_VLAN_VID;\n\n    /* Null pointer check */\n    if(NULL == pIndex)\n        return RT_ERR_NULL_POINTER;\n\n    /* Get 4K VLAN */\n    if (vid <= RTL8367C_VIDMAX)\n    {\n        memset(&vlan4K, 0x00, sizeof(rtl8367c_user_vlan4kentry));\n        vlan4K.vid = vid;\n        if ((retVal = rtl8367c_getAsicVlan4kEntry(&vlan4K)) != RT_ERR_OK)\n            return retVal;\n    }\n\n    /* Search exist entry */\n    for (idx = 0; idx <= RTL8367C_CVIDXMAX; idx++)\n    {\n        if(vlan_mbrCfgUsage[idx] == MBRCFG_USED_BY_VLAN)\n        {\n            if(vlan_mbrCfgVid[idx] == vid)\n            {\n                /* Found! return index */\n                *pIndex = idx;\n                return RT_ERR_OK;\n            }\n        }\n    }\n\n    /* Not found, Read H/W Member Configuration table to update database */\n    for (idx = 0; idx <= RTL8367C_CVIDXMAX; idx++)\n    {\n        if ((retVal = rtl8367c_getAsicVlanMemberConfig(idx, &vlanMC)) != RT_ERR_OK)\n            return retVal;\n\n        if( (vlanMC.evid == 0) && (vlanMC.mbr == 0x00))\n        {\n            vlan_mbrCfgUsage[idx]   = MBRCFG_UNUSED;\n            vlan_mbrCfgVid[idx]     = 0;\n        }\n        else\n        {\n            vlan_mbrCfgUsage[idx]   = MBRCFG_USED_BY_VLAN;\n            vlan_mbrCfgVid[idx]     = vlanMC.evid;\n        }\n    }\n\n    /* Search exist entry again */\n    for (idx = 0; idx <= RTL8367C_CVIDXMAX; idx++)\n    {\n        if(vlan_mbrCfgUsage[idx] == MBRCFG_USED_BY_VLAN)\n        {\n            if(vlan_mbrCfgVid[idx] == vid)\n            {\n                /* Found! return index */\n                *pIndex = idx;\n                return RT_ERR_OK;\n            }\n        }\n    }\n\n    /* try to look up an empty index */\n    for (idx = 0; idx <= RTL8367C_CVIDXMAX; idx++)\n    {\n        if(vlan_mbrCfgUsage[idx] == MBRCFG_UNUSED)\n        {\n            empty_idx = idx;\n            break;\n        }\n    }\n\n    if(empty_idx == 0xFFFF)\n    {\n        /* No empty index */\n        return RT_ERR_TBL_FULL;\n    }\n\n    if (vid > RTL8367C_VIDMAX)\n    {\n        /* > 4K, there is no 4K entry, create on member configuration directly */\n        memset(&vlanMC, 0x00, sizeof(rtl8367c_vlanconfiguser));\n        vlanMC.evid = vid;\n        if ((retVal = rtl8367c_setAsicVlanMemberConfig(empty_idx, &vlanMC)) != RT_ERR_OK)\n            return retVal;\n    }\n    else\n    {\n        /* Copy from 4K table */\n        vlanMC.evid = vid;\n        vlanMC.mbr = vlan4K.mbr;\n        vlanMC.fid_msti = vlan4K.fid_msti;\n        vlanMC.meteridx= vlan4K.meteridx;\n        vlanMC.envlanpol= vlan4K.envlanpol;\n        vlanMC.vbpen = vlan4K.vbpen;\n        vlanMC.vbpri = vlan4K.vbpri;\n        if ((retVal = rtl8367c_setAsicVlanMemberConfig(empty_idx, &vlanMC)) != RT_ERR_OK)\n            return retVal;\n    }\n\n    /* Update Database */\n    vlan_mbrCfgUsage[empty_idx] = MBRCFG_USED_BY_VLAN;\n    vlan_mbrCfgVid[empty_idx] = vid;\n\n    *pIndex = empty_idx;\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_vlan_reservedVidAction_set\n * Description:\n *      Set Action of VLAN ID = 0 & 4095 tagged packet\n * Input:\n *      action_vid0     - Action for VID 0.\n *      action_vid4095  - Action for VID 4095.\n * Output:\n *      None.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Error Input\n * Note:\n *\n */\nrtk_api_ret_t rtk_vlan_reservedVidAction_set(rtk_vlan_resVidAction_t action_vid0, rtk_vlan_resVidAction_t action_vid4095)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(action_vid0 >= RESVID_ACTION_END)\n        return RT_ERR_INPUT;\n\n    if(action_vid4095 >= RESVID_ACTION_END)\n        return RT_ERR_INPUT;\n\n    if ((retVal = rtl8367c_setReservedVidAction((rtk_uint32)action_vid0, (rtk_uint32)action_vid4095)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_vlan_reservedVidAction_get\n * Description:\n *      Get Action of VLAN ID = 0 & 4095 tagged packet\n * Input:\n *      pAction_vid0     - Action for VID 0.\n *      pAction_vid4095  - Action for VID 4095.\n * Output:\n *      None.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_NULL_POINTER - NULL Pointer\n * Note:\n *\n */\nrtk_api_ret_t rtk_vlan_reservedVidAction_get(rtk_vlan_resVidAction_t *pAction_vid0, rtk_vlan_resVidAction_t *pAction_vid4095)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(pAction_vid0 == NULL)\n        return RT_ERR_NULL_POINTER;\n\n    if(pAction_vid4095 == NULL)\n        return RT_ERR_NULL_POINTER;\n\n    if ((retVal = rtl8367c_getReservedVidAction((rtk_uint32 *)pAction_vid0, (rtk_uint32 *)pAction_vid4095)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_vlan_realKeepRemarkEnable_set\n * Description:\n *      Set Real keep 1p remarking feature\n * Input:\n *      enabled     - State of 1p remarking at real keep packet\n * Output:\n *      None.\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Error Input\n * Note:\n *\n */\nrtk_api_ret_t rtk_vlan_realKeepRemarkEnable_set(rtk_enable_t enabled)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(enabled >= RTK_ENABLE_END)\n        return RT_ERR_INPUT;\n\n    if ((retVal = rtl8367c_setRealKeepRemarkEn((rtk_uint32)enabled)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_vlan_realKeepRemarkEnable_get\n * Description:\n *      Get Real keep 1p remarking feature\n * Input:\n *      None.\n * Output:\n *      pEnabled     - State of 1p remarking at real keep packet\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Error Input\n * Note:\n *\n */\nrtk_api_ret_t rtk_vlan_realKeepRemarkEnable_get(rtk_enable_t *pEnabled)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if(NULL == pEnabled)\n        return RT_ERR_NULL_POINTER;\n\n    if ((retVal = rtl8367c_getRealKeepRemarkEn((rtk_uint32 *)pEnabled)) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n/* Function Name:\n *      rtk_vlan_reset\n * Description:\n *      Reset VLAN\n * Input:\n *      None.\n * Output:\n *      pEnabled     - State of 1p remarking at real keep packet\n * Return:\n *      RT_ERR_OK           - OK\n *      RT_ERR_FAILED       - Failed\n *      RT_ERR_SMI          - SMI access error\n *      RT_ERR_INPUT        - Error Input\n * Note:\n *\n */\nrtk_api_ret_t rtk_vlan_reset(void)\n{\n    rtk_api_ret_t retVal;\n\n    /* Check initialization state */\n    RTK_CHK_INIT_STATE();\n\n    if ((retVal = rtl8367c_resetVlan()) != RT_ERR_OK)\n        return retVal;\n\n    return RT_ERR_OK;\n}\n\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367s.c",
    "content": "/*\n * This program is free software; you can redistribute it and/or\n * modify it under the terms of the GNU General Public License\n * as published by the Free Software Foundation; either version 2\n * of the License, or (at your option) any later version.\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n * GNU General Public License for more details.\n *\n */\n\n#include <linux/kernel.h>\n#include <linux/module.h>\n#include <linux/init.h>\n#include <linux/device.h>\n#include <linux/delay.h>\n#include <linux/skbuff.h>\n#include <linux/switch.h>\n\n//include from rtl8367c dir\n#include  \"./rtl8367c/include/rtk_switch.h\"\n#include  \"./rtl8367c/include/vlan.h\"\n#include  \"./rtl8367c/include/stat.h\"\n#include  \"./rtl8367c/include/port.h\"\n\n#define RTL8367C_SW_CPU_PORT    6\n\n //RTL8367C_PHY_PORT_NUM + ext0 + ext1\n#define RTL8367C_NUM_PORTS 7 \n#define RTL8367C_NUM_VIDS  4096   \n\nstruct rtl8367_priv {\n\tstruct switch_dev\tswdev;\n\tbool\t\t\tglobal_vlan_enable;\n};\n\nstruct rtl8367_mib_counter {\t\n\tconst char *name;\n};\n\nstruct rtl8367_vlan_info {\n\tunsigned short\tvid;\n\tunsigned int\tuntag;\n\tunsigned int\tmember;\n\tunsigned char\t\tfid;\n};\n\nstruct rtl8367_priv  rtl8367_priv_data;\n\nunsigned int rtl8367c_port_id[RTL8367C_NUM_PORTS]={0,1,2,3,4,EXT_PORT1,EXT_PORT0};\n\nvoid (*rtl8367_switch_reset_func)(void)=NULL;\n\nstatic  struct rtl8367_mib_counter  rtl8367c_mib_counters[] = {\n\t{\"ifInOctets\"},\n\t{\"dot3StatsFCSErrors\"},\n\t{\"dot3StatsSymbolErrors\"},\n\t{\"dot3InPauseFrames\"},\n\t{\"dot3ControlInUnknownOpcodes\"},\n\t{\"etherStatsFragments\"},\n\t{\"etherStatsJabbers\"},\n\t{\"ifInUcastPkts\"},\n\t{\"etherStatsDropEvents\"},\n\t{\"etherStatsOctets\"},\n\t{\"etherStatsUndersizePkts\"},\n\t{\"etherStatsOversizePkts\"},\n\t{\"etherStatsPkts64Octets\"},\n\t{\"etherStatsPkts65to127Octets\"},\n\t{\"etherStatsPkts128to255Octets\"},\n\t{\"etherStatsPkts256to511Octets\"},\n\t{\"etherStatsPkts512to1023Octets\"},\n\t{\"etherStatsPkts1024toMaxOctets\"},\n\t{\"etherStatsMcastPkts\"}, \n\t{\"etherStatsBcastPkts\"},\n\t{\"ifOutOctets\"},\n\t{\"dot3StatsSingleCollisionFrames\"},\n\t{\"dot3StatsMultipleCollisionFrames\"},\n\t{\"dot3StatsDeferredTransmissions\"},\n\t{\"dot3StatsLateCollisions\"}, \n\t{\"etherStatsCollisions\"},\n\t{\"dot3StatsExcessiveCollisions\"},\n\t{\"dot3OutPauseFrames\"},\n\t{\"dot1dBasePortDelayExceededDiscards\"},\n\t{\"dot1dTpPortInDiscards\"},\n\t{\"ifOutUcastPkts\"},\n\t{\"ifOutMulticastPkts\"},\n\t{\"ifOutBrocastPkts\"},\n\t{\"outOampduPkts\"},\n\t{\"inOampduPkts\"},\n\t{\"pktgenPkts\"},\n\t{\"inMldChecksumError\"},\n\t{\"inIgmpChecksumError\"},\n\t{\"inMldSpecificQuery\"},\n\t{\"inMldGeneralQuery\"},\n\t{\"inIgmpSpecificQuery\"},\n\t{\"inIgmpGeneralQuery\"},\n\t{\"inMldLeaves\"},\n\t{\"inIgmpLeaves\"},\n\t{\"inIgmpJoinsSuccess\"},\n\t{\"inIgmpJoinsFail\"},\n\t{\"inMldJoinsSuccess\"},\n\t{\"inMldJoinsFail\"},\n\t{\"inReportSuppressionDrop\"},\n\t{\"inLeaveSuppressionDrop\"},\n\t{\"outIgmpReports\"},\n\t{\"outIgmpLeaves\"},\n\t{\"outIgmpGeneralQuery\"},\n\t{\"outIgmpSpecificQuery\"},\n\t{\"outMldReports\"},\n\t{\"outMldLeaves\"},\n\t{\"outMldGeneralQuery\"},\n\t{\"outMldSpecificQuery\"},\n\t{\"inKnownMulticastPkts\"},\n\t{\"ifInMulticastPkts\"},\n\t{\"ifInBroadcastPkts\"},\n\t{\"ifOutDiscards\"}\n};\n\n/*rtl8367c  proprietary switch API wrapper */\nstatic inline unsigned int rtl8367c_sw_to_phy_port(int port)\n{\n\treturn rtl8367c_port_id[port];\n}\n\nstatic inline unsigned int rtl8367c_portmask_phy_to_sw(rtk_portmask_t phy_portmask)\n{\n\tint i;\n\tfor (i = 0; i < RTL8367C_NUM_PORTS; i++) {\n\t\tif(RTK_PORTMASK_IS_PORT_SET(phy_portmask,rtl8367c_sw_to_phy_port(i))) {\n\t\t\tRTK_PORTMASK_PORT_CLEAR(phy_portmask,rtl8367c_sw_to_phy_port(i));\n\t\t\tRTK_PORTMASK_PORT_SET(phy_portmask,i);\n\t\t}\t\t\n\n\t}\n\treturn (unsigned int)phy_portmask.bits[0];\n}\n\nstatic int rtl8367c_reset_mibs(void)\n{\n\treturn rtk_stat_global_reset();\n}\n\nstatic int rtl8367c_reset_port_mibs(int port)\n{\n\n\treturn rtk_stat_port_reset(rtl8367c_sw_to_phy_port(port));\n}\n\nstatic int rtl8367c_get_mibs_num(void)\n{\n\treturn ARRAY_SIZE(rtl8367c_mib_counters);\n}\n\nstatic const char *rtl8367c_get_mib_name(int idx)\n{\n\t\n\treturn rtl8367c_mib_counters[idx].name;\n}\n\nstatic int rtl8367c_get_port_mib_counter(int idx, int port, unsigned long long *counter)\n{\n\treturn rtk_stat_port_get(rtl8367c_sw_to_phy_port(port), idx, counter);\n}\n\nstatic int rtl8367c_is_vlan_valid(unsigned int vlan)\n{\n\tunsigned max = RTL8367C_NUM_VIDS;\t\n\n\tif (vlan == 0 || vlan >= max)\n\t\treturn 0;\n\n\treturn 1;\n}\n\nstatic int rtl8367c_get_vlan( unsigned short vid, struct rtl8367_vlan_info *vlan)\n{\t\n\trtk_vlan_cfg_t vlan_cfg;\n\n\tmemset(vlan, '\\0', sizeof(struct rtl8367_vlan_info));\n\n\tif (vid >= RTL8367C_NUM_VIDS)\n\t\treturn -EINVAL;\t\n\n\tif(rtk_vlan_get(vid,&vlan_cfg))\n       \treturn -EINVAL;\t\t\n\t\n\tvlan->vid = vid;\n\tvlan->member = rtl8367c_portmask_phy_to_sw(vlan_cfg.mbr);\t\n\tvlan->untag = rtl8367c_portmask_phy_to_sw(vlan_cfg.untag);\t\n\tvlan->fid = vlan_cfg.fid_msti;\n\n\treturn 0;\n}\n\nstatic int rtl8367c_set_vlan( unsigned short vid, u32 mbr, u32 untag, u8 fid)\n{\t\n\trtk_vlan_cfg_t vlan_cfg;\n\tint i;\n\n\tmemset(&vlan_cfg, 0x00, sizeof(rtk_vlan_cfg_t));\t\n\n\tfor (i = 0; i < RTL8367C_NUM_PORTS; i++) {\n\t\tif (mbr & (1 << i)) {\n\t\t\tRTK_PORTMASK_PORT_SET(vlan_cfg.mbr, rtl8367c_sw_to_phy_port(i));\n\t\t\tif(untag & (1 << i))\n\t\t\t\tRTK_PORTMASK_PORT_SET(vlan_cfg.untag, rtl8367c_sw_to_phy_port(i));\t\t\t\n\t\t}\n\t}\n\tvlan_cfg.fid_msti=fid;\n\tvlan_cfg.ivl_en = 1;\n\treturn rtk_vlan_set(vid, &vlan_cfg);\n}\n\n\nstatic int rtl8367c_get_pvid( int port, int *pvid)\n{\n\tu32 prio=0;\n\t\n\tif (port >= RTL8367C_NUM_PORTS)\n\t\treturn -EINVAL;\t\t\n\n\treturn rtk_vlan_portPvid_get(rtl8367c_sw_to_phy_port(port),pvid,&prio);\n}\n\n\nstatic int rtl8367c_set_pvid( int port, int pvid)\n{\n\tu32 prio=0;\n\t\n\tif (port >= RTL8367C_NUM_PORTS)\n\t\treturn -EINVAL;\t\t\n\n\treturn rtk_vlan_portPvid_set(rtl8367c_sw_to_phy_port(port),pvid,prio);\n}\n\nstatic int rtl8367c_get_port_link(int port, int *link, int *speed, int *duplex)\n{\n\t\n\tif(rtk_port_phyStatus_get(rtl8367c_sw_to_phy_port(port),(rtk_port_linkStatus_t *)link,\n\t\t\t\t\t(rtk_port_speed_t *)speed,(rtk_port_duplex_t *)duplex))\n\t\treturn -EINVAL;\n\n\treturn 0;\n}\n\n/*common rtl8367 swconfig entry API*/\n\nstatic int\nrtl8367_sw_set_vlan_enable(struct switch_dev *dev,\n\t\t\t   const struct switch_attr *attr,\n\t\t\t   struct switch_val *val)\n{\n\tstruct rtl8367_priv *priv = container_of(dev, struct rtl8367_priv, swdev);\t\n\n\tpriv->global_vlan_enable = val->value.i ;\n\n\treturn 0;\n}\n\nstatic int\nrtl8367_sw_get_vlan_enable(struct switch_dev *dev,\n\t\t\t   const struct switch_attr *attr,\n\t\t\t   struct switch_val *val)\n{\n\tstruct rtl8367_priv *priv = container_of(dev, struct rtl8367_priv, swdev);\n\n\tval->value.i = priv->global_vlan_enable;\n\n\treturn 0;\n}\n\nstatic int rtl8367_sw_reset_mibs(struct switch_dev *dev,\n\t\t\t\t  const struct switch_attr *attr,\n\t\t\t\t  struct switch_val *val)\n{\n\treturn rtl8367c_reset_mibs();\n}\n\n\nstatic int rtl8367_sw_reset_port_mibs(struct switch_dev *dev,\n\t\t\t\t       const struct switch_attr *attr,\n\t\t\t\t       struct switch_val *val)\n{\n\tint port;\n\n\tport = val->port_vlan;\n\tif (port >= RTL8367C_NUM_PORTS)\n\t\treturn -EINVAL;\n\n\treturn rtl8367c_reset_port_mibs(port);\n}\n\nstatic int rtl8367_sw_get_port_mib(struct switch_dev *dev,\n\t\t\t    const struct switch_attr *attr,\n\t\t\t    struct switch_val *val)\n{\t\n\tint i, len = 0;\n\tunsigned long long counter = 0;\n\tstatic char mib_buf[4096];\n\n\tif (val->port_vlan >= RTL8367C_NUM_PORTS)\n\t\treturn -EINVAL;\n\n\tlen += snprintf(mib_buf + len, sizeof(mib_buf) - len,\n\t\t\t\"Port %d MIB counters\\n\",\n\t\t\tval->port_vlan);\t\n\n\tfor (i = 0; i <rtl8367c_get_mibs_num(); ++i) {\n\t\tlen += snprintf(mib_buf + len, sizeof(mib_buf) - len,\n\t\t\t\t\"%-36s: \",rtl8367c_get_mib_name(i));\n\t\tif (!rtl8367c_get_port_mib_counter(i, val->port_vlan,\n\t\t\t\t\t       &counter))\n\t\t\tlen += snprintf(mib_buf + len, sizeof(mib_buf) - len,\n\t\t\t\t\t\"%llu\\n\", counter);\n\t\telse\n\t\t\tlen += snprintf(mib_buf + len, sizeof(mib_buf) - len,\n\t\t\t\t\t\"%s\\n\", \"N/A\");\n\t}\n\n\tval->value.s = mib_buf;\n\tval->len = len;\n\treturn 0;\n}\n\n\nstatic int rtl8367_sw_get_vlan_info(struct switch_dev *dev,\n\t\t\t     const struct switch_attr *attr,\n\t\t\t     struct switch_val *val)\n{\t\n\tint i;\n\tu32 len = 0;\n\tstruct rtl8367_vlan_info vlan;\n\tstatic char vlan_buf[256];\n\tint err;\n\n\tif (!rtl8367c_is_vlan_valid(val->port_vlan))\n\t\treturn -EINVAL;\n\n\tmemset(vlan_buf, '\\0', sizeof(vlan_buf));\n\n\terr = rtl8367c_get_vlan(val->port_vlan, &vlan);\n\tif (err)\n\t\treturn err;\n\n\tlen += snprintf(vlan_buf + len, sizeof(vlan_buf) - len,\n\t\t\t\"VLAN %d: Ports: '\", vlan.vid);\n\n\tfor (i = 0; i <RTL8367C_NUM_PORTS; i++) {\n\t\tif (!(vlan.member & (1 << i)))\n\t\t\tcontinue;\n\n\t\tlen += snprintf(vlan_buf + len, sizeof(vlan_buf) - len, \"%d%s\", i,\n\t\t\t\t(vlan.untag & (1 << i)) ? \"\" : \"t\");\n\t}\n\n\tlen += snprintf(vlan_buf + len, sizeof(vlan_buf) - len,\n\t\t\t\"', members=%04x, untag=%04x, fid=%u\",\n\t\t\tvlan.member, vlan.untag, vlan.fid);\n\n\tval->value.s = vlan_buf;\n\tval->len = len;\n\n\treturn 0;\n}\n\n\nstatic int rtl8367_sw_get_vlan_ports(struct switch_dev *dev, struct switch_val *val)\n{\n\tstruct switch_port *port;\n\tstruct rtl8367_vlan_info vlan;\n\tint i;\t\n\t\n\tif (!rtl8367c_is_vlan_valid(val->port_vlan))\n\t\treturn -EINVAL;\n\n\tif(rtl8367c_get_vlan(val->port_vlan, &vlan))\n\t\treturn -EINVAL;\n\n\tport = &val->value.ports[0];\n\tval->len = 0;\n\tfor (i = 0; i <RTL8367C_NUM_PORTS ; i++) {\n\t\tif (!(vlan.member & BIT(i)))\n\t\t\tcontinue;\n\n\t\tport->id = i;\n\t\tport->flags = (vlan.untag & BIT(i)) ?\n\t\t\t\t\t0 : BIT(SWITCH_PORT_FLAG_TAGGED);\n\t\tval->len++;\n\t\tport++;\n\t}\n\treturn 0;\n}\n\n\nstatic int rtl8367_sw_set_vlan_ports(struct switch_dev *dev, struct switch_val *val)\n{\n\tstruct switch_port *port;\n\tu32 member = 0;\n\tu32 untag = 0;\n\tu8 fid=0;\n\tint err;\n\tint i;\t\n\t\n\tif (!rtl8367c_is_vlan_valid(val->port_vlan))\n\t\treturn -EINVAL;\n\n\tport = &val->value.ports[0];\n\tfor (i = 0; i < val->len; i++, port++) {\n\t\tint pvid = 0;\n\t\tmember |= BIT(port->id);\n\n\t\tif (!(port->flags & BIT(SWITCH_PORT_FLAG_TAGGED)))\n\t\t\tuntag |= BIT(port->id);\n\n\t\t/*\n\t\t * To ensure that we have a valid MC entry for this VLAN,\n\t\t * initialize the port VLAN ID here.\n\t\t */\n\t\terr = rtl8367c_get_pvid(port->id, &pvid);\n\t\tif (err < 0)\n\t\t\treturn err;\n\t\tif (pvid == 0) {\n\t\t\terr = rtl8367c_set_pvid(port->id, val->port_vlan);\n\t\t\tif (err < 0)\n\t\t\t\treturn err;\n\t\t}\n\t}\n\n\t//pr_info(\"[%s] vid=%d , mem=%x,untag=%x,fid=%d \\n\",__func__,val->port_vlan,member,untag,fid);\n\n\treturn rtl8367c_set_vlan(val->port_vlan, member, untag, fid);\t\n\n}\n\n\nstatic int rtl8367_sw_get_port_pvid(struct switch_dev *dev, int port, int *val)\n{\n\treturn rtl8367c_get_pvid(port, val);\n}\n\n\nstatic int rtl8367_sw_set_port_pvid(struct switch_dev *dev, int port, int val)\n{\t\n\treturn rtl8367c_set_pvid(port, val);\n}\n\n\nstatic int rtl8367_sw_reset_switch(struct switch_dev *dev)\n{\n\tif(rtl8367_switch_reset_func)\n\t\t(*rtl8367_switch_reset_func)();\n\telse\n\t\tprintk(\"rest switch is not supported\\n\");\n\n\treturn 0;\n}\n\nstatic int rtl8367_sw_get_port_link(struct switch_dev *dev, int port,\n\t\t\t\t    struct switch_port_link *link)\n{\t\n\tint speed;\n\n\tif (port >= RTL8367C_NUM_PORTS)\n\t\treturn -EINVAL;\n\n\tif(rtl8367c_get_port_link(port,(int *)&link->link,(int *)&speed,(int *)&link->duplex))\n\t\treturn -EINVAL;\t\t\n\n\tif (!link->link)\n\t\treturn 0;\t\n\n\tswitch (speed) {\n\tcase 0:\n\t\tlink->speed = SWITCH_PORT_SPEED_10;\n\t\tbreak;\n\tcase 1:\n\t\tlink->speed = SWITCH_PORT_SPEED_100;\n\t\tbreak;\n\tcase 2:\n\t\tlink->speed = SWITCH_PORT_SPEED_1000;\n\t\tbreak;\n\tdefault:\n\t\tlink->speed = SWITCH_PORT_SPEED_UNKNOWN;\n\t\tbreak;\n\t}\n\n\treturn 0;\n}\n\n\nstatic struct switch_attr rtl8367_globals[] = {\n\t{\n\t\t.type = SWITCH_TYPE_INT,\n\t\t.name = \"enable_vlan\",\n\t\t.description = \"Enable VLAN mode\",\n\t\t.set = rtl8367_sw_set_vlan_enable,\n\t\t.get = rtl8367_sw_get_vlan_enable,\n\t\t.max = 1,\t\t\n\t}, {\t\t\n\t\t.type = SWITCH_TYPE_NOVAL,\n\t\t.name = \"reset_mibs\",\n\t\t.description = \"Reset all MIB counters\",\n\t\t.set = rtl8367_sw_reset_mibs,\n\t}\n};\n\nstatic struct switch_attr rtl8367_port[] = {\n\t{\n\t\t.type = SWITCH_TYPE_NOVAL,\n\t\t.name = \"reset_mib\",\n\t\t.description = \"Reset single port MIB counters\",\n\t\t.set = rtl8367_sw_reset_port_mibs,\n\t}, {\n\t\t.type = SWITCH_TYPE_STRING,\n\t\t.name = \"mib\",\n\t\t.description = \"Get MIB counters for port\",\n\t\t//.max = 33,\n\t\t.set = NULL,\n\t\t.get = rtl8367_sw_get_port_mib,\n\t},\n};\n\nstatic struct switch_attr rtl8367_vlan[] = {\n\t{\n\t\t.type = SWITCH_TYPE_STRING,\n\t\t.name = \"info\",\n\t\t.description = \"Get vlan information\",\n\t\t.max = 1,\n\t\t.set = NULL,\n\t\t.get = rtl8367_sw_get_vlan_info,\n\t},\n};\n\nstatic const struct switch_dev_ops rtl8367_sw_ops = {\n\t.attr_global = {\n\t\t.attr = rtl8367_globals,\n\t\t.n_attr = ARRAY_SIZE(rtl8367_globals),\n\t},\n\t.attr_port = {\n\t\t.attr = rtl8367_port,\n\t\t.n_attr = ARRAY_SIZE(rtl8367_port),\n\t},\n\t.attr_vlan = {\n\t\t.attr = rtl8367_vlan,\n\t\t.n_attr = ARRAY_SIZE(rtl8367_vlan),\n\t},\n\n\t.get_vlan_ports = rtl8367_sw_get_vlan_ports,\n\t.set_vlan_ports = rtl8367_sw_set_vlan_ports,\n\t.get_port_pvid = rtl8367_sw_get_port_pvid,\n\t.set_port_pvid = rtl8367_sw_set_port_pvid,\n\t.reset_switch = rtl8367_sw_reset_switch,\n\t.get_port_link = rtl8367_sw_get_port_link,\n};\n\nint rtl8367s_swconfig_init(void (*reset_func)(void))\n{\n\tstruct rtl8367_priv  *priv = &rtl8367_priv_data;\n\tstruct switch_dev *dev=&priv->swdev;\n\tint err=0;\n\n\trtl8367_switch_reset_func = reset_func ;\n\t\n\tmemset(priv, 0, sizeof(struct rtl8367_priv));\t\n\tpriv->global_vlan_enable =0;\n\n\tdev->name = \"RTL8367C\";\n\tdev->cpu_port = RTL8367C_SW_CPU_PORT;\n\tdev->ports = RTL8367C_NUM_PORTS;\n\tdev->vlans = RTL8367C_NUM_VIDS;\n\tdev->ops = &rtl8367_sw_ops;\n\tdev->alias = \"RTL8367C\";\t\t\n\terr = register_switch(dev, NULL);\n\n\tpr_info(\"[%s]\\n\",__func__);\n\n\treturn err;\n}\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367s_dbg.c",
    "content": "#include <linux/uaccess.h>\n#include <linux/trace_seq.h>\n#include <linux/seq_file.h>\n#include <linux/proc_fs.h>\n#include <linux/u64_stats_sync.h>\n\n#include  \"./rtl8367c/include/rtk_switch.h\"\n#include  \"./rtl8367c/include/port.h\"\n#include  \"./rtl8367c/include/vlan.h\"\n#include  \"./rtl8367c/include/rtl8367c_asicdrv_port.h\"\n#include  \"./rtl8367c/include/stat.h\"\n#include  \"./rtl8367c/include/l2.h\"\n#include  \"./rtl8367c/include/smi.h\"\n#include  \"./rtl8367c/include/mirror.h\"\n#include  \"./rtl8367c/include/igmp.h\"\n#include  \"./rtl8367c/include/leaky.h\"\n\nstatic struct proc_dir_entry *proc_reg_dir;\nstatic struct proc_dir_entry *proc_esw_cnt;\nstatic struct proc_dir_entry *proc_vlan_cnt;\nstatic struct proc_dir_entry *proc_mac_tbl;\nstatic struct proc_dir_entry *proc_reg;\nstatic struct proc_dir_entry *proc_phyreg;\nstatic struct proc_dir_entry *proc_mirror;\nstatic struct proc_dir_entry *proc_igmp;\n\n#define PROCREG_ESW_CNT         \"esw_cnt\"\n#define PROCREG_VLAN            \"vlan\"\n#define PROCREG_MAC_TBL            \"mac_tbl\"\n#define PROCREG_REG            \"reg\"\n#define PROCREG_PHYREG            \"phyreg\"\n#define PROCREG_MIRROR            \"mirror\"\n#define PROCREG_IGMP            \"igmp\"\n#define PROCREG_DIR             \"rtk_gsw\"\n\n#define RTK_SW_VID_RANGE        16\n\nstatic void rtk_dump_mib_type(rtk_stat_port_type_t cntr_idx)\n{\n\trtk_port_t port;\n\trtk_stat_counter_t Cntr;\n\n\tfor (port = UTP_PORT0; port < (UTP_PORT0 + 5); port++) {\n\t\trtk_stat_port_get(port, cntr_idx, &Cntr);\n\t\tprintk(\"%8llu\", Cntr);\n\t}\n\n\tfor (port = EXT_PORT0; port < (EXT_PORT0 + 2); port++) {\n\t\trtk_stat_port_get(port, cntr_idx, &Cntr);\n\t\tprintk(\"%8llu\", Cntr);\n\t}\n\t\n\tprintk(\"\\n\");\n}\nstatic void rtk_hal_dump_mib(void)\n{\n\n\tprintk(\"==================%8s%8s%8s%8s%8s%8s%8s\\n\", \"Port0\", \"Port1\",\n\t       \"Port2\", \"Port3\", \"Port4\", \"Port16\", \"Port17\");\n\t/* Get TX Unicast Pkts */\n\tprintk(\"TX Unicast Pkts  :\");\n\trtk_dump_mib_type(STAT_IfOutUcastPkts);\n\t/* Get TX Multicast Pkts */\n\tprintk(\"TX Multicast Pkts:\");\n\trtk_dump_mib_type(STAT_IfOutMulticastPkts);\n\t/* Get TX BroadCast Pkts */\n\tprintk(\"TX BroadCast Pkts:\");\n\trtk_dump_mib_type(STAT_IfOutBroadcastPkts);\n\t/* Get TX Collisions */\n\t/* Get TX Puase Frames */\n\tprintk(\"TX Pause Frames  :\");\n\trtk_dump_mib_type(STAT_Dot3OutPauseFrames);\n\t/* Get TX Drop Events */\n\t/* Get RX Unicast Pkts */\n\tprintk(\"RX Unicast Pkts  :\");\n\trtk_dump_mib_type(STAT_IfInUcastPkts);\n\t/* Get RX Multicast Pkts */\n\tprintk(\"RX Multicast Pkts:\");\n\trtk_dump_mib_type(STAT_IfInMulticastPkts);\n\t/* Get RX Broadcast Pkts */\n\tprintk(\"RX Broadcast Pkts:\");\n\trtk_dump_mib_type(STAT_IfInBroadcastPkts);\n\t/* Get RX FCS Erros */\n\tprintk(\"RX FCS Errors    :\");\n\trtk_dump_mib_type(STAT_Dot3StatsFCSErrors);\n\t/* Get RX Undersize Pkts */\n\tprintk(\"RX Undersize Pkts:\");\n\trtk_dump_mib_type(STAT_EtherStatsUnderSizePkts);\n\t/* Get RX Discard Pkts */\n\tprintk(\"RX Discard Pkts  :\");\n\trtk_dump_mib_type(STAT_Dot1dTpPortInDiscards);\n\t/* Get RX Fragments */\n\tprintk(\"RX Fragments     :\");\n\trtk_dump_mib_type(STAT_EtherStatsFragments);\n\t/* Get RX Oversize Pkts */\n\tprintk(\"RX Oversize Pkts :\");\n\trtk_dump_mib_type(STAT_EtherOversizeStats);\n\t/* Get RX Jabbers */\n\tprintk(\"RX Jabbers       :\");\n\trtk_dump_mib_type(STAT_EtherStatsJabbers);\n\t/* Get RX Pause Frames */\n\tprintk(\"RX Pause Frames  :\");\n\trtk_dump_mib_type(STAT_Dot3InPauseFrames);\n\t/* clear MIB */\n\trtk_stat_global_reset();\n\t\n}\n\nstatic int rtk_hal_dump_vlan(void)\n{\n\trtk_vlan_cfg_t vlan;\n\tint i;\n\n\tprintk(\"vid    portmap\\n\");\n\tfor (i = 0; i < RTK_SW_VID_RANGE; i++) {\n\t\trtk_vlan_get(i, &vlan);\n\t\tprintk(\"%3d    \", i);\n\t\tprintk(\"%c\",\n\t\t       RTK_PORTMASK_IS_PORT_SET(vlan.mbr,\n\t                                UTP_PORT0) ? '1' : '-');\n\t\tprintk(\"%c\",\n\t       \tRTK_PORTMASK_IS_PORT_SET(vlan.mbr,\n\t                                UTP_PORT1) ? '1' : '-');\n\t\tprintk(\"%c\",\n\t\t       RTK_PORTMASK_IS_PORT_SET(vlan.mbr,\n\t                                UTP_PORT2) ? '1' : '-');\n\t\tprintk(\"%c\",\n\t\t       RTK_PORTMASK_IS_PORT_SET(vlan.mbr,\n\t                                UTP_PORT3) ? '1' : '-');\n\t\tprintk(\"%c\",\n\t       \tRTK_PORTMASK_IS_PORT_SET(vlan.mbr,\n\t                                UTP_PORT4) ? '1' : '-');\n\t\tprintk(\"%c\",\n\t\t       RTK_PORTMASK_IS_PORT_SET(vlan.mbr,\n\t                                EXT_PORT0) ? '1' : '-');\n\t\tprintk(\"%c\",\n\t\t       RTK_PORTMASK_IS_PORT_SET(vlan.mbr,\n\t                                EXT_PORT1) ? '1' : '-');\n\t\tprintk(\"\\n\");\n\t}\n\t\n\treturn 0;\n}\n\nstatic void rtk_hal_dump_table(void)\n{\n\trtk_uint32 i;\n\trtk_uint32 address = 0;\n\trtk_l2_ucastAddr_t l2_data;\n\trtk_l2_ipMcastAddr_t ipMcastAddr;\n\trtk_l2_age_time_t age_timout;\n\n\trtk_l2_aging_get(&age_timout);\n\tprintk(\"Mac table age timeout =%d\\n\",(unsigned int)age_timout);\n\n\tprintk(\"hash  port(0:17)   fid   vid  mac-address\\n\");\n\twhile (1) {\n\t\tif (rtk_l2_addr_next_get(READMETHOD_NEXT_L2UC, UTP_PORT0, &address, &l2_data) != RT_ERR_OK) {\n\t\t\tbreak;\n\t\t} else {\n\t\t\tprintk(\"%03x   \", l2_data.address);\n\t\t\tfor (i = 0; i < 5; i++)\n\t\t\t\tif ( l2_data.port == i)\n\t\t\t\t\tprintk(\"1\");\n\t\t\t\telse\n\t\t\t\t\tprintk(\"-\");\n\t\t\tfor (i = 16; i < 18; i++)\n\t\t\t\tif ( l2_data.port == i)\n\t\t\t\t\tprintk(\"1\");\n\t\t\t\telse\n\t\t\t\t\tprintk(\"-\");\n\n\t\t\tprintk(\"      %2d\", l2_data.fid);\n\t\t\tprintk(\"  %4d\", l2_data.cvid);\n\t\t\tprintk(\"  %02x%02x%02x%02x%02x%02x\\n\", l2_data.mac.octet[0],\n\t\t\tl2_data.mac.octet[1], l2_data.mac.octet[2], l2_data.mac.octet[3],\n\t\t\tl2_data.mac.octet[4], l2_data.mac.octet[5]);\n\t\t\taddress ++;\n\t\t\t}\n\t}\n\n\taddress = 0;\n\twhile (1) {\n        if (rtk_l2_ipMcastAddr_next_get(&address, &ipMcastAddr) != RT_ERR_OK) {\n            break;\n        } else {\n            printk(\"%03x   \", ipMcastAddr.address);\n            for (i = 0; i < 5; i++)\n                printk(\"%c\", RTK_PORTMASK_IS_PORT_SET(ipMcastAddr.portmask, i) ? '1' : '-');\n            for (i = 16; i < 18; i++)\n                printk(\"%c\", RTK_PORTMASK_IS_PORT_SET(ipMcastAddr.portmask, i) ? '1' : '-');\n\t\t\tprintk(\"                \");\n\t\t\tprintk(\"01005E%06x\\n\", (ipMcastAddr.dip & 0xefffff));\n            address ++;\n            }\n    }\n}\n\nstatic void rtk_hal_clear_table(void)\n{\n        rtk_api_ret_t ret;\n\n        ret = rtk_l2_table_clear();\n        if (ret != RT_ERR_OK)\n                printk(\"rtk_l2_table_clear failed\\n\");\n}\n\nstatic void rtk_hal_read_reg(unsigned int reg_addr)\n{\n        ret_t retVal;\n\t unsigned int reg_val;\n\n        retVal = smi_read(reg_addr, &reg_val);\n\n        if(retVal != RT_ERR_OK)\n                printk(\"switch reg read failed\\n\");\n        else\n                printk(\"reg0x%x = 0x%x\\n\", reg_addr, reg_val);\n}\n\nstatic void rtk_hal_write_reg(unsigned int reg_addr , unsigned int reg_val)\n{\n        ret_t retVal;\n\n    retVal = smi_write(reg_addr, reg_val);\n\n    if(retVal != RT_ERR_OK)\n        printk(\"switch reg write failed\\n\");\n    else\n        printk(\"write switch reg0x%x 0x%x success\\n\", reg_addr, reg_val);\n}\n\nstatic void rtk_hal_get_phy_reg(unsigned int port ,unsigned int reg_addr )\n{\n        ret_t retVal;\n        rtk_port_phy_data_t Data;\n\n        retVal = rtk_port_phyReg_get(port, reg_addr, &Data);\n        if (retVal == RT_ERR_OK)\n                printk(\"Get: phy[%d].reg[%d] = 0x%04x\\n\", port, reg_addr, Data);\n        else\n                printk(\"read phy reg failed\\n\");\n}\n\nstatic void rtk_hal_set_phy_reg(unsigned int port ,unsigned int reg_addr,unsigned int reg_val)\n{\n        ret_t retVal;\n\n        retVal = rtk_port_phyReg_set(port, reg_addr, reg_val);\n        if (retVal == RT_ERR_OK)\n                printk(\"Set: phy[%d].reg[%d] = 0x%04x\\n\", port, reg_addr, reg_val);\n        else\n                printk(\"write phy reg failed\\n\");\n}\n\nstatic void rtk_hal_set_port_mirror(unsigned int port ,unsigned int rx_port_map,unsigned int tx_port_map)\n{\n        rtk_portmask_t rx_portmask;\n        rtk_portmask_t tx_portmask;\n        rtk_api_ret_t ret;\n        int i;\n\n        rtk_mirror_portIso_set(ENABLED);\n        RTK_PORTMASK_CLEAR(rx_portmask);\n        RTK_PORTMASK_CLEAR(tx_portmask);\n\n\tfor (i = 0; i < 5; i++)\n                if (rx_port_map & (1 << i))\n                        RTK_PORTMASK_PORT_SET(rx_portmask, i);\n\n        for (i = 0; i < 2; i++)\n                if (rx_port_map & (1 << (i + 5)))\n                        RTK_PORTMASK_PORT_SET(rx_portmask, (i + EXT_PORT0));\n\n        RTK_PORTMASK_CLEAR(tx_portmask);\n\n\tfor (i = 0; i < 5; i++)\n\t\tif (tx_port_map & (1 << i))\n\t\t           RTK_PORTMASK_PORT_SET(tx_portmask, i);\n\n\tfor (i = 0; i < 2; i++)\n\t\tif (tx_port_map & (1 << (i + 5)))\n\t\t\tRTK_PORTMASK_PORT_SET(tx_portmask, (i + EXT_PORT0));\n\n\tret = rtk_mirror_portBased_set(port, &rx_portmask, &tx_portmask);\n\n        if (!ret)\n                printk(\"rtk_mirror_portBased_set success\\n\");\n\n}\n\nstatic void rtk_hal_enable_igmpsnoop(int hw_on)\n{\n        rtk_api_ret_t ret;\n        rtk_portmask_t pmask;\n\n        ret = rtk_igmp_init();\n        if (hw_on == 1) {\n                RTK_PORTMASK_CLEAR(pmask);\n                RTK_PORTMASK_PORT_SET(pmask, EXT_PORT0);\n                ret |= rtk_igmp_static_router_port_set(&pmask);\n                ret |= rtk_igmp_protocol_set(UTP_PORT4, PROTOCOL_IGMPv1, IGMP_ACTION_FORWARD);\n                ret |= rtk_igmp_protocol_set(UTP_PORT4, PROTOCOL_IGMPv2, IGMP_ACTION_FORWARD);\n                ret |= rtk_igmp_protocol_set(UTP_PORT4, PROTOCOL_MLDv1, IGMP_ACTION_FORWARD);\n                ret |= rtk_igmp_protocol_set(EXT_PORT1, PROTOCOL_IGMPv1, IGMP_ACTION_FORWARD);\n                ret |= rtk_igmp_protocol_set(EXT_PORT1, PROTOCOL_IGMPv2, IGMP_ACTION_FORWARD);\n                ret |= rtk_igmp_protocol_set(EXT_PORT1, PROTOCOL_MLDv1, IGMP_ACTION_FORWARD);\n                ret |= rtk_igmp_protocol_set(UTP_PORT0, PROTOCOL_IGMPv3, IGMP_ACTION_ASIC);\n                ret |= rtk_igmp_protocol_set(UTP_PORT1, PROTOCOL_IGMPv3, IGMP_ACTION_ASIC);\n                ret |= rtk_igmp_protocol_set(UTP_PORT2, PROTOCOL_IGMPv3, IGMP_ACTION_ASIC);\n                ret |= rtk_igmp_protocol_set(UTP_PORT3, PROTOCOL_IGMPv3, IGMP_ACTION_ASIC);\n                ret |= rtk_igmp_protocol_set(EXT_PORT0, PROTOCOL_IGMPv3, IGMP_ACTION_ASIC);\n\n                ret |= rtk_leaky_vlan_set(LEAKY_IPMULTICAST, ENABLED);\n                ret |= rtk_l2_ipMcastForwardRouterPort_set(DISABLED);\n                /* drop unknown multicast packets*/\n                /* ret |= rtk_trap_unknownMcastPktAction_set(UTP_PORT4, MCAST_IPV4, MCAST_ACTION_DROP);*/\n        } else {\n\t\tRTK_PORTMASK_CLEAR(pmask);\n\t\tRTK_PORTMASK_PORT_SET(pmask, EXT_PORT0);\n\t\tRTK_PORTMASK_PORT_SET(pmask, EXT_PORT1);\n                ret |= rtk_igmp_protocol_set(UTP_PORT0, PROTOCOL_IGMPv3, IGMP_ACTION_ASIC);\n                ret |= rtk_igmp_protocol_set(UTP_PORT1, PROTOCOL_IGMPv3, IGMP_ACTION_ASIC);\n                ret |= rtk_igmp_protocol_set(UTP_PORT2, PROTOCOL_IGMPv3, IGMP_ACTION_ASIC);\n                ret |= rtk_igmp_protocol_set(UTP_PORT3, PROTOCOL_IGMPv3, IGMP_ACTION_ASIC);\n                ret |= rtk_igmp_protocol_set(EXT_PORT0, PROTOCOL_IGMPv3, IGMP_ACTION_ASIC);\n\n                ret |= rtk_igmp_static_router_port_set(&pmask);\n        }\n\n        if(ret != RT_ERR_OK)\n                printk(\"enable switch igmpsnoop failed\\n\");\n\n}\n\nstatic void rtk_hal_disable_igmpsnoop(void)\n{\n        if (rtk_igmp_state_set(DISABLED) != RT_ERR_OK)\n                printk(\"Disable IGMP SNOOPING failed\\n\");\n}\n\nstatic ssize_t mac_tbl_write(struct file *file,\n                            const char __user *buffer, size_t count,\n                            loff_t *data)\n{\n\trtk_hal_clear_table();\n\n        return count;\n}\n\n\nstatic ssize_t phyreg_ops(struct file *file,\n                            const char __user *buffer, size_t count,\n                            loff_t *data)\n{\n        char buf[64];\n\t unsigned int port;\n        unsigned int offset;\n        unsigned int val;\n\n        memset(buf, 0, 64);\n\n        if (copy_from_user(buf, buffer, count))\n                return -EFAULT;\n\n\n        if(buf[0] == 'w') {\n\n                if(sscanf(buf, \"w %d %x %x\", &port,&offset,&val) == -1)\n                        return -EFAULT;\n                else\n                        rtk_hal_set_phy_reg(port,offset,val);\n\n        } else {\n\n\t\tif(sscanf(buf, \"r %d %x\",&port, &offset) == -1)\n                        return -EFAULT;\n                else\n                        rtk_hal_get_phy_reg(port,offset);\n        }\n\n        return count;\n}\n\nstatic ssize_t reg_ops(struct file *file,\n                            const char __user *buffer, size_t count,\n                            loff_t *data)\n{\n        char buf[64];\n        unsigned int offset;\n        unsigned int val;\n\n        memset(buf, 0, 64);\n\n        if (copy_from_user(buf, buffer, count))\n                return -EFAULT;\n\n\n        if(buf[0] == 'w') {\n\n                if(sscanf(buf, \"w %x %x\", &offset,&val) == -1)\n                        return -EFAULT;\n                else\n                        rtk_hal_write_reg(offset,val);\n\n        } else {\n\n                if(sscanf(buf, \"r %x\", &offset) == -1)\n                        return -EFAULT;\n                else\n                        rtk_hal_read_reg(offset);\n        }\n\n        return count;\n}\n\nstatic ssize_t mirror_ops(struct file *file,\n                            const char __user *buffer, size_t count,\n                            loff_t *data)\n{\n        char buf[64];\n\t unsigned int port;\n        unsigned int tx_map,rx_map;\n\n        memset(buf, 0, 64);\n\n        if (copy_from_user(buf, buffer, count))\n                return -EFAULT;\n\n\tif(sscanf(buf, \"%d %x %x\", &port,&rx_map,&tx_map) == -1)\n\t\treturn -EFAULT;\n\telse\n\t\trtk_hal_set_port_mirror(port,rx_map,tx_map);\n\n        return count;\n}\n\n\nstatic ssize_t igmp_ops(struct file *file,\n                            const char __user *buffer, size_t count,\n                            loff_t *data)\n{\n        char buf[8];\n        unsigned int ops;\n\n        if (copy_from_user(buf, buffer, count))\n                return -EFAULT;\n\n\tif(sscanf(buf, \"%d\", &ops) == -1)\n\t\treturn -EFAULT;\n\n        if(ops == 0)\n                rtk_hal_disable_igmpsnoop();\n\telse if (ops == 1)\n\t\trtk_hal_enable_igmpsnoop(0);\n\telse //hw igmp\n\t\trtk_hal_enable_igmpsnoop(1);\n\n        return count;\n}\n\n\nstatic int esw_cnt_read(struct seq_file *seq, void *v)\n{\n\trtk_hal_dump_mib();\n\treturn 0;\n}\n\nstatic int vlan_read(struct seq_file *seq, void *v)\n{\n\trtk_hal_dump_vlan();\n\treturn 0;\n}\n\nstatic int mac_tbl_read(struct seq_file *seq, void *v)\n{\n\trtk_hal_dump_table();\n\treturn 0;\n}\n\nstatic int reg_show(struct seq_file *seq, void *v)\n{\n\treturn 0;\n}\n\nstatic int phyreg_show(struct seq_file *seq, void *v)\n{\n\treturn 0;\n}\n\nstatic int mirror_show(struct seq_file *seq, void *v)\n{\n\treturn 0;\n}\n\nstatic int igmp_show(struct seq_file *seq, void *v)\n{\n\treturn 0;\n}\n\nstatic int switch_count_open(struct inode *inode, struct file *file)\n{\n\treturn single_open(file, esw_cnt_read, 0);\n}\n\nstatic int switch_vlan_open(struct inode *inode, struct file *file)\n{\n\treturn single_open(file, vlan_read, 0);\n}\n\nstatic int mac_tbl_open(struct inode *inode, struct file *file)\n{\n\treturn single_open(file, mac_tbl_read, 0);\n}\n\nstatic int reg_open(struct inode *inode, struct file *file)\n{\n\treturn single_open(file, reg_show, 0);\n}\n\nstatic int phyreg_open(struct inode *inode, struct file *file)\n{\n\treturn single_open(file, phyreg_show, 0);\n}\n\nstatic int mirror_open(struct inode *inode, struct file *file)\n{\n\treturn single_open(file, mirror_show, 0);\n}\n\nstatic int igmp_open(struct inode *inode, struct file *file)\n{\n\treturn single_open(file, igmp_show, 0);\n}\n\n\nstatic const struct proc_ops switch_count_fops = {\n\t.proc_open = switch_count_open,\n\t.proc_read = seq_read,\n\t.proc_lseek = seq_lseek,\n\t.proc_release = single_release\n};\n\nstatic const struct proc_ops switch_vlan_fops = {\n\t.proc_open = switch_vlan_open,\n\t.proc_read = seq_read,\n\t.proc_lseek = seq_lseek,\n\t.proc_release = single_release\n};\n\nstatic const struct proc_ops mac_tbl_fops = {\n\t.proc_open = mac_tbl_open,\n\t.proc_read = seq_read,\n\t.proc_lseek = seq_lseek,\n\t.proc_write = mac_tbl_write,\n\t.proc_release = single_release\n};\n\nstatic const struct proc_ops reg_fops = {\n\t.proc_open = reg_open,\n\t.proc_read = seq_read,\n\t.proc_lseek = seq_lseek,\n\t.proc_write = reg_ops,\n\t.proc_release = single_release\n};\n\nstatic const struct proc_ops phyreg_fops = {\n\t.proc_open = phyreg_open,\n\t.proc_read = seq_read,\n\t.proc_lseek = seq_lseek,\n\t.proc_write = phyreg_ops,\n\t.proc_release = single_release\n};\n\nstatic const struct proc_ops mirror_fops = {\n\t.proc_open = mirror_open,\n\t.proc_read = seq_read,\n\t.proc_lseek = seq_lseek,\n\t.proc_write = mirror_ops,\n\t.proc_release = single_release\n};\n\nstatic const struct proc_ops igmp_fops = {\n\t.proc_open = igmp_open,\n\t.proc_read = seq_read,\n\t.proc_lseek = seq_lseek,\n\t.proc_write = igmp_ops,\n\t.proc_release = single_release\n};\n\nint gsw_debug_proc_init(void)\n{\n\n\tif (!proc_reg_dir)\n\t\tproc_reg_dir = proc_mkdir(PROCREG_DIR, NULL);\n\n\tproc_esw_cnt =\n\tproc_create(PROCREG_ESW_CNT, 0, proc_reg_dir, &switch_count_fops);\n\n\tif (!proc_esw_cnt)\n\t\tpr_err(\"!! FAIL to create %s PROC !!\\n\", PROCREG_ESW_CNT);\n\n\tproc_vlan_cnt =\n\tproc_create(PROCREG_VLAN, 0, proc_reg_dir, &switch_vlan_fops);\n\n\tif (!proc_vlan_cnt)\n\t\tpr_err(\"!! FAIL to create %s PROC !!\\n\", PROCREG_VLAN);\n\n\tproc_mac_tbl =\n\tproc_create(PROCREG_MAC_TBL, 0, proc_reg_dir, &mac_tbl_fops);\n\n\tif (!proc_mac_tbl)\n\t\tpr_err(\"!! FAIL to create %s PROC !!\\n\", PROCREG_MAC_TBL);\n\n\tproc_reg =\n\tproc_create(PROCREG_REG, 0, proc_reg_dir, &reg_fops);\n\n\tif (!proc_reg)\n\t\tpr_err(\"!! FAIL to create %s PROC !!\\n\", PROCREG_REG);\n\n\tproc_phyreg =\n\tproc_create(PROCREG_PHYREG, 0, proc_reg_dir, &phyreg_fops);\n\n\tif (!proc_phyreg)\n\t\tpr_err(\"!! FAIL to create %s PROC !!\\n\", PROCREG_PHYREG);\n\n\tproc_mirror =\n\tproc_create(PROCREG_MIRROR, 0, proc_reg_dir, &mirror_fops);\n\n\tif (!proc_mirror)\n\t\tpr_err(\"!! FAIL to create %s PROC !!\\n\", PROCREG_MIRROR);\n\n\tproc_igmp =\n\tproc_create(PROCREG_IGMP, 0, proc_reg_dir, &igmp_fops);\n\n\tif (!proc_igmp)\n\t\tpr_err(\"!! FAIL to create %s PROC !!\\n\", PROCREG_IGMP);\n\n\treturn 0;\n}\n\nvoid gsw_debug_proc_exit(void)\n{\n\tif (proc_esw_cnt)\n\t\tremove_proc_entry(PROCREG_ESW_CNT, proc_reg_dir);\n}\n\n\n"
  },
  {
    "path": "target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367s_mdio.c",
    "content": "/*\n * This program is free software; you can redistribute it and/or\n * modify it under the terms of the GNU General Public License\n * as published by the Free Software Foundation; either version 2\n * of the License, or (at your option) any later version.\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n * GNU General Public License for more details.\n *\n */\n \n#include <linux/kernel.h>\n#include <linux/module.h>\n#include <linux/init.h>\n#include <linux/device.h>\n#include <linux/delay.h>\n#include <linux/of_mdio.h>\n#include <linux/of_platform.h>\n#include <linux/of_gpio.h>\n\n\n#include  \"./rtl8367c/include/rtk_switch.h\"\n#include  \"./rtl8367c/include/port.h\"\n#include  \"./rtl8367c/include/vlan.h\"\n#include  \"./rtl8367c/include/rtl8367c_asicdrv_port.h\"\n\nstruct rtk_gsw {\n \tstruct device           *dev;\n \tstruct mii_bus          *bus;\n\tint reset_pin;\n};\n\nstatic struct rtk_gsw *_gsw;\n\nextern int gsw_debug_proc_init(void);\nextern void gsw_debug_proc_exit(void);\n\n#ifdef CONFIG_SWCONFIG\nextern int rtl8367s_swconfig_init( void (*reset_func)(void) );\n#endif\n\n/*mii_mgr_read/mii_mgr_write is the callback API for rtl8367 driver*/\nunsigned int mii_mgr_read(unsigned int phy_addr,unsigned int phy_register,unsigned int *read_data)\n{\n\tstruct mii_bus *bus = _gsw->bus;\n\n\tmutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);\n\n\t*read_data = bus->read(bus, phy_addr, phy_register);\n\n\tmutex_unlock(&bus->mdio_lock);\n\n\treturn 0;\n}\n\nunsigned int mii_mgr_write(unsigned int phy_addr,unsigned int phy_register,unsigned int write_data)\n{\n\tstruct mii_bus *bus =  _gsw->bus;\n\n\tmutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);\n\n\tbus->write(bus, phy_addr, phy_register, write_data);\n\n\tmutex_unlock(&bus->mdio_lock);\n\t\n\treturn 0;\n}\n\nstatic int rtl8367s_hw_reset(void)\n{\n\tstruct rtk_gsw *gsw = _gsw;\n\tint ret;\n\n\tif (gsw->reset_pin < 0)\n\t\treturn 0;\n\n\tret = devm_gpio_request(gsw->dev, gsw->reset_pin, \"mediatek,reset-pin\");\n\n\tif (ret)\n                printk(\"fail to devm_gpio_request\\n\");\n\n\tgpio_direction_output(gsw->reset_pin, 0);\n\n\tusleep_range(1000, 1100);\n\n\tgpio_set_value(gsw->reset_pin, 1);\n\n\tmdelay(500);\n\n\tdevm_gpio_free(gsw->dev, gsw->reset_pin);\n\n\treturn 0;\n\t\n}\n\nstatic int rtl8367s_vlan_config(int want_at_p0)\n{\n\trtk_vlan_cfg_t vlan1, vlan2;\n\t\n\t/* Set LAN/WAN VLAN partition */\n\tmemset(&vlan1, 0x00, sizeof(rtk_vlan_cfg_t));\n\n\tRTK_PORTMASK_PORT_SET(vlan1.mbr, EXT_PORT0);\n\tRTK_PORTMASK_PORT_SET(vlan1.mbr, UTP_PORT1);\n\tRTK_PORTMASK_PORT_SET(vlan1.mbr, UTP_PORT2);\n\tRTK_PORTMASK_PORT_SET(vlan1.mbr, UTP_PORT3);\n\tRTK_PORTMASK_PORT_SET(vlan1.untag, EXT_PORT0);\n\tRTK_PORTMASK_PORT_SET(vlan1.untag, UTP_PORT1);\n\tRTK_PORTMASK_PORT_SET(vlan1.untag, UTP_PORT2);\n\tRTK_PORTMASK_PORT_SET(vlan1.untag, UTP_PORT3);\n  \n\t if (want_at_p0) {\n\t\tRTK_PORTMASK_PORT_SET(vlan1.mbr, UTP_PORT4);\n\t\tRTK_PORTMASK_PORT_SET(vlan1.untag, UTP_PORT4);\n        } else {\n\t\tRTK_PORTMASK_PORT_SET(vlan1.mbr, UTP_PORT0);\n\t\tRTK_PORTMASK_PORT_SET(vlan1.untag, UTP_PORT0);\n        }\n\n\tvlan1.ivl_en = 1;\n\t\n\trtk_vlan_set(1, &vlan1);\n\t\n\tmemset(&vlan2, 0x00, sizeof(rtk_vlan_cfg_t));\n\t\n\tRTK_PORTMASK_PORT_SET(vlan2.mbr, EXT_PORT1);\n\tRTK_PORTMASK_PORT_SET(vlan2.untag, EXT_PORT1);\n\n\tif (want_at_p0) {\n\t\tRTK_PORTMASK_PORT_SET(vlan2.mbr, UTP_PORT0);\n\t\tRTK_PORTMASK_PORT_SET(vlan2.untag, UTP_PORT0);\n\t} else {\n\t\tRTK_PORTMASK_PORT_SET(vlan2.mbr, UTP_PORT4);\n\t\tRTK_PORTMASK_PORT_SET(vlan2.untag, UTP_PORT4);\n\t}\n\n\tvlan2.ivl_en = 1;\n\trtk_vlan_set(2, &vlan2);\n\n\trtk_vlan_portPvid_set(EXT_PORT0, 1, 0);\n\trtk_vlan_portPvid_set(UTP_PORT1, 1, 0);\n\trtk_vlan_portPvid_set(UTP_PORT2, 1, 0);\n\trtk_vlan_portPvid_set(UTP_PORT3, 1, 0);\n\trtk_vlan_portPvid_set(EXT_PORT1, 2, 0);\n\n\tif (want_at_p0) {\n\t\trtk_vlan_portPvid_set(UTP_PORT0, 2, 0);\n\t\trtk_vlan_portPvid_set(UTP_PORT4, 1, 0);\n\t} else {\n\t\trtk_vlan_portPvid_set(UTP_PORT0, 1, 0);\n\t\trtk_vlan_portPvid_set(UTP_PORT4, 2, 0);\n\t}\n\n\treturn 0;\t\n}\n\nstatic int rtl8367s_hw_init(void)\n{\n\n\trtl8367s_hw_reset();\n\n\tif(rtk_switch_init())\n\t        return -1;\n\n\tmdelay(500);\n\n\tif (rtk_vlan_reset())\n\t        return -1;\n\n\tif (rtk_vlan_init())\n\t        return -1;\n\n\treturn 0;\n}\n\nstatic void set_rtl8367s_sgmii(void)\n{\n\trtk_port_mac_ability_t mac_cfg;\n\trtk_mode_ext_t mode;\n\n\tmode = MODE_EXT_HSGMII;\n\tmac_cfg.forcemode = MAC_FORCE;\n\tmac_cfg.speed = PORT_SPEED_2500M;\n\tmac_cfg.duplex = PORT_FULL_DUPLEX;\n\tmac_cfg.link = PORT_LINKUP;\n\tmac_cfg.nway = DISABLED;\n\tmac_cfg.txpause = ENABLED;\n\tmac_cfg.rxpause = ENABLED;\n\trtk_port_macForceLinkExt_set(EXT_PORT0, mode, &mac_cfg);\n\trtk_port_sgmiiNway_set(EXT_PORT0, DISABLED);\n\trtk_port_phyEnableAll_set(ENABLED);\n\n}\n\nstatic void set_rtl8367s_rgmii(void)\n{\n\trtk_port_mac_ability_t mac_cfg;\n\trtk_mode_ext_t mode;\n\n\tmode = MODE_EXT_RGMII;\n\tmac_cfg.forcemode = MAC_FORCE;\n\tmac_cfg.speed = PORT_SPEED_1000M;\n\tmac_cfg.duplex = PORT_FULL_DUPLEX;\n\tmac_cfg.link = PORT_LINKUP;\n\tmac_cfg.nway = DISABLED;\n\tmac_cfg.txpause = ENABLED;\n\tmac_cfg.rxpause = ENABLED;\n\trtk_port_macForceLinkExt_set(EXT_PORT1, mode, &mac_cfg);\n\trtk_port_rgmiiDelayExt_set(EXT_PORT1, 1, 3);\n\trtk_port_phyEnableAll_set(ENABLED);\n\t\n}\n\nvoid init_gsw(void)\n{\n\trtl8367s_hw_init();\n\tset_rtl8367s_sgmii();\n\tset_rtl8367s_rgmii();\n}\n\n// bleow are platform driver\nstatic const struct of_device_id rtk_gsw_match[] = {\n\t{ .compatible = \"mediatek,rtk-gsw\" },\n\t{},\n};\n\nMODULE_DEVICE_TABLE(of, rtk_gsw_match);\n\nstatic int rtk_gsw_probe(struct platform_device *pdev)\n{\n\tstruct device_node *np = pdev->dev.of_node;\n\tstruct device_node *mdio;\n\tstruct mii_bus *mdio_bus;\n\tstruct rtk_gsw *gsw;\n\tconst char *pm;\n\n\tmdio = of_parse_phandle(np, \"mediatek,mdio\", 0);\n\n\tif (!mdio)\n\t\treturn -EINVAL;\n\n\tmdio_bus = of_mdio_find_bus(mdio);\n\n\tif (!mdio_bus)\n\t\treturn -EPROBE_DEFER;\n\n\tgsw = devm_kzalloc(&pdev->dev, sizeof(struct rtk_gsw), GFP_KERNEL);\n\t\n\tif (!gsw)\n\t\treturn -ENOMEM;\t\n\n\tgsw->dev = &pdev->dev;\n\n\tgsw->bus = mdio_bus;\n\n\tgsw->reset_pin = of_get_named_gpio(np, \"mediatek,reset-pin\", 0);\n\n\t_gsw = gsw;\n\n\tinit_gsw();\n\n\t//init default vlan or init swocnfig\n\tif(!of_property_read_string(pdev->dev.of_node,\n\t\t\t\t\t\t\"mediatek,port_map\", &pm)) {\n\n\t\tif (!strcasecmp(pm, \"wllll\"))\n\t\t\trtl8367s_vlan_config(1); \n\t\telse\n\t\t\trtl8367s_vlan_config(0);\n\t\t\n\t\t} else {\n#ifdef CONFIG_SWCONFIG\t\t\n\t\trtl8367s_swconfig_init(&init_gsw);\n#else\n\t\trtl8367s_vlan_config(0);\n#endif\n\t}\n\n\tgsw_debug_proc_init();\n\n\tplatform_set_drvdata(pdev, gsw);\n\n\treturn 0;\n\t\n}\n\nstatic int rtk_gsw_remove(struct platform_device *pdev)\n{\n\tplatform_set_drvdata(pdev, NULL);\n\tgsw_debug_proc_exit();\n\n\treturn 0;\n}\n\nstatic struct platform_driver gsw_driver = {\n\t.probe = rtk_gsw_probe,\n\t.remove = rtk_gsw_remove,\n\t.driver = {\n\t\t.name = \"rtk-gsw\",\n\t\t.owner = THIS_MODULE,\n\t\t.of_match_table = rtk_gsw_match,\n\t},\n};\n\nmodule_platform_driver(gsw_driver);\n\nMODULE_LICENSE(\"GPL\");\nMODULE_AUTHOR(\"Mark Lee <marklee0201@gmail.com>\");\nMODULE_DESCRIPTION(\"rtl8367c switch driver for MT7622\");\n\n"
  },
  {
    "path": "target/linux/mediatek/image/Makefile",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2012-2015 OpenWrt.org\n# Copyright (C) 2016-2017 LEDE project\n\ninclude $(TOPDIR)/rules.mk\ninclude $(INCLUDE_DIR)/image.mk\n\n# default all platform image(fit) build\ndefine Device/Default\n  PROFILES = Default $$(DEVICE_NAME)\n  KERNEL_NAME := Image\n  KERNEL = kernel-bin | lzma | \\\n\tfit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb\n  KERNEL_INITRAMFS = kernel-bin | lzma | \\\n\tfit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd\n  FILESYSTEMS := squashfs\n  DEVICE_DTS_DIR := $(DTS_DIR)\n  IMAGES := sysupgrade.bin\n  IMAGE/sysupgrade.bin := append-kernel | pad-to 128k | append-rootfs | \\\n\tpad-rootfs | append-metadata\nendef\n\ninclude $(SUBTARGET).mk\n\ndefine Image/Build\n\t$(call Image/Build/$(1),$(1))\nendef\n\n$(eval $(call BuildImage))\n\n"
  },
  {
    "path": "target/linux/mediatek/image/gen_scatterfile.sh",
    "content": "#!/bin/sh\n# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright © 2020 David Woodhouse <dwmw2@infradead.org>\n#\n# Generate as \"scatter file\" for use with the MediaTek SP Flash tool for\n# writing images to MediaTek boards. This can be used to write images\n# even on a bricked board which has no preloader installed, or broken\n# U-Boot.\n#\n# NOTE: At the time of writing (2020-07-20), the Linux tool linked from\n# the front page of https://spflashtool.com/ is out of date and does not\n# support MT7623. The newer v5.1916 found on the download page at\n# https://spflashtool.com/download/ has been tested on UniElec U7623 and\n# Banana Pi R2 from Linux, and does work.\n#\n\nSOC=$1\nIMAGE=${2%.gz}\nPROJECT=${3%-scatter.txt}\nDEVICENAME=\"$4\"\n\ncat <<EOF\n# OpenWrt eMMC scatter file for ${DEVICENAME}\n# For use with SP Flash Tool: https://spflashtool.com/download/\n#\n# Unzip the file system file ${PROJECT}-${IMAGE}.gz before flashing.\n# Connect the device's USB port, although it won't appear to the host yet.\n# Load this scatter file into the SP Flash Tool, select 'Format All + Download'\n# After pressing the 'Download' button, power on the board.\n# The /dev/ttyACM0 device should appear on USB and the tool should find it.\n\n- general: MTK_PLATFORM_CFG\n  info:\n    - config_version: V1.1.2\n      platform: ${SOC}\n      project: ${PROJECT}\n      storage: EMMC\n      boot_channel: MSDC_0\n      block_size: 0x20000\n\n- partition_index: SYS0\n  partition_name: PRELOADER\n  file_name: ${PROJECT}-preloader.bin\n  is_download: true\n  type: SV5_BL_BIN\n  linear_start_addr: 0x0\n  physical_start_addr: 0x0\n  partition_size: 0x40000\n  region: EMMC_BOOT_1\n  storage: HW_STORAGE_EMMC\n  boundary_check: true\n  is_reserved: false\n  operation_type: BOOTLOADERS\n  d_type: FALSE\n  reserve: 0x00\n\n- partition_index: SYS1\n  partition_name: OPENWRT\n  file_name: ${PROJECT}-${IMAGE}\n  is_download: true\n  type: NORMAL_ROM\n  linear_start_addr: 0x00000\n  physical_start_addr: 0x00000\n  partition_size: 0x4000000\n  region: EMMC_USER\n  storage: HW_STORAGE_EMMC\n  boundary_check: true\n  is_reserved: false\n  operation_type: UPDATE\n  d_type: FALSE\n  reserve: 0x00\nEOF\n"
  },
  {
    "path": "target/linux/mediatek/image/mt7622.mk",
    "content": "DTS_DIR := $(DTS_DIR)/mediatek\n\nifdef CONFIG_LINUX_5_4\n  KERNEL_LOADADDR := 0x44080000\nelse\n  KERNEL_LOADADDR := 0x44000000\nendif\n\ndefine Image/Prepare\n\t# For UBI we want only one extra block\n\trm -f $(KDIR)/ubi_mark\n\techo -ne '\\xde\\xad\\xc0\\xde' > $(KDIR)/ubi_mark\nendef\n\ndefine Build/buffalo-kernel-trx\n\t$(eval magic=$(word 1,$(1)))\n\t$(eval dummy=$(word 2,$(1)))\n\t$(eval kern_size=$(if $(KERNEL_SIZE),$(KERNEL_SIZE),0x400000))\n\n\t$(if $(dummy),touch $(dummy))\n\t$(STAGING_DIR_HOST)/bin/otrx create $@.new \\\n\t\t$(if $(magic),-M $(magic),) \\\n\t\t-f $@ \\\n\t\t$(if $(dummy),\\\n\t\t\t-a 0x20000 \\\n\t\t\t-b $$(( $(subst k, * 1024,$(kern_size)) )) \\\n\t\t\t-f $(dummy),)\n\tmv $@.new $@\nendef\n\ndefine Build/bl2\n\tcat $(STAGING_DIR_IMAGE)/mt7622-$1-bl2.img >> $@\nendef\n\ndefine Build/bl31-uboot\n\tcat $(STAGING_DIR_IMAGE)/mt7622_$1-u-boot.fip >> $@\nendef\n\ndefine Build/mt7622-gpt\n\tcp $@ $@.tmp 2>/dev/null || true\n\tptgen -g -o $@.tmp -a 1 -l 1024 \\\n\t\t$(if $(findstring sdmmc,$1), \\\n\t\t\t-H \\\n\t\t\t-t 0x83\t-N bl2\t\t-r\t-p 512k@512k \\\n\t\t) \\\n\t\t\t-t 0xef\t-N fip\t\t-r\t-p 2M@2M \\\n\t\t\t-t 0x83\t-N ubootenv\t-r\t-p 1M@4M \\\n\t\t\t\t-N recovery\t-r\t-p 32M@6M \\\n\t\t$(if $(findstring sdmmc,$1), \\\n\t\t\t\t-N install\t-r\t-p 7M@38M \\\n\t\t\t-t 0x2e -N production\t\t-p $(CONFIG_TARGET_ROOTFS_PARTSIZE)M@45M \\\n\t\t) \\\n\t\t$(if $(findstring emmc,$1), \\\n\t\t\t-t 0x2e -N production\t\t-p $(CONFIG_TARGET_ROOTFS_PARTSIZE)M@40M \\\n\t\t)\n\tcat $@.tmp >> $@\n\trm $@.tmp\nendef\n\ndefine Build/trx-nand\n\t# kernel: always use 4 MiB (-28 B or TRX header) to allow upgrades even\n\t#\t  if it grows up between releases\n\t# root: UBI with one extra block containing UBI mark to trigger erasing\n\t#\trest of partition\n\t$(STAGING_DIR_HOST)/bin/otrx create $@.new \\\n\t\t-M 0x32504844 \\\n\t\t-f $(IMAGE_KERNEL) -a 0x20000 -b 0x400000 \\\n\t\t-f $@ \\\n\t\t-A $(KDIR)/ubi_mark -a 0x20000\n\tmv $@.new $@\nendef\n\ndefine Device/bananapi_bpi-r64\n  DEVICE_VENDOR := Bananapi\n  DEVICE_MODEL := BPi-R64\n  DEVICE_DTS := mt7622-bananapi-bpi-r64\n  DEVICE_DTS_OVERLAY := mt7622-bananapi-bpi-r64-pcie1 mt7622-bananapi-bpi-r64-sata\n  DEVICE_PACKAGES := kmod-ata-ahci-mtk kmod-btmtkuart kmod-usb3 e2fsprogs mkf2fs f2fsck\n  ARTIFACTS := emmc-preloader.bin emmc-bl31-uboot.fip sdcard.img.gz snand-preloader.bin snand-bl31-uboot.fip\n  IMAGES := sysupgrade.itb\n  KERNEL_INITRAMFS_SUFFIX := -recovery.itb\n  ARTIFACT/emmc-preloader.bin\t:= bl2 emmc-2ddr\n  ARTIFACT/emmc-bl31-uboot.fip\t:= bl31-uboot bananapi_bpi-r64-emmc\n  ARTIFACT/snand-preloader.bin\t:= bl2 snand-2ddr\n  ARTIFACT/snand-bl31-uboot.fip\t:= bl31-uboot bananapi_bpi-r64-snand\n  ARTIFACT/sdcard.img.gz\t:= mt7622-gpt sdmmc |\\\n\t\t\t\t   pad-to 512k | bl2 sdmmc-2ddr |\\\n\t\t\t\t   pad-to 2048k | bl31-uboot bananapi_bpi-r64-sdmmc |\\\n\t\t\t\t   pad-to 6144k | append-image-stage initramfs-recovery.itb |\\\n\t\t\t\t   pad-to 38912k | mt7622-gpt emmc |\\\n\t\t\t\t   pad-to 39424k | bl2 emmc-2ddr |\\\n\t\t\t\t   pad-to 40960k | bl31-uboot bananapi_bpi-r64-emmc |\\\n\t\t\t\t   pad-to 43008k | bl2 snand-2ddr |\\\n\t\t\t\t   pad-to 43520k | bl31-uboot bananapi_bpi-r64-snand |\\\n\t\t\t\t   pad-to 46080k | append-image squashfs-sysupgrade.itb | gzip\n  KERNEL\t\t\t:= kernel-bin | gzip\n  KERNEL_INITRAMFS\t\t:= kernel-bin | lzma | fit lzma $$(DTS_DIR)/$$(DEVICE_DTS).dtb with-initrd | pad-to 128k\n  IMAGE/sysupgrade.itb\t\t:= append-kernel | fit gzip $$(DTS_DIR)/$$(DEVICE_DTS).dtb external-static-with-rootfs | append-metadata\nendef\nTARGET_DEVICES += bananapi_bpi-r64\n\ndefine Device/buffalo_wsr-2533dhp2\n  DEVICE_VENDOR := Buffalo\n  DEVICE_MODEL := WSR-2533DHP2\n  DEVICE_DTS := mt7622-buffalo-wsr-2533dhp2\n  DEVICE_DTS_DIR := ../dts\n  IMAGE_SIZE := 59392k\n  KERNEL_SIZE := 4096k\n  BLOCKSIZE := 128k\n  PAGESIZE := 2048\n  SUBPAGESIZE := 512\n  UBINIZE_OPTS := -E 5\n  BUFFALO_TAG_PLATFORM := MTK\n  BUFFALO_TAG_VERSION := 9.99\n  BUFFALO_TAG_MINOR := 9.99\n  IMAGES += factory.bin factory-uboot.bin\n  KERNEL_INITRAMFS := kernel-bin | lzma | \\\n\tfit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd | \\\n\tbuffalo-kernel-trx\n  IMAGE/factory.bin := append-ubi | trx-nand | \\\n\tbuffalo-enc WSR-2533DHP2 $$(BUFFALO_TAG_VERSION) -l | \\\n\tbuffalo-tag-dhp WSR-2533DHP2 JP JP | buffalo-enc-tag -l | buffalo-dhp-image\n  IMAGE/factory-uboot.bin := append-ubi | trx-nand\n  IMAGE/sysupgrade.bin := append-kernel | \\\n\tbuffalo-kernel-trx 0x32504844 $(KDIR)/tmp/$$(DEVICE_NAME).null | \\\n\tsysupgrade-tar kernel=$$$$@ | append-metadata\n  DEVICE_PACKAGES := swconfig\nendef\nTARGET_DEVICES += buffalo_wsr-2533dhp2\n\ndefine Device/elecom_wrc-2533gent\n  DEVICE_VENDOR := Elecom\n  DEVICE_MODEL := WRC-2533GENT\n  DEVICE_DTS := mt7622-elecom-wrc-2533gent\n  DEVICE_DTS_DIR := ../dts\n  DEVICE_PACKAGES := kmod-btmtkuart kmod-usb3 swconfig\nendef\nTARGET_DEVICES += elecom_wrc-2533gent\n\ndefine Device/linksys_e8450\n  DEVICE_VENDOR := Linksys\n  DEVICE_MODEL := E8450\n  DEVICE_ALT0_VENDOR := Belkin\n  DEVICE_ALT0_MODEL := RT3200\n  DEVICE_DTS := mt7622-linksys-e8450\n  DEVICE_DTS_DIR := ../dts\n  DEVICE_PACKAGES := kmod-mt7915e kmod-usb3\nendef\nTARGET_DEVICES += linksys_e8450\n\ndefine Device/linksys_e8450-ubi\n  DEVICE_VENDOR := Linksys\n  DEVICE_MODEL := E8450\n  DEVICE_VARIANT := UBI\n  DEVICE_ALT0_VENDOR := Belkin\n  DEVICE_ALT0_MODEL := RT3200\n  DEVICE_ALT0_VARIANT := UBI\n  DEVICE_DTS := mt7622-linksys-e8450-ubi\n  DEVICE_DTS_DIR := ../dts\n  DEVICE_PACKAGES := kmod-mt7915e kmod-usb3\n  UBINIZE_OPTS := -E 5\n  BLOCKSIZE := 128k\n  PAGESIZE := 2048\n  UBOOTENV_IN_UBI := 1\n  KERNEL_IN_UBI := 1\n  KERNEL := kernel-bin | gzip\n# recovery can also be used with stock firmware web-ui, hence the padding...\n  KERNEL_INITRAMFS := kernel-bin | lzma | \\\n\tfit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd | pad-to 128k\n  KERNEL_INITRAMFS_SUFFIX := -recovery.itb\n  IMAGES := sysupgrade.itb\n  IMAGE/sysupgrade.itb := append-kernel | fit gzip $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb external-static-with-rootfs | append-metadata\n  ARTIFACTS := preloader.bin bl31-uboot.fip\n  ARTIFACT/preloader.bin := bl2 snand-1ddr\n  ARTIFACT/bl31-uboot.fip := bl31-uboot linksys_e8450\nendef\nTARGET_DEVICES += linksys_e8450-ubi\n\ndefine Device/mediatek_mt7622-rfb1\n  DEVICE_VENDOR := MediaTek\n  DEVICE_MODEL := MTK7622 rfb1 AP\n  DEVICE_DTS := mt7622-rfb1\n  DEVICE_PACKAGES := kmod-ata-ahci-mtk kmod-btmtkuart kmod-usb3\nendef\nTARGET_DEVICES += mediatek_mt7622-rfb1\n\ndefine Device/mediatek_mt7622-rfb1-ubi\n  DEVICE_VENDOR := MediaTek\n  DEVICE_MODEL := MTK7622 rfb1 AP (UBI)\n  DEVICE_DTS := mt7622-rfb1-ubi\n  DEVICE_DTS_DIR := ../dts\n  DEVICE_PACKAGES := kmod-ata-ahci-mtk kmod-btmtkuart kmod-usb3\n  BOARD_NAME := mediatek,mt7622-rfb1-ubi\n  UBINIZE_OPTS := -E 5\n  BLOCKSIZE := 128k\n  PAGESIZE := 2048\n  KERNEL_SIZE := 4194304\n  IMAGE_SIZE := 32768k\n  IMAGES += factory.bin\n  IMAGE/factory.bin := append-kernel | pad-to $$(KERNEL_SIZE) | append-ubi | \\\n                check-size $$$$(IMAGE_SIZE)\n  IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata\nendef\nTARGET_DEVICES += mediatek_mt7622-rfb1-ubi\n\ndefine Device/ruijie_rg-ew3200gx-pro\n  DEVICE_VENDOR := Ruijie\n  DEVICE_MODEL := RG-EW3200GX PRO\n  DEVICE_DTS := mt7622-ruijie-rg-ew3200gx-pro\n  DEVICE_DTS_DIR := ../dts\n  DEVICE_PACKAGES := kmod-mt7915e\nendef\nTARGET_DEVICES += ruijie_rg-ew3200gx-pro\n\ndefine Device/totolink_a8000ru\n  DEVICE_VENDOR := TOTOLINK\n  DEVICE_MODEL := A8000RU\n  DEVICE_DTS := mt7622-totolink-a8000ru\n  DEVICE_DTS_DIR := ../dts\n  DEVICE_PACKAGES := swconfig\n  IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata\nendef\nTARGET_DEVICES += totolink_a8000ru\n\ndefine Device/ubnt_unifi-6-lr\n  DEVICE_VENDOR := Ubiquiti\n  DEVICE_MODEL := UniFi 6 LR\n  DEVICE_DTS_CONFIG := config@1\n  DEVICE_DTS := mt7622-ubnt-unifi-6-lr\n  DEVICE_DTS_DIR := ../dts\n  DEVICE_PACKAGES := kmod-mt7915e kmod-leds-ubnt-ledbar\nendef\nTARGET_DEVICES += ubnt_unifi-6-lr\n\ndefine Device/ubnt_unifi-6-lr-ubootmod\n  DEVICE_VENDOR := Ubiquiti\n  DEVICE_MODEL := UniFi 6 LR\n  DEVICE_VARIANT := U-Boot mod\n  DEVICE_DTS := mt7622-ubnt-unifi-6-lr-ubootmod\n  DEVICE_DTS_DIR := ../dts\n  DEVICE_PACKAGES := kmod-mt7915e kmod-leds-ubnt-ledbar\n  KERNEL := kernel-bin | lzma\n  KERNEL_INITRAMFS_SUFFIX := -recovery.itb\n  KERNEL_INITRAMFS := kernel-bin | lzma | fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd | pad-to 64k\n  IMAGES := sysupgrade.itb\n  IMAGE/sysupgrade.itb := append-kernel | fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb external-static-with-rootfs | pad-rootfs | append-metadata\n  ARTIFACTS := preloader.bin bl31-uboot.fip\n  ARTIFACT/preloader.bin := bl2 nor-2ddr\n  ARTIFACT/bl31-uboot.fip := bl31-uboot ubnt_unifi-6-lr\nendef\nTARGET_DEVICES += ubnt_unifi-6-lr-ubootmod\n\ndefine Device/xiaomi_redmi-router-ax6s\n  DEVICE_VENDOR := Xiaomi\n  DEVICE_MODEL := Redmi Router AX6S\n  DEVICE_ALT0_VENDOR := Xiaomi\n  DEVICE_ALT0_MODEL := Router AX3200\n  DEVICE_DTS := mt7622-xiaomi-redmi-router-ax6s\n  DEVICE_DTS_DIR := ../dts\n  BOARD_NAME := xiaomi,redmi-router-ax6s\n  DEVICE_PACKAGES := kmod-mt7915e\n  UBINIZE_OPTS := -E 5\n  IMAGES += factory.bin\n  BLOCKSIZE := 128k\n  PAGESIZE := 2048\n  KERNEL_SIZE := 4096k\n  KERNEL_INITRAMFS_SUFFIX := -recovery.itb\n  IMAGE/factory.bin := append-kernel | pad-to $$(KERNEL_SIZE) | append-ubi\n  IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata\nendef\nTARGET_DEVICES += xiaomi_redmi-router-ax6s\n"
  },
  {
    "path": "target/linux/mediatek/image/mt7623.mk",
    "content": "KERNEL_LOADADDR := 0x80008000\nDEVICE_VARS += UBOOT_TARGET UBOOT_OFFSET UBOOT_IMAGE\n\n# The bootrom of MT7623 expects legacy MediaTek headers present in\n# exactly the location also used for the primary GPT partition table.\n# (*MMC_BOOT and BRLYT)\n# Hence only MSDOS/MBR partitioning can work here.\n#\n#   ------------------------   Sector   Offset\n#   |  MBR + SDMMC_BOOT    |     0       0x0\n#   |----------------------|\n#   |     BRLYT header     |     1       0x200\n#   |----------------------|\n#   .                      .\n#   .                      .\n#   |----------------------|\n#   |                      |     4       0x800\n#   |                      |\n#   |     Preloader        |\n#   .                      .\n#   .                      .\n#   |                      |     639\n#   |----------------------|\n#   |   MBR partition #1   |     640     0x50000\n#   |                      |\n#   |       U-Boot         |\n#   .                      .\n#   .                      .\n#   |                      |     1663\n#   |----------------------|\n#   |   MBR partition #2   |\n#   |                      |\n#   |       Recovery       |\n#   .                      .\n#   .     (uImage.FIT)     .\n#   |                      |\n#   |----------------------|\n#   |   MBR partition #3   |\n#   |                      |\n#   |      Production      |\n#   |                      |\n#   |     (uImage.FIT,     |\n#   .     rootfs_Data.)    .\n#   .                      .\n#   |                      |\n#   ------------------------\n#\n# For eMMC boot, everything up to and including the preloader must be\n# written to /dev/mmcblk0boot0, with the SDMMC_BOOT header changed to\n# read EMMC_BOOT\\0 instead.\n#\n# The contents of the main eMMC are identical to the SD card layout,\n# with the preloader loading 512KiB of U-Boot starting at 0x50000.\n\ndefine Build/mt7623-mbr\n\tcp $@ $@.tmp 2>/dev/null || true\n\tptgen -o $@.tmp -h 4 -s 63 -a 0 -l 1024 \\\n\t\t\t-t 0x41\t-N uboot\t-p 1M@$(UBOOT_OFFSET) \\\n\t\t\t-t 0xea\t-N recovery\t-p 40M@4M \\\n\t\t\t-t 0x2e -N production\t-p $(CONFIG_TARGET_ROOTFS_PARTSIZE)M@48M\n\n\techo -en \\\n\t\t$(if $(findstring sdmmc,$1),\"SDMMC_BOOT\\x00\\x00\\x01\\x00\\x00\\x00\\x00\\x02\\x00\\x00\") \\\n\t\t$(if $(findstring emmc,$1),\"EMMC_BOOT\\x00\\x00\\x00\\x01\\x00\\x00\\x00\\x00\\x02\\x00\\x00\") \\\n\t\t| dd bs=1 of=\"$@.tmp\" seek=0 conv=notrunc\n\n\techo -en \"BRLYT\\x00\\x00\\x00\\x01\\x00\\x00\\x00\\x00\\x08\\x00\\x00\\x00\\x08\\x00\\x00\\x42\\x42\\x42\\x42\\x08\\x00\\x01\\x00\\x00\\x08\\x00\\x00\\x00\\x08\\x00\\x00\\x01\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\"\\\n\t\t| dd bs=1 of=\"$@.tmp\" seek=512 conv=notrunc\n\n\tcat $@.tmp >> $@\n\trm $@.tmp\nendef\n\ndefine Build/append-preloader\n\tcat $(STAGING_DIR_IMAGE)/$1-preloader.bin >> $@\nendef\n\ndefine Build/append-bootloader\n\tcat $(STAGING_DIR_IMAGE)/$1-$(UBOOT_IMAGE) >> $@\nendef\n\ndefine Build/scatterfile\n\t./gen_scatterfile.sh $(subst mt,MT,$(SUBTARGET)) \"$1\" \\\n\t\t$(subst -scatter.txt,,$(notdir $@)) \"$(DEVICE_TITLE)\" > $@\nendef\n\ndefine Device/bananapi_bpi-r2\n  DEVICE_VENDOR := Bananapi\n  DEVICE_MODEL := BPi-R2\n  DEVICE_DTS := mt7623n-bananapi-bpi-r2\n  DEVICE_PACKAGES := mkf2fs e2fsprogs kmod-usb3 kmod-ata-ahci\n  UBOOT_OFFSET := 320k\n  UBOOT_TARGET := mt7623n_bpir2\n  UBOOT_IMAGE := u-boot.bin\n  UBOOT_PATH := $(STAGING_DIR_IMAGE)/$$(UBOOT_TARGET)-$$(UBOOT_IMAGE)\n  IMAGES := sysupgrade.itb\n  KERNEL := kernel-bin | gzip\n  KERNEL_INITRAMFS_SUFFIX := -recovery.itb\n  KERNEL_INITRAMFS := kernel-bin | gzip | fit gzip $$(DTS_DIR)/$$(DEVICE_DTS).dtb with-initrd\n  IMAGE/sysupgrade.itb := append-kernel | fit gzip $$(DTS_DIR)/$$(DEVICE_DTS).dtb external-static-with-rootfs | append-metadata\n  ARTIFACT/preloader.bin := mt7623-mbr emmc |\\\n\t\t\t    pad-to 2k | append-preloader $$(UBOOT_TARGET)\n  ARTIFACT/u-boot.bin := append-uboot\n  ARTIFACT/sdcard.img.gz := mt7623-mbr sdmmc |\\\n\t\t\t    pad-to 2k | append-preloader $$(UBOOT_TARGET) |\\\n\t\t\t    pad-to $$(UBOOT_OFFSET) | append-bootloader $$(UBOOT_TARGET) |\\\n\t\t\t    pad-to 4092k | mt7623-mbr emmc |\\\n\t\t\t    pad-to 4M | append-image-stage initramfs-recovery.itb |\\\n\t\t\t    pad-to 48M | append-image squashfs-sysupgrade.itb |\\\n\t\t\t    gzip\n  ARTIFACTS := u-boot.bin preloader.bin sdcard.img.gz\n  SUPPORTED_DEVICES := bananapi,bpi-r2\nendef\nTARGET_DEVICES += bananapi_bpi-r2\n\ndefine Device/unielec_u7623-02\n  DEVICE_VENDOR := UniElec\n  DEVICE_MODEL := U7623-02\n  # When we use FIT images, U-Boot will populate the /memory node with the correct\n  # memory size discovered from the preloader, so we don't need separate builds.\n  DEVICE_DTS := mt7623a-unielec-u7623-02\n  DEVICE_DTS_DIR := ../dts\n  DEVICE_PACKAGES := kmod-fs-vfat kmod-nls-cp437 kmod-nls-iso8859-1 kmod-mmc \\\n       mkf2fs e2fsprogs kmod-usb-ohci kmod-usb2 kmod-usb3 kmod-ata-ahci\n  UBOOT_OFFSET := 256k\n  UBOOT_TARGET := mt7623a_unielec_u7623\n  UBOOT_IMAGE := u-boot-mtk.bin\n  UBOOT_PATH := $(STAGING_DIR_IMAGE)/$$(UBOOT_TARGET)-$$(UBOOT_IMAGE)\n  IMAGES := sysupgrade.itb\n  KERNEL := kernel-bin | gzip\n  KERNEL_INITRAMFS_SUFFIX := -recovery.itb\n  KERNEL_INITRAMFS := kernel-bin | gzip | fit gzip $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd\n  IMAGE/sysupgrade.itb := append-kernel | fit gzip $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb external-static-with-rootfs | append-metadata\n  ARTIFACT/u-boot.bin := append-uboot\n# vendor Preloader seems not to care about SDMMC_BOOT/EMMC_BOOT header,\n# but OpenWrt expects 'SDMM' magic for sysupgrade.\n  ARTIFACT/emmc.img.gz := mt7623-mbr sdmmc |\\\n\t\t\t    pad-to $$(UBOOT_OFFSET) | append-bootloader $$(UBOOT_TARGET) |\\\n\t\t\t    pad-to 4M | append-image-stage initramfs-recovery.itb |\\\n\t\t\t    pad-to 48M | append-image squashfs-sysupgrade.itb |\\\n\t\t\t    gzip | append-metadata\n  ARTIFACT/scatter.txt := scatterfile emmc.img.gz\n  ARTIFACTS := u-boot.bin scatter.txt emmc.img.gz\n  SUPPORTED_DEVICES += unielec,u7623-02-emmc-512m\nendef\nTARGET_DEVICES += unielec_u7623-02\n\n\n# Legacy helper for U7623 board\ndefine Build/fat-recovery-fs\n\trm -f $@.recovery\n\tmkfs.fat -C $@.recovery 3070\n\tcat $@.recovery >> $@\nendef\n\n# Legacy partial image for U7623\n# This preserves the vendor U-Boot and starts with a uImage at 0xA00\ndefine Device/unielec_u7623-02-emmc-512m-legacy\n  DEVICE_VENDOR := UniElec\n  DEVICE_MODEL := U7623-02\n  DEVICE_VARIANT := eMMC/512MiB RAM (legacy image)\n  DEVICE_DTS := mt7623a-unielec-u7623-02-emmc-512m\n  DEVICE_DTS_DIR := ../dts\n  KERNEL_NAME := zImage\n  KERNEL := kernel-bin | append-dtb | uImage none\n  KERNEL_INITRAMFS := kernel-bin | append-dtb | uImage none\n  DEVICE_PACKAGES := kmod-fs-vfat kmod-nls-cp437 kmod-nls-iso8859-1 kmod-mmc \\\n\tmkf2fs e2fsprogs kmod-usb-ohci kmod-usb2 kmod-usb3 kmod-ata-ahci \\\n\tpartx-utils\n  IMAGES := sysupgrade.bin.gz\n  IMAGE/sysupgrade.bin.gz := append-kernel |\\\n\t\t\t\tpad-to 4864k | fat-recovery-fs |\\\n\t\t\t\tpad-to 7936k | append-rootfs |\\\n\t\t\t\tgzip | append-metadata\n  SUPPORTED_DEVICES := unielec,u7623-02-emmc-512m\nendef\nTARGET_DEVICES += unielec_u7623-02-emmc-512m-legacy\n"
  },
  {
    "path": "target/linux/mediatek/image/mt7629.mk",
    "content": "KERNEL_LOADADDR := 0x40008000\n\ndefine Device/mediatek_mt7629-rfb\n  DEVICE_VENDOR := MediaTek\n  DEVICE_MODEL := MT7629 rfb AP\n  DEVICE_DTS := mt7629-rfb\n  DEVICE_PACKAGES := swconfig\nendef\nTARGET_DEVICES += mediatek_mt7629-rfb\n"
  },
  {
    "path": "target/linux/mediatek/modules.mk",
    "content": "define KernelPackage/ata-ahci-mtk\n  TITLE:=Mediatek AHCI Serial ATA support\n  KCONFIG:=CONFIG_AHCI_MTK\n  FILES:= \\\n\t$(LINUX_DIR)/drivers/ata/ahci_mtk.ko \\\n\t$(LINUX_DIR)/drivers/ata/libahci_platform.ko\n  AUTOLOAD:=$(call AutoLoad,40,libahci libahci_platform ahci_mtk,1)\n  $(call AddDepends/ata)\n  DEPENDS+=@(TARGET_mediatek_mt7622||TARGET_mediatek_mt7623)\nendef\n\ndefine KernelPackage/ata-ahci-mtk/description\n Mediatek AHCI Serial ATA host controllers\nendef\n\n$(eval $(call KernelPackage,ata-ahci-mtk))\n\ndefine KernelPackage/btmtkuart\n  SUBMENU:=Other modules\n  TITLE:=MediaTek HCI UART driver\n  DEPENDS:=@TARGET_mediatek_mt7622 +kmod-bluetooth +mt7622bt-firmware\n  KCONFIG:=CONFIG_BT_MTKUART\n  FILES:= \\\n\t$(LINUX_DIR)/drivers/bluetooth/btmtkuart.ko\n  AUTOLOAD:=$(call AutoProbe,btmtkuart)\nendef\n\n$(eval $(call KernelPackage,btmtkuart))\n\ndefine KernelPackage/sdhci-mtk\n  SUBMENU:=Other modules\n  TITLE:=Mediatek SDHCI driver\n  DEPENDS:=@TARGET_mediatek_mt7622 +kmod-sdhci\n  KCONFIG:=CONFIG_MMC_MTK \n  FILES:= \\\n\t$(LINUX_DIR)/drivers/mmc/host/mtk-sd.ko\n  AUTOLOAD:=$(call AutoProbe,mtk-sd,1)\nendef\n\n$(eval $(call KernelPackage,sdhci-mtk))\n\ndefine KernelPackage/leds-ubnt-ledbar\n  SUBMENU:=LED modules\n  TITLE:=Ubiquiti UniFi 6 LR LED support\n  KCONFIG:=CONFIG_LEDS_UBNT_LEDBAR\n  FILES:= \\\n\t$(LINUX_DIR)/drivers/leds/leds-ubnt-ledbar.ko\n  AUTOLOAD:=$(call AutoProbe,leds-ubnt-ledbar,1)\n  DEPENDS:=@TARGET_mediatek_mt7622 +kmod-i2c-core\nendef\n\ndefine KernelPackage/leds-ubnt-ledbar/description\n  LED support for Ubiquiti UniFi 6 LR\nendef\n\n$(eval $(call KernelPackage,leds-ubnt-ledbar))\n"
  },
  {
    "path": "target/linux/mediatek/mt7622/base-files/etc/board.d/01_leds",
    "content": ". /lib/functions/leds.sh\n. /lib/functions/uci-defaults.sh\n\nboard=$(board_name)\n\nboard_config_update\n\ncase $board in\nlinksys,e8450|\\\nlinksys,e8450-ubi)\n\tucidef_set_led_netdev \"wan\" \"WAN\" \"inet:blue\" \"wan\"\n\t;;\nxiaomi,redmi-router-ax6s)\n\tucidef_set_led_netdev \"wan\" \"WAN\" \"blue:net\" \"wan\"\n\t;;\nesac\n\nboard_config_flush\n\nexit 0\n"
  },
  {
    "path": "target/linux/mediatek/mt7622/base-files/etc/board.d/02_network",
    "content": "\n. /lib/functions.sh\n. /lib/functions/uci-defaults.sh\n. /lib/functions/system.sh\n\nmediatek_setup_interfaces()\n{\n\tlocal board=\"$1\"\n\n\tcase $board in\n\tbananapi,bpi-r64|\\\n\tlinksys,e8450|\\\n\tlinksys,e8450-ubi|\\\n\tmediatek,mt7622-rfb1|\\\n\tmediatek,mt7622-rfb1-ubi|\\\n\truijie,rg-ew3200gx-pro)\n\t\tucidef_set_interfaces_lan_wan \"lan1 lan2 lan3 lan4\" wan\n\t\t;;\n\tbuffalo,wsr-2533dhp2)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0:lan\" \"1:lan\" \"2:lan\" \"3:lan\" \"4:wan\" \"6@eth0\"\n\t\t;;\n\tubnt,unifi-6-lr|\\\n\tubnt,unifi-6-lr-ubootmod)\n\t\tucidef_set_interface_lan \"eth0\"\n\t\t;;\n\txiaomi,redmi-router-ax6s)\n\t\tucidef_set_interfaces_lan_wan \"lan1 lan2 lan3\" wan\n\t\t;;\n\t*)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\t  \"0:lan\" \"1:lan\" \"2:lan\" \"3:lan\" \"4:wan\" \"6u@eth0\" \"5u@eth1\"\n\t\t;;\n\tesac\n}\n\nmediatek_setup_macs()\n{\n\tlocal board=\"$1\"\n\tlocal lan_mac=\"\"\n\tlocal wan_mac=\"\"\n\tlocal label_mac=\"\"\n\n\tcase $board in\n\truijie,rg-ew3200gx-pro)\n\t\tlan_mac=$(macaddr_add $(get_mac_label) 1)\n\t\t;;\n\txiaomi,redmi-router-ax6s)\n\t\twan_mac=$(mtd_get_mac_ascii bdata ethaddr_wan)\n\t\tlabel_mac=$wan_mac\n\t\t;;\n\tesac\n\n\t[ -n \"$lan_mac\" ] && ucidef_set_interface_macaddr \"lan\" $lan_mac\n\t[ -n \"$wan_mac\" ] && ucidef_set_interface_macaddr \"wan\" $wan_mac\n\t[ -n \"$label_mac\" ] && ucidef_set_label_macaddr $label_mac\n}\n\nboard_config_update\nboard=$(board_name)\nmediatek_setup_interfaces $board\nmediatek_setup_macs $board\nboard_config_flush\n\nexit 0\n"
  },
  {
    "path": "target/linux/mediatek/mt7622/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac",
    "content": "[ \"$ACTION\" == \"add\" ] || exit 0\n\nPHYNBR=${DEVPATH##*/phy}\n\n[ -n $PHYNBR ] || exit 0\n\n. /lib/functions.sh\n. /lib/functions/system.sh\n\nboard=$(board_name)\n\ncase \"$board\" in\n\truijie,rg-ew3200gx-pro)\n\t\t[ \"$PHYNBR\" = \"0\" ] && macaddr_add $(get_mac_label) 3 > /sys${DEVPATH}/macaddress\n\t\t[ \"$PHYNBR\" = \"1\" ] && macaddr_add $(get_mac_label) 2 > /sys${DEVPATH}/macaddress\n\t\t;;\nesac\n"
  },
  {
    "path": "target/linux/mediatek/mt7622/base-files/etc/init.d/bootcount",
    "content": "#!/bin/sh /etc/rc.common\n\nSTART=99\n\nboot() {\n\tcase $(board_name) in\n\tlinksys,e8450)\n\t\tmtd erase senv || true\n\t\t;;\n\tesac\n}\n"
  },
  {
    "path": "target/linux/mediatek/mt7622/base-files/etc/uci-defaults/09_fix_crc",
    "content": ". /lib/functions.sh\n\nkernel_size=$(sed -n 's/mtd[0-9]*: \\([0-9a-f]*\\).*\"\\(kernel\\|linux\\)\".*/\\1/p' /proc/mtd)\n\ncase \"$(board_name)\" in\nbuffalo,wsr-2533dhp2)\n\tmtd -M 0x44485032 ${kernel_size:+-c 0x$kernel_size} fixtrx firmware && exit 0\n\texit 1\n\t;;\nesac\n"
  },
  {
    "path": "target/linux/mediatek/mt7622/base-files/lib/upgrade/buffalo.sh",
    "content": "# ======== dev note ========\n# for following buffalo MT7622 devices:\n#\n# - WSR-2533DHP2 (trx magic: \"DHP2\")\n# - WSR-2533DHP3 (trx magic: \"DHP3\")\n# - WSR-3200AX4S (trx magic: \"DHP3\")\n#\n# sysupgrade-tar image:\n#\n# This is for normal upgrading for OpenWrt.\n# use nand_do_upgrade with CI_KERNPART=\"firmware\"\n#\n# - if the size of new kernel is not equal with the current kernel's\n#   -> block upgrade and print a message about using TRX + UBI\n#      formatted image\n#   (should be flashed the new ubi contains rootfs + rootfs_data\n#   with the offset (=new padded kernel's end) if this case? But\n#   it maybe too hard for writing scripts...)\n#\n# TRX + UBI formatted image:\n#\n# This is for upgrading if the new kernel is larger than the\n# current kernel.\n#\n# ex:\n#   - stock firmware is installed in the flash and booted with\n#     OpenWrt initramfs image\n#   - kernel partition is increased from 4MiB in OpenWrt in the\n#     future\n#\n# packing TRX + UBI formatted image by tar is needed for image validation\n# with the metadata in the future?\n# ====== dev note end ======\n#\n# The mtd partitions \"firmware\" and \"Kernel2\" on NAND flash are os-image\n# partitions. These partitions are called as \"Image1/Image2\" in U-Boot\n# on WSR-2533DHP2, and they are checked conditions when booting.\n# \"Image1\" is always used for booting.\n#\n# == U-Boot Behaviors ==\n# - \"Image1\"/\"Image2\" images are good, images are different or\n#   \"Image2\" image is broken\n#   -> writes os-image to \"Image2\" from \"Image1\"\n#\n# - \"Image1\" image is broken\n#   -> writes os-image to \"Image1\" from \"Image2\"\n#\n# - \"Image1\"/\"Image2\" images are broken\n#   -> fall to U-Boot command line\n\nbuffalo_check_image() {\n\tlocal board=\"$1\"\n\tlocal boardname=\"$(echo $board | tr ',' '_')\"\n\tlocal magic=\"$2\"\n\tlocal fw_image=\"$3\"\n\n\t# return error state if TRX + UBI formatted image specified\n\t# to notify about configurations\n\tif [ \"$magic\" = \"44485032\" -o \"$magic\" = \"44485033\" ]; then\n\t\techo \"Your configurations won't be saved if factory-uboot.bin image specified.\"\n\t\techo \"But if you want to upgrade, please execute sysupgrade with \\\"-F\\\" option.\"\n\t\treturn 1\n\tfi\n\n\t# check if valid tar file specifed\n\tif ! tar tf \"$fw_image\" &>/dev/null; then\n\t\techo \"Specified file is not a tar archive: $fw_image\"\n\t\treturn 1\n\tfi\n\n\tlocal control_len=$( (tar xf $fw_image sysupgrade-$boardname/CONTROL -O | wc -c) 2> /dev/null)\n\n\t# check if valid sysupgrade tar archive\n\tif [ \"$control_len\" = \"0\" ]; then\n\t\techo \"Invalid sysupgrade file: $fw_image\"\n\t\treturn 1\n\tfi\n\n\tlocal kern_part_len=$(grep \"\\\"linux\\\"\" /proc/mtd | sed \"s/mtd[0-9]*:[ \\t]*\\([^ \\t]*\\).*/\\1/\")\n\t[ -z \"$kern_part_len\" ] && {\n\t\techo \"Unable to get \\\"linux\\\" partition size\"\n\t\treturn 1\n\t}\n\tkern_part_len=$((0x$kern_part_len))\n\n\t# this also checks if the sysupgrade image is for correct models\n\tlocal kern_bin_len=$( (tar xf $fw_image sysupgrade-${boardname}/kernel -O | wc -c) 2> /dev/null)\n\tif [ -z \"$kern_bin_len\" ]; then\n\t\techo \"Failed to get new kernel size, is valid sysupgrade image specified for the device?\"\n\t\treturn 1\n\tfi\n\n\t# kernel binary has a trx header (len: 28 (0x1c))\n\tkern_bin_len=$((kern_bin_len - 28))\n\n\tif [ \"$kern_bin_len\" != \"$kern_part_len\" ]; then\n\t\techo -n \"The length of new kernel is invalid for current \"\n\t\techo \"\\\"linux\\\" partition, please use factory-uboot.bin image.\"\n\t\techo \"\\\"linux\\\" partition: $kern_part_len, new kernel: $kern_bin_len\"\n\t\treturn 1\n\tfi\n}\n\n# for TRX + UBI formatted image\nbuffalo_upgrade_ubinized() {\n\tsync\n\techo 3 > /proc/sys/vm/drop_caches\n\n\tlocal mtdnum=\"$( find_mtd_index \"ubi\" )\"\n\t# if no \"ubi\", don't return error for the purpose of recovery\n\t# ex: recovery after accidental erasing \"firmware\" partition\n\tif [ ! \"$mtdnum\" ]; then\n\t\techo \"cannot find ubi mtd partition \\\"ubi\\\", skip detachment\"\n\telse\n\t\tubidetach -m \"$mtdnum\"\n\tfi\n\n\t# erase all data in \"firmware\"\n\tmtd erase \"${PART_NAME}\"\n\t# write TRX + UBI formatted image to \"firmware\"\n\tget_image \"$1\" | mtd $MTD_ARGS write - \"${PART_NAME:-firmware}\"\n\tif [ $? -ne 0 ]; then\n\t\techo \"Failed to write the specified image.\"\n\t\texit 1\n\tfi\n}\n"
  },
  {
    "path": "target/linux/mediatek/mt7622/base-files/lib/upgrade/platform.sh",
    "content": "REQUIRE_IMAGE_METADATA=1\n\nplatform_do_upgrade() {\n\tlocal board=$(board_name)\n\tlocal file_type=$(identify $1)\n\n\tcase \"$board\" in\n\tbananapi,bpi-r64)\n\t\texport_bootdevice\n\t\texport_partdevice rootdev 0\n\t\tcase \"$rootdev\" in\n\t\tmmc*)\n\t\t\tCI_ROOTDEV=\"$rootdev\"\n\t\t\tCI_KERNPART=\"production\"\n\t\t\temmc_do_upgrade \"$1\"\n\t\t\t;;\n\t\t*)\n\t\t\tCI_KERNPART=\"fit\"\n\t\t\tnand_do_upgrade \"$1\"\n\t\t\t;;\n\t\tesac\n\t\t;;\n\tbuffalo,wsr-2533dhp2)\n\t\tlocal magic=\"$(get_magic_long \"$1\")\"\n\n\t\t# use \"mtd write\" if the magic is \"DHP2 (0x44485032)\"\n\t\t# or \"DHP3 (0x44485033)\"\n\t\tif [ \"$magic\" = \"44485032\" -o \"$magic\" = \"44485033\" ]; then\n\t\t\tbuffalo_upgrade_ubinized \"$1\"\n\t\telse\n\t\t\tCI_KERNPART=\"firmware\"\n\t\t\tnand_do_upgrade \"$1\"\n\t\tfi\n\t\t;;\n\tlinksys,e8450-ubi)\n\t\tCI_KERNPART=\"fit\"\n\t\tnand_do_upgrade \"$1\"\n\t\t;;\n\tlinksys,e8450)\n\t\tif grep -q mtdparts=slave /proc/cmdline; then\n\t\t\tPART_NAME=firmware2\n\t\telse\n\t\t\tPART_NAME=firmware1\n\t\tfi\n\t\tdefault_do_upgrade \"$1\"\n\t\t;;\n\tmediatek,mt7622-rfb1-ubi|\\\n\ttotolink,a8000ru|\\\n\txiaomi,redmi-router-ax6s)\n\t\tnand_do_upgrade \"$1\"\n\t\t;;\n\t*)\n\t\tdefault_do_upgrade \"$1\"\n\t\t;;\n\tesac\n}\n\nPART_NAME=firmware\n\nplatform_check_image() {\n\tlocal board=$(board_name)\n\tlocal magic=\"$(get_magic_long \"$1\")\"\n\n\t[ \"$#\" -gt 1 ] && return 1\n\n\tcase \"$board\" in\n\tbuffalo,wsr-2533dhp2)\n\t\tbuffalo_check_image \"$board\" \"$magic\" \"$1\" || return 1\n\t\t;;\n\tmediatek,mt7622-rfb1-ubi|\\\n\ttotolink,a8000ru|\\\n\txiaomi,redmi-router-ax6s)\n\t\tnand_do_platform_check \"$board\" \"$1\"\n\t\t;;\n\t*)\n\t\t[ \"$magic\" != \"d00dfeed\" ] && {\n\t\t\techo \"Invalid image type.\"\n\t\t\treturn 1\n\t\t}\n\t\treturn 0\n\t\t;;\n\tesac\n\n\treturn 0\n}\n\nplatform_copy_config() {\n\tcase \"$(board_name)\" in\n\tbananapi,bpi-r64)\n\t\texport_bootdevice\n\t\texport_partdevice rootdev 0\n\t\tif echo $rootdev | grep -q mmc; then\n\t\t\temmc_copy_config\n\t\tfi\n\t\t;;\n\tesac\n}\n"
  },
  {
    "path": "target/linux/mediatek/mt7622/config-5.15",
    "content": "CONFIG_64BIT=y\n# CONFIG_AHCI_MTK is not set\nCONFIG_AQUANTIA_PHY=y\nCONFIG_ARCH_DMA_ADDR_T_64BIT=y\nCONFIG_ARCH_KEEP_MEMBLOCK=y\nCONFIG_ARCH_MEDIATEK=y\nCONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y\nCONFIG_ARCH_MMAP_RND_BITS=18\nCONFIG_ARCH_MMAP_RND_BITS_MAX=24\nCONFIG_ARCH_MMAP_RND_BITS_MIN=18\nCONFIG_ARCH_MMAP_RND_COMPAT_BITS=11\nCONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11\nCONFIG_ARCH_PROC_KCORE_TEXT=y\nCONFIG_ARCH_SPARSEMEM_ENABLE=y\nCONFIG_ARCH_STACKWALK=y\nCONFIG_ARCH_SUSPEND_POSSIBLE=y\nCONFIG_ARCH_WANTS_NO_INSTR=y\nCONFIG_ARM64=y\nCONFIG_ARM64_4K_PAGES=y\n# CONFIG_ARM64_CNP is not set\nCONFIG_ARM64_CRYPTO=y\nCONFIG_ARM64_ERRATUM_843419=y\nCONFIG_ARM64_ERRATUM_845719=y\nCONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y\nCONFIG_ARM64_MODULE_PLTS=y\nCONFIG_ARM64_PAGE_SHIFT=12\nCONFIG_ARM64_PA_BITS=48\nCONFIG_ARM64_PA_BITS_48=y\n# CONFIG_ARM64_SW_TTBR0_PAN is not set\nCONFIG_ARM64_TAGGED_ADDR_ABI=y\nCONFIG_ARM64_VA_BITS=39\nCONFIG_ARM64_VA_BITS_39=y\n# CONFIG_ARMV8_DEPRECATED is not set\nCONFIG_ARM_AMBA=y\nCONFIG_ARM_ARCH_TIMER=y\nCONFIG_ARM_ARCH_TIMER_EVTSTREAM=y\nCONFIG_ARM_GIC=y\nCONFIG_ARM_GIC_V2M=y\nCONFIG_ARM_GIC_V3=y\nCONFIG_ARM_GIC_V3_ITS=y\nCONFIG_ARM_GIC_V3_ITS_PCI=y\nCONFIG_ARM_MEDIATEK_CPUFREQ=y\nCONFIG_ARM_PMU=y\nCONFIG_ARM_PSCI_FW=y\nCONFIG_ATA=y\nCONFIG_AUDIT_ARCH_COMPAT_GENERIC=y\nCONFIG_BLK_DEV_LOOP=y\nCONFIG_BLK_DEV_SD=y\nCONFIG_BLK_MQ_PCI=y\nCONFIG_BLK_PM=y\nCONFIG_BLOCK_COMPAT=y\nCONFIG_BSD_PROCESS_ACCT=y\nCONFIG_BSD_PROCESS_ACCT_V3=y\nCONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y\nCONFIG_CLKSRC_MMIO=y\nCONFIG_CLONE_BACKWARDS=y\nCONFIG_COMMON_CLK=y\nCONFIG_COMMON_CLK_MEDIATEK=y\nCONFIG_COMMON_CLK_MT2712=y\n# CONFIG_COMMON_CLK_MT2712_BDPSYS is not set\n# CONFIG_COMMON_CLK_MT2712_IMGSYS is not set\n# CONFIG_COMMON_CLK_MT2712_JPGDECSYS is not set\n# CONFIG_COMMON_CLK_MT2712_MFGCFG is not set\n# CONFIG_COMMON_CLK_MT2712_MMSYS is not set\n# CONFIG_COMMON_CLK_MT2712_VDECSYS is not set\n# CONFIG_COMMON_CLK_MT2712_VENCSYS is not set\n# CONFIG_COMMON_CLK_MT6779 is not set\n# CONFIG_COMMON_CLK_MT6797 is not set\nCONFIG_COMMON_CLK_MT7622=y\nCONFIG_COMMON_CLK_MT7622_AUDSYS=y\nCONFIG_COMMON_CLK_MT7622_ETHSYS=y\nCONFIG_COMMON_CLK_MT7622_HIFSYS=y\n# CONFIG_COMMON_CLK_MT8173 is not set\nCONFIG_COMMON_CLK_MT8183=y\n# CONFIG_COMMON_CLK_MT8183_AUDIOSYS is not set\n# CONFIG_COMMON_CLK_MT8183_CAMSYS is not set\n# CONFIG_COMMON_CLK_MT8183_IMGSYS is not set\n# CONFIG_COMMON_CLK_MT8183_IPU_ADL is not set\n# CONFIG_COMMON_CLK_MT8183_IPU_CONN is not set\n# CONFIG_COMMON_CLK_MT8183_IPU_CORE0 is not set\n# CONFIG_COMMON_CLK_MT8183_IPU_CORE1 is not set\n# CONFIG_COMMON_CLK_MT8183_MFGCFG is not set\n# CONFIG_COMMON_CLK_MT8183_MMSYS is not set\n# CONFIG_COMMON_CLK_MT8183_VDECSYS is not set\n# CONFIG_COMMON_CLK_MT8183_VENCSYS is not set\nCONFIG_COMMON_CLK_MT8516=y\n# CONFIG_COMMON_CLK_MT8516_AUDSYS is not set\nCONFIG_COMPAT=y\nCONFIG_COMPAT_32BIT_TIME=y\nCONFIG_COMPAT_BINFMT_ELF=y\nCONFIG_COMPAT_NETLINK_MESSAGES=y\nCONFIG_COMPAT_OLD_SIGACTION=y\nCONFIG_CONFIGFS_FS=y\nCONFIG_CONSOLE_LOGLEVEL_DEFAULT=15\n# CONFIG_CPUFREQ_DT is not set\nCONFIG_CPU_FREQ=y\n# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set\nCONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y\nCONFIG_CPU_FREQ_GOV_ATTR_SET=y\nCONFIG_CPU_FREQ_GOV_COMMON=y\nCONFIG_CPU_FREQ_GOV_CONSERVATIVE=y\nCONFIG_CPU_FREQ_GOV_ONDEMAND=y\nCONFIG_CPU_FREQ_GOV_PERFORMANCE=y\nCONFIG_CPU_FREQ_GOV_POWERSAVE=y\nCONFIG_CPU_FREQ_GOV_SCHEDUTIL=y\nCONFIG_CPU_FREQ_GOV_USERSPACE=y\nCONFIG_CPU_FREQ_STAT=y\nCONFIG_CPU_RMAP=y\nCONFIG_CPU_THERMAL=y\nCONFIG_CRC16=y\nCONFIG_CRYPTO_AES_ARM64=y\nCONFIG_CRYPTO_AES_ARM64_CE=y\nCONFIG_CRYPTO_AES_ARM64_CE_BLK=y\nCONFIG_CRYPTO_AES_ARM64_CE_CCM=y\nCONFIG_CRYPTO_CMAC=y\nCONFIG_CRYPTO_CRC32=y\nCONFIG_CRYPTO_CRC32C=y\nCONFIG_CRYPTO_CRYPTD=y\nCONFIG_CRYPTO_DEFLATE=y\nCONFIG_CRYPTO_DRBG=y\nCONFIG_CRYPTO_DRBG_HMAC=y\nCONFIG_CRYPTO_DRBG_MENU=y\nCONFIG_CRYPTO_ECB=y\nCONFIG_CRYPTO_ECC=y\nCONFIG_CRYPTO_ECDH=y\nCONFIG_CRYPTO_GHASH_ARM64_CE=y\nCONFIG_CRYPTO_HASH_INFO=y\nCONFIG_CRYPTO_HMAC=y\nCONFIG_CRYPTO_JITTERENTROPY=y\nCONFIG_CRYPTO_LIB_SHA256=y\nCONFIG_CRYPTO_LZO=y\nCONFIG_CRYPTO_RNG=y\nCONFIG_CRYPTO_RNG2=y\nCONFIG_CRYPTO_RNG_DEFAULT=y\nCONFIG_CRYPTO_SHA256=y\nCONFIG_CRYPTO_SHA256_ARM64=y\nCONFIG_CRYPTO_SHA2_ARM64_CE=y\nCONFIG_CRYPTO_SHA512=y\nCONFIG_CRYPTO_SIMD=y\nCONFIG_CRYPTO_ZSTD=y\nCONFIG_DCACHE_WORD_ACCESS=y\nCONFIG_DEBUG_MISC=y\nCONFIG_DIMLIB=y\nCONFIG_DMADEVICES=y\nCONFIG_DMATEST=y\nCONFIG_DMA_DIRECT_REMAP=y\nCONFIG_DMA_ENGINE=y\nCONFIG_DMA_ENGINE_RAID=y\nCONFIG_DMA_OF=y\nCONFIG_DMA_REMAP=y\nCONFIG_DMA_VIRTUAL_CHANNELS=y\nCONFIG_DTC=y\nCONFIG_DYNAMIC_DEBUG=y\nCONFIG_EDAC_SUPPORT=y\nCONFIG_EINT_MTK=y\nCONFIG_EXT4_FS=y\nCONFIG_F2FS_FS=y\nCONFIG_FIT_PARTITION=y\nCONFIG_FIXED_PHY=y\nCONFIG_FIX_EARLYCON_MEM=y\nCONFIG_FRAME_POINTER=y\nCONFIG_FS_IOMAP=y\nCONFIG_FS_MBCACHE=y\nCONFIG_FWNODE_MDIO=y\nCONFIG_FW_LOADER_PAGED_BUF=y\nCONFIG_GENERIC_ALLOCATOR=y\nCONFIG_GENERIC_ARCH_TOPOLOGY=y\nCONFIG_GENERIC_BUG=y\nCONFIG_GENERIC_BUG_RELATIVE_POINTERS=y\nCONFIG_GENERIC_CLOCKEVENTS=y\nCONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y\nCONFIG_GENERIC_CPU_AUTOPROBE=y\nCONFIG_GENERIC_CPU_VULNERABILITIES=y\nCONFIG_GENERIC_CSUM=y\nCONFIG_GENERIC_EARLY_IOREMAP=y\nCONFIG_GENERIC_FIND_FIRST_BIT=y\nCONFIG_GENERIC_GETTIMEOFDAY=y\nCONFIG_GENERIC_IDLE_POLL_SETUP=y\nCONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y\nCONFIG_GENERIC_IRQ_SHOW=y\nCONFIG_GENERIC_IRQ_SHOW_LEVEL=y\nCONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y\nCONFIG_GENERIC_MSI_IRQ=y\nCONFIG_GENERIC_MSI_IRQ_DOMAIN=y\nCONFIG_GENERIC_PCI_IOMAP=y\nCONFIG_GENERIC_PHY=y\nCONFIG_GENERIC_PINCONF=y\nCONFIG_GENERIC_PINCTRL_GROUPS=y\nCONFIG_GENERIC_PINMUX_FUNCTIONS=y\nCONFIG_GENERIC_SCHED_CLOCK=y\nCONFIG_GENERIC_SMP_IDLE_THREAD=y\nCONFIG_GENERIC_STRNCPY_FROM_USER=y\nCONFIG_GENERIC_STRNLEN_USER=y\nCONFIG_GENERIC_TIME_VSYSCALL=y\nCONFIG_GLOB=y\nCONFIG_GPIOLIB=y\nCONFIG_GPIO_CDEV=y\nCONFIG_GRO_CELLS=y\nCONFIG_HANDLE_DOMAIN_IRQ=y\nCONFIG_HARDIRQS_SW_RESEND=y\nCONFIG_HAS_DMA=y\nCONFIG_HAS_IOMEM=y\nCONFIG_HAS_IOPORT_MAP=y\nCONFIG_HW_RANDOM=y\nCONFIG_HW_RANDOM_MTK=y\nCONFIG_I2C=y\nCONFIG_I2C_BOARDINFO=y\nCONFIG_I2C_CHARDEV=y\nCONFIG_I2C_MT65XX=y\nCONFIG_ICPLUS_PHY=y\nCONFIG_IIO=y\nCONFIG_IKCONFIG=y\nCONFIG_IKCONFIG_PROC=y\nCONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000\nCONFIG_INITRAMFS_SOURCE=\"\"\nCONFIG_IO_URING=y\nCONFIG_IRQCHIP=y\nCONFIG_IRQ_DOMAIN=y\nCONFIG_IRQ_DOMAIN_HIERARCHY=y\nCONFIG_IRQ_FORCED_THREADING=y\nCONFIG_IRQ_TIME_ACCOUNTING=y\nCONFIG_IRQ_WORK=y\nCONFIG_JBD2=y\nCONFIG_JUMP_LABEL=y\nCONFIG_LIBFDT=y\nCONFIG_LOCK_DEBUGGING_SUPPORT=y\nCONFIG_LOCK_SPIN_ON_OWNER=y\nCONFIG_LZO_COMPRESS=y\nCONFIG_LZO_DECOMPRESS=y\nCONFIG_MAGIC_SYSRQ=y\nCONFIG_MDIO_BUS=y\nCONFIG_MDIO_DEVICE=y\nCONFIG_MDIO_DEVRES=y\nCONFIG_MEDIATEK_GE_PHY=y\nCONFIG_MEDIATEK_MT6577_AUXADC=y\nCONFIG_MEDIATEK_WATCHDOG=y\nCONFIG_MEMFD_CREATE=y\nCONFIG_MESSAGE_LOGLEVEL_DEFAULT=7\nCONFIG_MFD_SYSCON=y\nCONFIG_MIGRATION=y\nCONFIG_MMC=y\nCONFIG_MMC_BLOCK=y\nCONFIG_MMC_CQHCI=y\nCONFIG_MMC_MTK=y\nCONFIG_MODULES_TREE_LOOKUP=y\nCONFIG_MODULES_USE_ELF_RELA=y\nCONFIG_MTD_NAND_CORE=y\nCONFIG_MTD_NAND_ECC=y\nCONFIG_MTD_NAND_ECC_MEDIATEK=y\nCONFIG_MTD_NAND_ECC_SW_HAMMING=y\nCONFIG_MTD_NAND_MTK=y\nCONFIG_MTD_NAND_MTK_BMT=y\nCONFIG_MTD_PARSER_TRX=y\nCONFIG_MTD_RAW_NAND=y\nCONFIG_MTD_SPI_NAND=y\nCONFIG_MTD_SPI_NOR=y\nCONFIG_MTD_SPLIT_FIRMWARE=y\nCONFIG_MTD_SPLIT_FIT_FW=y\nCONFIG_MTD_UBI=y\nCONFIG_MTD_UBI_BEB_LIMIT=20\nCONFIG_MTD_UBI_BLOCK=y\nCONFIG_MTD_UBI_WL_THRESHOLD=4096\n# CONFIG_MTK_CMDQ is not set\n# CONFIG_MTK_CQDMA is not set\nCONFIG_MTK_EFUSE=y\nCONFIG_MTK_HSDMA=y\nCONFIG_MTK_INFRACFG=y\nCONFIG_MTK_PMIC_WRAP=y\nCONFIG_MTK_SCPSYS=y\nCONFIG_MTK_SCPSYS_PM_DOMAINS=y\nCONFIG_MTK_THERMAL=y\nCONFIG_MTK_TIMER=y\n# CONFIG_MTK_UART_APDMA is not set\nCONFIG_MUTEX_SPIN_ON_OWNER=y\nCONFIG_NEED_DMA_MAP_STATE=y\nCONFIG_NEED_SG_DMA_LENGTH=y\nCONFIG_NET_DEVLINK=y\nCONFIG_NET_DSA=y\nCONFIG_NET_DSA_MT7530=y\nCONFIG_NET_DSA_TAG_MTK=y\nCONFIG_NET_FLOW_LIMIT=y\nCONFIG_NET_MEDIATEK_SOC=y\nCONFIG_NET_MEDIATEK_SOC_WED=y\nCONFIG_NET_SELFTESTS=y\nCONFIG_NET_SWITCHDEV=y\nCONFIG_NET_VENDOR_MEDIATEK=y\nCONFIG_NLS=y\nCONFIG_NO_HZ_COMMON=y\nCONFIG_NO_HZ_IDLE=y\nCONFIG_NR_CPUS=2\nCONFIG_NVMEM=y\nCONFIG_NVMEM_SYSFS=y\nCONFIG_OF=y\nCONFIG_OF_ADDRESS=y\nCONFIG_OF_DYNAMIC=y\nCONFIG_OF_EARLY_FLATTREE=y\nCONFIG_OF_FLATTREE=y\nCONFIG_OF_GPIO=y\nCONFIG_OF_IRQ=y\nCONFIG_OF_KOBJ=y\nCONFIG_OF_MDIO=y\nCONFIG_OF_OVERLAY=y\nCONFIG_OF_RESOLVE=y\nCONFIG_OLD_SIGSUSPEND3=y\nCONFIG_PADATA=y\nCONFIG_PARTITION_PERCPU=y\nCONFIG_PCI=y\nCONFIG_PCIEAER=y\nCONFIG_PCIEASPM=y\n# CONFIG_PCIEASPM_DEFAULT is not set\nCONFIG_PCIEASPM_PERFORMANCE=y\n# CONFIG_PCIEASPM_POWERSAVE is not set\n# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set\nCONFIG_PCIEPORTBUS=y\nCONFIG_PCIE_MEDIATEK=y\nCONFIG_PCIE_PME=y\nCONFIG_PCI_DEBUG=y\nCONFIG_PCI_DOMAINS=y\nCONFIG_PCI_DOMAINS_GENERIC=y\nCONFIG_PCI_MSI=y\nCONFIG_PCI_MSI_IRQ_DOMAIN=y\nCONFIG_PERF_EVENTS=y\nCONFIG_PGTABLE_LEVELS=3\nCONFIG_PHYLIB=y\nCONFIG_PHYLINK=y\nCONFIG_PHYS_ADDR_T_64BIT=y\nCONFIG_PHY_MTK_TPHY=y\n# CONFIG_PHY_MTK_UFS is not set\n# CONFIG_PHY_MTK_XSPHY is not set\nCONFIG_PINCTRL=y\n# CONFIG_PINCTRL_MT2712 is not set\n# CONFIG_PINCTRL_MT6765 is not set\n# CONFIG_PINCTRL_MT6797 is not set\nCONFIG_PINCTRL_MT7622=y\n# CONFIG_PINCTRL_MT8173 is not set\n# CONFIG_PINCTRL_MT8183 is not set\nCONFIG_PINCTRL_MT8516=y\nCONFIG_PINCTRL_MTK=y\nCONFIG_PINCTRL_MTK_MOORE=y\nCONFIG_PINCTRL_MTK_V2=y\nCONFIG_PM=y\nCONFIG_PM_CLK=y\nCONFIG_PM_GENERIC_DOMAINS=y\nCONFIG_PM_GENERIC_DOMAINS_OF=y\nCONFIG_PM_OPP=y\nCONFIG_POWER_RESET=y\nCONFIG_POWER_RESET_SYSCON=y\nCONFIG_POWER_SUPPLY=y\nCONFIG_PRINTK_TIME=y\nCONFIG_PSTORE=y\nCONFIG_PSTORE_COMPRESS=y\nCONFIG_PSTORE_COMPRESS_DEFAULT=\"deflate\"\nCONFIG_PSTORE_CONSOLE=y\nCONFIG_PSTORE_DEFLATE_COMPRESS=y\nCONFIG_PSTORE_DEFLATE_COMPRESS_DEFAULT=y\nCONFIG_PSTORE_PMSG=y\nCONFIG_PSTORE_RAM=y\nCONFIG_PTP_1588_CLOCK_OPTIONAL=y\nCONFIG_PWM=y\nCONFIG_PWM_MEDIATEK=y\n# CONFIG_PWM_MTK_DISP is not set\nCONFIG_PWM_SYSFS=y\nCONFIG_QUEUED_RWLOCKS=y\nCONFIG_QUEUED_SPINLOCKS=y\nCONFIG_RAS=y\nCONFIG_RATIONAL=y\n# CONFIG_RAVE_SP_CORE is not set\nCONFIG_REALTEK_PHY=y\nCONFIG_REED_SOLOMON=y\nCONFIG_REED_SOLOMON_DEC8=y\nCONFIG_REED_SOLOMON_ENC8=y\nCONFIG_REGMAP=y\nCONFIG_REGMAP_MMIO=y\nCONFIG_REGULATOR=y\nCONFIG_REGULATOR_FIXED_VOLTAGE=y\nCONFIG_REGULATOR_MT6380=y\nCONFIG_RESET_CONTROLLER=y\nCONFIG_RFS_ACCEL=y\nCONFIG_RODATA_FULL_DEFAULT_ENABLED=y\nCONFIG_RPS=y\nCONFIG_RTC_CLASS=y\nCONFIG_RTC_DRV_MT7622=y\nCONFIG_RTC_I2C_AND_SPI=y\nCONFIG_RTL8367S_GSW=y\nCONFIG_RWSEM_SPIN_ON_OWNER=y\nCONFIG_SCHED_MC=y\nCONFIG_SCSI=y\nCONFIG_SCSI_COMMON=y\n# CONFIG_SECTION_MISMATCH_WARN_ONLY is not set\nCONFIG_SERIAL_8250_FSL=y\nCONFIG_SERIAL_8250_MT6577=y\nCONFIG_SERIAL_8250_NR_UARTS=3\nCONFIG_SERIAL_8250_RUNTIME_UARTS=3\nCONFIG_SERIAL_DEV_BUS=y\nCONFIG_SERIAL_DEV_CTRL_TTYPORT=y\nCONFIG_SERIAL_MCTRL_GPIO=y\nCONFIG_SERIAL_OF_PLATFORM=y\nCONFIG_SGL_ALLOC=y\nCONFIG_SG_POOL=y\nCONFIG_SMP=y\nCONFIG_SOCK_RX_QUEUE_MAPPING=y\nCONFIG_SPARSEMEM=y\nCONFIG_SPARSEMEM_EXTREME=y\nCONFIG_SPARSEMEM_VMEMMAP=y\nCONFIG_SPARSEMEM_VMEMMAP_ENABLE=y\nCONFIG_SPARSE_IRQ=y\nCONFIG_SPI=y\nCONFIG_SPI_DYNAMIC=y\nCONFIG_SPI_MASTER=y\nCONFIG_SPI_MEM=y\nCONFIG_SPI_MT65XX=y\nCONFIG_SPI_MTK_NOR=y\nCONFIG_SPI_MTK_SNFI=y\nCONFIG_SRCU=y\nCONFIG_SWCONFIG=y\nCONFIG_SWIOTLB=y\nCONFIG_SWPHY=y\nCONFIG_SYSCTL_EXCEPTION_TRACE=y\nCONFIG_SYSVIPC_COMPAT=y\nCONFIG_THERMAL=y\nCONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y\nCONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0\nCONFIG_THERMAL_EMULATION=y\nCONFIG_THERMAL_GOV_BANG_BANG=y\nCONFIG_THERMAL_GOV_FAIR_SHARE=y\nCONFIG_THERMAL_GOV_STEP_WISE=y\nCONFIG_THERMAL_GOV_USER_SPACE=y\nCONFIG_THERMAL_OF=y\nCONFIG_THERMAL_WRITABLE_TRIPS=y\nCONFIG_THREAD_INFO_IN_TASK=y\nCONFIG_TICK_CPU_ACCOUNTING=y\nCONFIG_TIMER_OF=y\nCONFIG_TIMER_PROBE=y\nCONFIG_TREE_RCU=y\nCONFIG_TREE_SRCU=y\nCONFIG_UBIFS_FS=y\n# CONFIG_UCLAMP_TASK is not set\n# CONFIG_UNMAP_KERNEL_AT_EL0 is not set\nCONFIG_USB=y\nCONFIG_USB_COMMON=y\nCONFIG_USB_SUPPORT=y\nCONFIG_USB_XHCI_HCD=y\nCONFIG_USB_XHCI_MTK=y\n# CONFIG_USB_XHCI_PLATFORM is not set\nCONFIG_VMAP_STACK=y\nCONFIG_WATCHDOG_CORE=y\nCONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_PANIC=y\nCONFIG_WATCHDOG_PRETIMEOUT_GOV=y\n# CONFIG_WATCHDOG_PRETIMEOUT_GOV_NOOP is not set\nCONFIG_WATCHDOG_PRETIMEOUT_GOV_PANIC=y\nCONFIG_WATCHDOG_PRETIMEOUT_GOV_SEL=m\nCONFIG_WATCHDOG_SYSFS=y\nCONFIG_XPS=y\nCONFIG_XXHASH=y\nCONFIG_ZLIB_DEFLATE=y\nCONFIG_ZLIB_INFLATE=y\nCONFIG_ZONE_DMA32=y\nCONFIG_ZSTD_COMPRESS=y\nCONFIG_ZSTD_DECOMPRESS=y\n"
  },
  {
    "path": "target/linux/mediatek/mt7622/target.mk",
    "content": "ARCH:=aarch64\nSUBTARGET:=mt7622\nBOARDNAME:=MT7622\nCPU_TYPE:=cortex-a53\nDEFAULT_PACKAGES += kmod-mt7615e kmod-mt7615-firmware wpad-basic-wolfssl uboot-envtools\nKERNELNAME:=Image dtbs\n\ndefine Target/Description\n\tBuild firmware images for MediaTek MT7622 ARM based boards.\nendef\n"
  },
  {
    "path": "target/linux/mediatek/mt7623/base-files/etc/board.d/02_network",
    "content": "\n. /lib/functions.sh\n. /lib/functions/uci-defaults.sh\n. /lib/functions/system.sh\n\nmediatek_setup_interfaces()\n{\n\tlocal board=\"$1\"\n\n\tcase $board in\n\tbananapi,bpi-r2|\\\n\tunielec,u7623-02|\\\n\tunielec,u7623-02-emmc-512m)\n\t\tucidef_set_interfaces_lan_wan \"lan0 lan1 lan2 lan3\" \"wan\"\n\t\t;;\n\tesac\n}\n\nmediatek_setup_macs()\n{\n\tlocal board=\"$1\"\n\n\tcase $board in\n\tbananapi,bpi-r2|\\\n\tunielec,u7623-02|\\\n\tunielec,u7623-02-emmc-512m)\n\t\tucidef_set_interface_macaddr \"wan\" \"$(cat /sys/class/net/wan/address)\"\n\t\t;;\n\tesac\n}\n\nboard_config_update\nboard=$(board_name)\nmediatek_setup_interfaces $board\nmediatek_setup_macs $board\nboard_config_flush\n\nexit 0\n"
  },
  {
    "path": "target/linux/mediatek/mt7623/base-files/etc/inittab",
    "content": "::sysinit:/etc/init.d/rcS S boot\n::shutdown:/etc/init.d/rcS K shutdown\n::askconsole:/usr/libexec/login.sh\ntty1::askfirst:/usr/libexec/login.sh\ntty2::askfirst:/usr/libexec/login.sh\ntty3::askfirst:/usr/libexec/login.sh\ntty4::askfirst:/usr/libexec/login.sh\ntty5::askfirst:/usr/libexec/login.sh\ntty6::askfirst:/usr/libexec/login.sh\n"
  },
  {
    "path": "target/linux/mediatek/mt7623/base-files/lib/preinit/07_set_iface_mac",
    "content": "# Copyright (C) 2018 OpenWrt.org\n\n. /lib/functions.sh\n. /lib/functions/system.sh\n\nset_recovery_mac_address() {\n\tlocal RECOVERY_PART=\"$1\"\n\tlocal mac\n\n\tif [ -b $RECOVERY_PART ]; then\n\t\tinsmod nls_cp437\n\t\tinsmod nls_iso8859-1\n\t\tinsmod fat\n\t\tinsmod vfat\n\t\tmkdir -p /tmp/recovery\n\t\tif mount -o rw,noatime $RECOVERY_PART -t vfat /tmp/recovery; then\n\t\t\tif [ -f \"/tmp/recovery/mac_addr\" ];\n\t\t\tthen\n\t\t\t\tmac=$(cat /tmp/recovery/mac_addr)\n\t\t\telse\n\t\t\t\tmac=$(cat /sys/class/net/eth0/address)\n\t\t\t\techo \"$mac\" > /tmp/recovery/mac_addr\n\t\t\tfi\n\n\t\t\tsync\n\t\t\tumount /tmp/recovery\n\t\t\trmdir /tmp/recovery\n\n\t\t\tip link set dev wan address $mac 2> /dev/null\n\n\t\t\tmac=$(macaddr_add $mac 1)\n\n\t\t\tip link set dev lan0 address $mac 2>/dev/null\n\t\t\tip link set dev lan1 address $mac 2>/dev/null\n\t\t\tip link set dev lan2 address $mac 2>/dev/null\n\t\t\tip link set dev lan3 address $mac 2>/dev/null\n\t\tfi\n\tfi\n}\n\npreinit_set_mac_address() {\n\tlocal rootpart\n\n\tcase $(board_name) in\n\tunielec,u7623-02-emmc-512m)\n\t\tset_recovery_mac_address /dev/mmcblk0p1\n\t\t;;\n\tesac\n}\n\nboot_hook_add preinit_main preinit_set_mac_address\n"
  },
  {
    "path": "target/linux/mediatek/mt7623/base-files/lib/preinit/79_move_config",
    "content": "# Copyright (C) 2015 OpenWrt.org\n\n. /lib/upgrade/common.sh\n\nmove_config() {\n\tlocal partdev partnum\n\n\tcase $(board_name) in\n\tunielec,u7623-02-emmc-512m)\n\t\tif grep -q root=/dev/mmcblk0p2 /proc/cmdline; then\n\t\t\tpartnum=1;\n\t\telse\n\t\t\tpartnum=2;\n\t\tfi\n\t\t;;\n\t*)\n\t\treturn 1\n\t\t;;\n\tesac\n\n\tif export_bootdevice && export_partdevice partdev $partnum; then\n\t\tinsmod nls_cp437\n\t\tinsmod nls_iso8859-1\n\t\tinsmod fat\n\t\tinsmod vfat\n\t\tmkdir -p /recovery\n\t\tmount -o rw,noatime \"/dev/$partdev\" -t vfat /recovery\n\t\t[ -f \"/recovery/$BACKUP_FILE\" ] && mv -f \"/recovery/$BACKUP_FILE\" /\n\t\tumount /recovery\n\tfi\n}\n\nboot_hook_add preinit_mount_root move_config\n"
  },
  {
    "path": "target/linux/mediatek/mt7623/base-files/lib/upgrade/platform.sh",
    "content": "REQUIRE_IMAGE_METADATA=1\n\n# Legacy full system upgrade including preloader for MediaTek SoCs on eMMC or SD\nlegacy_mtk_mmc_full_upgrade() {\n\tlocal diskdev partdev diff oldrecovery\n\n\tif grep -q root=/dev/mmcblk0p2 /proc/cmdline; then\n\t    oldrecovery=1\n\telse\n\t    oldrecovery=2\n\tfi\n\n\texport_bootdevice && export_partdevice diskdev 0 || {\n\t\techo \"Unable to determine upgrade device\"\n\t\treturn 1\n\t}\n\n\t#Keep the persistent random mac address (if it exists)\n\tmkdir -p /tmp/recovery\n\texport_partdevice recoverydev $oldrecovery\n\tif mount -o rw,noatime \"/dev/$recoverydev\" -tvfat /tmp/recovery; then\n\t\t[ -f \"/tmp/recovery/mac_addr\" ] && cp /tmp/recovery/mac_addr /tmp/\n\t\tumount /tmp/recovery\n\tfi\n\tsync\n\n\tif [ \"$UPGRADE_OPT_SAVE_PARTITIONS\" = \"1\" ]; then\n\t\tget_partitions \"/dev/$diskdev\" bootdisk\n\n\t\t#extract the boot sector from the image\n\t\tget_image \"$@\" | dd of=/tmp/image.bs count=1 bs=512b\n\n\t\tget_partitions /tmp/image.bs image\n\n\t\t#compare tables\n\t\tdiff=\"$(grep -F -x -v -f /tmp/partmap.bootdisk /tmp/partmap.image)\"\n\telse\n\t\tdiff=1\n\tfi\n\n\tif [ -n \"$diff\" ]; then\n\t\tget_image \"$@\" | dd of=\"/dev/$diskdev\" bs=4096 conv=fsync\n\n\t\t# Separate removal and addition is necessary; otherwise, partition 1\n\t\t# will be missing if it overlaps with the old partition 2\n\t\tpartx -d - \"/dev/$diskdev\"\n\t\tpartx -a - \"/dev/$diskdev\"\n\telse\n\t\t# iterate over each partition from the image and write it to the boot disk\n\t\twhile read part start size; do\n\t\t\tpart=\"$(($part - 2))\"\n\t\t\tif export_partdevice partdev $part; then\n\t\t\t\techo \"Writing image to /dev/$partdev...\"\n\t\t\t\tget_image \"$@\" | dd of=\"/dev/$partdev\" ibs=\"512\" obs=1M skip=\"$start\" count=\"$size\" conv=fsync\n\t\t\telse\n\t\t\t    echo \"Unable to find partition $part device, skipped.\"\n\t\t\tfi\n\t\tdone < /tmp/partmap.image\n\n\t\t#copy partition uuid\n\t\techo \"Writing new UUID to /dev/$diskdev...\"\n\t\tget_image \"$@\" | dd of=\"/dev/$diskdev\" bs=1 skip=440 count=4 seek=440 conv=fsync\n\tfi\n\n\texport_partdevice recoverydev 2\n\tif mount -o rw,noatime \"/dev/$recoverydev\" -t vfat /tmp/recovery; then\n\t\t[ -f \"/tmp/mac_addr\" ] && cp /tmp/mac_addr /tmp/recovery\n\n\t\tif [ \"$diskdev\" = \"mmcblk0\" -a -r /tmp/recovery/eMMCboot.bin ]; then\n\t\t\techo 0 > /sys/block/mmcblk0boot0/force_ro\n\t\t\tdd if=/tmp/recovery/eMMCboot.bin of=/dev/mmcblk0boot0 conv=fsync\n\t\t\tsync\n\t\t\techo 1 > /sys/block/mmcblk0boot0/force_ro\n\t\tfi\n\t\tsync\n\t\tumount /tmp/recovery\n\tfi\n}\n\nplatform_do_upgrade() {\n\tlocal board=$(board_name)\n\n\tcase \"$board\" in\n\tbananapi,bpi-r2|\\\n\tunielec,u7623-02)\n\t\texport_bootdevice\n\t\texport_partdevice fitpart 3\n\t\t[ \"$fitpart\" ] || return 1\n\t\tEMMC_KERN_DEV=\"/dev/$fitpart\"\n\t\temmc_do_upgrade \"$1\"\n\t\t;;\n\tunielec,u7623-02-emmc-512m)\n\t\tlocal magic=\"$(get_magic_long \"$1\")\"\n\t\tif [ \"$magic\" = \"53444d4d\" ]; then\n\t\t\tlegacy_mtk_mmc_full_upgrade \"$1\"\n\t\telse # Old partial image starting with uImage\n\t\t\t# Keep the persistent random mac address (if it exists)\n\t\t\trecoverydev=mmcblk0p1\n\t\t\tmkdir -p /tmp/recovery\n\t\t\tmount -o rw,noatime /dev/$recoverydev /tmp/recovery\n\t\t\t[ -f \"/tmp/recovery/mac_addr\" ] && \\\n\t\t\t\tmv -f /tmp/recovery/mac_addr /tmp/\n\t\t\tumount /tmp/recovery\n\n\t\t\t# 1310720 is the offset in bytes from the start of eMMC and to\n\t\t\t# the location of the kernel (2560 512 byte sectors)\n\t\t\tget_image \"$1\" | dd of=/dev/mmcblk0 bs=1310720 seek=1 conv=fsync\n\n\t\t\tmount -o rw,noatime /dev/$recoverydev /tmp/recovery\n\t\t\t[ -f \"/tmp/mac_addr\" ] && mv -f /tmp/mac_addr /tmp/recovery\n\t\t\tsync\n\t\t\tumount /tmp/recovery\n\t\tfi\n\t\t;;\n\t*)\n\t\tdefault_do_upgrade \"$1\"\n\t\t;;\n\tesac\n}\n\nplatform_check_image() {\n\tlocal magic=\"$(get_magic_long \"$1\")\"\n\n\t[ \"$#\" -gt 1 ] && return 1\n\n\tcase \"$(board_name)\" in\n\tbananapi,bpi-r2|\\\n\tunielec,u7623-02)\n\t\t[ \"$magic\" != \"d00dfeed\" ] && {\n\t\t\techo \"Invalid image type.\"\n\t\t\treturn 1\n\t\t}\n\t\t;;\n\tunielec,u7623-02-emmc-512m)\n\t\t# Can always upgrade to the new-style full image\n\t\t[ \"$magic\" = \"53444d4d\" ] && return 0\n\n\t\t# need to update to new bootchain via full image first\n\t\t[ \"$magic\" = \"d00dfeed\" ] && {\n\t\t\techo \"Please use full eMMC image to update bootloader first.\"\n\t\t\treturn 1\n\t\t}\n\n\t\t# Legacy uImage directly at 0xA00 on the eMMC.\n\t\t[ \"$magic\" != \"27051956\" ] && {\n\t\t\techo \"Invalid image type.\"\n\t\t\treturn 1\n\t\t}\n\t\t;;\n\t*)\n\t\techo \"Sysupgrade is not supported on your board yet.\"\n\t\treturn 1\n\t\t;;\n\tesac\n\n\treturn 0\n}\n\nplatform_copy_config() {\n\tcase \"$(board_name)\" in\n\tbananapi,bpi-r2|\\\n\tunielec,u7623-02)\n\t\temmc_copy_config\n\t\t;;\n\tunielec,u7623-02-emmc-512m)\n\t\t# platform_do_upgrade() will have set $recoverydev\n\t\tif [ -n \"$recoverydev\" ]; then\n\t\t\tmkdir -p /tmp/recovery\n\t\t\tmount -o rw,noatime \"/dev/$recoverydev\" -t vfat /tmp/recovery\n\t\t\tcp -af \"$UPGRADE_BACKUP\" \"/tmp/recovery/$BACKUP_FILE\"\n\t\t\tsync\n\t\t\tumount /tmp/recovery\n\t\tfi\n\t\t;;\n\tesac\n}\n"
  },
  {
    "path": "target/linux/mediatek/mt7623/config-5.15",
    "content": "# CONFIG_AIO is not set\nCONFIG_ALIGNMENT_TRAP=y\nCONFIG_ARCH_32BIT_OFF_T=y\nCONFIG_ARCH_HIBERNATION_POSSIBLE=y\nCONFIG_ARCH_KEEP_MEMBLOCK=y\nCONFIG_ARCH_MEDIATEK=y\nCONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y\nCONFIG_ARCH_MULTIPLATFORM=y\nCONFIG_ARCH_MULTI_V6_V7=y\nCONFIG_ARCH_MULTI_V7=y\nCONFIG_ARCH_NR_GPIO=0\nCONFIG_ARCH_OPTIONAL_KERNEL_RWX=y\nCONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y\nCONFIG_ARCH_SELECT_MEMORY_MODEL=y\nCONFIG_ARCH_SPARSEMEM_ENABLE=y\nCONFIG_ARCH_SUSPEND_POSSIBLE=y\nCONFIG_ARM=y\nCONFIG_ARM_APPENDED_DTB=y\nCONFIG_ARM_ARCH_TIMER=y\nCONFIG_ARM_ARCH_TIMER_EVTSTREAM=y\n# CONFIG_ARM_ATAG_DTB_COMPAT is not set\nCONFIG_ARM_CPU_SUSPEND=y\n# CONFIG_ARM_CPU_TOPOLOGY is not set\nCONFIG_ARM_DMA_IOMMU_ALIGNMENT=8\nCONFIG_ARM_DMA_USE_IOMMU=y\nCONFIG_ARM_GIC=y\nCONFIG_ARM_HAS_SG_CHAIN=y\nCONFIG_ARM_L1_CACHE_SHIFT=6\nCONFIG_ARM_L1_CACHE_SHIFT_6=y\nCONFIG_ARM_MEDIATEK_CPUFREQ=y\nCONFIG_ARM_PATCH_IDIV=y\nCONFIG_ARM_PATCH_PHYS_VIRT=y\n# CONFIG_ARM_SMMU is not set\nCONFIG_ARM_THUMB=y\nCONFIG_ARM_THUMBEE=y\nCONFIG_ARM_UNWIND=y\nCONFIG_ARM_VIRT_EXT=y\nCONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH=y\nCONFIG_ATAGS=y\nCONFIG_AUTO_ZRELADDR=y\nCONFIG_BACKLIGHT_CLASS_DEVICE=y\nCONFIG_BACKLIGHT_GPIO=y\nCONFIG_BACKLIGHT_LED=y\nCONFIG_BACKLIGHT_PWM=y\nCONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y\nCONFIG_BLK_DEV_LOOP=y\nCONFIG_BLK_MQ_PCI=y\nCONFIG_BLK_PM=y\nCONFIG_BOUNCE=y\n# CONFIG_CACHE_L2X0 is not set\nCONFIG_CLEANCACHE=y\nCONFIG_CLKSRC_MMIO=y\nCONFIG_CLONE_BACKWARDS=y\nCONFIG_CMDLINE=\"earlyprintk console=ttyS0,115200 rootfstype=squashfs,jffs2\"\nCONFIG_CMDLINE_FROM_BOOTLOADER=y\nCONFIG_CMDLINE_PARTITION=y\nCONFIG_COMMON_CLK=y\nCONFIG_COMMON_CLK_MEDIATEK=y\nCONFIG_COMMON_CLK_MT2701=y\nCONFIG_COMMON_CLK_MT2701_AUDSYS=y\nCONFIG_COMMON_CLK_MT2701_BDPSYS=y\nCONFIG_COMMON_CLK_MT2701_ETHSYS=y\nCONFIG_COMMON_CLK_MT2701_G3DSYS=y\nCONFIG_COMMON_CLK_MT2701_HIFSYS=y\nCONFIG_COMMON_CLK_MT2701_IMGSYS=y\nCONFIG_COMMON_CLK_MT2701_MMSYS=y\nCONFIG_COMMON_CLK_MT2701_VDECSYS=y\n# CONFIG_COMMON_CLK_MT7622 is not set\n# CONFIG_COMMON_CLK_MT7629 is not set\n# CONFIG_COMMON_CLK_MT8135 is not set\n# CONFIG_COMMON_CLK_MT8173 is not set\nCONFIG_COMMON_CLK_MT8516=y\n# CONFIG_COMMON_CLK_MT8516_AUDSYS is not set\nCONFIG_COMPAT_32BIT_TIME=y\nCONFIG_CONFIGFS_FS=y\nCONFIG_CONSOLE_TRANSLATIONS=y\nCONFIG_COREDUMP=y\n# CONFIG_CPUFREQ_DT is not set\nCONFIG_CPU_32v6K=y\nCONFIG_CPU_32v7=y\nCONFIG_CPU_ABRT_EV7=y\nCONFIG_CPU_CACHE_V7=y\nCONFIG_CPU_CACHE_VIPT=y\nCONFIG_CPU_COPY_V6=y\nCONFIG_CPU_CP15=y\nCONFIG_CPU_CP15_MMU=y\nCONFIG_CPU_FREQ=y\nCONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y\nCONFIG_CPU_FREQ_GOV_ATTR_SET=y\nCONFIG_CPU_FREQ_GOV_COMMON=y\nCONFIG_CPU_FREQ_GOV_CONSERVATIVE=y\nCONFIG_CPU_FREQ_GOV_ONDEMAND=y\nCONFIG_CPU_FREQ_GOV_PERFORMANCE=y\nCONFIG_CPU_FREQ_GOV_POWERSAVE=y\n# CONFIG_CPU_FREQ_GOV_USERSPACE is not set\nCONFIG_CPU_FREQ_STAT=y\nCONFIG_CPU_HAS_ASID=y\nCONFIG_CPU_PABRT_V7=y\nCONFIG_CPU_PM=y\nCONFIG_CPU_RMAP=y\nCONFIG_CPU_SPECTRE=y\nCONFIG_CPU_THUMB_CAPABLE=y\nCONFIG_CPU_TLB_V7=y\nCONFIG_CPU_V7=y\nCONFIG_CRC16=y\n# CONFIG_CRC32_SARWATE is not set\nCONFIG_CRC32_SLICEBY8=y\nCONFIG_CROSS_MEMORY_ATTACH=y\nCONFIG_CRYPTO_CRC32=y\nCONFIG_CRYPTO_CRC32C=y\nCONFIG_CRYPTO_DEFLATE=y\nCONFIG_CRYPTO_DRBG=y\nCONFIG_CRYPTO_DRBG_HMAC=y\nCONFIG_CRYPTO_DRBG_MENU=y\nCONFIG_CRYPTO_HASH_INFO=y\nCONFIG_CRYPTO_HMAC=y\nCONFIG_CRYPTO_HW=y\nCONFIG_CRYPTO_JITTERENTROPY=y\nCONFIG_CRYPTO_LIB_SHA256=y\nCONFIG_CRYPTO_LZO=y\nCONFIG_CRYPTO_RNG=y\nCONFIG_CRYPTO_RNG2=y\nCONFIG_CRYPTO_RNG_DEFAULT=y\nCONFIG_CRYPTO_SEQIV=y\nCONFIG_CRYPTO_SHA1=y\nCONFIG_CRYPTO_SHA256=y\nCONFIG_CRYPTO_SHA512=y\nCONFIG_CRYPTO_ZSTD=y\nCONFIG_DCACHE_WORD_ACCESS=y\nCONFIG_DEBUG_ALIGN_RODATA=y\nCONFIG_DEBUG_BUGVERBOSE=y\nCONFIG_DEBUG_GPIO=y\nCONFIG_DEBUG_INFO=y\nCONFIG_DEBUG_LL=y\nCONFIG_DEBUG_LL_INCLUDE=\"debug/8250.S\"\nCONFIG_DEBUG_MISC=y\nCONFIG_DEBUG_MT6589_UART0=y\n# CONFIG_DEBUG_MT8127_UART0 is not set\n# CONFIG_DEBUG_MT8135_UART3 is not set\nCONFIG_DEBUG_PREEMPT=y\nCONFIG_DEBUG_UART_8250=y\nCONFIG_DEBUG_UART_8250_SHIFT=2\nCONFIG_DEBUG_UART_PHYS=0x11004000\nCONFIG_DEBUG_UART_VIRT=0xf1004000\nCONFIG_DEBUG_UNCOMPRESS=y\n# CONFIG_DEVFREQ_GOV_PASSIVE is not set\n# CONFIG_DEVFREQ_GOV_PERFORMANCE is not set\n# CONFIG_DEVFREQ_GOV_POWERSAVE is not set\nCONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y\n# CONFIG_DEVFREQ_GOV_USERSPACE is not set\n# CONFIG_DEVFREQ_THERMAL is not set\nCONFIG_DIMLIB=y\nCONFIG_DMADEVICES=y\nCONFIG_DMA_ENGINE=y\nCONFIG_DMA_OF=y\nCONFIG_DMA_OPS=y\nCONFIG_DMA_REMAP=y\nCONFIG_DMA_SHARED_BUFFER=y\nCONFIG_DMA_VIRTUAL_CHANNELS=y\nCONFIG_DRM=y\nCONFIG_DRM_BRIDGE=y\nCONFIG_DRM_DISPLAY_CONNECTOR=y\nCONFIG_DRM_FBDEV_EMULATION=y\nCONFIG_DRM_FBDEV_OVERALLOC=100\nCONFIG_DRM_GEM_CMA_HELPER=y\nCONFIG_DRM_GEM_SHMEM_HELPER=y\nCONFIG_DRM_KMS_HELPER=y\nCONFIG_DRM_LIMA=y\nCONFIG_DRM_LVDS_CODEC=y\nCONFIG_DRM_MEDIATEK=y\nCONFIG_DRM_MEDIATEK_HDMI=y\nCONFIG_DRM_MIPI_DSI=y\nCONFIG_DRM_PANEL=y\nCONFIG_DRM_PANEL_BRIDGE=y\nCONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y\nCONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN=y\nCONFIG_DRM_SCHED=y\nCONFIG_DRM_SIMPLE_BRIDGE=y\nCONFIG_DTC=y\nCONFIG_DUMMY_CONSOLE=y\nCONFIG_EARLY_PRINTK=y\nCONFIG_EDAC_ATOMIC_SCRUB=y\nCONFIG_EDAC_SUPPORT=y\nCONFIG_EINT_MTK=y\nCONFIG_ELF_CORE=y\nCONFIG_EXT4_FS=y\nCONFIG_EXTCON=y\nCONFIG_F2FS_FS=y\nCONFIG_FB=y\nCONFIG_FB_CFB_COPYAREA=y\nCONFIG_FB_CFB_FILLRECT=y\nCONFIG_FB_CFB_IMAGEBLIT=y\nCONFIG_FB_CMDLINE=y\nCONFIG_FB_DEFERRED_IO=y\nCONFIG_FB_SYS_COPYAREA=y\nCONFIG_FB_SYS_FILLRECT=y\nCONFIG_FB_SYS_FOPS=y\nCONFIG_FB_SYS_IMAGEBLIT=y\nCONFIG_FIT_PARTITION=y\nCONFIG_FIXED_PHY=y\nCONFIG_FIX_EARLYCON_MEM=y\nCONFIG_FONT_8x16=y\nCONFIG_FONT_8x8=y\nCONFIG_FONT_SUPPORT=y\nCONFIG_FRAMEBUFFER_CONSOLE=y\nCONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y\nCONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y\nCONFIG_FREEZER=y\nCONFIG_FS_IOMAP=y\nCONFIG_FS_MBCACHE=y\nCONFIG_FWNODE_MDIO=y\nCONFIG_FW_CACHE=y\nCONFIG_FW_LOADER_PAGED_BUF=y\nCONFIG_GENERIC_ALLOCATOR=y\nCONFIG_GENERIC_BUG=y\nCONFIG_GENERIC_CLOCKEVENTS=y\nCONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y\nCONFIG_GENERIC_CPU_AUTOPROBE=y\nCONFIG_GENERIC_CPU_VULNERABILITIES=y\nCONFIG_GENERIC_EARLY_IOREMAP=y\nCONFIG_GENERIC_GETTIMEOFDAY=y\nCONFIG_GENERIC_IDLE_POLL_SETUP=y\nCONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y\nCONFIG_GENERIC_IRQ_MIGRATION=y\nCONFIG_GENERIC_IRQ_MULTI_HANDLER=y\nCONFIG_GENERIC_IRQ_SHOW=y\nCONFIG_GENERIC_IRQ_SHOW_LEVEL=y\nCONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y\nCONFIG_GENERIC_MSI_IRQ=y\nCONFIG_GENERIC_MSI_IRQ_DOMAIN=y\nCONFIG_GENERIC_PCI_IOMAP=y\nCONFIG_GENERIC_PHY=y\nCONFIG_GENERIC_PINCONF=y\nCONFIG_GENERIC_PINCTRL_GROUPS=y\nCONFIG_GENERIC_PINMUX_FUNCTIONS=y\nCONFIG_GENERIC_SCHED_CLOCK=y\nCONFIG_GENERIC_SMP_IDLE_THREAD=y\nCONFIG_GENERIC_STRNCPY_FROM_USER=y\nCONFIG_GENERIC_STRNLEN_USER=y\nCONFIG_GENERIC_TIME_VSYSCALL=y\nCONFIG_GENERIC_VDSO_32=y\nCONFIG_GPIOLIB=y\nCONFIG_GPIO_CDEV=y\nCONFIG_GRO_CELLS=y\nCONFIG_HANDLE_DOMAIN_IRQ=y\nCONFIG_HARDEN_BRANCH_PREDICTOR=y\nCONFIG_HARDIRQS_SW_RESEND=y\nCONFIG_HAS_DMA=y\nCONFIG_HAS_IOMEM=y\nCONFIG_HAS_IOPORT_MAP=y\nCONFIG_HAVE_SMP=y\nCONFIG_HDMI=y\nCONFIG_HID=y\nCONFIG_HIGHMEM=y\nCONFIG_HIGHPTE=y\nCONFIG_HOTPLUG_CPU=y\nCONFIG_HWMON=y\nCONFIG_HW_CONSOLE=y\nCONFIG_HW_RANDOM=y\nCONFIG_HW_RANDOM_MTK=y\nCONFIG_HZ_FIXED=0\nCONFIG_I2C=y\nCONFIG_I2C_ALGOBIT=y\nCONFIG_I2C_BOARDINFO=y\nCONFIG_I2C_CHARDEV=y\nCONFIG_I2C_MT65XX=y\nCONFIG_ICPLUS_PHY=y\nCONFIG_IIO=y\nCONFIG_INITRAMFS_SOURCE=\"\"\nCONFIG_INPUT=y\nCONFIG_INPUT_EVDEV=y\nCONFIG_INPUT_KEYBOARD=y\n# CONFIG_INPUT_MISC is not set\nCONFIG_INPUT_TOUCHSCREEN=y\nCONFIG_IOMMU_API=y\n# CONFIG_IOMMU_DEBUGFS is not set\n# CONFIG_IOMMU_DEFAULT_DMA_LAZY is not set\nCONFIG_IOMMU_DEFAULT_DMA_STRICT=y\n# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set\nCONFIG_IOMMU_IO_PGTABLE=y\nCONFIG_IOMMU_IO_PGTABLE_ARMV7S=y\n# CONFIG_IOMMU_IO_PGTABLE_ARMV7S_SELFTEST is not set\n# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set\nCONFIG_IOMMU_SUPPORT=y\nCONFIG_IO_URING=y\nCONFIG_IRQCHIP=y\nCONFIG_IRQ_DOMAIN=y\nCONFIG_IRQ_DOMAIN_HIERARCHY=y\nCONFIG_IRQ_FORCED_THREADING=y\nCONFIG_IRQ_WORK=y\nCONFIG_JBD2=y\nCONFIG_KALLSYMS=y\nCONFIG_KCMP=y\nCONFIG_KEYBOARD_MTK_PMIC=y\nCONFIG_KMAP_LOCAL=y\nCONFIG_KMAP_LOCAL_NON_LINEAR_PTE_ARRAY=y\nCONFIG_LCD_CLASS_DEVICE=y\nCONFIG_LCD_PLATFORM=y\nCONFIG_LEDS_MT6323=y\nCONFIG_LIBFDT=y\nCONFIG_LOCK_DEBUGGING_SUPPORT=y\nCONFIG_LOCK_SPIN_ON_OWNER=y\nCONFIG_LOGO=y\nCONFIG_LOGO_LINUX_CLUT224=y\n# CONFIG_LOGO_LINUX_MONO is not set\n# CONFIG_LOGO_LINUX_VGA16 is not set\nCONFIG_LZO_COMPRESS=y\nCONFIG_LZO_DECOMPRESS=y\n# CONFIG_MACH_MT2701 is not set\n# CONFIG_MACH_MT6589 is not set\n# CONFIG_MACH_MT6592 is not set\nCONFIG_MACH_MT7623=y\n# CONFIG_MACH_MT7629 is not set\n# CONFIG_MACH_MT8127 is not set\n# CONFIG_MACH_MT8135 is not set\nCONFIG_MAGIC_SYSRQ=y\nCONFIG_MAILBOX=y\n# CONFIG_MAILBOX_TEST is not set\nCONFIG_MDIO_BITBANG=y\nCONFIG_MDIO_BUS=y\nCONFIG_MDIO_DEVICE=y\nCONFIG_MDIO_DEVRES=y\nCONFIG_MDIO_GPIO=y\nCONFIG_MEDIATEK_GE_PHY=y\nCONFIG_MEDIATEK_MT6577_AUXADC=y\nCONFIG_MEDIATEK_WATCHDOG=y\nCONFIG_MEMFD_CREATE=y\nCONFIG_MEMORY=y\nCONFIG_MFD_CORE=y\n# CONFIG_MFD_HI6421_SPMI is not set\nCONFIG_MFD_MT6397=y\nCONFIG_MFD_SYSCON=y\nCONFIG_MIGHT_HAVE_CACHE_L2X0=y\nCONFIG_MIGRATION=y\nCONFIG_MMC=y\nCONFIG_MMC_BLOCK=y\nCONFIG_MMC_CQHCI=y\nCONFIG_MMC_MTK=y\nCONFIG_MMC_SDHCI=y\n# CONFIG_MMC_SDHCI_PCI is not set\nCONFIG_MMC_SDHCI_PLTFM=y\nCONFIG_MODULES_USE_ELF_REL=y\nCONFIG_MTD_CMDLINE_PARTS=y\n# CONFIG_MTD_NAND_ECC_MEDIATEK is not set\nCONFIG_MTD_SPI_NOR=y\nCONFIG_MTD_SPLIT_FIRMWARE=y\nCONFIG_MTD_SPLIT_UIMAGE_FW=y\nCONFIG_MTD_UBI=y\nCONFIG_MTD_UBI_BEB_LIMIT=20\nCONFIG_MTD_UBI_BLOCK=y\nCONFIG_MTD_UBI_WL_THRESHOLD=4096\nCONFIG_MTK_CMDQ=y\nCONFIG_MTK_CMDQ_MBOX=y\nCONFIG_MTK_CQDMA=y\nCONFIG_MTK_EFUSE=y\n# CONFIG_MTK_HSDMA is not set\nCONFIG_MTK_INFRACFG=y\nCONFIG_MTK_IOMMU=y\nCONFIG_MTK_IOMMU_V1=y\nCONFIG_MTK_MMSYS=y\nCONFIG_MTK_PMIC_WRAP=y\nCONFIG_MTK_SCPSYS=y\nCONFIG_MTK_SCPSYS_PM_DOMAINS=y\nCONFIG_MTK_SMI=y\nCONFIG_MTK_THERMAL=y\nCONFIG_MTK_TIMER=y\n# CONFIG_MTK_UART_APDMA is not set\n# CONFIG_MUSB_PIO_ONLY is not set\nCONFIG_MUTEX_SPIN_ON_OWNER=y\nCONFIG_NEED_DMA_MAP_STATE=y\nCONFIG_NEED_SG_DMA_LENGTH=y\nCONFIG_NEON=y\nCONFIG_NET_DEVLINK=y\nCONFIG_NET_DSA=y\nCONFIG_NET_DSA_MT7530=y\nCONFIG_NET_DSA_TAG_MTK=y\nCONFIG_NET_FLOW_LIMIT=y\nCONFIG_NET_MEDIATEK_SOC=y\nCONFIG_NET_MEDIATEK_SOC_WED=y\nCONFIG_NET_SELFTESTS=y\nCONFIG_NET_SWITCHDEV=y\nCONFIG_NET_VENDOR_MEDIATEK=y\n# CONFIG_NET_VENDOR_WIZNET is not set\nCONFIG_NLS=y\nCONFIG_NOP_USB_XCEIV=y\nCONFIG_NO_HZ=y\nCONFIG_NO_HZ_COMMON=y\nCONFIG_NO_HZ_IDLE=y\nCONFIG_NR_CPUS=4\nCONFIG_NVMEM=y\n# CONFIG_NVMEM_SPMI_SDAM is not set\nCONFIG_NVMEM_SYSFS=y\nCONFIG_OF=y\nCONFIG_OF_ADDRESS=y\nCONFIG_OF_DYNAMIC=y\nCONFIG_OF_EARLY_FLATTREE=y\nCONFIG_OF_FLATTREE=y\nCONFIG_OF_GPIO=y\nCONFIG_OF_IOMMU=y\nCONFIG_OF_IRQ=y\nCONFIG_OF_KOBJ=y\nCONFIG_OF_MDIO=y\nCONFIG_OF_OVERLAY=y\nCONFIG_OF_RESOLVE=y\nCONFIG_OLD_SIGACTION=y\nCONFIG_OLD_SIGSUSPEND3=y\nCONFIG_PADATA=y\nCONFIG_PAGE_OFFSET=0xC0000000\nCONFIG_PAHOLE_HAS_SPLIT_BTF=y\nCONFIG_PCI=y\nCONFIG_PCIEAER=y\nCONFIG_PCIEPORTBUS=y\nCONFIG_PCIE_MEDIATEK=y\nCONFIG_PCIE_PME=y\nCONFIG_PCI_DOMAINS=y\nCONFIG_PCI_DOMAINS_GENERIC=y\nCONFIG_PCI_MSI=y\nCONFIG_PCI_MSI_IRQ_DOMAIN=y\nCONFIG_PERF_USE_VMALLOC=y\nCONFIG_PGTABLE_LEVELS=2\nCONFIG_PHYLIB=y\nCONFIG_PHYLINK=y\nCONFIG_PHY_MTK_HDMI=y\nCONFIG_PHY_MTK_MIPI_DSI=y\nCONFIG_PHY_MTK_TPHY=y\n# CONFIG_PHY_MTK_UFS is not set\n# CONFIG_PHY_MTK_XSPHY is not set\nCONFIG_PINCTRL=y\nCONFIG_PINCTRL_MT2701=y\nCONFIG_PINCTRL_MT6397=y\nCONFIG_PINCTRL_MT7623=y\nCONFIG_PINCTRL_MTK=y\nCONFIG_PINCTRL_MTK_MOORE=y\nCONFIG_PINCTRL_MTK_V2=y\nCONFIG_PM=y\nCONFIG_PM_CLK=y\nCONFIG_PM_DEVFREQ=y\n# CONFIG_PM_DEVFREQ_EVENT is not set\nCONFIG_PM_GENERIC_DOMAINS=y\nCONFIG_PM_GENERIC_DOMAINS_OF=y\nCONFIG_PM_GENERIC_DOMAINS_SLEEP=y\nCONFIG_PM_OPP=y\nCONFIG_PM_SLEEP=y\nCONFIG_PM_SLEEP_SMP=y\nCONFIG_POWER_RESET=y\n# CONFIG_POWER_RESET_MT6323 is not set\nCONFIG_POWER_SUPPLY=y\nCONFIG_POWER_SUPPLY_HWMON=y\nCONFIG_PREEMPT=y\nCONFIG_PREEMPTION=y\nCONFIG_PREEMPT_COUNT=y\n# CONFIG_PREEMPT_NONE is not set\nCONFIG_PREEMPT_RCU=y\nCONFIG_PRINTK_TIME=y\nCONFIG_PTP_1588_CLOCK_OPTIONAL=y\nCONFIG_PWM=y\nCONFIG_PWM_MEDIATEK=y\n# CONFIG_PWM_MTK_DISP is not set\nCONFIG_PWM_SYSFS=y\nCONFIG_RAS=y\nCONFIG_RATIONAL=y\nCONFIG_REGMAP=y\nCONFIG_REGMAP_MMIO=y\nCONFIG_REGULATOR=y\nCONFIG_REGULATOR_FIXED_VOLTAGE=y\nCONFIG_REGULATOR_GPIO=y\nCONFIG_REGULATOR_MT6323=y\n# CONFIG_REGULATOR_MT6358 is not set\n# CONFIG_REGULATOR_MT6380 is not set\n# CONFIG_REGULATOR_MT6397 is not set\n# CONFIG_REGULATOR_QCOM_LABIBB is not set\n# CONFIG_REGULATOR_QCOM_SPMI is not set\n# CONFIG_REGULATOR_QCOM_USB_VBUS is not set\nCONFIG_RESET_CONTROLLER=y\nCONFIG_RFS_ACCEL=y\nCONFIG_RPS=y\nCONFIG_RTC_CLASS=y\n# CONFIG_RTC_DRV_MT6397 is not set\n# CONFIG_RTC_DRV_MT7622 is not set\nCONFIG_RTC_I2C_AND_SPI=y\nCONFIG_RTC_MC146818_LIB=y\n# CONFIG_RTL8367S_GSW is not set\nCONFIG_RWSEM_SPIN_ON_OWNER=y\n# CONFIG_SERIAL_8250_DMA is not set\nCONFIG_SERIAL_8250_FSL=y\nCONFIG_SERIAL_8250_MT6577=y\nCONFIG_SERIAL_8250_NR_UARTS=4\nCONFIG_SERIAL_8250_RUNTIME_UARTS=4\nCONFIG_SERIAL_MCTRL_GPIO=y\nCONFIG_SGL_ALLOC=y\nCONFIG_SMP=y\n# CONFIG_SMP_ON_UP is not set\nCONFIG_SOCK_RX_QUEUE_MAPPING=y\nCONFIG_SPARSE_IRQ=y\nCONFIG_SPI=y\nCONFIG_SPI_BITBANG=y\nCONFIG_SPI_DYNAMIC=y\nCONFIG_SPI_MASTER=y\nCONFIG_SPI_MEM=y\nCONFIG_SPI_MT65XX=y\n# CONFIG_SPI_MTK_NOR is not set\nCONFIG_SPMI=y\n# CONFIG_SPMI_HISI3670 is not set\nCONFIG_SRCU=y\n# CONFIG_STRIP_ASM_SYMS is not set\nCONFIG_SUSPEND=y\nCONFIG_SUSPEND_FREEZER=y\nCONFIG_SWCONFIG=y\nCONFIG_SWPHY=y\nCONFIG_SWP_EMULATE=y\nCONFIG_SYNC_FILE=y\nCONFIG_SYS_SUPPORTS_APM_EMULATION=y\nCONFIG_THERMAL=y\nCONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y\nCONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0\nCONFIG_THERMAL_GOV_STEP_WISE=y\nCONFIG_THERMAL_OF=y\nCONFIG_TICK_CPU_ACCOUNTING=y\nCONFIG_TIMER_OF=y\nCONFIG_TIMER_PROBE=y\nCONFIG_TOUCHSCREEN_EDT_FT5X06=y\nCONFIG_TREE_RCU=y\nCONFIG_TREE_SRCU=y\n# CONFIG_UACCE is not set\nCONFIG_UBIFS_FS=y\nCONFIG_UEVENT_HELPER_PATH=\"\"\nCONFIG_UNCOMPRESS_INCLUDE=\"debug/uncompress.h\"\nCONFIG_UNINLINE_SPIN_UNLOCK=y\nCONFIG_UNWINDER_ARM=y\nCONFIG_USB=y\nCONFIG_USB_COMMON=y\nCONFIG_USB_F_ACM=y\nCONFIG_USB_F_ECM=y\nCONFIG_USB_F_MASS_STORAGE=y\nCONFIG_USB_GADGET=y\nCONFIG_USB_GPIO_VBUS=y\nCONFIG_USB_G_MULTI=y\nCONFIG_USB_G_MULTI_CDC=y\n# CONFIG_USB_G_MULTI_RNDIS is not set\nCONFIG_USB_HID=y\nCONFIG_USB_HIDDEV=y\nCONFIG_USB_INVENTRA_DMA=y\nCONFIG_USB_LIBCOMPOSITE=y\nCONFIG_USB_MUSB_DUAL_ROLE=y\nCONFIG_USB_MUSB_HDRC=y\nCONFIG_USB_MUSB_MEDIATEK=y\nCONFIG_USB_OTG=y\nCONFIG_USB_PHY=y\nCONFIG_USB_ROLE_SWITCH=y\nCONFIG_USB_SUPPORT=y\nCONFIG_USB_U_ETHER=y\nCONFIG_USB_U_SERIAL=y\nCONFIG_USB_XHCI_HCD=y\nCONFIG_USB_XHCI_MTK=y\nCONFIG_USB_XHCI_PLATFORM=y\nCONFIG_USE_OF=y\nCONFIG_VFP=y\nCONFIG_VFPv3=y\nCONFIG_VIDEOMODE_HELPERS=y\nCONFIG_VM_EVENT_COUNTERS=y\nCONFIG_VT=y\nCONFIG_VT_CONSOLE=y\nCONFIG_VT_CONSOLE_SLEEP=y\nCONFIG_VT_HW_CONSOLE_BINDING=y\nCONFIG_WATCHDOG_CORE=y\nCONFIG_XPS=y\nCONFIG_XXHASH=y\nCONFIG_XZ_DEC_ARM=y\nCONFIG_XZ_DEC_BCJ=y\nCONFIG_ZBOOT_ROM_BSS=0\nCONFIG_ZBOOT_ROM_TEXT=0\nCONFIG_ZLIB_DEFLATE=y\nCONFIG_ZLIB_INFLATE=y\nCONFIG_ZSTD_COMPRESS=y\nCONFIG_ZSTD_DECOMPRESS=y\n"
  },
  {
    "path": "target/linux/mediatek/mt7623/target.mk",
    "content": "#\n# Copyright (C) 2009 OpenWrt.org\n#\n\nARCH:=arm\nSUBTARGET:=mt7623\nBOARDNAME:=MT7623\nCPU_TYPE:=cortex-a7\nCPU_SUBTYPE:=neon-vfpv4\nKERNELNAME:=Image dtbs zImage\nFEATURES+=display usbgadget\nDEFAULT_PACKAGES+=uboot-envtools\n\ndefine Target/Description\n\tBuild firmware images for MediaTek mt7623 ARM based boards.\nendef\n\n"
  },
  {
    "path": "target/linux/mediatek/mt7629/base-files/etc/board.d/02_network",
    "content": "\n. /lib/functions.sh\n. /lib/functions/uci-defaults.sh\n. /lib/functions/system.sh\n\nmediatek_setup_interfaces()\n{\n\tlocal board=\"$1\"\n\n\tcase $board in\n\tmediatek,mt7629-rfb)\n\t\tucidef_set_interface_wan \"eth1\"\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0:lan\" \"1:lan\" \"2:lan\" \"3:lan\" \"6@eth0\"\n\t\t;;\n\tesac\n}\n\nmediatek_setup_macs()\n{\n\tlocal board=\"$1\"\n\n\tcase $board in\n\tesac\n}\n\nboard_config_update\nboard=$(board_name)\nmediatek_setup_interfaces $board\nmediatek_setup_macs $board\nboard_config_flush\n\nexit 0\n"
  },
  {
    "path": "target/linux/mediatek/mt7629/base-files/lib/upgrade/platform.sh",
    "content": "PART_NAME=firmware\nREQUIRE_IMAGE_METADATA=1\n\nplatform_check_image() {\n\treturn 0\n}\n\nplatform_do_upgrade() {\n\tlocal board=$(board_name)\n\n\tcase \"$board\" in\n\t*)\n\t\tdefault_do_upgrade \"$1\"\n\t\t;;\n\tesac\n}\n"
  },
  {
    "path": "target/linux/mediatek/mt7629/config-5.15",
    "content": "CONFIG_AF_UNIX_OOB=y\nCONFIG_ALIGNMENT_TRAP=y\nCONFIG_ARCH_32BIT_OFF_T=y\nCONFIG_ARCH_HIBERNATION_POSSIBLE=y\nCONFIG_ARCH_KEEP_MEMBLOCK=y\nCONFIG_ARCH_MEDIATEK=y\nCONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y\nCONFIG_ARCH_MULTIPLATFORM=y\nCONFIG_ARCH_MULTI_V6_V7=y\nCONFIG_ARCH_MULTI_V7=y\nCONFIG_ARCH_NR_GPIO=0\nCONFIG_ARCH_OPTIONAL_KERNEL_RWX=y\nCONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y\nCONFIG_ARCH_SELECT_MEMORY_MODEL=y\nCONFIG_ARCH_SPARSEMEM_ENABLE=y\nCONFIG_ARCH_SUSPEND_POSSIBLE=y\nCONFIG_ARM=y\nCONFIG_ARM_ARCH_TIMER=y\nCONFIG_ARM_ARCH_TIMER_EVTSTREAM=y\nCONFIG_ARM_GIC=y\nCONFIG_ARM_HAS_SG_CHAIN=y\nCONFIG_ARM_HEAVY_MB=y\nCONFIG_ARM_L1_CACHE_SHIFT=6\nCONFIG_ARM_L1_CACHE_SHIFT_6=y\nCONFIG_ARM_PATCH_IDIV=y\nCONFIG_ARM_PATCH_PHYS_VIRT=y\nCONFIG_ARM_THUMB=y\nCONFIG_ARM_UNWIND=y\nCONFIG_ARM_VIRT_EXT=y\nCONFIG_ATAGS=y\nCONFIG_AUTO_ZRELADDR=y\nCONFIG_BINARY_PRINTF=y\nCONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y\nCONFIG_BLK_DEV_SD=y\nCONFIG_BLK_MQ_PCI=y\nCONFIG_BLK_PM=y\nCONFIG_BSD_PROCESS_ACCT=y\nCONFIG_BSD_PROCESS_ACCT_V3=y\nCONFIG_CACHE_L2X0=y\n# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set\nCONFIG_CC_OPTIMIZE_FOR_SIZE=y\nCONFIG_CHR_DEV_SCH=y\nCONFIG_CLKSRC_MMIO=y\nCONFIG_CLONE_BACKWARDS=y\nCONFIG_CMDLINE=\"rootfstype=squashfs,jffs2\"\nCONFIG_CMDLINE_FROM_BOOTLOADER=y\nCONFIG_COMMON_CLK=y\nCONFIG_COMMON_CLK_MEDIATEK=y\n# CONFIG_COMMON_CLK_MT2701 is not set\n# CONFIG_COMMON_CLK_MT7622 is not set\nCONFIG_COMMON_CLK_MT7629=y\nCONFIG_COMMON_CLK_MT7629_ETHSYS=y\nCONFIG_COMMON_CLK_MT7629_HIFSYS=y\n# CONFIG_COMMON_CLK_MT8135 is not set\n# CONFIG_COMMON_CLK_MT8173 is not set\nCONFIG_COMMON_CLK_MT8516=y\n# CONFIG_COMMON_CLK_MT8516_AUDSYS is not set\nCONFIG_COMPAT_32BIT_TIME=y\nCONFIG_CPU_32v6K=y\nCONFIG_CPU_32v7=y\nCONFIG_CPU_ABRT_EV7=y\nCONFIG_CPU_CACHE_V7=y\nCONFIG_CPU_CACHE_VIPT=y\nCONFIG_CPU_COPY_V6=y\nCONFIG_CPU_CP15=y\nCONFIG_CPU_CP15_MMU=y\nCONFIG_CPU_HAS_ASID=y\nCONFIG_CPU_IDLE=y\nCONFIG_CPU_IDLE_GOV_MENU=y\nCONFIG_CPU_PABRT_V7=y\nCONFIG_CPU_PM=y\nCONFIG_CPU_RMAP=y\nCONFIG_CPU_SPECTRE=y\nCONFIG_CPU_THUMB_CAPABLE=y\nCONFIG_CPU_TLB_V7=y\nCONFIG_CPU_V7=y\nCONFIG_CRC16=y\nCONFIG_CRYPTO_DEFLATE=y\nCONFIG_CRYPTO_HASH_INFO=y\nCONFIG_CRYPTO_LZO=y\nCONFIG_CRYPTO_RNG2=y\nCONFIG_CRYPTO_ZSTD=y\nCONFIG_DCACHE_WORD_ACCESS=y\nCONFIG_DEBUG_LL_INCLUDE=\"mach/debug-macro.S\"\nCONFIG_DEBUG_MISC=y\nCONFIG_DEFAULT_HOSTNAME=\"(mt7629)\"\nCONFIG_DIMLIB=y\nCONFIG_DMA_OPS=y\nCONFIG_DMA_REMAP=y\nCONFIG_DTC=y\nCONFIG_EDAC_ATOMIC_SCRUB=y\nCONFIG_EDAC_SUPPORT=y\nCONFIG_EINT_MTK=y\nCONFIG_FIXED_PHY=y\nCONFIG_FIX_EARLYCON_MEM=y\nCONFIG_FWNODE_MDIO=y\nCONFIG_FW_LOADER_PAGED_BUF=y\nCONFIG_GENERIC_ALLOCATOR=y\nCONFIG_GENERIC_ARCH_TOPOLOGY=y\nCONFIG_GENERIC_BUG=y\nCONFIG_GENERIC_CLOCKEVENTS=y\nCONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y\nCONFIG_GENERIC_CPU_AUTOPROBE=y\nCONFIG_GENERIC_CPU_VULNERABILITIES=y\nCONFIG_GENERIC_EARLY_IOREMAP=y\nCONFIG_GENERIC_GETTIMEOFDAY=y\nCONFIG_GENERIC_IDLE_POLL_SETUP=y\nCONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y\nCONFIG_GENERIC_IRQ_MIGRATION=y\nCONFIG_GENERIC_IRQ_MULTI_HANDLER=y\nCONFIG_GENERIC_IRQ_SHOW=y\nCONFIG_GENERIC_IRQ_SHOW_LEVEL=y\nCONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y\nCONFIG_GENERIC_MSI_IRQ=y\nCONFIG_GENERIC_MSI_IRQ_DOMAIN=y\nCONFIG_GENERIC_PCI_IOMAP=y\nCONFIG_GENERIC_PHY=y\nCONFIG_GENERIC_PINCONF=y\nCONFIG_GENERIC_PINCTRL_GROUPS=y\nCONFIG_GENERIC_PINMUX_FUNCTIONS=y\nCONFIG_GENERIC_SCHED_CLOCK=y\nCONFIG_GENERIC_SMP_IDLE_THREAD=y\nCONFIG_GENERIC_STRNCPY_FROM_USER=y\nCONFIG_GENERIC_STRNLEN_USER=y\nCONFIG_GENERIC_TIME_VSYSCALL=y\nCONFIG_GENERIC_VDSO_32=y\nCONFIG_GPIOLIB=y\nCONFIG_GPIO_CDEV=y\nCONFIG_HANDLE_DOMAIN_IRQ=y\n# CONFIG_HARDENED_USERCOPY is not set\nCONFIG_HARDEN_BRANCH_PREDICTOR=y\nCONFIG_HARDIRQS_SW_RESEND=y\nCONFIG_HAS_DMA=y\nCONFIG_HAS_IOMEM=y\nCONFIG_HAS_IOPORT_MAP=y\nCONFIG_HAVE_SMP=y\nCONFIG_HOTPLUG_CPU=y\nCONFIG_HW_RANDOM=y\nCONFIG_HW_RANDOM_MTK=y\nCONFIG_HZ_FIXED=0\nCONFIG_INITRAMFS_SOURCE=\"\"\nCONFIG_IO_URING=y\nCONFIG_IRQCHIP=y\nCONFIG_IRQ_DOMAIN=y\nCONFIG_IRQ_DOMAIN_HIERARCHY=y\nCONFIG_IRQ_FORCED_THREADING=y\nCONFIG_IRQ_TIME_ACCOUNTING=y\nCONFIG_IRQ_WORK=y\n# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set\nCONFIG_LIBFDT=y\nCONFIG_LOCK_DEBUGGING_SUPPORT=y\nCONFIG_LOCK_SPIN_ON_OWNER=y\nCONFIG_LTO_NONE=y\nCONFIG_LZO_COMPRESS=y\nCONFIG_LZO_DECOMPRESS=y\n# CONFIG_MACH_MT2701 is not set\n# CONFIG_MACH_MT6589 is not set\n# CONFIG_MACH_MT6592 is not set\n# CONFIG_MACH_MT7623 is not set\nCONFIG_MACH_MT7629=y\n# CONFIG_MACH_MT8127 is not set\n# CONFIG_MACH_MT8135 is not set\nCONFIG_MDIO_BUS=y\nCONFIG_MDIO_DEVICE=y\nCONFIG_MDIO_DEVRES=y\n# CONFIG_MEDIATEK_MT6577_AUXADC is not set\nCONFIG_MEDIATEK_WATCHDOG=y\nCONFIG_MEMFD_CREATE=y\nCONFIG_MFD_SYSCON=y\nCONFIG_MIGHT_HAVE_CACHE_L2X0=y\nCONFIG_MIGRATION=y\nCONFIG_MODULES_USE_ELF_REL=y\nCONFIG_MTD_NAND_CORE=y\nCONFIG_MTD_NAND_ECC=y\nCONFIG_MTD_NAND_ECC_MEDIATEK=y\nCONFIG_MTD_NAND_ECC_SW_HAMMING=y\nCONFIG_MTD_NAND_MTK_BMT=y\nCONFIG_MTD_RAW_NAND=y\nCONFIG_MTD_SPI_NAND=y\nCONFIG_MTD_SPI_NOR=y\nCONFIG_MTD_SPLIT_FIRMWARE=y\nCONFIG_MTD_SPLIT_FIT_FW=y\nCONFIG_MTD_UBI=y\nCONFIG_MTD_UBI_BEB_LIMIT=20\nCONFIG_MTD_UBI_BLOCK=y\nCONFIG_MTD_UBI_WL_THRESHOLD=4096\n# CONFIG_MTK_CMDQ is not set\n# CONFIG_MTK_EFUSE is not set\nCONFIG_MTK_INFRACFG=y\n# CONFIG_MTK_PMIC_WRAP is not set\nCONFIG_MTK_SCPSYS=y\nCONFIG_MTK_SCPSYS_PM_DOMAINS=y\n# CONFIG_MTK_THERMAL is not set\nCONFIG_MTK_TIMER=y\nCONFIG_MUTEX_SPIN_ON_OWNER=y\nCONFIG_NEED_DMA_MAP_STATE=y\nCONFIG_NETFILTER=y\nCONFIG_NET_FLOW_LIMIT=y\nCONFIG_NET_MEDIATEK_SOC=y\nCONFIG_NET_MEDIATEK_SOC_WED=y\nCONFIG_NET_SELFTESTS=y\nCONFIG_NET_SOCK_MSG=y\nCONFIG_NET_VENDOR_MEDIATEK=y\nCONFIG_NLS=y\nCONFIG_NO_HZ_COMMON=y\nCONFIG_NO_HZ_IDLE=y\nCONFIG_NR_CPUS=2\nCONFIG_NVMEM=y\nCONFIG_NVMEM_SYSFS=y\nCONFIG_OF=y\nCONFIG_OF_ADDRESS=y\nCONFIG_OF_EARLY_FLATTREE=y\nCONFIG_OF_FLATTREE=y\nCONFIG_OF_GPIO=y\nCONFIG_OF_IRQ=y\nCONFIG_OF_KOBJ=y\nCONFIG_OF_MDIO=y\nCONFIG_OLD_SIGACTION=y\nCONFIG_OLD_SIGSUSPEND3=y\nCONFIG_OUTER_CACHE=y\nCONFIG_OUTER_CACHE_SYNC=y\nCONFIG_PADATA=y\nCONFIG_PAGE_OFFSET=0xC0000000\nCONFIG_PCI=y\nCONFIG_PCIEAER=y\nCONFIG_PCIEPORTBUS=y\nCONFIG_PCIE_MEDIATEK=y\nCONFIG_PCIE_PME=y\nCONFIG_PCI_DOMAINS=y\nCONFIG_PCI_DOMAINS_GENERIC=y\nCONFIG_PCI_MSI=y\nCONFIG_PCI_MSI_IRQ_DOMAIN=y\nCONFIG_PERF_USE_VMALLOC=y\nCONFIG_PGTABLE_LEVELS=2\nCONFIG_PHYLIB=y\nCONFIG_PHYLINK=y\nCONFIG_PHY_MTK_TPHY=y\n# CONFIG_PHY_MTK_UFS is not set\n# CONFIG_PHY_MTK_XSPHY is not set\nCONFIG_PINCTRL=y\nCONFIG_PINCTRL_MT7629=y\nCONFIG_PINCTRL_MTK_MOORE=y\nCONFIG_PINCTRL_MTK_V2=y\nCONFIG_PM=y\nCONFIG_PM_CLK=y\nCONFIG_PM_GENERIC_DOMAINS=y\nCONFIG_PM_GENERIC_DOMAINS_OF=y\nCONFIG_PTP_1588_CLOCK_OPTIONAL=y\nCONFIG_PWM=y\nCONFIG_PWM_MEDIATEK=y\n# CONFIG_PWM_MTK_DISP is not set\nCONFIG_PWM_SYSFS=y\nCONFIG_RAS=y\nCONFIG_RATIONAL=y\nCONFIG_REGMAP=y\nCONFIG_REGMAP_MMIO=y\nCONFIG_RESET_CONTROLLER=y\nCONFIG_RFS_ACCEL=y\nCONFIG_RPS=y\n# CONFIG_RTL8367S_GSW is not set\nCONFIG_RWSEM_SPIN_ON_OWNER=y\nCONFIG_SCSI=y\nCONFIG_SCSI_COMMON=y\nCONFIG_SERIAL_8250_FSL=y\nCONFIG_SERIAL_8250_MT6577=y\nCONFIG_SERIAL_8250_NR_UARTS=3\nCONFIG_SERIAL_8250_RUNTIME_UARTS=3\nCONFIG_SERIAL_MCTRL_GPIO=y\nCONFIG_SERIAL_OF_PLATFORM=y\nCONFIG_SGL_ALLOC=y\nCONFIG_SG_POOL=y\nCONFIG_SMP=y\nCONFIG_SMP_ON_UP=y\nCONFIG_SOCK_RX_QUEUE_MAPPING=y\nCONFIG_SPARSE_IRQ=y\nCONFIG_SPI=y\nCONFIG_SPI_MASTER=y\nCONFIG_SPI_MEM=y\nCONFIG_SPI_MT65XX=y\nCONFIG_SPI_MTK_NOR=y\nCONFIG_SPI_MTK_SNFI=y\nCONFIG_SRCU=y\nCONFIG_STACKTRACE=y\n# CONFIG_SWAP is not set\nCONFIG_SWCONFIG=y\nCONFIG_SWPHY=y\nCONFIG_SWP_EMULATE=y\nCONFIG_SYS_SUPPORTS_APM_EMULATION=y\nCONFIG_TICK_CPU_ACCOUNTING=y\nCONFIG_TIMER_OF=y\nCONFIG_TIMER_PROBE=y\nCONFIG_TREE_RCU=y\nCONFIG_TREE_SRCU=y\nCONFIG_UBIFS_FS=y\nCONFIG_UNCOMPRESS_INCLUDE=\"debug/uncompress.h\"\nCONFIG_UNWINDER_ARM=y\nCONFIG_USB=y\nCONFIG_USB_COMMON=y\nCONFIG_USB_SUPPORT=y\nCONFIG_USB_XHCI_HCD=y\nCONFIG_USB_XHCI_MTK=y\n# CONFIG_USB_XHCI_PLATFORM is not set\nCONFIG_USE_OF=y\n# CONFIG_VFP is not set\nCONFIG_WATCHDOG_CORE=y\n# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set\nCONFIG_XPS=y\nCONFIG_XXHASH=y\nCONFIG_XZ_DEC_ARM=y\nCONFIG_XZ_DEC_BCJ=y\nCONFIG_ZBOOT_ROM_BSS=0\nCONFIG_ZBOOT_ROM_TEXT=0\nCONFIG_ZLIB_DEFLATE=y\nCONFIG_ZLIB_INFLATE=y\nCONFIG_ZSTD_COMPRESS=y\nCONFIG_ZSTD_DECOMPRESS=y\n"
  },
  {
    "path": "target/linux/mediatek/mt7629/target.mk",
    "content": "#\n# Copyright (C) 2009 OpenWrt.org\n#\n\nARCH:=arm\nSUBTARGET:=mt7629\nBOARDNAME:=MT7629\nCPU_TYPE:=cortex-a7\nFEATURES:=squashfs nand ramdisk\n\nKERNELNAME:=Image dtbs\n\ndefine Target/Description\n\tBuild firmware images for MediaTek mt7629 ARM based boards.\nendef\n\n"
  },
  {
    "path": "target/linux/mediatek/patches-5.15/100-dts-update-mt7622-rfb1.patch",
    "content": "--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts\n+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts\n@@ -1,7 +1,6 @@\n /*\n- * Copyright (c) 2017 MediaTek Inc.\n- * Author: Ming Huang <ming.huang@mediatek.com>\n- *\t   Sean Wang <sean.wang@mediatek.com>\n+ * Copyright (c) 2018 MediaTek Inc.\n+ * Author: Ryder Lee <ryder.lee@mediatek.com>\n  *\n  * SPDX-License-Identifier: (GPL-2.0 OR MIT)\n  */\n@@ -23,7 +22,7 @@\n \n \tchosen {\n \t\tstdout-path = \"serial0:115200n8\";\n-\t\tbootargs = \"earlycon=uart8250,mmio32,0x11002000 swiotlb=512\";\n+\t\tbootargs = \"earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n1 swiotlb=512\";\n \t};\n \n \tcpus {\n@@ -40,23 +39,22 @@\n \n \tgpio-keys {\n \t\tcompatible = \"gpio-keys\";\n-\t\tpoll-interval = <100>;\n \n \t\tfactory {\n \t\t\tlabel = \"factory\";\n \t\t\tlinux,code = <BTN_0>;\n-\t\t\tgpios = <&pio 0 0>;\n+\t\t\tgpios = <&pio 0 GPIO_ACTIVE_LOW>;\n \t\t};\n \n \t\twps {\n \t\t\tlabel = \"wps\";\n \t\t\tlinux,code = <KEY_WPS_BUTTON>;\n-\t\t\tgpios = <&pio 102 0>;\n+\t\t\tgpios = <&pio 102 GPIO_ACTIVE_LOW>;\n \t\t};\n \t};\n \n \tmemory {\n-\t\treg = <0 0x40000000 0 0x20000000>;\n+\t\treg = <0 0x40000000 0 0x40000000>;\n \t};\n \n \treg_1p8v: regulator-1p8v {\n@@ -132,22 +130,22 @@\n \n \t\t\t\tport@0 {\n \t\t\t\t\treg = <0>;\n-\t\t\t\t\tlabel = \"lan0\";\n+\t\t\t\t\tlabel = \"lan1\";\n \t\t\t\t};\n \n \t\t\t\tport@1 {\n \t\t\t\t\treg = <1>;\n-\t\t\t\t\tlabel = \"lan1\";\n+\t\t\t\t\tlabel = \"lan2\";\n \t\t\t\t};\n \n \t\t\t\tport@2 {\n \t\t\t\t\treg = <2>;\n-\t\t\t\t\tlabel = \"lan2\";\n+\t\t\t\t\tlabel = \"lan3\";\n \t\t\t\t};\n \n \t\t\t\tport@3 {\n \t\t\t\t\treg = <3>;\n-\t\t\t\t\tlabel = \"lan3\";\n+\t\t\t\t\tlabel = \"lan4\";\n \t\t\t\t};\n \n \t\t\t\tport@4 {\n@@ -236,15 +234,28 @@\n \n &pcie {\n \tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&pcie0_pins>;\n+\tpinctrl-0 = <&pcie0_pins>, <&pcie1_pins>;\n \tstatus = \"okay\";\n \n \tpcie@0,0 {\n \t\tstatus = \"okay\";\n \t};\n+\n+\tpcie@1,0 {\n+\t\tstatus = \"okay\";\n+\t};\n };\n \n &pio {\n+\t/* Attention: GPIO 90 is used to switch between PCIe@1,0 and\n+\t * SATA functions. i.e. output-high: PCIe, output-low: SATA\n+\t */\n+\tasm_sel {\n+\t\tgpio-hog;\n+\t\tgpios = <90 GPIO_ACTIVE_HIGH>;\n+\t\toutput-high;\n+\t};\n+\n \t/* eMMC is shared pin with parallel NAND */\n \temmc_pins_default: emmc-pins-default {\n \t\tmux {\n@@ -521,11 +532,11 @@\n };\n \n &sata {\n-\tstatus = \"okay\";\n+\tstatus = \"disabled\";\n };\n \n &sata_phy {\n-\tstatus = \"okay\";\n+\tstatus = \"disabled\";\n };\n \n &spi0 {\n"
  },
  {
    "path": "target/linux/mediatek/patches-5.15/101-dts-update-mt7629-rfb.patch",
    "content": "--- a/arch/arm/boot/dts/mt7629-rfb.dts\n+++ b/arch/arm/boot/dts/mt7629-rfb.dts\n@@ -18,6 +18,7 @@\n \n \tchosen {\n \t\tstdout-path = \"serial0:115200n8\";\n+\t\tbootargs = \"earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n8\";\n \t};\n \n \tgpio-keys {\n@@ -70,6 +71,10 @@\n \t\tcompatible = \"mediatek,eth-mac\";\n \t\treg = <0>;\n \t\tphy-mode = \"2500base-x\";\n+\n+\t\tnvmem-cells = <&macaddr_factory_2a>;\n+\t\tnvmem-cell-names = \"mac-address\";\n+\n \t\tfixed-link {\n \t\t\tspeed = <2500>;\n \t\t\tfull-duplex;\n@@ -82,6 +87,9 @@\n \t\treg = <1>;\n \t\tphy-mode = \"gmii\";\n \t\tphy-handle = <&phy0>;\n+\n+\t\tnvmem-cells = <&macaddr_factory_24>;\n+\t\tnvmem-cell-names = \"mac-address\";\n \t};\n \n \tmdio: mdio-bus {\n@@ -133,8 +141,9 @@\n \t\t\t};\n \n \t\t\tpartition@b0000 {\n-\t\t\t\tlabel = \"kernel\";\n+\t\t\t\tlabel = \"firmware\";\n \t\t\t\treg = <0xb0000 0xb50000>;\n+\t\t\t\tcompatible = \"denx,fit\";\n \t\t\t};\n \t\t};\n \t};\n@@ -272,3 +281,17 @@\n \tpinctrl-0 = <&watchdog_pins>;\n \tstatus = \"okay\";\n };\n+\n+&factory {\n+\tcompatible = \"nvmem-cells\";\n+\t#address-cells = <1>;\n+\t#size-cells = <1>;\n+\n+\tmacaddr_factory_24: macaddr@24 {\n+\t\treg = <0x24 0x6>;\n+\t};\n+\n+\tmacaddr_factory_2a: macaddr@2a {\n+\t\treg = <0x2a 0x6>;\n+\t};\n+};\n"
  },
  {
    "path": "target/linux/mediatek/patches-5.15/102-mt7629-enable-arch-timer.patch",
    "content": "--- a/arch/arm/mach-mediatek/Kconfig\n+++ b/arch/arm/mach-mediatek/Kconfig\n@@ -30,6 +30,7 @@ config MACH_MT7623\n config MACH_MT7629\n \tbool \"MediaTek MT7629 SoCs support\"\n \tdefault ARCH_MEDIATEK\n+\tselect HAVE_ARM_ARCH_TIMER\n \n config MACH_MT8127\n \tbool \"MediaTek MT8127 SoCs support\"\n"
  },
  {
    "path": "target/linux/mediatek/patches-5.15/103-mt7623-enable-arch-timer.patch",
    "content": "From d6a596012150960f0f3a214d31bbac4b607dbd1e Mon Sep 17 00:00:00 2001\nFrom: Chuanhong Guo <gch981213@gmail.com>\nDate: Fri, 29 Apr 2022 10:40:56 +0800\nSubject: [PATCH] arm: mediatek: select arch timer for mt7623\n\nSigned-off-by: Chuanhong Guo <gch981213@gmail.com>\n---\n arch/arm/mach-mediatek/Kconfig | 1 +\n 1 file changed, 1 insertion(+)\n\n--- a/arch/arm/mach-mediatek/Kconfig\n+++ b/arch/arm/mach-mediatek/Kconfig\n@@ -26,6 +26,7 @@ config MACH_MT6592\n config MACH_MT7623\n \tbool \"MediaTek MT7623 SoCs support\"\n \tdefault ARCH_MEDIATEK\n+\tselect HAVE_ARM_ARCH_TIMER\n \n config MACH_MT7629\n \tbool \"MediaTek MT7629 SoCs support\"\n"
  },
  {
    "path": "target/linux/mediatek/patches-5.15/104-mt7622-add-snor-irq.patch",
    "content": "--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi\n+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi\n@@ -558,6 +558,7 @@\n \t\tcompatible = \"mediatek,mt7622-nor\",\n \t\t\t     \"mediatek,mt8173-nor\";\n \t\treg = <0 0x11014000 0 0xe0>;\n+\t\tinterrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_LOW>;\n \t\tclocks = <&pericfg CLK_PERI_FLASH_PD>,\n \t\t\t <&topckgen CLK_TOP_FLASH_SEL>;\n \t\tclock-names = \"spi\", \"sf\";\n"
  },
  {
    "path": "target/linux/mediatek/patches-5.15/105-dts-mt7622-enable-pstore.patch",
    "content": "--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi\n+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi\n@@ -111,7 +111,7 @@\n \t};\n \n \tpsci {\n-\t\tcompatible  = \"arm,psci-0.2\";\n+\t\tcompatible  = \"arm,psci-1.0\";\n \t\tmethod      = \"smc\";\n \t};\n \n@@ -127,6 +127,13 @@\n \t\t#size-cells = <2>;\n \t\tranges;\n \n+\t\t/* 64 KiB reserved for ramoops/pstore */\n+\t\tramoops@42ff0000 {\n+\t\t\tcompatible = \"ramoops\";\n+\t\t\treg = <0 0x42ff0000 0 0x10000>;\n+\t\t\trecord-size = <0x1000>;\n+\t\t};\n+\n \t\t/* 192 KiB reserved for ARM Trusted Firmware (BL31) */\n \t\tsecmon_reserved: secmon@43000000 {\n \t\t\treg = <0 0x43000000 0 0x30000>;\n"
  },
  {
    "path": "target/linux/mediatek/patches-5.15/110-dts-fix-bpi2-console.patch",
    "content": "--- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts\n+++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts\n@@ -19,6 +19,7 @@\n \n \tchosen {\n \t\tstdout-path = \"serial2:115200n8\";\n+\t\tbootargs = \"console=ttyS2,115200n8 console=tty1\";\n \t};\n \n \tconnector {\n"
  },
  {
    "path": "target/linux/mediatek/patches-5.15/111-dts-fix-bpi64-console.patch",
    "content": "--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts\n+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts\n@@ -22,7 +22,7 @@\n \n \tchosen {\n \t\tstdout-path = \"serial0:115200n8\";\n-\t\tbootargs = \"earlycon=uart8250,mmio32,0x11002000 swiotlb=512\";\n+\t\tbootargs = \"earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n1 swiotlb=512\";\n \t};\n \n \tcpus {\n"
  },
  {
    "path": "target/linux/mediatek/patches-5.15/112-dts-fix-bpi64-lan-names.patch",
    "content": "--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts\n+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts\n@@ -18,6 +18,7 @@\n \n \taliases {\n \t\tserial0 = &uart0;\n+\t\tethernet0 = &gmac0;\n \t};\n \n \tchosen {\n@@ -160,22 +161,22 @@\n \n \t\t\t\tport@1 {\n \t\t\t\t\treg = <1>;\n-\t\t\t\t\tlabel = \"lan0\";\n+\t\t\t\t\tlabel = \"lan1\";\n \t\t\t\t};\n \n \t\t\t\tport@2 {\n \t\t\t\t\treg = <2>;\n-\t\t\t\t\tlabel = \"lan1\";\n+\t\t\t\t\tlabel = \"lan2\";\n \t\t\t\t};\n \n \t\t\t\tport@3 {\n \t\t\t\t\treg = <3>;\n-\t\t\t\t\tlabel = \"lan2\";\n+\t\t\t\t\tlabel = \"lan3\";\n \t\t\t\t};\n \n \t\t\t\tport@4 {\n \t\t\t\t\treg = <4>;\n-\t\t\t\t\tlabel = \"lan3\";\n+\t\t\t\t\tlabel = \"lan4\";\n \t\t\t\t};\n \n \t\t\t\tport@6 {\n"
  },
  {
    "path": "target/linux/mediatek/patches-5.15/113-dts-fix-bpi64-leds-and-buttons.patch",
    "content": "--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts\n+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts\n@@ -19,6 +19,10 @@\n \taliases {\n \t\tserial0 = &uart0;\n \t\tethernet0 = &gmac0;\n+\t\tled-boot = &led_system_green;\n+\t\tled-failsafe = &led_system_blue;\n+\t\tled-running = &led_system_green;\n+\t\tled-upgrade = &led_system_blue;\n \t};\n \n \tchosen {\n@@ -42,8 +46,8 @@\n \t\tcompatible = \"gpio-keys\";\n \n \t\tfactory {\n-\t\t\tlabel = \"factory\";\n-\t\t\tlinux,code = <BTN_0>;\n+\t\t\tlabel = \"reset\";\n+\t\t\tlinux,code = <KEY_RESTART>;\n \t\t\tgpios = <&pio 0 GPIO_ACTIVE_HIGH>;\n \t\t};\n \n@@ -57,17 +61,25 @@\n \tleds {\n \t\tcompatible = \"gpio-leds\";\n \n-\t\tgreen {\n-\t\t\tlabel = \"bpi-r64:pio:green\";\n-\t\t\tgpios = <&pio 89 GPIO_ACTIVE_HIGH>;\n+\t\tled_system_blue: blue {\n+\t\t\tlabel = \"bpi-r64:pio:blue\";\n+\t\t\tgpios = <&pio 85 GPIO_ACTIVE_HIGH>;\n \t\t\tdefault-state = \"off\";\n \t\t};\n \n-\t\tred {\n-\t\t\tlabel = \"bpi-r64:pio:red\";\n-\t\t\tgpios = <&pio 88 GPIO_ACTIVE_HIGH>;\n+\t\tled_system_green: green {\n+\t\t\tlabel = \"bpi-r64:pio:green\";\n+\t\t\tgpios = <&pio 89 GPIO_ACTIVE_HIGH>;\n \t\t\tdefault-state = \"off\";\n \t\t};\n+\n+/*\n+ *\t\tred {\n+ *\t\t\tlabel = \"bpi-r64:pio:red\";\n+ *\t\t\tgpios = <&pio 88 GPIO_ACTIVE_HIGH>;\n+ *\t\t\tdefault-state = \"off\";\n+ *\t\t};\n+ */\n \t};\n \n \tmemory {\n"
  },
  {
    "path": "target/linux/mediatek/patches-5.15/114-dts-bpi64-disable-rtc.patch",
    "content": "--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts\n+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts\n@@ -564,12 +564,16 @@\n \tstatus = \"okay\";\n };\n \n+&rtc {\n+\tstatus = \"disabled\";\n+};\n+\n &sata {\n-\tstatus = \"disable\";\n+\tstatus = \"disabled\";\n };\n \n &sata_phy {\n-\tstatus = \"disable\";\n+\tstatus = \"disabled\";\n };\n \n &spi0 {\n"
  },
  {
    "path": "target/linux/mediatek/patches-5.15/115-dts-bpi64-add-snand-support.patch",
    "content": "--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts\n+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts\n@@ -259,14 +259,42 @@\n \tstatus = \"disabled\";\n };\n \n-&nor_flash {\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&spi_nor_pins>;\n-\tstatus = \"disabled\";\n+&bch {\n+\tstatus = \"okay\";\n+};\n \n+&snfi {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&serial_nand_pins>;\n+\tstatus = \"okay\";\n \tflash@0 {\n-\t\tcompatible = \"jedec,spi-nor\";\n+\t\tcompatible = \"spi-nand\";\n \t\treg = <0>;\n+\t\tspi-tx-bus-width = <4>;\n+\t\tspi-rx-bus-width = <4>;\n+\t\tnand-ecc-engine = <&snfi>;\n+\t\tpartitions {\n+\t\t\tcompatible = \"fixed-partitions\";\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <1>;\n+\n+\t\t\tpartition@0 {\n+\t\t\t\tlabel = \"bl2\";\n+\t\t\t\treg = <0x0 0x80000>;\n+\t\t\t\tread-only;\n+\t\t\t};\n+\n+\t\t\tpartition@80000 {\n+\t\t\t\tlabel = \"fip\";\n+\t\t\t\treg = <0x80000 0x200000>;\n+\t\t\t\tread-only;\n+\t\t\t};\n+\n+\t\t\tpartition@280000 {\n+\t\t\t\tlabel = \"ubi\";\n+\t\t\t\treg = <0x280000 0x7d80000>;\n+\t\t\t};\n+\t\t};\n \t};\n };\n \n"
  },
  {
    "path": "target/linux/mediatek/patches-5.15/120-01-v5.18-mtd-nand-ecc-Add-infrastructure-to-support-hardware-.patch",
    "content": "From ad4944aa0b02cb043afe20bc2a018c161e65c992 Mon Sep 17 00:00:00 2001\nFrom: Miquel Raynal <miquel.raynal@bootlin.com>\nDate: Thu, 16 Dec 2021 12:16:38 +0100\nSubject: [PATCH 01/15] mtd: nand: ecc: Add infrastructure to support hardware\n engines\n\nAdd the necessary helpers to register/unregister hardware ECC engines\nthat will be called from ECC engine drivers.\n\nAlso add helpers to get the right engine from the user\nperspective. Keep a reference of the in use ECC engine in order to\nprevent modules to be unloaded. Put the reference when the engine gets\nretired.\n\nA static list of hardware (only) ECC engines is setup to keep track of\nthe registered engines.\n\nSigned-off-by: Miquel Raynal <miquel.raynal@bootlin.com>\nLink: https://lore.kernel.org/linux-mtd/20211216111654.238086-13-miquel.raynal@bootlin.com\n(cherry picked from commit 96489c1c0b53131b0e1ec33e2060538379ad6152)\n---\n drivers/mtd/nand/core.c  | 10 +++--\n drivers/mtd/nand/ecc.c   | 88 ++++++++++++++++++++++++++++++++++++++++\n include/linux/mtd/nand.h | 28 +++++++++++++\n 3 files changed, 123 insertions(+), 3 deletions(-)\n\n--- a/drivers/mtd/nand/core.c\n+++ b/drivers/mtd/nand/core.c\n@@ -232,7 +232,9 @@ static int nanddev_get_ecc_engine(struct\n \t\tnand->ecc.engine = nand_ecc_get_on_die_hw_engine(nand);\n \t\tbreak;\n \tcase NAND_ECC_ENGINE_TYPE_ON_HOST:\n-\t\tpr_err(\"On-host hardware ECC engines not supported yet\\n\");\n+\t\tnand->ecc.engine = nand_ecc_get_on_host_hw_engine(nand);\n+\t\tif (PTR_ERR(nand->ecc.engine) == -EPROBE_DEFER)\n+\t\t\treturn -EPROBE_DEFER;\n \t\tbreak;\n \tdefault:\n \t\tpr_err(\"Missing ECC engine type\\n\");\n@@ -252,7 +254,7 @@ static int nanddev_put_ecc_engine(struct\n {\n \tswitch (nand->ecc.ctx.conf.engine_type) {\n \tcase NAND_ECC_ENGINE_TYPE_ON_HOST:\n-\t\tpr_err(\"On-host hardware ECC engines not supported yet\\n\");\n+\t\tnand_ecc_put_on_host_hw_engine(nand);\n \t\tbreak;\n \tcase NAND_ECC_ENGINE_TYPE_NONE:\n \tcase NAND_ECC_ENGINE_TYPE_SOFT:\n@@ -297,7 +299,9 @@ int nanddev_ecc_engine_init(struct nand_\n \t/* Look for the ECC engine to use */\n \tret = nanddev_get_ecc_engine(nand);\n \tif (ret) {\n-\t\tpr_err(\"No ECC engine found\\n\");\n+\t\tif (ret != -EPROBE_DEFER)\n+\t\t\tpr_err(\"No ECC engine found\\n\");\n+\n \t\treturn ret;\n \t}\n \n--- a/drivers/mtd/nand/ecc.c\n+++ b/drivers/mtd/nand/ecc.c\n@@ -96,6 +96,12 @@\n #include <linux/module.h>\n #include <linux/mtd/nand.h>\n #include <linux/slab.h>\n+#include <linux/of.h>\n+#include <linux/of_device.h>\n+#include <linux/of_platform.h>\n+\n+static LIST_HEAD(on_host_hw_engines);\n+static DEFINE_MUTEX(on_host_hw_engines_mutex);\n \n /**\n  * nand_ecc_init_ctx - Init the ECC engine context\n@@ -611,6 +617,88 @@ struct nand_ecc_engine *nand_ecc_get_on_\n }\n EXPORT_SYMBOL(nand_ecc_get_on_die_hw_engine);\n \n+int nand_ecc_register_on_host_hw_engine(struct nand_ecc_engine *engine)\n+{\n+\tstruct nand_ecc_engine *item;\n+\n+\tif (!engine)\n+\t\treturn -EINVAL;\n+\n+\t/* Prevent multiple registrations of one engine */\n+\tlist_for_each_entry(item, &on_host_hw_engines, node)\n+\t\tif (item == engine)\n+\t\t\treturn 0;\n+\n+\tmutex_lock(&on_host_hw_engines_mutex);\n+\tlist_add_tail(&engine->node, &on_host_hw_engines);\n+\tmutex_unlock(&on_host_hw_engines_mutex);\n+\n+\treturn 0;\n+}\n+EXPORT_SYMBOL(nand_ecc_register_on_host_hw_engine);\n+\n+int nand_ecc_unregister_on_host_hw_engine(struct nand_ecc_engine *engine)\n+{\n+\tif (!engine)\n+\t\treturn -EINVAL;\n+\n+\tmutex_lock(&on_host_hw_engines_mutex);\n+\tlist_del(&engine->node);\n+\tmutex_unlock(&on_host_hw_engines_mutex);\n+\n+\treturn 0;\n+}\n+EXPORT_SYMBOL(nand_ecc_unregister_on_host_hw_engine);\n+\n+static struct nand_ecc_engine *nand_ecc_match_on_host_hw_engine(struct device *dev)\n+{\n+\tstruct nand_ecc_engine *item;\n+\n+\tlist_for_each_entry(item, &on_host_hw_engines, node)\n+\t\tif (item->dev == dev)\n+\t\t\treturn item;\n+\n+\treturn NULL;\n+}\n+\n+struct nand_ecc_engine *nand_ecc_get_on_host_hw_engine(struct nand_device *nand)\n+{\n+\tstruct nand_ecc_engine *engine = NULL;\n+\tstruct device *dev = &nand->mtd.dev;\n+\tstruct platform_device *pdev;\n+\tstruct device_node *np;\n+\n+\tif (list_empty(&on_host_hw_engines))\n+\t\treturn NULL;\n+\n+\t/* Check for an explicit nand-ecc-engine property */\n+\tnp = of_parse_phandle(dev->of_node, \"nand-ecc-engine\", 0);\n+\tif (np) {\n+\t\tpdev = of_find_device_by_node(np);\n+\t\tif (!pdev)\n+\t\t\treturn ERR_PTR(-EPROBE_DEFER);\n+\n+\t\tengine = nand_ecc_match_on_host_hw_engine(&pdev->dev);\n+\t\tplatform_device_put(pdev);\n+\t\tof_node_put(np);\n+\n+\t\tif (!engine)\n+\t\t\treturn ERR_PTR(-EPROBE_DEFER);\n+\t}\n+\n+\tif (engine)\n+\t\tget_device(engine->dev);\n+\n+\treturn engine;\n+}\n+EXPORT_SYMBOL(nand_ecc_get_on_host_hw_engine);\n+\n+void nand_ecc_put_on_host_hw_engine(struct nand_device *nand)\n+{\n+\tput_device(nand->ecc.engine->dev);\n+}\n+EXPORT_SYMBOL(nand_ecc_put_on_host_hw_engine);\n+\n MODULE_LICENSE(\"GPL\");\n MODULE_AUTHOR(\"Miquel Raynal <miquel.raynal@bootlin.com>\");\n MODULE_DESCRIPTION(\"Generic ECC engine\");\n--- a/include/linux/mtd/nand.h\n+++ b/include/linux/mtd/nand.h\n@@ -264,11 +264,35 @@ struct nand_ecc_engine_ops {\n };\n \n /**\n+ * enum nand_ecc_engine_integration - How the NAND ECC engine is integrated\n+ * @NAND_ECC_ENGINE_INTEGRATION_INVALID: Invalid value\n+ * @NAND_ECC_ENGINE_INTEGRATION_PIPELINED: Pipelined engine, performs on-the-fly\n+ *                                         correction, does not need to copy\n+ *                                         data around\n+ * @NAND_ECC_ENGINE_INTEGRATION_EXTERNAL: External engine, needs to bring the\n+ *                                        data into its own area before use\n+ */\n+enum nand_ecc_engine_integration {\n+\tNAND_ECC_ENGINE_INTEGRATION_INVALID,\n+\tNAND_ECC_ENGINE_INTEGRATION_PIPELINED,\n+\tNAND_ECC_ENGINE_INTEGRATION_EXTERNAL,\n+};\n+\n+/**\n  * struct nand_ecc_engine - ECC engine abstraction for NAND devices\n+ * @dev: Host device\n+ * @node: Private field for registration time\n  * @ops: ECC engine operations\n+ * @integration: How the engine is integrated with the host\n+ *               (only relevant on %NAND_ECC_ENGINE_TYPE_ON_HOST engines)\n+ * @priv: Private data\n  */\n struct nand_ecc_engine {\n+\tstruct device *dev;\n+\tstruct list_head node;\n \tstruct nand_ecc_engine_ops *ops;\n+\tenum nand_ecc_engine_integration integration;\n+\tvoid *priv;\n };\n \n void of_get_nand_ecc_user_config(struct nand_device *nand);\n@@ -279,8 +303,12 @@ int nand_ecc_prepare_io_req(struct nand_\n int nand_ecc_finish_io_req(struct nand_device *nand,\n \t\t\t   struct nand_page_io_req *req);\n bool nand_ecc_is_strong_enough(struct nand_device *nand);\n+int nand_ecc_register_on_host_hw_engine(struct nand_ecc_engine *engine);\n+int nand_ecc_unregister_on_host_hw_engine(struct nand_ecc_engine *engine);\n struct nand_ecc_engine *nand_ecc_get_sw_engine(struct nand_device *nand);\n struct nand_ecc_engine *nand_ecc_get_on_die_hw_engine(struct nand_device *nand);\n+struct nand_ecc_engine *nand_ecc_get_on_host_hw_engine(struct nand_device *nand);\n+void nand_ecc_put_on_host_hw_engine(struct nand_device *nand);\n \n #if IS_ENABLED(CONFIG_MTD_NAND_ECC_SW_HAMMING)\n struct nand_ecc_engine *nand_ecc_sw_hamming_get_engine(void);\n"
  },
  {
    "path": "target/linux/mediatek/patches-5.15/120-02-v5.18-mtd-nand-Add-a-new-helper-to-retrieve-the-ECC-contex.patch",
    "content": "From 840b2f8dd2d0579e517140e1f9bbc482eaf4ed07 Mon Sep 17 00:00:00 2001\nFrom: Miquel Raynal <miquel.raynal@bootlin.com>\nDate: Thu, 16 Dec 2021 12:16:39 +0100\nSubject: [PATCH 02/15] mtd: nand: Add a new helper to retrieve the ECC context\n\nIntroduce nand_to_ecc_ctx() which will allow to easily jump to the\nprivate pointer of an ECC context given a NAND device. This is very\nhandy, from the prepare or finish ECC hook, to get the internal context\nout of the NAND device object.\n\nSigned-off-by: Miquel Raynal <miquel.raynal@bootlin.com>\nLink: https://lore.kernel.org/linux-mtd/20211216111654.238086-14-miquel.raynal@bootlin.com\n(cherry picked from commit cda32a618debd3fad8e42757b198719ae180f8f4)\n---\n include/linux/mtd/nand.h | 5 +++++\n 1 file changed, 5 insertions(+)\n\n--- a/include/linux/mtd/nand.h\n+++ b/include/linux/mtd/nand.h\n@@ -990,6 +990,11 @@ int nanddev_markbad(struct nand_device *\n int nanddev_ecc_engine_init(struct nand_device *nand);\n void nanddev_ecc_engine_cleanup(struct nand_device *nand);\n \n+static inline void *nand_to_ecc_ctx(struct nand_device *nand)\n+{\n+\treturn nand->ecc.ctx.priv;\n+}\n+\n /* BBT related functions */\n enum nand_bbt_block_status {\n \tNAND_BBT_BLOCK_STATUS_UNKNOWN,\n"
  },
  {
    "path": "target/linux/mediatek/patches-5.15/120-03-v5.18-mtd-nand-ecc-Provide-a-helper-to-retrieve-a-pileline.patch",
    "content": "From 784866bc4f9f25e0494b77750f95af2a2619e498 Mon Sep 17 00:00:00 2001\nFrom: Miquel Raynal <miquel.raynal@bootlin.com>\nDate: Thu, 16 Dec 2021 12:16:41 +0100\nSubject: [PATCH 03/15] mtd: nand: ecc: Provide a helper to retrieve a\n pilelined engine device\n\nIn a pipelined engine situation, we might either have the host which\ninternally has support for error correction, or have it using an\nexternal hardware block for this purpose. In the former case, the host\nis also the ECC engine. In the latter case, it is not. In order to get\nthe right pointers on the right devices (for example: in order to devm_*\nallocate variables), let's introduce this helper which can safely be\ncalled by pipelined ECC engines in order to retrieve the right device\nstructure.\n\nSigned-off-by: Miquel Raynal <miquel.raynal@bootlin.com>\nLink: https://lore.kernel.org/linux-mtd/20211216111654.238086-16-miquel.raynal@bootlin.com\n(cherry picked from commit 5145abeb0649acf810a32e63bd762e617a9b3309)\n---\n drivers/mtd/nand/ecc.c   | 31 +++++++++++++++++++++++++++++++\n include/linux/mtd/nand.h |  1 +\n 2 files changed, 32 insertions(+)\n\n--- a/drivers/mtd/nand/ecc.c\n+++ b/drivers/mtd/nand/ecc.c\n@@ -699,6 +699,37 @@ void nand_ecc_put_on_host_hw_engine(stru\n }\n EXPORT_SYMBOL(nand_ecc_put_on_host_hw_engine);\n \n+/*\n+ * In the case of a pipelined engine, the device registering the ECC\n+ * engine is not necessarily the ECC engine itself but may be a host controller.\n+ * It is then useful to provide a helper to retrieve the right device object\n+ * which actually represents the ECC engine.\n+ */\n+struct device *nand_ecc_get_engine_dev(struct device *host)\n+{\n+\tstruct platform_device *ecc_pdev;\n+\tstruct device_node *np;\n+\n+\t/*\n+\t * If the device node contains this property, it means we need to follow\n+\t * it in order to get the right ECC engine device we are looking for.\n+\t */\n+\tnp = of_parse_phandle(host->of_node, \"nand-ecc-engine\", 0);\n+\tif (!np)\n+\t\treturn host;\n+\n+\tecc_pdev = of_find_device_by_node(np);\n+\tif (!ecc_pdev) {\n+\t\tof_node_put(np);\n+\t\treturn NULL;\n+\t}\n+\n+\tplatform_device_put(ecc_pdev);\n+\tof_node_put(np);\n+\n+\treturn &ecc_pdev->dev;\n+}\n+\n MODULE_LICENSE(\"GPL\");\n MODULE_AUTHOR(\"Miquel Raynal <miquel.raynal@bootlin.com>\");\n MODULE_DESCRIPTION(\"Generic ECC engine\");\n--- a/include/linux/mtd/nand.h\n+++ b/include/linux/mtd/nand.h\n@@ -309,6 +309,7 @@ struct nand_ecc_engine *nand_ecc_get_sw_\n struct nand_ecc_engine *nand_ecc_get_on_die_hw_engine(struct nand_device *nand);\n struct nand_ecc_engine *nand_ecc_get_on_host_hw_engine(struct nand_device *nand);\n void nand_ecc_put_on_host_hw_engine(struct nand_device *nand);\n+struct device *nand_ecc_get_engine_dev(struct device *host);\n \n #if IS_ENABLED(CONFIG_MTD_NAND_ECC_SW_HAMMING)\n struct nand_ecc_engine *nand_ecc_sw_hamming_get_engine(void);\n"
  },
  {
    "path": "target/linux/mediatek/patches-5.15/120-04-v5.18-spi-spi-mem-Introduce-a-capability-structure.patch",
    "content": "From 3e45577e70cbf8fdc5c13033114989794a3797d5 Mon Sep 17 00:00:00 2001\nFrom: Miquel Raynal <miquel.raynal@bootlin.com>\nDate: Thu, 27 Jan 2022 10:17:56 +0100\nSubject: [PATCH 04/15] spi: spi-mem: Introduce a capability structure\n\nCreate a spi_controller_mem_caps structure and put it within the\nspi_controller structure close to the spi_controller_mem_ops\nstrucure. So far the only field in this structure is the support for dtr\noperations, but soon we will add another parameter.\n\nAlso create a helper to parse the capabilities and check if the\nrequested capability has been set or not.\n\nSigned-off-by: Miquel Raynal <miquel.raynal@bootlin.com>\nReviewed-by: Pratyush Yadav <p.yadav@ti.com>\nReviewed-by: Boris Brezillon <boris.brezillon@collabora.com>\nReviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com>\nReviewed-by: Mark Brown <broonie@kernel.org>\nLink: https://lore.kernel.org/linux-mtd/20220127091808.1043392-2-miquel.raynal@bootlin.com\n(cherry picked from commit 4a3cc7fb6e63bcfdedec25364738f1493345bd20)\n---\n include/linux/spi/spi-mem.h | 11 +++++++++++\n include/linux/spi/spi.h     |  3 +++\n 2 files changed, 14 insertions(+)\n\n--- a/include/linux/spi/spi-mem.h\n+++ b/include/linux/spi/spi-mem.h\n@@ -286,6 +286,17 @@ struct spi_controller_mem_ops {\n };\n \n /**\n+ * struct spi_controller_mem_caps - SPI memory controller capabilities\n+ * @dtr: Supports DTR operations\n+ */\n+struct spi_controller_mem_caps {\n+\tbool dtr;\n+};\n+\n+#define spi_mem_controller_is_capable(ctlr, cap)\t\\\n+\t((ctlr)->mem_caps && (ctlr)->mem_caps->cap)\n+\n+/**\n  * struct spi_mem_driver - SPI memory driver\n  * @spidrv: inherit from a SPI driver\n  * @probe: probe a SPI memory. Usually where detection/initialization takes\n--- a/include/linux/spi/spi.h\n+++ b/include/linux/spi/spi.h\n@@ -23,6 +23,7 @@ struct software_node;\n struct spi_controller;\n struct spi_transfer;\n struct spi_controller_mem_ops;\n+struct spi_controller_mem_caps;\n \n /*\n  * INTERFACES between SPI master-side drivers and SPI slave protocol handlers,\n@@ -419,6 +420,7 @@ extern struct spi_device *spi_new_ancill\n  * @mem_ops: optimized/dedicated operations for interactions with SPI memory.\n  *\t     This field is optional and should only be implemented if the\n  *\t     controller has native support for memory like operations.\n+ * @mem_caps: controller capabilities for the handling of memory operations.\n  * @unprepare_message: undo any work done by prepare_message().\n  * @slave_abort: abort the ongoing transfer request on an SPI slave controller\n  * @cs_gpios: LEGACY: array of GPIO descs to use as chip select lines; one per\n@@ -643,6 +645,7 @@ struct spi_controller {\n \n \t/* Optimized handlers for SPI memory-like operations. */\n \tconst struct spi_controller_mem_ops *mem_ops;\n+\tconst struct spi_controller_mem_caps *mem_caps;\n \n \t/* gpio chip select */\n \tint\t\t\t*cs_gpios;\n"
  },
  {
    "path": "target/linux/mediatek/patches-5.15/120-05-v5.18-spi-spi-mem-Check-the-controller-extra-capabilities.patch",
    "content": "From c9cae7e1e5c87d0aa76b7bededa5191a0c8cf25a Mon Sep 17 00:00:00 2001\nFrom: Miquel Raynal <miquel.raynal@bootlin.com>\nDate: Thu, 27 Jan 2022 10:17:57 +0100\nSubject: [PATCH 05/15] spi: spi-mem: Check the controller extra capabilities\n\nControllers can now provide a spi-mem capabilities structure. Let's make\nuse of it in spi_mem_controller_default_supports_op(). As we want to\ncheck for DTR operations as well as normal operations in a single\nhelper, let's pull the necessary checks from spi_mem_dtr_supports_op()\nfor now.\n\nHowever, because no controller provide these extra capabilities, this\nchange has no effect so far.\n\nSigned-off-by: Miquel Raynal <miquel.raynal@bootlin.com>\nReviewed-by: Pratyush Yadav <p.yadav@ti.com>\nReviewed-by: Boris Brezillon <boris.brezillon@collabora.com>\nReviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com>\nLink: https://lore.kernel.org/linux-mtd/20220127091808.1043392-3-miquel.raynal@bootlin.com\n(cherry picked from commit cb7e96ee81edaa48c67d84c14df2cbe464391c37)\n---\n drivers/spi/spi-mem.c | 17 +++++++++++++----\n 1 file changed, 13 insertions(+), 4 deletions(-)\n\n--- a/drivers/spi/spi-mem.c\n+++ b/drivers/spi/spi-mem.c\n@@ -173,11 +173,20 @@ EXPORT_SYMBOL_GPL(spi_mem_dtr_supports_o\n bool spi_mem_default_supports_op(struct spi_mem *mem,\n \t\t\t\t const struct spi_mem_op *op)\n {\n-\tif (op->cmd.dtr || op->addr.dtr || op->dummy.dtr || op->data.dtr)\n-\t\treturn false;\n+\tstruct spi_controller *ctlr = mem->spi->controller;\n+\tbool op_is_dtr =\n+\t\top->cmd.dtr || op->addr.dtr || op->dummy.dtr || op->data.dtr;\n \n-\tif (op->cmd.nbytes != 1)\n-\t\treturn false;\n+\tif (op_is_dtr) {\n+\t\tif (!spi_mem_controller_is_capable(ctlr, dtr))\n+\t\t\treturn false;\n+\n+\t\tif (op->cmd.nbytes != 2)\n+\t\t\treturn false;\n+\t} else {\n+\t\tif (op->cmd.nbytes != 1)\n+\t\t\treturn false;\n+\t}\n \n \treturn spi_mem_check_buswidth(mem, op);\n }\n"
  },
  {
    "path": "target/linux/mediatek/patches-5.15/120-06-v5.18-spi-spi-mem-Kill-the-spi_mem_dtr_supports_op-helper.patch",
    "content": "From 2e5fba82e4aeb72d71230eef2541881615aaf7cf Mon Sep 17 00:00:00 2001\nFrom: Miquel Raynal <miquel.raynal@bootlin.com>\nDate: Thu, 27 Jan 2022 10:18:00 +0100\nSubject: [PATCH 06/15] spi: spi-mem: Kill the spi_mem_dtr_supports_op() helper\n\nNow that spi_mem_default_supports_op() has access to the static\ncontroller capabilities (relating to memory operations), and now that\nthese capabilities have been filled by the relevant controllers, there\nis no need for a specific helper checking only DTR operations, so let's\njust kill spi_mem_dtr_supports_op() and simply use\nspi_mem_default_supports_op() instead.\n\nSigned-off-by: Miquel Raynal <miquel.raynal@bootlin.com>\nReviewed-by: Pratyush Yadav <p.yadav@ti.com>\nReviewed-by: Boris Brezillon <boris.brezillon@collabora.com>\nReviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com>\nLink: https://lore.kernel.org/linux-mtd/20220127091808.1043392-6-miquel.raynal@bootlin.com\n(cherry picked from commit 9a15efc5d5e6b5beaed0883e5bdcd0b1384c1b20)\n---\n drivers/spi/spi-cadence-quadspi.c |  5 +----\n drivers/spi/spi-mem.c             | 10 ----------\n drivers/spi/spi-mxic.c            | 10 +---------\n include/linux/spi/spi-mem.h       | 11 -----------\n 4 files changed, 2 insertions(+), 34 deletions(-)\n\n--- a/drivers/spi/spi-cadence-quadspi.c\n+++ b/drivers/spi/spi-cadence-quadspi.c\n@@ -1249,10 +1249,7 @@ static bool cqspi_supports_mem_op(struct\n \t\treturn false;\n \t}\n \n-\tif (all_true)\n-\t\treturn spi_mem_dtr_supports_op(mem, op);\n-\telse\n-\t\treturn spi_mem_default_supports_op(mem, op);\n+\treturn spi_mem_default_supports_op(mem, op);\n }\n \n static int cqspi_of_get_flash_pdata(struct platform_device *pdev,\n--- a/drivers/spi/spi-mem.c\n+++ b/drivers/spi/spi-mem.c\n@@ -160,16 +160,6 @@ static bool spi_mem_check_buswidth(struc\n \treturn true;\n }\n \n-bool spi_mem_dtr_supports_op(struct spi_mem *mem,\n-\t\t\t     const struct spi_mem_op *op)\n-{\n-\tif (op->cmd.nbytes != 2)\n-\t\treturn false;\n-\n-\treturn spi_mem_check_buswidth(mem, op);\n-}\n-EXPORT_SYMBOL_GPL(spi_mem_dtr_supports_op);\n-\n bool spi_mem_default_supports_op(struct spi_mem *mem,\n \t\t\t\t const struct spi_mem_op *op)\n {\n--- a/drivers/spi/spi-mxic.c\n+++ b/drivers/spi/spi-mxic.c\n@@ -331,8 +331,6 @@ static int mxic_spi_data_xfer(struct mxi\n static bool mxic_spi_mem_supports_op(struct spi_mem *mem,\n \t\t\t\t     const struct spi_mem_op *op)\n {\n-\tbool all_false;\n-\n \tif (op->data.buswidth > 8 || op->addr.buswidth > 8 ||\n \t    op->dummy.buswidth > 8 || op->cmd.buswidth > 8)\n \t\treturn false;\n@@ -344,13 +342,7 @@ static bool mxic_spi_mem_supports_op(str\n \tif (op->addr.nbytes > 7)\n \t\treturn false;\n \n-\tall_false = !op->cmd.dtr && !op->addr.dtr && !op->dummy.dtr &&\n-\t\t    !op->data.dtr;\n-\n-\tif (all_false)\n-\t\treturn spi_mem_default_supports_op(mem, op);\n-\telse\n-\t\treturn spi_mem_dtr_supports_op(mem, op);\n+\treturn spi_mem_default_supports_op(mem, op);\n }\n \n static int mxic_spi_mem_exec_op(struct spi_mem *mem,\n--- a/include/linux/spi/spi-mem.h\n+++ b/include/linux/spi/spi-mem.h\n@@ -330,10 +330,6 @@ void spi_controller_dma_unmap_mem_op_dat\n \n bool spi_mem_default_supports_op(struct spi_mem *mem,\n \t\t\t\t const struct spi_mem_op *op);\n-\n-bool spi_mem_dtr_supports_op(struct spi_mem *mem,\n-\t\t\t     const struct spi_mem_op *op);\n-\n #else\n static inline int\n spi_controller_dma_map_mem_op_data(struct spi_controller *ctlr,\n@@ -356,13 +352,6 @@ bool spi_mem_default_supports_op(struct\n {\n \treturn false;\n }\n-\n-static inline\n-bool spi_mem_dtr_supports_op(struct spi_mem *mem,\n-\t\t\t     const struct spi_mem_op *op)\n-{\n-\treturn false;\n-}\n #endif /* CONFIG_SPI_MEM */\n \n int spi_mem_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op);\n"
  },
  {
    "path": "target/linux/mediatek/patches-5.15/120-07-v5.18-spi-spi-mem-Add-an-ecc-parameter-to-the-spi_mem_op-s.patch",
    "content": "From 9e7eb0ea442ecb1c3fe443289e288694f10c5148 Mon Sep 17 00:00:00 2001\nFrom: Miquel Raynal <miquel.raynal@bootlin.com>\nDate: Thu, 27 Jan 2022 10:18:01 +0100\nSubject: [PATCH 07/15] spi: spi-mem: Add an ecc parameter to the spi_mem_op\n structure\n\nSoon the SPI-NAND core will need a way to request a SPI controller to\nenable ECC support for a given operation. This is because of the\npipelined integration of certain ECC engines, which are directly managed\nby the SPI controller itself.\n\nIntroduce a spi_mem_op additional field for this purpose: ecc.\n\nSo far this field is left unset and checked to be false by all\nthe SPI controller drivers in their ->supports_op() hook, as they all\ncall spi_mem_default_supports_op().\n\nSigned-off-by: Miquel Raynal <miquel.raynal@bootlin.com>\nAcked-by: Pratyush Yadav <p.yadav@ti.com>\nReviewed-by: Boris Brezillon <boris.brezillon@collabora.com>\nReviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com>\nLink: https://lore.kernel.org/linux-mtd/20220127091808.1043392-7-miquel.raynal@bootlin.com\n(cherry picked from commit a433c2cbd75ab76f277364f44e76f32c7df306e7)\n---\n drivers/spi/spi-mem.c       | 5 +++++\n include/linux/spi/spi-mem.h | 4 ++++\n 2 files changed, 9 insertions(+)\n\n--- a/drivers/spi/spi-mem.c\n+++ b/drivers/spi/spi-mem.c\n@@ -178,6 +178,11 @@ bool spi_mem_default_supports_op(struct\n \t\t\treturn false;\n \t}\n \n+\tif (op->data.ecc) {\n+\t\tif (!spi_mem_controller_is_capable(ctlr, ecc))\n+\t\t\treturn false;\n+\t}\n+\n \treturn spi_mem_check_buswidth(mem, op);\n }\n EXPORT_SYMBOL_GPL(spi_mem_default_supports_op);\n--- a/include/linux/spi/spi-mem.h\n+++ b/include/linux/spi/spi-mem.h\n@@ -89,6 +89,7 @@ enum spi_mem_data_dir {\n  * @dummy.dtr: whether the dummy bytes should be sent in DTR mode or not\n  * @data.buswidth: number of IO lanes used to send/receive the data\n  * @data.dtr: whether the data should be sent in DTR mode or not\n+ * @data.ecc: whether error correction is required or not\n  * @data.dir: direction of the transfer\n  * @data.nbytes: number of data bytes to send/receive. Can be zero if the\n  *\t\t operation does not involve transferring data\n@@ -119,6 +120,7 @@ struct spi_mem_op {\n \tstruct {\n \t\tu8 buswidth;\n \t\tu8 dtr : 1;\n+\t\tu8 ecc : 1;\n \t\tenum spi_mem_data_dir dir;\n \t\tunsigned int nbytes;\n \t\tunion {\n@@ -288,9 +290,11 @@ struct spi_controller_mem_ops {\n /**\n  * struct spi_controller_mem_caps - SPI memory controller capabilities\n  * @dtr: Supports DTR operations\n+ * @ecc: Supports operations with error correction\n  */\n struct spi_controller_mem_caps {\n \tbool dtr;\n+\tbool ecc;\n };\n \n #define spi_mem_controller_is_capable(ctlr, cap)\t\\\n"
  },
  {
    "path": "target/linux/mediatek/patches-5.15/120-08-v5.18-mtd-spinand-Delay-a-little-bit-the-dirmap-creation.patch",
    "content": "From 94ef3c35b935a63f6c156957c92f6cf33c9a8dae Mon Sep 17 00:00:00 2001\nFrom: Miquel Raynal <miquel.raynal@bootlin.com>\nDate: Thu, 27 Jan 2022 10:18:02 +0100\nSubject: [PATCH 08/15] mtd: spinand: Delay a little bit the dirmap creation\n\nAs we will soon tweak the dirmap creation to act a little bit\ndifferently depending on the picked ECC engine, we need to initialize\ndirmaps after ECC engines. This should not have any effect as dirmaps\nare not yet used at this point.\n\nSigned-off-by: Miquel Raynal <miquel.raynal@bootlin.com>\nReviewed-by: Boris Brezillon <boris.brezillon@collabora.com>\nLink: https://lore.kernel.org/linux-mtd/20220127091808.1043392-8-miquel.raynal@bootlin.com\n(cherry picked from commit dc4c2cbf0be2d4a8e2a65013ea2815bb2c8ba949)\n---\n drivers/mtd/nand/spi/core.c | 16 ++++++++--------\n 1 file changed, 8 insertions(+), 8 deletions(-)\n\n--- a/drivers/mtd/nand/spi/core.c\n+++ b/drivers/mtd/nand/spi/core.c\n@@ -1210,14 +1210,6 @@ static int spinand_init(struct spinand_d\n \tif (ret)\n \t\tgoto err_free_bufs;\n \n-\tret = spinand_create_dirmaps(spinand);\n-\tif (ret) {\n-\t\tdev_err(dev,\n-\t\t\t\"Failed to create direct mappings for read/write operations (err = %d)\\n\",\n-\t\t\tret);\n-\t\tgoto err_manuf_cleanup;\n-\t}\n-\n \tret = nanddev_init(nand, &spinand_ops, THIS_MODULE);\n \tif (ret)\n \t\tgoto err_manuf_cleanup;\n@@ -1252,6 +1244,14 @@ static int spinand_init(struct spinand_d\n \tmtd->ecc_strength = nanddev_get_ecc_conf(nand)->strength;\n \tmtd->ecc_step_size = nanddev_get_ecc_conf(nand)->step_size;\n \n+\tret = spinand_create_dirmaps(spinand);\n+\tif (ret) {\n+\t\tdev_err(dev,\n+\t\t\t\"Failed to create direct mappings for read/write operations (err = %d)\\n\",\n+\t\t\tret);\n+\t\tgoto err_cleanup_ecc_engine;\n+\t}\n+\n \treturn 0;\n \n err_cleanup_ecc_engine:\n"
  },
  {
    "path": "target/linux/mediatek/patches-5.15/120-09-v5.18-mtd-spinand-Create-direct-mapping-descriptors-for-EC.patch",
    "content": "From eb4a2d282c3c5752211d69be6dff2674119e5583 Mon Sep 17 00:00:00 2001\nFrom: Miquel Raynal <miquel.raynal@bootlin.com>\nDate: Thu, 27 Jan 2022 10:18:03 +0100\nSubject: [PATCH 09/15] mtd: spinand: Create direct mapping descriptors for ECC\n operations\n\nIn order for pipelined ECC engines to be able to enable/disable the ECC\nengine only when needed and avoid races when future parallel-operations\nwill be supported, we need to provide the information about the use of\nthe ECC engine in the direct mapping hooks. As direct mapping\nconfigurations are meant to be static, it is best to create two new\nmappings: one for regular 'raw' accesses and one for accesses involving\ncorrection. It is up to the driver to use or not the new ECC enable\nboolean contained in the spi-mem operation.\n\nAs dirmaps are not free (they consume a few pages of MMIO address space)\nand because these extra entries are only meant to be used by pipelined\nengines, let's limit their use to this specific type of engine and save\na bit of memory with all the other setups.\n\nSigned-off-by: Miquel Raynal <miquel.raynal@bootlin.com>\nReviewed-by: Boris Brezillon <boris.brezillon@collabora.com>\nLink: https://lore.kernel.org/linux-mtd/20220127091808.1043392-9-miquel.raynal@bootlin.com\n(cherry picked from commit f9d7c7265bcff7d9a17425a8cddf702e8fe159c2)\n---\n drivers/mtd/nand/spi/core.c | 35 +++++++++++++++++++++++++++++++++--\n include/linux/mtd/spinand.h |  2 ++\n 2 files changed, 35 insertions(+), 2 deletions(-)\n\n--- a/drivers/mtd/nand/spi/core.c\n+++ b/drivers/mtd/nand/spi/core.c\n@@ -381,7 +381,10 @@ static int spinand_read_from_cache_op(st\n \t\t}\n \t}\n \n-\trdesc = spinand->dirmaps[req->pos.plane].rdesc;\n+\tif (req->mode == MTD_OPS_RAW)\n+\t\trdesc = spinand->dirmaps[req->pos.plane].rdesc;\n+\telse\n+\t\trdesc = spinand->dirmaps[req->pos.plane].rdesc_ecc;\n \n \twhile (nbytes) {\n \t\tret = spi_mem_dirmap_read(rdesc, column, nbytes, buf);\n@@ -452,7 +455,10 @@ static int spinand_write_to_cache_op(str\n \t\t\t       req->ooblen);\n \t}\n \n-\twdesc = spinand->dirmaps[req->pos.plane].wdesc;\n+\tif (req->mode == MTD_OPS_RAW)\n+\t\twdesc = spinand->dirmaps[req->pos.plane].wdesc;\n+\telse\n+\t\twdesc = spinand->dirmaps[req->pos.plane].wdesc_ecc;\n \n \twhile (nbytes) {\n \t\tret = spi_mem_dirmap_write(wdesc, column, nbytes, buf);\n@@ -865,6 +871,31 @@ static int spinand_create_dirmap(struct\n \n \tspinand->dirmaps[plane].rdesc = desc;\n \n+\tif (nand->ecc.engine->integration != NAND_ECC_ENGINE_INTEGRATION_PIPELINED) {\n+\t\tspinand->dirmaps[plane].wdesc_ecc = spinand->dirmaps[plane].wdesc;\n+\t\tspinand->dirmaps[plane].rdesc_ecc = spinand->dirmaps[plane].rdesc;\n+\n+\t\treturn 0;\n+\t}\n+\n+\tinfo.op_tmpl = *spinand->op_templates.update_cache;\n+\tinfo.op_tmpl.data.ecc = true;\n+\tdesc = devm_spi_mem_dirmap_create(&spinand->spimem->spi->dev,\n+\t\t\t\t\t  spinand->spimem, &info);\n+\tif (IS_ERR(desc))\n+\t\treturn PTR_ERR(desc);\n+\n+\tspinand->dirmaps[plane].wdesc_ecc = desc;\n+\n+\tinfo.op_tmpl = *spinand->op_templates.read_cache;\n+\tinfo.op_tmpl.data.ecc = true;\n+\tdesc = devm_spi_mem_dirmap_create(&spinand->spimem->spi->dev,\n+\t\t\t\t\t  spinand->spimem, &info);\n+\tif (IS_ERR(desc))\n+\t\treturn PTR_ERR(desc);\n+\n+\tspinand->dirmaps[plane].rdesc_ecc = desc;\n+\n \treturn 0;\n }\n \n--- a/include/linux/mtd/spinand.h\n+++ b/include/linux/mtd/spinand.h\n@@ -391,6 +391,8 @@ struct spinand_info {\n struct spinand_dirmap {\n \tstruct spi_mem_dirmap_desc *wdesc;\n \tstruct spi_mem_dirmap_desc *rdesc;\n+\tstruct spi_mem_dirmap_desc *wdesc_ecc;\n+\tstruct spi_mem_dirmap_desc *rdesc_ecc;\n };\n \n /**\n"
  },
  {
    "path": "target/linux/mediatek/patches-5.15/120-11-mtd-nand-make-mtk_ecc.c-a-separated-module.patch",
    "content": "From ebb9653d4a87c64fb679e4c339e867556dada719 Mon Sep 17 00:00:00 2001\nFrom: Chuanhong Guo <gch981213@gmail.com>\nDate: Tue, 22 Mar 2022 18:44:21 +0800\nSubject: [PATCH 11/15] mtd: nand: make mtk_ecc.c a separated module\n\nthis code will be used in mediatek snfi spi-mem controller with\npipelined ECC engine.\n\nSigned-off-by: Chuanhong Guo <gch981213@gmail.com>\n(cherry picked from commit 316f47cec4ce5b81aa8006de202d8769c117a52d)\n---\n drivers/mtd/nand/Kconfig                                   | 7 +++++++\n drivers/mtd/nand/Makefile                                  | 1 +\n drivers/mtd/nand/{raw/mtk_ecc.c => ecc-mtk.c}              | 3 +--\n drivers/mtd/nand/raw/Kconfig                               | 1 +\n drivers/mtd/nand/raw/Makefile                              | 2 +-\n drivers/mtd/nand/raw/mtk_nand.c                            | 2 +-\n .../nand/raw/mtk_ecc.h => include/linux/mtd/nand-ecc-mtk.h | 0\n 7 files changed, 12 insertions(+), 4 deletions(-)\n rename drivers/mtd/nand/{raw/mtk_ecc.c => ecc-mtk.c} (99%)\n rename drivers/mtd/nand/raw/mtk_ecc.h => include/linux/mtd/nand-ecc-mtk.h (100%)\n\n--- a/drivers/mtd/nand/Kconfig\n+++ b/drivers/mtd/nand/Kconfig\n@@ -50,6 +50,13 @@ config MTD_NAND_MTK_BMT\n \tbool \"Support MediaTek NAND Bad-block Management Table\"\n \tdefault n\n \n+config MTD_NAND_ECC_MEDIATEK\n+\ttristate \"Mediatek hardware ECC engine\"\n+\tdepends on HAS_IOMEM\n+\tselect MTD_NAND_ECC\n+\thelp\n+\t  This enables support for the hardware ECC engine from Mediatek.\n+\n endmenu\n \n endmenu\n--- a/drivers/mtd/nand/Makefile\n+++ b/drivers/mtd/nand/Makefile\n@@ -3,6 +3,7 @@\n nandcore-objs := core.o bbt.o\n obj-$(CONFIG_MTD_NAND_CORE) += nandcore.o\n obj-$(CONFIG_MTD_NAND_MTK_BMT)\t+= mtk_bmt.o mtk_bmt_v2.o mtk_bmt_bbt.o mtk_bmt_nmbm.o\n+obj-$(CONFIG_MTD_NAND_ECC_MEDIATEK) += ecc-mtk.o\n \n obj-y\t+= onenand/\n obj-y\t+= raw/\n--- a/drivers/mtd/nand/raw/mtk_ecc.c\n+++ /dev/null\n@@ -1,599 +0,0 @@\n-// SPDX-License-Identifier: GPL-2.0 OR MIT\n-/*\n- * MTK ECC controller driver.\n- * Copyright (C) 2016  MediaTek Inc.\n- * Authors:\tXiaolei Li\t\t<xiaolei.li@mediatek.com>\n- *\t\tJorge Ramirez-Ortiz\t<jorge.ramirez-ortiz@linaro.org>\n- */\n-\n-#include <linux/platform_device.h>\n-#include <linux/dma-mapping.h>\n-#include <linux/interrupt.h>\n-#include <linux/clk.h>\n-#include <linux/module.h>\n-#include <linux/iopoll.h>\n-#include <linux/of.h>\n-#include <linux/of_platform.h>\n-#include <linux/mutex.h>\n-\n-#include \"mtk_ecc.h\"\n-\n-#define ECC_IDLE_MASK\t\tBIT(0)\n-#define ECC_IRQ_EN\t\tBIT(0)\n-#define ECC_PG_IRQ_SEL\t\tBIT(1)\n-#define ECC_OP_ENABLE\t\t(1)\n-#define ECC_OP_DISABLE\t\t(0)\n-\n-#define ECC_ENCCON\t\t(0x00)\n-#define ECC_ENCCNFG\t\t(0x04)\n-#define\t\tECC_MS_SHIFT\t\t(16)\n-#define ECC_ENCDIADDR\t\t(0x08)\n-#define ECC_ENCIDLE\t\t(0x0C)\n-#define ECC_DECCON\t\t(0x100)\n-#define ECC_DECCNFG\t\t(0x104)\n-#define\t\tDEC_EMPTY_EN\t\tBIT(31)\n-#define\t\tDEC_CNFG_CORRECT\t(0x3 << 12)\n-#define ECC_DECIDLE\t\t(0x10C)\n-#define ECC_DECENUM0\t\t(0x114)\n-\n-#define ECC_TIMEOUT\t\t(500000)\n-\n-#define ECC_IDLE_REG(op)\t((op) == ECC_ENCODE ? ECC_ENCIDLE : ECC_DECIDLE)\n-#define ECC_CTL_REG(op)\t\t((op) == ECC_ENCODE ? ECC_ENCCON : ECC_DECCON)\n-\n-struct mtk_ecc_caps {\n-\tu32 err_mask;\n-\tu32 err_shift;\n-\tconst u8 *ecc_strength;\n-\tconst u32 *ecc_regs;\n-\tu8 num_ecc_strength;\n-\tu8 ecc_mode_shift;\n-\tu32 parity_bits;\n-\tint pg_irq_sel;\n-};\n-\n-struct mtk_ecc {\n-\tstruct device *dev;\n-\tconst struct mtk_ecc_caps *caps;\n-\tvoid __iomem *regs;\n-\tstruct clk *clk;\n-\n-\tstruct completion done;\n-\tstruct mutex lock;\n-\tu32 sectors;\n-\n-\tu8 *eccdata;\n-};\n-\n-/* ecc strength that each IP supports */\n-static const u8 ecc_strength_mt2701[] = {\n-\t4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28, 32, 36,\n-\t40, 44, 48, 52, 56, 60\n-};\n-\n-static const u8 ecc_strength_mt2712[] = {\n-\t4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28, 32, 36,\n-\t40, 44, 48, 52, 56, 60, 68, 72, 80\n-};\n-\n-static const u8 ecc_strength_mt7622[] = {\n-\t4, 6, 8, 10, 12\n-};\n-\n-enum mtk_ecc_regs {\n-\tECC_ENCPAR00,\n-\tECC_ENCIRQ_EN,\n-\tECC_ENCIRQ_STA,\n-\tECC_DECDONE,\n-\tECC_DECIRQ_EN,\n-\tECC_DECIRQ_STA,\n-};\n-\n-static int mt2701_ecc_regs[] = {\n-\t[ECC_ENCPAR00] =        0x10,\n-\t[ECC_ENCIRQ_EN] =       0x80,\n-\t[ECC_ENCIRQ_STA] =      0x84,\n-\t[ECC_DECDONE] =         0x124,\n-\t[ECC_DECIRQ_EN] =       0x200,\n-\t[ECC_DECIRQ_STA] =      0x204,\n-};\n-\n-static int mt2712_ecc_regs[] = {\n-\t[ECC_ENCPAR00] =        0x300,\n-\t[ECC_ENCIRQ_EN] =       0x80,\n-\t[ECC_ENCIRQ_STA] =      0x84,\n-\t[ECC_DECDONE] =         0x124,\n-\t[ECC_DECIRQ_EN] =       0x200,\n-\t[ECC_DECIRQ_STA] =      0x204,\n-};\n-\n-static int mt7622_ecc_regs[] = {\n-\t[ECC_ENCPAR00] =        0x10,\n-\t[ECC_ENCIRQ_EN] =       0x30,\n-\t[ECC_ENCIRQ_STA] =      0x34,\n-\t[ECC_DECDONE] =         0x11c,\n-\t[ECC_DECIRQ_EN] =       0x140,\n-\t[ECC_DECIRQ_STA] =      0x144,\n-};\n-\n-static inline void mtk_ecc_wait_idle(struct mtk_ecc *ecc,\n-\t\t\t\t     enum mtk_ecc_operation op)\n-{\n-\tstruct device *dev = ecc->dev;\n-\tu32 val;\n-\tint ret;\n-\n-\tret = readl_poll_timeout_atomic(ecc->regs + ECC_IDLE_REG(op), val,\n-\t\t\t\t\tval & ECC_IDLE_MASK,\n-\t\t\t\t\t10, ECC_TIMEOUT);\n-\tif (ret)\n-\t\tdev_warn(dev, \"%s NOT idle\\n\",\n-\t\t\t op == ECC_ENCODE ? \"encoder\" : \"decoder\");\n-}\n-\n-static irqreturn_t mtk_ecc_irq(int irq, void *id)\n-{\n-\tstruct mtk_ecc *ecc = id;\n-\tu32 dec, enc;\n-\n-\tdec = readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_STA])\n-\t\t    & ECC_IRQ_EN;\n-\tif (dec) {\n-\t\tdec = readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECDONE]);\n-\t\tif (dec & ecc->sectors) {\n-\t\t\t/*\n-\t\t\t * Clear decode IRQ status once again to ensure that\n-\t\t\t * there will be no extra IRQ.\n-\t\t\t */\n-\t\t\treadw(ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_STA]);\n-\t\t\tecc->sectors = 0;\n-\t\t\tcomplete(&ecc->done);\n-\t\t} else {\n-\t\t\treturn IRQ_HANDLED;\n-\t\t}\n-\t} else {\n-\t\tenc = readl(ecc->regs + ecc->caps->ecc_regs[ECC_ENCIRQ_STA])\n-\t\t      & ECC_IRQ_EN;\n-\t\tif (enc)\n-\t\t\tcomplete(&ecc->done);\n-\t\telse\n-\t\t\treturn IRQ_NONE;\n-\t}\n-\n-\treturn IRQ_HANDLED;\n-}\n-\n-static int mtk_ecc_config(struct mtk_ecc *ecc, struct mtk_ecc_config *config)\n-{\n-\tu32 ecc_bit, dec_sz, enc_sz;\n-\tu32 reg, i;\n-\n-\tfor (i = 0; i < ecc->caps->num_ecc_strength; i++) {\n-\t\tif (ecc->caps->ecc_strength[i] == config->strength)\n-\t\t\tbreak;\n-\t}\n-\n-\tif (i == ecc->caps->num_ecc_strength) {\n-\t\tdev_err(ecc->dev, \"invalid ecc strength %d\\n\",\n-\t\t\tconfig->strength);\n-\t\treturn -EINVAL;\n-\t}\n-\n-\tecc_bit = i;\n-\n-\tif (config->op == ECC_ENCODE) {\n-\t\t/* configure ECC encoder (in bits) */\n-\t\tenc_sz = config->len << 3;\n-\n-\t\treg = ecc_bit | (config->mode << ecc->caps->ecc_mode_shift);\n-\t\treg |= (enc_sz << ECC_MS_SHIFT);\n-\t\twritel(reg, ecc->regs + ECC_ENCCNFG);\n-\n-\t\tif (config->mode != ECC_NFI_MODE)\n-\t\t\twritel(lower_32_bits(config->addr),\n-\t\t\t       ecc->regs + ECC_ENCDIADDR);\n-\n-\t} else {\n-\t\t/* configure ECC decoder (in bits) */\n-\t\tdec_sz = (config->len << 3) +\n-\t\t\t config->strength * ecc->caps->parity_bits;\n-\n-\t\treg = ecc_bit | (config->mode << ecc->caps->ecc_mode_shift);\n-\t\treg |= (dec_sz << ECC_MS_SHIFT) | DEC_CNFG_CORRECT;\n-\t\treg |= DEC_EMPTY_EN;\n-\t\twritel(reg, ecc->regs + ECC_DECCNFG);\n-\n-\t\tif (config->sectors)\n-\t\t\tecc->sectors = 1 << (config->sectors - 1);\n-\t}\n-\n-\treturn 0;\n-}\n-\n-void mtk_ecc_get_stats(struct mtk_ecc *ecc, struct mtk_ecc_stats *stats,\n-\t\t       int sectors)\n-{\n-\tu32 offset, i, err;\n-\tu32 bitflips = 0;\n-\n-\tstats->corrected = 0;\n-\tstats->failed = 0;\n-\n-\tfor (i = 0; i < sectors; i++) {\n-\t\toffset = (i >> 2) << 2;\n-\t\terr = readl(ecc->regs + ECC_DECENUM0 + offset);\n-\t\terr = err >> ((i % 4) * ecc->caps->err_shift);\n-\t\terr &= ecc->caps->err_mask;\n-\t\tif (err == ecc->caps->err_mask) {\n-\t\t\t/* uncorrectable errors */\n-\t\t\tstats->failed++;\n-\t\t\tcontinue;\n-\t\t}\n-\n-\t\tstats->corrected += err;\n-\t\tbitflips = max_t(u32, bitflips, err);\n-\t}\n-\n-\tstats->bitflips = bitflips;\n-}\n-EXPORT_SYMBOL(mtk_ecc_get_stats);\n-\n-void mtk_ecc_release(struct mtk_ecc *ecc)\n-{\n-\tclk_disable_unprepare(ecc->clk);\n-\tput_device(ecc->dev);\n-}\n-EXPORT_SYMBOL(mtk_ecc_release);\n-\n-static void mtk_ecc_hw_init(struct mtk_ecc *ecc)\n-{\n-\tmtk_ecc_wait_idle(ecc, ECC_ENCODE);\n-\twritew(ECC_OP_DISABLE, ecc->regs + ECC_ENCCON);\n-\n-\tmtk_ecc_wait_idle(ecc, ECC_DECODE);\n-\twritel(ECC_OP_DISABLE, ecc->regs + ECC_DECCON);\n-}\n-\n-static struct mtk_ecc *mtk_ecc_get(struct device_node *np)\n-{\n-\tstruct platform_device *pdev;\n-\tstruct mtk_ecc *ecc;\n-\n-\tpdev = of_find_device_by_node(np);\n-\tif (!pdev)\n-\t\treturn ERR_PTR(-EPROBE_DEFER);\n-\n-\tecc = platform_get_drvdata(pdev);\n-\tif (!ecc) {\n-\t\tput_device(&pdev->dev);\n-\t\treturn ERR_PTR(-EPROBE_DEFER);\n-\t}\n-\n-\tclk_prepare_enable(ecc->clk);\n-\tmtk_ecc_hw_init(ecc);\n-\n-\treturn ecc;\n-}\n-\n-struct mtk_ecc *of_mtk_ecc_get(struct device_node *of_node)\n-{\n-\tstruct mtk_ecc *ecc = NULL;\n-\tstruct device_node *np;\n-\n-\tnp = of_parse_phandle(of_node, \"ecc-engine\", 0);\n-\tif (np) {\n-\t\tecc = mtk_ecc_get(np);\n-\t\tof_node_put(np);\n-\t}\n-\n-\treturn ecc;\n-}\n-EXPORT_SYMBOL(of_mtk_ecc_get);\n-\n-int mtk_ecc_enable(struct mtk_ecc *ecc, struct mtk_ecc_config *config)\n-{\n-\tenum mtk_ecc_operation op = config->op;\n-\tu16 reg_val;\n-\tint ret;\n-\n-\tret = mutex_lock_interruptible(&ecc->lock);\n-\tif (ret) {\n-\t\tdev_err(ecc->dev, \"interrupted when attempting to lock\\n\");\n-\t\treturn ret;\n-\t}\n-\n-\tmtk_ecc_wait_idle(ecc, op);\n-\n-\tret = mtk_ecc_config(ecc, config);\n-\tif (ret) {\n-\t\tmutex_unlock(&ecc->lock);\n-\t\treturn ret;\n-\t}\n-\n-\tif (config->mode != ECC_NFI_MODE || op != ECC_ENCODE) {\n-\t\tinit_completion(&ecc->done);\n-\t\treg_val = ECC_IRQ_EN;\n-\t\t/*\n-\t\t * For ECC_NFI_MODE, if ecc->caps->pg_irq_sel is 1, then it\n-\t\t * means this chip can only generate one ecc irq during page\n-\t\t * read / write. If is 0, generate one ecc irq each ecc step.\n-\t\t */\n-\t\tif (ecc->caps->pg_irq_sel && config->mode == ECC_NFI_MODE)\n-\t\t\treg_val |= ECC_PG_IRQ_SEL;\n-\t\tif (op == ECC_ENCODE)\n-\t\t\twritew(reg_val, ecc->regs +\n-\t\t\t       ecc->caps->ecc_regs[ECC_ENCIRQ_EN]);\n-\t\telse\n-\t\t\twritew(reg_val, ecc->regs +\n-\t\t\t       ecc->caps->ecc_regs[ECC_DECIRQ_EN]);\n-\t}\n-\n-\twritew(ECC_OP_ENABLE, ecc->regs + ECC_CTL_REG(op));\n-\n-\treturn 0;\n-}\n-EXPORT_SYMBOL(mtk_ecc_enable);\n-\n-void mtk_ecc_disable(struct mtk_ecc *ecc)\n-{\n-\tenum mtk_ecc_operation op = ECC_ENCODE;\n-\n-\t/* find out the running operation */\n-\tif (readw(ecc->regs + ECC_CTL_REG(op)) != ECC_OP_ENABLE)\n-\t\top = ECC_DECODE;\n-\n-\t/* disable it */\n-\tmtk_ecc_wait_idle(ecc, op);\n-\tif (op == ECC_DECODE) {\n-\t\t/*\n-\t\t * Clear decode IRQ status in case there is a timeout to wait\n-\t\t * decode IRQ.\n-\t\t */\n-\t\treadw(ecc->regs + ecc->caps->ecc_regs[ECC_DECDONE]);\n-\t\twritew(0, ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_EN]);\n-\t} else {\n-\t\twritew(0, ecc->regs + ecc->caps->ecc_regs[ECC_ENCIRQ_EN]);\n-\t}\n-\n-\twritew(ECC_OP_DISABLE, ecc->regs + ECC_CTL_REG(op));\n-\n-\tmutex_unlock(&ecc->lock);\n-}\n-EXPORT_SYMBOL(mtk_ecc_disable);\n-\n-int mtk_ecc_wait_done(struct mtk_ecc *ecc, enum mtk_ecc_operation op)\n-{\n-\tint ret;\n-\n-\tret = wait_for_completion_timeout(&ecc->done, msecs_to_jiffies(500));\n-\tif (!ret) {\n-\t\tdev_err(ecc->dev, \"%s timeout - interrupt did not arrive)\\n\",\n-\t\t\t(op == ECC_ENCODE) ? \"encoder\" : \"decoder\");\n-\t\treturn -ETIMEDOUT;\n-\t}\n-\n-\treturn 0;\n-}\n-EXPORT_SYMBOL(mtk_ecc_wait_done);\n-\n-int mtk_ecc_encode(struct mtk_ecc *ecc, struct mtk_ecc_config *config,\n-\t\t   u8 *data, u32 bytes)\n-{\n-\tdma_addr_t addr;\n-\tu32 len;\n-\tint ret;\n-\n-\taddr = dma_map_single(ecc->dev, data, bytes, DMA_TO_DEVICE);\n-\tret = dma_mapping_error(ecc->dev, addr);\n-\tif (ret) {\n-\t\tdev_err(ecc->dev, \"dma mapping error\\n\");\n-\t\treturn -EINVAL;\n-\t}\n-\n-\tconfig->op = ECC_ENCODE;\n-\tconfig->addr = addr;\n-\tret = mtk_ecc_enable(ecc, config);\n-\tif (ret) {\n-\t\tdma_unmap_single(ecc->dev, addr, bytes, DMA_TO_DEVICE);\n-\t\treturn ret;\n-\t}\n-\n-\tret = mtk_ecc_wait_done(ecc, ECC_ENCODE);\n-\tif (ret)\n-\t\tgoto timeout;\n-\n-\tmtk_ecc_wait_idle(ecc, ECC_ENCODE);\n-\n-\t/* Program ECC bytes to OOB: per sector oob = FDM + ECC + SPARE */\n-\tlen = (config->strength * ecc->caps->parity_bits + 7) >> 3;\n-\n-\t/* write the parity bytes generated by the ECC back to temp buffer */\n-\t__ioread32_copy(ecc->eccdata,\n-\t\t\tecc->regs + ecc->caps->ecc_regs[ECC_ENCPAR00],\n-\t\t\tround_up(len, 4));\n-\n-\t/* copy into possibly unaligned OOB region with actual length */\n-\tmemcpy(data + bytes, ecc->eccdata, len);\n-timeout:\n-\n-\tdma_unmap_single(ecc->dev, addr, bytes, DMA_TO_DEVICE);\n-\tmtk_ecc_disable(ecc);\n-\n-\treturn ret;\n-}\n-EXPORT_SYMBOL(mtk_ecc_encode);\n-\n-void mtk_ecc_adjust_strength(struct mtk_ecc *ecc, u32 *p)\n-{\n-\tconst u8 *ecc_strength = ecc->caps->ecc_strength;\n-\tint i;\n-\n-\tfor (i = 0; i < ecc->caps->num_ecc_strength; i++) {\n-\t\tif (*p <= ecc_strength[i]) {\n-\t\t\tif (!i)\n-\t\t\t\t*p = ecc_strength[i];\n-\t\t\telse if (*p != ecc_strength[i])\n-\t\t\t\t*p = ecc_strength[i - 1];\n-\t\t\treturn;\n-\t\t}\n-\t}\n-\n-\t*p = ecc_strength[ecc->caps->num_ecc_strength - 1];\n-}\n-EXPORT_SYMBOL(mtk_ecc_adjust_strength);\n-\n-unsigned int mtk_ecc_get_parity_bits(struct mtk_ecc *ecc)\n-{\n-\treturn ecc->caps->parity_bits;\n-}\n-EXPORT_SYMBOL(mtk_ecc_get_parity_bits);\n-\n-static const struct mtk_ecc_caps mtk_ecc_caps_mt2701 = {\n-\t.err_mask = 0x3f,\n-\t.err_shift = 8,\n-\t.ecc_strength = ecc_strength_mt2701,\n-\t.ecc_regs = mt2701_ecc_regs,\n-\t.num_ecc_strength = 20,\n-\t.ecc_mode_shift = 5,\n-\t.parity_bits = 14,\n-\t.pg_irq_sel = 0,\n-};\n-\n-static const struct mtk_ecc_caps mtk_ecc_caps_mt2712 = {\n-\t.err_mask = 0x7f,\n-\t.err_shift = 8,\n-\t.ecc_strength = ecc_strength_mt2712,\n-\t.ecc_regs = mt2712_ecc_regs,\n-\t.num_ecc_strength = 23,\n-\t.ecc_mode_shift = 5,\n-\t.parity_bits = 14,\n-\t.pg_irq_sel = 1,\n-};\n-\n-static const struct mtk_ecc_caps mtk_ecc_caps_mt7622 = {\n-\t.err_mask = 0x1f,\n-\t.err_shift = 5,\n-\t.ecc_strength = ecc_strength_mt7622,\n-\t.ecc_regs = mt7622_ecc_regs,\n-\t.num_ecc_strength = 5,\n-\t.ecc_mode_shift = 4,\n-\t.parity_bits = 13,\n-\t.pg_irq_sel = 0,\n-};\n-\n-static const struct of_device_id mtk_ecc_dt_match[] = {\n-\t{\n-\t\t.compatible = \"mediatek,mt2701-ecc\",\n-\t\t.data = &mtk_ecc_caps_mt2701,\n-\t}, {\n-\t\t.compatible = \"mediatek,mt2712-ecc\",\n-\t\t.data = &mtk_ecc_caps_mt2712,\n-\t}, {\n-\t\t.compatible = \"mediatek,mt7622-ecc\",\n-\t\t.data = &mtk_ecc_caps_mt7622,\n-\t},\n-\t{},\n-};\n-\n-static int mtk_ecc_probe(struct platform_device *pdev)\n-{\n-\tstruct device *dev = &pdev->dev;\n-\tstruct mtk_ecc *ecc;\n-\tstruct resource *res;\n-\tu32 max_eccdata_size;\n-\tint irq, ret;\n-\n-\tecc = devm_kzalloc(dev, sizeof(*ecc), GFP_KERNEL);\n-\tif (!ecc)\n-\t\treturn -ENOMEM;\n-\n-\tecc->caps = of_device_get_match_data(dev);\n-\n-\tmax_eccdata_size = ecc->caps->num_ecc_strength - 1;\n-\tmax_eccdata_size = ecc->caps->ecc_strength[max_eccdata_size];\n-\tmax_eccdata_size = (max_eccdata_size * ecc->caps->parity_bits + 7) >> 3;\n-\tmax_eccdata_size = round_up(max_eccdata_size, 4);\n-\tecc->eccdata = devm_kzalloc(dev, max_eccdata_size, GFP_KERNEL);\n-\tif (!ecc->eccdata)\n-\t\treturn -ENOMEM;\n-\n-\tres = platform_get_resource(pdev, IORESOURCE_MEM, 0);\n-\tecc->regs = devm_ioremap_resource(dev, res);\n-\tif (IS_ERR(ecc->regs))\n-\t\treturn PTR_ERR(ecc->regs);\n-\n-\tecc->clk = devm_clk_get(dev, NULL);\n-\tif (IS_ERR(ecc->clk)) {\n-\t\tdev_err(dev, \"failed to get clock: %ld\\n\", PTR_ERR(ecc->clk));\n-\t\treturn PTR_ERR(ecc->clk);\n-\t}\n-\n-\tirq = platform_get_irq(pdev, 0);\n-\tif (irq < 0)\n-\t\treturn irq;\n-\n-\tret = dma_set_mask(dev, DMA_BIT_MASK(32));\n-\tif (ret) {\n-\t\tdev_err(dev, \"failed to set DMA mask\\n\");\n-\t\treturn ret;\n-\t}\n-\n-\tret = devm_request_irq(dev, irq, mtk_ecc_irq, 0x0, \"mtk-ecc\", ecc);\n-\tif (ret) {\n-\t\tdev_err(dev, \"failed to request irq\\n\");\n-\t\treturn -EINVAL;\n-\t}\n-\n-\tecc->dev = dev;\n-\tmutex_init(&ecc->lock);\n-\tplatform_set_drvdata(pdev, ecc);\n-\tdev_info(dev, \"probed\\n\");\n-\n-\treturn 0;\n-}\n-\n-#ifdef CONFIG_PM_SLEEP\n-static int mtk_ecc_suspend(struct device *dev)\n-{\n-\tstruct mtk_ecc *ecc = dev_get_drvdata(dev);\n-\n-\tclk_disable_unprepare(ecc->clk);\n-\n-\treturn 0;\n-}\n-\n-static int mtk_ecc_resume(struct device *dev)\n-{\n-\tstruct mtk_ecc *ecc = dev_get_drvdata(dev);\n-\tint ret;\n-\n-\tret = clk_prepare_enable(ecc->clk);\n-\tif (ret) {\n-\t\tdev_err(dev, \"failed to enable clk\\n\");\n-\t\treturn ret;\n-\t}\n-\n-\treturn 0;\n-}\n-\n-static SIMPLE_DEV_PM_OPS(mtk_ecc_pm_ops, mtk_ecc_suspend, mtk_ecc_resume);\n-#endif\n-\n-MODULE_DEVICE_TABLE(of, mtk_ecc_dt_match);\n-\n-static struct platform_driver mtk_ecc_driver = {\n-\t.probe  = mtk_ecc_probe,\n-\t.driver = {\n-\t\t.name  = \"mtk-ecc\",\n-\t\t.of_match_table = of_match_ptr(mtk_ecc_dt_match),\n-#ifdef CONFIG_PM_SLEEP\n-\t\t.pm = &mtk_ecc_pm_ops,\n-#endif\n-\t},\n-};\n-\n-module_platform_driver(mtk_ecc_driver);\n-\n-MODULE_AUTHOR(\"Xiaolei Li <xiaolei.li@mediatek.com>\");\n-MODULE_DESCRIPTION(\"MTK Nand ECC Driver\");\n-MODULE_LICENSE(\"Dual MIT/GPL\");\n--- /dev/null\n+++ b/drivers/mtd/nand/ecc-mtk.c\n@@ -0,0 +1,598 @@\n+// SPDX-License-Identifier: GPL-2.0 OR MIT\n+/*\n+ * MTK ECC controller driver.\n+ * Copyright (C) 2016  MediaTek Inc.\n+ * Authors:\tXiaolei Li\t\t<xiaolei.li@mediatek.com>\n+ *\t\tJorge Ramirez-Ortiz\t<jorge.ramirez-ortiz@linaro.org>\n+ */\n+\n+#include <linux/platform_device.h>\n+#include <linux/dma-mapping.h>\n+#include <linux/interrupt.h>\n+#include <linux/clk.h>\n+#include <linux/module.h>\n+#include <linux/iopoll.h>\n+#include <linux/of.h>\n+#include <linux/of_platform.h>\n+#include <linux/mutex.h>\n+#include <linux/mtd/nand-ecc-mtk.h>\n+\n+#define ECC_IDLE_MASK\t\tBIT(0)\n+#define ECC_IRQ_EN\t\tBIT(0)\n+#define ECC_PG_IRQ_SEL\t\tBIT(1)\n+#define ECC_OP_ENABLE\t\t(1)\n+#define ECC_OP_DISABLE\t\t(0)\n+\n+#define ECC_ENCCON\t\t(0x00)\n+#define ECC_ENCCNFG\t\t(0x04)\n+#define\t\tECC_MS_SHIFT\t\t(16)\n+#define ECC_ENCDIADDR\t\t(0x08)\n+#define ECC_ENCIDLE\t\t(0x0C)\n+#define ECC_DECCON\t\t(0x100)\n+#define ECC_DECCNFG\t\t(0x104)\n+#define\t\tDEC_EMPTY_EN\t\tBIT(31)\n+#define\t\tDEC_CNFG_CORRECT\t(0x3 << 12)\n+#define ECC_DECIDLE\t\t(0x10C)\n+#define ECC_DECENUM0\t\t(0x114)\n+\n+#define ECC_TIMEOUT\t\t(500000)\n+\n+#define ECC_IDLE_REG(op)\t((op) == ECC_ENCODE ? ECC_ENCIDLE : ECC_DECIDLE)\n+#define ECC_CTL_REG(op)\t\t((op) == ECC_ENCODE ? ECC_ENCCON : ECC_DECCON)\n+\n+struct mtk_ecc_caps {\n+\tu32 err_mask;\n+\tu32 err_shift;\n+\tconst u8 *ecc_strength;\n+\tconst u32 *ecc_regs;\n+\tu8 num_ecc_strength;\n+\tu8 ecc_mode_shift;\n+\tu32 parity_bits;\n+\tint pg_irq_sel;\n+};\n+\n+struct mtk_ecc {\n+\tstruct device *dev;\n+\tconst struct mtk_ecc_caps *caps;\n+\tvoid __iomem *regs;\n+\tstruct clk *clk;\n+\n+\tstruct completion done;\n+\tstruct mutex lock;\n+\tu32 sectors;\n+\n+\tu8 *eccdata;\n+};\n+\n+/* ecc strength that each IP supports */\n+static const u8 ecc_strength_mt2701[] = {\n+\t4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28, 32, 36,\n+\t40, 44, 48, 52, 56, 60\n+};\n+\n+static const u8 ecc_strength_mt2712[] = {\n+\t4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28, 32, 36,\n+\t40, 44, 48, 52, 56, 60, 68, 72, 80\n+};\n+\n+static const u8 ecc_strength_mt7622[] = {\n+\t4, 6, 8, 10, 12\n+};\n+\n+enum mtk_ecc_regs {\n+\tECC_ENCPAR00,\n+\tECC_ENCIRQ_EN,\n+\tECC_ENCIRQ_STA,\n+\tECC_DECDONE,\n+\tECC_DECIRQ_EN,\n+\tECC_DECIRQ_STA,\n+};\n+\n+static int mt2701_ecc_regs[] = {\n+\t[ECC_ENCPAR00] =        0x10,\n+\t[ECC_ENCIRQ_EN] =       0x80,\n+\t[ECC_ENCIRQ_STA] =      0x84,\n+\t[ECC_DECDONE] =         0x124,\n+\t[ECC_DECIRQ_EN] =       0x200,\n+\t[ECC_DECIRQ_STA] =      0x204,\n+};\n+\n+static int mt2712_ecc_regs[] = {\n+\t[ECC_ENCPAR00] =        0x300,\n+\t[ECC_ENCIRQ_EN] =       0x80,\n+\t[ECC_ENCIRQ_STA] =      0x84,\n+\t[ECC_DECDONE] =         0x124,\n+\t[ECC_DECIRQ_EN] =       0x200,\n+\t[ECC_DECIRQ_STA] =      0x204,\n+};\n+\n+static int mt7622_ecc_regs[] = {\n+\t[ECC_ENCPAR00] =        0x10,\n+\t[ECC_ENCIRQ_EN] =       0x30,\n+\t[ECC_ENCIRQ_STA] =      0x34,\n+\t[ECC_DECDONE] =         0x11c,\n+\t[ECC_DECIRQ_EN] =       0x140,\n+\t[ECC_DECIRQ_STA] =      0x144,\n+};\n+\n+static inline void mtk_ecc_wait_idle(struct mtk_ecc *ecc,\n+\t\t\t\t     enum mtk_ecc_operation op)\n+{\n+\tstruct device *dev = ecc->dev;\n+\tu32 val;\n+\tint ret;\n+\n+\tret = readl_poll_timeout_atomic(ecc->regs + ECC_IDLE_REG(op), val,\n+\t\t\t\t\tval & ECC_IDLE_MASK,\n+\t\t\t\t\t10, ECC_TIMEOUT);\n+\tif (ret)\n+\t\tdev_warn(dev, \"%s NOT idle\\n\",\n+\t\t\t op == ECC_ENCODE ? \"encoder\" : \"decoder\");\n+}\n+\n+static irqreturn_t mtk_ecc_irq(int irq, void *id)\n+{\n+\tstruct mtk_ecc *ecc = id;\n+\tu32 dec, enc;\n+\n+\tdec = readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_STA])\n+\t\t    & ECC_IRQ_EN;\n+\tif (dec) {\n+\t\tdec = readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECDONE]);\n+\t\tif (dec & ecc->sectors) {\n+\t\t\t/*\n+\t\t\t * Clear decode IRQ status once again to ensure that\n+\t\t\t * there will be no extra IRQ.\n+\t\t\t */\n+\t\t\treadw(ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_STA]);\n+\t\t\tecc->sectors = 0;\n+\t\t\tcomplete(&ecc->done);\n+\t\t} else {\n+\t\t\treturn IRQ_HANDLED;\n+\t\t}\n+\t} else {\n+\t\tenc = readl(ecc->regs + ecc->caps->ecc_regs[ECC_ENCIRQ_STA])\n+\t\t      & ECC_IRQ_EN;\n+\t\tif (enc)\n+\t\t\tcomplete(&ecc->done);\n+\t\telse\n+\t\t\treturn IRQ_NONE;\n+\t}\n+\n+\treturn IRQ_HANDLED;\n+}\n+\n+static int mtk_ecc_config(struct mtk_ecc *ecc, struct mtk_ecc_config *config)\n+{\n+\tu32 ecc_bit, dec_sz, enc_sz;\n+\tu32 reg, i;\n+\n+\tfor (i = 0; i < ecc->caps->num_ecc_strength; i++) {\n+\t\tif (ecc->caps->ecc_strength[i] == config->strength)\n+\t\t\tbreak;\n+\t}\n+\n+\tif (i == ecc->caps->num_ecc_strength) {\n+\t\tdev_err(ecc->dev, \"invalid ecc strength %d\\n\",\n+\t\t\tconfig->strength);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tecc_bit = i;\n+\n+\tif (config->op == ECC_ENCODE) {\n+\t\t/* configure ECC encoder (in bits) */\n+\t\tenc_sz = config->len << 3;\n+\n+\t\treg = ecc_bit | (config->mode << ecc->caps->ecc_mode_shift);\n+\t\treg |= (enc_sz << ECC_MS_SHIFT);\n+\t\twritel(reg, ecc->regs + ECC_ENCCNFG);\n+\n+\t\tif (config->mode != ECC_NFI_MODE)\n+\t\t\twritel(lower_32_bits(config->addr),\n+\t\t\t       ecc->regs + ECC_ENCDIADDR);\n+\n+\t} else {\n+\t\t/* configure ECC decoder (in bits) */\n+\t\tdec_sz = (config->len << 3) +\n+\t\t\t config->strength * ecc->caps->parity_bits;\n+\n+\t\treg = ecc_bit | (config->mode << ecc->caps->ecc_mode_shift);\n+\t\treg |= (dec_sz << ECC_MS_SHIFT) | DEC_CNFG_CORRECT;\n+\t\treg |= DEC_EMPTY_EN;\n+\t\twritel(reg, ecc->regs + ECC_DECCNFG);\n+\n+\t\tif (config->sectors)\n+\t\t\tecc->sectors = 1 << (config->sectors - 1);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+void mtk_ecc_get_stats(struct mtk_ecc *ecc, struct mtk_ecc_stats *stats,\n+\t\t       int sectors)\n+{\n+\tu32 offset, i, err;\n+\tu32 bitflips = 0;\n+\n+\tstats->corrected = 0;\n+\tstats->failed = 0;\n+\n+\tfor (i = 0; i < sectors; i++) {\n+\t\toffset = (i >> 2) << 2;\n+\t\terr = readl(ecc->regs + ECC_DECENUM0 + offset);\n+\t\terr = err >> ((i % 4) * ecc->caps->err_shift);\n+\t\terr &= ecc->caps->err_mask;\n+\t\tif (err == ecc->caps->err_mask) {\n+\t\t\t/* uncorrectable errors */\n+\t\t\tstats->failed++;\n+\t\t\tcontinue;\n+\t\t}\n+\n+\t\tstats->corrected += err;\n+\t\tbitflips = max_t(u32, bitflips, err);\n+\t}\n+\n+\tstats->bitflips = bitflips;\n+}\n+EXPORT_SYMBOL(mtk_ecc_get_stats);\n+\n+void mtk_ecc_release(struct mtk_ecc *ecc)\n+{\n+\tclk_disable_unprepare(ecc->clk);\n+\tput_device(ecc->dev);\n+}\n+EXPORT_SYMBOL(mtk_ecc_release);\n+\n+static void mtk_ecc_hw_init(struct mtk_ecc *ecc)\n+{\n+\tmtk_ecc_wait_idle(ecc, ECC_ENCODE);\n+\twritew(ECC_OP_DISABLE, ecc->regs + ECC_ENCCON);\n+\n+\tmtk_ecc_wait_idle(ecc, ECC_DECODE);\n+\twritel(ECC_OP_DISABLE, ecc->regs + ECC_DECCON);\n+}\n+\n+static struct mtk_ecc *mtk_ecc_get(struct device_node *np)\n+{\n+\tstruct platform_device *pdev;\n+\tstruct mtk_ecc *ecc;\n+\n+\tpdev = of_find_device_by_node(np);\n+\tif (!pdev)\n+\t\treturn ERR_PTR(-EPROBE_DEFER);\n+\n+\tecc = platform_get_drvdata(pdev);\n+\tif (!ecc) {\n+\t\tput_device(&pdev->dev);\n+\t\treturn ERR_PTR(-EPROBE_DEFER);\n+\t}\n+\n+\tclk_prepare_enable(ecc->clk);\n+\tmtk_ecc_hw_init(ecc);\n+\n+\treturn ecc;\n+}\n+\n+struct mtk_ecc *of_mtk_ecc_get(struct device_node *of_node)\n+{\n+\tstruct mtk_ecc *ecc = NULL;\n+\tstruct device_node *np;\n+\n+\tnp = of_parse_phandle(of_node, \"ecc-engine\", 0);\n+\tif (np) {\n+\t\tecc = mtk_ecc_get(np);\n+\t\tof_node_put(np);\n+\t}\n+\n+\treturn ecc;\n+}\n+EXPORT_SYMBOL(of_mtk_ecc_get);\n+\n+int mtk_ecc_enable(struct mtk_ecc *ecc, struct mtk_ecc_config *config)\n+{\n+\tenum mtk_ecc_operation op = config->op;\n+\tu16 reg_val;\n+\tint ret;\n+\n+\tret = mutex_lock_interruptible(&ecc->lock);\n+\tif (ret) {\n+\t\tdev_err(ecc->dev, \"interrupted when attempting to lock\\n\");\n+\t\treturn ret;\n+\t}\n+\n+\tmtk_ecc_wait_idle(ecc, op);\n+\n+\tret = mtk_ecc_config(ecc, config);\n+\tif (ret) {\n+\t\tmutex_unlock(&ecc->lock);\n+\t\treturn ret;\n+\t}\n+\n+\tif (config->mode != ECC_NFI_MODE || op != ECC_ENCODE) {\n+\t\tinit_completion(&ecc->done);\n+\t\treg_val = ECC_IRQ_EN;\n+\t\t/*\n+\t\t * For ECC_NFI_MODE, if ecc->caps->pg_irq_sel is 1, then it\n+\t\t * means this chip can only generate one ecc irq during page\n+\t\t * read / write. If is 0, generate one ecc irq each ecc step.\n+\t\t */\n+\t\tif (ecc->caps->pg_irq_sel && config->mode == ECC_NFI_MODE)\n+\t\t\treg_val |= ECC_PG_IRQ_SEL;\n+\t\tif (op == ECC_ENCODE)\n+\t\t\twritew(reg_val, ecc->regs +\n+\t\t\t       ecc->caps->ecc_regs[ECC_ENCIRQ_EN]);\n+\t\telse\n+\t\t\twritew(reg_val, ecc->regs +\n+\t\t\t       ecc->caps->ecc_regs[ECC_DECIRQ_EN]);\n+\t}\n+\n+\twritew(ECC_OP_ENABLE, ecc->regs + ECC_CTL_REG(op));\n+\n+\treturn 0;\n+}\n+EXPORT_SYMBOL(mtk_ecc_enable);\n+\n+void mtk_ecc_disable(struct mtk_ecc *ecc)\n+{\n+\tenum mtk_ecc_operation op = ECC_ENCODE;\n+\n+\t/* find out the running operation */\n+\tif (readw(ecc->regs + ECC_CTL_REG(op)) != ECC_OP_ENABLE)\n+\t\top = ECC_DECODE;\n+\n+\t/* disable it */\n+\tmtk_ecc_wait_idle(ecc, op);\n+\tif (op == ECC_DECODE) {\n+\t\t/*\n+\t\t * Clear decode IRQ status in case there is a timeout to wait\n+\t\t * decode IRQ.\n+\t\t */\n+\t\treadw(ecc->regs + ecc->caps->ecc_regs[ECC_DECDONE]);\n+\t\twritew(0, ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_EN]);\n+\t} else {\n+\t\twritew(0, ecc->regs + ecc->caps->ecc_regs[ECC_ENCIRQ_EN]);\n+\t}\n+\n+\twritew(ECC_OP_DISABLE, ecc->regs + ECC_CTL_REG(op));\n+\n+\tmutex_unlock(&ecc->lock);\n+}\n+EXPORT_SYMBOL(mtk_ecc_disable);\n+\n+int mtk_ecc_wait_done(struct mtk_ecc *ecc, enum mtk_ecc_operation op)\n+{\n+\tint ret;\n+\n+\tret = wait_for_completion_timeout(&ecc->done, msecs_to_jiffies(500));\n+\tif (!ret) {\n+\t\tdev_err(ecc->dev, \"%s timeout - interrupt did not arrive)\\n\",\n+\t\t\t(op == ECC_ENCODE) ? \"encoder\" : \"decoder\");\n+\t\treturn -ETIMEDOUT;\n+\t}\n+\n+\treturn 0;\n+}\n+EXPORT_SYMBOL(mtk_ecc_wait_done);\n+\n+int mtk_ecc_encode(struct mtk_ecc *ecc, struct mtk_ecc_config *config,\n+\t\t   u8 *data, u32 bytes)\n+{\n+\tdma_addr_t addr;\n+\tu32 len;\n+\tint ret;\n+\n+\taddr = dma_map_single(ecc->dev, data, bytes, DMA_TO_DEVICE);\n+\tret = dma_mapping_error(ecc->dev, addr);\n+\tif (ret) {\n+\t\tdev_err(ecc->dev, \"dma mapping error\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tconfig->op = ECC_ENCODE;\n+\tconfig->addr = addr;\n+\tret = mtk_ecc_enable(ecc, config);\n+\tif (ret) {\n+\t\tdma_unmap_single(ecc->dev, addr, bytes, DMA_TO_DEVICE);\n+\t\treturn ret;\n+\t}\n+\n+\tret = mtk_ecc_wait_done(ecc, ECC_ENCODE);\n+\tif (ret)\n+\t\tgoto timeout;\n+\n+\tmtk_ecc_wait_idle(ecc, ECC_ENCODE);\n+\n+\t/* Program ECC bytes to OOB: per sector oob = FDM + ECC + SPARE */\n+\tlen = (config->strength * ecc->caps->parity_bits + 7) >> 3;\n+\n+\t/* write the parity bytes generated by the ECC back to temp buffer */\n+\t__ioread32_copy(ecc->eccdata,\n+\t\t\tecc->regs + ecc->caps->ecc_regs[ECC_ENCPAR00],\n+\t\t\tround_up(len, 4));\n+\n+\t/* copy into possibly unaligned OOB region with actual length */\n+\tmemcpy(data + bytes, ecc->eccdata, len);\n+timeout:\n+\n+\tdma_unmap_single(ecc->dev, addr, bytes, DMA_TO_DEVICE);\n+\tmtk_ecc_disable(ecc);\n+\n+\treturn ret;\n+}\n+EXPORT_SYMBOL(mtk_ecc_encode);\n+\n+void mtk_ecc_adjust_strength(struct mtk_ecc *ecc, u32 *p)\n+{\n+\tconst u8 *ecc_strength = ecc->caps->ecc_strength;\n+\tint i;\n+\n+\tfor (i = 0; i < ecc->caps->num_ecc_strength; i++) {\n+\t\tif (*p <= ecc_strength[i]) {\n+\t\t\tif (!i)\n+\t\t\t\t*p = ecc_strength[i];\n+\t\t\telse if (*p != ecc_strength[i])\n+\t\t\t\t*p = ecc_strength[i - 1];\n+\t\t\treturn;\n+\t\t}\n+\t}\n+\n+\t*p = ecc_strength[ecc->caps->num_ecc_strength - 1];\n+}\n+EXPORT_SYMBOL(mtk_ecc_adjust_strength);\n+\n+unsigned int mtk_ecc_get_parity_bits(struct mtk_ecc *ecc)\n+{\n+\treturn ecc->caps->parity_bits;\n+}\n+EXPORT_SYMBOL(mtk_ecc_get_parity_bits);\n+\n+static const struct mtk_ecc_caps mtk_ecc_caps_mt2701 = {\n+\t.err_mask = 0x3f,\n+\t.err_shift = 8,\n+\t.ecc_strength = ecc_strength_mt2701,\n+\t.ecc_regs = mt2701_ecc_regs,\n+\t.num_ecc_strength = 20,\n+\t.ecc_mode_shift = 5,\n+\t.parity_bits = 14,\n+\t.pg_irq_sel = 0,\n+};\n+\n+static const struct mtk_ecc_caps mtk_ecc_caps_mt2712 = {\n+\t.err_mask = 0x7f,\n+\t.err_shift = 8,\n+\t.ecc_strength = ecc_strength_mt2712,\n+\t.ecc_regs = mt2712_ecc_regs,\n+\t.num_ecc_strength = 23,\n+\t.ecc_mode_shift = 5,\n+\t.parity_bits = 14,\n+\t.pg_irq_sel = 1,\n+};\n+\n+static const struct mtk_ecc_caps mtk_ecc_caps_mt7622 = {\n+\t.err_mask = 0x1f,\n+\t.err_shift = 5,\n+\t.ecc_strength = ecc_strength_mt7622,\n+\t.ecc_regs = mt7622_ecc_regs,\n+\t.num_ecc_strength = 5,\n+\t.ecc_mode_shift = 4,\n+\t.parity_bits = 13,\n+\t.pg_irq_sel = 0,\n+};\n+\n+static const struct of_device_id mtk_ecc_dt_match[] = {\n+\t{\n+\t\t.compatible = \"mediatek,mt2701-ecc\",\n+\t\t.data = &mtk_ecc_caps_mt2701,\n+\t}, {\n+\t\t.compatible = \"mediatek,mt2712-ecc\",\n+\t\t.data = &mtk_ecc_caps_mt2712,\n+\t}, {\n+\t\t.compatible = \"mediatek,mt7622-ecc\",\n+\t\t.data = &mtk_ecc_caps_mt7622,\n+\t},\n+\t{},\n+};\n+\n+static int mtk_ecc_probe(struct platform_device *pdev)\n+{\n+\tstruct device *dev = &pdev->dev;\n+\tstruct mtk_ecc *ecc;\n+\tstruct resource *res;\n+\tu32 max_eccdata_size;\n+\tint irq, ret;\n+\n+\tecc = devm_kzalloc(dev, sizeof(*ecc), GFP_KERNEL);\n+\tif (!ecc)\n+\t\treturn -ENOMEM;\n+\n+\tecc->caps = of_device_get_match_data(dev);\n+\n+\tmax_eccdata_size = ecc->caps->num_ecc_strength - 1;\n+\tmax_eccdata_size = ecc->caps->ecc_strength[max_eccdata_size];\n+\tmax_eccdata_size = (max_eccdata_size * ecc->caps->parity_bits + 7) >> 3;\n+\tmax_eccdata_size = round_up(max_eccdata_size, 4);\n+\tecc->eccdata = devm_kzalloc(dev, max_eccdata_size, GFP_KERNEL);\n+\tif (!ecc->eccdata)\n+\t\treturn -ENOMEM;\n+\n+\tres = platform_get_resource(pdev, IORESOURCE_MEM, 0);\n+\tecc->regs = devm_ioremap_resource(dev, res);\n+\tif (IS_ERR(ecc->regs))\n+\t\treturn PTR_ERR(ecc->regs);\n+\n+\tecc->clk = devm_clk_get(dev, NULL);\n+\tif (IS_ERR(ecc->clk)) {\n+\t\tdev_err(dev, \"failed to get clock: %ld\\n\", PTR_ERR(ecc->clk));\n+\t\treturn PTR_ERR(ecc->clk);\n+\t}\n+\n+\tirq = platform_get_irq(pdev, 0);\n+\tif (irq < 0)\n+\t\treturn irq;\n+\n+\tret = dma_set_mask(dev, DMA_BIT_MASK(32));\n+\tif (ret) {\n+\t\tdev_err(dev, \"failed to set DMA mask\\n\");\n+\t\treturn ret;\n+\t}\n+\n+\tret = devm_request_irq(dev, irq, mtk_ecc_irq, 0x0, \"mtk-ecc\", ecc);\n+\tif (ret) {\n+\t\tdev_err(dev, \"failed to request irq\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tecc->dev = dev;\n+\tmutex_init(&ecc->lock);\n+\tplatform_set_drvdata(pdev, ecc);\n+\tdev_info(dev, \"probed\\n\");\n+\n+\treturn 0;\n+}\n+\n+#ifdef CONFIG_PM_SLEEP\n+static int mtk_ecc_suspend(struct device *dev)\n+{\n+\tstruct mtk_ecc *ecc = dev_get_drvdata(dev);\n+\n+\tclk_disable_unprepare(ecc->clk);\n+\n+\treturn 0;\n+}\n+\n+static int mtk_ecc_resume(struct device *dev)\n+{\n+\tstruct mtk_ecc *ecc = dev_get_drvdata(dev);\n+\tint ret;\n+\n+\tret = clk_prepare_enable(ecc->clk);\n+\tif (ret) {\n+\t\tdev_err(dev, \"failed to enable clk\\n\");\n+\t\treturn ret;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static SIMPLE_DEV_PM_OPS(mtk_ecc_pm_ops, mtk_ecc_suspend, mtk_ecc_resume);\n+#endif\n+\n+MODULE_DEVICE_TABLE(of, mtk_ecc_dt_match);\n+\n+static struct platform_driver mtk_ecc_driver = {\n+\t.probe  = mtk_ecc_probe,\n+\t.driver = {\n+\t\t.name  = \"mtk-ecc\",\n+\t\t.of_match_table = of_match_ptr(mtk_ecc_dt_match),\n+#ifdef CONFIG_PM_SLEEP\n+\t\t.pm = &mtk_ecc_pm_ops,\n+#endif\n+\t},\n+};\n+\n+module_platform_driver(mtk_ecc_driver);\n+\n+MODULE_AUTHOR(\"Xiaolei Li <xiaolei.li@mediatek.com>\");\n+MODULE_DESCRIPTION(\"MTK Nand ECC Driver\");\n+MODULE_LICENSE(\"Dual MIT/GPL\");\n--- a/drivers/mtd/nand/raw/Kconfig\n+++ b/drivers/mtd/nand/raw/Kconfig\n@@ -360,6 +360,7 @@ config MTD_NAND_QCOM\n \n config MTD_NAND_MTK\n \ttristate \"MTK NAND controller\"\n+\tdepends on MTD_NAND_ECC_MEDIATEK\n \tdepends on ARCH_MEDIATEK || COMPILE_TEST\n \tdepends on HAS_IOMEM\n \thelp\n--- a/drivers/mtd/nand/raw/Makefile\n+++ b/drivers/mtd/nand/raw/Makefile\n@@ -48,7 +48,7 @@ obj-$(CONFIG_MTD_NAND_SUNXI)\t\t+= sunxi_n\n obj-$(CONFIG_MTD_NAND_HISI504)\t        += hisi504_nand.o\n obj-$(CONFIG_MTD_NAND_BRCMNAND)\t\t+= brcmnand/\n obj-$(CONFIG_MTD_NAND_QCOM)\t\t+= qcom_nandc.o\n-obj-$(CONFIG_MTD_NAND_MTK)\t\t+= mtk_ecc.o mtk_nand.o\n+obj-$(CONFIG_MTD_NAND_MTK)\t\t+= mtk_nand.o\n obj-$(CONFIG_MTD_NAND_MXIC)\t\t+= mxic_nand.o\n obj-$(CONFIG_MTD_NAND_TEGRA)\t\t+= tegra_nand.o\n obj-$(CONFIG_MTD_NAND_STM32_FMC2)\t+= stm32_fmc2_nand.o\n--- a/drivers/mtd/nand/raw/mtk_nand.c\n+++ b/drivers/mtd/nand/raw/mtk_nand.c\n@@ -17,7 +17,7 @@\n #include <linux/iopoll.h>\n #include <linux/of.h>\n #include <linux/of_device.h>\n-#include \"mtk_ecc.h\"\n+#include <linux/mtd/nand-ecc-mtk.h>\n \n /* NAND controller register definition */\n #define NFI_CNFG\t\t(0x00)\n--- a/drivers/mtd/nand/raw/mtk_ecc.h\n+++ /dev/null\n@@ -1,47 +0,0 @@\n-/* SPDX-License-Identifier: GPL-2.0 OR MIT */\n-/*\n- * MTK SDG1 ECC controller\n- *\n- * Copyright (c) 2016 Mediatek\n- * Authors:\tXiaolei Li\t\t<xiaolei.li@mediatek.com>\n- *\t\tJorge Ramirez-Ortiz\t<jorge.ramirez-ortiz@linaro.org>\n- */\n-\n-#ifndef __DRIVERS_MTD_NAND_MTK_ECC_H__\n-#define __DRIVERS_MTD_NAND_MTK_ECC_H__\n-\n-#include <linux/types.h>\n-\n-enum mtk_ecc_mode {ECC_DMA_MODE = 0, ECC_NFI_MODE = 1};\n-enum mtk_ecc_operation {ECC_ENCODE, ECC_DECODE};\n-\n-struct device_node;\n-struct mtk_ecc;\n-\n-struct mtk_ecc_stats {\n-\tu32 corrected;\n-\tu32 bitflips;\n-\tu32 failed;\n-};\n-\n-struct mtk_ecc_config {\n-\tenum mtk_ecc_operation op;\n-\tenum mtk_ecc_mode mode;\n-\tdma_addr_t addr;\n-\tu32 strength;\n-\tu32 sectors;\n-\tu32 len;\n-};\n-\n-int mtk_ecc_encode(struct mtk_ecc *, struct mtk_ecc_config *, u8 *, u32);\n-void mtk_ecc_get_stats(struct mtk_ecc *, struct mtk_ecc_stats *, int);\n-int mtk_ecc_wait_done(struct mtk_ecc *, enum mtk_ecc_operation);\n-int mtk_ecc_enable(struct mtk_ecc *, struct mtk_ecc_config *);\n-void mtk_ecc_disable(struct mtk_ecc *);\n-void mtk_ecc_adjust_strength(struct mtk_ecc *ecc, u32 *p);\n-unsigned int mtk_ecc_get_parity_bits(struct mtk_ecc *ecc);\n-\n-struct mtk_ecc *of_mtk_ecc_get(struct device_node *);\n-void mtk_ecc_release(struct mtk_ecc *);\n-\n-#endif\n--- /dev/null\n+++ b/include/linux/mtd/nand-ecc-mtk.h\n@@ -0,0 +1,47 @@\n+/* SPDX-License-Identifier: GPL-2.0 OR MIT */\n+/*\n+ * MTK SDG1 ECC controller\n+ *\n+ * Copyright (c) 2016 Mediatek\n+ * Authors:\tXiaolei Li\t\t<xiaolei.li@mediatek.com>\n+ *\t\tJorge Ramirez-Ortiz\t<jorge.ramirez-ortiz@linaro.org>\n+ */\n+\n+#ifndef __DRIVERS_MTD_NAND_MTK_ECC_H__\n+#define __DRIVERS_MTD_NAND_MTK_ECC_H__\n+\n+#include <linux/types.h>\n+\n+enum mtk_ecc_mode {ECC_DMA_MODE = 0, ECC_NFI_MODE = 1};\n+enum mtk_ecc_operation {ECC_ENCODE, ECC_DECODE};\n+\n+struct device_node;\n+struct mtk_ecc;\n+\n+struct mtk_ecc_stats {\n+\tu32 corrected;\n+\tu32 bitflips;\n+\tu32 failed;\n+};\n+\n+struct mtk_ecc_config {\n+\tenum mtk_ecc_operation op;\n+\tenum mtk_ecc_mode mode;\n+\tdma_addr_t addr;\n+\tu32 strength;\n+\tu32 sectors;\n+\tu32 len;\n+};\n+\n+int mtk_ecc_encode(struct mtk_ecc *, struct mtk_ecc_config *, u8 *, u32);\n+void mtk_ecc_get_stats(struct mtk_ecc *, struct mtk_ecc_stats *, int);\n+int mtk_ecc_wait_done(struct mtk_ecc *, enum mtk_ecc_operation);\n+int mtk_ecc_enable(struct mtk_ecc *, struct mtk_ecc_config *);\n+void mtk_ecc_disable(struct mtk_ecc *);\n+void mtk_ecc_adjust_strength(struct mtk_ecc *ecc, u32 *p);\n+unsigned int mtk_ecc_get_parity_bits(struct mtk_ecc *ecc);\n+\n+struct mtk_ecc *of_mtk_ecc_get(struct device_node *);\n+void mtk_ecc_release(struct mtk_ecc *);\n+\n+#endif\n"
  },
  {
    "path": "target/linux/mediatek/patches-5.15/120-12-spi-add-driver-for-MTK-SPI-NAND-Flash-Interface.patch",
    "content": "From 8170bafa8936e9fbfdce992932a63bd20eca3bc3 Mon Sep 17 00:00:00 2001\nFrom: Chuanhong Guo <gch981213@gmail.com>\nDate: Sat, 2 Apr 2022 10:16:11 +0800\nSubject: [PATCH v6 2/5] spi: add driver for MTK SPI NAND Flash Interface\n\nThis driver implements support for the SPI-NAND mode of MTK NAND Flash\nInterface as a SPI-MEM controller with pipelined ECC capability.\n\nSigned-off-by: Chuanhong Guo <gch981213@gmail.com>\nTested-by: Daniel Golle <daniel@makrotopia.org>\n---\nChange since v1:\n  fix CI warnings\n\nChanges since v2:\n use streamed DMA api to avoid an extra memory copy during read\n make ECC engine config a per-nand context\n take user-requested ECC strength into account\n\nChange since v3: none\nChanges since v4:\n fix missing OOB write\n print page format with dev_dbg\n replace uint*_t copied from vendor driver with u*\n\nChanges since v5:\n add missing nfi mode register configuration in probe\n fix an off-by-one bug in mtk_snand_mac_io\n\n drivers/spi/Kconfig        |   10 +\n drivers/spi/Makefile       |    1 +\n drivers/spi/spi-mtk-snfi.c | 1470 ++++++++++++++++++++++++++++++++++++\n 3 files changed, 1481 insertions(+)\n create mode 100644 drivers/spi/spi-mtk-snfi.c\n\n--- a/drivers/spi/Kconfig\n+++ b/drivers/spi/Kconfig\n@@ -530,6 +530,16 @@ config SPI_MTK_NOR\n \t  SPI interface as well as several SPI NOR specific instructions\n \t  via SPI MEM interface.\n \n+config SPI_MTK_SNFI\n+\ttristate \"MediaTek SPI NAND Flash Interface\"\n+\tdepends on ARCH_MEDIATEK || COMPILE_TEST\n+\tdepends on MTD_NAND_ECC_MEDIATEK\n+\thelp\n+\t  This enables support for SPI-NAND mode on the MediaTek NAND\n+\t  Flash Interface found on MediaTek ARM SoCs. This controller\n+\t  is implemented as a SPI-MEM controller with pipelined ECC\n+\t  capcability.\n+\n config SPI_NPCM_FIU\n \ttristate \"Nuvoton NPCM FLASH Interface Unit\"\n \tdepends on ARCH_NPCM || COMPILE_TEST\n--- a/drivers/spi/Makefile\n+++ b/drivers/spi/Makefile\n@@ -71,6 +71,7 @@ obj-$(CONFIG_SPI_MPC52xx)\t\t+= spi-mpc52x\n obj-$(CONFIG_SPI_MT65XX)                += spi-mt65xx.o\n obj-$(CONFIG_SPI_MT7621)\t\t+= spi-mt7621.o\n obj-$(CONFIG_SPI_MTK_NOR)\t\t+= spi-mtk-nor.o\n+obj-$(CONFIG_SPI_MTK_SNFI)\t\t+= spi-mtk-snfi.o\n obj-$(CONFIG_SPI_MXIC)\t\t\t+= spi-mxic.o\n obj-$(CONFIG_SPI_MXS)\t\t\t+= spi-mxs.o\n obj-$(CONFIG_SPI_NPCM_FIU)\t\t+= spi-npcm-fiu.o\n--- /dev/null\n+++ b/drivers/spi/spi-mtk-snfi.c\n@@ -0,0 +1,1470 @@\n+// SPDX-License-Identifier: GPL-2.0\n+//\n+// Driver for the SPI-NAND mode of Mediatek NAND Flash Interface\n+//\n+// Copyright (c) 2022 Chuanhong Guo <gch981213@gmail.com>\n+//\n+// This driver is based on the SPI-NAND mtd driver from Mediatek SDK:\n+//\n+// Copyright (C) 2020 MediaTek Inc.\n+// Author: Weijie Gao <weijie.gao@mediatek.com>\n+//\n+// This controller organize the page data as several interleaved sectors\n+// like the following: (sizeof(FDM + ECC) = snf->nfi_cfg.spare_size)\n+// +---------+------+------+---------+------+------+-----+\n+// | Sector1 | FDM1 | ECC1 | Sector2 | FDM2 | ECC2 | ... |\n+// +---------+------+------+---------+------+------+-----+\n+// With auto-format turned on, DMA only returns this part:\n+// +---------+---------+-----+\n+// | Sector1 | Sector2 | ... |\n+// +---------+---------+-----+\n+// The FDM data will be filled to the registers, and ECC parity data isn't\n+// accessible.\n+// With auto-format off, all ((Sector+FDM+ECC)*nsectors) will be read over DMA\n+// in it's original order shown in the first table. ECC can't be turned on when\n+// auto-format is off.\n+//\n+// However, Linux SPI-NAND driver expects the data returned as:\n+// +------+-----+\n+// | Page | OOB |\n+// +------+-----+\n+// where the page data is continuously stored instead of interleaved.\n+// So we assume all instructions matching the page_op template between ECC\n+// prepare_io_req and finish_io_req are for page cache r/w.\n+// Here's how this spi-mem driver operates when reading:\n+//  1. Always set snf->autofmt = true in prepare_io_req (even when ECC is off).\n+//  2. Perform page ops and let the controller fill the DMA bounce buffer with\n+//     de-interleaved sector data and set FDM registers.\n+//  3. Return the data as:\n+//     +---------+---------+-----+------+------+-----+\n+//     | Sector1 | Sector2 | ... | FDM1 | FDM2 | ... |\n+//     +---------+---------+-----+------+------+-----+\n+//  4. For other matching spi_mem ops outside a prepare/finish_io_req pair,\n+//     read the data with auto-format off into the bounce buffer and copy\n+//     needed data to the buffer specified in the request.\n+//\n+// Write requests operates in a similar manner.\n+// As a limitation of this strategy, we won't be able to access any ECC parity\n+// data at all in Linux.\n+//\n+// Here's the bad block mark situation on MTK chips:\n+// In older chips like mt7622, MTK uses the first FDM byte in the first sector\n+// as the bad block mark. After de-interleaving, this byte appears at [pagesize]\n+// in the returned data, which is the BBM position expected by kernel. However,\n+// the conventional bad block mark is the first byte of the OOB, which is part\n+// of the last sector data in the interleaved layout. Instead of fixing their\n+// hardware, MTK decided to address this inconsistency in software. On these\n+// later chips, the BootROM expects the following:\n+// 1. The [pagesize] byte on a nand page is used as BBM, which will appear at\n+//    (page_size - (nsectors - 1) * spare_size) in the DMA buffer.\n+// 2. The original byte stored at that position in the DMA buffer will be stored\n+//    as the first byte of the FDM section in the last sector.\n+// We can't disagree with the BootROM, so after de-interleaving, we need to\n+// perform the following swaps in read:\n+// 1. Store the BBM at [page_size - (nsectors - 1) * spare_size] to [page_size],\n+//    which is the expected BBM position by kernel.\n+// 2. Store the page data byte at [pagesize + (nsectors-1) * fdm] back to\n+//    [page_size - (nsectors - 1) * spare_size]\n+// Similarly, when writing, we need to perform swaps in the other direction.\n+\n+#include <linux/kernel.h>\n+#include <linux/module.h>\n+#include <linux/init.h>\n+#include <linux/device.h>\n+#include <linux/mutex.h>\n+#include <linux/clk.h>\n+#include <linux/interrupt.h>\n+#include <linux/dma-mapping.h>\n+#include <linux/iopoll.h>\n+#include <linux/of_platform.h>\n+#include <linux/mtd/nand-ecc-mtk.h>\n+#include <linux/spi/spi.h>\n+#include <linux/spi/spi-mem.h>\n+#include <linux/mtd/nand.h>\n+\n+// NFI registers\n+#define NFI_CNFG 0x000\n+#define CNFG_OP_MODE_S 12\n+#define CNFG_OP_MODE_CUST 6\n+#define CNFG_OP_MODE_PROGRAM 3\n+#define CNFG_AUTO_FMT_EN BIT(9)\n+#define CNFG_HW_ECC_EN BIT(8)\n+#define CNFG_DMA_BURST_EN BIT(2)\n+#define CNFG_READ_MODE BIT(1)\n+#define CNFG_DMA_MODE BIT(0)\n+\n+#define NFI_PAGEFMT 0x0004\n+#define NFI_SPARE_SIZE_LS_S 16\n+#define NFI_FDM_ECC_NUM_S 12\n+#define NFI_FDM_NUM_S 8\n+#define NFI_SPARE_SIZE_S 4\n+#define NFI_SEC_SEL_512 BIT(2)\n+#define NFI_PAGE_SIZE_S 0\n+#define NFI_PAGE_SIZE_512_2K 0\n+#define NFI_PAGE_SIZE_2K_4K 1\n+#define NFI_PAGE_SIZE_4K_8K 2\n+#define NFI_PAGE_SIZE_8K_16K 3\n+\n+#define NFI_CON 0x008\n+#define CON_SEC_NUM_S 12\n+#define CON_BWR BIT(9)\n+#define CON_BRD BIT(8)\n+#define CON_NFI_RST BIT(1)\n+#define CON_FIFO_FLUSH BIT(0)\n+\n+#define NFI_INTR_EN 0x010\n+#define NFI_INTR_STA 0x014\n+#define NFI_IRQ_INTR_EN BIT(31)\n+#define NFI_IRQ_CUS_READ BIT(8)\n+#define NFI_IRQ_CUS_PG BIT(7)\n+\n+#define NFI_CMD 0x020\n+#define NFI_CMD_DUMMY_READ 0x00\n+#define NFI_CMD_DUMMY_WRITE 0x80\n+\n+#define NFI_STRDATA 0x040\n+#define STR_DATA BIT(0)\n+\n+#define NFI_STA 0x060\n+#define NFI_NAND_FSM GENMASK(28, 24)\n+#define NFI_FSM GENMASK(19, 16)\n+#define READ_EMPTY BIT(12)\n+\n+#define NFI_FIFOSTA 0x064\n+#define FIFO_WR_REMAIN_S 8\n+#define FIFO_RD_REMAIN_S 0\n+\n+#define NFI_ADDRCNTR 0x070\n+#define SEC_CNTR GENMASK(16, 12)\n+#define SEC_CNTR_S 12\n+#define NFI_SEC_CNTR(val) (((val)&SEC_CNTR) >> SEC_CNTR_S)\n+\n+#define NFI_STRADDR 0x080\n+\n+#define NFI_BYTELEN 0x084\n+#define BUS_SEC_CNTR(val) (((val)&SEC_CNTR) >> SEC_CNTR_S)\n+\n+#define NFI_FDM0L 0x0a0\n+#define NFI_FDM0M 0x0a4\n+#define NFI_FDML(n) (NFI_FDM0L + (n)*8)\n+#define NFI_FDMM(n) (NFI_FDM0M + (n)*8)\n+\n+#define NFI_DEBUG_CON1 0x220\n+#define WBUF_EN BIT(2)\n+\n+#define NFI_MASTERSTA 0x224\n+#define MAS_ADDR GENMASK(11, 9)\n+#define MAS_RD GENMASK(8, 6)\n+#define MAS_WR GENMASK(5, 3)\n+#define MAS_RDDLY GENMASK(2, 0)\n+#define NFI_MASTERSTA_MASK_7622 (MAS_ADDR | MAS_RD | MAS_WR | MAS_RDDLY)\n+\n+// SNFI registers\n+#define SNF_MAC_CTL 0x500\n+#define MAC_XIO_SEL BIT(4)\n+#define SF_MAC_EN BIT(3)\n+#define SF_TRIG BIT(2)\n+#define WIP_READY BIT(1)\n+#define WIP BIT(0)\n+\n+#define SNF_MAC_OUTL 0x504\n+#define SNF_MAC_INL 0x508\n+\n+#define SNF_RD_CTL2 0x510\n+#define DATA_READ_DUMMY_S 8\n+#define DATA_READ_MAX_DUMMY 0xf\n+#define DATA_READ_CMD_S 0\n+\n+#define SNF_RD_CTL3 0x514\n+\n+#define SNF_PG_CTL1 0x524\n+#define PG_LOAD_CMD_S 8\n+\n+#define SNF_PG_CTL2 0x528\n+\n+#define SNF_MISC_CTL 0x538\n+#define SW_RST BIT(28)\n+#define FIFO_RD_LTC_S 25\n+#define PG_LOAD_X4_EN BIT(20)\n+#define DATA_READ_MODE_S 16\n+#define DATA_READ_MODE GENMASK(18, 16)\n+#define DATA_READ_MODE_X1 0\n+#define DATA_READ_MODE_X2 1\n+#define DATA_READ_MODE_X4 2\n+#define DATA_READ_MODE_DUAL 5\n+#define DATA_READ_MODE_QUAD 6\n+#define PG_LOAD_CUSTOM_EN BIT(7)\n+#define DATARD_CUSTOM_EN BIT(6)\n+#define CS_DESELECT_CYC_S 0\n+\n+#define SNF_MISC_CTL2 0x53c\n+#define PROGRAM_LOAD_BYTE_NUM_S 16\n+#define READ_DATA_BYTE_NUM_S 11\n+\n+#define SNF_DLY_CTL3 0x548\n+#define SFCK_SAM_DLY_S 0\n+\n+#define SNF_STA_CTL1 0x550\n+#define CUS_PG_DONE BIT(28)\n+#define CUS_READ_DONE BIT(27)\n+#define SPI_STATE_S 0\n+#define SPI_STATE GENMASK(3, 0)\n+\n+#define SNF_CFG 0x55c\n+#define SPI_MODE BIT(0)\n+\n+#define SNF_GPRAM 0x800\n+#define SNF_GPRAM_SIZE 0xa0\n+\n+#define SNFI_POLL_INTERVAL 1000000\n+\n+static const u8 mt7622_spare_sizes[] = { 16, 26, 27, 28 };\n+\n+struct mtk_snand_caps {\n+\tu16 sector_size;\n+\tu16 max_sectors;\n+\tu16 fdm_size;\n+\tu16 fdm_ecc_size;\n+\tu16 fifo_size;\n+\n+\tbool bbm_swap;\n+\tbool empty_page_check;\n+\tu32 mastersta_mask;\n+\n+\tconst u8 *spare_sizes;\n+\tu32 num_spare_size;\n+};\n+\n+static const struct mtk_snand_caps mt7622_snand_caps = {\n+\t.sector_size = 512,\n+\t.max_sectors = 8,\n+\t.fdm_size = 8,\n+\t.fdm_ecc_size = 1,\n+\t.fifo_size = 32,\n+\t.bbm_swap = false,\n+\t.empty_page_check = false,\n+\t.mastersta_mask = NFI_MASTERSTA_MASK_7622,\n+\t.spare_sizes = mt7622_spare_sizes,\n+\t.num_spare_size = ARRAY_SIZE(mt7622_spare_sizes)\n+};\n+\n+static const struct mtk_snand_caps mt7629_snand_caps = {\n+\t.sector_size = 512,\n+\t.max_sectors = 8,\n+\t.fdm_size = 8,\n+\t.fdm_ecc_size = 1,\n+\t.fifo_size = 32,\n+\t.bbm_swap = true,\n+\t.empty_page_check = false,\n+\t.mastersta_mask = NFI_MASTERSTA_MASK_7622,\n+\t.spare_sizes = mt7622_spare_sizes,\n+\t.num_spare_size = ARRAY_SIZE(mt7622_spare_sizes)\n+};\n+\n+struct mtk_snand_conf {\n+\tsize_t page_size;\n+\tsize_t oob_size;\n+\tu8 nsectors;\n+\tu8 spare_size;\n+};\n+\n+struct mtk_snand {\n+\tstruct spi_controller *ctlr;\n+\tstruct device *dev;\n+\tstruct clk *nfi_clk;\n+\tstruct clk *pad_clk;\n+\tvoid __iomem *nfi_base;\n+\tint irq;\n+\tstruct completion op_done;\n+\tconst struct mtk_snand_caps *caps;\n+\tstruct mtk_ecc_config *ecc_cfg;\n+\tstruct mtk_ecc *ecc;\n+\tstruct mtk_snand_conf nfi_cfg;\n+\tstruct mtk_ecc_stats ecc_stats;\n+\tstruct nand_ecc_engine ecc_eng;\n+\tbool autofmt;\n+\tu8 *buf;\n+\tsize_t buf_len;\n+};\n+\n+static struct mtk_snand *nand_to_mtk_snand(struct nand_device *nand)\n+{\n+\tstruct nand_ecc_engine *eng = nand->ecc.engine;\n+\n+\treturn container_of(eng, struct mtk_snand, ecc_eng);\n+}\n+\n+static inline int snand_prepare_bouncebuf(struct mtk_snand *snf, size_t size)\n+{\n+\tif (snf->buf_len >= size)\n+\t\treturn 0;\n+\tkfree(snf->buf);\n+\tsnf->buf = kmalloc(size, GFP_KERNEL);\n+\tif (!snf->buf)\n+\t\treturn -ENOMEM;\n+\tsnf->buf_len = size;\n+\tmemset(snf->buf, 0xff, snf->buf_len);\n+\treturn 0;\n+}\n+\n+static inline u32 nfi_read32(struct mtk_snand *snf, u32 reg)\n+{\n+\treturn readl(snf->nfi_base + reg);\n+}\n+\n+static inline void nfi_write32(struct mtk_snand *snf, u32 reg, u32 val)\n+{\n+\twritel(val, snf->nfi_base + reg);\n+}\n+\n+static inline void nfi_write16(struct mtk_snand *snf, u32 reg, u16 val)\n+{\n+\twritew(val, snf->nfi_base + reg);\n+}\n+\n+static inline void nfi_rmw32(struct mtk_snand *snf, u32 reg, u32 clr, u32 set)\n+{\n+\tu32 val;\n+\n+\tval = readl(snf->nfi_base + reg);\n+\tval &= ~clr;\n+\tval |= set;\n+\twritel(val, snf->nfi_base + reg);\n+}\n+\n+static void nfi_read_data(struct mtk_snand *snf, u32 reg, u8 *data, u32 len)\n+{\n+\tu32 i, val = 0, es = sizeof(u32);\n+\n+\tfor (i = reg; i < reg + len; i++) {\n+\t\tif (i == reg || i % es == 0)\n+\t\t\tval = nfi_read32(snf, i & ~(es - 1));\n+\n+\t\t*data++ = (u8)(val >> (8 * (i % es)));\n+\t}\n+}\n+\n+static int mtk_nfi_reset(struct mtk_snand *snf)\n+{\n+\tu32 val, fifo_mask;\n+\tint ret;\n+\n+\tnfi_write32(snf, NFI_CON, CON_FIFO_FLUSH | CON_NFI_RST);\n+\n+\tret = readw_poll_timeout(snf->nfi_base + NFI_MASTERSTA, val,\n+\t\t\t\t !(val & snf->caps->mastersta_mask), 0,\n+\t\t\t\t SNFI_POLL_INTERVAL);\n+\tif (ret) {\n+\t\tdev_err(snf->dev, \"NFI master is still busy after reset\\n\");\n+\t\treturn ret;\n+\t}\n+\n+\tret = readl_poll_timeout(snf->nfi_base + NFI_STA, val,\n+\t\t\t\t !(val & (NFI_FSM | NFI_NAND_FSM)), 0,\n+\t\t\t\t SNFI_POLL_INTERVAL);\n+\tif (ret) {\n+\t\tdev_err(snf->dev, \"Failed to reset NFI\\n\");\n+\t\treturn ret;\n+\t}\n+\n+\tfifo_mask = ((snf->caps->fifo_size - 1) << FIFO_RD_REMAIN_S) |\n+\t\t    ((snf->caps->fifo_size - 1) << FIFO_WR_REMAIN_S);\n+\tret = readw_poll_timeout(snf->nfi_base + NFI_FIFOSTA, val,\n+\t\t\t\t !(val & fifo_mask), 0, SNFI_POLL_INTERVAL);\n+\tif (ret) {\n+\t\tdev_err(snf->dev, \"NFI FIFOs are not empty\\n\");\n+\t\treturn ret;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int mtk_snand_mac_reset(struct mtk_snand *snf)\n+{\n+\tint ret;\n+\tu32 val;\n+\n+\tnfi_rmw32(snf, SNF_MISC_CTL, 0, SW_RST);\n+\n+\tret = readl_poll_timeout(snf->nfi_base + SNF_STA_CTL1, val,\n+\t\t\t\t !(val & SPI_STATE), 0, SNFI_POLL_INTERVAL);\n+\tif (ret)\n+\t\tdev_err(snf->dev, \"Failed to reset SNFI MAC\\n\");\n+\n+\tnfi_write32(snf, SNF_MISC_CTL,\n+\t\t    (2 << FIFO_RD_LTC_S) | (10 << CS_DESELECT_CYC_S));\n+\n+\treturn ret;\n+}\n+\n+static int mtk_snand_mac_trigger(struct mtk_snand *snf, u32 outlen, u32 inlen)\n+{\n+\tint ret;\n+\tu32 val;\n+\n+\tnfi_write32(snf, SNF_MAC_CTL, SF_MAC_EN);\n+\tnfi_write32(snf, SNF_MAC_OUTL, outlen);\n+\tnfi_write32(snf, SNF_MAC_INL, inlen);\n+\n+\tnfi_write32(snf, SNF_MAC_CTL, SF_MAC_EN | SF_TRIG);\n+\n+\tret = readl_poll_timeout(snf->nfi_base + SNF_MAC_CTL, val,\n+\t\t\t\t val & WIP_READY, 0, SNFI_POLL_INTERVAL);\n+\tif (ret) {\n+\t\tdev_err(snf->dev, \"Timed out waiting for WIP_READY\\n\");\n+\t\tgoto cleanup;\n+\t}\n+\n+\tret = readl_poll_timeout(snf->nfi_base + SNF_MAC_CTL, val, !(val & WIP),\n+\t\t\t\t 0, SNFI_POLL_INTERVAL);\n+\tif (ret)\n+\t\tdev_err(snf->dev, \"Timed out waiting for WIP cleared\\n\");\n+\n+cleanup:\n+\tnfi_write32(snf, SNF_MAC_CTL, 0);\n+\n+\treturn ret;\n+}\n+\n+static int mtk_snand_mac_io(struct mtk_snand *snf, const struct spi_mem_op *op)\n+{\n+\tu32 rx_len = 0;\n+\tu32 reg_offs = 0;\n+\tu32 val = 0;\n+\tconst u8 *tx_buf = NULL;\n+\tu8 *rx_buf = NULL;\n+\tint i, ret;\n+\tu8 b;\n+\n+\tif (op->data.dir == SPI_MEM_DATA_IN) {\n+\t\trx_len = op->data.nbytes;\n+\t\trx_buf = op->data.buf.in;\n+\t} else {\n+\t\ttx_buf = op->data.buf.out;\n+\t}\n+\n+\tmtk_snand_mac_reset(snf);\n+\n+\tfor (i = 0; i < op->cmd.nbytes; i++, reg_offs++) {\n+\t\tb = (op->cmd.opcode >> ((op->cmd.nbytes - i - 1) * 8)) & 0xff;\n+\t\tval |= b << (8 * (reg_offs % 4));\n+\t\tif (reg_offs % 4 == 3) {\n+\t\t\tnfi_write32(snf, SNF_GPRAM + reg_offs - 3, val);\n+\t\t\tval = 0;\n+\t\t}\n+\t}\n+\n+\tfor (i = 0; i < op->addr.nbytes; i++, reg_offs++) {\n+\t\tb = (op->addr.val >> ((op->addr.nbytes - i - 1) * 8)) & 0xff;\n+\t\tval |= b << (8 * (reg_offs % 4));\n+\t\tif (reg_offs % 4 == 3) {\n+\t\t\tnfi_write32(snf, SNF_GPRAM + reg_offs - 3, val);\n+\t\t\tval = 0;\n+\t\t}\n+\t}\n+\n+\tfor (i = 0; i < op->dummy.nbytes; i++, reg_offs++) {\n+\t\tif (reg_offs % 4 == 3) {\n+\t\t\tnfi_write32(snf, SNF_GPRAM + reg_offs - 3, val);\n+\t\t\tval = 0;\n+\t\t}\n+\t}\n+\n+\tif (op->data.dir == SPI_MEM_DATA_OUT) {\n+\t\tfor (i = 0; i < op->data.nbytes; i++, reg_offs++) {\n+\t\t\tval |= tx_buf[i] << (8 * (reg_offs % 4));\n+\t\t\tif (reg_offs % 4 == 3) {\n+\t\t\t\tnfi_write32(snf, SNF_GPRAM + reg_offs - 3, val);\n+\t\t\t\tval = 0;\n+\t\t\t}\n+\t\t}\n+\t}\n+\n+\tif (reg_offs % 4)\n+\t\tnfi_write32(snf, SNF_GPRAM + (reg_offs & ~3), val);\n+\n+\tfor (i = 0; i < reg_offs; i += 4)\n+\t\tdev_dbg(snf->dev, \"%d: %08X\", i,\n+\t\t\tnfi_read32(snf, SNF_GPRAM + i));\n+\n+\tdev_dbg(snf->dev, \"SNF TX: %u RX: %u\", reg_offs, rx_len);\n+\n+\tret = mtk_snand_mac_trigger(snf, reg_offs, rx_len);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tif (!rx_len)\n+\t\treturn 0;\n+\n+\tnfi_read_data(snf, SNF_GPRAM + reg_offs, rx_buf, rx_len);\n+\treturn 0;\n+}\n+\n+static int mtk_snand_setup_pagefmt(struct mtk_snand *snf, u32 page_size,\n+\t\t\t\t   u32 oob_size)\n+{\n+\tint spare_idx = -1;\n+\tu32 spare_size, spare_size_shift, pagesize_idx;\n+\tu32 sector_size_512;\n+\tu8 nsectors;\n+\tint i;\n+\n+\t// skip if it's already configured as required.\n+\tif (snf->nfi_cfg.page_size == page_size &&\n+\t    snf->nfi_cfg.oob_size == oob_size)\n+\t\treturn 0;\n+\n+\tnsectors = page_size / snf->caps->sector_size;\n+\tif (nsectors > snf->caps->max_sectors) {\n+\t\tdev_err(snf->dev, \"too many sectors required.\\n\");\n+\t\tgoto err;\n+\t}\n+\n+\tif (snf->caps->sector_size == 512) {\n+\t\tsector_size_512 = NFI_SEC_SEL_512;\n+\t\tspare_size_shift = NFI_SPARE_SIZE_S;\n+\t} else {\n+\t\tsector_size_512 = 0;\n+\t\tspare_size_shift = NFI_SPARE_SIZE_LS_S;\n+\t}\n+\n+\tswitch (page_size) {\n+\tcase SZ_512:\n+\t\tpagesize_idx = NFI_PAGE_SIZE_512_2K;\n+\t\tbreak;\n+\tcase SZ_2K:\n+\t\tif (snf->caps->sector_size == 512)\n+\t\t\tpagesize_idx = NFI_PAGE_SIZE_2K_4K;\n+\t\telse\n+\t\t\tpagesize_idx = NFI_PAGE_SIZE_512_2K;\n+\t\tbreak;\n+\tcase SZ_4K:\n+\t\tif (snf->caps->sector_size == 512)\n+\t\t\tpagesize_idx = NFI_PAGE_SIZE_4K_8K;\n+\t\telse\n+\t\t\tpagesize_idx = NFI_PAGE_SIZE_2K_4K;\n+\t\tbreak;\n+\tcase SZ_8K:\n+\t\tif (snf->caps->sector_size == 512)\n+\t\t\tpagesize_idx = NFI_PAGE_SIZE_8K_16K;\n+\t\telse\n+\t\t\tpagesize_idx = NFI_PAGE_SIZE_4K_8K;\n+\t\tbreak;\n+\tcase SZ_16K:\n+\t\tpagesize_idx = NFI_PAGE_SIZE_8K_16K;\n+\t\tbreak;\n+\tdefault:\n+\t\tdev_err(snf->dev, \"unsupported page size.\\n\");\n+\t\tgoto err;\n+\t}\n+\n+\tspare_size = oob_size / nsectors;\n+\t// If we're using the 1KB sector size, HW will automatically double the\n+\t// spare size. We should only use half of the value in this case.\n+\tif (snf->caps->sector_size == 1024)\n+\t\tspare_size /= 2;\n+\n+\tfor (i = snf->caps->num_spare_size - 1; i >= 0; i--) {\n+\t\tif (snf->caps->spare_sizes[i] <= spare_size) {\n+\t\t\tspare_size = snf->caps->spare_sizes[i];\n+\t\t\tif (snf->caps->sector_size == 1024)\n+\t\t\t\tspare_size *= 2;\n+\t\t\tspare_idx = i;\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\n+\tif (spare_idx < 0) {\n+\t\tdev_err(snf->dev, \"unsupported spare size: %u\\n\", spare_size);\n+\t\tgoto err;\n+\t}\n+\n+\tnfi_write32(snf, NFI_PAGEFMT,\n+\t\t    (snf->caps->fdm_ecc_size << NFI_FDM_ECC_NUM_S) |\n+\t\t\t    (snf->caps->fdm_size << NFI_FDM_NUM_S) |\n+\t\t\t    (spare_idx << spare_size_shift) |\n+\t\t\t    (pagesize_idx << NFI_PAGE_SIZE_S) |\n+\t\t\t    sector_size_512);\n+\n+\tsnf->nfi_cfg.page_size = page_size;\n+\tsnf->nfi_cfg.oob_size = oob_size;\n+\tsnf->nfi_cfg.nsectors = nsectors;\n+\tsnf->nfi_cfg.spare_size = spare_size;\n+\n+\tdev_dbg(snf->dev, \"page format: (%u + %u) * %u\\n\",\n+\t\tsnf->caps->sector_size, spare_size, nsectors);\n+\treturn snand_prepare_bouncebuf(snf, page_size + oob_size);\n+err:\n+\tdev_err(snf->dev, \"page size %u + %u is not supported\\n\", page_size,\n+\t\toob_size);\n+\treturn -EOPNOTSUPP;\n+}\n+\n+static int mtk_snand_ooblayout_ecc(struct mtd_info *mtd, int section,\n+\t\t\t\t   struct mtd_oob_region *oobecc)\n+{\n+\t// ECC area is not accessible\n+\treturn -ERANGE;\n+}\n+\n+static int mtk_snand_ooblayout_free(struct mtd_info *mtd, int section,\n+\t\t\t\t    struct mtd_oob_region *oobfree)\n+{\n+\tstruct nand_device *nand = mtd_to_nanddev(mtd);\n+\tstruct mtk_snand *ms = nand_to_mtk_snand(nand);\n+\n+\tif (section >= ms->nfi_cfg.nsectors)\n+\t\treturn -ERANGE;\n+\n+\toobfree->length = ms->caps->fdm_size - 1;\n+\toobfree->offset = section * ms->caps->fdm_size + 1;\n+\treturn 0;\n+}\n+\n+static const struct mtd_ooblayout_ops mtk_snand_ooblayout = {\n+\t.ecc = mtk_snand_ooblayout_ecc,\n+\t.free = mtk_snand_ooblayout_free,\n+};\n+\n+static int mtk_snand_ecc_init_ctx(struct nand_device *nand)\n+{\n+\tstruct mtk_snand *snf = nand_to_mtk_snand(nand);\n+\tstruct nand_ecc_props *conf = &nand->ecc.ctx.conf;\n+\tstruct nand_ecc_props *reqs = &nand->ecc.requirements;\n+\tstruct nand_ecc_props *user = &nand->ecc.user_conf;\n+\tstruct mtd_info *mtd = nanddev_to_mtd(nand);\n+\tint step_size = 0, strength = 0, desired_correction = 0, steps;\n+\tbool ecc_user = false;\n+\tint ret;\n+\tu32 parity_bits, max_ecc_bytes;\n+\tstruct mtk_ecc_config *ecc_cfg;\n+\n+\tret = mtk_snand_setup_pagefmt(snf, nand->memorg.pagesize,\n+\t\t\t\t      nand->memorg.oobsize);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tecc_cfg = kzalloc(sizeof(*ecc_cfg), GFP_KERNEL);\n+\tif (!ecc_cfg)\n+\t\treturn -ENOMEM;\n+\n+\tnand->ecc.ctx.priv = ecc_cfg;\n+\n+\tif (user->step_size && user->strength) {\n+\t\tstep_size = user->step_size;\n+\t\tstrength = user->strength;\n+\t\tecc_user = true;\n+\t} else if (reqs->step_size && reqs->strength) {\n+\t\tstep_size = reqs->step_size;\n+\t\tstrength = reqs->strength;\n+\t}\n+\n+\tif (step_size && strength) {\n+\t\tsteps = mtd->writesize / step_size;\n+\t\tdesired_correction = steps * strength;\n+\t\tstrength = desired_correction / snf->nfi_cfg.nsectors;\n+\t}\n+\n+\tecc_cfg->mode = ECC_NFI_MODE;\n+\tecc_cfg->sectors = snf->nfi_cfg.nsectors;\n+\tecc_cfg->len = snf->caps->sector_size + snf->caps->fdm_ecc_size;\n+\n+\t// calculate the max possible strength under current page format\n+\tparity_bits = mtk_ecc_get_parity_bits(snf->ecc);\n+\tmax_ecc_bytes = snf->nfi_cfg.spare_size - snf->caps->fdm_size;\n+\tecc_cfg->strength = max_ecc_bytes * 8 / parity_bits;\n+\tmtk_ecc_adjust_strength(snf->ecc, &ecc_cfg->strength);\n+\n+\t// if there's a user requested strength, find the minimum strength that\n+\t// meets the requirement. Otherwise use the maximum strength which is\n+\t// expected by BootROM.\n+\tif (ecc_user && strength) {\n+\t\tu32 s_next = ecc_cfg->strength - 1;\n+\n+\t\twhile (1) {\n+\t\t\tmtk_ecc_adjust_strength(snf->ecc, &s_next);\n+\t\t\tif (s_next >= ecc_cfg->strength)\n+\t\t\t\tbreak;\n+\t\t\tif (s_next < strength)\n+\t\t\t\tbreak;\n+\t\t\ts_next = ecc_cfg->strength - 1;\n+\t\t}\n+\t}\n+\n+\tmtd_set_ooblayout(mtd, &mtk_snand_ooblayout);\n+\n+\tconf->step_size = snf->caps->sector_size;\n+\tconf->strength = ecc_cfg->strength;\n+\n+\tif (ecc_cfg->strength < strength)\n+\t\tdev_warn(snf->dev, \"unable to fulfill ECC of %u bits.\\n\",\n+\t\t\t strength);\n+\tdev_info(snf->dev, \"ECC strength: %u bits per %u bytes\\n\",\n+\t\t ecc_cfg->strength, snf->caps->sector_size);\n+\n+\treturn 0;\n+}\n+\n+static void mtk_snand_ecc_cleanup_ctx(struct nand_device *nand)\n+{\n+\tstruct mtk_ecc_config *ecc_cfg = nand_to_ecc_ctx(nand);\n+\n+\tkfree(ecc_cfg);\n+}\n+\n+static int mtk_snand_ecc_prepare_io_req(struct nand_device *nand,\n+\t\t\t\t\tstruct nand_page_io_req *req)\n+{\n+\tstruct mtk_snand *snf = nand_to_mtk_snand(nand);\n+\tstruct mtk_ecc_config *ecc_cfg = nand_to_ecc_ctx(nand);\n+\tint ret;\n+\n+\tret = mtk_snand_setup_pagefmt(snf, nand->memorg.pagesize,\n+\t\t\t\t      nand->memorg.oobsize);\n+\tif (ret)\n+\t\treturn ret;\n+\tsnf->autofmt = true;\n+\tsnf->ecc_cfg = ecc_cfg;\n+\treturn 0;\n+}\n+\n+static int mtk_snand_ecc_finish_io_req(struct nand_device *nand,\n+\t\t\t\t       struct nand_page_io_req *req)\n+{\n+\tstruct mtk_snand *snf = nand_to_mtk_snand(nand);\n+\tstruct mtd_info *mtd = nanddev_to_mtd(nand);\n+\n+\tsnf->ecc_cfg = NULL;\n+\tsnf->autofmt = false;\n+\tif ((req->mode == MTD_OPS_RAW) || (req->type != NAND_PAGE_READ))\n+\t\treturn 0;\n+\n+\tif (snf->ecc_stats.failed)\n+\t\tmtd->ecc_stats.failed += snf->ecc_stats.failed;\n+\tmtd->ecc_stats.corrected += snf->ecc_stats.corrected;\n+\treturn snf->ecc_stats.failed ? -EBADMSG : snf->ecc_stats.bitflips;\n+}\n+\n+static struct nand_ecc_engine_ops mtk_snfi_ecc_engine_ops = {\n+\t.init_ctx = mtk_snand_ecc_init_ctx,\n+\t.cleanup_ctx = mtk_snand_ecc_cleanup_ctx,\n+\t.prepare_io_req = mtk_snand_ecc_prepare_io_req,\n+\t.finish_io_req = mtk_snand_ecc_finish_io_req,\n+};\n+\n+static void mtk_snand_read_fdm(struct mtk_snand *snf, u8 *buf)\n+{\n+\tu32 vall, valm;\n+\tu8 *oobptr = buf;\n+\tint i, j;\n+\n+\tfor (i = 0; i < snf->nfi_cfg.nsectors; i++) {\n+\t\tvall = nfi_read32(snf, NFI_FDML(i));\n+\t\tvalm = nfi_read32(snf, NFI_FDMM(i));\n+\n+\t\tfor (j = 0; j < snf->caps->fdm_size; j++)\n+\t\t\toobptr[j] = (j >= 4 ? valm : vall) >> ((j % 4) * 8);\n+\n+\t\toobptr += snf->caps->fdm_size;\n+\t}\n+}\n+\n+static void mtk_snand_write_fdm(struct mtk_snand *snf, const u8 *buf)\n+{\n+\tu32 fdm_size = snf->caps->fdm_size;\n+\tconst u8 *oobptr = buf;\n+\tu32 vall, valm;\n+\tint i, j;\n+\n+\tfor (i = 0; i < snf->nfi_cfg.nsectors; i++) {\n+\t\tvall = 0;\n+\t\tvalm = 0;\n+\n+\t\tfor (j = 0; j < 8; j++) {\n+\t\t\tif (j < 4)\n+\t\t\t\tvall |= (j < fdm_size ? oobptr[j] : 0xff)\n+\t\t\t\t\t<< (j * 8);\n+\t\t\telse\n+\t\t\t\tvalm |= (j < fdm_size ? oobptr[j] : 0xff)\n+\t\t\t\t\t<< ((j - 4) * 8);\n+\t\t}\n+\n+\t\tnfi_write32(snf, NFI_FDML(i), vall);\n+\t\tnfi_write32(snf, NFI_FDMM(i), valm);\n+\n+\t\toobptr += fdm_size;\n+\t}\n+}\n+\n+static void mtk_snand_bm_swap(struct mtk_snand *snf, u8 *buf)\n+{\n+\tu32 buf_bbm_pos, fdm_bbm_pos;\n+\n+\tif (!snf->caps->bbm_swap || snf->nfi_cfg.nsectors == 1)\n+\t\treturn;\n+\n+\t// swap [pagesize] byte on nand with the first fdm byte\n+\t// in the last sector.\n+\tbuf_bbm_pos = snf->nfi_cfg.page_size -\n+\t\t      (snf->nfi_cfg.nsectors - 1) * snf->nfi_cfg.spare_size;\n+\tfdm_bbm_pos = snf->nfi_cfg.page_size +\n+\t\t      (snf->nfi_cfg.nsectors - 1) * snf->caps->fdm_size;\n+\n+\tswap(snf->buf[fdm_bbm_pos], buf[buf_bbm_pos]);\n+}\n+\n+static void mtk_snand_fdm_bm_swap(struct mtk_snand *snf)\n+{\n+\tu32 fdm_bbm_pos1, fdm_bbm_pos2;\n+\n+\tif (!snf->caps->bbm_swap || snf->nfi_cfg.nsectors == 1)\n+\t\treturn;\n+\n+\t// swap the first fdm byte in the first and the last sector.\n+\tfdm_bbm_pos1 = snf->nfi_cfg.page_size;\n+\tfdm_bbm_pos2 = snf->nfi_cfg.page_size +\n+\t\t       (snf->nfi_cfg.nsectors - 1) * snf->caps->fdm_size;\n+\tswap(snf->buf[fdm_bbm_pos1], snf->buf[fdm_bbm_pos2]);\n+}\n+\n+static int mtk_snand_read_page_cache(struct mtk_snand *snf,\n+\t\t\t\t     const struct spi_mem_op *op)\n+{\n+\tu8 *buf = snf->buf;\n+\tu8 *buf_fdm = buf + snf->nfi_cfg.page_size;\n+\t// the address part to be sent by the controller\n+\tu32 op_addr = op->addr.val;\n+\t// where to start copying data from bounce buffer\n+\tu32 rd_offset = 0;\n+\tu32 dummy_clk = (op->dummy.nbytes * BITS_PER_BYTE / op->dummy.buswidth);\n+\tu32 op_mode = 0;\n+\tu32 dma_len = snf->buf_len;\n+\tint ret = 0;\n+\tu32 rd_mode, rd_bytes, val;\n+\tdma_addr_t buf_dma;\n+\n+\tif (snf->autofmt) {\n+\t\tu32 last_bit;\n+\t\tu32 mask;\n+\n+\t\tdma_len = snf->nfi_cfg.page_size;\n+\t\top_mode = CNFG_AUTO_FMT_EN;\n+\t\tif (op->data.ecc)\n+\t\t\top_mode |= CNFG_HW_ECC_EN;\n+\t\t// extract the plane bit:\n+\t\t// Find the highest bit set in (pagesize+oobsize).\n+\t\t// Bits higher than that in op->addr are kept and sent over SPI\n+\t\t// Lower bits are used as an offset for copying data from DMA\n+\t\t// bounce buffer.\n+\t\tlast_bit = fls(snf->nfi_cfg.page_size + snf->nfi_cfg.oob_size);\n+\t\tmask = (1 << last_bit) - 1;\n+\t\trd_offset = op_addr & mask;\n+\t\top_addr &= ~mask;\n+\n+\t\t// check if we can dma to the caller memory\n+\t\tif (rd_offset == 0 && op->data.nbytes >= snf->nfi_cfg.page_size)\n+\t\t\tbuf = op->data.buf.in;\n+\t}\n+\tmtk_snand_mac_reset(snf);\n+\tmtk_nfi_reset(snf);\n+\n+\t// command and dummy cycles\n+\tnfi_write32(snf, SNF_RD_CTL2,\n+\t\t    (dummy_clk << DATA_READ_DUMMY_S) |\n+\t\t\t    (op->cmd.opcode << DATA_READ_CMD_S));\n+\n+\t// read address\n+\tnfi_write32(snf, SNF_RD_CTL3, op_addr);\n+\n+\t// Set read op_mode\n+\tif (op->data.buswidth == 4)\n+\t\trd_mode = op->addr.buswidth == 4 ? DATA_READ_MODE_QUAD :\n+\t\t\t\t\t\t   DATA_READ_MODE_X4;\n+\telse if (op->data.buswidth == 2)\n+\t\trd_mode = op->addr.buswidth == 2 ? DATA_READ_MODE_DUAL :\n+\t\t\t\t\t\t   DATA_READ_MODE_X2;\n+\telse\n+\t\trd_mode = DATA_READ_MODE_X1;\n+\trd_mode <<= DATA_READ_MODE_S;\n+\tnfi_rmw32(snf, SNF_MISC_CTL, DATA_READ_MODE,\n+\t\t  rd_mode | DATARD_CUSTOM_EN);\n+\n+\t// Set bytes to read\n+\trd_bytes = (snf->nfi_cfg.spare_size + snf->caps->sector_size) *\n+\t\t   snf->nfi_cfg.nsectors;\n+\tnfi_write32(snf, SNF_MISC_CTL2,\n+\t\t    (rd_bytes << PROGRAM_LOAD_BYTE_NUM_S) | rd_bytes);\n+\n+\t// NFI read prepare\n+\tnfi_write16(snf, NFI_CNFG,\n+\t\t    (CNFG_OP_MODE_CUST << CNFG_OP_MODE_S) | CNFG_DMA_BURST_EN |\n+\t\t\t    CNFG_READ_MODE | CNFG_DMA_MODE | op_mode);\n+\n+\tnfi_write32(snf, NFI_CON, (snf->nfi_cfg.nsectors << CON_SEC_NUM_S));\n+\n+\tbuf_dma = dma_map_single(snf->dev, buf, dma_len, DMA_FROM_DEVICE);\n+\tif (dma_mapping_error(snf->dev, buf_dma)) {\n+\t\tdev_err(snf->dev, \"DMA mapping failed.\\n\");\n+\t\tgoto cleanup;\n+\t}\n+\tnfi_write32(snf, NFI_STRADDR, buf_dma);\n+\tif (op->data.ecc) {\n+\t\tsnf->ecc_cfg->op = ECC_DECODE;\n+\t\tret = mtk_ecc_enable(snf->ecc, snf->ecc_cfg);\n+\t\tif (ret)\n+\t\t\tgoto cleanup_dma;\n+\t}\n+\t// Prepare for custom read interrupt\n+\tnfi_write32(snf, NFI_INTR_EN, NFI_IRQ_INTR_EN | NFI_IRQ_CUS_READ);\n+\treinit_completion(&snf->op_done);\n+\n+\t// Trigger NFI into custom mode\n+\tnfi_write16(snf, NFI_CMD, NFI_CMD_DUMMY_READ);\n+\n+\t// Start DMA read\n+\tnfi_rmw32(snf, NFI_CON, 0, CON_BRD);\n+\tnfi_write16(snf, NFI_STRDATA, STR_DATA);\n+\n+\tif (!wait_for_completion_timeout(\n+\t\t    &snf->op_done, usecs_to_jiffies(SNFI_POLL_INTERVAL))) {\n+\t\tdev_err(snf->dev, \"DMA timed out for reading from cache.\\n\");\n+\t\tret = -ETIMEDOUT;\n+\t\tgoto cleanup;\n+\t}\n+\n+\t// Wait for BUS_SEC_CNTR returning expected value\n+\tret = readl_poll_timeout(snf->nfi_base + NFI_BYTELEN, val,\n+\t\t\t\t BUS_SEC_CNTR(val) >= snf->nfi_cfg.nsectors, 0,\n+\t\t\t\t SNFI_POLL_INTERVAL);\n+\tif (ret) {\n+\t\tdev_err(snf->dev, \"Timed out waiting for BUS_SEC_CNTR\\n\");\n+\t\tgoto cleanup2;\n+\t}\n+\n+\t// Wait for bus becoming idle\n+\tret = readl_poll_timeout(snf->nfi_base + NFI_MASTERSTA, val,\n+\t\t\t\t !(val & snf->caps->mastersta_mask), 0,\n+\t\t\t\t SNFI_POLL_INTERVAL);\n+\tif (ret) {\n+\t\tdev_err(snf->dev, \"Timed out waiting for bus becoming idle\\n\");\n+\t\tgoto cleanup2;\n+\t}\n+\n+\tif (op->data.ecc) {\n+\t\tret = mtk_ecc_wait_done(snf->ecc, ECC_DECODE);\n+\t\tif (ret) {\n+\t\t\tdev_err(snf->dev, \"wait ecc done timeout\\n\");\n+\t\t\tgoto cleanup2;\n+\t\t}\n+\t\t// save status before disabling ecc\n+\t\tmtk_ecc_get_stats(snf->ecc, &snf->ecc_stats,\n+\t\t\t\t  snf->nfi_cfg.nsectors);\n+\t}\n+\n+\tdma_unmap_single(snf->dev, buf_dma, dma_len, DMA_FROM_DEVICE);\n+\n+\tif (snf->autofmt) {\n+\t\tmtk_snand_read_fdm(snf, buf_fdm);\n+\t\tif (snf->caps->bbm_swap) {\n+\t\t\tmtk_snand_bm_swap(snf, buf);\n+\t\t\tmtk_snand_fdm_bm_swap(snf);\n+\t\t}\n+\t}\n+\n+\t// copy data back\n+\tif (nfi_read32(snf, NFI_STA) & READ_EMPTY) {\n+\t\tmemset(op->data.buf.in, 0xff, op->data.nbytes);\n+\t\tsnf->ecc_stats.bitflips = 0;\n+\t\tsnf->ecc_stats.failed = 0;\n+\t\tsnf->ecc_stats.corrected = 0;\n+\t} else {\n+\t\tif (buf == op->data.buf.in) {\n+\t\t\tu32 cap_len = snf->buf_len - snf->nfi_cfg.page_size;\n+\t\t\tu32 req_left = op->data.nbytes - snf->nfi_cfg.page_size;\n+\n+\t\t\tif (req_left)\n+\t\t\t\tmemcpy(op->data.buf.in + snf->nfi_cfg.page_size,\n+\t\t\t\t       buf_fdm,\n+\t\t\t\t       cap_len < req_left ? cap_len : req_left);\n+\t\t} else if (rd_offset < snf->buf_len) {\n+\t\t\tu32 cap_len = snf->buf_len - rd_offset;\n+\n+\t\t\tif (op->data.nbytes < cap_len)\n+\t\t\t\tcap_len = op->data.nbytes;\n+\t\t\tmemcpy(op->data.buf.in, snf->buf + rd_offset, cap_len);\n+\t\t}\n+\t}\n+cleanup2:\n+\tif (op->data.ecc)\n+\t\tmtk_ecc_disable(snf->ecc);\n+cleanup_dma:\n+\t// unmap dma only if any error happens. (otherwise it's done before\n+\t// data copying)\n+\tif (ret)\n+\t\tdma_unmap_single(snf->dev, buf_dma, dma_len, DMA_FROM_DEVICE);\n+cleanup:\n+\t// Stop read\n+\tnfi_write32(snf, NFI_CON, 0);\n+\tnfi_write16(snf, NFI_CNFG, 0);\n+\n+\t// Clear SNF done flag\n+\tnfi_rmw32(snf, SNF_STA_CTL1, 0, CUS_READ_DONE);\n+\tnfi_write32(snf, SNF_STA_CTL1, 0);\n+\n+\t// Disable interrupt\n+\tnfi_read32(snf, NFI_INTR_STA);\n+\tnfi_write32(snf, NFI_INTR_EN, 0);\n+\n+\tnfi_rmw32(snf, SNF_MISC_CTL, DATARD_CUSTOM_EN, 0);\n+\treturn ret;\n+}\n+\n+static int mtk_snand_write_page_cache(struct mtk_snand *snf,\n+\t\t\t\t      const struct spi_mem_op *op)\n+{\n+\t// the address part to be sent by the controller\n+\tu32 op_addr = op->addr.val;\n+\t// where to start copying data from bounce buffer\n+\tu32 wr_offset = 0;\n+\tu32 op_mode = 0;\n+\tint ret = 0;\n+\tu32 wr_mode = 0;\n+\tu32 dma_len = snf->buf_len;\n+\tu32 wr_bytes, val;\n+\tsize_t cap_len;\n+\tdma_addr_t buf_dma;\n+\n+\tif (snf->autofmt) {\n+\t\tu32 last_bit;\n+\t\tu32 mask;\n+\n+\t\tdma_len = snf->nfi_cfg.page_size;\n+\t\top_mode = CNFG_AUTO_FMT_EN;\n+\t\tif (op->data.ecc)\n+\t\t\top_mode |= CNFG_HW_ECC_EN;\n+\n+\t\tlast_bit = fls(snf->nfi_cfg.page_size + snf->nfi_cfg.oob_size);\n+\t\tmask = (1 << last_bit) - 1;\n+\t\twr_offset = op_addr & mask;\n+\t\top_addr &= ~mask;\n+\t}\n+\tmtk_snand_mac_reset(snf);\n+\tmtk_nfi_reset(snf);\n+\n+\tif (wr_offset)\n+\t\tmemset(snf->buf, 0xff, wr_offset);\n+\n+\tcap_len = snf->buf_len - wr_offset;\n+\tif (op->data.nbytes < cap_len)\n+\t\tcap_len = op->data.nbytes;\n+\tmemcpy(snf->buf + wr_offset, op->data.buf.out, cap_len);\n+\tif (snf->autofmt) {\n+\t\tif (snf->caps->bbm_swap) {\n+\t\t\tmtk_snand_fdm_bm_swap(snf);\n+\t\t\tmtk_snand_bm_swap(snf, snf->buf);\n+\t\t}\n+\t\tmtk_snand_write_fdm(snf, snf->buf + snf->nfi_cfg.page_size);\n+\t}\n+\n+\t// Command\n+\tnfi_write32(snf, SNF_PG_CTL1, (op->cmd.opcode << PG_LOAD_CMD_S));\n+\n+\t// write address\n+\tnfi_write32(snf, SNF_PG_CTL2, op_addr);\n+\n+\t// Set read op_mode\n+\tif (op->data.buswidth == 4)\n+\t\twr_mode = PG_LOAD_X4_EN;\n+\n+\tnfi_rmw32(snf, SNF_MISC_CTL, PG_LOAD_X4_EN,\n+\t\t  wr_mode | PG_LOAD_CUSTOM_EN);\n+\n+\t// Set bytes to write\n+\twr_bytes = (snf->nfi_cfg.spare_size + snf->caps->sector_size) *\n+\t\t   snf->nfi_cfg.nsectors;\n+\tnfi_write32(snf, SNF_MISC_CTL2,\n+\t\t    (wr_bytes << PROGRAM_LOAD_BYTE_NUM_S) | wr_bytes);\n+\n+\t// NFI write prepare\n+\tnfi_write16(snf, NFI_CNFG,\n+\t\t    (CNFG_OP_MODE_PROGRAM << CNFG_OP_MODE_S) |\n+\t\t\t    CNFG_DMA_BURST_EN | CNFG_DMA_MODE | op_mode);\n+\n+\tnfi_write32(snf, NFI_CON, (snf->nfi_cfg.nsectors << CON_SEC_NUM_S));\n+\tbuf_dma = dma_map_single(snf->dev, snf->buf, dma_len, DMA_TO_DEVICE);\n+\tif (dma_mapping_error(snf->dev, buf_dma)) {\n+\t\tdev_err(snf->dev, \"DMA mapping failed.\\n\");\n+\t\tgoto cleanup;\n+\t}\n+\tnfi_write32(snf, NFI_STRADDR, buf_dma);\n+\tif (op->data.ecc) {\n+\t\tsnf->ecc_cfg->op = ECC_ENCODE;\n+\t\tret = mtk_ecc_enable(snf->ecc, snf->ecc_cfg);\n+\t\tif (ret)\n+\t\t\tgoto cleanup_dma;\n+\t}\n+\t// Prepare for custom write interrupt\n+\tnfi_write32(snf, NFI_INTR_EN, NFI_IRQ_INTR_EN | NFI_IRQ_CUS_PG);\n+\treinit_completion(&snf->op_done);\n+\t;\n+\n+\t// Trigger NFI into custom mode\n+\tnfi_write16(snf, NFI_CMD, NFI_CMD_DUMMY_WRITE);\n+\n+\t// Start DMA write\n+\tnfi_rmw32(snf, NFI_CON, 0, CON_BWR);\n+\tnfi_write16(snf, NFI_STRDATA, STR_DATA);\n+\n+\tif (!wait_for_completion_timeout(\n+\t\t    &snf->op_done, usecs_to_jiffies(SNFI_POLL_INTERVAL))) {\n+\t\tdev_err(snf->dev, \"DMA timed out for program load.\\n\");\n+\t\tret = -ETIMEDOUT;\n+\t\tgoto cleanup_ecc;\n+\t}\n+\n+\t// Wait for NFI_SEC_CNTR returning expected value\n+\tret = readl_poll_timeout(snf->nfi_base + NFI_ADDRCNTR, val,\n+\t\t\t\t NFI_SEC_CNTR(val) >= snf->nfi_cfg.nsectors, 0,\n+\t\t\t\t SNFI_POLL_INTERVAL);\n+\tif (ret)\n+\t\tdev_err(snf->dev, \"Timed out waiting for NFI_SEC_CNTR\\n\");\n+\n+cleanup_ecc:\n+\tif (op->data.ecc)\n+\t\tmtk_ecc_disable(snf->ecc);\n+cleanup_dma:\n+\tdma_unmap_single(snf->dev, buf_dma, dma_len, DMA_TO_DEVICE);\n+cleanup:\n+\t// Stop write\n+\tnfi_write32(snf, NFI_CON, 0);\n+\tnfi_write16(snf, NFI_CNFG, 0);\n+\n+\t// Clear SNF done flag\n+\tnfi_rmw32(snf, SNF_STA_CTL1, 0, CUS_PG_DONE);\n+\tnfi_write32(snf, SNF_STA_CTL1, 0);\n+\n+\t// Disable interrupt\n+\tnfi_read32(snf, NFI_INTR_STA);\n+\tnfi_write32(snf, NFI_INTR_EN, 0);\n+\n+\tnfi_rmw32(snf, SNF_MISC_CTL, PG_LOAD_CUSTOM_EN, 0);\n+\n+\treturn ret;\n+}\n+\n+/**\n+ * mtk_snand_is_page_ops() - check if the op is a controller supported page op.\n+ * @op spi-mem op to check\n+ *\n+ * Check whether op can be executed with read_from_cache or program_load\n+ * mode in the controller.\n+ * This controller can execute typical Read From Cache and Program Load\n+ * instructions found on SPI-NAND with 2-byte address.\n+ * DTR and cmd buswidth & nbytes should be checked before calling this.\n+ *\n+ * Return: true if the op matches the instruction template\n+ */\n+static bool mtk_snand_is_page_ops(const struct spi_mem_op *op)\n+{\n+\tif (op->addr.nbytes != 2)\n+\t\treturn false;\n+\n+\tif (op->addr.buswidth != 1 && op->addr.buswidth != 2 &&\n+\t    op->addr.buswidth != 4)\n+\t\treturn false;\n+\n+\t// match read from page instructions\n+\tif (op->data.dir == SPI_MEM_DATA_IN) {\n+\t\t// check dummy cycle first\n+\t\tif (op->dummy.nbytes * BITS_PER_BYTE / op->dummy.buswidth >\n+\t\t    DATA_READ_MAX_DUMMY)\n+\t\t\treturn false;\n+\t\t// quad io / quad out\n+\t\tif ((op->addr.buswidth == 4 || op->addr.buswidth == 1) &&\n+\t\t    op->data.buswidth == 4)\n+\t\t\treturn true;\n+\n+\t\t// dual io / dual out\n+\t\tif ((op->addr.buswidth == 2 || op->addr.buswidth == 1) &&\n+\t\t    op->data.buswidth == 2)\n+\t\t\treturn true;\n+\n+\t\t// standard spi\n+\t\tif (op->addr.buswidth == 1 && op->data.buswidth == 1)\n+\t\t\treturn true;\n+\t} else if (op->data.dir == SPI_MEM_DATA_OUT) {\n+\t\t// check dummy cycle first\n+\t\tif (op->dummy.nbytes)\n+\t\t\treturn false;\n+\t\t// program load quad out\n+\t\tif (op->addr.buswidth == 1 && op->data.buswidth == 4)\n+\t\t\treturn true;\n+\t\t// standard spi\n+\t\tif (op->addr.buswidth == 1 && op->data.buswidth == 1)\n+\t\t\treturn true;\n+\t}\n+\treturn false;\n+}\n+\n+static bool mtk_snand_supports_op(struct spi_mem *mem,\n+\t\t\t\t  const struct spi_mem_op *op)\n+{\n+\tif (!spi_mem_default_supports_op(mem, op))\n+\t\treturn false;\n+\tif (op->cmd.nbytes != 1 || op->cmd.buswidth != 1)\n+\t\treturn false;\n+\tif (mtk_snand_is_page_ops(op))\n+\t\treturn true;\n+\treturn ((op->addr.nbytes == 0 || op->addr.buswidth == 1) &&\n+\t\t(op->dummy.nbytes == 0 || op->dummy.buswidth == 1) &&\n+\t\t(op->data.nbytes == 0 || op->data.buswidth == 1));\n+}\n+\n+static int mtk_snand_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op)\n+{\n+\tstruct mtk_snand *ms = spi_controller_get_devdata(mem->spi->master);\n+\t// page ops transfer size must be exactly ((sector_size + spare_size) *\n+\t// nsectors). Limit the op size if the caller requests more than that.\n+\t// exec_op will read more than needed and discard the leftover if the\n+\t// caller requests less data.\n+\tif (mtk_snand_is_page_ops(op)) {\n+\t\tsize_t l;\n+\t\t// skip adjust_op_size for page ops\n+\t\tif (ms->autofmt)\n+\t\t\treturn 0;\n+\t\tl = ms->caps->sector_size + ms->nfi_cfg.spare_size;\n+\t\tl *= ms->nfi_cfg.nsectors;\n+\t\tif (op->data.nbytes > l)\n+\t\t\top->data.nbytes = l;\n+\t} else {\n+\t\tsize_t hl = op->cmd.nbytes + op->addr.nbytes + op->dummy.nbytes;\n+\n+\t\tif (hl >= SNF_GPRAM_SIZE)\n+\t\t\treturn -EOPNOTSUPP;\n+\t\tif (op->data.nbytes > SNF_GPRAM_SIZE - hl)\n+\t\t\top->data.nbytes = SNF_GPRAM_SIZE - hl;\n+\t}\n+\treturn 0;\n+}\n+\n+static int mtk_snand_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)\n+{\n+\tstruct mtk_snand *ms = spi_controller_get_devdata(mem->spi->master);\n+\n+\tdev_dbg(ms->dev, \"OP %02x ADDR %08llX@%d:%u DATA %d:%u\", op->cmd.opcode,\n+\t\top->addr.val, op->addr.buswidth, op->addr.nbytes,\n+\t\top->data.buswidth, op->data.nbytes);\n+\tif (mtk_snand_is_page_ops(op)) {\n+\t\tif (op->data.dir == SPI_MEM_DATA_IN)\n+\t\t\treturn mtk_snand_read_page_cache(ms, op);\n+\t\telse\n+\t\t\treturn mtk_snand_write_page_cache(ms, op);\n+\t} else {\n+\t\treturn mtk_snand_mac_io(ms, op);\n+\t}\n+}\n+\n+static const struct spi_controller_mem_ops mtk_snand_mem_ops = {\n+\t.adjust_op_size = mtk_snand_adjust_op_size,\n+\t.supports_op = mtk_snand_supports_op,\n+\t.exec_op = mtk_snand_exec_op,\n+};\n+\n+static const struct spi_controller_mem_caps mtk_snand_mem_caps = {\n+\t.ecc = true,\n+};\n+\n+static irqreturn_t mtk_snand_irq(int irq, void *id)\n+{\n+\tstruct mtk_snand *snf = id;\n+\tu32 sta, ien;\n+\n+\tsta = nfi_read32(snf, NFI_INTR_STA);\n+\tien = nfi_read32(snf, NFI_INTR_EN);\n+\n+\tif (!(sta & ien))\n+\t\treturn IRQ_NONE;\n+\n+\tnfi_write32(snf, NFI_INTR_EN, 0);\n+\tcomplete(&snf->op_done);\n+\treturn IRQ_HANDLED;\n+}\n+\n+static const struct of_device_id mtk_snand_ids[] = {\n+\t{ .compatible = \"mediatek,mt7622-snand\", .data = &mt7622_snand_caps },\n+\t{ .compatible = \"mediatek,mt7629-snand\", .data = &mt7629_snand_caps },\n+\t{},\n+};\n+\n+MODULE_DEVICE_TABLE(of, mtk_snand_ids);\n+\n+static int mtk_snand_enable_clk(struct mtk_snand *ms)\n+{\n+\tint ret;\n+\n+\tret = clk_prepare_enable(ms->nfi_clk);\n+\tif (ret) {\n+\t\tdev_err(ms->dev, \"unable to enable nfi clk\\n\");\n+\t\treturn ret;\n+\t}\n+\tret = clk_prepare_enable(ms->pad_clk);\n+\tif (ret) {\n+\t\tdev_err(ms->dev, \"unable to enable pad clk\\n\");\n+\t\tgoto err1;\n+\t}\n+\treturn 0;\n+err1:\n+\tclk_disable_unprepare(ms->nfi_clk);\n+\treturn ret;\n+}\n+\n+static void mtk_snand_disable_clk(struct mtk_snand *ms)\n+{\n+\tclk_disable_unprepare(ms->pad_clk);\n+\tclk_disable_unprepare(ms->nfi_clk);\n+}\n+\n+static int mtk_snand_probe(struct platform_device *pdev)\n+{\n+\tstruct device_node *np = pdev->dev.of_node;\n+\tconst struct of_device_id *dev_id;\n+\tstruct spi_controller *ctlr;\n+\tstruct mtk_snand *ms;\n+\tint ret;\n+\n+\tdev_id = of_match_node(mtk_snand_ids, np);\n+\tif (!dev_id)\n+\t\treturn -EINVAL;\n+\n+\tctlr = devm_spi_alloc_master(&pdev->dev, sizeof(*ms));\n+\tif (!ctlr)\n+\t\treturn -ENOMEM;\n+\tplatform_set_drvdata(pdev, ctlr);\n+\n+\tms = spi_controller_get_devdata(ctlr);\n+\n+\tms->ctlr = ctlr;\n+\tms->caps = dev_id->data;\n+\n+\tms->ecc = of_mtk_ecc_get(np);\n+\tif (IS_ERR(ms->ecc))\n+\t\treturn PTR_ERR(ms->ecc);\n+\telse if (!ms->ecc)\n+\t\treturn -ENODEV;\n+\n+\tms->nfi_base = devm_platform_ioremap_resource(pdev, 0);\n+\tif (IS_ERR(ms->nfi_base)) {\n+\t\tret = PTR_ERR(ms->nfi_base);\n+\t\tgoto release_ecc;\n+\t}\n+\n+\tms->dev = &pdev->dev;\n+\n+\tms->nfi_clk = devm_clk_get(&pdev->dev, \"nfi_clk\");\n+\tif (IS_ERR(ms->nfi_clk)) {\n+\t\tret = PTR_ERR(ms->nfi_clk);\n+\t\tdev_err(&pdev->dev, \"unable to get nfi_clk, err = %d\\n\", ret);\n+\t\tgoto release_ecc;\n+\t}\n+\n+\tms->pad_clk = devm_clk_get(&pdev->dev, \"pad_clk\");\n+\tif (IS_ERR(ms->pad_clk)) {\n+\t\tret = PTR_ERR(ms->pad_clk);\n+\t\tdev_err(&pdev->dev, \"unable to get pad_clk, err = %d\\n\", ret);\n+\t\tgoto release_ecc;\n+\t}\n+\n+\tret = mtk_snand_enable_clk(ms);\n+\tif (ret)\n+\t\tgoto release_ecc;\n+\n+\tinit_completion(&ms->op_done);\n+\n+\tms->irq = platform_get_irq(pdev, 0);\n+\tif (ms->irq < 0) {\n+\t\tret = ms->irq;\n+\t\tgoto disable_clk;\n+\t}\n+\tret = devm_request_irq(ms->dev, ms->irq, mtk_snand_irq, 0x0,\n+\t\t\t       \"mtk-snand\", ms);\n+\tif (ret) {\n+\t\tdev_err(ms->dev, \"failed to request snfi irq\\n\");\n+\t\tgoto disable_clk;\n+\t}\n+\n+\tret = dma_set_mask(ms->dev, DMA_BIT_MASK(32));\n+\tif (ret) {\n+\t\tdev_err(ms->dev, \"failed to set dma mask\\n\");\n+\t\tgoto disable_clk;\n+\t}\n+\n+\t// switch to SNFI mode\n+\tnfi_write32(ms, SNF_CFG, SPI_MODE);\n+\n+\t// setup an initial page format for ops matching page_cache_op template\n+\t// before ECC is called.\n+\tret = mtk_snand_setup_pagefmt(ms, ms->caps->sector_size,\n+\t\t\t\t      ms->caps->spare_sizes[0]);\n+\tif (ret) {\n+\t\tdev_err(ms->dev, \"failed to set initial page format\\n\");\n+\t\tgoto disable_clk;\n+\t}\n+\n+\t// setup ECC engine\n+\tms->ecc_eng.dev = &pdev->dev;\n+\tms->ecc_eng.integration = NAND_ECC_ENGINE_INTEGRATION_PIPELINED;\n+\tms->ecc_eng.ops = &mtk_snfi_ecc_engine_ops;\n+\tms->ecc_eng.priv = ms;\n+\n+\tret = nand_ecc_register_on_host_hw_engine(&ms->ecc_eng);\n+\tif (ret) {\n+\t\tdev_err(&pdev->dev, \"failed to register ecc engine.\\n\");\n+\t\tgoto disable_clk;\n+\t}\n+\n+\tctlr->num_chipselect = 1;\n+\tctlr->mem_ops = &mtk_snand_mem_ops;\n+\tctlr->mem_caps = &mtk_snand_mem_caps;\n+\tctlr->bits_per_word_mask = SPI_BPW_MASK(8);\n+\tctlr->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD | SPI_TX_DUAL | SPI_TX_QUAD;\n+\tctlr->dev.of_node = pdev->dev.of_node;\n+\tret = spi_register_controller(ctlr);\n+\tif (ret) {\n+\t\tdev_err(&pdev->dev, \"spi_register_controller failed.\\n\");\n+\t\tgoto disable_clk;\n+\t}\n+\n+\treturn 0;\n+disable_clk:\n+\tmtk_snand_disable_clk(ms);\n+release_ecc:\n+\tmtk_ecc_release(ms->ecc);\n+\treturn ret;\n+}\n+\n+static int mtk_snand_remove(struct platform_device *pdev)\n+{\n+\tstruct spi_controller *ctlr = platform_get_drvdata(pdev);\n+\tstruct mtk_snand *ms = spi_controller_get_devdata(ctlr);\n+\n+\tspi_unregister_controller(ctlr);\n+\tmtk_snand_disable_clk(ms);\n+\tmtk_ecc_release(ms->ecc);\n+\tkfree(ms->buf);\n+\treturn 0;\n+}\n+\n+static struct platform_driver mtk_snand_driver = {\n+\t.probe = mtk_snand_probe,\n+\t.remove = mtk_snand_remove,\n+\t.driver = {\n+\t\t.name = \"mtk-snand\",\n+\t\t.of_match_table = mtk_snand_ids,\n+\t},\n+};\n+\n+module_platform_driver(mtk_snand_driver);\n+\n+MODULE_LICENSE(\"GPL\");\n+MODULE_AUTHOR(\"Chuanhong Guo <gch981213@gmail.com>\");\n+MODULE_DESCRIPTION(\"MeidaTek SPI-NAND Flash Controller Driver\");\n"
  },
  {
    "path": "target/linux/mediatek/patches-5.15/120-13-mtd-nand-mtk-ecc-also-parse-nand-ecc-engine-if-avail.patch",
    "content": "From 433b76fa0f3ca2865841abc21538dd8077ca3edd Mon Sep 17 00:00:00 2001\nFrom: Chuanhong Guo <gch981213@gmail.com>\nDate: Mon, 4 Apr 2022 00:05:38 +0800\nSubject: [PATCH 13/15] mtd: nand: mtk-ecc: also parse nand-ecc-engine if\n available\n\nThe recently added ECC engine support introduced a generic property\nnamed nand-ecc-engine for ecc engine phandle. This patch adds support\nfor this new property.\n\nSigned-off-by: Chuanhong Guo <gch981213@gmail.com>\n(cherry picked from commit a41f25feb6e47c1c4d8d3279ae990ccbd8dfab54)\n---\n drivers/mtd/nand/ecc-mtk.c | 5 ++++-\n 1 file changed, 4 insertions(+), 1 deletion(-)\n\n--- a/drivers/mtd/nand/ecc-mtk.c\n+++ b/drivers/mtd/nand/ecc-mtk.c\n@@ -279,7 +279,10 @@ struct mtk_ecc *of_mtk_ecc_get(struct de\n \tstruct mtk_ecc *ecc = NULL;\n \tstruct device_node *np;\n \n-\tnp = of_parse_phandle(of_node, \"ecc-engine\", 0);\n+\tnp = of_parse_phandle(of_node, \"nand-ecc-engine\", 0);\n+\t/* for backward compatibility */\n+\tif (!np)\n+\t\tnp = of_parse_phandle(of_node, \"ecc-engine\", 0);\n \tif (np) {\n \t\tecc = mtk_ecc_get(np);\n \t\tof_node_put(np);\n"
  },
  {
    "path": "target/linux/mediatek/patches-5.15/120-14-arm64-dts-mediatek-add-mtk-snfi-for-mt7622.patch",
    "content": "From 9ba7c246063ae43baf2e53ccc8c8b5f8d025aaaa Mon Sep 17 00:00:00 2001\nFrom: Chuanhong Guo <gch981213@gmail.com>\nDate: Sun, 3 Apr 2022 10:19:29 +0800\nSubject: [PATCH 15/15] arm64: dts: mediatek: add mtk-snfi for mt7622\n\nThis patch adds a device-tree node for the MTK SPI-NAND Flash Interface\nfor MT7622 device tree.\n\nSigned-off-by: Chuanhong Guo <gch981213@gmail.com>\n(cherry picked from commit 2e022641709011ef0843d0416b0f264b5fc217af)\n---\n arch/arm64/boot/dts/mediatek/mt7622.dtsi | 12 ++++++++++++\n 1 file changed, 12 insertions(+)\n\n--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi\n+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi\n@@ -552,6 +552,18 @@\n \t\tstatus = \"disabled\";\n \t};\n \n+\tsnfi: spi@1100d000 {\n+\t\tcompatible = \"mediatek,mt7622-snand\";\n+\t\treg = <0 0x1100d000 0 0x1000>;\n+\t\tinterrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;\n+\t\tclocks = <&pericfg CLK_PERI_NFI_PD>, <&pericfg CLK_PERI_SNFI_PD>;\n+\t\tclock-names = \"nfi_clk\", \"pad_clk\";\n+\t\tnand-ecc-engine = <&bch>;\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\tstatus = \"disabled\";\n+\t};\n+\n \tbch: ecc@1100e000 {\n \t\tcompatible = \"mediatek,mt7622-ecc\";\n \t\treg = <0 0x1100e000 0 0x1000>;\n"
  },
  {
    "path": "target/linux/mediatek/patches-5.15/121-hack-spi-nand-1b-bbm.patch",
    "content": "--- a/drivers/mtd/nand/spi/core.c\n+++ b/drivers/mtd/nand/spi/core.c\n@@ -714,7 +714,7 @@ static int spinand_mtd_write(struct mtd_\n static bool spinand_isbad(struct nand_device *nand, const struct nand_pos *pos)\n {\n \tstruct spinand_device *spinand = nand_to_spinand(nand);\n-\tu8 marker[2] = { };\n+\tu8 marker[1] = { };\n \tstruct nand_page_io_req req = {\n \t\t.pos = *pos,\n \t\t.ooblen = sizeof(marker),\n@@ -725,7 +725,7 @@ static bool spinand_isbad(struct nand_de\n \n \tspinand_select_target(spinand, pos->target);\n \tspinand_read_page(spinand, &req);\n-\tif (marker[0] != 0xff || marker[1] != 0xff)\n+\tif (marker[0] != 0xff)\n \t\treturn true;\n \n \treturn false;\n"
  },
  {
    "path": "target/linux/mediatek/patches-5.15/130-dts-mt7629-add-snand-support.patch",
    "content": "From c813fbe806257c574240770ef716fbee19f7dbfa Mon Sep 17 00:00:00 2001\nFrom: Xiangsheng Hou <xiangsheng.hou@mediatek.com>\nDate: Thu, 6 Jun 2019 16:29:04 +0800\nSubject: [PATCH] spi: spi-mem: Mediatek: Add SPI Nand support for MT7629\n\nSigned-off-by: Xiangsheng Hou <xiangsheng.hou@mediatek.com>\n---\n arch/arm/boot/dts/mt7629-rfb.dts | 45 ++++++++++++++++++++++++++++++++\n arch/arm/boot/dts/mt7629.dtsi    | 22 ++++++++++++++++\n 3 files changed, 79 insertions(+)\n\n--- a/arch/arm/boot/dts/mt7629.dtsi\n+++ b/arch/arm/boot/dts/mt7629.dtsi\n@@ -272,6 +272,27 @@\n \t\t\tstatus = \"disabled\";\n \t\t};\n \n+\t\tsnfi: spi@1100d000 {\n+\t\t\tcompatible = \"mediatek,mt7629-snand\";\n+\t\t\treg = <0x1100d000 0x1000>;\n+\t\t\tinterrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;\n+\t\t\tclocks = <&pericfg CLK_PERI_NFI_PD>, <&pericfg CLK_PERI_SNFI_PD>;\n+\t\t\tclock-names = \"nfi_clk\", \"pad_clk\";\n+\t\t\tnand-ecc-engine = <&bch>;\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tbch: ecc@1100e000 {\n+\t\t\tcompatible = \"mediatek,mt7622-ecc\";\n+\t\t\treg = <0x1100e000 0x1000>;\n+\t\t\tinterrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_LOW>;\n+\t\t\tclocks = <&pericfg CLK_PERI_NFIECC_PD>;\n+\t\t\tclock-names = \"nfiecc_clk\";\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n \t\tspi: spi@1100a000 {\n \t\t\tcompatible = \"mediatek,mt7629-spi\",\n \t\t\t\t     \"mediatek,mt7622-spi\";\n--- a/arch/arm/boot/dts/mt7629-rfb.dts\n+++ b/arch/arm/boot/dts/mt7629-rfb.dts\n@@ -254,6 +254,50 @@\n \t};\n };\n \n+&bch {\n+\tstatus = \"okay\";\n+};\n+\n+&snfi {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&serial_nand_pins>;\n+\tstatus = \"okay\";\n+\tflash@0 {\n+\t\tcompatible = \"spi-nand\";\n+\t\treg = <0>;\n+\t\tspi-tx-bus-width = <4>;\n+\t\tspi-rx-bus-width = <4>;\n+\t\tnand-ecc-engine = <&snfi>;\n+\n+\t\tpartitions {\n+\t\t\tcompatible = \"fixed-partitions\";\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <1>;\n+\n+\t\t\tpartition@0 {\n+\t\t\t\tlabel = \"Bootloader\";\n+\t\t\t\treg = <0x00000 0x0100000>;\n+\t\t\t\tread-only;\n+\t\t\t};\n+\n+\t\t\tpartition@100000 {\n+\t\t\t\tlabel = \"Config\";\n+\t\t\t\treg = <0x100000 0x0040000>;\n+\t\t\t};\n+\n+\t\t\tpartition@140000 {\n+\t\t\t\tlabel = \"factory\";\n+\t\t\t\treg = <0x140000 0x0080000>;\n+\t\t\t};\n+\n+\t\t\tpartition@1c0000 {\n+\t\t\t\tlabel = \"firmware\";\n+\t\t\t\treg = <0x1c0000 0x1000000>;\n+\t\t\t};\n+\t\t};\n+\t};\n+};\n+\n &spi {\n \tpinctrl-names = \"default\";\n \tpinctrl-0 = <&spi_pins>;\n"
  },
  {
    "path": "target/linux/mediatek/patches-5.15/131-dts-mt7622-add-snand-support.patch",
    "content": "--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts\n+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts\n@@ -539,6 +539,65 @@\n \tstatus = \"disabled\";\n };\n \n+&bch {\n+\tstatus = \"okay\";\n+};\n+\n+&snfi {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&serial_nand_pins>;\n+\tstatus = \"okay\";\n+\tflash@0 {\n+\t\tcompatible = \"spi-nand\";\n+\t\treg = <0>;\n+\t\tspi-tx-bus-width = <4>;\n+\t\tspi-rx-bus-width = <4>;\n+\t\tnand-ecc-engine = <&snfi>;\n+\n+\t\tpartitions {\n+\t\t\tcompatible = \"fixed-partitions\";\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <1>;\n+\n+\t\t\tpartition@0 {\n+\t\t\t\tlabel = \"Preloader\";\n+\t\t\t\treg = <0x00000 0x0080000>;\n+\t\t\t\tread-only;\n+\t\t\t};\n+\n+\t\t\tpartition@80000 {\n+\t\t\t\tlabel = \"ATF\";\n+\t\t\t\treg = <0x80000 0x0040000>;\n+\t\t\t};\n+\n+\t\t\tpartition@c0000 {\n+\t\t\t\tlabel = \"Bootloader\";\n+\t\t\t\treg = <0xc0000 0x0080000>;\n+\t\t\t};\n+\n+\t\t\tpartition@140000 {\n+\t\t\t\tlabel = \"Config\";\n+\t\t\t\treg = <0x140000 0x0080000>;\n+\t\t\t};\n+\n+\t\t\tpartition@1c0000 {\n+\t\t\t\tlabel = \"Factory\";\n+\t\t\t\treg = <0x1c0000 0x0100000>;\n+\t\t\t};\n+\n+\t\t\tpartition@200000 {\n+\t\t\t\tlabel = \"firmware\";\n+\t\t\t\treg = <0x2c0000 0x2000000>;\n+\t\t\t};\n+\n+\t\t\tpartition@2200000 {\n+\t\t\t\tlabel = \"User_data\";\n+\t\t\t\treg = <0x22c0000 0x4000000>;\n+\t\t\t};\n+\t\t};\n+\t};\n+};\n+\n &spi0 {\n \tpinctrl-names = \"default\";\n \tpinctrl-0 = <&spic0_pins>;\n"
  },
  {
    "path": "target/linux/mediatek/patches-5.15/140-dts-fix-wmac-support-for-mt7622-rfb1.patch",
    "content": "--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts\n+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts\n@@ -580,7 +580,7 @@\n \t\t\t\treg = <0x140000 0x0080000>;\n \t\t\t};\n \n-\t\t\tpartition@1c0000 {\n+\t\t\tfactory: partition@1c0000 {\n \t\t\t\tlabel = \"Factory\";\n \t\t\t\treg = <0x1c0000 0x0100000>;\n \t\t\t};\n@@ -641,5 +641,6 @@\n &wmac {\n \tpinctrl-names = \"default\";\n \tpinctrl-0 = <&wmac_pins>;\n+\tmediatek,mtd-eeprom = <&factory 0x0000>;\n \tstatus = \"okay\";\n };\n"
  },
  {
    "path": "target/linux/mediatek/patches-5.15/150-dts-mt7623-eip97-inside-secure-support.patch",
    "content": "--- a/arch/arm/boot/dts/mt7623.dtsi\n+++ b/arch/arm/boot/dts/mt7623.dtsi\n@@ -951,17 +951,14 @@\n \t};\n \n \tcrypto: crypto@1b240000 {\n-\t\tcompatible = \"mediatek,eip97-crypto\";\n+\t\tcompatible = \"inside-secure,safexcel-eip97\";\n \t\treg = <0 0x1b240000 0 0x20000>;\n \t\tinterrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>,\n \t\t\t     <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>,\n \t\t\t     <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>,\n-\t\t\t     <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>,\n-\t\t\t     <GIC_SPI 97 IRQ_TYPE_LEVEL_LOW>;\n+\t\t\t     <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;\n+\t\tinterrupt-names = \"ring0\", \"ring1\", \"ring2\", \"ring3\";\n \t\tclocks = <&ethsys CLK_ETHSYS_CRYPTO>;\n-\t\tclock-names = \"cryp\";\n-\t\tpower-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;\n-\t\tstatus = \"disabled\";\n \t};\n \n \tbdpsys: syscon@1c000000 {\n"
  },
  {
    "path": "target/linux/mediatek/patches-5.15/160-dts-mt7623-bpi-r2-earlycon.patch",
    "content": "--- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts\n+++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts\n@@ -19,7 +19,7 @@\n \n \tchosen {\n \t\tstdout-path = \"serial2:115200n8\";\n-\t\tbootargs = \"console=ttyS2,115200n8 console=tty1\";\n+\t\tbootargs = \"earlycon=uart8250,mmio32,0x11004000 console=ttyS2,115200n8 console=tty1\";\n \t};\n \n \tconnector {\n"
  },
  {
    "path": "target/linux/mediatek/patches-5.15/161-dts-mt7623-bpi-r2-mmc-device-order.patch",
    "content": "--- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts\n+++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts\n@@ -15,6 +15,8 @@\n \n \taliases {\n \t\tserial2 = &uart2;\n+\t\tmmc0 = &mmc0;\n+\t\tmmc1 = &mmc1;\n \t};\n \n \tchosen {\n"
  },
  {
    "path": "target/linux/mediatek/patches-5.15/162-dts-mt7623-bpi-r2-led-aliases.patch",
    "content": "--- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts\n+++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts\n@@ -17,6 +17,10 @@\n \t\tserial2 = &uart2;\n \t\tmmc0 = &mmc0;\n \t\tmmc1 = &mmc1;\n+\t\tled-boot = &led_system_green;\n+\t\tled-failsafe = &led_system_blue;\n+\t\tled-running = &led_system_green;\n+\t\tled-upgrade = &led_system_blue;\n \t};\n \n \tchosen {\n@@ -112,13 +116,13 @@\n \t\tpinctrl-names = \"default\";\n \t\tpinctrl-0 = <&led_pins_a>;\n \n-\t\tblue {\n+\t\tled_system_blue: blue {\n \t\t\tlabel = \"bpi-r2:pio:blue\";\n \t\t\tgpios = <&pio 240 GPIO_ACTIVE_LOW>;\n \t\t\tdefault-state = \"off\";\n \t\t};\n \n-\t\tgreen {\n+\t\tled_system_green: green {\n \t\t\tlabel = \"bpi-r2:pio:green\";\n \t\t\tgpios = <&pio 241 GPIO_ACTIVE_LOW>;\n \t\t\tdefault-state = \"off\";\n"
  },
  {
    "path": "target/linux/mediatek/patches-5.15/163-dts-mt7623-bpi-r2-ethernet-alias.patch",
    "content": "--- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts\n+++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts\n@@ -15,6 +15,7 @@\n \n \taliases {\n \t\tserial2 = &uart2;\n+\t\tethernet0 = &gmac0;\n \t\tmmc0 = &mmc0;\n \t\tmmc1 = &mmc1;\n \t\tled-boot = &led_system_green;\n"
  },
  {
    "path": "target/linux/mediatek/patches-5.15/173-arm-dts-mt7623-add-musb-device-nodes.patch",
    "content": "From 21d106f15262f5a2ef7531636e0703ee61c33c61 Mon Sep 17 00:00:00 2001\nFrom: Sungbo Eo <mans0n@gorani.run>\nDate: Sun, 8 Aug 2021 21:38:40 +0900\nSubject: [PATCH 2/2] arm: dts: mt7623: add musb device nodes\n\nMT7623 has an musb controller that is compatible with the one from MT2701.\n\nSigned-off-by: Sungbo Eo <mans0n@gorani.run>\n---\n arch/arm/boot/dts/mt7623.dtsi  | 34 ++++++++++++++++++++++++++++++++++\n arch/arm/boot/dts/mt7623a.dtsi |  4 ++++\n 2 files changed, 38 insertions(+)\n\n--- a/arch/arm/boot/dts/mt7623.dtsi\n+++ b/arch/arm/boot/dts/mt7623.dtsi\n@@ -585,6 +585,40 @@\n \t\tstatus = \"disabled\";\n \t};\n \n+\tusb0: usb@11200000 {\n+\t\tcompatible = \"mediatek,mt7623-musb\",\n+\t\t\t     \"mediatek,mtk-musb\";\n+\t\treg = <0 0x11200000 0 0x1000>;\n+\t\tinterrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_LOW>;\n+\t\tinterrupt-names = \"mc\";\n+\t\tphys = <&u2port2 PHY_TYPE_USB2>;\n+\t\tdr_mode = \"otg\";\n+\t\tclocks = <&pericfg CLK_PERI_USB0>,\n+\t\t\t <&pericfg CLK_PERI_USB0_MCU>,\n+\t\t\t <&pericfg CLK_PERI_USB_SLV>;\n+\t\tclock-names = \"main\",\"mcu\",\"univpll\";\n+\t\tpower-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;\n+\t\tstatus = \"disabled\";\n+\t};\n+\n+\tu2phy1: t-phy@11210000 {\n+\t\tcompatible = \"mediatek,mt7623-tphy\",\n+\t\t\t     \"mediatek,generic-tphy-v1\";\n+\t\treg = <0 0x11210000 0 0x0800>;\n+\t\t#address-cells = <2>;\n+\t\t#size-cells = <2>;\n+\t\tranges;\n+\t\tstatus = \"disabled\";\n+\n+\t\tu2port2: usb-phy@11210800 {\n+\t\t\treg = <0 0x11210800 0 0x0100>;\n+\t\t\tclocks = <&topckgen CLK_TOP_USB_PHY48M>;\n+\t\t\tclock-names = \"ref\";\n+\t\t\t#phy-cells = <1>;\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n \taudsys: clock-controller@11220000 {\n \t\tcompatible = \"mediatek,mt7623-audsys\",\n \t\t\t     \"mediatek,mt2701-audsys\",\n--- a/arch/arm/boot/dts/mt7623a.dtsi\n+++ b/arch/arm/boot/dts/mt7623a.dtsi\n@@ -35,6 +35,10 @@\n \tclock-names = \"ethif\";\n };\n \n+&usb0 {\n+\tpower-domains = <&scpsys MT7623A_POWER_DOMAIN_IFR_MSC>;\n+};\n+\n &usb1 {\n \tpower-domains = <&scpsys MT7623A_POWER_DOMAIN_HIF>;\n };\n"
  },
  {
    "path": "target/linux/mediatek/patches-5.15/180-dts-mt7622-bpi-r64-add-mt7531-irq.patch",
    "content": "--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts\n+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts\n@@ -160,6 +160,10 @@\n \t\tswitch@0 {\n \t\t\tcompatible = \"mediatek,mt7531\";\n \t\t\treg = <0>;\n+\t\t\tinterrupt-controller;\n+\t\t\t#interrupt-cells = <1>;\n+\t\t\tinterrupt-parent = <&pio>;\n+\t\t\tinterrupts = <53 IRQ_TYPE_LEVEL_HIGH>;\n \t\t\treset-gpios = <&pio 54 0>;\n \n \t\t\tports {\n"
  },
  {
    "path": "target/linux/mediatek/patches-5.15/190-arm64-dts-mediatek-mt7622-fix-GICv2-range.patch",
    "content": "From patchwork Tue Apr 26 19:51:36 2022\nContent-Type: text/plain; charset=\"utf-8\"\nMIME-Version: 1.0\nContent-Transfer-Encoding: 7bit\nX-Patchwork-Submitter: Daniel Golle <daniel@makrotopia.org>\nX-Patchwork-Id: 12827872\nReturn-Path: \n <linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org>\nX-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on\n\taws-us-west-2-korg-lkml-1.web.codeaurora.org\nReceived: from bombadil.infradead.org (bombadil.infradead.org\n [198.137.202.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby smtp.lore.kernel.org (Postfix) with ESMTPS id BACF3C433EF\n\tfor <linux-arm-kernel@archiver.kernel.org>;\n Tue, 26 Apr 2022 19:53:05 +0000 (UTC)\nDKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;\n\td=lists.infradead.org; s=bombadil.20210309; h=Sender:\n\tContent-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post:\n\tList-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID:Subject:Cc:To:\n\tFrom:Date:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From:\n\tResent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:\n\tList-Owner; bh=OWGSxvlKoyPWz6b629RNINucULo6oOdFssAIiJETWRg=; b=T0HEjee0FX3hlb\n\tx5jl7xLK5sKM0pkE2oRgwzthbFlNg8ST1j/2GkgcgT0S2Bi0vRfFxHeu/RKzS9RmiVnKJnPGL8ctg\n\tWoBLyO5i+NcmosGoy6MmoOjGTNhj/+3q3Z1jRLBSJ4ySSP22X77YeuJTmVzySPUllQhWvDhjMVCR9\n\tQBRmQdc6gCAg3IYGEbWwS2TG+UHveDCeZRWxMzrwI8UPadNCRFROwugmiQ3mdU41lHCTDpnlfuRJh\n\to1igLKfMBLz+D8rFYvDh7FfkcKkY6lNoswA2HKUun1MEzgoyQKmITPnG2maX/BvJJuj/B3ZJShh4k\n\tAZHmXoQxq1mrsm2FxfnQ==;\nReceived: from localhost ([::1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux))\n\tid 1njRE5-00G05D-9z; Tue, 26 Apr 2022 19:51:57 +0000\nReceived: from fudo.makrotopia.org ([2a07:2ec0:3002::71])\n by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux))\n id 1njRE1-00G03h-9H; Tue, 26 Apr 2022 19:51:55 +0000\nReceived: from local\n by fudo.makrotopia.org with esmtpsa (TLS1.3:TLS_AES_256_GCM_SHA384:256)\n (Exim 4.94.2) (envelope-from <daniel@makrotopia.org>)\n id 1njRDu-0006aF-4F; Tue, 26 Apr 2022 21:51:46 +0200\nDate: Tue, 26 Apr 2022 20:51:36 +0100\nFrom: Daniel Golle <daniel@makrotopia.org>\nTo: devicetree@vger.kernel.org, linux-mediatek@lists.infradead.org,\n linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org\nCc: Rob Herring <robh+dt@kernel.org>,\n Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,\n Matthias Brugger <matthias.bgg@gmail.com>\nSubject: [PATCH] arm64: dts: mediatek: mt7622: fix GICv2 range\nMessage-ID: <YmhNSLgp/yg8Vr1F@makrotopia.org>\nMIME-Version: 1.0\nContent-Disposition: inline\nX-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 \nX-CRM114-CacheID: sfid-20220426_125153_359242_EA3D452C \nX-CRM114-Status: GOOD (  12.45  )\nX-BeenThere: linux-arm-kernel@lists.infradead.org\nX-Mailman-Version: 2.1.34\nPrecedence: list\nList-Id: <linux-arm-kernel.lists.infradead.org>\nList-Unsubscribe: \n <http://lists.infradead.org/mailman/options/linux-arm-kernel>,\n <mailto:linux-arm-kernel-request@lists.infradead.org?subject=unsubscribe>\nList-Archive: <http://lists.infradead.org/pipermail/linux-arm-kernel/>\nList-Post: <mailto:linux-arm-kernel@lists.infradead.org>\nList-Help: <mailto:linux-arm-kernel-request@lists.infradead.org?subject=help>\nList-Subscribe: \n <http://lists.infradead.org/mailman/listinfo/linux-arm-kernel>,\n <mailto:linux-arm-kernel-request@lists.infradead.org?subject=subscribe>\nSender: \"linux-arm-kernel\" <linux-arm-kernel-bounces@lists.infradead.org>\nErrors-To: \n linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org\n\nWith the current range specified for the CPU interface there is an\nerror message at boot:\n\nGIC: GICv2 detected, but range too small and irqchip.gicv2_force_probe not set\n\nSetting irqchip.gicv2_force_probe=1 in bootargs results in:\n\nGIC: Aliased GICv2 at 0x0000000010320000, trying to find the canonical range over 128kB\nGIC: Adjusting CPU interface base to 0x000000001032f000\nGIC: Using split EOI/Deactivate mode\n\nUsing the adjusted CPU interface base and 8K size results in only the\nfinal line remaining and fully working system as well as /proc/interrupts\nshowing additional IPI3,4,5,6:\n\nIPI3:         0          0       CPU stop (for crash dump) interrupts\nIPI4:         0          0       Timer broadcast interrupts\nIPI5:         0          0       IRQ work interrupts\nIPI6:         0          0       CPU wake-up interrupts\n\nSigned-off-by: Daniel Golle <daniel@makrotopia.org>\n---\n arch/arm64/boot/dts/mediatek/mt7622.dtsi | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi\n+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi\n@@ -339,7 +339,7 @@\n \t\t#interrupt-cells = <3>;\n \t\tinterrupt-parent = <&gic>;\n \t\treg = <0 0x10310000 0 0x1000>,\n-\t\t      <0 0x10320000 0 0x1000>,\n+\t\t      <0 0x1032f000 0 0x2000>,\n \t\t      <0 0x10340000 0 0x2000>,\n \t\t      <0 0x10360000 0 0x2000>;\n \t};\n"
  },
  {
    "path": "target/linux/mediatek/patches-5.15/191-arm64-dts-mt7622-specify-the-L2-cache-topology.patch",
    "content": "From patchwork Thu Apr 28 22:57:55 2022\nContent-Type: text/plain; charset=\"utf-8\"\nMIME-Version: 1.0\nContent-Transfer-Encoding: 7bit\nX-Patchwork-Submitter: Rui Salvaterra <rsalvaterra@gmail.com>\nX-Patchwork-Id: 12831311\nReturn-Path: \n <linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org>\nX-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on\n\taws-us-west-2-korg-lkml-1.web.codeaurora.org\nReceived: from bombadil.infradead.org (bombadil.infradead.org\n [198.137.202.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby smtp.lore.kernel.org (Postfix) with ESMTPS id 49367C433EF\n\tfor <linux-arm-kernel@archiver.kernel.org>;\n Thu, 28 Apr 2022 22:59:15 +0000 (UTC)\nDKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;\n\td=lists.infradead.org; s=bombadil.20210309; h=Sender:\n\tContent-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post:\n\tList-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:Cc\n\t:To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From:\n\tResent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:\n\tList-Owner; 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Specify the shared L2 cache node in the device tree, in\norder to fix this.\n\nSigned-off-by: Rui Salvaterra <rsalvaterra@gmail.com>\n---\n arch/arm64/boot/dts/mediatek/mt7622.dtsi | 7 +++++++\n 1 file changed, 7 insertions(+)\n\n--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi\n+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi\n@@ -80,6 +80,7 @@\n \t\t\tenable-method = \"psci\";\n \t\t\tclock-frequency = <1300000000>;\n \t\t\tcci-control-port = <&cci_control2>;\n+\t\t\tnext-level-cache = <&L2>;\n \t\t};\n \n \t\tcpu1: cpu@1 {\n@@ -94,6 +95,12 @@\n \t\t\tenable-method = \"psci\";\n \t\t\tclock-frequency = <1300000000>;\n \t\t\tcci-control-port = <&cci_control2>;\n+\t\t\tnext-level-cache = <&L2>;\n+\t\t};\n+\n+\t\tL2: l2-cache {\n+\t\t\tcompatible = \"cache\";\n+\t\t\tcache-level = <2>;\n \t\t};\n \t};\n \n"
  },
  {
    "path": "target/linux/mediatek/patches-5.15/192-arm64-dts-mt7622-specify-the-number-of-DMA-requests.patch",
    "content": "From patchwork Fri Apr 29 08:42:25 2022\nContent-Type: text/plain; charset=\"utf-8\"\nMIME-Version: 1.0\nContent-Transfer-Encoding: 7bit\nX-Patchwork-Submitter: Rui Salvaterra <rsalvaterra@gmail.com>\nX-Patchwork-Id: 12831649\nReturn-Path: \n <linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org>\nX-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on\n\taws-us-west-2-korg-lkml-1.web.codeaurora.org\nReceived: from bombadil.infradead.org (bombadil.infradead.org\n [198.137.202.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby smtp.lore.kernel.org (Postfix) with ESMTPS id 386E2C433FE\n\tfor <linux-arm-kernel@archiver.kernel.org>;\n Fri, 29 Apr 2022 08:43:49 +0000 (UTC)\nDKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;\n\td=lists.infradead.org; s=bombadil.20210309; h=Sender:\n\tContent-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post:\n\tList-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:Cc\n\t:To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From:\n\tResent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:\n\tList-Owner; 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Make this value explicit, in order to avoid the following dmesg notification:\n\nmtk_hsdma 1b007000.dma-controller: Using 3 as missing dma-requests property\n\nSigned-off-by: Rui Salvaterra <rsalvaterra@gmail.com>\n---\n arch/arm64/boot/dts/mediatek/mt7622.dtsi | 1 +\n 1 file changed, 1 insertion(+)\n\n--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi\n+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi\n@@ -941,6 +941,7 @@\n \t\tclock-names = \"hsdma\";\n \t\tpower-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>;\n \t\t#dma-cells = <1>;\n+\t\tdma-requests = <3>;\n \t};\n \n \tpcie_mirror: pcie-mirror@10000400 {\n"
  },
  {
    "path": "target/linux/mediatek/patches-5.15/200-phy-phy-mtk-tphy-Add-hifsys-support.patch",
    "content": "From 28f9a5e2a3f5441ab5594669ed82da11e32277a9 Mon Sep 17 00:00:00 2001\nFrom: Kristian Evensen <kristian.evensen@gmail.com>\nDate: Mon, 30 Apr 2018 14:38:01 +0200\nSubject: [PATCH] phy: phy-mtk-tphy: Add hifsys-support\n\n---\n drivers/phy/mediatek/phy-mtk-tphy.c | 20 ++++++++++++++++++++\n 1 file changed, 20 insertions(+)\n\n--- a/drivers/phy/mediatek/phy-mtk-tphy.c\n+++ b/drivers/phy/mediatek/phy-mtk-tphy.c\n@@ -18,6 +18,8 @@\n #include <linux/phy/phy.h>\n #include <linux/platform_device.h>\n #include <linux/regmap.h>\n+#include <linux/mfd/syscon.h>\n+#include <linux/regmap.h>\n \n /* version V1 sub-banks offset base address */\n /* banks shared by multiple phys */\n@@ -311,6 +313,9 @@\n \n #define TPHY_CLKS_CNT\t2\n \n+#define HIF_SYSCFG1\t\t\t0x14\n+#define HIF_SYSCFG1_PHY2_MASK\t\t(0x3 << 20)\n+\n enum mtk_phy_version {\n \tMTK_PHY_V1 = 1,\n \tMTK_PHY_V2,\n@@ -377,6 +382,7 @@ struct mtk_tphy {\n \tvoid __iomem *sif_base;\t/* only shared sif */\n \tconst struct mtk_phy_pdata *pdata;\n \tstruct mtk_phy_instance **phys;\n+\tstruct regmap *hif;\n \tint nphys;\n \tint src_ref_clk; /* MHZ, reference clock for slew rate calibrate */\n \tint src_coef; /* coefficient for slew rate calibrate */\n@@ -730,6 +736,10 @@ static void pcie_phy_instance_init(struc\n \tif (tphy->pdata->version != MTK_PHY_V1)\n \t\treturn;\n \n+\tif (tphy->hif)\n+\t\tregmap_update_bits(tphy->hif, HIF_SYSCFG1,\n+\t\t\t\t   HIF_SYSCFG1_PHY2_MASK, 0);\n+\n \ttmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG0);\n \ttmp &= ~(P3A_RG_XTAL_EXT_PE1H | P3A_RG_XTAL_EXT_PE2H);\n \ttmp |= P3A_RG_XTAL_EXT_PE1H_VAL(0x2) | P3A_RG_XTAL_EXT_PE2H_VAL(0x2);\n@@ -1436,6 +1446,16 @@ static int mtk_tphy_probe(struct platfor\n \t\t\t\t\t &tphy->src_coef);\n \t}\n \n+\tif (of_find_property(np, \"mediatek,phy-switch\", NULL)) {\n+\t\ttphy->hif = syscon_regmap_lookup_by_phandle(np,\n+\t\t\t\t\t\t\t    \"mediatek,phy-switch\");\n+\t\tif (IS_ERR(tphy->hif)) {\n+\t\t\tdev_err(&pdev->dev,\n+\t\t\t\t\"missing \\\"mediatek,phy-switch\\\" phandle\\n\");\n+\t\t\treturn PTR_ERR(tphy->hif);\n+\t\t}\n+\t}\n+\n \tport = 0;\n \tfor_each_child_of_node(np, child_np) {\n \t\tstruct mtk_phy_instance *instance;\n"
  },
  {
    "path": "target/linux/mediatek/patches-5.15/330-snand-mtk-bmt-support.patch",
    "content": "--- a/drivers/mtd/nand/spi/core.c\n+++ b/drivers/mtd/nand/spi/core.c\n@@ -19,6 +19,7 @@\n #include <linux/string.h>\n #include <linux/spi/spi.h>\n #include <linux/spi/spi-mem.h>\n+#include <linux/mtd/mtk_bmt.h>\n \n static int spinand_read_reg_op(struct spinand_device *spinand, u8 reg, u8 *val)\n {\n@@ -1332,6 +1333,7 @@ static int spinand_probe(struct spi_mem\n \tif (ret)\n \t\treturn ret;\n \n+\tmtk_bmt_attach(mtd);\n \tret = mtd_device_register(mtd, NULL, 0);\n \tif (ret)\n \t\tgoto err_spinand_cleanup;\n@@ -1339,6 +1341,7 @@ static int spinand_probe(struct spi_mem\n \treturn 0;\n \n err_spinand_cleanup:\n+\tmtk_bmt_detach(mtd);\n \tspinand_cleanup(spinand);\n \n \treturn ret;\n@@ -1357,6 +1360,7 @@ static int spinand_remove(struct spi_mem\n \tif (ret)\n \t\treturn ret;\n \n+\tmtk_bmt_detach(mtd);\n \tspinand_cleanup(spinand);\n \n \treturn 0;\n"
  },
  {
    "path": "target/linux/mediatek/patches-5.15/331-mt7622-rfb1-enable-bmt.patch",
    "content": "--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts\n+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts\n@@ -553,6 +553,7 @@\n \t\tspi-tx-bus-width = <4>;\n \t\tspi-rx-bus-width = <4>;\n \t\tnand-ecc-engine = <&snfi>;\n+\t\tmediatek,bmt-v2;\n \n \t\tpartitions {\n \t\t\tcompatible = \"fixed-partitions\";\n"
  },
  {
    "path": "target/linux/mediatek/patches-5.15/340-mtd-spinand-Add-support-for-the-Fidelix-FM35X1GA.patch",
    "content": "From 5f49a5c9b16330e0df8f639310e4715dcad71947 Mon Sep 17 00:00:00 2001\nFrom: Davide Fioravanti <pantanastyle@gmail.com>\nDate: Fri, 8 Jan 2021 15:35:24 +0100\nSubject: [PATCH] mtd: spinand: Add support for the Fidelix FM35X1GA\n\nDatasheet: http://www.hobos.com.cn/upload/datasheet/DS35X1GAXXX_100_rev00.pdf\n\nSigned-off-by: Davide Fioravanti <pantanastyle@gmail.com>\n---\n drivers/mtd/nand/spi/Makefile  |  2 +-\n drivers/mtd/nand/spi/core.c    |  1 +\n drivers/mtd/nand/spi/fidelix.c | 76 ++++++++++++++++++++++++++++++++++\n include/linux/mtd/spinand.h    |  1 +\n 4 files changed, 79 insertions(+), 1 deletion(-)\n create mode 100644 drivers/mtd/nand/spi/fidelix.c\n\n--- a/drivers/mtd/nand/spi/Makefile\n+++ b/drivers/mtd/nand/spi/Makefile\n@@ -1,3 +1,3 @@\n # SPDX-License-Identifier: GPL-2.0\n-spinand-objs := core.o esmt.o gigadevice.o macronix.o micron.o paragon.o toshiba.o winbond.o xtx.o\n+spinand-objs := core.o esmt.o fidelix.o gigadevice.o macronix.o micron.o paragon.o toshiba.o winbond.o xtx.o\n obj-$(CONFIG_MTD_SPI_NAND) += spinand.o\n--- a/drivers/mtd/nand/spi/core.c\n+++ b/drivers/mtd/nand/spi/core.c\n@@ -929,6 +929,7 @@ static const struct nand_ops spinand_ops\n \n static const struct spinand_manufacturer *spinand_manufacturers[] = {\n \t&esmt_c8_spinand_manufacturer,\n+\t&fidelix_spinand_manufacturer,\n \t&gigadevice_spinand_manufacturer,\n \t&macronix_spinand_manufacturer,\n \t&micron_spinand_manufacturer,\n--- /dev/null\n+++ b/drivers/mtd/nand/spi/fidelix.c\n@@ -0,0 +1,76 @@\n+// SPDX-License-Identifier: GPL-2.0\n+/*\n+ * Copyright (c) 2020 Davide Fioravanti <pantanastyle@gmail.com>\n+ */\n+\n+#include <linux/device.h>\n+#include <linux/kernel.h>\n+#include <linux/mtd/spinand.h>\n+\n+#define SPINAND_MFR_FIDELIX\t\t0xE5\n+#define FIDELIX_ECCSR_MASK\t\t0x0F\n+\n+static SPINAND_OP_VARIANTS(read_cache_variants,\n+\t\tSPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),\n+\t\tSPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),\n+\t\tSPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));\n+\n+static SPINAND_OP_VARIANTS(write_cache_variants,\n+\t\tSPINAND_PROG_LOAD_X4(true, 0, NULL, 0),\n+\t\tSPINAND_PROG_LOAD(true, 0, NULL, 0));\n+\n+static SPINAND_OP_VARIANTS(update_cache_variants,\n+\t\tSPINAND_PROG_LOAD_X4(false, 0, NULL, 0),\n+\t\tSPINAND_PROG_LOAD(false, 0, NULL, 0));\n+\n+static int fm35x1ga_ooblayout_ecc(struct mtd_info *mtd, int section,\n+\t\t\t\t  struct mtd_oob_region *region)\n+{\n+\tif (section > 3)\n+\t\treturn -ERANGE;\n+\n+\tregion->offset = (16 * section) + 8;\n+\tregion->length = 8;\n+\n+\treturn 0;\n+}\n+\n+static int fm35x1ga_ooblayout_free(struct mtd_info *mtd, int section,\n+\t\t\t\t   struct mtd_oob_region *region)\n+{\n+\tif (section > 3)\n+\t\treturn -ERANGE;\n+\n+\tregion->offset = (16 * section) + 2;\n+\tregion->length = 6;\n+\n+\treturn 0;\n+}\n+\n+static const struct mtd_ooblayout_ops fm35x1ga_ooblayout = {\n+\t.ecc = fm35x1ga_ooblayout_ecc,\n+\t.free = fm35x1ga_ooblayout_free,\n+};\n+\n+static const struct spinand_info fidelix_spinand_table[] = {\n+\tSPINAND_INFO(\"FM35X1GA\",\n+\t\t     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x71),\n+\t\t     NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),\n+\t\t     NAND_ECCREQ(4, 512),\n+\t\t     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,\n+\t\t\t\t\t      &write_cache_variants,\n+\t\t\t\t\t      &update_cache_variants),\n+\t\t     SPINAND_HAS_QE_BIT,\n+\t\t     SPINAND_ECCINFO(&fm35x1ga_ooblayout, NULL)),\n+};\n+\n+static const struct spinand_manufacturer_ops fidelix_spinand_manuf_ops = {\n+};\n+\n+const struct spinand_manufacturer fidelix_spinand_manufacturer = {\n+\t.id = SPINAND_MFR_FIDELIX,\n+\t.name = \"Fidelix\",\n+\t.chips = fidelix_spinand_table,\n+\t.nchips = ARRAY_SIZE(fidelix_spinand_table),\n+\t.ops = &fidelix_spinand_manuf_ops,\n+};\n--- a/include/linux/mtd/spinand.h\n+++ b/include/linux/mtd/spinand.h\n@@ -261,6 +261,7 @@ struct spinand_manufacturer {\n \n /* SPI NAND manufacturers */\n extern const struct spinand_manufacturer esmt_c8_spinand_manufacturer;\n+extern const struct spinand_manufacturer fidelix_spinand_manufacturer;\n extern const struct spinand_manufacturer gigadevice_spinand_manufacturer;\n extern const struct spinand_manufacturer macronix_spinand_manufacturer;\n extern const struct spinand_manufacturer micron_spinand_manufacturer;\n"
  },
  {
    "path": "target/linux/mediatek/patches-5.15/400-crypto-add-eip97-inside-secure-support.patch",
    "content": "--- a/drivers/crypto/inside-secure/safexcel.c\n+++ b/drivers/crypto/inside-secure/safexcel.c\n@@ -600,6 +600,14 @@ static int safexcel_hw_init(struct safex\n \t\tval |= EIP197_MST_CTRL_TX_MAX_CMD(5);\n \t\twritel(val, EIP197_HIA_AIC(priv) + EIP197_HIA_MST_CTRL);\n \t}\n+\t/*\n+\t * Set maximum number of TX commands to 2^4 = 16 for EIP97 HW2.1/HW2.3\n+\t */\n+\telse {\n+\t\tval = 0;\n+\t\tval |= EIP97_MST_CTRL_TX_MAX_CMD(4);\n+\t\twritel(val, EIP197_HIA_AIC(priv) + EIP197_HIA_MST_CTRL);\n+\t}\n \n \t/* Configure wr/rd cache values */\n \twritel(EIP197_MST_CTRL_RD_CACHE(RD_CACHE_4BITS) |\n--- a/drivers/crypto/inside-secure/safexcel.h\n+++ b/drivers/crypto/inside-secure/safexcel.h\n@@ -315,6 +315,7 @@\n #define EIP197_MST_CTRL_RD_CACHE(n)\t\t(((n) & 0xf) << 0)\n #define EIP197_MST_CTRL_WD_CACHE(n)\t\t(((n) & 0xf) << 4)\n #define EIP197_MST_CTRL_TX_MAX_CMD(n)\t\t(((n) & 0xf) << 20)\n+#define EIP97_MST_CTRL_TX_MAX_CMD(n)\t\t(((n) & 0xf) << 4)\n #define EIP197_MST_CTRL_BYTE_SWAP\t\tBIT(24)\n #define EIP197_MST_CTRL_NO_BYTE_SWAP\t\tBIT(25)\n #define EIP197_MST_CTRL_BYTE_SWAP_BITS          GENMASK(25, 24)\n"
  },
  {
    "path": "target/linux/mediatek/patches-5.15/401-crypto-fix-eip97-cache-incoherent.patch",
    "content": "--- a/drivers/crypto/inside-secure/safexcel.h\n+++ b/drivers/crypto/inside-secure/safexcel.h\n@@ -737,6 +737,9 @@ enum safexcel_eip_version {\n /* Priority we use for advertising our algorithms */\n #define SAFEXCEL_CRA_PRIORITY\t\t300\n \n+/* System cache line size */\n+#define SYSTEM_CACHELINE_SIZE\t\t64\n+\n /* SM3 digest result for zero length message */\n #define EIP197_SM3_ZEROM_HASH\t\"\\x1A\\xB2\\x1D\\x83\\x55\\xCF\\xA1\\x7F\" \\\n \t\t\t\t\"\\x8E\\x61\\x19\\x48\\x31\\xE8\\x1A\\x8F\" \\\n--- a/drivers/crypto/inside-secure/safexcel_hash.c\n+++ b/drivers/crypto/inside-secure/safexcel_hash.c\n@@ -55,9 +55,9 @@ struct safexcel_ahash_req {\n \tu8 block_sz;    /* block size, only set once */\n \tu8 digest_sz;   /* output digest size, only set once */\n \t__le32 state[SHA3_512_BLOCK_SIZE /\n-\t\t     sizeof(__le32)] __aligned(sizeof(__le32));\n+\t\t     sizeof(__le32)] __aligned(SYSTEM_CACHELINE_SIZE);\n \n-\tu64 len;\n+\tu64 len __aligned(SYSTEM_CACHELINE_SIZE);\n \tu64 processed;\n \n \tu8 cache[HASH_CACHE_SIZE] __aligned(sizeof(u32));\n"
  },
  {
    "path": "target/linux/mediatek/patches-5.15/410-bt-mtk-serial-fix.patch",
    "content": "--- a/drivers/tty/serial/8250/8250.h\n+++ b/drivers/tty/serial/8250/8250.h\n@@ -83,6 +83,7 @@ struct serial8250_config {\n #define UART_CAP_MINI\tBIT(17)\t/* Mini UART on BCM283X family lacks:\n \t\t\t\t\t * STOP PARITY EPAR SPAR WLEN5 WLEN6\n \t\t\t\t\t */\n+#define UART_CAP_NMOD\t(1 << 18)\t/* UART doesn't do termios */\n \n #define UART_BUG_QUOT\tBIT(0)\t/* UART has buggy quot LSB */\n #define UART_BUG_TXEN\tBIT(1)\t/* UART has buggy TX IIR status */\n--- a/drivers/tty/serial/8250/8250_port.c\n+++ b/drivers/tty/serial/8250/8250_port.c\n@@ -288,7 +288,7 @@ static const struct serial8250_config ua\n \t\t.tx_loadsz\t= 16,\n \t\t.fcr\t\t= UART_FCR_ENABLE_FIFO |\n \t\t\t\t  UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,\n-\t\t.flags\t\t= UART_CAP_FIFO,\n+\t\t.flags\t\t= UART_CAP_FIFO | UART_CAP_NMOD,\n \t},\n \t[PORT_NPCM] = {\n \t\t.name\t\t= \"Nuvoton 16550\",\n@@ -2764,6 +2764,11 @@ serial8250_do_set_termios(struct uart_po\n \tunsigned long flags;\n \tunsigned int baud, quot, frac = 0;\n \n+\tif (up->capabilities & UART_CAP_NMOD) {\n+\t\ttermios->c_cflag = 0;\n+\t\treturn;\n+\t}\n+\n \tif (up->capabilities & UART_CAP_MINI) {\n \t\ttermios->c_cflag &= ~(CSTOPB | PARENB | PARODD | CMSPAR);\n \t\tif ((termios->c_cflag & CSIZE) == CS5 ||\n"
  },
  {
    "path": "target/linux/mediatek/patches-5.15/420-mtd-spi-nor-add-support-for-Winbond-W25Q512JV.patch",
    "content": "From: David Bauer <mail@david-bauer.net>\nTo: linux-mtd@lists.infradead.org\nSubject: [PATCH] mtd: spi-nor: add support for Winbond W25Q512JV\nDate: Sat, 13 Feb 2021 16:10:47 +0100\n\nThe Winbond W25Q512JV is a 512mb SPI-NOR chip. It supports 4K\nsectors as well as block protection and Dual-/Quad-read.\n\nTested on: Ubiquiti UniFi 6 LR\n\nSigned-off-by: David Bauer <mail@david-bauer.net>\n---\n drivers/mtd/spi-nor/winbond.c | 4 ++++\n 1 file changed, 4 insertions(+)\n\n--- a/drivers/mtd/spi-nor/winbond.c\n+++ b/drivers/mtd/spi-nor/winbond.c\n@@ -98,6 +98,10 @@ static const struct flash_info winbond_p\n \t\t\t     SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },\n \t{ \"w25q256jw\", INFO(0xef6019, 0, 64 * 1024, 512,\n \t\t\t     SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },\n+\t{ \"w25q512jv\", INFO(0xef4020, 0, 64 * 1024, 1024,\n+\t\t\t    SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_DUAL_READ |\n+\t\t\t    SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6 |\n+\t\t\t    SPI_NOR_HAS_LOCK | SPI_NOR_4BIT_BP) },\n \t{ \"w25m512jv\", INFO(0xef7119, 0, 64 * 1024, 1024,\n \t\t\t    SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_DUAL_READ) },\n \t{ \"w25q512jvq\", INFO(0xef4020, 0, 64 * 1024, 1024,\n"
  },
  {
    "path": "target/linux/mediatek/patches-5.15/500-gsw-rtl8367s-mt7622-support.patch",
    "content": "--- a/drivers/net/phy/Kconfig\n+++ b/drivers/net/phy/Kconfig\n@@ -366,6 +366,12 @@ config ROCKCHIP_PHY\n \thelp\n \t  Currently supports the integrated Ethernet PHY.\n \n+config RTL8367S_GSW\n+\ttristate \"rtl8367 Gigabit Switch support for mt7622\"\n+\tdepends on NET_VENDOR_MEDIATEK\n+\thelp\n+\t  This driver supports rtl8367s in mt7622\n+\n config SMSC_PHY\n \ttristate \"SMSC PHYs\"\n \thelp\n--- a/drivers/net/phy/Makefile\n+++ b/drivers/net/phy/Makefile\n@@ -93,6 +93,7 @@ obj-$(CONFIG_QSEMI_PHY)\t\t+= qsemi.o\n obj-$(CONFIG_REALTEK_PHY)\t+= realtek.o\n obj-$(CONFIG_RENESAS_PHY)\t+= uPD60620.o\n obj-$(CONFIG_ROCKCHIP_PHY)\t+= rockchip.o\n+obj-$(CONFIG_RTL8367S_GSW)\t+= rtk/\n obj-$(CONFIG_SMSC_PHY)\t\t+= smsc.o\n obj-$(CONFIG_STE10XP)\t\t+= ste10Xp.o\n obj-$(CONFIG_TERANETICS_PHY)\t+= teranetics.o\n"
  },
  {
    "path": "target/linux/mediatek/patches-5.15/510-net-mediatek-add-flow-offload-for-mt7623.patch",
    "content": "From 4823778b116c08e9c55dbc5b5042223289ea6a0c Mon Sep 17 00:00:00 2001\nFrom: Frank Wunderlich <frank-w@public-files.de>\nDate: Wed, 31 Mar 2021 15:34:37 +0200\nSubject: [PATCH] net: mediatek: add flow offload for mt7623\n\nmt7623 uses offload version 2 too\n\ntested on Bananapi-R2\n\nSigned-off-by: Frank Wunderlich <frank-w@public-files.de>\n---\n drivers/net/ethernet/mediatek/mtk_eth_soc.c | 1 +\n 1 file changed, 1 insertion(+)\n\n--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c\n+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c\n@@ -3364,6 +3364,7 @@ static const struct mtk_soc_data mt2701_\n \t.hw_features = MTK_HW_FEATURES,\n \t.required_clks = MT7623_CLKS_BITMAP,\n \t.required_pctl = true,\n+\t.offload_version = 2,\n };\n \n static const struct mtk_soc_data mt7621_data = {\n"
  },
  {
    "path": "target/linux/mediatek/patches-5.15/600-arm64-dts-mediatek-Split-PCIe-node-for-MT2712-and-MT.patch",
    "content": "From: Chuanjia Liu <chuanjia.liu@mediatek.com>\nDate: Mon, 23 Aug 2021 11:27:59 +0800\nSubject: [PATCH] arm64: dts: mediatek: Split PCIe node for MT2712 and MT7622\n\nThere are two independent PCIe controllers in MT2712 and MT7622\nplatform. Each of them should contain an independent MSI domain.\n\nIn old dts architecture, MSI domain will be inherited from the root\nbridge, and all of the devices will share the same MSI domain.\nHence that, the PCIe devices will not work properly if the irq number\nwhich required is more than 32.\n\nSplit the PCIe node for MT2712 and MT7622 platform to comply with\nthe hardware design and fix MSI issue.\n\nSigned-off-by: Chuanjia Liu <chuanjia.liu@mediatek.com>\nAcked-by: Ryder Lee <ryder.lee@mediatek.com>\nLink: https://lore.kernel.org/r/20210823032800.1660-6-chuanjia.liu@mediatek.com\nSigned-off-by: Matthias Brugger <matthias.bgg@gmail.com>\n---\n\n--- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi\n+++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi\n@@ -915,64 +915,67 @@\n \t\t};\n \t};\n \n-\tpcie: pcie@11700000 {\n+\tpcie1: pcie@112ff000 {\n \t\tcompatible = \"mediatek,mt2712-pcie\";\n \t\tdevice_type = \"pci\";\n-\t\treg = <0 0x11700000 0 0x1000>,\n-\t\t      <0 0x112ff000 0 0x1000>;\n-\t\treg-names = \"port0\", \"port1\";\n+\t\treg = <0 0x112ff000 0 0x1000>;\n+\t\treg-names = \"port1\";\n+\t\tlinux,pci-domain = <1>;\n \t\t#address-cells = <3>;\n \t\t#size-cells = <2>;\n-\t\tinterrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,\n-\t\t\t     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;\n-\t\tclocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>,\n-\t\t\t <&topckgen CLK_TOP_PE2_MAC_P1_SEL>,\n-\t\t\t <&pericfg CLK_PERI_PCIE0>,\n+\t\tinterrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;\n+\t\tinterrupt-names = \"pcie_irq\";\n+\t\tclocks = <&topckgen CLK_TOP_PE2_MAC_P1_SEL>,\n \t\t\t <&pericfg CLK_PERI_PCIE1>;\n-\t\tclock-names = \"sys_ck0\", \"sys_ck1\", \"ahb_ck0\", \"ahb_ck1\";\n-\t\tphys = <&u3port0 PHY_TYPE_PCIE>, <&u3port1 PHY_TYPE_PCIE>;\n-\t\tphy-names = \"pcie-phy0\", \"pcie-phy1\";\n+\t\tclock-names = \"sys_ck1\", \"ahb_ck1\";\n+\t\tphys = <&u3port1 PHY_TYPE_PCIE>;\n+\t\tphy-names = \"pcie-phy1\";\n \t\tbus-range = <0x00 0xff>;\n-\t\tranges = <0x82000000 0 0x20000000  0x0 0x20000000  0 0x10000000>;\n+\t\tranges = <0x82000000 0 0x11400000  0x0 0x11400000  0 0x300000>;\n+\t\tstatus = \"disabled\";\n \n-\t\tpcie0: pcie@0,0 {\n-\t\t\tdevice_type = \"pci\";\n-\t\t\tstatus = \"disabled\";\n-\t\t\treg = <0x0000 0 0 0 0>;\n-\t\t\t#address-cells = <3>;\n-\t\t\t#size-cells = <2>;\n+\t\t#interrupt-cells = <1>;\n+\t\tinterrupt-map-mask = <0 0 0 7>;\n+\t\tinterrupt-map = <0 0 0 1 &pcie_intc1 0>,\n+\t\t\t\t<0 0 0 2 &pcie_intc1 1>,\n+\t\t\t\t<0 0 0 3 &pcie_intc1 2>,\n+\t\t\t\t<0 0 0 4 &pcie_intc1 3>;\n+\t\tpcie_intc1: interrupt-controller {\n+\t\t\tinterrupt-controller;\n+\t\t\t#address-cells = <0>;\n \t\t\t#interrupt-cells = <1>;\n-\t\t\tranges;\n-\t\t\tinterrupt-map-mask = <0 0 0 7>;\n-\t\t\tinterrupt-map = <0 0 0 1 &pcie_intc0 0>,\n-\t\t\t\t\t<0 0 0 2 &pcie_intc0 1>,\n-\t\t\t\t\t<0 0 0 3 &pcie_intc0 2>,\n-\t\t\t\t\t<0 0 0 4 &pcie_intc0 3>;\n-\t\t\tpcie_intc0: interrupt-controller {\n-\t\t\t\tinterrupt-controller;\n-\t\t\t\t#address-cells = <0>;\n-\t\t\t\t#interrupt-cells = <1>;\n-\t\t\t};\n \t\t};\n+\t};\n+\n+\tpcie0: pcie@11700000 {\n+\t\tcompatible = \"mediatek,mt2712-pcie\";\n+\t\tdevice_type = \"pci\";\n+\t\treg = <0 0x11700000 0 0x1000>;\n+\t\treg-names = \"port0\";\n+\t\tlinux,pci-domain = <0>;\n+\t\t#address-cells = <3>;\n+\t\t#size-cells = <2>;\n+\t\tinterrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;\n+\t\tinterrupt-names = \"pcie_irq\";\n+\t\tclocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>,\n+\t\t\t <&pericfg CLK_PERI_PCIE0>;\n+\t\tclock-names = \"sys_ck0\", \"ahb_ck0\";\n+\t\tphys = <&u3port0 PHY_TYPE_PCIE>;\n+\t\tphy-names = \"pcie-phy0\";\n+\t\tbus-range = <0x00 0xff>;\n+\t\tranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;\n+\t\tstatus = \"disabled\";\n \n-\t\tpcie1: pcie@1,0 {\n-\t\t\tdevice_type = \"pci\";\n-\t\t\tstatus = \"disabled\";\n-\t\t\treg = <0x0800 0 0 0 0>;\n-\t\t\t#address-cells = <3>;\n-\t\t\t#size-cells = <2>;\n+\t\t#interrupt-cells = <1>;\n+\t\tinterrupt-map-mask = <0 0 0 7>;\n+\t\tinterrupt-map = <0 0 0 1 &pcie_intc0 0>,\n+\t\t\t\t<0 0 0 2 &pcie_intc0 1>,\n+\t\t\t\t<0 0 0 3 &pcie_intc0 2>,\n+\t\t\t\t<0 0 0 4 &pcie_intc0 3>;\n+\t\tpcie_intc0: interrupt-controller {\n+\t\t\tinterrupt-controller;\n+\t\t\t#address-cells = <0>;\n \t\t\t#interrupt-cells = <1>;\n-\t\t\tranges;\n-\t\t\tinterrupt-map-mask = <0 0 0 7>;\n-\t\t\tinterrupt-map = <0 0 0 1 &pcie_intc1 0>,\n-\t\t\t\t\t<0 0 0 2 &pcie_intc1 1>,\n-\t\t\t\t\t<0 0 0 3 &pcie_intc1 2>,\n-\t\t\t\t\t<0 0 0 4 &pcie_intc1 3>;\n-\t\t\tpcie_intc1: interrupt-controller {\n-\t\t\t\tinterrupt-controller;\n-\t\t\t\t#address-cells = <0>;\n-\t\t\t\t#interrupt-cells = <1>;\n-\t\t\t};\n \t\t};\n \t};\n \n--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts\n+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts\n@@ -302,18 +302,16 @@\n \t};\n };\n \n-&pcie {\n+&pcie0 {\n \tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&pcie0_pins>, <&pcie1_pins>;\n+\tpinctrl-0 = <&pcie0_pins>;\n \tstatus = \"okay\";\n+};\n \n-\tpcie@0,0 {\n-\t\tstatus = \"okay\";\n-\t};\n-\n-\tpcie@1,0 {\n-\t\tstatus = \"okay\";\n-\t};\n+&pcie1 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pcie1_pins>;\n+\tstatus = \"okay\";\n };\n \n &pio {\n--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts\n+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts\n@@ -232,18 +232,16 @@\n \t};\n };\n \n-&pcie {\n+&pcie0 {\n \tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&pcie0_pins>, <&pcie1_pins>;\n+\tpinctrl-0 = <&pcie0_pins>;\n \tstatus = \"okay\";\n+};\n \n-\tpcie@0,0 {\n-\t\tstatus = \"okay\";\n-\t};\n-\n-\tpcie@1,0 {\n-\t\tstatus = \"okay\";\n-\t};\n+&pcie1 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pcie1_pins>;\n+\tstatus = \"okay\";\n };\n \n &pio {\n--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi\n+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi\n@@ -808,75 +808,83 @@\n \t\t#reset-cells = <1>;\n \t};\n \n-\tpcie: pcie@1a140000 {\n+\tpciecfg: pciecfg@1a140000 {\n+\t\tcompatible = \"mediatek,generic-pciecfg\", \"syscon\";\n+\t\treg = <0 0x1a140000 0 0x1000>;\n+\t};\n+\n+\tpcie0: pcie@1a143000 {\n \t\tcompatible = \"mediatek,mt7622-pcie\";\n \t\tdevice_type = \"pci\";\n-\t\treg = <0 0x1a140000 0 0x1000>,\n-\t\t      <0 0x1a143000 0 0x1000>,\n-\t\t      <0 0x1a145000 0 0x1000>;\n-\t\treg-names = \"subsys\", \"port0\", \"port1\";\n+\t\treg = <0 0x1a143000 0 0x1000>;\n+\t\treg-names = \"port0\";\n+\t\tlinux,pci-domain = <0>;\n \t\t#address-cells = <3>;\n \t\t#size-cells = <2>;\n-\t\tinterrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>,\n-\t\t\t     <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;\n+\t\tinterrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>;\n+\t\tinterrupt-names = \"pcie_irq\";\n \t\tclocks = <&pciesys CLK_PCIE_P0_MAC_EN>,\n-\t\t\t <&pciesys CLK_PCIE_P1_MAC_EN>,\n-\t\t\t <&pciesys CLK_PCIE_P0_AHB_EN>,\n \t\t\t <&pciesys CLK_PCIE_P0_AHB_EN>,\n \t\t\t <&pciesys CLK_PCIE_P0_AUX_EN>,\n-\t\t\t <&pciesys CLK_PCIE_P1_AUX_EN>,\n \t\t\t <&pciesys CLK_PCIE_P0_AXI_EN>,\n-\t\t\t <&pciesys CLK_PCIE_P1_AXI_EN>,\n \t\t\t <&pciesys CLK_PCIE_P0_OBFF_EN>,\n-\t\t\t <&pciesys CLK_PCIE_P1_OBFF_EN>,\n-\t\t\t <&pciesys CLK_PCIE_P0_PIPE_EN>,\n-\t\t\t <&pciesys CLK_PCIE_P1_PIPE_EN>;\n-\t\tclock-names = \"sys_ck0\", \"sys_ck1\", \"ahb_ck0\", \"ahb_ck1\",\n-\t\t\t      \"aux_ck0\", \"aux_ck1\", \"axi_ck0\", \"axi_ck1\",\n-\t\t\t      \"obff_ck0\", \"obff_ck1\", \"pipe_ck0\", \"pipe_ck1\";\n+\t\t\t <&pciesys CLK_PCIE_P0_PIPE_EN>;\n+\t\tclock-names = \"sys_ck0\", \"ahb_ck0\", \"aux_ck0\",\n+\t\t\t      \"axi_ck0\", \"obff_ck0\", \"pipe_ck0\";\n+\n \t\tpower-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;\n \t\tbus-range = <0x00 0xff>;\n-\t\tranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;\n+\t\tranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x8000000>;\n \t\tstatus = \"disabled\";\n \n-\t\tpcie0: pcie@0,0 {\n-\t\t\treg = <0x0000 0 0 0 0>;\n-\t\t\t#address-cells = <3>;\n-\t\t\t#size-cells = <2>;\n+\t\t#interrupt-cells = <1>;\n+\t\tinterrupt-map-mask = <0 0 0 7>;\n+\t\tinterrupt-map = <0 0 0 1 &pcie_intc0 0>,\n+\t\t\t\t<0 0 0 2 &pcie_intc0 1>,\n+\t\t\t\t<0 0 0 3 &pcie_intc0 2>,\n+\t\t\t\t<0 0 0 4 &pcie_intc0 3>;\n+\t\tpcie_intc0: interrupt-controller {\n+\t\t\tinterrupt-controller;\n+\t\t\t#address-cells = <0>;\n \t\t\t#interrupt-cells = <1>;\n-\t\t\tranges;\n-\t\t\tstatus = \"disabled\";\n-\n-\t\t\tinterrupt-map-mask = <0 0 0 7>;\n-\t\t\tinterrupt-map = <0 0 0 1 &pcie_intc0 0>,\n-\t\t\t\t\t<0 0 0 2 &pcie_intc0 1>,\n-\t\t\t\t\t<0 0 0 3 &pcie_intc0 2>,\n-\t\t\t\t\t<0 0 0 4 &pcie_intc0 3>;\n-\t\t\tpcie_intc0: interrupt-controller {\n-\t\t\t\tinterrupt-controller;\n-\t\t\t\t#address-cells = <0>;\n-\t\t\t\t#interrupt-cells = <1>;\n-\t\t\t};\n \t\t};\n+\t};\n \n-\t\tpcie1: pcie@1,0 {\n-\t\t\treg = <0x0800 0 0 0 0>;\n-\t\t\t#address-cells = <3>;\n-\t\t\t#size-cells = <2>;\n-\t\t\t#interrupt-cells = <1>;\n-\t\t\tranges;\n-\t\t\tstatus = \"disabled\";\n+\tpcie1: pcie@1a145000 {\n+\t\tcompatible = \"mediatek,mt7622-pcie\";\n+\t\tdevice_type = \"pci\";\n+\t\treg = <0 0x1a145000 0 0x1000>;\n+\t\treg-names = \"port1\";\n+\t\tlinux,pci-domain = <1>;\n+\t\t#address-cells = <3>;\n+\t\t#size-cells = <2>;\n+\t\tinterrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;\n+\t\tinterrupt-names = \"pcie_irq\";\n+\t\tclocks = <&pciesys CLK_PCIE_P1_MAC_EN>,\n+\t\t\t /* designer has connect RC1 with p0_ahb clock */\n+\t\t\t <&pciesys CLK_PCIE_P0_AHB_EN>,\n+\t\t\t <&pciesys CLK_PCIE_P1_AUX_EN>,\n+\t\t\t <&pciesys CLK_PCIE_P1_AXI_EN>,\n+\t\t\t <&pciesys CLK_PCIE_P1_OBFF_EN>,\n+\t\t\t <&pciesys CLK_PCIE_P1_PIPE_EN>;\n+\t\tclock-names = \"sys_ck1\", \"ahb_ck1\", \"aux_ck1\",\n+\t\t\t      \"axi_ck1\", \"obff_ck1\", \"pipe_ck1\";\n+\n+\t\tpower-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;\n+\t\tbus-range = <0x00 0xff>;\n+\t\tranges = <0x82000000 0 0x28000000 0x0 0x28000000 0 0x8000000>;\n+\t\tstatus = \"disabled\";\n \n-\t\t\tinterrupt-map-mask = <0 0 0 7>;\n-\t\t\tinterrupt-map = <0 0 0 1 &pcie_intc1 0>,\n-\t\t\t\t\t<0 0 0 2 &pcie_intc1 1>,\n-\t\t\t\t\t<0 0 0 3 &pcie_intc1 2>,\n-\t\t\t\t\t<0 0 0 4 &pcie_intc1 3>;\n-\t\t\tpcie_intc1: interrupt-controller {\n-\t\t\t\tinterrupt-controller;\n-\t\t\t\t#address-cells = <0>;\n-\t\t\t\t#interrupt-cells = <1>;\n-\t\t\t};\n+\t\t#interrupt-cells = <1>;\n+\t\tinterrupt-map-mask = <0 0 0 7>;\n+\t\tinterrupt-map = <0 0 0 1 &pcie_intc1 0>,\n+\t\t\t\t<0 0 0 2 &pcie_intc1 1>,\n+\t\t\t\t<0 0 0 3 &pcie_intc1 2>,\n+\t\t\t\t<0 0 0 4 &pcie_intc1 3>;\n+\t\tpcie_intc1: interrupt-controller {\n+\t\t\tinterrupt-controller;\n+\t\t\t#address-cells = <0>;\n+\t\t\t#interrupt-cells = <1>;\n \t\t};\n \t};\n \n"
  },
  {
    "path": "target/linux/mediatek/patches-5.15/601-PCI-mediatek-Assert-PERST-for-100ms-for-power-and-cl.patch",
    "content": "From: qizhong cheng <qizhong.cheng@mediatek.com>\nDate: Mon, 27 Dec 2021 21:31:10 +0800\nSubject: [PATCH] PCI: mediatek: Assert PERST# for 100ms for power and clock to\n stabilize\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nDescribed in PCIe CEM specification sections 2.2 (PERST# Signal) and\n2.2.1 (Initial Power-Up (G3 to S0)). The deassertion of PERST# should\nbe delayed 100ms (TPVPERL) for the power and clock to become stable.\n\nLink: https://lore.kernel.org/r/20211227133110.14500-1-qizhong.cheng@mediatek.com\nSigned-off-by: qizhong cheng <qizhong.cheng@mediatek.com>\nSigned-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>\nAcked-by: Pali Rohár <pali@kernel.org>\n---\n\n--- a/drivers/pci/controller/pcie-mediatek.c\n+++ b/drivers/pci/controller/pcie-mediatek.c\n@@ -702,6 +702,13 @@ static int mtk_pcie_startup_port_v2(stru\n \t */\n \twritel(PCIE_LINKDOWN_RST_EN, port->base + PCIE_RST_CTRL);\n \n+\t/*\n+\t * Described in PCIe CEM specification sections 2.2 (PERST# Signal) and\n+\t * 2.2.1 (Initial Power-Up (G3 to S0)). The deassertion of PERST# should\n+\t * be delayed 100ms (TPVPERL) for the power and clock to become stable.\n+\t */\n+\tmsleep(100);\n+\n \t/* De-assert PHY, PE, PIPE, MAC and configuration reset\t*/\n \tval = readl(port->base + PCIE_RST_CTRL);\n \tval |= PCIE_PHY_RSTB | PCIE_PERSTB | PCIE_PIPE_SRSTB |\n"
  },
  {
    "path": "target/linux/mediatek/patches-5.15/602-arm64-dts-mediatek-add-mt7622-pcie-slot-node.patch",
    "content": "--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi\n+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi\n@@ -848,6 +848,12 @@\n \t\t\t#address-cells = <0>;\n \t\t\t#interrupt-cells = <1>;\n \t\t};\n+\n+\t\tslot0: pcie@0,0 {\n+\t\t\treg = <0x0000 0 0 0 0>;\n+\t\t\t#address-cells = <3>;\n+\t\t\t#size-cells = <2>;\n+\t\t};\n \t};\n \n \tpcie1: pcie@1a145000 {\n@@ -886,6 +892,12 @@\n \t\t\t#address-cells = <0>;\n \t\t\t#interrupt-cells = <1>;\n \t\t};\n+\n+\t\tslot1: pcie@1,0 {\n+\t\t\treg = <0x0800 0 0 0 0>;\n+\t\t\t#address-cells = <3>;\n+\t\t\t#size-cells = <2>;\n+\t\t};\n \t};\n \n \tsata: sata@1a200000 {\n"
  },
  {
    "path": "target/linux/mediatek/patches-5.15/603-ARM-dts-mediatek-Update-mt7629-PCIe-node.patch",
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0.8.0 (BSD) ) MR-646709E3 \nX-CRM114-CacheID: sfid-20200527_232901_719172_E5A99C62 \nX-CRM114-Status: GOOD (  11.61  )\nX-Spam-Score: -0.2 (/)\nX-Spam-Report: SpamAssassin version 3.4.4 on bombadil.infradead.org summary:\n Content analysis details:   (-0.2 points)\n pts rule name              description\n ---- ----------------------\n --------------------------------------------------\n -0.0 SPF_PASS               SPF: sender matches SPF record\n 0.0 SPF_HELO_NONE          SPF: HELO does not publish an SPF Record\n 0.0 MIME_BASE64_TEXT       RAW: Message text disguised using base64\n encoding\n -0.1 DKIM_VALID_AU          Message has a valid DKIM or DK signature from\n author's domain\n 0.1 DKIM_SIGNED            Message has a DKIM or DK signature,\n not necessarily\n valid\n -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature\n -0.1 DKIM_VALID_EF          Message has a valid DKIM or DK signature from\n envelope-from domain\n 0.0 UNPARSEABLE_RELAY      Informational: message has unparseable relay\n lines\nX-BeenThere: linux-mediatek@lists.infradead.org\nX-Mailman-Version: 2.1.29\nPrecedence: list\nList-Id: <linux-mediatek.lists.infradead.org>\nList-Unsubscribe: <http://lists.infradead.org/mailman/options/linux-mediatek>,\n <mailto:linux-mediatek-request@lists.infradead.org?subject=unsubscribe>\nList-Archive: <http://lists.infradead.org/pipermail/linux-mediatek/>\nList-Post: <mailto:linux-mediatek@lists.infradead.org>\nList-Help: <mailto:linux-mediatek-request@lists.infradead.org?subject=help>\nList-Subscribe: <http://lists.infradead.org/mailman/listinfo/linux-mediatek>,\n <mailto:linux-mediatek-request@lists.infradead.org?subject=subscribe>\nCc: devicetree@vger.kernel.org, lorenzo.pieralisi@arm.com,\n srv_heupstream@mediatek.com, \"chuanjia.liu\" <Chuanjia.Liu@mediatek.com>,\n linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,\n jianjun.wang@mediatek.com, linux-mediatek@lists.infradead.org,\n yong.wu@mediatek.com, bhelgaas@google.com,\n linux-arm-kernel@lists.infradead.org, amurray@thegoodpenguin.co.uk\nSender: \"Linux-mediatek\" <linux-mediatek-bounces@lists.infradead.org>\nErrors-To: \n linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org\n\nFrom: \"chuanjia.liu\" <Chuanjia.Liu@mediatek.com>\n\nRemove unused property and add pciecfg node.\n\nSigned-off-by: chuanjia.liu <Chuanjia.Liu@mediatek.com>\n---\n arch/arm/boot/dts/mt7629-rfb.dts |  3 ++-\n arch/arm/boot/dts/mt7629.dtsi    | 23 +++++++++++++----------\n 2 files changed, 15 insertions(+), 11 deletions(-)\n\n--- a/arch/arm/boot/dts/mt7629-rfb.dts\n+++ b/arch/arm/boot/dts/mt7629-rfb.dts\n@@ -149,9 +149,10 @@\n \t};\n };\n \n-&pcie {\n+&pcie1 {\n \tpinctrl-names = \"default\";\n \tpinctrl-0 = <&pcie_pins>;\n+\tstatus = \"okay\";\n };\n \n &pciephy1 {\n--- a/arch/arm/boot/dts/mt7629.dtsi\n+++ b/arch/arm/boot/dts/mt7629.dtsi\n@@ -382,16 +382,21 @@\n \t\t\t#reset-cells = <1>;\n \t\t};\n \n-\t\tpcie: pcie@1a140000 {\n+\t\tpciecfg: pciecfg@1a140000 {\n+\t\t\tcompatible = \"mediatek,mt7629-pciecfg\", \"syscon\";\n+\t\t\treg = <0x1a140000 0x1000>;\n+\t\t};\n+\n+\t\tpcie1: pcie@1a145000 {\n \t\t\tcompatible = \"mediatek,mt7629-pcie\";\n \t\t\tdevice_type = \"pci\";\n-\t\t\treg = <0x1a140000 0x1000>,\n-\t\t\t      <0x1a145000 0x1000>;\n-\t\t\treg-names = \"subsys\",\"port1\";\n+\t\t\treg = <0x1a145000 0x1000>;\n+\t\t\treg-names = \"port1\";\n+\t\t\tmediatek,pcie-cfg = <&pciecfg>;\n \t\t\t#address-cells = <3>;\n \t\t\t#size-cells = <2>;\n-\t\t\tinterrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_LOW>,\n-\t\t\t\t     <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;\n+\t\t\tinterrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;\n+\t\t\tinterrupt-names = \"pcie_irq\";\n \t\t\tclocks = <&pciesys CLK_PCIE_P1_MAC_EN>,\n \t\t\t\t <&pciesys CLK_PCIE_P0_AHB_EN>,\n \t\t\t\t <&pciesys CLK_PCIE_P1_AUX_EN>,\n@@ -412,21 +417,19 @@\n \t\t\tpower-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;\n \t\t\tbus-range = <0x00 0xff>;\n \t\t\tranges = <0x82000000 0 0x20000000 0x20000000 0 0x10000000>;\n+\t\t\tstatus = \"disabled\";\n \n-\t\t\tpcie1: pcie@1,0 {\n-\t\t\t\tdevice_type = \"pci\";\n+\t\t\tslot1: pcie@1,0 {\n \t\t\t\treg = <0x0800 0 0 0 0>;\n \t\t\t\t#address-cells = <3>;\n \t\t\t\t#size-cells = <2>;\n \t\t\t\t#interrupt-cells = <1>;\n \t\t\t\tranges;\n-\t\t\t\tnum-lanes = <1>;\n \t\t\t\tinterrupt-map-mask = <0 0 0 7>;\n \t\t\t\tinterrupt-map = <0 0 0 1 &pcie_intc1 0>,\n \t\t\t\t\t\t<0 0 0 2 &pcie_intc1 1>,\n \t\t\t\t\t\t<0 0 0 3 &pcie_intc1 2>,\n \t\t\t\t\t\t<0 0 0 4 &pcie_intc1 3>;\n-\n \t\t\t\tpcie_intc1: interrupt-controller {\n \t\t\t\t\tinterrupt-controller;\n \t\t\t\t\t#address-cells = <0>;\n"
  },
  {
    "path": "target/linux/mediatek/patches-5.15/610-pcie-mediatek-fix-clearing-interrupt-status.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nDate: Fri, 4 Sep 2020 18:33:27 +0200\nSubject: [PATCH] pcie-mediatek: fix clearing interrupt status\n\nClearing the status needs to happen after running the handler, otherwise\nwe will get an extra spurious interrupt after the cause has been cleared\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n\n--- a/drivers/pci/controller/pcie-mediatek.c\n+++ b/drivers/pci/controller/pcie-mediatek.c\n@@ -614,9 +614,9 @@ static void mtk_pcie_intr_handler(struct\n \tif (status & INTX_MASK) {\n \t\tfor_each_set_bit_from(bit, &status, PCI_NUM_INTX + INTX_SHIFT) {\n \t\t\t/* Clear the INTx */\n-\t\t\twritel(1 << bit, port->base + PCIE_INT_STATUS);\n \t\t\tgeneric_handle_domain_irq(port->irq_domain,\n \t\t\t\t\t\t  bit - INTX_SHIFT);\n+\t\t\twritel(1 << bit, port->base + PCIE_INT_STATUS);\n \t\t}\n \t}\n \n"
  },
  {
    "path": "target/linux/mediatek/patches-5.15/702-v5.17-net-mdio-add-helpers-to-extract-clause-45-regad-and-.patch",
    "content": "From c6af53f038aa32cec12e8a305ba07c7ef168f1b0 Mon Sep 17 00:00:00 2001\nFrom: \"Russell King (Oracle)\" <rmk+kernel@armlinux.org.uk>\nDate: Tue, 4 Jan 2022 12:07:00 +0000\nSubject: [PATCH 2/3] net: mdio: add helpers to extract clause 45 regad and\n devad fields\n\nAdd a couple of helpers and definitions to extract the clause 45 regad\nand devad fields from the regnum passed into MDIO drivers.\n\nTested-by: Daniel Golle <daniel@makrotopia.org>\nReviewed-by: Andrew Lunn <andrew@lunn.ch>\nSigned-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>\nSigned-off-by: Daniel Golle <daniel@makrotopia.org>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n include/linux/mdio.h | 12 ++++++++++++\n 1 file changed, 12 insertions(+)\n\n--- a/include/linux/mdio.h\n+++ b/include/linux/mdio.h\n@@ -7,6 +7,7 @@\n #define __LINUX_MDIO_H__\n \n #include <uapi/linux/mdio.h>\n+#include <linux/bitfield.h>\n #include <linux/mod_devicetable.h>\n \n /* Or MII_ADDR_C45 into regnum for read/write on mii_bus to enable the 21 bit\n@@ -14,6 +15,7 @@\n  */\n #define MII_ADDR_C45\t\t(1<<30)\n #define MII_DEVADDR_C45_SHIFT\t16\n+#define MII_DEVADDR_C45_MASK\tGENMASK(20, 16)\n #define MII_REGADDR_C45_MASK\tGENMASK(15, 0)\n \n struct gpio_desc;\n@@ -355,6 +357,16 @@ static inline u32 mdiobus_c45_addr(int d\n \treturn MII_ADDR_C45 | devad << MII_DEVADDR_C45_SHIFT | regnum;\n }\n \n+static inline u16 mdiobus_c45_regad(u32 regnum)\n+{\n+\treturn FIELD_GET(MII_REGADDR_C45_MASK, regnum);\n+}\n+\n+static inline u16 mdiobus_c45_devad(u32 regnum)\n+{\n+\treturn FIELD_GET(MII_DEVADDR_C45_MASK, regnum);\n+}\n+\n static inline int __mdiobus_c45_read(struct mii_bus *bus, int prtad, int devad,\n \t\t\t\t     u16 regnum)\n {\n"
  },
  {
    "path": "target/linux/mediatek/patches-5.15/703-v5.17-net-ethernet-mtk_eth_soc-implement-Clause-45-MDIO-ac.patch",
    "content": "From e2e7f6e29c99a1c6afc0e0aa4b9ea80302d28720 Mon Sep 17 00:00:00 2001\nFrom: Daniel Golle <daniel@makrotopia.org>\nDate: Tue, 4 Jan 2022 12:07:46 +0000\nSubject: [PATCH 3/3] net: ethernet: mtk_eth_soc: implement Clause 45 MDIO\n access\n\nImplement read and write access to IEEE 802.3 Clause 45 Ethernet\nphy registers while making use of new mdiobus_c45_regad and\nmdiobus_c45_devad helpers.\n\nTested on the Ubiquiti UniFi 6 LR access point featuring\nMediaTek MT7622BV WiSoC with Aquantia AQR112C.\n\nSigned-off-by: Daniel Golle <daniel@makrotopia.org>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/ethernet/mediatek/mtk_eth_soc.c | 70 +++++++++++++++++----\n drivers/net/ethernet/mediatek/mtk_eth_soc.h |  3 +\n 2 files changed, 60 insertions(+), 13 deletions(-)\n\n--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c\n+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c\n@@ -106,13 +106,35 @@ static int _mtk_mdio_write(struct mtk_et\n \tif (ret < 0)\n \t\treturn ret;\n \n-\tmtk_w32(eth, PHY_IAC_ACCESS |\n-\t\t     PHY_IAC_START_C22 |\n-\t\t     PHY_IAC_CMD_WRITE |\n-\t\t     PHY_IAC_REG(phy_reg) |\n-\t\t     PHY_IAC_ADDR(phy_addr) |\n-\t\t     PHY_IAC_DATA(write_data),\n-\t\tMTK_PHY_IAC);\n+\tif (phy_reg & MII_ADDR_C45) {\n+\t\tmtk_w32(eth, PHY_IAC_ACCESS |\n+\t\t\t     PHY_IAC_START_C45 |\n+\t\t\t     PHY_IAC_CMD_C45_ADDR |\n+\t\t\t     PHY_IAC_REG(mdiobus_c45_devad(phy_reg)) |\n+\t\t\t     PHY_IAC_ADDR(phy_addr) |\n+\t\t\t     PHY_IAC_DATA(mdiobus_c45_regad(phy_reg)),\n+\t\t\tMTK_PHY_IAC);\n+\n+\t\tret = mtk_mdio_busy_wait(eth);\n+\t\tif (ret < 0)\n+\t\t\treturn ret;\n+\n+\t\tmtk_w32(eth, PHY_IAC_ACCESS |\n+\t\t\t     PHY_IAC_START_C45 |\n+\t\t\t     PHY_IAC_CMD_WRITE |\n+\t\t\t     PHY_IAC_REG(mdiobus_c45_devad(phy_reg)) |\n+\t\t\t     PHY_IAC_ADDR(phy_addr) |\n+\t\t\t     PHY_IAC_DATA(write_data),\n+\t\t\tMTK_PHY_IAC);\n+\t} else {\n+\t\tmtk_w32(eth, PHY_IAC_ACCESS |\n+\t\t\t     PHY_IAC_START_C22 |\n+\t\t\t     PHY_IAC_CMD_WRITE |\n+\t\t\t     PHY_IAC_REG(phy_reg) |\n+\t\t\t     PHY_IAC_ADDR(phy_addr) |\n+\t\t\t     PHY_IAC_DATA(write_data),\n+\t\t\tMTK_PHY_IAC);\n+\t}\n \n \tret = mtk_mdio_busy_wait(eth);\n \tif (ret < 0)\n@@ -129,12 +151,33 @@ static int _mtk_mdio_read(struct mtk_eth\n \tif (ret < 0)\n \t\treturn ret;\n \n-\tmtk_w32(eth, PHY_IAC_ACCESS |\n-\t\t     PHY_IAC_START_C22 |\n-\t\t     PHY_IAC_CMD_C22_READ |\n-\t\t     PHY_IAC_REG(phy_reg) |\n-\t\t     PHY_IAC_ADDR(phy_addr),\n-\t\tMTK_PHY_IAC);\n+\tif (phy_reg & MII_ADDR_C45) {\n+\t\tmtk_w32(eth, PHY_IAC_ACCESS |\n+\t\t\t     PHY_IAC_START_C45 |\n+\t\t\t     PHY_IAC_CMD_C45_ADDR |\n+\t\t\t     PHY_IAC_REG(mdiobus_c45_devad(phy_reg)) |\n+\t\t\t     PHY_IAC_ADDR(phy_addr) |\n+\t\t\t     PHY_IAC_DATA(mdiobus_c45_regad(phy_reg)),\n+\t\t\tMTK_PHY_IAC);\n+\n+\t\tret = mtk_mdio_busy_wait(eth);\n+\t\tif (ret < 0)\n+\t\t\treturn ret;\n+\n+\t\tmtk_w32(eth, PHY_IAC_ACCESS |\n+\t\t\t     PHY_IAC_START_C45 |\n+\t\t\t     PHY_IAC_CMD_C45_READ |\n+\t\t\t     PHY_IAC_REG(mdiobus_c45_devad(phy_reg)) |\n+\t\t\t     PHY_IAC_ADDR(phy_addr),\n+\t\t\tMTK_PHY_IAC);\n+\t} else {\n+\t\tmtk_w32(eth, PHY_IAC_ACCESS |\n+\t\t\t     PHY_IAC_START_C22 |\n+\t\t\t     PHY_IAC_CMD_C22_READ |\n+\t\t\t     PHY_IAC_REG(phy_reg) |\n+\t\t\t     PHY_IAC_ADDR(phy_addr),\n+\t\t\tMTK_PHY_IAC);\n+\t}\n \n \tret = mtk_mdio_busy_wait(eth);\n \tif (ret < 0)\n@@ -593,6 +636,7 @@ static int mtk_mdio_init(struct mtk_eth\n \teth->mii_bus->name = \"mdio\";\n \teth->mii_bus->read = mtk_mdio_read;\n \teth->mii_bus->write = mtk_mdio_write;\n+\teth->mii_bus->probe_capabilities = MDIOBUS_C22_C45;\n \teth->mii_bus->priv = eth;\n \teth->mii_bus->parent = eth->dev;\n \n--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h\n+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h\n@@ -349,9 +349,12 @@\n #define PHY_IAC_ADDR_MASK\tGENMASK(24, 20)\n #define PHY_IAC_ADDR(x)\t\tFIELD_PREP(PHY_IAC_ADDR_MASK, (x))\n #define PHY_IAC_CMD_MASK\tGENMASK(19, 18)\n+#define PHY_IAC_CMD_C45_ADDR\tFIELD_PREP(PHY_IAC_CMD_MASK, 0)\n #define PHY_IAC_CMD_WRITE\tFIELD_PREP(PHY_IAC_CMD_MASK, 1)\n #define PHY_IAC_CMD_C22_READ\tFIELD_PREP(PHY_IAC_CMD_MASK, 2)\n+#define PHY_IAC_CMD_C45_READ\tFIELD_PREP(PHY_IAC_CMD_MASK, 3)\n #define PHY_IAC_START_MASK\tGENMASK(17, 16)\n+#define PHY_IAC_START_C45\tFIELD_PREP(PHY_IAC_START_MASK, 0)\n #define PHY_IAC_START_C22\tFIELD_PREP(PHY_IAC_START_MASK, 1)\n #define PHY_IAC_DATA_MASK\tGENMASK(15, 0)\n #define PHY_IAC_DATA(x)\t\tFIELD_PREP(PHY_IAC_DATA_MASK, (x))\n"
  },
  {
    "path": "target/linux/mediatek/patches-5.15/704-net-ethernet-mtk_eth_soc-announce-2500baseT.patch",
    "content": "--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c\n+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c\n@@ -577,6 +577,7 @@ static void mtk_validate(struct phylink_\n \t\tif (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_SGMII)) {\n \t\t\tphylink_set(mask, 1000baseT_Full);\n \t\t\tphylink_set(mask, 1000baseX_Full);\n+\t\t\tphylink_set(mask, 2500baseT_Full);\n \t\t\tphylink_set(mask, 2500baseX_Full);\n \t\t}\n \t\tif (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_RGMII)) {\n"
  },
  {
    "path": "target/linux/mediatek/patches-5.15/710-pci-pcie-mediatek-add-support-for-coherent-DMA.patch",
    "content": "From: Felix Fietkau <nbd@nbd.name>\nDate: Fri, 4 Sep 2020 18:42:42 +0200\nSubject: [PATCH] pci: pcie-mediatek: add support for coherent DMA\n\nIt improves performance by eliminating the need for a cache flush for DMA on\nattached devices\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n\n--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi\n+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi\n@@ -836,6 +836,9 @@\n \t\tbus-range = <0x00 0xff>;\n \t\tranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x8000000>;\n \t\tstatus = \"disabled\";\n+\t\tdma-coherent;\n+\t\tmediatek,hifsys = <&hifsys>;\n+\t\tmediatek,cci-control = <&cci_control2>;\n \n \t\t#interrupt-cells = <1>;\n \t\tinterrupt-map-mask = <0 0 0 7>;\n@@ -880,6 +883,9 @@\n \t\tbus-range = <0x00 0xff>;\n \t\tranges = <0x82000000 0 0x28000000 0x0 0x28000000 0 0x8000000>;\n \t\tstatus = \"disabled\";\n+\t\tdma-coherent;\n+\t\tmediatek,hifsys = <&hifsys>;\n+\t\tmediatek,cci-control = <&cci_control2>;\n \n \t\t#interrupt-cells = <1>;\n \t\tinterrupt-map-mask = <0 0 0 7>;\n--- a/drivers/pci/controller/pcie-mediatek.c\n+++ b/drivers/pci/controller/pcie-mediatek.c\n@@ -20,6 +20,7 @@\n #include <linux/of_address.h>\n #include <linux/of_pci.h>\n #include <linux/of_platform.h>\n+#include <linux/of_address.h>\n #include <linux/pci.h>\n #include <linux/phy/phy.h>\n #include <linux/platform_device.h>\n@@ -139,6 +140,11 @@\n #define PCIE_LINK_STATUS_V2\t0x804\n #define PCIE_PORT_LINKUP_V2\tBIT(10)\n \n+/* DMA channel mapping */\n+#define HIFSYS_DMA_AG_MAP\t0x008\n+#define HIFSYS_DMA_AG_MAP_PCIE0\tBIT(0)\n+#define HIFSYS_DMA_AG_MAP_PCIE1\tBIT(1)\n+\n struct mtk_pcie_port;\n \n /**\n@@ -1053,6 +1059,27 @@ static int mtk_pcie_setup(struct mtk_pci\n \tstruct mtk_pcie_port *port, *tmp;\n \tint err, slot;\n \n+\tif (of_dma_is_coherent(node)) {\n+\t\tstruct regmap *con;\n+\t\tu32 mask;\n+\n+\t\tcon = syscon_regmap_lookup_by_phandle(node,\n+\t\t\t\t\t\t      \"mediatek,cci-control\");\n+\t\t/* enable CPU/bus coherency */\n+\t\tif (!IS_ERR(con))\n+\t\t\tregmap_write(con, 0, 3);\n+\n+\t\tcon = syscon_regmap_lookup_by_phandle(node,\n+\t\t\t\t\t\t      \"mediatek,hifsys\");\n+\t\tif (IS_ERR(con)) {\n+\t\t\tdev_err(dev, \"missing hifsys node\\n\");\n+\t\t\treturn PTR_ERR(con);\n+\t\t}\n+\n+\t\tmask = HIFSYS_DMA_AG_MAP_PCIE0 | HIFSYS_DMA_AG_MAP_PCIE1;\n+\t\tregmap_update_bits(con, HIFSYS_DMA_AG_MAP, mask, mask);\n+\t}\n+\n \tslot = of_get_pci_domain_nr(dev->of_node);\n \tif (slot < 0) {\n \t\tfor_each_available_child_of_node(node, child) {\n"
  },
  {
    "path": "target/linux/mediatek/patches-5.15/721-dts-mt7622-mediatek-fix-300mhz.patch",
    "content": "From: Jip de Beer <gpk6x3591g0l@opayq.com>\nDate: Sun, 9 Jan 2022 13:14:04 +0100\nSubject: [PATCH] mediatek mt7622: fix 300mhz typo in dts\n\nThe lowest frequency should be 300MHz, since that is the label\nassigned to the OPP in the mt7622.dtsi device tree, while there is one\nmissing zero in the actual value.\n\nTo be clear, the lowest frequency should be 300MHz instead of 30MHz.\n\nAs mentioned @dangowrt on the OpenWrt forum there is no benefit in\nleaving 30MHz as the lowest frequency.\n\nSigned-off-by: Jip de Beer <gpk6x3591g0l@opayq.com>\nSigned-off-by: Fritz D. Ansel <fdansel@yandex.ru>\n---\n--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi\n+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi\n@@ -24,7 +24,7 @@\n \t\tcompatible = \"operating-points-v2\";\n \t\topp-shared;\n \t\topp-300000000 {\n-\t\t\topp-hz = /bits/ 64 <30000000>;\n+\t\t\topp-hz = /bits/ 64 <300000000>;\n \t\t\topp-microvolt = <950000>;\n \t\t};\n \n"
  },
  {
    "path": "target/linux/mediatek/patches-5.15/800-ubnt-ledbar-driver.patch",
    "content": "--- a/drivers/leds/Kconfig\n+++ b/drivers/leds/Kconfig\n@@ -876,6 +876,16 @@ source \"drivers/leds/blink/Kconfig\"\n comment \"Flash and Torch LED drivers\"\n source \"drivers/leds/flash/Kconfig\"\n \n+config LEDS_UBNT_LEDBAR\n+\ttristate \"LED support for Ubiquiti UniFi 6 LR\"\n+\tdepends on LEDS_CLASS && I2C && OF\n+\thelp\n+\t  This option enables support for the Ubiquiti LEDBAR\n+\t  LED driver.\n+\n+\t  To compile this driver as a module, choose M here: the module\n+\t  will be called leds-ubnt-ledbar.\n+\n comment \"LED Triggers\"\n source \"drivers/leds/trigger/Kconfig\"\n \n--- a/drivers/leds/Makefile\n+++ b/drivers/leds/Makefile\n@@ -87,6 +87,7 @@ obj-$(CONFIG_LEDS_TURRIS_OMNIA)\t\t+= leds\n obj-$(CONFIG_LEDS_WM831X_STATUS)\t+= leds-wm831x-status.o\n obj-$(CONFIG_LEDS_WM8350)\t\t+= leds-wm8350.o\n obj-$(CONFIG_LEDS_WRAP)\t\t\t+= leds-wrap.o\n+obj-$(CONFIG_LEDS_UBNT_LEDBAR)\t\t+= leds-ubnt-ledbar.o\n \n # LED SPI Drivers\n obj-$(CONFIG_LEDS_CR0014114)\t\t+= leds-cr0014114.o\n"
  },
  {
    "path": "target/linux/mediatek/patches-5.15/900-dts-mt7622-bpi-r64-aliases-for-dtoverlay.patch",
    "content": "--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts\n+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts\n@@ -318,7 +318,7 @@\n \t/* Attention: GPIO 90 is used to switch between PCIe@1,0 and\n \t * SATA functions. i.e. output-high: PCIe, output-low: SATA\n \t */\n-\tasm_sel {\n+\tasmsel: asm_sel {\n \t\tgpio-hog;\n \t\tgpios = <90 GPIO_ACTIVE_HIGH>;\n \t\toutput-high;\n--- /dev/null\n+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64-sata.dts\n@@ -0,0 +1,31 @@\n+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */\n+\n+#include <dt-bindings/gpio/gpio.h>\n+\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"bananapi,bpi-r64\", \"mediatek,mt7622\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&asmsel>;\n+\t\t__overlay__ {\n+\t\t\tgpios = <90 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\t};\n+\n+\tfragment@1 {\n+\t\ttarget = <&sata>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tfragment@2 {\n+\t\ttarget = <&sata_phy>;\n+\t\t__overlay__ {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+};\n--- /dev/null\n+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64-pcie1.dts\n@@ -0,0 +1,17 @@\n+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */\n+\n+#include <dt-bindings/gpio/gpio.h>\n+\n+/dts-v1/;\n+/plugin/;\n+\n+/ {\n+\tcompatible = \"bananapi,bpi-r64\", \"mediatek,mt7622\";\n+\n+\tfragment@0 {\n+\t\ttarget = <&asmsel>;\n+\t\t__overlay__ {\n+\t\t\tgpios = <90 GPIO_ACTIVE_HIGH>;\n+\t\t};\n+\t};\n+};\n"
  },
  {
    "path": "target/linux/mediatek/patches-5.15/910-dts-mt7622-bpi-r64-wifi-eeprom.patch",
    "content": "--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts\n+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts\n@@ -645,5 +645,28 @@\n };\n \n &wmac {\n+\tmediatek,eeprom-data = <0x22760500\t0x0\t\t0x0\t\t0x0\n+\t\t\t\t0x0\t\t0x0\t\t0x0\t\t0x0\n+\t\t\t\t0x0\t\t0x0\t\t0x0\t\t0x0\n+\t\t\t\t0x0\t\t0x44000020\t0x0\t\t0x10002000\n+\t\t\t\t0x4400\t\t0x4000000\t0x0\t\t0x0\n+\t\t\t\t0x200000b3\t0x40b6c3c3\t0x26000000\t0x41c42600\n+\t\t\t\t0x41c4\t\t0x26000000\t0xc0c52600\t0x0\n+\t\t\t\t0x0\t\t0x0\t\t0x0\t\t0x0\n+\t\t\t\t0x0\t\t0x0\t\t0x0\t\t0x0\n+\t\t\t\t0x0\t\t0x0\t\t0x0\t\t0x0\n+\t\t\t\t0x0\t\t0x0\t\t0x0\t\t0x0\n+\t\t\t\t0x0\t\t0x0\t\t0x0\t\t0xc6c6\n+\t\t\t\t0xc3c3c2c1\t0xc300c3\t0x818181\t0x83c1c182\n+\t\t\t\t0x83838382\t0x0\t\t0x0\t\t0x0\n+\t\t\t\t0x0\t\t0x0\t\t0x0\t\t0x0\n+\t\t\t\t0x84002e00\t0x90000087\t0x8a000000\t0x0\n+\t\t\t\t0x0\t\t0x0\t\t0x0\t\t0x0\n+\t\t\t\t0x0\t\t0x0\t\t0x0\t\t0x0\n+\t\t\t\t0xb000009\t0x0\t\t0x0\t\t0x0\n+\t\t\t\t0x0\t\t0x0\t\t0x0\t\t0x0\n+\t\t\t\t0x0\t\t0x0\t\t0x0\t\t0x0\n+\t\t\t\t0x0\t\t0x0\t\t0x0\t\t0x7707>;\n+\n \tstatus = \"okay\";\n };\n"
  },
  {
    "path": "target/linux/mpc85xx/Makefile",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2010 OpenWrt.org\n\ninclude $(TOPDIR)/rules.mk\n\nARCH:=powerpc\nBOARD:=mpc85xx\nBOARDNAME:=Freescale MPC85xx\nCPU_TYPE:=8540\nFEATURES:=squashfs ramdisk\nSUBTARGETS:=p1010 p1020 p2020\n\nKERNEL_PATCHVER:=5.10\n\nKERNELNAME:=zImage\n\ninclude $(INCLUDE_DIR)/target.mk\n\nDEFAULT_PACKAGES += \\\n\tkmod-input-core kmod-input-gpio-keys kmod-button-hotplug \\\n\tkmod-leds-gpio swconfig kmod-ath9k wpad-basic-wolfssl kmod-usb2 \\\n\tuboot-envtools\n\n$(eval $(call BuildTarget))\n"
  },
  {
    "path": "target/linux/mpc85xx/base-files/etc/board.d/01_leds",
    "content": "\n. /lib/functions/leds.sh\n. /lib/functions/uci-defaults.sh\n\nboard=$(board_name)\nboardname=\"${board##*,}\"\n\nboard_config_update\n\ncase $board in\nextreme-networks,ws-ap3825i)\n\tucidef_set_led_netdev \"lan1\" \"LAN1\" \"green:lan1\" \"eth1\"\n\tucidef_set_led_netdev \"lan2\" \"LAN2\" \"green:lan2\" \"eth0\"\n\t;;\nesac\n\nboard_config_flush\n\nexit 0\n"
  },
  {
    "path": "target/linux/mpc85xx/base-files/etc/board.d/02_network",
    "content": "# Copyright (C) 2014-2015 OpenWrt.org\n\n. /lib/functions/uci-defaults.sh\n. /lib/functions.sh\n. /lib/functions/system.sh\n\nboard_config_update\n\nboard=$(board_name)\n\ncase \"$board\" in\naerohive,hiveap-330)\n\tucidef_set_interfaces_lan_wan \"eth1\" \"eth0\"\n\t;;\nocedo,panda)\n\tucidef_set_interface_wan \"eth1\"\n\tucidef_add_switch \"switch0\" \\\n\t\t\"0:lan\" \"1:lan\" \"2:lan\" \"3:lan\" \"4:lan\" \"5:lan\" \"6:lan\" \"7:lan\" \"8u@eth0\"\n\t;;\ntplink,tl-wdr4900-v1)\n\tucidef_add_switch \"switch0\" \\\n\t\t\"0@eth0\" \"2:lan:1\" \"3:lan:2\" \"4:lan:3\" \"5:lan:4\" \"1:wan\"\n\tucidef_set_interface_macaddr \"wan\" \"$(macaddr_add $(mtd_get_mac_binary u-boot 0x4fc00) 1)\"\n\t;;\n*)\n\tucidef_set_interfaces_lan_wan \"eth0\" \"eth1\"\n\t;;\nesac\n\nboard_config_flush\n\nexit 0\n"
  },
  {
    "path": "target/linux/mpc85xx/base-files/etc/hotplug.d/firmware/10-ath9k-eeprom",
    "content": "#!/bin/sh\n\n[ -e /lib/firmware/$FIRMWARE ] && exit 0\n\n. /lib/functions/caldata.sh\n\nboard=$(board_name)\n\ncase \"$FIRMWARE\" in\n\"pci_wmac0.eeprom\")\n\tcase $board in\n\ttplink,tl-wdr4900-v1)\n\t\tcaldata_extract \"caldata\" 0x1000 0x800\n\t\tath9k_patch_mac $(mtd_get_mac_binary u-boot 0x4fc00)\n\t\t;;\n\t*)\n\t\tcaldata_die \"board $board is not supported yet\"\n\t\t;;\n\tesac\n\t;;\n\n\"pci_wmac1.eeprom\")\n\tcase $board in\n\ttplink,tl-wdr4900-v1)\n\t\tcaldata_extract \"caldata\" 0x5000 0x800\n\t\tath9k_patch_mac $(macaddr_add $(mtd_get_mac_binary u-boot 0x4fc00) -1)\n\t\t;;\n\t*)\n\t\tcaldata_die \"board $board is not supported yet\"\n\t\t;;\n\tesac\n\t;;\nesac\n"
  },
  {
    "path": "target/linux/mpc85xx/base-files/etc/hotplug.d/ieee80211/05-wifi-migrate",
    "content": "#!/bin/sh\n\n# This must run before 10-wifi-detect\n\n\n[ \"${ACTION}\" = \"add\" ] || return\n\n\n. /lib/functions.sh\n\n\ncheck_radio()\n{\n\tlocal cfg=\"$1\" to=\"$2\"\n\n\tconfig_get path \"$cfg\" path\n\n\t[ \"$path\" = \"$to\" ] && PATH_EXISTS=true\n}\n\ndo_migrate_radio()\n{\n\tlocal cfg=\"$1\" from=\"$2\" to=\"$3\"\n\n\tconfig_get path \"$cfg\" path\n\n\t[ \"$path\" = \"$from\" ] || return\n\n\tuci set \"wireless.${cfg}.path=${to}\"\n\tWIRELESS_CHANGED=true\n\n\tlogger -t wifi-migrate \"Updated path of wireless.${cfg} from '${from}' to '${to}'\"\n}\n\nmigrate_radio()\n{\n\tlocal from=\"$1\" to=\"$2\"\n\n\tconfig_load wireless\n\n\t# Check if there is already a section with the target path: In this case, the system\n\t# was already upgraded to a version without this migration script before; better bail out,\n\t# as we can't be sure we don't break more than we fix.\n\tPATH_EXISTS=false\n\tconfig_foreach check_radio wifi-device \"$to\"\n\t$PATH_EXISTS && return\n\n\tconfig_foreach do_migrate_radio wifi-device \"$from\" \"$to\"\n}\n\n\nWIRELESS_CHANGED=false\n\ncase \"$(board_name)\" in\ntplink,tl-wdr4900-v1)\n\tmigrate_radio 'ffe09000.pcie/pci0000:00/0000:00:00.0/0000:01:00.0' 'ffe09000.pcie/pci9000:00/9000:00:00.0/9000:01:00.0'\n\tmigrate_radio 'ffe0a000.pcie/pci0001:02/0001:02:00.0/0001:03:00.0' 'ffe0a000.pcie/pcia000:02/a000:02:00.0/a000:03:00.0'\n\t;;\nesac\n\n$WIRELESS_CHANGED && uci commit wireless\n\nexit 0\n"
  },
  {
    "path": "target/linux/mpc85xx/base-files/etc/hotplug.d/ieee80211/10-fix-wifi-mac",
    "content": "#!/bin/ash\n\n[ \"$ACTION\" = \"add\" ] || exit 0\n\nPHYNBR=${DEVPATH##*/phy}\n\n[ -n \"$PHYNBR\" ] || exit 0\n\n. /lib/functions.sh\n. /lib/functions/system.sh\n\nboard=$(board_name)\n\ncase \"$board\" in\nenterasys,ws-ap3710i|\\\nextreme-networks,ws-ap3825i)\n\tmtd_get_mac_ascii cfg2 RADIOADDR${PHYNBR} > /sys${DEVPATH}/macaddress\n\t;;\nocedo,panda)\n\tmtd_get_mac_ascii uboot-env0 wmac$(($PHYNBR + 1)) > /sys${DEVPATH}/macaddress\n\t;;\nsophos,red-15w-rev1)\n\tmtd_get_mac_ascii u-boot-env ethaddr > /sys${DEVPATH}/macaddress\n\t;;\nesac\n"
  },
  {
    "path": "target/linux/mpc85xx/base-files/etc/uci-defaults/05_fix-compat-version",
    "content": ". /lib/functions.sh\n. /lib/functions/system.sh\n\ncase \"$(board_name)\" in\naerohive,hiveap-330)\n\tuci set system.@system[0].compat_version=\"2.0\"\n\tuci commit system\n\t;;\nesac\n\nexit 0\n"
  },
  {
    "path": "target/linux/mpc85xx/base-files/lib/preinit/05_set_preinit_iface_mpc85xx",
    "content": "#\n# Copyright (C) 2013 OpenWrt.org\n#\n\nmpc85xx_set_preinit_iface() {\n\tifname=eth0\n}\n\nboot_hook_add preinit_main mpc85xx_set_preinit_iface\n"
  },
  {
    "path": "target/linux/mpc85xx/base-files/lib/preinit/10_fix_eth_mac.sh",
    "content": ". /lib/functions.sh\n\npreinit_set_mac_address() {\n\tcase $(board_name) in\n\textreme-networks,ws-ap3825i)\n\t\tip link set dev eth0 address $(mtd_get_mac_ascii cfg1 ethaddr)\n\t\tip link set dev eth1 address $(mtd_get_mac_ascii cfg1 eth1addr)\n\t\t;;\n\tesac\n}\n\nboot_hook_add preinit_main preinit_set_mac_address\n"
  },
  {
    "path": "target/linux/mpc85xx/base-files/lib/upgrade/platform.sh",
    "content": "#\n# Copyright (C) 2011 OpenWrt.org\n#\n\nPART_NAME=firmware\nREQUIRE_IMAGE_METADATA=1\n\nplatform_check_image() {\n\treturn 0\n}\n\nplatform_do_upgrade() {\n\tlocal board=$(board_name)\n\n\tcase \"$board\" in\n\tocedo,panda|\\\n\tsophos,red-15w-rev1)\n\t\tnand_do_upgrade \"$1\"\n\t\t;;\n\t*)\n\t\tdefault_do_upgrade \"$1\"\n\t\t;;\n\tesac\n}\n"
  },
  {
    "path": "target/linux/mpc85xx/config-5.10",
    "content": "# CONFIG_40x is not set\n# CONFIG_44x is not set\n# CONFIG_ADVANCED_OPTIONS is not set\nCONFIG_AR8216_PHY=y\nCONFIG_AR8216_PHY_LEDS=y\nCONFIG_ARCH_32BIT_OFF_T=y\nCONFIG_ARCH_HIBERNATION_POSSIBLE=y\nCONFIG_ARCH_KEEP_MEMBLOCK=y\nCONFIG_ARCH_MAY_HAVE_PC_FDC=y\nCONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y\nCONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y\nCONFIG_ARCH_MMAP_RND_BITS=11\nCONFIG_ARCH_MMAP_RND_BITS_MAX=17\nCONFIG_ARCH_MMAP_RND_BITS_MIN=11\nCONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=17\nCONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11\nCONFIG_ARCH_OPTIONAL_KERNEL_RWX=y\nCONFIG_ARCH_SUSPEND_POSSIBLE=y\nCONFIG_ARCH_WEAK_RELEASE_ACQUIRE=y\nCONFIG_ASN1=y\nCONFIG_AUDIT_ARCH=y\nCONFIG_BLK_MQ_PCI=y\nCONFIG_BOOKE=y\nCONFIG_BOOKE_WDT=y\n# CONFIG_BSC9131_RDB is not set\n# CONFIG_BSC9132_QDS is not set\n# CONFIG_C293_PCIE is not set\nCONFIG_CLONE_BACKWARDS=y\nCONFIG_CLZ_TAB=y\nCONFIG_CMDLINE=\"console=ttyS0,115200\"\nCONFIG_CMDLINE_FROM_BOOTLOADER=y\n# CONFIG_CMDLINE_OVERRIDE is not set\n# CONFIG_COMMON_CLK is not set\nCONFIG_COMPAT_32BIT_TIME=y\n# CONFIG_CORENET_GENERIC is not set\n# CONFIG_CPM2 is not set\nCONFIG_CPU_BIG_ENDIAN=y\n# CONFIG_CRYPTO_AES_PPC_SPE is not set\nCONFIG_CRYPTO_AKCIPHER=y\nCONFIG_CRYPTO_AKCIPHER2=y\nCONFIG_CRYPTO_AUTHENC=y\nCONFIG_CRYPTO_HW=y\nCONFIG_CRYPTO_LIB_POLY1305_RSIZE=1\n# CONFIG_CRYPTO_MD5_PPC is not set\nCONFIG_CRYPTO_NULL=y\nCONFIG_CRYPTO_RNG=y\nCONFIG_CRYPTO_RNG2=y\nCONFIG_CRYPTO_RSA=y\n# CONFIG_CRYPTO_SHA1_PPC is not set\n# CONFIG_CRYPTO_SHA1_PPC_SPE is not set\n# CONFIG_CRYPTO_SHA256_PPC_SPE is not set\nCONFIG_DATA_SHIFT=12\nCONFIG_DEBUG_BUGVERBOSE=y\nCONFIG_DNOTIFY=y\nCONFIG_DTC=y\n# CONFIG_E200 is not set\nCONFIG_E500=y\n# CONFIG_E5500_CPU is not set\n# CONFIG_E6500_CPU is not set\nCONFIG_EARLY_PRINTK=y\nCONFIG_EDAC=y\nCONFIG_EDAC_ATOMIC_SCRUB=y\n# CONFIG_EDAC_DEBUG is not set\nCONFIG_EDAC_LEGACY_SYSFS=y\nCONFIG_EDAC_MPC85XX=y\nCONFIG_EDAC_SUPPORT=y\nCONFIG_ENABLE_MUST_CHECK=y\nCONFIG_ETHERNET_PACKET_MANGLE=y\nCONFIG_FIXED_PHY=y\nCONFIG_FSL_BOOKE=y\nCONFIG_FSL_EMB_PERFMON=y\n# CONFIG_FSL_FMAN is not set\nCONFIG_FSL_LBC=y\nCONFIG_FSL_PCI=y\nCONFIG_FSL_PQ_MDIO=y\nCONFIG_FSL_SOC=y\nCONFIG_FSL_SOC_BOOKE=y\nCONFIG_FW_LOADER_PAGED_BUF=y\nCONFIG_GENERIC_ALLOCATOR=y\nCONFIG_GENERIC_ATOMIC64=y\nCONFIG_GENERIC_BUG=y\nCONFIG_GENERIC_CLOCKEVENTS=y\nCONFIG_GENERIC_CMOS_UPDATE=y\nCONFIG_GENERIC_CPU=y\nCONFIG_GENERIC_CPU_AUTOPROBE=y\nCONFIG_GENERIC_CPU_VULNERABILITIES=y\nCONFIG_GENERIC_EARLY_IOREMAP=y\nCONFIG_GENERIC_IRQ_SHOW=y\nCONFIG_GENERIC_IRQ_SHOW_LEVEL=y\nCONFIG_GENERIC_ISA_DMA=y\nCONFIG_GENERIC_PCI_IOMAP=y\nCONFIG_GENERIC_SMP_IDLE_THREAD=y\nCONFIG_GENERIC_STRNCPY_FROM_USER=y\nCONFIG_GENERIC_STRNLEN_USER=y\nCONFIG_GENERIC_TIME_VSYSCALL=y\nCONFIG_GEN_RTC=y\n# CONFIG_GE_IMP3A is not set\nCONFIG_GIANFAR=y\nCONFIG_GPIOLIB=y\nCONFIG_GPIO_GENERIC=y\nCONFIG_GPIO_MPC8XXX=y\nCONFIG_HAS_DMA=y\nCONFIG_HAS_IOMEM=y\nCONFIG_HAS_IOPORT_MAP=y\n# CONFIG_HIVEAP_330 is not set\nCONFIG_HW_RANDOM=y\n# CONFIG_HW_RANDOM_XIPHERA is not set\nCONFIG_HZ_PERIODIC=y\nCONFIG_I2C=y\nCONFIG_I2C_BOARDINFO=y\nCONFIG_I2C_MPC=y\nCONFIG_ILLEGAL_POINTER_VALUE=0\nCONFIG_INITRAMFS_SOURCE=\"\"\nCONFIG_IRQCHIP=y\nCONFIG_IRQ_DOMAIN=y\nCONFIG_IRQ_FORCED_THREADING=y\nCONFIG_IRQ_WORK=y\nCONFIG_ISA_DMA_API=y\nCONFIG_KERNEL_START=0xc0000000\n# CONFIG_KSI8560 is not set\nCONFIG_LEGACY_PTYS=y\nCONFIG_LEGACY_PTY_COUNT=256\nCONFIG_LIBFDT=y\nCONFIG_LOCK_DEBUGGING_SUPPORT=y\nCONFIG_LOWMEM_CAM_NUM=3\nCONFIG_LOWMEM_SIZE=0x30000000\nCONFIG_LXT_PHY=y\n# CONFIG_MATH_EMULATION is not set\nCONFIG_MDIO_BUS=y\nCONFIG_MDIO_DEVICE=y\nCONFIG_MEMFD_CREATE=y\n# CONFIG_MFD_ROHM_BD71828 is not set\nCONFIG_MIGRATION=y\nCONFIG_MMU_GATHER_PAGE_SIZE=y\nCONFIG_MODULES_USE_ELF_RELA=y\n# CONFIG_MPC8536_DS is not set\n# CONFIG_MPC8540_ADS is not set\n# CONFIG_MPC8560_ADS is not set\n# CONFIG_MPC85xx_CDS is not set\n# CONFIG_MPC85xx_DS is not set\n# CONFIG_MPC85xx_MDS is not set\n# CONFIG_MPC85xx_RDB is not set\nCONFIG_MPIC=y\n# CONFIG_MPIC_MSGR is not set\nCONFIG_MPIC_TIMER=y\nCONFIG_MPILIB=y\n# CONFIG_MTD_CFI is not set\nCONFIG_MTD_NAND_CORE=y\nCONFIG_MTD_NAND_ECC=y\nCONFIG_MTD_NAND_ECC_SW_HAMMING=y\nCONFIG_MTD_RAW_NAND=y\nCONFIG_MTD_SPI_NOR=y\n# CONFIG_MVME2500 is not set\nCONFIG_NEED_PER_CPU_KM=y\nCONFIG_NEED_SG_DMA_LENGTH=y\nCONFIG_NLS=y\nCONFIG_NR_IRQS=512\nCONFIG_NVMEM=y\nCONFIG_OF=y\nCONFIG_OF_ADDRESS=y\nCONFIG_OF_DMA_DEFAULT_COHERENT=y\nCONFIG_OF_EARLY_FLATTREE=y\nCONFIG_OF_FLATTREE=y\nCONFIG_OF_GPIO=y\nCONFIG_OF_IRQ=y\nCONFIG_OF_KOBJ=y\nCONFIG_OF_MDIO=y\nCONFIG_OF_NET=y\nCONFIG_OLD_SIGACTION=y\nCONFIG_OLD_SIGSUSPEND=y\n# CONFIG_P1010_RDB is not set\n# CONFIG_P1022_DS is not set\n# CONFIG_P1022_RDK is not set\n# CONFIG_P1023_RDB is not set\nCONFIG_PAGE_OFFSET=0xc0000000\n# CONFIG_PANDA is not set\nCONFIG_PCI=y\nCONFIG_PCIEAER=y\nCONFIG_PCIEASPM=y\nCONFIG_PCIEASPM_DEFAULT=y\n# CONFIG_PCIEASPM_PERFORMANCE is not set\n# CONFIG_PCIEASPM_POWERSAVE is not set\n# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set\nCONFIG_PCIEPORTBUS=y\nCONFIG_PCI_DOMAINS=y\nCONFIG_PGTABLE_LEVELS=2\nCONFIG_PHYLIB=y\nCONFIG_PHYSICAL_ALIGN=0x04000000\nCONFIG_PHYSICAL_START=0x00000000\n# CONFIG_PHYS_64BIT is not set\n# CONFIG_PMU_SYSFS is not set\n# CONFIG_PPA8548 is not set\nCONFIG_PPC=y\nCONFIG_PPC32=y\n# CONFIG_PPC64 is not set\nCONFIG_PPC_85xx=y\n# CONFIG_PPC_8xx is not set\nCONFIG_PPC_ADV_DEBUG_DACS=2\nCONFIG_PPC_ADV_DEBUG_DVCS=0\nCONFIG_PPC_ADV_DEBUG_IACS=2\nCONFIG_PPC_ADV_DEBUG_REGS=y\nCONFIG_PPC_BARRIER_NOSPEC=y\nCONFIG_PPC_BOOK3E_MMU=y\n# CONFIG_PPC_BOOK3S_6xx is not set\nCONFIG_PPC_DOORBELL=y\n# CONFIG_PPC_E500MC is not set\n# CONFIG_PPC_EARLY_DEBUG is not set\nCONFIG_PPC_FSL_BOOK3E=y\nCONFIG_PPC_INDIRECT_PCI=y\n# CONFIG_PPC_IRQ_SOFT_MASK_DEBUG is not set\nCONFIG_PPC_MMU_NOHASH=y\nCONFIG_PPC_MMU_NOHASH_32=y\nCONFIG_PPC_PAGE_SHIFT=12\n# CONFIG_PPC_PTDUMP is not set\n# CONFIG_PPC_QEMU_E500 is not set\nCONFIG_PPC_SMP_MUXED_IPI=y\nCONFIG_PPC_UDBG_16550=y\nCONFIG_PPC_WERROR=y\nCONFIG_QE_GPIO=y\nCONFIG_QUICC_ENGINE=y\nCONFIG_RAS=y\n# CONFIG_RED_15W_REV1 is not set\nCONFIG_RTC_CLASS=y\nCONFIG_RTC_DRV_GENERIC=y\n# CONFIG_RTC_DRV_RV3032 is not set\nCONFIG_RTC_I2C_AND_SPI=y\nCONFIG_RTC_MC146818_LIB=y\n# CONFIG_SBC8548 is not set\n# CONFIG_SCOM_DEBUGFS is not set\nCONFIG_SERIAL_8250_EXTENDED=y\nCONFIG_SERIAL_8250_FSL=y\nCONFIG_SERIAL_8250_SHARE_IRQ=y\nCONFIG_SERIAL_MCTRL_GPIO=y\nCONFIG_SERIAL_OF_PLATFORM=y\n# CONFIG_SERIAL_QE is not set\n# CONFIG_SOCRATES is not set\nCONFIG_SPARSE_IRQ=y\nCONFIG_SPE=y\nCONFIG_SPE_POSSIBLE=y\nCONFIG_SPI=y\nCONFIG_SPI_FSL_ESPI=y\nCONFIG_SPI_MASTER=y\nCONFIG_SPI_MEM=y\nCONFIG_SRCU=y\n# CONFIG_STRIP_ASM_SYMS is not set\n# CONFIG_STX_GP3 is not set\nCONFIG_SWCONFIG=y\nCONFIG_SWPHY=y\nCONFIG_SYSCTL_EXCEPTION_TRACE=y\nCONFIG_TASK_SIZE=0xc0000000\nCONFIG_THREAD_INFO_IN_TASK=y\nCONFIG_THREAD_SHIFT=13\nCONFIG_TICK_CPU_ACCOUNTING=y\nCONFIG_TINY_SRCU=y\n# CONFIG_TL_WDR4900_V1 is not set\n# CONFIG_TQM8540 is not set\n# CONFIG_TQM8541 is not set\n# CONFIG_TQM8548 is not set\n# CONFIG_TQM8555 is not set\n# CONFIG_TQM8560 is not set\n# CONFIG_TWR_P102x is not set\nCONFIG_UCC=y\nCONFIG_UCC_FAST=y\nCONFIG_UCC_GETH=y\n# CONFIG_UGETH_TX_ON_DEMAND is not set\nCONFIG_USB_SUPPORT=y\nCONFIG_VDSO32=y\n# CONFIG_VIRT_CPU_ACCOUNTING_NATIVE is not set\nCONFIG_VM_EVENT_COUNTERS=y\nCONFIG_WATCHDOG_CORE=y\n# CONFIG_WS_AP3710I is not set\n# CONFIG_WS_AP3825I is not set\n# CONFIG_XES_MPC85xx is not set\nCONFIG_XZ_DEC_BCJ=y\nCONFIG_XZ_DEC_POWERPC=y\n"
  },
  {
    "path": "target/linux/mpc85xx/files/arch/powerpc/boot/dts/hiveap-330.dts",
    "content": "/*\n * Aerohive HiveAP-330 Device Tree Source\n *\n * Copyright (C) 2017 Chris Blake <chrisrblake93@gmail.com>\n *\n * This program is free software; you can redistribute  it and/or modify it\n * under  the terms of  the GNU General  Public License as published by the\n * Free Software Foundation;  either version 2 of the  License, or (at your\n * option) any later version.\n */\n\n#include <dt-bindings/leds/common.h>\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/gpio/gpio.h>\n\n/include/ \"fsl/p1020si-pre.dtsi\"\n/ {\n\tmodel = \"Aerohive HiveAP-330\";\n\tcompatible = \"aerohive,hiveap-330\";\n\n\taliases {\n\t\tled-boot = &led_power_green;\n\t\tled-failsafe = &led_fault_red;\n\t\tled-running = &led_power_green;\n\t\tled-upgrade = &led_fault_red;\n\t\tlabel-mac-device = &enet0;\n\t\tspi0 = &spi0;\n\t};\n\n\tmemory {\n\t\tdevice_type = \"memory\";\n\t};\n\n\tboard_lbc: lbc: localbus@ffe05000 {\n\t\treg = <0 0xffe05000 0 0x1000>;\n\t\tranges = <0x0 0x0 0x0 0xec000000 0x4000000>;\n\n\t\tnor@0,0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\t\t\tcompatible = \"cfi-flash\";\n\t\t\treg = <0x0 0x0 0x4000000>;\n\t\t\tbank-width = <2>;\n\t\t\tdevice-width = <1>;\n\n\t\t\tpartitions {\n\t\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\n\t\t\t\tfirmware@0 {\n\t\t\t\t\treg = <0x0 0x3f00000>;\n\t\t\t\t\tlabel = \"firmware\";\n\t\t\t\t\t/*\n\t\t\t\t\t * This unknown/invalid compatible prevents\n\t\t\t\t\t * openwrt's mtdsplit_fit to go off a tangent if it\n\t\t\t\t\t * finds a magic value inside the uncompressed kernel\n\t\t\t\t\t * at a blocksized aligned place.\n\t\t\t\t\t */\n\t\t\t\t\tcompatible = \"areohive,hiveap-330-image\";\n\t\t\t\t};\n\n\t\t\t\tpartition@0 {\n\t\t\t\t\treg = <0x0 0x40000>;\n\t\t\t\t\tlabel = \"dtb\";\n\t\t\t\t};\n\n\t\t\t\tpartition@40000 {\n\t\t\t\t\tcompatible = \"openwrt,uimage\", \"denx,uimage\";\n\t\t\t\t\treg = <0x40000 0x3ec0000>;\n\t\t\t\t\tlabel = \"kernel\";\n\t\t\t\t};\n\n\t\t\t\tpartition@3f00000 {\n\t\t\t\t\treg = <0x3f00000 0x20000>;\n\t\t\t\t\tlabel = \"hw-info\";\n\t\t\t\t\tread-only;\n\n\t\t\t\t\tcompatible = \"nvmem-cells\";\n\t\t\t\t\t#address-cells = <1>;\n\t\t\t\t\t#size-cells = <1>;\n\n\t\t\t\t\tmacaddr_hwinfo_0: macaddr@0 {\n\t\t\t\t\t\treg = <0x0 0x6>;\n\t\t\t\t\t};\n\t\t\t\t};\n\n\t\t\t\tpartition@3f20000 {\n\t\t\t\t\treg = <0x3f20000 0x20000>;\n\t\t\t\t\tlabel = \"boot-info\";\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\tpartition@3f40000 {\n\t\t\t\t\treg = <0x3f40000 0x20000>;\n\t\t\t\t\tlabel = \"boot-info-backup\";\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\tpartition@3f60000 {\n\t\t\t\t\treg = <0x3f60000 0x20000>;\n\t\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\t};\n\n\t\t\t\tpartition@3f80000 {\n\t\t\t\t\treg = <0x3f80000 0x80000>;\n\t\t\t\t\tlabel = \"u-boot\";\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t};\n\n\tboard_soc: soc: soc@ffe00000 {\n\t\tranges = <0x0 0x0 0xffe00000 0x100000>;\n\n\t\tspi0: spi@7000 {\n\t\t\ttemperature-sensor@1 {\n\t\t\t\tcompatible = \"ti,tmp125\";\n\t\t\t\treg = <1>;\n\t\t\t\tspi-max-frequency = <5000000>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@3100 {\n\t\t\ttpm@29 {\n\t\t\t\tcompatible = \"atmel,at97sc3204t\";\n\t\t\t\treg = <0x29>;\n\t\t\t};\n\n\t\t\tlp5521@32 {\n\t\t\t\tcompatible = \"national,lp5521\";\n\t\t\t\treg = <0x32>;\n\t\t\t\tclock-mode = /bits/ 8 <2>;\n#if 1\n\t\t\t\tled_fault_red: led@0 {\n\t\t\t\t\treg = <0>;\n\t\t\t\t\tchan-name = \"fault:red\";\n\t\t\t\t\tled-cur = /bits/ 8 <0x2f>;\n\t\t\t\t\tmax-cur = /bits/ 8 <0x5f>;\n\t\t\t\t\tcolor = <LED_COLOR_ID_RED>;\n\t\t\t\t\tfunction = LED_FUNCTION_FAULT;\n\t\t\t\t};\n\t\t\t\tled_power_green: led@1 {\n\t\t\t\t\treg = <1>;\n\t\t\t\t\tchan-name = \"power:green\";\n\t\t\t\t\tled-cur = /bits/ 8 <0x2f>;\n\t\t\t\t\tmax-cur = /bits/ 8 <0x5f>;\n\t\t\t\t\tcolor = <LED_COLOR_ID_GREEN>;\n\t\t\t\t\tfunction = LED_FUNCTION_POWER;\n\t\t\t\t};\n\t\t\t\tled@2{\n\t\t\t\t\treg = <2>;\n\t\t\t\t\tchan-name = \"blue\";\n\t\t\t\t\tled-cur = /bits/ 8 <0x2f>;\n\t\t\t\t\tmax-cur = /bits/ 8 <0x5f>;\n\t\t\t\t\tcolor = <LED_COLOR_ID_BLUE>;\n\t\t\t\t};\n#else\n\t\t\t\t/*\n\t\t\t\t * openwrt isn't ready to handle multi-intensity leds yet\n\t\t\t\t * # echo 255 255 255 > /sys/class/leds/tricolor/multi_intensity\n\t\t\t\t * # echo 255 > /sys/class/leds/tricolor/brightness\n\t\t\t\t */\n\n\t\t\t\trgbled-0 {\n\t\t\t\t\tfunction = LED_FUNCTION_POWER;\n\t\t\t\t\tcolor = <LED_COLOR_ID_RGB>;\n\t\t\t\t\t#address-cells = <1>;\n\t\t\t\t\t#size-cells = <0>;\n\n\t\t\t\t\tled@0 {\n\t\t\t\t\t\treg = <0>;\n\t\t\t\t\t\tchan-name = \"tricolor\";\n\t\t\t\t\t\tled-cur = /bits/ 8 <0x2f>;\n\t\t\t\t\t\tmax-cur = /bits/ 8 <0x5f>;\n\t\t\t\t\t\tcolor = <LED_COLOR_ID_RED>;\n\t\t\t\t\t};\n\t\t\t\t\tled@1 {\n\t\t\t\t\t\treg = <1>;\n\t\t\t\t\t\tchan-name = \"tricolor\";\n\t\t\t\t\t\tled-cur = /bits/ 8 <0x2f>;\n\t\t\t\t\t\tmax-cur = /bits/ 8 <0x5f>;\n\t\t\t\t\t\tcolor = <LED_COLOR_ID_GREEN>;\n\t\t\t\t\t};\n\t\t\t\t\tled@2{\n\t\t\t\t\t\treg = <2>;\n\t\t\t\t\t\tchan-name = \"tricolor\";\n\t\t\t\t\t\tled-cur = /bits/ 8 <0x2f>;\n\t\t\t\t\t\tmax-cur = /bits/ 8 <0x5f>;\n\t\t\t\t\t\tcolor = <LED_COLOR_ID_BLUE>;\n\t\t\t\t\t};\n\t\t\t\t};\n#endif\n\t\t\t};\n\n\t\t\teeprom@51 {\n\t\t\t\t/*\n\t\t\t\t * 1Kbit I2C/SMBus EEPROM with SHA-1 Engine\n\t\t\t\t * Aerohive calls it \"dallas\".\n\t\t\t\t */\n\t\t\t\tcompatible = \"adi,ds28cn01\";\n\t\t\t\treg = <0x51>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\n\t\tmdio@24000 {\n\t\t\tphy0: ethernet-phy@0 {\n\t\t\t\tinterrupts = <3 1 0 0>;\n\t\t\t\treg = <0x1>;\n\t\t\t};\n\n\t\t\tphy1: ethernet-phy@1 {\n\t\t\t\tinterrupts = <2 1 0 0>;\n\t\t\t\treg = <0x2>;\n\t\t\t};\n\t\t};\n\n\t\tmdio@25000 {\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tmdio@26000 {\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tenet0: ethernet@b0000 {\n\t\t\tstatus = \"okay\";\n\t\t\tphy-handle = <&phy0>;\n\t\t\tphy-connection-type = \"rgmii-id\";\n\t\t\tnvmem-cells = <&macaddr_hwinfo_0>;\n\t\t\tnvmem-cell-names = \"mac-address\";\n\t\t};\n\n\t\tenet1: ethernet@b1000 {\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tenet2: ethernet@b2000 {\n\t\t\tstatus = \"okay\";\n\t\t\tphy-handle = <&phy1>;\n\t\t\tphy-connection-type = \"rgmii-id\";\n\t\t\tnvmem-cells = <&macaddr_hwinfo_0>;\n\t\t\tnvmem-cell-names = \"mac-address\";\n\t\t\tmac-address-increment = <1>;\n\t\t};\n\n\t\tgpio0: gpio-controller@fc00 {\n\t\t};\n\n\t\tusb@22000 {\n\t\t\tphy_type = \"ulpi\";\n\t\t\tdr_mode = \"host\";\n\t\t};\n\n\t\tusb@23000 {\n\t\t\tstatus = \"disabled\";\n\t\t};\n\t};\n\n\tpci0: pcie@ffe09000 {\n\t\treg = <0x0 0xffe09000 0x0 0x1000>;\n\t\tranges = <0x2000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x20000000\n\t\t\t0x1000000 0x0 0x00000000 0x0 0xffc30000 0x0 0x10000>;\n\t\tpcie@0 {\n\t\t\tranges = <0x2000000 0x0 0xa0000000\n\t\t\t\t  0x2000000 0x0 0xa0000000\n\t\t\t\t  0x0 0x20000000\n\n\t\t\t\t  0x1000000 0x0 0x0\n\t\t\t\t  0x1000000 0x0 0x0\n\t\t\t\t  0x0 0x100000>;\n\t\t};\n\t};\n\n\tpci1: pcie@ffe0a000 {\n\t\treg = <0x0 0xffe0a000 0x0 0x1000>;\n\t\tranges = <0x2000000 0x0 0xc0000000 0x0 0xc0000000 0x0 0x20000000\n\t\t      0x1000000 0x0 0x00000000 0x0 0xffc20000 0x0 0x10000>;\n\t\tpcie@0 {\n\t\t\tranges = <0x2000000 0x0 0xc0000000\n\t\t\t      0x2000000 0x0 0xc0000000\n\t\t\t\t  0x0 0x20000000\n\n\t\t\t\t  0x1000000 0x0 0x0\n\t\t\t\t  0x1000000 0x0 0x0\n\t\t\t\t  0x0 0x100000>;\n\t\t};\n\t};\n\n\tbuttons {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"Reset button\";\n\t\t\tgpios = <&gpio0 8 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n};\n/include/ \"fsl/p1020si-post.dtsi\"\n"
  },
  {
    "path": "target/linux/mpc85xx/files/arch/powerpc/boot/dts/panda.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later or MIT\n\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/gpio/gpio.h>\n\n/include/ \"fsl/p1020si-pre.dtsi\"\n/ {\n\tmodel = \"OCEDO Panda\";\n\tcompatible = \"ocedo,panda\";\n\n\taliases {\n\t\tled-boot = &system_blue;\n\t\tled-failsafe = &system_blue;\n\t\tled-running = &system_blue;\n\t\tled-upgrade = &system_blue;\n\t};\n\n\tchosen {\n\t\t/* Needed for initramfs */\n\t\tbootargs-override = \"console=ttyS0,115200 ubi.mtd=3,2048\";\n\t};\n\n\tmemory {\n\t\tdevice_type = \"memory\";\n\t};\n\n\tlbc: localbus@ffe05000 {\n\t\treg = <0 0xffe05000 0 0x1000>;\n\t\tranges = <0x0 0x0 0x0 0xec000000 0x04000000\n\t\t\t  0x1 0x0 0x0 0xff800000 0x00040000\n\t\t\t  0x2 0x0 0x0 0xffa00000 0x00020000\n\t\t\t  0x3 0x0 0x0 0xffb00000 0x00020000>;\n\n\t\tnand@1,0 {\n\t\t\tcompatible = \"fsl,p1020-fcm-nand\", \"fsl,elbc-fcm-nand\";\n\t\t\treg = <0x1 0x0 0x40000>;\n\n\t\t\tpartitions {\n\t\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\n\t\t\t\tpartition@0 {\n\t\t\t\t\treg = <0x0 0xa0000>;\n\t\t\t\t\tlabel = \"uboot\";\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\tpartition@a0000 {\n\t\t\t\t\treg = <0xa0000 0x20000>;\n\t\t\t\t\tlabel = \"uboot-env0\";\n\t\t\t\t};\n\n\t\t\t\tpartition@c0000 {\n\t\t\t\t\treg = <0xc0000 0x40000>;\n\t\t\t\t\tlabel = \"uboot-env1\";\n\t\t\t\t};\n\n\t\t\t\tpartition@100000 {\n\t\t\t\t\treg = <0x100000 0xff00000>;\n\t\t\t\t\tlabel = \"ubi\";\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t};\n\n\tsoc: soc@ffe00000 {\n\t\tranges = <0x0 0x0 0xffe00000 0x100000>;\n\n\t\ti2c@3000 {\n\t\t\trtc@68 {\n\t\t\t\tcompatible = \"dallas,ds1339\";\n\t\t\t\treg = <0x68>;\n\t\t\t};\n\t\t};\n\n\t\tgpio0: gpio-controller@fc00 {\n\t\t};\n\n\t\tmdio@24000 {\n\t\t\tphy0: ethernet-phy@8 {\n\t\t\t\treg = <0x8>;\n\t\t\t};\n\n\t\t\tphy1: ethernet-phy@9 {\n\t\t\t\treg = <0x9>;\n\t\t\t};\n\n\t\t\tswitch0: ethernet-phy@0 {\n\t\t\t\treg = <0x0>;\n\n\t\t\t\tports {\n\t\t\t\t\t#address-cells = <1>;\n\t\t\t\t\t#size-cells = <0>;\n\n\t\t\t\t\tport@0 {\n\t\t\t\t\t\treg = <0>;\n\t\t\t\t\t\tlabel = \"lan1\";\n\t\t\t\t\t};\n\n\t\t\t\t\tport@1 {\n\t\t\t\t\t\treg = <1>;\n\t\t\t\t\t\tlabel = \"lan2\";\n\t\t\t\t\t};\n\n\t\t\t\t\tport@2 {\n\t\t\t\t\t\treg = <2>;\n\t\t\t\t\t\tlabel = \"lan3\";\n\t\t\t\t\t};\n\n\t\t\t\t\tport@3 {\n\t\t\t\t\t\treg = <3>;\n\t\t\t\t\t\tlabel = \"lan4\";\n\t\t\t\t\t};\n\n\t\t\t\t\tport@4 {\n\t\t\t\t\t\treg = <4>;\n\t\t\t\t\t\tlabel = \"lan5\";\n\t\t\t\t\t};\n\n\t\t\t\t\tport@5 {\n\t\t\t\t\t\treg = <5>;\n\t\t\t\t\t\tlabel = \"lan6\";\n\t\t\t\t\t};\n\n\t\t\t\t\tport@6 {\n\t\t\t\t\t\treg = <6>;\n\t\t\t\t\t\tlabel = \"lan7\";\n\t\t\t\t\t};\n\n\t\t\t\t\tport@7 {\n\t\t\t\t\t\treg = <7>;\n\t\t\t\t\t\tlabel = \"lan8\";\n\t\t\t\t\t};\n\n\t\t\t\t\tport@8 {\n\t\t\t\t\t\treg = <8>;\n\t\t\t\t\t\tlabel = \"cpu\";\n\n\t\t\t\t\t\tfixed-link {\n\t\t\t\t\t\t\tspeed = <1000>;\n\t\t\t\t\t\t\tfull-duplex;\n\t\t\t\t\t\t};\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tmdio@25000 {\n\t\t\ttbi_phy0: tbi-phy@11 {\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t};\n\n\t\tmdio@26000 {\n\t\t\ttbi_phy1: tbi-phy@11 {\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t};\n\n\t\tenet0: ethernet@b0000 {\n\t\t\tphy-connection-type = \"rgmii-id\";\n\t\t\tphy-handle = <&switch0>;\n\n\t\t\tfixed-link {\n\t\t\t\tspeed = <1000>;\n\t\t\t\tfull-duplex;\n\t\t\t};\n\t\t};\n\n\t\tenet1: ethernet@b1000 {\n\t\t\tphy-connection-type = \"sgmii\";\n\t\t\tphy-handle = <&phy0>;\n\n\t\t\ttbi-handle = <&tbi_phy0>;\n\t\t};\n\n\t\tenet2: ethernet@b2000 {\n\t\t\tphy-connection-type = \"sgmii\";\n\t\t\tphy-handle = <&phy1>;\n\n\t\t\ttbi-handle = <&tbi_phy1>;\n\t\t};\n\n\t\tusb@22000 {\n\t\t\tphy_type = \"ulpi\";\n\t\t\tdr_mode = \"host\";\n\t\t};\n\n\t\tusb@23000 {\n\t\t\tstatus = \"disabled\";\n\t\t};\n\t};\n\n\tpci0: pcie@ffe09000 {\n\t\tranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000\n\t\t\t  0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;\n\t\treg = <0 0xffe09000 0 0x1000>;\n\t\tpcie@0 {\n\t\t\tranges = <0x2000000 0x0 0xa0000000\n\t\t\t\t  0x2000000 0x0 0xa0000000\n\t\t\t\t  0x0 0x20000000\n\n\t\t\t\t  0x1000000 0x0 0x0\n\t\t\t\t  0x1000000 0x0 0x0\n\t\t\t\t  0x0 0x100000>;\n\t\t};\n\t};\n\n\tpci1: pcie@ffe0a000 {\n\t\treg = <0 0xffe0a000 0 0x1000>;\n\t\tranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000\n\t\t\t  0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;\n\t\tpcie@0 {\n\t\t\tranges = <0x2000000 0x0 0x80000000\n\t\t\t\t  0x2000000 0x0 0x80000000\n\t\t\t\t  0x0 0x20000000\n\n\t\t\t\t  0x1000000 0x0 0x0\n\t\t\t\t  0x1000000 0x0 0x0\n\t\t\t\t  0x0 0x100000>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tpower {\n\t\t\tgpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;\n\t\t\tlabel = \"panda:green:power\";\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\twlan0 {\n\t\t\tgpios = <&gpio0 3 GPIO_ACTIVE_HIGH>;\n\t\t\tlabel = \"panda:yellow:wlan0\";\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\twlan1 {\n\t\t\tgpios = <&gpio0 2 GPIO_ACTIVE_HIGH>;\n\t\t\tlabel = \"panda:red:wlan1\";\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\n\t\ttbd_orange {\n\t\t\tgpios = <&gpio0 1 GPIO_ACTIVE_HIGH>;\n\t\t\tlabel = \"panda:orange:tbd\";\n\t\t};\n\n\t\tsystem_blue: system {\n\t\t\tgpios = <&gpio0 4 GPIO_ACTIVE_HIGH>;\n\t\t\tlabel = \"panda:blue:system\";\n\t\t};\n\t};\n\n\tbuttons {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"Reset button\";\n\t\t\tgpios = <&gpio0 6 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n};\n/include/ \"fsl/p1020si-post.dtsi\"\n"
  },
  {
    "path": "target/linux/mpc85xx/files/arch/powerpc/boot/dts/red-15w-rev1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later or MIT\n\n#include <dt-bindings/gpio/gpio.h>\n\n/include/ \"fsl/p1010si-pre.dtsi\"\n\n/ {\n\tmodel = \"Sophos RED 15w Rev.1\";\n\tcompatible = \"sophos,red-15w-rev1\";\n\n\taliases {\n\t\tled-boot = &system_green;\n\t\tled-failsafe = &system_red;\n\t\tled-running = &system_green;\n\t\tled-upgrade = &system_red;\n\t};\n\n\tmemory {\n\t\tdevice_type = \"memory\";\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tsystem_green: system_green {\n\t\t\tgpios = <&gpio0 7 GPIO_ACTIVE_HIGH>;\n\t\t\tlabel = \"red-15w-rev1:green:system\";\n\t\t};\n\n\t\tsystem_red: system_red {\n\t\t\tgpios = <&gpio0 3 GPIO_ACTIVE_HIGH>;\n\t\t\tlabel = \"red-15w-rev1:red:system\";\n\t\t};\n\n\t\trouter {\n\t\t\tgpios = <&gpio0 5 GPIO_ACTIVE_LOW>;\n\t\t\tlabel = \"red-15w-rev1:green:router\";\n\t\t};\n\n\t\tinternet {\n\t\t\tgpios = <&gpio0 4 GPIO_ACTIVE_LOW>;\n\t\t\tlabel = \"red-15w-rev1:green:internet\";\n\t\t};\n\n\t\ttunnel {\n\t\t\tgpios = <&gpio0 8 GPIO_ACTIVE_LOW>;\n\t\t\tlabel = \"red-15w-rev1:green:tunnel\";\n\t\t};\n\t};\n\n\tsoc: soc@ffe00000 {\n\t\tranges = <0x0 0x0 0xffe00000 0x100000>;\n\n\t\ti2c@3000 {\n\t\t\teeprom@50 {\n\t\t\t\tcompatible = \"st,24c256\";\n\t\t\t\treg = <0x50>;\n\t\t\t};\n\t\t};\n\n\t\ti2c@3100 {\n\t\t\teeprom@52 {\n\t\t\t\tcompatible = \"atmel,24c01\";\n\t\t\t\treg = < 0x52 >;\n\t\t\t};\n\t\t};\n\n\t\tgpio0: gpio-controller@fc00 {\n\t\t};\n\n\t\tusb@22000 {\n\t\t\tphy_type = \"utmi\";\n\t\t\tdr_mode = \"host\";\n\t\t};\n\n\t\tmdio@24000 {\n\t\t\tphy0: ethernet-phy@0 {\n\t\t\t\treg = <0x0>;\n\t\t\t};\n\t\t};\n\n\t\tmdio@25000 {\n\t\t\ttbi_phy: tbi-phy@11 {\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t};\n\n\t\tmdio@26000 {\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tenet0: ethernet@b0000 {\n\t\t\tphy-connection-type = \"rgmii-id\";\n\n\t\t\tfixed-link {\n\t\t\t\tspeed = <1000>;\n\t\t\t\tfull-duplex;\n\t\t\t};\n\t\t};\n\n\t\tenet1: ethernet@b1000 {\n\t\t\tphy-handle = <&phy0>;\n\t\t\tphy-connection-type = \"sgmii\";\n\n\t\t\ttbi-handle = <&tbi_phy>;\n\t\t};\n\n\t\tenet2: ethernet@b2000 {\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tsdhc@2e000 {\n\t\t\tstatus = \"disabled\";\n\t\t};\n\t};\n\n\tifc: ifc@ffe1e000 {\n\t\treg = <0x0 0xffe1e000 0 0x2000>;\n\n\t\t/* NOR, NAND Flashes and CPLD on board */\n\t\tranges = <0x0 0x0 0x0 0xee000000 0x02000000\n\t\t\t0x1 0x0 0x0 0xff800000 0x00010000\n\t\t\t0x3 0x0 0x0 0xffb00000 0x00000020>;\n\n\t\tnand@1,0 {\n\t\t\tcompatible = \"fsl,ifc-nand\";\n\t\t\treg = <0x1 0x0 0x10000>;\n\n\t\t\tpartitions {\n\t\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\n\t\t\t\t/*\n\t\t\t\t * Original partition layout:\n\t\t\t\t * 0x000000000000-0x000000100000 : \"NAND U-Boot Image\"\n\t\t\t\t * 0x000000100000-0x000000200000 : \"NAND U-Boot Environment\"\n\t\t\t\t * 0x000000200000-0x000000300000 : \"Provisioning\"\n\t\t\t\t *  - OS-Image 1\n\t\t\t\t * 0x000000300000-0x000000400000 : \"fdt1\"\n\t\t\t\t * 0x000000400000-0x000000c00000 : \"uimage1\"\n\t\t\t\t * 0x000000c00000-0x000001c00000 : \"rootfs1\"\n\t\t\t\t *  - OS-Image 2\n\t\t\t\t * 0x000001c00000-0x000001d00000 : \"fdt2\"\n\t\t\t\t * 0x000001d00000-0x000002500000 : \"uimage2\"\n\t\t\t\t * 0x000002500000-0x000003500000 : \"rootfs2\"\n\t\t\t\t *  - Empty\n\t\t\t\t * 0x000003500000-0x000008000000 : \"data\"\n\t\t\t\t */\n\n\t\t\t\tpartition@0 {\n\t\t\t\t\treg = <0x0 0x100000>;\n\t\t\t\t\tlabel = \"u-boot\";\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\tpartition@100000 {\n\t\t\t\t\treg = <0x100000 0x100000>;\n\t\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\t};\n\n\t\t\t\tpartition@200000 {\n\t\t\t\t\treg = <0x200000 0x100000>;\n\t\t\t\t\tlabel = \"provisioning\";\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\tpartition@300000 {\n\t\t\t\t\treg = <0x300000 0x800000>;\n\t\t\t\t\tlabel = \"kernel\";\n\t\t\t\t};\n\n\t\t\t\tpartition@b00000 {\n\t\t\t\t\treg = <0xb00000 0x7500000>;\n\t\t\t\t\tlabel = \"ubi\";\n\t\t\t\t};\n\n\t\t\t\toem-partition@300000 {\n\t\t\t\t\treg = <0x300000 0x1900000>;\n\t\t\t\t\tlabel = \"sophos-os1\";\n\t\t\t\t};\n\n\t\t\t\toem-partition@1c00000 {\n\t\t\t\t\treg = <0x1c00000 0x1900000>;\n\t\t\t\t\tlabel = \"sophos-os2\";\n\t\t\t\t};\n\n\t\t\t\toem-partition@3500000 {\n\t\t\t\t\treg = <0x3500000 0x4b00000>;\n\t\t\t\t\tlabel = \"sophos-data\";\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t};\n\n\tpci0: pcie@ffe09000 {\n\t\tstatus = \"disabled\";\n\t};\n\n\tpci1: pcie@ffe0a000 {\n\t\treg = <0 0xffe0a000 0 0x1000>;\n\t\tranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000\n\t\t\t  0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;\n\t\tpcie@0 {\n\t\t\tranges = <0x2000000 0x0 0x80000000\n\t\t\t\t  0x2000000 0x0 0x80000000\n\t\t\t\t  0x0 0x20000000\n\n\t\t\t\t  0x1000000 0x0 0x0\n\t\t\t\t  0x1000000 0x0 0x0\n\t\t\t\t  0x0 0x100000>;\n\t\t};\n\t};\n};\n\n/include/ \"fsl/p1010si-post.dtsi\"\n"
  },
  {
    "path": "target/linux/mpc85xx/files/arch/powerpc/boot/dts/tl-wdr4900-v1.dts",
    "content": "/*\n * TP-Link TL-WDR4900 v1 Device Tree Source\n *\n * Copyright 2013 Gabor Juhos <juhosg@openwrt.org>\n *\n * This program is free software; you can redistribute  it and/or modify it\n * under  the terms of  the GNU General  Public License as published by the\n * Free Software Foundation;  either version 2 of the  License, or (at your\n * option) any later version.\n */\n\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/gpio/gpio.h>\n\n/include/ \"fsl/p1010si-pre.dtsi\"\n\n/ {\n\tmodel = \"TP-Link TL-WDR4900 v1\";\n\tcompatible = \"tplink,tl-wdr4900-v1\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200\";\n/*\n\t\tstdout-path = \"/soc@ffe00000/serial@4500\";\n*/\n\t};\n\n\taliases {\n\t\tspi0 = &spi0;\n\t\tled-boot = &system_green;\n\t\tled-failsafe = &system_green;\n\t\tled-running = &system_green;\n\t\tled-upgrade = &system_green;\n\t\tlabel-mac-device = &enet0;\n\t};\n\n\tmemory {\n\t\tdevice_type = \"memory\";\n\t};\n\n\tsoc: soc@ffe00000 {\n\t\tranges = <0x0 0x0 0xffe00000 0x100000>;\n\n\t\tspi0: spi@7000 {\n\t\t\tflash@0 {\n\t\t\t\tcompatible = \"jedec,spi-nor\";\n\t\t\t\treg = <0>;\n\t\t\t\tspi-max-frequency = <25000000>;\n\n\t\t\t\tpartitions {\n\t\t\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t\t\t#address-cells = <1>;\n\t\t\t\t\t#size-cells = <1>;\n\n\t\t\t\t\tuboot: partition@0 {\n\t\t\t\t\t\treg = <0x0 0x0050000>;\n\t\t\t\t\t\tlabel = \"u-boot\";\n\t\t\t\t\t\tread-only;\n\n\t\t\t\t\t\tcompatible = \"nvmem-cells\";\n\t\t\t\t\t\t#address-cells = <1>;\n\t\t\t\t\t\t#size-cells = <1>;\n\n\t\t\t\t\t\tmacaddr_uboot_4fc00: macaddr@4fc00 {\n\t\t\t\t\t\t\treg = <0x4fc00 0x6>;\n\t\t\t\t\t\t};\n\t\t\t\t\t};\n\n\t\t\t\t\tpartition@50000 {\n\t\t\t\t\t\treg = <0x00050000 0x00010000>;\n\t\t\t\t\t\tlabel = \"dtb\";\n\t\t\t\t\t\tread-only;\n\t\t\t\t\t};\n\n\t\t\t\t\tpartition@60000 {\n\t\t\t\t\t\tcompatible = \"tplink,firmware\";\n\t\t\t\t\t\treg = <0x00060000 0x00f80000>;\n\t\t\t\t\t\tlabel = \"firmware\";\n\t\t\t\t\t};\n\n\t\t\t\t\tpartition@fe0000 {\n\t\t\t\t\t\treg = <0x00fe0000 0x00010000>;\n\t\t\t\t\t\tlabel = \"config\";\n\t\t\t\t\t\tread-only;\n\t\t\t\t\t};\n\n\t\t\t\t\tpartition@ff0000 {\n\t\t\t\t\t\treg = <0x00ff0000 0x00010000>;\n\t\t\t\t\t\tlabel = \"caldata\";\n\t\t\t\t\t\tread-only;\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tgpio0: gpio-controller@fc00 {\n\t\t};\n\n\t\tusb@22000 {\n\t\t\tphy_type = \"utmi\";\n\t\t\tdr_mode = \"host\";\n\t\t};\n\n\t\tmdio@24000 {\n\t\t\tphy0: ethernet-phy@0 {\n\t\t\t\treg = <0x0>;\n\t\t\t\tqca,ar8327-initvals = <\n\t\t\t\t\t0x00004 0x07600000 /* PAD0_MODE */\n\t\t\t\t\t0x00008 0x00000000 /* PAD5_MODE */\n\t\t\t\t\t0x0000c 0x01000000 /* PAD6_MODE */\n\t\t\t\t\t0x00010 0x40000000 /* POWER_ON_STRAP */\n\t\t\t\t\t0x00050 0xcf35cf35 /* LED_CTRL0 */\n\t\t\t\t\t0x00054 0xcf35cf35 /* LED_CTRL1 */\n\t\t\t\t\t0x00058 0xcf35cf35 /* LED_CTRL2 */\n\t\t\t\t\t0x0005c 0x03ffff00 /* LED_CTRL3 */\n\t\t\t\t\t0x0007c 0x0000007e /* PORT0_STATUS */\n\t\t\t\t\t0x00094 0x00000200 /* PORT6_STATUS */\n\t\t\t\t>;\n\t\t\t};\n\t\t};\n\n\t\tmdio@25000 {\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tmdio@26000 {\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tenet0: ethernet@b0000 {\n\t\t\tphy-handle = <&phy0>;\n\t\t\tphy-connection-type = \"rgmii-id\";\n\t\t\tnvmem-cells = <&macaddr_uboot_4fc00>;\n\t\t\tnvmem-cell-names = \"mac-address\";\n\t\t};\n\n\t\tenet1: ethernet@b1000 {\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tenet2: ethernet@b2000 {\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tsdhc@2e000 {\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tserial1: serial@4600 {\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tcan0: can@1c000 {\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tcan1: can@1d000 {\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tptp_clock@b0e00 {\n\t\t\tcompatible = \"fsl,etsec-ptp\";\n\t\t\treg = <0xb0e00 0xb0>;\n\t\t\tinterrupts = <68 2 0 0 69 2 0 0 70 2 0 0>;\n\t\t\tfsl,cksel       = <1>;\n\t\t\tfsl,tclk-period\t= <5>;\n\t\t\tfsl,tmr-prsc\t= <2>;\n\t\t\tfsl,tmr-add\t= <0xcccccccd>;\n\t\t\tfsl,tmr-fiper1\t= <0x3b9ac9fb>; /* 1PPS */\n\t\t\tfsl,tmr-fiper2\t= <0x00018696>;\n\t\t\tfsl,max-adj\t= <249999999>;\n\t\t};\n\t};\n\n\tpci0: pcie@ffe09000 {\n\t\treg = <0 0xffe09000 0 0x1000>;\n\t\tranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000\n\t\t\t  0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;\n\t\tpcie@0 {\n\t\t\tranges = <0x2000000 0x0 0xa0000000\n\t\t\t\t  0x2000000 0x0 0xa0000000\n\t\t\t\t  0x0 0x20000000\n\n\t\t\t\t  0x1000000 0x0 0x0\n\t\t\t\t  0x1000000 0x0 0x0\n\t\t\t\t  0x0 0x100000>;\n\t\t};\n\t};\n\n\tpci1: pcie@ffe0a000 {\n\t\treg = <0 0xffe0a000 0 0x1000>;\n\t\tranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000\n\t\t\t  0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;\n\t\tpcie@0 {\n\t\t\tranges = <0x2000000 0x0 0x80000000\n\t\t\t\t  0x2000000 0x0 0x80000000\n\t\t\t\t  0x0 0x20000000\n\n\t\t\t\t  0x1000000 0x0 0x0\n\t\t\t\t  0x1000000 0x0 0x0\n\t\t\t\t  0x0 0x100000>;\n\t\t};\n\t};\n\n\tifc: ifc@ffe1e000 {\n\t\tstatus = \"disabled\";\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tsystem_green: system {\n\t\t\tgpios = <&gpio0 2 GPIO_ACTIVE_LOW>;\n\t\t\tlabel = \"tp-link:blue:system\";\n\t\t};\n\n\t\tusb1 {\n\t\t\tgpios = <&gpio0 3 GPIO_ACTIVE_LOW>;\n\t\t\tlabel = \"tp-link:green:usb1\";\n\t\t};\n\n\t\tusb2 {\n\t\t\tgpios = <&gpio0 4 GPIO_ACTIVE_LOW>;\n\t\t\tlabel = \"tp-link:green:usb2\";\n\t\t};\n\n\t\tusbpower {\n\t\t\tgpios = <&gpio0 10 GPIO_ACTIVE_LOW>;\n\t\t\tlabel = \"tp-link:usb:power\";\n\t\t};\n\t};\n\n\tbuttons {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"Reset button\";\n\t\t\tgpios = <&gpio0 5 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\trfkill {\n\t\t\tlabel = \"RFKILL switch\";\n\t\t\tgpios = <&gpio0 11 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RFKILL>;\n\t\t};\n\t};\n};\n\n/include/ \"fsl/p1010si-post.dtsi\"\n\n/ {\n\tcpus {\n\t\tPowerPC,P1010@0 {\n\t\t\tbus-frequency = <399999996>;\n\t\t\ttimebase-frequency = <49999999>;\n\t\t\tclock-frequency = <799999992>;\n\t\t};\n\t};\n\n\tmemory {\n\t\treg = <0x0 0x0 0x0 0x8000000>;\n\t};\n\n\tsoc@ffe00000 {\n\t\tbus-frequency = <399999996>;\n\n\t\tserial@4600 {\n\t\t\tclock-frequency = <399999996>;\n\t\t};\n\n\t\tserial@4500 {\n\t\t\tclock-frequency = <399999996>;\n\t\t};\n\n\t\tpic@40000 {\n\t\t\tclock-frequency = <399999996>;\n\t\t};\n\t};\n};\n\n/*\n * The TL-WDR4900 v1 uses the NXP (Freescale) P1014 SoC which is closely\n * related to the P1010.\n *\n * NXP QP1010FS.pdf \"QorIQ P1010 and P1014 Communications Processors\"\n * datasheet states that the P1014 does not include the accelerated crypto\n * module (CAAM/SEC4) which is present in the P1010.\n *\n * NXP Appliation Note AN4938 Rev. 2 implies that some P1014 may contain the\n * SEC4 module, but states that SoCs with System Version Register values\n * 0x80F10110 or 0x80F10120 do not have the security feature.\n *\n * All v1.3 TL-WDR4900 tested have SVR == 0x80F10110 which AN4938 describes\n * as: core rev 1.0, \"P1014 (without security)\".\n *\n * The SVR value is reported by uboot on the serial console.\n */\n\n/ {\n\tsoc: soc@ffe00000 {\n\t\t/delete-node/ crypto@30000; /* Pulled in by p1010si-post */\n\t};\n};\n"
  },
  {
    "path": "target/linux/mpc85xx/files/arch/powerpc/boot/dts/ws-ap3710i.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later or MIT\n\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/gpio/gpio.h>\n\n/include/ \"fsl/p1020si-pre.dtsi\"\n/ {\n\tmodel = \"Enterasys WS-AP3710i\";\n\tcompatible = \"enterasys,ws-ap3710i\";\n\n\taliases {\n\t\tled-boot = &led_power_green;\n\t\tled-failsafe = &led_power_red;\n\t\tled-running = &led_power_green;\n\t\tled-upgrade = &led_power_red;\n\t\tlabel-mac-device = &enet0;\n\t};\n\n\tmemory {\n\t\tdevice_type = \"memory\";\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twifi1 {\n\t\t\tgpios = <&gpio0 3 GPIO_ACTIVE_HIGH>;\n\t\t\tlabel = \"ws-ap3710i:green:radio1\";\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\twifi2 {\n\t\t\tgpios = <&gpio0 4 GPIO_ACTIVE_HIGH>;\n\t\t\tlabel = \"ws-ap3710i:green:radio2\";\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\n\t\tled_power_green: power_green {\n\t\t\tgpios = <&gpio0 8 GPIO_ACTIVE_HIGH>;\n\t\t\tlabel = \"ws-ap3710i:green:power\";\n\t\t};\n\n\t\tled_power_red: power_red {\n\t\t\tgpios = <&gpio0 9 GPIO_ACTIVE_HIGH>;\n\t\t\tlabel = \"ws-ap3710i:red:power\";\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"Reset button\";\n\t\t\tgpios = <&gpio0 1 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tlbc: localbus@ffe05000 {\n\t\treg = <0 0xffe05000 0 0x1000>;\n\t\tranges = <0x0 0x0 0x0 0xee000000 0x2000000>;\n\n\t\tnor@0,0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\t\t\tcompatible = \"cfi-flash\";\n\t\t\treg = <0x0 0x0 0x2000000>;\n\t\t\tbank-width = <2>;\n\t\t\tdevice-width = <1>;\n\n\t\t\tpartitions {\n\t\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\n\t\t\t\tpartition@0 {\n\t\t\t\t\tcompatible = \"denx,fit\";\n\t\t\t\t\treg = <0x0 0x1d80000>;\n\t\t\t\t\tlabel = \"firmware\";\n\t\t\t\t};\n\n\t\t\t\tpartition@1d80000 {\n\t\t\t\t\treg = <0x1d80000 0x80000>;\n\t\t\t\t\tlabel = \"u-boot\";\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\tpartition@1e00000 {\n\t\t\t\t\treg = <0x1e00000 0x100000>;\n\t\t\t\t\tlabel = \"nvram\";\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\tpartition@1f00000 {\n\t\t\t\t\treg = <0x1f00000 0x20000>;\n\t\t\t\t\tlabel = \"cfg2\";\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\tpartition@1f20000 {\n\t\t\t\t\treg = <0x1f20000 0x20000>;\n\t\t\t\t\tlabel = \"cfg1\";\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t};\n\n\tsoc: soc@ffe00000 {\n\t\tranges = <0x0 0x0 0xffe00000 0x100000>;\n\n\t\tgpio0: gpio-controller@fc00 {\n\t\t};\n\n\t\tmdio@24000 {\n\t\t\tphy4: ethernet-phy@4 {\n\t\t\t\treg = <0x4>;\n\t\t\t\treset-gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;\n\t\t\t};\n\t\t};\n\n\t\tenet0: ethernet@b0000 {\n\t\t\tphy-connection-type = \"rgmii-id\";\n\t\t\tphy-handle = <&phy4>;\n\t\t};\n\n\t\tenet1: ethernet@b1000 {\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tenet2: ethernet@b2000 {\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tusb@22000 {\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tusb@23000 {\n\t\t\tstatus = \"disabled\";\n\t\t};\n\t};\n\n\tpci0: pcie@ffe09000 {\n\t\tranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000\n\t\t\t  0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;\n\t\treg = <0 0xffe09000 0 0x1000>;\n\t\tpcie@0 {\n\t\t\tranges = <0x2000000 0x0 0xa0000000\n\t\t\t\t  0x2000000 0x0 0xa0000000\n\t\t\t\t  0x0 0x20000000\n\n\t\t\t\t  0x1000000 0x0 0x0\n\t\t\t\t  0x1000000 0x0 0x0\n\t\t\t\t  0x0 0x100000>;\n\t\t};\n\t};\n\n\tpci1: pcie@ffe0a000 {\n\t\treg = <0 0xffe0a000 0 0x1000>;\n\t\tranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000\n\t\t\t  0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;\n\t\tpcie@0 {\n\t\t\tranges = <0x2000000 0x0 0x80000000\n\t\t\t\t  0x2000000 0x0 0x80000000\n\t\t\t\t  0x0 0x20000000\n\n\t\t\t\t  0x1000000 0x0 0x0\n\t\t\t\t  0x1000000 0x0 0x0\n\t\t\t\t  0x0 0x100000>;\n\t\t};\n\t};\n\n};\n/include/ \"fsl/p1020si-post.dtsi\"\n"
  },
  {
    "path": "target/linux/mpc85xx/files/arch/powerpc/boot/dts/ws-ap3825i.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later or MIT\n\n/include/ \"fsl/p1020si-pre.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"Extreme Networks WS-AP3825i\";\n\tcompatible = \"extreme-networks,ws-ap3825i\";\n\n\taliases {\n\t\tethernet0 = &enet0;\n\t\tethernet1 = &enet2;\n\t\tled-boot = &led_power_green;\n\t\tled-failsafe = &led_power_red;\n\t\tled-running = &led_power_green;\n\t\tled-upgrade = &led_power_red;\n\t};\n\n\tchosen {\n\t\tbootargs-override = \"console=ttyS0,115200\";\n\t};\n\n\tmemory {\n\t\tdevice_type = \"memory\";\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twifi1 {\n\t\t\tgpios = <&spi_gpio 3 GPIO_ACTIVE_HIGH>;\n\t\t\tlabel = \"green:radio1\";\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\twifi2 {\n\t\t\tgpios = <&spi_gpio 2 GPIO_ACTIVE_HIGH>;\n\t\t\tlabel = \"green:radio2\";\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\n\t\tled_power_green: power_green {\n\t\t\tgpios = <&spi_gpio 0 GPIO_ACTIVE_HIGH>;\n\t\t\tlabel = \"green:power\";\n\t\t};\n\n\t\tled_power_red: power_red {\n\t\t\tgpios = <&spi_gpio 1 GPIO_ACTIVE_HIGH>;\n\t\t\tlabel = \"red:power\";\n\t\t};\n\n\t\tlan1_red {\n\t\t\tgpios = <&spi_gpio 6 GPIO_ACTIVE_HIGH>;\n\t\t\tlabel = \"red:lan1\";\n\t\t};\n\n\t\tlan1_green {\n\t\t\tgpios = <&spi_gpio 4 GPIO_ACTIVE_HIGH>;\n\t\t\tlabel = \"green:lan1\";\n\t\t};\n\n\t\tlan2_red {\n\t\t\tgpios = <&spi_gpio 7 GPIO_ACTIVE_HIGH>;\n\t\t\tlabel = \"red:lan2\";\n\t\t};\n\n\t\tlan2_green {\n\t\t\tgpios = <&spi_gpio 5 GPIO_ACTIVE_HIGH>;\n\t\t\tlabel = \"green:lan2\";\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"Reset button\";\n\t\t\tgpios = <&gpio0 8 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tlbc: localbus@ffe05000 {\n\t\treg = <0 0xffe05000 0 0x1000>;\n\t\tranges = <0x0 0x0 0x0 0xec000000 0x4000000>;\n\n\t\tnor@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\t\t\tcompatible = \"cfi-flash\";\n\t\t\treg = <0x0 0x0 0x4000000>;\n\t\t\tbank-width = <2>;\n\t\t\tdevice-width = <1>;\n\n\t\t\tpartitions {\n\t\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\n\t\t\t\tpartition@0 {\n\t\t\t\t\tcompatible = \"denx,fit\";\n\t\t\t\t\treg = <0x0 0x3d60000>;\n\t\t\t\t\tlabel = \"firmware\";\n\t\t\t\t};\n\n\t\t\t\tpartition@3d60000 {\n\t\t\t\t\treg = <0x3d60000 0x20000>;\n\t\t\t\t\tlabel = \"calib\";\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\tpartition@3d80000{\n\t\t\t\t\treg = <0x3d80000 0x80000>;\n\t\t\t\t\tlabel = \"u-boot\";\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\tpartition@3e00000{\n\t\t\t\t\treg = <0x3e00000 0x100000>;\n\t\t\t\t\tlabel = \"nvram\";\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\tpartition@3f00000 {\n\t\t\t\t\treg = <0x3f00000 0x20000>;\n\t\t\t\t\tlabel = \"cfg2\";\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\tpartition@3f20000 {\n\t\t\t\t\treg = <0x3f20000 0x20000>;\n\t\t\t\t\tlabel = \"cfg1\";\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t};\n\n\tsoc: soc@ffe00000 {\n\t\tranges = <0x0 0x0 0xffe00000 0x100000>;\n\n\t\tgpio0: gpio-controller@fc00 {\n\t\t};\n\n\t\tmdio@24000 {\n\t\t\tphy0: ethernet-phy@0 {\n\t\t\t\tinterrupts = <3 1 0 0>;\n\t\t\t\treg = <0x5>;\n\t\t\t\treset-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;\n\t\t\t\treset-assert-us = <10000>;\n\t\t\t\treset-deassert-us = <10000>;\n\t\t\t};\n\n\t\t\tphy2: ethernet-phy@2 {\n\t\t\t\tinterrupts = <1 1 0 0>;\n\t\t\t\treg = <0x6>;\n\t\t\t\treset-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;\n\t\t\t\treset-assert-us = <10000>;\n\t\t\t\treset-deassert-us = <10000>;\n\t\t\t};\n\t\t};\n\n\t\tmdio@25000 {\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tmdio@26000 {\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tenet0: ethernet@b0000 {\n\t\t\tstatus = \"okay\";\n\t\t\tphy-handle = <&phy0>;\n\t\t\tphy-connection-type = \"rgmii-id\";\n\t\t};\n\n\t\tenet1: ethernet@b1000 {\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tenet2: ethernet@b2000 {\n\t\t\tstatus = \"okay\";\n\t\t\tphy-handle = <&phy2>;\n\t\t\tphy-connection-type = \"rgmii-id\";\n\t\t};\n\n\t\tusb@22000 {\n\t\t\tphy_type = \"ulpi\";\n\t\t\tdr_mode = \"host\";\n\t\t};\n\n\t\tusb@23000 {\n\t\t\tstatus = \"disabled\";\n\t\t};\n\t};\n\n\tpci0: pcie@ffe09000 {\n\t\tranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000\n\t\t\t  0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;\n\t\treg = <0 0xffe09000 0 0x1000>;\n\t\tpcie@0 {\n\t\t\tranges = <0x2000000 0x0 0xa0000000\n\t\t\t\t  0x2000000 0x0 0xa0000000\n\t\t\t\t  0x0 0x20000000\n\n\t\t\t\t  0x1000000 0x0 0x0\n\t\t\t\t  0x1000000 0x0 0x0\n\t\t\t\t  0x0 0x100000>;\n\t\t};\n\t};\n\n\tpci1: pcie@ffe0a000 {\n\t\treg = <0 0xffe0a000 0 0x1000>;\n\t\tranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000\n\t\t\t  0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;\n\t\tpcie@0 {\n\t\t\tranges = <0x2000000 0x0 0x80000000\n\t\t\t\t  0x2000000 0x0 0x80000000\n\t\t\t\t  0x0 0x20000000\n\n\t\t\t\t  0x1000000 0x0 0x0\n\t\t\t\t  0x1000000 0x0 0x0\n\t\t\t\t  0x0 0x100000>;\n\t\t};\n\t};\n};\n\n&soc {\n\tled_spi {\n\t\t/*\n\t\t * This is currently non-functioning because the spi-gpio\n\t\t * driver refuses to register when presented with this node.\n\t\t */\n\t\tcompatible = \"spi-gpio\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tsck-gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;\n\t\tmosi-gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>;\n\t\tnum-chipselects = <0>;\n\n\t\tspi_gpio: led_gpio@0 {\n\t\t\tcompatible = \"fairchild,74hc595\";\n\t\t\treg = <0>;\n\t\t\tgpio-controller;\n\t\t\t#gpio-cells = <2>;\n\t\t\tregisters-number = <1>;\n\t\t\tspi-max-frequency = <100000>;\n\t\t};\n\t};\n};\n\n/include/ \"fsl/p1020si-post.dtsi\"\n"
  },
  {
    "path": "target/linux/mpc85xx/files/arch/powerpc/platforms/85xx/hiveap-330.c",
    "content": "/*\n * Aerohive HiveAP-330 Board Setup\n *\n * Copyright (C) 2017 Chris Blake <chrisrblake93@gmail.com>\n *\n * Based on:\n *   mpc85xx_rdb.c:\n *      MPC85xx RDB Board Setup\n *      Copyright 2013 Freescale Semiconductor Inc.\n *\n * This program is free software; you can redistribute  it and/or modify it\n * under  the terms of  the GNU General  Public License as published by the\n * Free Software Foundation;  either version 2 of the  License, or (at your\n * option) any later version.\n */\n\n#include <linux/stddef.h>\n#include <linux/kernel.h>\n#include <linux/delay.h>\n#include <linux/interrupt.h>\n#include <linux/of_platform.h>\n\n#include <asm/time.h>\n#include <asm/machdep.h>\n#include <asm/pci-bridge.h>\n#include <mm/mmu_decl.h>\n#include <asm/prom.h>\n#include <asm/udbg.h>\n#include <asm/mpic.h>\n\n#include <sysdev/fsl_soc.h>\n#include <sysdev/fsl_pci.h>\n#include \"smp.h\"\n\n#include \"mpc85xx.h\"\n\nvoid __init hiveap_330_pic_init(void)\n{\n\tstruct mpic *mpic;\n\n\tmpic = mpic_alloc(NULL, 0,\n\t  MPIC_BIG_ENDIAN |\n\t  MPIC_SINGLE_DEST_CPU,\n\t  0, 256, \" OpenPIC  \");\n\n\tBUG_ON(mpic == NULL);\n\tmpic_init(mpic);\n}\n\n/*\n * Setup the architecture\n */\nstatic void __init hiveap_330_setup_arch(void)\n{\n\tif (ppc_md.progress)\n\t\tppc_md.progress(\"hiveap_330_setup_arch()\", 0);\n\n\tmpc85xx_smp_init();\n\n\tfsl_pci_assign_primary();\n\n\tprintk(KERN_INFO \"HiveAP-330 board from Aerohive\\n\");\n}\n\nmachine_arch_initcall(hiveap_330, mpc85xx_common_publish_devices);\n\n/*\n * Called very early, device-tree isn't unflattened\n */\nstatic int __init hiveap_330_probe(void)\n{\n\tif (of_machine_is_compatible(\"aerohive,hiveap-330\"))\n\t\treturn 1;\n\treturn 0;\n}\n\ndefine_machine(hiveap_330) {\n\t.name\t\t\t= \"P1020 RDB\",\n\t.probe\t\t\t= hiveap_330_probe,\n\t.setup_arch\t\t= hiveap_330_setup_arch,\n\t.init_IRQ\t\t= hiveap_330_pic_init,\n#ifdef CONFIG_PCI\n\t.pcibios_fixup_bus\t= fsl_pcibios_fixup_bus,\n\t.pcibios_fixup_phb      = fsl_pcibios_fixup_phb,\n#endif\n\t.get_irq\t\t= mpic_get_irq,\n\t.calibrate_decr\t\t= generic_calibrate_decr,\n\t.progress\t\t= udbg_progress,\n};\n"
  },
  {
    "path": "target/linux/mpc85xx/files/arch/powerpc/platforms/85xx/panda.c",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later\n\n/*\n * OCEDO Panda Board Setup\n *\n * Copyright (C) 2019 David Bauer <mail@david-bauer.net>\n *\n * Based on:\n *   mpc85xx_rdb.c:\n *      MPC85xx RDB Board Setup\n *      Copyright 2013 Freescale Semiconductor Inc.\n *\n * This program is free software; you can redistribute  it and/or modify it\n * under  the terms of  the GNU General  Public License as published by the\n * Free Software Foundation;  either version 2 of the  License, or (at your\n * option) any later version.\n */\n\n#include <linux/stddef.h>\n#include <linux/kernel.h>\n#include <linux/delay.h>\n#include <linux/interrupt.h>\n#include <linux/of_platform.h>\n\n#include <asm/time.h>\n#include <asm/machdep.h>\n#include <asm/pci-bridge.h>\n#include <mm/mmu_decl.h>\n#include <asm/prom.h>\n#include <asm/udbg.h>\n#include <asm/mpic.h>\n\n#include <sysdev/fsl_soc.h>\n#include <sysdev/fsl_pci.h>\n#include \"smp.h\"\n\n#include \"mpc85xx.h\"\n\nvoid __init panda_pic_init(void)\n{\n\tstruct mpic *mpic;\n\n\tmpic = mpic_alloc(NULL, 0,\n\t  MPIC_BIG_ENDIAN |\n\t  MPIC_SINGLE_DEST_CPU,\n\t  0, 256, \" OpenPIC  \");\n\n\tBUG_ON(mpic == NULL);\n\tmpic_init(mpic);\n}\n\n/*\n * Setup the architecture\n */\nstatic void __init panda_setup_arch(void)\n{\n\tif (ppc_md.progress)\n\t\tppc_md.progress(\"panda_setup_arch()\", 0);\n\n\tmpc85xx_smp_init();\n\n\tfsl_pci_assign_primary();\n\n\tpr_info(\"Panda board from OCEDO\\n\");\n}\n\nmachine_arch_initcall(panda, mpc85xx_common_publish_devices);\n\n/*\n * Called very early, device-tree isn't unflattened\n */\nstatic int __init panda_probe(void)\n{\n\tif (of_machine_is_compatible(\"ocedo,panda\"))\n\t\treturn 1;\n\treturn 0;\n}\n\ndefine_machine(panda) {\n\t.name\t\t\t= \"P1020 RDB\",\n\t.probe\t\t\t= panda_probe,\n\t.setup_arch\t\t= panda_setup_arch,\n\t.init_IRQ\t\t= panda_pic_init,\n#ifdef CONFIG_PCI\n\t.pcibios_fixup_bus\t= fsl_pcibios_fixup_bus,\n\t.pcibios_fixup_phb      = fsl_pcibios_fixup_phb,\n#endif\n\t.get_irq\t\t= mpic_get_irq,\n\t.calibrate_decr\t\t= generic_calibrate_decr,\n\t.progress\t\t= udbg_progress,\n};\n"
  },
  {
    "path": "target/linux/mpc85xx/files/arch/powerpc/platforms/85xx/red15w_rev1.c",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later\n\n/*\n * Sophos RED 15w Rev.1 Board Setup\n *\n * Copyright (C) 2019 David Bauer <mail@david-bauer.net>\n *\n * Based on:\n *   p1010rdb.c:\n *      P1010 RDB Board Setup\n *      Copyright 2011 Freescale Semiconductor Inc.\n *\n * This program is free software; you can redistribute  it and/or modify it\n * under  the terms of  the GNU General  Public License as published by the\n * Free Software Foundation;  either version 2 of the  License, or (at your\n * option) any later version.\n */\n\n#include <linux/stddef.h>\n#include <linux/kernel.h>\n#include <linux/delay.h>\n#include <linux/interrupt.h>\n#include <linux/of_platform.h>\n\n#include <asm/time.h>\n#include <asm/machdep.h>\n#include <asm/pci-bridge.h>\n#include <mm/mmu_decl.h>\n#include <asm/prom.h>\n#include <asm/udbg.h>\n#include <asm/mpic.h>\n\n#include <sysdev/fsl_soc.h>\n#include <sysdev/fsl_pci.h>\n\n#include \"mpc85xx.h\"\n\nvoid __init red_15w_rev1_pic_init(void)\n{\n\tstruct mpic *mpic;\n\n\tmpic = mpic_alloc(NULL, 0,\n\t  MPIC_BIG_ENDIAN | MPIC_SINGLE_DEST_CPU,\n\t  0, 256, \" OpenPIC  \");\n\n\tBUG_ON(mpic == NULL);\n\tmpic_init(mpic);\n}\n\n/*\n * Setup the architecture\n */\nstatic void __init red_15w_rev1_setup_arch(void)\n{\n\tif (ppc_md.progress)\n\t\tppc_md.progress(\"red_15w_rev1_setup_arch()\", 0);\n\n\tfsl_pci_assign_primary();\n\n\tpr_info(\"RED 15w Rev.1 from Sophos\\n\");\n}\n\nmachine_arch_initcall(red_15w_rev1, mpc85xx_common_publish_devices);\n\n/*\n * Called very early, device-tree isn't unflattened\n */\nstatic int __init red_15w_rev1_probe(void)\n{\n\tif (of_machine_is_compatible(\"sophos,red-15w-rev1\"))\n\t\treturn 1;\n\treturn 0;\n}\n\ndefine_machine(red_15w_rev1) {\n\t.name\t\t\t= \"P1010 RDB\",\n\t.probe\t\t\t= red_15w_rev1_probe,\n\t.setup_arch\t\t= red_15w_rev1_setup_arch,\n\t.init_IRQ\t\t= red_15w_rev1_pic_init,\n#ifdef CONFIG_PCI\n\t.pcibios_fixup_bus\t= fsl_pcibios_fixup_bus,\n\t.pcibios_fixup_phb      = fsl_pcibios_fixup_phb,\n#endif\n\t.get_irq\t\t= mpic_get_irq,\n\t.calibrate_decr\t\t= generic_calibrate_decr,\n\t.progress\t\t= udbg_progress,\n};\n"
  },
  {
    "path": "target/linux/mpc85xx/files/arch/powerpc/platforms/85xx/tl_wdr4900_v1.c",
    "content": "/*\n * TL-WDR4900 v1 board setup\n *\n * Copyright (c) 2013 Gabor Juhos <juhosg@openwrt.org>\n *\n * Based on:\n *   p1010rdb.c:\n *      P1010RDB Board Setup\n *      Copyright 2011 Freescale Semiconductor Inc.\n *\n * This program is free software; you can redistribute  it and/or modify it\n * under  the terms of  the GNU General  Public License as published by the\n * Free Software Foundation;  either version 2 of the  License, or (at your\n * option) any later version.\n */\n\n#include <linux/stddef.h>\n#include <linux/kernel.h>\n#include <linux/pci.h>\n#include <linux/delay.h>\n#include <linux/interrupt.h>\n#include <linux/of_platform.h>\n#include <linux/ath9k_platform.h>\n#include <linux/leds.h>\n\n#include <asm/time.h>\n#include <asm/machdep.h>\n#include <asm/pci-bridge.h>\n#include <mm/mmu_decl.h>\n#include <asm/prom.h>\n#include <asm/udbg.h>\n#include <asm/mpic.h>\n\n#include <sysdev/fsl_soc.h>\n#include <sysdev/fsl_pci.h>\n\n#include \"mpc85xx.h\"\n\nvoid __init tl_wdr4900_v1_pic_init(void)\n{\n\tstruct mpic *mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN |\n\t  MPIC_SINGLE_DEST_CPU,\n\t  0, 256, \" OpenPIC  \");\n\n\tBUG_ON(mpic == NULL);\n\n\tmpic_init(mpic);\n}\n\n#ifdef CONFIG_PCI\nstatic struct gpio_led tl_wdr4900_v1_wmac_leds_gpio[] = {\n\t{\n\t\t.name\t\t= \"tp-link:blue:wps\",\n\t\t.gpio\t\t= 1,\n\t\t.active_low\t= 1,\n\t},\n};\n\nstatic struct ath9k_platform_data tl_wdr4900_v1_wmac0_data = {\n\t.led_pin = 0,\n\t.eeprom_name = \"pci_wmac0.eeprom\",\n\t.leds = tl_wdr4900_v1_wmac_leds_gpio,\n\t.num_leds = ARRAY_SIZE(tl_wdr4900_v1_wmac_leds_gpio),\n};\n\nstatic struct ath9k_platform_data tl_wdr4900_v1_wmac1_data = {\n\t.led_pin = 0,\n\t.eeprom_name = \"pci_wmac1.eeprom\",\n};\n\nstatic void tl_wdr4900_v1_pci_wmac_fixup(struct pci_dev *dev)\n{\n\tif (!machine_is(tl_wdr4900_v1))\n\t\treturn;\n\n\tif (dev->bus->number == 1 &&\n\t    PCI_SLOT(dev->devfn) == 0) {\n\t\tdev->dev.platform_data = &tl_wdr4900_v1_wmac0_data;\n\t\treturn;\n\t}\n\n\tif (dev->bus->number == 3 &&\n\t    PCI_SLOT(dev->devfn) == 0 &&\n\t    dev->device == 0xabcd) {\n\t\tdev->dev.platform_data = &tl_wdr4900_v1_wmac1_data;\n\n\t\t/*\n\t\t * The PCI header of the AR9381 chip is not programmed\n\t\t * correctly by the bootloader and the device uses wrong\n\t\t * data due to that. Replace the broken values with the\n\t\t * correct ones.\n\t\t */\n\t\tdev->device = 0x30;\n\t\tdev->class = 0x028000;\n\n\t\tpr_info(\"pci %s: AR9381 fixup applied\\n\", pci_name(dev));\n\t}\n}\n\nDECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATHEROS, PCI_ANY_ID,\n\t\t\ttl_wdr4900_v1_pci_wmac_fixup);\n#endif /* CONFIG_PCI */\n\n/*\n * Setup the architecture\n */\nstatic void __init tl_wdr4900_v1_setup_arch(void)\n{\n\tif (ppc_md.progress)\n\t\tppc_md.progress(\"tl_wdr4900_v1_setup_arch()\", 0);\n\n\tfsl_pci_assign_primary();\n\n\tprintk(KERN_INFO \"TL-WDR4900 v1 board from TP-Link\\n\");\n}\n\nmachine_arch_initcall(tl_wdr4900_v1, mpc85xx_common_publish_devices);\n\n/*\n * Called very early, device-tree isn't unflattened\n */\nstatic int __init tl_wdr4900_v1_probe(void)\n{\n\tunsigned long root = of_get_flat_dt_root();\n\n\tif (of_flat_dt_is_compatible(root, \"tplink,tl-wdr4900-v1\"))\n\t\treturn 1;\n\n\treturn 0;\n}\n\ndefine_machine(tl_wdr4900_v1) {\n\t.name\t\t\t= \"Freescale P1014\",\n\t.probe\t\t\t= tl_wdr4900_v1_probe,\n\t.setup_arch\t\t= tl_wdr4900_v1_setup_arch,\n\t.init_IRQ\t\t= tl_wdr4900_v1_pic_init,\n#ifdef CONFIG_PCI\n\t.pcibios_fixup_bus\t= fsl_pcibios_fixup_bus,\n#endif\n\t.get_irq\t\t= mpic_get_irq,\n\t.calibrate_decr\t\t= generic_calibrate_decr,\n\t.progress\t\t= udbg_progress,\n};\n"
  },
  {
    "path": "target/linux/mpc85xx/files/arch/powerpc/platforms/85xx/ws-ap3710i.c",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later\n\n/*\n * Enterasys WS-AP3710i Board Setup\n *\n * Copyright (C) 2019 David Bauer <mail@david-bauer.net>\n *\n * Based on:\n *   mpc85xx_rdb.c:\n *      MPC85xx RDB Board Setup\n *      Copyright 2013 Freescale Semiconductor Inc.\n *\n * This program is free software; you can redistribute  it and/or modify it\n * under  the terms of  the GNU General  Public License as published by the\n * Free Software Foundation;  either version 2 of the  License, or (at your\n * option) any later version.\n */\n\n#include <linux/stddef.h>\n#include <linux/kernel.h>\n#include <linux/delay.h>\n#include <linux/interrupt.h>\n#include <linux/of_platform.h>\n\n#include <asm/time.h>\n#include <asm/machdep.h>\n#include <asm/pci-bridge.h>\n#include <mm/mmu_decl.h>\n#include <asm/prom.h>\n#include <asm/udbg.h>\n#include <asm/mpic.h>\n\n#include <sysdev/fsl_soc.h>\n#include <sysdev/fsl_pci.h>\n#include \"smp.h\"\n\n#include \"mpc85xx.h\"\n\nvoid __init ws_ap3710i_pic_init(void)\n{\n\tstruct mpic *mpic;\n\n\tmpic = mpic_alloc(NULL, 0,\n\t  MPIC_BIG_ENDIAN |\n\t  MPIC_SINGLE_DEST_CPU,\n\t  0, 256, \" OpenPIC  \");\n\n\tBUG_ON(mpic == NULL);\n\tmpic_init(mpic);\n}\n\n/*\n * Setup the architecture\n */\nstatic void __init ws_ap3710i_setup_arch(void)\n{\n\tif (ppc_md.progress)\n\t\tppc_md.progress(\"ws_ap3710i_setup_arch()\", 0);\n\n\tmpc85xx_smp_init();\n\n\tfsl_pci_assign_primary();\n\n\tpr_info(\"WS-AP3710i board from Enterasys\\n\");\n}\n\nmachine_arch_initcall(ws_ap3710i, mpc85xx_common_publish_devices);\n\n/*\n * Called very early, device-tree isn't unflattened\n */\nstatic int __init ws_ap3710i_probe(void)\n{\n\tif (of_machine_is_compatible(\"enterasys,ws-ap3710i\"))\n\t\treturn 1;\n\treturn 0;\n}\n\ndefine_machine(ws_ap3710i) {\n\t.name\t\t\t= \"P1020 RDB\",\n\t.probe\t\t\t= ws_ap3710i_probe,\n\t.setup_arch\t\t= ws_ap3710i_setup_arch,\n\t.init_IRQ\t\t= ws_ap3710i_pic_init,\n#ifdef CONFIG_PCI\n\t.pcibios_fixup_bus\t= fsl_pcibios_fixup_bus,\n\t.pcibios_fixup_phb      = fsl_pcibios_fixup_phb,\n#endif\n\t.get_irq\t\t= mpic_get_irq,\n\t.calibrate_decr\t\t= generic_calibrate_decr,\n\t.progress\t\t= udbg_progress,\n};\n"
  },
  {
    "path": "target/linux/mpc85xx/files/arch/powerpc/platforms/85xx/ws-ap3825i.c",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later\n\n/*\n * Extreme Networks WS-AP3825i Board Setup\n *\n * Copyright (C) 2021 Martin Kennedy <hurricos@gmail.com>\n *\n * Based on:\n *   mpc85xx_rdb.c:\n *      MPC85xx RDB Board Setup\n *      Copyright 2013 Freescale Semiconductor Inc.\n *\n * This program is free software; you can redistribute  it and/or modify it\n * under  the terms of  the GNU General  Public License as published by the\n * Free Software Foundation;  either version 2 of the  License, or (at your\n * option) any later version.\n */\n\n#include <linux/stddef.h>\n#include <linux/kernel.h>\n#include <linux/delay.h>\n#include <linux/interrupt.h>\n#include <linux/of_platform.h>\n\n#include <asm/time.h>\n#include <asm/machdep.h>\n#include <asm/pci-bridge.h>\n#include <mm/mmu_decl.h>\n#include <asm/prom.h>\n#include <asm/udbg.h>\n#include <asm/mpic.h>\n\n#include <sysdev/fsl_soc.h>\n#include <sysdev/fsl_pci.h>\n#include \"smp.h\"\n\n#include \"mpc85xx.h\"\n\nvoid __init ws_ap3825i_pic_init(void)\n{\n\tstruct mpic *mpic;\n\n\tmpic = mpic_alloc(NULL, 0,\n\t  MPIC_BIG_ENDIAN |\n\t  MPIC_SINGLE_DEST_CPU,\n\t  0, 256, \" OpenPIC  \");\n\n\tBUG_ON(mpic == NULL);\n\tmpic_init(mpic);\n}\n\n/*\n * Setup the architecture\n */\nstatic void __init ws_ap3825i_setup_arch(void)\n{\n\tif (ppc_md.progress)\n\t\tppc_md.progress(\"ws_ap3825i_setup_arch()\", 0);\n\n\tmpc85xx_smp_init();\n\n\tfsl_pci_assign_primary();\n\n\tpr_info(\"WS-AP3825i board from Extreme Networks\\n\");\n}\n\nmachine_arch_initcall(ws_ap3825i, mpc85xx_common_publish_devices);\n\n/*\n * Called very early, device-tree isn't unflattened\n */\nstatic int __init ws_ap3825i_probe(void)\n{\n\tif (of_machine_is_compatible(\"extreme-networks,ws-ap3825i\"))\n\t\treturn 1;\n\treturn 0;\n}\n\ndefine_machine(ws_ap3825i) {\n\t.name\t\t\t= \"P1020 RDB\",\n\t.probe\t\t\t= ws_ap3825i_probe,\n\t.setup_arch\t\t= ws_ap3825i_setup_arch,\n\t.init_IRQ\t\t= ws_ap3825i_pic_init,\n#ifdef CONFIG_PCI\n\t.pcibios_fixup_bus\t= fsl_pcibios_fixup_bus,\n\t.pcibios_fixup_phb      = fsl_pcibios_fixup_phb,\n#endif\n\t.get_irq\t\t= mpic_get_irq,\n\t.calibrate_decr\t\t= generic_calibrate_decr,\n\t.progress\t\t= udbg_progress,\n};\n"
  },
  {
    "path": "target/linux/mpc85xx/image/Makefile",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n\ninclude $(TOPDIR)/rules.mk\ninclude $(INCLUDE_DIR)/image.mk\n\nDEVICE_VARS += DTB_SIZE\n\ndefine Build/pad-dtb\n\t$(call Image/BuildDTB,$(DTS_DIR)/$(DEVICE_DTS).dts,$(dir $@)/image-$(DEVICE_DTS).dtb,,--space $(DTB_SIZE))\nendef\n\ndefine Device/Default\n  PROFILES := Default\n  DEVICE_DTS := $(lastword $(subst _, ,$(1)))\n  KERNEL_DEPENDS = $$(wildcard $(DTS_DIR)/$$(DEVICE_DTS).dts)\n  KERNEL_ENTRY := 0x00000000\n  KERNEL_LOADADDR := 0x00000000\n  KERNEL := kernel-bin\nendef\n\ninclude $(SUBTARGET).mk\n\n$(eval $(call BuildImage))\n"
  },
  {
    "path": "target/linux/mpc85xx/image/p1010.mk",
    "content": "DEVICE_VARS += TPLINK_HWID TPLINK_HWREV TPLINK_FLASHLAYOUT TPLINK_HEADER_VERSION\n\ndefine Device/tplink_tl-wdr4900-v1\n  DEVICE_VENDOR := TP-Link\n  DEVICE_MODEL := TL-WDR4900\n  DEVICE_VARIANT := v1\n  TPLINK_HEADER_VERSION := 1\n  TPLINK_HWID := 0x49000001\n  TPLINK_HWREV := 1\n  TPLINK_FLASHLAYOUT := 16Mppc\n  KERNEL_SIZE := 2684k\n  KERNEL_NAME := simpleImage.tl-wdr4900-v1\n  KERNEL_INITRAMFS :=\n  KERNEL := kernel-bin | uImage none\n  KERNEL_ENTRY := 0x1000000\n  KERNEL_LOADADDR := 0x1000000\n  SUPPORTED_DEVICES += tl-wdr4900-v1\n  ARTIFACTS := fdt.bin\n  ARTIFACT/fdt.bin := append-dtb\n  IMAGES := factory.bin sysupgrade.bin\n  IMAGE/sysupgrade.bin := tplink-v1-image sysupgrade | append-metadata\n  IMAGE/factory.bin := tplink-v1-image factory\n  DEFAULT := n\nendef\nTARGET_DEVICES += tplink_tl-wdr4900-v1\n\ndefine Device/sophos_red-15w-rev1\n  DEVICE_VENDOR := Sophos\n  DEVICE_MODEL := RED 15w\n  DEVICE_VARIANT := Rev.1\n  # Original firmware uses a dedicated DTB-partition.\n  # The bootloader however supports FIT-images.\n  KERNEL = kernel-bin | gzip | fit gzip $(KDIR)/image-$$(DEVICE_DTS).dtb\n  IMAGES := sysupgrade.bin\n  IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata\nendef\nTARGET_DEVICES += sophos_red-15w-rev1\n"
  },
  {
    "path": "target/linux/mpc85xx/image/p1020.mk",
    "content": "define Build/MultiImage\n        rm -rf $@.fakerd $@.new\n\n        dd if=/dev/zero of=$@.fakerd bs=32 count=1 conv=sync\n\n        -$(STAGING_DIR_HOST)/bin/mkimage -A $(LINUX_KARCH) -O linux -T multi -C $(1)  \\\n\t\t-a $(KERNEL_LOADADDR) -e $(KERNEL_ENTRY) -n '$(BOARD_NAME) initramfs' \\\n\t\t-d $@:$@.fakerd:$(KDIR)/image-$(firstword $(DEVICE_DTS)).dtb $@.new\n        mv $@.new $@\n        rm -rf $@.fakerd\nendef\n\ndefine Device/aerohive_hiveap-330\n  DEVICE_VENDOR := Aerohive\n  DEVICE_MODEL := HiveAP-330\n  DEVICE_ALT0_VENDOR := Aerohive\n  DEVICE_ALT0_MODEL := HiveAP-350\n  DEVICE_PACKAGES := kmod-tpm-i2c-atmel kmod-hwmon-lm70\n  BLOCKSIZE := 128k\n  KERNEL := kernel-bin | uImage none\n  KERNEL_INITRAMFS := kernel-bin | MultiImage none\n  KERNEL_SIZE := 16m\n  IMAGES := sysupgrade.bin\n  IMAGE/sysupgrade.bin := append-dtb | pad-to 256k | append-kernel | \\\n\tappend-rootfs | pad-rootfs | check-size | append-metadata\n  IMAGE_SIZE = 63m\n  DEVICE_COMPAT_VERSION := 2.0\n  DEVICE_COMPAT_MESSAGE := \\n$\\\n    !The partitioning of the HiveAP 330 has changed! \\n$\\\n    To upgrade, please take a look at the install instructions over \\\n    at the device's wiki: <https://openwrt.org/toh/aerohive/hiveap-330> \\n$\\\n    An abridged version for the console is provided here for comfort. \\n$\\\n    Run the following script into a shell on the device and retry this \\\n    sysupgrade again: \\n$\\\n    cat <<- \"EOF\" > /tmp/uboot-fix.sh; sh /tmp/uboot-fix.sh \\n$\\\n    . /lib/functions.sh \\n$\\\n    . /lib/functions/system.sh \\n$\\\n    opkg update && opkg install uboot-envtools kmod-mtd-rw || exit 2 \\n$\\\n    insmod mtd-rw i_want_a_brick=y || exit 3 \\n$\\\n    echo \"/dev/mtd$$$$(find_mtd_index u-boot-env) 0x0 0x20000 0x10000\" > \"/etc/fw_env.config\" \\n$\\\n    fw_setenv owrt_boot 'setenv bootargs console=ttyS0,9600;bootm 0xEC040000 - 0xEC000000' \\n$\\\n    cp \"/dev/mtd$$$$(find_mtd_index 'u-boot')\" /tmp/uboot \\n$\\\n    cp /tmp/uboot /tmp/uboot_patched \\n$\\\n    strings -td < /tmp/uboot | grep '^ *[0-9]* *\\\\(run owrt_boot\\\\|setenv bootargs\\\\).*cp\\\\.l' | \\n$\\\n       awk '{print $$$$1}' | \\n$\\\n       while read offset; do \\n$\\\n         echo -n \"run owrt_boot;            \" | dd of=/tmp/uboot_patched bs=1 seek=$$$${offset} conv=notrunc \\n$\\\n       done \\n$\\\n       mtd write /tmp/uboot_patched u-boot \\n$\\\n       uci set system.@system[0].compat_version=2.0; uci commit; \\n$\\\n    EOF \\n$\\\n    \\n$\\\n    Note that if this fails, you will need to use the serial console \\n$\\\n    to re-install OpenWrt. \\n$\\\n    Note that after this sysupgrade, the AP will be unavailable for 7 \\n$\\\n    minutes to reformat flash.\"\n\nendef\nTARGET_DEVICES += aerohive_hiveap-330\n\ndefine Device/enterasys_ws-ap3710i\n  DEVICE_VENDOR := Enterasys\n  DEVICE_MODEL := WS-AP3710i\n  BLOCKSIZE := 128k\n  KERNEL = kernel-bin | lzma | fit lzma $(KDIR)/image-$$(DEVICE_DTS).dtb\n  IMAGES := sysupgrade.bin\n  IMAGE/sysupgrade.bin := append-kernel | append-rootfs | pad-rootfs | append-metadata\nendef\nTARGET_DEVICES += enterasys_ws-ap3710i\n\ndefine Device/extreme-networks_ws-ap3825i\n  DEVICE_VENDOR := Extreme Networks\n  DEVICE_MODEL := WS-AP3825i\n  DEVICE_PACKAGES := kmod-ath10k-ct ath10k-firmware-qca988x-ct\n  BLOCKSIZE := 128k\n  DTB_SIZE := 20480\n  KERNEL = kernel-bin | lzma | pad-dtb | fit lzma $(KDIR)/image-$$(DEVICE_DTS).dtb\n  IMAGES := sysupgrade.bin\n  IMAGE/sysupgrade.bin := append-kernel | append-rootfs | pad-rootfs | append-metadata\nendef\nTARGET_DEVICES += extreme-networks_ws-ap3825i\n\ndefine Device/ocedo_panda\n  DEVICE_VENDOR := OCEDO\n  DEVICE_MODEL := Panda\n  DEVICE_PACKAGES := kmod-rtc-ds1307\n  KERNEL = kernel-bin | gzip | fit gzip $(KDIR)/image-$$(DEVICE_DTS).dtb\n  PAGESIZE := 2048\n  SUBPAGESIZE := 512\n  BLOCKSIZE := 128k\n  IMAGES := fdt.bin sysupgrade.bin\n  IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata\n  IMAGE/fdt.bin := append-dtb\nendef\nTARGET_DEVICES += ocedo_panda\n\n"
  },
  {
    "path": "target/linux/mpc85xx/image/p2020.mk",
    "content": "define Device/freescale_p2020rdb\n  DEVICE_VENDOR := Freescale\n  DEVICE_MODEL := P2020RDB\n  DEVICE_DTS_DIR := $(DTS_DIR)/fsl\n  DEVICE_PACKAGES := kmod-hwmon-lm90 kmod-rtc-ds1307 \\\n\tkmod-gpio-pca953x kmod-eeprom-at24\n  BLOCKSIZE := 128k\n  KERNEL := kernel-bin | gzip | \\\n\tfit gzip $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb\n  SUPPORTED_DEVICES := fsl,P2020RDB\n  IMAGES := sysupgrade.bin\n  IMAGE/sysupgrade.bin := append-kernel | append-rootfs | \\\n\tpad-rootfs $$(BLOCKSIZE) | append-metadata\nendef\nTARGET_DEVICES += freescale_p2020rdb\n"
  },
  {
    "path": "target/linux/mpc85xx/p1010/config-default",
    "content": "# CONFIG_FSL_CORENET_CF is not set\nCONFIG_MTD_NAND_FSL_IFC=y\nCONFIG_MTD_SPLIT_FIRMWARE=y\nCONFIG_MTD_SPLIT_TPLINK_FW=y\nCONFIG_MTD_UBI=y\nCONFIG_MTD_UBI_BEB_LIMIT=20\nCONFIG_MTD_UBI_BLOCK=y\nCONFIG_MTD_UBI_WL_THRESHOLD=4096\nCONFIG_REALTEK_PHY=y\nCONFIG_RED_15W_REV1=y\nCONFIG_TL_WDR4900_V1=y\nCONFIG_UBIFS_FS=y\n"
  },
  {
    "path": "target/linux/mpc85xx/p1010/profiles/00-default.mk",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n\ndefine Profile/Default\n  NAME:=Default Profile\n  PRIORITY:=1\nendef\n\ndefine Profile/Default/Description\n\tDefault package set compatible with most P1010 boards.\nendef\n\n$(eval $(call Profile,Default))\n"
  },
  {
    "path": "target/linux/mpc85xx/p1010/target.mk",
    "content": "BOARDNAME:=P1010\nFEATURES+=nand\nKERNELNAME:=simpleImage.tl-wdr4900-v1\n\ndefine Target/Description\n\tBuild firmware images for P1010 based boards.\nendef\n\n"
  },
  {
    "path": "target/linux/mpc85xx/p1020/config-default",
    "content": "CONFIG_ARCH_HAS_TICK_BROADCAST=y\nCONFIG_AT803X_PHY=y\nCONFIG_BROADCOM_PHY=y\nCONFIG_CMDLINE_OVERRIDE=y\nCONFIG_CPU_RMAP=y\nCONFIG_EEPROM_LEGACY=y\n# CONFIG_FSL_CORENET_CF is not set\nCONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y\nCONFIG_GENERIC_TBSYNC=y\nCONFIG_GPIO_74X164=y\n# CONFIG_GPIO_MAX77620 is not set\nCONFIG_HAVE_RCU_TABLE_FREE=y\nCONFIG_HIVEAP_330=y\nCONFIG_PANDA=y\nCONFIG_I2C_CHARDEV=y\nCONFIG_LEDS_LP5521=y\nCONFIG_LEDS_LP55XX_COMMON=y\nCONFIG_LOCK_SPIN_ON_OWNER=y\n# CONFIG_MAX77620_THERMAL is not set\n# CONFIG_MAX77620_WATCHDOG is not set\nCONFIG_MFD_CORE=y\nCONFIG_MFD_MAX77620=y\nCONFIG_MTD_CFI=y\nCONFIG_MTD_NAND_FSL_ELBC=y\nCONFIG_MTD_PHYSMAP=y\nCONFIG_MTD_SPLIT_FIRMWARE=y\nCONFIG_MTD_SPLIT_FIT_FW=y\nCONFIG_MTD_SPLIT_UIMAGE_FW=y\nCONFIG_MTD_UBI=y\nCONFIG_MTD_UBI_BEB_LIMIT=20\nCONFIG_MTD_UBI_BLOCK=y\nCONFIG_MTD_UBI_WL_THRESHOLD=4096\nCONFIG_MUTEX_SPIN_ON_OWNER=y\nCONFIG_NET_FLOW_LIMIT=y\nCONFIG_NR_CPUS=2\nCONFIG_PADATA=y\nCONFIG_REGMAP_IRQ=y\nCONFIG_REGULATOR=y\nCONFIG_RFS_ACCEL=y\nCONFIG_RPS=y\n# CONFIG_RTC_DRV_MAX77686 is not set\nCONFIG_RWSEM_SPIN_ON_OWNER=y\nCONFIG_SMP=y\nCONFIG_SPI_GPIO=y\nCONFIG_SWCONFIG_B53=y\n# CONFIG_SWCONFIG_B53_MMAP_DRIVER is not set\nCONFIG_SWCONFIG_B53_PHY_DRIVER=y\n# CONFIG_SWCONFIG_B53_PHY_FIXUP is not set\n# CONFIG_SWCONFIG_B53_SPI_DRIVER is not set\n# CONFIG_SWCONFIG_B53_SRAB_DRIVER is not set\nCONFIG_TREE_RCU=y\nCONFIG_UBIFS_FS=y\nCONFIG_WS_AP3710I=y\nCONFIG_WS_AP3825I=y\nCONFIG_XPS=y\n"
  },
  {
    "path": "target/linux/mpc85xx/p1020/profiles/00-default.mk",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n\ndefine Profile/Default\n  NAME:=Default Profile\n  PRIORITY:=1\nendef\n\ndefine Profile/Default/Description\n\tDefault package set compatible with most P1020 boards.\nendef\n\n$(eval $(call Profile,Default))\n"
  },
  {
    "path": "target/linux/mpc85xx/p1020/target.mk",
    "content": "BOARDNAME:=P1020\nFEATURES+=nand\n\ndefine Target/Description\n\tBuild firmware images for Freescale P1020 based boards.\nendef\n"
  },
  {
    "path": "target/linux/mpc85xx/p2020/config-default",
    "content": "CONFIG_ARCH_HAS_TICK_BROADCAST=y\nCONFIG_CPU_RMAP=y\nCONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y\nCONFIG_GENERIC_IRQ_MIGRATION=y\nCONFIG_GENERIC_TBSYNC=y\nCONFIG_HAVE_RCU_TABLE_FREE=y\nCONFIG_LOCK_SPIN_ON_OWNER=y\nCONFIG_MPC85xx_RDB=y\nCONFIG_MTD_CFI=y\nCONFIG_MTD_NAND_BCH=y\nCONFIG_MTD_NAND_ECC_BCH=y\nCONFIG_MTD_NAND_FSL_ELBC=y\nCONFIG_MTD_PHYSMAP=y\nCONFIG_MTD_SPLIT_FIRMWARE=y\nCONFIG_MTD_SPLIT_FIT_FW=y\nCONFIG_MUTEX_SPIN_ON_OWNER=y\nCONFIG_NET_FLOW_LIMIT=y\nCONFIG_NR_CPUS=2\nCONFIG_PADATA=y\nCONFIG_PCI_MSI=y\nCONFIG_PPC_MSI_BITMAP=y\nCONFIG_RFS_ACCEL=y\nCONFIG_RPS=y\nCONFIG_RWSEM_SPIN_ON_OWNER=y\nCONFIG_SMP=y\nCONFIG_TREE_RCU=y\nCONFIG_TREE_SRCU=y\nCONFIG_XPS=y\n"
  },
  {
    "path": "target/linux/mpc85xx/p2020/profiles/00-default.mk",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n\ndefine Profile/Default\n  NAME:=Default Profile\n  PRIORITY:=1\nendef\n\ndefine Profile/Default/Description\n\tDefault package set compatible with most P2020 boards.\nendef\n\n$(eval $(call Profile,Default))\n"
  },
  {
    "path": "target/linux/mpc85xx/p2020/target.mk",
    "content": "BOARDNAME:=P2020\n\ndefine Target/Description\n\tBuild firmware images for Freescale P2020 based boards.\nendef\n"
  },
  {
    "path": "target/linux/mpc85xx/patches-5.10/001-powerpc-85xx-add-gpio-keys-to-of-match-table.patch",
    "content": "--- a/arch/powerpc/platforms/85xx/common.c\n+++ b/arch/powerpc/platforms/85xx/common.c\n@@ -30,6 +30,7 @@ static const struct of_device_id mpc85xx\n \t{ .compatible = \"fsl,mpc8548-guts\", },\n \t/* Probably unnecessary? */\n \t{ .compatible = \"gpio-leds\", },\n+\t{ .compatible = \"gpio-keys\", },\n \t/* For all PCI controllers */\n \t{ .compatible = \"fsl,mpc8540-pci\", },\n \t{ .compatible = \"fsl,mpc8548-pcie\", },\n"
  },
  {
    "path": "target/linux/mpc85xx/patches-5.10/100-powerpc-85xx-tl-wdr4900-v1-support.patch",
    "content": "From 1d9f596e572917772b87a2a37e1680902964782f Mon Sep 17 00:00:00 2001\nFrom: Gabor Juhos <juhosg@openwrt.org>\nDate: Wed, 20 Feb 2013 08:40:33 +0100\nSubject: [PATCH] powerpc: 85xx: add support for the TP-Link TL-WDR4900 v1\n board\n\nThis patch adds support for the TP-Link TL-WDR4900 v1\nconcurrent dual-band wireless router. The devices uses\nthe Freescale P1014 SoC.\n\nSigned-off-by: Gabor Juhos <juhosg@openwrt.org>\nSigned-off-by: Pawel Dembicki <paweldembicki@gmail.com>\n---\n arch/powerpc/boot/Makefile           |  3 ++-\n arch/powerpc/boot/wrapper            |  5 +++++\n arch/powerpc/platforms/85xx/Kconfig  | 12 ++++++++++++\n arch/powerpc/platforms/85xx/Makefile |  1 +\n 4 files changed, 20 insertions(+), 1 deletion(-)\n\n--- a/arch/powerpc/boot/Makefile\n+++ b/arch/powerpc/boot/Makefile\n@@ -157,6 +157,7 @@ src-plat-$(CONFIG_PPC_PSERIES) += pserie\n src-plat-$(CONFIG_PPC_POWERNV) += pseries-head.S\n src-plat-$(CONFIG_PPC_IBM_CELL_BLADE) += pseries-head.S\n src-plat-$(CONFIG_MVME7100) += motload-head.S mvme7100.c\n+src-plat-$(CONFIG_TL_WDR4900_V1) += simpleboot.c fixed-head.S\n \n src-wlib := $(sort $(src-wlib-y))\n src-plat := $(sort $(src-plat-y))\n@@ -336,7 +337,7 @@ image-$(CONFIG_TQM8555)\t\t\t+= cuImage.tqm\n image-$(CONFIG_TQM8560)\t\t\t+= cuImage.tqm8560\n image-$(CONFIG_SBC8548)\t\t\t+= cuImage.sbc8548\n image-$(CONFIG_KSI8560)\t\t\t+= cuImage.ksi8560\n-\n+image-$(CONFIG_TL_WDR4900_V1)\t\t+= simpleImage.tl-wdr4900-v1\n # Board ports in arch/powerpc/platform/86xx/Kconfig\n image-$(CONFIG_MVME7100)                += dtbImage.mvme7100\n \n--- a/arch/powerpc/boot/wrapper\n+++ b/arch/powerpc/boot/wrapper\n@@ -324,6 +324,11 @@ adder875-redboot)\n     platformo=\"$object/fixed-head.o $object/redboot-8xx.o\"\n     binary=y\n     ;;\n+simpleboot-tl-wdr4900-v1)\n+    platformo=\"$object/fixed-head.o $object/simpleboot.o\"\n+    link_address='0x1000000'\n+    binary=y\n+    ;;\n simpleboot-*)\n     platformo=\"$object/fixed-head.o $object/simpleboot.o\"\n     binary=y\n--- a/arch/powerpc/platforms/85xx/Kconfig\n+++ b/arch/powerpc/platforms/85xx/Kconfig\n@@ -170,6 +170,18 @@ config STX_GP3\n \tselect CPM2\n \tselect DEFAULT_UIMAGE\n \n+config TL_WDR4900_V1\n+    bool \"TP-Link TL-WDR4900 v1\"\n+    select DEFAULT_UIMAGE\n+    select ARCH_REQUIRE_GPIOLIB\n+    select GPIO_MPC8XXX\n+    select SWIOTLB\n+    help\n+      This option enables support for the TP-Link TL-WDR4900 v1 board.\n+\n+      This board is a Concurrent Dual-Band wireless router with a\n+      Freescale P1014 SoC.\n+\n config TQM8540\n \tbool \"TQ Components TQM8540\"\n \thelp\n--- a/arch/powerpc/platforms/85xx/Makefile\n+++ b/arch/powerpc/platforms/85xx/Makefile\n@@ -28,6 +28,7 @@ obj-$(CONFIG_CORENET_GENERIC)   += coren\n obj-$(CONFIG_FB_FSL_DIU)\t+= t1042rdb_diu.o\n obj-$(CONFIG_STX_GP3)\t  += stx_gp3.o\n obj-$(CONFIG_TQM85xx)\t  += tqm85xx.o\n+obj-$(CONFIG_TL_WDR4900_V1) += tl_wdr4900_v1.o\n obj-$(CONFIG_SBC8548)     += sbc8548.o\n obj-$(CONFIG_PPA8548)     += ppa8548.o\n obj-$(CONFIG_SOCRATES)    += socrates.o socrates_fpga_pic.o\n"
  },
  {
    "path": "target/linux/mpc85xx/patches-5.10/101-powerpc-85xx-hiveap-330-support.patch",
    "content": "--- a/arch/powerpc/platforms/85xx/Kconfig\n+++ b/arch/powerpc/platforms/85xx/Kconfig\n@@ -49,6 +49,17 @@ config BSC9132_QDS\n \t  and dual StarCore SC3850 DSP cores.\n \t  Manufacturer : Freescale Semiconductor, Inc\n \n+config HIVEAP_330\n+    bool \"Aerohive HiveAP-330\"\n+    select DEFAULT_UIMAGE\n+    select ARCH_REQUIRE_GPIOLIB\n+    select GPIO_MPC8XXX\n+    help\n+      This option enables support for the Aerohive HiveAP-330 board.\n+\n+      This board is a Concurrent Dual-Band wireless access point with a\n+      Freescale P1020 SoC.\n+\n config MPC8540_ADS\n \tbool \"Freescale MPC8540 ADS\"\n \tselect DEFAULT_UIMAGE\n--- a/arch/powerpc/platforms/85xx/Makefile\n+++ b/arch/powerpc/platforms/85xx/Makefile\n@@ -12,6 +12,7 @@ obj-y += common.o\n obj-$(CONFIG_BSC9131_RDB) += bsc913x_rdb.o\n obj-$(CONFIG_BSC9132_QDS) += bsc913x_qds.o\n obj-$(CONFIG_C293_PCIE)   += c293pcie.o\n+obj-$(CONFIG_HIVEAP_330) += hiveap-330.o\n obj-$(CONFIG_MPC8540_ADS) += mpc85xx_ads.o\n obj-$(CONFIG_MPC8560_ADS) += mpc85xx_ads.o\n obj-$(CONFIG_MPC85xx_CDS) += mpc85xx_cds.o\n"
  },
  {
    "path": "target/linux/mpc85xx/patches-5.10/102-powerpc-add-cmdline-override.patch",
    "content": "--- a/arch/powerpc/Kconfig\n+++ b/arch/powerpc/Kconfig\n@@ -932,6 +932,14 @@ config CMDLINE_FORCE\n \n endchoice\n \n+config CMDLINE_OVERRIDE\n+    bool \"Use alternative cmdline from device tree\"\n+    help\n+      Some bootloaders may have uneditable bootargs. While CMDLINE_FORCE can\n+      be used, this is not a good option for kernels that are shared across\n+      devices. This setting enables using \"chosen/cmdline-override\" as the\n+      cmdline if it exists in the device tree.\n+\n config EXTRA_TARGETS\n \tstring \"Additional default image types\"\n \thelp\n--- a/drivers/of/fdt.c\n+++ b/drivers/of/fdt.c\n@@ -1059,6 +1059,17 @@ int __init early_init_dt_scan_chosen(uns\n \tif (p != NULL && l > 0)\n \t\tstrlcat(data, p, min_t(int, strlen(data) + (int)l, COMMAND_LINE_SIZE));\n \n+    /* CONFIG_CMDLINE_OVERRIDE is used to fallback to a different\n+     * device tree option of chosen/bootargs-override. This is\n+     * helpful on boards where u-boot sets bootargs, and is unable\n+     * to be modified.\n+     */\n+#ifdef CONFIG_CMDLINE_OVERRIDE\n+\tp = of_get_flat_dt_prop(node, \"bootargs-override\", &l);\n+\tif (p != NULL && l > 0)\n+\t\tstrlcpy(data, p, min((int)l, COMMAND_LINE_SIZE));\n+#endif\n+\n \t/*\n \t * CONFIG_CMDLINE is meant to be a default in case nothing else\n \t * managed to set the command line, unless CONFIG_CMDLINE_FORCE\n"
  },
  {
    "path": "target/linux/mpc85xx/patches-5.10/103-powerpc-85xx-red-15w-rev1.patch",
    "content": "--- a/arch/powerpc/platforms/85xx/Kconfig\n+++ b/arch/powerpc/platforms/85xx/Kconfig\n@@ -173,6 +173,16 @@ config XES_MPC85xx\n \t  Manufacturer: Extreme Engineering Solutions, Inc.\n \t  URL: <https://www.xes-inc.com/>\n \n+config RED_15W_REV1\n+\tbool \"Sophos RED 15w Rev.1\"\n+\tselect DEFAULT_UIMAGE\n+\tselect ARCH_REQUIRE_GPIOLIB\n+\tselect GPIO_MPC8XXX\n+\thelp\n+\t  This option enables support for the Sophos RED 15w Rev.1 board.\n+\n+\t  This board is a wireless VPN router with a Freescale P1010 SoC.\n+\n config STX_GP3\n \tbool \"Silicon Turnkey Express GP3\"\n \thelp\n--- a/arch/powerpc/platforms/85xx/Makefile\n+++ b/arch/powerpc/platforms/85xx/Makefile\n@@ -27,6 +27,7 @@ obj-$(CONFIG_P1023_RDB)   += p1023_rdb.o\n obj-$(CONFIG_TWR_P102x)   += twr_p102x.o\n obj-$(CONFIG_CORENET_GENERIC)   += corenet_generic.o\n obj-$(CONFIG_FB_FSL_DIU)\t+= t1042rdb_diu.o\n+obj-$(CONFIG_RED_15W_REV1)\t+= red15w_rev1.o\n obj-$(CONFIG_STX_GP3)\t  += stx_gp3.o\n obj-$(CONFIG_TQM85xx)\t  += tqm85xx.o\n obj-$(CONFIG_TL_WDR4900_V1) += tl_wdr4900_v1.o\n"
  },
  {
    "path": "target/linux/mpc85xx/patches-5.10/104-powerpc-mpc85xx-change-P2020RDB-dts-file-for-OpenWRT.patch",
    "content": "From 93514afd769c305182beeed1f9c4c46235879ef8 Mon Sep 17 00:00:00 2001\nFrom: Pawel Dembicki <paweldembicki@gmail.com>\nDate: Sun, 30 Dec 2018 23:24:41 +0100\nSubject: [PATCH] powerpc: mpc85xx: change P2020RDB dts file for OpenWRT\n\nThis patch apply chages for OpenWRT in P2020RDB\ndts file.\n\nSigned-off-by: Pawel Dembicki <paweldembicki@gmail.com>\n---\n arch/powerpc/boot/dts/fsl/p2020rdb.dts | 98 +++++++++++++++++---------\n 1 file changed, 63 insertions(+), 35 deletions(-)\n\n--- a/arch/powerpc/boot/dts/fsl/p2020rdb.dts\n+++ b/arch/powerpc/boot/dts/fsl/p2020rdb.dts\n@@ -5,10 +5,15 @@\n  * Copyright 2009-2012 Freescale Semiconductor Inc.\n  */\n \n+/dts-v1/;\n+\n /include/ \"p2020si-pre.dtsi\"\n \n+#include <dt-bindings/gpio/gpio.h>\n+#include <dt-bindings/input/input.h>\n+\n / {\n-\tmodel = \"fsl,P2020RDB\";\n+\tmodel = \"Freescale P2020RDB\";\n \tcompatible = \"fsl,P2020RDB\";\n \n \taliases {\n@@ -34,48 +39,38 @@\n \t\t\t  0x2 0x0 0x0 0xffb00000 0x00020000>;\n \n \t\tnor@0,0 {\n-\t\t\t#address-cells = <1>;\n-\t\t\t#size-cells = <1>;\n \t\t\tcompatible = \"cfi-flash\";\n \t\t\treg = <0x0 0x0 0x1000000>;\n \t\t\tbank-width = <2>;\n \t\t\tdevice-width = <1>;\n \n-\t\t\tpartition@0 {\n-\t\t\t\t/* This location must not be altered  */\n-\t\t\t\t/* 256KB for Vitesse 7385 Switch firmware */\n-\t\t\t\treg = <0x0 0x00040000>;\n-\t\t\t\tlabel = \"NOR (RO) Vitesse-7385 Firmware\";\n-\t\t\t\tread-only;\n-\t\t\t};\n-\n-\t\t\tpartition@40000 {\n-\t\t\t\t/* 256KB for DTB Image */\n-\t\t\t\treg = <0x00040000 0x00040000>;\n-\t\t\t\tlabel = \"NOR (RO) DTB Image\";\n-\t\t\t\tread-only;\n-\t\t\t};\n+\t\t\tpartitions {\n+\t\t\t\tcompatible = \"fixed-partitions\";\n+\t\t\t\t#address-cells = <1>;\n+\t\t\t\t#size-cells = <1>;\n \n-\t\t\tpartition@80000 {\n-\t\t\t\t/* 3.5 MB for Linux Kernel Image */\n-\t\t\t\treg = <0x00080000 0x00380000>;\n-\t\t\t\tlabel = \"NOR (RO) Linux Kernel Image\";\n-\t\t\t\tread-only;\n-\t\t\t};\n+\t\t\t\tpartition@0 {\n+\t\t\t\t\t/* This location must not be altered  */\n+\t\t\t\t\t/* 256KB for Vitesse 7385 Switch firmware */\n+\t\t\t\t\treg = <0x0 0x00040000>;\n+\t\t\t\t\tlabel = \"NOR (RO) Vitesse-7385 Firmware\";\n+\t\t\t\t\tread-only;\n+\t\t\t\t};\n \n-\t\t\tpartition@400000 {\n-\t\t\t\t/* 11MB for JFFS2 based Root file System */\n-\t\t\t\treg = <0x00400000 0x00b00000>;\n-\t\t\t\tlabel = \"NOR (RW) JFFS2 Root File System\";\n-\t\t\t};\n+\t\t\t\tpartition@40000 {\n+\t\t\t\t\tcompatible = \"denx,fit\";\n+\t\t\t\t\treg = <0x00040000 0x00ec0000>;\n+\t\t\t\t\tlabel = \"firmware\";\n+\t\t\t\t};\n \n-\t\t\tpartition@f00000 {\n-\t\t\t\t/* This location must not be altered  */\n-\t\t\t\t/* 512KB for u-boot Bootloader Image */\n-\t\t\t\t/* 512KB for u-boot Environment Variables */\n-\t\t\t\treg = <0x00f00000 0x00100000>;\n-\t\t\t\tlabel = \"NOR (RO) U-Boot Image\";\n-\t\t\t\tread-only;\n+\t\t\t\tpartition@f00000 {\n+\t\t\t\t\t/* This location must not be altered  */\n+\t\t\t\t\t/* 512KB for u-boot Bootloader Image */\n+\t\t\t\t\t/* 512KB for u-boot Environment Variables */\n+\t\t\t\t\treg = <0x00f00000 0x00100000>;\n+\t\t\t\t\tlabel = \"u-boot\";\n+\t\t\t\t\tread-only;\n+\t\t\t\t};\n \t\t\t};\n \t\t};\n \n@@ -85,6 +80,7 @@\n \t\t\tcompatible = \"fsl,p2020-fcm-nand\",\n \t\t\t\t     \"fsl,elbc-fcm-nand\";\n \t\t\treg = <0x1 0x0 0x40000>;\n+\t\t\tnand-ecc-mode = \"none\";\n \n \t\t\tpartition@0 {\n \t\t\t\t/* This location must not be altered  */\n@@ -140,13 +136,43 @@\n \tsoc: soc@ffe00000 {\n \t\tranges = <0x0 0x0 0xffe00000 0x100000>;\n \n+\t\tgpio0: gpio-controller@fc00 {\n+\t\t};\n+\n \t\ti2c@3000 {\n+\t\t\ttemperature-sensor@4c {\n+\t\t\t\tcompatible = \"adi,adt7461\";\n+\t\t\t\treg = <0x4c>;\n+\t\t\t};\n+\n+\t\t\teeprom@50 {\n+\t\t\t\tcompatible = \"atmel,24c256\";\n+\t\t\t\treg = <0x50>;\n+\t\t\t};\n+\n \t\t\trtc@68 {\n \t\t\t\tcompatible = \"dallas,ds1339\";\n \t\t\t\treg = <0x68>;\n \t\t\t};\n \t\t};\n \n+\t\ti2c@3100 {\n+\t\t\tpmic@11 {\n+\t\t\t\tcompatible = \"zl2006\";\n+\t\t\t\treg = <0x11>;\n+\t\t\t};\n+\n+\t\t\tgpio@18 {\n+\t\t\t\tcompatible = \"nxp,pca9557\";\n+\t\t\t\treg = <0x18>;\n+\t\t\t};\n+\n+\t\t\teeprom@52 {\n+\t\t\t\tcompatible = \"atmel,24c01\";\n+\t\t\t\treg = <0x52>;\n+\t\t\t};\n+\t\t};\n+\n \t\tspi@7000 {\n \t\t\tflash@0 {\n \t\t\t\t#address-cells = <1>;\n@@ -200,10 +226,12 @@\n \t\t\tphy0: ethernet-phy@0 {\n \t\t\t\tinterrupts = <3 1 0 0>;\n \t\t\t\treg = <0x0>;\n+\t\t\t\treset-gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;\n \t\t\t};\n \t\t\tphy1: ethernet-phy@1 {\n \t\t\t\tinterrupts = <3 1 0 0>;\n \t\t\t\treg = <0x1>;\n+\t\t\t\treset-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;\n \t\t\t};\n \t\t\ttbi-phy@2 {\n \t\t\t\tdevice_type = \"tbi-phy\";\n"
  },
  {
    "path": "target/linux/mpc85xx/patches-5.10/105-powerpc-85xx-panda-support.patch",
    "content": "--- a/arch/powerpc/platforms/85xx/Kconfig\n+++ b/arch/powerpc/platforms/85xx/Kconfig\n@@ -60,6 +60,17 @@ config HIVEAP_330\n       This board is a Concurrent Dual-Band wireless access point with a\n       Freescale P1020 SoC.\n \n+config PANDA\n+\tbool \"OCEDO PANDA\"\n+\tselect DEFAULT_UIMAGE\n+\tselect ARCH_REQUIRE_GPIOLIB\n+\tselect GPIO_MPC8XXX\n+\thelp\n+\t  This option enables support for the OCEDO PANDA board.\n+\n+\t  This board is a Concurrent Dual-Band wireless access point with a\n+\t  Freescale P1020 SoC.\n+\n config MPC8540_ADS\n \tbool \"Freescale MPC8540 ADS\"\n \tselect DEFAULT_UIMAGE\n--- a/arch/powerpc/platforms/85xx/Makefile\n+++ b/arch/powerpc/platforms/85xx/Makefile\n@@ -24,6 +24,7 @@ obj-$(CONFIG_P1010_RDB)   += p1010rdb.o\n obj-$(CONFIG_P1022_DS)    += p1022_ds.o\n obj-$(CONFIG_P1022_RDK)   += p1022_rdk.o\n obj-$(CONFIG_P1023_RDB)   += p1023_rdb.o\n+obj-$(CONFIG_PANDA)       += panda.o\n obj-$(CONFIG_TWR_P102x)   += twr_p102x.o\n obj-$(CONFIG_CORENET_GENERIC)   += corenet_generic.o\n obj-$(CONFIG_FB_FSL_DIU)\t+= t1042rdb_diu.o\n"
  },
  {
    "path": "target/linux/mpc85xx/patches-5.10/106-powerpc-85xx-ws-ap3710i-support.patch",
    "content": "--- a/arch/powerpc/platforms/85xx/Kconfig\n+++ b/arch/powerpc/platforms/85xx/Kconfig\n@@ -71,6 +71,17 @@ config PANDA\n \t  This board is a Concurrent Dual-Band wireless access point with a\n \t  Freescale P1020 SoC.\n \n+config WS_AP3710I\n+\tbool \"Enterasys WS-AP3710i\"\n+\tselect DEFAULT_UIMAGE\n+\tselect ARCH_REQUIRE_GPIOLIB\n+\tselect GPIO_MPC8XXX\n+\thelp\n+\t  This option enables support for the Enterasys WS-AP3710i board.\n+\n+\t  This board is a Concurrent Dual-Band wireless access point with a\n+\t  Freescale P1020 SoC.\n+\n config MPC8540_ADS\n \tbool \"Freescale MPC8540 ADS\"\n \tselect DEFAULT_UIMAGE\n--- a/arch/powerpc/platforms/85xx/Makefile\n+++ b/arch/powerpc/platforms/85xx/Makefile\n@@ -26,6 +26,7 @@ obj-$(CONFIG_P1022_RDK)   += p1022_rdk.o\n obj-$(CONFIG_P1023_RDB)   += p1023_rdb.o\n obj-$(CONFIG_PANDA)       += panda.o\n obj-$(CONFIG_TWR_P102x)   += twr_p102x.o\n+obj-$(CONFIG_WS_AP3710I)  += ws-ap3710i.o\n obj-$(CONFIG_CORENET_GENERIC)   += corenet_generic.o\n obj-$(CONFIG_FB_FSL_DIU)\t+= t1042rdb_diu.o\n obj-$(CONFIG_RED_15W_REV1)\t+= red15w_rev1.o\n"
  },
  {
    "path": "target/linux/mpc85xx/patches-5.10/107-powerpc-85xx-add-ws-ap3825i-support.patch",
    "content": "From 2fa1a7983ef30f3c7486f9b07c001bee87d1f6d6 Mon Sep 17 00:00:00 2001\nFrom: Martin Kennedy <hurricos@gmail.com>\nDate: Sat, 1 Jan 2022 11:01:37 -0500\nSubject: [PATCH] PowerPC 85xx: Add WS-AP3825i support\n\nThis patch adds support for building Linux for the Extreme Networks\nWS-AP3825i AP.\n\n--- a/arch/powerpc/platforms/85xx/Kconfig\n+++ b/arch/powerpc/platforms/85xx/Kconfig\n@@ -82,6 +82,16 @@ config WS_AP3710I\n \t  This board is a Concurrent Dual-Band wireless access point with a\n \t  Freescale P1020 SoC.\n \n+config WS_AP3825I\n+\tbool \"Extreme Networks WS-AP3825i\"\n+\tselect DEFAULT_UIMAGE\n+\tselect ARCH_REQUIRE_GPIOLIB\n+\tselect GPIO_MPC8XXX\n+\thelp\n+\t  This option enables support for the Extreme Networks WS-AP3825i board.\n+\t  This board is a Concurrent Dual-Band wireless access point with a\n+\t  Freescale P1020 SoC.\n+\n config MPC8540_ADS\n \tbool \"Freescale MPC8540 ADS\"\n \tselect DEFAULT_UIMAGE\n--- a/arch/powerpc/platforms/85xx/Makefile\n+++ b/arch/powerpc/platforms/85xx/Makefile\n@@ -27,6 +27,7 @@ obj-$(CONFIG_P1023_RDB)   += p1023_rdb.o\n obj-$(CONFIG_PANDA)       += panda.o\n obj-$(CONFIG_TWR_P102x)   += twr_p102x.o\n obj-$(CONFIG_WS_AP3710I)  += ws-ap3710i.o\n+obj-$(CONFIG_WS_AP3825I)  += ws-ap3825i.o\n obj-$(CONFIG_CORENET_GENERIC)   += corenet_generic.o\n obj-$(CONFIG_FB_FSL_DIU)\t+= t1042rdb_diu.o\n obj-$(CONFIG_RED_15W_REV1)\t+= red15w_rev1.o\n"
  },
  {
    "path": "target/linux/mpc85xx/patches-5.10/900-powerpc-bootwrapper-disable-uImage-generation.patch",
    "content": "From d43ab14605510d9d2bd257a8cd70f24ada4621b0 Mon Sep 17 00:00:00 2001\nFrom: David Bauer <mail@david-bauer.net>\nDate: Sat, 29 Feb 2020 14:27:04 +0100\nSubject: [PATCH] powerpc: bootwrapper: disable uImage generation\n\nDue to CONFIG_KERNEL_XZ symbol, the bootwrapper code tries to\ninstruct the mkimage to use the xz compression, which isn't\nsupported. This disables the uImage generation, as OpenWrt\ngenerates individual uImages for each board using it's own\ntoolchain.\n\nSigned-off-by: David Bauer <mail@david-bauer.net>\n---\n arch/powerpc/boot/Makefile | 9 ---------\n 1 file changed, 9 deletions(-)\n\n--- a/arch/powerpc/boot/Makefile\n+++ b/arch/powerpc/boot/Makefile\n@@ -264,7 +264,6 @@ image-$(CONFIG_PPC_CHRP)\t\t+= zImage.chrp\n image-$(CONFIG_PPC_EFIKA)\t\t+= zImage.chrp\n image-$(CONFIG_PPC_PMAC)\t\t+= zImage.pmac\n image-$(CONFIG_PPC_HOLLY)\t\t+= dtbImage.holly\n-image-$(CONFIG_DEFAULT_UIMAGE)\t\t+= uImage\n image-$(CONFIG_EPAPR_BOOT)\t\t+= zImage.epapr\n \n #\n@@ -395,15 +394,6 @@ $(obj)/dtbImage.%: vmlinux $(wrapperbits\n $(obj)/vmlinux.strip: vmlinux\n \t$(STRIP) -s -R .comment $< -o $@\n \n-$(obj)/uImage: vmlinux $(wrapperbits) FORCE\n-\t$(call if_changed,wrap,uboot)\n-\n-$(obj)/uImage.initrd.%: vmlinux $(obj)/dts/%.dtb $(wrapperbits) FORCE\n-\t$(call if_changed,wrap,uboot-$*,,$(obj)/dts/$*.dtb,$(obj)/ramdisk.image.gz)\n-\n-$(obj)/uImage.%: vmlinux $(obj)/dts/%.dtb $(wrapperbits) FORCE\n-\t$(call if_changed,wrap,uboot-$*,,$(obj)/dts/$*.dtb)\n-\n $(obj)/cuImage.initrd.%: vmlinux $(obj)/dts/%.dtb $(wrapperbits) FORCE\n \t$(call if_changed,wrap,cuboot-$*,,$(obj)/dts/$*.dtb,$(obj)/ramdisk.image.gz)\n \n"
  },
  {
    "path": "target/linux/mvebu/Makefile",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2012-2015 OpenWrt.org\n\ninclude $(TOPDIR)/rules.mk\n\nBOARD:=mvebu\nBOARDNAME:=Marvell EBU Armada\nFEATURES:=fpu usb pci pcie gpio nand squashfs ramdisk boot-part rootfs-part legacy-sdcard targz\nSUBTARGETS:=cortexa9 cortexa53 cortexa72\n\nKERNEL_PATCHVER:=5.10\n\ninclude $(INCLUDE_DIR)/target.mk\n\nDEFAULT_PACKAGES += uboot-envtools kmod-gpio-button-hotplug\n\n$(eval $(call BuildTarget))\n"
  },
  {
    "path": "target/linux/mvebu/base-files/lib/preinit/79_move_config",
    "content": "# Copyright (C) 2015 OpenWrt.org\n\n. /lib/functions.sh\n. /lib/upgrade/common.sh\n\nmove_config() {\n\tlocal partdev\n\n\tif export_bootdevice && export_partdevice partdev 1; then\n\t\tcase $(board_name) in\n\t\t\tcznic,turris-omnia)\n\t\t\tinsmod nls_cp437\n\t\t\tinsmod nls_iso8859-1\n\t\t\tinsmod fat\n\t\t\tinsmod vfat\n\t\t\t;;\n\t\tesac\n\t\tmkdir -p /boot\n\t\tmount -o rw,noatime \"/dev/$partdev\" /boot\n\t\t[ -f \"/boot/$BACKUP_FILE\" ] && mv -f \"/boot/$BACKUP_FILE\" /\n\t\tumount /boot\n\tfi\n}\n\nboot_hook_add preinit_mount_root move_config\n"
  },
  {
    "path": "target/linux/mvebu/config-5.10",
    "content": "CONFIG_AHCI_MVEBU=y\nCONFIG_ALIGNMENT_TRAP=y\nCONFIG_ARCH_32BIT_OFF_T=y\nCONFIG_ARCH_HIBERNATION_POSSIBLE=y\nCONFIG_ARCH_KEEP_MEMBLOCK=y\nCONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y\nCONFIG_ARCH_MULTIPLATFORM=y\nCONFIG_ARCH_MULTI_V6_V7=y\nCONFIG_ARCH_MULTI_V7=y\nCONFIG_ARCH_MVEBU=y\nCONFIG_ARCH_NR_GPIO=0\nCONFIG_ARCH_OPTIONAL_KERNEL_RWX=y\nCONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y\nCONFIG_ARCH_SELECT_MEMORY_MODEL=y\nCONFIG_ARCH_SPARSEMEM_ENABLE=y\nCONFIG_ARCH_SUSPEND_POSSIBLE=y\nCONFIG_ARM=y\nCONFIG_ARMADA_370_CLK=y\nCONFIG_ARMADA_370_XP_IRQ=y\nCONFIG_ARMADA_370_XP_TIMER=y\n# CONFIG_ARMADA_37XX_WATCHDOG is not set\nCONFIG_ARMADA_38X_CLK=y\nCONFIG_ARMADA_THERMAL=y\nCONFIG_ARMADA_XP_CLK=y\nCONFIG_ARM_APPENDED_DTB=y\nCONFIG_ARM_ARCH_TIMER=y\nCONFIG_ARM_ARCH_TIMER_EVTSTREAM=y\n# CONFIG_ARM_ARMADA_37XX_CPUFREQ is not set\n# CONFIG_ARM_ARMADA_8K_CPUFREQ is not set\nCONFIG_ARM_ATAG_DTB_COMPAT=y\n# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER is not set\nCONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE=y\nCONFIG_ARM_CPU_SUSPEND=y\nCONFIG_ARM_CRYPTO=y\nCONFIG_ARM_ERRATA_720789=y\nCONFIG_ARM_ERRATA_764369=y\nCONFIG_ARM_GIC=y\nCONFIG_ARM_GLOBAL_TIMER=y\nCONFIG_ARM_HAS_SG_CHAIN=y\nCONFIG_ARM_HEAVY_MB=y\nCONFIG_ARM_L1_CACHE_SHIFT=6\nCONFIG_ARM_L1_CACHE_SHIFT_6=y\nCONFIG_ARM_MVEBU_V7_CPUIDLE=y\nCONFIG_ARM_PATCH_IDIV=y\nCONFIG_ARM_PATCH_PHYS_VIRT=y\nCONFIG_ARM_THUMB=y\nCONFIG_ARM_UNWIND=y\nCONFIG_ARM_VIRT_EXT=y\nCONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH=y\nCONFIG_ATA=y\nCONFIG_ATAGS=y\nCONFIG_ATA_LEDS=y\nCONFIG_AUTO_ZRELADDR=y\nCONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y\nCONFIG_BLK_DEV_LOOP=y\nCONFIG_BLK_DEV_NVME=y\nCONFIG_BLK_DEV_SD=y\nCONFIG_BLK_MQ_PCI=y\nCONFIG_BLK_SCSI_REQUEST=y\nCONFIG_BOUNCE=y\n# CONFIG_CACHE_FEROCEON_L2 is not set\nCONFIG_CACHE_L2X0=y\nCONFIG_CLKDEV_LOOKUP=y\nCONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK=y\nCONFIG_CLKSRC_MMIO=y\nCONFIG_CLONE_BACKWARDS=y\nCONFIG_COMMON_CLK=y\nCONFIG_COMPAT_32BIT_TIME=y\nCONFIG_CPUFREQ_DT=y\nCONFIG_CPUFREQ_DT_PLATDEV=y\nCONFIG_CPU_32v6K=y\nCONFIG_CPU_32v7=y\nCONFIG_CPU_ABRT_EV7=y\nCONFIG_CPU_CACHE_V7=y\nCONFIG_CPU_CACHE_VIPT=y\nCONFIG_CPU_COPY_V6=y\nCONFIG_CPU_CP15=y\nCONFIG_CPU_CP15_MMU=y\nCONFIG_CPU_FREQ=y\nCONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y\n# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set\nCONFIG_CPU_FREQ_GOV_ATTR_SET=y\nCONFIG_CPU_FREQ_GOV_COMMON=y\n# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set\nCONFIG_CPU_FREQ_GOV_ONDEMAND=y\nCONFIG_CPU_FREQ_GOV_PERFORMANCE=y\n# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set\n# CONFIG_CPU_FREQ_GOV_USERSPACE is not set\nCONFIG_CPU_FREQ_STAT=y\nCONFIG_CPU_HAS_ASID=y\nCONFIG_CPU_IDLE=y\nCONFIG_CPU_IDLE_GOV_LADDER=y\nCONFIG_CPU_PABRT_V7=y\nCONFIG_CPU_PJ4B=y\nCONFIG_CPU_PM=y\nCONFIG_CPU_RMAP=y\nCONFIG_CPU_SPECTRE=y\nCONFIG_CPU_THERMAL=y\nCONFIG_CPU_THUMB_CAPABLE=y\nCONFIG_CPU_TLB_V7=y\nCONFIG_CPU_V7=y\nCONFIG_CRC16=y\nCONFIG_CRYPTO_ACOMP2=y\nCONFIG_CRYPTO_AES_ARM=y\nCONFIG_CRYPTO_AES_ARM_BS=y\nCONFIG_CRYPTO_AUTHENC=y\nCONFIG_CRYPTO_CRC32=y\nCONFIG_CRYPTO_CRC32C=y\nCONFIG_CRYPTO_CRYPTD=y\nCONFIG_CRYPTO_DEFLATE=y\nCONFIG_CRYPTO_DES=y\nCONFIG_CRYPTO_DEV_MARVELL=y\nCONFIG_CRYPTO_DEV_MARVELL_CESA=y\nCONFIG_CRYPTO_ESSIV=y\nCONFIG_CRYPTO_HASH_INFO=y\nCONFIG_CRYPTO_HW=y\nCONFIG_CRYPTO_LIB_DES=y\nCONFIG_CRYPTO_LZO=y\nCONFIG_CRYPTO_NULL=y\nCONFIG_CRYPTO_RNG2=y\nCONFIG_CRYPTO_SHA1=y\nCONFIG_CRYPTO_SHA1_ARM=y\nCONFIG_CRYPTO_SHA1_ARM_NEON=y\nCONFIG_CRYPTO_SHA256_ARM=y\nCONFIG_CRYPTO_SHA512_ARM=y\nCONFIG_CRYPTO_SIMD=y\nCONFIG_DCACHE_WORD_ACCESS=y\nCONFIG_DEBUG_ALIGN_RODATA=y\nCONFIG_DEBUG_INFO=y\nCONFIG_DEBUG_LL=y\nCONFIG_DEBUG_LL_INCLUDE=\"debug/8250.S\"\nCONFIG_DEBUG_MVEBU_UART0=y\n# CONFIG_DEBUG_MVEBU_UART0_ALTERNATE is not set\n# CONFIG_DEBUG_MVEBU_UART1_ALTERNATE is not set\nCONFIG_DEBUG_UART_8250=y\nCONFIG_DEBUG_UART_8250_SHIFT=2\nCONFIG_DEBUG_UART_PHYS=0xd0012000\nCONFIG_DEBUG_UART_VIRT=0xfec12000\nCONFIG_DEBUG_UNCOMPRESS=y\nCONFIG_DEBUG_USER=y\nCONFIG_DMADEVICES=y\nCONFIG_DMA_ENGINE=y\nCONFIG_DMA_ENGINE_RAID=y\nCONFIG_DMA_OF=y\nCONFIG_DMA_OPS=y\nCONFIG_DMA_REMAP=y\nCONFIG_DTC=y\nCONFIG_EARLY_PRINTK=y\nCONFIG_EDAC_ATOMIC_SCRUB=y\nCONFIG_EDAC_SUPPORT=y\nCONFIG_EXT4_FS=y\nCONFIG_EXTCON=y\nCONFIG_F2FS_FS=y\nCONFIG_FIXED_PHY=y\nCONFIG_FIX_EARLYCON_MEM=y\nCONFIG_FS_IOMAP=y\nCONFIG_FS_MBCACHE=y\nCONFIG_FW_LOADER_PAGED_BUF=y\nCONFIG_GENERIC_ALLOCATOR=y\nCONFIG_GENERIC_ARCH_TOPOLOGY=y\nCONFIG_GENERIC_BUG=y\nCONFIG_GENERIC_CLOCKEVENTS=y\nCONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y\nCONFIG_GENERIC_CPU_AUTOPROBE=y\nCONFIG_GENERIC_EARLY_IOREMAP=y\nCONFIG_GENERIC_GETTIMEOFDAY=y\nCONFIG_GENERIC_IDLE_POLL_SETUP=y\nCONFIG_GENERIC_IRQ_CHIP=y\nCONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y\nCONFIG_GENERIC_IRQ_MIGRATION=y\nCONFIG_GENERIC_IRQ_MULTI_HANDLER=y\nCONFIG_GENERIC_IRQ_SHOW=y\nCONFIG_GENERIC_IRQ_SHOW_LEVEL=y\nCONFIG_GENERIC_MSI_IRQ=y\nCONFIG_GENERIC_MSI_IRQ_DOMAIN=y\nCONFIG_GENERIC_PCI_IOMAP=y\nCONFIG_GENERIC_PHY=y\nCONFIG_GENERIC_SCHED_CLOCK=y\nCONFIG_GENERIC_SMP_IDLE_THREAD=y\nCONFIG_GENERIC_STRNCPY_FROM_USER=y\nCONFIG_GENERIC_STRNLEN_USER=y\nCONFIG_GENERIC_TIME_VSYSCALL=y\nCONFIG_GENERIC_VDSO_32=y\nCONFIG_GLOB=y\nCONFIG_GPIOLIB=y\nCONFIG_GPIOLIB_IRQCHIP=y\nCONFIG_GPIO_GENERIC=y\nCONFIG_GPIO_GENERIC_PLATFORM=y\nCONFIG_GPIO_MVEBU=y\nCONFIG_GPIO_PCA953X=y\nCONFIG_GPIO_PCA953X_IRQ=y\nCONFIG_GRO_CELLS=y\nCONFIG_HANDLE_DOMAIN_IRQ=y\nCONFIG_HARDEN_BRANCH_PREDICTOR=y\nCONFIG_HARDIRQS_SW_RESEND=y\nCONFIG_HAS_DMA=y\nCONFIG_HAS_IOMEM=y\nCONFIG_HAS_IOPORT_MAP=y\nCONFIG_HAVE_SMP=y\nCONFIG_HIGHMEM=y\nCONFIG_HIGHPTE=y\nCONFIG_HOTPLUG_CPU=y\nCONFIG_HWBM=y\nCONFIG_HWMON=y\nCONFIG_HW_RANDOM=y\nCONFIG_HZ_FIXED=0\nCONFIG_HZ_PERIODIC=y\nCONFIG_I2C=y\nCONFIG_I2C_BOARDINFO=y\nCONFIG_I2C_CHARDEV=y\nCONFIG_I2C_MV64XXX=y\n# CONFIG_I2C_PXA is not set\nCONFIG_INITRAMFS_SOURCE=\"\"\nCONFIG_IRQCHIP=y\nCONFIG_IRQ_DOMAIN=y\nCONFIG_IRQ_DOMAIN_HIERARCHY=y\nCONFIG_IRQ_FORCED_THREADING=y\nCONFIG_IRQ_WORK=y\n# CONFIG_IWMMXT is not set\nCONFIG_JBD2=y\nCONFIG_LEDS_GPIO=y\nCONFIG_LEDS_PCA963X=y\nCONFIG_LEDS_TLC591XX=y\nCONFIG_LEDS_TRIGGER_DISK=y\nCONFIG_LIBFDT=y\nCONFIG_LOCK_DEBUGGING_SUPPORT=y\nCONFIG_LOCK_SPIN_ON_OWNER=y\nCONFIG_LZO_COMPRESS=y\nCONFIG_LZO_DECOMPRESS=y\nCONFIG_MACH_ARMADA_370=y\n# CONFIG_MACH_ARMADA_375 is not set\nCONFIG_MACH_ARMADA_38X=y\n# CONFIG_MACH_ARMADA_39X is not set\nCONFIG_MACH_ARMADA_XP=y\n# CONFIG_MACH_DOVE is not set\nCONFIG_MACH_MVEBU_ANY=y\nCONFIG_MACH_MVEBU_V7=y\nCONFIG_MAGIC_SYSRQ=y\nCONFIG_MANGLE_BOOTARGS=y\nCONFIG_MARVELL_PHY=y\nCONFIG_MDIO_BUS=y\nCONFIG_MDIO_DEVICE=y\nCONFIG_MDIO_I2C=y\nCONFIG_MEMFD_CREATE=y\nCONFIG_MEMORY=y\nCONFIG_MIGHT_HAVE_CACHE_L2X0=y\nCONFIG_MIGRATION=y\nCONFIG_MMC=y\nCONFIG_MMC_BLOCK=y\nCONFIG_MMC_MVSDIO=y\nCONFIG_MMC_SDHCI=y\n# CONFIG_MMC_SDHCI_PCI is not set\nCONFIG_MMC_SDHCI_PLTFM=y\nCONFIG_MMC_SDHCI_PXAV3=y\nCONFIG_MODULES_USE_ELF_REL=y\nCONFIG_MTD_CFI_STAA=y\nCONFIG_MTD_NAND_CORE=y\nCONFIG_MTD_NAND_ECC=y\nCONFIG_MTD_NAND_ECC_SW_HAMMING=y\nCONFIG_MTD_NAND_MARVELL=y\nCONFIG_MTD_RAW_NAND=y\nCONFIG_MTD_SPI_NOR=y\nCONFIG_MTD_SPLIT_FIRMWARE=y\nCONFIG_MTD_UBI=y\nCONFIG_MTD_UBI_BEB_LIMIT=20\nCONFIG_MTD_UBI_BLOCK=y\nCONFIG_MTD_UBI_WL_THRESHOLD=4096\nCONFIG_MUTEX_SPIN_ON_OWNER=y\nCONFIG_MVEBU_CLK_COMMON=y\nCONFIG_MVEBU_CLK_COREDIV=y\nCONFIG_MVEBU_CLK_CPU=y\nCONFIG_MVEBU_DEVBUS=y\nCONFIG_MVEBU_MBUS=y\nCONFIG_MVMDIO=y\nCONFIG_MVNETA=y\nCONFIG_MVNETA_BM=y\nCONFIG_MVNETA_BM_ENABLE=y\n# CONFIG_MVPP2 is not set\nCONFIG_MV_XOR=y\nCONFIG_NEED_DMA_MAP_STATE=y\nCONFIG_NEON=y\nCONFIG_NET_DEVLINK=y\nCONFIG_NET_DSA=y\nCONFIG_NET_DSA_MV88E6XXX=y\nCONFIG_NET_DSA_MV88E6XXX_GLOBAL2=y\nCONFIG_NET_DSA_TAG_DSA=y\nCONFIG_NET_DSA_TAG_EDSA=y\nCONFIG_NET_FLOW_LIMIT=y\nCONFIG_NET_SWITCHDEV=y\nCONFIG_NLS=y\nCONFIG_NOP_USB_XCEIV=y\nCONFIG_NR_CPUS=4\nCONFIG_NVMEM=y\nCONFIG_NVME_CORE=y\n# CONFIG_NVME_HWMON is not set\n# CONFIG_NVME_MULTIPATH is not set\n# CONFIG_NVME_TCP is not set\nCONFIG_OF=y\nCONFIG_OF_ADDRESS=y\nCONFIG_OF_EARLY_FLATTREE=y\nCONFIG_OF_FLATTREE=y\nCONFIG_OF_GPIO=y\nCONFIG_OF_IRQ=y\nCONFIG_OF_KOBJ=y\nCONFIG_OF_MDIO=y\nCONFIG_OF_NET=y\nCONFIG_OLD_SIGACTION=y\nCONFIG_OLD_SIGSUSPEND3=y\nCONFIG_ORION_WATCHDOG=y\nCONFIG_OUTER_CACHE=y\nCONFIG_OUTER_CACHE_SYNC=y\nCONFIG_PADATA=y\nCONFIG_PAGE_OFFSET=0xC0000000\nCONFIG_PAGE_POOL=y\nCONFIG_PCI=y\nCONFIG_PCI_BRIDGE_EMUL=y\nCONFIG_PCI_DOMAINS=y\nCONFIG_PCI_DOMAINS_GENERIC=y\nCONFIG_PCI_MSI=y\nCONFIG_PCI_MSI_IRQ_DOMAIN=y\nCONFIG_PCI_MVEBU=y\nCONFIG_PERF_USE_VMALLOC=y\nCONFIG_PGTABLE_LEVELS=2\nCONFIG_PHYLIB=y\nCONFIG_PHYLINK=y\n# CONFIG_PHY_MVEBU_A3700_COMPHY is not set\n# CONFIG_PHY_MVEBU_A3700_UTMI is not set\n# CONFIG_PHY_MVEBU_A38X_COMPHY is not set\n# CONFIG_PHY_MVEBU_CP110_COMPHY is not set\nCONFIG_PINCTRL=y\nCONFIG_PINCTRL_ARMADA_370=y\nCONFIG_PINCTRL_ARMADA_38X=y\nCONFIG_PINCTRL_ARMADA_XP=y\nCONFIG_PINCTRL_MVEBU=y\n# CONFIG_PINCTRL_SINGLE is not set\nCONFIG_PJ4B_ERRATA_4742=y\nCONFIG_PL310_ERRATA_753970=y\nCONFIG_PLAT_ORION=y\nCONFIG_PM_OPP=y\nCONFIG_POWER_RESET=y\nCONFIG_POWER_RESET_GPIO=y\nCONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=11\nCONFIG_PWM=y\nCONFIG_PWM_SYSFS=y\nCONFIG_RATIONAL=y\nCONFIG_REGMAP=y\nCONFIG_REGMAP_I2C=y\nCONFIG_REGMAP_MMIO=y\nCONFIG_REGULATOR=y\nCONFIG_REGULATOR_FIXED_VOLTAGE=y\nCONFIG_RFS_ACCEL=y\nCONFIG_RPS=y\nCONFIG_RTC_CLASS=y\nCONFIG_RTC_DRV_ARMADA38X=y\n# CONFIG_RTC_DRV_MV is not set\nCONFIG_RTC_I2C_AND_SPI=y\nCONFIG_RTC_MC146818_LIB=y\nCONFIG_RWSEM_SPIN_ON_OWNER=y\nCONFIG_SATA_AHCI_PLATFORM=y\nCONFIG_SATA_HOST=y\nCONFIG_SATA_MV=y\nCONFIG_SATA_PMP=y\nCONFIG_SCSI=y\nCONFIG_SENSORS_PWM_FAN=y\nCONFIG_SENSORS_TMP421=y\nCONFIG_SERIAL_8250_DW=y\nCONFIG_SERIAL_8250_DWLIB=y\nCONFIG_SERIAL_8250_FSL=y\nCONFIG_SERIAL_MCTRL_GPIO=y\nCONFIG_SERIAL_MVEBU_CONSOLE=y\nCONFIG_SERIAL_MVEBU_UART=y\nCONFIG_SFP=y\nCONFIG_SGL_ALLOC=y\nCONFIG_SG_POOL=y\nCONFIG_SMP=y\nCONFIG_SMP_ON_UP=y\nCONFIG_SOC_BUS=y\nCONFIG_SPARSE_IRQ=y\nCONFIG_SPI=y\n# CONFIG_SPI_ARMADA_3700 is not set\nCONFIG_SPI_MASTER=y\nCONFIG_SPI_MEM=y\nCONFIG_SPI_ORION=y\nCONFIG_SRAM=y\nCONFIG_SRAM_EXEC=y\nCONFIG_SRCU=y\nCONFIG_SWPHY=y\nCONFIG_SWP_EMULATE=y\nCONFIG_SYS_SUPPORTS_APM_EMULATION=y\nCONFIG_THERMAL=y\nCONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y\nCONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0\nCONFIG_THERMAL_GOV_STEP_WISE=y\nCONFIG_THERMAL_HWMON=y\nCONFIG_THERMAL_OF=y\nCONFIG_TICK_CPU_ACCOUNTING=y\nCONFIG_TIMER_OF=y\nCONFIG_TIMER_PROBE=y\nCONFIG_TREE_RCU=y\nCONFIG_TREE_SRCU=y\nCONFIG_UBIFS_FS=y\nCONFIG_UNCOMPRESS_INCLUDE=\"debug/uncompress.h\"\nCONFIG_UNWINDER_ARM=y\nCONFIG_USB=y\nCONFIG_USB_COMMON=y\nCONFIG_USB_EHCI_HCD=y\nCONFIG_USB_EHCI_HCD_ORION=y\nCONFIG_USB_EHCI_HCD_PLATFORM=y\nCONFIG_USB_LEDS_TRIGGER_USBPORT=y\nCONFIG_USB_PHY=y\nCONFIG_USB_STORAGE=y\nCONFIG_USB_SUPPORT=y\nCONFIG_USB_XHCI_HCD=y\nCONFIG_USB_XHCI_MVEBU=y\nCONFIG_USB_XHCI_PLATFORM=y\nCONFIG_USE_OF=y\nCONFIG_VFP=y\nCONFIG_VFPv3=y\nCONFIG_WATCHDOG_CORE=y\nCONFIG_XPS=y\nCONFIG_XZ_DEC_ARM=y\nCONFIG_XZ_DEC_BCJ=y\nCONFIG_ZBOOT_ROM_BSS=0x0\nCONFIG_ZBOOT_ROM_TEXT=0x0\nCONFIG_ZLIB_DEFLATE=y\nCONFIG_ZLIB_INFLATE=y\n"
  },
  {
    "path": "target/linux/mvebu/cortexa53/base-files/etc/board.d/01_leds",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n\n. /lib/functions/uci-defaults.sh\n\nboard_config_update\n\nboard=$(board_name)\n\ncase \"$board\" in\nglinet,gl-mv1000)\n\tucidef_set_led_netdev \"wan\" \"WAN\" \"green:wan\" \"wan\"\n\t;;\nesac\n\nboard_config_flush\n\nexit 0\n"
  },
  {
    "path": "target/linux/mvebu/cortexa53/base-files/etc/board.d/02_network",
    "content": "#\n# Copyright (C) 2014-2016 OpenWrt.org\n# Copyright (C) 2016 LEDE-Project.org\n#\n\n. /lib/functions/uci-defaults.sh\n\nboard_config_update\n\nboard=$(board_name)\n\ncase \"$board\" in\nglinet,gl-mv1000|\\\nglobalscale,espressobin|\\\nglobalscale,espressobin-emmc|\\\nglobalscale,espressobin-v7|\\\nglobalscale,espressobin-v7-emmc)\n\tucidef_set_interfaces_lan_wan \"lan0 lan1\" \"wan\"\n\t;;\nglobalscale,espressobin-ultra)\n\tucidef_set_interfaces_lan_wan \"lan0 lan1 lan2 lan3\" \"wan\"\n\t;;\nmarvell,armada-3720-db|\\\nmethode,udpu)\n\tucidef_set_interfaces_lan_wan \"eth1\" \"eth0\"\n\t;;\n*)\n\tucidef_set_interface_lan \"eth0\"\n\t;;\nesac\n\nboard_config_flush\n\nexit 0\n"
  },
  {
    "path": "target/linux/mvebu/cortexa53/base-files/lib/preinit/82_uDPU",
    "content": "#\n# Copyright (C) 2014-2019 OpenWrt.org\n# Copyright (C) 2016 LEDE-Project.org\n#\n\npreinit_mount_udpu() {\n\t. /lib/functions.sh\n\t. /lib/upgrade/common.sh\n\n\tcase $(board_name) in\n\tmethode,udpu)\n\t\t# Check which device is detected\n\t\t[ -b \"/dev/mmcblk0\" ] && mmcdev=\"/dev/mmcblk0\" || mmcdev=\"/dev/mmcblk1\"\n\n\t\tif [ -b \"${mmcdev}p4\" ]; then\n\t\t\tmkdir /misc\n\t\t\tmount -t f2fs ${mmcdev}p4 /misc\n\t\t\t[ -f \"/misc/$BACKUP_FILE\" ] && {\n\t\t\t\techo \"- Restoring configuration files -\"\n\t\t\t\ttar xzf \"/misc/$BACKUP_FILE\" -C /\n\t\t\t\trm -f \"/misc/$BACKUP_FILE\"\n\t\t\t\tsync\n\t\t\t}\n\t\t\t[ -f \"/misc/firmware/recovery.itb\" ] && {\n\t\t\t\t\techo \"- Updating /recovery partition -\"\n\t\t\t\t\tmkfs.ext4 -q ${mmcdev}p2 | echo y &> /dev/null\n\t\t\t\t\tmkdir -p /tmp/recovery\n\t\t\t\t\tmount ${mmcdev}p2 /tmp/recovery\n\t\t\t\t\tcp /misc/firmware/recovery.itb /tmp/recovery\n\t\t\t\t\t[ -f \"/misc/firmware/boot.scr\" ] && \\\n\t\t\t\t\t\tcp /misc/firmware/boot.scr /tmp/recovery\n\t\t\t\t\tsync\n\t\t\t\t\tumount /tmp/recovery\n\t\t\t\t\trm -rf /tmp/recovery\n\n\t\t\t\t\t# Replace previous backup with the new one\n\t\t\t\t\t[ -d \"/misc/firmware_old\" ] && rm -rf /misc/firmware_old\n\t\t\t\t\t[ -d \"/misc/firmware\" ] && mv /misc/firmware /misc/firmware_old\n\t\t\t\t}\n\t\tfi\n\n\t\t# Legacy support - if rootfs was booted, instruct u-boot to keep the current root dev\n\t\t[ \"$(df | grep /dev/root)\" ] && fw_setenv root_ok '2'\n\t;;\n\tesac\n}\n\nboot_hook_add preinit_main preinit_mount_udpu\n"
  },
  {
    "path": "target/linux/mvebu/cortexa53/base-files/lib/upgrade/platform.sh",
    "content": "#\n# Copyright (C) 2014-2016 OpenWrt.org\n# Copyright (C) 2016 LEDE-Project.org\n#\n\nRAMFS_COPY_BIN='fw_printenv fw_setenv'\nRAMFS_COPY_DATA='/etc/fw_env.config /var/lock/fw_printenv.lock'\nREQUIRE_IMAGE_METADATA=1\n\nplatform_check_image() {\n\tcase \"$(board_name)\" in\n\tglinet,gl-mv1000|\\\n\tglobalscale,espressobin|\\\n\tglobalscale,espressobin-emmc|\\\n\tglobalscale,espressobin-ultra|\\\n\tglobalscale,espressobin-v7|\\\n\tglobalscale,espressobin-v7-emmc)\n\t\tlegacy_sdcard_check_image \"$1\"\n\t\t;;\n\t*)\n\t\treturn 0\n\t\t;;\n\tesac\n}\n\nplatform_do_upgrade() {\n\tcase \"$(board_name)\" in\n\tglinet,gl-mv1000|\\\n\tglobalscale,espressobin|\\\n\tglobalscale,espressobin-emmc|\\\n\tglobalscale,espressobin-ultra|\\\n\tglobalscale,espressobin-v7|\\\n\tglobalscale,espressobin-v7-emmc)\n\t\tlegacy_sdcard_do_upgrade \"$1\"\n\t\t;;\n\tmethode,udpu)\n\t\tplatform_do_upgrade_uDPU \"$1\"\n\t\t;;\n\t*)\n\t\tdefault_do_upgrade \"$1\"\n\t\t;;\n\tesac\n}\nplatform_copy_config() {\n\tcase \"$(board_name)\" in\n\tglinet,gl-mv1000|\\\n\tglobalscale,espressobin|\\\n\tglobalscale,espressobin-emmc|\\\n\tglobalscale,espressobin-ultra|\\\n\tglobalscale,espressobin-v7|\\\n\tglobalscale,espressobin-v7-emmc)\n\t\tlegacy_sdcard_copy_config\n\t\t;;\n\tmethode,udpu)\n\t\tplatform_copy_config_uDPU\n\t\t;;\n\tesac\n}\n"
  },
  {
    "path": "target/linux/mvebu/cortexa53/base-files/lib/upgrade/uDPU.sh",
    "content": "udpu_check_emmc() {\n# uDPU uses combined ext4 and f2fs partitions.\n# partition layout:\n#\t1. boot\t(ext4)\n#\t2. recovery  (ext4)\n#\t3. rootfs (f2fs)\n#\t4. misc (f2fs)\n\n\t# Check which device is available, depending on the board revision\n\tif [ -b \"/dev/mmcblk1\" ]; then\n\t\temmc_dev=/dev/mmcblk1\n\telif [ -b \"/dev/mmcblk0\" ]; then\n\t\temmc_dev=/dev/mmcblk0\n\telse\n\t\techo \"Cannot detect eMMC flash, aborting..\"\n\t\texit 1\n\tfi\n}\n\nudpu_part_prep() {\n\t if [ \"$(grep $1 /proc/mounts)\" ]; then\n\t\tmounted_part=\"$(grep $1 /proc/mounts | awk '{print $2}' | head -1)\"\n\t\tumount $mounted_part\n\t\t[ \"$(grep -wo $mounted_part /proc/mounts)\" ] && umount -l $mounted_part\n\tfi\n}\n\nudpu_do_part_check() {\n\tlocal emmc_parts=\"1 2 3 4\"\n\tlocal part_valid=\"1\"\n\n\t# Check if the block devices exist\n\tfor num in ${emmc_parts}; do\n\t\t[ ! -b ${emmc_dev}p${num} ] && part_valid=\"0\"\n\tdone\n\n\t# If partitions are missing create a new partition table\n\tif [ \"$part_valid\" != \"1\" ]; then\n\t\tprintf \"Invalid partition table, creating a new one\\n\"\n\t\tprintf \"o\\nn\\np\\n1\\n\\n+256M\\nn\\np\\n2\\n\\n+256M\\nn\\np\\n3\\n\\n+1536M\\nn\\np\\n\\n\\nw\\n\" | fdisk -W always $emmc_dev  > /dev/null 2>&1\n\n\t\t# Format the /misc part right away as we will need it for the firmware\n\t\tprintf \"Formating /misc partition, this make take a while..\\n\"\n\t\tudpu_part_prep ${emmc_dev}p4\n\t\tmkfs.f2fs -q -l misc ${emmc_dev}p4\n\t\t[ $? -eq 0 ] && printf \"/misc partition formated successfully\\n\" || printf \"/misc partition formatting failed\\n\"\n\n\t\tudpu_do_initial_setup\n\telse\n\t\tprintf \"Partition table looks ok\\n\"\n\tfi\n}\n\nudpu_do_misc_prep() {\n\tif [ ! \"$(grep -wo /misc /proc/mounts)\" ]; then\n\t\tmkdir -p /misc\n\t\tmount ${emmc_dev}p4 /misc\n\n\t\t# If the mount fails, try to reformat partition\n\t\t# Leaving possiblity for multiple iterations\n\t\tif [ $? -ne 0 ]; then\n\t\t\tprintf \"Error while mounting /misc, trying to reformat..\\n\"\n\n\t\t\tformat_count=0\n\t\t\twhile [ \"$format_count\" -lt \"1\" ]; do\n\t\t\t\tudpu_part_prep ${emmc_dev}p4\n\t\t\t\tmkfs.f2fs -q -l misc ${emmc_dev}p4\n\t\t\t\tmount ${emmc_dev}p4 /misc\n\t\t\t\tif [ $? -ne 0 ]; then\n\t\t\t\t\tumount -l /misc\n\t\t\t\t\tprintf \"Failed while mounting /misc\\n\"\n\t\t\t\t\tformat_count=$((format_count +1))\n\t\t\t\telse\n\t\t\t\t\tprintf \"Mounted /misc successfully\\n\"\n\t\t\t\t\tbreak\n\t\t\t\tfi\n\t\t\tdone\n\t\tfi\n\tfi\n}\n\nudpu_do_initial_setup() {\n\t# Prepare /recovery parition\n\tudpu_part_prep ${emmc_dev}p2\n\tmkfs.ext4 -q ${emmc_dev}p2 | echo y &> /dev/null\n\n\t# Prepare /boot partition\n\tudpu_part_prep ${emmc_dev}p1\n\tmkfs.ext4 -q ${emmc_dev}p1 | echo y &> /dev/null\n\n\t# Prepare /root partition\n\tprintf \"Formating /root partition, this may take a while..\\n\"\n\tudpu_part_prep ${emmc_dev}p3\n\tmkfs.f2fs -q -l rootfs ${emmc_dev}p3\n\t[ $? -eq 0 ] && printf \"/root partition reformated\\n\"\n}\n\nudpu_do_regular_upgrade() {\n\t# Clean /boot partition - mfks.ext4 is not available in chroot\n\t[ \"$(grep -wo /boot /proc/mounts)\" ] && umount /boot\n\tmkdir -p /tmp/boot\n\tmount ${emmc_dev}p1 /tmp/boot\n\trm -rf /tmp/boot/*\n\n\t# Clean /root partition - mkfs.f2fs is not available in chroot\n\t[ \"$(grep -wo /dev/root /proc/mounts)\" ] && umount /\n\tmkdir -p /tmp/rootpart\n\tmount ${emmc_dev}p3 /tmp/rootpart\n\trm -rf /tmp/rootpart/*\n}\n\nplatform_do_upgrade_uDPU() {\n\tudpu_check_emmc\n\n\t# Prepare and extract firmware on /misc partition\n\tudpu_do_misc_prep\n\n\t[ -f \"/misc/firmware\" ] && rm -r /misc/firmware\n\tmkdir -p /misc/firmware\n\ttar xzf \"$1\" -C /misc/firmware/\n\n\tudpu_do_regular_upgrade\n\n\tprintf \"Updating /boot partition\\n\"\n\ttar xzf /misc/firmware/boot.tgz -C /tmp/boot\n\t[ $? -eq 0 ] && printf \"/boot partition updated successfully\\n\" || printf \"/boot partition update failed\\n\"\n\tsync\n\n\tprintf \"Updating /root partition\\n\"\n\ttar xzf /misc/firmware/rootfs.tgz -C /tmp/rootpart\n\t[ $? -eq 0 ] && printf \"/root partition updated successfully\\n\" || printf \"/root partition update failed\\n\"\n\tsync\n\n\t# Saving configuration files over sysupgrade\n\tplatform_copy_config_uDPU\n\n\t# Remove tmp mounts\n\ttmp_parts=$(grep \"${emmc_dev}\" /proc/mounts | awk '{print $2}')\n\tfor part in ${tmp_parts}; do\n\t\tumount $part\n\t\t# Force umount is necessary\n\t\t[ \"$(grep \"${part}\" /proc/mounts)\" ] && umount -l $part\n\tdone\n\n\t# Sysupgrade complains about /tmp and /dev, so we can detach them here\n\tumount -l /tmp\n\tumount -l /dev\n}\n\nplatform_copy_config_uDPU() {\n\t# Config is saved on the /misc partition and copied on the rootfs after the reboot\n\tif [ -f \"$UPGRADE_BACKUP\" ]; then\n\t\tcp -f \"$UPGRADE_BACKUP\" \"/misc/$BACKUP_FILE\"\n\t\tsync\n\tfi\n}\n"
  },
  {
    "path": "target/linux/mvebu/cortexa53/config-5.10",
    "content": "CONFIG_64BIT=y\nCONFIG_ARCH_DMA_ADDR_T_64BIT=y\nCONFIG_ARCH_MMAP_RND_BITS=18\nCONFIG_ARCH_MMAP_RND_BITS_MAX=24\nCONFIG_ARCH_MMAP_RND_BITS_MIN=18\nCONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11\nCONFIG_ARCH_PROC_KCORE_TEXT=y\nCONFIG_ARCH_SPARSEMEM_DEFAULT=y\nCONFIG_ARCH_STACKWALK=y\nCONFIG_ARM64=y\nCONFIG_ARM64_4K_PAGES=y\nCONFIG_ARM64_PAGE_SHIFT=12\nCONFIG_ARM64_PA_BITS=48\nCONFIG_ARM64_PA_BITS_48=y\nCONFIG_ARM64_PTR_AUTH=y\nCONFIG_ARM64_SVE=y\nCONFIG_ARM64_TAGGED_ADDR_ABI=y\nCONFIG_ARM64_VA_BITS=39\nCONFIG_ARM64_VA_BITS_39=y\nCONFIG_ARMADA_37XX_CLK=y\nCONFIG_ARMADA_37XX_WATCHDOG=y\nCONFIG_ARMADA_37XX_RWTM_MBOX=y\nCONFIG_ARMADA_AP806_SYSCON=y\nCONFIG_ARMADA_AP_CP_HELPER=y\nCONFIG_ARMADA_CP110_SYSCON=y\nCONFIG_ARM_AMBA=y\nCONFIG_ARM_ARMADA_37XX_CPUFREQ=y\nCONFIG_ARM_GIC_V2M=y\nCONFIG_ARM_GIC_V3=y\nCONFIG_ARM_GIC_V3_ITS=y\nCONFIG_ARM_GIC_V3_ITS_PCI=y\n# CONFIG_ARM_PL172_MPMC is not set\nCONFIG_ARM_PSCI_FW=y\nCONFIG_AUDIT_ARCH_COMPAT_GENERIC=y\nCONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y\nCONFIG_DMA_DIRECT_REMAP=y\n# CONFIG_FLATMEM_MANUAL is not set\nCONFIG_FRAME_POINTER=y\nCONFIG_GENERIC_BUG_RELATIVE_POINTERS=y\nCONFIG_GENERIC_CPU_VULNERABILITIES=y\nCONFIG_GENERIC_CSUM=y\nCONFIG_GENERIC_PINCONF=y\nCONFIG_HOLES_IN_ZONE=y\nCONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000\nCONFIG_MAILBOX=y\n# CONFIG_MAILBOX_TEST is not set\nCONFIG_MFD_SYSCON=y\nCONFIG_MMC_SDHCI_XENON=y\nCONFIG_MODULES_USE_ELF_RELA=y\nCONFIG_MVEBU_GICP=y\nCONFIG_MVEBU_ICU=y\nCONFIG_MVEBU_ODMI=y\nCONFIG_MVEBU_PIC=y\nCONFIG_MVEBU_SEI=y\nCONFIG_NEED_SG_DMA_LENGTH=y\nCONFIG_PARTITION_PERCPU=y\nCONFIG_PCI_AARDVARK=y\nCONFIG_PGTABLE_LEVELS=3\nCONFIG_PHYS_ADDR_T_64BIT=y\nCONFIG_PHY_MVEBU_A3700_COMPHY=y\nCONFIG_PHY_MVEBU_A3700_UTMI=y\nCONFIG_PINCTRL_ARMADA_37XX=y\nCONFIG_PINCTRL_ARMADA_AP806=y\nCONFIG_PINCTRL_ARMADA_CP110=y\nCONFIG_POWER_SUPPLY=y\nCONFIG_QUEUED_RWLOCKS=y\nCONFIG_QUEUED_SPINLOCKS=y\nCONFIG_REGULATOR_GPIO=y\nCONFIG_RODATA_FULL_DEFAULT_ENABLED=y\nCONFIG_SPARSEMEM=y\nCONFIG_SPARSEMEM_EXTREME=y\nCONFIG_SPARSEMEM_MANUAL=y\nCONFIG_SPARSEMEM_VMEMMAP=y\nCONFIG_SPARSEMEM_VMEMMAP_ENABLE=y\nCONFIG_SPI_ARMADA_3700=y\nCONFIG_SWIOTLB=y\nCONFIG_SYSCTL_EXCEPTION_TRACE=y\nCONFIG_SYS_SUPPORTS_HUGETLBFS=y\nCONFIG_THREAD_INFO_IN_TASK=y\nCONFIG_TURRIS_MOX_RWTM=y\nCONFIG_UNMAP_KERNEL_AT_EL0=y\nCONFIG_VMAP_STACK=y\nCONFIG_ZONE_DMA32=y\n"
  },
  {
    "path": "target/linux/mvebu/cortexa53/target.mk",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2017 Hauke Mehrtens\n\ninclude $(TOPDIR)/rules.mk\n\nARCH:=aarch64\nBOARDNAME:=Marvell Armada 3700LP (ARM64)\nCPU_TYPE:=cortex-a53\nFEATURES+=ext4\nDEFAULT_PACKAGES+=e2fsprogs ethtool mkf2fs partx-utils\n\nKERNELNAME:=Image dtbs\n"
  },
  {
    "path": "target/linux/mvebu/cortexa72/base-files/etc/board.d/01_leds",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n\n. /lib/functions/uci-defaults.sh\n\nboard_config_update\n\nboard=$(board_name)\n\ncase \"$board\" in\niei,puzzle-m901)\n\tucidef_set_led_netdev \"wan\" \"WAN\" \"white:network\" \"eth0\" \"link\"\n\t;;\niei,puzzle-m902)\n\tucidef_set_led_netdev \"wan\" \"WAN\" \"white:network\" \"eth2\" \"link\"\n\t;;\nesac\n\nboard_config_flush\n\nexit 0\n"
  },
  {
    "path": "target/linux/mvebu/cortexa72/base-files/etc/board.d/02_network",
    "content": "#\n# Copyright (C) 2014-2016 OpenWrt.org\n# Copyright (C) 2016 LEDE-Project.org\n#\n\n. /lib/functions/uci-defaults.sh\n\nboard_config_update\n\nboard=$(board_name)\n\ncase \"$board\" in\nglobalscale,mochabin)\n\tucidef_set_interfaces_lan_wan \"lan0 lan1 lan2 lan3\" \"eth0 eth2\"\n\t;;\niei,puzzle-m901)\n\tucidef_set_interfaces_lan_wan \"eth1 eth2 eth3 eth4 eth5\" \"eth0\"\n\t;;\niei,puzzle-m902)\n\tucidef_set_interfaces_lan_wan \"eth0 eth1 eth3 eth4 eth5 eth6 eth7 eth8\" \"eth2\"\n\t;;\nmarvell,armada8040-mcbin-doubleshot|\\\nmarvell,armada8040-mcbin-singleshot)\n\tucidef_set_interfaces_lan_wan \"eth0 eth1 eth3\" \"eth2\"\n\t;;\nmarvell,armada8040-db)\n\tucidef_set_interfaces_lan_wan \"eth0 eth2 eth3\" \"eth1\"\n\t;;\nmarvell,armada7040-db)\n\tucidef_set_interfaces_lan_wan \"eth0 eth2\" \"eth1\"\n\t;;\n*)\n\tucidef_set_interface_lan \"eth0\"\n\t;;\nesac\n\nboard_config_flush\n\nexit 0\n"
  },
  {
    "path": "target/linux/mvebu/cortexa72/base-files/lib/upgrade/emmc-puzzle.sh",
    "content": "platform_do_upgrade_emmc() {\n\tlocal board=$(board_name)\n\tlocal diskdev partdev\n\n\texport_bootdevice && export_partdevice diskdev 0 || {\n\t\tv \"Unable to determine upgrade device\"\n\t\treturn 1\n\t}\n\tsync\n\tif [ \"$UPGRADE_OPT_SAVE_PARTITIONS\" = \"1\" ]; then\n\t\tget_partitions \"/dev/$diskdev\" bootdisk\n\t\tv \"Extract boot sector from the image\"\n\t\tget_image_dd \"$1\" of=/tmp/image.bs count=1 bs=512b\n\t\tget_partitions /tmp/image.bs image\n\tfi\n\n\t#iterate over each partition from the image and write it to the boot disk\n\twhile read part start size; do\n\t\tif export_partdevice partdev $part; then\n\t\t\tif [ \"$partdev\" = \"mmcblk0p2\" ]; then\n\t\t\t\tv \"Writing image mmcblk0p3 for /dev/$partdev  $start $size\"\n\t\t\t\tget_image_dd \"$1\" of=\"/dev/mmcblk0p3\" ibs=\"512\" obs=1M skip=\"$start\" count=\"$size\" conv=fsync\n\t\t\telif [ \"$partdev\" = \"mmcblk0p1\" ]; then\n\t\t\t\tv \"Writing image mmcblk0p1 for /dev/$partdev $start $size\"\n\t\t\t\tget_image_dd \"$1\" of=\"/dev/$partdev\" ibs=\"512\" obs=1M skip=\"$start\" count=\"$size\" conv=fsync\n\t\t\tfi\n\t\telse\n\t\t\tv \"Unable to find partition $part device, skipped.\"\n\t\tfi\n\tdone < /tmp/partmap.image\n\n\tv \"Writing new UUID to /dev/$diskdev...\"\n\tget_image_dd \"$1\" of=\"/dev/$diskdev\" bs=1 skip=440 count=4 seek=440 conv=fsync\n\n\tsleep 1\n}\n"
  },
  {
    "path": "target/linux/mvebu/cortexa72/base-files/lib/upgrade/platform.sh",
    "content": "#\n# Copyright (C) 2014-2016 OpenWrt.org\n# Copyright (C) 2016 LEDE-Project.org\n#\n\nRAMFS_COPY_BIN='fw_printenv fw_setenv'\nRAMFS_COPY_DATA='/etc/fw_env.config /var/lock/fw_printenv.lock'\nREQUIRE_IMAGE_METADATA=1\n\nplatform_check_image() {\n\tcase \"$(board_name)\" in\n\tglobalscale,mochabin|\\\n\tiei,puzzle-m901|\\\n\tiei,puzzle-m902|\\\n\tmarvell,armada8040-mcbin-doubleshot|\\\n\tmarvell,armada8040-mcbin-singleshot)\n\t\tlegacy_sdcard_check_image \"$1\"\n\t\t;;\n\t*)\n\t\treturn 0\n\t\t;;\n\tesac\n}\n\nplatform_do_upgrade() {\n\tcase \"$(board_name)\" in\n\tiei,puzzle-m901|\\\n\tiei,puzzle-m902)\n\t\tplatform_do_upgrade_emmc \"$1\"\n\t\t;;\n\tglobalscale,mochabin|\\\n\tmarvell,armada8040-mcbin-doubleshot|\\\n\tmarvell,armada8040-mcbin-singleshot)\n\t\tlegacy_sdcard_do_upgrade \"$1\"\n\t\t;;\n\t*)\n\t\tdefault_do_upgrade \"$1\"\n\t\t;;\n\tesac\n}\nplatform_copy_config() {\n\tcase \"$(board_name)\" in\n\tglobalscale,mochabin|\\\n\tiei,puzzle-m901|\\\n\tiei,puzzle-m902|\\\n\tmarvell,armada8040-mcbin-doubleshot|\\\n\tmarvell,armada8040-mcbin-singleshot)\n\t\tlegacy_sdcard_copy_config\n\t\t;;\n\tesac\n}\n"
  },
  {
    "path": "target/linux/mvebu/cortexa72/config-5.10",
    "content": "CONFIG_64BIT=y\nCONFIG_AQUANTIA_PHY=y\nCONFIG_ARCH_DMA_ADDR_T_64BIT=y\nCONFIG_ARCH_MMAP_RND_BITS=18\nCONFIG_ARCH_MMAP_RND_BITS_MAX=24\nCONFIG_ARCH_MMAP_RND_BITS_MIN=18\nCONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11\nCONFIG_ARCH_PROC_KCORE_TEXT=y\nCONFIG_ARCH_SPARSEMEM_DEFAULT=y\nCONFIG_ARCH_STACKWALK=y\nCONFIG_ARM64=y\nCONFIG_ARM64_4K_PAGES=y\nCONFIG_ARM64_PAGE_SHIFT=12\nCONFIG_ARM64_PA_BITS=48\nCONFIG_ARM64_PA_BITS_48=y\n# CONFIG_ARM64_PTR_AUTH is not set\nCONFIG_ARM64_SVE=y\n# CONFIG_ARM64_TAGGED_ADDR_ABI is not set\nCONFIG_ARM64_VA_BITS=39\nCONFIG_ARM64_VA_BITS_39=y\nCONFIG_ARMADA_37XX_CLK=y\nCONFIG_ARMADA_AP806_SYSCON=y\nCONFIG_ARMADA_AP_CP_HELPER=y\nCONFIG_ARMADA_CP110_SYSCON=y\nCONFIG_ARM_AMBA=y\nCONFIG_ARM_ARMADA_8K_CPUFREQ=y\nCONFIG_ARM_GIC_V2M=y\nCONFIG_ARM_GIC_V3=y\nCONFIG_ARM_GIC_V3_ITS=y\nCONFIG_ARM_GIC_V3_ITS_PCI=y\n# CONFIG_ARM_PL172_MPMC is not set\nCONFIG_ARM_PSCI_FW=y\nCONFIG_AUDIT_ARCH_COMPAT_GENERIC=y\nCONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y\nCONFIG_CRYPTO_ZSTD=y\nCONFIG_DMA_DIRECT_REMAP=y\n# CONFIG_FLATMEM_MANUAL is not set\nCONFIG_FRAME_POINTER=y\nCONFIG_GENERIC_BUG_RELATIVE_POINTERS=y\nCONFIG_GENERIC_CPU_VULNERABILITIES=y\nCONFIG_GENERIC_CSUM=y\nCONFIG_GENERIC_PINCONF=y\nCONFIG_HOLES_IN_ZONE=y\nCONFIG_HW_RANDOM_OMAP=y\nCONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000\nCONFIG_LEDS_IS31FL319X=y\nCONFIG_LEDS_IEI_WT61P803_PUZZLE=y\nCONFIG_MARVELL_10G_PHY=y\nCONFIG_MDIO_DEVRES=y\nCONFIG_MFD_IEI_WT61P803_PUZZLE=y\nCONFIG_MFD_SYSCON=y\nCONFIG_MMC_SDHCI_XENON=y\nCONFIG_MODULES_USE_ELF_RELA=y\nCONFIG_MVEBU_GICP=y\nCONFIG_MVEBU_ICU=y\nCONFIG_MVEBU_ODMI=y\nCONFIG_MVEBU_PIC=y\nCONFIG_MVEBU_SEI=y\nCONFIG_MVPP2=y\nCONFIG_MV_XOR_V2=y\nCONFIG_NEED_SG_DMA_LENGTH=y\nCONFIG_PARTITION_PERCPU=y\nCONFIG_PCIEAER=y\nCONFIG_PCIEPORTBUS=y\nCONFIG_PCIE_ARMADA_8K=y\nCONFIG_PCIE_DW=y\nCONFIG_PCIE_DW_HOST=y\n# CONFIG_PCI_AARDVARK is not set\nCONFIG_PGTABLE_LEVELS=3\nCONFIG_PHYS_ADDR_T_64BIT=y\nCONFIG_PHY_MVEBU_CP110_COMPHY=y\nCONFIG_PINCTRL_ARMADA_37XX=y\nCONFIG_PINCTRL_ARMADA_AP806=y\nCONFIG_PINCTRL_ARMADA_CP110=y\nCONFIG_POWER_SUPPLY=y\nCONFIG_QUEUED_RWLOCKS=y\nCONFIG_QUEUED_SPINLOCKS=y\nCONFIG_RAS=y\n# CONFIG_RAVE_SP_CORE is not set\nCONFIG_REGULATOR_GPIO=y\n# CONFIG_RODATA_FULL_DEFAULT_ENABLED is not set\nCONFIG_SENSORS_IEI_WT61P803_PUZZLE_HWMON=y\nCONFIG_SERIAL_DEV_BUS=y\nCONFIG_SERIAL_DEV_CTRL_TTYPORT=y\nCONFIG_SPARSEMEM=y\nCONFIG_SPARSEMEM_EXTREME=y\nCONFIG_SPARSEMEM_MANUAL=y\nCONFIG_SPARSEMEM_VMEMMAP=y\nCONFIG_SPARSEMEM_VMEMMAP_ENABLE=y\nCONFIG_SWIOTLB=y\nCONFIG_SYSCTL_EXCEPTION_TRACE=y\nCONFIG_SYS_SUPPORTS_HUGETLBFS=y\nCONFIG_THREAD_INFO_IN_TASK=y\nCONFIG_UNMAP_KERNEL_AT_EL0=y\nCONFIG_VMAP_STACK=y\nCONFIG_XXHASH=y\nCONFIG_ZONE_DMA32=y\nCONFIG_ZSTD_COMPRESS=y\nCONFIG_ZSTD_DECOMPRESS=y\n"
  },
  {
    "path": "target/linux/mvebu/cortexa72/target.mk",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2018 Sartura Ltd.\n\ninclude $(TOPDIR)/rules.mk\n\nARCH:=aarch64\nBOARDNAME:=Marvell Armada 7k/8k (ARM64)\nCPU_TYPE:=cortex-a72\nFEATURES+=ext4\nDEFAULT_PACKAGES+=e2fsprogs ethtool mkf2fs partx-utils\n\nKERNELNAME:=Image dtbs\n"
  },
  {
    "path": "target/linux/mvebu/cortexa9/base-files/etc/board.d/01_leds",
    "content": "#\n# Copyright (C) 2014-2016 OpenWrt.org\n# Copyright (C) 2016 LEDE-Project.org\n#\n\n. /lib/functions/uci-defaults.sh\n\nboard_config_update\n\nboard=$(board_name)\nboardname=\"${board##*,}\"\n\ncase \"$board\" in\nctera,c200-v2)\n\tucidef_set_led_usbport \"usb2\" \"USB2\" \"green:usb-2\" \"usb1-port1\" \"usb2-port1\"\n\tucidef_set_led_usbport \"usb3\" \"USB3\" \"green:usb-1\" \"usb1-port2\" \"usb2-port2\"\n\t;;\nkobol,helios4)\n\tucidef_set_led_usbport \"USB\" \"USB\" \"helios4:green:usb\" \"usb1-port1\" \"usb2-port1\" \"usb3-port1\" \"usb4-port1\" \"usb5-port1\"\n\t;;\nlinksys,wrt1200ac)\n\tucidef_set_led_netdev \"wan\" \"WAN\" \"pca963x:caiman:white:wan\" \"wan\"\n\tucidef_set_led_usbport \"usb1\" \"USB 1\" \"pca963x:caiman:white:usb2\" \"usb1-port1\"\n\tucidef_set_led_usbport \"usb2\" \"USB 2\" \"pca963x:caiman:white:usb3_1\" \"usb2-port1\" \"usb3-port1\"\n\tucidef_set_led_usbport \"usb2_ss\" \"USB 2 SS\" \"pca963x:caiman:white:usb3_2\" \"usb3-port1\"\n\t;;\nlinksys,wrt1900ac-v1)\n\tucidef_set_led_netdev \"wan\" \"WAN\" \"mamba:white:wan\" \"wan\"\n\tucidef_set_led_usbport \"usb1\" \"USB 1\" \"mamba:white:usb2\" \"usb1-port1\"\n\tucidef_set_led_usbport \"usb2\" \"USB 2\" \"mamba:white:usb3_1\" \"usb2-port1\" \"usb3-port1\"\n\tucidef_set_led_usbport \"usb2_ss\" \"USB 2 SS\" \"mamba:white:usb3_2\" \"usb3-port2\"\n\t;;\nlinksys,wrt1900ac-v2)\n\tucidef_set_led_netdev \"wan\" \"WAN\" \"pca963x:cobra:white:wan\" \"wan\"\n\tucidef_set_led_usbport \"usb1\" \"USB 1\" \"pca963x:cobra:white:usb2\" \"usb1-port1\"\n\tucidef_set_led_usbport \"usb2\" \"USB 2\" \"pca963x:cobra:white:usb3_1\" \"usb2-port1\" \"usb3-port1\"\n\tucidef_set_led_usbport \"usb2_ss\" \"USB 2 SS\" \"pca963x:cobra:white:usb3_2\" \"usb3-port1\"\n\t;;\nlinksys,wrt1900acs)\n\tucidef_set_led_netdev \"wan\" \"WAN\" \"pca963x:shelby:white:wan\" \"wan\"\n\tucidef_set_led_usbport \"usb1\" \"USB 1\" \"pca963x:shelby:white:usb2\" \"usb1-port1\"\n\tucidef_set_led_usbport \"usb2\" \"USB 2\" \"pca963x:shelby:white:usb3_1\" \"usb2-port1\" \"usb3-port1\"\n\tucidef_set_led_usbport \"usb2_ss\" \"USB 2 SS\" \"pca963x:shelby:white:usb3_2\" \"usb3-port1\"\n\t;;\nlinksys,wrt3200acm)\n\tucidef_set_led_netdev \"wan\" \"WAN\" \"pca963x:rango:white:wan\" \"wan\"\n\tucidef_set_led_usbport \"usb1\" \"USB 1\" \"pca963x:rango:white:usb2\" \"usb1-port1\"\n\tucidef_set_led_usbport \"usb2\" \"USB 2\" \"pca963x:rango:white:usb3_1\" \"usb2-port1\" \"usb3-port1\"\n\tucidef_set_led_usbport \"usb2_ss\" \"USB 2 SS\" \"pca963x:rango:white:usb3_2\" \"usb3-port1\"\n\t;;\nlinksys,wrt32x)\n\tucidef_set_led_netdev \"wan\" \"WAN\" \"pca963x:venom:blue:wan\" \"wan\"\n\tucidef_set_led_usbport \"usb1\" \"USB 1\" \"pca963x:venom:blue:usb2\" \"usb1-port1\"\n\tucidef_set_led_usbport \"usb2\" \"USB 2\" \"pca963x:venom:blue:usb3_1\" \"usb2-port1\" \"usb3-port1\"\n\tucidef_set_led_usbport \"usb2_ss\" \"USB 2 SS\" \"pca963x:venom:blue:usb3_2\" \"usb3-port1\"\n\t;;\nesac\n\nboard_config_flush\n\nexit 0\n"
  },
  {
    "path": "target/linux/mvebu/cortexa9/base-files/etc/board.d/02_network",
    "content": "#\n# Copyright (C) 2014-2016 OpenWrt.org\n# Copyright (C) 2016 LEDE-Project.org\n#\n\n. /lib/functions.sh\n. /lib/functions/uci-defaults.sh\n. /lib/functions/system.sh\n\nmvebu_setup_interfaces()\n{\n\tlocal board=\"$1\"\n\n\tcase \"$board\" in\n\tctera,c200-v2)\n\t\tucidef_set_interface_lan \"eth0\" \"dhcp\"\n\t\t;;\n\tcznic,turris-omnia)\n\t\tucidef_set_interfaces_lan_wan \"lan0 lan1 lan2 lan3 lan4\" \"eth2\"\n\t\t;;\n\tiptime,nas1dual)\n\t\tucidef_set_interface_lan \"eth0 eth1\" \"dhcp\"\n\t\t;;\n\tlinksys,wrt1200ac|\\\n\tlinksys,wrt1900ac-v1|\\\n\tlinksys,wrt1900ac-v2|\\\n\tlinksys,wrt1900acs|\\\n\tlinksys,wrt3200acm|\\\n\tlinksys,wrt32x)\n\t\tucidef_set_interfaces_lan_wan \"lan1 lan2 lan3 lan4\" \"wan\"\n\t\t;;\n\tmarvell,a385-db-ap)\n\t\tucidef_set_interfaces_lan_wan \"eth0 eth1\" \"eth2\"\n\t\t;;\n\tmarvell,axp-gp)\n\t\tucidef_set_interface_lan \"eth0 eth1 eth2 eth3\"\n\t\t;;\n\tsolidrun,clearfog-base-a1)\n\t\t# eth0 is standalone ethernet\n\t\t# eth1 is standalone ethernet\n\t\t# eth2 is SFP\n\t\tucidef_set_interfaces_lan_wan \"eth1\" \"eth0 eth2\"\n\t\t;;\n\tsolidrun,clearfog-pro-a1)\n\t\t# eth0 is standalone ethernet\n\t\t# eth1 is switch\n\t\t# eth2 is SFP\n\t\tucidef_set_interfaces_lan_wan \"lan1 lan2 lan3 lan4 lan5 lan6\" \"eth0 eth2\"\n\t\t;;\n\t*)\n\t\tucidef_set_interface_lan \"eth0\"\n\t\t;;\n\tesac\n}\n\nmvebu_setup_macs()\n{\n\tlocal board=\"$1\"\n\tlocal lan_mac=\"\"\n\tlocal wan_mac=\"\"\n\tlocal label_mac=\"\"\n\n\tcase \"$board\" in\n\tbuffalo,ls421de)\n\t\tlan_mac=$(mtd_get_mac_ascii u-boot-env eth1addr)\n\t\t;;\n\tctera,c200-v2)\n\t\tlabel_mac=$(mtd_get_mac_ascii dev_params mac)\n\t\tlan_mac=$label_mac\n\t\t;;\n\tlinksys,wrt1200ac|\\\n\tlinksys,wrt1900ac-v2|\\\n\tlinksys,wrt1900acs|\\\n\tlinksys,wrt3200acm|\\\n\tlinksys,wrt32x)\n\t\tlabel_mac=$(mtd_get_mac_ascii devinfo hw_mac_addr)\n\t\twan_mac=$(macaddr_setbit_la $label_mac)\n\t\t;;\n\tlinksys,wrt1900ac-v1)\n\t\tlabel_mac=$(mtd_get_mac_ascii devinfo hw_mac_addr)\n\t\tlan_mac=$label_mac\n\t\twan_mac=$label_mac\n\t\t;;\n\tesac\n\n\t[ -n \"$lan_mac\" ] && ucidef_set_interface_macaddr \"lan\" $lan_mac\n\t[ -n \"$wan_mac\" ] && ucidef_set_interface_macaddr \"wan\" $wan_mac\n\t[ -n \"$label_mac\" ] && ucidef_set_label_macaddr $label_mac\n}\n\nboard_config_update\nboard=$(board_name)\nmvebu_setup_interfaces $board\nmvebu_setup_macs $board\nboard_config_flush\n\nexit 0\n"
  },
  {
    "path": "target/linux/mvebu/cortexa9/base-files/etc/board.d/05_compat-version",
    "content": "#\n# Copyright (C) 2020 OpenWrt.org\n#\n\n. /lib/functions.sh\n. /lib/functions/uci-defaults.sh\n\nboard_config_update\n\ncase \"$(board_name)\" in\n\tlinksys,wrt1200ac|\\\n\tlinksys,wrt1900ac-v1|\\\n\tlinksys,wrt1900ac-v2|\\\n\tlinksys,wrt1900acs|\\\n\tlinksys,wrt3200acm|\\\n\tlinksys,wrt32x|\\\n\tsolidrun,clearfog-base-a1|\\\n\tsolidrun,clearfog-pro-a1)\n\t\tucidef_set_compat_version \"1.1\"\n\t\t;;\nesac\n\nboard_config_flush\n\nexit 0\n"
  },
  {
    "path": "target/linux/mvebu/cortexa9/base-files/etc/hotplug.d/ieee80211/00-wifi-config-migrate",
    "content": "#!/bin/sh\n\n# The pcie-controller device was renamed to pcie in Linux kernel 4.14\n# commit 28fbb9c539e2 (\"ARM: dts: marvell: fix PCI bus dtc warnings\").\n# This script migrates the path in the UCI configuration from the old\n# name to the new name and also back, when am upgrade or downgrade is\n# done. It checks if the name exists before changing the configuration.\n# This has to be done before the 10-wifi-detect script from mac80211 is\n# executed because this would add the devices again under the new path\n# name.\n\n. /lib/functions.sh\n\nPATH_CHANGED=0\n\nrename_wifi_path() {\n\tlocal path_old=$(uci get wireless.${1}.path)\n\tlocal path_new=$(echo ${path_old} | sed \"${2}\")\n\n\tif [ -e \"/sys/devices/platform/${path_new}\" ] && [ ${path_old} != ${path_new} ]\n\tthen \n\t\tuci set wireless.${1}.path=${path_new}\n\t\tPATH_CHANGED=1\n\tfi\n}\n\nrename_wifi_path_list() {\n\t# migration from kernel 4.9 to 4.14\n\trename_wifi_path $1 \"s/soc:pcie-controller/soc:pcie/\"\n\t# migration from kernel 4.14 to 4.9\n\trename_wifi_path $1 \"s/soc:pcie/soc:pcie-controller/\"\n}\n\n[ \"${ACTION}\" = \"add\" ] && {\n\t[ ! -e /etc/config/wireless ] && return\n\n\tconfig_load wireless\n\tconfig_foreach rename_wifi_path_list wifi-device\n\n\t[ \"$PATH_CHANGED\" = \"1\" ] && uci commit wireless\n}\n"
  },
  {
    "path": "target/linux/mvebu/cortexa9/base-files/etc/init.d/bootcount",
    "content": "#!/bin/sh /etc/rc.common\n\nSTART=99\n\nboot() {\n\tcase $(board_name) in\n\tlinksys,wrt1200ac|\\\n\tlinksys,wrt1900ac-v1|\\\n\tlinksys,wrt1900ac-v2|\\\n\tlinksys,wrt1900acs|\\\n\tlinksys,wrt3200acm|\\\n\tlinksys,wrt32x)\n\t\tmtd resetbc s_env || true\n\t\t;;\n\tesac\n}\n"
  },
  {
    "path": "target/linux/mvebu/cortexa9/base-files/etc/uci-defaults/03_wireless",
    "content": "#\n# Copyright (C) 2015 OpenWrt.org\n#\n\n[ ! -e /etc/config/wireless ] && exit 0\n\n. /lib/functions.sh\n. /lib/functions/system.sh\n\nboard=$(board_name)\n\ncase \"$board\" in\nlinksys,wrt1200ac|\\\nlinksys,wrt1900ac-v1|\\\nlinksys,wrt1900ac-v2|\\\nlinksys,wrt1900acs|\\\nlinksys,wrt3200acm|\\\nlinksys,wrt32x)\n\tSKU=$(strings /dev/mtd3|sed -ne 's/^cert_region=//p')\n\tWIFIMAC2G=$(macaddr_add $(mtd_get_mac_ascii devinfo hw_mac_addr) 1)\n\tWIFIMAC5G=$(macaddr_add $WIFIMAC2G 1)\n\tcase \"$SKU\" in\n\t\tAP)\n\t\t\tREGD=CN\n\t\t;;\n\t\tAU)\n\t\t\tREGD=AU\n\t\t;;\n\t\tCA)\n\t\t\tREGD=CA\n\t\t;;\n\t\tEU)\n\t\t\tREGD=FR\n\t\t;;\n\t\tUS)\n\t\t\tREGD=US\n\t\t;;\n\tesac\n\n\tcase \"$board\" in\n\t\tlinksys,wrt1900ac-v1)\n\t\t\tWIFIMAC0=$WIFIMAC2G\n\t\t\tWIFIMAC1=$WIFIMAC5G\n\t\t;;\n\t\t*)\n\t\t\tWIFIMAC0=$WIFIMAC5G\n\t\t\tWIFIMAC1=$WIFIMAC2G\n\t\t;;\n\tesac\n\n\tuci get wireless.radio0.country || uci set wireless.radio0.country=$REGD\n\tuci get wireless.@wifi-iface[0].macaddr || uci set wireless.@wifi-iface[0].macaddr=$WIFIMAC0\n\tuci get wireless.radio1.country || uci set wireless.radio1.country=$REGD\n\tuci get wireless.@wifi-iface[1].macaddr || uci set wireless.@wifi-iface[1].macaddr=$WIFIMAC1\n\t;;\nesac\n\nuci commit wireless\n\nexit 0\n"
  },
  {
    "path": "target/linux/mvebu/cortexa9/base-files/etc/uci-defaults/04_mambafan",
    "content": "#\n# Copyright (C) 2017 LEDE-Project.org\n#\n\n. /lib/functions.sh\n\nboard=$(board_name)\n\ncase \"$board\" in\nlinksys,wrt1900ac-v1)\n\t# Set fan script execution in crontab\n\tgrep -s -q fan_ctrl.sh /etc/crontabs/root && exit 0\n\n\techo \"# mamba fan script runs every 5 minutes\" >> /etc/crontabs/root\n\techo \"*/5 * * * * /sbin/fan_ctrl.sh\" >> /etc/crontabs/root\n\n\t# Execute one time after initial flash (instead of waiting 5 min for cron)\n\t/sbin/fan_ctrl.sh\n\t;;\nesac\n\nexit 0\n"
  },
  {
    "path": "target/linux/mvebu/cortexa9/base-files/etc/uci-defaults/05_fix-compat-version",
    "content": ". /lib/functions.sh\n\ncase \"$(board_name)\" in\n\tlinksys,wrt1900ac-v1|\\\n        linksys,wrt32x)\n\t\tuci set system.@system[0].compat_version=\"2.0\"\n\t\tuci commit system\n\t\t;;\nesac\n\nexit 0\n"
  },
  {
    "path": "target/linux/mvebu/cortexa9/base-files/etc/uci-defaults/35_turris-omnia_uboot-env",
    "content": "# This must be sourced after 30_uboot-envtools\n\n. /lib/functions.sh\n\nboard=$(board_name)\n\ncase \"$board\" in\ncznic,turris-omnia)\n\t# Do nothing if this is not the old U-Boot\n\tgrep -q 'U-Boot 2015.10-rc2' /dev/mtd0 || exit 0\n\t# Do nothing if we already have distro_bootcmd\n\tfw_printenv distro_bootcmd >/dev/null 2>/dev/null && exit 0\n\t# Set the complete environment, since U-Boot does not merge the default environment from its own image!\n\tfw_setenv -s - <<-\"EOF\"\n\t\tbaudrate 115200\n\t\tbootdelay 3\n\t\tethact neta2\n\t\tfdt_high 0x10000000\n\t\tinitrd_high 0x10000000\n\t\tbootargs earlyprintk console=ttyS0,115200 rootfstype=btrfs rootdelay=2 root=b301 rootflags=subvol=@,commit=5 rw\n\t\tbootcmd i2c dev 1; i2c read 0x2a 0x9 1 0x00FFFFF0; setexpr.b rescue *0x00FFFFF0; if test $rescue -ge 1; then echo BOOT RESCUE; run rescueboot; else echo BOOT eMMC FS; run mmcboot; setenv bootargs; run distro_bootcmd; fi\n\t\trescueboot i2c mw 0x2a.1 0x3 0x1c 1; i2c mw 0x2a.1 0x4 0x1c 1; mw.l 0x01000000 0x00ff000c; i2c write 0x01000000 0x2a.1 0x5 4 -s; setenv bootargs \"$bootargs omniarescue=$rescue\"; sf probe; sf read 0x1000000 0x100000 0x700000; bootz 0x1000000\n\t\tmmcboot btrload mmc 0 ${kernel_addr_r} boot/zImage @ && btrload mmc 0 ${fdt_addr_r} boot/dtb @ && setenv bootargs ${bootargs} cfg80211.freg=${regdomain} && bootz ${kernel_addr_r} - ${fdt_addr_r}\n\t\tkernel_addr_r 0x1000000\n\t\tscriptaddr 0x1800000\n\t\tfdt_addr_r 0x2000000\n\t\tboot_targets mmc0 scsi0\n\t\tboot_prefixes / /boot/\n\t\tboot_scripts boot.scr\n\t\tdistro_bootcmd scsi_need_init=true; for target in ${boot_targets}; do run bootcmd_${target}; done\n\t\tbootcmd_mmc0 devnum=0; run mmc_boot\n\t\tmmc_boot if mmc dev ${devnum}; then devtype=mmc; run scan_dev_for_boot_part; fi\n\t\tbootcmd_scsi0 devnum=0; run scsi_boot\n\t\tscsi_boot run scsi_init; if scsi dev ${devnum}; then devtype=scsi; run scan_dev_for_boot_part; fi\n\t\tscsi_init if ${scsi_need_init}; then scsi_need_init=false; scsi scan; fi\n\t\tscan_dev_for_boot_part for distro_bootpart in 1; do if fstype ${devtype} ${devnum}:${distro_bootpart} bootfstype; then run scan_dev_for_boot; fi; done\n\t\tscan_dev_for_boot echo Scanning ${devtype} ${devnum}:${distro_bootpart}...; for prefix in ${boot_prefixes}; do run scan_dev_for_scripts; done\n\t\tscan_dev_for_scripts for script in ${boot_scripts}; do if test -e ${devtype} ${devnum}:${distro_bootpart} ${prefix}${script}; then echo Found U-Boot script ${prefix}${script}; run boot_a_script; echo SCRIPT FAILED: continuing...; fi; done\n\t\tboot_a_script load ${devtype} ${devnum}:${distro_bootpart} ${scriptaddr} ${prefix}${script}; source ${scriptaddr}\n\tEOF\n\t;;\nesac\n\nexit 0\n"
  },
  {
    "path": "target/linux/mvebu/cortexa9/base-files/lib/preinit/81_linksys_syscfg",
    "content": "#\n# Copyright (C) 2014-2016 OpenWrt.org\n# Copyright (C) 2016 LEDE-Project.org\n#\n\npreinit_mount_syscfg() {\n\t. /lib/functions.sh\n\t. /lib/upgrade/common.sh\n\n\tcase $(board_name) in\n\tlinksys,wrt1200ac|\\\n\tlinksys,wrt1900ac-v1|\\\n\tlinksys,wrt1900ac-v2|\\\n\tlinksys,wrt1900acs|\\\n\tlinksys,wrt3200acm|\\\n\tlinksys,wrt32x)\n\t\tneeds_recovery=0\n\t\tsyscfg_part=$(grep syscfg /proc/mtd |cut -c4)\n\t\tubiattach -m $syscfg_part || needs_recovery=1\n\t\tif [ $needs_recovery -eq 1 ]\n\t\tthen\n\t\t\techo \"ubifs syscfg partition is damaged, reformatting\"\n\t\t\tubidetach -m $syscfg_part\n\t\t\tubiformat -y -O 2048 -q /dev/mtd$syscfg_part\n\t\t\tubiattach -m $syscfg_part\n\t\t\tubimkvol /dev/ubi1 -n 0 -N syscfg -t dynamic --maxavsize\n\t\tfi\n\t\tmkdir /tmp/syscfg\n\t\tmount -t ubifs ubi1:syscfg /tmp/syscfg\n\t\t[ -f \"/tmp/syscfg/$BACKUP_FILE\" ] && {\n\t\techo \"- config restore -\"\n\t\tcd /\n\t\tmv \"/tmp/syscfg/$BACKUP_FILE\" /tmp\n\t\ttar xzf \"/tmp/$BACKUP_FILE\"\n\t\trm -f \"/tmp/$BACKUP_FILE\"\n\t\tsync\n\t\t}\n\t\t;;\n\tesac\n}\n\nboot_hook_add preinit_main preinit_mount_syscfg\n"
  },
  {
    "path": "target/linux/mvebu/cortexa9/base-files/lib/upgrade/linksys.sh",
    "content": "#\n# Copyright (C) 2014-2015 OpenWrt.org\n#\n\nlinksys_get_target_firmware() {\n\n\tlocal cur_boot_part mtd_ubi0\n\n\tcur_boot_part=$(/usr/sbin/fw_printenv -n boot_part)\n\tif [ -z \"${cur_boot_part}\" ] ; then\n\t\tmtd_ubi0=$(cat /sys/devices/virtual/ubi/ubi0/mtd_num)\n\t\tcase $(grep -E ^mtd${mtd_ubi0}: /proc/mtd | cut -d '\"' -f 2) in\n\t\tkernel1|rootfs1)\n\t\t\tcur_boot_part=1\n\t\t\t;;\n\t\tkernel2|rootfs2)\n\t\t\tcur_boot_part=2\n\t\t\t;;\n\t\tesac\n\t\t>&2 printf \"Current boot_part='%s' selected from ubi0/mtd_num='%s'\" \\\n\t\t\t\"${cur_boot_part}\" \"${mtd_ubi0}\"\n\tfi\n\n\tcase $cur_boot_part in\n\t1)\n\t\tfw_setenv -s - <<-EOF\n\t\t\tboot_part 2\n\t\t\tbootcmd \"run altnandboot\"\n\t\tEOF\n\t\tprintf \"kernel2\"\n\t\treturn\n\t\t;;\n\t2)\n\t\tfw_setenv -s - <<-EOF\n\t\t\tboot_part 1\n\t\t\tbootcmd \"run nandboot\"\n\t\tEOF\n\t\tprintf \"kernel1\"\n\t\treturn\n\t\t;;\n\t*)\n\t\treturn\n\t\t;;\n\tesac\n}\n\nplatform_do_upgrade_linksys() {\n\tlocal magic_long=\"$(get_magic_long \"$1\")\"\n\n\tmkdir -p /var/lock\n\tlocal part_label=\"$(linksys_get_target_firmware)\"\n\ttouch /var/lock/fw_printenv.lock\n\n\tif [ ! -n \"$part_label\" ]\n\tthen\n\t\tv \"cannot find target partition\"\n\t\texit 1\n\tfi\n\n\tlocal target_mtd=$(find_mtd_part $part_label)\n\n\t[ \"$magic_long\" = \"73797375\" ] && {\n\t\tCI_KERNPART=\"$part_label\"\n\t\tif [ \"$part_label\" = \"kernel1\" ]\n\t\tthen\n\t\t\tCI_UBIPART=\"rootfs1\"\n\t\telse\n\t\t\tCI_UBIPART=\"rootfs2\"\n\t\tfi\n\n\t\tnand_upgrade_tar \"$1\"\n\t}\n\t[ \"$magic_long\" = \"27051956\" -o \"$magic_long\" = \"0000a0e1\" ] && {\n\t\tget_image \"$1\" | mtd write - $part_label\n\t}\n}\n\nplatform_copy_config_linksys() {\n\tcp -f \"$UPGRADE_BACKUP\" \"/tmp/syscfg/$BACKUP_FILE\"\n\tsync\n}\n"
  },
  {
    "path": "target/linux/mvebu/cortexa9/base-files/lib/upgrade/platform.sh",
    "content": "#\n# Copyright (C) 2014-2016 OpenWrt.org\n# Copyright (C) 2016 LEDE-Project.org\n#\n\nRAMFS_COPY_BIN='fw_printenv fw_setenv strings'\nRAMFS_COPY_DATA='/etc/fw_env.config /var/lock/fw_printenv.lock'\n\nPART_NAME=firmware\nREQUIRE_IMAGE_METADATA=1\n\nplatform_check_image() {\n\tcase \"$(board_name)\" in\n\tcznic,turris-omnia|\\\n\tkobol,helios4|\\\n\tsolidrun,clearfog-base-a1|\\\n\tsolidrun,clearfog-pro-a1)\n\t\tlegacy_sdcard_check_image \"$1\"\n\t\t;;\n\t*)\n\t\treturn 0\n\t\t;;\n\tesac\n}\n\nplatform_do_upgrade() {\n\tcase \"$(board_name)\" in\n\tbuffalo,ls421de)\n\t\tnand_do_upgrade \"$1\"\n\t\t;;\n\tctera,c200-v2)\n\tpart=$(find_mtd_part \"active_bank\")\n\n\tif [ -n \"$part\" ]; then\n\t\tCI_KERNPART=\"$(strings $part | grep bank)\"\n\t\tnand_do_upgrade \"$1\"\n\telse\n\t\techo \"active_bank partition missed!\"\n\t\treturn 1\n\tfi\n\t;;\n\tcznic,turris-omnia|\\\n\tkobol,helios4|\\\n\tsolidrun,clearfog-base-a1|\\\n\tsolidrun,clearfog-pro-a1)\n\t\tlegacy_sdcard_do_upgrade \"$1\"\n\t\t;;\n\tlinksys,wrt1200ac|\\\n\tlinksys,wrt1900ac-v1|\\\n\tlinksys,wrt1900ac-v2|\\\n\tlinksys,wrt1900acs|\\\n\tlinksys,wrt3200acm|\\\n\tlinksys,wrt32x)\n\t\tplatform_do_upgrade_linksys \"$1\"\n\t\t;;\n\t*)\n\t\tdefault_do_upgrade \"$1\"\n\t\t;;\n\tesac\n}\nplatform_copy_config() {\n\tcase \"$(board_name)\" in\n\tcznic,turris-omnia|\\\n\tkobol,helios4|\\\n\tsolidrun,clearfog-base-a1|\\\n\tsolidrun,clearfog-pro-a1)\n\t\tlegacy_sdcard_copy_config\n\t\t;;\n\tlinksys,wrt1200ac|\\\n\tlinksys,wrt1900ac-v1|\\\n\tlinksys,wrt1900ac-v2|\\\n\tlinksys,wrt1900acs|\\\n\tlinksys,wrt3200acm|\\\n\tlinksys,wrt32x)\n\t\tplatform_copy_config_linksys\n\t\t;;\n\tesac\n}\n"
  },
  {
    "path": "target/linux/mvebu/cortexa9/base-files/sbin/fan_ctrl.sh",
    "content": "#!/bin/sh\n\nCPU_TEMP=$(cut -c1-2 /sys/class/hwmon/hwmon2/temp1_input)\nDDR_TEMP=$(cut -c1-2 /sys/class/hwmon/hwmon1/temp1_input)\nWIFI_TEMP=$(cut -c1-2 /sys/class/hwmon/hwmon1/temp2_input)\n\nCPU_LOW=85\nCPU_HIGH=95\nDDR_LOW=65\nDDR_HIGH=75\nWIFI_LOW=100\nWIFI_HIGH=115\n\nif [ -d /sys/devices/pwm_fan ];then\n\tFAN_CTRL=/sys/devices/pwm_fan/hwmon/hwmon0/pwm1\nelif [ -d /sys/devices/platform/pwm_fan ];then\n\tFAN_CTRL=/sys/devices/platform/pwm_fan/hwmon/hwmon0/pwm1\nelse\n\texit 0\nfi\n\nif [ \"$CPU_TEMP\" -ge \"$CPU_HIGH\" -o \"$DDR_TEMP\" -ge \"$DDR_HIGH\" -o \"$WIFI_TEMP\" -ge \"$WIFI_HIGH\" ];then\n\techo \"255\" > $FAN_CTRL\nelif [ \"$CPU_TEMP\" -ge \"$CPU_LOW\" -o \"$DDR_TEMP\" -ge \"$DDR_LOW\" -o \"$WIFI_TEMP\" -ge \"$WIFI_LOW\" ];then\n\techo \"100\" > $FAN_CTRL\nelse\n\techo \"0\" > $FAN_CTRL\nfi\n"
  },
  {
    "path": "target/linux/mvebu/cortexa9/config-5.10",
    "content": "CONFIG_PHY_MVEBU_A38X_COMPHY=y\nCONFIG_RTC_DRV_MV=y\n"
  },
  {
    "path": "target/linux/mvebu/cortexa9/target.mk",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2017 Hauke Mehrtens\n\ninclude $(TOPDIR)/rules.mk\n\nARCH:=arm\nBOARDNAME:=Marvell Armada 37x/38x/XP\nCPU_TYPE:=cortex-a9\nCPU_SUBTYPE:=vfpv3-d16\nKERNELNAME:=zImage dtbs\n"
  },
  {
    "path": "target/linux/mvebu/files/arch/arm/boot/dts/armada-370-buffalo-ls421de.dts",
    "content": "// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)\n/*\n * Device Tree file for Buffalo LinkStation LS421DE\n *\n * Copyright (C) 2020 Daniel González Cabanelas <dgcbueu@gmail.com>\n */\n\n/dts-v1/;\n\n#include \"armada-370.dtsi\"\n#include \"mvebu-linkstation-fan.dtsi\"\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/thermal/thermal.h>\n\n/ {\n\tmodel = \"Buffalo LinkStation LS421DE\";\n\tcompatible = \"buffalo,ls421de\", \"marvell,armada370\", \"marvell,armada-370-xp\";\n\n\taliases {\n\t\tled-boot = &led_boot;\n\t\tled-failsafe = &led_failsafe;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_upgrade;\n\t};\n\n\tchosen {\n\t\tbootargs = \"earlycon\";\n\t\tstdout-path = \"serial0:115200n8\";\n\t\tappend-rootblock = \"nullparameter=\"; /* override the bootloader args */\n\t};\n\n\tmemory {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x00000000 0x20000000>; /* 512 MB */\n\t};\n\n\tsoc {\n\t\tranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000\n\t\t\t  MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000\n\t\t\t  MBUS_ID(0x09, 0x01) 0 0xf1100000 0x10000>;\n\t};\n\n\tsystem_fan: gpio_fan {\n\t\tgpios = <&gpio0 13 GPIO_ACTIVE_HIGH\n\t\t\t &gpio0 14 GPIO_ACTIVE_HIGH>;\n\t\talarm-gpios = <&gpio0 10 GPIO_ACTIVE_HIGH>;\n\n\t\t#cooling-cells = <2>;\n\t};\n\n\tthermal-zones {\n\t\thdd-thermal {\n\t\t\tpolling-delay = <20000>;\n\t\t\tpolling-delay-passive = <2000>;\n\n\t\t\tthermal-sensors = <&hdd0_temp>; /* only one drivetemp sensor is supported */\n\n\t\t\ttrips {\n\t\t\t\thdd_alert1: trip1 {\n\t\t\t\t\ttemperature = <36000>;\n\t\t\t\t\thysteresis = <2000>;\n\t\t\t\t\ttype = \"active\";\n\t\t\t\t};\n\t\t\t\thdd_alert2: trip2 {\n\t\t\t\t\ttemperature = <44000>;\n\t\t\t\t\thysteresis = <2000>;\n\t\t\t\t\ttype = \"active\";\n\t\t\t\t};\n\t\t\t\thdd_alert3: trip3 {\n\t\t\t\t\ttemperature = <52000>;\n\t\t\t\t\thysteresis = <2000>;\n\t\t\t\t\ttype = \"passive\";\n\t\t\t\t};\n\t\t\t\thdd_crit: trip4 {\n\t\t\t\t\ttemperature = <60000>;\n\t\t\t\t\thysteresis = <2000>;\n\t\t\t\t\ttype = \"critical\";\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tcooling-maps {\n\t\t\t\tmap1 {\n\t\t\t\t\ttrip = <&hdd_alert1>;\n\t\t\t\t\tcooling-device = <&system_fan THERMAL_NO_LIMIT 1>;\n\t\t\t\t};\n\t\t\t\tmap2 {\n\t\t\t\t\ttrip = <&hdd_alert2>;\n\t\t\t\t\tcooling-device = <&system_fan 2 2>;\n\t\t\t\t};\n\t\t\t\tmap3 {\n\t\t\t\t\ttrip = <&hdd_alert3>;\n\t\t\t\t\tcooling-device = <&system_fan 3 THERMAL_NO_LIMIT>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\tethphy-thermal {\n\t\t\tpolling-delay = <20000>;\n\t\t\tpolling-delay-passive = <2000>;\n\n\t\t\tthermal-sensors = <&ethphy0>;\n\n\t\t\ttrips {\n\t\t\t\tethphy_alert1: trip1 {\n\t\t\t\t\ttemperature = <65000>;\n\t\t\t\t\thysteresis = <4000>;\n\t\t\t\t\ttype = \"passive\";\n\t\t\t\t};\n\n\t\t\t\tethphy_crit: trip2 {\n\t\t\t\t\ttemperature = <100000>;\n\t\t\t\t\thysteresis = <2000>;\n\t\t\t\t\ttype = \"critical\";\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tcooling-maps {\n\t\t\t\tmap1 {\n\t\t\t\t\ttrip = <&ethphy_alert1>;\n\t\t\t\t\tcooling-device = <&system_fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;\n\t\t\t\t};\n\n\t\t\t};\n\t\t};\n\t};\n\n\tgpio_keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tpinctrl-0 = <&pmx_buttons>;\n\t\tpinctrl-names = \"default\";\n\n\t\tpower {\n\t\t\tlabel = \"Power Switch\";\n\t\t\tlinux,code = <KEY_POWER>;\n\t\t\tlinux,input-type = <EV_SW>;\n\t\t\tgpios = <&gpio0 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tfunction {\n\t\t\tlabel = \"Function Button\";\n\t\t\tlinux,code = <KEY_CONFIG>;\n\t\t\tgpios = <&gpio0 16 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tgpio_leds {\n\t\tcompatible = \"gpio-leds\";\n\t\tpinctrl-names = \"default\";\n\t\tpinctrl-0 = <&pmx_leds1 &pmx_leds2>;\n\n\t\tsystem_red {\n\t\t\tlabel = \"ls421de:red:system\";\n\t\t\tgpios = <&gpio0 7 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tled_power: power_white {\n\t\t\tlabel = \"ls421de:white:power\";\n\t\t\tgpios = <&gpio1 22 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\tled_failsafe: power_red {\n\t\t\tlabel = \"ls421de:red:power\";\n\t\t\tgpios = <&gpio1 23 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tled_upgrade: power_orange {\n\t\t\tlabel = \"ls421de:orange:power\";\n\t\t\tgpios = <&gpio1 25 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tled_boot: system_white {\n\t\t\tlabel = \"ls421de:white:system\";\n\t\t\tgpios = <&gpio1 27 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\thdd1_red {\n\t\t\tlabel = \"ls421de:red:hdd1\";\n\t\t\tgpios = <&gpio1 29 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"ata1\";\n\t\t};\n\n\t\thdd2_red {\n\t\t\tlabel = \"ls421de:red:hdd2\";\n\t\t\tgpios = <&gpio1 30 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"ata2\";\n\t\t};\n\t};\n\n\tregulators {\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tpinctrl-0 = <&pmx_power_usb &pmx_power_hdd1 &pmx_power_hdd2>;\n\t\tpinctrl-names = \"default\";\n\n\t\tusb_power: regulator@0 {\n\t\t\tcompatible = \"regulator-fixed\";\n\t\t\treg = <0>;\n\t\t\tregulator-name = \"USB\";\n\t\t\tregulator-min-microvolt = <5000000>;\n\t\t\tregulator-max-microvolt = <5000000>;\n\t\t\tenable-active-high;\n\t\t\tregulator-always-on;\n\t\t\tregulator-boot-on;\n\t\t\tgpio = <&gpio0 5 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tsata1_power: regulator@1 {\n\t\t\tcompatible = \"regulator-fixed\";\n\t\t\treg = <1>;\n\t\t\tregulator-name = \"HDD1\";\n\t\t\tregulator-min-microvolt = <12000000>;\n\t\t\tregulator-max-microvolt = <12000000>;\n\t\t\tstartup-delay-us = <2000000>;\n\t\t\tenable-active-high;\n\t\t\tregulator-always-on;\n\t\t\tregulator-boot-on;\n\t\t\tgpio = <&gpio0 8 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tsata2_power: regulator@2 {\n\t\t\tcompatible = \"regulator-fixed\";\n\t\t\treg = <2>;\n\t\t\tregulator-name = \"HDD2\";\n\t\t\tregulator-min-microvolt = <12000000>;\n\t\t\tregulator-max-microvolt = <12000000>;\n\t\t\tstartup-delay-us = <4000000>;\n\t\t\tenable-active-high;\n\t\t\tregulator-always-on;\n\t\t\tregulator-boot-on;\n\t\t\tgpio = <&gpio0 9 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&coherencyfab {\n\tbroken-idle;\n};\n\n&eth1 {\n\tpinctrl-0 = <&ge1_rgmii_pins>;\n\tpinctrl-names = \"default\";\n\tstatus = \"okay\";\n\tphy-handle = <&ethphy0>;\n\tphy-connection-type = \"rgmii-id\";\n};\n\n&i2c0 {\n\tpinctrl-0 = <&i2c0_pins>;\n\tpinctrl-names = \"default\";\n\tclock-frequency = <100000>;\n\tstatus = \"okay\";\n\n\trs5c372a: rs5c372a@32 {\n\t\tcompatible = \"ricoh,rs5c372a\";\n\t\treg = <0x32>;\n\t\twakeup-source;\n\t};\n};\n\n&mdio {\n\tpinctrl-0 = <&mdio_pins>;\n\tpinctrl-names = \"default\";\n\n\tethphy0: ethernet-phy@0 { /* Marvell 88E1518 */\n\t\treg = <0>;\n\t\tmarvell,reg-init = <0x2 0x10 0xffff 0x0006>, /* disable CLK125 */\n\t\t\t\t   <0x3 0x10 0x0000 0x1991>, /* LED function */\n\t\t\t\t   <0x3 0x11 0x0000 0x4401>, /* LED polarity */\n\t\t\t\t   <0x3 0x12 0x0000 0x4905>; /* LED timer */\n\t\t#thermal-sensor-cells = <0>;\n\t};\n};\n\n&pciec {\n\tstatus = \"okay\";\n\tpinctrl-0 = <&pmx_pcie>;\n\tpinctrl-names = \"default\";\n\n\t/* Connected to uPD720202 USB 3.0 Host */\n\tpcie@1,0 {\n\t\tstatus = \"okay\";\n\t};\n};\n\n&pmsu {\n\tpinctrl-0 = <&pmx_power_cpu>;\n\tpinctrl-names = \"default\";\n};\n\n&rtc {\n\tstatus = \"disabled\";\n};\n\n&sata {\n\tnr-ports = <2>;\n\tstatus = \"okay\";\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\n\thdd0_temp: sata-port@0 {\n\t\treg = <0>;\n\t\t#thermal-sensor-cells = <0>;\n\t};\n\n\thdd1_temp: sata-port@1 {\n\t\treg = <1>;\n\t\t#thermal-sensor-cells = <0>;\n\t};\n};\n\n&sdio {\n\tpinctrl-0 = <&sdio_pins2>;\n\tpinctrl-names = \"default\";\n\tstatus = \"okay\";\n\t/* No CD or WP GPIOs */\n\tbroken-cd;\n};\n\n&uart0 {\n\tstatus = \"okay\";\n};\n\n&usb0 {\n\tstatus = \"okay\";\n};\n\n&nand_controller {\n\tstatus = \"okay\";\n\n\tnand@0 {\n\t\treg = <0>;\n\t\tlabel = \"pxa3xx_nand-0\";\n\t\tnand-rb = <0>;\n\t\tmarvell,nand-keep-config;\n\t\tnand-on-flash-bbt;\n\t\tnand-ecc-strength = <4>;\n\t\tnand-ecc-step-size = <512>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"kernel\";\n\t\t\t\treg = <0x00000000 0x02000000>;  /* 32 MiB */\n\t\t\t};\n\n\t\t\tpartition@2000000 {\n\t\t\t\tlabel = \"ubi\";\n\t\t\t\treg = <0x02000000 0x1e000000>;  /* 480 MiB */\n\t\t\t};\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\tpinctrl-0 = <&spi0_pins2>;\n\tpinctrl-names = \"default\";\n\n\tspi-flash@0 {\n\t\tcompatible = \"mxicy,mx25l8005\", \"jedec,spi-nor\";\n\t\treg = <0>; /* Chip select 0 */\n\t\tspi-max-frequency = <50000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\treg = <0x00000 0xf0000>; /* 960 KiB*/\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@f0000 {\n\t\t\t\treg = <0xf0000 0x10000>; /* 64 KiB */\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pinctrl {\n\tpmx_power_cpu: pmx-power-cpu {\n\t\tmarvell,pins = \"mpp4\";\n\t\tmarvell,function = \"vdd\";\n\t};\n\n\tpmx_power_usb: pmx-power-usb {\n\t\tmarvell,pins = \"mpp5\";\n\t\tmarvell,function = \"gpo\";\n\t};\n\n\tpmx_power_hdd1: pmx-power-hdd1 {\n\t\tmarvell,pins = \"mpp8\";\n\t\tmarvell,function = \"gpio\";\n\t};\n\n\tpmx_power_hdd2: pmx-power-hdd2 {\n\t\tmarvell,pins = \"mpp9\";\n\t\tmarvell,function = \"gpo\";\n\t};\n\n\tpmx_fan_lock: pmx-fan-lock {\n\t\tmarvell,pins = \"mpp10\";\n\t\tmarvell,function = \"gpio\";\n\t};\n\n\tpmx_hdd_present: pmx-hdd-present {\n\t\tmarvell,pins = \"mpp11\", \"mpp12\";\n\t\tmarvell,function = \"gpio\";\n\t};\n\n\tpmx_fan_high: pmx-fan-high {\n\t\tmarvell,pins = \"mpp13\";\n\t\tmarvell,function = \"gpio\";\n\t};\n\n\tpmx_fan_low: pmx-fan-low {\n\t\tmarvell,pins = \"mpp14\";\n\t\tmarvell,function = \"gpio\";\n\t};\n\n\tpmx_buttons: pmx-buttons {\n\t\tmarvell,pins = \"mpp15\", \"mpp16\";\n\t\tmarvell,function = \"gpio\";\n\t};\n\n\tpmx_leds1: pmx-leds {\n\t\tmarvell,pins = \"mpp7\", \"mpp54\", \"mpp59\", \"mpp61\";\n\t\tmarvell,function = \"gpo\";\n\t};\n\n\tpmx_leds2: pmx-leds {\n\t\tmarvell,pins = \"mpp55\", \"mpp57\", \"mpp62\";\n\t\tmarvell,function = \"gpio\";\n\t};\n\n\tpmx_pcie: pmx-pcie {\n\t\tmarvell,pins = \"mpp56\", \"mpp60\";\n\t\tmarvell,function = \"pcie\";\n\t};\n};\n"
  },
  {
    "path": "target/linux/mvebu/files/arch/arm/boot/dts/armada-370-c200-v2.dts",
    "content": "// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)\n/*\n * Device Tree file for Ctera C200-V2\n *\n * Copyright (C) 2021 Pawel Dembicki <paweldembicki@gmail.com>\n */\n\n/dts-v1/;\n\n#include \"armada-370.dtsi\"\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/thermal/thermal.h>\n#include <dt-bindings/leds/common.h>\n\n/ {\n\tmodel = \"Ctera C200 V2\";\n\tcompatible = \"ctera,c200-v2\", \"marvell,armada370\", \"marvell,armada-370-xp\";\n\n\taliases {\n\t\tled-boot = &led_status_green;\n\t\tled-failsafe = &led_status_red;\n\t\tled-running = &led_status_green;\n\t\tled-upgrade = &led_status_red;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200\";\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\tmemory {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x00000000 0x40000000>; /* 1024 MB */\n\t};\n\n\tsoc {\n\t\tranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000\n\t\t\t  MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000\n\t\t\t  MBUS_ID(0x09, 0x01) 0 0xf1100000 0x10000>;\n\t};\n\n\tthermal-zones {\n\t\tethphy-thermal {\n\t\t\tpolling-delay = <20000>;\n\t\t\tpolling-delay-passive = <2000>;\n\n\t\t\tthermal-sensors = <&ethphy0>;\n\n\t\t\ttrips {\n\t\t\t\tethphy_alert1: trip1 {\n\t\t\t\t\ttemperature = <65000>;\n\t\t\t\t\thysteresis = <4000>;\n\t\t\t\t\ttype = \"passive\";\n\t\t\t\t};\n\n\t\t\t\tethphy_crit: trip2 {\n\t\t\t\t\ttemperature = <100000>;\n\t\t\t\t\thysteresis = <2000>;\n\t\t\t\t\ttype = \"critical\";\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\t\tpinctrl-0 = <&pmx_buttons>;\n\t\tpinctrl-names = \"default\";\n\n\t\tpower {\n\t\t\tlabel = \"Power Button\";\n\t\t\tlinux,code = <KEY_POWER>;\n\t\t\tgpios = <&gpio0 10 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"Reset Button\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio0 6 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tusb1 {\n\t\t\tlabel = \"USB1 Button\";\n\t\t\tlinux,code = <BTN_0>;\n\t\t\tgpios = <&gpio1 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tusb2 {\n\t\t\tlabel = \"USB2 Button\";\n\t\t\tlinux,code = <BTN_1>;\n\t\t\tgpios = <&gpio0 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tgpio-poweroff {\n\t\tcompatible = \"gpio-poweroff\";\n\t\tpinctrl-0 = <&pmx_poweroff>;\n\t\tpinctrl-names = \"default\";\n\t\tgpios = <&gpio0 7 GPIO_ACTIVE_HIGH>;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tpinctrl-0 = <&pmx_leds1 &pmx_leds2>;\n\t\tpinctrl-names = \"default\";\n\n\t\tled-0 {\n\t\t\tfunction = LED_FUNCTION_USB;\n\t\t\tfunction-enumerator = <2>;\n\t\t\tcolor = <LED_COLOR_ID_RED>;\n\t\t\tgpios = <&gpio0 12 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled-1 {\n\t\t\tfunction = LED_FUNCTION_USB;\n\t\t\tfunction-enumerator = <2>;\n\t\t\tcolor = <LED_COLOR_ID_GREEN>;\n\t\t\tgpios = <&gpio0 13 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t\ttrigger-sources = <&usb1_port 1>, <&usb2_port 1>;\n\t\t};\n\n\t\tled-2 {\n\t\t\tfunction = LED_FUNCTION_USB;\n\t\t\tfunction-enumerator = <1>;\n\t\t\tcolor = <LED_COLOR_ID_RED>;\n\t\t\tgpios = <&gpio0 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled-3 {\n\t\t\tfunction = LED_FUNCTION_USB;\n\t\t\tfunction-enumerator = <1>;\n\t\t\tcolor = <LED_COLOR_ID_GREEN>;\n\t\t\tgpios = <&gpio0 16 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t\ttrigger-sources = <&usb1_port 2>, <&usb2_port 2>;\n\t\t};\n\n\t\tled-4 {\n\t\t\tfunction = LED_FUNCTION_DISK;\n\t\t\tfunction-enumerator = <2>;\n\t\t\tcolor = <LED_COLOR_ID_GREEN>;\n\t\t\tgpios = <&gpio1 15 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"ata2\";\n\t\t};\n\n\t\tled-5 {\n\t\t\tfunction = LED_FUNCTION_DISK;\n\t\t\tfunction-enumerator = <1>;\n\t\t\tcolor = <LED_COLOR_ID_RED>;\n\t\t\tgpios = <&gpio1 18 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled-6 {\n\t\t\tfunction = LED_FUNCTION_DISK;\n\t\t\tfunction-enumerator = <2>;\n\t\t\tcolor = <LED_COLOR_ID_RED>;\n\t\t\tgpios = <&gpio1 19 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled-7 {\n\t\t\tfunction = LED_FUNCTION_INDICATOR;\n\t\t\tcolor = <LED_COLOR_ID_BLUE>;\n\t\t\tgpios = <&gpio1 20 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tled-8 {\n\t\t\tfunction = LED_FUNCTION_DISK_ERR;\n\t\t\tcolor = <LED_COLOR_ID_RED>;\n\t\t\tgpios = <&gpio1 21 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled-9 {\n\t\t\tfunction = LED_FUNCTION_DISK_ERR;\n\t\t\tcolor = <LED_COLOR_ID_GREEN>;\n\t\t\tgpios = <&gpio1 23 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_status_red: led-10 {\n\t\t\tlabel = \"red:status\";\n\t\t\tfunction = LED_FUNCTION_STATUS;\n\t\t\tcolor = <LED_COLOR_ID_RED>;\n\t\t\tgpios = <&gpio1 24 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled-11 {\n\t\t\tfunction = LED_FUNCTION_DISK;\n\t\t\tfunction-enumerator = <1>;\n\t\t\tcolor = <LED_COLOR_ID_GREEN>;\n\t\t\tgpios = <&gpio1 25 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"ata1\";\n\t\t};\n\n\t\tled_status_green: led-12 {\n\t\t\tlabel = \"green:status\";\n\t\t\tfunction = LED_FUNCTION_STATUS;\n\t\t\tcolor = <LED_COLOR_ID_GREEN>;\n\t\t\tgpios = <&gpio1 26 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&coherencyfab {\n\tbroken-idle;\n};\n\n&eth1 {\n\tpinctrl-0 = <&ge1_rgmii_pins>;\n\tpinctrl-names = \"default\";\n\tstatus = \"okay\";\n\tphy-handle = <&ethphy0>;\n\tphy-connection-type = \"rgmii-id\";\n};\n\n&i2c0 {\n\tpinctrl-0 = <&i2c0_pins>;\n\tpinctrl-names = \"default\";\n\tclock-frequency = <100000>;\n\tstatus = \"okay\";\n\n\thwmon@2a {\n\t\tcompatible = \"nuvoton,nct7802\";\n\t\treg = <0x2a>;\n\t};\n\n\trtc@30 {\n\t\tcompatible = \"sii,s35390a\";\n\t\treg = <0x30>;\n\t};\n};\n\n&mdio {\n\tpinctrl-0 = <&mdio_pins>;\n\tpinctrl-names = \"default\";\n\n\tethphy0: ethernet-phy@0 { /* Marvell 88E1318 */\n\t\treg = <0>;\n\t\t#thermal-sensor-cells = <0>;\n\t};\n};\n\n&nand_controller {\n\tstatus = \"okay\";\n\n\tnand@0 {\n\t\treg = <0>;\n\t\tlabel = \"pxa3xx_nand-0\";\n\t\tnand-rb = <0>;\n\t\tmarvell,nand-keep-config;\n\t\tnand-on-flash-bbt;\n\t\tnand-ecc-strength = <4>;\n\t\tnand-ecc-step-size = <512>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"uboot\";\n\t\t\t\treg = <0x0000000 0x200000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@200000 {\n\t\t\t\tlabel = \"certificate\";\n\t\t\t\treg = <0x0200000 0x100000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@300000 {\n\t\t\t\tlabel = \"preset_cfg\";\n\t\t\t\treg = <0x0300000 0x100000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@400000 {\n\t\t\t\tlabel = \"dev_params\";\n\t\t\t\treg = <0x0400000 0x100000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@500000 {\n\t\t\t\tlabel = \"active_bank\";\n\t\t\t\treg = <0x0500000 0x0100000>;\n\t\t\t};\n\n\t\t\tpartition@600000 {\n\t\t\t\tlabel = \"magic\";\n\t\t\t\treg = <0x0600000 0x0100000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@700000 {\n\t\t\t\tlabel = \"bank1\";\n\t\t\t\treg = <0x0700000 0x2800000>;\n\t\t\t};\n\n\t\t\tpartition@2f00000 {\n\t\t\t\tlabel = \"bank2\";\n\t\t\t\treg = <0x2f00000 0x2800000>;\n\t\t\t};\n\n\t\t\t/* 0x5700000-0x5a00000 undefined in vendor firmware */\n\n\t\t\tpartition@5a00000 {\n\t\t\t\tlabel = \"reserved\";\n\t\t\t\treg = <0x5a00000 0x2000000>;\n\t\t\t};\n\n\t\t\tpartition@7a00000 {\n\t\t\t\tlabel = \"ubi\";\n\t\t\t\treg = <0x7a00000 0x8600000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pciec {\n\tstatus = \"okay\";\n\n\tpcie@1,0 {\n\t\tpinctrl-0 = <&pmx_pcie>;\n\t\tpinctrl-names = \"default\";\n\t\tstatus = \"okay\";\n\t\treset-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>;\n\n\t\t/* -[0000:00]---01.0-[01]----00.0 */\n\t\t/* usbport trigger won't work */\n\t\tbridge@0,1 {\n\t\t\tcompatible = \"pci11ab,6710\";\n\t\t\treg = <0x3800 0 0 0 0>;\n\t\t\t#address-cells = <3>;\n\t\t\t#size-cells = <2>;\n\n\t\t\tusb@1,0 {\n\t\t\t\t/* Renesas uPD720202 */\n\t\t\t\tcompatible = \"pci1912,0015\";\n\t\t\t\treg = <0x1000 0 0 0 0>;\n\t\t\t\t#address-cells = <3>;\n\t\t\t\t#size-cells = <2>;\n\n\t\t\t\tusb1_port: port@1 {\n\t\t\t\t\treg = <1>;\n\t\t\t\t\t#trigger-source-cells = <1>;\n\t\t\t\t};\n\n\t\t\t\tusb2_port: port@2 {\n\t\t\t\t\treg = <2>;\n\t\t\t\t\t#trigger-source-cells = <1>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pinctrl {\n\tpmx_poweroff: pmx-poweroff {\n\t\tmarvell,pins = \"mpp7\";\n\t\tmarvell,function = \"gpo\";\n\t};\n\n\tpmx_power_cpu: pmx-power-cpu {\n\t\tmarvell,pins = \"mpp4\";\n\t\tmarvell,function = \"vdd\";\n\t};\n\n\tpmx_buttons: pmx-buttons {\n\t\tmarvell,pins = \"mpp6\", \"mpp10\", \"mpp14\", \"mpp32\";\n\t\tmarvell,function = \"gpio\";\n\t};\n\n\tpmx_leds1: pmx-leds1 {\n\t\tmarvell,pins = \"mpp47\";\n\t\tmarvell,function = \"gpo\";\n\t};\n\n\tpmx_leds2: pmx-leds2 {\n\t\tmarvell,pins = \"mpp12\", \"mpp13\", \"mpp15\", \"mpp16\", \"mpp50\", \"mpp51\",\n\t\t\t       \"mpp52\", \"mpp53\", \"mpp55\", \"mpp56\", \"mpp57\", \"mpp58\";\n\t\tmarvell,function = \"gpio\";\n\t};\n\n\tpmx_pcie: pmx-pcie {\n\t\tmarvell,pins = \"mpp59\";\n\t\tmarvell,function = \"gpio\";\n\t};\n\n\t/* this gpio is connected to the pin of buzzer\n\t * leave it as is due lack of proper driver\n\t */\n\tpmx_buzzer: pmx-buzzer {\n\t\tmarvell,pins = \"mpp63\";\n\t\tmarvell,function = \"gpio\";\n\t};\n};\n\n&pmsu {\n\tpinctrl-0 = <&pmx_power_cpu>;\n\tpinctrl-names = \"default\";\n};\n\n&rtc {\n\tstatus = \"disabled\";\n};\n\n&sata {\n\tnr-ports = <2>;\n\tstatus = \"okay\";\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\n\thdd0_temp: sata-port@0 {\n\t\treg = <0>;\n\t\t#thermal-sensor-cells = <0>;\n\t};\n\n\thdd1_temp: sata-port@1 {\n\t\treg = <1>;\n\t\t#thermal-sensor-cells = <0>;\n\t};\n};\n\n&uart0 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/mvebu/files/arch/arm/boot/dts/armada-385-linksys-venom.dts",
    "content": "/*\n * Device Tree file for the Linksys WRT32X (Venom)\n *\n * Copyright (C) 2017 Imre Kaloz <kaloz@openwrt.org>\n *\n *\n * This file is dual-licensed: you can use it either under the terms\n * of the GPL or the X11 license, at your option. Note that this dual\n * licensing only applies to this file, and not this project as a\n * whole.\n *\n *  a) This file is licensed under the terms of the GNU General Public\n *     License version 2.  This program is licensed \"as is\" without\n *     any warranty of any kind, whether express or implied.\n *\n * Or, alternatively,\n *\n *  b) Permission is hereby granted, free of charge, to any person\n *     obtaining a copy of this software and associated documentation\n *     files (the \"Software\"), to deal in the Software without\n *     restriction, including without limitation the rights to use,\n *     copy, modify, merge, publish, distribute, sublicense, and/or\n *     sell copies of the Software, and to permit persons to whom the\n *     Software is furnished to do so, subject to the following\n *     conditions:\n *\n *     The above copyright notice and this permission notice shall be\n *     included in all copies or substantial portions of the Software.\n *\n *     THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n *     OTHER DEALINGS IN THE SOFTWARE.\n */\n\n/dts-v1/;\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n#include \"armada-385-linksys.dtsi\"\n\n/ {\n\tmodel = \"Linksys WRT32X\";\n\tcompatible = \"linksys,wrt32x\", \"linksys,venom\", \"linksys,armada385\",\n\t\t     \"marvell,armada385\", \"marvell,armada380\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200\";\n\t\tstdout-path = \"serial0:115200n8\";\n\t\tappend-rootblock = \"root=/dev/mtdblock\";\n\t};\n};\n\n&expander0 {\n\twan_amber@0 {\n\t\tlabel = \"venom:amber:wan\";\n\t\treg = <0x0>;\n\t};\n\n\twan_blue@1 {\n\t\tlabel = \"venom:blue:wan\";\n\t\treg = <0x1>;\n\t};\n\n\tusb2@5 {\n\t\tlabel = \"venom:blue:usb2\";\n\t\treg = <0x5>;\n\t};\n\n\tusb3_1@6 {\n\t\tlabel = \"venom:blue:usb3_1\";\n\t\treg = <0x6>;\n\t};\n\n\tusb3_2@7 {\n\t\tlabel = \"venom:blue:usb3_2\";\n\t\treg = <0x7>;\n\t};\n\n\twps_blue@8 {\n\t\tlabel = \"venom:blue:wps\";\n\t\treg = <0x8>;\n\t};\n\n\twps_amber@9 {\n\t\tlabel = \"venom:amber:wps\";\n\t\treg = <0x9>;\n\t};\n};\n\n&gpio_leds {\n\tpower {\n\t\tgpios = <&gpio1 24 GPIO_ACTIVE_HIGH>;\n\t\tlabel = \"venom:blue:power\";\n\t};\n\n\tsata {\n\t\tgpios = <&gpio1 21 GPIO_ACTIVE_LOW>;\n\t\tlabel = \"venom:blue:sata\";\n\t};\n\n\twlan_2g {\n\t\tgpios = <&gpio1 13 GPIO_ACTIVE_LOW>;\n\t\tlabel = \"venom:blue:wlan_2g\";\n\t};\n\n\twlan_5g {\n\t\tgpios = <&gpio1 14 GPIO_ACTIVE_LOW>;\n\t\tlabel = \"venom:blue:wlan_5g\";\n\t};\n};\n\n&gpio_leds_pins {\n\tmarvell,pins = \"mpp21\", \"mpp45\", \"mpp46\", \"mpp56\";\n};\n\n&nand {\n\t/* Spansion S34ML02G2 256MiB, OEM Layout */\n\tpartitions {\n\t\tcompatible = \"fixed-partitions\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"u-boot\";\n\t\t\treg = <0x0000000 0x200000>;\t/* 2MB */\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@200000 {\n\t\t\tlabel = \"u_env\";\n\t\t\treg = <0x200000 0x20000>;\t/* 128KB */\n\t\t};\n\n\t\tpartition@220000 {\n\t\t\tlabel = \"s_env\";\n\t\t\treg = <0x220000 0x40000>;\t/* 256KB */\n\t\t};\n\n\t\tpartition@180000 {\n\t\t\tlabel = \"unused_area\";\n\t\t\treg = <0x260000 0x5c0000>;\t/* 5.75MB */\n\t\t};\n\n\t\tpartition@7e0000 {\n\t\t\tlabel = \"devinfo\";\n\t\t\treg = <0x7e0000 0x40000>;\t/* 256KB */\n\t\t\tread-only;\n\t\t};\n\n\t\t/* kernel1 overlaps with rootfs1 by design */\n\t\tpartition@900000 {\n\t\t\tlabel = \"kernel1\";\n\t\t\treg = <0x900000 0x7b00000>;\t/* 123MB */\n\t\t};\n\n\t\tpartition@f00000 {\n\t\t\tlabel = \"rootfs1\";\n\t\t\treg = <0xf00000 0x7500000>;\t/* 117MB */\n\t\t};\n\n\t\t/* kernel2 overlaps with rootfs2 by design */\n\t\tpartition@8400000 {\n\t\t\tlabel = \"kernel2\";\n\t\t\treg = <0x8400000 0x7b00000>;\t/* 123MB */\n\t\t};\n\n\t\tpartition@8a00000 {\n\t\t\tlabel = \"rootfs2\";\n\t\t\treg = <0x8a00000 0x7500000>;\t/* 117MB */\n\t\t};\n\n\t\t/* last MB is for the BBT, not writable */\n\t\tpartition@ff00000 {\n\t\t\tlabel = \"BBT\";\n\t\t\treg = <0xff00000 0x100000>;\n\t\t};\n\t};\n};\n\n\n&pcie1 {\n\tmwlwifi {\n\t\tmarvell,chainmask = <4 4>;\n\t};\n};\n\n&pcie2 {\n\tmwlwifi {\n\t\tmarvell,chainmask = <4 4>;\n\t};\n};\n\n&sdhci {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&sdhci_pins>;\n\tno-1-8-v;\n\tnon-removable;\n\twp-inverted;\n\tbus-width = <8>;\n\tstatus = \"okay\";\n};\n\n&usb3_1_vbus {\n\tgpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;\n};\n\n&usb3_1_vbus_pins {\n\tmarvell,pins = \"mpp44\";\n};\n"
  },
  {
    "path": "target/linux/mvebu/files/arch/arm/boot/dts/armada-385-nas1dual.dts",
    "content": "// SPDX-License-Identifier: (GPL-2.0-only OR MIT)\n/*\n * Device Tree file for ipTIME NAS1dual\n *\n * Copyright (C) 2020 Sungbo Eo <mans0n@gorani.run>\n *\n * Based on armada-385-linksys.dtsi\n * Copyright (C) 2015 Imre Kaloz <kaloz@openwrt.org>\n */\n\n/dts-v1/;\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n#include \"armada-385.dtsi\"\n\n/ {\n\tmodel = \"ipTIME NAS1dual\";\n\tcompatible = \"iptime,nas1dual\", \"marvell,armada385\", \"marvell,armada380\";\n\n\taliases {\n\t\tled-boot = &led_ready;\n\t\tled-failsafe = &led_ready;\n\t\tled-running = &led_ready;\n\t\tled-upgrade = &led_ready;\n\t\tlabel-mac-device = &eth0;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200n8\";\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\tmemory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x00000000 0x80000000>; /* 2GB */\n\t};\n\n\tsoc {\n\t\tranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000\n\t\t          MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000\n\t\t          MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000\n\t\t          MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000\n\t\t          MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;\n\t};\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tpinctrl-names = \"default\";\n\t\tpinctrl-0 = <&gpio_keys_pins>;\n\n\t\tpower {\n\t\t\tlabel = \"Power Button\";\n\t\t\tlinux,input-type = <EV_SW>;\n\t\t\tlinux,code = <KEY_POWER>;\n\t\t\tgpios = <&gpio0 24 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"Reset Button\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio0 26 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tcopy {\n\t\t\tlabel = \"USB Copy Button\";\n\t\t\tlinux,code = <KEY_COPY>;\n\t\t\tgpios = <&gpio1 16 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tgpio-leds {\n\t\tcompatible = \"gpio-leds\";\n\t\tpinctrl-names = \"default\";\n\t\tpinctrl-0 = <&gpio_leds_pins>;\n\n\t\tled_ready: ready {\n\t\t\tlabel = \"blue:ready\";\n\t\t\tgpios = <&gpio0 18 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\thdd {\n\t\t\tlabel = \"blue:hdd\";\n\t\t\tgpios = <&gpio0 20 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"disk-activity\";\n\t\t};\n\n\t\tusb {\n\t\t\tlabel = \"blue:usb\";\n\t\t\tgpios = <&gpio1 19 GPIO_ACTIVE_HIGH>;\n\t\t\ttrigger-sources = <&usb3_0_port1 &usb3_0_port2>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\t};\n\n\tgpio-fan {\n\t\tcompatible = \"gpio-fan\";\n\t\tpinctrl-names = \"default\";\n\t\tpinctrl-0 = <&gpio_fan_pins>;\n\t\tgpios = <&gpio0 25 GPIO_ACTIVE_HIGH>,\n\t\t        <&gpio1 18 GPIO_ACTIVE_HIGH>;\n\t\t/* We don't know the exact rpm, just use dummy values here. */\n\t\tgpio-fan,speed-map = <0 0>, <1 1>, <2 2>;\n\t\t#cooling-cells = <2>;\n\t};\n\n\tgpio-poweroff {\n\t\tcompatible = \"gpio-poweroff\";\n\t\tgpios = <&pca9536 1 GPIO_ACTIVE_LOW>;\n\t};\n\n\tregulators {\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tpinctrl-names = \"default\";\n\t\tpinctrl-0 = <&sata_power_pins>;\n\n\t\treg_sata_power: regulator@1 {\n\t\t\tcompatible = \"regulator-fixed\";\n\t\t\treg = <1>;\n\t\t\tregulator-name = \"sata-power\";\n\t\t\tregulator-min-microvolt = <12000000>;\n\t\t\tregulator-max-microvolt = <12000000>;\n\t\t\tgpio = <&gpio1 20 GPIO_ACTIVE_LOW>;\n\t\t\tregulator-always-on;\n\t\t};\n\t};\n};\n\n&ahci0 {\n\tstatus = \"okay\";\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\n\tsata-port@0 {\n\t\treg = <0>;\n\t\ttarget-supply = <&reg_sata_power>;\n\t\t#thermal-sensor-cells = <0>;\n\t};\n};\n\n&bm {\n\tstatus = \"okay\";\n};\n\n&bm_bppi {\n\tstatus = \"okay\";\n};\n\n&eth0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&ge0_rgmii_pins>;\n\tstatus = \"okay\";\n\tphy-handle = <&ethphy1>;\n\tphy-connection-type = \"rgmii-id\";\n\tbuffer-manager = <&bm>;\n\tbm,pool-long = <0>;\n\tbm,pool-short = <1>;\n\tnvmem-cells = <&macaddr_uboot_fffa8>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&eth1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&ge1_rgmii_pins>;\n\tstatus = \"okay\";\n\tphy-handle = <&ethphy0>;\n\tphy-connection-type = \"rgmii-id\";\n\tbuffer-manager = <&bm>;\n\tbm,pool-long = <2>;\n\tbm,pool-short = <3>;\n\tnvmem-cells = <&macaddr_uboot_fffa8>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&i2c0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&i2c0_pins>;\n\tstatus = \"okay\";\n\n\tpca9536: gpio@41 {\n\t\tcompatible = \"nxp,pca9536\";\n\t\treg = <0x41>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\tgpio-line-names = \"power-led\", \"power-board\";\n\t};\n};\n\n&mdio {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&mdio_pins>;\n\n\t/* LED1: On - Link, Blink - Activity, Off - No Link */\n\n\tethphy0: ethernet-phy@0 {\n\t\treg = <0>;\n\t\tmarvell,reg-init = <3 16 0 0x1017>;\n\t};\n\n\tethphy1: ethernet-phy@1 {\n\t\treg = <1>;\n\t\tmarvell,reg-init = <3 16 0 0x1017>;\n\t};\n};\n\n&pinctrl {\n\tgpio_keys_pins: gpio-keys-pins {\n\t\tmarvell,pins = \"mpp24\", \"mpp26\", \"mpp48\";\n\t\tmarvell,function = \"gpio\";\n\t};\n\n\tgpio_leds_pins: gpio-leds-pins {\n\t\tmarvell,pins = \"mpp18\", \"mpp20\", \"mpp51\";\n\t\tmarvell,function = \"gpio\";\n\t};\n\n\tgpio_fan_pins: gpio-fan-pins {\n\t\tmarvell,pins = \"mpp25\", \"mpp50\";\n\t\tmarvell,function = \"gpio\";\n\t};\n\n\tsata_power_pins: sata-power-pins {\n\t\tmarvell,pins = \"mpp52\";\n\t\tmarvell,function = \"gpio\";\n\t};\n\n\tuart1_pins_alt: uart-pins-1-alt {\n\t\tmarvell,pins = \"mpp45\", \"mpp46\";\n\t\tmarvell,function = \"ua1\";\n\t};\n};\n\n&spi1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&spi1_pins>;\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <40000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\treg = <0x00000000 0x00100000>;\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\tread-only;\n\n\t\t\t\tcompatible = \"nvmem-cells\";\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\n\t\t\t\tmacaddr_uboot_fffa8: macaddr@fffa8 {\n\t\t\t\t\treg = <0xfffa8 0x6>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tpartition@100000 {\n\t\t\t\treg = <0x00100000 0x03ec0000>;\n\t\t\t\tlabel = \"firmware\";\n\n\t\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\n\t\t\t\tpartition@0 {\n\t\t\t\t\treg = <0x00000000 0x00600000>;\n\t\t\t\t\tlabel = \"kernel\";\n\t\t\t\t};\n\n\t\t\t\tpartition@600000 {\n\t\t\t\t\treg = <0x00600000 0x038c0000>;\n\t\t\t\t\tlabel = \"rootfs\";\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tpartition@3fc0000 {\n\t\t\t\treg = <0x03fc0000 0x00040000>;\n\t\t\t\tlabel = \"config\";\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&uart0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&uart0_pins>;\n\tstatus = \"okay\";\n};\n\n&uart1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&uart1_pins_alt>;\n\tstatus = \"okay\";\n};\n\n&usb3_0 {\n\tstatus = \"okay\";\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\n\tusb3_0_port1: port@1 {\n\t\treg = <1>;\n\t\t#trigger-source-cells = <0>;\n\t};\n\n\tusb3_0_port2: port@2 {\n\t\treg = <2>;\n\t\t#trigger-source-cells = <0>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/mvebu/files/arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts",
    "content": "// SPDX-License-Identifier: (GPL-2.0+ OR MIT)\n/*\n * Device Tree file for ESPRESSObin-Ultra\n * Copyright (C) 2019 Globalscale technologies, Inc.\n *\n * Jason Hung <jhung@globalscaletechnologies.com>\n */\n\n/dts-v1/;\n\n#include <dt-bindings/gpio/gpio.h>\n#include \"armada-372x.dtsi\"\n\n/ {\n\tmodel = \"Globalscale Marvell ESPRESSOBin Ultra Board\";\n\tcompatible = \"globalscale,espressobin-ultra\", \"marvell,armada3720\",\n\t\t     \"marvell,armada3710\";\n\n\taliases {\n\t\t/* for dsa slave device */\n\t\tethernet1 = &switch0port1;\n\t\tethernet2 = &switch0port2;\n\t\tethernet3 = &switch0port3;\n\t\tethernet4 = &switch0port4;\n\t\tethernet5 = &switch0port5;\n\t};\n\n\tchosen {\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\tmemory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x00000000 0x00000000 0x00000000 0x20000000>;\n\t};\n\n\treg_usb3_vbus: usb3-vbus {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"usb3-vbus\";\n\t\tregulator-min-microvolt = <5000000>;\n\t\tregulator-max-microvolt = <5000000>;\n\t\tenable-active-high;\n\t\tgpio = <&gpionb 19 GPIO_ACTIVE_HIGH>;\n\t};\n\n\tusb3_phy: usb3-phy {\n\t\tcompatible = \"usb-nop-xceiv\";\n\t\tvcc-supply = <&reg_usb3_vbus>;\n\t};\n\n\tleds {\n\t\tpinctrl-names = \"default\";\n\t\tcompatible = \"gpio-leds\";\n\t\t/* No assigned functions to the LEDs by default */\n\t\tled1 {\n\t\t\tlabel = \"ebin-ultra:blue:led1\";\n\t\t\tgpios = <&gpionb 11 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tled2 {\n\t\t\tlabel = \"ebin-ultra:green:led2\";\n\t\t\tgpios = <&gpionb 12 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tled3 {\n\t\t\tlabel = \"ebin-ultra:red:led3\";\n\t\t\tgpios = <&gpionb 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tled4 {\n\t\t\tlabel = \"ebin-ultra:yellow:led4\";\n\t\t\tgpios = <&gpionb 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&pcie0 {\n\tstatus = \"okay\";\n};\n\n&sata {\n\tstatus = \"okay\";\n};\n\n&sdhci0 {\n\tstatus = \"okay\";\n\tnon-removable;\n\tbus-width = <8>;\n\tmmc-ddr-1_8v;\n\tmmc-hs400-1_8v;\n\tmarvell,pad-type = \"fixed-1-8v\";\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&spi_quad_pins>;\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <108000000>;\n\t\tspi-rx-bus-width = <4>;\n\t\tspi-tx-bus-width = <4>;\n\t\tm25p,fast-read;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x0 0x3e0000>;\n\t\t\t};\n\t\t\tpartition@3e0000 {\n\t\t\t\tlabel = \"hw-info\";\n\t\t\t\treg = <0x3e0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@3f0000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x3f0000 0x10000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&uart0 {\n\tstatus = \"okay\";\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&uart1_pins>;\n};\n\n&i2c0 {\n\tstatus = \"okay\";\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&i2c1_pins>;\n\n\tclock-frequency = <100000>;\n\n\trtc@51 {\n\t\tcompatible = \"nxp,pcf8563\";\n\t\treg = <0x51>;\n\t};\n};\n\n&usb3 {\n\tstatus = \"okay\";\n\tusb-phy = <&usb3_phy>;\n};\n\n&usb2 {\n\tstatus = \"okay\";\n};\n\n&eth0 {\n\tstatus = \"okay\";\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&rgmii_pins>;\n\tphy-mode = \"rgmii-id\";\n\n\tfixed-link {\n\t\tspeed = <1000>;\n\t\tfull-duplex;\n\t};\n};\n\n&mdio {\n\tstatus = \"okay\";\n\n\textphy: ethernet-phy@0 {\n\t\treg = <1>;\n\t};\n\n\tswitch0: switch0@1 {\n\t\tcompatible = \"marvell,mv88e6085\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <3>;\n\n\t\tdsa,member = <0 0>;\n\n\t\tports {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\n\t\t\tswitch0port0: port@0 {\n\t\t\t\treg = <0>;\n\t\t\t\tlabel = \"cpu\";\n\t\t\t\tethernet = <&eth0>;\n\t\t\t};\n\n\t\t\tswitch0port1: port@1 {\n\t\t\t\treg = <1>;\n\t\t\t\tlabel = \"lan0\";\n\t\t\t\tphy-handle = <&switch0phy1>;\n\t\t\t};\n\n\t\t\tswitch0port2: port@2 {\n\t\t\t\treg = <2>;\n\t\t\t\tlabel = \"lan1\";\n\t\t\t\tphy-handle = <&switch0phy2>;\n\t\t\t};\n\n\t\t\tswitch0port3: port@3 {\n\t\t\t\treg = <3>;\n\t\t\t\tlabel = \"lan2\";\n\t\t\t\tphy-handle = <&switch0phy3>;\n\t\t\t};\n\n\t\t\tswitch0port4: port@4 {\n\t\t\t\treg = <4>;\n\t\t\t\tlabel = \"lan3\";\n\t\t\t\tphy-handle = <&switch0phy4>;\n\t\t\t};\n\n\t\t\tswitch0port5: port@5 {\n\t\t\t\treg = <5>;\n\t\t\t\tlabel = \"wan\";\n\t\t\t\tphy-handle = <&extphy>;\n\t\t\t\tphy-mode = \"sgmii\";\n\t\t\t};\n\t\t};\n\n\t\tmdio {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\n\t\t\tswitch0phy1: switch0phy1@11 {\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\tswitch0phy2: switch0phy2@12 {\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t\tswitch0phy3: switch0phy3@13 {\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t\tswitch0phy4: switch0phy4@14 {\n\t\t\t\treg = <0x14>;\n\t\t\t};\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/mvebu/files/arch/arm64/boot/dts/marvell/armada-3720-gl-mv1000.dts",
    "content": "// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)\n\n/dts-v1/;\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n#include \"armada-372x.dtsi\"\n\n/ {\n\tmodel = \"GL.iNet GL-MV1000\";\n\tcompatible = \"glinet,gl-mv1000\", \"marvell,armada3720\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tchosen {\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\tmemory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x00000000 0x00000000 0x00000000 0x20000000>;\n\t};\n\n\tvcc_sd_reg1: regulator {\n\t\tcompatible = \"regulator-gpio\";\n\t\tregulator-name = \"vcc_sd1\";\n\t\tregulator-min-microvolt = <1800000>;\n\t\tregulator-max-microvolt = <3300000>;\n\t\tregulator-boot-on;\n\n\t\tgpios-states = <0>;\n\t\tstates = <1800000 0x1\n\t\t\t3300000 0x0>;\n\t\tenable-active-high;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpionb 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tswitch {\n\t\t\tlabel = \"switch\";\n\t\t\tlinux,code = <BTN_0>;\n\t\t\tgpios = <&gpiosb 22 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tvpn {\n\t\t\tlabel = \"green:vpn\";\n\t\t\tgpios = <&gpionb 11 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twan {\n\t\t\tlabel = \"green:wan\";\n\t\t\tgpios = <&gpionb 12 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_power: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpionb 13 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\treg = <0>;\n\t\tcompatible = \"jedec,spi-nor\";\n\t\tspi-max-frequency = <104000000>;\n\t\tm25p,fast-read;\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0 0xf0000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@f0000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0Xf0000 0x8000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@f8000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0xf8000 0x8000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&sdhci1 {\n\twp-inverted;\n\tbus-width = <4>;\n\tcd-gpios = <&gpionb 17 GPIO_ACTIVE_LOW>;\n\tmarvell,pad-type = \"sd\";\n\tno-1-8-v;\n\tvqmmc-supply = <&vcc_sd_reg1>;\n\tstatus = \"okay\";\n};\n\n&sdhci0 {\n\tbus-width = <8>;\n\tmmc-ddr-1_8v;\n\tmmc-hs400-1_8v;\n\tnon-removable;\n\tno-sd;\n\tno-sdio;\n\tmarvell,pad-type = \"fixed-1-8v\";\n\tstatus = \"okay\";\n};\n\n&usb3 {\n\tstatus = \"okay\";\n};\n\n&usb2 {\n\tstatus = \"okay\";\n};\n\n&uart0 {\n\tstatus = \"okay\";\n};\n\n&mdio {\n\tswitch0: switch0@1 {\n\t\tcompatible = \"marvell,mv88e6085\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <1>;\n\n\t\tdsa,member = <0 0>;\n\n\t\tports: ports {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\n\t\t\tport@0 {\n\t\t\t\treg = <0>;\n\t\t\t\tlabel = \"cpu\";\n\t\t\t\tethernet = <&eth0>;\n\t\t\t};\n\n\t\t\tport@1 {\n\t\t\t\treg = <1>;\n\t\t\t\tlabel = \"wan\";\n\t\t\t\tphy-handle = <&switch0phy0>;\n\t\t\t};\n\n\t\t\tport@2 {\n\t\t\t\treg = <2>;\n\t\t\t\tlabel = \"lan0\";\n\t\t\t\tphy-handle = <&switch0phy1>;\n\n\t\t\t\tnvmem-cells = <&macaddr_factory_6>;\n\t\t\t\tnvmem-cell-names = \"mac-address\";\n\t\t\t};\n\n\t\t\tport@3 {\n\t\t\t\treg = <3>;\n\t\t\t\tlabel = \"lan1\";\n\t\t\t\tphy-handle = <&switch0phy2>;\n\n\t\t\t\tnvmem-cells = <&macaddr_factory_6>;\n\t\t\t\tnvmem-cell-names = \"mac-address\";\n\t\t\t};\n\t\t};\n\n\t\tmdio {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\n\t\t\tswitch0phy0: switch0phy0@11 {\n\t\t\t\treg = <0x11>;\n\t\t\t};\n\t\t\tswitch0phy1: switch0phy1@12 {\n\t\t\t\treg = <0x12>;\n\t\t\t};\n\t\t\tswitch0phy2: switch0phy2@13 {\n\t\t\t\treg = <0x13>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&eth0 {\n\tnvmem-cells = <&macaddr_factory_0>;\n\tnvmem-cell-names = \"mac-address\";\n\tphy-mode = \"rgmii-id\";\n\tstatus = \"okay\";\n\n\tfixed-link {\n\t\tspeed = <1000>;\n\t\tfull-duplex;\n\t};\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n\n\tmacaddr_factory_6: macaddr@6 {\n\t\treg = <0x6 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/mvebu/files/arch/arm64/boot/dts/marvell/armada-7040-mochabin.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n/*\n * Device Tree file for Globalscale MOCHAbin\n * Copyright (C) 2019 Globalscale technologies, Inc.\n * Copyright (C) 2021 Sartura Ltd.\n *\n */\n\n/dts-v1/;\n\n#include <dt-bindings/gpio/gpio.h>\n#include \"armada-7040.dtsi\"\n\n/ {\n\tmodel = \"Globalscale MOCHAbin\";\n\tcompatible = \"globalscale,mochabin\", \"marvell,armada7040\",\n\t\t     \"marvell,armada-ap806-quad\", \"marvell,armada-ap806\";\n\n\tchosen {\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\taliases {\n\t\tethernet0 = &cp0_eth0;\n\t\tethernet1 = &cp0_eth1;\n\t\tethernet2 = &cp0_eth2;\n\t\tethernet3 = &swport1;\n\t\tethernet4 = &swport2;\n\t\tethernet5 = &swport3;\n\t\tethernet6 = &swport4;\n\t};\n\n\t/* SFP+ 10G */\n\tsfp_eth0: sfp-eth0 {\n\t\tcompatible = \"sff,sfp\";\n\t\ti2c-bus = <&cp0_i2c1>;\n\t\tlos-gpio = <&sfp_gpio 3 GPIO_ACTIVE_HIGH>;\n\t\tmod-def0-gpio = <&sfp_gpio 2 GPIO_ACTIVE_LOW>;\n\t\ttx-disable-gpio = <&sfp_gpio 1 GPIO_ACTIVE_HIGH>;\n\t\ttx-fault-gpio  = <&sfp_gpio 0 GPIO_ACTIVE_HIGH>;\n\t};\n\n\t/* SFP 1G */\n\tsfp_eth2: sfp-eth2 {\n\t\tcompatible = \"sff,sfp\";\n\t\ti2c-bus = <&cp0_i2c0>;\n\t\tlos-gpio = <&sfp_gpio 7 GPIO_ACTIVE_HIGH>;\n\t\tmod-def0-gpio = <&sfp_gpio 6 GPIO_ACTIVE_LOW>;\n\t\ttx-disable-gpio = <&sfp_gpio 5 GPIO_ACTIVE_HIGH>;\n\t\ttx-fault-gpio  = <&sfp_gpio 4 GPIO_ACTIVE_HIGH>;\n\t};\n};\n\n/* microUSB UART console */\n&uart0 {\n\tstatus = \"okay\";\n\n\tpinctrl-0 = <&uart0_pins>;\n\tpinctrl-names = \"default\";\n};\n\n/* eMMC */\n&ap_sdhci0 {\n\tstatus = \"okay\";\n\n\tbus-width = <4>;\n\tnon-removable;\n\t/delete-property/ marvell,xenon-phy-slow-mode;\n\tno-1-8-v;\n};\n\n&cp0_pinctrl {\n\tcp0_uart0_pins: cp0-uart0-pins {\n\t\tmarvell,pins = \"mpp6\", \"mpp7\";\n\t\tmarvell,function = \"uart0\";\n\t};\n\n\tcp0_spi0_pins: cp0-spi0-pins {\n\t\tmarvell,pins = \"mpp56\", \"mpp57\", \"mpp58\", \"mpp59\";\n\t\tmarvell,function = \"spi0\";\n\t};\n\n\tcp0_spi1_pins: cp0-spi1-pins {\n\t\tmarvell,pins = \"mpp13\", \"mpp14\", \"mpp15\", \"mpp16\";\n\t\tmarvell,function = \"spi1\";\n\t};\n\n\tcp0_i2c0_pins: cp0-i2c0-pins {\n\t\tmarvell,pins = \"mpp37\", \"mpp38\";\n\t\tmarvell,function = \"i2c0\";\n\t};\n\n\tcp0_i2c1_pins: cp0-i2c1-pins {\n\t\tmarvell,pins = \"mpp2\", \"mpp3\";\n\t\tmarvell,function = \"i2c1\";\n\t};\n\n\tpca9554_int_pins: pca9554-int-pins {\n\t\tmarvell,pins = \"mpp27\";\n\t\tmarvell,function = \"gpio\";\n\t};\n\n\tcp0_rgmii1_pins: cp0-rgmii1-pins {\n\t\tmarvell,pins = \"mpp44\", \"mpp45\", \"mpp46\", \"mpp47\", \"mpp48\", \"mpp49\",\n\t\t\t       \"mpp50\", \"mpp51\", \"mpp52\", \"mpp53\", \"mpp54\", \"mpp55\";\n\t\tmarvell,function = \"ge1\";\n\t};\n\n\tis31_sdb_pins: is31-sdb-pins {\n\t\tmarvell,pins = \"mpp30\";\n\t\tmarvell,function = \"gpio\";\n\t};\n\n\tcp0_pcie_reset_pins: cp0-pcie-reset-pins {\n\t\tmarvell,pins = \"mpp9\";\n\t\tmarvell,function = \"gpio\";\n\t};\n\n\tcp0_switch_pins: cp0-switch-pins {\n\t\tmarvell,pins = \"mpp0\", \"mpp1\";\n\t\tmarvell,function = \"gpio\";\n\t};\n\n\tcp0_phy_pins: cp0-phy-pins {\n\t\tmarvell,pins = \"mpp12\";\n\t\tmarvell,function = \"gpio\";\n\t};\n};\n\n/* mikroBUS UART */\n&cp0_uart0 {\n\tstatus = \"okay\";\n\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&cp0_uart0_pins>;\n};\n\n/* mikroBUS SPI */\n&cp0_spi0 {\n\tstatus = \"okay\";\n\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&cp0_spi0_pins>;\n};\n\n/* SPI-NOR */\n&cp0_spi1{\n\tstatus = \"okay\";\n\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&cp0_spi1_pins>;\n\n\tspi-flash@0 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <20000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x3e0000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@3e0000 {\n\t\t\t\tlabel = \"hw-info\";\n\t\t\t\treg = <0x3e0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@3f0000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x3f0000 0x10000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n/* mikroBUS, 1G SFP and GPIO expander */\n&cp0_i2c0 {\n\tstatus = \"okay\";\n\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&cp0_i2c0_pins>;\n\tclock-frequency = <100000>;\n\n\tsfp_gpio: pca9554@39 {\n\t\tcompatible = \"nxp,pca9554\";\n\t\tpinctrl-names = \"default\";\n\t\tpinctrl-0 = <&pca9554_int_pins>;\n\t\treg = <0x39>;\n\n\t\tinterrupt-parent = <&cp0_gpio1>;\n\t\tinterrupts = <27 IRQ_TYPE_LEVEL_LOW>;\n\t\tinterrupt-controller;\n\t\t#interrupt-cells = <2>;\n\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\n\t\t/*\n\t\t * IO0_0: SFP+_TX_FAULT\n\t\t * IO0_1: SFP+_TX_DISABLE\n\t\t * IO0_2: SFP+_PRSNT\n\t\t * IO0_3: SFP+_LOSS\n\t\t * IO0_4: SFP_TX_FAULT\n\t\t * IO0_5: SFP_TX_DISABLE\n\t\t * IO0_6: SFP_PRSNT\n\t\t * IO0_7: SFP_LOSS\n\t\t */\n\t};\n};\n\n/* IS31FL3199, mini-PCIe and 10G SFP+ */\n&cp0_i2c1 {\n\tstatus = \"okay\";\n\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&cp0_i2c1_pins>;\n\tclock-frequency = <100000>;\n\n\tleds@64 {\n\t\tcompatible = \"issi,is31fl3199\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tpinctrl-names = \"default\";\n\t\tpinctrl-0 = <&is31_sdb_pins>;\n\t\tshutdown-gpios = <&cp0_gpio1 30 GPIO_ACTIVE_HIGH>;\n\t\treg = <0x64>;\n\n\t\tled1_red: led@1 {\n\t\t\tlabel = \"red:led1\";\n\t\t\treg = <1>;\n\t\t\tled-max-microamp = <20000>;\n\t\t};\n\n\t\tled1_green: led@2 {\n\t\t\tlabel = \"green:led1\";\n\t\t\treg = <2>;\n\t\t};\n\n\t\tled1_blue: led@3 {\n\t\t\tlabel = \"blue:led1\";\n\t\t\treg = <3>;\n\t\t};\n\n\t\tled2_red: led@4 {\n\t\t\tlabel = \"red:led2\";\n\t\t\treg = <4>;\n\t\t};\n\n\t\tled2_green: led@5 {\n\t\t\tlabel = \"green:led2\";\n\t\t\treg = <5>;\n\t\t};\n\n\t\tled2_blue: led@6 {\n\t\t\tlabel = \"blue:led2\";\n\t\t\treg = <6>;\n\t\t};\n\n\t\tled3_red: led@7 {\n\t\t\tlabel = \"red:led3\";\n\t\t\treg = <7>;\n\t\t};\n\n\t\tled3_green: led@8 {\n\t\t\tlabel = \"green:led3\";\n\t\t\treg = <8>;\n\t\t};\n\n\t\tled3_blue: led@9 {\n\t\t\tlabel = \"blue:led3\";\n\t\t\treg = <9>;\n\t\t};\n\t};\n};\n\n&cp0_mdio {\n\tstatus = \"okay\";\n\n\t/* 88E1512 PHY */\n\teth2phy: ethernet-phy@1 {\n\t\treg = <1>;\n\t\tsfp = <&sfp_eth2>;\n\n\t\tpinctrl-names = \"default\";\n\t\tpinctrl-0 = <&cp0_phy_pins>;\n\t\treset-gpios = <&cp0_gpio1 12 GPIO_ACTIVE_LOW>;\n\t};\n\n\t/* 88E6141 Topaz switch */\n\tswitch: switch@3 {\n\t\tcompatible = \"marvell,mv88e6085\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <3>;\n\n\t\tpinctrl-names = \"default\";\n\t\tpinctrl-0 = <&cp0_switch_pins>;\n\t\treset-gpios = <&cp0_gpio1 0 GPIO_ACTIVE_LOW>;\n\n\t\tinterrupt-parent = <&cp0_gpio1>;\n\t\tinterrupts = <1 IRQ_TYPE_LEVEL_LOW>;\n\n\t\tports {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\n\t\t\tswport1: port@1 {\n\t\t\t\treg = <1>;\n\t\t\t\tlabel = \"lan0\";\n\t\t\t\tphy-handle = <&swphy1>;\n\t\t\t};\n\n\t\t\tswport2: port@2 {\n\t\t\t\treg = <2>;\n\t\t\t\tlabel = \"lan1\";\n\t\t\t\tphy-handle = <&swphy2>;\n\t\t\t};\n\n\t\t\tswport3: port@3 {\n\t\t\t\treg = <3>;\n\t\t\t\tlabel = \"lan2\";\n\t\t\t\tphy-handle = <&swphy3>;\n\t\t\t};\n\n\t\t\tswport4: port@4 {\n\t\t\t\treg = <4>;\n\t\t\t\tlabel = \"lan3\";\n\t\t\t\tphy-handle = <&swphy4>;\n\t\t\t};\n\n\t\t\tport@5 {\n\t\t\t\treg = <5>;\n\t\t\t\tlabel = \"cpu\";\n\t\t\t\tethernet = <&cp0_eth1>;\n\t\t\t\tphy-mode = \"2500base-x\";\n\t\t\t\tmanaged = \"in-band-status\";\n\t\t\t};\n\t\t};\n\n\t\tmdio {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\n\t\t\tswphy1: swphy1@17 {\n\t\t\t\treg = <17>;\n\t\t\t};\n\n\t\t\tswphy2: swphy2@18 {\n\t\t\t\treg = <18>;\n\t\t\t};\n\n\t\t\tswphy3: swphy3@19 {\n\t\t\t\treg = <19>;\n\t\t\t};\n\n\t\t\tswphy4: swphy4@20 {\n\t\t\t\treg = <20>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&cp0_ethernet {\n\tstatus = \"okay\";\n};\n\n/* 10G SFP+ */\n&cp0_eth0 {\n\tstatus = \"okay\";\n\n\tphy-mode = \"10gbase-r\";\n\tphys = <&cp0_comphy4 0>;\n\tmanaged = \"in-band-status\";\n\tsfp = <&sfp_eth0>;\n};\n\n/* Topaz switch uplink */\n&cp0_eth1 {\n\tstatus = \"okay\";\n\n\tphy-mode = \"2500base-x\";\n\tphys = <&cp0_comphy0 1>;\n\n\tfixed-link {\n\t\tspeed = <2500>;\n\t\tfull-duplex;\n\t};\n};\n\n/* 1G SFP or 1G RJ45 */\n&cp0_eth2 {\n\tstatus = \"okay\";\n\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&cp0_rgmii1_pins>;\n\n\tphy = <&eth2phy>;\n\tphy-mode = \"rgmii-id\";\n};\n\n/* SMSC USB5434B hub */\n&cp0_usb3_0 {\n\tstatus = \"okay\";\n\n\tphys = <&cp0_comphy1 0>;\n\tphy-names = \"cp0-usb3h0-comphy\";\n};\n\n/* miniPCI-E USB */\n&cp0_usb3_1 {\n\tstatus = \"okay\";\n};\n\n&cp0_sata0 {\n\tstatus = \"okay\";\n\n\t/* 7 + 12 SATA connector (J24) */\n\tsata-port@0 {\n\t\tphys = <&cp0_comphy2 0>;\n\t\tphy-names = \"cp0-sata0-0-phy\";\n\t};\n\n\t/* M.2-2250 B-key (J39) */\n\tsata-port@1 {\n\t\tphys = <&cp0_comphy3 1>;\n\t\tphy-names = \"cp0-sata0-1-phy\";\n\t};\n};\n\n/* miniPCI-E (J5) */\n&cp0_pcie2 {\n\tstatus = \"okay\";\n\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&cp0_pcie_reset_pins>;\n\tphys = <&cp0_comphy5 2>;\n\tphy-names = \"cp0-pcie2-x1-phy\";\n\treset-gpio = <&cp0_gpio1 9 GPIO_ACTIVE_LOW>;\n};\n"
  },
  {
    "path": "target/linux/mvebu/files/arch/arm64/boot/dts/marvell/cn9131-puzzle-m901.dts",
    "content": "// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)\n/*\n * Copyright (C) 2019 Marvell International Ltd.\n *\n * Device tree for the CN9131-DB board.\n */\n\n#include \"cn9130.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"iEi Puzzle-M901\";\n\tcompatible = \"iei,puzzle-m901\",\n\t\t     \"marvell,armada-ap807-quad\", \"marvell,armada-ap807\";\n\n\tchosen {\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\taliases {\n\t\ti2c0 = &cp1_i2c0;\n\t\ti2c1 = &cp0_i2c0;\n\t\tethernet0 = &cp0_eth0;\n\t\tethernet1 = &cp0_eth1;\n\t\tethernet2 = &cp0_eth2;\n\t\tethernet3 = &cp1_eth0;\n\t\tethernet4 = &cp1_eth1;\n\t\tethernet5 = &cp1_eth2;\n\t\tgpio1 = &cp0_gpio1;\n\t\tgpio2 = &cp0_gpio2;\n\t\tgpio3 = &cp1_gpio1;\n\t\tgpio4 = &cp1_gpio2;\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_info;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_info;\n\t};\n\n\tmemory@00000000 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x0 0x0 0x0 0x80000000>;\n\t};\n\n\tgpio_keys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"Reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&cp0_gpio2 4 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&uart0 {\n\tstatus = \"okay\";\n};\n\n&cp0_uart0 {\n\tstatus = \"okay\";\n\n\tpuzzle-mcu {\n\t\tcompatible = \"iei,wt61p803-puzzle\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcurrent-speed = <115200>;\n\t\tenable-beep;\n\t\tstatus = \"okay\";\n\n\t\tleds {\n\t\t\tcompatible = \"iei,wt61p803-puzzle-leds\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tstatus = \"okay\";\n\n\t\t\tled@0 {\n\t\t\t\treg = <0>;\n\t\t\t\tlabel = \"white:network\";\n\t\t\t\tactive-low;\n\t\t\t};\n\n\t\t\tled@1 {\n\t\t\t\treg = <1>;\n\t\t\t\tlabel = \"green:cloud\";\n\t\t\t\tactive-low;\n\t\t\t};\n\n\t\t\tled_info: led@2 {\n\t\t\t\treg = <2>;\n\t\t\t\tlabel = \"orange:info\";\n\t\t\t\tactive-low;\n\t\t\t};\n\n\t\t\tled_power: led@3 {\n\t\t\t\treg = <3>;\n\t\t\t\tlabel = \"yellow:power\";\n\t\t\t\tactive-low;\n\t\t\t\tdefault-state = \"on\";\n\t\t\t};\n\t\t};\n\n\t\thwmon {\n\t\t\tcompatible = \"iei,wt61p803-puzzle-hwmon\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\n\t\t\tchassis_fan_group0: fan-group@0 {\n\t\t\t\t#cooling-cells = <2>;\n\t\t\t\treg = <0x00>;\n\t\t\t\tcooling-levels = <64 102 170 230 250>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&ap_thermal_cpu1 {\n\ttrips {\n\t\tcpu_active: cpu-active {\n\t\t\ttemperature = <44000>;\n\t\t\thysteresis = <2000>;\n\t\t\ttype = \"active\";\n\t\t};\n\t};\n\tcooling-maps {\n\t\tfan-map {\n\t\t\ttrip = <&cpu_active>;\n\t\t\tcooling-device = <&chassis_fan_group0 64 THERMAL_NO_LIMIT>;\n\t\t};\n\t};\n};\n\n/* on-board eMMC - U9 */\n&ap_sdhci0 {\n\tpinctrl-names = \"default\";\n\tbus-width = <8>;\n\tstatus = \"okay\";\n\tmmc-ddr-1_8v;\n\tmmc-hs400-1_8v;\n};\n\n&cp0_crypto {\n\tstatus = \"okay\";\n};\n\n&cp0_xmdio {\n\tstatus = \"okay\";\n\tcp0_nbaset_phy0: ethernet-phy@0 {\n\t\tcompatible = \"ethernet-phy-ieee802.3-c45\";\n\t\treg = <2>;\n\t};\n\tcp0_nbaset_phy1: ethernet-phy@1 {\n\t\tcompatible = \"ethernet-phy-ieee802.3-c45\";\n\t\treg = <0>;\n\t};\n\tcp0_nbaset_phy2: ethernet-phy@2 {\n\t\tcompatible = \"ethernet-phy-ieee802.3-c45\";\n\t\treg = <8>;\n\t};\n};\n\n&cp0_ethernet {\n\tstatus = \"okay\";\n};\n\n/* SLM-1521-V2, CON9 */\n&cp0_eth0 {\n\tstatus = \"okay\";\n\tphy-mode = \"2500base-x\";\n\tphys = <&cp0_comphy2 0>;\n\tphy = <&cp0_nbaset_phy0>;\n};\n\n&cp0_eth1 {\n\tstatus = \"okay\";\n\tphy-mode = \"2500base-x\";\n\tphys = <&cp0_comphy4 1>;\n\tphy = <&cp0_nbaset_phy1>;\n};\n\n&cp0_eth2 {\n\tstatus = \"okay\";\n\tphy-mode = \"2500base-x\";\n\tphys = <&cp0_comphy5 2>;\n\tphy = <&cp0_nbaset_phy2>;\n};\n\n&cp0_gpio1 {\n\tstatus = \"okay\";\n};\n\n&cp0_gpio2 {\n\tstatus = \"okay\";\n};\n\n&cp0_i2c0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&cp0_i2c0_pins>;\n\tstatus = \"okay\";\n\tclock-frequency = <100000>;\n\trtc@32 {\n\t\tcompatible = \"epson,rx8130\";\n\t\treg = <0x32>;\n\t\twakeup-source;\n\t};\n};\n\n/* SLM-1521-V2, CON6 */\n&cp0_pcie0 {\n\tstatus = \"okay\";\n\tnum-lanes = <2>;\n\tnum-viewport = <8>;\n\tphys = <&cp0_comphy0 0>, <&cp0_comphy1 0>;\n};\n\n/* U55 */\n&cp0_spi1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&cp0_spi0_pins>;\n\treg = <0x700680 0x50>,          /* control */\n\t      <0x2000000 0x1000000>;    /* CS0 */\n\tstatus = \"okay\";\n\tspi-flash@0 {\n\t\t#address-cells = <0x1>;\n\t\t#size-cells = <0x1>;\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0x0>;\n\t\tspi-max-frequency = <40000000>;\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"U-Boot\";\n\t\t\t\treg = <0x0 0x1f0000>;\n\t\t\t};\n\t\t\tpartition@1f0000 {\n\t\t\t\tlabel = \"U-Boot ENV Factory\";\n\t\t\t\treg = <0x1f0000 0x10000>;\n\t\t\t};\n\t\t\tpartition@200000 {\n\t\t\t\tlabel = \"Reserved\";\n\t\t\t\treg = <0x200000 0x1f0000>;\n\t\t\t};\n\t\t\tpartition@3f0000 {\n\t\t\t\tlabel = \"U-Boot ENV\";\n\t\t\t\treg = <0x3f0000 0x10000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&cp0_syscon0 {\n\tcp0_pinctrl: pinctrl {\n\t\tcompatible = \"marvell,cp115-standalone-pinctrl\";\n\t\tcp0_i2c0_pins: cp0-i2c-pins-0 {\n\t\t\tmarvell,pins = \"mpp37\", \"mpp38\";\n\t\t\tmarvell,function = \"i2c0\";\n\t\t};\n\t\tcp0_i2c1_pins: cp0-i2c-pins-1 {\n\t\t\tmarvell,pins = \"mpp35\", \"mpp36\";\n\t\t\tmarvell,function = \"i2c1\";\n\t\t};\n\t\tcp0_ge1_rgmii_pins: cp0-ge-rgmii-pins-0 {\n\t\t\tmarvell,pins = \"mpp0\", \"mpp1\", \"mpp2\",\n\t\t\t\t       \"mpp3\", \"mpp4\", \"mpp5\",\n\t\t\t\t       \"mpp6\", \"mpp7\", \"mpp8\",\n\t\t\t\t       \"mpp9\", \"mpp10\", \"mpp11\";\n\t\t\tmarvell,function = \"ge0\";\n\t\t};\n\t\tcp0_ge2_rgmii_pins: cp0-ge-rgmii-pins-1 {\n\t\t\tmarvell,pins = \"mpp44\", \"mpp45\", \"mpp46\",\n\t\t\t\t       \"mpp47\", \"mpp48\", \"mpp49\",\n\t\t\t\t       \"mpp50\", \"mpp51\", \"mpp52\",\n\t\t\t\t       \"mpp53\", \"mpp54\", \"mpp55\";\n\t\t\tmarvell,function = \"ge1\";\n\t\t};\n\t\tcp0_spi0_pins: cp0-spi-pins-0 {\n\t\t\tmarvell,pins = \"mpp13\", \"mpp14\", \"mpp15\", \"mpp16\";\n\t\t\tmarvell,function = \"spi1\";\n\t\t};\n\t};\n};\n\n/*\n * Instantiate the first connected CP115\n */\n\n#define CP11X_NAME\t\tcp1\n#define CP11X_BASE\t\tf6000000\n#define CP11X_PCIEx_MEM_BASE(iface) (0xe2000000 + (iface * 0x1000000))\n#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000\n#define CP11X_PCIE0_BASE\tf6600000\n#define CP11X_PCIE1_BASE\tf6620000\n#define CP11X_PCIE2_BASE\tf6640000\n\n#include \"armada-cp115.dtsi\"\n\n#undef CP11X_NAME\n#undef CP11X_BASE\n#undef CP11X_PCIEx_MEM_BASE\n#undef CP11X_PCIEx_MEM_SIZE\n#undef CP11X_PCIE0_BASE\n#undef CP11X_PCIE1_BASE\n#undef CP11X_PCIE2_BASE\n\n&cp1_crypto {\n\tstatus = \"okay\";\n};\n\n&cp1_xmdio {\n\tstatus = \"okay\";\n\tcp1_nbaset_phy0: ethernet-phy@3 {\n\t\tcompatible = \"ethernet-phy-ieee802.3-c45\";\n\t\treg = <2>;\n\t};\n\tcp1_nbaset_phy1: ethernet-phy@4 {\n\t\tcompatible = \"ethernet-phy-ieee802.3-c45\";\n\t\treg = <0>;\n\t};\n\tcp1_nbaset_phy2: ethernet-phy@5 {\n\t\tcompatible = \"ethernet-phy-ieee802.3-c45\";\n\t\treg = <8>;\n\t};\n};\n\n&cp1_ethernet {\n\tstatus = \"okay\";\n};\n\n/* CON50 */\n&cp1_eth0 {\n\tstatus = \"okay\";\n\tphy-mode = \"2500base-x\";\n\tphys = <&cp1_comphy2 0>;\n\tphy = <&cp1_nbaset_phy0>;\n};\n\n&cp1_eth1 {\n\tstatus = \"okay\";\n\tphy-mode = \"2500base-x\";\n\tphys = <&cp1_comphy4 1>;\n\tphy = <&cp1_nbaset_phy1>;\n};\n\n&cp1_eth2 {\n\tstatus = \"okay\";\n\tphy-mode = \"2500base-x\";\n\tphys = <&cp1_comphy5 2>;\n\tphy = <&cp1_nbaset_phy2>;\n};\n\n&cp1_sata0 {\n\tstatus = \"okay\";\n\tsata-port@1 {\n\t\tstatus = \"okay\";\n\t\tphys = <&cp1_comphy0 1>;\n\t};\n};\n\n&cp1_gpio1 {\n\tstatus = \"okay\";\n};\n\n&cp1_gpio2 {\n\tstatus = \"okay\";\n};\n\n&cp1_i2c0 {\n\tstatus = \"okay\";\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&cp1_i2c0_pins>;\n\tclock-frequency = <100000>;\n};\n\n&cp1_syscon0 {\n\tcp1_pinctrl: pinctrl {\n\t\tcompatible = \"marvell,cp115-standalone-pinctrl\";\n\t\tcp1_i2c0_pins: cp1-i2c-pins-0 {\n\t\t\tmarvell,pins = \"mpp37\", \"mpp38\";\n\t\t\tmarvell,function = \"i2c0\";\n\t\t};\n\t\tcp1_spi0_pins: cp1-spi-pins-0 {\n\t\t\tmarvell,pins = \"mpp13\", \"mpp14\", \"mpp15\", \"mpp16\";\n\t\t\tmarvell,function = \"spi1\";\n\t\t};\n\t\tcp1_xhci0_vbus_pins: cp1-xhci0-vbus-pins {\n\t\t\tmarvell,pins = \"mpp3\";\n\t\t\tmarvell,function = \"gpio\";\n\t\t};\n\t\tcp1_sfp_pins: sfp-pins {\n\t\t\tmarvell,pins = \"mpp8\", \"mpp9\", \"mpp10\", \"mpp11\";\n\t\t\tmarvell,function = \"gpio\";\n\t\t};\n\t};\n};\n\n&cp1_usb3_1 {\n\tstatus = \"okay\";\n\tphys = <&cp1_comphy3 1>;\n\tphy-names = \"usb\";\n};\n"
  },
  {
    "path": "target/linux/mvebu/files/arch/arm64/boot/dts/marvell/cn9132-puzzle-m902.dts",
    "content": "// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)\n/*\n * Copyright (C) 2019 Marvell International Ltd.\n *\n * Device tree for the CN9132-DB board.\n */\n\n#include \"cn9130.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"iEi Puzzle-M902\";\n\tcompatible = \"iei,puzzle-m902\",\n\t\t     \"marvell,armada-ap807-quad\", \"marvell,armada-ap807\";\n\n\tchosen {\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\taliases {\n\t\ti2c0 = &cp1_i2c0;\n\t\ti2c1 = &cp0_i2c0;\n\t\tgpio1 = &cp0_gpio1;\n\t\tgpio2 = &cp0_gpio2;\n\t\tgpio3 = &cp1_gpio1;\n\t\tgpio4 = &cp1_gpio2;\n\t\tgpio5 = &cp2_gpio1;\n\t\tgpio6 = &cp2_gpio2;\n\t\tethernet0 = &cp0_eth0;\n\t\tethernet1 = &cp0_eth1;\n\t\tethernet2 = &cp0_eth2;\n\t\tethernet3 = &cp1_eth0;\n\t\tethernet4 = &cp1_eth1;\n\t\tethernet5 = &cp1_eth2;\n\t\tethernet6 = &cp2_eth0;\n\t\tethernet7 = &cp2_eth1;\n\t\tethernet8 = &cp2_eth2;\n\t\tspi1 = &cp0_spi0;\n\t\tspi2 = &cp0_spi1;\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_info;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_info;\n\t};\n\n\tmemory@00000000 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x0 0x0 0x0 0x80000000>;\n\t};\n\n\tgpio_keys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"Reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&cp0_gpio2 4 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tcp2_reg_usb3_vbus0: cp2_usb3_vbus@0 {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"cp2-xhci0-vbus\";\n\t\tregulator-min-microvolt = <5000000>;\n\t\tregulator-max-microvolt = <5000000>;\n\t\tenable-active-high;\n\t\tgpio = <&cp2_gpio1 2 GPIO_ACTIVE_HIGH>;\n\t};\n\n\tcp2_usb3_0_phy0: cp2_usb3_phy0 {\n\t\tcompatible = \"usb-nop-xceiv\";\n\t\tvcc-supply = <&cp2_reg_usb3_vbus0>;\n\t};\n\n\tcp2_reg_usb3_vbus1: cp2_usb3_vbus@1 {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"cp2-xhci1-vbus\";\n\t\tregulator-min-microvolt = <5000000>;\n\t\tregulator-max-microvolt = <5000000>;\n\t\tenable-active-high;\n\t\tgpio = <&cp2_gpio1 3 GPIO_ACTIVE_HIGH>;\n\t};\n\n\tcp2_usb3_0_phy1: cp2_usb3_phy1 {\n\t\tcompatible = \"usb-nop-xceiv\";\n\t\tvcc-supply = <&cp2_reg_usb3_vbus1>;\n\t};\n\n\tcp2_sfp_eth0: sfp-eth0 {\n\t\tcompatible = \"sff,sfp\";\n\t\ti2c-bus = <&cp2_sfpp0_i2c>;\n\t\tlos-gpio = <&cp2_module_expander1 11 GPIO_ACTIVE_HIGH>;\n\t\tmod-def0-gpio = <&cp2_module_expander1 10 GPIO_ACTIVE_LOW>;\n\t\ttx-disable-gpio = <&cp2_module_expander1 9 GPIO_ACTIVE_HIGH>;\n\t\ttx-fault-gpio = <&cp2_module_expander1 8 GPIO_ACTIVE_HIGH>;\n\t\tstatus = \"disabled\";\n\t};\n};\n\n&uart0 {\n\tstatus = \"okay\";\n};\n\n&cp0_uart0 {\n\tstatus = \"okay\";\n\n\tpuzzle-mcu {\n\t\tcompatible = \"iei,wt61p803-puzzle\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcurrent-speed = <115200>;\n\t\tenable-beep;\n\t\tstatus = \"okay\";\n\n\t\tleds {\n\t\t\tcompatible = \"iei,wt61p803-puzzle-leds\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tstatus = \"okay\";\n\n\t\t\tled@0 {\n\t\t\t\treg = <0>;\n\t\t\t\tlabel = \"white:network\";\n\t\t\t\tactive-low;\n\t\t\t};\n\n\t\t\tled@1 {\n\t\t\t\treg = <1>;\n\t\t\t\tlabel = \"green:cloud\";\n\t\t\t\tactive-low;\n\t\t\t};\n\n\t\t\tled_info: led@2 {\n\t\t\t\treg = <2>;\n\t\t\t\tlabel = \"orange:info\";\n\t\t\t\tactive-low;\n\t\t\t};\n\n\t\t\tled_power: led@3 {\n\t\t\t\treg = <3>;\n\t\t\t\tlabel = \"yellow:power\";\n\t\t\t\tactive-low;\n\t\t\t\tdefault-state = \"on\";\n\t\t\t};\n\t\t};\n\n\t\thwmon {\n\t\t\tcompatible = \"iei,wt61p803-puzzle-hwmon\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\n\t\t\tchassis_fan_group0: fan-group@0 {\n\t\t\t\t#cooling-cells = <2>;\n\t\t\t\treg = <0x00>;\n\t\t\t\tcooling-levels = <64 102 170 230 250>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&ap_thermal_cpu1 {\n\ttrips {\n\t\tcpu_active: cpu-active {\n\t\t\ttemperature = <44000>;\n\t\t\thysteresis = <2000>;\n\t\t\ttype = \"active\";\n\t\t};\n\t};\n\tcooling-maps {\n\t\tfan-map {\n\t\t\ttrip = <&cpu_active>;\n\t\t\tcooling-device = <&chassis_fan_group0 64 THERMAL_NO_LIMIT>;\n\t\t};\n\t};\n};\n\n/* on-board eMMC - U9 */\n&ap_sdhci0 {\n\tpinctrl-names = \"default\";\n\tbus-width = <8>;\n\tstatus = \"okay\";\n\tmmc-ddr-1_8v;\n\tmmc-hs400-1_8v;\n};\n\n&cp0_crypto {\n\tstatus = \"okay\";\n};\n\n&cp0_xmdio {\n\tstatus = \"okay\";\n\tcp0_nbaset_phy0: ethernet-phy@0 {\n\t\tcompatible = \"ethernet-phy-ieee802.3-c45\";\n\t\treg = <2>;\n\t};\n\tcp0_nbaset_phy1: ethernet-phy@1 {\n\t\tcompatible = \"ethernet-phy-ieee802.3-c45\";\n\t\treg = <0>;\n\t};\n\tcp0_nbaset_phy2: ethernet-phy@2 {\n\t\tcompatible = \"ethernet-phy-ieee802.3-c45\";\n\t\treg = <8>;\n\t};\n};\n\n&cp0_ethernet {\n\tstatus = \"okay\";\n};\n\n/* SLM-1521-V2, CON9 */\n&cp0_eth0 {\n\tstatus = \"okay\";\n\tphy-mode = \"10gbase-kr\";\n\tphys = <&cp0_comphy2 0>;\n\tphy = <&cp0_nbaset_phy0>;\n};\n\n&cp0_eth1 {\n\tstatus = \"okay\";\n\tphy-mode = \"2500base-x\";\n\tphys = <&cp0_comphy4 1>;\n\tphy = <&cp0_nbaset_phy1>;\n};\n\n&cp0_eth2 {\n\tstatus = \"okay\";\n\tphy-mode = \"2500base-x\";\n\tphys = <&cp0_comphy1 2>;\n\tphy = <&cp0_nbaset_phy2>;\n};\n\n&cp0_gpio1 {\n\tstatus = \"okay\";\n};\n\n&cp0_gpio2 {\n\tstatus = \"okay\";\n};\n\n&cp0_i2c0 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&cp0_i2c0_pins>;\n\tstatus = \"okay\";\n\tclock-frequency = <100000>;\n\trtc@32 {\n\t\tcompatible = \"epson,rx8130\";\n\t\treg = <0x32>;\n\t\twakeup-source;\n\t};\n};\n\n&cp0_i2c1 {\n\tclock-frequency = <100000>;\n};\n\n/* SLM-1521-V2, CON6 */\n&cp0_sata0 {\n\tstatus = \"okay\";\n\tsata-port@1 {\n\t\tstatus = \"okay\";\n\t\tphys = <&cp0_comphy0 1>;\n\t};\n};\n\n&cp0_pcie2 {\n\tstatus = \"okay\";\n\tnum-lanes = <1>;\n\tnum-viewport = <8>;\n\tphys = <&cp0_comphy5 2>;\n};\n\n/* U55 */\n&cp0_spi1 {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&cp0_spi0_pins>;\n\treg = <0x700680 0x50>,          /* control */\n\t      <0x2000000 0x1000000>;    /* CS0 */\n\tstatus = \"okay\";\n\tspi-flash@0 {\n\t\t#address-cells = <0x1>;\n\t\t#size-cells = <0x1>;\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0x0>;\n\t\tspi-max-frequency = <40000000>;\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"U-Boot\";\n\t\t\t\treg = <0x0 0x1f0000>;\n\t\t\t};\n\t\t\tpartition@1f0000 {\n\t\t\t\tlabel = \"U-Boot ENV Factory\";\n\t\t\t\treg = <0x1f0000 0x10000>;\n\t\t\t};\n\t\t\tpartition@200000 {\n\t\t\t\tlabel = \"Reserved\";\n\t\t\t\treg = <0x200000 0x1f0000>;\n\t\t\t};\n\t\t\tpartition@3f0000 {\n\t\t\t\tlabel = \"U-Boot ENV\";\n\t\t\t\treg = <0x3f0000 0x10000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&cp0_syscon0 {\n\tcp0_pinctrl: pinctrl {\n\t\tcompatible = \"marvell,cp115-standalone-pinctrl\";\n\t\tcp0_i2c0_pins: cp0-i2c-pins-0 {\n\t\t\tmarvell,pins = \"mpp37\", \"mpp38\";\n\t\t\tmarvell,function = \"i2c0\";\n\t\t};\n\t\tcp0_i2c1_pins: cp0-i2c-pins-1 {\n\t\t\tmarvell,pins = \"mpp35\", \"mpp36\";\n\t\t\tmarvell,function = \"i2c1\";\n\t\t};\n\t\tcp0_ge1_rgmii_pins: cp0-ge-rgmii-pins-0 {\n\t\t\tmarvell,pins = \"mpp0\", \"mpp1\", \"mpp2\",\n\t\t\t\t       \"mpp3\", \"mpp4\", \"mpp5\",\n\t\t\t\t       \"mpp6\", \"mpp7\", \"mpp8\",\n\t\t\t\t       \"mpp9\", \"mpp10\", \"mpp11\";\n\t\t\tmarvell,function = \"ge0\";\n\t\t};\n\t\tcp0_ge2_rgmii_pins: cp0-ge-rgmii-pins-1 {\n\t\t\tmarvell,pins = \"mpp44\", \"mpp45\", \"mpp46\",\n\t\t\t\t       \"mpp47\", \"mpp48\", \"mpp49\",\n\t\t\t\t       \"mpp50\", \"mpp51\", \"mpp52\",\n\t\t\t\t       \"mpp53\", \"mpp54\", \"mpp55\";\n\t\t\tmarvell,function = \"ge1\";\n\t\t};\n\t\tcp0_spi0_pins: cp0-spi-pins-0 {\n\t\t\tmarvell,pins = \"mpp13\", \"mpp14\", \"mpp15\", \"mpp16\";\n\t\t\tmarvell,function = \"spi1\";\n\t\t};\n\t};\n};\n\n&cp0_usb3_1 {\n\tstatus = \"okay\";\n\tphys = <&cp0_comphy3 1>;\n\tphy-names = \"usb\";\n};\n\n/*\n * Instantiate the first connected CP115\n */\n\n#define CP11X_NAME\t\tcp1\n#define CP11X_BASE\t\tf4000000\n#define CP11X_PCIEx_MEM_BASE(iface) (0xe2000000 + (iface * 0x1000000))\n#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000\n#define CP11X_PCIE0_BASE\tf4600000\n#define CP11X_PCIE1_BASE\tf4620000\n#define CP11X_PCIE2_BASE\tf4640000\n\n#include \"armada-cp115.dtsi\"\n\n#undef CP11X_NAME\n#undef CP11X_BASE\n#undef CP11X_PCIEx_MEM_BASE\n#undef CP11X_PCIEx_MEM_SIZE\n#undef CP11X_PCIE0_BASE\n#undef CP11X_PCIE1_BASE\n#undef CP11X_PCIE2_BASE\n\n&cp1_crypto {\n\tstatus = \"okay\";\n};\n\n&cp1_xmdio {\n\tstatus = \"okay\";\n\tcp1_nbaset_phy0: ethernet-phy@3 {\n\t\tcompatible = \"ethernet-phy-ieee802.3-c45\";\n\t\treg = <2>;\n\t};\n\tcp1_nbaset_phy1: ethernet-phy@4 {\n\t\tcompatible = \"ethernet-phy-ieee802.3-c45\";\n\t\treg = <0>;\n\t};\n\tcp1_nbaset_phy2: ethernet-phy@5 {\n\t\tcompatible = \"ethernet-phy-ieee802.3-c45\";\n\t\treg = <8>;\n\t};\n};\n\n&cp1_ethernet {\n\tstatus = \"okay\";\n};\n\n/* CON50 */\n&cp1_eth0 {\n\tstatus = \"okay\";\n\tphy-mode = \"10gbase-kr\";\n\tphys = <&cp1_comphy2 0>;\n\tphy = <&cp1_nbaset_phy0>;\n};\n\n&cp1_eth1 {\n\tstatus = \"okay\";\n\tphy-mode = \"2500base-x\";\n\tphys = <&cp1_comphy4 1>;\n\tphy = <&cp1_nbaset_phy1>;\n};\n\n&cp1_eth2 {\n\tstatus = \"okay\";\n\tphy-mode = \"2500base-x\";\n\tphys = <&cp1_comphy1 2>;\n\tphy = <&cp1_nbaset_phy2>;\n};\n\n&cp1_gpio1 {\n\tstatus = \"okay\";\n};\n\n&cp1_gpio2 {\n\tstatus = \"okay\";\n};\n\n&cp1_i2c0 {\n\tstatus = \"okay\";\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&cp1_i2c0_pins>;\n\tclock-frequency = <100000>;\n};\n\n&cp1_syscon0 {\n\tcp1_pinctrl: pinctrl {\n\t\tcompatible = \"marvell,cp115-standalone-pinctrl\";\n\t\tcp1_i2c0_pins: cp1-i2c-pins-0 {\n\t\t\tmarvell,pins = \"mpp37\", \"mpp38\";\n\t\t\tmarvell,function = \"i2c0\";\n\t\t};\n\t\tcp1_spi0_pins: cp1-spi-pins-0 {\n\t\t\tmarvell,pins = \"mpp13\", \"mpp14\", \"mpp15\", \"mpp16\";\n\t\t\tmarvell,function = \"spi1\";\n\t\t};\n\t\tcp1_xhci0_vbus_pins: cp1-xhci0-vbus-pins {\n\t\t\tmarvell,pins = \"mpp3\";\n\t\t\tmarvell,function = \"gpio\";\n\t\t};\n\t};\n};\n\n/*\n * Instantiate the second connected CP115\n */\n\n#define CP11X_NAME\t\tcp2\n#define CP11X_BASE\t\tf6000000\n#define CP11X_PCIEx_MEM_BASE(iface) (0xe5000000 + (iface * 0x1000000))\n#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000\n#define CP11X_PCIE0_BASE\tf6600000\n#define CP11X_PCIE1_BASE\tf6620000\n#define CP11X_PCIE2_BASE\tf6640000\n\n#include \"armada-cp115.dtsi\"\n\n#undef CP11X_NAME\n#undef CP11X_BASE\n#undef CP11X_PCIEx_MEM_BASE\n#undef CP11X_PCIEx_MEM_SIZE\n#undef CP11X_PCIE0_BASE\n#undef CP11X_PCIE1_BASE\n#undef CP11X_PCIE2_BASE\n\n&cp2_crypto {\n\tstatus = \"okay\";\n};\n\n&cp2_ethernet {\n\tstatus = \"okay\";\n};\n\n&cp2_xmdio {\n\tstatus = \"okay\";\n\tcp2_nbaset_phy0: ethernet-phy@6 {\n\t\tcompatible = \"ethernet-phy-ieee802.3-c45\";\n\t\treg = <2>;\n\t};\n\tcp2_nbaset_phy1: ethernet-phy@7 {\n\t\tcompatible = \"ethernet-phy-ieee802.3-c45\";\n\t\treg = <0>;\n\t};\n\tcp2_nbaset_phy2: ethernet-phy@8 {\n\t\tcompatible = \"ethernet-phy-ieee802.3-c45\";\n\t\treg = <8>;\n\t};\n};\n\n/* SLM-1521-V2, CON9 */\n&cp2_eth0 {\n\tstatus = \"okay\";\n\tphy-mode = \"10gbase-kr\";\n\tphys = <&cp2_comphy2 0>;\n\tphy = <&cp2_nbaset_phy0>;\n};\n\n&cp2_eth1 {\n\tstatus = \"okay\";\n\tphy-mode = \"2500base-x\";\n\tphys = <&cp2_comphy4 1>;\n\tphy = <&cp2_nbaset_phy1>;\n};\n\n&cp2_eth2 {\n\tstatus = \"okay\";\n\tphy-mode = \"2500base-x\";\n\tphys = <&cp2_comphy1 2>;\n\tphy = <&cp2_nbaset_phy2>;\n};\n\n&cp2_gpio1 {\n\tstatus = \"okay\";\n};\n\n&cp2_gpio2 {\n\tstatus = \"okay\";\n};\n\n&cp2_i2c0 {\n\tclock-frequency = <100000>;\n\t/* SLM-1521-V2 - U3 */\n\ti2c-mux@72 {\n\t\tcompatible = \"nxp,pca9544\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x72>;\n\t\tcp2_sfpp0_i2c: i2c@0 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <0>;\n\t\t};\n\n\t\ti2c@1 {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\treg = <1>;\n\t\t\t/* U12 */\n\t\t\tcp2_module_expander1: pca9555@21 {\n\t\t\t\tcompatible = \"nxp,pca9555\";\n\t\t\t\tpinctrl-names = \"default\";\n\t\t\t\tgpio-controller;\n\t\t\t\t#gpio-cells = <2>;\n\t\t\t\treg = <0x21>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&cp2_syscon0 {\n\tcp2_pinctrl: pinctrl {\n\t\tcompatible = \"marvell,cp115-standalone-pinctrl\";\n\t\tcp2_i2c0_pins: cp2-i2c-pins-0 {\n\t\t\tmarvell,pins = \"mpp37\", \"mpp38\";\n\t\t\tmarvell,function = \"i2c0\";\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/mvebu/image/Makefile",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2012-2016 OpenWrt.org\n# Copyright (C) 2016 LEDE-project.org\n\nJFFS2_BLOCKSIZE = 128k\n\ninclude $(TOPDIR)/rules.mk\ninclude $(INCLUDE_DIR)/image.mk\n\nDEVICE_VARS += BOOT_SCRIPT UBOOT\nKERNEL_LOADADDR := 0x00008000\n\ndefine Build/boot-scr\n\trm -f $@-boot.scr\n\tsed \\\n\t\t-e 's#@ROOT@#$(IMG_PART_SIGNATURE)#g' \\\n\t\t-e 's#@DTB@#$(firstword $(DEVICE_DTS))#g' \\\n\t\t$(BOOT_SCRIPT).bootscript > $@-new.bootscript\n\tmkimage -A arm -O linux -T script -C none -a 0 -e 0 -d $@-new.bootscript $@-boot.scr\nendef\n\ndefine Build/boot-img\n\trm -f $@.boot\n\tmkfs.fat -C $@.boot $$(( $(CONFIG_TARGET_KERNEL_PARTSIZE) * 1024 ))\n\t$(foreach dts,$(DEVICE_DTS), mcopy -i $@.boot $(KDIR)/image-$(dts).dtb ::$(dts).dtb;)\n\tmcopy -i $@.boot $(IMAGE_KERNEL) ::$(KERNEL_NAME)\n\t-mcopy -i $@.boot $@-boot.scr ::boot.scr\nendef\n\ndefine Build/boot-img-ext4\n\trm -fR $@.boot\n\tmkdir -p $@.boot\n\t$(foreach dts,$(DEVICE_DTS), $(CP) $(KDIR)/image-$(dts).dtb $@.boot/$(dts).dtb;)\n\t$(CP) $(IMAGE_KERNEL) $@.boot/$(KERNEL_NAME)\n\t-$(CP) $@-boot.scr $@.boot/boot.scr\n\tmake_ext4fs -J -L kernel -l $(CONFIG_TARGET_KERNEL_PARTSIZE)M \\\n\t\t$(if $(SOURCE_DATE_EPOCH),-T $(SOURCE_DATE_EPOCH)) \\\n\t\t$@.bootimg $@.boot\nendef\n\ndefine Build/buffalo-kernel-jffs2\n\trm -rf $(KDIR)/kernel_jffs2 $@.fakerd\n\tmkdir -p $(KDIR)/kernel_jffs2\n\tdd if=/dev/zero of=$@.fakerd bs=131008 count=1 conv=sync\n\t$(STAGING_DIR_HOST)/bin/mkimage \\\n\t\t-T ramdisk -A $(LINUX_KARCH) -O linux -C gzip -n 'fake initrd' \\\n\t\t-d $@.fakerd $(KDIR)/kernel_jffs2/initrd.buffalo\n\tcp $@ $(KDIR)/kernel_jffs2/uImage.buffalo\n\t$(STAGING_DIR_HOST)/bin/mkfs.jffs2 \\\n\t\t--little-endian -v --squash-uids -q -f -n -x lzma -x rtime -m none \\\n\t\t--eraseblock=128KiB --pad=$(KERNEL_SIZE) -d $(KDIR)/kernel_jffs2 -o $@\n\trm -rf $(KDIR)/kernel_jffs2 $@.fakerd\nendef\n\n# Some info about Ctera firmware:\n# 1. It's simple tar file (GNU standard), but it must have \".firm\" suffix.\n# 2. It contains two images: kernel and romdisk. Both are required.\n# 3. Every image has header and trailer file.\n# 4. The struct of tar firmware is: header kernel trailer header romdisk trailer\n# 5. In header file are some strings used to describe image. It was decoded from\n#    factory image.\n# 6. Version format in header file is restricted by Original FW.\n# 7. Trailer file contains MD5 sum string of header and image file.\n# 8. Firmware file must have <=24MB size.\n\ndefine Build/ctera-firmware\n\tmkdir -p $@.tmp\n\n\t# Prepare header and trailer file for kernel\n\techo \"# CTera firmware information file\" > $@.tmp/header\n\techo \"image_type=kernel\" >> $@.tmp/header\n\techo \"arch=ARM\" >> $@.tmp/header\n\techo \"board=2Drive_A\" >> $@.tmp/header\n\techo \"version=5.5.165.61499\" >> $@.tmp/header\n\techo \"kernel_cmd=console=ttyS0,115200 earlycon\" >> $@.tmp/header\n\techo \"date=$$(date $(if $(SOURCE_DATE_EPOCH),-d@$(SOURCE_DATE_EPOCH)))\" \\\n\t\t>> $@.tmp/header\n\n\tcp $@ $@.tmp/kernel\n\n\techo \"MD5=$$(cat $@.tmp/header $@.tmp/kernel | $(MKHASH) md5)\" \\\n\t\t> $@.tmp/trailer\n\n\ttar $(if $(SOURCE_DATE_EPOCH),--mtime=\"@$(SOURCE_DATE_EPOCH)\") \\\n\t\t-H gnu -C $@.tmp -cf $@.tar header kernel trailer\n\n\t# Prepare header and trailer file for fake romdisk\n\techo \"# CTera firmware information file\" > $@.tmp/header\n\techo \"image_type=romdisk\" >> $@.tmp/header\n\techo \"initrd=yes\" >> $@.tmp/header\n\techo \"arch=ARM\" >> $@.tmp/header\n\techo \"board=2Drive_A\" >> $@.tmp/header\n\techo \"version=5.5.165.61499\" >> $@.tmp/header\n\techo \"date=$$(date $(if $(SOURCE_DATE_EPOCH),-d@$(SOURCE_DATE_EPOCH)))\" \\\n\t\t>> $@.tmp/header\n\n\trm -f $@\n\ttouch $@\n\t$(call Build/append-uImage-fakehdr, ramdisk)\n\tcp $@ $@.tmp/romdisk\n\n\techo \"MD5=$$(cat $@.tmp/header $@.tmp/romdisk | $(MKHASH) md5)\" \\\n\t\t> $@.tmp/trailer\n\n\ttar $(if $(SOURCE_DATE_EPOCH),--mtime=\"@$(SOURCE_DATE_EPOCH)\") \\\n\t\t-H gnu -C $@.tmp -rf $@.tar header romdisk trailer\n\n\tmv $@.tar $@\n\trm -rf $@.tmp\nendef\n\ndefine Build/sdcard-img\n\tSIGNATURE=\"$(IMG_PART_SIGNATURE)\" \\\n\t./gen_mvebu_sdcard_img.sh $@ \\\n\t\t$(if $(UBOOT),$(STAGING_DIR_IMAGE)/$(UBOOT)) \\\n\t\tc $(CONFIG_TARGET_KERNEL_PARTSIZE) $@.boot \\\n\t\t83 $(CONFIG_TARGET_ROOTFS_PARTSIZE) $(IMAGE_ROOTFS)\nendef\n\ndefine Build/sdcard-img-ext4\n\tSIGNATURE=\"$(IMG_PART_SIGNATURE)\" \\\n\t./gen_mvebu_sdcard_img.sh $@ \\\n\t\t$(if $(UBOOT),$(STAGING_DIR_IMAGE)/$(UBOOT)) \\\n\t\t83 $(CONFIG_TARGET_KERNEL_PARTSIZE) $@.bootimg \\\n\t\t83 $(CONFIG_TARGET_ROOTFS_PARTSIZE) $(IMAGE_ROOTFS)\nendef\n\ndefine Build/omnia-medkit-initramfs\n\t$(TAR) -c -T /dev/null -f $@\n\trm -rf $(dir $(IMAGE_KERNEL))boot\n\tmkdir -p $(dir $(IMAGE_KERNEL))boot/boot/\n\tcp $(KDIR)/zImage-initramfs $(dir $(IMAGE_KERNEL))boot/boot/zImage\n\tcp $(KDIR)/image-$(DEVICE_DTS).dtb $(dir $(IMAGE_KERNEL))boot/boot/dtb\n\t$(TAR) -rp --numeric-owner --owner=0 --group=0 --sort=name \\\n\t\t$(if $(SOURCE_DATE_EPOCH),--mtime=\"@$(SOURCE_DATE_EPOCH)\") \\\n\t\t--file=$@ -C $(dir $(IMAGE_KERNEL))boot/ .\nendef\n\ndefine Build/uDPU-firmware\n\t(rm -fR $@-fw; mkdir -p $@-fw)\n\t$(CP) $(BIN_DIR)/$(DEVICE_IMG_PREFIX)-initramfs.itb $@-fw/recovery.itb\n\t$(CP) $@-boot.scr $@-fw/boot.scr\n\t$(TAR) -cvzp --numeric-owner --owner=0 --group=0 --sort=name \\\n\t\t$(if $(SOURCE_DATE_EPOCH),--mtime=\"@$(SOURCE_DATE_EPOCH)\") \\\n\t\t-f $@-fw/rootfs.tgz -C $(TARGET_DIR) .\n\t$(TAR) -cvzp --numeric-owner --owner=0 --group=0 --sort=name \\\n\t\t$(if $(SOURCE_DATE_EPOCH),--mtime=\"@$(SOURCE_DATE_EPOCH)\") \\\n\t\t-f $@-fw/boot.tgz -C $@.boot .\n\t$(TAR) -cvzp --numeric-owner --owner=0 --group=0 --sort=name \\\n\t\t$(if $(SOURCE_DATE_EPOCH),--mtime=\"@$(SOURCE_DATE_EPOCH)\") \\\n\t\t-f $(KDIR_TMP)/$(DEVICE_IMG_PREFIX)-firmware.tgz -C $@-fw .\nendef\n\ndefine Device/Default\n  PROFILES := Default\n  DEVICE_DTS = $$(SOC)-$(lastword $(subst _, ,$(1)))\n  DEVICE_DTS_DIR := $(DTS_DIR)\n  BOARD_NAME = $$(DEVICE_DTS)\n  KERNEL_NAME := zImage\n  KERNEL := kernel-bin | append-dtb | uImage none\n  IMAGES := sysupgrade.bin\n  IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata\n  UBINIZE_OPTS := -E 5\n  UBOOT :=\n  BOOT_SCRIPT :=\nendef\n\ndefine Device/Default-arm64\n  BOOT_SCRIPT := generic-arm64\n  DEVICE_DTS_DIR := $(DTS_DIR)/marvell\n  IMAGES := sdcard.img.gz\n  IMAGE/sdcard.img.gz := boot-scr | boot-img-ext4 | sdcard-img-ext4 | gzip | append-metadata\n  KERNEL_NAME := Image\n  KERNEL := kernel-bin\nendef\n\ndefine Device/NAND-128K\n  BLOCKSIZE := 128k\n  PAGESIZE := 2048\n  SUBPAGESIZE := 512\n  VID_HDR_OFFSET := 2048\nendef\n\ndefine Device/NAND-256K\n  BLOCKSIZE := 256k\n  PAGESIZE := 4096\nendef\n\ndefine Device/NAND-512K\n  BLOCKSIZE := 512k\n  PAGESIZE := 4096\nendef\n\ninclude $(SUBTARGET).mk\n\n$(eval $(call BuildImage))\n"
  },
  {
    "path": "target/linux/mvebu/image/clearfog.bootscript",
    "content": "# Standard Boot-Script\n# use only well-known variable names provided by U-Boot Distro boot\n# This script assumes that there is a boot partition,\n# and that the root partition is always the next one.\n\n# rootfs is always on the next partition\nsetexpr openwrt_rootpart ${distro_bootpart} + 1\n\n# figure out partition uuid to pass to the kernel as root=\npart uuid ${devtype} ${devnum}:${openwrt_rootpart} uuid\n\n# generate bootargs (rootfs)\nsetenv bootargs ${bootargs} root=PARTUUID=${uuid} rootfstype=auto rootwait\n\n# add console= option to bootargs, if any\nif test -n \"${console}\"; then\n\tsetenv bootargs ${bootargs} console=${console}\nfi\n\necho \"Booting Linux with ${bootargs}\"\nload ${devtype} ${devnum}:${distro_bootpart} ${fdt_addr_r} @DTB@.dtb\nload ${devtype} ${devnum}:${distro_bootpart} ${kernel_addr_r} zImage\nbootz ${kernel_addr_r} - ${fdt_addr_r}\n"
  },
  {
    "path": "target/linux/mvebu/image/cortexa53.mk",
    "content": "define Device/glinet_gl-mv1000\n  $(call Device/Default-arm64)\n  DEVICE_VENDOR := GL.iNet\n  DEVICE_MODEL := GL-MV1000\n  SOC := armada-3720\nendef\nTARGET_DEVICES += glinet_gl-mv1000\n\ndefine Device/globalscale_espressobin\n  $(call Device/Default-arm64)\n  DEVICE_VENDOR := Marvell\n  DEVICE_MODEL := ESPRESSObin\n  DEVICE_VARIANT := Non-eMMC\n  DEVICE_ALT0_VENDOR := Marvell\n  DEVICE_ALT0_MODEL := Armada 3700 Community Board\n  DEVICE_ALT0_VARIANT := Non-eMMC\n  SOC := armada-3720\n  BOOT_SCRIPT := espressobin\nendef\nTARGET_DEVICES += globalscale_espressobin\n\ndefine Device/globalscale_espressobin-emmc\n  $(call Device/Default-arm64)\n  DEVICE_VENDOR := Marvell\n  DEVICE_MODEL := ESPRESSObin\n  DEVICE_VARIANT := eMMC\n  DEVICE_ALT0_VENDOR := Marvell\n  DEVICE_ALT0_MODEL := Armada 3700 Community Board\n  DEVICE_ALT0_VARIANT := eMMC\n  SOC := armada-3720\n  BOOT_SCRIPT := espressobin\nendef\nTARGET_DEVICES += globalscale_espressobin-emmc\n\ndefine Device/globalscale_espressobin-ultra\n  $(call Device/Default-arm64)\n  DEVICE_VENDOR := Marvell\n  DEVICE_MODEL := ESPRESSObin\n  DEVICE_VARIANT := Ultra\n  DEVICE_PACKAGES += kmod-i2c-pxa kmod-rtc-pcf8563\n  SOC := armada-3720\n  BOOT_SCRIPT := espressobin\nendef\nTARGET_DEVICES += globalscale_espressobin-ultra\n\ndefine Device/globalscale_espressobin-v7\n  $(call Device/Default-arm64)\n  DEVICE_VENDOR := Marvell\n  DEVICE_MODEL := ESPRESSObin\n  DEVICE_VARIANT := V7 Non-eMMC\n  DEVICE_ALT0_VENDOR := Marvell\n  DEVICE_ALT0_MODEL := Armada 3700 Community Board\n  DEVICE_ALT0_VARIANT := V7 Non-eMMC\n  SOC := armada-3720\n  BOOT_SCRIPT := espressobin\nendef\nTARGET_DEVICES += globalscale_espressobin-v7\n\ndefine Device/globalscale_espressobin-v7-emmc\n  $(call Device/Default-arm64)\n  DEVICE_VENDOR := Marvell\n  DEVICE_MODEL := ESPRESSObin\n  DEVICE_VARIANT := V7 eMMC\n  DEVICE_ALT0_VENDOR := Marvell\n  DEVICE_ALT0_MODEL := Armada 3700 Community Board\n  DEVICE_ALT0_VARIANT := V7 eMMC\n  SOC := armada-3720\n  BOOT_SCRIPT := espressobin\nendef\nTARGET_DEVICES += globalscale_espressobin-v7-emmc\n\ndefine Device/marvell_armada-3720-db\n  $(call Device/Default-arm64)\n  DEVICE_VENDOR := Marvell\n  DEVICE_MODEL := Armada 3720 Development Board (DB-88F3720-DDR3)\n  DEVICE_DTS := armada-3720-db\nendef\nTARGET_DEVICES += marvell_armada-3720-db\n\ndefine Device/methode_udpu\n  $(call Device/Default-arm64)\n  DEVICE_VENDOR := Methode\n  DEVICE_MODEL := micro-DPU (uDPU)\n  DEVICE_DTS := armada-3720-uDPU\n  KERNEL_LOADADDR := 0x00800000\n  KERNEL_INITRAMFS := kernel-bin | gzip | fit gzip $$(KDIR)/image-$$(DEVICE_DTS).dtb\n  KERNEL_INITRAMFS_SUFFIX := .itb\n  DEVICE_PACKAGES += f2fs-tools fdisk kmod-i2c-pxa kmod-hwmon-lm75\n  DEVICE_IMG_NAME = $$(DEVICE_IMG_PREFIX)-$$(2)\n  IMAGES := firmware.tgz\n  IMAGE/firmware.tgz := boot-scr | boot-img-ext4 | uDPU-firmware | append-metadata\n  BOOT_SCRIPT := udpu\nendef\nTARGET_DEVICES += methode_udpu\n"
  },
  {
    "path": "target/linux/mvebu/image/cortexa72.mk",
    "content": "define Device/globalscale_mochabin\n  $(call Device/Default-arm64)\n  DEVICE_VENDOR := Globalscale\n  DEVICE_MODEL := MOCHAbin\n  SOC := armada-7040\nendef\nTARGET_DEVICES += globalscale_mochabin\n\ndefine Device/marvell_armada7040-db\n  $(call Device/Default-arm64)\n  DEVICE_VENDOR := Marvell\n  DEVICE_MODEL := Armada 7040 Development Board\n  DEVICE_DTS := armada-7040-db\n  IMAGE/sdcard.img.gz := boot-img-ext4 | sdcard-img-ext4 | gzip | append-metadata\nendef\nTARGET_DEVICES += marvell_armada7040-db\n\ndefine Device/marvell_armada8040-db\n  $(call Device/Default-arm64)\n  DEVICE_VENDOR := Marvell\n  DEVICE_MODEL := Armada 8040 Development Board\n  DEVICE_DTS := armada-8040-db\n  IMAGE/sdcard.img.gz := boot-img-ext4 | sdcard-img-ext4 | gzip | append-metadata\nendef\nTARGET_DEVICES += marvell_armada8040-db\n\ndefine Device/marvell_macchiatobin-doubleshot\n  $(call Device/Default-arm64)\n  DEVICE_VENDOR := SolidRun\n  DEVICE_MODEL := MACCHIATObin\n  DEVICE_VARIANT := Double Shot\n  DEVICE_ALT0_VENDOR := SolidRun\n  DEVICE_ALT0_MODEL := Armada 8040 Community Board\n  DEVICE_ALT0_VARIANT := Double Shot\n  DEVICE_PACKAGES += kmod-i2c-mux-pca954x\n  DEVICE_DTS := armada-8040-mcbin\n  SUPPORTED_DEVICES := marvell,armada8040-mcbin-doubleshot marvell,armada8040-mcbin\nendef\nTARGET_DEVICES += marvell_macchiatobin-doubleshot\n\ndefine Device/marvell_macchiatobin-singleshot\n  $(call Device/Default-arm64)\n  DEVICE_VENDOR := SolidRun\n  DEVICE_MODEL := MACCHIATObin\n  DEVICE_VARIANT := Single Shot\n  DEVICE_ALT0_VENDOR := SolidRun\n  DEVICE_ALT0_MODEL := Armada 8040 Community Board\n  DEVICE_ALT0_VARIANT := Single Shot\n  DEVICE_PACKAGES += kmod-i2c-mux-pca954x\n  DEVICE_DTS := armada-8040-mcbin-singleshot\n  SUPPORTED_DEVICES := marvell,armada8040-mcbin-singleshot\nendef\nTARGET_DEVICES += marvell_macchiatobin-singleshot\n\ndefine Device/iei_puzzle-m901\n  $(call Device/Default-arm64)\n  DEVICE_VENDOR := iEi\n  DEVICE_MODEL := Puzzle-M901\n  SOC := cn9131\n  IMAGE/sdcard.img.gz := boot-img-ext4 | sdcard-img-ext4 | gzip | append-metadata\nendef\nTARGET_DEVICES += iei_puzzle-m901\n\ndefine Device/iei_puzzle-m902\n  $(call Device/Default-arm64)\n  DEVICE_VENDOR := iEi\n  DEVICE_MODEL := Puzzle-M902\n  SOC := cn9132\n  IMAGE/sdcard.img.gz := boot-img-ext4 | sdcard-img-ext4 | gzip | append-metadata\nendef\nTARGET_DEVICES += iei_puzzle-m902\n"
  },
  {
    "path": "target/linux/mvebu/image/cortexa9.mk",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2012-2016 OpenWrt.org\n# Copyright (C) 2016 LEDE-project.org\n\ndefine Device/dsa-migration\n  DEVICE_COMPAT_VERSION := 1.1\n  DEVICE_COMPAT_MESSAGE := Config cannot be migrated from swconfig to DSA\nendef\n\ndefine Device/kernel-size-migration\n  DEVICE_COMPAT_VERSION := 2.0\n  DEVICE_COMPAT_MESSAGE := Partition design has changed compared to older versions (up to 19.07) due to kernel size restrictions. \\\n\tUpgrade via sysupgrade mechanism is not possible, so new installation via factory style image is required.\nendef\n\ndefine Device/buffalo_ls421de\n  $(Device/NAND-128K)\n  DEVICE_VENDOR := Buffalo\n  DEVICE_MODEL := LinkStation LS421DE\n  SUBPAGESIZE :=\n  KERNEL_SIZE := 33554432\n  FILESYSTEMS := squashfs ubifs\n  KERNEL := kernel-bin | append-dtb | uImage none | buffalo-kernel-jffs2\n  KERNEL_INITRAMFS := kernel-bin | append-dtb | uImage none\n  DEVICE_DTS := armada-370-buffalo-ls421de\n  DEVICE_PACKAGES :=  \\\n    kmod-rtc-rs5c372a kmod-hwmon-gpiofan kmod-hwmon-drivetemp kmod-usb3 \\\n    kmod-linkstation-poweroff kmod-md-raid0 kmod-md-raid1 kmod-md-mod \\\n    kmod-fs-xfs mkf2fs e2fsprogs partx-utils\nendef\nTARGET_DEVICES += buffalo_ls421de\n\ndefine Device/ctera_c200-v2\n  PAGESIZE := 2048\n  SUBPAGESIZE := 512\n  BLOCKSIZE := 128k\n  DEVICE_VENDOR := Ctera\n  DEVICE_MODEL := C200\n  DEVICE_VARIANT := V2\n  SOC := armada-370\n  KERNEL := kernel-bin | append-dtb | uImage none | ctera-firmware\n  KERNEL_IN_UBI :=\n  KERNEL_SUFFIX := -factory.firm\n  DEVICE_PACKAGES :=  \\\n    kmod-gpio-button-hotplug kmod-hwmon-drivetemp kmod-hwmon-nct7802 \\\n    kmod-rtc-s35390a kmod-usb3 kmod-usb-ledtrig-usbport\n  IMAGES := sysupgrade.bin\nendef\nTARGET_DEVICES += ctera_c200-v2\n\ndefine Device/cznic_turris-omnia\n  DEVICE_VENDOR := CZ.NIC\n  DEVICE_MODEL := Turris Omnia\n  KERNEL_INSTALL := 1\n  SOC := armada-385\n  KERNEL := kernel-bin\n  KERNEL_INITRAMFS := kernel-bin | gzip | fit gzip $$(KDIR)/image-$$(DEVICE_DTS).dtb\n  DEVICE_PACKAGES :=  \\\n    mkf2fs e2fsprogs kmod-fs-vfat kmod-nls-cp437 kmod-nls-iso8859-1 \\\n    wpad-basic-wolfssl kmod-ath9k kmod-ath10k-ct ath10k-firmware-qca988x-ct \\\n    partx-utils kmod-i2c-mux-pca954x\n  IMAGES := $$(DEVICE_IMG_PREFIX)-sysupgrade.img.gz omnia-medkit-$$(DEVICE_IMG_PREFIX)-initramfs.tar.gz\n  IMAGE/$$(DEVICE_IMG_PREFIX)-sysupgrade.img.gz := boot-scr | boot-img | sdcard-img | gzip | append-metadata\n  IMAGE/omnia-medkit-$$(DEVICE_IMG_PREFIX)-initramfs.tar.gz := omnia-medkit-initramfs | gzip\n  DEVICE_IMG_NAME = $$(2)\n  SUPPORTED_DEVICES += armada-385-turris-omnia\n  BOOT_SCRIPT := turris-omnia\nendef\nTARGET_DEVICES += cznic_turris-omnia\n\ndefine Device/globalscale_mirabox\n  $(Device/NAND-512K)\n  DEVICE_VENDOR := Globalscale\n  DEVICE_MODEL := Mirabox\n  SOC := armada-370\n  SUPPORTED_DEVICES += mirabox\nendef\nTARGET_DEVICES += globalscale_mirabox\n\ndefine Device/iptime_nas1dual\n  DEVICE_VENDOR := ipTIME\n  DEVICE_MODEL := NAS1dual\n  DEVICE_PACKAGES := kmod-hwmon-drivetemp kmod-hwmon-gpiofan kmod-usb3\n  SOC := armada-385\n  KERNEL := kernel-bin | append-dtb | iptime-naspkg nas1dual\n  KERNEL_SIZE := 6144k\n  IMAGES := sysupgrade.bin\n  IMAGE_SIZE := 64256k\n  IMAGE/sysupgrade.bin := append-kernel | pad-to $$(KERNEL_SIZE) | \\\n\tappend-rootfs | pad-rootfs | check-size | append-metadata\nendef\nTARGET_DEVICES += iptime_nas1dual\n\ndefine Device/kobol_helios4\n  DEVICE_VENDOR := Kobol\n  DEVICE_MODEL := Helios4\n  KERNEL_INSTALL := 1\n  KERNEL := kernel-bin\n  DEVICE_PACKAGES := mkf2fs e2fsprogs partx-utils\n  IMAGES := sdcard.img.gz\n  IMAGE/sdcard.img.gz := boot-scr | boot-img-ext4 | sdcard-img-ext4 | gzip | append-metadata\n  SOC := armada-388\n  UBOOT := helios4-u-boot-spl.kwb\n  BOOT_SCRIPT := clearfog\nendef\nTARGET_DEVICES += kobol_helios4\n\ndefine Device/linksys\n  $(Device/NAND-128K)\n  DEVICE_VENDOR := Linksys\n  DEVICE_PACKAGES := kmod-mwlwifi wpad-basic-wolfssl\n  IMAGES += factory.img\n  IMAGE/factory.img := append-kernel | pad-to $$$$(KERNEL_SIZE) | \\\n\tappend-ubi | pad-to $$$$(PAGESIZE)\n  KERNEL_SIZE := 6144k\nendef\n\ndefine Device/linksys_wrt1200ac\n  $(call Device/linksys)\n  $(Device/dsa-migration)\n  DEVICE_MODEL := WRT1200AC\n  DEVICE_ALT0_VENDOR := Linksys\n  DEVICE_ALT0_MODEL := Caiman\n  DEVICE_DTS := armada-385-linksys-caiman\n  DEVICE_PACKAGES += mwlwifi-firmware-88w8864\n  SUPPORTED_DEVICES += armada-385-linksys-caiman linksys,caiman\nendef\nTARGET_DEVICES += linksys_wrt1200ac\n\ndefine Device/linksys_wrt1900acs\n  $(call Device/linksys)\n  $(Device/dsa-migration)\n  DEVICE_MODEL := WRT1900ACS\n  DEVICE_VARIANT := v1\n  DEVICE_ALT0_VENDOR := Linksys\n  DEVICE_ALT0_MODEL := WRT1900ACS\n  DEVICE_ALT0_VARIANT := v2\n  DEVICE_ALT1_VENDOR := Linksys\n  DEVICE_ALT1_MODEL := Shelby\n  DEVICE_DTS := armada-385-linksys-shelby\n  DEVICE_PACKAGES += mwlwifi-firmware-88w8864\n  SUPPORTED_DEVICES += armada-385-linksys-shelby linksys,shelby\nendef\nTARGET_DEVICES += linksys_wrt1900acs\n\ndefine Device/linksys_wrt1900ac-v1\n  $(call Device/linksys)\n  $(Device/kernel-size-migration)\n  DEVICE_MODEL := WRT1900AC\n  DEVICE_VARIANT := v1\n  DEVICE_ALT0_VENDOR := Linksys\n  DEVICE_ALT0_MODEL := Mamba\n  DEVICE_DTS := armada-xp-linksys-mamba\n  DEVICE_PACKAGES += mwlwifi-firmware-88w8864\n  KERNEL_SIZE := 4096k\n  SUPPORTED_DEVICES += armada-xp-linksys-mamba linksys,mamba\nendef\nTARGET_DEVICES += linksys_wrt1900ac-v1\n\ndefine Device/linksys_wrt1900ac-v2\n  $(call Device/linksys)\n  $(Device/dsa-migration)\n  DEVICE_MODEL := WRT1900AC\n  DEVICE_VARIANT := v2\n  DEVICE_ALT0_VENDOR := Linksys\n  DEVICE_ALT0_MODEL := Cobra\n  DEVICE_DTS := armada-385-linksys-cobra\n  DEVICE_PACKAGES += mwlwifi-firmware-88w8864\n  SUPPORTED_DEVICES += armada-385-linksys-cobra linksys,cobra\nendef\nTARGET_DEVICES += linksys_wrt1900ac-v2\n\ndefine Device/linksys_wrt3200acm\n  $(call Device/linksys)\n  $(Device/dsa-migration)\n  DEVICE_MODEL := WRT3200ACM\n  DEVICE_ALT0_VENDOR := Linksys\n  DEVICE_ALT0_MODEL := Rango\n  DEVICE_DTS := armada-385-linksys-rango\n  DEVICE_PACKAGES += kmod-btmrvl kmod-mwifiex-sdio mwlwifi-firmware-88w8964\n  SUPPORTED_DEVICES += armada-385-linksys-rango linksys,rango\nendef\nTARGET_DEVICES += linksys_wrt3200acm\n\ndefine Device/linksys_wrt32x\n  $(call Device/linksys)\n  $(Device/kernel-size-migration)\n  DEVICE_MODEL := WRT32X\n  DEVICE_ALT0_VENDOR := Linksys\n  DEVICE_ALT0_MODEL := Venom\n  DEVICE_DTS := armada-385-linksys-venom\n  DEVICE_PACKAGES += kmod-btmrvl kmod-mwifiex-sdio mwlwifi-firmware-88w8964\n  KERNEL_SIZE := 6144k\n  KERNEL := kernel-bin | append-dtb\n  SUPPORTED_DEVICES += armada-385-linksys-venom linksys,venom\nendef\nTARGET_DEVICES += linksys_wrt32x\n\ndefine Device/marvell_a370-db\n  $(Device/NAND-512K)\n  DEVICE_VENDOR := Marvell\n  DEVICE_MODEL := Armada 370 Development Board (DB-88F6710-BP-DDR3)\n  DEVICE_DTS := armada-370-db\n  SUPPORTED_DEVICES += armada-370-db\nendef\nTARGET_DEVICES += marvell_a370-db\n\ndefine Device/marvell_a370-rd\n  $(Device/NAND-512K)\n  DEVICE_VENDOR := Marvell\n  DEVICE_MODEL := Armada 370 RD (RD-88F6710-A1)\n  DEVICE_DTS := armada-370-rd\n  SUPPORTED_DEVICES += armada-370-rd\nendef\nTARGET_DEVICES += marvell_a370-rd\n\ndefine Device/marvell_a385-db-ap\n  $(Device/NAND-256K)\n  DEVICE_VENDOR := Marvell\n  DEVICE_MODEL := Armada 385 Development Board AP (DB-88F6820-AP)\n  DEVICE_DTS := armada-385-db-ap\n  IMAGES += factory.img\n  IMAGE/factory.img := append-kernel | pad-to $$$$(KERNEL_SIZE) | \\\n\tappend-ubi | pad-to $$$$(PAGESIZE)\n  KERNEL_SIZE := 8192k\n  SUPPORTED_DEVICES += armada-385-db-ap\nendef\nTARGET_DEVICES += marvell_a385-db-ap\n\ndefine Device/marvell_a388-rd\n  DEVICE_VENDOR := Marvell\n  DEVICE_MODEL := Armada 388 RD (RD-88F6820-AP)\n  DEVICE_DTS := armada-388-rd\n  IMAGES := firmware.bin\n  IMAGE/firmware.bin := append-kernel | pad-to 256k | append-rootfs | pad-rootfs\n  SUPPORTED_DEVICES := armada-388-rd marvell,a385-rd\nendef\nTARGET_DEVICES += marvell_a388-rd\n\ndefine Device/marvell_axp-db\n  $(Device/NAND-512K)\n  DEVICE_VENDOR := Marvell\n  DEVICE_MODEL := Armada XP Development Board (DB-78460-BP)\n  DEVICE_DTS := armada-xp-db\n  SUPPORTED_DEVICES += armada-xp-db\nendef\nTARGET_DEVICES += marvell_axp-db\n\ndefine Device/marvell_axp-gp\n  $(Device/NAND-512K)\n  DEVICE_VENDOR := Marvell\n  DEVICE_MODEL := Armada Armada XP GP (DB-MV784MP-GP)\n  DEVICE_DTS := armada-xp-gp\n  SUPPORTED_DEVICES += armada-xp-gp\nendef\nTARGET_DEVICES += marvell_axp-gp\n\ndefine Device/plathome_openblocks-ax3-4\n  DEVICE_VENDOR := Plat'Home\n  DEVICE_MODEL := OpenBlocks AX3\n  DEVICE_VARIANT := 4 ports\n  SOC := armada-xp\n  SUPPORTED_DEVICES += openblocks-ax3-4\n  BLOCKSIZE := 128k\n  PAGESIZE := 1\n  IMAGES += factory.img\n  IMAGE/factory.img := append-kernel | pad-to $$(BLOCKSIZE) | append-ubi\nendef\nTARGET_DEVICES += plathome_openblocks-ax3-4\n\ndefine Device/solidrun_clearfog-base-a1\n  DEVICE_VENDOR := SolidRun\n  DEVICE_MODEL := ClearFog Base\n  KERNEL_INSTALL := 1\n  KERNEL := kernel-bin\n  DEVICE_PACKAGES := mkf2fs e2fsprogs partx-utils\n  IMAGES := sdcard.img.gz\n  IMAGE/sdcard.img.gz := boot-scr | boot-img-ext4 | sdcard-img-ext4 | gzip | append-metadata\n  DEVICE_DTS := armada-388-clearfog-base armada-388-clearfog-pro\n  UBOOT := clearfog-u-boot-spl.kwb\n  BOOT_SCRIPT := clearfog\n  SUPPORTED_DEVICES += armada-388-clearfog-base\n  DEVICE_COMPAT_VERSION := 1.1\n  DEVICE_COMPAT_MESSAGE := Ethernet interface rename has been dropped\nendef\nTARGET_DEVICES += solidrun_clearfog-base-a1\n\ndefine Device/solidrun_clearfog-pro-a1\n  $(Device/dsa-migration)\n  DEVICE_VENDOR := SolidRun\n  DEVICE_MODEL := ClearFog Pro\n  KERNEL_INSTALL := 1\n  KERNEL := kernel-bin\n  DEVICE_PACKAGES := mkf2fs e2fsprogs partx-utils\n  IMAGES := sdcard.img.gz\n  IMAGE/sdcard.img.gz := boot-scr | boot-img-ext4 | sdcard-img-ext4 | gzip | append-metadata\n  DEVICE_DTS := armada-388-clearfog-pro armada-388-clearfog-base\n  UBOOT := clearfog-u-boot-spl.kwb\n  BOOT_SCRIPT := clearfog\n  SUPPORTED_DEVICES += armada-388-clearfog armada-388-clearfog-pro\nendef\nTARGET_DEVICES += solidrun_clearfog-pro-a1\n"
  },
  {
    "path": "target/linux/mvebu/image/espressobin.bootscript",
    "content": "# Bootscript for Globalscale ESPRESSOBin Board\n\n# Set distro variables if necessary for compability with downstream firmware\nif test -z \"${kernel_addr_r}\"; then\n\tsetenv kernel_addr_r 0x7000000\nfi\n\nif test -z \"${fdt_add_r}\"; then\n\tsetenv fdt_addr_r 0x6f00000\nfi\n\nif test -z \"${devtype}\"; then\n\tsetenv devtype mmc\nfi\n\nif test -z \"${devnum}\"; then\n\tif mmc dev 0; then\n\t\tsetenv devnum 0\n\telif mmc dev 1; then\n\t\tsetenv devnum 1\n\tfi\nfi\n\n# figure out partition uuid to pass to the kernel as root=\npart uuid ${devtype} ${devnum}:2 uuid\n\nsetenv console \"console=ttyMV0,115200 earlycon=ar3700_uart,0xd0012000\"\nsetenv bootargs \"root=PARTUUID=${uuid} rw rootwait ${console}\"\n\necho \"Booting Linux from ${devtype} ${devnum} with args: ${bootargs}\"\nload ${devtype} ${devnum}:1 ${fdt_addr_r} @DTB@.dtb\nload ${devtype} ${devnum}:1 ${kernel_addr_r} Image\n\nbooti ${kernel_addr_r} - ${fdt_addr_r}\n"
  },
  {
    "path": "target/linux/mvebu/image/gen_mvebu_sdcard_img.sh",
    "content": "#!/bin/sh\n# SPDX-License-Identifier: GPL-2.0-or-later\n#\n# Copyright (C) 2016 Josua Mayer\n\nusage() {\n\techo \"$0 <outfile> [<bootloader> <type_partitionN> <size_partitionN> <img_partitionN>]?\"\n}\n\n# always require first 2 or 3 arguments\n# then in pairs up to 8 more for a total of up to 4 partitions\nif [ $# -lt 1 ] || [ $# -gt 14 ] || [ $((($# - 1) % 3)) -ne 0 ]; then\n\tif [ $# -lt 2 ] || [ $# -gt 15 ] || [ $((($# - 2) % 3)) -ne 0 ]; then\n\t\tusage\n\t\texit 1\n\telse\n\t\tBOOTLOADER=\"$2\"\n\tfi\nfi\n\nset -e\n\n# parameters\nOUTFILE=\"$1\"; shift\nif [ -n \"$BOOTLOADER\" ]; then\n\tshift\nfi\n\n# generate image file\nprintf \"Creating %s from /dev/zero: \" \"$OUTFILE\"\ndd if=/dev/zero of=\"$OUTFILE\" bs=512 count=1 >/dev/null\nprintf \"Done\\n\"\n\nwhile [ \"$#\" -ge 3 ]; do\n\tptgen_args=\"$ptgen_args -t $1 -p $(($2 * 1024 + 256))\"\n\tparts=\"$parts$3 \"\n\tshift; shift; shift\ndone\n\nhead=16\nsect=63\n\n# create real partition table using fdisk\nprintf \"Creating partition table: \"\nset $(ptgen -o \"$OUTFILE\" -h $head -s $sect -l 1024 -S 0x$SIGNATURE $ptgen_args)\nprintf \"Done\\n\"\n\n# install bootloader\nif [ -n \"$BOOTLOADER\" ]; then\n\tprintf \"Writing bootloader: \"\n\tdd of=\"$OUTFILE\" if=\"$BOOTLOADER\" bs=512 seek=1 conv=notrunc 2>/dev/null\n\tprintf \"Done\\n\"\nfi\n\ni=1\nwhile [ \"$#\" -ge 2 ]; do\n\timg=\"${parts%% *}\"\n\tparts=\"${parts#* }\"\n\n\tprintf \"Writing %s to partition %i: \" \"$img\" $i\n\t(\n\t\tcat \"$img\"\n\t\t# add padding to avoid leaving behind old overlay fs data\n\t\tdd if=/dev/zero bs=128k count=1 2>/dev/null\n\t) | dd of=\"$OUTFILE\" bs=512 seek=$(($1 / 512)) conv=notrunc 2>/dev/null\n\tprintf \"Done\\n\"\n\n\ti=$((i+1))\n\tshift; shift\ndone\n"
  },
  {
    "path": "target/linux/mvebu/image/generic-arm64.bootscript",
    "content": "setenv bootargs \"root=PARTUUID=@ROOT@-02 rw rootwait\"\n\nif test -n \"${console}\"; then\n\tsetenv bootargs \"${bootargs} ${console}\"\nfi\n\nif mmc dev 0; then\n\tsetenv mmcdev 0\nelif mmc dev 1; then\n\tsetenv mmcdev 1\nfi\n\nif test -n \"${fdt_addr_r}\"; then\n       setenv fdt_addr ${fdt_addr_r}\nfi\n\nif test -n \"${kernel_addr_r}\"; then\n       setenv kernel_addr ${kernel_addr_r}\nfi\n\nload mmc ${mmcdev}:1 ${fdt_addr} @DTB@.dtb\nload mmc ${mmcdev}:1 ${kernel_addr} Image\n\nbooti ${kernel_addr} - ${fdt_addr}\n"
  },
  {
    "path": "target/linux/mvebu/image/turris-omnia.bootscript",
    "content": "# Determine root device\nsetexpr rootpart ${distro_bootpart} + 1\nif test ${devtype} = mmc -a ${devnum} = 0; then\n\tsetenv rootdev /dev/mmcblk0p${rootpart}\nelif test ${devtype} = scsi -a ${devnum} = 0; then\n\tsetenv rootdev /dev/sda${rootpart}\nelse\n\t# New U-Boot only\n\tpart uuid ${devtype} ${devnum}:${rootpart} uuid\n\tsetenv rootdev PARTUUID=${uuid}\nfi\nsetenv bootargs earlyprintk console=ttyS0,115200 root=${rootdev} rootfstype=auto rootwait\n\n# Load device tree and prepare for modification\nload ${devtype} ${devnum}:${distro_bootpart} ${fdt_addr_r} @DTB@.dtb\nfdt addr ${fdt_addr_r}\nfdt resize\n\n# Enable SFP cage, if module is present\ni2c dev 0\ni2c mw 0x70 0.0 0xf\ni2c read 0x71 0 1 0x00fffff1\nsetexpr.b mod_def0 *0x00fffff1 \\& 0x10\nif test ${mod_def0} -eq 0; then\n\tfdt set /sfp status okay\n\tfdt rm /soc/internal-regs/ethernet@34000 phy-handle\n\tfdt set /soc/internal-regs/ethernet@34000 managed in-band-status\nfi\n\n# Load kernel and boot\nload ${devtype} ${devnum}:${distro_bootpart} ${kernel_addr_r} zImage\nbootz ${kernel_addr_r} - ${fdt_addr_r}\n"
  },
  {
    "path": "target/linux/mvebu/image/udpu.bootscript",
    "content": "# Bootscript for Methode uDPU device\n# Device and variables may vary between different revisions\n# of device, so we need to make sure everything is set correctly.\n\n# Set the LED's correctly\ngpio clear 12; gpio clear 40; gpio clear 45;\n\n# Find eMMC device,\nif mmc dev 0; then\n\tsetenv mmcdev 0\n\tsetenv rootdev 'root=/dev/mmcblk0p3'\nelif mmc dev 1; then\n\tsetenv mmcdev 1\n\tsetenv rootdev 'root=/dev/mmcblk1p3'\nfi\n\n# Set the variables if necessary\nif test ${kernel_addr_r}; then\n\tsetenv kernel_addr_r 0x5000000\nfi\n\nif test ${fdt_add_r}; then\n\tsetenv fdt_addr_r 0x4f00000\nfi\n\nsetenv console 'console=ttyMV0,115200 earlycon=ar3700_uart,0xd0012000'\nsetenv bootargs ${console} $rootdev rw rootwait\n\nload mmc ${mmcdev}:1 ${fdt_addr_r} @DTB@.dtb\nload mmc ${mmcdev}:1 ${kernel_addr_r} Image\n\nbooti ${kernel_addr_r} - ${fdt_addr_r}\n\n# If the boot command fails, fallback to recovery image\necho '-- Boot failed, falling back to the recovery image --'\nsetenv bootargs $console\nload mmc ${mmcdev}:2 ${kernel_addr_r} recovery.itb\nbootm ${kernel_addr_r}\n"
  },
  {
    "path": "target/linux/mvebu/modules.mk",
    "content": "define KernelPackage/linkstation-poweroff\n  SUBMENU:=$(OTHER_MENU)\n  DEPENDS:=@TARGET_mvebu\n  TITLE:=Buffalo LinkStation power off driver\n  KCONFIG:=CONFIG_POWER_RESET_LINKSTATION\n  FILES:=$(LINUX_DIR)/drivers/power/reset/linkstation-poweroff.ko\n  AUTOLOAD:=$(call AutoLoad,31,linkstation-poweroff,1)\nendef\n\ndefine KernelPackage/linkstation-poweroff/description\n  This driver supports turning off some Buffalo LinkStations by\n  setting an output pin at the ethernet PHY to the correct state.\n  It also makes the device compatible with the WoL function.\n  Say Y here if you have a Buffalo LinkStation LS421D/E.\nendef\n\n$(eval $(call KernelPackage,linkstation-poweroff))\n"
  },
  {
    "path": "target/linux/mvebu/patches-5.10/001-v5.11-arm64-dts-mcbin-singleshot-add-heartbeat-LED.patch",
    "content": "From da57203dc7fd556fbb3f0ec7d7d7c0b0e893b386 Mon Sep 17 00:00:00 2001\nFrom: Tomasz Maciej Nowak <tmn505@gmail.com>\nDate: Tue, 10 Nov 2020 16:38:31 +0100\nSubject: [PATCH] arm64: dts: mcbin-singleshot: add heartbeat LED\n\nWith board revision 1.3, SolidRun moved the power LED to the middle of\nthe board. In old place of power LED a GPIO controllable heartbeat LED\nwas added. This commit only touches Single Shot variant, since only this\nvariant is all revision 1.3.\n\nNote:\nThis is slightly modified patch. Some boards could be placed in an\nenclosure, so the LED18 is enabled by default, since that'll be the only\nvisible indicator that the board is operating.\n\nReported-by: Alexandra Alth <alexandra@alth.de>\nSigned-off-by: Tomasz Maciej Nowak <tmn505@gmail.com>\nSigned-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>\n---\n .../marvell/armada-8040-mcbin-singleshot.dts  | 22 +++++++++++++++++++\n 1 file changed, 22 insertions(+)\n\n--- a/arch/arm64/boot/dts/marvell/armada-8040-mcbin-singleshot.dts\n+++ b/arch/arm64/boot/dts/marvell/armada-8040-mcbin-singleshot.dts\n@@ -5,6 +5,8 @@\n  * Device Tree file for MACCHIATOBin Armada 8040 community board platform\n  */\n \n+#include <dt-bindings/leds/common.h>\n+\n #include \"armada-8040-mcbin.dtsi\"\n \n / {\n@@ -12,6 +14,20 @@\n \tcompatible = \"marvell,armada8040-mcbin-singleshot\",\n \t\t\t\"marvell,armada8040-mcbin\", \"marvell,armada8040\",\n \t\t\t\"marvell,armada-ap806-quad\", \"marvell,armada-ap806\";\n+\n+\tleds {\n+\t\tcompatible = \"gpio-leds\";\n+\t\tpinctrl-0 = <&cp0_led18_pins>;\n+\t\tpinctrl-names = \"default\";\n+\n+\t\tled18 {\n+\t\t\tgpios = <&cp0_gpio2 1 GPIO_ACTIVE_LOW>;\n+\t\t\tfunction = LED_FUNCTION_HEARTBEAT;\n+\t\t\tcolor = <LED_COLOR_ID_GREEN>;\n+\t\t\tlinux,default-trigger = \"heartbeat\";\n+\t\t\tdefault-state = \"on\";\n+\t\t};\n+\t};\n };\n \n &cp0_eth0 {\n@@ -27,3 +43,10 @@\n \tmanaged = \"in-band-status\";\n \tsfp = <&sfp_eth1>;\n };\n+\n+&cp0_pinctrl {\n+\tcp0_led18_pins: led18-pins {\n+\t\tmarvell,pins = \"mpp33\";\n+\t\tmarvell,function = \"gpio\";\n+\t};\n+};\n"
  },
  {
    "path": "target/linux/mvebu/patches-5.10/002-v5.11-ARM-dts-turris-omnia-enable-HW-buffer-management.patch",
    "content": "From 018b88eee1a2efda26ed2f09aab33ccdc40ef18f Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Marek=20Beh=C3=BAn?= <kabel@kernel.org>\nDate: Sun, 15 Nov 2020 14:59:17 +0100\nSubject: ARM: dts: turris-omnia: enable HW buffer management\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nThe buffer manager is available on Turris Omnia but needs to be\ndescribed in device-tree to be used.\n\nSigned-off-by: Marek Behún <kabel@kernel.org>\nFixes: 26ca8b52d6e1 (\"ARM: dts: add support for Turris Omnia\")\nCc: linux-arm-kernel@lists.infradead.org\nCc: Uwe Kleine-König <uwe@kleine-koenig.org>\nCc: Jason Cooper <jason@lakedaemon.net>\nCc: Gregory CLEMENT <gregory.clement@bootlin.com>\nCc: Andreas Färber <afaerber@suse.de>\nCc: Andrew Lunn <andrew@lunn.ch>\nCc: Rob Herring <robh+dt@kernel.org>\nCc: devicetree@vger.kernel.org\nSigned-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>\n---\n arch/arm/boot/dts/armada-385-turris-omnia.dts | 17 +++++++++++++++++\n 1 file changed, 17 insertions(+)\n\n(limited to 'arch/arm/boot/dts/armada-385-turris-omnia.dts')\n\n--- a/arch/arm/boot/dts/armada-385-turris-omnia.dts\n+++ b/arch/arm/boot/dts/armada-385-turris-omnia.dts\n@@ -84,12 +84,23 @@\n \t};\n };\n \n+&bm {\n+\tstatus = \"okay\";\n+};\n+\n+&bm_bppi {\n+\tstatus = \"okay\";\n+};\n+\n /* Connected to 88E6176 switch, port 6 */\n &eth0 {\n \tpinctrl-names = \"default\";\n \tpinctrl-0 = <&ge0_rgmii_pins>;\n \tstatus = \"okay\";\n \tphy-mode = \"rgmii\";\n+\tbuffer-manager = <&bm>;\n+\tbm,pool-long = <0>;\n+\tbm,pool-short = <3>;\n \n \tfixed-link {\n \t\tspeed = <1000>;\n@@ -103,6 +114,9 @@\n \tpinctrl-0 = <&ge1_rgmii_pins>;\n \tstatus = \"okay\";\n \tphy-mode = \"rgmii\";\n+\tbuffer-manager = <&bm>;\n+\tbm,pool-long = <1>;\n+\tbm,pool-short = <3>;\n \n \tfixed-link {\n \t\tspeed = <1000>;\n@@ -115,6 +129,9 @@\n \tstatus = \"okay\";\n \tphy-mode = \"sgmii\";\n \tphy = <&phy1>;\n+\tbuffer-manager = <&bm>;\n+\tbm,pool-long = <2>;\n+\tbm,pool-short = <3>;\n };\n \n &i2c0 {\n"
  },
  {
    "path": "target/linux/mvebu/patches-5.10/003-v5.11-ARM-dts-turris-omnia-add-comphy-handle-to-eth2.patch",
    "content": "From 9ec25ef84832209a8326f9a71fe3ba14f4bcf301 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Marek=20Beh=C3=BAn?= <kabel@kernel.org>\nDate: Sun, 15 Nov 2020 14:59:18 +0100\nSubject: ARM: dts: turris-omnia: add comphy handle to eth2\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nThe eth2 controller on Turris Omnia is connected to SerDes. For SFP to\nbe able to switch between 1G and 2.5G modes the comphy link has to be\ndefined.\n\nSigned-off-by: Marek Behún <kabel@kernel.org>\nFixes: f3a6a9f3704a (\"ARM: dts: add description for Armada 38x ...\")\nReviewed-by: Andrew Lunn <andrew@lunn.ch>\nReviewed-by: Andreas Färber <afaerber@suse.de>\nCc: linux-arm-kernel@lists.infradead.org\nCc: Uwe Kleine-König <uwe@kleine-koenig.org>\nCc: Jason Cooper <jason@lakedaemon.net>\nCc: Gregory CLEMENT <gregory.clement@bootlin.com>\nCc: Rob Herring <robh+dt@kernel.org>\nCc: devicetree@vger.kernel.org\nSigned-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>\n---\n arch/arm/boot/dts/armada-385-turris-omnia.dts | 1 +\n 1 file changed, 1 insertion(+)\n\n--- a/arch/arm/boot/dts/armada-385-turris-omnia.dts\n+++ b/arch/arm/boot/dts/armada-385-turris-omnia.dts\n@@ -129,6 +129,7 @@\n \tstatus = \"okay\";\n \tphy-mode = \"sgmii\";\n \tphy = <&phy1>;\n+\tphys = <&comphy5 2>;\n \tbuffer-manager = <&bm>;\n \tbm,pool-long = <2>;\n \tbm,pool-short = <3>;\n"
  },
  {
    "path": "target/linux/mvebu/patches-5.10/004-v5.11-ARM-dts-turris-omnia-describe-switch-interrupt.patch",
    "content": "From d29b67c220caf5f4905e1f1576e71bcb6de4af9e Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Marek=20Beh=C3=BAn?= <kabel@kernel.org>\nDate: Sun, 15 Nov 2020 14:59:19 +0100\nSubject: ARM: dts: turris-omnia: describe switch interrupt\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nDescribe switch interrupt for Turris Omnia so that the CPU does not have\nto poll the switch. We also need to to set mpp45 pin to gpio function\nfor this.\n\nSigned-off-by: Marek Behún <kabel@kernel.org>\nFixes: 26ca8b52d6e1 (\"ARM: dts: add support for Turris Omnia\")\nCc: linux-arm-kernel@lists.infradead.org\nCc: Uwe Kleine-König <uwe@kleine-koenig.org>\nCc: Jason Cooper <jason@lakedaemon.net>\nCc: Gregory CLEMENT <gregory.clement@bootlin.com>\nCc: Andreas Färber <afaerber@suse.de>\nCc: Andrew Lunn <andrew@lunn.ch>\nCc: Rob Herring <robh+dt@kernel.org>\nCc: devicetree@vger.kernel.org\nSigned-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>\n---\n arch/arm/boot/dts/armada-385-turris-omnia.dts | 12 +++++++++++-\n 1 file changed, 11 insertions(+), 1 deletion(-)\n\n--- a/arch/arm/boot/dts/armada-385-turris-omnia.dts\n+++ b/arch/arm/boot/dts/armada-385-turris-omnia.dts\n@@ -261,13 +261,18 @@\n \n \t/* Switch MV88E6176 at address 0x10 */\n \tswitch@10 {\n+\t\tpinctrl-names = \"default\";\n+\t\tpinctrl-0 = <&swint_pins>;\n \t\tcompatible = \"marvell,mv88e6085\";\n \t\t#address-cells = <1>;\n \t\t#size-cells = <0>;\n-\t\tdsa,member = <0 0>;\n \n+\t\tdsa,member = <0 0>;\n \t\treg = <0x10>;\n \n+\t\tinterrupt-parent = <&gpio1>;\n+\t\tinterrupts = <13 IRQ_TYPE_LEVEL_LOW>;\n+\n \t\tports {\n \t\t\t#address-cells = <1>;\n \t\t\t#size-cells = <0>;\n@@ -320,6 +325,11 @@\n \t\tmarvell,function = \"gpio\";\n \t};\n \n+\tswint_pins: swint-pins {\n+\t\tmarvell,pins = \"mpp45\";\n+\t\tmarvell,function = \"gpio\";\n+\t};\n+\n \tspi0cs0_pins: spi0cs0-pins {\n \t\tmarvell,pins = \"mpp25\";\n \t\tmarvell,function = \"spi0\";\n"
  },
  {
    "path": "target/linux/mvebu/patches-5.10/005-v5.11-ARM-dts-turris-omnia-add-SFP-node.patch",
    "content": "From add2d65962977caf23ca2fa21a2457d31b636574 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Marek=20Beh=C3=BAn?= <kabel@kernel.org>\nDate: Mon, 16 Nov 2020 13:24:22 +0100\nSubject: ARM: dts: turris-omnia: add SFP node\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nTurris Omnia has an SFP cage that, together with WAN PHY, is connected\nto eth2 SerDes via a SerDes multiplexor. When a SFP module is present,\nthe multiplexor switches the SerDes signal from PHY to SFP.\n\nDescribe the SFP cage, but leave it disabled. Until phylink has support\nfor such configuration, we are leaving it to U-Boot to enable SFP and\ndisable WAN PHY at boot time depending on whether a SFP module is\npresent.\n\nSigned-off-by: Marek Behún <kabel@kernel.org>\nFixes: 26ca8b52d6e1 (\"ARM: dts: add support for Turris Omnia\")\nReviewed-by: Andrew Lunn <andrew@lunn.ch>\nCc: Russell King - ARM Linux admin <linux@armlinux.org.uk>\nCc: linux-arm-kernel@lists.infradead.org\nCc: Uwe Kleine-König <uwe@kleine-koenig.org>\nCc: Jason Cooper <jason@lakedaemon.net>\nCc: Gregory CLEMENT <gregory.clement@bootlin.com>\nCc: Andreas Färber <afaerber@suse.de>\nCc: Rob Herring <robh+dt@kernel.org>\nCc: devicetree@vger.kernel.org\nSigned-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>\n---\n arch/arm/boot/dts/armada-385-turris-omnia.dts | 30 ++++++++++++++++++++++++++-\n 1 file changed, 29 insertions(+), 1 deletion(-)\n\n--- a/arch/arm/boot/dts/armada-385-turris-omnia.dts\n+++ b/arch/arm/boot/dts/armada-385-turris-omnia.dts\n@@ -82,6 +82,24 @@\n \t\t\t};\n \t\t};\n \t};\n+\n+\tsfp: sfp {\n+\t\tcompatible = \"sff,sfp\";\n+\t\ti2c-bus = <&sfp_i2c>;\n+\t\ttx-fault-gpios = <&pcawan 0 GPIO_ACTIVE_HIGH>;\n+\t\ttx-disable-gpios = <&pcawan 1 GPIO_ACTIVE_HIGH>;\n+\t\trate-select0-gpios = <&pcawan 2 GPIO_ACTIVE_HIGH>;\n+\t\tlos-gpios = <&pcawan 3 GPIO_ACTIVE_HIGH>;\n+\t\tmod-def0-gpios = <&pcawan 4 GPIO_ACTIVE_LOW>;\n+\t\tmaximum-power-milliwatt = <3000>;\n+\n+\t\t/*\n+\t\t * For now this has to be enabled at boot time by U-Boot when\n+\t\t * a SFP module is present. Read more in the comment in the\n+\t\t * eth2 node below.\n+\t\t */\n+\t\tstatus = \"disabled\";\n+\t};\n };\n \n &bm {\n@@ -126,10 +144,20 @@\n \n /* WAN port */\n &eth2 {\n+\t/*\n+\t * eth2 is connected via a multiplexor to both the SFP cage and to\n+\t * ethernet-phy@1. The multiplexor switches the signal to SFP cage when\n+\t * a SFP module is present, as determined by the mode-def0 GPIO.\n+\t *\n+\t * Until kernel supports this configuration properly, in case SFP module\n+\t * is present, U-Boot has to enable the sfp node above, remove phy\n+\t * handle and add managed = \"in-band-status\" property.\n+\t */\n \tstatus = \"okay\";\n \tphy-mode = \"sgmii\";\n \tphy = <&phy1>;\n \tphys = <&comphy5 2>;\n+\tsfp = <&sfp>;\n \tbuffer-manager = <&bm>;\n \tbm,pool-long = <2>;\n \tbm,pool-short = <3>;\n@@ -195,7 +223,7 @@\n \t\t\t/* routed to PCIe2 connector (CN62A) */\n \t\t};\n \n-\t\ti2c@4 {\n+\t\tsfp_i2c: i2c@4 {\n \t\t\t#address-cells = <1>;\n \t\t\t#size-cells = <0>;\n \t\t\treg = <4>;\n"
  },
  {
    "path": "target/linux/mvebu/patches-5.10/006-v5.11-ARM-dts-turris-omnia-add-LED-controller-node.patch",
    "content": "From 91dd42d0e30fdbb250c61d1192af569f07e6ada4 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Marek=20Beh=C3=BAn?= <kabel@kernel.org>\nDate: Sun, 15 Nov 2020 14:59:21 +0100\nSubject: ARM: dts: turris-omnia: add LED controller node\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nLinux now has incomplete support for the LED controller on Turris Omnia:\nit can set brightness and colors for each LED.\n\nThe controller can also put these LEDs into HW controlled mode, in which\nthe LEDs are controlled by HW: for example the WAN LED is connected via\nMCU to the WAN PHY LED pin.\n\nThe driver does not support these HW controlled modes yet, and on probe\nputs the LEDs into SW controlled mode.\n\nAdd node describing the LED controller, but disable it for now.\n\nSigned-off-by: Marek Behún <kabel@kernel.org>\nCc: linux-arm-kernel@lists.infradead.org\nCc: Uwe Kleine-König <uwe@kleine-koenig.org>\nCc: Jason Cooper <jason@lakedaemon.net>\nCc: Gregory CLEMENT <gregory.clement@bootlin.com>\nCc: Andreas Färber <afaerber@suse.de>\nCc: Rob Herring <robh+dt@kernel.org>\nCc: devicetree@vger.kernel.org\nSigned-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>\n---\n arch/arm/boot/dts/armada-385-turris-omnia.dts | 111 +++++++++++++++++++++++++-\n 1 file changed, 110 insertions(+), 1 deletion(-)\n\n--- a/arch/arm/boot/dts/armada-385-turris-omnia.dts\n+++ b/arch/arm/boot/dts/armada-385-turris-omnia.dts\n@@ -12,6 +12,7 @@\n \n #include <dt-bindings/gpio/gpio.h>\n #include <dt-bindings/input/input.h>\n+#include <dt-bindings/leds/common.h>\n #include \"armada-385.dtsi\"\n \n / {\n@@ -181,7 +182,115 @@\n \t\t\treg = <0>;\n \n \t\t\t/* STM32F0 command interface at address 0x2a */\n-\t\t\t/* leds device (in STM32F0) at address 0x2b */\n+\n+\t\t\tled-controller@2b {\n+\t\t\t\tcompatible = \"cznic,turris-omnia-leds\";\n+\t\t\t\treg = <0x2b>;\n+\t\t\t\t#address-cells = <1>;\n+\t\t\t\t#size-cells = <0>;\n+\n+\t\t\t\t/*\n+\t\t\t\t * LEDs are controlled by MCU (STM32F0) at\n+\t\t\t\t * address 0x2b.\n+\t\t\t\t *\n+\t\t\t\t * The driver does not support HW control mode\n+\t\t\t\t * for the LEDs yet. Disable the LEDs for now.\n+\t\t\t\t *\n+\t\t\t\t * Also LED functions are not stable yet:\n+\t\t\t\t * - there are 3 LEDs connected via MCU to PCIe\n+\t\t\t\t *   ports. One of these ports supports mSATA.\n+\t\t\t\t *   There is no mSATA nor PCIe function.\n+\t\t\t\t *   For now we use LED_FUNCTION_WLAN, since\n+\t\t\t\t *   in most cases users have wifi cards in\n+\t\t\t\t *   these slots\n+\t\t\t\t * - there are 2 LEDs dedicated for user: A and\n+\t\t\t\t *   B. Again there is no such function defined.\n+\t\t\t\t *   For now we use LED_FUNCTION_INDICATOR\n+\t\t\t\t */\n+\t\t\t\tstatus = \"disabled\";\n+\n+\t\t\t\tmulti-led@0 {\n+\t\t\t\t\treg = <0x0>;\n+\t\t\t\t\tcolor = <LED_COLOR_ID_RGB>;\n+\t\t\t\t\tfunction = LED_FUNCTION_INDICATOR;\n+\t\t\t\t\tfunction-enumerator = <2>;\n+\t\t\t\t};\n+\n+\t\t\t\tmulti-led@1 {\n+\t\t\t\t\treg = <0x1>;\n+\t\t\t\t\tcolor = <LED_COLOR_ID_RGB>;\n+\t\t\t\t\tfunction = LED_FUNCTION_INDICATOR;\n+\t\t\t\t\tfunction-enumerator = <1>;\n+\t\t\t\t};\n+\n+\t\t\t\tmulti-led@2 {\n+\t\t\t\t\treg = <0x2>;\n+\t\t\t\t\tcolor = <LED_COLOR_ID_RGB>;\n+\t\t\t\t\tfunction = LED_FUNCTION_WLAN;\n+\t\t\t\t\tfunction-enumerator = <3>;\n+\t\t\t\t};\n+\n+\t\t\t\tmulti-led@3 {\n+\t\t\t\t\treg = <0x3>;\n+\t\t\t\t\tcolor = <LED_COLOR_ID_RGB>;\n+\t\t\t\t\tfunction = LED_FUNCTION_WLAN;\n+\t\t\t\t\tfunction-enumerator = <2>;\n+\t\t\t\t};\n+\n+\t\t\t\tmulti-led@4 {\n+\t\t\t\t\treg = <0x4>;\n+\t\t\t\t\tcolor = <LED_COLOR_ID_RGB>;\n+\t\t\t\t\tfunction = LED_FUNCTION_WLAN;\n+\t\t\t\t\tfunction-enumerator = <1>;\n+\t\t\t\t};\n+\n+\t\t\t\tmulti-led@5 {\n+\t\t\t\t\treg = <0x5>;\n+\t\t\t\t\tcolor = <LED_COLOR_ID_RGB>;\n+\t\t\t\t\tfunction = LED_FUNCTION_WAN;\n+\t\t\t\t};\n+\n+\t\t\t\tmulti-led@6 {\n+\t\t\t\t\treg = <0x6>;\n+\t\t\t\t\tcolor = <LED_COLOR_ID_RGB>;\n+\t\t\t\t\tfunction = LED_FUNCTION_LAN;\n+\t\t\t\t\tfunction-enumerator = <4>;\n+\t\t\t\t};\n+\n+\t\t\t\tmulti-led@7 {\n+\t\t\t\t\treg = <0x7>;\n+\t\t\t\t\tcolor = <LED_COLOR_ID_RGB>;\n+\t\t\t\t\tfunction = LED_FUNCTION_LAN;\n+\t\t\t\t\tfunction-enumerator = <3>;\n+\t\t\t\t};\n+\n+\t\t\t\tmulti-led@8 {\n+\t\t\t\t\treg = <0x8>;\n+\t\t\t\t\tcolor = <LED_COLOR_ID_RGB>;\n+\t\t\t\t\tfunction = LED_FUNCTION_LAN;\n+\t\t\t\t\tfunction-enumerator = <2>;\n+\t\t\t\t};\n+\n+\t\t\t\tmulti-led@9 {\n+\t\t\t\t\treg = <0x9>;\n+\t\t\t\t\tcolor = <LED_COLOR_ID_RGB>;\n+\t\t\t\t\tfunction = LED_FUNCTION_LAN;\n+\t\t\t\t\tfunction-enumerator = <1>;\n+\t\t\t\t};\n+\n+\t\t\t\tmulti-led@a {\n+\t\t\t\t\treg = <0xa>;\n+\t\t\t\t\tcolor = <LED_COLOR_ID_RGB>;\n+\t\t\t\t\tfunction = LED_FUNCTION_LAN;\n+\t\t\t\t\tfunction-enumerator = <0>;\n+\t\t\t\t};\n+\n+\t\t\t\tmulti-led@b {\n+\t\t\t\t\treg = <0xb>;\n+\t\t\t\t\tcolor = <LED_COLOR_ID_RGB>;\n+\t\t\t\t\tfunction = LED_FUNCTION_POWER;\n+\t\t\t\t};\n+\t\t\t};\n \n \t\t\teeprom@54 {\n \t\t\t\tcompatible = \"atmel,24c64\";\n"
  },
  {
    "path": "target/linux/mvebu/patches-5.10/007-v5.11-ARM-dts-turris-omnia-update-ethernet-phy-node-and-handle-name.patch",
    "content": "From 8ee4a5f4f40da60bb85e13d9dd218a3c9197e3e3 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Marek=20Beh=C3=BAn?= <kabel@kernel.org>\nDate: Sun, 15 Nov 2020 14:59:22 +0100\nSubject: ARM: dts: turris-omnia: update ethernet-phy node and handle name\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nUse property name `phy-handle` instead of the deprecated `phy` to\nconnect eth2 to the PHY.\nRename the node from \"phy@1\" to \"ethernet-phy@1\", since \"phy@1\" is\nincorrect according to device-tree bindings documentation.\nAlso remove the \"ethernet-phy-id0141.0DD1\" compatible string, it is not\nneeded. Kernel can read the PHY identifier itself.\n\nSigned-off-by: Marek Behún <kabel@kernel.org>\nReviewed-by: Andrew Lunn <andrew@lunn.ch>\nCc: linux-arm-kernel@lists.infradead.org\nCc: Uwe Kleine-König <uwe@kleine-koenig.org>\nCc: Jason Cooper <jason@lakedaemon.net>\nCc: Gregory CLEMENT <gregory.clement@bootlin.com>\nCc: Andreas Färber <afaerber@suse.de>\nCc: Rob Herring <robh+dt@kernel.org>\nCc: devicetree@vger.kernel.org\nSigned-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>\n---\n arch/arm/boot/dts/armada-385-turris-omnia.dts | 6 +++---\n 1 file changed, 3 insertions(+), 3 deletions(-)\n\n--- a/arch/arm/boot/dts/armada-385-turris-omnia.dts\n+++ b/arch/arm/boot/dts/armada-385-turris-omnia.dts\n@@ -156,7 +156,7 @@\n \t */\n \tstatus = \"okay\";\n \tphy-mode = \"sgmii\";\n-\tphy = <&phy1>;\n+\tphy-handle = <&phy1>;\n \tphys = <&comphy5 2>;\n \tsfp = <&sfp>;\n \tbuffer-manager = <&bm>;\n@@ -387,9 +387,9 @@\n \tpinctrl-0 = <&mdio_pins>;\n \tstatus = \"okay\";\n \n-\tphy1: phy@1 {\n+\tphy1: ethernet-phy@1 {\n \t\tstatus = \"okay\";\n-\t\tcompatible = \"ethernet-phy-id0141.0DD1\", \"ethernet-phy-ieee802.3-c22\";\n+\t\tcompatible = \"ethernet-phy-ieee802.3-c22\";\n \t\treg = <1>;\n \t\tmarvell,reg-init = <3 18 0 0x4985>;\n \n"
  },
  {
    "path": "target/linux/mvebu/patches-5.10/008-v5.12-ARM-dts-turris-omnia-fix-hardware-buffer-management.patch",
    "content": "From 5b2c7e0ae762fff2b172caf16b2766cc3e1ad859 Mon Sep 17 00:00:00 2001\nFrom: Rui Salvaterra <rsalvaterra@gmail.com>\nDate: Wed, 17 Feb 2021 15:30:38 +0000\nSubject: ARM: dts: turris-omnia: fix hardware buffer management\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nHardware buffer management has never worked on the Turris Omnia, as the\nrequired MBus window hadn't been reserved. Fix thusly.\n\nFixes: 018b88eee1a2 (\"ARM: dts: turris-omnia: enable HW buffer management\")\n\nSigned-off-by: Rui Salvaterra <rsalvaterra@gmail.com>\nReviewed-by: Marek Behún <kabel@kernel.org>\nTested-by: Klaus Kudielka <klaus.kudielka@gmail.com>\nSigned-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>\n---\n arch/arm/boot/dts/armada-385-turris-omnia.dts | 3 ++-\n 1 file changed, 2 insertions(+), 1 deletion(-)\n\n--- a/arch/arm/boot/dts/armada-385-turris-omnia.dts\n+++ b/arch/arm/boot/dts/armada-385-turris-omnia.dts\n@@ -32,7 +32,8 @@\n \t\tranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000\n \t\t\t  MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000\n \t\t\t  MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000\n-\t\t\t  MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000>;\n+\t\t\t  MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000\n+\t\t\t  MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;\n \n \t\tinternal-regs {\n \n"
  },
  {
    "path": "target/linux/mvebu/patches-5.10/300-mvebu-Mangle-bootloader-s-kernel-arguments.patch",
    "content": "From 71270226b14733a4b1f2cde58ea9265caa50b38d Mon Sep 17 00:00:00 2001\nFrom: Adrian Panella <ianchi74@outlook.com>\nDate: Thu, 9 Mar 2017 09:37:17 +0100\nSubject: [PATCH 67/69] generic: Mangle bootloader's kernel arguments\n\nThe command-line arguments provided by the boot loader will be\nappended to a new device tree property: bootloader-args.\nIf there is a property \"append-rootblock\" in DT under /chosen\nand a root= option in bootloaders command line it will be parsed\nand added to DT bootargs with the form: <append-rootblock>XX.\nOnly command line ATAG will be processed, the rest of the ATAGs\nsent by bootloader will be ignored.\nThis is usefull in dual boot systems, to get the current root partition\nwithout afecting the rest of the system.\n\nSigned-off-by: Adrian Panella <ianchi74@outlook.com>\n\nThis patch has been modified to be mvebu specific. The original patch \ndid not pass the bootloader cmdline on if no append-rootblock stanza \nwas found, resulting in blank cmdline and failure to boot.\n\nSigned-off-by: Michael Gray <michael.gray@lantisproject.com>\n---\n arch/arm/Kconfig                        | 11 ++++\n arch/arm/boot/compressed/atags_to_fdt.c | 85 ++++++++++++++++++++++++-\n init/main.c                             | 16 +++++\n 3 files changed, 111 insertions(+), 1 deletion(-)\n\n--- a/arch/arm/Kconfig\n+++ b/arch/arm/Kconfig\n@@ -1781,6 +1781,17 @@ config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEN\n \t  The command-line arguments provided by the boot loader will be\n \t  appended to the the device tree bootargs property.\n \n+config ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE\n+\tbool \"Append rootblock parsing bootloader's kernel arguments\"\n+\thelp\n+\t  The command-line arguments provided by the boot loader will be\n+\t  appended to a new device tree property: bootloader-args.\n+\t  If there is a property \"append-rootblock\" in DT under /chosen \n+\t  and a root= option in bootloaders command line it will be parsed \n+\t  and added to DT bootargs with the form: <append-rootblock>XX.\n+\t  Only command line ATAG will be processed, the rest of the ATAGs\n+\t  sent by bootloader will be ignored.\n+\n endchoice\n \n config CMDLINE\n--- a/arch/arm/boot/compressed/atags_to_fdt.c\n+++ b/arch/arm/boot/compressed/atags_to_fdt.c\n@@ -5,6 +5,8 @@\n \n #if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND)\n #define do_extend_cmdline 1\n+#elif defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)\n+#define do_extend_cmdline 1\n #else\n #define do_extend_cmdline 0\n #endif\n@@ -69,6 +71,72 @@ static uint32_t get_cell_size(const void\n \treturn cell_size;\n }\n \n+#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)\n+\n+static char *append_rootblock(char *dest, const char *str, int len, void *fdt)\n+{\n+\tchar *ptr, *end;\n+\tchar *root=\"root=\";\n+\tint i, l;\n+\tconst char *rootblock;\n+\n+\t//ARM doesn't have __HAVE_ARCH_STRSTR, so search manually\n+\tptr = str - 1;\n+\n+\tdo {\n+\t\t//first find an 'r' at the begining or after a space\n+\t\tdo {\n+\t\t\tptr++;\n+\t\t\tptr = strchr(ptr, 'r');\n+\t\t\tif (!ptr)\n+\t\t\t\tgoto no_append;\n+\n+\t\t} while (ptr != str && *(ptr-1) != ' ');\n+\n+\t\t//then check for the rest\n+\t\tfor(i = 1; i <= 4; i++)\n+\t\t\tif(*(ptr+i) != *(root+i)) break;\n+\n+\t} while (i != 5);\n+\n+\tend = strchr(ptr, ' ');\n+\tend = end ? (end - 1) : (strchr(ptr, 0) - 1);\n+\n+\t//find partition number (assumes format root=/dev/mtdXX | /dev/mtdblockXX | yy:XX )\n+\tfor( i = 0; end >= ptr && *end >= '0' && *end <= '9'; end--, i++);\n+\tptr = end + 1;\n+\n+\t/* if append-rootblock property is set use it to append to command line */\n+\trootblock = getprop(fdt, \"/chosen\", \"append-rootblock\", &l);\n+\tif (rootblock == NULL)\n+\t\tgoto no_append;\n+\n+\tif (*dest != ' ') {\n+\t\t*dest = ' ';\n+\t\tdest++;\n+\t\tlen++;\n+\t}\n+\n+\tif (len + l + i <= COMMAND_LINE_SIZE) {\n+\t\tmemcpy(dest, rootblock, l);\n+\t\tdest += l - 1;\n+\t\tmemcpy(dest, ptr, i);\n+\t\tdest += i;\n+\t}\n+\n+\treturn dest;\n+\n+no_append:\n+\tlen = strlen(str);\n+\tif (len + 1 < COMMAND_LINE_SIZE) {\n+\t\tmemcpy(dest, str, len);\n+\t\tdest += len;\n+\t}\n+\n+\treturn dest;\n+}\n+#endif\n+\n static void merge_fdt_bootargs(void *fdt, const char *fdt_cmdline)\n {\n \tchar cmdline[COMMAND_LINE_SIZE];\n@@ -88,12 +156,21 @@ static void merge_fdt_bootargs(void *fdt\n \n \t/* and append the ATAG_CMDLINE */\n \tif (fdt_cmdline) {\n+\n+#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)\n+\t\t//save original bootloader args\n+\t\t//and append ubi.mtd with root partition number to current cmdline\n+\t\tsetprop_string(fdt, \"/chosen\", \"bootloader-args\", fdt_cmdline);\n+\t\tptr = append_rootblock(ptr, fdt_cmdline, len, fdt);\n+\n+#else\n \t\tlen = strlen(fdt_cmdline);\n \t\tif (ptr - cmdline + len + 2 < COMMAND_LINE_SIZE) {\n \t\t\t*ptr++ = ' ';\n \t\t\tmemcpy(ptr, fdt_cmdline, len);\n \t\t\tptr += len;\n \t\t}\n+#endif\n \t}\n \t*ptr = '\\0';\n \n@@ -168,7 +245,9 @@ int atags_to_fdt(void *atag_list, void *\n \t\t\telse\n \t\t\t\tsetprop_string(fdt, \"/chosen\", \"bootargs\",\n \t\t\t\t\t       atag->u.cmdline.cmdline);\n-\t\t} else if (atag->hdr.tag == ATAG_MEM) {\n+\t\t}\n+#ifndef CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE\n+\t\telse if (atag->hdr.tag == ATAG_MEM) {\n \t\t\tif (memcount >= sizeof(mem_reg_property)/4)\n \t\t\t\tcontinue;\n \t\t\tif (!atag->u.mem.size)\n@@ -212,6 +291,10 @@ int atags_to_fdt(void *atag_list, void *\n \t\tsetprop(fdt, \"/memory\", \"reg\", mem_reg_property,\n \t\t\t4 * memcount * memsize);\n \t}\n+#else\n+\n+\t}\n+#endif\n \n \treturn fdt_pack(fdt);\n }\n--- a/init/main.c\n+++ b/init/main.c\n@@ -110,6 +110,10 @@\n \n #include <kunit/test.h>\n \n+#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)\n+#include <linux/of.h>\n+#endif\n+\n static int kernel_init(void *);\n \n extern void init_IRQ(void);\n@@ -904,6 +908,18 @@ asmlinkage __visible void __init __no_sa\n \tpage_alloc_init();\n \n \tpr_notice(\"Kernel command line: %s\\n\", saved_command_line);\n+\n+#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)\n+\t//Show bootloader's original command line for reference\n+\tif(of_chosen) {\n+\t\tconst char *prop = of_get_property(of_chosen, \"bootloader-args\", NULL);\n+\t\tif(prop)\n+\t\t\tpr_notice(\"Bootloader command line (ignored): %s\\n\", prop);\n+\t\telse\n+\t\t\tpr_notice(\"Bootloader command line not present\\n\");\n+\t}\n+#endif\n+\n \t/* parameters may set static keys */\n \tjump_label_init();\n \tparse_early_param();\n"
  },
  {
    "path": "target/linux/mvebu/patches-5.10/301-mvebu-armada-38x-enable-libata-leds.patch",
    "content": "--- a/arch/arm/mach-mvebu/Kconfig\n+++ b/arch/arm/mach-mvebu/Kconfig\n@@ -67,6 +67,7 @@ config MACH_ARMADA_38X\n \tselect HAVE_ARM_TWD if SMP\n \tselect MACH_MVEBU_V7\n \tselect PINCTRL_ARMADA_38X\n+\tselect ARCH_WANT_LIBATA_LEDS\n \thelp\n \t  Say 'Y' here if you want your kernel to support boards based\n \t  on the Marvell Armada 380/385 SoC with device tree.\n"
  },
  {
    "path": "target/linux/mvebu/patches-5.10/302-add_powertables.patch",
    "content": "--- a/arch/arm/boot/dts/armada-385-linksys.dtsi\n+++ b/arch/arm/boot/dts/armada-385-linksys.dtsi\n@@ -212,11 +212,19 @@\n &pcie1 {\n \t/* Marvell 88W8864, 5GHz-only */\n \tstatus = \"okay\";\n+\n+\tmwlwifi {\n+\t\tmarvell,2ghz = <0>;\n+\t};\n };\n \n &pcie2 {\n \t/* Marvell 88W8864, 2GHz-only */\n \tstatus = \"okay\";\n+\n+\tmwlwifi {\n+\t\tmarvell,5ghz = <0>;\n+\t};\n };\n \n &pinctrl {\n--- a/arch/arm/boot/dts/armada-385-linksys-caiman.dts\n+++ b/arch/arm/boot/dts/armada-385-linksys-caiman.dts\n@@ -142,3 +142,205 @@\n \t\t};\n \t};\n };\n+\n+&pcie1 {\n+\tmwlwifi {\n+\t\tmarvell,chainmask = <2 2>;\n+\t\tmarvell,powertable {\n+\t\t\tAU =\n+\t\t\t\t<36 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,\n+\t\t\t\t<40 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,\n+\t\t\t\t<44 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,\n+\t\t\t\t<48 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,\n+\t\t\t\t<52 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,\n+\t\t\t\t<56 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,\n+\t\t\t\t<60 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,\n+\t\t\t\t<64 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,\n+\t\t\t\t<100 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,\n+\t\t\t\t<104 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,\n+\t\t\t\t<108 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,\n+\t\t\t\t<112 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,\n+\t\t\t\t<116 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,\n+\t\t\t\t<120 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,\n+\t\t\t\t<124 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,\n+\t\t\t\t<128 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,\n+\t\t\t\t<132 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,\n+\t\t\t\t<136 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,\n+\t\t\t\t<140 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,\n+\t\t\t\t<149 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x1a 0x1a 0x17 0x14 0 0xf>,\n+\t\t\t\t<153 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x1a 0x1a 0x17 0x14 0 0xf>,\n+\t\t\t\t<157 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x1a 0x1a 0x17 0x14 0 0xf>,\n+\t\t\t\t<161 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x1a 0x1a 0x17 0x14 0 0xf>,\n+\t\t\t\t<165 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x1a 0x1a 0x17 0x14 0 0xf>;\n+\t\t\tCA =\n+\t\t\t\t<36 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0 0xf>,\n+\t\t\t\t<40 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0 0xf>,\n+\t\t\t\t<44 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0 0xf>,\n+\t\t\t\t<48 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0 0xf>,\n+\t\t\t\t<52 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,\n+\t\t\t\t<56 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,\n+\t\t\t\t<60 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,\n+\t\t\t\t<64 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,\n+\t\t\t\t<100 0 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,\n+\t\t\t\t<104 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,\n+\t\t\t\t<108 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,\n+\t\t\t\t<112 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,\n+\t\t\t\t<116 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,\n+\t\t\t\t<120 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,\n+\t\t\t\t<124 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,\n+\t\t\t\t<128 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,\n+\t\t\t\t<132 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,\n+\t\t\t\t<136 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,\n+\t\t\t\t<140 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,\n+\t\t\t\t<149 0 0x1a 0x1a 0x18 0x17 0x19 0x19 0x17 0x15 0x18 0x18 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>,\n+\t\t\t\t<153 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>,\n+\t\t\t\t<157 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>,\n+\t\t\t\t<161 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>,\n+\t\t\t\t<165 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>;\n+\t\t\tCN =\n+\t\t\t\t<36 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,\n+\t\t\t\t<40 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,\n+\t\t\t\t<44 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,\n+\t\t\t\t<48 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,\n+\t\t\t\t<52 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,\n+\t\t\t\t<56 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,\n+\t\t\t\t<60 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,\n+\t\t\t\t<64 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,\n+\t\t\t\t<100 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,\n+\t\t\t\t<104 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,\n+\t\t\t\t<108 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,\n+\t\t\t\t<112 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,\n+\t\t\t\t<116 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,\n+\t\t\t\t<120 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,\n+\t\t\t\t<124 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,\n+\t\t\t\t<128 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,\n+\t\t\t\t<132 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,\n+\t\t\t\t<136 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,\n+\t\t\t\t<140 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,\n+\t\t\t\t<149 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x11 0x11 0x11 0x11 0 0xf>,\n+\t\t\t\t<153 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0 0xf>,\n+\t\t\t\t<157 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0 0xf>,\n+\t\t\t\t<161 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0 0xf>,\n+\t\t\t\t<165 0 0x15 0x15 0x15 0x15 0x16 0x16 0x16 0x15 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0 0xf>;\n+\t\t\tETSI =\n+\t\t\t\t<36 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,\n+\t\t\t\t<40 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,\n+\t\t\t\t<44 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,\n+\t\t\t\t<48 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,\n+\t\t\t\t<52 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,\n+\t\t\t\t<56 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,\n+\t\t\t\t<60 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,\n+\t\t\t\t<64 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 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0x10 0x10 0 0xf>,\n+\t\t\t\t<64 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,\n+\t\t\t\t<100 0 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,\n+\t\t\t\t<104 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,\n+\t\t\t\t<108 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,\n+\t\t\t\t<112 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,\n+\t\t\t\t<116 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,\n+\t\t\t\t<120 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,\n+\t\t\t\t<124 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,\n+\t\t\t\t<128 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,\n+\t\t\t\t<132 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,\n+\t\t\t\t<136 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,\n+\t\t\t\t<140 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,\n+\t\t\t\t<149 0 0x1a 0x1a 0x18 0x17 0x19 0x19 0x17 0x15 0x18 0x18 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>,\n+\t\t\t\t<153 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>,\n+\t\t\t\t<157 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>,\n+\t\t\t\t<161 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>,\n+\t\t\t\t<165 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>;\n+\t\t};\n+\t};\n+};\n+\n+&pcie2 {\n+\tmwlwifi {\n+\t\tmarvell,chainmask = <2 2>;\n+\t\tmarvell,powertable {\n+\t\t\tAU =\n+\t\t\t\t<1 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<2 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<3 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<4 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<5 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<6 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<7 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<8 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<9 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<10 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<11 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>;\n+\t\t\tCA =\n+\t\t\t\t<1 0 0x19 0x14 0x14 0x14 0x13 0x13 0x13 0x13 0x10 0x10 0x10 0x10 0x00 0x00 0x00 0x00 0 0xf>,\n+\t\t\t\t<2 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>,\n+\t\t\t\t<3 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>,\n+\t\t\t\t<4 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>,\n+\t\t\t\t<5 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>,\n+\t\t\t\t<6 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>,\n+\t\t\t\t<7 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>,\n+\t\t\t\t<8 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>,\n+\t\t\t\t<9 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>,\n+\t\t\t\t<10 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>,\n+\t\t\t\t<11 0 0x19 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x13 0x13 0x13 0x13 0x00 0x00 0x00 0x00 0 0xf>;\n+\t\t\tCN =\n+\t\t\t\t<1 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<2 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<3 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<4 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<5 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<6 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<7 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<8 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<9 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<10 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<11 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<12 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<13 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<14 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>;\n+\t\t\tETSI =\n+\t\t\t\t<1 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<2 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<3 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<4 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<5 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<6 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<7 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<8 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<9 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<10 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<11 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<12 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<13 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>;\n+\t\t\tFCC =\n+\t\t\t\t<1 0 0x19 0x14 0x14 0x14 0x13 0x13 0x13 0x13 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<2 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<3 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<4 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<5 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<6 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<7 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<8 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<9 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<10 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<11 0 0x19 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x13 0x13 0x13 0x13 0x0 0x0 0x0 0x0 0 0xf>;\n+\t\t};\n+\t};\n+};\n--- a/arch/arm/boot/dts/armada-385-linksys-cobra.dts\n+++ b/arch/arm/boot/dts/armada-385-linksys-cobra.dts\n@@ -142,3 +142,205 @@\n \t\t};\n \t};\n };\n+\n+&pcie1 {\n+\tmwlwifi {\n+\t\tmarvell,chainmask = <4 4>;\n+\t\tmarvell,powertable {\n+\t\t\tAU =\n+\t\t\t\t<36 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,\n+\t\t\t\t<40 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,\n+\t\t\t\t<44 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,\n+\t\t\t\t<48 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,\n+\t\t\t\t<52 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,\n+\t\t\t\t<56 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,\n+\t\t\t\t<60 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,\n+\t\t\t\t<64 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,\n+\t\t\t\t<100 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,\n+\t\t\t\t<104 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,\n+\t\t\t\t<108 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,\n+\t\t\t\t<112 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,\n+\t\t\t\t<116 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,\n+\t\t\t\t<120 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,\n+\t\t\t\t<124 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,\n+\t\t\t\t<128 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,\n+\t\t\t\t<132 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,\n+\t\t\t\t<136 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,\n+\t\t\t\t<140 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,\n+\t\t\t\t<149 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>,\n+\t\t\t\t<153 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>,\n+\t\t\t\t<157 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>,\n+\t\t\t\t<161 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>,\n+\t\t\t\t<165 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>;\n+\t\t\tCA =\n+\t\t\t\t<36 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,\n+\t\t\t\t<40 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,\n+\t\t\t\t<44 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,\n+\t\t\t\t<48 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,\n+\t\t\t\t<52 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,\n+\t\t\t\t<56 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,\n+\t\t\t\t<60 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,\n+\t\t\t\t<64 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,\n+\t\t\t\t<100 0 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,\n+\t\t\t\t<104 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,\n+\t\t\t\t<108 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,\n+\t\t\t\t<112 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,\n+\t\t\t\t<116 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,\n+\t\t\t\t<120 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,\n+\t\t\t\t<124 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,\n+\t\t\t\t<128 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,\n+\t\t\t\t<132 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,\n+\t\t\t\t<136 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,\n+\t\t\t\t<140 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,\n+\t\t\t\t<149 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,\n+\t\t\t\t<153 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,\n+\t\t\t\t<157 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,\n+\t\t\t\t<161 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,\n+\t\t\t\t<165 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>;\n+\t\t\tCN =\n+\t\t\t\t<36 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,\n+\t\t\t\t<40 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,\n+\t\t\t\t<44 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,\n+\t\t\t\t<48 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,\n+\t\t\t\t<52 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,\n+\t\t\t\t<56 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,\n+\t\t\t\t<60 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,\n+\t\t\t\t<64 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,\n+\t\t\t\t<100 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,\n+\t\t\t\t<104 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,\n+\t\t\t\t<108 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,\n+\t\t\t\t<112 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,\n+\t\t\t\t<116 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,\n+\t\t\t\t<120 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,\n+\t\t\t\t<124 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,\n+\t\t\t\t<128 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,\n+\t\t\t\t<132 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,\n+\t\t\t\t<136 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,\n+\t\t\t\t<140 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,\n+\t\t\t\t<149 0 0x14 0x14 0x14 0x14 0x13 0x13 0x13 0x13 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,\n+\t\t\t\t<153 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>,\n+\t\t\t\t<157 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>,\n+\t\t\t\t<161 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>,\n+\t\t\t\t<165 0 0x13 0x13 0x13 0x13 0x13 0x13 0x13 0x13 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>;\n+\t\t\tETSI =\n+\t\t\t\t<36 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,\n+\t\t\t\t<40 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,\n+\t\t\t\t<44 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,\n+\t\t\t\t<48 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,\n+\t\t\t\t<52 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,\n+\t\t\t\t<56 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,\n+\t\t\t\t<60 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,\n+\t\t\t\t<64 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,\n+\t\t\t\t<100 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,\n+\t\t\t\t<104 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,\n+\t\t\t\t<108 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,\n+\t\t\t\t<112 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,\n+\t\t\t\t<116 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,\n+\t\t\t\t<120 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,\n+\t\t\t\t<124 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,\n+\t\t\t\t<128 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,\n+\t\t\t\t<132 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,\n+\t\t\t\t<136 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,\n+\t\t\t\t<140 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,\n+\t\t\t\t<149 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>;\n+\t\t\tFCC =\n+\t\t\t\t<36 0 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0 0xf>,\n+\t\t\t\t<40 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0xf 0xf 0xf 0xf 0 0xf>,\n+\t\t\t\t<44 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0xf 0xf 0xf 0xf 0 0xf>,\n+\t\t\t\t<48 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0xf 0xf 0xf 0xf 0 0xf>,\n+\t\t\t\t<52 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,\n+\t\t\t\t<56 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,\n+\t\t\t\t<60 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,\n+\t\t\t\t<64 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,\n+\t\t\t\t<100 0 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,\n+\t\t\t\t<104 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,\n+\t\t\t\t<108 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,\n+\t\t\t\t<112 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,\n+\t\t\t\t<116 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,\n+\t\t\t\t<120 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,\n+\t\t\t\t<124 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,\n+\t\t\t\t<128 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,\n+\t\t\t\t<132 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,\n+\t\t\t\t<136 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,\n+\t\t\t\t<140 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,\n+\t\t\t\t<149 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,\n+\t\t\t\t<153 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,\n+\t\t\t\t<157 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,\n+\t\t\t\t<161 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,\n+\t\t\t\t<165 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>;\n+\t\t};\n+\t};\n+};\n+\n+&pcie2 {\n+\tmwlwifi {\n+\t\tmarvell,chainmask = <4 4>;\n+\t\tmarvell,powertable {\n+\t\t\tAU =\n+\t\t\t\t<1 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<2 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<3 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<4 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<5 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<6 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<7 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<8 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<9 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<10 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<11 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>;\n+\t\t\tCA =\n+\t\t\t\t<1 0 0x17 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0xe 0xe 0xe 0xe 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<2 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<3 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<4 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<5 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<6 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<7 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<8 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<9 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<10 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<11 0 0x17 0x12 0x12 0x12 0x13 0x13 0x13 0x13 0xf 0xf 0xf 0xf 0x0 0x0 0x0 0x0 0 0xf>;\n+\t\t\tCN =\n+\t\t\t\t<1 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<2 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<3 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<4 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<5 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<6 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<7 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<8 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<9 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<10 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<11 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<12 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<13 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<14 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>;\n+\t\t\tETSI =\n+\t\t\t\t<1 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<2 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<3 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<4 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<5 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<6 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<7 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<8 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<9 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<10 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<11 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<12 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<13 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>;\n+\t\t\tFCC =\n+\t\t\t\t<1 0 0x17 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0xe 0xe 0xe 0xe 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<2 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 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b/arch/arm/boot/dts/armada-385-linksys-shelby.dts\n@@ -142,3 +142,205 @@\n \t\t};\n \t};\n };\n+\n+&pcie1 {\n+\tmwlwifi {\n+\t\tmarvell,chainmask = <4 4>;\n+\t\tmarvell,powertable {\n+\t\t\tAU =\n+\t\t\t\t<36 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,\n+\t\t\t\t<40 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,\n+\t\t\t\t<44 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,\n+\t\t\t\t<48 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,\n+\t\t\t\t<52 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,\n+\t\t\t\t<56 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,\n+\t\t\t\t<60 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,\n+\t\t\t\t<64 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,\n+\t\t\t\t<100 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 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0xf>,\n+\t\t\t\t<100 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,\n+\t\t\t\t<104 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,\n+\t\t\t\t<108 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,\n+\t\t\t\t<112 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,\n+\t\t\t\t<116 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,\n+\t\t\t\t<120 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,\n+\t\t\t\t<124 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,\n+\t\t\t\t<128 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,\n+\t\t\t\t<132 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,\n+\t\t\t\t<136 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,\n+\t\t\t\t<140 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,\n+\t\t\t\t<149 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>;\n+\t\t\tFCC =\n+\t\t\t\t<36 0 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0 0xf>,\n+\t\t\t\t<40 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0xf 0xf 0xf 0xf 0 0xf>,\n+\t\t\t\t<44 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0xf 0xf 0xf 0xf 0 0xf>,\n+\t\t\t\t<48 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0xf 0xf 0xf 0xf 0 0xf>,\n+\t\t\t\t<52 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,\n+\t\t\t\t<56 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,\n+\t\t\t\t<60 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,\n+\t\t\t\t<64 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,\n+\t\t\t\t<100 0 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,\n+\t\t\t\t<104 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,\n+\t\t\t\t<108 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,\n+\t\t\t\t<112 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,\n+\t\t\t\t<116 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,\n+\t\t\t\t<120 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,\n+\t\t\t\t<124 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,\n+\t\t\t\t<128 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,\n+\t\t\t\t<132 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,\n+\t\t\t\t<136 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,\n+\t\t\t\t<140 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,\n+\t\t\t\t<149 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,\n+\t\t\t\t<153 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,\n+\t\t\t\t<157 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,\n+\t\t\t\t<161 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,\n+\t\t\t\t<165 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>;\n+\t\t};\n+\t};\n+};\n+\n+&pcie2 {\n+\tmwlwifi {\n+\t\tmarvell,chainmask = <4 4>;\n+\t\tmarvell,powertable {\n+\t\t\tAU =\n+\t\t\t\t<1 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<2 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<3 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<4 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<5 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<6 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<7 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<8 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<9 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<10 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<11 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>;\n+\t\t\tCA =\n+\t\t\t\t<1 0 0x17 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0xe 0xe 0xe 0xe 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<2 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<3 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<4 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<5 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<6 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<7 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<8 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<9 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<10 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<11 0 0x17 0x12 0x12 0x12 0x13 0x13 0x13 0x13 0xf 0xf 0xf 0xf 0x0 0x0 0x0 0x0 0 0xf>;\n+\t\t\tCN =\n+\t\t\t\t<1 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<2 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<3 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<4 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<5 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<6 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<7 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<8 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<9 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<10 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<11 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<12 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<13 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<14 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>;\n+\t\t\tETSI =\n+\t\t\t\t<1 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<2 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<3 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<4 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<5 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<6 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<7 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<8 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<9 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<10 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<11 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<12 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<13 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>;\n+\t\t\tFCC =\n+\t\t\t\t<1 0 0x17 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0xe 0xe 0xe 0xe 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<2 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<3 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<4 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<5 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<6 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<7 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<8 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<9 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<10 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t<11 0 0x17 0x12 0x12 0x12 0x13 0x13 0x13 0x13 0xf 0xf 0xf 0xf 0x0 0x0 0x0 0x0 0 0xf>;\n+\t\t};\n+\t};\n+};\n--- a/arch/arm/boot/dts/armada-385-linksys-rango.dts\n+++ b/arch/arm/boot/dts/armada-385-linksys-rango.dts\n@@ -157,6 +157,18 @@\n \t};\n };\n \n+&pcie1 {\n+\tmwlwifi {\n+\t\tmarvell,chainmask = <4 4>;\n+\t};\n+};\n+\n+&pcie2 {\n+\tmwlwifi {\n+\t\tmarvell,chainmask = <4 4>;\n+\t};\n+};\n+\n &sdhci {\n \tpinctrl-names = \"default\";\n \tpinctrl-0 = <&sdhci_pins>;\n--- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts\n+++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts\n@@ -225,12 +225,100 @@\n \tpcie@2,0 {\n \t\t/* Port 0, Lane 1 */\n \t\tstatus = \"okay\";\n+\n+\t\tmwlwifi {\n+\t\t\tmarvell,5ghz = <0>;\n+\t\t\tmarvell,chainmask = <4 4>;\n+\t\t\tmarvell,powertable {\n+\t\t\t\tFCC =\n+\t\t\t\t\t<1 0 0x17 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t\t<2 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t\t<3 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t\t<4 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t\t<5 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t\t<6 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t\t<7 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t\t<8 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t\t<9 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t\t<10 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t\t<11 0 0x17 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>;\n+\n+\t\t\t\tETSI =\n+\t\t\t\t\t<1 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t\t<2 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t\t<3 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t\t<4 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t\t<5 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t\t<6 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t\t<7 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t\t<8 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t\t<9 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t\t<10 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t\t<11 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t\t<12 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,\n+\t\t\t\t\t<13 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>;\n+\t\t\t};\n+\t\t};\n \t};\n \n \t/* Second mini-PCIe port */\n \tpcie@3,0 {\n \t\t/* Port 0, Lane 3 */\n \t\tstatus = \"okay\";\n+\n+\t\tmwlwifi {\n+\t\t\tmarvell,2ghz = <0>;\n+\t\t\tmarvell,chainmask = <4 4>;\n+\t\t\tmarvell,powertable {\n+\t\t\t\tFCC =\n+\t\t\t\t\t<36 0 0x8 0x8 0x8 0x8 0x8 0x8 0x8 0x8 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,\n+\t\t\t\t\t<40 0 0x8 0x8 0x8 0x8 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,\n+\t\t\t\t\t<44 0 0x8 0x8 0x8 0x8 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,\n+\t\t\t\t\t<48 0 0x8 0x8 0x8 0x8 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,\n+\t\t\t\t\t<52 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0 0xf>,\n+\t\t\t\t\t<56 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0 0xf>,\n+\t\t\t\t\t<60 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0 0xf>,\n+\t\t\t\t\t<64 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0 0xf>,\n+\t\t\t\t\t<100 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,\n+\t\t\t\t\t<104 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,\n+\t\t\t\t\t<108 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,\n+\t\t\t\t\t<112 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,\n+\t\t\t\t\t<116 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,\n+\t\t\t\t\t<120 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,\n+\t\t\t\t\t<124 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,\n+\t\t\t\t\t<128 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,\n+\t\t\t\t\t<132 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,\n+\t\t\t\t\t<136 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,\n+\t\t\t\t\t<140 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,\n+\t\t\t\t\t<149 0 0x16 0x16 0x16 0x16 0x14 0x14 0x14 0x14 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0 0xf>,\n+\t\t\t\t\t<153 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0 0xf>,\n+\t\t\t\t\t<157 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0 0xf>,\n+\t\t\t\t\t<161 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0 0xf>,\n+\t\t\t\t\t<165 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0 0xf>;\n+\n+\t\t\t\tETSI =\n+\t\t\t\t\t<36 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,\n+\t\t\t\t\t<40 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,\n+\t\t\t\t\t<44 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,\n+\t\t\t\t\t<48 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,\n+\t\t\t\t\t<52 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,\n+\t\t\t\t\t<56 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,\n+\t\t\t\t\t<60 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,\n+\t\t\t\t\t<64 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,\n+\t\t\t\t\t<100 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,\n+\t\t\t\t\t<104 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,\n+\t\t\t\t\t<108 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,\n+\t\t\t\t\t<112 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,\n+\t\t\t\t\t<116 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,\n+\t\t\t\t\t<120 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,\n+\t\t\t\t\t<124 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,\n+\t\t\t\t\t<128 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,\n+\t\t\t\t\t<132 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,\n+\t\t\t\t\t<136 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,\n+\t\t\t\t\t<140 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,\n+\t\t\t\t\t<149 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>;\n+\t\t\t};\n+\t\t};\n \t};\n };\n \n"
  },
  {
    "path": "target/linux/mvebu/patches-5.10/303-linksys_hardcode_nand_ecc_settings.patch",
    "content": "Newer Linksys boards might come with a Winbond W29N02GV which can be\nconfigured in different ways. Make sure we configure it the same way\nas the older chips so everything keeps working.\n\nSigned-off-by: Imre Kaloz <kaloz@openwrt.org>\n\n--- a/arch/arm/boot/dts/armada-385-linksys.dtsi\n+++ b/arch/arm/boot/dts/armada-385-linksys.dtsi\n@@ -148,6 +148,8 @@\n \t\treg = <0>;\n \t\tlabel = \"pxa3xx_nand-0\";\n \t\tnand-rb = <0>;\n+\t\tnand-ecc-strength = <4>;\n+\t\tnand-ecc-step-size = <512>;\n \t\tmarvell,nand-keep-config;\n \t\tnand-on-flash-bbt;\n \t};\n"
  },
  {
    "path": "target/linux/mvebu/patches-5.10/304-revert_i2c_delay.patch",
    "content": "--- a/arch/arm/boot/dts/armada-xp.dtsi\n+++ b/arch/arm/boot/dts/armada-xp.dtsi\n@@ -237,12 +237,10 @@\n };\n \n &i2c0 {\n-\tcompatible = \"marvell,mv78230-i2c\", \"marvell,mv64xxx-i2c\";\n \treg = <0x11000 0x100>;\n };\n \n &i2c1 {\n-\tcompatible = \"marvell,mv78230-i2c\", \"marvell,mv64xxx-i2c\";\n \treg = <0x11100 0x100>;\n };\n \n"
  },
  {
    "path": "target/linux/mvebu/patches-5.10/305-armada-385-rd-mtd-partitions.patch",
    "content": "--- a/arch/arm/boot/dts/armada-388-rd.dts\n+++ b/arch/arm/boot/dts/armada-388-rd.dts\n@@ -103,6 +103,16 @@\n \t\tcompatible = \"st,m25p128\", \"jedec,spi-nor\";\n \t\treg = <0>; /* Chip select 0 */\n \t\tspi-max-frequency = <108000000>;\n+\n+\t\tpartition@0 {\n+\t\t\tlabel = \"uboot\";\n+\t\t\treg = <0 0x400000>;\n+\t\t};\n+\n+\t\tpartition@1 {\n+\t\t\tlabel = \"firmware\";\n+\t\t\treg = <0x400000 0xc00000>;\n+\t\t};\n \t};\n };\n \n"
  },
  {
    "path": "target/linux/mvebu/patches-5.10/306-ARM-mvebu-385-ap-Add-partitions.patch",
    "content": "From 9861f93a59142a3131870df2521eb2deb73026d7 Mon Sep 17 00:00:00 2001\nFrom: Maxime Ripard <maxime.ripard@free-electrons.com>\nDate: Tue, 13 Jan 2015 11:14:09 +0100\nSubject: [PATCH 2/2] ARM: mvebu: 385-ap: Add partitions\n\nSigned-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>\n---\n arch/arm/boot/dts/armada-385-db-ap.dts | 15 +++++++++++++++\n 1 file changed, 15 insertions(+)\n\n--- a/arch/arm/boot/dts/armada-385-db-ap.dts\n+++ b/arch/arm/boot/dts/armada-385-db-ap.dts\n@@ -218,19 +218,19 @@\n \t\t\t#size-cells = <1>;\n \n \t\t\tpartition@0 {\n-\t\t\t\tlabel = \"U-Boot\";\n+\t\t\t\tlabel = \"u-boot\";\n \t\t\t\treg = <0x00000000 0x00800000>;\n \t\t\t\tread-only;\n \t\t\t};\n \n \t\t\tpartition@800000 {\n-\t\t\t\tlabel = \"uImage\";\n+\t\t\t\tlabel = \"kernel\";\n \t\t\t\treg = <0x00800000 0x00400000>;\n \t\t\t\tread-only;\n \t\t\t};\n \n \t\t\tpartition@c00000 {\n-\t\t\t\tlabel = \"Root\";\n+\t\t\t\tlabel = \"ubi\";\n \t\t\t\treg = <0x00c00000 0x3f400000>;\n \t\t\t};\n \t\t};\n"
  },
  {
    "path": "target/linux/mvebu/patches-5.10/307-armada-xp-linksys-mamba-broken-idle.patch",
    "content": "--- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts\n+++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts\n@@ -485,3 +485,7 @@\n \t\t};\n \t};\n };\n+\n+&coherencyfab {\n+\tbroken-idle;\n+};\n"
  },
  {
    "path": "target/linux/mvebu/patches-5.10/308-armada-xp-linksys-mamba-wan.patch",
    "content": "--- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts\n+++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts\n@@ -387,7 +387,7 @@\n \n \t\t\tport@4 {\n \t\t\t\treg = <4>;\n-\t\t\t\tlabel = \"internet\";\n+\t\t\t\tlabel = \"wan\";\n \t\t\t};\n \n \t\t\tport@5 {\n"
  },
  {
    "path": "target/linux/mvebu/patches-5.10/309-linksys-status-led.patch",
    "content": "--- a/arch/arm/boot/dts/armada-385-linksys.dtsi\n+++ b/arch/arm/boot/dts/armada-385-linksys.dtsi\n@@ -14,6 +14,13 @@\n \tcompatible = \"linksys,armada385\", \"marvell,armada385\",\n \t\t     \"marvell,armada380\";\n \n+\taliases {\n+\t\tled-boot = &led_power;\n+\t\tled-failsafe = &led_power;\n+\t\tled-running = &led_power;\n+\t\tled-upgrade = &led_power;\n+\t};\n+\n \tchosen {\n \t\tstdout-path = \"serial0:115200n8\";\n \t};\n@@ -71,7 +78,7 @@\n \t\tpinctrl-0 = <&gpio_leds_pins>;\n \t\tpinctrl-names = \"default\";\n \n-\t\tpower {\n+\t\tled_power: power {\n \t\t\tgpios = <&gpio1 23 GPIO_ACTIVE_HIGH>;\n \t\t\tdefault-state = \"on\";\n \t\t};\n--- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts\n+++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts\n@@ -26,6 +26,13 @@\n \tcompatible = \"linksys,mamba\", \"marvell,armadaxp-mv78230\",\n \t\t     \"marvell,armadaxp\", \"marvell,armada-370-xp\";\n \n+\taliases {\n+\t\tled-boot = &led_power;\n+\t\tled-failsafe = &led_power;\n+\t\tled-running = &led_power;\n+\t\tled-upgrade = &led_power;\n+\t};\n+\n \tchosen {\n \t\tbootargs = \"console=ttyS0,115200\";\n \t\tstdout-path = &uart0;\n@@ -197,7 +204,7 @@\n \t\tpinctrl-0 = <&power_led_pin>;\n \t\tpinctrl-names = \"default\";\n \n-\t\tpower {\n+\t\tled_power: power {\n \t\t\tlabel = \"mamba:white:power\";\n \t\t\tgpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;\n \t\t\tdefault-state = \"on\";\n"
  },
  {
    "path": "target/linux/mvebu/patches-5.10/310-linksys-use-eth0-as-cpu-port.patch",
    "content": "--- a/arch/arm/boot/dts/armada-385-linksys.dtsi\n+++ b/arch/arm/boot/dts/armada-385-linksys.dtsi\n@@ -116,7 +116,7 @@\n };\n \n &eth2 {\n-\tstatus = \"okay\";\n+\tstatus = \"disabled\";\n \tphy-mode = \"sgmii\";\n \tbuffer-manager = <&bm>;\n \tbm,pool-long = <2>;\n@@ -200,10 +200,10 @@\n \t\t\t\tlabel = \"wan\";\n \t\t\t};\n \n-\t\t\tport@5 {\n-\t\t\t\treg = <5>;\n+\t\t\tport@6 {\n+\t\t\t\treg = <6>;\n \t\t\t\tlabel = \"cpu\";\n-\t\t\t\tethernet = <&eth2>;\n+\t\t\t\tethernet = <&eth0>;\n \n \t\t\t\tfixed-link {\n \t\t\t\t\tspeed = <1000>;\n"
  },
  {
    "path": "target/linux/mvebu/patches-5.10/311-adjust-compatible-for-linksys.patch",
    "content": "--- a/arch/arm/boot/dts/armada-385-linksys-rango.dts\n+++ b/arch/arm/boot/dts/armada-385-linksys-rango.dts\n@@ -12,8 +12,8 @@\n \n / {\n \tmodel = \"Linksys WRT3200ACM\";\n-\tcompatible = \"linksys,rango\", \"linksys,armada385\", \"marvell,armada385\",\n-\t\t     \"marvell,armada380\";\n+\tcompatible = \"linksys,wrt3200acm\", \"linksys,rango\", \"linksys,armada385\",\n+\t\t     \"marvell,armada385\", \"marvell,armada380\";\n };\n \n &expander0 {\n--- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts\n+++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts\n@@ -22,9 +22,10 @@\n #include \"armada-xp-mv78230.dtsi\"\n \n / {\n-\tmodel = \"Linksys WRT1900AC\";\n-\tcompatible = \"linksys,mamba\", \"marvell,armadaxp-mv78230\",\n-\t\t     \"marvell,armadaxp\", \"marvell,armada-370-xp\";\n+\tmodel = \"Linksys WRT1900AC v1\";\n+\tcompatible = \"linksys,wrt1900ac-v1\", \"linksys,mamba\",\n+\t\t     \"marvell,armadaxp-mv78230\", \"marvell,armadaxp\",\n+\t\t     \"marvell,armada-370-xp\";\n \n \taliases {\n \t\tled-boot = &led_power;\n--- a/arch/arm/boot/dts/armada-385-linksys-cobra.dts\n+++ b/arch/arm/boot/dts/armada-385-linksys-cobra.dts\n@@ -9,8 +9,9 @@\n #include \"armada-385-linksys.dtsi\"\n \n / {\n-\tmodel = \"Linksys WRT1900ACv2\";\n-\tcompatible = \"linksys,cobra\", \"linksys,armada385\", \"marvell,armada385\",\n+\tmodel = \"Linksys WRT1900AC v2\";\n+\tcompatible = \"linksys,wrt1900ac-v2\", \"linksys,cobra\",\n+\t\t     \"linksys,armada385\", \"marvell,armada385\",\n \t\t     \"marvell,armada380\";\n };\n \n--- a/arch/arm/boot/dts/armada-385-linksys-caiman.dts\n+++ b/arch/arm/boot/dts/armada-385-linksys-caiman.dts\n@@ -10,8 +10,8 @@\n \n / {\n \tmodel = \"Linksys WRT1200AC\";\n-\tcompatible = \"linksys,caiman\", \"linksys,armada385\", \"marvell,armada385\",\n-\t\t     \"marvell,armada380\";\n+\tcompatible = \"linksys,wrt1200ac\", \"linksys,caiman\", \"linksys,armada385\",\n+\t\t     \"marvell,armada385\", \"marvell,armada380\";\n };\n \n &expander0 {\n--- a/arch/arm/boot/dts/armada-385-linksys-shelby.dts\n+++ b/arch/arm/boot/dts/armada-385-linksys-shelby.dts\n@@ -10,7 +10,8 @@\n \n / {\n \tmodel = \"Linksys WRT1900ACS\";\n-\tcompatible = \"linksys,shelby\", \"linksys,armada385\", \"marvell,armada385\",\n+\tcompatible = \"linksys,wrt1900acs\", \"linksys,shelby\",\n+\t\t     \"linksys,armada385\", \"marvell,armada385\",\n \t\t     \"marvell,armada380\";\n };\n \n"
  },
  {
    "path": "target/linux/mvebu/patches-5.10/312-ARM-dts-armada388-clearfog-emmc-on-clearfog-base.patch",
    "content": "From 8137da20701c776ad3481115305a5e8e410871ba Mon Sep 17 00:00:00 2001\nFrom: Russell King <rmk+kernel@armlinux.org.uk>\nDate: Tue, 29 Nov 2016 10:15:45 +0000\nSubject: ARM: dts: armada388-clearfog: emmc on clearfog base\n\nSigned-off-by: Russell King <rmk+kernel@armlinux.org.uk>\n---\n arch/arm/boot/dts/armada-388-clearfog-base.dts     |  1 +\n .../dts/armada-38x-solidrun-microsom-emmc.dtsi     | 62 ++++++++++++++++++++++\n 2 files changed, 63 insertions(+)\n create mode 100644 arch/arm/boot/dts/armada-38x-solidrun-microsom-emmc.dtsi\n\n--- a/arch/arm/boot/dts/armada-388-clearfog-base.dts\n+++ b/arch/arm/boot/dts/armada-388-clearfog-base.dts\n@@ -7,6 +7,7 @@\n \n /dts-v1/;\n #include \"armada-388-clearfog.dtsi\"\n+#include \"armada-38x-solidrun-microsom-emmc.dtsi\"\n \n / {\n \tmodel = \"SolidRun Clearfog Base A1\";\n--- /dev/null\n+++ b/arch/arm/boot/dts/armada-38x-solidrun-microsom-emmc.dtsi\n@@ -0,0 +1,62 @@\n+/*\n+ * Device Tree file for SolidRun Armada 38x Microsom add-on for eMMC\n+ *\n+ *  Copyright (C) 2015 Russell King\n+ *\n+ * This board is in development; the contents of this file work with\n+ * the A1 rev 2.0 of the board, which does not represent final\n+ * production board.  Things will change, don't expect this file to\n+ * remain compatible info the future.\n+ *\n+ * This file is dual-licensed: you can use it either under the terms\n+ * of the GPL or the X11 license, at your option. Note that this dual\n+ * licensing only applies to this file, and not this project as a\n+ * whole.\n+ *\n+ *  a) This file is free software; you can redistribute it and/or\n+ *     modify it under the terms of the GNU General Public License\n+ *     version 2 as published by the Free Software Foundation.\n+ *\n+ *     This file is distributed in the hope that it will be useful\n+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of\n+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n+ *     GNU General Public License for more details.\n+ *\n+ * Or, alternatively\n+ *\n+ *  b) Permission is hereby granted, free of charge, to any person\n+ *     obtaining a copy of this software and associated documentation\n+ *     files (the \"Software\"), to deal in the Software without\n+ *     restriction, including without limitation the rights to use\n+ *     copy, modify, merge, publish, distribute, sublicense, and/or\n+ *     sell copies of the Software, and to permit persons to whom the\n+ *     Software is furnished to do so, subject to the following\n+ *     conditions:\n+ *\n+ *     The above copyright notice and this permission notice shall be\n+ *     included in all copies or substantial portions of the Software.\n+ *\n+ *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND\n+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY\n+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n+ *     OTHER DEALINGS IN THE SOFTWARE.\n+ */\n+/ {\n+\tsoc {\n+\t\tinternal-regs {\n+\t\t\tsdhci@d8000 {\n+\t\t\t\tbus-width = <4>;\n+\t\t\t\tno-1-8-v;\n+\t\t\t\tnon-removable;\n+\t\t\t\tpinctrl-0 = <&microsom_sdhci_pins>;\n+\t\t\t\tpinctrl-names = \"default\";\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t\twp-inverted;\n+\t\t\t};\n+\t\t};\n+\t};\n+};\n"
  },
  {
    "path": "target/linux/mvebu/patches-5.10/313-helios4-dts-status-led-alias.patch",
    "content": "--- a/arch/arm/boot/dts/armada-388-helios4.dts\n+++ b/arch/arm/boot/dts/armada-388-helios4.dts\n@@ -15,6 +15,13 @@\n \tmodel = \"Helios4\";\n \tcompatible = \"kobol,helios4\", \"marvell,armada388\",\n \t\t\"marvell,armada385\", \"marvell,armada380\";\n+\t\t\n+\taliases {\n+\t\tled-boot = &led_status;\n+\t\tled-failsafe = &led_status;\n+\t\tled-running = &led_status;\n+\t\tled-upgrade = &led_status;\n+\t};\n \n \tmemory {\n \t\tdevice_type = \"memory\";\n@@ -73,10 +80,9 @@\n \t\tpinctrl-names = \"default\";\n \t\tpinctrl-0 = <&helios_system_led_pins>;\n \n-\t\tstatus-led {\n+\t\tled_status: status-led {\n \t\t\tlabel = \"helios4:green:status\";\n \t\t\tgpios = <&gpio0 24 GPIO_ACTIVE_LOW>;\n-\t\t\tlinux,default-trigger = \"heartbeat\";\n \t\t\tdefault-state = \"on\";\n \t\t};\n \n"
  },
  {
    "path": "target/linux/mvebu/patches-5.10/314-arm64-dts-uDPU-switch-PHY-operation-mode-to-2500base.patch",
    "content": "Certain SFP modules (most notably Nokia GPON ones) first check\nconnectivity on 1000base-x, and switch to 2500base-x afterwards. This\nis considered a quirk so the phylink switches the interface to\n2500base-x as well.\n\nHowever, after power-cycling the uDPU device, network interface/SFP module\nwill not work correctly until the module is re-seated. This patch\nresolves this issue by forcing the interface to be brought up in\n2500base-x mode by default.\n\nSigned-off-by: Jakov Petrina <jakov.petrina@sartura.hr>\nSigned-off-by: Vladimir Vid <vladimir.vid@sartura.hr>\nCc: Luka Perkov <luka.perkov@sartura.hr>\n\n--- a/arch/arm64/boot/dts/marvell/armada-3720-uDPU.dts\n+++ b/arch/arm64/boot/dts/marvell/armada-3720-uDPU.dts\n@@ -162,7 +162,7 @@\n };\n \n &eth0 {\n-\tphy-mode = \"sgmii\";\n+\tphy-mode = \"2500base-x\";\n \tstatus = \"okay\";\n \tmanaged = \"in-band-status\";\n \tphys = <&comphy1 0>;\n@@ -170,7 +170,7 @@\n };\n \n &eth1 {\n-\tphy-mode = \"sgmii\";\n+\tphy-mode = \"2500base-x\";\n \tstatus = \"okay\";\n \tmanaged = \"in-band-status\";\n \tphys = <&comphy0 1>;\n"
  },
  {
    "path": "target/linux/mvebu/patches-5.10/315-armada-xp-linksys-mamba-resize-kernel.patch",
    "content": "From 258233f00bcd013050efee00c5d9128ef8cd62dd Mon Sep 17 00:00:00 2001\nFrom: Tad <tad@spotco.us>\nDate: Fri, 5 Feb 2021 22:32:11 -0500\nSubject: [PATCH] ARM: dts: armada-xp-linksys-mamba: Increase kernel\n partition to 4MB\n\nSigned-off-by: Tad Davanzo <tad@spotco.us>\n---\n arch/arm/boot/dts/armada-xp-linksys-mamba.dts | 8 ++++----\n 1 file changed, 4 insertions(+), 4 deletions(-)\n\n--- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts\n+++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts\n@@ -456,9 +456,9 @@\n \t\t\t\treg = <0xa00000 0x2800000>;  /* 40MB */\n \t\t\t};\n \n-\t\t\tpartition@d00000 {\n+\t\t\tpartition@e00000 {\n \t\t\t\tlabel = \"rootfs1\";\n-\t\t\t\treg = <0xd00000 0x2500000>;  /* 37MB */\n+\t\t\t\treg = <0xe00000 0x2400000>;  /* 36MB */\n \t\t\t};\n \n \t\t\t/* kernel2 overlaps with rootfs2 by design */\n@@ -467,9 +467,9 @@\n \t\t\t\treg = <0x3200000 0x2800000>; /* 40MB */\n \t\t\t};\n \n-\t\t\tpartition@3500000 {\n+\t\t\tpartition@3600000 {\n \t\t\t\tlabel = \"rootfs2\";\n-\t\t\t\treg = <0x3500000 0x2500000>; /* 37MB */\n+\t\t\t\treg = <0x3600000 0x2400000>; /* 36MB */\n \t\t\t};\n \n \t\t\t/*\n"
  },
  {
    "path": "target/linux/mvebu/patches-5.10/316-armada-370-dts-fix-crypto-engine.patch",
    "content": "--- a/arch/arm/boot/dts/armada-370.dtsi\n+++ b/arch/arm/boot/dts/armada-370.dtsi\n@@ -234,7 +234,7 @@\n \t\t\t\tclocks = <&gateclk 23>;\n \t\t\t\tclock-names = \"cesa0\";\n \t\t\t\tmarvell,crypto-srams = <&crypto_sram>;\n-\t\t\t\tmarvell,crypto-sram-size = <0x7e0>;\n+\t\t\t\tmarvell,crypto-sram-size = <0x800>;\n \t\t\t};\n \t\t};\n \n@@ -255,12 +255,17 @@\n \t\t\t * cpuidle workaround.\n \t\t\t */\n \t\t\tidle-sram@0 {\n+\t\t\t\tstatus = \"disabled\";\n \t\t\t\treg = <0x0 0x20>;\n \t\t\t};\n \t\t};\n \t};\n };\n \n+&coherencyfab {\n+\tbroken-idle;\n+};\n+\n /*\n  * Default UART pinctrl setting without RTS/CTS, can be overwritten on\n  * board level if a different configuration is used.\n"
  },
  {
    "path": "target/linux/mvebu/patches-5.10/400-find_active_root.patch",
    "content": "The WRT1900AC among other Linksys routers uses a dual-firmware layout.\nDynamically rename the active partition to \"ubi\".\n\nSigned-off-by: Imre Kaloz <kaloz@openwrt.org>\n\n--- a/drivers/mtd/parsers/ofpart_core.c\n+++ b/drivers/mtd/parsers/ofpart_core.c\n@@ -38,6 +38,8 @@ static bool node_has_compatible(struct d\n \treturn of_get_property(pp, \"compatible\", NULL);\n }\n \n+static int mangled_rootblock;\n+\n static int parse_fixed_partitions(struct mtd_info *master,\n \t\t\t\t  const struct mtd_partition **pparts,\n \t\t\t\t  struct mtd_part_parser_data *data)\n@@ -48,6 +50,7 @@ static int parse_fixed_partitions(struct\n \tstruct device_node *mtd_node;\n \tstruct device_node *ofpart_node;\n \tconst char *partname;\n+\tconst char *owrtpart = \"ubi\";\n \tstruct device_node *pp;\n \tint nr_parts, i, ret = 0;\n \tbool dedicated = true;\n@@ -133,9 +136,13 @@ static int parse_fixed_partitions(struct\n \t\tparts[i].size = of_read_number(reg + a_cells, s_cells);\n \t\tparts[i].of_node = pp;\n \n-\t\tpartname = of_get_property(pp, \"label\", &len);\n-\t\tif (!partname)\n-\t\t\tpartname = of_get_property(pp, \"name\", &len);\n+\t\tif (mangled_rootblock && (i == mangled_rootblock)) {\n+\t\t\tpartname = owrtpart;\n+\t\t} else {\n+\t\t\tpartname = of_get_property(pp, \"label\", &len);\n+\t\t\tif (!partname)\n+\t\t\t\tpartname = of_get_property(pp, \"name\", &len);\n+\t\t}\n \t\tparts[i].name = partname;\n \n \t\tif (of_get_property(pp, \"read-only\", &len))\n@@ -252,6 +259,18 @@ static int __init ofpart_parser_init(voi\n \treturn 0;\n }\n \n+static int __init active_root(char *str)\n+{\n+\tget_option(&str, &mangled_rootblock);\n+\n+\tif (!mangled_rootblock)\n+\t\treturn 1;\n+\n+\treturn 1;\n+}\n+\n+__setup(\"mangled_rootblock=\", active_root);\n+\n static void __exit ofpart_parser_exit(void)\n {\n \tderegister_mtd_parser(&ofpart_parser);\n"
  },
  {
    "path": "target/linux/mvebu/patches-5.10/700-mvneta-tx-queue-workaround.patch",
    "content": "The hardware queue scheduling is apparently configured with fixed\npriorities, which creates a nasty fairness issue where traffic from one\nCPU can starve traffic from all other CPUs.\n\nWork around this issue by forcing all tx packets to go through one CPU,\nuntil this issue is fixed properly.\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n--- a/drivers/net/ethernet/marvell/mvneta.c\n+++ b/drivers/net/ethernet/marvell/mvneta.c\n@@ -4903,6 +4903,16 @@ static int mvneta_ethtool_set_eee(struct\n \treturn phylink_ethtool_set_eee(pp->phylink, eee);\n }\n \n+#ifndef CONFIG_ARM64\n+static u16 mvneta_select_queue(struct net_device *dev, struct sk_buff *skb,\n+\t\t\t       struct net_device *sb_dev)\n+{\n+\t/* XXX: hardware queue scheduling is broken,\n+\t * use only one queue until it is fixed */\n+\treturn 0;\n+}\n+#endif\n+\n static const struct net_device_ops mvneta_netdev_ops = {\n \t.ndo_open            = mvneta_open,\n \t.ndo_stop            = mvneta_stop,\n@@ -4913,6 +4923,9 @@ static const struct net_device_ops mvnet\n \t.ndo_fix_features    = mvneta_fix_features,\n \t.ndo_get_stats64     = mvneta_get_stats64,\n \t.ndo_do_ioctl        = mvneta_ioctl,\n+#ifndef CONFIG_ARM64\n+\t.ndo_select_queue    = mvneta_select_queue,\n+#endif\n \t.ndo_bpf\t     = mvneta_xdp,\n \t.ndo_xdp_xmit        = mvneta_xdp_xmit,\n };\n"
  },
  {
    "path": "target/linux/mvebu/patches-5.10/701-v5.14-net-ethernet-marvell-mvnetaMQPrio.patch",
    "content": "From 4906887a8ae5f1296f8079bcf4565a6092a8e402 Mon Sep 17 00:00:00 2001\nFrom: Maxime Chevallier <maxime.chevallier@bootlin.com>\nDate: Tue, 16 Feb 2021 10:25:36 +0100\nSubject: net: mvneta: Implement mqprio support\n\nImplement a basic MQPrio support, inserting rules in RX that translate\nthe TC to prio mapping into vlan prio to queues.\n\nThe TX logic stays the same as when we don't offload the qdisc.\n\nSigned-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/ethernet/marvell/mvneta.c | 61 +++++++++++++++++++++++++++++++++++\n 1 file changed, 61 insertions(+)\n\n(limited to 'drivers/net/ethernet/marvell/mvneta.c')\n\n--- a/drivers/net/ethernet/marvell/mvneta.c\n+++ b/drivers/net/ethernet/marvell/mvneta.c\n@@ -102,6 +102,8 @@\n #define      MVNETA_TX_NO_DATA_SWAP              BIT(5)\n #define      MVNETA_DESC_SWAP                    BIT(6)\n #define      MVNETA_TX_BRST_SZ_MASK(burst)       ((burst) << 22)\n+#define\tMVNETA_VLAN_PRIO_TO_RXQ\t\t\t 0x2440\n+#define      MVNETA_VLAN_PRIO_RXQ_MAP(prio, rxq) ((rxq) << ((prio) * 3))\n #define MVNETA_PORT_STATUS                       0x2444\n #define      MVNETA_TX_IN_PRGRS                  BIT(0)\n #define      MVNETA_TX_FIFO_EMPTY                BIT(8)\n@@ -490,6 +492,7 @@ struct mvneta_port {\n \tu8 mcast_count[256];\n \tu16 tx_ring_size;\n \tu16 rx_ring_size;\n+\tu8 prio_tc_map[8];\n \n \tphy_interface_t phy_interface;\n \tstruct device_node *dn;\n@@ -4913,6 +4916,63 @@ static u16 mvneta_select_queue(struct ne\n }\n #endif\n \n+static void mvneta_clear_rx_prio_map(struct mvneta_port *pp)\n+{\n+\tmvreg_write(pp, MVNETA_VLAN_PRIO_TO_RXQ, 0);\n+}\n+\n+static void mvneta_setup_rx_prio_map(struct mvneta_port *pp)\n+{\n+\tu32 val = 0;\n+\tint i;\n+\n+\tfor (i = 0; i < rxq_number; i++)\n+\t\tval |= MVNETA_VLAN_PRIO_RXQ_MAP(i, pp->prio_tc_map[i]);\n+\n+\tmvreg_write(pp, MVNETA_VLAN_PRIO_TO_RXQ, val);\n+}\n+\n+static int mvneta_setup_mqprio(struct net_device *dev,\n+\t\t\t       struct tc_mqprio_qopt *qopt)\n+{\n+\tstruct mvneta_port *pp = netdev_priv(dev);\n+\tu8 num_tc;\n+\tint i;\n+\n+\tqopt->hw = TC_MQPRIO_HW_OFFLOAD_TCS;\n+\tnum_tc = qopt->num_tc;\n+\n+\tif (num_tc > rxq_number)\n+\t\treturn -EINVAL;\n+\n+\tif (!num_tc) {\n+\t\tmvneta_clear_rx_prio_map(pp);\n+\t\tnetdev_reset_tc(dev);\n+\t\treturn 0;\n+\t}\n+\n+\tmemcpy(pp->prio_tc_map, qopt->prio_tc_map, sizeof(pp->prio_tc_map));\n+\n+\tmvneta_setup_rx_prio_map(pp);\n+\n+\tnetdev_set_num_tc(dev, qopt->num_tc);\n+\tfor (i = 0; i < qopt->num_tc; i++)\n+\t\tnetdev_set_tc_queue(dev, i, qopt->count[i], qopt->offset[i]);\n+\n+\treturn 0;\n+}\n+\n+static int mvneta_setup_tc(struct net_device *dev, enum tc_setup_type type,\n+\t\t\t   void *type_data)\n+{\n+\tswitch (type) {\n+\tcase TC_SETUP_QDISC_MQPRIO:\n+\t\treturn mvneta_setup_mqprio(dev, type_data);\n+\tdefault:\n+\t\treturn -EOPNOTSUPP;\n+\t}\n+}\n+\n static const struct net_device_ops mvneta_netdev_ops = {\n \t.ndo_open            = mvneta_open,\n \t.ndo_stop            = mvneta_stop,\n@@ -4928,6 +4988,7 @@ static const struct net_device_ops mvnet\n #endif\n \t.ndo_bpf\t     = mvneta_xdp,\n \t.ndo_xdp_xmit        = mvneta_xdp_xmit,\n+\t.ndo_setup_tc\t     = mvneta_setup_tc,\n };\n \n static const struct ethtool_ops mvneta_eth_tool_ops = {\n"
  },
  {
    "path": "target/linux/mvebu/patches-5.10/702-net-next-ethernet-marvell-mvnetaMQPrioOffload.patch",
    "content": "From 75fa71e3acadbb4ab5eda18505277eb9a1f69b23 Mon Sep 17 00:00:00 2001\nFrom: Maxime Chevallier <maxime.chevallier@bootlin.com>\nDate: Fri, 26 Nov 2021 12:20:53 +0100\nSubject: net: mvneta: Use struct tc_mqprio_qopt_offload for MQPrio\n configuration\n\nThe struct tc_mqprio_qopt_offload is a container for struct tc_mqprio_qopt,\nthat allows passing extra parameters, such as traffic shaping. This commit\nconverts the current mqprio code to that new struct.\n\nSigned-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/ethernet/marvell/mvneta.c | 17 ++++++++++-------\n 1 file changed, 10 insertions(+), 7 deletions(-)\n\n(limited to 'drivers/net/ethernet/marvell/mvneta.c')\n\n--- a/drivers/net/ethernet/marvell/mvneta.c\n+++ b/drivers/net/ethernet/marvell/mvneta.c\n@@ -38,6 +38,7 @@\n #include <net/ipv6.h>\n #include <net/tso.h>\n #include <net/page_pool.h>\n+#include <net/pkt_cls.h>\n #include <linux/bpf_trace.h>\n \n /* Registers */\n@@ -4933,14 +4934,14 @@ static void mvneta_setup_rx_prio_map(str\n }\n \n static int mvneta_setup_mqprio(struct net_device *dev,\n-\t\t\t       struct tc_mqprio_qopt *qopt)\n+\t\t\t       struct tc_mqprio_qopt_offload *mqprio)\n {\n \tstruct mvneta_port *pp = netdev_priv(dev);\n \tu8 num_tc;\n \tint i;\n \n-\tqopt->hw = TC_MQPRIO_HW_OFFLOAD_TCS;\n-\tnum_tc = qopt->num_tc;\n+\tmqprio->qopt.hw = TC_MQPRIO_HW_OFFLOAD_TCS;\n+\tnum_tc = mqprio->qopt.num_tc;\n \n \tif (num_tc > rxq_number)\n \t\treturn -EINVAL;\n@@ -4951,13 +4952,15 @@ static int mvneta_setup_mqprio(struct ne\n \t\treturn 0;\n \t}\n \n-\tmemcpy(pp->prio_tc_map, qopt->prio_tc_map, sizeof(pp->prio_tc_map));\n+\tmemcpy(pp->prio_tc_map, mqprio->qopt.prio_tc_map,\n+\t       sizeof(pp->prio_tc_map));\n \n \tmvneta_setup_rx_prio_map(pp);\n \n-\tnetdev_set_num_tc(dev, qopt->num_tc);\n-\tfor (i = 0; i < qopt->num_tc; i++)\n-\t\tnetdev_set_tc_queue(dev, i, qopt->count[i], qopt->offset[i]);\n+\tnetdev_set_num_tc(dev, mqprio->qopt.num_tc);\n+\tfor (i = 0; i < mqprio->qopt.num_tc; i++)\n+\t\tnetdev_set_tc_queue(dev, i, mqprio->qopt.count[i],\n+\t\t\t\t    mqprio->qopt.offset[i]);\n \n \treturn 0;\n }\n"
  },
  {
    "path": "target/linux/mvebu/patches-5.10/703-net-next-ethernet-marvell-mvnetaMQPrioFlag.patch",
    "content": "From e7ca75fe6662f78bfeb0112671c812e4c7b8e214 Mon Sep 17 00:00:00 2001\nFrom: Maxime Chevallier <maxime.chevallier@bootlin.com>\nDate: Fri, 26 Nov 2021 12:20:54 +0100\nSubject: net: mvneta: Don't force-set the offloading flag\n\nThe qopt->hw flag is set by the TC code according to the offloading mode\nasked by user. Don't force-set it in the driver, but instead read it to\nmake sure we do what's asked.\n\nSigned-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/ethernet/marvell/mvneta.c | 4 +++-\n 1 file changed, 3 insertions(+), 1 deletion(-)\n\n(limited to 'drivers/net/ethernet/marvell/mvneta.c')\n\n--- a/drivers/net/ethernet/marvell/mvneta.c\n+++ b/drivers/net/ethernet/marvell/mvneta.c\n@@ -4940,7 +4940,9 @@ static int mvneta_setup_mqprio(struct ne\n \tu8 num_tc;\n \tint i;\n \n-\tmqprio->qopt.hw = TC_MQPRIO_HW_OFFLOAD_TCS;\n+\tif (mqprio->qopt.hw != TC_MQPRIO_HW_OFFLOAD_TCS)\n+\t\treturn 0;\n+\n \tnum_tc = mqprio->qopt.num_tc;\n \n \tif (num_tc > rxq_number)\n"
  },
  {
    "path": "target/linux/mvebu/patches-5.10/704-net-next-ethernet-marvell-mvnetaMQPrioQueue.patch",
    "content": "From e9f7099d0730341b24c057acbf545dd019581db6 Mon Sep 17 00:00:00 2001\nFrom: Maxime Chevallier <maxime.chevallier@bootlin.com>\nDate: Fri, 26 Nov 2021 12:20:55 +0100\nSubject: net: mvneta: Allow having more than one queue per TC\n\nThe current mqprio implementation assumed that we are only using one\nqueue per TC. Use the offset and count parameters to allow using\nmultiple queues per TC. In that case, the controller will use a standard\nround-robin algorithm to pick queues assigned to the same TC, with the\nsame priority.\n\nThis only applies to VLAN priorities in ingress traffic, each TC\ncorresponding to a vlan priority.\n\nSigned-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/ethernet/marvell/mvneta.c | 35 ++++++++++++++++++++---------------\n 1 file changed, 20 insertions(+), 15 deletions(-)\n\n(limited to 'drivers/net/ethernet/marvell/mvneta.c')\n\n--- a/drivers/net/ethernet/marvell/mvneta.c\n+++ b/drivers/net/ethernet/marvell/mvneta.c\n@@ -493,7 +493,6 @@ struct mvneta_port {\n \tu8 mcast_count[256];\n \tu16 tx_ring_size;\n \tu16 rx_ring_size;\n-\tu8 prio_tc_map[8];\n \n \tphy_interface_t phy_interface;\n \tstruct device_node *dn;\n@@ -4922,13 +4921,12 @@ static void mvneta_clear_rx_prio_map(str\n \tmvreg_write(pp, MVNETA_VLAN_PRIO_TO_RXQ, 0);\n }\n \n-static void mvneta_setup_rx_prio_map(struct mvneta_port *pp)\n+static void mvneta_map_vlan_prio_to_rxq(struct mvneta_port *pp, u8 pri, u8 rxq)\n {\n-\tu32 val = 0;\n-\tint i;\n+\tu32 val = mvreg_read(pp, MVNETA_VLAN_PRIO_TO_RXQ);\n \n-\tfor (i = 0; i < rxq_number; i++)\n-\t\tval |= MVNETA_VLAN_PRIO_RXQ_MAP(i, pp->prio_tc_map[i]);\n+\tval &= ~MVNETA_VLAN_PRIO_RXQ_MAP(pri, 0x7);\n+\tval |= MVNETA_VLAN_PRIO_RXQ_MAP(pri, rxq);\n \n \tmvreg_write(pp, MVNETA_VLAN_PRIO_TO_RXQ, val);\n }\n@@ -4937,8 +4935,8 @@ static int mvneta_setup_mqprio(struct ne\n \t\t\t       struct tc_mqprio_qopt_offload *mqprio)\n {\n \tstruct mvneta_port *pp = netdev_priv(dev);\n+\tint rxq, tc;\n \tu8 num_tc;\n-\tint i;\n \n \tif (mqprio->qopt.hw != TC_MQPRIO_HW_OFFLOAD_TCS)\n \t\treturn 0;\n@@ -4948,21 +4946,28 @@ static int mvneta_setup_mqprio(struct ne\n \tif (num_tc > rxq_number)\n \t\treturn -EINVAL;\n \n+\tmvneta_clear_rx_prio_map(pp);\n+\n \tif (!num_tc) {\n-\t\tmvneta_clear_rx_prio_map(pp);\n \t\tnetdev_reset_tc(dev);\n \t\treturn 0;\n \t}\n \n-\tmemcpy(pp->prio_tc_map, mqprio->qopt.prio_tc_map,\n-\t       sizeof(pp->prio_tc_map));\n+\tnetdev_set_num_tc(dev, mqprio->qopt.num_tc);\n \n-\tmvneta_setup_rx_prio_map(pp);\n+\tfor (tc = 0; tc < mqprio->qopt.num_tc; tc++) {\n+\t\tnetdev_set_tc_queue(dev, tc, mqprio->qopt.count[tc],\n+\t\t\t\t    mqprio->qopt.offset[tc]);\n+\n+\t\tfor (rxq = mqprio->qopt.offset[tc];\n+\t\t     rxq < mqprio->qopt.count[tc] + mqprio->qopt.offset[tc];\n+\t\t     rxq++) {\n+\t\t\tif (rxq >= rxq_number)\n+\t\t\t\treturn -EINVAL;\n \n-\tnetdev_set_num_tc(dev, mqprio->qopt.num_tc);\n-\tfor (i = 0; i < mqprio->qopt.num_tc; i++)\n-\t\tnetdev_set_tc_queue(dev, i, mqprio->qopt.count[i],\n-\t\t\t\t    mqprio->qopt.offset[i]);\n+\t\t\tmvneta_map_vlan_prio_to_rxq(pp, tc, rxq);\n+\t\t}\n+\t}\n \n \treturn 0;\n }\n"
  },
  {
    "path": "target/linux/mvebu/patches-5.10/705-net-next-ethernet-marvell-mvnetaMQPrioTCOffload.patch",
    "content": "From 2551dc9e398c37a15e52122d385c29a8b06be45f Mon Sep 17 00:00:00 2001\nFrom: Maxime Chevallier <maxime.chevallier@bootlin.com>\nDate: Fri, 26 Nov 2021 12:20:56 +0100\nSubject: net: mvneta: Add TC traffic shaping offload\n\nThe mvneta controller is able to do some tocken-bucket per-queue traffic\nshaping. This commit adds support for setting these using the TC mqprio\ninterface.\n\nThe token-bucket parameters are customisable, but the current\nimplementation configures them to have a 10kbps resolution for the\nrate limitation, since it allows to cover the whole range of max_rate\nvalues from 10kbps to 5Gbps with 10kbps increments.\n\nSigned-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n drivers/net/ethernet/marvell/mvneta.c | 120 +++++++++++++++++++++++++++++++++-\n 1 file changed, 119 insertions(+), 1 deletion(-)\n\n(limited to 'drivers/net/ethernet/marvell/mvneta.c')\n\n--- a/drivers/net/ethernet/marvell/mvneta.c\n+++ b/drivers/net/ethernet/marvell/mvneta.c\n@@ -248,12 +248,39 @@\n #define      MVNETA_TXQ_SENT_DESC_MASK           0x3fff0000\n #define MVNETA_PORT_TX_RESET                     0x3cf0\n #define      MVNETA_PORT_TX_DMA_RESET            BIT(0)\n+#define MVNETA_TXQ_CMD1_REG\t\t\t 0x3e00\n+#define      MVNETA_TXQ_CMD1_BW_LIM_SEL_V1\t BIT(3)\n+#define      MVNETA_TXQ_CMD1_BW_LIM_EN\t\t BIT(0)\n+#define MVNETA_REFILL_NUM_CLK_REG\t\t 0x3e08\n+#define      MVNETA_REFILL_MAX_NUM_CLK\t\t 0x0000ffff\n #define MVNETA_TX_MTU                            0x3e0c\n #define MVNETA_TX_TOKEN_SIZE                     0x3e14\n #define      MVNETA_TX_TOKEN_SIZE_MAX            0xffffffff\n+#define MVNETA_TXQ_BUCKET_REFILL_REG(q)\t\t (0x3e20 + ((q) << 2))\n+#define      MVNETA_TXQ_BUCKET_REFILL_PERIOD_MASK\t0x3ff00000\n+#define      MVNETA_TXQ_BUCKET_REFILL_PERIOD_SHIFT\t20\n+#define      MVNETA_TXQ_BUCKET_REFILL_VALUE_MAX\t 0x0007ffff\n #define MVNETA_TXQ_TOKEN_SIZE_REG(q)             (0x3e40 + ((q) << 2))\n #define      MVNETA_TXQ_TOKEN_SIZE_MAX           0x7fffffff\n \n+/* The values of the bucket refill base period and refill period are taken from\n+ * the reference manual, and adds up to a base resolution of 10Kbps. This allows\n+ * to cover all rate-limit values from 10Kbps up to 5Gbps\n+ */\n+\n+/* Base period for the rate limit algorithm */\n+#define MVNETA_TXQ_BUCKET_REFILL_BASE_PERIOD_NS\t100\n+\n+/* Number of Base Period to wait between each bucket refill */\n+#define MVNETA_TXQ_BUCKET_REFILL_PERIOD\t1000\n+\n+/* The base resolution for rate limiting, in bps. Any max_rate value should be\n+ * a multiple of that value.\n+ */\n+#define MVNETA_TXQ_RATE_LIMIT_RESOLUTION (NSEC_PER_SEC / \\\n+\t\t\t\t\t (MVNETA_TXQ_BUCKET_REFILL_BASE_PERIOD_NS * \\\n+\t\t\t\t\t  MVNETA_TXQ_BUCKET_REFILL_PERIOD))\n+\n #define MVNETA_LPI_CTRL_0                        0x2cc0\n #define MVNETA_LPI_CTRL_1                        0x2cc4\n #define      MVNETA_LPI_REQUEST_ENABLE           BIT(0)\n@@ -4931,11 +4958,74 @@ static void mvneta_map_vlan_prio_to_rxq(\n \tmvreg_write(pp, MVNETA_VLAN_PRIO_TO_RXQ, val);\n }\n \n+static int mvneta_enable_per_queue_rate_limit(struct mvneta_port *pp)\n+{\n+\tunsigned long core_clk_rate;\n+\tu32 refill_cycles;\n+\tu32 val;\n+\n+\tcore_clk_rate = clk_get_rate(pp->clk);\n+\tif (!core_clk_rate)\n+\t\treturn -EINVAL;\n+\n+\trefill_cycles = MVNETA_TXQ_BUCKET_REFILL_BASE_PERIOD_NS /\n+\t\t\t(NSEC_PER_SEC / core_clk_rate);\n+\n+\tif (refill_cycles > MVNETA_REFILL_MAX_NUM_CLK)\n+\t\treturn -EINVAL;\n+\n+\t/* Enable bw limit algorithm version 3 */\n+\tval = mvreg_read(pp, MVNETA_TXQ_CMD1_REG);\n+\tval &= ~(MVNETA_TXQ_CMD1_BW_LIM_SEL_V1 | MVNETA_TXQ_CMD1_BW_LIM_EN);\n+\tmvreg_write(pp, MVNETA_TXQ_CMD1_REG, val);\n+\n+\t/* Set the base refill rate */\n+\tmvreg_write(pp, MVNETA_REFILL_NUM_CLK_REG, refill_cycles);\n+\n+\treturn 0;\n+}\n+\n+static void mvneta_disable_per_queue_rate_limit(struct mvneta_port *pp)\n+{\n+\tu32 val = mvreg_read(pp, MVNETA_TXQ_CMD1_REG);\n+\n+\tval |= (MVNETA_TXQ_CMD1_BW_LIM_SEL_V1 | MVNETA_TXQ_CMD1_BW_LIM_EN);\n+\tmvreg_write(pp, MVNETA_TXQ_CMD1_REG, val);\n+}\n+\n+static int mvneta_setup_queue_rates(struct mvneta_port *pp, int queue,\n+\t\t\t\t    u64 min_rate, u64 max_rate)\n+{\n+\tu32 refill_val, rem;\n+\tu32 val = 0;\n+\n+\t/* Convert to from Bps to bps */\n+\tmax_rate *= 8;\n+\n+\tif (min_rate)\n+\t\treturn -EINVAL;\n+\n+\trefill_val = div_u64_rem(max_rate, MVNETA_TXQ_RATE_LIMIT_RESOLUTION,\n+\t\t\t\t &rem);\n+\n+\tif (rem || !refill_val ||\n+\t    refill_val > MVNETA_TXQ_BUCKET_REFILL_VALUE_MAX)\n+\t\treturn -EINVAL;\n+\n+\tval = refill_val;\n+\tval |= (MVNETA_TXQ_BUCKET_REFILL_PERIOD <<\n+\t\tMVNETA_TXQ_BUCKET_REFILL_PERIOD_SHIFT);\n+\n+\tmvreg_write(pp, MVNETA_TXQ_BUCKET_REFILL_REG(queue), val);\n+\n+\treturn 0;\n+}\n+\n static int mvneta_setup_mqprio(struct net_device *dev,\n \t\t\t       struct tc_mqprio_qopt_offload *mqprio)\n {\n \tstruct mvneta_port *pp = netdev_priv(dev);\n-\tint rxq, tc;\n+\tint rxq, txq, tc, ret;\n \tu8 num_tc;\n \n \tif (mqprio->qopt.hw != TC_MQPRIO_HW_OFFLOAD_TCS)\n@@ -4949,6 +5039,7 @@ static int mvneta_setup_mqprio(struct ne\n \tmvneta_clear_rx_prio_map(pp);\n \n \tif (!num_tc) {\n+\t\tmvneta_disable_per_queue_rate_limit(pp);\n \t\tnetdev_reset_tc(dev);\n \t\treturn 0;\n \t}\n@@ -4969,6 +5060,33 @@ static int mvneta_setup_mqprio(struct ne\n \t\t}\n \t}\n \n+\tif (mqprio->shaper != TC_MQPRIO_SHAPER_BW_RATE) {\n+\t\tmvneta_disable_per_queue_rate_limit(pp);\n+\t\treturn 0;\n+\t}\n+\n+\tif (mqprio->qopt.num_tc > txq_number)\n+\t\treturn -EINVAL;\n+\n+\tret = mvneta_enable_per_queue_rate_limit(pp);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tfor (tc = 0; tc < mqprio->qopt.num_tc; tc++) {\n+\t\tfor (txq = mqprio->qopt.offset[tc];\n+\t\t     txq < mqprio->qopt.count[tc] + mqprio->qopt.offset[tc];\n+\t\t     txq++) {\n+\t\t\tif (txq >= txq_number)\n+\t\t\t\treturn -EINVAL;\n+\n+\t\t\tret = mvneta_setup_queue_rates(pp, txq,\n+\t\t\t\t\t\t       mqprio->min_rate[tc],\n+\t\t\t\t\t\t       mqprio->max_rate[tc]);\n+\t\t\tif (ret)\n+\t\t\t\treturn ret;\n+\t\t}\n+\t}\n+\n \treturn 0;\n }\n \n"
  },
  {
    "path": "target/linux/mvebu/patches-5.10/800-cpuidle-mvebu-indicate-failure-to-enter-deeper-sleep.patch",
    "content": "From c28b2d367da8a471482e6a4aa8337ab6369a80c2 Mon Sep 17 00:00:00 2001\nFrom: Russell King <rmk+kernel@arm.linux.org.uk>\nDate: Sat, 3 Oct 2015 09:13:05 +0100\nSubject: cpuidle: mvebu: indicate failure to enter deeper sleep states\n\nThe cpuidle ->enter method expects the return value to be the sleep\nstate we entered.  Returning negative numbers or other codes is not\npermissible since coupled CPU idle was merged.\n\nAt least some of the mvebu_v7_cpu_suspend() implementations return the\nvalue from cpu_suspend(), which returns zero if the CPU vectors back\ninto the kernel via cpu_resume() (the success case), or the non-zero\nreturn value of the suspend actor, or one (failure cases).\n\nWe do not want to be returning the failure case value back to CPU idle\nas that indicates that we successfully entered one of the deeper idle\nstates.  Always return zero instead, indicating that we slept for the\nshortest amount of time.\n\nSigned-off-by: Russell King <rmk+kernel@arm.linux.org.uk>\n---\n drivers/cpuidle/cpuidle-mvebu-v7.c | 6 +++++-\n 1 file changed, 5 insertions(+), 1 deletion(-)\n\n--- a/drivers/cpuidle/cpuidle-mvebu-v7.c\n+++ b/drivers/cpuidle/cpuidle-mvebu-v7.c\n@@ -39,8 +39,12 @@ static int mvebu_v7_enter_idle(struct cp\n \tret = mvebu_v7_cpu_suspend(deepidle);\n \tcpu_pm_exit();\n \n+\t/*\n+\t * If we failed to enter the desired state, indicate that we\n+\t * slept lightly.\n+\t */\n \tif (ret)\n-\t\treturn ret;\n+\t\treturn 0;\n \n \treturn index;\n }\n"
  },
  {
    "path": "target/linux/mvebu/patches-5.10/801-pci-mvebu-time-out-reset-on-link-up.patch",
    "content": "From 287b9df160b6159f8d385424904f8bac501280c1 Mon Sep 17 00:00:00 2001\nFrom: Russell King <rmk+kernel@armlinux.org.uk>\nDate: Sat, 9 Jul 2016 10:58:16 +0100\nSubject: pci: mvebu: time out reset on link up\n\nIf the port reports that the link is up while we are resetting, there's\nlittle point in waiting for the full duration.\n\nSigned-off-by: Russell King <rmk+kernel@armlinux.org.uk>\n---\n drivers/pci/controller/pci-mvebu.c | 20 ++++++++++++++------\n 1 file changed, 14 insertions(+), 6 deletions(-)\n\n--- a/drivers/pci/controller/pci-mvebu.c\n+++ b/drivers/pci/controller/pci-mvebu.c\n@@ -941,6 +941,7 @@ static int mvebu_pcie_powerup(struct mve\n \n \tif (port->reset_gpio) {\n \t\tu32 reset_udelay = PCI_PM_D3COLD_WAIT * 1000;\n+\t\tunsigned int i;\n \n \t\tof_property_read_u32(port->dn, \"reset-delay-us\",\n \t\t\t\t     &reset_udelay);\n@@ -948,7 +949,13 @@ static int mvebu_pcie_powerup(struct mve\n \t\tudelay(100);\n \n \t\tgpiod_set_value_cansleep(port->reset_gpio, 0);\n-\t\tmsleep(reset_udelay / 1000);\n+\t\tfor (i = 0; i < reset_udelay; i += 1000) {\n+\t\t\tif (mvebu_pcie_link_up(port))\n+\t\t\t\tbreak;\n+\t\t\tmsleep(1);\n+\t\t}\n+\n+\t\tprintk(\"%s: reset completed in %dus\\n\", port->name, i);\n \t}\n \n \treturn 0;\n@@ -1108,15 +1115,16 @@ static int mvebu_pcie_probe(struct platf\n \t\tif (!child)\n \t\t\tcontinue;\n \n-\t\tret = mvebu_pcie_powerup(port);\n-\t\tif (ret < 0)\n-\t\t\tcontinue;\n-\n \t\tport->base = mvebu_pcie_map_registers(pdev, child, port);\n \t\tif (IS_ERR(port->base)) {\n \t\t\tdev_err(dev, \"%s: cannot map registers\\n\", port->name);\n \t\t\tport->base = NULL;\n-\t\t\tmvebu_pcie_powerdown(port);\n+\t\t\tcontinue;\n+\t\t}\n+\n+\t\tret = mvebu_pcie_powerup(port);\n+\t\tif (ret < 0) {\n+\t\t\tport->base = NULL;\n \t\t\tcontinue;\n \t\t}\n \n"
  },
  {
    "path": "target/linux/mvebu/patches-5.10/901-dt-bindings-Add-IEI-vendor-prefix-and-IEI-WT61P803-P.patch",
    "content": "From aa4a0ccc41997f2da172165c92803abace43bd1c Mon Sep 17 00:00:00 2001\nFrom: Luka Kovacic <luka.kovacic () sartura ! hr>\nDate: Tue, 24 Aug 2021 12:44:32 +0000\nSubject: [PATCH 1/7] dt-bindings: Add IEI vendor prefix and IEI WT61P803\n PUZZLE driver bindings\n\nAdd the IEI WT61P803 PUZZLE Device Tree bindings for MFD, HWMON and LED\ndrivers. A new vendor prefix is also added accordingly for\nIEI Integration Corp.\n\nSigned-off-by: Luka Kovacic <luka.kovacic@sartura.hr>\nSigned-off-by: Pavo Banicevic <pavo.banicevic@sartura.hr>\nCc: Luka Perkov <luka.perkov@sartura.hr>\nCc: Robert Marko <robert.marko@sartura.hr>\n---\n .../hwmon/iei,wt61p803-puzzle-hwmon.yaml      | 53 ++++++++++++\n .../leds/iei,wt61p803-puzzle-leds.yaml        | 39 +++++++++\n .../bindings/mfd/iei,wt61p803-puzzle.yaml     | 82 +++++++++++++++++++\n .../devicetree/bindings/vendor-prefixes.yaml  |  2 +\n 4 files changed, 176 insertions(+)\n create mode 100644 Documentation/devicetree/bindings/hwmon/iei,wt61p803-puzzle-hwmon.yaml\n create mode 100644 Documentation/devicetree/bindings/leds/iei,wt61p803-puzzle-leds.yaml\n create mode 100644 Documentation/devicetree/bindings/mfd/iei,wt61p803-puzzle.yaml\n\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/hwmon/iei,wt61p803-puzzle-hwmon.yaml\n@@ -0,0 +1,53 @@\n+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause\n+%YAML 1.2\n+---\n+$id: http://devicetree.org/schemas/hwmon/iei,wt61p803-puzzle-hwmon.yaml#\n+$schema: http://devicetree.org/meta-schemas/core.yaml#\n+\n+title: IEI WT61P803 PUZZLE MCU HWMON module from IEI Integration Corp.\n+\n+maintainers:\n+  - Luka Kovacic <luka.kovacic@sartura.hr>\n+\n+description: |\n+  This module is a part of the IEI WT61P803 PUZZLE MFD device. For more details\n+  see Documentation/devicetree/bindings/mfd/iei,wt61p803-puzzle.yaml.\n+\n+  The HWMON module is a sub-node of the MCU node in the Device Tree.\n+\n+properties:\n+  compatible:\n+    const: iei,wt61p803-puzzle-hwmon\n+\n+  \"#address-cells\":\n+    const: 1\n+\n+  \"#size-cells\":\n+    const: 0\n+\n+patternProperties:\n+  \"^fan-group@[0-1]$\":\n+    type: object\n+    properties:\n+      reg:\n+        minimum: 0\n+        maximum: 1\n+        description:\n+          Fan group ID\n+\n+      cooling-levels:\n+        minItems: 1\n+        maxItems: 255\n+        description:\n+          Cooling levels for the fans (PWM value mapping)\n+    description: |\n+      Properties for each fan group.\n+    required:\n+      - reg\n+\n+required:\n+  - compatible\n+  - \"#address-cells\"\n+  - \"#size-cells\"\n+\n+additionalProperties: false\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/leds/iei,wt61p803-puzzle-leds.yaml\n@@ -0,0 +1,39 @@\n+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause\n+%YAML 1.2\n+---\n+$id: http://devicetree.org/schemas/leds/iei,wt61p803-puzzle-leds.yaml#\n+$schema: http://devicetree.org/meta-schemas/core.yaml#\n+\n+title: IEI WT61P803 PUZZLE MCU LED module from IEI Integration Corp.\n+\n+maintainers:\n+  - Luka Kovacic <luka.kovacic@sartura.hr>\n+\n+description: |\n+  This module is a part of the IEI WT61P803 PUZZLE MFD device. For more details\n+  see Documentation/devicetree/bindings/mfd/iei,wt61p803-puzzle.yaml.\n+\n+  The LED module is a sub-node of the MCU node in the Device Tree.\n+\n+properties:\n+  compatible:\n+    const: iei,wt61p803-puzzle-leds\n+\n+  \"#address-cells\":\n+    const: 1\n+\n+  \"#size-cells\":\n+    const: 0\n+\n+  led@0:\n+    type: object\n+    $ref: common.yaml\n+    description: |\n+      Properties for a single LED.\n+\n+required:\n+  - compatible\n+  - \"#address-cells\"\n+  - \"#size-cells\"\n+\n+additionalProperties: false\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/mfd/iei,wt61p803-puzzle.yaml\n@@ -0,0 +1,82 @@\n+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause\n+%YAML 1.2\n+---\n+$id: http://devicetree.org/schemas/mfd/iei,wt61p803-puzzle.yaml#\n+$schema: http://devicetree.org/meta-schemas/core.yaml#\n+\n+title: IEI WT61P803 PUZZLE MCU from IEI Integration Corp.\n+\n+maintainers:\n+  - Luka Kovacic <luka.kovacic@sartura.hr>\n+\n+description: |\n+  IEI WT61P803 PUZZLE MCU is embedded in some IEI Puzzle series boards.\n+  It's used for controlling system power states, fans, LEDs and temperature\n+  sensors.\n+\n+  For Device Tree bindings of other sub-modules (HWMON, LEDs) refer to the\n+  binding documents under the respective subsystem directories.\n+\n+properties:\n+  compatible:\n+    const: iei,wt61p803-puzzle\n+\n+  current-speed:\n+    description:\n+      Serial bus speed in bps\n+    maxItems: 1\n+\n+  enable-beep: true\n+\n+  hwmon:\n+    $ref: /schemas/hwmon/iei,wt61p803-puzzle-hwmon.yaml\n+\n+  leds:\n+    $ref: /schemas/leds/iei,wt61p803-puzzle-leds.yaml\n+\n+required:\n+  - compatible\n+  - current-speed\n+\n+additionalProperties: false\n+\n+examples:\n+  - |\n+    #include <dt-bindings/leds/common.h>\n+    serial {\n+        mcu {\n+            compatible = \"iei,wt61p803-puzzle\";\n+            current-speed = <115200>;\n+            enable-beep;\n+\n+            leds {\n+                compatible = \"iei,wt61p803-puzzle-leds\";\n+                #address-cells = <1>;\n+                #size-cells = <0>;\n+\n+                led@0 {\n+                    reg = <0>;\n+                    function = LED_FUNCTION_POWER;\n+                    color = <LED_COLOR_ID_BLUE>;\n+                };\n+            };\n+\n+            hwmon {\n+                compatible = \"iei,wt61p803-puzzle-hwmon\";\n+                #address-cells = <1>;\n+                #size-cells = <0>;\n+\n+                fan-group@0 {\n+                    #cooling-cells = <2>;\n+                    reg = <0x00>;\n+                    cooling-levels = <64 102 170 230 250>;\n+                };\n+\n+                fan-group@1 {\n+                    #cooling-cells = <2>;\n+                    reg = <0x01>;\n+                    cooling-levels = <64 102 170 230 250>;\n+                };\n+            };\n+        };\n+    };\n--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml\n+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml\n@@ -475,6 +475,8 @@ patternProperties:\n     description: IC Plus Corp.\n   \"^idt,.*\":\n     description: Integrated Device Technologies, Inc.\n+  \"^iei,.*\":\n+    description: IEI Integration Corp.\n   \"^ifi,.*\":\n     description: Ingenieurburo Fur Ic-Technologie (I/F/I)\n   \"^ilitek,.*\":\n"
  },
  {
    "path": "target/linux/mvebu/patches-5.10/902-drivers-mfd-Add-a-driver-for-IEI-WT61P803-PUZZLE-MCU.patch",
    "content": "From 692cfa85272dd12995b427c0a7a585ced5d54f32 Mon Sep 17 00:00:00 2001\nFrom: Luka Kovacic <luka.kovacic () sartura ! hr>\nDate: Tue, 24 Aug 2021 12:44:33 +0000\nSubject: [PATCH 2/7] drivers: mfd: Add a driver for IEI WT61P803 PUZZLE MCU\n\nAdd a driver for the IEI WT61P803 PUZZLE microcontroller, used in some\nIEI Puzzle series devices. The microcontroller controls system power,\ntemperature sensors, fans and LEDs.\n\nThis driver implements the core functionality for device communication\nover the system serial (serdev bus). It handles MCU messages and the\ninternal MCU properties. Some properties can be managed over sysfs.\n\nSigned-off-by: Luka Kovacic <luka.kovacic@sartura.hr>\nSigned-off-by: Pavo Banicevic <pavo.banicevic@sartura.hr>\nCc: Luka Perkov <luka.perkov@sartura.hr>\nCc: Robert Marko <robert.marko@sartura.hr>\n---\n drivers/mfd/Kconfig                     |   8 +\n drivers/mfd/Makefile                    |   1 +\n drivers/mfd/iei-wt61p803-puzzle.c       | 908 ++++++++++++++++++++++++\n include/linux/mfd/iei-wt61p803-puzzle.h |  66 ++\n 4 files changed, 983 insertions(+)\n create mode 100644 drivers/mfd/iei-wt61p803-puzzle.c\n create mode 100644 include/linux/mfd/iei-wt61p803-puzzle.h\n\n--- a/drivers/mfd/Kconfig\n+++ b/drivers/mfd/Kconfig\n@@ -2155,6 +2155,15 @@ config SGI_MFD_IOC3\n \t  If you have an SGI Origin, Octane, or a PCI IOC3 card,\n \t  then say Y. Otherwise say N.\n \n+config MFD_IEI_WT61P803_PUZZLE\n+\ttristate \"IEI WT61P803 PUZZLE MCU driver\"\n+\tdepends on SERIAL_DEV_BUS\n+\tselect MFD_CORE\n+\thelp\n+\t  IEI WT61P803 PUZZLE is a system power management microcontroller\n+\t  used for fan control, temperature sensor reading, LED control\n+\t  and system identification.\n+\n config MFD_INTEL_M10_BMC\n \ttristate \"Intel MAX 10 Board Management Controller\"\n \tdepends on SPI_MASTER\n--- a/drivers/mfd/Makefile\n+++ b/drivers/mfd/Makefile\n@@ -237,6 +237,7 @@ obj-$(CONFIG_MFD_HI655X_PMIC)   += hi655\n obj-$(CONFIG_MFD_DLN2)\t\t+= dln2.o\n obj-$(CONFIG_MFD_RT5033)\t+= rt5033.o\n obj-$(CONFIG_MFD_SKY81452)\t+= sky81452.o\n+obj-$(CONFIG_MFD_IEI_WT61P803_PUZZLE)\t+= iei-wt61p803-puzzle.o\n \n intel-soc-pmic-objs\t\t:= intel_soc_pmic_core.o intel_soc_pmic_crc.o\n obj-$(CONFIG_INTEL_SOC_PMIC)\t+= intel-soc-pmic.o\n--- /dev/null\n+++ b/drivers/mfd/iei-wt61p803-puzzle.c\n@@ -0,0 +1,908 @@\n+// SPDX-License-Identifier: GPL-2.0-only\n+/* IEI WT61P803 PUZZLE MCU Driver\n+ * System management microcontroller for fan control, temperature sensor reading,\n+ * LED control and system identification on IEI Puzzle series ARM-based appliances.\n+ *\n+ * Copyright (C) 2020 Sartura Ltd.\n+ * Author: Luka Kovacic <luka.kovacic@sartura.hr>\n+ */\n+\n+#include <linux/atomic.h>\n+#include <linux/delay.h>\n+#include <linux/export.h>\n+#include <linux/init.h>\n+#include <linux/kernel.h>\n+#include <linux/mfd/core.h>\n+#include <linux/mfd/iei-wt61p803-puzzle.h>\n+#include <linux/mod_devicetable.h>\n+#include <linux/module.h>\n+#include <linux/of_platform.h>\n+#include <linux/property.h>\n+#include <linux/sched.h>\n+#include <linux/serdev.h>\n+#include <linux/slab.h>\n+#include <linux/sysfs.h>\n+#include <asm/unaligned.h>\n+\n+/* start, payload and XOR checksum at end */\n+#define IEI_WT61P803_PUZZLE_MAX_COMMAND_LENGTH\t(1 + 20 + 1)\n+#define IEI_WT61P803_PUZZLE_RESP_BUF_SIZE\t512\n+\n+#define IEI_WT61P803_PUZZLE_MAC_LENGTH\t\t\t17\n+#define IEI_WT61P803_PUZZLE_SN_LENGTH\t\t\t36\n+#define IEI_WT61P803_PUZZLE_VERSION_LENGTH\t\t 6\n+#define IEI_WT61P803_PUZZLE_BUILD_INFO_LENGTH\t\t16\n+#define IEI_WT61P803_PUZZLE_PROTOCOL_VERSION_LENGTH\t 8\n+#define IEI_WT61P803_PUZZLE_NB_MAC\t\t\t 8\n+\n+/* Use HZ as a timeout value throughout the driver */\n+#define IEI_WT61P803_PUZZLE_GENERAL_TIMEOUT HZ\n+\n+enum iei_wt61p803_puzzle_attribute_type {\n+\tIEI_WT61P803_PUZZLE_VERSION,\n+\tIEI_WT61P803_PUZZLE_BUILD_INFO,\n+\tIEI_WT61P803_PUZZLE_BOOTLOADER_MODE,\n+\tIEI_WT61P803_PUZZLE_PROTOCOL_VERSION,\n+\tIEI_WT61P803_PUZZLE_SERIAL_NUMBER,\n+\tIEI_WT61P803_PUZZLE_MAC_ADDRESS,\n+\tIEI_WT61P803_PUZZLE_AC_RECOVERY_STATUS,\n+\tIEI_WT61P803_PUZZLE_POWER_LOSS_RECOVERY,\n+\tIEI_WT61P803_PUZZLE_POWER_STATUS,\n+};\n+\n+struct iei_wt61p803_puzzle_device_attribute {\n+\tstruct device_attribute dev_attr;\n+\tenum iei_wt61p803_puzzle_attribute_type type;\n+\tu8 index;\n+};\n+\n+/**\n+ * struct iei_wt61p803_puzzle_mcu_status - MCU flags state\n+ * @ac_recovery_status_flag:\tAC Recovery Status Flag\n+ * @power_loss_recovery:\tSystem recovery after power loss\n+ * @power_status:\t\tSystem Power-on Method\n+ */\n+struct iei_wt61p803_puzzle_mcu_status {\n+\tu8 ac_recovery_status_flag;\n+\tu8 power_loss_recovery;\n+\tu8 power_status;\n+};\n+\n+/**\n+ * struct iei_wt61p803_puzzle_reply - MCU reply\n+ * @size:\tSize of the MCU reply\n+ * @data:\tFull MCU reply buffer\n+ * @state:\tCurrent state of the packet\n+ * @received:\tWas the response fullfilled\n+ */\n+struct iei_wt61p803_puzzle_reply {\n+\tsize_t size;\n+\tunsigned char data[IEI_WT61P803_PUZZLE_RESP_BUF_SIZE];\n+\tstruct completion received;\n+};\n+\n+/**\n+ * struct iei_wt61p803_puzzle_mcu_version - MCU version status\n+ * @version:\t\tPrimary firmware version\n+ * @build_info:\t\tBuild date and time\n+ * @bootloader_mode:\tStatus of the MCU operation\n+ * @protocol_version:\tMCU communication protocol version\n+ * @serial_number:\tDevice factory serial number\n+ * @mac_address:\tDevice factory MAC addresses\n+ *\n+ * Last element of arrays is reserved for '\\0'.\n+ */\n+struct iei_wt61p803_puzzle_mcu_version {\n+\tchar version[IEI_WT61P803_PUZZLE_VERSION_LENGTH + 1];\n+\tchar build_info[IEI_WT61P803_PUZZLE_BUILD_INFO_LENGTH + 1];\n+\tbool bootloader_mode;\n+\tchar protocol_version[IEI_WT61P803_PUZZLE_PROTOCOL_VERSION_LENGTH + 1];\n+\tchar serial_number[IEI_WT61P803_PUZZLE_SN_LENGTH + 1];\n+\tchar mac_address[IEI_WT61P803_PUZZLE_NB_MAC][IEI_WT61P803_PUZZLE_MAC_LENGTH + 1];\n+};\n+\n+/**\n+ * struct iei_wt61p803_puzzle - IEI WT61P803 PUZZLE MCU Driver\n+ * @serdev:\t\tPointer to underlying serdev device\n+ * @dev:\t\tPointer to underlying dev device\n+ * @reply_lock:\t\tReply mutex lock\n+ * @reply:\t\tPointer to the iei_wt61p803_puzzle_reply struct\n+ * @version:\t\tMCU version related data\n+ * @status:\t\tMCU status related data\n+ * @response_buffer\tCommand response buffer allocation\n+ * @lock\t\tGeneral member mutex lock\n+ */\n+struct iei_wt61p803_puzzle {\n+\tstruct serdev_device *serdev;\n+\tstruct device *dev;\n+\tstruct mutex reply_lock; /* lock to prevent multiple firmware calls */\n+\tstruct iei_wt61p803_puzzle_reply *reply;\n+\tstruct iei_wt61p803_puzzle_mcu_version version;\n+\tstruct iei_wt61p803_puzzle_mcu_status status;\n+\tunsigned char response_buffer[IEI_WT61P803_PUZZLE_BUF_SIZE];\n+\tstruct mutex lock; /* lock to protect response buffer */\n+};\n+\n+static unsigned char iei_wt61p803_puzzle_checksum(unsigned char *buf, size_t len)\n+{\n+\tunsigned char checksum = 0;\n+\tsize_t i;\n+\n+\tfor (i = 0; i < len; i++)\n+\t\tchecksum ^= buf[i];\n+\treturn checksum;\n+}\n+\n+static int iei_wt61p803_puzzle_process_resp(struct iei_wt61p803_puzzle *mcu,\n+\t\t\t\t\t    const unsigned char *raw_resp_data, size_t size)\n+{\n+\tunsigned char checksum;\n+\n+\t/* Check the incoming frame header */\n+\tif (!(raw_resp_data[0] == IEI_WT61P803_PUZZLE_CMD_HEADER_START ||\n+\t      raw_resp_data[0] == IEI_WT61P803_PUZZLE_CMD_HEADER_START_OTHER ||\n+\t     (raw_resp_data[0] == IEI_WT61P803_PUZZLE_CMD_HEADER_EEPROM &&\n+\t      raw_resp_data[1] == IEI_WT61P803_PUZZLE_CMD_EEPROM_READ))) {\n+\t\tif (mcu->reply->size + size >= sizeof(mcu->reply->data))\n+\t\t\treturn -EIO;\n+\n+\t\t/* Append the frame to existing data */\n+\t\tmemcpy(mcu->reply->data + mcu->reply->size, raw_resp_data, size);\n+\t\tmcu->reply->size += size;\n+\t} else {\n+\t\tif (size >= sizeof(mcu->reply->data))\n+\t\t\treturn -EIO;\n+\n+\t\t/* Start processing a new frame */\n+\t\tmemcpy(mcu->reply->data, raw_resp_data, size);\n+\t\tmcu->reply->size = size;\n+\t}\n+\n+\tchecksum = iei_wt61p803_puzzle_checksum(mcu->reply->data, mcu->reply->size - 1);\n+\tif (checksum != mcu->reply->data[mcu->reply->size - 1]) {\n+\t\t/* The checksum isn't matched yet, wait for new frames */\n+\t\treturn size;\n+\t}\n+\n+\t/* Received all the data */\n+\tcomplete(&mcu->reply->received);\n+\n+\treturn size;\n+}\n+\n+static int iei_wt61p803_puzzle_recv_buf(struct serdev_device *serdev,\n+\t\t\t\t\tconst unsigned char *data, size_t size)\n+{\n+\tstruct iei_wt61p803_puzzle *mcu = serdev_device_get_drvdata(serdev);\n+\tint ret;\n+\n+\tret = iei_wt61p803_puzzle_process_resp(mcu, data, size);\n+\t/* Return the number of processed bytes if function returns error,\n+\t * discard the remaining incoming data, since the frame this data\n+\t * belongs to is broken anyway\n+\t */\n+\tif (ret < 0)\n+\t\treturn size;\n+\n+\treturn ret;\n+}\n+\n+static const struct serdev_device_ops iei_wt61p803_puzzle_serdev_device_ops = {\n+\t.receive_buf  = iei_wt61p803_puzzle_recv_buf,\n+\t.write_wakeup = serdev_device_write_wakeup,\n+};\n+\n+/**\n+ * iei_wt61p803_puzzle_write_command_watchdog() - Watchdog of the normal cmd\n+ * @mcu: Pointer to the iei_wt61p803_puzzle core MFD struct\n+ * @cmd: Pointer to the char array to send (size should be content + 1 (xor))\n+ * @size: Size of the cmd char array\n+ * @reply_data: Pointer to the reply/response data array (should be allocated)\n+ * @reply_size: Pointer to size_t (size of reply_data)\n+ * @retry_count: Number of times to retry sending the command to the MCU\n+ */\n+int iei_wt61p803_puzzle_write_command_watchdog(struct iei_wt61p803_puzzle *mcu,\n+\t\t\t\t\t       unsigned char *cmd, size_t size,\n+\t\t\t\t\t       unsigned char *reply_data,\n+\t\t\t\t\t       size_t *reply_size, int retry_count)\n+{\n+\tstruct device *dev = &mcu->serdev->dev;\n+\tint ret, i;\n+\n+\tfor (i = 0; i < retry_count; i++) {\n+\t\tret = iei_wt61p803_puzzle_write_command(mcu, cmd, size,\n+\t\t\t\t\t\t\treply_data, reply_size);\n+\t\tif (ret != -ETIMEDOUT)\n+\t\t\treturn ret;\n+\t}\n+\n+\tdev_err(dev, \"Command response timed out. Retries: %d\\n\", retry_count);\n+\n+\treturn -ETIMEDOUT;\n+}\n+EXPORT_SYMBOL_GPL(iei_wt61p803_puzzle_write_command_watchdog);\n+\n+/**\n+ * iei_wt61p803_puzzle_write_command() - Send a structured command to the MCU\n+ * @mcu: Pointer to the iei_wt61p803_puzzle core MFD struct\n+ * @cmd: Pointer to the char array to send (size should be content + 1 (xor))\n+ * @size: Size of the cmd char array\n+ * @reply_data: Pointer to the reply/response data array (should be allocated)\n+ *\n+ * Sends a structured command to the MCU.\n+ */\n+int iei_wt61p803_puzzle_write_command(struct iei_wt61p803_puzzle *mcu,\n+\t\t\t\t      unsigned char *cmd, size_t size,\n+\t\t\t\t      unsigned char *reply_data,\n+\t\t\t\t      size_t *reply_size)\n+{\n+\tstruct device *dev = &mcu->serdev->dev;\n+\tint ret;\n+\n+\tif (size <= 1 || size > IEI_WT61P803_PUZZLE_MAX_COMMAND_LENGTH)\n+\t\treturn -EINVAL;\n+\n+\tmutex_lock(&mcu->reply_lock);\n+\n+\tcmd[size - 1] = iei_wt61p803_puzzle_checksum(cmd, size - 1);\n+\n+\t/* Initialize reply struct */\n+\treinit_completion(&mcu->reply->received);\n+\tmcu->reply->size = 0;\n+\tusleep_range(2000, 10000);\n+\tserdev_device_write_flush(mcu->serdev);\n+\tret = serdev_device_write_buf(mcu->serdev, cmd, size);\n+\tif (ret < 0)\n+\t\tgoto exit;\n+\n+\tserdev_device_wait_until_sent(mcu->serdev, IEI_WT61P803_PUZZLE_GENERAL_TIMEOUT);\n+\tret = wait_for_completion_timeout(&mcu->reply->received,\n+\t\t\t\t\t  IEI_WT61P803_PUZZLE_GENERAL_TIMEOUT);\n+\tif (ret == 0) {\n+\t\tdev_err(dev, \"Command reply receive timeout\\n\");\n+\t\tret = -ETIMEDOUT;\n+\t\tgoto exit;\n+\t}\n+\n+\t*reply_size = mcu->reply->size;\n+\t/* Copy the received data, as it will not be available after a new frame is received */\n+\tmemcpy(reply_data, mcu->reply->data, mcu->reply->size);\n+\tret = 0;\n+exit:\n+\tmutex_unlock(&mcu->reply_lock);\n+\treturn ret;\n+}\n+EXPORT_SYMBOL_GPL(iei_wt61p803_puzzle_write_command);\n+\n+static int iei_wt61p803_puzzle_buzzer(struct iei_wt61p803_puzzle *mcu, bool long_beep)\n+{\n+\tunsigned char *resp_buf = mcu->response_buffer;\n+\tunsigned char buzzer_cmd[4] = {};\n+\tsize_t reply_size;\n+\tint ret;\n+\n+\tbuzzer_cmd[0] = IEI_WT61P803_PUZZLE_CMD_HEADER_START;\n+\tbuzzer_cmd[1] = IEI_WT61P803_PUZZLE_CMD_FUNCTION_SINGLE;\n+\tbuzzer_cmd[2] = long_beep ? '3' : '2'; /* Buzzer 1.5 / 0.5 second beep */\n+\n+\tmutex_lock(&mcu->lock);\n+\tret = iei_wt61p803_puzzle_write_command(mcu, buzzer_cmd, sizeof(buzzer_cmd),\n+\t\t\t\t\t\tresp_buf, &reply_size);\n+\tif (ret)\n+\t\tgoto exit;\n+\n+\tif (reply_size != 3) {\n+\t\tret = -EIO;\n+\t\tgoto exit;\n+\t}\n+\n+\tif (!(resp_buf[0] == IEI_WT61P803_PUZZLE_CMD_HEADER_START &&\n+\t      resp_buf[1] == IEI_WT61P803_PUZZLE_CMD_RESPONSE_OK &&\n+\t      resp_buf[2] == IEI_WT61P803_PUZZLE_CHECKSUM_RESPONSE_OK)) {\n+\t\tret = -EPROTO;\n+\t\tgoto exit;\n+\t}\n+exit:\n+\tmutex_unlock(&mcu->lock);\n+\treturn ret;\n+}\n+\n+static int iei_wt61p803_puzzle_get_version(struct iei_wt61p803_puzzle *mcu)\n+{\n+\tunsigned char version_cmd[3] = {\n+\t\tIEI_WT61P803_PUZZLE_CMD_HEADER_START_OTHER,\n+\t\tIEI_WT61P803_PUZZLE_CMD_OTHER_VERSION,\n+\t};\n+\tunsigned char build_info_cmd[3] = {\n+\t\tIEI_WT61P803_PUZZLE_CMD_HEADER_START_OTHER,\n+\t\tIEI_WT61P803_PUZZLE_CMD_OTHER_BUILD,\n+\t};\n+\tunsigned char bootloader_mode_cmd[3] = {\n+\t\tIEI_WT61P803_PUZZLE_CMD_HEADER_START_OTHER,\n+\t\tIEI_WT61P803_PUZZLE_CMD_OTHER_BOOTLOADER_MODE,\n+\t};\n+\tunsigned char protocol_version_cmd[3] = {\n+\t\tIEI_WT61P803_PUZZLE_CMD_HEADER_START_OTHER,\n+\t\tIEI_WT61P803_PUZZLE_CMD_OTHER_PROTOCOL_VERSION,\n+\t};\n+\tunsigned char *rb = mcu->response_buffer;\n+\tsize_t reply_size;\n+\tint ret;\n+\n+\tmutex_lock(&mcu->lock);\n+\n+\tret = iei_wt61p803_puzzle_write_command(mcu, version_cmd, sizeof(version_cmd),\n+\t\t\t\t\t\trb, &reply_size);\n+\tif (ret)\n+\t\tgoto err;\n+\tif (reply_size < 7) {\n+\t\tret = -EIO;\n+\t\tgoto err;\n+\t}\n+\tsprintf(mcu->version.version, \"v%c.%.3s\", rb[2], &rb[3]);\n+\n+\tret = iei_wt61p803_puzzle_write_command(mcu, build_info_cmd,\n+\t\t\t\t\t\tsizeof(build_info_cmd),\trb,\n+\t\t\t\t\t\t&reply_size);\n+\tif (ret)\n+\t\tgoto err;\n+\tif (reply_size < 15) {\n+\t\tret = -EIO;\n+\t\tgoto err;\n+\t}\n+\tsprintf(mcu->version.build_info, \"%c%c/%c%c/%.4s %c%c:%c%c\",\n+\t\trb[8], rb[9], rb[6], rb[7], &rb[2], rb[10], rb[11],\n+\t\trb[12], rb[13]);\n+\n+\tret = iei_wt61p803_puzzle_write_command(mcu, bootloader_mode_cmd,\n+\t\t\t\t\t\tsizeof(bootloader_mode_cmd), rb,\n+\t\t\t\t\t\t&reply_size);\n+\tif (ret)\n+\t\tgoto err;\n+\tif (reply_size < 4) {\n+\t\tret = -EIO;\n+\t\tgoto err;\n+\t}\n+\tif (rb[2] == IEI_WT61P803_PUZZLE_CMD_OTHER_MODE_APPS)\n+\t\tmcu->version.bootloader_mode = false;\n+\telse if (rb[2] == IEI_WT61P803_PUZZLE_CMD_OTHER_MODE_BOOTLOADER)\n+\t\tmcu->version.bootloader_mode = true;\n+\n+\tret = iei_wt61p803_puzzle_write_command(mcu, protocol_version_cmd,\n+\t\t\t\t\t\tsizeof(protocol_version_cmd), rb,\n+\t\t\t\t\t\t&reply_size);\n+\tif (ret)\n+\t\tgoto err;\n+\tif (reply_size < 9) {\n+\t\tret = -EIO;\n+\t\tgoto err;\n+\t}\n+\tsprintf(mcu->version.protocol_version, \"v%c.%c%c%c%c%c\",\n+\t\trb[7], rb[6], rb[5], rb[4], rb[3], rb[2]);\n+err:\n+\tmutex_unlock(&mcu->lock);\n+\treturn ret;\n+}\n+\n+static int iei_wt61p803_puzzle_get_mcu_status(struct iei_wt61p803_puzzle *mcu)\n+{\n+\tunsigned char mcu_status_cmd[5] = {\n+\t\tIEI_WT61P803_PUZZLE_CMD_HEADER_START,\n+\t\tIEI_WT61P803_PUZZLE_CMD_FUNCTION_OTHER,\n+\t\tIEI_WT61P803_PUZZLE_CMD_FUNCTION_OTHER_STATUS,\n+\t\tIEI_WT61P803_PUZZLE_CMD_FUNCTION_OTHER_STATUS,\n+\t};\n+\tunsigned char *resp_buf = mcu->response_buffer;\n+\tsize_t reply_size;\n+\tint ret;\n+\n+\tmutex_lock(&mcu->lock);\n+\tret = iei_wt61p803_puzzle_write_command(mcu, mcu_status_cmd, sizeof(mcu_status_cmd),\n+\t\t\t\t\t\tresp_buf, &reply_size);\n+\tif (ret)\n+\t\tgoto exit;\n+\tif (reply_size < 20) {\n+\t\tret = -EIO;\n+\t\tgoto exit;\n+\t}\n+\n+\t/* Response format:\n+\t * (IDX\tRESPONSE)\n+\t * 0\t@\n+\t * 1\tO\n+\t * 2\tS\n+\t * 3\tS\n+\t * ...\n+\t * 5\tAC Recovery Status Flag\n+\t * ...\n+\t * 10\tPower Loss Recovery\n+\t * ...\n+\t * 19\tPower Status (system power on method)\n+\t * 20\tXOR checksum\n+\t */\n+\tif (resp_buf[0] == IEI_WT61P803_PUZZLE_CMD_HEADER_START &&\n+\t    resp_buf[1] == IEI_WT61P803_PUZZLE_CMD_FUNCTION_OTHER &&\n+\t    resp_buf[2] == IEI_WT61P803_PUZZLE_CMD_FUNCTION_OTHER_STATUS &&\n+\t    resp_buf[3] == IEI_WT61P803_PUZZLE_CMD_FUNCTION_OTHER_STATUS) {\n+\t\tmcu->status.ac_recovery_status_flag = resp_buf[5];\n+\t\tmcu->status.power_loss_recovery = resp_buf[10];\n+\t\tmcu->status.power_status = resp_buf[19];\n+\t}\n+exit:\n+\tmutex_unlock(&mcu->lock);\n+\treturn ret;\n+}\n+\n+static int iei_wt61p803_puzzle_get_serial_number(struct iei_wt61p803_puzzle *mcu)\n+{\n+\tunsigned char *resp_buf = mcu->response_buffer;\n+\tunsigned char serial_number_cmd[5] = {\n+\t\tIEI_WT61P803_PUZZLE_CMD_HEADER_EEPROM,\n+\t\tIEI_WT61P803_PUZZLE_CMD_EEPROM_READ,\n+\t\t0x00,\t/* EEPROM read address */\n+\t\t0x24,\t/* Data length */\n+\t};\n+\tsize_t reply_size;\n+\tint ret;\n+\n+\tmutex_lock(&mcu->lock);\n+\tret = iei_wt61p803_puzzle_write_command(mcu, serial_number_cmd,\n+\t\t\t\t\t\tsizeof(serial_number_cmd),\n+\t\t\t\t\t\tresp_buf, &reply_size);\n+\tif (ret)\n+\t\tgoto err;\n+\n+\tif (reply_size < IEI_WT61P803_PUZZLE_SN_LENGTH + 4) {\n+\t\tret = -EIO;\n+\t\tgoto err;\n+\t}\n+\n+\tsprintf(mcu->version.serial_number, \"%.*s\",\n+\t\tIEI_WT61P803_PUZZLE_SN_LENGTH, resp_buf + 4);\n+err:\n+\tmutex_unlock(&mcu->lock);\n+\treturn ret;\n+}\n+\n+static int iei_wt61p803_puzzle_write_serial_number(struct iei_wt61p803_puzzle *mcu,\n+\t\t\t\t\t\t   unsigned char serial_number[36])\n+{\n+\tunsigned char *resp_buf = mcu->response_buffer;\n+\tunsigned char serial_number_header[4] = {\n+\t\tIEI_WT61P803_PUZZLE_CMD_HEADER_EEPROM,\n+\t\tIEI_WT61P803_PUZZLE_CMD_EEPROM_WRITE,\n+\t\t0x00,\t/* EEPROM write address */\n+\t\t0xC,\t/* Data length */\n+\t};\n+\tunsigned char serial_number_cmd[4 + 12 + 1]; /* header, serial number, XOR checksum */\n+\tint ret, sn_counter;\n+\tsize_t reply_size;\n+\n+\t/* The MCU can only handle 22 byte messages, send the S/N in 12 byte chunks */\n+\tmutex_lock(&mcu->lock);\n+\tfor (sn_counter = 0; sn_counter < 3; sn_counter++) {\n+\t\tserial_number_header[2] = 0x0 + 0xC * sn_counter;\n+\n+\t\tmemcpy(serial_number_cmd, serial_number_header, sizeof(serial_number_header));\n+\t\tmemcpy(serial_number_cmd + sizeof(serial_number_header),\n+\t\t       serial_number + 0xC * sn_counter, 0xC);\n+\n+\t\tret = iei_wt61p803_puzzle_write_command(mcu, serial_number_cmd,\n+\t\t\t\t\t\t\tsizeof(serial_number_cmd),\n+\t\t\t\t\t\t\tresp_buf, &reply_size);\n+\t\tif (ret)\n+\t\t\tgoto err;\n+\t\tif (reply_size != 3) {\n+\t\t\tret = -EIO;\n+\t\t\tgoto err;\n+\t\t}\n+\t\tif (!(resp_buf[0] == IEI_WT61P803_PUZZLE_CMD_HEADER_START &&\n+\t\t      resp_buf[1] == IEI_WT61P803_PUZZLE_CMD_RESPONSE_OK &&\n+\t\t      resp_buf[2] == IEI_WT61P803_PUZZLE_CHECKSUM_RESPONSE_OK)) {\n+\t\t\tret = -EPROTO;\n+\t\t\tgoto err;\n+\t\t}\n+\t}\n+\n+\tsprintf(mcu->version.serial_number, \"%.*s\",\n+\t\tIEI_WT61P803_PUZZLE_SN_LENGTH, serial_number);\n+err:\n+\tmutex_unlock(&mcu->lock);\n+\treturn ret;\n+}\n+\n+static int iei_wt61p803_puzzle_get_mac_address(struct iei_wt61p803_puzzle *mcu, int index)\n+{\n+\tunsigned char *resp_buf = mcu->response_buffer;\n+\tunsigned char mac_address_cmd[5] = {\n+\t\tIEI_WT61P803_PUZZLE_CMD_HEADER_EEPROM,\n+\t\tIEI_WT61P803_PUZZLE_CMD_EEPROM_READ,\n+\t\t0x00,\t/* EEPROM read address */\n+\t\t0x11,\t/* Data length */\n+\t};\n+\tsize_t reply_size;\n+\tint ret;\n+\n+\tmutex_lock(&mcu->lock);\n+\tmac_address_cmd[2] = 0x24 + 0x11 * index;\n+\n+\tret = iei_wt61p803_puzzle_write_command(mcu, mac_address_cmd,\n+\t\t\t\t\t\tsizeof(mac_address_cmd),\n+\t\t\t\t\t\tresp_buf, &reply_size);\n+\tif (ret)\n+\t\tgoto err;\n+\n+\tif (reply_size < 22) {\n+\t\tret = -EIO;\n+\t\tgoto err;\n+\t}\n+\n+\tsprintf(mcu->version.mac_address[index], \"%.*s\",\n+\t\tIEI_WT61P803_PUZZLE_MAC_LENGTH, resp_buf + 4);\n+err:\n+\tmutex_unlock(&mcu->lock);\n+\treturn ret;\n+}\n+\n+static int\n+iei_wt61p803_puzzle_write_mac_address(struct iei_wt61p803_puzzle *mcu,\n+\t\t\t\t      unsigned char mac_address[IEI_WT61P803_PUZZLE_MAC_LENGTH],\n+\t\t\t\t      int mac_address_idx)\n+{\n+\tunsigned char mac_address_cmd[4 + IEI_WT61P803_PUZZLE_MAC_LENGTH + 1];\n+\tunsigned char *resp_buf = mcu->response_buffer;\n+\tunsigned char mac_address_header[4] = {\n+\t\tIEI_WT61P803_PUZZLE_CMD_HEADER_EEPROM,\n+\t\tIEI_WT61P803_PUZZLE_CMD_EEPROM_WRITE,\n+\t\t0x00,\t/* EEPROM write address */\n+\t\t0x11,\t/* Data length */\n+\t};\n+\tsize_t reply_size;\n+\tint ret;\n+\n+\tif (mac_address_idx < 0 || mac_address_idx >= IEI_WT61P803_PUZZLE_NB_MAC)\n+\t\treturn -EINVAL;\n+\n+\tmac_address_header[2] = 0x24 + 0x11 * mac_address_idx;\n+\n+\t/* Concat mac_address_header, mac_address to mac_address_cmd */\n+\tmemcpy(mac_address_cmd, mac_address_header, sizeof(mac_address_header));\n+\tmemcpy(mac_address_cmd + sizeof(mac_address_header), mac_address,\n+\t       IEI_WT61P803_PUZZLE_MAC_LENGTH);\n+\n+\tmutex_lock(&mcu->lock);\n+\tret = iei_wt61p803_puzzle_write_command(mcu, mac_address_cmd,\n+\t\t\t\t\t\tsizeof(mac_address_cmd),\n+\t\t\t\t\t\tresp_buf, &reply_size);\n+\tif (ret)\n+\t\tgoto err;\n+\tif (reply_size != 3) {\n+\t\tret = -EIO;\n+\t\tgoto err;\n+\t}\n+\tif (!(resp_buf[0] == IEI_WT61P803_PUZZLE_CMD_HEADER_START &&\n+\t      resp_buf[1] == IEI_WT61P803_PUZZLE_CMD_RESPONSE_OK &&\n+\t      resp_buf[2] == IEI_WT61P803_PUZZLE_CHECKSUM_RESPONSE_OK)) {\n+\t\tret = -EPROTO;\n+\t\tgoto err;\n+\t}\n+\n+\tsprintf(mcu->version.mac_address[mac_address_idx], \"%.*s\",\n+\t\tIEI_WT61P803_PUZZLE_MAC_LENGTH, mac_address);\n+err:\n+\tmutex_unlock(&mcu->lock);\n+\treturn ret;\n+}\n+\n+static int iei_wt61p803_puzzle_write_power_loss_recovery(struct iei_wt61p803_puzzle *mcu,\n+\t\t\t\t\t\t\t int power_loss_recovery_action)\n+{\n+\tunsigned char *resp_buf = mcu->response_buffer;\n+\tunsigned char power_loss_recovery_cmd[5] = {};\n+\tsize_t reply_size;\n+\tint ret;\n+\n+\tif (power_loss_recovery_action < 0 || power_loss_recovery_action > 4)\n+\t\treturn -EINVAL;\n+\n+\tpower_loss_recovery_cmd[0] = IEI_WT61P803_PUZZLE_CMD_HEADER_START;\n+\tpower_loss_recovery_cmd[1] = IEI_WT61P803_PUZZLE_CMD_FUNCTION_OTHER;\n+\tpower_loss_recovery_cmd[2] = IEI_WT61P803_PUZZLE_CMD_FUNCTION_OTHER_POWER_LOSS;\n+\tpower_loss_recovery_cmd[3] = hex_asc[power_loss_recovery_action];\n+\n+\tmutex_lock(&mcu->lock);\n+\tret = iei_wt61p803_puzzle_write_command(mcu, power_loss_recovery_cmd,\n+\t\t\t\t\t\tsizeof(power_loss_recovery_cmd),\n+\t\t\t\t\t\tresp_buf, &reply_size);\n+\tif (ret)\n+\t\tgoto exit;\n+\tmcu->status.power_loss_recovery = power_loss_recovery_action;\n+exit:\n+\tmutex_unlock(&mcu->lock);\n+\treturn ret;\n+}\n+\n+#define to_puzzle_dev_attr(_attr) \\\n+\tcontainer_of(_attr, struct iei_wt61p803_puzzle_device_attribute, dev_attr)\n+\n+static ssize_t show_output(struct device *dev,\n+\t\t\t   struct device_attribute *attr, char *buf)\n+{\n+\tstruct iei_wt61p803_puzzle *mcu = dev_get_drvdata(dev);\n+\tstruct iei_wt61p803_puzzle_device_attribute *pattr = to_puzzle_dev_attr(attr);\n+\tint ret;\n+\n+\tswitch (pattr->type) {\n+\tcase IEI_WT61P803_PUZZLE_VERSION:\n+\t\treturn scnprintf(buf, PAGE_SIZE, \"%s\\n\", mcu->version.version);\n+\tcase IEI_WT61P803_PUZZLE_BUILD_INFO:\n+\t\treturn scnprintf(buf, PAGE_SIZE, \"%s\\n\", mcu->version.build_info);\n+\tcase IEI_WT61P803_PUZZLE_BOOTLOADER_MODE:\n+\t\treturn scnprintf(buf, PAGE_SIZE, \"%d\\n\", mcu->version.bootloader_mode);\n+\tcase IEI_WT61P803_PUZZLE_PROTOCOL_VERSION:\n+\t\treturn scnprintf(buf, PAGE_SIZE, \"%s\\n\", mcu->version.protocol_version);\n+\tcase IEI_WT61P803_PUZZLE_SERIAL_NUMBER:\n+\t\tret = iei_wt61p803_puzzle_get_serial_number(mcu);\n+\t\tif (!ret)\n+\t\t\tret = scnprintf(buf, PAGE_SIZE, \"%s\\n\", mcu->version.serial_number);\n+\t\telse\n+\t\t\tret = 0;\n+\t\treturn ret;\n+\tcase IEI_WT61P803_PUZZLE_MAC_ADDRESS:\n+\t\tret = iei_wt61p803_puzzle_get_mac_address(mcu, pattr->index);\n+\t\tif (!ret)\n+\t\t\tret = scnprintf(buf, PAGE_SIZE, \"%s\\n\",\n+\t\t\t\t\tmcu->version.mac_address[pattr->index]);\n+\t\telse\n+\t\t\tret = 0;\n+\t\treturn ret;\n+\tcase IEI_WT61P803_PUZZLE_AC_RECOVERY_STATUS:\n+\tcase IEI_WT61P803_PUZZLE_POWER_LOSS_RECOVERY:\n+\tcase IEI_WT61P803_PUZZLE_POWER_STATUS:\n+\t\tret = iei_wt61p803_puzzle_get_mcu_status(mcu);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\n+\t\tmutex_lock(&mcu->lock);\n+\t\tswitch (pattr->type) {\n+\t\tcase IEI_WT61P803_PUZZLE_AC_RECOVERY_STATUS:\n+\t\t\tret = scnprintf(buf, PAGE_SIZE, \"%x\\n\",\n+\t\t\t\t\tmcu->status.ac_recovery_status_flag);\n+\t\t\tbreak;\n+\t\tcase IEI_WT61P803_PUZZLE_POWER_LOSS_RECOVERY:\n+\t\t\tret = scnprintf(buf, PAGE_SIZE, \"%x\\n\", mcu->status.power_loss_recovery);\n+\t\t\tbreak;\n+\t\tcase IEI_WT61P803_PUZZLE_POWER_STATUS:\n+\t\t\tret = scnprintf(buf, PAGE_SIZE, \"%x\\n\", mcu->status.power_status);\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tret = 0;\n+\t\t\tbreak;\n+\t\t}\n+\t\tmutex_unlock(&mcu->lock);\n+\t\treturn ret;\n+\tdefault:\n+\t\treturn 0;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static ssize_t store_output(struct device *dev,\n+\t\t\t    struct device_attribute *attr,\n+\t\t\t    const char *buf, size_t len)\n+{\n+\tunsigned char serial_number[IEI_WT61P803_PUZZLE_SN_LENGTH];\n+\tunsigned char mac_address[IEI_WT61P803_PUZZLE_MAC_LENGTH];\n+\tstruct iei_wt61p803_puzzle *mcu = dev_get_drvdata(dev);\n+\tstruct iei_wt61p803_puzzle_device_attribute *pattr = to_puzzle_dev_attr(attr);\n+\tint power_loss_recovery_action = 0;\n+\tint ret;\n+\n+\tswitch (pattr->type) {\n+\tcase IEI_WT61P803_PUZZLE_SERIAL_NUMBER:\n+\t\tif (len != (size_t)(IEI_WT61P803_PUZZLE_SN_LENGTH + 1))\n+\t\t\treturn -EINVAL;\n+\t\tmemcpy(serial_number, buf, sizeof(serial_number));\n+\t\tret = iei_wt61p803_puzzle_write_serial_number(mcu, serial_number);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\t\treturn len;\n+\tcase IEI_WT61P803_PUZZLE_MAC_ADDRESS:\n+\t\tif (len != (size_t)(IEI_WT61P803_PUZZLE_MAC_LENGTH + 1))\n+\t\t\treturn -EINVAL;\n+\n+\t\tmemcpy(mac_address, buf, sizeof(mac_address));\n+\n+\t\tif (strlen(attr->attr.name) != 13)\n+\t\t\treturn -EIO;\n+\n+\t\tret = iei_wt61p803_puzzle_write_mac_address(mcu, mac_address, pattr->index);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\t\treturn len;\n+\tcase IEI_WT61P803_PUZZLE_POWER_LOSS_RECOVERY:\n+\t\tret = kstrtoint(buf, 10, &power_loss_recovery_action);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\t\tret = iei_wt61p803_puzzle_write_power_loss_recovery(mcu,\n+\t\t\t\t\t\t\t\t    power_loss_recovery_action);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\t\treturn len;\n+\tdefault:\n+\t\treturn -EINVAL;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+#define IEI_WT61P803_PUZZLE_ATTR(_name, _mode, _show, _store, _type, _index) \\\n+\tstruct iei_wt61p803_puzzle_device_attribute dev_attr_##_name = \\\n+\t\t{ .dev_attr\t= __ATTR(_name, _mode, _show, _store), \\\n+\t\t  .type\t\t= _type, \\\n+\t\t  .index\t= _index }\n+\n+#define IEI_WT61P803_PUZZLE_ATTR_RO(_name, _type, _id) \\\n+\tIEI_WT61P803_PUZZLE_ATTR(_name, 0444, show_output, NULL, _type, _id)\n+\n+#define IEI_WT61P803_PUZZLE_ATTR_RW(_name, _type, _id) \\\n+\tIEI_WT61P803_PUZZLE_ATTR(_name, 0644, show_output, store_output, _type, _id)\n+\n+static IEI_WT61P803_PUZZLE_ATTR_RO(version, IEI_WT61P803_PUZZLE_VERSION, 0);\n+static IEI_WT61P803_PUZZLE_ATTR_RO(build_info, IEI_WT61P803_PUZZLE_BUILD_INFO, 0);\n+static IEI_WT61P803_PUZZLE_ATTR_RO(bootloader_mode, IEI_WT61P803_PUZZLE_BOOTLOADER_MODE, 0);\n+static IEI_WT61P803_PUZZLE_ATTR_RO(protocol_version, IEI_WT61P803_PUZZLE_PROTOCOL_VERSION, 0);\n+static IEI_WT61P803_PUZZLE_ATTR_RW(serial_number, IEI_WT61P803_PUZZLE_SERIAL_NUMBER, 0);\n+static IEI_WT61P803_PUZZLE_ATTR_RW(mac_address_0, IEI_WT61P803_PUZZLE_MAC_ADDRESS, 0);\n+static IEI_WT61P803_PUZZLE_ATTR_RW(mac_address_1, IEI_WT61P803_PUZZLE_MAC_ADDRESS, 1);\n+static IEI_WT61P803_PUZZLE_ATTR_RW(mac_address_2, IEI_WT61P803_PUZZLE_MAC_ADDRESS, 2);\n+static IEI_WT61P803_PUZZLE_ATTR_RW(mac_address_3, IEI_WT61P803_PUZZLE_MAC_ADDRESS, 3);\n+static IEI_WT61P803_PUZZLE_ATTR_RW(mac_address_4, IEI_WT61P803_PUZZLE_MAC_ADDRESS, 4);\n+static IEI_WT61P803_PUZZLE_ATTR_RW(mac_address_5, IEI_WT61P803_PUZZLE_MAC_ADDRESS, 5);\n+static IEI_WT61P803_PUZZLE_ATTR_RW(mac_address_6, IEI_WT61P803_PUZZLE_MAC_ADDRESS, 6);\n+static IEI_WT61P803_PUZZLE_ATTR_RW(mac_address_7, IEI_WT61P803_PUZZLE_MAC_ADDRESS, 7);\n+static IEI_WT61P803_PUZZLE_ATTR_RO(ac_recovery_status, IEI_WT61P803_PUZZLE_AC_RECOVERY_STATUS, 0);\n+static IEI_WT61P803_PUZZLE_ATTR_RW(power_loss_recovery, IEI_WT61P803_PUZZLE_POWER_LOSS_RECOVERY, 0);\n+static IEI_WT61P803_PUZZLE_ATTR_RO(power_status, IEI_WT61P803_PUZZLE_POWER_STATUS, 0);\n+\n+static struct attribute *iei_wt61p803_puzzle_attrs[] = {\n+\t&dev_attr_version.dev_attr.attr,\n+\t&dev_attr_build_info.dev_attr.attr,\n+\t&dev_attr_bootloader_mode.dev_attr.attr,\n+\t&dev_attr_protocol_version.dev_attr.attr,\n+\t&dev_attr_serial_number.dev_attr.attr,\n+\t&dev_attr_mac_address_0.dev_attr.attr,\n+\t&dev_attr_mac_address_1.dev_attr.attr,\n+\t&dev_attr_mac_address_2.dev_attr.attr,\n+\t&dev_attr_mac_address_3.dev_attr.attr,\n+\t&dev_attr_mac_address_4.dev_attr.attr,\n+\t&dev_attr_mac_address_5.dev_attr.attr,\n+\t&dev_attr_mac_address_6.dev_attr.attr,\n+\t&dev_attr_mac_address_7.dev_attr.attr,\n+\t&dev_attr_ac_recovery_status.dev_attr.attr,\n+\t&dev_attr_power_loss_recovery.dev_attr.attr,\n+\t&dev_attr_power_status.dev_attr.attr,\n+\tNULL\n+};\n+ATTRIBUTE_GROUPS(iei_wt61p803_puzzle);\n+\n+static int iei_wt61p803_puzzle_sysfs_create(struct device *dev,\n+\t\t\t\t\t    struct iei_wt61p803_puzzle *mcu)\n+{\n+\tint ret;\n+\n+\tret = sysfs_create_groups(&mcu->dev->kobj, iei_wt61p803_puzzle_groups);\n+\tif (ret)\n+\t\tmfd_remove_devices(mcu->dev);\n+\n+\treturn ret;\n+}\n+\n+static int iei_wt61p803_puzzle_sysfs_remove(struct device *dev,\n+\t\t\t\t\t    struct iei_wt61p803_puzzle *mcu)\n+{\n+\t/* Remove sysfs groups */\n+\tsysfs_remove_groups(&mcu->dev->kobj, iei_wt61p803_puzzle_groups);\n+\tmfd_remove_devices(mcu->dev);\n+\n+\treturn 0;\n+}\n+\n+static int iei_wt61p803_puzzle_probe(struct serdev_device *serdev)\n+{\n+\tstruct device *dev = &serdev->dev;\n+\tstruct iei_wt61p803_puzzle *mcu;\n+\tu32 baud;\n+\tint ret;\n+\n+\t/* Read the baud rate from 'current-speed', because the MCU supports different rates */\n+\tif (device_property_read_u32(dev, \"current-speed\", &baud)) {\n+\t\tdev_err(dev,\n+\t\t\t\"'current-speed' is not specified in device node\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\tdev_dbg(dev, \"Driver baud rate: %d\\n\", baud);\n+\n+\t/* Allocate the memory */\n+\tmcu = devm_kzalloc(dev, sizeof(*mcu), GFP_KERNEL);\n+\tif (!mcu)\n+\t\treturn -ENOMEM;\n+\n+\tmcu->reply = devm_kzalloc(dev, sizeof(*mcu->reply), GFP_KERNEL);\n+\tif (!mcu->reply)\n+\t\treturn -ENOMEM;\n+\n+\t/* Initialize device struct data */\n+\tmcu->serdev = serdev;\n+\tmcu->dev = dev;\n+\tinit_completion(&mcu->reply->received);\n+\tmutex_init(&mcu->reply_lock);\n+\tmutex_init(&mcu->lock);\n+\n+\t/* Setup UART interface */\n+\tserdev_device_set_drvdata(serdev, mcu);\n+\tserdev_device_set_client_ops(serdev, &iei_wt61p803_puzzle_serdev_device_ops);\n+\tret = devm_serdev_device_open(dev, serdev);\n+\tif (ret)\n+\t\treturn ret;\n+\tserdev_device_set_baudrate(serdev, baud);\n+\tserdev_device_set_flow_control(serdev, false);\n+\tret = serdev_device_set_parity(serdev, SERDEV_PARITY_NONE);\n+\tif (ret) {\n+\t\tdev_err(dev, \"Failed to set parity\\n\");\n+\t\treturn ret;\n+\t}\n+\n+\tret = iei_wt61p803_puzzle_get_version(mcu);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tdev_dbg(dev, \"MCU version: %s\\n\", mcu->version.version);\n+\tdev_dbg(dev, \"MCU firmware build info: %s\\n\", mcu->version.build_info);\n+\tdev_dbg(dev, \"MCU in bootloader mode: %s\\n\",\n+\t\tmcu->version.bootloader_mode ? \"true\" : \"false\");\n+\tdev_dbg(dev, \"MCU protocol version: %s\\n\", mcu->version.protocol_version);\n+\n+\tif (device_property_read_bool(dev, \"enable-beep\")) {\n+\t\tret = iei_wt61p803_puzzle_buzzer(mcu, false);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\t}\n+\n+\tret = iei_wt61p803_puzzle_sysfs_create(dev, mcu);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\treturn devm_of_platform_populate(dev);\n+}\n+\n+static void iei_wt61p803_puzzle_remove(struct serdev_device *serdev)\n+{\n+\tstruct device *dev = &serdev->dev;\n+\tstruct iei_wt61p803_puzzle *mcu = dev_get_drvdata(dev);\n+\n+\tiei_wt61p803_puzzle_sysfs_remove(dev, mcu);\n+}\n+\n+static const struct of_device_id iei_wt61p803_puzzle_dt_ids[] = {\n+\t{ .compatible = \"iei,wt61p803-puzzle\" },\n+\t{ }\n+};\n+\n+MODULE_DEVICE_TABLE(of, iei_wt61p803_puzzle_dt_ids);\n+\n+static struct serdev_device_driver iei_wt61p803_puzzle_drv = {\n+\t.probe\t\t\t= iei_wt61p803_puzzle_probe,\n+\t.remove\t\t\t= iei_wt61p803_puzzle_remove,\n+\t.driver = {\n+\t\t.name\t\t= \"iei-wt61p803-puzzle\",\n+\t\t.of_match_table\t= iei_wt61p803_puzzle_dt_ids,\n+\t},\n+};\n+\n+module_serdev_device_driver(iei_wt61p803_puzzle_drv);\n+\n+MODULE_LICENSE(\"GPL v2\");\n+MODULE_AUTHOR(\"Luka Kovacic <luka.kovacic@sartura.hr>\");\n+MODULE_DESCRIPTION(\"IEI WT61P803 PUZZLE MCU Driver\");\n--- /dev/null\n+++ b/include/linux/mfd/iei-wt61p803-puzzle.h\n@@ -0,0 +1,66 @@\n+/* SPDX-License-Identifier: GPL-2.0-only */\n+/* IEI WT61P803 PUZZLE MCU Driver\n+ * System management microcontroller for fan control, temperature sensor reading,\n+ * LED control and system identification on IEI Puzzle series ARM-based appliances.\n+ *\n+ * Copyright (C) 2020 Sartura Ltd.\n+ * Author: Luka Kovacic <luka.kovacic@sartura.hr>\n+ */\n+\n+#ifndef _MFD_IEI_WT61P803_PUZZLE_H_\n+#define _MFD_IEI_WT61P803_PUZZLE_H_\n+\n+#define IEI_WT61P803_PUZZLE_BUF_SIZE 512\n+\n+/* Command magic numbers */\n+#define IEI_WT61P803_PUZZLE_CMD_HEADER_START\t\t0x40 /* @ */\n+#define IEI_WT61P803_PUZZLE_CMD_HEADER_START_OTHER\t0x25 /* % */\n+#define IEI_WT61P803_PUZZLE_CMD_HEADER_EEPROM\t\t0xF7\n+\n+#define IEI_WT61P803_PUZZLE_CMD_RESPONSE_OK\t\t0x30 /* 0 */\n+#define IEI_WT61P803_PUZZLE_CHECKSUM_RESPONSE_OK\t0x70\n+\n+#define IEI_WT61P803_PUZZLE_CMD_EEPROM_READ\t\t0xA1\n+#define IEI_WT61P803_PUZZLE_CMD_EEPROM_WRITE\t\t0xA0\n+\n+#define IEI_WT61P803_PUZZLE_CMD_OTHER_VERSION\t\t0x56 /* V */\n+#define IEI_WT61P803_PUZZLE_CMD_OTHER_BUILD\t\t0x42 /* B */\n+#define IEI_WT61P803_PUZZLE_CMD_OTHER_BOOTLOADER_MODE\t0x4D /* M */\n+#define IEI_WT61P803_PUZZLE_CMD_OTHER_MODE_BOOTLOADER\t0x30\n+#define IEI_WT61P803_PUZZLE_CMD_OTHER_MODE_APPS\t\t0x31\n+#define IEI_WT61P803_PUZZLE_CMD_OTHER_PROTOCOL_VERSION\t0x50 /* P */\n+\n+#define IEI_WT61P803_PUZZLE_CMD_FUNCTION_SINGLE\t\t0x43 /* C */\n+#define IEI_WT61P803_PUZZLE_CMD_FUNCTION_OTHER\t\t0x4F /* O */\n+#define IEI_WT61P803_PUZZLE_CMD_FUNCTION_OTHER_STATUS\t0x53 /* S */\n+#define IEI_WT61P803_PUZZLE_CMD_FUNCTION_OTHER_POWER_LOSS 0x41 /* A */\n+\n+#define IEI_WT61P803_PUZZLE_CMD_LED\t\t\t0x52 /* R */\n+#define IEI_WT61P803_PUZZLE_CMD_LED_POWER\t\t0x31 /* 1 */\n+\n+#define IEI_WT61P803_PUZZLE_CMD_TEMP\t\t\t0x54 /* T */\n+#define IEI_WT61P803_PUZZLE_CMD_TEMP_ALL\t\t0x41 /* A */\n+\n+#define IEI_WT61P803_PUZZLE_CMD_FAN\t\t\t0x46 /* F */\n+#define IEI_WT61P803_PUZZLE_CMD_FAN_PWM_READ\t\t0x5A /* Z */\n+#define IEI_WT61P803_PUZZLE_CMD_FAN_PWM_WRITE\t\t0x57 /* W */\n+#define IEI_WT61P803_PUZZLE_CMD_FAN_PWM_BASE\t\t0x30\n+#define IEI_WT61P803_PUZZLE_CMD_FAN_RPM_BASE\t\t0x41 /* A */\n+\n+#define IEI_WT61P803_PUZZLE_CMD_FAN_PWM(x) (IEI_WT61P803_PUZZLE_CMD_FAN_PWM_BASE + (x)) /* 0 - 1 */\n+#define IEI_WT61P803_PUZZLE_CMD_FAN_RPM(x) (IEI_WT61P803_PUZZLE_CMD_FAN_RPM_BASE + (x)) /* 0 - 5 */\n+\n+struct iei_wt61p803_puzzle_mcu_version;\n+struct iei_wt61p803_puzzle_reply;\n+struct iei_wt61p803_puzzle;\n+\n+int iei_wt61p803_puzzle_write_command_watchdog(struct iei_wt61p803_puzzle *mcu,\n+\t\t\t\t\t       unsigned char *cmd, size_t size,\n+\t\t\t\t\t       unsigned char *reply_data, size_t *reply_size,\n+\t\t\t\t\t       int retry_count);\n+\n+int iei_wt61p803_puzzle_write_command(struct iei_wt61p803_puzzle *mcu,\n+\t\t\t\t      unsigned char *cmd, size_t size,\n+\t\t\t\t      unsigned char *reply_data, size_t *reply_size);\n+\n+#endif /* _MFD_IEI_WT61P803_PUZZLE_H_ */\n"
  },
  {
    "path": "target/linux/mvebu/patches-5.10/903-drivers-hwmon-Add-the-IEI-WT61P803-PUZZLE-HWMON-driv.patch",
    "content": "From e3310a638cd310bfd93dbbc6d2732ab6aea18dd2 Mon Sep 17 00:00:00 2001\nFrom: Luka Kovacic <luka.kovacic () sartura ! hr>\nDate: Tue, 24 Aug 2021 12:44:34 +0000\nSubject: [PATCH 3/7] drivers: hwmon: Add the IEI WT61P803 PUZZLE HWMON driver\n\nAdd the IEI WT61P803 PUZZLE HWMON driver, that handles the fan speed\ncontrol via PWM, reading fan speed and reading on-board temperature\nsensors.\n\nThe driver registers a HWMON device and a simple thermal cooling device to\nenable in-kernel fan management.\n\nThis driver depends on the IEI WT61P803 PUZZLE MFD driver.\n\nSigned-off-by: Luka Kovacic <luka.kovacic@sartura.hr>\nSigned-off-by: Pavo Banicevic <pavo.banicevic@sartura.hr>\nAcked-by: Guenter Roeck <linux@roeck-us.net>\nCc: Luka Perkov <luka.perkov@sartura.hr>\nCc: Robert Marko <robert.marko@sartura.hr>\n---\n drivers/hwmon/Kconfig                     |   8 +\n drivers/hwmon/Makefile                    |   1 +\n drivers/hwmon/iei-wt61p803-puzzle-hwmon.c | 413 ++++++++++++++++++++++\n 3 files changed, 422 insertions(+)\n create mode 100644 drivers/hwmon/iei-wt61p803-puzzle-hwmon.c\n\n--- a/drivers/hwmon/Kconfig\n+++ b/drivers/hwmon/Kconfig\n@@ -722,6 +722,14 @@ config SENSORS_IBMPOWERNV\n \t  This driver can also be built as a module. If so, the module\n \t  will be called ibmpowernv.\n \n+config SENSORS_IEI_WT61P803_PUZZLE_HWMON\n+\ttristate \"IEI WT61P803 PUZZLE MFD HWMON Driver\"\n+\tdepends on MFD_IEI_WT61P803_PUZZLE\n+\thelp\n+\t  The IEI WT61P803 PUZZLE MFD HWMON Driver handles reading fan speed\n+\t  and writing fan PWM values. It also supports reading on-board\n+\t  temperature sensors.\n+\n config SENSORS_IIO_HWMON\n \ttristate \"Hwmon driver that uses channels specified via iio maps\"\n \tdepends on IIO\n--- a/drivers/hwmon/Makefile\n+++ b/drivers/hwmon/Makefile\n@@ -83,6 +83,7 @@ obj-$(CONFIG_SENSORS_HIH6130)\t+= hih6130\n obj-$(CONFIG_SENSORS_ULTRA45)\t+= ultra45_env.o\n obj-$(CONFIG_SENSORS_I5500)\t+= i5500_temp.o\n obj-$(CONFIG_SENSORS_I5K_AMB)\t+= i5k_amb.o\n+obj-$(CONFIG_SENSORS_IEI_WT61P803_PUZZLE_HWMON) += iei-wt61p803-puzzle-hwmon.o\n obj-$(CONFIG_SENSORS_IBMAEM)\t+= ibmaem.o\n obj-$(CONFIG_SENSORS_IBMPEX)\t+= ibmpex.o\n obj-$(CONFIG_SENSORS_IBMPOWERNV)+= ibmpowernv.o\n--- /dev/null\n+++ b/drivers/hwmon/iei-wt61p803-puzzle-hwmon.c\n@@ -0,0 +1,413 @@\n+// SPDX-License-Identifier: GPL-2.0-only\n+/* IEI WT61P803 PUZZLE MCU HWMON Driver\n+ *\n+ * Copyright (C) 2020 Sartura Ltd.\n+ * Author: Luka Kovacic <luka.kovacic@sartura.hr>\n+ */\n+\n+#include <linux/err.h>\n+#include <linux/hwmon.h>\n+#include <linux/interrupt.h>\n+#include <linux/irq.h>\n+#include <linux/math64.h>\n+#include <linux/mfd/iei-wt61p803-puzzle.h>\n+#include <linux/mod_devicetable.h>\n+#include <linux/module.h>\n+#include <linux/platform_device.h>\n+#include <linux/property.h>\n+#include <linux/slab.h>\n+#include <linux/thermal.h>\n+\n+#define IEI_WT61P803_PUZZLE_HWMON_MAX_PWM\t2\n+#define IEI_WT61P803_PUZZLE_HWMON_MAX_PWM_VAL\t255\n+\n+/**\n+ * struct iei_wt61p803_puzzle_thermal_cooling_device - Thermal cooling device instance\n+ * @mcu_hwmon:\t\tParent driver struct pointer\n+ * @tcdev:\t\tThermal cooling device pointer\n+ * @name:\t\tThermal cooling device name\n+ * @pwm_channel:\tControlled PWM channel (0 or 1)\n+ * @cooling_levels:\tThermal cooling device cooling levels (DT)\n+ */\n+struct iei_wt61p803_puzzle_thermal_cooling_device {\n+\tstruct iei_wt61p803_puzzle_hwmon *mcu_hwmon;\n+\tstruct thermal_cooling_device *tcdev;\n+\tchar name[THERMAL_NAME_LENGTH];\n+\tint pwm_channel;\n+\tu8 *cooling_levels;\n+};\n+\n+/**\n+ * struct iei_wt61p803_puzzle_hwmon - MCU HWMON Driver\n+ * @mcu:\t\t\t\tMCU struct pointer\n+ * @response_buffer\t\t\tGlobal MCU response buffer\n+ * @thermal_cooling_dev_present:\tPer-channel thermal cooling device control indicator\n+ * @cdev:\t\t\t\tPer-channel thermal cooling device private structure\n+ */\n+struct iei_wt61p803_puzzle_hwmon {\n+\tstruct iei_wt61p803_puzzle *mcu;\n+\tunsigned char response_buffer[IEI_WT61P803_PUZZLE_BUF_SIZE];\n+\tbool thermal_cooling_dev_present[IEI_WT61P803_PUZZLE_HWMON_MAX_PWM];\n+\tstruct iei_wt61p803_puzzle_thermal_cooling_device\n+\t\t*cdev[IEI_WT61P803_PUZZLE_HWMON_MAX_PWM];\n+\tstruct mutex lock; /* mutex to protect response_buffer array */\n+};\n+\n+#define raw_temp_to_milidegree_celsius(x) (((x) - 0x80) * 1000)\n+static int iei_wt61p803_puzzle_read_temp_sensor(struct iei_wt61p803_puzzle_hwmon *mcu_hwmon,\n+\t\t\t\t\t\tint channel, long *value)\n+{\n+\tunsigned char *resp_buf = mcu_hwmon->response_buffer;\n+\tunsigned char temp_sensor_ntc_cmd[4] = {\n+\t\tIEI_WT61P803_PUZZLE_CMD_HEADER_START,\n+\t\tIEI_WT61P803_PUZZLE_CMD_TEMP,\n+\t\tIEI_WT61P803_PUZZLE_CMD_TEMP_ALL,\n+\t};\n+\tsize_t reply_size;\n+\tint ret;\n+\n+\tmutex_lock(&mcu_hwmon->lock);\n+\tret = iei_wt61p803_puzzle_write_command(mcu_hwmon->mcu, temp_sensor_ntc_cmd,\n+\t\t\t\t\t\tsizeof(temp_sensor_ntc_cmd), resp_buf,\n+\t\t\t\t\t\t&reply_size);\n+\tif (ret)\n+\t\tgoto exit;\n+\n+\tif (reply_size != 7) {\n+\t\tret = -EIO;\n+\t\tgoto exit;\n+\t}\n+\n+\t/* Check the number of NTC values */\n+\tif (resp_buf[3] != '2') {\n+\t\tret = -EIO;\n+\t\tgoto exit;\n+\t}\n+\n+\t*value = raw_temp_to_milidegree_celsius(resp_buf[4 + channel]);\n+exit:\n+\tmutex_unlock(&mcu_hwmon->lock);\n+\treturn ret;\n+}\n+\n+#define raw_fan_val_to_rpm(x, y) ((((x) << 8 | (y)) / 2) * 60)\n+static int iei_wt61p803_puzzle_read_fan_speed(struct iei_wt61p803_puzzle_hwmon *mcu_hwmon,\n+\t\t\t\t\t      int channel, long *value)\n+{\n+\tunsigned char *resp_buf = mcu_hwmon->response_buffer;\n+\tunsigned char fan_speed_cmd[4] = {};\n+\tsize_t reply_size;\n+\tint ret;\n+\n+\tfan_speed_cmd[0] = IEI_WT61P803_PUZZLE_CMD_HEADER_START;\n+\tfan_speed_cmd[1] = IEI_WT61P803_PUZZLE_CMD_FAN;\n+\tfan_speed_cmd[2] = IEI_WT61P803_PUZZLE_CMD_FAN_RPM(channel);\n+\n+\tmutex_lock(&mcu_hwmon->lock);\n+\tret = iei_wt61p803_puzzle_write_command(mcu_hwmon->mcu, fan_speed_cmd,\n+\t\t\t\t\t\tsizeof(fan_speed_cmd), resp_buf,\n+\t\t\t\t\t\t&reply_size);\n+\tif (ret)\n+\t\tgoto exit;\n+\n+\tif (reply_size != 7) {\n+\t\tret = -EIO;\n+\t\tgoto exit;\n+\t}\n+\n+\t*value = raw_fan_val_to_rpm(resp_buf[3], resp_buf[4]);\n+exit:\n+\tmutex_unlock(&mcu_hwmon->lock);\n+\treturn ret;\n+}\n+\n+static int iei_wt61p803_puzzle_write_pwm_channel(struct iei_wt61p803_puzzle_hwmon *mcu_hwmon,\n+\t\t\t\t\t\t int channel, long pwm_set_val)\n+{\n+\tunsigned char *resp_buf = mcu_hwmon->response_buffer;\n+\tunsigned char pwm_set_cmd[6] = {};\n+\tsize_t reply_size;\n+\tint ret;\n+\n+\tpwm_set_cmd[0] = IEI_WT61P803_PUZZLE_CMD_HEADER_START;\n+\tpwm_set_cmd[1] = IEI_WT61P803_PUZZLE_CMD_FAN;\n+\tpwm_set_cmd[2] = IEI_WT61P803_PUZZLE_CMD_FAN_PWM_WRITE;\n+\tpwm_set_cmd[3] = IEI_WT61P803_PUZZLE_CMD_FAN_PWM(channel);\n+\tpwm_set_cmd[4] = pwm_set_val;\n+\n+\tmutex_lock(&mcu_hwmon->lock);\n+\tret = iei_wt61p803_puzzle_write_command(mcu_hwmon->mcu, pwm_set_cmd,\n+\t\t\t\t\t\tsizeof(pwm_set_cmd), resp_buf,\n+\t\t\t\t\t\t&reply_size);\n+\tif (ret)\n+\t\tgoto exit;\n+\n+\tif (reply_size != 3) {\n+\t\tret = -EIO;\n+\t\tgoto exit;\n+\t}\n+\n+\tif (!(resp_buf[0] == IEI_WT61P803_PUZZLE_CMD_HEADER_START &&\n+\t      resp_buf[1] == IEI_WT61P803_PUZZLE_CMD_RESPONSE_OK &&\n+\t      resp_buf[2] == IEI_WT61P803_PUZZLE_CHECKSUM_RESPONSE_OK)) {\n+\t\tret = -EIO;\n+\t\tgoto exit;\n+\t}\n+exit:\n+\tmutex_unlock(&mcu_hwmon->lock);\n+\treturn ret;\n+}\n+\n+static int iei_wt61p803_puzzle_read_pwm_channel(struct iei_wt61p803_puzzle_hwmon *mcu_hwmon,\n+\t\t\t\t\t\tint channel, long *value)\n+{\n+\tunsigned char *resp_buf = mcu_hwmon->response_buffer;\n+\tunsigned char pwm_get_cmd[5] = {};\n+\tsize_t reply_size;\n+\tint ret;\n+\n+\tpwm_get_cmd[0] = IEI_WT61P803_PUZZLE_CMD_HEADER_START;\n+\tpwm_get_cmd[1] = IEI_WT61P803_PUZZLE_CMD_FAN;\n+\tpwm_get_cmd[2] = IEI_WT61P803_PUZZLE_CMD_FAN_PWM_READ;\n+\tpwm_get_cmd[3] = IEI_WT61P803_PUZZLE_CMD_FAN_PWM(channel);\n+\n+\tret = iei_wt61p803_puzzle_write_command(mcu_hwmon->mcu, pwm_get_cmd,\n+\t\t\t\t\t\tsizeof(pwm_get_cmd), resp_buf,\n+\t\t\t\t\t\t&reply_size);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tif (reply_size != 5)\n+\t\treturn -EIO;\n+\n+\tif (resp_buf[2] != IEI_WT61P803_PUZZLE_CMD_FAN_PWM_READ)\n+\t\treturn -EIO;\n+\n+\t*value = resp_buf[3];\n+\n+\treturn 0;\n+}\n+\n+static int iei_wt61p803_puzzle_read(struct device *dev, enum hwmon_sensor_types type,\n+\t\t\t\t    u32 attr, int channel, long *val)\n+{\n+\tstruct iei_wt61p803_puzzle_hwmon *mcu_hwmon = dev_get_drvdata(dev->parent);\n+\n+\tswitch (type) {\n+\tcase hwmon_pwm:\n+\t\treturn iei_wt61p803_puzzle_read_pwm_channel(mcu_hwmon, channel, val);\n+\tcase hwmon_fan:\n+\t\treturn iei_wt61p803_puzzle_read_fan_speed(mcu_hwmon, channel, val);\n+\tcase hwmon_temp:\n+\t\treturn iei_wt61p803_puzzle_read_temp_sensor(mcu_hwmon, channel, val);\n+\tdefault:\n+\t\treturn -EINVAL;\n+\t}\n+}\n+\n+static int iei_wt61p803_puzzle_write(struct device *dev, enum hwmon_sensor_types type,\n+\t\t\t\t     u32 attr, int channel, long val)\n+{\n+\tstruct iei_wt61p803_puzzle_hwmon *mcu_hwmon = dev_get_drvdata(dev->parent);\n+\n+\treturn iei_wt61p803_puzzle_write_pwm_channel(mcu_hwmon, channel, val);\n+}\n+\n+static umode_t iei_wt61p803_puzzle_is_visible(const void *data, enum hwmon_sensor_types type,\n+\t\t\t\t\t      u32 attr, int channel)\n+{\n+\tconst struct iei_wt61p803_puzzle_hwmon *mcu_hwmon = data;\n+\n+\tswitch (type) {\n+\tcase hwmon_pwm:\n+\t\tif (mcu_hwmon->thermal_cooling_dev_present[channel])\n+\t\t\treturn 0444;\n+\t\tif (attr == hwmon_pwm_input)\n+\t\t\treturn 0644;\n+\t\tbreak;\n+\tcase hwmon_fan:\n+\t\tif (attr == hwmon_fan_input)\n+\t\t\treturn 0444;\n+\t\tbreak;\n+\tcase hwmon_temp:\n+\t\tif (attr == hwmon_temp_input)\n+\t\t\treturn 0444;\n+\t\tbreak;\n+\tdefault:\n+\t\treturn 0;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static const struct hwmon_ops iei_wt61p803_puzzle_hwmon_ops = {\n+\t.is_visible = iei_wt61p803_puzzle_is_visible,\n+\t.read = iei_wt61p803_puzzle_read,\n+\t.write = iei_wt61p803_puzzle_write,\n+};\n+\n+static const struct hwmon_channel_info *iei_wt61p803_puzzle_info[] = {\n+\tHWMON_CHANNEL_INFO(pwm,\n+\t\t\t   HWMON_PWM_INPUT,\n+\t\t\t   HWMON_PWM_INPUT),\n+\tHWMON_CHANNEL_INFO(fan,\n+\t\t\t   HWMON_F_INPUT,\n+\t\t\t   HWMON_F_INPUT,\n+\t\t\t   HWMON_F_INPUT,\n+\t\t\t   HWMON_F_INPUT,\n+\t\t\t   HWMON_F_INPUT),\n+\tHWMON_CHANNEL_INFO(temp,\n+\t\t\t   HWMON_T_INPUT,\n+\t\t\t   HWMON_T_INPUT),\n+\tNULL\n+};\n+\n+static const struct hwmon_chip_info iei_wt61p803_puzzle_chip_info = {\n+\t.ops = &iei_wt61p803_puzzle_hwmon_ops,\n+\t.info = iei_wt61p803_puzzle_info,\n+};\n+\n+static int iei_wt61p803_puzzle_get_max_state(struct thermal_cooling_device *tcdev,\n+\t\t\t\t\t     unsigned long *state)\n+{\n+\t*state = IEI_WT61P803_PUZZLE_HWMON_MAX_PWM_VAL;\n+\n+\treturn 0;\n+}\n+\n+static int iei_wt61p803_puzzle_get_cur_state(struct thermal_cooling_device *tcdev,\n+\t\t\t\t\t     unsigned long *state)\n+{\n+\tstruct iei_wt61p803_puzzle_thermal_cooling_device *cdev = tcdev->devdata;\n+\tstruct iei_wt61p803_puzzle_hwmon *mcu_hwmon = cdev->mcu_hwmon;\n+\tlong value;\n+\tint ret;\n+\n+\tret = iei_wt61p803_puzzle_read_pwm_channel(mcu_hwmon, cdev->pwm_channel, &value);\n+\tif (ret)\n+\t\treturn ret;\n+\t*state = value;\n+\treturn 0;\n+}\n+\n+static int iei_wt61p803_puzzle_set_cur_state(struct thermal_cooling_device *tcdev,\n+\t\t\t\t\t     unsigned long state)\n+{\n+\tstruct iei_wt61p803_puzzle_thermal_cooling_device *cdev = tcdev->devdata;\n+\tstruct iei_wt61p803_puzzle_hwmon *mcu_hwmon = cdev->mcu_hwmon;\n+\n+\treturn iei_wt61p803_puzzle_write_pwm_channel(mcu_hwmon, cdev->pwm_channel, state);\n+}\n+\n+static const struct thermal_cooling_device_ops iei_wt61p803_puzzle_cooling_ops = {\n+\t.get_max_state = iei_wt61p803_puzzle_get_max_state,\n+\t.get_cur_state = iei_wt61p803_puzzle_get_cur_state,\n+\t.set_cur_state = iei_wt61p803_puzzle_set_cur_state,\n+};\n+\n+static int\n+iei_wt61p803_puzzle_enable_thermal_cooling_dev(struct device *dev,\n+\t\t\t\t\t       struct fwnode_handle *child,\n+\t\t\t\t\t       struct iei_wt61p803_puzzle_hwmon *mcu_hwmon)\n+{\n+\tstruct iei_wt61p803_puzzle_thermal_cooling_device *cdev;\n+\tu32 pwm_channel;\n+\tu8 num_levels;\n+\tint ret;\n+\n+\tret = fwnode_property_read_u32(child, \"reg\", &pwm_channel);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tmcu_hwmon->thermal_cooling_dev_present[pwm_channel] = true;\n+\n+\tnum_levels = fwnode_property_count_u8(child, \"cooling-levels\");\n+\tif (!num_levels)\n+\t\treturn -EINVAL;\n+\n+\tcdev = devm_kzalloc(dev, sizeof(*cdev), GFP_KERNEL);\n+\tif (!cdev)\n+\t\treturn -ENOMEM;\n+\n+\tcdev->cooling_levels = devm_kmalloc_array(dev, num_levels, sizeof(u8), GFP_KERNEL);\n+\tif (!cdev->cooling_levels)\n+\t\treturn -ENOMEM;\n+\n+\tret = fwnode_property_read_u8_array(child, \"cooling-levels\",\n+\t\t\t\t\t    cdev->cooling_levels,\n+\t\t\t\t\t    num_levels);\n+\tif (ret) {\n+\t\tdev_err(dev, \"Couldn't read property 'cooling-levels'\\n\");\n+\t\treturn ret;\n+\t}\n+\n+\tsnprintf(cdev->name, THERMAL_NAME_LENGTH, \"wt61p803_puzzle_%d\", pwm_channel);\n+\tcdev->tcdev = devm_thermal_of_cooling_device_register(dev, NULL, cdev->name, cdev,\n+\t\t\t\t\t\t\t      &iei_wt61p803_puzzle_cooling_ops);\n+\tif (IS_ERR(cdev->tcdev))\n+\t\treturn PTR_ERR(cdev->tcdev);\n+\n+\tcdev->mcu_hwmon = mcu_hwmon;\n+\tcdev->pwm_channel = pwm_channel;\n+\tmcu_hwmon->cdev[pwm_channel] = cdev;\n+\n+\treturn 0;\n+}\n+\n+static int iei_wt61p803_puzzle_hwmon_probe(struct platform_device *pdev)\n+{\n+\tstruct device *dev = &pdev->dev;\n+\tstruct iei_wt61p803_puzzle *mcu = dev_get_drvdata(dev->parent);\n+\tstruct iei_wt61p803_puzzle_hwmon *mcu_hwmon;\n+\tstruct fwnode_handle *child;\n+\tstruct device *hwmon_dev;\n+\tint ret;\n+\n+\tmcu_hwmon = devm_kzalloc(dev, sizeof(*mcu_hwmon), GFP_KERNEL);\n+\tif (!mcu_hwmon)\n+\t\treturn -ENOMEM;\n+\n+\tmcu_hwmon->mcu = mcu;\n+\tplatform_set_drvdata(pdev, mcu_hwmon);\n+\tmutex_init(&mcu_hwmon->lock);\n+\n+\thwmon_dev = devm_hwmon_device_register_with_info(dev, \"iei_wt61p803_puzzle\",\n+\t\t\t\t\t\t\t mcu_hwmon,\n+\t\t\t\t\t\t\t &iei_wt61p803_puzzle_chip_info,\n+\t\t\t\t\t\t\t NULL);\n+\tif (IS_ERR(hwmon_dev))\n+\t\treturn PTR_ERR(hwmon_dev);\n+\n+\t/* Control fans via PWM lines via Linux Kernel */\n+\tif (IS_ENABLED(CONFIG_THERMAL)) {\n+\t\tdevice_for_each_child_node(dev, child) {\n+\t\t\tret = iei_wt61p803_puzzle_enable_thermal_cooling_dev(dev, child, mcu_hwmon);\n+\t\t\tif (ret) {\n+\t\t\t\tdev_err(dev, \"Enabling the PWM fan failed\\n\");\n+\t\t\t\tfwnode_handle_put(child);\n+\t\t\t\treturn ret;\n+\t\t\t}\n+\t\t}\n+\t}\n+\treturn 0;\n+}\n+\n+static const struct of_device_id iei_wt61p803_puzzle_hwmon_id_table[] = {\n+\t{ .compatible = \"iei,wt61p803-puzzle-hwmon\" },\n+\t{}\n+};\n+MODULE_DEVICE_TABLE(of, iei_wt61p803_puzzle_hwmon_id_table);\n+\n+static struct platform_driver iei_wt61p803_puzzle_hwmon_driver = {\n+\t.driver = {\n+\t\t.name = \"iei-wt61p803-puzzle-hwmon\",\n+\t\t.of_match_table = iei_wt61p803_puzzle_hwmon_id_table,\n+\t},\n+\t.probe = iei_wt61p803_puzzle_hwmon_probe,\n+};\n+\n+module_platform_driver(iei_wt61p803_puzzle_hwmon_driver);\n+\n+MODULE_DESCRIPTION(\"IEI WT61P803 PUZZLE MCU HWMON Driver\");\n+MODULE_AUTHOR(\"Luka Kovacic <luka.kovacic@sartura.hr>\");\n+MODULE_LICENSE(\"GPL v2\");\n"
  },
  {
    "path": "target/linux/mvebu/patches-5.10/904-drivers-leds-Add-the-IEI-WT61P803-PUZZLE-LED-driver.patch",
    "content": "From f3b44eb69cc561cf05d00506dcec0dd9be003ed8 Mon Sep 17 00:00:00 2001\nFrom: Luka Kovacic <luka.kovacic () sartura ! hr>\nDate: Tue, 24 Aug 2021 12:44:35 +0000\nSubject: [PATCH 4/7] drivers: leds: Add the IEI WT61P803 PUZZLE LED driver\n\nAdd support for the IEI WT61P803 PUZZLE LED driver.\nCurrently only the front panel power LED is supported,\nsince it is the only LED on this board wired through the\nMCU.\n\nThe LED is wired directly to the on-board MCU controller\nand is toggled using an MCU command.\n\nSupport for more LEDs is going to be added in case more\nboards implement this microcontroller, as LEDs use many\ndifferent GPIOs.\n\nThis driver depends on the IEI WT61P803 PUZZLE MFD driver.\n\nSigned-off-by: Luka Kovacic <luka.kovacic@sartura.hr>\nSigned-off-by: Pavo Banicevic <pavo.banicevic@sartura.hr>\nCc: Luka Perkov <luka.perkov@sartura.hr>\nCc: Robert Marko <robert.marko@sartura.hr>\n---\n drivers/leds/Kconfig                    |   8 ++\n drivers/leds/Makefile                   |   1 +\n drivers/leds/leds-iei-wt61p803-puzzle.c | 147 ++++++++++++++++++++++++\n 3 files changed, 156 insertions(+)\n create mode 100644 drivers/leds/leds-iei-wt61p803-puzzle.c\n\n--- a/drivers/leds/Kconfig\n+++ b/drivers/leds/Kconfig\n@@ -333,6 +333,14 @@ config LEDS_IPAQ_MICRO\n \t  Choose this option if you want to use the notification LED on\n \t  Compaq/HP iPAQ h3100 and h3600.\n \n+config LEDS_IEI_WT61P803_PUZZLE\n+\ttristate \"LED Support for the IEI WT61P803 PUZZLE MCU\"\n+\tdepends on LEDS_CLASS\n+\tdepends on MFD_IEI_WT61P803_PUZZLE\n+\thelp\n+\t  This option enables support for LEDs controlled by the IEI WT61P803\n+\t  M801 MCU.\n+\n config LEDS_HP6XX\n \ttristate \"LED Support for the HP Jornada 6xx\"\n \tdepends on LEDS_CLASS\n--- a/drivers/leds/Makefile\n+++ b/drivers/leds/Makefile\n@@ -35,6 +35,7 @@ obj-$(CONFIG_LEDS_HP6XX)\t\t+= leds-hp6xx.\n obj-$(CONFIG_LEDS_INTEL_SS4200)\t\t+= leds-ss4200.o\n obj-$(CONFIG_LEDS_IP30)\t\t\t+= leds-ip30.o\n obj-$(CONFIG_LEDS_IPAQ_MICRO)\t\t+= leds-ipaq-micro.o\n+obj-$(CONFIG_LEDS_IEI_WT61P803_PUZZLE)\t+= leds-iei-wt61p803-puzzle.o\n obj-$(CONFIG_LEDS_IS31FL319X)\t\t+= leds-is31fl319x.o\n obj-$(CONFIG_LEDS_IS31FL32XX)\t\t+= leds-is31fl32xx.o\n obj-$(CONFIG_LEDS_KTD2692)\t\t+= leds-ktd2692.o\n--- /dev/null\n+++ b/drivers/leds/leds-iei-wt61p803-puzzle.c\n@@ -0,0 +1,147 @@\n+// SPDX-License-Identifier: GPL-2.0-only\n+/* IEI WT61P803 PUZZLE MCU LED Driver\n+ *\n+ * Copyright (C) 2020 Sartura Ltd.\n+ * Author: Luka Kovacic <luka.kovacic@sartura.hr>\n+ */\n+\n+#include <linux/leds.h>\n+#include <linux/mfd/iei-wt61p803-puzzle.h>\n+#include <linux/mod_devicetable.h>\n+#include <linux/module.h>\n+#include <linux/platform_device.h>\n+#include <linux/property.h>\n+#include <linux/slab.h>\n+\n+enum iei_wt61p803_puzzle_led_state {\n+\tIEI_LED_OFF = 0x30,\n+\tIEI_LED_ON = 0x31,\n+\tIEI_LED_BLINK_5HZ = 0x32,\n+\tIEI_LED_BLINK_1HZ = 0x33,\n+};\n+\n+/**\n+ * struct iei_wt61p803_puzzle_led - MCU LED Driver\n+ * @cdev:\t\tLED classdev\n+ * @mcu:\t\tMCU struct pointer\n+ * @response_buffer\tGlobal MCU response buffer\n+ * @lock:\t\tGeneral mutex lock to protect simultaneous R/W access to led_power_state\n+ * @led_power_state:\tState of the front panel power LED\n+ */\n+struct iei_wt61p803_puzzle_led {\n+\tstruct led_classdev cdev;\n+\tstruct iei_wt61p803_puzzle *mcu;\n+\tunsigned char response_buffer[IEI_WT61P803_PUZZLE_BUF_SIZE];\n+\tstruct mutex lock; /* mutex to protect led_power_state */\n+\tint led_power_state;\n+};\n+\n+static inline struct iei_wt61p803_puzzle_led *cdev_to_iei_wt61p803_puzzle_led\n+\t(struct led_classdev *led_cdev)\n+{\n+\treturn container_of(led_cdev, struct iei_wt61p803_puzzle_led, cdev);\n+}\n+\n+static int iei_wt61p803_puzzle_led_brightness_set_blocking(struct led_classdev *cdev,\n+\t\t\t\t\t\t\t   enum led_brightness brightness)\n+{\n+\tstruct iei_wt61p803_puzzle_led *priv = cdev_to_iei_wt61p803_puzzle_led(cdev);\n+\tunsigned char *resp_buf = priv->response_buffer;\n+\tunsigned char led_power_cmd[5] = {};\n+\tsize_t reply_size;\n+\tint ret;\n+\n+\tled_power_cmd[0] = IEI_WT61P803_PUZZLE_CMD_HEADER_START;\n+\tled_power_cmd[1] = IEI_WT61P803_PUZZLE_CMD_LED;\n+\tled_power_cmd[2] = IEI_WT61P803_PUZZLE_CMD_LED_POWER;\n+\tled_power_cmd[3] = brightness == LED_OFF ? IEI_LED_OFF : IEI_LED_ON;\n+\n+\tret = iei_wt61p803_puzzle_write_command(priv->mcu, led_power_cmd,\n+\t\t\t\t\t\tsizeof(led_power_cmd),\n+\t\t\t\t\t\tresp_buf,\n+\t\t\t\t\t\t&reply_size);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tif (reply_size != 3)\n+\t\treturn -EIO;\n+\n+\tif (!(resp_buf[0] == IEI_WT61P803_PUZZLE_CMD_HEADER_START &&\n+\t      resp_buf[1] == IEI_WT61P803_PUZZLE_CMD_RESPONSE_OK &&\n+\t      resp_buf[2] == IEI_WT61P803_PUZZLE_CHECKSUM_RESPONSE_OK))\n+\t\treturn -EIO;\n+\n+\tmutex_lock(&priv->lock);\n+\tpriv->led_power_state = brightness;\n+\tmutex_unlock(&priv->lock);\n+\n+\treturn 0;\n+}\n+\n+static enum led_brightness iei_wt61p803_puzzle_led_brightness_get(struct led_classdev *cdev)\n+{\n+\tstruct iei_wt61p803_puzzle_led *priv = cdev_to_iei_wt61p803_puzzle_led(cdev);\n+\tint led_state;\n+\n+\tmutex_lock(&priv->lock);\n+\tled_state = priv->led_power_state;\n+\tmutex_unlock(&priv->lock);\n+\n+\treturn led_state;\n+}\n+\n+static int iei_wt61p803_puzzle_led_probe(struct platform_device *pdev)\n+{\n+\tstruct device *dev = &pdev->dev;\n+\tstruct iei_wt61p803_puzzle *mcu = dev_get_drvdata(dev->parent);\n+\tstruct iei_wt61p803_puzzle_led *priv;\n+\tstruct led_init_data init_data = {};\n+\tstruct fwnode_handle *child;\n+\tint ret;\n+\n+\tif (device_get_child_node_count(dev) != 1)\n+\t\treturn -EINVAL;\n+\n+\tpriv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);\n+\tif (!priv)\n+\t\treturn -ENOMEM;\n+\n+\tpriv->mcu = mcu;\n+\tpriv->led_power_state = 1;\n+\tmutex_init(&priv->lock);\n+\tdev_set_drvdata(dev, priv);\n+\n+\tchild = device_get_next_child_node(dev, NULL);\n+\tinit_data.fwnode = child;\n+\n+\tpriv->cdev.brightness_set_blocking = iei_wt61p803_puzzle_led_brightness_set_blocking;\n+\tpriv->cdev.brightness_get = iei_wt61p803_puzzle_led_brightness_get;\n+\tpriv->cdev.max_brightness = 1;\n+\n+\tret = devm_led_classdev_register_ext(dev, &priv->cdev, &init_data);\n+\tif (ret)\n+\t\tdev_err(dev, \"Could not register LED\\n\");\n+\n+\tfwnode_handle_put(child);\n+\treturn ret;\n+}\n+\n+static const struct of_device_id iei_wt61p803_puzzle_led_of_match[] = {\n+\t{ .compatible = \"iei,wt61p803-puzzle-leds\" },\n+\t{ }\n+};\n+MODULE_DEVICE_TABLE(of, iei_wt61p803_puzzle_led_of_match);\n+\n+static struct platform_driver iei_wt61p803_puzzle_led_driver = {\n+\t.driver = {\n+\t\t.name = \"iei-wt61p803-puzzle-led\",\n+\t\t.of_match_table = iei_wt61p803_puzzle_led_of_match,\n+\t},\n+\t.probe = iei_wt61p803_puzzle_led_probe,\n+};\n+module_platform_driver(iei_wt61p803_puzzle_led_driver);\n+\n+MODULE_DESCRIPTION(\"IEI WT61P803 PUZZLE front panel LED driver\");\n+MODULE_AUTHOR(\"Luka Kovacic <luka.kovacic@sartura.hr>\");\n+MODULE_LICENSE(\"GPL v2\");\n+MODULE_ALIAS(\"platform:leds-iei-wt61p803-puzzle\");\n"
  },
  {
    "path": "target/linux/mvebu/patches-5.10/905-Documentation-ABI-Add-iei-wt61p803-puzzle-driver-sys.patch",
    "content": "From 2fab3b4956c5b2f83c1e1abffc1df39de2933d83 Mon Sep 17 00:00:00 2001\nFrom: Luka Kovacic <luka.kovacic () sartura ! hr>\nDate: Tue, 24 Aug 2021 12:44:36 +0000\nSubject: [PATCH 5/7] Documentation/ABI: Add iei-wt61p803-puzzle driver sysfs\n interface documentation\n\nAdd the iei-wt61p803-puzzle driver sysfs interface documentation to allow\nmonitoring and control of the microcontroller from user space.\n\nSigned-off-by: Luka Kovacic <luka.kovacic@sartura.hr>\nSigned-off-by: Pavo Banicevic <pavo.banicevic@sartura.hr>\nCc: Luka Perkov <luka.perkov@sartura.hr>\nCc: Robert Marko <robert.marko@sartura.hr>\n---\n .../testing/sysfs-driver-iei-wt61p803-puzzle  | 61 +++++++++++++++++++\n 1 file changed, 61 insertions(+)\n create mode 100644 Documentation/ABI/testing/sysfs-driver-iei-wt61p803-puzzle\n\n--- /dev/null\n+++ b/Documentation/ABI/testing/sysfs-driver-iei-wt61p803-puzzle\n@@ -0,0 +1,61 @@\n+What:\t\t/sys/bus/serial/devices/.../mac_address_*\n+Date:\t\tSeptember 2020\n+Contact:\tLuka Kovacic <luka.kovacic@sartura.hr>\n+Description:\t(RW) Internal factory assigned MAC address values\n+\n+What:\t\t/sys/bus/serial/devices/.../serial_number\n+Date:\t\tSeptember 2020\n+Contact:\tLuka Kovacic <luka.kovacic@sartura.hr>\n+Description:\t(RW) Internal factory assigned serial number\n+\n+What:\t\t/sys/bus/serial/devices/.../version\n+Date:\t\tSeptember 2020\n+Contact:\tLuka Kovacic <luka.kovacic@sartura.hr>\n+Description:\t(RO) Internal MCU firmware version\n+\n+What:\t\t/sys/bus/serial/devices/.../protocol_version\n+Date:\t\tSeptember 2020\n+Contact:\tLuka Kovacic <luka.kovacic@sartura.hr>\n+Description:\t(RO) Internal MCU communication protocol version\n+\n+What:\t\t/sys/bus/serial/devices/.../power_loss_recovery\n+Date:\t\tSeptember 2020\n+Contact:\tLuka Kovacic <luka.kovacic@sartura.hr>\n+Description:\t(RW) Host platform power loss recovery settings\n+\t\tValue mapping: 0 - Always-On, 1 - Always-Off, 2 - Always-AC, 3 - Always-WA\n+\n+What:\t\t/sys/bus/serial/devices/.../bootloader_mode\n+Date:\t\tSeptember 2020\n+Contact:\tLuka Kovacic <luka.kovacic@sartura.hr>\n+Description:\t(RO) Internal MCU bootloader mode status\n+\t\tValue mapping:\n+\t\t0 - normal mode\n+\t\t1 - bootloader mode\n+\n+What:\t\t/sys/bus/serial/devices/.../power_status\n+Date:\t\tSeptember 2020\n+Contact:\tLuka Kovacic <luka.kovacic@sartura.hr>\n+Description:\t(RO) Power status indicates the host platform power on method.\n+\t\tValue mapping (bitwise list):\n+\t\t0x80 - Null\n+\t\t0x40 - Firmware flag\n+\t\t0x20 - Power loss detection flag (powered off)\n+\t\t0x10 - Power loss detection flag (AC mode)\n+\t\t0x08 - Button power on\n+\t\t0x04 - Wake-on-LAN power on\n+\t\t0x02 - RTC alarm power on\n+\t\t0x01 - AC recover power on\n+\n+What:\t\t/sys/bus/serial/devices/.../build_info\n+Date:\t\tSeptember 2020\n+Contact:\tLuka Kovacic <luka.kovacic@sartura.hr>\n+Description:\t(RO) Internal MCU firmware build date\n+\t\tFormat: yyyy/mm/dd hh:mm\n+\n+What:\t\t/sys/bus/serial/devices/.../ac_recovery_status\n+Date:\t\tSeptember 2020\n+Contact:\tLuka Kovacic <luka.kovacic@sartura.hr>\n+Description:\t(RO) Host platform AC recovery status value\n+\t\tValue mapping:\n+\t\t0 - board has not been recovered from power down\n+\t\t1 - board has been recovered from power down\n"
  },
  {
    "path": "target/linux/mvebu/patches-5.10/906-Documentation-hwmon-Add-iei-wt61p803-puzzle-hwmon-dr.patch",
    "content": "From 0aff3e5923fecc6842473ad07a688d6e2f2c2d55 Mon Sep 17 00:00:00 2001\nFrom: Luka Kovacic <luka.kovacic () sartura ! hr>\nDate: Tue, 24 Aug 2021 12:44:37 +0000\nSubject: [PATCH 6/7] Documentation/hwmon: Add iei-wt61p803-puzzle hwmon driver\n documentation\n\nAdd the iei-wt61p803-puzzle driver hwmon driver interface documentation.\n\nSigned-off-by: Luka Kovacic <luka.kovacic@sartura.hr>\nSigned-off-by: Pavo Banicevic <pavo.banicevic@sartura.hr>\nCc: Luka Perkov <luka.perkov@sartura.hr>\nCc: Robert Marko <robert.marko@sartura.hr>\n---\n .../hwmon/iei-wt61p803-puzzle-hwmon.rst       | 43 +++++++++++++++++++\n Documentation/hwmon/index.rst                 |  1 +\n 2 files changed, 44 insertions(+)\n create mode 100644 Documentation/hwmon/iei-wt61p803-puzzle-hwmon.rst\n\n--- /dev/null\n+++ b/Documentation/hwmon/iei-wt61p803-puzzle-hwmon.rst\n@@ -0,0 +1,43 @@\n+.. SPDX-License-Identifier: GPL-2.0-only\n+\n+Kernel driver iei-wt61p803-puzzle-hwmon\n+=======================================\n+\n+Supported chips:\n+ * IEI WT61P803 PUZZLE for IEI Puzzle M801\n+\n+   Prefix: 'iei-wt61p803-puzzle-hwmon'\n+\n+Author: Luka Kovacic <luka.kovacic@sartura.hr>\n+\n+\n+Description\n+-----------\n+\n+This driver adds fan and temperature sensor reading for some IEI Puzzle\n+series boards.\n+\n+Sysfs attributes\n+----------------\n+\n+The following attributes are supported:\n+\n+- IEI WT61P803 PUZZLE for IEI Puzzle M801\n+\n+/sys files in hwmon subsystem\n+-----------------------------\n+\n+================= == =====================================================\n+fan[1-5]_input    RO files for fan speed (in RPM)\n+pwm[1-2]          RW files for fan[1-2] target duty cycle (0..255)\n+temp[1-2]_input   RO files for temperature sensors, in millidegree Celsius\n+================= == =====================================================\n+\n+/sys files in thermal subsystem\n+-------------------------------\n+\n+================= == =====================================================\n+cur_state         RW file for current cooling state of the cooling device\n+                     (0..max_state)\n+max_state         RO file for maximum cooling state of the cooling device\n+================= == =====================================================\n--- a/Documentation/hwmon/index.rst\n+++ b/Documentation/hwmon/index.rst\n@@ -71,6 +71,7 @@ Hardware Monitoring Kernel Drivers\n    ibmaem\n    ibm-cffps\n    ibmpowernv\n+   iei-wt61p803-puzzle-hwmon\n    ina209\n    ina2xx\n    ina3221\n"
  },
  {
    "path": "target/linux/mvebu/patches-5.10/907-MAINTAINERS-Add-an-entry-for-the-IEI-WT61P803-PUZZLE.patch",
    "content": "From 12479baad28d2a08c6cb9e83471057635fa1635c Mon Sep 17 00:00:00 2001\nFrom: Luka Kovacic <luka.kovacic () sartura ! hr>\nDate: Tue, 24 Aug 2021 12:44:38 +0000\nSubject: [PATCH 7/7] MAINTAINERS: Add an entry for the IEI WT61P803 PUZZLE\n driver\n\nAdd an entry for the IEI WT61P803 PUZZLE driver (MFD, HWMON, LED drivers).\n\nSigned-off-by: Luka Kovacic <luka.kovacic@sartura.hr>\nSigned-off-by: Pavo Banicevic <pavo.banicevic@sartura.hr>\nCc: Luka Perkov <luka.perkov@sartura.hr>\nCc: Robert Marko <robert.marko@sartura.hr>\n---\n MAINTAINERS | 16 ++++++++++++++++\n 1 file changed, 16 insertions(+)\n\n--- a/MAINTAINERS\n+++ b/MAINTAINERS\n@@ -8538,6 +8538,22 @@ F:\tinclude/net/nl802154.h\n F:\tnet/ieee802154/\n F:\tnet/mac802154/\n \n+IEI WT61P803 M801 MFD DRIVER\n+M:\tLuka Kovacic <luka.kovacic@sartura.hr>\n+M:\tLuka Perkov <luka.perkov@sartura.hr>\n+M:\tGoran Medic <goran.medic@sartura.hr>\n+L:\tlinux-kernel@vger.kernel.org\n+S:\tMaintained\n+F:\tDocumentation/ABI/stable/sysfs-driver-iei-wt61p803-puzzle\n+F:\tDocumentation/devicetree/bindings/hwmon/iei,wt61p803-puzzle-hwmon.yaml\n+F:\tDocumentation/devicetree/bindings/leds/iei,wt61p803-puzzle-leds.yaml\n+F:\tDocumentation/devicetree/bindings/mfd/iei,wt61p803-puzzle.yaml\n+F:\tDocumentation/hwmon/iei-wt61p803-puzzle-hwmon.rst\n+F:\tdrivers/hwmon/iei-wt61p803-puzzle-hwmon.c\n+F:\tdrivers/leds/leds-iei-wt61p803-puzzle.c\n+F:\tdrivers/mfd/iei-wt61p803-puzzle.c\n+F:\tinclude/linux/mfd/iei-wt61p803-puzzle.h\n+\n IFE PROTOCOL\n M:\tYotam Gigi <yotam.gi@gmail.com>\n M:\tJamal Hadi Salim <jhs@mojatatu.com>\n"
  },
  {
    "path": "target/linux/mvebu/patches-5.10/910-drivers-leds-wt61p803-puzzle-improvements.patch",
    "content": "--- a/drivers/leds/leds-iei-wt61p803-puzzle.c\n+++ b/drivers/leds/leds-iei-wt61p803-puzzle.c\n@@ -9,9 +9,13 @@\n #include <linux/mfd/iei-wt61p803-puzzle.h>\n #include <linux/mod_devicetable.h>\n #include <linux/module.h>\n+#include <linux/of.h>\n #include <linux/platform_device.h>\n #include <linux/property.h>\n #include <linux/slab.h>\n+#include <linux/workqueue.h>\n+\n+#define IEI_LEDS_MAX\t\t4\n \n enum iei_wt61p803_puzzle_led_state {\n \tIEI_LED_OFF = 0x30,\n@@ -33,7 +37,11 @@ struct iei_wt61p803_puzzle_led {\n \tstruct iei_wt61p803_puzzle *mcu;\n \tunsigned char response_buffer[IEI_WT61P803_PUZZLE_BUF_SIZE];\n \tstruct mutex lock; /* mutex to protect led_power_state */\n+\tstruct work_struct work;\n \tint led_power_state;\n+\tint id;\n+\tu8 blinking;\n+\tbool active_low;\n };\n \n static inline struct iei_wt61p803_puzzle_led *cdev_to_iei_wt61p803_puzzle_led\n@@ -51,10 +59,18 @@ static int iei_wt61p803_puzzle_led_brigh\n \tsize_t reply_size;\n \tint ret;\n \n+\tif (priv->blinking) {\n+\t\tif (brightness == LED_OFF)\n+\t\t\tpriv->blinking = 0;\n+\t\telse\n+\t\t\treturn 0;\n+\t}\n+\n \tled_power_cmd[0] = IEI_WT61P803_PUZZLE_CMD_HEADER_START;\n \tled_power_cmd[1] = IEI_WT61P803_PUZZLE_CMD_LED;\n-\tled_power_cmd[2] = IEI_WT61P803_PUZZLE_CMD_LED_POWER;\n-\tled_power_cmd[3] = brightness == LED_OFF ? IEI_LED_OFF : IEI_LED_ON;\n+\tled_power_cmd[2] = IEI_WT61P803_PUZZLE_CMD_LED_SET(priv->id);\n+\tled_power_cmd[3] = ((brightness == LED_OFF) ^ priv->active_low) ?\n+\t\t\t\tIEI_LED_OFF : priv->blinking?priv->blinking:IEI_LED_ON;\n \n \tret = iei_wt61p803_puzzle_write_command(priv->mcu, led_power_cmd,\n \t\t\t\t\t\tsizeof(led_power_cmd),\n@@ -90,39 +106,166 @@ static enum led_brightness iei_wt61p803_\n \treturn led_state;\n }\n \n+static void iei_wt61p803_puzzle_led_apply_blink(struct work_struct *work)\n+{\n+\tstruct iei_wt61p803_puzzle_led *priv = container_of(work, struct iei_wt61p803_puzzle_led, work);\n+\tunsigned char led_blink_cmd[5] = {};\n+\tunsigned char resp_buf[IEI_WT61P803_PUZZLE_BUF_SIZE];\n+\tsize_t reply_size;\n+\n+\tled_blink_cmd[0] = IEI_WT61P803_PUZZLE_CMD_HEADER_START;\n+\tled_blink_cmd[1] = IEI_WT61P803_PUZZLE_CMD_LED;\n+\tled_blink_cmd[2] = IEI_WT61P803_PUZZLE_CMD_LED_SET(priv->id);\n+\tled_blink_cmd[3] = priv->blinking;\n+\n+\tiei_wt61p803_puzzle_write_command(priv->mcu, led_blink_cmd,\n+\t\t\t\t\t  sizeof(led_blink_cmd),\n+\t\t\t\t\t  resp_buf,\n+\t\t\t\t\t  &reply_size);\n+\n+\treturn;\n+}\n+\n+static int iei_wt61p803_puzzle_led_set_blink(struct led_classdev *cdev,\n+\t\t\t\t\t     unsigned long *delay_on,\n+\t\t\t\t\t     unsigned long *delay_off)\n+{\n+\tstruct iei_wt61p803_puzzle_led *priv = cdev_to_iei_wt61p803_puzzle_led(cdev);\n+\tu8 blink_mode = 0;\n+\tint ret = 0;\n+\n+\t/* set defaults */\n+\tif (!*delay_on && !*delay_off) {\n+\t\t*delay_on = 500;\n+\t\t*delay_off = 500;\n+\t}\n+\n+\t/* minimum delay for soft-driven blinking is 100ms to keep load low */\n+\tif (*delay_on < 100)\n+\t\t*delay_on = 100;\n+\n+\tif (*delay_off < 100)\n+\t\t*delay_off = 100;\n+\n+\t/* offload blinking to hardware, if possible */\n+\tif (*delay_on != *delay_off) {\n+\t\tret = -EINVAL;\n+\t} else if (*delay_on == 100) {\n+\t\tblink_mode = IEI_LED_BLINK_5HZ;\n+\t\t*delay_on = 100;\n+\t\t*delay_off = 100;\n+\t} else if (*delay_on <= 500) {\n+\t\tblink_mode = IEI_LED_BLINK_1HZ;\n+\t\t*delay_on = 500;\n+\t\t*delay_off = 500;\n+\t} else {\n+\t\tret = -EINVAL;\n+\t}\n+\n+\tmutex_lock(&priv->lock);\n+\tpriv->blinking = blink_mode;\n+\tmutex_unlock(&priv->lock);\n+\n+\tif (blink_mode)\n+\t\tschedule_work(&priv->work);\n+\n+\treturn ret;\n+}\n+\n+\n+static int iei_wt61p803_puzzle_led_set_dt_default(struct led_classdev *cdev,\n+\t\t\t\t     struct device_node *np)\n+{\n+\tconst char *state;\n+\tint ret = 0;\n+\n+\tstate = of_get_property(np, \"default-state\", NULL);\n+\tif (state) {\n+\t\tif (!strcmp(state, \"on\")) {\n+\t\t\tret =\n+\t\t\tiei_wt61p803_puzzle_led_brightness_set_blocking(\n+\t\t\t\tcdev, cdev->max_brightness);\n+\t\t} else  {\n+\t\t\tret = iei_wt61p803_puzzle_led_brightness_set_blocking(\n+\t\t\t\tcdev, LED_OFF);\n+\t\t}\n+\t}\n+\n+\treturn ret;\n+}\n+\n static int iei_wt61p803_puzzle_led_probe(struct platform_device *pdev)\n {\n \tstruct device *dev = &pdev->dev;\n+\tstruct device_node *np = dev_of_node(dev);\n+\tstruct device_node *child;\n \tstruct iei_wt61p803_puzzle *mcu = dev_get_drvdata(dev->parent);\n \tstruct iei_wt61p803_puzzle_led *priv;\n-\tstruct led_init_data init_data = {};\n-\tstruct fwnode_handle *child;\n \tint ret;\n+\tu32 reg;\n \n-\tif (device_get_child_node_count(dev) != 1)\n+\tif (device_get_child_node_count(dev) > IEI_LEDS_MAX)\n \t\treturn -EINVAL;\n \n-\tpriv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);\n-\tif (!priv)\n-\t\treturn -ENOMEM;\n-\n-\tpriv->mcu = mcu;\n-\tpriv->led_power_state = 1;\n-\tmutex_init(&priv->lock);\n-\tdev_set_drvdata(dev, priv);\n-\n-\tchild = device_get_next_child_node(dev, NULL);\n-\tinit_data.fwnode = child;\n-\n-\tpriv->cdev.brightness_set_blocking = iei_wt61p803_puzzle_led_brightness_set_blocking;\n-\tpriv->cdev.brightness_get = iei_wt61p803_puzzle_led_brightness_get;\n-\tpriv->cdev.max_brightness = 1;\n+\tfor_each_available_child_of_node(np, child) {\n+\t\tstruct led_init_data init_data = {};\n \n-\tret = devm_led_classdev_register_ext(dev, &priv->cdev, &init_data);\n-\tif (ret)\n-\t\tdev_err(dev, \"Could not register LED\\n\");\n+\t\tret = of_property_read_u32(child, \"reg\", &reg);\n+\t\tif (ret) {\n+\t\t\tdev_err(dev, \"Failed to read led 'reg' property\\n\");\n+\t\t\tgoto put_child_node;\n+\t\t}\n+\n+\t\tif (reg > IEI_LEDS_MAX) {\n+\t\t\tdev_err(dev, \"Invalid led reg %u\\n\", reg);\n+\t\t\tret = -EINVAL;\n+\t\t\tgoto put_child_node;\n+\t\t}\n+\n+\t\tpriv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);\n+\t\tif (!priv) {\n+\t\t\tret = -ENOMEM;\n+\t\t\tgoto put_child_node;\n+\t\t}\n+\n+\t\tmutex_init(&priv->lock);\n+\n+\t\tdev_set_drvdata(dev, priv);\n+\n+\t\tif (of_property_read_bool(child, \"active-low\"))\n+\t\t\tpriv->active_low = true;\n+\n+\t\tpriv->mcu = mcu;\n+\t\tpriv->id = reg;\n+\t\tpriv->led_power_state = 1;\n+\t\tpriv->blinking = 0;\n+\t\tinit_data.fwnode = of_fwnode_handle(child);\n+\n+\t\tpriv->cdev.brightness_set_blocking = iei_wt61p803_puzzle_led_brightness_set_blocking;\n+\t\tpriv->cdev.brightness_get = iei_wt61p803_puzzle_led_brightness_get;\n+\t\tpriv->cdev.blink_set = iei_wt61p803_puzzle_led_set_blink;\n+\n+\t\tpriv->cdev.max_brightness = 1;\n+\n+\t\tINIT_WORK(&priv->work, iei_wt61p803_puzzle_led_apply_blink);\n+\n+\t\tret = iei_wt61p803_puzzle_led_set_dt_default(&priv->cdev, child);\n+\t\tif (ret) {\n+\t\t\tdev_err(dev, \"Could apply default from DT\\n\");\n+\t\t\tgoto put_child_node;\n+\t\t}\n+\n+\t\tret = devm_led_classdev_register_ext(dev, &priv->cdev, &init_data);\n+\t\tif (ret) {\n+\t\t\tdev_err(dev, \"Could not register LED\\n\");\n+\t\t\tgoto put_child_node;\n+\t\t}\n+\t}\n+\n+\treturn ret;\n \n-\tfwnode_handle_put(child);\n+put_child_node:\n+\tof_node_put(child);\n \treturn ret;\n }\n \n--- a/include/linux/mfd/iei-wt61p803-puzzle.h\n+++ b/include/linux/mfd/iei-wt61p803-puzzle.h\n@@ -36,7 +36,7 @@\n #define IEI_WT61P803_PUZZLE_CMD_FUNCTION_OTHER_POWER_LOSS 0x41 /* A */\n \n #define IEI_WT61P803_PUZZLE_CMD_LED\t\t\t0x52 /* R */\n-#define IEI_WT61P803_PUZZLE_CMD_LED_POWER\t\t0x31 /* 1 */\n+#define IEI_WT61P803_PUZZLE_CMD_LED_SET(n)\t\t(0x30 | (n))\n \n #define IEI_WT61P803_PUZZLE_CMD_TEMP\t\t\t0x54 /* T */\n #define IEI_WT61P803_PUZZLE_CMD_TEMP_ALL\t\t0x41 /* A */\n--- a/drivers/mfd/iei-wt61p803-puzzle.c\n+++ b/drivers/mfd/iei-wt61p803-puzzle.c\n@@ -176,6 +176,9 @@ static int iei_wt61p803_puzzle_recv_buf(\n \tstruct iei_wt61p803_puzzle *mcu = serdev_device_get_drvdata(serdev);\n \tint ret;\n \n+\tprint_hex_dump_debug(\"puzzle-mcu rx: \", DUMP_PREFIX_NONE,\n+\t\t\t     16, 1, data, size, false);\n+\n \tret = iei_wt61p803_puzzle_process_resp(mcu, data, size);\n \t/* Return the number of processed bytes if function returns error,\n \t * discard the remaining incoming data, since the frame this data\n@@ -246,6 +249,9 @@ int iei_wt61p803_puzzle_write_command(st\n \n \tcmd[size - 1] = iei_wt61p803_puzzle_checksum(cmd, size - 1);\n \n+\tprint_hex_dump_debug(\"puzzle-mcu tx: \", DUMP_PREFIX_NONE,\n+\t\t\t     16, 1, cmd, size, false);\n+\n \t/* Initialize reply struct */\n \treinit_completion(&mcu->reply->received);\n \tmcu->reply->size = 0;\n"
  },
  {
    "path": "target/linux/mxs/Makefile",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2013-2014 OpenWrt.org\n\ninclude $(TOPDIR)/rules.mk\n\nARCH:=arm\nBOARD:=mxs\nBOARDNAME:=Freescale i.MX23/i.MX28\nFEATURES:=ext4 rtc usb gpio\nCPU_TYPE:=arm926ej-s\n\nKERNEL_PATCHVER:=5.10\nKERNEL_TESTING_PATCHVER:=5.15\n\nKERNELNAME:=zImage dtbs\n\ndefine Target/Description\n\tSupport for Freescale i.MX23/i.MX28 boards\nendef\n\ninclude $(INCLUDE_DIR)/target.mk\n\n$(eval $(call BuildTarget))\n"
  },
  {
    "path": "target/linux/mxs/base-files/etc/board.d/02_network",
    "content": "# Copyright (C) 2013-2015 OpenWrt.org\n\n. /lib/functions/uci-defaults.sh\n\nboard_config_update\n\nboard=$(board_name)\n\ncase \"$board\" in\n*)\n\tucidef_set_interface_lan 'eth0'\n\t;;\nesac\n\nboard_config_flush\n\nexit 0\n"
  },
  {
    "path": "target/linux/mxs/base-files/etc/diag.sh",
    "content": "#!/bin/sh\n# Copyright (C) 2013-2014 OpenWrt.org\n\n. /lib/functions.sh\n. /lib/functions/leds.sh\n\nget_status_led() {\n\tcase $(board_name) in\n\ti2se,duckbill*)\n\t\tstatus_led=\"duckbill:green:status\"\n\t\t;;\n\tolimex,imx23-olinuxino)\n\t\tstatus_led=\"green\"\n\t\t;;\n\t*)\n\t\tstatus_led=$(cd /sys/class/leds && ls -1d *:status 2> /dev/null | head -n 1)\n\t\t;;\n\tesac\n}\n\nset_state() {\n\tget_status_led\n\n\tcase \"$1\" in\n\tpreinit)\n\t\tstatus_led_blink_preinit\n\t\t;;\n\tfailsafe)\n\t\tstatus_led_blink_failsafe\n\t\t;;\n\tpreinit_regular)\n\t\tstatus_led_blink_preinit_regular\n\t\t;;\n\tdone)\n\t\tstatus_led_on\n\t\t;;\n\tesac\n}\n"
  },
  {
    "path": "target/linux/mxs/base-files/etc/inittab",
    "content": "::sysinit:/etc/init.d/rcS S boot\n::shutdown:/etc/init.d/rcS K shutdown\n::askconsole:/usr/libexec/login.sh\nttyGS0::askfirst:/usr/libexec/login.sh\n"
  },
  {
    "path": "target/linux/mxs/config-5.10",
    "content": "CONFIG_ALIGNMENT_TRAP=y\nCONFIG_ARCH_32BIT_OFF_T=y\nCONFIG_ARCH_HIBERNATION_POSSIBLE=y\nCONFIG_ARCH_KEEP_MEMBLOCK=y\nCONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y\nCONFIG_ARCH_MULTIPLATFORM=y\nCONFIG_ARCH_MULTI_CPU_AUTO=y\n# CONFIG_ARCH_MULTI_V4 is not set\n# CONFIG_ARCH_MULTI_V4T is not set\nCONFIG_ARCH_MULTI_V4_V5=y\nCONFIG_ARCH_MULTI_V5=y\nCONFIG_ARCH_MXS=y\nCONFIG_ARCH_NR_GPIO=0\nCONFIG_ARCH_OPTIONAL_KERNEL_RWX=y\nCONFIG_ARCH_SELECT_MEMORY_MODEL=y\nCONFIG_ARCH_SPARSEMEM_ENABLE=y\nCONFIG_ARCH_SUSPEND_POSSIBLE=y\nCONFIG_ARM=y\nCONFIG_ARM_AMBA=y\nCONFIG_ARM_APPENDED_DTB=y\nCONFIG_ARM_ATAG_DTB_COMPAT=y\nCONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y\nCONFIG_ARM_CPU_SUSPEND=y\nCONFIG_ARM_HAS_SG_CHAIN=y\nCONFIG_ARM_L1_CACHE_SHIFT=5\nCONFIG_ARM_PATCH_PHYS_VIRT=y\nCONFIG_ARM_THUMB=y\nCONFIG_ARM_UNWIND=y\nCONFIG_ATAGS=y\nCONFIG_AUTO_ZRELADDR=y\nCONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y\nCONFIG_BLK_PM=y\nCONFIG_CLKDEV_LOOKUP=y\nCONFIG_CLKSRC_MMIO=y\nCONFIG_CLONE_BACKWARDS=y\nCONFIG_CMDLINE=\"console=ttyAMA0,115200 root=/dev/mmcblk0p2 rw rootwait\"\nCONFIG_CMDLINE_FROM_BOOTLOADER=y\nCONFIG_COMMON_CLK=y\nCONFIG_COMPAT_32BIT_TIME=y\nCONFIG_COREDUMP=y\nCONFIG_CPU_32v5=y\nCONFIG_CPU_ABRT_EV5TJ=y\nCONFIG_CPU_ARM926T=y\n# CONFIG_CPU_CACHE_ROUND_ROBIN is not set\nCONFIG_CPU_CACHE_VIVT=y\nCONFIG_CPU_COPY_V4WB=y\nCONFIG_CPU_CP15=y\nCONFIG_CPU_CP15_MMU=y\n# CONFIG_CPU_DCACHE_WRITETHROUGH is not set\nCONFIG_CPU_IDLE=y\nCONFIG_CPU_IDLE_GOV_LADDER=y\nCONFIG_CPU_IDLE_GOV_MENU=y\nCONFIG_CPU_PABRT_LEGACY=y\nCONFIG_CPU_PM=y\nCONFIG_CPU_THUMB_CAPABLE=y\nCONFIG_CPU_TLB_V4WBI=y\nCONFIG_CPU_USE_DOMAINS=y\nCONFIG_CRC16=y\nCONFIG_CROSS_MEMORY_ATTACH=y\nCONFIG_CRYPTO_CBC=y\nCONFIG_CRYPTO_CRC32C=y\nCONFIG_CRYPTO_DEV_MXS_DCP=y\nCONFIG_CRYPTO_ECB=y\nCONFIG_CRYPTO_HW=y\nCONFIG_CRYPTO_RNG2=y\nCONFIG_DEBUG_ALIGN_RODATA=y\nCONFIG_DEBUG_LL_INCLUDE=\"mach/debug-macro.S\"\nCONFIG_DMADEVICES=y\nCONFIG_DMA_ENGINE=y\nCONFIG_DMA_OF=y\nCONFIG_DMA_OPS=y\nCONFIG_DMA_REMAP=y\nCONFIG_DTC=y\nCONFIG_EDAC_ATOMIC_SCRUB=y\nCONFIG_EDAC_SUPPORT=y\nCONFIG_EXT4_FS=y\nCONFIG_EXTCON=y\nCONFIG_FEC=y\nCONFIG_FIXED_PHY=y\nCONFIG_FIX_EARLYCON_MEM=y\nCONFIG_FS_IOMAP=y\nCONFIG_FS_MBCACHE=y\nCONFIG_FW_LOADER_PAGED_BUF=y\nCONFIG_GENERIC_ALLOCATOR=y\nCONFIG_GENERIC_ATOMIC64=y\nCONFIG_GENERIC_BUG=y\nCONFIG_GENERIC_CLOCKEVENTS=y\nCONFIG_GENERIC_CPU_AUTOPROBE=y\nCONFIG_GENERIC_EARLY_IOREMAP=y\nCONFIG_GENERIC_IDLE_POLL_SETUP=y\nCONFIG_GENERIC_IRQ_CHIP=y\nCONFIG_GENERIC_IRQ_MULTI_HANDLER=y\nCONFIG_GENERIC_IRQ_SHOW=y\nCONFIG_GENERIC_IRQ_SHOW_LEVEL=y\nCONFIG_GENERIC_PCI_IOMAP=y\nCONFIG_GENERIC_SCHED_CLOCK=y\nCONFIG_GENERIC_SMP_IDLE_THREAD=y\nCONFIG_GENERIC_STRNCPY_FROM_USER=y\nCONFIG_GENERIC_STRNLEN_USER=y\n# CONFIG_GIANFAR is not set\nCONFIG_GLOB=y\nCONFIG_GPIOLIB=y\nCONFIG_GPIO_GENERIC=y\nCONFIG_GPIO_GENERIC_PLATFORM=y\nCONFIG_GPIO_MXS=y\nCONFIG_HANDLE_DOMAIN_IRQ=y\nCONFIG_HARDIRQS_SW_RESEND=y\nCONFIG_HAS_DMA=y\nCONFIG_HAS_IOMEM=y\nCONFIG_HAS_IOPORT_MAP=y\nCONFIG_HZ_FIXED=0\nCONFIG_HZ_PERIODIC=y\nCONFIG_I2C=y\nCONFIG_I2C_ALGOBIT=y\nCONFIG_I2C_ALGOPCA=y\nCONFIG_I2C_ALGOPCF=y\nCONFIG_I2C_BOARDINFO=y\nCONFIG_I2C_CHARDEV=y\nCONFIG_I2C_COMPAT=y\nCONFIG_I2C_MUX=y\nCONFIG_I2C_MUX_PINCTRL=y\nCONFIG_I2C_MXS=y\nCONFIG_IIO=y\nCONFIG_IIO_BUFFER=y\nCONFIG_IIO_KFIFO_BUF=y\nCONFIG_IIO_SYSFS_TRIGGER=y\nCONFIG_IIO_TRIGGER=y\n# CONFIG_IIO_TRIGGERED_BUFFER is not set\nCONFIG_INITRAMFS_SOURCE=\"\"\nCONFIG_INPUT=y\nCONFIG_IRQCHIP=y\nCONFIG_IRQ_DOMAIN=y\nCONFIG_IRQ_FORCED_THREADING=y\nCONFIG_IRQ_MXS=y\nCONFIG_IRQ_WORK=y\n# CONFIG_ISDN is not set\nCONFIG_JBD2=y\nCONFIG_LIBFDT=y\nCONFIG_LOCK_DEBUGGING_SUPPORT=y\nCONFIG_MDIO_BUS=y\nCONFIG_MDIO_DEVICE=y\nCONFIG_MDIO_DEVRES=y\nCONFIG_MEMFD_CREATE=y\nCONFIG_MFD_CORE=y\nCONFIG_MFD_MXS_LRADC=y\nCONFIG_MIGRATION=y\nCONFIG_MMC=y\nCONFIG_MMC_BLOCK=y\nCONFIG_MMC_MXS=y\nCONFIG_MODULES_USE_ELF_REL=y\nCONFIG_MXS_DMA=y\n# CONFIG_MXS_LRADC_ADC is not set\nCONFIG_MXS_TIMER=y\nCONFIG_NEED_DMA_MAP_STATE=y\nCONFIG_NEED_KUSER_HELPERS=y\nCONFIG_NEED_PER_CPU_KM=y\nCONFIG_NET_PTP_CLASSIFY=y\nCONFIG_NLS=y\nCONFIG_NVMEM=y\nCONFIG_NVMEM_MXS_OCOTP=y\nCONFIG_OF=y\nCONFIG_OF_ADDRESS=y\nCONFIG_OF_EARLY_FLATTREE=y\nCONFIG_OF_FLATTREE=y\nCONFIG_OF_GPIO=y\nCONFIG_OF_IRQ=y\nCONFIG_OF_KOBJ=y\nCONFIG_OF_MDIO=y\nCONFIG_OF_NET=y\nCONFIG_OLD_SIGACTION=y\nCONFIG_OLD_SIGSUSPEND3=y\nCONFIG_PAGE_OFFSET=0xC0000000\nCONFIG_PERF_USE_VMALLOC=y\nCONFIG_PGTABLE_LEVELS=2\nCONFIG_PHYLIB=y\nCONFIG_PINCTRL=y\nCONFIG_PINCTRL_IMX23=y\nCONFIG_PINCTRL_IMX28=y\nCONFIG_PINCTRL_MXS=y\n# CONFIG_PINCTRL_SINGLE is not set\nCONFIG_PM=y\nCONFIG_PM_CLK=y\nCONFIG_POWER_SUPPLY=y\nCONFIG_PPS=y\nCONFIG_PTP_1588_CLOCK=y\nCONFIG_RATIONAL=y\nCONFIG_REGULATOR=y\nCONFIG_REGULATOR_FIXED_VOLTAGE=y\nCONFIG_REGULATOR_GPIO=y\nCONFIG_RESET_CONTROLLER=y\nCONFIG_RTC_CLASS=y\nCONFIG_RTC_DRV_STMP=y\nCONFIG_RTC_I2C_AND_SPI=y\nCONFIG_RTC_MC146818_LIB=y\n# CONFIG_SERIAL_8250 is not set\nCONFIG_SERIAL_AMBA_PL011=y\nCONFIG_SERIAL_AMBA_PL011_CONSOLE=y\nCONFIG_SERIAL_MCTRL_GPIO=y\nCONFIG_SERIAL_MXS_AUART=y\nCONFIG_SERIAL_MXS_AUART_CONSOLE=y\nCONFIG_SMSC_PHY=y\nCONFIG_SOC_BUS=y\nCONFIG_SOC_IMX23=y\nCONFIG_SOC_IMX28=y\nCONFIG_SPARSE_IRQ=y\nCONFIG_SPI=y\nCONFIG_SPI_MASTER=y\nCONFIG_SPI_MXS=y\nCONFIG_SPLIT_PTLOCK_CPUS=999999\nCONFIG_SRCU=y\nCONFIG_STMP3XXX_RTC_WATCHDOG=y\nCONFIG_STMP_DEVICE=y\nCONFIG_SWPHY=y\nCONFIG_SYS_SUPPORTS_APM_EMULATION=y\nCONFIG_TICK_CPU_ACCOUNTING=y\nCONFIG_TIMER_OF=y\nCONFIG_TIMER_PROBE=y\nCONFIG_TINY_SRCU=y\nCONFIG_UNCOMPRESS_INCLUDE=\"debug/uncompress.h\"\nCONFIG_UNWINDER_ARM=y\nCONFIG_USB=y\nCONFIG_USB_CHIPIDEA=y\nCONFIG_USB_CHIPIDEA_HOST=y\nCONFIG_USB_CHIPIDEA_IMX=y\nCONFIG_USB_CHIPIDEA_UDC=y\nCONFIG_USB_COMMON=y\nCONFIG_USB_EHCI_HCD=y\n# CONFIG_USB_EHCI_HCD_PLATFORM is not set\nCONFIG_USB_GADGET=y\nCONFIG_USB_MXS_PHY=y\nCONFIG_USB_OTG=y\nCONFIG_USB_PHY=y\nCONFIG_USB_ROLE_SWITCH=y\nCONFIG_USB_SUPPORT=y\nCONFIG_USB_ULPI_BUS=y\nCONFIG_USE_OF=y\n# CONFIG_VFP is not set\nCONFIG_WATCHDOG_CORE=y\nCONFIG_XZ_DEC_ARM=y\nCONFIG_XZ_DEC_BCJ=y\nCONFIG_ZBOOT_ROM_BSS=0\nCONFIG_ZBOOT_ROM_TEXT=0\n"
  },
  {
    "path": "target/linux/mxs/config-5.15",
    "content": "CONFIG_ALIGNMENT_TRAP=y\nCONFIG_ARCH_32BIT_OFF_T=y\nCONFIG_ARCH_HIBERNATION_POSSIBLE=y\nCONFIG_ARCH_KEEP_MEMBLOCK=y\nCONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y\nCONFIG_ARCH_MULTIPLATFORM=y\nCONFIG_ARCH_MULTI_CPU_AUTO=y\n# CONFIG_ARCH_MULTI_V4 is not set\n# CONFIG_ARCH_MULTI_V4T is not set\nCONFIG_ARCH_MULTI_V4_V5=y\nCONFIG_ARCH_MULTI_V5=y\nCONFIG_ARCH_MXS=y\nCONFIG_ARCH_NR_GPIO=0\nCONFIG_ARCH_OPTIONAL_KERNEL_RWX=y\nCONFIG_ARCH_SELECT_MEMORY_MODEL=y\nCONFIG_ARCH_SPARSEMEM_ENABLE=y\nCONFIG_ARCH_SUSPEND_POSSIBLE=y\nCONFIG_ARM=y\nCONFIG_ARM_AMBA=y\nCONFIG_ARM_APPENDED_DTB=y\nCONFIG_ARM_ATAG_DTB_COMPAT=y\nCONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y\nCONFIG_ARM_CPU_SUSPEND=y\nCONFIG_ARM_HAS_SG_CHAIN=y\nCONFIG_ARM_L1_CACHE_SHIFT=5\nCONFIG_ARM_PATCH_PHYS_VIRT=y\nCONFIG_ARM_THUMB=y\nCONFIG_ARM_UNWIND=y\nCONFIG_ATAGS=y\nCONFIG_AUTO_ZRELADDR=y\nCONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y\nCONFIG_BLK_PM=y\nCONFIG_CLKSRC_MMIO=y\nCONFIG_CLONE_BACKWARDS=y\nCONFIG_CMDLINE=\"console=ttyAMA0,115200 root=/dev/mmcblk0p2 rw rootwait\"\nCONFIG_CMDLINE_FROM_BOOTLOADER=y\nCONFIG_COMMON_CLK=y\nCONFIG_COMPAT_32BIT_TIME=y\nCONFIG_COREDUMP=y\nCONFIG_CPU_32v5=y\nCONFIG_CPU_ABRT_EV5TJ=y\nCONFIG_CPU_ARM926T=y\n# CONFIG_CPU_CACHE_ROUND_ROBIN is not set\nCONFIG_CPU_CACHE_VIVT=y\nCONFIG_CPU_COPY_V4WB=y\nCONFIG_CPU_CP15=y\nCONFIG_CPU_CP15_MMU=y\n# CONFIG_CPU_DCACHE_WRITETHROUGH is not set\nCONFIG_CPU_IDLE=y\nCONFIG_CPU_IDLE_GOV_LADDER=y\nCONFIG_CPU_IDLE_GOV_MENU=y\nCONFIG_CPU_PABRT_LEGACY=y\nCONFIG_CPU_PM=y\nCONFIG_CPU_THUMB_CAPABLE=y\nCONFIG_CPU_TLB_V4WBI=y\nCONFIG_CPU_USE_DOMAINS=y\nCONFIG_CRC16=y\nCONFIG_CROSS_MEMORY_ATTACH=y\nCONFIG_CRYPTO_CBC=y\nCONFIG_CRYPTO_CRC32C=y\nCONFIG_CRYPTO_DEV_MXS_DCP=y\nCONFIG_CRYPTO_ECB=y\nCONFIG_CRYPTO_HW=y\nCONFIG_CRYPTO_RNG2=y\nCONFIG_DEBUG_ALIGN_RODATA=y\nCONFIG_DEBUG_LL_INCLUDE=\"mach/debug-macro.S\"\nCONFIG_DMADEVICES=y\nCONFIG_DMA_ENGINE=y\nCONFIG_DMA_OF=y\nCONFIG_DMA_OPS=y\nCONFIG_DMA_REMAP=y\nCONFIG_DTC=y\nCONFIG_EDAC_ATOMIC_SCRUB=y\nCONFIG_EDAC_SUPPORT=y\nCONFIG_EXT4_FS=y\nCONFIG_EXTCON=y\nCONFIG_FEC=y\nCONFIG_FIXED_PHY=y\nCONFIG_FIX_EARLYCON_MEM=y\nCONFIG_FS_IOMAP=y\nCONFIG_FS_MBCACHE=y\nCONFIG_FWNODE_MDIO=y\nCONFIG_FW_LOADER_PAGED_BUF=y\nCONFIG_GENERIC_ALLOCATOR=y\nCONFIG_GENERIC_ATOMIC64=y\nCONFIG_GENERIC_BUG=y\nCONFIG_GENERIC_CLOCKEVENTS=y\nCONFIG_GENERIC_CPU_AUTOPROBE=y\nCONFIG_GENERIC_EARLY_IOREMAP=y\nCONFIG_GENERIC_IDLE_POLL_SETUP=y\nCONFIG_GENERIC_IRQ_CHIP=y\nCONFIG_GENERIC_IRQ_MULTI_HANDLER=y\nCONFIG_GENERIC_IRQ_SHOW=y\nCONFIG_GENERIC_IRQ_SHOW_LEVEL=y\nCONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y\nCONFIG_GENERIC_PCI_IOMAP=y\nCONFIG_GENERIC_SCHED_CLOCK=y\nCONFIG_GENERIC_SMP_IDLE_THREAD=y\nCONFIG_GENERIC_STRNCPY_FROM_USER=y\nCONFIG_GENERIC_STRNLEN_USER=y\n# CONFIG_GIANFAR is not set\nCONFIG_GLOB=y\nCONFIG_GPIOLIB=y\nCONFIG_GPIO_CDEV=y\nCONFIG_GPIO_GENERIC=y\nCONFIG_GPIO_GENERIC_PLATFORM=y\nCONFIG_GPIO_MXS=y\nCONFIG_HANDLE_DOMAIN_IRQ=y\nCONFIG_HARDIRQS_SW_RESEND=y\nCONFIG_HAS_DMA=y\nCONFIG_HAS_IOMEM=y\nCONFIG_HAS_IOPORT_MAP=y\nCONFIG_HZ_FIXED=0\nCONFIG_HZ_PERIODIC=y\nCONFIG_I2C=y\nCONFIG_I2C_ALGOBIT=y\nCONFIG_I2C_ALGOPCA=y\nCONFIG_I2C_ALGOPCF=y\nCONFIG_I2C_BOARDINFO=y\nCONFIG_I2C_CHARDEV=y\nCONFIG_I2C_COMPAT=y\nCONFIG_I2C_MUX=y\nCONFIG_I2C_MUX_PINCTRL=y\nCONFIG_I2C_MXS=y\nCONFIG_IIO=y\nCONFIG_IIO_BUFFER=y\nCONFIG_IIO_KFIFO_BUF=y\nCONFIG_IIO_SYSFS_TRIGGER=y\nCONFIG_IIO_TRIGGER=y\n# CONFIG_IIO_TRIGGERED_BUFFER is not set\nCONFIG_INITRAMFS_SOURCE=\"\"\nCONFIG_INPUT=y\nCONFIG_IRQCHIP=y\nCONFIG_IRQ_DOMAIN=y\nCONFIG_IRQ_FORCED_THREADING=y\nCONFIG_IRQ_MXS=y\nCONFIG_IRQ_WORK=y\n# CONFIG_ISDN is not set\nCONFIG_JBD2=y\nCONFIG_LIBFDT=y\nCONFIG_LOCK_DEBUGGING_SUPPORT=y\nCONFIG_MDIO_BUS=y\nCONFIG_MDIO_DEVICE=y\nCONFIG_MDIO_DEVRES=y\nCONFIG_MEMFD_CREATE=y\nCONFIG_MFD_CORE=y\nCONFIG_MFD_MXS_LRADC=y\nCONFIG_MIGRATION=y\nCONFIG_MMC=y\nCONFIG_MMC_BLOCK=y\nCONFIG_MMC_MXS=y\nCONFIG_MODULES_USE_ELF_REL=y\nCONFIG_MXS_DMA=y\n# CONFIG_MXS_LRADC_ADC is not set\nCONFIG_MXS_TIMER=y\nCONFIG_NEED_DMA_MAP_STATE=y\nCONFIG_NEED_KUSER_HELPERS=y\nCONFIG_NEED_PER_CPU_KM=y\nCONFIG_NET_PTP_CLASSIFY=y\nCONFIG_NET_SELFTESTS=y\nCONFIG_NLS=y\nCONFIG_NVMEM=y\nCONFIG_NVMEM_MXS_OCOTP=y\nCONFIG_OF=y\nCONFIG_OF_ADDRESS=y\nCONFIG_OF_EARLY_FLATTREE=y\nCONFIG_OF_FLATTREE=y\nCONFIG_OF_GPIO=y\nCONFIG_OF_IRQ=y\nCONFIG_OF_KOBJ=y\nCONFIG_OF_MDIO=y\nCONFIG_OLD_SIGACTION=y\nCONFIG_OLD_SIGSUSPEND3=y\nCONFIG_PAGE_OFFSET=0xC0000000\nCONFIG_PERF_USE_VMALLOC=y\nCONFIG_PGTABLE_LEVELS=2\nCONFIG_PHYLIB=y\nCONFIG_PINCTRL=y\nCONFIG_PINCTRL_IMX23=y\nCONFIG_PINCTRL_IMX28=y\nCONFIG_PINCTRL_MXS=y\n# CONFIG_PINCTRL_SINGLE is not set\nCONFIG_PM=y\nCONFIG_PM_CLK=y\nCONFIG_POWER_SUPPLY=y\nCONFIG_PPS=y\nCONFIG_PTP_1588_CLOCK=y\nCONFIG_PTP_1588_CLOCK_OPTIONAL=y\nCONFIG_RATIONAL=y\nCONFIG_REGULATOR=y\nCONFIG_REGULATOR_FIXED_VOLTAGE=y\nCONFIG_REGULATOR_GPIO=y\nCONFIG_RESET_CONTROLLER=y\nCONFIG_RTC_CLASS=y\nCONFIG_RTC_DRV_STMP=y\nCONFIG_RTC_I2C_AND_SPI=y\nCONFIG_RTC_MC146818_LIB=y\n# CONFIG_SERIAL_8250 is not set\nCONFIG_SERIAL_AMBA_PL011=y\nCONFIG_SERIAL_AMBA_PL011_CONSOLE=y\nCONFIG_SERIAL_MCTRL_GPIO=y\nCONFIG_SERIAL_MXS_AUART=y\nCONFIG_SERIAL_MXS_AUART_CONSOLE=y\nCONFIG_SMSC_PHY=y\nCONFIG_SOC_BUS=y\nCONFIG_SOC_IMX23=y\nCONFIG_SOC_IMX28=y\nCONFIG_SPARSE_IRQ=y\nCONFIG_SPI=y\nCONFIG_SPI_MASTER=y\nCONFIG_SPI_MXS=y\nCONFIG_SPLIT_PTLOCK_CPUS=999999\nCONFIG_SRCU=y\nCONFIG_STMP3XXX_RTC_WATCHDOG=y\nCONFIG_STMP_DEVICE=y\nCONFIG_SWPHY=y\nCONFIG_SYS_SUPPORTS_APM_EMULATION=y\nCONFIG_TICK_CPU_ACCOUNTING=y\nCONFIG_TIMER_OF=y\nCONFIG_TIMER_PROBE=y\nCONFIG_TINY_SRCU=y\nCONFIG_UNCOMPRESS_INCLUDE=\"debug/uncompress.h\"\nCONFIG_UNWINDER_ARM=y\nCONFIG_USB=y\nCONFIG_USB_CHIPIDEA=y\nCONFIG_USB_CHIPIDEA_HOST=y\nCONFIG_USB_CHIPIDEA_IMX=y\nCONFIG_USB_CHIPIDEA_UDC=y\nCONFIG_USB_COMMON=y\nCONFIG_USB_EHCI_HCD=y\n# CONFIG_USB_EHCI_HCD_PLATFORM is not set\nCONFIG_USB_GADGET=y\nCONFIG_USB_MXS_PHY=y\nCONFIG_USB_OTG=y\nCONFIG_USB_PHY=y\nCONFIG_USB_ROLE_SWITCH=y\nCONFIG_USB_SUPPORT=y\nCONFIG_USB_ULPI_BUS=y\nCONFIG_USE_OF=y\n# CONFIG_VFP is not set\nCONFIG_WATCHDOG_CORE=y\nCONFIG_XZ_DEC_ARM=y\nCONFIG_XZ_DEC_BCJ=y\nCONFIG_ZBOOT_ROM_BSS=0\nCONFIG_ZBOOT_ROM_TEXT=0\n"
  },
  {
    "path": "target/linux/mxs/image/Config.in",
    "content": "config TARGET_BOOTFS_PARTSIZE\n\tint \"Boot (SD Card) filesystem partition size (in MB)\"\n\tdepends on TARGET_mxs_olinuxino-maxi || TARGET_mxs_olinuxino-micro\n\tdefault 8\n\thelp\n\t    On the Olimex OLinuXino boards, mainline U-Boot loads the\n\t    linux kernel and device tree file from a FAT partition.\n\t    The default value of 8 MB should be more than adequate.\n"
  },
  {
    "path": "target/linux/mxs/image/Makefile",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2013-2015 OpenWrt.org\n\ninclude $(TOPDIR)/rules.mk\ninclude $(INCLUDE_DIR)/image.mk\n\nBOARDS:= \\\n\timx23-olinuxino \\\n\timx28-duckbill\n\nFAT32_BLOCK_SIZE=1024\nFAT32_BLOCKS=$(shell echo $$(($(CONFIG_TARGET_BOOTFS_PARTSIZE)*1024*1024/$(FAT32_BLOCK_SIZE))))\n\ndefine Image/BuildKernel\n\tmkimage -A arm -O linux -T kernel -C none \\\n\t\t-a 0x40008000 -e 0x40008000 \\\n\t\t-n 'ARM OpenWrt Linux-$(LINUX_VERSION)' \\\n\t\t-d $(KDIR)/zImage $(KDIR)/uImage\n\tcp $(KDIR)/uImage $(BIN_DIR)/$(IMG_PREFIX)-uImage\nendef\n\ndefine Image/InstallKernel\n\tmkdir -p $(TARGET_DIR)/boot\n\tcp \\\n\t\t$(KDIR)/zImage $(KDIR)/uImage \\\n\t\t$(foreach board,$(BOARDS),$(DTS_DIR)/$(board).dtb) \\\n\t\t$(TARGET_DIR)/boot/\nendef\n\ndefine Image/Build/SDCard-vfat-ext4\n\trm -f $(KDIR)/boot.img\n\tmkfs.fat $(KDIR)/boot.img -C $(FAT32_BLOCKS)\n\n\tmcopy -i $(KDIR)/boot.img $(DTS_DIR)/$(3).dtb ::$(3).dtb\n\tmcopy -i $(KDIR)/boot.img $(BIN_DIR)/$(IMG_PREFIX)-uImage ::uImage\n\n\t./gen_sdcard_vfat_ext4.sh \\\n\t\t$(BIN_DIR)/$(2) \\\n\t\t$(STAGING_DIR_IMAGE)/$(4)-u-boot.sb \\\n\t\t$(KDIR)/boot.img \\\n\t\t$(KDIR)/root.$(1) \\\n\t\t$(CONFIG_TARGET_BOOTFS_PARTSIZE) \\\n\t\t$(CONFIG_TARGET_ROOTFS_PARTSIZE)\n\t$(call Image/Gzip,$(BIN_DIR)/$(2))\nendef\n\ndefine Image/Build/SDCard-ext4-ext4\n\t./gen_sdcard_ext4_ext4.sh \\\n\t\t$(BIN_DIR)/$(2) \\\n\t\t$(STAGING_DIR_IMAGE)/$(4)-u-boot.sb \\\n\t\t$(KDIR)/root.$(1) \\\n\t\t$(CONFIG_TARGET_ROOTFS_PARTSIZE)\n\t$(call Image/Gzip,$(BIN_DIR)/$(2))\nendef\n\ndefine Image/Build/Profile/olinuxino-maxi\n\t$(call Image/Build/SDCard-vfat-ext4,$(1),$(2),imx23-olinuxino,mx23_olinuxino)\nendef\n\ndefine Image/Build/Profile/olinuxino-micro\n\t$(call Image/Build/SDCard-vfat-ext4,$(1),$(2),imx23-olinuxino,mx23_olinuxino)\nendef\n\ndefine Image/Build/Profile/duckbill\n\t$(call Image/Build/SDCard-ext4-ext4,$(1),$(2),imx28-duckbill,duckbill)\nendef\n\ndefine Image/Build\n\t$(call Image/Build/$(1),$(1))\n\t$(call Image/Build/Profile/$(PROFILE),$(1),$(IMG_PREFIX)-$(PROFILE)-sdcard.img)\n\tdd if=$(KDIR)/root.$(1) of=$(BIN_DIR)/$(IMG_PREFIX)-root.$(1) bs=128k conv=sync\n\t$(call Image/Gzip,$(BIN_DIR)/$(IMG_PREFIX)-root.$(1))\nendef\n\n$(eval $(call BuildImage))\n"
  },
  {
    "path": "target/linux/mxs/image/gen_sdcard_ext4_ext4.sh",
    "content": "#!/bin/sh\n# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2015 OpenWrt.org\n\nset -x\n[ $# -eq 4 ] || {\n    echo \"SYNTAX: $0 <file> <u-boot.sb image> <rootfs image> <rootfs size>\"\n    exit 1\n}\n\nOUTPUT=\"$1\"\nUBOOT=\"$2\"\nROOTFS=\"$3\"\nROOTFSSIZE=\"$4\"\n\nhead=4\nsect=63\n\n# set the Boot stream partition size to 1M\nset $(ptgen -o $OUTPUT -h $head -s $sect -l 1024 -t 53 -p 1M -t 83 -p ${ROOTFSSIZE}M -t 83 -p ${ROOTFSSIZE}M)\n\nROOTFS1OFFSET=\"$(($3 / 512))\"\nROOTFS1SIZE=\"$(($4 / 512))\"\nROOTFS2OFFSET=\"$(($5 / 512))\"\nROOTFS2SIZE=\"$(($6 / 512))\"\n\ndd bs=512 if=\"$ROOTFS\" of=\"$OUTPUT\" seek=\"$ROOTFS1OFFSET\" conv=notrunc\ndd bs=512 if=\"$ROOTFS\" of=\"$OUTPUT\" seek=\"$ROOTFS2OFFSET\" conv=notrunc\nsdimage -d \"$OUTPUT\" -f \"$UBOOT\"\n"
  },
  {
    "path": "target/linux/mxs/image/gen_sdcard_vfat_ext4.sh",
    "content": "#!/bin/sh\n# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2015 OpenWrt.org\n\nset -x\n[ $# -eq 6 ] || {\n    echo \"SYNTAX: $0 <file> <u-boot.sb image> <bootfs image> <rootfs image> <bootfs size> <rootfs size>\"\n    exit 1\n}\n\nOUTPUT=\"$1\"\nUBOOT=\"$2\"\nBOOTFS=\"$3\"\nROOTFS=\"$4\"\nBOOTFSSIZE=\"$5\"\nROOTFSSIZE=\"$6\"\n\nhead=4\nsect=63\n\n# Set the u-boot storage to 2M\nset $(ptgen -o $OUTPUT -h $head -s $sect -l 1024 -t 53 -p 2M -t c -p ${BOOTFSSIZE}M -t 83 -p ${ROOTFSSIZE}M)\n\nUBOOTOFFSET=\"$(($1 / 512))\"\nUBOOTSIZE=\"$(($2 / 512))\"\nBOOTOFFSET=\"$(($3 / 512))\"\nBOOTSIZE=\"$(($4 / 512))\"\nROOTFSOFFSET=\"$(($5 / 512))\"\nROOTFSSIZE=\"$(($6 / 512))\"\n\ndd bs=512 if=\"$BOOTFS\" of=\"$OUTPUT\" seek=\"$BOOTOFFSET\" conv=notrunc\ndd bs=512 if=\"$ROOTFS\" of=\"$OUTPUT\" seek=\"$ROOTFSOFFSET\" conv=notrunc\nsdimage -d \"$OUTPUT\" -f \"$UBOOT\"\n"
  },
  {
    "path": "target/linux/mxs/profiles/01-duckbill.mk",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2013 OpenWrt.org\n\ndefine Profile/duckbill\n  NAME:=I2SE Duckbill boards\n  FEATURES+=usbgadget\n  PACKAGES+= \\\n\t-dnsmasq -firewall -ppp -ip6tables -iptables -6relayd -mtd uboot-envtools \\\n\tkmod-leds-gpio -kmod-ipt-nathelper uboot-mxs-duckbill\nendef\n\ndefine Profile/duckbill/Description\n\tI2SE's Duckbill devices\nendef\n\n$(eval $(call Profile,duckbill))\n"
  },
  {
    "path": "target/linux/mxs/profiles/02-olinuxino-maxi.mk",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2013 OpenWrt.org\n\ndefine Profile/olinuxino-maxi\n  NAME:=Olimex OLinuXino Maxi/Mini boards\n  PACKAGES += imx-bootlets uboot-mxs-mx23_olinuxino \\\n\t  kmod-usb-net-smsc95xx kmod-gpio-mcp23s08 \\\n\t  kmod-leds-gpio kmod-sound-core\nendef\n\ndefine Profile/olinuxino-maxi/Description\n\tOlimex OLinuXino Maxi/Mini boards\nendef\n\n$(eval $(call Profile,olinuxino-maxi))\n"
  },
  {
    "path": "target/linux/mxs/profiles/03-olinuxino-micro.mk",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2013 OpenWrt.org\n\ndefine Profile/olinuxino-micro\n  NAME:=Olimex OLinuXino Micro/Nano boards\n  PACKAGES += imx-bootlets uboot-mxs-mx23_olinuxino \\\n\t  kmod-gpio-mcp23s08 kmod-leds-gpio\nendef\n\ndefine Profile/olinuxino-micro/Description\n\tOlimex OLinuXino Micro/Nano boards\nendef\n\n$(eval $(call Profile,olinuxino-micro))\n"
  },
  {
    "path": "target/linux/octeon/Makefile",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2013 OpenWrt.org\n\ninclude $(TOPDIR)/rules.mk\n\nARCH:=mips64\nBOARD:=octeon\nBOARDNAME:=Cavium Networks Octeon\nFEATURES:=squashfs ramdisk pci usb\nCPU_TYPE:=octeonplus\n\nKERNEL_PATCHVER:=5.10\nKERNEL_TESTING_PATCHVER:=5.15\n\ndefine Target/Description\n\tBuild firmware images for Cavium Networks Octeon-based boards.\nendef\n\ninclude $(INCLUDE_DIR)/target.mk\n\nDEFAULT_PACKAGES += mkf2fs e2fsprogs\n\n$(eval $(call BuildTarget))\n"
  },
  {
    "path": "target/linux/octeon/base-files/etc/board.d/01_network",
    "content": "#\n# Copyright (C) 2014-2015 OpenWrt.org\n#\n\n. /lib/functions/uci-defaults.sh\n\nboard_config_update\n\ncase \"$(board_name)\" in\nitus,shield-router)\n\tucidef_set_interfaces_lan_wan \"eth1 eth2\" \"eth0\"\n\t;;\nubnt,edgerouter-4)\n\tucidef_set_interfaces_lan_wan \"lan1 lan2 lan3\" \"lan0\"\n\t;;\nubnt,edgerouter-6p)\n\tucidef_set_interfaces_lan_wan \"lan1 lan2 lan3 lan4 lan5\" \"lan0\"\n\t;;\n*)\n\tucidef_set_interfaces_lan_wan \"eth0\" \"eth1\"\n\t;;\nesac\n\nboard_config_flush\n\nexit 0\n"
  },
  {
    "path": "target/linux/octeon/base-files/lib/preinit/01_sysinfo",
    "content": "do_sysinfo_octeon() {\n\tlocal machine\n\tlocal name\n\n\tmachine=$(grep \"^system type\" /proc/cpuinfo | sed \"s/system type.*: \\(.*\\)/\\1/g\")\n\n\tcase \"$machine\" in\n\t\"UBNT_E100\"*)\n\t\tname=\"erlite\"\n\t\t;;\n\n\t\"UBNT_E200\"*)\n\t\tname=\"er\"\n\t\t;;\n\n\t\"UBNT_E220\"*)\n\t\tname=\"erpro\"\n\t\t;;\n\n\t\"UBNT_E300\"*)\n\t\t# let generic 02_sysinfo handle it since device has its own device tree\n\t\treturn 0\n\t\t;;\n\n\t\"ITUS_SHIELD\"*)\n\t\tname=\"itus,shield-router\"\n\t\t;;\n\n\t*)\n\t\tname=\"generic\"\n\t\t;;\n\tesac\n\n\t[ -e \"/tmp/sysinfo/\" ] || mkdir -p \"/tmp/sysinfo/\"\n\n\techo \"$name\" > /tmp/sysinfo/board_name\n\techo \"$machine\" > /tmp/sysinfo/model\n}\n\nboot_hook_add preinit_main do_sysinfo_octeon\n"
  },
  {
    "path": "target/linux/octeon/base-files/lib/preinit/79_move_config",
    "content": "# Copyright (C) 2014 OpenWrt.org\n\nmove_config() {\n\t. /lib/upgrade/common.sh\n\n\tlocal device=\"$1\"\n\t[ -n \"$device\" ] && [ -b \"$device\" ] && {\n\t\tmount -t vfat \"$device\" /mnt\n\t\t[ -f \"/mnt/$BACKUP_FILE\" ] && mv -f \"/mnt/$BACKUP_FILE\" /\n\t\tumount /mnt\n\t}\n}\n\nocteon_move_config() {\n\t. /lib/functions.sh\n\n\tcase \"$(board_name)\" in\n\t\terlite)\n\t\t\tmove_config \"/dev/sda1\"\n\t\t\t;;\n\t\titus,shield-router)\n\t\t\tmove_config \"/dev/mmcblk1p1\"\n\t\t\t;;\n\t\tubnt,edgerouter-4 | \\\n\t\tubnt,edgerouter-6p)\n\t\t\tmove_config \"/dev/mmcblk0p1\"\n\t\t\t;;\n\tesac\n}\n\nboot_hook_add preinit_mount_root octeon_move_config\n"
  },
  {
    "path": "target/linux/octeon/base-files/lib/upgrade/platform.sh",
    "content": "#\n# Copyright (C) 2021 OpenWrt.org\n#\n\nplatform_get_rootfs() {\n\tlocal rootfsdev\n\n\tif read cmdline < /proc/cmdline; then\n\t\tcase \"$cmdline\" in\n\t\t\t*root=*)\n\t\t\t\trootfsdev=\"${cmdline##*root=}\"\n\t\t\t\trootfsdev=\"${rootfsdev%% *}\"\n\t\t\t;;\n\t\tesac\n\n\t\techo \"${rootfsdev}\"\n\tfi\n}\n\nplatform_copy_config_helper() {\n\tlocal device=$1\n\n\tmount -t vfat \"$device\" /mnt\n\tcp -af \"$UPGRADE_BACKUP\" \"/mnt/$BACKUP_FILE\"\n\tumount /mnt\n}\n\nplatform_copy_config() {\n\tcase \"$(board_name)\" in\n\terlite)\n\t\tplatform_copy_config_helper /dev/sda1\n\t\t;;\n\titus,shield-router)\n\t\tplatform_copy_config_helper /dev/mmcblk1p1\n\t\t;;\n\tubnt,edgerouter-4|\\\n\tubnt,edgerouter-6p)\n\t\tplatform_copy_config_helper /dev/mmcblk0p1\n\t\t;;\n\tesac\n}\n\nplatform_do_flash() {\n\tlocal tar_file=$1\n\tlocal board=$2\n\tlocal kernel=$3\n\tlocal rootfs=$4\n\n\tlocal board_dir=$(tar tf \"$tar_file\" | grep -m 1 '^sysupgrade-.*/$')\n\tboard_dir=${board_dir%/}\n\t[ -n \"$board_dir\" ] || return 1\n\n\tmkdir -p /boot\n\n\tif [ $board = \"itus,shield-router\" ]; then\n\t\t# mmcblk1p1 (fat) contains all ELF-bin images for the Shield\n\t\tmount /dev/mmcblk1p1 /boot\n\n\t\techo \"flashing Itus Kernel to /boot/$kernel (/dev/mmblk1p1)\"\n\t\ttar -Oxf $tar_file \"$board_dir/kernel\" > /boot/$kernel\n\telse\n\t\tmount -t vfat /dev/$kernel /boot\n\n\t\t[ -f /boot/vmlinux.64 -a ! -L /boot/vmlinux.64 ] && {\n\t\t\tmv /boot/vmlinux.64 /boot/vmlinux.64.previous\n\t\t\tmv /boot/vmlinux.64.md5 /boot/vmlinux.64.md5.previous\n\t\t}\n\n\t\techo \"flashing kernel to /dev/$kernel\"\n\t\ttar xf $tar_file $board_dir/kernel -O > /boot/vmlinux.64\n\t\tmd5sum /boot/vmlinux.64 | cut -f1 -d \" \" > /boot/vmlinux.64.md5\n\tfi\n\n\techo \"flashing rootfs to ${rootfs}\"\n\ttar xf $tar_file $board_dir/root -O | dd of=\"${rootfs}\" bs=4096\n\n\tsync\n\tumount /boot\n}\n\nplatform_do_upgrade() {\n\tlocal tar_file=\"$1\"\n\tlocal board=$(board_name)\n\tlocal rootfs=\"$(platform_get_rootfs)\"\n\tlocal kernel=\n\n\t[ -b \"${rootfs}\" ] || return 1\n\tcase \"$board\" in\n\ter | \\\n\tubnt,edgerouter-4 | \\\n\tubnt,edgerouter-6p)\n\t\tkernel=mmcblk0p1\n\t\t;;\n\terlite)\n\t\tkernel=sda1\n\t\t;;\n\titus,shield-router)\n\t\tkernel=ItusrouterImage\n\t\t;;\n\t*)\n\t\treturn 1\n\tesac\n\n\tplatform_do_flash $tar_file $board $kernel $rootfs\n\n\treturn 0\n}\n\nplatform_check_image() {\n\tlocal board=$(board_name)\n\tlocal tar_file=\"$1\"\n\n\tlocal board_dir=$(tar tf \"$tar_file\" | grep -m 1 '^sysupgrade-.*/$')\n\tboard_dir=${board_dir%/}\n\t[ -n \"$board_dir\" ] || return 1\n\n\tcase \"$board\" in\n\ter | \\\n\terlite | \\\n\titus,shield-router | \\\n\tubnt,edgerouter-4 | \\\n\tubnt,edgerouter-6p)\n\t\tlocal kernel_length=$(tar xf $tar_file $board_dir/kernel -O | wc -c 2> /dev/null)\n\t\tlocal rootfs_length=$(tar xf $tar_file $board_dir/root -O | wc -c 2> /dev/null)\n\t\t[ \"$kernel_length\" = 0 -o \"$rootfs_length\" = 0 ] && {\n\t\t\techo \"The upgrade image is corrupt.\"\n\t\t\treturn 1\n\t\t}\n\t\treturn 0\n\t\t;;\n\tesac\n\n\techo \"Sysupgrade is not yet supported on $board.\"\n\treturn 1\n}\n"
  },
  {
    "path": "target/linux/octeon/config-5.10",
    "content": "CONFIG_64BIT=y\nCONFIG_ARCH_DMA_ADDR_T_64BIT=y\nCONFIG_ARCH_HIBERNATION_POSSIBLE=y\nCONFIG_ARCH_MMAP_RND_BITS=12\nCONFIG_ARCH_MMAP_RND_BITS_MAX=18\nCONFIG_ARCH_MMAP_RND_BITS_MIN=12\nCONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15\nCONFIG_ARCH_SPARSEMEM_ENABLE=y\nCONFIG_ARCH_SUSPEND_POSSIBLE=y\nCONFIG_BLK_DEV_LOOP=y\nCONFIG_BLK_DEV_SD=y\nCONFIG_BLK_MQ_PCI=y\nCONFIG_BLK_SCSI_REQUEST=y\nCONFIG_BUILTIN_DTB=y\nCONFIG_CAVIUM_CN63XXP1=y\nCONFIG_CAVIUM_OCTEON_CVMSEG_SIZE=0\nCONFIG_CAVIUM_OCTEON_LOCK_L2=y\nCONFIG_CAVIUM_OCTEON_LOCK_L2_EXCEPTION=y\nCONFIG_CAVIUM_OCTEON_LOCK_L2_INTERRUPT=y\nCONFIG_CAVIUM_OCTEON_LOCK_L2_LOW_LEVEL_INTERRUPT=y\nCONFIG_CAVIUM_OCTEON_LOCK_L2_MEMCPY=y\nCONFIG_CAVIUM_OCTEON_LOCK_L2_TLB=y\nCONFIG_CAVIUM_OCTEON_SOC=y\nCONFIG_CEVT_R4K=y\nCONFIG_CLONE_BACKWARDS=y\n# CONFIG_COMMON_CLK is not set\nCONFIG_COMPAT_32BIT_TIME=y\nCONFIG_CPU_BIG_ENDIAN=y\nCONFIG_CPU_CAVIUM_OCTEON=y\nCONFIG_CPU_GENERIC_DUMP_TLB=y\nCONFIG_CPU_HAS_DIEI=y\nCONFIG_CPU_HAS_PREFETCH=y\nCONFIG_CPU_HAS_RIXI=y\nCONFIG_CPU_HAS_SYNC=y\n# CONFIG_CPU_LITTLE_ENDIAN is not set\nCONFIG_CPU_MIPS64=y\nCONFIG_CPU_MIPSR2=y\nCONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y\nCONFIG_CPU_RMAP=y\nCONFIG_CPU_SUPPORTS_64BIT_KERNEL=y\nCONFIG_CPU_SUPPORTS_HIGHMEM=y\nCONFIG_CPU_SUPPORTS_HUGEPAGES=y\nCONFIG_CRAMFS=y\nCONFIG_CRC16=y\nCONFIG_CRYPTO_CRC32=y\nCONFIG_CRYPTO_CRC32C=y\nCONFIG_CRYPTO_LIB_POLY1305_RSIZE=2\n# CONFIG_CRYPTO_MD5_OCTEON is not set\nCONFIG_CRYPTO_RNG2=y\n# CONFIG_CRYPTO_SHA1_OCTEON is not set\n# CONFIG_CRYPTO_SHA256_OCTEON is not set\n# CONFIG_CRYPTO_SHA512_OCTEON is not set\nCONFIG_DNOTIFY=y\nCONFIG_DTC=y\nCONFIG_EARLY_PRINTK=y\nCONFIG_EDAC=y\nCONFIG_EDAC_ATOMIC_SCRUB=y\n# CONFIG_EDAC_DEBUG is not set\nCONFIG_EDAC_LEGACY_SYSFS=y\nCONFIG_EDAC_OCTEON_L2C=y\nCONFIG_EDAC_OCTEON_LMC=y\nCONFIG_EDAC_OCTEON_PC=y\nCONFIG_EDAC_OCTEON_PCI=y\nCONFIG_EDAC_SUPPORT=y\nCONFIG_ENABLE_MUST_CHECK=y\nCONFIG_EXT4_FS=y\nCONFIG_F2FS_FS=y\nCONFIG_FAT_FS=y\nCONFIG_FIXED_PHY=y\nCONFIG_FRAME_WARN=2048\nCONFIG_FS_IOMAP=y\nCONFIG_FS_MBCACHE=y\nCONFIG_FW_LOADER_PAGED_BUF=y\nCONFIG_GENERIC_ALLOCATOR=y\nCONFIG_GENERIC_CLOCKEVENTS=y\nCONFIG_GENERIC_CMOS_UPDATE=y\nCONFIG_GENERIC_CPU_AUTOPROBE=y\nCONFIG_GENERIC_GETTIMEOFDAY=y\nCONFIG_GENERIC_IOMAP=y\nCONFIG_GENERIC_IRQ_SHOW=y\nCONFIG_GENERIC_LIB_ASHLDI3=y\nCONFIG_GENERIC_LIB_ASHRDI3=y\nCONFIG_GENERIC_LIB_CMPDI2=y\nCONFIG_GENERIC_LIB_LSHRDI3=y\nCONFIG_GENERIC_LIB_UCMPDI2=y\nCONFIG_GENERIC_PCI_IOMAP=y\nCONFIG_GENERIC_SMP_IDLE_THREAD=y\nCONFIG_GENERIC_TIME_VSYSCALL=y\nCONFIG_GPIOLIB=y\nCONFIG_GPIO_OCTEON=y\nCONFIG_GRO_CELLS=y\nCONFIG_HANDLE_DOMAIN_IRQ=y\nCONFIG_HARDWARE_WATCHPOINTS=y\nCONFIG_HAS_DMA=y\nCONFIG_HAS_IOMEM=y\nCONFIG_HAS_IOPORT_MAP=y\nCONFIG_HOLES_IN_ZONE=y\nCONFIG_HW_RANDOM=y\nCONFIG_HW_RANDOM_OCTEON=y\nCONFIG_HZ_PERIODIC=y\nCONFIG_I2C=y\nCONFIG_I2C_BOARDINFO=y\nCONFIG_I2C_OCTEON=y\nCONFIG_IMAGE_CMDLINE_HACK=y\nCONFIG_INITRAMFS_SOURCE=\"\"\nCONFIG_IRQCHIP=y\nCONFIG_IRQ_DOMAIN=y\nCONFIG_IRQ_FORCED_THREADING=y\nCONFIG_IRQ_WORK=y\nCONFIG_JBD2=y\nCONFIG_LIBFDT=y\nCONFIG_LOCK_DEBUGGING_SUPPORT=y\nCONFIG_MDIO_BUS=y\nCONFIG_MDIO_CAVIUM=y\nCONFIG_MDIO_DEVICE=y\nCONFIG_MDIO_DEVRES=y\nCONFIG_MDIO_OCTEON=y\nCONFIG_MEMFD_CREATE=y\nCONFIG_MIGRATION=y\nCONFIG_MIPS=y\n# CONFIG_MIPS32_N32 is not set\n# CONFIG_MIPS32_O32 is not set\nCONFIG_MIPS_ASID_BITS=8\nCONFIG_MIPS_ASID_SHIFT=0\n# CONFIG_MIPS_CMDLINE_DTB_EXTEND is not set\nCONFIG_MIPS_CMDLINE_FROM_BOOTLOADER=y\n# CONFIG_MIPS_CMDLINE_FROM_DTB is not set\nCONFIG_MIPS_EBPF_JIT=y\nCONFIG_MIPS_ELF_APPENDED_DTB=y\nCONFIG_MIPS_L1_CACHE_SHIFT=7\nCONFIG_MIPS_L1_CACHE_SHIFT_7=y\nCONFIG_MIPS_LD_CAN_LINK_VDSO=y\n# CONFIG_MIPS_NO_APPENDED_DTB is not set\nCONFIG_MIPS_NR_CPU_NR_MAP=1024\nCONFIG_MIPS_NR_CPU_NR_MAP_1024=y\nCONFIG_MIPS_PGD_C0_CONTEXT=y\n# CONFIG_MIPS_RAW_APPENDED_DTB is not set\nCONFIG_MIPS_SPRAM=y\n# CONFIG_MIPS_VA_BITS_48 is not set\nCONFIG_MMC=y\nCONFIG_MMC_BLOCK=y\nCONFIG_MMC_CAVIUM_OCTEON=y\nCONFIG_MODULES_USE_ELF_REL=y\nCONFIG_MODULES_USE_ELF_RELA=y\n# CONFIG_MTD_CFI_INTELEXT is not set\nCONFIG_MTD_CMDLINE_PARTS=y\nCONFIG_MTD_PHYSMAP=y\nCONFIG_MTD_SPI_NOR=y\nCONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y\nCONFIG_NEED_DMA_MAP_STATE=y\nCONFIG_NET_DEVLINK=y\nCONFIG_NET_DSA=y\nCONFIG_NET_FLOW_LIMIT=y\nCONFIG_NET_SWITCHDEV=y\nCONFIG_NLS=y\nCONFIG_NLS_CODEPAGE_437=y\nCONFIG_NLS_ISO8859_1=y\nCONFIG_NO_GENERIC_PCI_IOPORT_MAP=y\nCONFIG_NR_CPUS=16\nCONFIG_NR_CPUS_DEFAULT_64=y\nCONFIG_NVMEM=y\nCONFIG_OCTEON_ETHERNET=y\nCONFIG_OCTEON_ILM=y\nCONFIG_OCTEON_MGMT_ETHERNET=y\nCONFIG_OCTEON_USB=y\nCONFIG_OCTEON_WDT=y\nCONFIG_OF=y\nCONFIG_OF_ADDRESS=y\nCONFIG_OF_EARLY_FLATTREE=y\nCONFIG_OF_FLATTREE=y\nCONFIG_OF_GPIO=y\nCONFIG_OF_IRQ=y\nCONFIG_OF_KOBJ=y\nCONFIG_OF_MDIO=y\nCONFIG_OF_NET=y\nCONFIG_PADATA=y\n# CONFIG_PARTITION_ADVANCED is not set\nCONFIG_PCI=y\nCONFIG_PCIEAER=y\nCONFIG_PCIEPORTBUS=y\nCONFIG_PCI_DOMAINS=y\nCONFIG_PCI_DRIVERS_LEGACY=y\nCONFIG_PERF_USE_VMALLOC=y\nCONFIG_PGTABLE_LEVELS=3\nCONFIG_PHYLIB=y\nCONFIG_PHYLINK=y\nCONFIG_PHYS_ADDR_T_64BIT=y\nCONFIG_POSIX_MQUEUE=y\nCONFIG_POSIX_MQUEUE_SYSCTL=y\nCONFIG_QUEUED_RWLOCKS=y\nCONFIG_QUEUED_SPINLOCKS=y\nCONFIG_RAS=y\nCONFIG_RELAY=y\nCONFIG_RFS_ACCEL=y\nCONFIG_RPS=y\nCONFIG_SCSI=y\nCONFIG_SECCOMP=y\nCONFIG_SECCOMP_FILTER=y\nCONFIG_SERIAL_8250_DW=y\nCONFIG_SERIAL_8250_DWLIB=y\nCONFIG_SERIAL_MCTRL_GPIO=y\nCONFIG_SG_POOL=y\nCONFIG_SMP=y\nCONFIG_SPARSEMEM=y\nCONFIG_SPARSEMEM_STATIC=y\nCONFIG_SPI=y\nCONFIG_SPI_MASTER=y\nCONFIG_SPI_MEM=y\nCONFIG_SPI_OCTEON=y\nCONFIG_SRCU=y\nCONFIG_SWIOTLB=y\nCONFIG_SWPHY=y\nCONFIG_SYSCTL_EXCEPTION_TRACE=y\nCONFIG_SYS_HAS_CPU_CAVIUM_OCTEON=y\nCONFIG_SYS_HAS_EARLY_PRINTK=y\nCONFIG_SYS_SUPPORTS_64BIT_KERNEL=y\nCONFIG_SYS_SUPPORTS_ARBIT_HZ=y\nCONFIG_SYS_SUPPORTS_BIG_ENDIAN=y\nCONFIG_SYS_SUPPORTS_HOTPLUG_CPU=y\nCONFIG_SYS_SUPPORTS_HUGETLBFS=y\nCONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y\nCONFIG_SYS_SUPPORTS_RELOCATABLE=y\nCONFIG_SYS_SUPPORTS_SMP=y\nCONFIG_TARGET_ISA_REV=2\nCONFIG_TICK_CPU_ACCOUNTING=y\nCONFIG_TREE_RCU=y\nCONFIG_TREE_SRCU=y\nCONFIG_USB=y\nCONFIG_USB_COMMON=y\nCONFIG_USB_EHCI_BIG_ENDIAN_MMIO=y\nCONFIG_USB_EHCI_HCD=y\nCONFIG_USB_EHCI_HCD_PLATFORM=y\nCONFIG_USB_XHCI_HCD=y\nCONFIG_USB_XHCI_PLATFORM=y\n# CONFIG_USB_OCTEON_EHCI is not set\n# CONFIG_USB_OCTEON_OHCI is not set\nCONFIG_USB_OHCI_BIG_ENDIAN_MMIO=y\nCONFIG_USB_OHCI_HCD=y\nCONFIG_USB_OHCI_HCD_PLATFORM=y\nCONFIG_USB_STORAGE=y\nCONFIG_USB_SUPPORT=y\nCONFIG_USE_OF=y\nCONFIG_VFAT_FS=y\nCONFIG_VITESSE_PHY=y\nCONFIG_VM_EVENT_COUNTERS=y\nCONFIG_WATCHDOG_CORE=y\nCONFIG_WEAK_ORDERING=y\nCONFIG_XPS=y\nCONFIG_ZLIB_INFLATE=y\nCONFIG_ZONE_DMA32=y\n"
  },
  {
    "path": "target/linux/octeon/config-5.15",
    "content": "CONFIG_64BIT=y\nCONFIG_AHCI_OCTEON=y\nCONFIG_ARCH_DMA_ADDR_T_64BIT=y\nCONFIG_ARCH_HIBERNATION_POSSIBLE=y\nCONFIG_ARCH_KEEP_MEMBLOCK=y\nCONFIG_ARCH_MMAP_RND_BITS=12\nCONFIG_ARCH_MMAP_RND_BITS_MAX=18\nCONFIG_ARCH_MMAP_RND_BITS_MIN=12\nCONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15\nCONFIG_ARCH_SPARSEMEM_ENABLE=y\nCONFIG_ARCH_SUSPEND_POSSIBLE=y\nCONFIG_ATA=y\nCONFIG_BLK_DEV_LOOP=y\nCONFIG_BLK_DEV_SD=y\nCONFIG_BLK_MQ_PCI=y\nCONFIG_BUILTIN_DTB=y\nCONFIG_CAVIUM_CN63XXP1=y\nCONFIG_CAVIUM_OCTEON_CVMSEG_SIZE=0\nCONFIG_CAVIUM_OCTEON_LOCK_L2=y\nCONFIG_CAVIUM_OCTEON_LOCK_L2_EXCEPTION=y\nCONFIG_CAVIUM_OCTEON_LOCK_L2_INTERRUPT=y\nCONFIG_CAVIUM_OCTEON_LOCK_L2_LOW_LEVEL_INTERRUPT=y\nCONFIG_CAVIUM_OCTEON_LOCK_L2_MEMCPY=y\nCONFIG_CAVIUM_OCTEON_LOCK_L2_TLB=y\nCONFIG_CAVIUM_OCTEON_SOC=y\nCONFIG_CEVT_R4K=y\nCONFIG_CLONE_BACKWARDS=y\n# CONFIG_COMMON_CLK is not set\nCONFIG_COMPAT_32BIT_TIME=y\nCONFIG_CPU_BIG_ENDIAN=y\nCONFIG_CPU_CAVIUM_OCTEON=y\nCONFIG_CPU_GENERIC_DUMP_TLB=y\nCONFIG_CPU_HAS_DIEI=y\nCONFIG_CPU_HAS_PREFETCH=y\nCONFIG_CPU_HAS_RIXI=y\nCONFIG_CPU_HAS_SYNC=y\n# CONFIG_CPU_LITTLE_ENDIAN is not set\nCONFIG_CPU_MIPS64=y\nCONFIG_CPU_MIPSR2=y\nCONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y\nCONFIG_CPU_R4K_FPU=y\nCONFIG_CPU_RMAP=y\nCONFIG_CPU_SUPPORTS_64BIT_KERNEL=y\nCONFIG_CPU_SUPPORTS_HIGHMEM=y\nCONFIG_CPU_SUPPORTS_HUGEPAGES=y\nCONFIG_CRAMFS=y\nCONFIG_CRC16=y\nCONFIG_CRYPTO_CRC32=y\nCONFIG_CRYPTO_CRC32C=y\nCONFIG_CRYPTO_LIB_POLY1305_RSIZE=2\n# CONFIG_CRYPTO_MD5_OCTEON is not set\nCONFIG_CRYPTO_RNG2=y\n# CONFIG_CRYPTO_SHA1_OCTEON is not set\n# CONFIG_CRYPTO_SHA256_OCTEON is not set\n# CONFIG_CRYPTO_SHA512_OCTEON is not set\nCONFIG_DNOTIFY=y\nCONFIG_DTC=y\nCONFIG_EARLY_PRINTK=y\nCONFIG_EDAC=y\nCONFIG_EDAC_ATOMIC_SCRUB=y\n# CONFIG_EDAC_DEBUG is not set\nCONFIG_EDAC_LEGACY_SYSFS=y\nCONFIG_EDAC_OCTEON_L2C=y\nCONFIG_EDAC_OCTEON_LMC=y\nCONFIG_EDAC_OCTEON_PC=y\nCONFIG_EDAC_OCTEON_PCI=y\nCONFIG_EDAC_SUPPORT=y\nCONFIG_EXT4_FS=y\nCONFIG_F2FS_FS=y\nCONFIG_FAT_FS=y\nCONFIG_FIXED_PHY=y\nCONFIG_FRAME_WARN=2048\nCONFIG_FS_IOMAP=y\nCONFIG_FS_MBCACHE=y\nCONFIG_FWNODE_MDIO=y\nCONFIG_FW_LOADER_PAGED_BUF=y\nCONFIG_GENERIC_ALLOCATOR=y\nCONFIG_GENERIC_CLOCKEVENTS=y\nCONFIG_GENERIC_CMOS_UPDATE=y\nCONFIG_GENERIC_CPU_AUTOPROBE=y\nCONFIG_GENERIC_FIND_FIRST_BIT=y\nCONFIG_GENERIC_GETTIMEOFDAY=y\nCONFIG_GENERIC_IOMAP=y\nCONFIG_GENERIC_IRQ_SHOW=y\nCONFIG_GENERIC_LIB_ASHLDI3=y\nCONFIG_GENERIC_LIB_ASHRDI3=y\nCONFIG_GENERIC_LIB_CMPDI2=y\nCONFIG_GENERIC_LIB_LSHRDI3=y\nCONFIG_GENERIC_LIB_UCMPDI2=y\nCONFIG_GENERIC_PCI_IOMAP=y\nCONFIG_GENERIC_SMP_IDLE_THREAD=y\nCONFIG_GENERIC_TIME_VSYSCALL=y\nCONFIG_GLOB=y\nCONFIG_GPIOLIB=y\nCONFIG_GPIO_CDEV=y\nCONFIG_GPIO_OCTEON=y\nCONFIG_GRO_CELLS=y\nCONFIG_HANDLE_DOMAIN_IRQ=y\nCONFIG_HARDWARE_WATCHPOINTS=y\nCONFIG_HAS_DMA=y\nCONFIG_HAS_IOMEM=y\nCONFIG_HAS_IOPORT_MAP=y\nCONFIG_HW_RANDOM=y\nCONFIG_HW_RANDOM_OCTEON=y\nCONFIG_HZ_PERIODIC=y\nCONFIG_I2C=y\nCONFIG_I2C_BOARDINFO=y\nCONFIG_I2C_OCTEON=y\nCONFIG_IMAGE_CMDLINE_HACK=y\nCONFIG_INITRAMFS_SOURCE=\"\"\nCONFIG_IRQCHIP=y\nCONFIG_IRQ_DOMAIN=y\nCONFIG_IRQ_FORCED_THREADING=y\nCONFIG_IRQ_WORK=y\nCONFIG_JBD2=y\nCONFIG_LIBFDT=y\nCONFIG_LOCK_DEBUGGING_SUPPORT=y\nCONFIG_MDIO_BUS=y\nCONFIG_MDIO_CAVIUM=y\nCONFIG_MDIO_DEVICE=y\nCONFIG_MDIO_DEVRES=y\nCONFIG_MDIO_OCTEON=y\nCONFIG_MEMFD_CREATE=y\nCONFIG_MIGRATION=y\nCONFIG_MIPS=y\nCONFIG_MIPS_ASID_BITS=8\nCONFIG_MIPS_ASID_SHIFT=0\nCONFIG_MIPS_CMDLINE_FROM_BOOTLOADER=y\nCONFIG_MIPS_EBPF_JIT=y\nCONFIG_MIPS_ELF_APPENDED_DTB=y\nCONFIG_MIPS_FP_SUPPORT=y\nCONFIG_MIPS_L1_CACHE_SHIFT=7\nCONFIG_MIPS_L1_CACHE_SHIFT_7=y\nCONFIG_MIPS_LD_CAN_LINK_VDSO=y\n# CONFIG_MIPS_NO_APPENDED_DTB is not set\nCONFIG_MIPS_NR_CPU_NR_MAP=1024\nCONFIG_MIPS_NR_CPU_NR_MAP_1024=y\nCONFIG_MIPS_PGD_C0_CONTEXT=y\nCONFIG_MIPS_SPRAM=y\nCONFIG_MMC=y\nCONFIG_MMC_BLOCK=y\nCONFIG_MMC_CAVIUM_OCTEON=y\nCONFIG_MODULES_USE_ELF_REL=y\nCONFIG_MODULES_USE_ELF_RELA=y\n# CONFIG_MTD_CFI_INTELEXT is not set\nCONFIG_MTD_CMDLINE_PARTS=y\nCONFIG_MTD_PHYSMAP=y\nCONFIG_MTD_SPI_NOR=y\nCONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y\nCONFIG_NEED_DMA_MAP_STATE=y\nCONFIG_NET_DEVLINK=y\nCONFIG_NET_DSA=y\nCONFIG_NET_FLOW_LIMIT=y\nCONFIG_NET_SELFTESTS=y\nCONFIG_NET_SWITCHDEV=y\nCONFIG_NLS=y\nCONFIG_NLS_CODEPAGE_437=y\nCONFIG_NLS_ISO8859_1=y\nCONFIG_NO_GENERIC_PCI_IOPORT_MAP=y\nCONFIG_NR_CPUS=16\nCONFIG_NR_CPUS_DEFAULT_64=y\nCONFIG_NVMEM=y\nCONFIG_OCTEON_ETHERNET=y\nCONFIG_OCTEON_ILM=y\nCONFIG_OCTEON_MGMT_ETHERNET=y\nCONFIG_OCTEON_USB=y\nCONFIG_OCTEON_WDT=y\nCONFIG_OF=y\nCONFIG_OF_ADDRESS=y\nCONFIG_OF_EARLY_FLATTREE=y\nCONFIG_OF_FLATTREE=y\nCONFIG_OF_GPIO=y\nCONFIG_OF_IRQ=y\nCONFIG_OF_KOBJ=y\nCONFIG_OF_MDIO=y\nCONFIG_PADATA=y\n# CONFIG_PARTITION_ADVANCED is not set\nCONFIG_PATA_OCTEON_CF=y\nCONFIG_PATA_TIMINGS=y\nCONFIG_PCI=y\nCONFIG_PCIEAER=y\nCONFIG_PCIEPORTBUS=y\nCONFIG_PCI_DOMAINS=y\nCONFIG_PCI_DRIVERS_LEGACY=y\nCONFIG_PERF_USE_VMALLOC=y\nCONFIG_PGTABLE_LEVELS=3\nCONFIG_PHYLIB=y\nCONFIG_PHYLINK=y\nCONFIG_PHYS_ADDR_T_64BIT=y\nCONFIG_POSIX_MQUEUE=y\nCONFIG_POSIX_MQUEUE_SYSCTL=y\nCONFIG_PTP_1588_CLOCK_OPTIONAL=y\nCONFIG_QUEUED_RWLOCKS=y\nCONFIG_QUEUED_SPINLOCKS=y\nCONFIG_RAS=y\nCONFIG_RELAY=y\nCONFIG_RFS_ACCEL=y\nCONFIG_RPS=y\nCONFIG_SATA_AHCI_PLATFORM=y\nCONFIG_SATA_HOST=y\nCONFIG_SCSI=y\nCONFIG_SCSI_COMMON=y\nCONFIG_SECCOMP=y\nCONFIG_SECCOMP_FILTER=y\nCONFIG_SERIAL_8250_DW=y\nCONFIG_SERIAL_8250_DWLIB=y\nCONFIG_SERIAL_MCTRL_GPIO=y\nCONFIG_SG_POOL=y\nCONFIG_SMP=y\nCONFIG_SOCK_RX_QUEUE_MAPPING=y\nCONFIG_SPARSEMEM=y\nCONFIG_SPARSEMEM_STATIC=y\nCONFIG_SPI=y\nCONFIG_SPI_MASTER=y\nCONFIG_SPI_MEM=y\nCONFIG_SPI_OCTEON=y\nCONFIG_SRCU=y\nCONFIG_SWIOTLB=y\nCONFIG_SWPHY=y\nCONFIG_SYSCTL_EXCEPTION_TRACE=y\nCONFIG_SYS_HAS_CPU_CAVIUM_OCTEON=y\nCONFIG_SYS_HAS_EARLY_PRINTK=y\nCONFIG_SYS_SUPPORTS_64BIT_KERNEL=y\nCONFIG_SYS_SUPPORTS_ARBIT_HZ=y\nCONFIG_SYS_SUPPORTS_BIG_ENDIAN=y\nCONFIG_SYS_SUPPORTS_HOTPLUG_CPU=y\nCONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y\nCONFIG_SYS_SUPPORTS_RELOCATABLE=y\nCONFIG_SYS_SUPPORTS_SMP=y\nCONFIG_TARGET_ISA_REV=2\nCONFIG_TICK_CPU_ACCOUNTING=y\nCONFIG_TREE_RCU=y\nCONFIG_TREE_SRCU=y\nCONFIG_USB=y\nCONFIG_USB_COMMON=y\nCONFIG_USB_EHCI_BIG_ENDIAN_MMIO=y\nCONFIG_USB_EHCI_HCD=y\nCONFIG_USB_EHCI_HCD_PLATFORM=y\n# CONFIG_USB_OCTEON_EHCI is not set\n# CONFIG_USB_OCTEON_OHCI is not set\nCONFIG_USB_OHCI_BIG_ENDIAN_MMIO=y\nCONFIG_USB_OHCI_HCD=y\nCONFIG_USB_OHCI_HCD_PLATFORM=y\nCONFIG_USB_STORAGE=y\nCONFIG_USB_SUPPORT=y\nCONFIG_USB_XHCI_HCD=y\nCONFIG_USB_XHCI_PLATFORM=y\nCONFIG_USE_OF=y\nCONFIG_VFAT_FS=y\nCONFIG_VITESSE_PHY=y\nCONFIG_VM_EVENT_COUNTERS=y\nCONFIG_WATCHDOG_CORE=y\nCONFIG_WEAK_ORDERING=y\nCONFIG_XPS=y\nCONFIG_ZLIB_INFLATE=y\nCONFIG_ZONE_DMA32=y\n"
  },
  {
    "path": "target/linux/octeon/files/arch/mips/boot/dts/cavium-octeon/cn7130_ubnt_edgerouter-4.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"cn7130_ubnt_edgerouter-e300.dtsi\"\n\n/ {\n\tcompatible = \"ubnt,edgerouter-4\", \"cavium,cn7130\";\n\tmodel = \"Ubiquiti EdgeRouter 4\";\n};\n\n&pip {\n\tinterface@0 {\n\t\tethernet@0 {\n\t\t\tlabel = \"lan3\";\n\t\t\tstatus = \"okay\";\n\t\t\tphy-mode = \"sgmii\";\n\t\t\tphy-handle = <&phy4>;\n\t\t\tnvmem-cells = <&macaddr_eeprom_0>;\n\t\t\tnvmem-cell-names = \"mac-address\";\n\t\t};\n\t};\n};\n\n&eeprom {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_eeprom_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/octeon/files/arch/mips/boot/dts/cavium-octeon/cn7130_ubnt_edgerouter-6p.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"cn7130_ubnt_edgerouter-e300.dtsi\"\n\n/ {\n\tcompatible = \"ubnt,edgerouter-6p\", \"cavium,cn7130\";\n\tmodel = \"Ubiquiti EdgeRouter 6P\";\n};\n\n&smi0 {\n\tphy8: ethernet-phy@8 {\n\t\tdevice_type = \"ethernet-phy\";\n\t\tinterrupts = <17 8>;\n\t\tinterrupt-parent = <&gpio>;\n\t\tcompatible = \"vitesse,vsc8514\", \"ethernet-phy-ieee802.3-c22\";\n\t\treg = <8>;\n\t};\n\n\tphy9: ethernet-phy@9 {\n\t\tdevice_type = \"ethernet-phy\";\n\t\tinterrupts = <17 8>;\n\t\tinterrupt-parent = <&gpio>;\n\t\tcompatible = \"vitesse,vsc8514\", \"ethernet-phy-ieee802.3-c22\";\n\t\treg = <9>;\n\t};\n};\n\n&pip {\n\tinterface@0 {\n\t\tethernet@0 {\n\t\t\tlabel = \"lan5\";\n\t\t\tstatus = \"okay\";\n\t\t\tphy-mode = \"sgmii\";\n\t\t\tphy-handle = <&phy4>;\n\t\t\tnvmem-cells = <&macaddr_eeprom_0>;\n\t\t\tnvmem-cell-names = \"mac-address\";\n\t\t};\n\t};\n\n\tinterface@1 {\n\t\tstatus = \"okay\";\n\n\t\tethernet@0 {\n\t\t\tlabel = \"lan3\";\n\t\t\tstatus = \"okay\";\n\t\t\tphy-mode = \"sgmii\";\n\t\t\tphy-handle = <&phy8>;\n\t\t\tnvmem-cells = <&macaddr_eeprom_0>;\n\t\t\tnvmem-cell-names = \"mac-address\";\n\t\t\tmac-address-increment = <(4)>;\n\t\t};\n\n\t\tethernet@1 {\n\t\t\tlabel = \"lan4\";\n\t\t\tstatus = \"okay\";\n\t\t\tphy-mode = \"sgmii\";\n\t\t\tphy-handle = <&phy9>;\n\t\t\tnvmem-cells = <&macaddr_eeprom_0>;\n\t\t\tnvmem-cell-names = \"mac-address\";\n\t\t\tmac-address-increment = <(5)>;\n\t\t};\n\t};\n};\n\n&eeprom {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_eeprom_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/octeon/files/arch/mips/boot/dts/cavium-octeon/cn7130_ubnt_edgerouter-e300.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"cn71xx.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"ubnt,edgerouter-e300\", \"cavium,cn7130\";\n\tmodel = \"Ubiquiti EdgeRouter E300 series\";\n\n\taliases {\n\t\t/* White + Blinking Blue */\n\t\tled-boot = &led_power_white;\n\t\t/* Blue + Blinking White */\n\t\tled-failsafe = &led_power_blue;\n\t\t/* Constant Blue */\n\t\tled-running = &led_power_blue;\n\t\t/* Blue + Blinking White */\n\t\tled-upgrade = &led_power_blue;\n\t};\n\n\tmemory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x0 0x00000000>,\n\t\t      <0x0 0x10000000>,\n\t\t      <0x0 0x20000000>,\n\t\t      <0x0 0x30000000>;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power_blue: power_blue {\n\t\t\tlabel = \"blue:power\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_power_white: power_white {\n\t\t\tlabel = \"white:power\";\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tsfp: sfp {\n\t\tcompatible = \"sff,sfp\";\n\t\ti2c-bus = <&twsi0>;\n\t\t/* Pins 12, 13 and 14 gets pulled low when SFP is plugged in */\n\t\tmod-def0-gpio = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t};\n};\n\n&uart0 {\n\tstatus = \"okay\";\n};\n\n&usb0 {\n\tstatus = \"okay\";\n};\n\n&xhci0 {\n\tstatus = \"okay\";\n\tdr_mode = \"host\";\n};\n\n&twsi0 {\n\tstatus = \"okay\";\n\n\tsfp_eeprom@50 {\n\t\tcompatible = \"at,24c04\";\n\t\treg = <0x50>;\n\t};\n\n\tsfp_eeprom@51 {\n\t\tcompatible = \"at,24c04\";\n\t\treg = <0x51>;\n\t};\n};\n\n&spi {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"Macronix,mx25l6405d\", \"spi-flash\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"boot0\";\n\t\t\tread-only;\n\t\t\treg = <0x000000 0x300000>;\n\t\t};\n\n\t\tpartition@300000 {\n\t\t\tlabel = \"dummy\";\n\t\t\tread-only;\n\t\t\treg = <0x300000 0x100000>;\n\t\t};\n\n\t\teeprom: partition@400000 {\n\t\t\tlabel = \"eeprom\";\n\t\t\tread-only;\n\t\t\treg = <0x400000 0x10000>;\n\t\t};\n\t};\n};\n\n&mmc {\n\tstatus = \"okay\";\n\n\tmmc-slot@0 {\n\t\tcompatible = \"mmc-slot\";\n\t\treg = <0>;\n\t\tnon-removable;\n\t\tmax-frequency = <26000000>;\n\t\tvoltage-ranges = <3300 3300>;\n\t\tbus-width = <8>;\n\t};\n};\n\n&smi0 {\n\tstatus = \"okay\";\n\n\tphy4: ethernet-phy@4 {\n\t\tdevice_type = \"ethernet-phy\";\n\t\tinterrupts = <17 8>;\n\t\tinterrupt-parent = <&gpio>;\n\t\tcompatible = \"vitesse,vsc8504\", \"ethernet-phy-ieee802.3-c22\";\n\t\treg = <4>;\n\t\tsfp = <&sfp>;\n\t};\n\n\tphy5: ethernet-phy@5 {\n\t\tdevice_type = \"ethernet-phy\";\n\t\tinterrupts = <17 8>;\n\t\tinterrupt-parent = <&gpio>;\n\t\tcompatible = \"vitesse,vsc8504\", \"ethernet-phy-ieee802.3-c22\";\n\t\treg = <5>;\n\t};\n\n\tphy6: ethernet-phy@6 {\n\t\tdevice_type = \"ethernet-phy\";\n\t\tinterrupts = <17 8>;\n\t\tinterrupt-parent = <&gpio>;\n\t\tcompatible = \"vitesse,vsc8504\", \"ethernet-phy-ieee802.3-c22\";\n\t\treg = <6>;\n\t};\n\n\tphy7: ethernet-phy@7 {\n\t\tdevice_type = \"ethernet-phy\";\n\t\tinterrupts = <17 8>;\n\t\tinterrupt-parent = <&gpio>;\n\t\tcompatible = \"vitesse,vsc8504\", \"ethernet-phy-ieee802.3-c22\";\n\t\treg = <7>;\n\t};\n};\n\n&pip {\n\tstatus = \"okay\";\n\n\tinterface@0 {\n\t\tstatus = \"okay\";\n\n\t\tethernet@1 {\n\t\t\tlabel = \"lan0\";\n\t\t\tstatus = \"okay\";\n\t\t\tphy-mode = \"sgmii\";\n\t\t\tphy-handle = <&phy5>;\n\t\t\tnvmem-cells = <&macaddr_eeprom_0>;\n\t\t\tnvmem-cell-names = \"mac-address\";\n\t\t\tmac-address-increment = <(1)>;\n\t\t};\n\n\t\tethernet@2 {\n\t\t\tlabel = \"lan1\";\n\t\t\tstatus = \"okay\";\n\t\t\tphy-mode = \"sgmii\";\n\t\t\tphy-handle = <&phy6>;\n\t\t\tnvmem-cells = <&macaddr_eeprom_0>;\n\t\t\tnvmem-cell-names = \"mac-address\";\n\t\t\tmac-address-increment = <(2)>;\n\t\t};\n\n\t\tethernet@3 {\n\t\t\tlabel = \"lan2\";\n\t\t\tstatus = \"okay\";\n\t\t\tphy-mode = \"sgmii\";\n\t\t\tphy-handle = <&phy7>;\n\t\t\tnvmem-cells = <&macaddr_eeprom_0>;\n\t\t\tnvmem-cell-names = \"mac-address\";\n\t\t\tmac-address-increment = <(3)>;\n\t\t};\n\t};\n};\n\n&eeprom {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_eeprom_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/octeon/files/arch/mips/boot/dts/cavium-octeon/cn71xx.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n/dts-v1/;\n\n/ {\n\tcompatible = \"cavium,cn71xx\";\n\t#address-cells = <2>;\n\t#size-cells = <2>;\n\tinterrupt-parent = <&ciu>;\n\n\tsoc {\n\t\t#address-cells = <2>;\n\t\t#size-cells = <2>;\n\t\tcompatible = \"simple-bus\";\n\t\tranges;\n\n\t\tbootbus@1180000000000 {\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <1>;\n\t\t\tcompatible = \"cavium,octeon-3860-bootbus\";\n\t\t\treg = <0x11800 0x00 0x00 0x200>;\n\t\t\tranges = <0x00 0x00 0x10000 0x10000000 0x00>,\n\t\t\t\t <0x01 0x00 0x10000 0x20000000 0x00>,\n\t\t\t\t <0x02 0x00 0x10000 0x30000000 0x00>,\n\t\t\t\t <0x03 0x00 0x10000 0x40000000 0x00>,\n\t\t\t\t <0x04 0x00 0x10000 0x50000000 0x00>,\n\t\t\t\t <0x05 0x00 0x10000 0x60000000 0x00>,\n\t\t\t\t <0x06 0x00 0x10000 0x70000000 0x00>,\n\t\t\t\t <0x07 0x00 0x10000 0x80000000 0x00>;\n\t\t};\n\n\t\tdma0: dma-engine@1180000000100 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"cavium,octeon-5750-bootbus-dma\";\n\t\t\treg = <0x11800 0x100 0x0 0x08>;\n\t\t\tinterrupts = <0 63>;\n\t\t};\n\n\t\tdma1: dma-engine@1180000000108 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"cavium,octeon-5750-bootbus-dma\";\n\t\t\treg = <0x11800 0x108 0x0 0x08>;\n\t\t\tinterrupts = <0 63>;\n\t\t};\n\n\t\tciu: interrupt-controller@1070000000000 {\n\t\t\t#interrupt-cells = <2>;\n\t\t\tcompatible = \"cavium,octeon-3860-ciu\";\n\t\t\treg = <0x10700 0x00000000 0x0 0x7000>;\n\t\t\tinterrupt-controller;\n\t\t};\n\n\t\tcib0: interrupt-controller@107000000e000 {\n\t\t\t#interrupt-cells = <2>;\n\t\t\tcompatible = \"cavium,octeon-7130-cib\";\n\t\t\treg = <0x10700 0xe000 0x0 0x08>, /* RAW */\n\t\t\t      <0x10700 0xe100 0x0 0x08>; /* EN */\n\t\t\tcavium,max-bits = <23>;\n\t\t\tinterrupts = <1 24>;\n\t\t\tinterrupt-parent = <&ciu>;\n\t\t\tinterrupt-controller;\n\t\t};\n\n\t\tcib1: interrupt-controller@107000000e200 {\n\t\t\t#interrupt-cells = <2>;\n\t\t\tcompatible = \"cavium,octeon-7130-cib\";\n\t\t\treg = <0x10700 0xe200 0x0 0x08>, /* RAW */\n\t\t\t      <0x10700 0xe300 0x0 0x08>; /* EN */\n\t\t\tcavium,max-bits = <12>;\n\t\t\tinterrupts = <1 52>;\n\t\t\tinterrupt-parent = <&ciu>;\n\t\t\tinterrupt-controller;\n\t\t};\n\n\t\tcib2: interrupt-controller@107000000e400 {\n\t\t\t#interrupt-cells = <2>;\n\t\t\tcompatible = \"cavium,octeon-7130-cib\";\n\t\t\treg = <0x10700 0xe400 0x0 0x08>, /* RAW */\n\t\t\t      <0x10700 0xe500 0x0 0x08>; /* EN */\n\t\t\tcavium,max-bits = <6>;\n\t\t\tinterrupts = <1 63>;\n\t\t\tinterrupt-parent = <&ciu>;\n\t\t\tinterrupt-controller;\n\t\t};\n\n\t\tcib3: interrupt-controller@107000000e600 {\n\t\t\t#interrupt-cells = <2>;\n\t\t\tcompatible = \"cavium,octeon-7130-cib\";\n\t\t\treg = <0x10700 0xe600 0x0 0x08>, /* RAW */\n\t\t\t      <0x10700 0xe700 0x0 0x08>; /* EN */\n\t\t\tcavium,max-bits = <4>;\n\t\t\tinterrupts = <2 16>;\n\t\t\tinterrupt-parent = <&ciu>;\n\t\t\tinterrupt-controller;\n\t\t};\n\n\t\tcib4: interrupt-controller@107000000e800 {\n\t\t\t#interrupt-cells = <2>;\n\t\t\tcompatible = \"cavium,octeon-7130-cib\";\n\t\t\treg = <0x10700 0xe800 0x0 0x08>, /* RAW */\n\t\t\t      <0x10700 0xea00 0x0 0x08>; /* EN */\n\t\t\tcavium,max-bits = <11>;\n\t\t\tinterrupts = <1 33>;\n\t\t\tinterrupt-parent = <&ciu>;\n\t\t\tinterrupt-controller;\n\t\t};\n\n\t\tcib5: interrupt-controller@107000000e900 {\n\t\t\t#interrupt-cells = <2>;\n\t\t\tcompatible = \"cavium,octeon-7130-cib\";\n\t\t\treg = <0x10700 0xe900 0x00 0x08>, /* RAW */\n\t\t\t      <0x10700 0xeb00 0x00 0x08>; /* EN */\n\t\t\tcavium,max-bits = <11>;\n\t\t\tinterrupts = <1 23>;\n\t\t\tinterrupt-parent = <&ciu>;\n\t\t\tinterrupt-controller;\n\t\t};\n\n\t\tcib6: interrupt-controller@107000000ec00 {\n\t\t\t#interrupt-cells = <2>;\n\t\t\tcompatible = \"cavium,octeon-7130-cib\";\n\t\t\treg = <0x10700 0xec00 0x0 0x08>, /* RAW */\n\t\t\t      <0x10700 0xee00 0x0 0x08>; /* EN */\n\t\t\tcavium,max-bits = <15>;\n\t\t\tinterrupts = <2 17>;\n\t\t\tinterrupt-parent = <&ciu>;\n\t\t\tinterrupt-controller;\n\t\t};\n\n\t\tgpio: gpio-controller@1070000000800 {\n\t\t\t#interrupt-cells = <2>;\n\t\t\t#gpio-cells = <2>;\n\t\t\tcompatible = \"cavium,octeon-3860-gpio\";\n\t\t\treg = <0x10700 0x800 0x0 0x100>;\n\t\t\tinterrupts = <0 16>, <0 17>, <0 18>, <0 19>,\n\t\t\t\t     <0 20>, <0 21>, <0 22>, <0 23>,\n\t\t\t\t     <0 24>, <0 25>, <0 26>, <0 27>,\n\t\t\t\t     <0 28>, <0 29>, <0 30>, <0 31>;\n\t\t\tinterrupt-controller;\n\t\t\tgpio-controller;\n\t\t};\n\n\t\tmmc: mmc@1180000002000 {\n\t\t\tstatus = \"disabled\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tcompatible = \"cavium,octeon-6130-mmc\";\n\t\t\treg = <0x11800 0x2000 0x0 0x100>,\n\t\t\t      <0x11800 0x168 0x0 0x20>;\n\t\t\tinterrupts = <1 19>, <0 63>;\n\t\t};\n\n\t\tsmi0: mdio@1180000001800 {\n\t\t\tstatus = \"disabled\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tcompatible = \"cavium,octeon-3860-mdio\";\n\t\t\treg = <0x11800 0x1800 0x0 0x40>;\n\t\t};\n\n\t\tsmi1: mdio@1180000001900 {\n\t\t\tstatus = \"disabled\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tcompatible = \"cavium,octeon-3860-mdio\";\n\t\t\treg = <0x11800 0x1900 0x0 0x40>;\n\t\t};\n\n\t\tpip: pip@11800a0000000 {\n\t\t\tstatus = \"disabled\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tcompatible = \"cavium,octeon-3860-pip\";\n\t\t\treg = <0x11800 0xa0000000 0x0 0x2000>;\n\n\t\t\tinterface@0 {\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\t\t\t\tcompatible = \"cavium,octeon-3860-pip-interface\";\n\t\t\t\treg = <0>; /* Interface */\n\n\t\t\t\tethernet@0 {\n\t\t\t\t\tstatus = \"disabled\";\n\t\t\t\t\tcompatible = \"cavium,octeon-3860-pip-port\";\n\t\t\t\t\treg = <0>; /* Port */\n\t\t\t\t};\n\n\t\t\t\tethernet@1 {\n\t\t\t\t\tstatus = \"disabled\";\n\t\t\t\t\tcompatible = \"cavium,octeon-3860-pip-port\";\n\t\t\t\t\treg = <1>; /* Port */\n\t\t\t\t};\n\n\t\t\t\tethernet@2 {\n\t\t\t\t\tstatus = \"disabled\";\n\t\t\t\t\tcompatible = \"cavium,octeon-3860-pip-port\";\n\t\t\t\t\treg = <2>; /* Port */\n\t\t\t\t};\n\n\t\t\t\tethernet@3 {\n\t\t\t\t\tstatus = \"disabled\";\n\t\t\t\t\tcompatible = \"cavium,octeon-3860-pip-port\";\n\t\t\t\t\treg = <3>; /* Port */\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tinterface@1 {\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <0>;\n\t\t\t\tcompatible = \"cavium,octeon-3860-pip-interface\";\n\t\t\t\treg = <1>; /* Interface */\n\n\t\t\t\tethernet@0 {\n\t\t\t\t\tstatus = \"disabled\";\n\t\t\t\t\tcompatible = \"cavium,octeon-3860-pip-port\";\n\t\t\t\t\treg = <0>; /* Port */\n\t\t\t\t};\n\n\t\t\t\tethernet@1 {\n\t\t\t\t\tstatus = \"disabled\";\n\t\t\t\t\tcompatible = \"cavium,octeon-3860-pip-port\";\n\t\t\t\t\treg = <1>; /* Port */\n\t\t\t\t};\n\n\t\t\t\tethernet@2 {\n\t\t\t\t\tstatus = \"disabled\";\n\t\t\t\t\tcompatible = \"cavium,octeon-3860-pip-port\";\n\t\t\t\t\treg = <2>; /* Port */\n\t\t\t\t};\n\n\t\t\t\tethernet@3 {\n\t\t\t\t\tstatus = \"disabled\";\n\t\t\t\t\tcompatible = \"cavium,octeon-3860-pip-port\";\n\t\t\t\t\treg = <3>; /* Port */\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\n\t\ttwsi0: i2c@1180000001000 {\n\t\t\tstatus = \"disabled\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tcompatible = \"cavium,octeon-3860-twsi\";\n\t\t\treg = <0x11800 0x1000 0x0 0x200>;\n\t\t\tinterrupts = <0 45>;\n\t\t\tclock-frequency = <100000>;\n\t\t};\n\n\t\ttwsi1: i2c@1180000001200 {\n\t\t\tstatus = \"disabled\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tcompatible = \"cavium,octeon-3860-twsi\";\n\t\t\treg = <0x11800 0x1200 0x0 0x200>;\n\t\t\tinterrupts = <0 59>;\n\t\t\tclock-frequency = <100000>;\n\t\t};\n\n\t\tuctl@118006c000000 {\n\t\t\tstatus = \"disabled\";\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\t\t\tcompatible = \"cavium,octeon-7130-sata-uctl\";\n\t\t\treg = <0x11800 0x6c000000 0x00 0x100>;\n\t\t\tranges;\n\n\t\t\tsata@16c0000000000 {\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\tcompatible = \"cavium,octeon-7130-ahci\";\n\t\t\t\treg = <0x16c00 0x00 0x00 0x200>;\n\t\t\t\tinterrupt-parent = <&cib3>;\n\t\t\t\tinterrupts = <2 4>;\n\t\t\t};\n\t\t};\n\n\t\tusb0: uctl@1180068000000 {\n\t\t\tstatus = \"disabled\";\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\t\t\tcompatible = \"cavium,octeon-7130-usb-uctl\";\n\t\t\treg = <0x11800 0x68000000 0x00 0x100>;\n\t\t\tranges;\n\t\t\tpower = <0x02 0x01 0x00>;\n\t\t\trefclk-frequency = <100000000>;\n\t\t\trefclk-type-hs = \"pll_ref_clk\";\n\t\t\trefclk-type-ss = \"dlmc_ref_clk1\";\n\n\t\t\txhci0: xhci@1680000000000 {\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\tcompatible = \"cavium,octeon-7130-xhci\", \"synopsys,dwc3\";\n\t\t\t\treg = <0x16800 0x0 0x10 0x00>;\n\t\t\t\tinterrupts = <9 4>;\n\t\t\t\tinterrupt-parent = <&cib4>;\n\t\t\t};\n\t\t};\n\n\t\tusb1: uctl@1180069000000 {\n\t\t\tstatus = \"disabled\";\n\t\t\t#address-cells = <2>;\n\t\t\t#size-cells = <2>;\n\t\t\tcompatible = \"cavium,octeon-7130-usb-uctl\";\n\t\t\treg = <0x11800 0x69000000 0x00 0x100>;\n\t\t\tranges;\n\t\t\tpower = <0x02 0x02 0x01>;\n\t\t\trefclk-frequency = <100000000>;\n\t\t\trefclk-type-hs = \"pll_ref_clk\";\n\t\t\trefclk-type-ss = \"dlmc_ref_clk1\";\n\n\t\t\txhci1: xhci@1690000000000 {\n\t\t\t\tstatus = \"disabled\";\n\t\t\t\tcompatible = \"cavium,octeon-7130-xhci\", \"synopsys,dwc3\";\n\t\t\t\treg = <0x16900 0x0 0x10 0x00>;\n\t\t\t\tinterrupts = <9 4>;\n\t\t\t\tinterrupt-parent = <&cib5>;\n\t\t\t};\n\t\t};\n\n\t\tuart0: serial@1180000000800 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"cavium,octeon-3860-uart\", \"ns16550\";\n\t\t\treg = <0x11800 0x800 0x0 0x400>;\n\t\t\treg-shift = <3>;\n\t\t\tinterrupts = <0 34>;\n\t\t\tclock-frequency = <400000000>;\n\t\t\tcurrent-speed = <115200>;\n\t\t};\n\n\t\tuart1: serial@1180000000c00 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"cavium,octeon-3860-uart\", \"ns16550\";\n\t\t\treg = <0x11800 0xc00 0x0 0x400>;\n\t\t\treg-shift = <3>;\n\t\t\tinterrupts = <0 35>;\n\t\t\tclock-frequency = <400000000>;\n\t\t\tcurrent-speed = <115200>;\n\t\t};\n\n\t\tocla0@11800a8000000 {\n\t\t\tstatus = \"disabled\";\n\t\t\tcompatible = \"cavium,octeon-7130-ocla\";\n\t\t\treg = <0x11800 0xa8000000 0x0 0x500000>;\n\t\t\tinterrupts = <0x08 0x01 0x09 0x01 0x0b 0x01>;\n\t\t\tinterrupt-parent = <&cib6>;\n\t\t};\n\n\t\tspi: spi@1070000001000 {\n\t\t\tstatus = \"disabled\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t\tcompatible = \"cavium,octeon-3010-spi\";\n\t\t\treg = <0x10700 0x1000 0x00 0x100>;\n\t\t\tinterrupts = <0 58>;\n\t\t\tspi-max-frequency = <100000000>;\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/octeon/image/Makefile",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2009-2010 OpenWrt.org\n\ninclude $(TOPDIR)/rules.mk\ninclude $(INCLUDE_DIR)/image.mk\n\ndefine Build/append-dtb-to-elf\n\t$(TARGET_CROSS)objcopy --update-section .appended_dtb=$(KDIR)/image-$(DEVICE_DTS).dtb $@\nendef\n\ndefine Build/strip-kernel\n\t# Workaround pre-SDK-1.9.0 u-boot versions not handling the .notes section\n\t$(TARGET_CROSS)strip -R .notes $@ -o $@.stripped && mv $@.stripped $@\nendef\n\nDTS_DIR := $(DTS_DIR)/cavium-octeon\n\ndefine Device/Default\n  PROFILES = Default $$(DEVICE_NAME)\n  KERNEL_NAME := vmlinux.elf\n  KERNEL_INITRAMFS_NAME := vmlinux-initramfs.elf\n  KERNEL := kernel-bin | strip-kernel | patch-cmdline\n  IMAGES := sysupgrade.tar\n  IMAGE/sysupgrade.tar/squashfs := append-rootfs | pad-extra 128k | sysupgrade-tar rootfs=$$$$@\n  IMAGE/sysupgrade.tar := sysupgrade-tar\nendef\n\ndefine Device/generic\n  DEVICE_VENDOR := Generic\n  DEVICE_MODEL := Octeon\n  FILESYSTEMS := ext4\nendef\nTARGET_DEVICES += generic\n\nITUSROUTER_CMDLINE:=console=ttyS0,115200 root=/dev/mmcblk1p2 rootfstype=squashfs,ext4,f2fs rootwait\ndefine Device/itus_shield-router\n  DEVICE_VENDOR := Itus Networks\n  DEVICE_MODEL := Shield Router\n  CMDLINE := $(ITUSROUTER_CMDLINE)\n  IMAGE/sysupgrade.tar/squashfs += | append-metadata\nendef\nTARGET_DEVICES += itus_shield-router\n\nER_CMDLINE:=-mtdparts=phys_mapped_flash:640k(boot0)ro,640k(boot1)ro,64k(eeprom)ro root=/dev/mmcblk0p2 rootfstype=squashfs,ext4 rootwait\ndefine Device/ubnt_edgerouter\n  DEVICE_VENDOR := Ubiquiti\n  DEVICE_MODEL := EdgeRouter\n  BOARD_NAME := er\n  CMDLINE := $(ER_CMDLINE)\nendef\nTARGET_DEVICES += ubnt_edgerouter\n\ndefine Device/ubnt_edgerouter-e300\n  DEVICE_VENDOR := Ubiquiti\n  DEVICE_PACKAGES += kmod-gpio-button-hotplug kmod-leds-gpio kmod-of-mdio kmod-sfp kmod-usb3 kmod-usb-dwc3 kmod-usb-storage-uas\n  KERNEL := kernel-bin | patch-cmdline | append-dtb-to-elf\n  KERNEL_DEPENDS := $$(wildcard $(DTS_DIR)/$(DEVICE_DTS).dts)\n  CMDLINE := root=/dev/mmcblk0p2 rootfstype=squashfs,ext4 rootwait\nendef\n\ndefine Device/ubnt_edgerouter-4\n  $(Device/ubnt_edgerouter-e300)\n  DEVICE_MODEL := EdgeRouter 4\n  DEVICE_DTS := cn7130_ubnt_edgerouter-4\nendef\nTARGET_DEVICES += ubnt_edgerouter-4\n\ndefine Device/ubnt_edgerouter-6p\n  $(Device/ubnt_edgerouter-e300)\n  DEVICE_MODEL := EdgeRouter 6P\n  DEVICE_DTS := cn7130_ubnt_edgerouter-6p\nendef\nTARGET_DEVICES += ubnt_edgerouter-6p\n\nERLITE_CMDLINE:=-mtdparts=phys_mapped_flash:512k(boot0)ro,512k(boot1)ro,64k(eeprom)ro root=/dev/sda2 rootfstype=squashfs,ext4 rootwait\ndefine Device/ubnt_edgerouter-lite\n  DEVICE_VENDOR := Ubiquiti\n  DEVICE_MODEL := EdgeRouter Lite\n  BOARD_NAME := erlite\n  CMDLINE := $(ERLITE_CMDLINE)\nendef\nTARGET_DEVICES += ubnt_edgerouter-lite\n\n$(eval $(call BuildImage))\n"
  },
  {
    "path": "target/linux/octeon/patches-5.10/100-ubnt_edgerouter2_support.patch",
    "content": "--- a/arch/mips/cavium-octeon/executive/cvmx-helper-board.c\n+++ b/arch/mips/cavium-octeon/executive/cvmx-helper-board.c\n@@ -174,6 +174,8 @@ int cvmx_helper_board_get_mii_address(in\n \t\t\treturn 7 - ipd_port;\n \t\telse\n \t\t\treturn -1;\n+\tcase CVMX_BOARD_TYPE_UBNT_E200:\n+\t\treturn -1;\n \tcase CVMX_BOARD_TYPE_KONTRON_S1901:\n \t\tif (ipd_port == CVMX_HELPER_BOARD_MGMT_IPD_PORT)\n \t\t\treturn 1;\n"
  },
  {
    "path": "target/linux/octeon/patches-5.10/110-er200-ethernet_probe_order.patch",
    "content": "--- a/drivers/staging/octeon/ethernet.c\n+++ b/drivers/staging/octeon/ethernet.c\n@@ -679,6 +679,7 @@ static int cvm_oct_probe(struct platform\n \tint interface;\n \tint fau = FAU_NUM_PACKET_BUFFERS_TO_FREE;\n \tint qos;\n+\tint i;\n \tstruct device_node *pip;\n \tint mtu_overhead = ETH_HLEN + ETH_FCS_LEN;\n \n@@ -800,13 +801,19 @@ static int cvm_oct_probe(struct platform\n \t}\n \n \tnum_interfaces = cvmx_helper_get_number_of_interfaces();\n-\tfor (interface = 0; interface < num_interfaces; interface++) {\n-\t\tcvmx_helper_interface_mode_t imode =\n-\t\t    cvmx_helper_interface_get_mode(interface);\n-\t\tint num_ports = cvmx_helper_ports_on_interface(interface);\n+\tfor (i = 0; i < num_interfaces; i++) {\n+\t\tcvmx_helper_interface_mode_t imode;\n+\t\tint interface;\n+\t\tint num_ports;\n \t\tint port;\n \t\tint port_index;\n \n+\t\tinterface = i;\n+\t\tif (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_UBNT_E200)\n+\t\t\tinterface = num_interfaces - (i + 1);\n+\n+\t\tnum_ports = cvmx_helper_ports_on_interface(interface);\n+\t\timode = cvmx_helper_interface_get_mode(interface);\n \t\tfor (port_index = 0,\n \t\t     port = cvmx_helper_get_ipd_port(interface, 0);\n \t\t     port < cvmx_helper_get_ipd_port(interface, num_ports);\n"
  },
  {
    "path": "target/linux/octeon/patches-5.10/120-cmdline-hack.patch",
    "content": "--- a/arch/mips/cavium-octeon/setup.c\n+++ b/arch/mips/cavium-octeon/setup.c\n@@ -654,6 +654,35 @@ void octeon_user_io_init(void)\n \twrite_c0_derraddr1(0);\n }\n \n+#ifdef CONFIG_IMAGE_CMDLINE_HACK\n+extern char __image_cmdline[];\n+\n+static int __init octeon_use_image_cmdline(void)\n+{\n+       char *p = __image_cmdline;\n+       int replace = 0;\n+\n+       if (*p == '-') {\n+               replace = 1;\n+               p++;\n+       }\n+\n+       if (*p == '\\0')\n+               return 0;\n+\n+       if (replace) {\n+               strlcpy(arcs_cmdline, p, sizeof(arcs_cmdline));\n+       } else {\n+               strlcat(arcs_cmdline, \" \", sizeof(arcs_cmdline));\n+               strlcat(arcs_cmdline, p, sizeof(arcs_cmdline));\n+       }\n+\n+       return 1;\n+}\n+#else\n+static inline int octeon_use_image_cmdline(void) { return 0; }\n+#endif\n+\n /**\n  * Early entry point for arch setup\n  */\n@@ -898,6 +927,8 @@ void __init prom_init(void)\n \t\t}\n \t}\n \n+\tocteon_use_image_cmdline();\n+\n \tif (strstr(arcs_cmdline, \"console=\") == NULL) {\n \t\tif (octeon_uart == 1)\n \t\t\tstrcat(arcs_cmdline, \" console=ttyS1,115200\");\n"
  },
  {
    "path": "target/linux/octeon/patches-5.10/130-itus_shield_support.patch",
    "content": "--- a/arch/mips/include/asm/octeon/cvmx-bootinfo.h\n+++ b/arch/mips/include/asm/octeon/cvmx-bootinfo.h\n@@ -297,7 +297,7 @@ enum cvmx_board_types_enum {\n \tCVMX_BOARD_TYPE_UBNT_E100 = 20002,\n \tCVMX_BOARD_TYPE_UBNT_E200 = 20003,\n \tCVMX_BOARD_TYPE_UBNT_E220 = 20005,\n-\tCVMX_BOARD_TYPE_CUST_DSR1000N = 20006,\n+\tCVMX_BOARD_TYPE_ITUS_SHIELD = 20006,\n \tCVMX_BOARD_TYPE_KONTRON_S1901 = 21901,\n \tCVMX_BOARD_TYPE_CUST_PRIVATE_MAX = 30000,\n \n@@ -400,7 +400,7 @@ static inline const char *cvmx_board_typ\n \t\tENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_UBNT_E100)\n \t\tENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_UBNT_E200)\n \t\tENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_UBNT_E220)\n-\t\tENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_DSR1000N)\n+\t\tENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_ITUS_SHIELD)\n \t\tENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_KONTRON_S1901)\n \t\tENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_PRIVATE_MAX)\n \t}\n--- a/arch/mips/cavium-octeon/octeon-platform.c\n+++ b/arch/mips/cavium-octeon/octeon-platform.c\n@@ -773,7 +773,7 @@ int __init octeon_prune_device_tree(void\n \tif (fdt_check_header(initial_boot_params))\n \t\tpanic(\"Corrupt Device Tree.\");\n \n-\tWARN(octeon_bootinfo->board_type == CVMX_BOARD_TYPE_CUST_DSR1000N,\n+\tWARN(octeon_bootinfo->board_type == CVMX_BOARD_TYPE_ITUS_SHIELD,\n \t     \"Built-in DTB booting is deprecated on %s. Please switch to use appended DTB.\",\n \t     cvmx_board_type_to_string(octeon_bootinfo->board_type));\n \n--- a/arch/mips/pci/pci-octeon.c\n+++ b/arch/mips/pci/pci-octeon.c\n@@ -211,8 +211,6 @@ const char *octeon_get_pci_interrupts(vo\n \t\treturn \"AAABAAAAAAAAAAAAAAAAAAAAAAAAAAAA\";\n \tcase CVMX_BOARD_TYPE_BBGW_REF:\n \t\treturn \"AABCD\";\n-\tcase CVMX_BOARD_TYPE_CUST_DSR1000N:\n-\t\treturn \"CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC\";\n \tcase CVMX_BOARD_TYPE_THUNDER:\n \tcase CVMX_BOARD_TYPE_EBH3000:\n \tdefault:\n"
  },
  {
    "path": "target/linux/octeon/patches-5.10/140-octeon_e300_support.patch",
    "content": "--- a/arch/mips/include/asm/octeon/cvmx-bootinfo.h\n+++ b/arch/mips/include/asm/octeon/cvmx-bootinfo.h\n@@ -298,6 +298,7 @@ enum cvmx_board_types_enum {\n \tCVMX_BOARD_TYPE_UBNT_E200 = 20003,\n \tCVMX_BOARD_TYPE_UBNT_E220 = 20005,\n \tCVMX_BOARD_TYPE_ITUS_SHIELD = 20006,\n+\tCVMX_BOARD_TYPE_UBNT_E300 = 20300,\n \tCVMX_BOARD_TYPE_KONTRON_S1901 = 21901,\n \tCVMX_BOARD_TYPE_CUST_PRIVATE_MAX = 30000,\n \n@@ -401,6 +402,7 @@ static inline const char *cvmx_board_typ\n \t\tENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_UBNT_E200)\n \t\tENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_UBNT_E220)\n \t\tENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_ITUS_SHIELD)\n+\t\tENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_UBNT_E300)\n \t\tENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_KONTRON_S1901)\n \t\tENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_PRIVATE_MAX)\n \t}\n"
  },
  {
    "path": "target/linux/octeon/patches-5.10/700-allocate_interface_by_label.patch",
    "content": "From: Roman Kuzmitskii <damex.pp@icloud.com>\nDate: Wed, 28 Oct 2020 19:00:00 +0000\nSubject: [PATCH] staging: octeon: add net-labels support\n\nWith this patch, device name can be set within dts file\nin the same way as dsa port can.\n\nAdd label to pip interface node to use this feature:\nlabel = \"lan0\";\n\nTested-by: Johannes Kimmel <fff@bareminimum.eu>\nSigned-off-by: Roman Kuzmitskii <damex.pp@icloud.com>\n--- a/drivers/staging/octeon/ethernet.c\n+++ b/drivers/staging/octeon/ethernet.c\n@@ -407,8 +407,12 @@ static int cvm_oct_common_set_mac_addres\n int cvm_oct_common_init(struct net_device *dev)\n {\n \tstruct octeon_ethernet *priv = netdev_priv(dev);\n+\tconst u8 *label = NULL;\n \tint ret;\n \n+\tif (priv->of_node)\n+\t\tlabel = of_get_property(priv->of_node, \"label\", NULL);\n+\n \tret = of_get_mac_address(priv->of_node, dev->dev_addr);\n \tif (ret)\n \t\teth_hw_addr_random(dev);\n@@ -441,6 +445,9 @@ int cvm_oct_common_init(struct net_devic\n \tif (dev->netdev_ops->ndo_stop)\n \t\tdev->netdev_ops->ndo_stop(dev);\n \n+\tif (!IS_ERR_OR_NULL(label))\n+\t\tdev_alloc_name(dev, label);\n+\n \treturn 0;\n }\n \n"
  },
  {
    "path": "target/linux/octeon/patches-5.10/701-honor_sgmii_node_device_tree_status.patch",
    "content": "From: Roman Kuzmitskii <damex.pp@icloud.com>\nDate: Sun, 01 Nov 2020 19:00:00 +0000\nSubject: [PATCH] staging: octeon: sgmii to honor disabled dt node status\n\nWith this patch, sgmii interface device tree node could be disabled and\nthat disabled interface will not be unnecessarily initialized.\n\nIt solves the problem with Octeon boards that have 8 sgmii or more ports\ninitialized but have nothing connected to them.\n\nTested-by: Johannes Kimmel <fff@bareminimum.eu>\nSigned-off-by: Roman Kuzmitskii <damex.pp@icloud.com>\n--- a/drivers/staging/octeon/ethernet.c\n+++ b/drivers/staging/octeon/ethernet.c\n@@ -880,8 +880,10 @@ static int cvm_oct_probe(struct platform\n \n \t\t\tcase CVMX_HELPER_INTERFACE_MODE_SGMII:\n \t\t\t\tpriv->phy_mode = PHY_INTERFACE_MODE_SGMII;\n-\t\t\t\tdev->netdev_ops = &cvm_oct_sgmii_netdev_ops;\n-\t\t\t\tstrscpy(dev->name, \"eth%d\", sizeof(dev->name));\n+\t\t\t\tif (of_device_is_available(priv->of_node)) {\n+\t\t\t\t\tdev->netdev_ops = &cvm_oct_sgmii_netdev_ops;\n+\t\t\t\t\tstrscpy(dev->name, \"eth%d\", sizeof(dev->name));\n+\t\t\t\t}\n \t\t\t\tbreak;\n \n \t\t\tcase CVMX_HELPER_INTERFACE_MODE_SPI:\n"
  },
  {
    "path": "target/linux/octeon/patches-5.15/100-ubnt_edgerouter2_support.patch",
    "content": "--- a/arch/mips/cavium-octeon/executive/cvmx-helper-board.c\n+++ b/arch/mips/cavium-octeon/executive/cvmx-helper-board.c\n@@ -174,6 +174,8 @@ int cvmx_helper_board_get_mii_address(in\n \t\t\treturn 7 - ipd_port;\n \t\telse\n \t\t\treturn -1;\n+\tcase CVMX_BOARD_TYPE_UBNT_E200:\n+\t\treturn -1;\n \tcase CVMX_BOARD_TYPE_KONTRON_S1901:\n \t\tif (ipd_port == CVMX_HELPER_BOARD_MGMT_IPD_PORT)\n \t\t\treturn 1;\n"
  },
  {
    "path": "target/linux/octeon/patches-5.15/110-er200-ethernet_probe_order.patch",
    "content": "--- a/drivers/staging/octeon/ethernet.c\n+++ b/drivers/staging/octeon/ethernet.c\n@@ -676,6 +676,7 @@ static int cvm_oct_probe(struct platform\n \tint interface;\n \tint fau = FAU_NUM_PACKET_BUFFERS_TO_FREE;\n \tint qos;\n+\tint i;\n \tstruct device_node *pip;\n \tint mtu_overhead = ETH_HLEN + ETH_FCS_LEN;\n \n@@ -797,13 +798,19 @@ static int cvm_oct_probe(struct platform\n \t}\n \n \tnum_interfaces = cvmx_helper_get_number_of_interfaces();\n-\tfor (interface = 0; interface < num_interfaces; interface++) {\n-\t\tcvmx_helper_interface_mode_t imode =\n-\t\t    cvmx_helper_interface_get_mode(interface);\n-\t\tint num_ports = cvmx_helper_ports_on_interface(interface);\n+\tfor (i = 0; i < num_interfaces; i++) {\n+\t\tcvmx_helper_interface_mode_t imode;\n+\t\tint interface;\n+\t\tint num_ports;\n \t\tint port;\n \t\tint port_index;\n \n+\t\tinterface = i;\n+\t\tif (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_UBNT_E200)\n+\t\t\tinterface = num_interfaces - (i + 1);\n+\n+\t\tnum_ports = cvmx_helper_ports_on_interface(interface);\n+\t\timode = cvmx_helper_interface_get_mode(interface);\n \t\tfor (port_index = 0,\n \t\t     port = cvmx_helper_get_ipd_port(interface, 0);\n \t\t     port < cvmx_helper_get_ipd_port(interface, num_ports);\n"
  },
  {
    "path": "target/linux/octeon/patches-5.15/120-cmdline-hack.patch",
    "content": "--- a/arch/mips/cavium-octeon/setup.c\n+++ b/arch/mips/cavium-octeon/setup.c\n@@ -650,6 +650,35 @@ void octeon_user_io_init(void)\n \twrite_c0_derraddr1(0);\n }\n \n+#ifdef CONFIG_IMAGE_CMDLINE_HACK\n+extern char __image_cmdline[];\n+\n+static int __init octeon_use_image_cmdline(void)\n+{\n+       char *p = __image_cmdline;\n+       int replace = 0;\n+\n+       if (*p == '-') {\n+               replace = 1;\n+               p++;\n+       }\n+\n+       if (*p == '\\0')\n+               return 0;\n+\n+       if (replace) {\n+               strlcpy(arcs_cmdline, p, sizeof(arcs_cmdline));\n+       } else {\n+               strlcat(arcs_cmdline, \" \", sizeof(arcs_cmdline));\n+               strlcat(arcs_cmdline, p, sizeof(arcs_cmdline));\n+       }\n+\n+       return 1;\n+}\n+#else\n+static inline int octeon_use_image_cmdline(void) { return 0; }\n+#endif\n+\n /**\n  * prom_init - Early entry point for arch setup\n  */\n@@ -873,6 +902,8 @@ void __init prom_init(void)\n \t\t}\n \t}\n \n+\tocteon_use_image_cmdline();\n+\n \tif (strstr(arcs_cmdline, \"console=\") == NULL) {\n \t\tif (octeon_uart == 1)\n \t\t\tstrcat(arcs_cmdline, \" console=ttyS1,115200\");\n"
  },
  {
    "path": "target/linux/octeon/patches-5.15/130-add_itus_support.patch",
    "content": "--- a/arch/mips/cavium-octeon/octeon-platform.c\n+++ b/arch/mips/cavium-octeon/octeon-platform.c\n@@ -773,7 +773,7 @@ int __init octeon_prune_device_tree(void\n \tif (fdt_check_header(initial_boot_params))\n \t\tpanic(\"Corrupt Device Tree.\");\n \n-\tWARN(octeon_bootinfo->board_type == CVMX_BOARD_TYPE_CUST_DSR1000N,\n+\tWARN(octeon_bootinfo->board_type == CVMX_BOARD_TYPE_ITUS_SHIELD,\n \t     \"Built-in DTB booting is deprecated on %s. Please switch to use appended DTB.\",\n \t     cvmx_board_type_to_string(octeon_bootinfo->board_type));\n \n--- a/arch/mips/include/asm/octeon/cvmx-bootinfo.h\n+++ b/arch/mips/include/asm/octeon/cvmx-bootinfo.h\n@@ -297,7 +297,7 @@ enum cvmx_board_types_enum {\n \tCVMX_BOARD_TYPE_UBNT_E100 = 20002,\n \tCVMX_BOARD_TYPE_UBNT_E200 = 20003,\n \tCVMX_BOARD_TYPE_UBNT_E220 = 20005,\n-\tCVMX_BOARD_TYPE_CUST_DSR1000N = 20006,\n+\tCVMX_BOARD_TYPE_ITUS_SHIELD = 20006,\n \tCVMX_BOARD_TYPE_UBNT_E300 = 20300,\n \tCVMX_BOARD_TYPE_KONTRON_S1901 = 21901,\n \tCVMX_BOARD_TYPE_CUST_PRIVATE_MAX = 30000,\n@@ -401,7 +401,7 @@ static inline const char *cvmx_board_typ\n \t\tENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_UBNT_E100)\n \t\tENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_UBNT_E200)\n \t\tENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_UBNT_E220)\n-\t\tENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_DSR1000N)\n+\t\tENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_ITUS_SHIELD)\n \t\tENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_UBNT_E300)\n \t\tENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_KONTRON_S1901)\n \t\tENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_PRIVATE_MAX)\n--- a/arch/mips/pci/pci-octeon.c\n+++ b/arch/mips/pci/pci-octeon.c\n@@ -211,7 +211,7 @@ const char *octeon_get_pci_interrupts(vo\n \t\treturn \"AAABAAAAAAAAAAAAAAAAAAAAAAAAAAAA\";\n \tcase CVMX_BOARD_TYPE_BBGW_REF:\n \t\treturn \"AABCD\";\n-\tcase CVMX_BOARD_TYPE_CUST_DSR1000N:\n+\tcase CVMX_BOARD_TYPE_ITUS_SHIELD:\n \t\treturn \"CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC\";\n \tcase CVMX_BOARD_TYPE_THUNDER:\n \tcase CVMX_BOARD_TYPE_EBH3000:\n"
  },
  {
    "path": "target/linux/octeon/patches-5.15/700-allocate_interface_by_label.patch",
    "content": "From: Roman Kuzmitskii <damex.pp@icloud.com>\nDate: Wed, 28 Oct 2020 19:00:00 +0000\nSubject: [PATCH] staging: octeon: add net-labels support\n\nWith this patch, device name can be set within dts file\nin the same way as dsa port can.\n\nAdd label to pip interface node to use this feature:\nlabel = \"lan0\";\n\nTested-by: Johannes Kimmel <fff@bareminimum.eu>\nSigned-off-by: Roman Kuzmitskii <damex.pp@icloud.com>\n--- a/drivers/staging/octeon/ethernet.c\n+++ b/drivers/staging/octeon/ethernet.c\n@@ -407,8 +407,12 @@ static int cvm_oct_common_set_mac_addres\n int cvm_oct_common_init(struct net_device *dev)\n {\n \tstruct octeon_ethernet *priv = netdev_priv(dev);\n+\tconst u8 *label = NULL;\n \tint ret;\n \n+\tif (priv->of_node)\n+\t\tlabel = of_get_property(priv->of_node, \"label\", NULL);\n+\n \tret = of_get_mac_address(priv->of_node, dev->dev_addr);\n \tif (ret)\n \t\teth_hw_addr_random(dev);\n@@ -441,6 +445,9 @@ int cvm_oct_common_init(struct net_devic\n \tif (dev->netdev_ops->ndo_stop)\n \t\tdev->netdev_ops->ndo_stop(dev);\n \n+\tif (!IS_ERR_OR_NULL(label))\n+\t\tdev_alloc_name(dev, label);\n+\n \treturn 0;\n }\n \n"
  },
  {
    "path": "target/linux/octeon/patches-5.15/701-honor_sgmii_node_device_tree_status.patch",
    "content": "From: Roman Kuzmitskii <damex.pp@icloud.com>\nDate: Sun, 01 Nov 2020 19:00:00 +0000\nSubject: [PATCH] staging: octeon: sgmii to honor disabled dt node status\n\nWith this patch, sgmii interface device tree node could be disabled and\nthat disabled interface will not be unnecessarily initialized.\n\nIt solves the problem with Octeon boards that have 8 sgmii or more ports\ninitialized but have nothing connected to them.\n\nTested-by: Johannes Kimmel <fff@bareminimum.eu>\nSigned-off-by: Roman Kuzmitskii <damex.pp@icloud.com>\n--- a/drivers/staging/octeon/ethernet.c\n+++ b/drivers/staging/octeon/ethernet.c\n@@ -877,8 +877,10 @@ static int cvm_oct_probe(struct platform\n \n \t\t\tcase CVMX_HELPER_INTERFACE_MODE_SGMII:\n \t\t\t\tpriv->phy_mode = PHY_INTERFACE_MODE_SGMII;\n-\t\t\t\tdev->netdev_ops = &cvm_oct_sgmii_netdev_ops;\n-\t\t\t\tstrscpy(dev->name, \"eth%d\", sizeof(dev->name));\n+\t\t\t\tif (of_device_is_available(priv->of_node)) {\n+\t\t\t\t\tdev->netdev_ops = &cvm_oct_sgmii_netdev_ops;\n+\t\t\t\t\tstrscpy(dev->name, \"eth%d\", sizeof(dev->name));\n+\t\t\t\t}\n \t\t\t\tbreak;\n \n \t\t\tcase CVMX_HELPER_INTERFACE_MODE_SPI:\n"
  },
  {
    "path": "target/linux/octeon/profiles/000-Generic.mk",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2013 OpenWrt.org\n\ndefine Profile/Default\n  NAME:=Default Profile\n  PRIORITY:=1\nendef\n\ndefine Profile/Default/Description\n   Base packages for Octeon boards.\nendef\n\n$(eval $(call Profile,Default))\n"
  },
  {
    "path": "target/linux/octeontx/Makefile",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2018 OpenWrt.org\n\ninclude $(TOPDIR)/rules.mk\n\nARCH:=aarch64\nBOARD:=octeontx\nBOARDNAME:=Octeon-TX\nFEATURES:=targz pcie gpio rtc usb fpu\n\nKERNEL_PATCHVER:=5.10\n\ndefine Target/Description\n\tBuild images for Octeon-TX CN80XX/CN81XX based boards\nendef\n\ninclude $(INCLUDE_DIR)/target.mk\n\nKERNELNAME:=Image\n\n$(eval $(call BuildTarget))\n"
  },
  {
    "path": "target/linux/octeontx/base-files/etc/board.d/02_network",
    "content": "#\n# Copyright (C) 2018 OpenWrt.org\n#\n\n. ./lib/functions/uci-defaults.sh\n\nboard=$(board_name)\n\nboard_config_update\n\ncase \"$board\" in\nesac\n\nboard_config_flush\n\nexit 0\n"
  },
  {
    "path": "target/linux/octeontx/base-files/etc/inittab",
    "content": "::sysinit:/etc/init.d/rcS S boot\n::shutdown:/etc/init.d/rcS K shutdown\ntts/0::askfirst:/usr/libexec/login.sh\nttyAMA0::askfirst:/usr/libexec/login.sh\ntty1::askfirst:/usr/libexec/login.sh\n"
  },
  {
    "path": "target/linux/octeontx/config-5.10",
    "content": "CONFIG_64BIT=y\nCONFIG_ARCH_DMA_ADDR_T_64BIT=y\nCONFIG_ARCH_HIBERNATION_HEADER=y\nCONFIG_ARCH_HIBERNATION_POSSIBLE=y\nCONFIG_ARCH_KEEP_MEMBLOCK=y\nCONFIG_ARCH_MMAP_RND_BITS=18\nCONFIG_ARCH_MMAP_RND_BITS_MAX=33\nCONFIG_ARCH_MMAP_RND_BITS_MIN=18\nCONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11\nCONFIG_ARCH_PROC_KCORE_TEXT=y\nCONFIG_ARCH_SELECT_MEMORY_MODEL=y\nCONFIG_ARCH_SPARSEMEM_DEFAULT=y\nCONFIG_ARCH_SPARSEMEM_ENABLE=y\nCONFIG_ARCH_STACKWALK=y\nCONFIG_ARCH_SUSPEND_POSSIBLE=y\nCONFIG_ARCH_THUNDER=y\nCONFIG_ARM64=y\nCONFIG_ARM64_4K_PAGES=y\nCONFIG_ARM64_CNP=y\nCONFIG_ARM64_CRYPTO=y\nCONFIG_ARM64_ERRATUM_819472=y\nCONFIG_ARM64_ERRATUM_824069=y\nCONFIG_ARM64_ERRATUM_826319=y\nCONFIG_ARM64_ERRATUM_827319=y\nCONFIG_ARM64_ERRATUM_843419=y\nCONFIG_ARM64_HW_AFDBM=y\nCONFIG_ARM64_MODULE_PLTS=y\nCONFIG_ARM64_PAGE_SHIFT=12\nCONFIG_ARM64_PAN=y\nCONFIG_ARM64_PA_BITS=48\nCONFIG_ARM64_PA_BITS_48=y\nCONFIG_ARM64_PTR_AUTH=y\nCONFIG_ARM64_SVE=y\nCONFIG_ARM64_TAGGED_ADDR_ABI=y\nCONFIG_ARM64_UAO=y\nCONFIG_ARM64_VA_BITS=48\n# CONFIG_ARM64_VA_BITS_39 is not set\nCONFIG_ARM64_VA_BITS_48=y\nCONFIG_ARM64_VHE=y\nCONFIG_ARM64_WORKAROUND_CLEAN_CACHE=y\nCONFIG_ARM_AMBA=y\nCONFIG_ARM_ARCH_TIMER=y\nCONFIG_ARM_ARCH_TIMER_EVTSTREAM=y\nCONFIG_ARM_CPUIDLE=y\nCONFIG_ARM_GIC=y\nCONFIG_ARM_GIC_V2M=y\nCONFIG_ARM_GIC_V3=y\nCONFIG_ARM_GIC_V3_ITS=y\nCONFIG_ARM_GIC_V3_ITS_PCI=y\nCONFIG_ARM_PSCI_FW=y\nCONFIG_ARM_SBSA_WATCHDOG=y\nCONFIG_ATA=y\n# CONFIG_ATA_SFF is not set\nCONFIG_AUDIT_ARCH_COMPAT_GENERIC=y\nCONFIG_BALLOON_COMPACTION=y\nCONFIG_BLK_DEV_BSG=y\nCONFIG_BLK_DEV_BSGLIB=y\nCONFIG_BLK_DEV_LOOP=y\nCONFIG_BLK_MQ_PCI=y\nCONFIG_BLK_MQ_VIRTIO=y\nCONFIG_BLK_PM=y\nCONFIG_BLK_SCSI_REQUEST=y\nCONFIG_CAVIUM_ERRATUM_22375=y\nCONFIG_CAVIUM_ERRATUM_23144=y\nCONFIG_CAVIUM_ERRATUM_23154=y\nCONFIG_CAVIUM_ERRATUM_27456=y\nCONFIG_CAVIUM_ERRATUM_30115=y\nCONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y\nCONFIG_CLKDEV_LOOKUP=y\nCONFIG_CLONE_BACKWARDS=y\nCONFIG_CMA=y\nCONFIG_CMA_ALIGNMENT=8\nCONFIG_CMA_AREAS=7\n# CONFIG_CMA_DEBUG is not set\n# CONFIG_CMA_DEBUGFS is not set\nCONFIG_CMA_SIZE_MBYTES=16\n# CONFIG_CMA_SIZE_SEL_MAX is not set\nCONFIG_CMA_SIZE_SEL_MBYTES=y\n# CONFIG_CMA_SIZE_SEL_MIN is not set\n# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set\nCONFIG_COMMON_CLK=y\nCONFIG_COMMON_CLK_CS2000_CP=y\n# CONFIG_COMPAT_32BIT_TIME is not set\nCONFIG_CONFIGFS_FS=y\nCONFIG_CONTIG_ALLOC=y\nCONFIG_CPU_IDLE=y\nCONFIG_CPU_IDLE_GOV_MENU=y\nCONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y\nCONFIG_CPU_PM=y\nCONFIG_CPU_RMAP=y\nCONFIG_CRASH_CORE=y\nCONFIG_CRASH_DUMP=y\nCONFIG_CRC16=y\nCONFIG_CRC7=y\nCONFIG_CRC_ITU_T=y\nCONFIG_CRC_T10DIF=y\nCONFIG_CRYPTO_AES_ARM64=y\nCONFIG_CRYPTO_AES_ARM64_CE=y\nCONFIG_CRYPTO_AES_ARM64_CE_BLK=y\nCONFIG_CRYPTO_AES_ARM64_CE_CCM=y\nCONFIG_CRYPTO_ANSI_CPRNG=y\nCONFIG_CRYPTO_CRC32=y\nCONFIG_CRYPTO_CRC32C=y\nCONFIG_CRYPTO_CRCT10DIF=y\nCONFIG_CRYPTO_CRYPTD=y\nCONFIG_CRYPTO_DRBG=y\nCONFIG_CRYPTO_DRBG_HMAC=y\nCONFIG_CRYPTO_DRBG_MENU=y\nCONFIG_CRYPTO_ECHAINIV=y\nCONFIG_CRYPTO_GHASH_ARM64_CE=y\nCONFIG_CRYPTO_HMAC=y\nCONFIG_CRYPTO_JITTERENTROPY=y\nCONFIG_CRYPTO_LIB_SHA256=y\nCONFIG_CRYPTO_RNG=y\nCONFIG_CRYPTO_RNG2=y\nCONFIG_CRYPTO_RNG_DEFAULT=y\nCONFIG_CRYPTO_SHA1=y\nCONFIG_CRYPTO_SHA1_ARM64_CE=y\nCONFIG_CRYPTO_SHA256=y\nCONFIG_CRYPTO_SHA256_ARM64=y\nCONFIG_CRYPTO_SHA2_ARM64_CE=y\nCONFIG_CRYPTO_SIMD=y\nCONFIG_DCACHE_WORD_ACCESS=y\nCONFIG_DMADEVICES=y\nCONFIG_DMA_CMA=y\nCONFIG_DMA_DIRECT_REMAP=y\nCONFIG_DMA_ENGINE=y\nCONFIG_DMA_OF=y\nCONFIG_DMA_PERNUMA_CMA=y\nCONFIG_DMA_REMAP=y\nCONFIG_DMA_SHARED_BUFFER=y\nCONFIG_DTC=y\nCONFIG_DT_IDLE_STATES=y\nCONFIG_EDAC=y\n# CONFIG_EDAC_DEBUG is not set\n# CONFIG_EDAC_DMC520 is not set\nCONFIG_EDAC_LEGACY_SYSFS=y\nCONFIG_EDAC_SUPPORT=y\nCONFIG_EDAC_THUNDERX=y\n# CONFIG_EDAC_XGENE is not set\nCONFIG_EEPROM_AT24=y\nCONFIG_FAT_FS=y\nCONFIG_FIXED_PHY=y\nCONFIG_FIX_EARLYCON_MEM=y\nCONFIG_FRAME_POINTER=y\nCONFIG_FREEZER=y\nCONFIG_FW_CACHE=y\nCONFIG_FW_LOADER_PAGED_BUF=y\nCONFIG_GENERIC_ALLOCATOR=y\nCONFIG_GENERIC_ARCH_TOPOLOGY=y\nCONFIG_GENERIC_BUG=y\nCONFIG_GENERIC_BUG_RELATIVE_POINTERS=y\nCONFIG_GENERIC_CLOCKEVENTS=y\nCONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y\nCONFIG_GENERIC_CPU_AUTOPROBE=y\nCONFIG_GENERIC_CPU_VULNERABILITIES=y\nCONFIG_GENERIC_CSUM=y\nCONFIG_GENERIC_EARLY_IOREMAP=y\nCONFIG_GENERIC_GETTIMEOFDAY=y\nCONFIG_GENERIC_IDLE_POLL_SETUP=y\nCONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y\nCONFIG_GENERIC_IRQ_MIGRATION=y\nCONFIG_GENERIC_IRQ_MULTI_HANDLER=y\nCONFIG_GENERIC_IRQ_SHOW=y\nCONFIG_GENERIC_IRQ_SHOW_LEVEL=y\nCONFIG_GENERIC_MSI_IRQ=y\nCONFIG_GENERIC_MSI_IRQ_DOMAIN=y\nCONFIG_GENERIC_PCI_IOMAP=y\nCONFIG_GENERIC_PHY=y\nCONFIG_GENERIC_SCHED_CLOCK=y\nCONFIG_GENERIC_SMP_IDLE_THREAD=y\nCONFIG_GENERIC_STRNCPY_FROM_USER=y\nCONFIG_GENERIC_STRNLEN_USER=y\nCONFIG_GENERIC_TIME_VSYSCALL=y\nCONFIG_GLOB=y\nCONFIG_GPIOLIB=y\nCONFIG_GPIOLIB_IRQCHIP=y\nCONFIG_GPIO_PCA953X=y\nCONFIG_GPIO_PCA953X_IRQ=y\nCONFIG_GPIO_THUNDERX=y\nCONFIG_HANDLE_DOMAIN_IRQ=y\nCONFIG_HARDIRQS_SW_RESEND=y\nCONFIG_HAS_DMA=y\nCONFIG_HAS_IOMEM=y\nCONFIG_HAS_IOPORT_MAP=y\nCONFIG_HIBERNATE_CALLBACKS=y\nCONFIG_HIBERNATION=y\nCONFIG_HIBERNATION_SNAPSHOT_DEV=y\nCONFIG_HOLES_IN_ZONE=y\nCONFIG_HOTPLUG_CPU=y\nCONFIG_HUGETLBFS=y\nCONFIG_HUGETLB_PAGE=y\nCONFIG_HWSPINLOCK=y\nCONFIG_HW_RANDOM=y\nCONFIG_HW_RANDOM_CAVIUM=y\nCONFIG_HW_RANDOM_OPTEE=y\nCONFIG_I2C=y\nCONFIG_I2C_ALGOBIT=y\nCONFIG_I2C_BOARDINFO=y\nCONFIG_I2C_CHARDEV=y\nCONFIG_I2C_MUX=y\nCONFIG_I2C_SMBUS=y\nCONFIG_I2C_THUNDERX=y\nCONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000\nCONFIG_INITRAMFS_SOURCE=\"\"\nCONFIG_IRQCHIP=y\nCONFIG_IRQ_DOMAIN=y\nCONFIG_IRQ_DOMAIN_HIERARCHY=y\nCONFIG_IRQ_FASTEOI_HIERARCHY_HANDLERS=y\nCONFIG_IRQ_FORCED_THREADING=y\nCONFIG_IRQ_TIME_ACCOUNTING=y\nCONFIG_IRQ_WORK=y\n# CONFIG_ISDN is not set\nCONFIG_JUMP_LABEL=y\nCONFIG_KEXEC=y\nCONFIG_KEXEC_CORE=y\nCONFIG_KSM=y\nCONFIG_LIBFDT=y\nCONFIG_LOCK_DEBUGGING_SUPPORT=y\nCONFIG_LOCK_SPIN_ON_OWNER=y\nCONFIG_LZO_COMPRESS=y\nCONFIG_LZO_DECOMPRESS=y\nCONFIG_MAGIC_SYSRQ=y\nCONFIG_MAILBOX=y\n# CONFIG_MAILBOX_TEST is not set\nCONFIG_MDIO_BUS=y\nCONFIG_MDIO_CAVIUM=y\nCONFIG_MDIO_DEVICE=y\nCONFIG_MDIO_DEVRES=y\nCONFIG_MDIO_THUNDER=y\nCONFIG_MEMFD_CREATE=y\nCONFIG_MEMORY_BALLOON=y\nCONFIG_MEMORY_ISOLATION=y\nCONFIG_MEMTEST=y\nCONFIG_MFD_SYSCON=y\nCONFIG_MIGRATION=y\nCONFIG_MMC=y\nCONFIG_MMC_BLOCK=y\nCONFIG_MMC_CAVIUM_THUNDERX=y\nCONFIG_MODULES_USE_ELF_RELA=y\nCONFIG_MSDOS_FS=y\n# CONFIG_MTD is not set\nCONFIG_MUTEX_SPIN_ON_OWNER=y\nCONFIG_NEED_DMA_MAP_STATE=y\nCONFIG_NEED_MULTIPLE_NODES=y\nCONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK=y\nCONFIG_NEED_SG_DMA_LENGTH=y\nCONFIG_NET_FLOW_LIMIT=y\nCONFIG_NLS=y\nCONFIG_NLS_CODEPAGE_437=y\nCONFIG_NLS_ISO8859_1=y\nCONFIG_NODES_SHIFT=2\nCONFIG_NO_HZ_COMMON=y\nCONFIG_NO_HZ_IDLE=y\nCONFIG_NR_CPUS=64\nCONFIG_NUMA=y\nCONFIG_NUMA_BALANCING=y\nCONFIG_NUMA_BALANCING_DEFAULT_ENABLED=y\nCONFIG_NVMEM=y\nCONFIG_NVMEM_SYSFS=y\nCONFIG_OF=y\nCONFIG_OF_ADDRESS=y\nCONFIG_OF_EARLY_FLATTREE=y\nCONFIG_OF_FLATTREE=y\nCONFIG_OF_GPIO=y\nCONFIG_OF_IRQ=y\nCONFIG_OF_KOBJ=y\nCONFIG_OF_MDIO=y\nCONFIG_OF_NET=y\nCONFIG_OF_NUMA=y\nCONFIG_OPTEE=y\nCONFIG_OPTEE_SHM_NUM_PRIV_PAGES=1\nCONFIG_PADATA=y\nCONFIG_PAGE_REPORTING=y\nCONFIG_PARAVIRT=y\nCONFIG_PARTITION_PERCPU=y\nCONFIG_PCI=y\nCONFIG_PCIEAER=y\nCONFIG_PCIEPORTBUS=y\nCONFIG_PCIE_PME=y\nCONFIG_PCI_ATS=y\nCONFIG_PCI_DOMAINS=y\nCONFIG_PCI_DOMAINS_GENERIC=y\nCONFIG_PCI_ECAM=y\nCONFIG_PCI_HOST_COMMON=y\nCONFIG_PCI_HOST_GENERIC=y\nCONFIG_PCI_HOST_THUNDER_ECAM=y\nCONFIG_PCI_HOST_THUNDER_PEM=y\nCONFIG_PCI_IOV=y\nCONFIG_PCI_MSI=y\nCONFIG_PCI_MSI_IRQ_DOMAIN=y\nCONFIG_PGTABLE_LEVELS=4\nCONFIG_PHYLIB=y\nCONFIG_PHYS_ADDR_T_64BIT=y\nCONFIG_PM=y\nCONFIG_PM_CLK=y\nCONFIG_PM_SLEEP=y\nCONFIG_PM_SLEEP_SMP=y\nCONFIG_PM_STD_PARTITION=\"\"\nCONFIG_POSIX_MQUEUE=y\nCONFIG_POSIX_MQUEUE_SYSCTL=y\nCONFIG_POWER_RESET=y\nCONFIG_POWER_RESET_SYSCON=y\nCONFIG_POWER_RESET_XGENE=y\nCONFIG_POWER_SUPPLY=y\nCONFIG_PROC_VMCORE=y\nCONFIG_QUEUED_RWLOCKS=y\nCONFIG_QUEUED_SPINLOCKS=y\nCONFIG_RAS=y\nCONFIG_RATIONAL=y\n# CONFIG_RAVE_SP_CORE is not set\nCONFIG_REBOOT_MODE=y\nCONFIG_REGMAP=y\nCONFIG_REGMAP_I2C=y\nCONFIG_REGMAP_MMIO=y\nCONFIG_RESET_CONTROLLER=y\nCONFIG_RFS_ACCEL=y\nCONFIG_RODATA_FULL_DEFAULT_ENABLED=y\nCONFIG_RPS=y\nCONFIG_RTC_CLASS=y\nCONFIG_RTC_DRV_DS1672=y\nCONFIG_RTC_I2C_AND_SPI=y\nCONFIG_RWSEM_SPIN_ON_OWNER=y\nCONFIG_SATA_AHCI=y\nCONFIG_SATA_AHCI_PLATFORM=y\nCONFIG_SATA_HOST=y\nCONFIG_SCHED_INFO=y\nCONFIG_SCHED_MC=y\nCONFIG_SCSI=y\n# CONFIG_SCSI_LOWLEVEL is not set\n# CONFIG_SCSI_PROC_FS is not set\nCONFIG_SCSI_SAS_ATA=y\nCONFIG_SCSI_SAS_ATTRS=y\nCONFIG_SCSI_SAS_HOST_SMP=y\nCONFIG_SCSI_SAS_LIBSAS=y\nCONFIG_SECCOMP=y\nCONFIG_SECCOMP_FILTER=y\nCONFIG_SERIAL_8250_DW=y\nCONFIG_SERIAL_8250_DWLIB=y\nCONFIG_SERIAL_8250_EXTENDED=y\nCONFIG_SERIAL_8250_FSL=y\nCONFIG_SERIAL_8250_SHARE_IRQ=y\nCONFIG_SERIAL_AMBA_PL011=y\nCONFIG_SERIAL_AMBA_PL011_CONSOLE=y\nCONFIG_SERIAL_DEV_BUS=y\nCONFIG_SERIAL_DEV_CTRL_TTYPORT=y\nCONFIG_SERIAL_MCTRL_GPIO=y\nCONFIG_SERIAL_OF_PLATFORM=y\nCONFIG_SERIAL_XILINX_PS_UART=y\nCONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y\nCONFIG_SG_POOL=y\nCONFIG_SMP=y\nCONFIG_SPARSEMEM=y\nCONFIG_SPARSEMEM_EXTREME=y\nCONFIG_SPARSEMEM_MANUAL=y\nCONFIG_SPARSEMEM_VMEMMAP=y\nCONFIG_SPARSEMEM_VMEMMAP_ENABLE=y\nCONFIG_SPARSE_IRQ=y\nCONFIG_SPI=y\nCONFIG_SPI_MASTER=y\nCONFIG_SPI_THUNDERX=y\nCONFIG_SRAM=y\nCONFIG_SRCU=y\nCONFIG_SWIOTLB=y\nCONFIG_SWPHY=y\nCONFIG_SYNC_FILE=y\nCONFIG_SYSCON_REBOOT_MODE=y\nCONFIG_SYSCTL_EXCEPTION_TRACE=y\nCONFIG_SYS_SUPPORTS_HUGETLBFS=y\nCONFIG_TASKSTATS=y\nCONFIG_TASK_DELAY_ACCT=y\nCONFIG_TASK_IO_ACCOUNTING=y\nCONFIG_TASK_XACCT=y\nCONFIG_TEE=y\nCONFIG_THREAD_INFO_IN_TASK=y\nCONFIG_THUNDER_NIC_BGX=y\nCONFIG_THUNDER_NIC_PF=y\nCONFIG_THUNDER_NIC_RGX=y\nCONFIG_THUNDER_NIC_VF=y\nCONFIG_TICK_CPU_ACCOUNTING=y\nCONFIG_TIMER_OF=y\nCONFIG_TIMER_PROBE=y\nCONFIG_TRANSPARENT_HUGEPAGE=y\nCONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y\n# CONFIG_TRANSPARENT_HUGEPAGE_MADVISE is not set\nCONFIG_TREE_RCU=y\nCONFIG_TREE_SRCU=y\nCONFIG_UNMAP_KERNEL_AT_EL0=y\nCONFIG_USB=y\nCONFIG_USB_COMMON=y\nCONFIG_USB_PCI=y\nCONFIG_USB_SUPPORT=y\n# CONFIG_USB_UHCI_HCD is not set\nCONFIG_USB_XHCI_HCD=y\nCONFIG_USB_XHCI_PCI=y\nCONFIG_USB_XHCI_PLATFORM=y\nCONFIG_USE_PERCPU_NUMA_NODE_ID=y\nCONFIG_VIRTIO=y\nCONFIG_VIRTIO_BALLOON=y\n# CONFIG_VIRTIO_BLK is not set\nCONFIG_VIRTIO_MMIO=y\n# CONFIG_VIRTIO_NET is not set\nCONFIG_VIRTIO_PCI=y\nCONFIG_VIRTIO_PCI_LEGACY=y\nCONFIG_VMAP_STACK=y\nCONFIG_WATCHDOG_CORE=y\nCONFIG_XARRAY_MULTI=y\nCONFIG_XPS=y\nCONFIG_XXHASH=y\nCONFIG_ZONE_DMA32=y\n"
  },
  {
    "path": "target/linux/octeontx/image/Makefile",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2018 OpenWrt.org\n\ninclude $(TOPDIR)/rules.mk\ninclude $(INCLUDE_DIR)/image.mk\n\ndefine Image/Build/Initramfs\n\t$(CP) $(KERNEL_BUILD_DIR)/vmlinux $(BIN_DIR)/$(IMG_PREFIX)-vmlinux\n\t$(CP) $(KERNEL_BUILD_DIR)/vmlinux-initramfs $(BIN_DIR)/$(IMG_PREFIX)-vmlinux-initramfs\nendef\n\ndefine Image/Build\n\t$(call Image/Build/$(1))\n\tcp $(KDIR)/root.$(1) $(BIN_DIR)/$(IMG_PREFIX)-$(1).img\n\tcp $(KDIR)/vmlinux $(BIN_DIR)/$(IMG_PREFIX)-vmlinux\nendef\n\n$(eval $(call BuildImage))\n"
  },
  {
    "path": "target/linux/octeontx/patches-5.10/0004-PCI-add-quirk-for-Gateworks-PLX-PEX860x-switch-with-.patch",
    "content": "From d0ff7a1bcfe886cab1a237895b08ac51ecfe10e7 Mon Sep 17 00:00:00 2001\nFrom: Tim Harvey <tharvey@gateworks.com>\nDate: Wed, 10 Apr 2019 08:00:47 -0700\nSubject: [PATCH 04/12] PCI: add quirk for Gateworks PLX PEX860x switch with\n GPIO PERST#\n\nGateworks boards use PLX PEX860x switches where downstream ports\nhave their PERST# driven from the PEX GPIO.\n\nSigned-off-by: Tim Harvey <tharvey@gateworks.com>\n---\n drivers/pci/quirks.c | 32 ++++++++++++++++++++++++++++++++\n 1 file changed, 32 insertions(+)\n\n--- a/drivers/pci/quirks.c\n+++ b/drivers/pci/quirks.c\n@@ -25,6 +25,7 @@\n #include <linux/ktime.h>\n #include <linux/mm.h>\n #include <linux/nvme.h>\n+#include <linux/of.h>\n #include <linux/platform_data/x86/apple.h>\n #include <linux/pm_runtime.h>\n #include <linux/suspend.h>\n@@ -5784,3 +5785,34 @@ static void nvidia_ion_ahci_fixup(struct\n \tpdev->dev_flags |= PCI_DEV_FLAGS_HAS_MSI_MASKING;\n }\n DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, 0x0ab8, nvidia_ion_ahci_fixup);\n+\n+#ifdef CONFIG_PCI_HOST_THUNDER_PEM\n+/*\n+ * fixup for PLX PEX8909 bridge to configure GPIO1-7 as output High\n+ * as they are used for slots1-7 PERST#\n+ */\n+static void newport_pciesw_early_fixup(struct pci_dev *dev)\n+{\n+\tu32 dw;\n+\n+\tif (!of_machine_is_compatible(\"gw,newport\"))\n+\t\treturn;\n+\n+\tif (dev->devfn != 0)\n+\t\treturn;\n+\n+\tdev_info(&dev->dev, \"de-asserting PERST#\\n\");\n+\tpci_read_config_dword(dev, 0x62c, &dw);\n+\tdw |= 0xaaa8; /* GPIO1-7 outputs */\n+\tpci_write_config_dword(dev, 0x62c, dw);\n+\n+\tpci_read_config_dword(dev, 0x644, &dw);\n+\tdw |= 0xfe;   /* GPIO1-7 output high */\n+\tpci_write_config_dword(dev, 0x644, dw);\n+\n+\tmsleep(100);\n+}\n+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8609, newport_pciesw_early_fixup);\n+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8606, newport_pciesw_early_fixup);\n+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8604, newport_pciesw_early_fixup);\n+#endif /* CONFIG_PCI_HOST_THUNDER_PEM */\n"
  },
  {
    "path": "target/linux/omap/Makefile",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2012-2014 OpenWrt.org\n\ninclude $(TOPDIR)/rules.mk\n\nARCH:=arm\nBOARD:=omap\nBOARDNAME:=TI OMAP3/4/AM33xx\nFEATURES:=usb usbgadget ext4 targz fpu audio display nand rootfs-part squashfs\nCPU_TYPE:=cortex-a8\nCPU_SUBTYPE:=vfpv3\n\nKERNEL_PATCHVER:=5.10\n\nKERNELNAME:=zImage dtbs\n\ndefine Target/Description\n\tTI OMAP boards\nendef\n\ninclude $(INCLUDE_DIR)/target.mk\n\nDEFAULT_PACKAGES += partx-utils mkf2fs e2fsprogs\n\n$(eval $(call BuildTarget))\n"
  },
  {
    "path": "target/linux/omap/base-files/etc/inittab",
    "content": "::sysinit:/etc/init.d/rcS S boot\n::shutdown:/etc/init.d/rcS K shutdown\nttyO0::askfirst:/usr/libexec/login.sh\nttyO2::askfirst:/usr/libexec/login.sh\ntty1::askfirst:/usr/libexec/login.sh\n"
  },
  {
    "path": "target/linux/omap/base-files/lib/preinit/79_move_config",
    "content": "# Copyright (C) 2012-2015 OpenWrt.org\n\nmove_config() {\n\tlocal partdev\n\n\t. /lib/upgrade/common.sh\n\n\tif export_bootdevice && export_partdevice partdev 1; then\n\t\tif mount -t vfat -o rw,noatime \"/dev/$partdev\" /mnt; then\n\t\t\tif [ -f \"/mnt/$BACKUP_FILE\" ]; then\n\t\t\t\tmv -f \"/mnt/$BACKUP_FILE\" /\n\t\t\tfi\n\t\t\tumount /mnt\n\t\tfi\n\tfi\n}\n\nboot_hook_add preinit_mount_root move_config\n\n"
  },
  {
    "path": "target/linux/omap/base-files/lib/upgrade/platform.sh",
    "content": "platform_check_image() {\n\tlocal diskdev partdev diff\n\n\texport_bootdevice && export_partdevice diskdev 0 || {\n\t\techo \"Unable to determine upgrade device\"\n\t\treturn 1\n\t}\n\n\tget_partitions \"/dev/$diskdev\" bootdisk\n\n\t#extract the boot sector from the image\n\tget_image \"$@\" | dd of=/tmp/image.bs count=1 bs=512b 2>/dev/null\n\n\tget_partitions /tmp/image.bs image\n\n\t#compare tables\n\tdiff=\"$(grep -F -x -v -f /tmp/partmap.bootdisk /tmp/partmap.image)\"\n\n\trm -f /tmp/image.bs /tmp/partmap.bootdisk /tmp/partmap.image\n\n\tif [ -n \"$diff\" ]; then\n\t\techo \"Partition layout has changed. Full image will be written.\"\n\t\task_bool 0 \"Abort\" && exit 1\n\t\treturn 0\n\tfi\n}\n\nplatform_copy_config() {\n\tlocal partdev\n\n\tif export_partdevice partdev 1; then\n\t\tmount -t vfat -o rw,noatime \"/dev/$partdev\" /mnt\n\t\tcp -af \"$UPGRADE_BACKUP\" \"/mnt/$BACKUP_FILE\"\n\t\tumount /mnt\n\tfi\n}\n\nplatform_do_upgrade() {\n\tlocal diskdev partdev diff\n\n\texport_bootdevice && export_partdevice diskdev 0 || {\n\t\techo \"Unable to determine upgrade device\"\n\t\treturn 1\n\t}\n\n\tsync\n\n\tif [ \"$UPGRADE_OPT_SAVE_PARTITIONS\" = \"1\" ]; then\n\t\tget_partitions \"/dev/$diskdev\" bootdisk\n\n\t\t#extract the boot sector from the image\n\t\tget_image \"$@\" | dd of=/tmp/image.bs count=1 bs=512b\n\n\t\tget_partitions /tmp/image.bs image\n\n\t\t#compare tables\n\t\tdiff=\"$(grep -F -x -v -f /tmp/partmap.bootdisk /tmp/partmap.image)\"\n\telse\n\t\tdiff=1\n\tfi\n\n\tif [ -n \"$diff\" ]; then\n\t\tget_image \"$@\" | dd of=\"/dev/$diskdev\" bs=4096 conv=fsync\n\n\t\t# Separate removal and addtion is necessary; otherwise, partition 1\n\t\t# will be missing if it overlaps with the old partition 2\n\t\tpartx -d - \"/dev/$diskdev\"\n\t\tpartx -a - \"/dev/$diskdev\"\n\n\t\treturn 0\n\tfi\n\n\t#write uboot image\n\tget_image \"$@\" | dd of=\"$diskdev\" bs=1024 skip=8 seek=8 count=1016 conv=fsync\n\t#iterate over each partition from the image and write it to the boot disk\n\twhile read part start size; do\n\t\tif export_partdevice partdev $part; then\n\t\t\techo \"Writing image to /dev/$partdev...\"\n\t\t\tget_image \"$@\" | dd of=\"/dev/$partdev\" ibs=\"512\" obs=1M skip=\"$start\" count=\"$size\" conv=fsync\n\t\telse\n\t\t\techo \"Unable to find partition $part device, skipped.\"\n\t\tfi\n\tdone < /tmp/partmap.image\n\n\t#copy partition uuid\n\techo \"Writing new UUID to /dev/$diskdev...\"\n\tget_image \"$@\" | dd of=\"/dev/$diskdev\" bs=1 skip=440 count=4 seek=440 conv=fsync\n}\n"
  },
  {
    "path": "target/linux/omap/config-5.10",
    "content": "# CONFIG_AHCI_DM816 is not set\nCONFIG_ALIGNMENT_TRAP=y\nCONFIG_AM335X_CONTROL_USB=y\nCONFIG_AM335X_PHY_USB=y\nCONFIG_ARCH_32BIT_OFF_T=y\nCONFIG_ARCH_HIBERNATION_POSSIBLE=y\nCONFIG_ARCH_KEEP_MEMBLOCK=y\nCONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y\nCONFIG_ARCH_MULTIPLATFORM=y\nCONFIG_ARCH_MULTI_V6_V7=y\nCONFIG_ARCH_MULTI_V7=y\nCONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED=y\nCONFIG_ARCH_NR_GPIO=0\nCONFIG_ARCH_OMAP=y\nCONFIG_ARCH_OMAP2PLUS=y\nCONFIG_ARCH_OMAP2PLUS_TYPICAL=y\nCONFIG_ARCH_OMAP3=y\nCONFIG_ARCH_OMAP4=y\nCONFIG_ARCH_OPTIONAL_KERNEL_RWX=y\nCONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y\nCONFIG_ARCH_SELECT_MEMORY_MODEL=y\nCONFIG_ARCH_SPARSEMEM_ENABLE=y\nCONFIG_ARCH_SUSPEND_POSSIBLE=y\nCONFIG_ARM=y\nCONFIG_ARM_APPENDED_DTB=y\nCONFIG_ARM_ATAG_DTB_COMPAT=y\nCONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y\nCONFIG_ARM_CPU_SUSPEND=y\nCONFIG_ARM_ERRATA_430973=y\nCONFIG_ARM_ERRATA_720789=y\nCONFIG_ARM_ERRATA_754322=y\nCONFIG_ARM_ERRATA_775420=y\nCONFIG_ARM_GIC=y\nCONFIG_ARM_HAS_SG_CHAIN=y\nCONFIG_ARM_HEAVY_MB=y\nCONFIG_ARM_L1_CACHE_SHIFT=6\nCONFIG_ARM_L1_CACHE_SHIFT_6=y\nCONFIG_ARM_OMAP2PLUS_CPUFREQ=y\nCONFIG_ARM_PATCH_IDIV=y\nCONFIG_ARM_PATCH_PHYS_VIRT=y\nCONFIG_ARM_THUMB=y\nCONFIG_ARM_THUMBEE=y\nCONFIG_ARM_TI_CPUFREQ=y\nCONFIG_ARM_UNWIND=y\nCONFIG_ARM_VIRT_EXT=y\nCONFIG_ASSOCIATIVE_ARRAY=y\nCONFIG_AT803X_PHY=y\nCONFIG_ATA=y\nCONFIG_AUDIT=y\nCONFIG_AUDITSYSCALL=y\nCONFIG_AUDIT_GENERIC=y\nCONFIG_AUTO_ZRELADDR=y\nCONFIG_BACKLIGHT_CLASS_DEVICE=y\n# CONFIG_BACKLIGHT_TPS65217 is not set\nCONFIG_BCH=y\nCONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y\nCONFIG_BLK_DEV_LOOP=y\nCONFIG_BLK_DEV_RAM=y\nCONFIG_BLK_DEV_RAM_COUNT=16\nCONFIG_BLK_DEV_RAM_SIZE=16384\nCONFIG_BLK_DEV_SD=y\nCONFIG_BLK_PM=y\nCONFIG_BLK_SCSI_REQUEST=y\nCONFIG_BOUNCE=y\nCONFIG_BSD_PROCESS_ACCT=y\nCONFIG_CACHE_L2X0=y\nCONFIG_CEC_CORE=y\n# CONFIG_CHARGER_TPS65217 is not set\nCONFIG_CLKDEV_LOOKUP=y\nCONFIG_CLKSRC_MMIO=y\nCONFIG_CLKSRC_TI_32K=y\nCONFIG_CLK_TWL6040=y\nCONFIG_CLONE_BACKWARDS=y\nCONFIG_CMA=y\nCONFIG_CMA_ALIGNMENT=8\nCONFIG_CMA_AREAS=7\n# CONFIG_CMA_DEBUG is not set\n# CONFIG_CMA_DEBUGFS is not set\nCONFIG_CMA_SIZE_MBYTES=16\n# CONFIG_CMA_SIZE_SEL_MAX is not set\nCONFIG_CMA_SIZE_SEL_MBYTES=y\n# CONFIG_CMA_SIZE_SEL_MIN is not set\n# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set\nCONFIG_CMDLINE=\"root=/dev/mmcblk0p2 rootwait console=ttyO2,115200\"\nCONFIG_COMMON_CLK=y\n# CONFIG_COMMON_CLK_PALMAS is not set\n# CONFIG_COMMON_CLK_TI_ADPLL is not set\nCONFIG_COMPAT_32BIT_TIME=y\nCONFIG_CONFIGFS_FS=y\nCONFIG_CONNECTOR=y\nCONFIG_CONTIG_ALLOC=y\nCONFIG_CPUFREQ_DT=y\nCONFIG_CPUFREQ_DT_PLATDEV=y\nCONFIG_CPU_32v6K=y\nCONFIG_CPU_32v7=y\nCONFIG_CPU_ABRT_EV7=y\nCONFIG_CPU_CACHE_V7=y\nCONFIG_CPU_CACHE_VIPT=y\nCONFIG_CPU_COPY_V6=y\nCONFIG_CPU_CP15=y\nCONFIG_CPU_CP15_MMU=y\nCONFIG_CPU_FREQ=y\nCONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y\n# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set\nCONFIG_CPU_FREQ_GOV_ATTR_SET=y\nCONFIG_CPU_FREQ_GOV_COMMON=y\nCONFIG_CPU_FREQ_GOV_CONSERVATIVE=y\nCONFIG_CPU_FREQ_GOV_ONDEMAND=y\nCONFIG_CPU_FREQ_GOV_PERFORMANCE=y\nCONFIG_CPU_FREQ_GOV_POWERSAVE=y\nCONFIG_CPU_FREQ_GOV_USERSPACE=y\nCONFIG_CPU_FREQ_STAT=y\nCONFIG_CPU_HAS_ASID=y\nCONFIG_CPU_IDLE=y\nCONFIG_CPU_IDLE_GOV_LADDER=y\nCONFIG_CPU_IDLE_GOV_MENU=y\nCONFIG_CPU_PABRT_V7=y\nCONFIG_CPU_PM=y\nCONFIG_CPU_RMAP=y\nCONFIG_CPU_SPECTRE=y\nCONFIG_CPU_THERMAL=y\nCONFIG_CPU_THUMB_CAPABLE=y\nCONFIG_CPU_TLB_V7=y\nCONFIG_CPU_V7=y\nCONFIG_CRAMFS=y\nCONFIG_CRC16=y\nCONFIG_CRC7=y\nCONFIG_CRC_CCITT=y\nCONFIG_CRC_ITU_T=y\nCONFIG_CRC_T10DIF=y\nCONFIG_CRYPTO_CBC=y\nCONFIG_CRYPTO_CRC32=y\nCONFIG_CRYPTO_CRC32C=y\nCONFIG_CRYPTO_CRCT10DIF=y\nCONFIG_CRYPTO_DEFLATE=y\nCONFIG_CRYPTO_DES=y\nCONFIG_CRYPTO_DEV_OMAP=y\nCONFIG_CRYPTO_DEV_OMAP_AES=y\nCONFIG_CRYPTO_DEV_OMAP_DES=y\nCONFIG_CRYPTO_DEV_OMAP_SHAM=y\nCONFIG_CRYPTO_DRBG=y\nCONFIG_CRYPTO_DRBG_HMAC=y\nCONFIG_CRYPTO_DRBG_MENU=y\nCONFIG_CRYPTO_ECB=y\nCONFIG_CRYPTO_ENGINE=y\nCONFIG_CRYPTO_HASH_INFO=y\nCONFIG_CRYPTO_HMAC=y\nCONFIG_CRYPTO_HW=y\nCONFIG_CRYPTO_JITTERENTROPY=y\nCONFIG_CRYPTO_LIB_DES=y\nCONFIG_CRYPTO_LIB_SHA256=y\nCONFIG_CRYPTO_LZO=y\nCONFIG_CRYPTO_MD5=y\nCONFIG_CRYPTO_RNG=y\nCONFIG_CRYPTO_RNG2=y\nCONFIG_CRYPTO_RNG_DEFAULT=y\nCONFIG_CRYPTO_SEQIV=y\nCONFIG_CRYPTO_SHA1=y\nCONFIG_CRYPTO_SHA256=y\nCONFIG_CRYPTO_SHA512=y\nCONFIG_CRYPTO_ZSTD=y\nCONFIG_DCACHE_WORD_ACCESS=y\nCONFIG_DDR=y\nCONFIG_DEBUG_INFO=y\nCONFIG_DEBUG_LL_INCLUDE=\"mach/debug-macro.S\"\nCONFIG_DM9000=y\n# CONFIG_DM9000_FORCE_SIMPLE_PHY_POLL is not set\nCONFIG_DMADEVICES=y\nCONFIG_DMA_CMA=y\nCONFIG_DMA_ENGINE=y\nCONFIG_DMA_OF=y\nCONFIG_DMA_OMAP=y\nCONFIG_DMA_OPS=y\nCONFIG_DMA_REMAP=y\nCONFIG_DMA_SHARED_BUFFER=y\nCONFIG_DMA_VIRTUAL_CHANNELS=y\nCONFIG_DNS_RESOLVER=y\nCONFIG_DRM=y\nCONFIG_DRM_BRIDGE=y\nCONFIG_DRM_DISPLAY_CONNECTOR=y\nCONFIG_DRM_KMS_HELPER=y\nCONFIG_DRM_OMAP=y\nCONFIG_DRM_OMAP_PANEL_DSI_CM=y\nCONFIG_DRM_PANEL=y\nCONFIG_DRM_PANEL_BRIDGE=y\nCONFIG_DRM_PANEL_LG_LB035Q02=y\nCONFIG_DRM_PANEL_NEC_NL8048HL11=y\nCONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y\nCONFIG_DRM_PANEL_SHARP_LS037V7DW01=y\nCONFIG_DRM_PANEL_SONY_ACX565AKM=y\nCONFIG_DRM_PANEL_TPO_TD028TTEC1=y\nCONFIG_DRM_PANEL_TPO_TD043MTEA1=y\nCONFIG_DRM_SIMPLE_BRIDGE=y\nCONFIG_DRM_TI_TFP410=y\nCONFIG_DRM_TI_TPD12S015=y\nCONFIG_DTC=y\nCONFIG_EDAC_ATOMIC_SCRUB=y\nCONFIG_EDAC_SUPPORT=y\nCONFIG_EEPROM_93CX6=y\nCONFIG_EXT4_FS=y\nCONFIG_EXTCON=y\nCONFIG_EXTCON_PALMAS=y\nCONFIG_EXTCON_USB_GPIO=y\nCONFIG_F2FS_FS=y\nCONFIG_FANOTIFY=y\nCONFIG_FAT_FS=y\nCONFIG_FB_CMDLINE=y\nCONFIG_FHANDLE=y\nCONFIG_FIXED_PHY=y\nCONFIG_FIX_EARLYCON_MEM=y\nCONFIG_FS_IOMAP=y\nCONFIG_FS_MBCACHE=y\nCONFIG_FS_POSIX_ACL=y\nCONFIG_FW_LOADER_PAGED_BUF=y\nCONFIG_GENERIC_ALLOCATOR=y\nCONFIG_GENERIC_ARCH_TOPOLOGY=y\nCONFIG_GENERIC_BUG=y\nCONFIG_GENERIC_CLOCKEVENTS=y\nCONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y\nCONFIG_GENERIC_CPU_AUTOPROBE=y\nCONFIG_GENERIC_EARLY_IOREMAP=y\nCONFIG_GENERIC_GETTIMEOFDAY=y\nCONFIG_GENERIC_IDLE_POLL_SETUP=y\nCONFIG_GENERIC_IRQ_CHIP=y\nCONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y\nCONFIG_GENERIC_IRQ_MULTI_HANDLER=y\nCONFIG_GENERIC_IRQ_SHOW=y\nCONFIG_GENERIC_IRQ_SHOW_LEVEL=y\nCONFIG_GENERIC_PCI_IOMAP=y\nCONFIG_GENERIC_PHY=y\nCONFIG_GENERIC_PINCONF=y\nCONFIG_GENERIC_PINCTRL_GROUPS=y\nCONFIG_GENERIC_PINMUX_FUNCTIONS=y\nCONFIG_GENERIC_SCHED_CLOCK=y\nCONFIG_GENERIC_SMP_IDLE_THREAD=y\nCONFIG_GENERIC_STRNCPY_FROM_USER=y\nCONFIG_GENERIC_STRNLEN_USER=y\nCONFIG_GENERIC_TIME_VSYSCALL=y\nCONFIG_GENERIC_VDSO_32=y\nCONFIG_GLOB=y\nCONFIG_GPIOLIB=y\nCONFIG_GPIOLIB_IRQCHIP=y\nCONFIG_GPIO_OMAP=y\nCONFIG_GPIO_PALMAS=y\nCONFIG_GPIO_PCA953X=y\nCONFIG_GPIO_PCA953X_IRQ=y\nCONFIG_GPIO_PCF857X=y\n# CONFIG_GPIO_TPS65218 is not set\nCONFIG_GPIO_TPS65910=y\nCONFIG_GPIO_TWL4030=y\nCONFIG_GPIO_TWL6040=y\nCONFIG_GRACE_PERIOD=y\nCONFIG_GRO_CELLS=y\nCONFIG_HANDLE_DOMAIN_IRQ=y\nCONFIG_HARDEN_BRANCH_PREDICTOR=y\nCONFIG_HARDIRQS_SW_RESEND=y\nCONFIG_HAS_DMA=y\nCONFIG_HAS_IOMEM=y\nCONFIG_HAS_IOPORT_MAP=y\nCONFIG_HAVE_SMP=y\nCONFIG_HDMI=y\nCONFIG_HIGHMEM=y\nCONFIG_HIGHPTE=y\nCONFIG_HSI=y\nCONFIG_HSI_BOARDINFO=y\n# CONFIG_HSI_CHAR is not set\nCONFIG_HWMON=y\nCONFIG_HW_RANDOM=y\nCONFIG_HW_RANDOM_OMAP=y\nCONFIG_HZ_FIXED=0\nCONFIG_I2C=y\nCONFIG_I2C_ALGOBIT=y\nCONFIG_I2C_BOARDINFO=y\nCONFIG_I2C_CHARDEV=y\nCONFIG_I2C_OMAP=y\nCONFIG_IKCONFIG=y\nCONFIG_IKCONFIG_PROC=y\nCONFIG_INITRAMFS_SOURCE=\"\"\nCONFIG_IP_PNP=y\nCONFIG_IP_PNP_BOOTP=y\nCONFIG_IP_PNP_DHCP=y\nCONFIG_IP_PNP_RARP=y\nCONFIG_IRQCHIP=y\nCONFIG_IRQ_DOMAIN=y\nCONFIG_IRQ_DOMAIN_HIERARCHY=y\nCONFIG_IRQ_FORCED_THREADING=y\nCONFIG_IRQ_WORK=y\nCONFIG_JBD2=y\nCONFIG_JFFS2_LZO=y\nCONFIG_JFFS2_RUBIN=y\nCONFIG_KALLSYMS=y\nCONFIG_KALLSYMS_ALL=y\nCONFIG_KCMP=y\nCONFIG_KEYS=y\nCONFIG_KPROBES=y\nCONFIG_KRETPROBES=y\nCONFIG_KS8851=y\nCONFIG_KS8851_MLL=y\nCONFIG_LCD_CLASS_DEVICE=y\nCONFIG_LCD_PLATFORM=y\nCONFIG_LEDS_GPIO=y\nCONFIG_LEDS_PWM=y\nCONFIG_LEDS_TRIGGER_BACKLIGHT=y\nCONFIG_LEDS_TRIGGER_CPU=y\nCONFIG_LEDS_TRIGGER_GPIO=y\nCONFIG_LEDS_TRIGGER_ONESHOT=y\nCONFIG_LIBCRC32C=y\nCONFIG_LIBFDT=y\nCONFIG_LOCKD=y\nCONFIG_LOCK_DEBUGGING_SUPPORT=y\nCONFIG_LOCK_SPIN_ON_OWNER=y\nCONFIG_LZO_COMPRESS=y\nCONFIG_LZO_DECOMPRESS=y\n# CONFIG_MACH_OMAP3517EVM is not set\n# CONFIG_MACH_OMAP3_PANDORA is not set\nCONFIG_MACH_OMAP_GENERIC=y\nCONFIG_MAGIC_SYSRQ=y\nCONFIG_MDIO_BUS=y\nCONFIG_MDIO_DEVICE=y\nCONFIG_MDIO_DEVRES=y\nCONFIG_MEMFD_CREATE=y\nCONFIG_MEMORY=y\nCONFIG_MEMORY_ISOLATION=y\nCONFIG_MFD_CORE=y\nCONFIG_MFD_PALMAS=y\nCONFIG_MFD_SYSCON=y\nCONFIG_MFD_TI_AM335X_TSCADC=y\nCONFIG_MFD_TPS65217=y\nCONFIG_MFD_TPS65218=y\nCONFIG_MFD_TPS65910=y\nCONFIG_MFD_TWL4030_AUDIO=y\nCONFIG_MIGHT_HAVE_CACHE_L2X0=y\nCONFIG_MIGRATION=y\nCONFIG_MMC=y\nCONFIG_MMC_BLOCK=y\n# CONFIG_MMC_OMAP is not set\nCONFIG_MMC_OMAP_HS=y\nCONFIG_MMC_SDHCI=y\nCONFIG_MMC_SDHCI_EXTERNAL_DMA=y\nCONFIG_MMC_SDHCI_OMAP=y\nCONFIG_MMC_SDHCI_PLTFM=y\nCONFIG_MODULES_USE_ELF_REL=y\nCONFIG_MSDOS_FS=y\nCONFIG_MTD_CMDLINE_PARTS=y\nCONFIG_MTD_NAND_CORE=y\nCONFIG_MTD_NAND_ECC=y\nCONFIG_MTD_NAND_ECC_SW_HAMMING=y\nCONFIG_MTD_NAND_OMAP2=y\nCONFIG_MTD_NAND_OMAP_BCH=y\nCONFIG_MTD_NAND_OMAP_BCH_BUILD=y\nCONFIG_MTD_ONENAND=y\n# CONFIG_MTD_ONENAND_2X_PROGRAM is not set\n# CONFIG_MTD_ONENAND_GENERIC is not set\nCONFIG_MTD_ONENAND_OMAP2=y\n# CONFIG_MTD_ONENAND_OTP is not set\nCONFIG_MTD_ONENAND_VERIFY_WRITE=y\nCONFIG_MTD_OOPS=y\nCONFIG_MTD_PHYSMAP=y\nCONFIG_MTD_RAW_NAND=y\nCONFIG_MTD_SPI_NOR=y\nCONFIG_MTD_UBI=y\nCONFIG_MTD_UBI_BEB_LIMIT=20\n# CONFIG_MTD_UBI_BLOCK is not set\nCONFIG_MTD_UBI_WL_THRESHOLD=4096\n# CONFIG_MUSB_PIO_ONLY is not set\nCONFIG_MUTEX_SPIN_ON_OWNER=y\nCONFIG_NEED_DMA_MAP_STATE=y\nCONFIG_NEON=y\nCONFIG_NET_FLOW_LIMIT=y\nCONFIG_NET_KEY=y\nCONFIG_NET_KEY_MIGRATE=y\nCONFIG_NET_PTP_CLASSIFY=y\nCONFIG_NFS_ACL_SUPPORT=y\nCONFIG_NFS_FS=y\nCONFIG_NFS_USE_KERNEL_DNS=y\n# CONFIG_NFS_USE_LEGACY_DNS is not set\nCONFIG_NFS_V3_ACL=y\nCONFIG_NFS_V4=y\nCONFIG_NLS=y\nCONFIG_NLS_CODEPAGE_437=y\nCONFIG_NLS_ISO8859_1=y\nCONFIG_NOP_USB_XCEIV=y\nCONFIG_NO_HZ=y\nCONFIG_NO_HZ_COMMON=y\nCONFIG_NO_HZ_IDLE=y\nCONFIG_NR_CPUS=4\nCONFIG_NVMEM=y\nCONFIG_OF=y\nCONFIG_OF_ADDRESS=y\nCONFIG_OF_EARLY_FLATTREE=y\nCONFIG_OF_FLATTREE=y\nCONFIG_OF_GPIO=y\nCONFIG_OF_IRQ=y\nCONFIG_OF_KOBJ=y\nCONFIG_OF_MDIO=y\nCONFIG_OF_NET=y\nCONFIG_OID_REGISTRY=y\nCONFIG_OLD_SIGACTION=y\nCONFIG_OLD_SIGSUSPEND3=y\nCONFIG_OMAP2_DSS=y\nCONFIG_OMAP2_DSS_DPI=y\nCONFIG_OMAP2_DSS_DSI=y\nCONFIG_OMAP2_DSS_HDMI_COMMON=y\nCONFIG_OMAP2_DSS_INIT=y\nCONFIG_OMAP2_DSS_MIN_FCK_PER_PCK=0\nCONFIG_OMAP2_DSS_SDI=y\nCONFIG_OMAP2_DSS_SLEEP_AFTER_VENC_RESET=y\nCONFIG_OMAP2_DSS_VENC=y\n# CONFIG_OMAP3_L2_AUX_SECURE_SAVE_RESTORE is not set\n# CONFIG_OMAP3_SDRC_AC_TIMING is not set\nCONFIG_OMAP3_THERMAL=y\nCONFIG_OMAP4_DSS_HDMI=y\nCONFIG_OMAP4_DSS_HDMI_CEC=y\nCONFIG_OMAP4_THERMAL=y\nCONFIG_OMAP5_DSS_HDMI=y\nCONFIG_OMAP_32K_TIMER=y\nCONFIG_OMAP_CONTROL_PHY=y\nCONFIG_OMAP_DM_TIMER=y\nCONFIG_OMAP_DSS_BASE=y\nCONFIG_OMAP_GPMC=y\n# CONFIG_OMAP_GPMC_DEBUG is not set\nCONFIG_OMAP_INTERCONNECT=y\nCONFIG_OMAP_INTERCONNECT_BARRIER=y\nCONFIG_OMAP_IRQCHIP=y\nCONFIG_OMAP_OCP2SCP=y\nCONFIG_OMAP_RESET_CLOCKS=y\n# CONFIG_OMAP_SSI is not set\nCONFIG_OMAP_USB2=y\nCONFIG_OMAP_WATCHDOG=y\nCONFIG_OPROFILE=y\nCONFIG_OPTPROBES=y\nCONFIG_OUTER_CACHE=y\nCONFIG_OUTER_CACHE_SYNC=y\nCONFIG_PADATA=y\nCONFIG_PAGE_OFFSET=0xC0000000\nCONFIG_PAGE_POOL=y\nCONFIG_PERF_USE_VMALLOC=y\nCONFIG_PGTABLE_LEVELS=2\nCONFIG_PHYLIB=y\n# CONFIG_PHY_DM816X_USB is not set\nCONFIG_PHY_TI_GMII_SEL=y\nCONFIG_PINCTRL=y\n# CONFIG_PINCTRL_PALMAS is not set\nCONFIG_PL310_ERRATA_588369=y\nCONFIG_PL310_ERRATA_727915=y\nCONFIG_PM=y\nCONFIG_PM_CLK=y\nCONFIG_PM_GENERIC_DOMAINS=y\nCONFIG_PM_GENERIC_DOMAINS_OF=y\nCONFIG_PM_OPP=y\nCONFIG_POSIX_MQUEUE=y\nCONFIG_POSIX_MQUEUE_SYSCTL=y\nCONFIG_POWER_AVS_OMAP=y\nCONFIG_POWER_AVS_OMAP_CLASS3=y\nCONFIG_POWER_SUPPLY=y\nCONFIG_PPS=y\nCONFIG_PRINTK_TIME=y\nCONFIG_PRINT_QUOTA_WARNING=y\nCONFIG_PROC_EVENTS=y\nCONFIG_PROFILING=y\nCONFIG_PTP_1588_CLOCK=y\nCONFIG_PWM=y\n# CONFIG_PWM_OMAP_DMTIMER is not set\nCONFIG_PWM_SYSFS=y\nCONFIG_PWM_TIECAP=y\nCONFIG_PWM_TIEHRPWM=y\n# CONFIG_PWM_TWL is not set\n# CONFIG_PWM_TWL_LED is not set\n# CONFIG_QFMT_V1 is not set\nCONFIG_QFMT_V2=y\nCONFIG_QUOTA=y\nCONFIG_QUOTACTL=y\n# CONFIG_QUOTA_NETLINK_INTERFACE is not set\nCONFIG_QUOTA_TREE=y\nCONFIG_RATIONAL=y\nCONFIG_REGMAP=y\nCONFIG_REGMAP_I2C=y\nCONFIG_REGMAP_IRQ=y\nCONFIG_REGMAP_MMIO=y\nCONFIG_REGMAP_SPI=y\nCONFIG_REGULATOR=y\nCONFIG_REGULATOR_FIXED_VOLTAGE=y\nCONFIG_REGULATOR_PALMAS=y\nCONFIG_REGULATOR_PBIAS=y\nCONFIG_REGULATOR_TI_ABB=y\nCONFIG_REGULATOR_TPS62360=y\nCONFIG_REGULATOR_TPS65023=y\nCONFIG_REGULATOR_TPS6507X=y\nCONFIG_REGULATOR_TPS65217=y\nCONFIG_REGULATOR_TPS65218=y\nCONFIG_REGULATOR_TPS65910=y\nCONFIG_REGULATOR_TWL4030=y\nCONFIG_RESET_CONTROLLER=y\nCONFIG_RFS_ACCEL=y\nCONFIG_RING_BUFFER=y\nCONFIG_RING_BUFFER_ALLOW_SWAP=y\nCONFIG_ROOT_NFS=y\nCONFIG_RPS=y\nCONFIG_RTC_CLASS=y\nCONFIG_RTC_DRV_DS1307=y\nCONFIG_RTC_DRV_OMAP=y\nCONFIG_RTC_DRV_PALMAS=y\n# CONFIG_RTC_DRV_TPS65910 is not set\nCONFIG_RTC_DRV_TWL4030=y\nCONFIG_RTC_I2C_AND_SPI=y\nCONFIG_RTC_MC146818_LIB=y\nCONFIG_RWSEM_SPIN_ON_OWNER=y\nCONFIG_SATA_AHCI_PLATFORM=y\nCONFIG_SATA_HOST=y\nCONFIG_SCHEDSTATS=y\nCONFIG_SCHED_INFO=y\nCONFIG_SCHED_MC=y\nCONFIG_SCSI=y\nCONFIG_SCSI_SCAN_ASYNC=y\nCONFIG_SDIO_UART=y\nCONFIG_SECCOMP=y\nCONFIG_SECCOMP_FILTER=y\nCONFIG_SENSORS_GPIO_FAN=y\nCONFIG_SENSORS_LM75=y\nCONFIG_SENSORS_TMP102=y\nCONFIG_SENSORS_TSL2550=y\nCONFIG_SERIAL_8250_DETECT_IRQ=y\nCONFIG_SERIAL_8250_EXTENDED=y\nCONFIG_SERIAL_8250_FSL=y\nCONFIG_SERIAL_8250_MANY_PORTS=y\nCONFIG_SERIAL_8250_NR_UARTS=32\n# CONFIG_SERIAL_8250_OMAP is not set\nCONFIG_SERIAL_8250_RSA=y\nCONFIG_SERIAL_8250_SHARE_IRQ=y\nCONFIG_SERIAL_MCTRL_GPIO=y\nCONFIG_SERIAL_OF_PLATFORM=y\nCONFIG_SERIAL_OMAP=y\nCONFIG_SERIAL_OMAP_CONSOLE=y\nCONFIG_SERIO=y\nCONFIG_SGL_ALLOC=y\nCONFIG_SG_POOL=y\nCONFIG_SG_SPLIT=y\nCONFIG_SKB_EXTENSIONS=y\nCONFIG_SMC91X=y\nCONFIG_SMP=y\nCONFIG_SMP_ON_UP=y\nCONFIG_SMSC911X=y\nCONFIG_SMSC_PHY=y\nCONFIG_SND=y\n# CONFIG_SND_COMPRESS_OFFLOAD is not set\nCONFIG_SND_DMAENGINE_PCM=y\nCONFIG_SND_JACK=y\nCONFIG_SND_PCM=y\nCONFIG_SND_PCM_OSS=y\nCONFIG_SND_SIMPLE_CARD=y\nCONFIG_SND_SIMPLE_CARD_UTILS=y\nCONFIG_SND_SOC=y\nCONFIG_SND_SOC_DAVINCI_MCASP=y\nCONFIG_SND_SOC_DMIC=y\nCONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y\nCONFIG_SND_SOC_I2C_AND_SPI=y\n# CONFIG_SND_SOC_NOKIA_RX51 is not set\n# CONFIG_SND_SOC_OMAP3_PANDORA is not set\nCONFIG_SND_SOC_OMAP3_TWL4030=y\nCONFIG_SND_SOC_OMAP_ABE_TWL6040=y\nCONFIG_SND_SOC_OMAP_DMIC=y\nCONFIG_SND_SOC_OMAP_HDMI=y\nCONFIG_SND_SOC_OMAP_MCBSP=y\nCONFIG_SND_SOC_OMAP_MCPDM=y\nCONFIG_SND_SOC_TI_EDMA_PCM=y\nCONFIG_SND_SOC_TI_SDMA_PCM=y\nCONFIG_SND_SOC_TI_UDMA_PCM=y\nCONFIG_SND_SOC_TLV320AIC3X=y\nCONFIG_SND_SOC_TWL4030=y\nCONFIG_SND_SOC_TWL6040=y\nCONFIG_SND_VERBOSE_PRINTK=y\nCONFIG_SOC_AM33XX=y\nCONFIG_SOC_AM43XX=y\nCONFIG_SOC_BUS=y\nCONFIG_SOC_HAS_OMAP2_SDRC=y\nCONFIG_SOC_OMAP3430=y\n# CONFIG_SOC_TI81XX is not set\nCONFIG_SOUND=y\nCONFIG_SOUND_OSS_CORE=y\nCONFIG_SOUND_OSS_CORE_PRECLAIM=y\nCONFIG_SPARSE_IRQ=y\nCONFIG_SPI=y\nCONFIG_SPI_MASTER=y\nCONFIG_SPI_MEM=y\nCONFIG_SPI_OMAP24XX=y\nCONFIG_SPI_TI_QSPI=y\nCONFIG_SRAM=y\nCONFIG_SRAM_EXEC=y\nCONFIG_SRCU=y\nCONFIG_STACKTRACE=y\nCONFIG_SUNRPC=y\nCONFIG_SUNRPC_GSS=y\nCONFIG_SWPHY=y\nCONFIG_SWP_EMULATE=y\nCONFIG_SYNC_FILE=y\nCONFIG_SYS_SUPPORTS_APM_EMULATION=y\nCONFIG_THERMAL=y\nCONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y\nCONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0\nCONFIG_THERMAL_GOV_FAIR_SHARE=y\nCONFIG_THERMAL_GOV_STEP_WISE=y\nCONFIG_THERMAL_GOV_USER_SPACE=y\nCONFIG_THERMAL_OF=y\nCONFIG_TICK_CPU_ACCOUNTING=y\nCONFIG_TIMER_OF=y\nCONFIG_TIMER_PROBE=y\nCONFIG_TI_CPPI41=y\nCONFIG_TI_CPSW=y\nCONFIG_TI_CPSW_PHY_SEL=y\nCONFIG_TI_CPTS=y\nCONFIG_TI_DAVINCI_EMAC=y\nCONFIG_TI_DAVINCI_MDIO=y\nCONFIG_TI_DMA_CROSSBAR=y\nCONFIG_TI_EDMA=y\nCONFIG_TI_EMIF=y\n# CONFIG_TI_EMIF_SRAM is not set\nCONFIG_TI_PIPE3=y\nCONFIG_TI_PRUSS_INTC=y\nCONFIG_TI_PWMSS=y\nCONFIG_TI_SOC_THERMAL=y\nCONFIG_TI_SYSC=y\nCONFIG_TI_THERMAL=y\nCONFIG_TMPFS_POSIX_ACL=y\nCONFIG_TRACE_CLOCK=y\nCONFIG_TREE_RCU=y\nCONFIG_TREE_SRCU=y\nCONFIG_TWL4030_CORE=y\nCONFIG_TWL4030_POWER=y\nCONFIG_TWL4030_USB=y\nCONFIG_TWL4030_WATCHDOG=y\n# CONFIG_TWL6030_USB is not set\nCONFIG_TWL6040_CORE=y\nCONFIG_UBIFS_FS=y\nCONFIG_UNCOMPRESS_INCLUDE=\"debug/uncompress.h\"\nCONFIG_UNWINDER_ARM=y\nCONFIG_USB=y\n# CONFIG_USB_AUDIO is not set\nCONFIG_USB_COMMON=y\nCONFIG_USB_DWC3=y\nCONFIG_USB_DWC3_DUAL_ROLE=y\n# CONFIG_USB_DWC3_GADGET is not set\n# CONFIG_USB_DWC3_HOST is not set\nCONFIG_USB_DWC3_OMAP=y\nCONFIG_USB_EHCI_HCD=y\nCONFIG_USB_EHCI_HCD_OMAP=y\n# CONFIG_USB_EHCI_HCD_PLATFORM is not set\n# CONFIG_USB_ETH is not set\nCONFIG_USB_GADGET=y\nCONFIG_USB_INVENTRA_DMA=y\nCONFIG_USB_MUSB_AM35X=y\nCONFIG_USB_MUSB_DSPS=y\nCONFIG_USB_MUSB_DUAL_ROLE=y\n# CONFIG_USB_MUSB_GADGET is not set\nCONFIG_USB_MUSB_HDRC=y\n# CONFIG_USB_MUSB_HOST is not set\nCONFIG_USB_MUSB_OMAP2PLUS=y\nCONFIG_USB_MUSB_TUSB6010=y\nCONFIG_USB_PHY=y\nCONFIG_USB_ROLE_SWITCH=y\nCONFIG_USB_SUPPORT=y\nCONFIG_USB_TI_CPPI41_DMA=y\nCONFIG_USB_TUSB_OMAP_DMA=y\nCONFIG_USE_OF=y\nCONFIG_VFAT_FS=y\nCONFIG_VFP=y\nCONFIG_VFPv3=y\nCONFIG_VIDEOMODE_HELPERS=y\nCONFIG_WATCHDOG_CORE=y\nCONFIG_XFRM_ALGO=y\nCONFIG_XFRM_MIGRATE=y\nCONFIG_XPS=y\nCONFIG_XXHASH=y\nCONFIG_XZ_DEC_ARM=y\nCONFIG_XZ_DEC_BCJ=y\nCONFIG_ZBOOT_ROM_BSS=0x0\nCONFIG_ZBOOT_ROM_TEXT=0x0\nCONFIG_ZLIB_DEFLATE=y\nCONFIG_ZLIB_INFLATE=y\nCONFIG_ZSTD_COMPRESS=y\nCONFIG_ZSTD_DECOMPRESS=y\n"
  },
  {
    "path": "target/linux/omap/image/Config.in",
    "content": "config OMAP_SD_BOOT_PARTSIZE\n\tint \"Boot (SD Card) filesystem partition size (in MB)\"\n\tdepends on TARGET_omap\n\tdefault 20\n\n"
  },
  {
    "path": "target/linux/omap/image/Makefile",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2012-2014 OpenWrt.org\n\ninclude $(TOPDIR)/rules.mk\ninclude $(INCLUDE_DIR)/image.mk\n\nFAT32_BLOCK_SIZE=1024\nFAT32_BLOCKS=$(shell echo $$(($(CONFIG_OMAP_SD_BOOT_PARTSIZE)*1024*1024/$(FAT32_BLOCK_SIZE))))\n\nUBIFS_OPTS = -F -m 2048 -e 124KiB -c 4096 -U\nUBI_OPTS = -m 2048 -p 128KiB -s 512 -O 2048\n\ndefine Build/omap-sdcard\n\trm -f $@.boot\n\tmkfs.fat $@.boot -C $(FAT32_BLOCKS)\n\n\tmcopy -i $@.boot $(STAGING_DIR_IMAGE)/$(DEVICE_NAME)/MLO ::MLO\n\tmcopy -i $@.boot $(STAGING_DIR_IMAGE)/$(DEVICE_NAME)/u-boot.img ::u-boot.img\n\tmcopy -i $@.boot $(STAGING_DIR_IMAGE)/$(DEVICE_NAME)/boot.scr ::boot.scr\n\tmmd -i $@.boot ::/dtbs\n\tmcopy -i $@.boot $(DTS_DIR)/$(DEVICE_DTS).dtb ::/dtbs/$(DEVICE_DTS).dtb\n\tmcopy -i $@.boot $(IMAGE_KERNEL) ::/zImage\n\t./gen_omap_sdcard_img.sh $@ \\\n\t\t$@.boot \\\n\t\t$(IMAGE_ROOTFS) \\\n\t\t$(CONFIG_OMAP_SD_BOOT_PARTSIZE) \\\n\t\t$(CONFIG_TARGET_ROOTFS_PARTSIZE)\n\trm -f $@.boot\nendef\n\ndefine Device/Default\n  PROFILES := Default\n  KERNEL_NAME := zImage\n  KERNEL := kernel-bin\n  DEVICE_DTS = $(lastword $(subst _, ,$(1)))\n  IMAGES := sdcard.img.gz\n  IMAGE/sdcard.img.gz := omap-sdcard | append-metadata | gzip\nendef\n\n#uboot-omap-am335x_evm uboot-omap-omap3_beagle uboot-omap-omap4_panda\n\ndefine Device/ti_am335x-evm\n  DEVICE_VENDOR := Texas Instruments\n  DEVICE_MODEL := AM335x EVM\nendef\n\nTARGET_DEVICES += ti_am335x-evm\n\ndefine Device/ti_am335x-bone-black\n  DEVICE_VENDOR := Texas Instruments\n  DEVICE_MODEL := AM335x BeagleBone Black\n  DEVICE_DTS := am335x-boneblack\nendef\n\nTARGET_DEVICES += ti_am335x-bone-black\n\ndefine Device/ti_omap4-panda\n  DEVICE_VENDOR := PandaBoard.org\n  DEVICE_MODEL := OMAP4 TI pandaboard\n  DEVICE_PACKAGES := kmod-usb-net-smsc95xx\nendef\n\nTARGET_DEVICES += ti_omap4-panda\n\ndefine Device/ti_omap3-beagle\n  DEVICE_VENDOR := BeagleBoard.org\n  DEVICE_MODEL := OMAP3 TI beagleboard\n  # beagleboard doesn't have a network interface, support most common usb net\n  DEVICE_PACKAGES := \\\n\tkmod-usb-net-asix kmod-usb-net-asix-ax88179 kmod-usb-net-hso \\\n\tkmod-usb-net-kaweth kmod-usb-net-pegasus kmod-usb-net-mcs7830 \\\n\tkmod-usb-net-smsc95xx kmod-usb-net-dm9601-ether\nendef\n\nTARGET_DEVICES += ti_omap3-beagle\n\n$(eval $(call BuildImage))\n"
  },
  {
    "path": "target/linux/omap/image/gen_omap_sdcard_img.sh",
    "content": "#!/bin/sh\n# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2013 OpenWrt.org\n\nset -x\n[ $# -eq 5 ] || {\n    echo \"SYNTAX: $0 <file> <bootfs image> <rootfs image> <bootfs size> <rootfs size>\"\n    exit 1\n}\n\nOUTPUT=\"$1\"\nBOOTFS=\"$2\"\nROOTFS=\"$3\"\nBOOTFSSIZE=\"$4\"\nROOTFSSIZE=\"$5\"\n\nhead=4\nsect=63\n\nset $(ptgen -o $OUTPUT -h $head -s $sect -l 1024 -t c -p ${BOOTFSSIZE}M -t 83 -p ${ROOTFSSIZE}M)\n\nBOOTOFFSET=\"$(($1 / 512))\"\nBOOTSIZE=\"$(($2 / 512))\"\nROOTFSOFFSET=\"$(($3 / 512))\"\nROOTFSSIZE=\"$(($4 / 512))\"\n\ndd bs=512 if=\"$BOOTFS\" of=\"$OUTPUT\" seek=\"$BOOTOFFSET\" conv=notrunc\ndd bs=512 if=\"$ROOTFS\" of=\"$OUTPUT\" seek=\"$ROOTFSOFFSET\" conv=notrunc\n"
  },
  {
    "path": "target/linux/omap/image/ubinize.cfg",
    "content": "[rootfs]\n# Volume mode (other option is static)\nmode=ubi\n# Source image\nimage=root.ubifs\n# Volume ID in UBI image\nvol_id=0\n# Allow for dynamic resize\nvol_type=dynamic\n# Volume name\nvol_name=rootfs\n# Autoresize volume at first mount\nvol_flags=autoresize\n\n"
  },
  {
    "path": "target/linux/omap/profiles/00-default.mk",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2013 OpenWrt.org\n\ndefine Profile/Default\n  NAME:=Default Profile\n  PACKAGES:= \\\n\tkmod-usb-net-asix kmod-usb-net-asix-ax88179 kmod-usb-net-hso \\\n\tkmod-usb-net-kaweth kmod-usb-net-pegasus kmod-usb-net-mcs7830 \\\n\tkmod-usb-net-smsc95xx kmod-usb-net-dm9601-ether \\\n\twpad-basic-wolfssl\n  PRIORITY := 1\nendef\n\ndefine Profile/Default/Description\n\tDefault package set compatible with most boards.\nendef\n\n$(eval $(call Profile,Default))\n"
  },
  {
    "path": "target/linux/oxnas/Makefile",
    "content": "include $(TOPDIR)/rules.mk\n\nARCH:=arm\nBOARD:=oxnas\nBOARDNAME:=PLXTECH/Oxford NAS782x/OX8xx\nSUBTARGETS:=ox810se ox820\nFEATURES:=gpio ramdisk rtc squashfs\nDEVICE_TYPE:=nas\n\nKERNEL_PATCHVER:=5.10\n\ninclude $(INCLUDE_DIR)/target.mk\n\nDEFAULT_PACKAGES += \\\n\tkmod-button-hotplug kmod-input-gpio-keys-polled \\\n\tkmod-leds-gpio uboot-envtools\n\nKERNELNAME:=zImage dtbs\n\n$(eval $(call BuildTarget))\n"
  },
  {
    "path": "target/linux/oxnas/base-files/etc/board.d/02_network",
    "content": "\n. /lib/functions/uci-defaults.sh\n. /lib/functions/system.sh\n\nbootloader_cmdline_var() {\n\tlocal param\n\tlocal pval\n\tfor arg in $(cat /proc/device-tree/chosen/bootloader-args); do\n\t\tparam=\"$(echo $arg | cut -d'=' -f 1)\"\n\t\tpval=\"$(echo $arg | cut -d'=' -f 2-)\"\n\n\t\tif [ \"$param\" = \"$1\" ]; then\n\t\t\techo \"$pval\"\n\t\tfi\n\tdone\n}\n\nlegacy_boot_mac_adr() {\n\tlocal macstr\n\tlocal oIFS\n\tmacstr=\"$(bootloader_cmdline_var mac_adr)\"\n\toIFS=\"$IFS\"\n\tIFS=\",\"\n\tset -- $macstr\n\tprintf \"%02x:%02x:%02x:%02x:%02x:%02x\" $1 $2 $3 $4 $5 $6\n\tIFS=\"$oIFS\"\n}\n\noxnas_setup_interfaces()\n{\n\tlocal board=\"$1\"\n\n\tcase $board in\n\t*)\n\t\tucidef_set_interface_lan \"eth0\" \"dhcp\"\n\t\t;;\n\tesac\n}\n\noxnas_setup_macs()\n{\n\tlocal board=\"$1\"\n\tlocal lan_mac=\"\"\n\n\tcase $board in\n\tshuttle,kd20)\n\t\tlan_mac=\"$(legacy_boot_mac_adr)\"\n\t\t;;\n\tesac\n\n\t[ -n \"$lan_mac\" ] && ucidef_set_interface_macaddr \"lan\" $lan_mac\n}\n\nboard_config_update\nboard=$(board_name)\noxnas_setup_interfaces $board\noxnas_setup_macs $board\nboard_config_flush\n\nexit 0\n"
  },
  {
    "path": "target/linux/oxnas/base-files/etc/init.d/set-irq-affinity",
    "content": "#!/bin/sh /etc/rc.common\n\nSTART=99\n\nget_irq() {\n\tlocal name=\"$1\"\n\tgrep -m 1 \"$name\" /proc/interrupts | cut -d: -f1 | sed 's, *,,'\n}\n\nset_irq_affinity() {\n\tlocal name=\"$1\"\n\tlocal val=\"$2\"\n\tlocal irq=\"$(get_irq \"$name\")\"\n\t[ -n \"$irq\" ] || return\n\techo \"$val\" > \"/proc/irq/$irq/smp_affinity\"\n}\n\nstart() {\n\tset_irq_affinity ehci_hcd 2\n\tset_irq_affinity xhci_hcd 2\n\tset_irq_affinity sata 2\n}\n"
  },
  {
    "path": "target/linux/oxnas/base-files/lib/upgrade/platform.sh",
    "content": "REQUIRE_IMAGE_METADATA=1\n\nplatform_check_image() {\n\treturn 0\n}\n\nplatform_do_upgrade() {\n\tnand_do_upgrade $1\n}\n"
  },
  {
    "path": "target/linux/oxnas/config-5.10",
    "content": "CONFIG_ALIGNMENT_TRAP=y\nCONFIG_ARCH_32BIT_OFF_T=y\nCONFIG_ARCH_CLOCKSOURCE_DATA=y\nCONFIG_ARCH_HAS_BINFMT_FLAT=y\nCONFIG_ARCH_HAS_DEBUG_VIRTUAL=y\nCONFIG_ARCH_HAS_DMA_WRITE_COMBINE=y\nCONFIG_ARCH_HAS_ELF_RANDOMIZE=y\nCONFIG_ARCH_HAS_FORTIFY_SOURCE=y\nCONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y\nCONFIG_ARCH_HAS_KCOV=y\nCONFIG_ARCH_HAS_KEEPINITRD=y\nCONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y\nCONFIG_ARCH_HAS_PHYS_TO_DMA=y\nCONFIG_ARCH_HAS_RESET_CONTROLLER=y\nCONFIG_ARCH_HAS_SETUP_DMA_OPS=y\nCONFIG_ARCH_HAS_SET_MEMORY=y\nCONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y\nCONFIG_ARCH_HAS_STRICT_MODULE_RWX=y\nCONFIG_ARCH_HAS_TEARDOWN_DMA_OPS=y\nCONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y\nCONFIG_ARCH_HIBERNATION_POSSIBLE=y\nCONFIG_ARCH_KEEP_MEMBLOCK=y\nCONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y\nCONFIG_ARCH_MULTIPLATFORM=y\nCONFIG_ARCH_MULTI_CPU_AUTO=y\n# CONFIG_ARCH_MULTI_V4 is not set\n# CONFIG_ARCH_MULTI_V4T is not set\nCONFIG_ARCH_MULTI_V4_V5=y\nCONFIG_ARCH_MULTI_V5=y\nCONFIG_ARCH_NR_GPIO=0\nCONFIG_ARCH_OPTIONAL_KERNEL_RWX=y\nCONFIG_ARCH_OXNAS=y\nCONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y\nCONFIG_ARCH_SUPPORTS_UPROBES=y\nCONFIG_ARCH_SUSPEND_POSSIBLE=y\nCONFIG_ARCH_USE_BUILTIN_BSWAP=y\nCONFIG_ARCH_USE_CMPXCHG_LOCKREF=y\nCONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y\nCONFIG_ARCH_WANT_GENERAL_HUGETLB=y\nCONFIG_ARCH_WANT_IPC_PARSE_VERSION=y\nCONFIG_ARCH_WANT_LIBATA_LEDS=y\nCONFIG_ARM=y\nCONFIG_ARM_APPENDED_DTB=y\nCONFIG_ARM_ATAG_DTB_COMPAT=y\n# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set\n# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER is not set\nCONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE=y\nCONFIG_ARM_CPU_SUSPEND=y\nCONFIG_ARM_HAS_SG_CHAIN=y\nCONFIG_ARM_L1_CACHE_SHIFT=5\nCONFIG_ARM_PATCH_PHYS_VIRT=y\nCONFIG_ARM_PMU=y\n# CONFIG_ARM_SMMU is not set\nCONFIG_ARM_THUMB=y\nCONFIG_ARM_UNWIND=y\nCONFIG_ATAGS=y\nCONFIG_AUTO_ZRELADDR=y\nCONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y\nCONFIG_BLK_CMDLINE_PARSER=y\nCONFIG_BLK_DEBUG_FS=y\nCONFIG_BLK_DEV_BSG=y\nCONFIG_BLK_DEV_LOOP=y\nCONFIG_BLK_DEV_RAM=y\nCONFIG_BLK_DEV_RAM_COUNT=16\nCONFIG_BLK_DEV_RAM_SIZE=65536\nCONFIG_BLK_PM=y\nCONFIG_BLK_SCSI_REQUEST=y\nCONFIG_CC_HAS_KASAN_GENERIC=y\nCONFIG_CLKDEV_LOOKUP=y\nCONFIG_CLKSRC_MMIO=y\nCONFIG_CLONE_BACKWARDS=y\nCONFIG_CMA=y\nCONFIG_CMA_ALIGNMENT=8\nCONFIG_CMA_AREAS=7\n# CONFIG_CMA_DEBUG is not set\n# CONFIG_CMA_DEBUGFS is not set\nCONFIG_CMA_SIZE_MBYTES=64\n# CONFIG_CMA_SIZE_SEL_MAX is not set\nCONFIG_CMA_SIZE_SEL_MBYTES=y\n# CONFIG_CMA_SIZE_SEL_MIN is not set\n# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set\nCONFIG_CMDLINE_PARTITION=y\nCONFIG_COMMON_CLK=y\nCONFIG_COMMON_CLK_OXNAS=y\nCONFIG_COMPAT_32BIT_TIME=y\nCONFIG_CONTIG_ALLOC=y\nCONFIG_COREDUMP=y\nCONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y\nCONFIG_CPU_32v5=y\nCONFIG_CPU_ABRT_EV5TJ=y\nCONFIG_CPU_ARM926T=y\n# CONFIG_CPU_CACHE_ROUND_ROBIN is not set\nCONFIG_CPU_CACHE_VIVT=y\nCONFIG_CPU_COPY_V4WB=y\nCONFIG_CPU_CP15=y\nCONFIG_CPU_CP15_MMU=y\n# CONFIG_CPU_DCACHE_WRITETHROUGH is not set\n# CONFIG_CPU_ICACHE_DISABLE is not set\nCONFIG_CPU_PABRT_LEGACY=y\nCONFIG_CPU_PM=y\nCONFIG_CPU_THUMB_CAPABLE=y\nCONFIG_CPU_TLB_V4WBI=y\nCONFIG_CPU_USE_DOMAINS=y\nCONFIG_CRASH_CORE=y\nCONFIG_CRC16=y\n# CONFIG_CRC32_SARWATE is not set\nCONFIG_CRC32_SLICEBY8=y\nCONFIG_CROSS_MEMORY_ATTACH=y\nCONFIG_CRYPTO_RNG2=y\nCONFIG_DEBUG_ALIGN_RODATA=y\nCONFIG_DEBUG_BUGVERBOSE=y\nCONFIG_DEBUG_LL_INCLUDE=\"mach/debug-macro.S\"\n# CONFIG_DEBUG_USER is not set\nCONFIG_DECOMPRESS_BZIP2=y\nCONFIG_DECOMPRESS_GZIP=y\nCONFIG_DECOMPRESS_LZ4=y\nCONFIG_DECOMPRESS_LZMA=y\nCONFIG_DECOMPRESS_LZO=y\nCONFIG_DECOMPRESS_XZ=y\nCONFIG_DMA_CMA=y\nCONFIG_DMA_REMAP=y\nCONFIG_DNOTIFY=y\nCONFIG_DTC=y\n# CONFIG_DWMAC_DWC_QOS_ETH is not set\nCONFIG_DWMAC_GENERIC=y\nCONFIG_DWMAC_OXNAS=y\nCONFIG_EDAC_ATOMIC_SCRUB=y\nCONFIG_EDAC_SUPPORT=y\nCONFIG_ELF_CORE=y\nCONFIG_FAT_FS=y\nCONFIG_FIXED_PHY=y\nCONFIG_FIX_EARLYCON_MEM=y\nCONFIG_FREEZER=y\n# CONFIG_FW_CACHE is not set\nCONFIG_FW_LOADER_PAGED_BUF=y\nCONFIG_GENERIC_ALLOCATOR=y\nCONFIG_GENERIC_ATOMIC64=y\nCONFIG_GENERIC_BUG=y\nCONFIG_GENERIC_CLOCKEVENTS=y\nCONFIG_GENERIC_CPU_AUTOPROBE=y\nCONFIG_GENERIC_EARLY_IOREMAP=y\nCONFIG_GENERIC_IDLE_POLL_SETUP=y\nCONFIG_GENERIC_IRQ_MULTI_HANDLER=y\nCONFIG_GENERIC_IRQ_SHOW=y\nCONFIG_GENERIC_IRQ_SHOW_LEVEL=y\nCONFIG_GENERIC_PCI_IOMAP=y\nCONFIG_GENERIC_PHY=y\nCONFIG_GENERIC_PINCONF=y\nCONFIG_GENERIC_SCHED_CLOCK=y\nCONFIG_GENERIC_SMP_IDLE_THREAD=y\nCONFIG_GENERIC_STRNCPY_FROM_USER=y\nCONFIG_GENERIC_STRNLEN_USER=y\nCONFIG_GPIOLIB=y\nCONFIG_GPIOLIB_IRQCHIP=y\nCONFIG_GPIO_GENERIC=y\nCONFIG_GPIO_GENERIC_PLATFORM=y\nCONFIG_HANDLE_DOMAIN_IRQ=y\nCONFIG_HARDIRQS_SW_RESEND=y\nCONFIG_HAS_DMA=y\nCONFIG_HAS_IOMEM=y\nCONFIG_HAS_IOPORT_MAP=y\nCONFIG_HAVE_ARCH_AUDITSYSCALL=y\nCONFIG_HAVE_ARCH_JUMP_LABEL=y\nCONFIG_HAVE_ARCH_KGDB=y\nCONFIG_HAVE_ARCH_PFN_VALID=y\nCONFIG_HAVE_ARCH_SECCOMP_FILTER=y\nCONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y\nCONFIG_HAVE_ARCH_TRACEHOOK=y\nCONFIG_HAVE_CLK=y\nCONFIG_HAVE_CLK_PREPARE=y\nCONFIG_HAVE_CONTEXT_TRACKING=y\nCONFIG_HAVE_COPY_THREAD_TLS=y\nCONFIG_HAVE_C_RECORDMCOUNT=y\nCONFIG_HAVE_DEBUG_KMEMLEAK=y\nCONFIG_HAVE_DMA_CONTIGUOUS=y\nCONFIG_HAVE_DYNAMIC_FTRACE=y\nCONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y\nCONFIG_HAVE_EBPF_JIT=y\nCONFIG_HAVE_FTRACE_MCOUNT_RECORD=y\nCONFIG_HAVE_FUNCTION_GRAPH_TRACER=y\nCONFIG_HAVE_FUNCTION_TRACER=y\nCONFIG_HAVE_IRQ_TIME_ACCOUNTING=y\nCONFIG_HAVE_LD_DEAD_CODE_DATA_ELIMINATION=y\nCONFIG_HAVE_MOD_ARCH_SPECIFIC=y\nCONFIG_HAVE_NET_DSA=y\nCONFIG_HAVE_OPROFILE=y\nCONFIG_HAVE_OPTPROBES=y\nCONFIG_HAVE_PCI=y\nCONFIG_HAVE_PERF_EVENTS=y\nCONFIG_HAVE_PERF_REGS=y\nCONFIG_HAVE_PERF_USER_STACK_DUMP=y\nCONFIG_HAVE_PROC_CPU=y\nCONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y\nCONFIG_HAVE_RSEQ=y\nCONFIG_HAVE_SYSCALL_TRACEPOINTS=y\nCONFIG_HAVE_UID16=y\nCONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y\nCONFIG_HID=y\nCONFIG_HID_GENERIC=y\nCONFIG_HWMON=y\nCONFIG_HZ_FIXED=0\nCONFIG_ICPLUS_PHY=y\nCONFIG_INET_DIAG=y\n# CONFIG_INET_DIAG_DESTROY is not set\n# CONFIG_INET_RAW_DIAG is not set\nCONFIG_INET_TCP_DIAG=y\nCONFIG_INITRAMFS_SOURCE=\"\"\nCONFIG_INPUT=y\n# CONFIG_IOMMU_DEBUGFS is not set\n# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set\n# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set\nCONFIG_IOMMU_SUPPORT=y\nCONFIG_IRQCHIP=y\nCONFIG_IRQ_DOMAIN=y\nCONFIG_IRQ_FORCED_THREADING=y\nCONFIG_IRQ_WORK=y\n# CONFIG_ISDN is not set\n# CONFIG_JFFS2_FS is not set\nCONFIG_KALLSYMS=y\nCONFIG_KERNEL_GZIP=y\n# CONFIG_KERNEL_XZ is not set\nCONFIG_KEXEC=y\nCONFIG_KEXEC_CORE=y\n# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set\nCONFIG_LEDS_GPIO=y\nCONFIG_LEDS_TRIGGER_CPU=y\nCONFIG_LEDS_TRIGGER_GPIO=y\nCONFIG_LEDS_TRIGGER_ONESHOT=y\nCONFIG_LIBFDT=y\nCONFIG_LOCALVERSION_AUTO=y\nCONFIG_LOCK_DEBUGGING_SUPPORT=y\nCONFIG_LZ4_DECOMPRESS=y\nCONFIG_LZO_DECOMPRESS=y\n# CONFIG_MACH_OX810SE is not set\nCONFIG_MDIO_BUS=y\nCONFIG_MDIO_DEVICE=y\nCONFIG_MEMFD_CREATE=y\nCONFIG_MEMORY_ISOLATION=y\nCONFIG_MFD_SYSCON=y\nCONFIG_MIGRATION=y\nCONFIG_MODULES_TREE_LOOKUP=y\nCONFIG_MODULES_USE_ELF_REL=y\nCONFIG_NEED_DMA_MAP_STATE=y\nCONFIG_NEED_KUSER_HELPERS=y\nCONFIG_NEED_PER_CPU_KM=y\nCONFIG_NET_PTP_CLASSIFY=y\nCONFIG_NLS=y\nCONFIG_NO_HZ=y\nCONFIG_NO_HZ_COMMON=y\nCONFIG_NO_HZ_IDLE=y\nCONFIG_OF=y\nCONFIG_OF_ADDRESS=y\nCONFIG_OF_EARLY_FLATTREE=y\nCONFIG_OF_FLATTREE=y\nCONFIG_OF_GPIO=y\nCONFIG_OF_IRQ=y\nCONFIG_OF_KOBJ=y\nCONFIG_OF_MDIO=y\nCONFIG_OF_NET=y\nCONFIG_OLD_SIGACTION=y\nCONFIG_OLD_SIGSUSPEND3=y\nCONFIG_OXNAS_RPS_TIMER=y\nCONFIG_PAGE_OFFSET=0xC0000000\nCONFIG_PAGE_POOL=y\n# CONFIG_PANIC_ON_OOPS is not set\nCONFIG_PANIC_ON_OOPS_VALUE=0\nCONFIG_PANIC_TIMEOUT=0\nCONFIG_PERF_USE_VMALLOC=y\nCONFIG_PGTABLE_LEVELS=2\nCONFIG_PHYLIB=y\nCONFIG_PHYLINK=y\nCONFIG_PHY_OXNAS=y\nCONFIG_PINCTRL=y\nCONFIG_PINCTRL_OXNAS=y\n# CONFIG_PINCTRL_SINGLE is not set\nCONFIG_PM=y\nCONFIG_PM_CLK=y\n# CONFIG_PM_DEBUG is not set\nCONFIG_PM_SLEEP=y\nCONFIG_POWER_RESET=y\nCONFIG_POWER_RESET_OXNAS=y\nCONFIG_PPS=y\nCONFIG_PTP_1588_CLOCK=y\nCONFIG_RAS=y\nCONFIG_RATIONAL=y\nCONFIG_RCU_TRACE=y\nCONFIG_RD_BZIP2=y\nCONFIG_RD_GZIP=y\nCONFIG_RD_LZ4=y\nCONFIG_RD_LZMA=y\nCONFIG_RD_LZO=y\nCONFIG_RD_XZ=y\nCONFIG_REALTEK_PHY=y\nCONFIG_REFCOUNT_FULL=y\nCONFIG_REGMAP=y\nCONFIG_REGMAP_MMIO=y\nCONFIG_RESET_CONTROLLER=y\nCONFIG_RESET_OXNAS=y\nCONFIG_SCHED_DEBUG=y\nCONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y\nCONFIG_SERIAL_8250_FSL=y\nCONFIG_SERIAL_8250_NR_UARTS=4\nCONFIG_SERIAL_8250_RUNTIME_UARTS=4\nCONFIG_SERIAL_MCTRL_GPIO=y\nCONFIG_SERIAL_OF_PLATFORM=y\nCONFIG_SERIO=y\nCONFIG_SERIO_LIBPS2=y\nCONFIG_SERIO_SERPORT=y\nCONFIG_SIMPLE_PM_BUS=y\nCONFIG_SLUB_DEBUG=y\nCONFIG_SOCK_DIAG=y\nCONFIG_SPARSE_IRQ=y\nCONFIG_SPLIT_PTLOCK_CPUS=999999\nCONFIG_SRCU=y\nCONFIG_STACKTRACE=y\nCONFIG_STMMAC_ETH=y\nCONFIG_STMMAC_PLATFORM=y\n# CONFIG_STMMAC_SELFTESTS is not set\n# CONFIG_STRIP_ASM_SYMS is not set\nCONFIG_SUSPEND=y\nCONFIG_SUSPEND_FREEZER=y\nCONFIG_SWPHY=y\nCONFIG_SYS_SUPPORTS_APM_EMULATION=y\nCONFIG_THERMAL=y\nCONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y\nCONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0\nCONFIG_THERMAL_GOV_STEP_WISE=y\nCONFIG_THERMAL_HWMON=y\nCONFIG_THERMAL_OF=y\nCONFIG_TICK_CPU_ACCOUNTING=y\nCONFIG_TIMER_OF=y\nCONFIG_TIMER_PROBE=y\nCONFIG_TINY_SRCU=y\nCONFIG_TRACE_CLOCK=y\nCONFIG_UEVENT_HELPER_PATH=\"\"\nCONFIG_UNCOMPRESS_INCLUDE=\"debug/uncompress.h\"\nCONFIG_UNWINDER_ARM=y\n# CONFIG_UNWINDER_FRAME_POINTER is not set\nCONFIG_USB_SUPPORT=y\nCONFIG_USE_OF=y\nCONFIG_VERSATILE_FPGA_IRQ=y\nCONFIG_VERSATILE_FPGA_IRQ_NR=4\nCONFIG_VFAT_FS=y\n# CONFIG_VFP is not set\nCONFIG_VM_EVENT_COUNTERS=y\n# CONFIG_WATCHDOG is not set\n# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set\nCONFIG_XZ_DEC_ARM=y\nCONFIG_XZ_DEC_BCJ=y\nCONFIG_XZ_DEC_IA64=y\nCONFIG_XZ_DEC_POWERPC=y\nCONFIG_XZ_DEC_SPARC=y\nCONFIG_XZ_DEC_X86=y\nCONFIG_ZBOOT_ROM_BSS=0\nCONFIG_ZBOOT_ROM_TEXT=0\nCONFIG_ZLIB_INFLATE=y\n"
  },
  {
    "path": "target/linux/oxnas/files/arch/arm/boot/dts/ox820-akitio-mycloud.dts",
    "content": "/dts-v1/;\n\n#include \"ox820.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"Akitio MyCloud\";\n\n\tcompatible = \"akitio,mycloud\", \"oxsemi,ox820\";\n\n\tchosen {\n\t\tbootargs = \"earlyprintk console=ttyS0,115200\";\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\tmemory {\n\t\t/* 128Mbytes DDR */\n\t\treg = <0x60000000 0x8000000>;\n\t};\n\n\taliases {\n\t\tserial0 = &uart0;\n\t\tgpio0 = &gpio0;\n\t\tgpio1 = &gpio1;\n\t\tled-boot = &led_status;\n\t\tled-failsafe = &led_status;\n\t\tled-running = &led_status;\n\t\tled-upgrade = &led_status;\n\t};\n\n\ti2c-gpio {\n\t\tcompatible = \"i2c-gpio\";\n\t\tgpios = <&gpio1  9 GPIO_ACTIVE_HIGH\n\t\t         &gpio1 10 GPIO_ACTIVE_HIGH>;\n\t\tpinctrl-names = \"default\";\n\t\tpinctrl-0 = <&pinctrl_i2c>;\n\t\ti2c-gpio,delay-us = <10>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tds1307: rtc@68 {\n\t\t\tcompatible = \"dallas,ds1307\";\n\t\t\treg = <0x68>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpinctrl-names = \"default\";\n\t\tpinctrl-0 = <&pinctrl_buttons>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tpoll-interval = <100>;\n\t\tpower {\n\t\t\tlabel = \"power\";\n\t\t\tgpios = <&gpio0 11 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_POWER>;\n\t\t};\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio1 6 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tpinctrl-names = \"default\";\n\t\tpinctrl-0 = <&pinctrl_leds>;\n\t\tled_status: status {\n\t\t\tlabel = \"akitio:red:status\";\n\t\t\tgpios = <&gpio0 29 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n\n\tgpio-poweroff {\n\t\tcompatible = \"gpio-poweroff\";\n\t\tpinctrl-names = \"default\";\n\t\tpinctrl-0 = <&pinctrl_poweroff>;\n\t\tgpios = <&gpio1 13 GPIO_SINGLE_ENDED>;\n\t};\n};\n\n&pinctrl {\n\tpinctrl_i2c: i2c-0 {\n\t\ti2c {\n\t\t\tpins = \"gpio41\", \"gpio42\"; /* MF_B9, MF_B10 */\n\t\t\tfunction = \"gpio\";\n\t\t\t/* ToDo: find a way to set debounce for those pins */\n\t\t};\n\t};\n\tpinctrl_buttons: buttons-0 {\n\t\tbuttons {\n\t\t\tpins = \"gpio11\", \"gpio38\"; /* MF_A11, MF_B6 GPIO */\n\t\t\tfunction = \"gpio\";\n\t\t};\n\t};\n\tpinctrl_leds: leds-0 {\n\t\tleds {\n\t\t\tpins = \"gpio29\"; /* MF_A29 GPIO */\n\t\t\tfunction = \"gpio\";\n\t\t};\n\t};\n\tpinctrl_poweroff: poweroff-0 {\n\t\tpoweroff {\n\t\t\tpins = \"gpio45\"; /* MF_B13 GPIO */\n\t\t\tfunction = \"gpio\";\n\t\t};\n\t};\n};\n\n&uart0 {\n\tstatus = \"okay\";\n\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0>;\n};\n\n&nandc {\n\tstatus = \"okay\";\n\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_nand>;\n\n\tnand@0 {\n\t\treg = <0>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tnand-ecc-mode = \"soft\";\n\t\tnand-ecc-algo = \"hamming\";\n\n\t\tpartition@0 {\n\t\t\tlabel = \"boot\";\n\t\t\treg = <0x0 0x26c0000>;\n\t\t};\n\n\t\tpartition@26c0000 {\n\t\t\tlabel = \"ubi\";\n\t\t\treg = <0x26c0000 0xd940000>;\n\t\t};\n\t};\n};\n\n&etha {\n\tstatus = \"okay\";\n\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_etha_mdio>;\n};\n\n&ehci {\n\tstatus = \"okay\";\n};\n\n&sata {\n\tstatus = \"okay\";\n\tnr-ports = <2>;\n};\n\n&pcie_phy {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/oxnas/files/arch/arm/boot/dts/ox820-cloudengines-pogoplugpro.dts",
    "content": "/*\n * cloudengines-pogoplug-series-3.dtsi - Device tree file for Cloud Engines PogoPlug Series 3\n *\n * Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com>\n *\n * Licensed under GPLv2 or later\n */\n\n/dts-v1/;\n#include \"ox820.dtsi\"\n#include <dt-bindings/gpio/gpio.h>\n\n/ {\n\tmodel = \"Cloud Engines PogoPlug Pro\";\n\n\tcompatible = \"cloudengines,pogoplugpro\", \"oxsemi,ox820\";\n\n\tchosen {\n\t\tbootargs = \"earlyprintk console=ttyS0,115200\";\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\tmemory {\n\t\t/* 128Mbytes DDR */\n\t\treg = <0x60000000 0x8000000>;\n\t};\n\n\taliases {\n\t\tserial0 = &uart0;\n\t\tgpio0 = &gpio0;\n\t\tgpio1 = &gpio1;\n\t\tled-boot = &led_status;\n\t\tled-failsafe = &led_warn;\n\t\tled-running = &led_act;\n\t\tled-upgrade = &led_warn;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_status: blue {\n\t\t\tlabel = \"pogoplug:blue\";\n\t\t\tgpios = <&gpio0 2 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"keep\";\n\t\t};\n\n\t\tled_warn: orange {\n\t\t\tlabel = \"pogoplug:orange\";\n\t\t\tgpios = <&gpio1 16 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"keep\";\n\t\t};\n\n\t\tled_act: green {\n\t\t\tlabel = \"pogoplug:green\";\n\t\t\tgpios = <&gpio1 17 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"keep\";\n\t\t};\n\t};\n};\n\n&uart0 {\n\tstatus = \"okay\";\n\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0>;\n};\n\n&nandc {\n\tstatus = \"okay\";\n\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_nand>;\n\n\tnand@0 {\n\t\treg = <0>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tnand-ecc-mode = \"soft\";\n\t\tnand-ecc-algo = \"hamming\";\n\n\t\tpartition@0 {\n\t\t\tlabel = \"stage1\";\n\t\t\treg = <0x00000000 0x00040000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@40000 {\n\t\t\tlabel = \"u-boot\";\n\t\t\treg = <0x00040000 0x00380000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@3c0000 {\n\t\t\tlabel = \"u-boot-env\";\n\t\t\treg = <0x003c0000 0x00080000>;\n\t\t};\n\n\t\tpartition@440000 {\n\t\t\tlabel = \"kernel\";\n\t\t\treg = <0x00440000 0x009c0000>;\n\t\t};\n\n\t\tpartition@e00000 {\n\t\t\tlabel = \"ubi\";\n\t\t\treg = <0x00e00000 0x07200000>;\n\t\t};\n\t};\n};\n\n&ehci {\n\tstatus = \"okay\";\n};\n\n&etha {\n\tstatus = \"okay\";\n\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_etha_mdio>;\n};\n\n&sata {\n\tstatus = \"okay\";\n};\n\n&pcie_phy {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/oxnas/files/arch/arm/boot/dts/ox820-mitrastar-stg-212.dts",
    "content": "/dts-v1/;\n\n#include \"ox820.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"MitraStar Technology Corp. STG-212\";\n\n\tcompatible = \"mitrastar,stg-212\", \"oxsemi,ox820\";\n\n\tchosen {\n\t\tbootargs = \"earlyprintk console=ttyS0,115200\";\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\tmemory {\n\t\t/* 128Mbytes DDR */\n\t\treg = <0x60000000 0x8000000>;\n\t};\n\n\taliases {\n\t\tserial0 = &uart0;\n\t\tgpio0 = &gpio0;\n\t\tgpio1 = &gpio1;\n\t\tled-boot = &led_status;\n\t\tled-failsafe = &led_warn;\n\t\tled-running = &led_status;\n\t\tled-upgrade = &led_warn;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tpoll-interval = <100>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio1 11 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t\tcopy {\n\t\t\tlabel = \"copy\";\n\t\t\tgpios = <&gpio1 13 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_COPY>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tled_status: status {\n\t\t\tlabel = \"zyxel:blue:status\";\n\t\t\tgpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t\tled_warn: status2 {\n\t\t\tlabel = \"zyxel:red:status\";\n\t\t\tgpios = <&gpio1 6 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tcopy {\n\t\t\tlabel = \"zyxel:orange:copy\";\n\t\t\tgpios = <&gpio1 8 GPIO_ACTIVE_LOW>;\n\t\t\ttrigger-sources = <&ehci_port1>, <&ehci_port2>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\t};\n\n\ti2c-gpio {\n\t\tcompatible = \"i2c-gpio\";\n\t\tgpios = <&gpio1  9 GPIO_ACTIVE_HIGH\n\t\t         &gpio1 10 GPIO_ACTIVE_HIGH>;\n\t\ti2c-gpio,delay-us = <10>;\n\t};\n};\n\n&uart0 {\n\tstatus = \"okay\";\n\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0>;\n};\n\n&nandc {\n\tstatus = \"okay\";\n\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_nand>;\n\n\tnand@0 {\n\t\treg = <0>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tnand-ecc-mode = \"soft\";\n\t\tnand-ecc-algo = \"hamming\";\n\n\t\tpartition@0 {\n\t\t\tlabel = \"stage1\";\n\t\t\treg = <0x00000000 0x00040000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@40000 {\n\t\t\tlabel = \"u-boot\";\n\t\t\treg = <0x00040000 0x00380000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@3c0000 {\n\t\t\tlabel = \"u-boot-env\";\n\t\t\treg = <0x003c0000 0x00080000>;\n\t\t};\n\n\t\tpartition@440000 {\n\t\t\tlabel = \"kernel\";\n\t\t\treg = <0x00440000 0x009c0000>;\n\t\t};\n\n\t\tpartition@e00000 {\n\t\t\tlabel = \"ubi\";\n\t\t\treg = <0x00e00000 0x07200000>;\n\t\t};\n\t};\n};\n\n&etha {\n\tstatus = \"okay\";\n\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_etha_mdio>;\n};\n\n&ehci {\n\tstatus = \"okay\";\n};\n\n&sata {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/oxnas/files/arch/arm/boot/dts/ox820-shuttle-kd20.dts",
    "content": "/dts-v1/;\n\n#include \"ox820.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/thermal/thermal.h>\n\n/ {\n\tmodel = \"Shuttle KD20\";\n\n\tcompatible = \"shuttle,kd20\", \"oxsemi,ox820\";\n\n\tchosen {\n\t\tbootargs = \"earlyprintk console=ttyS0,115200\";\n\t\tstdout-path = \"serial0:115200n8\";\n\t};\n\n\tmemory {\n\t\t/* 256Mbytes DDR */\n\t\treg = <0x60000000 0x10000000>;\n\t};\n\n\taliases {\n\t\tserial0 = &uart0;\n\t\tgpio0 = &gpio0;\n\t\tgpio1 = &gpio1;\n\t\tled-boot = &led_status;\n\t\tled-failsafe = &led_warn;\n\t\tled-running = &led_status;\n\t\tled-upgrade = &led_warn;\n\t};\n\n\tthermal_zones {\n\t\tchassis-thermal {\n\t\t\t/* Poll every 20 seconds */\n\t\t\tpolling-delay = <20000>;\n\t\t\t/* Poll every 2nd second when cooling */\n\t\t\tpolling-delay-passive = <2000>;\n\n\t\t\tthermal-sensors = <&hdd0_temp>, <&hdd1_temp>;\n\n\t\t\ttrips {\n\t\t\t\tchassis_alert0: chassis-alert0 {\n\t\t\t\t\t/* At 43 degrees turn on fan */\n\t\t\t\t\ttemperature = <43000>;\n\t\t\t\t\thysteresis = <3000>;\n\t\t\t\t\ttype = \"active\";\n\t\t\t\t};\n\n\t\t\t\tchassis_alert1: chassis-alert1 {\n\t\t\t\t\t/* At 60 degrees emergency shutdown */\n\t\t\t\t\ttemperature = <60000>;\n\t\t\t\t\thysteresis = <2000>;\n\t\t\t\t\ttype = \"critical\";\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tcooling-maps {\n\t\t\t\tmap0 {\n\t\t\t\t\ttrip = <&chassis_alert0>;\n\t\t\t\t\tcooling-device = <&system_fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t};\n\n\ti2c-gpio {\n\t\tcompatible = \"i2c-gpio\";\n\t\tsda-gpios = <&gpio1 9 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;\n\t\tsck-gpios = <&gpio1 10 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;\n\t\ti2c-gpio,delay-us = <10>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\trtc0: rtc@51 {\n\t\t\tcompatible = \"nxp,pcf8563\";\n\t\t\treg = <0x51>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tpoll-interval = <100>;\n\n\t\tpower {\n\t\t\tlabel = \"power\";\n\t\t\tgpios = <&gpio0 10 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_POWER>;\n\t\t};\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 11 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t\teject1 {\n\t\t\tlabel = \"eject1\";\n\t\t\tgpios = <&gpio0 5 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_EJECTCD>;\n\t\t};\n\t\teject2 {\n\t\t\tlabel = \"eject2\";\n\t\t\tgpios = <&gpio0 6 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <162>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tled_status: status {\n\t\t\tlabel = \"kd20:blue:status\";\n\t\t\tgpios = <&gpio1 16 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t\tled_warn: status2 {\n\t\t\tlabel = \"kd20:red:status\";\n\t\t\tgpios = <&gpio1 17 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t\thdd1blue {\n\t\t\tlabel = \"kd20:blue:hdd1\";\n\t\t\tgpios = <&gpio0 27 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"ata1\";\n\t\t};\n\t\thdd1red {\n\t\t\tlabel = \"kd20:red:hdd1\";\n\t\t\tgpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t\thdd2blue {\n\t\t\tlabel = \"kd20:blue:hdd2\";\n\t\t\tgpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"ata2\";\n\t\t};\n\t\thdd2red {\n\t\t\tlabel = \"kd20:red:hdd2\";\n\t\t\tgpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t\tusb {\n\t\t\tlabel = \"kd20:blue:usb\";\n\t\t\tgpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;\n\t\t\ttrigger-sources = <&ehci_port1>, <&ehci_port2>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\t};\n\n\tbeeper: beeper {\n\t\tcompatible = \"gpio-beeper\";\n\t\tgpios = <&gpio1 11 GPIO_ACTIVE_HIGH>;\n\t};\n\n\tsystem_fan: gpio-fan {\n\t\tcompatible = \"gpio-fan\";\n\t\tgpios = <&gpio0 2 GPIO_ACTIVE_HIGH>;\n\t\tgpio-fan,speed-map = <0    0\n\t\t\t\t      3000 1>;\n\t};\n\n\tgpio-poweroff {\n\t\tcompatible = \"gpio-poweroff\";\n\t\tgpios = <&gpio0 9 GPIO_ACTIVE_HIGH>;\n\t};\n};\n\n&uart0 {\n\tstatus = \"okay\";\n\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_uart0>;\n};\n\n&nandc {\n\tstatus = \"okay\";\n\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_nand>;\n\n\tnand@0 {\n\t\treg = <0>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tnand-ecc-mode = \"soft\";\n\t\tnand-ecc-algo = \"hamming\";\n\n\t\tpartition@0 {\n\t\t\tlabel = \"stage1\";\n\t\t\treg = <0x00000000 0x00040000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@40000 {\n\t\t\tlabel = \"u-boot\";\n\t\t\treg = <0x00040000 0x001e0000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@220000 {\n\t\t\tlabel = \"u-boot-env\";\n\t\t\treg = <0x00220000 0x00020000>;\n\t\t};\n\n\t\tpartition@240000 {\n\t\t\tlabel = \"initrd\";\n\t\t\treg = <0x00240000 0x00600000>;\n\t\t};\n\n\t\tpartition@840000 {\n\t\t\tlabel = \"kernel\";\n\t\t\treg = <0x00840000 0x007C0000>;\n\t\t};\n\n\t\tpartition@e00000 {\n\t\t\tlabel = \"ubi\";\n\t\t\treg = <0x01000000 0x07000000>;\n\t\t};\n\t};\n};\n\n&etha {\n\tstatus = \"okay\";\n\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pinctrl_etha_mdio>;\n};\n\n&ehci {\n\tstatus = \"okay\";\n};\n\n&sata {\n\tstatus = \"okay\";\n\tnr-ports = <2>;\n\n\thdd0_temp: sata-port@0 {\n\t\treg = <0>;\n\t\t#thermal-sensor-cells = <0>;\n\t};\n\n\thdd1_temp: sata-port@1 {\n\t\treg = <1>;\n\t\t#thermal-sensor-cells = <0>;\n\t};\n};\n\n&pcie_phy {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/oxnas/files/arch/arm/include/debug/uncompress-ox820.h",
    "content": "/* linux/include/asm-arm/arch-oxnas/uncompress.h\n *\n * This program is free software; you can redistribute it and/or modify\n * it under the terms of the GNU General Public License version 2 as\n * published by the Free Software Foundation.\n*/\n\n#ifndef __ASM_ARCH_UNCOMPRESS_H\n#define __ASM_ARCH_UNCOMPRESS_H\n\n#define OXNAS_UART1_BASE 0x44200000\n\nstatic inline void putc(int c)\n{\n\tstatic volatile unsigned char *uart =\n\t\t(volatile unsigned char *)OXNAS_UART1_BASE;\n\n\twhile (!(uart[5] & 0x20)) {\t/* LSR reg THR empty bit */\n\t\tbarrier();\n\t}\n\tuart[0] = c;\t\t\t/* THR register */\n}\n\nstatic inline void flush(void)\n{\n}\n\n#define arch_decomp_setup()\n\n#define arch_decomp_wdog()\n\n#endif /* __ASM_ARCH_UNCOMPRESS_H */\n"
  },
  {
    "path": "target/linux/oxnas/files/drivers/ata/sata_oxnas.c",
    "content": "/*\n * sata_oxnas\n *      A driver to interface the 934 based sata core present in the ox820\n *      with libata and scsi\n * based on sata_oxnas driver by Ma Haijun <mahaijuns@gmail.com>\n * based on ox820 sata code by:\n *  Copyright (c) 2007 Oxford Semiconductor Ltd.\n *\n * This program is free software; you can redistribute it and/or modify\n * it under the terms of the GNU General Public License as published by\n * the Free Software Foundation; either version 2, or (at your option)\n * any later version.\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n * GNU General Public License for more details.\n */\n\n#include <linux/ata.h>\n#include <linux/libata.h>\n#include <linux/of_platform.h>\n#include <linux/delay.h>\n#include <linux/module.h>\n#include <linux/slab.h>\n#include <linux/spinlock.h>\n#include <linux/of_address.h>\n#include <linux/of_irq.h>\n#include <linux/clk.h>\n#include <linux/reset.h>\n\n#include <linux/io.h>\n#include <linux/sizes.h>\n\nstatic inline void oxnas_register_clear_mask(void __iomem *p, unsigned mask)\n{\n\tu32 val = readl_relaxed(p);\n\n\tval &= ~mask;\n\twritel_relaxed(val, p);\n}\n\nstatic inline void oxnas_register_set_mask(void __iomem *p, unsigned mask)\n{\n\tu32 val = readl_relaxed(p);\n\n\tval |= mask;\n\twritel_relaxed(val, p);\n}\n\nstatic inline void oxnas_register_value_mask(void __iomem *p,\n\t\t\t\t\t     unsigned mask, unsigned new_value)\n{\n\t/* TODO sanity check mask & new_value = new_value */\n\tu32 val = readl_relaxed(p);\n\n\tval &= ~mask;\n\tval |= new_value;\n\twritel_relaxed(val, p);\n}\n\n/* sgdma request structure */\nstruct sgdma_request {\n\tvolatile u32 qualifier;\n\tvolatile u32 control;\n\tdma_addr_t src_pa;\n\tdma_addr_t dst_pa;\n} __packed __aligned(4);\n\n\n/* Controller information */\nenum {\n\tSATA_OXNAS_MAX_PRD = 63,\n\tSATA_OXNAS_DMA_SIZE = SATA_OXNAS_MAX_PRD *\n\t\t\t\tsizeof(struct ata_bmdma_prd) +\n\t\t\t\tsizeof(struct sgdma_request),\n\tSATA_OXNAS_MAX_PORTS\t= 2,\n\t/** The different Oxsemi SATA core version numbers */\n\tSATA_OXNAS_CORE_VERSION = 0x1f3,\n\tSATA_OXNAS_IRQ_FLAG\t= IRQF_SHARED,\n\tSATA_OXNAS_HOST_FLAGS\t= (ATA_FLAG_SATA | ATA_FLAG_PIO_DMA |\n\t\t\tATA_FLAG_NO_ATAPI /*| ATA_FLAG_NCQ*/),\n\tSATA_OXNAS_QUEUE_DEPTH\t= 32,\n\n\tSATA_OXNAS_DMA_BOUNDARY = 0xFFFFFFFF,\n};\n\n\n/*\n * SATA Port Registers\n */\nenum {\n\t/** sata host port register offsets */\n\tORB1 = 0x00,\n\tORB2 = 0x04,\n\tORB3 = 0x08,\n\tORB4 = 0x0C,\n\tORB5 = 0x10,\n\tMASTER_STATUS = 0x10,\n\tFIS_CTRL = 0x18,\n\tFIS_DATA = 0x1C,\n\tINT_STATUS = 0x30,\n\tINT_CLEAR = 0x30,\n\tINT_ENABLE = 0x34,\n\tINT_DISABLE = 0x38,\n\tVERSION = 0x3C,\n\tSATA_CONTROL = 0x5C,\n\tSATA_COMMAND = 0x60,\n\tHID_FEATURES = 0x64,\n\tPORT_CONTROL = 0x68,\n\tDRIVE_CONTROL = 0x6C,\n\t/** These registers allow access to the link layer registers\n\tthat reside in a different clock domain to the processor bus */\n\tLINK_DATA = 0x70,\n\tLINK_RD_ADDR = 0x74,\n\tLINK_WR_ADDR = 0x78,\n\tLINK_CONTROL = 0x7C,\n\t/* window control */\n\tWIN1LO = 0x80,\n\tWIN1HI = 0x84,\n\tWIN2LO = 0x88,\n\tWIN2HI = 0x8C,\n\tWIN0_CONTROL = 0x90,\n};\n\n/** sata port register bits */\nenum{\n\t/**\n\t * commands to issue in the master status to tell it to move shadow ,\n\t * registers to the actual device ,\n\t */\n\tSATA_OPCODE_MASK = 0x00000007,\n\tCMD_WRITE_TO_ORB_REGS_NO_COMMAND = 0x4,\n\tCMD_WRITE_TO_ORB_REGS = 0x2,\n\tCMD_SYNC_ESCAPE = 0x7,\n\tCMD_CORE_BUSY = (1 << 7),\n\tCMD_DRIVE_SELECT_SHIFT = 12,\n\tCMD_DRIVE_SELECT_MASK = (0xf << CMD_DRIVE_SELECT_SHIFT),\n\n\t/** interrupt bits */\n\tINT_END_OF_CMD = 1 << 0,\n\tINT_LINK_SERROR = 1 << 1,\n\tINT_ERROR = 1 << 2,\n\tINT_LINK_IRQ = 1 << 3,\n\tINT_REG_ACCESS_ERR = 1 << 7,\n\tINT_BIST_FIS = 1 << 11,\n\tINT_MASKABLE =\tINT_END_OF_CMD |\n\t\t\tINT_LINK_SERROR |\n\t\t\tINT_ERROR |\n\t\t\tINT_LINK_IRQ |\n\t\t\tINT_REG_ACCESS_ERR |\n\t\t\tINT_BIST_FIS,\n\tINT_WANT =\tINT_END_OF_CMD |\n\t\t\tINT_LINK_SERROR |\n\t\t\tINT_REG_ACCESS_ERR |\n\t\t\tINT_ERROR,\n\tINT_ERRORS =\tINT_LINK_SERROR |\n\t\t\tINT_REG_ACCESS_ERR |\n\t\t\tINT_ERROR,\n\n\t/** raw interrupt bits, unmaskable, but do not generate interrupts */\n\tRAW_END_OF_CMD  = INT_END_OF_CMD << 16,\n\tRAW_LINK_SERROR = INT_LINK_SERROR  << 16,\n\tRAW_ERROR  = INT_ERROR << 16,\n\tRAW_LINK_IRQ  = INT_LINK_IRQ << 16,\n\tRAW_REG_ACCESS_ERR = INT_REG_ACCESS_ERR << 16,\n\tRAW_BIST_FIS  = INT_BIST_FIS << 16,\n\tRAW_WANT  = INT_WANT << 16,\n\tRAW_ERRORS  = INT_ERRORS << 16,\n\n\t/**\n\t * variables to write to the device control register to set the current\n\t * device, ie. master or slave.\n\t */\n\tDR_CON_48 = 2,\n\tDR_CON_28 = 0,\n\n\tSATA_CTL_ERR_MASK = 0x00000016,\n\n};\n\n/* ATA SGDMA register offsets */\nenum {\n\tSGDMA_CONTROL = 0x0,\n\tSGDMA_STATUS = 0x4,\n\tSGDMA_REQUESTPTR = 0x8,\n\tSGDMA_RESETS = 0xC,\n\tSGDMA_CORESIZE = 0x10,\n};\n\n/* DMA controller register offsets */\nenum {\n\tDMA_CONTROL = 0x0,\n\tDMA_CORESIZE = 0x20,\n\n\tDMA_CONTROL_RESET = (1 << 12),\n};\n\nenum {\n\t/* see DMA core docs for the values. Out means from memory (bus A) out\n\t * to disk (bus B) */\n\tSGDMA_REQCTL0OUT = 0x0497c03d,\n\t/* burst mode disabled when no micro code used */\n\tSGDMA_REQCTL0IN = 0x0493a3c1,\n\tSGDMA_REQCTL1OUT = 0x0497c07d,\n\tSGDMA_REQCTL1IN = 0x0497a3c5,\n\tSGDMA_CONTROL_NOGO = 0x3e,\n\tSGDMA_CONTROL_GO = SGDMA_CONTROL_NOGO | 1,\n\tSGDMA_ERRORMASK = 0x3f,\n\tSGDMA_BUSY = 0x80,\n\n\tSGDMA_RESETS_CTRL = 1 << 0,\n\tSGDMA_RESETS_ARBT = 1 << 1,\n\tSGDMA_RESETS_AHB = 1 << 2,\n\tSGDMA_RESETS_ALL =\tSGDMA_RESETS_CTRL |\n\t\t\t\tSGDMA_RESETS_ARBT |\n\t\t\t\tSGDMA_RESETS_AHB,\n\n\t/* Final EOTs */\n\tSGDMA_REQQUAL = 0x00220001,\n\n};\n\n/** SATA core register offsets */\nenum {\n\tDM_DBG1 = 0x000,\n\tRAID_SET = 0x004,\n\tDM_DBG2 = 0x008,\n\tDATACOUNT_PORT0 = 0x010,\n\tDATACOUNT_PORT1 = 0x014,\n\tCORE_INT_STATUS = 0x030,\n\tCORE_INT_CLEAR = 0x030,\n\tCORE_INT_ENABLE = 0x034,\n\tCORE_INT_DISABLE  = 0x038,\n\tCORE_REBUILD_ENABLE = 0x050,\n\tCORE_FAILED_PORT_R = 0x054,\n\tDEVICE_CONTROL = 0x068,\n\tEXCESS = 0x06C,\n\tRAID_SIZE_LOW = 0x070,\n\tRAID_SIZE_HIGH = 0x074,\n\tPORT_ERROR_MASK = 0x078,\n\tIDLE_STATUS = 0x07C,\n\tRAID_CONTROL = 0x090,\n\tDATA_PLANE_CTRL = 0x0AC,\n\tCORE_DATAPLANE_STAT = 0x0b8,\n\tPROC_PC = 0x100,\n\tCONFIG_IN = 0x3d8,\n\tPROC_START = 0x3f0,\n\tPROC_RESET = 0x3f4,\n\tUCODE_STORE = 0x1000,\n\tRAID_WP_BOT_LOW = 0x1FF0,\n\tRAID_WP_BOT_HIGH  = 0x1FF4,\n\tRAID_WP_TOP_LOW = 0x1FF8,\n\tRAID_WP_TOP_HIGH = 0x1FFC,\n\tDATA_MUX_RAM0 = 0x8000,\n\tDATA_MUX_RAM1 = 0xA000,\n\tPORT_SIZE = 0x10000,\n};\n\nenum {\n\t/* Sata core debug1 register bits */\n\tCORE_PORT0_DATA_DIR_BIT = 20,\n\tCORE_PORT1_DATA_DIR_BIT = 21,\n\tCORE_PORT0_DATA_DIR = 1 << CORE_PORT0_DATA_DIR_BIT,\n\tCORE_PORT1_DATA_DIR = 1 << CORE_PORT1_DATA_DIR_BIT,\n\n\t/** sata core control register bits */\n\tSCTL_CLR_ERR = 0x00003016,\n\tRAID_CLR_ERR = 0x0000011e,\n\n\t/* Interrupts direct from the ports */\n\tNORMAL_INTS_WANTED = 0x00000303,\n\n\t/* shift these left by port number */\n\tCOREINT_HOST = 0x00000001,\n\tCOREINT_END = 0x00000100,\n\tCORERAW_HOST = COREINT_HOST << 16,\n\tCORERAW_END = COREINT_END  << 16,\n\n\t/* Interrupts from the RAID controller only */\n\tRAID_INTS_WANTED = 0x00008300,\n\n\t/* The bits in the IDLE_STATUS that, when set indicate an idle core */\n\tIDLE_CORES = (1 << 18) | (1 << 19),\n\n\t/* Data plane control error-mask mask and bit, these bit in the data\n\t * plane control mask out errors from the ports that prevent the SGDMA\n\t * care from sending an interrupt */\n\tDPC_ERROR_MASK = 0x00000300,\n\tDPC_ERROR_MASK_BIT = 0x00000100,\n\t/* enable jbod micro-code */\n\tDPC_JBOD_UCODE = 1 << 0,\n\tDPC_FIS_SWCH = 1 << 1,\n\n\t/** Device Control register bits */\n\tDEVICE_CONTROL_DMABT = 1 << 4,\n\tDEVICE_CONTROL_ABORT = 1 << 2,\n\tDEVICE_CONTROL_PAD = 1 << 3,\n\tDEVICE_CONTROL_PADPAT = 1 << 16,\n\tDEVICE_CONTROL_PRTRST = 1 << 8,\n\tDEVICE_CONTROL_RAMRST = 1 << 12,\n\tDEVICE_CONTROL_ATA_ERR_OVERRIDE = 1 << 28,\n\n\t/** oxsemi HW raid modes */\n\tOXNASSATA_NOTRAID = 0,\n\tOXNASSATA_RAID0 = 1,\n\tOXNASSATA_RAID1 = 2,\n\t/** OX820 specific HW-RAID register values */\n\tRAID_TWODISKS = 3,\n\tUNKNOWN_MODE = ~0,\n\n\tCONFIG_IN_RESUME = 2,\n};\n\n/* SATA PHY Registers */\nenum {\n\tPHY_STAT = 0x00,\n\tPHY_DATA = 0x04,\n};\n\nenum {\n\tSTAT_READ_VALID = (1 << 21),\n\tSTAT_CR_ACK = (1 << 20),\n\tSTAT_CR_READ = (1 << 19),\n\tSTAT_CR_WRITE = (1 << 18),\n\tSTAT_CAP_DATA = (1 << 17),\n\tSTAT_CAP_ADDR = (1 << 16),\n\n\tSTAT_ACK_ANY =\tSTAT_CR_ACK |\n\t\t\tSTAT_CR_READ |\n\t\t\tSTAT_CR_WRITE |\n\t\t\tSTAT_CAP_DATA |\n\t\t\tSTAT_CAP_ADDR,\n\n\tCR_READ_ENABLE = (1 << 16),\n\tCR_WRITE_ENABLE = (1 << 17),\n\tCR_CAP_DATA = (1 << 18),\n};\n\nenum {\n\t/* Link layer registers */\n\tSERROR_IRQ_MASK = 5,\n};\n\nenum {\n\tOXNAS_SATA_SOFTRESET = 1,\n\tOXNAS_SATA_REINIT = 2,\n};\n\nenum {\n\tOXNAS_SATA_UCODE_RAID0,\n\tOXNAS_SATA_UCODE_RAID1,\n\tOXNAS_SATA_UCODE_JBOD,\n\tOXNAS_SATA_UCODE_NONE,\n};\n\nenum {\n\tSATA_UNLOCKED,\n\tSATA_WRITER,\n\tSATA_READER,\n\tSATA_REBUILD,\n\tSATA_HWRAID,\n\tSATA_SCSI_STACK\n};\n\ntypedef irqreturn_t (*oxnas_sata_isr_callback_t)(int, unsigned long, int);\n\nstruct sata_oxnas_host_priv {\n\tvoid __iomem *port_base;\n\tvoid __iomem *dmactl_base;\n\tvoid __iomem *sgdma_base;\n\tvoid __iomem *core_base;\n\tvoid __iomem *phy_base;\n\tdma_addr_t dma_base;\n\tvoid __iomem *dma_base_va;\n\tsize_t dma_size;\n\tint irq;\n\tint n_ports;\n\tint current_ucode;\n\tu32 port_frozen;\n\tu32 port_in_eh;\n\tstruct clk *clk;\n\tstruct reset_control *rst_sata;\n\tstruct reset_control *rst_link;\n\tstruct reset_control *rst_phy;\n\tspinlock_t phy_lock;\n\tspinlock_t core_lock;\n\tint core_locked;\n\tint reentrant_port_no;\n\tint hw_lock_count;\n\tint direct_lock_count;\n\tvoid *locker_uid;\n\tint current_locker_type;\n\tint scsi_nonblocking_attempts;\n\toxnas_sata_isr_callback_t isr_callback;\n\tvoid *isr_arg;\n\twait_queue_head_t fast_wait_queue;\n\twait_queue_head_t scsi_wait_queue;\n};\n\n\nstruct sata_oxnas_port_priv {\n\tvoid __iomem *port_base;\n\tvoid __iomem *dmactl_base;\n\tvoid __iomem *sgdma_base;\n\tvoid __iomem *core_base;\n\tstruct sgdma_request *sgdma_request;\n\tdma_addr_t sgdma_request_pa;\n};\n\nstatic u8 sata_oxnas_check_status(struct ata_port *ap);\nstatic int sata_oxnas_cleanup(struct ata_host *ah);\nstatic void sata_oxnas_tf_load(struct ata_port *ap,\n\t\t\t\tconst struct ata_taskfile *tf);\nstatic void sata_oxnas_irq_on(struct ata_port *ap);\nstatic void sata_oxnas_post_reset_init(struct ata_port *ap);\n\nstatic int sata_oxnas_acquire_hw(struct ata_port *ap, int may_sleep,\n\t\t\t\t int timeout_jiffies);\nstatic void sata_oxnas_release_hw(struct ata_port *ap);\n\nstatic const void *HW_LOCKER_UID = (void *)0xdeadbeef;\n\n/***************************************************************************\n* ASIC access\n***************************************************************************/\nstatic void wait_cr_ack(void __iomem *phy_base)\n{\n\twhile ((ioread32(phy_base + PHY_STAT) >> 16) & 0x1f)\n\t\t; /* wait for an ack bit to be set */\n}\n\nstatic u16 read_cr(void __iomem *phy_base, u16 address)\n{\n\tiowrite32((u32)address, phy_base + PHY_STAT);\n\twait_cr_ack(phy_base);\n\tiowrite32(CR_READ_ENABLE, phy_base + PHY_DATA);\n\twait_cr_ack(phy_base);\n\treturn (u16)ioread32(phy_base + PHY_STAT);\n}\n\nstatic void write_cr(void __iomem *phy_base, u16 data, u16 address)\n{\n\tiowrite32((u32)address, phy_base + PHY_STAT);\n\twait_cr_ack(phy_base);\n\tiowrite32((data | CR_CAP_DATA), phy_base + PHY_DATA);\n\twait_cr_ack(phy_base);\n\tiowrite32(CR_WRITE_ENABLE, phy_base + PHY_DATA);\n\twait_cr_ack(phy_base);\n}\n\n#define PH_GAIN\t\t 2\n#define FR_GAIN\t\t 3\n#define PH_GAIN_OFFSET  6\n#define FR_GAIN_OFFSET  8\n#define PH_GAIN_MASK  (0x3 << PH_GAIN_OFFSET)\n#define FR_GAIN_MASK  (0x3 << FR_GAIN_OFFSET)\n#define USE_INT_SETTING  (1<<5)\n\nvoid workaround5458(struct ata_host *ah)\n{\n\tstruct sata_oxnas_host_priv *hd = ah->private_data;\n\tvoid __iomem *phy_base = hd->phy_base;\n\tu16 rx_control;\n\tunsigned i;\n\n\tfor (i = 0; i < 2; i++) {\n\t\trx_control = read_cr(phy_base, 0x201d + (i << 8));\n\t\trx_control &= ~(PH_GAIN_MASK | FR_GAIN_MASK);\n\t\trx_control |= PH_GAIN << PH_GAIN_OFFSET;\n\t\trx_control |= (FR_GAIN << FR_GAIN_OFFSET) | USE_INT_SETTING;\n\t\twrite_cr(phy_base, rx_control, 0x201d+(i<<8));\n\t}\n}\n\n/**\n * allows access to the link layer registers\n * @param link_reg the link layer register to access (oxsemi indexing ie\n *\t\t00 = static config, 04 = phy ctrl)\n */\nvoid sata_oxnas_link_write(struct ata_port *ap, unsigned int link_reg, u32 val)\n{\n\tstruct sata_oxnas_port_priv *pd = ap->private_data;\n\tstruct sata_oxnas_host_priv *hd = ap->host->private_data;\n\tvoid __iomem *port_base = pd->port_base;\n\tu32 patience;\n\tunsigned long flags;\n\n\tDPRINTK(\"P%d [0x%02x]->0x%08x\\n\", ap->port_no, link_reg, val);\n\n\tspin_lock_irqsave(&hd->phy_lock, flags);\n\tiowrite32(val, port_base + LINK_DATA);\n\n\t/* accessed twice as a work around for a bug in the SATA abp bridge\n\t * hardware (bug 6828) */\n\tiowrite32(link_reg , port_base + LINK_WR_ADDR);\n\tioread32(port_base + LINK_WR_ADDR);\n\n\tfor (patience = 0x100000; patience > 0; --patience) {\n\t\tif (ioread32(port_base + LINK_CONTROL) & 0x00000001)\n\t\t\tbreak;\n\t}\n\tspin_unlock_irqrestore(&hd->phy_lock, flags);\n}\n\nstatic int sata_oxnas_scr_write_port(struct ata_port *ap, unsigned int sc_reg,\n\t\t\t\t\tu32 val)\n{\n\tsata_oxnas_link_write(ap, 0x20 + (sc_reg * 4), val);\n\treturn 0;\n}\n\nstatic int sata_oxnas_scr_write(struct ata_link *link, unsigned int sc_reg,\n\t\t\t\tu32 val)\n{\n\treturn sata_oxnas_scr_write_port(link->ap, sc_reg, val);\n}\n\nu32 sata_oxnas_link_read(struct ata_port *ap, unsigned int link_reg)\n{\n\tstruct sata_oxnas_port_priv *pd = ap->private_data;\n\tstruct sata_oxnas_host_priv *hd = ap->host->private_data;\n\tvoid __iomem *port_base = pd->port_base;\n\tu32 result;\n\tu32 patience;\n\tunsigned long flags;\n\n\tspin_lock_irqsave(&hd->phy_lock, flags);\n\t/* accessed twice as a work around for a bug in the SATA abp bridge\n\t * hardware (bug 6828) */\n\tiowrite32(link_reg, port_base + LINK_RD_ADDR);\n\tioread32(port_base + LINK_RD_ADDR);\n\n\tfor (patience = 0x100000; patience > 0; --patience) {\n\t\tif (ioread32(port_base + LINK_CONTROL) & 0x00000001)\n\t\t\tbreak;\n\t}\n\tif (patience == 0)\n\t\tDPRINTK(\"link read timed out for port %d\\n\", ap->port_no);\n\n\tresult = ioread32(port_base + LINK_DATA);\n\tspin_unlock_irqrestore(&hd->phy_lock, flags);\n\n\treturn result;\n}\n\nstatic int sata_oxnas_scr_read_port(struct ata_port *ap, unsigned int sc_reg,\n\t\t\t\t\tu32 *val)\n{\n\t*val = sata_oxnas_link_read(ap, 0x20 + (sc_reg*4));\n\treturn 0;\n}\n\nstatic int sata_oxnas_scr_read(struct ata_link *link,\n\t\t\t     unsigned int sc_reg, u32 *val)\n{\n\treturn sata_oxnas_scr_read_port(link->ap, sc_reg, val);\n}\n\n/**\n * sata_oxnas_irq_clear is called during probe just before the interrupt handler is\n * registered, to be sure hardware is quiet. It clears and masks interrupt bits\n * in the SATA core.\n *\n * @param ap hardware with the registers in\n */\nstatic void sata_oxnas_irq_clear(struct ata_port *ap)\n{\n\tstruct sata_oxnas_port_priv *port_priv = ap->private_data;\n\n\t/* clear pending interrupts */\n\tiowrite32(~0, port_priv->port_base + INT_CLEAR);\n\tiowrite32(COREINT_END, port_priv->core_base + CORE_INT_CLEAR);\n}\n\n/**\n * qc_issue is used to make a command active, once the hardware and S/G tables\n * have been prepared. IDE BMDMA drivers use the helper function\n * ata_qc_issue_prot() for taskfile protocol-based dispatch. More advanced\n * drivers roll their own ->qc_issue implementation, using this as the\n * \"issue new ATA command to hardware\" hook.\n * @param qc the queued command to issue\n */\nstatic unsigned int sata_oxnas_qc_issue(struct ata_queued_cmd *qc)\n{\n\tstruct sata_oxnas_port_priv *pd = qc->ap->private_data;\n\tstruct sata_oxnas_host_priv *hd = qc->ap->host->private_data;\n\n\tvoid __iomem *port_base = pd->port_base;\n\tvoid __iomem *core_base = pd->core_base;\n\tint port_no = qc->ap->port_no;\n\tint no_microcode = (hd->current_ucode == UNKNOWN_MODE);\n\tu32 reg;\n\n\t/* check the core is idle */\n\tif (ioread32(port_base + SATA_COMMAND) & CMD_CORE_BUSY) {\n\t\tint count = 0;\n\n\t\tDPRINTK(\"core busy for a command on port %d\\n\",\n\t\t\tqc->ap->port_no);\n\t\tdo {\n\t\t\tmdelay(1);\n\t\t\tif (++count > 100) {\n\t\t\t\tDPRINTK(\"core busy for a command on port %d\\n\",\n\t\t\t\t\tqc->ap->port_no);\n\t\t\t\t/* CrazyDumpDebug(); */\n\t\t\t\tsata_oxnas_cleanup(qc->ap->host);\n\t\t\t}\n\t\t} while (ioread32(port_base + SATA_COMMAND) & CMD_CORE_BUSY);\n\t}\n\n\t/* enable passing of error signals to DMA sub-core by clearing the\n\t * appropriate bit */\n\treg = ioread32(core_base + DATA_PLANE_CTRL);\n\tif (no_microcode)\n\t\treg |= (DPC_ERROR_MASK_BIT | (DPC_ERROR_MASK_BIT << 1));\n\treg &= ~(DPC_ERROR_MASK_BIT << port_no);\n\tiowrite32(reg, core_base + DATA_PLANE_CTRL);\n\n\t/* Disable all interrupts for ports and RAID controller */\n\tiowrite32(~0, port_base + INT_DISABLE);\n\n\t/* Disable all interrupts for core */\n\tiowrite32(~0, core_base + CORE_INT_DISABLE);\n\twmb();\n\n\t/* Load the command settings into the orb registers */\n\tsata_oxnas_tf_load(qc->ap, &qc->tf);\n\n\t/* both pio and dma commands use dma */\n\tif (ata_is_dma(qc->tf.protocol) || ata_is_pio(qc->tf.protocol)) {\n\t\t/* Start the DMA */\n\t\tiowrite32(SGDMA_CONTROL_GO,\tpd->sgdma_base + SGDMA_CONTROL);\n\t\twmb();\n\t}\n\n\t/* enable End of command interrupt */\n\tiowrite32(INT_WANT, port_base + INT_ENABLE);\n\tiowrite32(COREINT_END, core_base + CORE_INT_ENABLE);\n\twmb();\n\n\t/* Start the command */\n\treg = ioread32(port_base + SATA_COMMAND);\n\treg &= ~SATA_OPCODE_MASK;\n\treg |= CMD_WRITE_TO_ORB_REGS;\n\tiowrite32(reg , port_base + SATA_COMMAND);\n\twmb();\n\n\treturn 0;\n}\n\n/**\n * Will schedule the libATA error handler on the premise that there has\n * been a hotplug event on the port specified\n */\nvoid sata_oxnas_checkforhotplug(struct ata_port *ap)\n{\n\tDPRINTK(\"ENTER\\n\");\n\n\tata_ehi_hotplugged(&ap->link.eh_info);\n\tata_port_freeze(ap);\n}\n\n\n/**************************************************************************/\n/* Locking                                                                */\n/**************************************************************************/\n/**\n * The underlying function that controls access to the sata core\n *\n * @return non-zero indicates that you have acquired exclusive access to the\n *         sata core.\n */\nstatic int __acquire_sata_core(\n\tstruct ata_host *ah,\n\tint port_no,\n\toxnas_sata_isr_callback_t callback,\n\tvoid                    *arg,\n\tint                      may_sleep,\n\tint                      timeout_jiffies,\n\tint                      hw_access,\n\tvoid                    *uid,\n\tint                      locker_type)\n{\n\tunsigned long end = jiffies + timeout_jiffies;\n\tint           acquired = 0;\n\tunsigned long flags;\n\tint           timed_out = 0;\n\tstruct sata_oxnas_host_priv *hd;\n\n\tDEFINE_WAIT(wait);\n\n\tif (!ah)\n\t\treturn acquired;\n\n\thd = ah->private_data;\n\n\tspin_lock_irqsave(&hd->core_lock, flags);\n\n\tDPRINTK(\"Entered uid %p, port %d, h/w count %d, d count %d, \"\n\t\t    \"callback %p, hw_access %d, core_locked %d, \"\n\t\t    \"reentrant_port_no %d, isr_callback %p\\n\",\n\t\tuid, port_no, hd->hw_lock_count, hd->direct_lock_count,\n\t\tcallback, hw_access, hd->core_locked, hd->reentrant_port_no,\n\t\thd->isr_callback);\n\n\twhile (!timed_out) {\n\t\tif (hd->core_locked ||\n\t\t    (!hw_access && hd->scsi_nonblocking_attempts)) {\n\t\t\t/* Can only allow access if from SCSI/SATA stack and if\n\t\t\t * reentrant access is allowed and this access is to the\n\t\t\t * same port for which the lock is current held\n\t\t\t */\n\t\t\tif (hw_access && (port_no == hd->reentrant_port_no)) {\n\t\t\t\tBUG_ON(!hd->hw_lock_count);\n\t\t\t\t++(hd->hw_lock_count);\n\n\t\t\t\tDPRINTK(\"Allow SCSI/SATA re-entrant access to \"\n\t\t\t\t\t\"uid %p port %d\\n\", uid, port_no);\n\t\t\t\tacquired = 1;\n\t\t\t\tbreak;\n\t\t\t} else if (!hw_access) {\n\t\t\t\tif ((locker_type == SATA_READER) &&\n\t\t\t\t    (hd->current_locker_type == SATA_READER)) {\n\t\t\t\t\tWARN(1,\n\t\t\t\t\t\t\"Already locked by reader, \"\n\t\t\t\t\t\t\"uid %p, locker_uid %p, \"\n\t\t\t\t\t\t\"port %d, h/w count %d, \"\n\t\t\t\t\t\t\"d count %d, hw_access %d\\n\",\n\t\t\t\t\t\tuid, hd->locker_uid, port_no,\n\t\t\t\t\t\thd->hw_lock_count,\n\t\t\t\t\t\thd->direct_lock_count,\n\t\t\t\t\t\thw_access);\n\t\t\t\t\tgoto check_uid;\n\t\t\t\t}\n\n\t\t\t\tif ((locker_type != SATA_READER) &&\n\t\t\t\t    (locker_type != SATA_WRITER)) {\n\t\t\t\t\tgoto wait_for_lock;\n\t\t\t\t}\n\ncheck_uid:\n\t\t\t\tWARN(uid == hd->locker_uid, \"Attempt to lock \"\n\t\t\t\t\t\"by locker type %d uid %p, already \"\n\t\t\t\t\t\"locked by locker type %d with \"\n\t\t\t\t\t\"locker_uid %p, port %d, \"\n\t\t\t\t\t\"h/w count %d, d count %d, \"\n\t\t\t\t\t\"hw_access %d\\n\", locker_type, uid,\n\t\t\t\t\thd->current_locker_type,\n\t\t\t\t\thd->locker_uid, port_no,\n\t\t\t\t\thd->hw_lock_count,\n\t\t\t\t\thd->direct_lock_count, hw_access);\n\t\t\t}\n\t\t} else {\n\t\t\tWARN(hd->hw_lock_count || hd->direct_lock_count,\n\t\t\t\t\"Core unlocked but counts non-zero: uid %p, \"\n\t\t\t\t\"locker_uid %p, port %d, h/w count %d, \"\n\t\t\t\t\"d count %d, hw_access %d\\n\", uid,\n\t\t\t\thd->locker_uid, port_no, hd->hw_lock_count,\n\t\t\t\thd->direct_lock_count, hw_access);\n\n\t\t\tBUG_ON(hd->current_locker_type != SATA_UNLOCKED);\n\n\t\t\tWARN(hd->locker_uid, \"Attempt to lock uid %p when \"\n\t\t\t\t\"locker_uid %p is non-zero,  port %d, \"\n\t\t\t\t\"h/w count %d, d count %d, hw_access %d\\n\",\n\t\t\t\tuid, hd->locker_uid, port_no, hd->hw_lock_count,\n\t\t\t\thd->direct_lock_count, hw_access);\n\n\t\t\tif (!hw_access) {\n\t\t\t\t/* Direct access attempting to acquire\n\t\t\t\t * non-contented lock\n\t\t\t\t */\n\t\t\t\t/* Must have callback for direct access */\n\t\t\t\tBUG_ON(!callback);\n\t\t\t\t/* Sanity check lock state */\n\t\t\t\tBUG_ON(hd->reentrant_port_no != -1);\n\n\t\t\t\thd->isr_callback = callback;\n\t\t\t\thd->isr_arg = arg;\n\t\t\t\t++(hd->direct_lock_count);\n\n\t\t\t\thd->current_locker_type = locker_type;\n\t\t\t} else {\n\t\t\t\t/* SCSI/SATA attempting to acquire\n\t\t\t\t * non-contented lock\n\t\t\t\t */\n\t\t\t\t/* No callbacks for SCSI/SATA access */\n\t\t\t\tBUG_ON(callback);\n\t\t\t\t/* No callback args for SCSI/SATA access */\n\t\t\t\tBUG_ON(arg);\n\n\t\t\t\t/* Sanity check lock state */\n\t\t\t\tBUG_ON(hd->isr_callback);\n\t\t\t\tBUG_ON(hd->isr_arg);\n\n\t\t\t\t++(hd->hw_lock_count);\n\t\t\t\thd->reentrant_port_no = port_no;\n\n\t\t\t\thd->current_locker_type = SATA_SCSI_STACK;\n\t\t\t}\n\n\t\t\thd->core_locked = 1;\n\t\t\thd->locker_uid = uid;\n\t\t\tacquired = 1;\n\t\t\tbreak;\n\t\t}\n\nwait_for_lock:\n\t\tif (!may_sleep) {\n\t\t\tDPRINTK(\"Denying for uid %p locker_type %d, \"\n\t\t\t\"hw_access %d, port %d, current_locker_type %d as \"\n\t\t\t\"cannot sleep\\n\", uid, locker_type, hw_access, port_no,\n\t\t\thd->current_locker_type);\n\n\t\t\tif (hw_access)\n\t\t\t\t++(hd->scsi_nonblocking_attempts);\n\n\t\t\tbreak;\n\t\t}\n\n\t\t/* Core is locked and we're allowed to sleep, so wait to be\n\t\t * awoken when the core is unlocked\n\t\t */\n\t\tfor (;;) {\n\t\t\tprepare_to_wait(hw_access ? &hd->scsi_wait_queue :\n\t\t\t\t\t\t    &hd->fast_wait_queue,\n\t\t\t\t\t&wait, TASK_UNINTERRUPTIBLE);\n\t\t\tif (!hd->core_locked &&\n\t\t\t    !(!hw_access && hd->scsi_nonblocking_attempts)) {\n\t\t\t\t/* We're going to use variables that will have\n\t\t\t\t * been changed by the waker prior to clearing\n\t\t\t\t * core_locked so we need to ensure we see\n\t\t\t\t * changes to all those variables\n\t\t\t\t */\n\t\t\t\tsmp_rmb();\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\tif (time_after(jiffies, end)) {\n\t\t\t\tprintk(KERN_WARNING \"__acquire_sata_core() \"\n\t\t\t\t\t\"uid %p failing for port %d timed out, \"\n\t\t\t\t\t\"locker_uid %p, h/w count %d, \"\n\t\t\t\t\t\"d count %d, callback %p, hw_access %d, \"\n\t\t\t\t\t\"core_locked %d, reentrant_port_no %d, \"\n\t\t\t\t\t\"isr_callback %p, isr_arg %p\\n\", uid,\n\t\t\t\t\tport_no, hd->locker_uid,\n\t\t\t\t\thd->hw_lock_count,\n\t\t\t\t\thd->direct_lock_count, callback,\n\t\t\t\t\thw_access, hd->core_locked,\n\t\t\t\t\thd->reentrant_port_no, hd->isr_callback,\n\t\t\t\t\thd->isr_arg);\n\t\t\t\ttimed_out = 1;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\tspin_unlock_irqrestore(&hd->core_lock, flags);\n\t\t\tif (!schedule_timeout(4*HZ)) {\n\t\t\t\tprintk(KERN_INFO \"__acquire_sata_core() uid %p, \"\n\t\t\t\t\t\"locker_uid %p, timed-out of \"\n\t\t\t\t\t\"schedule(), checking overall timeout\\n\",\n\t\t\t\t\tuid, hd->locker_uid);\n\t\t\t}\n\t\t\tspin_lock_irqsave(&hd->core_lock, flags);\n\t\t}\n\t\tfinish_wait(hw_access ? &hd->scsi_wait_queue :\n\t\t\t\t\t&hd->fast_wait_queue, &wait);\n\t}\n\n\tif (hw_access && acquired) {\n\t\tif (hd->scsi_nonblocking_attempts)\n\t\t\thd->scsi_nonblocking_attempts = 0;\n\n\t\t/* Wake any other SCSI/SATA waiters so they can get reentrant\n\t\t * access to the same port if appropriate. This is because if\n\t\t * the SATA core is locked by fast access, or SCSI/SATA access\n\t\t * to other port, then can have >1 SCSI/SATA waiters on the wait\n\t\t * list so want to give reentrant accessors a chance to get\n\t\t * access ASAP\n\t\t */\n\t\tif (!list_empty(&hd->scsi_wait_queue.head))\n\t\t\twake_up(&hd->scsi_wait_queue);\n\t}\n\n\tDPRINTK(\"Leaving uid %p with acquired = %d, port %d, callback %p\\n\",\n\t\tuid, acquired, port_no, callback);\n\n\tspin_unlock_irqrestore(&hd->core_lock, flags);\n\n\treturn acquired;\n}\n\nint sata_core_has_fast_waiters(struct ata_host *ah)\n{\n\tint has_waiters;\n\tunsigned long flags;\n\tstruct sata_oxnas_host_priv *hd = ah->private_data;\n\n\tspin_lock_irqsave(&hd->core_lock, flags);\n\thas_waiters = !list_empty(&hd->fast_wait_queue.head);\n\tspin_unlock_irqrestore(&hd->core_lock, flags);\n\n\treturn has_waiters;\n}\nEXPORT_SYMBOL(sata_core_has_fast_waiters);\n\nint sata_core_has_scsi_waiters(struct ata_host *ah)\n{\n\tint has_waiters;\n\tunsigned long flags;\n\tstruct sata_oxnas_host_priv *hd = ah->private_data;\n\n\tspin_lock_irqsave(&hd->core_lock, flags);\n\thas_waiters = hd->scsi_nonblocking_attempts ||\n\t\t      !list_empty(&hd->scsi_wait_queue.head);\n\tspin_unlock_irqrestore(&hd->core_lock, flags);\n\n\treturn has_waiters;\n}\nEXPORT_SYMBOL(sata_core_has_scsi_waiters);\n\n/*\n * ata_port operation to gain ownership of the SATA hardware prior to issuing\n * a command against a SATA host. Allows any number of users of the port against\n * which the lock was first acquired, thus enforcing that only one SATA core\n * port may be operated on at once.\n */\nstatic int sata_oxnas_acquire_hw(\n\tstruct ata_port *ap,\n\tint may_sleep,\n\tint timeout_jiffies)\n{\n\treturn __acquire_sata_core(ap->host, ap->port_no, NULL, 0, may_sleep,\n\t\t\t\t   timeout_jiffies, 1, (void *)HW_LOCKER_UID,\n\t\t\t\t   SATA_SCSI_STACK);\n}\n\n/*\n * operation to release ownership of the SATA hardware\n */\nstatic void sata_oxnas_release_hw(struct ata_port *ap)\n{\n\tunsigned long flags;\n\tint released = 0;\n\tstruct sata_oxnas_host_priv *hd = ap->host->private_data;\n\n\tspin_lock_irqsave(&hd->core_lock, flags);\n\n\tDPRINTK(\"Entered port_no = %d, h/w count %d, d count %d, \"\n\t\t\"core locked = %d, reentrant_port_no = %d, isr_callback %p\\n\",\n\t\tap->port_no, hd->hw_lock_count, hd->direct_lock_count,\n\t\thd->core_locked, hd->reentrant_port_no, hd->isr_callback);\n\n\tif (!hd->core_locked) {\n\t\t/* Nobody holds the SATA lock */\n\t\tprintk(KERN_WARNING \"Nobody holds SATA lock, port_no %d\\n\",\n\t\t       ap->port_no);\n\t\treleased = 1;\n\t} else if (!hd->hw_lock_count) {\n\t\t/* SCSI/SATA has released without holding the lock */\n\t\tprintk(KERN_WARNING \"SCSI/SATA does not hold SATA lock, \"\n\t\t       \"port_no %d\\n\", ap->port_no);\n\t} else {\n\t\t/* Trap incorrect usage */\n\t\tBUG_ON(hd->reentrant_port_no == -1);\n\t\tBUG_ON(ap->port_no != hd->reentrant_port_no);\n\t\tBUG_ON(hd->direct_lock_count);\n\t\tBUG_ON(hd->current_locker_type != SATA_SCSI_STACK);\n\n\t\tWARN(!hd->locker_uid || (hd->locker_uid != HW_LOCKER_UID),\n\t\t\t\"Invalid locker uid %p, h/w count %d, d count %d, \"\n\t\t\t\"reentrant_port_no %d, core_locked %d, \"\n\t\t\t\"isr_callback %p\\n\", hd->locker_uid, hd->hw_lock_count,\n\t\t\thd->direct_lock_count, hd->reentrant_port_no,\n\t\t\thd->core_locked, hd->isr_callback);\n\n\t\tif (--(hd->hw_lock_count)) {\n\t\t\tDPRINTK(\"Still nested port_no %d\\n\", ap->port_no);\n\t\t} else {\n\t\t\tDPRINTK(\"Release port_no %d\\n\", ap->port_no);\n\t\t\thd->reentrant_port_no = -1;\n\t\t\thd->isr_callback = NULL;\n\t\t\thd->current_locker_type = SATA_UNLOCKED;\n\t\t\thd->locker_uid = 0;\n\t\t\thd->core_locked = 0;\n\t\t\treleased = 1;\n\t\t\twake_up(!list_empty(&hd->scsi_wait_queue.head) ?\n\t\t\t\t\t\t&hd->scsi_wait_queue :\n\t\t\t\t\t\t&hd->fast_wait_queue);\n\t\t}\n\t}\n\n\tDPRINTK(\"Leaving, port_no %d, count %d\\n\", ap->port_no,\n\t\thd->hw_lock_count);\n\n\tspin_unlock_irqrestore(&hd->core_lock, flags);\n\n\t/* CONFIG_SATA_OX820_DIRECT_HWRAID */\n\t/*    if (released)\n\t     ox820hwraid_restart_queue();\n\t} */\n}\n\nstatic inline int sata_oxnas_is_host_frozen(struct ata_host *ah)\n{\n\tstruct sata_oxnas_host_priv *hd = ah->private_data;\n\n\tsmp_rmb();\n\treturn hd->port_in_eh || hd->port_frozen;\n}\n\n\nstatic inline u32 sata_oxnas_hostportbusy(struct ata_port *ap)\n{\n\tstruct sata_oxnas_host_priv *hd = ap->host->private_data;\n\n\treturn (ioread32(hd->port_base + SATA_COMMAND) & CMD_CORE_BUSY) ||\n\t       (hd->n_ports > 1 &&\n\t\t(ioread32(hd->port_base + PORT_SIZE + SATA_COMMAND) &\n\t\t CMD_CORE_BUSY));\n}\n\nstatic inline u32 sata_oxnas_hostdmabusy(struct ata_port *ap)\n{\n\tstruct sata_oxnas_port_priv *pd = ap->private_data;\n\n\treturn ioread32(pd->sgdma_base + SGDMA_STATUS) & SGDMA_BUSY;\n}\n\n\n/**\n * Turns on the cores clock and resets it\n */\nstatic void sata_oxnas_reset_core(struct ata_host *ah)\n{\n\tstruct sata_oxnas_host_priv *host_priv = ah->private_data;\n\tint n;\n\n\tDPRINTK(\"ENTER\\n\");\n\tclk_prepare_enable(host_priv->clk);\n\n\treset_control_assert(host_priv->rst_sata);\n\treset_control_assert(host_priv->rst_link);\n\treset_control_assert(host_priv->rst_phy);\n\n\tudelay(50);\n\n\t/* un-reset the PHY, then Link and Controller */\n\treset_control_deassert(host_priv->rst_phy);\n\tudelay(50);\n\n\treset_control_deassert(host_priv->rst_sata);\n\treset_control_deassert(host_priv->rst_link);\n\tudelay(50);\n\n\tworkaround5458(ah);\n\t/* tune for sata compatibility */\n\tsata_oxnas_link_write(ah->ports[0], 0x60, 0x2988);\n\n\tfor (n = 0; n < host_priv->n_ports; n++) {\n\t\t/* each port in turn */\n\t\tsata_oxnas_link_write(ah->ports[n], 0x70, 0x55629);\n\t}\n\tudelay(50);\n}\n\n\n/**\n * Called after an identify device command has worked out what kind of device\n * is on the port\n *\n * @param port The port to configure\n * @param pdev The hardware associated with controlling the port\n */\nstatic void sata_oxnas_dev_config(struct ata_device *pdev)\n{\n\tstruct sata_oxnas_port_priv *pd = pdev->link->ap->private_data;\n\tvoid __iomem *port_base = pd->port_base;\n\tu32 reg;\n\n\tDPRINTK(\"ENTER\\n\");\n\t/* Set the bits to put the port into 28 or 48-bit node */\n\treg = ioread32(port_base + DRIVE_CONTROL);\n\treg &= ~3;\n\treg |= (pdev->flags & ATA_DFLAG_LBA48) ? DR_CON_48 : DR_CON_28;\n\tiowrite32(reg, port_base + DRIVE_CONTROL);\n\n\t/* if this is an ATA-6 disk, put port into ATA-5 auto translate mode */\n\tif (pdev->flags & ATA_DFLAG_LBA48) {\n\t\treg = ioread32(port_base + PORT_CONTROL);\n\t\treg |= 2;\n\t\tiowrite32(reg, port_base + PORT_CONTROL);\n\t}\n}\n/**\n * called to write a taskfile into the ORB registers\n * @param ap hardware with the registers in\n * @param tf taskfile to write to the registers\n */\nstatic void sata_oxnas_tf_load(struct ata_port *ap,\n\t\t\t\tconst struct ata_taskfile *tf)\n{\n\tu32 count = 0;\n\tu32 Orb1 = 0;\n\tu32 Orb2 = 0;\n\tu32 Orb3 = 0;\n\tu32 Orb4 = 0;\n\tu32 Command_Reg;\n\n\tstruct sata_oxnas_port_priv *port_priv = ap->private_data;\n\tvoid __iomem *port_base = port_priv->port_base;\n\tunsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;\n\n\t/* wait a maximum of 10ms for the core to be idle */\n\tdo {\n\t\tCommand_Reg = ioread32(port_base + SATA_COMMAND);\n\t\tif (!(Command_Reg & CMD_CORE_BUSY))\n\t\t\tbreak;\n\t\tcount++;\n\t\tudelay(50);\n\t} while (count < 200);\n\n\t/* check if the ctl register has interrupts disabled or enabled and\n\t * modify the interrupt enable registers on the ata core as required */\n\tif (tf->ctl & ATA_NIEN) {\n\t\t/* interrupts disabled */\n\t\tu32 mask = (COREINT_END << ap->port_no);\n\n\t\tiowrite32(mask, port_priv->core_base + CORE_INT_DISABLE);\n\t\tsata_oxnas_irq_clear(ap);\n\t} else {\n\t\tsata_oxnas_irq_on(ap);\n\t}\n\n\tOrb2 |= (tf->command) << 24;\n\n\t/* write 48 or 28 bit tf parameters */\n\tif (is_addr) {\n\t\t/* set LBA bit as it's an address */\n\t\tOrb1 |= (tf->device & ATA_LBA) << 24;\n\n\t\tif (tf->flags & ATA_TFLAG_LBA48) {\n\t\t\tOrb1 |= ATA_LBA << 24;\n\t\t\tOrb2 |= (tf->hob_nsect) << 8;\n\t\t\tOrb3 |= (tf->hob_lbal) << 24;\n\t\t\tOrb4 |= (tf->hob_lbam) << 0;\n\t\t\tOrb4 |= (tf->hob_lbah) << 8;\n\t\t\tOrb4 |= (tf->hob_feature) << 16;\n\t\t} else {\n\t\t\tOrb3 |= (tf->device & 0xf) << 24;\n\t\t}\n\n\t\t/* write 28-bit lba */\n\t\tOrb2 |= (tf->nsect) << 0;\n\t\tOrb2 |= (tf->feature) << 16;\n\t\tOrb3 |= (tf->lbal) << 0;\n\t\tOrb3 |= (tf->lbam) << 8;\n\t\tOrb3 |= (tf->lbah) << 16;\n\t\tOrb4 |= (tf->ctl) << 24;\n\t}\n\n\tif (tf->flags & ATA_TFLAG_DEVICE)\n\t\tOrb1 |= (tf->device) << 24;\n\n\tap->last_ctl = tf->ctl;\n\n\t/* write values to registers */\n\tiowrite32(Orb1, port_base + ORB1);\n\tiowrite32(Orb2, port_base + ORB2);\n\tiowrite32(Orb3, port_base + ORB3);\n\tiowrite32(Orb4, port_base + ORB4);\n}\n\n\nvoid sata_oxnas_set_mode(struct ata_host *ah, u32 mode, u32 force)\n{\n\tstruct sata_oxnas_host_priv *host_priv = ah->private_data;\n\tvoid __iomem *core_base = host_priv->core_base;\n\n\tunsigned int *src;\n\tvoid __iomem *dst;\n\tunsigned int progmicrocode = 0;\n\tunsigned int changeparameters = 0;\n\n\tu32 previous_mode;\n\n\t/* these micro-code programs _should_ include the version word */\n\n\t/* JBOD */\n\tstatic const unsigned int jbod[] = {\n\t\t0x07B400AC, 0x0228A280, 0x00200001, 0x00204002, 0x00224001,\n\t\t0x00EE0009, 0x00724901, 0x01A24903, 0x00E40009, 0x00224001,\n\t\t0x00621120, 0x0183C908, 0x00E20005, 0x00718908, 0x0198A206,\n\t\t0x00621124, 0x0183C908, 0x00E20046, 0x00621104, 0x0183C908,\n\t\t0x00E20015, 0x00EE009D, 0x01A3E301, 0x00E2001B, 0x0183C900,\n\t\t0x00E2001B, 0x00210001, 0x00EE0020, 0x01A3E302, 0x00E2009D,\n\t\t0x0183C901, 0x00E2009D, 0x00210002, 0x0235D700, 0x0208A204,\n\t\t0x0071C908, 0x000F8207, 0x000FC207, 0x0071C920, 0x000F8507,\n\t\t0x000FC507, 0x0228A240, 0x02269A40, 0x00094004, 0x00621104,\n\t\t0x0180C908, 0x00E40031, 0x00621112, 0x01A3C801, 0x00E2002B,\n\t\t0x00294000, 0x0228A220, 0x01A69ABF, 0x002F8000, 0x002FC000,\n\t\t0x0198A204, 0x0001C022, 0x01B1A220, 0x0001C106, 0x00088007,\n\t\t0x0183C903, 0x00E2009D, 0x0228A220, 0x0071890C, 0x0208A206,\n\t\t0x0198A206, 0x0001C022, 0x01B1A220, 0x0001C106, 0x00088007,\n\t\t0x00EE009D, 0x00621104, 0x0183C908, 0x00E2004A, 0x00EE009D,\n\t\t0x01A3C901, 0x00E20050, 0x0021E7FF, 0x0183E007, 0x00E2009D,\n\t\t0x00EE0054, 0x0061600B, 0x0021E7FF, 0x0183C507, 0x00E2009D,\n\t\t0x01A3E301, 0x00E2005A, 0x0183C900, 0x00E2005A, 0x00210001,\n\t\t0x00EE005F, 0x01A3E302, 0x00E20005, 0x0183C901, 0x00E20005,\n\t\t0x00210002, 0x0235D700, 0x0208A204, 0x000F8109, 0x000FC109,\n\t\t0x0071C918, 0x000F8407, 0x000FC407, 0x0001C022, 0x01A1A2BF,\n\t\t0x0001C106, 0x00088007, 0x02269A40, 0x00094004, 0x00621112,\n\t\t0x01A3C801, 0x00E4007F, 0x00621104, 0x0180C908, 0x00E4008D,\n\t\t0x00621128, 0x0183C908, 0x00E2006C, 0x01A3C901, 0x00E2007B,\n\t\t0x0021E7FF, 0x0183E007, 0x00E2007F, 0x00EE006C, 0x0061600B,\n\t\t0x0021E7FF, 0x0183C507, 0x00E4006C, 0x00621111, 0x01A3C801,\n\t\t0x00E2007F, 0x00621110, 0x01A3C801, 0x00E20082, 0x0228A220,\n\t\t0x00621119, 0x01A3C801, 0x00E20086, 0x0001C022, 0x01B1A220,\n\t\t0x0001C106, 0x00088007, 0x0198A204, 0x00294000, 0x01A69ABF,\n\t\t0x002F8000, 0x002FC000, 0x0183C903, 0x00E20005, 0x0228A220,\n\t\t0x0071890C, 0x0208A206, 0x0198A206, 0x0001C022, 0x01B1A220,\n\t\t0x0001C106, 0x00088007, 0x00EE009D, 0x00621128, 0x0183C908,\n\t\t0x00E20005, 0x00621104, 0x0183C908, 0x00E200A6, 0x0062111C,\n\t\t0x0183C908, 0x00E20005, 0x0071890C, 0x0208A206, 0x0198A206,\n\t\t0x00718908, 0x0208A206, 0x00EE0005, ~0\n\t};\n\n\t/* Bi-Modal RAID-0/1 */\n\tstatic const unsigned int raid[] = {\n\t\t0x00F20145, 0x00EE20FA, 0x00EE20A7, 0x0001C009, 0x00EE0004,\n\t\t0x00220000, 0x0001000B, 0x037003FF, 0x00700018, 0x037003FE,\n\t\t0x037043FD, 0x00704118, 0x037043FC, 0x01A3D240, 0x00E20017,\n\t\t0x00B3C235, 0x00E40018, 0x0093C104, 0x00E80014, 0x0093C004,\n\t\t0x00E80017, 0x01020000, 0x00274020, 0x00EE0083, 0x0080C904,\n\t\t0x0093C104, 0x00EA0020, 0x0093C103, 0x00EC001F, 0x00220002,\n\t\t0x00924104, 0x0005C009, 0x00EE0058, 0x0093CF04, 0x00E80026,\n\t\t0x00900F01, 0x00600001, 0x00910400, 0x00EE0058, 0x00601604,\n\t\t0x01A00003, 0x00E2002C, 0x01018000, 0x00274040, 0x00EE0083,\n\t\t0x0093CF03, 0x00EC0031, 0x00220003, 0x00924F04, 0x0005C009,\n\t\t0x00810104, 0x00B3C235, 0x00E20037, 0x0022C000, 0x00218210,\n\t\t0x00EE0039, 0x0022C001, 0x00218200, 0x00600401, 0x00A04901,\n\t\t0x00604101, 0x01A0C401, 0x00E20040, 0x00216202, 0x00EE0041,\n\t\t0x00216101, 0x02018506, 0x00EE2141, 0x00904901, 0x00E20049,\n\t\t0x00A00401, 0x00600001, 0x02E0C301, 0x00EE2141, 0x00216303,\n\t\t0x037003EE, 0x01A3C001, 0x00E40105, 0x00250080, 0x00204000,\n\t\t0x002042F1, 0x0004C001, 0x00230001, 0x00100006, 0x02C18605,\n\t\t0x00100006, 0x01A3D502, 0x00E20055, 0x00EE0053, 0x00004009,\n\t\t0x00000004, 0x00B3C235, 0x00E40062, 0x0022C001, 0x0020C000,\n\t\t0x00EE2141, 0x0020C001, 0x00EE2141, 0x00EE006B, 0x0022C000,\n\t\t0x0060D207, 0x00EE2141, 0x00B3C242, 0x00E20069, 0x01A3D601,\n\t\t0x00E2006E, 0x02E0C301, 0x00EE2141, 0x00230001, 0x00301303,\n\t\t0x00EE007B, 0x00218210, 0x01A3C301, 0x00E20073, 0x00216202,\n\t\t0x00EE0074, 0x00216101, 0x02018506, 0x00214000, 0x037003EE,\n\t\t0x01A3C001, 0x00E40108, 0x00230001, 0x00100006, 0x00250080,\n\t\t0x00204000, 0x002042F1, 0x0004C001, 0x00EE007F, 0x0024C000,\n\t\t0x01A3D1F0, 0x00E20088, 0x00230001, 0x00300000, 0x01A3D202,\n\t\t0x00E20085, 0x00EE00A5, 0x00B3C800, 0x00E20096, 0x00218000,\n\t\t0x00924709, 0x0005C009, 0x00B20802, 0x00E40093, 0x037103FD,\n\t\t0x00710418, 0x037103FC, 0x00EE0006, 0x00220000, 0x0001000F,\n\t\t0x00EE0006, 0x00800B0C, 0x00B00001, 0x00204000, 0x00208550,\n\t\t0x00208440, 0x002083E0, 0x00208200, 0x00208100, 0x01008000,\n\t\t0x037083EE, 0x02008212, 0x02008216, 0x01A3C201, 0x00E400A5,\n\t\t0x0100C000, 0x00EE20FA, 0x02800000, 0x00208000, 0x00B24C00,\n\t\t0x00E400AD, 0x00224001, 0x00724910, 0x0005C009, 0x00B3CDC4,\n\t\t0x00E200D5, 0x00B3CD29, 0x00E200D5, 0x00B3CD20, 0x00E200D5,\n\t\t0x00B3CD24, 0x00E200D5, 0x00B3CDC5, 0x00E200D2, 0x00B3CD39,\n\t\t0x00E200D2, 0x00B3CD30, 0x00E200D2, 0x00B3CD34, 0x00E200D2,\n\t\t0x00B3CDCA, 0x00E200CF, 0x00B3CD35, 0x00E200CF, 0x00B3CDC8,\n\t\t0x00E200CC, 0x00B3CD25, 0x00E200CC, 0x00B3CD40, 0x00E200CB,\n\t\t0x00B3CD42, 0x00E200CB, 0x01018000, 0x00EE0083, 0x0025C000,\n\t\t0x036083EE, 0x0000800D, 0x00EE00D8, 0x036083EE, 0x00208035,\n\t\t0x00EE00DA, 0x036083EE, 0x00208035, 0x00EE00DA, 0x00208007,\n\t\t0x036083EE, 0x00208025, 0x036083EF, 0x02400000, 0x01A3D208,\n\t\t0x00E200D8, 0x0067120A, 0x0021C000, 0x0021C224, 0x00220000,\n\t\t0x00404B1C, 0x00600105, 0x00800007, 0x0020C00E, 0x00214000,\n\t\t0x01004000, 0x01A0411F, 0x00404E01, 0x01A3C101, 0x00E200F1,\n\t\t0x00B20800, 0x00E400D8, 0x00220001, 0x0080490B, 0x00B04101,\n\t\t0x0040411C, 0x00EE00E1, 0x02269A01, 0x01020000, 0x02275D80,\n\t\t0x01A3D202, 0x00E200F4, 0x01B75D80, 0x01030000, 0x01B69A01,\n\t\t0x00EE00D8, 0x01A3D204, 0x00E40104, 0x00224000, 0x0020C00E,\n\t\t0x0020001E, 0x00214000, 0x01004000, 0x0212490E, 0x00214001,\n\t\t0x01004000, 0x02400000, 0x00B3D702, 0x00E80112, 0x00EE010E,\n\t\t0x00B3D702, 0x00E80112, 0x00B3D702, 0x00E4010E, 0x00230001,\n\t\t0x00EE0140, 0x00200005, 0x036003EE, 0x00204001, 0x00EE0116,\n\t\t0x00230001, 0x00100006, 0x02C18605, 0x00100006, 0x01A3D1F0,\n\t\t0x00E40083, 0x037003EE, 0x01A3C002, 0x00E20121, 0x0020A300,\n\t\t0x0183D102, 0x00E20124, 0x037003EE, 0x01A00005, 0x036003EE,\n\t\t0x01A0910F, 0x00B3C20F, 0x00E2012F, 0x01A3D502, 0x00E20116,\n\t\t0x01A3C002, 0x00E20116, 0x00B3D702, 0x00E4012C, 0x00300000,\n\t\t0x00EE011F, 0x02C18605, 0x00100006, 0x00EE0116, 0x01A3D1F0,\n\t\t0x00E40083, 0x037003EE, 0x01A3C004, 0x00E20088, 0x00200003,\n\t\t0x036003EE, 0x01A3D502, 0x00E20136, 0x00230001, 0x00B3C101,\n\t\t0x00E4012C, 0x00100006, 0x02C18605, 0x00100006, 0x00204000,\n\t\t0x00EE0116, 0x00100006, 0x01A3D1F0, 0x00E40083, 0x01000000,\n\t\t0x02400000, ~0\n\t};\n\n\tDPRINTK(\"ENTER: mode:%d, force:%d\\n\", mode, force);\n\n\tif (force)\n\t\tprevious_mode = UNKNOWN_MODE;\n\telse\n\t\tprevious_mode = host_priv->current_ucode;\n\n\tif (mode == previous_mode)\n\t\treturn;\n\n\thost_priv->current_ucode = mode;\n\n\t/* decide what needs to be done using the STD in my logbook */\n\tswitch (previous_mode) {\n\tcase OXNASSATA_RAID1:\n\t\tswitch (mode) {\n\t\tcase OXNASSATA_RAID0:\n\t\t\tchangeparameters = 1;\n\t\t\tbreak;\n\t\tcase OXNASSATA_NOTRAID:\n\t\t\tchangeparameters = 1;\n\t\t\tprogmicrocode = 1;\n\t\t\tbreak;\n\t\t}\n\t\tbreak;\n\tcase OXNASSATA_RAID0:\n\t\tswitch (mode) {\n\t\tcase OXNASSATA_RAID1:\n\t\t\tchangeparameters = 1;\n\t\t\tbreak;\n\t\tcase OXNASSATA_NOTRAID:\n\t\t\tchangeparameters = 1;\n\t\t\tprogmicrocode = 1;\n\t\t\tbreak;\n\t\t}\n\t\tbreak;\n\tcase OXNASSATA_NOTRAID:\n\t\tswitch (mode) {\n\t\tcase OXNASSATA_RAID0:\n\t\tcase OXNASSATA_RAID1:\n\t\t\tchangeparameters = 1;\n\t\t\tprogmicrocode = 1;\n\t\t\tbreak;\n\t\t}\n\t\tbreak;\n\tcase UNKNOWN_MODE:\n\t\tchangeparameters = 1;\n\t\tprogmicrocode = 1;\n\t\tbreak;\n\t}\n\n\t/* no need to reprogram everything if already in the right mode */\n\tif (progmicrocode) {\n\t\t/* reset micro-code processor */\n\t\tiowrite32(1, core_base + PROC_RESET);\n\t\twmb();\n\n\t\t/* select micro-code */\n\t\tswitch (mode) {\n\t\tcase OXNASSATA_RAID1:\n\t\tcase OXNASSATA_RAID0:\n\t\t\tVPRINTK(\"Loading RAID micro-code\\n\");\n\t\t\tsrc = (unsigned int *)&raid[1];\n\t\t\tbreak;\n\t\tcase OXNASSATA_NOTRAID:\n\t\t\tVPRINTK(\"Loading JBOD micro-code\\n\");\n\t\t\tsrc = (unsigned int *)&jbod[1];\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tBUG();\n\t\t\tbreak;\n\t\t}\n\n\t\t/* load micro code */\n\t\tdst = core_base + UCODE_STORE;\n\t\twhile (*src != ~0) {\n\t\t\tiowrite32(*src, dst);\n\t\t\tsrc++;\n\t\t\tdst += sizeof(*src);\n\t\t}\n\t\twmb();\n\t}\n\n\tif (changeparameters) {\n\t\tu32 reg;\n\t\t/* set other mode dependent flags */\n\t\tswitch (mode) {\n\t\tcase OXNASSATA_RAID1:\n\t\t\t/* clear JBOD mode */\n\t\t\treg = ioread32(core_base + DATA_PLANE_CTRL);\n\t\t\treg |= DPC_JBOD_UCODE;\n\t\t\treg &= ~DPC_FIS_SWCH;\n\t\t\tiowrite32(reg, core_base + DATA_PLANE_CTRL);\n\t\t\twmb();\n\n\t\t\t/* set the hardware up for RAID-1 */\n\t\t\tiowrite32(0, core_base + RAID_WP_BOT_LOW);\n\t\t\tiowrite32(0, core_base + RAID_WP_BOT_HIGH);\n\t\t\tiowrite32(0xffffffff, core_base + RAID_WP_TOP_LOW);\n\t\t\tiowrite32(0x7fffffff, core_base + RAID_WP_TOP_HIGH);\n\t\t\tiowrite32(0, core_base + RAID_SIZE_LOW);\n\t\t\tiowrite32(0, core_base + RAID_SIZE_HIGH);\n\t\t\twmb();\n\t\t\tbreak;\n\t\tcase OXNASSATA_RAID0:\n\t\t\t/* clear JBOD mode */\n\t\t\treg = ioread32(core_base + DATA_PLANE_CTRL);\n\t\t\treg |= DPC_JBOD_UCODE;\n\t\t\treg &= ~DPC_FIS_SWCH;\n\t\t\tiowrite32(reg, core_base + DATA_PLANE_CTRL);\n\t\t\twmb();\n\n\t\t\t/* set the hardware up for RAID-1 */\n\t\t\tiowrite32(0, core_base + RAID_WP_BOT_LOW);\n\t\t\tiowrite32(0, core_base + RAID_WP_BOT_HIGH);\n\t\t\tiowrite32(0xffffffff, core_base + RAID_WP_TOP_LOW);\n\t\t\tiowrite32(0x7fffffff, core_base + RAID_WP_TOP_HIGH);\n\t\t\tiowrite32(0xffffffff, core_base + RAID_SIZE_LOW);\n\t\t\tiowrite32(0x7fffffff, core_base + RAID_SIZE_HIGH);\n\t\t\twmb();\n\t\t\tbreak;\n\t\tcase OXNASSATA_NOTRAID:\n\t\t\t/* enable jbod mode */\n\t\t\treg = ioread32(core_base + DATA_PLANE_CTRL);\n\t\t\treg &= ~DPC_JBOD_UCODE;\n\t\t\treg &= ~DPC_FIS_SWCH;\n\t\t\tiowrite32(reg, core_base + DATA_PLANE_CTRL);\n\t\t\twmb();\n\n\t\t\t/* start micro-code processor*/\n\t\t\tiowrite32(1, core_base + PROC_START);\n\t\t\tbreak;\n\t\tdefault:\n\t\t\treg = ioread32(core_base + DATA_PLANE_CTRL);\n\t\t\treg |= DPC_JBOD_UCODE;\n\t\t\treg &= ~DPC_FIS_SWCH;\n\t\t\tiowrite32(reg, core_base + DATA_PLANE_CTRL);\n\t\t\twmb();\n\t\t\tbreak;\n\t\t}\n\t}\n}\n\n/**\n * sends a sync-escape if there is a link present\n */\nstatic inline void sata_oxnas_send_sync_escape(struct ata_port *ap)\n{\n\tstruct sata_oxnas_port_priv *pd = ap->private_data;\n\tu32 reg;\n\n\t/* read the SSTATUS register and only send a sync escape if there is a\n\t* link active */\n\tif ((sata_oxnas_link_read(ap, 0x20) & 3) == 3) {\n\t\treg = ioread32(pd->port_base + SATA_COMMAND);\n\t\treg &= ~SATA_OPCODE_MASK;\n\t\treg |= CMD_SYNC_ESCAPE;\n\t\tiowrite32(reg, pd->port_base + SATA_COMMAND);\n\t}\n}\n\n/* clears errors */\nstatic inline void sata_oxnas_clear_CS_error(struct ata_port *ap)\n{\n\tstruct sata_oxnas_port_priv *pd = ap->private_data;\n\tu32 *base = pd->port_base;\n\tu32 reg;\n\n\treg = ioread32(base + SATA_CONTROL);\n\treg &= SATA_CTL_ERR_MASK;\n\tiowrite32(reg, base + SATA_CONTROL);\n}\n\nstatic inline void sata_oxnas_reset_sgdma(struct ata_port *ap)\n{\n\tstruct sata_oxnas_port_priv *pd = ap->private_data;\n\n\tiowrite32(SGDMA_RESETS_CTRL, pd->sgdma_base + SGDMA_RESETS);\n}\n\nstatic inline void sata_oxnas_reset_dma(struct ata_port *ap, int assert)\n{\n\tstruct sata_oxnas_port_priv *pd = ap->private_data;\n\tu32 reg;\n\n\treg = ioread32(pd->dmactl_base + DMA_CONTROL);\n\tif (assert)\n\t\treg |= DMA_CONTROL_RESET;\n\telse\n\t\treg &= ~DMA_CONTROL_RESET;\n\n\tiowrite32(reg, pd->dmactl_base + DMA_CONTROL);\n};\n\n/**\n * Clears the error caused by the core's registers being accessed when the\n * core is busy.\n */\nstatic inline void sata_oxnas_clear_reg_access_error(struct ata_port *ap)\n{\n\tstruct sata_oxnas_port_priv *pd = ap->private_data;\n\tu32 *base = pd->port_base;\n\tu32 reg;\n\n\treg = ioread32(base + INT_STATUS);\n\n\tDPRINTK(\"ENTER\\n\");\n\tif (reg & INT_REG_ACCESS_ERR) {\n\t\tDPRINTK(\"clearing register access error on port %d\\n\",\n\t\t\tap->port_no);\n\t\tiowrite32(INT_REG_ACCESS_ERR, base + INT_STATUS);\n\t}\n\treg = ioread32(base + INT_STATUS);\n\tif (reg & INT_REG_ACCESS_ERR)\n\t\tDPRINTK(\"register access error didn't clear\\n\");\n}\n\nstatic inline void sata_oxnas_clear_sctl_error(struct ata_port *ap)\n{\n\tstruct sata_oxnas_port_priv *pd = ap->private_data;\n\tu32 *base = pd->port_base;\n\tu32 reg;\n\n\treg = ioread32(base + SATA_CONTROL);\n\treg |= SCTL_CLR_ERR;\n\tiowrite32(reg, base + SATA_CONTROL);\n}\n\nstatic inline void sata_oxnas_clear_raid_error(struct ata_host *ah)\n{\n\treturn;\n};\n\n/**\n * Clean up all the state machines in the sata core.\n * @return post cleanup action required\n */\nstatic int sata_oxnas_cleanup(struct ata_host *ah)\n{\n\tstruct sata_oxnas_host_priv *hd = ah->private_data;\n\tint actions_required = 0;\n\tint n;\n\n\tprintk(KERN_INFO \"sata_oxnas: resetting SATA core\\n\");\n\t/* core not recovering, reset it */\n\tmdelay(5);\n\tsata_oxnas_reset_core(ah);\n\tmdelay(5);\n\tactions_required |= OXNAS_SATA_REINIT;\n\t/* Perform any SATA core re-initialisation after reset post reset init\n\t * needs to be called for both ports as there's one reset for both\n\t * ports */\n\tfor (n = 0; n < hd->n_ports; n++)\n\t\tsata_oxnas_post_reset_init(ah->ports[n]);\n\n\n\treturn actions_required;\n}\n\n/**\n *  ata_qc_new - Request an available ATA command, for queueing\n *  @ap: Port associated with device @dev\n *  @return non zero will refuse a new command, zero will may grant on subject\n *          to conditions elsewhere.\n *\n */\nstatic int sata_oxnas_qc_new(struct ata_port *ap)\n{\n\tstruct sata_oxnas_host_priv *hd = ap->host->private_data;\n\n\tDPRINTK(\"port %d\\n\", ap->port_no);\n\tsmp_rmb();\n\tif (hd->port_frozen || hd->port_in_eh)\n\t\treturn 1;\n\telse\n\t\treturn !sata_oxnas_acquire_hw(ap, 0, 0);\n}\n\n/**\n * releases the lock on the port the command used\n */\nstatic void sata_oxnas_qc_free(struct ata_queued_cmd *qc)\n{\n\tDPRINTK(\"\\n\");\n\tsata_oxnas_release_hw(qc->ap);\n}\n\nstatic void sata_oxnas_freeze(struct ata_port *ap)\n{\n\tstruct sata_oxnas_host_priv *hd = ap->host->private_data;\n\n\tDPRINTK(\"\\n\");\n\thd->port_frozen |= BIT(ap->port_no);\n\tsmp_wmb();\n}\n\nstatic void sata_oxnas_thaw(struct ata_port *ap)\n{\n\tstruct sata_oxnas_host_priv *hd = ap->host->private_data;\n\n\tDPRINTK(\"\\n\");\n\thd->port_frozen &= ~BIT(ap->port_no);\n\tsmp_wmb();\n}\n\nvoid sata_oxnas_freeze_host(struct ata_port *ap)\n{\n\tstruct sata_oxnas_host_priv *hd = ap->host->private_data;\n\n\tDPRINTK(\"ENTER\\n\");\n\thd->port_in_eh |= BIT(ap->port_no);\n\tsmp_wmb();\n}\n\nvoid sata_oxnas_thaw_host(struct ata_port *ap)\n{\n\tstruct sata_oxnas_host_priv *hd = ap->host->private_data;\n\n\tDPRINTK(\"ENTER\\n\");\n\thd->port_in_eh &= ~BIT(ap->port_no);\n\tsmp_wmb();\n}\n\nstatic void sata_oxnas_post_internal_cmd(struct ata_queued_cmd *qc)\n{\n\tDPRINTK(\"ENTER\\n\");\n\t/* If the core is busy here, make it idle */\n\tif (qc->flags & ATA_QCFLAG_FAILED)\n\t\tsata_oxnas_cleanup(qc->ap->host);\n}\n\n\n/**\n * turn on the interrupts\n *\n * @param ap Hardware with the registers in\n */\nstatic void sata_oxnas_irq_on(struct ata_port *ap)\n{\n\tstruct sata_oxnas_port_priv *pd = ap->private_data;\n\tu32 mask = (COREINT_END << ap->port_no);\n\n\t/* Clear pending interrupts */\n\tiowrite32(~0, pd->port_base + INT_CLEAR);\n\tiowrite32(mask, pd->core_base + CORE_INT_STATUS);\n\twmb();\n\n\t/* enable End of command interrupt */\n\tiowrite32(INT_WANT, pd->port_base + INT_ENABLE);\n\tiowrite32(mask, pd->core_base + CORE_INT_ENABLE);\n}\n\n\n/** @return true if the port has a cable connected */\nint sata_oxnas_check_link(struct ata_port *ap)\n{\n\tint reg;\n\n\tsata_oxnas_scr_read_port(ap, SCR_STATUS, &reg);\n\t/* Check for the cable present indicated by SCR status bit-0 set */\n\treturn reg & 0x1;\n}\n\n/**\n *\tata_std_postreset - standard postreset callback\n *\t@link: the target ata_link\n *\t@classes: classes of attached devices\n *\n *\tThis function is invoked after a successful reset. Note that\n *\tthe device might have been reset more than once using\n *\tdifferent reset methods before postreset is invoked.\n *\n *\tLOCKING:\n *\tKernel thread context (may sleep)\n */\nstatic void sata_oxnas_postreset(struct ata_link *link, unsigned int *classes)\n{\n\tstruct ata_port *ap = link->ap;\n\tstruct sata_oxnas_host_priv *hd = ap->host->private_data;\n\n\tunsigned int dev;\n\n\tDPRINTK(\"ENTER\\n\");\n\tata_std_postreset(link, classes);\n\n\t/* turn on phy error detection by removing the masks */\n\tsata_oxnas_link_write(ap->host->ports[0], 0x0c, 0x30003);\n\tif (hd->n_ports > 1)\n\t\tsata_oxnas_link_write(ap->host->ports[1], 0x0c, 0x30003);\n\n\t/* bail out if no device is present */\n\tif (classes[0] == ATA_DEV_NONE && classes[1] == ATA_DEV_NONE) {\n\t\tDPRINTK(\"EXIT, no device\\n\");\n\t\treturn;\n\t}\n\n\t/* go through all the devices and configure them */\n\tfor (dev = 0; dev < ATA_MAX_DEVICES; ++dev) {\n\t\tif (ap->link.device[dev].class == ATA_DEV_ATA)\n\t\t\tsata_oxnas_dev_config(&(ap->link.device[dev]));\n\t}\n\n\tDPRINTK(\"EXIT\\n\");\n}\n\n/**\n * Called to read the hardware registers / DMA buffers, to\n * obtain the current set of taskfile register values.\n * @param ap hardware with the registers in\n * @param tf taskfile to read the registers into\n */\nstatic void sata_oxnas_tf_read(struct ata_port *ap, struct ata_taskfile *tf)\n{\n\tstruct sata_oxnas_port_priv *port_priv = ap->private_data;\n\tvoid __iomem *port_base = port_priv->port_base;\n\t/* read the orb registers */\n\tu32 Orb1 = ioread32(port_base + ORB1);\n\tu32 Orb2 = ioread32(port_base + ORB2);\n\tu32 Orb3 = ioread32(port_base + ORB3);\n\tu32 Orb4 = ioread32(port_base + ORB4);\n\n\t/* read common 28/48 bit tf parameters */\n\ttf->device = (Orb1 >> 24);\n\ttf->nsect = (Orb2 >> 0);\n\ttf->feature = (Orb2 >> 16);\n\ttf->command = sata_oxnas_check_status(ap);\n\n\t/* read 48 or 28 bit tf parameters */\n\tif (tf->flags & ATA_TFLAG_LBA48) {\n\t\ttf->hob_nsect = (Orb2 >> 8);\n\t\ttf->lbal = (Orb3 >> 0);\n\t\ttf->lbam = (Orb3 >> 8);\n\t\ttf->lbah = (Orb3 >> 16);\n\t\ttf->hob_lbal = (Orb3 >> 24);\n\t\ttf->hob_lbam = (Orb4 >> 0);\n\t\ttf->hob_lbah = (Orb4 >> 8);\n\t\t/* feature ext and control are write only */\n\t} else {\n\t\t/* read 28-bit lba */\n\t\ttf->lbal = (Orb3 >> 0);\n\t\ttf->lbam = (Orb3 >> 8);\n\t\ttf->lbah = (Orb3 >> 16);\n\t}\n}\n\n/**\n * Read a result task-file from the sata core registers.\n */\nstatic bool sata_oxnas_qc_fill_rtf(struct ata_queued_cmd *qc)\n{\n\t/* Read the most recently received FIS from the SATA core ORB registers\n\t and convert to an ATA taskfile */\n\tsata_oxnas_tf_read(qc->ap, &qc->result_tf);\n\treturn true;\n}\n\n/**\n * Reads the Status ATA shadow register from hardware.\n *\n * @return The status register\n */\nstatic u8 sata_oxnas_check_status(struct ata_port *ap)\n{\n\tu32 Reg;\n\tu8 status;\n\tstruct sata_oxnas_port_priv *port_priv = ap->private_data;\n\tvoid __iomem *port_base = port_priv->port_base;\n\n\t/* read byte 3 of Orb2 register */\n\tstatus = ioread32(port_base + ORB2) >> 24;\n\n\t/* check for the drive going missing indicated by SCR status bits\n\t * 0-3 = 0 */\n\tsata_oxnas_scr_read_port(ap, SCR_STATUS, &Reg);\n\n\tif (!(Reg & 0x1)) {\n\t\tstatus |= ATA_DF;\n\t\tstatus |= ATA_ERR;\n\t}\n\n\treturn status;\n}\n\nstatic inline void sata_oxnas_reset_ucode(struct ata_host *ah, int force,\n\t\t\t\t\t  int no_microcode)\n{\n\tstruct sata_oxnas_host_priv *hd = ah->private_data;\n\n\tDPRINTK(\"ENTER\\n\");\n\tif (no_microcode) {\n\t\tu32 reg;\n\n\t\tsata_oxnas_set_mode(ah, UNKNOWN_MODE, force);\n\t\treg = ioread32(hd->core_base + DEVICE_CONTROL);\n\t\treg |= DEVICE_CONTROL_ATA_ERR_OVERRIDE;\n\t\tiowrite32(reg, hd->core_base + DEVICE_CONTROL);\n\t} else {\n\t\t/* JBOD uCode */\n\t\tsata_oxnas_set_mode(ah, OXNASSATA_NOTRAID, force);\n\t\t/* Turn the work around off as it may have been left on by any\n\t\t * HW-RAID code that we've been working with */\n\t\tiowrite32(0x0, hd->core_base + PORT_ERROR_MASK);\n\t}\n}\n\n/**\n * Prepare as much as possible for a command without involving anything that is\n * shared between ports.\n */\nstatic enum ata_completion_errors sata_oxnas_qc_prep(struct ata_queued_cmd *qc)\n{\n\tstruct sata_oxnas_port_priv *pd;\n\tint port_no = qc->ap->port_no;\n\n\t/* if the port's not connected, complete now with an error */\n\tif (!sata_oxnas_check_link(qc->ap)) {\n\t\tata_port_err(qc->ap,\n\t\t\t\"port %d not connected completing with error\\n\",\n\t\t\tport_no);\n\t\tqc->err_mask |= AC_ERR_ATA_BUS;\n\t\tata_qc_complete(qc);\n\t}\n\n\tsata_oxnas_reset_ucode(qc->ap->host, 0, 0);\n\n\t/* both pio and dma commands use dma */\n\tif (ata_is_dma(qc->tf.protocol) || ata_is_pio(qc->tf.protocol)) {\n\n\t\t/* program the scatterlist into the prd table */\n\t\tata_bmdma_qc_prep(qc);\n\n\t\t/* point the sgdma controller at the dma request structure */\n\t\tpd = qc->ap->private_data;\n\n\t\tiowrite32(pd->sgdma_request_pa,\n\t\t\t\tpd->sgdma_base + SGDMA_REQUESTPTR);\n\n\t\t/* setup the request table */\n\t\tif (port_no == 0) {\n\t\t\tpd->sgdma_request->control =\n\t\t\t\t(qc->dma_dir == DMA_FROM_DEVICE) ?\n\t\t\t\t\tSGDMA_REQCTL0IN : SGDMA_REQCTL0OUT;\n\t\t} else {\n\t\t\tpd->sgdma_request->control =\n\t\t\t\t(qc->dma_dir == DMA_FROM_DEVICE) ?\n\t\t\t\t\tSGDMA_REQCTL1IN : SGDMA_REQCTL1OUT;\n\t\t}\n\t\tpd->sgdma_request->qualifier = SGDMA_REQQUAL;\n\t\tpd->sgdma_request->src_pa = qc->ap->bmdma_prd_dma;\n\t\tpd->sgdma_request->dst_pa = qc->ap->bmdma_prd_dma;\n\t\tsmp_wmb();\n\n\t\t/* tell it to wait */\n\t\tiowrite32(SGDMA_CONTROL_NOGO, pd->sgdma_base + SGDMA_CONTROL);\n\t}\n\n\treturn AC_ERR_OK;\n}\n\nstatic int sata_oxnas_port_start(struct ata_port *ap)\n{\n\tstruct sata_oxnas_host_priv *host_priv = ap->host->private_data;\n\tstruct device *dev = ap->host->dev;\n\tstruct sata_oxnas_port_priv *pp;\n\tvoid *mem;\n\tdma_addr_t mem_dma;\n\n\tDPRINTK(\"ENTER\\n\");\n\n\tpp = kzalloc(sizeof(*pp), GFP_KERNEL);\n\tif (!pp)\n\t\treturn -ENOMEM;\n\n\tpp->port_base = host_priv->port_base +\n\t\t\t(ap->port_no ? PORT_SIZE : 0);\n\tpp->dmactl_base = host_priv->dmactl_base +\n\t\t\t (ap->port_no ? DMA_CORESIZE : 0);\n\tpp->sgdma_base = host_priv->sgdma_base +\n\t\t\t (ap->port_no ? SGDMA_CORESIZE : 0);\n\tpp->core_base = host_priv->core_base;\n\n\t/* preallocated */\n\tif (host_priv->dma_size >= SATA_OXNAS_DMA_SIZE * host_priv->n_ports) {\n\t\tDPRINTK(\"using preallocated DMA\\n\");\n\t\tmem_dma = host_priv->dma_base +\n\t\t\t\t(ap->port_no ? SATA_OXNAS_DMA_SIZE : 0);\n\t\tmem = ioremap(mem_dma, SATA_OXNAS_DMA_SIZE);\n\t} else {\n\t\tmem = dma_alloc_coherent(dev, SATA_OXNAS_DMA_SIZE, &mem_dma,\n\t\t\t\t\t GFP_KERNEL);\n\t}\n\tif (!mem)\n\t\tgoto err_ret;\n\n\tpp->sgdma_request_pa = mem_dma;\n\tpp->sgdma_request = mem;\n\n\tap->bmdma_prd_dma = mem_dma + sizeof(struct sgdma_request);\n\tap->bmdma_prd = mem + sizeof(struct sgdma_request);\n\n\tap->private_data = pp;\n\n\tsata_oxnas_post_reset_init(ap);\n\n\treturn 0;\n\nerr_ret:\n\tkfree(pp);\n\treturn -ENOMEM;\n\n}\n\nstatic void sata_oxnas_port_stop(struct ata_port *ap)\n{\n\tstruct device *dev = ap->host->dev;\n\tstruct sata_oxnas_port_priv *pp = ap->private_data;\n\tstruct sata_oxnas_host_priv *host_priv = ap->host->private_data;\n\n\tDPRINTK(\"ENTER\\n\");\n\tap->private_data = NULL;\n\tif (host_priv->dma_size) {\n\t\tiounmap(pp->sgdma_request);\n\t} else {\n\t\tdma_free_coherent(dev, SATA_OXNAS_DMA_SIZE,\n\t\t\t\t  pp->sgdma_request, pp->sgdma_request_pa);\n\t}\n\n\tkfree(pp);\n}\n\n\nstatic void sata_oxnas_post_reset_init(struct ata_port *ap)\n{\n\tuint dev;\n\n\t/* force to load u-code only once after reset */\n\tsata_oxnas_reset_ucode(ap->host, !ap->port_no, 0);\n\n\t/* turn on phy error detection by removing the masks */\n\tsata_oxnas_link_write(ap, 0x0C, 0x30003);\n\n\t/* enable hotplug event detection */\n\tsata_oxnas_scr_write_port(ap, SCR_ERROR, ~0);\n\tsata_oxnas_scr_write_port(ap, SERROR_IRQ_MASK, 0x03feffff);\n\tsata_oxnas_scr_write_port(ap, SCR_ACTIVE, ~0 & ~(1 << 26) & ~(1 << 16));\n\n\t/* enable interrupts for ports */\n\tsata_oxnas_irq_on(ap);\n\n\t/* go through all the devices and configure them */\n\tfor (dev = 0; dev < ATA_MAX_DEVICES; ++dev) {\n\t\tif (ap->link.device[dev].class == ATA_DEV_ATA) {\n\t\t\tsata_std_hardreset(&ap->link, NULL, jiffies + HZ);\n\t\t\tsata_oxnas_dev_config(&(ap->link.device[dev]));\n\t\t}\n\t}\n\n\t/* clean up any remaining errors */\n\tsata_oxnas_scr_write_port(ap, SCR_ERROR, ~0);\n\tVPRINTK(\"done\\n\");\n}\n\n/**\n * host_stop() is called when the rmmod or hot unplug process begins. The\n * hook must stop all hardware interrupts, DMA engines, etc.\n *\n * @param ap hardware with the registers in\n */\nstatic void sata_oxnas_host_stop(struct ata_host *host_set)\n{\n\tDPRINTK(\"\\n\");\n}\n\n\n#define ERROR_HW_ACQUIRE_TIMEOUT_JIFFIES (10 * HZ)\nstatic void sata_oxnas_error_handler(struct ata_port *ap)\n{\n\tDPRINTK(\"Enter port_no %d\\n\", ap->port_no);\n\tsata_oxnas_freeze_host(ap);\n\n\t/* If the core is busy here, make it idle */\n\tsata_oxnas_cleanup(ap->host);\n\n\tata_std_error_handler(ap);\n\n\tsata_oxnas_thaw_host(ap);\n}\n\nstatic int sata_oxnas_softreset(struct ata_link *link, unsigned int *class,\n\t\t\t\t unsigned long deadline)\n{\n\tstruct ata_port *ap = link->ap;\n\tstruct sata_oxnas_port_priv *pd = ap->private_data;\n\tvoid __iomem *port_base = pd->port_base;\n\tint rc;\n\n\tstruct ata_taskfile tf;\n\tu32 Command_Reg;\n\n\tDPRINTK(\"ENTER\\n\");\n\n\tport_base = pd->port_base;\n\n\tif (ata_link_offline(link)) {\n\t\tDPRINTK(\"PHY reports no device\\n\");\n\t\t*class = ATA_DEV_NONE;\n\t\tgoto out;\n\t}\n\n\t/* write value to register */\n\tiowrite32(0, port_base + ORB1);\n\tiowrite32(0, port_base + ORB2);\n\tiowrite32(0, port_base + ORB3);\n\tiowrite32((ap->ctl) << 24, port_base + ORB4);\n\n\t/* command the core to send a control FIS */\n\tCommand_Reg = ioread32(port_base + SATA_COMMAND);\n\tCommand_Reg &= ~SATA_OPCODE_MASK;\n\tCommand_Reg |= CMD_WRITE_TO_ORB_REGS_NO_COMMAND;\n\tiowrite32(Command_Reg, port_base + SATA_COMMAND);\n\tudelay(20);\t/* FIXME: flush */\n\n\t/* write value to register */\n\tiowrite32((ap->ctl | ATA_SRST) << 24, port_base + ORB4);\n\n\t/* command the core to send a control FIS */\n\tCommand_Reg &= ~SATA_OPCODE_MASK;\n\tCommand_Reg |= CMD_WRITE_TO_ORB_REGS_NO_COMMAND;\n\tiowrite32(Command_Reg, port_base + SATA_COMMAND);\n\tudelay(20);\t/* FIXME: flush */\n\n\t/* write value to register */\n\tiowrite32((ap->ctl) << 24, port_base + ORB4);\n\n\t/* command the core to send a control FIS */\n\tCommand_Reg &= ~SATA_OPCODE_MASK;\n\tCommand_Reg |= CMD_WRITE_TO_ORB_REGS_NO_COMMAND;\n\tiowrite32(Command_Reg, port_base + SATA_COMMAND);\n\n\tmsleep(150);\n\n\trc = ata_sff_wait_ready(link, deadline);\n\n\t/* if link is occupied, -ENODEV too is an error */\n\tif (rc && (rc != -ENODEV || sata_scr_valid(link))) {\n\t\tata_link_printk(link, KERN_ERR, \"SRST failed (errno=%d)\\n\", rc);\n\t\treturn rc;\n\t}\n\n\t/* determine by signature whether we have ATA or ATAPI devices */\n\tsata_oxnas_tf_read(ap, &tf);\n\t*class = ata_dev_classify(&tf);\n\n\tif (*class == ATA_DEV_UNKNOWN)\n\t\t*class = ATA_DEV_NONE;\n\nout:\n\tDPRINTK(\"EXIT, class=%u\\n\", *class);\n\treturn 0;\n}\n\n\nint\tsata_oxnas_init_controller(struct ata_host *host)\n{\n\treturn 0;\n}\n\n/**\n * Ref bug-6320\n *\n * This code is a work around for a DMA hardware bug that will repeat the\n * penultimate 8-bytes on some reads. This code will check that the amount\n * of data transferred is a multiple of 512 bytes, if not the in it will\n * fetch the correct data from a buffer in the SATA core and copy it into\n * memory.\n *\n * @param port SATA port to check and if necessary, correct.\n */\nstatic int sata_oxnas_bug_6320_detect(struct ata_port *ap)\n{\n\tstruct sata_oxnas_port_priv *pd = ap->private_data;\n\tvoid __iomem *core_base = pd->core_base;\n\tint is_read;\n\tint quads_transferred;\n\tint remainder;\n\tint sector_quads_remaining;\n\tint bug_present = 0;\n\n\t/* Only want to apply fix to reads */\n\tis_read = !(ioread32(core_base + DM_DBG1) & (ap->port_no ?\n\t\t\tBIT(CORE_PORT1_DATA_DIR_BIT) :\n\t\t\t\tBIT(CORE_PORT0_DATA_DIR_BIT)));\n\n\t/* Check for an incomplete transfer, i.e. not a multiple of 512 bytes\n\t   transferred (datacount_port register counts quads transferred) */\n\tquads_transferred =\n\t\tioread32(core_base + (ap->port_no ?\n\t\t\t\t\tDATACOUNT_PORT1 : DATACOUNT_PORT0));\n\n\tremainder = quads_transferred & 0x7f;\n\tsector_quads_remaining = remainder ? (0x80 - remainder) : 0;\n\n\tif (is_read && (sector_quads_remaining == 2)) {\n\t\tbug_present = 1;\n\t} else if (sector_quads_remaining) {\n\t\tif (is_read) {\n\t\t\tata_port_warn(ap, \"SATA read fixup cannot deal with \"\n\t\t\t\t\"%d quads remaining\\n\",\n\t\t\t\tsector_quads_remaining);\n\t\t} else {\n\t\t\tata_port_warn(ap, \"SATA write fixup of %d quads \"\n\t\t\t\t\"remaining not supported\\n\",\n\t\t\t\tsector_quads_remaining);\n\t\t}\n\t}\n\n\treturn bug_present;\n}\n\n/* This port done an interrupt */\nstatic void sata_oxnas_port_irq(struct ata_port *ap, int force_error)\n{\n\tstruct ata_queued_cmd *qc;\n\tstruct sata_oxnas_port_priv *pd = ap->private_data;\n\tvoid __iomem *port_base = pd->port_base;\n\n\tu32 int_status;\n\tunsigned long flags = 0;\n\n\tDPRINTK(\"ENTER port %d irqstatus %x\\n\", ap->port_no,\n\t\tioread32(port_base + INT_STATUS));\n\n\tif (ap->qc_active & (1ULL << ATA_TAG_INTERNAL)) {\n\t\t\tqc = ata_qc_from_tag(ap, ATA_TAG_INTERNAL);\n\t\t\tDPRINTK(\"completing non-ncq cmd\\n\");\n\n\t\t\tif (qc)\n\t\t\t\tata_qc_complete(qc);\n\n\t\t\treturn;\n\t}\n\n\tqc = ata_qc_from_tag(ap, ap->link.active_tag);\n\n\n\t/* record the port's interrupt */\n\tint_status = ioread32(port_base + INT_STATUS);\n\n\t/* If there's no command associated with this IRQ, ignore it. We may get\n\t * spurious interrupts when cleaning-up after a failed command, ignore\n\t * these too. */\n\tif (likely(qc)) {\n\t\t/* get the status before any error cleanup */\n\t\tqc->err_mask = ac_err_mask(sata_oxnas_check_status(ap));\n\t\tif (force_error) {\n\t\t\t/* Pretend there has been a link error */\n\t\t\tqc->err_mask |= AC_ERR_ATA_BUS;\n\t\t\tDPRINTK(\" ####force error####\\n\");\n\t\t}\n\t\t/* tell libata we're done */\n\t\tlocal_irq_save(flags);\n\t\tsata_oxnas_irq_clear(ap);\n\t\tlocal_irq_restore(flags);\n\t\tata_qc_complete(qc);\n\t} else {\n\t\tVPRINTK(\"Ignoring interrupt, can't find the command tag=\"\n\t\t\t\"%d %08x\\n\", ap->link.active_tag, ap->qc_active);\n\t}\n\n\t/* maybe a hotplug event */\n\tif (unlikely(int_status & INT_LINK_SERROR)) {\n\t\tu32 serror;\n\n\t\tsata_oxnas_scr_read_port(ap, SCR_ERROR, &serror);\n\t\tif (serror & (SERR_DEV_XCHG | SERR_PHYRDY_CHG)) {\n\t\t\tata_ehi_hotplugged(&ap->link.eh_info);\n\t\t\tata_port_freeze(ap);\n\t\t}\n\t}\n}\n\n/**\n * irq_handler is the interrupt handling routine registered with the system,\n * by libata.\n */\nstatic irqreturn_t sata_oxnas_interrupt(int irq, void *dev_instance)\n{\n\tstruct ata_host *ah = dev_instance;\n\tstruct sata_oxnas_host_priv *hd = ah->private_data;\n\tvoid __iomem *core_base = hd->core_base;\n\n\tu32 int_status;\n\tirqreturn_t ret = IRQ_NONE;\n\tu32 port_no;\n\tu32 mask;\n\tint bug_present;\n\n\t/* loop until there are no more interrupts */\n\twhile ((int_status = (ioread32(core_base + CORE_INT_STATUS)) &\n\t\t(COREINT_END | (COREINT_END << 1)))) {\n\n\t\t/* clear any interrupt */\n\t\tiowrite32(int_status, core_base + CORE_INT_CLEAR);\n\n\t\t/* Only need workaround_bug_6320 for single disk systems as dual\n\t\t * disk will use uCode which prevents this read underrun problem\n\t\t * from occurring.\n\t\t * All single disk systems will use port 0 */\n\t\tfor (port_no = 0; port_no < hd->n_ports; ++port_no) {\n\t\t\t/* check the raw end of command interrupt to see if the\n\t\t\t * port is done */\n\t\t\tmask = (COREINT_END << port_no);\n\t\t\tif (!(int_status & mask))\n\t\t\t\tcontinue;\n\n\t\t\t/* this port had an interrupt, clear it */\n\t\t\tiowrite32(mask, core_base + CORE_INT_CLEAR);\n\t\t\t/* check for bug 6320 only if no microcode was loaded */\n\t\t\tbug_present = (hd->current_ucode == UNKNOWN_MODE) &&\n\t\t\t\tsata_oxnas_bug_6320_detect(ah->ports[port_no]);\n\n\t\t\tsata_oxnas_port_irq(ah->ports[port_no],\n\t\t\t\t\t\tbug_present);\n\t\t\tret = IRQ_HANDLED;\n\t\t}\n\t}\n\n\treturn ret;\n}\n\n/*\n * scsi mid-layer and libata interface structures\n */\nstatic struct scsi_host_template sata_oxnas_sht = {\n\tATA_NCQ_SHT(\"sata_oxnas\"),\n\t.can_queue = SATA_OXNAS_QUEUE_DEPTH,\n\t.sg_tablesize = SATA_OXNAS_MAX_PRD,\n\t.dma_boundary = ATA_DMA_BOUNDARY,\n\t.unchecked_isa_dma  = 0,\n};\n\n\nstatic struct ata_port_operations sata_oxnas_ops = {\n\t.inherits = &sata_port_ops,\n\t.qc_prep = sata_oxnas_qc_prep,\n\t.qc_issue = sata_oxnas_qc_issue,\n\t.qc_fill_rtf = sata_oxnas_qc_fill_rtf,\n\t.qc_new = sata_oxnas_qc_new,\n\t.qc_free = sata_oxnas_qc_free,\n\n\t.scr_read = sata_oxnas_scr_read,\n\t.scr_write = sata_oxnas_scr_write,\n\n\t.freeze = sata_oxnas_freeze,\n\t.thaw = sata_oxnas_thaw,\n\t.softreset = sata_oxnas_softreset,\n\t/* .hardreset = sata_oxnas_hardreset, */\n\t.postreset = sata_oxnas_postreset,\n\t.error_handler = sata_oxnas_error_handler,\n\t.post_internal_cmd = sata_oxnas_post_internal_cmd,\n\n\t.port_start = sata_oxnas_port_start,\n\t.port_stop = sata_oxnas_port_stop,\n\n\t.host_stop = sata_oxnas_host_stop,\n\t/* .pmp_attach = sata_oxnas_pmp_attach, */\n\t/* .pmp_detach = sata_oxnas_pmp_detach, */\n\t.sff_check_status = sata_oxnas_check_status,\n\t.acquire_hw = sata_oxnas_acquire_hw,\n};\n\nstatic const struct ata_port_info sata_oxnas_port_info = {\n\t.flags = SATA_OXNAS_HOST_FLAGS,\n\t.pio_mask = ATA_PIO4,\n\t.udma_mask = ATA_UDMA6,\n\t.port_ops = &sata_oxnas_ops,\n};\n\nstatic int sata_oxnas_probe(struct platform_device *ofdev)\n{\n\tint retval = -ENXIO;\n\tint n_ports = 0;\n\tvoid __iomem *port_base = NULL;\n\tvoid __iomem *dmactl_base = NULL;\n\tvoid __iomem *sgdma_base = NULL;\n\tvoid __iomem *core_base = NULL;\n\tvoid __iomem *phy_base = NULL;\n\tstruct reset_control *rstc;\n\n\tstruct resource res = {};\n\tstruct sata_oxnas_host_priv *host_priv = NULL;\n\tint irq = 0;\n\tstruct ata_host *host = NULL;\n\tstruct clk *clk = NULL;\n\n\tconst struct ata_port_info *ppi[] = { &sata_oxnas_port_info, NULL };\n\n\tof_property_read_u32(ofdev->dev.of_node, \"nr-ports\", &n_ports);\n\tif (n_ports < 1 || n_ports > SATA_OXNAS_MAX_PORTS)\n\t\tgoto error_exit_with_cleanup;\n\n\tport_base = of_iomap(ofdev->dev.of_node, 0);\n\tif (!port_base)\n\t\tgoto error_exit_with_cleanup;\n\n\tdmactl_base = of_iomap(ofdev->dev.of_node, 1);\n\tif (!dmactl_base)\n\t\tgoto error_exit_with_cleanup;\n\n\tsgdma_base = of_iomap(ofdev->dev.of_node, 2);\n\tif (!sgdma_base)\n\t\tgoto error_exit_with_cleanup;\n\n\tcore_base = of_iomap(ofdev->dev.of_node, 3);\n\tif (!core_base)\n\t\tgoto error_exit_with_cleanup;\n\n\tphy_base = of_iomap(ofdev->dev.of_node, 4);\n\tif (!phy_base)\n\t\tgoto error_exit_with_cleanup;\n\n\thost_priv = devm_kzalloc(&ofdev->dev,\n\t\t\t\t\tsizeof(struct sata_oxnas_host_priv),\n\t\t\t\t\tGFP_KERNEL);\n\tif (!host_priv)\n\t\tgoto error_exit_with_cleanup;\n\n\thost_priv->port_base = port_base;\n\thost_priv->dmactl_base = dmactl_base;\n\thost_priv->sgdma_base = sgdma_base;\n\thost_priv->core_base = core_base;\n\thost_priv->phy_base = phy_base;\n\thost_priv->n_ports = n_ports;\n\thost_priv->current_ucode = UNKNOWN_MODE;\n\n\tif (!of_address_to_resource(ofdev->dev.of_node, 5, &res)) {\n\t\thost_priv->dma_base = res.start;\n\t\thost_priv->dma_size = resource_size(&res);\n\t}\n\n\tirq = irq_of_parse_and_map(ofdev->dev.of_node, 0);\n\tif (!irq) {\n\t\tdev_err(&ofdev->dev, \"invalid irq from platform\\n\");\n\t\tgoto error_exit_with_cleanup;\n\t}\n\thost_priv->irq = irq;\n\n\tclk = of_clk_get(ofdev->dev.of_node, 0);\n\tif (IS_ERR(clk)) {\n\t\tretval = PTR_ERR(clk);\n\t\tclk = NULL;\n\t\tgoto error_exit_with_cleanup;\n\t}\n\thost_priv->clk = clk;\n\n\trstc = devm_reset_control_get(&ofdev->dev, \"sata\");\n\tif (IS_ERR(rstc)) {\n\t\tretval = PTR_ERR(rstc);\n\t\tgoto error_exit_with_cleanup;\n\t}\n\thost_priv->rst_sata = rstc;\n\n\trstc = devm_reset_control_get(&ofdev->dev, \"link\");\n\tif (IS_ERR(rstc)) {\n\t\tretval = PTR_ERR(rstc);\n\t\tgoto error_exit_with_cleanup;\n\t}\n\thost_priv->rst_link = rstc;\n\n\trstc = devm_reset_control_get(&ofdev->dev, \"phy\");\n\tif (IS_ERR(rstc)) {\n\t\tretval = PTR_ERR(rstc);\n\t\tgoto error_exit_with_cleanup;\n\t}\n\thost_priv->rst_phy = rstc;\n\n\t/* allocate host structure */\n\thost = ata_host_alloc_pinfo(&ofdev->dev, ppi, n_ports);\n\n\tif (!host) {\n\t\tretval = -ENOMEM;\n\t\tgoto error_exit_with_cleanup;\n\t}\n\thost->private_data = host_priv;\n\thost->iomap = port_base;\n\n\t/* initialize core locking and queues */\n\tinit_waitqueue_head(&host_priv->fast_wait_queue);\n\tinit_waitqueue_head(&host_priv->scsi_wait_queue);\n\tspin_lock_init(&host_priv->phy_lock);\n\tspin_lock_init(&host_priv->core_lock);\n\thost_priv->core_locked = 0;\n\thost_priv->reentrant_port_no = -1;\n\thost_priv->hw_lock_count = 0;\n\thost_priv->direct_lock_count = 0;\n\thost_priv->locker_uid = 0;\n\thost_priv->current_locker_type = SATA_UNLOCKED;\n\thost_priv->isr_arg = NULL;\n\thost_priv->isr_callback = NULL;\n\n\t/* initialize host controller */\n\tretval = sata_oxnas_init_controller(host);\n\tif (retval)\n\t\tgoto error_exit_with_cleanup;\n\n\t/*\n\t * Now, register with libATA core, this will also initiate the\n\t * device discovery process, invoking our port_start() handler &\n\t * error_handler() to execute a dummy softreset EH session\n\t */\n\tata_host_activate(host, irq, sata_oxnas_interrupt, SATA_OXNAS_IRQ_FLAG,\n\t\t\t  &sata_oxnas_sht);\n\n\treturn 0;\n\nerror_exit_with_cleanup:\n\tif (irq)\n\t\tirq_dispose_mapping(host_priv->irq);\n\tif (clk)\n\t\tclk_put(clk);\n\tif (host)\n\t\tata_host_detach(host);\n\tif (port_base)\n\t\tiounmap(port_base);\n\tif (sgdma_base)\n\t\tiounmap(sgdma_base);\n\tif (core_base)\n\t\tiounmap(core_base);\n\tif (phy_base)\n\t\tiounmap(phy_base);\n\treturn retval;\n}\n\n\nstatic int sata_oxnas_remove(struct platform_device *ofdev)\n{\n\tstruct ata_host *host = dev_get_drvdata(&ofdev->dev);\n\tstruct sata_oxnas_host_priv *host_priv = host->private_data;\n\n\tata_host_detach(host);\n\n\tirq_dispose_mapping(host_priv->irq);\n\tiounmap(host_priv->port_base);\n\tiounmap(host_priv->sgdma_base);\n\tiounmap(host_priv->core_base);\n\n\t/* reset Controller, Link and PHY */\n\treset_control_assert(host_priv->rst_sata);\n\treset_control_assert(host_priv->rst_link);\n\treset_control_assert(host_priv->rst_phy);\n\n\t/* Disable the clock to the SATA block */\n\tclk_disable_unprepare(host_priv->clk);\n\tclk_put(host_priv->clk);\n\n\treturn 0;\n}\n\n#ifdef CONFIG_PM\nstatic int sata_oxnas_suspend(struct platform_device *op, pm_message_t state)\n{\n\tstruct ata_host *host = dev_get_drvdata(&op->dev);\n\n\treturn ata_host_suspend(host, state);\n}\n\nstatic int sata_oxnas_resume(struct platform_device *op)\n{\n\tstruct ata_host *host = dev_get_drvdata(&op->dev);\n\tint ret;\n\n\tret = sata_oxnas_init_controller(host);\n\tif (ret) {\n\t\tdev_err(&op->dev, \"Error initializing hardware\\n\");\n\t\treturn ret;\n\t}\n\tata_host_resume(host);\n\treturn 0;\n}\n#endif\n\n\n\nstatic struct of_device_id oxnas_sata_match[] = {\n\t{\n\t\t.compatible = \"plxtech,nas782x-sata\",\n\t},\n\t{},\n};\n\nMODULE_DEVICE_TABLE(of, oxnas_sata_match);\n\nstatic struct platform_driver oxnas_sata_driver = {\n\t.driver = {\n\t\t.name = \"oxnas-sata\",\n\t\t.owner = THIS_MODULE,\n\t\t.of_match_table = oxnas_sata_match,\n\t},\n\t.probe\t\t= sata_oxnas_probe,\n\t.remove\t\t= sata_oxnas_remove,\n#ifdef CONFIG_PM\n\t.suspend\t= sata_oxnas_suspend,\n\t.resume\t\t= sata_oxnas_resume,\n#endif\n};\n\nmodule_platform_driver(oxnas_sata_driver);\n\nMODULE_LICENSE(\"GPL\");\nMODULE_VERSION(\"1.0\");\nMODULE_AUTHOR(\"Oxford Semiconductor Ltd.\");\nMODULE_DESCRIPTION(\"low-level driver for Oxford 934 SATA core\");\n"
  },
  {
    "path": "target/linux/oxnas/files/drivers/pci/controller/pcie-oxnas.c",
    "content": "/*\n * PCIe driver for PLX NAS782X SoCs\n *\n * Author: Ma Haijun <mahaijuns@gmail.com>\n *\n * This file is licensed under the terms of the GNU General Public\n * License version 2.  This program is licensed \"as is\" without any\n * warranty of any kind, whether express or implied.\n */\n\n#include <linux/kernel.h>\n#include <linux/pci.h>\n#include <linux/clk.h>\n#include <linux/module.h>\n#include <linux/mbus.h>\n#include <linux/mfd/syscon.h>\n#include <linux/slab.h>\n#include <linux/platform_device.h>\n#include <linux/of_address.h>\n#include <linux/of_device.h>\n#include <linux/of_gpio.h>\n#include <linux/of_irq.h>\n#include <linux/of_pci.h>\n#include <linux/of_platform.h>\n#include <linux/gpio.h>\n#include <linux/delay.h>\n#include <linux/clk.h>\n#include <linux/phy.h>\n#include <linux/phy/phy.h>\n#include <linux/regmap.h>\n#include <linux/reset.h>\n#include <linux/io.h>\n#include <linux/sizes.h>\n\n#include \"../pci.h\"\n\n#define SYS_CTRL_HCSL_CTRL_REGOFFSET\t0x114\n\nstatic inline void oxnas_register_clear_mask(void __iomem *p, unsigned mask)\n{\n\tu32 val = readl_relaxed(p);\n\n\tval &= ~mask;\n\twritel_relaxed(val, p);\n}\n\nstatic inline void oxnas_register_set_mask(void __iomem *p, unsigned mask)\n{\n\tu32 val = readl_relaxed(p);\n\n\tval |= mask;\n\twritel_relaxed(val, p);\n}\n\nstatic inline void oxnas_register_value_mask(void __iomem *p,\n\t\t\t\t\t     unsigned mask, unsigned new_value)\n{\n\t/* TODO sanity check mask & new_value = new_value */\n\tu32 val = readl_relaxed(p);\n\n\tval &= ~mask;\n\tval |= new_value;\n\twritel_relaxed(val, p);\n}\n\n#define VERSION_ID_MAGIC\t\t0x082510b5\n#define LINK_UP_TIMEOUT_SECONDS\t\t1\n#define NUM_CONTROLLERS\t\t\t1\n\nenum {\n\tPCIE_DEVICE_TYPE_MASK = 0x0F,\n\tPCIE_DEVICE_TYPE_ENDPOINT = 0,\n\tPCIE_DEVICE_TYPE_LEGACY_ENDPOINT = 1,\n\tPCIE_DEVICE_TYPE_ROOT = 4,\n\n\tPCIE_LTSSM = BIT(4),\n\tPCIE_READY_ENTR_L23 = BIT(9),\n\tPCIE_LINK_UP = BIT(11),\n\tPCIE_OBTRANS = BIT(12),\n};\n\n/* core config registers */\nenum {\n\tPCI_CONFIG_VERSION_DEVICEID = 0,\n\tPCI_CONFIG_COMMAND_STATUS = 4,\n};\n\n/* inbound config registers */\nenum {\n\tIB_ADDR_XLATE_ENABLE = 0xFC,\n\n\t/* bits */\n\tENABLE_IN_ADDR_TRANS = BIT(0),\n};\n\n/* outbound config registers, offset relative to PCIE_POM0_MEM_ADDR */\nenum {\n\tPCIE_POM0_MEM_ADDR\t= 0,\n\tPCIE_POM1_MEM_ADDR\t= 4,\n\tPCIE_IN0_MEM_ADDR\t= 8,\n\tPCIE_IN1_MEM_ADDR\t= 12,\n\tPCIE_IN_IO_ADDR\t\t= 16,\n\tPCIE_IN_CFG0_ADDR\t= 20,\n\tPCIE_IN_CFG1_ADDR\t= 24,\n\tPCIE_IN_MSG_ADDR\t= 28,\n\tPCIE_IN0_MEM_LIMIT\t= 32,\n\tPCIE_IN1_MEM_LIMIT\t= 36,\n\tPCIE_IN_IO_LIMIT\t= 40,\n\tPCIE_IN_CFG0_LIMIT\t= 44,\n\tPCIE_IN_CFG1_LIMIT\t= 48,\n\tPCIE_IN_MSG_LIMIT\t= 52,\n\tPCIE_AHB_SLAVE_CTRL\t= 56,\n\n\tPCIE_SLAVE_BE_SHIFT\t= 22,\n};\n\n#define PCIE_SLAVE_BE(val)\t((val) << PCIE_SLAVE_BE_SHIFT)\n#define PCIE_SLAVE_BE_MASK\tPCIE_SLAVE_BE(0xF)\n\nstruct oxnas_pcie_shared {\n\t/* seems all access are serialized, no lock required */\n\tint refcount;\n};\n\n/* Structure representing one PCIe interfaces */\nstruct oxnas_pcie {\n\tvoid __iomem *cfgbase;\n\tvoid __iomem *base;\n\tvoid __iomem *inbound;\n\tstruct regmap *sys_ctrl;\n\tunsigned int outbound_offset;\n\tunsigned int pcie_ctrl_offset;\n\tstruct phy *phy;\n\tint haslink;\n\tstruct platform_device *pdev;\n\tstruct resource io;\n\tstruct resource cfg;\n\tstruct resource pre_mem;\t/* prefetchable */\n\tstruct resource non_mem;\t/* non-prefetchable */\n\tstruct resource busn;\t\t/* max available bus numbers */\n\tint card_reset;\t\t\t/* gpio pin, optional */\n\tunsigned hcsl_en;\t\t/* hcsl pci enable bit */\n\tstruct clk *clk;\n\tstruct clk *busclk;\t\t/* for pcie bus, actually the PLLB */\n\tvoid *private_data[1];\n\tspinlock_t lock;\n};\n\nstatic struct oxnas_pcie_shared pcie_shared = {\n\t.refcount = 0,\n};\n\nstatic inline struct oxnas_pcie *sys_to_pcie(struct pci_sys_data *sys)\n{\n\treturn sys->private_data;\n}\n\n\nstatic inline void set_out_lanes(struct oxnas_pcie *pcie, unsigned lanes)\n{\n\tregmap_update_bits(pcie->sys_ctrl, pcie->outbound_offset + PCIE_AHB_SLAVE_CTRL,\n\t\t\t\t  PCIE_SLAVE_BE_MASK, PCIE_SLAVE_BE(lanes));\n\twmb();\n}\n\nstatic int oxnas_pcie_link_up(struct oxnas_pcie *pcie)\n{\n\tunsigned long end;\n\tunsigned int val;\n\n\t/* Poll for PCIE link up */\n\tend = jiffies + (LINK_UP_TIMEOUT_SECONDS * HZ);\n\twhile (!time_after(jiffies, end)) {\n\t\tregmap_read(pcie->sys_ctrl, pcie->pcie_ctrl_offset, &val);\n\t\tif (val & PCIE_LINK_UP)\n\t\t\treturn 1;\n\t}\n\treturn 0;\n}\n\nstatic void oxnas_pcie_setup_hw(struct oxnas_pcie *pcie)\n{\n\t/* We won't have any inbound address translation. This allows PCI\n\t * devices to access anywhere in the AHB address map. Might be regarded\n\t * as a bit dangerous, but let's get things working before we worry\n\t * about that\n\t */\n\toxnas_register_clear_mask(pcie->inbound + IB_ADDR_XLATE_ENABLE,\n\t\t\t\t  ENABLE_IN_ADDR_TRANS);\n\twmb();\n\n\t/*\n\t * Program outbound translation windows\n\t *\n\t * Outbound window is what is referred to as \"PCI client\" region in HRM\n\t *\n\t * Could use the larger alternative address space to get >>64M regions\n\t * for graphics cards etc., but will not bother at this point.\n\t *\n\t * IP bug means that AMBA window size must be a power of 2\n\t *\n\t * Set mem0 window for first 16MB of outbound window non-prefetchable\n\t * Set mem1 window for second 16MB of outbound window prefetchable\n\t * Set io window for next 16MB of outbound window\n\t * Set cfg0 for final 1MB of outbound window\n\t *\n\t * Ignore mem1, cfg1 and msg windows for now as no obvious use cases for\n\t * 820 that would need them\n\t *\n\t * Probably ideally want no offset between mem0 window start as seen by\n\t * ARM and as seen on PCI bus and get Linux to assign memory regions to\n\t * PCI devices using the same \"PCI client\" region start address as seen\n\t * by ARM\n\t */\n\n\t/* Set PCIeA mem0 region to be 1st 16MB of the 64MB PCIeA window */\n\tregmap_write(pcie->sys_ctrl, pcie->outbound_offset + PCIE_IN0_MEM_ADDR, pcie->non_mem.start);\n\tregmap_write(pcie->sys_ctrl, pcie->outbound_offset + PCIE_IN0_MEM_LIMIT, pcie->non_mem.end);\n\tregmap_write(pcie->sys_ctrl, pcie->outbound_offset + PCIE_POM0_MEM_ADDR, pcie->non_mem.start);\n\n\t/* Set PCIeA mem1 region to be 2nd 16MB of the 64MB PCIeA window */\n\tregmap_write(pcie->sys_ctrl, pcie->outbound_offset + PCIE_IN1_MEM_ADDR, pcie->pre_mem.start);\n\tregmap_write(pcie->sys_ctrl, pcie->outbound_offset + PCIE_IN1_MEM_LIMIT, pcie->pre_mem.end);\n\tregmap_write(pcie->sys_ctrl, pcie->outbound_offset + PCIE_POM1_MEM_ADDR, pcie->pre_mem.start);\n\n\t/* Set PCIeA io to be third 16M region of the 64MB PCIeA window*/\n\tregmap_write(pcie->sys_ctrl, pcie->outbound_offset + PCIE_IN_IO_ADDR, pcie->io.start);\n\tregmap_write(pcie->sys_ctrl, pcie->outbound_offset + PCIE_IN_IO_LIMIT, pcie->io.end);\n\n\n\t/* Set PCIeA cgf0 to be last 16M region of the 64MB PCIeA window*/\n\tregmap_write(pcie->sys_ctrl, pcie->outbound_offset + PCIE_IN_CFG0_ADDR, pcie->cfg.start);\n\tregmap_write(pcie->sys_ctrl, pcie->outbound_offset + PCIE_IN_CFG0_LIMIT, pcie->cfg.end);\n\twmb();\n\n\t/* Enable outbound address translation */\n\tregmap_write_bits(pcie->sys_ctrl, pcie->pcie_ctrl_offset, PCIE_OBTRANS, PCIE_OBTRANS);\n\twmb();\n\n\t/*\n\t * Program PCIe command register for core to:\n\t *  enable memory space\n\t *  enable bus master\n\t *  enable io\n\t */\n\twritel_relaxed(7, pcie->base + PCI_CONFIG_COMMAND_STATUS);\n\t/* which is which */\n\twmb();\n}\n\nstatic unsigned oxnas_pcie_cfg_to_offset(\n\tstruct pci_sys_data *sys,\n\tunsigned char bus_number,\n\tunsigned int devfn,\n\tint where)\n{\n\tunsigned int function = PCI_FUNC(devfn);\n\tunsigned int slot = PCI_SLOT(devfn);\n\tunsigned char bus_number_offset;\n\n\tbus_number_offset = bus_number - sys->busnr;\n\n\t/*\n\t * We'll assume for now that the offset, function, slot, bus encoding\n\t * should map onto linear, contiguous addresses in PCIe config space,\n\t * albeit that the majority will be unused as only slot 0 is valid for\n\t * any PCIe bus and most devices have only function 0\n\t *\n\t * Could be that PCIe in fact works by not encoding the slot number into\n\t * the config space address as it's known that only slot 0 is valid.\n\t * We'll have to experiment if/when we get a PCIe switch connected to\n\t * the PCIe host\n\t */\n\treturn (bus_number_offset << 20) | (slot << 15) | (function << 12) |\n\t\t(where & ~3);\n}\n\n/* PCI configuration space write function */\nstatic int oxnas_pcie_wr_conf(struct pci_bus *bus, u32 devfn,\n\t\t\t      int where, int size, u32 val)\n{\n\tunsigned long flags;\n\tstruct oxnas_pcie *pcie = sys_to_pcie(bus->sysdata);\n\tunsigned offset;\n\tu32 value;\n\tu32 lanes;\n\n\t/* Only a single device per bus for PCIe point-to-point links */\n\tif (PCI_SLOT(devfn) > 0)\n\t\treturn PCIBIOS_DEVICE_NOT_FOUND;\n\n\tif (!pcie->haslink)\n\t\treturn PCIBIOS_DEVICE_NOT_FOUND;\n\n\toffset = oxnas_pcie_cfg_to_offset(bus->sysdata, bus->number, devfn,\n\t\t\t\t\t  where);\n\n\tvalue = val << (8 * (where & 3));\n\tlanes = (0xf >> (4-size)) << (where & 3);\n\t/* it race with mem and io write, but the possibility is low, normally\n\t * all config writes happens at driver initialize stage, wont interleave\n\t * with others.\n\t * and many pcie cards use dword (4bytes) access mem/io access only,\n\t * so not bother to copy that ugly work-around now. */\n\tspin_lock_irqsave(&pcie->lock, flags);\n\tset_out_lanes(pcie, lanes);\n\twritel_relaxed(value, pcie->cfgbase + offset);\n\tset_out_lanes(pcie, 0xf);\n\tspin_unlock_irqrestore(&pcie->lock, flags);\n\n\treturn PCIBIOS_SUCCESSFUL;\n}\n\n/* PCI configuration space read function */\nstatic int oxnas_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,\n\t\t\t      int size, u32 *val)\n{\n\tstruct oxnas_pcie *pcie = sys_to_pcie(bus->sysdata);\n\tunsigned offset;\n\tu32 value;\n\tu32 left_bytes, right_bytes;\n\n\t/* Only a single device per bus for PCIe point-to-point links */\n\tif (PCI_SLOT(devfn) > 0) {\n\t\t*val = 0xffffffff;\n\t\treturn PCIBIOS_DEVICE_NOT_FOUND;\n\t}\n\n\tif (!pcie->haslink) {\n\t\t*val = 0xffffffff;\n\t\treturn PCIBIOS_DEVICE_NOT_FOUND;\n\t}\n\n\toffset = oxnas_pcie_cfg_to_offset(bus->sysdata, bus->number, devfn,\n\t\t\t\t\t  where);\n\tvalue = readl_relaxed(pcie->cfgbase + offset);\n\tleft_bytes = where & 3;\n\tright_bytes = 4 - left_bytes - size;\n\tvalue <<= right_bytes * 8;\n\tvalue >>= (left_bytes + right_bytes) * 8;\n\t*val = value;\n\n\treturn PCIBIOS_SUCCESSFUL;\n}\n\nstatic struct pci_ops oxnas_pcie_ops = {\n\t.read = oxnas_pcie_rd_conf,\n\t.write = oxnas_pcie_wr_conf,\n};\n\nstatic int oxnas_pcie_setup(int nr, struct pci_sys_data *sys)\n{\n\tstruct oxnas_pcie *pcie = sys_to_pcie(sys);\n\n\tpci_add_resource_offset(&sys->resources, &pcie->non_mem, sys->mem_offset);\n\tpci_add_resource_offset(&sys->resources, &pcie->pre_mem, sys->mem_offset);\n\tpci_add_resource_offset(&sys->resources, &pcie->io, sys->io_offset);\n\tpci_add_resource(&sys->resources, &pcie->busn);\n\tif (sys->busnr == 0) { /* default one */\n\t\tsys->busnr = pcie->busn.start;\n\t}\n\t/* do not use devm_ioremap_resource, it does not like cfg resource */\n\tpcie->cfgbase = devm_ioremap(&pcie->pdev->dev, pcie->cfg.start,\n\t\t\t\t     resource_size(&pcie->cfg));\n\tif (!pcie->cfgbase)\n\t\treturn -ENOMEM;\n\n\toxnas_pcie_setup_hw(pcie);\n\n\treturn 1;\n}\n\nstatic void oxnas_pcie_enable(struct device *dev, struct oxnas_pcie *pcie)\n{\n\tstruct hw_pci hw;\n\tint i;\n\n\tmemset(&hw, 0, sizeof(hw));\n\tfor (i = 0; i < NUM_CONTROLLERS; i++)\n\t\tpcie->private_data[i] = pcie;\n\n\thw.nr_controllers = NUM_CONTROLLERS;\n/* I think use stack pointer is a bad idea though it is valid in this case */\n\thw.private_data   = pcie->private_data;\n\thw.setup          = oxnas_pcie_setup;\n\thw.map_irq        = of_irq_parse_and_map_pci;\n\thw.ops            = &oxnas_pcie_ops;\n\n\t/* pass dev to maintain of tree, interrupt mapping rely on this */\n\tpci_common_init_dev(dev, &hw);\n}\n\nstatic int oxnas_pcie_shared_init(struct platform_device *pdev, struct oxnas_pcie *pcie)\n{\n\tif (++pcie_shared.refcount == 1) {\n\t\tphy_init(pcie->phy);\n\t\tphy_power_on(pcie->phy);\n\t\treturn 0;\n\t} else {\n\t\treturn 0;\n\t}\n}\n\n#if 0\n/* maybe we will call it when enter low power state */\nstatic void oxnas_pcie_shared_deinit(struct platform_device *pdev)\n{\n\tif (--pcie_shared.refcount == 0) {\n\t\t/* no cleanup needed */;\n\t}\n}\n#endif\n\nstatic int\noxnas_pcie_map_registers(struct platform_device *pdev,\n\t\t\t struct device_node *np,\n\t\t\t struct oxnas_pcie *pcie)\n{\n\tstruct resource regs;\n\tint ret = 0;\n\tu32 outbound_ctrl_offset;\n\tu32 pcie_ctrl_offset;\n\n\tret = of_address_to_resource(np, 0, &regs);\n\tif (ret) {\n\t\tdev_err(&pdev->dev, \"failed to parse base register space\\n\");\n\t\treturn -EINVAL;\n\t}\n\n\tpcie->base = devm_ioremap_resource(&pdev->dev, &regs);\n\tif (!pcie->base) {\n\t\tdev_err(&pdev->dev, \"failed to map base register space\\n\");\n\t\treturn -ENOMEM;\n\t}\n\n\tret = of_address_to_resource(np, 1, &regs);\n\tif (ret) {\n\t\tdev_err(&pdev->dev, \"failed to parse inbound register space\\n\");\n\t\treturn -EINVAL;\n\t}\n\n\tpcie->inbound = devm_ioremap_resource(&pdev->dev, &regs);\n\tif (!pcie->inbound) {\n\t\tdev_err(&pdev->dev, \"failed to map inbound register space\\n\");\n\t\treturn -ENOMEM;\n\t}\n\n\tpcie->phy = devm_of_phy_get(&pdev->dev, np, NULL);\n\tif (IS_ERR(pcie->phy)) {\n\t\tif (PTR_ERR(pcie->phy) == -EPROBE_DEFER) {\n\t\t\tdev_err(&pdev->dev, \"failed to probe phy\\n\");\n\t\t\treturn PTR_ERR(pcie->phy);\n\t\t}\n\t\tdev_warn(&pdev->dev, \"phy not attached\\n\");\n\t\tpcie->phy = NULL;\n\t}\n\n\tif (of_property_read_u32(np, \"plxtech,pcie-outbound-offset\",\n\t\t\t\t &outbound_ctrl_offset)) {\n\t\tdev_err(&pdev->dev, \"failed to parse outbound register offset\\n\");\n\t\treturn -EINVAL;\n\t}\n\tpcie->outbound_offset = outbound_ctrl_offset;\n\n\tif (of_property_read_u32(np, \"plxtech,pcie-ctrl-offset\",\n\t\t\t\t &pcie_ctrl_offset)) {\n\t\tdev_err(&pdev->dev, \"failed to parse pcie-ctrl register offset\\n\");\n\t\treturn -EINVAL;\n\t}\n\tpcie->pcie_ctrl_offset = pcie_ctrl_offset;\n\n\treturn 0;\n}\n\nstatic int oxnas_pcie_init_res(struct platform_device *pdev,\n\t\t\t\t      struct oxnas_pcie *pcie,\n\t\t\t\t      struct device_node *np)\n{\n\tstruct of_pci_range range;\n\tstruct of_pci_range_parser parser;\n\tint ret;\n\n\tif (of_pci_range_parser_init(&parser, np))\n\t\treturn -EINVAL;\n\n\t/* Get the I/O and memory ranges from DT */\n\tfor_each_of_pci_range(&parser, &range) {\n\n\t\tunsigned long restype = range.flags & IORESOURCE_TYPE_BITS;\n\t\tif (restype == IORESOURCE_IO) {\n\t\t\tof_pci_range_to_resource(&range, np, &pcie->io);\n\t\t\tpcie->io.name = \"I/O\";\n\t\t}\n\t\tif (restype == IORESOURCE_MEM) {\n\t\t\tif (range.flags & IORESOURCE_PREFETCH) {\n\t\t\t\tof_pci_range_to_resource(&range, np, &pcie->pre_mem);\n\t\t\t\tpcie->pre_mem.name = \"PRE MEM\";\n\t\t\t} else {\n\t\t\t\tof_pci_range_to_resource(&range, np, &pcie->non_mem);\n\t\t\t\tpcie->non_mem.name = \"NON MEM\";\n\t\t\t}\n\n\t\t}\n\t\tif (restype == 0)\n\t\t\tof_pci_range_to_resource(&range, np, &pcie->cfg);\n\t}\n\n\t/* Get the bus range */\n\tret = of_pci_parse_bus_range(np, &pcie->busn);\n\n\tif (ret) {\n\t\tdev_err(&pdev->dev, \"failed to parse bus-range property: %d\\n\",\n\t\t\tret);\n\t\treturn ret;\n\t}\n\n\tpcie->card_reset = of_get_gpio(np, 0);\n\tif (pcie->card_reset < 0)\n\t\tdev_info(&pdev->dev, \"card reset gpio pin not exists\\n\");\n\n\tif (of_property_read_u32(np, \"plxtech,pcie-hcsl-bit\", &pcie->hcsl_en))\n\t\treturn -EINVAL;\n\n\tpcie->clk = of_clk_get_by_name(np, \"pcie\");\n\tif (IS_ERR(pcie->clk)) {\n\t\treturn PTR_ERR(pcie->clk);\n\t}\n\n\tpcie->busclk = of_clk_get_by_name(np, \"busclk\");\n\tif (IS_ERR(pcie->busclk)) {\n\t\tclk_put(pcie->clk);\n\t\treturn PTR_ERR(pcie->busclk);\n\t}\n\n\treturn 0;\n}\n\nstatic void oxnas_pcie_init_hw(struct platform_device *pdev,\n\t\t\t       struct oxnas_pcie *pcie)\n{\n\tu32 version_id;\n\tint ret;\n\n\tclk_prepare_enable(pcie->busclk);\n\n\t/* reset PCIe cards use hard-wired gpio pin */\n\tif (pcie->card_reset >= 0 &&\n\t    !gpio_direction_output(pcie->card_reset, 0)) {\n\t\twmb();\n\t\tmdelay(10);\n\t\t/* must tri-state the pin to pull it up */\n\t\tgpio_direction_input(pcie->card_reset);\n\t\twmb();\n\t\tmdelay(100);\n\t}\n\n\t/* ToDo: use phy power-on port... */\n\tregmap_update_bits(pcie->sys_ctrl, SYS_CTRL_HCSL_CTRL_REGOFFSET,\n\t                   BIT(pcie->hcsl_en), BIT(pcie->hcsl_en));\n\n\t/* core */\n\tret = device_reset(&pdev->dev);\n\tif (ret) {\n\t\tdev_err(&pdev->dev, \"core reset failed %d\\n\", ret);\n\t\treturn;\n\t}\n\n\t/* Start PCIe core clocks */\n\tclk_prepare_enable(pcie->clk);\n\n\tversion_id = readl_relaxed(pcie->base + PCI_CONFIG_VERSION_DEVICEID);\n\tdev_info(&pdev->dev, \"PCIe version/deviceID 0x%x\\n\", version_id);\n\n\tif (version_id != VERSION_ID_MAGIC) {\n\t\tdev_info(&pdev->dev, \"PCIe controller not found\\n\");\n\t\tpcie->haslink = 0;\n\t\treturn;\n\t}\n\n\t/* allow entry to L23 state */\n\tregmap_write_bits(pcie->sys_ctrl, pcie->pcie_ctrl_offset,\n\t                  PCIE_READY_ENTR_L23, PCIE_READY_ENTR_L23);\n\n\t/* Set PCIe core into RootCore mode */\n\tregmap_write_bits(pcie->sys_ctrl, pcie->pcie_ctrl_offset,\n\t                  PCIE_DEVICE_TYPE_MASK, PCIE_DEVICE_TYPE_ROOT);\n\twmb();\n\n\t/* Bring up the PCI core */\n\tregmap_write_bits(pcie->sys_ctrl, pcie->pcie_ctrl_offset,\n\t                  PCIE_LTSSM, PCIE_LTSSM);\n\twmb();\n}\n\nstatic int oxnas_pcie_probe(struct platform_device *pdev)\n{\n\tstruct oxnas_pcie *pcie;\n\tstruct device_node *np = pdev->dev.of_node;\n\tint ret;\n\n\tpcie = devm_kzalloc(&pdev->dev, sizeof(struct oxnas_pcie),\n\t\t\t    GFP_KERNEL);\n\tif (!pcie)\n\t\treturn -ENOMEM;\n\n\tpcie->pdev = pdev;\n\tpcie->haslink = 1;\n\tspin_lock_init(&pcie->lock);\n\n\tpcie->sys_ctrl = syscon_regmap_lookup_by_compatible(\"oxsemi,ox820-sys-ctrl\");\n\tif (IS_ERR(pcie->sys_ctrl))\n\t\treturn PTR_ERR(pcie->sys_ctrl);\n\n\tret = oxnas_pcie_init_res(pdev, pcie, np);\n\tif (ret)\n\t\treturn ret;\n\tif (pcie->card_reset >= 0) {\n\t\tret = gpio_request_one(pcie->card_reset, GPIOF_DIR_IN,\n\t\t\t\t       dev_name(&pdev->dev));\n\t\tif (ret) {\n\t\t\tdev_err(&pdev->dev, \"cannot request gpio pin %d\\n\",\n\t\t\t\tpcie->card_reset);\n\t\t\treturn ret;\n\t\t}\n\t}\n\n\tret = oxnas_pcie_map_registers(pdev, np, pcie);\n\tif (ret) {\n\t\tdev_err(&pdev->dev, \"cannot map registers\\n\");\n\t\tgoto err_free_gpio;\n\t}\n\n\tret = oxnas_pcie_shared_init(pdev, pcie);\n\tif (ret)\n\t\tgoto err_free_gpio;\n\n\t/* if hw not found, haslink cleared */\n\toxnas_pcie_init_hw(pdev, pcie);\n\n\tif (pcie->haslink && oxnas_pcie_link_up(pcie)) {\n\t\tpcie->haslink = 1;\n\t\tdev_info(&pdev->dev, \"link up\\n\");\n\t} else {\n\t\tpcie->haslink = 0;\n\t\tdev_info(&pdev->dev, \"link down\\n\");\n\t}\n\t/* should we register our controller even when pcie->haslink is 0 ? */\n\t/* register the controller with framework */\n\toxnas_pcie_enable(&pdev->dev, pcie);\n\n\treturn 0;\n\nerr_free_gpio:\n\tif (pcie->card_reset)\n\t\tgpio_free(pcie->card_reset);\n\n\treturn ret;\n}\n\nstatic const struct of_device_id oxnas_pcie_of_match_table[] = {\n\t{ .compatible = \"plxtech,nas782x-pcie\", },\n\t{},\n};\n\nstatic struct platform_driver oxnas_pcie_driver = {\n\t.driver = {\n\t\t.name = \"oxnas-pcie\",\n\t\t.suppress_bind_attrs = true,\n\t\t.of_match_table = oxnas_pcie_of_match_table,\n\t},\n\t.probe = oxnas_pcie_probe,\n};\n\nbuiltin_platform_driver(oxnas_pcie_driver);\n"
  },
  {
    "path": "target/linux/oxnas/files/drivers/phy/phy-oxnas-pcie.c",
    "content": "// SPDX-License-Identifier: GPL-2.0-only\n/*\n * Copyright (c) 2019 Daniel Golle <daniel@makrotopia.org>\n *\n */\n\n#include <dt-bindings/phy/phy.h>\n#include <linux/io.h>\n#include <linux/iopoll.h>\n#include <linux/module.h>\n#include <linux/of_address.h>\n#include <linux/of_device.h>\n#include <linux/mfd/syscon.h>\n#include <linux/phy/phy.h>\n#include <linux/platform_device.h>\n#include <linux/regmap.h>\n#include <linux/reset.h>\n\n#define ADDR_VAL(val)\t((val) & 0xFFFF)\n#define DATA_VAL(val)\t((val) & 0xFFFF)\n\n#define SYS_CTRL_HCSL_CTRL_REGOFFSET\t0x114\n\nenum {\n\tHCSL_BIAS_ON = BIT(0),\n\tHCSL_PCIE_EN = BIT(1),\n\tHCSL_PCIEA_EN = BIT(2),\n\tHCSL_PCIEB_EN = BIT(3),\n};\n\nenum {\n\t/* pcie phy reg offset */\n\tPHY_ADDR = 0,\n\tPHY_DATA = 4,\n\t/* phy data reg bits */\n\tREAD_EN = BIT(16),\n\tWRITE_EN = BIT(17),\n\tCAP_DATA = BIT(18),\n};\n\nstruct oxnas_pcie_phy {\n\tstruct device *dev;\n\tvoid __iomem *membase;\n\tconst struct phy_ops *ops;\n\tstruct regmap *sys_ctrl;\n\tstruct reset_control *rstc;\n};\n\nstatic int oxnas_pcie_phy_init(struct phy *phy)\n{\n\tstruct oxnas_pcie_phy *pciephy = phy_get_drvdata(phy);\n\tint ret;\n\n\t/* generate clocks from HCSL buffers, shared parts */\n\tregmap_write(pciephy->sys_ctrl, SYS_CTRL_HCSL_CTRL_REGOFFSET, HCSL_BIAS_ON|HCSL_PCIE_EN);\n\n\t/* Ensure PCIe PHY is properly reset */\n\tret = reset_control_reset(pciephy->rstc);\n\n\tif (ret) {\n\t\tdev_err(pciephy->dev, \"phy reset failed %d\\n\", ret);\n\t\treturn ret;\n\t}\n\n\treturn 0;\n}\n\nstatic int oxnas_pcie_phy_power_on(struct phy *phy)\n{\n\tstruct oxnas_pcie_phy *pciephy = phy_get_drvdata(phy);\n\n\t/* Enable PCIe Pre-Emphasis: What these value means? */\n\twritel(ADDR_VAL(0x0014), pciephy->membase + PHY_ADDR);\n\twritel(DATA_VAL(0xce10) | CAP_DATA, pciephy->membase + PHY_DATA);\n\twritel(DATA_VAL(0xce10) | WRITE_EN, pciephy->membase + PHY_DATA);\n\n\twritel(ADDR_VAL(0x2004), pciephy->membase + PHY_ADDR);\n\twritel(DATA_VAL(0x82c7) | CAP_DATA, pciephy->membase + PHY_DATA);\n\twritel(DATA_VAL(0x82c7) | WRITE_EN, pciephy->membase + PHY_DATA);\n\n\treturn 0;\n}\n\nstatic const struct phy_ops ops = {\n\t.init           = oxnas_pcie_phy_init,\n\t.power_on       = oxnas_pcie_phy_power_on,\n\t.owner          = THIS_MODULE,\n};\n\nstatic int oxnas_pcie_phy_probe(struct platform_device *pdev)\n{\n\tstruct device *dev = &pdev->dev;\n\tstruct device_node *np = pdev->dev.of_node;\n\tstruct phy *generic_phy;\n\tstruct phy_provider *phy_provider;\n\tstruct oxnas_pcie_phy *pciephy;\n\tstruct regmap *sys_ctrl;\n\tstruct reset_control *rstc;\n\tvoid __iomem *membase;\n\n\tmembase = of_iomap(np, 0);\n\tif (IS_ERR(membase))\n\t\treturn PTR_ERR(membase);\n\n\tsys_ctrl = syscon_regmap_lookup_by_compatible(\"oxsemi,ox820-sys-ctrl\");\n\tif (IS_ERR(sys_ctrl))\n\t\treturn PTR_ERR(sys_ctrl);\n\n\trstc = devm_reset_control_get_shared(dev, \"phy\");\n\tif (IS_ERR(rstc))\n\t\treturn PTR_ERR(rstc);\n\n\tpciephy = devm_kzalloc(dev, sizeof(*pciephy), GFP_KERNEL);\n\tif (!pciephy)\n\t\treturn -ENOMEM;\n\n\tpciephy->sys_ctrl = sys_ctrl;\n\tpciephy->rstc = rstc;\n\tpciephy->membase = membase;\n\tpciephy->dev = dev;\n\tpciephy->ops = &ops;\n\n\tgeneric_phy = devm_phy_create(dev, dev->of_node, pciephy->ops);\n\tif (IS_ERR(generic_phy)) {\n\t\tdev_err(dev, \"failed to create PHY\\n\");\n\t\treturn PTR_ERR(generic_phy);\n\t}\n\n\tphy_set_drvdata(generic_phy, pciephy);\n\tphy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);\n\n\treturn PTR_ERR_OR_ZERO(phy_provider);\n}\n\nstatic const struct of_device_id oxnas_pcie_phy_id_table[] = {\n\t{ .compatible = \"oxsemi,ox820-pcie-phy\" },\n\t{ },\n};\n\nstatic struct platform_driver oxnas_pcie_phy_driver = {\n\t.probe\t\t= oxnas_pcie_phy_probe,\n\t.driver\t\t= {\n\t\t.name\t\t= \"ox820-pcie-phy\",\n\t\t.of_match_table\t= oxnas_pcie_phy_id_table,\n\t},\n};\n\nbuiltin_platform_driver(oxnas_pcie_phy_driver);\n"
  },
  {
    "path": "target/linux/oxnas/files/drivers/power/reset/oxnas-restart.c",
    "content": "// SPDX-License-Identifier: (GPL-2.0)\n/*\n * oxnas SoC reset driver\n * based on:\n * Microsemi MIPS SoC reset driver\n * and ox820_assert_system_reset() written by Ma Hajun <mahaijuns@gmail.com>\n *\n * License: GPL\n * Copyright (c) 2013 Ma Hajun <mahaijuns@gmail.com>\n * Copyright (c) 2017 Microsemi Corporation\n * Copyright (c) 2019 Daniel Golle <daniel@makrotopia.org>\n */\n#include <linux/delay.h>\n#include <linux/io.h>\n#include <linux/notifier.h>\n#include <linux/mfd/syscon.h>\n#include <linux/of_address.h>\n#include <linux/of_device.h>\n#include <linux/platform_device.h>\n#include <linux/reboot.h>\n#include <linux/regmap.h>\n\n/* bit numbers of reset control register */\n#define OX820_SYS_CTRL_RST_SCU                0\n#define OX820_SYS_CTRL_RST_COPRO              1\n#define OX820_SYS_CTRL_RST_ARM0               2\n#define OX820_SYS_CTRL_RST_ARM1               3\n#define OX820_SYS_CTRL_RST_USBHS              4\n#define OX820_SYS_CTRL_RST_USBHSPHYA          5\n#define OX820_SYS_CTRL_RST_MACA               6\n#define OX820_SYS_CTRL_RST_MAC                OX820_SYS_CTRL_RST_MACA\n#define OX820_SYS_CTRL_RST_PCIEA              7\n#define OX820_SYS_CTRL_RST_SGDMA              8\n#define OX820_SYS_CTRL_RST_CIPHER             9\n#define OX820_SYS_CTRL_RST_DDR                10\n#define OX820_SYS_CTRL_RST_SATA               11\n#define OX820_SYS_CTRL_RST_SATA_LINK          12\n#define OX820_SYS_CTRL_RST_SATA_PHY           13\n#define OX820_SYS_CTRL_RST_PCIEPHY            14\n#define OX820_SYS_CTRL_RST_STATIC             15\n#define OX820_SYS_CTRL_RST_GPIO               16\n#define OX820_SYS_CTRL_RST_UART1              17\n#define OX820_SYS_CTRL_RST_UART2              18\n#define OX820_SYS_CTRL_RST_MISC               19\n#define OX820_SYS_CTRL_RST_I2S                20\n#define OX820_SYS_CTRL_RST_SD                 21\n#define OX820_SYS_CTRL_RST_MACB               22\n#define OX820_SYS_CTRL_RST_PCIEB              23\n#define OX820_SYS_CTRL_RST_VIDEO              24\n#define OX820_SYS_CTRL_RST_DDR_PHY            25\n#define OX820_SYS_CTRL_RST_USBHSPHYB          26\n#define OX820_SYS_CTRL_RST_USBDEV             27\n#define OX820_SYS_CTRL_RST_ARMDBG             29\n#define OX820_SYS_CTRL_RST_PLLA               30\n#define OX820_SYS_CTRL_RST_PLLB               31\n\n/* bit numbers of clock control register */\n#define OX820_SYS_CTRL_CLK_COPRO              0\n#define OX820_SYS_CTRL_CLK_DMA                1\n#define OX820_SYS_CTRL_CLK_CIPHER             2\n#define OX820_SYS_CTRL_CLK_SD                 3\n#define OX820_SYS_CTRL_CLK_SATA               4\n#define OX820_SYS_CTRL_CLK_I2S                5\n#define OX820_SYS_CTRL_CLK_USBHS              6\n#define OX820_SYS_CTRL_CLK_MACA               7\n#define OX820_SYS_CTRL_CLK_MAC                OX820_SYS_CTRL_CLK_MACA\n#define OX820_SYS_CTRL_CLK_PCIEA              8\n#define OX820_SYS_CTRL_CLK_STATIC             9\n#define OX820_SYS_CTRL_CLK_MACB               10\n#define OX820_SYS_CTRL_CLK_PCIEB              11\n#define OX820_SYS_CTRL_CLK_REF600             12\n#define OX820_SYS_CTRL_CLK_USBDEV             13\n#define OX820_SYS_CTRL_CLK_DDR                14\n#define OX820_SYS_CTRL_CLK_DDRPHY             15\n#define OX820_SYS_CTRL_CLK_DDRCK              16\n\n/* Regmap offsets */\n#define OX820_CLK_SET_REGOFFSET               0x2c\n#define OX820_CLK_CLR_REGOFFSET               0x30\n#define OX820_RST_SET_REGOFFSET               0x34\n#define OX820_RST_CLR_REGOFFSET               0x38\n#define OX820_SECONDARY_SEL_REGOFFSET         0x14\n#define OX820_TERTIARY_SEL_REGOFFSET          0x8c\n#define OX820_QUATERNARY_SEL_REGOFFSET        0x94\n#define OX820_DEBUG_SEL_REGOFFSET             0x9c\n#define OX820_ALTERNATIVE_SEL_REGOFFSET       0xa4\n#define OX820_PULLUP_SEL_REGOFFSET            0xac\n#define OX820_SEC_SECONDARY_SEL_REGOFFSET     0x100014\n#define OX820_SEC_TERTIARY_SEL_REGOFFSET      0x10008c\n#define OX820_SEC_QUATERNARY_SEL_REGOFFSET    0x100094\n#define OX820_SEC_DEBUG_SEL_REGOFFSET         0x10009c\n#define OX820_SEC_ALTERNATIVE_SEL_REGOFFSET   0x1000a4\n#define OX820_SEC_PULLUP_SEL_REGOFFSET        0x1000ac\n\n\nstruct oxnas_restart_context {\n\tstruct regmap *sys_ctrl;\n\tstruct notifier_block restart_handler;\n};\n\nstatic int ox820_restart_handle(struct notifier_block *this,\n\t\t\t\t unsigned long mode, void *cmd)\n{\n\tstruct oxnas_restart_context *ctx = container_of(this, struct\n\t\t\t\t\t\t\toxnas_restart_context,\n\t\t\t\t\t\t\trestart_handler);\n\tu32 value;\n\n\t/* Assert reset to cores as per power on defaults\n\t * Don't touch the DDR interface as things will come to an impromptu stop\n\t * NB Possibly should be asserting reset for PLLB, but there are timing\n\t *    concerns here according to the docs */\n\tvalue = BIT(OX820_SYS_CTRL_RST_COPRO)\t\t|\n\t\tBIT(OX820_SYS_CTRL_RST_USBHS)\t\t|\n\t\tBIT(OX820_SYS_CTRL_RST_USBHSPHYA)\t|\n\t\tBIT(OX820_SYS_CTRL_RST_MACA)\t\t|\n\t\tBIT(OX820_SYS_CTRL_RST_PCIEA)\t\t|\n\t\tBIT(OX820_SYS_CTRL_RST_SGDMA)\t\t|\n\t\tBIT(OX820_SYS_CTRL_RST_CIPHER)\t\t|\n\t\tBIT(OX820_SYS_CTRL_RST_SATA)\t\t|\n\t\tBIT(OX820_SYS_CTRL_RST_SATA_LINK)\t|\n\t\tBIT(OX820_SYS_CTRL_RST_SATA_PHY)\t|\n\t\tBIT(OX820_SYS_CTRL_RST_PCIEPHY)\t\t|\n\t\tBIT(OX820_SYS_CTRL_RST_STATIC)\t\t|\n\t\tBIT(OX820_SYS_CTRL_RST_UART1)\t\t|\n\t\tBIT(OX820_SYS_CTRL_RST_UART2)\t\t|\n\t\tBIT(OX820_SYS_CTRL_RST_MISC)\t\t|\n\t\tBIT(OX820_SYS_CTRL_RST_I2S)\t\t|\n\t\tBIT(OX820_SYS_CTRL_RST_SD)\t\t|\n\t\tBIT(OX820_SYS_CTRL_RST_MACB)\t\t|\n\t\tBIT(OX820_SYS_CTRL_RST_PCIEB)\t\t|\n\t\tBIT(OX820_SYS_CTRL_RST_VIDEO)\t\t|\n\t\tBIT(OX820_SYS_CTRL_RST_USBHSPHYB)\t|\n\t\tBIT(OX820_SYS_CTRL_RST_USBDEV);\n\n\tregmap_write(ctx->sys_ctrl, OX820_RST_SET_REGOFFSET, value);\n\n\t/* Release reset to cores as per power on defaults */\n\tregmap_write(ctx->sys_ctrl, OX820_RST_CLR_REGOFFSET, BIT(OX820_SYS_CTRL_RST_GPIO));\n\n\t/* Disable clocks to cores as per power-on defaults - must leave DDR\n\t * related clocks enabled otherwise we'll stop rather abruptly. */\n\tvalue =\n\t\tBIT(OX820_SYS_CTRL_CLK_COPRO)\t\t|\n\t\tBIT(OX820_SYS_CTRL_CLK_DMA)\t\t|\n\t\tBIT(OX820_SYS_CTRL_CLK_CIPHER)\t\t|\n\t\tBIT(OX820_SYS_CTRL_CLK_SD)\t\t|\n\t\tBIT(OX820_SYS_CTRL_CLK_SATA)\t\t|\n\t\tBIT(OX820_SYS_CTRL_CLK_I2S)\t\t|\n\t\tBIT(OX820_SYS_CTRL_CLK_USBHS)\t\t|\n\t\tBIT(OX820_SYS_CTRL_CLK_MAC)\t\t|\n\t\tBIT(OX820_SYS_CTRL_CLK_PCIEA)\t\t|\n\t\tBIT(OX820_SYS_CTRL_CLK_STATIC)\t\t|\n\t\tBIT(OX820_SYS_CTRL_CLK_MACB)\t\t|\n\t\tBIT(OX820_SYS_CTRL_CLK_PCIEB)\t\t|\n\t\tBIT(OX820_SYS_CTRL_CLK_REF600)\t\t|\n\t\tBIT(OX820_SYS_CTRL_CLK_USBDEV);\n\n\tregmap_write(ctx->sys_ctrl, OX820_CLK_CLR_REGOFFSET, value);\n\n\t/* Enable clocks to cores as per power-on defaults */\n\n\t/* Set sys-control pin mux'ing as per power-on defaults */\n\tregmap_write(ctx->sys_ctrl, OX820_SECONDARY_SEL_REGOFFSET, 0);\n\tregmap_write(ctx->sys_ctrl, OX820_TERTIARY_SEL_REGOFFSET, 0);\n\tregmap_write(ctx->sys_ctrl, OX820_QUATERNARY_SEL_REGOFFSET, 0);\n\tregmap_write(ctx->sys_ctrl, OX820_DEBUG_SEL_REGOFFSET, 0);\n\tregmap_write(ctx->sys_ctrl, OX820_ALTERNATIVE_SEL_REGOFFSET, 0);\n\tregmap_write(ctx->sys_ctrl, OX820_PULLUP_SEL_REGOFFSET, 0);\n\n\tregmap_write(ctx->sys_ctrl, OX820_SEC_SECONDARY_SEL_REGOFFSET, 0);\n\tregmap_write(ctx->sys_ctrl, OX820_SEC_TERTIARY_SEL_REGOFFSET, 0);\n\tregmap_write(ctx->sys_ctrl, OX820_SEC_QUATERNARY_SEL_REGOFFSET, 0);\n\tregmap_write(ctx->sys_ctrl, OX820_SEC_DEBUG_SEL_REGOFFSET, 0);\n\tregmap_write(ctx->sys_ctrl, OX820_SEC_ALTERNATIVE_SEL_REGOFFSET, 0);\n\tregmap_write(ctx->sys_ctrl, OX820_SEC_PULLUP_SEL_REGOFFSET, 0);\n\n\t/* No need to save any state, as the ROM loader can determine whether\n\t * reset is due to power cycling or programatic action, just hit the\n\t * (self-clearing) CPU reset bit of the block reset register */\n\tvalue =\n\t\tBIT(OX820_SYS_CTRL_RST_SCU) |\n\t\tBIT(OX820_SYS_CTRL_RST_ARM0) |\n\t\tBIT(OX820_SYS_CTRL_RST_ARM1);\n\n\tregmap_write(ctx->sys_ctrl, OX820_RST_SET_REGOFFSET, value);\n\n\tpr_emerg(\"Unable to restart system\\n\");\n\treturn NOTIFY_DONE;\n}\n\nstatic int ox820_restart_probe(struct platform_device *pdev)\n{\n\tstruct oxnas_restart_context *ctx;\n\tstruct regmap *sys_ctrl;\n\tstruct device *dev = &pdev->dev;\n\tint err = 0;\n\n\tsys_ctrl = syscon_node_to_regmap(pdev->dev.of_node);\n\tif (IS_ERR(sys_ctrl))\n\t\treturn PTR_ERR(sys_ctrl);\n\n\tctx = devm_kzalloc(&pdev->dev, sizeof(*ctx), GFP_KERNEL);\n\tif (!ctx)\n\t\treturn -ENOMEM;\n\n\tctx->sys_ctrl = sys_ctrl;\n\tctx->restart_handler.notifier_call = ox820_restart_handle;\n\tctx->restart_handler.priority = 192;\n\terr = register_restart_handler(&ctx->restart_handler);\n\tif (err)\n\t\tdev_err(dev, \"can't register restart notifier (err=%d)\\n\", err);\n\n\treturn err;\n}\n\nstatic const struct of_device_id ox820_restart_of_match[] = {\n\t{ .compatible = \"oxsemi,ox820-sys-ctrl\" },\n\t{}\n};\n\nstatic struct platform_driver ox820_restart_driver = {\n\t.probe = ox820_restart_probe,\n\t.driver = {\n\t\t.name = \"ox820-chip-reset\",\n\t\t.of_match_table = ox820_restart_of_match,\n\t},\n};\nbuiltin_platform_driver(ox820_restart_driver);\n"
  },
  {
    "path": "target/linux/oxnas/files/drivers/usb/host/ehci-oxnas.c",
    "content": "/*\n * drivers/usb/host/ehci-oxnas.c\n *\n * Tzachi Perelstein <tzachi@marvell.com>\n *\n * This file is licensed under  the terms of the GNU General Public\n * License version 2. This program is licensed \"as is\" without any\n * warranty of any kind, whether express or implied.\n */\n\n#include <linux/kernel.h>\n#include <linux/module.h>\n#include <linux/platform_device.h>\n#include <linux/of.h>\n#include <linux/of_address.h>\n#include <linux/of_irq.h>\n#include <linux/mfd/syscon.h>\n#include <linux/usb.h>\n#include <linux/usb/hcd.h>\n#include <linux/dma-mapping.h>\n#include <linux/clk.h>\n#include <linux/regmap.h>\n#include <linux/reset.h>\n\n#define USBHSMPH_CTRL_REGOFFSET\t\t0x40\n#define USBHSMPH_STAT_REGOFFSET\t\t0x44\n#define REF300_DIV_REGOFFSET\t\t0xF8\n#define USBHSPHY_CTRL_REGOFFSET\t\t0x84\n#define USB_CTRL_REGOFFSET\t\t0x90\n#define PLLB_DIV_CTRL_REGOFFSET\t\t0x1000F8\n#define USBHSPHY_SUSPENDM_MANUAL_ENABLE\t\t16\n#define USBHSPHY_SUSPENDM_MANUAL_STATE\t\t15\n#define USBHSPHY_ATE_ESET\t\t\t14\n#define USBHSPHY_TEST_DIN\t\t\t6\n#define USBHSPHY_TEST_ADD\t\t\t2\n#define USBHSPHY_TEST_DOUT_SEL\t\t\t1\n#define USBHSPHY_TEST_CLK\t\t\t0\n\n#define USB_CTRL_USBAPHY_CKSEL_SHIFT\t5\n#define USB_CLK_XTAL0_XTAL1\t\t(0 << USB_CTRL_USBAPHY_CKSEL_SHIFT)\n#define USB_CLK_XTAL0\t\t\t(1 << USB_CTRL_USBAPHY_CKSEL_SHIFT)\n#define USB_CLK_INTERNAL\t\t(2 << USB_CTRL_USBAPHY_CKSEL_SHIFT)\n\n#define USBAMUX_DEVICE\t\t\tBIT(4)\n\n#define USBPHY_REFCLKDIV_SHIFT\t\t2\n#define USB_PHY_REF_12MHZ\t\t(0 << USBPHY_REFCLKDIV_SHIFT)\n#define USB_PHY_REF_24MHZ\t\t(1 << USBPHY_REFCLKDIV_SHIFT)\n#define USB_PHY_REF_48MHZ\t\t(2 << USBPHY_REFCLKDIV_SHIFT)\n\n#define USB_CTRL_USB_CKO_SEL_BIT\t0\n\n#define USB_INT_CLK_XTAL\t\t0\n#define USB_INT_CLK_REF300\t\t2\n#define USB_INT_CLK_PLLB\t\t3\n\n#define REF300_DIV_INT_SHIFT            8\n#define REF300_DIV_FRAC_SHIFT           0\n#define REF300_DIV_INT(val)             ((val) << REF300_DIV_INT_SHIFT)\n#define REF300_DIV_FRAC(val)            ((val) << REF300_DIV_FRAC_SHIFT)\n\n#define PLLB_BYPASS                     1\n#define PLLB_ENSAT                      3\n#define PLLB_OUTDIV                     4\n#define PLLB_REFDIV                     8\n#define PLLB_DIV_INT_SHIFT              8\n#define PLLB_DIV_FRAC_SHIFT             0\n#define PLLB_DIV_INT(val)               ((val) << PLLB_DIV_INT_SHIFT)\n#define PLLB_DIV_FRAC(val)              ((val) << PLLB_DIV_FRAC_SHIFT)\n\n#include \"ehci.h\"\n\nstruct oxnas_hcd {\n\tstruct clk *clk;\n\tstruct clk *refsrc;\n\tstruct clk *phyref;\n\tint use_pllb;\n\tint use_phya;\n\tstruct reset_control *rst_host;\n\tstruct reset_control *rst_phya;\n\tstruct reset_control *rst_phyb;\n\tstruct regmap *syscon;\n};\n\n#define DRIVER_DESC \"Oxnas On-Chip EHCI Host Controller\"\n\nstatic struct hc_driver __read_mostly oxnas_hc_driver;\n\nstatic void start_oxnas_usb_ehci(struct oxnas_hcd *oxnas)\n{\n\tif (oxnas->use_pllb) {\n\t\t/* enable pllb */\n\t\tclk_prepare_enable(oxnas->refsrc);\n\t\t/* enable ref600 */\n\t\tclk_prepare_enable(oxnas->phyref);\n\t\t/* 600MHz pllb divider for 12MHz */\n\t\tregmap_write_bits(oxnas->syscon, PLLB_DIV_CTRL_REGOFFSET, 0xffff, PLLB_DIV_INT(50) | PLLB_DIV_FRAC(0));\n\t} else {\n\t\t/* ref 300 divider for 12MHz */\n\t\tregmap_write_bits(oxnas->syscon, REF300_DIV_REGOFFSET, 0xffff, REF300_DIV_INT(25) | REF300_DIV_FRAC(0));\n\t}\n\n\t/* Ensure the USB block is properly reset */\n\treset_control_reset(oxnas->rst_host);\n\treset_control_reset(oxnas->rst_phya);\n\treset_control_reset(oxnas->rst_phyb);\n\n\t/* Force the high speed clock to be generated all the time, via serial\n\t programming of the USB HS PHY */\n\tregmap_write_bits(oxnas->syscon, USBHSPHY_CTRL_REGOFFSET, 0xffff,\n\t\t\t  (2UL << USBHSPHY_TEST_ADD) |\n\t\t\t  (0xe0UL << USBHSPHY_TEST_DIN));\n\n\tregmap_write_bits(oxnas->syscon, USBHSPHY_CTRL_REGOFFSET, 0xffff,\n\t\t\t  (1UL << USBHSPHY_TEST_CLK) |\n\t\t\t  (2UL << USBHSPHY_TEST_ADD) |\n\t\t\t  (0xe0UL << USBHSPHY_TEST_DIN));\n\n\tregmap_write_bits(oxnas->syscon, USBHSPHY_CTRL_REGOFFSET, 0xffff,\n\t\t\t  (0xfUL << USBHSPHY_TEST_ADD) |\n\t\t\t  (0xaaUL << USBHSPHY_TEST_DIN));\n\n\tregmap_write_bits(oxnas->syscon, USBHSPHY_CTRL_REGOFFSET, 0xffff,\n\t\t\t  (1UL << USBHSPHY_TEST_CLK) |\n\t\t\t  (0xfUL << USBHSPHY_TEST_ADD) |\n\t\t\t  (0xaaUL << USBHSPHY_TEST_DIN));\n\n\tif (oxnas->use_pllb) /* use pllb clock */\n\t\tregmap_write_bits(oxnas->syscon, USB_CTRL_REGOFFSET, 0xffff,\n\t\t\t\t  USB_CLK_INTERNAL | USB_INT_CLK_PLLB);\n\telse /* use ref300 derived clock */\n\t\tregmap_write_bits(oxnas->syscon, USB_CTRL_REGOFFSET, 0xffff,\n\t\t\t\t  USB_CLK_INTERNAL | USB_INT_CLK_REF300);\n\n\tif (oxnas->use_phya) {\n\t\t/* Configure USB PHYA as a host */\n\t\tregmap_update_bits(oxnas->syscon, USB_CTRL_REGOFFSET, USBAMUX_DEVICE, 0);\n\t}\n\n\t/* Enable the clock to the USB block */\n\tclk_prepare_enable(oxnas->clk);\n}\n\nstatic void stop_oxnas_usb_ehci(struct oxnas_hcd *oxnas)\n{\n\treset_control_assert(oxnas->rst_host);\n\treset_control_assert(oxnas->rst_phya);\n\treset_control_assert(oxnas->rst_phyb);\n\n\tif (oxnas->use_pllb) {\n\t\tclk_disable_unprepare(oxnas->phyref);\n\t\tclk_disable_unprepare(oxnas->refsrc);\n\t}\n\tclk_disable_unprepare(oxnas->clk);\n}\n\nstatic int ehci_oxnas_reset(struct usb_hcd *hcd)\n{\n\t#define  txttfill_tuning\treserved2[0]\n\n\tstruct ehci_hcd\t*ehci;\n\tu32 tmp;\n\tint retval = ehci_setup(hcd);\n\tif (retval)\n\t\treturn retval;\n\n\tehci = hcd_to_ehci(hcd);\n\ttmp = ehci_readl(ehci, &ehci->regs->txfill_tuning);\n\ttmp &= ~0x00ff0000;\n\ttmp |= 0x003f0000; /* set burst pre load count to 0x40 (63 * 4 bytes)  */\n\ttmp |= 0x16; /* set sheduler overhead to 22 * 1.267us (HS) or 22 * 6.33us (FS/LS)*/\n\tehci_writel(ehci, tmp,  &ehci->regs->txfill_tuning);\n\n\ttmp = ehci_readl(ehci, &ehci->regs->txttfill_tuning);\n\ttmp |= 0x2; /* set sheduler overhead to 2 * 6.333us */\n\tehci_writel(ehci, tmp,  &ehci->regs->txttfill_tuning);\n\n\treturn retval;\n}\n\nstatic int ehci_oxnas_drv_probe(struct platform_device *ofdev)\n{\n\tstruct device_node *np = ofdev->dev.of_node;\n\tstruct usb_hcd *hcd;\n\tstruct ehci_hcd *ehci;\n\tstruct resource res;\n\tstruct oxnas_hcd *oxnas;\n\tint irq, err;\n\tstruct reset_control *rstc;\n\n\tif (usb_disabled())\n\t\treturn -ENODEV;\n\n\tif (!ofdev->dev.dma_mask)\n\t\tofdev->dev.dma_mask = &ofdev->dev.coherent_dma_mask;\n\tif (!ofdev->dev.coherent_dma_mask)\n\t\tofdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);\n\n\thcd = usb_create_hcd(&oxnas_hc_driver,\t&ofdev->dev,\n\t\t\t\t\tdev_name(&ofdev->dev));\n\tif (!hcd)\n\t\treturn -ENOMEM;\n\n\terr = of_address_to_resource(np, 0, &res);\n\tif (err)\n\t\tgoto err_res;\n\n\thcd->rsrc_start = res.start;\n\thcd->rsrc_len = resource_size(&res);\n\n\thcd->regs = devm_ioremap_resource(&ofdev->dev, &res);\n\tif (IS_ERR(hcd->regs)) {\n\t\tdev_err(&ofdev->dev, \"devm_ioremap_resource failed\\n\");\n\t\terr = PTR_ERR(hcd->regs);\n\t\tgoto err_ioremap;\n\t}\n\n\toxnas = (struct oxnas_hcd *)hcd_to_ehci(hcd)->priv;\n\n\toxnas->use_pllb = of_property_read_bool(np, \"oxsemi,ehci_use_pllb\");\n\toxnas->use_phya = of_property_read_bool(np, \"oxsemi,ehci_use_phya\");\n\n\toxnas->syscon = syscon_regmap_lookup_by_phandle(np, \"oxsemi,sys-ctrl\");\n\tif (IS_ERR(oxnas->syscon)) {\n\t\terr = PTR_ERR(oxnas->syscon);\n\t\tgoto err_syscon;\n\t}\n\n\toxnas->clk = of_clk_get_by_name(np, \"usb\");\n\tif (IS_ERR(oxnas->clk)) {\n\t\terr = PTR_ERR(oxnas->clk);\n\t\tgoto err_clk;\n\t}\n\n\tif (oxnas->use_pllb) {\n\t\toxnas->refsrc = of_clk_get_by_name(np, \"refsrc\");\n\t\tif (IS_ERR(oxnas->refsrc)) {\n\t\t\terr = PTR_ERR(oxnas->refsrc);\n\t\t\tgoto err_refsrc;\n\t\t}\n\t\toxnas->phyref = of_clk_get_by_name(np, \"phyref\");\n\t\tif (IS_ERR(oxnas->refsrc)) {\n\t\t\terr = PTR_ERR(oxnas->refsrc);\n\t\t\tgoto err_phyref;\n\t\t}\n\n\t} else {\n\t\toxnas->refsrc = NULL;\n\t\toxnas->phyref = NULL;\n\t}\n\n\trstc = devm_reset_control_get(&ofdev->dev, \"host\");\n\tif (IS_ERR(rstc)) {\n\t\terr = PTR_ERR(rstc);\n\t\tgoto err_rst;\n\t}\n\toxnas->rst_host = rstc;\n\n\trstc = devm_reset_control_get(&ofdev->dev, \"phya\");\n\tif (IS_ERR(rstc)) {\n\t\terr = PTR_ERR(rstc);\n\t\tgoto err_rst;\n\t}\n\toxnas->rst_phya = rstc;\n\n\trstc = devm_reset_control_get(&ofdev->dev, \"phyb\");\n\tif (IS_ERR(rstc)) {\n\t\terr = PTR_ERR(rstc);\n\t\tgoto err_rst;\n\t}\n\toxnas->rst_phyb = rstc;\n\n\tirq = irq_of_parse_and_map(np, 0);\n\tif (!irq) {\n\t\tdev_err(&ofdev->dev, \"irq_of_parse_and_map failed\\n\");\n\t\terr = -EBUSY;\n\t\tgoto err_irq;\n\t}\n\n\thcd->has_tt = 1;\n\tehci = hcd_to_ehci(hcd);\n\tehci->caps = hcd->regs;\n\n\tstart_oxnas_usb_ehci(oxnas);\n\n\terr = usb_add_hcd(hcd, irq, IRQF_SHARED);\n\tif (err)\n\t\tgoto err_hcd;\n\n\treturn 0;\n\nerr_hcd:\n\tstop_oxnas_usb_ehci(oxnas);\nerr_irq:\nerr_rst:\n\tif (oxnas->phyref)\n\t\tclk_put(oxnas->phyref);\nerr_phyref:\n\tif (oxnas->refsrc)\n\t\tclk_put(oxnas->refsrc);\nerr_refsrc:\n\tclk_put(oxnas->clk);\nerr_syscon:\nerr_clk:\nerr_ioremap:\nerr_res:\n\tusb_put_hcd(hcd);\n\n\treturn err;\n}\n\nstatic int ehci_oxnas_drv_remove(struct platform_device *pdev)\n{\n\tstruct usb_hcd *hcd = platform_get_drvdata(pdev);\n\tstruct oxnas_hcd *oxnas = (struct oxnas_hcd *)hcd_to_ehci(hcd)->priv;\n\n\tusb_remove_hcd(hcd);\n\tif (oxnas->use_pllb) {\n\t\tclk_disable_unprepare(oxnas->phyref);\n\t\tclk_put(oxnas->phyref);\n\t\tclk_disable_unprepare(oxnas->refsrc);\n\t\tclk_put(oxnas->refsrc);\n\t}\n\tclk_disable_unprepare(oxnas->clk);\n\tusb_put_hcd(hcd);\n\n\treturn 0;\n}\n\nstatic const struct of_device_id oxnas_ehci_dt_ids[] = {\n\t{ .compatible = \"plxtech,nas782x-ehci\" },\n\t{ /* sentinel */ }\n};\n\nMODULE_DEVICE_TABLE(of, oxnas_ehci_dt_ids);\n\nstatic struct platform_driver ehci_oxnas_driver = {\n\t.probe\t\t= ehci_oxnas_drv_probe,\n\t.remove\t\t= ehci_oxnas_drv_remove,\n\t.shutdown\t= usb_hcd_platform_shutdown,\n\t.driver.name\t= \"oxnas-ehci\",\n\t.driver.of_match_table\t= oxnas_ehci_dt_ids,\n};\n\nstatic const struct ehci_driver_overrides oxnas_overrides __initconst = {\n\t.reset = ehci_oxnas_reset,\n\t.extra_priv_size = sizeof(struct oxnas_hcd),\n};\n\nstatic int __init ehci_oxnas_init(void)\n{\n\tif (usb_disabled())\n\t\treturn -ENODEV;\n\n\tehci_init_driver(&oxnas_hc_driver, &oxnas_overrides);\n\treturn platform_driver_register(&ehci_oxnas_driver);\n}\nmodule_init(ehci_oxnas_init);\n\nstatic void __exit ehci_oxnas_cleanup(void)\n{\n\tplatform_driver_unregister(&ehci_oxnas_driver);\n}\nmodule_exit(ehci_oxnas_cleanup);\n\nMODULE_DESCRIPTION(DRIVER_DESC);\nMODULE_ALIAS(\"platform:oxnas-ehci\");\nMODULE_LICENSE(\"GPL\");\n"
  },
  {
    "path": "target/linux/oxnas/image/Makefile",
    "content": "include $(TOPDIR)/rules.mk\ninclude $(INCLUDE_DIR)/image.mk\n\nVMLINUX:=$(BIN_DIR)/$(IMG_PREFIX)-vmlinux\nUIMAGE:=$(BIN_DIR)/$(IMG_PREFIX)-uImage\n\ninclude $(SUBTARGET).mk\n\n$(eval $(call BuildImage))\n"
  },
  {
    "path": "target/linux/oxnas/image/ox810se.mk",
    "content": "KERNEL_LOADADDR := 0x48008000\n\ndefine Device/Default\n  KERNEL_NAME := zImage\n  KERNEL_SUFFIX := -uImage\n  KERNEL_INSTALL := 1\n  FILESYSTEMS := squashfs ext4\n  PROFILES := Default\n  DEVICE_DTS := ox810se-$(subst _,-,$(1))\n  IMAGES := sysupgrade.tar\n  IMAGE/sysupgrade.tar := sysupgrade-tar | append-metadata\nendef\n\ndefine Device/wd_mbwe\n  DEVICE_VENDOR := Western Digital\n  DEVICE_MODEL := My Book\n  DEVICE_VARIANT := World Edition\n  KERNEL := kernel-bin | append-dtb | uImage none\nendef\nTARGET_DEVICES += wd_mbwe\n"
  },
  {
    "path": "target/linux/oxnas/image/ox820.mk",
    "content": "UBIFS_OPTS := -m 2048 -e 126KiB -c 4096\nKERNEL_LOADADDR := 0x60008000\n\ndefine Device/Default\n  KERNEL_NAME := zImage\n  KERNEL_SUFFIX := -uImage\n  KERNEL_INSTALL := 1\n  BLOCKSIZE := 128k\n  PAGESIZE := 2048\n  SUBPAGESIZE := 512\n  FILESYSTEMS := squashfs ubifs\n  PROFILES := Default\n  DEVICE_DTS := ox820-$(subst _,-,$(1))\n  KERNEL := kernel-bin | append-dtb | uImage none\n  IMAGES := ubinized.bin sysupgrade.tar\n  IMAGE/ubinized.bin := append-ubi\n  IMAGE/sysupgrade.tar := sysupgrade-tar | append-metadata\nendef\n\ndefine Build/omninas-factory\n\trm -rf $@.tmp $@.dummy $@.dummy.gz\n\tmkdir -p $@.tmp\n\t$(CP) $@ $@.tmp/uImage\n\tdd if=/dev/zero bs=64k count=4 of=$@.dummy\n\tgzip $@.dummy\n\tmkimage -A arm -T ramdisk -C gzip -n \"dummy\" \\\n\t\t-d $@.dummy.gz \\\n\t\t$@.tmp/rdimg.gz\n\techo 2.35.20140102 > $@.tmp/version ; echo >> $@.tmp/version\n\tchmod 0744 $@.tmp/*\n\t$(TAR) -C $@.tmp -czvf $@ \\\n\t\t$(if $(SOURCE_DATE_EPOCH),--mtime=\"@$(SOURCE_DATE_EPOCH)\") .\nendef\n\ndefine Build/encrypt-3des\n\topenssl enc -des3 -a -k $(1) -in $@ -out $@.new && mv $@.new $@\nendef\n\ndefine Device/akitio_mycloud\n  DEVICE_VENDOR := Akitio\n  DEVICE_MODEL := MyCloud Mini\n  SUPPORTED_DEVICES += akitio\n  DEVICE_PACKAGES := kmod-ata-oxnas-sata kmod-i2c-gpio kmod-rtc-ds1307 \\\n\tkmod-usb2-oxnas kmod-usb-ledtrig-usbport\nendef\nTARGET_DEVICES += akitio_mycloud\n\ndefine Device/cloudengines_pogoplugpro\n  DEVICE_VENDOR := Cloud Engines\n  DEVICE_MODEL := PogoPlug Pro (with mPCIe)\n  SUPPORTED_DEVICES += pogoplug-pro\n  DEVICE_PACKAGES := kmod-usb2-oxnas kmod-usb-ledtrig-usbport \\\n\tkmod-ata-oxnas-sata kmod-rt2800-pci wpad-basic-wolfssl\nendef\nTARGET_DEVICES += cloudengines_pogoplugpro\n\ndefine Device/cloudengines_pogoplug-series-3\n  DEVICE_VENDOR := Cloud Engines\n  DEVICE_MODEL := PogoPlug Series V3 (without mPCIe)\n  SUPPORTED_DEVICES += cloudengines,pogoplugv3 pogoplug-v3\n  DEVICE_PACKAGES := kmod-usb2-oxnas kmod-usb-ledtrig-usbport \\\n\tkmod-ata-oxnas-sata\nendef\nTARGET_DEVICES += cloudengines_pogoplug-series-3\n\ndefine Device/shuttle_kd20\n  DEVICE_VENDOR := Shuttle\n  DEVICE_MODEL := KD20\n  SUPPORTED_DEVICES += kd20\n  DEVICE_PACKAGES := kmod-usb2-oxnas kmod-usb3 kmod-usb-ledtrig-usbport \\\n\tkmod-i2c-gpio kmod-rtc-pcf8563 kmod-gpio-beeper kmod-hwmon-drivetemp \\\n\tkmod-hwmon-gpiofan kmod-ata-oxnas-sata kmod-md-mod kmod-md-raid0 \\\n\tkmod-md-raid1 kmod-fs-ext4 kmod-fs-xfs\nendef\nTARGET_DEVICES += shuttle_kd20\n\ndefine Device/mitrastar_stg-212\n  DEVICE_VENDOR := MitraStar\n  DEVICE_MODEL := STG-212\n  SUPPORTED_DEVICES += stg212\n  DEVICE_PACKAGES := kmod-ata-oxnas-sata kmod-fs-ext4 kmod-fs-xfs \\\n\tkmod-usb2-oxnas kmod-usb-ledtrig-usbport\nendef\nTARGET_DEVICES += mitrastar_stg-212\n"
  },
  {
    "path": "target/linux/oxnas/modules.mk",
    "content": "define KernelPackage/ata-oxnas-sata\n  TITLE:=oxnas Serial ATA support\n  KCONFIG:=CONFIG_SATA_OXNAS\n  FILES:=$(LINUX_DIR)/drivers/ata/sata_oxnas.ko\n  AUTOLOAD:=$(call AutoLoad,41,sata_oxnas,1)\n  $(call AddDepends/ata,@TARGET_oxnas)\nendef\n\ndefine KernelPackage/ata-oxnas-sata/description\n SATA support for OX934 core found in the OX8xx/PLX782x SoCs\nendef\n\n$(eval $(call KernelPackage,ata-oxnas-sata))\n\n\ndefine KernelPackage/usb2-oxnas\n  TITLE:=OX820 EHCI driver\n  KCONFIG:=CONFIG_USB_EHCI_OXNAS\n  FILES:=$(LINUX_DIR)/drivers/usb/host/ehci-oxnas.ko\n  AUTOLOAD:=$(call AutoLoad,55,ehci-oxnas,1)\n  $(call AddDepends/usb,@TARGET_oxnas_ox820 +kmod-usb2)\nendef\n\ndefine KernelPackage/usb2-oxnas/description\n This driver provides USB Device Controller support for the\n EHCI USB host built-in to the OX820 SoC.\nendef\n\n$(eval $(call KernelPackage,usb2-oxnas))\n"
  },
  {
    "path": "target/linux/oxnas/ox810se/config-default",
    "content": "# CONFIG_CACHE_L2X0 is not set\nCONFIG_CPU_IDLE=y\nCONFIG_CPU_IDLE_GOV_MENU=y\nCONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y\n# CONFIG_DEBUG_UNCOMPRESS is not set\nCONFIG_EXT4_FS=y\nCONFIG_FS_MBCACHE=y\nCONFIG_MACH_OX810SE=y\n"
  },
  {
    "path": "target/linux/oxnas/ox810se/profiles/00-default.mk",
    "content": "define Profile/Default\n\tNAME:=Default Profile\n\tPRIORITY:=1\nendef\n\ndefine Profile/Default/Description\n\tDefault package set compatible with most boards.\nendef\n\n$(eval $(call Profile,Default))\n"
  },
  {
    "path": "target/linux/oxnas/ox810se/target.mk",
    "content": "FEATURES+=source-only\n\nSUBTARGET:=ox810se\nBOARDNAME:=OX810SE\nCPU_TYPE:=arm926ej-s\n\ndefine Target/Description\n    Oxford OX810SE\nendef\n"
  },
  {
    "path": "target/linux/oxnas/ox820/config-default",
    "content": "CONFIG_ARCH_HAS_TICK_BROADCAST=y\n# CONFIG_ARCH_MULTI_CPU_AUTO is not set\nCONFIG_ARCH_MULTI_V6=y\nCONFIG_ARCH_MULTI_V6_V7=y\nCONFIG_ARCH_WANT_LIBATA_LEDS=y\nCONFIG_ARM_GIC=y\nCONFIG_ARM_HEAVY_MB=y\nCONFIG_ATA_LEDS=y\nCONFIG_CACHE_L2X0=y\n# CONFIG_CACHE_L2X0_PMU is not set\nCONFIG_CPU_32v6=y\nCONFIG_CPU_32v6K=y\nCONFIG_CPU_ABRT_EV6=y\n# CONFIG_CPU_BPREDICT_DISABLE is not set\nCONFIG_CPU_CACHE_V6=y\nCONFIG_CPU_CACHE_VIPT=y\nCONFIG_CPU_COPY_V6=y\nCONFIG_CPU_HAS_ASID=y\n# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set\nCONFIG_CPU_IDLE=y\nCONFIG_CPU_IDLE_GOV_MENU=y\nCONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y\nCONFIG_CPU_PABRT_V6=y\nCONFIG_CPU_RMAP=y\nCONFIG_CPU_TLB_V6=y\nCONFIG_CPU_V6K=y\nCONFIG_DCACHE_WORD_ACCESS=y\nCONFIG_DEBUG_LL=y\nCONFIG_DEBUG_LL_INCLUDE=\"debug/8250.S\"\nCONFIG_DEBUG_LL_UART_8250=y\n# CONFIG_DEBUG_UART_8250 is not set\n# CONFIG_DEBUG_UART_8250_FLOW_CONTROL is not set\nCONFIG_DEBUG_UART_8250_SHIFT=0\nCONFIG_DEBUG_UART_PHYS=0x44200000\nCONFIG_DEBUG_UART_VIRT=0xf4200000\nCONFIG_DEBUG_UNCOMPRESS=y\nCONFIG_DMA_CACHE_RWFO=y\nCONFIG_FORCE_MAX_ZONEORDER=12\nCONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y\nCONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y\nCONFIG_HAVE_ARM_SCU=y\nCONFIG_HAVE_ARM_TWD=y\nCONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y\nCONFIG_HAVE_HW_BREAKPOINT=y\nCONFIG_HAVE_SMP=y\nCONFIG_HOTPLUG_CPU=y\nCONFIG_LOCK_SPIN_ON_OWNER=y\nCONFIG_MACH_OX820=y\nCONFIG_MIGHT_HAVE_CACHE_L2X0=y\nCONFIG_MIGHT_HAVE_PCI=y\n# CONFIG_MTD_CFI is not set\nCONFIG_MTD_CMDLINE_PARTS=y\n# CONFIG_MTD_COMPLEX_MAPPINGS is not set\nCONFIG_MTD_NAND=y\nCONFIG_MTD_NAND_ECC=y\nCONFIG_MTD_NAND_OXNAS=y\nCONFIG_MTD_RAW_NAND=y\nCONFIG_MTD_UBI=y\nCONFIG_MTD_UBI_BEB_LIMIT=20\nCONFIG_MTD_UBI_BLOCK=y\nCONFIG_MTD_UBI_WL_THRESHOLD=4096\nCONFIG_MUTEX_SPIN_ON_OWNER=y\nCONFIG_NET_FLOW_LIMIT=y\nCONFIG_NR_CPUS=16\nCONFIG_OUTER_CACHE=y\nCONFIG_OUTER_CACHE_SYNC=y\nCONFIG_PCI=y\nCONFIG_PCIEAER=y\nCONFIG_PCIEPORTBUS=y\nCONFIG_PCIE_OXNAS=y\nCONFIG_PCIE_PME=y\nCONFIG_PCI_DOMAINS=y\nCONFIG_PCI_DOMAINS_GENERIC=y\nCONFIG_PCI_MSI=y\nCONFIG_PCI_MSI_IRQ_DOMAIN=y\n# CONFIG_PL310_ERRATA_588369 is not set\n# CONFIG_PL310_ERRATA_727915 is not set\n# CONFIG_PL310_ERRATA_753970 is not set\n# CONFIG_PL310_ERRATA_769419 is not set\nCONFIG_PM_SLEEP_SMP=y\nCONFIG_RFS_ACCEL=y\nCONFIG_RPS=y\nCONFIG_RWSEM_SPIN_ON_OWNER=y\nCONFIG_SMP=y\nCONFIG_SMP_ON_UP=y\nCONFIG_TREE_RCU=y\nCONFIG_TREE_SRCU=y\nCONFIG_UBIFS_FS=y\nCONFIG_UBIFS_FS_SECURITY=y\nCONFIG_UNCOMPRESS_INCLUDE=\"debug/uncompress-ox820.h\"\nCONFIG_XPS=y\n"
  },
  {
    "path": "target/linux/oxnas/ox820/profiles/00-default.mk",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2016 OpenWrt.org\n\ndefine Profile/Default\n\tNAME:=Default Profile\n\tPRIORITY:=1\n\tPACKAGES:=\\\n\t\tkmod-i2c-gpio kmod-gpio-beeper kmod-hwmon-gpiofan \\\n\t\tkmod-rtc-pcf8563 kmod-rtc-ds1307 kmod-usb3\nendef\n\ndefine Profile/Default/Description\n\tDefault package set compatible with most boards.\nendef\n\n$(eval $(call Profile,Default))\n"
  },
  {
    "path": "target/linux/oxnas/ox820/target.mk",
    "content": "SUBTARGET:=ox820\nBOARDNAME:=OX820/NAS782x\nCPU_TYPE:=mpcore\nFEATURES+=nand pci pcie ubifs usb\n\ndefine Target/Description\n    Oxford/PLXTECH OX820/NAS782x\nendef"
  },
  {
    "path": "target/linux/oxnas/patches-5.10/010-pogoplug-series-3.patch",
    "content": "- add compatible string\n- add console to bootargs\n- add led aliases\n- adjust nand partition table\n---\n--- a/arch/arm/boot/dts/ox820-cloudengines-pogoplug-series-3.dts\n+++ b/arch/arm/boot/dts/ox820-cloudengines-pogoplug-series-3.dts\n@@ -11,10 +11,10 @@\n / {\n \tmodel = \"Cloud Engines PogoPlug Series 3\";\n \n-\tcompatible = \"cloudengines,pogoplugv3\", \"oxsemi,ox820\";\n+\tcompatible = \"cloudengines,pogoplug-series-3\", \"cloudengines,pogoplugv3\", \"oxsemi,ox820\";\n \n \tchosen {\n-\t\tbootargs = \"earlyprintk\";\n+\t\tbootargs = \"earlyprintk console=ttyS0,115200\";\n \t\tstdout-path = \"serial0:115200n8\";\n \t};\n \n@@ -27,24 +27,28 @@\n \t\tserial0 = &uart0;\n \t\tgpio0 = &gpio0;\n \t\tgpio1 = &gpio1;\n+\t\tled-boot = &led_status;\n+\t\tled-failsafe = &led_warn;\n+\t\tled-running = &led_act;\n+\t\tled-upgrade = &led_warn;\n \t};\n \n \tleds {\n \t\tcompatible = \"gpio-leds\";\n \n-\t\tblue {\n+\t\tled_status: blue {\n \t\t\tlabel = \"pogoplug:blue\";\n \t\t\tgpios = <&gpio0 2 0>;\n \t\t\tdefault-state = \"keep\";\n \t\t};\n \n-\t\torange {\n+\t\tled_warn: orange {\n \t\t\tlabel = \"pogoplug:orange\";\n \t\t\tgpios = <&gpio1 16 1>;\n \t\t\tdefault-state = \"keep\";\n \t\t};\n \n-\t\tgreen {\n+\t\tled_act: green {\n \t\t\tlabel = \"pogoplug:green\";\n \t\t\tgpios = <&gpio1 17 1>;\n \t\t\tdefault-state = \"keep\";\n@@ -73,11 +77,27 @@\n \t\tnand-ecc-algo = \"hamming\";\n \n \t\tpartition@0 {\n-\t\t\tlabel = \"boot\";\n-\t\t\treg = <0x00000000 0x00e00000>;\n+\t\t\tlabel = \"stage1\";\n+\t\t\treg = <0x00000000 0x00040000>;\n \t\t\tread-only;\n \t\t};\n \n+\t\tpartition@40000 {\n+\t\t\tlabel = \"u-boot\";\n+\t\t\treg = <0x00040000 0x00380000>;\n+\t\t\tread-only;\n+\t\t};\n+\n+\t\tpartition@3c0000 {\n+\t\t\tlabel = \"u-boot-env\";\n+\t\t\treg = <0x003c0000 0x00080000>;\n+\t\t};\n+\n+\t\tpartition@440000 {\n+\t\t\tlabel = \"kernel\";\n+\t\t\treg = <0x00440000 0x009c0000>;\n+\t\t};\n+\n \t\tpartition@e00000 {\n \t\t\tlabel = \"ubi\";\n \t\t\treg = <0x00e00000 0x07200000>;\n"
  },
  {
    "path": "target/linux/oxnas/patches-5.10/050-ox820-remove-left-overs.patch",
    "content": "From 552ed4955c1fee1109bf5ba137dc35a411a1448c Mon Sep 17 00:00:00 2001\nFrom: Daniel Golle <daniel@makrotopia.org>\nDate: Fri, 1 Jun 2018 02:41:15 +0200\nSubject: [PATCH] arm: ox820: remove left-overs\n\nSigned-off-by: Daniel Golle <daniel@makrotopia.org>\n---\n drivers/clk/clk-oxnas.c                  |  2 --\n include/dt-bindings/clock/oxsemi,ox820.h | 32 +++++++++++-------------\n 2 files changed, 14 insertions(+), 20 deletions(-)\n\n--- a/drivers/clk/clk-oxnas.c\n+++ b/drivers/clk/clk-oxnas.c\n@@ -29,8 +29,6 @@ struct oxnas_stdclk_data {\n \tstruct clk_hw_onecell_data *onecell_data;\n \tstruct clk_oxnas_gate **gates;\n \tunsigned int ngates;\n-\tstruct clk_oxnas_pll **plls;\n-\tunsigned int nplls;\n };\n \n /* Regmap offsets */\n--- a/include/dt-bindings/clock/oxsemi,ox820.h\n+++ b/include/dt-bindings/clock/oxsemi,ox820.h\n@@ -6,24 +6,20 @@\n #ifndef DT_CLOCK_OXSEMI_OX820_H\n #define DT_CLOCK_OXSEMI_OX820_H\n \n-/* PLLs */\n-#define CLK_820_PLLA\t\t0\n-#define CLK_820_PLLB\t\t1\n-\n /* Gate Clocks */\n-#define CLK_820_LEON\t\t2\n-#define CLK_820_DMA_SGDMA\t3\n-#define CLK_820_CIPHER\t\t4\n-#define CLK_820_SD\t\t5\n-#define CLK_820_SATA\t\t6\n-#define CLK_820_AUDIO\t\t7\n-#define CLK_820_USBMPH\t\t8\n-#define CLK_820_ETHA\t\t9\n-#define CLK_820_PCIEA\t\t10\n-#define CLK_820_NAND\t\t11\n-#define CLK_820_PCIEB\t\t12\n-#define CLK_820_ETHB\t\t13\n-#define CLK_820_REF600\t\t14\n-#define CLK_820_USBDEV\t\t15\n+#define CLK_820_LEON\t\t0\n+#define CLK_820_DMA_SGDMA\t1\n+#define CLK_820_CIPHER\t\t2\n+#define CLK_820_SD\t\t3\n+#define CLK_820_SATA\t\t4\n+#define CLK_820_AUDIO\t\t5\n+#define CLK_820_USBMPH\t\t6\n+#define CLK_820_ETHA\t\t7\n+#define CLK_820_PCIEA\t\t8\n+#define CLK_820_NAND\t\t9\n+#define CLK_820_PCIEB\t\t10\n+#define CLK_820_ETHB\t\t11\n+#define CLK_820_REF600\t\t12\n+#define CLK_820_USBDEV\t\t13\n \n #endif /* DT_CLOCK_OXSEMI_OX820_H */\n"
  },
  {
    "path": "target/linux/oxnas/patches-5.10/100-oxnas-clk-plla-pllb.patch",
    "content": "--- a/drivers/clk/clk-oxnas.c\n+++ b/drivers/clk/clk-oxnas.c\n@@ -5,19 +5,42 @@\n  * Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com>\n  */\n \n+#include <linux/clk.h>\n+#include <linux/clkdev.h>\n #include <linux/clk-provider.h>\n #include <linux/kernel.h>\n #include <linux/init.h>\n+#include <linux/delay.h>\n #include <linux/of.h>\n #include <linux/of_device.h>\n #include <linux/platform_device.h>\n #include <linux/stringify.h>\n #include <linux/regmap.h>\n #include <linux/mfd/syscon.h>\n+#include <linux/reset.h>\n \n #include <dt-bindings/clock/oxsemi,ox810se.h>\n #include <dt-bindings/clock/oxsemi,ox820.h>\n \n+#define REF300_DIV_INT_SHIFT\t\t8\n+#define REF300_DIV_FRAC_SHIFT\t\t0\n+#define REF300_DIV_INT(val)\t\t((val) << REF300_DIV_INT_SHIFT)\n+#define REF300_DIV_FRAC(val)\t\t((val) << REF300_DIV_FRAC_SHIFT)\n+\n+#define PLLB_BYPASS\t\t\t1\n+#define PLLB_ENSAT\t\t\t3\n+#define PLLB_OUTDIV\t\t\t4\n+#define PLLB_REFDIV\t\t\t8\n+#define PLLB_DIV_INT_SHIFT\t\t8\n+#define PLLB_DIV_FRAC_SHIFT\t\t0\n+#define PLLB_DIV_INT(val)\t\t((val) << PLLB_DIV_INT_SHIFT)\n+#define PLLB_DIV_FRAC(val)\t\t((val) << PLLB_DIV_FRAC_SHIFT)\n+\n+#define PLLA_REFDIV_MASK\t\t0x3F\n+#define PLLA_REFDIV_SHIFT\t\t8\n+#define PLLA_OUTDIV_MASK\t\t0x7\n+#define PLLA_OUTDIV_SHIFT\t\t4\n+\n /* Standard regmap gate clocks */\n struct clk_oxnas_gate {\n \tstruct clk_hw hw;\n@@ -36,6 +59,135 @@ struct oxnas_stdclk_data {\n #define CLK_SET_REGOFFSET\t0x2c\n #define CLK_CLR_REGOFFSET\t0x30\n \n+#define PLLA_CTRL0_REGOFFSET\t0x1f0\n+#define PLLA_CTRL1_REGOFFSET\t0x1f4\n+#define PLLB_CTRL0_REGOFFSET\t0x1001f0\n+#define MHZ (1000 * 1000)\n+\n+struct clk_oxnas_pll {\n+\tstruct clk_hw hw;\n+\tstruct device_node *devnode;\n+\tstruct reset_control *rstc;\n+\tstruct regmap *syscon;\n+};\n+\n+#define to_clk_oxnas_pll(_hw) container_of(_hw, struct clk_oxnas_pll, hw)\n+\n+static unsigned long plla_clk_recalc_rate(struct clk_hw *hw,\n+\tunsigned long parent_rate)\n+{\n+\tstruct clk_oxnas_pll *plla = to_clk_oxnas_pll(hw);\n+\tunsigned long fin = parent_rate;\n+\tunsigned long refdiv, outdiv;\n+\tunsigned int pll0, fbdiv;\n+\n+\tBUG_ON(regmap_read(plla->syscon, PLLA_CTRL0_REGOFFSET, &pll0));\n+\n+\trefdiv = (pll0 >> PLLA_REFDIV_SHIFT) & PLLA_REFDIV_MASK;\n+\trefdiv += 1;\n+\toutdiv = (pll0 >> PLLA_OUTDIV_SHIFT) & PLLA_OUTDIV_MASK;\n+\toutdiv += 1;\n+\n+\tBUG_ON(regmap_read(plla->syscon, PLLA_CTRL1_REGOFFSET, &fbdiv));\n+\t/* seems we will not be here when pll is bypassed, so ignore this\n+\t * case */\n+\n+\treturn fin / MHZ * fbdiv / (refdiv * outdiv) / 32768 * MHZ;\n+}\n+\n+static const char *pll_clk_parents[] = {\n+\t\"oscillator\",\n+};\n+\n+static struct clk_ops plla_ops = {\n+\t.recalc_rate = plla_clk_recalc_rate,\n+};\n+\n+static struct clk_init_data clk_plla_init = {\n+\t.name = \"plla\",\n+\t.ops = &plla_ops,\n+\t.parent_names = pll_clk_parents,\n+\t.num_parents = ARRAY_SIZE(pll_clk_parents),\n+};\n+\n+static int pllb_clk_is_prepared(struct clk_hw *hw)\n+{\n+\tstruct clk_oxnas_pll *pllb = to_clk_oxnas_pll(hw);\n+\n+\treturn !!pllb->rstc;\n+}\n+\n+static int pllb_clk_prepare(struct clk_hw *hw)\n+{\n+\tstruct clk_oxnas_pll *pllb = to_clk_oxnas_pll(hw);\n+\n+\tpllb->rstc = of_reset_control_get(pllb->devnode, NULL);\n+\n+\treturn IS_ERR(pllb->rstc) ? PTR_ERR(pllb->rstc) : 0;\n+}\n+\n+static void pllb_clk_unprepare(struct clk_hw *hw)\n+{\n+\tstruct clk_oxnas_pll *pllb = to_clk_oxnas_pll(hw);\n+\n+\tBUG_ON(IS_ERR(pllb->rstc));\n+\n+\treset_control_put(pllb->rstc);\n+\tpllb->rstc = NULL;\n+}\n+\n+static int pllb_clk_enable(struct clk_hw *hw)\n+{\n+\tstruct clk_oxnas_pll *pllb = to_clk_oxnas_pll(hw);\n+\n+\tBUG_ON(IS_ERR(pllb->rstc));\n+\n+\t/* put PLL into bypass */\n+\tregmap_update_bits(pllb->syscon, PLLB_CTRL0_REGOFFSET, BIT(PLLB_BYPASS), BIT(PLLB_BYPASS));\n+\twmb();\n+\tudelay(10);\n+\treset_control_assert(pllb->rstc);\n+\tudelay(10);\n+\t/* set PLL B control information */\n+\tregmap_write_bits(pllb->syscon, PLLB_CTRL0_REGOFFSET, 0xffff,\n+\t\t\t  (1 << PLLB_ENSAT) | (1 << PLLB_OUTDIV) | (2 << PLLB_REFDIV));\n+\treset_control_deassert(pllb->rstc);\n+\tudelay(100);\n+\tregmap_update_bits(pllb->syscon, PLLB_CTRL0_REGOFFSET, BIT(PLLB_BYPASS), 0);\n+\n+\treturn 0;\n+}\n+\n+static void pllb_clk_disable(struct clk_hw *hw)\n+{\n+\tstruct clk_oxnas_pll *pllb = to_clk_oxnas_pll(hw);\n+\n+\tBUG_ON(IS_ERR(pllb->rstc));\n+\n+\t/* put PLL into bypass */\n+\tregmap_update_bits(pllb->syscon, PLLB_CTRL0_REGOFFSET, BIT(PLLB_BYPASS), BIT(PLLB_BYPASS));\n+\n+\twmb();\n+\tudelay(10);\n+\n+\treset_control_assert(pllb->rstc);\n+}\n+\n+static struct clk_ops pllb_ops = {\n+\t.prepare = pllb_clk_prepare,\n+\t.unprepare = pllb_clk_unprepare,\n+\t.is_prepared = pllb_clk_is_prepared,\n+\t.enable = pllb_clk_enable,\n+\t.disable = pllb_clk_disable,\n+};\n+\n+static struct clk_init_data clk_pllb_init = {\n+\t.name = \"pllb\",\n+\t.ops = &pllb_ops,\n+\t.parent_names = pll_clk_parents,\n+\t.num_parents = ARRAY_SIZE(pll_clk_parents),\n+};\n+\n static inline struct clk_oxnas_gate *to_clk_oxnas_gate(struct clk_hw *hw)\n {\n \treturn container_of(hw, struct clk_oxnas_gate, hw);\n@@ -249,3 +401,42 @@ static struct platform_driver oxnas_stdc\n \t},\n };\n builtin_platform_driver(oxnas_stdclk_driver);\n+\n+void __init oxnas_init_plla(struct device_node *np)\n+{\n+\tstruct clk *clk;\n+\tstruct clk_oxnas_pll *plla;\n+\n+\tplla = kmalloc(sizeof(*plla), GFP_KERNEL);\n+\tBUG_ON(!plla);\n+\n+\tplla->syscon = syscon_node_to_regmap(of_get_parent(np));\n+\tplla->hw.init = &clk_plla_init;\n+\tplla->devnode = np;\n+\tplla->rstc = NULL;\n+\tclk = clk_register(NULL, &plla->hw);\n+\tBUG_ON(IS_ERR(clk));\n+\t/* mark it as enabled */\n+\tclk_prepare_enable(clk);\n+\tof_clk_add_provider(np, of_clk_src_simple_get, clk);\n+}\n+CLK_OF_DECLARE(oxnas_plla, \"plxtech,nas782x-plla\", oxnas_init_plla);\n+\n+void __init oxnas_init_pllb(struct device_node *np)\n+{\n+\tstruct clk *clk;\n+\tstruct clk_oxnas_pll *pllb;\n+\n+\tpllb = kmalloc(sizeof(*pllb), GFP_KERNEL);\n+\tBUG_ON(!pllb);\n+\n+\tpllb->syscon = syscon_node_to_regmap(of_get_parent(np));\n+\tpllb->hw.init = &clk_pllb_init;\n+\tpllb->devnode = np;\n+\tpllb->rstc = NULL;\n+\n+\tclk = clk_register(NULL, &pllb->hw);\n+\tBUG_ON(IS_ERR(clk));\n+\tof_clk_add_provider(np, of_clk_src_simple_get, clk);\n+}\n+CLK_OF_DECLARE(oxnas_pllb, \"plxtech,nas782x-pllb\", oxnas_init_pllb);\n--- a/arch/arm/boot/dts/ox820.dtsi\n+++ b/arch/arm/boot/dts/ox820.dtsi\n@@ -61,12 +61,6 @@\n \t\t\tclocks = <&osc>;\n \t\t};\n \n-\t\tplla: plla {\n-\t\t\tcompatible = \"fixed-clock\";\n-\t\t\t#clock-cells = <0>;\n-\t\t\tclock-frequency = <850000000>;\n-\t\t};\n-\n \t\tarmclk: armclk {\n \t\t\tcompatible = \"fixed-factor-clock\";\n \t\t\t#clock-cells = <0>;\n@@ -266,6 +260,19 @@\n \t\t\t\t\tcompatible = \"oxsemi,ox820-stdclk\", \"oxsemi,ox810se-stdclk\";\n \t\t\t\t\t#clock-cells = <1>;\n \t\t\t\t};\n+\n+\t\t\t\tplla: plla {\n+\t\t\t\t\tcompatible = \"plxtech,nas782x-plla\";\n+\t\t\t\t\t#clock-cells = <0>;\n+\t\t\t\t\tclocks = <&osc>;\n+\t\t\t\t};\n+\n+\t\t\t\tpllb: pllb {\n+\t\t\t\t\tcompatible = \"plxtech,nas782x-pllb\";\n+\t\t\t\t\t#clock-cells = <0>;\n+\t\t\t\t\tclocks = <&osc>;\n+\t\t\t\t\tresets = <&reset RESET_PLLB>;\n+\t\t\t\t};\n \t\t\t};\n \t\t};\n \n@@ -287,6 +294,13 @@\n \t\t\t\tclocks = <&armclk>;\n \t\t\t};\n \n+\t\t\twatchdog@620 {\n+\t\t\t\tcompatible = \"mpcore_wdt\";\n+\t\t\t\treg = <0x620 0x20>;\n+\t\t\t\tinterrupts = <GIC_PPI 14 (GIC_CPU_MASK_RAW(3)|IRQ_TYPE_LEVEL_HIGH)>;\n+\t\t\t\tclocks = <&armclk>;\n+\t\t\t};\n+\n \t\t\tgic: gic@1000 {\n \t\t\t\tcompatible = \"arm,arm11mp-gic\";\n \t\t\t\tinterrupt-controller;\n"
  },
  {
    "path": "target/linux/oxnas/patches-5.10/150-oxnas-restart.patch",
    "content": "--- a/drivers/power/reset/Kconfig\n+++ b/drivers/power/reset/Kconfig\n@@ -141,6 +141,12 @@ config POWER_RESET_OXNAS\n \thelp\n \t  Restart support for OXNAS/PLXTECH OX820 SoC.\n \n+config POWER_RESET_OXNAS\n+\tbool \"OXNAS SoC restart driver\"\n+\tdepends on ARCH_OXNAS\n+\thelp\n+\t  Restart support for OXNAS boards.\n+\n config POWER_RESET_PIIX4_POWEROFF\n \ttristate \"Intel PIIX4 power-off driver\"\n \tdepends on PCI\n--- a/drivers/power/reset/Makefile\n+++ b/drivers/power/reset/Makefile\n@@ -18,6 +18,7 @@ obj-$(CONFIG_POWER_RESET_QCOM_PON) += qc\n obj-$(CONFIG_POWER_RESET_OCELOT_RESET) += ocelot-reset.o\n obj-$(CONFIG_POWER_RESET_PIIX4_POWEROFF) += piix4-poweroff.o\n obj-$(CONFIG_POWER_RESET_LTC2952) += ltc2952-poweroff.o\n+obj-$(CONFIG_POWER_RESET_OXNAS) += oxnas-restart.o\n obj-$(CONFIG_POWER_RESET_QNAP) += qnap-poweroff.o\n obj-$(CONFIG_POWER_RESET_RESTART) += restart-poweroff.o\n obj-$(CONFIG_POWER_RESET_ST) += st-poweroff.o\n"
  },
  {
    "path": "target/linux/oxnas/patches-5.10/320-oxnas-phy-pcie.patch",
    "content": "--- a/arch/arm/boot/dts/ox820.dtsi\n+++ b/arch/arm/boot/dts/ox820.dtsi\n@@ -247,6 +247,15 @@\n \t\t\t\t};\n \t\t\t};\n \n+\t\t\tpcie_phy: pcie-phy@a00000 {\n+\t\t\t\tcompatible = \"oxsemi,ox820-pcie-phy\";\n+\t\t\t\treg = <0xa00000 0x10>;\n+\t\t\t\t#phy-cells = <0>;\n+\t\t\t\tresets = <&reset RESET_PCIEPHY>;\n+\t\t\t\treset-names = \"phy\";\n+\t\t\t\tstatus = \"disabled\";\n+\t\t\t};\n+\n \t\t\tsys: sys-ctrl@e00000 {\n \t\t\t\tcompatible = \"oxsemi,ox820-sys-ctrl\", \"syscon\", \"simple-mfd\";\n \t\t\t\treg = <0xe00000 0x200000>;\n--- a/drivers/phy/Kconfig\n+++ b/drivers/phy/Kconfig\n@@ -35,6 +35,13 @@ config PHY_LPC18XX_USB_OTG\n \t  This driver is need for USB0 support on LPC18xx/43xx and takes\n \t  care of enabling and clock setup.\n \n+config PHY_OXNAS\n+\ttristate \"Oxford Semi. OX820 PCI-E PHY support\"\n+\tdepends on HAS_IOMEM && OF && (ARM || COMPILE_TEST)\n+\tselect GENERIC_PHY\n+\thelp\n+\t  This option enables support for OXNAS OX820 SoC PCIE PHY.\n+\n config PHY_PISTACHIO_USB\n \ttristate \"IMG Pistachio USB2.0 PHY driver\"\n \tdepends on MACH_PISTACHIO\n--- a/drivers/phy/Makefile\n+++ b/drivers/phy/Makefile\n@@ -6,6 +6,7 @@\n obj-$(CONFIG_GENERIC_PHY)\t\t+= phy-core.o\n obj-$(CONFIG_GENERIC_PHY_MIPI_DPHY)\t+= phy-core-mipi-dphy.o\n obj-$(CONFIG_PHY_LPC18XX_USB_OTG)\t+= phy-lpc18xx-usb-otg.o\n+obj-$(CONFIG_PHY_OXNAS)\t\t\t+= phy-oxnas-pcie.o\n obj-$(CONFIG_PHY_XGENE)\t\t\t+= phy-xgene.o\n obj-$(CONFIG_PHY_PISTACHIO_USB)\t\t+= phy-pistachio-usb.o\n obj-$(CONFIG_USB_LGM_PHY)\t\t+= phy-lgm-usb.o\n"
  },
  {
    "path": "target/linux/oxnas/patches-5.10/340-oxnas-pcie.patch",
    "content": "--- a/drivers/pci/controller/Kconfig\n+++ b/drivers/pci/controller/Kconfig\n@@ -305,6 +305,11 @@ config PCIE_HISI_ERR\n \t  Say Y here if you want error handling support\n \t  for the PCIe controller's errors on HiSilicon HIP SoCs\n \n+config PCIE_OXNAS\n+\tbool \"PLX Oxnas PCIe controller\"\n+\tdepends on ARCH_OXNAS\n+\tselect PCIEPORTBUS\n+\n source \"drivers/pci/controller/dwc/Kconfig\"\n source \"drivers/pci/controller/mobiveil/Kconfig\"\n source \"drivers/pci/controller/cadence/Kconfig\"\n--- a/drivers/pci/controller/Makefile\n+++ b/drivers/pci/controller/Makefile\n@@ -27,6 +27,7 @@ obj-$(CONFIG_PCIE_ROCKCHIP) += pcie-rock\n obj-$(CONFIG_PCIE_ROCKCHIP_EP) += pcie-rockchip-ep.o\n obj-$(CONFIG_PCIE_ROCKCHIP_HOST) += pcie-rockchip-host.o\n obj-$(CONFIG_PCIE_MEDIATEK) += pcie-mediatek.o\n+obj-$(CONFIG_PCIE_OXNAS) += pcie-oxnas.o\n obj-$(CONFIG_PCIE_TANGO_SMP8759) += pcie-tango.o\n obj-$(CONFIG_VMD) += vmd.o\n obj-$(CONFIG_PCIE_BRCMSTB) += pcie-brcmstb.o\n--- a/arch/arm/boot/dts/ox820.dtsi\n+++ b/arch/arm/boot/dts/ox820.dtsi\n@@ -289,7 +289,7 @@\n \t\t\t#address-cells = <1>;\n \t\t\t#size-cells = <1>;\n \t\t\tcompatible = \"simple-bus\";\n-\t\t\tranges = <0 0x47000000 0x1000000>;\n+\t\t\tranges = <0 0x47000000 0x2000>;\n \n \t\t\tscu: scu@0 {\n \t\t\t\tcompatible = \"arm,arm11mp-scu\";\n@@ -318,5 +318,86 @@\n \t\t\t\t      <0x100 0x500>;\n \t\t\t};\n \t\t};\n+\n+\t\tpcie0: pcie-controller@47c00000 {\n+\t\t\tcompatible = \"plxtech,nas782x-pcie\";\n+\t\t\tdevice_type = \"pci\";\n+\t\t\t#address-cells = <3>;\n+\t\t\t#size-cells = <2>;\n+\n+\t\t\t/*\t\tflag & space\tbus address\thost address\tsize */\n+\t\t\tranges = <\t0x82000000\t0 0x48000000\t0x48000000\t0 0x2000000\n+\t\t\t\t\t0xC2000000\t0 0x4A000000\t0x4A000000\t0 0x1E00000\n+\t\t\t\t\t0x81000000\t0 0x4BE00000\t0x4BE00000\t0 0x0100000\n+\t\t\t\t\t0x80000000\t0 0x4BF00000\t0x4BF00000\t0 0x0100000>;\n+\n+\t\t\tbus-range = <0x00 0x7f>;\n+\n+\t\t\t/*\tcfg\t\t\tinbound translator\t*/\n+\t\t\treg =\t<0x47c00000 0x1000>,\t<0x47d00000 0x100>;\n+\n+\t\t\tphys = <&pcie_phy>;\n+\t\t\tphy-names = \"pcie-phy\";\n+\n+\t\t\t#interrupt-cells = <1>;\n+\t\t\t/* wild card mask, match all bus address & interrupt specifier */\n+\t\t\t/* format: bus address mask, interrupt specifier mask */\n+\t\t\t/* each bit 1 means need match, 0 means ignored when match */\n+\t\t\tinterrupt-map-mask = <0 0 0 0>;\n+\t\t\t/* format: a list of: bus address, interrupt specifier,\n+\t\t\t * parent interrupt controller & specifier */\n+\t\t\tinterrupt-map = <0 0 0 0 &gic 0 19 0x304>;\n+\t\t\tgpios = <&gpio1 12 0>;\n+\t\t\tclocks = <&stdclk CLK_820_PCIEA>, <&pllb>;\n+\t\t\tclock-names = \"pcie\", \"busclk\";\n+\t\t\tresets = <&reset RESET_PCIEA>;\n+\t\t\treset-names = \"pcie\";\n+\n+\t\t\tplxtech,pcie-hcsl-bit = <2>;\n+\t\t\tplxtech,pcie-ctrl-offset = <0x120>;\n+\t\t\tplxtech,pcie-outbound-offset = <0x138>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tpcie1: pcie-controller@47e00000 {\n+\t\t\tcompatible = \"plxtech,nas782x-pcie\";\n+\t\t\tdevice_type = \"pci\";\n+\t\t\t#address-cells = <3>;\n+\t\t\t#size-cells = <2>;\n+\n+\t\t\t/*\t\tflag & space\tbus address\thost address\tsize */\n+\t\t\tranges = <\t0x82000000\t0 0x4C000000\t0x4C000000\t0 0x2000000\n+\t\t\t\t\t0xC2000000\t0 0x4E000000\t0x4E000000\t0 0x1E00000\n+\t\t\t\t\t0x81000000\t0 0x4FE00000\t0x4FE00000\t0 0x0100000\n+\t\t\t\t\t0x80000000\t0 0x4FF00000\t0x4FF00000\t0 0x0100000>;\n+\n+\t\t\tbus-range = <0x80 0xff>;\n+\n+\t\t\t/*\tcfg\t\t\tinbound translator\t*/\n+\t\t\treg =\t<0x47e00000 0x1000>,\t<0x47f00000 0x100>;\n+\n+\t\t\tphys = <&pcie_phy>;\n+\t\t\tphy-names = \"pcie-phy\";\n+\n+\t\t\t#interrupt-cells = <1>;\n+\t\t\t/* wild card mask, match all bus address & interrupt specifier */\n+\t\t\t/* format: bus address mask, interrupt specifier mask */\n+\t\t\t/* each bit 1 means need match, 0 means ignored when match */\n+\t\t\tinterrupt-map-mask = <0 0 0 0>;\n+\t\t\t/* format: a list of: bus address, interrupt specifier,\n+\t\t\t * parent interrupt controller & specifier */\n+\t\t\tinterrupt-map = <0 0 0 0 &gic 0 20 0x304>;\n+\n+\t\t\t/* gpios = <&gpio1 12 0>; */\n+\t\t\tclocks = <&stdclk CLK_820_PCIEB>, <&pllb>;\n+\t\t\tclock-names = \"pcie\", \"busclk\";\n+\t\t\tresets = <&reset RESET_PCIEB>;\n+\t\t\treset-names = \"pcie\";\n+\n+\t\t\tplxtech,pcie-hcsl-bit = <3>;\n+\t\t\tplxtech,pcie-ctrl-offset = <0x124>;\n+\t\t\tplxtech,pcie-outbound-offset = <0x174>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n \t};\n };\n"
  },
  {
    "path": "target/linux/oxnas/patches-5.10/500-oxnas-sata.patch",
    "content": "--- a/drivers/ata/Kconfig\n+++ b/drivers/ata/Kconfig\n@@ -568,6 +568,14 @@ config SATA_VITESSE\n \n \t  If unsure, say N.\n \n+config SATA_OXNAS\n+\ttristate \"PLXTECH NAS782X SATA support\"\n+\tselect SATA_HOST\n+\thelp\n+\t  This option enables support for Nas782x Serial ATA controller.\n+\n+\t  If unsure, say N.\n+\n comment \"PATA SFF controllers with BMDMA\"\n \n config PATA_ALI\n--- a/drivers/ata/Makefile\n+++ b/drivers/ata/Makefile\n@@ -46,6 +46,7 @@ obj-$(CONFIG_SATA_SVW)\t\t+= sata_svw.o\n obj-$(CONFIG_SATA_ULI)\t\t+= sata_uli.o\n obj-$(CONFIG_SATA_VIA)\t\t+= sata_via.o\n obj-$(CONFIG_SATA_VITESSE)\t+= sata_vsc.o\n+obj-$(CONFIG_SATA_OXNAS)\t+= sata_oxnas.o\n \n # SFF PATA w/ BMDMA\n obj-$(CONFIG_PATA_ALI)\t\t+= pata_ali.o\n--- a/arch/arm/boot/dts/ox820.dtsi\n+++ b/arch/arm/boot/dts/ox820.dtsi\n@@ -399,5 +399,20 @@\n \t\t\tplxtech,pcie-outbound-offset = <0x174>;\n \t\t\tstatus = \"disabled\";\n \t\t};\n+\n+\t\tsata: sata@45900000 {\n+\t\t\tcompatible = \"plxtech,nas782x-sata\";\n+\t\t\t\t/*\tports\t\tdmactl\t\tsgdma\t*/\n+\t\t\treg = <0x45900000 0x20000>, <0x459A0000 0x40>, <0x459B0000 0x20>,\n+\t\t\t\t/*\tcore\t\tphy\t\tdescriptors (optional)\t*/\n+\t\t\t\t<0x459E0000 0x2000>, <0x44900000 0x0C>, <0x50000000 0x1000>;\n+\t\t\tinterrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tclocks = <&stdclk CLK_820_SATA>;\n+\t\t\tresets = <&reset RESET_SATA>, <&reset RESET_SATA_LINK>, <&reset RESET_SATA_PHY>;\n+\t\t\treset-names = \"sata\", \"link\", \"phy\";\n+\t\t\tnr-ports = <1>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n \t};\n };\n--- a/arch/arm/boot/dts/ox820-cloudengines-pogoplug-series-3.dts\n+++ b/arch/arm/boot/dts/ox820-cloudengines-pogoplug-series-3.dts\n@@ -111,3 +111,7 @@\n \tpinctrl-names = \"default\";\n \tpinctrl-0 = <&pinctrl_etha_mdio>;\n };\n+\n+&sata {\n+\tstatus = \"okay\";\n+};\n"
  },
  {
    "path": "target/linux/oxnas/patches-5.10/510-ox820-libata-leds.patch",
    "content": "--- a/arch/arm/mach-oxnas/Kconfig\n+++ b/arch/arm/mach-oxnas/Kconfig\n@@ -2,6 +2,7 @@\n menuconfig ARCH_OXNAS\n \tbool \"Oxford Semiconductor OXNAS Family SoCs\"\n \tselect ARCH_HAS_RESET_CONTROLLER\n+\tselect ARCH_WANT_LIBATA_LEDS\n \tselect COMMON_CLK_OXNAS\n \tselect GPIOLIB\n \tselect MFD_SYSCON\n"
  },
  {
    "path": "target/linux/oxnas/patches-5.10/800-oxnas-ehci.patch",
    "content": "--- a/drivers/usb/host/Kconfig\n+++ b/drivers/usb/host/Kconfig\n@@ -350,6 +350,13 @@ config USB_OCTEON_EHCI\n \t  USB 2.0 device support.  All CN6XXX based chips with USB are\n \t  supported.\n \n+config USB_EHCI_OXNAS\n+\ttristate \"OXNAS EHCI Module\"\n+\tdepends on USB_EHCI_HCD && ARCH_OXNAS\n+\tselect USB_EHCI_ROOT_HUB_TT\n+\thelp\n+\t  Enable support for the OX820 SOC's on-chip EHCI controller.\n+\n endif # USB_EHCI_HCD\n \n config USB_OXU210HP_HCD\n--- a/drivers/usb/host/Makefile\n+++ b/drivers/usb/host/Makefile\n@@ -48,6 +48,7 @@ obj-$(CONFIG_USB_EHCI_HCD_SPEAR)\t+= ehci\n obj-$(CONFIG_USB_EHCI_HCD_STI)\t+= ehci-st.o\n obj-$(CONFIG_USB_EHCI_EXYNOS)\t+= ehci-exynos.o\n obj-$(CONFIG_USB_EHCI_HCD_AT91) += ehci-atmel.o\n+obj-$(CONFIG_USB_EHCI_OXNAS)\t+= ehci-oxnas.o\n obj-$(CONFIG_USB_EHCI_TEGRA)\t+= ehci-tegra.o\n obj-$(CONFIG_USB_EHCI_BRCMSTB)\t+= ehci-brcm.o\n \n--- a/arch/arm/boot/dts/ox820.dtsi\n+++ b/arch/arm/boot/dts/ox820.dtsi\n@@ -106,6 +106,31 @@\n \t\t\tstatus = \"disabled\";\n \t\t};\n \n+\t\tehci: ehci@40200100 {\n+\t\t\tcompatible = \"plxtech,nas782x-ehci\";\n+\t\t\treg = <0x40200100 0xf00>;\n+\t\t\tinterrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tclocks = <&stdclk CLK_820_USBMPH>, <&pllb>, <&stdclk CLK_820_REF600>;\n+\t\t\tclock-names = \"usb\", \"refsrc\", \"phyref\";\n+\t\t\tresets = <&reset RESET_USBHS>, <&reset RESET_USBPHYA>, <&reset RESET_USBPHYB>;\n+\t\t\treset-names = \"host\", \"phya\", \"phyb\";\n+\t\t\toxsemi,sys-ctrl = <&sys>;\n+\t\t\t/* Otherwise ref300 is used, which is derived from sata phy\n+\t\t\t * in that case, usb depends on sata initialization */\n+\t\t\t/* FIXME: how to make this dependency explicit ? */\n+\t\t\toxsemi,ehci_use_pllb;\n+\t\t\tstatus = \"disabled\";\n+\n+\t\t\tehci_port1: port@1 {\n+\t\t\t\treg = <1>;\n+\t\t\t\t#trigger-source-cells = <0>;\n+\t\t\t};\n+\t\t\tehci_port2: port@2 {\n+\t\t\t\treg = <2>;\n+\t\t\t\t#trigger-source-cells = <0>;\n+\t\t\t};\n+\t\t};\n+\n \t\tapb-bridge@44000000 {\n \t\t\t#address-cells = <1>;\n \t\t\t#size-cells = <1>;\n--- a/arch/arm/boot/dts/ox820-cloudengines-pogoplug-series-3.dts\n+++ b/arch/arm/boot/dts/ox820-cloudengines-pogoplug-series-3.dts\n@@ -105,6 +105,10 @@\n \t};\n };\n \n+&ehci {\n+\tstatus = \"okay\";\n+};\n+\n &etha {\n \tstatus = \"okay\";\n \n"
  },
  {
    "path": "target/linux/oxnas/patches-5.10/996-generic-Mangle-bootloader-s-kernel-arguments.patch",
    "content": "From 71270226b14733a4b1f2cde58ea9265caa50b38d Mon Sep 17 00:00:00 2001\nFrom: Adrian Panella <ianchi74@outlook.com>\nDate: Thu, 9 Mar 2017 09:37:17 +0100\nSubject: [PATCH 67/69] generic: Mangle bootloader's kernel arguments\n\nThe command-line arguments provided by the boot loader will be\nappended to a new device tree property: bootloader-args.\nIf there is a property \"append-rootblock\" in DT under /chosen\nand a root= option in bootloaders command line it will be parsed\nand added to DT bootargs with the form: <append-rootblock>XX.\nOnly command line ATAG will be processed, the rest of the ATAGs\nsent by bootloader will be ignored.\nThis is usefull in dual boot systems, to get the current root partition\nwithout afecting the rest of the system.\n\nSigned-off-by: Adrian Panella <ianchi74@outlook.com>\n---\n arch/arm/Kconfig                        | 11 +++++\n arch/arm/boot/compressed/atags_to_fdt.c | 72 ++++++++++++++++++++++++++++++++-\n init/main.c                             | 16 ++++++++\n 3 files changed, 98 insertions(+), 1 deletion(-)\n\n--- a/arch/arm/Kconfig\n+++ b/arch/arm/Kconfig\n@@ -1781,6 +1781,17 @@ config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEN\n \t  The command-line arguments provided by the boot loader will be\n \t  appended to the the device tree bootargs property.\n \n+config ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE\n+\tbool \"Append rootblock parsing bootloader's kernel arguments\"\n+\thelp\n+\t  The command-line arguments provided by the boot loader will be\n+\t  appended to a new device tree property: bootloader-args.\n+\t  If there is a property \"append-rootblock\" in DT under /chosen \n+\t  and a root= option in bootloaders command line it will be parsed \n+\t  and added to DT bootargs with the form: <append-rootblock>XX.\n+\t  Only command line ATAG will be processed, the rest of the ATAGs\n+\t  sent by bootloader will be ignored.\n+\n endchoice\n \n config CMDLINE\n--- a/arch/arm/boot/compressed/atags_to_fdt.c\n+++ b/arch/arm/boot/compressed/atags_to_fdt.c\n@@ -5,6 +5,8 @@\n \n #if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND)\n #define do_extend_cmdline 1\n+#elif defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)\n+#define do_extend_cmdline 1\n #else\n #define do_extend_cmdline 0\n #endif\n@@ -69,6 +71,59 @@ static uint32_t get_cell_size(const void\n \treturn cell_size;\n }\n \n+#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)\n+\n+static char *append_rootblock(char *dest, const char *str, int len, void *fdt)\n+{\n+\tchar *ptr, *end;\n+\tchar *root=\"root=\";\n+\tint i, l;\n+\tconst char *rootblock;\n+\n+\t//ARM doesn't have __HAVE_ARCH_STRSTR, so search manually\n+\tptr = str - 1;\n+\n+\tdo {\n+\t\t//first find an 'r' at the begining or after a space\n+\t\tdo {\n+\t\t\tptr++;\n+\t\t\tptr = strchr(ptr, 'r');\n+\t\t\tif(!ptr) return dest;\n+\n+\t\t} while (ptr != str && *(ptr-1) != ' ');\n+\n+\t\t//then check for the rest\n+\t\tfor(i = 1; i <= 4; i++)\n+\t\t\tif(*(ptr+i) != *(root+i)) break;\n+\n+\t} while (i != 5);\n+\n+\tend = strchr(ptr, ' ');\n+\tend = end ? (end - 1) : (strchr(ptr, 0) - 1);\n+\n+\t//find partition number (assumes format root=/dev/mtdXX | /dev/mtdblockXX | yy:XX )\n+\tfor( i = 0; end >= ptr && *end >= '0' && *end <= '9'; end--, i++);\n+\tptr = end + 1;\n+\n+\t/* if append-rootblock property is set use it to append to command line */\n+\trootblock = getprop(fdt, \"/chosen\", \"append-rootblock\", &l);\n+\tif(rootblock != NULL) {\n+\t\tif(*dest != ' ') {\n+\t\t\t*dest = ' ';\n+\t\t\tdest++;\n+\t\t\tlen++;\n+\t\t}\n+\t\tif (len + l + i <= COMMAND_LINE_SIZE) {\n+\t\t\tmemcpy(dest, rootblock, l);\n+\t\t\tdest += l - 1;\n+\t\t\tmemcpy(dest, ptr, i);\n+\t\t\tdest += i;\n+\t\t}\n+\t}\n+\treturn dest;\n+}\n+#endif\n+\n static void merge_fdt_bootargs(void *fdt, const char *fdt_cmdline)\n {\n \tchar cmdline[COMMAND_LINE_SIZE];\n@@ -88,12 +143,21 @@ static void merge_fdt_bootargs(void *fdt\n \n \t/* and append the ATAG_CMDLINE */\n \tif (fdt_cmdline) {\n+\n+#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)\n+\t\t//save original bootloader args\n+\t\t//and append ubi.mtd with root partition number to current cmdline\n+\t\tsetprop_string(fdt, \"/chosen\", \"bootloader-args\", fdt_cmdline);\n+\t\tptr = append_rootblock(ptr, fdt_cmdline, len, fdt);\n+\n+#else\n \t\tlen = strlen(fdt_cmdline);\n \t\tif (ptr - cmdline + len + 2 < COMMAND_LINE_SIZE) {\n \t\t\t*ptr++ = ' ';\n \t\t\tmemcpy(ptr, fdt_cmdline, len);\n \t\t\tptr += len;\n \t\t}\n+#endif\n \t}\n \t*ptr = '\\0';\n \n@@ -168,7 +232,9 @@ int atags_to_fdt(void *atag_list, void *\n \t\t\telse\n \t\t\t\tsetprop_string(fdt, \"/chosen\", \"bootargs\",\n \t\t\t\t\t       atag->u.cmdline.cmdline);\n-\t\t} else if (atag->hdr.tag == ATAG_MEM) {\n+\t\t}\n+#ifndef CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE\n+\t\telse if (atag->hdr.tag == ATAG_MEM) {\n \t\t\tif (memcount >= sizeof(mem_reg_property)/4)\n \t\t\t\tcontinue;\n \t\t\tif (!atag->u.mem.size)\n@@ -212,6 +278,10 @@ int atags_to_fdt(void *atag_list, void *\n \t\tsetprop(fdt, \"/memory\", \"reg\", mem_reg_property,\n \t\t\t4 * memcount * memsize);\n \t}\n+#else\n+\n+\t}\n+#endif\n \n \treturn fdt_pack(fdt);\n }\n--- a/init/main.c\n+++ b/init/main.c\n@@ -110,6 +110,10 @@\n \n #include <kunit/test.h>\n \n+#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)\n+#include <linux/of.h>\n+#endif\n+\n static int kernel_init(void *);\n \n extern void init_IRQ(void);\n@@ -904,6 +908,18 @@ asmlinkage __visible void __init __no_sa\n \tpage_alloc_init();\n \n \tpr_notice(\"Kernel command line: %s\\n\", saved_command_line);\n+\n+#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)\n+\t//Show bootloader's original command line for reference\n+\tif(of_chosen) {\n+\t\tconst char *prop = of_get_property(of_chosen, \"bootloader-args\", NULL);\n+\t\tif(prop)\n+\t\t\tpr_notice(\"Bootloader command line (ignored): %s\\n\", prop);\n+\t\telse\n+\t\t\tpr_notice(\"Bootloader command line not present\\n\");\n+\t}\n+#endif\n+\n \t/* parameters may set static keys */\n \tjump_label_init();\n \tparse_early_param();\n"
  },
  {
    "path": "target/linux/oxnas/patches-5.10/999-libata-hacks.patch",
    "content": "--- a/drivers/ata/libata-core.c\n+++ b/drivers/ata/libata-core.c\n@@ -1528,6 +1528,14 @@ unsigned ata_exec_internal_sg(struct ata\n \t\treturn AC_ERR_SYSTEM;\n \t}\n \n+\tif (ap->ops->acquire_hw && !ap->ops->acquire_hw(ap, 0, 0)) {\n+\t\tspin_unlock_irqrestore(ap->lock, flags);\n+\t\tif (!ap->ops->acquire_hw(ap, 1, (2*HZ))) {\n+\t\t\treturn AC_ERR_TIMEOUT;\n+\t\t}\n+\t\tspin_lock_irqsave(ap->lock, flags);\n+\t}\n+\n \t/* initialize internal qc */\n \tqc = __ata_qc_from_tag(ap, ATA_TAG_INTERNAL);\n \n@@ -4558,6 +4566,9 @@ struct ata_queued_cmd *ata_qc_new_init(s\n \tif (unlikely(ap->pflags & ATA_PFLAG_FROZEN))\n \t\treturn NULL;\n \n+\tif (ap->ops->qc_new && ap->ops->qc_new(ap))\n+\t\treturn NULL;\n+\n \t/* libsas case */\n \tif (ap->flags & ATA_FLAG_SAS_HOST) {\n \t\ttag = ata_sas_allocate_tag(ap);\n@@ -4603,6 +4614,8 @@ void ata_qc_free(struct ata_queued_cmd *\n \t\tqc->tag = ATA_TAG_POISON;\n \t\tif (ap->flags & ATA_FLAG_SAS_HOST)\n \t\t\tata_sas_free_tag(tag, ap);\n+\t\tif (ap->ops->qc_free)\n+\t\t\tap->ops->qc_free(qc);\n \t}\n }\n \n--- a/include/linux/libata.h\n+++ b/include/linux/libata.h\n@@ -912,6 +912,8 @@ struct ata_port_operations {\n \tenum ata_completion_errors (*qc_prep)(struct ata_queued_cmd *qc);\n \tunsigned int (*qc_issue)(struct ata_queued_cmd *qc);\n \tbool (*qc_fill_rtf)(struct ata_queued_cmd *qc);\n+\tint (*qc_new)(struct ata_port *ap);\n+\tvoid (*qc_free)(struct ata_queued_cmd *qc);\n \n \t/*\n \t * Configuration and exception handling\n@@ -1002,6 +1004,9 @@ struct ata_port_operations {\n \tvoid (*phy_reset)(struct ata_port *ap);\n \tvoid (*eng_timeout)(struct ata_port *ap);\n \n+\tint (*acquire_hw)(struct ata_port *ap, int may_sleep,\n+\t\t\t  int timeout_jiffies);\n+\n \t/*\n \t * ->inherits must be the last field and all the preceding\n \t * fields must be pointers.\n"
  },
  {
    "path": "target/linux/pistachio/Makefile",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2017-2021 OpenWrt.org\n\ninclude $(TOPDIR)/rules.mk\n\nARCH:=mipsel\nBOARD:=pistachio\nBOARDNAME:=MIPS pistachio\nFEATURES:=fpu usb usbgadget squashfs targz nand\nCPU_TYPE:=24kc\nCPU_SUBTYPE:=24kf\n\nKERNEL_PATCHVER:=5.10\n\ninclude $(INCLUDE_DIR)/target.mk\n\nKERNELNAME:=vmlinux dtbs\n\nDEFAULT_PACKAGES += \\\n\tkmod-gpio-button-hotplug \\\n\tuboot-envtools\n\n$(eval $(call BuildTarget))\n"
  },
  {
    "path": "target/linux/pistachio/base-files/etc/board.d/02_network",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2017 OpenWrt.org\n\n. /lib/functions/uci-defaults.sh\n\nboard_config_update\n\nucidef_set_interface_lan 'eth0' 'dhcp'\n\nboard_config_flush\n\nexit 0\n"
  },
  {
    "path": "target/linux/pistachio/base-files/lib/upgrade/platform.sh",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2017 OpenWrt.org\n\nRAMFS_COPY_BIN='fw_printenv fw_setenv dmesg'\nRAMFS_COPY_DATA=\"/etc/fw_env.config\"\nREQUIRE_IMAGE_METADATA=0\n\nplatform_check_image()\n{\n\tlocal board=$(board_name)\n\n\tnand_do_platform_check $board $1\n\treturn $?\n}\n\nplatform_do_upgrade() {\n\t# TODO no need to switch to ramfs with dual partitions in\n\t# fact we don't even want to reboot as part of seamless\n\t# upgrades. Instead just upgrade opposite partition and mark\n\t# the next reboot to boot from that partition. Could just call\n\t# stage2 directly but need to refactor nand_upgrade_success\n\t# for this to work.\n\t#   Also the nand functions don't allow url to be used\n\n\tlocal board=$(board_name)\n\n\tcase \"$board\" in\n\timg,pistachio-marduk)\n\t\tlocal boot_partition=$(dmesg | grep \"ubi0: attached.*\" | sed \"s/^.*\\(firmware[0-1]\\).*/\\1/g\")\n\n\t\techo \"Current boot partiton $boot_partition (/dev/mtd$(find_mtd_index $boot_partition))\"\n\t\tmkdir -p /var/lock\n\t\tif [ \"$boot_partition\" == \"firmware0\" ]; then\n\t\t\tCI_UBIPART=\"firmware1\"\n\t\t\tfw_setenv boot_partition 1 || exit 1\n\t\telse\n\t\t\tCI_UBIPART=\"firmware0\"\n\t\t\tfw_setenv boot_partition 0 || exit 1\n\t\tfi\n\t\techo \"Upgrading partition $CI_UBIPART (/dev/mtd$(find_mtd_index $CI_UBIPART))\"\n\t\t;;\n\tesac\n\n\tnand_do_upgrade $1\n}\n"
  },
  {
    "path": "target/linux/pistachio/config-5.10",
    "content": "CONFIG_ARCH_32BIT_OFF_T=y\nCONFIG_ARCH_HIBERNATION_POSSIBLE=y\nCONFIG_ARCH_MMAP_RND_BITS_MAX=15\nCONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15\nCONFIG_ARCH_SUSPEND_POSSIBLE=y\nCONFIG_BLK_DEV_LOOP=y\nCONFIG_BLK_DEV_SD=y\nCONFIG_BLK_SCSI_REQUEST=y\nCONFIG_BOARD_SCACHE=y\nCONFIG_BOOT_ELF32=y\nCONFIG_CEVT_R4K=y\nCONFIG_CLKDEV_LOOKUP=y\nCONFIG_CLKSRC_MIPS_GIC=y\nCONFIG_CLKSRC_PISTACHIO=y\nCONFIG_CLOCKSOURCE_WATCHDOG=y\nCONFIG_CLONE_BACKWARDS=y\nCONFIG_COMMON_CLK=y\n# CONFIG_COMMON_CLK_BOSTON is not set\nCONFIG_COMPAT_32BIT_TIME=y\nCONFIG_CONNECTOR=y\nCONFIG_CPU_GENERIC_DUMP_TLB=y\nCONFIG_CPU_HAS_DIEI=y\nCONFIG_CPU_HAS_PREFETCH=y\nCONFIG_CPU_HAS_RIXI=y\nCONFIG_CPU_HAS_SYNC=y\nCONFIG_CPU_IDLE=y\nCONFIG_CPU_IDLE_GOV_LADDER=y\nCONFIG_CPU_IDLE_GOV_MENU=y\nCONFIG_CPU_MIPS32=y\nCONFIG_CPU_MIPS32_R2=y\nCONFIG_CPU_MIPSR2=y\nCONFIG_CPU_MIPSR2_IRQ_EI=y\nCONFIG_CPU_MIPSR2_IRQ_VI=y\nCONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y\nCONFIG_CPU_PM=y\nCONFIG_CPU_R4K_CACHE_TLB=y\nCONFIG_CPU_RMAP=y\nCONFIG_CPU_SUPPORTS_32BIT_KERNEL=y\nCONFIG_CPU_SUPPORTS_HIGHMEM=y\nCONFIG_CPU_SUPPORTS_MSA=y\nCONFIG_CRC16=y\nCONFIG_CRC_CCITT=y\nCONFIG_CRYPTO_CBC=y\nCONFIG_CRYPTO_CRC32C=y\nCONFIG_CRYPTO_DEFLATE=y\nCONFIG_CRYPTO_HASH_INFO=y\nCONFIG_CRYPTO_LIB_POLY1305_RSIZE=2\nCONFIG_CRYPTO_LIB_SHA256=y\nCONFIG_CRYPTO_LZO=y\nCONFIG_CRYPTO_MD5=y\nCONFIG_CRYPTO_RNG=y\nCONFIG_CRYPTO_RNG2=y\nCONFIG_CRYPTO_SHA1=y\nCONFIG_CRYPTO_SHA256=y\nCONFIG_CRYPTO_ZSTD=y\nCONFIG_CSRC_R4K=y\nCONFIG_DMADEVICES=y\nCONFIG_DMA_ENGINE=y\nCONFIG_DMA_NONCOHERENT=y\nCONFIG_DMA_OF=y\nCONFIG_DMA_VIRTUAL_CHANNELS=y\nCONFIG_DTC=y\nCONFIG_DWMAC_GENERIC=y\nCONFIG_EARLY_PRINTK=y\nCONFIG_EARLY_PRINTK_8250=y\nCONFIG_EXT4_FS=y\nCONFIG_EXT4_FS_POSIX_ACL=y\nCONFIG_EXT4_FS_SECURITY=y\nCONFIG_FIXED_PHY=y\nCONFIG_FS_IOMAP=y\nCONFIG_FS_MBCACHE=y\nCONFIG_FS_POSIX_ACL=y\nCONFIG_FW_LOADER_PAGED_BUF=y\nCONFIG_GENERIC_ALLOCATOR=y\nCONFIG_GENERIC_ATOMIC64=y\nCONFIG_GENERIC_CLOCKEVENTS=y\nCONFIG_GENERIC_CMOS_UPDATE=y\nCONFIG_GENERIC_CPU_AUTOPROBE=y\nCONFIG_GENERIC_GETTIMEOFDAY=y\nCONFIG_GENERIC_IOMAP=y\nCONFIG_GENERIC_IRQ_CHIP=y\nCONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y\nCONFIG_GENERIC_IRQ_SHOW=y\nCONFIG_GENERIC_LIB_ASHLDI3=y\nCONFIG_GENERIC_LIB_ASHRDI3=y\nCONFIG_GENERIC_LIB_CMPDI2=y\nCONFIG_GENERIC_LIB_LSHRDI3=y\nCONFIG_GENERIC_LIB_UCMPDI2=y\nCONFIG_GENERIC_PCI_IOMAP=y\nCONFIG_GENERIC_PHY=y\nCONFIG_GENERIC_PINCONF=y\nCONFIG_GENERIC_PINCTRL_GROUPS=y\nCONFIG_GENERIC_PINMUX_FUNCTIONS=y\nCONFIG_GENERIC_SCHED_CLOCK=y\nCONFIG_GENERIC_SMP_IDLE_THREAD=y\nCONFIG_GENERIC_TIME_VSYSCALL=y\nCONFIG_GPIOLIB=y\nCONFIG_GPIOLIB_IRQCHIP=y\nCONFIG_HANDLE_DOMAIN_IRQ=y\nCONFIG_HARDWARE_WATCHPOINTS=y\nCONFIG_HAS_DMA=y\nCONFIG_HAS_IOMEM=y\nCONFIG_HAS_IOPORT_MAP=y\nCONFIG_HOTPLUG_CPU=y\nCONFIG_I2C=y\nCONFIG_I2C_BOARDINFO=y\nCONFIG_I2C_IMG=y\nCONFIG_IMGPDC_WDT=y\nCONFIG_IMG_MDC_DMA=y\nCONFIG_INITRAMFS_SOURCE=\"\"\nCONFIG_IRQCHIP=y\nCONFIG_IRQ_DOMAIN=y\nCONFIG_IRQ_DOMAIN_HIERARCHY=y\nCONFIG_IRQ_FORCED_THREADING=y\nCONFIG_IRQ_MIPS_CPU=y\nCONFIG_IRQ_WORK=y\nCONFIG_JBD2=y\nCONFIG_LEDS_GPIO=y\nCONFIG_LEDS_PWM=y\nCONFIG_LIBFDT=y\nCONFIG_LKDTM=y\nCONFIG_LOCK_DEBUGGING_SUPPORT=y\nCONFIG_LOG_BUF_SHIFT=18\nCONFIG_LZO_COMPRESS=y\nCONFIG_LZO_DECOMPRESS=y\nCONFIG_MACH_PISTACHIO=y\nCONFIG_MAGIC_SYSRQ=y\nCONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0\nCONFIG_MDIO_BUS=y\nCONFIG_MDIO_DEVICE=y\nCONFIG_MDIO_DEVRES=y\nCONFIG_MEMFD_CREATE=y\nCONFIG_MFD_SYSCON=y\nCONFIG_MICREL_PHY=y\nCONFIG_MIGRATION=y\nCONFIG_MIPS=y\nCONFIG_MIPS_ASID_BITS=8\nCONFIG_MIPS_ASID_SHIFT=0\nCONFIG_MIPS_CLOCK_VSYSCALL=y\nCONFIG_MIPS_CM=y\nCONFIG_MIPS_CMDLINE_DTB_EXTEND=y\n# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set\n# CONFIG_MIPS_CMDLINE_FROM_DTB is not set\nCONFIG_MIPS_CPC=y\nCONFIG_MIPS_CPS=y\n# CONFIG_MIPS_CPS_CPUIDLE is not set\n# CONFIG_MIPS_CPS_NS16550_BOOL is not set\nCONFIG_MIPS_CPS_PM=y\nCONFIG_MIPS_CPU_SCACHE=y\nCONFIG_MIPS_EBPF_JIT=y\n# CONFIG_MIPS_ELF_APPENDED_DTB is not set\nCONFIG_MIPS_EXTERNAL_TIMER=y\nCONFIG_MIPS_GIC=y\nCONFIG_MIPS_L1_CACHE_SHIFT=5\nCONFIG_MIPS_LD_CAN_LINK_VDSO=y\nCONFIG_MIPS_MT=y\nCONFIG_MIPS_MT_FPAFF=y\nCONFIG_MIPS_MT_SMP=y\nCONFIG_MIPS_NO_APPENDED_DTB=y\nCONFIG_MIPS_NR_CPU_NR_MAP=4\nCONFIG_MIPS_PERF_SHARED_TC_COUNTERS=y\n# CONFIG_MIPS_RAW_APPENDED_DTB is not set\nCONFIG_MIPS_SPRAM=y\nCONFIG_MMC=y\nCONFIG_MMC_BLOCK=y\nCONFIG_MMC_DW=y\n# CONFIG_MMC_DW_BLUEFIELD is not set\n# CONFIG_MMC_DW_EXYNOS is not set\n# CONFIG_MMC_DW_HI3798CV200 is not set\n# CONFIG_MMC_DW_K3 is not set\nCONFIG_MMC_DW_PLTFM=y\nCONFIG_MODULES_USE_ELF_REL=y\nCONFIG_MODULE_FORCE_UNLOAD=y\nCONFIG_MTD_CMDLINE_PARTS=y\nCONFIG_MTD_NAND_CORE=y\nCONFIG_MTD_SPI_NAND=y\nCONFIG_MTD_SPI_NOR=y\nCONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y\nCONFIG_MTD_SPI_NOR_USE_4K_SECTORS_LIMIT=16384\nCONFIG_MTD_UBI=y\nCONFIG_MTD_UBI_BEB_LIMIT=20\nCONFIG_MTD_UBI_BLOCK=y\nCONFIG_MTD_UBI_FASTMAP=y\nCONFIG_MTD_UBI_WL_THRESHOLD=4096\nCONFIG_NAMESPACES=y\nCONFIG_NEED_DMA_MAP_STATE=y\nCONFIG_NET_FLOW_LIMIT=y\nCONFIG_NET_NS=y\nCONFIG_NET_PTP_CLASSIFY=y\nCONFIG_NLS=y\nCONFIG_NO_GENERIC_PCI_IOPORT_MAP=y\nCONFIG_NO_HZ=y\nCONFIG_NO_HZ_COMMON=y\nCONFIG_NO_HZ_IDLE=y\nCONFIG_NR_CPUS=4\nCONFIG_OF=y\nCONFIG_OF_ADDRESS=y\nCONFIG_OF_EARLY_FLATTREE=y\nCONFIG_OF_FLATTREE=y\nCONFIG_OF_GPIO=y\nCONFIG_OF_IRQ=y\nCONFIG_OF_KOBJ=y\nCONFIG_OF_MDIO=y\nCONFIG_OF_NET=y\nCONFIG_PADATA=y\nCONFIG_PAGE_POOL=y\nCONFIG_PCI_DRIVERS_LEGACY=y\nCONFIG_PCS_XPCS=y\nCONFIG_PERF_USE_VMALLOC=y\nCONFIG_PGTABLE_LEVELS=2\nCONFIG_PHYLIB=y\nCONFIG_PHYLINK=y\nCONFIG_PHY_PISTACHIO_USB=y\nCONFIG_PINCTRL=y\nCONFIG_PINCTRL_PISTACHIO=y\nCONFIG_PISTACHIO_GPTIMER_CLKSRC=y\nCONFIG_POWER_SUPPLY=y\nCONFIG_PPS=y\n# CONFIG_PREEMPT_NONE is not set\nCONFIG_PREEMPT_VOLUNTARY=y\nCONFIG_PRINTK_TIME=y\nCONFIG_PROC_EVENTS=y\nCONFIG_PROFILING=y\nCONFIG_PTP_1588_CLOCK=y\nCONFIG_PWM=y\nCONFIG_PWM_IMG=y\nCONFIG_PWM_SYSFS=y\nCONFIG_QUEUED_RWLOCKS=y\nCONFIG_QUEUED_SPINLOCKS=y\nCONFIG_RATIONAL=y\nCONFIG_REGMAP=y\nCONFIG_REGMAP_MMIO=y\nCONFIG_REGMAP_SPI=y\nCONFIG_REGULATOR=y\nCONFIG_REGULATOR_FIXED_VOLTAGE=y\nCONFIG_REGULATOR_GPIO=y\nCONFIG_RESET_CONTROLLER=y\nCONFIG_RESET_PISTACHIO=y\nCONFIG_RFS_ACCEL=y\nCONFIG_RPS=y\nCONFIG_SCHEDSTATS=y\nCONFIG_SCHED_INFO=y\nCONFIG_SCSI=y\nCONFIG_SCSI_SPI_ATTRS=y\nCONFIG_SERIAL_8250_DW=y\nCONFIG_SERIAL_8250_DWLIB=y\nCONFIG_SERIAL_MCTRL_GPIO=y\nCONFIG_SERIAL_OF_PLATFORM=y\nCONFIG_SERIAL_SC16IS7XX=y\nCONFIG_SERIAL_SC16IS7XX_CORE=y\n# CONFIG_SERIAL_SC16IS7XX_I2C is not set\nCONFIG_SERIAL_SC16IS7XX_SPI=y\nCONFIG_SGL_ALLOC=y\nCONFIG_SG_POOL=y\nCONFIG_SMP=y\nCONFIG_SMP_UP=y\nCONFIG_SPI=y\nCONFIG_SPI_IMG_SPFI=y\nCONFIG_SPI_MASTER=y\nCONFIG_SPI_MEM=y\nCONFIG_SRAM=y\nCONFIG_SRCU=y\nCONFIG_STMMAC_ETH=y\nCONFIG_STMMAC_PLATFORM=y\n# CONFIG_STMMAC_SELFTESTS is not set\nCONFIG_SWPHY=y\nCONFIG_SYNC_R4K=y\nCONFIG_SYSCTL_EXCEPTION_TRACE=y\nCONFIG_SYS_HAS_CPU_MIPS32_R2=y\nCONFIG_SYS_HAS_EARLY_PRINTK=y\nCONFIG_SYS_SUPPORTS_32BIT_KERNEL=y\nCONFIG_SYS_SUPPORTS_ARBIT_HZ=y\nCONFIG_SYS_SUPPORTS_HOTPLUG_CPU=y\nCONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y\nCONFIG_SYS_SUPPORTS_MIPS_CPS=y\nCONFIG_SYS_SUPPORTS_MULTITHREADING=y\nCONFIG_SYS_SUPPORTS_RELOCATABLE=y\nCONFIG_SYS_SUPPORTS_SCHED_SMT=y\nCONFIG_SYS_SUPPORTS_SMP=y\nCONFIG_SYS_SUPPORTS_ZBOOT=y\nCONFIG_TARGET_ISA_REV=2\nCONFIG_TICK_CPU_ACCOUNTING=y\nCONFIG_TIMER_OF=y\nCONFIG_TIMER_PROBE=y\nCONFIG_TMPFS_POSIX_ACL=y\nCONFIG_TREE_RCU=y\nCONFIG_TREE_SRCU=y\nCONFIG_UBIFS_FS=y\nCONFIG_USB=y\nCONFIG_USB_ANNOUNCE_NEW_DEVICES=y\nCONFIG_USB_COMMON=y\nCONFIG_USB_DWC2=y\nCONFIG_USB_DWC2_DUAL_ROLE=y\nCONFIG_USB_EHCI_HCD=y\n# CONFIG_USB_EHCI_HCD_PLATFORM is not set\nCONFIG_USB_GADGET=y\nCONFIG_USB_ROLE_SWITCH=y\nCONFIG_USB_STORAGE=y\nCONFIG_USB_SUPPORT=y\nCONFIG_USER_NS=y\nCONFIG_USE_GENERIC_EARLY_PRINTK_8250=y\nCONFIG_USE_OF=y\nCONFIG_WATCHDOG_CORE=y\nCONFIG_WEAK_ORDERING=y\nCONFIG_XPS=y\nCONFIG_XXHASH=y\nCONFIG_ZLIB_DEFLATE=y\nCONFIG_ZLIB_INFLATE=y\nCONFIG_ZSMALLOC=y\n# CONFIG_ZSMALLOC_STAT is not set\nCONFIG_ZSTD_COMPRESS=y\nCONFIG_ZSTD_DECOMPRESS=y\n"
  },
  {
    "path": "target/linux/pistachio/image/Makefile",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2017 OpenWrt.org\n\ninclude $(TOPDIR)/rules.mk\ninclude $(INCLUDE_DIR)/image.mk\n\nKERNEL_LOADADDR := 0x80400000\n\ndefine Device/Default\n  PROFILES := Default\n  FILESYSTEMS := squashfs\n  KERNEL_DEPENDS = $$(wildcard $$(DTS_DIR)/$$(DEVICE_DTS).dts)\n  KERNEL = kernel-bin | gzip | fit gzip $$(DTS_DIR)/$$(DEVICE_DTS).dtb\n  KERNEL_SUFFIX := -kernel.itb\n  KERNEL_INSTALL := 1\n  KERNEL_IN_UBI := 1\n  DEVICE_DTS_CONFIG := config@1\n  IMAGES := factory.ubi sysupgrade.tar\n  IMAGE/factory.ubi := append-ubi\n  IMAGE/sysupgrade.tar := sysupgrade-tar\nendef\n\ndefine Device/img_creator-ci40\n  DEVICE_VENDOR := Imagination Technologies\n  DEVICE_MODEL := Creator Ci40 (VL-62899)\n  DEVICE_ALT0_VENDOR := Imagination Technologies\n  DEVICE_ALT0_MODEL := Marduk board\n  BOARD_NAME := img,pistachio-marduk\n  DEVICE_DTS := img/pistachio_marduk\n  BLOCKSIZE := 256KiB\n  PAGESIZE := 4KiB\n  DEVICE_PACKAGES := kmod-tpm-i2c-infineon kmod-ca8210 wpan-tools\nendef\n\nTARGET_DEVICES += img_creator-ci40\n\n\n$(eval $(call BuildImage))\n"
  },
  {
    "path": "target/linux/pistachio/patches-5.10/101-dmaengine-img-mdc-Handle-early-status-read.patch",
    "content": "From a2dd154377c9aa6ddda00d39b8c7c334e4fa16ff Mon Sep 17 00:00:00 2001\nFrom: Damien Horsley <damien.horsley@imgtec.com>\nDate: Tue, 22 Mar 2016 12:46:09 +0000\nSubject: dmaengine: img-mdc: Handle early status read\n\nIt is possible that mdc_tx_status may be called before the first\nnode has been read from memory.\n\nIn this case, the residue value stored in the register is undefined.\nReturn the transfer size instead.\n\nSigned-off-by: Damien Horsley <damien.horsley@imgtec.com>\n---\n drivers/dma/img-mdc-dma.c | 40 ++++++++++++++++++++++++----------------\n 1 file changed, 24 insertions(+), 16 deletions(-)\n\n--- a/drivers/dma/img-mdc-dma.c\n+++ b/drivers/dma/img-mdc-dma.c\n@@ -618,25 +618,33 @@ static enum dma_status mdc_tx_status(str\n \t\t\t(MDC_CMDS_PROCESSED_CMDS_DONE_MASK + 1);\n \n \t\t/*\n-\t\t * If the command loaded event hasn't been processed yet, then\n-\t\t * the difference above includes an extra command.\n+\t\t * If the first node has not yet been read from memory,\n+\t\t * the residue register value is undefined\n \t\t */\n-\t\tif (!mdesc->cmd_loaded)\n-\t\t\tcmds--;\n-\t\telse\n-\t\t\tcmds += mdesc->list_cmds_done;\n-\n-\t\tbytes = mdesc->list_xfer_size;\n-\t\tldesc = mdesc->list;\n-\t\tfor (i = 0; i < cmds; i++) {\n-\t\t\tbytes -= ldesc->xfer_size + 1;\n-\t\t\tldesc = ldesc->next_desc;\n-\t\t}\n-\t\tif (ldesc) {\n-\t\t\tif (residue != MDC_TRANSFER_SIZE_MASK)\n-\t\t\t\tbytes -= ldesc->xfer_size - residue;\n+\t\tif (!mdesc->cmd_loaded && !cmds) {\n+\t\t\tbytes = mdesc->list_xfer_size;\n+\t\t} else {\n+\t\t\t/*\n+\t\t\t * If the command loaded event hasn't been processed yet, then\n+\t\t\t * the difference above includes an extra command.\n+\t\t\t */\n+\t\t\tif (!mdesc->cmd_loaded)\n+\t\t\t\tcmds--;\n \t\t\telse\n+\t\t\t\tcmds += mdesc->list_cmds_done;\n+\n+\t\t\tbytes = mdesc->list_xfer_size;\n+\t\t\tldesc = mdesc->list;\n+\t\t\tfor (i = 0; i < cmds; i++) {\n \t\t\t\tbytes -= ldesc->xfer_size + 1;\n+\t\t\t\tldesc = ldesc->next_desc;\n+\t\t\t}\n+\t\t\tif (ldesc) {\n+\t\t\t\tif (residue != MDC_TRANSFER_SIZE_MASK)\n+\t\t\t\t\tbytes -= ldesc->xfer_size - residue;\n+\t\t\t\telse\n+\t\t\t\t\tbytes -= ldesc->xfer_size + 1;\n+\t\t\t}\n \t\t}\n \t}\n \tspin_unlock_irqrestore(&mchan->vc.lock, flags);\n"
  },
  {
    "path": "target/linux/pistachio/patches-5.10/102-spi-img-spfi-Implement-dual-and-quad-mode.patch",
    "content": "From cd2a6af51553d38072cd31699b58d16ca6176ef5 Mon Sep 17 00:00:00 2001\nFrom: Ionela Voinescu <ionela.voinescu@imgtec.com>\nDate: Thu, 2 Feb 2017 16:46:14 +0000\nSubject: spi: img-spfi: Implement dual and quad mode\n\nFor dual and quad modes to work the SPFI controller needs\nto have information about command/address/dummy bytes in the\ntransaction register. This information is not relevant for\nsingle mode, and therefore it can have any value in the\nallowed range. Therefore, for any read or write transfers of less\nthan 8 bytes (cmd = 1 byte, addr up to 7 bytes), SPFI will be\nconfigured, but not enabled (unless it is the last transfer in\nthe queue). The transfer will be enabled by the subsequent tranfer.\nA pending transfer is determined by the content of the transaction\nregister: if command part is set and tsize is not.\n\nThis way we ensure that for dual and quad transactions\nthe command request size will apear in the command/address part\nof the transaction register, while the data size will be in\ntsize, all data being sent/received in the same transaction (as\nset up in the transaction register).\n\nSigned-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>\nSigned-off-by: Ezequiel Garcia <ezequiel.garcia@imgtec.com>\n---\n drivers/spi/spi-img-spfi.c | 96 ++++++++++++++++++++++++++++++++++++++++------\n 1 file changed, 85 insertions(+), 11 deletions(-)\n\n--- a/drivers/spi/spi-img-spfi.c\n+++ b/drivers/spi/spi-img-spfi.c\n@@ -36,7 +36,8 @@\n #define SPFI_CONTROL_SOFT_RESET\t\t\tBIT(11)\n #define SPFI_CONTROL_SEND_DMA\t\t\tBIT(10)\n #define SPFI_CONTROL_GET_DMA\t\t\tBIT(9)\n-#define SPFI_CONTROL_SE\t\t\tBIT(8)\n+#define SPFI_CONTROL_SE\t\t\t\tBIT(8)\n+#define SPFI_CONTROL_TX_RX\t\t\tBIT(1)\n #define SPFI_CONTROL_TMODE_SHIFT\t\t5\n #define SPFI_CONTROL_TMODE_MASK\t\t\t0x7\n #define SPFI_CONTROL_TMODE_SINGLE\t\t0\n@@ -47,6 +48,10 @@\n #define SPFI_TRANSACTION\t\t\t0x18\n #define SPFI_TRANSACTION_TSIZE_SHIFT\t\t16\n #define SPFI_TRANSACTION_TSIZE_MASK\t\t0xffff\n+#define SPFI_TRANSACTION_CMD_SHIFT\t\t13\n+#define SPFI_TRANSACTION_CMD_MASK\t\t0x7\n+#define SPFI_TRANSACTION_ADDR_SHIFT\t\t10\n+#define SPFI_TRANSACTION_ADDR_MASK\t\t0x7\n \n #define SPFI_PORT_STATE\t\t\t\t0x1c\n #define SPFI_PORT_STATE_DEV_SEL_SHIFT\t\t20\n@@ -83,6 +88,7 @@\n  */\n #define SPFI_32BIT_FIFO_SIZE\t\t\t64\n #define SPFI_8BIT_FIFO_SIZE\t\t\t16\n+#define SPFI_DATA_REQUEST_MAX_SIZE\t\t8\n \n struct img_spfi {\n \tstruct device *dev;\n@@ -99,6 +105,8 @@ struct img_spfi {\n \tstruct dma_chan *tx_ch;\n \tbool tx_dma_busy;\n \tbool rx_dma_busy;\n+\n+\tbool complete;\n };\n \n static inline u32 spfi_readl(struct img_spfi *spfi, u32 reg)\n@@ -115,9 +123,11 @@ static inline void spfi_start(struct img\n {\n \tu32 val;\n \n-\tval = spfi_readl(spfi, SPFI_CONTROL);\n-\tval |= SPFI_CONTROL_SPFI_EN;\n-\tspfi_writel(spfi, val, SPFI_CONTROL);\n+\tif (spfi->complete) {\n+\t\tval = spfi_readl(spfi, SPFI_CONTROL);\n+\t\tval |= SPFI_CONTROL_SPFI_EN;\n+\t\tspfi_writel(spfi, val, SPFI_CONTROL);\n+\t}\n }\n \n static inline void spfi_reset(struct img_spfi *spfi)\n@@ -130,12 +140,21 @@ static int spfi_wait_all_done(struct img\n {\n \tunsigned long timeout = jiffies + msecs_to_jiffies(50);\n \n+\tif (!(spfi->complete))\n+\t\treturn 0;\n+\n \twhile (time_before(jiffies, timeout)) {\n \t\tu32 status = spfi_readl(spfi, SPFI_INTERRUPT_STATUS);\n \n \t\tif (status & SPFI_INTERRUPT_ALLDONETRIG) {\n \t\t\tspfi_writel(spfi, SPFI_INTERRUPT_ALLDONETRIG,\n \t\t\t\t    SPFI_INTERRUPT_CLEAR);\n+\t\t\t/*\n+\t\t\t * Disable SPFI for it not to interfere with\n+\t\t\t * pending transactions\n+\t\t\t */\n+\t\t\tspfi_writel(spfi, spfi_readl(spfi, SPFI_CONTROL)\n+\t\t\t& ~SPFI_CONTROL_SPFI_EN, SPFI_CONTROL);\n \t\t\treturn 0;\n \t\t}\n \t\tcpu_relax();\n@@ -441,9 +460,32 @@ static void img_spfi_config(struct spi_m\n \t\t\t    struct spi_transfer *xfer)\n {\n \tstruct img_spfi *spfi = spi_master_get_devdata(spi->master);\n-\tu32 val, div;\n+\tu32 val, div, transact;\n+\tbool is_pending;\n \n \t/*\n+\t * For read or write transfers of less than 8 bytes (cmd = 1 byte,\n+\t * addr up to 7 bytes), SPFI will be configured, but not enabled\n+\t * (unless it is the last transfer in the queue).The transfer will\n+\t * be enabled by the subsequent transfer.\n+\t * A pending transfer is determined by the content of the\n+\t * transaction register: if command part is set and tsize\n+\t * is not\n+\t */\n+\ttransact = spfi_readl(spfi, SPFI_TRANSACTION);\n+\tis_pending = ((transact >> SPFI_TRANSACTION_CMD_SHIFT) &\n+\t\t\tSPFI_TRANSACTION_CMD_MASK) &&\n+\t\t\t(!((transact >> SPFI_TRANSACTION_TSIZE_SHIFT) &\n+\t\t\tSPFI_TRANSACTION_TSIZE_MASK));\n+\n+\t/* If there are no pending transactions it's OK to soft reset */\n+\tif (!is_pending) {\n+\t\t/* Start the transaction from a known (reset) state */\n+\t\tspfi_reset(spfi);\n+\t}\n+\n+\t/*\n+\t * Before anything else, set up parameters.\n \t * output = spfi_clk * (BITCLK / 512), where BITCLK must be a\n \t * power of 2 up to 128\n \t */\n@@ -456,20 +498,52 @@ static void img_spfi_config(struct spi_m\n \tval |= div << SPFI_DEVICE_PARAMETER_BITCLK_SHIFT;\n \tspfi_writel(spfi, val, SPFI_DEVICE_PARAMETER(spi->chip_select));\n \n-\tspfi_writel(spfi, xfer->len << SPFI_TRANSACTION_TSIZE_SHIFT,\n-\t\t    SPFI_TRANSACTION);\n+\tif (!list_is_last(&xfer->transfer_list, &master->cur_msg->transfers) &&\n+\t\t/*\n+\t\t * For duplex mode (both the tx and rx buffers are !NULL) the\n+\t\t * CMD, ADDR, and DUMMY byte parts of the transaction register\n+\t\t * should always be 0 and therefore the pending transfer\n+\t\t * technique cannot be used.\n+\t\t */\n+\t\t(xfer->tx_buf) && (!xfer->rx_buf) &&\n+\t\t(xfer->len <= SPFI_DATA_REQUEST_MAX_SIZE) && !is_pending) {\n+\t\ttransact = (1 & SPFI_TRANSACTION_CMD_MASK) <<\n+\t\t\tSPFI_TRANSACTION_CMD_SHIFT;\n+\t\ttransact |= ((xfer->len - 1) & SPFI_TRANSACTION_ADDR_MASK) <<\n+\t\t\tSPFI_TRANSACTION_ADDR_SHIFT;\n+\t\tspfi->complete = false;\n+\t} else {\n+\t\tspfi->complete = true;\n+\t\tif (is_pending) {\n+\t\t\t/* Keep setup from pending transfer */\n+\t\t\ttransact |= ((xfer->len & SPFI_TRANSACTION_TSIZE_MASK) <<\n+\t\t\t\tSPFI_TRANSACTION_TSIZE_SHIFT);\n+\t\t} else {\n+\t\t\ttransact = ((xfer->len & SPFI_TRANSACTION_TSIZE_MASK) <<\n+\t\t\t\tSPFI_TRANSACTION_TSIZE_SHIFT);\n+\t\t}\n+\t}\n+\tspfi_writel(spfi, transact, SPFI_TRANSACTION);\n \n \tval = spfi_readl(spfi, SPFI_CONTROL);\n \tval &= ~(SPFI_CONTROL_SEND_DMA | SPFI_CONTROL_GET_DMA);\n-\tif (xfer->tx_buf)\n+\t/*\n+\t * We set up send DMA for pending transfers also, as\n+\t * those are always send transfers\n+\t */\n+\tif ((xfer->tx_buf) || is_pending)\n \t\tval |= SPFI_CONTROL_SEND_DMA;\n-\tif (xfer->rx_buf)\n+\tif (xfer->tx_buf)\n+\t\tval |= SPFI_CONTROL_TX_RX;\n+\tif (xfer->rx_buf) {\n \t\tval |= SPFI_CONTROL_GET_DMA;\n+\t\tval &= ~SPFI_CONTROL_TX_RX;\n+\t}\n \tval &= ~(SPFI_CONTROL_TMODE_MASK << SPFI_CONTROL_TMODE_SHIFT);\n-\tif (xfer->tx_nbits == SPI_NBITS_DUAL &&\n+\tif (xfer->tx_nbits == SPI_NBITS_DUAL ||\n \t    xfer->rx_nbits == SPI_NBITS_DUAL)\n \t\tval |= SPFI_CONTROL_TMODE_DUAL << SPFI_CONTROL_TMODE_SHIFT;\n-\telse if (xfer->tx_nbits == SPI_NBITS_QUAD &&\n+\telse if (xfer->tx_nbits == SPI_NBITS_QUAD ||\n \t\t xfer->rx_nbits == SPI_NBITS_QUAD)\n \t\tval |= SPFI_CONTROL_TMODE_QUAD << SPFI_CONTROL_TMODE_SHIFT;\n \tval |= SPFI_CONTROL_SE;\n"
  },
  {
    "path": "target/linux/pistachio/patches-5.10/104-spi-img-spfi-use-device-0-configuration-for-all-devi.patch",
    "content": "From 905ee06a9966113fe51d6bad1819759cb30fd0bd Mon Sep 17 00:00:00 2001\nFrom: Ionela Voinescu <ionela.voinescu@imgtec.com>\nDate: Tue, 9 Feb 2016 10:18:31 +0000\nSubject: spi: img-spfi: use device 0 configuration for all devices\n\nGiven that we control the chip select line externally\nwe can use only one parameter register (device 0 parameter\nregister) and one set of configuration bits (port configuration\nbits for device 0) for all devices (all chip select lines).\n\nSigned-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>\n---\n drivers/spi/spi-img-spfi.c | 23 ++++++++++++++++-------\n 1 file changed, 16 insertions(+), 7 deletions(-)\n\n--- a/drivers/spi/spi-img-spfi.c\n+++ b/drivers/spi/spi-img-spfi.c\n@@ -429,18 +429,23 @@ static int img_spfi_prepare(struct spi_m\n \tstruct img_spfi *spfi = spi_master_get_devdata(master);\n \tu32 val;\n \n+\t/*\n+\t * The chip select line is controlled externally so\n+\t * we can use the CS0 configuration for all devices\n+\t */\n \tval = spfi_readl(spfi, SPFI_PORT_STATE);\n+\n+\t/* 0 for device selection */\n \tval &= ~(SPFI_PORT_STATE_DEV_SEL_MASK <<\n \t\t SPFI_PORT_STATE_DEV_SEL_SHIFT);\n-\tval |= msg->spi->chip_select << SPFI_PORT_STATE_DEV_SEL_SHIFT;\n \tif (msg->spi->mode & SPI_CPHA)\n-\t\tval |= SPFI_PORT_STATE_CK_PHASE(msg->spi->chip_select);\n+\t\tval |= SPFI_PORT_STATE_CK_PHASE(0);\n \telse\n-\t\tval &= ~SPFI_PORT_STATE_CK_PHASE(msg->spi->chip_select);\n+\t\tval &= ~SPFI_PORT_STATE_CK_PHASE(0);\n \tif (msg->spi->mode & SPI_CPOL)\n-\t\tval |= SPFI_PORT_STATE_CK_POL(msg->spi->chip_select);\n+\t\tval |= SPFI_PORT_STATE_CK_POL(0);\n \telse\n-\t\tval &= ~SPFI_PORT_STATE_CK_POL(msg->spi->chip_select);\n+\t\tval &= ~SPFI_PORT_STATE_CK_POL(0);\n \tspfi_writel(spfi, val, SPFI_PORT_STATE);\n \n \treturn 0;\n@@ -492,11 +497,15 @@ static void img_spfi_config(struct spi_m\n \tdiv = DIV_ROUND_UP(clk_get_rate(spfi->spfi_clk), xfer->speed_hz);\n \tdiv = clamp(512 / (1 << get_count_order(div)), 1, 128);\n \n-\tval = spfi_readl(spfi, SPFI_DEVICE_PARAMETER(spi->chip_select));\n+\t/*\n+\t * The chip select line is controlled externally so\n+\t * we can use the CS0 parameters for all devices\n+\t */\n+\tval = spfi_readl(spfi, SPFI_DEVICE_PARAMETER(0));\n \tval &= ~(SPFI_DEVICE_PARAMETER_BITCLK_MASK <<\n \t\t SPFI_DEVICE_PARAMETER_BITCLK_SHIFT);\n \tval |= div << SPFI_DEVICE_PARAMETER_BITCLK_SHIFT;\n-\tspfi_writel(spfi, val, SPFI_DEVICE_PARAMETER(spi->chip_select));\n+\tspfi_writel(spfi, val, SPFI_DEVICE_PARAMETER(0));\n \n \tif (!list_is_last(&xfer->transfer_list, &master->cur_msg->transfers) &&\n \t\t/*\n"
  },
  {
    "path": "target/linux/pistachio/patches-5.10/105-spi-img-spfi-RX-maximum-burst-size-for-DMA-is-8.patch",
    "content": "From 56466f505f58f44b69feb7eaed3b506842800456 Mon Sep 17 00:00:00 2001\nFrom: Ionela Voinescu <ionela.voinescu@imgtec.com>\nDate: Tue, 1 Mar 2016 17:49:45 +0000\nSubject: spi: img-spfi: RX maximum burst size for DMA is 8\n\nThe depth of the FIFOs is 16 bytes. The DMA request line is tied\nto the half full/empty (depending on the use of the TX or RX FIFO)\nthreshold. For the TX FIFO, if you set a burst size of 8 (equal to\nhalf the depth) the first burst goes into FIFO without any issues,\nbut due the latency involved (the time the data leaves  the DMA\nengine to the time it arrives at the FIFO), the DMA might trigger\nanother burst of 8. But given that there is no space for 2 additonal\nbursts of 8, this would result in a failure. Therefore, we have to\nkeep the burst size for TX to 4 to accomodate for an extra burst.\n\nFor the read (RX) scenario, the DMA request line goes high when\nthere is at least 8 entries in the FIFO (half full), and we can\nprogram the burst size to be 8 because the risk of accidental burst\ndoes not exist. The DMA engine will not trigger another read until\nthe read data for all the burst it has sent out has been received.\n\nWhile here, move the burst size setting outside of the if/else branches\nas they have the same value for both 8 and 32 bit data widths.\n\nSigned-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>\n---\n drivers/spi/spi-img-spfi.c | 6 ++----\n 1 file changed, 2 insertions(+), 4 deletions(-)\n\n--- a/drivers/spi/spi-img-spfi.c\n+++ b/drivers/spi/spi-img-spfi.c\n@@ -338,12 +338,11 @@ static int img_spfi_start_dma(struct spi\n \t\tif (xfer->len % 4 == 0) {\n \t\t\trxconf.src_addr = spfi->phys + SPFI_RX_32BIT_VALID_DATA;\n \t\t\trxconf.src_addr_width = 4;\n-\t\t\trxconf.src_maxburst = 4;\n \t\t} else {\n \t\t\trxconf.src_addr = spfi->phys + SPFI_RX_8BIT_VALID_DATA;\n \t\t\trxconf.src_addr_width = 1;\n-\t\t\trxconf.src_maxburst = 4;\n \t\t}\n+\t\trxconf.src_maxburst = 8;\n \t\tdmaengine_slave_config(spfi->rx_ch, &rxconf);\n \n \t\trxdesc = dmaengine_prep_slave_sg(spfi->rx_ch, xfer->rx_sg.sgl,\n@@ -362,12 +361,11 @@ static int img_spfi_start_dma(struct spi\n \t\tif (xfer->len % 4 == 0) {\n \t\t\ttxconf.dst_addr = spfi->phys + SPFI_TX_32BIT_VALID_DATA;\n \t\t\ttxconf.dst_addr_width = 4;\n-\t\t\ttxconf.dst_maxburst = 4;\n \t\t} else {\n \t\t\ttxconf.dst_addr = spfi->phys + SPFI_TX_8BIT_VALID_DATA;\n \t\t\ttxconf.dst_addr_width = 1;\n-\t\t\ttxconf.dst_maxburst = 4;\n \t\t}\n+\t\ttxconf.dst_maxburst = 4;\n \t\tdmaengine_slave_config(spfi->tx_ch, &txconf);\n \n \t\ttxdesc = dmaengine_prep_slave_sg(spfi->tx_ch, xfer->tx_sg.sgl,\n"
  },
  {
    "path": "target/linux/pistachio/patches-5.10/106-spi-img-spfi-finish-every-transfer-cleanly.patch",
    "content": "From 5fcca3fd4b621d7b5bdeca18d36dfc6ca6cfe383 Mon Sep 17 00:00:00 2001\nFrom: Ionela Voinescu <ionela.voinescu@imgtec.com>\nDate: Wed, 10 Aug 2016 11:42:26 +0100\nSubject: spi: img-spfi: finish every transfer cleanly\n\nBefore this change, the interrupt status bit that signaled\nthe end of a tranfers was cleared in the wait_all_done\nfunction. That functionality triggered issues for DMA\nduplex transactions where the wait function was called\ntwice, in both the TX and RX callbacks.\n\nIn order to fix the issue, clear all interrupt data bits\nat the end of a PIO transfer or at the end of both TX and RX\nduplex transfers, if the transfer is not a pending tranfer\n(command waiting for data). After that, the status register\nis checked for new incoming data or new data requests to be\nsignaled. If SPFI finished cleanly, no new interrupt data\nbits should be set.\n\nSigned-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>\n---\n drivers/spi/spi-img-spfi.c | 49 +++++++++++++++++++++++++++++++++-------------\n 1 file changed, 35 insertions(+), 14 deletions(-)\n\n--- a/drivers/spi/spi-img-spfi.c\n+++ b/drivers/spi/spi-img-spfi.c\n@@ -79,6 +79,14 @@\n #define SPFI_INTERRUPT_SDE\t\t\tBIT(1)\n #define SPFI_INTERRUPT_SDTRIG\t\t\tBIT(0)\n \n+#define SPFI_INTERRUPT_DATA_BITS\t\t(SPFI_INTERRUPT_SDHF |\\\n+\t\t\t\t\t\tSPFI_INTERRUPT_SDFUL |\\\n+\t\t\t\t\t\tSPFI_INTERRUPT_GDEX32BIT |\\\n+\t\t\t\t\t\tSPFI_INTERRUPT_GDHF |\\\n+\t\t\t\t\t\tSPFI_INTERRUPT_GDFUL |\\\n+\t\t\t\t\t\tSPFI_INTERRUPT_ALLDONETRIG |\\\n+\t\t\t\t\t\tSPFI_INTERRUPT_GDEX8BIT)\n+\n /*\n  * There are four parallel FIFOs of 16 bytes each.  The word buffer\n  * (*_32BIT_VALID_DATA) accesses all four FIFOs at once, resulting in an\n@@ -136,6 +144,23 @@ static inline void spfi_reset(struct img\n \tspfi_writel(spfi, 0, SPFI_CONTROL);\n }\n \n+static inline void spfi_finish(struct img_spfi *spfi)\n+{\n+\tif (!(spfi->complete))\n+\t\treturn;\n+\n+\t/* Clear data bits as all transfers(TX and RX) have finished */\n+\tspfi_writel(spfi, SPFI_INTERRUPT_DATA_BITS, SPFI_INTERRUPT_CLEAR);\n+\tif (spfi_readl(spfi, SPFI_INTERRUPT_STATUS) & SPFI_INTERRUPT_DATA_BITS) {\n+\t\tdev_err(spfi->dev, \"SPFI did not finish transfer cleanly.\\n\");\n+\t\tspfi_reset(spfi);\n+\t}\n+\t/* Disable SPFI for it not to interfere with pending transactions */\n+\tspfi_writel(spfi,\n+\t\t    spfi_readl(spfi, SPFI_CONTROL) & ~SPFI_CONTROL_SPFI_EN,\n+\t\t    SPFI_CONTROL);\n+}\n+\n static int spfi_wait_all_done(struct img_spfi *spfi)\n {\n \tunsigned long timeout = jiffies + msecs_to_jiffies(50);\n@@ -144,19 +169,9 @@ static int spfi_wait_all_done(struct img\n \t\treturn 0;\n \n \twhile (time_before(jiffies, timeout)) {\n-\t\tu32 status = spfi_readl(spfi, SPFI_INTERRUPT_STATUS);\n-\n-\t\tif (status & SPFI_INTERRUPT_ALLDONETRIG) {\n-\t\t\tspfi_writel(spfi, SPFI_INTERRUPT_ALLDONETRIG,\n-\t\t\t\t    SPFI_INTERRUPT_CLEAR);\n-\t\t\t/*\n-\t\t\t * Disable SPFI for it not to interfere with\n-\t\t\t * pending transactions\n-\t\t\t */\n-\t\t\tspfi_writel(spfi, spfi_readl(spfi, SPFI_CONTROL)\n-\t\t\t& ~SPFI_CONTROL_SPFI_EN, SPFI_CONTROL);\n+\t\tif (spfi_readl(spfi, SPFI_INTERRUPT_STATUS) &\n+\t\t    SPFI_INTERRUPT_ALLDONETRIG)\n \t\t\treturn 0;\n-\t\t}\n \t\tcpu_relax();\n \t}\n \n@@ -288,6 +303,8 @@ static int img_spfi_start_pio(struct spi\n \t}\n \n \tret = spfi_wait_all_done(spfi);\n+\tspfi_finish(spfi);\n+\n \tif (ret < 0)\n \t\treturn ret;\n \n@@ -303,8 +320,10 @@ static void img_spfi_dma_rx_cb(void *dat\n \n \tspin_lock_irqsave(&spfi->lock, flags);\n \tspfi->rx_dma_busy = false;\n-\tif (!spfi->tx_dma_busy)\n+\tif (!spfi->tx_dma_busy) {\n+\t\tspfi_finish(spfi);\n \t\tspi_finalize_current_transfer(spfi->master);\n+\t}\n \tspin_unlock_irqrestore(&spfi->lock, flags);\n }\n \n@@ -317,8 +336,10 @@ static void img_spfi_dma_tx_cb(void *dat\n \n \tspin_lock_irqsave(&spfi->lock, flags);\n \tspfi->tx_dma_busy = false;\n-\tif (!spfi->rx_dma_busy)\n+\tif (!spfi->rx_dma_busy) {\n+\t\tspfi_finish(spfi);\n \t\tspi_finalize_current_transfer(spfi->master);\n+\t}\n \tspin_unlock_irqrestore(&spfi->lock, flags);\n }\n \n"
  },
  {
    "path": "target/linux/pistachio/patches-5.10/108-clk-pistachio-Fix-wrong-SDHost-card-speed.patch",
    "content": "From 3642843a06025ec333d7e92580cf52cb8db2a652 Mon Sep 17 00:00:00 2001\nFrom: Govindraj Raja <Govindraj.Raja@imgtec.com>\nDate: Fri, 8 Jan 2016 16:36:07 +0000\nSubject: clk: pistachio: Fix wrong SDHost card speed\n\nThe SDHost currently clocks the card 4x slower than it\nshould do, because there is fixed divide by 4 in the\nsdhost wrapper that is not present in the clock tree.\nTo model this add a fixed divide by 4 clock node in\nthe SDHost clock path.\n\nThis will ensure the right clock frequency is selected when\nthe mmc driver tries to configure frequency on card insert.\n\nSigned-off-by: Govindraj Raja <Govindraj.Raja@imgtec.com>\n---\n drivers/clk/pistachio/clk-pistachio.c     | 3 ++-\n include/dt-bindings/clock/pistachio-clk.h | 1 +\n 2 files changed, 3 insertions(+), 1 deletion(-)\n\n--- a/drivers/clk/pistachio/clk-pistachio.c\n+++ b/drivers/clk/pistachio/clk-pistachio.c\n@@ -41,7 +41,7 @@ static struct pistachio_gate pistachio_g\n \tGATE(CLK_AUX_ADC_INTERNAL, \"aux_adc_internal\", \"sys_internal_div\",\n \t     0x104, 22),\n \tGATE(CLK_AUX_ADC, \"aux_adc\", \"aux_adc_div\", 0x104, 23),\n-\tGATE(CLK_SD_HOST, \"sd_host\", \"sd_host_div\", 0x104, 24),\n+\tGATE(CLK_SD_HOST, \"sd_host\", \"sd_host_div4\", 0x104, 24),\n \tGATE(CLK_BT, \"bt\", \"bt_div\", 0x104, 25),\n \tGATE(CLK_BT_DIV4, \"bt_div4\", \"bt_div4_div\", 0x104, 26),\n \tGATE(CLK_BT_DIV8, \"bt_div8\", \"bt_div8_div\", 0x104, 27),\n@@ -51,6 +51,7 @@ static struct pistachio_gate pistachio_g\n static struct pistachio_fixed_factor pistachio_ffs[] __initdata = {\n \tFIXED_FACTOR(CLK_WIFI_DIV4, \"wifi_div4\", \"wifi_pll\", 4),\n \tFIXED_FACTOR(CLK_WIFI_DIV8, \"wifi_div8\", \"wifi_pll\", 8),\n+\tFIXED_FACTOR(CLK_SDHOST_DIV4, \"sd_host_div4\", \"sd_host_div\", 4),\n };\n \n static struct pistachio_div pistachio_divs[] __initdata = {\n--- a/include/dt-bindings/clock/pistachio-clk.h\n+++ b/include/dt-bindings/clock/pistachio-clk.h\n@@ -18,6 +18,7 @@\n /* Fixed-factor clocks */\n #define CLK_WIFI_DIV4\t\t\t16\n #define CLK_WIFI_DIV8\t\t\t17\n+#define CLK_SDHOST_DIV4\t\t\t18\n \n /* Gate clocks */\n #define CLK_MIPS\t\t\t32\n"
  },
  {
    "path": "target/linux/pistachio/patches-5.10/109-MIPS-DTS-img-marduk-switch-mmc-to-1-bit-mode.patch",
    "content": "From 981c1d416af45eff207227aec106381ac23aac99 Mon Sep 17 00:00:00 2001\nFrom: Ian Pozella <Ian.Pozella@imgtec.com>\nDate: Mon, 20 Feb 2017 10:00:52 +0000\nSubject: MIPS: DTS: img: marduk: switch mmc to 1 bit mode\n\nThe mmc block in Pistachio allows 1 to 8 data bits to be used.\nMarduk uses 4 bits allowing the upper 4 bits to be allocated\nto the Mikrobus ports. However these bits are still connected\ninternally meaning the mmc block recieves signals on all data lines\nand seems the internal HW CRC checks get corrupted by this erroneous\ndata.\n\nWe cannot control what data is sent on these lines because they go\nto external ports. 1 bit mode does not exhibit the issue hence the\nsafe default is to use this. If a user knows that in their use case\nthey will not use the upper bits then they can set to 4 bit mode in\norder to improve performance.\n\nAlso make sure that the upper 4 bits don't get allocated to the mmc\ndriver (the default is to assign all 8 pins) so they can be allocated\nto other drivers. Allocating all 4 despite setting 1 bit mode as this\nmatches what is there in hardware.\n\nSigned-off-by: Ian Pozella <Ian.Pozella@imgtec.com>\n---\n arch/mips/boot/dts/img/pistachio_marduk.dts | 3 ++-\n 1 file changed, 2 insertions(+), 1 deletion(-)\n\n--- a/arch/mips/boot/dts/img/pistachio_marduk.dts\n+++ b/arch/mips/boot/dts/img/pistachio_marduk.dts\n@@ -117,7 +117,7 @@\n \n &sdhost {\n \tstatus = \"okay\";\n-\tbus-width = <4>;\n+\tbus-width = <1>;\n \tdisable-wp;\n };\n \n@@ -127,6 +127,7 @@\n \n &pin_sdhost_data {\n \tdrive-strength = <2>;\n+\tpins = \"mfio17\", \"mfio18\", \"mfio19\", \"mfio20\";\n };\n \n &pwm {\n"
  },
  {
    "path": "target/linux/pistachio/patches-5.10/401-mtd-nor-support-mtd-name-from-device-tree.patch",
    "content": "From f32bc2aa01edcba2f2ed5db151cf183eac9ef919 Mon Sep 17 00:00:00 2001\nFrom: Abhimanyu Vishwakarma <Abhimanyu.Vishwakarma@imgtec.com>\nDate: Sat, 25 Feb 2017 16:42:50 +0000\nSubject: mtd: nor: support mtd name from device tree\n\nSigned-off-by: Abhimanyu Vishwakarma <Abhimanyu.Vishwakarma@imgtec.com>\n---\n drivers/mtd/spi-nor/spi-nor.c | 8 +++++++-\n 1 file changed, 7 insertions(+), 1 deletion(-)\n\n--- a/drivers/mtd/spi-nor/core.c\n+++ b/drivers/mtd/spi-nor/core.c\n@@ -3147,6 +3147,7 @@ int spi_nor_scan(struct spi_nor *nor, co\n \tstruct device *dev = nor->dev;\n \tstruct mtd_info *mtd = &nor->mtd;\n \tstruct device_node *np = spi_nor_get_flash_node(nor);\n+\tconst char __maybe_unused *of_mtd_name = NULL;\n \tint ret;\n \tint i;\n \n@@ -3201,7 +3202,12 @@ int spi_nor_scan(struct spi_nor *nor, co\n \tif (ret)\n \t\treturn ret;\n \n-\tif (!mtd->name)\n+#ifdef CONFIG_MTD_OF_PARTS\n+\tof_property_read_string(np, \"linux,mtd-name\", &of_mtd_name);\n+#endif\n+\tif (of_mtd_name)\n+\t\tmtd->name = of_mtd_name;\n+\telse if (!mtd->name)\n \t\tmtd->name = dev_name(dev);\n \tmtd->priv = nor;\n \tmtd->type = MTD_NORFLASH;\n--- a/drivers/mtd/mtdcore.c\n+++ b/drivers/mtd/mtdcore.c\n@@ -778,6 +778,17 @@ out_error:\n  */\n static void mtd_set_dev_defaults(struct mtd_info *mtd)\n {\n+#ifdef CONFIG_MTD_OF_PARTS\n+\tconst char __maybe_unused *of_mtd_name = NULL;\n+\tstruct device_node *np;\n+\n+\tnp = mtd_get_of_node(mtd);\n+\tif (np && !mtd->name) {\n+\t\tof_property_read_string(np, \"linux,mtd-name\", &of_mtd_name);\n+\t\tif (of_mtd_name)\n+\t\t\tmtd->name = of_mtd_name;\n+\t} else\n+#endif\n \tif (mtd->dev.parent) {\n \t\tif (!mtd->owner && mtd->dev.parent->driver)\n \t\t\tmtd->owner = mtd->dev.parent->driver->owner;\n"
  },
  {
    "path": "target/linux/pistachio/patches-5.10/901-MIPS-DTS-img-marduk-Add-SPI-NAND-flash.patch",
    "content": "From 0023c706f7e0f0f02bd48a63a2f3c04c839532ae Mon Sep 17 00:00:00 2001\nFrom: Hauke Mehrtens <hauke@hauke-m.de>\nDate: Sat, 15 Aug 2020 16:04:53 +0200\nSubject: [PATCH 901/904] MIPS: DTS: img: marduk: Add SPI NAND flash\n\nAdd Gigadevice GD5F4GQ4UCYIGT SPI NAND flash to the device tree.\n\nThe NAND flash chip is connected with quad SPI, but reading currently\nfails in quad SPI mode.\n\nSigned-off-by: Hauke Mehrtens <hauke@hauke-m.de>\n---\n arch/mips/boot/dts/img/pistachio_marduk.dts | 6 ++++++\n 1 file changed, 6 insertions(+)\n\n--- a/arch/mips/boot/dts/img/pistachio_marduk.dts\n+++ b/arch/mips/boot/dts/img/pistachio_marduk.dts\n@@ -88,6 +88,12 @@\n \t\treg = <0>;\n \t\tspi-max-frequency = <50000000>;\n \t};\n+\n+\tflash@1 {\n+\t\tcompatible = \"spi-nand\";\n+\t\treg = <1>;\n+\t\tspi-max-frequency = <50000000>;\n+\t};\n };\n \n &uart0 {\n"
  },
  {
    "path": "target/linux/pistachio/patches-5.10/902-MIPS-DTS-img-marduk-Add-Cascoda-CA8210-6LoWPAN.patch",
    "content": "From b7700154d75e8d7c9a2022f09c2d5430137606fa Mon Sep 17 00:00:00 2001\nFrom: Hauke Mehrtens <hauke@hauke-m.de>\nDate: Sat, 15 Aug 2020 16:05:25 +0200\nSubject: [PATCH 902/904] MIPS: DTS: img: marduk: Add Cascoda CA8210 6LoWPAN\n\nAdd Cascoda CA8210 6LoWPAN controller to device tree.\n\nSigned-off-by: Hauke Mehrtens <hauke@hauke-m.de>\n---\n arch/mips/boot/dts/img/pistachio_marduk.dts | 22 +++++++++++++++++++++\n 1 file changed, 22 insertions(+)\n\n--- a/arch/mips/boot/dts/img/pistachio_marduk.dts\n+++ b/arch/mips/boot/dts/img/pistachio_marduk.dts\n@@ -75,6 +75,28 @@\n \tVDD-supply = <&internal_dac_supply>;\n };\n \n+&spfi0 {\n+\tstatus = \"okay\";\n+\tpinctrl-0 = <&spim0_pins>, <&spim0_cs0_alt_pin>, <&spim0_cs2_alt_pin>, <&spim0_cs3_alt_pin>, <&spim0_cs4_alt_pin>;\n+\tpinctrl-names = \"default\";\n+\n+\tcs-gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>, <&gpio0 2 GPIO_ACTIVE_HIGH>,\n+\t\t\t<&gpio1 12 GPIO_ACTIVE_HIGH>, <&gpio1 13 GPIO_ACTIVE_HIGH>;\n+\n+\tca8210: ca8210@0 {\n+\t\tstatus = \"okay\";\n+\t\tcompatible = \"cascoda,ca8210\";\n+\t\treg = <0>;\n+\t\tspi-max-frequency = <4000000>;\n+\t\tspi-cpol;\n+\t\treset-gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>;\n+\t\tirq-gpio = <&gpio2 12 GPIO_ACTIVE_HIGH>;\n+\t\textclock-enable;\n+\t\textclock-freq = <16000000>;\n+\t\textclock-gpio = <2>;\n+\t};\n+};\n+\n &spfi1 {\n \tstatus = \"okay\";\n \n"
  },
  {
    "path": "target/linux/pistachio/patches-5.10/903-MIPS-DTS-img-marduk-Add-NXP-SC16IS752IPW.patch",
    "content": "From ad4eba0c36ce8af6ab9ea1bc163e4c1ac7c271c3 Mon Sep 17 00:00:00 2001\nFrom: Hauke Mehrtens <hauke@hauke-m.de>\nDate: Sat, 15 Aug 2020 16:09:02 +0200\nSubject: [PATCH 903/904] MIPS: DTS: img: marduk: Add NXP SC16IS752IPW\n\nAdd NXP SC16IS752IPW SPI-UART controller to device tree.\n\nThis controller drives 2 UARTs and 7 LEDs on the board.\n\nSigned-off-by: Hauke Mehrtens <hauke@hauke-m.de>\n---\n arch/mips/boot/dts/img/pistachio_marduk.dts | 51 +++++++++++++++++++++\n 1 file changed, 51 insertions(+)\n\n--- a/arch/mips/boot/dts/img/pistachio_marduk.dts\n+++ b/arch/mips/boot/dts/img/pistachio_marduk.dts\n@@ -46,6 +46,46 @@\n \t\tregulator-max-microvolt = <1800000>;\n \t};\n \n+\t/* EXT clock from ca8210 is fed to sc16is752 */\n+\tca8210_ext_clk: ca8210-ext-clk {\n+\t\tcompatible = \"fixed-clock\";\n+\t\t#clock-cells = <0>;\n+\t\tclock-frequency = <16000000>;\n+\t\tclock-output-names = \"ca8210_ext_clock\";\n+\t};\n+\n+\tgpioleds {\n+\t\tcompatible = \"gpio-leds\";\n+\t\tuser1 {\n+\t\t\tlabel = \"marduk:red:user1\";\n+\t\t\tgpios = <&sc16is752 0 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\t\tuser2 {\n+\t\t\tlabel = \"marduk:red:user2\";\n+\t\t\tgpios = <&sc16is752 1 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\t\tuser3 {\n+\t\t\tlabel = \"marduk:red:user3\";\n+\t\t\tgpios = <&sc16is752 2 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\t\tuser4 {\n+\t\t\tlabel = \"marduk:red:user4\";\n+\t\t\tgpios = <&sc16is752 3 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\t\tuser5 {\n+\t\t\tlabel = \"marduk:red:user5\";\n+\t\t\tgpios = <&sc16is752 4 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\t\tuser6 {\n+\t\t\tlabel = \"marduk:red:user6\";\n+\t\t\tgpios = <&sc16is752 5 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\t\tuser7 {\n+\t\t\tlabel = \"marduk:red:user7\";\n+\t\t\tgpios = <&sc16is752 6 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\t};\n+\n \tleds {\n \t\tcompatible = \"pwm-leds\";\n \t\theartbeat {\n@@ -95,6 +135,17 @@\n \t\textclock-freq = <16000000>;\n \t\textclock-gpio = <2>;\n \t};\n+\n+\tsc16is752: sc16is752@1 {\n+\t\tcompatible = \"nxp,sc16is752\";\n+\t\treg = <1>;\n+\t\tclocks = <&ca8210_ext_clk>;\n+\t\tspi-max-frequency = <4000000>;\n+\t\tinterrupt-parent = <&gpio0>;\n+\t\tinterrupts = <11 IRQ_TYPE_EDGE_FALLING>;\n+\t\tgpio-controller;\n+\t\t#gpio-cells = <2>;\n+\t};\n };\n \n &spfi1 {\n"
  },
  {
    "path": "target/linux/pistachio/patches-5.10/904-MIPS-DTS-img-marduk-Add-partition-name.patch",
    "content": "From ff0e950b605047bf50d470023e0fb2fc2003a0f0 Mon Sep 17 00:00:00 2001\nFrom: Ian Pozella <Ian.Pozella@imgtec.com>\nDate: Mon, 20 Feb 2017 10:38:07 +0000\nSubject: [PATCH 904/904] MIPS: DTS: img: marduk: Add partition name\n\nSigned-off-by: Ian Pozella <Ian.Pozella@imgtec.com>\n---\n arch/mips/boot/dts/img/pistachio_marduk.dts | 2 ++\n 1 file changed, 2 insertions(+)\n\n--- a/arch/mips/boot/dts/img/pistachio_marduk.dts\n+++ b/arch/mips/boot/dts/img/pistachio_marduk.dts\n@@ -160,12 +160,14 @@\n \t\tcompatible = \"spansion,s25fl016k\", \"jedec,spi-nor\";\n \t\treg = <0>;\n \t\tspi-max-frequency = <50000000>;\n+\t\tlinux,mtd-name = \"spi-nor\";\n \t};\n \n \tflash@1 {\n \t\tcompatible = \"spi-nand\";\n \t\treg = <1>;\n \t\tspi-max-frequency = <50000000>;\n+\t\tlinux,mtd-name = \"spi-nand\";\n \t};\n };\n \n"
  },
  {
    "path": "target/linux/pistachio/patches-5.10/905-MIPS-DTS-img-marduk-Add-led-aliases.patch",
    "content": "--- a/arch/mips/boot/dts/img/pistachio_marduk.dts\n+++ b/arch/mips/boot/dts/img/pistachio_marduk.dts\n@@ -19,6 +19,11 @@\n \t\tethernet0 = &enet;\n \t\tspi0 = &spfi0;\n \t\tspi1 = &spfi1;\n+\n+\t\tled-boot = &led_heartbeat;\n+\t\tled-failsafe = &led_heartbeat;\n+\t\tled-running = &led_heartbeat;\n+\t\tled-upgrade = &led_heartbeat;\n \t};\n \n \tchosen {\n@@ -88,11 +93,10 @@\n \n \tleds {\n \t\tcompatible = \"pwm-leds\";\n-\t\theartbeat {\n+\t\tled_heartbeat: heartbeat {\n \t\t\tlabel = \"marduk:red:heartbeat\";\n \t\t\tpwms = <&pwm 3 300000>;\n \t\t\tmax-brightness = <255>;\n-\t\t\tlinux,default-trigger = \"heartbeat\";\n \t\t};\n \t};\n \n"
  },
  {
    "path": "target/linux/pistachio/profiles/00-default.mk",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2017 OpenWrt.org\n\ndefine Profile/Default\n  NAME:=Default Profile\n  PRIORITY:=1\n  PACKAGES:=\nendef\n\ndefine Profile/Default/Description\n\tDefault package set compatible with most boards.\nendef\n$(eval $(call Profile,Default))\n"
  },
  {
    "path": "target/linux/qoriq/Makefile",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2021 Stijn Tintel <stijn@linux-ipv6.be>\n\ninclude $(TOPDIR)/rules.mk\n\nARCH:=powerpc64\nBOARD:=qoriq\nBOARDNAME:=NXP QorIQ (PowerPC)\nCPU_TYPE:=e5500\nFEATURES:=boot-part ext4 fpu legacy-sdcard powerpc64 ramdisk root-part rtc source-only\nSUBTARGETS:=generic\n\nKERNEL_PATCHVER:=5.10\n\nKERNELNAME:=zImage\n\ninclude $(INCLUDE_DIR)/target.mk\n\nDEFAULT_PACKAGES += e2fsprogs mkf2fs uboot-envtools\n\n$(eval $(call BuildTarget))\n"
  },
  {
    "path": "target/linux/qoriq/base-files/etc/board.d/02_network",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n. /lib/functions/uci-defaults.sh\n. /lib/functions.sh\n. /lib/functions/system.sh\n\nboard_config_update\nboard=$(board_name)\n\nwg_set_opt_interface() {\n\tlocal device=\"$1\"\n\tlocal offset=\"$2\"\n\n\tucidef_set_interface \"$device\" device \"$device\" protocol static ipaddr \"10.0.${offset}.1\" netmask 255.255.255.0\n}\n\ncase \"$board\" in\nwatchguard,firebox-m300)\n\tucidef_set_interfaces_lan_wan \"eth1\" \"eth0\"\n\twg_set_opt_interface \"eth2\" \"2\"\n\n\tsweth_mac_offset=0x186d\n\n\tfor sweth in /sys/class/net/sweth*; do\n\t\tdevice=\"$(basename \"$sweth\")\"\n\t\tmac=\"$(mtd_get_mac_text wg_cfg0 \"$sweth_mac_offset\")\"\n\t\tswitchports=\"$switchports $device\"\n\t\tucidef_set_network_device_mac \"$device\" \"$mac\"\n\t\twg_set_opt_interface \"$device\" \"${device#sweth}\"\n\t\tsweth_mac_offset=$(printf \"0x%X\\n\" $(( $sweth_mac_offset + 0x14)))\n\tdone\n\n\t;;\nesac\n\nboard_config_flush\n\nexit 0\n"
  },
  {
    "path": "target/linux/qoriq/base-files/lib/preinit/79_move_config",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\n. /lib/functions.sh\n. /lib/upgrade/common.sh\n\nmove_config() {\n\tlocal partdev\n\n\tif export_bootdevice && export_partdevice partdev 1; then\n\t\tmkdir -p /boot\n\t\tmount -o rw,noatime \"/dev/$partdev\" /boot\n\t\t[ -f \"/boot/$BACKUP_FILE\" ] && mv -f \"/boot/$BACKUP_FILE\" /\n\t\tumount /boot\n\tfi\n}\n\nboot_hook_add preinit_mount_root move_config\n"
  },
  {
    "path": "target/linux/qoriq/base-files/lib/upgrade/platform.sh",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\nPART_NAME=firmware\nREQUIRE_IMAGE_METADATA=1\n\nplatform_check_image() {\n\tcase \"$(board_name)\" in\n\twatchguard,firebox-m300)\n\t\tlegacy_sdcard_check_image \"$1\"\n\t\t;;\n\t*)\n\t\treturn 0\n\t\t;;\n\tesac\n}\n\nplatform_copy_config() {\n\tcase \"$(board_name)\" in\n\twatchguard,firebox-m300)\n\t\tlegacy_sdcard_copy_config \"$1\"\n\t\t;;\n\t*)\n\t\treturn 0\n\tesac\n}\n\nplatform_do_upgrade() {\n\tcase \"$(board_name)\" in\n\twatchguard,firebox-m300)\n\t\tlegacy_sdcard_do_upgrade \"$1\"\n\t\t;;\n\t*)\n\t\tdefault_do_upgrade \"$1\"\n\t\t;;\n\tesac\n}\n"
  },
  {
    "path": "target/linux/qoriq/config-5.10",
    "content": "CONFIG_64BIT=y\nCONFIG_ALTIVEC=y\nCONFIG_ARCH_DMA_ADDR_T_64BIT=y\nCONFIG_ARCH_HIBERNATION_POSSIBLE=y\nCONFIG_ARCH_KEEP_MEMBLOCK=y\nCONFIG_ARCH_MAY_HAVE_PC_FDC=y\nCONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y\nCONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y\nCONFIG_ARCH_MMAP_RND_BITS=18\nCONFIG_ARCH_MMAP_RND_BITS_MAX=32\nCONFIG_ARCH_MMAP_RND_BITS_MIN=18\nCONFIG_ARCH_MMAP_RND_COMPAT_BITS=11\nCONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=17\nCONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11\nCONFIG_ARCH_SELECT_MEMORY_MODEL=y\nCONFIG_ARCH_SPARSEMEM_ENABLE=y\nCONFIG_ARCH_WEAK_RELEASE_ACQUIRE=y\nCONFIG_ASN1=y\nCONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH=y\nCONFIG_AUDIT_ARCH=y\nCONFIG_BLK_DEV_LOOP=y\nCONFIG_BLK_DEV_SD=y\nCONFIG_BLK_MQ_PCI=y\nCONFIG_BLK_PM=y\nCONFIG_BLK_SCSI_REQUEST=y\nCONFIG_BLOCK_COMPAT=y\nCONFIG_BOOKE=y\nCONFIG_CLKDEV_LOOKUP=y\nCONFIG_CLK_QORIQ=y\nCONFIG_CLONE_BACKWARDS=y\nCONFIG_CLZ_TAB=y\nCONFIG_COMMON_CLK=y\nCONFIG_COMPAT=y\n# CONFIG_COMPAT_32BIT_TIME is not set\nCONFIG_COMPAT_BINFMT_ELF=y\nCONFIG_COMPAT_NETLINK_MESSAGES=y\nCONFIG_COMPAT_OLD_SIGACTION=y\nCONFIG_CONSOLE_TRANSLATIONS=y\nCONFIG_CORENET_GENERIC=y\n# CONFIG_CPUFREQ_DT is not set\nCONFIG_CPU_BIG_ENDIAN=y\nCONFIG_CPU_FREQ=y\n# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set\nCONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y\nCONFIG_CPU_FREQ_GOV_ATTR_SET=y\nCONFIG_CPU_FREQ_GOV_COMMON=y\nCONFIG_CPU_FREQ_GOV_CONSERVATIVE=y\nCONFIG_CPU_FREQ_GOV_ONDEMAND=y\nCONFIG_CPU_FREQ_GOV_PERFORMANCE=y\nCONFIG_CPU_FREQ_GOV_POWERSAVE=y\nCONFIG_CPU_FREQ_GOV_SCHEDUTIL=y\nCONFIG_CPU_FREQ_GOV_USERSPACE=y\n# CONFIG_CPU_FREQ_STAT is not set\nCONFIG_CPU_IDLE=y\nCONFIG_CPU_IDLE_GOV_TEO=y\nCONFIG_CPU_ISOLATION=y\nCONFIG_CPU_RMAP=y\nCONFIG_CRC16=y\nCONFIG_CRYPTO_AUTHENC=y\nCONFIG_CRYPTO_CRC32=y\nCONFIG_CRYPTO_CRC32C=y\n# CONFIG_CRYPTO_CRC32C_VPMSUM is not set\nCONFIG_CRYPTO_DES=y\nCONFIG_CRYPTO_DEV_FSL_CAAM=y\nCONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API=y\nCONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API_DESC=y\nCONFIG_CRYPTO_DEV_FSL_CAAM_COMMON=y\nCONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API=y\nCONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API_DESC=y\nCONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API_QI=y\n# CONFIG_CRYPTO_DEV_FSL_CAAM_DEBUG is not set\n# CONFIG_CRYPTO_DEV_FSL_CAAM_INTC is not set\nCONFIG_CRYPTO_DEV_FSL_CAAM_JR=y\nCONFIG_CRYPTO_DEV_FSL_CAAM_PKC_API=y\nCONFIG_CRYPTO_DEV_FSL_CAAM_RINGSIZE=9\nCONFIG_CRYPTO_DEV_FSL_CAAM_RNG_API=y\n# CONFIG_CRYPTO_DEV_NX is not set\nCONFIG_CRYPTO_ECB=y\nCONFIG_CRYPTO_ENGINE=y\nCONFIG_CRYPTO_HW=y\nCONFIG_CRYPTO_LIB_DES=y\nCONFIG_CRYPTO_LIB_POLY1305_RSIZE=1\n# CONFIG_CRYPTO_MD5_PPC is not set\nCONFIG_CRYPTO_RNG=y\nCONFIG_CRYPTO_RNG2=y\nCONFIG_CRYPTO_RSA=y\n# CONFIG_CRYPTO_SHA1_PPC is not set\nCONFIG_CRYPTO_XTS=y\nCONFIG_DATA_SHIFT=12\nCONFIG_DEBUG_INFO=y\nCONFIG_DEBUG_INFO_DWARF4=y\nCONFIG_DEFAULT_UIMAGE=y\nCONFIG_DMADEVICES=y\nCONFIG_DMA_ENGINE=y\nCONFIG_DMA_OF=y\nCONFIG_DMA_OPS=y\nCONFIG_DMA_OPS_BYPASS=y\nCONFIG_DTC=y\nCONFIG_DUMMY_CONSOLE=y\nCONFIG_DYNAMIC_DEBUG=y\nCONFIG_E500=y\n# CONFIG_E5500_CPU is not set\nCONFIG_E6500_CPU=y\nCONFIG_EARLY_PRINTK=y\nCONFIG_EDAC=y\nCONFIG_EDAC_ATOMIC_SCRUB=y\n# CONFIG_EDAC_CPC925 is not set\n# CONFIG_EDAC_DEBUG is not set\nCONFIG_EDAC_LEGACY_SYSFS=y\nCONFIG_EDAC_MPC85XX=y\nCONFIG_EDAC_SUPPORT=y\nCONFIG_EPAPR_PARAVIRT=y\nCONFIG_EXT4_FS=y\nCONFIG_EXT4_FS_POSIX_ACL=y\nCONFIG_F2FS_FS=y\nCONFIG_FIXED_PHY=y\nCONFIG_FORCE_MAX_ZONEORDER=13\n# CONFIG_FSL_BMAN_TEST is not set\nCONFIG_FSL_CORENET_CF=y\nCONFIG_FSL_CORENET_RCPM=y\nCONFIG_FSL_DMA=y\nCONFIG_FSL_DPAA=y\n# CONFIG_FSL_DPAA_CHECKING is not set\nCONFIG_FSL_DPAA_ETH=y\nCONFIG_FSL_EMB_PERFMON=y\nCONFIG_FSL_FMAN=y\nCONFIG_FSL_GUTS=y\nCONFIG_FSL_IFC=y\nCONFIG_FSL_LBC=y\nCONFIG_FSL_MPIC_TIMER_WAKEUP=y\nCONFIG_FSL_PAMU=y\nCONFIG_FSL_PCI=y\n# CONFIG_FSL_QMAN_TEST is not set\nCONFIG_FSL_SOC=y\nCONFIG_FSL_SOC_BOOKE=y\nCONFIG_FSL_XGMAC_MDIO=y\nCONFIG_FS_IOMAP=y\nCONFIG_FS_MBCACHE=y\nCONFIG_FS_POSIX_ACL=y\nCONFIG_FTL=y\nCONFIG_FUNCTION_ERROR_INJECTION=y\nCONFIG_FW_LOADER_PAGED_BUF=y\nCONFIG_GENERIC_ALLOCATOR=y\nCONFIG_GENERIC_BUG=y\nCONFIG_GENERIC_CLOCKEVENTS=y\nCONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y\nCONFIG_GENERIC_CMOS_UPDATE=y\n# CONFIG_GENERIC_CPU is not set\nCONFIG_GENERIC_CPU_AUTOPROBE=y\nCONFIG_GENERIC_CPU_VULNERABILITIES=y\nCONFIG_GENERIC_EARLY_IOREMAP=y\nCONFIG_GENERIC_IRQ_MIGRATION=y\nCONFIG_GENERIC_IRQ_SHOW=y\nCONFIG_GENERIC_IRQ_SHOW_LEVEL=y\nCONFIG_GENERIC_ISA_DMA=y\nCONFIG_GENERIC_MSI_IRQ=y\nCONFIG_GENERIC_MSI_IRQ_DOMAIN=y\nCONFIG_GENERIC_PCI_IOMAP=y\nCONFIG_GENERIC_PHY=y\nCONFIG_GENERIC_SMP_IDLE_THREAD=y\nCONFIG_GENERIC_STRNCPY_FROM_USER=y\nCONFIG_GENERIC_STRNLEN_USER=y\nCONFIG_GENERIC_TIME_VSYSCALL=y\n# CONFIG_GEN_RTC is not set\n# CONFIG_GIANFAR is not set\nCONFIG_GLOB=y\nCONFIG_GPIOLIB=y\nCONFIG_GPIO_GENERIC=y\nCONFIG_GPIO_MPC8XXX=y\nCONFIG_GRO_CELLS=y\n# CONFIG_HANGCHECK_TIMER is not set\n# CONFIG_HARDENED_USERCOPY is not set\nCONFIG_HAS_DMA=y\nCONFIG_HAS_IOMEM=y\nCONFIG_HAS_IOPORT_MAP=y\nCONFIG_HWMON=y\nCONFIG_HW_CONSOLE=y\nCONFIG_HW_RANDOM=y\nCONFIG_I2C=y\nCONFIG_I2C_BOARDINFO=y\nCONFIG_I2C_MPC=y\nCONFIG_ILLEGAL_POINTER_VALUE=0x5deadbeef0000000\nCONFIG_INITRAMFS_SOURCE=\"\"\nCONFIG_INPUT=y\nCONFIG_IOMMU_API=y\n# CONFIG_IOMMU_DEBUGFS is not set\n# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set\nCONFIG_IOMMU_HELPER=y\nCONFIG_IOMMU_SUPPORT=y\nCONFIG_IRQCHIP=y\nCONFIG_IRQ_DOMAIN=y\nCONFIG_IRQ_DOMAIN_HIERARCHY=y\nCONFIG_IRQ_FORCED_THREADING=y\nCONFIG_IRQ_WORK=y\nCONFIG_ISA_DMA_API=y\nCONFIG_JBD2=y\nCONFIG_JUMP_LABEL=y\nCONFIG_JUMP_LABEL_FEATURE_CHECKS=y\n# CONFIG_JUMP_LABEL_FEATURE_CHECK_DEBUG is not set\nCONFIG_KALLSYMS=y\nCONFIG_KERNEL_GZIP=y\nCONFIG_KERNEL_START=0xc000000000000000\nCONFIG_KPROBES=y\nCONFIG_KRETPROBES=y\n# CONFIG_LD_HEAD_STUB_CATCH is not set\nCONFIG_LIBFDT=y\nCONFIG_LOCK_DEBUGGING_SUPPORT=y\nCONFIG_LOCK_SPIN_ON_OWNER=y\nCONFIG_MAGIC_SYSRQ=y\nCONFIG_MARVELL_PHY=y\nCONFIG_MATH_EMULATION=y\n# CONFIG_MATH_EMULATION_FULL is not set\nCONFIG_MATH_EMULATION_HW_UNIMPLEMENTED=y\nCONFIG_MDIO_BUS=y\nCONFIG_MDIO_DEVICE=y\nCONFIG_MDIO_DEVRES=y\nCONFIG_MEMFD_CREATE=y\nCONFIG_MEMORY=y\nCONFIG_MIGRATION=y\nCONFIG_MMC=y\nCONFIG_MMC_BLOCK=y\nCONFIG_MMC_DEBUG=y\nCONFIG_MMC_SDHCI=y\nCONFIG_MMC_SDHCI_IO_ACCESSORS=y\nCONFIG_MMC_SDHCI_OF_ESDHC=y\n# CONFIG_MMC_SDHCI_PCI is not set\nCONFIG_MMC_SDHCI_PLTFM=y\n# CONFIG_MMC_WBSD is not set\nCONFIG_MMIOWB=y\nCONFIG_MMU_GATHER_PAGE_SIZE=y\nCONFIG_MODULES_USE_ELF_RELA=y\nCONFIG_MPIC=y\nCONFIG_MPIC_MSGR=y\nCONFIG_MPIC_TIMER=y\nCONFIG_MPILIB=y\nCONFIG_MTD_NAND_CORE=y\nCONFIG_MTD_NAND_ECC=y\nCONFIG_MTD_NAND_ECC_SW_HAMMING=y\nCONFIG_MTD_NAND_FSL_IFC=y\nCONFIG_MTD_PHYSMAP=y\nCONFIG_MTD_RAW_NAND=y\nCONFIG_MUTEX_SPIN_ON_OWNER=y\nCONFIG_NEED_DMA_MAP_STATE=y\nCONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK=y\nCONFIG_NEED_PER_CPU_PAGE_FIRST_CHUNK=y\nCONFIG_NEED_SG_DMA_LENGTH=y\nCONFIG_NET_DEVLINK=y\nCONFIG_NET_DSA=y\nCONFIG_NET_DSA_MV88E6XXX=y\nCONFIG_NET_DSA_MV88E6XXX_GLOBAL2=y\nCONFIG_NET_DSA_TAG_DSA=y\nCONFIG_NET_DSA_TAG_EDSA=y\nCONFIG_NET_DSA_TAG_OCELOT=y\nCONFIG_NET_DSA_TAG_TRAILER=y\nCONFIG_NET_FLOW_LIMIT=y\nCONFIG_NET_SWITCHDEV=y\nCONFIG_NLS=y\nCONFIG_NO_HZ_COMMON=y\nCONFIG_NO_HZ_IDLE=y\nCONFIG_NR_CPUS=24\nCONFIG_NR_IRQS=512\nCONFIG_OF=y\nCONFIG_OF_ADDRESS=y\nCONFIG_OF_DMA_DEFAULT_COHERENT=y\nCONFIG_OF_EARLY_FLATTREE=y\nCONFIG_OF_FLATTREE=y\nCONFIG_OF_GPIO=y\nCONFIG_OF_IOMMU=y\nCONFIG_OF_IRQ=y\nCONFIG_OF_KOBJ=y\nCONFIG_OF_MDIO=y\nCONFIG_OF_NET=y\nCONFIG_OLD_SIGSUSPEND=y\nCONFIG_OPTPROBES=y\nCONFIG_PACKING=y\nCONFIG_PADATA=y\nCONFIG_PAGE_OFFSET=0xc000000000000000\nCONFIG_PCI=y\nCONFIG_PCI_DOMAINS=y\nCONFIG_PCI_MSI=y\nCONFIG_PCI_MSI_ARCH_FALLBACKS=y\nCONFIG_PCI_MSI_IRQ_DOMAIN=y\nCONFIG_PGTABLE_LEVELS=4\nCONFIG_PHYLIB=y\nCONFIG_PHYLINK=y\nCONFIG_PHYSICAL_START=0x00000000\nCONFIG_PHYS_64BIT=y\nCONFIG_PHYS_ADDR_T_64BIT=y\nCONFIG_PM=y\n# CONFIG_PMU_SYSFS is not set\nCONFIG_PM_CLK=y\nCONFIG_PPC=y\nCONFIG_PPC64=y\nCONFIG_PPC_ADV_DEBUG_DACS=2\nCONFIG_PPC_ADV_DEBUG_DVCS=0\nCONFIG_PPC_ADV_DEBUG_IACS=2\nCONFIG_PPC_ADV_DEBUG_REGS=y\nCONFIG_PPC_BARRIER_NOSPEC=y\nCONFIG_PPC_BOOK3E=y\nCONFIG_PPC_BOOK3E_64=y\nCONFIG_PPC_BOOK3E_MMU=y\n# CONFIG_PPC_BOOK3S_64 is not set\nCONFIG_PPC_DAWR=y\nCONFIG_PPC_DOORBELL=y\nCONFIG_PPC_E500MC=y\n# CONFIG_PPC_EARLY_DEBUG is not set\nCONFIG_PPC_EPAPR_HV_PIC=y\nCONFIG_PPC_FPU=y\nCONFIG_PPC_FSL_BOOK3E=y\nCONFIG_PPC_INDIRECT_PCI=y\n# CONFIG_PPC_IRQ_SOFT_MASK_DEBUG is not set\nCONFIG_PPC_MMU_NOHASH=y\nCONFIG_PPC_MSI_BITMAP=y\nCONFIG_PPC_OF_BOOT_TRAMPOLINE=y\nCONFIG_PPC_PAGE_SHIFT=12\n# CONFIG_PPC_PTDUMP is not set\n# CONFIG_PPC_QEMU_E500 is not set\nCONFIG_PPC_QUEUED_SPINLOCKS=y\nCONFIG_PPC_SMP_MUXED_IPI=y\nCONFIG_PPC_UDBG_16550=y\nCONFIG_PPC_WERROR=y\nCONFIG_PPS=y\nCONFIG_PTE_64BIT=y\nCONFIG_QORIQ_CPUFREQ=y\nCONFIG_QORIQ_THERMAL=y\nCONFIG_QUEUED_RWLOCKS=y\nCONFIG_QUEUED_SPINLOCKS=y\nCONFIG_RAS=y\nCONFIG_RATIONAL=y\n# CONFIG_RAVE_SP_CORE is not set\nCONFIG_REGMAP=y\nCONFIG_REGMAP_MMIO=y\nCONFIG_RFS_ACCEL=y\nCONFIG_RPS=y\nCONFIG_RWSEM_SPIN_ON_OWNER=y\n# CONFIG_SCOM_DEBUGFS is not set\nCONFIG_SCSI=y\nCONFIG_SERIAL_8250_EXTENDED=y\nCONFIG_SERIAL_8250_FSL=y\nCONFIG_SERIAL_8250_NR_UARTS=4\nCONFIG_SERIAL_8250_RUNTIME_UARTS=4\nCONFIG_SERIAL_8250_SHARE_IRQ=y\nCONFIG_SERIAL_DEV_BUS=y\nCONFIG_SERIAL_DEV_CTRL_TTYPORT=y\nCONFIG_SERIAL_FSL_LINFLEXUART=y\nCONFIG_SERIAL_FSL_LINFLEXUART_CONSOLE=y\nCONFIG_SERIAL_FSL_LPUART=y\nCONFIG_SERIAL_FSL_LPUART_CONSOLE=y\nCONFIG_SERIAL_MCTRL_GPIO=y\nCONFIG_SG_POOL=y\nCONFIG_SLUB_DEBUG=y\nCONFIG_SMP=y\nCONFIG_SOC_BUS=y\nCONFIG_SPARSEMEM_VMEMMAP_ENABLE=y\nCONFIG_SPARSE_IRQ=y\nCONFIG_SPI=y\nCONFIG_SPI_FSL_ESPI=y\nCONFIG_SPI_MASTER=y\nCONFIG_SRCU=y\nCONFIG_SWIOTLB=y\nCONFIG_SWPHY=y\nCONFIG_SYSCTL_EXCEPTION_TRACE=y\nCONFIG_SYSVIPC_COMPAT=y\nCONFIG_SYS_SUPPORTS_HUGETLBFS=y\nCONFIG_TARGET_CPU_BOOL=y\nCONFIG_THERMAL=y\nCONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y\nCONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0\nCONFIG_THERMAL_GOV_STEP_WISE=y\nCONFIG_THERMAL_OF=y\nCONFIG_THREAD_INFO_IN_TASK=y\nCONFIG_THREAD_SHIFT=14\nCONFIG_TREE_RCU=y\nCONFIG_TREE_SRCU=y\n# CONFIG_UACCE is not set\n# CONFIG_UCLAMP_TASK is not set\nCONFIG_USB=y\nCONFIG_USB_COMMON=y\nCONFIG_USB_EHCI_FSL=y\nCONFIG_USB_EHCI_HCD=y\n# CONFIG_USB_EHCI_HCD_PLATFORM is not set\nCONFIG_USB_STORAGE=y\nCONFIG_USB_SUPPORT=y\nCONFIG_USB_UAS=y\nCONFIG_VDSO32=y\nCONFIG_VGA_CONSOLE=y\nCONFIG_VIRT_CPU_ACCOUNTING=y\nCONFIG_VIRT_CPU_ACCOUNTING_NATIVE=y\nCONFIG_VT=y\nCONFIG_VT_CONSOLE=y\n# CONFIG_VT_HW_CONSOLE_BINDING is not set\n# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set\nCONFIG_XPS=y\nCONFIG_ZLIB_DEFLATE=y\n"
  },
  {
    "path": "target/linux/qoriq/files/arch/powerpc/boot/dts/fsl/watchguard-firebox-m300.dts",
    "content": "// SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-or-later\n/*\n * WatchGuard Firebox M300 Device Tree Source\n * Based on t2081qds.dts from Linux 5.10\n *\n * Copyright 2013 - 2015 Freescale Semiconductor Inc.\n * Copyright 2020 - 2021 Stijn Tintel <stijn@linux-ipv6.be>\n */\n\n/include/ \"t208xsi-pre.dtsi\"\n/include/ \"t208xqds.dtsi\"\n\n/ {\n\tmodel = \"WatchGuard Firebox M300\";\n\tcompatible = \"watchguard,firebox-m300\", \"fsl,T2081QDS\";\n\n\tinterrupt-parent = <&mpic>;\n\n\taliases {\n\t\t/delete-property/ ethernet0;\n\t\t/delete-property/ ethernet1;\n\t\t/delete-property/ ethernet2;\n\t\t/delete-property/ ethernet3;\n\t\t/delete-property/ ethernet4;\n\t\t/delete-property/ ethernet5;\n\t\t/delete-property/ ethernet6;\n\t\t/delete-property/ ethernet7;\n\n\t\tethernet0 = &enet7;\n\t\tethernet1 = &enet0;\n\t\tethernet2 = &enet1;\n\t\tethernet3 = &enet2;\n\t\tethernet4 = &enet3;\n\t};\n};\n\n&soc {\n// Include first to make this the first interface\n/include/ \"qoriq-fman3-0-10g-1.dtsi\"\n};\n\n// mdio-mux under &boardctrl + its aliases removed. causes crash:\n// Oops: Machine check, sig: 7 [#1]\n\n/include/ \"t2081si-post.dtsi\"\n\n// add stuff below the include to make sure we override whatever is there\n\n&enet0 {\n\tphy-connection-type = \"sgmii\";\n\tphy-handle = <&phy1>;\n};\n\n&enet1 {\n\tphy-connection-type = \"sgmii\";\n\tphy-handle = <&phy2>;\n};\n\n&enet2 {\n\tphy-connection-type = \"rgmii\";\n\n\tfixed-link {\n\t\tspeed = <1000>;\n\t\tfull-duplex;\n\t};\n};\n\n&enet3 {\n\tphy-connection-type = \"rgmii\";\n\n\tfixed-link {\n\t\tspeed = <1000>;\n\t\tfull-duplex;\n\t};\n};\n\n&enet4 {\n\tstatus = \"disabled\";\n};\n\n&enet5 {\n\tstatus = \"disabled\";\n};\n\n&enet6 {\n\tstatus = \"disabled\";\n};\n\n&enet7 {\n\tphy-connection-type = \"sgmii\";\n\tphy-handle = <&phy0>;\n};\n\n&ifc {\n\tranges = <0x00 0x00 0x0f 0xefc00000 0x400000>;\n\n\tnor@0,0 {\n\t\treg = <0x00 0x00 0x400000>;\n\n\t\tpartition@0{\n\t\t\treg = <0x0 0x10000>;\n\t\t\tlabel = \"qoriq-rcw\";\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@10000 {\n\t\t\treg = <0x10000 0x20000>;\n\t\t\tlabel = \"wg_cfg0\";\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@30000 {\n\t\t\treg = <0x30000 0x10000>;\n\t\t\tlabel = \"wg_cfg1\";\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@40000 {\n\t\t\treg = <0x40000 0x10000>;\n\t\t\tlabel = \"wg_mfg_data\";\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@50000 {\n\t\t\treg = <0x50000 0xb0000>;\n\t\t\tlabel = \"wg_bootopt_data_and_reserved\";\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@100000 {\n\t\t\treg = <0x100000 0xb0000>;\n\t\t\tlabel = \"wg_extra_reserved_1\";\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@1B0000 {\n\t\t\treg = <0x1b0000 0xb0000>;\n\t\t\tlabel = \"wg_extra_reserved_2\";\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@260000 {\n\t\t\treg = <0x260000 0xc0000>;\n\t\t\tlabel = \"wg_u-boot_failsafe\";\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@320000 {\n\t\t\treg = <0x320000 0x10000>;\n\t\t\tlabel = \"qoriq-fman\";\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@330000 {\n\t\t\treg = <0x330000 0x10000>;\n\t\t\tlabel = \"u-boot-env\";\n\t\t};\n\n\t\tpartition@340000 {\n\t\t\treg = <0x340000 0xc0000>;\n\t\t\tlabel = \"u-boot\";\n\t\t\tread-only;\n\t\t};\n\t};\n\n\tnand@2,0 {\n\t\tstatus = \"disabled\";\n\t};\n};\n\n&mdio0 {\n\t// m300 ethernet port 0\n\tphy0: ethernet-phy@0 {\n\t\treg = <0x00>;\n\t};\n\n\t// m300 ethernet port 1\n\tphy1: ethernet-phy@1 {\n\t\treg = <0x01>;\n\t};\n\n\tphy2: ethernet-phy@2 {\n\t\treg = <0x02>;\n\t};\n\n\tphy3: ethernet-phy@3 {\n\t\treg = <0x03>;\n\t};\n\n\tswitch0: switch@10 {\n\t\tcompatible = \"marvell,mv88e6085\";\n\t\treg = <0x10>;\n\n\t\tmdio {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\n\t\t\tswitch0phy0: switch0phy0@0 {\n\t\t\t\treg = <0x00>;\n\t\t\t\tinterrupt-parent = <&switch0>;\n\t\t\t};\n\n\t\t\tswitch0phy1: switch0phy1@1 {\n\t\t\t\treg = <0x01>;\n\t\t\t\tinterrupt-parent = <&switch0>;\n\t\t\t};\n\n\t\t\tswitch0phy2: switch0phy2@2 {\n\t\t\t\treg = <0x02>;\n\t\t\t\tinterrupt-parent = <&switch0>;\n\t\t\t};\n\n\t\t\tswitch0phy3: switch0phy3@3 {\n\t\t\t\treg = <0x03>;\n\t\t\t\tinterrupt-parent = <&switch0>;\n\t\t\t};\n\n\t\t\tswitch0phy4: switch0phy4@4 {\n\t\t\t\treg = <0x04>;\n\t\t\t\tinterrupt-parent = <&switch0>;\n\t\t\t};\n\t\t};\n\n\t\tports {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\n\t\t\tport@0 {\n\t\t\t\treg = <0>;\n\t\t\t\tlabel = \"sweth3\";\n\t\t\t\tphy-handle = <&switch0phy0>;\n\t\t\t};\n\n\t\t\tport@1 {\n\t\t\t\treg = <1>;\n\t\t\t\tlabel = \"sweth4\";\n\t\t\t\tphy-handle = <&switch0phy1>;\n\t\t\t};\n\n\t\t\tport@2 {\n\t\t\t\treg = <2>;\n\t\t\t\tlabel = \"sweth5\";\n\t\t\t\tphy-handle = <&switch0phy2>;\n\t\t\t};\n\n\t\t\tport@3 {\n\t\t\t\treg = <3>;\n\t\t\t\tlabel = \"sweth6\";\n\t\t\t\tphy-handle = <&switch0phy3>;\n\t\t\t};\n\n\t\t\tport@4 {\n\t\t\t\treg = <4>;\n\t\t\t\tlabel = \"sweth7\";\n\t\t\t\tphy-handle = <&switch0phy4>;\n\t\t\t};\n\n\t\t\t// OEM bootlog suggests multiple ports are attached to switch\n\t\t\t// Keep this until OEM supplies GPL sources\n\t\t\tport@5 {\n\t\t\t\tstatus = \"disabled\";\n\n\t\t\t\treg = \"<5>\";\n\t\t\t\tlabel = \"cpu\";\n\t\t\t\tethernet = <&enet2>;\n\t\t\t\tphy-mode = \"rgmii-id\";\n\n\t\t\t\tfixed-link {\n\t\t\t\t\tspeed = <1000>;\n\t\t\t\t\tfull-duplex;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tport@6 {\n\t\t\t\treg = <6>;\n\t\t\t\tlabel = \"cpu\";\n\t\t\t\tethernet = <&enet3>;\n\t\t\t\tphy-mode = \"rgmii-id\";\n\n\t\t\t\tfixed-link {\n\t\t\t\t\tspeed = <1000>;\n\t\t\t\t\tfull-duplex;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t};\n};\n\n&soc {\n\ti2c@118000 {\n\t\ttpm@29 {\n\t\t\tcompatible = \"tpm,tpm_i2c_atmel\";\n\t\t\treg = <0x29>;\n\t\t};\n\t\thwmon@2c {\n\t\t\tcompatible = \"winbond,w83793\";\n\t\t\treg = <0x2c>;\n\t\t};\n\t\thwmon@2d {\n\t\t\tcompatible = \"winbond,w83793\";\n\t\t\treg = <0x2d>;\n\t\t};\n\t\trtc@32 {\n\t\t\tcompatible = \"ricoh,rs5c372a\";\n\t\t\treg = <0x32>;\n\t\t};\n\t\tpca9547@77 {\n\t\t\tstatus = \"disabled\";\n\t\t};\n\t};\n\n\tspi@110000 {\n\t\t// DTS decompiled from OEM DTB contains flash@0 but doesn't work\n\t\t// spi-nor spi0.0: unrecognized JEDEC id bytes: ff ff ff ff ff ff\n\t\t// disable for now\n\t\tflash@0 {\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tflash@1 {\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tflash@2 {\n\t\t\tstatus = \"disabled\";\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/qoriq/generic/target.mk",
    "content": "define Target/Description\n        Build firmware images for NXP QorIQ boards in the\n        T-Series(T1-T5) aka AMP Series platforms.\n        Features the e5500 and e6500 64-bit Power Architecture cores.\nendef\n"
  },
  {
    "path": "target/linux/qoriq/image/Makefile",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n\ninclude $(TOPDIR)/rules.mk\ninclude $(INCLUDE_DIR)/image.mk\n\nSQUASHFSCOMP := xz $(LZMA_XZ_OPTIONS)\n\ndefine Build/sdcard-img\n        rm -fR $@.boot\n        mkdir -p $@.boot\n        $(CP) $(KDIR)/$(DEVICE_NAME)-kernel.bin $@.boot\n        $(if $(DEVICE_DTS),\\\n                $(foreach dtb,$(DEVICE_DTS),$(CP) $(KDIR)/image-$(dtb).dtb $@.boot), \\\n                $(CP) $(KDIR)/image-/*.dtb $@.boot)\n\n        $(SCRIPT_DIR)/gen_image_generic.sh \\\n                $@ \\\n                $(CONFIG_TARGET_KERNEL_PARTSIZE) $@.boot \\\n                $(CONFIG_TARGET_ROOTFS_PARTSIZE) $(IMAGE_ROOTFS) \\\n                2048\n\n        $(if $(UBOOT),dd if=$(STAGING_DIR_IMAGE)/$(UBOOT).img of=$@ bs=512 skip=1 seek=1 conv=notrunc)\nendef\n\ndefine Device/Default\n  PROFILES := Default\n  DEVICE_DTS := $(subst _,-,$(1))\n  KERNEL_DEPENDS = $$(wildcard $(DTS_DIR)/$$(DEVICE_DTS).dts)\n  KERNEL_ENTRY := 0x00000000\n  KERNEL_LOADADDR := 0x00000000\n  KERNEL := kernel-bin\nendef\n\ninclude $(SUBTARGET).mk\n\n$(eval $(call BuildImage))\n"
  },
  {
    "path": "target/linux/qoriq/image/generic.mk",
    "content": "define Device/watchguard_firebox-m300\n  DEVICE_VENDOR := WatchGuard\n  DEVICE_MODEL := Firebox M300\n  DEVICE_DTS_DIR := $(DTS_DIR)/fsl\n  DEVICE_PACKAGES := \\\n\tkmod-hwmon-w83793 kmod-ptp-qoriq kmod-rtc-rs5c372a kmod-tpm-i2c-atmel\n  KERNEL := kernel-bin | gzip | uImage gzip\n  IMAGES := sdcard.img.gz sysupgrade.img.gz\n  IMAGE/sysupgrade.img.gz :=  sdcard-img | gzip | append-metadata\n  IMAGE/sdcard.img.gz := sdcard-img | gzip\nendef\nTARGET_DEVICES += watchguard_firebox-m300\n"
  },
  {
    "path": "target/linux/ramips/Makefile",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2008-2011 OpenWrt.org\n\ninclude $(TOPDIR)/rules.mk\n\nARCH:=mipsel\nBOARD:=ramips\nBOARDNAME:=MediaTek Ralink MIPS\nSUBTARGETS:=mt7620 mt7621 mt76x8 rt288x rt305x rt3883\nFEATURES:=squashfs gpio\n\nKERNEL_PATCHVER:=5.10\nKERNEL_TESTING_PATCHVER:=5.15\n\ndefine Target/Description\n\tBuild firmware images for Ralink RT288x/RT3xxx based boards.\nendef\n\ninclude $(INCLUDE_DIR)/target.mk\nDEFAULT_PACKAGES += kmod-leds-gpio kmod-gpio-button-hotplug\n\n$(eval $(call BuildTarget))\n"
  },
  {
    "path": "target/linux/ramips/base-files/etc/hotplug.d/usb/10-motion",
    "content": "[ \"$ACTION\" = \"motion\" ] && logger webcam motion event\n"
  },
  {
    "path": "target/linux/ramips/base-files/etc/inittab",
    "content": "::sysinit:/etc/init.d/rcS S boot\n::shutdown:/etc/init.d/rcS K shutdown\n::askconsole:/usr/libexec/login.sh\n"
  },
  {
    "path": "target/linux/ramips/base-files/etc/uci-defaults/04_led_migration",
    "content": ". /lib/functions.sh\n. /lib/functions/migrations.sh\n\nremove_devicename_leds \"rt2800soc-phy0\" \"rt2800pci-phy0\"\n\nmigrations_apply system\n\nexit 0\n"
  },
  {
    "path": "target/linux/ramips/base-files/etc/uci-defaults/09_fix-checksum",
    "content": "#\n# Copyright (C) 2012 OpenWrt.org\n#\n\n. /lib/functions.sh\n\nfix_checksum() {\n\tlocal kernel_size=$(sed -n 's/mtd[0-9]*: \\([0-9a-f]*\\).*\"kernel\".*/\\1/p' /proc/mtd)\n\n\t[ \"$kernel_size\" ] && mtd -c 0x$kernel_size fix$1 firmware\n}\n\nboard=$(board_name)\n\ncase \"$board\" in\ndlink,dap-1522-a1)\n\tfix_checksum wrg\n\t;;\ndlink,dch-m225|\\\ndlink,dir-645|\\\ndlink,dir-860l-b1|\\\nsamsung,cy-swr1100)\n\tfix_checksum seama\n\t;;\nesac\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620a.dtsi",
    "content": "/dts-v1/;\n\n/ {\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\tcompatible = \"ralink,mt7620a-soc\";\n\n\taliases {\n\t\tspi0 = &spi0;\n\t\tspi1 = &spi1;\n\t\tserial0 = &uartlite;\n\t};\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu@0 {\n\t\t\tcompatible = \"mips,mips24KEc\";\n\t\t\treg = <0>;\n\t\t};\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,57600\";\n\t};\n\n\tcpuintc: cpuintc {\n\t\t#address-cells = <0>;\n\t\t#interrupt-cells = <1>;\n\t\tinterrupt-controller;\n\t\tcompatible = \"mti,cpu-interrupt-controller\";\n\t};\n\n\tpalmbus: palmbus@10000000 {\n\t\tcompatible = \"palmbus\";\n\t\treg = <0x10000000 0x200000>;\n\t\tranges = <0x0 0x10000000 0x1FFFFF>;\n\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tsysc: sysc@0 {\n\t\t\tcompatible = \"ralink,mt7620a-sysc\", \"ralink,rt3050-sysc\", \"syscon\";\n\t\t\treg = <0x0 0x100>;\n\t\t};\n\n\t\ttimer: timer@100 {\n\t\t\tcompatible = \"ralink,mt7620a-timer\", \"ralink,rt2880-timer\";\n\t\t\treg = <0x100 0x20>;\n\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <1>;\n\t\t};\n\n\t\twatchdog: watchdog@120 {\n\t\t\tcompatible = \"ralink,mt7620a-wdt\", \"ralink,rt2880-wdt\";\n\t\t\treg = <0x120 0x10>;\n\n\t\t\tresets = <&rstctrl 8>;\n\t\t\treset-names = \"wdt\";\n\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <1>;\n\t\t};\n\n\t\tintc: intc@200 {\n\t\t\tcompatible = \"ralink,mt7620a-intc\", \"ralink,rt2880-intc\";\n\t\t\treg = <0x200 0x100>;\n\n\t\t\tresets = <&rstctrl 19>;\n\t\t\treset-names = \"intc\";\n\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <1>;\n\n\t\t\tinterrupt-parent = <&cpuintc>;\n\t\t\tinterrupts = <2>;\n\t\t};\n\n\t\tmemc: memc@300 {\n\t\t\tcompatible = \"ralink,mt7620a-memc\", \"ralink,rt3050-memc\";\n\t\t\treg = <0x300 0x100>;\n\n\t\t\tresets = <&rstctrl 20>;\n\t\t\treset-names = \"mc\";\n\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <3>;\n\t\t};\n\n\t\tuart: uart@500 {\n\t\t\tcompatible = \"ralink,mt7620a-uart\", \"ralink,rt2880-uart\", \"ns16550a\";\n\t\t\treg = <0x500 0x100>;\n\n\t\t\tresets = <&rstctrl 12>;\n\t\t\treset-names = \"uart\";\n\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <5>;\n\n\t\t\treg-shift = <2>;\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tgpio0: gpio@600 {\n\t\t\tcompatible = \"ralink,mt7620a-gpio\", \"ralink,rt2880-gpio\";\n\t\t\treg = <0x600 0x34>;\n\n\t\t\tresets = <&rstctrl 13>;\n\t\t\treset-names = \"pio\";\n\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <6>;\n\n\t\t\tgpio-controller;\n\t\t\t#gpio-cells = <2>;\n\n\t\t\tngpios = <24>;\n\t\t\tralink,gpio-base = <0>;\n\t\t\tralink,register-map = [ 00 04 08 0c\n\t\t\t\t\t\t20 24 28 2c\n\t\t\t\t\t\t30 34 ];\n\t\t};\n\n\t\tgpio1: gpio@638 {\n\t\t\tcompatible = \"ralink,mt7620a-gpio\", \"ralink,rt2880-gpio\";\n\t\t\treg = <0x638 0x24>;\n\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <6>;\n\n\t\t\tgpio-controller;\n\t\t\t#gpio-cells = <2>;\n\n\t\t\tngpios = <16>;\n\t\t\tralink,gpio-base = <24>;\n\t\t\tralink,register-map = [ 00 04 08 0c\n\t\t\t\t\t\t10 14 18 1c\n\t\t\t\t\t\t20 24 ];\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tgpio2: gpio@660 {\n\t\t\tcompatible = \"ralink,mt7620a-gpio\", \"ralink,rt2880-gpio\";\n\t\t\treg = <0x660 0x24>;\n\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <6>;\n\n\t\t\tgpio-controller;\n\t\t\t#gpio-cells = <2>;\n\n\t\t\tngpios = <32>;\n\t\t\tralink,gpio-base = <40>;\n\t\t\tralink,register-map = [ 00 04 08 0c\n\t\t\t\t\t\t10 14 18 1c\n\t\t\t\t\t\t20 24 ];\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tgpio3: gpio@688 {\n\t\t\tcompatible = \"ralink,mt7620a-gpio\", \"ralink,rt2880-gpio\";\n\t\t\treg = <0x688 0x24>;\n\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <6>;\n\n\t\t\tgpio-controller;\n\t\t\t#gpio-cells = <2>;\n\n\t\t\tngpios = <1>;\n\t\t\tralink,gpio-base = <72>;\n\t\t\tralink,register-map = [ 00 04 08 0c\n\t\t\t\t\t\t10 14 18 1c\n\t\t\t\t\t\t20 24 ];\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\ti2c: i2c@900 {\n\t\t\tcompatible = \"ralink,rt2880-i2c\";\n\t\t\treg = <0x900 0x100>;\n\n\t\t\tresets = <&rstctrl 16>;\n\t\t\treset-names = \"i2c\";\n\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\n\t\t\tstatus = \"disabled\";\n\n\t\t\tpinctrl-names = \"default\";\n\t\t\tpinctrl-0 = <&i2c_pins>;\n\t\t};\n\n\t\ti2s: i2s@a00 {\n\t\t\tcompatible = \"mediatek,mt7620-i2s\";\n\t\t\treg = <0xa00 0x100>;\n\n\t\t\tresets = <&rstctrl 17>;\n\t\t\treset-names = \"i2s\";\n\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <10>;\n\n\t\t\ttxdma-req = <2>;\n\t\t\trxdma-req = <3>;\n\n\t\t\tdmas = <&gdma 4>,\n\t\t\t\t<&gdma 6>;\n\t\t\tdma-names = \"tx\", \"rx\";\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tspi0: spi@b00 {\n\t\t\tcompatible = \"ralink,mt7620a-spi\", \"ralink,rt2880-spi\";\n\t\t\treg = <0xb00 0x40>;\n\n\t\t\tresets = <&rstctrl 18>;\n\t\t\treset-names = \"spi\";\n\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\n\t\t\tstatus = \"disabled\";\n\n\t\t\tpinctrl-names = \"default\";\n\t\t\tpinctrl-0 = <&spi_pins>;\n\t\t};\n\n\t\tspi1: spi@b40 {\n\t\t\tcompatible = \"ralink,rt2880-spi\";\n\t\t\treg = <0xb40 0x60>;\n\n\t\t\tresets = <&rstctrl 18>;\n\t\t\treset-names = \"spi\";\n\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\n\t\t\tstatus = \"disabled\";\n\n\t\t\tpinctrl-names = \"default\";\n\t\t\tpinctrl-0 = <&spi_cs1>;\n\t\t};\n\n\t\tuartlite: uartlite@c00 {\n\t\t\tcompatible = \"ralink,mt7620a-uart\", \"ralink,rt2880-uart\", \"ns16550a\";\n\t\t\treg = <0xc00 0x100>;\n\n\t\t\tresets = <&rstctrl 19>;\n\t\t\treset-names = \"uartl\";\n\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <12>;\n\n\t\t\treg-shift = <2>;\n\n\t\t\tpinctrl-names = \"default\";\n\t\t\tpinctrl-0 = <&uartlite_pins>;\n\t\t};\n\n\t\tsystick: systick@d00 {\n\t\t\tcompatible = \"ralink,mt7620a-systick\", \"ralink,cevt-systick\";\n\t\t\treg = <0xd00 0x10>;\n\n\t\t\tresets = <&rstctrl 28>;\n\t\t\treset-names = \"intc\";\n\n\t\t\tinterrupt-parent = <&cpuintc>;\n\t\t\tinterrupts = <7>;\n\t\t};\n\n\t\tpcm: pcm@2000 {\n\t\t\tcompatible = \"ralink,mt7620a-pcm\";\n\t\t\treg = <0x2000 0x800>;\n\n\t\t\tresets = <&rstctrl 11>;\n\t\t\treset-names = \"pcm\";\n\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <4>;\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tgdma: gdma@2800 {\n\t\t\tcompatible = \"ralink,mt7620a-gdma\", \"ralink,rt3883-gdma\";\n\t\t\treg = <0x2800 0x800>;\n\n\t\t\tresets = <&rstctrl 14>;\n\t\t\treset-names = \"dma\";\n\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <7>;\n\n\t\t\t#dma-cells = <1>;\n\t\t\t#dma-channels = <16>;\n\t\t\t#dma-requests = <16>;\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\t};\n\n\tpinctrl: pinctrl {\n\t\tcompatible = \"ralink,rt2880-pinmux\";\n\t\tpinctrl-names = \"default\";\n\t\tpinctrl-0 = <&state_default>;\n\n\t\tstate_default: pinctrl0 {\n\t\t};\n\n\t\tpcm_i2s_pins: pcm_i2s {\n\t\t\tpcm_i2s {\n\t\t\t\tgroups = \"uartf\";\n\t\t\t\tfunction = \"pcm i2s\";\n\t\t\t};\n\t\t};\n\n\t\tuartf_gpio_pins: uartf_gpio {\n\t\t\tuartf_gpio {\n\t\t\t\tgroups = \"uartf\";\n\t\t\t\tfunction = \"gpio uartf\";\n\t\t\t};\n\t\t};\n\n\t\tgpio_i2s_pins: gpio_i2s {\n\t\t\tgpio_i2s {\n\t\t\t\tgroups = \"uartf\";\n\t\t\t\tfunction = \"gpio i2s\";\n\t\t\t};\n\t\t};\n\n\t\tspi_pins: spi_pins {\n\t\t\tspi_pins {\n\t\t\t\tgroups = \"spi\";\n\t\t\t\tfunction = \"spi\";\n\t\t\t};\n\t\t};\n\n\t\tspi_cs1: spi1 {\n\t\t\tspi1 {\n\t\t\t\tgroups = \"spi refclk\";\n\t\t\t\tfunction = \"spi refclk\";\n\t\t\t};\n\t\t};\n\n\t\ti2c_pins: i2c_pins {\n\t\t\ti2c_pins {\n\t\t\t\tgroups = \"i2c\";\n\t\t\t\tfunction = \"i2c\";\n\t\t\t};\n\t\t};\n\n\t\tuartlite_pins: uartlite {\n\t\t\tuart {\n\t\t\t\tgroups = \"uartlite\";\n\t\t\t\tfunction = \"uartlite\";\n\t\t\t};\n\t\t};\n\n\t\tmdio_pins: mdio {\n\t\t\tmdio {\n\t\t\t\tgroups = \"mdio\";\n\t\t\t\tfunction = \"mdio\";\n\t\t\t};\n\t\t};\n\n\t\tmdio_refclk_pins: mdio_refclk {\n\t\t\tmdio_refclk {\n\t\t\t\tgroups = \"mdio\";\n\t\t\t\tfunction = \"refclk\";\n\t\t\t};\n\t\t};\n\n\t\tephy_pins: ephy {\n\t\t\tephy {\n\t\t\t\tgroups = \"ephy\";\n\t\t\t\tfunction = \"ephy\";\n\t\t\t};\n\t\t};\n\n\t\twled_pins: wled {\n\t\t\twled {\n\t\t\t\tgroups = \"wled\";\n\t\t\t\tfunction = \"wled\";\n\t\t\t};\n\t\t};\n\n\t\trgmii1_pins: rgmii1 {\n\t\t\trgmii1 {\n\t\t\t\tgroups = \"rgmii1\";\n\t\t\t\tfunction = \"rgmii1\";\n\t\t\t};\n\t\t};\n\n\t\trgmii2_pins: rgmii2 {\n\t\t\trgmii2 {\n\t\t\t\tgroups = \"rgmii2\";\n\t\t\t\tfunction = \"rgmii2\";\n\t\t\t};\n\t\t};\n\n\t\tpcie_pins: pcie {\n\t\t\tpcie {\n\t\t\t\tgroups = \"pcie\";\n\t\t\t\tfunction = \"pcie rst\";\n\t\t\t};\n\t\t};\n\n\t\tpa_pins: pa {\n\t\t\tpa {\n\t\t\t\tgroups = \"pa\";\n\t\t\t\tfunction = \"pa\";\n\t\t\t};\n\t\t};\n\n\t\tsdhci_pins: sdhci {\n\t\t\tsdhci {\n\t\t\t\tgroups = \"nd_sd\";\n\t\t\t\tfunction = \"sd\";\n\t\t\t};\n\t\t};\n\t};\n\n\trstctrl: rstctrl {\n\t\tcompatible = \"ralink,mt7620a-reset\", \"ralink,rt2880-reset\";\n\t\t#reset-cells = <1>;\n\t};\n\n\tclkctrl: clkctrl {\n\t\tcompatible = \"ralink,rt2880-clock\";\n\t\t#clock-cells = <1>;\n\t};\n\n\tusbphy: usbphy {\n\t\tcompatible = \"mediatek,mt7620-usbphy\";\n\t\t#phy-cells = <0>;\n\n\t\tralink,sysctl = <&sysc>;\n\t\tresets = <&rstctrl 22 &rstctrl 25>;\n\t\treset-names = \"host\", \"device\";\n\n\t\tclocks = <&clkctrl 22 &clkctrl 25>;\n\t\tclock-names = \"host\", \"device\";\n\t};\n\n\tethernet: ethernet@10100000 {\n\t\tcompatible = \"mediatek,mt7620-eth\";\n\t\treg = <0x10100000 0x10000>;\n\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tinterrupt-parent = <&cpuintc>;\n\t\tinterrupts = <5>;\n\n\t\tresets = <&rstctrl 21 &rstctrl 23>;\n\t\treset-names = \"fe\", \"esw\";\n\n\t\tmediatek,switch = <&gsw>;\n\n\t\tport@4 {\n\t\t\tcompatible = \"mediatek,mt7620a-gsw-port\", \"mediatek,eth-port\";\n\t\t\treg = <4>;\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tport@5 {\n\t\t\tcompatible = \"mediatek,mt7620a-gsw-port\", \"mediatek,eth-port\";\n\t\t\treg = <5>;\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tmdio-bus {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\t};\n\n\tgsw: gsw@10110000 {\n\t\tcompatible = \"mediatek,mt7620-gsw\";\n\t\treg = <0x10110000 0x8000>;\n\n\t\tresets = <&rstctrl 23>;\n\t\treset-names = \"esw\";\n\n\t\tinterrupt-parent = <&intc>;\n\t\tinterrupts = <17>;\n\t};\n\n\tsdhci: sdhci@10130000 {\n\t\tcompatible = \"ralink,mt7620-sdhci\";\n\t\treg = <0x10130000 0x4000>;\n\n\t\tinterrupt-parent = <&intc>;\n\t\tinterrupts = <14>;\n\n\t\tpinctrl-names = \"default\";\n\t\tpinctrl-0 = <&sdhci_pins>;\n\n\t\tstatus = \"disabled\";\n\t};\n\n\tehci: ehci@101c0000 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tcompatible = \"generic-ehci\";\n\t\treg = <0x101c0000 0x1000>;\n\n\t\tinterrupt-parent = <&intc>;\n\t\tinterrupts = <18>;\n\n\t\tphys = <&usbphy>;\n\t\tphy-names = \"usb\";\n\n\t\tstatus = \"disabled\";\n\n\t\tehci_port1: port@1 {\n\t\t\treg = <1>;\n\t\t\t#trigger-source-cells = <0>;\n\t\t};\n\t};\n\n\tohci: ohci@101c1000 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tcompatible = \"generic-ohci\";\n\t\treg = <0x101c1000 0x1000>;\n\n\t\tinterrupt-parent = <&intc>;\n\t\tinterrupts = <18>;\n\n\t\tphys = <&usbphy>;\n\t\tphy-names = \"usb\";\n\n\t\tstatus = \"disabled\";\n\n\t\tohci_port1: port@1 {\n\t\t\treg = <1>;\n\t\t\t#trigger-source-cells = <0>;\n\t\t};\n\t};\n\n\tpcie: pcie@10140000 {\n\t\tcompatible = \"mediatek,mt7620-pci\";\n\t\treg = <0x10140000 0x100\n\t\t\t0x10142000 0x100>;\n\n\t\t#address-cells = <3>;\n\t\t#size-cells = <2>;\n\n\t\tresets = <&rstctrl 26>;\n\t\treset-names = \"pcie0\";\n\n\t\tclocks = <&clkctrl 26>;\n\t\tclock-names = \"pcie0\";\n\n\t\tinterrupt-parent = <&cpuintc>;\n\t\tinterrupts = <4>;\n\n\t\tpinctrl-names = \"default\";\n\t\tpinctrl-0 = <&pcie_pins>;\n\n\t\tdevice_type = \"pci\";\n\n\t\tbus-range = <0 255>;\n\t\tranges = <\n\t\t\t0x02000000 0 0x00000000 0x20000000 0 0x10000000 /* pci memory */\n\t\t\t0x01000000 0 0x00000000 0x10160000 0 0x00010000 /* io space */\n\t\t>;\n\n\t\tstatus = \"disabled\";\n\n\t\tpcie0: pcie@0,0 {\n\t\t\treg = <0x0000 0 0 0 0>;\n\n\t\t\t#address-cells = <3>;\n\t\t\t#size-cells = <2>;\n\n\t\t\tdevice_type = \"pci\";\n\n\t\t\tranges;\n\t\t};\n\t};\n\n\twmac: wmac@10180000 {\n\t\tcompatible = \"ralink,rt7620-wmac\", \"ralink,rt2880-wmac\";\n\t\treg = <0x10180000 0x40000>;\n\n\t\tinterrupt-parent = <&cpuintc>;\n\t\tinterrupts = <6>;\n\n\t\tralink,eeprom = \"soc_wmac.eeprom\";\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620a_aigale_ai-br100.dts",
    "content": "#include \"mt7620a.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"aigale,ai-br100\", \"ralink,mt7620a-soc\";\n\tmodel = \"Aigale Ai-BR100\";\n\n\taliases {\n\t\tled-boot = &led_wlan;\n\t\tled-failsafe = &led_wlan;\n\t\tled-running = &led_wlan;\n\t\tled-upgrade = &led_wlan;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twan {\n\t\t\tlabel = \"blue:wan\";\n\t\t\tgpios = <&gpio2 4 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_wlan: wlan {\n\t\t\tlabel = \"blue:wlan\";\n\t\t\tgpios = <&gpio3 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 12 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n};\n\n&gpio2 {\n\tstatus = \"okay\";\n};\n\n&gpio3 {\n\tstatus = \"okay\";\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x20000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x20000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@30000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x40000 0x7c0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&ehci {\n\tstatus = \"okay\";\n};\n\n&ohci {\n\tstatus = \"okay\";\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"uartf\", \"rgmii1\", \"rgmii2\", \"ephy\", \"wled\", \"nd_sd\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tmediatek,portmap = \"llllw\";\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620a_alfa-network_ac1200rm.dts",
    "content": "// SPDX-License-Identifier: BSD-3-Clause\n/*\n *  Copyright (C) 2018 Piotr Dymacz <pepe2k@gmail.com>\n *  All rights reserved.\n */\n\n#include \"mt7620a.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"alfa-network,ac1200rm\", \"ralink,mt7620a-soc\";\n\tmodel = \"ALFA Network AC1200RM\";\n\n\taliases {\n\t\tled-boot = &led_wps;\n\t\tled-failsafe = &led_wps;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio2 15 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twlan2g {\n\t\t\tlabel = \"green:wlan2g\";\n\t\t\tgpios = <&gpio3 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_wps: wps {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&ehci {\n\tstatus = \"okay\";\n};\n\n&ethernet {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&ephy_pins>;\n\n\tnvmem-cells = <&macaddr_factory_28>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tmediatek,portmap = \"llllw\";\n};\n\n&gpio1 {\n\tstatus = \"okay\";\n};\n\n&gpio2 {\n\tstatus = \"okay\";\n};\n\n&gpio3 {\n\tstatus = \"okay\";\n};\n\n&ohci {\n\tstatus = \"okay\";\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\tmt76@0,0 {\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\n\t\tled {\n\t\t\tled-sources = <2>;\n\t\t\tled-active-low;\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"nd_sd\", \"spi refclk\", \"wled\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x1000>;\n\t\t\t};\n\n\t\t\tpartition@31000 {\n\t\t\t\tlabel = \"config\";\n\t\t\t\treg = <0x31000 0xf000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0xfb0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_28: macaddr@28 {\n\t\treg = <0x28 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620a_alfa-network_r36m-e4g.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7620a.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"alfa-network,r36m-e4g\", \"ralink,mt7620a-soc\";\n\tmodel = \"ALFA Network R36M-E4G\";\n\n\taliases {\n\t\tlabel-mac-device = &wmac;\n\t\tled-boot = &led_system;\n\t\tled-failsafe = &led_system;\n\t\tled-running = &led_system;\n\t\tled-upgrade = &led_system;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyS1,115200\";\n\t};\n\n\tgpio-export {\n\t\tcompatible = \"gpio-export\";\n\t\t#size-cells = <0>;\n\n\t\tmodem-enable {\n\t\t\tgpio-export,name = \"modem-enable\";\n\t\t\tgpio-export,output = <1>;\n\t\t\tgpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tmodem-rf-enable {\n\t\t\tgpio-export,name = \"modem-rf-enable\";\n\t\t\tgpio-export,output = <1>;\n\t\t\tgpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\trtc-enable {\n\t\t\tgpio-export,name = \"rtc-enable\";\n\t\t\tgpio-export,output = <1>;\n\t\t\tgpio-export,direction_may_change = <1>;\n\t\t\tgpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tsim-select {\n\t\t\tgpio-export,name = \"sim-select\";\n\t\t\tgpio-export,output = <0>;\n\t\t\tgpios = <&gpio1 0 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tsim1-detect {\n\t\t\tgpio-export,name = \"sim1-detect\";\n\t\t\tgpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tsim2-detect {\n\t\t\tgpio-export,name = \"sim2-detect\";\n\t\t\tgpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio1 9 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\trfkill {\n\t\t\tlabel = \"rfkill\";\n\t\t\tgpios = <&gpio1 7 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RFKILL>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\t4g {\n\t\t\tlabel = \"orange:4g\";\n\t\t\tgpios = <&gpio1 3 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan {\n\t\t\tlabel = \"green:lan\";\n\t\t\tgpios = <&gpio2 3 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_system: system {\n\t\t\tlabel = \"green:system\";\n\t\t\tgpios = <&gpio2 0 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"keep\";\n\t\t};\n\n\t\tsim1 {\n\t\t\tlabel = \"green:sim1\";\n\t\t\tgpios = <&gpio1 5 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"keep\";\n\t\t};\n\n\t\tsim2 {\n\t\t\tlabel = \"green:sim2\";\n\t\t\tgpios = <&gpio2 2 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"keep\";\n\t\t};\n\n\t\twan {\n\t\t\tlabel = \"green:wan\";\n\t\t\tgpios = <&gpio2 4 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan {\n\t\t\tlabel = \"orange:wlan\";\n\t\t\tgpios = <&gpio3 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0radio\";\n\t\t};\n\t};\n};\n\n&ehci {\n\tstatus = \"okay\";\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_28>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&gpio1 {\n\tstatus = \"okay\";\n};\n\n&gpio2 {\n\tstatus = \"okay\";\n};\n\n&gpio3 {\n\tstatus = \"okay\";\n};\n\n&i2c {\n\tstatus = \"okay\";\n};\n\n&ohci {\n\tstatus = \"okay\";\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"ephy\", \"pcie\", \"rgmii1\", \"wled\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <50000000>;\n\t\tm25p,fast-read;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x1000>;\n\t\t\t};\n\n\t\t\tpartition@31000 {\n\t\t\t\tlabel = \"config\";\n\t\t\t\treg = <0x31000 0xf000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0xfb0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&uart {\n\tstatus = \"okay\";\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_28: macaddr@28 {\n\t\treg = <0x28 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620a_alfa-network_tube-e4g.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7620a.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"alfa-network,tube-e4g\", \"ralink,mt7620a-soc\";\n\tmodel = \"ALFA Network Tube-E4G\";\n\n\taliases {\n\t\tlabel-mac-device = &ethernet;\n\t\tled-boot = &power;\n\t\tled-failsafe = &power;\n\t\tled-running = &power;\n\t\tled-upgrade = &power;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200\";\n\t};\n\n\tgpio-export {\n\t\tcompatible = \"gpio-export\";\n\t\t#size-cells = <0>;\n\n\t\tmodem-enable {\n\t\t\tgpio-export,name = \"modem-enable\";\n\t\t\tgpio-export,output = <1>;\n\t\t\tgpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tmodem-rf-enable {\n\t\t\tgpio-export,name = \"modem-rf-enable\";\n\t\t\tgpio-export,output = <1>;\n\t\t\tgpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tsim-select {\n\t\t\tgpio-export,name = \"sim-select\";\n\t\t\tgpio-export,output = <0>;\n\t\t\tgpios = <&gpio0 13 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tsim1-detect {\n\t\t\tgpio-export,name = \"sim1-detect\";\n\t\t\tgpios = <&gpio0 9 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tsim2-detect {\n\t\t\tgpio-export,name = \"sim2-detect\";\n\t\t\tgpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio2 15 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\t4g {\n\t\t\tlabel = \"green:4g\";\n\t\t\tgpios = <&gpio0 7 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan {\n\t\t\tlabel = \"blue:lan\";\n\t\t\tgpios = <&gpio2 4 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tpower: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio2 0 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"keep\";\n\t\t};\n\n\t\tsim1 {\n\t\t\tlabel = \"green:sim1\";\n\t\t\tgpios = <&gpio2 3 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"keep\";\n\t\t};\n\n\t\tsim2 {\n\t\t\tlabel = \"green:sim2\";\n\t\t\tgpios = <&gpio2 2 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"keep\";\n\t\t};\n\t};\n};\n\n&ehci {\n\tstatus = \"okay\";\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_28>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&gpio1 {\n\tstatus = \"okay\";\n};\n\n&gpio2 {\n\tstatus = \"okay\";\n};\n\n&ohci {\n\tstatus = \"okay\";\n};\n\n&pcie {\n\tstatus = \"disabled\";\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"ephy\", \"nd_sd\", \"pcie\", \"uartf\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <50000000>;\n\t\tm25p,fast-read;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x1000>;\n\t\t\t};\n\n\t\t\tpartition@31000 {\n\t\t\t\tlabel = \"config\";\n\t\t\t\treg = <0x31000 0xf000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0xfb0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&wmac {\n\tstatus = \"disabled\";\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_28: macaddr@28 {\n\t\treg = <0x28 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620a_asus_rp-n53.dts",
    "content": "#include \"mt7620a.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"asus,rp-n53\", \"ralink,mt7620a-soc\";\n\tmodel = \"Asus RP-N53\";\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\ttouch {\n\t\t\tlabel = \"touch\";\n\t\t\tgpios = <&gpio1 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_0>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio1 1 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_0>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio1 2 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_0>;\n\t\t};\n\n\t\taudio {\n\t\t\tlabel = \"audio\";\n\t\t\tgpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = <BTN_1>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tbacklight {\n\t\t\tlabel = \"white:back\";\n\t\t\tgpios = <&gpio1 4 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twifi0 {\n\t\t\tlabel = \"blue:5g3\";\n\t\t\tgpios = <&gpio1 5 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twifi1 {\n\t\t\tlabel = \"blue:5g2\";\n\t\t\tgpios = <&gpio1 6 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twifi2 {\n\t\t\tlabel = \"blue:5g1\";\n\t\t\tgpios = <&gpio1 7 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twifi3 {\n\t\t\tlabel = \"blue:wifi\";\n\t\t\tgpios = <&gpio1 8 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twifi4 {\n\t\t\tlabel = \"blue:2g1\";\n\t\t\tgpios = <&gpio1 9 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twifi5 {\n\t\t\tlabel = \"blue:2g2\";\n\t\t\tgpios = <&gpio1 10 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twifi6 {\n\t\t\tlabel = \"blue:2g3\";\n\t\t\tgpios = <&gpio1 11 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&gpio1 {\n\tstatus = \"okay\";\n};\n\n&i2c {\n\tstatus = \"okay\";\n};\n\n&i2s {\n\tstatus = \"okay\";\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pcm_i2s_pins>;\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x7b0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pcm {\n\tstatus = \"okay\";\n};\n\n&gdma {\n\tstatus = \"okay\";\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"mdio\", \"rgmii1\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&ephy_pins>;\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\twifi@0,0 {\n\t\tcompatible = \"pci1814,5592\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tralink,2ghz = <0>;\n\t\tralink,mtd-eeprom = <&factory 0x8000>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620a_asus_rt-ac51u.dts",
    "content": "#include \"mt7620a_asus_rt-ac5x.dtsi\"\n\n/ {\n\tcompatible = \"asus,rt-ac51u\", \"ralink,mt7620a-soc\";\n\tmodel = \"Asus RT-AC51U\";\n};\n\n&pcie0 {\n\twifi@0,0 {\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620a_asus_rt-ac54u.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7620a_asus_rt-ac5x.dtsi\"\n\n/ {\n\tcompatible = \"asus,rt-ac54u\", \"ralink,mt7620a-soc\";\n\tmodel = \"Asus RT-AC54U\";\n};\n\n&pcie0 {\n\twifi@0,0 {\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\n\t\tled {\n\t\t\tled-sources = <2>;\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620a_asus_rt-ac5x.dtsi",
    "content": "#include \"mt7620a.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\taliases {\n\t\tlabel-mac-device = &ethernet;\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 1 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio0 2 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"blue:power\";\n\t\t\tgpios = <&gpio0 9 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tusb {\n\t\t\tlabel = \"blue:usb\";\n\t\t\tgpios = <&gpio0 14 GPIO_ACTIVE_LOW>;\n\t\t\ttrigger-sources = <&ohci_port1>, <&ehci_port1>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\n\t\twifi2g {\n\t\t\tlabel = \"blue:wifi2g\";\n\t\t\tgpios = <&gpio3 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\n\t\tspi-max-frequency = <50000000>;\n\t\tm25p,fast-read;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0xfb0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&ehci {\n\tstatus = \"okay\";\n};\n\n&ohci {\n\tstatus = \"okay\";\n};\n\n&gpio0 {\n\tenable-leds {\n\t\tgpio-hog;\n\t\tline-name = \"enable-leds\";\n\t\toutput-low;\n\t\tgpios = <10 GPIO_ACTIVE_HIGH>;\n\t};\n};\n\n&gpio3 {\n\tstatus = \"okay\";\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"wled\", \"uartf\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_28>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tmediatek,portmap = \"wllll\";\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_28: macaddr@28 {\n\t\treg = <0x28 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620a_bdcom_wap2100-sk.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7620a.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"bdcom,wap2100-sk\", \"ralink,mt7620a-soc\";\n\tmodel = \"BDCOM WAP2100-SK\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200\";\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tusb {\n\t\t\tlabel = \"green:usb\";\n\t\t\tgpios = <&gpio0 11 GPIO_ACTIVE_LOW>;\n\t\t\ttrigger-sources = <&ohci_port1>, <&ehci_port1>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\n\t\tled_power: wps {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&gpio1 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan2g {\n\t\t\tlabel = \"green:wlan2g\";\n\t\t\tgpios = <&gpio3 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio0 12 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 13 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0xf70000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&gpio1 {\n\tstatus = \"okay\";\n};\n\n&gpio3 {\n\tstatus = \"okay\";\n};\n\n&sdhci {\n\tstatus = \"okay\";\n};\n\n&ehci {\n\tstatus = \"okay\";\n};\n\n&ohci {\n\tstatus = \"okay\";\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tmediatek,portmap = \"wllll\";\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\twifi@0,0 {\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\t};\n};\n\n&state_default {\n\tdefault {\n\t\tgroups = \"spi refclk\", \"uartf\", \"wled\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620a_buffalo_whr-1166d.dts",
    "content": "#include \"mt7620a.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"buffalo,whr-1166d\", \"ralink,mt7620a-soc\";\n\tmodel = \"Buffalo WHR-1166D\";\n\n\taliases {\n\t\tled-boot = &led_power_green;\n\t\tled-failsafe = &led_power_green;\n\t\tled-running = &led_power_green;\n\t\tled-upgrade = &led_power_green;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tpower {\n\t\t\tlabel = \"red:power\";\n\t\t\tgpios = <&gpio0 7 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twifi {\n\t\t\tlabel = \"green:wifi\";\n\t\t\tgpios = <&gpio0 8 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_power_green: power2 {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio0 9 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twifi2 {\n\t\t\tlabel = \"orange:wifi\";\n\t\t\tgpios = <&gpio0 10 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tinternet {\n\t\t\tlabel = \"green:internet\";\n\t\t\tgpios = <&gpio2 17 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\trouter {\n\t\t\tlabel = \"orange:router\";\n\t\t\tgpios = <&gpio2 18 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\trouter2 {\n\t\t\tlabel = \"green:router\";\n\t\t\tgpios = <&gpio2 19 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio2 12 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\taoss {\n\t\t\tlabel = \"aoss\";\n\t\t\tgpios = <&gpio2 13 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\n\t\tap {\n\t\t\tlabel = \"ap\";\n\t\t\tgpios = <&gpio2 14 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_0>;\n\t\t\tlinux,input-type = <EV_SW>;\n\t\t};\n\n\t\tbridge {\n\t\t\tlabel = \"bridge\";\n\t\t\tgpios = <&gpio2 15 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_0>;\n\t\t\tlinux,input-type = <EV_SW>;\n\t\t};\n\t};\n};\n\n&gpio2 {\n\tstatus = \"okay\";\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0xfb0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"uartf\", \"wled\", \"nd_sd\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&rgmii1_pins &mdio_pins>;\n\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tport@5 {\n\t\tstatus = \"okay\";\n\t\tphy-handle = <&phy5>;\n\t\tphy-mode = \"rgmii\";\n\t};\n\n\tmdio-bus {\n\t\tstatus = \"okay\";\n\n\t\tphy5: ethernet-phy@5 {\n\t\t\treg = <5>;\n\t\t\tphy-mode = \"rgmii-rxid\";\n\t\t};\n\t};\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\twifi@0,0 {\n\t\tcompatible = \"pci0,0\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\t};\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620a_buffalo_whr-300hp2.dts",
    "content": "#include \"mt7620a.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"buffalo,whr-300hp2\", \"ralink,mt7620a-soc\";\n\tmodel = \"Buffalo WHR-300HP2\";\n\n\taliases {\n\t\tled-boot = &led_power_green;\n\t\tled-failsafe = &led_power_green;\n\t\tled-running = &led_power_green;\n\t\tled-upgrade = &led_power_green;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tpower {\n\t\t\tlabel = \"red:power\";\n\t\t\tgpios = <&gpio0 7 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twifi {\n\t\t\tlabel = \"green:wifi\";\n\t\t\tgpios = <&gpio0 8 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_power_green: power2 {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio0 9 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twifi2 {\n\t\t\tlabel = \"orange:wifi\";\n\t\t\tgpios = <&gpio0 10 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tinternet {\n\t\t\tlabel = \"green:internet\";\n\t\t\tgpios = <&gpio2 17 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\trouter {\n\t\t\tlabel = \"green:router\";\n\t\t\tgpios = <&gpio2 18 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\trouter2 {\n\t\t\tlabel = \"orange:router\";\n\t\t\tgpios = <&gpio2 19 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio2 12 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\taoss {\n\t\t\tlabel = \"aoss\";\n\t\t\tgpios = <&gpio2 13 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\n\t\tap {\n\t\t\tlabel = \"ap\";\n\t\t\tgpios = <&gpio2 14 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_0>;\n\t\t\tlinux,input-type = <EV_SW>;\n\t\t};\n\n\t\tbridge {\n\t\t\tlabel = \"bridge\";\n\t\t\tgpios = <&gpio2 15 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_0>;\n\t\t\tlinux,input-type = <EV_SW>;\n\t\t};\n\t};\n};\n\n&gpio2 {\n\tstatus = \"okay\";\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x7b0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"uartf\", \"rgmii1\", \"rgmii2\", \"wled\", \"nd_sd\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&ephy_pins>;\n\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tmediatek,portmap = \"llllw\";\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pa_pins>;\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620a_buffalo_whr-600d.dts",
    "content": "#include \"mt7620a.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"buffalo,whr-600d\", \"ralink,mt7620a-soc\";\n\tmodel = \"Buffalo WHR-600D\";\n\n\taliases {\n\t\tled-boot = &led_power_green;\n\t\tled-failsafe = &led_power_green;\n\t\tled-running = &led_power_green;\n\t\tled-upgrade = &led_power_green;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tpower {\n\t\t\tlabel = \"red:power\";\n\t\t\tgpios = <&gpio0 7 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twifi {\n\t\t\tlabel = \"green:wifi\";\n\t\t\tgpios = <&gpio0 8 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_power_green: power2 {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio0 9 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twifi2 {\n\t\t\tlabel = \"orange:wifi\";\n\t\t\tgpios = <&gpio0 10 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tinternet {\n\t\t\tlabel = \"green:internet\";\n\t\t\tgpios = <&gpio2 17 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\trouter {\n\t\t\tlabel = \"green:router\";\n\t\t\tgpios = <&gpio2 18 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\trouter2 {\n\t\t\tlabel = \"orange:router\";\n\t\t\tgpios = <&gpio2 19 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio2 12 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\taoss {\n\t\t\tlabel = \"aoss\";\n\t\t\tgpios = <&gpio2 13 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\n\t\tap {\n\t\t\tlabel = \"ap\";\n\t\t\tgpios = <&gpio2 14 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_0>;\n\t\t\tlinux,input-type = <EV_SW>;\n\t\t};\n\n\t\tbridge {\n\t\t\tlabel = \"bridge\";\n\t\t\tgpios = <&gpio2 15 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_0>;\n\t\t\tlinux,input-type = <EV_SW>;\n\t\t};\n\t};\n};\n\n&gpio2 {\n\tstatus = \"okay\";\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x7b0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"uartf\", \"rgmii1\", \"rgmii2\", \"wled\", \"nd_sd\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&ephy_pins>;\n\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tmediatek,portmap = \"llllw\";\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\twifi@0,0 {\n\t\tcompatible = \"pci1814,5592\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tralink,mtd-eeprom = <&factory 0x8000>;\n\t};\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620a_cameo_810.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7620a.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\taliases {\n\t\tlabel-mac-device = &ethernet;\n\t\tled-boot = &led_power_green;\n\t\tled-failsafe = &led_power_green;\n\t\tled-running = &led_power_green;\n\t\tled-upgrade = &led_power_green;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 1 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio0 2 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power_green: power_green {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio0 9 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\twan_orange {\n\t\t\tlabel = \"orange:wan\";\n\t\t\tgpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\twan_green {\n\t\t\tlabel = \"green:wan\";\n\t\t\tgpios = <&gpio2 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tpower_orange {\n\t\t\tlabel = \"orange:power\";\n\t\t\tgpios = <&gpio0 13 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <50000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory5g: partition@50000 {\n\t\t\t\tlabel = \"factory5g\";\n\t\t\t\treg = <0x50000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@60000 {\n\t\t\t\tlabel = \"Wolf_Config\";\n\t\t\t\treg = <0x60000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@70000 {\n\t\t\t\tlabel = \"MyDlink\";\n\t\t\t\treg = <0x70000 0x80000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@f0000 {\n\t\t\t\tlabel = \"Jffs2\";\n\t\t\t\treg = <0xf0000 0x80000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@170000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x170000 0x690000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"uartf\", \"ephy\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_28>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tmediatek,portmap = \"llllw\";\n};\n\n&gpio2 {\n\tstatus = \"okay\";\n};\n\n&wmac {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pa_pins>;\n\n\tralink,mtd-eeprom = <&factory 0x0>;\n\tnvmem-cells = <&macaddr_factory_28>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\twifi@0,0 {\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\t\tnvmem-cells = <&macaddr_factory_28>;\n\t\tnvmem-cell-names = \"mac-address\";\n\t\tmac-address-increment = <2>;\n\t};\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_28: macaddr@28 {\n\t\treg = <0x28 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620a_dlink_dch-m225.dts",
    "content": "#include \"mt7620a.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"dlink,dch-m225\", \"ralink,mt7620a-soc\";\n\tmodel = \"D-Link DCH-M225\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio0 11 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RFKILL>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio1 2 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio1 5 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\tstatus {\n\t\t\tlabel = \"red:status\";\n\t\t\tgpios = <&gpio1 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tsound {\n\t\tcompatible = \"simple-audio-card\";\n\t\tsimple-audio-card,name = \"Audio-I2S\";\n\t\tsimple-audio-card,format = \"i2s\";\n\t\tsimple-audio-card,bitclock-master = <&dailink0_master>;\n\t\tsimple-audio-card,frame-master = <&dailink0_master>;\n\t\tsimple-audio-card,widgets =\n\t\t\t\"Headphone\", \"Headphones\";\n\t\tsimple-audio-card,routing =\n\t\t\t\"Headphones\", \"HP_L\",\n\t\t\t\"Headphones\", \"HP_R\";\n\t\tsimple-audio-card,mclk-fs = <256>;\n\t\tsimple-audio-card,hp-det-gpio = <&gpio0 14 GPIO_ACTIVE_LOW>;\n\n\t\tsimple-audio-card,cpu {\n\t\t\tsound-dai = <&i2s>;\n\t\t};\n\n\t\tdailink0_master: simple-audio-card,codec {\n\t\t\tsound-dai = <&codec>;\n\t\t};\n\t};\n};\n\n&gpio1 {\n\tstatus = \"okay\";\n};\n\n&i2c {\n\tstatus = \"okay\";\n\n\tcodec: wm8960@1a {\n\t\t#sound-dai-cells = <0>;\n\t\tcompatible = \"wlf,wm8960\";\n\t\treg = <0x1a>;\n\n\t\twlf,shared-lrclk;\n\t};\n};\n\n&i2s {\n\t#sound-dai-cells = <0>;\n\tstatus = \"okay\";\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&mdio_refclk_pins>;\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <80000000>;\n\t\tm25p,fast-read;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x4000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@34000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x34000 0x4000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tnvram: partition@38000 {\n\t\t\t\tlabel = \"nvram\";\n\t\t\t\treg = <0x38000 0x8000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"devconf\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tlabel = \"upgrade_rec\";\n\t\t\t\treg = <0x50000 0x100000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@150000 {\n\t\t\t\tcompatible = \"seama\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x150000 0x6b0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&gdma {\n\tstatus = \"okay\";\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"wdt\", \"rgmii1\";\n\t\tfunction = \"gpio\";\n\t};\n\n\tgpio_i2s {\n\t\tgroups = \"uartf\";\n\t\tfunction = \"gpio i2s\";\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pa_pins>;\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620a_dlink_dir-510l.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7620a.dtsi\"\n\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/mtd/partitions/uimage.h>\n\n/ {\n\tcompatible = \"dlink,dir-510l\", \"ralink,mt7620a-soc\";\n\tmodel = \"D-Link DIR-510L\";\n\n\taliases {\n\t\tled-boot = &led_status;\n\t\tled-failsafe = &led_status;\n\t\tled-running = &led_status;\n\t\tled-upgrade = &led_status;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyS1,57600\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 1 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio0 2 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_status: status {\n\t\t\tlabel = \"green:status\";\n\t\t\tgpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tstatus-red {\n\t\t\tlabel = \"red:status\";\n\t\t\tgpios = <&gpio0 11 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&ethernet {\n\tmediatek,portmap = \"llllw\";\n};\n\n&uart {\n\tstatus = \"okay\";\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <50000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"jboot\";\n\t\t\t\treg = <0x0 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@10000 {\n\t\t\t\tlabel = \"recovery\";\n\t\t\t\treg = <0x10000 0x200000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@210000 {\n\t\t\t\tcompatible = \"openwrt,uimage\", \"denx,uimage\";\n\t\t\t\topenwrt,ih-magic = <IH_MAGIC_OKLI>;\n\t\t\t\topenwrt,offset = <0x10000>;\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x210000 0xde0000>;\n\t\t\t};\n\n\t\t\tconfig: partition@ff0000 {\n\t\t\t\tlabel = \"config\";\n\t\t\t\treg = <0xff0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&ehci {\n\tstatus = \"okay\";\n};\n\n&ohci {\n\tstatus = \"okay\";\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\tmt76x0e@0,0 {\n\t\treg = <0x0000 0 0 0 0>;\n\t\tnvmem-cells = <&macaddr_config_e490>;\n\t\tnvmem-cell-names = \"mac-address\";\n\t\tmac-address-increment = <(2)>;\n\t\tmediatek,mtd-eeprom = <&config 0xe05d>;\n\t};\n};\n\n&state_default {\n\tdefault {\n\t\tgroups = \"i2c\", \"uartf\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&config {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_config_e490: macaddr@e490 {\n\t\treg = <0xe490 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620a_dlink_dir-810l.dts",
    "content": "#include \"mt7620a_cameo_810.dtsi\"\n\n/ {\n\tcompatible = \"dlink,dir-810l\", \"ralink,mt7620a-soc\";\n\tmodel = \"D-Link DIR-810L\";\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620a_dlink_dwr-118-a1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7620a.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/mtd/partitions/uimage.h>\n\n/ {\n\tcompatible = \"dlink,dwr-118-a1\", \"ralink,mt7620a-soc\";\n\tmodel = \"D-Link DWR-118 A1\";\n\n\taliases {\n\t\tled-boot = &led_internet;\n\t\tled-failsafe = &led_internet;\n\t\tled-upgrade = &led_internet;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio0 12 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 13 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twan {\n\t\t\tlabel = \"green:wan\";\n\t\t\tgpios = <&gpio3 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_internet: internet {\n\t\t\tlabel = \"green:internet\";\n\t\t\tgpios = <&gpio2 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan {\n\t\t\tlabel = \"green:lan\";\n\t\t\tgpios = <&gpio2 1 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan2g {\n\t\t\tlabel = \"green:wlan2g\";\n\t\t\tgpios = <&gpio1 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tusb {\n\t\t\tlabel = \"green:usb\";\n\t\t\tgpios = <&gpio0 11 GPIO_ACTIVE_LOW>;\n\t\t\ttrigger-sources = <&ohci_port1>, <&ehci_port1>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\t};\n\n\tgpio_export {\n\t\tcompatible = \"gpio-export\";\n\t\t#size-cells = <0>;\n\n\t\tusb {\n\t\t\tgpio-export,name = \"usb\";\n\t\t\tgpio-export,output = <0>;\n\t\t\tgpios = <&gpio1 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&gpio1 {\n\tstatus = \"okay\";\n};\n\n&gpio2 {\n\tstatus = \"okay\";\n};\n\n&gpio3 {\n\tstatus = \"okay\";\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <80000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"jboot\";\n\t\t\t\treg = <0x0 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@10000 {\n\t\t\t\tcompatible = \"openwrt,uimage\", \"denx,uimage\";\n\t\t\t\topenwrt,ih-magic = <IH_MAGIC_OKLI>;\n\t\t\t\topenwrt,offset = <0x10000>;\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x10000 0xfe0000>;\n\t\t\t};\n\n\t\t\tconfig: partition@ff0000 {\n\t\t\t\tlabel = \"config\";\n\t\t\t\treg = <0xff0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&ehci {\n\tstatus = \"okay\";\n};\n\n&ohci {\n\tstatus = \"okay\";\n};\n\n&state_default {\n\tdefault {\n\t\tgroups = \"ephy\", \"uartf\", \"spi refclk\", \"wled\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\twifi@0,0 {\n\t\treg = <0x0000 0 0 0 0>;\n\t\tnvmem-cells = <&macaddr_config_e496>;\n\t\tnvmem-cell-names = \"mac-address\";\n\t\tmac-address-increment = <(2)>;\n\t\tmediatek,mtd-eeprom = <&config 0xe083>;\n\n\t\tled {\n\t\t\tled-sources = <0>;\n\t\t\tled-active-low;\n\t\t};\n\t};\n};\n\n&ethernet {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&rgmii1_pins &rgmii2_pins &mdio_pins>;\n\n\tport@4 {\n\t\tstatus = \"okay\";\n\t\tphy-handle = <&phy4>;\n\t\tphy-mode = \"rgmii\";\n\t};\n\n\tport@5 {\n\t\tstatus = \"okay\";\n\t\tphy-handle = <&phy5>;\n\t\tphy-mode = \"rgmii\";\n\t};\n\n\tmdio-bus {\n\t\tstatus = \"okay\";\n\n\t\tphy4: ethernet-phy@4 {\n\t\t\treg = <4>;\n\t\t\tphy-mode = \"rgmii-rxid\";\n\t\t};\n\n\t\tphy5: ethernet-phy@5 {\n\t\t\treg = <5>;\n\t\t\tphy-mode = \"rgmii-rxid\";\n\t\t};\n\t};\n};\n\n&gsw {\n\tmediatek,port4-gmac;\n\tmediatek,ephy-base = /bits/ 8 <8>;\n};\n\n&config {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_config_e496: macaddr@e496 {\n\t\treg = <0xe496 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620a_dlink_dwr-118-a2.dts",
    "content": "#include \"mt7620a.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/mtd/partitions/uimage.h>\n\n/ {\n\tcompatible = \"dlink,dwr-118-a2\", \"ralink,mt7620a-soc\";\n\tmodel = \"D-Link DWR-118 A2\";\n\n\taliases {\n\t\tled-boot = &led_internet;\n\t\tled-failsafe = &led_internet;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio0 12 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 13 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twan {\n\t\t\tlabel = \"green:wan\";\n\t\t\tgpios = <&gpio3 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_internet: internet {\n\t\t\tlabel = \"green:internet\";\n\t\t\tgpios = <&gpio2 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan {\n\t\t\tlabel = \"green:lan\";\n\t\t\tgpios = <&gpio2 1 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan2g {\n\t\t\tlabel = \"green:wlan2g\";\n\t\t\tgpios = <&gpio1 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tusb {\n\t\t\tlabel = \"green:usb\";\n\t\t\tgpios = <&gpio0 11 GPIO_ACTIVE_LOW>;\n\t\t\ttrigger-sources = <&ohci_port1>, <&ehci_port1>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\t};\n\n\tgpio_export {\n\t\tcompatible = \"gpio-export\";\n\t\t#size-cells = <0>;\n\n\t\tusb {\n\t\t\tgpio-export,name = \"usb\";\n\t\t\tgpio-export,output = <1>;\n\t\t\tgpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&gpio1 {\n\tstatus = \"okay\";\n};\n\n&gpio2 {\n\tstatus = \"okay\";\n};\n\n&gpio3 {\n\tstatus = \"okay\";\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <50000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"jboot\";\n\t\t\t\treg = <0x0 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@10000 {\n\t\t\t\tcompatible = \"openwrt,uimage\", \"denx,uimage\";\n\t\t\t\topenwrt,ih-magic = <IH_MAGIC_OKLI>;\n\t\t\t\topenwrt,offset = <0x10000>;\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x10000 0xfe0000>;\n\t\t\t};\n\n\t\t\tconfig: partition@ff0000 {\n\t\t\t\tlabel = \"config\";\n\t\t\t\treg = <0xff0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&ehci {\n\tstatus = \"okay\";\n};\n\n&ohci {\n\tstatus = \"okay\";\n};\n\n&state_default {\n\tdefault {\n\t\tgroups = \"ephy\", \"uartf\", \"spi refclk\", \"wled\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\twifi@0,0 {\n\t\treg = <0x0000 0 0 0 0>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\t\tnvmem-cells = <&macaddr_config_e4a8>;\n\t\tnvmem-cell-names = \"mac-address\";\n\t\tmac-address-increment = <(2)>;\n\n\t\tled {\n\t\t\tled-sources = <2>;\n\t\t\tled-active-low;\n\t\t};\n\t};\n};\n\n&ethernet {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&rgmii1_pins &mdio_pins>;\n\n\tmediatek,portmap = \"wllll\";\n\n\tport@4 {\n\t\tstatus = \"okay\";\n\t\tphy-handle = <&phy0>;\n\t\tphy-mode = \"rgmii\";\n\t};\n\n\tmdio-bus {\n\t\tstatus = \"okay\";\n\n\t\tphy0: ethernet-phy@0 {\n\t\t\treg = <0>;\n\t\t\tphy-mode = \"rgmii-rxid\";\n\t\t};\n\t};\n};\n\n&gsw {\n\tmediatek,port4-gmac;\n\tmediatek,ephy-base = /bits/ 8 <2>;\n};\n\n&config {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_config_e4a8: macaddr@e4a8 {\n\t\treg = <0xe4a8 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620a_dlink_dwr-960.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7620a_dlink_dwr-96x.dtsi\"\n\n/ {\n\tcompatible = \"dlink,dwr-960\", \"ralink,mt7620a-soc\";\n\tmodel = \"D-Link DWR-960\";\n};\n\n&ethernet {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&rgmii2_pins &mdio_pins>;\n\n\tmediatek,portmap = \"wllll\";\n\n\tport@5 {\n\t\tstatus = \"okay\";\n\t\tphy-mode = \"rgmii-txid\";\n\t\tphy-handle = <&phy7>;\n\t};\n\n\tmdio-bus {\n\t\tstatus = \"okay\";\n\n\t\tphy7: ethernet-phy@7 {\n\t\t\treg = <7>;\n\t\t\tphy-mode = \"rgmii-id\";\n\t\t};\n\t};\n};\n\n&wifi {\n\tmediatek,mtd-eeprom = <&config 0xe08e>;\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620a_dlink_dwr-961-a1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later\n/*\n * D-Link DWR-961 A1 Board Description\n * Copyright 2022 Pawel Dembicki <paweldembicki@gmail.com>\n */\n#include \"mt7620a_dlink_dwr-96x.dtsi\"\n\n/ {\n\tcompatible = \"dlink,dwr-961-a1\", \"ralink,mt7620a-soc\";\n\tmodel = \"D-Link DWR-961 A1\";\n\n\tleds {\n\t\thidden-1 { /* hidden next to wlan5g led */\n\t\t\tlabel = \"green:hidden-1\";\n\t\t\tgpios = <&gpio0 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\thidden-2 { /* hidden next to sms led*/\n\t\t\tlabel = \"green:hidden-2\";\n\t\t\tgpios = <&gpio0 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&ethernet {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&rgmii1_pins &mdio_pins>;\n\n\tport@5 {\n\t\tstatus = \"okay\";\n\t\tphy-mode = \"rgmii\";\n\t\tmediatek,fixed-link = <1000 1 1 1>;\n\t};\n\n\tmdio-bus {\n\t\tstatus = \"okay\";\n\n\t\tethernet-phy@0 {\n\t\t\treg = <0>;\n\t\t\tphy-mode = \"rgmii\";\n\t\t\tqca,ar8327-initvals = <\n\t\t\t\t0x04 0x87300000 /* PORT0 PAD MODE CTRL */\n\t\t\t\t0x0c 0x00000000 /* PORT6 PAD MODE CTRL */\n\t\t\t\t0x7c 0x0000007e /* PORT0_STATUS */\n\t\t\t\t0x80 0x00001200 /* PORT1_STATUS */\n\t\t\t\t0x84 0x00001200 /* PORT2_STATUS */\n\t\t\t\t0x88 0x00001200 /* PORT3_STATUS */\n\t\t\t\t0x8c 0x00001200 /* PORT4_STATUS */\n\t\t\t\t0x90 0x00001200 /* PORT5_STATUS */\n\t\t\t\t0x94 0x00000000 /* PORT6_STATUS */\n\t\t\t>;\n\t\t};\n\t};\n};\n\n&gsw {\n\tmediatek,ephy-base = /bits/ 8 <8>;\n};\n\n&wifi {\n\tmediatek,mtd-eeprom = <&config 0xe29e>;\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620a_dlink_dwr-96x.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later\n/*\n * D-Link DWR-96x Common Board Description\n * Copyright 2022 Pawel Dembicki <paweldembicki@gmail.com>\n */\n#include \"mt7620a.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/mtd/partitions/uimage.h>\n\n/ {\n\taliases {\n\t\tled-boot = &led_status;\n\t\tled-failsafe = &led_status;\n\t\tled-running = &led_status;\n\t\tled-upgrade = &led_status;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 1 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio0 2 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_status: status {\n\t\t\tlabel = \"green:status\";\n\t\t\tgpios = <&gpio0 7 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twan {\n\t\t\tlabel = \"green:wan\";\n\t\t\tgpios = <&gpio0 11 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan {\n\t\t\tlabel = \"green:lan\";\n\t\t\tgpios = <&gpio0 12 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tsms {\n\t\t\tlabel = \"green:sms\";\n\t\t\tgpios = <&gpio1 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tsignal_green {\n\t\t\tlabel = \"green:signal\";\n\t\t\tgpios = <&gpio2 0 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tsignal_red {\n\t\t\tlabel = \"red:signal\";\n\t\t\tgpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\t4g {\n\t\t\tlabel = \"green:4g\";\n\t\t\tgpios = <&gpio2 2 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\t3g {\n\t\t\tlabel = \"green:3g\";\n\t\t\tgpios = <&gpio2 3 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan5g {\n\t\t\tlabel = \"green:wlan5g\";\n\t\t\tgpios = <&gpio2 4 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\twlan2g {\n\t\t\tlabel = \"green:wlan2g\";\n\t\t\tgpios = <&gpio3 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\t};\n};\n\n&ehci {\n\tstatus = \"okay\";\n};\n\n&gpio1 {\n\tstatus = \"okay\";\n};\n\n&gpio2 {\n\tstatus = \"okay\";\n};\n\n&gpio3 {\n\tstatus = \"okay\";\n};\n\n&ohci {\n\tstatus = \"okay\";\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\twifi: wifi@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\t\tnvmem-cells = <&macaddr_config_e50e>;\n\t\tnvmem-cell-names = \"mac-address\";\n\t\tmac-address-increment = <(2)>;\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <50000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"jboot\";\n\t\t\t\treg = <0x0 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@10000 {\n\t\t\t\tcompatible = \"openwrt,uimage\", \"denx,uimage\";\n\t\t\t\topenwrt,ih-magic = <IH_MAGIC_OKLI>;\n\t\t\t\topenwrt,offset = <0x10000>;\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x10000 0xfe0000>;\n\t\t\t};\n\n\t\t\tconfig: partition@ff0000 {\n\t\t\t\tcompatible = \"nvmem-cells\";\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\n\t\t\t\tlabel = \"config\";\n\t\t\t\treg = <0xff0000 0x10000>;\n\t\t\t\tread-only;\n\n\t\t\t\tmacaddr_config_e50e: macaddr@e50e {\n\t\t\t\t\treg = <0xe50e 0x6>;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t};\n};\n\n&state_default {\n\tdefault {\n\t\tgroups = \"i2c\", \"wled\", \"spi refclk\", \"uartf\", \"ephy\";\n\t\tfunction = \"gpio\";\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620a_domywifi.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7620a.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\taliases {\n\t\tled-boot = &led_system_amber;\n\t\tled-failsafe = &led_system_amber;\n\t\tled-running = &led_system_green;\n\t\tled-upgrade = &led_system_amber;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 13 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_system_green: system_green {\n\t\t\tlabel = \"green:system\";\n\t\t\tgpios = <&gpio1 6 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_system_amber: system_amber {\n\t\t\tlabel = \"amber:system\";\n\t\t\tgpios = <&gpio1 2 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tinternet_green {\n\t\t\tlabel = \"green:internet\";\n\t\t\tgpios = <&gpio1 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tinternet_amber {\n\t\t\tlabel = \"amber:internet\";\n\t\t\tgpios = <&gpio1 5 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan1 {\n\t\t\tlabel = \"amber:lan1\";\n\t\t\tgpios = <&gpio1 3 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan2 {\n\t\t\tlabel = \"amber:lan2\";\n\t\t\tgpios = <&gpio1 1 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan3 {\n\t\t\tlabel = \"amber:lan3\";\n\t\t\tgpios = <&gpio1 4 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan4 {\n\t\t\tlabel = \"amber:lan4\";\n\t\t\tgpios = <&gpio1 9 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twan {\n\t\t\tlabel = \"amber:wan\";\n\t\t\tgpios = <&gpio1 7 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan2g {\n\t\t\tlabel = \"green:wlan2g\";\n\t\t\tgpios = <&gpio3 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\t};\n};\n\n&gpio1 {\n\tstatus = \"okay\";\n};\n\n&gpio3 {\n\tstatus = \"okay\";\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <80000000>;\n\t\tm25p,fast-read;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"bootloader\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"config\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0xfb0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"uartf\", \"rgmii1\", \"wled\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&ephy_pins>;\n\n\tmediatek,portmap = \"wllll\";\n\n\tnvmem-cells = <&macaddr_factory_28>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&sdhci {\n\tstatus = \"okay\";\n};\n\n&ehci {\n\tstatus = \"okay\";\n};\n\n&ohci {\n\tstatus = \"okay\";\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\twifi@0,0 {\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\n\t\tled {\n\t\t\tled-sources = <0>;\n\t\t\tled-active-low;\n\t\t};\n\t};\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_28: macaddr@28 {\n\t\treg = <0x28 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620a_domywifi_dm202.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7620a_domywifi.dtsi\"\n\n/ {\n\tcompatible = \"domywifi,dm202\", \"ralink,mt7620a-soc\";\n\tmodel = \"DomyWifi DM202\";\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620a_domywifi_dm203.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7620a_domywifi.dtsi\"\n\n/ {\n\tcompatible = \"domywifi,dm203\", \"ralink,mt7620a-soc\";\n\tmodel = \"DomyWifi DM203\";\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620a_domywifi_dw22d.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7620a_domywifi.dtsi\"\n\n/ {\n\tcompatible = \"domywifi,dw22d\", \"ralink,mt7620a-soc\";\n\tmodel = \"DomyWifi DW22D\";\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620a_dovado_tiny-ac.dts",
    "content": "#include \"mt7620a.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"dovado,tiny-ac\", \"ralink,mt7620a-soc\";\n\tmodel = \"Dovado Tiny AC\";\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tusb {\n\t\t\tlabel = \"green:usb\";\n\t\t\tgpios = <&gpio0 11 GPIO_ACTIVE_LOW>;\n\t\t\ttrigger-sources = <&ohci_port1>, <&ehci_port1>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\n\t\twifi {\n\t\t\tlabel = \"orange:wifi\";\n\t\t\tgpios = <&gpio3 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 13 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tgpio_export {\n\t\tcompatible = \"gpio-export\";\n\t\t#size-cells = <0>;\n\n\t\tusbpower {\n\t\t\tgpio-export,name = \"usbpower\";\n\t\t\tgpio-export,output = <1>;\n\t\t\tgpios = <&gpio2 5 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&gpio2 {\n\tstatus = \"okay\";\n};\n\n&gpio3 {\n\tstatus = \"okay\";\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x7b0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&ehci {\n\tstatus = \"okay\";\n};\n\n&ohci {\n\tstatus = \"okay\";\n};\n\n&ethernet {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&rgmii1_pins &rgmii2_pins &mdio_pins>;\n\n\tmediatek,portmap = \"llllw\";\n\n\tport@4 {\n\t\tstatus = \"okay\";\n\t\tphy-mode = \"rgmii\";\n\t\tphy-handle = <&phy4>;\n\t};\n\n\tport@5 {\n\t\tstatus = \"okay\";\n\t\tphy-mode = \"rgmii\";\n\t\tphy-handle = <&phy5>;\n\t};\n\n\tmdio-bus {\n\t\tstatus = \"okay\";\n\n\t\tphy4: ethernet-phy@4 {\n\t\t\treg = <4>;\n\t\t\tphy-mode = \"rgmii\";\n\t\t};\n\n\t\tphy5: ethernet-phy@5 {\n\t\t\treg = <5>;\n\t\t\tphy-mode = \"rgmii\";\n\t\t};\n\t};\n};\n\n&gsw {\n\tmediatek,port4-gmac;\n\tmediatek,ephy-base = /bits/ 8 <8>;\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"uartf\", \"nd_sd\", \"wled\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&pcie0 {\n\tmt76@0,0 {\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620a_edimax_br-6478ac-v2.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-only\n/*\n * Copyright (C) 2016 Rohan Murch <rohan.murch@gmail.com>\n * Copyright (C) 2016 Hans Ulli Kroll <ulli.kroll@googlemail.com>\n * Copyright (C) 2017 James McKenzie <openwrt@madingley.org>\n */\n\n#include \"mt7620a.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/mtd/partitions/uimage.h>\n\n/ {\n\tcompatible = \"edimax,br-6478ac-v2\", \"ralink,mt7620a-soc\";\n\tmodel = \"Edimax BR-6478AC v2\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset_wps {\n\t\t\tlabel = \"reset_wps\";\n\t\t\tgpios = <&gpio0 2 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"white:power\";\n\t\t\tgpios = <&gpio0 11 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tinternet {\n\t\t\tlabel = \"blue:internet\";\n\t\t\tgpios = <&gpio0 7 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan {\n\t\t\tlabel = \"blue:wlan\";\n\t\t\tgpios = <&gpio0 10 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tusb {\n\t\t\tlabel = \"blue:usb\";\n\t\t\tgpios = <&gpio0 14 GPIO_ACTIVE_LOW>;\n\t\t\ttrigger-sources = <&ohci_port1>, <&ehci_port1>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\t};\n\n\tgpio_export {\n\t\tcompatible = \"gpio-export\";\n\t\t#size-cells = <0>;\n\t\tusb-power {\n\t\t\tgpio-export,name=\"usb-power\";\n\t\t\tgpio-export,output=<1>;\n\t\t\tgpios = <&gpio2 5 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&gpio2 {\n\tstatus = \"okay\";\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tlabel = \"cimage\";\n\t\t\t\treg = <0x50000 0x20000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@70000 {\n\t\t\t\tcompatible = \"openwrt,uimage\", \"denx,uimage\";\n\t\t\t\topenwrt,offset = <FW_EDIMAX_OFFSET>;\n\t\t\t\topenwrt,partition-magic = <FW_MAGIC_EDIMAX>;\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x00070000 0x00790000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"uartf\", \"nd_sd\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&rgmii1_pins &rgmii2_pins &mdio_pins>;\n\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tmediatek,portmap = \"wllll\";\n\n\tport@5 {\n\t\tstatus = \"okay\";\n\t\tmediatek,fixed-link = <1000 1 1 1>;\n\t\tphy-mode = \"rgmii\";\n\t};\n\n\tmdio-bus {\n\t\tstatus = \"okay\";\n\n\t\tphy0: ethernet-phy@0 {\n\t\t\treg = <0>;\n\t\t\tphy-mode = \"rgmii\";\n\t\t};\n\n\t\tphy1: ethernet-phy@1 {\n\t\t\treg = <1>;\n\t\t\tphy-mode = \"rgmii\";\n\t\t};\n\n\t\tphy2: ethernet-phy@2 {\n\t\t\treg = <2>;\n\t\t\tphy-mode = \"rgmii\";\n\t\t};\n\n\t\tphy3: ethernet-phy@3 {\n\t\t\treg = <3>;\n\t\t\tphy-mode = \"rgmii\";\n\t\t};\n\n\t\tphy4: ethernet-phy@4 {\n\t\t\treg = <4>;\n\t\t\tphy-mode = \"rgmii\";\n\t\t};\n\n\t\tphy1f: ethernet-phy@1f {\n\t\t\treg = <0x1f>;\n\t\t\tphy-mode = \"rgmii\";\n\t\t};\n\t};\n};\n\n&gsw {\n\tmediatek,ephy-base = /bits/ 8 <12>;\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\twifi@0,0 {\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t\tmediatek,2ghz = <0>;\n\t};\n};\n\n&ehci {\n\tstatus = \"okay\";\n};\n\n&ohci {\n\tstatus = \"okay\";\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620a_edimax_ew-7476rpc.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7620a_edimax_ew-747x.dtsi\"\n\n/ {\n\tcompatible = \"edimax,ew-7476rpc\", \"ralink,mt7620a-soc\";\n\tmodel = \"Edimax EW-7476RPC\";\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620a_edimax_ew-7478ac.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7620a_edimax_ew-747x.dtsi\"\n\n/ {\n\tcompatible = \"edimax,ew-7478ac\", \"ralink,mt7620a-soc\";\n\tmodel = \"Edimax EW-7478AC\";\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620a_edimax_ew-7478apc.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7620a.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/mtd/partitions/uimage.h>\n\n/ {\n\tcompatible = \"edimax,ew-7478apc\", \"ralink,mt7620a-soc\";\n\tmodel = \"Edimax EW-7478APC\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset_wps {\n\t\t\tlabel = \"reset_wps\";\n\t\t\tgpios = <&gpio0 2 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"white:power\";\n\t\t\tgpios = <&gpio0 11 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tinternet {\n\t\t\tlabel = \"blue:internet\";\n\t\t\tgpios = <&gpio0 7 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan {\n\t\t\tlabel = \"blue:wlan\";\n\t\t\tgpios = <&gpio0 10 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tusb {\n\t\t\tlabel = \"blue:usb\";\n\t\t\tgpios = <&gpio0 14 GPIO_ACTIVE_LOW>;\n\t\t\ttrigger-sources = <&ohci_port1>, <&ehci_port1>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\t};\n};\n\n&gpio2 {\n\tstatus = \"okay\";\n\n\tenable_usb_power {\n\t\tgpio-hog;\n\t\tline-name = \"enable USB power\";\n\t\tgpios = <5 GPIO_ACTIVE_HIGH>;\n\t\toutput-high;\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tlabel = \"cimage\";\n\t\t\t\treg = <0x50000 0x20000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@70000 {\n\t\t\t\tcompatible = \"openwrt,uimage\", \"denx,uimage\";\n\t\t\t\topenwrt,offset = <FW_EDIMAX_OFFSET>;\n\t\t\t\topenwrt,partition-magic = <FW_MAGIC_EDIMAX>;\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x00070000 0x00790000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"uartf\", \"nd_sd\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&rgmii1_pins &rgmii2_pins &mdio_pins>;\n\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tmediatek,portmap = \"wllll\";\n\n\tport@5 {\n\t\tstatus = \"okay\";\n\t\tmediatek,fixed-link = <1000 1 1 1>;\n\t\tphy-mode = \"rgmii\";\n\t};\n\n\tmdio-bus {\n\t\tstatus = \"okay\";\n\n\t\tphy0: ethernet-phy@0 {\n\t\t\treg = <0>;\n\t\t\tphy-mode = \"rgmii\";\n\t\t};\n\n\t\tphy1: ethernet-phy@1 {\n\t\t\treg = <1>;\n\t\t\tphy-mode = \"rgmii\";\n\t\t};\n\n\t\tphy2: ethernet-phy@2 {\n\t\t\treg = <2>;\n\t\t\tphy-mode = \"rgmii\";\n\t\t};\n\n\t\tphy3: ethernet-phy@3 {\n\t\t\treg = <3>;\n\t\t\tphy-mode = \"rgmii\";\n\t\t};\n\n\t\tphy4: ethernet-phy@4 {\n\t\t\treg = <4>;\n\t\t\tphy-mode = \"rgmii\";\n\t\t};\n\n\t\tphy1f: ethernet-phy@1f {\n\t\t\treg = <0x1f>;\n\t\t\tphy-mode = \"rgmii\";\n\t\t};\n\t};\n};\n\n&gsw {\n\tmediatek,ephy-base = /bits/ 8 <12>;\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\twifi@0,0 {\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t\tmediatek,2ghz = <0>;\n\t};\n};\n\n&ehci {\n\tstatus = \"okay\";\n};\n\n&ohci {\n\tstatus = \"okay\";\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620a_edimax_ew-747x.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7620a.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/mtd/partitions/uimage.h>\n\n/ {\n\tcompatible = \"ralink,mt7620a-soc\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset_wps {\n\t\t\tlabel = \"reset_wps\";\n\t\t\tgpios = <&gpio2 20 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\tswitch_high {\n\t\t\tlabel = \"switch high\";\n\t\t\tgpios = <&gpio2 22 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_0>;\n\t\t\tlinux,input-type = <EV_SW>;\n\t\t};\n\n\t\tswitch_off {\n\t\t\tlabel = \"switch off\";\n\t\t\tgpios = <&gpio2 23 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_1>;\n\t\t\tlinux,input-type = <EV_SW>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio2 27 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan {\n\t\t\tlabel = \"green:lan\";\n\t\t\tgpios = <&gpio2 26 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan2g {\n\t\t\tlabel = \"blue:wlan2g\";\n\t\t\tgpios = <&gpio2 30 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1radio\";\n\t\t};\n\n\t\twlan5g {\n\t\t\tlabel = \"blue:wlan5g\";\n\t\t\tgpios = <&gpio2 31 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0radio\";\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&gpio2 28 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tcrossband {\n\t\t\tlabel = \"green:crossband\";\n\t\t\tgpios = <&gpio2 29 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&gpio1 {\n\tstatus = \"okay\";\n};\n\n&gpio2 {\n\tstatus = \"okay\";\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tlabel = \"cimage\";\n\t\t\t\treg = <0x50000 0x20000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@70000 {\n\t\t\t\tcompatible = \"openwrt,uimage\", \"denx,uimage\";\n\t\t\t\topenwrt,offset = <FW_EDIMAX_OFFSET>;\n\t\t\t\topenwrt,partition-magic = <FW_MAGIC_EDIMAX>;\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x00070000 0x00790000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"uartf\", \"nd_sd\", \"rgmii2\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&pinctrl {\n\tphy_reset_pins: phy-reset {\n\t\tgpio {\n\t\t\tgroups = \"spi refclk\";\n\t\t\tfunction = \"gpio\";\n\t\t};\n\t};\n};\n\n&ethernet {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&rgmii1_pins &mdio_pins &phy_reset_pins>;\n\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tphy-reset-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;\n\tphy-reset-duration = <30>;\n\n\tport@5 {\n\t\tstatus = \"okay\";\n\t\tmediatek,fixed-link = <1000 1 1 1>;\n\t\tphy-mode = \"rgmii\";\n\t};\n\n\tmdio-bus {\n\t\tstatus = \"okay\";\n\n\t\tphy0: ethernet-phy@0 {\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <0>;\n\t\t\tphy-mode = \"rgmii\";\n\t\t};\n\n\t\tphy1: ethernet-phy@1 {\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <1>;\n\t\t\tphy-mode = \"rgmii\";\n\t\t};\n\n\t\tphy2: ethernet-phy@2 {\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <2>;\n\t\t\tphy-mode = \"rgmii\";\n\t\t};\n\n\t\tphy3: ethernet-phy@3 {\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <3>;\n\t\t\tphy-mode = \"rgmii\";\n\t\t};\n\n\t\tphy4: ethernet-phy@4 {\n\t\t\tstatus = \"disabled\";\n\t\t\treg = <4>;\n\t\t\tphy-mode = \"rgmii\";\n\t\t};\n\t};\n};\n\n&gsw {\n\tmediatek,ephy-base = /bits/ 8 <8>;\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\twifi@0,0 {\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t\tmediatek,2ghz = <0>;\n\t};\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620a_engenius_esr600.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7620a.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"engenius,esr600\", \"ralink,mt7620a-soc\";\n\tmodel = \"EnGenius ESR600\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200\";\n\t};\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"amber:power\";\n\t\t\tgpios = <&gpio0 9 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twps2g {\n\t\t\tlabel = \"amber:wps2g\";\n\t\t\tgpios = <&gpio2 6 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan5g {\n\t\t\tlabel = \"blue:wlan5g\";\n\t\t\tgpios = <&gpio0 7 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan2g {\n\t\t\tlabel = \"blue:wlan2g\";\n\t\t\tgpios = <&gpio3 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 1 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio0 2 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n};\n\n&gpio2 {\n\tstatus = \"okay\";\n};\n\n&gpio3 {\n\tstatus = \"okay\";\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <50000000>;\n\t\tm25p,fast-read;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tiNIC_rf: partition@50000 {\n\t\t\t\tlabel = \"iNIC_rf\";\n\t\t\t\treg = <0x50000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@60000 {\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x60000 0xf40000>;\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t};\n\n\t\t\tpartition@fa0000 {\n\t\t\t\tlabel = \"backup\";\n\t\t\t\treg = <0xfa0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@fb0000 {\n\t\t\t\tlabel = \"storage\";\n\t\t\t\treg = <0xfb0000 0x50000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&ethernet {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&rgmii1_pins &mdio_pins>;\n\n\tnvmem-cells = <&macaddr_iNIC_rf_4>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tport@5 {\n\t\tstatus = \"okay\";\n\t\tphy-mode = \"rgmii\";\n\t\tmediatek,fixed-link = <1000 1 1 1>;\n\t};\n\n\tmdio-bus {\n\t\tstatus = \"okay\";\n\n\t\tethernet-phy@0 {\n\t\t\treg = <0>;\n\t\t\tphy-mode = \"rgmii\";\n\t\t\tqca,ar8327-initvals = <\n\t\t\t\t0x10 0x40000000 /* POWER-ON STRAPPING */\n\t\t\t\t0x04 0x07600000 /* PORT0 PAD MODE CTRL */\n\t\t\t\t0x7c 0x0000007e /* PORT0 STATUS */\n\t\t\t\t0x0c 0x05600000 /* PORT6 PAD MODE CTRL */\n\t\t\t\t0x94 0x0000007e /* PORT6 STATUS */\n\t\t\t>;\n\t\t};\n\t};\n};\n\n&gsw {\n\tmediatek,ephy-base = /bits/ 8 <8>;\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"uartf\", \"nd_sd\", \"wled\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\twifi@0,0 {\n\t\tcompatible = \"pci1814,5592\";\n\t\treg = <0x0 0 0 0 0>;\n\t\tralink,mtd-eeprom = <&factory 0x0>;\n\t};\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&iNIC_rf 0x0>;\n};\n\n&ehci {\n\tstatus = \"okay\";\n};\n\n&ohci {\n\tstatus = \"okay\";\n};\n\n&iNIC_rf {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_iNIC_rf_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620a_fon_fon2601.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-only\n\n#include \"mt7620a.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"fon,fon2601\", \"ralink,mt7620a-soc\";\n\tmodel = \"Fon FON2601\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power_r {\n\t\t\tlabel = \"red:power\";\n\t\t\tgpios = <&gpio0 9 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tinternet_g {\n\t\t\tlabel = \"green:internet\";\n\t\t\tgpios = <&gpio0 10 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tnet_g {\n\t\t\tlabel = \"green:net\";\n\t\t\tgpios = <&gpio0 12 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twifi_g {\n\t\t\tlabel = \"green:wifi\";\n\t\t\tgpios = <&gpio0 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 2 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"openwrt,uimage\", \"denx,uimage\";\n\t\t\t\topenwrt,padding = <32>;\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0xf90000>;\n\t\t\t};\n\n\t\t\tpartition@fe0000 {\n\t\t\t\tlabel = \"board_data\";\n\t\t\t\treg = <0xfe0000 0x20000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"uartf\";\n\t\tfunction = \"gpio\";\n\t};\n\tnd_sd {\n\t\tgroups = \"nd_sd\";\n\t\tfunction = \"sd\";\n\t};\n\tspi_cs {\n\t\tgroups = \"spi refclk\";\n\t\tfunction = \"spi refclk\";\n\t};\n};\n\n&ethernet {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&rgmii2_pins &mdio_pins>;\n\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tport@4 {\n\t\tstatus = \"okay\";\n\t\tphy-handle = <&phy4>;\n\t\tphy-mode = \"rgmii\";\n\t};\n\n\tmdio-bus {\n\t\tstatus = \"okay\";\n\n\t\tphy4: ethernet-phy@4 {\n\t\t\treg = <4>;\n\t\t\tphy-mode = \"rgmii\";\n\t\t};\n\t};\n};\n\n&gsw {\n\tmediatek,port4-gmac;\n\tmediatek,ephy-base = /bits/ 8 <8>;\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pa_pins>, <&wled_pins>;\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n&pcie0 {\n\twifi@0,0 {\n\t\tcompatible = \"pci14c3,7662\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\t};\n};\n\n&ehci {\n\tstatus = \"okay\";\n};\n\n&ohci {\n\tstatus = \"okay\";\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620a_glinet_gl-mt300a.dts",
    "content": "#include \"mt7620a.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"glinet,gl-mt300a\", \"ralink,mt7620a-soc\";\n\tmodel = \"GL-MT300A\";\n\n\taliases {\n\t\tlabel-mac-device = &wmac;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200\";\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twan {\n\t\t\tlabel = \"gl-mt300a:wan\";\n\t\t\tgpios = <&gpio2 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan {\n\t\t\tlabel = \"gl-mt300a:lan\";\n\t\t\tgpios = <&gpio2 1 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan {\n\t\t\tlabel = \"gl-mt300a:wlan\";\n\t\t\tgpios = <&gpio3 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tusb {\n\t\t\tlabel = \"gl-mt300a:usb\";\n\t\t\tgpios = <&gpio0 7 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 13 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\tBTN_0 {\n\t\t\tlabel = \"BTN_0\";\n\t\t\tgpios = <&gpio0 1 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_0>;\n\t\t};\n\n\t\tBTN_1 {\n\t\t\tlabel = \"BTN_1\";\n\t\t\tgpios = <&gpio0 2 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_1>;\n\t\t};\n\t};\n};\n\n&gpio2 {\n\tstatus = \"okay\";\n};\n\n&gpio3 {\n\tstatus = \"okay\";\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0xf80000>;\n\t\t\t};\n\n\t\t\tpartition@ff0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0xff0000 0x10000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&sdhci {\n\tstatus = \"okay\";\n};\n\n&ehci {\n\tstatus = \"okay\";\n};\n\n&ohci {\n\tstatus = \"okay\";\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_4000>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tmediatek,portmap = \"wllll\";\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"wled\",\"ephy\",\"uartf\",\"i2c\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4000: macaddr@4000 {\n\t\treg = <0x4000 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620a_glinet_gl-mt300n.dts",
    "content": "#include \"mt7620a.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"glinet,gl-mt300n\", \"ralink,mt7620a-soc\";\n\tmodel = \"GL-MT300N\";\n\n\taliases {\n\t\tlabel-mac-device = &wmac;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200\";\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twan {\n\t\t\tlabel = \"gl-mt300n:wan\";\n\t\t\tgpios = <&gpio2 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan {\n\t\t\tlabel = \"gl-mt300n:lan\";\n\t\t\tgpios = <&gpio2 1 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan {\n\t\t\tlabel = \"gl-mt300n:wlan\";\n\t\t\tgpios = <&gpio3 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 1 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\tBTN_0 {\n\t\t\tlabel = \"BTN_0\";\n\t\t\tgpios = <&gpio2 2 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_0>;\n\t\t};\n\n\t\tBTN_1 {\n\t\t\tlabel = \"BTN_1\";\n\t\t\tgpios = <&gpio2 3 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_1>;\n\t\t};\n\t};\n};\n\n&gpio2 {\n\tstatus = \"okay\";\n};\n\n&gpio3 {\n\tstatus = \"okay\";\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0xf80000>;\n\t\t\t};\n\n\t\t\tpartition@ff0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0xff0000 0x10000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&ehci {\n\tstatus = \"okay\";\n};\n\n&ohci {\n\tstatus = \"okay\";\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_4000>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tmediatek,portmap = \"wllll\";\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"wled\",\"ephy\",\"i2c\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4000: macaddr@4000 {\n\t\treg = <0x4000 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620a_glinet_gl-mt750.dts",
    "content": "#include \"mt7620a.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"glinet,gl-mt750\", \"ralink,mt7620a-soc\";\n\tmodel = \"GL-MT750\";\n\n\taliases {\n\t\tlabel-mac-device = &wmac;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200\";\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twan {\n\t\t\tlabel = \"gl-mt750:wan\";\n\t\t\tgpios = <&gpio2 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan {\n\t\t\tlabel = \"gl-mt750:lan\";\n\t\t\tgpios = <&gpio2 1 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan {\n\t\t\tlabel = \"gl-mt750:wlan\";\n\t\t\tgpios = <&gpio3 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 13 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\tBTN_0 {\n\t\t\tlabel = \"BTN_0\";\n\t\t\tgpios = <&gpio2 2 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_0>;\n\t\t};\n\n\t\tBTN_1 {\n\t\t\tlabel = \"BTN_1\";\n\t\t\tgpios = <&gpio2 3 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_1>;\n\t\t};\n\t};\n};\n\n&gpio2 {\n\tstatus = \"okay\";\n};\n\n&gpio3 {\n\tstatus = \"okay\";\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0xf80000>;\n\t\t\t};\n\n\t\t\tpartition@ff0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0xff0000 0x10000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&sdhci {\n\tstatus = \"okay\";\n};\n\n&ehci {\n\tstatus = \"okay\";\n};\n\n&ohci {\n\tstatus = \"okay\";\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_4000>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tmediatek,portmap = \"wllll\";\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\tmt76@0,0 {\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"wled\",\"ephy\",\"uartf\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4000: macaddr@4000 {\n\t\treg = <0x4000 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620a_head-weblink_hdrm200.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7620a.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"head-weblink,hdrm200\", \"ralink,mt7620a-soc\";\n\tmodel = \"Head Weblink HDRM200\";\n\n\taliases {\n\t\tled-boot = &led_system;\n\t\tled-failsafe = &led_system;\n\t\tled-running = &led_system;\n\t\tled-upgrade = &led_system;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyS1,57600\";\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\trssi {\n\t\t\tlabel = \"red:rssi\";\n\t\t\tgpios = <&gpio0 19 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_system: system {\n\t\t\tlabel = \"green:system\";\n\t\t\tgpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tair {\n\t\t\tlabel = \"green:wifi\";\n\t\t\tgpios = <&gpio3 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio0 12 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 13 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfirmware: partition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0xfb0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&gpio1 {\n\tstatus = \"okay\";\n};\n\n&gpio3 {\n\tstatus = \"okay\";\n};\n\n&sdhci {\n\tstatus = \"okay\";\n};\n\n&ehci {\n\tstatus = \"okay\";\n};\n\n&ohci {\n\tstatus = \"okay\";\n};\n\n&ethernet {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&rgmii1_pins &rgmii2_pins &mdio_pins>;\n\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tport@4 {\n\t\tstatus = \"okay\";\n\t\tphy-handle = <&phy4>;\n\t\tphy-mode = \"rgmii\";\n\t};\n\n\tport@5 {\n\t\tstatus = \"okay\";\n\t\tphy-handle = <&phy5>;\n\t\tphy-mode = \"rgmii\";\n\t};\n\n\tmdio-bus {\n\t\tstatus = \"okay\";\n\n\t\tphy4: ethernet-phy@4 {\n\t\t\treg = <4>;\n\t\t\tphy-mode = \"rgmii\";\n\t\t};\n\n\t\tphy5: ethernet-phy@5 {\n\t\t\treg = <5>;\n\t\t\tphy-mode = \"rgmii\";\n\t\t};\n\t};\n};\n\n&gsw {\n\tmediatek,port4-gmac;\n\tmediatek,ephy-base = /bits/ 8 <8>;\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&state_default {\n\tdefault {\n\t\tgroups = \"i2c\", \"uartf\", \"pa\", \"spi refclk\",\n\t\t\t       \"wled\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\twifi@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\t};\n};\n\n&uart {\n\tstatus = \"okay\";\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620a_hiwifi_hc5661.dts",
    "content": "#include \"mt7620a_hiwifi_hc5x61.dtsi\"\n\n/ {\n\tcompatible = \"hiwifi,hc5661\", \"hiwifi,hc5x61\", \"ralink,mt7620a-soc\";\n\tmodel = \"HiWiFi HC5661\";\n\n\taliases {\n\t\tled-boot = &led_system;\n\t\tled-failsafe = &led_system;\n\t\tled-running = &led_system;\n\t\tled-upgrade = &led_system;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_system: system {\n\t\t\tlabel = \"blue:system\";\n\t\t\tgpios = <&gpio0 9 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tinternet {\n\t\t\tlabel = \"blue:internet\";\n\t\t\tgpios = <&gpio0 11 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan2g {\n\t\t\tlabel = \"blue:wlan2g\";\n\t\t\tgpios = <&gpio3 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620a_hiwifi_hc5761.dts",
    "content": "#include \"mt7620a_hiwifi_hc5x61.dtsi\"\n\n/ {\n\tcompatible = \"hiwifi,hc5761\", \"hiwifi,hc5x61\", \"ralink,mt7620a-soc\";\n\tmodel = \"HiWiFi HC5761\";\n\n\taliases {\n\t\tled-boot = &led_system;\n\t\tled-failsafe = &led_system;\n\t\tled-running = &led_system;\n\t\tled-upgrade = &led_system;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_system: system {\n\t\t\tlabel = \"blue:system\";\n\t\t\tgpios = <&gpio0 9 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tinternet {\n\t\t\tlabel = \"blue:internet\";\n\t\t\tgpios = <&gpio0 11 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan2g {\n\t\t\tlabel = \"blue:wlan2g\";\n\t\t\tgpios = <&gpio3 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\n\t\twlan5g {\n\t\t\tlabel = \"blue:wlan5g\";\n\t\t\tgpios = <&gpio0 7 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\t};\n\n\tgpio_export {\n\t\tcompatible = \"gpio-export\";\n\t\t#size-cells = <0>;\n\n\t\tusbpower {\n\t\t\tgpio-export,name = \"usbpower\";\n\t\t\tgpio-export,output = <1>;\n\t\t\tgpios = <&gpio0 13 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&ehci {\n\tstatus = \"okay\";\n};\n\n&ohci {\n\tstatus = \"okay\";\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\tmt76@0,0 {\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620a_hiwifi_hc5861.dts",
    "content": "#include \"mt7620a_hiwifi_hc5x61.dtsi\"\n\n/ {\n\tcompatible = \"hiwifi,hc5861\", \"hiwifi,hc5x61\", \"ralink,mt7620a-soc\";\n\tmodel = \"HiWiFi HC5861\";\n\n\taliases {\n\t\tled-boot = &led_system;\n\t\tled-failsafe = &led_system;\n\t\tled-running = &led_system;\n\t\tled-upgrade = &led_system;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_system: system {\n\t\t\tlabel = \"blue:system\";\n\t\t\tgpios = <&gpio0 9 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan2g {\n\t\t\tlabel = \"blue:wlan2g\";\n\t\t\tgpios = <&gpio0 11 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\n\t\tinternet {\n\t\t\tlabel = \"blue:internet\";\n\t\t\tgpios = <&gpio3 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan5g {\n\t\t\tlabel = \"blue:wlan5g\";\n\t\t\tgpios = <&gpio0 7 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\tturbo {\n\t\t\tlabel = \"blue:turbo\";\n\t\t\tgpios = <&gpio0 10 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tgpio_export {\n\t\tcompatible = \"gpio-export\";\n\t\t#size-cells = <0>;\n\n\t\tusbpower {\n\t\t\tgpio-export,name = \"usbpower\";\n\t\t\tgpio-export,output = <0>;\n\t\t\tgpios = <&gpio0 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tsdpower {\n\t\t\tgpio-export,name = \"sdpower\";\n\t\t\tgpio-export,output = <0>;\n\t\t\tgpios = <&gpio0 8 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&ehci {\n\tstatus = \"okay\";\n};\n\n&ohci {\n\tstatus = \"okay\";\n};\n\n&ethernet {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&rgmii1_pins &mdio_pins>;\n\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tmediatek,portmap = \"llllw\";\n\n\tport@5 {\n\t\tstatus = \"okay\";\n\t\tphy-handle = <&phy5>;\n\t\tphy-mode = \"rgmii\";\n\t};\n\n\tmdio-bus {\n\t\tstatus = \"okay\";\n\n\t\tphy5: ethernet-phy@5 {\n\t\t\treg = <5>;\n\t\t\tphy-mode = \"rgmii\";\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\twifi@0,0 {\n\t\tcompatible = \"pci14c3,7662\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\t};\n};\n\n&wmac {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pa_pins>;\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620a_hiwifi_hc5x61.dtsi",
    "content": "#include \"mt7620a.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"hiwifi,hc5x61\", \"ralink,mt7620a-soc\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 12 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n};\n\n&gpio3 {\n\tstatus = \"okay\";\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <80000000>;\n\t\tm25p,fast-read;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"hw_panic\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0xf70000>;\n\t\t\t};\n\n\t\t\tpartition@fc0000 {\n\t\t\t\tlabel = \"oem\";\n\t\t\t\treg = <0xfc0000 0x20000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tbdinfo: partition@fe0000 {\n\t\t\t\tlabel = \"bdinfo\";\n\t\t\t\treg = <0xfe0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@ff0000 {\n\t\t\t\tlabel = \"backup\";\n\t\t\t\treg = <0xff0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tmediatek,portmap = \"wllll\";\n};\n\n&sdhci {\n\tstatus = \"okay\";\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"uartf\", \"wled\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620a_hnet_c108.dts",
    "content": "// SPDX-License-Identifier: BSD-3-Clause\n/*\n *  Copyright(c) 2017 Kristian Evensen <kristian.evensen@gmail.com>.\n *  All rights reserved.\n */\n\n#include \"mt7620a.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"hnet,c108\", \"ralink,mt7620a-soc\";\n\tmodel = \"HNET C108\";\n\n\taliases {\n\t\tled-boot = &led_lan_green;\n\t\tled-failsafe = &led_lan_green;\n\t\tled-running = &led_lan_green;\n\t\tled-upgrade = &led_lan_green;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200\";\n\t};\n\n\tgpio-export {\n\t\tcompatible = \"gpio-export\";\n\t\t#size-cells = <0>;\n\n\t\tpower_modem {\n\t\t\tgpio-export,name = \"power_modem\";\n\t\t\tgpio-export,output = <1>;\n\t\t\tgpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tsdcard {\n\t\t\tlabel = \"green:sdcard\";\n\t\t\tgpios = <&gpio0 13 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tmodem_green {\n\t\t\tlabel = \"green:modem\";\n\t\t\tgpios = <&gpio1 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tmodem_red {\n\t\t\tlabel = \"red:modem\";\n\t\t\tgpios = <&gpio1 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan_red {\n\t\t\tlabel = \"red:lan\";\n\t\t\tgpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tled_lan_green: lan_green {\n\t\t\tlabel = \"green:lan\";\n\t\t\tgpios = <&gpio2 4 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 1 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n};\n\n&gpio1 {\n\tstatus = \"okay\";\n};\n\n&gpio2 {\n\tstatus = \"okay\";\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0xfb0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&sdhci {\n\tstatus = \"okay\";\n};\n\n&ehci {\n\tstatus = \"okay\";\n};\n\n&ohci {\n\tstatus = \"okay\";\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_28>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&state_default {\n\tdefault {\n\t\tgroups = \"i2c\", \"uartf\", \"spi refclk\", \"ephy\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_28: macaddr@28 {\n\t\treg = <0x28 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620a_humax_e2.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7620a.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/mtd/partitions/uimage.h>\n\n/ {\n\tcompatible = \"humax,e2\", \"ralink,mt7620a-soc\";\n\tmodel = \"HUMAX E2\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t\tlabel-mac-device = &ethernet;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio1 3 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tpairing {\n\t\t\tlabel = \"green:pairing\";\n\t\t\tgpios = <&gpio1 8 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan {\n\t\t\tlabel = \"green:wlan\";\n\t\t\tgpios = <&gpio1 9 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan {\n\t\t\tlabel = \"green:lan\";\n\t\t\tgpios = <&gpio1 4 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&gpio1 5 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio1 1 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n};\n\n&gpio1 {\n\tstatus = \"okay\";\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <50000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x30000>;\n\t\t\t\tread-only;\n\n\t\t\t\tcompatible = \"nvmem-cells\";\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\n\t\t\t\tmacaddr_factory_10007: macaddr@10007 {\n\t\t\t\t\treg = <0x10007 0x6>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tpartition@70000 {\n\t\t\t\tcompatible = \"openwrt,uimage\", \"denx,uimage\";\n\t\t\t\topenwrt,offset = <FW_EDIMAX_OFFSET>;\n\t\t\t\topenwrt,partition-magic = <FW_MAGIC_EDIMAX>;\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x70000 0x790000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_10007>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\twifi@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\t};\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"rgmii1\";\n\t\tfunction = \"gpio\";\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620a_iodata_wn-ac1167gr.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7620a.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"iodata,wn-ac1167gr\", \"ralink,mt7620a-soc\";\n\tmodel = \"I-O DATA WN-AC1167GR\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio0 7 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\twlan2g {\n\t\t\tlabel = \"green:wlan2g\";\n\t\t\tgpios = <&gpio0 10 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tnotification {\n\t\t\tlabel = \"green:notification\";\n\t\t\tgpios = <&gpio0 11 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan5g {\n\t\t\tlabel = \"green:wlan5g\";\n\t\t\tgpios = <&gpio0 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio0 1 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 2 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\tauto {\n\t\t\tlabel = \"auto\";\n\t\t\tgpios = <&gpio0 12 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_0>;\n\t\t\tlinux,input-type = <EV_SW>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x8000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tiNIC_rf: partition@48000 {\n\t\t\t\tlabel = \"iNIC_rf\";\n\t\t\t\treg = <0x48000 0x8000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tlabel = \"NoUsed\";\n\t\t\t\treg = <0x50000 0x20000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@70000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x70000 0x6b4000>;\n\t\t\t};\n\n\t\t\tpartition@724000 {\n\t\t\t\tlabel = \"manufacture\";\n\t\t\t\treg = <0x724000 0x8c000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@7b0000 {\n\t\t\t\tlabel = \"backup\";\n\t\t\t\treg = <0x7b0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@7c0000 {\n\t\t\t\tlabel = \"storage\";\n\t\t\t\treg = <0x7c0000 0x40000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&ethernet {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&rgmii1_pins &mdio_pins>;\n\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tport@5 {\n\t\tstatus = \"okay\";\n\t\tmediatek,fixed-link = <1000 1 1 1>;\n\t\tphy-mode = \"rgmii\";\n\t};\n\n\tmdio-bus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tstatus = \"okay\";\n\n\t\tethernet-phy@0 {\n\t\t\treg = <0>;\n\t\t\tphy-mode = \"rgmii\";\n\t\t};\n\n\t\tethernet-phy@1 {\n\t\t\treg = <1>;\n\t\t\tphy-mode = \"rgmii\";\n\t\t};\n\n\t\tethernet-phy@2 {\n\t\t\treg = <2>;\n\t\t\tphy-mode = \"rgmii\";\n\t\t};\n\n\t\tethernet-phy@3 {\n\t\t\treg = <3>;\n\t\t\tphy-mode = \"rgmii\";\n\t\t};\n\n\t\tethernet-phy@4 {\n\t\t\treg = <4>;\n\t\t\tphy-mode = \"rgmii\";\n\t\t};\n\n\t\tethernet-phy@1f {\n\t\t\treg = <0x1f>;\n\t\t\tphy-mode = \"rgmii\";\n\t\t};\n\t};\n};\n\n&gsw {\n\tmediatek,ephy-base = /bits/ 8 <12>;\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"uartf\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\twifi@0,0 {\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&iNIC_rf 0x0>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\t};\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620a_iodata_wn-ac733gr3.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7620a.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"iodata,wn-ac733gr3\", \"ralink,mt7620a-soc\";\n\tmodel = \"I-O DATA WN-AC733GR3\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio0 7 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\tnotification {\n\t\t\tlabel = \"green:notification\";\n\t\t\tgpios = <&gpio0 8 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan2g {\n\t\t\tlabel = \"green:wlan2g\";\n\t\t\tgpios = <&gpio0 10 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan5g {\n\t\t\tlabel = \"green:wlan5g\";\n\t\t\tgpios = <&gpio0 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 1 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio0 2 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\n\t\trouter {\n\t\t\tlabel = \"router\";\n\t\t\tgpios = <&gpio0 12 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_0>;\n\t\t\tlinux,input-type = <EV_SW>;\n\t\t};\n\n\t\tauto {\n\t\t\tlabel = \"auto\";\n\t\t\tgpios = <&gpio0 13 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_0>;\n\t\t\tlinux,input-type = <EV_SW>;\n\t\t};\n\t};\n\n\trtl8367rb {\n\t\tcompatible = \"realtek,rtl8367b\";\n\t\tgpio-sda = <&gpio0 22 GPIO_ACTIVE_HIGH>;\n\t\tgpio-sck = <&gpio0 23 GPIO_ACTIVE_HIGH>;\n\t\trealtek,extif1 = <1 0 1 1 1 1 1 1 2>;\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x8000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tiNIC_rf: partition@48000 {\n\t\t\t\tlabel = \"iNIC_rf\";\n\t\t\t\treg = <0x48000 0x8000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x6d4000>;\n\t\t\t};\n\n\t\t\tpartition@724000 {\n\t\t\t\tlabel = \"manufacture\";\n\t\t\t\treg = <0x724000 0x8c000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@7b0000 {\n\t\t\t\tlabel = \"backup\";\n\t\t\t\treg = <0x7b0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@7c0000 {\n\t\t\t\tlabel = \"storage\";\n\t\t\t\treg = <0x7c0000 0x40000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&ethernet {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&rgmii1_pins>;\n\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tport@5 {\n\t\tstatus = \"okay\";\n\t\tmediatek,fixed-link = <1000 1 1 1>;\n\t\tphy-mode = \"rgmii\";\n\t};\n};\n\n&gpio0 {\n\trtl8367rb_reset {\n\t\tgpio-hog;\n\t\tgpios = <0 GPIO_ACTIVE_HIGH>;\n\t\toutput-high;\n\t\tline-name = \"rtl8367rb-reset\";\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"uartf\", \"mdio\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\twifi@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&iNIC_rf 0x0>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\t};\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620a_iptime.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7620a.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\taliases {\n\t\tlabel-mac-device = &ethernet;\n\t};\n};\n\n&gpio1 {\n\tstatus = \"okay\";\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <40000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tuboot: partition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x20000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tlabel = \"config\";\n\t\t\t\treg = <0x20000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfirmware: partition@30000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t};\n\t\t};\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_uboot_1fc20>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&ehci {\n\tstatus = \"okay\";\n};\n\n&ohci {\n\tstatus = \"okay\";\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\twifi@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&uboot 0x1f800>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\n\t\tled {\n\t\t\tled-sources = <0>;\n\t\t\tled-active-low;\n\t\t};\n\t};\n};\n\n&wmac {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&wled_pins>;\n\n\tralink,mtd-eeprom = <&uboot 0x1f400>;\n};\n\n&uboot {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_uboot_1fc20: macaddr@1fc20 {\n\t\treg = <0x1fc20 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620a_iptime_a1004ns.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7620a_iptime.dtsi\"\n\n/ {\n\tcompatible = \"iptime,a1004ns\", \"ralink,mt7620a-soc\";\n\tmodel = \"ipTIME A1004ns\";\n\n\taliases {\n\t\tled-boot = &led_cpu;\n\t\tled-failsafe = &led_cpu;\n\t\tled-running = &led_cpu;\n\t\tled-upgrade = &led_cpu;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_cpu: cpu {\n\t\t\tlabel = \"blue:cpu\";\n\t\t\tgpios = <&gpio0 11 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tusb {\n\t\t\tlabel = \"blue:usb\";\n\t\t\tgpios = <&gpio1 15 GPIO_ACTIVE_LOW>;\n\t\t\ttrigger-sources = <&ohci_port1>, <&ehci_port1>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 1 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio0 2 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n};\n\n&firmware {\n\treg = <0x30000 0xfd0000>;\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"uartf\", \"spi refclk\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&rgmii1_pins &mdio_pins>;\n\n\tport@5 {\n\t\tstatus = \"okay\";\n\t\tmediatek,fixed-link = <1000 1 1 1>;\n\t\tphy-mode = \"rgmii\";\n\t};\n\n\tmdio-bus {\n\t\tstatus = \"okay\";\n\n\t\tethernet-phy@0 {\n\t\t\treg = <0>;\n\t\t\tphy-mode = \"rgmii\";\n\t\t};\n\n\t\tethernet-phy@1 {\n\t\t\treg = <1>;\n\t\t\tphy-mode = \"rgmii\";\n\t\t};\n\n\t\tethernet-phy@2 {\n\t\t\treg = <2>;\n\t\t\tphy-mode = \"rgmii\";\n\t\t};\n\n\t\tethernet-phy@3 {\n\t\t\treg = <3>;\n\t\t\tphy-mode = \"rgmii\";\n\t\t};\n\n\t\tethernet-phy@4 {\n\t\t\treg = <4>;\n\t\t\tphy-mode = \"rgmii\";\n\t\t};\n\n\t\tethernet-phy@1f {\n\t\t\treg = <0x1f>;\n\t\t\tphy-mode = \"rgmii\";\n\t\t};\n\t};\n};\n\n&gsw {\n\tmediatek,ephy-base = /bits/ 8 <12>;\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620a_iptime_a104ns.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7620a_iptime.dtsi\"\n\n/ {\n\tcompatible = \"iptime,a104ns\", \"ralink,mt7620a-soc\";\n\tmodel = \"ipTIME A104ns\";\n\n\taliases {\n\t\tled-boot = &led_cpu;\n\t\tled-failsafe = &led_cpu;\n\t\tled-running = &led_cpu;\n\t\tled-upgrade = &led_cpu;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tusb {\n\t\t\tlabel = \"blue:usb\";\n\t\t\tgpios = <&gpio0 11 GPIO_ACTIVE_LOW>;\n\t\t\ttrigger-sources = <&ohci_port1>, <&ehci_port1>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\n\t\tled_cpu: cpu {\n\t\t\tlabel = \"blue:cpu\";\n\t\t\tgpios = <&gpio1 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio0 12 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 13 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n};\n\n&firmware {\n\treg = <0x30000 0x7d0000>;\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"uartf\", \"spi refclk\";\n\t\tfunction = \"gpio\";\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620a_kimax_u25awf-h1.dts",
    "content": "#include \"mt7620a.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/{\n\tcompatible = \"kimax,u25awf-h1\",\"ralink,mt7620a-soc\";\n\tmodel = \"Kimax U25AWF-H1\";\n\n\taliases {\n\t\tled-boot = &led_wifi;\n\t\tled-failsafe = &led_wifi;\n\t\tled-running = &led_wifi;\n\t\tled-upgrade = &led_wifi;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 13 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_wifi: wifi {\n\t\t\tlabel = \"red:wifi\";\n\t\t\tgpios = <&gpio3 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan {\n\t\t\tlabel = \"green:lan\";\n\t\t\tgpios = <&gpio2 4 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&gpio2 {\n\tstatus = \"okay\";\n};\n\n&gpio3 {\n\tstatus = \"okay\";\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0xfb0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&ehci {\n\tstatus = \"okay\";\n};\n\n&ohci {\n\tstatus = \"okay\";\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&state_default {\n\tdefault {\n\t\tgroups = \"uartf\", \"ephy\", \"wled\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620a_lava_lr-25g001.dts",
    "content": "#include \"mt7620a.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/mtd/partitions/uimage.h>\n\n/ {\n\tcompatible = \"lava,lr-25g001\", \"ralink,mt7620a-soc\";\n\tmodel = \"LAVA LR-25G001\";\n\n\taliases {\n\t\tled-boot = &led_status;\n\t\tled-failsafe = &led_status;\n\t\tled-running = &led_status;\n\t\tled-upgrade = &led_status;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio0 2 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 1 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_status: status {\n\t\t\tlabel = \"green:status\";\n\t\t\tgpios = <&gpio0 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twifi2g {\n\t\t\tlabel = \"green:wifi2g\";\n\t\t\tgpios = <&gpio0 11 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\n\t\twifi5g {\n\t\t\tlabel = \"green:wifi5g\";\n\t\t\tgpios = <&gpio0 13 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\t};\n\n\tgpio_export {\n\t\tcompatible = \"gpio-export\";\n\t\t#size-cells = <0>;\n\n\t\tusbpower {\n\t\t\tgpio-export,name = \"usbpower\";\n\t\t\tgpio-export,output = <1>;\n\t\t\tgpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"jboot\";\n\t\t\t\treg = <0x0 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@10000 {\n\t\t\t\tcompatible = \"openwrt,uimage\", \"denx,uimage\";\n\t\t\t\topenwrt,ih-magic = <IH_MAGIC_OKLI>;\n\t\t\t\topenwrt,offset = <0x10000>;\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x10000 0xfe0000>;\n\t\t\t};\n\n\t\t\tconfig: partition@ff0000 {\n\t\t\t\tlabel = \"config\";\n\t\t\t\treg = <0xff0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&ehci {\n\tstatus = \"okay\";\n};\n\n&ohci {\n\tstatus = \"okay\";\n};\n\n&ethernet {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&rgmii1_pins &rgmii2_pins &mdio_pins>;\n\n\tport@5 {\n\t\tstatus = \"okay\";\n\t\tphy-mode = \"rgmii\";\n\t\tmediatek,fixed-link = <1000 1 1 1>;\n\t};\n\n\tmdio-bus {\n\t\tstatus = \"okay\";\n\n\t\tethernet-phy@0 {\n\t\t\treg = <0>;\n\t\t\tphy-mode = \"rgmii\";\n\t\t\tqca,ar8327-initvals = <\n\t\t\t\t0x04 0x87300000 /* PORT0 PAD MODE CTRL */\n\t\t\t\t0x0c 0x00000000 /* PORT6 PAD MODE CTRL */\n\t\t\t\t0x7c 0x0000007e /* PORT0_STATUS */\n\t\t\t\t0x80 0x00001200 /* PORT1_STATUS */\n\t\t\t\t0x84 0x00001200 /* PORT2_STATUS */\n\t\t\t\t0x88 0x00001200 /* PORT3_STATUS */\n\t\t\t\t0x8c 0x00001200 /* PORT4_STATUS */\n\t\t\t\t0x90 0x00001200 /* PORT5_STATUS */\n\t\t\t\t0x94 0x00000000 /* PORT6_STATUS */\n\t\t\t>;\n\t\t};\n\t};\n};\n\n&gsw {\n\tmediatek,ephy-base = /bits/ 8 <8>;\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\tmt76x0e@0,0 {\n\t\treg = <0x0000 0 0 0 0>;\n\t\tnvmem-cells = <&macaddr_config_e07e>;\n\t\tnvmem-cell-names = \"mac-address\";\n\t\tmac-address-increment = <(2)>;\n\t\tmediatek,mtd-eeprom = <&config 0xe08a>;\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"uartf\", \"i2c\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&config {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_config_e07e: macaddr@e07e {\n\t\treg = <0xe07e 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620a_lb-link_bl-w1200.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-only\n\n#include \"mt7620a.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"lb-link,bl-w1200\", \"ralink,mt7620a-soc\";\n\tmodel = \"LB-Link BL-W1200\";\n\n\taliases {\n\t\tled-boot = &led_wps;\n\t\tled-failsafe = &led_wps;\n\t\tled-upgrade = &led_wps;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset_wps {\n\t\t\tlabel = \"reset_wps\";\n\t\t\tgpios = <&gpio0 13 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_wps: wps {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&gpio1 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&gpio1 {\n\tstatus = \"okay\";\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <50000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"config\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x7b0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"uartf\", \"spi refclk\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&rgmii2_pins &mdio_pins>;\n\n\tnvmem-cells = <&macaddr_factory_28>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tmediatek,portmap = \"wllll\";\n\n\tport@5 {\n\t\tstatus = \"okay\";\n\t\tmediatek,fixed-link = <1000 1 1 1>;\n\t\tphy-mode = \"rgmii\";\n\t};\n\n\tmdio-bus {\n\t\tstatus = \"okay\";\n\n\t\tethernet-phy@0 {\n\t\t\treg = <0>;\n\t\t\tphy-mode = \"rgmii\";\n\t\t};\n\n\t\tethernet-phy@1 {\n\t\t\treg = <1>;\n\t\t\tphy-mode = \"rgmii\";\n\t\t};\n\n\t\tethernet-phy@2 {\n\t\t\treg = <2>;\n\t\t\tphy-mode = \"rgmii\";\n\t\t};\n\n\t\tethernet-phy@3 {\n\t\t\treg = <3>;\n\t\t\tphy-mode = \"rgmii\";\n\t\t};\n\n\t\tethernet-phy@4 {\n\t\t\treg = <4>;\n\t\t\tphy-mode = \"rgmii\";\n\t\t};\n\n\t\tethernet-phy@1f {\n\t\t\treg = <0x1f>;\n\t\t\tphy-mode = \"rgmii\";\n\t\t};\n\t};\n};\n\n&gsw {\n\tmediatek,ephy-base = /bits/ 8 <12>;\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\twifi@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\n\t\tled {\n\t\t\tled-sources = <2>;\n\t\t\tled-active-low;\n\t\t};\n\t};\n};\n\n&ehci {\n\tstatus = \"okay\";\n};\n\n&ohci {\n\tstatus = \"okay\";\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_28: macaddr@28 {\n\t\treg = <0x28 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620a_lenovo_newifi-y1.dts",
    "content": "#include \"mt7620a_lenovo_newifi-y1.dtsi\"\n\n/ {\n\tcompatible = \"lenovo,newifi-y1\", \"ralink,mt7620a-soc\";\n\tmodel = \"Lenovo Y1\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t\tlabel-mac-device = &ethernet;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"blue:power\";\n\t\t\tgpios = <&gpio0 9 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan1 {\n\t\t\tlabel = \"blue:wifi\";\n\t\t\tgpios = <&gpio3 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan2 {\n\t\t\tlabel = \"blue:wifi5g\";\n\t\t\tgpios = <&gpio2 10 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tusb {\n\t\t\tlabel = \"blue:usb\";\n\t\t\tgpios = <&gpio2 12 GPIO_ACTIVE_LOW>;\n\t\t\ttrigger-sources = <&ohci_port1>, <&ehci_port1>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\n\t\tlan {\n\t\t\tlabel = \"blue:lan\";\n\t\t\tgpios = <&gpio2 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tinternet {\n\t\t\tlabel = \"blue:internet\";\n\t\t\tgpios = <&gpio2 11 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&ethernet {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&ephy_pins>;\n\n\tnvmem-cells = <&macaddr_factory_28>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tmediatek,portmap = \"llllw\";\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_28: macaddr@28 {\n\t\treg = <0x28 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620a_lenovo_newifi-y1.dtsi",
    "content": "#include \"mt7620a.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"lenovo,newifi-y1\", \"ralink,mt7620a-soc\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 11 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n};\n\n&gpio2 {\n\tstatus = \"okay\";\n};\n\n&gpio3 {\n\tstatus = \"okay\";\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0xfb0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&ehci {\n\tstatus = \"okay\";\n};\n\n&ohci {\n\tstatus = \"okay\";\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\tmt76@0,0 {\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\t};\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pa_pins>;\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"uartf\", \"wled\", \"nd_sd\";\n\t\tfunction = \"gpio\";\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620a_lenovo_newifi-y1s.dts",
    "content": "#include \"mt7620a_lenovo_newifi-y1.dtsi\"\n\n/ {\n\tcompatible = \"lenovo,newifi-y1s\", \"lenovo,newifi-y1\", \"ralink,mt7620a-soc\";\n\tmodel = \"Lenovo Y1S\";\n\n\taliases {\n\t\tled-boot = &led_power_blue;\n\t\tled-failsafe = &led_power_blue;\n\t\tled-running = &led_power_blue;\n\t\tled-upgrade = &led_power_blue;\n\t\tlabel-mac-device = &ethernet;\n\t};\n\n\tgpio_export {\n\t\tcompatible = \"gpio-export\";\n\t\t#size-cells = <0>;\n\n\t\tusb0 {\n\t\t\tgpio-export,name = \"usb0\";\n\t\t\tgpio-export,output = <1>;\n\t\t\tgpios = <&gpio2 14 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t\tusb1 {\n\t\t\tgpio-export,name = \"usb1\";\n\t\t\tgpio-export,output = <1>;\n\t\t\tgpios = <&gpio2 15 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t\tusb2 {\n\t\t\tgpio-export,name = \"usb2\";\n\t\t\tgpio-export,output = <1>;\n\t\t\tgpios = <&gpio2 16 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tpower1 {\n\t\t\tlabel = \"yellow:power\";\n\t\t\tgpios = <&gpio0 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_power_blue: power2 {\n\t\t\tlabel = \"blue:power\";\n\t\t\tgpios = <&gpio0 9 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan1 {\n\t\t\tlabel = \"yellow:wifi\";\n\t\t\tgpios = <&gpio3 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan2 {\n\t\t\tlabel = \"blue:wifi\";\n\t\t\tgpios = <&gpio2 10 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tusb1 {\n\t\t\tlabel = \"yellow:usb\";\n\t\t\tgpios = <&gpio2 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tusb2 {\n\t\t\tlabel = \"blue:usb\";\n\t\t\tgpios = <&gpio2 12 GPIO_ACTIVE_LOW>;\n\t\t\ttrigger-sources = <&ohci_port1>, <&ehci_port1>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\n\t\tinternet {\n\t\t\tlabel = \"blue:internet\";\n\t\t\tgpios = <&gpio2 11 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&ethernet {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&rgmii1_pins &rgmii2_pins &mdio_pins>;\n\n\tnvmem-cells = <&macaddr_factory_28>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tmediatek,portmap = \"wllll\";\n\n\tport@4 {\n\t\tstatus = \"okay\";\n\t\tphy-handle = <&phy4>;\n\t\tphy-mode = \"rgmii\";\n\t};\n\n\tport@5 {\n\t\tstatus = \"okay\";\n\t\tphy-handle = <&phy5>;\n\t\tphy-mode = \"rgmii\";\n\t};\n\n\tmdio-bus {\n\t\tstatus = \"okay\";\n\n\t\tphy4: ethernet-phy@4 {\n\t\t\treg = <4>;\n\t\t\tphy-mode = \"rgmii\";\n\t\t};\n\n\t\tphy5: ethernet-phy@5 {\n\t\t\treg = <5>;\n\t\t\tphy-mode = \"rgmii\";\n\t\t};\n\t};\n};\n\n&gsw {\n\tmediatek,port4-gmac;\n\tmediatek,ephy-base = /bits/ 8 <8>;\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_28: macaddr@28 {\n\t\treg = <0x28 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620a_linksys_e1700.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-only\n/*\n * Copyright (C) 2014 Imre Kaloz <kaloz@openwrt.org>\n */\n\n#include \"mt7620a.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"linksys,e1700\", \"ralink,mt7620a-soc\";\n\tmodel = \"Linksys E1700\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 1 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio0 2 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio0 10 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twan {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&gpio0 12 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"config\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x7b0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"uartf\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&rgmii1_pins &rgmii2_pins &mdio_pins>;\n\n\tnvmem-cells = <&macaddr_factory_28>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tport@5 {\n\t\tstatus = \"okay\";\n\t\tmediatek,fixed-link = <1000 1 1 1>;\n\t\tphy-mode = \"rgmii\";\n\t};\n\n\tmdio-bus {\n\t\tstatus = \"okay\";\n\n\t\tphy0: ethernet-phy@0 {\n\t\t\treg = <0>;\n\t\t\tphy-mode = \"rgmii\";\n\t\t};\n\n\t\tphy1: ethernet-phy@1 {\n\t\t\treg = <1>;\n\t\t\tphy-mode = \"rgmii\";\n\t\t};\n\n\t\tphy2: ethernet-phy@2 {\n\t\t\treg = <2>;\n\t\t\tphy-mode = \"rgmii\";\n\t\t};\n\n\t\tphy3: ethernet-phy@3 {\n\t\t\treg = <3>;\n\t\t\tphy-mode = \"rgmii\";\n\t\t};\n\n\t\tphy4: ethernet-phy@4 {\n\t\t\treg = <4>;\n\t\t\tphy-mode = \"rgmii\";\n\t\t};\n\n\t\tphy1f: ethernet-phy@1f {\n\t\t\treg = <0x1f>;\n\t\t\tphy-mode = \"rgmii\";\n\t\t};\n\t};\n};\n\n&gsw {\n\tmediatek,ephy-base = /bits/ 8 <12>;\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_28: macaddr@28 {\n\t\treg = <0x28 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620a_microduino_microwrt.dts",
    "content": "#include \"mt7620a.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"microduino,microwrt\", \"ralink,mt7620a-soc\";\n\tmodel = \"Microduino MicroWRT\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 1 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio0 2 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x20000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x20000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@30000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x40000 0xfc0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&ehci {\n\tstatus = \"okay\";\n};\n\n&ohci {\n\tstatus = \"okay\";\n};\n\n&ethernet {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&ephy_pins>;\n\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tmediatek,portmap = \"llllw\";\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&state_default {\n\tdefault {\n\t\tgroups = \"wled\", \"i2c\", \"wdt\", \"uartf\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620a_netgear_ex2700.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-only\n/*\n * Copyright (C) 2016 Joseph C. Lehner <joseph.c.lehner@gmail.com>\n */\n\n#include \"mt7620a.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"netgear,ex2700\", \"ralink,mt7620a-soc\";\n\tmodel = \"Netgear EX2700\";\n\n\taliases {\n\t\tled-boot = &led_power_green;\n\t\tled-failsafe = &led_power_green;\n\t\tled-running = &led_power_green;\n\t\tled-upgrade = &led_power_green;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 1 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio0 2 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power_green: power_g {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio0 9 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\tpower_r {\n\t\t\tlabel = \"red:power\";\n\t\t\tgpios = <&gpio0 11 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tdevice_g {\n\t\t\tlabel = \"green:device\";\n\t\t\tgpios = <&gpio0 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tdevice_r {\n\t\t\tlabel = \"red:device\";\n\t\t\tgpios = <&gpio0 10 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\trouter_g {\n\t\t\tlabel = \"green:router\";\n\t\t\tgpios = <&gpio0 12 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\trouter_r {\n\t\t\tlabel = \"red:router\";\n\t\t\tgpios = <&gpio0 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&gpio1 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&gpio1 {\n\tstatus = \"okay\";\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x40000 0x3b0000>;\n\t\t\t};\n\n\t\t\tart: partition@3f0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0x3f0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&art 0x1000>;\n\n\tnvmem-cells = <&macaddr_art_6>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&state_default {\n\tdefault {\n\t\tgroups = \"i2c\", \"uartf\", \"spi refclk\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n\n\tmacaddr_art_6: macaddr@6 {\n\t\treg = <0x6 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620a_netgear_ex3700.dts",
    "content": "/* This file is released into the public domain */\n\n#include \"mt7620a_netgear_ex3x00_ex61xx.dtsi\"\n\n/ {\n\tcompatible = \"netgear,ex3700\", \"ralink,mt7620a-soc\";\n\tmodel = \"Netgear EX3700/EX3800\";\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620a_netgear_ex3x00_ex61xx.dtsi",
    "content": "#include \"mt7620a.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\taliases {\n\t\tled-boot = &led_power_amber;\n\t\tled-failsafe = &led_power_amber;\n\t\tled-running = &led_power_green;\n\t\tled-upgrade = &led_power_green;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio2 26 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio0 2 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power_green: power_green {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio2 23 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\tled_power_amber: power_amber {\n\t\t\tlabel = \"amber:power\";\n\t\t\tgpios = <&gpio2 28 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\trouter_green {\n\t\t\tlabel = \"green:router\";\n\t\t\tgpios = <&gpio2 25 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\trouter_red {\n\t\t\tlabel = \"red:router\";\n\t\t\tgpios = <&gpio2 24 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tdevice_green {\n\t\t\tlabel = \"green:device\";\n\t\t\tgpios = <&gpio2 20 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tdevice_red {\n\t\t\tlabel = \"red:device\";\n\t\t\tgpios = <&gpio2 21 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&gpio2 27 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&gpio2 {\n\tstatus = \"okay\";\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <50000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"config\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x790000>;\n\t\t\t};\n\n\t\t\tpartition@7e0000 {\n\t\t\t\tlabel = \"board_data\";\n\t\t\t\treg = <0x7e0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@7f0000 {\n\t\t\t\tlabel = \"nvram\";\n\t\t\t\treg = <0x7f0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\tmt76@0,0 {\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_28>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&state_default {\n\tdefault {\n\t\tgroups = \"i2c\", \"rgmii2\", \"spi refclk\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_28: macaddr@28 {\n\t\treg = <0x28 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620a_netgear_ex6120.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7620a_netgear_ex3x00_ex61xx.dtsi\"\n\n/ {\n\tcompatible = \"netgear,ex6120\", \"ralink,mt7620a-soc\";\n\tmodel = \"Netgear EX6120\";\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620a_netgear_ex6130.dts",
    "content": "/* This file is released into the public domain */\n\n#include \"mt7620a_netgear_ex3x00_ex61xx.dtsi\"\n\n/ {\n\tcompatible = \"netgear,ex6130\", \"ralink,mt7620a-soc\";\n\tmodel = \"Netgear EX6130\";\n\n\taliases {\n\t\tlabel-mac-device = &ethernet;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620a_netgear_wn3000rp-v3.dts",
    "content": "/* This file is released into the public domain */\n\n#include \"mt7620a_netgear_wn3x00rp.dtsi\"\n\n/ {\n\tcompatible = \"netgear,wn3000rp-v3\", \"ralink,mt7620a-soc\";\n\tmodel = \"Netgear WN3000RP v3\";\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620a_netgear_wn3100rp-v2.dts",
    "content": "/* This file is released into the public domain */\n\n#include \"mt7620a_netgear_wn3x00rp.dtsi\"\n\n/ {\n\tcompatible = \"netgear,wn3100rp-v2\", \"ralink,mt7620a-soc\";\n\tmodel = \"Netgear WN3100RP v2\";\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620a_netgear_wn3x00rp.dtsi",
    "content": "/* This file is released into the public domain */\n\n#include \"mt7620a.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\taliases {\n\t\tled-boot = &led_power_green;\n\t\tled-failsafe = &led_power_green;\n\t\tled-running = &led_power_green;\n\t\tled-upgrade = &led_power_green;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 1 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio0 2 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power_green: power_g {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio0 9 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\tpower_r {\n\t\t\tlabel = \"red:power\";\n\t\t\tgpios = <&gpio0 11 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tclient_g {\n\t\t\tlabel = \"green:client\";\n\t\t\tgpios = <&gpio0 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tclient_r {\n\t\t\tlabel = \"red:client\";\n\t\t\tgpios = <&gpio0 10 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\trouter_g {\n\t\t\tlabel = \"green:router\";\n\t\t\tgpios = <&gpio0 12 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\trouter_r {\n\t\t\tlabel = \"red:router\";\n\t\t\tgpios = <&gpio0 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&gpio1 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tl_arrow {\n\t\t\tlabel = \"blue:leftarrow\";\n\t\t\tgpios = <&gpio0 7 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tr_arrow {\n\t\t\tlabel = \"blue:rightarrow\";\n\t\t\tgpios = <&gpio0 8 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&gpio1 {\n\tstatus = \"okay\";\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x40000 0x7b0000>;\n\t\t\t};\n\n\t\t\tart: partition@7f0000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0x7f0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_art_0>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&art 0x1000>;\n\n\tnvmem-cells = <&macaddr_art_6>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&state_default {\n\tdefault {\n\t\tgroups = \"i2c\", \"uartf\", \"spi refclk\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&art {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_art_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n\n\tmacaddr_art_6: macaddr@6 {\n\t\treg = <0x6 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620a_netis_wf2770.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7620a.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"netis,wf2770\", \"ralink,mt7620a-soc\";\n\tmodel = \"NETIS WF2770\";\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twlan {\n\t\t\tlabel = \"blue:wlan\";\n\t\t\tgpios = <&gpio0 14 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 1 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio0 2 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\n\t\trfkill {\n\t\t\tlabel = \"rfkill\";\n\t\t\tgpios = <&gpio0 7 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RFKILL>;\n\t\t};\n\n\t\tled-toggle {\n\t\t\tlabel = \"led-toggle\";\n\t\t\tgpios = <&gpio0 11 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_LIGHTS_TOGGLE>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <50000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"config\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0xfb0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"uartf\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&rgmii1_pins &mdio_pins>;\n\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tport@5 {\n\t\tstatus = \"okay\";\n\t\tmediatek,fixed-link = <1000 1 1 1>;\n\t\tphy-mode = \"rgmii\";\n\t};\n\n\tmdio-bus {\n\t\tstatus = \"okay\";\n\n\t\tethernet-phy@0 {\n\t\t\treg = <0>;\n\t\t\tphy-mode = \"rgmii\";\n\t\t};\n\n\t\tethernet-phy@1 {\n\t\t\treg = <1>;\n\t\t\tphy-mode = \"rgmii\";\n\t\t};\n\n\t\tethernet-phy@2 {\n\t\t\treg = <2>;\n\t\t\tphy-mode = \"rgmii\";\n\t\t};\n\n\t\tethernet-phy@3 {\n\t\t\treg = <3>;\n\t\t\tphy-mode = \"rgmii\";\n\t\t};\n\n\t\tethernet-phy@4 {\n\t\t\treg = <4>;\n\t\t\tphy-mode = \"rgmii\";\n\t\t};\n\n\t\tethernet-phy@1f {\n\t\t\treg = <0x1f>;\n\t\t\tphy-mode = \"rgmii\";\n\t\t};\n\t};\n};\n\n&gsw {\n\tmediatek,ephy-base = /bits/ 8 <12>;\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\twifi@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\t};\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620a_ohyeah_oy-0001.dts",
    "content": "#include \"mt7620a.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"ohyeah,oy-0001\", \"ralink,mt7620a-soc\";\n\tmodel = \"OY-0001\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200\";\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: powerled {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio0 9 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twifiled {\n\t\t\tlabel = \"green:wifi\";\n\t\t\tgpios = <&gpio3 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\ts1 {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 1 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n};\n\n&gpio3 {\n\tstatus = \"okay\";\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0xfb0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"uartf\", \"rgmii1\", \"rgmii2\", \"wled\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&ephy_pins>;\n\n\tnvmem-cells = <&macaddr_factory_28>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tmediatek,portmap = \"llllw\";\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&sdhci {\n\tstatus = \"okay\";\n};\n\n&ehci {\n\tstatus = \"okay\";\n};\n\n&ohci {\n\tstatus = \"okay\";\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_28: macaddr@28 {\n\t\treg = <0x28 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620a_phicomm_k2-v22.4.dts",
    "content": "#include \"mt7620a_phicomm_k2x.dtsi\"\n\n/ {\n\tcompatible = \"phicomm,k2-v22.4\", \"ralink,mt7620a-soc\";\n\tmodel = \"Phicomm K2 v22.4 or older\";\n};\n\n&partitions {\n\tpartition@50000 {\n\t\tcompatible = \"denx,uimage\";\n\t\tlabel = \"firmware\";\n\t\treg = <0x50000 0x7b0000>;\n\t};\n};\n\n&ethernet {\n\tmediatek,portmap = \"llllw\";\n};\n\n&wmac {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pa_pins>;\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620a_phicomm_k2-v22.5.dts",
    "content": "#include \"mt7620a_phicomm_k2x.dtsi\"\n\n/ {\n\tcompatible = \"phicomm,k2-v22.5\", \"ralink,mt7620a-soc\";\n\tmodel = \"Phicomm K2 v22.5 or newer\";\n};\n\n&partitions {\n\tpartition@50000 {\n\t\tlabel = \"permanent_config\";\n\t\treg = <0x50000 0x50000>;\n\t\tread-only;\n\t};\n\n\tpartition@a0000 {\n\t\tcompatible = \"denx,uimage\";\n\t\tlabel = \"firmware\";\n\t\treg = <0xa0000 0x760000>;\n\t};\n};\n\n&ethernet {\n\tmediatek,portmap = \"llllw\";\n};\n\n&wmac {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pa_pins>;\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620a_phicomm_k2g.dts",
    "content": "#include \"mt7620a_phicomm_k2x.dtsi\"\n\n/ {\n\tcompatible = \"phicomm,k2g\", \"ralink,mt7620a-soc\";\n\tmodel = \"Phicomm K2G\";\n};\n\n&partitions {\n\tpartition@50000 {\n\t\treg = <0x50000 0x50000>;\n\t\tlabel = \"permanent_config\";\n\t\tread-only;\n\t};\n\n\tpartition@a0000 {\n\t\tcompatible = \"denx,uimage\";\n\t\treg = <0xa0000 0x760000>;\n\t\tlabel = \"firmware\";\n\t};\n};\n\n&ethernet {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&rgmii2_pins &mdio_pins>;\n\n\tmediatek,portmap = \"llllw\";\n\n\tport@5 {\n\t\tstatus = \"okay\";\n\t\tphy-handle = <&phy5>;\n\t\tphy-mode = \"rgmii\";\n\t};\n\n\tmdio-bus {\n\t\tstatus = \"okay\";\n\n\t\tphy5: ethernet-phy@5 {\n\t\t\treg = <5>;\n\t\t\tphy-mode = \"rgmii\";\n\t\t};\n\t};\n};\n\n&wmac {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pa_pins>;\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620a_phicomm_k2x.dtsi",
    "content": "#include \"mt7620a.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\taliases {\n\t\tled-boot = &led_blue;\n\t\tled-failsafe = &led_blue;\n\t\tled-running = &led_blue;\n\t\tled-upgrade = &led_blue;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 1 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_blue: blue {\n\t\t\tlabel = \"blue:status\";\n\t\t\tgpios = <&gpio0 10 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\tyellow {\n\t\t\tlabel = \"yellow:status\";\n\t\t\tgpios = <&gpio0 11 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tred {\n\t\t\tlabel = \"red:status\";\n\t\t\tgpios = <&gpio0 8 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <80000000>;\n\t\tm25p,fast-read;\n\n\t\tpartitions: partitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"uartf\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\tmt76@0,0 {\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_28>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_28: macaddr@28 {\n\t\treg = <0x28 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620a_phicomm_psg1208.dts",
    "content": "#include \"mt7620a.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"phicomm,psg1208\", \"ralink,mt7620a-soc\";\n\tmodel = \"Phicomm PSG1208\";\n\n\taliases {\n\t\tled-boot = &led_wps;\n\t\tled-failsafe = &led_wps;\n\t\tled-running = &led_wps;\n\t\tled-upgrade = &led_wps;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_wps: wps {\n\t\t\tlabel = \"white:wps\";\n\t\t\tgpios = <&gpio1 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan {\n\t\t\tlabel = \"white:wlan2g\";\n\t\t\tgpios = <&gpio3 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 1 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n};\n\n&gpio1 {\n\tstatus = \"okay\";\n};\n\n&gpio3 {\n\tstatus = \"okay\";\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <80000000>;\n\t\tm25p,fast-read;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@30000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x7b0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"spi refclk\", \"wled\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&ephy_pins>;\n\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tmediatek,portmap = \"llllw\";\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\tmt76@0,0 {\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\t};\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620a_phicomm_psg1218b.dts",
    "content": "#include \"mt7620a_phicomm_k2x.dtsi\"\n\n/ {\n\tcompatible = \"phicomm,psg1218b\", \"phicomm,psg1218\", \"ralink,mt7620a-soc\";\n\tmodel = \"Phicomm PSG1218 rev.B\";\n};\n\n&partitions {\n\tpartition@50000 {\n\t\tcompatible = \"denx,uimage\";\n\t\tlabel = \"firmware\";\n\t\treg = <0x50000 0x7b0000>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620a_planex_cs-qr10.dts",
    "content": "#include \"mt7620a.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"planex,cs-qr10\", \"ralink,mt7620a-soc\";\n\tmodel = \"Planex CS-QR10\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"red:power\";\n\t\t\tgpios = <&gpio1 4 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\ts1 {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio1 1 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\ts2 {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio1 3 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n};\n\n&gpio1 {\n\tstatus = \"okay\";\n};\n\n&i2c {\n\tstatus = \"okay\";\n};\n\n&i2s {\n\tstatus = \"okay\";\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pcm_i2s_pins>;\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x7b0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pcm {\n\tstatus = \"okay\";\n};\n\n&gdma {\n\tstatus = \"okay\";\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"spi refclk\", \"rgmii1\";\n\t\tfunction = \"gpio\";\n\t};\n\twdt {\n\t\tgroups = \"wdt\";\n\t\tfunction = \"wdt refclk\";\n\t};\n};\n\n&ethernet {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&ephy_pins>;\n\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tmediatek,portmap = \"llllw\";\n};\n\n&sdhci {\n\tstatus = \"okay\";\n};\n\n&ehci {\n\tstatus = \"okay\";\n};\n\n&ohci {\n\tstatus = \"okay\";\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620a_planex_db-wrt01.dts",
    "content": "#include \"mt7620a.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"planex,db-wrt01\", \"ralink,mt7620a-soc\";\n\tmodel = \"Planex DB-WRT01\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"orange:power\";\n\t\t\tgpios = <&gpio1 1 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\ts1 {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio0 2 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n};\n\n&gpio1 {\n\tstatus = \"okay\";\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x7b0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"spi refclk\", \"rgmii1\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&ephy_pins>;\n\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tmediatek,portmap = \"llllw\";\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620a_planex_mzk-750dhp.dts",
    "content": "#include \"mt7620a.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"planex,mzk-750dhp\", \"ralink,mt7620a-soc\";\n\tmodel = \"Planex MZK-750DHP\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twps {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&gpio2 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_power: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio1 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan5g {\n\t\t\tlabel = \"green:wlan5g\";\n\t\t\tgpios = <&gpio1 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\ts1 {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 1 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\ts2 {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio2 19 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n};\n\n&gpio1 {\n\tstatus = \"okay\";\n};\n\n&gpio2 {\n\tstatus = \"okay\";\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x7b0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"spi refclk\", \"rgmii1\", \"nd_sd\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&ephy_pins>;\n\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tmediatek,portmap = \"llllw\";\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\tmt76@0,0 {\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t};\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620a_planex_mzk-ex300np.dts",
    "content": "#include \"mt7620a.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"planex,mzk-ex300np\", \"ralink,mt7620a-soc\";\n\tmodel = \"Planex MZK-EX300NP\";\n\n\taliases {\n\t\tled-boot = &led_wps;\n\t\tled-failsafe = &led_wps;\n\t\tled-running = &led_wps;\n\t\tled-upgrade = &led_wps;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twifi {\n\t\t\tlabel = \"green:wifi\";\n\t\t\tgpios = <&gpio3 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_wps: wps {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&gpio1 5 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\trep {\n\t\t\tlabel = \"blue:rep\";\n\t\t\tgpios = <&gpio1 4 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twifi1 {\n\t\t\tlabel = \"blue:wifi1\";\n\t\t\tgpios = <&gpio1 1 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twifi2 {\n\t\t\tlabel = \"blue:wifi2\";\n\t\t\tgpios = <&gpio1 2 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twifi3 {\n\t\t\tlabel = \"blue:wifi3\";\n\t\t\tgpios = <&gpio1 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 1 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = <KEY_RFKILL>;\n\t\t};\n\t};\n};\n\n&gpio1 {\n\tstatus = \"okay\";\n};\n\n&gpio3 {\n\tstatus = \"okay\";\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x730000>;\n\t\t\t};\n\n\t\t\tpartition@780000 {\n\t\t\t\tlabel = \"Udata\";\n\t\t\t\treg = <0x780000 0x80000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"spi refclk\", \"rgmii1\", \"wled\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&ephy_pins>;\n\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tmediatek,portmap = \"llllw\";\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620a_planex_mzk-ex750np.dts",
    "content": "#include \"mt7620a.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"planex,mzk-ex750np\", \"ralink,mt7620a-soc\";\n\tmodel = \"Planex MZK-EX750NP\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"red:power\";\n\t\t\tgpios = <&gpio0 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twifi {\n\t\t\tlabel = \"red:wifi\";\n\t\t\tgpios = <&gpio3 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&gpio0 10 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\trep {\n\t\t\tlabel = \"blue:rep\";\n\t\t\tgpios = <&gpio2 16 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twifi1 {\n\t\t\tlabel = \"blue:wifi1\";\n\t\t\tgpios = <&gpio2 19 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twifi2 {\n\t\t\tlabel = \"blue:wifi2\";\n\t\t\tgpios = <&gpio2 18 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twifi3 {\n\t\t\tlabel = \"blue:wifi3\";\n\t\t\tgpios = <&gpio2 17 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 9 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio0 13 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = <KEY_RFKILL>;\n\t\t};\n\t};\n};\n\n&gpio2 {\n\tstatus = \"okay\";\n};\n\n&gpio3 {\n\tstatus = \"okay\";\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x730000>;\n\t\t\t};\n\n\t\t\tpartition@780000 {\n\t\t\t\tlabel = \"Udata\";\n\t\t\t\treg = <0x780000 0x80000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"uartf\", \"nd_sd\", \"rgmii2\", \"wled\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&ephy_pins>;\n\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tmediatek,portmap = \"llllw\";\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\tmt76@0,0 {\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t};\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620a_ralink_mt7620a-evb.dts",
    "content": "#include \"mt7620a.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"ralink,mt7620a-evb\", \"ralink,mt7620a-soc\";\n\tmodel = \"Ralink MT7620a + MT7610e evaluation board\";\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\ts2 {\n\t\t\tlabel = \"S2\";\n\t\t\tgpios = <&gpio0 1 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_0>;\n\t\t};\n\n\t\ts3 {\n\t\t\tlabel = \"S3\";\n\t\t\tgpios = <&gpio0 2 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_1>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x7b0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"uartf\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&rgmii1_pins &rgmii2_pins &mdio_pins>;\n\n\tmediatek,portmap = \"llllw\";\n\n\tport@4 {\n\t\tstatus = \"okay\";\n\t\tphy-mode = \"rgmii\";\n\t\tphy-handle = <&phy4>;\n\t};\n\n\tport@5 {\n\t\tstatus = \"okay\";\n\t\tphy-mode = \"rgmii\";\n\t\tphy-handle = <&phy5>;\n\t};\n\n\tmdio-bus {\n\t\tstatus = \"okay\";\n\n\t\tphy4: ethernet-phy@4 {\n\t\t\treg = <4>;\n\t\t\tphy-mode = \"rgmii\";\n\t\t};\n\n\t\tphy5: ethernet-phy@5 {\n\t\t\treg = <5>;\n\t\t\tphy-mode = \"rgmii\";\n\t\t};\n\t};\n};\n\n&gsw {\n\tmediatek,port4-gmac;\n\tmediatek,ephy-base = /bits/ 8 <8>;\n};\n\n&sdhci {\n\tstatus = \"okay\";\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&ehci {\n\tstatus = \"okay\";\n};\n\n&ohci {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620a_ralink_mt7620a-mt7530-evb.dts",
    "content": "#include \"mt7620a.dtsi\"\n\n/ {\n\tcompatible = \"ralink,mt7620a-mt7530-evb\", \"ralink,mt7620a-soc\";\n\tmodel = \"Ralink MT7620a + MT7530 evaluation board\";\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x7b0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"uartf\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&rgmii1_pins &rgmii2_pins &mdio_pins>;\n\n\tmediatek,portmap = \"llllw\";\n\n\tport@5 {\n\t\tstatus = \"okay\";\n\t\tmediatek,fixed-link = <1000 1 1 1>;\n\t\tphy-mode = \"rgmii\";\n\t};\n\n\tmdio-bus {\n\t\tstatus = \"okay\";\n\n\t\tphy0: ethernet-phy@0 {\n\t\t\treg = <0>;\n\t\t\tphy-mode = \"rgmii\";\n\t\t};\n\n\t\tphy1: ethernet-phy@1 {\n\t\t\treg = <1>;\n\t\t\tphy-mode = \"rgmii\";\n\t\t};\n\n\t\tphy2: ethernet-phy@2 {\n\t\t\treg = <2>;\n\t\t\tphy-mode = \"rgmii\";\n\t\t};\n\n\t\tphy3: ethernet-phy@3 {\n\t\t\treg = <3>;\n\t\t\tphy-mode = \"rgmii\";\n\t\t};\n\n\t\tphy4: ethernet-phy@4 {\n\t\t\treg = <4>;\n\t\t\tphy-mode = \"rgmii\";\n\t\t};\n\n\t\tphy1f: ethernet-phy@1f {\n\t\t\treg = <0x1f>;\n\t\t\tphy-mode = \"rgmii\";\n\t\t};\n\t};\n};\n\n&gsw {\n\tmediatek,ephy-base = /bits/ 8 <12>;\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&ehci {\n\tstatus = \"okay\";\n};\n\n&ohci {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620a_ralink_mt7620a-mt7610e-evb.dts",
    "content": "#include \"mt7620a.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"ralink,mt7620a-mt7610e-evb\", \"ralink,mt7620a-soc\";\n\tmodel = \"Ralink MT7620A evaluation board\";\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio0 12 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_0>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 13 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_1>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <1000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x7b0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&ethernet {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&ephy_pins>;\n\n\tmediatek,portmap = \"llllw\";\n};\n\n&sdhci {\n\tstatus = \"okay\";\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\twifi@0,0 {\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620a_ralink_mt7620a-v22sg-evb.dts",
    "content": "#include \"mt7620a.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"ralink,mt7620a-v22sg-evb\", \"ralink,mt7620a-soc\";\n\tmodel = \"Ralink MT7620a V22SG High Power evaluation board\";\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 1 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\taoss {\n\t\t\tlabel = \"aoss\";\n\t\t\tgpios = <&gpio0 2 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n\n\tnand {\n\t\tcompatible = \"mtk,mt7620-nand\";\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x40000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x40000 0x20000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@60000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x60000 0x20000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@80000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x80000 0x7f80000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"uartf\", \"spi\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&rgmii1_pins &rgmii2_pins &mdio_pins>;\n\n\tmediatek,portmap = \"llllw\";\n\n\tport@4 {\n\t\tstatus = \"okay\";\n\t\tphy-handle = <&phy4>;\n\t\tphy-mode = \"rgmii\";\n\t};\n\n\tport@5 {\n\t\tstatus = \"okay\";\n\t\tphy-handle = <&phy5>;\n\t\tphy-mode = \"rgmii\";\n\t};\n\n\tmdio-bus {\n\t\tstatus = \"okay\";\n\n\t\tphy4: ethernet-phy@4 {\n\t\t\treg = <4>;\n\t\t\tphy-mode = \"rgmii\";\n\t\t};\n\n\t\tphy5: ethernet-phy@5 {\n\t\t\treg = <5>;\n\t\t\tphy-mode = \"rgmii\";\n\t\t};\n\t};\n};\n\n&gsw {\n\tmediatek,port4-gmac;\n\tmediatek,ephy-base = /bits/ 8 <8>;\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&ehci {\n\tstatus = \"okay\";\n};\n\n&ohci {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620a_sanlinking_d240.dts",
    "content": "// SPDX-License-Identifier: BSD-3-Clause\n/*\n *  Copyright(c) 2017 Kristian Evensen <kristian.evensen@gmail.com>.\n *  All rights reserved.\n */\n\n#include \"mt7620a.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"sanlinking,d240\", \"ralink,mt7620a-soc\";\n\tmodel = \"Sanlinking Technologies D240\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200\";\n\t};\n\n\tgpio-export {\n\t\tcompatible = \"gpio-export\";\n\t\t#size-cells = <0>;\n\n\t\tpower_mpcie2 {\n\t\t\tgpio-export,name = \"power_mpcie2\";\n\t\t\tgpio-export,output = <1>;\n\t\t\tgpios = <&gpio2 5 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tpower_mpcie1 {\n\t\t\tgpio-export,name = \"power_mpcie1\";\n\t\t\tgpio-export,output = <1>;\n\t\t\tgpios = <&gpio2 6 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"blue:power\";\n\t\t\tgpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tusb {\n\t\t\tlabel = \"blue:usb\";\n\t\t\tgpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;\n\t\t\ttrigger-sources = <&ohci_port1>, <&ehci_port1>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\n\t\tair {\n\t\t\tlabel = \"blue:wifi\";\n\t\t\tgpios = <&gpio3 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 1 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n};\n\n&gpio1 {\n\tstatus = \"okay\";\n};\n\n&gpio2 {\n\tstatus = \"okay\";\n};\n\n&gpio3 {\n\tstatus = \"okay\";\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0xfb0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&sdhci {\n\tstatus = \"okay\";\n\t/* the pins function is already set during pinmux driver load */\n\t/delete-property/ pinctrl-0;\n};\n\n&ehci {\n\tstatus = \"okay\";\n};\n\n&ohci {\n\tstatus = \"okay\";\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tmediatek,portmap = \"llllw\";\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&state_default {\n\tdefault {\n\t\tgroups = \"i2c\", \"uartf\", \"wled\", \"spi refclk\", \"pa\";\n\t\tfunction = \"gpio\";\n\t};\n\n\t/*\n\t * The sd function of the nd_sd group configures two of the\n\t * groups pins as gpios. The pins are used as PCIe reset/power.\n\t * Due to the driver load order, the pins are configured way to\n\t * late if triggered by the sd-card driver.\n\t * To not introduce another kind of driver load order\n\t * dependency and configure the pins as early as possible,\n\t * means during pinmux driver load.\n\t */\n\tgpio_sd {\n\t\tgroups = \"nd_sd\";\n\t\tfunction = \"sd\";\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620a_sercomm_na930.dts",
    "content": "#include \"mt7620a.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"sercomm,na930\", \"ralink,mt7620a-soc\";\n\tmodel = \"Sercomm NA930\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyS1,57600\";\n\t};\n\n\tnand {\n\t\tcompatible = \"mtk,mt7620-nand\";\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x20000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@200000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x200000 0x40000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@240000 {\n\t\t\t\tlabel = \"Config\";\n\t\t\t\treg = <0x240000 0x400000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@640000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x640000 0x1400000>;\n\t\t\t};\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 11 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\tzwave {\n\t\t\tlabel = \"zwave\";\n\t\t\tgpios = <&gpio0 12 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_0>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio0 14 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tzwave {\n\t\t\tlabel = \"blue:zwave\";\n\t\t\tgpios = <&gpio2 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tstatus {\n\t\t\tlabel = \"blue:status\";\n\t\t\tgpios = <&gpio2 26 GPIO_ACTIVE_LOW>;\n\t\t\ttrigger-sources = <&ohci_port1>, <&ehci_port1>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\n\t\tservice {\n\t\t\tlabel = \"blue:service\";\n\t\t\tgpios = <&gpio2 28 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_power: power {\n\t\t\tlabel = \"blue:power\";\n\t\t\tgpios = <&gpio2 29 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tgpio_export {\n\t\tcompatible = \"gpio-export\";\n\t\t#size-cells = <0>;\n\n\t\ttelit {\n\t\t\tgpio-export,name = \"telit\";\n\t\t\tgpio-export,output = <1>;\n\t\t\tgpios = <&gpio0 13 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"rgmii2\", \"spi\", \"ephy\";\n\t\tfunction = \"gpio\";\n\t};\n\n\tuartf_gpio {\n\t\tgroups = \"uartf\";\n\t\tfunction = \"gpio uartf\";\n\t};\n};\n\n&uart {\n\tstatus = \"okay\";\n};\n\n&gpio2 {\n\tstatus = \"okay\";\n};\n\n&ethernet {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&rgmii1_pins &mdio_pins>;\n\n\tmediatek,portmap = \"llllw\";\n\n\tport@4 {\n\t\tstatus = \"okay\";\n\t\tphy-handle = <&phy4>;\n\t\tphy-mode = \"rgmii\";\n\t};\n\n\tport@5 {\n\t\tstatus = \"okay\";\n\t\tphy-handle = <&phy5>;\n\t\tphy-mode = \"rgmii\";\n\t};\n\n\tmdio-bus {\n\t\tstatus = \"okay\";\n\n\t\tphy4: ethernet-phy@4 {\n\t\t\treg = <4>;\n\t\t\tphy-mode = \"rgmii\";\n\t\t};\n\n\t\tphy5: ethernet-phy@5 {\n\t\t\treg = <5>;\n\t\t\tphy-mode = \"rgmii\";\n\t\t};\n\t};\n};\n\n&gsw {\n\tmediatek,port4-gmac;\n\tmediatek,ephy-base = /bits/ 8 <8>;\n};\n\n&ehci {\n\tstatus = \"okay\";\n};\n\n&ohci {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620a_sitecom_wlr-4100-v1-002.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7620a.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"sitecom,wlr-4100-v1-002\", \"ralink,mt7620a-soc\";\n\tmodel = \"Sitecom WLR-4100 v1 002\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200\";\n\t};\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"amber:power\";\n\t\t\tgpios = <&gpio0 9 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\twifi {\n\t\t\tlabel = \"blue:wifi\";\n\t\t\tgpios = <&gpio3 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"white:wps\";\n\t\t\tgpios = <&gpio1 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio0 2 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 1 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tgpio_export {\n\t\tcompatible = \"gpio-export\";\n\t\t#size-cells = <0>;\n\n\t\tusb-power {\n\t\t\tgpio-export,name = \"usb-power\";\n\t\t\tgpio-export,output = <1>;\n\t\t\tgpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&gpio1 {\n\tstatus = \"okay\";\n};\n\n&gpio3 {\n\tstatus = \"okay\";\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <20000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"uboot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x790000>;\n\t\t\t};\n\n\t\t\tpartition@7e0000 {\n\t\t\t\tlabel = \"backup\";\n\t\t\t\treg = <0x7e0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@7f0000 {\n\t\t\t\tlabel = \"storage\";\n\t\t\t\treg = <0x7f0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&ethernet {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&rgmii1_pins &mdio_pins>;\n\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tport@5 {\n\t\tstatus = \"okay\";\n\n\t\tphy-mode = \"rgmii\";\n\t\tmediatek,fixed-link = <1000 1 1 1>;\n\t};\n\n\tmdio-bus {\n\t\tstatus = \"okay\";\n\n\t\tethernet-phy@0 {\n\t\t\treg = <0>;\n\t\t\tphy-mode = \"rgmii\";\n\n\t\t\tqca,ar8327-initvals = <\n\t\t\t\t0x04 0x06200000  /* PORT0 PAD MODE CTRL */\n\t\t\t\t0x08 0x01000000  /* PORT5 PAD MODE CTRL  RX delay EN all ports 0, 5, 6 */\n\t\t\t\t0x7c 0x0000007e  /* PORT0_STATUS */\n\t\t\t\t0x94 0x00000000  /* PORT6_STATUS */\n\t\t\t>;\n\t\t};\n\t};\n};\n\n&gsw {\n\tmediatek,ephy-base = /bits/ 8 <8>;\n};\n\n&ehci {\n\tstatus = \"okay\";\n};\n\n&ohci {\n\tstatus = \"okay\";\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"uartf\", \"i2c\", \"wled\", \"spi refclk\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620a_tplink_archer-c2-v1.dts",
    "content": "#include \"mt7620a.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"tplink,archer-c2-v1\", \"ralink,mt7620a-soc\";\n\tmodel = \"TP-Link Archer C2 v1\";\n\n\taliases {\n\t\tled-boot = &led_wps;\n\t\tled-failsafe = &led_wps;\n\t\tled-running = &led_wps;\n\t\tled-upgrade = &led_wps;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200\";\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tlan {\n\t\t\tlabel = \"green:lan\";\n\t\t\tgpios = <&gpio0 1 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tusb {\n\t\t\tlabel = \"green:usb\";\n\t\t\tgpios = <&gpio0 11 GPIO_ACTIVE_LOW>;\n\t\t\ttrigger-sources = <&ohci_port1>, <&ehci_port1>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\n\t\tled_wps: wps {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&gpio1 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twan {\n\t\t\tlabel = \"green:wan\";\n\t\t\tgpios = <&gpio2 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan {\n\t\t\tlabel = \"green:wlan\";\n\t\t\tgpios = <&gpio3 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset_wps {\n\t\t\tlabel = \"reset_wps\";\n\t\t\tgpios = <&gpio0 13 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\trfkill {\n\t\t\tlabel = \"rfkill\";\n\t\t\tgpios = <&gpio0 2 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RFKILL>;\n\t\t};\n\t};\n\n\trtl8367rb {\n\t\tcompatible = \"realtek,rtl8367b\", \"rtl8367b\";\n\t\tcpu_port = <6>;\n\t\trealtek,extif1 = <1 0 1 1 1 1 1 1 2>;\n\t\tmii-bus = <&mdio0>;\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <30000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x20000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tcompatible = \"tplink,firmware\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x20000 0x7a0000>;\n\t\t\t};\n\n\t\t\tpartition@7c0000 {\n\t\t\t\tlabel = \"config\";\n\t\t\t\treg = <0x7c0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\trom: partition@7d0000 {\n\t\t\t\tlabel = \"rom\";\n\t\t\t\treg = <0x7d0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@7e0000 {\n\t\t\t\tlabel = \"romfile\";\n\t\t\t\treg = <0x7e0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tradio: partition@7f0000 {\n\t\t\t\tlabel = \"radio\";\n\t\t\t\treg = <0x7f0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&ethernet {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&rgmii1_pins &rgmii2_pins &mdio_pins>;\n\n\tnvmem-cells = <&macaddr_rom_f100>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tport@5 {\n\t\tstatus = \"okay\";\n\t\tmediatek,fixed-link = <1000 1 1 1>;\n\t\tphy-mode = \"rgmii\";\n\t};\n\n\tmdio0: mdio-bus {\n\t\tstatus = \"okay\";\n\t};\n};\n\n&gpio1 {\n\tstatus = \"okay\";\n};\n\n&gpio2 {\n\tstatus = \"okay\";\n};\n\n&gpio3 {\n\tstatus = \"okay\";\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"uartf\", \"wled\", \"ephy\", \"spi refclk\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&radio 0x0>;\n\tnvmem-cells = <&macaddr_rom_f100>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&ehci {\n\tstatus = \"okay\";\n};\n\n&ohci {\n\tstatus = \"okay\";\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\tmt76@0,0 {\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&radio 0x8000>;\n\t\tnvmem-cells = <&macaddr_rom_f100>;\n\t\tnvmem-cell-names = \"mac-address\";\n\t\tmac-address-increment = <(-1)>;\n\t};\n};\n\n&rom {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_rom_f100: macaddr@f100 {\n\t\treg = <0xf100 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620a_tplink_archer-c20-v1.dts",
    "content": "#include \"mt7620a_tplink_archer.dtsi\"\n\n/ {\n\tcompatible = \"tplink,archer-c20-v1\", \"ralink,mt7620a-soc\";\n\tmodel = \"TP-Link Archer C20 v1\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tlan {\n\t\t\tlabel = \"blue:lan\";\n\t\t\tgpios = <&gpio0 1 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_power: power {\n\t\t\tlabel = \"blue:power\";\n\t\t\tgpios = <&gpio0 7 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"keep\";\n\t\t};\n\n\t\tusb {\n\t\t\tlabel = \"blue:usb\";\n\t\t\tgpios = <&gpio2 4 GPIO_ACTIVE_LOW>;\n\t\t\ttrigger-sources = <&ohci_port1>, <&ehci_port1>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\n\t\twan {\n\t\t\tlabel = \"blue:wan\";\n\t\t\tgpios = <&gpio0 11 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\twan_orange {\n\t\t\tlabel = \"orange:wan\";\n\t\t\tgpios = <&gpio0 9 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\twlan5g {\n\t\t\tlabel = \"blue:wlan5g\";\n\t\t\tgpios = <&gpio0 17 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\twlan2g {\n\t\t\tlabel = \"blue:wlan2g\";\n\t\t\tgpios = <&gpio3 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"blue:wps\";\n\t\t\tgpios = <&gpio1 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"uartf\", \"wled\", \"ephy\", \"spi refclk\", \"wdt\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&wmac {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pa_pins>;\n\n\tnvmem-cells = <&macaddr_rom_f100>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <(-2)>;\n};\n\n&wifi {\n\tnvmem-cells = <&macaddr_rom_f100>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <(-1)>;\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620a_tplink_archer-c20i.dts",
    "content": "#include \"mt7620a_tplink_archer.dtsi\"\n\n/ {\n\tcompatible = \"tplink,archer-c20i\", \"ralink,mt7620a-soc\";\n\tmodel = \"TP-Link Archer C20i\";\n\n\taliases {\n\t\tled-boot = &led_wps;\n\t\tled-failsafe = &led_wps;\n\t\tled-running = &led_wps;\n\t\tled-upgrade = &led_wps;\n\t\tlabel-mac-device = &ethernet;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tlan {\n\t\t\tlabel = \"blue:lan\";\n\t\t\tgpios = <&gpio0 1 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tusb {\n\t\t\tlabel = \"blue:usb\";\n\t\t\tgpios = <&gpio0 11 GPIO_ACTIVE_LOW>;\n\t\t\ttrigger-sources = <&ohci_port1>, <&ehci_port1>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\n\t\tled_wps: wps {\n\t\t\tlabel = \"blue:wps\";\n\t\t\tgpios = <&gpio1 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twan {\n\t\t\tlabel = \"blue:wan\";\n\t\t\tgpios = <&gpio2 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan {\n\t\t\tlabel = \"blue:wlan\";\n\t\t\tgpios = <&gpio3 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"uartf\", \"rgmii1\", \"rgmii2\", \"wled\", \"nd_sd\", \"ephy\", \"spi refclk\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&wmac {\n\tnvmem-cells = <&macaddr_rom_f100>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wifi {\n\tnvmem-cells = <&macaddr_rom_f100>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <(-1)>;\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620a_tplink_archer-c50-v1.dts",
    "content": "#include \"mt7620a_tplink_archer.dtsi\"\n\n/ {\n\tcompatible = \"tplink,archer-c50-v1\", \"ralink,mt7620a-soc\";\n\tmodel = \"TP-Link Archer C50 v1\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tlan {\n\t\t\tlabel = \"green:lan\";\n\t\t\tgpios = <&gpio0 1 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_power: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio0 7 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\tusb {\n\t\t\tlabel = \"green:usb\";\n\t\t\tgpios = <&gpio0 9 GPIO_ACTIVE_LOW>;\n\t\t\ttrigger-sources = <&ohci_port1>, <&ehci_port1>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\n\t\twan {\n\t\t\tlabel = \"green:wan\";\n\t\t\tgpios = <&gpio0 17 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twan_orange {\n\t\t\tlabel = \"orange:wan\";\n\t\t\tgpios = <&gpio2 4 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan5g {\n\t\t\tlabel = \"green:wlan5g\";\n\t\t\tgpios = <&gpio0 11 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\twlan2g {\n\t\t\tlabel = \"green:wlan2g\";\n\t\t\tgpios = <&gpio3 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&gpio1 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"uartf\", \"rgmii1\", \"rgmii2\", \"wled\", \"ephy\", \"spi refclk\", \"mdio\", \"wdt\", \"nd_sd\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&wmac {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pa_pins>;\n\n\tnvmem-cells = <&macaddr_rom_f100>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <(-2)>;\n};\n\n&wifi {\n\tnvmem-cells = <&macaddr_rom_f100>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <(-1)>;\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620a_tplink_archer-mr200.dts",
    "content": "#include \"mt7620a.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"tplink,archer-mr200\", \"ralink,mt7620a-soc\";\n\tmodel = \"TP-Link Archer MR200\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200\";\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tlan {\n\t\t\tlabel = \"white:lan\";\n\t\t\tgpios = <&gpio0 1 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twan {\n\t\t\tlabel = \"white:wan\";\n\t\t\tgpios = <&gpio0 8 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_power: power {\n\t\t\tlabel = \"white:power\";\n\t\t\tgpios = <&gpio0 12 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\t4g {\n\t\t\tlabel = \"white:4g\";\n\t\t\tgpios = <&gpio0 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"white:wps\";\n\t\t\tgpios = <&gpio1 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tsignal1 {\n\t\t\tlabel = \"white:signal1\";\n\t\t\tgpios = <&gpio2 1 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tsignal2 {\n\t\t\tlabel = \"white:signal2\";\n\t\t\tgpios = <&gpio2 2 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tsignal3 {\n\t\t\tlabel = \"white:signal3\";\n\t\t\tgpios = <&gpio2 3 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tsignal4 {\n\t\t\tlabel = \"white:signal4\";\n\t\t\tgpios = <&gpio2 4 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan {\n\t\t\tlabel = \"white:wlan\";\n\t\t\tgpios = <&gpio3 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 13 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\trfkill {\n\t\t\tlabel = \"rfkill\";\n\t\t\tgpios = <&gpio0 9 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = <KEY_RFKILL>;\n\t\t};\n\t};\n\n\tgpio_export {\n\t\tcompatible = \"gpio-export\";\n\t\t#size-cells = <0>;\n\n\t\tpower_usb {\n\t\t\tgpio-export,name = \"power_usb1\";\n\t\t\tgpio-export,output = <1>;\n\t\t\tgpios = <&gpio0 11 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&gpio1 {\n\tstatus = \"okay\";\n};\n\n&gpio2 {\n\tstatus = \"okay\";\n};\n\n&gpio3 {\n\tstatus = \"okay\";\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <30000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x20000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tcompatible = \"tplink,firmware\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x20000 0x7b0000>;\n\t\t\t};\n\n\t\t\trom: partition@7d0000 {\n\t\t\t\tlabel = \"rom\";\n\t\t\t\treg = <0x7d0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@7e0000 {\n\t\t\t\tlabel = \"romfile\";\n\t\t\t\treg = <0x7e0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tradio: partition@7f0000 {\n\t\t\t\tlabel = \"radio\";\n\t\t\t\treg = <0x7f0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"uartf\", \"rgmii1\", \"rgmii2\", \"wled\", \"nd_sd\", \"ephy\", \"spi refclk\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_rom_f100>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&ehci {\n\tstatus = \"okay\";\n};\n\n&ohci {\n\tstatus = \"okay\";\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&radio 0x0>;\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\tmt76@0,0 {\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&radio 0x8000>;\n\t};\n};\n\n&rom {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_rom_f100: macaddr@f100 {\n\t\treg = <0xf100 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620a_tplink_archer.dtsi",
    "content": "#include \"mt7620a.dtsi\"\n\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/gpio/gpio.h>\n\n/ {\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 13 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\trfkill {\n\t\t\tlabel = \"rfkill\";\n\t\t\tgpios = <&gpio0 2 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RFKILL>;\n\t\t};\n\t};\n};\n\n&gpio1 {\n\tstatus = \"okay\";\n};\n\n&gpio2 {\n\tstatus = \"okay\";\n};\n\n&gpio3 {\n\tstatus = \"okay\";\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <30000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x20000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tcompatible = \"tplink,firmware\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x20000 0x7a0000>;\n\t\t\t};\n\n\t\t\tpartition@7c0000 {\n\t\t\t\tlabel = \"config\";\n\t\t\t\treg = <0x7c0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\trom: partition@7d0000 {\n\t\t\t\tlabel = \"rom\";\n\t\t\t\treg = <0x7d0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@7e0000 {\n\t\t\t\tlabel = \"romfile\";\n\t\t\t\treg = <0x7e0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tradio: partition@7f0000 {\n\t\t\t\tlabel = \"radio\";\n\t\t\t\treg = <0x7f0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&ethernet {\n\tpinctrl-names = \"default\";\n\n\tnvmem-cells = <&macaddr_rom_f100>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tmediatek,portmap = \"wllll\";\n};\n\n&ehci {\n\tstatus = \"okay\";\n};\n\n&ohci {\n\tstatus = \"okay\";\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&radio 0x0>;\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\twifi: mt76@0,0 {\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&radio 0x8000>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\t};\n};\n\n&rom {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_rom_f100: macaddr@f100 {\n\t\treg = <0xf100 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620a_tplink_re200-v1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7620a_tplink_re2x0-v1.dtsi\"\n\n/ {\n\tcompatible = \"tplink,re200-v1\", \"ralink,mt7620a-soc\";\n\tmodel = \"TP-Link RE200 v1\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio1 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan {\n\t\t\tlabel = \"green:lan\";\n\t\t\tgpios = <&gpio2 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan {\n\t\t\tlabel = \"green:wlan\";\n\t\t\tgpios = <&gpio1 3 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tqss {\n\t\t\tlabel = \"green:qss\";\n\t\t\tgpios = <&gpio1 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan2g_red {\n\t\t\tlabel = \"red:wlan2g\";\n\t\t\tgpios = <&gpio0 2 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan2g_green {\n\t\t\tlabel = \"green:wlan2g\";\n\t\t\tgpios = <&gpio3 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\t};\n};\n\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"uartf\", \"ephy\", \"wled\", \"rgmii1\", \"spi refclk\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&gpio1 {\n\tstatus = \"okay\";\n};\n\n&gpio2 {\n\tstatus = \"okay\";\n};\n\n&gpio3 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620a_tplink_re210-v1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7620a_tplink_re2x0-v1.dtsi\"\n\n/ {\n\tcompatible = \"tplink,re210-v1\", \"ralink,mt7620a-soc\";\n\tmodel = \"TP-Link RE210 v1\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio1 3 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\trssi_high {\n\t\t\tlabel = \"green:rssi-high\";\n\t\t\tgpios = <&gpio1 1 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\trssi_low {\n\t\t\tlabel = \"red:rssi-low\";\n\t\t\tgpios = <&gpio1 2 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan2g {\n\t\t\tlabel = \"green:wlan2g\";\n\t\t\tgpios = <&gpio3 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\n\t\twlan5g {\n\t\t\tlabel = \"green:wlan5g\";\n\t\t\tgpios = <&gpio0 1 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\t};\n};\n\n&keys {\n\tled_power {\n\t\tlabel = \"LED power\";\n\t\tgpios = <&gpio1 0 GPIO_ACTIVE_LOW>;\n\t\tlinux,code = <BTN_0>;\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"uartf\", \"wled\", \"rgmii1\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&gsw {\n\tmediatek,port4-gmac;\n\tmediatek,ephy-base = /bits/ 8 <8>;\n};\n\n&ethernet {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&rgmii2_pins &mdio_pins>;\n\n\tport@4 {\n\t\tstatus = \"okay\";\n\n\t\tphy-handle = <&phy4>;\n\t\tphy-mode = \"rgmii\";\n\t};\n\n\tmdio-bus {\n\t\tstatus = \"okay\";\n\n\t\tphy4: ethernet-phy@4 {\n\t\t\treg = <4>;\n\t\t\tphy-mode = \"rgmii\";\n\t\t};\n\t};\n};\n\n&gpio1 {\n\tstatus = \"okay\";\n};\n\n&gpio3 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620a_tplink_re2x0-v1.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7620a.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\taliases {\n\t\tlabel-mac-device = &ethernet;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,57600n8\";\n\t};\n\n\tkeys: keys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 13 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio0 12 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <50000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tuboot: partition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x20000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tcompatible = \"tplink,firmware\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x20000 0x7c0000>;\n\t\t\t};\n\n\t\t\tpartition@7e0000 {\n\t\t\t\tlabel = \"config\";\n\t\t\t\treg = <0x7e0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tradio: partition@7f0000 {\n\t\t\t\tlabel = \"radio\";\n\t\t\t\treg = <0x7f0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_uboot_1fc00>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&radio 0x0>;\n\tnvmem-cells = <&macaddr_uboot_1fc00>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\tmt76@0,0 {\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&radio 0x8000>;\n\t\tnvmem-cells = <&macaddr_uboot_1fc00>;\n\t\tnvmem-cell-names = \"mac-address\";\n\t\tmac-address-increment = <2>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\t};\n};\n\n&uboot {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_uboot_1fc00: macaddr@1fc00 {\n\t\treg = <0x1fc00 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620a_trendnet_tew-810dr.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7620a_cameo_810.dtsi\"\n\n/ {\n\tcompatible = \"trendnet,tew-810dr\", \"ralink,mt7620a-soc\";\n\tmodel = \"TRENDnet TEW-810DR\";\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620a_wavlink_wl-wn530hg4.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later\n\n#include \"mt7620a.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"wavlink,wl-wn530hg4\", \"ralink,mt7620a-soc\";\n\tmodel = \"Wavlink WL-WN530HG4\";\n\n\taliases {\n\t\tled-boot = &led_status_blue;\n\t\tled-failsafe = &led_status_blue;\n\t\tled-running = &led_status_blue;\n\t\tled-upgrade = &led_status_blue;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_status_blue: status_blue {\n\t\t\tlabel = \"blue:status\";\n\t\t\tgpios = <&gpio0 10 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tstatus_yellow {\n\t\t\tlabel = \"yellow:status\";\n\t\t\tgpios = <&gpio0 11 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tstatus_red {\n\t\t\tlabel = \"red:status\";\n\t\t\tgpios = <&gpio0 8 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 1 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <24000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"config\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x7b0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"uartf\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&rgmii2_pins &mdio_pins>;\n\n\tnvmem-cells = <&macaddr_factory_28>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tmediatek,portmap = \"llllw\";\n\n\tport@5 {\n\t\tstatus = \"okay\";\n\t\tphy-handle = <&phy5>;\n\t\tphy-mode = \"rgmii\";\n\t};\n\n\tmdio-bus {\n\t\tstatus = \"okay\";\n\n\t\tphy5: ethernet-phy@5 {\n\t\t\treg = <5>;\n\t\t\tphy-mode = \"rgmii\";\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\tmt76@0,0 {\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\t};\n};\n\n&wmac {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pa_pins>;\n\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_28: macaddr@28 {\n\t\treg = <0x28 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620a_wavlink_wl-wn535k1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later\n\n#include \"mt7620a.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"wavlink,wl-wn535k1\", \"ralink,mt7620a-soc\";\n\tmodel = \"Wavlink WL-WN535K1\";\n\n\taliases {\n\t\tlabel-mac-device = &wifi0;\n\t\tled-boot = &led_status_blue;\n\t\tled-failsafe = &led_status_red;\n\t\tled-running = &led_status_blue;\n\t\tled-upgrade = &led_status_red;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 1 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\ttouchlink {\n\t\t\tlabel = \"touchlink\";\n\t\t\tgpios = <&gpio0 11 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_status_blue: status_blue {\n\t\t\tlabel = \"blue:status\";\n\t\t\tgpios = <&gpio0 9 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tled_status_red: status_red {\n\t\t\tlabel = \"red:status\";\n\t\t\tgpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tlan1 {\n\t\t\tlabel = \"green:lan1\";\n\t\t\tgpios = <&gpio2 2 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan2 {\n\t\t\tlabel = \"green:lan2\";\n\t\t\tgpios = <&gpio2 3 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twan {\n\t\t\tlabel = \"green:wan\";\n\t\t\tgpios = <&gpio2 4 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&gpio2 {\n\tstatus = \"okay\";\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <50000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"config\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\n\t\t\t\tcompatible = \"nvmem-cells\";\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\n\t\t\t\tmacaddr_factory_28: macaddr@28 {\n\t\t\t\t\treg = <0x28 0x6>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x730000>;\n\t\t\t};\n\n\t\t\tpartition@780000 {\n\t\t\t\tlabel = \"vendor\";\n\t\t\t\treg = <0x780000 0x80000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\twifi0: wifi@0,0 {\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\t};\n};\n\n&ethernet {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&rgmii1_pins &rgmii2_pins &mdio_pins>;\n\n\tnvmem-cells = <&macaddr_factory_28>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tmediatek,portmap = \"llllw\";\n\n\tport@4 {\n\t\tstatus = \"okay\";\n\t\tphy-handle = <&phy4>;\n\t\tphy-mode = \"rgmii\";\n\t};\n\n\tport@5 {\n\t\tstatus = \"okay\";\n\t\tphy-handle = <&phy5>;\n\t\tphy-mode = \"rgmii\";\n\t};\n\n\tmdio-bus {\n\t\tstatus = \"okay\";\n\n\t\tphy4: ethernet-phy@4 {\n\t\t\treg = <4>;\n\t\t\tphy-mode = \"rgmii\";\n\t\t};\n\n\t\tphy5: ethernet-phy@5 {\n\t\t\treg = <5>;\n\t\t\tphy-mode = \"rgmii\";\n\t\t};\n\t};\n};\n\n&gsw {\n\tmediatek,port4-gmac;\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"ephy\", \"i2c\", \"uartf\";\n\t\tfunction = \"gpio\";\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620a_wavlink_wl-wn579x3.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later\n\n#include \"mt7620a.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"wavlink,wl-wn579x3\", \"ralink,mt7620a-soc\";\n\tmodel = \"Wavlink WL-WN579X3\";\n\n\taliases {\n\t\tled-boot = &led_wps;\n\t\tled-failsafe = &led_wps;\n\t\tled-running = &led_wps;\n\t\tled-upgrade = &led_wps;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 1 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio0 2 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\n\t\tswitch_aps {\n\t\t\tlabel = \"mode_aps\";\n\t\t\tgpios = <&gpio0 11 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_1>;\n\t\t\tlinux,input-type = <EV_SW>;\n\t\t};\n\n\t\tswitch_repeater {\n\t\t\tlabel = \"mode_repeater\";\n\t\t\tgpios = <&gpio0 9 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_0>;\n\t\t\tlinux,input-type = <EV_SW>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_wps: wps {\n\t\t\tlabel = \"blue:wps\";\n\t\t\tgpios = <&gpio2 2 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan {\n\t\t\tlabel = \"blue:lan\";\n\t\t\tgpios = <&gpio2 4 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twan {\n\t\t\tlabel = \"blue:wan\";\n\t\t\tgpios = <&gpio2 1 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twifi {\n\t\t\tlabel = \"blue:wifi\";\n\t\t\tgpios = <&gpio3 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\t/* These three form the signal wifi strength segments */\n\t\twifi_high {\n\t\t\tlabel = \"blue:wifi_high\";\n\t\t\tgpios = <&gpio0 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twifi_medium {\n\t\t\tlabel = \"blue:wifi_medium\";\n\t\t\tgpios = <&gpio0 12 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twifi_low {\n\t\t\tlabel = \"blue:wifi_low\";\n\t\t\tgpios = <&gpio2 3 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&gpio2 {\n\tstatus = \"okay\";\n};\n\n&gpio3 {\n\tstatus = \"okay\";\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <50000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"config\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x790000>;\n\t\t\t};\n\n\t\t\tpartition@7e0000 {\n\t\t\t\tlabel = \"board_data\";\n\t\t\t\treg = <0x7e0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@7f0000 {\n\t\t\t\tlabel = \"nvram\";\n\t\t\t\treg = <0x7f0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\twifi@0,0 {\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\t};\n};\n\n&ethernet {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&rgmii1_pins &rgmii2_pins &mdio_pins>;\n\n\tnvmem-cells = <&macaddr_factory_28>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tmediatek,portmap = \"llllw\";\n\n\tport@4 {\n\t\tstatus = \"okay\";\n\t\tphy-handle = <&phy4>;\n\t\tphy-mode = \"rgmii\";\n\t};\n\n\tport@5 {\n\t\tstatus = \"okay\";\n\t\tphy-handle = <&phy5>;\n\t\tphy-mode = \"rgmii\";\n\t};\n\n\tmdio-bus {\n\t\tstatus = \"okay\";\n\n\t\tphy4: ethernet-phy@4 {\n\t\t\treg = <4>;\n\t\t\tphy-mode = \"rgmii\";\n\t\t};\n\n\t\tphy5: ethernet-phy@5 {\n\t\t\treg = <5>;\n\t\t\tphy-mode = \"rgmii\";\n\t\t};\n\t};\n};\n\n&gsw {\n\tmediatek,port4-gmac;\n\tmediatek,ephy-base = /bits/ 8 <8>;\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"ephy\", \"i2c\", \"wled\", \"uartf\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_28: macaddr@28 {\n\t\treg = <0x28 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620a_wevo_air-duo.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7620a.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/leds/common.h>\n\n/ {\n\tcompatible = \"wevo,air-duo\", \"ralink,mt7620a-soc\";\n\tmodel = \"WeVO AIR DUO\";\n\n\taliases {\n\t\tled-boot = &led_status;\n\t\tled-failsafe = &led_status;\n\t\tled-running = &led_status;\n\t\tled-upgrade = &led_status;\n\t\tlabel-mac-device = &ethernet;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_status: led-0 {\n\t\t\tlabel = \"blue:status\";\n\t\t\tcolor = <LED_COLOR_ID_BLUE>;\n\t\t\tfunction = LED_FUNCTION_STATUS;\n\t\t\tgpios = <&gpio0 11 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled-1 {\n\t\t\tcolor = <LED_COLOR_ID_BLUE>;\n\t\t\tfunction = LED_FUNCTION_WPS;\n\t\t\tgpios = <&gpio1 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio0 1 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 2 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n};\n\n&gpio1 {\n\tstatus = \"okay\";\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <50000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"config\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\n\t\t\t\tcompatible = \"nvmem-cells\";\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\n\t\t\t\tmacaddr_factory_4: macaddr@4 {\n\t\t\t\t\treg = <0x4 0x6>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0xeb0000>;\n\t\t\t};\n\n\t\t\tpartition@f00000 {\n\t\t\t\tlabel = \"db\";\n\t\t\t\treg = <0xf00000 0x100000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"uartf\", \"spi refclk\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&rgmii1_pins &mdio_pins>;\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tport@5 {\n\t\tstatus = \"okay\";\n\t\tmediatek,fixed-link = <1000 1 1 1>;\n\t\tphy-mode = \"rgmii\";\n\t};\n\n\tmdio-bus {\n\t\tstatus = \"okay\";\n\n\t\tethernet-phy@0 {\n\t\t\treg = <0>;\n\t\t\tphy-mode = \"rgmii\";\n\t\t};\n\n\t\tethernet-phy@1 {\n\t\t\treg = <1>;\n\t\t\tphy-mode = \"rgmii\";\n\t\t};\n\n\t\tethernet-phy@2 {\n\t\t\treg = <2>;\n\t\t\tphy-mode = \"rgmii\";\n\t\t};\n\n\t\tethernet-phy@3 {\n\t\t\treg = <3>;\n\t\t\tphy-mode = \"rgmii\";\n\t\t};\n\n\t\tethernet-phy@4 {\n\t\t\treg = <4>;\n\t\t\tphy-mode = \"rgmii\";\n\t\t};\n\n\t\tethernet-phy@1f {\n\t\t\treg = <0x1f>;\n\t\t\tphy-mode = \"rgmii\";\n\t\t};\n\t};\n};\n\n&gsw {\n\tmediatek,ephy-base = /bits/ 8 <12>;\n};\n\n&ehci {\n\tstatus = \"okay\";\n};\n\n&ohci {\n\tstatus = \"okay\";\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\twifi@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\n\t\tled {\n\t\t\tled-sources = <2>;\n\t\t\tled-active-low;\n\t\t};\n\t};\n};\n\n&wmac {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&wled_pins>;\n\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620a_xiaomi_miwifi-mini.dts",
    "content": "#include \"mt7620a.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"xiaomi,miwifi-mini\", \"ralink,mt7620a-soc\";\n\tmodel = \"Xiaomi MiWiFi Mini\";\n\n\taliases {\n\t\tled-boot = &led_blue;\n\t\tled-failsafe = &led_blue;\n\t\tled-running = &led_blue;\n\t\tled-upgrade = &led_blue;\n\t\tlabel-mac-device = &ethernet;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200\";\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_blue: blue {\n\t\t\tlabel = \"blue:status\";\n\t\t\tgpios = <&gpio1 0 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\tyellow {\n\t\t\tlabel = \"yellow:status\";\n\t\t\tgpios = <&gpio1 2 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tred {\n\t\t\tlabel = \"red:status\";\n\t\t\tgpios = <&gpio1 5 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twan {\n\t\t\tlabel = \"green:wan\";\n\t\t\tgpios = <&gpio2 4 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan1 {\n\t\t\tlabel = \"green:lan1\";\n\t\t\tgpios = <&gpio2 1 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan2 {\n\t\t\tlabel = \"green:lan2\";\n\t\t\tgpios = <&gpio2 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n};\n\n&gpio1 {\n\tstatus = \"okay\";\n};\n\n&gpio2 {\n\tstatus = \"okay\";\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <70000000>;\n\t\tm25p,fast-read;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0xf80000>;\n\t\t\t};\n\n\t\t\tpartition@fd0000 {\n\t\t\t\tlabel = \"crash\";\n\t\t\t\treg = <0xfd0000 0x10000>;\n\t\t\t};\n\n\t\t\tpartition@fe0000 {\n\t\t\t\tlabel = \"reserved\";\n\t\t\t\treg = <0xfe0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@ff0000 {\n\t\t\t\tlabel = \"Bdata\";\n\t\t\t\treg = <0xff0000 0x10000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&ehci {\n\tstatus = \"okay\";\n};\n\n&ohci {\n\tstatus = \"okay\";\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_28>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tmediatek,portmap = \"llllw\";\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pa_pins>;\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\tmt76@0,0 {\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"ephy\", \"i2c\", \"rgmii1\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_28: macaddr@28 {\n\t\treg = <0x28 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620a_youku_yk-l1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7620a_youku_yk-l1.dtsi\"\n\n/ {\n\tcompatible = \"youku,yk-l1\", \"ralink,mt7620a-soc\";\n\tmodel = \"Youku YK-L1\";\n};\n\n&flash0 {\n\tbroken-flash-reset;\n};\n\n&firmware {\n\treg = <0x50000 0x1fb0000>;\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620a_youku_yk-l1.dtsi",
    "content": "#include \"mt7620a.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t\tlabel-mac-device = &ethernet;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twlan {\n\t\t\tlabel = \"blue:wlan\";\n\t\t\tgpios = <&gpio3 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\tusb {\n\t\t\tlabel = \"blue:usb\";\n\t\t\tgpios = <&gpio1 11 GPIO_ACTIVE_LOW>;\n\t\t\ttrigger-sources = <&ohci_port1>, <&ehci_port1>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\n\t\tled_power: power {\n\t\t\tlabel = \"blue:power\";\n\t\t\tgpios = <&gpio1 5 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 1 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n};\n\n&gpio1 {\n\tstatus = \"okay\";\n};\n\n&gpio3 {\n\tstatus = \"okay\";\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash0: flash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <80000000>;\n\t\tm25p,fast-read;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfirmware: partition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\t/* reg property is set based on flash size in DTS files */\n\t\t\t};\n\t\t};\n\t};\n};\n\n&state_default {\n\tdefault {\n\t\tgroups = \"i2c\", \"rgmii1\", \"wled\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&ephy_pins>;\n\n\tnvmem-cells = <&macaddr_factory_28>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tmediatek,portmap = \"llllw\";\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&sdhci {\n\tstatus = \"okay\";\n};\n\n&ehci {\n\tstatus = \"okay\";\n};\n\n&ohci {\n\tstatus = \"okay\";\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_28: macaddr@28 {\n\t\treg = <0x28 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620a_youku_yk-l1c.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7620a_youku_yk-l1.dtsi\"\n\n/ {\n\tcompatible = \"youku,yk-l1c\", \"ralink,mt7620a-soc\";\n\tmodel = \"Youku YK-L1c\";\n};\n\n&firmware {\n\treg = <0x50000 0xfb0000>;\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620a_yukai_bocco.dts",
    "content": "#include \"mt7620a.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"yukai,bocco\", \"ralink,mt7620a-soc\";\n\tmodel = \"YUKAI Engineering BOCCO\";\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio1 7 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tgpio_export {\n\t\tcompatible = \"gpio-export\";\n\t\t#size-cells = <0>;\n\n\t\ts1 {\n\t\t\tgpio-export,name = \"rec\";\n\t\t\tgpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t\ts2 {\n\t\t\tgpio-export,name = \"play\";\n\t\t\tgpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n\n\tsound {\n\t\tcompatible = \"simple-audio-card\";\n\t\tsimple-audio-card,name = \"Audio-I2S\";\n\t\tsimple-audio-card,format = \"i2s\";\n\t\tsimple-audio-card,bitclock-master = <&dailink0_master>;\n\t\tsimple-audio-card,frame-master = <&dailink0_master>;\n\t\tsimple-audio-card,widgets =\n\t\t\t\"Headphone\", \"Headphones\";\n\t\tsimple-audio-card,routing =\n\t\t\t\"Headphones\", \"HP_L\",\n\t\t\t\"Headphones\", \"HP_R\";\n\t\tsimple-audio-card,mclk-fs = <256>;\n\n\t\tsimple-audio-card,cpu {\n\t\t\tsound-dai = <&i2s>;\n\t\t};\n\n\t\tdailink0_master: simple-audio-card,codec {\n\t\t\tsound-dai = <&codec>;\n\t\t};\n\t};\n};\n\n&gpio1 {\n\tstatus = \"okay\";\n};\n\n&i2c {\n\tstatus = \"okay\";\n\n\tcodec: wm8960@1a {\n\t\t#sound-dai-cells = <0>;\n\t\tcompatible = \"wlf,wm8960\";\n\t\treg = <0x1a>;\n\n\t\twlf,shared-lrclk;\n\t};\n};\n\n&i2s {\n\t#sound-dai-cells = <0>;\n\tstatus = \"okay\";\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pcm_i2s_pins>;\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x7b0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pcm {\n\tstatus = \"okay\";\n};\n\n&gdma {\n\tstatus = \"okay\";\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"spi refclk\", \"rgmii1\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&ephy_pins>;\n\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tmediatek,portmap = \"llllw\";\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620a_zbtlink_zbt-ape522ii.dts",
    "content": "#include \"mt7620a.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"zbtlink,zbt-ape522ii\", \"ralink,mt7620a-soc\";\n\tmodel = \"Zbtlink ZBT-APE522II\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200\";\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tsys1 {\n\t\t\tlabel = \"green:sys1\";\n\t\t\tgpios = <&gpio0 11 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tsys2 {\n\t\t\tlabel = \"green:sys2\";\n\t\t\tgpios = <&gpio0 12 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tsys3 {\n\t\t\tlabel = \"green:sys3\";\n\t\t\tgpios = <&gpio0 9 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tsys4 {\n\t\t\tlabel = \"green:sys4\";\n\t\t\tgpios = <&gpio0 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan2g4 {\n\t\t\tlabel = \"green:wlan2g4\";\n\t\t\tgpios = <&gpio3 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 2 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n};\n\n&gpio3 {\n\tstatus = \"okay\";\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0xf80000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&ethernet {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&ephy_pins>;\n\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tmediatek,portmap = \"llllw\";\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pa_pins>;\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\tmt76@0,0 {\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"wled\", \"i2c\", \"uartf\", \"wdt\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620a_zbtlink_zbt-we1026-5g-16m.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7620a_zbtlink_zbt-we1026-5g.dtsi\"\n\n/ {\n\tcompatible = \"zbtlink,zbt-we1026-5g-16m\", \"zbtlink,zbt-we1026-5g\",\n\t\t\"zbtlink,zbt-we1026\", \"ralink,mt7620a-soc\";\n\tmodel = \"Zbtlink ZBT-WE1026-5G (16M)\";\n};\n\n&firmware {\n\treg = <0x50000 0xfb0000>;\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620a_zbtlink_zbt-we1026-5g.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7620a_zbtlink_zbt-we1026.dtsi\"\n\n/ {\n\tcompatible = \"zbtlink,zbt-we1026-5g\", \"zbtlink,zbt-we1026\",\n\t\t\"ralink,mt7620a-soc\";\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tlan {\n\t\t\tlabel = \"green:lan\";\n\t\t\tgpios = <&gpio2 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tusb {\n\t\t\tlabel = \"green:usb\";\n\t\t\tgpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;\n\t\t\ttrigger-sources = <&ohci_port1>, <&ehci_port1>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\n\t\twifi {\n\t\t\tlabel = \"green:wifi\";\n\t\t\tgpios = <&gpio3 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\twatchdog {\n\t\tcompatible = \"linux,wdt-gpio\";\n\t\tgpios = <&gpio0 11 GPIO_ACTIVE_HIGH>;\n\t\thw_algo = \"toggle\";\n\t\thw_margin_ms = <20000>;\n\t\talways-running;\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\twifi@0,0 {\n\t\tcompatible = \"pci14c3,7662\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620a_zbtlink_zbt-we1026-h-32m.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7620a_zbtlink_zbt-we1026-h.dtsi\"\n\n/ {\n\tcompatible = \"zbtlink,zbt-we1026-h-32m\", \"zbtlink,zbt-we1026-h\",\n\t\t\"zbtlink,zbt-we1026\", \"ralink,mt7620a-soc\";\n\tmodel = \"Zbtlink ZBT-WE1026-H (32M)\";\n};\n\n&flash0 {\n\tbroken-flash-reset;\n};\n\n&firmware {\n\treg = <0x50000 0x1fb0000>;\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620a_zbtlink_zbt-we1026-h.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7620a_zbtlink_zbt-we1026.dtsi\"\n\n/ {\n\tcompatible = \"zbtlink,zbt-we1026-h\", \"zbtlink,zbt-we1026\",\n\t\t\"ralink,mt7620a-soc\";\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tusb {\n\t\t\tlabel = \"green:usb\";\n\t\t\tgpios = <&gpio2 2 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan {\n\t\t\tlabel = \"green:lan\";\n\t\t\tgpios = <&gpio2 3 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twan {\n\t\t\tlabel = \"green:wan\";\n\t\t\tgpios = <&gpio2 4 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twifi {\n\t\t\tlabel = \"green:wifi\";\n\t\t\tgpios = <&gpio3 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620a_zbtlink_zbt-we1026.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7620a.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"zbtlink,zbt-we1026\", \"ralink,mt7620a-soc\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 1 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\taliases {\n\t\tlabel-mac-device = &wmac;\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash0: flash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfirmware: partition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t};\n\t\t};\n\t};\n};\n\n&gpio2 {\n\tstatus = \"okay\";\n};\n\n&gpio3 {\n\tstatus = \"okay\";\n};\n\n&sdhci {\n\tstatus = \"okay\";\n};\n\n&ehci {\n\tstatus = \"okay\";\n};\n\n&ohci {\n\tstatus = \"okay\";\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_28>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&state_default {\n\tdefault {\n\t\tgroups = \"i2c\", \"uartf\", \"spi refclk\", \"ephy\", \"wled\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_28: macaddr@28 {\n\t\treg = <0x28 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620a_zbtlink_zbt-we826-16m.dts",
    "content": "#include \"mt7620a_zbtlink_zbt-we826.dtsi\"\n\n/ {\n\tcompatible = \"zbtlink,zbt-we826-16m\", \"zbtlink,zbt-we826\", \"ralink,mt7620a-soc\";\n\tmodel = \"Zbtlink ZBT-WE826 (16M)\";\n};\n\n&firmware {\n\treg = <0x50000 0xfb0000>;\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620a_zbtlink_zbt-we826-32m.dts",
    "content": "#include \"mt7620a_zbtlink_zbt-we826.dtsi\"\n\n/ {\n\tcompatible = \"zbtlink,zbt-we826-32m\", \"zbtlink,zbt-we826\", \"ralink,mt7620a-soc\";\n\tmodel = \"Zbtlink ZBT-WE826 (32M)\";\n};\n\n&flash0 {\n\tbroken-flash-reset;\n};\n\n&firmware {\n\treg = <0x50000 0x1fb0000>;\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620a_zbtlink_zbt-we826-e.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7620a_zbtlink_zbt-we826.dtsi\"\n\n/ {\n\tcompatible = \"zbtlink,zbt-we826-e\", \"zbtlink,zbt-we826\", \"ralink,mt7620a-soc\";\n\tmodel = \"Zbtlink ZBT-WE826-E\";\n\n\t/delete-node/ leds;\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: gsm {\n\t\t\tlabel = \"blue:gsm\";\n\t\t\tgpios = <&gpio0 9 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tsignal {\n\t\t\tlabel = \"green:signal\";\n\t\t\tgpios = <&gpio0 11 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tsim {\n\t\t\tlabel = \"red:sim\";\n\t\t\tgpios = <&gpio0 12 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tair {\n\t\t\tlabel = \"red:wifi\";\n\t\t\tgpios = <&gpio3 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&flash0 {\n\tbroken-flash-reset;\n};\n\n&firmware {\n\treg = <0x50000 0x1fb0000>;\n};\n\n&state_default {\n\tdefault {\n\t\tgroups = \"i2c\", \"uartf\", \"wled\";\n\t\tfunction = \"gpio\";\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620a_zbtlink_zbt-we826.dtsi",
    "content": "#include \"mt7620a.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"zbtlink,zbt-we826\", \"ralink,mt7620a-soc\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200\";\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tusb {\n\t\t\tlabel = \"green:usb\";\n\t\t\tgpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;\n\t\t\ttrigger-sources = <&ohci_port1>, <&ehci_port1>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\n\t\tair {\n\t\t\tlabel = \"green:wifi\";\n\t\t\tgpios = <&gpio3 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 1 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash0: flash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfirmware: partition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\t/* reg property is set based on flash size in DTS files */\n\t\t\t};\n\t\t};\n\t};\n};\n\n&gpio1 {\n\tstatus = \"okay\";\n};\n\n&gpio3 {\n\tstatus = \"okay\";\n};\n\n&sdhci {\n\tstatus = \"okay\";\n};\n\n&ehci {\n\tstatus = \"okay\";\n};\n\n&ohci {\n\tstatus = \"okay\";\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tmediatek,portmap = \"llllw\";\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&state_default {\n\tdefault {\n\t\tgroups = \"i2c\", \"uartf\", \"wled\", \"spi refclk\", \"pa\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620a_zte_q7.dts",
    "content": "#include \"mt7620a.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"zte,q7\", \"ralink,mt7620a-soc\";\n\tmodel = \"ZTE Q7\";\n\n\taliases {\n\t\tled-boot = &led_status_blue;\n\t\tled-failsafe = &led_status_blue;\n\t\tled-running = &led_status_blue;\n\t\tled-upgrade = &led_status_blue;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tstatred {\n\t\t\tlabel = \"red:status\";\n\t\t\tgpios = <&gpio0 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_status_blue: statblue {\n\t\t\tlabel = \"blue:status\";\n\t\t\tgpios = <&gpio0 9 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio1 2 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n};\n\n&gpio1 {\n\tstatus = \"okay\";\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x7b0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"uartf\", \"rgmii1\", \"rgmii2\", \"ephy\", \"wled\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tmediatek,portmap = \"wllll\";\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&sdhci {\n\tstatus = \"okay\";\n};\n\n&ehci {\n\tstatus = \"okay\";\n};\n\n&ohci {\n\tstatus = \"okay\";\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620a_zyxel_keenetic-viva.dts",
    "content": "#include \"mt7620a.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"zyxel,keenetic-viva\", \"ralink,mt7620a-soc\";\n\tmodel = \"ZyXEL Keenetic Viva\";\n\n\taliases {\n\t\tled-boot = &led_power_green;\n\t\tled-failsafe = &led_power_green;\n\t\tled-running = &led_power_green;\n\t\tled-upgrade = &led_power_green;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twan {\n\t\t\tlabel = \"green:wan\";\n\t\t\tgpios = <&gpio0 7 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tusb {\n\t\t\tlabel = \"green:usb\";\n\t\t\tgpios = <&gpio0 8 GPIO_ACTIVE_LOW>;\n\t\t\ttrigger-sources = <&ohci_port1>, <&ehci_port1>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\n\t\tpower_alert {\n\t\t\tlabel = \"red:power\";\n\t\t\tgpios = <&gpio0 10 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twifi {\n\t\t\tlabel = \"green:wifi\";\n\t\t\tgpios = <&gpio0 11 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_power_green: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio0 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 1 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio0 2 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\n\t\tfn {\n\t\t\tlabel = \"fn\";\n\t\t\tgpios = <&gpio0 9 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_0>;\n\t\t};\n\t};\n\n\tgpio_export {\n\t\tcompatible = \"gpio-export\";\n\t\t#size-cells = <0>;\n\n\t\tusb_power {\n\t\t\tgpio-export,name = \"usb\";\n\t\t\tgpio-export,output = <1>;\n\t\t\tgpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n\n\trtl8367rb {\n\t\tcompatible = \"realtek,rtl8367b\";\n\t\tcpu_port = <7>;\n\t\trealtek,extif2 = <1 0 1 1 1 1 1 1 2>;\n\t\tmii-bus = <&mdio0>;\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0xfb0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"uartf\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&rgmii2_pins &mdio_pins>;\n\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tport@4 {\n\t\tstatus = \"okay\";\n\t\tmediatek,fixed-link = <1000 1 1 1>;\n\t\tphy-mode = \"rgmii\";\n\t\tphy-handle = <&phy4>;\n\t};\n\n\tmdio0: mdio-bus {\n\t\tstatus = \"okay\";\n\n\t\tphy4: ethernet-phy@4 {\n\t\t\treg = <4>;\n\t\t\tphy-mode = \"rgmii\";\n\t\t};\n\t};\n};\n\n&gsw {\n\tmediatek,port4-gmac;\n\tmediatek,ephy-base = /bits/ 8 <8>;\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&ehci {\n\tstatus = \"okay\";\n};\n\n&ohci {\n\tstatus = \"okay\";\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620n.dtsi",
    "content": "/dts-v1/;\n\n/ {\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\tcompatible = \"ralink,mt7620n-soc\";\n\n\taliases {\n\t\tspi0 = &spi0;\n\t\tspi1 = &spi1;\n\t\tserial0 = &uartlite;\n\t};\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu@0 {\n\t\t\tcompatible = \"mips,mips24KEc\";\n\t\t\treg = <0>;\n\t\t};\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,57600\";\n\t};\n\n\tcpuintc: cpuintc {\n\t\t#address-cells = <0>;\n\t\t#interrupt-cells = <1>;\n\t\tinterrupt-controller;\n\t\tcompatible = \"mti,cpu-interrupt-controller\";\n\t};\n\n\tpalmbus: palmbus@10000000 {\n\t\tcompatible = \"palmbus\";\n\t\treg = <0x10000000 0x200000>;\n\t\tranges = <0x0 0x10000000 0x1FFFFF>;\n\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tsysc: sysc@0 {\n\t\t\tcompatible = \"ralink,mt7620a-sysc\", \"ralink,rt3050-sysc\", \"syscon\";\n\t\t\treg = <0x0 0x100>;\n\t\t};\n\n\t\ttimer: timer@100 {\n\t\t\tcompatible = \"ralink,mt7620a-timer\", \"ralink,rt2880-timer\";\n\t\t\treg = <0x100 0x20>;\n\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <1>;\n\t\t};\n\n\t\twatchdog: watchdog@120 {\n\t\t\tcompatible = \"ralink,mt7620a-wdt\", \"ralink,rt2880-wdt\";\n\t\t\treg = <0x120 0x10>;\n\n\t\t\tresets = <&rstctrl 8>;\n\t\t\treset-names = \"wdt\";\n\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <1>;\n\t\t};\n\n\t\tintc: intc@200 {\n\t\t\tcompatible = \"ralink,mt7620a-intc\", \"ralink,rt2880-intc\";\n\t\t\treg = <0x200 0x100>;\n\n\t\t\tresets = <&rstctrl 19>;\n\t\t\treset-names = \"intc\";\n\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <1>;\n\n\t\t\tinterrupt-parent = <&cpuintc>;\n\t\t\tinterrupts = <2>;\n\t\t};\n\n\t\tmemc: memc@300 {\n\t\t\tcompatible = \"ralink,mt7620a-memc\", \"ralink,rt3050-memc\";\n\t\t\treg = <0x300 0x100>;\n\n\t\t\tresets = <&rstctrl 20>;\n\t\t\treset-names = \"mc\";\n\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <3>;\n\t\t};\n\n\t\tgpio0: gpio@600 {\n\t\t\tcompatible = \"ralink,mt7620a-gpio\", \"ralink,rt2880-gpio\";\n\t\t\treg = <0x600 0x34>;\n\n\t\t\tresets = <&rstctrl 13>;\n\t\t\treset-names = \"pio\";\n\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <6>;\n\n\t\t\tgpio-controller;\n\t\t\t#gpio-cells = <2>;\n\n\t\t\tngpios = <24>;\n\t\t\tralink,gpio-base = <0>;\n\t\t\tralink,register-map = [ 00 04 08 0c\n\t\t\t\t\t\t20 24 28 2c\n\t\t\t\t\t\t30 34 ];\n\t\t};\n\n\t\tgpio1: gpio@638 {\n\t\t\tcompatible = \"ralink,mt7620a-gpio\", \"ralink,rt2880-gpio\";\n\t\t\treg = <0x638 0x24>;\n\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <6>;\n\n\t\t\tgpio-controller;\n\t\t\t#gpio-cells = <2>;\n\n\t\t\tngpios = <16>;\n\t\t\tralink,gpio-base = <24>;\n\t\t\tralink,register-map = [ 00 04 08 0c\n\t\t\t\t\t\t10 14 18 1c\n\t\t\t\t\t\t20 24 ];\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tgpio2: gpio@660 {\n\t\t\tcompatible = \"ralink,mt7620a-gpio\", \"ralink,rt2880-gpio\";\n\t\t\treg = <0x660 0x24>;\n\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <6>;\n\n\t\t\tgpio-controller;\n\t\t\t#gpio-cells = <2>;\n\n\t\t\tngpios = <32>;\n\t\t\tralink,gpio-base = <40>;\n\t\t\tralink,register-map = [ 00 04 08 0c\n\t\t\t\t\t\t10 14 18 1c\n\t\t\t\t\t\t20 24 ];\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tgpio3: gpio@688 {\n\t\t\tcompatible = \"ralink,mt7620a-gpio\", \"ralink,rt2880-gpio\";\n\t\t\treg = <0x688 0x24>;\n\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <6>;\n\n\t\t\tgpio-controller;\n\t\t\t#gpio-cells = <2>;\n\n\t\t\tngpios = <1>;\n\t\t\tralink,gpio-base = <72>;\n\t\t\tralink,register-map = [ 00 04 08 0c\n\t\t\t\t\t\t10 14 18 1c\n\t\t\t\t\t\t20 24 ];\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\ti2c: i2c@900 {\n\t\t\tcompatible = \"ralink,rt2880-i2c\";\n\t\t\treg = <0x900 0x100>;\n\n\t\t\tresets = <&rstctrl 16>;\n\t\t\treset-names = \"i2c\";\n\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\n\t\t\tstatus = \"disabled\";\n\n\t\t\tpinctrl-names = \"default\";\n\t\t\tpinctrl-0 = <&i2c_pins>;\n\t\t};\n\n\t\tspi0: spi@b00 {\n\t\t\tcompatible = \"ralink,mt7620a-spi\", \"ralink,rt2880-spi\";\n\t\t\treg = <0xb00 0x40>;\n\n\t\t\tresets = <&rstctrl 18>;\n\t\t\treset-names = \"spi\";\n\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\n\t\t\tstatus = \"disabled\";\n\n\t\t\tpinctrl-names = \"default\";\n\t\t\tpinctrl-0 = <&spi_pins>;\n\t\t};\n\n\t\tspi1: spi@b40 {\n\t\t\tcompatible = \"ralink,rt2880-spi\";\n\t\t\treg = <0xb40 0x60>;\n\n\t\t\tresets = <&rstctrl 18>;\n\t\t\treset-names = \"spi\";\n\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\n\t\t\tstatus = \"disabled\";\n\n\t\t\tpinctrl-names = \"default\";\n\t\t\tpinctrl-0 = <&spi_cs1>;\n\t\t};\n\n\t\tuartlite: uartlite@c00 {\n\t\t\tcompatible = \"ralink,mt7620a-uart\", \"ralink,rt2880-uart\", \"ns16550a\";\n\t\t\treg = <0xc00 0x100>;\n\n\t\t\tresets = <&rstctrl 19>;\n\t\t\treset-names = \"uartl\";\n\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <12>;\n\n\t\t\treg-shift = <2>;\n\n\t\t\tpinctrl-names = \"default\";\n\t\t\tpinctrl-0 = <&uartlite_pins>;\n\t\t};\n\n\t\tsystick: systick@d00 {\n\t\t\tcompatible = \"ralink,mt7620a-systick\", \"ralink,cevt-systick\";\n\t\t\treg = <0xd00 0x10>;\n\n\t\t\tresets = <&rstctrl 28>;\n\t\t\treset-names = \"intc\";\n\n\t\t\tinterrupt-parent = <&cpuintc>;\n\t\t\tinterrupts = <7>;\n\t\t};\n\t};\n\n\tpinctrl: pinctrl {\n\t\tcompatible = \"ralink,rt2880-pinmux\";\n\t\tpinctrl-names = \"default\";\n\t\tpinctrl-0 = <&state_default>;\n\n\t\tstate_default: pinctrl0 {\n\t\t};\n\n\t\tephy_pins: ephy {\n\t\t\tephy {\n\t\t\t\tgroups = \"ephy\";\n\t\t\t\tfunction = \"ephy\";\n\t\t\t};\n\t\t};\n\n\t\tspi_pins: spi_pins {\n\t\t\tspi_pins {\n\t\t\t\tgroups = \"spi\";\n\t\t\t\tfunction = \"spi\";\n\t\t\t};\n\t\t};\n\n\t\tspi_cs1: spi1 {\n\t\t\tspi1 {\n\t\t\t\tgroups = \"spi refclk\";\n\t\t\t\tfunction = \"spi refclk\";\n\t\t\t};\n\t\t};\n\n\t\ti2c_pins: i2c_pins {\n\t\t\ti2c_pins {\n\t\t\t\tgroups = \"i2c\";\n\t\t\t\tfunction = \"i2c\";\n\t\t\t};\n\t\t};\n\n\t\tuartlite_pins: uartlite {\n\t\t\tuart {\n\t\t\t\tgroups = \"uartlite\";\n\t\t\t\tfunction = \"uartlite\";\n\t\t\t};\n\t\t};\n\t};\n\n\trstctrl: rstctrl {\n\t\tcompatible = \"ralink,mt7620a-reset\", \"ralink,rt2880-reset\";\n\t\t#reset-cells = <1>;\n\t};\n\n\tclkctrl: clkctrl {\n\t\tcompatible = \"ralink,rt2880-clock\";\n\t\t#clock-cells = <1>;\n\t};\n\n\tusbphy: usbphy {\n\t\tcompatible = \"mediatek,mt7620-usbphy\";\n\t\t#phy-cells = <0>;\n\n\t\tralink,sysctl = <&sysc>;\n\t\tresets = <&rstctrl 22 &rstctrl 25>;\n\t\treset-names = \"host\", \"device\";\n\n\t\tclocks = <&clkctrl 22 &clkctrl 25>;\n\t\tclock-names = \"host\", \"device\";\n\t};\n\n\tethernet: ethernet@10100000 {\n\t\tcompatible = \"mediatek,mt7620-eth\";\n\t\treg = <0x10100000 0x10000>;\n\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tinterrupt-parent = <&cpuintc>;\n\t\tinterrupts = <5>;\n\n\t\tresets = <&rstctrl 21 &rstctrl 23>;\n\t\treset-names = \"fe\", \"esw\";\n\n\t\tmediatek,switch = <&gsw>;\n\t};\n\n\tgsw: gsw@10110000 {\n\t\tcompatible = \"mediatek,mt7620-gsw\";\n\t\treg = <0x10110000 0x8000>;\n\n\t\tresets = <&rstctrl 23>;\n\t\treset-names = \"esw\";\n\n\t\tinterrupt-parent = <&intc>;\n\t\tinterrupts = <17>;\n\t};\n\n\tehci: ehci@101c0000 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tcompatible = \"generic-ehci\";\n\t\treg = <0x101c0000 0x1000>;\n\n\t\tinterrupt-parent = <&intc>;\n\t\tinterrupts = <18>;\n\n\t\tphys = <&usbphy>;\n\t\tphy-names = \"usb\";\n\n\t\tstatus = \"disabled\";\n\n\t\tehci_port1: port@1 {\n\t\t\treg = <1>;\n\t\t\t#trigger-source-cells = <0>;\n\t\t};\n\t};\n\n\tohci: ohci@101c1000 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tcompatible = \"generic-ohci\";\n\t\treg = <0x101c1000 0x1000>;\n\n\t\tphys = <&usbphy>;\n\t\tphy-names = \"usb\";\n\n\t\tinterrupt-parent = <&intc>;\n\t\tinterrupts = <18>;\n\n\t\tstatus = \"disabled\";\n\n\t\tohci_port1: port@1 {\n\t\t\treg = <1>;\n\t\t\t#trigger-source-cells = <0>;\n\t\t};\n\t};\n\n\twmac: wmac@10180000 {\n\t\tcompatible = \"ralink,rt7620-wmac\", \"ralink,rt2880-wmac\";\n\t\treg = <0x10180000 0x40000>;\n\n\t\tinterrupt-parent = <&cpuintc>;\n\t\tinterrupts = <6>;\n\n\t\tralink,eeprom = \"soc_wmac.eeprom\";\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620n_asus_rt-n12p.dts",
    "content": "#include \"mt7620n.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"asus,rt-n12p\", \"ralink,mt7620n-soc\";\n\tmodel = \"Asus RT-N12+\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200\";\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twan {\n\t\t\tlabel = \"green:wan\";\n\t\t\tgpios = <&gpio2 4 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan {\n\t\t\tlabel = \"green:lan\";\n\t\t\tgpios = <&gpio1 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_power: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio2 3 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tair {\n\t\t\tlabel = \"green:air\";\n\t\t\tgpios = <&gpio3 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 17 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n};\n\n&gpio1 {\n\tstatus = \"okay\";\n};\n\n&gpio2 {\n\tstatus = \"okay\";\n};\n\n&gpio3 {\n\tstatus = \"okay\";\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0xfb0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tmediatek,portmap = \"llllw\";\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&state_default {\n\tdefault {\n\t\tgroups = \"ephy\", \"wled\", \"i2c\", \"wdt\", \"pa\", \"spi refclk\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620n_asus_rt-n14u.dts",
    "content": "#include \"mt7620n.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"asus,rt-n14u\", \"ralink,mt7620n-soc\";\n\tmodel = \"Asus RT-N14U\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twan {\n\t\t\tlabel = \"blue:wan\";\n\t\t\tgpios = <&gpio2 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan {\n\t\t\tlabel = \"blue:lan\";\n\t\t\tgpios = <&gpio2 1 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tusb {\n\t\t\tlabel = \"blue:usb\";\n\t\t\tgpios = <&gpio2 2 GPIO_ACTIVE_LOW>;\n\t\t\ttrigger-sources = <&ohci_port1>, <&ehci_port1>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\n\t\tled_power: power {\n\t\t\tlabel = \"blue:power\";\n\t\t\tgpios = <&gpio2 3 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tair {\n\t\t\tlabel = \"blue:air\";\n\t\t\tgpios = <&gpio3 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 1 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio0 2 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n};\n\n&gpio2 {\n\tstatus = \"okay\";\n};\n\n&gpio3 {\n\tstatus = \"okay\";\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0xfb0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&ehci {\n\tstatus = \"okay\";\n};\n\n&ohci {\n\tstatus = \"okay\";\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tmediatek,portmap = \"wllll\";\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&state_default {\n\tdefault {\n\t\tgroups = \"ephy\", \"wled\", \"i2c\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620n_buffalo_wmr-300.dts",
    "content": "#include \"mt7620n.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"buffalo,wmr-300\", \"ralink,mt7620n-soc\";\n\tmodel = \"Buffalo WMR-300\";\n\n\taliases {\n\t\tled-boot = &led_status;\n\t\tled-failsafe = &led_status;\n\t\tled-running = &led_status;\n\t\tled-upgrade = &led_status;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\taoss1 {\n\t\t\tlabel = \"red:aoss\";\n\t\t\tgpios = <&gpio2 1 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\taoss2 {\n\t\t\tlabel = \"green:aoss\";\n\t\t\tgpios = <&gpio2 2 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_status: status {\n\t\t\tlabel = \"green:status\";\n\t\t\tgpios = <&gpio2 4 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 1 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\taoss {\n\t\t\tlabel = \"aoss\";\n\t\t\tgpios = <&gpio0 2 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n};\n\n&gpio2 {\n\tstatus = \"okay\";\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x7b0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tmediatek,portmap = \"wllll\";\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&state_default {\n\tdefault {\n\t\tgroups = \"i2c\", \"ephy\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620n_comfast_cf-wr800n.dts",
    "content": "#include \"mt7620n.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"comfast,cf-wr800n\", \"ralink,mt7620n-soc\";\n\tmodel = \"Comfast CF-WR800N\";\n\n\taliases {\n\t\tled-boot = &led_wps;\n\t\tled-failsafe = &led_wps;\n\t\tled-running = &led_wps;\n\t\tled-upgrade = &led_wps;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200\";\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tethernet {\n\t\t\tlabel = \"white:ethernet\";\n\t\t\tgpios = <&gpio2 4 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twifi {\n\t\t\tlabel = \"white:wifi\";\n\t\t\tgpios = <&gpio3 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_wps: wps {\n\t\t\tlabel = \"white:wps\";\n\t\t\tgpios = <&gpio1 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 2 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n};\n\n&gpio1 {\n\tstatus = \"okay\";\n};\n\n&gpio2 {\n\tstatus = \"okay\";\n};\n\n&gpio3 {\n\tstatus = \"okay\";\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x7b0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&state_default {\n\tdefault {\n\t\tgroups = \"ephy\", \"wled\", \"spi refclk\", \"i2c\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620n_dlink_dwr-116-a1.dts",
    "content": "#include \"mt7620n.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/mtd/partitions/uimage.h>\n\n/ {\n\tcompatible = \"dlink,dwr-116-a1\", \"ralink,mt7620n-soc\";\n\tmodel = \"D-Link DWR-116 A1/A2\";\n\n\taliases {\n\t\tled-boot = &led_status;\n\t\tled-failsafe = &led_status;\n\t\tled-running = &led_status;\n\t\tled-upgrade = &led_status;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio0 2 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 1 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_status: status {\n\t\t\tlabel = \"green:status\";\n\t\t\tgpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\twifi {\n\t\t\tlabel = \"green:wifi\";\n\t\t\tgpios = <&gpio3 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&gpio3 {\n\tstatus = \"okay\";\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <50000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"jboot\";\n\t\t\t\treg = <0x0 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@10000 {\n\t\t\t\tcompatible = \"openwrt,uimage\", \"denx,uimage\";\n\t\t\t\topenwrt,ih-magic = <IH_MAGIC_OKLI>;\n\t\t\t\topenwrt,offset = <0x10000>;\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x10000 0x7e0000>;\n\t\t\t};\n\n\t\t\tconfig: partition@7f0000 {\n\t\t\t\tlabel = \"config\";\n\t\t\t\treg = <0x7f0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&ehci {\n\tstatus = \"okay\";\n};\n\n&ohci {\n\tstatus = \"okay\";\n};\n\n&state_default {\n\tdefault {\n\t\tgroups = \"i2c\", \"wled\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&ephy_pins>;\n\n\tmediatek,portmap = \"llllw\";\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620n_dlink_dwr-921-c1.dts",
    "content": "#include \"mt7620n.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/mtd/partitions/uimage.h>\n\n/ {\n\tcompatible = \"dlink,dwr-921-c1\", \"ralink,mt7620n-soc\";\n\tmodel = \"D-Link DWR-921 C1\";\n\n\taliases {\n\t\tled-boot = &led_sstrenghg;\n\t\tled-failsafe = &led_sstrenghg;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio0 2 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 1 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tsms {\n\t\t\tlabel = \"green:sms\";\n\t\t\tgpios = <&gpio1 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan {\n\t\t\tlabel = \"green:lan\";\n\t\t\tgpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tled_sstrenghg: sstrengthg {\n\t\t\tlabel = \"green:sigstrength\";\n\t\t\tgpios = <&gpio2 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tsstrengthr {\n\t\t\tlabel = \"red:sigstrength\";\n\t\t\tgpios = <&gpio2 1 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\t4g {\n\t\t\tlabel = \"green:4g\";\n\t\t\tgpios = <&gpio2 2 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\t3g {\n\t\t\tlabel = \"green:3g\";\n\t\t\tgpios = <&gpio2 3 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twifi {\n\t\t\tlabel = \"green:wifi\";\n\t\t\tgpios = <&gpio3 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tgpio_export {\n\t\tcompatible = \"gpio-export\";\n\t\t#size-cells = <0>;\n\n\t\tlte_modem_enable {\n\t\t\tgpio-export,name = \"lte_modem_enable\";\n\t\t\tgpio-export,output = <1>;\n\t\t\tgpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&gpio1 {\n\tstatus = \"okay\";\n};\n\n&gpio2 {\n\tstatus = \"okay\";\n};\n\n&gpio3 {\n\tstatus = \"okay\";\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"jboot\";\n\t\t\t\treg = <0x0 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@10000 {\n\t\t\t\tcompatible = \"openwrt,uimage\", \"denx,uimage\";\n\t\t\t\topenwrt,ih-magic = <IH_MAGIC_OKLI>;\n\t\t\t\topenwrt,offset = <0x10000>;\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x10000 0xfe0000>;\n\t\t\t};\n\n\t\t\tconfig: partition@ff0000 {\n\t\t\t\tlabel = \"config\";\n\t\t\t\treg = <0xff0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&ehci {\n\tstatus = \"okay\";\n};\n\n&ohci {\n\tstatus = \"okay\";\n};\n\n&state_default {\n\tdefault {\n\t\tgroups = \"spi refclk\", \"i2c\", \"ephy\", \"wled\";\n\t\tfunction = \"gpio\";\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620n_dlink_dwr-922-e2.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7620n.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/mtd/partitions/uimage.h>\n\n/ {\n\tcompatible = \"dlink,dwr-922-e2\", \"ralink,mt7620n-soc\";\n\tmodel = \"D-Link DWR-922 E2\";\n\n\taliases {\n\t\tled-boot = &sstrengthg;\n\t\tled-failsafe = &sstrengthg;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio0 2 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 1 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tled-boot = &sstrengthg;\n\n\t\tsms {\n\t\t\tlabel = \"green:sms\";\n\t\t\tgpios = <&gpio1 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan {\n\t\t\tlabel = \"green:lan\";\n\t\t\tgpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tsstrengthg: sstrengthg {\n\t\t\tlabel = \"green:sigstrength\";\n\t\t\tgpios = <&gpio2 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tsstrengthr {\n\t\t\tlabel = \"red:sigstrength\";\n\t\t\tgpios = <&gpio2 1 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\t4g {\n\t\t\tlabel = \"green:4g\";\n\t\t\tgpios = <&gpio2 2 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\t3g {\n\t\t\tlabel = \"green:3g\";\n\t\t\tgpios = <&gpio2 3 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twifi {\n\t\t\tlabel = \"green:wifi\";\n\t\t\tgpios = <&gpio3 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tgpio_export {\n\t\tcompatible = \"gpio-export\";\n\t\t#size-cells = <0>;\n\n\t\tlte_modem_enable {\n\t\t\tgpio-export,name = \"lte_modem_enable\";\n\t\t\tgpio-export,output = <1>;\n\t\t\tgpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&gpio1 {\n\tstatus = \"okay\";\n};\n\n&gpio2 {\n\tstatus = \"okay\";\n};\n\n&gpio3 {\n\tstatus = \"okay\";\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"jboot\";\n\t\t\t\treg = <0x0 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@10000 {\n\t\t\t\tcompatible = \"openwrt,uimage\", \"denx,uimage\";\n\t\t\t\topenwrt,ih-magic = <IH_MAGIC_OKLI>;\n\t\t\t\topenwrt,offset = <0x10000>;\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x10000 0xfe0000>;\n\t\t\t};\n\n\t\t\tconfig: partition@ff0000 {\n\t\t\t\tlabel = \"config\";\n\t\t\t\treg = <0xff0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&ehci {\n\tstatus = \"okay\";\n};\n\n&ohci {\n\tstatus = \"okay\";\n};\n\n&state_default {\n\tdefault {\n\t\tgroups = \"spi refclk\", \"i2c\", \"ephy\", \"wled\";\n\t\tfunction = \"gpio\";\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620n_elecom_wrh-300cr.dts",
    "content": "#include \"mt7620n.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"elecom,wrh-300cr\", \"ralink,mt7620n-soc\";\n\tmodel = \"ELECOM WRH-300CR\";\n\n\taliases {\n\t\tled-boot = &led_wps;\n\t\tled-failsafe = &led_wps;\n\t\tled-running = &led_wps;\n\t\tled-upgrade = &led_wps;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_wps: wps {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&gpio2 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tethernet {\n\t\t\tlabel = \"green:ethernet\";\n\t\t\tgpios = <&gpio2 3 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan {\n\t\t\tlabel = \"green:wlan\";\n\t\t\tgpios = <&gpio3 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 1 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio0 2 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n};\n\n&gpio2 {\n\tstatus = \"okay\";\n};\n\n&gpio3 {\n\tstatus = \"okay\";\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tlabel = \"recover\";\n\t\t\t\treg = <0x50000 0x1c0000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@210000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x210000 0xdf0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&ehci {\n\tstatus = \"okay\";\n};\n\n&ohci {\n\tstatus = \"okay\";\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_2e>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tmediatek,portmap = \"llllw\";\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&state_default {\n\tdefault {\n\t\tgroups = \"i2c\", \"ephy\", \"wled\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_2e: macaddr@2e {\n\t\treg = <0x2e 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620n_hootoo_ht-tm05.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7620n_sunvalley_filehub.dtsi\"\n\n/ {\n\tcompatible = \"hootoo,ht-tm05\", \"ralink,mt7620n-soc\";\n\tmodel = \"HooToo HT-TM05\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"blue:power\";\n\t\t\tgpios = <&gpio3 0 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\twifi {\n\t\t\tlabel = \"green:wifi\";\n\t\t\tgpios = <&gpio2 0 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620n_kimax_u35wf.dts",
    "content": "#include \"mt7620n.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"kimax,u35wf\",\"ralink,mt7620n-soc\";\n\tmodel = \"Kimax U35WF\";\n\n\taliases {\n\t\tled-boot = &led_wifi;\n\t\tled-failsafe = &led_wifi;\n\t\tled-running = &led_wifi;\n\t\tled-upgrade = &led_wifi;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio2 3 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_wifi: wifi {\n\t\t\tlabel = \"blue:wifi\";\n\t\t\tgpios = <&gpio3 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan {\n\t\t\tlabel = \"green:eth\";\n\t\t\tgpios = <&gpio2 4 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&gpio2 {\n\tstatus = \"okay\";\n};\n\n&gpio3 {\n\tstatus = \"okay\";\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0xfb0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&ehci {\n\tstatus = \"okay\";\n};\n\n&ohci {\n\tstatus = \"okay\";\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&state_default {\n\tdefault {\n\t\tgroups = \"ephy\", \"wled\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620n_kingston_mlw221.dts",
    "content": "#include \"mt7620n.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"kingston,mlw221\", \"ralink,mt7620n-soc\";\n\tmodel = \"Kingston MLW221\";\n\n\taliases {\n\t\tled-boot = &led_system;\n\t\tled-failsafe = &led_system;\n\t\tled-running = &led_system;\n\t\tled-upgrade = &led_system;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_system: system {\n\t\t\tlabel = \"blue:system\";\n\t\t\tgpios = <&gpio2 3 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twifi {\n\t\t\tlabel = \"blue:wifi\";\n\t\t\tgpios = <&gpio3 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 1 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\tsystem {\n\t\t\tlabel = \"system\";\n\t\t\tgpios = <&gpio0 2 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RFKILL>;\n\t\t};\n\t};\n};\n\n&gpio2 {\n\tstatus = \"okay\";\n};\n\n&gpio3 {\n\tstatus = \"okay\";\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0xf60000>;\n\t\t\t};\n\n\t\t\tpartition@fb0000 {\n\t\t\t\tlabel = \"user-config\";\n\t\t\t\treg = <0xfb0000 0x50000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&ehci {\n\tstatus = \"okay\";\n};\n\n&ohci {\n\tstatus = \"okay\";\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tmediatek,portmap = \"wllll\";\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&state_default {\n\tdefault {\n\t\tgroups = \"i2c\", \"ephy\", \"wled\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620n_kingston_mlwg2.dts",
    "content": "#include \"mt7620n.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"kingston,mlwg2\", \"ralink,mt7620n-soc\";\n\tmodel = \"Kingston MLWG2\";\n\n\taliases {\n\t\tled-boot = &led_system;\n\t\tled-failsafe = &led_system;\n\t\tled-running = &led_system;\n\t\tled-upgrade = &led_system;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_system: system {\n\t\t\tlabel = \"blue:system\";\n\t\t\tgpios = <&gpio2 3 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twifi {\n\t\t\tlabel = \"blue:wifi\";\n\t\t\tgpios = <&gpio3 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 1 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\tsystem {\n\t\t\tlabel = \"system\";\n\t\t\tgpios = <&gpio0 2 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RFKILL>;\n\t\t};\n\t};\n};\n\n&gpio2 {\n\tstatus = \"okay\";\n};\n\n&gpio3 {\n\tstatus = \"okay\";\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0xf60000>;\n\t\t\t};\n\n\t\t\tpartition@fb0000 {\n\t\t\t\tlabel = \"user-config\";\n\t\t\t\treg = <0xfb0000 0x50000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&ehci {\n\tstatus = \"okay\";\n};\n\n&ohci {\n\tstatus = \"okay\";\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tmediatek,portmap = \"wllll\";\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&state_default {\n\tdefault {\n\t\tgroups = \"i2c\", \"ephy\", \"wled\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620n_netgear_jwnr2010-v5.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7620n_netgear_n300.dtsi\"\n\n/ {\n\tcompatible = \"netgear,jwnr2010-v5\", \"ralink,mt7620n-soc\";\n\tmodel = \"Netgear JWNR2010 v5\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t\tlabel-mac-device = &ethernet;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio0 21 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twan {\n\t\t\tlabel = \"green:wan\";\n\t\t\tgpios = <&gpio0 19 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\twlan {\n\t\t\tlabel = \"green:wlan\";\n\t\t\tgpios = <&gpio3 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0radio\";\n\t\t};\n\n\t\tlan1 {\n\t\t\tlabel = \"green:lan1\";\n\t\t\tgpios = <&gpio2 3 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan2 {\n\t\t\tlabel = \"green:lan2\";\n\t\t\tgpios = <&gpio2 2 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan3 {\n\t\t\tlabel = \"green:lan3\";\n\t\t\tgpios = <&gpio2 1 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan4 {\n\t\t\tlabel = \"green:lan4\";\n\t\t\tgpios = <&gpio2 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620n_netgear_n300.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7620n.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 20 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n};\n\n&gpio2 {\n\tstatus = \"okay\";\n};\n\n&gpio3 {\n\tstatus = \"okay\";\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <30000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x20000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x20000 0x3c0000>;\n\t\t\t};\n\n\t\t\tpartition@3e0000 {\n\t\t\t\tlabel = \"nvram\";\n\t\t\t\treg = <0x3e0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@3f0000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x3f0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tmediatek,portmap = \"llllw\";\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&state_default {\n\tdefault {\n\t\tgroups = \"pa\", \"ephy\", \"wled\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620n_nexx_wt3020-4m.dts",
    "content": "#include \"mt7620n_nexx_wt3020.dtsi\"\n\n/ {\n\tcompatible = \"nexx,wt3020-4m\", \"nexx,wt3020\", \"ralink,mt7620n-soc\";\n\tmodel = \"Nexx WT3020 (4M)\";\n};\n\n&firmware {\n\treg = <0x50000 0x3b0000>;\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620n_nexx_wt3020-8m.dts",
    "content": "#include \"mt7620n_nexx_wt3020.dtsi\"\n\n/ {\n\tcompatible = \"nexx,wt3020-8m\", \"nexx,wt3020\", \"ralink,mt7620n-soc\";\n\tmodel = \"Nexx WT3020 (8M)\";\n};\n\n&firmware {\n\treg = <0x50000 0x7b0000>;\n};\n\n&ehci {\n\tstatus = \"okay\";\n};\n\n&ohci {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620n_nexx_wt3020.dtsi",
    "content": "#include \"mt7620n.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"nexx,wt3020\", \"ralink,mt7620n-soc\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t\tlabel-mac-device = &ethernet;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 1 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"blue:power\";\n\t\t\tgpios = <&gpio3 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfirmware: partition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\t/* reg property is set based on flash size in DTS files */\n\t\t\t};\n\t\t};\n\t};\n};\n\n&gpio3 {\n\tstatus = \"okay\";\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tmediatek,portmap = \"wllll\";\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&state_default {\n\tdefault {\n\t\tgroups = \"ephy\", \"wled\", \"pa\", \"i2c\", \"wdt\", \"uartf\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620n_ravpower_rp-wd03.dts",
    "content": "#include \"mt7620n_sunvalley_filehub.dtsi\"\n\n/ {\n\tcompatible = \"ravpower,rp-wd03\", \"ralink,mt7620n-soc\";\n\tmodel = \"RAVPower RP-WD03\";\n\n\taliases {\n\t\tled-boot = &led_wifi_blue;\n\t\tled-failsafe = &led_wifi_blue;\n\t\tled-running = &led_wifi_blue;\n\t\tled-upgrade = &led_wifi_blue;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twifi_green {\n\t\t\tlabel = \"green:wifi\";\n\t\t\tgpios = <&gpio2 0 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tled_wifi_blue: wifi_blue {\n\t\t\tlabel = \"blue:wifi\";\n\t\t\tgpios = <&gpio3 0 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620n_sunvalley_filehub.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7620n.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/mtd/partitions/uimage.h>\n\n/ {\n\taliases {\n\t\tlabel-mac-device = &ethernet;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio2 1 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tvirtual_flash {\n\t\tcompatible = \"mtd-concat\";\n\n\t\tdevices = <&fwconcat0 &fwconcat1 &fwconcat2>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tcompatible = \"openwrt,uimage\", \"denx,uimage\";\n\t\t\t\topenwrt,ih-magic = <IH_MAGIC_OKLI>;\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x0 0x0>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&gpio2 {\n\tstatus = \"okay\";\n};\n\n&gpio3 {\n\tstatus = \"okay\";\n};\n\n&i2c {\n\tstatus = \"okay\";\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <50000000>;\n\t\tm25p,fast-read;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"config\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tlabel = \"loader\";\n\t\t\t\treg = <0x50000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfwconcat1: partition@60000 {\n\t\t\t\tlabel = \"fwconcat1\";\n\t\t\t\treg = <0x60000 0x170000>;\n\t\t\t};\n\n\t\t\tpartition@1d0000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x1d0000 0x10000>;\n\t\t\t};\n\n\t\t\tfwconcat2: partition@1e0000 {\n\t\t\t\tlabel = \"fwconcat2\";\n\t\t\t\treg = <0x1e0000 0x20000>;\n\t\t\t};\n\n\t\t\tfwconcat0: partition@200000 {\n\t\t\t\tlabel = \"fwconcat0\";\n\t\t\t\treg = <0x200000 0x600000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&ehci {\n\tstatus = \"okay\";\n};\n\n&ohci {\n\tstatus = \"okay\";\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_28>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"wled\", \"ephy\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_28: macaddr@28 {\n\t\treg = <0x28 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620n_vonets_var11n-300.dts",
    "content": "#include \"mt7620n.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"vonets,var11n-300\", \"ralink,mt7620n-soc\";\n\tmodel = \"Vonets VAR11N-300\";\n\n\taliases {\n\t\tled-boot = &led_system;\n\t\tled-failsafe = &led_system;\n\t\tled-running = &led_system;\n\t\tled-upgrade = &led_system;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_system: system {\n\t\t\tlabel = \"blue:system\";\n\t\t\tgpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 1 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x3b0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tmediatek,portmap = \"llllw\";\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&state_default {\n\tdefault {\n\t\tgroups = \"i2c\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620n_wrtnode_wrtnode.dts",
    "content": "#include \"mt7620n.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n\n/ {\n\tcompatible = \"wrtnode,wrtnode\", \"ralink,mt7620n-soc\";\n\tmodel = \"WRTNODE\";\n\n\taliases {\n\t\tled-boot = &led_indicator;\n\t\tled-failsafe = &led_indicator;\n\t\tled-running = &led_indicator;\n\t\tled-upgrade = &led_indicator;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_indicator: indicator {\n\t\t\tlabel = \"blue:indicator\";\n\t\t\tgpios = <&gpio1 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&gpio1 {\n\tstatus = \"okay\";\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0xfb0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&ehci {\n\tstatus = \"okay\";\n};\n\n&ohci {\n\tstatus = \"okay\";\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tmediatek,portmap = \"wllll\";\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&state_default {\n\tdefault {\n\t\tgroups = \"ephy\", \"wled\", \"pa\", \"i2c\", \"wdt\", \"uartf\", \"spi refclk\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620n_zbtlink_zbt-cpe102.dts",
    "content": "#include \"mt7620n.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"zbtlink,zbt-cpe102\", \"ralink,mt7620n-soc\";\n\tmodel = \"Zbtlink ZBT-CPE102\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200\";\n\t};\n\n\taliases {\n\t\tled-boot = &led_4g_0;\n\t\tled-failsafe = &led_4g_0;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_4g_0: 4g-0 {\n\t\t\tlabel = \"green:4g-0\";\n\t\t\tgpios = <&gpio1 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\t4g-1 {\n\t\t\tlabel = \"green:4g-1\";\n\t\t\tgpios = <&gpio0 2 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\t4g-2 {\n\t\t\tlabel = \"green:4g-2\";\n\t\t\tgpios = <&gpio1 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 1 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n};\n\n&gpio1 {\n\tstatus = \"okay\";\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x760000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&ehci {\n\tstatus = \"okay\";\n};\n\n&ohci {\n\tstatus = \"okay\";\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tmediatek,portmap = \"wllll\";\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&state_default {\n\tdefault {\n\t\tgroups = \"i2c\", \"spi refclk\", \"wled\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620n_zbtlink_zbt-wa05.dts",
    "content": "#include \"mt7620n.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"zbtlink,zbt-wa05\", \"ralink,mt7620n-soc\";\n\tmodel = \"Zbtlink ZBT-WA05\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200\";\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"blue:power\";\n\t\t\tgpios = <&gpio1 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tusb {\n\t\t\tlabel = \"blue:usb\";\n\t\t\tgpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;\n\t\t\ttrigger-sources = <&ohci_port1>, <&ehci_port1>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\n\t\tair {\n\t\t\tlabel = \"blue:air\";\n\t\t\tgpios = <&gpio3 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 1 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n};\n\n&gpio1 {\n\tstatus = \"okay\";\n};\n\n&gpio3 {\n\tstatus = \"okay\";\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x760000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&ehci {\n\tstatus = \"okay\";\n};\n\n&ohci {\n\tstatus = \"okay\";\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tmediatek,portmap = \"wllll\";\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&state_default {\n\tdefault {\n\t\tgroups = \"i2c\", \"spi refclk\", \"wled\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620n_zbtlink_zbt-we2026.dts",
    "content": "#include \"mt7620n.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"zbtlink,zbt-we2026\", \"ralink,mt7620n-soc\";\n\tmodel = \"Zbtlink ZBT-WE2026\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200\";\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"red:power\";\n\t\t\tgpios = <&gpio1 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan {\n\t\t\tlabel = \"green:wlan\";\n\t\t\tgpios = <&gpio3 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 1 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n};\n\n&gpio1 {\n\tstatus = \"okay\";\n};\n\n&gpio3 {\n\tstatus = \"okay\";\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x760000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tmediatek,portmap = \"llllw\";\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&state_default {\n\tdefault {\n\t\tgroups = \"i2c\", \"spi refclk\", \"wled\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620n_zbtlink_zbt-wr8305rt.dts",
    "content": "#include \"mt7620n.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"zbtlink,zbt-wr8305rt\", \"ralink,mt7620n-soc\";\n\tmodel = \"Zbtlink ZBT-WR8305RT\";\n\n\taliases {\n\t\tled-boot = &led_sys;\n\t\tled-failsafe = &led_sys;\n\t\tled-running = &led_sys;\n\t\tled-upgrade = &led_sys;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_sys: sys {\n\t\t\tlabel = \"green:sys\";\n\t\t\tgpios = <&gpio1 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan {\n\t\t\tlabel = \"green:usb\";\n\t\t\tgpios = <&gpio1 15 GPIO_ACTIVE_LOW>;\n\t\t\ttrigger-sources = <&ohci_port1>, <&ehci_port1>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\n\t\twifi {\n\t\t\tlabel = \"green:wifi\";\n\t\t\tgpios = <&gpio3 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 1 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n};\n\n&gpio1 {\n\tstatus = \"okay\";\n};\n\n&gpio3 {\n\tstatus = \"okay\";\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x7b0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&ehci {\n\tstatus = \"okay\";\n};\n\n&ohci {\n\tstatus = \"okay\";\n};\n\n&ethernet {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&ephy_pins>;\n\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tmediatek,portmap = \"llllw\";\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&state_default {\n\tdefault {\n\t\tgroups = \"i2c\", \"uartf\", \"spi refclk\", \"wled\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620n_zyxel_keenetic-omni-ii.dts",
    "content": "#include \"mt7620n.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"zyxel,keenetic-omni-ii\", \"ralink,mt7620n-soc\";\n\tmodel = \"ZyXEL Keenetic Omni II\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twan {\n\t\t\tlabel = \"green:wan\";\n\t\t\tgpios = <&gpio1 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tusb {\n\t\t\tlabel = \"green:usb\";\n\t\t\tgpios = <&gpio0 20 GPIO_ACTIVE_LOW>;\n\t\t\ttrigger-sources = <&ohci_port1>, <&ehci_port1>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\n\t\twifi {\n\t\t\tlabel = \"green:wifi\";\n\t\t\tgpios = <&gpio3 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_power: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio1 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 1 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio0 2 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\n\t\tfn {\n\t\t\tlabel = \"fn\";\n\t\t\tgpios = <&gpio0 17 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_0>;\n\t\t};\n\t};\n\n\tgpio_export {\n\t\tcompatible = \"gpio-export\";\n\t\t#size-cells = <0>;\n\n\t\tusb_power {\n\t\t\tgpio-export,name = \"usb\";\n\t\t\tgpio-export,output = <1>;\n\t\t\tgpios = <&gpio0 21 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&gpio1 {\n\tstatus = \"okay\";\n};\n\n&gpio3 {\n\tstatus = \"okay\";\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x7b0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"wdt\", \"pa\", \"spi refclk\", \"wled\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tmediatek,portmap = \"wllll\";\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&ehci {\n\tstatus = \"okay\";\n};\n\n&ohci {\n\tstatus = \"okay\";\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7620n_zyxel_keenetic-omni.dts",
    "content": "#include \"mt7620n.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"zyxel,keenetic-omni\", \"ralink,mt7620n-soc\";\n\tmodel = \"ZyXEL Keenetic Omni\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twan {\n\t\t\tlabel = \"green:wan\";\n\t\t\tgpios = <&gpio1 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tusb {\n\t\t\tlabel = \"green:usb\";\n\t\t\tgpios = <&gpio1 15 GPIO_ACTIVE_LOW>;\n\t\t\ttrigger-sources = <&ohci_port1>, <&ehci_port1>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\n\t\twifi {\n\t\t\tlabel = \"green:wifi\";\n\t\t\tgpios = <&gpio3 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_power: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio0 20 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 1 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio0 2 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\n\t\tfn {\n\t\t\tlabel = \"fn\";\n\t\t\tgpios = <&gpio0 17 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_0>;\n\t\t};\n\t};\n\n\tgpio_export {\n\t\tcompatible = \"gpio-export\";\n\t\t#size-cells = <0>;\n\n\t\tusb_power {\n\t\t\tgpio-export,name = \"usb\";\n\t\t\tgpio-export,output = <1>;\n\t\t\tgpios = <&gpio0 21 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&gpio1 {\n\tstatus = \"okay\";\n};\n\n&gpio3 {\n\tstatus = \"okay\";\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x7b0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"wdt\", \"pa\", \"spi refclk\", \"wled\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tmediatek,portmap = \"llllw\";\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&ehci {\n\tstatus = \"okay\";\n};\n\n&ohci {\n\tstatus = \"okay\";\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621.dtsi",
    "content": "/dts-v1/;\n\n#include <dt-bindings/interrupt-controller/mips-gic.h>\n#include <dt-bindings/clock/mt7621-clk.h>\n#include <dt-bindings/gpio/gpio.h>\n\n/ {\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\tcompatible = \"mediatek,mt7621-soc\";\n\n\taliases {\n\t\tserial0 = &uartlite;\n\t};\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu@0 {\n\t\t\tdevice_type = \"cpu\";\n\t\t\tcompatible = \"mips,mips1004Kc\";\n\t\t\treg = <0>;\n\t\t};\n\n\t\tcpu@1 {\n\t\t\tdevice_type = \"cpu\";\n\t\t\tcompatible = \"mips,mips1004Kc\";\n\t\t\treg = <1>;\n\t\t};\n\t};\n\n\tcpuintc: cpuintc {\n\t\t#address-cells = <0>;\n\t\t#interrupt-cells = <1>;\n\t\tinterrupt-controller;\n\t\tcompatible = \"mti,cpu-interrupt-controller\";\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,57600\";\n\t};\n\n#ifdef DTS_LEGACY\n\tpll: pll {\n\t\tcompatible = \"mediatek,mt7621-pll\", \"syscon\";\n\n\t\t#clock-cells = <1>;\n\t\tclock-output-names = \"cpu\", \"bus\";\n\t};\n#endif\n\n\tsysclock: sysclock {\n\t\t#clock-cells = <0>;\n\t\tcompatible = \"fixed-clock\";\n\n\t\t/* FIXME: there should be way to detect this */\n\t\tclock-frequency = <50000000>;\n\t};\n\n\tpalmbus: palmbus@1e000000 {\n\t\tcompatible = \"palmbus\";\n\t\treg = <0x1e000000 0x100000>;\n\t\tranges = <0x0 0x1e000000 0x0fffff>;\n\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tsysc: syscon@0 {\n#ifdef DTS_LEGACY\n\t\t\tcompatible = \"mtk,mt7621-sysc\", \"syscon\";\n#else\n\t\t\tcompatible = \"mediatek,mt7621-sysc\", \"syscon\";\n\t\t\t#clock-cells = <1>;\n\t\t\tralink,memctl = <&memc>;\n\t\t\tclock-output-names = \"xtal\", \"cpu\", \"bus\",\n\t\t\t\t\t     \"50m\", \"125m\", \"150m\",\n\t\t\t\t\t     \"250m\", \"270m\";\n#endif\n\t\t\treg = <0x0 0x100>;\n\t\t};\n\n\t\twdt: wdt@100 {\n\t\t\tcompatible = \"mediatek,mt7621-wdt\";\n\t\t\treg = <0x100 0x100>;\n\t\t};\n\n\t\tgpio: gpio@600 {\n\t\t\t#gpio-cells = <2>;\n\t\t\t#interrupt-cells = <2>;\n\t\t\tcompatible = \"mediatek,mt7621-gpio\";\n\t\t\tgpio-controller;\n\t\t\tgpio-ranges = <&pinctrl 0 0 95>;\n\t\t\tinterrupt-controller;\n\t\t\treg = <0x600 0x100>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <GIC_SHARED 12 IRQ_TYPE_LEVEL_HIGH>;\n\t\t};\n\n\t\ti2c: i2c@900 {\n\t\t\tcompatible = \"mediatek,mt7621-i2c\";\n\t\t\treg = <0x900 0x100>;\n\n\t\t\tclocks = <&sysclock>;\n\n\t\t\tresets = <&rstctrl 16>;\n\t\t\treset-names = \"i2c\";\n\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\n\t\t\tstatus = \"disabled\";\n\n\t\t\tpinctrl-names = \"default\";\n\t\t\tpinctrl-0 = <&i2c_pins>;\n\t\t};\n\n\t\ti2s: i2s@a00 {\n\t\t\tcompatible = \"mediatek,mt7621-i2s\";\n\t\t\treg = <0xa00 0x100>;\n\n\t\t\tclocks = <&sysclock>;\n\n\t\t\tresets = <&rstctrl 17>;\n\t\t\treset-names = \"i2s\";\n\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <GIC_SHARED 16 IRQ_TYPE_LEVEL_HIGH>;\n\n\t\t\ttxdma-req = <2>;\n\t\t\trxdma-req = <3>;\n\n\t\t\tdmas = <&gdma 4>,\n\t\t\t\t<&gdma 6>;\n\t\t\tdma-names = \"tx\", \"rx\";\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tsystick: systick@500 {\n\t\t\tcompatible = \"ralink,mt7621-systick\", \"ralink,cevt-systick\";\n\t\t\treg = <0x500 0x10>;\n\n\t\t\tresets = <&rstctrl 28>;\n\t\t\treset-names = \"intc\";\n\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <GIC_SHARED 5 IRQ_TYPE_LEVEL_HIGH>;\n\t\t};\n\n\t\tmemc: syscon@5000 {\n#ifdef DTS_LEGACY\n\t\t\tcompatible = \"mtk,mt7621-memc\", \"syscon\";\n#else\n\t\t\tcompatible = \"mediatek,mt7621-memc\", \"syscon\";\n#endif\n\t\t\treg = <0x5000 0x1000>;\n\t\t};\n\n\t\tuartlite: uartlite@c00 {\n\t\t\tcompatible = \"ns16550a\";\n\t\t\treg = <0xc00 0x100>;\n\n\t\t\tclock-frequency = <50000000>;\n\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <GIC_SHARED 26 IRQ_TYPE_LEVEL_HIGH>;\n\n\t\t\treg-shift = <2>;\n\t\t\treg-io-width = <4>;\n\t\t\tno-loopback-test;\n\t\t};\n\n\t\tuartlite2: uartlite2@d00 {\n\t\t\tcompatible = \"ns16550a\";\n\t\t\treg = <0xd00 0x100>;\n\n\t\t\tclock-frequency = <50000000>;\n\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <GIC_SHARED 27 IRQ_TYPE_LEVEL_HIGH>;\n\n\t\t\treg-shift = <2>;\n\t\t\treg-io-width = <4>;\n\n\t\t\tpinctrl-names = \"default\";\n\t\t\tpinctrl-0 = <&uart2_pins>;\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tuartlite3: uartlite3@e00 {\n\t\t\tcompatible = \"ns16550a\";\n\t\t\treg = <0xe00 0x100>;\n\n\t\t\tclock-frequency = <50000000>;\n\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <GIC_SHARED 28 IRQ_TYPE_LEVEL_HIGH>;\n\n\t\t\treg-shift = <2>;\n\t\t\treg-io-width = <4>;\n\n\t\t\tpinctrl-names = \"default\";\n\t\t\tpinctrl-0 = <&uart3_pins>;\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tspi0: spi@b00 {\n\t\t\tstatus = \"disabled\";\n\n\t\t\tcompatible = \"ralink,mt7621-spi\";\n\t\t\treg = <0xb00 0x100>;\n\n#ifdef DTS_LEGACY\n\t\t\tclocks = <&pll MT7621_CLK_BUS>;\n#else\n\t\t\tclocks = <&sysc MT7621_CLK_BUS>;\n#endif\n\n\t\t\tresets = <&rstctrl 18>;\n\t\t\treset-names = \"spi\";\n\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\n\t\t\tpinctrl-names = \"default\";\n\t\t\tpinctrl-0 = <&spi_pins>;\n\t\t};\n\n\t\tgdma: gdma@2800 {\n\t\t\tcompatible = \"ralink,rt3883-gdma\";\n\t\t\treg = <0x2800 0x800>;\n\n\t\t\tresets = <&rstctrl 14>;\n\t\t\treset-names = \"dma\";\n\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>;\n\n\t\t\t#dma-cells = <1>;\n\t\t\t#dma-channels = <16>;\n\t\t\t#dma-requests = <16>;\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\thsdma: hsdma@7000 {\n\t\t\tcompatible = \"mediatek,mt7621-hsdma\";\n\t\t\treg = <0x7000 0x1000>;\n\n\t\t\tresets = <&rstctrl 5>;\n\t\t\treset-names = \"hsdma\";\n\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;\n\n\t\t\t#dma-cells = <1>;\n\t\t\t#dma-channels = <1>;\n\t\t\t#dma-requests = <1>;\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\t};\n\n\tpinctrl: pinctrl {\n\t\tcompatible = \"ralink,rt2880-pinmux\";\n\t\tpinctrl-names = \"default\";\n\t\tpinctrl-0 = <&state_default>;\n\n\t\tstate_default: pinctrl0 {\n\t\t};\n\n\t\ti2c_pins: i2c_pins {\n\t\t\ti2c_pins {\n\t\t\t\tgroups = \"i2c\";\n\t\t\t\tfunction = \"i2c\";\n\t\t\t};\n\t\t};\n\n\t\tspi_pins: spi_pins {\n\t\t\tspi_pins {\n\t\t\t\tgroups = \"spi\";\n\t\t\t\tfunction = \"spi\";\n\t\t\t};\n\t\t};\n\n\t\tuart1_pins: uart1 {\n\t\t\tuart1 {\n\t\t\t\tgroups = \"uart1\";\n\t\t\t\tfunction = \"uart1\";\n\t\t\t};\n\t\t};\n\n\t\tuart2_pins: uart2 {\n\t\t\tuart2 {\n\t\t\t\tgroups = \"uart2\";\n\t\t\t\tfunction = \"uart2\";\n\t\t\t};\n\t\t};\n\n\t\tuart3_pins: uart3 {\n\t\t\tuart3 {\n\t\t\t\tgroups = \"uart3\";\n\t\t\t\tfunction = \"uart3\";\n\t\t\t};\n\t\t};\n\n\t\trgmii1_pins: rgmii1 {\n\t\t\trgmii1 {\n\t\t\t\tgroups = \"rgmii1\";\n\t\t\t\tfunction = \"rgmii1\";\n\t\t\t};\n\t\t};\n\n\t\trgmii2_pins: rgmii2 {\n\t\t\trgmii2 {\n\t\t\t\tgroups = \"rgmii2\";\n\t\t\t\tfunction = \"rgmii2\";\n\t\t\t};\n\t\t};\n\n\t\tmdio_pins: mdio {\n\t\t\tmdio {\n\t\t\t\tgroups = \"mdio\";\n\t\t\t\tfunction = \"mdio\";\n\t\t\t};\n\t\t};\n\n\t\tpcie_pins: pcie {\n\t\t\tpcie {\n\t\t\t\tgroups = \"pcie\";\n\t\t\t\tfunction = \"gpio\";\n\t\t\t};\n\t\t};\n\n\t\tnand_pins: nand {\n\t\t\tspi-nand {\n\t\t\t\tgroups = \"spi\";\n\t\t\t\tfunction = \"nand1\";\n\t\t\t};\n\n\t\t\tsdhci-nand {\n\t\t\t\tgroups = \"sdhci\";\n\t\t\t\tfunction = \"nand2\";\n\t\t\t};\n\t\t};\n\n\t\tsdhci_pins: sdhci {\n\t\t\tsdhci {\n\t\t\t\tgroups = \"sdhci\";\n\t\t\t\tfunction = \"sdhci\";\n\t\t\t};\n\t\t};\n\t};\n\n\trstctrl: rstctrl {\n\t\tcompatible = \"ralink,rt2880-reset\";\n\t\t#reset-cells = <1>;\n\t};\n\n\tclkctrl: clkctrl {\n\t\tcompatible = \"ralink,rt2880-clock\";\n\t\t#clock-cells = <1>;\n\t};\n\n\tsdhci: sdhci@1e130000 {\n\t\tstatus = \"disabled\";\n\n\t\tcompatible = \"ralink,mt7620-sdhci\";\n\t\treg = <0x1e130000 0x4000>;\n\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <GIC_SHARED 20 IRQ_TYPE_LEVEL_HIGH>;\n\n\t\tpinctrl-names = \"default\";\n\t\tpinctrl-0 = <&sdhci_pins>;\n\t};\n\n\txhci: xhci@1e1c0000 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcompatible = \"mediatek,mt8173-xhci\";\n\t\treg = <0x1e1c0000 0x1000\n\t\t       0x1e1d0700 0x0100>;\n\t\treg-names = \"mac\", \"ippc\";\n\n\t\tclocks = <&sysclock>;\n\t\tclock-names = \"sys_ck\";\n\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <GIC_SHARED 22 IRQ_TYPE_LEVEL_HIGH>;\n\n\t\t/*\n\t\t * Port 1 of both hubs is one usb slot and referenced here.\n\t\t * The binding doesn't allow to address individual hubs.\n\t\t * hub 1 - port 1 is ehci and ohci, hub 2 - port 1 is xhci.\n\t\t */\n\t\txhci_ehci_port1: port@1 {\n\t\t\treg = <1>;\n\t\t\t#trigger-source-cells = <0>;\n\t\t};\n\n\t\t/*\n\t\t * Only the second usb hub has a second port. That port serves\n\t\t * ehci and ohci.\n\t\t */\n\t\tehci_port2: port@2 {\n\t\t\treg = <2>;\n\t\t\t#trigger-source-cells = <0>;\n\t\t};\n\t};\n\n\tgic: interrupt-controller@1fbc0000 {\n\t\tcompatible = \"mti,gic\";\n\t\treg = <0x1fbc0000 0x2000>;\n\n\t\tinterrupt-controller;\n\t\t#interrupt-cells = <3>;\n\n\t\tmti,reserved-cpu-vectors = <7>;\n\n\t\ttimer {\n\t\t\tcompatible = \"mti,gic-timer\";\n\t\t\tinterrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;\n#ifdef DTS_LEGACY\n\t\t\tclocks = <&pll MT7621_CLK_CPU>;\n#else\n\t\t\tclocks = <&sysc MT7621_CLK_CPU>;\n#endif\n\t\t};\n\t};\n\n\tnficlock: nficlock {\n\t\t#clock-cells = <0>;\n\t\tcompatible = \"fixed-clock\";\n\n\t\tclock-frequency = <125000000>;\n\t};\n\n\tcpc: cpc@1fbf0000 {\n\t\tcompatible = \"mti,mips-cpc\";\n\t\treg = <0x1fbf0000 0x8000>;\n\t};\n\n\tmc: mc@1fbf8000 {\n\t\tcompatible = \"mti,mips-cdmm\";\n\t\treg = <0x1fbf8000 0x8000>;\n\t};\n\n\tnand: nand@1e003000 {\n\t\tstatus = \"disabled\";\n\n\t\tcompatible = \"mediatek,mt7621-nfc\";\n\t\treg = <0x1e003000 0x800\n\t\t\t0x1e003800 0x800>;\n\t\treg-names = \"nfi\", \"ecc\";\n\n\t\tclocks = <&nficlock>;\n\t\tclock-names = \"nfi_clk\";\n\t};\n\n\tethernet: ethernet@1e100000 {\n\t\tcompatible = \"mediatek,mt7621-eth\";\n\t\treg = <0x1e100000 0x10000>;\n\n#ifdef DTS_LEGACY\n\t\tclocks = <&sysclock>;\n\t\tclock-names = \"ethif\";\n#else\n\t\tclocks = <&sysc MT7621_CLK_FE>,\n\t\t\t <&sysc MT7621_CLK_ETH>;\n\t\tclock-names = \"fe\", \"ethif\";\n#endif\n\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tresets = <&rstctrl 6>, <&rstctrl 23>;\n\t\treset-names = \"fe\", \"eth\";\n\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>;\n\n\t\tmediatek,ethsys = <&sysc>;\n\n#ifdef DTS_LEGACY\n\t\tpinctrl-names = \"default\";\n\t\tpinctrl-0 = <&mdio_pins>, <&rgmii1_pins>, <&rgmii2_pins>;\n#endif\n\n\t\tgmac0: mac@0 {\n\t\t\tcompatible = \"mediatek,eth-mac\";\n\t\t\treg = <0>;\n\t\t\tphy-mode = \"rgmii\";\n\n\t\t\tfixed-link {\n\t\t\t\tspeed = <1000>;\n\t\t\t\tfull-duplex;\n\t\t\t\tpause;\n\t\t\t};\n\t\t};\n\n\t\tgmac1: mac@1 {\n\t\t\tcompatible = \"mediatek,eth-mac\";\n\t\t\treg = <1>;\n\t\t\tstatus = \"disabled\";\n\t\t\tphy-mode = \"rgmii-rxid\";\n\t\t};\n\n\t\tmdio: mdio-bus {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\n\t\t\tswitch0: switch@1f {\n\t\t\t\tcompatible = \"mediatek,mt7621\";\n\t\t\t\treg = <0x1f>;\n\t\t\t\tmediatek,mcm;\n\t\t\t\tresets = <&rstctrl 2>;\n\t\t\t\treset-names = \"mcm\";\n\t\t\t\tinterrupt-controller;\n\t\t\t\t#interrupt-cells = <1>;\n\t\t\t\tinterrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>;\n\n\t\t\t\tports {\n\t\t\t\t\t#address-cells = <1>;\n\t\t\t\t\t#size-cells = <0>;\n\n\t\t\t\t\tport@0 {\n\t\t\t\t\t\tstatus = \"disabled\";\n\t\t\t\t\t\treg = <0>;\n\t\t\t\t\t\tlabel = \"lan0\";\n\t\t\t\t\t};\n\n\t\t\t\t\tport@1 {\n\t\t\t\t\t\tstatus = \"disabled\";\n\t\t\t\t\t\treg = <1>;\n\t\t\t\t\t\tlabel = \"lan1\";\n\t\t\t\t\t};\n\n\t\t\t\t\tport@2 {\n\t\t\t\t\t\tstatus = \"disabled\";\n\t\t\t\t\t\treg = <2>;\n\t\t\t\t\t\tlabel = \"lan2\";\n\t\t\t\t\t};\n\n\t\t\t\t\tport@3 {\n\t\t\t\t\t\tstatus = \"disabled\";\n\t\t\t\t\t\treg = <3>;\n\t\t\t\t\t\tlabel = \"lan3\";\n\t\t\t\t\t};\n\n\t\t\t\t\tport@4 {\n\t\t\t\t\t\tstatus = \"disabled\";\n\t\t\t\t\t\treg = <4>;\n\t\t\t\t\t\tlabel = \"lan4\";\n\t\t\t\t\t};\n\n\t\t\t\t\tport@6 {\n\t\t\t\t\t\treg = <6>;\n\t\t\t\t\t\tlabel = \"cpu\";\n\t\t\t\t\t\tethernet = <&gmac0>;\n\t\t\t\t\t\tphy-mode = \"rgmii\";\n\n\t\t\t\t\t\tfixed-link {\n\t\t\t\t\t\t\tspeed = <1000>;\n\t\t\t\t\t\t\tfull-duplex;\n\t\t\t\t\t\t\tpause;\n\t\t\t\t\t\t};\n\t\t\t\t\t};\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t};\n\n\tpcie: pcie@1e140000 {\n\t\tcompatible = \"mediatek,mt7621-pci\";\n\t\treg = <0x1e140000 0x100>, /* host-pci bridge registers */\n\t\t      <0x1e142000 0x100>, /* pcie port 0 RC control registers */\n\t\t      <0x1e143000 0x100>, /* pcie port 1 RC control registers */\n\t\t      <0x1e144000 0x100>; /* pcie port 2 RC control registers */\n\t\t#address-cells = <3>;\n\t\t#size-cells = <2>;\n\n\t\tpinctrl-names = \"default\";\n\t\tpinctrl-0 = <&pcie_pins>;\n\n\t\tdevice_type = \"pci\";\n\n#ifdef DTS_LEGACY\n\t\tranges = <0x02000000 0 0x00000000 0x60000000 0 0x10000000>, /* pci memory */\n\t\t\t <0x01000000 0 0x00000000 0x1e160000 0 0x00010000>; /* io space */\n#else\n\t\tranges = <0x02000000 0 0x60000000 0x60000000 0 0x10000000>, /* pci memory */\n\t\t\t <0x01000000 0 0x00000000 0x1e160000 0 0x00010000>; /* io space */\n#endif\n\n\t\tstatus = \"disabled\";\n\n#ifdef DTS_LEGACY\n\t\tinterrupt-parent = <&gic>;\n\t\tinterrupts = <GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH\n\t\t\t\tGIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH\n\t\t\t\tGIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;\n\n\n\t\tresets = <&rstctrl 24>, <&rstctrl 25>, <&rstctrl 26>;\n\t\treset-names = \"pcie0\", \"pcie1\", \"pcie2\";\n\t\tclocks = <&clkctrl 24>, <&clkctrl 25>, <&clkctrl 26>;\n\t\tclock-names = \"pcie0\", \"pcie1\", \"pcie2\";\n\t\tphys = <&pcie0_phy 1>, <&pcie2_phy 0>;\n\t\tphy-names = \"pcie-phy0\", \"pcie-phy2\";\n#else\n\t\t#interrupt-cells = <1>;\n\t\tinterrupt-map-mask = <0xF800 0 0 0>;\n\t\tinterrupt-map = <0x0000 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>,\n\t\t\t\t<0x0800 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>,\n\t\t\t\t<0x1000 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;\n#endif\n\n\t\treset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>;\n\n\t\tpcie0: pcie@0,0 {\n\t\t\treg = <0x0000 0 0 0 0>;\n\t\t\t#address-cells = <3>;\n\t\t\t#size-cells = <2>;\n\t\t\tdevice_type = \"pci\";\n\t\t\tranges;\n#ifndef DTS_LEGACY\n\t\t\t#interrupt-cells = <1>;\n\t\t\tinterrupt-map-mask = <0 0 0 0>;\n\t\t\tinterrupt-map = <0 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>;\n\t\t\tresets = <&rstctrl 24>;\n\t\t\tclocks = <&sysc MT7621_CLK_PCIE0>;\n\t\t\tphys = <&pcie0_phy 1>;\n\t\t\tphy-names = \"pcie-phy0\";\n#endif\n\t\t};\n\n\t\tpcie1: pcie@1,0 {\n\t\t\treg = <0x0800 0 0 0 0>;\n\t\t\t#address-cells = <3>;\n\t\t\t#size-cells = <2>;\n\t\t\tdevice_type = \"pci\";\n\t\t\tranges;\n#ifndef DTS_LEGACY\n\t\t\t#interrupt-cells = <1>;\n\t\t\tinterrupt-map-mask = <0 0 0 0>;\n\t\t\tinterrupt-map = <0 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>;\n\t\t\tresets = <&rstctrl 25>;\n\t\t\tclocks = <&sysc MT7621_CLK_PCIE1>;\n\t\t\tphys = <&pcie0_phy 1>;\n\t\t\tphy-names = \"pcie-phy1\";\n#endif\n\t\t};\n\n\t\tpcie2: pcie@2,0 {\n\t\t\treg = <0x1000 0 0 0 0>;\n\t\t\t#address-cells = <3>;\n\t\t\t#size-cells = <2>;\n\t\t\tdevice_type = \"pci\";\n\t\t\tranges;\n#ifndef DTS_LEGACY\n\t\t\t#interrupt-cells = <1>;\n\t\t\tinterrupt-map-mask = <0 0 0 0>;\n\t\t\tinterrupt-map = <0 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;\n\t\t\tresets = <&rstctrl 26>;\n\t\t\tclocks = <&sysc MT7621_CLK_PCIE2>;\n\t\t\tphys = <&pcie2_phy 0>;\n\t\t\tphy-names = \"pcie-phy2\";\n#endif\n\t\t};\n\t};\n\n\tpcie0_phy: pcie-phy@1e149000 {\n\t\tcompatible = \"mediatek,mt7621-pci-phy\";\n\t\treg = <0x1e149000 0x0700>;\n#ifndef DTS_LEGACY\n\t\tclocks = <&sysc MT7621_CLK_XTAL>;\n#endif\n\t\t#phy-cells = <1>;\n\t};\n\n\tpcie2_phy: pcie-phy@1e14a000 {\n\t\tcompatible = \"mediatek,mt7621-pci-phy\";\n\t\treg = <0x1e14a000 0x0700>;\n#ifndef DTS_LEGACY\n\t\tclocks = <&sysc MT7621_CLK_XTAL>;\n#endif\n\t\t#phy-cells = <1>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_adslr_g7.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"adslr,g7\", \"mediatek,mt7621-soc\";\n\tmodel = \"ADSLR G7\";\n\n\taliases {\n\t\tled-boot = &led_sys;\n\t\tled-failsafe = &led_sys;\n\t\tled-running = &led_sys;\n\t\tled-upgrade = &led_sys;\n\t\tlabel-mac-device = &gmac0;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_sys: sys {\n\t\t\tlabel = \"blue:sys\";\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 8 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <40000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0xfb0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\twifi@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x0000>;\n\t\tieee80211-freq-limit = <2400000 2500000>;\n\t};\n};\n\n&pcie1 {\n\twifi@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\t};\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_factory_e00c>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&switch0 {\n\tports {\n\t\tport@0 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan1\";\n\t\t};\n\n\t\tport@1 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan2\";\n\t\t};\n\n\t\tport@2 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan3\";\n\t\t};\n\n\t\tport@3 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan4\";\n\t\t};\n\n\t\tport@4 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"wan\";\n\t\t\tnvmem-cells = <&macaddr_factory_e00c>;\n\t\t\tnvmem-cell-names = \"mac-address\";\n\t\t\tmac-address-increment = <1>;\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"uart3\", \"wdt\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_e00c: macaddr@e00c {\n\t\treg = <0xe00c 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_afoundry_ew1200.dts",
    "content": "#include \"mt7621.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"afoundry,ew1200\", \"mediatek,mt7621-soc\";\n\tmodel = \"EW1200\";\n\n\taliases {\n\t\tled-boot = &led_run;\n\t\tled-failsafe = &led_run;\n\t\tled-running = &led_run;\n\t\tled-upgrade = &led_run;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_run: run {\n\t\t\tlabel = \"green:run\";\n\t\t\tgpios = <&gpio 5 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tusb {\n\t\t\tlabel = \"green:usb\";\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_LOW>;\n\t\t\ttrigger-sources = <&xhci_ehci_port1>, <&ehci_port2>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\t};\n};\n\n&sdhci {\n\tstatus = \"okay\";\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0xfb0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\tmt76@0,0 {\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\t};\n};\n\n&pcie1 {\n\tmt76@0,0 {\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x0000>;\n\t\tieee80211-freq-limit = <2400000 2500000>;\n\t};\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_factory_e000>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&switch0 {\n\tports {\n\t\tport@0 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan1\";\n\t\t};\n\n\t\tport@1 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan2\";\n\t\t};\n\n\t\tport@2 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan3\";\n\t\t};\n\n\t\tport@3 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan4\";\n\t\t};\n\n\t\tport@4 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"wan\";\n\t\t\tnvmem-cells = <&macaddr_factory_e000>;\n\t\t\tnvmem-cell-names = \"mac-address\";\n\t\t\tmac-address-increment = <1>;\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"uart3\", \"wdt\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_e000: macaddr@e000 {\n\t\treg = <0xe000 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_alfa-network_quad-e4g.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"alfa-network,quad-e4g\", \"mediatek,mt7621-soc\";\n\tmodel = \"ALFA Network Quad-E4G\";\n\n\taliases {\n\t\tlabel-mac-device = &gmac0;\n\t\tled-boot = &led_system;\n\t\tled-failsafe = &led_system;\n\t\tled-running = &led_system;\n\t\tled-upgrade = &led_system;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200\";\n\t};\n\n\tgpio-export {\n\t\tcompatible = \"gpio-export\";\n\t\t#size-cells = <0>;\n\n\t\tm2-enable {\n\t\t\tgpio-export,name = \"m2-enable\";\n\t\t\tgpio-export,output = <1>;\n\t\t\tgpios = <&gpio 32 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tminipcie0-enable {\n\t\t\tgpio-export,name = \"minipcie0-enable\";\n\t\t\tgpio-export,output = <1>;\n\t\t\tgpios = <&gpio 29 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tminipcie0-reset {\n\t\t\tgpio-export,name = \"minipcie0-reset\";\n\t\t\tgpio-export,output = <0>;\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tminipcie1-enable {\n\t\t\tgpio-export,name = \"minipcie1-enable\";\n\t\t\tgpio-export,output = <1>;\n\t\t\tgpios = <&gpio 30 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tminipcie1-reset {\n\t\t\tgpio-export,name = \"minipcie1-reset\";\n\t\t\tgpio-export,output = <0>;\n\t\t\tgpios = <&gpio 24 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tminipcie2-enable {\n\t\t\tgpio-export,name = \"minipcie2-enable\";\n\t\t\tgpio-export,output = <1>;\n\t\t\tgpios = <&gpio 31 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tminipcie2-reset {\n\t\t\tgpio-export,name = \"minipcie2-reset\";\n\t\t\tgpio-export,output = <0>;\n\t\t\tgpios = <&gpio 25 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tpcie-perst-disable {\n\t\t\tgpio-export,name = \"pcie-perst-enable\";\n\t\t\tgpio-export,output = <0>;\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tsim-select {\n\t\t\tgpio-export,name = \"sim-select\";\n\t\t\tgpio-export,output = <1>;\n\t\t\tgpios = <&gpio 0 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\twatchdog-enable {\n\t\t\tgpio-export,name = \"watchdog-enable\";\n\t\t\tgpio-export,output = <1>;\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\tuser1 {\n\t\t\tlabel = \"user1\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_0>;\n\t\t};\n\n\t\tuser2 {\n\t\t\tlabel = \"user2\";\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_1>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_system: system {\n\t\t\tlabel = \"red:system\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"keep\";\n\t\t};\n\n\t\tm2 {\n\t\t\tlabel = \"orange:m2\";\n\t\t\tgpios = <&gpio 33 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tminipcie0 {\n\t\t\tlabel = \"orange:minipcie0\";\n\t\t\tgpios = <&gpio 26 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tminipcie1 {\n\t\t\tlabel = \"orange:minipcie1\";\n\t\t\tgpios = <&gpio 27 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tminipcie2 {\n\t\t\tlabel = \"orange:minipcie2\";\n\t\t\tgpios = <&gpio 28 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\twatchdog {\n\t\tcompatible = \"linux,wdt-gpio\";\n\t\tgpios = <&gpio 18 GPIO_ACTIVE_HIGH>;\n\t\thw_algo = \"toggle\";\n\t\thw_margin_ms = <25000>;\n\t\talways-running;\n\t};\n};\n\n&ethernet {\n\tpinctrl-0 = <&mdio_pins>, <&rgmii1_pins>;\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_factory_e000>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&switch0 {\n\tports {\n\t\tport@0 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan4\";\n\t\t};\n\n\t\tport@1 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan3\";\n\t\t};\n\n\t\tport@2 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan2\";\n\t\t};\n\n\t\tport@3 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan1\";\n\t\t};\n\n\t\tport@4 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"wan\";\n\t\t\tnvmem-cells = <&macaddr_factory_e006>;\n\t\t\tnvmem-cell-names = \"mac-address\";\n\t\t};\n\t};\n};\n\n&i2c {\n\tstatus = \"okay\";\n\n\trtc@68 {\n\t\tcompatible = \"ti,bq32000\";\n\t\treg = <0x68>;\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"jtag\", \"rgmii2\", \"wdt\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&sdhci {\n\tstatus = \"okay\";\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <50000000>;\n\t\tm25p,fast-read;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x1000>;\n\t\t\t};\n\n\t\t\tpartition@31000 {\n\t\t\t\tlabel = \"config\";\n\t\t\t\treg = <0x31000 0xf000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0xfb0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&uartlite2 {\n\tstatus = \"okay\";\n};\n\n&uartlite3 {\n\tstatus = \"okay\";\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_e000: macaddr@e000 {\n\t\treg = <0xe000 0x6>;\n\t};\n\n\tmacaddr_factory_e006: macaddr@e006 {\n\t\treg = <0xe006 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_ampedwireless_ally-00x19k.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621_ampedwireless_ally.dtsi\"\n\n/ {\n\tcompatible = \"ampedwireless,ally-00x19k\", \"mediatek,mt7621-soc\";\n\tmodel = \"Amped Wireless ALLY-00X19K\";\n};\n\n&switch0 {\n\tports {\n\t\tport@2 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan\";\n\t\t};\n\t};\n};\n\n&xhci {\n\tstatus = \"disabled\";\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_ampedwireless_ally-r1900k.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621_ampedwireless_ally.dtsi\"\n\n/ {\n\tcompatible = \"ampedwireless,ally-r1900k\", \"mediatek,mt7621-soc\";\n\tmodel = \"Amped Wireless ALLY-R1900K\";\n};\n\n&switch0 {\n\tports {\n\t\tport@1 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"wan\";\n\t\t};\n\n\t\tport@2 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan1\";\n\t\t};\n\n\t\tport@3 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan2\";\n\t\t};\n\n\t\tport@4 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan3\";\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_ampedwireless_ally.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\taliases {\n\t\tled-boot = &led_status_amber;\n\t\tled-failsafe = &led_status_amber;\n\t\tled-running = &led_status_green;\n\t\tled-upgrade = &led_status_red;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\tled_switch {\n\t\t\tlabel = \"led_switch\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = <KEY_LIGHTS_TOGGLE>;\n\t\t\tlinux,input-type = <EV_SW>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_status_green: status_green {\n\t\t\tlabel = \"green:status\";\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tled_status_red: status_red {\n\t\t\tlabel = \"red:status\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tled_status_amber: status_amber {\n\t\t\tlabel = \"amber:status\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\twifi@0,0 {\n\t\tcompatible = \"pci14c3,7615\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x0000>;\n\t\tieee80211-freq-limit = <2400000 2500000>;\n\t};\n};\n\n&pcie1 {\n\twifi@0,0 {\n\t\tcompatible = \"pci14c3,7615\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"uart2\", \"uart3\", \"jtag\", \"wdt\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&nand {\n\tstatus = \"okay\";\n\n\tpartitions {\n\t\tcompatible = \"fixed-partitions\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"u-boot\";\n\t\t\treg = <0x0 0x80000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@80000 {\n\t\t\tlabel = \"u-boot-env\";\n\t\t\treg = <0x80000 0x80000>;\n\t\t};\n\n\t\tfactory: partition@100000 {\n\t\t\tlabel = \"factory\";\n\t\t\treg = <0x100000 0x40000>;\n\t\t\tread-only;\n\t\t};\n\n\t\t/*\n\t\t * uboot expects to find kernels at 0x140000 & 0x2140000,\n\t\t * referred to as Uimage & Uimage1 in factory FW, respectively.\n\t\t * U-boot variable 'bootImage' controls which is booted;\n\t\t * 0 for the first, 1 for the 2nd.\n\t\t * There's a 3rd partition, Uimage2 (0x4140000), which\n\t\t * I expected to be a recovery image, but is actually blank.\n\t\t *\n\t\t * A kernel is considered suitable for handing control over\n\t\t * if its linux magic number exists & uImage CRC are correct.\n\t\t * If either of those conditions fail, 'bootImage' value\n\t\t * is toggled in uboot env & a restart performed in the hope that the\n\t\t * alternate kernel is okay.\n\t\t *\n\t\t * Note uboot's tftp flash install writes the transferred\n\t\t * image to the active kernel partition.\n\t\t */\n\n\t\tpartition@140000 {\n\t\t\tlabel = \"kernel\";\n\t\t\treg = <0x140000 0x400000>;\n\t\t};\n\n\t\tpartition@540000 {\n\t\t\tlabel = \"ubi\";\n\t\t\treg = <0x540000 0x1c00000>;\n\t\t};\n\n\t\tpartition@2140000 {\n\t\t\tlabel = \"oem\";\n\t\t\treg = <0x2140000 0x2000000>;\n\t\t};\n\n\t\tpartition@4140000 {\n\t\t\tlabel = \"backup\";\n\t\t\treg = <0x4140000 0x2000000>;\n\t\t};\n\n\t\tpartition@6140000 {\n\t\t\tlabel = \"chime\";\n\t\t\treg = <0x6140000 0xa00000>;\n\t\t};\n\n\t\tpartition@6b40000 {\n\t\t\tlabel = \"data\";\n\t\t\treg = <0x6b40000 0xa00000>;\n\t\t};\n\n\t\tpartition@7540000 {\n\t\t\tlabel = \"reserved\";\n\t\t\treg = <0x7540000 0x840000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@7d80000 {\n\t\t\tlabel = \"nvram\";\n\t\t\treg = <0x7d80000 0x100000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@7e80000 {\n\t\t\tlabel = \"hwconfig\";\n\t\t\treg = <0x7e80000 0x100000>;\n\t\t\tread-only;\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_asiarf_ap7621-001.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621_asiarf_ap7621.dtsi\"\n\n/ {\n\tcompatible = \"asiarf,ap7621-001\", \"mediatek,mt7621-soc\";\n\tmodel = \"AsiaRF AP7621-001\";\n};\n\n&switch0 {\n\tports {\n\t\tport@0 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan\";\n\t\t};\n\n\t\tport@4 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"wan\";\n\t\t\tnvmem-cells = <&macaddr_factory_e000>;\n\t\t\tnvmem-cell-names = \"mac-address\";\n\t\t\tmac-address-increment = <1>;\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_asiarf_ap7621-nv1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621_asiarf_ap7621.dtsi\"\n\n/ {\n\tcompatible = \"asiarf,ap7621-nv1\", \"mediatek,mt7621-soc\";\n\tmodel = \"AsiaRF AP7621-NV1\";\n};\n\n&switch0 {\n\tports {\n\t\tport@0 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"wan\";\n\t\t\tnvmem-cells = <&macaddr_factory_e000>;\n\t\t\tnvmem-cell-names = \"mac-address\";\n\t\t\tmac-address-increment = <1>;\n\t\t};\n\n\t\tport@2 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan1\";\n\t\t};\n\n\t\tport@3 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan2\";\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_asiarf_ap7621.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twlan1 {\n\t\t\tlabel = \"orange:wlan1\";\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan0 {\n\t\t\tlabel = \"orange:wlan0\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&sdhci {\n\tstatus = \"okay\";\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <40000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x2000>;\n\t\t\t};\n\n\t\t\tpartition@32000 {\n\t\t\t\tlabel = \"2860\";\n\t\t\t\treg = <0x32000 0x4000>;\n\t\t\t};\n\n\t\t\tpartition@36000 {\n\t\t\t\tlabel = \"rtdev\";\n\t\t\t\treg = <0x36000 0x2000>;\n\t\t\t};\n\n\t\t\tpartition@38000 {\n\t\t\t\tlabel = \"Reserve\";\n\t\t\t\treg = <0x38000 0x8000>;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0xfa0000>;\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t};\n\n\t\t\tpartition@ff0000 {\n\t\t\t\tlabel = \"nvram\";\n\t\t\t\treg = <0xff0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_factory_e000>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"wdt\", \"jtag\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_e000: macaddr@e000 {\n\t\treg = <0xe000 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_asus_rt-ac57u.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"asus,rt-ac57u\", \"mediatek,mt7621-soc\";\n\tmodel = \"ASUS RT-AC57U\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"blue:power\";\n\t\t\tgpios = <&gpio 48 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tusb {\n\t\t\tlabel = \"blue:usb\";\n\t\t\tgpios = <&gpio 47 GPIO_ACTIVE_LOW>;\n\t\t\ttrigger-sources = <&ehci_port2>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio 43 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 41 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tled-regulator {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"LED-Power\";\n\t\tgpio = <&gpio 46 GPIO_ACTIVE_LOW>;\n\t\tregulator-min-microvolt = <3300000>;\n\t\tregulator-max-microvolt = <3300000>;\n\t\tregulator-always-on;\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"config\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0xfb0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\twifi@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\n\t\tled {\n\t\t\tled-sources = <2>;\n\t\t\tled-active-low;\n\t\t};\n\t};\n};\n\n&pcie1 {\n\twifi@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x0000>;\n\n\t\tled {\n\t\t\tled-active-low;\n\t\t};\n\t};\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_factory_e000>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&switch0 {\n\tports {\n\t\tport@0 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"wan\";\n\t\t\tnvmem-cells = <&macaddr_factory_e006>;\n\t\t\tnvmem-cell-names = \"mac-address\";\n\t\t};\n\n\t\tport@1 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan1\";\n\t\t};\n\n\t\tport@2 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan2\";\n\t\t};\n\n\t\tport@3 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan3\";\n\t\t};\n\n\t\tport@4 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan4\";\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"sdhci\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_e000: macaddr@e000 {\n\t\treg = <0xe000 0x6>;\n\t};\n\n\tmacaddr_factory_e006: macaddr@e006 {\n\t\treg = <0xe006 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_asus_rt-ac65p.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621_asus_rt-acx5p.dtsi\"\n\n/ {\n\tcompatible = \"asus,rt-ac65p\", \"mediatek,mt7621-soc\";\n\tmodel = \"ASUS RT-AC65P\";\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_asus_rt-ac85p.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621_asus_rt-acx5p.dtsi\"\n\n/ {\n\tcompatible = \"asus,rt-ac85p\", \"mediatek,mt7621-soc\";\n\tmodel = \"ASUS RT-AC85P\";\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_asus_rt-acx5p.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 3 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio 6 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"blue:power\";\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan5g {\n\t\t\tlabel = \"blue:wlan5g\";\n\t\t\tgpios = <&gpio 8 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1radio\";\n\t\t};\n\n\t\twlan2g {\n\t\t\tlabel = \"blue:wlan2g\";\n\t\t\tgpios = <&gpio 10 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0radio\";\n\t\t};\n\t};\n};\n\n&i2c {\n\tstatus = \"okay\";\n};\n\n&sdhci {\n\tstatus = \"okay\";\n};\n\n&nand {\n\tstatus = \"okay\";\n\n\tpartitions {\n\t\tcompatible = \"fixed-partitions\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"u-boot\";\n\t\t\treg = <0x0 0xe0000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@e0000 {\n\t\t\tlabel = \"u-boot-env\";\n\t\t\treg = <0xe0000 0x100000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tfactory: partition@1e0000 {\n\t\t\tlabel = \"factory\";\n\t\t\treg = <0x1e0000 0x100000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tfactory2: partition@2e0000 {\n\t\t\tlabel = \"factory2\";\n\t\t\treg = <0x2e0000 0x100000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@3e0000 {\n\t\t\tlabel = \"kernel\";\n\t\t\treg = <0x3e0000 0x400000>;\n\t\t};\n\n\t\tpartition@7e0000 {\n\t\t\tlabel = \"ubi\";\n\t\t\treg = <0x7e0000 0x2e00000>;\n\t\t};\n\n\t\tpartition@35e0000 {\n\t\t\tlabel = \"firmware2\";\n\t\t\treg = <0x35e0000 0x3200000>;\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\twifi0: wifi@0,0 {\n\t\tcompatible = \"pci14c3,7615\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x0000>;\n\t\tieee80211-freq-limit = <2400000 2500000>;\n\t};\n};\n\n&pcie1 {\n\twifi1: wifi@0,0 {\n\t\tcompatible = \"pci14c3,7615\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\t};\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_factory_e000>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&switch0 {\n\tports {\n\t\tport@0 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"wan\";\n\t\t};\n\n\t\tport@1 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan1\";\n\t\t};\n\n\t\tport@2 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan2\";\n\t\t};\n\n\t\tport@3 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan3\";\n\t\t};\n\n\t\tport@4 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan4\";\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"uart2\", \"uart3\", \"i2c\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_e000: macaddr@e000 {\n\t\treg = <0xe000 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_asus_rt-n56u-b1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"asus,rt-n56u-b1\", \"mediatek,mt7621-soc\";\n\tmodel = \"ASUS RT-N56U B1\";\n\n\taliases {\n\t\tlabel-mac-device = &wan;\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200\";\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"blue:power\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan2g {\n\t\t\tlabel = \"blue:wlan2g\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\twlan5g {\n\t\t\tlabel = \"blue:wlan5g\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\n\t\twan {\n\t\t\tlabel = \"blue:wan\";\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan {\n\t\t\tlabel = \"blue:lan\";\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tusb {\n\t\t\tlabel = \"blue:usb\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t\ttrigger-sources = <&xhci_ehci_port1>, <&ehci_port2>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 6 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <50000000>;\n\t\tm25p,fast-read;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"config\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0xfb0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\twifi@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t};\n};\n\n&pcie1 {\n\twifi@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x0000>;\n\t};\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_factory_8004>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&switch0 {\n\tports {\n\t\tport@0 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan4\";\n\t\t};\n\n\t\tport@1 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan3\";\n\t\t};\n\n\t\tport@2 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan2\";\n\t\t};\n\n\t\tport@3 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan1\";\n\t\t};\n\n\t\twan: port@4 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"wan\";\n\t\t\tnvmem-cells = <&macaddr_factory_4>;\n\t\t\tnvmem-cell-names = \"mac-address\";\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"uart3\", \"uart2\", \"jtag\", \"wdt\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n\n\tmacaddr_factory_8004: macaddr@8004 {\n\t\treg = <0x8004 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_beeline_smartbox-flash.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/leds/common.h>\n\n/ {\n\tcompatible = \"beeline,smartbox-flash\", \"mediatek,mt7621-soc\";\n\tmodel = \"Beeline SmartBox Flash\";\n\n\taliases {\n\t\tled-boot = &led_status_red;\n\t\tled-failsafe = &led_status_red;\n\t\tled-running = &led_status_green;\n\t\tled-upgrade = &led_status_red;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled-0 {\n\t\t\tlabel = \"blue:wan\";\n\t\t\tcolor = <LED_COLOR_ID_BLUE>;\n\t\t\tfunction = LED_FUNCTION_WAN;\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_status_green: led-1 {\n\t\t\tlabel = \"green:status\";\n\t\t\tcolor = <LED_COLOR_ID_GREEN>;\n\t\t\tfunction = LED_FUNCTION_STATUS;\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_status_red: led-2 {\n\t\t\tlabel = \"red:status\";\n\t\t\tcolor = <LED_COLOR_ID_RED>;\n\t\t\tfunction = LED_FUNCTION_STATUS;\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 3 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tubi-concat {\n\t\tcompatible = \"mtd-concat\";\n\t\tdevices = <&ubiconcat0 &ubiconcat1>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"ubi\";\n\t\t\t\treg = <0x0 0x5240000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&nand {\n\tstatus = \"okay\";\n\n\tpartitions {\n\t\tcompatible = \"fixed-partitions\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"u-boot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@100000 {\n\t\t\tlabel = \"u-boot-env\";\n\t\t\treg = <0x100000 0x100000>;\n\t\t};\n\n\t\tfactory: partition@200000 {\n\t\t\tlabel = \"Factory\";\n\t\t\treg = <0x200000 0x100000>;\n\t\t\tread-only;\n\n\t\t\tcompatible = \"nvmem-cells\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tmacaddr_factory_fff0: macaddr@fff0 {\n\t\t\t\treg = <0xfff0 0x6>;\n\t\t\t};\n\t\t};\n\n\t\tpartition@300000 {\n\t\t\tlabel = \"firmware\";\n\t\t\treg = <0x300000 0x2000000>;\n\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"kernel\";\n\t\t\t\treg = <0x0 0x440000>;\n\t\t\t};\n\n\t\t\tubiconcat0: partition@400000 {\n\t\t\t\tlabel = \"ubiconcat0\";\n\t\t\t\treg = <0x440000 0x1bc0000>;\n\t\t\t};\n\t\t};\n\n\t\tpartition@2300000 {\n\t\t\tlabel = \"Firmware2\";\n\t\t\treg = <0x2300000 0x2000000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@4300000 {\n\t\t\tlabel = \"glbcfg\";\n\t\t\treg = <0x4300000 0x200000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@4500000 {\n\t\t\tlabel = \"board_data\";\n\t\t\treg = <0x4500000 0x100000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@4600000 {\n\t\t\tlabel = \"glbcfg2\";\n\t\t\treg = <0x4600000 0x200000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@4800000 {\n\t\t\tlabel = \"board_data2\";\n\t\t\treg = <0x4800000 0x100000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tubiconcat1: partition@4900000 {\n\t\t\tlabel = \"ubiconcat1\";\n\t\t\treg = <0x4900000 0x3680000>;\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\twifi@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x0>;\n\t};\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_factory_fff0>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&switch0 {\n\tports {\n\t\tport@2 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan2\";\n\t\t};\n\n\t\tport@3 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan1\";\n\t\t};\n\n\t\tport@4 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"wan\";\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"jtag\";\n\t\tfunction = \"gpio\";\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_bolt_arion.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"bolt,arion\", \"mediatek,mt7621-soc\";\n\tmodel = \"Bolt Arion\";\n\n\taliases {\n\t\tlabel-mac-device = &wan;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,57600n8\";\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_wlan_blue: wlan_blue {\n\t\t\tlabel = \"blue:wlan\";\n\t\t\tgpios = <&gpio 43 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_wlan_red: wlan_red {\n\t\t\tlabel = \"red:wlan\";\n\t\t\tgpios = <&gpio 86 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_tel_blue: tel_blue {\n\t\t\tlabel = \"blue:tel\";\n\t\t\tgpios = <&gpio 41 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_sig1_blue: sig1_blue {\n\t\t\tlabel = \"blue:sig1\";\n\t\t\tgpios = <&gpio 44 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_sig1_red: sig1_red {\n\t\t\tlabel = \"red:sig1\";\n\t\t\tgpios = <&gpio 87 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_sig2_blue: sig2_blue {\n\t\t\tlabel = \"blue:sig2\";\n\t\t\tgpios = <&gpio 45 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_sig3_blue: sig3_blue {\n\t\t\tlabel = \"blue:sig3\";\n\t\t\tgpios = <&gpio 46 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 26 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"WPS\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <50000000>;\n\t\tm25p,fast-read;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x20000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x20000 0x20000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x1fb0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\twifi@0,0 {\n\t\tcompatible = \"pci14c3,7603\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x0000>;\n\t\tieee80211-freq-limit = <2400000 2500000>;\n\t};\n};\n\n&pcie1 {\n\twifi@0,0 {\n\t\tcompatible = \"pci14c3,7662\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\t};\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_factory_4000>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <3>;\n};\n\n&switch0 {\n\tports {\n\t\tport@0 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"modem\";\n\t\t};\n\n\t\twan: port@1 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"wan\";\n\t\t\tnvmem-cells = <&macaddr_factory_4000>;\n\t\t\tnvmem-cell-names = \"mac-address\";\n\t\t};\n\n\t\tport@2 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan\";\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"jtag\", \"uart2\", \"uart3\", \"wdt\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4000: macaddr@4000 {\n\t\treg = <0x28 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_buffalo_wsr-1166dhp.dts",
    "content": "#include \"mt7621.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"buffalo,wsr-1166dhp\", \"mediatek,mt7621-soc\";\n\tmodel = \"Buffalo WSR-1166DHP\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tinternet_g {\n\t\t\tlabel = \"green:internet\";\n\t\t\tgpios = <&gpio 41 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\trouter_g {\n\t\t\tlabel = \"green:router\";\n\t\t\tgpios = <&gpio 42 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\trouter_o {\n\t\t\tlabel = \"orange:router\";\n\t\t\tgpios = <&gpio 43 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tinternet_o {\n\t\t\tlabel = \"orange:internet\";\n\t\t\tgpios = <&gpio 44 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twifi_o {\n\t\t\tlabel = \"orange:wifi\";\n\t\t\tgpios = <&gpio 45 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_power: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 46 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tdiag {\n\t\t\tlabel = \"orange:diag\";\n\t\t\tgpios = <&gpio 47 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twifi_g {\n\t\t\tlabel = \"green:wifi\";\n\t\t\tgpios = <&gpio 48 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\tpower {\n\t\t\tlabel = \"power\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_POWER>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 3 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\taoss {\n\t\t\tlabel = \"aoss\";\n\t\t\tgpios = <&gpio 6 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\n\t\tauto {\n\t\t\tlabel = \"mode\";\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = <BTN_0>;\n\t\t\tlinux,input-type = <EV_SW>;\n\t\t};\n\n\t\tap {\n\t\t\tlabel = \"ap\";\n\t\t\tgpios = <&gpio 10 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = <BTN_0>;\n\t\t\tlinux,input-type = <EV_SW>;\n\t\t};\n\n\t\trouter {\n\t\t\tlabel = \"router\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = <BTN_0>;\n\t\t\tlinux,input-type = <EV_SW>;\n\t\t};\n\t};\n\n\tgpio_poweroff {\n\t\tcompatible = \"gpio-poweroff\";\n\t\tgpios = <&gpio 0 GPIO_ACTIVE_LOW>;\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"openwrt,trx\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0xf90000>;\n\t\t\t};\n\n\t\t\tpartition@fe0000 {\n\t\t\t\tlabel = \"board_data\";\n\t\t\t\treg = <0xfe0000 0x20000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&ethernet {\n\tpinctrl-0 = <&mdio_pins>, <&rgmii1_pins>;\n};\n\n&switch0 {\n\tports {\n\t\tport@0 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan1\";\n\t\t};\n\n\t\tport@1 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan2\";\n\t\t};\n\n\t\tport@2 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan3\";\n\t\t};\n\n\t\tport@3 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan4\";\n\t\t};\n\n\t\tport@4 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"wan\";\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"uart2\", \"uart3\", \"rgmii2\", \"sdhci\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\tmt76@0,0 {\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\t};\n};\n\n&pcie1 {\n\tmt76@0,0 {\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x0000>;\n\t};\n};\n\n&xhci {\n\tstatus = \"disabled\";\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_buffalo_wsr-2533dhpl.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"buffalo,wsr-2533dhpl\", \"mediatek,mt7621-soc\";\n\tmodel = \"Buffalo WSR-2533DHPL\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_diag;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t\tlabel-mac-device = &gmac0;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tinternet_green {\n\t\t\tlabel = \"green:internet\";\n\t\t\tgpios = <&gpio 41 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\trouter_green {\n\t\t\tlabel = \"green:router\";\n\t\t\tgpios = <&gpio 42 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\trouter_amber {\n\t\t\tlabel = \"amber:router\";\n\t\t\tgpios = <&gpio 43 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tinternet_amber {\n\t\t\tlabel = \"amber:internet\";\n\t\t\tgpios = <&gpio 44 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twireless_amber {\n\t\t\tlabel = \"amber:wireless\";\n\t\t\tgpios = <&gpio 45 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_power: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 46 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_diag: diag {\n\t\t\tlabel = \"amber:diag\";\n\t\t\tgpios = <&gpio 47 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twireless_green {\n\t\t\tlabel = \"green:wireless\";\n\t\t\tgpios = <&gpio 48 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 3 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\taoss {\n\t\t\tlabel = \"aoss\";\n\t\t\tgpios = <&gpio 6 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\n\t\tauto {\n\t\t\tlabel = \"auto\";\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_0>;\n\t\t\tlinux,input-type = <EV_SW>;\n\t\t};\n\n\t\tbridge {\n\t\t\tlabel = \"wb\";\n\t\t\tgpios = <&gpio 10 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_1>;\n\t\t\tlinux,input-type = <EV_SW>;\n\t\t};\n\n\t\trouter {\n\t\t\tlabel = \"router\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_1>;\n\t\t\tlinux,input-type = <EV_SW>;\n\t\t};\n\n\t\tpower {\n\t\t\tlabel = \"power\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = <KEY_POWER>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <40000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"openwrt,trx\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x7c0000>;\n\t\t\t};\n\n\t\t\tpartition@810000 {\n\t\t\t\tlabel = \"Kernel2\";\n\t\t\t\treg = <0x810000 0x7c0000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@fd0000 {\n\t\t\t\tlabel = \"glbcfg\";\n\t\t\t\treg = <0xfd0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@fe0000 {\n\t\t\t\tlabel = \"board_data\";\n\t\t\t\treg = <0xfe0000 0x20000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <(-1)>;\n};\n\n&switch0 {\n\tports {\n\t\tport@0 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"wan\";\n\t\t};\n\n\t\tport@1 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan4\";\n\t\t};\n\n\t\tport@2 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan3\";\n\t\t};\n\n\t\tport@3 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan2\";\n\t\t};\n\n\t\tport@4 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan1\";\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\twifi@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x0000>;\n\t\tieee80211-freq-limit = <2400000 2500000>;\n\t};\n};\n\n&pcie1 {\n\twifi@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"uart2\", \"uart3\", \"wdt\", \"sdhci\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&xhci {\n\tstatus = \"disabled\";\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_buffalo_wsr-600dhp.dts",
    "content": "#include \"mt7621.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"buffalo,wsr-600dhp\", \"mediatek,mt7621-soc\";\n\tmodel = \"Buffalo WSR-600DHP\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twifi_o {\n\t\t\tlabel = \"orange:wifi\";\n\t\t\tgpios = <&gpio 41 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tdiag {\n\t\t\tlabel = \"orange:diag\";\n\t\t\tgpios = <&gpio 42 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twifi_g {\n\t\t\tlabel = \"green:wifi\";\n\t\t\tgpios = <&gpio 44 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\trouter_o {\n\t\t\tlabel = \"orange:router\";\n\t\t\tgpios = <&gpio 45 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\trouter_g {\n\t\t\tlabel = \"green:router\";\n\t\t\tgpios = <&gpio 46 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tinternet_o {\n\t\t\tlabel = \"orange:internet\";\n\t\t\tgpios = <&gpio 47 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tinternet_g {\n\t\t\tlabel = \"green:internet\";\n\t\t\tgpios = <&gpio 48 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\tpower {\n\t\t\tlabel = \"power\";\n\t\t\tgpios = <&gpio 8 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_POWER>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\taoss {\n\t\t\tlabel = \"aoss\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\n\t\tauto {\n\t\t\tlabel = \"mode\";\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = <BTN_0>;\n\t\t\tlinux,input-type = <EV_SW>;\n\t\t};\n\n\t\tap {\n\t\t\tlabel = \"ap\";\n\t\t\tgpios = <&gpio 6 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = <BTN_0>;\n\t\t\tlinux,input-type = <EV_SW>;\n\t\t};\n\n\t\trouter {\n\t\t\tlabel = \"router\";\n\t\t\tgpios = <&gpio 10 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = <BTN_0>;\n\t\t\tlinux,input-type = <EV_SW>;\n\t\t};\n\t};\n\n\tgpio_poweroff {\n\t\tcompatible = \"gpio-poweroff\";\n\t\tgpios = <&gpio 43 GPIO_ACTIVE_LOW>;\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0xfb0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"uart2\", \"uart3\", \"rgmii2\", \"sdhci\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\trt5592@0,0 {\n\t\treg = <0x0000 0 0 0 0>;\n\t\tralink,mtd-eeprom = <&factory 0x8000>;\n\t};\n};\n\n&pcie1 {\n\tmt76@0,0 {\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x0000>;\n\t};\n};\n\n&ethernet {\n\tpinctrl-0 = <&mdio_pins>, <&rgmii1_pins>;\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&switch0 {\n\tports {\n\t\tport@0 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan1\";\n\t\t};\n\n\t\tport@1 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan2\";\n\t\t};\n\n\t\tport@2 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan3\";\n\t\t};\n\n\t\tport@3 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan4\";\n\t\t};\n\n\t\tport@4 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"wan\";\n\t\t};\n\t};\n};\n\n&xhci {\n\tstatus = \"disabled\";\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_cudy_wr1300.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621.dtsi\"\n\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/gpio/gpio.h>\n\n/ {\n\tcompatible = \"cudy,wr1300\", \"mediatek,mt7621-soc\";\n\tmodel = \"Cudy WR1300\";\n\n\taliases {\n\t\tled-boot = &led_sys;\n\t\tled-failsafe = &led_sys;\n\t\tled-running = &led_sys;\n\t\tled-upgrade = &led_sys;\n\t\tlabel-mac-device = &gmac0;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio 3 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_sys: sys {\n\t\t\tlabel = \"green:sys\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tusb {\n\t\t\tlabel = \"green:usb\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_HIGH>;\n\t\t\ttrigger-sources = <&xhci_ehci_port1>, <&ehci_port2>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <80000000>;\n\t\tm25p,fast-read;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0xf80000>;\n\t\t\t};\n\n\t\t\tpartition@fd0000 {\n\t\t\t\tlabel = \"debug\";\n\t\t\t\treg = <0xfd0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@fe0000 {\n\t\t\t\tlabel = \"backup\";\n\t\t\t\treg = <0xfe0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tbdinfo: partition@ff0000 {\n\t\t\t\tlabel = \"bdinfo\";\n\t\t\t\treg = <0xff0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\twifi@0,0 {\n\t\tcompatible = \"pci14c3,7603\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x0000>;\n\t\tnvmem-cells = <&macaddr_bdinfo_de00>;\n\t\tnvmem-cell-names = \"mac-address\";\n\t\tieee80211-freq-limit = <2400000 2500000>;\n\n\t\tled {\n\t\t\tled-active-low;\n\t\t};\n\t};\n};\n\n&pcie1 {\n\twifi@0,0 {\n\t\tcompatible = \"pci14c3,7662\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t\tnvmem-cells = <&macaddr_bdinfo_de00>;\n\t\tnvmem-cell-names = \"mac-address\";\n\t\tmac-address-increment = <2>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\n\t\tled {\n\t\t\tled-sources = <2>;\n\t\t\tled-active-low;\n\t\t};\n\t};\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_bdinfo_de00>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&switch0 {\n\tports {\n\t\tport@0 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan4\";\n\t\t};\n\n\t\tport@1 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan3\";\n\t\t};\n\n\t\tport@2 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan2\";\n\t\t};\n\n\t\tport@3 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan1\";\n\t\t};\n\n\t\tport@4 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"wan\";\n\t\t\tnvmem-cells = <&macaddr_bdinfo_de00>;\n\t\t\tnvmem-cell-names = \"mac-address\";\n\t\t\tmac-address-increment = <1>;\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"wdt\", \"i2c\", \"jtag\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&bdinfo {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_bdinfo_de00: macaddr@de00 {\n\t\treg = <0xde00 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_cudy_wr2100.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"cudy,wr2100\", \"mediatek,mt7621-soc\";\n\tmodel = \"Cudy WR2100\";\n\n\taliases {\n\t\tled-boot = &led_internet_blue;\n\t\tled-failsafe = &led_internet_blue;\n\t\tled-running = &led_internet_blue;\n\t\tled-upgrade = &led_internet_blue;\n\t\tlabel-mac-device = &gmac0;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 8 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio 10 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_internet_blue: internet_blue {\n\t\t\tlabel = \"blue:internet\";\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tinternet_red {\n\t\t\tlabel = \"red:internet\";\n\t\t\tgpios = <&gpio 3 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twan {\n\t\t\tlabel = \"green:wan\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan1 {\n\t\t\tlabel = \"green:lan1\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan2 {\n\t\t\tlabel = \"green:lan2\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan3 {\n\t\t\tlabel = \"green:lan3\";\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan4 {\n\t\t\tlabel = \"green:lan4\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_bdinfo_de00>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\twifi@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x0000>;\n\t\tieee80211-freq-limit = <2400000 2500000>;\n\t};\n};\n\n&pcie1 {\n\twifi@1,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <50000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0xf80000>;\n\t\t\t};\n\n\t\t\tpartition@fd0000 {\n\t\t\t\tlabel = \"debug\";\n\t\t\t\treg = <0xfd0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@fe0000 {\n\t\t\t\tlabel = \"backup\";\n\t\t\t\treg = <0xfe0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tbdinfo: partition@ff0000 {\n\t\t\t\tlabel = \"bdinfo\";\n\t\t\t\treg = <0xff0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"jtag\", \"uart2\", \"uart3\", \"wdt\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&switch0 {\n\tports {\n\t\tport@0 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan1\";\n\t\t};\n\n\t\tport@1 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan2\";\n\t\t};\n\n\t\tport@2 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan3\";\n\t\t};\n\n\t\tport@3 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan4\";\n\t\t};\n\n\t\tport@4 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"wan\";\n\n\t\t\tnvmem-cells = <&macaddr_bdinfo_de00>;\n\t\t\tnvmem-cell-names = \"mac-address\";\n\t\t\tmac-address-increment = <1>;\n\t\t};\n\t};\n};\n\n&bdinfo {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_bdinfo_de00: macaddr@de00 {\n\t\treg = <0xde00 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_cudy_x6.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"cudy,x6\", \"mediatek,mt7621-soc\";\n\tmodel = \"CUDY X6\";\n\n\taliases {\n\t\tled-boot = &led_internet_blue;\n\t\tled-failsafe = &led_internet_blue;\n\t\tled-running = &led_internet_blue;\n\t\tled-upgrade = &led_internet_blue;\n\t\tlabel-mac-device = &gmac0;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 8 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_internet_blue: internet_blue {\n\t\t\tlabel = \"blue:internet\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tinternet_red {\n\t\t\tlabel = \"red:internet\";\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <50000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x1f80000>;\n\t\t\t};\n\n\t\t\tpartition@1fd0000 {\n\t\t\t\tlabel = \"debug\";\n\t\t\t\treg = <0x1fd0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@1fe0000 {\n\t\t\t\tlabel = \"backup\";\n\t\t\t\treg = <0x1fe0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tbdinfo: partition@1ff0000 {\n\t\t\t\tlabel = \"bdinfo\";\n\t\t\t\treg = <0x1ff0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie1 {\n\twifi@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x0000>;\n\t};\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_bdinfo_de00>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&switch0 {\n\tports {\n\t\tport@0 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan1\";\n\t\t};\n\n\t\tport@1 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan2\";\n\t\t};\n\n\t\tport@2 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan3\";\n\t\t};\n\n\t\tport@3 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan4\";\n\t\t};\n\n\t\tport@4 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"wan\";\n\t\t\tnvmem-cells = <&macaddr_bdinfo_de00>;\n\t\t\tnvmem-cell-names = \"mac-address\";\n\t\t\tmac-address-increment = <1>;\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"uart3\", \"jtag\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&bdinfo {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_bdinfo_de00: macaddr@de00 {\n\t\treg = <0xde00 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_d-team_newifi-d2.dts",
    "content": "#include \"mt7621.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"d-team,newifi-d2\", \"mediatek,mt7621-soc\";\n\tmodel = \"Newifi-D2\";\n\n\taliases {\n\t\tled-boot = &led_power_blue;\n\t\tled-failsafe = &led_power_blue;\n\t\tled-running = &led_power_blue;\n\t\tled-upgrade = &led_power_blue;\n\t\tlabel-mac-device = &gmac0;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200\";\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tpower-amber {\n\t\t\tlabel = \"amber:power\";\n\t\t\tgpios = <&gpio 6 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_power_blue: power-blue {\n\t\t\tlabel = \"blue:power\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tinternet-amber {\n\t\t\tlabel = \"amber:internet\";\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tinternet-blue {\n\t\t\tlabel = \"blue:internet\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan2g {\n\t\t\tlabel = \"blue:wlan2g\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan5g {\n\t\t\tlabel = \"blue:wlan5g\";\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tusb {\n\t\t\tlabel = \"blue:usb\";\n\t\t\tgpios = <&gpio 10 GPIO_ACTIVE_LOW>;\n\t\t\ttrigger-sources = <&xhci_ehci_port1>, <&ehci_port2>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 3 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n\n\tgpio_export {\n\t\tcompatible = \"gpio-export\";\n\t\t#size-cells = <0>;\n\n\t\tpower_usb3 {\n\t\t\tgpio-export,name = \"power_usb3\";\n\t\t\tgpio-export,output = <1>;\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <45000000>;\n\t\tbroken-flash-reset;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x1fb0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\tmt76@0,0 {\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\t};\n};\n\n&pcie1 {\n\tmt76@0,0 {\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x0000>;\n\t};\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_factory_e000>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&switch0 {\n\tports {\n\t\tport@0 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan4\";\n\t\t};\n\n\t\tport@1 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan3\";\n\t\t};\n\n\t\tport@2 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan2\";\n\t\t};\n\n\t\tport@3 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan1\";\n\t\t};\n\n\t\tport@4 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"wan\";\n\t\t\tnvmem-cells = <&macaddr_factory_e006>;\n\t\t\tnvmem-cell-names = \"mac-address\";\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"jtag\", \"uart2\", \"uart3\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_e000: macaddr@e000 {\n\t\treg = <0xe000 0x6>;\n\t};\n\n\tmacaddr_factory_e006: macaddr@e006 {\n\t\treg = <0xe006 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_d-team_pbr-m1.dts",
    "content": "#include \"mt7621.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"d-team,pbr-m1\", \"mediatek,mt7621-soc\";\n\tmodel = \"PBR-M1\";\n\n\taliases {\n\t\tled-boot = &led_sys;\n\t\tled-failsafe = &led_sys;\n\t\tled-running = &led_sys;\n\t\tled-upgrade = &led_sys;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200\";\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tpower {\n\t\t\tlabel = \"blue:power\";\n\t\t\tgpios = <&gpio 31 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\tled_sys: sys {\n\t\t\tlabel = \"blue:sys\";\n\t\t\tgpios = <&gpio 32 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tinternet {\n\t\t\tlabel = \"blue:internet\";\n\t\t\tgpios = <&gpio 29 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan2g {\n\t\t\tlabel = \"blue:wlan2g\";\n\t\t\tgpios = <&gpio 33 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan5g {\n\t\t\tlabel = \"blue:wlan5g\";\n\t\t\tgpios = <&gpio 28 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tgpio_export {\n\t\tcompatible = \"gpio-export\";\n\t\t#size-cells = <0>;\n\n\t\tpower_usb2 {\n\t\t\tgpio-export,name = \"power_usb2\";\n\t\t\tgpio-export,output = <1>;\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tpower_usb3 {\n\t\t\tgpio-export,name = \"power_usb3\";\n\t\t\tgpio-export,output = <1>;\n\t\t\tgpios = <&gpio 25 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tpower_sata {\n\t\t\tgpio-export,name = \"power_sata\";\n\t\t\tgpio-export,output = <1>;\n\t\t\tgpios = <&gpio 27 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n\n\tbeeper: beeper {\n\t\tcompatible = \"gpio-beeper\";\n\t\tgpios = <&gpio 26 GPIO_ACTIVE_LOW>;\n\t};\n};\n\n&i2c {\n\tstatus = \"okay\";\n\n\trtc@51 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"nxp,pcf8563\";\n\t\treg = <0x51>;\n\t};\n};\n\n&sdhci {\n\tstatus = \"okay\";\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <50000000>;\n\t\tm25p,fast-read;\n\t\tbroken-flash-reset;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x1fb0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pinctrl {\n\tuart3_gpio: uart3-gpio {\n\t\tuart3 {\n\t\t\tgroups = \"uart3\";\n\t\t\tfunction = \"gpio\";\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n\tpinctrl-0 = <&pcie_pins>, <&uart3_gpio>;\n\treset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>,\n\t\t      <&gpio 7 GPIO_ACTIVE_LOW>;\n};\n\n&pcie0 {\n\tmt76@0,0 {\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\t};\n};\n\n&pcie1 {\n\tmt76@0,0 {\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x0000>;\n\t};\n};\n\n&ethernet {\n\tpinctrl-0 = <&mdio_pins>, <&rgmii1_pins>;\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_factory_e000>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&switch0 {\n\tports {\n\t\tport@0 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan1\";\n\t\t};\n\n\t\tport@1 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan2\";\n\t\t};\n\n\t\tport@2 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan3\";\n\t\t};\n\n\t\tport@3 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan4\";\n\t\t};\n\n\t\tport@4 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"wan\";\n\t\t\tnvmem-cells = <&macaddr_factory_e006>;\n\t\t\tnvmem-cell-names = \"mac-address\";\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"wdt\", \"rgmii2\", \"jtag\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_e000: macaddr@e000 {\n\t\treg = <0xe000 0x6>;\n\t};\n\n\tmacaddr_factory_e006: macaddr@e006 {\n\t\treg = <0xe006 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_dlink_dir-1960-a1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621_dlink_dir-xx60-a1.dtsi\"\n\n/ {\n\tcompatible = \"dlink,dir-1960-a1\", \"mediatek,mt7621-soc\";\n\tmodel = \"D-Link DIR-1960 A1\";\n};\n\n&leds {\n\tusb_white {\n\t\tlabel = \"white:usb\";\n\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\ttrigger-sources = <&xhci_ehci_port1>;\n\t\tlinux,default-trigger = \"usbport\";\n\t};\n};\n\n&wifi0 {\n\tnvmem-cells = <&macaddr_factory_e000>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <1>;\n};\n\n&wifi1 {\n\tnvmem-cells = <&macaddr_factory_e000>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <2>;\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_dlink_dir-2640-a1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621_dlink_dir-xx60-a1.dtsi\"\n\n/ {\n\tcompatible = \"dlink,dir-2640-a1\", \"mediatek,mt7621-soc\";\n\tmodel = \"D-Link DIR-2640 A1\";\n};\n\n&leds {\n\tusb2_white {\n\t\tlabel = \"white:usb2\";\n\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\ttrigger-sources = <&ehci_port2>;\n\t\tlinux,default-trigger = \"usbport\";\n\t};\n\n\tusb3_white {\n\t\tlabel = \"white:usb3\";\n\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\ttrigger-sources = <&xhci_ehci_port1>;\n\t\tlinux,default-trigger = \"usbport\";\n\t};\n};\n\n&wifi0 {\n\tnvmem-cells = <&macaddr_factory_e000>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <1>;\n};\n\n&wifi1 {\n\tnvmem-cells = <&macaddr_factory_e000>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <2>;\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_dlink_dir-2660-a1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621_dlink_dir-xx60-a1.dtsi\"\n\n/ {\n\tcompatible = \"dlink,dir-2660-a1\", \"mediatek,mt7621-soc\";\n\tmodel = \"D-Link DIR-2660 A1\";\n};\n\n&leds {\n\tusb2_white {\n\t\tlabel = \"white:usb2\";\n\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\ttrigger-sources = <&ehci_port2>;\n\t\tlinux,default-trigger = \"usbport\";\n\t};\n\n\tusb3_white {\n\t\tlabel = \"white:usb3\";\n\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\ttrigger-sources = <&xhci_ehci_port1>;\n\t\tlinux,default-trigger = \"usbport\";\n\t};\n};\n\n&wifi0 {\n\tnvmem-cells = <&macaddr_factory_e000>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <1>;\n};\n\n&wifi1 {\n\tnvmem-cells = <&macaddr_factory_e000>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <2>;\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_dlink_dir-853-a3.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"dlink,dir-853-a3\", \"mediatek,mt7621-soc\";\n\tmodel = \"D-Link DIR-853 A3\";\n\n\taliases {\n\t\tlabel-mac-device = &gmac0;\n\n\t\tled-boot = &led_power_orange;\n\t\tled-failsafe = &led_power_blue;\n\t\tled-running = &led_power_blue;\n\t\tled-upgrade = &led_net_orange;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 8 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\n\t\twifi {\n\t\t\tlabel = \"wifi\";\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RFKILL>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power_orange: power_orange {\n\t\t\tlabel = \"orange:power\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_power_blue: power_blue {\n\t\t\tlabel = \"blue:power\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_net_orange: net_orange {\n\t\t\tlabel = \"orange:net\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tnet_blue {\n\t\t\tlabel = \"blue:net\";\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tusb_blue {\n\t\t\tlabel = \"blue:usb\";\n\t\t\tgpios = <&gpio 10 GPIO_ACTIVE_LOW>;\n\t\t\ttrigger-sources = <&xhci_ehci_port1>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\n\t\twlan2g {\n\t\t\tlabel = \"blue:wlan2g\";\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0radio\";\n\t\t};\n\n\t\twlan5g {\n\t\t\tlabel = \"blue:wlan5g\";\n\t\t\tgpios = <&gpio 3 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1radio\";\n\t\t};\n\t};\n};\n\n&nand {\n\tstatus = \"okay\";\n\n\tpartitions {\n\t\tcompatible = \"fixed-partitions\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"u-boot\";\n\t\t\treg = <0x0 0x80000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@80000 {\n\t\t\tlabel = \"config\";\n\t\t\treg = <0x80000 0x80000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tfactory: partition@100000 {\n\t\t\tlabel = \"factory\";\n\t\t\treg = <0x100000 0x40000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@140000 {\n\t\t\tlabel = \"config2\";\n\t\t\treg = <0x140000 0x40000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@180000 {\n\t\t\tlabel = \"firmware\";\n\t\t\tcompatible = \"openwrt,uimage\", \"denx,uimage\";\n\t\t\topenwrt,padding = <96>;\n\t\t\treg = <0x180000 0x2800000>;\n\t\t};\n\n\t\tpartition@2980000 {\n\t\t\tlabel = \"private\";\n\t\t\treg = <0x2980000 0x2000000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@4980000 {\n\t\t\tlabel = \"firmware2\";\n\t\t\treg = <0x4980000 0x2800000>;\n\t\t};\n\n\t\tpartition@7180000 {\n\t\t\tlabel = \"mydlink\";\n\t\t\treg = <0x7180000 0x600000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@7780000 {\n\t\t\tlabel = \"reserved\";\n\t\t\treg = <0x7780000 0x880000>;\n\t\t\tread-only;\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\twifi@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x0>;\n\t\t/* 5 GHz (phy1) does not take the address from calibration data,\n\t\t   but setting it manually here works */\n\t\tnvmem-cells = <&macaddr_factory_4>;\n\t\tnvmem-cell-names = \"mac-address\";\n\t};\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_factory_e000>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&switch0 {\n\tports {\n\t\tport@0 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan4\";\n\t\t};\n\n\t\tport@1 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan3\";\n\t\t};\n\n\t\tport@2 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan2\";\n\t\t};\n\n\t\tport@3 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan1\";\n\t\t};\n\n\t\tport@4 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"wan\";\n\t\t\tnvmem-cells = <&macaddr_factory_e006>;\n\t\t\tnvmem-cell-names = \"mac-address\";\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"uart2\", \"uart3\", \"jtag\", \"wdt\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n\n\tmacaddr_factory_e000: macaddr@e000 {\n\t\treg = <0xe000 0x6>;\n\t};\n\n\tmacaddr_factory_e006: macaddr@e006 {\n\t\treg = <0xe006 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_dlink_dir-853-r1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621.dtsi\"\n\n#include \"mt7621_dlink_flash-16m-r1.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"dlink,dir-853-r1\", \"mediatek,mt7621-soc\";\n\tmodel = \"D-Link DIR-853 R1\";\n\n\taliases {\n\t\tlabel-mac-device = &wan;\n\n\t\tled-boot = &led_power_orange;\n\t\tled-failsafe = &led_power_blue;\n\t\tled-running = &led_power_blue;\n\t\tled-upgrade = &led_net_orange;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power_orange: power_orange {\n\t\t\tlabel = \"orange:power\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_power_blue: power_blue {\n\t\t\tlabel = \"blue:power\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_net_orange: net_orange {\n\t\t\tlabel = \"orange:net\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tnet_blue {\n\t\t\tlabel = \"blue:net\";\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tusb_blue {\n\t\t\tlabel = \"blue:usb\";\n\t\t\tgpios = <&gpio 10 GPIO_ACTIVE_LOW>;\n\t\t\ttrigger-sources = <&xhci_ehci_port1>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\n\t\twlan2g {\n\t\t\tlabel = \"blue:wlan2g\";\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0radio\";\n\t\t};\n\n\t\twlan5g {\n\t\t\tlabel = \"blue:wlan5g\";\n\t\t\tgpios = <&gpio 3 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1radio\";\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 8 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\n\t\twifi {\n\t\t\tlabel = \"wifi\";\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RFKILL>;\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\twifi@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0000 0 0 0 0>;\n\n\t\tmediatek,mtd-eeprom = <&factory 0x0>;\n\n\t\t/* 5 GHz (phy1) does not take the address from calibration data,\n\t\t   but setting it manually here works */\n\t\tnvmem-cells = <&macaddr_factory_4>;\n\t\tnvmem-cell-names = \"mac-address\";\n\t};\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <(-1)>;\n};\n\n&switch0 {\n\tports {\n\t\tport@0 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan4\";\n\t\t};\n\n\t\tport@1 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan3\";\n\t\t};\n\n\t\tport@2 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan2\";\n\t\t};\n\n\t\tport@3 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan1\";\n\t\t};\n\n\t\twan: port@4 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"wan\";\n\t\t\tnvmem-cells = <&macaddr_factory_4>;\n\t\t\tnvmem-cell-names = \"mac-address\";\n\t\t\tmac-address-increment = <(-2)>;\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"uart3\", \"uart2\", \"jtag\", \"wdt\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_dlink_dir-860l-b1.dts",
    "content": "#include \"mt7621.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"dlink,dir-860l-b1\", \"mediatek,mt7621-soc\";\n\tmodel = \"D-Link DIR-860L B1\";\n\n\taliases {\n\t\tlabel-mac-device = &gmac0;\n\n\t\tled-boot = &led_power_green;\n\t\tled-failsafe = &led_power_green;\n\t\tled-running = &led_power_green;\n\t\tled-upgrade = &led_power_green;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tpower {\n\t\t\tlabel = \"orange:power\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_power_green: power2 {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tnet {\n\t\t\tlabel = \"orange:net\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tnet2 {\n\t\t\tlabel = \"green:net\";\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x4000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tradio: partition@34000 {\n\t\t\t\tlabel = \"radio\";\n\t\t\t\treg = <0x34000 0x4000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@38000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x38000 0x8000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"defaults\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"seama\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0xfb0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_radio_4>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&switch0 {\n\tports {\n\t\tport@0 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"wan\";\n\t\t};\n\n\t\tport@1 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan4\";\n\t\t};\n\n\t\tport@2 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan3\";\n\t\t};\n\n\t\tport@3 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan2\";\n\t\t};\n\n\t\tport@4 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan1\";\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n\n\treset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>,\n\t\t      <&gpio 8 GPIO_ACTIVE_LOW>;\n};\n\n&pcie0 {\n\twifi0: mt76@0,0 {\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&radio 0x2000>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\t};\n};\n\n&pcie1 {\n\twifi1: mt76@0,0 {\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&radio 0x0>;\n\t\tieee80211-freq-limit = <2400000 2500000>;\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"uart3\", \"jtag\", \"wdt\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&radio {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_radio_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_dlink_dir-867-a1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621_dlink_dir-8xx.dtsi\"\n#include \"mt7621_dlink_flash-16m-a1.dtsi\"\n\n/ {\n\tcompatible = \"dlink,dir-867-a1\", \"mediatek,mt7621-soc\";\n\tmodel = \"D-Link DIR-867 A1\";\n\n\taliases {\n\t\tlabel-mac-device = &gmac0;\n\t};\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_factory_e000>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wan {\n\tnvmem-cells = <&macaddr_factory_e006>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_e000: macaddr@e000 {\n\t\treg = <0xe000 0x6>;\n\t};\n\n\tmacaddr_factory_e006: macaddr@e006 {\n\t\treg = <0xe006 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_dlink_dir-878-a1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621_dlink_dir-8xx.dtsi\"\n#include \"mt7621_dlink_flash-16m-a1.dtsi\"\n\n/ {\n\tcompatible = \"dlink,dir-878-a1\", \"mediatek,mt7621-soc\";\n\tmodel = \"D-Link DIR-878 A1\";\n\n\taliases {\n\t\tlabel-mac-device = &gmac0;\n\t};\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_factory_e000>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wan {\n\tnvmem-cells = <&macaddr_factory_e006>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_e000: macaddr@e000 {\n\t\treg = <0xe000 0x6>;\n\t};\n\n\tmacaddr_factory_e006: macaddr@e006 {\n\t\treg = <0xe006 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_dlink_dir-878-r1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621_dlink_dir-8xx.dtsi\"\n#include \"mt7621_dlink_flash-16m-r1.dtsi\"\n\n/ {\n\tcompatible = \"dlink,dir-878-r1\", \"mediatek,mt7621-soc\";\n\tmodel = \"D-Link DIR-878 R1\";\n\n\taliases {\n\t\tlabel-mac-device = &gmac0;\n\t};\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_factory_e000>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wan {\n\tnvmem-cells = <&macaddr_factory_e006>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_e000: macaddr@e000 {\n\t\treg = <0xe000 0x6>;\n\t};\n\n\tmacaddr_factory_e006: macaddr@e006 {\n\t\treg = <0xe006 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_dlink_dir-882-a1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621_dlink_dir-8xx.dtsi\"\n#include \"mt7621_dlink_flash-16m-a1.dtsi\"\n\n/ {\n\tcompatible = \"dlink,dir-882-a1\", \"mediatek,mt7621-soc\";\n\tmodel = \"D-Link DIR-882 A1\";\n\n\taliases {\n\t\tlabel-mac-device = &gmac0;\n\t};\n};\n\n&leds {\n\tusb2 {\n\t\tlabel = \"green:usb2\";\n\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\ttrigger-sources = <&ehci_port2>;\n\t\tlinux,default-trigger = \"usbport\";\n\t};\n\n\tusb3 {\n\t\tlabel = \"green:usb3\";\n\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\ttrigger-sources = <&xhci_ehci_port1>;\n\t\tlinux,default-trigger = \"usbport\";\n\t};\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_factory_e000>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wan {\n\tnvmem-cells = <&macaddr_factory_e006>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_e000: macaddr@e000 {\n\t\treg = <0xe000 0x6>;\n\t};\n\n\tmacaddr_factory_e006: macaddr@e006 {\n\t\treg = <0xe006 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_dlink_dir-882-r1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621_dlink_dir-8xx.dtsi\"\n#include \"mt7621_dlink_flash-16m-r1.dtsi\"\n\n/ {\n\tcompatible = \"dlink,dir-882-r1\", \"mediatek,mt7621-soc\";\n\tmodel = \"D-Link DIR-882 R1\";\n\n\taliases {\n\t\tlabel-mac-device = &gmac0;\n\t};\n};\n\n&leds {\n\tusb2 {\n\t\tlabel = \"green:usb2\";\n\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\ttrigger-sources = <&ehci_port2>;\n\t\tlinux,default-trigger = \"usbport\";\n\t};\n\n\tusb3 {\n\t\tlabel = \"green:usb3\";\n\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\ttrigger-sources = <&xhci_ehci_port1>;\n\t\tlinux,default-trigger = \"usbport\";\n\t};\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_factory_e000>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wan {\n\tnvmem-cells = <&macaddr_factory_e006>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_e000: macaddr@e000 {\n\t\treg = <0xe000 0x6>;\n\t};\n\n\tmacaddr_factory_e006: macaddr@e006 {\n\t\treg = <0xe006 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_dlink_dir-8xx.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\taliases {\n\t\tled-boot = &led_power_orange;\n\t\tled-failsafe = &led_power_green;\n\t\tled-running = &led_power_green;\n\t\tled-upgrade = &led_net_orange;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\n\t\twifi {\n\t\t\tlabel = \"wifi\";\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RFKILL>;\n\t\t};\n\t};\n\n\tleds: leds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power_orange: power_orange {\n\t\t\tlabel = \"orange:power\";\n\t\t\tgpios = <&gpio 8 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_power_green: power_green {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_net_orange: net_orange {\n\t\t\tlabel = \"orange:net\";\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tnet_green {\n\t\t\tlabel = \"green:net\";\n\t\t\tgpios = <&gpio 3 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\twifi@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x0000>;\n\t\tieee80211-freq-limit = <2400000 2500000>;\n\n\t\tled {\n\t\t\tled-active-low;\n\t\t};\n\t};\n};\n\n&pcie1 {\n\twifi@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\n\t\tled {\n\t\t\tled-active-low;\n\t\t};\n\t};\n};\n\n&switch0 {\n\tports {\n\t\tport@0 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan4\";\n\t\t};\n\n\t\tport@1 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan3\";\n\t\t};\n\n\t\tport@2 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan2\";\n\t\t};\n\n\t\tport@3 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan1\";\n\t\t};\n\n\t\twan: port@4 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"wan\";\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"uart3\", \"jtag\", \"wdt\";\n\t\tfunction = \"gpio\";\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_dlink_dir-xx60-a1.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\taliases {\n\t\tlabel-mac-device = &gmac0;\n\t\tled-boot = &led_power_orange;\n\t\tled-failsafe = &led_power_white;\n\t\tled-running = &led_power_white;\n\t\tled-upgrade = &led_net_orange;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n\n\tleds: leds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power_orange: power_orange {\n\t\t\tlabel = \"orange:power\";\n\t\t\tgpios = <&gpio 8 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_power_white: power_white {\n\t\t\tlabel = \"white:power\";\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_net_orange: net_orange {\n\t\t\tlabel = \"orange:net\";\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tnet_white {\n\t\t\tlabel = \"white:net\";\n\t\t\tgpios = <&gpio 3 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&nand {\n\tstatus = \"okay\";\n\n\tpartitions {\n\t\tcompatible = \"fixed-partitions\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"Bootloader\";\n\t\t\treg = <0x0 0x80000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@80000 {\n\t\t\tlabel = \"config\";\n\t\t\treg = <0x80000 0x80000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tfactory: partition@100000 {\n\t\t\tlabel = \"factory\";\n\t\t\treg = <0x100000 0x40000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@140000 {\n\t\t\tlabel = \"config2\";\n\t\t\treg = <0x140000 0x40000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@180000 {\n\t\t\tlabel = \"firmware\";\n\t\t\tcompatible = \"openwrt,uimage\", \"denx,uimage\";\n\t\t\topenwrt,padding = <96>;\n\t\t\treg = <0x180000 0x2800000>;\n\t\t};\n\n\t\tpartition@2980000 {\n\t\t\tlabel = \"private\";\n\t\t\treg = <0x2980000 0x2000000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@4980000 {\n\t\t\tlabel = \"firmware2\";\n\t\t\treg = <0x4980000 0x2800000>;\n\t\t};\n\n\t\tpartition@7180000 {\n\t\t\tlabel = \"mydlink\";\n\t\t\treg = <0x7180000 0x600000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@7780000 {\n\t\t\tlabel = \"reserved\";\n\t\t\treg = <0x7780000 0x880000>;\n\t\t\tread-only;\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\twifi0: wifi@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x0000>;\n\t\tieee80211-freq-limit = <2400000 2500000>;\n\n\t\tled {\n\t\t\tled-active-low;\n\t\t};\n\t};\n};\n\n&pcie1 {\n\twifi1: wifi@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\n\t\tled {\n\t\t\tled-active-low;\n\t\t};\n\t};\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_factory_e000>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&switch0 {\n\tports {\n\t\tport@0 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan4\";\n\t\t};\n\n\t\tport@1 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan3\";\n\t\t};\n\n\t\tport@2 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan2\";\n\t\t};\n\n\t\tport@3 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan1\";\n\t\t};\n\n\t\tport@4 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"wan\";\n\t\t\tnvmem-cells = <&macaddr_factory_e006>;\n\t\t\tnvmem-cell-names = \"mac-address\";\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"uart3\", \"jtag\", \"wdt\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_e000: macaddr@e000 {\n\t\treg = <0xe000 0x6>;\n\t};\n\n\tmacaddr_factory_e006: macaddr@e006 {\n\t\treg = <0xe006 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_dlink_flash-16m-a1.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <50000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x20000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@60000 {\n\t\t\t\tcompatible = \"openwrt,uimage\", \"denx,uimage\";\n\t\t\t\topenwrt,padding = <96>;\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x60000 0xfa0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_dlink_flash-16m-r1.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <50000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0xfb0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_dual-q_h721.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"dual-q,h721\", \"mediatek,mt7621-soc\";\n\tmodel = \"Dual-Q H721\";\n\n\taliases {\n\t\tled-boot = &led_status;\n\t\tled-failsafe = &led_status;\n\t\tled-running = &led_status;\n\t\tled-upgrade = &led_status;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200\";\n\t};\n\n\tgpio-export {\n\t\tcompatible = \"gpio-export\";\n\t\t#size-cells = <0>;\n\n\t\tusb-30-power {\n\t\t\tgpio-export,name = \"usb-30-power\";\n\t\t\tgpio-export,output = <0>;\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tusb-20-power {\n\t\t\tgpio-export,name = \"usb-20-power\";\n\t\t\tgpio-export,output = <0>;\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tusb1 {\n\t\t\tlabel = \"green:usb1\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tsig1 {\n\t\t\tlabel = \"green:sig1\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tusb2 {\n\t\t\tlabel = \"green:usb2\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tsig2 {\n\t\t\tlabel = \"green:sig2\";\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\ttf {\n\t\t\tlabel = \"green:tf\";\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twifi1 {\n\t\t\tlabel = \"green:wifi1\";\n\t\t\tgpios = <&gpio 24 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twifi2 {\n\t\t\tlabel = \"green:wifi2\";\n\t\t\tgpios = <&gpio 25 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_status: status {\n\t\t\tlabel = \"green:status\";\n\t\t\tgpios = <&gpio 27 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <40000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"bootloader\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"config\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\n\t\t\t\tcompatible = \"nvmem-cells\";\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\n\t\t\t\tmacaddr_factory_e000: macaddr@e000 {\n\t\t\t\t\treg = <0xe000 0x6>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0xfb0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&sdhci {\n\tstatus = \"okay\";\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&switch0 {\n\tports {\n\t\tport@0 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan1\";\n\t\t};\n\n\t\tport@1 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan2\";\n\t\t};\n\n\t\tport@2 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan3\";\n\t\t};\n\n\t\tport@3 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan4\";\n\t\t};\n\n\t\tport@4 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"wan\";\n\n\t\t\tnvmem-cells = <&macaddr_factory_e000>;\n\t\t\tnvmem-cell-names = \"mac-address\";\n\t\t\tmac-address-increment = <1>;\n\t\t};\n\t};\n};\n\n&ethernet {\n\tpinctrl-0 = <&mdio_pins>, <&rgmii1_pins>;\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_factory_e000>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"jtag\", \"wdt\", \"rgmii2\";\n\t\tfunction = \"gpio\";\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_edimax_ra21s.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621_edimax_rx21s.dtsi\"\n\n/ {\n\tcompatible = \"edimax,ra21s\", \"mediatek,mt7621-soc\";\n\tmodel = \"Edimax RA21S\";\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_edimax_re23s.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/mtd/partitions/uimage.h>\n\n/ {\n\tcompatible = \"edimax,re23s\", \"mediatek,mt7621-soc\";\n\tmodel = \"Edimax RE23S\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_wifi_red;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t\tlabel-mac-device = &gmac0;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\twifi_green {\n\t\t\tlabel = \"green:wifi\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\twifi_amber {\n\t\t\tlabel = \"amber:wifi\";\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tled_wifi_red: wifi_red {\n\t\t\tlabel = \"red:wifi\";\n\t\t\tgpios = <&gpio 6 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <50000000>;\n\t\tm25p,fast-read;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"bootloader\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"config\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tlabel = \"cimage\";\n\t\t\t\treg = <0x50000 0x20000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@70000 {\n\t\t\t\tcompatible = \"openwrt,uimage\", \"denx,uimage\";\n\t\t\t\topenwrt,offset = <FW_EDIMAX_OFFSET>;\n\t\t\t\topenwrt,partition-magic = <FW_MAGIC_EDIMAX>;\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x70000 0xf50000>;\n\t\t\t};\n\n\t\t\tpartition@fc0000 {\n\t\t\t\tlabel = \"freespace\";\n\t\t\t\treg = <0xfc0000 0x40000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\twifi@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x0>;\n\t\tieee80211-freq-limit = <2400000 2500000>;\n\t};\n};\n\n&pcie1 {\n\twifi@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\t};\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_factory_8004>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&switch0 {\n\tports {\n\t\tport@4 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan\";\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"uart3\", \"uart2\", \"jtag\", \"wdt\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&xhci {\n\tstatus = \"disabled\";\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_8004: macaddr@8004 {\n\t\treg = <0x8004 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_edimax_rg21s.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621_edimax_rx21s.dtsi\"\n\n/ {\n\tcompatible = \"edimax,rg21s\", \"mediatek,mt7621-soc\";\n\tmodel = \"Edimax RG21S\";\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_edimax_rx21s.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\taliases {\n\t\tlabel-mac-device = &gmac0;\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: led_1 {\n\t\t\tlabel = \"red:led1\";\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tled_2 {\n\t\t\tlabel = \"red:led2\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tled_3 {\n\t\t\tlabel = \"red:led3\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tled_4 {\n\t\t\tlabel = \"red:led4\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <40000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0xfb0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\twifi0: wifi@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x0000>;\n\t\tieee80211-freq-limit = <2400000 2500000>;\n\t};\n};\n\n&pcie1 {\n\twifi1: wifi@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\t};\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&switch0 {\n\tports {\n\t\tport@0 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"wan\";\n\t\t};\n\n\t\tport@1 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan4\";\n\t\t};\n\n\t\tport@2 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan3\";\n\t\t};\n\n\t\tport@3 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan2\";\n\t\t};\n\n\t\tport@4 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan1\";\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"uart3\", \"uart2\", \"jtag\", \"wdt\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&xhci {\n\tstatus = \"disabled\";\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_elecom_wrc-1167ghbk2-s.dts",
    "content": "#include \"mt7621.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"elecom,wrc-1167ghbk2-s\", \"mediatek,mt7621-soc\";\n\tmodel = \"ELECOM WRC-1167GHBK2-S\";\n\n\taliases {\n\t\tled-boot = &led_power_green;\n\t\tled-failsafe = &led_power_green;\n\t\tled-running = &led_power_green;\n\t\tled-upgrade = &led_power_green;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twlan2g {\n\t\t\tlabel = \"white:wlan2g\";\n\t\t\tgpios = <&gpio 3 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0radio\";\n\t\t};\n\n\t\twlan5g {\n\t\t\tlabel = \"white:wlan5g\";\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_power_green: power_green {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tpower_blue {\n\t\t\tlabel = \"blue:power\";\n\t\t\tgpios = <&gpio 8 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"red:wps\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tpower_red {\n\t\t\tlabel = \"red:power\";\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_factory_e000>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&switch0 {\n\tports {\n\t\tport@0 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"wan\";\n\t\t\tnvmem-cells = <&macaddr_factory_e006>;\n\t\t\tnvmem-cell-names = \"mac-address\";\n\t\t};\n\n\t\tport@1 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan4\";\n\t\t};\n\n\t\tport@2 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan3\";\n\t\t};\n\n\t\tport@3 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan2\";\n\t\t};\n\n\t\tport@4 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan1\";\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0xf20000>;\n\t\t\t};\n\n\t\t\tpartition@f70000 {\n\t\t\t\tlabel = \"user_data\";\n\t\t\t\treg = <0xf70000 0x80000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@ff0000 {\n\t\t\t\tlabel = \"NVRAM\";\n\t\t\t\treg = <0xff0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"uart3\", \"jtag\", \"wdt\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\twifi@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x0>;\n\t\tnvmem-cells = <&macaddr_factory_e000>;\n\t\tnvmem-cell-names = \"mac-address\";\n\t\tmac-address-increment = <1>;\n\t};\n};\n\n&xhci {\n\tstatus = \"disabled\";\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_e000: macaddr@e000 {\n\t\treg = <0xe000 0x6>;\n\t};\n\n\tmacaddr_factory_e006: macaddr@e006 {\n\t\treg = <0xe006 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_elecom_wrc-1167gs2-b.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621_elecom_wrc-gs-1pci.dtsi\"\n\n/ {\n\tcompatible = \"elecom,wrc-1167gs2-b\", \"mediatek,mt7621-soc\";\n\tmodel = \"ELECOM WRC-1167GS2-B\";\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_factory_fff4>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wan {\n\tnvmem-cells = <&macaddr_factory_fffa>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&partitions {\n\tpartition@50000 {\n\t\tcompatible = \"denx,uimage\";\n\t\tlabel = \"firmware\";\n\t\treg = <0x50000 0xb00000>;\n\t};\n\n\tpartition@b50000 {\n\t\tlabel = \"tm_pattern\";\n\t\treg = <0xb50000 0x380000>;\n\t\tread-only;\n\t};\n\n\tpartition@ed0000 {\n\t\tlabel = \"tm_key\";\n\t\treg = <0xed0000 0x80000>;\n\t\tread-only;\n\t};\n\n\tpartition@f50000 {\n\t\tlabel = \"nvram\";\n\t\treg = <0xf50000 0x30000>;\n\t\tread-only;\n\t};\n\n\tpartition@f80000 {\n\t\tlabel = \"user_data\";\n\t\treg = <0xf80000 0x80000>;\n\t\tread-only;\n\t};\n};\n\n&wifi {\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <(-1)>;\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n\n\tmacaddr_factory_fff4: macaddr@fff4 {\n\t\treg = <0xfff4 0x6>;\n\t};\n\n\tmacaddr_factory_fffa: macaddr@fffa {\n\t\treg = <0xfffa 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_elecom_wrc-1167gst2.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621_elecom_wrc-gs-1pci.dtsi\"\n\n/ {\n\tcompatible = \"elecom,wrc-1167gst2\", \"mediatek,mt7621-soc\";\n\tmodel = \"ELECOM WRC-1167GST2\";\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_factory_e000>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wan {\n\tnvmem-cells = <&macaddr_factory_e006>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&partitions {\n\tpartition@50000 {\n\t\tcompatible = \"denx,uimage\";\n\t\tlabel = \"firmware\";\n\t\treg = <0x50000 0x1800000>;\n\t};\n\n\tpartition@1850000 {\n\t\tlabel = \"tm_pattern\";\n\t\treg = <0x1850000 0x400000>;\n\t\tread-only;\n\t};\n\n\tpartition@1c50000 {\n\t\tlabel = \"tm_key\";\n\t\treg = <0x1c50000 0x100000>;\n\t\tread-only;\n\t};\n\n\tpartition@1d50000 {\n\t\tlabel = \"nvram\";\n\t\treg = <0x1d50000 0xb0000>;\n\t\tread-only;\n\t};\n\n\tpartition@1e00000 {\n\t\tlabel = \"user_data\";\n\t\treg = <0x1e00000 0x200000>;\n\t\tread-only;\n\t};\n};\n\n&wifi {\n\tnvmem-cells = <&macaddr_factory_e006>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <1>;\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_e000: macaddr@e000 {\n\t\treg = <0xe000 0x6>;\n\t};\n\n\tmacaddr_factory_e006: macaddr@e006 {\n\t\treg = <0xe006 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_elecom_wrc-1750gs.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621_elecom_wrc-gs-2pci.dtsi\"\n\n/ {\n\tcompatible = \"elecom,wrc-1750gs\", \"mediatek,mt7621-soc\";\n\tmodel = \"ELECOM WRC-1750GS\";\n};\n\n&partitions {\n\tpartition@50000 {\n\t\tcompatible = \"denx,uimage\";\n\t\tlabel = \"firmware\";\n\t\treg = <0x50000 0xb00000>;\n\t};\n\n\tpartition@b50000 {\n\t\tlabel = \"tm_pattern\";\n\t\treg = <0xb50000 0x380000>;\n\t\tread-only;\n\t};\n\n\tpartition@ed0000 {\n\t\tlabel = \"tm_key\";\n\t\treg = <0xed0000 0x80000>;\n\t\tread-only;\n\t};\n\n\tpartition@f50000 {\n\t\tlabel = \"art_block\";\n\t\treg = <0xf50000 0x30000>;\n\t\tread-only;\n\t};\n\n\tpartition@f80000 {\n\t\tlabel = \"user_data\";\n\t\treg = <0xf80000 0x80000>;\n\t\tread-only;\n\t};\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_factory_e000>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wan {\n\tnvmem-cells = <&macaddr_factory_e006>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_e000: macaddr@e000 {\n\t\treg = <0xe000 0x6>;\n\t};\n\n\tmacaddr_factory_e006: macaddr@e006 {\n\t\treg = <0xe006 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_elecom_wrc-1750gst2.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621_elecom_wrc-gs-2pci.dtsi\"\n\n/ {\n\tcompatible = \"elecom,wrc-1750gst2\", \"mediatek,mt7621-soc\";\n\tmodel = \"ELECOM WRC-1750GST2\";\n};\n\n&partitions {\n\tpartition@50000 {\n\t\tcompatible = \"denx,uimage\";\n\t\tlabel = \"firmware\";\n\t\treg = <0x50000 0x1800000>;\n\t};\n\n\tpartition@1850000 {\n\t\tlabel = \"tm_pattern\";\n\t\treg = <0x1850000 0x400000>;\n\t\tread-only;\n\t};\n\n\tpartition@1c50000 {\n\t\tlabel = \"tm_key\";\n\t\treg = <0x1c50000 0x100000>;\n\t\tread-only;\n\t};\n\n\tpartition@1d50000 {\n\t\tlabel = \"nvram\";\n\t\treg = <0x1d50000 0xb0000>;\n\t\tread-only;\n\t};\n\n\tpartition@1e00000 {\n\t\tlabel = \"user_data\";\n\t\treg = <0x1e00000 0x200000>;\n\t\tread-only;\n\t};\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_factory_e000>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wan {\n\tnvmem-cells = <&macaddr_factory_e006>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_e000: macaddr@e000 {\n\t\treg = <0xe000 0x6>;\n\t};\n\n\tmacaddr_factory_e006: macaddr@e006 {\n\t\treg = <0xe006 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_elecom_wrc-1750gsv.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621_elecom_wrc-gs-2pci.dtsi\"\n\n/ {\n\tcompatible = \"elecom,wrc-1750gsv\", \"mediatek,mt7621-soc\";\n\tmodel = \"ELECOM WRC-1750GSV\";\n};\n\n&partitions {\n\tpartition@50000 {\n\t\tcompatible = \"denx,uimage\";\n\t\tlabel = \"firmware\";\n\t\treg = <0x50000 0xb00000>;\n\t};\n\n\tpartition@b50000 {\n\t\tlabel = \"tm_pattern\";\n\t\treg = <0xb50000 0x380000>;\n\t\tread-only;\n\t};\n\n\tpartition@ed0000 {\n\t\tlabel = \"tm_key\";\n\t\treg = <0xed0000 0x80000>;\n\t\tread-only;\n\t};\n\n\tpartition@f50000 {\n\t\tlabel = \"nvram\";\n\t\treg = <0xf50000 0x30000>;\n\t\tread-only;\n\t};\n\n\tpartition@f80000 {\n\t\tlabel = \"user_data\";\n\t\treg = <0xf80000 0x80000>;\n\t\tread-only;\n\t};\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_factory_e000>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wan {\n\tnvmem-cells = <&macaddr_factory_e006>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_e000: macaddr@e000 {\n\t\treg = <0xe000 0x6>;\n\t};\n\n\tmacaddr_factory_e006: macaddr@e006 {\n\t\treg = <0xe006 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_elecom_wrc-1900gst.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-only\n\n#include \"mt7621_elecom_wrc-gs-2pci.dtsi\"\n\n/ {\n\tcompatible = \"elecom,wrc-1900gst\", \"mediatek,mt7621-soc\";\n\tmodel = \"ELECOM WRC-1900GST\";\n};\n\n&partitions {\n\tpartition@50000 {\n\t\tcompatible = \"denx,uimage\";\n\t\tlabel = \"firmware\";\n\t\treg = <0x50000 0xb00000>;\n\t};\n\n\tpartition@b50000 {\n\t\tlabel = \"tm_pattern\";\n\t\treg = <0xb50000 0x380000>;\n\t\tread-only;\n\t};\n\n\tpartition@ed0000 {\n\t\tlabel = \"tm_key\";\n\t\treg = <0xed0000 0x80000>;\n\t\tread-only;\n\t};\n\n\tpartition@f50000 {\n\t\tlabel = \"art_block\";\n\t\treg = <0xf50000 0x30000>;\n\t\tread-only;\n\t};\n\n\tpartition@f80000 {\n\t\tlabel = \"user_data\";\n\t\treg = <0xf80000 0x80000>;\n\t\tread-only;\n\t};\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_factory_e000>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wan {\n\tnvmem-cells = <&macaddr_factory_e006>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_e000: macaddr@e000 {\n\t\treg = <0xe000 0x6>;\n\t};\n\n\tmacaddr_factory_e006: macaddr@e006 {\n\t\treg = <0xe006 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_elecom_wrc-2533ghbk-i.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"elecom,wrc-2533ghbk-i\", \"mediatek,mt7621-soc\";\n\tmodel = \"ELECOM WRC-2533GHBK-I\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twps {\n\t\t\tlabel = \"red:wps\";\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tled_power: power {\n\t\t\tlabel = \"white:power\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\twlan2g {\n\t\t\tlabel = \"white:wlan2g\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy0radio\";\n\t\t};\n\n\t\twlan5g {\n\t\t\tlabel = \"white:wlan5g\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy1radio\";\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\tauto {\n\t\t\tlabel = \"auto\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_0>;\n\t\t\tlinux,input-type = <EV_SW>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <40000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x9a0000>;\n\t\t\t};\n\n\t\t\tpartition@9f0000 {\n\t\t\t\tlabel = \"TM_1\";\n\t\t\t\treg = <0x9f0000 0x200000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@bf0000 {\n\t\t\t\tlabel = \"TM_2\";\n\t\t\t\treg = <0xbf0000 0x200000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@df0000 {\n\t\t\t\tlabel = \"manufacture\";\n\t\t\t\treg = <0xdf0000 0x180000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@f70000 {\n\t\t\t\tlabel = \"backup\";\n\t\t\t\treg = <0xf70000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@f80000 {\n\t\t\t\tlabel = \"storage\";\n\t\t\t\treg = <0xf80000 0x80000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&switch0 {\n\tports {\n\t\tport@0 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"wan\";\n\t\t};\n\n\t\tport@1 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan4\";\n\t\t};\n\n\t\tport@2 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan3\";\n\t\t};\n\n\t\tport@3 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan2\";\n\t\t};\n\n\t\tport@4 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan1\";\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"uart2\", \"uart3\", \"jtag\", \"wdt\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\twifi@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x0>;\n\t\tieee80211-freq-limit = <2400000 2500000>;\n\t};\n};\n\n&pcie1 {\n\twifi@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\t};\n};\n\n&xhci {\n\tstatus = \"disabled\";\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_elecom_wrc-2533gs2.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621_elecom_wrc-gs-2pci.dtsi\"\n\n/ {\n\tcompatible = \"elecom,wrc-2533gs2\", \"mediatek,mt7621-soc\";\n\tmodel = \"ELECOM WRC-2533GS2\";\n};\n\n&partitions {\n\tpartition@50000 {\n\t\tcompatible = \"denx,uimage\";\n\t\tlabel = \"firmware\";\n\t\treg = <0x50000 0xb00000>;\n\t};\n\n\tpartition@b50000 {\n\t\tlabel = \"tm_pattern\";\n\t\treg = <0xb50000 0x380000>;\n\t\tread-only;\n\t};\n\n\tpartition@ed0000 {\n\t\tlabel = \"tm_key\";\n\t\treg = <0xed0000 0x80000>;\n\t\tread-only;\n\t};\n\n\tpartition@f50000 {\n\t\tlabel = \"nvram\";\n\t\treg = <0xf50000 0x30000>;\n\t\tread-only;\n\t};\n\n\tpartition@f80000 {\n\t\tlabel = \"user_data\";\n\t\treg = <0xf80000 0x80000>;\n\t\tread-only;\n\t};\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_factory_fff4>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wan {\n\tnvmem-cells = <&macaddr_factory_fffa>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_fff4: macaddr@fff4 {\n\t\treg = <0xfff4 0x6>;\n\t};\n\n\tmacaddr_factory_fffa: macaddr@fffa {\n\t\treg = <0xfffa 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_elecom_wrc-2533gst.dts",
    "content": "#include \"mt7621_elecom_wrc-gs-2pci.dtsi\"\n\n/ {\n\tcompatible = \"elecom,wrc-2533gst\", \"mediatek,mt7621-soc\";\n\tmodel = \"ELECOM WRC-2533GST\";\n};\n\n&partitions {\n\tpartition@50000 {\n\t\tcompatible = \"denx,uimage\";\n\t\tlabel = \"firmware\";\n\t\treg = <0x50000 0xb00000>;\n\t};\n\n\tpartition@b50000 {\n\t\tlabel = \"tm_pattern\";\n\t\treg = <0xb50000 0x380000>;\n\t\tread-only;\n\t};\n\n\tpartition@ed0000 {\n\t\tlabel = \"tm_key\";\n\t\treg = <0xed0000 0x80000>;\n\t\tread-only;\n\t};\n\n\tpartition@f50000 {\n\t\tlabel = \"art_block\";\n\t\treg = <0xf50000 0x30000>;\n\t\tread-only;\n\t};\n\n\tpartition@f80000 {\n\t\tlabel = \"user_data\";\n\t\treg = <0xf80000 0x80000>;\n\t\tread-only;\n\t};\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_factory_e000>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wan {\n\tnvmem-cells = <&macaddr_factory_e006>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_e000: macaddr@e000 {\n\t\treg = <0xe000 0x6>;\n\t};\n\n\tmacaddr_factory_e006: macaddr@e006 {\n\t\treg = <0xe006 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_elecom_wrc-2533gst2.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621_elecom_wrc-gs-2pci.dtsi\"\n\n/ {\n\tcompatible = \"elecom,wrc-2533gst2\", \"mediatek,mt7621-soc\";\n\tmodel = \"ELECOM WRC-2533GST2\";\n};\n\n&partitions {\n\tpartition@50000 {\n\t\tcompatible = \"denx,uimage\";\n\t\tlabel = \"firmware\";\n\t\treg = <0x50000 0x1800000>;\n\t};\n\n\tpartition@1850000 {\n\t\tlabel = \"tm_pattern\";\n\t\treg = <0x1850000 0x400000>;\n\t\tread-only;\n\t};\n\n\tpartition@1c50000 {\n\t\tlabel = \"tm_key\";\n\t\treg = <0x1c50000 0x100000>;\n\t\tread-only;\n\t};\n\n\tpartition@1d50000 {\n\t\tlabel = \"nvram\";\n\t\treg = <0x1d50000 0xb0000>;\n\t\tread-only;\n\t};\n\n\tpartition@1e00000 {\n\t\tlabel = \"user_data\";\n\t\treg = <0x1e00000 0x200000>;\n\t\tread-only;\n\t};\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_factory_e000>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wan {\n\tnvmem-cells = <&macaddr_factory_e006>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_e000: macaddr@e000 {\n\t\treg = <0xe000 0x6>;\n\t};\n\n\tmacaddr_factory_e006: macaddr@e006 {\n\t\treg = <0xe006 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_elecom_wrc-gs-1pci.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-only\n\n#include \"mt7621_elecom_wrc-gs.dtsi\"\n\n&leds {\n\twlan2g {\n\t\tlabel = \"white:wlan2g\";\n\t\tgpios = <&gpio 3 GPIO_ACTIVE_LOW>;\n\t};\n\n\twlan5g {\n\t\tlabel = \"white:wlan5g\";\n\t\tgpios = <&gpio 4 GPIO_ACTIVE_LOW>;\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"uart3\", \"jtag\", \"wdt\", \"sdhci\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&pcie0 {\n\twifi: wifi@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x0>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_elecom_wrc-gs-2pci.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-only\n\n#include \"mt7621_elecom_wrc-gs.dtsi\"\n\n&state_default {\n\tgpio {\n\t\tgroups = \"uart3\", \"jtag\", \"wdt\", \"sdhci\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&pcie0 {\n\twifi@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x0000>;\n\t\tieee80211-freq-limit = <2400000 2500000>;\n\n\t\tled {\n\t\t\tled-sources = <0>;\n\t\t\tled-active-low;\n\t\t};\n\t};\n};\n\n&pcie1 {\n\twifi@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\n\t\tled {\n\t\t\tled-sources = <0>;\n\t\t\tled-active-low;\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_elecom_wrc-gs.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-only\n\n#include \"mt7621.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\taliases {\n\t\tled-boot = &led_power_green;\n\t\tled-failsafe = &led_power_green;\n\t\tled-running = &led_power_green;\n\t\tled-upgrade = &led_power_green;\n\t\tlabel-mac-device = &wan;\n\t};\n\n\tleds: leds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power_green: power_green {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tpower_blue {\n\t\t\tlabel = \"blue:power\";\n\t\t\tgpios = <&gpio 8 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"red:wps\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tpower_red {\n\t\t\tlabel = \"red:power\";\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\n\t\tclient {\n\t\t\tlabel = \"client\";\n\t\t\tgpios = <&gpio 41 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_0>;\n\t\t\tlinux,input-type = <EV_SW>;\n\t\t};\n\n\t\tap {\n\t\t\tlabel = \"ap\";\n\t\t\tgpios = <&gpio 42 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_0>;\n\t\t\tlinux,input-type = <EV_SW>;\n\t\t};\n\n\t\textender {\n\t\t\tlabel = \"extender\";\n\t\t\tgpios = <&gpio 43 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_0>;\n\t\t\tlinux,input-type = <EV_SW>;\n\t\t};\n\n\t\trouter {\n\t\t\tlabel = \"router\";\n\t\t\tgpios = <&gpio 44 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_0>;\n\t\t\tlinux,input-type = <EV_SW>;\n\t\t};\n\t};\n};\n\n&switch0 {\n\tports {\n\t\twan: port@0 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"wan\";\n\t\t};\n\n\t\tport@1 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan4\";\n\t\t};\n\n\t\tport@2 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan3\";\n\t\t};\n\n\t\tport@3 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan2\";\n\t\t};\n\n\t\tport@4 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan1\";\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <40000000>;\n\n\t\tpartitions: partitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&xhci {\n\tstatus = \"disabled\";\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_firefly_firewrt.dts",
    "content": "#include \"mt7621.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"firefly,firewrt\", \"mediatek,mt7621-soc\";\n\tmodel = \"Firefly FireWRT\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\n\t\tpower {\n\t\t\tlabel = \"power\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_POWER>;\n\t\t};\n\t};\n};\n\n&sdhci {\n\tstatus = \"okay\";\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0xfb0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\tmt76@0,0 {\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\t};\n};\n\n&pcie1 {\n\tmt76@0,0 {\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x0000>;\n\t\tieee80211-freq-limit = <2400000 2500000>;\n\t};\n};\n\n&ethernet {\n\tpinctrl-0 = <&mdio_pins>, <&rgmii1_pins>;\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_factory_e000>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&switch0 {\n\tports {\n\t\tport@0 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan1\";\n\t\t};\n\n\t\tport@1 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan2\";\n\t\t};\n\n\t\tport@2 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan3\";\n\t\t};\n\n\t\tport@3 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan4\";\n\t\t};\n\n\t\tport@4 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"wan\";\n\t\t\tnvmem-cells = <&macaddr_factory_e000>;\n\t\t\tnvmem-cell-names = \"mac-address\";\n\t\t\tmac-address-increment = <1>;\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"wdt\", \"rgmii2\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_e000: macaddr@e000 {\n\t\treg = <0xe000 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_gehua_ghl-r-001.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"gehua,ghl-r-001\", \"mediatek,mt7621-soc\";\n\tmodel = \"GeHua GHL-R-001\";\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tinternet {\n\t\t\tlabel = \"blue:internet\";\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tusb {\n\t\t\tlabel = \"blue:usb\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t\ttrigger-sources = <&xhci_ehci_port1>, <&ehci_port2>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n};\n\n&uartlite3 {\n\tstatus = \"okay\";\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\t\tbroken-flash-reset;\n\t\tm25p,fast-read;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x1fb0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\twifi@0,0 {\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x0000>;\n\t};\n};\n\n&pcie1 {\n\twifi@0,0 {\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\n\t\tled {\n\t\t\tled-sources = <2>;\n\t\t\tled-active-low;\n\t\t};\n\t};\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_factory_e000>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&switch0 {\n\tports {\n\t\tport@0 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan1\";\n\t\t};\n\n\t\tport@1 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan2\";\n\t\t};\n\n\t\tport@2 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan3\";\n\t\t};\n\n\t\tport@4 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"wan\";\n\t\t\tnvmem-cells = <&macaddr_factory_e000>;\n\t\t\tnvmem-cell-names = \"mac-address\";\n\t\t\tmac-address-increment = <1>;\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"jtag\", \"wdt\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_e000: macaddr@e000 {\n\t\treg = <0xe000 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_glinet_gl-mt1300.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"glinet,gl-mt1300\", \"mediatek,mt7621-soc\";\n\tmodel = \"GL.iNet GL-MT1300\";\n\n\taliases {\n\t\tled-boot = &led_run;\n\t\tled-failsafe = &led_run;\n\t\tled-running = &led_run;\n\t\tled-upgrade = &led_run;\n\t\tlabel-mac-device = &wan;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\tswitch {\n\t\t\tlabel = \"switch\";\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_0>;\n\t\t\tlinux,input-type = <EV_SW>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_run: run {\n\t\t\tlabel = \"blue:run\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tsystem {\n\t\t\tlabel = \"white:system\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&i2c {\n\tstatus = \"okay\";\n};\n\n&sdhci {\n\tstatus = \"okay\";\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <80000000>;\n\t\tm25p,fast-read;\n\t\tbroken-flash-reset;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x1fb0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\twifi@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x0>;\n\t};\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_factory_4000>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <1>;\n};\n\n&switch0 {\n\tports {\n\t\tport@2 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan1\";\n\t\t};\n\n\t\tport@3 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan2\";\n\t\t};\n\n\t\twan: port@4 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"wan\";\n\t\t\tnvmem-cells = <&macaddr_factory_4000>;\n\t\t\tnvmem-cell-names = \"mac-address\";\n\t\t};\n\t};\n};\n\n&uartlite3 {\n\tstatus = \"okay\";\n};\n\n&state_default {\n\tgpio {\n\t\tgroup = \"wdt\", \"jtag\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4000: macaddr@4000 {\n\t\treg = <0x4000 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_gnubee_gb-pc1.dts",
    "content": "#include \"mt7621.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"gnubee,gb-pc1\", \"mediatek,mt7621-soc\";\n\tmodel = \"GB-PC1\";\n\n\taliases {\n\t\tled-boot = &led_status;\n\t\tled-failsafe = &led_status;\n\t\tled-running = &led_status;\n\t\tled-upgrade = &led_status;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tsystem {\n\t\t\tlabel = \"green:system\";\n\t\t\tgpios = <&gpio 6 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_status: status {\n\t\t\tlabel = \"green:status\";\n\t\t\tgpios = <&gpio 8 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan1 {\n\t\t\tlabel = \"green:lan1\";\n\t\t\tgpios = <&gpio 24 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan2 {\n\t\t\tlabel = \"green:lan2\";\n\t\t\tgpios = <&gpio 25 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&sdhci {\n\tstatus = \"okay\";\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <80000000>;\n\t\tbroken-flash-reset;\n\t\tm25p,fast-read;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x1fb0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&ethernet {\n\tpinctrl-0 = <&mdio_pins>, <&rgmii1_pins>;\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_factory_e000>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&switch0 {\n\tports {\n\t\tport@0 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan1\";\n\t\t};\n\n\t\tport@4 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan2\";\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"jtag\", \"rgmii2\", \"uart3\", \"wdt\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_e000: macaddr@e000 {\n\t\treg = <0xe000 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_gnubee_gb-pc2.dts",
    "content": "#include \"mt7621.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"gnubee,gb-pc2\", \"mediatek,mt7621-soc\";\n\tmodel = \"GB-PC2\";\n\n\taliases {\n\t\tled-boot = &led_status;\n\t\tled-failsafe = &led_status;\n\t\tled-running = &led_status;\n\t\tled-upgrade = &led_status;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tsystem {\n\t\t\tlabel = \"green:system\";\n\t\t\tgpios = <&gpio 6 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_status: status {\n\t\t\tlabel = \"green:status\";\n\t\t\tgpios = <&gpio 8 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan1 {\n\t\t\tlabel = \"green:lan1\";\n\t\t\tgpios = <&gpio 24 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan2 {\n\t\t\tlabel = \"green:lan2\";\n\t\t\tgpios = <&gpio 25 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan3-yellow {\n\t\t\tlabel = \"yellow:lan3\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan3-green {\n\t\t\tlabel = \"green:lan3\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&sdhci {\n\tstatus = \"okay\";\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <80000000>;\n\t\tbroken-flash-reset;\n\t\tm25p,fast-read;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x1fb0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&ethernet {\n\tpinctrl-0 = <&mdio_pins>, <&rgmii1_pins>;\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_factory_e000>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&switch0 {\n\tports {\n\t\tport@0 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan1\";\n\t\t};\n\n\t\tport@4 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan2\";\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"jtag\", \"rgmii2\", \"uart3\", \"wdt\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_e000: macaddr@e000 {\n\t\treg = <0xe000 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_hilink_hlk-7621a-evb.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later\n\n#include \"mt7621.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"hilink,hlk-7621a-evb\", \"mediatek,mt7621-soc\";\n\tmodel = \"HiLink HLK-7621A evaluation board\";\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <44000000>;\n\t\tbroken-flash-reset;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x1fb0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&switch0 {\n\tports {\n\t\tport@0 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan1\";\n\t\t};\n\n\t\tport@1 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan2\";\n\t\t};\n\n\t\tport@2 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan3\";\n\t\t};\n\n\t\tport@3 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan4\";\n\t\t};\n\n\t\tport@4 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"wan\";\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie2 {\n\twifi@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"wdt\";\n\t\tfunction = \"gpio\";\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_hiwifi_hc5962.dts",
    "content": "#include \"mt7621.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"hiwifi,hc5962\", \"mediatek,mt7621-soc\";\n\tmodel = \"HiWiFi HC5962\";\n\n\taliases {\n\t\tled-boot = &led_system;\n\t\tled-failsafe = &led_system;\n\t\tled-running = &led_status;\n\t\tled-upgrade = &led_status;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200\";\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_status: status {\n\t\t\tlabel = \"white:status\";\n\t\t\tgpios = <&gpio 6 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_system: system {\n\t\t\tlabel = \"red:system\";\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_LOW>;\n\t\t\tpanic-indicator;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tubi-concat {\n\t\tcompatible = \"mtd-concat\";\n\t\tdevices = <&ubiconcat0 &ubiconcat1>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"ubi\";\n\t\t\t\treg = <0x0 0x79c0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&nand {\n\tstatus = \"okay\";\n\n\tpartitions {\n\t\tcompatible = \"fixed-partitions\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"u-boot\";\n\t\t\treg = <0x0 0x80000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@80000 {\n\t\t\tlabel = \"debug\";\n\t\t\treg = <0x80000 0x80000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tfactory: partition@100000 {\n\t\t\tlabel = \"factory\";\n\t\t\treg = <0x100000 0x40000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@140000 {\n\t\t\tlabel = \"kernel\";\n\t\t\treg = <0x140000 0x400000>;\n\t\t};\n\n\t\tubiconcat0: partition@540000 {\n\t\t\tlabel = \"ubiconcat0\";\n\t\t\treg = <0x540000 0x1c80000>;\n\t\t};\n\n\t\tpartition@21c0000 {\n\t\t\tlabel = \"bdinfo\";\n\t\t\treg = <0x21c0000 0x80000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tubiconcat1: partition@2240000 {\n\t\t\tlabel = \"ubiconcat1\";\n\t\t\treg = <0x2240000 0x5d40000>;\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\tmt76@0,0 {\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x0000>;\n\t\tieee80211-freq-limit = <2400000 2500000>;\n\t};\n};\n\n&pcie1 {\n\tmt76@0,0 {\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\t};\n};\n\n&switch0 {\n\tports {\n\t\tport@1 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan1\";\n\t\t};\n\n\t\tport@2 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan2\";\n\t\t};\n\n\t\tport@3 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan3\";\n\t\t};\n\n\t\tport@4 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"wan\";\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"uart3\", \"jtag\";\n\t\tfunction = \"gpio\";\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_humax_e10.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/mtd/partitions/uimage.h>\n\n/ {\n\tcompatible = \"humax,e10\", \"mediatek,mt7621-soc\";\n\tmodel = \"HUMAX E10\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t\tlabel-mac-device = &wan;\n\t};\n\n\tgpio-export {\n\t\tcompatible = \"gpio-export\";\n\n\t\tgpio-usb-power {\n\t\t\tgpio-export,name = \"power:usb\";\n\t\t\tgpio-export,output = <1>;\n\t\t\tgpios = <&gpio 8 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 6 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tpairing {\n\t\t\tlabel = \"green:pairing\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\twlan {\n\t\t\tlabel = \"green:wlan\";\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\twps-reset {\n\t\t\tlabel = \"wps_reset\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <50000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@70000 {\n\t\t\t\tcompatible = \"openwrt,uimage\", \"denx,uimage\";\n\t\t\t\topenwrt,offset = <FW_EDIMAX_OFFSET>;\n\t\t\t\topenwrt,partition-magic = <FW_MAGIC_EDIMAX>;\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x70000 0xf90000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\twifi@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x0000>;\n\t\tieee80211-freq-limit = <2400000 2500000>;\n\t};\n};\n\n&pcie1 {\n\twifi@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\t};\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_factory_10007>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&switch0 {\n\tports {\n\t\twan: port@0 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"wan\";\n\t\t\tnvmem-cells = <&macaddr_factory_1000d>;\n\t\t\tnvmem-cell-names = \"mac-address\";\n\t\t};\n\n\t\tport@1 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan\";\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"jtag\", \"uart2\", \"uart3\", \"wdt\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_10007: macaddr@10007 {\n\t\treg = <0x10007 0x6>;\n\t};\n\n\tmacaddr_factory_1000d: macaddr@1000d {\n\t\treg = <0x1000d 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_iodata_wn-ax1167gr.dts",
    "content": "#include \"mt7621.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"iodata,wn-ax1167gr\", \"mediatek,mt7621-soc\";\n\tmodel = \"I-O DATA WN-AX1167GR\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200\";\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 10 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\n\t\tauto {\n\t\t\tlabel = \"auto\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_0>;\n\t\t\tlinux,input-type = <EV_SW>;\n\t\t};\n\n\t\tcustom {\n\t\t\tlabel = \"custom\";\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_0>;\n\t\t\tlinux,input-type = <EV_SW>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"Bootloader\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"Config\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tiNIC_rf: partition@50000 {\n\t\t\t\tlabel = \"iNIC_rf\";\n\t\t\t\treg = <0x50000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@60000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x60000 0xf30000>;\n\t\t\t};\n\n\t\t\tpartition@f90000 {\n\t\t\t\tlabel = \"Key\";\n\t\t\t\treg = <0xf90000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@fa0000 {\n\t\t\t\tlabel = \"backup\";\n\t\t\t\treg = <0xfa0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@fb0000 {\n\t\t\t\tlabel = \"storage\";\n\t\t\t\treg = <0xfb0000 0x50000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_iNIC_rf_4>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&switch0 {\n\tports {\n\t\tport@0 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"wan\";\n\t\t\tnvmem-cells = <&macaddr_factory_4>;\n\t\t\tnvmem-cell-names = \"mac-address\";\n\t\t\tmac-address-increment = <1>;\n\t\t};\n\n\t\tport@1 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan4\";\n\t\t};\n\n\t\tport@2 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan3\";\n\t\t};\n\n\t\tport@3 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan2\";\n\t\t};\n\n\t\tport@4 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan1\";\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"uart2\", \"uart3\", \"jtag\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\tmt76@0,0 {\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&iNIC_rf 0x0>;\n\t};\n};\n\n&pcie1 {\n\tmt76@0,0 {\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x0>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\t};\n};\n\n&xhci {\n\tstatus = \"disabled\";\n};\n\n&iNIC_rf {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_iNIC_rf_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_iodata_wn-ax1167gr2.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621_iodata_wn-xx-xr.dtsi\"\n\n/ {\n\tcompatible = \"iodata,wn-ax1167gr2\", \"mediatek,mt7621-soc\";\n\tmodel = \"I-O DATA WN-AX1167GR2\";\n};\n\n&partitions {\n\tpartition@6b00000 {\n\t\tlabel = \"Backup\";\n\t\treg = <0x6b00000 0x1480000>;\n\t\tread-only;\n\t};\n};\n\n&pcie1 {\n\twifi@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x0>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_iodata_wn-ax2033gr.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621_iodata_wn-xx-xr.dtsi\"\n\n/ {\n\tcompatible = \"iodata,wn-ax2033gr\", \"mediatek,mt7621-soc\";\n\tmodel = \"I-O DATA WN-AX2033GR\";\n};\n\n&partitions {\n\tpartition@6b00000 {\n\t\tlabel = \"Backup\";\n\t\treg = <0x6b00000 0x1480000>;\n\t\tread-only;\n\t};\n};\n\n&pcie0 {\n\twifi@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0000 0 0 0 0>;\n\n\t\tmediatek,mtd-eeprom = <&factory 0x0>;\n\t\tieee80211-freq-limit = <2400000 2483000>;\n\t};\n};\n\n&pcie1 {\n\twifi@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0000 0 0 0 0>;\n\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t\tieee80211-freq-limit = <5000000 5710000>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_iodata_wn-dx1167r.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621_iodata_wn-xx-xr.dtsi\"\n\n/ {\n\tcompatible = \"iodata,wn-dx1167r\", \"mediatek,mt7621-soc\";\n\tmodel = \"I-O DATA WN-DX1167R\";\n};\n\n&partitions {\n\tpartition@6b00000 {\n\t\tlabel = \"idmkey\";\n\t\treg = <0x6b00000 0x0100000>;\n\t\tread-only;\n\t};\n\n\tpartition@6c00000 {\n\t\tlabel = \"Backup\";\n\t\treg = <0x6c00000 0x1380000>;\n\t\tread-only;\n\t};\n};\n\n&pcie1 {\n\twifi@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x0>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_iodata_wn-dx1200gr.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"iodata,wn-dx1200gr\", \"mediatek,mt7621-soc\";\n\tmodel = \"I-O DATA WN-DX1200GR\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t\tlabel-mac-device = &wan;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twps {\n\t\t\tlabel = \"blue:wps\";\n\t\t\tgpios = <&gpio 8 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_power: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 9 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 6 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\trepeater {\n\t\t\tlabel = \"repeater\";\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_0>;\n\t\t\tlinux,input-type = <EV_SW>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n};\n\n&nand {\n\tstatus = \"okay\";\n\n\tpartitions {\n\t\tcompatible = \"fixed-partitions\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"u-boot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@100000 {\n\t\t\tlabel = \"u-boot-env\";\n\t\t\treg = <0x100000 0x100000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tfactory: partition@200000 {\n\t\t\tlabel = \"factory\";\n\t\t\treg = <0x200000 0x200000>;\n\t\t};\n\n\t\tpartition@400000 {\n\t\t\tlabel = \"kernel\";\n\t\t\treg = <0x400000 0x400000>;\n\t\t};\n\n\t\tpartition@800000 {\n\t\t\tlabel = \"ubi\";\n\t\t\treg = <0x800000 0x2e00000>;\n\t\t};\n\n\t\tpartition@3600000 {\n\t\t\tlabel = \"Config\";\n\t\t\treg = <0x3600000 0x100000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@3700000 {\n\t\t\tlabel = \"firmware_2\";\n\t\t\treg = <0x3700000 0x3200000>;\n\t\t};\n\n\t\tpartition@6900000 {\n\t\t\tlabel = \"Config_2\";\n\t\t\treg = <0x6900000 0x100000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@6a00000 {\n\t\t\tlabel = \"persist\";\n\t\t\treg = <0x6a00000 0x100000>;\n\t\t};\n\n\t\tpartition@6b00000 {\n\t\t\tlabel = \"idmkey\";\n\t\t\treg = <0x6b00000 0x100000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@6c00000 {\n\t\t\tlabel = \"Backup\";\n\t\t\treg = <0x6c00000 0x1380000>;\n\t\t\tread-only;\n\t\t};\n\t};\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_factory_1e000>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&switch0 {\n\tports {\n\t\twan: port@0 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"wan\";\n\t\t\tnvmem-cells = <&macaddr_factory_1e006>;\n\t\t\tnvmem-cell-names = \"mac-address\";\n\t\t};\n\n\t\tport@1 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan4\";\n\t\t};\n\n\t\tport@2 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan3\";\n\t\t};\n\n\t\tport@3 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan2\";\n\t\t};\n\n\t\tport@4 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan1\";\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\twifi@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0000 0 0 0 0>;\n\n\t\tmediatek,mtd-eeprom = <&factory 0x0>;\n\t\tieee80211-freq-limit = <2400000 2500000>;\n\t};\n};\n\n&pcie1 {\n\twifi@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0000 0 0 0 0>;\n\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"uart2\", \"uart3\", \"wdt\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&xhci {\n\tstatus = \"disabled\";\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_1e000: macaddr@1e000 {\n\t\treg = <0x1e000 0x6>;\n\t};\n\n\tmacaddr_factory_1e006: macaddr@1e006 {\n\t\treg = <0x1e006 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_iodata_wn-dx2033gr.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621_iodata_wn-xx-xr.dtsi\"\n\n/ {\n\tcompatible = \"iodata,wn-dx2033gr\", \"mediatek,mt7621-soc\";\n\tmodel = \"I-O DATA WN-DX2033GR\";\n};\n\n&partitions {\n\tpartition@6b00000 {\n\t\tlabel = \"idmkey\";\n\t\treg = <0x6b00000 0x0100000>;\n\t\tread-only;\n\t};\n\n\tpartition@6c00000 {\n\t\tlabel = \"Backup\";\n\t\treg = <0x6c00000 0x1380000>;\n\t\tread-only;\n\t};\n};\n\n&pcie0 {\n\twifi@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x0>;\n\t\tieee80211-freq-limit = <2400000 2483000>;\n\t};\n};\n\n&pcie1 {\n\twifi@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t\tieee80211-freq-limit = <5000000 5710000>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_iodata_wn-gx300gr.dts",
    "content": "#include \"mt7621.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"iodata,wn-gx300gr\", \"mediatek,mt7621-soc\";\n\tmodel = \"I-O DATA WN-GX300GR\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200\";\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 10 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\n\t\tauto {\n\t\t\tlabel = \"auto\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_0>;\n\t\t\tlinux,input-type = <EV_SW>;\n\t\t};\n\n\t\tcustom {\n\t\t\tlabel = \"custom\";\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_0>;\n\t\t\tlinux,input-type = <EV_SW>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"Bootloader\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"Config\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tlabel = \"iNIC_rf\";\n\t\t\t\treg = <0x50000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@60000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x60000 0x770000>;\n\t\t\t};\n\n\t\t\tpartition@7d0000 {\n\t\t\t\tlabel = \"Key\";\n\t\t\t\treg = <0x7d0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@7e0000 {\n\t\t\t\tlabel = \"backup\";\n\t\t\t\treg = <0x7e0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@7f0000 {\n\t\t\t\tlabel = \"storage\";\n\t\t\t\treg = <0x7f0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&switch0 {\n\tports {\n\t\tport@0 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"wan\";\n\t\t\tnvmem-cells = <&macaddr_factory_4>;\n\t\t\tnvmem-cell-names = \"mac-address\";\n\t\t\tmac-address-increment = <1>;\n\t\t};\n\n\t\tport@1 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan4\";\n\t\t};\n\n\t\tport@2 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan3\";\n\t\t};\n\n\t\tport@3 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan2\";\n\t\t};\n\n\t\tport@4 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan1\";\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"uart2\", \"uart3\", \"jtag\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\tmt76@0,0 {\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x0>;\n\t};\n};\n\n&xhci {\n\tstatus = \"disabled\";\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_iodata_wn-xx-xr.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t\tlabel-mac-device = &wan;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twps {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&gpio 8 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_power: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 9 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 6 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\trepeater {\n\t\t\tlabel = \"repeater\";\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_0>;\n\t\t\tlinux,input-type = <EV_SW>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n};\n\n&nand {\n\tstatus = \"okay\";\n\n\tpartitions: partitions {\n\t\tcompatible = \"fixed-partitions\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"u-boot\";\n\t\t\treg = <0x0 0x0100000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@100000 {\n\t\t\tlabel = \"u-boot-env\";\n\t\t\treg = <0x0100000 0x0100000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tfactory: partition@200000 {\n\t\t\tlabel = \"factory\";\n\t\t\treg = <0x0200000 0x0100000>;\n\t\t};\n\n\t\tpartition@300000 {\n\t\t\tlabel = \"SecondBoot\";\n\t\t\treg = <0x0300000 0x0100000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@400000 {\n\t\t\tlabel = \"kernel\";\n\t\t\treg = <0x0400000 0x0400000>;\n\t\t};\n\n\t\tpartition@800000 {\n\t\t\tlabel = \"ubi\";\n\t\t\treg = <0x0800000 0x2e00000>;\n\t\t};\n\n\t\tpartition@3600000 {\n\t\t\tlabel = \"Config\";\n\t\t\treg = <0x3600000 0x0100000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@3700000 {\n\t\t\tlabel = \"firmware_2\";\n\t\t\treg = <0x3700000 0x3200000>;\n\t\t};\n\n\t\tpartition@6900000 {\n\t\t\tlabel = \"Config_2\";\n\t\t\treg = <0x6900000 0x0100000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@6a00000 {\n\t\t\tlabel = \"persist\";\n\t\t\treg = <0x6a00000 0x0100000>;\n\t\t};\n\t};\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_factory_e000>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&switch0 {\n\tports {\n\t\twan: port@0 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"wan\";\n\t\t\tnvmem-cells = <&macaddr_factory_e006>;\n\t\t\tnvmem-cell-names = \"mac-address\";\n\t\t};\n\n\t\tport@1 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan4\";\n\t\t};\n\n\t\tport@2 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan3\";\n\t\t};\n\n\t\tport@3 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan2\";\n\t\t};\n\n\t\tport@4 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan1\";\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"uart2\", \"uart3\", \"wdt\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&xhci {\n\tstatus = \"disabled\";\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_e000: macaddr@e000 {\n\t\treg = <0xe000 0x6>;\n\t};\n\n\tmacaddr_factory_e006: macaddr@e006 {\n\t\treg = <0xe006 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_iodata_wnpr2600g.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"iodata,wnpr2600g\", \"mediatek,mt7621-soc\";\n\tmodel = \"I-O DATA WNPR2600G\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\tnotification {\n\t\t\tlabel = \"green:notification\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\twlan2g {\n\t\t\tlabel = \"green:wlan2g\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy0radio\";\n\t\t};\n\n\t\twlan5g {\n\t\t\tlabel = \"green:wlan5g\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy1radio\";\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\tauto {\n\t\t\tlabel = \"auto\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_0>;\n\t\t\tlinux,input-type = <EV_SW>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <40000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x030000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x030000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x040000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x050000 0xda0000>;\n\t\t\t};\n\n\t\t\tpartition@df0000 {\n\t\t\t\tlabel = \"manufacture\";\n\t\t\t\treg = <0xdf0000 0x190000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@f80000 {\n\t\t\t\tlabel = \"storage\";\n\t\t\t\treg = <0xf80000 0x080000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&switch0 {\n\tports {\n\t\tport@0 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"wan\";\n\t\t};\n\n\t\tport@1 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan4\";\n\t\t};\n\n\t\tport@2 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan3\";\n\t\t};\n\n\t\tport@3 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan2\";\n\t\t};\n\n\t\tport@4 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan1\";\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"uart2\", \"uart3\", \"jtag\", \"wdt\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\twifi@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x0>;\n\t\tieee80211-freq-limit = <2400000 2500000>;\n\t};\n};\n\n&pcie1 {\n\twifi@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\t};\n};\n\n&xhci {\n\tstatus = \"disabled\";\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_iptime_a3002mesh.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/leds/common.h>\n\n/ {\n\tcompatible = \"iptime,a3002mesh\", \"mediatek,mt7621-soc\";\n\tmodel = \"ipTIME A3002MESH\";\n\n\taliases {\n\t\tled-boot = &led_cpu;\n\t\tled-failsafe = &led_cpu;\n\t\tled-running = &led_cpu;\n\t\tled-upgrade = &led_cpu;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_cpu: led-0 {\n\t\t\tlabel = \"amber:cpu\";\n\t\t\tcolor = <LED_COLOR_ID_AMBER>;\n\t\t\tfunction = LED_FUNCTION_CPU;\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled-1 {\n\t\t\tcolor = <LED_COLOR_ID_AMBER>;\n\t\t\tfunction = LED_FUNCTION_WLAN;\n\t\t\tfunction-enumerator = <0>;\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0radio\";\n\t\t};\n\n\t\tled-2 {\n\t\t\tcolor = <LED_COLOR_ID_AMBER>;\n\t\t\tfunction = LED_FUNCTION_WLAN;\n\t\t\tfunction-enumerator = <1>;\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1radio\";\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <50000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x20000>;\n\t\t\t\tread-only;\n\n\t\t\t\tcompatible = \"nvmem-cells\";\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\n\t\t\t\tmacaddr_uboot_1fc40: macaddr@1fc40 {\n\t\t\t\t\treg = <0x1fc40 0x6>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tlabel = \"config\";\n\t\t\t\treg = <0x20000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@30000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x40000 0xfc0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_uboot_1fc40>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <(2)>;\n};\n\n&switch0 {\n\tports {\n\t\tport@0 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"wan\";\n\t\t\tnvmem-cells = <&macaddr_uboot_1fc40>;\n\t\t\tnvmem-cell-names = \"mac-address\";\n\t\t};\n\n\t\tport@3 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan1\";\n\t\t};\n\n\t\tport@4 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan2\";\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\twifi@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x0000>;\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"jtag\", \"wdt\";\n\t\tfunction = \"gpio\";\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_iptime_a3004ns-dual.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"iptime,a3004ns-dual\", \"mediatek,mt7621-soc\";\n\tmodel = \"ipTIME A3004NS-dual\";\n\n\taliases {\n\t\tled-boot = &led_cpu;\n\t\tled-failsafe = &led_cpu;\n\t\tled-running = &led_cpu;\n\t\tled-upgrade = &led_cpu;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_cpu: cpu {\n\t\t\tlabel = \"blue:cpu\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tusb {\n\t\t\tlabel = \"blue:usb\";\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_LOW>;\n\t\t\ttrigger-sources = <&xhci_ehci_port1>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio 3 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t };\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <50000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tuboot: partition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x20000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tlabel = \"config\";\n\t\t\t\treg = <0x20000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@30000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x40000 0xfc0000>;\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t};\n\t\t};\n\t};\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_uboot_1fc20>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&switch0 {\n\tports {\n\t\tport@0 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"wan\";\n\t\t\tnvmem-cells = <&macaddr_uboot_1fc40>;\n\t\t\tnvmem-cell-names = \"mac-address\";\n\t\t};\n\n\t\tport@1 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan1\";\n\t\t};\n\n\t\tport@2 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan2\";\n\t\t};\n\n\t\tport@3 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan3\";\n\t\t};\n\n\t\tport@4 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan4\";\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\twifi@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\n\t\tled {\n\t\t\tled-sources = <2>;\n\t\t\tled-active-low;\n\t\t};\n\t};\n};\n\n&pcie1 {\n\twifi@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x0000>;\n\t\tieee80211-freq-limit = <2400000 2500000>;\n\n\t\tled {\n\t\t\tled-sources = <2>;\n\t\t\tled-active-low;\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"wdt\", \"i2c\", \"uart3\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&uboot {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_uboot_1fc20: macaddr@1fc20 {\n\t\treg = <0x1fc20 0x6>;\n\t};\n\n\tmacaddr_uboot_1fc40: macaddr@1fc40 {\n\t\treg = <0x1fc40 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_iptime_a3004t.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/leds/common.h>\n\n/ {\n\tcompatible = \"iptime,a3004t\", \"mediatek,mt7621-soc\";\n\tmodel = \"ipTIME A3004T\";\n\n\taliases {\n\t\tled-boot = &led_cpu;\n\t\tled-failsafe = &led_cpu;\n\t\tled-running = &led_cpu;\n\t\tled-upgrade = &led_cpu;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_cpu: led-0 {\n\t\t\tlabel = \"amber:cpu\";\n\t\t\tcolor = <LED_COLOR_ID_AMBER>;\n\t\t\tfunction = LED_FUNCTION_CPU;\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled-1 {\n\t\t\tcolor = <LED_COLOR_ID_AMBER>;\n\t\t\tfunction = LED_FUNCTION_WLAN;\n\t\t\tfunction-enumerator = <0>;\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0radio\";\n\t\t};\n\n\t\tled-2 {\n\t\t\tcolor = <LED_COLOR_ID_AMBER>;\n\t\t\tfunction = LED_FUNCTION_WLAN;\n\t\t\tfunction-enumerator = <1>;\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1radio\";\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n};\n\n&nand {\n\tstatus = \"okay\";\n\n\tpartitions {\n\t\tcompatible = \"fixed-partitions\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"u-boot\";\n\t\t\treg = <0x0 0x80000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@80000 {\n\t\t\tlabel = \"config\";\n\t\t\treg = <0x80000 0x20000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tfactory: partition@a0000 {\n\t\t\tlabel = \"factory\";\n\t\t\treg = <0xa0000 0x20000>;\n\t\t\tread-only;\n\n\t\t\tcompatible = \"nvmem-cells\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tmacaddr_factory_4: macaddr@4 {\n\t\t\t\treg = <0x4 0x6>;\n\t\t\t};\n\n\t\t\tmacaddr_factory_8004: macaddr@8004 {\n\t\t\t\treg = <0x8004 0x6>;\n\t\t\t};\n\t\t};\n\n\t\tpartition@140000 {\n\t\t\tlabel = \"firmware\";\n\t\t\treg = <0x140000 0x7e40000>;\n\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"kernel\";\n\t\t\t\treg = <0x0 0x400000>;\n\t\t\t};\n\n\t\t\tpartition@400000 {\n\t\t\t\tlabel = \"ubi\";\n\t\t\t\treg = <0x400000 0x7a40000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <(3)>;\n};\n\n&switch0 {\n\tports {\n\t\tport@0 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"wan\";\n\t\t\tnvmem-cells = <&macaddr_factory_4>;\n\t\t\tnvmem-cell-names = \"mac-address\";\n\t\t\tmac-address-increment = <(1)>;\n\t\t};\n\n\t\tport@1 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan4\";\n\t\t};\n\n\t\tport@2 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan3\";\n\t\t};\n\n\t\tport@3 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan2\";\n\t\t};\n\n\t\tport@4 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan1\";\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\twifi@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x0>;\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"jtag\", \"wdt\";\n\t\tfunction = \"gpio\";\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_iptime_a6004ns-m.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621_iptime_a6004ns-m.dtsi\"\n\n/ {\n\tcompatible = \"iptime,a6004ns-m\", \"mediatek,mt7621-soc\";\n\tmodel = \"ipTIME A6004NS-M\";\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_iptime_a6004ns-m.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\taliases {\n\t\tled-boot = &led_cpu;\n\t\tled-failsafe = &led_cpu;\n\t\tled-running = &led_cpu;\n\t\tled-upgrade = &led_cpu;\n\t\tlabel-mac-device = &gmac0;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tusb {\n\t\t\tlabel = \"blue:usb\";\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_LOW>;\n\t\t\ttrigger-sources = <&xhci_ehci_port1>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\n\t\twlan5g {\n\t\t\tlabel = \"blue:wlan5g\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0radio\";\n\t\t};\n\n\t\twlan2g {\n\t\t\tlabel = \"blue:wlan2g\";\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1radio\";\n\t\t};\n\n\t\tled_cpu: cpu {\n\t\t\tlabel = \"blue:cpu\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio 3 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <80000000>;\n\t\tm25p,fast-read;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tuboot: partition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x20000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tlabel = \"config\";\n\t\t\t\treg = <0x20000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@30000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x40000 0xfc0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"uart3\", \"jtag\", \"wdt\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_uboot_1fc20>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&switch0 {\n\tports {\n\t\tport@0 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"wan\";\n\t\t\tnvmem-cells = <&macaddr_uboot_1fc40>;\n\t\t\tnvmem-cell-names = \"mac-address\";\n\t\t};\n\n\t\tport@1 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan1\";\n\t\t};\n\n\t\tport@2 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan2\";\n\t\t};\n\n\t\tport@3 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan3\";\n\t\t};\n\n\t\tport@4 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan4\";\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\twifi@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x0>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\t};\n};\n\n&pcie1 {\n\twifi@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t\tieee80211-freq-limit = <2400000 2500000>;\n\t};\n};\n\n&uboot {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_uboot_1fc20: macaddr@1fc20 {\n\t\treg = <0x1fc20 0x6>;\n\t};\n\n\tmacaddr_uboot_1fc40: macaddr@1fc40 {\n\t\treg = <0x1fc40 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_iptime_a6ns-m.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621_iptime_a6004ns-m.dtsi\"\n\n/ {\n\tcompatible = \"iptime,a6ns-m\", \"mediatek,mt7621-soc\";\n\tmodel = \"ipTIME A6ns-M\";\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_iptime_a8004t.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"iptime,a8004t\", \"mediatek,mt7621-soc\";\n\tmodel = \"ipTIME A8004T\";\n\n\taliases {\n\t\tled-boot = &led_cpu;\n\t\tled-failsafe = &led_cpu;\n\t\tled-running = &led_cpu;\n\t\tled-upgrade = &led_cpu;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_cpu: cpu {\n\t\t\tlabel = \"orange:cpu\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan2g {\n\t\t\tlabel = \"orange:wlan2g\";\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0radio\";\n\t\t};\n\n\t\twlan5g {\n\t\t\tlabel = \"orange:wlan5g\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1radio\";\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio 3 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <50000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tuboot: partition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x20000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tlabel = \"config\";\n\t\t\t\treg = <0x20000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@30000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x40000 0xfc0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_uboot_1fc20>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&switch0 {\n\tports {\n\t\tport@0 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"wan\";\n\t\t\tnvmem-cells = <&macaddr_uboot_1fc40>;\n\t\t\tnvmem-cell-names = \"mac-address\";\n\t\t};\n\n\t\tport@1 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan4\";\n\t\t};\n\n\t\tport@2 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan3\";\n\t\t};\n\n\t\tport@3 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan2\";\n\t\t};\n\n\t\tport@4 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan1\";\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\twifi@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x0000>;\n\t\tieee80211-freq-limit = <2400000 2500000>;\n\t};\n};\n\n&pcie1 {\n\twifi@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"wdt\", \"jtag\", \"i2c\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&uboot {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_uboot_1fc20: macaddr@1fc20 {\n\t\treg = <0x1fc20 0x6>;\n\t};\n\n\tmacaddr_uboot_1fc40: macaddr@1fc40 {\n\t\treg = <0x1fc40 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_iptime_ax2004m.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"iptime,ax2004m\", \"mediatek,mt7621-soc\";\n\tmodel = \"ipTIME AX2004M\";\n\n\taliases {\n\t\tled-boot = &led_cpu;\n\t\tled-failsafe = &led_cpu;\n\t\tled-running = &led_cpu;\n\t\tled-upgrade = &led_cpu;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200\";\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_cpu: cpu {\n\t\t\tlabel = \"amber:cpu\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan2g {\n\t\t\tlabel = \"amber:wlan2g\";\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0radio\";\n\t\t};\n\n\t\twlan5g {\n\t\t\tlabel = \"amber:wlan5g\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1radio\";\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n};\n\n&nand {\n\tstatus = \"okay\";\n\n\tpartitions {\n\t\tcompatible = \"fixed-partitions\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"u-boot\";\n\t\t\treg = <0x0 0x80000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@80000 {\n\t\t\tlabel = \"config\";\n\t\t\treg = <0x80000 0x80000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tfactory: partition@100000 {\n\t\t\tlabel = \"factory\";\n\t\t\treg = <0x100000 0x80000>;\n\t\t\tread-only;\n\n\t\t\tcompatible = \"nvmem-cells\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tmacaddr_factory_4: macaddr@4 {\n\t\t\t\treg = <0x4 0x6>;\n\t\t\t};\n\t\t};\n\n\t\tpartition@180000 {\n\t\t\tlabel = \"firmware\";\n\t\t\treg = <0x180000 0x7680000>;\n\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"kernel\";\n\t\t\t\treg = <0x0 0x400000>;\n\t\t\t};\n\n\t\t\tpartition@400000 {\n\t\t\t\tlabel = \"ubi\";\n\t\t\t\treg = <0x400000 0x7280000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"jtag\", \"wdt\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <3>;\n};\n\n&switch0 {\n\tports {\n\t\tport@0 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"wan\";\n\t\t\tnvmem-cells = <&macaddr_factory_4>;\n\t\t\tnvmem-cell-names = \"mac-address\";\n\t\t\tmac-address-increment = <1>;\n\t\t};\n\n\t\tport@1 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan4\";\n\t\t};\n\n\t\tport@2 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan3\";\n\t\t};\n\n\t\tport@3 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan2\";\n\t\t};\n\n\t\tport@4 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan1\";\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie1 {\n\twifi@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x0>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_iptime_t5004.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/leds/common.h>\n\n/ {\n\tcompatible = \"iptime,t5004\", \"mediatek,mt7621-soc\";\n\tmodel = \"ipTIME T5004\";\n\n\taliases {\n\t\tled-boot = &led_cpu;\n\t\tled-failsafe = &led_cpu;\n\t\tled-running = &led_cpu;\n\t\tled-upgrade = &led_cpu;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_cpu: led-0 {\n\t\t\tlabel = \"blue:cpu\";\n\t\t\tcolor = <LED_COLOR_ID_BLUE>;\n\t\t\tfunction = LED_FUNCTION_CPU;\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n};\n\n&nand {\n\tstatus = \"okay\";\n\n\tpartitions {\n\t\tcompatible = \"fixed-partitions\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"u-boot\";\n\t\t\treg = <0x0 0x80000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@80000 {\n\t\t\tlabel = \"config\";\n\t\t\treg = <0x80000 0xc0000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@140000 {\n\t\t\tlabel = \"firmware\";\n\t\t\treg = <0x140000 0x7e40000>;\n\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"kernel\";\n\t\t\t\treg = <0x0 0x400000>;\n\t\t\t};\n\n\t\t\tpartition@400000 {\n\t\t\t\tlabel = \"ubi\";\n\t\t\t\treg = <0x400000 0x7a40000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"wdt\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&switch0 {\n\tports {\n\t\tport@0 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"wan\";\n\t\t};\n\n\t\tport@1 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan4\";\n\t\t};\n\n\t\tport@2 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan3\";\n\t\t};\n\n\t\tport@3 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan2\";\n\t\t};\n\n\t\tport@4 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan1\";\n\t\t};\n\t};\n};\n\n&xhci {\n\tstatus = \"disabled\";\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_jcg_jhr-ac876m.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"jcg,jhr-ac876m\", \"mediatek,mt7621-soc\";\n\tmodel = \"JCG JHR-AC876M\";\n\n\taliases {\n\t\tled-boot = &led_wps;\n\t\tled-failsafe = &led_wps;\n\t\tled-running = &led_wps;\n\t\tled-upgrade = &led_wps;\n\t\tlabel-mac-device = &wan;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tusb3 {\n\t\t\tlabel = \"blue:usb3\";\n\t\t\tgpios = <&gpio 3 GPIO_ACTIVE_LOW>;\n\t\t\ttrigger-sources = <&xhci_ehci_port1>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\n\t\tusb2 {\n\t\t\tlabel = \"blue:usb2\";\n\t\t\tgpios = <&gpio 6 GPIO_ACTIVE_LOW>;\n\t\t\ttrigger-sources = <&ehci_port2>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\n\t\tled_wps: wps {\n\t\t\tlabel = \"blue:wps\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <80000000>;\n\t\tm25p,fast-read;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0xfb0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\twifi@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x0>;\n\t\tieee80211-freq-limit = <2400000 2500000>;\n\n\t\tled {\n\t\t\tled-active-low;\n\t\t};\n\t};\n};\n\n&pcie1 {\n\twifi@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\n\t\tled {\n\t\t\tled-active-low;\n\t\t};\n\t};\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_factory_e000>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&switch0 {\n\tports {\n\t\tport@0 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan1\";\n\t\t};\n\n\t\tport@1 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan2\";\n\t\t};\n\n\t\tport@2 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan3\";\n\t\t};\n\n\t\tport@3 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan4\";\n\t\t};\n\t\twan: port@4 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"wan\";\n\t\t\tnvmem-cells = <&macaddr_factory_4>;\n\t\t\tnvmem-cell-names = \"mac-address\";\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"uart3\", \"jtag\", \"wdt\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n\n\tmacaddr_factory_e000: macaddr@e000 {\n\t\treg = <0xe000 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_jcg_q20.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"jcg,q20\", \"mediatek,mt7621-soc\";\n\tmodel = \"JCG Q20\";\n\n\taliases {\n\t\tled-boot = &led_status_red;\n\t\tled-failsafe = &led_status_red;\n\t\tled-running = &led_status_blue;\n\t\tled-upgrade = &led_status_blue;\n\t\tlabel-mac-device = &gmac0;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200\";\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_status_red: status_red {\n\t\t\tlabel = \"red:status\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tled_status_blue: status_blue {\n\t\t\tlabel = \"blue:status\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n\n\tubi-concat {\n\t\tcompatible = \"mtd-concat\";\n\t\tdevices = <&ubiconcat0 &ubiconcat1>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"ubi\";\n\t\t\t\treg = <0x0 0x5900000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&nand {\n\tstatus = \"okay\";\n\n\tpartitions {\n\t\tcompatible = \"fixed-partitions\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"Bootloader\";\n\t\t\treg = <0x0 0x80000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@80000 {\n\t\t\tlabel = \"Config\";\n\t\t\treg = <0x80000 0x80000>;\n\t\t};\n\n\t\tfactory: partition@100000 {\n\t\t\tlabel = \"Factory\";\n\t\t\treg = <0x100000 0x80000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@180000 {\n\t\t\tlabel = \"kernel\";\n\t\t\treg = <0x180000 0x400000>;\n\t\t};\n\n\t\tubiconcat0: partition@580000 {\n\t\t\tlabel = \"ubiconcat0\";\n\t\t\treg = <0x580000 0x1c00000>;\n\t\t};\n\n\t\tpartition@2180000 {\n\t\t\tlabel = \"firmware_backup\";\n\t\t\treg = <0x2180000 0x2000000>;\n\t\t};\n\n\t\tpartition@4180000 {\n\t\t\tlabel = \"rootfs_data_back\";\n\t\t\treg = <0x4180000 0x80000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@4200000 {\n\t\t\tlabel = \"nvram_config\";\n\t\t\treg = <0x4200000 0x80000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tubiconcat1: partition@4280000 {\n\t\t\tlabel = \"ubiconcat1\";\n\t\t\treg = <0x4280000 0x3d00000>;\n\t\t};\n\n\t\t/*\n\t\t * last 512 KiB are for the bad block table\n\t\t */\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie1 {\n\twifi@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x0>;\n\t};\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_factory_3fff4>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&switch0 {\n\tports {\n\t\tport@0 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"wan\";\n\t\t\tnvmem-cells = <&macaddr_factory_3fffa>;\n\t\t\tnvmem-cell-names = \"mac-address\";\n\t\t};\n\n\t\tport@1 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan1\";\n\t\t};\n\n\t\tport@4 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan2\";\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"jtag\", \"wdt\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_3fff4: macaddr@3fff4 {\n\t\treg = <0x3fff4 0x6>;\n\t};\n\n\tmacaddr_factory_3fffa: macaddr@3fffa {\n\t\treg = <0x3fffa 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_jcg_y2.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"jcg,y2\", \"mediatek,mt7621-soc\";\n\tmodel = \"JCG Y2\";\n\n\taliases {\n\t\tled-boot = &led_internet;\n\t\tled-failsafe = &led_internet;\n\t\tled-upgrade = &led_internet;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_internet: internet {\n\t\t\tlabel = \"blue:internet\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <80000000>;\n\t\tm25p,fast-read;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"bootloader\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"config\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0xfb0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\twifi@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x0>;\n\t};\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_factory_e000>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&switch0 {\n\tports {\n\t\tport@0 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan4\";\n\t\t};\n\n\t\tport@1 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan3\";\n\t\t};\n\n\t\tport@2 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan2\";\n\t\t};\n\n\t\tport@3 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan1\";\n\t\t};\n\n\t\twan: port@4 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"wan\";\n\t\t\tnvmem-cells = <&macaddr_factory_e006>;\n\t\t\tnvmem-cell-names = \"mac-address\";\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"jtag\", \"wdt\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_e000: macaddr@e000 {\n\t\treg = <0xe000 0x6>;\n\t};\n\n\tmacaddr_factory_e006: macaddr@e006 {\n\t\treg = <0xe006 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_lenovo_newifi-d1.dts",
    "content": "#include \"mt7621.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"lenovo,newifi-d1\", \"mediatek,mt7621-soc\";\n\tmodel = \"Newifi-D1\";\n\n\taliases {\n\t\tled-boot = &led_blue;\n\t\tled-failsafe = &led_blue;\n\t\tled-running = &led_blue;\n\t\tled-upgrade = &led_blue;\n\t\tlabel-mac-device = &gmac0;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200\";\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tstatus-red {\n\t\t\tlabel = \"red:status\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tstatus-green {\n\t\t\tlabel = \"green:status\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_blue: status-blue {\n\t\t\tlabel = \"blue:status\";\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n\n\tgpio_export {\n\t\tcompatible = \"gpio-export\";\n\t\t#size-cells = <0>;\n\n\t\tusb2power {\n\t\t\tgpio-export,name = \"usb2power\";\n\t\t\tgpio-export,output = <1>;\n\t\t\tgpios = <&gpio 9 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tusb3power {\n\t\t\tgpio-export,name = \"usb3power\";\n\t\t\tgpio-export,output = <1>;\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&sdhci {\n\tstatus = \"okay\";\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <45000000>;\n\t\tbroken-flash-reset;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x1fb0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\tmt76@0,0 {\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\t};\n};\n\n&pcie1 {\n\tmt76@0,0 {\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x0000>;\n\t};\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_factory_e000>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&switch0 {\n\tports {\n\t\tport@1 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan2\";\n\t\t};\n\n\t\tport@2 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan1\";\n\t\t};\n\n\t\tport@4 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"wan\";\n\t\t\tnvmem-cells = <&macaddr_factory_e006>;\n\t\t\tnvmem-cell-names = \"mac-address\";\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"jtag\", \"uart2\", \"wdt\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_e000: macaddr@e000 {\n\t\treg = <0xe000 0x6>;\n\t};\n\n\tmacaddr_factory_e006: macaddr@e006 {\n\t\treg = <0xe006 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_linksys_e5600.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"linksys,e5600\", \"mediatek,mt7621-soc\";\n\tmodel = \"Linksys E5600\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twps {\n\t\t\tlabel = \"amber:wps\";\n\t\t\tgpios = <&gpio 5 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tled_power: power {\n\t\t\tlabel = \"blue:power\";\n\t\t\tgpios = <&gpio 10 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\twan_amber {\n\t\t\tlabel = \"amber:wan\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\twan_blue {\n\t\t\tlabel = \"blue:wan\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&nand {\n\tstatus = \"okay\";\n\n\tpartitions {\n\t\tcompatible = \"fixed-partitions\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"boot\";\n\t\t\treg = <0x0 0x80000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@80000 {\n\t\t\tlabel = \"u_env\";\n\t\t\treg = <0x80000 0x40000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tfactory: partition@c0000 {\n\t\t\tlabel = \"factory\";\n\t\t\treg = <0xc0000 0x40000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@100000 {\n\t\t\tlabel = \"s_env\";\n\t\t\treg = <0x100000 0x40000>;\n\t\t};\n\n\t\tpartition@140000 {\n\t\t\tlabel = \"devinfo\";\n\t\t\treg = <0x140000 0x40000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@180000 {\n\t\t\tlabel = \"kernel\";\n\t\t\treg = <0x180000 0x400000>;\n\t\t};\n\n\t\tpartition@580000 {\n\t\t\tlabel = \"ubi\";\n\t\t\treg = <0x580000 0x1a00000>;\n\t\t};\n\n\t\tpartition@1f80000 {\n\t\t\tlabel = \"alt_firmware\";\n\t\t\treg = <0x1f80000 0x1e00000>;\n\t\t};\n\n\t\tpartition@3d80000 {\n\t\t\tlabel = \"gdata\";\n\t\t\treg = <0x3d80000 0x4200000>;\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"uart2\", \"uart3\", \"jtag\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\tmt76@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x0000>;\n\t};\n};\n\n&pcie1 {\n\tmt76@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t};\n};\n\n&switch0 {\n\tports {\n\t\tport@0 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan1\";\n\t\t};\n\n\t\tport@1 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan2\";\n\t\t};\n\n\t\tport@2 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan3\";\n\t\t};\n\n\t\tport@3 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan4\";\n\t\t};\n\n\t\tport@4 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"wan\";\n\t\t};\n\t};\n};\n\n&xhci {\n\tstatus = \"disabled\";\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_linksys_ea6350-v4.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621_linksys_ea7xxx.dtsi\"\n\n/ {\n\tcompatible = \"linksys,ea6350-v4\", \"mediatek,mt7621-soc\";\n\tmodel = \"Linksys EA6350 v4\";\n};\n\n&switch0 {\n\tports {\n\t\tport@0 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan1\";\n\t\t};\n\n\t\tport@1 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan2\";\n\t\t};\n\n\t\tport@2 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan3\";\n\t\t};\n\n\t\tport@3 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan4\";\n\t\t};\n\n\t\tport@4 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"wan\";\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_linksys_ea7300-v1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621_linksys_ea7xxx.dtsi\"\n\n/ {\n\tcompatible = \"linksys,ea7300-v1\", \"mediatek,mt7621-soc\";\n\tmodel = \"Linksys EA7300 v1\";\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_linksys_ea7300-v2.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621_linksys_ea7xxx.dtsi\"\n\n/ {\n\tcompatible = \"linksys,ea7300-v2\", \"mediatek,mt7621-soc\";\n\tmodel = \"Linksys EA7300 v2\";\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_linksys_ea7500-v2.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621_linksys_ea7xxx.dtsi\"\n\n/ {\n\tcompatible = \"linksys,ea7500-v2\", \"mediatek,mt7621-soc\";\n\tmodel = \"Linksys EA7500 v2\";\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_linksys_ea7xxx.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twan_green {\n\t\t\tlabel = \"green:wan\";\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan1_green {\n\t\t\tlabel = \"green:lan1\";\n\t\t\tgpios = <&gpio 3 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan2_green {\n\t\t\tlabel = \"green:lan2\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan3_green {\n\t\t\tlabel = \"green:lan3\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan4_green {\n\t\t\tlabel = \"green:lan4\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_power: power {\n\t\t\tlabel = \"white:power\";\n\t\t\tgpios = <&gpio 10 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&gpio 5 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&nand {\n\tstatus = \"okay\";\n\n\tmediatek,bbt;\n\tmediatek,bmt-remap-range =\n\t\t<0x180000 0x580000>,\n\t\t<0x2980000 0x2d80000>;\n\n\tpartitions {\n\t\tcompatible = \"fixed-partitions\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"boot\";\n\t\t\treg = <0x0 0x80000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@80000 {\n\t\t\tlabel = \"u_env\";\n\t\t\treg = <0x80000 0x40000>;\n\t\t};\n\n\t\tfactory: partition@c0000 {\n\t\t\tlabel = \"factory\";\n\t\t\treg = <0xc0000 0x40000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@100000 {\n\t\t\tlabel = \"s_env\";\n\t\t\treg = <0x100000 0x40000>;\n\t\t};\n\n\t\tpartition@140000 {\n\t\t\tlabel = \"devinfo\";\n\t\t\treg = <0x140000 0x40000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@180000 {\n\t\t\tlabel = \"kernel\";\n\t\t\treg = <0x180000 0x400000>;\n\t\t};\n\n\t\tpartition@580000 {\n\t\t\tlabel = \"ubi\";\n\t\t\treg = <0x580000 0x2400000>;\n\t\t};\n\n\t\tpartition@2980000 {\n\t\t\tlabel = \"alt_kernel\";\n\t\t\treg = <0x2980000 0x400000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@2d80000 {\n\t\t\tlabel = \"alt_rootfs\";\n\t\t\treg = <0x2d80000 0x2400000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@5180000 {\n\t\t\tlabel = \"sysdiag\";\n\t\t\treg = <0x5180000 0x100000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@5280000 {\n\t\t\tlabel = \"syscfg\";\n\t\t\treg = <0x5280000 0x2d00000>;\n\t\t\tread-only;\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"uart2\", \"uart3\", \"jtag\", \"wdt\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\tmt76@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x0000>;\n\t};\n};\n\n&pcie1 {\n\tmt76@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t};\n};\n\n&switch0 {\n\tports {\n\t\tport@0 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"wan\";\n\t\t};\n\n\t\tport@1 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan1\";\n\t\t};\n\n\t\tport@2 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan2\";\n\t\t};\n\n\t\tport@3 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan3\";\n\t\t};\n\n\t\tport@4 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan4\";\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_linksys_ea8100-v1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621_linksys_ea7xxx.dtsi\"\n\n/ {\n\tcompatible = \"linksys,ea8100-v1\", \"mediatek,mt7621-soc\";\n\tmodel = \"Linksys EA8100\";\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_linksys_ea8100-v2.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621_linksys_ea7xxx.dtsi\"\n\n/ {\n\tcompatible = \"linksys,ea8100-v2\", \"mediatek,mt7621-soc\";\n\tmodel = \"Linksys EA8100 v2\";\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_linksys_re6500.dts",
    "content": "#include \"mt7621.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"linksys,re6500\", \"mediatek,mt7621-soc\";\n\tmodel = \"Linksys RE6500\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twifi {\n\t\t\tlabel = \"orange:wifi\";\n\t\t\tgpios = <&gpio 0 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tled_power: power {\n\t\t\tlabel = \"white:power\";\n\t\t\tgpios = <&gpio 9 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio 10 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x7b0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"uart2\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\tmt76@0,0 {\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x0000>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\t};\n};\n\n&pcie1 {\n\tmt76@0,0 {\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t\tieee80211-freq-limit = <2400000 2500000>;\n\t};\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_factory_2e>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&switch0 {\n\tports {\n\t\tport@0 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan1\";\n\t\t};\n\n\t\tport@1 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan2\";\n\t\t};\n\n\t\tport@2 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan3\";\n\t\t};\n\n\t\tport@3 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan4\";\n\t\t};\n\t};\n};\n\n&xhci {\n\tstatus = \"disabled\";\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_2e: macaddr@2e {\n\t\treg = <0x2e 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_mediatek_ap-mt7621a-v60.dts",
    "content": "#include \"mt7621.dtsi\"\n\n/ {\n\tcompatible = \"mediatek,ap-mt7621a-v60\", \"mediatek,mt7621-soc\";\n\tmodel = \"Mediatek AP-MT7621A-V60 EVB\";\n\n\tsound {\n\t\tcompatible = \"simple-audio-card\";\n\t\tsimple-audio-card,name = \"Audio-I2S\";\n\t\tsimple-audio-card,format = \"i2s\";\n\t\tsimple-audio-card,bitclock-master = <&dailink0_master>;\n\t\tsimple-audio-card,frame-master = <&dailink0_master>;\n\t\tsimple-audio-card,widgets =\n\t\t\t\"Microphone\", \"Microphone Jack\",\n\t\t\t\"Headphone\", \"Headphone Jack\";\n\t\tsimple-audio-card,routing =\n\t\t\t\"LINPUT1\", \"Microphone Jack\",\n\t\t\t\"RINPUT1\", \"Microphone Jack\",\n\t\t\t\"Headphone Jack\", \"HP_L\",\n\t\t\t\"Headphone Jack\", \"HP_R\";\n\t\tsimple-audio-card,mclk-fs = <256>;\n\n\t\tsimple-audio-card,cpu {\n\t\t\tsound-dai = <&i2s>;\n\t\t};\n\n\t\tdailink0_master: simple-audio-card,codec {\n\t\t\tsound-dai = <&codec>;\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"uart2\", \"rgmii2\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&pinctrl {\n\ti2s_pins: i2s {\n\t\ti2s {\n\t\t\tgroups = \"uart3\";\n\t\t\tfunction = \"i2s\";\n\t\t};\n\t};\n};\n\n&i2c {\n\tstatus = \"okay\";\n\n\tcodec: wm8960@1a {\n\t\t#sound-dai-cells = <0>;\n\t\tcompatible = \"wlf,wm8960\";\n\t\treg = <0x1a>;\n\t\twlf,shared-lrclk;\n\t};\n};\n\n&gdma {\n\tstatus = \"okay\";\n};\n\n&i2s {\n\t#sound-dai-cells = <0>;\n\tstatus = \"okay\";\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&i2s_pins>;\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"mx25l6405d\",\"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x7b0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&sdhci {\n\tstatus = \"okay\";\n};\n\n&ethernet {\n\tpinctrl-0 = <&mdio_pins>, <&rgmii1_pins>;\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_factory_5>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&switch0 {\n\tports {\n\t\tport@0 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan1\";\n\t\t};\n\n\t\tport@1 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan2\";\n\t\t};\n\n\t\tport@2 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan3\";\n\t\t};\n\n\t\tport@3 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan4\";\n\t\t};\n\n\t\tport@4 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"wan\";\n\t\t\tnvmem-cells = <&macaddr_factory_5>;\n\t\t\tnvmem-cell-names = \"mac-address\";\n\t\t\tmac-address-increment = <1>;\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_5: macaddr@5 {\n\t\treg = <0x5 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_mediatek_mt7621-eval-board.dts",
    "content": "#include \"mt7621.dtsi\"\n\n/ {\n\tcompatible = \"mediatek,mt7621-eval-board\", \"mediatek,mt7621-soc\";\n\tmodel = \"Mediatek MT7621 evaluation board\";\n};\n\n&nand {\n\tstatus = \"okay\";\n\n\tpartitions {\n\t\tcompatible = \"fixed-partitions\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"uboot\";\n\t\t\treg = <0x00000 0x80000>; /* 64 KB */\n\t\t};\n\n\t\tpartition@80000 {\n\t\t\tlabel = \"uboot_env\";\n\t\t\treg = <0x80000 0x80000>; /* 64 KB */\n\t\t};\n\n\t\tpartition@100000 {\n\t\t\tlabel = \"factory\";\n\t\t\treg = <0x100000 0x40000>;\n\t\t};\n\n\t\tpartition@140000 {\n\t\t\tlabel = \"rootfs\";\n\t\t\treg = <0x140000 0xec0000>;\n\t\t};\n\t};\n};\n\n&sdhci {\n\tstatus = \"okay\";\n};\n\n&ethernet {\n\tpinctrl-0 = <&mdio_pins>, <&rgmii1_pins>;\n};\n\n&switch0 {\n\tports {\n\t\tport@0 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan1\";\n\t\t};\n\n\t\tport@1 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan2\";\n\t\t};\n\n\t\tport@2 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan3\";\n\t\t};\n\n\t\tport@3 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan4\";\n\t\t};\n\n\t\tport@4 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"wan\";\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"uart2\", \"uart3\", \"rgmii2\", \"sdhci\";\n\t\tfunction = \"gpio\";\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_mikrotik.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621.dtsi\"\n\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/gpio/gpio.h>\n\n/ {\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200\";\n\t};\n\n\tkeys: keys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <33000000>;\n\n\t\tpartitions: partitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"RouterBoot\";\n\t\t\t\treg = <0x0 0x40000>;\n\t\t\t\tcompatible = \"mikrotik,routerboot-partitions\";\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\n\t\t\t\tpartition@0 {\n\t\t\t\t\tlabel = \"bootloader1\";\n\t\t\t\t\treg = <0x0 0x0>;\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\thard_config {\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\tpartition@10000 {\n\t\t\t\t\tlabel = \"bootloader2\";\n\t\t\t\t\treg = <0x10000 0xf000>;\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\n\t\t\t\tsoft_config {\n\t\t\t\t};\n\n\t\t\t\tpartition@30000 {\n\t\t\t\t\tlabel = \"bios\";\n\t\t\t\t\treg = <0x30000 0x1000>;\n\t\t\t\t\tread-only;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_mikrotik_routerboard-750gr3.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621_mikrotik_routerboard-7xx.dtsi\"\n\n/ {\n\tcompatible = \"mikrotik,routerboard-750gr3\", \"mediatek,mt7621-soc\";\n\tmodel = \"MikroTik RouterBOARD 750Gr3\";\n\n\taliases {\n\t\tled-boot = &led_usr;\n\t\tled-failsafe = &led_usr;\n\t\tled-running = &led_usr;\n\t\tled-upgrade = &led_usr;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tpwr {\n\t\t\tlabel = \"blue:pwr\";\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\tled_usr: usr {\n\t\t\tlabel = \"green:usr\";\n\t\t\tgpios = <&gpio 0 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"uart2\", \"jtag\", \"wdt\";\n\t\tfunction = \"gpio\";\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_mikrotik_routerboard-760igs.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621_mikrotik_routerboard-7xx.dtsi\"\n\n/ {\n\tcompatible = \"mikrotik,routerboard-760igs\", \"mediatek,mt7621-soc\";\n\tmodel = \"MikroTik RouterBOARD 760iGS\";\n\n\taliases {\n\t\tled-boot = &led_pwr;\n\t\tled-failsafe = &led_pwr;\n\t\tled-running = &led_pwr;\n\t\tled-upgrade = &led_pwr;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_pwr: pwr {\n\t\t\tlabel = \"blue:pwr\";\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\tsfp {\n\t\t\tlabel = \"blue:sfp\";\n\t\t\tgpios = <&gpio 9 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n\n\tsfp1: sfp1 {\n\t\tcompatible = \"sff,sfp\";\n\t\ti2c-bus = <&i2c>;\n\t\tlos-gpios = <&gpio 6 GPIO_ACTIVE_HIGH>;\n\t\tmod-def0-gpios = <&gpio 8 GPIO_ACTIVE_LOW>;\n\t\ttx-disable-gpios = <&gpio 10 GPIO_ACTIVE_HIGH>;\n\t\tmaximum-power-milliwatt = <1000>;\n\t};\n};\n\n&mdio {\n\tephy7: ethernet-phy@7 {\n\t\treg = <7>;\n\t\tsfp = <&sfp1>;\n\t};\n};\n\n&gmac1 {\n\tstatus = \"okay\";\n\n\tlabel = \"sfp\";\n\tphy-handle = <&ephy7>;\n};\n\n&i2c {\n\tstatus = \"okay\";\n};\n\n&state_default {\n\tgpio {\n\t\t/* gpio7 (uart3 group) goes high when\n\t\t * port5 (PoE out) is cabled to a\n\t\t * Mikrotik PoE-in capable port,\n\t\t * such as port1 on another rb760iGS */\n\t\tgroups = \"uart2\", \"uart3\", \"jtag\", \"wdt\";\n\t\tfunction = \"gpio\";\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_mikrotik_routerboard-7xx.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621_mikrotik.dtsi\"\n\n/ {\n\tgpio_export {\n\t\tcompatible = \"gpio-export\";\n\t\t#size-cells = <0>;\n\n\t\tbuzzer {\n\t\t\t/* Beeper requires PWM for frequency selection */\n\t\t\tgpio-export,name = \"buzzer\";\n\t\t\tgpio-export,output = <0>;\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tusb_power {\n\t\t\tgpio-export,name = \"usb_power\";\n\t\t\tgpio-export,output = <1>;\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&keys {\n\tmode {\n\t\tlabel = \"mode\";\n\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\tlinux,code = <BTN_0>;\n\t};\n};\n\n&partitions {\n\tpartition@40000 {\n\t\tcompatible = \"mikrotik,minor\";\n\t\tlabel = \"firmware\";\n\t\treg = <0x040000 0xfc0000>;\n\t};\n};\n\n&switch0 {\n\tports {\n\t\tport@0 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"wan\";\n\t\t};\n\n\t\tport@1 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan2\";\n\t\t};\n\n\t\tport@2 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan3\";\n\t\t};\n\n\t\tport@3 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan4\";\n\t\t};\n\n\t\tport@4 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan5\";\n\t\t};\n\t};\n};\n\n&sdhci {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_mikrotik_routerboard-m11g.dts",
    "content": "#include \"mt7621_mikrotik.dtsi\"\n\n/ {\n\tcompatible = \"mikrotik,routerboard-m11g\", \"mediatek,mt7621-soc\";\n\tmodel = \"MikroTik RouterBOARD M11G\";\n\n\taliases {\n\t\tled-boot = &led_usr;\n\t\tled-failsafe = &led_usr;\n\t\tled-running = &led_usr;\n\t\tled-upgrade = &led_usr;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_usr: usr {\n\t\t\tlabel = \"green:usr\";\n\t\t\tgpios = <&gpio 0 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\trssi0 {\n\t\t\tlabel = \"green:rssi0\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\trssi1 {\n\t\t\tlabel = \"green:rssi1\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\trssi2 {\n\t\t\tlabel = \"green:rssi2\";\n\t\t\tgpios = <&gpio 24 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\trssi3 {\n\t\t\tlabel = \"green:rssi3\";\n\t\t\tgpios = <&gpio 25 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\trssi4 {\n\t\t\tlabel = \"green:rssi4\";\n\t\t\tgpios = <&gpio 26 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tpcie0_vcc_reg {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"pcie0_vcc\";\n\n\t\tregulator-min-microvolt = <3300000>;\n\t\tregulator-max-microvolt = <3300000>;\n\t\tgpio = <&gpio 9 GPIO_ACTIVE_HIGH>;\n\t\tenable-active-high;\n\t\tregulator-boot-on;\n\t\tregulator-always-on;\n\t};\n};\n\n&partitions {\n\tpartition@40000 {\n\t\tcompatible = \"mikrotik,minor\";\n\t\tlabel = \"firmware\";\n\t\treg = <0x040000 0xfc0000>;\n\t};\n};\n\n&ethernet {\n\tpinctrl-0 = <&mdio_pins>, <&rgmii1_pins>;\n};\n\n&switch0 {\n\tports {\n\t\tport@0 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan\";\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"uart2\", \"wdt\", \"rgmii2\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&i2c {\n\tstatus = \"okay\";\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_mikrotik_routerboard-m33g.dts",
    "content": "#include \"mt7621_mikrotik.dtsi\"\n\n/ {\n\tcompatible = \"mikrotik,routerboard-m33g\", \"mediatek,mt7621-soc\";\n\tmodel = \"MikroTik RouterBOARD M33G\";\n\n\taliases {\n\t\tled-boot = &led_usr;\n\t\tled-failsafe = &led_usr;\n\t\tled-running = &led_usr;\n\t\tled-upgrade = &led_usr;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_usr: usr {\n\t\t\tlabel = \"green:usr\";\n\t\t\tgpios = <&gpio 0 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n\n\tpcie0_vcc_reg {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"pcie0_vcc\";\n\n\t\tregulator-min-microvolt = <3300000>;\n\t\tregulator-max-microvolt = <3300000>;\n\t\tgpio = <&gpio 9 GPIO_ACTIVE_HIGH>;\n\t\tenable-active-high;\n\t\tregulator-boot-on;\n\t\tregulator-always-on;\n\t};\n\n\tpcie1_vcc_reg {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"pcie1_vcc\";\n\n\t\tregulator-min-microvolt = <3300000>;\n\t\tregulator-max-microvolt = <3300000>;\n\t\tgpio = <&gpio 10 GPIO_ACTIVE_HIGH>;\n\t\tenable-active-high;\n\t\tregulator-boot-on;\n\t\tregulator-always-on;\n\t};\n\n\tpcie2_vcc_reg {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"pcie2_vcc\";\n\n\t\tregulator-min-microvolt = <3300000>;\n\t\tregulator-max-microvolt = <3300000>;\n\t\tgpio = <&gpio 11 GPIO_ACTIVE_HIGH>;\n\t\tenable-active-high;\n\t\tregulator-boot-on;\n\t\tregulator-always-on;\n\t};\n\n\tusb_vcc_reg {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"usb_vcc\";\n\n\t\tregulator-min-microvolt = <5000000>;\n\t\tregulator-max-microvolt = <5000000>;\n\t\tgpio = <&gpio 12 GPIO_ACTIVE_HIGH>;\n\t\tenable-active-high;\n\t\tregulator-always-on;\n\t};\n};\n\n&spi0 {\n\tflash@1 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <1>;\n\t\tspi-max-frequency = <33000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\t// Region <0x0 0x40000> seems reserved by OEM\n\n\t\t\tpartition@40000 {\n\t\t\t\tcompatible = \"mikrotik,minor\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x040000 0xfc0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&switch0 {\n\tports {\n\t\tport@0 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"wan\";\n\t\t};\n\n\t\tport@1 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan1\";\n\t\t};\n\n\t\tport@2 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan2\";\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"uart2\", \"wdt\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&sdhci {\n\tstatus = \"okay\";\n};\n\n&i2c {\n\tstatus = \"okay\";\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&uartlite3 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_mqmaker_witi.dts",
    "content": "#include \"mt7621.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"mqmaker,witi\", \"mediatek,mt7621-soc\";\n\tmodel = \"MQmaker WiTi\";\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n};\n\n&i2c {\n\tstatus = \"okay\";\n\n\trtc@51 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"nxp,pcf8563\";\n\t\treg = <0x51>;\n\t};\n};\n\n&sdhci {\n\tstatus = \"okay\";\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0xfb0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\tmt76@0,0 {\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\t\tnvmem-cells = <&macaddr_factory_e000>;\n\t\tnvmem-cell-names = \"mac-address\";\n\t};\n};\n\n&pcie1 {\n\tmt76@0,0 {\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x0000>;\n\t\tieee80211-freq-limit = <2400000 2500000>;\n\t\tnvmem-cells = <&macaddr_factory_e000>;\n\t\tnvmem-cell-names = \"mac-address\";\n\t};\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_factory_e000>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&switch0 {\n\tports {\n\t\tport@0 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan1\";\n\t\t};\n\n\t\tport@1 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan2\";\n\t\t};\n\n\t\tport@2 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan3\";\n\t\t};\n\n\t\tport@3 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan4\";\n\t\t};\n\n\t\tport@4 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"wan\";\n\t\t\tnvmem-cells = <&macaddr_factory_e000>;\n\t\t\tnvmem-cell-names = \"mac-address\";\n\t\t\tmac-address-increment = <1>;\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"wdt\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_e000: macaddr@e000 {\n\t\treg = <0xe000 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_mtc_wr1201.dts",
    "content": "#include \"mt7621.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"mtc,wr1201\", \"mediatek,mt7621-soc\";\n\tmodel = \"MTC Wireless Router WR1201\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t\tlabel-mac-device = &gmac0;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 24 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tusb {\n\t\t\tlabel = \"green:usb\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_LOW>;\n\t\t\ttrigger-sources = <&xhci_ehci_port1>, <&ehci_port2>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\n\t\teth_link {\n\t\t\tlabel = \"green:eth_link\";\n\t\t\tgpios = <&gpio 26 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 25 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"Bootloader\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"Config\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0xfa0000>;\n\t\t\t};\n\n\t\t\tpartition@ff0000 {\n\t\t\t\tlabel = \"Second_Config\";\n\t\t\t\treg = <0xff0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&ethernet {\n\tpinctrl-0 = <&mdio_pins>, <&rgmii1_pins>;\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&switch0 {\n\tports {\n\t\tport@0 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan4\";\n\t\t};\n\n\t\tport@1 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan3\";\n\t\t};\n\n\t\tport@2 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan2\";\n\t\t};\n\n\t\tport@3 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan1\";\n\t\t};\n\n\t\tport@4 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"wan\";\n\t\t\tnvmem-cells = <&macaddr_factory_4>;\n\t\t\tnvmem-cell-names = \"mac-address\";\n\t\t\tmac-address-increment = <1>;\n\t\t};\n\t};\n};\n\n&sdhci {\n\tstatus = \"okay\";\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\twifi@0,0 {\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\n\t\tled {\n\t\t\tled-sources = <2>;\n\t\t\tled-active-low;\n\t\t};\n\t};\n};\n\n&pcie1 {\n\twifi@0,0 {\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x0000>;\n\t\tieee80211-freq-limit = <2400000 2500000>;\n\n\t\tled {\n\t\t\tled-sources = <2>;\n\t\t\tled-active-low;\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"rgmii2\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_netgear_ex6150.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"netgear,ex6150\", \"mediatek,mt7621-soc\";\n\tmodel = \"Netgear EX6150\";\n\n\taliases {\n\t\tled-boot = &power_green;\n\t\tled-failsafe = &power_amber;\n\t\tled-running = &power_green;\n\t\tled-upgrade = &power_amber;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tpower_amber: power_amber {\n\t\t\tlabel = \"amber:power\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tpower_green: power_green {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\trightarrow {\n\t\t\tlabel = \"blue:rightarrow\";\n\t\t\tgpios = <&gpio 28 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tleftarrow {\n\t\t\tlabel = \"blue:leftarrow\";\n\t\t\tgpios = <&gpio 31 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\trouter_green {\n\t\t\tlabel = \"green:router\";\n\t\t\tgpios = <&gpio 29 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\n\t\trouter_red {\n\t\t\tlabel = \"red:router\";\n\t\t\tgpios = <&gpio 30 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tclient_green {\n\t\t\tlabel = \"green:client\";\n\t\t\tgpios = <&gpio 33 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\tclient_red {\n\t\t\tlabel = \"red:client\";\n\t\t\tgpios = <&gpio 32 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio 47 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 46 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\ttoggle {\n\t\t\tlabel = \"AP/Extender toggle\";\n\t\t\tgpios = <&gpio 48 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_0>;\n\t\t\tlinux,input-type = <EV_SW>;\n\t\t\t/* Active when switch is set to \"Access Point\" */\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"config\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0xe80000>;\n\t\t\t};\n\n\t\t\tpartition@ed0000 {\n\t\t\t\tlabel = \"ML1\";\n\t\t\t\treg = <0xed0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@ef0000 {\n\t\t\t\tlabel = \"ML2\";\n\t\t\t\treg = <0xef0000 0x20000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@f10000 {\n\t\t\t\tlabel = \"ML3\";\n\t\t\t\treg = <0xf10000 0x20000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@f30000 {\n\t\t\t\tlabel = \"ML4\";\n\t\t\t\treg = <0xf30000 0x20000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@f50000 {\n\t\t\t\tlabel = \"ML5\";\n\t\t\t\treg = <0xf50000 0x20000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@f70000 {\n\t\t\t\tlabel = \"ML6\";\n\t\t\t\treg = <0xf70000 0x20000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@f90000 {\n\t\t\t\tlabel = \"ML7\";\n\t\t\t\treg = <0xf90000 0x20000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@fb0000 {\n\t\t\t\tlabel = \"T_Meter1\";\n\t\t\t\treg = <0xfb0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@fc0000 {\n\t\t\t\tlabel = \"T_Meter2\";\n\t\t\t\treg = <0xfc0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@fd0000 {\n\t\t\t\tlabel = \"POT\";\n\t\t\t\treg = <0xfd0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@fe0000 {\n\t\t\t\tlabel = \"board_data\";\n\t\t\t\treg = <0xfe0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@ff0000 {\n\t\t\t\tlabel = \"nvram\";\n\t\t\t\treg = <0xff0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n\n\treset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>,\n\t\t      <&gpio 8 GPIO_ACTIVE_LOW>;\n};\n\n&pcie0 {\n\twifi@0,0 {\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\t};\n};\n\n&pcie1 {\n\twifi@0,0 {\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x0000>;\n\t\tieee80211-freq-limit = <2400000 2500000>;\n\t};\n};\n\n&ethernet {\n\tpinctrl-0 = <&mdio_pins>, <&rgmii1_pins>;\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&switch0 {\n\tports {\n\t\tport@0 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan\";\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"sdhci\", \"rgmii2\", \"jtag\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_netgear_r6220.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-only\n\n#include \"mt7621_netgear_sercomm_ayx.dtsi\"\n\n/ {\n\tcompatible = \"netgear,r6220\", \"mediatek,mt7621-soc\";\n\tmodel = \"Netgear R6220\";\n\n\taliases {\n\t\tlabel-mac-device = &gmac0;\n\t};\n};\n\n&nand {\n\tstatus = \"okay\";\n\n\tpartitions {\n\t\tcompatible = \"fixed-partitions\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"u-boot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@100000 {\n\t\t\tlabel = \"SC PID\";\n\t\t\treg = <0x100000 0x100000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@200000 {\n\t\t\tlabel = \"kernel\";\n\t\t\treg = <0x200000 0x400000>;\n\t\t};\n\n\t\tpartition@600000 {\n\t\t\tlabel = \"ubi\";\n\t\t\treg = <0x600000 0x1c00000>;\n\t\t};\n\n\t\tfactory: partition@2e00000 {\n\t\t\tlabel = \"factory\";\n\t\t\treg = <0x2e00000 0x100000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@4200000 {\n\t\t\tlabel = \"reserved\";\n\t\t\treg = <0x4200000 0x3c00000>;\n\t\t\tread-only;\n\t\t};\n\t};\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wan {\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <1>;\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_netgear_r6260.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-only\n\n#include \"mt7621_netgear_sercomm_chj.dtsi\"\n\n/ {\n\tcompatible = \"netgear,r6260\", \"mediatek,mt7621-soc\";\n\tmodel = \"Netgear R6260\";\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_netgear_r6350.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-only\n\n#include \"mt7621_netgear_sercomm_chj.dtsi\"\n\n/ {\n\tcompatible = \"netgear,r6350\", \"mediatek,mt7621-soc\";\n\tmodel = \"Netgear R6350\";\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_netgear_r6700-v2.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-only\n\n#include \"mt7621_netgear_sercomm_bzv.dtsi\"\n\n/ {\n\tcompatible = \"netgear,r6700-v2\", \"mediatek,mt7621-soc\";\n\tmodel = \"Netgear R6700 v2\";\n};\n\n&leds {\n\tguest_wifi {\n\t\tgpios = <&gpio_expander 6 GPIO_ACTIVE_LOW>;\n\t\tlabel = \"white:guest_wifi\";\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_netgear_r6800.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-only\n\n#include \"mt7621_netgear_sercomm_bzv.dtsi\"\n\n/ {\n\tcompatible = \"netgear,r6800\", \"mediatek,mt7621-soc\";\n\tmodel = \"Netgear R6800\";\n};\n\n&leds {\n\tusb2 {\n\t\tgpios = <&gpio_expander 6 GPIO_ACTIVE_LOW>;\n\t\tlabel = \"white:usb2\";\n\t\tlinux,default-trigger = \"usbport\";\n\t\ttrigger-sources = <&ehci_port2>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_netgear_r6850.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-only\n\n#include \"mt7621_netgear_sercomm_chj.dtsi\"\n\n/ {\n\tcompatible = \"netgear,r6850\", \"mediatek,mt7621-soc\";\n\tmodel = \"Netgear R6850\";\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_netgear_r6900-v2.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-only\n\n#include \"mt7621_netgear_sercomm_bzv.dtsi\"\n\n/ {\n\tcompatible = \"netgear,r6900-v2\", \"mediatek,mt7621-soc\";\n\tmodel = \"Netgear R6900 v2\";\n};\n\n&leds {\n\tguest_wifi {\n\t\tgpios = <&gpio_expander 6 GPIO_ACTIVE_LOW>;\n\t\tlabel = \"white:guest_wifi\";\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_netgear_r7200.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-only\n\n#include \"mt7621_netgear_sercomm_bzv.dtsi\"\n\n/ {\n\tcompatible = \"netgear,r7200\", \"mediatek,mt7621-soc\";\n\tmodel = \"Netgear R7200\";\n};\n\n&leds {\n\tguest_wifi {\n\t\tgpios = <&gpio_expander 6 GPIO_ACTIVE_LOW>;\n\t\tlabel = \"white:guest_wifi\";\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_netgear_r7450.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-only\n\n#include \"mt7621_netgear_sercomm_bzv.dtsi\"\n\n/ {\n\tcompatible = \"netgear,r7450\", \"mediatek,mt7621-soc\";\n\tmodel = \"Netgear R7450\";\n};\n\n&leds {\n\tguest_wifi {\n\t\tgpios = <&gpio_expander 6 GPIO_ACTIVE_LOW>;\n\t\tlabel = \"white:guest_wifi\";\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_netgear_sercomm_ayx.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-only\n\n#include \"mt7621.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"mediatek,mt7621-soc\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\n\t\twifi {\n\t\t\tlabel = \"wifi\";\n\t\t\tgpios = <&gpio 8 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RFKILL>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tusb {\n\t\t\tlabel = \"green:usb\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t\ttrigger-sources = <&xhci_ehci_port1>, <&ehci_port2>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\n\t\tinternet {\n\t\t\tlabel = \"green:wan\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twifi {\n\t\t\tlabel = \"green:wifi\";\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\treg_usb_vbus: regulator {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"usb_vbus\";\n\t\tregulator-min-microvolt = <5000000>;\n\t\tregulator-max-microvolt = <5000000>;\n\t\tgpio = <&gpio 10 GPIO_ACTIVE_HIGH>;\n\t\tenable-active-high;\n\t};\n};\n\n&xhci {\n\tvbus-supply = <&reg_usb_vbus>;\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\twifi@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\t};\n};\n\n&pcie1 {\n\twifi@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x0>;\n\t\tieee80211-freq-limit = <2400000 2500000>;\n\t};\n};\n\n&switch0 {\n\tports {\n\t\tport@0 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan4\";\n\t\t};\n\n\t\tport@1 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan3\";\n\t\t};\n\n\t\tport@2 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan2\";\n\t\t};\n\n\t\tport@3 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan1\";\n\t\t};\n\n\t\twan: port@4 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"wan\";\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"uart3\", \"uart2\", \"jtag\", \"wdt\";\n\t\tfunction = \"gpio\";\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_netgear_sercomm_bzv.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-only\n\n#include \"mt7621.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"mediatek,mt7621-soc\";\n\n\taliases {\n\t\tlabel-mac-device = &gmac0;\n\t\tled-boot = &led_power_white;\n\t\tled-failsafe = &led_power_orange;\n\t\tled-running = &led_power_white;\n\t\tled-upgrade = &led_power_orange;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\n\t\trfkill {\n\t\t\tlabel = \"rfkill\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RFKILL>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tleds: leds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power_orange: power_orange {\n\t\t\tgpios = <&gpio_expander 0 GPIO_ACTIVE_LOW>;\n\t\t\tlabel = \"orange:power\";\n\t\t};\n\n\t\tled_power_white: power_white {\n\t\t\tgpios = <&gpio_expander 1 GPIO_ACTIVE_LOW>;\n\t\t\tlabel = \"white:power\";\n\t\t};\n\n\t\twan_orange {\n\t\t\tgpios = <&gpio_expander 2 GPIO_ACTIVE_LOW>;\n\t\t\tlabel = \"orange:wan\";\n\t\t};\n\n\t\twan_white {\n\t\t\tgpios = <&gpio_expander 3 GPIO_ACTIVE_LOW>;\n\t\t\tlabel = \"white:wan\";\n\t\t};\n\n\t\twlan2g {\n\t\t\tgpios = <&gpio_expander 4 GPIO_ACTIVE_LOW>;\n\t\t\tlabel = \"white:wlan2g\";\n\t\t\tlinux,default-trigger = \"phy0radio\";\n\t\t};\n\n\t\twlan5g {\n\t\t\tgpios = <&gpio_expander 5 GPIO_ACTIVE_LOW>;\n\t\t\tlabel = \"white:wlan5g\";\n\t\t\tlinux,default-trigger = \"phy1radio\";\n\t\t};\n\n\t\tusb3 {\n\t\t\tgpios = <&gpio_expander 7 GPIO_ACTIVE_LOW>;\n\t\t\tlabel = \"white:usb3\";\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t\ttrigger-sources = <&xhci_ehci_port1>;\n\t\t};\n\n\t\tlan1_orange {\n\t\t\tgpios = <&gpio_expander 8 GPIO_ACTIVE_LOW>;\n\t\t\tlabel = \"orange:lan1\";\n\t\t};\n\n\t\tlan1_white {\n\t\t\tgpios = <&gpio_expander 9 GPIO_ACTIVE_LOW>;\n\t\t\tlabel = \"white:lan1\";\n\t\t};\n\n\t\tlan2_orange {\n\t\t\tgpios = <&gpio_expander 10 GPIO_ACTIVE_LOW>;\n\t\t\tlabel = \"orange:lan2\";\n\t\t};\n\n\t\tlan2_white {\n\t\t\tgpios = <&gpio_expander 11 GPIO_ACTIVE_LOW>;\n\t\t\tlabel = \"white:lan2\";\n\t\t};\n\n\t\tlan3_orange {\n\t\t\tgpios = <&gpio_expander 12 GPIO_ACTIVE_LOW>;\n\t\t\tlabel = \"orange:lan3\";\n\t\t};\n\n\t\tlan3_white {\n\t\t\tgpios = <&gpio_expander 13 GPIO_ACTIVE_LOW>;\n\t\t\tlabel = \"white:lan3\";\n\t\t};\n\n\t\tlan4_orange {\n\t\t\tgpios = <&gpio_expander 14 GPIO_ACTIVE_LOW>;\n\t\t\tlabel = \"orange:lan4\";\n\t\t};\n\n\t\tlan4_white {\n\t\t\tgpios = <&gpio_expander 15 GPIO_ACTIVE_LOW>;\n\t\t\tlabel = \"white:lan4\";\n\t\t};\n\n\t\twps {\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\t\t\tlabel = \"white:wps\";\n\t\t};\n\n\t\twlan {\n\t\t\tgpios = <&gpio 5 GPIO_ACTIVE_LOW>;\n\t\t\tlabel = \"white:wlan\";\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"uart3\", \"uart2\", \"jtag\", \"wdt\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\twifi@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x0>;\n\t\tieee80211-freq-limit = <2400000 2500000>;\n\t};\n};\n\n&pcie1 {\n\twifi@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\t};\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&switch0 {\n\tports {\n\t\tport@0 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan4\";\n\t\t};\n\n\t\tport@1 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan3\";\n\t\t};\n\n\t\tport@2 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan2\";\n\t\t};\n\n\t\tport@3 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan1\";\n\t\t};\n\n\t\tport@4 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"wan\";\n\t\t\tnvmem-cells = <&macaddr_factory_4>;\n\t\t\tnvmem-cell-names = \"mac-address\";\n\t\t\tmac-address-increment = <2>;\n\t\t};\n\t};\n};\n\n&i2c {\n\tstatus = \"okay\";\n\n\tgpio_expander: i2c0gpio-expander@20{\n\t\t#gpio-cells = <2>;\n\t\t#interrupt-cells = <2>;\n\t\tcompatible = \"semtech,sx1503q\";\n\t\treg = <0x20>;\n\n\t\tgpio-controller;\n\t};\n};\n\n&nand {\n\tstatus = \"okay\";\n\n\tpartitions {\n\t\tcompatible = \"fixed-partitions\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"u-boot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@100000 {\n\t\t\tlabel = \"SC PART_MAP\";\n\t\t\treg = <0x100000 0x100000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@200000 {\n\t\t\tlabel = \"kernel\";\n\t\t\treg = <0x200000 0x400000>;\n\t\t};\n\n\t\tpartition@600000 {\n\t\t\tlabel = \"ubi\";\n\t\t\treg = <0x600000 0x2800000>;\n\t\t};\n\n\t\tpartition@2e00000 {\n\t\t\tlabel = \"reserved0\";\n\t\t\treg = <0x2e00000 0x1800000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tfactory: partition@4600000 {\n\t\t\tlabel = \"factory\";\n\t\t\treg = <0x4600000 0x200000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@4800000 {\n\t\t\tlabel = \"reserved1\";\n\t\t\treg = <0x4800000 0x3800000>;\n\t\t\tread-only;\n\t\t};\n\t};\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_netgear_sercomm_chj.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-only\n\n#include \"mt7621.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"mediatek,mt7621-soc\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t\tlabel-mac-device = &gmac0;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tusb {\n\t\t\tlabel = \"green:usb\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t\ttrigger-sources = <&xhci_ehci_port1>, <&ehci_port2>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\n\t\tinternet {\n\t\t\tlabel = \"green:wan\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twifi {\n\t\t\tlabel = \"green:wifi\";\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\treg_usb_vbus: regulator {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"usb_vbus\";\n\t\tregulator-min-microvolt = <5000000>;\n\t\tregulator-max-microvolt = <5000000>;\n\t\tgpio = <&gpio 10 GPIO_ACTIVE_HIGH>;\n\t\tenable-active-high;\n\t};\n};\n\n&xhci {\n\tvbus-supply = <&reg_usb_vbus>;\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\twifi@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\t};\n};\n\n&pcie1 {\n\twifi@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x0>;\n\t\tieee80211-freq-limit = <2400000 2500000>;\n\t};\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&switch0 {\n\tports {\n\t\tport@0 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan4\";\n\t\t};\n\n\t\tport@1 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan3\";\n\t\t};\n\n\t\tport@2 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan2\";\n\t\t};\n\n\t\tport@3 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan1\";\n\t\t};\n\n\t\tport@4 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"wan\";\n\t\t\tnvmem-cells = <&macaddr_factory_4>;\n\t\t\tnvmem-cell-names = \"mac-address\";\n\t\t\tmac-address-increment = <2>;\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"uart3\", \"uart2\", \"jtag\", \"wdt\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&nand {\n\tstatus = \"okay\";\n\n\tpartitions {\n\t\tcompatible = \"fixed-partitions\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"u-boot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@100000 {\n\t\t\tlabel = \"SC PART_MAP\";\n\t\t\treg = <0x100000 0x100000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@200000 {\n\t\t\tlabel = \"kernel\";\n\t\t\treg = <0x200000 0x400000>;\n\t\t};\n\n\t\tpartition@600000 {\n\t\t\tlabel = \"ubi\";\n\t\t\treg = <0x600000 0x2800000>;\n\t\t};\n\n\t\tpartition@2e00000 {\n\t\t\tlabel = \"reserved0\";\n\t\t\treg = <0x2e00000 0x1800000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tfactory: partition@4600000 {\n\t\t\tlabel = \"factory\";\n\t\t\treg = <0x4600000 0x200000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@4800000 {\n\t\t\tlabel = \"reserved1\";\n\t\t\treg = <0x4800000 0x3800000>;\n\t\t\tread-only;\n\t\t};\n\t};\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_netgear_wac104.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-only or MIT\n\n#include \"mt7621.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"netgear,wac104\", \"mediatek,mt7621-soc\";\n\tmodel = \"Netgear WAC104\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t\tlabel-mac-device = &gmac0;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\n\t\twifi {\n\t\t\tlabel = \"wifi\";\n\t\t\tgpios = <&gpio 8 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RFKILL>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twps {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_power: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twifi {\n\t\t\tlabel = \"green:wifi\";\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\t};\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&nand {\n\tstatus = \"okay\";\n\n\tpartitions {\n\t\tcompatible = \"fixed-partitions\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"u-boot\";\n\t\t\treg = <0x0 0x100000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@100000 {\n\t\t\tlabel = \"SC PID\";\n\t\t\treg = <0x100000 0x100000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@200000 {\n\t\t\tlabel = \"kernel\";\n\t\t\treg = <0x200000 0x400000>;\n\t\t};\n\n\t\tpartition@600000 {\n\t\t\tlabel = \"ubi\";\n\t\t\treg = <0x600000 0x1c00000>;\n\t\t};\n\n\t\tfactory: partition@2e00000 {\n\t\t\tlabel = \"factory\";\n\t\t\treg = <0x2e00000 0x100000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@4200000 {\n\t\t\tlabel = \"reserved\";\n\t\t\treg = <0x4200000 0x3c00000>;\n\t\t\tread-only;\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\twifi@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\t};\n};\n\n&pcie1 {\n\twifi@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x0>;\n\t\tieee80211-freq-limit = <2400000 2500000>;\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"uart3\", \"jtag\", \"wdt\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&switch0 {\n\tports {\n\t\tport@0 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan4\";\n\t\t};\n\n\t\tport@1 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan3\";\n\t\t};\n\n\t\tport@2 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan2\";\n\t\t};\n\n\t\tport@3 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan1\";\n\t\t};\n\t};\n};\n\n&xhci {\n\tstatus = \"disabled\";\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_netgear_wac124.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-only\n\n#include \"mt7621_netgear_sercomm_chj.dtsi\"\n\n/ {\n\tcompatible = \"netgear,wac124\", \"mediatek,mt7621-soc\";\n\tmodel = \"Netgear WAC124\";\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_netgear_wndr3700-v5.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-only\n\n#include \"mt7621_netgear_sercomm_ayx.dtsi\"\n\n/ {\n\tcompatible = \"netgear,wndr3700-v5\", \"mediatek,mt7621-soc\";\n\tmodel = \"Netgear WNDR3700 v5\";\n\n\taliases {\n\t\tlabel-mac-device = &gmac0;\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@f30000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0xf30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0xee0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wan {\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <1>;\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_netis_wf2881.dts",
    "content": "#include \"mt7621.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"netis,wf2881\", \"mediatek,mt7621-soc\";\n\tmodel = \"NETIS WF2881\";\n\n\taliases {\n\t\tled-boot = &led_wps;\n\t\tled-failsafe = &led_wps;\n\t\tled-running = &led_wps;\n\t\tled-upgrade = &led_wps;\n\t\tlabel-mac-device = &gmac0;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tusb {\n\t\t\tlabel = \"green:usb\";\n\t\t\tgpios = <&gpio 6 GPIO_ACTIVE_LOW>;\n\t\t\ttrigger-sources = <&xhci_ehci_port1>, <&ehci_port2>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\n\t\tled_wps: wps {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&gpio 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n};\n\n&nand {\n\tstatus = \"okay\";\n\n\tpartitions {\n\t\tcompatible = \"fixed-partitions\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"u-boot\";\n\t\t\treg = <0x0 0x80000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@80000 {\n\t\t\tlabel = \"config\";\n\t\t\treg = <0x80000 0x80000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tfactory: partition@100000 {\n\t\t\tlabel = \"factory\";\n\t\t\treg = <0x100000 0x40000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@140000 {\n\t\t\tlabel = \"firmware\";\n\t\t\treg = <0x140000 0x7e40000>;\n\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"kernel\";\n\t\t\t\treg = <0x0 0x400000>;\n\t\t\t};\n\n\t\t\tpartition@400000 {\n\t\t\t\tlabel = \"ubi\";\n\t\t\t\treg = <0x400000 0x7a40000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\twifi@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\n\t\tled {\n\t\t\tled-sources = <2>;\n\t\t\tled-active-low;\n\t\t};\n\t};\n};\n\n&pcie1 {\n\twifi@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x0000>;\n\t\tieee80211-freq-limit = <2400000 2500000>;\n\n\t\tled {\n\t\t\tled-sources = <2>;\n\t\t\tled-active-low;\n\t\t};\n\t};\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_factory_e000>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&switch0 {\n\tports {\n\t\tport@0 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan4\";\n\t\t};\n\n\t\tport@1 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan3\";\n\t\t};\n\n\t\tport@2 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan2\";\n\t\t};\n\n\t\tport@3 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan1\";\n\t\t};\n\n\t\tport@4 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"wan\";\n\t\t\tnvmem-cells = <&macaddr_factory_e006>;\n\t\t\tnvmem-cell-names = \"mac-address\";\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"uart3\", \"uart2\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_e000: macaddr@e000 {\n\t\treg = <0xe000 0x6>;\n\t};\n\n\tmacaddr_factory_e006: macaddr@e006 {\n\t\treg = <0xe006 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_oraybox_x3a.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"oraybox,x3a\", \"mediatek,mt7621-soc\";\n\tmodel = \"OrayBox X3A\";\n\n\taliases {\n\t\tled-boot = &led_status_green;\n\t\tled-failsafe = &led_status_red;\n\t\tled-running = &led_status_blue;\n\t\tled-upgrade = &led_status_green;\n\t\tlabel-mac-device = &gmac0;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200\";\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_status_red: status-red {\n\t\t\tlabel = \"red:status\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_status_blue: status-blue {\n\t\t\tlabel = \"blue:status\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_status_green: status-green {\n\t\t\tlabel = \"green:status\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <30000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0xf00000>;\n\t\t\t};\n\n\t\t\tpartition@fe0000 {\n\t\t\t\tlabel = \"bdinfo\";\n\t\t\t\treg = <0xfe0000 0x10000>;\n\t\t\t\tread-only;\n\n\t\t\t\tcompatible = \"nvmem-cells\";\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\n\t\t\t\tmacaddr_bdinfo_9: macaddr@9 {\n\t\t\t\t\treg = <0x9 0x6>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tpartition@ff0000 {\n\t\t\t\tlabel = \"reserve\";\n\t\t\t\treg = <0xff0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\twifi@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x0>;\n\t};\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_bdinfo_9>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&switch0 {\n\tports {\t\t\n\t\tport@2 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan2\";\n\t\t};\n\n\t\tport@3 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan1\";\n\t\t};\n\n\t\tport@4 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"wan\";\n\t\t\tnvmem-cells = <&macaddr_bdinfo_9>;\n\t\t\tnvmem-cell-names = \"mac-address\";\n\t\t\tmac-address-increment = <1>;\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"jtag\", \"wdt\";\n\t\tfunction = \"gpio\";\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_phicomm_k2p.dts",
    "content": "#include \"mt7621.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"phicomm,k2p\", \"mediatek,mt7621-soc\";\n\tmodel = \"Phicomm K2P\";\n\n\taliases {\n\t\tled-boot = &led_blue;\n\t\tled-failsafe = &led_blue;\n\t\tled-running = &led_blue;\n\t\tled-upgrade = &led_blue;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tstat_r {\n\t\t\tlabel = \"red:status\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tstat_y {\n\t\t\tlabel = \"yellow:status\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_blue: stat_b {\n\t\t\tlabel = \"blue:status\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 3 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <80000000>;\n\t\tm25p,fast-read;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tlabel = \"permanent_config\";\n\t\t\t\treg = <0x50000 0x50000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@a0000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0xa0000 0xf60000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\twifi@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x0>;\n\n\t\t/* 5 GHz (phy1) does not take the address from calibration data,\n\t\t   but setting it manually here works */\n\t\tnvmem-cells = <&macaddr_factory_4>;\n\t\tnvmem-cell-names = \"mac-address\";\n\t};\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_factory_e000>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&switch0 {\n\tports {\n\t\tport@0 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan1\";\n\t\t};\n\n\t\tport@1 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan2\";\n\t\t};\n\n\t\tport@2 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan3\";\n\t\t};\n\n\t\tport@3 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan4\";\n\t\t};\n\n\t\tport@4 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"wan\";\n\t\t\tnvmem-cells = <&macaddr_factory_e006>;\n\t\t\tnvmem-cell-names = \"mac-address\";\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"jtag\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n\n\tmacaddr_factory_e000: macaddr@e000 {\n\t\treg = <0xe000 0x6>;\n\t};\n\n\tmacaddr_factory_e006: macaddr@e006 {\n\t\treg = <0xe006 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_planex_vr500.dts",
    "content": "#include \"mt7621.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"planex,vr500\", \"mediatek,mt7621-soc\";\n\tmodel = \"Planex VR500\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 45 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 47 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x3fb0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_factory_e000>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&switch0 {\n\tports {\n\t\tport@0 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan1\";\n\t\t};\n\n\t\tport@1 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan2\";\n\t\t};\n\n\t\tport@2 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan3\";\n\t\t};\n\n\t\tport@3 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan4\";\n\t\t};\n\n\t\tport@4 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"wan\";\n\t\t\tnvmem-cells = <&macaddr_factory_e006>;\n\t\t\tnvmem-cell-names = \"mac-address\";\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"sdhci\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_e000: macaddr@e000 {\n\t\treg = <0xe000 0x6>;\n\t};\n\n\tmacaddr_factory_e006: macaddr@e006 {\n\t\treg = <0xe006 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_raisecom_msg1500-x-00.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"raisecom,msg1500-x-00\", \"mediatek,mt7621-soc\";\n\tmodel = \"RAISECOM MSG1500 X.00\";\n\n\taliases {\n\t\tled-boot = &led_usb;\n\t\tled-failsafe = &led_usb;\n\t\tled-upgrade = &led_usb;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twlan2g {\n\t\t\tlabel = \"blue:wlan2g\";\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0radio\";\n\t\t};\n\n\t\twlan5g {\n\t\t\tlabel = \"blue:wlan5g\";\n\t\t\tgpios = <&gpio 3 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1radio\";\n\t\t};\n\n\t\tled_usb: usb {\n\t\t\tlabel = \"blue:usb\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t\ttrigger-sources = <&ehci_port2>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\n\t\twifi {\n\t\t\tlabel = \"wifi\";\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RFKILL>;\n\t\t};\n\t};\n};\n\n&nand {\n\tstatus = \"okay\";\n\n\tpartitions {\n\t\tcompatible = \"fixed-partitions\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"Bootloader\";\n\t\t\treg = <0x0 0x80000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@80000 {\n\t\t\tlabel = \"Config\";\n\t\t\treg = <0x80000 0x80000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tfactory: partition@100000 {\n\t\t\tlabel = \"Factory\";\n\t\t\treg = <0x100000 0x40000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@140000 {\n\t\t\tlabel = \"kernel\";\n\t\t\treg = <0x140000 0x400000>;\n\t\t};\n\n\t\tpartition@540000 {\n\t\t\tlabel = \"ubi\";\n\t\t\treg = <0x540000 0x7a40000>;\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\twifi@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x0>;\n\t\t/* 5 GHz (phy1) does not take the address from calibration data,\n\t\t   but setting it manually here works */\n\t\tnvmem-cells = <&macaddr_factory_4>;\n\t\tnvmem-cell-names = \"mac-address\";\n\t};\n};\n\n&switch0 {\n\tports {\n\t\tport@0 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan4\";\n\t\t};\n\n\t\tport@1 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan3\";\n\t\t};\n\n\t\tport@2 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan2\";\n\t\t};\n\n\t\tport@3 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan1\";\n\t\t};\n\n\t\tport@4 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"wan\";\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"jtag\", \"uart3\", \"wdt\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_renkforce_ws-wn530hp3-a.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"renkforce,ws-wn530hp3-a\", \"mediatek,mt7621-soc\";\n\tmodel = \"Renkforce WS-WN530HP3-A\";\n\n\taliases {\n\t\tlabel-mac-device = &gmac0;\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: led_1 {\n\t\t\tlabel = \"red:led1\";\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_2 {\n\t\t\tlabel = \"blue:led2\";\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <40000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0xf30000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\twifi0: wifi@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x0000>;\n\t\tieee80211-freq-limit = <2400000 2500000>;\n\t\tnvmem-cells = <&macaddr_factory_4>;\n\t\tnvmem-cell-names = \"mac-address\";\n\t};\n};\n\n&pcie1 {\n\twifi1: wifi@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\t\tnvmem-cells = <&macaddr_factory_4>;\n\t\tnvmem-cell-names = \"mac-address\";\n\t\tmac-address-increment = <1>;\n\t};\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <(-2)>;\n};\n\n&switch0 {\n\tports {\n\t\tport@0 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan2\";\n\t\t};\n\n\t\tport@1 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan1\";\n\t\t};\n\n\t\tport@4 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"wan\";\n\t\t\tnvmem-cells = <&macaddr_factory_4>;\n\t\t\tnvmem-cell-names = \"mac-address\";\n\t\t\tmac-address-increment = <(-1)>;\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"uart2\", \"jtag\", \"wdt\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&xhci {\n\tstatus = \"disabled\";\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_samknows_whitebox-v8.dts",
    "content": "#include \"mt7621.dtsi\"\n\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/gpio/gpio.h>\n\n/ {\n\tcompatible = \"samknows,whitebox-v8\", \"mediatek,mt7621-soc\";\n\tmodel = \"SamKnows Whitebox 8\";\n\n\taliases {\n\t\tled-boot = &led_wps;\n\t\tled-failsafe = &led_wps;\n\t\tled-running = &led_wps;\n\t\tled-upgrade = &led_wps;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_wps: wps {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&gpio 46 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tusb {\n\t\t\tlabel = \"green:usb\";\n\t\t\tgpios = <&gpio 47 GPIO_ACTIVE_LOW>;\n\t\t\ttrigger-sources = <&xhci_ehci_port1>, <&ehci_port2>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio 43 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 41 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0xfb0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\tmt76@0,0 {\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\t};\n};\n\n&pcie1 {\n\tmt76@0,0 {\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x0000>;\n\t};\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_factory_e000>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&switch0 {\n\tports {\n\t\tport@0 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan1\";\n\t\t};\n\n\t\tport@1 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan2\";\n\t\t};\n\n\t\tport@2 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan3\";\n\t\t};\n\n\t\tport@3 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan4\";\n\t\t};\n\n\t\tport@4 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"wan\";\n\t\t\tnvmem-cells = <&macaddr_factory_e006>;\n\t\t\tnvmem-cell-names = \"mac-address\";\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"sdhci\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_e000: macaddr@e000 {\n\t\treg = <0xe000 0x6>;\n\t};\n\n\tmacaddr_factory_e006: macaddr@e006 {\n\t\treg = <0xe006 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_sercomm_na502.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later\n\n#include \"mt7621.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"sercomm,na502\", \"mediatek,mt7621-soc\";\n\tmodel = \"SERCOMM NA502\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tinternet {\n\t\t\tlabel = \"green:internet\";\n\t\t\tgpios = <&gpio 24 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twifi {\n\t\t\tlabel = \"green:wifi\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\tzwave {\n\t\t\tlabel = \"green:zwave\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tservice {\n\t\t\tlabel = \"green:service\";\n\t\t\tgpios = <&gpio 26 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tzigbee {\n\t\t\tlabel = \"green:zigbee\";\n\t\t\tgpios = <&gpio 27 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tbluetooth {\n\t\t\tlabel = \"green:bluetooth\";\n\t\t\tgpios = <&gpio 25 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 28 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\tselect {\n\t\t\tlabel = \"select\";\n\t\t\tgpios = <&gpio 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_0>;\n\t\t};\n\n\t\tsync {\n\t\t\tlabel = \"sync\";\n\t\t\tgpios = <&gpio 32 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RFKILL>;\n\t\t};\n\t};\n\n\tgpio-export {\n\t\tcompatible = \"gpio-export\";\n\n\t\tzwave_reset {\n\t\t\tgpio-export,name = \"zwave_reset\";\n\t\t\tgpio-export,output = <1>;\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tzigbee_reset {\n\t\t\tgpio-export,name = \"zigbee_reset\";\n\t\t\tgpio-export,output = <1>;\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&ethernet {\n\tpinctrl-0 = <&mdio_pins>, <&rgmii1_pins>;\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_factory_e000>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&nand {\n\tstatus = \"okay\";\n\n\tpartitions {\n\t\tcompatible = \"fixed-partitions\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"u-boot\";\n\t\t\treg = <0x0 0x80000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@80000 {\n\t\t\tlabel = \"config\";\n\t\t\treg = <0x80000 0x80000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tfactory: partition@100000 {\n\t\t\tlabel = \"factory\";\n\t\t\treg = <0x100000 0x40000>;\n\t\t};\n\n\t\tpartition@140000 {\n\t\t\tlabel = \"kernel1\";\n\t\t\treg = <0x140000 0x1400000>;\n\t\t};\n\n\t\tpartition@1540000 {\n\t\t\tlabel = \"kernel\";\n\t\t\treg = <0x1540000 0x400000>;\n\t\t};\n\n\t\tpartition@1940000 {\n\t\t\tlabel = \"ubi\";\n\t\t\treg = <0x1940000 0x1000000>;\n\t\t};\n\n\t\tpartition@2940000 {\n\t\t\tlabel = \"user_storage\";\n\t\t\treg = <0x2940000 0x100000>;\n\t\t};\n\n\t\tpartition@2a40000 {\n\t\t\tlabel = \"data\";\n\t\t\treg = <0x2a40000 0x1000000>;\n\t\t};\n\n\t\tpartition@3a40000 {\n\t\t\tlabel = \"storage\";\n\t\t\treg = <0x3a40000 0x3200000>;\n\t\t};\n\n\t\tpartition@6c40000 {\n\t\t\tlabel = \"backup\";\n\t\t\treg = <0x6c40000 0x1340000>;\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\twifi@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t\tnvmem-cells = <&macaddr_factory_e000>;\n\t\tnvmem-cell-names = \"mac-address\";\n\t\tmac-address-increment = <1>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\t};\n};\n\n&pcie1 {\n\twifi@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x0000>;\n\t\tnvmem-cells = <&macaddr_factory_e000>;\n\t\tnvmem-cell-names = \"mac-address\";\n\t\tmac-address-increment = <2>;\n\t\tieee80211-freq-limit = <2400000 2500000>;\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"jtag\", \"rgmii2\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&switch0 {\n\tports {\n\t\tport@4 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan\";\n\t\t};\n\t};\n};\n\n&uartlite2 {\n\tstatus = \"okay\";\n};\n\n&uartlite3 {\n\tstatus = \"okay\";\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_e000: macaddr@e000 {\n\t\treg = <0xe000 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_storylink_sap-g3200u3.dts",
    "content": "#include \"mt7621.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"storylink,sap-g3200u3\", \"mediatek,mt7621-soc\";\n\tmodel = \"STORYLiNK SAP-G3200U3\";\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tusb {\n\t\t\tlabel = \"green:usb\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t\ttrigger-sources = <&xhci_ehci_port1>, <&ehci_port2>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\trfkill {\n\t\t\tlabel = \"rfkill\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RFKILL>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x1000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@31000 {\n\t\t\t\tlabel = \"config\";\n\t\t\t\treg = <0x31000 0xf000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x7b0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\tmt76@0,0 {\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\t};\n};\n\n&pcie1 {\n\tmt76@0,0 {\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x0000>;\n\t\tieee80211-freq-limit = <2400000 2500000>;\n\t};\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_factory_e006>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&switch0 {\n\tports {\n\t\tport@0 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan1\";\n\t\t};\n\n\t\tport@1 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan2\";\n\t\t};\n\n\t\tport@2 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan3\";\n\t\t};\n\n\t\tport@3 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan4\";\n\t\t};\n\n\t\tport@4 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"wan\";\n\t\t\tnvmem-cells = <&macaddr_factory_e006>;\n\t\t\tnvmem-cell-names = \"mac-address\";\n\t\t\tmac-address-increment = <1>;\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"uart3\", \"jtag\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_e006: macaddr@e006 {\n\t\treg = <0xe006 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_telco-electronics_x1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"telco-electronics,x1\", \"mediatek,mt7621-soc\";\n\tmodel = \"Telco Electronics X1\";\n\n\taliases {\n\t\tled-boot = &system_led;\n\t\tled-failsafe = &system_led;\n\t\tled-running = &system_led;\n\t\tled-upgrade = &system_led;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tsystem_led: system {\n\t\t\tlabel = \"green:system\";\n\t\t\tgpios = <&gpio 26 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tmodem_offline {\n\t\t\tlabel = \"red:modem-offline\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tmodem_4g {\n\t\t\tlabel = \"blue:modem-4g\";\n\t\t\tgpios = <&gpio 24 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tmodem_3g {\n\t\t\tlabel = \"green:modem-3g\";\n\t\t\tgpios = <&gpio 25 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tmodem_rssi_lowest {\n\t\t\tlabel = \"green:modem-rssi-lowest\";\n\t\t\tgpios = <&gpio 27 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tmodem_rssi_low {\n\t\t\tlabel = \"green:modem-rssi-low\";\n\t\t\tgpios = <&gpio 28 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tmodem_rssi_medium {\n\t\t\tlabel = \"green:modem-rssi-medium\";\n\t\t\tgpios = <&gpio 29 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tmodem_rssi_high {\n\t\t\tlabel = \"green:modem-rssi-high\";\n\t\t\tgpios = <&gpio 30 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tmodem_rssi_highest {\n\t\t\tlabel = \"green:modem-rssi-highest\";\n\t\t\tgpios = <&gpio 31 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <14000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"bootloader\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"config\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfirmware: partition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0xfb0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&ethernet {\n\tpinctrl-0 = <&mdio_pins>, <&rgmii1_pins>;\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_factory_e006>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&switch0 {\n\tports {\n\t\tport@0 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan1\";\n\t\t};\n\n\t\tport@1 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan2\";\n\t\t};\n\n\t\tport@2 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan3\";\n\t\t};\n\n\t\tport@3 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan4\";\n\t\t};\n\n\t\tport@4 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"wan\";\n\t\t\tnvmem-cells = <&macaddr_factory_e006>;\n\t\t\tnvmem-cell-names = \"mac-address\";\n\t\t\tmac-address-increment = <1>;\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"wdt\", \"rgmii2\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\twifi@0,0 {\n\t\tcompatible = \"pci14c3,7603\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x0000>;\n\t\tieee80211-freq-limit = <2400000 2500000>;\n\t};\n};\n\n&pcie1 {\n\twifi@0,0 {\n\t\tcompatible = \"pci14c3,7662\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\n\t\tled {\n\t\t\tled-sources = <2>;\n\t\t};\n\t};\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_e006: macaddr@e006 {\n\t\treg = <0xe006 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_tenbay_t-mb5eu-v01.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"tenbay,t-mb5eu-v01\", \"mediatek,mt7621-soc\";\n\tmodel = \"Tenbay T-MB5EU-V01\";\n\n\taliases {\n\t\tled-boot = &led_green;\n\t\tled-failsafe = &led_red;\n\t\tled-running = &led_blue;\n\t\tled-upgrade = &led_red;\n\t\tlabel-mac-device = &wan_port;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200\";\n\t\tbootargs-override = \"console=ttyS0,115200\";\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tpinctrl-names = \"default\";\n\t\tpinctrl-0 = <&led_pins>;\n\n\t\tled_blue: blue {\n\t\t\tlabel = \"blue\";\n\t\t\tgpios = <&aw9523 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_red: red {\n\t\t\tlabel = \"red\";\n\t\t\tgpios = <&aw9523 1 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_green: green {\n\t\t\tlabel = \"green\";\n\t\t\tgpios = <&aw9523 11 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <50>;\n\t\tpinctrl-names = \"default\";\n\t\tpinctrl-0 = <&button_pins>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&aw9523 9 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&aw9523 8 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n\n\ti2c-gpio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcompatible = \"i2c-gpio\";\n\t\tgpios = <&gpio 7 GPIO_ACTIVE_HIGH &gpio 8 GPIO_ACTIVE_HIGH>;\n\t\ti2c-gpio,delay-us = <10>;\n\n\t\taw9523: gpio-expander@5b {\n\t\t\tcompatible = \"awinic,aw9523-pinctrl\";\n\t\t\treg = <0x5b>;\n\t\t\tgpio-controller;\n\t\t\t#gpio-cells = <2>;\n\t\t\tgpio-ranges = <&aw9523 0 0 16>;\n\n\t\t\treset-gpios = <&gpio 6 GPIO_ACTIVE_HIGH>;\n\n\t\t\tbutton_pins: button-pins {\n\t\t\t\tpins = \"gpio8\", \"gpio9\";\n\t\t\t\tfunction = \"gpio\";\n\t\t\t\tbias-pull-up;\n\t\t\t\tdrive-open-drain;\n\t\t\t\tinput-enable;\n\t\t\t};\n\n\t\t\tled_pins: led-pins {\n\t\t\t\tpins = \"gpio0\", \"gpio1\", \"gpio11\";\n\t\t\t\tfunction = \"gpio\";\n\t\t\t\tinput-disable;\n\t\t\t\toutput-low;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie1 {\n\twifi@0,0 {\n\t\treg = <0x0 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x0>;\n\t};\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&switch0 {\n\tports {\n\t\twan_port: port@0 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"wan\";\n\t\t\tnvmem-cells = <&macaddr_factory_4>;\n\t\t\tnvmem-cell-names = \"mac-address\";\n\t\t\tmac-address-increment = <(-2)>;\n\t\t};\n\n\t\tport@1 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan1\";\n\t\t};\n\n\t\tport@2 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan2\";\n\t\t};\n\n\t\tport@3 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan3\";\n\t\t};\n\n\t\tport@4 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan4\";\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"uart3\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <50000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"product\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@50000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x50000 0x40000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@90000 {\n\t\t\t\tcompatible = \"denx,fit\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x90000 0xf70000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_thunder_timecloud.dts",
    "content": "#include \"mt7621.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"thunder,timecloud\", \"mediatek,mt7621-soc\";\n\tmodel = \"Thunder Timecloud\";\n\n\taliases {\n\t\tled-boot = &led_statuso;\n\t\tled-failsafe = &led_statuso;\n\t\tled-running = &led_statuso;\n\t\tled-upgrade = &led_statuso;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200\";\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tstatw {\n\t\t\tlabel = \"white:status\";\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tled_statuso: stato {\n\t\t\tlabel = \"orange:status\";\n\t\t\tgpios = <&gpio 8 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\tBTN_0 {\n\t\t\tlabel = \"BTN_0\";\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_0>;\n\t\t};\n\t};\n};\n\n&sdhci {\n\tstatus = \"okay\";\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0xfb0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_factory_e000>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&switch0 {\n\tports {\n\t\tport@4 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan\";\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"uart2\", \"jtag\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_e000: macaddr@e000 {\n\t\treg = <0xe000 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_totolink_a7000r.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"totolink,a7000r\", \"mediatek,mt7621-soc\";\n\tmodel = \"TOTOLINK A7000R\";\n\n\taliases {\n\t\tled-boot = &led_sys;\n\t\tled-failsafe = &led_sys;\n\t\tled-running = &led_sys;\n\t\tled-upgrade = &led_sys;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_sys: sys {\n\t\t\tlabel = \"blue:sys\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <40000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0xfb0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\twifi@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x0000>;\n\t\tieee80211-freq-limit = <2400000 2500000>;\n\t};\n};\n\n&pcie1 {\n\twifi@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\t};\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_factory_e000>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&switch0 {\n\tports {\n\t\tport@0 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan1\";\n\t\t};\n\n\t\tport@1 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan2\";\n\t\t};\n\n\t\tport@2 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan3\";\n\t\t};\n\n\t\tport@3 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan4\";\n\t\t};\n\n\t\tport@4 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"wan\";\n\t\t\tnvmem-cells = <&macaddr_factory_e000>;\n\t\t\tnvmem-cell-names = \"mac-address\";\n\t\t\tmac-address-increment = <1>;\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"wdt\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_e000: macaddr@e000 {\n\t\treg = <0xe000 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_totolink_x5000r.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"totolink,x5000r\", \"mediatek,mt7621-soc\";\n\tmodel = \"TOTOLINK X5000R\";\n\n\taliases {\n\t\tled-boot = &led_sys;\n\t\tled-failsafe = &led_sys;\n\t\tled-running = &led_sys;\n\t\tled-upgrade = &led_sys;\n\t\tlabel-mac-device = &gmac0;\n\t};\n\n\tchosen {\n\t\tstdout-path = \"serial0:115200n8\";\n\t\tbootargs = \"console=ttyS0,115200n8\";\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_sys: sys {\n\t\t\tlabel = \"blue:sys\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <50000000>;\n\t\tm25p,fast-read;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0xfb0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie1 {\n\twifi@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x0000>;\n\t};\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_factory_e000>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&switch0 {\n\tports {\n\t\tport@0 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan1\";\n\t\t};\n\n\t\tport@1 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan2\";\n\t\t};\n\n\t\tport@2 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan3\";\n\t\t};\n\n\t\tport@3 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan4\";\n\t\t};\n\n\t\tport@4 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"wan\";\n\t\t\tnvmem-cells = <&macaddr_factory_e006>;\n\t\t\tnvmem-cell-names = \"mac-address\";\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"wdt\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_e000: macaddr@e000 {\n\t\treg = <0xe000 0x6>;\n\t};\n\n\tmacaddr_factory_e006: macaddr@e006 {\n\t\treg = <0xe006 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_tplink_archer-a6-v3.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621_tplink_archer-x6-v3.dtsi\"\n\n/ {\n\tcompatible = \"tplink,archer-a6-v3\", \"mediatek,mt7621-soc\";\n\tmodel = \"TP-Link Archer A6 v3\";\n\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_tplink_archer-c6-v3.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621_tplink_archer-x6-v3.dtsi\"\n\n/ {\n\tcompatible = \"tplink,archer-c6-v3\", \"mediatek,mt7621-soc\";\n\tmodel = \"TP-Link Archer C6 v3\";\n\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_tplink_archer-c6u-v1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"tplink,archer-c6u-v1\", \"mediatek,mt7621-soc\";\n\tmodel = \"TP-Link Archer C6U v1\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t\tlabel-mac-device = &gmac0;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 8 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio 10 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tusb {\n\t\t\tlabel = \"green:usb\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t\ttrigger-sources = <&ehci_port2>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\n\t\twan-orange {\n\t\t\tlabel = \"orange:wan\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan {\n\t\t\tlabel = \"green:lan\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twifi5g {\n\t\t\tlabel = \"green:wifi5g\";\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\n\t\twifi2g {\n\t\t\tlabel = \"green:wifi2g\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\twan-green {\n\t\t\tlabel = \"green:wan\";\n\t\t\tgpios = <&gpio 45 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\treg_usb_vbus: regulator {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"usb_vbus\";\n\t\tregulator-min-microvolt = <5000000>;\n\t\tregulator-max-microvolt = <5000000>;\n\t\tgpio = <&gpio 3 GPIO_ACTIVE_HIGH>;\n\t\tenable-active-high;\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <80000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x000000 0x040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x040000 0xf60000>;\n\t\t\t};\n\n\t\t\tconfig: partition@fa0000 {\n\t\t\t\tlabel = \"config\";\n\t\t\t\treg = <0xfa0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@fb0000 {\n\t\t\t\tlabel = \"tplink\";\n\t\t\t\treg = <0xfb0000 0x040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tradio: partition@ff0000 {\n\t\t\t\tlabel = \"radio\";\n\t\t\t\treg = <0xff0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\tmt76@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&radio 0x0>;\n\t\tnvmem-cells = <&macaddr_config_8>;\n\t\tnvmem-cell-names = \"mac-address\";\n\t\tieee80211-freq-limit = <2400000 2500000>;\n\t};\n};\n\n&pcie1 {\n\tmt76@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&radio 0x8000>;\n\t\tnvmem-cells = <&macaddr_config_8>;\n\t\tnvmem-cell-names = \"mac-address\";\n\t\tmac-address-increment = <(-1)>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\t};\n};\n\n&ethernet {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&rgmii1_pins &mdio_pins>;\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_config_8>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&switch0 {\n\tports {\n\t\tport@0 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"wan\";\n\t\t\tnvmem-cells = <&macaddr_config_8>;\n\t\t\tnvmem-cell-names = \"mac-address\";\n\t\t\tmac-address-increment = <1>;\n\t\t};\n\n\t\tport@1 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan1\";\n\t\t};\n\n\t\tport@2 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan2\";\n\t\t};\n\n\t\tport@3 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan3\";\n\t\t};\n\n\t\tport@4 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan4\";\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"uart2\", \"uart3\", \"jtag\", \"wdt\", \"sdhci\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&xhci {\n\tvbus-supply = <&reg_usb_vbus>;\n};\n\n&config {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_config_8: macaddr@8 {\n\t\treg = <0x8 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_tplink_archer-x6-v3.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-only\n\n#include \"mt7621.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\taliases {\n\t\tlabel-mac-device = &gmac0;\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200n8\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio 28 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 8 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twan_orange {\n\t\t\tlabel = \"orange:wan\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan {\n\t\t\tlabel = \"green:lan\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twifi5g {\n\t\t\tlabel = \"green:wifi5g\";\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\n\t\twifi2g {\n\t\t\tlabel = \"green:wifi2g\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\twan_green {\n\t\t\tlabel = \"green:wan\";\n\t\t\tgpios = <&gpio 45 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <40000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x40000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\treg = <0x40000 0xf60000>;\n\t\t\t};\n\n\t\t\tconfig: partition@fa0000 {\n\t\t\t\tlabel = \"config\";\n\t\t\t\treg = <0xfa0000 0x50000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tradio: partition@ff0000 {\n\t\t\t\tlabel = \"radio\";\n\t\t\t\treg = <0xff0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups =  \"i2c\", \"rgmii2\", \"uart2\", \"uart3\", \"jtag\", \"wdt\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&rgmii1_pins &mdio_pins>;\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\twifi@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&radio 0x0>;\n\t\tnvmem-cells = <&macaddr_config_8>;\n\t\tnvmem-cell-names = \"mac-address\";\n\t\tmac-address-increment = <1>;\n\t\tieee80211-freq-limit = <2400000 2500000>;\n\t};\n};\n\n&pcie1 {\n\twifi@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&radio 0x8000>;\n\t\tnvmem-cells = <&macaddr_config_8>;\n\t\tnvmem-cell-names = \"mac-address\";\n\t\tmac-address-increment = <2>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\t};\n};\n\n&ethernet {\n\tpinctrl-0 = <&mdio_pins>, <&rgmii1_pins>;\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_config_8>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&switch0 {\n\tports {\n\t\tport@0 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"wan\";\n\t\t};\n\n\t\tport@1 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan1\";\n\t\t};\n\n\t\tport@2 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan2\";\n\t\t};\n\n\t\tport@3 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan3\";\n\t\t};\n\n\t\tport@4 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan4\";\n\t\t};\n\t};\n};\n\n&config {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_config_8: macaddr@8 {\n\t\treg = <0x8 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_tplink_eap235-wall-v1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later\n\n#include \"mt7621.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/leds/common.h>\n\n/ {\n\tcompatible = \"tplink,eap235-wall-v1\", \"mediatek,mt7621-soc\";\n\tmodel = \"TP-Link EAP235-Wall v1\";\n\n\taliases {\n\t\tlabel-mac-device = &gmac0;\n\t\tled-boot = &led_status;\n\t\tled-failsafe = &led_status;\n\t\tled-running = &led_status;\n\t\tled-upgrade = &led_status;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_status: status {\n\t\t\tlabel = \"white:status\";\n\t\t\tcolor = <LED_COLOR_ID_WHITE>;\n\t\t\tfunction = LED_FUNCTION_STATUS;\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\tled {\n\t\t\tlabel = \"led\";\n\t\t\tgpios = <&gpio 10 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_LIGHTS_TOGGLE>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 8 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tgpio-export {\n\t\tcompatible = \"gpio-export\";\n\n\t\tpoe_passthrough {\n\t\t\tgpio-export,name = \"poe-passthrough\";\n\t\t\tgpio-export,output = <0>;\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <20000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x00000 0x80000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@80000 {\n\t\t\t\tlabel = \"partition-table\";\n\t\t\t\treg = <0x80000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tinfo: partition@90000 {\n\t\t\t\tlabel = \"product-info\";\n\t\t\t\treg = <0x90000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@a0000 {\n\t\t\t\tcompatible = \"tplink,firmware\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x0a0000 0xd20000>;\n\t\t\t};\n\n\t\t\tpartition@dc0000 {\n\t\t\t\tlabel = \"user-config\";\n\t\t\t\treg = <0xdc0000 0x030000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\t/* 0xdf0000 - 0xf30000 unused  */\n\n\t\t\tpartition@f30000 {\n\t\t\t\tlabel = \"mutil-log\";\n\t\t\t\treg = <0xf30000 0x080000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@fb0000 {\n\t\t\t\tlabel = \"oops\";\n\t\t\t\treg = <0xfb0000 0x040000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tradio: partition@ff0000 {\n\t\t\t\tlabel = \"radio\";\n\t\t\t\treg = <0xff0000 0x010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"uart2\", \"uart3\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\twifi@0,0 {\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&radio 0x0>;\n\t\tnvmem-cells = <&macaddr_info_8>;\n\t\tnvmem-cell-names = \"mac-address\";\n\t};\n};\n\n&pcie1 {\n\twifi@0,0 {\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&radio 0x8000>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\t\tnvmem-cells = <&macaddr_info_8>;\n\t\tnvmem-cell-names = \"mac-address\";\n\t\tmac-address-increment = <1>;\n\t};\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_info_8>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&switch0 {\n\tports {\n\t\tport@0 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan0\";\n\t\t};\n\n\t\tport@1 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan3\";\n\t\t};\n\n\t\tport@2 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan2\";\n\t\t};\n\n\t\tport@3 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan1\";\n\t\t};\n\t};\n};\n\n&info {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_info_8: macaddr@8 {\n\t\treg = <0x8 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_tplink_eap615-wall-v1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later\n\n#include \"mt7621.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/leds/common.h>\n\n/ {\n\tcompatible = \"tplink,eap615-wall-v1\", \"mediatek,mt7621-soc\";\n\tmodel = \"TP-Link EAP615-Wall v1\";\n\n\taliases {\n\t\tlabel-mac-device = &gmac0;\n\t\tled-boot = &led_status;\n\t\tled-failsafe = &led_status;\n\t\tled-running = &led_status;\n\t\tled-upgrade = &led_status;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200\";\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_status: status {\n\t\t\tlabel = \"white:status\";\n\t\t\tcolor = <LED_COLOR_ID_WHITE>;\n\t\t\tfunction = LED_FUNCTION_STATUS;\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\tled {\n\t\t\tlabel = \"led\";\n\t\t\tgpios = <&gpio 10 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_LIGHTS_TOGGLE>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 8 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tgpio-export {\n\t\tcompatible = \"gpio-export\";\n\n\t\tpoe_passthrough {\n\t\t\tgpio-export,name = \"poe-passthrough\";\n\t\t\tgpio-export,output = <0>;\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&ethernet {\n\treg = <0x1e100000 0xe000>;\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <20000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x80000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@80000 {\n\t\t\t\tlabel = \"partition-table\";\n\t\t\t\treg = <0x80000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tinfo: partition@90000 {\n\t\t\t\tlabel = \"product-info\";\n\t\t\t\treg = <0x90000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@a0000 {\n\t\t\t\tcompatible = \"denx,fit\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0xa0000 0xcf0000>;\n\t\t\t};\n\n\t\t\tpartition@d90000 {\n\t\t\t\tlabel = \"user-config\";\n\t\t\t\treg = <0xd90000 0x60000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@f30000 {\n\t\t\t\tlabel = \"mutil-log\";\n\t\t\t\treg = <0xf30000 0x80000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@fb0000 {\n\t\t\t\tlabel = \"oops\";\n\t\t\t\treg = <0xfb0000 0x40000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tradio: partition@ff0000 {\n\t\t\t\tlabel = \"radio\";\n\t\t\t\treg = <0xff0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"uart2\", \"uart3\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie1 {\n\twifi@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&radio 0x0>;\n\t\tnvmem-cells = <&macaddr_info_8>;\n\t\tnvmem-cell-names = \"mac-address\";\n\t};\n};\n\n&pcie2 {\n\tstatus = \"disabled\";\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_info_8>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&switch0 {\n\tcompatible = \"mediatek,mt7530\";\n\tports {\n\t\tport@0 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan0\";\n\t\t};\n\n\t\tport@1 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan3\";\n\t\t};\n\n\t\tport@2 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan2\";\n\t\t};\n\n\t\tport@3 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan1\";\n\t\t};\n\t};\n};\n\n&info {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_info_8: macaddr@8 {\n\t\treg = <0x8 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_tplink_re350-v1.dts",
    "content": "#include \"mt7621.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"tplink,re350-v1\", \"mediatek,mt7621-soc\";\n\tmodel = \"TP-LINK RE350 v1\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"blue:power\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twifi2g {\n\t\t\tlabel = \"blue:wifi2G\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twifi5g {\n\t\t\tlabel = \"blue:wifi5G\";\n\t\t\tgpios = <&gpio 24 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twps_r {\n\t\t\tlabel = \"red:wps\";\n\t\t\tgpios = <&gpio 25 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\twps_b {\n\t\t\tlabel = \"blue:wps\";\n\t\t\tgpios = <&gpio 26 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\teth {\n\t\t\tlabel = \"green:eth_act\";\n\t\t\tgpios = <&gpio 28 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\teth2 {\n\t\t\tlabel = \"green:eth_link\";\n\t\t\tgpios = <&gpio 29 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\tled {\n\t\t\tlabel = \"led\";\n\t\t\tgpios = <&gpio 30 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_0>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 31 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\tpower {\n\t\t\tlabel = \"power\";\n\t\t\tgpios = <&gpio 32 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_POWER>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio 33 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x20000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tcompatible = \"tplink,firmware\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x20000 0x5e0000>;\n\t\t\t};\n\n\t\t\tconfig: partition@600000 {\n\t\t\t\tlabel = \"config\";\n\t\t\t\treg = <0x600000 0x50000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tradio: partition@7f0000 {\n\t\t\t\tlabel = \"radio\";\n\t\t\t\treg = <0x7f0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\tmt76@0,0 {\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&radio 0x0>;\n\t\tnvmem-cells = <&macaddr_config_10008>;\n\t\tnvmem-cell-names = \"mac-address\";\n\t\tmac-address-increment = <1>;\n\t};\n};\n\n&pcie1 {\n\tmt76@0,0 {\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&radio 0x8000>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\t\tnvmem-cells = <&macaddr_config_10008>;\n\t\tnvmem-cell-names = \"mac-address\";\n\t\tmac-address-increment = <2>;\n\t};\n};\n\n&ethernet {\n\tpinctrl-0 = <&mdio_pins>, <&rgmii1_pins>;\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_config_10008>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&switch0 {\n\tports {\n\t\tport@0 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan\";\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"rgmii2\", \"wdt\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&config {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_config_10008: macaddr@10008 {\n\t\treg = <0x10008 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_tplink_re500-v1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621_tplink_rexx0-v1.dtsi\"\n\n/ {\n\tcompatible = \"tplink,re500-v1\", \"mediatek,mt7621-soc\";\n\tmodel = \"TP-Link RE500 v1\";\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_tplink_re650-v1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621_tplink_rexx0-v1.dtsi\"\n\n/ {\n\tcompatible = \"tplink,re650-v1\", \"mediatek,mt7621-soc\";\n\tmodel = \"TP-Link RE650 v1\";\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_tplink_re650-v2.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"tplink,re650-v2\", \"mediatek,mt7621-soc\";\n\tmodel = \"TP-Link RE650 v2\";\n\n\taliases {\n\t\tlabel-mac-device = &gmac0;\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\n\t\tpower {\n\t\t\tlabel = \"power\";\n\t\t\tgpios = <&gpio 25 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t\tlinux,code = <KEY_POWER>;\n\t\t};\n\n\t\tled {\n\t\t\tlabel = \"led\";\n\t\t\tgpios = <&gpio 30 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t\tlinux,code = <KEY_LIGHTS_TOGGLE>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 31 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"blue:power\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twifi2g {\n\t\t\tlabel = \"blue:wifi2g\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\twifi5g {\n\t\t\tlabel = \"blue:wifi5g\";\n\t\t\tgpios = <&gpio 24 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\n\t\twps_red {\n\t\t\tlabel = \"red:wps\";\n\t\t\tgpios = <&gpio 26 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\twps_blue {\n\t\t\tlabel = \"blue:wps\";\n\t\t\tgpios = <&gpio 27 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\teth_act {\n\t\t\tlabel = \"green:eth_act\";\n\t\t\tgpios = <&gpio 28 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\teth_link {\n\t\t\tlabel = \"green:eth_link\";\n\t\t\tgpios = <&gpio 29 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <40000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x20000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tcompatible = \"tplink,firmware\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x20000 0x7a0000>;\n\t\t\t};\n\n\t\t\tconfig: partition@7c0000 {\n\t\t\t\tlabel = \"config\";\n\t\t\t\treg = <0x7c0000 0x2d440>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tradio: partition@7f0000 {\n\t\t\t\tlabel = \"radio\";\n\t\t\t\treg = <0x7f0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"rgmii2\", \"wdt\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie1 {\n\twifi@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&radio 0x0>;\n\t\tnvmem-cells = <&macaddr_config_10008>;\n\t\tnvmem-cell-names = \"mac-address\";\n\t\tmac-address-increment = <1>;\n\t\tieee80211-freq-limit = <2400000 2500000>;\n\t};\n};\n\n&pcie0 {\n\twifi@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&radio 0x8000>;\n\t\tnvmem-cells = <&macaddr_config_10008>;\n\t\tnvmem-cell-names = \"mac-address\";\n\t\tmac-address-increment = <2>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\t};\n};\n\n&ethernet {\n\tpinctrl-0 = <&mdio_pins>, <&rgmii1_pins>;\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_config_10008>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&switch0 {\n\tports {\n\t\tport@0 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan\";\n\t\t};\n\t};\n};\n\n&config {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_config_10008: macaddr@10008 {\n\t\treg = <0x10008 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_tplink_rexx0-v1.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\taliases {\n\t\tlabel-mac-device = &gmac0;\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\n\t\tpower {\n\t\t\tlabel = \"power\";\n\t\t\tgpios = <&gpio 25 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t\tlinux,code = <KEY_POWER>;\n\t\t};\n\n\t\tled {\n\t\t\tlabel = \"led\";\n\t\t\tgpios = <&gpio 30 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t\tlinux,code = <KEY_LIGHTS_TOGGLE>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 31 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"blue:power\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twifi2g {\n\t\t\tlabel = \"blue:wifi2g\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\twifi5g {\n\t\t\tlabel = \"blue:wifi5g\";\n\t\t\tgpios = <&gpio 24 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\n\t\twps_red {\n\t\t\tlabel = \"red:wps\";\n\t\t\tgpios = <&gpio 26 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\twps_blue {\n\t\t\tlabel = \"blue:wps\";\n\t\t\tgpios = <&gpio 27 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\teth_act {\n\t\t\tlabel = \"green:eth_act\";\n\t\t\tgpios = <&gpio 28 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\teth_link {\n\t\t\tlabel = \"green:eth_link\";\n\t\t\tgpios = <&gpio 29 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <40000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x20000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tcompatible = \"tplink,firmware\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x20000 0xde0000>;\n\t\t\t};\n\n\t\t\tconfig: partition@e00000 {\n\t\t\t\tlabel = \"config\";\n\t\t\t\treg = <0xe00000 0x50000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\t/* range 0xe50000 to 0xff0000 is empty in vendor\n\t\t\t * firmware, so we do not use it either\n\t\t\t */\n\n\t\t\tradio: partition@ff0000 {\n\t\t\t\tlabel = \"radio\";\n\t\t\t\treg = <0xff0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"rgmii2\", \"wdt\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\twifi@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&radio 0x0>;\n\t\tnvmem-cells = <&macaddr_config_10008>;\n\t\tnvmem-cell-names = \"mac-address\";\n\t\tmac-address-increment = <1>;\n\t\tieee80211-freq-limit = <2400000 2500000>;\n\t};\n};\n\n&pcie1 {\n\twifi@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&radio 0x8000>;\n\t\tnvmem-cells = <&macaddr_config_10008>;\n\t\tnvmem-cell-names = \"mac-address\";\n\t\tmac-address-increment = <2>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\t};\n};\n\n&ethernet {\n\tpinctrl-0 = <&mdio_pins>, <&rgmii1_pins>;\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_config_10008>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&switch0 {\n\tports {\n\t\tport@0 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan\";\n\t\t};\n\t};\n};\n\n&config {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_config_10008: macaddr@10008 {\n\t\treg = <0x10008 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_tplink_tl-wpa8631p-v3.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"tplink,tl-wpa8631p-v3\", \"mediatek,mt7621-soc\";\n\tmodel = \"TP-Link TL-WPA8631P v3\";\n\n\taliases {\n\t\tlabel-mac-device = &gmac0;\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tgpios = <&gpio 31 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\tled {\n\t\t\tlabel = \"led\";\n\t\t\tlinux,code = <KEY_LIGHTS_TOGGLE>;\n\t\t\tgpios = <&gpio 30 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\tpair {\n\t\t\tlabel = \"pair\";\n\t\t\tlinux,code = <BTN_1>;\n\t\t\tgpios = <&gpio 32 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\twifi {\n\t\t\tlabel = \"wifi\";\n\t\t\tlinux,code = <KEY_RFKILL>;\n\t\t\tgpios = <&gpio 33 GPIO_ACTIVE_LOW>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan {\n\t\t\tlabel = \"green:lan\";\n\t\t\tgpios = <&gpio 29 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twifi2g {\n\t\t\tlabel = \"green:wifi2g\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\twifi5g {\n\t\t\tlabel = \"green:wifi5g\";\n\t\t\tgpios = <&gpio 24 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\t};\n\n\tgpio-export {\n\t\tcompatible = \"gpio-export\";\n\n\t\tled_control {\n\t\t\tgpio-export,name = \"tp-link:led:control\";\n\t\t\tgpio-export,output = <0>;\n\t\t\tgpios = <&gpio 25 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x20000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tcompatible = \"tplink,firmware\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x20000 0x710000>;\n\t\t\t};\n\n\t\t\tconfig: partition@730000 {\n\t\t\t\tlabel = \"config\";\n\t\t\t\treg = <0x730000 0xc0000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tradio: partition@7f0000 {\n\t\t\t\tlabel = \"radio\";\n\t\t\t\treg = <0x7f0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"rgmii2\", \"wdt\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\twifi@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&radio 0x0>;\n\t\tnvmem-cells = <&macaddr_config_2008>;\n\t\tnvmem-cell-names = \"mac-address\";\n\t\tieee80211-freq-limit = <2400000 2500000>;\n\t};\n};\n\n&pcie1 {\n\twifi@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&radio 0x8000>;\n\t\tnvmem-cells = <&macaddr_config_2008>;\n\t\tnvmem-cell-names = \"mac-address\";\n\t\tmac-address-increment = <1>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\t};\n};\n\n&ethernet {\n\tpinctrl-0 = <&mdio_pins>, <&rgmii1_pins>;\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_config_2008>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&switch0 {\n\tports {\n\t\tport@0 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"plc0\";\n\t\t};\n\n\t\tport@1 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan1\";\n\t\t};\n\n\t\tport@2 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan2\";\n\t\t};\n\n\t\tport@3 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan3\";\n\t\t};\n\t};\n};\n\n&config {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_config_2008: macaddr@2008 {\n\t\treg = <0x2008 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_ubnt_edgerouter-x-sfp.dts",
    "content": "#include \"mt7621_ubnt_edgerouter-x.dtsi\"\n\n/ {\n\tmodel = \"Ubiquiti EdgeRouter X SFP\";\n\tcompatible = \"ubnt,edgerouter-x-sfp\", \"mediatek,mt7621-soc\";\n\n\tsfp_eth5: sfp_eth5 {\n\t\tcompatible = \"sff,sfp\";\n\t\ti2c-bus = <&i2c>;\n\t\tmod-def0-gpio = <&expander0 5 GPIO_ACTIVE_LOW>;\n\t\tmaximum-power-milliwatt = <1000>;\n\t};\n};\n\n&i2c {\n\tstatus = \"okay\";\n\n\t/*\n\t * PCA9655 GPIO expander\n\t *  0-POE power port eth0\n\t *  1-POE power port eth1\n\t *  2-POE power port eth2\n\t *  3-POE power port eth3\n\t *  4-POE power port eth4\n\t *  5-SFP_MOD_DEF0#\n\t *  6-\n\t *  7-\n\t *  8-Pull up to VCC\n\t *  9-Pull down to GND\n\t * 10-Pull down to GND\n\t * 11-Pull down to GND\n\t * 12-Pull down to GND\n\t * 13-Pull down to GND\n\t * 14-Pull down to GND\n\t * 15-Pull down to GND\n\t */\n\texpander0: pca9555@25 {\n\t\tcompatible = \"nxp,pca9555\";\n\t\tinterrupt-parent = <&gpio>;\n\t\tinterrupts = <8 IRQ_TYPE_EDGE_FALLING>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t\treg = <0x25>;\n\t};\n};\n\n&gpio {\n\tsfp_i2c_clk_gate {\n\t\tgpio-hog;\n\t\tgpios = <7 GPIO_ACTIVE_LOW>;\n\t\toutput-high;\n\t};\n};\n\n&mdio {\n\tephy7: ethernet-phy@7 {\n\t\treg = <7>;\n\t\tsfp = <&sfp_eth5>;\n\t};\n};\n\n&switch0 {\n\tports {\n\t\tport@5 {\n\t\t\treg = <5>;\n\t\t\tlabel = \"eth5\";\n\t\t\tphy-handle = <&ephy7>;\n\t\t\tphy-mode = \"rgmii-rxid\";\n\t\t\tnvmem-cells = <&macaddr_factory_22>;\n\t\t\tnvmem-cell-names = \"mac-address\";\n\t\t\tmac-address-increment = <5>;\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_ubnt_edgerouter-x.dts",
    "content": "#include \"mt7621_ubnt_edgerouter-x.dtsi\"\n\n/ {\n\tmodel = \"Ubiquiti EdgeRouter X\";\n\tcompatible = \"ubnt,edgerouter-x\", \"mediatek,mt7621-soc\";\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_ubnt_edgerouter-x.dtsi",
    "content": "#include \"mt7621.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\taliases {\n\t\tlabel-mac-device = &gmac0;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n};\n\n&ethernet {\n\tpinctrl-0 = <&mdio_pins>, <&rgmii1_pins>;\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_factory_22>;\n\tnvmem-cell-names = \"mac-address\";\n\tlabel = \"dsa\";\n};\n\n&switch0 {\n\tports {\n\t\tport@0 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"eth0\";\n\t\t};\n\n\t\tport@1 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"eth1\";\n\t\t\tnvmem-cells = <&macaddr_factory_22>;\n\t\t\tnvmem-cell-names = \"mac-address\";\n\t\t\tmac-address-increment = <1>;\n\t\t};\n\n\t\tport@2 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"eth2\";\n\t\t\tnvmem-cells = <&macaddr_factory_22>;\n\t\t\tnvmem-cell-names = \"mac-address\";\n\t\t\tmac-address-increment = <2>;\n\t\t};\n\n\t\tport@3 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"eth3\";\n\t\t\tnvmem-cells = <&macaddr_factory_22>;\n\t\t\tnvmem-cell-names = \"mac-address\";\n\t\t\tmac-address-increment = <3>;\n\t\t};\n\n\t\tport@4 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"eth4\";\n\t\t\tnvmem-cells = <&macaddr_factory_22>;\n\t\t\tnvmem-cell-names = \"mac-address\";\n\t\t\tmac-address-increment = <4>;\n\t\t};\n\t};\n};\n\n&nand {\n\tstatus = \"okay\";\n\n\tpartitions {\n\t\tcompatible = \"fixed-partitions\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"u-boot\";\n\t\t\treg = <0x0 0x80000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@80000 {\n\t\t\tlabel = \"u-boot-env\";\n\t\t\treg = <0x80000 0x60000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tfactory: partition@e0000 {\n\t\t\tlabel = \"factory\";\n\t\t\treg = <0xe0000 0x60000>;\n\t\t};\n\n\t\tpartition@140000 {\n\t\t\tlabel = \"kernel1\";\n\t\t\treg = <0x140000 0x300000>;\n\t\t};\n\n\t\tpartition@440000 {\n\t\t\tlabel = \"kernel2\";\n\t\t\treg = <0x440000 0x300000>;\n\t\t};\n\n\t\tpartition@740000 {\n\t\t\tlabel = \"ubi\";\n\t\t\treg = <0x740000 0xf7c0000>;\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"uart2\", \"uart3\", \"pcie\", \"rgmii2\", \"jtag\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&spi0 {\n\t/*\n\t * This board has 2Mb spi flash soldered in and visible\n\t * from manufacturer's firmware.\n\t * But this SoC shares spi and nand pins,\n\t * and current driver doesn't handle this sharing well\n\t */\n\tstatus = \"disabled\";\n\n\tflash@1 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <1>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"spi\";\n\t\t\t\treg = <0x0 0x200000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&xhci {\n\tstatus = \"disabled\";\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_22: macaddr@22 {\n\t\treg = <0x22 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_ubnt_unifi-6-lite.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621_ubnt_unifi.dtsi\"\n\n/ {\n\tcompatible = \"ubnt,unifi-6-lite\", \"mediatek,mt7621-soc\";\n\tmodel = \"Ubiquiti UniFi 6 Lite\";\n\n\tchosen {\n\t\tbootargs-override = \"console=ttyS0,115200\";\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <50000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x60000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@60000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x60000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@70000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x70000 0x40000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\teeprom: partition@b0000 {\n\t\t\t\tlabel = \"eeprom\";\n\t\t\t\treg = <0xb0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@c0000 {\n\t\t\t\tlabel = \"bs\";\n\t\t\t\treg = <0xc0000 0x10000>;\n\t\t\t};\n\n\t\t\tpartition@d0000 {\n\t\t\t\tlabel = \"cfg\";\n\t\t\t\treg = <0xd0000 0x100000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@1d0000 {\n\t\t\t\tcompatible = \"denx,fit\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x1d0000 0xf10000>;\n\t\t\t};\n\n\t\t\tpartition@10e0000 {\n\t\t\t\tlabel = \"kernel1\";\n\t\t\t\treg = <0x10e0000 0xf10000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_eeprom_0>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wlan_2g {\n\tmediatek,mtd-eeprom = <&factory 0x0>;\n\n\tnvmem-cells = <&macaddr_eeprom_0>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wlan_5g {\n\tmediatek,mtd-eeprom = <&factory 0x20000>;\n\n\tnvmem-cells = <&macaddr_eeprom_6>;\n\tnvmem-cell-names = \"mac-address\";\n\n\t/* This is a workaround.\n\t *\n\t * Ubiquiti uses a +2 offset in the first octet relative\n\t * to the 2.4 GHz WMAC. Other octets are identical.\n\t *\n\t * The vendor firmware increases the last octet by 2 for each\n\t * VAP.\n\t *\n\t * This is in conflict on how mac80211 addresses subsequent VAPs.\n\t * mac80211 increases the first octet by two for each VAP, leading\n\t * to conflicting MAC addresses for subsequent interfaces.\n\t */\n\tmac-address-increment = <1>;\n\n\tieee80211-freq-limit = <5000000 6000000>;\n};\n\n&eeprom {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_eeprom_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n\n\tmacaddr_eeprom_6: macaddr@6 {\n\t\treg = <0x6 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_ubnt_unifi-nanohd.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621_ubnt_unifi.dtsi\"\n\n/ {\n\tcompatible = \"ubnt,unifi-nanohd\", \"mediatek,mt7621-soc\";\n\tmodel = \"Ubiquiti UniFi nanoHD\";\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <50000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x60000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@60000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x60000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@70000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x70000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\teeprom: partition@80000 {\n\t\t\t\tlabel = \"eeprom\";\n\t\t\t\treg = <0x80000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@90000 {\n\t\t\t\tlabel = \"bs\";\n\t\t\t\treg = <0x90000 0x10000>;\n\t\t\t};\n\n\t\t\tpartition@a0000 {\n\t\t\t\tlabel = \"cfg\";\n\t\t\t\treg = <0xa0000 0x100000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@1a0000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x1a0000 0xf30000>;\n\t\t\t};\n\n\t\t\tpartition@10d0000 {\n\t\t\t\tlabel = \"kernel1\";\n\t\t\t\treg = <0x10d0000 0xf30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_eeprom_0>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wlan_2g {\n\tmediatek,mtd-eeprom = <&factory 0x0>;\n};\n\n&wlan_5g {\n\tmediatek,mtd-eeprom = <&factory 0x8000>;\n};\n\n&eeprom {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_eeprom_0: macaddr@0 {\n\t\treg = <0x0 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_ubnt_unifi.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\taliases {\n\t\tled-boot = &led_white;\n\t\tled-failsafe = &led_white;\n\t\tled-running = &led_blue;\n\t\tled-upgrade = &led_blue;\n\t\tlabel-mac-device = &gmac0;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200\";\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_blue: dome_blue {\n\t\t\tlabel = \"blue:dome\";\n\t\t\tgpios = <&gpio 3 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tled_white: dome_white {\n\t\t\tlabel = \"white:dome\";\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\twlan_2g: wifi@0,0 {\n\t\treg = <0x0 0 0 0 0>;\n\t};\n};\n\n&pcie1 {\n\twlan_5g: wifi@0,0 {\n\t\treg = <0x0 0 0 0 0>;\n\t};\n};\n\n&switch0 {\n\tports {\n\t\tport@0 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan\";\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"uart2\";\n\t\tfunction = \"gpio\";\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_ubnt_usw-flex.dts",
    "content": "#include \"mt7621.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"Ubiquiti UniFi Switch Flex\";\n\tcompatible = \"ubnt,usw-flex\", \"mediatek,mt7621-soc\";\n\n\taliases {\n\t\tled-boot = &led_white;\n\t\tled-failsafe = &led_white;\n\t\tled-running = &led_blue;\n\t\tled-upgrade = &led_blue;\n\t\tlabel-mac-device = &gmac0;\n\t};\n\n\tchosen {\n\t\tbootargs-override = \"console=ttyS0,115200\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_blue: status_blue {\n\t\t\tlabel = \"blue:status\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tled_white: status_white {\n\t\t\tlabel = \"white:status\";\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n\n\ti2c-gpio {\n\t\tcompatible = \"i2c-gpio\";\n\n\t\tsda-gpios = <&gpio 3 GPIO_ACTIVE_HIGH>;\n\t\tscl-gpios = <&gpio 4 GPIO_ACTIVE_HIGH>;\n\n\t\ti2c-gpio,delay-us = <50>;\n\n\t\t/* Microsemi PD69104B1 PSE controller */\n\t};\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_eeprom>;\n\tnvmem-cell-names = \"mac-address\";\n\tlabel = \"dsa\";\n};\n\n&switch0 {\n\tports {\n\t\tport@0 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan5\";\n\t\t};\n\n\t\tport@1 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan4\";\n\t\t};\n\n\t\tport@2 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan3\";\n\t\t};\n\n\t\tport@3 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan2\";\n\t\t};\n\n\t\tport@4 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan1\";\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"uart2\", \"uart3\", \"jtag\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <30000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x60000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@60000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x60000 0x10000>;\n\t\t\t};\n\n\t\t\tpartition@70000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x70000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpart_eeprom: partition@80000 {\n\t\t\t\tcompatible = \"nvmem-cells\";\n\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\n\t\t\t\tlabel = \"eeprom\";\n\t\t\t\treg = <0x80000 0x10000>;\n\t\t\t\tread-only;\n\n\t\t\t\tmacaddr_eeprom: macaddr@0 {\n\t\t\t\t\treg = <0x0 0x6>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tpartition@90000 {\n\t\t\t\tlabel = \"bs\";\n\t\t\t\treg = <0x90000 0x10000>;\n\t\t\t};\n\n\t\t\tpartition@a0000 {\n\t\t\t\tlabel = \"cfg\";\n\t\t\t\treg = <0xa0000 0x100000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@1a0000 {\n\t\t\t\tcompatible = \"denx,fit\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x1a0000 0x730000>;\n\t\t\t};\n\n\t\t\tpartition@8d0000 {\n\t\t\t\tlabel = \"kernel1\";\n\t\t\t\treg = <0x8d0000 0x730000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&xhci {\n\tstatus = \"disabled\";\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_unielec_u7621-01-16m.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621_unielec_u7621-01.dtsi\"\n\n/ {\n\tcompatible = \"unielec,u7621-01-16m\", \"unielec,u7621-01\", \"mediatek,mt7621-soc\";\n\tmodel = \"UniElec U7621-01 (16M flash)\";\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <14000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"bootloader\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"config\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0xfb0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_factory_e000>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wan {\n\tnvmem-cells = <&macaddr_factory_e000>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <1>;\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_e000: macaddr@e000 {\n\t\treg = <0xe000 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_unielec_u7621-01.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"unielec,u7621-01\", \"mediatek,mt7621-soc\";\n\n\taliases {\n\t\tled-boot = &led_status;\n\t\tled-failsafe = &led_status;\n\t\tled-running = &led_status;\n\t\tled-upgrade = &led_status;\n\t};\n\n\tgpio-export {\n\t\tcompatible = \"gpio-export\";\n\t\t#size-cells = <0>;\n\n\t\tmodem_reset {\n\t\t\tgpio-export,name = \"modem_reset\";\n\t\t\tgpio-export,output = <1>;\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_status: status {\n\t\t\tlabel = \"green:status\";\n\t\t\tgpios = <&gpio 10 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\twifi@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x0000>;\n\t\tieee80211-freq-limit = <2400000 2500000>;\n\t};\n};\n\n&pcie1 {\n\twifi@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\n\t\tled {\n\t\t\tled-sources = <2>;\n\t\t};\n\t};\n};\n\n&switch0 {\n\tports {\n\t\twan: port@0 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"wan\";\n\t\t};\n\n\t\tport@1 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan1\";\n\t\t};\n\n\t\tport@2 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan2\";\n\t\t};\n\n\t\tport@3 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan3\";\n\t\t};\n\n\t\tport@4 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan4\";\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"jtag\", \"uart2\", \"wdt\";\n\t\tfunction = \"gpio\";\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_unielec_u7621-06-16m.dts",
    "content": "// SPDX-License-Identifier: BSD-3-Clause\n/*\n *  Copyright(c) 2017 Kristian Evensen <kristian.evensen@gmail.com>.\n *  Copyright(c) 2017 Piotr Dymacz <pepe2k@gmail.com>.\n *  All rights reserved.\n */\n\n#include \"mt7621_unielec_u7621-06.dtsi\"\n\n/ {\n\tcompatible = \"unielec,u7621-06-16m\", \"unielec,u7621-06\", \"mediatek,mt7621-soc\";\n\tmodel = \"UniElec U7621-06 (16M flash)\";\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <14000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"bootloader\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"config\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfirmware: partition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0xfb0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_factory_e000>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wan {\n\tnvmem-cells = <&macaddr_factory_e000>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <1>;\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_e000: macaddr@e000 {\n\t\treg = <0xe000 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_unielec_u7621-06-64m.dts",
    "content": "// SPDX-License-Identifier: BSD-3-Clause\n/*\n *  Copyright(c) 2017 Kristian Evensen <kristian.evensen@gmail.com>.\n *  Copyright(c) 2017 Piotr Dymacz <pepe2k@gmail.com>.\n *  Copyright(c) 2018 Nishant Sharma <codemarauder@gmail.com>.\n *  All rights reserved.\n */\n\n#include \"mt7621_unielec_u7621-06.dtsi\"\n\n/ {\n\tcompatible = \"unielec,u7621-06-64m\", \"unielec,u7621-06\", \"mediatek,mt7621-soc\";\n\tmodel = \"UniElec U7621-06 (64M flash)\";\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"bootloader\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"config\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfirmware: partition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x3fb0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_factory_e000>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wan {\n\tnvmem-cells = <&macaddr_factory_e000>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <1>;\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_e000: macaddr@e000 {\n\t\treg = <0xe000 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_unielec_u7621-06.dtsi",
    "content": "// SPDX-License-Identifier: BSD-3-Clause\n/*\n *  Copyright(c) 2017 Kristian Evensen <kristian.evensen@gmail.com>.\n *  Copyright(c) 2017 Piotr Dymacz <pepe2k@gmail.com>.\n *  All rights reserved.\n */\n\n#include \"mt7621.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"unielec,u7621-06\", \"mediatek,mt7621-soc\";\n\n\taliases {\n\t\tled-boot = &led_status;\n\t\tled-failsafe = &led_status;\n\t\tled-running = &led_status;\n\t\tled-upgrade = &led_status;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200\";\n\t};\n\n\tgpio-export {\n\t\tcompatible = \"gpio-export\";\n\t\t#size-cells = <0>;\n\n\t\tmodem_reset {\n\t\t\tgpio-export,name = \"modem_reset\";\n\t\t\tgpio-export,output = <1>;\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_status: status {\n\t\t\tlabel = \"green:status\";\n\t\t\tgpios = <&gpio 10 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled4 {\n\t\t\tlabel = \"green:led4\";\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tled5 {\n\t\t\tlabel = \"green:led5\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&sdhci {\n\tstatus = \"okay\";\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&switch0 {\n\tports {\n\t\tport@0 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan1\";\n\t\t};\n\n\t\tport@1 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan2\";\n\t\t};\n\n\t\tport@2 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan3\";\n\t\t};\n\n\t\tport@3 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan4\";\n\t\t};\n\n\t\twan: port@4 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"wan\";\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"jtag\", \"uart2\", \"wdt\";\n\t\tfunction = \"gpio\";\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_wavlink_wl-wn531a6.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621_wavlink_wl-wn53xax.dtsi\"\n\n/ {\n\tcompatible = \"wavlink,wl-wn531a6\", \"mediatek,mt7621-soc\";\n\tmodel = \"Wavlink WL-WN531A6\";\n};\n\n&wifi0{\n\tieee80211-freq-limit = <2400000 2500000>;\n};\n\n&wifi1{\n\tieee80211-freq-limit = <5000000 6000000>;\n};\n\n&port0{\n\tlabel = \"lan1\";\n};\n\n&port1{\n\tlabel = \"lan2\";\n};\n\n&port2{\n\tlabel = \"lan3\";\n};\n\n&port3{\n\tlabel = \"lan4\";\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_wavlink_wl-wn533a8.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621_wavlink_wl-wn53xax.dtsi\"\n\n/ {\n\tcompatible = \"wavlink,wl-wn533a8\", \"mediatek,mt7621-soc\";\n\tmodel = \"Wavlink WL-WN533A8\";\n};\n\n&wifi0{\n\tieee80211-freq-limit = <2400000 5490000>;\n};\n\n&wifi1{\n\tieee80211-freq-limit = <5490000 6000000>;\n};\n\n&port0{\n\tlabel = \"lan4\";\n};\n\n&port1{\n\tlabel = \"lan3\";\n};\n\n&port2{\n\tlabel = \"lan2\";\n};\n\n&port3{\n\tlabel = \"lan1\";\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_wavlink_wl-wn53xax.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\taliases {\n\t\tled-boot = &led_status_red;\n\t\tled-failsafe = &led_status_red;\n\t\tled-running = &led_status_blue;\n\t\tled-upgrade = &led_status_red;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"Reset Button\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\ttouch { /* RH6015C touch sensor -> GPIO 14 */\n\t\t\tlabel = \"Touch Button\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_0>;\n\t\t};\n\n\t\tturbo {\n\t\t\tlabel = \"Turbo Button\";\n\t\t\tgpios = <&gpio 25 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_1>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"WPS Button\";\n\t\t\tgpios = <&gpio 24 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_status_blue: status_blue {\n\t\t\tlabel = \"blue:power\";\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tled_status_red: status_red {\n\t\t\tlabel = \"red:power\";\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\twifi2g {\n\t\t\tlabel = \"blue:wifi2g\";\n\t\t\tgpios = <&gpio 23 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\t};\n};\n\n&i2c {\n\tstatus = \"okay\";\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <40000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"config\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0xeb0000>;\n\t\t\t};\n\n\t\t\tpartition@f00000 {\n\t\t\t\tlabel = \"vendor\";\n\t\t\t\treg = <0xf00000 0x100000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\twifi0: mt76@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x0>;\n\t};\n};\n\n&pcie1 {\n\twifi1: mt76@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t};\n};\n\n&ethernet {\n\tpinctrl-0 = <&mdio_pins>, <&rgmii1_pins>;\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_factory_e000>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&switch0 {\n\tports {\n\t\tport0: port@0 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tport1: port@1 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tport2: port@2 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tport3: port@3 {\n\t\t\tstatus = \"okay\";\n\t\t};\n\n\t\tport@4 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"wan\";\n\t\t\tnvmem-cells = <&macaddr_factory_e006>;\n\t\t\tnvmem-cell-names = \"mac-address\";\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"rgmii2\", \"jtag\", \"wdt\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&uartlite2 {\n\tstatus = \"okay\";\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_e000: macaddr@e000 {\n\t\treg = <0xe000 0x6>;\n\t};\n\n\tmacaddr_factory_e006: macaddr@e006 {\n\t\treg = <0xe006 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_wevo_11acnas.dts",
    "content": "#include \"mt7621_wevo_w2914ns-v2.dtsi\"\n\n/ {\n\tcompatible = \"wevo,11acnas\", \"mediatek,mt7621-soc\";\n\tmodel = \"WeVO 11AC NAS Router\";\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_wevo_w2914ns-v2.dts",
    "content": "#include \"mt7621_wevo_w2914ns-v2.dtsi\"\n\n/ {\n\tcompatible = \"wevo,w2914ns-v2\", \"mediatek,mt7621-soc\";\n\tmodel = \"WeVO W2914NS v2\";\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_wevo_w2914ns-v2.dtsi",
    "content": "#include \"mt7621.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\taliases {\n\t\tlabel-mac-device = &wan;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tusb {\n\t\t\tlabel = \"green:usb\";\n\t\t\tgpios = <&gpio 27 GPIO_ACTIVE_LOW>;\n\t\t\ttrigger-sources = <&xhci_ehci_port1>, <&ehci_port2>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 29 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <80000000>;\n\t\tm25p,fast-read;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0xfb0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\twifi@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x0>;\n\n\t\tled {\n\t\t\tled-sources = <0>;\n\t\t\tled-active-low;\n\t\t};\n\t};\n};\n\n&pcie1 {\n\twifi@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\n\t\tled {\n\t\t\tled-sources = <2>;\n\t\t\tled-active-low;\n\t\t};\n\t};\n};\n\n&ethernet {\n\tpinctrl-0 = <&mdio_pins>, <&rgmii1_pins>;\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_factory_e000>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&switch0 {\n\tports {\n\t\tport@0 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan4\";\n\t\t};\n\n\t\tport@1 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan3\";\n\t\t};\n\n\t\tport@2 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan2\";\n\t\t};\n\n\t\tport@3 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan1\";\n\t\t};\n\t\twan: port@4 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"wan\";\n\t\t\tnvmem-cells = <&macaddr_factory_2e>;\n\t\t\tnvmem-cell-names = \"mac-address\";\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"wdt\", \"rgmii2\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_2e: macaddr@2e {\n\t\treg = <0x2e 0x6>;\n\t};\n\n\tmacaddr_factory_e000: macaddr@e000 {\n\t\treg = <0xe000 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_winstars_ws-wn583a6.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"winstars,ws-wn583a6\", \"mediatek,mt7621-soc\";\n\tmodel = \"Winstars WS-WN583A6\";\n\n\taliases {\n\t\tled-boot = &led_status_red;\n\t\tled-failsafe = &led_status_red;\n\t\tled-running = &led_status_blue;\n\t\tled-upgrade = &led_status_red;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tnight_light_white {\n\t\t\tlabel = \"white:night_light\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tled_status_blue: status_blue {\n\t\t\tlabel = \"blue:status\";\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tstatus_amber {\n\t\t\tlabel = \"amber:status\";\n\t\t\tgpios = <&gpio 24 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_status_red: status_red {\n\t\t\tlabel = \"red:status\";\n\t\t\tgpios = <&gpio 25 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <104000000>;\n\t\tm25p,fast-read;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"bootloader\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"config\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x7b0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\twifi@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x0000>;\n\t};\n};\n\n&pcie1 {\n\twifi@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t};\n};\n\n&ethernet {\n\tpinctrl-0 = <&mdio_pins>, <&rgmii1_pins>;\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_factory_e000>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&switch0 {\n\tports {\n\t\tport@0 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"wan\";\n\t\t\tnvmem-cells = <&macaddr_factory_e006>;\n\t\t\tnvmem-cell-names = \"mac-address\";\n\t\t};\n\n\t\tport@1 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan\";\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"jtag\", \"wdt\", \"rgmii2\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&xhci {\n\tstatus = \"disabled\";\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_e000: macaddr@e000 {\n\t\treg = <0xe000 0x6>;\n\t};\n\n\tmacaddr_factory_e006: macaddr@e006 {\n\t\treg = <0xe006 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_xiaomi_mi-router-3-pro.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"xiaomi,mi-router-3-pro\", \"mediatek,mt7621-soc\";\n\tmodel = \"Xiaomi Mi Router 3 Pro\";\n\n\taliases {\n\t\tled-boot = &led_status_yellow;\n\t\tled-failsafe = &led_status_red;\n\t\tled-running = &led_status_blue;\n\t\tled-upgrade = &led_status_yellow;\n\t\tlabel-mac-device = &gmac0;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200n8\";\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_status_red: status_red {\n\t\t\tlabel = \"red:status\";\n\t\t\tgpios = <&gpio 6 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_status_blue: status_blue {\n\t\t\tlabel = \"blue:status\";\n\t\t\tgpios = <&gpio 8 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_status_yellow: status_yellow {\n\t\t\tlabel = \"yellow:status\";\n\t\t\tgpios = <&gpio 10 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twan_amber {\n\t\t\tlabel = \"amber:wan\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"dsa-0.0:04:1Gbps\";\n\t\t};\n\n\t\tlan3_amber {\n\t\t\tlabel = \"amber:lan3\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"dsa-0.0:03:1Gbps\";\n\t\t};\n\n\t\tlan2_amber {\n\t\t\tlabel = \"amber:lan2\";\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"dsa-0.0:02:1Gbps\";\n\t\t};\n\n\t\tlan1_amber {\n\t\t\tlabel = \"amber:lan1\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"dsa-0.0:01:1Gbps\";\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\treg_usb_vbus: regulator {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"usb_vbus\";\n\t\tregulator-min-microvolt = <5000000>;\n\t\tregulator-max-microvolt = <5000000>;\n\t\tgpio = <&gpio 12 GPIO_ACTIVE_HIGH>;\n\t\tenable-active-high;\n\t};\n};\n\n&xhci {\n\tvbus-supply = <&reg_usb_vbus>;\n};\n\n&nand {\n\tstatus = \"okay\";\n\n\tpartitions {\n\t\tcompatible = \"fixed-partitions\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"Bootloader\";\n\t\t\treg = <0x0 0x40000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@40000 {\n\t\t\tlabel = \"Config\";\n\t\t\treg = <0x40000 0x40000>;\n\t\t};\n\n\t\tpartition@80000 {\n\t\t\tlabel = \"Bdata\";\n\t\t\treg = <0x80000 0x40000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tfactory: partition@c0000 {\n\t\t\tlabel = \"factory\";\n\t\t\treg = <0x0c0000 0x40000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@100000 {\n\t\t\tlabel = \"crash\";\n\t\t\treg = <0x100000 0x40000>;\n\t\t};\n\n\t\tpartition@140000 {\n\t\t\tlabel = \"crash_syslog\";\n\t\t\treg = <0x140000 0x80000>;\n\t\t};\n\n\t\tpartition@1c0000 {\n\t\t\tlabel = \"reserved0\";\n\t\t\treg = <0x1c0000 0x40000>;\n\t\t\tread-only;\n\t\t};\n\n\t\t/* We keep stock xiaomi firmware (kernel0) here */\n\t\tpartition@200000 {\n\t\t\tlabel = \"kernel_stock\";\n\t\t\treg = <0x200000 0x400000>;\n\t\t};\n\n\t\tpartition@600000 {\n\t\t\tlabel = \"kernel\";\n\t\t\treg = <0x600000 0x400000>;\n\t\t};\n\n\t\tpartition@a00000 {\n\t\t\tlabel = \"ubi\";\n\t\t\treg = <0xa00000 0xf580000>;\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\twifi@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x0000>;\n\t\tieee80211-freq-limit = <2400000 2500000>;\n\t};\n};\n\n&pcie1 {\n\twifi@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\t};\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_factory_e006>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&switch0 {\n\tports {\n\t\tport@1 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan3\";\n\t\t};\n\n\t\tport@2 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan2\";\n\t\t};\n\n\t\tport@3 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan1\";\n\t\t};\n\n\t\tport@4 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"wan\";\n\t\t\tnvmem-cells = <&macaddr_factory_e000>;\n\t\t\tnvmem-cell-names = \"mac-address\";\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"jtag\", \"uart2\", \"uart3\", \"wdt\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_e000: macaddr@e000 {\n\t\treg = <0xe000 0x6>;\n\t};\n\n\tmacaddr_factory_e006: macaddr@e006 {\n\t\treg = <0xe006 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_xiaomi_mi-router-3g-v2.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621_xiaomi_mi-router-4a-3g-v2.dtsi\"\n\n/ {\n\tcompatible = \"xiaomi,mi-router-3g-v2\", \"mediatek,mt7621-soc\";\n\tmodel = \"Xiaomi Mi Router 3G v2\";\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_xiaomi_mi-router-3g.dts",
    "content": "#include \"mt7621_xiaomi_nand_128m.dtsi\"\n\n/ {\n\tcompatible = \"xiaomi,mi-router-3g\", \"mediatek,mt7621-soc\";\n\tmodel = \"Xiaomi Mi Router 3G\";\n\n\taliases {\n\t\tled-boot = &led_status_yellow;\n\t\tled-failsafe = &led_status_red;\n\t\tled-running = &led_status_blue;\n\t\tled-upgrade = &led_status_yellow;\n\t\tlabel-mac-device = &gmac0;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_status_red: status_red {\n\t\t\tlabel = \"red:status\";\n\t\t\tgpios = <&gpio 6 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_status_blue: status_blue {\n\t\t\tlabel = \"blue:status\";\n\t\t\tgpios = <&gpio 8 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_status_yellow: status_yellow {\n\t\t\tlabel = \"yellow:status\";\n\t\t\tgpios = <&gpio 10 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twan_amber {\n\t\t\tlabel = \"amber:wan\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"dsa-0.0:01:1Gbps\";\n\t\t};\n\n\t\tlan1_amber {\n\t\t\tlabel = \"amber:lan1\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"dsa-0.0:03:1Gbps\";\n\t\t};\n\n\t\tlan2_amber {\n\t\t\tlabel = \"amber:lan2\";\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"dsa-0.0:02:1Gbps\";\n\t\t};\n\t};\n\n\treg_usb_vbus: regulator {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-name = \"usb_vbus\";\n\t\tregulator-min-microvolt = <5000000>;\n\t\tregulator-max-microvolt = <5000000>;\n\t\tgpio = <&gpio 12 GPIO_ACTIVE_HIGH>;\n\t\tenable-active-high;\n\t};\n};\n\n&xhci {\n\tvbus-supply = <&reg_usb_vbus>;\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\twifi@0,0 {\n\t\tcompatible = \"pci14c3,7603\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x0000>;\n\t\tieee80211-freq-limit = <2400000 2500000>;\n\t};\n};\n\n&pcie1 {\n\twifi@0,0 {\n\t\tcompatible = \"pci14c3,7662\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\t};\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_factory_e006>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&switch0 {\n\tports {\n\t\tport@1 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"wan\";\n\t\t\tnvmem-cells = <&macaddr_factory_e000>;\n\t\t\tnvmem-cell-names = \"mac-address\";\n\t\t};\n\n\t\tport@2 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan2\";\n\t\t};\n\n\t\tport@3 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan1\";\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"jtag\", \"uart2\", \"uart3\", \"wdt\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_e000: macaddr@e000 {\n\t\treg = <0xe000 0x6>;\n\t};\n\n\tmacaddr_factory_e006: macaddr@e006 {\n\t\treg = <0xe006 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_xiaomi_mi-router-4.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621_xiaomi_nand_128m.dtsi\"\n\n/ {\n\tcompatible = \"xiaomi,mi-router-4\", \"mediatek,mt7621-soc\";\n\tmodel = \"Xiaomi Mi Router 4\";\n\n\taliases {\n\t\tled-boot = &led_status_yellow;\n\t\tled-failsafe = &led_status_red;\n\t\tled-running = &led_status_blue;\n\t\tled-upgrade = &led_status_yellow;\n\t\tlabel-mac-device = &gmac0;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_status_red: status_red {\n\t\t\tlabel = \"red:status\";\n\t\t\tgpios = <&gpio 6 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_status_blue: status_blue {\n\t\t\tlabel = \"blue:status\";\n\t\t\tgpios = <&gpio 8 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_status_yellow: status_yellow {\n\t\t\tlabel = \"yellow:status\";\n\t\t\tgpios = <&gpio 10 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&keys {\n\tminet {\n\t\tlabel = \"minet\";\n\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\twifi@0,0 {\n\t\tcompatible = \"pci14c3,7603\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x0000>;\n\t\tieee80211-freq-limit = <2400000 2500000>;\n\t};\n};\n\n&pcie1 {\n\twifi@0,0 {\n\t\tcompatible = \"pci14c3,7662\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\t};\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_factory_e000>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&switch0 {\n\tports {\n\t\tport@1 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan2\";\n\t\t};\n\n\t\tport@2 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan1\";\n\t\t};\n\n\t\tport@4 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"wan\";\n\t\t\tnvmem-cells = <&macaddr_factory_e006>;\n\t\t\tnvmem-cell-names = \"mac-address\";\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"jtag\", \"uart2\", \"uart3\", \"wdt\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_e000: macaddr@e000 {\n\t\treg = <0xe000 0x6>;\n\t};\n\n\tmacaddr_factory_e006: macaddr@e006 {\n\t\treg = <0xe006 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_xiaomi_mi-router-4a-3g-v2.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\taliases {\n\t\tled-boot = &led_status_yellow;\n\t\tled-failsafe = &led_status_yellow;\n\t\tled-running = &led_status_blue;\n\t\tled-upgrade = &led_status_yellow;\n\t\tlabel-mac-device = &wan;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200n8\";\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_status_blue: status_blue {\n\t\t\tlabel = \"blue:status\";\n\t\t\tgpios = <&gpio 8 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_status_yellow: status_yellow {\n\t\t\tlabel = \"yellow:status\";\n\t\t\tgpios = <&gpio 10 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <50000000>;\n\t\tm25p,fast-read;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"Bdata\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@50000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x50000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@60000 {\n\t\t\t\tlabel = \"crash\";\n\t\t\t\treg = <0x60000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@70000 {\n\t\t\t\tlabel = \"cfg_bak\";\n\t\t\t\treg = <0x70000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@80000 {\n\t\t\t\tlabel = \"overlay\";\n\t\t\t\treg = <0x80000 0x100000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfirmware: partition@180000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x180000 0xe80000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\twifi@0,0 {\n\t\tcompatible = \"pci14c3,7662\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\t};\n};\n\n&pcie1 {\n\twifi@0,0 {\n\t\tcompatible = \"pci14c3,7603\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x0000>;\n\t\tieee80211-freq-limit = <2400000 2500000>;\n\t};\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_factory_e000>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&switch0 {\n\tports {\n\t\tport@2 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan2\";\n\t\t};\n\n\t\tport@3 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan1\";\n\t\t};\n\n\t\twan: port@4 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"wan\";\n\t\t\tnvmem-cells = <&macaddr_factory_e006>;\n\t\t\tnvmem-cell-names = \"mac-address\";\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"jtag\", \"uart2\", \"uart3\", \"wdt\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_e000: macaddr@e000 {\n\t\treg = <0xe000 0x6>;\n\t};\n\n\tmacaddr_factory_e006: macaddr@e006 {\n\t\treg = <0xe006 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_xiaomi_mi-router-4a-gigabit.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621_xiaomi_mi-router-4a-3g-v2.dtsi\"\n\n/ {\n\tcompatible = \"xiaomi,mi-router-4a-gigabit\", \"mediatek,mt7621-soc\";\n\tmodel = \"Xiaomi Mi Router 4A Gigabit Edition\";\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_xiaomi_mi-router-ac2100.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621_xiaomi_router-ac2100.dtsi\"\n\n/ {\n\tcompatible = \"xiaomi,mi-router-ac2100\", \"mediatek,mt7621-soc\";\n\tmodel = \"Xiaomi Mi Router AC2100\";\n\n\taliases {\n\t\tled-boot = &led_status_yellow;\n\t\tled-failsafe = &led_status_yellow;\n\t\tled-running = &led_status_blue;\n\t\tled-upgrade = &led_status_blue;\n\t\tlabel-mac-device = &gmac0;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twan_yellow {\n\t\t\tlabel = \"yellow:wan\";\n\t\t\tgpios = <&gpio 6 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twan_blue {\n\t\t\tlabel = \"blue:wan\";\n\t\t\tgpios = <&gpio 8 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_status_yellow: status_yellow {\n\t\t\tlabel = \"yellow:status\";\n\t\t\tgpios = <&gpio 10 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_status_blue: status_blue {\n\t\t\tlabel = \"blue:status\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_xiaomi_mi-router-cr6606.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621_xiaomi_mi-router-cr660x.dtsi\"\n\n/ {\n\tcompatible = \"xiaomi,mi-router-cr6606\", \"mediatek,mt7621-soc\";\n\tmodel = \"Xiaomi Mi Router CR6606\";\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_xiaomi_mi-router-cr6608.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621_xiaomi_mi-router-cr660x.dtsi\"\n\n/ {\n\tcompatible = \"xiaomi,mi-router-cr6608\", \"mediatek,mt7621-soc\";\n\tmodel = \"Xiaomi Mi Router CR6608\";\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_xiaomi_mi-router-cr6609.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621_xiaomi_mi-router-cr660x.dtsi\"\n\n/ {\n\tcompatible = \"xiaomi,mi-router-cr6609\", \"mediatek,mt7621-soc\";\n\tmodel = \"Xiaomi Mi Router CR6609\";\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_xiaomi_mi-router-cr660x.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\taliases {\n\t\tled-boot = &led_sys_yellow;\n\t\tled-failsafe = &led_sys_yellow;\n\t\tled-running = &led_sys_blue;\n\t\tled-upgrade = &led_sys_yellow;\n\t\tlabel-mac-device = &gmac0;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200n8\";\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_sys_yellow: sys_yellow {\n\t\t\tlabel = \"yellow:sys\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_sys_blue: sys_blue {\n\t\t\tlabel = \"blue:sys\";\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tnet_yellow {\n\t\t\tlabel = \"yellow:net\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tnet_blue {\n\t\t\tlabel = \"blue:net\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n};\n\n&nand {\n\tstatus = \"okay\";\n\n\tpartitions {\n\t\tcompatible = \"fixed-partitions\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"Bootloader\";\n\t\t\treg = <0x0 0x80000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@80000 {\n\t\t\tlabel = \"Nvram\";\n\t\t\treg = <0x80000 0x40000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@c0000 {\n\t\t\tlabel = \"Bdata\";\n\t\t\treg = <0xc0000 0x40000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tfactory: partition@100000 {\n\t\t\tlabel = \"Factory\";\n\t\t\treg = <0x100000 0x80000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@180000 {\n\t\t\tlabel = \"crash\";\n\t\t\treg = <0x180000 0x40000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@1c0000 {\n\t\t\tlabel = \"crash_log\";\n\t\t\treg = <0x1c0000 0x40000>;\n\t\t\tread-only;\n\t\t};\n\n\t\t/* \"kernel\" and \"ubi\" partition is the result of\n\t\t * squashing next consecutive stock partitions:\n\t\t * 1. firmware  0x0200000 - 0x2000000 (Stock firmware 0)\n\t\t * 2. firmware1 0x2000000 - 0x3e00000 (Stock firmware 1)\n\t\t * 3. overlay   0x3e00000 - 0x7000000 (Stock fw Ubi overlay)\n\t\t * 4. obr       0x7000000 - 0x8000000 (Unallocated?)\n\t\t */\n\n\t\tpartition@200000 {\n\t\t\tlabel = \"kernel\";\n\t\t\treg = <0x200000 0x400000>;\n\t\t};\n\n\t\tpartition@600000 {\n\t\t\tlabel = \"ubi\";\n\t\t\treg = <0x600000 0x7980000>;\n\t\t};\n\n\t\t/*\n\t\t * Leave 512 KiB for the bad block table\n\t\t */\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie1 {\n\twifi@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x0>;\n\t};\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_factory_3fff4>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&switch0 {\n\tports {\n\t\tport@0 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan1\";\n\t\t};\n\n\t\tport@1 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan2\";\n\t\t};\n\n\t\tport@2 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan3\";\n\t\t};\n\n\t\tport@4 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"wan\";\n\t\t\tnvmem-cells = <&macaddr_factory_3fffa>;\n\t\t\tnvmem-cell-names = \"mac-address\";\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"jtag\", \"uart3\", \"wdt\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_3fff4: macaddr@3fff4 {\n\t\treg = <0x3fff4 0x6>;\n\t};\n\n\tmacaddr_factory_3fffa: macaddr@3fffa {\n\t\treg = <0x3fffa 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_xiaomi_nand_128m.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200n8\";\n\t};\n\n\tkeys: keys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n};\n\n&nand {\n\tstatus = \"okay\";\n\n\tpartitions {\n\t\tcompatible = \"fixed-partitions\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"Bootloader\";\n\t\t\treg = <0x0 0x80000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@80000 {\n\t\t\tlabel = \"Config\";\n\t\t\treg = <0x80000 0x40000>;\n\t\t};\n\n\t\tpartition@c0000 {\n\t\t\tlabel = \"Bdata\";\n\t\t\treg = <0xc0000 0x40000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tfactory: partition@100000 {\n\t\t\tlabel = \"factory\";\n\t\t\treg = <0x100000 0x40000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@140000 {\n\t\t\tlabel = \"crash\";\n\t\t\treg = <0x140000 0x40000>;\n\t\t};\n\n\t\tpartition@180000 {\n\t\t\tlabel = \"crash_syslog\";\n\t\t\treg = <0x180000 0x40000>;\n\t\t};\n\n\t\tpartition@1c0000 {\n\t\t\tlabel = \"reserved0\";\n\t\t\treg = <0x1c0000 0x40000>;\n\t\t\tread-only;\n\t\t};\n\n\t\t/* uboot expects to find kernels at 0x200000 & 0x600000\n\t\t * referred to as system 1 & system 2 respectively.\n\t\t * a kernel is considered suitable for handing control over\n\t\t * if its linux magic number exists & uImage CRC are correct.\n\t\t * If either of those conditions fail, a matching sys'n'_fail flag\n\t\t * is set in uboot env & a restart performed in the hope that the\n\t\t * alternate kernel is okay.\n\t\t * if neither kernel checksums ok and both are marked failed, system 2\n\t\t * is booted anyway.\n\t\t *\n\t\t * Note uboot's tftp flash install writes the transferred\n\t\t * image to both kernel partitions.\n\t\t */\n\n\t\t/* We keep stock xiaomi firmware (kernel0) here */\n\t\tpartition@200000 {\n\t\t\tlabel = \"kernel_stock\";\n\t\t\treg = <0x200000 0x400000>;\n\t\t};\n\n\t\tpartition@600000 {\n\t\t\tlabel = \"kernel\";\n\t\t\treg = <0x600000 0x400000>;\n\t\t};\n\n\t\t/* ubi partition is the result of squashing\n\t\t * next consecutive stock partitions:\n\t\t * - rootfs0 (rootfs partition for stock kernel0),\n\t\t * - rootfs1 (rootfs partition for stock failsafe kernel1),\n\t\t * - overlay (used as ubi overlay in stock fw)\n\t\t * resulting 117,5MiB space for packages.\n\t\t */\n\n\t\tpartition@a00000 {\n\t\t\tlabel = \"ubi\";\n\t\t\treg = <0xa00000 0x7580000>;\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_xiaomi_redmi-router-ac2100.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621_xiaomi_router-ac2100.dtsi\"\n\n/ {\n\tcompatible = \"xiaomi,redmi-router-ac2100\", \"mediatek,mt7621-soc\";\n\tmodel = \"Xiaomi Redmi Router AC2100\";\n\n\taliases {\n\t\tled-boot = &led_status_amber;\n\t\tled-failsafe = &led_status_amber;\n\t\tled-running = &led_status_white;\n\t\tled-upgrade = &led_status_white;\n\t\tlabel-mac-device = &gmac0;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_status_amber: status_amber {\n\t\t\tlabel = \"amber:status\";\n\t\t\tgpios = <&gpio 6 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_status_white: status_white {\n\t\t\tlabel = \"white:status\";\n\t\t\tgpios = <&gpio 8 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twan_amber {\n\t\t\tlabel = \"amber:wan\";\n\t\t\tgpios = <&gpio 10 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twan_white {\n\t\t\tlabel = \"white:wan\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_xiaomi_router-ac2100.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621_xiaomi_nand_128m.dtsi\"\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\twifi@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\t};\n};\n\n&pcie1 {\n\twifi@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x0000>;\n\t\tieee80211-freq-limit = <2400000 2500000>;\n\t};\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_factory_e000>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&switch0 {\n\tports {\n\t\tport@0 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"wan\";\n\t\t\tnvmem-cells = <&macaddr_factory_e006>;\n\t\t\tnvmem-cell-names = \"mac-address\";\n\t\t};\n\n\t\tport@2 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan1\";\n\t\t};\n\n\t\tport@3 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan2\";\n\t\t};\n\n\t\tport@4 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan3\";\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"uart2\", \"uart3\", \"wdt\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_e000: macaddr@e000 {\n\t\treg = <0xe000 0x6>;\n\t};\n\n\tmacaddr_factory_e006: macaddr@e006 {\n\t\treg = <0xe006 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_xiaoyu_xy-c5.dts",
    "content": "#include \"mt7621.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"xiaoyu,xy-c5\", \"mediatek,mt7621-soc\";\n\tmodel = \"XiaoYu XY-C5\";\n\n\taliases {\n\t\tled-boot = &led_sys;\n\t\tled-failsafe = &led_sys;\n\t\tled-running = &led_sys;\n\t\tled-upgrade = &led_sys;\n\t\tlabel-mac-device = &gmac0;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twork {\n\t\t\tlabel = \"green:work\";\n\t\t\tgpios = <&gpio 8 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_sys: sys {\n\t\t\tlabel = \"green:sys\";\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\t\tbroken-flash-reset;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x1fb0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&switch0 {\n\tports {\n\t\tport@0 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan1\";\n\t\t};\n\n\t\tport@1 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan2\";\n\t\t};\n\n\t\tport@2 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan3\";\n\t\t};\n\n\t\tport@3 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan4\";\n\t\t};\n\n\t\tport@4 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"wan\";\n\t\t\tnvmem-cells = <&macaddr_factory_4>;\n\t\t\tnvmem-cell-names = \"mac-address\";\n\t\t\tmac-address-increment = <1>;\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"uart3\", \"wdt\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_xzwifi_creativebox-v1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"xzwifi,creativebox-v1\", \"mediatek,mt7621-soc\";\n\tmodel = \"CreativeBox v1\";\n\n\taliases {\n\t\tled-boot = &led_sys;\n\t\tled-failsafe = &led_sys;\n\t\tled-running = &led_sys;\n\t\tled-upgrade = &led_sys;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200\";\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tpower {\n\t\t\tlabel = \"blue:power\";\n\t\t\tgpios = <&gpio 31 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\tled_sys: sys {\n\t\t\tlabel = \"blue:sys\";\n\t\t\tgpios = <&gpio 32 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tinternet {\n\t\t\tlabel = \"blue:internet\";\n\t\t\tgpios = <&gpio 29 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan2g {\n\t\t\tlabel = \"blue:wlan2g\";\n\t\t\tgpios = <&gpio 33 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\twlan5g {\n\t\t\tlabel = \"blue:wlan5g\";\n\t\t\tgpios = <&gpio 28 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tgpio_export {\n\t\tcompatible = \"gpio-export\";\n\t\t#size-cells = <0>;\n\n\t\tpower_usb2 {\n\t\t\tgpio-export,name = \"power_usb2\";\n\t\t\tgpio-export,output = <1>;\n\t\t\tgpios = <&gpio 22 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tpower_usb3 {\n\t\t\tgpio-export,name = \"power_usb3\";\n\t\t\tgpio-export,output = <1>;\n\t\t\tgpios = <&gpio 25 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tpower_sata {\n\t\t\tgpio-export,name = \"power_sata\";\n\t\t\tgpio-export,output = <1>;\n\t\t\tgpios = <&gpio 27 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <40000000>;\n\t\tbroken-flash-reset;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x1fb0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&sdhci {\n\tstatus = \"okay\";\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\twifi@0,0 {\n\t\tcompatible = \"pci1400,7603\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x0000>;\n\t};\n};\n\n&pcie1 {\n\twifi@0,0 {\n\t\tcompatible = \"pci14c3,7662\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\t};\n};\n\n&ethernet {\n\tpinctrl-0 = <&mdio_pins>, <&rgmii1_pins>;\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_factory_e000>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&switch0 {\n\tports {\n\t\tport@0 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan1\";\n\t\t};\n\n\t\tport@1 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan2\";\n\t\t};\n\n\t\tport@2 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan3\";\n\t\t};\n\n\t\tport@3 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan4\";\n\t\t};\n\n\t\tport@4 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"wan\";\n\t\t\tnvmem-cells = <&macaddr_factory_e000>;\n\t\t\tnvmem-cell-names = \"mac-address\";\n\t\t\tmac-address-increment = <1>;\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"wdt\", \"rgmii2\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_e000: macaddr@e000 {\n\t\treg = <0xe000 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_youhua_wr1200js.dts",
    "content": "#include \"mt7621.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"youhua,wr1200js\", \"mediatek,mt7621-soc\";\n\tmodel = \"YouHua WR1200JS\";\n\n\taliases {\n\t\tled-boot = &led_wps;\n\t\tled-failsafe = &led_wps;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200\";\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tinternet {\n\t\t\tlabel = \"blue:internet\";\n\t\t\tgpios = <&gpio 6 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_wps: wps {\n\t\t\tlabel = \"blue:wps\";\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tusb {\n\t\t\tlabel = \"blue:usb\";\n\t\t\tgpios = <&gpio 8 GPIO_ACTIVE_LOW>;\n\t\t\ttrigger-sources = <&xhci_ehci_port1>, <&ehci_port2>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 3 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\n\t\twifi {\n\t\t\tlabel = \"wifi\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RFKILL>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0xfb0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\tmt76@0,0 {\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x0000>;\n\t};\n};\n\n&pcie1 {\n\tmt76@0,0 {\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\n\t\tled {\n\t\t\tled-sources = <2>;\n\t\t\tled-active-low;\n\t\t};\n\t};\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_factory_e000>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&switch0 {\n\tports {\n\t\tport@0 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"wan\";\n\t\t\tnvmem-cells = <&macaddr_factory_e006>;\n\t\t\tnvmem-cell-names = \"mac-address\";\n\t\t};\n\n\t\tport@1 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan1\";\n\t\t};\n\n\t\tport@2 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan2\";\n\t\t};\n\n\t\tport@3 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan3\";\n\t\t};\n\n\t\tport@4 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan4\";\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"uart2\", \"uart3\", \"wdt\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_e000: macaddr@e000 {\n\t\treg = <0xe000 0x6>;\n\t};\n\n\tmacaddr_factory_e006: macaddr@e006 {\n\t\treg = <0xe006 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_youku_yk-l2.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"youku,yk-l2\", \"mediatek,mt7621-soc\";\n\tmodel = \"Youku YK-L2\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_wps;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200\";\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"blue:power\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\tled_wps: wps {\n\t\t\tlabel = \"blue:wps\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tusb {\n\t\t\tlabel = \"blue:usb\";\n\t\t\tgpios = <&gpio 16 GPIO_ACTIVE_LOW>;\n\t\t\ttrigger-sources = <&xhci_ehci_port1>, <&ehci_port2>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio 17 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n};\n\n&sdhci {\n\tstatus = \"okay\";\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0xfb0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\twifi@0,0 {\n\t\tcompatible = \"pci14c3,7603\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x0000>;\n\t\tieee80211-freq-limit = <2400000 2500000>;\n\t\tled {\n\t\t\tled-active-low;\n\t\t};\n\t};\n};\n\n&pcie1 {\n\twifi@0,0 {\n\t\tcompatible = \"pci14c3,7662\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\t\tled {\n\t\t\tled-sources = <2>;\n\t\t\tled-active-low;\n\t\t};\n\t};\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_factory_e000>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&switch0 {\n\tports {\n\t\tport@0 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan1\";\n\t\t};\n\n\t\tport@1 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan2\";\n\t\t};\n\n\t\tport@2 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan3\";\n\t\t};\n\n\t\tport@3 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan4\";\n\t\t};\n\n\t\tport@4 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"wan\";\n\t\t\tnvmem-cells = <&macaddr_factory_e006>;\n\t\t\tnvmem-cell-names = \"mac-address\";\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"jtag\", \"wdt\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_e000: macaddr@e000 {\n\t\treg = <0xe000 0x6>;\n\t};\n\n\tmacaddr_factory_e006: macaddr@e006 {\n\t\treg = <0xe006 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_yuncore_ax820.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"yuncore,ax820\", \"mediatek,mt7621-soc\";\n\tmodel = \"YunCore AX820\";\n\n\taliases {\n\t\tled-boot = &led_status_green;\n\t\tled-failsafe = &led_status_green;\n\t\tled-running = &led_status_green;\n\t\tled-upgrade = &led_status_green;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200\";\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_status_green: status_green {\n\t\t\tlabel = \"green:status\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\twatchdog {\n\t\tcompatible = \"linux,wdt-gpio\";\n\t\tgpios = <&gpio 0 GPIO_ACTIVE_LOW>;\n\t\thw_algo = \"toggle\";\n\t\thw_margin_ms = <200>;\n\t\talways-running;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <80000000>;\n\t\tm25p,fast-read;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"Bootloader\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"Config\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\t/* range 0x40000 to 0x50000 is empty in vendor\n\t\t\t * firmware, so we do not use it either\n\t\t\t */\n\n\t\t\tfactory: partition@50000 {\n\t\t\t\tlabel = \"Factory\";\n\t\t\t\treg = <0x50000 0x40000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@90000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x90000 0xf70000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie1 {\n\twifi@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x0>;\n\t};\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_factory_e000>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&switch0 {\n\tports {\n\t\tport@0 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"wan\";\n\t\t\tnvmem-cells = <&macaddr_factory_e000>;\n\t\t\tnvmem-cell-names = \"mac-address\";\n\t\t\tmac-address-increment = <1>;\n\t\t};\n\n\t\tport@1 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan\";\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"jtag\", \"wdt\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_e000: macaddr@e000 {\n\t\treg = <0xe000 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_zbtlink_zbt-we1326.dts",
    "content": "#include \"mt7621.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"zbtlink,zbt-we1326\", \"mediatek,mt7621-soc\";\n\tmodel = \"Zbtlink ZBT-WE1326\";\n\n\taliases {\n\t\tlabel-mac-device = &wifi1;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"wdt\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0xfb0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_factory_e000>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&switch0 {\n\tports {\n\t\tport@0 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan1\";\n\t\t};\n\n\t\tport@1 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan2\";\n\t\t};\n\n\t\tport@2 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan3\";\n\t\t};\n\n\t\tport@3 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan4\";\n\t\t};\n\n\t\tport@4 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"wan\";\n\t\t\tnvmem-cells = <&macaddr_factory_e006>;\n\t\t\tnvmem-cell-names = \"mac-address\";\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\twifi0: mt76@0,0 {\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\t};\n};\n\n&pcie1 {\n\twifi1: mt76@0,0 {\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x0000>;\n\t\tieee80211-freq-limit = <2400000 2500000>;\n\t};\n};\n\n&sdhci {\n\tstatus = \"okay\";\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_e000: macaddr@e000 {\n\t\treg = <0xe000 0x6>;\n\t};\n\n\tmacaddr_factory_e006: macaddr@e006 {\n\t\treg = <0xe006 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_zbtlink_zbt-we3526.dts",
    "content": "#include \"mt7621.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"zbtlink,zbt-we3526\", \"mediatek,mt7621-soc\";\n\tmodel = \"Zbtlink ZBT-WE3526\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n};\n\n&i2c {\n\tstatus = \"okay\";\n};\n\n&sdhci {\n\tstatus = \"okay\";\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfirmware: partition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0xfb0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\twifi@0,0 {\n\t\tcompatible = \"pci14c3,7662\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\n\t\tled {\n\t\t\tled-sources = <2>;\n\t\t};\n\t};\n};\n\n&pcie1 {\n\twifi@0,0 {\n\t\tcompatible = \"pci14c3,7603\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x0000>;\n\t};\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_factory_e000>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&switch0 {\n\tports {\n\t\tport@0 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan1\";\n\t\t};\n\n\t\tport@1 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan2\";\n\t\t};\n\n\t\tport@2 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan3\";\n\t\t};\n\n\t\tport@3 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan4\";\n\t\t};\n\n\t\tport@4 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"wan\";\n\t\t\tnvmem-cells = <&macaddr_factory_e006>;\n\t\t\tnvmem-cell-names = \"mac-address\";\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"wdt\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_e000: macaddr@e000 {\n\t\treg = <0xe000 0x6>;\n\t};\n\n\tmacaddr_factory_e006: macaddr@e006 {\n\t\treg = <0xe006 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_zbtlink_zbt-wg1602-16m.dts",
    "content": "#include \"mt7621_zbtlink_zbt-wg1602.dtsi\"\n\n/ {\n\tcompatible = \"zbtlink,zbt-wg1602-16m\", \"zbtlink,zbt-wg1602\", \"mediatek,mt7621-soc\";\n\tmodel = \"Zbtlink ZBT-WG1602 (16M)\";\n};\n\n&firmware {\n\treg = <0x50000 0xfb0000>;\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_zbtlink_zbt-wg1602.dtsi",
    "content": "#include \"mt7621.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"zbtlink,zbt-wg1602\", \"mediatek,mt7621-soc\";\n\n\taliases {\n\t\tled-boot = &led_sm;\n\t\tled-failsafe = &led_sm;\n\t\tled-running = &led_sm;\n\t\tled-upgrade = &led_sm;\n\t\tlabel-mac-device = &gmac0;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_sm: sm {\n\t\t\tlabel = \"green:sm\";\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\t4g1 {\n\t\t\tlabel = \"green:4g1\";\n\t\t\tgpios = <&gpio 10 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\t4g2 {\n\t\t\tlabel = \"green:4g2\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\twatchdog {\n\t\tcompatible = \"linux,wdt-gpio\";\n\t\tgpios = <&gpio 3 GPIO_ACTIVE_HIGH>;\n\t\thw_algo = \"toggle\";\n\t\t/* hw_margin_ms is actually ~120s but driver limits it to 60s */\n\t\thw_margin_ms = <60000>;\n\t\talways-running;\n\t};\n\n\tgpio-export {\n\t\tcompatible = \"gpio-export\";\n\t\t#size-cells = <0>;\n\n\t\t4g1-pwr {\n\t\t\tgpio-export,name = \"4g1-pwr\";\n\t\t\tgpio-export,output = <1>;\n\t\t\tgpios = <&gpio 8 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\t4g2-pwr {\n\t\t\tgpio-export,name = \"4g2-pwr\";\n\t\t\tgpio-export,output = <1>;\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\text-usb {\n\t\t\tgpio-export,name = \"ext-usb\";\n\t\t\tgpio-export,output = <1>;\n\t\t\tgpios = <&gpio 6 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&sdhci {\n\tstatus = \"okay\";\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfirmware: partition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\twifi0: wifi@0,0 {\n\t\tcompatible = \"pci14c3,7603\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x0000>;\n\t};\n};\n\n&pcie1 {\n\twifi1: wifi@0,0 {\n\t\tcompatible = \"pci14c3,7662\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\n\t\tled {\n\t\t\tled-sources = <2>;\n\t\t};\n\t};\n};\n\n&ethernet {\n\tpinctrl-0 = <&mdio_pins>, <&rgmii1_pins>;\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_factory_e000>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&switch0 {\n\tports {\n\t\tport@0 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan1\";\n\t\t};\n\n\t\tport@1 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan2\";\n\t\t};\n\n\t\tport@2 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan3\";\n\t\t};\n\n\t\tport@3 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan4\";\n\t\t};\n\n\t\tport@4 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"wan\";\n\t\t\tnvmem-cells = <&macaddr_factory_e006>;\n\t\t\tnvmem-cell-names = \"mac-address\";\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"rgmii2\", \"uart2\", \"wdt\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_e000: macaddr@e000 {\n\t\treg = <0xe000 0x6>;\n\t};\n\n\tmacaddr_factory_e006: macaddr@e006 {\n\t\treg = <0xe006 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_zbtlink_zbt-wg1608-16m.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621_zbtlink_zbt-wg1608.dtsi\"\n\n/ {\n\tcompatible = \"zbtlink,zbt-wg1608-16m\", \"zbtlink,zbt-wg1608\", \"mediatek,mt7621-soc\";\n\tmodel = \"Zbtlink ZBT-WG1608 (16M)\";\n};\n\n&firmware {\n\treg = <0x50000 0xfb0000>;\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_zbtlink_zbt-wg1608.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/leds/common.h>\n\n/ {\n\tcompatible = \"zbtlink,zbt-wg1608\", \"mediatek,mt7621-soc\";\n\n\taliases {\n\t\tled-boot = &led_internet;\n\t\tled-failsafe = &led_internet;\n\t\tled-running = &led_internet;\n\t\tled-upgrade = &led_internet;\n\t\tlabel-mac-device = &gmac0;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_internet: internet {\n\t\t\tlabel = \"green:internet\";\n\t\t\tgpios = <&gpio 12 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twwan {\n\t\t\tlabel = \"green:wwan\";\n\t\t\tgpios = <&gpio 10 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t\ttrigger-sources = <&hub_port2>;\n\t\t};\n\n\t\twifi5g {\n\t\t\tlabel = \"green:wifi5g\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\n\t\tlan1 {\n\t\t\tcolor = <LED_COLOR_ID_GREEN>;\n\t\t\tfunction = LED_FUNCTION_LAN;\n\t\t\tfunction-enumerator = <1>;\n\t\t\tgpios = <&switch0 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan2 {\n\t\t\tcolor = <LED_COLOR_ID_GREEN>;\n\t\t\tfunction = LED_FUNCTION_LAN;\n\t\t\tfunction-enumerator = <2>;\n\t\t\tgpios = <&switch0 3 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan3 {\n\t\t\tcolor = <LED_COLOR_ID_GREEN>;\n\t\t\tfunction = LED_FUNCTION_LAN;\n\t\t\tfunction-enumerator = <3>;\n\t\t\tgpios = <&switch0 6 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan4 {\n\t\t\tcolor = <LED_COLOR_ID_GREEN>;\n\t\t\tfunction = LED_FUNCTION_LAN;\n\t\t\tfunction-enumerator = <4>;\n\t\t\tgpios = <&switch0 9 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\twan {\n\t\t\tcolor = <LED_COLOR_ID_GREEN>;\n\t\t\tfunction = LED_FUNCTION_WAN;\n\t\t\tgpios = <&switch0 12 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&sdhci {\n\tstatus = \"okay\";\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <50000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\n\t\t\t\tcompatible = \"nvmem-cells\";\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\n\t\t\t\tmacaddr_factory_e000: macaddr@e000 {\n\t\t\t\t\treg = <0xe000 0x6>;\n\t\t\t\t};\n\n\t\t\t\tmacaddr_factory_e006: macaddr@e006 {\n\t\t\t\t\treg = <0xe006 0x6>;\n\t\t\t\t};\n\n\t\t\t};\n\n\t\t\tfirmware: partition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\twifi@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x0000>;\n\t};\n};\n\n&pcie1 {\n\twifi@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\t};\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_factory_e000>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&switch0 {\n\tgpio-controller;\n\t#gpio-cells = <2>;\n\n\tports {\n\t\tport@0 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan1\";\n\t\t};\n\n\t\tport@1 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan2\";\n\t\t};\n\n\t\tport@2 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan3\";\n\t\t};\n\n\t\tport@3 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan4\";\n\t\t};\n\n\t\tport@4 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"wan\";\n\t\t\tnvmem-cells = <&macaddr_factory_e006>;\n\t\t\tnvmem-cell-names = \"mac-address\";\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"wdt\", \"uart2\", \"jtag\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&xhci_ehci_port1 {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\n\thub_port2: port@2 {\n\t\treg = <2>;\n\t\t#trigger-source-cells = <0>;\n\t};\n\n\tport@4 {\n\t\treg = <4>;\n\t\t#trigger-source-cells = <0>;\n\t};\n};\n\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_zbtlink_zbt-wg2626.dts",
    "content": "#include \"mt7621.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"zbtlink,zbt-wg2626\", \"mediatek,mt7621-soc\";\n\tmodel = \"Zbtlink ZBT-WG2626\";\n\n\taliases {\n\t\tled-boot = &led_status;\n\t\tled-failsafe = &led_status;\n\t\tled-running = &led_status;\n\t\tled-upgrade = &led_status;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_status: status {\n\t\t\tlabel = \"green:status\";\n\t\t\tgpios = <&gpio 24 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&i2c {\n\tstatus = \"okay\";\n};\n\n&sdhci {\n\tstatus = \"okay\";\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0xfb0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n\n\treset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>,\n\t\t\t<&gpio 8 GPIO_ACTIVE_LOW>;\n};\n\n&pcie0 {\n\tmt76@0,0 {\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\t};\n};\n\n&pcie1 {\n\tmt76@0,0 {\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x0000>;\n\t\tieee80211-freq-limit = <2400000 2500000>;\n\t};\n};\n\n&ethernet {\n\tpinctrl-0 = <&mdio_pins>, <&rgmii1_pins>;\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_factory_e000>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&switch0 {\n\tports {\n\t\tport@0 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan4\";\n\t\t};\n\n\t\tport@1 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan3\";\n\t\t};\n\n\t\tport@2 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan2\";\n\t\t};\n\n\t\tport@3 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan1\";\n\t\t};\n\n\t\tport@4 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"wan\";\n\t\t\tnvmem-cells = <&macaddr_factory_e000>;\n\t\t\tnvmem-cell-names = \"mac-address\";\n\t\t\tmac-address-increment = <1>;\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"wdt\", \"rgmii2\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_e000: macaddr@e000 {\n\t\treg = <0xe000 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_zbtlink_zbt-wg3526-16m.dts",
    "content": "#include \"mt7621_zbtlink_zbt-wg3526.dtsi\"\n\n/ {\n\tcompatible = \"zbtlink,zbt-wg3526-16m\", \"zbtlink,zbt-wg3526\", \"mediatek,mt7621-soc\";\n\tmodel = \"Zbtlink ZBT-WG3526 (16M)\";\n};\n\n&firmware {\n\treg = <0x50000 0xfb0000>;\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_zbtlink_zbt-wg3526-32m.dts",
    "content": "#include \"mt7621_zbtlink_zbt-wg3526.dtsi\"\n\n/ {\n\tcompatible = \"zbtlink,zbt-wg3526-32m\", \"zbtlink,zbt-wg3526\", \"mediatek,mt7621-soc\";\n\tmodel = \"Zbtlink ZBT-WG3526 (32M)\";\n};\n\n&flash0 {\n\tbroken-flash-reset;\n};\n\n&firmware {\n\treg = <0x50000 0x1fb0000>;\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_zbtlink_zbt-wg3526.dtsi",
    "content": "#include \"mt7621.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"zbtlink,zbt-wg3526\", \"mediatek,mt7621-soc\";\n\n\taliases {\n\t\tled-boot = &led_status;\n\t\tled-failsafe = &led_status;\n\t\tled-running = &led_status;\n\t\tled-upgrade = &led_status;\n\t\tlabel-mac-device = &wifi0;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_status: status {\n\t\t\tlabel = \"green:status\";\n\t\t\tgpios = <&gpio 24 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&i2c {\n\tstatus = \"okay\";\n};\n\n&sdhci {\n\tstatus = \"okay\";\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash0: flash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfirmware: partition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\twifi0: wifi@0,0 {\n\t\tcompatible = \"pci14c3,7603\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x0000>;\n\t};\n};\n\n&pcie1 {\n\twifi1: wifi@0,0 {\n\t\tcompatible = \"pci14c3,7662\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\n\t\tled {\n\t\t\tled-sources = <2>;\n\t\t};\n\t};\n};\n\n&ethernet {\n\tpinctrl-0 = <&mdio_pins>, <&rgmii1_pins>;\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_factory_e000>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&switch0 {\n\tports {\n\t\tport@0 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan1\";\n\t\t};\n\n\t\tport@1 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan2\";\n\t\t};\n\n\t\tport@2 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan3\";\n\t\t};\n\n\t\tport@3 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan4\";\n\t\t};\n\n\t\tport@4 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"wan\";\n\t\t\tnvmem-cells = <&macaddr_factory_e000>;\n\t\t\tnvmem-cell-names = \"mac-address\";\n\t\t\tmac-address-increment = <1>;\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"wdt\", \"rgmii2\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_e000: macaddr@e000 {\n\t\treg = <0xe000 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_zio_freezio.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621_wevo_w2914ns-v2.dtsi\"\n\n/ {\n\tcompatible = \"zio,freezio\", \"mediatek,mt7621-soc\";\n\tmodel = \"ZIO FREEZIO\";\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_zyxel_nr7101.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"zyxel,nr7101\", \"mediatek,mt7621-soc\";\n\tmodel = \"ZyXEL NR7101\";\n\n\taliases {\n\t\tled-boot = &led_system_green;\n\t\tled-failsafe = &led_system_green;\n\t\tled-running = &led_system_green;\n\t\tled-upgrade = &led_system_green;\n\t\tlabel-mac-device = &gmac0;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tsystem_yellow {\n\t\t\tlabel = \"yellow:system\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tled_system_green: system_green {\n\t\t\tlabel = \"green:system\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tsystem_red {\n\t\t\tlabel = \"red:system\";\n\t\t\tgpios = <&gpio 15 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\twps {\n\t\t\tlabel = \"wlan\";\n\t\t\tgpios = <&gpio 8 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WLAN>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 6 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n};\n\n&gpio {\n\tlte_pwrkey {\n\t\tgpio-hog;\n\t\tgpios = <4 GPIO_ACTIVE_HIGH>;\n\t\toutput-high;\n\t\tline-name = \"lte-pwrkey\";\n\t};\n\n\tlte_power {\n\t\tgpio-hog;\n\t\tgpios = <18 GPIO_ACTIVE_HIGH>;\n\t\toutput-high;\n\t\tline-name = \"lte-power\";\n\t};\n};\n\n&nand {\n\tstatus = \"okay\";\n\n\tpartitions {\n\t\tcompatible = \"fixed-partitions\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"Bootloader\";\n\t\t\treg = <0x0 0x80000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@80000 {\n\t\t\tlabel = \"Config\";\n\t\t\treg = <0x80000 0x80000>;\n\t\t};\n\n\t\tfactory: partition@100000 {\n\t\t\tlabel = \"Factory\";\n\t\t\treg = <0x100000 0x40000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@140000 {\n\t\t\tlabel = \"Kernel\";\n\t\t\treg = <0x140000 0x1ec0000>;\n\t\t};\n\n\t\tpartition@540000 {\n\t\t\tlabel = \"ubi\";\n\t\t\treg = <0x540000 0x1ac0000>;\n\t\t};\n\n\t\tpartition@2140000 {\n\t\t\tlabel = \"Kernel2\";\n\t\t\treg = <0x2140000 0x1ec0000>;\n\t\t};\n\n\t\tpartition@4000000 {\n\t\t\tlabel = \"wwan\";\n\t\t\treg = <0x4000000 0x100000>;\n\t\t};\n\n\t\tpartition@4100000 {\n\t\t\tlabel = \"data\";\n\t\t\treg = <0x4100000 0x1000000>;\n\t\t};\n\n\t\tpartition@5100000 {\n\t\t\tlabel = \"rom-d\";\n\t\t\treg = <0x5100000 0x100000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@5200000 {\n\t\t\tlabel = \"reserve\";\n\t\t\treg = <0x5200000 0x80000>;\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\tmt76@0,0 {\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x0>;\n\t};\n};\n\n&ethernet {\n\tpinctrl-0 = <&mdio_pins>, <&rgmii1_pins>;\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_factory_e000>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&switch0 {\n\tports {\n\t\tport@2 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan\";\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"rgmii2\", \"uart3\", \"jtag\", \"wdt\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_e000: macaddr@e000 {\n\t\treg = <0xe000 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7621_zyxel_wap6805.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7621.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"zyxel,wap6805\", \"mediatek,mt7621-soc\";\n\tmodel = \"ZyXEL WAP6805\";\n\n\taliases {\n\t\tled-boot = &led_status_green;\n\t\tled-failsafe = &led_status_red;\n\t\tled-running = &led_status_green;\n\t\tled-upgrade = &led_status_green;\n\t\tlabel-mac-device = &gmac0;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_status_red: status_red {\n\t\t\tlabel = \"red:status\";\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tstatus_blink {\n\t\t\tlabel = \"blink:status\";\n\t\t\tgpios = <&gpio 7 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tled_status_green: status_green {\n\t\t\tlabel = \"green:status\";\n\t\t\tgpios = <&gpio 13 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio 8 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n};\n\n&nand {\n\tstatus = \"okay\";\n\n\tpartitions {\n\t\tcompatible = \"fixed-partitions\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tpartition@0 {\n\t\t\tlabel = \"Bootloader\";\n\t\t\treg = <0x0 0x100000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@100000 {\n\t\t\tlabel = \"MRD\";\n\t\t\treg = <0x100000 0x100000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tfactory: partition@200000 {\n\t\t\tlabel = \"Factory\";\n\t\t\treg = <0x200000 0x100000>;\n\t\t\tread-only;\n\t\t};\n\n\t\tpartition@300000 {\n\t\t\tlabel = \"Config\";\n\t\t\treg = <0x300000 0x100000>;\n\t\t};\n\n\t\tpartition@400000 {\n\t\t\tlabel = \"Kernel\";\n\t\t\treg = <0x400000 0x2000000>;\n\t\t};\n\n\t\tpartition@800000 {\n\t\t\tlabel = \"ubi\";\n\t\t\treg = <0x800000 0x1c00000>;\n\t\t};\n\n\t\tpartition@2400000 {\n\t\t\tlabel = \"Kernel2\";\n\t\t\treg = <0x2400000 0x2000000>;\n\t\t};\n\n\t\tpartition@4400000 {\n\t\t\tlabel = \"Private\";\n\t\t\treg = <0x4400000 0x100000>;\n\t\t};\n\n\t\tpartition@4500000 {\n\t\t\tlabel = \"Log\";\n\t\t\treg = <0x4500000 0x1000000>;\n\t\t};\n\n\t\tpartition@5500000 {\n\t\t\tlabel = \"App\";\n\t\t\treg = <0x5500000 0x2b00000>;\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\tmt76@0,0 {\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x0>;\n\t};\n};\n\n&gmac0 {\n\tnvmem-cells = <&macaddr_factory_e000>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&gmac1 {\n\tstatus = \"okay\";\n\n\tfixed-link {\n\t\tspeed = <1000>;\n\t\tfull-duplex;\n\t};\n};\n\n&switch0 {\n\tports {\n\t\tport@0 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan4\";\n\t\t};\n\t\tport@1 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan3\";\n\t\t};\n\t\tport@2 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan2\";\n\t\t};\n\t\tport@3 {\n\t\t\tstatus = \"okay\";\n\t\t\tlabel = \"lan1\";\n\t\t};\n\t};\n};\n\n&xhci {\n\tstatus = \"disabled\";\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"uart3\", \"jtag\", \"wdt\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_e000: macaddr@e000 {\n\t\treg = <0xe000 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7628an.dtsi",
    "content": "/dts-v1/;\n\n/ {\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\tcompatible = \"mediatek,mt7628an-soc\";\n\n\taliases {\n\t\tserial0 = &uartlite;\n\t};\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu@0 {\n\t\t\tcompatible = \"mips,mips24KEc\";\n\t\t\treg = <0>;\n\t\t};\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,57600\";\n\t};\n\n\tcpuintc: cpuintc {\n\t\t#address-cells = <0>;\n\t\t#interrupt-cells = <1>;\n\t\tinterrupt-controller;\n\t\tcompatible = \"mti,cpu-interrupt-controller\";\n\t};\n\n\tpalmbus: palmbus@10000000 {\n\t\tcompatible = \"palmbus\";\n\t\treg = <0x10000000 0x200000>;\n\t\tranges = <0x0 0x10000000 0x1FFFFF>;\n\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tsysc: sysc@0 {\n\t\t\tcompatible = \"ralink,mt7620a-sysc\", \"syscon\";\n\t\t\treg = <0x0 0x100>;\n\t\t};\n\n\t\twatchdog: watchdog@100 {\n\t\t\tcompatible = \"ralink,mt7628an-wdt\", \"mediatek,mt7621-wdt\";\n\t\t\treg = <0x100 0x30>;\n\n\t\t\tresets = <&rstctrl 8>;\n\t\t\treset-names = \"wdt\";\n\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <24>;\n\t\t};\n\n\t\tintc: intc@200 {\n\t\t\tcompatible = \"ralink,mt7628an-intc\", \"ralink,rt2880-intc\";\n\t\t\treg = <0x200 0x100>;\n\n\t\t\tresets = <&rstctrl 9>;\n\t\t\treset-names = \"intc\";\n\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <1>;\n\n\t\t\tinterrupt-parent = <&cpuintc>;\n\t\t\tinterrupts = <2>;\n\n\t\t\tralink,intc-registers = <0x9c 0xa0\n\t\t\t\t\t\t 0x6c 0xa4\n\t\t\t\t\t\t 0x80 0x78>;\n\t\t};\n\n\t\tmemc: memc@300 {\n\t\t\tcompatible = \"ralink,mt7620a-memc\", \"ralink,rt3050-memc\";\n\t\t\treg = <0x300 0x100>;\n\n\t\t\tresets = <&rstctrl 20>;\n\t\t\treset-names = \"mc\";\n\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <3>;\n\t\t};\n\n\t\tgpio: gpio@600 {\n\t\t\tcompatible = \"mediatek,mt7621-gpio\";\n\t\t\treg = <0x600 0x100>;\n\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <6>;\n\n\t\t\t#interrupt-cells = <2>;\n\t\t\tinterrupt-controller;\n\n\t\t\tgpio-controller;\n\t\t\t#gpio-cells = <2>;\n\t\t};\n\n\t\ti2c: i2c@900 {\n\t\t\tcompatible = \"mediatek,mt7621-i2c\";\n\t\t\treg = <0x900 0x100>;\n\n\t\t\tresets = <&rstctrl 16>;\n\t\t\treset-names = \"i2c\";\n\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\n\t\t\tstatus = \"disabled\";\n\n\t\t\tpinctrl-names = \"default\";\n\t\t\tpinctrl-0 = <&i2c_pins>;\n\t\t};\n\n\t\ti2s: i2s@a00 {\n\t\t\tcompatible = \"mediatek,mt7628-i2s\";\n\t\t\treg = <0xa00 0x100>;\n\n\t\t\tresets = <&rstctrl 17>;\n\t\t\treset-names = \"i2s\";\n\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <10>;\n\n\t\t\ttxdma-req = <2>;\n\t\t\trxdma-req = <3>;\n\n\t\t\tdmas = <&gdma 4>,\n\t\t\t\t<&gdma 6>;\n\t\t\tdma-names = \"tx\", \"rx\";\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tspi0: spi@b00 {\n\t\t\tcompatible = \"ralink,mt7621-spi\";\n\t\t\treg = <0xb00 0x100>;\n\n\t\t\tresets = <&rstctrl 18>;\n\t\t\treset-names = \"spi\";\n\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\n\t\t\tpinctrl-names = \"default\";\n\t\t\tpinctrl-0 = <&spi_pins>;\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tuartlite: uartlite@c00 {\n\t\t\tcompatible = \"ns16550a\";\n\t\t\treg = <0xc00 0x100>;\n\n\t\t\treg-shift = <2>;\n\t\t\treg-io-width = <4>;\n\t\t\tno-loopback-test;\n\n\t\t\tclock-frequency = <40000000>;\n\n\t\t\tresets = <&rstctrl 12>;\n\t\t\treset-names = \"uartl\";\n\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <20>;\n\n\t\t\tpinctrl-names = \"default\";\n\t\t\tpinctrl-0 = <&uart0_pins>;\n\t\t};\n\n\t\tuart1: uart1@d00 {\n\t\t\tcompatible = \"ns16550a\";\n\t\t\treg = <0xd00 0x100>;\n\n\t\t\treg-shift = <2>;\n\t\t\treg-io-width = <4>;\n\t\t\tno-loopback-test;\n\n\t\t\tclock-frequency = <40000000>;\n\n\t\t\tresets = <&rstctrl 19>;\n\t\t\treset-names = \"uart1\";\n\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <21>;\n\n\t\t\tpinctrl-names = \"default\";\n\t\t\tpinctrl-0 = <&uart1_pins>;\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tuart2: uart2@e00 {\n\t\t\tcompatible = \"ns16550a\";\n\t\t\treg = <0xe00 0x100>;\n\n\t\t\treg-shift = <2>;\n\t\t\treg-io-width = <4>;\n\t\t\tno-loopback-test;\n\n\t\t\tclock-frequency = <40000000>;\n\n\t\t\tresets = <&rstctrl 20>;\n\t\t\treset-names = \"uart2\";\n\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <22>;\n\n\t\t\tpinctrl-names = \"default\";\n\t\t\tpinctrl-0 = <&uart2_pins>;\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tpwm: pwm@5000 {\n\t\t\tcompatible = \"mediatek,mt7628-pwm\";\n\t\t\treg = <0x5000 0x1000>;\n\t\t\t#pwm-cells = <2>;\n\n\t\t\tresets = <&rstctrl 31>;\n\t\t\treset-names = \"pwm\";\n\n\t\t\tpinctrl-names = \"default\";\n\t\t\tpinctrl-0 = <&pwm0_pins>, <&pwm1_pins>;\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tpcm: pcm@2000 {\n\t\t\tcompatible = \"ralink,mt7620a-pcm\";\n\t\t\treg = <0x2000 0x800>;\n\n\t\t\tresets = <&rstctrl 11>;\n\t\t\treset-names = \"pcm\";\n\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <4>;\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tgdma: gdma@2800 {\n\t\t\tcompatible = \"ralink,rt3883-gdma\";\n\t\t\treg = <0x2800 0x800>;\n\n\t\t\tresets = <&rstctrl 14>;\n\t\t\treset-names = \"dma\";\n\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <7>;\n\n\t\t\t#dma-cells = <1>;\n\t\t\t#dma-channels = <16>;\n\t\t\t#dma-requests = <16>;\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\t};\n\n\tpinctrl: pinctrl {\n\t\tcompatible = \"ralink,rt2880-pinmux\";\n\t\tpinctrl-names = \"default\";\n\t\tpinctrl-0 = <&state_default>;\n\n\t\tstate_default: pinctrl0 {\n\t\t};\n\n\t\tspi_pins: spi_pins {\n\t\t\tspi_pins {\n\t\t\t\tgroups = \"spi\";\n\t\t\t\tfunction = \"spi\";\n\t\t\t};\n\t\t};\n\n\t\tspi_cs1_pins: spi_cs1 {\n\t\t\tspi_cs1 {\n\t\t\t\tgroups = \"spi cs1\";\n\t\t\t\tfunction = \"spi cs1\";\n\t\t\t};\n\t\t};\n\n\t\ti2c_pins: i2c_pins {\n\t\t\ti2c_pins {\n\t\t\t\tgroups = \"i2c\";\n\t\t\t\tfunction = \"i2c\";\n\t\t\t};\n\t\t};\n\n\t\ti2s_pins: i2s {\n\t\t\ti2s {\n\t\t\t\tgroups = \"i2s\";\n\t\t\t\tfunction = \"i2s\";\n\t\t\t};\n\t\t};\n\n\t\tuart0_pins: uartlite {\n\t\t\tuartlite {\n\t\t\t\tgroups = \"uart0\";\n\t\t\t\tfunction = \"uart0\";\n\t\t\t};\n\t\t};\n\n\t\tuart1_pins: uart1 {\n\t\t\tuart1 {\n\t\t\t\tgroups = \"uart1\";\n\t\t\t\tfunction = \"uart1\";\n\t\t\t};\n\t\t};\n\n\t\tuart2_pins: uart2 {\n\t\t\tuart2 {\n\t\t\t\tgroups = \"uart2\";\n\t\t\t\tfunction = \"uart2\";\n\t\t\t};\n\t\t};\n\n\t\tsdxc_pins: sdxc {\n\t\t\tsdxc {\n\t\t\t\tgroups = \"sdmode\";\n\t\t\t\tfunction = \"sdxc\";\n\t\t\t};\n\t\t};\n\n\t\tpwm0_pins: pwm0 {\n\t\t\tpwm0 {\n\t\t\t\tgroups = \"pwm0\";\n\t\t\t\tfunction = \"pwm0\";\n\t\t\t};\n\t\t};\n\n\t\tpwm1_pins: pwm1 {\n\t\t\tpwm1 {\n\t\t\t\tgroups = \"pwm1\";\n\t\t\t\tfunction = \"pwm1\";\n\t\t\t};\n\t\t};\n\n\t\tpcm_i2s_pins: pcm_i2s {\n\t\t\tpcm_i2s {\n\t\t\t\tgroups = \"i2s\";\n\t\t\t\tfunction = \"pcm\";\n\t\t\t};\n\t\t};\n\n\t\trefclk_pins: refclk {\n\t\t\trefclk {\n\t\t\t\tgroups = \"refclk\";\n\t\t\t\tfunction = \"refclk\";\n\t\t\t};\n\t\t};\n\t};\n\n\trstctrl: rstctrl {\n\t\tcompatible = \"ralink,mt7620a-reset\", \"ralink,rt2880-reset\";\n\t\t#reset-cells = <1>;\n\t};\n\n\tclkctrl: clkctrl {\n\t\tcompatible = \"ralink,rt2880-clock\";\n\t\t#clock-cells = <1>;\n\t};\n\n\tusbphy: usbphy@10120000 {\n\t\tcompatible = \"mediatek,mt7628-usbphy\", \"mediatek,mt7620-usbphy\";\n\t\treg = <0x10120000 0x1000>;\n\t\t#phy-cells = <0>;\n\n\t\tralink,sysctl = <&sysc>;\n\t\tresets = <&rstctrl 22 &rstctrl 25>;\n\t\treset-names = \"host\", \"device\";\n\t\tclocks = <&clkctrl 22 &clkctrl 25>;\n\t\tclock-names = \"host\", \"device\";\n\t};\n\n\tsdhci: sdhci@10130000 {\n\t\tcompatible = \"ralink,mt7620-sdhci\";\n\t\treg = <0x10130000 0x4000>;\n\n\t\tinterrupt-parent = <&intc>;\n\t\tinterrupts = <14>;\n\n\t\tpinctrl-names = \"default\";\n\t\tpinctrl-0 = <&sdxc_pins>;\n\n\t\tstatus = \"disabled\";\n\t};\n\n\tehci: ehci@101c0000 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tcompatible = \"generic-ehci\";\n\t\treg = <0x101c0000 0x1000>;\n\n\t\tphys = <&usbphy>;\n\t\tphy-names = \"usb\";\n\n\t\tinterrupt-parent = <&intc>;\n\t\tinterrupts = <18>;\n\n\t\tehci_port1: port@1 {\n\t\t\treg = <1>;\n\t\t\t#trigger-source-cells = <0>;\n\t\t};\n\t};\n\n\tohci: ohci@101c1000 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tcompatible = \"generic-ohci\";\n\t\treg = <0x101c1000 0x1000>;\n\n\t\tphys = <&usbphy>;\n\t\tphy-names = \"usb\";\n\n\t\tinterrupt-parent = <&intc>;\n\t\tinterrupts = <18>;\n\n\t\tohci_port1: port@1 {\n\t\t\treg = <1>;\n\t\t\t#trigger-source-cells = <0>;\n\t\t};\n\t};\n\n\tethernet: ethernet@10100000 {\n\t\tcompatible = \"ralink,rt5350-eth\";\n\t\treg = <0x10100000 0x10000>;\n\n\t\tinterrupt-parent = <&cpuintc>;\n\t\tinterrupts = <5>;\n\n\t\tresets = <&rstctrl 21>;\n\t\treset-names = \"fe\";\n\n\t\tmediatek,switch = <&esw>;\n\t};\n\n\tesw: esw@10110000 {\n\t\tcompatible = \"mediatek,mt7628-esw\", \"ralink,rt3050-esw\";\n\t\treg = <0x10110000 0x8000>;\n\n\t\tresets = <&rstctrl 23 &rstctrl 24>;\n\t\treset-names = \"esw\", \"ephy\";\n\n\t\tinterrupt-parent = <&intc>;\n\t\tinterrupts = <17>;\n\t};\n\n\tpcie: pcie@10140000 {\n\t\tcompatible = \"mediatek,mt7620-pci\";\n\t\treg = <0x10140000 0x100\n\t\t\t0x10142000 0x100>;\n\n\t\t#address-cells = <3>;\n\t\t#size-cells = <2>;\n\n\t\tinterrupt-parent = <&cpuintc>;\n\t\tinterrupts = <4>;\n\n\t\tresets = <&rstctrl 26 &rstctrl 27>;\n\t\treset-names = \"pcie0\", \"pcie1\";\n\t\tclocks = <&clkctrl 26 &clkctrl 27>;\n\t\tclock-names = \"pcie0\", \"pcie1\";\n\n\t\tstatus = \"disabled\";\n\n\t\tdevice_type = \"pci\";\n\n\t\tbus-range = <0 255>;\n\t\tranges = <\n\t\t\t0x02000000 0 0x00000000 0x20000000 0 0x10000000 /* pci memory */\n\t\t\t0x01000000 0 0x00000000 0x10160000 0 0x00010000 /* io space */\n\t\t>;\n\n\t\tpcie0: pcie@0,0 {\n\t\t\treg = <0x0000 0 0 0 0>;\n\n\t\t\t#address-cells = <3>;\n\t\t\t#size-cells = <2>;\n\n\t\t\tdevice_type = \"pci\";\n\n\t\t\tranges;\n\t\t};\n\t};\n\n\twmac: wmac@10300000 {\n\t\tcompatible = \"mediatek,mt7628-wmac\";\n\t\treg = <0x10300000 0x100000>;\n\n\t\tinterrupt-parent = <&cpuintc>;\n\t\tinterrupts = <6>;\n\n\t\tstatus = \"disabled\";\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7628an_alfa-network_awusfree1.dts",
    "content": "// SPDX-License-Identifier: BSD-3-Clause\n/*\n *  Copyright (C) 2018 Piotr Dymacz <pepe2k@gmail.com>\n *  All rights reserved.\n */\n\n#include \"mt7628an.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"alfa-network,awusfree1\", \"mediatek,mt7628an-soc\";\n\tmodel = \"ALFA Network AWUSFREE1\";\n\n\taliases {\n\t\tled-boot = &led_system;\n\t\tled-failsafe = &led_system;\n\t\tled-running = &led_system;\n\t\tled-upgrade = &led_system;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 38 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_system: system {\n\t\t\tlabel = \"orange:system\";\n\t\t\tgpios = <&gpio 43 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan {\n\t\t\tlabel = \"blue:wlan\";\n\t\t\tgpios = <&gpio 44 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&ehci {\n\tstatus = \"disabled\";\n};\n\n&esw {\n\tmediatek,portdisable = <0x1e>;\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_2e>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&ohci {\n\tstatus = \"disabled\";\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"p0led_an\", \"wdt\", \"wled_an\";\n\t\tfunction = \"gpio\";\n\t};\n\n\text_lna {\n\t\tgroups = \"uart1\";\n\t\tfunction = \"sw_r\";\n\t};\n\n\text_pa {\n\t\tgroups = \"i2s\";\n\t\tfunction = \"antenna\";\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x1000>;\n\t\t\t};\n\n\t\t\tpartition@31000 {\n\t\t\t\tlabel = \"config\";\n\t\t\t\treg = <0x31000 0xf000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x7b0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmediatek,mtd-eeprom = <&factory 0x0>;\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_2e: macaddr@2e {\n\t\treg = <0x2e 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7628an_asus_rt-ac1200-v2.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7628an_asus_rt-ac1200.dtsi\"\n\n/ {\n\tcompatible = \"asus,rt-ac1200-v2\", \"mediatek,mt7628an-soc\";\n\tmodel = \"ASUS RT-AC1200 V2\";\n};\n\n&state_default {\n\tspis {\n\t\tgroups = \"spis\";\n\t\tfunction = \"spis\";\n\t};\n\n\tgpio {\n\t\tgroups = \"refclk\", \"i2c\", \"wled_an\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&usbphy {\n\tstatus = \"disabled\";\n};\n\n&ehci {\n\tstatus = \"disabled\";\n};\n\n&ohci {\n\tstatus = \"disabled\";\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7628an_asus_rt-ac1200.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n// Copyright (c) 2022 Ray Wang\n// Copyright (c) 2022 Ivan Pavlov\n\n#include \"mt7628an_asus_rt-ac1200.dtsi\"\n\n/ {\n\tcompatible = \"asus,rt-ac1200\", \"mediatek,mt7628an-soc\";\n\tmodel = \"Asus RT-AC1200\";\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tusb {\n\t\t\tlabel = \"blue:usb\";\n\t\t\tgpios = <&gpio 6 GPIO_ACTIVE_HIGH>;\n\t\t\ttrigger-sources = <&ohci_port1>, <&ehci_port1>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"spi cs1\", \"refclk\", \"wled_an\";\n\t\tfunction = \"gpio\";\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7628an_asus_rt-ac1200.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7628an.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\taliases {\n\t\tled-boot = &led_wps;\n\t\tled-failsafe = &led_wps;\n\t\tled-running = &led_wps;\n\t\tled-upgrade = &led_wps;\n\t\tlabel-mac-device = &ethernet;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 5 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_wps: wps {\n\t\t\tlabel = \"blue:wps\";\n\t\t\tgpios = <&gpio 37 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan2g {\n\t\t\tlabel = \"blue:wlan2g\";\n\t\t\tgpios = <&gpio 44 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <58000000>;\n\t\tm25p,fast-read;\n\n\t\tpartitions: partitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\n\t\t\t\tcompatible = \"nvmem-cells\";\n\t\t\t\t#address-cells = <1>;\n\t\t\t\t#size-cells = <1>;\n\n\t\t\t\tmacaddr_factory_4: macaddr@4 {\n\t\t\t\t\treg = <0x4 0x6>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0xfb0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&gpio {\n\tenable-leds {\n\t\tgpio-hog;\n\t\tline-name = \"enable-leds\";\n\t\toutput-low;\n\t\tgpios = <4 GPIO_ACTIVE_HIGH>;\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&esw {\n\tmediatek,portmap = <0x3e>;\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmediatek,mtd-eeprom = <&factory 0x0>;\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\tmt76@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\n\t\tled {\n\t\t\tled-sources = <2>;\n\t\t\tled-active-low;\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7628an_asus_rt-n10p-v3.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later\n\n#include \"mt7628an_asus_rt-n1x.dtsi\"\n\n/ {\n\tcompatible = \"asus,rt-n10p-v3\", \"mediatek,mt7628an-soc\";\n\tmodel = \"Asus RT-N10P V3\";\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7628an_asus_rt-n11p-b1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later\n\n#include \"mt7628an_asus_rt-n1x.dtsi\"\n\n/ {\n\tcompatible = \"asus,rt-n11p-b1\", \"mediatek,mt7628an-soc\";\n\tmodel = \"Asus RT-N11P B1\";\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7628an_asus_rt-n12-vp-b1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later\n\n#include \"mt7628an_asus_rt-n1x.dtsi\"\n\n/ {\n\tcompatible = \"asus,rt-n12-vp-b1\", \"mediatek,mt7628an-soc\";\n\tmodel = \"Asus RT-N12 VP B1\";\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7628an_asus_rt-n1x.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later\n\n#include \"mt7628an.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 5 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 37 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan {\n\t\t\tlabel = \"green:wlan\";\n\t\t\tgpios = <&gpio 44 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\twan {\n\t\t\tlabel = \"green:wan\";\n\t\t\tgpios = <&gpio 43 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan {\n\t\t\tlabel = \"green:lan\";\n\t\t\tgpios = <&gpio 42 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <40000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x7b0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&esw {\n\tmediatek,portmap = <0x2f>;\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmediatek,mtd-eeprom = <&factory 0x0>;\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"p0led_an\", \"p1led_an\", \"refclk\", \"wled_an\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&usbphy {\n\tstatus = \"disabled\";\n};\n\n&ehci {\n\tstatus = \"disabled\";\n};\n\n&ohci {\n\tstatus = \"disabled\";\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7628an_buffalo_wcr-1166ds.dts",
    "content": "#include \"mt7628an.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"buffalo,wcr-1166ds\", \"mediatek,mt7628an-soc\";\n\tmodel = \"Buffalo WCR-1166DS\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\taoss {\n\t\t\tlabel = \"aoss\";\n\t\t\tgpios = <&gpio 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\n\t\tap {\n\t\t\tlabel = \"ap\";\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_0>;\n\t\t\tlinux,input-type = <EV_SW>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 46 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\trouter_o {\n\t\t\tlabel = \"orange:router\";\n\t\t\tgpios = <&gpio 37 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\trouter_g {\n\t\t\tlabel = \"green:router\";\n\t\t\tgpios = <&gpio 38 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tinternet_o {\n\t\t\tlabel = \"orange:internet\";\n\t\t\tgpios = <&gpio 39 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tinternet_g {\n\t\t\tlabel = \"green:internet\";\n\t\t\tgpios = <&gpio 40 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twireless_o {\n\t\t\tlabel = \"orange:wireless\";\n\t\t\tgpios = <&gpio 41 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twireless_g {\n\t\t\tlabel = \"green:wireless\";\n\t\t\tgpios = <&gpio 42 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tdiag {\n\t\t\tlabel = \"orange:diag\";\n\t\t\tgpios = <&gpio 43 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_power: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 44 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&ehci {\n\tstatus = \"disabled\";\n};\n\n&esw {\n\tmediatek,portmap = <0x2f>;\n\tmediatek,portdisable = <0x27>;\n};\n\n&ohci {\n\tstatus = \"disabled\";\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\tmt76@0,0 {\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"uart1\", \"wled_an\", \"p0led_an\", \"p1led_an\", \"p2led_an\", \"p3led_an\", \"p4led_an\", \"wdt\", \"refclk\", \"gpio\", \"i2s\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <40000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"brcm,trx\";\n\t\t\t\tbrcm,trx-magic = <0x746f435c>;\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x7c0000>;\n\t\t\t};\n\n\t\t\tpartition@810000 {\n\t\t\t\tlabel = \"firmware2\";\n\t\t\t\treg = <0x810000 0x7c0000>;\n\t\t\t};\n\n\t\t\tpartition@fd0000 {\n\t\t\t\tlabel = \"glbcfg\";\n\t\t\t\treg = <0xfd0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@fe0000 {\n\t\t\t\tlabel = \"board_data\";\n\t\t\t\treg = <0xfe0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmediatek,mtd-eeprom = <&factory 0x0>;\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7628an_comfast_cf-wr758ac-v1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7628an_comfast_cf-wr758ac.dtsi\"\n\n/ {\n\tcompatible = \"comfast,cf-wr758ac-v1\", \"mediatek,mt7628an-soc\";\n\tmodel = \"COMFAST CF-WR758AC V1\";\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7628an_comfast_cf-wr758ac-v2.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7628an_comfast_cf-wr758ac.dtsi\"\n\n/ {\n\tcompatible = \"comfast,cf-wr758ac-v2\", \"mediatek,mt7628an-soc\";\n\tmodel = \"COMFAST CF-WR758AC V2\";\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7628an_comfast_cf-wr758ac.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7628an.dtsi\"\n\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/gpio/gpio.h>\n\n/ {\n\tcompatible = \"comfast,cf-wr758ac\", \"mediatek,mt7628an-soc\";\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio 38 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twifi-high {\n\t\t\tlabel = \"blue:wifi-high\";\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twifi-med {\n\t\t\tlabel = \"blue:wifi-med\";\n\t\t\tgpios = <&gpio 44 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twifi-low {\n\t\t\tlabel = \"blue:wifi-low\";\n\t\t\tgpios = <&gpio 37 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"refclk\", \"wdt\", \"wled_an\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\twifi@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <50000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x7b0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmediatek,mtd-eeprom = <&factory 0x0>;\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_e000>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&esw {\n\tmediatek,portdisable = <0x2f>;\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_e000: macaddr@e000 {\n\t\treg = <0xe000 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7628an_cudy_wr1000.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7628an.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"cudy,wr1000\", \"mediatek,mt7628an-soc\";\n\tmodel = \"Cudy WR1000\";\n\n\taliases {\n\t\tled-boot = &led_wps;\n\t\tled-failsafe = &led_wps;\n\t\tled-upgrade = &led_wps;\n\t\tlabel-mac-device = &wmac;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 38 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"rfkill\";\n\t\t\tgpios = <&gpio 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tlan1 {\n\t\t\tlabel = \"blue:lan1\";\n\t\t\tgpios = <&gpio 40 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan2 {\n\t\t\tlabel = \"blue:lan2\";\n\t\t\tgpios = <&gpio 41 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twan {\n\t\t\tlabel = \"blue:wan\";\n\t\t\tgpios = <&gpio 39 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan2g {\n\t\t\tlabel = \"blue:wlan2g\";\n\t\t\tgpios = <&gpio 44 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\tled_wps: wps {\n\t\t\tlabel = \"blue:wps\";\n\t\t\tgpios = <&gpio 37 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x7b0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2s\", \"refclk\", \"wdt\", \"p4led_an\",\n\t\t\t\t\"p3led_an\", \"p2led_an\", \"wled_an\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\twifi@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\n\t\tled {\n\t\t\tled-sources = <2>;\n\t\t\tled-active-low;\n\t\t};\n\t};\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmediatek,mtd-eeprom = <&factory 0x0>;\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_28>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&esw {\n\tmediatek,portmap = <0x2f>;\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_28: macaddr@28 {\n\t\treg = <0x28 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7628an_d-team_pbr-d1.dts",
    "content": "#include \"mt7628an.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"d-team,pbr-d1\", \"mediatek,mt7628an-soc\";\n\tmodel = \"PBR-D1\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200\";\n\t};\n\n\taliases {\n\t\tserial0 = &uart2;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tusb {\n\t\t\tlabel = \"orange:usb\";\n\t\t\tgpios = <&gpio 0 GPIO_ACTIVE_LOW>;\n\t\t\ttrigger-sources = <&ohci_port1>, <&ehci_port1>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\n\t\tled_power: power {\n\t\t\tlabel = \"orange:power\";\n\t\t\tgpios = <&gpio 14 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 70 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\twgpio: gpio-wifi {\n\t\tcompatible = \"mediatek,gpio-wifi\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"gpio\";\n\t\tfunction = \"gpio\";\n\t};\n\n\ti2c {\n\t\tgroups = \"i2c\";\n\t\tfunction = \"gpio\";\n\t};\n\n\ti2s {\n\t\tgroups = \"i2s\";\n\t\tfunction = \"gpio\";\n\t};\n\n\tspis {\n\t\tgroups = \"spis\";\n\t\tfunction = \"gpio\";\n\t};\n\n\twdt {\n\t\tgroups = \"wdt\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&spi_pins>, <&spi_cs1_pins>;\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <40000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x0fb0000>;\n\t\t\t};\n\t\t};\n\t};\n\n\tspidev@1 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"linux,spidev\";\n\t\treg = <1>;\n\t\tspi-max-frequency = <40000000>;\n\t};\n};\n\n&i2c {\n\tstatus = \"okay\";\n};\n\n&uart1 {\n\tstatus = \"okay\";\n};\n\n&uart2 {\n\tstatus = \"okay\";\n};\n\n&pwm {\n\tstatus = \"okay\";\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_28>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&sdhci {\n\tstatus = \"okay\";\n\tmediatek,cd-high;\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_28: macaddr@28 {\n\t\treg = <0x28 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7628an_dlink_dap-1325-a1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7628an.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"dlink,dap-1325-a1\", \"mediatek,mt7628an-soc\";\n\tmodel = \"D-Link DAP-1325 A1\";\n\n\taliases {\n\t\tled-boot = &led_status_green;\n\t\tled-failsafe = &led_status_green;\n\t\tled-running = &led_status_green;\n\t\tled-upgrade = &led_status_red;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_status_red: status_red {\n\t\t\tlabel = \"red:status\";\n\t\t\tgpios = <&gpio 37 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_status_green: status_green {\n\t\t\tlabel = \"green:status\";\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twifi-high {\n\t\t\tlabel = \"green:wifi-high\";\n\t\t\tgpios = <&gpio 44 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twifi-mid {\n\t\t\tlabel = \"green:wifi-mid\";\n\t\t\tgpios = <&gpio 3 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twifi-low {\n\t\t\tlabel = \"green:wifi-low\";\n\t\t\tgpios = <&gpio 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twifi-verylow {\n\t\t\tlabel = \"red:wifi-verylow\";\n\t\t\tgpios = <&gpio 2 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio 45 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 38 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"refclk\", \"gpio\", \"wled_an\", \"i2s\", \"uart1\", \"wdt\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_28>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmediatek,mtd-eeprom = <&factory 0x0>;\n\n\tnvmem-cells = <&macaddr_factory_28>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <50000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x7b0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_28: macaddr@28 {\n\t\treg = <0x28 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7628an_duzun_dm06.dts",
    "content": "#include \"mt7628an.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"duzun,dm06\", \"mediatek,mt7628an-soc\";\n\tmodel = \"DuZun DM06\";\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 46 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio 38 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n\n\tsound {\n\t\tcompatible = \"simple-audio-card\";\n\t\tsimple-audio-card,name = \"Audio-I2S\";\n\t\tsimple-audio-card,format = \"i2s\";\n\t\tsimple-audio-card,bitclock-master = <&dailink0_master>;\n\t\tsimple-audio-card,frame-master = <&dailink0_master>;\n\t\tsimple-audio-card,widgets =\n\t\t\t\"Headphone\", \"Headphones\";\n\t\tsimple-audio-card,routing =\n\t\t\t\"Headphones\", \"HP_L\",\n\t\t\t\"Headphones\", \"HP_R\";\n\t\tsimple-audio-card,mclk-fs = <256>;\n\n\t\tsimple-audio-card,cpu {\n\t\t\tsound-dai = <&i2s>;\n\t\t};\n\n\t\tdailink0_master: simple-audio-card,codec {\n\t\t\tsound-dai = <&codec>;\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"wdt\", \"uart1\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&i2c {\n\tstatus = \"okay\";\n\n\tcodec: wm8960@1a {\n\t\t#sound-dai-cells = <0>;\n\t\tcompatible = \"wlf,wm8960\";\n\t\treg = <0x1a>;\n\n\t\twlf,shared-lrclk;\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&esw {\n\tmediatek,portmap = <0x3e>;\n\tmediatek,portdisable = <0x3c>;\n};\n\n&i2s {\n\t#sound-dai-cells = <0>;\n\tstatus = \"okay\";\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&i2s_pins>, <&refclk_pins>;\n};\n\n&sdhci {\n\tstatus = \"okay\";\n};\n\n&gdma {\n\tstatus = \"okay\";\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <60000000>;\n\t\tm25p,fast-read;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x7b0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7628an_elecom_wrc-1167fs.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7628an.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"elecom,wrc-1167fs\", \"mediatek,mt7628an-soc\";\n\tmodel = \"ELECOM WRC-1167FS\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan5g {\n\t\t\tlabel = \"green:wlan5g\";\n\t\t\tgpios = <&gpio 2 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"red:wps\";\n\t\t\tgpios = <&gpio 37 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tinternet {\n\t\t\tlabel = \"green:internet\";\n\t\t\tgpios = <&gpio 39 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan {\n\t\t\tlabel = \"green:lan\";\n\t\t\tgpios = <&gpio 40 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan2g {\n\t\t\tlabel = \"green:wlan2g\";\n\t\t\tgpios = <&gpio 44 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\tap {\n\t\t\tlabel = \"ap\";\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_0>;\n\t\t\tlinux,input-type = <EV_SW>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 5 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio 38 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <40000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x730000>;\n\t\t\t};\n\n\t\t\tpartition@780000 {\n\t\t\t\tlabel = \"storage\";\n\t\t\t\treg = <0x780000 0x80000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&ehci {\n\tstatus = \"disabled\";\n};\n\n&esw {\n\tmediatek,portmap = <0x2f>;\n\tmediatek,portdisable = <0x27>;\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_28>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&ohci {\n\tstatus = \"disabled\";\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\twifi@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"wled_an\", \"p3led_an\", \"p4led_an\", \"wdt\", \"refclk\", \"i2c\", \"i2s\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmediatek,mtd-eeprom = <&factory 0x0>;\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_28: macaddr@28 {\n\t\treg = <0x28 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7628an_glinet_gl-mt300n-v2.dts",
    "content": "#include \"mt7628an.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/{\n\tcompatible = \"glinet,gl-mt300n-v2\", \"mediatek,mt7628an-soc\";\n\tmodel = \"GL-MT300N-V2\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t\tlabel-mac-device = &ethernet;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200\";\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tdefault-state = \"on\";\n\t\t\tgpios = <&gpio 42 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twan {\n\t\t\tlabel = \"green:wan\";\n\t\t\tgpios = <&gpio 43 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan {\n\t\t\tlabel = \"red:wlan\";\n\t\t\tgpios = <&gpio 44 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 38 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\tBTN_0 {\n\t\t\tlabel = \"BTN_0\";\n\t\t\tgpios = <&gpio 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_0>;\n\t\t};\n\n\t\tBTN_1 {\n\t\t\tlabel = \"BTN_1\";\n\t\t\tgpios = <&gpio 3 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_1>;\n\t\t};\n\t};\n\n\tgpio_export {\n\t\tcompatible = \"gpio-export\";\n\t\t#size-cells = <0>;\n\n\t\tusb {\n\t\t\tgpio-export,name = \"usb\";\n\t\t\tgpio-export,output = <1>;\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"wdt\", \"gpio\", \"wled_an\", \"p0led_an\", \"p1led_an\", \"i2s\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmediatek,mtd-eeprom = <&factory 0x0>;\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0xfb0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&i2c {\n\tstatus = \"okay\";\n};\n\n&uart1 {\n\tstatus = \"okay\";\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7628an_glinet_microuter-n300.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7628an_glinet_vixmini_microuter.dtsi\"\n\n/ {\n\tcompatible = \"glinet,microuter-n300\", \"mediatek,mt7628an-soc\";\n\tmodel = \"GL.iNet microuter-N300\";\n};\n\n&firmware_part {\n\treg = <0x50000 0xfb0000>;\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7628an_glinet_vixmini.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7628an_glinet_vixmini_microuter.dtsi\"\n\n/ {\n\tcompatible = \"glinet,vixmini\", \"mediatek,mt7628an-soc\";\n\tmodel = \"GL.iNet VIXMINI\";\n};\n\n&firmware_part {\n\treg = <0x50000 0x7b0000>;\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7628an_glinet_vixmini_microuter.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7628an.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\taliases {\n\t\tled-boot = &led_power_blue;\n\t\tled-failsafe = &led_power_blue;\n\t\tled-running = &led_power_blue;\n\t\tled-upgrade = &led_power_blue;\n\n\t\tlabel-mac-device = &ethernet;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200\";\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power_blue: power {\n\t\t\tlabel = \"blue:power\";\n\t\t\tgpios = <&gpio 42 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan {\n\t\t\tlabel = \"white:wlan\";\n\t\t\tgpios = <&gpio 44 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 38 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"wdt\", \"wled_an\", \"p1led_an\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmediatek,mtd-eeprom = <&factory 0x0>;\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions: partitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\t/*\n\t\t\t * Firmware-partition size is model-specific\n\t\t\t * due to different flash sizes.\n\t\t\t */\n\t\t\tfirmware_part: partition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t};\n\t\t};\n\t};\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7628an_hak5_wifi-pineapple-mk7.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7628an.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"hak5,wifi-pineapple-mk7\", \"mediatek,mt7628an-soc\";\n\tmodel = \"Hak5 WiFi Pineapple Mark 7\";\n\n\taliases {\n\t\tled-boot = &led_system_blue;\n\t\tled-failsafe = &led_system_blue;\n\t\tled-upgrade = &led_system_blue;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tsystem_red {\n\t\t\tlabel = \"red:system\";\n\t\t\tgpios = <&gpio 0 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tsystem_green {\n\t\t\tlabel = \"green:system\";\n\t\t\tgpios = <&gpio 2 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tled_system_blue: system_blue {\n\t\t\tlabel = \"blue:system\";\n\t\t\tgpios = <&gpio 3 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tgpio-export {\n\t\tcompatible = \"gpio-export\";\n\t\t#size-cells = <0>;\n\n\t\tusb-power {\n\t\t\tgpio-export,name = \"usb-power\";\n\t\t\tgpio-export,output = <1>;\n\t\t\tgpios = <&gpio 5 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tsdhci@10130000 {\n\t\tcompatible = \"ralink,mt7620-sdhci\";\n\t\treg = <0x10130000 4000>;\n\n\t\tinterrupt-parent = <&intc>;\n\t\tinterrupts = <14>;\n\n\t\tstatus = \"okay\";\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"gpio\", \"i2c\", \"i2s\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <50000000>;\n\t\tbroken-flash-reset;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x1fb0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&ethernet {\n\tstatus = \"okay\";\n\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmediatek,mtd-eeprom = <&factory 0x0>;\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7628an_hilink_hlk-7628n.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7628an.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"hilink,hlk-7628n\", \"mediatek,mt7628an-soc\";\n\tmodel = \"HILINK HLK-7628N\";\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 38 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twlan {\n\t\t\tlabel = \"green:wlan\";\n\t\t\tgpios = <&gpio 44 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&uart1 {\n\tstatus = \"okay\";\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\t\tbroken-flash-reset;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x1fb0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_28>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmediatek,mtd-eeprom = <&factory 0x0>;\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_28: macaddr@28 {\n\t\treg = <0x28 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7628an_hilink_hlk-7688a.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7628an.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"hilink,hlk-7688a\", \"mediatek,mt7628an-soc\";\n\tmodel = \"Hi-Link HLK-7688A\";\n\n\taliases {\n\t\tled-boot = &led_wlan;\n\t\tled-failsafe = &led_wlan;\n\t\tled-upgrade = &led_wlan;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 38 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_wlan: wlan {\n\t\t\tlabel = \"green:wlan\";\n\t\t\tgpios = <&gpio 44 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"wdt\", \"wled_an\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&uart1 {\n\tstatus = \"okay\";\n};\n\n&i2c {\n\tstatus = \"okay\";\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&spi_pins>, <&spi_cs1_pins>;\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <40000000>;\n\t\tbroken-flash-reset;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x1fb0000>;\n\t\t\t};\n\t\t};\n\t};\n\n\tspidev@1 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"linux,spidev\";\n\t\treg = <1>;\n\t\tspi-max-frequency = <40000000>;\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_28>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&esw {\n\tmediatek,portmap = <0x3e>;\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmediatek,mtd-eeprom = <&factory 0x0>;\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_28: macaddr@28 {\n\t\treg = <0x28 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7628an_hiwifi_hc5661a.dts",
    "content": "#include \"mt7628an_hiwifi_hc5x61a.dtsi\"\n\n/ {\n\tcompatible = \"hiwifi,hc5661a\", \"mediatek,mt7628an-soc\";\n\tmodel = \"HiWiFi HC5661A\";\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_system: system {\n\t\t\tlabel = \"blue:system\";\n\t\t\tgpios = <&gpio 37 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tinternet {\n\t\t\tlabel = \"blue:internet\";\n\t\t\tgpios = <&gpio 1 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\twlan2g {\n\t\t\tlabel = \"blue:wlan2g\";\n\t\t\tgpios = <&gpio 44 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"refclk\", \"wdt\", \"wled_an\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ehci {\n\tstatus = \"disabled\";\n};\n\n&ohci {\n\tstatus = \"disabled\";\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7628an_hiwifi_hc5761a.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7628an_hiwifi_hc5x61a.dtsi\"\n\n/ {\n\tcompatible = \"hiwifi,hc5761a\", \"mediatek,mt7628an-soc\";\n\tmodel = \"HiWiFi HC5761A\";\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_system: system {\n\t\t\tlabel = \"blue:system\";\n\t\t\tgpios = <&gpio 37 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tinternet {\n\t\t\tlabel = \"blue:internet\";\n\t\t\tgpios = <&gpio 1 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\twlan2g {\n\t\t\tlabel = \"blue:wlan2g\";\n\t\t\tgpios = <&gpio 44 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\twlan5g {\n\t\t\tlabel = \"blue:wlan5g\";\n\t\t\tgpios = <&gpio 40 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\t};\n\n\tgpio_export {\n\t\tcompatible = \"gpio-export\";\n\t\t#size-cells = <0>;\n\n\t\tusb_power {\n\t\t\tgpio-export,name = \"usb_power\";\n\t\t\tgpio-export,output = <0>;\n\t\t\tgpios = <&gpio 41 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"refclk\", \"wdt\", \"p2led_an\", \"p3led_an\", \"wled_an\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\twifi@0,0 {\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7628an_hiwifi_hc5861b.dts",
    "content": "#include \"mt7628an_hiwifi_hc5x61a.dtsi\"\n\n/ {\n\tcompatible = \"hiwifi,hc5861b\", \"mediatek,mt7628an-soc\";\n\tmodel = \"HiWiFi HC5861B\";\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_system: system {\n\t\t\tlabel = \"green:system\";\n\t\t\tgpios = <&gpio 37 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan2g {\n\t\t\tlabel = \"green:wlan2g\";\n\t\t\tgpios = <&gpio 44 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"refclk\", \"wdt\", \"wled_an\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ehci {\n\tstatus = \"disabled\";\n};\n\n&ohci {\n\tstatus = \"disabled\";\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\twifi@0,0 {\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t\tnvmem-cells = <&macaddr_factory_2e>;\n\t\tnvmem-cell-names = \"mac-address\";\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\n\t\tled {\n\t\t\tled-sources = <2>;\n\t\t\tled-active-low;\n\t\t};\n\t};\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_2e: macaddr@2e {\n\t\treg = <0x2e 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7628an_hiwifi_hc5x61a.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7628an.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"hiwifi,hc5x61a\", \"mediatek,mt7628an-soc\";\n\n\taliases {\n\t\tled-boot = &led_system;\n\t\tled-failsafe = &led_system;\n\t\tled-running = &led_system;\n\t\tled-upgrade = &led_system;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 38 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <80000000>;\n\t\tm25p,fast-read;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"hw_panic\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0xf70000>;\n\t\t\t};\n\n\t\t\tpartition@fc0000 {\n\t\t\t\tlabel = \"oem\";\n\t\t\t\treg = <0xfc0000 0x20000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tbdinfo: partition@fe0000 {\n\t\t\t\tlabel = \"bdinfo\";\n\t\t\t\treg = <0xfe0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@ff0000 {\n\t\t\t\tlabel = \"backup\";\n\t\t\t\treg = <0xff0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmediatek,mtd-eeprom = <&factory 0x0>;\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7628an_iptime.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7628an.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\taliases {\n\t\tlabel-mac-device = &ethernet;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 38 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio 45 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t\tdebounce-interval = <60>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <40000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tuboot: partition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x20000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tlabel = \"config\";\n\t\t\t\treg = <0x20000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@30000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x40000 0x7c0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"uart1\", \"wdt\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ehci {\n\tstatus = \"disabled\";\n};\n\n&ohci {\n\tstatus = \"disabled\";\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_uboot_1fc20>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\twifi@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\t};\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmediatek,mtd-eeprom = <&factory 0x0>;\n};\n\n&uboot {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_uboot_1fc20: macaddr@1fc20 {\n\t\treg = <0x1fc20 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7628an_iptime_a3.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7628an_iptime.dtsi\"\n\n/ {\n\tcompatible = \"iptime,a3\", \"mediatek,mt7628an-soc\";\n\tmodel = \"ipTIME A3\";\n\n\taliases {\n\t\tled-boot = &led_cpu;\n\t\tled-failsafe = &led_cpu;\n\t\tled-running = &led_cpu;\n\t\tled-upgrade = &led_cpu;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_cpu: cpu {\n\t\t\tlabel = \"blue:cpu\";\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan {\n\t\t\tlabel = \"blue:wlan\";\n\t\t\tgpios = <&gpio 46 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\t};\n};\n\n&esw {\n\tmediatek,portmap = <0x3e>;\n\tmediatek,portdisable = <0x32>;\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7628an_iptime_a604m.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7628an_iptime.dtsi\"\n\n/ {\n\tcompatible = \"iptime,a604m\", \"mediatek,mt7628an-soc\";\n\tmodel = \"ipTIME A604M\";\n\n\taliases {\n\t\tled-boot = &led_cpu;\n\t\tled-failsafe = &led_cpu;\n\t\tled-running = &led_cpu;\n\t\tled-upgrade = &led_cpu;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twlan5g {\n\t\t\tlabel = \"blue:wlan5g\";\n\t\t\tgpios = <&gpio 5 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\n\t\tled_cpu: cpu {\n\t\t\tlabel = \"blue:cpu\";\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan2g {\n\t\t\tlabel = \"blue:wlan2g\";\n\t\t\tgpios = <&gpio 46 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"uart1\", \"wdt\";\n\t\tfunction = \"gpio\";\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7628an_jotale_js76x8-16m.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7628an_jotale_js76x8.dtsi\"\n\n/ {\n\tcompatible = \"jotale,js76x8-16m\", \"jotale,js76x8\", \"mediatek,mt7628an-soc\";\n\tmodel = \"Jotale JS76x8 (16M)\";\n};\n\n&firmware {\n\treg = <0x50000 0xfb0000>;\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7628an_jotale_js76x8-32m.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7628an_jotale_js76x8.dtsi\"\n\n/ {\n\tcompatible = \"jotale,js76x8-32m\", \"jotale,js76x8\", \"mediatek,mt7628an-soc\";\n\tmodel = \"Jotale JS76x8 (32M)\";\n};\n\n&flash0 {\n\tbroken-flash-reset;\n};\n\n&firmware {\n\treg = <0x50000 0x1fb0000>;\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7628an_jotale_js76x8-8m.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7628an_jotale_js76x8.dtsi\"\n\n/ {\n\tcompatible = \"jotale,js76x8-8m\", \"mediatek,mt7628an-soc\";\n\tmodel = \"Jotale JS76x8 (8M)\";\n};\n\n&firmware {\n\treg = <0x50000 0x7b0000>;\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7628an_jotale_js76x8.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7628an.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"jotale,js76x8\", \"mediatek,mt7628an-soc\";\n\n\taliases {\n\t\tled-boot = &led_system;\n\t\tled-failsafe = &led_system;\n\t\tled-running = &led_system;\n\t\tled-upgrade = &led_system;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200\";\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_system: system {\n\t\t\tlabel = \"green:system\";\n\t\t\tgpios = <&gpio 37 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twifi {\n\t\t\tlabel = \"green:wifi\";\n\t\t\tgpios = <&gpio 44 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 38 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"refclk\", \"wdt\", \"wled_an\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&spi_pins>, <&spi_cs1_pins>;\n\n\tflash0: flash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <40000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfirmware: partition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\t/* reg property is set based on flash size in DTS files */\n\t\t\t};\n\t\t};\n\t};\n};\n\n&i2c {\n\tstatus = \"okay\";\n};\n\n&i2s {\n\tstatus = \"okay\";\n};\n\n&uart1 {\n\tstatus = \"okay\";\n};\n\n&uart2 {\n\tstatus = \"okay\";\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_28>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&sdhci {\n\tstatus = \"okay\";\n\tmediatek,cd-low;\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmediatek,mtd-eeprom = <&factory 0x0>;\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_28: macaddr@28 {\n\t\treg = <0x28 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7628an_mediatek_linkit-smart-7688.dts",
    "content": "#include \"mt7628an.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"mediatek,linkit-smart-7688\", \"mediatek,mt7628an-soc\";\n\tmodel = \"MediaTek LinkIt Smart 7688\";\n\n\taliases {\n\t\tled-boot = &led_wifi;\n\t\tled-failsafe = &led_wifi;\n\t\tled-running = &led_wifi;\n\t\tled-upgrade = &led_wifi;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyS2,57600\";\n\t};\n\n\taliases {\n\t\tserial0 = &uart2;\n\t};\n\n\tbootstrap {\n\t\tcompatible = \"mediatek,linkit\";\n\n\t\tstatus = \"okay\";\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_wifi: wifi {\n\t\t\tlabel = \"orange:wifi\";\n\t\t\tgpios = <&gpio 44 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\twps {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 38 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"gpio\";\n\t\tfunction = \"gpio\";\n\t};\n\n\trefclk {\n\t\tgroups = \"refclk\";\n\t\tfunction = \"gpio\";\n\t};\n\n\ti2s {\n\t\tgroups = \"i2s\";\n\t\tfunction = \"gpio\";\n\t};\n\n\tspis {\n\t\tgroups = \"spis\";\n\t\tfunction = \"gpio\";\n\t};\n\n\twled_an {\n\t\tgroups = \"wled_an\";\n\t\tfunction = \"gpio\";\n\t};\n\n\twdt {\n\t\tgroups = \"wdt\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&spi_pins>, <&spi_cs1_pins>;\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <40000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x1fb0000>;\n\t\t\t};\n\t\t};\n\t};\n\n\tspidev@1 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"linux,spidev\";\n\t\treg = <1>;\n\t\tspi-max-frequency = <40000000>;\n\t};\n};\n\n&i2c {\n\tstatus = \"okay\";\n};\n\n&uart1 {\n\tstatus = \"okay\";\n};\n\n&uart2 {\n\tstatus = \"okay\";\n};\n\n&pwm {\n\tstatus = \"okay\";\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_2e>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&sdhci {\n\tstatus = \"okay\";\n\tmediatek,cd-high;\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmediatek,mtd-eeprom = <&factory 0x0>;\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_2e: macaddr@2e {\n\t\treg = <0x2e 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7628an_mediatek_mt7628an-eval-board.dts",
    "content": "#include \"mt7628an.dtsi\"\n\n/ {\n\tcompatible = \"mediatek,mt7628an-eval-board\", \"mediatek,mt7628an-soc\";\n\tmodel = \"Mediatek MT7628AN evaluation board\";\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x7b0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmediatek,mtd-eeprom = <&factory 0x0>;\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7628an_mercury_mac1200r-v2.dts",
    "content": "#include \"mt7628an.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"mercury,mac1200r-v2\", \"mediatek,mt7628an-soc\";\n\tmodel = \"Mercury MAC1200R v2\";\n\n\taliases {\n\t\tled-boot = &led_status;\n\t\tled-failsafe = &led_status;\n\t\tled-running = &led_status;\n\t\tled-upgrade = &led_status;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_status: status {\n\t\t\tlabel = \"green:status\";\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x1d800>;\n\t\t\t};\n\n\t\t\tfactory: partition@1d800 {\n\t\t\t\tlabel = \"factory_info\";\n\t\t\t\treg = <0x1d800 0x800>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tart: partition@1e000 {\n\t\t\t\tlabel = \"art\";\n\t\t\t\treg = <0x1e000 0x2000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tlabel = \"config\";\n\t\t\t\treg = <0x20000 0x10000>;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot2\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x40000 0x7c0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&ethernet {\n\tpinctrl-names = \"default\";\n\tnvmem-cells = <&macaddr_factory_d>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&esw {\n\tmediatek,portmap = <0x2f>;\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmediatek,mtd-eeprom = <&factory 0x0>;\n\tralink,mtd-eeprom = <&art 0x0>;\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\tmt76@0,0 {\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&art 0x1000>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\t};\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_d: macaddr@d {\n\t\treg = <0xd 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7628an_minew_g1-c.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7628an.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"Minew G1-C\";\n\tcompatible = \"minew,g1-c\", \"mediatek,mt7628an-soc\";\n\n\taliases {\n\t\tled-boot = &led_system;\n\t\tled-failsafe = &led_system;\n\t\tled-running = &led_system;\n\t\tled-upgrade = &led_system;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 38 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_system: system {\n\t\t\tlabel = \"red:system\";\n\t\t\tgpios = <&gpio 43 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\tgpio-export {\n\t\tcompatible = \"gpio-export\";\n\t\t#size-cells = <0>;\n\n\t\tws2812 {\n\t\t\tgpio-export,name = \"ws2812\";\n\t\t\tgpio-export,output = <1>;\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tnrf_power {\n\t\t\tgpio-export,name = \"nrf_power\";\n\t\t\tgpio-export,output = <1>;\n\t\t\tgpios = <&gpio 45 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"gpio\";\n\t\tfunction = \"gpio\";\n\t};\n\n\tp0led_an {\n\t\tgroups = \"p0led_an\";\n\t\tfunction = \"gpio\";\n\t};\n\n\tuart1 {\n\t\tgroups = \"uart1\";\n\t\tfunction = \"gpio\";\n\t};\n\n\twdt {\n\t\tgroups = \"wdt\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&spi_pins>, <&spi_cs1_pins>;\n\n\tm25p80@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <40000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0xfb0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_28>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&esw {\n\tmediatek,portmap = <0x3e>;\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmediatek,mtd-eeprom = <&factory 0x0>;\n};\n\n&sdhci {\n\tstatus = \"okay\";\n\tmediatek,cd-high;\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_28: macaddr@28 {\n\t\treg = <0x28 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7628an_motorola_mwr03.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7628an.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tmodel = \"Motorola MWR03\";\n\tcompatible = \"motorola,mwr03\", \"mediatek,mt7628an-soc\";\n\n\taliases {\n\t\tled-boot = &led_status_orange;\n\t\tled-failsafe = &led_status_orange;\n\t\tled-running = &led_status_white;\n\t\tled-upgrade = &led_status_orange;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 5 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_status_orange: status_orange {\n\t\t\tlabel = \"orange:status\";\n\t\t\tgpios = <&gpio 3 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_status_white: status_white {\n\t\t\tlabel = \"white:status\";\n\t\t\tgpios = <&gpio 2 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <80000000>;\n\t\tm25p,fast-read;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"bootloader\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"config\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x7b0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"i2s\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&usbphy {\n\tstatus = \"disabled\";\n};\n\n&ehci {\n\tstatus = \"disabled\";\n};\n\n&ohci {\n\tstatus = \"disabled\";\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <(-1)>;\n};\n\n&esw {\n\tmediatek,portmap = <0x3e>;\n\tmediatek,portdisable = <0x30>;\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\twifi@0,0 {\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\t};\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmediatek,mtd-eeprom = <&factory 0x0>;\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7628an_netgear_r6020.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7628an_netgear_r6xxx.dtsi\"\n\n/ {\n\tcompatible = \"netgear,r6020\", \"mediatek,mt7628an-soc\";\n\tmodel = \"Netgear R6020\";\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"p0led_an\", \"p1led_an\", \"p2led_an\", \"p3led_an\",\n\t\t         \"p4led_an\", \"wdt\", \"wled_an\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&partitions {\n\tpartition@90000 {\n\t\tcompatible = \"denx,uimage\";\n\t\tlabel = \"firmware\";\n\t\treg = <0x90000 0x6f0000>;\n\t};\n\n\tpartition@780000 {\n\t\tlabel = \"ML\";\n\t\treg = <0x780000 0x20000>;\n\t\tread-only;\n\t};\n\n\tpartition@7a0000 {\n\t\tlabel = \"ML1\";\n\t\treg = <0x7a0000 0x20000>;\n\t\tread-only;\n\t};\n\n\tpartition@7c0000 {\n\t\tlabel = \"ML2\";\n\t\treg = <0x7c0000 0x20000>;\n\t\tread-only;\n\t};\n\n\tpartition@7e0000 {\n\t\tlabel = \"POT\";\n\t\treg = <0x7e0000 0x10000>;\n\t\tread-only;\n\t};\n\n\tpartition@7f0000 {\n\t\tlabel = \"reserved\";\n\t\treg = <0x7f0000 0x10000>;\n\t\tread-only;\n\t};\n};\n\n&ehci {\n\tstatus = \"disabled\";\n};\n\n&ohci {\n\tstatus = \"disabled\";\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7628an_netgear_r6080.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7628an_netgear_r6xxx.dtsi\"\n\n/ {\n\tcompatible = \"netgear,r6080\", \"mediatek,mt7628an-soc\";\n\tmodel = \"Netgear R6080\";\n\n\taliases {\n\t\tlabel-mac-device = &ethernet;\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"p0led_an\", \"p1led_an\", \"p2led_an\", \"p3led_an\",\n\t\t         \"p4led_an\", \"wdt\", \"wled_an\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&partitions {\n\tpartition@90000 {\n\t\tcompatible = \"denx,uimage\";\n\t\tlabel = \"firmware\";\n\t\treg = <0x90000 0x760000>;\n\t};\n\n\tpartition@7f0000 {\n\t\tlabel = \"reserved\";\n\t\treg = <0x7f0000 0x10000>;\n\t\tread-only;\n\t};\n};\n\n&ehci {\n\tstatus = \"disabled\";\n};\n\n&ohci {\n\tstatus = \"disabled\";\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7628an_netgear_r6120.dts",
    "content": "#include \"mt7628an_netgear_r6xxx.dtsi\"\n\n/ {\n\tcompatible = \"netgear,r6120\", \"mediatek,mt7628an-soc\";\n\tmodel = \"Netgear R6120\";\n\n\taliases {\n\t\tlabel-mac-device = &ethernet;\n\t};\n\n\tusb-regulator {\n\t\tcompatible = \"regulator-fixed\";\n\n\t\tregulator-name = \"USB-power\";\n\t\tgpio = <&gpio 45 GPIO_ACTIVE_HIGH>;\n\t\tregulator-min-microvolt = <5000000>;\n\t\tregulator-max-microvolt = <5000000>;\n\t\tenable-active-high;\n\n\t\tregulator-always-on;\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"p0led_an\", \"p1led_an\", \"p2led_an\", \"p3led_an\",\n\t\t         \"p4led_an\", \"wdt\", \"wled_an\", \"uart1\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&partitions {\n\tpartition@90000 {\n\t\tcompatible = \"denx,uimage\";\n\t\tlabel = \"firmware\";\n\t\treg = <0x90000 0xf60000>;\n\t};\n\n\tpartition@ff0000 {\n\t\tlabel = \"reserved\";\n\t\treg = <0xff0000 0x10000>;\n\t\tread-only;\n\t};\n};\n\n&wifi5 {\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <(2)>;\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7628an_netgear_r6xxx.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7628an.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 38 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tlan {\n\t\t\tlabel = \"green:lan\";\n\t\t\tgpios = <&gpio 44 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_power: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 43 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan2g_green {\n\t\t\tlabel = \"green:wlan2g\";\n\t\t\tgpios = <&gpio 42 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\twlan2g_orange {\n\t\t\tlabel = \"orange:wlan2g\";\n\t\t\tgpios = <&gpio 41 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twan_green {\n\t\t\tlabel = \"green:wan\";\n\t\t\tgpios = <&gpio 40 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twan_orange {\n\t\t\tlabel = \"orange:wan\";\n\t\t\tgpios = <&gpio 39 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <86000000>;\n\t\tm25p,fast-read;\n\n\t\tpartitions: partitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x40000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x20000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@60000 {\n\t\t\t\tlabel = \"nvram\";\n\t\t\t\treg = <0x60000 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmediatek,mtd-eeprom = <&factory 0x0>;\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\twifi5: wifi@0,0 {\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\t};\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7628an_onion_omega2.dts",
    "content": "#include \"mt7628an_onion_omega2.dtsi\"\n\n/ {\n\tcompatible = \"onion,omega2\", \"mediatek,mt7628an-soc\";\n\tmodel = \"Onion Omega2\";\n};\n\n&firmware {\n\treg = <0x50000 0xfb0000>;\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7628an_onion_omega2.dtsi",
    "content": "#include \"mt7628an.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"onion,omega2\", \"mediatek,mt7628an-soc\";\n\n\taliases {\n\t\tled-boot = &led_system;\n\t\tled-failsafe = &led_system;\n\t\tled-running = &led_system;\n\t\tled-upgrade = &led_system;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200\";\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_system: system {\n\t\t\tlabel = \"amber:system\";\n\t\t\tgpios = <&gpio 44 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 38 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"gpio\";\n\t\tfunction = \"gpio\";\n\t};\n\n\tperst {\n\t\tgroups = \"perst\";\n\t\tfunction = \"gpio\";\n\t};\n\n\trefclk {\n\t\tgroups = \"refclk\";\n\t\tfunction = \"gpio\";\n\t};\n\n\ti2s {\n\t\tgroups = \"i2s\";\n\t\tfunction = \"gpio\";\n\t};\n\n\tspis {\n\t\tgroups = \"spis\";\n\t\tfunction = \"gpio\";\n\t};\n\n\twled_kn {\n\t\tgroups = \"wled_kn\";\n\t\tfunction = \"gpio\";\n\t};\n\n\twled_an {\n\t\tgroups = \"wled_an\";\n\t\tfunction = \"gpio\";\n\t};\n\n\twdt {\n\t\tgroups = \"wdt\";\n\t\tfunction = \"gpio\";\n\t};\n\n\tpwm0 {\n\t\tgroups = \"pwm0\";\n\t\tfunction = \"gpio\";\n\t};\n\n\tpwm1 {\n\t\tgroups = \"pwm1\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&spi_pins>, <&spi_cs1_pins>;\n\n\tflash0: flash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <40000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfirmware: partition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t};\n\t\t};\n\t};\n\n\tspidev@1 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"linux,spidev\";\n\t\treg = <1>;\n\t\tspi-max-frequency = <40000000>;\n\t};\n};\n\n&i2c {\n\tstatus = \"okay\";\n};\n\n&uart1 {\n\tstatus = \"okay\";\n};\n\n&uart2 {\n\tstatus = \"okay\";\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_28>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&sdhci {\n\tstatus = \"okay\";\n\tmediatek,cd-low;\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmediatek,mtd-eeprom = <&factory 0x0>;\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_28: macaddr@28 {\n\t\treg = <0x28 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7628an_onion_omega2p.dts",
    "content": "#include \"mt7628an_onion_omega2.dtsi\"\n\n/ {\n\tcompatible = \"onion,omega2p\", \"onion,omega2\", \"mediatek,mt7628an-soc\";\n\tmodel = \"Onion Omega2+\";\n};\n\n&flash0 {\n\tbroken-flash-reset;\n};\n\n&firmware {\n\treg = <0x50000 0x1fb0000>;\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7628an_rakwireless_rak633.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7628an.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"rakwireless,rak633\", \"mediatek,mt7628an-soc\";\n\tmodel = \"Rakwireless RAK633\";\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twifi {\n\t\t\tlabel = \"blue:wifi\";\n\t\t\tgpios = <&gpio 44 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&state_default {\n\twled_an {\n\t\tgroups = \"wled_an\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x7b0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&i2c {\n\tstatus = \"okay\";\n};\n\n&i2s {\n\tstatus = \"okay\";\n};\n\n&uart1 {\n\tstatus = \"okay\";\n};\n\n&uart2 {\n\tstatus = \"okay\";\n};\n\n&gdma {\n\tstatus = \"okay\";\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_28>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmediatek,mtd-eeprom = <&factory 0x0>;\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_28: macaddr@28 {\n\t\treg = <0x28 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7628an_ravpower_rp-wd009.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7628an.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"ravpower,rp-wd009\", \"mediatek,mt7628an-soc\";\n\tmodel = \"RAVPower RP-WD009\";\n\n\taliases {\n\t\tled-boot = &led_globe;\n\t\tled-failsafe = &led_globe;\n\t\tled-running = &led_globe;\n\t\tled-upgrade = &led_globe;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_globe: globe {\n\t\t\tlabel = \"white:globe\";\n\t\t\tgpios = <&gpio 43 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan2 {\n\t\t\tlabel = \"white:wlan2\";\n\t\t\tgpios = <&gpio 44 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\twlan5 {\n\t\t\tlabel = \"white:wlan5\";\n\t\t\tgpios = <&gpio 18 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\n\t\tsd_white {\n\t\t\tlabel = \"white:sd\";\n\t\t\tgpios = <&gpio 41 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tsd_red {\n\t\t\tlabel = \"red:sd\";\n\t\t\tgpios = <&gpio 3 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 46 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\t/* Power interrupt on Pin 39 */\n\n\t\trfkill {\n\t\t\tlabel = \"rfkill\";\n\t\t\tgpios = <&gpio 21 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RFKILL>;\n\t\t};\n\n\t\tbackup {\n\t\t\tlabel = \"backup\";\n\t\t\tgpios = <&gpio 40 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_COPY>;\n\t\t};\n\t};\n};\n\n&gpio {\n\tmt7610-power {\n\t\tgpio-hog;\n\t\tgpios = <20 GPIO_ACTIVE_HIGH>;\n\t\toutput-high;\n\t\tline-name = \"mt7610-power\";\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"uart1\", \"wled_an\", \"p0led_an\", \"p2led_an\", \"p3led_an\",\n\t\t\t\t\"p4led_an\", \"uart2\", \"pwm0\", \"i2s\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&sdhci {\n\tstatus = \"okay\";\n};\n\n&i2c {\n\tstatus = \"okay\";\n\n\t/* Custom PMIC at 0x0a */\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\twifi@0,0 {\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t\tieee80211-freq-limit = <5470000 6000000>;\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <40000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"bootloader\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"config\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tlabel = \"loader\";\n\t\t\t\treg = <0x50000 0x180000>;\n\t\t\t};\n\n\t\t\tpartition@1d0000 {\n\t\t\t\tlabel = \"params\";\n\t\t\t\treg = <0x1d0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@1e0000 {\n\t\t\t\tlabel = \"user_backup\";\n\t\t\t\treg = <0x1e0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@1f0000 {\n\t\t\t\tlabel = \"user\";\n\t\t\t\treg = <0x1f0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@200000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x200000 0xdf0000>;\n\t\t\t};\n\n\t\t\tpartition@ff0000 {\n\t\t\t\tlabel = \"mode\";\n\t\t\t\treg = <0xff0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmediatek,mtd-eeprom = <&factory 0x0>;\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7628an_skylab_skw92a.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7628an.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"skylab,skw92a\", \"mediatek,mt7628an-soc\";\n\tmodel = \"SKYLAB SKW92A\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: wps {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&gpio 37 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan {\n\t\t\tlabel = \"green:wlan\";\n\t\t\tgpios = <&gpio 44 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 38 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"wdt\", \"refclk\", \"wled_an\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_28>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmediatek,mtd-eeprom = <&factory 0x0>;\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0xfb0000>;\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t};\n\t\t};\n\t};\n};\n\n&uart1 {\n\tstatus = \"okay\";\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_28: macaddr@28 {\n\t\treg = <0x28 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7628an_tama_w06.dts",
    "content": "#include \"mt7628an.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"tama,w06\", \"mediatek,mt7628an-soc\";\n\tmodel = \"Tama W06\";\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twps {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twan {\n\t\t\tlabel = \"green:wan\";\n\t\t\tgpios = <&gpio 43 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twireless {\n\t\t\tlabel = \"green:wlan\";\n\t\t\tgpios = <&gpio 46 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 38 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_28>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"uart1\", \"p0led_an\", \"wdt\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0xeb0000>;\n\t\t\t};\n\n\t\t\tpartition@f00000 {\n\t\t\t\tlabel = \"user-data\";\n\t\t\t\treg = <0xf00000 0x100000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmediatek,mtd-eeprom = <&factory 0x0>;\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_28: macaddr@28 {\n\t\treg = <0x28 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7628an_totolink_a3.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7628an_iptime.dtsi\"\n\n/ {\n\tcompatible = \"totolink,a3\", \"mediatek,mt7628an-soc\";\n\tmodel = \"TOTOLINK A3\";\n\n\taliases {\n\t\tled-boot = &led_cpu;\n\t\tled-failsafe = &led_cpu;\n\t\tled-running = &led_cpu;\n\t\tled-upgrade = &led_cpu;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_cpu: cpu {\n\t\t\tlabel = \"blue:cpu\";\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan {\n\t\t\tlabel = \"blue:wlan\";\n\t\t\tgpios = <&gpio 46 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\t};\n};\n\n&esw {\n\tmediatek,portmap = <0x3e>;\n\tmediatek,portdisable = <0x32>;\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7628an_totolink_lr1200.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7628an.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"totolink,lr1200\", \"mediatek,mt7628dan\";\n\tmodel = \"TOTOLINK LR1200\";\n\n\taliases {\n\t\tled-boot = &led_sys;\n\t\tled-failsafe = &led_sys;\n\t\tled-running = &led_sys;\n\t\tled-upgrade = &led_sys;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_sys: sys {\n\t\t\tlabel = \"blue:sys\";\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tsms {\n\t\t\tlabel = \"blue:sms\";\n\t\t\tgpios = <&gpio 37 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twifi {\n\t\t\tlabel = \"blue:wifi\";\n\t\t\tgpios = <&gpio 44 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\t3g {\n\t\t\tlabel = \"blue:3g\";\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\t4g {\n\t\t\tlabel = \"blue:4g\";\n\t\t\tgpios = <&gpio 5 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\trssi1 {\n\t\t\tlabel = \"blue:rssi1\";\n\t\t\tgpios = <&gpio 46 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\trssi2 {\n\t\t\tlabel = \"blue:rssi2\";\n\t\t\tgpios = <&gpio 3 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\trssi3 {\n\t\t\tlabel = \"blue:rssi3\";\n\t\t\tgpios = <&gpio 2 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\trssi4 {\n\t\t\tlabel = \"blue:rssi4\";\n\t\t\tgpios = <&gpio 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 38 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n};\n\n&gpio {\n\tgpio_modem_reset {\n\t\tgpio-hog;\n\t\tgpios = <45 GPIO_ACTIVE_HIGH>;\n\t\toutput-high;\n\t\tline-name = \"modem-reset\";\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"gpio\", \"i2c\", \"i2s\", \"refclk\", \"uart1\", \"wdt\", \"wled_an\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\tmt76@0,0 {\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\t};\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmediatek,mtd-eeprom = <&factory 0x0>;\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_28>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <40000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x7b0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_28: macaddr@28 {\n\t\treg = <0x28 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7628an_tplink_8m-split-uboot.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7628an.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200\";\n\t};\n\n\taliases {\n\t\tlabel-mac-device = &ethernet;\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"factory-uboot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"boot\";\n\t\t\t\treg = <0x30000 0x20000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"tplink,firmware\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x770000>;\n\t\t\t};\n\n\t\t\tpartition@7c0000 {\n\t\t\t\tlabel = \"config\";\n\t\t\t\treg = <0x7c0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\trom: partition@7d0000 {\n\t\t\t\tlabel = \"rom\";\n\t\t\t\treg = <0x7d0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@7e0000 {\n\t\t\t\tlabel = \"romfile\";\n\t\t\t\treg = <0x7e0000 0x10000>;\n\t\t\t};\n\n\t\t\tradio: partition@7f0000 {\n\t\t\t\tlabel = \"radio\";\n\t\t\t\treg = <0x7f0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmediatek,mtd-eeprom = <&radio 0x0>;\n\n\tnvmem-cells = <&macaddr_rom_f100>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_rom_f100>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&esw {\n\tmediatek,portmap = <0x3e>;\n};\n\n&rom {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_rom_f100: macaddr@f100 {\n\t\treg = <0xf100 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7628an_tplink_8m.dtsi",
    "content": "#include \"mt7628an.dtsi\"\n\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/gpio/gpio.h>\n\n/ {\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200\";\n\t};\n\n\taliases {\n\t\tlabel-mac-device = &ethernet;\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"boot\";\n\t\t\t\treg = <0x0 0x20000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tcompatible = \"tplink,firmware\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x20000 0x7a0000>;\n\t\t\t};\n\n\t\t\tpartition@7c0000 {\n\t\t\t\tlabel = \"config\";\n\t\t\t\treg = <0x7c0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@7d0000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x7d0000 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmediatek,mtd-eeprom = <&factory 0x20000>;\n\n\tnvmem-cells = <&macaddr_factory_f100>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_f100>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_f100: macaddr@f100 {\n\t\treg = <0xf100 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7628an_tplink_archer-c20-v4.dts",
    "content": "#include \"mt7628an_tplink_8m.dtsi\"\n\n/ {\n\tcompatible = \"tplink,archer-c20-v4\", \"mediatek,mt7628an-soc\";\n\tmodel = \"TP-Link Archer C20 v4\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tlan {\n\t\t\tlabel = \"green:lan\";\n\t\t\tgpios = <&gpio 42 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_power: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 2 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twan {\n\t\t\tlabel = \"green:wan\";\n\t\t\tgpios = <&gpio 43 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twan_orange {\n\t\t\tlabel = \"orange:wan\";\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan5g {\n\t\t\tlabel = \"green:wlan5g\";\n\t\t\tgpios = <&gpio 40 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\n\t\twlan2g {\n\t\t\tlabel = \"green:wlan2g\";\n\t\t\tgpios = <&gpio 39 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&gpio 41 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 38 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\trfkill {\n\t\t\tlabel = \"rfkill\";\n\t\t\tgpios = <&gpio 37 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RFKILL>;\n\t\t};\n\t};\n};\n\n&ehci {\n\tstatus = \"disabled\";\n};\n\n&ohci {\n\tstatus = \"disabled\";\n};\n\n&wmac {\n\tmac-address-increment = <(-2)>;\n};\n\n&esw {\n\tmediatek,portmap = <0x3e>;\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2s\", \"gpio\", \"refclk\", \"p0led_an\", \"p1led_an\", \"p2led_an\", \"p3led_an\", \"p4led_an\", \"wdt\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\tmt76@0,0 {\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x28000>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\t\tnvmem-cells = <&macaddr_factory_f100>;\n\t\tnvmem-cell-names = \"mac-address\";\n\t\tmac-address-increment = <(-1)>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7628an_tplink_archer-c20-v5.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7628an_tplink_8m-split-uboot.dtsi\"\n\n/ {\n\tcompatible = \"tplink,archer-c20-v5\", \"mediatek,mt7628an-soc\";\n\tmodel = \"TP-Link Archer C20 v5\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 38 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\trfkill {\n\t\t\tlabel = \"rfkill\";\n\t\t\tgpios = <&gpio 37 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RFKILL>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 2 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan2g {\n\t\t\tlabel = \"green:wlan2g\";\n\t\t\tgpios = <&gpio 39 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\twlan5g {\n\t\t\tlabel = \"green:wlan5g\";\n\t\t\tgpios = <&gpio 40 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\n\t\tlan {\n\t\t\tlabel = \"green:lan\";\n\t\t\tgpios = <&gpio 42 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twan_green {\n\t\t\tlabel = \"green:wan\";\n\t\t\tgpios = <&gpio 43 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twan_orange {\n\t\t\tlabel = \"orange:wan\";\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&gpio 41 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&ehci {\n\tstatus = \"disabled\";\n};\n\n&ohci {\n\tstatus = \"disabled\";\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2s\", \"gpio\", \"refclk\", \"p0led_an\", \"p1led_an\",\n\t\t\t\t\t\"p2led_an\", \"p3led_an\", \"p4led_an\", \"wdt\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\twifi@0,0 {\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&radio 0x8000>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\t\tnvmem-cells = <&macaddr_rom_f100>;\n\t\tnvmem-cell-names = \"mac-address\";\n\t\tmac-address-increment = <(-1)>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7628an_tplink_archer-c50-v3.dts",
    "content": "#include \"mt7628an_tplink_8m.dtsi\"\n\n/ {\n\tcompatible = \"tplink,archer-c50-v3\", \"mediatek,mt7628an-soc\";\n\tmodel = \"TP-Link Archer C50 v3\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 38 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\trfkill {\n\t\t\tlabel = \"rfkill\";\n\t\t\tgpios = <&gpio 5 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RFKILL>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tlan {\n\t\t\tlabel = \"green:lan\";\n\t\t\tgpios = <&gpio 41 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_power: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twan {\n\t\t\tlabel = \"green:wan\";\n\t\t\tgpios = <&gpio 39 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twan_orange {\n\t\t\tlabel = \"orange:wan\";\n\t\t\tgpios = <&gpio 40 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan {\n\t\t\tlabel = \"green:wlan2g\";\n\t\t\tgpios = <&gpio 44 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan5 {\n\t\t\tlabel = \"green:wlan5g\";\n\t\t\tgpios = <&gpio 42 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&gpio 43 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&ehci {\n\tstatus = \"disabled\";\n};\n\n&ohci {\n\tstatus = \"disabled\";\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"gpio\", \"p0led_an\", \"p1led_an\", \"p2led_an\",\n\t\t\t\t   \"p3led_an\", \"p4led_an\", \"wdt\", \"wled_an\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&esw {\n\tmediatek,portmap = <0x3e>;\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\tmt76@0,0 {\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x28000>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\t\tnvmem-cells = <&macaddr_factory_f100>;\n\t\tnvmem-cell-names = \"mac-address\";\n\t\tmac-address-increment = <(-1)>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7628an_tplink_archer-c50-v4.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7628an_tplink_8m-split-uboot.dtsi\"\n\n/ {\n\tcompatible = \"tplink,archer-c50-v4\", \"mediatek,mt7628an-soc\";\n\tmodel = \"TP-Link Archer C50 v4\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 38 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\trfkill {\n\t\t\tlabel = \"rfkill\";\n\t\t\tgpios = <&gpio 5 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RFKILL>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan2 {\n\t\t\tlabel = \"green:wlan2g\";\n\t\t\tgpios = <&gpio 44 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan5 {\n\t\t\tlabel = \"green:wlan5g\";\n\t\t\tgpios = <&gpio 42 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan {\n\t\t\tlabel = \"green:lan\";\n\t\t\tgpios = <&gpio 41 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twan {\n\t\t\tlabel = \"green:wan\";\n\t\t\tgpios = <&gpio 39 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twan_orange {\n\t\t\tlabel = \"orange:wan\";\n\t\t\tgpios = <&gpio 40 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&gpio 43 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&ehci {\n\tstatus = \"disabled\";\n};\n\n&ohci {\n\tstatus = \"disabled\";\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"p0led_an\", \"p1led_an\", \"p2led_an\",\n\t\t\t\t   \"p3led_an\", \"p4led_an\", \"wdt\", \"wled_an\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\twifi@0,0 {\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&radio 0x8000>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\t\tnvmem-cells = <&macaddr_rom_f100>;\n\t\tnvmem-cell-names = \"mac-address\";\n\t\tmac-address-increment = <(-1)>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7628an_tplink_re200-v2.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7628an_tplink_re200.dtsi\"\n\n/ {\n\tcompatible = \"tplink,re200-v2\", \"mediatek,mt7628an-soc\";\n\tmodel = \"TP-Link RE200 v2\";\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7628an_tplink_re200-v3.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7628an_tplink_re200.dtsi\"\n\n/ {\n\tcompatible = \"tplink,re200-v3\", \"mediatek,mt7628an-soc\";\n\tmodel = \"TP-Link RE200 v3\";\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7628an_tplink_re200-v4.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7628an_tplink_re200.dtsi\"\n\n/ {\n\tcompatible = \"tplink,re200-v4\", \"mediatek,mt7628an-soc\";\n\tmodel = \"TP-Link RE200 v4\";\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7628an_tplink_re200.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7628an.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\taliases {\n\t\tlabel-mac-device = &ethernet;\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,57600n8\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 37 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio 38 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twps {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&gpio 5 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twifi {\n\t\t\tlabel = \"green:wifi\";\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan {\n\t\t\tlabel = \"green:lan\";\n\t\t\tgpios = <&gpio 39 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_power: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 44 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twifi2g_green {\n\t\t\tlabel = \"green:wifi2g\";\n\t\t\tgpios = <&gpio 41 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\twifi5g_green {\n\t\t\tlabel = \"green:wifi5g\";\n\t\t\tgpios = <&gpio 42 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\n\t\twifi2g_red {\n\t\t\tlabel = \"red:wifi2g\";\n\t\t\tgpios = <&gpio 43 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twifi5g_red {\n\t\t\tlabel = \"red:wifi5g\";\n\t\t\tgpios = <&gpio 40 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <50000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x20000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tcompatible = \"tplink,firmware\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x20000 0x7a0000>;\n\t\t\t};\n\n\t\t\tconfig: partition@7c0000 {\n\t\t\t\tlabel = \"config\";\n\t\t\t\treg = <0x7c0000 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tradio: partition@7f0000 {\n\t\t\t\tlabel = \"radio\";\n\t\t\t\treg = <0x7f0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"p4led_an\", \"p3led_an\", \"p2led_an\", \"p1led_an\",\n\t\t\t\t\"p0led_an\", \"wled_an\", \"i2c\", \"wdt\", \"refclk\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_config_2008>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmediatek,mtd-eeprom = <&radio 0x0>;\n\n\tnvmem-cells = <&macaddr_config_2008>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <1>;\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\tmt76@0,0 {\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&radio 0x8000>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\t\tnvmem-cells = <&macaddr_config_2008>;\n\t\tnvmem-cell-names = \"mac-address\";\n\t\tmac-address-increment = <2>;\n\t};\n};\n\n&config {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_config_2008: macaddr@2008 {\n\t\treg = <0x2008 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7628an_tplink_re220-v2.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7628an_tplink_re200.dtsi\"\n\n/ {\n\tcompatible = \"tplink,re220-v2\", \"mediatek,mt7628an-soc\";\n\tmodel = \"TP-Link RE220 v2\";\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7628an_tplink_re305-v1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7628an_tplink_re305.dtsi\"\n\n/ {\n\tcompatible = \"tplink,re305-v1\", \"mediatek,mt7628an-soc\";\n\tmodel = \"TP-Link RE305 v1\";\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <50000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x20000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tcompatible = \"tplink,firmware\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x20000 0x5e0000>;\n\t\t\t};\n\n\t\t\tconfig: partition@600000 {\n\t\t\t\tlabel = \"config\";\n\t\t\t\treg = <0x600000 0x50000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\t/*\n\t\t\t\tThe flash space between 0x650000 and 0x7f0000 is blank in the\n\t\t\t\tstock firmware so it is left out as well.\n\t\t\t*/\n\n\t\t\tradio: partition@7f0000 {\n\t\t\t\tlabel = \"radio\";\n\t\t\t\treg = <0x7f0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&wlan5g {\n\tmediatek,mtd-eeprom = <&radio 0x8000>;\n\n\tnvmem-cells = <&macaddr_config_10008>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <2>;\n};\n\n&wmac {\n\tmediatek,mtd-eeprom = <&radio 0x0>;\n\n\tnvmem-cells = <&macaddr_config_10008>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <1>;\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_config_10008>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&config {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_config_10008: macaddr@10008 {\n\t\treg = <0x10008 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7628an_tplink_re305-v3.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7628an_tplink_re305.dtsi\"\n\n/ {\n\tcompatible = \"tplink,re305-v3\", \"mediatek,mt7628an-soc\";\n\tmodel = \"TP-Link RE305 v3\";\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <50000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x20000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tcompatible = \"tplink,firmware\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x20000 0x7a0000>;\n\t\t\t};\n\n\t\t\tconfig: partition@7c0000 {\n\t\t\t\tlabel = \"config\";\n\t\t\t\treg = <0x7c0000 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tradio: partition@7f0000 {\n\t\t\t\tlabel = \"radio\";\n\t\t\t\treg = <0x7f0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&wlan5g {\n\tmediatek,mtd-eeprom = <&radio 0x8000>;\n\n\tnvmem-cells = <&macaddr_config_2008>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <(-2)>;\n};\n\n&wmac {\n\tmediatek,mtd-eeprom = <&radio 0x0>;\n\n\tnvmem-cells = <&macaddr_config_2008>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <(-1)>;\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_config_2008>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&config {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_config_2008: macaddr@2008 {\n\t\treg = <0x2008 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7628an_tplink_re305.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7628an.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t\tlabel-mac-device = &ethernet;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 37 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio 38 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"blue:power\";\n\t\t\tgpios = <&gpio 39 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan2g {\n\t\t\tlabel = \"blue:wlan2g\";\n\t\t\tgpios = <&gpio 41 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\twlan5g {\n\t\t\tlabel = \"blue:wlan5g\";\n\t\t\tgpios = <&gpio 40 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy1tpt\";\n\t\t};\n\n\t\trssi1 {\n\t\t\tlabel = \"red:rssi\";\n\t\t\tgpios = <&gpio 43 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\trssi2 {\n\t\t\tlabel = \"blue:rssi\";\n\t\t\tgpios = <&gpio 42 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"refclk\", \"wdt\", \"p0led_an\", \"p1led_an\", \"p2led_an\", \"p3led_an\", \"p4led_an\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\twlan5g: mt76@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\t};\n};\n\n&wmac {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7628an_tplink_tl-mr3020-v3.dts",
    "content": "#include \"mt7628an.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"tplink,tl-mr3020-v3\", \"mediatek,mt7628an-soc\";\n\tmodel = \"TP-Link TL-MR3020 v3\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t\tlabel-mac-device = &ethernet;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio 38 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\n\t\tmodec1 {\n\t\t\tlabel = \"sw1\";\n\t\t\tgpios = <&gpio 41 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_0>;\n\t\t\tlinux,input-type = <EV_SW>;\n\t\t};\n\n\t\tmodec2 {\n\t\t\tlabel = \"sw2\";\n\t\t\tgpios = <&gpio 42 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_1>;\n\t\t\tlinux,input-type = <EV_SW>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 37 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\twan {\n\t\t\tlabel = \"green:3g\";\n\t\t\tgpios = <&gpio 43 GPIO_ACTIVE_LOW>;\n\t\t\ttrigger-sources = <&ehci_port1>, <&ohci_port1>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\n\t\twlan {\n\t\t\tlabel = \"green:wlan\";\n\t\t\tgpios = <&gpio 44 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&gpio 2 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan {\n\t\t\tlabel = \"green:lan\";\n\t\t\tgpios = <&gpio 3 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tgpio_export {\n\t\tcompatible = \"gpio-export\";\n\t\t#size-cells = <0>;\n\n\t\tusbpower {\n\t\t\tgpio-export,name = \"usbpower\";\n\t\t\tgpio-export,output = <1>;\n\t\t\tgpios = <&gpio 39 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <50000000>;\n\t\tm25p,fast-read;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"boot\";\n\t\t\t\treg = <0x0 0x20000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tcompatible = \"tplink,firmware\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x20000 0x7a0000>;\n\t\t\t};\n\n\t\t\tpartition@7c0000 {\n\t\t\t\tlabel = \"config\";\n\t\t\t\treg = <0x7c0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@7d0000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x7d0000 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2s\", \"refclk\", \"wdt\", \"p4led_an\", \"p2led_an\", \"p1led_an\", \"p0led_an\", \"wled_an\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmediatek,mtd-eeprom = <&factory 0x20000>;\n\n\tnvmem-cells = <&macaddr_factory_f100>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_f100>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_f100: macaddr@f100 {\n\t\treg = <0xf100 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7628an_tplink_tl-mr3420-v5.dts",
    "content": "#include \"mt7628an_tplink_8m.dtsi\"\n\n/ {\n\tcompatible = \"tplink,tl-mr3420-v5\", \"mediatek,mt7628an-soc\";\n\tmodel = \"TP-Link TL-MR3420 v5\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 38 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\trfkill {\n\t\t\tlabel = \"rfkill\";\n\t\t\tgpios = <&gpio 46 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RFKILL>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tlan {\n\t\t\tlabel = \"green:lan\";\n\t\t\tgpios = <&gpio 41 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_power: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 2 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tusb {\n\t\t\tlabel = \"green:usb\";\n\t\t\tgpios = <&gpio 3 GPIO_ACTIVE_LOW>;\n\t\t\ttrigger-sources = <&ohci_port1>, <&ehci_port1>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\n\t\twan {\n\t\t\tlabel = \"green:wan\";\n\t\t\tgpios = <&gpio 5 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twan_amber {\n\t\t\tlabel = \"amber:wan\";\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan {\n\t\t\tlabel = \"green:wlan\";\n\t\t\tgpios = <&gpio 44 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&gpio 37 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"i2s\", \"p2led_an\", \"refclk\", \"uart1\", \"wdt\", \"wled_an\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&esw {\n\tmediatek,portmap = <0x3e>;\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7628an_tplink_tl-mr6400-v4.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7628an_tplink_8m.dtsi\"\n\n/ {\n\tcompatible = \"tplink,tl-mr6400-v4\", \"mediatek,mt7628an-soc\";\n\tmodel = \"TP-Link TL-MR6400 v4\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 38 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\trfkill {\n\t\t\tlabel = \"rfkill\";\n\t\t\tgpios = <&gpio 46 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RFKILL>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"white:power\";\n\t\t\tgpios = <&gpio 37 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twan {\n\t\t\tlabel = \"white:wan\";\n\t\t\tgpios = <&gpio 39 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan {\n\t\t\tlabel = \"white:wlan\";\n\t\t\tgpios = <&gpio 40 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\tlan {\n\t\t\tlabel = \"white:lan\";\n\t\t\tgpios = <&gpio 41 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tsignal1 {\n\t\t\tlabel = \"white:signal1\";\n\t\t\tgpios = <&gpio 42 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tsignal2 {\n\t\t\tlabel = \"white:signal2\";\n\t\t\tgpios = <&gpio 43 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tsignal3 {\n\t\t\tlabel = \"white:signal3\";\n\t\t\tgpios = <&gpio 44 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"p0led_an\", \"p1led_an\", \"p2led_an\", \"p3led_an\", \"p4led_an\", \"refclk\", \"uart1\", \"wdt\", \"wled_an\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&esw {\n\tmediatek,portmap = <0x2f>;\n\tmediatek,portdisable = <0x21>;\n};\n\n&wmac {\n\tnvmem-cells = <&macaddr_factory_1f100>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_1f100>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_1f100: macaddr@1f100 {\n\t\treg = <0x1f100 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7628an_tplink_tl-mr6400-v5.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7628an_tplink_8m.dtsi\"\n\n/ {\n\tcompatible = \"tplink,tl-mr6400-v5\", \"mediatek,mt7628an-soc\";\n\tmodel = \"TP-Link TL-MR6400 v5\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 38 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\trfkill {\n\t\t\tlabel = \"rfkill\";\n\t\t\tgpios = <&gpio 46 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RFKILL>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twlan {\n\t\t\tlabel = \"white:wlan\";\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\tlan {\n\t\t\tlabel = \"white:lan\";\n\t\t\tgpios = <&gpio 5 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_power: power {\n\t\t\tlabel = \"white:power\";\n\t\t\tgpios = <&gpio 39 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twan {\n\t\t\tlabel = \"white:wan\";\n\t\t\tgpios = <&gpio 40 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tsignal1 {\n\t\t\tlabel = \"white:signal1\";\n\t\t\tgpios = <&gpio 41 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tsignal2 {\n\t\t\tlabel = \"white:signal2\";\n\t\t\tgpios = <&gpio 42 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tsignal3 {\n\t\t\tlabel = \"white:signal3\";\n\t\t\tgpios = <&gpio 43 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"p0led_an\", \"p1led_an\", \"p2led_an\", \"p3led_an\", \"p4led_an\", \"uart1\", \"wdt\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&esw {\n\tmediatek,portmap = <0x37>;\n\tmediatek,portdisable = <0x30>;\n};\n\n&wmac {\n\tnvmem-cells = <&macaddr_factory_1f100>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_1f100>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_1f100: macaddr@1f100 {\n\t\treg = <0x1f100 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7628an_tplink_tl-wa801nd-v5.dts",
    "content": "#include \"mt7628an_tplink_8m.dtsi\"\n\n/ {\n\tcompatible = \"tplink,tl-wa801nd-v5\", \"mediatek,mt7628an-soc\";\n\tmodel = \"TP-Link TL-WA801ND v5\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 38 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio 46 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 36 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan {\n\t\t\tlabel = \"green:lan\";\n\t\t\tgpios = <&gpio 37 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan {\n\t\t\tlabel = \"green:wlan\";\n\t\t\tgpios = <&gpio 44 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\twps_red {\n\t\t\tlabel = \"red:wps\";\n\t\t\tgpios = <&gpio 43 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\twps_green {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&gpio 42 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&ehci {\n\tstatus = \"disabled\";\n};\n\n&ohci {\n\tstatus = \"disabled\";\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"p0led_an\", \"p1led_an\", \"perst\", \"refclk\",\n\t\t\t\t\"uart1\", \"wdt\", \"wled_an\";\n\t\tfunction = \"gpio\";\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7628an_tplink_tl-wr802n-v4.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7628an_tplink_8m.dtsi\"\n\n/ {\n\tcompatible = \"tplink,tl-wr802n-v4\", \"mediatek,mt7628an-soc\";\n\tmodel = \"TP-Link TL-WR802N v4\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 38 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 37 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&ehci {\n\tstatus = \"disabled\";\n};\n\n&ohci {\n\tstatus = \"disabled\";\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"refclk\", \"wdt\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_f100>;\n\tnvmem-cell-names = \"mac-address\";\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7628an_tplink_tl-wr840n-v4.dts",
    "content": "#include \"mt7628an_tplink_8m.dtsi\"\n\n/ {\n\tcompatible = \"tplink,tl-wr840n-v4\", \"mediatek,mt7628an-soc\";\n\tmodel = \"TP-Link TL-WR840N v4\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 38 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tlan {\n\t\t\tlabel = \"green:lan\";\n\t\t\tgpios = <&gpio 41 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_power: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 36 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twan {\n\t\t\tlabel = \"green:wan\";\n\t\t\tgpios = <&gpio 43 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan {\n\t\t\tlabel = \"green:wlan\";\n\t\t\tgpios = <&gpio 44 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&gpio 37 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&ehci {\n\tstatus = \"disabled\";\n};\n\n&ohci {\n\tstatus = \"disabled\";\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"p0led_an\", \"p2led_an\", \"perst\", \"refclk\", \"wdt\", \"wled_an\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&esw {\n\tmediatek,portmap = <0x3e>;\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7628an_tplink_tl-wr840n-v5.dts",
    "content": "#include \"mt7628an.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"tplink,tl-wr840n-v5\", \"mediatek,mt7628an-soc\";\n\tmodel = \"TP-Link TL-WR840N v5\";\n\n\taliases {\n\t\tled-boot = &led_power_green;\n\t\tled-failsafe = &led_power_green;\n\t\tled-running = &led_power_green;\n\t\tled-upgrade = &led_power_green;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 38 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\t/* LED used is dual-color,dual lead LED */\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power_green: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 41 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\torange {\n\t\t\tlabel = \"orange:power\";\n\t\t\tgpios = <&gpio 43 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"boot\";\n\t\t\t\treg = <0x0 0x20000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tcompatible = \"tplink,firmware\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x20000 0x3d0000>;\n\t\t\t};\n\n\t\t\tfactory: partition@3f0000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x3f0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&ehci {\n\tstatus = \"disabled\";\n};\n\n&ohci {\n\tstatus = \"disabled\";\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmediatek,mtd-eeprom = <&factory 0x0>;\n\n\tnvmem-cells = <&macaddr_factory_f100>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_f100>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&esw {\n\tmediatek,portmap = <0x3e>;\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"p0led_an\", \"p2led_an\", \"perst\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_f100: macaddr@f100 {\n\t\treg = <0xf100 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7628an_tplink_tl-wr841n-v13.dts",
    "content": "#include \"mt7628an_tplink_8m.dtsi\"\n\n/ {\n\tcompatible = \"tplink,tl-wr841n-v13\", \"mediatek,mt7628an-soc\";\n\tmodel = \"TP-Link TL-WR841N v13\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 38 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\trfkill {\n\t\t\tlabel = \"rfkill\";\n\t\t\tgpios = <&gpio 37 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RFKILL>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 36 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&gpio 46 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan1 {\n\t\t\tlabel = \"green:lan1\";\n\t\t\tgpios = <&gpio 42 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan2 {\n\t\t\tlabel = \"green:lan2\";\n\t\t\tgpios = <&gpio 41 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan3 {\n\t\t\tlabel = \"green:lan3\";\n\t\t\tgpios = <&gpio 40 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan4 {\n\t\t\tlabel = \"green:lan4\";\n\t\t\tgpios = <&gpio 39 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twan_green {\n\t\t\tlabel = \"green:wan\";\n\t\t\tgpios = <&gpio 43 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twan_orange {\n\t\t\tlabel = \"orange:wan\";\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan {\n\t\t\tlabel = \"green:wlan\";\n\t\t\tgpios = <&gpio 44 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&ehci {\n\tstatus = \"disabled\";\n};\n\n&ohci {\n\tstatus = \"disabled\";\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"gpio\", \"p0led_an\", \"p1led_an\", \"p2led_an\", \"p3led_an\", \"p4led_an\", \"perst\", \"refclk\", \"uart1\", \"wdt\", \"wled_an\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&esw {\n\tmediatek,portmap = <0x3e>;\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7628an_tplink_tl-wr841n-v14.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7628an.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"tplink,tl-wr841n-v14\", \"mediatek,mt7628an-soc\";\n\tmodel = \"TP-Link TL-WR841N v14\";\n\n\taliases {\n\t\tled-boot = &led_wlan;\n\t\tled-failsafe = &led_wlan;\n\t\tled-upgrade = &led_wlan;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 38 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tlan {\n\t\t\tlabel = \"green:lan\";\n\t\t\tgpios = <&gpio 39 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twan_green {\n\t\t\tlabel = \"green:wan\";\n\t\t\tgpios = <&gpio 40 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_wlan: wlan {\n\t\t\tlabel = \"green:wlan\";\n\t\t\tgpios = <&gpio 41 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\twan_orange {\n\t\t\tlabel = \"orange:wan\";\n\t\t\tgpios = <&gpio 42 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"boot\";\n\t\t\t\treg = <0x0 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@10000 {\n\t\t\t\tcompatible = \"tplink,firmware\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x10000 0x3e0000>;\n\t\t\t};\n\n\t\t\tfactory: partition@3f0000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x3f0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&ehci {\n\tstatus = \"disabled\";\n};\n\n&ohci {\n\tstatus = \"disabled\";\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmediatek,mtd-eeprom = <&factory 0x0>;\n\n\tnvmem-cells = <&macaddr_factory_f100>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_f100>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&esw {\n\tmediatek,portmap = <0x3e>;\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"p4led_an\", \"p3led_an\", \"p2led_an\", \"p1led_an\", \"p0led_an\", \"wdt\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&gpio {\n\tled_wlan_enable {\n\t\tgpio-hog;\n\t\tgpios = <43 GPIO_ACTIVE_HIGH>;\n\t\toutput-high;\n\t};\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_f100: macaddr@f100 {\n\t\treg = <0xf100 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7628an_tplink_tl-wr842n-v5.dts",
    "content": "#include \"mt7628an_tplink_8m.dtsi\"\n\n/ {\n\tcompatible = \"tplink,tl-wr842n-v5\", \"mediatek,mt7628an-soc\";\n\tmodel = \"TP-Link TL-WR842N v5\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 46 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\trfkill {\n\t\t\tlabel = \"rfkill\";\n\t\t\tgpios = <&gpio 38 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RFKILL>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tlan {\n\t\t\tlabel = \"green:lan\";\n\t\t\tgpios = <&gpio 41 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_power: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 2 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tusb {\n\t\t\tlabel = \"green:usb\";\n\t\t\tgpios = <&gpio 3 GPIO_ACTIVE_LOW>;\n\t\t\ttrigger-sources = <&ohci_port1>, <&ehci_port1>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\n\t\twan {\n\t\t\tlabel = \"green:wan\";\n\t\t\tgpios = <&gpio 5 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twan_amber {\n\t\t\tlabel = \"amber:wan\";\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan {\n\t\t\tlabel = \"green:wlan\";\n\t\t\tgpios = <&gpio 44 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&gpio 37 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"i2s\", \"p2led_an\", \"refclk\", \"uart1\", \"wdt\", \"wled_an\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&esw {\n\tmediatek,portmap = <0x3e>;\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7628an_tplink_tl-wr850n-v2.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7628an_tplink_8m.dtsi\"\n\n/ {\n\tcompatible = \"tplink,tl-wr850n-v2\", \"mediatek,mt7628an-soc\";\n\tmodel = \"TP-Link TL-WR850N v2\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 38 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 36 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&gpio 37 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan {\n\t\t\tlabel = \"green:lan\";\n\t\t\tgpios = <&gpio 41 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twan {\n\t\t\tlabel = \"green:wan\";\n\t\t\tgpios = <&gpio 43 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan {\n\t\t\tlabel = \"green:wlan\";\n\t\t\tgpios = <&gpio 44 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\t};\n};\n\n&ehci {\n\tstatus = \"disabled\";\n};\n\n&ohci {\n\tstatus = \"disabled\";\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"p0led_an\", \"p2led_an\", \"perst\", \"refclk\", \"wdt\", \"wled_an\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&esw {\n\tmediatek,portmap = <0x3e>;\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7628an_tplink_tl-wr902ac-v3.dts",
    "content": "#include \"mt7628an_tplink_8m.dtsi\"\n\n/ {\n\tcompatible = \"tplink,tl-wr902ac-v3\", \"mediatek,mt7628an-soc\";\n\tmodel = \"TP-Link TL-WR902AC v3\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 38 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\tsw1 {\n\t\t\tlabel = \"sw1\";\n\t\t\tgpios = <&gpio 2 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_0>;\n\t\t};\n\n\t\tsw2 {\n\t\t\tlabel = \"sw2\";\n\t\t\tgpios = <&gpio 3 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_1>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio 41 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tlan {\n\t\t\tlabel = \"green:lan\";\n\t\t\tgpios = <&gpio 5 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tled_power: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 46 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tusb {\n\t\t\tlabel = \"green:usb\";\n\t\t\tgpios = <&gpio 43 GPIO_ACTIVE_LOW>;\n\t\t\ttrigger-sources = <&ohci_port1>, <&ehci_port1>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\n\t\twan {\n\t\t\tlabel = \"green:wan\";\n\t\t\tgpios = <&gpio 39 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan {\n\t\t\tlabel = \"green:wlan\";\n\t\t\tgpios = <&gpio 44 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"i2s\", \"p0led_an\", \"p2led_an\", \"p4led_an\", \"uart1\", \"wdt\", \"wled_an\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\tmt76@0,0 {\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x28000>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\t\tnvmem-cells = <&macaddr_factory_f100>;\n\t\tnvmem-cell-names = \"mac-address\";\n\t\tmac-address-increment = <(-1)>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7628an_unielec_u7628-01-16m.dts",
    "content": "// SPDX-License-Identifier: BSD-3-Clause\n/*\n *  Copyright(c) 2017 Kristian Evensen <kristian.evensen@gmail.com>.\n *  Copyright(c) 2017 Piotr Dymacz <pepe2k@gmail.com>.\n *  All rights reserved.\n */\n\n#include \"mt7628an_unielec_u7628-01.dtsi\"\n\n/ {\n\tcompatible = \"unielec,u7628-01-16m\", \"unielec,u7628-01\", \"mediatek,mt7628an-soc\";\n\tmodel = \"UniElec U7628-01 (16M flash)\";\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <12000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"bootloader\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"config\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0xfb0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_28>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_28: macaddr@28 {\n\t\treg = <0x28 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7628an_unielec_u7628-01.dtsi",
    "content": "// SPDX-License-Identifier: BSD-3-Clause\n/*\n *  Copyright(c) 2017 Kristian Evensen <kristian.evensen@gmail.com>.\n *  Copyright(c) 2017 Piotr Dymacz <pepe2k@gmail.com>.\n *  All rights reserved.\n */\n\n#include \"mt7628an.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"unielec,u7628-01\", \"mediatek,mt7628an-soc\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 38 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 44 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan {\n\t\t\tlabel = \"green:wlan\";\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twan {\n\t\t\tlabel = \"green:wan\";\n\t\t\tgpios = <&gpio 43 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan1 {\n\t\t\tlabel = \"green:lan1\";\n\t\t\tgpios = <&gpio 42 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan2 {\n\t\t\tlabel = \"green:lan2\";\n\t\t\tgpios = <&gpio 41 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan3 {\n\t\t\tlabel = \"green:lan3\";\n\t\t\tgpios = <&gpio 40 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan4 {\n\t\t\tlabel = \"green:lan4\";\n\t\t\tgpios = <&gpio 39 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tusb {\n\t\t\tlabel = \"green:usb\";\n\t\t\tgpios = <&gpio 37 GPIO_ACTIVE_LOW>;\n\t\t\ttrigger-sources = <&ohci_port1>, <&ehci_port1>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmediatek,mtd-eeprom = <&factory 0x0>;\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"gpio\", \"p0led_an\", \"p1led_an\", \"p2led_an\", \"p3led_an\", \"p4led_an\", \"refclk\", \"wdt\", \"wled_an\";\n\t\tfunction = \"gpio\";\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7628an_vocore_vocore2-lite.dts",
    "content": "#include \"mt7628an_vocore_vocore2.dtsi\"\n\n/ {\n\tcompatible = \"vocore,vocore2-lite\", \"vocore,vocore2\", \"mediatek,mt7628an-soc\";\n\tmodel = \"VoCore2-Lite\";\n\n\taliases {\n\t\tled-boot = &led_status;\n\t\tled-failsafe = &led_status;\n\t\tled-running = &led_status;\n\t\tled-upgrade = &led_status;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_status: status {\n\t\t\tlabel = \"green:status\";\n\t\t\tgpios = <&gpio 44 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&firmware {\n\treg = <0x50000 0x7b0000>;\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7628an_vocore_vocore2.dts",
    "content": "#include \"mt7628an_vocore_vocore2.dtsi\"\n\n/ {\n\tcompatible = \"vocore,vocore2\", \"mediatek,mt7628an-soc\";\n\tmodel = \"VoCore2\";\n\n\taliases {\n\t\tled-boot = &led_status;\n\t\tled-failsafe = &led_status;\n\t\tled-running = &led_status;\n\t\tled-upgrade = &led_status;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_status: status {\n\t\t\tlabel = \"fuchsia:status\";\n\t\t\tgpios = <&gpio 44 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&firmware {\n\treg = <0x50000 0xfb0000>;\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7628an_vocore_vocore2.dtsi",
    "content": "#include \"mt7628an.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n\n/ {\n\tcompatible = \"vocore,vocore2\", \"mediatek,mt7628an-soc\";\n\n\taliases {\n\t\tlabel-mac-device = &wmac;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyS2,115200\";\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfirmware: partition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\t/* reg property is set based on flash size in DTS files */\n\t\t\t};\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"wled_an\", \"refclk\", \"wdt\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmediatek,mtd-eeprom = <&factory 0x0>;\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_28>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&esw {\n\tmediatek,portmap = <0x7>;\n\tmediatek,portdisable = <0x3a>;\n};\n\n&i2s {\n\tstatus = \"okay\";\n};\n\n&gdma {\n\tstatus = \"okay\";\n};\n\n&pwm {\n\tstatus = \"okay\";\n};\n\n&uart1 {\n\tstatus = \"okay\";\n};\n\n&uart2 {\n\tstatus = \"okay\";\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_28: macaddr@28 {\n\t\treg = <0x28 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7628an_wavlink_wl-wn531a3.dts",
    "content": "#include \"mt7628an.dtsi\"\n\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/gpio/gpio.h>\n\n/ {\n\tcompatible = \"wavlink,wl-wn531a3\", \"mediatek,mt7628an-soc\";\n\tmodel = \"Wavlink WL-WN531A3\";\n\n\taliases {\n\t\tled-boot = &led_status_blue;\n\t\tled-failsafe = &led_status_red;\n\t\tled-running = &led_status_blue;\n\t\tled-upgrade = &led_status_red;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\tturbo {\n\t\t\tlabel = \"turbo\";\n\t\t\tgpios = <&gpio 46 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_1>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio 45 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 38 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\ttouchlink {\n\t\t\tlabel = \"touchlink\";\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_0>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twifi {\n\t\t\tlabel = \"blue:wifi\";\n\t\t\tgpios = <&gpio 44 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,default-trigger = \"phy0tpt\";\n\t\t};\n\n\t\tled_status_blue: led_status_blue {\n\t\t\tlabel = \"blue:status\";\n\t\t\tgpios = <&gpio 5 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tled_status_red: led_status_red {\n\t\t\tlabel = \"red:status\";\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"wled_an\", \"gpio\", \"wdt\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\tmt76@0,0 {\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <40000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x7b0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmediatek,mtd-eeprom = <&factory 0x0>;\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_28>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&esw {\n\tmediatek,portmap = <0x2f>;\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_28: macaddr@28 {\n\t\treg = <0x28 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7628an_wavlink_wl-wn570ha1.dts",
    "content": "#include \"mt7628an.dtsi\"\n\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/gpio/gpio.h>\n\n/ {\n\tcompatible = \"wavlink,wl-wn570ha1\", \"mediatek,mt7628an-soc\";\n\tmodel = \"Wavlink WL-WN570HA1\";\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 38 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tpower {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 37 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"keep\";\n\t\t};\n\n\t\twan {\n\t\t\tlabel = \"green:wan\";\n\t\t\tgpios = <&gpio 43 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twifi-high {\n\t\t\tlabel = \"green:wifi-high\";\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twifi-med {\n\t\t\tlabel = \"green:wifi-med\";\n\t\t\tgpios = <&gpio 5 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twifi-low {\n\t\t\tlabel = \"green:wifi-low\";\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twifi {\n\t\t\tlabel = \"green:wifi\";\n\t\t\tgpios = <&gpio 44 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"wled_an\", \"p0led_an\", \"wdt\", \"refclk\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\twifi@0,0 {\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x7b0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmediatek,mtd-eeprom = <&factory 0x0>;\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_2e>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&esw {\n\tmediatek,portmap = <0x2f>;\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_2e: macaddr@2e {\n\t\treg = <0x2e 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7628an_wavlink_wl-wn575a3.dts",
    "content": "#include \"mt7628an.dtsi\"\n\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/gpio/gpio.h>\n\n/ {\n\tcompatible = \"wavlink,wl-wn575a3\", \"mediatek,mt7628an-soc\";\n\tmodel = \"Wavlink WL-WN575A3\";\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 43 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio 38 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twifi-high {\n\t\t\tlabel = \"green:wifi-high\";\n\t\t\tgpios = <&gpio 37 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twifi-med {\n\t\t\tlabel = \"green:wifi-med\";\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twifi-low {\n\t\t\tlabel = \"green:wifi-low\";\n\t\t\tgpios = <&gpio 44 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"wled_an\", \"gpio\", \"refclk\", \"wdt\", \"p0led_an\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\tmt76@0,0 {\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x7b0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmediatek,mtd-eeprom = <&factory 0x0>;\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_28>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&esw {\n\tmediatek,portmap = <0x2f>;\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_28: macaddr@28 {\n\t\treg = <0x28 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7628an_wavlink_wl-wn576a2.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7628an.dtsi\"\n\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/gpio/gpio.h>\n\n/ {\n\tcompatible = \"wavlink,wl-wn576a2\", \"mediatek,mt7628an-soc\";\n\tmodel = \"Wavlink WL-WN576A2\";\n\n\taliases {\n\t\tled-boot = &led_wps;\n\t\tled-failsafe = &led_wps;\n\t\tled-running = &led_wps;\n\t\tled-upgrade = &led_wps;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 43 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio 38 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\n\t\tap {\n\t\t\tlabel = \"ap\";\n\t\t\tgpios = <&gpio 41 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_0>;\n\t\t\tlinux,input-type = <EV_SW>;\n\t\t};\n\n\t\trepeater {\n\t\t\tlabel = \"repeater\";\n\t\t\tgpios = <&gpio 42 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_1>;\n\t\t\tlinux,input-type = <EV_SW>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twifi-high {\n\t\t\tlabel = \"blue:wifi-high\";\n\t\t\tgpios = <&gpio 37 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twifi-mediumhigh {\n\t\t\tlabel = \"blue:wifi-mediumhigh\";\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twifi-medium {\n\t\t\tlabel = \"blue:wifi-medium\";\n\t\t\tgpios = <&gpio 44 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twifi-mediumlow {\n\t\t\tlabel = \"blue:wifi-mediumlow\";\n\t\t\tgpios = <&gpio 39 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twifi-low {\n\t\t\tlabel = \"blue:wifi-low\";\n\t\t\tgpios = <&gpio 40 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan {\n\t\t\tlabel = \"blue:lan\";\n\t\t\tgpios = <&gpio 2 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_wps: wps {\n\t\t\tlabel = \"blue:wps\";\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"i2s\", \"wdt\", \"wled_an\", \"p0led_an\", \"p1led_an\",\n\t\t\t\"p2led_an\", \"p3led_an\", \"p4led_an\", \"refclk\", \"gpio\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\twifi@0,0 {\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <40000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x7b0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmediatek,mtd-eeprom = <&factory 0x0>;\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_28>;\n\tnvmem-cells-names = \"max-address\";\n};\n\n&esw {\n\tmediatek,portmap = <0x3f>;\n};\n\n&usbphy {\n\tstatus = \"disabled\";\n};\n\n&ehci {\n\tstatus = \"disabled\";\n};\n\n&ohci {\n\tstatus = \"disabled\";\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_28: macaddr@28 {\n\t\treg = <0x28 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7628an_wavlink_wl-wn577a2.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7628an.dtsi\"\n\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/gpio/gpio.h>\n\n/ {\n\tcompatible = \"wavlink,wl-wn577a2\", \"maginon,wlr-755\", \"mediatek,mt7628an-soc\";\n\tmodel = \"WAVLINK WL-WN577A2\";\n\n\taliases {\n\t\tled-boot = &led_wps;\n\t\tled-failsafe = &led_wps;\n\t\tled-running = &led_wps;\n\t\tled-upgrade = &led_wps;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 43 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio 38 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tlan {\n\t\t\tlabel = \"green:lan\";\n\t\t\tgpios = <&gpio 40 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twan {\n\t\t\tlabel = \"green:wan\";\n\t\t\tgpios = <&gpio 39 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_wps: wps {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"wdt\", \"p0led_an\", \"p3led_an\", \"p4led_an\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\tmt76@0,0 {\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <40000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x7b0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmediatek,mtd-eeprom = <&factory 0x0>;\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_28>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&esw {\n\tmediatek,portmap = <0x2f>;\n};\n\n&usbphy {\n\tstatus = \"disabled\";\n};\n\n&ehci {\n\tstatus = \"disabled\";\n};\n\n&ohci {\n\tstatus = \"disabled\";\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_28: macaddr@28 {\n\t\treg = <0x28 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7628an_wavlink_wl-wn578a2.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7628an.dtsi\"\n\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/gpio/gpio.h>\n\n/ {\n\tcompatible = \"wavlink,wl-wn578a2\", \"mediatek,mt7628an-soc\";\n\tmodel = \"Wavlink WL-WN578A2\";\n\n\taliases {\n\t\tled-boot = &led_wps;\n\t\tled-failsafe = &led_wps;\n\t\tled-running = &led_wps;\n\t\tled-upgrade = &led_wps;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 43 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio 38 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\n\t\tap {\n\t\t\tlabel = \"ap\";\n\t\t\tgpios = <&gpio 41 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_0>;\n\t\t\tlinux,input-type = <EV_SW>;\n\t\t};\n\n\t\trepeater {\n\t\t\tlabel = \"repeater\";\n\t\t\tgpios = <&gpio 42 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_1>;\n\t\t\tlinux,input-type = <EV_SW>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twifi-high {\n\t\t\tlabel = \"green:wifi-high\";\n\t\t\tgpios = <&gpio 37 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twifi-med {\n\t\t\tlabel = \"green:wifi-med\";\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twifi-low {\n\t\t\tlabel = \"green:wifi-low\";\n\t\t\tgpios = <&gpio 44 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan {\n\t\t\tlabel = \"green:lan\";\n\t\t\tgpios = <&gpio 40 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twan {\n\t\t\tlabel = \"green:wan\";\n\t\t\tgpios = <&gpio 39 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_wps: wps {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"wdt\", \"wled_an\", \"p0led_an\", \"p1led_an\",\n\t\t\t\"p2led_an\", \"p3led_an\", \"p4led_an\", \"refclk\", \"gpio\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\twifi@0,0 {\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <40000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x7b0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmediatek,mtd-eeprom = <&factory 0x0>;\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_28>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&esw {\n\tmediatek,portmap = <0x2f>;\n};\n\n&usbphy {\n\tstatus = \"disabled\";\n};\n\n&ehci {\n\tstatus = \"disabled\";\n};\n\n&ohci {\n\tstatus = \"disabled\";\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_28: macaddr@28 {\n\t\treg = <0x28 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7628an_widora_neo-16m.dts",
    "content": "#include \"mt7628an_widora_neo.dtsi\"\n\n/ {\n\tcompatible = \"widora,neo-16m\", \"widora,neo\", \"mediatek,mt7628an-soc\";\n\tmodel = \"Widora-NEO (16M)\";\n};\n\n&firmware {\n\treg = <0x50000 0xfb0000>;\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7628an_widora_neo-32m.dts",
    "content": "#include \"mt7628an_widora_neo.dtsi\"\n\n/ {\n\tcompatible = \"widora,neo-32m\", \"widora,neo\", \"mediatek,mt7628an-soc\";\n\tmodel = \"Widora-NEO (32M)\";\n};\n\n&flash0 {\n\tbroken-flash-reset;\n};\n\n&firmware {\n\treg = <0x50000 0x1fb0000>;\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7628an_widora_neo.dtsi",
    "content": "#include \"mt7628an.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"widora,neo\", \"mediatek,mt7628an-soc\";\n\n\taliases {\n\t\tled-boot = &led_wifi;\n\t\tled-failsafe = &led_wifi;\n\t\tled-running = &led_wifi;\n\t\tled-upgrade = &led_wifi;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200\";\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_wifi: wifi {\n\t\t\tlabel = \"orange:wifi\";\n\t\t\tgpios = <&wgpio 0 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\twps {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 38 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n\n\twgpio: gpio-wifi {\n\t\tcompatible = \"mediatek,gpio-wifi\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tgpio-controller;\n\t\t#gpio-cells = <2>;\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&spi_pins>, <&spi_cs1_pins>;\n\n\tflash0: flash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <40000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfirmware: partition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\t/* reg property is set based on flash size in DTS files */\n\t\t\t};\n\t\t};\n\t};\n\n\tspidev@1 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"linux,spidev\";\n\t\treg = <1>;\n\t\tspi-max-frequency = <40000000>;\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"gpio\";\n\t\tfunction = \"gpio\";\n\t};\n\n\tperst {\n\t\tgroups = \"perst\";\n\t\tfunction = \"gpio\";\n\t};\n\n\trefclk {\n\t\tgroups = \"refclk\";\n\t\tfunction = \"gpio\";\n\t};\n\n\ti2s {\n\t\tgroups = \"i2s\";\n\t\tfunction = \"gpio\";\n\t};\n\n\tspis {\n\t\tgroups = \"spis\";\n\t\tfunction = \"gpio\";\n\t};\n\n\twled_kn {\n\t\tgroups = \"wled_kn\";\n\t\tfunction = \"gpio\";\n\t};\n\n\twled_an {\n\t\tgroups = \"wled_an\";\n\t\tfunction = \"wled_an\";\n\t};\n\n\twdt {\n\t\tgroups = \"wdt\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&i2c {\n\tstatus = \"okay\";\n};\n\n&uart1 {\n\tstatus = \"okay\";\n};\n\n&uart2 {\n\tstatus = \"okay\";\n};\n\n&pwm {\n\tstatus = \"okay\";\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_28>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&sdhci {\n\tstatus = \"okay\";\n\tmediatek,cd-low;\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmediatek,mtd-eeprom = <&factory 0x0>;\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_28: macaddr@28 {\n\t\treg = <0x28 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7628an_wiznet_wizfi630s.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7628an.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"wiznet,wizfi630s\", \"mediatek,mt7628an-soc\";\n\tmodel = \"WIZnet WizFi630S\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyS1,115200\";\n\t};\n\n\taliases {\n\t\tled-boot = &led_run;\n\t\tled-failsafe = &led_run;\n\t\tled-running = &led_run;\n\t\tled-upgrade = &led_run;\n\t\tserial0 = &uart1;\n\t\tserial1 = &uartlite;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_run: run {\n\t\t\tlabel = \"green:run\";\n\t\t\tgpios = <&gpio 5 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tledwps {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&gpio 42 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tleduart1 {\n\t\t\tlabel = \"green:uart1\";\n\t\t\tgpios = <&gpio 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tleduart2 {\n\t\t\tlabel = \"green:uart2\";\n\t\t\tgpios = <&gpio 3 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio 41 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\n\t\tscm1 {\n\t\t\tlabel = \"SCM1\";\n\t\t\tgpios = <&gpio 4 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_1>;\n\t\t\tlinux,input-type = <EV_SW>;\n\t\t};\n\n\t\tscm2 {\n\t\t\tlabel = \"SCM2\";\n\t\t\tgpios = <&gpio 2 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_2>;\n\t\t\tlinux,input-type = <EV_SW>;\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"gpio\", \"i2s\", \"i2c\", \"wdt\", \"refclk\", \"p1led_an\", \"p2led_an\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&spi_pins>, <&spi_cs1_pins>;\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <40000000>;\n\t\tbroken-flash-reset;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x1fb0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&uart1 {\n\tstatus = \"okay\";\n};\n\n&uart2 {\n\tstatus = \"okay\";\n};\n\n&pwm {\n\tstatus = \"okay\";\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_2e>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&esw {\n\tmediatek,portmap = <0x3e>;\n\tmediatek,portdisable = <0x26>;\n};\n\n&sdhci {\n\tstatus = \"okay\";\n\tmediatek,cd-high;\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmediatek,mtd-eeprom = <&factory 0x0>;\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_2e: macaddr@2e {\n\t\treg = <0x2e 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7628an_wrtnode_wrtnode2.dtsi",
    "content": "#include \"mt7628an.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"wrtnode,wrtnode2\", \"mediatek,mt7628an-soc\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 5 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\t\tbroken-flash-reset;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x1fb0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&uart1 {\n\tstatus = \"okay\";\n};\n\n&i2c {\n\tstatus = \"okay\";\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&esw {\n\tmediatek,portmap = <0x3e>;\n};\n\n&sdhci {\n\tstatus = \"okay\";\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmediatek,mtd-eeprom = <&factory 0x0>;\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7628an_wrtnode_wrtnode2p.dts",
    "content": "#include \"mt7628an_wrtnode_wrtnode2.dtsi\"\n\n/ {\n\tcompatible = \"wrtnode,wrtnode2p\", \"wrtnode,wrtnode2\", \"mediatek,mt7628an-soc\";\n\tmodel = \"WRTnode2P\";\n\n\taliases {\n\t\tled-boot = &led_indicator;\n\t\tled-failsafe = &led_indicator;\n\t\tled-running = &led_indicator;\n\t\tled-upgrade = &led_indicator;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_indicator: indicator {\n\t\t\tlabel = \"blue:indicator\";\n\t\t\tgpios = <&gpio 41 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"gpio\";\n\t\tfunction = \"gpio\";\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7628an_wrtnode_wrtnode2r.dts",
    "content": "#include \"mt7628an_wrtnode_wrtnode2.dtsi\"\n\n/ {\n\tcompatible = \"wrtnode,wrtnode2r\", \"wrtnode,wrtnode2\", \"mediatek,mt7628an-soc\";\n\tmodel = \"WRTnode2R\";\n\n\taliases {\n\t\tled-boot = &led_indicator;\n\t\tled-failsafe = &led_indicator;\n\t\tled-running = &led_indicator;\n\t\tled-upgrade = &led_indicator;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tpinctrl-names = \"default\";\n\t\tpinctrl-0 = <&led_pins>;\n\n\t\tled_indicator: indicator {\n\t\t\tlabel = \"blue:indicator\";\n\t\t\tgpios = <&gpio 44 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"gpio\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&pinctrl {\n\tled_pins: led {\n\t\tgpio {\n\t\t\tgroups = \"wled_an\";\n\t\t\tfunction = \"gpio\";\n\t\t};\n\t};\n};\n\n&spi0 {\n\tspidev@1 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"linux,spidev\";\n\t\treg = <1>;\n\t\tspi-max-frequency = <10000000>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7628an_xiaomi_mi-router-4.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7628an.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\taliases {\n\t\tled-boot = &led_power_yellow;\n\t\tled-failsafe = &led_power_yellow;\n\t\tled-running = &led_power_blue;\n\t\tled-upgrade = &led_power_yellow;\n\t\tlabel-mac-device = &ethernet;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200\";\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power_blue: power_blue {\n\t\t\tlabel = \"blue:power\";\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_power_yellow: power_yellow {\n\t\t\tlabel = \"yellow:power\";\n\t\t\tgpios = <&gpio 44 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 38 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash0: flash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions: partitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"bootloader\";\n\t\t\t\treg = <0x0 0x20000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tlabel = \"config\";\n\t\t\t\treg = <0x20000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@30000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"crash\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tlabel = \"cfg_bak\";\n\t\t\t\treg = <0x50000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\t/* additional partitions in DTS */\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"gpio\", \"wdt\", \"wled_an\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmediatek,mtd-eeprom = <&factory 0x0>;\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7628an_xiaomi_mi-router-4a-100m.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7628an_xiaomi_mi-router-4.dtsi\"\n\n/ {\n\tcompatible = \"xiaomi,mi-router-4a-100m\", \"mediatek,mt7628an-soc\";\n\tmodel = \"Xiaomi Mi Router 4A (100M Edition)\";\n};\n\n&partitions {\n\tpartition@60000 {\n\t\tlabel = \"overlay\";\n\t\treg = <0x60000 0x100000>;\n\t\tread-only;\n\t};\n\n\tpartition@160000 {\n\t\tlabel = \"firmware\";\n\t\treg = <0x160000 0xea0000>;\n\t\tcompatible = \"denx,uimage\";\n\t};\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\twifi@0,0 {\n\t\tcompatible = \"mediatek,mt76\";\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <(-1)>;\n};\n\n&esw {\n\tmediatek,portmap = <0x3e>;\n\tmediatek,portdisable = <0x2a>;\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7628an_xiaomi_mi-router-4c.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7628an_xiaomi_mi-router-4.dtsi\"\n\n/ {\n\tcompatible = \"xiaomi,mi-router-4c\", \"mediatek,mt7628an-soc\";\n\tmodel = \"Xiaomi Mi Router 4C\";\n\n\taliases {\n\t\tlabel-mac-device = &ethernet;\n\t};\n};\n\n&flash0 {\n\tspi-max-frequency = <40000000>;\n};\n\n&partitions {\n\tpartition@60000 {\n\t\tlabel = \"overlay\";\n\t\treg = <0x60000 0x100000>;\n\t\tread-only;\n\t};\n\n\tpartition@160000 {\n\t\tlabel = \"firmware\";\n\t\treg = <0x160000 0xea0000>;\n\t\tcompatible = \"denx,uimage\";\n\t};\n};\n\n&ehci {\n\tstatus = \"disabled\";\n};\n\n&ohci {\n\tstatus = \"disabled\";\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_28>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&esw {\n\tmediatek,portmap = <0x3d>;\n\tmediatek,portdisable = <0x29>;\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_28: macaddr@28 {\n\t\treg = <0x28 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7628an_xiaomi_miwifi-3c.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"mt7628an.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"xiaomi,miwifi-3c\", \"mediatek,mt7628an-soc\";\n\tmodel = \"Xiaomi MiWiFi 3C\";\n\n\taliases {\n\t\tled-boot = &led_status_amber;\n\t\tled-failsafe = &led_status_red;\n\t\tled-running = &led_status_blue;\n\t\tled-upgrade = &led_status_amber;\n\t\tlabel-mac-device = &ethernet;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200\";\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_status_blue: status_blue {\n\t\t\tlabel = \"blue:status\";\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_status_red: status_red {\n\t\t\tlabel = \"red:status\";\n\t\t\tgpios = <&gpio 37 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_status_amber: status_amber {\n\t\t\tlabel = \"amber:status\";\n\t\t\tgpios = <&gpio 44 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 38 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"gpio\", \"refclk\", \"wdt\", \"wled_an\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ehci {\n\tstatus = \"disabled\";\n};\n\n&ohci {\n\tstatus = \"disabled\";\n};\n\n&esw {\n\tmediatek,portmap = <0x3e>;\n\tmediatek,portdisable = <0x2a>;\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmediatek,mtd-eeprom = <&factory 0x0>;\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_28>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <40000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"Bootloader\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"Config\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"Bdata\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@50000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x50000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@60000 {\n\t\t\t\tlabel = \"crash\";\n\t\t\t\treg = <0x60000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@70000 {\n\t\t\t\tlabel = \"cfg_bak\";\n\t\t\t\treg = <0x70000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@80000 {\n\t\t\t\tlabel = \"overlay\";\n\t\t\t\treg = <0x80000 0xc0000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@140000 {\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\treg = <0x140000 0xec0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_28: macaddr@28 {\n\t\treg = <0x28 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7628an_xiaomi_miwifi-nano.dts",
    "content": "#include \"mt7628an.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"xiaomi,miwifi-nano\", \"mediatek,mt7628an-soc\";\n\tmodel = \"Xiaomi MiWiFi Nano\";\n\n\taliases {\n\t\tled-boot = &led_status_amber;\n\t\tled-failsafe = &led_status_red;\n\t\tled-running = &led_status_blue;\n\t\tled-upgrade = &led_status_amber;\n\t\tlabel-mac-device = &ethernet;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200\";\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_status_blue: status_blue {\n\t\t\tlabel = \"blue:status\";\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_status_red: status_red {\n\t\t\tlabel = \"red:status\";\n\t\t\tgpios = <&gpio 37 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_status_amber: status_amber {\n\t\t\tlabel = \"amber:status\";\n\t\t\tgpios = <&gpio 44 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 38 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"gpio\", \"refclk\", \"wdt\", \"wled_an\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ehci {\n\tstatus = \"disabled\";\n};\n\n&ohci {\n\tstatus = \"disabled\";\n};\n\n&esw {\n\tmediatek,portmap = <0x2f>;\n\tmediatek,portdisable = <0x2a>;\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmediatek,mtd-eeprom = <&factory 0x0>;\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_28>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <40000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0xfb0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_28: macaddr@28 {\n\t\treg = <0x28 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7628an_zbtlink_zbt-we1226.dts",
    "content": "#include \"mt7628an.dtsi\"\n\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/gpio/gpio.h>\n\n/ {\n\tcompatible = \"zbtlink,zbt-we1226\", \"mediatek,mt7628an-soc\";\n\tmodel = \"Zbtlink ZBT-WE1226\";\n\n\taliases {\n\t\tled-boot = &led_wlan;\n\t\tled-failsafe = &led_wlan;\n\t\tled-running = &led_wlan;\n\t\tled-upgrade = &led_wlan;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 38 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twan {\n\t\t\tlabel = \"green:wan\";\n\t\t\tgpios = <&gpio 39 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan1 {\n\t\t\tlabel = \"green:lan1\";\n\t\t\tgpios = <&gpio 43 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan2 {\n\t\t\tlabel = \"green:lan2\";\n\t\t\tgpios = <&gpio 42 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_wlan: wlan {\n\t\t\tlabel = \"green:wlan\";\n\t\t\tgpios = <&gpio 44 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"p0led_an\", \"p1led_an\", \"p4led_an\", \"wdt\", \"wled_an\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x7b0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmediatek,mtd-eeprom = <&factory 0x0>;\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_2e>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&esw {\n\tmediatek,portmap = <0x2f>;\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_2e: macaddr@2e {\n\t\treg = <0x2e 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/mt7628an_zyxel_keenetic-extra-ii.dts",
    "content": "#include \"mt7628an.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"zyxel,keenetic-extra-ii\", \"mediatek,mt7628an-soc\";\n\tmodel = \"ZyXEL Keenetic Extra II\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,57600n8\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio 2 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio 46 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\n\t\tfn {\n\t\t\tlabel = \"fn\";\n\t\t\tgpios = <&gpio 45 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_0>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio 11 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"keep\";\n\t\t};\n\n\t\tinternet {\n\t\t\tlabel = \"green:internet\";\n\t\t\tgpios = <&gpio 44 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twifi {\n\t\t\tlabel = \"green:wifi\";\n\t\t\tgpios = <&gpio 37 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tusb {\n\t\t\tlabel = \"green:usb\";\n\t\t\tgpios = <&gpio 1 GPIO_ACTIVE_LOW>;\n\t\t\ttrigger-sources = <&ohci_port1>, <&ehci_port1>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\t};\n\n\tgpio_export {\n\t\tcompatible = \"gpio-export\";\n\t\t#size-cells = <0>;\n\n\t\tusbpower {\n\t\t\tgpio-export,name = \"usbpower\";\n\t\t\tgpio-export,output = <1>;\n\t\t\tgpios = <&gpio 6 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\t\tbroken-flash-reset;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-config\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0xe90000>;\n\t\t\t};\n\n\t\t\tpartition@ee0000 {\n\t\t\t\tlabel = \"config_1\";\n\t\t\t\treg = <0xee0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@ef0000 {\n\t\t\t\tlabel = \"storage\";\n\t\t\t\treg = <0xef0000 0x100000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@ff0000 {\n\t\t\t\tlabel = \"dump\";\n\t\t\t\treg = <0xff0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@1000000 {\n\t\t\t\tlabel = \"u-state\";\n\t\t\t\treg = <0x1000000 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@1030000 {\n\t\t\t\tlabel = \"u-config_res\";\n\t\t\t\treg = <0x1030000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@1040000 {\n\t\t\t\tlabel = \"rf-eeprom_res\";\n\t\t\t\treg = <0x1040000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@1050000 {\n\t\t\t\tlabel = \"firmware_2\";\n\t\t\t\treg = <0x1050000 0xe90000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@1ee0000 {\n\t\t\t\tlabel = \"config_2\";\n\t\t\t\treg = <0x1ee0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&esw {\n\tmediatek,portmap = <0x3e>;\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tmediatek,mtd-eeprom = <&factory 0x0>;\n};\n\n&pcie {\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\tmt76@0,0 {\n\t\treg = <0x0000 0 0 0 0>;\n\t\tmediatek,mtd-eeprom = <&factory 0x8000>;\n\t\tieee80211-freq-limit = <5000000 6000000>;\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"gpio\", \"i2s\", \"refclk\", \"spi cs1\", \"uart1\", \"wled_an\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt2880.dtsi",
    "content": "/dts-v1/;\n\n/ {\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\tcompatible = \"ralink,rt2880-soc\";\n\n\taliases {\n\t\tserial0 = &uartlite;\n\t};\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu@0 {\n\t\t\tcompatible = \"mips,mips24KEc\";\n\t\t\treg = <0>;\n\t\t};\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,57600\";\n\t};\n\n\tcpuintc: cpuintc {\n\t\t#address-cells = <0>;\n\t\t#interrupt-cells = <1>;\n\t\tinterrupt-controller;\n\t\tcompatible = \"mti,cpu-interrupt-controller\";\n\t};\n\n\tpalmbus: palmbus@300000 {\n\t\tcompatible = \"palmbus\";\n\t\treg = <0x300000 0x200000>;\n\t\tranges = <0x0 0x300000 0x1FFFFF>;\n\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tsysc: sysc@0 {\n\t\t\tcompatible = \"ralink,rt2880-sysc\";\n\t\t\treg = <0x000 0x100>;\n\t\t};\n\n\t\ttimer: timer@100 {\n\t\t\tcompatible = \"ralink,rt2880-timer\";\n\t\t\treg = <0x100 0x20>;\n\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <1>;\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\twatchdog: watchdog@120 {\n\t\t\tcompatible = \"ralink,rt2880-wdt\";\n\t\t\treg = <0x120 0x10>;\n\t\t};\n\n\t\tintc: intc@200 {\n\t\t\tcompatible = \"ralink,rt2880-intc\";\n\t\t\treg = <0x200 0x100>;\n\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <1>;\n\n\t\t\tinterrupt-parent = <&cpuintc>;\n\t\t\tinterrupts = <2>;\n\t\t};\n\n\t\tmemc: memc@300 {\n\t\t\tcompatible = \"ralink,rt2880-memc\";\n\t\t\treg = <0x300 0x100>;\n\t\t};\n\n\t\tgpio0: gpio@600 {\n\t\t\tcompatible = \"ralink,rt2880-gpio\";\n\t\t\treg = <0x600 0x34>;\n\n\t\t\tgpio-controller;\n\t\t\t#gpio-cells = <2>;\n\n\t\t\tngpios = <24>;\n\t\t\tralink,gpio-base = <0>;\n\t\t\tralink,register-map = [ 00 04 08 0c\n\t\t\t\t\t\t20 24 28 2c\n\t\t\t\t\t\t30 34 ];\n\t\t};\n\n\t\tgpio1: gpio@638 {\n\t\t\tcompatible = \"ralink,rt2880-gpio\";\n\t\t\treg = <0x638 0x24>;\n\n\t\t\tgpio-controller;\n\t\t\t#gpio-cells = <2>;\n\n\t\t\tngpios = <16>;\n\t\t\tralink,gpio-base = <24>;\n\t\t\tralink,register-map = [ 00 04 08 0c\n\t\t\t\t\t\t10 14 18 1c\n\t\t\t\t\t\t20 24 ];\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tgpio2: gpio@660 {\n\t\t\tcompatible = \"ralink,rt2880-gpio\";\n\t\t\treg = <0x660 0x24>;\n\n\t\t\tgpio-controller;\n\t\t\t#gpio-cells = <2>;\n\n\t\t\tngpios = <32>;\n\t\t\tralink,gpio-base = <40>;\n\t\t\tralink,register-map = [ 00 04 08 0c\n\t\t\t\t\t\t10 14 18 1c\n\t\t\t\t\t\t20 24 ];\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\ti2c: i2c@900 {\n\t\t\tcompatible = \"ralink,rt2880-i2c\";\n\t\t\treg = <0x900 0x100>;\n\n\t\t\tresets = <&rstctrl 9>;\n\t\t\treset-names = \"i2c\";\n\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\n\t\t\tstatus = \"disabled\";\n\n\t\t\tpinctrl-names = \"default\";\n\t\t\tpinctrl-0 = <&i2c_pins>;\n\t\t};\n\n\t\tuartlite: uartlite@c00 {\n\t\t\tcompatible = \"ralink,rt2880-uart\", \"ns16550a\";\n\t\t\treg = <0xc00 0x100>;\n\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <8>;\n\n\t\t\treg-shift = <2>;\n\t\t};\n\t};\n\n\tpinctrl: pinctrl {\n\t\tcompatible = \"ralink,rt2880-pinmux\";\n\n\t\tpinctrl-names = \"default\";\n\t\tpinctrl-0 = <&state_default>;\n\n\t\tstate_default: pinctrl0 {\n\t\t\tsdram {\n\t\t\t\tgroups = \"sdram\";\n\t\t\t\tfunction = \"sdram\";\n\t\t\t};\n\t\t};\n\n\t\ti2c_pins: i2c_pins {\n\t\t\ti2c_pins {\n\t\t\t\tgroups = \"i2c\";\n\t\t\t\tfunction = \"i2c\";\n\t\t\t};\n\t\t};\n\n\t\tspi_pins: spi_pins {\n\t\t\tspi_pins {\n\t\t\t\tgroups = \"spi\";\n\t\t\t\tfunction = \"spi\";\n\t\t\t};\n\t\t};\n\n\t\tuartlite_pins: uartlite {\n\t\t\tuart {\n\t\t\t\tgroups = \"uartlite\";\n\t\t\t\tfunction = \"uartlite\";\n\t\t\t};\n\t\t};\n\t};\n\n\trstctrl: rstctrl {\n\t\tcompatible = \"ralink,rt2880-reset\";\n\t\t#reset-cells = <1>;\n\t};\n\n\tclkctrl: clkctrl {\n\t\tcompatible = \"ralink,rt2880-clock\";\n\t\t#clock-cells = <1>;\n\t};\n\n\tpci: pci@440000 {\n\t\tcompatible = \"ralink,rt288x-pci\";\n\t\treg = <0x00440000 0x20000>;\n\t\t#address-cells = <3>;\n\t\t#size-cells = <2>;\n\t\tstatus = \"disabled\";\n\t};\n\n\tethernet: ethernet@400000 {\n\t\tcompatible = \"ralink,rt2880-eth\";\n\t\treg = <0x00400000 0x10000>;\n\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tresets = <&rstctrl 18>;\n\t\treset-names = \"fe\";\n\n\t\tinterrupt-parent = <&cpuintc>;\n\t\tinterrupts = <5>;\n\n\t\tstatus = \"disabled\";\n\n\t\tport@0 {\n\t\t\tcompatible = \"ralink,rt2880-port\", \"mediatek,eth-port\";\n\t\t\treg = <0>;\n\t\t};\n\n\t\tmdio-bus {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\t};\n\n\twmac: wmac@480000 {\n\t\tcompatible = \"ralink,rt2880-wmac\";\n\t\treg = <0x480000 0x40000>;\n\n\t\tinterrupt-parent = <&cpuintc>;\n\t\tinterrupts = <6>;\n\n\t\tralink,eeprom = \"soc_wmac.eeprom\";\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt2880_airlink101_ar670w.dts",
    "content": "#include \"rt2880.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"airlink101,ar670w\", \"ralink,rt2880-soc\";\n\tmodel = \"Airlink101 AR670W\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tflash@bdc00000 {\n\t\tcompatible = \"cfi-flash\";\n\t\treg = <0xbc400000 0x800000>;\n\t\tbank-width = <2>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@30000 {\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tlabel = \"factory\";\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tcompatible = \"lzma\";\n\t\t\t\treg = <0x40000 0x3c0000>;\n\t\t\t\tlabel = \"firmware\";\n\t\t\t};\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio0 7 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twpsblue {\n\t\t\tlabel = \"blue:wps\";\n\t\t\tgpios = <&gpio0 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <100>;\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio0 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 9 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"spi\", \"uartlite\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tstatus = \"okay\";\n\tnvmem-cells = <&macaddr_factory_2004>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tport@0 {\n\t\tphy-handle = <&phy0>;\n\t\tphy-mode = \"mii\";\n\t};\n\n\tmdio-bus {\n\t\tstatus = \"okay\";\n\n\t\tphy0: ethernet-phy@0 {\n\t\t\tphy-mode = \"mii\";\n\t\t\treg = <0>;\n\t\t};\n\t};\n};\n\n&wmac {\n\tstatus = \"okay\";\n\tralink,mtd-eeprom = <&factory 0x2000>;\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_2004: macaddr@2004 {\n\t\treg = <0x2004 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt2880_airlink101_ar725w.dts",
    "content": "#include \"rt2880.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"airlink101,ar725w\", \"ralink,rt2880-soc\";\n\tmodel = \"Airlink101 AR725W\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tflash@bdc00000 {\n\t\tcompatible = \"cfi-flash\";\n\t\treg = <0xbc400000 0x800000>;\n\t\tbank-width = <2>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tlabel = \"factory\";\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\treg = <0x50000 0x3B0000>;\n\t\t\t\tlabel = \"firmware\";\n\t\t\t};\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio0 7 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\twpsred {\n\t\t\tlabel = \"red:wps\";\n\t\t\tgpios = <&gpio0 8 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twpsblue {\n\t\t\tlabel = \"blue:wps\";\n\t\t\tgpios = <&gpio0 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <100>;\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio0 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 9 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"spi\", \"uartlite\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tstatus = \"okay\";\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tport@0 {\n\t\tphy-handle = <&phy0>;\n\t\tphy-mode = \"mii\";\n\t};\n\n\tmdio-bus {\n\t\tstatus = \"okay\";\n\n\t\tphy0: ethernet-phy@0 {\n\t\t\tphy-mode = \"mii\";\n\t\t\treg = <0>;\n\t\t};\n\t};\n};\n\n&wmac {\n\tstatus = \"okay\";\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt2880_asus_rt-n15.dts",
    "content": "#include \"rt2880.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\tcompatible = \"asus,rt-n15\", \"ralink,rt2880-soc\";\n\tmodel = \"Asus RT-N15\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tflash@1f000000 {\n\t\tcompatible = \"cfi-flash\";\n\t\treg = <0x1f000000 0x800000>;\n\t\tbank-width = <2>;\n\t\tdevice-width = <2>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"uboot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"uboot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x3b0000>;\n\t\t\t};\n\t\t};\n\t};\n\n\trtl8366s {\n\t\tcompatible = \"realtek,rtl8366s\";\n\t\tgpio-sda = <&gpio0 1 GPIO_ACTIVE_HIGH>;\n\t\tgpio-sck = <&gpio0 2 GPIO_ACTIVE_HIGH>;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <100>;\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"blue:power\";\n\t\t\tgpios = <&gpio0 11 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"uartlite\", \"mdio\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tstatus = \"okay\";\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tport@0 {\n\t\tmediatek,fixed-link = <1000 1 1 1>;\n\t};\n\n\tmdio-bus {\n\t\tstatus = \"okay\";\n\n\t\tphy0: ethernet-phy@0 {\n\t\t\tphy-mode = \"mii\";\n\t\t\treg = <0>;\n\t\t};\n\t};\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt2880_belkin_f5d8235-v1.dts",
    "content": "#include \"rt2880.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\tcompatible = \"belkin,f5d8235-v1\", \"ralink,rt2880-soc\";\n\tmodel = \"Belkin F5D8235 v1\";\n\n\taliases {\n\t\tled-boot = &led_wired_blue;\n\t\tled-failsafe = &led_wired_blue;\n\t};\n\n\tflash@1f000000 {\n\t\tcompatible = \"cfi-flash\";\n\t\treg = <0xbc400000 0x800000>;\n\t\tbank-width = <2>;\n\t\tdevice-width = <2>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"uboot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"uboot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x7b0000>;\n\t\t\t};\n\t\t};\n\t};\n\n\trtl8366s {\n\t\tcompatible = \"realtek,rtl8366s\";\n\t\tgpio-sda = <&gpio0 1 GPIO_ACTIVE_HIGH>;\n\t\tgpio-sck = <&gpio0 2 GPIO_ACTIVE_HIGH>;\n\n\t\trealtek,initvals = <\n\t\t\t0x0242 0x02BF\n\t\t\t0x0245 0x02BF\n\t\t\t0x0248 0x02BF\n\t\t\t0x024B 0x02BF\n\t\t\t0x024E 0x02BF\n\t\t\t0x0251 0x02BF\n\t\t\t0x0254 0x0A3F\n\t\t\t0x0256 0x0A3F\n\t\t\t0x0258 0x0A3F\n\t\t\t0x025A 0x0A3F\n\t\t\t0x025C 0x0A3F\n\t\t\t0x025E 0x0A3F\n\t\t\t0x0263 0x007C\n\t\t\t0x0100 0x0004\n\t\t\t0xBE5B 0x3500\n\t\t\t0x800E 0x200F\n\t\t\t0xBE1D 0x0F00\n\t\t\t0x8001 0x5011\n\t\t\t0x800A 0xA2F4\n\t\t\t0x800B 0x17A3\n\t\t\t0xBE4B 0x17A3\n\t\t\t0xBE41 0x5011\n\t\t\t0xBE17 0x2100\n\t\t\t0x8000 0x8304\n\t\t\t0xBE40 0x8304\n\t\t\t0xBE4A 0xA2F4\n\t\t\t0x800C 0xA8D5\n\t\t\t0x8014 0x5500\n\t\t\t0x8015 0x0004\n\t\t\t0xBE4C 0xA8D5\n\t\t\t0xBE59 0x0008\n\t\t\t0xBE09 0x0E00\n\t\t\t0xBE36 0x1036\n\t\t\t0xBE37 0x1036\n\t\t\t0x800D 0x00FF\n\t\t\t0xBE4D 0x00FF\n\t\t>;\n\n\t\trealtek,green-ethernet-features;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <100>;\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio0 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 9 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tinternet {\n\t\t\tlabel = \"blue:internet\";\n\t\t\tgpios = <&gpio0 17 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tinternet2 {\n\t\t\tlabel = \"amber:internet\";\n\t\t\tgpios = <&gpio0 18 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tmodem {\n\t\t\tlabel = \"blue:modem\";\n\t\t\tgpios = <&gpio0 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tmodem2 {\n\t\t\tlabel = \"amber:modem\";\n\t\t\tgpios = <&gpio0 21 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\trouter {\n\t\t\tlabel = \"blue:router\";\n\t\t\tgpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tstorage {\n\t\t\tlabel = \"blue:storage\";\n\t\t\tgpios = <&gpio0 7 GPIO_ACTIVE_LOW>;\n\t\t\ttrigger-sources = <&ohci_port1>, <&ehci_port1>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\n\t\tstorage2 {\n\t\t\tlabel = \"amber:storage\";\n\t\t\tgpios = <&gpio0 8 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tsecurity {\n\t\t\tlabel = \"blue:security\";\n\t\t\tgpios = <&gpio0 10 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tsecurity2 {\n\t\t\tlabel = \"amber:security\";\n\t\t\tgpios = <&gpio0 12 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_wired_blue: wired {\n\t\t\tlabel = \"blue:wired\";\n\t\t\tgpios = <&gpio0 5 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twired2 {\n\t\t\tlabel = \"amber:wired\";\n\t\t\tgpios = <&gpio0 20 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twireless {\n\t\t\tlabel = \"blue:wireless\";\n\t\t\tgpios = <&gpio0 6 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twireless2 {\n\t\t\tlabel = \"amber:wireless\";\n\t\t\tgpios = <&gpio0 19 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"spi\", \"i2c\", \"jtag\", \"mdio\", \"uartlite\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tstatus = \"okay\";\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tport@0 {\n\t\tmediatek,fixed-link = <1000 1 1 1>;\n\t};\n};\n\n&pci {\n\tstatus = \"okay\";\n\n\tusb@11,0 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tcompatible = \"pci1033,0035\";\n\t\treg = <0x8800 0 0 0 0>;\n\n\t\tohci_port1: port@1 {\n\t\t\treg = <1>;\n\t\t\t#trigger-source-cells = <0>;\n\t\t};\n\t};\n\n\tusb@11,1 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tcompatible = \"pci1033,00e0\";\n\t\treg = <0x8900 0 0 0 0>;\n\n\t\tehci_port1: port@1 {\n\t\t\treg = <1>;\n\t\t\t#trigger-source-cells = <0>;\n\t\t};\n\t};\n};\n\n&wmac {\n\tstatus = \"okay\";\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt2880_buffalo_wli-tx4-ag300n.dts",
    "content": "#include \"rt2880.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\tcompatible = \"buffalo,wli-tx4-ag300n\", \"ralink,rt2880-soc\";\n\tmodel = \"Buffalo WLI-TX4-AG300N\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tflash@1f000000 {\n\t\tcompatible = \"cfi-flash\";\n\t\treg = <0x1f000000 0x800000>;\n\t\tbank-width = <2>;\n\t\tdevice-width = <2>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"uboot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"uboot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x3b0000>;\n\t\t\t};\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <100>;\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio0 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\n\t\tbandwidth {\n\t\t\tlabel = \"bandwidth\";\n\t\t\tgpios = <&gpio0 8 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 9 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tdiag {\n\t\t\tlabel = \"red:diag\";\n\t\t\tgpios = <&gpio0 10 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_power: power {\n\t\t\tlabel = \"blue:power\";\n\t\t\tgpios = <&gpio0 12 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tsecurity {\n\t\t\tlabel = \"blue:security\";\n\t\t\tgpios = <&gpio0 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&ethernet {\n\tstatus = \"okay\";\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tport@0 {\n\t\tmediatek,fixed-link = <100 1 1 1>;\n\t};\n\n\tmdio-bus {\n\t\tstatus = \"okay\";\n\n\t\tphy0: ethernet-phy@0 {\n\t\t\tphy-mode = \"mii\";\n\t\t\treg = <0>;\n\t\t};\n\t};\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt2880_buffalo_wzr-agl300nh.dts",
    "content": "#include \"rt2880.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\tcompatible = \"buffalo,wzr-agl300nh\", \"ralink,rt2880-soc\";\n\tmodel = \"Buffalo WZR-AGL300NH\";\n\n\taliases {\n\t\tled-boot = &led_router;\n\t\tled-failsafe = &led_router;\n\t\tled-running = &led_router;\n\t\tled-upgrade = &led_router;\n\t};\n\n\tflash@1f000000 {\n\t\tcompatible = \"cfi-flash\";\n\t\treg = <0x1f000000 0x800000>;\n\t\tbank-width = <2>;\n\t\tdevice-width = <2>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"uboot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"uboot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x3b0000>;\n\t\t\t};\n\t\t};\n\t};\n\n\trtl8366s {\n\t\tcompatible = \"realtek,rtl8366s\";\n\t\tgpio-sda = <&gpio0 1 GPIO_ACTIVE_HIGH>;\n\t\tgpio-sck = <&gpio0 2 GPIO_ACTIVE_HIGH>;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <100>;\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio0 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\n\t\trouter {\n\t\t\tlabel = \"router_switch\";\n\t\t\tgpios = <&gpio0 7 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = <BTN_0>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 9 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_router: router {\n\t\t\tlabel = \"green:router\";\n\t\t\tgpios = <&gpio0 8 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tdiag {\n\t\t\tlabel = \"red:diag\";\n\t\t\tgpios = <&gpio0 12 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tsecurity_g {\n\t\t\tlabel = \"orange:security_g\";\n\t\t\tgpios = <&gpio0 11 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tsecurity_n {\n\t\t\tlabel = \"orange:security_n\";\n\t\t\tgpios = <&gpio0 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"uartlite\", \"mdio\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tstatus = \"okay\";\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tport@0 {\n\t\tmediatek,fixed-link = <1000 1 1 1>;\n\t};\n\n\tmdio-bus {\n\t\tstatus = \"okay\";\n\n\t\tphy0: ethernet-phy@0 {\n\t\t\tphy-mode = \"mii\";\n\t\t\treg = <0>;\n\t\t};\n\t};\n};\n\n&pci {\n\tstatus = \"okay\";\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt2880_dlink_dap-1522-a1.dts",
    "content": "#include \"rt2880.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"dlink,dap-1522-a1\", \"ralink,rt2880-soc\";\n\tmodel = \"D-Link DAP-1522 A1\";\n\n\taliases {\n\t\tled-boot = &led_status;\n\t\tled-failsafe = &led_status;\n\t\tled-running = &led_status;\n\t\tled-upgrade = &led_status;\n\t};\n\n\tflash@bc400000 {\n\t\tcompatible = \"cfi-flash\";\n\t\treg = <0xbc400000 0x800000>;\n\t\tbank-width = <2>;\n\t\tdevice-width = <2>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"uboot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@30000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tcompatible = \"wrg\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x40000 0x3a0000>;\n\t\t\t};\n\t\t};\n\t};\n\n\trtl8366s {\n\t\tcompatible = \"realtek,rtl8366s\";\n\t\tgpio-sda = <&gpio0 1 GPIO_ACTIVE_HIGH>;\n\t\tgpio-sck = <&gpio0 2 GPIO_ACTIVE_HIGH>;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <100>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 9 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio2 16 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\n\t\tap {\n\t\t\tlabel = \"ap\";\n\t\t\tgpios = <&gpio2 13 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_0>;\n\t\t\tlinux,input-type = <EV_SW>;\n\t\t};\n\n\t\tbridge {\n\t\t\tlabel = \"bridge\";\n\t\t\tgpios = <&gpio2 14 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_1>;\n\t\t\tlinux,input-type = <EV_SW>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twps {\n\t\t\tlabel = \"blue:wps\";\n\t\t\tgpios = <&gpio2 17 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tap {\n\t\t\tlabel = \"blue:ap\";\n\t\t\tgpios = <&gpio2 18 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tsta {\n\t\t\tlabel = \"red:sta\";\n\t\t\tgpios = <&gpio2 19 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_status: status {\n\t\t\tlabel = \"blue:status\";\n\t\t\tgpios = <&gpio2 20 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&gpio2 {\n\tstatus = \"okay\";\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"uartlite\", \"pci\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tstatus = \"okay\";\n\tnvmem-cells = <&macaddr_factory_2004>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tport@0 {\n\t\tmediatek,fixed-link = <1000 1 1 1>;\n\t};\n\n\tmdio-bus {\n\t\tstatus = \"okay\";\n\n\t\tphy0: ethernet-phy@0 {\n\t\t\tphy-mode = \"mii\";\n\t\t\treg = <0>;\n\t\t};\n\t};\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x2000>;\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_2004: macaddr@2004 {\n\t\treg = <0x2004 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt2880_ralink_v11st-fe.dts",
    "content": "#include \"rt2880.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"ralink,v11st-fe\", \"ralink,rt2880-soc\";\n\tmodel = \"Ralink V11ST-FE\";\n\n\taliases {\n\t\tled-boot = &led_status;\n\t\tled-failsafe = &led_status;\n\t\tled-running = &led_status;\n\t\tled-upgrade = &led_status;\n\t};\n\n\tflash@1c000000 {\n\t\tcompatible = \"cfi-flash\";\n\t\treg = <0x1c000000 0x800000>;\n\t\tbank-width = <2>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\treg = <0x0 0x0030000>;\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\treg = <0x00030000 0x00010000>;\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\treg = <0x00040000 0x00010000>;\n\t\t\t\tlabel = \"factory\";\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\treg = <0x00050000 0x003b0000>;\n\t\t\t\tlabel = \"firmware\";\n\t\t\t};\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <100>;\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_status: status {\n\t\t\tlabel = \"green:status\";\n\t\t\tgpios = <&gpio0 12 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&ethernet {\n\tstatus = \"okay\";\n};\n\n&pci {\n\tstatus = \"okay\";\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt3050.dtsi",
    "content": "/dts-v1/;\n\n/ {\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\tcompatible = \"ralink,rt3050-soc\", \"ralink,rt3052-soc\", \"ralink,rt3350-soc\";\n\n\taliases {\n\t\tspi0 = &spi0;\n\t\tserial0 = &uartlite;\n\t};\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu@0 {\n\t\t\tcompatible = \"mips,mips24KEc\";\n\t\t\treg = <0>;\n\t\t};\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,57600\";\n\t};\n\n\tcpuintc: cpuintc {\n\t\t#address-cells = <0>;\n\t\t#interrupt-cells = <1>;\n\t\tinterrupt-controller;\n\t\tcompatible = \"mti,cpu-interrupt-controller\";\n\t};\n\n\tpalmbus: palmbus@10000000 {\n\t\tcompatible = \"palmbus\";\n\t\treg = <0x10000000 0x200000>;\n\t\tranges = <0x0 0x10000000 0x1FFFFF>;\n\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tsysc: sysc@0 {\n\t\t\tcompatible = \"ralink,rt3050-sysc\", \"syscon\";\n\t\t\treg = <0x0 0x100>;\n\t\t};\n\n\t\ttimer: timer@100 {\n\t\t\tcompatible = \"ralink,rt3050-timer\", \"ralink,rt2880-timer\";\n\t\t\treg = <0x100 0x20>;\n\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <1>;\n\t\t};\n\n\t\twatchdog: watchdog@120 {\n\t\t\tcompatible = \"ralink,rt3050-wdt\", \"ralink,rt2880-wdt\";\n\t\t\treg = <0x120 0x10>;\n\n\t\t\tresets = <&rstctrl 8>;\n\t\t\treset-names = \"wdt\";\n\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <1>;\n\t\t};\n\n\t\tintc: intc@200 {\n\t\t\tcompatible = \"ralink,rt3050-intc\", \"ralink,rt2880-intc\";\n\t\t\treg = <0x200 0x100>;\n\n\t\t\tresets = <&rstctrl 19>;\n\t\t\treset-names = \"intc\";\n\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <1>;\n\n\t\t\tinterrupt-parent = <&cpuintc>;\n\t\t\tinterrupts = <2>;\n\t\t};\n\n\t\tmemc: memc@300 {\n\t\t\tcompatible = \"ralink,rt3050-memc\";\n\t\t\treg = <0x300 0x100>;\n\n\t\t\tresets = <&rstctrl 20>;\n\t\t\treset-names = \"mc\";\n\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <3>;\n\t\t};\n\n\t\tuart: uart@500 {\n\t\t\tcompatible = \"ralink,rt3050-uart\", \"ralink,rt2880-uart\", \"ns16550a\";\n\t\t\treg = <0x500 0x100>;\n\n\t\t\tresets = <&rstctrl 12>;\n\t\t\treset-names = \"uart\";\n\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <5>;\n\n\t\t\treg-shift = <2>;\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tgpio0: gpio@600 {\n\t\t\tcompatible = \"ralink,rt3050-gpio\", \"ralink,rt2880-gpio\";\n\t\t\treg = <0x600 0x34>;\n\n\t\t\tgpio-controller;\n\t\t\t#gpio-cells = <2>;\n\n\t\t\tngpios = <24>;\n\t\t\tralink,gpio-base = <0>;\n\t\t\tralink,register-map = [ 00 04 08 0c\n\t\t\t\t\t\t20 24 28 2c\n\t\t\t\t\t\t30 34 ];\n\n\t\t\tresets = <&rstctrl 13>;\n\t\t\treset-names = \"pio\";\n\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <6>;\n\t\t};\n\n\t\tgpio1: gpio@638 {\n\t\t\tcompatible = \"ralink,rt3050-gpio\", \"ralink,rt2880-gpio\";\n\t\t\treg = <0x638 0x24>;\n\n\t\t\tgpio-controller;\n\t\t\t#gpio-cells = <2>;\n\n\t\t\tngpios = <16>;\n\t\t\tralink,gpio-base = <24>;\n\t\t\tralink,register-map = [ 00 04 08 0c\n\t\t\t\t\t\t10 14 18 1c\n\t\t\t\t\t\t20 24 ];\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tgpio2: gpio@660 {\n\t\t\tcompatible = \"ralink,rt3050-gpio\", \"ralink,rt2880-gpio\";\n\t\t\treg = <0x660 0x24>;\n\n\t\t\tgpio-controller;\n\t\t\t#gpio-cells = <2>;\n\n\t\t\tngpios = <12>;\n\t\t\tralink,gpio-base = <40>;\n\t\t\tralink,register-map = [ 00 04 08 0c\n\t\t\t\t\t\t10 14 18 1c\n\t\t\t\t\t\t20 24 ];\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tgdma: gdma@700 {\n\t\t\tcompatible = \"ralink,rt305x-gdma\";\n\t\t\treg = <0x700 0x100>;\n\n\t\t\tresets = <&rstctrl 14>;\n\t\t\treset-names = \"dma\";\n\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <7>;\n\n\t\t\t#dma-cells = <1>;\n\t\t\t#dma-channels = <8>;\n\t\t\t#dma-requests = <8>;\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\ti2c@900 {\n\t\t\tcompatible = \"ralink,rt2880-i2c\";\n\t\t\treg = <0x900 0x100>;\n\n\t\t\tresets = <&rstctrl 16>;\n\t\t\treset-names = \"i2c\";\n\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\n\t\t\tstatus = \"disabled\";\n\n\t\t\tpinctrl-names = \"default\";\n\t\t\tpinctrl-0 = <&i2c_pins>;\n\t\t};\n\n\t\ti2s@a00 {\n\t\t\tcompatible = \"ralink,rt3050-i2s\";\n\t\t\treg = <0xa00 0x100>;\n\n\t\t\tresets = <&rstctrl 17>;\n\t\t\treset-names = \"i2s\";\n\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <10>;\n\n\t\t\ttxdma-req = <2>;\n\n\t\t\tdmas = <&gdma 4>;\n\t\t\tdma-names = \"tx\";\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tspi0: spi@b00 {\n\t\t\tcompatible = \"ralink,rt3050-spi\", \"ralink,rt2880-spi\";\n\t\t\treg = <0xb00 0x100>;\n\n\t\t\tresets = <&rstctrl 18>;\n\t\t\treset-names = \"spi\";\n\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\n\t\t\tpinctrl-names = \"default\";\n\t\t\tpinctrl-0 = <&spi_pins>;\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tuartlite: uartlite@c00 {\n\t\t\tcompatible = \"ralink,rt3050-uart\", \"ralink,rt2880-uart\", \"ns16550a\";\n\t\t\treg = <0xc00 0x100>;\n\n\t\t\tresets = <&rstctrl 19>;\n\t\t\treset-names = \"uartl\";\n\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <12>;\n\n\t\t\treg-shift = <2>;\n\n\t\t\tpinctrl-names = \"default\";\n\t\t\tpinctrl-0 = <&uartlite_pins>;\n\t\t};\n\t};\n\n\tpinctrl: pinctrl {\n\t\tcompatible = \"ralink,rt2880-pinmux\";\n\n\t\tpinctrl-names = \"default\";\n\t\tpinctrl-0 = <&state_default>;\n\n\t\tstate_default: pinctrl0 {\n\t\t\tsdram {\n\t\t\t\tgroups = \"sdram\";\n\t\t\t\tfunction = \"sdram\";\n\t\t\t};\n\t\t};\n\n\t\ti2c_pins: i2c_pins {\n\t\t\ti2c_pins {\n\t\t\t\tgroups = \"i2c\";\n\t\t\t\tfunction = \"i2c\";\n\t\t\t};\n\t\t};\n\n\t\tspi_pins: spi_pins {\n\t\t\tspi_pins {\n\t\t\t\tgroups = \"spi\";\n\t\t\t\tfunction = \"spi\";\n\t\t\t};\n\t\t};\n\n\t\trgmii_pins: rgmii {\n\t\t\trgmii {\n\t\t\t\tgroups = \"rgmii\";\n\t\t\t\tfunction = \"rgmii\";\n\t\t\t};\n\t\t};\n\n\t\tuartlite_pins: uartlite {\n\t\t\tuart {\n\t\t\t\tgroups = \"uartlite\";\n\t\t\t\tfunction = \"uartlite\";\n\t\t\t};\n\t\t};\n\t};\n\n\trstctrl: rstctrl {\n\t\tcompatible = \"ralink,rt3050-reset\", \"ralink,rt2880-reset\";\n\t\t#reset-cells = <1>;\n\t};\n\n\tclkctrl: clkctrl {\n\t\tcompatible = \"ralink,rt2880-clock\";\n\t\t#clock-cells = <1>;\n\t};\n\n\tusbphy: usbphy {\n\t\tcompatible = \"ralink,rt3050-usbphy\";\n\t\t#phy-cells = <0>;\n\n\t\tralink,sysctl = <&sysc>;\n\t\tresets = <&rstctrl 22>;\n\t\treset-names = \"host\";\n\t\tclocks = <&clkctrl 18>;\n\t\tclock-names = \"host\";\n\t};\n\n\tethernet: ethernet@10100000 {\n\t\tcompatible = \"ralink,rt3050-eth\";\n\t\treg = <0x10100000 0x10000>;\n\n\t\tresets = <&rstctrl 21>;\n\t\treset-names = \"fe\";\n\n\t\tinterrupt-parent = <&cpuintc>;\n\t\tinterrupts = <5>;\n\n\t\tmediatek,switch = <&esw>;\n\t};\n\n\tesw: esw@10110000 {\n\t\tcompatible = \"ralink,rt3050-esw\";\n\t\treg = <0x10110000 0x8000>;\n\n\t\tresets = <&rstctrl 23 &rstctrl 24>;\n\t\treset-names = \"esw\", \"ephy\";\n\n\t\tinterrupt-parent = <&intc>;\n\t\tinterrupts = <17>;\n\t};\n\n\twmac: wmac@10180000 {\n\t\tcompatible = \"ralink,rt3050-wmac\", \"ralink,rt2880-wmac\";\n\t\treg = <0x10180000 0x40000>;\n\n\t\tinterrupt-parent = <&cpuintc>;\n\t\tinterrupts = <6>;\n\n\t\tralink,eeprom = \"soc_wmac.eeprom\";\n\t};\n\n\totg: otg@101c0000 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tcompatible = \"ralink,rt3050-otg\", \"snps,dwc2\";\n\t\treg = <0x101c0000 0x40000>;\n\n\t\tinterrupt-parent = <&intc>;\n\t\tinterrupts = <18>;\n\n\t\tresets = <&rstctrl 22>;\n\t\treset-names = \"otg\";\n\n\t\tstatus = \"disabled\";\n\n\t\totg_port1: port@1 {\n\t\t\treg = <1>;\n\t\t\t#trigger-source-cells = <0>;\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt3050_8devices_carambola.dts",
    "content": "#include \"rt3050.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"8devices,carambola\", \"ralink,rt3050-soc\";\n\tmodel = \"8devices Carambola\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200\";\n\t};\n\n\tflash@1f000000 {\n\t\tcompatible = \"cfi-flash\";\n\t\treg = <0x1f000000 0x800000>;\n\t\tbank-width = <2>;\n\t\tdevice-width = <2>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x7b0000>;\n\t\t\t};\n\t\t};\n\t};\n\n\ti2c-gpio {\n\t\tcompatible = \"i2c-gpio\";\n\t\tgpios = <&gpio0 1 GPIO_ACTIVE_HIGH &gpio0 2 GPIO_ACTIVE_HIGH>;\n\t\ti2c-gpio,delay-us = <10>;\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"spi\", \"i2c\", \"jtag\", \"rgmii\", \"mdio\", \"uartf\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_28>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&esw {\n\tmediatek,portmap = <0x3f>;\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&otg {\n\tstatus = \"okay\";\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_28: macaddr@28 {\n\t\treg = <0x28 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt3050_allnet_all0256n-4m.dts",
    "content": "#include \"rt3050_allnet_all0256n.dtsi\"\n\n/ {\n\tcompatible = \"allnet,all0256n-4m\", \"allnet,all0256n\", \"ralink,rt3050-soc\";\n\tmodel = \"Allnet ALL0256N (4M)\";\n};\n\n&firmware {\n\treg = <0x50000 0x3b0000>;\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt3050_allnet_all0256n-8m.dts",
    "content": "#include \"rt3050_allnet_all0256n.dtsi\"\n\n/ {\n\tcompatible = \"allnet,all0256n-8m\", \"allnet,all0256n\", \"ralink,rt3050-soc\";\n\tmodel = \"Allnet ALL0256N (8M)\";\n};\n\n&firmware {\n\treg = <0x50000 0x7b0000>;\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt3050_allnet_all0256n.dtsi",
    "content": "#include \"rt3050.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"allnet,all0256n\", \"ralink,rt3050-soc\";\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\trssilow {\n\t\t\tlabel = \"green:rssilow\";\n\t\t\tgpios = <&gpio0 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\trssimed {\n\t\t\tlabel = \"green:rssimed\";\n\t\t\tgpios = <&gpio0 12 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\trssihigh {\n\t\t\tlabel = \"green:rssihigh\";\n\t\t\tgpios = <&gpio0 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfirmware: partition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\t/* reg property is set based on flash size in DTS files */\n\t\t\t};\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"jtag\", \"rgmii\", \"mdio\", \"uartf\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_28>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&esw {\n\tmediatek,portmap = <0x3f>;\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_28: macaddr@28 {\n\t\treg = <0x28 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt3050_alphanetworks_asl26555-16m.dts",
    "content": "#include \"rt3050_alphanetworks_asl26555.dtsi\"\n\n/ {\n\tcompatible = \"alphanetworks,asl26555-16m\", \"alphanetworks,asl26555\", \"ralink,rt3050-soc\";\n\tmodel = \"Alpha ASL26555 (16M)\";\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"uboot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"uboot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0xf80000>;\n\t\t\t};\n\n\t\t\tpartition@fd0000 {\n\t\t\t\tlabel = \"cert\";\n\t\t\t\treg = <0xfd0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@fe0000 {\n\t\t\t\tlabel = \"langpack\";\n\t\t\t\treg = <0xfe0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tdevdata: partition@ff0000 {\n\t\t\t\tlabel = \"devdata\";\n\t\t\t\treg = <0xff0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_devdata_4004>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&devdata {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_devdata_4004: macaddr@4004 {\n\t\treg = <0x4004 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt3050_alphanetworks_asl26555-8m.dts",
    "content": "#include \"rt3050_alphanetworks_asl26555.dtsi\"\n\n/ {\n\tcompatible = \"alphanetworks,asl26555-8m\", \"alphanetworks,asl26555\", \"ralink,rt3050-soc\";\n\tmodel = \"Alpha ASL26555 (8M)\";\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"uboot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tdevdata: partition@30000 {\n\t\t\t\tlabel = \"uboot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"rgdb\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x790000>;\n\t\t\t};\n\n\t\t\tpartition@7e0000 {\n\t\t\t\tlabel = \"cert\";\n\t\t\t\treg = <0x7e0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@7f0000 {\n\t\t\t\tlabel = \"langpack\";\n\t\t\t\treg = <0x7f0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_devdata_4004>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&devdata {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_devdata_4004: macaddr@4004 {\n\t\treg = <0x4004 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt3050_alphanetworks_asl26555.dtsi",
    "content": "#include \"rt3050.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"alphanetworks,asl26555\", \"ralink,rt3050-soc\";\n\n\taliases {\n\t\tled-boot = &led_power_green;\n\t\tled-failsafe = &led_power_green;\n\t\tled-running = &led_power_green;\n\t\tled-upgrade = &led_power_green;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 10 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\teth {\n\t\t\tlabel = \"green:eth\";\n\t\t\tgpios = <&gpio0 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twan-red {\n\t\t\tlabel = \"red:wan\";\n\t\t\tgpios = <&gpio0 1 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\twan-green {\n\t\t\tlabel = \"green:wan\";\n\t\t\tgpios = <&gpio0 2 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\twlan {\n\t\t\tlabel = \"green:wlan\";\n\t\t\tgpios = <&gpio0 7 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tled_power_green: power-green {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio0 8 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tpower-red {\n\t\t\tlabel = \"red:power\";\n\t\t\tgpios = <&gpio0 9 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\t3g-green {\n\t\t\tlabel = \"green:3g\";\n\t\t\tgpios = <&gpio0 14 GPIO_ACTIVE_LOW>;\n\t\t\ttrigger-sources = <&otg_port1>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\n\t\t3g-red {\n\t\t\tlabel = \"red:3g\";\n\t\t\tgpios = <&gpio0 17 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"jtag\", \"rgmii\", \"mdio\", \"uartf\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&esw {\n\tmediatek,portmap = <0x1e>;\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&devdata 0x4000>;\n};\n\n&otg {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt3050_arcwireless_freestation5.dts",
    "content": "#include \"rt3050.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"arcwireless,freestation5\", \"ralink,rt3050-soc\";\n\tmodel = \"ARC FreeStation5\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200\";\n\t};\n\n\tflash@1f000000 {\n\t\tcompatible = \"cfi-flash\";\n\t\treg = <0x1f000000 0x800000>;\n\t\tbank-width = <2>;\n\t\tdevice-width = <2>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x7b0000>;\n\t\t\t};\n\t\t};\n\t};\n\n\tgpio-export {\n\t\tcompatible = \"gpio-export\";\n\n\t\t/*\n\t\t * Used to enable power-over-ethernet passthrough from port0 to port1.\n\t\t * Disable passthrough by default to prevent accidental equipment damage.\n\t\t */\n\t\tpoe {\n\t\t\tgpio-export,name = \"poe-passthrough\";\n\t\t\tgpio-export,output = <1>;\n\t\t\tgpios = <&gpio0 11 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\t/*\n\t\t * The following leds are defined in the ArcOS firmware, but reportedly\n\t\t * not present in the Freestation5 device.\n\t\t */\n\t\twifi {\n\t\t\tlabel = \"unknown:wifi\";\n\t\t\tgpios = <&gpio0 7 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tpowerg {\n\t\t\tlabel = \"unknown:powerg\";\n\t\t\tgpios = <&gpio0 9 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tusb {\n\t\t\tlabel = \"unknown:usb\";\n\t\t\tgpios = <&gpio0 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"spi\", \"i2c\", \"jtag\", \"rgmii\", \"mdio\", \"uartf\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&esw {\n\tmediatek,portmap = <0x01>;\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&otg {\n\tstatus = \"okay\";\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt3050_asus_rt-g32-b1.dts",
    "content": "#include \"rt3050.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"asus,rt-g32-b1\", \"ralink,rt3050-soc\";\n\tmodel = \"Asus RT-G32 B1\";\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 10 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio0 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"devdata\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tdevconf: partition@40000 {\n\t\t\t\tlabel = \"devconf\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x3b0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"jtag\", \"rgmii\", \"mdio\", \"uartf\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_devconf_4>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&esw {\n\tmediatek,portmap = <0x2f>;\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&devconf 0x0>;\n};\n\n&devconf {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_devconf_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt3050_asus_rt-n10-plus.dts",
    "content": "#include \"rt3050.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"asus,rt-n10-plus\", \"ralink,rt3050-soc\";\n\tmodel = \"Asus RT-N10+\";\n\n\taliases {\n\t\tled-boot = &led_wps;\n\t\tled-failsafe = &led_wps;\n\t\tled-running = &led_wps;\n\t\tled-upgrade = &led_wps;\n\t};\n\n\tflash@1f000000 {\n\t\tcompatible = \"cfi-flash\";\n\t\treg = <0x1f000000 0x800000>;\n\t\tbank-width = <2>;\n\t\tdevice-width = <2>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"devdata\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tdevconf: partition@40000 {\n\t\t\t\tlabel = \"devconf\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x3b0000>;\n\t\t\t};\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_wps: wps {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&gpio0 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 10 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio0 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_devconf_4>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&esw {\n\tmediatek,portmap = <0x3e>;\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&devconf 0x0>;\n};\n\n&devconf {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_devconf_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt3050_asus_wl-330n.dts",
    "content": "#include \"rt3050.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"asus,wl-330n\", \"ralink,rt3050-soc\";\n\tmodel = \"Asus WL-330N\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tlink {\n\t\t\tlabel = \"blue:link\";\n\t\t\tgpios = <&gpio0 9 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_power: power {\n\t\t\tlabel = \"blue:power\";\n\t\t\tgpios = <&gpio0 11 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 10 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio0 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x3b0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"jtag\", \"rgmii\", \"mdio\", \"uartf\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&esw {\n\tmediatek,portmap = <0x3e>;\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt3050_asus_wl-330n3g.dts",
    "content": "#include \"rt3050.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"asus,wl-330n3g\", \"ralink,rt3050-soc\";\n\tmodel = \"Asus WL-330N3G\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\t3g {\n\t\t\tlabel = \"blue:3g\";\n\t\t\tgpios = <&gpio0 9 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\t3g2 {\n\t\t\tlabel = \"red:3g\";\n\t\t\tgpios = <&gpio0 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_power: power {\n\t\t\tlabel = \"blue:power\";\n\t\t\tgpios = <&gpio0 11 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 10 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio0 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x3b0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"jtag\", \"rgmii\", \"mdio\", \"uartf\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&esw {\n\tmediatek,portmap = <0x3e>;\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&otg {\n\tstatus = \"okay\";\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt3050_dlink_dcs-930.dts",
    "content": "#include \"rt3050.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"dlink,dcs-930\", \"ralink,rt3050-soc\";\n\tmodel = \"D-Link DCS-930\";\n\n\taliases {\n\t\tled-boot = &led_status;\n\t\tled-failsafe = &led_status;\n\t\tled-running = &led_status;\n\t\tled-upgrade = &led_status;\n\t};\n\n\tflash@1f000000 {\n\t\tcompatible = \"cfi-flash\";\n\t\treg = <0x1f000000 0x400000>;\n\t\tbank-width = <2>;\n\t\tdevice-width = <2>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x3b0000>;\n\t\t\t};\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twifi {\n\t\t\tlabel = \"red:alert\";\n\t\t\tgpios = <&gpio0 8 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_status: status {\n\t\t\tlabel = \"green:status\";\n\t\t\tgpios = <&gpio0 9 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"blue:wps\";\n\t\t\tgpios = <&gpio0 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <20>;\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio0 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_1>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 10 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"spi\", \"jtag\", \"mdio\", \"rgmii\", \"uartf\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&esw {\n\tmediatek,portmap = <0x2f>;\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&otg {\n\tstatus = \"okay\";\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt3050_dlink_dir-300-b1.dts",
    "content": "#include \"rt3050.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"dlink,dir-300-b1\", \"ralink,rt3050-soc\";\n\tmodel = \"D-Link DIR-300 B1\";\n\n\taliases {\n\t\tled-boot = &led_status_green;\n\t\tled-failsafe = &led_status_green;\n\t\tled-running = &led_status_green;\n\t\tled-upgrade = &led_status_green;\n\t};\n\n\tflash@1f000000 {\n\t\tcompatible = \"cfi-flash\";\n\t\treg = <0x1f000000 0x800000>;\n\t\tbank-width = <2>;\n\t\tdevice-width = <2>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tdevdata: partition@30000 {\n\t\t\t\tlabel = \"devdata\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"devconf\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x3b0000>;\n\t\t\t};\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 10 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio0 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tstatus {\n\t\t\tlabel = \"amber:status\";\n\t\t\tgpios = <&gpio0 8 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_status_green: status2 {\n\t\t\tlabel = \"green:status\";\n\t\t\tgpios = <&gpio0 9 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twan {\n\t\t\tlabel = \"amber:wan\";\n\t\t\tgpios = <&gpio0 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twan2 {\n\t\t\tlabel = \"green:wan\";\n\t\t\tgpios = <&gpio0 12 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"blue:wps\";\n\t\t\tgpios = <&gpio0 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"spi\", \"jtag\", \"mdio\", \"rgmii\", \"uartf\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_devdata_4004>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&esw {\n\tmediatek,portmap = <0x2f>;\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&devdata 0x4000>;\n};\n\n&devdata {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_devdata_4004: macaddr@4004 {\n\t\treg = <0x4004 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt3050_dlink_dir-600-b1.dts",
    "content": "#include \"rt3050.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"dlink,dir-600-b1\", \"ralink,rt3050-soc\";\n\tmodel = \"D-Link DIR-600 B1\";\n\n\taliases {\n\t\tled-boot = &led_status_green;\n\t\tled-failsafe = &led_status_green;\n\t\tled-running = &led_status_green;\n\t\tled-upgrade = &led_status_green;\n\t};\n\n\tflash@1f000000 {\n\t\tcompatible = \"cfi-flash\";\n\t\treg = <0x1f000000 0x800000>;\n\t\tbank-width = <2>;\n\t\tdevice-width = <2>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tdevdata: partition@30000 {\n\t\t\t\tlabel = \"devdata\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"devconf\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x3b0000>;\n\t\t\t};\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 10 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio0 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tstatus {\n\t\t\tlabel = \"amber:status\";\n\t\t\tgpios = <&gpio0 8 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_status_green: status2 {\n\t\t\tlabel = \"green:status\";\n\t\t\tgpios = <&gpio0 9 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twan {\n\t\t\tlabel = \"amber:wan\";\n\t\t\tgpios = <&gpio0 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twan2 {\n\t\t\tlabel = \"green:wan\";\n\t\t\tgpios = <&gpio0 12 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"blue:wps\";\n\t\t\tgpios = <&gpio0 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"spi\", \"jtag\", \"mdio\", \"rgmii\", \"uartf\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_devdata_4004>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&esw {\n\tmediatek,portmap = <0x2f>;\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&devdata 0x4000>;\n};\n\n&devdata {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_devdata_4004: macaddr@4004 {\n\t\treg = <0x4004 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt3050_dlink_dir-615-d.dts",
    "content": "#include \"rt3050.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"dlink,dir-615-d\", \"ralink,rt3050-soc\";\n\tmodel = \"D-Link DIR-615 D\";\n\n\taliases {\n\t\tled-boot = &led_status_green;\n\t\tled-failsafe = &led_status_green;\n\t\tled-running = &led_status_green;\n\t\tled-upgrade = &led_status_green;\n\t\tlabel-mac-device = &wmac;\n\t};\n\n\tflash@1f000000 {\n\t\tcompatible = \"cfi-flash\";\n\t\treg = <0x1f000000 0x800000>;\n\t\tbank-width = <2>;\n\t\tdevice-width = <2>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tdevdata: partition@30000 {\n\t\t\t\tlabel = \"devdata\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"devconf\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x3b0000>;\n\t\t\t};\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 10 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio0 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tstatus_amber {\n\t\t\tlabel = \"amber:status\";\n\t\t\tgpios = <&gpio0 8 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_status_green: status_green {\n\t\t\tlabel = \"green:status\";\n\t\t\tgpios = <&gpio0 9 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\twan_amber {\n\t\t\tlabel = \"amber:wan\";\n\t\t\tgpios = <&gpio0 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twan_green {\n\t\t\tlabel = \"green:wan\";\n\t\t\tgpios = <&gpio0 12 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"blue:wps\";\n\t\t\tgpios = <&gpio0 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&esw {\n\tmediatek,portmap = <0x2f>;\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&devdata 0x4000>;\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"spi\", \"jtag\", \"mdio\", \"rgmii\", \"uartf\";\n\t\tfunction = \"gpio\";\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt3050_dlink_dir-620-a1.dts",
    "content": "#include \"rt3050.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"dlink,dir-620-a1\", \"ralink,rt3050-soc\";\n\tmodel = \"D-Link DIR-620 A1\";\n\n\taliases {\n\t\tled-boot = &led_status_green;\n\t\tled-failsafe = &led_status_green;\n\t\tled-running = &led_status_green;\n\t\tled-upgrade = &led_status_green;\n\t};\n\n\tflash@1f000000 {\n\t\tcompatible = \"cfi-flash\";\n\t\treg = <0x1f000000 0x800000>;\n\t\tbank-width = <2>;\n\t\tdevice-width = <2>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x7b0000>;\n\t\t\t};\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 10 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio0 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tstatus {\n\t\t\tlabel = \"amber:status\";\n\t\t\tgpios = <&gpio0 8 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_status_green: status2 {\n\t\t\tlabel = \"green:status\";\n\t\t\tgpios = <&gpio0 9 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twan {\n\t\t\tlabel = \"amber:wan\";\n\t\t\tgpios = <&gpio0 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twan2 {\n\t\t\tlabel = \"green:wan\";\n\t\t\tgpios = <&gpio0 12 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"blue:wps\";\n\t\t\tgpios = <&gpio0 13 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\twps2 {\n\t\t\tlabel = \"amber:wps\";\n\t\t\tgpios = <&gpio0 11 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"jtag\", \"rgmii\", \"mdio\", \"uartf\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&esw {\n\tmediatek,portmap = <0x2f>;\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&otg {\n\tstatus = \"okay\";\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt3050_edimax_3g-6200n.dts",
    "content": "#include \"rt3050.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/mtd/partitions/uimage.h>\n\n/ {\n\tcompatible = \"edimax,3g-6200n\", \"ralink,rt3050-soc\";\n\tmodel = \"Edimax 3g-6200n\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tflash@1f000000 {\n\t\tcompatible = \"cfi-flash\";\n\t\treg = <0x1f000000 0x800000>;\n\t\tbank-width = <2>;\n\t\tdevice-width = <2>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@3e0000 {\n\t\t\t\tlabel = \"cimage\";\n\t\t\t\treg = <0x3e0000 0x20000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"openwrt,uimage\", \"denx,uimage\";\n\t\t\t\topenwrt,offset = <FW_EDIMAX_OFFSET>;\n\t\t\t\topenwrt,partition-magic = <FW_MAGIC_EDIMAX>;\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x390000>;\n\t\t\t};\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio0 9 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan {\n\t\t\tlabel = \"amber:wlan\";\n\t\t\tgpios = <&gpio0 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\t3g {\n\t\t\tlabel = \"blue:3g\";\n\t\t\tgpios = <&gpio0 7 GPIO_ACTIVE_LOW>;\n\t\t\ttrigger-sources = <&otg_port1>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 12 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\trfkill {\n\t\t\tlabel = \"wlanswitch\";\n\t\t\tgpios = <&gpio0 13 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RFKILL>;\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"spi\", \"i2c\", \"jtag\", \"rgmii\", \"mdio\", \"uartf\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&esw {\n\tmediatek,portmap = <0x2f>;\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&otg {\n\tstatus = \"okay\";\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt3050_edimax_3g-6200nl.dts",
    "content": "#include \"rt3050.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/mtd/partitions/uimage.h>\n\n/ {\n\tcompatible = \"edimax,3g-6200nl\", \"ralink,rt3050-soc\";\n\tmodel = \"Edimax 3g-6200nl\";\n\n\taliases {\n\t\tled-boot = &led_internet;\n\t\tled-failsafe = &led_internet;\n\t\tled-running = &led_internet;\n\t\tled-upgrade = &led_internet;\n\t};\n\n\tflash@1f000000 {\n\t\tcompatible = \"cfi-flash\";\n\t\treg = <0x1f000000 0x800000>;\n\t\tbank-width = <2>;\n\t\tdevice-width = <2>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@3e0000 {\n\t\t\t\tlabel = \"cimage\";\n\t\t\t\treg = <0x3e0000 0x20000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"openwrt,uimage\", \"denx,uimage\";\n\t\t\t\topenwrt,offset = <FW_EDIMAX_OFFSET>;\n\t\t\t\topenwrt,partition-magic = <FW_MAGIC_EDIMAX>;\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x390000>;\n\t\t\t};\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_internet: internet {\n\t\t\tlabel = \"green:internet\";\n\t\t\tgpios = <&gpio0 9 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan {\n\t\t\tlabel = \"green:wlan\";\n\t\t\tgpios = <&gpio0 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 12 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"spi\", \"i2c\", \"jtag\", \"rgmii\", \"mdio\", \"uartf\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&esw {\n\tmediatek,portdisable = <0x37>;\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&otg {\n\tstatus = \"okay\";\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt3050_huawei_d105.dts",
    "content": "#include \"rt3050.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"huawei,d105\", \"ralink,rt3050-soc\";\n\tmodel = \"Huawei D105\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tflash@1f000000 {\n\t\tcompatible = \"cfi-flash\";\n\t\treg = <0x1f000000 0x800000>;\n\t\tbank-width = <2>;\n\t\tdevice-width = <2>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x3b0000>;\n\t\t\t};\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"red:power\";\n\t\t\tgpios = <&gpio0 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tusb {\n\t\t\tlabel = \"green:usb\";\n\t\t\tgpios = <&gpio0 13 GPIO_ACTIVE_LOW>;\n\t\t\ttrigger-sources = <&otg_port1>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 10 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"spi\", \"i2c\", \"jtag\", \"rgmii\", \"mdio\", \"uartf\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&esw {\n\tmediatek,portmap = <0x2f>;\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&otg {\n\tstatus = \"okay\";\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt3050_jcg_jhr-n805r.dts",
    "content": "#include \"rt3050.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"jcg,jhr-n805r\", \"ralink,rt3050-soc\";\n\tmodel = \"JCG JHR-N805R\";\n\n\taliases {\n\t\tled-boot = &led_system;\n\t\tled-failsafe = &led_system;\n\t\tled-running = &led_system;\n\t\tled-upgrade = &led_system;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_system: system {\n\t\t\tlabel = \"blue:system\";\n\t\t\tgpios = <&gpio0 9 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 10 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"jtag\", \"rgmii\", \"mdio\", \"uartf\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x3b0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_2e>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&esw {\n\tmediatek,portmap = <0x3e>;\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_2e: macaddr@2e {\n\t\treg = <0x2e 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt3050_netcore_nw718.dts",
    "content": "#include \"rt3050.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"netcore,nw718\", \"ralink,rt3050-soc\";\n\tmodel = \"Netcore NW718\";\n\n\taliases {\n\t\tled-boot = &led_cpu;\n\t\tled-failsafe = &led_cpu;\n\t\tled-running = &led_cpu;\n\t\tled-upgrade = &led_cpu;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_cpu: cpu {\n\t\t\tlabel = \"amber:cpu\";\n\t\t\tgpios = <&gpio0 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tusb {\n\t\t\tlabel = \"amber:usb\";\n\t\t\tgpios = <&gpio0 8 GPIO_ACTIVE_LOW>;\n\t\t\ttrigger-sources = <&otg_port1>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"amber:wps\";\n\t\t\tgpios = <&gpio0 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 10 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio0 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"config\";\n\t\t\t\treg = <0x30000 0x20000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@50000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x50000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@60000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x60000 0x3a0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"jtag\", \"rgmii\", \"mdio\", \"uartf\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&esw {\n\tmediatek,portmap = <0x2f>;\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&otg {\n\tstatus = \"okay\";\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt3050_sparklan_wcr-150gn.dts",
    "content": "#include \"rt3050.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"sparklan,wcr-150gn\", \"ralink,rt3050-soc\";\n\tmodel = \"Sparklan WCR-150GN\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tflash@1f000000 {\n\t\tcompatible = \"cfi-flash\";\n\t\treg = <0x1f000000 0x800000>;\n\t\tbank-width = <2>;\n\t\tdevice-width = <2>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x3b0000>;\n\t\t\t};\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tuser {\n\t\t\tlabel = \"amber:user\";\n\t\t\tgpios = <&gpio0 12 GPIO_ACTIVE_LOW>;\n\t\t\ttrigger-sources = <&otg_port1>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\n\t\tled_power: power {\n\t\t\tlabel = \"amber:power\";\n\t\t\tgpios = <&gpio0 8 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <20>;\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio0 10 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"spi\", \"i2c\", \"jtag\", \"rgmii\", \"mdio\", \"uartf\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&esw {\n\tmediatek,portmap = <0x2f>;\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&otg {\n\tstatus = \"okay\";\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt3050_teltonika_rut5xx.dts",
    "content": "#include \"rt3050.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"teltonika,rut5xx\", \"ralink,rt3050-soc\";\n\tmodel = \"Teltonika RUT5XX\";\n\n\taliases {\n\t\tled-boot = &led_status;\n\t\tled-failsafe = &led_status;\n\t\tled-running = &led_status;\n\t\tled-upgrade = &led_status;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_status: status {\n\t\t\tlabel = \"green:status\";\n\t\t\tgpios = <&gpio0 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 10 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\twatchdog {\n\t\tcompatible = \"linux,wdt-gpio\";\n\t\tgpios = <&gpio0 11 GPIO_ACTIVE_LOW>;\n\t\thw_algo = \"toggle\";\n\t\t/* hw_margin_ms is actually 280s but driver limits it to 60s */\n\t\thw_margin_ms = <60000>;\n\t\talways-running;\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0xfb0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"jtag\", \"rgmii\", \"mdio\", \"uartf\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_28>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&esw {\n\tmediatek,portmap = <0x3e>;\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&otg {\n\tstatus = \"okay\";\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_28: macaddr@28 {\n\t\treg = <0x28 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt3050_tenda_w150m.dts",
    "content": "#include \"rt3050.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"tenda,w150m\", \"ralink,rt3050-soc\";\n\tmodel = \"Tenda W150M\";\n\n\taliases {\n\t\tled-boot = &led_ap;\n\t\tled-failsafe = &led_ap;\n\t\tled-running = &led_ap;\n\t\tled-upgrade = &led_ap;\n\t};\n\n\tflash@1f000000 {\n\t\tcompatible = \"cfi-flash\";\n\t\treg = <0x1f000000 0x800000>;\n\t\tbank-width = <2>;\n\t\tdevice-width = <2>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x3b0000>;\n\t\t\t};\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\t3grouter {\n\t\t\tlabel = \"blue:3grouter\";\n\t\t\tgpios = <&gpio0 11 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_ap: ap {\n\t\t\tlabel = \"blue:ap\";\n\t\t\tgpios = <&gpio0 12 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twisprouter {\n\t\t\tlabel = \"blue:wisprouter\";\n\t\t\tgpios = <&gpio0 9 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twirelessrouter {\n\t\t\tlabel = \"blue:wirelessrouter\";\n\t\t\tgpios = <&gpio0 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\t3g {\n\t\t\tlabel = \"blue:3g\";\n\t\t\tgpios = <&gpio0 7 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twpsreset {\n\t\t\tlabel = \"blue:wpsreset\";\n\t\t\tgpios = <&gpio0 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\tmode {\n\t\t\tlabel = \"mode\";\n\t\t\tgpios = <&gpio0 10 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_0>;\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"spi\", \"i2c\", \"jtag\", \"rgmii\", \"mdio\", \"uartf\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&esw {\n\tmediatek,portmap = <0x2f>;\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt3050_trendnet_tew-638apb-v2.dts",
    "content": "#include \"rt3050.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"trendnet,tew-638apb-v2\", \"ralink,rt3050-soc\";\n\tmodel = \"TRENDnet TEW-638APB v2\";\n\n\taliases {\n\t\tled-boot = &led_wps_green;\n\t\tled-failsafe = &led_wps_green;\n\t\tled-running = &led_wps_green;\n\t\tled-upgrade = &led_wps_green;\n\t};\n\n\tflash@1f000000 {\n\t\tcompatible = \"cfi-flash\";\n\t\treg = <0x1f000000 0x400000>;\n\t\tbank-width = <2>;\n\t\tdevice-width = <2>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x3b0000>;\n\t\t\t};\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 10 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio0 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twps {\n\t\t\tlabel = \"orange:wps\";\n\t\t\tgpios = <&gpio0 11 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_wps_green: wps2 {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&gpio0 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"uartf\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&esw {\n\tmediatek,portmap = <0x2f>;\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt3052_accton_wr6202.dts",
    "content": "#include \"rt3050.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"accton,wr6202\", \"ralink,rt3052-soc\";\n\tmodel = \"Accton WR6202\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200\";\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twps {\n\t\t\tlabel = \"blue:wps\";\n\t\t\tgpios = <&gpio0 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\t3g {\n\t\t\tlabel = \"blue:3g\";\n\t\t\tgpios = <&gpio0 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 10 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio0 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n\n\tflash@1f000000 {\n\t\tcompatible = \"cfi-flash\";\n\t\treg = <0x1f000000 0x800000>;\n\t\tbank-width = <2>;\n\t\tdevice-width = <2>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x7b0000>;\n\t\t\t};\n\t\t};\n\t};\n\n\tgpio_export {\n\t\tcompatible = \"gpio-export\";\n\t\t#size-cells = <0>;\n\n\t\tusb {\n\t\t\tgpio-export,name = \"usb\";\n\t\t\tgpio-export,output = <0>;\n\t\t\tgpios = <&gpio0 11 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"spi\", \"i2c\", \"jtag\", \"rgmii\", \"mdio\", \"uartf\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_28>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&esw {\n\tmediatek,portmap = <0x3e>;\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&otg {\n\tstatus = \"okay\";\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_28: macaddr@28 {\n\t\treg = <0x28 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt3052_alfa-network_w502u.dts",
    "content": "#include \"rt3050.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"alfa-network,w502u\", \"ralink,rt3052-soc\";\n\tmodel = \"ALFA Network W502U\";\n\n\taliases {\n\t\tled-boot = &led_wps;\n\t\tled-failsafe = &led_wps;\n\t\tled-running = &led_wps;\n\t\tled-upgrade = &led_wps;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200\";\n\t};\n\n\tflash@1f000000 {\n\t\tcompatible = \"cfi-flash\";\n\t\treg = <0x1f000000 0x800000>;\n\t\tbank-width = <2>;\n\t\tdevice-width = <2>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x7b0000>;\n\t\t\t};\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tusb {\n\t\t\tlabel = \"blue:usb\";\n\t\t\tgpios = <&gpio0 13 GPIO_ACTIVE_LOW>;\n\t\t\ttrigger-sources = <&otg_port1>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\n\t\tled_wps: wps {\n\t\t\tlabel = \"blue:wps\";\n\t\t\tgpios = <&gpio0 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 10 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio0 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"spi\", \"i2c\", \"jtag\", \"rgmii\", \"mdio\", \"uartf\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_28>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&esw {\n\tmediatek,portmap = <0x3e>;\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&otg {\n\tstatus = \"okay\";\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_28: macaddr@28 {\n\t\treg = <0x28 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt3052_argus_atp-52b.dts",
    "content": "#include \"rt3050.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"argus,atp-52b\", \"ralink,rt3052-soc\";\n\tmodel = \"Argus ATP-52B\";\n\n\taliases {\n\t\tled-boot = &led_run;\n\t\tled-failsafe = &led_run;\n\t\tled-running = &led_run;\n\t\tled-upgrade = &led_run;\n\t};\n\n\tflash@1f000000 {\n\t\tcompatible = \"cfi-flash\";\n\t\treg = <0x1f000000 0x800000>;\n\t\tbank-width = <2>;\n\t\tdevice-width = <2>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"bootloader\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"config\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x7a0000>;\n\t\t\t};\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_run: run {\n\t\t\tlabel = \"green:run\";\n\t\t\tgpios = <&gpio0 9 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tnet {\n\t\t\tlabel = \"amber:net\";\n\t\t\tgpios = <&gpio0 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <20>;\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio0 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 10 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"jtag\", \"rgmii\", \"mdio\", \"uartf\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&esw {\n\tmediatek,portmap = <0x3e>;\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&otg {\n\tstatus = \"okay\";\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt3052_asiarf_awapn2403.dts",
    "content": "#include \"rt3050.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"asiarf,awapn2403\", \"ralink,rt3052-soc\";\n\tmodel = \"AsiaRF AWAPN2403\";\n\n\taliases {\n\t\tled-boot = &led_wps;\n\t\tled-failsafe = &led_wps;\n\t\tled-running = &led_wps;\n\t\tled-upgrade = &led_wps;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_wps: wps {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&gpio0 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x3b0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"jtag\", \"rgmii\", \"mdio\", \"uartf\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&esw {\n\tmediatek,portmap = <0x3e>;\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt3052_asus_rt-n13u.dts",
    "content": "#include \"rt3050.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"asus,rt-n13u\", \"ralink,rt3052-soc\";\n\tmodel = \"Asus RT-N13U\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tflash@1f000000 {\n\t\tcompatible = \"cfi-flash\";\n\t\treg = <0x1f000000 0x800000>;\n\t\tbank-width = <2>;\n\t\tdevice-width = <2>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x7b0000>;\n\t\t\t};\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"blue:power\";\n\t\t\tgpios = <&gpio0 7 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twifi {\n\t\t\tlabel = \"blue:wifi\";\n\t\t\tgpios = <&gpio0 8 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <10>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 10 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio0 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"spi\", \"i2c\", \"jtag\", \"rgmii\", \"mdio\", \"uartf\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_28>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&esw {\n\tmediatek,portmap = <0x2f>;\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&otg {\n\tstatus = \"okay\";\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_28: macaddr@28 {\n\t\treg = <0x28 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt3052_aximcom_mr-102n.dts",
    "content": "#include \"rt3050.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"aximcom,mr-102n\", \"ralink,rt3052-soc\";\n\tmodel = \"AXIMCom MR-102N\";\n\n\taliases {\n\t\tled-boot = &led_status;\n\t\tled-failsafe = &led_status;\n\t\tled-running = &led_status;\n\t\tled-upgrade = &led_status;\n\t};\n\n\tflash@1f000000 {\n\t\tcompatible = \"cfi-flash\";\n\t\treg = <0x1f000000 0x800000>;\n\t\tbank-width = <2>;\n\t\tdevice-width = <2>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x790000>;\n\t\t\t};\n\n\t\t\tpartition@7e0000 {\n\t\t\t\tlabel = \"nvram\";\n\t\t\t\treg = <0x7e0000 0x10000>;\n\t\t\t};\n\n\t\t\tpartition@7f0000 {\n\t\t\t\tlabel = \"nvram_backup\";\n\t\t\t\treg = <0x7f0000 0x10000>;\n\t\t\t};\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tusb {\n\t\t\tlabel = \"green:usb\";\n\t\t\tgpios = <&gpio0 8 GPIO_ACTIVE_LOW>;\n\t\t\ttrigger-sources = <&otg_port1>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\n\t\tled_status: status {\n\t\t\tlabel = \"amber:status\";\n\t\t\tgpios = <&gpio0 9 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan {\n\t\t\tlabel = \"green:wlan\";\n\t\t\tgpios = <&gpio0 11 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 13 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio0 18 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"jtag\", \"rgmii\", \"mdio\", \"uartf\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&esw {\n\tstatus = \"okay\";\n\tmediatek,portmap = <0x2f>;\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&otg {\n\tstatus = \"okay\";\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt3052_aztech_hw550-3g.dts",
    "content": "#include \"rt3050.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"aztech,hw550-3g\", \"ralink,rt3052-soc\";\n\tmodel = \"Aztech HW550-3G\";\n\n\taliases {\n\t\tled-boot = &led_status;\n\t\tled-failsafe = &led_status;\n\t\tled-running = &led_status;\n\t\tled-upgrade = &led_status;\n\t};\n\n\tflash@1f000000 {\n\t\tcompatible = \"cfi-flash\";\n\t\treg = <0x1f000000 0x800000>;\n\t\tbank-width = <2>;\n\t\tdevice-width = <2>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x7b0000>;\n\t\t\t};\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tusb {\n\t\t\tlabel = \"green:usb\";\n\t\t\tgpios = <&gpio0 8 GPIO_ACTIVE_LOW>;\n\t\t\ttrigger-sources = <&otg_port1>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\n\t\t3g {\n\t\t\tlabel = \"green:3g\";\n\t\t\tgpios = <&gpio0 11 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_status: status {\n\t\t\tlabel = \"green:status\";\n\t\t\tgpios = <&gpio0 12 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&gpio0 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 10 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\tconnect {\n\t\t\tlabel = \"connect\";\n\t\t\tgpios = <&gpio0 7 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_CONNECT>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio0 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"spi\", \"i2c\", \"jtag\", \"rgmii\", \"mdio\", \"uartf\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_28>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&esw {\n\tmediatek,portmap = <0x3e>;\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&otg {\n\tstatus = \"okay\";\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_28: macaddr@28 {\n\t\treg = <0x28 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt3052_belkin_f5d8235-v2.dts",
    "content": "#include \"rt3050.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"belkin,f5d8235-v2\", \"ralink,rt3052-soc\";\n\tmodel = \"Belkin F5D8235 v2\";\n\n\taliases {\n\t\tled-boot = &led_router;\n\t\tled-failsafe = &led_router;\n\t\tled-running = &led_router;\n\t\tled-upgrade = &led_router;\n\t};\n\n\tflash@1f000000 {\n\t\tcompatible = \"cfi-flash\";\n\t\treg = <0x1f000000 0x800000>;\n\t\tbank-width = <2>;\n\t\tdevice-width = <2>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tuboot: partition@0 {\n\t\t\t\tlabel = \"uboot\";\n\t\t\t\treg = <0x0 0x50000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x790000>;\n\t\t\t};\n\n\t\t\tpartition@7e0000 {\n\t\t\t\tlabel = \"nvram\";\n\t\t\t\treg = <0x7e0000 0x10000>;\n\t\t\t};\n\n\t\t\tfactory: partition@7f0000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x7f0000 0x10000>;\n\t\t\t};\n\t\t};\n\t};\n\n\trtl8366rb {\n\t\tcompatible = \"realtek,rtl8366rb\";\n\t\tgpio-sda = <&gpio0 1 GPIO_ACTIVE_HIGH>;\n\t\tgpio-sck = <&gpio0 2 GPIO_ACTIVE_HIGH>;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tinternet {\n\t\t\tlabel = \"blue:internet\";\n\t\t\tgpios = <&gpio0 5 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tinternet2 {\n\t\t\tlabel = \"amber:internet\";\n\t\t\tgpios = <&gpio0 6 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tmodem {\n\t\t\tlabel = \"blue:modem\";\n\t\t\tgpios = <&gpio0 11 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tmodem2 {\n\t\t\tlabel = \"amber:modem\";\n\t\t\tgpios = <&gpio0 8 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_router: router {\n\t\t\tlabel = \"blue:router\";\n\t\t\tgpios = <&gpio0 9 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tstorage {\n\t\t\tlabel = \"blue:storage\";\n\t\t\tgpios = <&gpio0 23 GPIO_ACTIVE_LOW>;\n\t\t\ttrigger-sources = <&otg_port1>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\n\t\tstorage2 {\n\t\t\tlabel = \"amber:storage\";\n\t\t\tgpios = <&gpio0 22 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tsecurity {\n\t\t\tlabel = \"blue:security\";\n\t\t\tgpios = <&gpio0 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tsecurity2 {\n\t\t\tlabel = \"amber:security\";\n\t\t\tgpios = <&gpio0 12 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"spi\", \"i2c\", \"jtag\", \"mdio\", \"uartf\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_uboot_40004>;\n\tnvmem-cell-names = \"mac-address\";\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&rgmii_pins>;\n};\n\n&esw {\n\tralink,rgmii = <1>;\n\tmediatek,portmap = <0x3f>;\n\tralink,fct2 = <0x0002500c>;\n\t/*\n\t * ext phy base addr 31, rx/tx clock skew 0,\n\t * turbo mii off, rgmi 3.3v off, port 5 polling off\n\t * port5: enabled, gige, full-duplex, rx/tx-flow-control\n\t * port6: enabled, gige, full-duplex, rx/tx-flow-control\n\t*/\n\tralink,fpa2 = <0x1f003fff>;\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&uboot 0x40000>;\n};\n\n&otg {\n\tstatus = \"okay\";\n};\n\n&uboot {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_uboot_40004: macaddr@40004 {\n\t\treg = <0x40004 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt3052_buffalo_whr-g300n.dts",
    "content": "#include \"rt3050.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"buffalo,whr-g300n\", \"ralink,rt3052-soc\";\n\tmodel = \"Buffalo WHR-G300N\";\n\n\taliases {\n\t\tled-boot = &led_diag;\n\t\tled-failsafe = &led_diag;\n\t\tled-upgrade = &led_diag;\n\t};\n\n\tflash@1f000000 {\n\t\tcompatible = \"cfi-flash\";\n\t\treg = <0x1f000000 0x800000>;\n\t\tbank-width = <2>;\n\t\tdevice-width = <2>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x3a0000>;\n\t\t\t};\n\n\t\t\tpartition@3f0000 {\n\t\t\t\tlabel = \"user\";\n\t\t\t\treg = <0x3f0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_diag: diag {\n\t\t\tlabel = \"red:diag\";\n\t\t\tgpios = <&gpio0 7 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\trouter {\n\t\t\tlabel = \"green:router\";\n\t\t\tgpios = <&gpio0 9 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tsecurity {\n\t\t\tlabel = \"amber:security\";\n\t\t\tgpios = <&gpio0 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 10 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\taoss {\n\t\t\tlabel = \"aoss\";\n\t\t\tgpios = <&gpio0 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\n\t\trouter-off {\n\t\t\tlabel = \"router-off\";\n\t\t\tgpios = <&gpio0 11 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_2>;\n\t\t};\n\n\t\trouter-on {\n\t\t\tlabel = \"router-on\";\n\t\t\tgpios = <&gpio0 8 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_3>;\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"spi\", \"i2c\", \"jtag\", \"rgmii\", \"mdio\", \"uartf\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&esw {\n\tmediatek,portmap = <0x2f>;\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt3052_dlink_dap-1350.dts",
    "content": "#include \"rt3050.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"dlink,dap-1350\", \"ralink,rt3052-soc\";\n\tmodel = \"D-Link DAP-1350\";\n\n\taliases {\n\t\tled-boot = &led_power_blue;\n\t\tled-failsafe = &led_power_blue;\n\t\tled-running = &led_power_blue;\n\t\tled-upgrade = &led_power_blue;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200\";\n\t};\n\n\tflash@1f000000 {\n\t\tcompatible = \"cfi-flash\";\n\t\treg = <0x1f000000 0x800000>;\n\t\tbank-width = <2>;\n\t\tdevice-width = <2>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tdevdata: partition@30000 {\n\t\t\t\tlabel = \"devdata\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"devconf\";\n\t\t\t\treg = <0x40000 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@70000 {\n\t\t\t\tlabel = \"devlang\";\n\t\t\t\treg = <0x70000 0x40000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@b0000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0xb0000 0x750000>;\n\t\t\t};\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power_blue: power {\n\t\t\tlabel = \"blue:power\";\n\t\t\tgpios = <&gpio0 8 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tpower2 {\n\t\t\tlabel = \"red:power\";\n\t\t\tgpios = <&gpio0 9 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"blue:wps\";\n\t\t\tgpios = <&gpio0 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 10 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio0 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\n\t\trt {\n\t\t\tlabel = \"rt\";\n\t\t\tgpios = <&gpio0 11 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_0>;\n\t\t};\n\n\t\tap {\n\t\t\tlabel = \"ap\";\n\t\t\tgpios = <&gpio0 7 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_1>;\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"spi\", \"i2c\", \"jtag\", \"rgmii\", \"mdio\", \"uartf\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_devdata_2e>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&esw {\n\tmediatek,portmap = <0x2f>;\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&devdata 0x0>;\n};\n\n&otg {\n\tstatus = \"okay\";\n};\n\n&devdata {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_devdata_2e: macaddr@2e {\n\t\treg = <0x2e 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt3052_engenius_esr-9753.dts",
    "content": "#include \"rt3050.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"engenius,esr-9753\", \"ralink,rt3052-soc\";\n\tmodel = \"Senao / EnGenius ESR-9753\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tflash@1f000000 {\n\t\tcompatible = \"cfi-flash\";\n\t\treg = <0x1f000000 0x800000>;\n\t\tbank-width = <2>;\n\t\tdevice-width = <2>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x3b0000>;\n\t\t\t};\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"orange:power\";\n\t\t\tgpios = <&gpio0 8 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"orange:wps\";\n\t\t\tgpios = <&gpio0 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 10 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio0 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"spi\", \"i2c\", \"jtag\", \"rgmii\", \"mdio\", \"uartf\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&esw {\n\tmediatek,portmap = <0x3e>;\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt3052_fon_fonera-20n.dts",
    "content": "#include \"rt3050.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"fon,fonera-20n\", \"ralink,rt3052-soc\";\n\tmodel = \"La Fonera 2.0N\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tflash@1f000000 {\n\t\tcompatible = \"cfi-flash\";\n\t\treg = <0x1f000000 0x800000>;\n\t\tbank-width = <2>;\n\t\tdevice-width = <2>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x7b0000>;\n\t\t\t};\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twifi {\n\t\t\tlabel = \"orange:wifi\";\n\t\t\tgpios = <&gpio0 7 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_power: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio0 9 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tusb {\n\t\t\tlabel = \"orange:usb\";\n\t\t\tgpios = <&gpio0 14 GPIO_ACTIVE_LOW>;\n\t\t\ttrigger-sources = <&otg_port1>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 12 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\tswitch {\n\t\t\tlabel = \"switch\";\n\t\t\tgpios = <&gpio0 13 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RFKILL>;\n\t\t\tlinux,input-type = <EV_SW>;\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"spi\", \"jtag\", \"mdio\", \"rgmii\", \"uartf\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_28>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&esw {\n\t#address-cells = <1>;\n\t#size-cells = <0>;\n\n\tmediatek,portmap = <0x2f>;\n\n\tport@0 {\n\t\tcompatible = \"swconfig,port\";\n\t\treg = <0>;\n\t\tswconfig,segment = \"lan\";\n\t\tswconfig,portmap = <0 4>;\n\t};\n\n\tport@1 {\n\t\tcompatible = \"swconfig,port\";\n\t\treg = <1>;\n\t\tswconfig,segment = \"lan\";\n\t\tswconfig,portmap = <1 3>;\n\t};\n\n\tport@2 {\n\t\tcompatible = \"swconfig,port\";\n\t\treg = <2>;\n\t\tswconfig,segment = \"lan\";\n\t\tswconfig,portmap = <2 2>;\n\t};\n\n\tport@3 {\n\t\tcompatible = \"swconfig,port\";\n\t\treg = <3>;\n\t\tswconfig,segment = \"lan\";\n\t\tswconfig,portmap = <3 1>;\n\t};\n\n\tport@4 {\n\t\tcompatible = \"swconfig,port\";\n\t\treg = <4>;\n\t\tswconfig,segment = \"wan\";\n\t\tswconfig,portmap = <4 0>;\n\t};\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&otg {\n\tstatus = \"okay\";\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_28: macaddr@28 {\n\t\treg = <0x28 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt3052_hauppauge_broadway.dts",
    "content": "#include \"rt3050.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"hauppauge,broadway\", \"ralink,rt3052-soc\";\n\tmodel = \"Hauppauge Broadway\";\n\n\tflash@1f000000 {\n\t\tcompatible = \"cfi-flash\";\n\t\treg = <0x1f000000 0x800000>;\n\t\tbank-width = <2>;\n\t\tdevice-width = <2>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"bootloader\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"config\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x790000>;\n\t\t\t};\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tdiskmounted {\n\t\t\tlabel = \"red:diskmounted\";\n\t\t\tgpios = <&gpio0 9 GPIO_ACTIVE_LOW>;\n\t\t\ttrigger-sources = <&otg_port1>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\n\t\twps_active {\n\t\t\tlabel = \"red:wps_active\";\n\t\t\tgpios = <&gpio0 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <20>;\n\n\t\tfactory {\n\t\t\tlabel = \"Factory Reset button\";\n\t\t\tgpios = <&gpio0 13 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"spi\", \"i2c\", \"jtag\", \"rgmii\", \"mdio\", \"uartf\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&esw {\n\tmediatek,portmap = <0x3e>;\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&otg {\n\tstatus = \"okay\";\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt3052_huawei_hg255d.dts",
    "content": "#include \"rt3050.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"huawei,hg255d\", \"ralink,rt3052-soc\";\n\tmodel = \"HuaWei HG255D\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tflash@1f000000 {\n\t\tcompatible = \"cfi-flash\";\n\t\treg = <0x1f000000 0x1000000>;\n\t\tbank-width = <2>;\n\t\tdevice-width = <2>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x40000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x40000 0x20000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@60000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x60000 0x20000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@80000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x80000 0xf60000>;\n\t\t\t};\n\n\t\t\tpartition@fa0000 {\n\t\t\t\tlabel = \"factory-orig\";\n\t\t\t\treg = <0xfa0000 0x20000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio0 8 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tinternet {\n\t\t\tlabel = \"green:internet\";\n\t\t\tgpios = <&gpio0 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twifi {\n\t\t\tlabel = \"green:wlan\";\n\t\t\tgpios = <&gpio0 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tusb {\n\t\t\tlabel = \"green:usb\";\n\t\t\tgpios = <&gpio0 9 GPIO_ACTIVE_LOW>;\n\t\t\ttrigger-sources = <&otg_port1>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&gpio0 12 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tvoice {\n\t\t\tlabel = \"green:voice\";\n\t\t\tgpios = <&gpio0 5 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <10>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 4 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio0 10 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\n\t\trfkill {\n\t\t\tlabel = \"rfkill\";\n\t\t\tgpios = <&gpio0 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RFKILL>;\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"spi\", \"i2c\", \"jtag\", \"rgmii\", \"mdio\", \"uartf\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_28>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&esw {\n\tmediatek,portmap = <0x2f>;\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&otg {\n\tstatus = \"okay\";\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_28: macaddr@28 {\n\t\treg = <0x28 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt3052_jcg_jhr-n825r.dts",
    "content": "#include \"rt3050.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"jcg,jhr-n825r\", \"ralink,rt3052-soc\";\n\tmodel = \"JCG JHR-N825R\";\n\n\taliases {\n\t\tled-boot = &led_system;\n\t\tled-failsafe = &led_system;\n\t\tled-running = &led_system;\n\t\tled-upgrade = &led_system;\n\t};\n\n\tflash@1f000000 {\n\t\tcompatible = \"cfi-flash\";\n\t\treg = <0x1f000000 0x800000>;\n\t\tbank-width = <2>;\n\t\tdevice-width = <2>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x3b0000>;\n\t\t\t};\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\t\tled_system: system {\n\t\t\tlabel = \"red:power\";\n\t\t\tgpios = <&gpio0 9 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <20>;\n\t\treset_wps {\n\t\t\tlabel = \"reset_wps\";\n\t\t\tgpios = <&gpio0 10 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"spi\", \"i2c\", \"jtag\", \"rgmii\", \"mdio\", \"uartf\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_2e>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&esw {\n\tmediatek,portmap = <0x3e>;\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_2e: macaddr@2e {\n\t\treg = <0x2e 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt3052_jcg_jhr-n926r.dts",
    "content": "#include \"rt3050.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"jcg,jhr-n926r\", \"ralink,rt3052-soc\";\n\tmodel = \"JCG JHR-N926R\";\n\n\taliases {\n\t\tled-boot = &led_system;\n\t\tled-failsafe = &led_system;\n\t\tled-running = &led_system;\n\t\tled-upgrade = &led_system;\n\t};\n\n\tflash@1f000000 {\n\t\tcompatible = \"cfi-flash\";\n\t\treg = <0x1f000000 0x800000>;\n\t\tbank-width = <2>;\n\t\tdevice-width = <2>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x3b0000>;\n\t\t\t};\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twlan1 {\n\t\t\tlabel = \"red:wlan\";\n\t\t\tgpios = <&gpio0 20 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan2 {\n\t\t\tlabel = \"yellow:wlan\";\n\t\t\tgpios = <&gpio0 19 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan3 {\n\t\t\tlabel = \"green:wlan\";\n\t\t\tgpios = <&gpio0 17 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_system: system {\n\t\t\tlabel = \"blue:system\";\n\t\t\tgpios = <&gpio0 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tgpio_export {\n\t\tcompatible = \"gpio-export\";\n\t\t#size-cells = <0>;\n\n\t\tdisplay_data {\n\t\t\tgpio-export,name = \"display_data\";\n\t\t\tgpio-export,output = <1>;\n\t\t\tgpios = <&gpio0 7 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tdisplay_clock {\n\t\t\tgpio-export,name = \"display_clock\";\n\t\t\tgpio-export,output = <1>;\n\t\t\tgpios = <&gpio0 8 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tdisplay_blank {\n\t\t\tgpio-export,name = \"display_blank\";\n\t\t\tgpio-export,output = <1>;\n\t\t\tgpios = <&gpio0 11 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <20>;\n\n\t\treset_wps {\n\t\t\tlabel = \"reset_wps\";\n\t\t\tgpios = <&gpio0 10 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twlan {\n\t\t\tlabel = \"wlan\";\n\t\t\tgpios = <&gpio0 1 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_0>;\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"spi\", \"i2c\", \"jtag\", \"rgmii\", \"mdio\", \"uartf\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_2e>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&esw {\n\tmediatek,portmap = <0x3e>;\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_2e: macaddr@2e {\n\t\treg = <0x2e 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt3052_mofinetwork_mofi3500-3gn.dts",
    "content": "#include \"rt3050.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"mofinetwork,mofi3500-3gn\", \"ralink,rt3052-soc\";\n\tmodel = \"MoFi Network MOFI3500-3GN\";\n\n\taliases {\n\t\tled-boot = &led_status;\n\t\tled-failsafe = &led_status;\n\t\tled-running = &led_status;\n\t\tled-upgrade = &led_status;\n\t};\n\n\tflash@1f000000 {\n\t\tcompatible = \"cfi-flash\";\n\t\treg = <0x1f000000 0x800000>;\n\t\tbank-width = <2>;\n\t\tdevice-width = <2>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x7b0000>;\n\t\t\t};\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tusb {\n\t\t\tlabel = \"green:usb\";\n\t\t\tgpios = <&gpio0 8 GPIO_ACTIVE_LOW>;\n\t\t\ttrigger-sources = <&otg_port1>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\n\t\t3g {\n\t\t\tlabel = \"green:3g\";\n\t\t\tgpios = <&gpio0 11 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_status: status {\n\t\t\tlabel = \"green:status\";\n\t\t\tgpios = <&gpio0 12 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&gpio0 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 10 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\tconnect {\n\t\t\tlabel = \"connect\";\n\t\t\tgpios = <&gpio0 7 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_CONNECT>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio0 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"spi\", \"i2c\", \"jtag\", \"rgmii\", \"mdio\", \"uartf\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&esw {\n\tmediatek,portmap = <0x2f>;\n};\n\n&wmac {\n\tstatus = \"okay\";\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&otg {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt3052_netgear_wnce2001.dts",
    "content": "#include \"rt3050.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"netgear,wnce2001\", \"ralink,rt3052-soc\";\n\tmodel = \"Netgear WNCE2001\";\n\n\taliases {\n\t\tled-boot = &led_power_green;\n\t\tled-failsafe = &led_power_green;\n\t\tled-running = &led_power_green;\n\t\tled-upgrade = &led_power_green;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200\";\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power_green: power-green {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio0 8 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tpower-red {\n\t\t\tlabel = \"red:power\";\n\t\t\tgpios = <&gpio0 9 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan-green {\n\t\t\tlabel = \"green:wlan\";\n\t\t\tgpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\twlan-red {\n\t\t\tlabel = \"red:wlan\";\n\t\t\tgpios = <&gpio0 13 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 10 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio0 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\n\t\trt {\n\t\t\tlabel = \"rt\";\n\t\t\tgpios = <&gpio0 11 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_0>;\n\t\t};\n\n\t\tap {\n\t\t\tlabel = \"ap\";\n\t\t\tgpios = <&gpio0 7 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_1>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@30000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"config\";\n\t\t\t\treg = <0x40000 0x20000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@60000 {\n\t\t\t\tlabel = \"language\";\n\t\t\t\treg = <0x60000 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@90000 {\n\t\t\t\tlabel = \"pot\";\n\t\t\t\treg = <0x90000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@a0000 {\n\t\t\t\tlabel = \"checksum\";\n\t\t\t\treg = <0xa0000 0x10000>;\n\t\t\t};\n\n\t\t\tpartition@b0000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0xb0000 0x350000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"jtag\", \"rgmii\", \"mdio\", \"uartf\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_28>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_28: macaddr@28 {\n\t\treg = <0x28 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt3052_nexaira_bc2.dts",
    "content": "#include \"rt3050.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"nexaira,bc2\", \"ralink,rt3052-soc\";\n\tmodel = \"NexAira BC2\";\n\n\tflash@1f000000 {\n\t\tcompatible = \"cfi-flash\";\n\t\treg = <0x1f000000 0x800000>;\n\t\tbank-width = <2>;\n\t\tdevice-width = <2>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x7b0000>;\n\t\t\t};\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tusb {\n\t\t\tlabel = \"blue:usb\";\n\t\t\tgpios = <&gpio0 20 GPIO_ACTIVE_LOW>;\n\t\t\ttrigger-sources = <&otg_port1>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 17 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"spi\", \"i2c\", \"jtag\", \"rgmii\", \"mdio\", \"uartf\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&esw {\n\tmediatek,portmap = <0x2f>;\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&otg {\n\tstatus = \"okay\";\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt3052_omnima_miniembwifi.dts",
    "content": "#include \"rt3050.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"omnima,miniembwifi\", \"ralink,rt3052-soc\";\n\tmodel = \"Omnima MiniEMBWiFi\";\n\n\taliases {\n\t\tled-boot = &led_status;\n\t\tled-failsafe = &led_status;\n\t\tled-running = &led_status;\n\t\tled-upgrade = &led_status;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_status: status {\n\t\t\tlabel = \"green:status\";\n\t\t\tgpios = <&gpio0 9 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan {\n\t\t\tlabel = \"green:wlan\";\n\t\t\tgpios = <&gpio0 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 12 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tflash@1f000000 {\n\t\tcompatible = \"cfi-flash\";\n\t\treg = <0x1f000000 0x800000>;\n\t\tbank-width = <2>;\n\t\tdevice-width = <2>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x7b0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"spi\", \"i2c\", \"jtag\", \"rgmii\", \"mdio\", \"uartf\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_28>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&esw {\n\tmediatek,portmap = <0x2f>;\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&otg {\n\tstatus = \"okay\";\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_28: macaddr@28 {\n\t\treg = <0x28 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt3052_petatel_psr-680w.dts",
    "content": "#include \"rt3050.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"petatel,psr-680w\", \"ralink,rt3052-soc\";\n\tmodel = \"Petatel PSR-680W Wireless 3G Router\";\n\n\taliases {\n\t\tled-boot = &led_wan;\n\t\tled-failsafe = &led_wan;\n\t\tled-running = &led_wan;\n\t\tled-upgrade = &led_wan;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200\";\n\t};\n\n\tflash@1f000000 {\n\t\tcompatible = \"cfi-flash\";\n\t\treg = <0x1f000000 0x800000>;\n\t\tbank-width = <2>;\n\t\tdevice-width = <2>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x3b0000>;\n\t\t\t};\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_wan: wan {\n\t\t\tlabel = \"red:wan\";\n\t\t\tgpios = <&gpio0 19 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"spi\", \"i2c\", \"jtag\", \"rgmii\", \"mdio\", \"uartf\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&esw {\n\tmediatek,portmap = <0x3e>;\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&otg {\n\tstatus = \"okay\";\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt3052_planex_mzk-w300nh2.dts",
    "content": "#include \"rt3050.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"planex,mzk-w300nh2\", \"ralink,rt3052-soc\";\n\tmodel = \"Planex MZK-W300NH2\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tflash@1f000000 {\n\t\tcompatible = \"cfi-flash\";\n\t\treg = <0x1f000000 0x800000>;\n\t\tbank-width = <2>;\n\t\tdevice-width = <2>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@3e0000 {\n\t\t\t\tlabel = \"cimage\";\n\t\t\t\treg = <0x3e0000 0x20000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x390000>;\n\t\t\t};\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio0 9 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan {\n\t\t\tlabel = \"amber:wlan\";\n\t\t\tgpios = <&gpio0 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"amber:wps\";\n\t\t\tgpios = <&gpio0 11 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <20>;\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio0 12 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\trt {\n\t\t\tlabel = \"rt\";\n\t\t\tgpios = <&gpio0 13 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_0>;\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"spi\", \"i2c\", \"jtag\", \"rgmii\", \"mdio\", \"uartf\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&esw {\n\tmediatek,portmap = <0x2f>;\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt3052_planex_mzk-wdpr.dts",
    "content": "#include \"rt3050.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n\n/ {\n\tcompatible = \"planex,mzk-wdpr\", \"ralink,rt3052-soc\";\n\tmodel = \"Planex MZK-WDPR\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200\";\n\t};\n\n\tflash@1f000000 {\n\t\tcompatible = \"cfi-flash\";\n\t\treg = <0x1f000000 0x800000>;\n\n\t\tbank-width = <2>;\n\t\tdevice-width = <2>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@7f0000 {\n\t\t\t\tlabel = \"Data3G\";\n\t\t\t\treg = <0x7f0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x680000>;\n\t\t\t};\n\t\t};\n\t};\n\n\tgpio-export {\n\t\tcompatible = \"gpio-export\";\n\n\t\tlcd_ctrl1 {\n\t\t\tgpio-export,name = \"lcd_ctrl1\";\n\t\t\tgpio-export,output = <0>;\n\t\t\tgpios = <&gpio0 1 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"spi\", \"i2c\", \"jtag\", \"rgmii\", \"mdio\", \"uartf\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_28>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&esw {\n\tmediatek,portmap = <0x2f>;\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&otg {\n\tstatus = \"okay\";\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_28: macaddr@28 {\n\t\treg = <0x28 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt3052_poray_ip2202.dts",
    "content": "#include \"rt3050.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"poray,ip2202\", \"ralink,rt3052-soc\";\n\tmodel = \"Poray IP2202\";\n\n\taliases {\n\t\tled-boot = &led_run;\n\t\tled-failsafe = &led_run;\n\t\tled-running = &led_run;\n\t\tled-upgrade = &led_run;\n\t};\n\n\tflash@1f000000 {\n\t\tcompatible = \"cfi-flash\";\n\t\treg = <0x1f000000 0x800000>;\n\t\tbank-width = <2>;\n\t\tdevice-width = <2>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x7b0000>;\n\t\t\t};\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_run: run {\n\t\t\tlabel = \"green:run\";\n\t\t\tgpios = <&gpio0 9 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tnet {\n\t\t\tlabel = \"amber:net\";\n\t\t\tgpios = <&gpio0 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 10 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"spi\", \"i2c\", \"jtag\", \"rgmii\", \"mdio\", \"uartf\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_28>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&esw {\n\tmediatek,portmap = <0x2f>;\n};\n\n&otg {\n\tstatus = \"okay\";\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_28: macaddr@28 {\n\t\treg = <0x28 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt3052_prolink_pwh2004.dts",
    "content": "#include \"rt3050.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"prolink,pwh2004\", \"ralink,rt3052-soc\";\n\tmodel = \"Prolink PWH2004\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tflash@1f000000 {\n\t\tcompatible = \"cfi-flash\";\n\t\treg = <0x1f000000 0x800000>;\n\t\tbank-width = <2>;\n\t\tdevice-width = <2>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x7b0000>;\n\t\t\t};\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twifi {\n\t\t\tlabel = \"red:wifi\";\n\t\t\tgpios = <&gpio0 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_power: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio0 9 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <20>;\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio0 12 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"spi\", \"i2c\", \"jtag\", \"rgmii\", \"mdio\", \"uartf\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&esw {\n\tmediatek,portmap = <0x2f>;\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt3052_ralink_v22rw-2x2.dts",
    "content": "#include \"rt3050.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"ralink,v22rw-2x2\", \"ralink,rt3052-soc\";\n\tmodel = \"Ralink AP-RT3052-V22RW-2X2\";\n\n\taliases {\n\t\tled-boot = &led_security;\n\t\tled-failsafe = &led_security;\n\t\tled-running = &led_security;\n\t\tled-upgrade = &led_security;\n\t};\n\n\tflash@1f000000 {\n\t\tcompatible = \"cfi-flash\";\n\t\treg = <0x1f000000 0x800000>;\n\t\tbank-width = <2>;\n\t\tdevice-width = <2>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x3b0000>;\n\t\t\t};\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_security: security {\n\t\t\tlabel = \"green:security\";\n\t\t\tgpios = <&gpio0 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"red:wps\";\n\t\t\tgpios = <&gpio0 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 10 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio0 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"spi\", \"i2c\", \"jtag\", \"rgmii\", \"mdio\", \"uartf\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&esw {\n\tmediatek,portmap = <0x2f>;\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&otg {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt3052_sitecom_wl-351.dts",
    "content": "#include \"rt3050.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"sitecom,wl-351\", \"ralink,rt3052-soc\";\n\tmodel = \"Sitecom WL-351 v1 002\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tflash@1f000000 {\n\t\tcompatible = \"cfi-flash\";\n\t\treg = <0x1f000000 0x800000>;\n\t\tbank-width = <2>;\n\t\tdevice-width = <2>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x3b0000>;\n\t\t\t};\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"amber:power\";\n\t\t\tgpios = <&gpio0 8 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tunpopulated {\n\t\t\tlabel = \"amber:unpopulated\";\n\t\t\tgpios = <&gpio0 12 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tunpopulated2 {\n\t\t\tlabel = \"blue:unpopulated\";\n\t\t\tgpios = <&gpio0 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 10 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio0 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n\n\trtl8366rb {\n\t\tcompatible = \"realtek,rtl8366rb\";\n\t\tgpio-sda = <&gpio0 1 GPIO_ACTIVE_HIGH>;\n\t\tgpio-sck = <&gpio0 2 GPIO_ACTIVE_HIGH>;\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"spi\", \"i2c\", \"jtag\", \"mdio\", \"uartf\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&rgmii_pins>;\n};\n\n&esw {\n\tralink,rgmii = <1>;\n\tmediatek,portmap = <0x3f>;\n\tralink,fct2 = <0x0002500c>;\n\t/*\n\t * ext phy base addr 31, rx/tx clock skew 0,\n\t * turbo mii off, rgmi 3.3v off, port 5 polling off\n\t * port5: enabled, gige, full-duplex, rx/tx-flow-control\n\t * port6: enabled, gige, full-duplex, rx/tx-flow-control\n\t*/\n\tralink,fpa2 = <0x1f003fff>;\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&otg {\n\tstatus = \"okay\";\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt3052_skyline_sl-r7205.dts",
    "content": "#include \"rt3050.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"skyline,sl-r7205\", \"ralink,rt3052-soc\";\n\tmodel = \"Skyline SL-R7205 Wireless 3G Router\";\n\n\taliases {\n\t\tled-boot = &led_wifi;\n\t\tled-failsafe = &led_wifi;\n\t\tled-running = &led_wifi;\n\t\tled-upgrade = &led_wifi;\n\t};\n\n\tflash@1f000000 {\n\t\tcompatible = \"cfi-flash\";\n\t\treg = <0x1f000000 0x800000>;\n\t\tbank-width = <2>;\n\t\tdevice-width = <2>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x3b0000>;\n\t\t\t};\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_wifi: wifi {\n\t\t\tlabel = \"green:wifi\";\n\t\t\tgpios = <&gpio0 7 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 10 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio0 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"spi\", \"i2c\", \"jtag\", \"rgmii\", \"mdio\", \"uartf\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&esw {\n\tmediatek,portmap = <0x3e>;\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&otg {\n\tstatus = \"okay\";\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt3052_tenda_3g300m.dts",
    "content": "#include \"rt3050.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"tenda,3g300m\", \"ralink,rt3052-soc\";\n\tmodel = \"Tenda 3G300M\";\n\n\taliases {\n\t\tled-boot = &led_ap;\n\t\tled-failsafe = &led_ap;\n\t\tled-running = &led_ap;\n\t\tled-upgrade = &led_ap;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\t3grouter {\n\t\t\tlabel = \"blue:3grouter\";\n\t\t\tgpios = <&gpio0 11 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_ap: ap {\n\t\t\tlabel = \"blue:ap\";\n\t\t\tgpios = <&gpio0 12 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twisprouter {\n\t\t\tlabel = \"blue:wisprouter\";\n\t\t\tgpios = <&gpio0 9 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twirelessrouter {\n\t\t\tlabel = \"blue:wirelessrouter\";\n\t\t\tgpios = <&gpio0 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\t3g {\n\t\t\tlabel = \"blue:3g\";\n\t\t\tgpios = <&gpio0 7 GPIO_ACTIVE_LOW>;\n\t\t\ttrigger-sources = <&otg_port1>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\n\t\twpsreset {\n\t\t\tlabel = \"blue:wpsreset\";\n\t\t\tgpios = <&gpio0 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\tmode {\n\t\t\tlabel = \"mode\";\n\t\t\tgpios = <&gpio0 10 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_0>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x3b0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"jtag\", \"rgmii\", \"mdio\", \"uartf\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&esw {\n\tmediatek,portmap = <0x2f>;\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&otg {\n\tstatus = \"okay\";\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt3052_tenda_w306r-v2.dts",
    "content": "#include \"rt3050.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"tenda,w306r-v2\", \"ralink,rt3052-soc\";\n\tmodel = \"Tenda W306R V2.0\";\n\n\taliases {\n\t\tled-boot = &led_sys;\n\t\tled-failsafe = &led_sys;\n\t\tled-running = &led_sys;\n\t\tled-upgrade = &led_sys;\n\t};\n\n\tflash@1f000000 {\n\t\tcompatible = \"cfi-flash\";\n\t\treg = <0x1f000000 0x800000>;\n\t\tbank-width = <2>;\n\t\tdevice-width = <2>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x3b0000>;\n\t\t\t};\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_sys: sys {\n\t\t\tlabel = \"green:sys\";\n\t\t\tgpios = <&gpio0 9 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&gpio0 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"RESET/WPS\";\n\t\t\tgpios = <&gpio0 10 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"spi\", \"i2c\", \"jtag\", \"rgmii\", \"mdio\", \"uartf\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_28>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&esw {\n\tmediatek,portmap = <0x3e>;\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_28: macaddr@28 {\n\t\treg = <0x28 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt3052_unbranded_wr512-3gn-4m.dts",
    "content": "#include \"rt3052_unbranded_wr512-3gn.dtsi\"\n\n/ {\n\tcompatible = \"unbranded,wr512-3gn-4m\", \"unbranded,wr512-3gn\", \"ralink,rt3052-soc\";\n\tmodel = \"Unbranded WR512-3GN (4M)\";\n\n\tflash@1f000000 {\n\t\tcompatible = \"cfi-flash\";\n\t\treg = <0x1f000000 0x800000>;\n\t\tbank-width = <2>;\n\t\tdevice-width = <2>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x3b0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt3052_unbranded_wr512-3gn-8m.dts",
    "content": "#include \"rt3052_unbranded_wr512-3gn.dtsi\"\n\n/ {\n\tcompatible = \"unbranded,wr512-3gn-8m\", \"unbranded,wr512-3gn\", \"ralink,rt3052-soc\";\n\tmodel = \"Unbranded WR512-3GN (8M)\";\n\n\tflash@1f000000 {\n\t\tcompatible = \"cfi-flash\";\n\t\treg = <0x1f000000 0x800000>;\n\t\tbank-width = <2>;\n\t\tdevice-width = <2>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x7b0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt3052_unbranded_wr512-3gn.dtsi",
    "content": "#include \"rt3050.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"unbranded,wr512-3gn\", \"ralink,rt3052-soc\";\n\n\taliases {\n\t\tled-boot = &led_wps;\n\t\tled-failsafe = &led_wps;\n\t\tled-running = &led_wps;\n\t\tled-upgrade = &led_wps;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\t3g {\n\t\t\tlabel = \"green:3g\";\n\t\t\tgpios = <&gpio0 9 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tgateway {\n\t\t\tlabel = \"green:gateway\";\n\t\t\tgpios = <&gpio0 11 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tap {\n\t\t\tlabel = \"green:ap\";\n\t\t\tgpios = <&gpio0 12 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_wps: wps {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&gpio0 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tstation {\n\t\t\tlabel = \"green:station\";\n\t\t\tgpios = <&gpio0 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <20>;\n\n\t\treset_wps {\n\t\t\tlabel = \"reset_wps\";\n\t\t\tgpios = <&gpio0 10 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\tmode {\n\t\t\tlabel = \"mode\";\n\t\t\tgpios = <&gpio0 7 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_0>;\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"spi\", \"i2c\", \"jtag\", \"rgmii\", \"mdio\", \"uartf\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&esw {\n\tmediatek,portmap = <0x2f>;\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&otg {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt3052_unbranded_xdx-rn502j.dts",
    "content": "#include \"rt3050.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"unbranded,xdx-rn502j\", \"ralink,rt3052-soc\";\n\tmodel = \"Unbranded XDX-RN502J\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tflash@1f000000 {\n\t\tcompatible = \"cfi-flash\";\n\t\treg = <0x1f000000 0x800000>;\n\t\tbank-width = <2>;\n\t\tdevice-width = <2>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x3b0000>;\n\t\t\t};\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twifi {\n\t\t\tlabel = \"green:wifi\";\n\t\t\tgpios = <&gpio0 7 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_power: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio0 9 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 10 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"spi\", \"i2c\", \"jtag\", \"rgmii\", \"mdio\", \"uartf\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_28>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&esw {\n\tmediatek,portmap = <0x3e>;\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&otg {\n\tstatus = \"okay\";\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_28: macaddr@28 {\n\t\treg = <0x28 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt3052_upvel_ur-326n4g.dts",
    "content": "#include \"rt3050.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"upvel,ur-326n4g\", \"ralink,rt3052-soc\";\n\tmodel = \"UPVEL UR-326N4G\";\n\n\taliases {\n\t\tled-boot = &led_wps;\n\t\tled-failsafe = &led_wps;\n\t\tled-running = &led_wps;\n\t\tled-upgrade = &led_wps;\n\t};\n\n\tflash@1f000000 {\n\t\tcompatible = \"cfi-flash\";\n\t\treg = <0x1f000000 0x800000>;\n\t\tbank-width = <2>;\n\t\tdevice-width = <2>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x3b0000>;\n\t\t\t};\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\t3g {\n\t\t\tlabel = \"green:3g\";\n\t\t\tgpios = <&gpio0 9 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tgateway {\n\t\t\tlabel = \"green:gateway\";\n\t\t\tgpios = <&gpio0 11 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tap {\n\t\t\tlabel = \"green:ap\";\n\t\t\tgpios = <&gpio0 12 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_wps: wps {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&gpio0 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tstation {\n\t\t\tlabel = \"green:station\";\n\t\t\tgpios = <&gpio0 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <20>;\n\n\t\treset_wps {\n\t\t\tlabel = \"reset_wps\";\n\t\t\tgpios = <&gpio0 10 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\tmode {\n\t\t\tlabel = \"mode\";\n\t\t\tgpios = <&gpio0 7 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_0>;\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"spi\", \"i2c\", \"jtag\", \"rgmii\", \"mdio\", \"uartf\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_4004>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&esw {\n\tmediatek,portmap = <0x2f>;\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&otg {\n\tstatus = \"okay\";\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4004: macaddr@4004 {\n\t\treg = <0x4004 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt3052_upvel_ur-336un.dts",
    "content": "#include \"rt3050.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"upvel,ur-336un\", \"ralink,rt3052-soc\";\n\tmodel = \"UPVEL UR-336UN\";\n\n\taliases {\n\t\tled-boot = &led_wps;\n\t\tled-failsafe = &led_wps;\n\t\tled-running = &led_wps;\n\t\tled-upgrade = &led_wps;\n\t};\n\n\tflash@1f000000 {\n\t\tcompatible = \"cfi-flash\";\n\t\treg = <0x1f000000 0x800000>;\n\t\tbank-width = <2>;\n\t\tdevice-width = <2>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x7b0000>;\n\t\t\t};\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\t3g {\n\t\t\tlabel = \"green:3g\";\n\t\t\tgpios = <&gpio0 9 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tgateway {\n\t\t\tlabel = \"green:gateway\";\n\t\t\tgpios = <&gpio0 11 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tap {\n\t\t\tlabel = \"green:ap\";\n\t\t\tgpios = <&gpio0 12 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_wps: wps {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&gpio0 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tstation {\n\t\t\tlabel = \"green:station\";\n\t\t\tgpios = <&gpio0 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <20>;\n\n\t\treset_wps {\n\t\t\tlabel = \"reset_wps\";\n\t\t\tgpios = <&gpio0 10 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\tmode {\n\t\t\tlabel = \"mode\";\n\t\t\tgpios = <&gpio0 7 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_0>;\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"spi\", \"i2c\", \"jtag\", \"rgmii\", \"mdio\", \"uartf\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_4004>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&esw {\n\tmediatek,portmap = <0x2f>;\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&otg {\n\tstatus = \"okay\";\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4004: macaddr@4004 {\n\t\treg = <0x4004 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt3052_zyxel_keenetic.dts",
    "content": "#include \"rt3050.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"zyxel,keenetic\", \"ralink,rt3052-soc\";\n\tmodel = \"ZyXEL Keenetic\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tflash@1f000000 {\n\t\tcompatible = \"cfi-flash\";\n\t\treg = <0x1f000000 0x800000>;\n\t\tbank-width = <2>;\n\t\tdevice-width = <2>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x7b0000>;\n\t\t\t};\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio0 9 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tusb {\n\t\t\tlabel = \"green:usb\";\n\t\t\tgpios = <&gpio0 13 GPIO_ACTIVE_LOW>;\n\t\t\ttrigger-sources = <&otg_port1>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&gpio0 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 10 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\trfkill {\n\t\t\tlabel = \"rfkill\";\n\t\t\tgpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = <KEY_RFKILL>;\n\t\t\tlinux,input-type = <EV_SW>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio0 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"uartf\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_28>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&esw {\n\tmediatek,portmap = <0x2f>;\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&otg {\n\tstatus = \"okay\";\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_28: macaddr@28 {\n\t\treg = <0x28 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt3052_zyxel_nbg-419n.dts",
    "content": "#include \"rt3050.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"zyxel,nbg-419n\", \"ralink,rt3052-soc\";\n\tmodel = \"ZyXEL NBG-419N\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tflash@1f000000 {\n\t\tcompatible = \"cfi-flash\";\n\t\treg = <0x1f000000 0x800000>;\n\t\tbank-width = <2>;\n\t\tdevice-width = <2>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x3b0000>;\n\t\t\t};\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio0 9 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&gpio0 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 10 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio0 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"spi\", \"i2c\", \"jtag\", \"rgmii\", \"mdio\", \"uartf\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_28>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&esw {\n\tmediatek,portmap = <0x2f>;\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_28: macaddr@28 {\n\t\treg = <0x28 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt3352.dtsi",
    "content": "/dts-v1/;\n\n/ {\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\tcompatible = \"ralink,rt3352-soc\";\n\n\taliases {\n\t\tspi0 = &spi0;\n\t\tspi1 = &spi1;\n\t\tserial0 = &uartlite;\n\t};\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu@0 {\n\t\t\tcompatible = \"mips,mips24KEc\";\n\t\t\treg = <0>;\n\t\t};\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,57600\";\n\t};\n\n\tcpuintc: cpuintc {\n\t\t#address-cells = <0>;\n\t\t#interrupt-cells = <1>;\n\t\tinterrupt-controller;\n\t\tcompatible = \"mti,cpu-interrupt-controller\";\n\t};\n\n\tpalmbus: palmbus@10000000 {\n\t\tcompatible = \"palmbus\";\n\t\treg = <0x10000000 0x200000>;\n\t\tranges = <0x0 0x10000000 0x1FFFFF>;\n\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tsysc: sysc@0 {\n\t\t\tcompatible = \"ralink,rt3352-sysc\", \"ralink,rt3050-sysc\", \"syscon\";\n\t\t\treg = <0x0 0x100>;\n\t\t};\n\n\t\ttimer: timer@100 {\n\t\t\tcompatible = \"ralink,rt3352-timer\", \"ralink,rt2880-timer\";\n\t\t\treg = <0x100 0x20>;\n\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <1>;\n\t\t};\n\n\t\twatchdog: watchdog@120 {\n\t\t\tcompatible = \"ralink,rt3352-wdt\", \"ralink,rt2880-wdt\";\n\t\t\treg = <0x120 0x10>;\n\n\t\t\tresets = <&rstctrl 8>;\n\t\t\treset-names = \"wdt\";\n\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <1>;\n\t\t};\n\n\t\tintc: intc@200 {\n\t\t\tcompatible = \"ralink,rt3352-intc\", \"ralink,rt2880-intc\";\n\t\t\treg = <0x200 0x100>;\n\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <1>;\n\n\t\t\tinterrupt-parent = <&cpuintc>;\n\t\t\tinterrupts = <2>;\n\t\t};\n\n\t\tmemc: memc@300 {\n\t\t\tcompatible = \"ralink,rt3352-memc\", \"ralink,rt3050-memc\";\n\t\t\treg = <0x300 0x100>;\n\n\t\t\tresets = <&rstctrl 20>;\n\t\t\treset-names = \"mc\";\n\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <3>;\n\t\t};\n\n\t\tuart: uart@500 {\n\t\t\tcompatible = \"ralink,rt3352-uart\", \"ralink,rt2880-uart\", \"ns16550a\";\n\t\t\treg = <0x500 0x100>;\n\n\t\t\tresets = <&rstctrl 12>;\n\t\t\treset-names = \"uart\";\n\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <5>;\n\n\t\t\treg-shift = <2>;\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tgpio0: gpio@600 {\n\t\t\tcompatible = \"ralink,rt3352-gpio\", \"ralink,rt2880-gpio\";\n\t\t\treg = <0x600 0x34>;\n\n\t\t\tgpio-controller;\n\t\t\t#gpio-cells = <2>;\n\n\t\t\tngpios = <24>;\n\t\t\tralink,gpio-base = <0>;\n\t\t\tralink,register-map = [ 00 04 08 0c\n\t\t\t\t\t\t20 24 28 2c\n\t\t\t\t\t\t30 34 ];\n\t\t\tresets = <&rstctrl 13>;\n\t\t\treset-names = \"pio\";\n\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <6>;\n\t\t};\n\n\t\tgpio1: gpio@638 {\n\t\t\tcompatible = \"ralink,rt3352-gpio\", \"ralink,rt2880-gpio\";\n\t\t\treg = <0x638 0x24>;\n\n\t\t\tgpio-controller;\n\t\t\t#gpio-cells = <2>;\n\n\t\t\tngpios = <16>;\n\t\t\tralink,gpio-base = <24>;\n\t\t\tralink,register-map = [ 00 04 08 0c\n\t\t\t\t\t\t10 14 18 1c\n\t\t\t\t\t\t20 24 ];\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tgpio2: gpio@660 {\n\t\t\tcompatible = \"ralink,rt3352-gpio\", \"ralink,rt2880-gpio\";\n\t\t\treg = <0x660 0x24>;\n\n\t\t\tgpio-controller;\n\t\t\t#gpio-cells = <2>;\n\n\t\t\tngpios = <6>;\n\t\t\tralink,gpio-base = <40>;\n\t\t\tralink,register-map = [ 00 04 08 0c\n\t\t\t\t\t\t10 14 18 1c\n\t\t\t\t\t\t20 24 ];\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\ti2c@900 {\n\t\t\tcompatible = \"ralink,rt2880-i2c\";\n\t\t\treg = <0x900 0x100>;\n\n\t\t\tresets = <&rstctrl 16>;\n\t\t\treset-names = \"i2c\";\n\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\n\t\t\tstatus = \"disabled\";\n\n\t\t\tpinctrl-names = \"default\";\n\t\t\tpinctrl-0 = <&i2c_pins>;\n\t\t};\n\n\t\ti2s@a00 {\n\t\t\tcompatible = \"ralink,rt3352-i2s\";\n\t\t\treg = <0xa00 0x100>;\n\n\t\t\tresets = <&rstctrl 17>;\n\t\t\treset-names = \"i2s\";\n\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <10>;\n\n\t\t\ttxdma-req = <2>;\n\t\t\trxdma-req = <3>;\n\n\t\t\tdmas = <&gdma 4>,\n\t\t\t\t<&gdma 6>;\n\t\t\tdma-names = \"tx\", \"rx\";\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tspi0: spi@b00 {\n\t\t\tcompatible = \"ralink,rt3352-spi\", \"ralink,rt2880-spi\";\n\t\t\treg = <0xb00 0x40>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\n\t\t\tresets = <&rstctrl 18>;\n\t\t\treset-names = \"spi\";\n\n\t\t\tpinctrl-names = \"default\";\n\t\t\tpinctrl-0 = <&spi_pins>;\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tspi1: spi@b40 {\n\t\t\tcompatible = \"ralink,rt3352-spi\", \"ralink,rt2880-spi\";\n\t\t\treg = <0xb40 0x60>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\n\t\t\tresets = <&rstctrl 18>;\n\t\t\treset-names = \"spi\";\n\n\t\t\tpinctrl-names = \"default\";\n\t\t\tpinctrl-0 = <&spi_cs1>;\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tuartlite: uartlite@c00 {\n\t\t\tcompatible = \"ralink,rt3352-uart\", \"ralink,rt2880-uart\", \"ns16550a\";\n\t\t\treg = <0xc00 0x100>;\n\n\t\t\tresets = <&rstctrl 19>;\n\t\t\treset-names = \"uartl\";\n\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <12>;\n\n\t\t\treg-shift = <2>;\n\n\t\t\tpinctrl-names = \"default\";\n\t\t\tpinctrl-0 = <&uartlite_pins>;\n\t\t};\n\n\t\tgdma: gdma@2800 {\n\t\t\tcompatible = \"ralink,rt3883-gdma\";\n\t\t\treg = <0x2800 0x800>;\n\n\t\t\tresets = <&rstctrl 14>;\n\t\t\treset-names = \"dma\";\n\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <7>;\n\n\t\t\t#dma-cells = <1>;\n\t\t\t#dma-channels = <16>;\n\t\t\t#dma-requests = <16>;\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\t};\n\n\tpinctrl: pinctrl {\n\t\tcompatible = \"ralink,rt2880-pinmux\";\n\n\t\tpinctrl-names = \"default\";\n\t\tpinctrl-0 = <&state_default>;\n\n\t\tstate_default: pinctrl0 {\n\t\t};\n\n\t\ti2c_pins: i2c_pins {\n\t\t\ti2c_pins {\n\t\t\t\tgroups = \"i2c\";\n\t\t\t\tfunction = \"i2c\";\n\t\t\t};\n\t\t};\n\n\t\tmdio_pins: mdio {\n\t\t\tmdio {\n\t\t\t\tgroups = \"mdio\";\n\t\t\t\tfunction = \"mdio\";\n\t\t\t};\n\t\t};\n\n\t\trgmii_pins: rgmii {\n\t\t\trgmii {\n\t\t\t\tgroups = \"rgmii\";\n\t\t\t\tfunction = \"rgmii\";\n\t\t\t};\n\t\t};\n\n\t\tspi_pins: spi_pins {\n\t\t\tspi_pins {\n\t\t\t\tgroups = \"spi\";\n\t\t\t\tfunction = \"spi\";\n\t\t\t};\n\t\t};\n\n\t\tspi_cs1: spi1 {\n\t\t\tspi1 {\n\t\t\t\tgroups = \"spi_cs1\";\n\t\t\t\tfunction = \"spi_cs1\";\n\t\t\t};\n\t\t};\n\n\t\tuartlite_pins: uartlite {\n\t\t\tuart {\n\t\t\t\tgroups = \"uartlite\";\n\t\t\t\tfunction = \"uartlite\";\n\t\t\t};\n\t\t};\n\t};\n\n\trstctrl: rstctrl {\n\t\tcompatible = \"ralink,rt3352-reset\", \"ralink,rt2880-reset\";\n\t\t#reset-cells = <1>;\n\t};\n\n\tclkctrl: clkctrl {\n\t\tcompatible = \"ralink,rt2880-clock\";\n\t\t#clock-cells = <1>;\n\t};\n\n\tethernet: ethernet@10100000 {\n\t\tcompatible = \"ralink,rt3352-eth\", \"ralink,rt3050-eth\";\n\t\treg = <0x10100000 0x10000>;\n\n\t\tresets = <&rstctrl 21>;\n\t\treset-names = \"fe\";\n\n\t\tinterrupt-parent = <&cpuintc>;\n\t\tinterrupts = <5>;\n\n\t\tmediatek,switch = <&esw>;\n\t};\n\n\tesw: esw@10110000 {\n\t\tcompatible = \"ralink,rt3352-esw\", \"ralink,rt3050-esw\";\n\t\treg = <0x10110000 0x8000>;\n\n\t\tresets = <&rstctrl 23 &rstctrl 24>;\n\t\treset-names = \"esw\", \"ephy\";\n\n\t\tinterrupt-parent = <&intc>;\n\t\tinterrupts = <17>;\n\t};\n\n\tusbphy: usbphy {\n\t\tcompatible = \"ralink,rt3352-usbphy\";\n\t\t#phy-cells = <0>;\n\n\t\tralink,sysctl = <&sysc>;\n\t\tresets = <&rstctrl 22 &rstctrl 25>;\n\t\treset-names = \"host\", \"device\";\n\t\tclocks = <&clkctrl 18 &clkctrl 20>;\n\t\tclock-names = \"host\", \"device\";\n\t};\n\n\twmac: wmac@10180000 {\n\t\tcompatible = \"ralink,rt3352-wmac\", \"ralink,rt2880-wmac\";\n\t\treg = <0x10180000 0x40000>;\n\n\t\tinterrupt-parent = <&cpuintc>;\n\t\tinterrupts = <6>;\n\n\t\tralink,eeprom = \"soc_wmac.eeprom\";\n\t};\n\n\tehci: ehci@101c0000 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tcompatible = \"generic-ehci\";\n\t\treg = <0x101c0000 0x1000>;\n\n\t\tphys = <&usbphy>;\n\t\tphy-names = \"usb\";\n\n\t\tinterrupt-parent = <&intc>;\n\t\tinterrupts = <18>;\n\n\t\tstatus = \"disabled\";\n\n\t\tehci_port1: port@1 {\n\t\t\treg = <1>;\n\t\t\t#trigger-source-cells = <0>;\n\t\t};\n\t};\n\n\tohci: ohci@101c1000 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tcompatible = \"generic-ohci\";\n\t\treg = <0x101c1000 0x1000>;\n\n\t\tphys = <&usbphy>;\n\t\tphy-names = \"usb\";\n\n\t\tinterrupt-parent = <&intc>;\n\t\tinterrupts = <18>;\n\n\t\tstatus = \"disabled\";\n\n\t\tohci_port1: port@1 {\n\t\t\treg = <1>;\n\t\t\t#trigger-source-cells = <0>;\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt3352_allnet_all5002.dts",
    "content": "#include \"rt3352.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"allnet,all5002\", \"ralink,rt3352-soc\";\n\tmodel = \"Allnet ALL5002\";\n\n\ti2c-gpio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcompatible = \"i2c-gpio\";\n\t\tgpios = <&gpio0 1 GPIO_ACTIVE_HIGH &gpio0 2 GPIO_ACTIVE_HIGH>;\n\t\ti2c-gpio,delay-us = <10>;\n\n\t\tpcf0: iexp@38 {\n\t\t\t#gpio-cells = <2>;\n\t\t\tcompatible = \"inxp,pcf8574a\";\n\t\t\treg = <0x38>;\n\t\t\tgpio-controller;\n\t\t};\n\n\t\thwmon@4b {\n\t\t\tcompatible = \"national,lm92\";\n\t\t\treg = <0x4b>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tld1 {\n\t\t\tlabel = \"green:ld1\";\n\t\t\tgpios = <&pcf0 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tld2 {\n\t\t\tlabel = \"green:ld2\";\n\t\t\tgpios = <&pcf0 1 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x1fb0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"jtag\", \"rgmii\", \"mdio\", \"uartf\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_28>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&esw {\n\tmediatek,portmap = <0x3f>;\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&ehci {\n\tstatus = \"okay\";\n};\n\n&ohci {\n\tstatus = \"okay\";\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_28: macaddr@28 {\n\t\treg = <0x28 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt3352_dlink_dir-615-h1.dts",
    "content": "#include \"rt3352.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"dlink,dir-615-h1\", \"ralink,rt3352-soc\";\n\tmodel = \"D-Link DIR-615 H1\";\n\n\taliases {\n\t\tled-boot = &led_status_green;\n\t\tled-failsafe = &led_status_green;\n\t\tled-running = &led_status_green;\n\t\tled-upgrade = &led_status_green;\n\t\tlabel-mac-device = &wmac;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tstatus {\n\t\t\tlabel = \"amber:status\";\n\t\t\tgpios = <&gpio0 7 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tled_status_green: status2 {\n\t\t\tlabel = \"green:status\";\n\t\t\tgpios = <&gpio0 9 GPIO_ACTIVE_HIGH>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\twan {\n\t\t\tlabel = \"amber:wan\";\n\t\t\tgpios = <&gpio0 12 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twan2 {\n\t\t\tlabel = \"green:wan\";\n\t\t\tgpios = <&gpio0 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"blue:wps\";\n\t\t\tgpios = <&gpio0 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 10 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio0 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x3b0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"jtag\", \"uartf\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_28>;\n\tnvmem-cell-names = \"mac-address\";\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&rgmii_pins &mdio_pins>;\n};\n\n&esw {\n\tmediatek,portmap = <0x2f>;\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_28: macaddr@28 {\n\t\treg = <0x28 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt3352_dlink_dir-620-d1.dts",
    "content": "#include \"rt3352.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"dlink,dir-620-d1\", \"ralink,rt3352-soc\";\n\tmodel = \"D-Link DIR-620 D1\";\n\n\taliases {\n\t\tled-boot = &led_status;\n\t\tled-failsafe = &led_status;\n\t\tled-running = &led_status;\n\t\tled-upgrade = &led_status;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_status: status {\n\t\t\tlabel = \"green:status\";\n\t\t\tgpios = <&gpio0 9 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twifi {\n\t\t\tlabel = \"green:wifi\";\n\t\t\tgpios = <&gpio0 17 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <20>;\n\n\t\treset_wps {\n\t\t\tlabel = \"reset_wps\";\n\t\t\tgpios = <&gpio0 7 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x7b0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"jtag\", \"uartf\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&rgmii_pins &mdio_pins>;\n};\n\n&esw {\n\tmediatek,portmap = <0x2f>;\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&ehci {\n\tstatus = \"okay\";\n};\n\n&ohci {\n\tstatus = \"okay\";\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt3352_zte_mf283plus.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"rt3352.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"zte,mf283plus\", \"ralink,rt3352-soc\";\n\tmodel = \"ZTE MF283+\";\n\n\taliases {\n\t\tled-boot = &led_wwan_green;\n\t\tled-failsafe = &led_wwan_red;\n\t\tled-upgrade = &led_wwan_red;\n\t\tlabel-mac-device = &ethernet;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_wwan_blue: wwan_blue {\n\t\t\tlabel = \"blue:wwan\";\n\t\t\tgpios = <&gpio1 1 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_wwan_green: wwan_green {\n\t\t\tlabel = \"green:wwan\";\n\t\t\tgpios = <&gpio1 2 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_wwan_red: wwan_red {\n\t\t\tlabel = \"red:wwan\";\n\t\t\tgpios = <&gpio1 7 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tsignal {\n\t\t\tlabel = \"blue:signal\";\n\t\t\tgpios = <&gpio1 3 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio1 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio0 19 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <50000000>;\n\t\tm25p,fast-read;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x60000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@60000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x60000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@70000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x70000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@80000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x80000 0xf80000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"jtag\", \"rgmii\", \"mdio\", \"uartf\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&gpio1 {\n\tstatus = \"okay\";\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_28>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&esw {\n\tmediatek,portmap = <0x2f>;\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&ehci {\n\tstatus = \"okay\";\n};\n\n&ohci {\n\tstatus = \"okay\";\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_28: macaddr@28 {\n\t\treg = <0x28 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt3352_zyxel_nbg-419n-v2.dts",
    "content": "#include \"rt3352.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"zyxel,nbg-419n-v2\", \"ralink,rt3352-soc\";\n\tmodel = \"ZyXEL NBG-419N v2\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio0 9 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&gpio0 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tusb {\n\t\t\tlabel = \"green:usb\";\n\t\t\tgpios = <&gpio0 13 GPIO_ACTIVE_LOW>;\n\t\t\ttrigger-sources = <&ohci_port1>, <&ehci_port1>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <20>;\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 10 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio0 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t\trfkill {\n\t\t\tlabel = \"rfkill\";\n\t\t\tlinux,input-type = <EV_SW>;\n\t\t\tgpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = <KEY_RFKILL>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x7b0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"jtag\", \"rgmii\", \"mdio\", \"uartf\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_28>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&esw {\n\tmediatek,portmap = <0x2f>;\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&ehci {\n\tstatus = \"okay\";\n};\n\n&ohci {\n\tstatus = \"okay\";\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_28: macaddr@28 {\n\t\treg = <0x28 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt3662_asus_rt-n56u.dts",
    "content": "#include \"rt3883.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"asus,rt-n56u\", \"ralink,rt3662-soc\", \"ralink,rt3883-soc\";\n\tmodel = \"Asus RT-N56U\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tflash@1c000000 {\n\t\tcompatible = \"cfi-flash\";\n\t\treg = <0x1c000000 0x800000>;\n\t\tbank-width = <2>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\treg = <0x0 0x0030000>;\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\treg = <0x00030000 0x00010000>;\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\treg = <0x00040000 0x00010000>;\n\t\t\t\tlabel = \"factory\";\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\treg = <0x00050000 0x007b0000>;\n\t\t\t\tlabel = \"firmware\";\n\t\t\t};\n\t\t};\n\t};\n\n\trtl8367 {\n\t\tcompatible = \"realtek,rtl8367\";\n\t\tgpio-sda = <&gpio0 1 GPIO_ACTIVE_HIGH>;\n\t\tgpio-sck = <&gpio0 2 GPIO_ACTIVE_HIGH>;\n\t\trealtek,extif1 = <1 0 1 1 1 1 1 1 2>;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <100>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 13 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio1 2 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"blue:power\";\n\t\t\tgpios = <&gpio0 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan {\n\t\t\tlabel = \"blue:lan\";\n\t\t\tgpios = <&gpio0 19 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twan {\n\t\t\tlabel = \"blue:wan\";\n\t\t\tgpios = <&gpio1 3 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tusb {\n\t\t\tlabel = \"blue:usb\";\n\t\t\tgpios = <&gpio1 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&gpio1 {\n\tstatus = \"okay\";\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"spi\", \"i2c\", \"jtag\", \"uartf\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tport@0 {\n\t\tmediatek,fixed-link = <1000 1 1 1>;\n\t};\n};\n\n&pci {\n\tstatus = \"okay\";\n};\n\n&pci1 {\n\tstatus = \"okay\";\n\n\twifi@0,0 {\n\t\tcompatible = \"pci1814,3091\";\n\t\treg = <0x10000 0 0 0 0>;\n\t\tralink,mtd-eeprom = <&factory 0x8000>;\n\t};\n};\n\n&wmac {\n\tstatus = \"okay\";\n\tralink,2ghz = <0>;\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&ehci {\n\tstatus = \"okay\";\n};\n\n&ohci {\n\tstatus = \"okay\";\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt3662_dlink_dir-645.dts",
    "content": "#include \"rt3883.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"dlink,dir-645\", \"ralink,rt3662-soc\", \"ralink,rt3883-soc\";\n\tmodel = \"D-Link DIR-645\";\n\n\taliases {\n\t\tled-boot = &led_wps;\n\t\tled-failsafe = &led_wps;\n\t\tled-running = &led_wps;\n\t\tled-upgrade = &led_wps;\n\t};\n\n\trtl8367b {\n\t\tcompatible = \"realtek,rtl8367b\";\n\t\tgpio-sda = <&gpio0 1 GPIO_ACTIVE_HIGH>;\n\t\tgpio-sck = <&gpio0 2 GPIO_ACTIVE_HIGH>;\n\t\trealtek,extif1 = <1 0 1 1 1 1 1 1 2>;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <100>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 9 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio0 14 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tinet {\n\t\t\tlabel = \"green:inet\";\n\t\t\tgpios = <&gpio0 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_wps: wps {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n\n\tgpio_export {\n\t\tcompatible = \"gpio-export\";\n\t\t#size-cells = <0>;\n\n\t\tusb {\n\t\t\tgpio-export,name = \"usb\";\n\t\t\tgpio-export,output = <1>;\n\t\t\tgpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&gpio1 {\n\tstatus = \"okay\";\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"uboot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"uboot-env\";\n\t\t\t\treg = <0x30000 0x4000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@34000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x34000 0x4000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@38000 {\n\t\t\t\tlabel = \"nvram\";\n\t\t\t\treg = <0x38000 0x8000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"devdata\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"seama\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x7b0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"jtag\", \"uartf\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tport@0 {\n\t\tmediatek,fixed-link = <1000 1 1 0>;\n\t};\n};\n\n&wmac {\n\tralink,5ghz = <0>;\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&ehci {\n\tstatus = \"okay\";\n};\n\n&ohci {\n\tstatus = \"okay\";\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt3662_edimax_br-6475nd.dts",
    "content": "#include \"rt3883.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/mtd/partitions/uimage.h>\n\n/ {\n\tcompatible = \"edimax,br-6475nd\", \"ralink,rt3662-soc\", \"ralink,rt3883-soc\";\n\tmodel = \"Edimax BR-6475nD\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <100>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 7 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\trfkill {\n\t\t\tlabel = \"rfkill\";\n\t\t\tgpios = <&gpio0 9 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,input-type = <EV_SW>;\n\t\t\tlinux,code = <KEY_RFKILL>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio0 10 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan {\n\t\t\tlabel = \"amber:wlan\";\n\t\t\tgpios = <&gpio0 11 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twlan_5ghz {\n\t\t\tlabel = \"amber:wlan_5ghz\";\n\t\t\tgpios = <&gpio0 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tflash@1c000000 {\n\t\tcompatible = \"cfi-flash\";\n\t\treg = <0x1c000000 0x800000>;\n\t\tbank-width = <2>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\treg = <0x00000000 0x00030000>;\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\treg = <0x00030000 0x00010000>;\n\t\t\t\tlabel = \"nvram\";\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\treg = <0x00040000 0x00010000>;\n\t\t\t\tlabel = \"factory\";\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tdevdata: partition@50000 {\n\t\t\t\treg = <0x00050000 0x00020000>;\n\t\t\t\tlabel = \"devdata\";\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@70000 {\n\t\t\t\tcompatible = \"openwrt,uimage\", \"denx,uimage\";\n\t\t\t\topenwrt,offset = <FW_EDIMAX_OFFSET>;\n\t\t\t\topenwrt,partition-magic = <FW_MAGIC_EDIMAX>;\n\t\t\t\treg = <0x00070000 0x00790000>;\n\t\t\t\tlabel = \"firmware\";\n\t\t\t};\n\t\t};\n\t};\n\n\trtl8367 {\n\t\tcompatible = \"realtek,rtl8367\";\n\t\tgpio-sda = <&gpio0 5 GPIO_ACTIVE_HIGH>;\n\t\tgpio-sck = <&gpio0 4 GPIO_ACTIVE_HIGH>;\n\t\trealtek,extif0 = <1 0 1 1 1 1 1 1 2>;\n\t};\n\n\t/*\n\t * Unclear if this is the correct gpio setup; the USB ports are\n\t * unpopulated on a stock BR-6475nD, even though the hardware exists\n\t * and the headers are there.\n\t */\n\t/*\n\tgpio_export {\n\t\tcompatible = \"gpio-export\";\n\t\t#size-cells = <0>;\n\n\t\tusb {\n\t\t\tgpio-export,name=\"usb\";\n\t\t\tgpio-export,output=<0>;\n\t\t\tgpios = <&gpio0 19 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\t*/\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"spi\", \"jtag\", \"uartf\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&timer {\n\tstatus = \"okay\";\n};\n\n&uartlite {\n\tstatus = \"okay\";\n};\n\n&ethernet {\n\tstatus = \"okay\";\n\tnvmem-cells = <&macaddr_devdata_d>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tport@0 {\n\t\tmediatek,fixed-link = <1000 1 1 1>;\n\t};\n};\n\n&wmac {\n\tstatus = \"okay\";\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&pci {\n\tstatus = \"okay\";\n};\n\n&pci1 {\n\tstatus = \"okay\";\n\n\twifi@0,0 {\n\t\tcompatible = \"pci0,0\";\n\t\treg = <0x10000 0 0 0 0>;\n\t\tralink,5ghz = <0>;\n\t\tralink,mtd-eeprom = <&factory 0x8000>;\n\t};\n};\n\n&ehci {\n\tstatus = \"okay\";\n};\n\n&ohci {\n\tstatus = \"okay\";\n};\n\n&devdata {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_devdata_d: macaddr@d {\n\t\treg = <0xd 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt3662_engenius_esr600h.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"rt3883.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"engenius,esr600h\", \"ralink,rt3662-soc\", \"ralink,rt3883-soc\";\n\tmodel = \"EnGenius ESR600H\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"blue:power\";\n\t\t\tgpios = <&gpio0 1 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"blue:wps\";\n\t\t\tgpios = <&gpio0 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <100>;\n\n\t\treset-wps {\n\t\t\tlabel = \"reset-wps\";\n\t\t\tgpios = <&gpio1 2 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tgpio_export {\n\t\tcompatible = \"gpio-export\";\n\t\t#size-cells = <0>;\n\n\t\tusb {\n\t\t\tgpio-export,name = \"usb\";\n\t\t\tgpio-export,output = <1>;\n\t\t\tgpios = <&gpio0 9 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&gpio1 {\n\tstatus = \"okay\";\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <20000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x1000>;\n\t\t\t};\n\n\t\t\tpartition@32000 {\n\t\t\t\tlabel = \"config\";\n\t\t\t\treg = <0x32000 0xe000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x7b0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"jtag\", \"uartf\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tstatus = \"okay\";\n\n\tport@0 {\n\t\tphy-handle = <&phy0>;\n\t\tphy-mode = \"rgmii\";\n\t};\n\n\tmdio-bus {\n\t\tstatus = \"okay\";\n\n\t\tphy0: ethernet-phy@0 {\n\t\t\treg = <0>;\n\t\t\tphy-mode = \"rgmii\";\n\n\t\t\tqca,ar8327-initvals = <\n\t\t\t\t0x04 0x07600000 /* PORT0 PAD MODE CTRL */\n\t\t\t\t0x0c 0x07600000 /* PORT6 PAD MODE CTRL */\n\t\t\t\t0x10 0x40000000 /* Power-on Strapping: 176-pin interface configuration */\n\t\t\t\t0x50 0xc437c437 /* LED Control Register 0 */\n\t\t\t\t0x54 0xc337c337 /* LED Control Register 1 */\n\t\t\t\t0x58 0x00000000 /* LED Control Register 2 */\n\t\t\t\t0x5c 0x03ffff00 /* LED Control Register 3 */\n\t\t\t\t0x7c 0x0000007e /* PORT0_STATUS */\n\t\t\t\t0x94 0x0000007e /* PORT6 STATUS */\n\t\t\t>;\n\t\t};\n\t};\n};\n\n&pci {\n\tstatus = \"okay\";\n};\n\n&pci1 {\n\tstatus = \"okay\";\n\n\twifi@0,1,0 {\n\t\tcompatible = \"pci1814,3091\";\n\t\treg = <0x0 1 0 0 0>;\n\t\tralink,5ghz = <0>;\n\t\tralink,mtd-eeprom = <&factory 0x8000>;\n\t};\n};\n\n&wmac {\n\tstatus = \"okay\";\n\n\tralink,2ghz = <0>;\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&ehci {\n\tstatus = \"okay\";\n};\n\n&ohci {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt3662_loewe_wmdr-143n.dts",
    "content": "#include \"rt3883.dtsi\"\n\n/ {\n\tcompatible = \"loewe,wmdr-143n\", \"ralink,rt3662-soc\", \"ralink,rt3883-soc\";\n\tmodel = \"Loewe WMDR-143N\";\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x00010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x7b0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&ethernet {\n\tport@0 {\n\t\tphy-handle = <&phy0>;\n\t\tphy-mode = \"mii\";\n\t};\n\tmdio-bus {\n\t\tstatus = \"okay\";\n\n\t\tphy0: ethernet-phy@0 {\n\t\t\treg = <0>;\n\t\t\tphy-mode = \"mii\";\n\t\t};\n\t};\n};\n\n&wmac {\n\tstatus = \"okay\";\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt3662_omnima_hpm.dts",
    "content": "#include \"rt3883.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"omnima,hpm\", \"ralink,rt3662-soc\", \"ralink,rt3883-soc\";\n\tmodel = \"Omnima HPM\";\n\n\taliases {\n\t\tled-boot = &led_status;\n\t\tled-failsafe = &led_status;\n\t\tled-running = &led_status;\n\t\tled-upgrade = &led_status;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200\";\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <100>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tpower {\n\t\t\tlabel = \"orange:power\";\n\t\t\tgpios = <&gpio0 7 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\tled_status: status {\n\t\t\tlabel = \"green:status\";\n\t\t\tgpios = <&gpio0 21 GPIO_ACTIVE_LOW>;\n\t\t\tdefault-state = \"on\";\n\t\t};\n\n\t\teth {\n\t\t\tlabel = \"green:eth\";\n\t\t\tgpios = <&gpio0 20 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\teth2 {\n\t\t\tlabel = \"red:eth\";\n\t\t\tgpios = <&gpio0 18 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twifi {\n\t\t\tlabel = \"green:wifi\";\n\t\t\tgpios = <&gpio0 17 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twifi2 {\n\t\t\tlabel = \"red:wifi\";\n\t\t\tgpios = <&gpio0 19 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tgpio_export {\n\t\tcompatible = \"gpio-export\";\n\t\t#size-cells = <0>;\n\t\t/* gpio 12 and 13 handle the OC input */\n\n\t\tusb0 {\n\t\t\tgpio-export,name = \"usb0\";\n\t\t\tgpio-export,output = <1>;\n\t\t\tgpios = <&gpio0 2 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tusb1 {\n\t\t\tgpio-export,name = \"usb1\";\n\t\t\tgpio-export,output = <1>;\n\t\t\tgpios = <&gpio0 1 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\tspi-max-frequency = <25000000>;\n\t\treg = <0>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\treg = <0x0 0x0030000>;\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\treg = <0x00030000 0x00010000>;\n\t\t\t\tlabel = \"config\";\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\treg = <0x00040000 0x00010000>;\n\t\t\t\tlabel = \"factory\";\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\treg = <0x00050000 0x00fb0000>;\n\t\t\t\tlabel = \"firmware\";\n\t\t\t};\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"jtag\", \"uartf\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tphy-handle = <&phy0>;\n\tphy-mode = \"rgmii\";\n\tnvmem-cells = <&macaddr_factory_28>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tmdio-bus {\n\t\tstatus = \"okay\";\n\n\t\tphy0: ethernet-phy@4 {\n\t\t\treg = <4>;\n\t\t};\n\t};\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&ehci {\n\tstatus = \"okay\";\n};\n\n&ohci {\n\tstatus = \"okay\";\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_28: macaddr@28 {\n\t\treg = <0x28 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt3662_samsung_cy-swr1100.dts",
    "content": "#include \"rt3883.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"samsung,cy-swr1100\", \"ralink,rt3662-soc\", \"ralink,rt3883-soc\";\n\tmodel = \"Samsung CY-SWR1100\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tflash@1c000000 {\n\t\tcompatible = \"cfi-flash\";\n\t\treg = <0x1c000000 0x800000>;\n\t\tbank-width = <2>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"uboot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"uboot-env\";\n\t\t\t\treg = <0x30000 0x4000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@34000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x34000 0x4000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@38000 {\n\t\t\t\tlabel = \"nvram\";\n\t\t\t\treg = <0x38000 0x8000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"devconf\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"seama\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x7b0000>;\n\t\t\t};\n\t\t};\n\t};\n\n\trtl8367 {\n\t\tcompatible = \"realtek,rtl8367\";\n\t\tgpio-sda = <&gpio0 1 GPIO_ACTIVE_HIGH>;\n\t\tgpio-sck = <&gpio0 2 GPIO_ACTIVE_HIGH>;\n\t\trealtek,extif0 = <1 0 1 1 1 1 1 1 2>;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 6 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio0 3 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twps {\n\t\t\tlabel = \"blue:wps\";\n\t\t\tgpios = <&gpio0 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tusb {\n\t\t\tlabel = \"blue:usb\";\n\t\t\tgpios = <&gpio1 1 GPIO_ACTIVE_LOW>;\n\t\t\ttrigger-sources = <&ohci_port1>, <&ehci_port1>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\n\t\tled_power: power {\n\t\t\tlabel = \"blue:power\";\n\t\t\tgpios = <&gpio1 2 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&gpio1 {\n\tstatus = \"okay\";\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"spi\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tport@0 {\n\t\tmediatek,fixed-link = <1000 1 1 1>;\n\t\tphy-mode = \"rgmii\";\n\t};\n};\n\n&pci {\n\tstatus = \"okay\";\n};\n\n&pci1 {\n\tstatus = \"okay\";\n\n\twifi@0,0 {\n\t\tcompatible = \"pci1814,3091\";\n\t\treg = <0x10000 0 0 0 0>;\n\t\tralink,mtd-eeprom = <&factory 0x2000>;\n\t};\n};\n\n&wmac {\n\tstatus = \"okay\";\n\tralink,2ghz = <0>;\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&ehci {\n\tstatus = \"okay\";\n};\n\n&ohci {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt3883.dtsi",
    "content": "/dts-v1/;\n\n/ {\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\tcompatible = \"ralink,rt3883-soc\";\n\n\taliases {\n\t\tspi0 = &spi0;\n\t\tspi1 = &spi1;\n\t\tserial0 = &uartlite;\n\t};\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu@0 {\n\t\t\tcompatible = \"mips,mips74Kc\";\n\t\t\treg = <0>;\n\t\t};\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,57600\";\n\t};\n\n\tcpuintc: cpuintc {\n\t\t#address-cells = <0>;\n\t\t#interrupt-cells = <1>;\n\t\tinterrupt-controller;\n\t\tcompatible = \"mti,cpu-interrupt-controller\";\n\t};\n\n\tpalmbus: palmbus@10000000 {\n\t\tcompatible = \"palmbus\";\n\t\treg = <0x10000000 0x200000>;\n\t\tranges = <0x0 0x10000000 0x1FFFFF>;\n\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tsysc: sysc@0 {\n\t\t\tcompatible = \"ralink,rt3883-sysc\", \"ralink,rt3050-sysc\", \"syscon\";\n\t\t\treg = <0x0 0x100>;\n\t\t};\n\n\t\ttimer: timer@100 {\n\t\t\tcompatible = \"ralink,rt3883-timer\", \"ralink,rt2880-timer\";\n\t\t\treg = <0x100 0x20>;\n\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <1>;\n\t\t};\n\n\t\twatchdog: watchdog@120 {\n\t\t\tcompatible = \"ralink,rt3883-wdt\", \"ralink,rt2880-wdt\";\n\t\t\treg = <0x120 0x10>;\n\n\t\t\tresets = <&rstctrl 8>;\n\t\t\treset-names = \"wdt\";\n\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <1>;\n\t\t};\n\n\t\tintc: intc@200 {\n\t\t\tcompatible = \"ralink,rt3883-intc\", \"ralink,rt2880-intc\";\n\t\t\treg = <0x200 0x100>;\n\n\t\t\tresets = <&rstctrl 19>;\n\t\t\treset-names = \"intc\";\n\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <1>;\n\n\t\t\tinterrupt-parent = <&cpuintc>;\n\t\t\tinterrupts = <2>;\n\t\t};\n\n\t\tmemc: memc@300 {\n\t\t\tcompatible = \"ralink,rt3883-memc\", \"ralink,rt3050-memc\";\n\t\t\treg = <0x300 0x100>;\n\n\t\t\tresets = <&rstctrl 20>;\n\t\t\treset-names = \"mc\";\n\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <3>;\n\t\t};\n\n\t\tuart: uart@500 {\n\t\t\tcompatible = \"ralink,rt3883-uart\", \"ralink,rt2880-uart\", \"ns16550a\";\n\t\t\treg = <0x500 0x100>;\n\n\t\t\tresets = <&rstctrl 12>;\n\t\t\treset-names = \"uart\";\n\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <5>;\n\n\t\t\treg-shift = <2>;\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tgpio0: gpio@600 {\n\t\t\tcompatible = \"ralink,rt3883-gpio\", \"ralink,rt2880-gpio\";\n\t\t\treg = <0x600 0x34>;\n\n\t\t\tresets = <&rstctrl 13>;\n\t\t\treset-names = \"pio\";\n\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <6>;\n\n\t\t\tgpio-controller;\n\t\t\t#gpio-cells = <2>;\n\n\t\t\tngpios = <24>;\n\t\t\tralink,gpio-base = <0>;\n\t\t\tralink,register-map = [ 00 04 08 0c\n\t\t\t\t\t\t20 24 28 2c\n\t\t\t\t\t\t30 34 ];\n\t\t};\n\n\t\tgpio1: gpio@638 {\n\t\t\tcompatible = \"ralink,rt3883-gpio\", \"ralink,rt2880-gpio\";\n\t\t\treg = <0x638 0x24>;\n\n\t\t\tgpio-controller;\n\t\t\t#gpio-cells = <2>;\n\n\t\t\tngpios = <16>;\n\t\t\tralink,gpio-base = <24>;\n\t\t\tralink,register-map = [ 00 04 08 0c\n\t\t\t\t\t\t10 14 18 1c\n\t\t\t\t\t\t20 24 ];\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tgpio2: gpio@660 {\n\t\t\tcompatible = \"ralink,rt3883-gpio\", \"ralink,rt2880-gpio\";\n\t\t\treg = <0x660 0x24>;\n\n\t\t\tgpio-controller;\n\t\t\t#gpio-cells = <2>;\n\n\t\t\tngpios = <32>;\n\t\t\tralink,gpio-base = <40>;\n\t\t\tralink,register-map = [ 00 04 08 0c\n\t\t\t\t\t\t10 14 18 1c\n\t\t\t\t\t\t20 24 ];\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tgpio3: gpio@688 {\n\t\t\tcompatible = \"ralink,rt3883-gpio\", \"ralink,rt2880-gpio\";\n\t\t\treg = <0x688 0x24>;\n\n\t\t\tgpio-controller;\n\t\t\t#gpio-cells = <2>;\n\n\t\t\tngpios = <24>;\n\t\t\tralink,gpio-base = <72>;\n\t\t\tralink,register-map = [ 00 04 08 0c\n\t\t\t\t\t\t10 14 18 1c\n\t\t\t\t\t\t20 24 ];\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\ti2c@900 {\n\t\t\tcompatible = \"ralink,rt2880-i2c\";\n\t\t\treg = <0x900 0x100>;\n\n\t\t\tresets = <&rstctrl 16>;\n\t\t\treset-names = \"i2c\";\n\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\n\t\t\tstatus = \"disabled\";\n\n\t\t\tpinctrl-names = \"default\";\n\t\t\tpinctrl-0 = <&i2c_pins>;\n\t\t};\n\n\t\ti2s@a00 {\n\t\t\tcompatible = \"ralink,rt3883-i2s\";\n\t\t\treg = <0xa00 0x100>;\n\n\t\t\tresets = <&rstctrl 17>;\n\t\t\treset-names = \"i2s\";\n\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <10>;\n\n\t\t\ttxdma-req = <2>;\n\t\t\trxdma-req = <3>;\n\n\t\t\tdmas = <&gdma 4>,\n\t\t\t\t<&gdma 6>;\n\t\t\tdma-names = \"tx\", \"rx\";\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tspi0: spi@b00 {\n\t\t\tcompatible = \"ralink,rt3883-spi\", \"ralink,rt2880-spi\";\n\t\t\treg = <0xb00 0x40>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\n\t\t\tresets = <&rstctrl 18>;\n\t\t\treset-names = \"spi\";\n\n\t\t\tpinctrl-names = \"default\";\n\t\t\tpinctrl-0 = <&spi_pins>;\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tspi1: spi@b40 {\n\t\t\tcompatible = \"ralink,rt3883-spi\", \"ralink,rt2880-spi\";\n\t\t\treg = <0xb40 0x60>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\n\t\t\tresets = <&rstctrl 18>;\n\t\t\treset-names = \"spi\";\n\n\t\t\tpinctrl-names = \"default\";\n\t\t\tpinctrl-0 = <&spi_cs1>;\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tuartlite: uartlite@c00 {\n\t\t\tcompatible = \"ralink,rt3883-uart\", \"ralink,rt2880-uart\", \"ns16550a\";\n\t\t\treg = <0xc00 0x100>;\n\n\t\t\tresets = <&rstctrl 19>;\n\t\t\treset-names = \"uartl\";\n\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <12>;\n\n\t\t\treg-shift = <2>;\n\n\t\t\tpinctrl-names = \"default\";\n\t\t\tpinctrl-0 = <&uartlite_pins>;\n\t\t};\n\n\t\tgdma: gdma@2800 {\n\t\t\tcompatible = \"ralink,rt3883-gdma\";\n\t\t\treg = <0x2800 0x800>;\n\n\t\t\tresets = <&rstctrl 14>;\n\t\t\treset-names = \"dma\";\n\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <7>;\n\n\t\t\t#dma-cells = <1>;\n\t\t\t#dma-channels = <16>;\n\t\t\t#dma-requests = <16>;\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\t};\n\n\tpinctrl: pinctrl {\n\t\tcompatible = \"ralink,rt2880-pinmux\";\n\n\t\tpinctrl-names = \"default\";\n\t\tpinctrl-0 = <&state_default>;\n\n\t\tstate_default: pinctrl0 {\n\t\t};\n\n\t\ti2c_pins: i2c_pins {\n\t\t\ti2c_pins {\n\t\t\t\tgroups = \"i2c\";\n\t\t\t\tfunction = \"i2c\";\n\t\t\t};\n\t\t};\n\n\t\tspi_pins: spi_pins {\n\t\t\tspi_pins {\n\t\t\t\tgroups = \"spi\";\n\t\t\t\tfunction = \"spi\";\n\t\t\t};\n\t\t};\n\n\t\tspi_cs1: spi1 {\n\t\t\tspi1 {\n\t\t\t\tgroups = \"pci\";\n\t\t\t\tfunction = \"pci-func\";\n\t\t\t};\n\t\t};\n\n\t\tuartlite_pins: uartlite {\n\t\t\tuart {\n\t\t\t\tgroups = \"uartlite\";\n\t\t\t\tfunction = \"uartlite\";\n\t\t\t};\n\t\t};\n\n\t\tpci_pins: pci {\n\t\t\tpci {\n\t\t\t\tgroups = \"pci\";\n\t\t\t\tfunction = \"pci-fnc\";\n\t\t\t};\n\t\t};\n\t};\n\n\tethernet: ethernet@10100000 {\n\t\tcompatible = \"ralink,rt3883-eth\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0x10100000 0x10000>;\n\n\t\tresets = <&rstctrl 21>;\n\t\treset-names = \"fe\";\n\n\t\tinterrupt-parent = <&cpuintc>;\n\t\tinterrupts = <5>;\n\n\t\tport@0 {\n\t\t\tcompatible = \"ralink,rt3883-port\", \"mediatek,eth-port\";\n\t\t\treg = <0>;\n\t\t};\n\n\t\tmdio-bus {\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\t};\n\n\trstctrl: rstctrl {\n\t\tcompatible = \"ralink,rt3883-reset\", \"ralink,rt2880-reset\";\n\t\t#reset-cells = <1>;\n\t};\n\n\tclkctrl: clkctrl {\n\t\tcompatible = \"ralink,rt2880-clock\";\n\t\t#clock-cells = <1>;\n\t};\n\n\tpci: pci@10140000 {\n\t\tcompatible = \"ralink,rt3883-pci\";\n\t\treg = <0x10140000 0x20000>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tranges; /* direct mapping */\n\n\t\tpinctrl-names = \"default\";\n\t\tpinctrl-0 = <&pci_pins>;\n\n\t\tstatus = \"disabled\";\n\n\t\tpciintc: interrupt-controller {\n\t\t\tinterrupt-controller;\n\t\t\t#address-cells = <0>;\n\t\t\t#interrupt-cells = <1>;\n\n\t\t\tinterrupt-parent = <&cpuintc>;\n\t\t\tinterrupts = <4>;\n\t\t};\n\n\t\tpci@0 {\n\t\t\t#address-cells = <3>;\n\t\t\t#size-cells = <2>;\n\t\t\t#interrupt-cells = <1>;\n\n\t\t\tdevice_type = \"pci\";\n\n\t\t\tbus-range = <0 255>;\n\t\t\tranges = <\n\t\t\t\t0x02000000 0 0x00000000 0x20000000 0 0x10000000 /* pci memory */\n\t\t\t\t0x01000000 0 0x00000000 0x10160000 0 0x00010000 /* io space */\n\t\t\t>;\n\n\t\t\tinterrupt-map-mask = <0xf800 0 0 7>;\n\t\t\tinterrupt-map = <\n\t\t\t\t/* IDSEL 17 */\n\t\t\t\t0x8800 0 0 1 &pciintc 18\n\t\t\t\t0x8800 0 0 2 &pciintc 18\n\t\t\t\t0x8800 0 0 3 &pciintc 18\n\t\t\t\t0x8800 0 0 4 &pciintc 18\n\t\t\t\t/* IDSEL 18 */\n\t\t\t\t0x9000 0 0 1 &pciintc 19\n\t\t\t\t0x9000 0 0 2 &pciintc 19\n\t\t\t\t0x9000 0 0 3 &pciintc 19\n\t\t\t\t0x9000 0 0 4 &pciintc 19\n\t\t\t>;\n\n\t\t\tpci1: pci@1 {\n\t\t\t\treg = <0x0800 0 0 0 0>;\n\t\t\t\tdevice_type = \"pci\";\n\t\t\t\t#interrupt-cells = <1>;\n\t\t\t\t#address-cells = <3>;\n\t\t\t\t#size-cells = <2>;\n\n\t\t\t\tstatus = \"disabled\";\n\n\t\t\t\tinterrupt-map-mask = <0x0 0 0 0>;\n\t\t\t\tinterrupt-map = <0x0 0 0 0 &pciintc 20>;\n\n\t\t\t\tbus-range = <1 255>;\n\t\t\t\tranges;\n\t\t\t};\n\n\t\t\tpci17: pci@11,0 {\n\t\t\t\treg = <0x8800 0 0 0 0>;\n\t\t\t\t#interrupt-cells = <1>;\n\t\t\t\t#address-cells = <3>;\n\t\t\t\t#size-cells = <2>;\n\n\t\t\t\tstatus = \"disabled\";\n\t\t\t};\n\n\t\t\tpci18: pci@12,0 {\n\t\t\t\treg = <0x9000 0 0 0 0>;\n\t\t\t\t#interrupt-cells = <1>;\n\t\t\t\t#address-cells = <3>;\n\t\t\t\t#size-cells = <2>;\n\n\t\t\t\tstatus = \"disabled\";\n\t\t\t};\n\t\t};\n\t};\n\n\tusbphy: usbphy {\n\t\tcompatible = \"ralink,rt3352-usbphy\";\n\t\t#phy-cells = <0>;\n\n\t\tralink,sysctl = <&sysc>;\n\t\tresets = <&rstctrl 22 &rstctrl 25>;\n\t\treset-names = \"host\", \"device\";\n\t\tclocks = <&clkctrl 22 &clkctrl 25>;\n\t\tclock-names = \"host\", \"device\";\n\t};\n\n\twmac: wmac@10180000 {\n\t\tcompatible = \"ralink,rt3883-wmac\", \"ralink,rt2880-wmac\";\n\t\treg = <0x10180000 0x40000>;\n\n\t\tinterrupt-parent = <&cpuintc>;\n\t\tinterrupts = <6>;\n\n\t\tralink,eeprom = \"soc_wmac.eeprom\";\n\t};\n\n\tehci: ehci@101c0000 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tcompatible = \"generic-ehci\";\n\t\treg = <0x101c0000 0x1000>;\n\n\t\tphys = <&usbphy>;\n\t\tphy-names = \"usb\";\n\n\t\tinterrupt-parent = <&intc>;\n\t\tinterrupts = <18>;\n\n\t\tstatus = \"disabled\";\n\n\t\tehci_port1: port@1 {\n\t\t\treg = <1>;\n\t\t\t#trigger-source-cells = <0>;\n\t\t};\n\t};\n\n\tohci: ohci@101c1000 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tcompatible = \"generic-ohci\";\n\t\treg = <0x101c1000 0x1000>;\n\n\t\tphys = <&usbphy>;\n\t\tphy-names = \"usb\";\n\n\t\tinterrupt-parent = <&intc>;\n\t\tinterrupts = <18>;\n\n\t\tstatus = \"disabled\";\n\n\t\tohci_port1: port@1 {\n\t\t\treg = <1>;\n\t\t\t#trigger-source-cells = <0>;\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt3883_belkin_f9k1109v1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"rt3883_belkin_f9k110x.dtsi\"\n\n/ {\n\tcompatible = \"belkin,f9k1109v1\", \"ralink,rt3883-soc\";\n\tmodel = \"Belkin F9K1109 Version 1.0\";\n\n\taliases {\n\t\tled-boot = &led_status_amber;\n\t\tled-failsafe = &led_status_amber;\n\t\tled-running = &led_status_blue;\n\t\tled-upgrade = &led_status_amber;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_status_amber: internet_amber {\n\t\t\tlabel = \"amber:internet\";\n\t\t\tgpios = <&gpio0 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_status_blue: internet_blue {\n\t\t\tlabel = \"blue:internet\";\n\t\t\tgpios = <&gpio0 12 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tusb1 {\n\t\t\tlabel = \"green:usb1\";\n\t\t\tgpios = <&gpio0 9 GPIO_ACTIVE_LOW>;\n\t\t\ttrigger-sources = <&ohci_port1>, <&ehci_port1>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\n\t\tusb2 {\n\t\t\tlabel = \"green:usb2\";\n\t\t\tgpios = <&gpio0 14 GPIO_ACTIVE_LOW>;\n\t\t\ttrigger-sources = <&ohci_port2>, <&ehci_port2>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\n\t\twps_amber {\n\t\t\tlabel = \"amber:wps\";\n\t\t\tgpios = <&gpio0 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twps_blue {\n\t\t\tlabel = \"blue:wps\";\n\t\t\tgpios = <&gpio0 10 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <100>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 25 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio0 26 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n};\n\n&ehci {\n\tehci_port2: port@2 {\n\t\treg = <2>;\n\t\t#trigger-source-cells = <0>;\n\t};\n};\n\n&ohci {\n\tohci_port2: port@2 {\n\t\treg = <2>;\n\t\t#trigger-source-cells = <0>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt3883_belkin_f9k110x.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"rt3883.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"ralink,rt3883-soc\";\n\n\trtl8367b {\n\t\tcompatible = \"realtek,rtl8367b\";\n\t\tgpio-sda = <&gpio0 1 GPIO_ACTIVE_HIGH>;\n\t\tgpio-sck = <&gpio0 2 GPIO_ACTIVE_HIGH>;\n\t\trealtek,extif1 = <1 0 1 1 1 1 1 1 2>;\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <25000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"uboot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"uboot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x7a0000>;\n\t\t\t};\n\n\t\t\tpartition@7f0000 {\n\t\t\t\tlabel = \"user-cfg\";\n\t\t\t\treg = <0x7f0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&ethernet {\n\tport@0 {\n\t\tmediatek,fixed-link = <1000 1 1 1>;\n\t\tphy-mode = \"rgmii\";\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"jtag\", \"uartf\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&wmac {\n\tstatus = \"okay\";\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&pci {\n\tstatus = \"okay\";\n};\n\n&pci1 {\n\tstatus = \"okay\";\n\n\twifi@1,0 {\n\t\tcompatible = \"pci1814,3091\";\n\t\treg = <0x10000 0 0 0 0>;\n\t\tralink,5ghz = <0>;\n\t\tralink,mtd-eeprom = <&factory 0x8000>;\n\t};\n};\n\n&ehci {\n\tstatus = \"okay\";\n};\n\n&ohci {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt3883_sitecom_wlr-6000.dts",
    "content": "#include \"rt3883.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"sitecom,wlr-6000\", \"ralink,rt3883-soc\";\n\tmodel = \"Sitecom WLR-6000\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio1 2 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"red:power\";\n\t\t\tgpios = <&gpio0 1 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tops {\n\t\t\tlabel = \"white:ops\";\n\t\t\tgpios = <&gpio0 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tgpio_export {\n\t\tcompatible = \"gpio-export\";\n\t\t#size-cells = <0>;\n\n\t\tusb {\n\t\t\tgpio-export,name = \"usb\";\n\t\t\tgpio-export,output = <1>;\n\t\t\tgpios = <&gpio0 9 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&gpio1 {\n\tstatus = \"okay\";\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"jtag\", \"uartf\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tstatus = \"okay\";\n\tnvmem-cells = <&macaddr_factory_8004>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <1>;\n\n\tport@0 {\n\t\tphy-handle = <&phy0>;\n\t\tphy-mode = \"rgmii\";\n\t};\n\n\tmdio-bus {\n\t\tstatus = \"okay\";\n\n\t\tphy0: ethernet-phy@0 {\n\t\t\treg = <0>;\n\t\t\tphy-mode = \"rgmii\";\n\n\t\t\tqca,ar8327-initvals = <\n\t\t\t\t0x04 0x07600000 /* PORT0 PAD MODE CTRL */\n\t\t\t\t0x0c 0x07600000 /* PORT6 PAD MODE CTRL */\n\t\t\t\t0x10 0x40000000 /* Power-on Strapping: 176-pin interface configuration */\n\t\t\t\t0x50 0xc437c437 /* LED Control Register 0 */\n\t\t\t\t0x54 0xc337c337 /* LED Control Register 1 */\n\t\t\t\t0x58 0x00000000 /* LED Control Register 2 */\n\t\t\t\t0x5c 0x03ffff00 /* LED Control Register 3 */\n\t\t\t\t0x7c 0x0000007e /* PORT0_STATUS */\n\t\t\t\t0x94 0x0000007e /* PORT6 STATUS */\n\t\t\t>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <8600000>;\n\t\tm25p,fast-read;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x713000>;\n\t\t\t};\n\n\t\t\tpartition@763000 {\n\t\t\t\tlabel = \"manufacture\";\n\t\t\t\treg = <0x763000 0x7D000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@7E0000 {\n\t\t\t\tlabel = \"backup\";\n\t\t\t\treg = <0x7E0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@7F0000 {\n\t\t\t\tlabel = \"storage\";\n\t\t\t\treg = <0x7F0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&pci {\n\tstatus = \"okay\";\n};\n\n&pci1 {\n\tstatus = \"okay\";\n\n\twifi@0,0 {\n\t\tcompatible = \"pci1814,3091\";\n\t\treg = <0x10000 0 0 0 0>;\n\t\tralink,mtd-eeprom = <&factory 0x8000>;\n\t};\n};\n\n&wmac {\n\tstatus = \"okay\";\n\tralink,2ghz = <0>;\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&ehci {\n\tstatus = \"okay\";\n};\n\n&ohci {\n\tstatus = \"okay\";\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_8004: macaddr@8004 {\n\t\treg = <0x8004 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt3883_trendnet_tew-691gr.dts",
    "content": "#include \"rt3883.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"trendnet,tew-691gr\", \"ralink,rt3883-soc\";\n\tmodel = \"TRENDnet TEW-691GR\";\n\n\taliases {\n\t\tled-boot = &led_wps;\n\t\tled-failsafe = &led_wps;\n\t\tled-running = &led_wps;\n\t\tled-upgrade = &led_wps;\n\t};\n\n\tflash@1c000000 {\n\t\tcompatible = \"cfi-flash\";\n\t\treg = <0x1c000000 0x800000>;\n\t\tbank-width = <2>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\treg = <0x0 0x0030000>;\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\treg = <0x00030000 0x00010000>;\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\treg = <0x00040000 0x00010000>;\n\t\t\t\tlabel = \"factory\";\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\treg = <0x00050000 0x007b0000>;\n\t\t\t\tlabel = \"firmware\";\n\t\t\t};\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <100>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 10 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio1 2 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\n\t\trfkill {\n\t\t\tlabel = \"rfkill\";\n\t\t\tgpios = <&gpio0 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RFKILL>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_wps: wps {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&gpio0 9 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&gpio1 {\n\tstatus = \"okay\";\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"spi\", \"i2c\", \"jtag\", \"uartf\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tport@0 {\n\t\tphy-handle = <&phy0>;\n\t\tphy-mode = \"rgmii\";\n\t};\n\n\tmdio-bus {\n\t\tstatus = \"okay\";\n\n\t\tphy0: ethernet-phy@0 {\n\t\t\treg = <0>;\n\t\t\tphy-mode = \"rgmii\";\n\t\t};\n\t};\n};\n\n&wmac {\n\tstatus = \"okay\";\n\tralink,mtd-eeprom = <&factory 0x0>;\n\tralink,5ghz = <0>;\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <1>;\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt3883_trendnet_tew-692gr.dts",
    "content": "#include \"rt3883.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"trendnet,tew-692gr\", \"ralink,rt3883-soc\";\n\tmodel = \"TRENDnet TEW-692GR\";\n\n\taliases {\n\t\tled-boot = &led_wps_green;\n\t\tled-failsafe = &led_wps_green;\n\t\tled-running = &led_wps_green;\n\t\tled-upgrade = &led_wps_green;\n\t};\n\n\tflash@1c000000 {\n\t\tcompatible = \"cfi-flash\";\n\t\treg = <0x1c000000 0x800000>;\n\t\tbank-width = <2>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\treg = <0x0 0x0030000>;\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\treg = <0x00030000 0x00010000>;\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\treg = <0x00040000 0x00010000>;\n\t\t\t\tlabel = \"factory\";\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\treg = <0x00050000 0x007b0000>;\n\t\t\t\tlabel = \"firmware\";\n\t\t\t};\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <100>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 10 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio1 2 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twps {\n\t\t\tlabel = \"orange:wps\";\n\t\t\tgpios = <&gpio0 9 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_wps_green: wps2 {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&gpio1 4 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&gpio1 {\n\tstatus = \"okay\";\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"spi\", \"i2c\", \"jtag\", \"uartf\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tstatus = \"okay\";\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n\n\tport@0 {\n\t\tphy-handle = <&phy0>;\n\t\tphy-mode = \"rgmii\";\n\t};\n\n\tmdio-bus {\n\t\tstatus = \"okay\";\n\n\t\tphy0: ethernet-phy@0 {\n\t\t\treg = <0>;\n\t\t\tphy-mode = \"rgmii\";\n\n\t\t\tqca,ar8327-initvals = <\n\t\t\t\t0x04 0x07600000 /* PORT0 PAD MODE CTRL */\n\t\t\t\t0x0c 0x07600000 /* PORT6 PAD MODE CTRL */\n\t\t\t\t0x10 0x40000000 /* Power-on Strapping: 176-pin interface configuration */\n\t\t\t\t0x50 0xc437c437 /* LED Control Register 0 */\n\t\t\t\t0x54 0xc337c337 /* LED Control Register 1 */\n\t\t\t\t0x58 0x00000000 /* LED Control Register 2 */\n\t\t\t\t0x5c 0x03ffff00 /* LED Control Register 3 */\n\t\t\t\t0x7c 0x0000007e /* PORT0_STATUS */\n\t\t\t\t0x94 0x0000007e /* PORT6 STATUS */\n\t\t\t>;\n\t\t};\n\t};\n};\n\n&pci {\n\tstatus = \"okay\";\n};\n\n&pci1 {\n\tstatus = \"okay\";\n\n\twifi@0,0 {\n\t\tcompatible = \"pci0,0\";\n\t\treg = < 0x10000 0 0 0 0 >;\n\t\tralink,2ghz = <0>;\n\t};\n};\n\n&wmac {\n\tstatus = \"okay\";\n\tralink,mtd-eeprom = <&factory 0x0>;\n\tralink,5ghz = <0>;\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n\tmac-address-increment = <3>;\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt5350.dtsi",
    "content": "/dts-v1/;\n\n/ {\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\tcompatible = \"ralink,rt5350-soc\";\n\n\taliases {\n\t\tspi0 = &spi0;\n\t\tspi1 = &spi1;\n\t\tserial0 = &uartlite;\n\t};\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcpu@0 {\n\t\t\tcompatible = \"mips,mips24KEc\";\n\t\t\treg = <0>;\n\t\t};\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,57600\";\n\t};\n\n\tcpuintc: cpuintc {\n\t\t#address-cells = <0>;\n\t\t#interrupt-cells = <1>;\n\t\tinterrupt-controller;\n\t\tcompatible = \"mti,cpu-interrupt-controller\";\n\t};\n\n\tpalmbus: palmbus@10000000 {\n\t\tcompatible = \"palmbus\";\n\t\treg = <0x10000000 0x200000>;\n\t\tranges = <0x0 0x10000000 0x1FFFFF>;\n\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\n\t\tsysc: sysc@0 {\n\t\t\tcompatible = \"ralink,rt5350-sysc\", \"ralink,rt3050-sysc\", \"syscon\";\n\t\t\treg = <0x0 0x100>;\n\t\t};\n\n\t\ttimer: timer@100 {\n\t\t\tcompatible = \"ralink,rt5350-timer\", \"ralink,rt2880-timer\";\n\t\t\treg = <0x100 0x20>;\n\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <1>;\n\t\t};\n\n\t\twatchdog: watchdog@120 {\n\t\t\tcompatible = \"ralink,rt5350-wdt\", \"ralink,rt2880-wdt\";\n\t\t\treg = <0x120 0x10>;\n\n\t\t\tresets = <&rstctrl 8>;\n\t\t\treset-names = \"wdt\";\n\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <1>;\n\t\t};\n\n\t\tintc: intc@200 {\n\t\t\tcompatible = \"ralink,rt5350-intc\", \"ralink,rt2880-intc\";\n\t\t\treg = <0x200 0x100>;\n\n\t\t\tresets = <&rstctrl 19>;\n\t\t\treset-names = \"intc\";\n\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <1>;\n\n\t\t\tinterrupt-parent = <&cpuintc>;\n\t\t\tinterrupts = <2>;\n\t\t};\n\n\t\tmemc: memc@300 {\n\t\t\tcompatible = \"ralink,rt5350-memc\", \"ralink,rt3050-memc\";\n\t\t\treg = <0x300 0x100>;\n\n\t\t\tresets = <&rstctrl 20>;\n\t\t\treset-names = \"mc\";\n\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <3>;\n\t\t};\n\n\t\tuart: uart@500 {\n\t\t\tcompatible = \"ralink,rt5350-uart\", \"ralink,rt2880-uart\", \"ns16550a\";\n\t\t\treg = <0x500 0x100>;\n\n\t\t\tresets = <&rstctrl 12>;\n\t\t\treset-names = \"uart\";\n\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <5>;\n\n\t\t\treg-shift = <2>;\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tgpio0: gpio@600 {\n\t\t\tcompatible = \"ralink,rt5350-gpio\", \"ralink,rt2880-gpio\";\n\t\t\treg = <0x600 0x34>;\n\n\t\t\tresets = <&rstctrl 13>;\n\t\t\treset-names = \"pio\";\n\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <6>;\n\n\t\t\tgpio-controller;\n\t\t\t#gpio-cells = <2>;\n\n\t\t\tngpios = <22>;\n\t\t\tralink,gpio-base = <0>;\n\t\t\tralink,register-map = [ 00 04 08 0c\n\t\t\t\t\t\t20 24 28 2c\n\t\t\t\t\t\t30 34 ];\n\t\t};\n\n\t\tgpio1: gpio@660 {\n\t\t\tcompatible = \"ralink,rt5350-gpio\", \"ralink,rt2880-gpio\";\n\t\t\treg = <0x660 0x24>;\n\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <6>;\n\n\t\t\tgpio-controller;\n\t\t\t#gpio-cells = <2>;\n\n\t\t\tngpios = <6>;\n\t\t\tralink,gpio-base = <22>;\n\t\t\tralink,register-map = [ 00 04 08 0c\n\t\t\t\t\t\t10 14 18 1c\n\t\t\t\t\t\t20 24 ];\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\ti2c: i2c@900 {\n\t\t\tcompatible = \"ralink,rt2880-i2c\";\n\t\t\treg = <0x900 0x100>;\n\n\t\t\tresets = <&rstctrl 16>;\n\t\t\treset-names = \"i2c\";\n\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\n\t\t\tpinctrl-names = \"default\";\n\t\t\tpinctrl-0 = <&i2c_pins>;\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\ti2s: i2s@a00 {\n\t\t\tcompatible = \"ralink,rt3352-i2s\";\n\t\t\treg = <0xa00 0x100>;\n\n\t\t\tresets = <&rstctrl 17>;\n\t\t\treset-names = \"i2s\";\n\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <10>;\n\n\t\t\ttxdma-req = <2>;\n\t\t\trxdma-req = <3>;\n\n\t\t\tdmas = <&gdma 4>,\n\t\t\t\t<&gdma 6>;\n\t\t\tdma-names = \"tx\", \"rx\";\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tspi0: spi@b00 {\n\t\t\tcompatible = \"ralink,rt5350-spi\", \"ralink,rt2880-spi\";\n\t\t\treg = <0xb00 0x40>;\n\n\t\t\tresets = <&rstctrl 18>;\n\t\t\treset-names = \"spi\";\n\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\n\t\t\tpinctrl-names = \"default\";\n\t\t\tpinctrl-0 = <&spi_pins>;\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tspi1: spi@b40 {\n\t\t\tcompatible = \"ralink,rt5350-spi\", \"ralink,rt2880-spi\";\n\t\t\treg = <0xb40 0x60>;\n\n\t\t\tresets = <&rstctrl 18>;\n\t\t\treset-names = \"spi\";\n\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\n\t\t\tpinctrl-names = \"default\";\n\t\t\tpinctrl-0 = <&spi_cs1>;\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tuartlite: uartlite@c00 {\n\t\t\tcompatible = \"ralink,rt5350-uart\", \"ralink,rt2880-uart\", \"ns16550a\";\n\t\t\treg = <0xc00 0x100>;\n\n\t\t\tresets = <&rstctrl 19>;\n\t\t\treset-names = \"uartl\";\n\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <12>;\n\n\t\t\tpinctrl-names = \"default\";\n\t\t\tpinctrl-0 = <&uartlite_pins>;\n\n\t\t\treg-shift = <2>;\n\t\t};\n\n\t\tsystick: systick@d00 {\n\t\t\tcompatible = \"ralink,rt5350-systick\", \"ralink,cevt-systick\";\n\t\t\treg = <0xd00 0x10>;\n\n\t\t\tinterrupt-parent = <&cpuintc>;\n\t\t\tinterrupts = <7>;\n\t\t};\n\n\t\tpcm: pcm@2000 {\n\t\t\tcompatible = \"ralink,rt5350-pcm\";\n\t\t\treg = <0x2000 0x800>;\n\n\t\t\tresets = <&rstctrl 11>;\n\t\t\treset-names = \"pcm\";\n\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <4>;\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tgdma: gdma@2800 {\n\t\t\tcompatible = \"ralink,rt3883-gdma\";\n\t\t\treg = <0x2800 0x800>;\n\n\t\t\tresets = <&rstctrl 14>;\n\t\t\treset-names = \"dma\";\n\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <7>;\n\n\t\t\t#dma-cells = <1>;\n\t\t\t#dma-channels = <16>;\n\t\t\t#dma-requests = <16>;\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\t};\n\n\tpinctrl: pinctrl {\n\t\tcompatible = \"ralink,rt2880-pinmux\";\n\n\t\tpinctrl-names = \"default\";\n\t\tpinctrl-0 = <&state_default>;\n\n\t\tstate_default: pinctrl0 {\n\t\t};\n\n\t\ti2c_pins: i2c_pins {\n\t\t\ti2c_pins {\n\t\t\t\tgroups = \"i2c\";\n\t\t\t\tfunction = \"i2c\";\n\t\t\t};\n\t\t};\n\n\t\tspi_pins: spi_pins {\n\t\t\tspi_pins {\n\t\t\t\tgroups = \"spi\";\n\t\t\t\tfunction = \"spi\";\n\t\t\t};\n\t\t};\n\n\t\tphy_led_pins: phy_led {\n\t\t\tphy_led {\n\t\t\t\tgroups = \"led\";\n\t\t\t\tfunction = \"led\";\n\t\t\t};\n\t\t};\n\n\t\tuartlite_pins: uartlite {\n\t\t\tuart {\n\t\t\t\tgroups = \"uartlite\";\n\t\t\t\tfunction = \"uartlite\";\n\t\t\t};\n\t\t};\n\n\t\tuartf_pins: uartf {\n\t\t\tuartf {\n\t\t\t\tgroups = \"uartf\";\n\t\t\t\tfunction = \"uartf\";\n\t\t\t};\n\t\t};\n\n\t\tspi_cs1: spi1 {\n\t\t\tspi1 {\n\t\t\t\tgroups = \"spi_cs1\";\n\t\t\t\tfunction = \"spi_cs1\";\n\t\t\t};\n\t\t};\n\t};\n\n\trstctrl: rstctrl {\n\t\tcompatible = \"ralink,rt5350-reset\", \"ralink,rt2880-reset\";\n\t\t#reset-cells = <1>;\n\t};\n\n\tclkctrl: clkctrl {\n\t\tcompatible = \"ralink,rt2880-clock\";\n\t\t#clock-cells = <1>;\n\t};\n\n\tusbphy: usbphy {\n\t\tcompatible = \"ralink,rt3352-usbphy\";\n\t\t#phy-cells = <0>;\n\n\t\tralink,sysctl = <&sysc>;\n\t\tresets = <&rstctrl 22 &rstctrl 25>;\n\t\treset-names = \"host\", \"device\";\n\t\tclocks = <&clkctrl 18>;\n\t\tclock-names = \"host\";\n\t};\n\n\tethernet: ethernet@10100000 {\n\t\tcompatible = \"ralink,rt5350-eth\";\n\t\treg = <0x10100000 0x10000>;\n\n\t\tresets = <&rstctrl 21>;\n\t\treset-names = \"fe\";\n\n\t\tinterrupt-parent = <&cpuintc>;\n\t\tinterrupts = <5>;\n\n\t\tmediatek,switch = <&esw>;\n\t};\n\n\tesw: esw@10110000 {\n\t\tcompatible = \"ralink,rt5350-esw\", \"ralink,rt3050-esw\";\n\t\treg = <0x10110000 0x8000>;\n\n\t\tresets = <&rstctrl 23 &rstctrl 24>;\n\t\treset-names = \"esw\", \"ephy\";\n\n\t\tinterrupt-parent = <&intc>;\n\t\tinterrupts = <17>;\n\t};\n\n\twmac: wmac@10180000 {\n\t\tcompatible = \"ralink,rt5350-wmac\", \"ralink,rt2880-wmac\";\n\t\treg = <0x10180000 0x40000>;\n\n\t\tinterrupt-parent = <&cpuintc>;\n\t\tinterrupts = <6>;\n\n\t\tralink,eeprom = \"soc_wmac.eeprom\";\n\t};\n\n\tehci: ehci@101c0000 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tcompatible = \"generic-ehci\";\n\t\treg = <0x101c0000 0x1000>;\n\n\t\tphys = <&usbphy>;\n\t\tphy-names = \"usb\";\n\n\t\tinterrupt-parent = <&intc>;\n\t\tinterrupts = <18>;\n\n\t\tehci_port1: port@1 {\n\t\t\treg = <1>;\n\t\t\t#trigger-source-cells = <0>;\n\t\t};\n\t};\n\n\tohci: ohci@101c1000 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tcompatible = \"generic-ohci\";\n\t\treg = <0x101c1000 0x1000>;\n\n\t\tphys = <&usbphy>;\n\t\tphy-names = \"usb\";\n\n\t\tinterrupt-parent = <&intc>;\n\t\tinterrupts = <18>;\n\n\t\tohci_port1: port@1 {\n\t\t\treg = <1>;\n\t\t\t#trigger-source-cells = <0>;\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt5350_7links_px-4885-4m.dts",
    "content": "#include \"rt5350_7links_px-4885.dtsi\"\n\n/ {\n\tcompatible = \"7links,px-4885-4m\", \"7links,px-4885\", \"ralink,rt5350-soc\";\n\tmodel = \"7Links PX-4885 (4M)\";\n};\n\n&firmware {\n\treg = <0x50000 0x3b0000>;\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt5350_7links_px-4885-8m.dts",
    "content": "#include \"rt5350_7links_px-4885.dtsi\"\n\n/ {\n\tcompatible = \"7links,px-4885-8m\", \"7links,px-4885\", \"ralink,rt5350-soc\";\n\tmodel = \"7Links PX-4885 (8M)\";\n};\n\n&firmware {\n\treg = <0x50000 0x7b0000>;\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt5350_7links_px-4885.dtsi",
    "content": "#include \"rt5350.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"7links,px-4885\", \"ralink,rt5350-soc\";\n\n\taliases {\n\t\tled-boot = &led_wifi;\n\t\tled-failsafe = &led_wifi;\n\t\tled-running = &led_wifi;\n\t\tled-upgrade = &led_wifi;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 10 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_wifi: wifi {\n\t\t\tlabel = \"orange:wifi\";\n\t\t\tgpios = <&gpio0 18 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tstorage {\n\t\t\tlabel = \"blue:storage\";\n\t\t\tgpios = <&gpio0 19 GPIO_ACTIVE_LOW>;\n\t\t\ttrigger-sources = <&ohci_port1>, <&ehci_port1>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x20000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@20000 {\n\t\t\t\tlabel = \"devdata\";\n\t\t\t\treg = <0x20000 0x20000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tdevconf: partition@40000 {\n\t\t\t\tlabel = \"devconf\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfirmware: partition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\t/* reg property is set based on flash size in DTS files */\n\t\t\t};\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"jtag\", \"uartf\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_devconf_28>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&esw {\n\tmediatek,portmap = <0x3f>;\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&devconf 0x0>;\n};\n\n&devconf {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_devconf_28: macaddr@28 {\n\t\treg = <0x28 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt5350_airlive_air3gii.dts",
    "content": "#include \"rt5350.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"airlive,air3gii\", \"ralink,rt5350-soc\";\n\tmodel = \"AirLive Air3GII\";\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twlan {\n\t\t\tlabel = \"green:wlan\";\n\t\t\tgpios = <&gpio0 8 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tmobile {\n\t\t\tlabel = \"green:mobile\";\n\t\t\tgpios = <&gpio0 9 GPIO_ACTIVE_LOW>;\n\t\t\ttrigger-sources = <&ohci_port1>, <&ehci_port1>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <20>;\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio0 7 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x3b0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"jtag\", \"uartf\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&esw {\n\tmediatek,portmap = <0x2f>;\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt5350_allnet_all5003.dts",
    "content": "#include \"rt5350.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"allnet,all5003\", \"ralink,rt5350-soc\";\n\tmodel = \"Allnet ALL5003\";\n\n\ti2c-gpio {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tcompatible = \"i2c-gpio\";\n\t\tgpios = <&gpio0 1 GPIO_ACTIVE_HIGH &gpio0 2 GPIO_ACTIVE_HIGH>;\n\t\ti2c-gpio,delay-us = <10>;\n\n\t\tpcf0: iexp@38 {\n\t\t\t#gpio-cells = <2>;\n\t\t\tcompatible = \"inxp,pcf8574a\";\n\t\t\treg = <0x38>;\n\t\t\tgpio-controller;\n\t\t};\n\n\t\thwmon@4b {\n\t\t\tcompatible = \"national,lm92\";\n\t\t\treg = <0x4b>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tld1 {\n\t\t\tlabel = \"green:ld1\";\n\t\t\tgpios = <&pcf0 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tld2 {\n\t\t\tlabel = \"green:ld2\";\n\t\t\tgpios = <&pcf0 1 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x1fb0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"jtag\", \"uartf\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_28>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&esw {\n\tmediatek,portmap = <0x3f>;\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_28: macaddr@28 {\n\t\treg = <0x28 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt5350_asiarf_awm002-evb-4m.dts",
    "content": "#include \"rt5350_asiarf_awm002-evb.dtsi\"\n\n/ {\n\tcompatible = \"asiarf,awm002-evb-4m\", \"ralink,rt5350-soc\";\n\tmodel = \"AsiaRF AWM002 EVB (4M)\";\n};\n\n&firmware {\n\treg = <0x50000 0x3b0000>;\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt5350_asiarf_awm002-evb-8m.dts",
    "content": "#include \"rt5350_asiarf_awm002-evb.dtsi\"\n\n/ {\n\tcompatible = \"asiarf,awm002-evb-8m\", \"ralink,rt5350-soc\";\n\tmodel = \"AsiaRF AWM002 EVB (8M)\";\n};\n\n&firmware {\n\treg = <0x50000 0x7b0000>;\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt5350_asiarf_awm002-evb.dtsi",
    "content": "#include \"rt5350.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"asiarf,awm002-evb\", \"ralink,rt5350-soc\";\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\ttx {\n\t\t\tlabel = \"green:tx\";\n\t\t\tgpios = <&gpio0 15 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\trx {\n\t\t\tlabel = \"green:rx\";\n\t\t\tgpios = <&gpio0 16 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&gpio0 21 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <20>;\n\n\t\treset_wps {\n\t\t\tlabel = \"reset_wps\";\n\t\t\tgpios = <&gpio0 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\tmode {\n\t\t\tlabel = \"mode\";\n\t\t\tgpios = <&gpio0 20 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_0>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\treg = <0>;\n\t\tcompatible = \"jedec,spi-nor\";\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfirmware: partition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\t/* reg property is set based on flash size in DTS files */\n\t\t\t};\n\t\t};\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_28>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"jtag\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&esw {\n\tmediatek,portmap = <0x3f>;\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_28: macaddr@28 {\n\t\treg = <0x28 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt5350_belkin_f7c027.dts",
    "content": "#include \"rt5350.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"belkin,f7c027\", \"ralink,rt5350-soc\";\n\tmodel = \"Belkin F7C027\";\n\n\taliases {\n\t\tled-boot = &led_status_orange;\n\t\tled-failsafe = &led_status_orange;\n\t\tled-running = &led_status_orange;\n\t\tled-upgrade = &led_status_orange;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tstatus {\n\t\t\tlabel = \"blue:status\";\n\t\t\tgpios = <&gpio0 7 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tpower {\n\t\t\tlabel = \"blue:power\";\n\t\t\tgpios = <&gpio0 9 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_status_orange: orange {\n\t\t\tlabel = \"orange:status\";\n\t\t\tgpios = <&gpio0 11 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\trelay {\n\t\t\tlabel = \"device:relay\";\n\t\t\tgpios = <&gpio0 13 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <20>;\n\n\t\ttop {\n\t\t\tlabel = \"restore\";\n\t\t\tgpios = <&gpio0 10 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\tpower {\n\t\t\tlabel = \"power\";\n\t\t\tgpios = <&gpio0 12 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RFKILL>;\n\t\t};\n\n\t\tsensor {\n\t\t\tlabel = \"sensor\";\n\t\t\tgpios = <&gpio0 14 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_0>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x770000>;\n\t\t\t};\n\n\t\t\tpartition@7c0000 {\n\t\t\t\tlabel = \"firmware2\";\n\t\t\t\treg = <0x7c0000 0x770000>;\n\t\t\t};\n\n\t\t\tpartition@f30000 {\n\t\t\t\tlabel = \"belkin_settings\";\n\t\t\t\treg = <0xf30000 0xa0000>;\n\t\t\t};\n\n\t\t\tpartition@fd0000 {\n\t\t\t\tlabel = \"unknown\";\n\t\t\t\treg = <0xfd0000 0x10000>;\n\t\t\t};\n\n\t\t\tpartition@fe0000 {\n\t\t\t\tlabel = \"nvram\";\n\t\t\t\treg = <0xfe0000 0x10000>;\n\t\t\t};\n\n\t\t\tpartition@ff0000 {\n\t\t\t\tlabel = \"user_factory\";\n\t\t\t\treg = <0xff0000 0x10000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"jtag\", \"uartf\";\n\t\tfunction = \"gpio\";\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt5350_dlink_dcs-930l-b1.dts",
    "content": "#include \"rt5350.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"dlink,dcs-930l-b1\", \"ralink,rt5350-soc\";\n\tmodel = \"D-Link DCS-930L B1\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"red:power\";\n\t\t\tgpios = <&gpio0 17 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"blue:wps\";\n\t\t\tgpios = <&gpio0 19 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio0 20 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x3b0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"jtag\", \"uartf\", \"led\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&esw {\n\tmediatek,portmap = <0x2f>;\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt5350_dlink_dir-300-b7.dts",
    "content": "#include \"rt5350.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"dlink,dir-300-b7\", \"ralink,rt5350-soc\";\n\tmodel = \"D-Link DIR-300 B7\";\n\n\taliases {\n\t\tled-boot = &led_status;\n\t\tled-failsafe = &led_status;\n\t\tled-running = &led_status;\n\t\tled-upgrade = &led_status;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_status: status {\n\t\t\tlabel = \"green:status\";\n\t\t\tgpios = <&gpio0 9 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"blue:wps\";\n\t\t\tgpios = <&gpio0 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 10 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio0 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x7b0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"jtag\", \"uartf\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&esw {\n\tmediatek,portmap = <0x2f>;\n\tmediatek,led_polarity = <0x17>;\n};\n\n&wmac {\n\tstatus = \"okay\";\n\tralink,led-polarity = <1>;\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt5350_dlink_dir-320-b1.dts",
    "content": "#include \"rt5350.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"dlink,dir-320-b1\", \"ralink,rt5350-soc\";\n\tmodel = \"D-Link DIR-320 B1\";\n\n\taliases {\n\t\tled-boot = &led_status;\n\t\tled-failsafe = &led_status;\n\t\tled-running = &led_status;\n\t\tled-upgrade = &led_status;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_status: status {\n\t\t\tlabel = \"green:status\";\n\t\t\tgpios = <&gpio0 9 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tusb {\n\t\t\tlabel = \"green:usb\";\n\t\t\tgpios = <&gpio0 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&gpio0 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 10 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio0 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n\n\tgpio_export {\n\t\tcompatible = \"gpio-export\";\n\t\t#size-cells = <0>;\n\n\t\tusb {\n\t\t\tgpio-export,name = \"usb\";\n\t\t\tgpio-export,output = <1>;\n\t\t\tgpios = <&gpio0 7 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\troot_hub {\n\t\t\tgpio-export,name = \"root_hub\";\n\t\t\tgpio-export,output = <1>;\n\t\t\tgpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x7b0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"jtag\", \"uartf\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&esw {\n\tmediatek,portmap = <0x2f>;\n\tmediatek,led_polarity = <0x17>;\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt5350_dlink_dir-610-a1.dts",
    "content": "#include \"rt5350.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"dlink,dir-610-a1\", \"ralink,rt5350-soc\";\n\tmodel = \"D-Link DIR-610 A1\";\n\n\taliases {\n\t\tled-boot = &led_status;\n\t\tled-failsafe = &led_status;\n\t\tled-running = &led_status;\n\t\tled-upgrade = &led_status;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_status: status {\n\t\t\tlabel = \"green:status\";\n\t\t\tgpios = <&gpio0 9 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&gpio0 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 10 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio0 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tdevdata: partition@30000 {\n\t\t\t\tlabel = \"devdata\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"seama\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x3b0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"jtag\", \"uartf\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_devdata_4004>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&esw {\n\tstatus = \"okay\";\n\tmediatek,portmap = <0x2f>;\n\tmediatek,led_polarity = <0x17>;\n};\n\n&wmac {\n\tstatus = \"okay\";\n\tralink,led-polarity = <1>;\n\tralink,mtd-eeprom = <&devdata 0x4000>;\n};\n\n&devdata {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_devdata_4004: macaddr@4004 {\n\t\treg = <0x4004 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt5350_dlink_dwr-512-b.dts",
    "content": "#include \"rt5350.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"dlink,dwr-512-b\", \"ralink,rt5350-soc\";\n\tmodel = \"D-Link DWR-512 B\";\n\n\taliases {\n\t\tled-boot = &led_status;\n\t\tled-failsafe = &led_status;\n\t\tled-running = &led_status;\n\t\tled-upgrade = &led_status;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <20>;\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio0 7 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 2 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tsms {\n\t\t\tlabel = \"green:sms\";\n\t\t\tgpios = <&gpio0 8 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t\tled_status: status {\n\t\t\tlabel = \"green:status\";\n\t\t\tgpios = <&gpio0 9 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\t2g {\n\t\t\tlabel = \"green:2g\";\n\t\t\tgpios = <&gpio0 17 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\t3g {\n\t\t\tlabel = \"green:3g\";\n\t\t\tgpios = <&gpio0 19 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tsstrengthr {\n\t\t\tlabel = \"red:sigstrength\";\n\t\t\tgpios = <&gpio0 20 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tsstrengthg {\n\t\t\tlabel = \"green:sigstrength\";\n\t\t\tgpios = <&gpio0 21 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tgpio-export {\n\t\tcompatible = \"gpio-export\";\n\t\t#size-cells = <0>;\n\n\t\tslic_int {\n\t\t\tgpio-export,name = \"slic_int\";\n\t\t\tgpios = <&gpio0 1 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tmodem3g_enable {\n\t\t\tgpio-export,name = \"modem3g_enable\";\n\t\t\tgpio-export,output = <1>;\n\t\t\tgpios = <&gpio0 18 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <30000000>;\n\t\tm25p,fast-read;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"jboot\";\n\t\t\t\treg = <0x0 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@10000 {\n\t\t\t\tcompatible = \"amit,jimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x10000 0x7e0000>;\n\t\t\t};\n\n\t\t\tconfig: partition@7f0000 {\n\t\t\t\tlabel = \"config\";\n\t\t\t\treg = <0x7f0000 0x10000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&spi1 {\n\tstatus = \"okay\";\n\n\tspidev@0 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tcompatible = \"siliconlabs,si3210\";\n\n\t\treg = <0>;\n\t\tspi-max-frequency = <1000000>;\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"jtag\", \"uartf\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&esw {\n\tmediatek,portmap = <0x2f>;\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_config_e07e>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&config 0xe08a>;\n\tralink,led-polarity = <1>;\n\tnvmem-cells = <&macaddr_config_e07e>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&config {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_config_e07e: macaddr@e07e {\n\t\treg = <0xe07e 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt5350_easyacc_wizard-8800.dts",
    "content": "#include \"rt5350.dtsi\"\n\n/ {\n\tcompatible = \"easyacc,wizard-8800\", \"ralink,rt5350-soc\";\n\tmodel = \"EASYACC WI-STOR WIZARD 8800\";\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x7b0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"jtag\", \"uartf\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&esw {\n\tmediatek,portmap = <0x2f>;\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt5350_hame_mpr-a1.dts",
    "content": "#include \"rt5350.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"hame,mpr-a1\", \"ralink,rt5350-soc\";\n\tmodel = \"HAME MPR-A1\";\n\n\taliases {\n\t\tled-boot = &led_system;\n\t\tled-failsafe = &led_system;\n\t\tled-running = &led_system;\n\t\tled-upgrade = &led_system;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_system: system {\n\t\t\tlabel = \"blue:system\";\n\t\t\tgpios = <&gpio0 20 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tpower {\n\t\t\tlabel = \"red:power\";\n\t\t\tgpios = <&gpio0 17 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <20>;\n\n\t\twps {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tgpio_export {\n\t\tcompatible = \"gpio-export\";\n\t\t#size-cells = <0>;\n\n\t\tusb {\n\t\t\tgpio-export,name = \"usb\";\n\t\t\tgpio-export,output = <1>;\n\t\t\tgpios = <&gpio0 7 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\troot_hub {\n\t\t\tgpio-export,name = \"root_hub\";\n\t\t\tgpio-export,output = <1>;\n\t\t\tgpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x3b0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"jtag\", \"uartf\", \"led\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&esw {\n\tmediatek,portmap = <0x2f>;\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt5350_hame_mpr-a2.dts",
    "content": "#include \"rt5350.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"hame,mpr-a2\", \"ralink,rt5350-soc\";\n\tmodel = \"HAME MPR-A2\";\n\n\taliases {\n\t\tled-boot = &led_system;\n\t\tled-failsafe = &led_system;\n\t\tled-running = &led_system;\n\t\tled-upgrade = &led_system;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_system: system {\n\t\t\tlabel = \"blue:system\";\n\t\t\tgpios = <&gpio0 20 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tpower {\n\t\t\tlabel = \"red:power\";\n\t\t\tgpios = <&gpio0 17 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <20>;\n\n\t\twps {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tgpio_export {\n\t\tcompatible = \"gpio-export\";\n\t\t#size-cells = <0>;\n\n\t\tusb {\n\t\t\tgpio-export,name = \"usb\";\n\t\t\tgpio-export,output = <1>;\n\t\t\tgpios = <&gpio0 7 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\troot_hub {\n\t\t\tgpio-export,name = \"root_hub\";\n\t\t\tgpio-export,output = <1>;\n\t\t\tgpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x7b0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"jtag\", \"uartf\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&esw {\n\tmediatek,portmap = <0x1>;\n\tmediatek,portdisable = <0x3e>;\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt5350_hilink_hlk-rm04.dts",
    "content": "#include \"rt5350.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"hilink,hlk-rm04\", \"ralink,rt5350-soc\";\n\tmodel = \"HILINK HLK-RM04\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyS1,57600\";\n\t};\n\n\tgpio-export {\n\t\tcompatible = \"gpio-export\";\n\t\t#size-cells = <0>;\n\n\t\t/* I2C */\n\t\tgpio1 {\n\t\t\t/* I2C_I2C_SD */\n\t\t\tgpio-export,name = \"hlk-rm04:gpio0\";\n\t\t\tgpio-export,direction_may_change = <1>;\n\t\t\tgpios = <&gpio0 1 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t\tgpio2 {\n\t\t\t/* I2C_I2C_SCLK */\n\t\t\tgpio-export,name = \"hlk-rm04:gpio1\";\n\t\t\tgpio-export,direction_may_change = <1>;\n\t\t\tgpios = <&gpio0 2 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <20>;\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio0 14 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n};\n\n&uart {\n\tstatus = \"okay\";\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x3b0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"jtag\";\n\t\tfunction = \"gpio\";\n\t};\n\n\tuartf_gpio {\n\t\tgroups = \"uartf\";\n\t\tfunction = \"gpio uartf\";\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt5350_hootoo_ht-tm02.dts",
    "content": "#include \"rt5350.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"hootoo,ht-tm02\", \"ralink,rt5350-soc\";\n\tmodel = \"HooToo HT-TM02\";\n\n\taliases {\n\t\tled-boot = &led_wlan;\n\t\tled-failsafe = &led_wlan;\n\t\tled-running = &led_wlan;\n\t\tled-upgrade = &led_wlan;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_wlan: wlan {\n\t\t\tlabel = \"blue:wlan\";\n\t\t\tgpios = <&gpio0 7 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tlan {\n\t\t\tlabel = \"green:lan\";\n\t\t\tgpios = <&gpio0 12 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 10 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\tmodeswitch {\n\t\t\tlabel = \"modeswitch\";\n\t\t\tgpios = <&gpio0 14 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_0>;\n\t\t\tlinux,input-type = <EV_SW>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x7b0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"jtag\", \"uartf\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_28>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&esw {\n\tmediatek,portmap = <0x10>;\n\tmediatek,portdisable = <0x2f>;\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_28: macaddr@28 {\n\t\treg = <0x28 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt5350_intenso_memory2move.dts",
    "content": "#include \"rt5350.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"intenso,memory2move\", \"ralink,rt5350-soc\";\n\tmodel = \"Intenso Memory 2 Move\";\n\n\taliases {\n\t\tled-boot = &led_wifi;\n\t\tled-failsafe = &led_wifi;\n\t\tled-running = &led_wifi;\n\t\tled-upgrade = &led_wifi;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,57600n8 root=/dev/mtdblock5\";\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_wifi: wifi {\n\t\t\tlabel = \"blue:wifi\";\n\t\t\tgpios = <&gpio0 7 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twan {\n\t\t\tlabel = \"green:wan\";\n\t\t\tgpios = <&gpio0 12 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <20>;\n\n\t\tpower {\n\t\t\tlabel = \"power\";\n\t\t\tgpios = <&gpio0 1 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_POWER>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 10 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"Bootloader\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"Config\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x7b0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"uartf\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_28>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&esw {\n\tmediatek,portmap = <0x2f>;\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_28: macaddr@28 {\n\t\treg = <0x28 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt5350_nexx_wt1520-4m.dts",
    "content": "#include \"rt5350_nexx_wt1520.dtsi\"\n\n/ {\n\tcompatible = \"nexx,wt1520-4m\", \"nexx,wt1520\", \"ralink,rt5350-soc\";\n\tmodel = \"Nexx WT1520 (4M)\";\n};\n\n&firmware {\n\treg = <0x50000 0x3b0000>;\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt5350_nexx_wt1520-8m.dts",
    "content": "#include \"rt5350_nexx_wt1520.dtsi\"\n\n/ {\n\tcompatible = \"nexx,wt1520-8m\", \"nexx,wt1520\", \"ralink,rt5350-soc\";\n\tmodel = \"Nexx WT1520 (8M)\";\n};\n\n&firmware {\n\treg = <0x50000 0x7b0000>;\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt5350_nexx_wt1520.dtsi",
    "content": "#include \"rt5350.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"nexx,wt1520\", \"ralink,rt5350-soc\";\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 10 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfirmware: partition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\t/* reg property is set based on flash size in DTS files */\n\t\t\t};\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"jtag\", \"uartf\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt5350_nixcore_x1-16m.dts",
    "content": "#include \"rt5350_nixcore_x1.dtsi\"\n\n/ {\n\tcompatible = \"nixcore,x1-16m\", \"nixcore,x1\", \"ralink,rt5350-soc\";\n\tmodel = \"NixcoreX1 (16M)\";\n};\n\n&firmware {\n\treg = <0x50000 0xfb0000>;\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt5350_nixcore_x1-8m.dts",
    "content": "#include \"rt5350_nixcore_x1.dtsi\"\n\n/ {\n\tcompatible = \"nixcore,x1-8m\", \"nixcore,x1\", \"ralink,rt5350-soc\";\n\tmodel = \"NixcoreX1 (8M)\";\n};\n\n&firmware {\n\treg = <0x50000 0x7b0000>;\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt5350_nixcore_x1.dtsi",
    "content": "#include \"rt5350.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n\n/ {\n\tcompatible = \"nixcore,x1\", \"ralink,rt5350-soc\";\n\n\tchosen {\n\t\tbootargs = \"console=ttyS1,57600\";\n\t};\n\n\tgpio-export {\n\t\tcompatible = \"gpio-export\";\n\t\t#size-cells = <0>;\n\n\t\tgpio0 {\n\t\t\tgpio-export,name = \"gpio0\";\n\t\t\tgpio-export,direction_may_change = <1>;\n\t\t\tgpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tgpio1 {\n\t\t\tgpio-export,name = \"gpio1\";\n\t\t\tgpio-export,direction_may_change = <1>;\n\t\t\tgpios = <&gpio1 0 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\t/* GPIOs 1-6 are I2C,SPI */\n\t\t/* GPIO 7-14 are uart1 */\n\t\t/* GPIOs 15 & 16 are uart2 */\n\t\t/* JTAG */\n\n\t\tgpio17 {\n\t\t\t/* JTAG_TDO */\n\t\t\tgpio-export,name = \"gpio17\";\n\t\t\tgpio-export,direction_may_change = <1>;\n\t\t\tgpios = <&gpio0 17 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tgpio18 {\n\t\t\t/* JTAG_TDI */\n\t\t\tgpio-export,name = \"gpio18\";\n\t\t\tgpio-export,direction_may_change = <1>;\n\t\t\tgpios = <&gpio0 18 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tgpio19 {\n\t\t\t/* JTAG_TMS */\n\t\t\tgpio-export,name = \"gpio19\";\n\t\t\tgpio-export,direction_may_change = <1>;\n\t\t\tgpios = <&gpio0 19 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tgpio20 {\n\t\t\t/* JTAG_TCLK */\n\t\t\tgpio-export,name = \"gpio20\";\n\t\t\tgpio-export,direction_may_change = <1>;\n\t\t\tgpios = <&gpio0 20 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tgpio21 {\n\t\t\t/* JTAG_TRST_N */\n\t\t\tgpio-export,name = \"gpio21\";\n\t\t\tgpio-export,direction_may_change = <1>;\n\t\t\tgpios = <&gpio0 21 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\t/* ETH LEDs */\n\t\t/*\n\t\tgpio22 {\n\t\t\tgpio-export,name = \"gpio22\";\n\t\t\tgpio-export,direction_may_change = <1>;\n\t\t\tgpios = <&gpio1 0 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tgpio23 {\n\t\t\tgpio-export,name = \"gpio23\";\n\t\t\tgpio-export,direction_may_change = <1>;\n\t\t\tgpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tgpio24 {\n\t\t\tgpio-export,name = \"gpio24\";\n\t\t\tgpio-export,direction_may_change = <1>;\n\t\t\tgpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tgpio25 {\n\t\t\tgpio-export,name = \"gpio25\";\n\t\t\tgpio-export,direction_may_change = <1>;\n\t\t\tgpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\t*/\n\t\tgpio26 {\n\t\t\t/* ETH4_LED */\n\t\t\tgpio-export,name = \"gpio26\";\n\t\t\tgpio-export,direction_may_change = <1>;\n\t\t\tgpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tgpio27 {\n\t\t\t/* spi_cs1 */\n\t\t\tgpio-export,name = \"gpio27\";\n\t\t\tgpio-export,direction_may_change = <1>;\n\t\t\tgpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"uboot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"uboot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfirmware: partition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\t/* reg property is set based on flash size in DTS files */\n\t\t\t};\n\t\t};\n\t};\n};\n\n&gpio1 {\n\tstatus = \"okay\";\n};\n\n&i2c {\n\tstatus = \"okay\";\n};\n\n&uart {\n\tstatus = \"okay\";\n\treset-names = \"gpio uartf\";\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"jtag\", \"led\", \"spi_cs1\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&esw {\n\tmediatek,portmap = <0x17>;\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt5350_olimex_rt5350f-olinuxino-evb.dts",
    "content": "#include \"rt5350_olimex_rt5350f-olinuxino.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n\n/ {\n\tcompatible = \"olimex,rt5350f-olinuxino-evb\", \"ralink,rt5350-soc\";\n\tmodel = \"Olimex RT5350F-OLinuXino-EVB\";\n\n\tgpio_export {\n\t\tcompatible = \"gpio-export\";\n\t\t#size-cells = <0>;\n\n\t\trelay1 {\n\t\t\tgpio-export,name = \"relay1\";\n\t\t\tgpio-export,output = <0>;\n\t\t\tgpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\trelay2 {\n\t\t\tgpio-export,name = \"relay2\";\n\t\t\tgpio-export,output = <0>;\n\t\t\tgpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tbutton {\n\t\t\tgpio-export,name = \"button\";\n\t\t\tgpios = <&gpio0 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt5350_olimex_rt5350f-olinuxino.dts",
    "content": "#include \"rt5350_olimex_rt5350f-olinuxino.dtsi\"\n\n/ {\n\tcompatible = \"olimex,rt5350f-olinuxino\", \"ralink,rt5350-soc\";\n\tmodel = \"Olimex RT5350F-OLinuXino\";\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt5350_olimex_rt5350f-olinuxino.dtsi",
    "content": "#include \"rt5350.dtsi\"\n\n/ {\n\tcompatible = \"olimex,rt5350f-olinuxino\", \"ralink,rt5350-soc\";\n\n\taliases {\n\t\tserial1 = &uart;\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x7b0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"jtag\";\n\t\tfunction = \"gpio\";\n\t};\n\tuartf_gpio {\n\t\tgroups = \"uartf\";\n\t\tfunction = \"gpio uartf\";\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&esw {\n\tmediatek,portmap = <0x2f>;\n\tmediatek,led_polarity = <0x17>;\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n\tralink,led-polarity = <1>;\n};\n\n&i2c {\n\tstatus = \"okay\";\n};\n\n&uart {\n\tstatus = \"okay\";\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt5350_omnima_miniembplug.dts",
    "content": "#include \"rt5350.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"omnima,miniembplug\", \"ralink,rt5350-soc\";\n\tmodel = \"Omnima MiniEMBPlug\";\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\twlan {\n\t\t\tlabel = \"red:wlan\";\n\t\t\tgpios = <&gpio0 9 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tmobile {\n\t\t\tlabel = \"green:mobile\";\n\t\t\tgpios = <&gpio0 13 GPIO_ACTIVE_LOW>;\n\t\t\ttrigger-sources = <&ohci_port1>, <&ehci_port1>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <20>;\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio0 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 10 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\n\t\tmode-one {\n\t\t\tlabel = \"mode1\";\n\t\t\tgpios = <&gpio0 11 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\n\t\tmode-two {\n\t\t\tlabel = \"mode2\";\n\t\t\tgpios = <&gpio0 12 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"jtag\", \"uartf\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x7b0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&esw {\n\tmediatek,portmap = <0x2f>;\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt5350_planex_mzk-dp150n.dts",
    "content": "#include \"rt5350.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"planex,mzk-dp150n\", \"ralink,rt5350-soc\";\n\tmodel = \"Planex MZK-DP150N\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio0 9 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 10 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"uboot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"uboot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x3b0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&spi1 {\n\tspidev@0 {\n\t\tcompatible = \"linux,spidev\";\n\t\tspi-max-frequency = <10000000>;\n\t\treg = <0>;\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"jtag\", \"uartf\", \"led\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&esw {\n\tmediatek,portmap = <0x17>;\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n\tralink,led-polarity = <1>;\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt5350_poray_m3.dts",
    "content": "#include \"rt5350.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"poray,m3\", \"ralink,rt5350-soc\";\n\tmodel = \"Poray M3\";\n\n\taliases {\n\t\tled-boot = &led_status;\n\t\tled-failsafe = &led_status;\n\t\tled-running = &led_status;\n\t\tled-upgrade = &led_status;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_status: status {\n\t\t\tlabel = \"blue:status\";\n\t\t\tgpios = <&gpio0 9 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 10 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\tmode {\n\t\t\tlabel = \"mode\";\n\t\t\tgpios = <&gpio0 17 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_0>;\n\t\t\tlinux,input-type = <EV_SW>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x3b0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"jtag\", \"uartf\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&esw {\n\tmediatek,portmap = <0x2f>;\n\tmediatek,led_polarity = <1>;\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n\tralink,led-polarity = <1>;\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt5350_poray_m4-4m.dts",
    "content": "#include \"rt5350_poray_m4.dtsi\"\n\n/ {\n\tcompatible = \"poray,m4-4m\", \"poray,m4\", \"ralink,rt5350-soc\";\n\tmodel = \"Poray M4 (4M)\";\n};\n\n&firmware {\n\treg = <0x50000 0x3b0000>;\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt5350_poray_m4-8m.dts",
    "content": "#include \"rt5350_poray_m4.dtsi\"\n\n/ {\n\tcompatible = \"poray,m4-8m\", \"poray,m4\", \"ralink,rt5350-soc\";\n\tmodel = \"Poray M4 (8M)\";\n};\n\n&firmware {\n\treg = <0x50000 0x7b0000>;\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt5350_poray_m4.dtsi",
    "content": "#include \"rt5350.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"poray,m4\", \"ralink,rt5350-soc\";\n\n\taliases {\n\t\tled-boot = &led_status;\n\t\tled-failsafe = &led_status;\n\t\tled-running = &led_status;\n\t\tled-upgrade = &led_status;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_status: status {\n\t\t\tlabel = \"blue:status\";\n\t\t\tgpios = <&gpio0 9 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 10 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfirmware: partition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\t/* reg property is set based on flash size in DTS files */\n\t\t\t};\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"jtag\", \"uartf\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&esw {\n\tmediatek,portmap = <0x2f>;\n\tmediatek,led_polarity = <1>;\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n\tralink,led-polarity = <1>;\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt5350_poray_x5.dts",
    "content": "#include \"rt5350.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"poray,x5\", \"ralink,rt5350-soc\";\n\tmodel = \"Poray X5\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio0 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\t20 {\n\t\t\tlabel = \"green:20\";\n\t\t\tgpios = <&gpio0 12 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\t50 {\n\t\t\tlabel = \"green:50\";\n\t\t\tgpios = <&gpio0 11 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\t80 {\n\t\t\tlabel = \"green:80\";\n\t\t\tgpios = <&gpio0 7 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <20>;\n\n\t\tbat {\n\t\t\tlabel = \"bat\";\n\t\t\tgpios = <&gpio0 9 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 10 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\tmode {\n\t\t\tlabel = \"mode\";\n\t\t\tgpios = <&gpio0 14 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_0>;\n\t\t\tlinux,input-type = <EV_SW>;\n\t\t};\n\t};\n\n\tgpio_export {\n\t\tcompatible = \"gpio-export\";\n\t\t#size-cells = <0>;\n\n\t\tusb-mode {\n\t\t\tgpio-export,name = \"usb-mode\";\n\t\t\tgpio-export,output = <0>;\n\t\t\tgpios = <&gpio0 18 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x7b0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"jtag\", \"uartf\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&esw {\n\tmediatek,portmap = <0x2f>;\n\tmediatek,led_polarity = <1>;\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n\tralink,led-polarity = <1>;\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt5350_poray_x8.dts",
    "content": "#include \"rt5350.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"poray,x8\", \"ralink,rt5350-soc\";\n\tmodel = \"Poray X8\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio0 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 10 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x7b0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"jtag\", \"uartf\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&esw {\n\tmediatek,portmap = <0x2f>;\n\tmediatek,led_polarity = <1>;\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n\tralink,led-polarity = <1>;\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt5350_tenda_3g150b.dts",
    "content": "#include \"rt5350.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"tenda,3g150b\", \"ralink,rt5350-soc\";\n\tmodel = \"Tenda 3G150B\";\n\n\taliases {\n\t\tled-boot = &led_ap;\n\t\tled-failsafe = &led_ap;\n\t\tled-running = &led_ap;\n\t\tled-upgrade = &led_ap;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_ap: ap {\n\t\t\tlabel = \"blue:ap\";\n\t\t\tgpios = <&gpio0 7 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\t3g {\n\t\t\tlabel = \"blue:3g\";\n\t\t\tgpios = <&gpio0 14 GPIO_ACTIVE_LOW>;\n\t\t\ttrigger-sources = <&ohci_port1>, <&ehci_port1>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tgpio_export {\n\t\tcompatible = \"gpio-export\";\n\t\t#size-cells = <0>;\n\n\t\tusb {\n\t\t\tgpio-export,name = \"usb\";\n\t\t\tgpio-export,output = <1>;\n\t\t\tgpios = <&gpio0 13 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x3b0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"jtag\", \"uartf\", \"led\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&esw {\n\tmediatek,portmap = <0x2f>;\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n\tralink,led-polarity = <1>;\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt5350_trendnet_tew-714tru.dts",
    "content": "#include \"rt5350.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"trendnet,tew-714tru\", \"ralink,rt5350-soc\";\n\tmodel = \"TRENDnet TEW714TRU\";\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tusb {\n\t\t\tlabel = \"red:usb\";\n\t\t\tgpios = <&gpio0 9 GPIO_ACTIVE_LOW>;\n\t\t\ttrigger-sources = <&ohci_port1>, <&ehci_port1>;\n\t\t\tlinux,default-trigger = \"usbport\";\n\t\t};\n\n\t\twifi {\n\t\t\tlabel = \"green:wifi\";\n\t\t\tgpios = <&gpio0 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 10 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio0 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n\n\tgpio_export {\n\t\tcompatible = \"gpio-export\";\n\t\t#size-cells = <0>;\n\n\t\trepeater {\n\t\t\tgpio-export,name = \"repeater_switch\";\n\t\t\tgpios = <&gpio0 7 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\twisp {\n\t\t\tgpio-export,name = \"wisp_switch\";\n\t\t\tgpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x7b0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"jtag\", \"uartf\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&esw {\n\tmediatek,portmap = <0x1>;\n\tmediatek,portdisable = <0x3e>;\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt5350_unbranded_a5-v11.dts",
    "content": "#include \"rt5350.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"unbranded,a5-v11\", \"ralink,rt5350-soc\";\n\tmodel = \"Unbranded A5-V11\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t\tlabel-mac-device = &ethernet;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tsystem {\n\t\t\tlabel = \"blue:system\";\n\t\t\tgpios = <&gpio0 20 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_power: power {\n\t\t\tlabel = \"red:power\";\n\t\t\tgpios = <&gpio0 17 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tgpio_export {\n\t\tcompatible = \"gpio-export\";\n\t\t#size-cells = <0>;\n\n\t\tusb {\n\t\t\tgpio-export,name = \"usb\";\n\t\t\tgpio-export,output = <1>;\n\t\t\tgpios = <&gpio0 7 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\troot_hub {\n\t\t\tgpio-export,name = \"root_hub\";\n\t\t\tgpio-export,output = <1>;\n\t\t\tgpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x3b0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"jtag\", \"uartf\", \"led\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&esw {\n\tmediatek,portmap = <0x1>;\n\tmediatek,portdisable = <0x3e>;\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt5350_vocore_vocore-16m.dts",
    "content": "#include \"rt5350_vocore_vocore.dtsi\"\n\n/ {\n\tcompatible = \"vocore,vocore-16m\", \"vocore,vocore\", \"ralink,rt5350-soc\";\n\tmodel = \"VoCore (16M)\";\n};\n\n&firmware {\n\treg = <0x50000 0xfb0000>;\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt5350_vocore_vocore-8m.dts",
    "content": "#include \"rt5350_vocore_vocore.dtsi\"\n\n/ {\n\tcompatible = \"vocore,vocore-8m\", \"vocore,vocore\", \"ralink,rt5350-soc\";\n\tmodel = \"VoCore (8M)\";\n};\n\n&firmware {\n\treg = <0x50000 0x7b0000>;\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt5350_vocore_vocore.dtsi",
    "content": "#include \"rt5350.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n\n/ {\n\tcompatible = \"vocore,vocore\", \"ralink,rt5350-soc\";\n\n\taliases {\n\t\tled-boot = &led_status;\n\t\tled-failsafe = &led_status;\n\t\tled-running = &led_status;\n\t\tled-upgrade = &led_status;\n\t\tlabel-mac-device = &ethernet;\n\t};\n\n\tgpio-export {\n\t\tcompatible = \"gpio-export\";\n\t\t#size-cells = <0>;\n\n\t\tgpio0 {\n\t\t\tgpio-export,name = \"gpio0\";\n\t\t\tgpio-export,direction_may_change = <1>;\n\t\t\tgpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\t/* UARTF */\n\t\tgpio7 {\n\t\t\t/* UARTF_RTS_N */\n\t\t\tgpio-export,name = \"gpio7\";\n\t\t\tgpio-export,direction_may_change = <1>;\n\t\t\tgpios = <&gpio0 7 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tgpio8 {\n\t\t\t/* UARTF_TXD */\n\t\t\tgpio-export,name = \"gpio8\";\n\t\t\tgpio-export,direction_may_change = <1>;\n\t\t\tgpios = <&gpio0 8 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tgpio9 {\n\t\t\t/* UARTF_CTS_N */\n\t\t\tgpio-export,name = \"gpio9\";\n\t\t\tgpio-export,direction_may_change = <1>;\n\t\t\tgpios = <&gpio0 9 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tgpio12 {\n\t\t\t/* UARTF_DCD_N */\n\t\t\tgpio-export,name = \"gpio12\";\n\t\t\tgpio-export,direction_may_change = <1>;\n\t\t\tgpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tgpio13 {\n\t\t\t/* UARTF_DSR_N */\n\t\t\tgpio-export,name = \"gpio13\";\n\t\t\tgpio-export,direction_may_change = <1>;\n\t\t\tgpios = <&gpio0 13 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tgpio14 {\n\t\t\t/* UARTF_RIN */\n\t\t\tgpio-export,name = \"gpio14\";\n\t\t\tgpio-export,direction_may_change = <1>;\n\t\t\tgpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\t/* JTAG */\n\t\tgpio17 {\n\t\t\t/* JTAG_TDO */\n\t\t\tgpio-export,name = \"gpio17\";\n\t\t\tgpio-export,direction_may_change = <1>;\n\t\t\tgpios = <&gpio0 17 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tgpio18 {\n\t\t\t/* JTAG_TDI */\n\t\t\tgpio-export,name = \"gpio18\";\n\t\t\tgpio-export,direction_may_change = <1>;\n\t\t\tgpios = <&gpio0 18 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tgpio19 {\n\t\t\t/* JTAG_TMS */\n\t\t\tgpio-export,name = \"gpio19\";\n\t\t\tgpio-export,direction_may_change = <1>;\n\t\t\tgpios = <&gpio0 19 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tgpio20 {\n\t\t\t/* JTAG_TCLK */\n\t\t\tgpio-export,name = \"gpio20\";\n\t\t\tgpio-export,direction_may_change = <1>;\n\t\t\tgpios = <&gpio0 20 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tgpio21 {\n\t\t\t/* JTAG_TRST_N */\n\t\t\tgpio-export,name = \"gpio21\";\n\t\t\tgpio-export,direction_may_change = <1>;\n\t\t\tgpios = <&gpio0 21 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\t/* ETH LEDs */\n\t\tgpio22 {\n\t\t\t/* ETH0_LED */\n\t\t\tgpio-export,name = \"gpio22\";\n\t\t\tgpio-export,direction_may_change = <1>;\n\t\t\tgpios = <&gpio1 0 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tgpio23 {\n\t\t\t/* ETH1_LED */\n\t\t\tgpio-export,name = \"gpio23\";\n\t\t\tgpio-export,direction_may_change = <1>;\n\t\t\tgpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tgpio24 {\n\t\t\t/* ETH2_LED */\n\t\t\tgpio-export,name = \"gpio24\";\n\t\t\tgpio-export,direction_may_change = <1>;\n\t\t\tgpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tgpio25 {\n\t\t\t/* ETH3_LED */\n\t\t\tgpio-export,name = \"gpio25\";\n\t\t\tgpio-export,direction_may_change = <1>;\n\t\t\tgpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tgpio26 {\n\t\t\t/* ETH4_LED */\n\t\t\tgpio-export,name = \"gpio26\";\n\t\t\tgpio-export,direction_may_change = <1>;\n\t\t\tgpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_status: status {\n\t\t\t/* UARTF_RXD */\n\t\t\tlabel = \"green:status\";\n\t\t\tgpios = <&gpio0 10 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\teth {\n\t\t\t/* UARTF_DTR_N */\n\t\t\tlabel = \"orange:eth\";\n\t\t\tgpios = <&gpio0 11 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"uboot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"uboot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfirmware: partition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\t/* reg property is set based on flash size in DTS files */\n\t\t\t};\n\t\t};\n\t};\n};\n\n&gpio1 {\n\tstatus = \"okay\";\n};\n\n&i2c {\n\tstatus = \"okay\";\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"jtag\", \"uartf\", \"led\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&esw {\n\tmediatek,portmap = <0x11>;\n\tmediatek,portdisable = <0x2e>;\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&spi1 {\n\tstatus = \"okay\";\n\n\tspidev@0 {\n\t\tcompatible = \"linux,spidev\";\n\t\tspi-max-frequency = <10000000>;\n\t\treg = <0>;\n\t};\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt5350_wansview_ncs601w.dts",
    "content": "#include \"rt5350.dtsi\"\n\n/ {\n\tcompatible = \"wansview,ncs601w\", \"ralink,rt5350-soc\";\n\tmodel = \"Wansview NCS601W\";\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x7b0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"jtag\", \"uartf\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&esw {\n\tmediatek,portmap = <0x2f>;\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt5350_wiznet_wizfi630a.dts",
    "content": "#include \"rt5350.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"wiznet,wizfi630a\", \"ralink,rt5350-soc\";\n\tmodel = \"WIZnet WizFi630A\";\n\n\taliases {\n\t\tled-boot = &led_run;\n\t\tled-failsafe = &led_run;\n\t\tled-running = &led_run;\n\t\tled-upgrade = &led_run;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyS1,115200\";\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_run: run {\n\t\t\tlabel = \":run\";\n\t\t\tgpios = <&gpio0 1 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \":wps\";\n\t\t\tgpios = <&gpio0 20 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tuart1 {\n\t\t\tlabel = \":uart1\";\n\t\t\tgpios = <&gpio0 18 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tuart2 {\n\t\t\tlabel = \":uart2\";\n\t\t\tgpios = <&gpio0 21 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 17 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio0 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\n\t\tscm1 {\n\t\t\tlabel = \"SCM1\";\n\t\t\tgpios = <&gpio0 19 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_0>;\n\t\t};\n\n\t\tscm2 {\n\t\t\tlabel = \"SCM2\";\n\t\t\tgpios = <&gpio0 2 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_1>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\t#size-cells = <1>;\n\t\t\t\tlabel = \"uboot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\t#size-cells = <1>;\n\t\t\t\tlabel = \"uboot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\t#size-cells = <1>;\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\t#size-cells = <1>;\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0xfb0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&uart {\n\tstatus = \"okay\";\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&uartf_pins>;\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"jtag\" ;\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&esw {\n\tmediatek,portmap = <0x17>;\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt5350_zorlik_zl5900v2.dts",
    "content": "#include \"rt5350.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"zorlik,zl5900v2\", \"ralink,rt5350-soc\";\n\tmodel = \"Zorlik ZL5900V2\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tlan {\n\t\t\tlabel = \"green:lan\";\n\t\t\tgpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;\n\t\t};\n\n\t\tled_power: power {\n\t\t\tlabel = \"blue:power\";\n\t\t\tgpios = <&gpio0 17 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x7b0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"jtag\", \"uartf\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_4>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&esw {\n\tmediatek,portdisable = <0x2f>;\n};\n\n&wmac {\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_4: macaddr@4 {\n\t\treg = <0x4 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt5350_zyxel_keenetic-lite-b.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later\n\n#include \"rt5350.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"zyxel,keenetic-lite-b\", \"ralink,rt5350-soc\";\n\tmodel = \"ZyXEL Keenetic Lite Rev.B\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio0 9 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"green:wps\";\n\t\t\tgpios = <&gpio0 14 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio0 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 10 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <60000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x7b0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"uartf\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_28>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&esw {\n\tmediatek,portmap = <0x2f>;\n\tmediatek,led_polarity = <0x17>;\n};\n\n&wmac {\n\tralink,led-polarity = <1>;\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_28: macaddr@28 {\n\t\treg = <0x28 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/dts/rt5350_zyxel_keenetic-start.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"rt5350.dtsi\"\n\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/input/input.h>\n\n/ {\n\tcompatible = \"zyxel,keenetic-start\", \"ralink,rt5350-soc\";\n\tmodel = \"ZyXEL Keenetic Start\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t\tlabel-mac-device = &ethernet;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio0 9 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tinternet {\n\t\t\tlabel = \"green:internet\";\n\t\t\tgpios = <&gpio0 13 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 10 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\n\t\twps {\n\t\t\tlabel = \"wps\";\n\t\t\tgpios = <&gpio0 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_WPS_BUTTON>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x30000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@30000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x30000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tfactory: partition@40000 {\n\t\t\t\tlabel = \"factory\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@50000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x50000 0x3b0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&state_default {\n\tgpio {\n\t\tgroups = \"i2c\", \"jtag\", \"uartf\";\n\t\tfunction = \"gpio\";\n\t};\n};\n\n&ethernet {\n\tnvmem-cells = <&macaddr_factory_28>;\n\tnvmem-cell-names = \"mac-address\";\n};\n\n&esw {\n\tmediatek,portmap = <0x2f>;\n\tmediatek,led_polarity = <0x17>;\n};\n\n&wmac {\n\tstatus = \"okay\";\n\tralink,led-polarity = <1>;\n\tralink,mtd-eeprom = <&factory 0x0>;\n};\n\n&factory {\n\tcompatible = \"nvmem-cells\";\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tmacaddr_factory_28: macaddr@28 {\n\t\treg = <0x28 0x6>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/ramips/files/drivers/mmc/host/mtk-mmc/Kconfig",
    "content": "config MTK_MMC\n\ttristate \"MTK SD/MMC\"\n\tdepends on !MTD_NAND_RALINK\n\nconfig MTK_AEE_KDUMP\n\tbool \"MTK AEE KDUMP\"\n\tdepends on MTK_MMC\n\nconfig MTK_MMC_CD_POLL\n\tbool \"Card Detect with Polling\"\n\tdepends on MTK_MMC\n\n"
  },
  {
    "path": "target/linux/ramips/files/drivers/mmc/host/mtk-mmc/Makefile",
    "content": "# Copyright Statement:\n#\n# This software/firmware and related documentation (\"MediaTek Software\") are\n# protected under relevant copyright laws. The information contained herein\n# is confidential and proprietary to MediaTek Inc. and/or its licensors.\n# Without the prior written permission of MediaTek inc. and/or its licensors,\n# any reproduction, modification, use or disclosure of MediaTek Software,\n# and information contained herein, in whole or in part, shall be strictly prohibited.\n#\n# MediaTek Inc. (C) 2010. All rights reserved.\n#\n# BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES\n# THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS (\"MEDIATEK SOFTWARE\")\n# RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON\n# AN \"AS-IS\" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,\n# EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF\n# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.\n# NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE\n# SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR\n# SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH\n# THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES\n# THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES\n# CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK\n# SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR\n# STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND\n# CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,\n# AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,\n# OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO\n# MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.\n#\n# The following software/firmware and/or related documentation (\"MediaTek Software\")\n# have been modified by MediaTek Inc. All revisions are subject to any receiver's\n# applicable license agreements with MediaTek Inc.\n\nobj-$(CONFIG_MTK_MMC) += mtk_sd.o\nmtk_sd-objs := sd.o dbg.o\nifeq ($(CONFIG_MTK_AEE_KDUMP),y)\nEXTRA_CFLAGS\t\t+= -DMT6575_SD_DEBUG\nendif\n\nclean:\n\t@rm -f *.o modules.order .*.cmd\n"
  },
  {
    "path": "target/linux/ramips/files/drivers/mmc/host/mtk-mmc/board.h",
    "content": "/* Copyright Statement:\n *\n * This software/firmware and related documentation (\"MediaTek Software\") are\n * protected under relevant copyright laws. The information contained herein\n * is confidential and proprietary to MediaTek Inc. and/or its licensors.\n * Without the prior written permission of MediaTek inc. and/or its licensors,\n * any reproduction, modification, use or disclosure of MediaTek Software,\n * and information contained herein, in whole or in part, shall be strictly prohibited.\n */\n/* MediaTek Inc. (C) 2010. All rights reserved.\n *\n * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES\n * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS (\"MEDIATEK SOFTWARE\")\n * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON\n * AN \"AS-IS\" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF\n * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.\n * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE\n * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR\n * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH\n * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES\n * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES\n * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK\n * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR\n * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND\n * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,\n * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,\n * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO\n * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.\n *\n * The following software/firmware and/or related documentation (\"MediaTek Software\")\n * have been modified by MediaTek Inc. All revisions are subject to any receiver's\n * applicable license agreements with MediaTek Inc.\n */\n\n#ifndef __ARCH_ARM_MACH_BOARD_H\n#define __ARCH_ARM_MACH_BOARD_H\n\n#define MSDC_CD_PIN_EN      (1 << 0)  /* card detection pin is wired   */\n#define MSDC_WP_PIN_EN      (1 << 1)  /* write protection pin is wired */\n#define MSDC_RST_PIN_EN     (1 << 2)  /* emmc reset pin is wired       */\n#define MSDC_REMOVABLE      (1 << 5)  /* removable slot                */\n\n#define MSDC_SMPL_RISING    (0)\n#define MSDC_SMPL_FALLING   (1)\n\n#define MSDC_CMD_PIN        (0)\n#define MSDC_DAT_PIN        (1)\n#define MSDC_CD_PIN         (2)\n#define MSDC_WP_PIN         (3)\n#define MSDC_RST_PIN        (4)\n\nstruct msdc_hw {\n\tunsigned char  clk_src;          /* host clock source */\n\tunsigned long  flags;            /* hardware capability flags */\n\n\t/* config gpio pull mode */\n\tvoid (*config_gpio_pin)(int type, int pull);\n};\n\nextern struct msdc_hw msdc0_hw;\n\n#endif /* __ARCH_ARM_MACH_BOARD_H */\n"
  },
  {
    "path": "target/linux/ramips/files/drivers/mmc/host/mtk-mmc/dbg.c",
    "content": "/* Copyright Statement:\n *\n * This software/firmware and related documentation (\"MediaTek Software\") are\n * protected under relevant copyright laws. The information contained herein\n * is confidential and proprietary to MediaTek Inc. and/or its licensors.\n * Without the prior written permission of MediaTek inc. and/or its licensors,\n * any reproduction, modification, use or disclosure of MediaTek Software,\n * and information contained herein, in whole or in part, shall be strictly prohibited.\n *\n * MediaTek Inc. (C) 2010. All rights reserved.\n *\n * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES\n * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS (\"MEDIATEK SOFTWARE\")\n * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON\n * AN \"AS-IS\" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF\n * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.\n * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE\n * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR\n * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH\n * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES\n * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES\n * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK\n * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR\n * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND\n * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,\n * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,\n * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO\n * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.\n *\n * The following software/firmware and/or related documentation (\"MediaTek Software\")\n * have been modified by MediaTek Inc. All revisions are subject to any receiver's\n * applicable license agreements with MediaTek Inc.\n */\n\n#include <linux/version.h>\n#include <linux/kernel.h>\n#include <linux/sched.h>\n#include <linux/kthread.h>\n#include <linux/delay.h>\n#include <linux/module.h>\n#include <linux/init.h>\n#include <linux/proc_fs.h>\n#include <linux/string.h>\n#include <linux/uaccess.h>\n// #include <mach/mt6575_gpt.h> /* --- by chhung */\n#include \"dbg.h\"\n#include \"mt6575_sd.h\"\n#include <linux/seq_file.h>\n\nstatic char cmd_buf[256];\n\n/* for debug zone */\nunsigned int sd_debug_zone[4] = {\n\t0,\n\t0,\n\t0,\n\t0\n};\n\n#if defined(MT6575_SD_DEBUG)\n/* for driver profile */\n#define TICKS_ONE_MS  (13000)\nu32 gpt_enable;\nu32 sdio_pro_enable;   /* make sure gpt is enabled */\nu32 sdio_pro_time;     /* no more than 30s */\nstruct sdio_profile sdio_perfomance = {0};\n\n#if 0 /* --- chhung */\nvoid msdc_init_gpt(void)\n{\n\tGPT_CONFIG config;\n\n\tconfig.num  = GPT6;\n\tconfig.mode = GPT_FREE_RUN;\n\tconfig.clkSrc = GPT_CLK_SRC_SYS;\n\tconfig.clkDiv = GPT_CLK_DIV_1;   /* 13MHz GPT6 */\n\n\tif (GPT_Config(config) == FALSE)\n\t\treturn;\n\n\tGPT_Start(GPT6);\n}\n#endif /* end of --- */\n\nu32 msdc_time_calc(u32 old_L32, u32 old_H32, u32 new_L32, u32 new_H32)\n{\n\tu32 ret = 0;\n\n\tif (new_H32 == old_H32) {\n\t\tret = new_L32 - old_L32;\n\t} else if (new_H32 == (old_H32 + 1)) {\n\t\tif (new_L32 > old_L32)\n\t\t\tprintk(\"msdc old_L<0x%x> new_L<0x%x>\\n\", old_L32, new_L32);\n\t\tret = (0xffffffff - old_L32);\n\t\tret += new_L32;\n\t} else {\n\t\tprintk(\"msdc old_H<0x%x> new_H<0x%x>\\n\", old_H32, new_H32);\n\t}\n\n\treturn ret;\n}\n\nvoid msdc_sdio_profile(struct sdio_profile *result)\n{\n\tstruct cmd_profile *cmd;\n\tu32 i;\n\n\tprintk(\"sdio === performance dump ===\\n\");\n\tprintk(\"sdio === total execute tick<%d> time<%dms> Tx<%dB> Rx<%dB>\\n\",\n\t\tresult->total_tc, result->total_tc / TICKS_ONE_MS,\n\t\tresult->total_tx_bytes, result->total_rx_bytes);\n\n\t/* CMD52 Dump */\n\tcmd = &result->cmd52_rx;\n\tprintk(\"sdio === CMD52 Rx <%d>times tick<%d> Max<%d> Min<%d> Aver<%d>\\n\", cmd->count, cmd->tot_tc,\n\t       cmd->max_tc, cmd->min_tc, cmd->tot_tc / cmd->count);\n\tcmd = &result->cmd52_tx;\n\tprintk(\"sdio === CMD52 Tx <%d>times tick<%d> Max<%d> Min<%d> Aver<%d>\\n\", cmd->count, cmd->tot_tc,\n\t       cmd->max_tc, cmd->min_tc, cmd->tot_tc / cmd->count);\n\n\t/* CMD53 Rx bytes + block mode */\n\tfor (i = 0; i < 512; i++) {\n\t\tcmd = &result->cmd53_rx_byte[i];\n\t\tif (cmd->count) {\n\t\t\tprintk(\"sdio<%6d><%3dB>_Rx_<%9d><%9d><%6d><%6d>_<%9dB><%2dM>\\n\", cmd->count, i, cmd->tot_tc,\n\t\t\t       cmd->max_tc, cmd->min_tc, cmd->tot_tc / cmd->count,\n\t\t\t       cmd->tot_bytes, (cmd->tot_bytes / 10) * 13 / (cmd->tot_tc / 10));\n\t\t}\n\t}\n\tfor (i = 0; i < 100; i++) {\n\t\tcmd = &result->cmd53_rx_blk[i];\n\t\tif (cmd->count) {\n\t\t\tprintk(\"sdio<%6d><%3d>B_Rx_<%9d><%9d><%6d><%6d>_<%9dB><%2dM>\\n\", cmd->count, i, cmd->tot_tc,\n\t\t\t       cmd->max_tc, cmd->min_tc, cmd->tot_tc / cmd->count,\n\t\t\t       cmd->tot_bytes, (cmd->tot_bytes / 10) * 13 / (cmd->tot_tc / 10));\n\t\t}\n\t}\n\n\t/* CMD53 Tx bytes + block mode */\n\tfor (i = 0; i < 512; i++) {\n\t\tcmd = &result->cmd53_tx_byte[i];\n\t\tif (cmd->count) {\n\t\t\tprintk(\"sdio<%6d><%3dB>_Tx_<%9d><%9d><%6d><%6d>_<%9dB><%2dM>\\n\", cmd->count, i, cmd->tot_tc,\n\t\t\t       cmd->max_tc, cmd->min_tc, cmd->tot_tc / cmd->count,\n\t\t\t       cmd->tot_bytes, (cmd->tot_bytes / 10) * 13 / (cmd->tot_tc / 10));\n\t\t}\n\t}\n\tfor (i = 0; i < 100; i++) {\n\t\tcmd = &result->cmd53_tx_blk[i];\n\t\tif (cmd->count) {\n\t\t\tprintk(\"sdio<%6d><%3d>B_Tx_<%9d><%9d><%6d><%6d>_<%9dB><%2dM>\\n\", cmd->count, i, cmd->tot_tc,\n\t\t\t       cmd->max_tc, cmd->min_tc, cmd->tot_tc / cmd->count,\n\t\t\t       cmd->tot_bytes, (cmd->tot_bytes / 10) * 13 / (cmd->tot_tc / 10));\n\t\t}\n\t}\n\n\tprintk(\"sdio === performance dump done ===\\n\");\n}\n\n//========= sdio command table ===========\nvoid msdc_performance(u32 opcode, u32 sizes, u32 bRx, u32 ticks)\n{\n\tstruct sdio_profile *result = &sdio_perfomance;\n\tstruct cmd_profile *cmd;\n\tu32 block;\n\n\tif (sdio_pro_enable == 0)\n\t\treturn;\n\n\tif (opcode == 52) {\n\t\tcmd = bRx ?  &result->cmd52_rx : &result->cmd52_tx;\n\t} else if (opcode == 53) {\n\t\tif (sizes < 512) {\n\t\t\tcmd = bRx ?  &result->cmd53_rx_byte[sizes] : &result->cmd53_tx_byte[sizes];\n\t\t} else {\n\t\t\tblock = sizes / 512;\n\t\t\tif (block >= 99) {\n\t\t\t\tprintk(\"cmd53 error blocks\\n\");\n\t\t\t\twhile (1)\n\t\t\t\t\t;\n\t\t\t}\n\t\t\tcmd = bRx ?  &result->cmd53_rx_blk[block] : &result->cmd53_tx_blk[block];\n\t\t}\n\t} else {\n\t\treturn;\n\t}\n\n\t/* update the members */\n\tif (ticks > cmd->max_tc)\n\t\tcmd->max_tc = ticks;\n\tif (cmd->min_tc == 0 || ticks < cmd->min_tc)\n\t\tcmd->min_tc = ticks;\n\tcmd->tot_tc += ticks;\n\tcmd->tot_bytes += sizes;\n\tcmd->count++;\n\n\tif (bRx)\n\t\tresult->total_rx_bytes += sizes;\n\telse\n\t\tresult->total_tx_bytes += sizes;\n\tresult->total_tc += ticks;\n\n\t/* dump when total_tc > 30s */\n\tif (result->total_tc >= sdio_pro_time * TICKS_ONE_MS * 1000) {\n\t\tmsdc_sdio_profile(result);\n\t\tmemset(result, 0, sizeof(struct sdio_profile));\n\t}\n}\n\n//========== driver proc interface ===========\nstatic int msdc_debug_proc_read(struct seq_file *s, void *p)\n{\n\tseq_puts(s, \"\\n=========================================\\n\");\n\tseq_puts(s, \"Index<0> + Id + Zone\\n\");\n\tseq_puts(s, \"-> PWR<9> WRN<8> | FIO<7> OPS<6> FUN<5> CFG<4> | INT<3> RSP<2> CMD<1> DMA<0>\\n\");\n\tseq_puts(s, \"-> echo 0 3 0x3ff >msdc_bebug -> host[3] debug zone set to 0x3ff\\n\");\n\tseq_printf(s, \"-> MSDC[0] Zone: 0x%.8x\\n\", sd_debug_zone[0]);\n\tseq_printf(s, \"-> MSDC[1] Zone: 0x%.8x\\n\", sd_debug_zone[1]);\n\tseq_printf(s, \"-> MSDC[2] Zone: 0x%.8x\\n\", sd_debug_zone[2]);\n\tseq_printf(s, \"-> MSDC[3] Zone: 0x%.8x\\n\", sd_debug_zone[3]);\n\n\tseq_puts(s, \"Index<3> + SDIO_PROFILE + TIME\\n\");\n\tseq_puts(s, \"-> echo 3 1 0x1E >msdc_bebug -> enable sdio_profile, 30s\\n\");\n\tseq_printf(s, \"-> SDIO_PROFILE<%d> TIME<%ds>\\n\", sdio_pro_enable, sdio_pro_time);\n\tseq_puts(s, \"=========================================\\n\\n\");\n\n\treturn 0;\n}\n\nstatic ssize_t msdc_debug_proc_write(struct file *file,\n\t\t\t\tconst char __user *buf, size_t count, loff_t *data)\n{\n\tint ret;\n\n\tint cmd, p1, p2;\n\tint id, zone;\n\tint mode, size;\n\n\tif (count == 0)\n\t\treturn -1;\n\tif (count > 255)\n\t\tcount = 255;\n\n\tif (copy_from_user(cmd_buf, buf, count))\n\t\treturn -EFAULT;\n\n\tcmd_buf[count] = '\\0';\n\tprintk(\"msdc Write %s\\n\", cmd_buf);\n\n\tsscanf(cmd_buf, \"%x %x %x\", &cmd, &p1, &p2);\n\n\tif (cmd == SD_TOOL_ZONE) {\n\t\tid = p1;\n\t\tzone = p2;\n\t\tzone &= 0x3ff;\n\t\tprintk(\"msdc host_id<%d> zone<0x%.8x>\\n\", id, zone);\n\t\tif (id >= 0 && id <= 3) {\n\t\t\tsd_debug_zone[id] = zone;\n\t\t} else if (id == 4) {\n\t\t\tsd_debug_zone[0] = sd_debug_zone[1] = zone;\n\t\t\tsd_debug_zone[2] = sd_debug_zone[3] = zone;\n\t\t} else {\n\t\t\tprintk(\"msdc host_id error when set debug zone\\n\");\n\t\t}\n\t} else if (cmd == SD_TOOL_SDIO_PROFILE) {\n\t\tif (p1 == 1) { /* enable profile */\n\t\t\tif (gpt_enable == 0) {\n\t\t\t\t// msdc_init_gpt(); /* --- by chhung */\n\t\t\t\tgpt_enable = 1;\n\t\t\t}\n\t\t\tsdio_pro_enable = 1;\n\t\t\tif (p2 == 0)\n\t\t\t\tp2 = 1;\n\t\t\tif (p2 >= 30)\n\t\t\t\tp2 = 30;\n\t\t\tsdio_pro_time = p2;\n\t\t} else if (p1 == 0) {\n\t\t\t/* todo */\n\t\t\tsdio_pro_enable = 0;\n\t\t}\n\t}\n\n\treturn count;\n}\n\nstatic int msdc_debug_show(struct inode *inode, struct file *file)\n{\n\treturn single_open(file, msdc_debug_proc_read, NULL);\n}\n\nstatic const struct file_operations msdc_debug_fops = {\n\t.owner\t\t= THIS_MODULE,\n\t.open\t\t= msdc_debug_show,\n\t.read\t\t= seq_read,\n\t.write\t\t= msdc_debug_proc_write,\n\t.llseek\t\t= seq_lseek,\n\t.release\t= single_release,\n};\n\nvoid msdc_debug_proc_init(void)\n{\n\tproc_create(\"msdc_debug\", 0660, NULL, &msdc_debug_fops);\n}\nEXPORT_SYMBOL_GPL(msdc_debug_proc_init);\n#endif\n"
  },
  {
    "path": "target/linux/ramips/files/drivers/mmc/host/mtk-mmc/dbg.h",
    "content": "/* Copyright Statement:\n *\n * This software/firmware and related documentation (\"MediaTek Software\") are\n * protected under relevant copyright laws. The information contained herein\n * is confidential and proprietary to MediaTek Inc. and/or its licensors.\n * Without the prior written permission of MediaTek inc. and/or its licensors,\n * any reproduction, modification, use or disclosure of MediaTek Software,\n * and information contained herein, in whole or in part, shall be strictly prohibited.\n *\n * MediaTek Inc. (C) 2010. All rights reserved.\n *\n * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES\n * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS (\"MEDIATEK SOFTWARE\")\n * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON\n * AN \"AS-IS\" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF\n * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.\n * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE\n * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR\n * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH\n * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES\n * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES\n * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK\n * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR\n * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND\n * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,\n * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,\n * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO\n * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.\n *\n * The following software/firmware and/or related documentation (\"MediaTek Software\")\n * have been modified by MediaTek Inc. All revisions are subject to any receiver's\n * applicable license agreements with MediaTek Inc.\n */\n#ifndef __MT_MSDC_DEUBG__\n#define __MT_MSDC_DEUBG__\n\n//==========================\nextern u32 sdio_pro_enable;\n/* for a type command, e.g. CMD53, 2 blocks */\nstruct cmd_profile {\n\tu32 max_tc;    /* Max tick count */\n\tu32 min_tc;\n\tu32 tot_tc;    /* total tick count */\n\tu32 tot_bytes;\n\tu32 count;     /* the counts of the command */\n};\n\n/* dump when total_tc and total_bytes */\nstruct sdio_profile {\n\tu32 total_tc;         /* total tick count of CMD52 and CMD53 */\n\tu32 total_tx_bytes;   /* total bytes of CMD53 Tx */\n\tu32 total_rx_bytes;   /* total bytes of CMD53 Rx */\n\n\t/*CMD52*/\n\tstruct cmd_profile cmd52_tx;\n\tstruct cmd_profile cmd52_rx;\n\n\t/*CMD53 in byte unit */\n\tstruct cmd_profile cmd53_tx_byte[512];\n\tstruct cmd_profile cmd53_rx_byte[512];\n\n\t/*CMD53 in block unit */\n\tstruct cmd_profile cmd53_tx_blk[100];\n\tstruct cmd_profile cmd53_rx_blk[100];\n};\n\n//==========================\nenum msdc_dbg {\n\tSD_TOOL_ZONE = 0,\n\tSD_TOOL_DMA_SIZE  = 1,\n\tSD_TOOL_PM_ENABLE = 2,\n\tSD_TOOL_SDIO_PROFILE = 3,\n};\n\nenum msdc_mode {\n\tMODE_PIO = 0,\n\tMODE_DMA = 1,\n\tMODE_SIZE_DEP = 2,\n};\n\n/* Debug message event */\n#define DBG_EVT_NONE        (0)       /* No event */\n#define DBG_EVT_DMA         (1 << 0)  /* DMA related event */\n#define DBG_EVT_CMD         (1 << 1)  /* MSDC CMD related event */\n#define DBG_EVT_RSP         (1 << 2)  /* MSDC CMD RSP related event */\n#define DBG_EVT_INT         (1 << 3)  /* MSDC INT event */\n#define DBG_EVT_CFG         (1 << 4)  /* MSDC CFG event */\n#define DBG_EVT_FUC         (1 << 5)  /* Function event */\n#define DBG_EVT_OPS         (1 << 6)  /* Read/Write operation event */\n#define DBG_EVT_FIO         (1 << 7)  /* FIFO operation event */\n#define DBG_EVT_WRN         (1 << 8)  /* Warning event */\n#define DBG_EVT_PWR         (1 << 9)  /* Power event */\n#define DBG_EVT_ALL         (0xffffffff)\n\n#define DBG_EVT_MASK        (DBG_EVT_ALL)\n\nextern unsigned int sd_debug_zone[4];\n#define TAG \"msdc\"\n#if 0 /* +++ chhung */\n#define BUG_ON(x) \\\ndo { \\\n\tif (x) { \\\n\t\tprintk(\"[BUG] %s LINE:%d FILE:%s\\n\", #x, __LINE__, __FILE__); \\\n\t\twhile (1)\t\t\t\t\t\t\\\n\t\t\t;\t\t\t\t\t\t\\\n\t} \\\n} while (0)\n#endif /* end of +++ */\n\n#define N_MSG(evt, fmt, args...)\n/*\ndo {    \\\n    if ((DBG_EVT_##evt) & sd_debug_zone[host->id]) { \\\n        printk(KERN_ERR TAG\"%d -> \"fmt\" <- %s() : L<%d> PID<%s><0x%x>\\n\", \\\n            host->id,  ##args , __FUNCTION__, __LINE__, current->comm, current->pid);\t\\\n    } \\\n} while(0)\n*/\n\n#define ERR_MSG(fmt, args...) \\\ndo { \\\n\tprintk(KERN_ERR TAG\"%d -> \"fmt\" <- %s() : L<%d> PID<%s><0x%x>\\n\", \\\n\t       host->id,  ##args, __FUNCTION__, __LINE__, current->comm, current->pid); \\\n} while (0);\n\n#if 1\n//defined CONFIG_MTK_MMC_CD_POLL\n#define INIT_MSG(fmt, args...)\n#define IRQ_MSG(fmt, args...)\n#else\n#define INIT_MSG(fmt, args...) \\\ndo { \\\n\tprintk(KERN_ERR TAG\"%d -> \"fmt\" <- %s() : L<%d> PID<%s><0x%x>\\n\", \\\n\t       host->id,  ##args, __FUNCTION__, __LINE__, current->comm, current->pid); \\\n} while (0);\n\n/* PID in ISR in not corrent */\n#define IRQ_MSG(fmt, args...) \\\ndo { \\\n\tprintk(KERN_ERR TAG\"%d -> \"fmt\" <- %s() : L<%d>\\n\",\t\\\n\t       host->id,  ##args, __FUNCTION__, __LINE__);\t\\\n} while (0);\n#endif\n\nvoid msdc_debug_proc_init(void);\n\n#if 0 /* --- chhung */\nvoid msdc_init_gpt(void);\nextern void GPT_GetCounter64(UINT32 *cntL32, UINT32 *cntH32);\n#endif /* end of --- */\nu32 msdc_time_calc(u32 old_L32, u32 old_H32, u32 new_L32, u32 new_H32);\nvoid msdc_performance(u32 opcode, u32 sizes, u32 bRx, u32 ticks);\n\n#endif\n"
  },
  {
    "path": "target/linux/ramips/files/drivers/mmc/host/mtk-mmc/mt6575_sd.h",
    "content": "/* Copyright Statement:\n *\n * This software/firmware and related documentation (\"MediaTek Software\") are\n * protected under relevant copyright laws. The information contained herein\n * is confidential and proprietary to MediaTek Inc. and/or its licensors.\n * Without the prior written permission of MediaTek inc. and/or its licensors,\n * any reproduction, modification, use or disclosure of MediaTek Software,\n * and information contained herein, in whole or in part, shall be strictly prohibited.\n */\n/* MediaTek Inc. (C) 2010. All rights reserved.\n *\n * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES\n * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS (\"MEDIATEK SOFTWARE\")\n * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON\n * AN \"AS-IS\" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF\n * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.\n * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE\n * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR\n * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH\n * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES\n * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES\n * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK\n * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR\n * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND\n * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,\n * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,\n * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO\n * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.\n *\n * The following software/firmware and/or related documentation (\"MediaTek Software\")\n * have been modified by MediaTek Inc. All revisions are subject to any receiver's\n * applicable license agreements with MediaTek Inc.\n */\n\n#ifndef MT6575_SD_H\n#define MT6575_SD_H\n\n#include <linux/bitops.h>\n#include <linux/mmc/host.h>\n\n// #include <mach/mt6575_reg_base.h> /* --- by chhung */\n\n/*--------------------------------------------------------------------------*/\n/* Common Macro                                                             */\n/*--------------------------------------------------------------------------*/\n#define REG_ADDR(x)                 (base + OFFSET_##x)\n\n/*--------------------------------------------------------------------------*/\n/* Common Definition                                                        */\n/*--------------------------------------------------------------------------*/\n#define MSDC_FIFO_SZ            (128)\n#define MSDC_FIFO_THD           (64)  // (128)\n#define MSDC_NUM                (4)\n\n#define MSDC_MS                 (0)\n#define MSDC_SDMMC              (1)\n\n#define MSDC_MODE_UNKNOWN       (0)\n#define MSDC_MODE_PIO           (1)\n#define MSDC_MODE_DMA_BASIC     (2)\n#define MSDC_MODE_DMA_DESC      (3)\n#define MSDC_MODE_DMA_ENHANCED  (4)\n#define MSDC_MODE_MMC_STREAM    (5)\n\n#define MSDC_BUS_1BITS          (0)\n#define MSDC_BUS_4BITS          (1)\n#define MSDC_BUS_8BITS          (2)\n\n#define MSDC_BRUST_8B           (3)\n#define MSDC_BRUST_16B          (4)\n#define MSDC_BRUST_32B          (5)\n#define MSDC_BRUST_64B          (6)\n\n#define MSDC_PIN_PULL_NONE      (0)\n#define MSDC_PIN_PULL_DOWN      (1)\n#define MSDC_PIN_PULL_UP        (2)\n#define MSDC_PIN_KEEP           (3)\n\n#define MSDC_MAX_SCLK           (48000000) /* +/- by chhung */\n#define MSDC_MIN_SCLK           (260000)\n\n#define MSDC_AUTOCMD12          (0x0001)\n#define MSDC_AUTOCMD23          (0x0002)\n#define MSDC_AUTOCMD19          (0x0003)\n\n#define MSDC_EMMC_BOOTMODE0     (0)     /* Pull low CMD mode */\n#define MSDC_EMMC_BOOTMODE1     (1)     /* Reset CMD mode */\n\nenum {\n\tRESP_NONE = 0,\n\tRESP_R1,\n\tRESP_R2,\n\tRESP_R3,\n\tRESP_R4,\n\tRESP_R5,\n\tRESP_R6,\n\tRESP_R7,\n\tRESP_R1B\n};\n\n/*--------------------------------------------------------------------------*/\n/* Register Offset                                                          */\n/*--------------------------------------------------------------------------*/\n#define OFFSET_MSDC_CFG         (0x0)\n#define OFFSET_MSDC_IOCON       (0x04)\n#define OFFSET_MSDC_PS          (0x08)\n#define OFFSET_MSDC_INT         (0x0c)\n#define OFFSET_MSDC_INTEN       (0x10)\n#define OFFSET_MSDC_FIFOCS      (0x14)\n#define OFFSET_MSDC_TXDATA      (0x18)\n#define OFFSET_MSDC_RXDATA      (0x1c)\n#define OFFSET_SDC_CFG          (0x30)\n#define OFFSET_SDC_CMD          (0x34)\n#define OFFSET_SDC_ARG          (0x38)\n#define OFFSET_SDC_STS          (0x3c)\n#define OFFSET_SDC_RESP0        (0x40)\n#define OFFSET_SDC_RESP1        (0x44)\n#define OFFSET_SDC_RESP2        (0x48)\n#define OFFSET_SDC_RESP3        (0x4c)\n#define OFFSET_SDC_BLK_NUM      (0x50)\n#define OFFSET_SDC_CSTS         (0x58)\n#define OFFSET_SDC_CSTS_EN      (0x5c)\n#define OFFSET_SDC_DCRC_STS     (0x60)\n#define OFFSET_EMMC_CFG0        (0x70)\n#define OFFSET_EMMC_CFG1        (0x74)\n#define OFFSET_EMMC_STS         (0x78)\n#define OFFSET_EMMC_IOCON       (0x7c)\n#define OFFSET_SDC_ACMD_RESP    (0x80)\n#define OFFSET_SDC_ACMD19_TRG   (0x84)\n#define OFFSET_SDC_ACMD19_STS   (0x88)\n#define OFFSET_MSDC_DMA_SA      (0x90)\n#define OFFSET_MSDC_DMA_CA      (0x94)\n#define OFFSET_MSDC_DMA_CTRL    (0x98)\n#define OFFSET_MSDC_DMA_CFG     (0x9c)\n#define OFFSET_MSDC_DBG_SEL     (0xa0)\n#define OFFSET_MSDC_DBG_OUT     (0xa4)\n#define OFFSET_MSDC_PATCH_BIT   (0xb0)\n#define OFFSET_MSDC_PATCH_BIT1  (0xb4)\n#define OFFSET_MSDC_PAD_CTL0    (0xe0)\n#define OFFSET_MSDC_PAD_CTL1    (0xe4)\n#define OFFSET_MSDC_PAD_CTL2    (0xe8)\n#define OFFSET_MSDC_PAD_TUNE    (0xec)\n#define OFFSET_MSDC_DAT_RDDLY0  (0xf0)\n#define OFFSET_MSDC_DAT_RDDLY1  (0xf4)\n#define OFFSET_MSDC_HW_DBG      (0xf8)\n#define OFFSET_MSDC_VERSION     (0x100)\n#define OFFSET_MSDC_ECO_VER     (0x104)\n\n/*--------------------------------------------------------------------------*/\n/* Register Address                                                         */\n/*--------------------------------------------------------------------------*/\n\n/* common register */\n#define MSDC_CFG                REG_ADDR(MSDC_CFG)\n#define MSDC_IOCON              REG_ADDR(MSDC_IOCON)\n#define MSDC_PS                 REG_ADDR(MSDC_PS)\n#define MSDC_INT                REG_ADDR(MSDC_INT)\n#define MSDC_INTEN              REG_ADDR(MSDC_INTEN)\n#define MSDC_FIFOCS             REG_ADDR(MSDC_FIFOCS)\n#define MSDC_TXDATA             REG_ADDR(MSDC_TXDATA)\n#define MSDC_RXDATA             REG_ADDR(MSDC_RXDATA)\n#define MSDC_PATCH_BIT0         REG_ADDR(MSDC_PATCH_BIT)\n\n/* sdmmc register */\n#define SDC_CFG                 REG_ADDR(SDC_CFG)\n#define SDC_CMD                 REG_ADDR(SDC_CMD)\n#define SDC_ARG                 REG_ADDR(SDC_ARG)\n#define SDC_STS                 REG_ADDR(SDC_STS)\n#define SDC_RESP0               REG_ADDR(SDC_RESP0)\n#define SDC_RESP1               REG_ADDR(SDC_RESP1)\n#define SDC_RESP2               REG_ADDR(SDC_RESP2)\n#define SDC_RESP3               REG_ADDR(SDC_RESP3)\n#define SDC_BLK_NUM             REG_ADDR(SDC_BLK_NUM)\n#define SDC_CSTS                REG_ADDR(SDC_CSTS)\n#define SDC_CSTS_EN             REG_ADDR(SDC_CSTS_EN)\n#define SDC_DCRC_STS            REG_ADDR(SDC_DCRC_STS)\n\n/* emmc register*/\n#define EMMC_CFG0               REG_ADDR(EMMC_CFG0)\n#define EMMC_CFG1               REG_ADDR(EMMC_CFG1)\n#define EMMC_STS                REG_ADDR(EMMC_STS)\n#define EMMC_IOCON              REG_ADDR(EMMC_IOCON)\n\n/* auto command register */\n#define SDC_ACMD_RESP           REG_ADDR(SDC_ACMD_RESP)\n#define SDC_ACMD19_TRG          REG_ADDR(SDC_ACMD19_TRG)\n#define SDC_ACMD19_STS          REG_ADDR(SDC_ACMD19_STS)\n\n/* dma register */\n#define MSDC_DMA_SA             REG_ADDR(MSDC_DMA_SA)\n#define MSDC_DMA_CA             REG_ADDR(MSDC_DMA_CA)\n#define MSDC_DMA_CTRL           REG_ADDR(MSDC_DMA_CTRL)\n#define MSDC_DMA_CFG            REG_ADDR(MSDC_DMA_CFG)\n\n/* pad ctrl register */\n#define MSDC_PAD_CTL0           REG_ADDR(MSDC_PAD_CTL0)\n#define MSDC_PAD_CTL1           REG_ADDR(MSDC_PAD_CTL1)\n#define MSDC_PAD_CTL2           REG_ADDR(MSDC_PAD_CTL2)\n\n/* data read delay */\n#define MSDC_DAT_RDDLY0         REG_ADDR(MSDC_DAT_RDDLY0)\n#define MSDC_DAT_RDDLY1         REG_ADDR(MSDC_DAT_RDDLY1)\n\n/* debug register */\n#define MSDC_DBG_SEL            REG_ADDR(MSDC_DBG_SEL)\n#define MSDC_DBG_OUT            REG_ADDR(MSDC_DBG_OUT)\n\n/* misc register */\n#define MSDC_PATCH_BIT          REG_ADDR(MSDC_PATCH_BIT)\n#define MSDC_PATCH_BIT1         REG_ADDR(MSDC_PATCH_BIT1)\n#define MSDC_PAD_TUNE           REG_ADDR(MSDC_PAD_TUNE)\n#define MSDC_HW_DBG             REG_ADDR(MSDC_HW_DBG)\n#define MSDC_VERSION            REG_ADDR(MSDC_VERSION)\n#define MSDC_ECO_VER            REG_ADDR(MSDC_ECO_VER) /* ECO Version */\n\n/*--------------------------------------------------------------------------*/\n/* Register Mask                                                            */\n/*--------------------------------------------------------------------------*/\n\n/* MSDC_CFG mask */\n#define MSDC_CFG_MODE           (0x1  << 0)     /* RW */\n#define MSDC_CFG_CKPDN          (0x1  << 1)     /* RW */\n#define MSDC_CFG_RST            (0x1  << 2)     /* RW */\n#define MSDC_CFG_PIO            (0x1  << 3)     /* RW */\n#define MSDC_CFG_CKDRVEN        (0x1  << 4)     /* RW */\n#define MSDC_CFG_BV18SDT        (0x1  << 5)     /* RW */\n#define MSDC_CFG_BV18PSS        (0x1  << 6)     /* R  */\n#define MSDC_CFG_CKSTB          (0x1  << 7)     /* R  */\n#define MSDC_CFG_CKDIV          (0xff << 8)     /* RW */\n#define MSDC_CFG_CKMOD          (0x3  << 16)    /* RW */\n\n/* MSDC_IOCON mask */\n#define MSDC_IOCON_SDR104CKS    (0x1  << 0)     /* RW */\n#define MSDC_IOCON_RSPL         (0x1  << 1)     /* RW */\n#define MSDC_IOCON_DSPL         (0x1  << 2)     /* RW */\n#define MSDC_IOCON_DDLSEL       (0x1  << 3)     /* RW */\n#define MSDC_IOCON_DDR50CKD     (0x1  << 4)     /* RW */\n#define MSDC_IOCON_DSPLSEL      (0x1  << 5)     /* RW */\n#define MSDC_IOCON_D0SPL        (0x1  << 16)    /* RW */\n#define MSDC_IOCON_D1SPL        (0x1  << 17)    /* RW */\n#define MSDC_IOCON_D2SPL        (0x1  << 18)    /* RW */\n#define MSDC_IOCON_D3SPL        (0x1  << 19)    /* RW */\n#define MSDC_IOCON_D4SPL        (0x1  << 20)    /* RW */\n#define MSDC_IOCON_D5SPL        (0x1  << 21)    /* RW */\n#define MSDC_IOCON_D6SPL        (0x1  << 22)    /* RW */\n#define MSDC_IOCON_D7SPL        (0x1  << 23)    /* RW */\n#define MSDC_IOCON_RISCSZ       (0x3  << 24)    /* RW */\n\n/* MSDC_PS mask */\n#define MSDC_PS_CDEN            (0x1  << 0)     /* RW */\n#define MSDC_PS_CDSTS           (0x1  << 1)     /* R  */\n#define MSDC_PS_CDDEBOUNCE      (0xf  << 12)    /* RW */\n#define MSDC_PS_DAT             (0xff << 16)    /* R  */\n#define MSDC_PS_CMD             (0x1  << 24)    /* R  */\n#define MSDC_PS_WP              (0x1UL << 31)    /* R  */\n\n/* MSDC_INT mask */\n#define MSDC_INT_MMCIRQ         (0x1  << 0)     /* W1C */\n#define MSDC_INT_CDSC           (0x1  << 1)     /* W1C */\n#define MSDC_INT_ACMDRDY        (0x1  << 3)     /* W1C */\n#define MSDC_INT_ACMDTMO        (0x1  << 4)     /* W1C */\n#define MSDC_INT_ACMDCRCERR     (0x1  << 5)     /* W1C */\n#define MSDC_INT_DMAQ_EMPTY     (0x1  << 6)     /* W1C */\n#define MSDC_INT_SDIOIRQ        (0x1  << 7)     /* W1C */\n#define MSDC_INT_CMDRDY         (0x1  << 8)     /* W1C */\n#define MSDC_INT_CMDTMO         (0x1  << 9)     /* W1C */\n#define MSDC_INT_RSPCRCERR      (0x1  << 10)    /* W1C */\n#define MSDC_INT_CSTA           (0x1  << 11)    /* R */\n#define MSDC_INT_XFER_COMPL     (0x1  << 12)    /* W1C */\n#define MSDC_INT_DXFER_DONE     (0x1  << 13)    /* W1C */\n#define MSDC_INT_DATTMO         (0x1  << 14)    /* W1C */\n#define MSDC_INT_DATCRCERR      (0x1  << 15)    /* W1C */\n#define MSDC_INT_ACMD19_DONE    (0x1  << 16)    /* W1C */\n\n/* MSDC_INTEN mask */\n#define MSDC_INTEN_MMCIRQ       (0x1  << 0)     /* RW */\n#define MSDC_INTEN_CDSC         (0x1  << 1)     /* RW */\n#define MSDC_INTEN_ACMDRDY      (0x1  << 3)     /* RW */\n#define MSDC_INTEN_ACMDTMO      (0x1  << 4)     /* RW */\n#define MSDC_INTEN_ACMDCRCERR   (0x1  << 5)     /* RW */\n#define MSDC_INTEN_DMAQ_EMPTY   (0x1  << 6)     /* RW */\n#define MSDC_INTEN_SDIOIRQ      (0x1  << 7)     /* RW */\n#define MSDC_INTEN_CMDRDY       (0x1  << 8)     /* RW */\n#define MSDC_INTEN_CMDTMO       (0x1  << 9)     /* RW */\n#define MSDC_INTEN_RSPCRCERR    (0x1  << 10)    /* RW */\n#define MSDC_INTEN_CSTA         (0x1  << 11)    /* RW */\n#define MSDC_INTEN_XFER_COMPL   (0x1  << 12)    /* RW */\n#define MSDC_INTEN_DXFER_DONE   (0x1  << 13)    /* RW */\n#define MSDC_INTEN_DATTMO       (0x1  << 14)    /* RW */\n#define MSDC_INTEN_DATCRCERR    (0x1  << 15)    /* RW */\n#define MSDC_INTEN_ACMD19_DONE  (0x1  << 16)    /* RW */\n\n/* MSDC_FIFOCS mask */\n#define MSDC_FIFOCS_RXCNT       (0xff << 0)     /* R */\n#define MSDC_FIFOCS_TXCNT       (0xff << 16)    /* R */\n#define MSDC_FIFOCS_CLR         (0x1UL << 31)    /* RW */\n\n/* SDC_CFG mask */\n#define SDC_CFG_SDIOINTWKUP     (0x1  << 0)     /* RW */\n#define SDC_CFG_INSWKUP         (0x1  << 1)     /* RW */\n#define SDC_CFG_BUSWIDTH        (0x3  << 16)    /* RW */\n#define SDC_CFG_SDIO            (0x1  << 19)    /* RW */\n#define SDC_CFG_SDIOIDE         (0x1  << 20)    /* RW */\n#define SDC_CFG_INTATGAP        (0x1  << 21)    /* RW */\n#define SDC_CFG_DTOC            (0xffUL << 24)  /* RW */\n\n/* SDC_CMD mask */\n#define SDC_CMD_OPC             (0x3f << 0)     /* RW */\n#define SDC_CMD_BRK             (0x1  << 6)     /* RW */\n#define SDC_CMD_RSPTYP          (0x7  << 7)     /* RW */\n#define SDC_CMD_DTYP            (0x3  << 11)    /* RW */\n#define SDC_CMD_DTYP            (0x3  << 11)    /* RW */\n#define SDC_CMD_RW              (0x1  << 13)    /* RW */\n#define SDC_CMD_STOP            (0x1  << 14)    /* RW */\n#define SDC_CMD_GOIRQ           (0x1  << 15)    /* RW */\n#define SDC_CMD_BLKLEN          (0xfff << 16)    /* RW */\n#define SDC_CMD_AUTOCMD         (0x3  << 28)    /* RW */\n#define SDC_CMD_VOLSWTH         (0x1  << 30)    /* RW */\n\n/* SDC_STS mask */\n#define SDC_STS_SDCBUSY         (0x1  << 0)     /* RW */\n#define SDC_STS_CMDBUSY         (0x1  << 1)     /* RW */\n#define SDC_STS_SWR_COMPL       (0x1  << 31)    /* RW */\n\n/* SDC_DCRC_STS mask */\n#define SDC_DCRC_STS_NEG        (0xf  << 8)     /* RO */\n#define SDC_DCRC_STS_POS        (0xff << 0)     /* RO */\n\n/* EMMC_CFG0 mask */\n#define EMMC_CFG0_BOOTSTART     (0x1  << 0)     /* W */\n#define EMMC_CFG0_BOOTSTOP      (0x1  << 1)     /* W */\n#define EMMC_CFG0_BOOTMODE      (0x1  << 2)     /* RW */\n#define EMMC_CFG0_BOOTACKDIS    (0x1  << 3)     /* RW */\n#define EMMC_CFG0_BOOTWDLY      (0x7  << 12)    /* RW */\n#define EMMC_CFG0_BOOTSUPP      (0x1  << 15)    /* RW */\n\n/* EMMC_CFG1 mask */\n#define EMMC_CFG1_BOOTDATTMC    (0xfffff << 0)  /* RW */\n#define EMMC_CFG1_BOOTACKTMC    (0xfffUL << 20) /* RW */\n\n/* EMMC_STS mask */\n#define EMMC_STS_BOOTCRCERR     (0x1  << 0)     /* W1C */\n#define EMMC_STS_BOOTACKERR     (0x1  << 1)     /* W1C */\n#define EMMC_STS_BOOTDATTMO     (0x1  << 2)     /* W1C */\n#define EMMC_STS_BOOTACKTMO     (0x1  << 3)     /* W1C */\n#define EMMC_STS_BOOTUPSTATE    (0x1  << 4)     /* R */\n#define EMMC_STS_BOOTACKRCV     (0x1  << 5)     /* W1C */\n#define EMMC_STS_BOOTDATRCV     (0x1  << 6)     /* R */\n\n/* EMMC_IOCON mask */\n#define EMMC_IOCON_BOOTRST      (0x1  << 0)     /* RW */\n\n/* SDC_ACMD19_TRG mask */\n#define SDC_ACMD19_TRG_TUNESEL  (0xf  << 0)     /* RW */\n\n/* MSDC_DMA_CTRL mask */\n#define MSDC_DMA_CTRL_START     (0x1  << 0)     /* W */\n#define MSDC_DMA_CTRL_STOP      (0x1  << 1)     /* W */\n#define MSDC_DMA_CTRL_RESUME    (0x1  << 2)     /* W */\n#define MSDC_DMA_CTRL_MODE      (0x1  << 8)     /* RW */\n#define MSDC_DMA_CTRL_LASTBUF   (0x1  << 10)    /* RW */\n#define MSDC_DMA_CTRL_BRUSTSZ   (0x7  << 12)    /* RW */\n#define MSDC_DMA_CTRL_XFERSZ    (0xffffUL << 16)/* RW */\n\n/* MSDC_DMA_CFG mask */\n#define MSDC_DMA_CFG_STS        (0x1  << 0)     /* R */\n#define MSDC_DMA_CFG_DECSEN     (0x1  << 1)     /* RW */\n#define MSDC_DMA_CFG_BDCSERR    (0x1  << 4)     /* R */\n#define MSDC_DMA_CFG_GPDCSERR   (0x1  << 5)     /* R */\n\n/* MSDC_PATCH_BIT mask */\n#define MSDC_PATCH_BIT_WFLSMODE (0x1  << 0)     /* RW */\n#define MSDC_PATCH_BIT_ODDSUPP  (0x1  << 1)     /* RW */\n#define MSDC_PATCH_BIT_CKGEN_CK (0x1  << 6)     /* E2: Fixed to 1 */\n#define MSDC_PATCH_BIT_IODSSEL  (0x1  << 16)    /* RW */\n#define MSDC_PATCH_BIT_IOINTSEL (0x1  << 17)    /* RW */\n#define MSDC_PATCH_BIT_BUSYDLY  (0xf  << 18)    /* RW */\n#define MSDC_PATCH_BIT_WDOD     (0xf  << 22)    /* RW */\n#define MSDC_PATCH_BIT_IDRTSEL  (0x1  << 26)    /* RW */\n#define MSDC_PATCH_BIT_CMDFSEL  (0x1  << 27)    /* RW */\n#define MSDC_PATCH_BIT_INTDLSEL (0x1  << 28)    /* RW */\n#define MSDC_PATCH_BIT_SPCPUSH  (0x1  << 29)    /* RW */\n#define MSDC_PATCH_BIT_DECRCTMO (0x1  << 30)    /* RW */\n\n/* MSDC_PATCH_BIT1 mask */\n#define MSDC_PATCH_BIT1_WRDAT_CRCS  (0x7 << 3)\n#define MSDC_PATCH_BIT1_CMD_RSP     (0x7 << 0)\n\n/* MSDC_PAD_CTL0 mask */\n#define MSDC_PAD_CTL0_CLKDRVN   (0x7  << 0)     /* RW */\n#define MSDC_PAD_CTL0_CLKDRVP   (0x7  << 4)     /* RW */\n#define MSDC_PAD_CTL0_CLKSR     (0x1  << 8)     /* RW */\n#define MSDC_PAD_CTL0_CLKPD     (0x1  << 16)    /* RW */\n#define MSDC_PAD_CTL0_CLKPU     (0x1  << 17)    /* RW */\n#define MSDC_PAD_CTL0_CLKSMT    (0x1  << 18)    /* RW */\n#define MSDC_PAD_CTL0_CLKIES    (0x1  << 19)    /* RW */\n#define MSDC_PAD_CTL0_CLKTDSEL  (0xf  << 20)    /* RW */\n#define MSDC_PAD_CTL0_CLKRDSEL  (0xffUL << 24)   /* RW */\n\n/* MSDC_PAD_CTL1 mask */\n#define MSDC_PAD_CTL1_CMDDRVN   (0x7  << 0)     /* RW */\n#define MSDC_PAD_CTL1_CMDDRVP   (0x7  << 4)     /* RW */\n#define MSDC_PAD_CTL1_CMDSR     (0x1  << 8)     /* RW */\n#define MSDC_PAD_CTL1_CMDPD     (0x1  << 16)    /* RW */\n#define MSDC_PAD_CTL1_CMDPU     (0x1  << 17)    /* RW */\n#define MSDC_PAD_CTL1_CMDSMT    (0x1  << 18)    /* RW */\n#define MSDC_PAD_CTL1_CMDIES    (0x1  << 19)    /* RW */\n#define MSDC_PAD_CTL1_CMDTDSEL  (0xf  << 20)    /* RW */\n#define MSDC_PAD_CTL1_CMDRDSEL  (0xffUL << 24)   /* RW */\n\n/* MSDC_PAD_CTL2 mask */\n#define MSDC_PAD_CTL2_DATDRVN   (0x7  << 0)     /* RW */\n#define MSDC_PAD_CTL2_DATDRVP   (0x7  << 4)     /* RW */\n#define MSDC_PAD_CTL2_DATSR     (0x1  << 8)     /* RW */\n#define MSDC_PAD_CTL2_DATPD     (0x1  << 16)    /* RW */\n#define MSDC_PAD_CTL2_DATPU     (0x1  << 17)    /* RW */\n#define MSDC_PAD_CTL2_DATIES    (0x1  << 19)    /* RW */\n#define MSDC_PAD_CTL2_DATSMT    (0x1  << 18)    /* RW */\n#define MSDC_PAD_CTL2_DATTDSEL  (0xf  << 20)    /* RW */\n#define MSDC_PAD_CTL2_DATRDSEL  (0xffUL << 24)   /* RW */\n\n/* MSDC_PAD_TUNE mask */\n#define MSDC_PAD_TUNE_DATWRDLY  (0x1F << 0)     /* RW */\n#define MSDC_PAD_TUNE_DATRRDLY  (0x1F << 8)     /* RW */\n#define MSDC_PAD_TUNE_CMDRDLY   (0x1F << 16)    /* RW */\n#define MSDC_PAD_TUNE_CMDRRDLY  (0x1FUL << 22)  /* RW */\n#define MSDC_PAD_TUNE_CLKTXDLY  (0x1FUL << 27)  /* RW */\n\n/* MSDC_DAT_RDDLY0/1 mask */\n#define MSDC_DAT_RDDLY0_D0      (0x1F << 0)     /* RW */\n#define MSDC_DAT_RDDLY0_D1      (0x1F << 8)     /* RW */\n#define MSDC_DAT_RDDLY0_D2      (0x1F << 16)    /* RW */\n#define MSDC_DAT_RDDLY0_D3      (0x1F << 24)    /* RW */\n\n#define MSDC_DAT_RDDLY1_D4      (0x1F << 0)     /* RW */\n#define MSDC_DAT_RDDLY1_D5      (0x1F << 8)     /* RW */\n#define MSDC_DAT_RDDLY1_D6      (0x1F << 16)    /* RW */\n#define MSDC_DAT_RDDLY1_D7      (0x1F << 24)    /* RW */\n\n#define MSDC_CKGEN_MSDC_DLY_SEL   (0x1F << 10)\n#define MSDC_INT_DAT_LATCH_CK_SEL  (0x7 << 7)\n#define MSDC_CKGEN_MSDC_CK_SEL     (0x1 << 6)\n#define CARD_READY_FOR_DATA             (1 << 8)\n#define CARD_CURRENT_STATE(x)           ((x & 0x00001E00) >> 9)\n\n/*--------------------------------------------------------------------------*/\n/* Descriptor Structure                                                     */\n/*--------------------------------------------------------------------------*/\nstruct gpd {\n\tu32  hwo:1; /* could be changed by hw */\n\tu32  bdp:1;\n\tu32  rsv0:6;\n\tu32  chksum:8;\n\tu32  intr:1;\n\tu32  rsv1:15;\n\tvoid *next;\n\tvoid *ptr;\n\tu32  buflen:16;\n\tu32  extlen:8;\n\tu32  rsv2:8;\n\tu32  arg;\n\tu32  blknum;\n\tu32  cmd;\n};\n\nstruct bd {\n\tu32  eol:1;\n\tu32  rsv0:7;\n\tu32  chksum:8;\n\tu32  rsv1:1;\n\tu32  blkpad:1;\n\tu32  dwpad:1;\n\tu32  rsv2:13;\n\tvoid *next;\n\tvoid *ptr;\n\tu32  buflen:16;\n\tu32  rsv3:16;\n};\n\n/*--------------------------------------------------------------------------*/\n/* Register Debugging Structure                                             */\n/*--------------------------------------------------------------------------*/\n\nstruct msdc_cfg_reg {\n\tu32 msdc:1;\n\tu32 ckpwn:1;\n\tu32 rst:1;\n\tu32 pio:1;\n\tu32 ckdrven:1;\n\tu32 start18v:1;\n\tu32 pass18v:1;\n\tu32 ckstb:1;\n\tu32 ckdiv:8;\n\tu32 ckmod:2;\n\tu32 pad:14;\n};\n\nstruct msdc_iocon_reg {\n\tu32 sdr104cksel:1;\n\tu32 rsmpl:1;\n\tu32 dsmpl:1;\n\tu32 ddlysel:1;\n\tu32 ddr50ckd:1;\n\tu32 dsplsel:1;\n\tu32 pad1:10;\n\tu32 d0spl:1;\n\tu32 d1spl:1;\n\tu32 d2spl:1;\n\tu32 d3spl:1;\n\tu32 d4spl:1;\n\tu32 d5spl:1;\n\tu32 d6spl:1;\n\tu32 d7spl:1;\n\tu32 riscsz:1;\n\tu32 pad2:7;\n};\n\nstruct msdc_ps_reg {\n\tu32 cden:1;\n\tu32 cdsts:1;\n\tu32 pad1:10;\n\tu32 cddebounce:4;\n\tu32 dat:8;\n\tu32 cmd:1;\n\tu32 pad2:6;\n\tu32 wp:1;\n};\n\nstruct msdc_int_reg {\n\tu32 mmcirq:1;\n\tu32 cdsc:1;\n\tu32 pad1:1;\n\tu32 atocmdrdy:1;\n\tu32 atocmdtmo:1;\n\tu32 atocmdcrc:1;\n\tu32 dmaqempty:1;\n\tu32 sdioirq:1;\n\tu32 cmdrdy:1;\n\tu32 cmdtmo:1;\n\tu32 rspcrc:1;\n\tu32 csta:1;\n\tu32 xfercomp:1;\n\tu32 dxferdone:1;\n\tu32 dattmo:1;\n\tu32 datcrc:1;\n\tu32 atocmd19done:1;\n\tu32 pad2:15;\n};\n\nstruct msdc_inten_reg {\n\tu32 mmcirq:1;\n\tu32 cdsc:1;\n\tu32 pad1:1;\n\tu32 atocmdrdy:1;\n\tu32 atocmdtmo:1;\n\tu32 atocmdcrc:1;\n\tu32 dmaqempty:1;\n\tu32 sdioirq:1;\n\tu32 cmdrdy:1;\n\tu32 cmdtmo:1;\n\tu32 rspcrc:1;\n\tu32 csta:1;\n\tu32 xfercomp:1;\n\tu32 dxferdone:1;\n\tu32 dattmo:1;\n\tu32 datcrc:1;\n\tu32 atocmd19done:1;\n\tu32 pad2:15;\n};\n\nstruct msdc_fifocs_reg {\n\tu32 rxcnt:8;\n\tu32 pad1:8;\n\tu32 txcnt:8;\n\tu32 pad2:7;\n\tu32 clr:1;\n};\n\nstruct msdc_txdat_reg {\n\tu32 val;\n};\n\nstruct msdc_rxdat_reg {\n\tu32 val;\n};\n\nstruct sdc_cfg_reg {\n\tu32 sdiowkup:1;\n\tu32 inswkup:1;\n\tu32 pad1:14;\n\tu32 buswidth:2;\n\tu32 pad2:1;\n\tu32 sdio:1;\n\tu32 sdioide:1;\n\tu32 intblkgap:1;\n\tu32 pad4:2;\n\tu32 dtoc:8;\n};\n\nstruct sdc_cmd_reg {\n\tu32 cmd:6;\n\tu32 brk:1;\n\tu32 rsptyp:3;\n\tu32 pad1:1;\n\tu32 dtype:2;\n\tu32 rw:1;\n\tu32 stop:1;\n\tu32 goirq:1;\n\tu32 blklen:12;\n\tu32 atocmd:2;\n\tu32 volswth:1;\n\tu32 pad2:1;\n};\n\nstruct sdc_arg_reg {\n\tu32 arg;\n};\n\nstruct sdc_sts_reg {\n\tu32 sdcbusy:1;\n\tu32 cmdbusy:1;\n\tu32 pad:29;\n\tu32 swrcmpl:1;\n};\n\nstruct sdc_resp0_reg {\n\tu32 val;\n};\n\nstruct sdc_resp1_reg {\n\tu32 val;\n};\n\nstruct sdc_resp2_reg {\n\tu32 val;\n};\n\nstruct sdc_resp3_reg {\n\tu32 val;\n};\n\nstruct sdc_blknum_reg {\n\tu32 num;\n};\n\nstruct sdc_csts_reg {\n\tu32 sts;\n};\n\nstruct sdc_cstsen_reg {\n\tu32 sts;\n};\n\nstruct sdc_datcrcsts_reg {\n\tu32 datcrcsts:8;\n\tu32 ddrcrcsts:4;\n\tu32 pad:20;\n};\n\nstruct emmc_cfg0_reg {\n\tu32 bootstart:1;\n\tu32 bootstop:1;\n\tu32 bootmode:1;\n\tu32 pad1:9;\n\tu32 bootwaidly:3;\n\tu32 bootsupp:1;\n\tu32 pad2:16;\n};\n\nstruct emmc_cfg1_reg {\n\tu32 bootcrctmc:16;\n\tu32 pad:4;\n\tu32 bootacktmc:12;\n};\n\nstruct emmc_sts_reg {\n\tu32 bootcrcerr:1;\n\tu32 bootackerr:1;\n\tu32 bootdattmo:1;\n\tu32 bootacktmo:1;\n\tu32 bootupstate:1;\n\tu32 bootackrcv:1;\n\tu32 bootdatrcv:1;\n\tu32 pad:25;\n};\n\nstruct emmc_iocon_reg {\n\tu32 bootrst:1;\n\tu32 pad:31;\n};\n\nstruct msdc_acmd_resp_reg {\n\tu32 val;\n};\n\nstruct msdc_acmd19_trg_reg {\n\tu32 tunesel:4;\n\tu32 pad:28;\n};\n\nstruct msdc_acmd19_sts_reg {\n\tu32 val;\n};\n\nstruct msdc_dma_sa_reg {\n\tu32 addr;\n};\n\nstruct msdc_dma_ca_reg {\n\tu32 addr;\n};\n\nstruct msdc_dma_ctrl_reg {\n\tu32 start:1;\n\tu32 stop:1;\n\tu32 resume:1;\n\tu32 pad1:5;\n\tu32 mode:1;\n\tu32 pad2:1;\n\tu32 lastbuf:1;\n\tu32 pad3:1;\n\tu32 brustsz:3;\n\tu32 pad4:1;\n\tu32 xfersz:16;\n};\n\nstruct msdc_dma_cfg_reg {\n\tu32 status:1;\n\tu32 decsen:1;\n\tu32 pad1:2;\n\tu32 bdcsen:1;\n\tu32 gpdcsen:1;\n\tu32 pad2:26;\n};\n\nstruct msdc_dbg_sel_reg {\n\tu32 sel:16;\n\tu32 pad2:16;\n};\n\nstruct msdc_dbg_out_reg {\n\tu32 val;\n};\n\nstruct msdc_pad_ctl0_reg {\n\tu32 clkdrvn:3;\n\tu32 rsv0:1;\n\tu32 clkdrvp:3;\n\tu32 rsv1:1;\n\tu32 clksr:1;\n\tu32 rsv2:7;\n\tu32 clkpd:1;\n\tu32 clkpu:1;\n\tu32 clksmt:1;\n\tu32 clkies:1;\n\tu32 clktdsel:4;\n\tu32 clkrdsel:8;\n};\n\nstruct msdc_pad_ctl1_reg {\n\tu32 cmddrvn:3;\n\tu32 rsv0:1;\n\tu32 cmddrvp:3;\n\tu32 rsv1:1;\n\tu32 cmdsr:1;\n\tu32 rsv2:7;\n\tu32 cmdpd:1;\n\tu32 cmdpu:1;\n\tu32 cmdsmt:1;\n\tu32 cmdies:1;\n\tu32 cmdtdsel:4;\n\tu32 cmdrdsel:8;\n};\n\nstruct msdc_pad_ctl2_reg {\n\tu32 datdrvn:3;\n\tu32 rsv0:1;\n\tu32 datdrvp:3;\n\tu32 rsv1:1;\n\tu32 datsr:1;\n\tu32 rsv2:7;\n\tu32 datpd:1;\n\tu32 datpu:1;\n\tu32 datsmt:1;\n\tu32 daties:1;\n\tu32 dattdsel:4;\n\tu32 datrdsel:8;\n};\n\nstruct msdc_pad_tune_reg {\n\tu32 wrrxdly:3;\n\tu32 pad1:5;\n\tu32 rdrxdly:8;\n\tu32 pad2:16;\n};\n\nstruct msdc_dat_rddly0 {\n\tu32 dat0:5;\n\tu32 rsv0:3;\n\tu32 dat1:5;\n\tu32 rsv1:3;\n\tu32 dat2:5;\n\tu32 rsv2:3;\n\tu32 dat3:5;\n\tu32 rsv3:3;\n};\n\nstruct msdc_dat_rddly1 {\n\tu32 dat4:5;\n\tu32 rsv4:3;\n\tu32 dat5:5;\n\tu32 rsv5:3;\n\tu32 dat6:5;\n\tu32 rsv6:3;\n\tu32 dat7:5;\n\tu32 rsv7:3;\n};\n\nstruct msdc_hw_dbg_reg {\n\tu32 dbg0sel:8;\n\tu32 dbg1sel:6;\n\tu32 pad1:2;\n\tu32 dbg2sel:6;\n\tu32 pad2:2;\n\tu32 dbg3sel:6;\n\tu32 pad3:2;\n};\n\nstruct msdc_version_reg {\n\tu32 val;\n};\n\nstruct msdc_eco_ver_reg {\n\tu32 val;\n};\n\nstruct msdc_regs {\n\tstruct msdc_cfg_reg        msdc_cfg;      /* base+0x00h */\n\tstruct msdc_iocon_reg      msdc_iocon;    /* base+0x04h */\n\tstruct msdc_ps_reg         msdc_ps;       /* base+0x08h */\n\tstruct msdc_int_reg        msdc_int;      /* base+0x0ch */\n\tstruct msdc_inten_reg      msdc_inten;    /* base+0x10h */\n\tstruct msdc_fifocs_reg     msdc_fifocs;   /* base+0x14h */\n\tstruct msdc_txdat_reg      msdc_txdat;    /* base+0x18h */\n\tstruct msdc_rxdat_reg      msdc_rxdat;    /* base+0x1ch */\n\tu32                 rsv1[4];\n\tstruct sdc_cfg_reg         sdc_cfg;       /* base+0x30h */\n\tstruct sdc_cmd_reg         sdc_cmd;       /* base+0x34h */\n\tstruct sdc_arg_reg         sdc_arg;       /* base+0x38h */\n\tstruct sdc_sts_reg         sdc_sts;       /* base+0x3ch */\n\tstruct sdc_resp0_reg       sdc_resp0;     /* base+0x40h */\n\tstruct sdc_resp1_reg       sdc_resp1;     /* base+0x44h */\n\tstruct sdc_resp2_reg       sdc_resp2;     /* base+0x48h */\n\tstruct sdc_resp3_reg       sdc_resp3;     /* base+0x4ch */\n\tstruct sdc_blknum_reg      sdc_blknum;    /* base+0x50h */\n\tu32                 rsv2[1];\n\tstruct sdc_csts_reg        sdc_csts;      /* base+0x58h */\n\tstruct sdc_cstsen_reg      sdc_cstsen;    /* base+0x5ch */\n\tstruct sdc_datcrcsts_reg   sdc_dcrcsta;   /* base+0x60h */\n\tu32                 rsv3[3];\n\tstruct emmc_cfg0_reg       emmc_cfg0;     /* base+0x70h */\n\tstruct emmc_cfg1_reg       emmc_cfg1;     /* base+0x74h */\n\tstruct emmc_sts_reg        emmc_sts;      /* base+0x78h */\n\tstruct emmc_iocon_reg      emmc_iocon;    /* base+0x7ch */\n\tstruct msdc_acmd_resp_reg  acmd_resp;     /* base+0x80h */\n\tstruct msdc_acmd19_trg_reg acmd19_trg;    /* base+0x84h */\n\tstruct msdc_acmd19_sts_reg acmd19_sts;    /* base+0x88h */\n\tu32                 rsv4[1];\n\tstruct msdc_dma_sa_reg     dma_sa;        /* base+0x90h */\n\tstruct msdc_dma_ca_reg     dma_ca;        /* base+0x94h */\n\tstruct msdc_dma_ctrl_reg   dma_ctrl;      /* base+0x98h */\n\tstruct msdc_dma_cfg_reg    dma_cfg;       /* base+0x9ch */\n\tstruct msdc_dbg_sel_reg    dbg_sel;       /* base+0xa0h */\n\tstruct msdc_dbg_out_reg    dbg_out;       /* base+0xa4h */\n\tu32                 rsv5[2];\n\tu32                 patch0;        /* base+0xb0h */\n\tu32                 patch1;        /* base+0xb4h */\n\tu32                 rsv6[10];\n\tstruct msdc_pad_ctl0_reg   pad_ctl0;      /* base+0xe0h */\n\tstruct msdc_pad_ctl1_reg   pad_ctl1;      /* base+0xe4h */\n\tstruct msdc_pad_ctl2_reg   pad_ctl2;      /* base+0xe8h */\n\tstruct msdc_pad_tune_reg   pad_tune;      /* base+0xech */\n\tstruct msdc_dat_rddly0     dat_rddly0;    /* base+0xf0h */\n\tstruct msdc_dat_rddly1     dat_rddly1;    /* base+0xf4h */\n\tstruct msdc_hw_dbg_reg     hw_dbg;        /* base+0xf8h */\n\tu32                 rsv7[1];\n\tstruct msdc_version_reg    version;       /* base+0x100h */\n\tstruct msdc_eco_ver_reg    eco_ver;       /* base+0x104h */\n};\n\nstruct msdc_dma {\n\tu32 sglen;                   /* size of scatter list */\n\tstruct scatterlist *sg;      /* I/O scatter list */\n\tu8  mode;                    /* dma mode        */\n\n\tstruct gpd *gpd;                  /* pointer to gpd array */\n\tstruct bd  *bd;                   /* pointer to bd array */\n\tdma_addr_t gpd_addr;         /* the physical address of gpd array */\n\tdma_addr_t bd_addr;          /* the physical address of bd array */\n};\n\nstruct msdc_host {\n\tstruct msdc_hw              *hw;\n\n\tstruct mmc_host             *mmc;           /* mmc structure */\n\tstruct mmc_command          *cmd;\n\tstruct mmc_data             *data;\n\tstruct mmc_request          *mrq;\n\tint                         cmd_rsp;\n\n\tint                         error;\n\tspinlock_t                  lock;           /* mutex */\n\tstruct semaphore            sem;\n\n\tu32                         blksz;          /* host block size */\n\tvoid __iomem                *base;           /* host base address */\n\tint                         id;             /* host id */\n\tint                         pwr_ref;        /* core power reference count */\n\n\tu32                         xfer_size;      /* total transferred size */\n\n\tstruct msdc_dma             dma;            /* dma channel */\n\tu32                         dma_xfer_size;  /* dma transfer size in bytes */\n\n\tu32                         timeout_ns;     /* data timeout ns */\n\tu32                         timeout_clks;   /* data timeout clks */\n\n\tint                         irq;            /* host interrupt */\n\n\tstruct delayed_work\t\tcard_delaywork;\n\n\tstruct completion           cmd_done;\n\tstruct completion           xfer_done;\n\tstruct pm_message           pm_state;\n\n\tu32                         mclk;           /* mmc subsystem clock */\n\tu32                         hclk;           /* host clock speed */\n\tu32                         sclk;           /* SD/MS clock speed */\n\tu8                          core_clkon;     /* Host core clock on ? */\n\tu8                          card_clkon;     /* Card clock on ? */\n\tu8                          core_power;     /* core power */\n\tu8                          power_mode;     /* host power mode */\n\tu8                          card_inserted;  /* card inserted ? */\n\tu8                          suspend;        /* host suspended ? */\n\tu8                          app_cmd;        /* for app command */\n\tu32                         app_cmd_arg;\n};\n\n#define sdr_read8(reg)            readb(reg)\n#define sdr_read32(reg)           readl(reg)\n#define sdr_write8(reg, val)      writeb(val, reg)\n#define sdr_write32(reg, val)     writel(val, reg)\n\nstatic inline void sdr_set_bits(void __iomem *reg, u32 bs)\n{\n\tu32 val = readl(reg);\n\n\tval |= bs;\n\twritel(val, reg);\n}\n\nstatic inline void sdr_clr_bits(void __iomem *reg, u32 bs)\n{\n\tu32 val = readl(reg);\n\n\tval &= ~bs;\n\twritel(val, reg);\n}\n\nstatic inline void sdr_set_field(void __iomem *reg, u32 field, u32 val)\n{\n\tunsigned int tv = readl(reg);\n\n\ttv &= ~field;\n\ttv |= ((val) << (ffs((unsigned int)field) - 1));\n\twritel(tv, reg);\n}\n\nstatic inline void sdr_get_field(void __iomem *reg, u32 field, u32 *val)\n{\n\tunsigned int tv = readl(reg);\n\t*val = ((tv & field) >> (ffs((unsigned int)field) - 1));\n}\n\n#endif\n"
  },
  {
    "path": "target/linux/ramips/files/drivers/mmc/host/mtk-mmc/sd.c",
    "content": "/* Copyright Statement:\n *\n * This software/firmware and related documentation (\"MediaTek Software\") are\n * protected under relevant copyright laws. The information contained herein\n * is confidential and proprietary to MediaTek Inc. and/or its licensors.\n * Without the prior written permission of MediaTek inc. and/or its licensors,\n * any reproduction, modification, use or disclosure of MediaTek Software,\n * and information contained herein, in whole or in part, shall be strictly prohibited.\n *\n * MediaTek Inc. (C) 2010. All rights reserved.\n *\n * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES\n * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS (\"MEDIATEK SOFTWARE\")\n * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON\n * AN \"AS-IS\" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,\n * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF\n * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.\n * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE\n * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR\n * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH\n * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES\n * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES\n * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK\n * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR\n * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND\n * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,\n * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,\n * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO\n * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.\n *\n * The following software/firmware and/or related documentation (\"MediaTek Software\")\n * have been modified by MediaTek Inc. All revisions are subject to any receiver's\n * applicable license agreements with MediaTek Inc.\n */\n\n#include <linux/module.h>\n#include <linux/delay.h>\n#include <linux/dma-mapping.h>\n#include <linux/spinlock.h>\n#include <linux/platform_device.h>\n#include <linux/interrupt.h>\n#include <linux/of.h>\n\n#include <linux/mmc/host.h>\n#include <linux/mmc/mmc.h>\n#include <linux/mmc/sd.h>\n#include <linux/mmc/sdio.h>\n\n#include <asm/mach-ralink/ralink_regs.h>\n\n#include \"board.h\"\n#include \"dbg.h\"\n#include \"mt6575_sd.h\"\n\n//#define IRQ_SDC 14\t//MT7620 /*FIXME*/\n#ifdef CONFIG_SOC_MT7621\n#define RALINK_SYSCTL_BASE\t\t0xbe000000\n#define RALINK_MSDC_BASE\t\t0xbe130000\n#else\n#define RALINK_SYSCTL_BASE\t\t0xb0000000\n#define RALINK_MSDC_BASE\t\t0xb0130000\n#endif\n#define IRQ_SDC\t\t\t22\t/*FIXME*/\n\n#define DRV_NAME            \"mtk-sd\"\n\n#if defined(CONFIG_SOC_MT7620)\n#define HOST_MAX_MCLK       (48000000) /* +/- by chhung */\n#elif defined(CONFIG_SOC_MT7621)\n#define HOST_MAX_MCLK       (50000000) /* +/- by chhung */\n#endif\n#define HOST_MIN_MCLK       (260000)\n\n#define HOST_MAX_BLKSZ      (2048)\n\n#define MSDC_OCR_AVAIL      (MMC_VDD_28_29 | MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33)\n\n#define GPIO_PULL_DOWN      (0)\n#define GPIO_PULL_UP        (1)\n\n#if 0 /* --- by chhung */\n#define MSDC_CLKSRC_REG     (0xf100000C)\n#define PDN_REG           (0xF1000010)\n#endif /* end of --- */\n\n#define DEFAULT_DEBOUNCE    (8)       /* 8 cycles */\n#define DEFAULT_DTOC        (40)      /* data timeout counter. 65536x40 sclk. */\n\n#define CMD_TIMEOUT         (HZ / 10)     /* 100ms */\n#define DAT_TIMEOUT         (HZ / 2 * 5)  /* 500ms x5 */\n\n#define MAX_DMA_CNT         (64 * 1024 - 512)   /* a single transaction for WIFI may be 50K*/\n\n#define MAX_GPD_NUM         (1 + 1)  /* one null gpd */\n#define MAX_BD_NUM          (1024)\n#define MAX_BD_PER_GPD      (MAX_BD_NUM)\n\n#define MAX_HW_SGMTS        (MAX_BD_NUM)\n#define MAX_PHY_SGMTS       (MAX_BD_NUM)\n#define MAX_SGMT_SZ         (MAX_DMA_CNT)\n#define MAX_REQ_SZ          (MAX_SGMT_SZ * 8)\n\nstatic int cd_active_low = 1;\n\n//=================================\n#define PERI_MSDC0_PDN      (15)\n//#define PERI_MSDC1_PDN    (16)\n//#define PERI_MSDC2_PDN    (17)\n//#define PERI_MSDC3_PDN    (18)\n\n#if 0 /* --- by chhung */\n/* gate means clock power down */\nstatic int g_clk_gate = 0;\n#define msdc_gate_clock(id) \\\n\tdo {\t\t\t\t\t       \\\n\t\tg_clk_gate &= ~(1 << ((id) + PERI_MSDC0_PDN));\t\\\n\t} while (0)\n/* not like power down register. 1 means clock on. */\n#define msdc_ungate_clock(id) \\\n\tdo {\t\t\t\t\t    \\\n\t\tg_clk_gate |= 1 << ((id) + PERI_MSDC0_PDN);\t\\\n\t} while (0)\n\n// do we need sync object or not\nvoid msdc_clk_status(int *status)\n{\n\t*status = g_clk_gate;\n}\n#endif /* end of --- */\n\n/* +++ by chhung */\nstruct msdc_hw msdc0_hw = {\n\t.clk_src        = 0,\n\t.flags          = MSDC_CD_PIN_EN | MSDC_REMOVABLE,\n//\t.flags          = MSDC_WP_PIN_EN | MSDC_CD_PIN_EN | MSDC_REMOVABLE,\n};\n\n/* end of +++ */\n\nstatic int msdc_rsp[] = {\n\t0,  /* RESP_NONE */\n\t1,  /* RESP_R1 */\n\t2,  /* RESP_R2 */\n\t3,  /* RESP_R3 */\n\t4,  /* RESP_R4 */\n\t1,  /* RESP_R5 */\n\t1,  /* RESP_R6 */\n\t1,  /* RESP_R7 */\n\t7,  /* RESP_R1b */\n};\n\n#define msdc_txfifocnt()   ((sdr_read32(MSDC_FIFOCS) & MSDC_FIFOCS_TXCNT) >> 16)\n#define msdc_rxfifocnt()   ((sdr_read32(MSDC_FIFOCS) & MSDC_FIFOCS_RXCNT) >> 0)\n#define msdc_fifo_write32(v)   sdr_write32(MSDC_TXDATA, (v))\n#define msdc_fifo_write8(v)    sdr_write8(MSDC_TXDATA, (v))\n#define msdc_fifo_read32()   sdr_read32(MSDC_RXDATA)\n#define msdc_fifo_read8()    sdr_read8(MSDC_RXDATA)\n\n#define msdc_dma_on()        sdr_clr_bits(MSDC_CFG, MSDC_CFG_PIO)\n\n#define msdc_retry(expr, retry, cnt) \\\n\tdo {\t\t\t\t\t\t\t\t\\\n\t\tint backup = cnt;\t\t\t\t\t\\\n\t\twhile (retry) {\t\t\t\t\t\t\\\n\t\t\tif (!(expr))\t\t\t\t\t\\\n\t\t\t\tbreak;\t\t\t\t\t\\\n\t\t\tif (cnt-- == 0) {\t\t\t\t\\\n\t\t\t\tretry--; mdelay(1); cnt = backup;\t\\\n\t\t\t}\t\t\t\t\t\t\\\n\t\t}\t\t\t\t\t\t\t\\\n\t\tWARN_ON(retry == 0);\t\t\t\t\t\\\n\t} while (0)\n\nstatic void msdc_reset_hw(struct msdc_host *host)\n{\n\tvoid __iomem *base = host->base;\n\n\tsdr_set_bits(MSDC_CFG, MSDC_CFG_RST);\n\twhile (sdr_read32(MSDC_CFG) & MSDC_CFG_RST)\n\t\tcpu_relax();\n}\n\n#define msdc_clr_int() \\\n\tdo {\t\t\t\t\t\t\t\\\n\t\tvolatile u32 val = sdr_read32(MSDC_INT);\t\\\n\t\tsdr_write32(MSDC_INT, val);\t\t\t\\\n\t} while (0)\n\n#define msdc_clr_fifo() \\\n\tdo {\t\t\t\t\t\t\t\t\\\n\t\tint retry = 3, cnt = 1000;\t\t\t\t\\\n\t\tsdr_set_bits(MSDC_FIFOCS, MSDC_FIFOCS_CLR);\t\t\\\n\t\tmsdc_retry(sdr_read32(MSDC_FIFOCS) & MSDC_FIFOCS_CLR, retry, cnt); \\\n\t} while (0)\n\n#define msdc_irq_save(val) \\\n\tdo {\t\t\t\t\t\\\n\t\tval = sdr_read32(MSDC_INTEN);\t\\\n\t\tsdr_clr_bits(MSDC_INTEN, val);\t\\\n\t} while (0)\n\n#define msdc_irq_restore(val) \\\n\tdo {\t\t\t\t\t\\\n\t\tsdr_set_bits(MSDC_INTEN, val);\t\\\n\t} while (0)\n\n/* clock source for host: global */\n#if defined(CONFIG_SOC_MT7620)\nstatic u32 hclks[] = {48000000}; /* +/- by chhung */\n#elif defined(CONFIG_SOC_MT7621)\nstatic u32 hclks[] = {50000000}; /* +/- by chhung */\n#endif\n\n//============================================\n// the power for msdc host controller: global\n//    always keep the VMC on.\n//============================================\n#define msdc_vcore_on(host) \\\n\tdo {\t\t\t\t\t\t\t\t\\\n\t\tINIT_MSG(\"[+]VMC ref. count<%d>\", ++host->pwr_ref);\t\\\n\t\t(void)hwPowerOn(MT65XX_POWER_LDO_VMC, VOL_3300, \"SD\");\t\\\n\t} while (0)\n#define msdc_vcore_off(host) \\\n\tdo {\t\t\t\t\t\t\t\t\\\n\t\tINIT_MSG(\"[-]VMC ref. count<%d>\", --host->pwr_ref);\t\\\n\t\t(void)hwPowerDown(MT65XX_POWER_LDO_VMC, \"SD\");\t\t\\\n\t} while (0)\n\n//====================================\n// the vdd output for card: global\n//   always keep the VMCH on.\n//====================================\n#define msdc_vdd_on(host) \\\n\tdo {\t\t\t\t\t\t\t\t\\\n\t\t(void)hwPowerOn(MT65XX_POWER_LDO_VMCH, VOL_3300, \"SD\"); \\\n\t} while (0)\n#define msdc_vdd_off(host) \\\n\tdo {\t\t\t\t\t\t\t\\\n\t\t(void)hwPowerDown(MT65XX_POWER_LDO_VMCH, \"SD\"); \\\n\t} while (0)\n\n#define sdc_is_busy()          (sdr_read32(SDC_STS) & SDC_STS_SDCBUSY)\n#define sdc_is_cmd_busy()      (sdr_read32(SDC_STS) & SDC_STS_CMDBUSY)\n\n#define sdc_send_cmd(cmd, arg) \\\n\tdo {\t\t\t\t\t\\\n\t\tsdr_write32(SDC_ARG, (arg));\t\\\n\t\tsdr_write32(SDC_CMD, (cmd));\t\\\n\t} while (0)\n\n// can modify to read h/w register.\n//#define is_card_present(h)   ((sdr_read32(MSDC_PS) & MSDC_PS_CDSTS) ? 0 : 1);\n#define is_card_present(h)     (((struct msdc_host *)(h))->card_inserted)\n\n/* +++ by chhung */\n#ifndef __ASSEMBLY__\n#define PHYSADDR(a)             (((unsigned long)(a)) & 0x1fffffff)\n#else\n#define PHYSADDR(a)             ((a) & 0x1fffffff)\n#endif\n/* end of +++ */\nstatic unsigned int msdc_do_command(struct msdc_host   *host,\n\t\t\t\t    struct mmc_command *cmd,\n\t\t\t\t    int                 tune,\n\t\t\t\t    unsigned long       timeout);\n\nstatic int msdc_tune_cmdrsp(struct msdc_host *host, struct mmc_command *cmd);\n\n#ifdef MT6575_SD_DEBUG\nstatic void msdc_dump_card_status(struct msdc_host *host, u32 status)\n{\n/* N_MSG is currently a no-op */\n#if 0\n\tstatic char *state[] = {\n\t\t\"Idle\",\t\t\t/* 0 */\n\t\t\"Ready\",\t\t/* 1 */\n\t\t\"Ident\",\t\t/* 2 */\n\t\t\"Stby\",\t\t\t/* 3 */\n\t\t\"Tran\",\t\t\t/* 4 */\n\t\t\"Data\",\t\t\t/* 5 */\n\t\t\"Rcv\",\t\t\t/* 6 */\n\t\t\"Prg\",\t\t\t/* 7 */\n\t\t\"Dis\",\t\t\t/* 8 */\n\t\t\"Reserved\",\t\t/* 9 */\n\t\t\"Reserved\",\t\t/* 10 */\n\t\t\"Reserved\",\t\t/* 11 */\n\t\t\"Reserved\",\t\t/* 12 */\n\t\t\"Reserved\",\t\t/* 13 */\n\t\t\"Reserved\",\t\t/* 14 */\n\t\t\"I/O mode\",\t\t/* 15 */\n\t};\n#endif\n\tif (status & R1_OUT_OF_RANGE)\n\t\tN_MSG(RSP, \"[CARD_STATUS] Out of Range\");\n\tif (status & R1_ADDRESS_ERROR)\n\t\tN_MSG(RSP, \"[CARD_STATUS] Address Error\");\n\tif (status & R1_BLOCK_LEN_ERROR)\n\t\tN_MSG(RSP, \"[CARD_STATUS] Block Len Error\");\n\tif (status & R1_ERASE_SEQ_ERROR)\n\t\tN_MSG(RSP, \"[CARD_STATUS] Erase Seq Error\");\n\tif (status & R1_ERASE_PARAM)\n\t\tN_MSG(RSP, \"[CARD_STATUS] Erase Param\");\n\tif (status & R1_WP_VIOLATION)\n\t\tN_MSG(RSP, \"[CARD_STATUS] WP Violation\");\n\tif (status & R1_CARD_IS_LOCKED)\n\t\tN_MSG(RSP, \"[CARD_STATUS] Card is Locked\");\n\tif (status & R1_LOCK_UNLOCK_FAILED)\n\t\tN_MSG(RSP, \"[CARD_STATUS] Lock/Unlock Failed\");\n\tif (status & R1_COM_CRC_ERROR)\n\t\tN_MSG(RSP, \"[CARD_STATUS] Command CRC Error\");\n\tif (status & R1_ILLEGAL_COMMAND)\n\t\tN_MSG(RSP, \"[CARD_STATUS] Illegal Command\");\n\tif (status & R1_CARD_ECC_FAILED)\n\t\tN_MSG(RSP, \"[CARD_STATUS] Card ECC Failed\");\n\tif (status & R1_CC_ERROR)\n\t\tN_MSG(RSP, \"[CARD_STATUS] CC Error\");\n\tif (status & R1_ERROR)\n\t\tN_MSG(RSP, \"[CARD_STATUS] Error\");\n\tif (status & R1_UNDERRUN)\n\t\tN_MSG(RSP, \"[CARD_STATUS] Underrun\");\n\tif (status & R1_OVERRUN)\n\t\tN_MSG(RSP, \"[CARD_STATUS] Overrun\");\n\tif (status & R1_CID_CSD_OVERWRITE)\n\t\tN_MSG(RSP, \"[CARD_STATUS] CID/CSD Overwrite\");\n\tif (status & R1_WP_ERASE_SKIP)\n\t\tN_MSG(RSP, \"[CARD_STATUS] WP Eraser Skip\");\n\tif (status & R1_CARD_ECC_DISABLED)\n\t\tN_MSG(RSP, \"[CARD_STATUS] Card ECC Disabled\");\n\tif (status & R1_ERASE_RESET)\n\t\tN_MSG(RSP, \"[CARD_STATUS] Erase Reset\");\n\tif (status & R1_READY_FOR_DATA)\n\t\tN_MSG(RSP, \"[CARD_STATUS] Ready for Data\");\n\tif (status & R1_SWITCH_ERROR)\n\t\tN_MSG(RSP, \"[CARD_STATUS] Switch error\");\n\tif (status & R1_APP_CMD)\n\t\tN_MSG(RSP, \"[CARD_STATUS] App Command\");\n\n\tN_MSG(RSP, \"[CARD_STATUS] '%s' State\", state[R1_CURRENT_STATE(status)]);\n}\n\nstatic void msdc_dump_ocr_reg(struct msdc_host *host, u32 resp)\n{\n\tif (resp & (1 << 7))\n\t\tN_MSG(RSP, \"[OCR] Low Voltage Range\");\n\tif (resp & (1 << 15))\n\t\tN_MSG(RSP, \"[OCR] 2.7-2.8 volt\");\n\tif (resp & (1 << 16))\n\t\tN_MSG(RSP, \"[OCR] 2.8-2.9 volt\");\n\tif (resp & (1 << 17))\n\t\tN_MSG(RSP, \"[OCR] 2.9-3.0 volt\");\n\tif (resp & (1 << 18))\n\t\tN_MSG(RSP, \"[OCR] 3.0-3.1 volt\");\n\tif (resp & (1 << 19))\n\t\tN_MSG(RSP, \"[OCR] 3.1-3.2 volt\");\n\tif (resp & (1 << 20))\n\t\tN_MSG(RSP, \"[OCR] 3.2-3.3 volt\");\n\tif (resp & (1 << 21))\n\t\tN_MSG(RSP, \"[OCR] 3.3-3.4 volt\");\n\tif (resp & (1 << 22))\n\t\tN_MSG(RSP, \"[OCR] 3.4-3.5 volt\");\n\tif (resp & (1 << 23))\n\t\tN_MSG(RSP, \"[OCR] 3.5-3.6 volt\");\n\tif (resp & (1 << 24))\n\t\tN_MSG(RSP, \"[OCR] Switching to 1.8V Accepted (S18A)\");\n\tif (resp & (1 << 30))\n\t\tN_MSG(RSP, \"[OCR] Card Capacity Status (CCS)\");\n\tif (resp & (1 << 31))\n\t\tN_MSG(RSP, \"[OCR] Card Power Up Status (Idle)\");\n\telse\n\t\tN_MSG(RSP, \"[OCR] Card Power Up Status (Busy)\");\n}\n\nstatic void msdc_dump_rca_resp(struct msdc_host *host, u32 resp)\n{\n\tu32 status = (((resp >> 15) & 0x1) << 23) |\n\t\t     (((resp >> 14) & 0x1) << 22) |\n\t\t     (((resp >> 13) & 0x1) << 19) |\n\t\t     (resp & 0x1fff);\n\n\tN_MSG(RSP, \"[RCA] 0x%.4x\", resp >> 16);\n\tmsdc_dump_card_status(host, status);\n}\n\nstatic void msdc_dump_io_resp(struct msdc_host *host, u32 resp)\n{\n\tu32 flags = (resp >> 8) & 0xFF;\n#if 0\n\tchar *state[] = {\"DIS\", \"CMD\", \"TRN\", \"RFU\"};\n#endif\n\tif (flags & (1 << 7))\n\t\tN_MSG(RSP, \"[IO] COM_CRC_ERR\");\n\tif (flags & (1 << 6))\n\t\tN_MSG(RSP, \"[IO] Illgal command\");\n\tif (flags & (1 << 3))\n\t\tN_MSG(RSP, \"[IO] Error\");\n\tif (flags & (1 << 2))\n\t\tN_MSG(RSP, \"[IO] RFU\");\n\tif (flags & (1 << 1))\n\t\tN_MSG(RSP, \"[IO] Function number error\");\n\tif (flags & (1 << 0))\n\t\tN_MSG(RSP, \"[IO] Out of range\");\n\n\tN_MSG(RSP, \"[IO] State: %s, Data:0x%x\", state[(resp >> 12) & 0x3], resp & 0xFF);\n}\n#endif\n\nstatic void msdc_set_timeout(struct msdc_host *host, u32 ns, u32 clks)\n{\n\tvoid __iomem *base = host->base;\n\tu32 timeout, clk_ns;\n\n\thost->timeout_ns   = ns;\n\thost->timeout_clks = clks;\n\n\tclk_ns  = 1000000000UL / host->sclk;\n\ttimeout = ns / clk_ns + clks;\n\ttimeout = timeout >> 16; /* in 65536 sclk cycle unit */\n\ttimeout = timeout > 1 ? timeout - 1 : 0;\n\ttimeout = timeout > 255 ? 255 : timeout;\n\n\tsdr_set_field(SDC_CFG, SDC_CFG_DTOC, timeout);\n\n\tN_MSG(OPS, \"Set read data timeout: %dns %dclks -> %d x 65536 cycles\",\n\t      ns, clks, timeout + 1);\n}\n\nstatic void msdc_tasklet_card(struct work_struct *work)\n{\n\tstruct msdc_host *host = (struct msdc_host *)container_of(work,\n\t\t\t\tstruct msdc_host, card_delaywork.work);\n\tvoid __iomem *base = host->base;\n\tu32 inserted;\n\tu32 status = 0;\n    //u32 change = 0;\n\n\tspin_lock(&host->lock);\n\n\tstatus = sdr_read32(MSDC_PS);\n\tif (cd_active_low)\n\t\tinserted = (status & MSDC_PS_CDSTS) ? 0 : 1;\n\telse\n\t\tinserted = (status & MSDC_PS_CDSTS) ? 1 : 0;\n\tif (host->mmc->caps & MMC_CAP_NEEDS_POLL)\n\t\tinserted = 1;\n\n#if 0\n\tchange = host->card_inserted ^ inserted;\n\thost->card_inserted = inserted;\n\n\tif (change && !host->suspend) {\n\t\tif (inserted)\n\t\t\thost->mmc->f_max = HOST_MAX_MCLK;  // work around\n\t\tmmc_detect_change(host->mmc, msecs_to_jiffies(20));\n\t}\n#else  /* Make sure: handle the last interrupt */\n\thost->card_inserted = inserted;\n\n\tif (!host->suspend) {\n\t\thost->mmc->f_max = HOST_MAX_MCLK;\n\t\tmmc_detect_change(host->mmc, msecs_to_jiffies(20));\n\t}\n\n\tIRQ_MSG(\"card found<%s>\", inserted ? \"inserted\" : \"removed\");\n#endif\n\n\tspin_unlock(&host->lock);\n}\n\n#if 0 /* --- by chhung */\n/* For E2 only */\nstatic u8 clk_src_bit[4] = {\n\t0, 3, 5, 7\n};\n\nstatic void msdc_select_clksrc(struct msdc_host *host, unsigned char clksrc)\n{\n\tu32 val;\n\tvoid __iomem *base = host->base;\n\n\tBUG_ON(clksrc > 3);\n\tINIT_MSG(\"set clock source to <%d>\", clksrc);\n\n\tval = sdr_read32(MSDC_CLKSRC_REG);\n\tif (sdr_read32(MSDC_ECO_VER) >= 4) {\n\t\tval &= ~(0x3  << clk_src_bit[host->id]);\n\t\tval |= clksrc << clk_src_bit[host->id];\n\t} else {\n\t\tval &= ~0x3; val |= clksrc;\n\t}\n\tsdr_write32(MSDC_CLKSRC_REG, val);\n\n\thost->hclk = hclks[clksrc];\n\thost->hw->clk_src = clksrc;\n}\n#endif /* end of --- */\n\nstatic void msdc_set_mclk(struct msdc_host *host, int ddr, unsigned int hz)\n{\n\t//struct msdc_hw *hw = host->hw;\n\tvoid __iomem *base = host->base;\n\tu32 mode;\n\tu32 flags;\n\tu32 div;\n\tu32 sclk;\n\tu32 hclk = host->hclk;\n\t//u8  clksrc = hw->clk_src;\n\n\tif (!hz) { // set mmc system clock to 0 ?\n\t\t//ERR_MSG(\"set mclk to 0!!!\");\n\t\tmsdc_reset_hw(host);\n\t\treturn;\n\t}\n\n\tmsdc_irq_save(flags);\n\n\tif (ddr) {\n\t\tmode = 0x2; /* ddr mode and use divisor */\n\t\tif (hz >= (hclk >> 2)) {\n\t\t\tdiv  = 1;         /* mean div = 1/4 */\n\t\t\tsclk = hclk >> 2; /* sclk = clk / 4 */\n\t\t} else {\n\t\t\tdiv  = (hclk + ((hz << 2) - 1)) / (hz << 2);\n\t\t\tsclk = (hclk >> 2) / div;\n\t\t}\n\t} else if (hz >= hclk) { /* bug fix */\n\t\tmode = 0x1; /* no divisor and divisor is ignored */\n\t\tdiv  = 0;\n\t\tsclk = hclk;\n\t} else {\n\t\tmode = 0x0; /* use divisor */\n\t\tif (hz >= (hclk >> 1)) {\n\t\t\tdiv  = 0;         /* mean div = 1/2 */\n\t\t\tsclk = hclk >> 1; /* sclk = clk / 2 */\n\t\t} else {\n\t\t\tdiv  = (hclk + ((hz << 2) - 1)) / (hz << 2);\n\t\t\tsclk = (hclk >> 2) / div;\n\t\t}\n\t}\n\n\t/* set clock mode and divisor */\n\tsdr_set_field(MSDC_CFG, MSDC_CFG_CKMOD, mode);\n\tsdr_set_field(MSDC_CFG, MSDC_CFG_CKDIV, div);\n\n\t/* wait clock stable */\n\twhile (!(sdr_read32(MSDC_CFG) & MSDC_CFG_CKSTB))\n\t\tcpu_relax();\n\n\thost->sclk = sclk;\n\thost->mclk = hz;\n\tmsdc_set_timeout(host, host->timeout_ns, host->timeout_clks); // need?\n\n\tINIT_MSG(\"================\");\n\tINIT_MSG(\"!!! Set<%dKHz> Source<%dKHz> -> sclk<%dKHz>\", hz / 1000, hclk / 1000, sclk / 1000);\n\tINIT_MSG(\"================\");\n\n\tmsdc_irq_restore(flags);\n}\n\n/* Fix me. when need to abort */\nstatic void msdc_abort_data(struct msdc_host *host)\n{\n\tvoid __iomem *base = host->base;\n\tstruct mmc_command *stop = host->mrq->stop;\n\n\tERR_MSG(\"Need to Abort.\");\n\n\tmsdc_reset_hw(host);\n\tmsdc_clr_fifo();\n\tmsdc_clr_int();\n\n\t// need to check FIFO count 0 ?\n\n\tif (stop) {  /* try to stop, but may not success */\n\t\tERR_MSG(\"stop when abort CMD<%d>\", stop->opcode);\n\t\t(void)msdc_do_command(host, stop, 0, CMD_TIMEOUT);\n\t}\n\n\t//if (host->mclk >= 25000000) {\n\t//      msdc_set_mclk(host, 0, host->mclk >> 1);\n\t//}\n}\n\n#if 0 /* --- by chhung */\nstatic void msdc_pin_config(struct msdc_host *host, int mode)\n{\n\tstruct msdc_hw *hw = host->hw;\n\tvoid __iomem *base = host->base;\n\tint pull = (mode == MSDC_PIN_PULL_UP) ? GPIO_PULL_UP : GPIO_PULL_DOWN;\n\n\t/* Config WP pin */\n\tif (hw->flags & MSDC_WP_PIN_EN) {\n\t\tif (hw->config_gpio_pin) /* NULL */\n\t\t\thw->config_gpio_pin(MSDC_WP_PIN, pull);\n\t}\n\n\tswitch (mode) {\n\tcase MSDC_PIN_PULL_UP:\n\t\t//sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKPU, 1); /* Check & FIXME */\n\t\t//sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKPD, 0); /* Check & FIXME */\n\t\tsdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDPU, 1);\n\t\tsdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDPD, 0);\n\t\tsdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATPU, 1);\n\t\tsdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATPD, 0);\n\t\tbreak;\n\tcase MSDC_PIN_PULL_DOWN:\n\t\t//sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKPU, 0); /* Check & FIXME */\n\t\t//sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKPD, 1); /* Check & FIXME */\n\t\tsdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDPU, 0);\n\t\tsdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDPD, 1);\n\t\tsdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATPU, 0);\n\t\tsdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATPD, 1);\n\t\tbreak;\n\tcase MSDC_PIN_PULL_NONE:\n\tdefault:\n\t\t//sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKPU, 0); /* Check & FIXME */\n\t\t//sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKPD, 0); /* Check & FIXME */\n\t\tsdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDPU, 0);\n\t\tsdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDPD, 0);\n\t\tsdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATPU, 0);\n\t\tsdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATPD, 0);\n\t\tbreak;\n\t}\n\n\tN_MSG(CFG, \"Pins mode(%d), down(%d), up(%d)\",\n\t      mode, MSDC_PIN_PULL_DOWN, MSDC_PIN_PULL_UP);\n}\n\nvoid msdc_pin_reset(struct msdc_host *host, int mode)\n{\n\tstruct msdc_hw *hw = (struct msdc_hw *)host->hw;\n\tvoid __iomem *base = host->base;\n\tint pull = (mode == MSDC_PIN_PULL_UP) ? GPIO_PULL_UP : GPIO_PULL_DOWN;\n\n\t/* Config reset pin */\n\tif (hw->flags & MSDC_RST_PIN_EN) {\n\t\tif (hw->config_gpio_pin) /* NULL */\n\t\t\thw->config_gpio_pin(MSDC_RST_PIN, pull);\n\n\t\tif (mode == MSDC_PIN_PULL_UP)\n\t\t\tsdr_clr_bits(EMMC_IOCON, EMMC_IOCON_BOOTRST);\n\t\telse\n\t\t\tsdr_set_bits(EMMC_IOCON, EMMC_IOCON_BOOTRST);\n\t}\n}\n\nstatic void msdc_core_power(struct msdc_host *host, int on)\n{\n\tN_MSG(CFG, \"Turn %s %s power (copower: %d -> %d)\",\n\t\ton ? \"on\" : \"off\", \"core\", host->core_power, on);\n\n\tif (on && host->core_power == 0) {\n\t\tmsdc_vcore_on(host);\n\t\thost->core_power = 1;\n\t\tmsleep(1);\n\t} else if (!on && host->core_power == 1) {\n\t\tmsdc_vcore_off(host);\n\t\thost->core_power = 0;\n\t\tmsleep(1);\n\t}\n}\n\nstatic void msdc_host_power(struct msdc_host *host, int on)\n{\n\tN_MSG(CFG, \"Turn %s %s power \", on ? \"on\" : \"off\", \"host\");\n\n\tif (on) {\n\t\t//msdc_core_power(host, 1); // need do card detection.\n\t\tmsdc_pin_reset(host, MSDC_PIN_PULL_UP);\n\t} else {\n\t\tmsdc_pin_reset(host, MSDC_PIN_PULL_DOWN);\n\t\t//msdc_core_power(host, 0);\n\t}\n}\n\nstatic void msdc_card_power(struct msdc_host *host, int on)\n{\n\tN_MSG(CFG, \"Turn %s %s power \", on ? \"on\" : \"off\", \"card\");\n\n\tif (on) {\n\t\tmsdc_pin_config(host, MSDC_PIN_PULL_UP);\n\t\t//msdc_vdd_on(host);  // need todo card detection.\n\t\tmsleep(1);\n\t} else {\n\t\t//msdc_vdd_off(host);\n\t\tmsdc_pin_config(host, MSDC_PIN_PULL_DOWN);\n\t\tmsleep(1);\n\t}\n}\n\nstatic void msdc_set_power_mode(struct msdc_host *host, u8 mode)\n{\n\tN_MSG(CFG, \"Set power mode(%d)\", mode);\n\n\tif (host->power_mode == MMC_POWER_OFF && mode != MMC_POWER_OFF) {\n\t\tmsdc_host_power(host, 1);\n\t\tmsdc_card_power(host, 1);\n\t} else if (host->power_mode != MMC_POWER_OFF && mode == MMC_POWER_OFF) {\n\t\tmsdc_card_power(host, 0);\n\t\tmsdc_host_power(host, 0);\n\t}\n\thost->power_mode = mode;\n}\n#endif /* end of --- */\n\n#ifdef CONFIG_PM\n/*\n   register as callback function of WIFI(combo_sdio_register_pm) .\n   can called by msdc_drv_suspend/resume too.\n*/\nstatic void msdc_pm(pm_message_t state, void *data)\n{\n\tstruct msdc_host *host = (struct msdc_host *)data;\n\tint evt = state.event;\n\n\tif (evt == PM_EVENT_USER_RESUME || evt == PM_EVENT_USER_SUSPEND) {\n\t\tINIT_MSG(\"USR_%s: suspend<%d> power<%d>\",\n\t\t\tevt == PM_EVENT_USER_RESUME ? \"EVENT_USER_RESUME\" : \"EVENT_USER_SUSPEND\",\n\t\t\thost->suspend, host->power_mode);\n\t}\n\n\tif (evt == PM_EVENT_SUSPEND || evt == PM_EVENT_USER_SUSPEND) {\n\t\tif (host->suspend) /* already suspend */  /* default 0*/\n\t\t\treturn;\n\n\t\t/* for memory card. already power off by mmc */\n\t\tif (evt == PM_EVENT_SUSPEND && host->power_mode == MMC_POWER_OFF)\n\t\t\treturn;\n\n\t\thost->suspend = 1;\n\t\thost->pm_state = state;  /* default PMSG_RESUME */\n\n\t} else if (evt == PM_EVENT_RESUME || evt == PM_EVENT_USER_RESUME) {\n\t\tif (!host->suspend) {\n\t\t\t//ERR_MSG(\"warning: already resume\");\n\t\t\treturn;\n\t\t}\n\n\t\t/* No PM resume when USR suspend */\n\t\tif (evt == PM_EVENT_RESUME && host->pm_state.event == PM_EVENT_USER_SUSPEND) {\n\t\t\tERR_MSG(\"PM Resume when in USR Suspend\");\t\t/* won't happen. */\n\t\t\treturn;\n\t\t}\n\n\t\thost->suspend = 0;\n\t\thost->pm_state = state;\n\n\t}\n}\n#endif\n\n/*--------------------------------------------------------------------------*/\n/* mmc_host_ops members                                                      */\n/*--------------------------------------------------------------------------*/\nstatic unsigned int msdc_command_start(struct msdc_host   *host,\n\t\t\t\t       struct mmc_command *cmd,\n\t\t\t\t       int                 tune,   /* not used */\n\t\t\t\t       unsigned long       timeout)\n{\n\tvoid __iomem *base = host->base;\n\tu32 opcode = cmd->opcode;\n\tu32 rawcmd;\n\tu32 wints = MSDC_INT_CMDRDY  | MSDC_INT_RSPCRCERR  | MSDC_INT_CMDTMO  |\n\t\t    MSDC_INT_ACMDRDY | MSDC_INT_ACMDCRCERR | MSDC_INT_ACMDTMO |\n\t\t    MSDC_INT_ACMD19_DONE;\n\n\tu32 resp;\n\tunsigned long tmo;\n\n\t/* Protocol layer does not provide response type, but our hardware needs\n\t * to know exact type, not just size!\n\t */\n\tif (opcode == MMC_SEND_OP_COND || opcode == SD_APP_OP_COND) {\n\t\tresp = RESP_R3;\n\t} else if (opcode == MMC_SET_RELATIVE_ADDR) {\n\t\tresp = (mmc_cmd_type(cmd) == MMC_CMD_BCR) ? RESP_R6 : RESP_R1;\n\t} else if (opcode == MMC_FAST_IO) {\n\t\tresp = RESP_R4;\n\t} else if (opcode == MMC_GO_IRQ_STATE) {\n\t\tresp = RESP_R5;\n\t} else if (opcode == MMC_SELECT_CARD) {\n\t\tresp = (cmd->arg != 0) ? RESP_R1B : RESP_NONE;\n\t} else if (opcode == SD_IO_RW_DIRECT || opcode == SD_IO_RW_EXTENDED) {\n\t\tresp = RESP_R1; /* SDIO workaround. */\n\t} else if (opcode == SD_SEND_IF_COND && (mmc_cmd_type(cmd) == MMC_CMD_BCR)) {\n\t\tresp = RESP_R1;\n\t} else {\n\t\tswitch (mmc_resp_type(cmd)) {\n\t\tcase MMC_RSP_R1:\n\t\t\tresp = RESP_R1;\n\t\t\tbreak;\n\t\tcase MMC_RSP_R1B:\n\t\t\tresp = RESP_R1B;\n\t\t\tbreak;\n\t\tcase MMC_RSP_R2:\n\t\t\tresp = RESP_R2;\n\t\t\tbreak;\n\t\tcase MMC_RSP_R3:\n\t\t\tresp = RESP_R3;\n\t\t\tbreak;\n\t\tcase MMC_RSP_NONE:\n\t\tdefault:\n\t\t\tresp = RESP_NONE;\n\t\t\tbreak;\n\t\t}\n\t}\n\n\tcmd->error = 0;\n\t/* rawcmd :\n\t * vol_swt << 30 | auto_cmd << 28 | blklen << 16 | go_irq << 15 |\n\t * stop << 14 | rw << 13 | dtype << 11 | rsptyp << 7 | brk << 6 | opcode\n\t */\n\trawcmd = opcode | msdc_rsp[resp] << 7 | host->blksz << 16;\n\n\tif (opcode == MMC_READ_MULTIPLE_BLOCK) {\n\t\trawcmd |= (2 << 11);\n\t} else if (opcode == MMC_READ_SINGLE_BLOCK) {\n\t\trawcmd |= (1 << 11);\n\t} else if (opcode == MMC_WRITE_MULTIPLE_BLOCK) {\n\t\trawcmd |= ((2 << 11) | (1 << 13));\n\t} else if (opcode == MMC_WRITE_BLOCK) {\n\t\trawcmd |= ((1 << 11) | (1 << 13));\n\t} else if (opcode == SD_IO_RW_EXTENDED) {\n\t\tif (cmd->data->flags & MMC_DATA_WRITE)\n\t\t\trawcmd |= (1 << 13);\n\t\tif (cmd->data->blocks > 1)\n\t\t\trawcmd |= (2 << 11);\n\t\telse\n\t\t\trawcmd |= (1 << 11);\n\t} else if (opcode == SD_IO_RW_DIRECT && cmd->flags == (unsigned int)-1) {\n\t\trawcmd |= (1 << 14);\n\t} else if ((opcode == SD_APP_SEND_SCR) ||\n\t\t(opcode == SD_APP_SEND_NUM_WR_BLKS) ||\n\t\t(opcode == SD_SWITCH && (mmc_cmd_type(cmd) == MMC_CMD_ADTC)) ||\n\t\t(opcode == SD_APP_SD_STATUS && (mmc_cmd_type(cmd) == MMC_CMD_ADTC)) ||\n\t\t(opcode == MMC_SEND_EXT_CSD && (mmc_cmd_type(cmd) == MMC_CMD_ADTC))) {\n\t\trawcmd |= (1 << 11);\n\t} else if (opcode == MMC_STOP_TRANSMISSION) {\n\t\trawcmd |= (1 << 14);\n\t\trawcmd &= ~(0x0FFF << 16);\n\t}\n\n\tN_MSG(CMD, \"CMD<%d><0x%.8x> Arg<0x%.8x>\", opcode, rawcmd, cmd->arg);\n\n\ttmo = jiffies + timeout;\n\n\tif (opcode == MMC_SEND_STATUS) {\n\t\tfor (;;) {\n\t\t\tif (!sdc_is_cmd_busy())\n\t\t\t\tbreak;\n\n\t\t\tif (time_after(jiffies, tmo)) {\n\t\t\t\tERR_MSG(\"XXX cmd_busy timeout: before CMD<%d>\", opcode);\n\t\t\t\tcmd->error = -ETIMEDOUT;\n\t\t\t\tmsdc_reset_hw(host);\n\t\t\t\tgoto end;\n\t\t\t}\n\t\t}\n\t} else {\n\t\tfor (;;) {\n\t\t\tif (!sdc_is_busy())\n\t\t\t\tbreak;\n\t\t\tif (time_after(jiffies, tmo)) {\n\t\t\t\tERR_MSG(\"XXX sdc_busy timeout: before CMD<%d>\", opcode);\n\t\t\t\tcmd->error = -ETIMEDOUT;\n\t\t\t\tmsdc_reset_hw(host);\n\t\t\t\tgoto end;\n\t\t\t}\n\t\t}\n\t}\n\n\t//BUG_ON(in_interrupt());\n\thost->cmd     = cmd;\n\thost->cmd_rsp = resp;\n\n\tinit_completion(&host->cmd_done);\n\n\tsdr_set_bits(MSDC_INTEN, wints);\n\tsdc_send_cmd(rawcmd, cmd->arg);\n\nend:\n\treturn cmd->error;\n}\n\nstatic unsigned int msdc_command_resp(struct msdc_host   *host,\n\t\t\t\t      struct mmc_command *cmd,\n\t\t\t\t      int                 tune,\n\t\t\t\t      unsigned long       timeout)\n\t__must_hold(&host->lock)\n{\n\tvoid __iomem *base = host->base;\n\tu32 opcode = cmd->opcode;\n\t//u32 rawcmd;\n\tu32 resp;\n\tu32 wints = MSDC_INT_CMDRDY  | MSDC_INT_RSPCRCERR  | MSDC_INT_CMDTMO  |\n\t\t    MSDC_INT_ACMDRDY | MSDC_INT_ACMDCRCERR | MSDC_INT_ACMDTMO |\n\t\t    MSDC_INT_ACMD19_DONE;\n\n\tresp = host->cmd_rsp;\n\n\tBUG_ON(in_interrupt());\n\t//init_completion(&host->cmd_done);\n\t//sdr_set_bits(MSDC_INTEN, wints);\n\n\tspin_unlock(&host->lock);\n\tif (!wait_for_completion_timeout(&host->cmd_done, 10 * timeout)) {\n\t\tERR_MSG(\"XXX CMD<%d> wait_for_completion timeout ARG<0x%.8x>\", opcode, cmd->arg);\n\t\tcmd->error = -ETIMEDOUT;\n\t\tmsdc_reset_hw(host);\n\t}\n\tspin_lock(&host->lock);\n\n\tsdr_clr_bits(MSDC_INTEN, wints);\n\thost->cmd = NULL;\n\n//end:\n#ifdef MT6575_SD_DEBUG\n\tswitch (resp) {\n\tcase RESP_NONE:\n\t\tN_MSG(RSP, \"CMD_RSP(%d): %d RSP(%d)\", opcode, cmd->error, resp);\n\t\tbreak;\n\tcase RESP_R2:\n\t\tN_MSG(RSP, \"CMD_RSP(%d): %d RSP(%d)= %.8x %.8x %.8x %.8x\",\n\t\t\topcode, cmd->error, resp, cmd->resp[0], cmd->resp[1],\n\t\t\tcmd->resp[2], cmd->resp[3]);\n\t\tbreak;\n\tdefault: /* Response types 1, 3, 4, 5, 6, 7(1b) */\n\t\tN_MSG(RSP, \"CMD_RSP(%d): %d RSP(%d)= 0x%.8x\",\n\t\t\topcode, cmd->error, resp, cmd->resp[0]);\n\t\tif (cmd->error == 0) {\n\t\t\tswitch (resp) {\n\t\t\tcase RESP_R1:\n\t\t\tcase RESP_R1B:\n\t\t\t\tmsdc_dump_card_status(host, cmd->resp[0]);\n\t\t\t\tbreak;\n\t\t\tcase RESP_R3:\n\t\t\t\tmsdc_dump_ocr_reg(host, cmd->resp[0]);\n\t\t\t\tbreak;\n\t\t\tcase RESP_R5:\n\t\t\t\tmsdc_dump_io_resp(host, cmd->resp[0]);\n\t\t\t\tbreak;\n\t\t\tcase RESP_R6:\n\t\t\t\tmsdc_dump_rca_resp(host, cmd->resp[0]);\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t\tbreak;\n\t}\n#endif\n\n\t/* do we need to save card's RCA when SD_SEND_RELATIVE_ADDR */\n\n\tif (!tune)\n\t\treturn cmd->error;\n\n\t/* memory card CRC */\n\tif (host->hw->flags & MSDC_REMOVABLE && cmd->error == -EIO) {\n\t\tif (sdr_read32(SDC_CMD) & 0x1800) { /* check if has data phase */\n\t\t\tmsdc_abort_data(host);\n\t\t} else {\n\t\t\t/* do basic: reset*/\n\t\t\tmsdc_reset_hw(host);\n\t\t\tmsdc_clr_fifo();\n\t\t\tmsdc_clr_int();\n\t\t}\n\t\tcmd->error = msdc_tune_cmdrsp(host, cmd);\n\t}\n\n\t//  check DAT0\n\t/* if (resp == RESP_R1B) {\n\t   while ((sdr_read32(MSDC_PS) & 0x10000) != 0x10000);\n\t   } */\n\t/* CMD12 Error Handle */\n\n\treturn cmd->error;\n}\n\nstatic unsigned int msdc_do_command(struct msdc_host   *host,\n\t\t\t\t    struct mmc_command *cmd,\n\t\t\t\t    int                 tune,\n\t\t\t\t    unsigned long       timeout)\n{\n\tif (msdc_command_start(host, cmd, tune, timeout))\n\t\tgoto end;\n\n\tif (msdc_command_resp(host, cmd, tune, timeout))\n\t\tgoto end;\n\nend:\n\n\tN_MSG(CMD, \"        return<%d> resp<0x%.8x>\", cmd->error, cmd->resp[0]);\n\treturn cmd->error;\n}\n\n#if 0 /* --- by chhung */\n// DMA resume / start / stop\nstatic void msdc_dma_resume(struct msdc_host *host)\n{\n\tvoid __iomem *base = host->base;\n\n\tsdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_RESUME, 1);\n\n\tN_MSG(DMA, \"DMA resume\");\n}\n#endif /* end of --- */\n\nstatic void msdc_dma_start(struct msdc_host *host)\n{\n\tvoid __iomem *base = host->base;\n\tu32 wints = MSDC_INTEN_XFER_COMPL | MSDC_INTEN_DATTMO | MSDC_INTEN_DATCRCERR;\n\n\tsdr_set_bits(MSDC_INTEN, wints);\n\t//dsb(); /* --- by chhung */\n\tsdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_START, 1);\n\n\tN_MSG(DMA, \"DMA start\");\n}\n\nstatic void msdc_dma_stop(struct msdc_host *host)\n{\n\tvoid __iomem *base = host->base;\n\t//u32 retries=500;\n\tu32 wints = MSDC_INTEN_XFER_COMPL | MSDC_INTEN_DATTMO | MSDC_INTEN_DATCRCERR;\n\n\tN_MSG(DMA, \"DMA status: 0x%.8x\", sdr_read32(MSDC_DMA_CFG));\n\t//while (sdr_read32(MSDC_DMA_CFG) & MSDC_DMA_CFG_STS);\n\n\tsdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_STOP, 1);\n\twhile (sdr_read32(MSDC_DMA_CFG) & MSDC_DMA_CFG_STS)\n\t\t;\n\n\t//dsb(); /* --- by chhung */\n\tsdr_clr_bits(MSDC_INTEN, wints); /* Not just xfer_comp */\n\n\tN_MSG(DMA, \"DMA stop\");\n}\n\n/* calc checksum */\nstatic u8 msdc_dma_calcs(u8 *buf, u32 len)\n{\n\tu32 i, sum = 0;\n\n\tfor (i = 0; i < len; i++)\n\t\tsum += buf[i];\n\treturn 0xFF - (u8)sum;\n}\n\n/* gpd bd setup + dma registers */\nstatic void msdc_dma_config(struct msdc_host *host, struct msdc_dma *dma)\n{\n\tvoid __iomem *base = host->base;\n\t//u32 i, j, num, bdlen, arg, xfersz;\n\tu32 j, num;\n\tstruct scatterlist *sg;\n\tstruct gpd *gpd;\n\tstruct bd *bd;\n\n\tswitch (dma->mode) {\n\tcase MSDC_MODE_DMA_BASIC:\n\t\tBUG_ON(host->xfer_size > 65535);\n\t\tBUG_ON(dma->sglen != 1);\n\t\tsdr_write32(MSDC_DMA_SA, PHYSADDR(sg_dma_address(sg)));\n\t\tsdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_LASTBUF, 1);\n//#if defined (CONFIG_RALINK_MT7620)\n\t\tif (ralink_soc == MT762X_SOC_MT7620A)\n\t\t\tsdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_XFERSZ, sg_dma_len(sg));\n//#elif defined (CONFIG_RALINK_MT7621) || defined (CONFIG_RALINK_MT7628)\n\t\telse\n\t\t\tsdr_write32((void __iomem *)(RALINK_MSDC_BASE + 0xa8), sg_dma_len(sg));\n//#endif\n\t\tsdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_BRUSTSZ,\n\t\t\t      MSDC_BRUST_64B);\n\t\tsdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_MODE, 0);\n\t\tbreak;\n\tcase MSDC_MODE_DMA_DESC:\n\n\t\t/* calculate the required number of gpd */\n\t\tnum = (dma->sglen + MAX_BD_PER_GPD - 1) / MAX_BD_PER_GPD;\n\t\tBUG_ON(num != 1);\n\n\t\tgpd = dma->gpd;\n\t\tbd  = dma->bd;\n\n\t\t/* modify gpd*/\n\t\t//gpd->intr = 0;\n\t\tgpd->hwo = 1;  /* hw will clear it */\n\t\tgpd->bdp = 1;\n\t\tgpd->chksum = 0;  /* need to clear first. */\n\t\tgpd->chksum = msdc_dma_calcs((u8 *)gpd, 16);\n\n\t\t/* modify bd*/\n\t\tfor_each_sg(dma->sg, sg, dma->sglen, j) {\n\t\t\tbd[j].blkpad = 0;\n\t\t\tbd[j].dwpad = 0;\n\t\t\tbd[j].ptr = (void *)sg_dma_address(sg);\n\t\t\tbd[j].buflen = sg_dma_len(sg);\n\n\t\t\tif (j == dma->sglen - 1)\n\t\t\t\tbd[j].eol = 1;\t/* the last bd */\n\t\t\telse\n\t\t\t\tbd[j].eol = 0;\n\n\t\t\tbd[j].chksum = 0; /* checksume need to clear first */\n\t\t\tbd[j].chksum = msdc_dma_calcs((u8 *)(&bd[j]), 16);\n\t\t}\n\n\t\tsdr_set_field(MSDC_DMA_CFG, MSDC_DMA_CFG_DECSEN, 1);\n\t\tsdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_BRUSTSZ,\n\t\t\t      MSDC_BRUST_64B);\n\t\tsdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_MODE, 1);\n\n\t\tsdr_write32(MSDC_DMA_SA, PHYSADDR((u32)dma->gpd_addr));\n\t\tbreak;\n\n\tdefault:\n\t\tbreak;\n\t}\n\n\tN_MSG(DMA, \"DMA_CTRL = 0x%x\", sdr_read32(MSDC_DMA_CTRL));\n\tN_MSG(DMA, \"DMA_CFG  = 0x%x\", sdr_read32(MSDC_DMA_CFG));\n\tN_MSG(DMA, \"DMA_SA   = 0x%x\", sdr_read32(MSDC_DMA_SA));\n\n}\n\nstatic void msdc_dma_setup(struct msdc_host *host, struct msdc_dma *dma,\n\t\t\t   struct scatterlist *sg, unsigned int sglen)\n{\n\tBUG_ON(sglen > MAX_BD_NUM); /* not support currently */\n\n\tdma->sg = sg;\n\tdma->sglen = sglen;\n\n\tdma->mode = MSDC_MODE_DMA_DESC;\n\n\tN_MSG(DMA, \"DMA mode<%d> sglen<%d> xfersz<%d>\", dma->mode, dma->sglen,\n\t      host->xfer_size);\n\n\tmsdc_dma_config(host, dma);\n}\n\nstatic int msdc_do_request(struct mmc_host *mmc, struct mmc_request *mrq)\n\t__must_hold(&host->lock)\n{\n\tstruct msdc_host *host = mmc_priv(mmc);\n\tstruct mmc_command *cmd;\n\tstruct mmc_data *data;\n\tvoid __iomem *base = host->base;\n\t//u32 intsts = 0;\n\tint read = 1, send_type = 0;\n\n#define SND_DAT 0\n#define SND_CMD 1\n\n\tBUG_ON(mmc == NULL);\n\tBUG_ON(mrq == NULL);\n\n\thost->error = 0;\n\n\tcmd  = mrq->cmd;\n\tdata = mrq->cmd->data;\n\n#if 0 /* --- by chhung */\n\t//if(host->id ==1){\n\tN_MSG(OPS, \"enable clock!\");\n\tmsdc_ungate_clock(host->id);\n\t//}\n#endif /* end of --- */\n\n\tif (!data) {\n\t\tsend_type = SND_CMD;\n\t\tif (msdc_do_command(host, cmd, 1, CMD_TIMEOUT) != 0)\n\t\t\tgoto done;\n\t} else {\n\t\tBUG_ON(data->blksz > HOST_MAX_BLKSZ);\n\t\tsend_type = SND_DAT;\n\n\t\tdata->error = 0;\n\t\tread = data->flags & MMC_DATA_READ ? 1 : 0;\n\t\thost->data = data;\n\t\thost->xfer_size = data->blocks * data->blksz;\n\t\thost->blksz = data->blksz;\n\n\t\tif (read) {\n\t\t\tif ((host->timeout_ns != data->timeout_ns) ||\n\t\t\t\t(host->timeout_clks != data->timeout_clks)) {\n\t\t\t\tmsdc_set_timeout(host, data->timeout_ns, data->timeout_clks);\n\t\t\t}\n\t\t}\n\n\t\tsdr_write32(SDC_BLK_NUM, data->blocks);\n\t\t//msdc_clr_fifo();  /* no need */\n\n\t\tmsdc_dma_on();  /* enable DMA mode first!! */\n\t\tinit_completion(&host->xfer_done);\n\n\t\t/* start the command first*/\n\t\tif (msdc_command_start(host, cmd, 1, CMD_TIMEOUT) != 0)\n\t\t\tgoto done;\n\n\t\tdata->sg_count = dma_map_sg(mmc_dev(mmc), data->sg,\n\t\t\t\t\t    data->sg_len,\n\t\t\t\t\t    mmc_get_dma_dir(data));\n\t\tmsdc_dma_setup(host, &host->dma, data->sg,\n\t\t\t       data->sg_count);\n\n\t\t/* then wait command done */\n\t\tif (msdc_command_resp(host, cmd, 1, CMD_TIMEOUT) != 0)\n\t\t\tgoto done;\n\n\t\t/* for read, the data coming too fast, then CRC error\n\t\t   start DMA no business with CRC. */\n\t\t//init_completion(&host->xfer_done);\n\t\tmsdc_dma_start(host);\n\n\t\tspin_unlock(&host->lock);\n\t\tif (!wait_for_completion_timeout(&host->xfer_done, DAT_TIMEOUT)) {\n\t\t\tERR_MSG(\"XXX CMD<%d> wait xfer_done<%d> timeout!!\", cmd->opcode, data->blocks * data->blksz);\n\t\t\tERR_MSG(\"    DMA_SA   = 0x%x\", sdr_read32(MSDC_DMA_SA));\n\t\t\tERR_MSG(\"    DMA_CA   = 0x%x\", sdr_read32(MSDC_DMA_CA));\n\t\t\tERR_MSG(\"    DMA_CTRL = 0x%x\", sdr_read32(MSDC_DMA_CTRL));\n\t\t\tERR_MSG(\"    DMA_CFG  = 0x%x\", sdr_read32(MSDC_DMA_CFG));\n\t\t\tdata->error = -ETIMEDOUT;\n\n\t\t\tmsdc_reset_hw(host);\n\t\t\tmsdc_clr_fifo();\n\t\t\tmsdc_clr_int();\n\t\t}\n\t\tspin_lock(&host->lock);\n\t\tmsdc_dma_stop(host);\n\n\t\t/* Last: stop transfer */\n\t\tif (data->stop) {\n\t\t\tif (msdc_do_command(host, data->stop, 0, CMD_TIMEOUT) != 0)\n\t\t\t\tgoto done;\n\t\t}\n\t}\n\ndone:\n\tif (data != NULL) {\n\t\thost->data = NULL;\n\t\tdma_unmap_sg(mmc_dev(mmc), data->sg, data->sg_len,\n\t\t\t     mmc_get_dma_dir(data));\n\t\thost->blksz = 0;\n\n#if 0 // don't stop twice!\n\t\tif (host->hw->flags & MSDC_REMOVABLE && data->error) {\n\t\t\tmsdc_abort_data(host);\n\t\t\t/* reset in IRQ, stop command has issued. -> No need */\n\t\t}\n#endif\n\n\t\tN_MSG(OPS, \"CMD<%d> data<%s %s> blksz<%d> block<%d> error<%d>\", cmd->opcode, (dma ? \"dma\" : \"pio\"),\n\t\t\t(read ? \"read \" : \"write\"), data->blksz, data->blocks, data->error);\n\t}\n\n#if 0 /* --- by chhung */\n#if 1\n\t//if(host->id==1) {\n\tif (send_type == SND_CMD) {\n\t\tif (cmd->opcode == MMC_SEND_STATUS) {\n\t\t\tif ((cmd->resp[0] & CARD_READY_FOR_DATA) || (CARD_CURRENT_STATE(cmd->resp[0]) != 7)) {\n\t\t\t\tN_MSG(OPS, \"disable clock, CMD13 IDLE\");\n\t\t\t\tmsdc_gate_clock(host->id);\n\t\t\t}\n\t\t} else {\n\t\t\tN_MSG(OPS, \"disable clock, CMD<%d>\", cmd->opcode);\n\t\t\tmsdc_gate_clock(host->id);\n\t\t}\n\t} else {\n\t\tif (read) {\n\t\t\tN_MSG(OPS, \"disable clock!!! Read CMD<%d>\", cmd->opcode);\n\t\t\tmsdc_gate_clock(host->id);\n\t\t}\n\t}\n\t//}\n#else\n\tmsdc_gate_clock(host->id);\n#endif\n#endif /* end of --- */\n\n\tif (mrq->cmd->error)\n\t\thost->error = 0x001;\n\tif (mrq->data && mrq->data->error)\n\t\thost->error |= 0x010;\n\tif (mrq->stop && mrq->stop->error)\n\t\thost->error |= 0x100;\n\n\t//if (host->error) ERR_MSG(\"host->error<%d>\", host->error);\n\n\treturn host->error;\n}\n\nstatic int msdc_app_cmd(struct mmc_host *mmc, struct msdc_host *host)\n{\n\tstruct mmc_command cmd;\n\tstruct mmc_request mrq;\n\tu32 err;\n\n\tmemset(&cmd, 0, sizeof(struct mmc_command));\n\tcmd.opcode = MMC_APP_CMD;\n#if 0   /* bug: we meet mmc->card is null when ACMD6 */\n\tcmd.arg = mmc->card->rca << 16;\n#else\n\tcmd.arg = host->app_cmd_arg;\n#endif\n\tcmd.flags = MMC_RSP_SPI_R1 | MMC_RSP_R1 | MMC_CMD_AC;\n\n\tmemset(&mrq, 0, sizeof(struct mmc_request));\n\tmrq.cmd = &cmd; cmd.mrq = &mrq;\n\tcmd.data = NULL;\n\n\terr = msdc_do_command(host, &cmd, 0, CMD_TIMEOUT);\n\treturn err;\n}\n\nstatic int msdc_tune_cmdrsp(struct msdc_host *host, struct mmc_command *cmd)\n{\n\tint result = -1;\n\tvoid __iomem *base = host->base;\n\tu32 rsmpl, cur_rsmpl, orig_rsmpl;\n\tu32 rrdly, cur_rrdly = 0xffffffff, orig_rrdly;\n\tu32 skip = 1;\n\n\t/* ==== don't support 3.0 now ====\n\t   1: R_SMPL[1]\n\t   2: PAD_CMD_RESP_RXDLY[26:22]\n\t   ==========================*/\n\n\t// save the previous tune result\n\tsdr_get_field(MSDC_IOCON,    MSDC_IOCON_RSPL,        &orig_rsmpl);\n\tsdr_get_field(MSDC_PAD_TUNE, MSDC_PAD_TUNE_CMDRRDLY, &orig_rrdly);\n\n\trrdly = 0;\n\tdo {\n\t\tfor (rsmpl = 0; rsmpl < 2; rsmpl++) {\n\t\t\t/* Lv1: R_SMPL[1] */\n\t\t\tcur_rsmpl = (orig_rsmpl + rsmpl) % 2;\n\t\t\tif (skip == 1) {\n\t\t\t\tskip = 0;\n\t\t\t\tcontinue;\n\t\t\t}\n\t\t\tsdr_set_field(MSDC_IOCON, MSDC_IOCON_RSPL, cur_rsmpl);\n\n\t\t\tif (host->app_cmd) {\n\t\t\t\tresult = msdc_app_cmd(host->mmc, host);\n\t\t\t\tif (result) {\n\t\t\t\t\tERR_MSG(\"TUNE_CMD app_cmd<%d> failed: RESP_RXDLY<%d>,R_SMPL<%d>\",\n\t\t\t\t\t\thost->mrq->cmd->opcode, cur_rrdly, cur_rsmpl);\n\t\t\t\t\tcontinue;\n\t\t\t\t}\n\t\t\t}\n\t\t\tresult = msdc_do_command(host, cmd, 0, CMD_TIMEOUT); // not tune.\n\t\t\tERR_MSG(\"TUNE_CMD<%d> %s PAD_CMD_RESP_RXDLY[26:22]<%d> R_SMPL[1]<%d>\", cmd->opcode,\n\t\t\t\t(result == 0) ? \"PASS\" : \"FAIL\", cur_rrdly, cur_rsmpl);\n\n\t\t\tif (result == 0)\n\t\t\t\treturn 0;\n\t\t\tif (result != -EIO) {\n\t\t\t\tERR_MSG(\"TUNE_CMD<%d> Error<%d> not -EIO\", cmd->opcode, result);\n\t\t\t\treturn result;\n\t\t\t}\n\n\t\t\t/* should be EIO */\n\t\t\tif (sdr_read32(SDC_CMD) & 0x1800) { /* check if has data phase */\n\t\t\t\tmsdc_abort_data(host);\n\t\t\t}\n\t\t}\n\n\t\t/* Lv2: PAD_CMD_RESP_RXDLY[26:22] */\n\t\tcur_rrdly = (orig_rrdly + rrdly + 1) % 32;\n\t\tsdr_set_field(MSDC_PAD_TUNE, MSDC_PAD_TUNE_CMDRRDLY, cur_rrdly);\n\t} while (++rrdly < 32);\n\n\treturn result;\n}\n\n/* Support SD2.0 Only */\nstatic int msdc_tune_bread(struct mmc_host *mmc, struct mmc_request *mrq)\n{\n\tstruct msdc_host *host = mmc_priv(mmc);\n\tvoid __iomem *base = host->base;\n\tu32 ddr = 0;\n\tu32 dcrc = 0;\n\tu32 rxdly, cur_rxdly0, cur_rxdly1;\n\tu32 dsmpl, cur_dsmpl,  orig_dsmpl;\n\tu32 cur_dat0,  cur_dat1,  cur_dat2,  cur_dat3;\n\tu32 cur_dat4,  cur_dat5,  cur_dat6,  cur_dat7;\n\tu32 orig_dat0, orig_dat1, orig_dat2, orig_dat3;\n\tu32 orig_dat4, orig_dat5, orig_dat6, orig_dat7;\n\tint result = -1;\n\tu32 skip = 1;\n\n\tsdr_get_field(MSDC_IOCON, MSDC_IOCON_DSPL, &orig_dsmpl);\n\n\t/* Tune Method 2. */\n\tsdr_set_field(MSDC_IOCON, MSDC_IOCON_DDLSEL, 1);\n\n\trxdly = 0;\n\tdo {\n\t\tfor (dsmpl = 0; dsmpl < 2; dsmpl++) {\n\t\t\tcur_dsmpl = (orig_dsmpl + dsmpl) % 2;\n\t\t\tif (skip == 1) {\n\t\t\t\tskip = 0;\n\t\t\t\tcontinue;\n\t\t\t}\n\t\t\tsdr_set_field(MSDC_IOCON, MSDC_IOCON_DSPL, cur_dsmpl);\n\n\t\t\tif (host->app_cmd) {\n\t\t\t\tresult = msdc_app_cmd(host->mmc, host);\n\t\t\t\tif (result) {\n\t\t\t\t\tERR_MSG(\"TUNE_BREAD app_cmd<%d> failed\", host->mrq->cmd->opcode);\n\t\t\t\t\tcontinue;\n\t\t\t\t}\n\t\t\t}\n\t\t\tresult = msdc_do_request(mmc, mrq);\n\n\t\t\tsdr_get_field(SDC_DCRC_STS,\n\t\t\t\t      SDC_DCRC_STS_POS | SDC_DCRC_STS_NEG,\n\t\t\t\t      &dcrc); /* RO */\n\t\t\tif (!ddr)\n\t\t\t\tdcrc &= ~SDC_DCRC_STS_NEG;\n\t\t\tERR_MSG(\"TUNE_BREAD<%s> dcrc<0x%x> DATRDDLY0/1<0x%x><0x%x> dsmpl<0x%x>\",\n\t\t\t\t(result == 0 && dcrc == 0) ? \"PASS\" : \"FAIL\", dcrc,\n\t\t\t\tsdr_read32(MSDC_DAT_RDDLY0), sdr_read32(MSDC_DAT_RDDLY1), cur_dsmpl);\n\n\t\t\t/* Fix me: result is 0, but dcrc is still exist */\n\t\t\tif (result == 0 && dcrc == 0) {\n\t\t\t\tgoto done;\n\t\t\t} else {\n\t\t\t\t/* there is a case: command timeout, and data phase not processed */\n\t\t\t\tif (mrq->data->error != 0 &&\n\t\t\t\t    mrq->data->error != -EIO) {\n\t\t\t\t\tERR_MSG(\"TUNE_READ: result<0x%x> cmd_error<%d> data_error<%d>\",\n\t\t\t\t\t\tresult, mrq->cmd->error, mrq->data->error);\n\t\t\t\t\tgoto done;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n\t\tcur_rxdly0 = sdr_read32(MSDC_DAT_RDDLY0);\n\t\tcur_rxdly1 = sdr_read32(MSDC_DAT_RDDLY1);\n\n\t\t/* E1 ECO. YD: Reverse */\n\t\tif (sdr_read32(MSDC_ECO_VER) >= 4) {\n\t\t\torig_dat0 = (cur_rxdly0 >> 24) & 0x1F;\n\t\t\torig_dat1 = (cur_rxdly0 >> 16) & 0x1F;\n\t\t\torig_dat2 = (cur_rxdly0 >>  8) & 0x1F;\n\t\t\torig_dat3 = (cur_rxdly0 >>  0) & 0x1F;\n\t\t\torig_dat4 = (cur_rxdly1 >> 24) & 0x1F;\n\t\t\torig_dat5 = (cur_rxdly1 >> 16) & 0x1F;\n\t\t\torig_dat6 = (cur_rxdly1 >>  8) & 0x1F;\n\t\t\torig_dat7 = (cur_rxdly1 >>  0) & 0x1F;\n\t\t} else {\n\t\t\torig_dat0 = (cur_rxdly0 >>  0) & 0x1F;\n\t\t\torig_dat1 = (cur_rxdly0 >>  8) & 0x1F;\n\t\t\torig_dat2 = (cur_rxdly0 >> 16) & 0x1F;\n\t\t\torig_dat3 = (cur_rxdly0 >> 24) & 0x1F;\n\t\t\torig_dat4 = (cur_rxdly1 >>  0) & 0x1F;\n\t\t\torig_dat5 = (cur_rxdly1 >>  8) & 0x1F;\n\t\t\torig_dat6 = (cur_rxdly1 >> 16) & 0x1F;\n\t\t\torig_dat7 = (cur_rxdly1 >> 24) & 0x1F;\n\t\t}\n\n\t\tif (ddr) {\n\t\t\tcur_dat0 = (dcrc & (1 << 0) || dcrc & (1 << 8))  ? ((orig_dat0 + 1) % 32) : orig_dat0;\n\t\t\tcur_dat1 = (dcrc & (1 << 1) || dcrc & (1 << 9))  ? ((orig_dat1 + 1) % 32) : orig_dat1;\n\t\t\tcur_dat2 = (dcrc & (1 << 2) || dcrc & (1 << 10)) ? ((orig_dat2 + 1) % 32) : orig_dat2;\n\t\t\tcur_dat3 = (dcrc & (1 << 3) || dcrc & (1 << 11)) ? ((orig_dat3 + 1) % 32) : orig_dat3;\n\t\t} else {\n\t\t\tcur_dat0 = (dcrc & (1 << 0)) ? ((orig_dat0 + 1) % 32) : orig_dat0;\n\t\t\tcur_dat1 = (dcrc & (1 << 1)) ? ((orig_dat1 + 1) % 32) : orig_dat1;\n\t\t\tcur_dat2 = (dcrc & (1 << 2)) ? ((orig_dat2 + 1) % 32) : orig_dat2;\n\t\t\tcur_dat3 = (dcrc & (1 << 3)) ? ((orig_dat3 + 1) % 32) : orig_dat3;\n\t\t}\n\t\tcur_dat4 = (dcrc & (1 << 4)) ? ((orig_dat4 + 1) % 32) : orig_dat4;\n\t\tcur_dat5 = (dcrc & (1 << 5)) ? ((orig_dat5 + 1) % 32) : orig_dat5;\n\t\tcur_dat6 = (dcrc & (1 << 6)) ? ((orig_dat6 + 1) % 32) : orig_dat6;\n\t\tcur_dat7 = (dcrc & (1 << 7)) ? ((orig_dat7 + 1) % 32) : orig_dat7;\n\n\t\tcur_rxdly0 = (cur_dat0 << 24) | (cur_dat1 << 16) | (cur_dat2 << 8) | (cur_dat3 << 0);\n\t\tcur_rxdly1 = (cur_dat4 << 24) | (cur_dat5 << 16) | (cur_dat6 << 8) | (cur_dat7 << 0);\n\n\t\tsdr_write32(MSDC_DAT_RDDLY0, cur_rxdly0);\n\t\tsdr_write32(MSDC_DAT_RDDLY1, cur_rxdly1);\n\n\t} while (++rxdly < 32);\n\ndone:\n\treturn result;\n}\n\nstatic int msdc_tune_bwrite(struct mmc_host *mmc, struct mmc_request *mrq)\n{\n\tstruct msdc_host *host = mmc_priv(mmc);\n\tvoid __iomem *base = host->base;\n\n\tu32 wrrdly, cur_wrrdly = 0xffffffff, orig_wrrdly;\n\tu32 dsmpl,  cur_dsmpl,  orig_dsmpl;\n\tu32 rxdly,  cur_rxdly0;\n\tu32 orig_dat0, orig_dat1, orig_dat2, orig_dat3;\n\tu32 cur_dat0,  cur_dat1,  cur_dat2,  cur_dat3;\n\tint result = -1;\n\tu32 skip = 1;\n\n\t// MSDC_IOCON_DDR50CKD need to check. [Fix me]\n\n\tsdr_get_field(MSDC_PAD_TUNE, MSDC_PAD_TUNE_DATWRDLY, &orig_wrrdly);\n\tsdr_get_field(MSDC_IOCON,    MSDC_IOCON_DSPL,        &orig_dsmpl);\n\n\t/* Tune Method 2. just DAT0 */\n\tsdr_set_field(MSDC_IOCON, MSDC_IOCON_DDLSEL, 1);\n\tcur_rxdly0 = sdr_read32(MSDC_DAT_RDDLY0);\n\n\t/* E1 ECO. YD: Reverse */\n\tif (sdr_read32(MSDC_ECO_VER) >= 4) {\n\t\torig_dat0 = (cur_rxdly0 >> 24) & 0x1F;\n\t\torig_dat1 = (cur_rxdly0 >> 16) & 0x1F;\n\t\torig_dat2 = (cur_rxdly0 >>  8) & 0x1F;\n\t\torig_dat3 = (cur_rxdly0 >>  0) & 0x1F;\n\t} else {\n\t\torig_dat0 = (cur_rxdly0 >>  0) & 0x1F;\n\t\torig_dat1 = (cur_rxdly0 >>  8) & 0x1F;\n\t\torig_dat2 = (cur_rxdly0 >> 16) & 0x1F;\n\t\torig_dat3 = (cur_rxdly0 >> 24) & 0x1F;\n\t}\n\n\trxdly = 0;\n\tdo {\n\t\twrrdly = 0;\n\t\tdo {\n\t\t\tfor (dsmpl = 0; dsmpl < 2; dsmpl++) {\n\t\t\t\tcur_dsmpl = (orig_dsmpl + dsmpl) % 2;\n\t\t\t\tif (skip == 1) {\n\t\t\t\t\tskip = 0;\n\t\t\t\t\tcontinue;\n\t\t\t\t}\n\t\t\t\tsdr_set_field(MSDC_IOCON, MSDC_IOCON_DSPL, cur_dsmpl);\n\n\t\t\t\tif (host->app_cmd) {\n\t\t\t\t\tresult = msdc_app_cmd(host->mmc, host);\n\t\t\t\t\tif (result) {\n\t\t\t\t\t\tERR_MSG(\"TUNE_BWRITE app_cmd<%d> failed\", host->mrq->cmd->opcode);\n\t\t\t\t\t\tcontinue;\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\tresult = msdc_do_request(mmc, mrq);\n\n\t\t\t\tERR_MSG(\"TUNE_BWRITE<%s> DSPL<%d> DATWRDLY<%d> MSDC_DAT_RDDLY0<0x%x>\",\n\t\t\t\t\tresult == 0 ? \"PASS\" : \"FAIL\",\n\t\t\t\t\tcur_dsmpl, cur_wrrdly, cur_rxdly0);\n\n\t\t\t\tif (result == 0) {\n\t\t\t\t\tgoto done;\n\t\t\t\t} else {\n\t\t\t\t\t/* there is a case: command timeout, and data phase not processed */\n\t\t\t\t\tif (mrq->data->error != -EIO) {\n\t\t\t\t\t\tERR_MSG(\"TUNE_READ: result<0x%x> cmd_error<%d> data_error<%d>\",\n\t\t\t\t\t\t\tresult, mrq->cmd->error, mrq->data->error);\n\t\t\t\t\t\tgoto done;\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t\tcur_wrrdly = (orig_wrrdly + wrrdly + 1) % 32;\n\t\t\tsdr_set_field(MSDC_PAD_TUNE, MSDC_PAD_TUNE_DATWRDLY, cur_wrrdly);\n\t\t} while (++wrrdly < 32);\n\n\t\tcur_dat0 = (orig_dat0 + rxdly) % 32; /* only adjust bit-1 for crc */\n\t\tcur_dat1 = orig_dat1;\n\t\tcur_dat2 = orig_dat2;\n\t\tcur_dat3 = orig_dat3;\n\n\t\tcur_rxdly0 = (cur_dat0 << 24) | (cur_dat1 << 16) | (cur_dat2 << 8) | (cur_dat3 << 0);\n\t\tsdr_write32(MSDC_DAT_RDDLY0, cur_rxdly0);\n\t} while (++rxdly < 32);\n\ndone:\n\treturn result;\n}\n\nstatic int msdc_get_card_status(struct mmc_host *mmc, struct msdc_host *host, u32 *status)\n{\n\tstruct mmc_command cmd;\n\tstruct mmc_request mrq;\n\tu32 err;\n\n\tmemset(&cmd, 0, sizeof(struct mmc_command));\n\tcmd.opcode = MMC_SEND_STATUS;\n\tif (mmc->card) {\n\t\tcmd.arg = mmc->card->rca << 16;\n\t} else {\n\t\tERR_MSG(\"cmd13 mmc card is null\");\n\t\tcmd.arg = host->app_cmd_arg;\n\t}\n\tcmd.flags = MMC_RSP_SPI_R2 | MMC_RSP_R1 | MMC_CMD_AC;\n\n\tmemset(&mrq, 0, sizeof(struct mmc_request));\n\tmrq.cmd = &cmd; cmd.mrq = &mrq;\n\tcmd.data = NULL;\n\n\terr = msdc_do_command(host, &cmd, 1, CMD_TIMEOUT);\n\n\tif (status)\n\t\t*status = cmd.resp[0];\n\n\treturn err;\n}\n\nstatic int msdc_check_busy(struct mmc_host *mmc, struct msdc_host *host)\n{\n\tu32 err = 0;\n\tu32 status = 0;\n\n\tdo {\n\t\terr = msdc_get_card_status(mmc, host, &status);\n\t\tif (err)\n\t\t\treturn err;\n\t\t/* need cmd12? */\n\t\tERR_MSG(\"cmd<13> resp<0x%x>\", status);\n\t} while (R1_CURRENT_STATE(status) == 7);\n\n\treturn err;\n}\n\n/* failed when msdc_do_request */\nstatic int msdc_tune_request(struct mmc_host *mmc, struct mmc_request *mrq)\n{\n\tstruct msdc_host *host = mmc_priv(mmc);\n\tstruct mmc_command *cmd;\n\tstruct mmc_data *data;\n\t//u32 base = host->base;\n\tint ret = 0, read;\n\n\tcmd  = mrq->cmd;\n\tdata = mrq->cmd->data;\n\n\tread = data->flags & MMC_DATA_READ ? 1 : 0;\n\n\tif (read) {\n\t\tif (data->error == -EIO)\n\t\t\tret = msdc_tune_bread(mmc, mrq);\n\t} else {\n\t\tret = msdc_check_busy(mmc, host);\n\t\tif (ret) {\n\t\t\tERR_MSG(\"XXX cmd13 wait program done failed\");\n\t\t\treturn ret;\n\t\t}\n\t\t/* CRC and TO */\n\t\t/* Fix me: don't care card status? */\n\t\tret = msdc_tune_bwrite(mmc, mrq);\n\t}\n\n\treturn ret;\n}\n\n/* ops.request */\nstatic void msdc_ops_request(struct mmc_host *mmc, struct mmc_request *mrq)\n{\n\tstruct msdc_host *host = mmc_priv(mmc);\n\n\t//=== for sdio profile ===\n#if 0 /* --- by chhung */\n\tu32 old_H32, old_L32, new_H32, new_L32;\n\tu32 ticks = 0, opcode = 0, sizes = 0, bRx = 0;\n#endif /* end of --- */\n\n\tWARN_ON(host->mrq);\n\n\t/* start to process */\n\tspin_lock(&host->lock);\n#if 0 /* --- by chhung */\n\tif (sdio_pro_enable) {  //=== for sdio profile ===\n\t\tif (mrq->cmd->opcode == 52 || mrq->cmd->opcode == 53)\n\t\t\tGPT_GetCounter64(&old_L32, &old_H32);\n\t}\n#endif /* end of --- */\n\n\thost->mrq = mrq;\n\n\tif (msdc_do_request(mmc, mrq)) {\n\t\tif (host->hw->flags & MSDC_REMOVABLE && ralink_soc == MT762X_SOC_MT7621AT && mrq->data && mrq->data->error)\n\t\t\tmsdc_tune_request(mmc, mrq);\n\t}\n\n\t/* ==== when request done, check if app_cmd ==== */\n\tif (mrq->cmd->opcode == MMC_APP_CMD) {\n\t\thost->app_cmd = 1;\n\t\thost->app_cmd_arg = mrq->cmd->arg;  /* save the RCA */\n\t} else {\n\t\thost->app_cmd = 0;\n\t\t//host->app_cmd_arg = 0;\n\t}\n\n\thost->mrq = NULL;\n\n#if 0 /* --- by chhung */\n\t//=== for sdio profile ===\n\tif (sdio_pro_enable) {\n\t\tif (mrq->cmd->opcode == 52 || mrq->cmd->opcode == 53) {\n\t\t\tGPT_GetCounter64(&new_L32, &new_H32);\n\t\t\tticks = msdc_time_calc(old_L32, old_H32, new_L32, new_H32);\n\n\t\t\topcode = mrq->cmd->opcode;\n\t\t\tif (mrq->cmd->data) {\n\t\t\t\tsizes = mrq->cmd->data->blocks * mrq->cmd->data->blksz;\n\t\t\t\tbRx = mrq->cmd->data->flags & MMC_DATA_READ ? 1 : 0;\n\t\t\t} else {\n\t\t\t\tbRx = mrq->cmd->arg\t& 0x80000000 ? 1 : 0;\n\t\t\t}\n\n\t\t\tif (!mrq->cmd->error)\n\t\t\t\tmsdc_performance(opcode, sizes, bRx, ticks);\n\t\t}\n\t}\n#endif /* end of --- */\n\tspin_unlock(&host->lock);\n\n\tmmc_request_done(mmc, mrq);\n\n\treturn;\n}\n\n/* called by ops.set_ios */\nstatic void msdc_set_buswidth(struct msdc_host *host, u32 width)\n{\n\tvoid __iomem *base = host->base;\n\tu32 val = sdr_read32(SDC_CFG);\n\n\tval &= ~SDC_CFG_BUSWIDTH;\n\n\tswitch (width) {\n\tdefault:\n\tcase MMC_BUS_WIDTH_1:\n\t\twidth = 1;\n\t\tval |= (MSDC_BUS_1BITS << 16);\n\t\tbreak;\n\tcase MMC_BUS_WIDTH_4:\n\t\tval |= (MSDC_BUS_4BITS << 16);\n\t\tbreak;\n\tcase MMC_BUS_WIDTH_8:\n\t\tval |= (MSDC_BUS_8BITS << 16);\n\t\tbreak;\n\t}\n\n\tsdr_write32(SDC_CFG, val);\n\n\tN_MSG(CFG, \"Bus Width = %d\", width);\n}\n\n/* ops.set_ios */\nstatic void msdc_ops_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)\n{\n\tstruct msdc_host *host = mmc_priv(mmc);\n\tvoid __iomem *base = host->base;\n\tu32 ddr = 0;\n\n#ifdef MT6575_SD_DEBUG\n\tstatic char *vdd[] = {\n\t\t\"1.50v\", \"1.55v\", \"1.60v\", \"1.65v\", \"1.70v\", \"1.80v\", \"1.90v\",\n\t\t\"2.00v\", \"2.10v\", \"2.20v\", \"2.30v\", \"2.40v\", \"2.50v\", \"2.60v\",\n\t\t\"2.70v\", \"2.80v\", \"2.90v\", \"3.00v\", \"3.10v\", \"3.20v\", \"3.30v\",\n\t\t\"3.40v\", \"3.50v\", \"3.60v\"\n\t};\n\tstatic char *power_mode[] = {\n\t\t\"OFF\", \"UP\", \"ON\"\n\t};\n\tstatic char *bus_mode[] = {\n\t\t\"UNKNOWN\", \"OPENDRAIN\", \"PUSHPULL\"\n\t};\n\tstatic char *timing[] = {\n\t\t\"LEGACY\", \"MMC_HS\", \"SD_HS\"\n\t};\n\n\tprintk(\"SET_IOS: CLK(%dkHz), BUS(%s), BW(%u), PWR(%s), VDD(%s), TIMING(%s)\",\n\t\tios->clock / 1000, bus_mode[ios->bus_mode],\n\t\t(ios->bus_width == MMC_BUS_WIDTH_4) ? 4 : 1,\n\t\tpower_mode[ios->power_mode], vdd[ios->vdd], timing[ios->timing]);\n#endif\n\n\tmsdc_set_buswidth(host, ios->bus_width);\n\n\t/* Power control ??? */\n\tswitch (ios->power_mode) {\n\tcase MMC_POWER_OFF:\n\tcase MMC_POWER_UP:\n\t\t// msdc_set_power_mode(host, ios->power_mode); /* --- by chhung */\n\t\tbreak;\n\tcase MMC_POWER_ON:\n\t\thost->power_mode = MMC_POWER_ON;\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\n\t/* Clock control */\n\tif (host->mclk != ios->clock) {\n\t\tif (ios->clock > 25000000) {\n\t\t\t//if (!(host->hw->flags & MSDC_REMOVABLE)) {\n\t\t\tINIT_MSG(\"SD data latch edge<%d>\", MSDC_SMPL_FALLING);\n\t\t\tsdr_set_field(MSDC_IOCON, MSDC_IOCON_RSPL,\n\t\t\t\t      MSDC_SMPL_FALLING);\n\t\t\tsdr_set_field(MSDC_IOCON, MSDC_IOCON_DSPL,\n\t\t\t\t      MSDC_SMPL_FALLING);\n\t\t\t//} /* for tuning debug */\n\t\t} else { /* default value */\n\t\t\tsdr_write32(MSDC_IOCON,      0x00000000);\n\t\t\t// sdr_write32(MSDC_DAT_RDDLY0, 0x00000000);\n\t\t\tsdr_write32(MSDC_DAT_RDDLY0, 0x10101010);\t\t// for MT7620 E2 and afterward\n\t\t\tsdr_write32(MSDC_DAT_RDDLY1, 0x00000000);\n\t\t\t// sdr_write32(MSDC_PAD_TUNE,   0x00000000);\n\t\t\tsdr_write32(MSDC_PAD_TUNE,   0x84101010);\t\t// for MT7620 E2 and afterward\n\t\t}\n\t\tmsdc_set_mclk(host, ddr, ios->clock);\n\t}\n}\n\n/* ops.get_ro */\nstatic int msdc_ops_get_ro(struct mmc_host *mmc)\n{\n\tstruct msdc_host *host = mmc_priv(mmc);\n\tvoid __iomem *base = host->base;\n\tunsigned long flags;\n\tint ro = 0;\n\n\tif (host->hw->flags & MSDC_WP_PIN_EN) { /* set for card */\n\t\tspin_lock_irqsave(&host->lock, flags);\n\t\tro = (sdr_read32(MSDC_PS) >> 31);\n\t\tspin_unlock_irqrestore(&host->lock, flags);\n\t}\n\treturn ro;\n}\n\n/* ops.get_cd */\nstatic int msdc_ops_get_cd(struct mmc_host *mmc)\n{\n\tstruct msdc_host *host = mmc_priv(mmc);\n\tvoid __iomem *base = host->base;\n\tunsigned long flags;\n\tint present = 1;\n\n\t/* for sdio, MSDC_REMOVABLE not set, always return 1 */\n\tif (!(host->hw->flags & MSDC_REMOVABLE)) {\n\t\t/* For sdio, read H/W always get<1>, but may timeout some times */\n#if 1\n\t\thost->card_inserted = 1;\n\t\treturn 1;\n#else\n\t\thost->card_inserted = (host->pm_state.event == PM_EVENT_USER_RESUME) ? 1 : 0;\n\t\tINIT_MSG(\"sdio ops_get_cd<%d>\", host->card_inserted);\n\t\treturn host->card_inserted;\n#endif\n\t}\n\n\t/* MSDC_CD_PIN_EN set for card */\n\tif (host->hw->flags & MSDC_CD_PIN_EN) {\n\t\tspin_lock_irqsave(&host->lock, flags);\n#if 0\n\t\tpresent = host->card_inserted;  /* why not read from H/W: Fix me*/\n#else\n\t\t// CD\n\t\tif (cd_active_low)\n\t\t\tpresent = (sdr_read32(MSDC_PS) & MSDC_PS_CDSTS) ? 0 : 1;\n\t\telse\n\t\t\tpresent = (sdr_read32(MSDC_PS) & MSDC_PS_CDSTS) ? 1 : 0;\n\t\tif (host->mmc->caps & MMC_CAP_NEEDS_POLL)\n\t\t\tpresent = 1;\n\t\thost->card_inserted = present;\n#endif\n\t\tspin_unlock_irqrestore(&host->lock, flags);\n\t} else {\n\t\tpresent = 0; /* TODO? Check DAT3 pins for card detection */\n\t}\n\n\tINIT_MSG(\"ops_get_cd return<%d>\", present);\n\treturn present;\n}\n\nstatic struct mmc_host_ops mt_msdc_ops = {\n\t.request         = msdc_ops_request,\n\t.set_ios         = msdc_ops_set_ios,\n\t.get_ro          = msdc_ops_get_ro,\n\t.get_cd          = msdc_ops_get_cd,\n};\n\n/*--------------------------------------------------------------------------*/\n/* interrupt handler                                                    */\n/*--------------------------------------------------------------------------*/\nstatic irqreturn_t msdc_irq(int irq, void *dev_id)\n{\n\tstruct msdc_host  *host = (struct msdc_host *)dev_id;\n\tstruct mmc_data   *data = host->data;\n\tstruct mmc_command *cmd = host->cmd;\n\tvoid __iomem *base = host->base;\n\n\tu32 cmdsts = MSDC_INT_RSPCRCERR  | MSDC_INT_CMDTMO  | MSDC_INT_CMDRDY  |\n\t\tMSDC_INT_ACMDCRCERR | MSDC_INT_ACMDTMO | MSDC_INT_ACMDRDY |\n\t\tMSDC_INT_ACMD19_DONE;\n\tu32 datsts = MSDC_INT_DATCRCERR | MSDC_INT_DATTMO;\n\n\tu32 intsts = sdr_read32(MSDC_INT);\n\tu32 inten  = sdr_read32(MSDC_INTEN); inten &= intsts;\n\n\tsdr_write32(MSDC_INT, intsts);  /* clear interrupts */\n\t/* MSG will cause fatal error */\n\n\t/* card change interrupt */\n\tif (intsts & MSDC_INT_CDSC) {\n\t\tif (host->mmc->caps & MMC_CAP_NEEDS_POLL)\n\t\t\treturn IRQ_HANDLED;\n\t\tIRQ_MSG(\"MSDC_INT_CDSC irq<0x%.8x>\", intsts);\n\t\tschedule_delayed_work(&host->card_delaywork, HZ);\n\t\t/* tuning when plug card ? */\n\t}\n\n\t/* sdio interrupt */\n\tif (intsts & MSDC_INT_SDIOIRQ) {\n\t\tIRQ_MSG(\"XXX MSDC_INT_SDIOIRQ\");  /* seems not sdio irq */\n\t\t//mmc_signal_sdio_irq(host->mmc);\n\t}\n\n\t/* transfer complete interrupt */\n\tif (data != NULL) {\n\t\tif (inten & MSDC_INT_XFER_COMPL) {\n\t\t\tdata->bytes_xfered = host->xfer_size;\n\t\t\tcomplete(&host->xfer_done);\n\t\t}\n\n\t\tif (intsts & datsts) {\n\t\t\t/* do basic reset, or stop command will sdc_busy */\n\t\t\tmsdc_reset_hw(host);\n\t\t\tmsdc_clr_fifo();\n\t\t\tmsdc_clr_int();\n\n\t\t\tif (intsts & MSDC_INT_DATTMO) {\n\t\t\t\tIRQ_MSG(\"XXX CMD<%d> MSDC_INT_DATTMO\", host->mrq->cmd->opcode);\n\t\t\t\tdata->error = -ETIMEDOUT;\n\t\t\t} else if (intsts & MSDC_INT_DATCRCERR) {\n\t\t\t\tIRQ_MSG(\"XXX CMD<%d> MSDC_INT_DATCRCERR, SDC_DCRC_STS<0x%x>\", host->mrq->cmd->opcode, sdr_read32(SDC_DCRC_STS));\n\t\t\t\tdata->error = -EIO;\n\t\t\t}\n\n\t\t\t//if(sdr_read32(MSDC_INTEN) & MSDC_INT_XFER_COMPL) {\n\t\t\tcomplete(&host->xfer_done); /* Read CRC come fast, XFER_COMPL not enabled */\n\t\t}\n\t}\n\n\t/* command interrupts */\n\tif ((cmd != NULL) && (intsts & cmdsts)) {\n\t\tif ((intsts & MSDC_INT_CMDRDY) || (intsts & MSDC_INT_ACMDRDY) ||\n\t\t\t(intsts & MSDC_INT_ACMD19_DONE)) {\n\t\t\tu32 *rsp = &cmd->resp[0];\n\n\t\t\tswitch (host->cmd_rsp) {\n\t\t\tcase RESP_NONE:\n\t\t\t\tbreak;\n\t\t\tcase RESP_R2:\n\t\t\t\t*rsp++ = sdr_read32(SDC_RESP3); *rsp++ = sdr_read32(SDC_RESP2);\n\t\t\t\t*rsp++ = sdr_read32(SDC_RESP1); *rsp++ = sdr_read32(SDC_RESP0);\n\t\t\t\tbreak;\n\t\t\tdefault: /* Response types 1, 3, 4, 5, 6, 7(1b) */\n\t\t\t\tif ((intsts & MSDC_INT_ACMDRDY) || (intsts & MSDC_INT_ACMD19_DONE))\n\t\t\t\t\t*rsp = sdr_read32(SDC_ACMD_RESP);\n\t\t\t\telse\n\t\t\t\t\t*rsp = sdr_read32(SDC_RESP0);\n\t\t\t\tbreak;\n\t\t\t}\n\t\t} else if ((intsts & MSDC_INT_RSPCRCERR) || (intsts & MSDC_INT_ACMDCRCERR)) {\n\t\t\tif (intsts & MSDC_INT_ACMDCRCERR)\n\t\t\t\tIRQ_MSG(\"XXX CMD<%d> MSDC_INT_ACMDCRCERR\", cmd->opcode);\n\t\t\telse\n\t\t\t\tIRQ_MSG(\"XXX CMD<%d> MSDC_INT_RSPCRCERR\", cmd->opcode);\n\t\t\tcmd->error = -EIO;\n\t\t} else if ((intsts & MSDC_INT_CMDTMO) || (intsts & MSDC_INT_ACMDTMO)) {\n\t\t\tif (intsts & MSDC_INT_ACMDTMO)\n\t\t\t\tIRQ_MSG(\"XXX CMD<%d> MSDC_INT_ACMDTMO\", cmd->opcode);\n\t\t\telse\n\t\t\t\tIRQ_MSG(\"XXX CMD<%d> MSDC_INT_CMDTMO\", cmd->opcode);\n\t\t\tcmd->error = -ETIMEDOUT;\n\t\t\tmsdc_reset_hw(host);\n\t\t\tmsdc_clr_fifo();\n\t\t\tmsdc_clr_int();\n\t\t}\n\t\tcomplete(&host->cmd_done);\n\t}\n\n\t/* mmc irq interrupts */\n\tif (intsts & MSDC_INT_MMCIRQ)\n\t\tprintk(KERN_INFO \"msdc[%d] MMCIRQ: SDC_CSTS=0x%.8x\\r\\n\", host->id, sdr_read32(SDC_CSTS));\n\n#ifdef MT6575_SD_DEBUG\n\t{\n/*        msdc_int_reg *int_reg = (msdc_int_reg*)&intsts;*/\n\t\tN_MSG(INT, \"IRQ_EVT(0x%x): MMCIRQ(%d) CDSC(%d), ACRDY(%d), ACTMO(%d), ACCRE(%d) AC19DN(%d)\",\n\t\t\tintsts,\n\t\t\tint_reg->mmcirq,\n\t\t\tint_reg->cdsc,\n\t\t\tint_reg->atocmdrdy,\n\t\t\tint_reg->atocmdtmo,\n\t\t\tint_reg->atocmdcrc,\n\t\t\tint_reg->atocmd19done);\n\t\tN_MSG(INT, \"IRQ_EVT(0x%x): SDIO(%d) CMDRDY(%d), CMDTMO(%d), RSPCRC(%d), CSTA(%d)\",\n\t\t\tintsts,\n\t\t\tint_reg->sdioirq,\n\t\t\tint_reg->cmdrdy,\n\t\t\tint_reg->cmdtmo,\n\t\t\tint_reg->rspcrc,\n\t\t\tint_reg->csta);\n\t\tN_MSG(INT, \"IRQ_EVT(0x%x): XFCMP(%d) DXDONE(%d), DATTMO(%d), DATCRC(%d), DMAEMP(%d)\",\n\t\t\tintsts,\n\t\t\tint_reg->xfercomp,\n\t\t\tint_reg->dxferdone,\n\t\t\tint_reg->dattmo,\n\t\t\tint_reg->datcrc,\n\t\t\tint_reg->dmaqempty);\n\t}\n#endif\n\n\treturn IRQ_HANDLED;\n}\n\n/*--------------------------------------------------------------------------*/\n/* platform_driver members                                                      */\n/*--------------------------------------------------------------------------*/\n/* called by msdc_drv_probe/remove */\nstatic void msdc_enable_cd_irq(struct msdc_host *host, int enable)\n{\n\tstruct msdc_hw *hw = host->hw;\n\tvoid __iomem *base = host->base;\n\n\t/* for sdio, not set */\n\tif ((hw->flags & MSDC_CD_PIN_EN) == 0) {\n\t\t/* Pull down card detection pin since it is not avaiable */\n\t\t/*\n\t\t  if (hw->config_gpio_pin)\n\t\t  hw->config_gpio_pin(MSDC_CD_PIN, GPIO_PULL_DOWN);\n\t\t*/\n\t\tsdr_clr_bits(MSDC_PS, MSDC_PS_CDEN);\n\t\tsdr_clr_bits(MSDC_INTEN, MSDC_INTEN_CDSC);\n\t\tsdr_clr_bits(SDC_CFG, SDC_CFG_INSWKUP);\n\t\treturn;\n\t}\n\n\tN_MSG(CFG, \"CD IRQ Eanable(%d)\", enable);\n\n\tif (enable) {\n\t\t/* card detection circuit relies on the core power so that the core power\n\t\t * shouldn't be turned off. Here adds a reference count to keep\n\t\t * the core power alive.\n\t\t */\n\t\t//msdc_vcore_on(host); //did in msdc_init_hw()\n\n\t\tif (hw->config_gpio_pin) /* NULL */\n\t\t\thw->config_gpio_pin(MSDC_CD_PIN, GPIO_PULL_UP);\n\n\t\tsdr_set_field(MSDC_PS, MSDC_PS_CDDEBOUNCE, DEFAULT_DEBOUNCE);\n\t\tsdr_set_bits(MSDC_PS, MSDC_PS_CDEN);\n\t\tsdr_set_bits(MSDC_INTEN, MSDC_INTEN_CDSC);\n\t\tsdr_set_bits(SDC_CFG, SDC_CFG_INSWKUP);  /* not in document! Fix me */\n\t} else {\n\t\tif (hw->config_gpio_pin) /* NULL */\n\t\t\thw->config_gpio_pin(MSDC_CD_PIN, GPIO_PULL_DOWN);\n\n\t\tsdr_clr_bits(SDC_CFG, SDC_CFG_INSWKUP);\n\t\tsdr_clr_bits(MSDC_PS, MSDC_PS_CDEN);\n\t\tsdr_clr_bits(MSDC_INTEN, MSDC_INTEN_CDSC);\n\n\t\t/* Here decreases a reference count to core power since card\n\t\t * detection circuit is shutdown.\n\t\t */\n\t\t//msdc_vcore_off(host);\n\t}\n}\n\n/* called by msdc_drv_probe */\nstatic void msdc_init_hw(struct msdc_host *host)\n{\n\tvoid __iomem *base = host->base;\n\n\t/* Power on */\n#if 0 /* --- by chhung */\n\tmsdc_vcore_on(host);\n\tmsdc_pin_reset(host, MSDC_PIN_PULL_UP);\n\tmsdc_select_clksrc(host, hw->clk_src);\n\tenable_clock(PERI_MSDC0_PDN + host->id, \"SD\");\n\tmsdc_vdd_on(host);\n#endif /* end of --- */\n\t/* Configure to MMC/SD mode */\n\tsdr_set_field(MSDC_CFG, MSDC_CFG_MODE, MSDC_SDMMC);\n\n\t/* Reset */\n\tmsdc_reset_hw(host);\n\tmsdc_clr_fifo();\n\n\t/* Disable card detection */\n\tsdr_clr_bits(MSDC_PS, MSDC_PS_CDEN);\n\n\t/* Disable and clear all interrupts */\n\tsdr_clr_bits(MSDC_INTEN, sdr_read32(MSDC_INTEN));\n\tsdr_write32(MSDC_INT, sdr_read32(MSDC_INT));\n\n#if 1\n\t/* reset tuning parameter */\n\tsdr_write32(MSDC_PAD_CTL0,   0x00090000);\n\tsdr_write32(MSDC_PAD_CTL1,   0x000A0000);\n\tsdr_write32(MSDC_PAD_CTL2,   0x000A0000);\n\t// sdr_write32(MSDC_PAD_TUNE,   0x00000000);\n\tsdr_write32(MSDC_PAD_TUNE,   0x84101010);\t\t// for MT7620 E2 and afterward\n\t// sdr_write32(MSDC_DAT_RDDLY0, 0x00000000);\n\tsdr_write32(MSDC_DAT_RDDLY0, 0x10101010);\t\t// for MT7620 E2 and afterward\n\tsdr_write32(MSDC_DAT_RDDLY1, 0x00000000);\n\tsdr_write32(MSDC_IOCON,      0x00000000);\n#if 0 // use MT7620 default value: 0x403c004f\n\tsdr_write32(MSDC_PATCH_BIT0, 0x003C000F); /* bit0 modified: Rx Data Clock Source: 1 -> 2.0*/\n#endif\n\n\tif (sdr_read32(MSDC_ECO_VER) >= 4) {\n\t\tif (host->id == 1) {\n\t\t\tsdr_set_field(MSDC_PATCH_BIT1, MSDC_PATCH_BIT1_WRDAT_CRCS, 1);\n\t\t\tsdr_set_field(MSDC_PATCH_BIT1, MSDC_PATCH_BIT1_CMD_RSP,    1);\n\n\t\t\t/* internal clock: latch read data */\n\t\t\tsdr_set_bits(MSDC_PATCH_BIT0, MSDC_PATCH_BIT_CKGEN_CK);\n\t\t}\n\t}\n#endif\n\n\t/* for safety, should clear SDC_CFG.SDIO_INT_DET_EN & set SDC_CFG.SDIO in\n\t   pre-loader,uboot,kernel drivers. and SDC_CFG.SDIO_INT_DET_EN will be only\n\t   set when kernel driver wants to use SDIO bus interrupt */\n\t/* Configure to enable SDIO mode. it's must otherwise sdio cmd5 failed */\n\tsdr_set_bits(SDC_CFG, SDC_CFG_SDIO);\n\n\t/* disable detect SDIO device interupt function */\n\tsdr_clr_bits(SDC_CFG, SDC_CFG_SDIOIDE);\n\n\t/* eneable SMT for glitch filter */\n\tsdr_set_bits(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKSMT);\n\tsdr_set_bits(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDSMT);\n\tsdr_set_bits(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATSMT);\n\n#if 1\n\t/* set clk, cmd, dat pad driving */\n\tsdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKDRVN, 4);\n\tsdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKDRVP, 4);\n\tsdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDDRVN, 4);\n\tsdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDDRVP, 4);\n\tsdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATDRVN, 4);\n\tsdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATDRVP, 4);\n#else\n\tsdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKDRVN, 0);\n\tsdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKDRVP, 0);\n\tsdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDDRVN, 0);\n\tsdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDDRVP, 0);\n\tsdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATDRVN, 0);\n\tsdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATDRVP, 0);\n#endif\n\n\t/* set sampling edge */\n\n\t/* write crc timeout detection */\n\tsdr_set_field(MSDC_PATCH_BIT0, 1 << 30, 1);\n\n\t/* Configure to default data timeout */\n\tsdr_set_field(SDC_CFG, SDC_CFG_DTOC, DEFAULT_DTOC);\n\n\tmsdc_set_buswidth(host, MMC_BUS_WIDTH_1);\n\n\tN_MSG(FUC, \"init hardware done!\");\n}\n\n/* called by msdc_drv_remove */\nstatic void msdc_deinit_hw(struct msdc_host *host)\n{\n\tvoid __iomem *base = host->base;\n\n\t/* Disable and clear all interrupts */\n\tsdr_clr_bits(MSDC_INTEN, sdr_read32(MSDC_INTEN));\n\tsdr_write32(MSDC_INT, sdr_read32(MSDC_INT));\n\n\t/* Disable card detection */\n\tmsdc_enable_cd_irq(host, 0);\n\t// msdc_set_power_mode(host, MMC_POWER_OFF);   /* make sure power down */ /* --- by chhung */\n}\n\n/* init gpd and bd list in msdc_drv_probe */\nstatic void msdc_init_gpd_bd(struct msdc_host *host, struct msdc_dma *dma)\n{\n\tstruct gpd *gpd = dma->gpd;\n\tstruct bd  *bd  = dma->bd;\n\tint i;\n\n\t/* we just support one gpd, but gpd->next must be set for desc\n\t * DMA. That's why we alloc 2 gpd structurs.\n\t */\n\n\tmemset(gpd, 0, sizeof(struct gpd) * 2);\n\n\tgpd->bdp  = 1;   /* hwo, cs, bd pointer */\n\tgpd->ptr = (void *)dma->bd_addr; /* physical address */\n\tgpd->next = (void *)((u32)dma->gpd_addr + sizeof(struct gpd));\n\n\tmemset(bd, 0, sizeof(struct bd) * MAX_BD_NUM);\n\tfor (i = 0; i < (MAX_BD_NUM - 1); i++)\n\t\tbd[i].next = (void *)(dma->bd_addr + sizeof(*bd) * (i + 1));\n}\n\nstatic int msdc_drv_probe(struct platform_device *pdev)\n{\n\tstruct resource *res;\n\t__iomem void *base;\n\tstruct mmc_host *mmc;\n\tstruct msdc_host *host;\n\tstruct msdc_hw *hw;\n\tint ret;\n\n\t//FIXME: this should be done by pinconf and not by the sd driver\n\tif ((ralink_soc == MT762X_SOC_MT7688 ||\n\t     ralink_soc == MT762X_SOC_MT7628AN) &&\n\t    (!(rt_sysc_r32(0x60) & BIT(15))))\n\t\trt_sysc_m32(0xf << 17, 0xf << 17, 0x3c);\n\n\thw = &msdc0_hw;\n\n\tif (of_property_read_bool(pdev->dev.of_node, \"mtk,wp-en\"))\n\t\tmsdc0_hw.flags |= MSDC_WP_PIN_EN;\n\n\t/* Allocate MMC host for this device */\n\tmmc = mmc_alloc_host(sizeof(struct msdc_host), &pdev->dev);\n\tif (!mmc)\n\t\treturn -ENOMEM;\n\n\tres = platform_get_resource(pdev, IORESOURCE_MEM, 0);\n\tbase = devm_ioremap_resource(&pdev->dev, res);\n\tif (IS_ERR(base)) {\n\t\tret = PTR_ERR(base);\n\t\tgoto host_free;\n\t}\n\n\t/* Set host parameters to mmc */\n\tmmc->ops        = &mt_msdc_ops;\n\tmmc->f_min      = HOST_MIN_MCLK;\n\tmmc->f_max      = HOST_MAX_MCLK;\n\tmmc->ocr_avail  = MSDC_OCR_AVAIL;\n\n\tmmc->caps   = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED;\n\n\t//TODO: read this as bus-width from dt (via mmc_of_parse)\n\tmmc->caps  |= MMC_CAP_4_BIT_DATA;\n\n\tcd_active_low = !of_property_read_bool(pdev->dev.of_node, \"mediatek,cd-high\");\n\n\tif (of_property_read_bool(pdev->dev.of_node, \"mediatek,cd-poll\"))\n\t\tmmc->caps |= MMC_CAP_NEEDS_POLL;\n\n\t/* MMC core transfer sizes tunable parameters */\n\tmmc->max_segs      = MAX_HW_SGMTS;\n\n\tmmc->max_seg_size  = MAX_SGMT_SZ;\n\tmmc->max_blk_size  = HOST_MAX_BLKSZ;\n\tmmc->max_req_size  = MAX_REQ_SZ;\n\tmmc->max_blk_count = mmc->max_req_size;\n\n\thost = mmc_priv(mmc);\n\thost->hw        = hw;\n\thost->mmc       = mmc;\n\thost->id        = pdev->id;\n\tif (host->id < 0 || host->id >= 4)\n\t\thost->id = 0;\n\thost->error     = 0;\n\n\thost->irq       = platform_get_irq(pdev, 0);\n\tif (host->irq < 0) {\n\t\tret = -EINVAL;\n\t\tgoto host_free;\n\t}\n\n\thost->base      = base;\n\thost->mclk      = 0;                   /* mclk: the request clock of mmc sub-system */\n\thost->hclk      = hclks[hw->clk_src];  /* hclk: clock of clock source to msdc controller */\n\thost->sclk      = 0;                   /* sclk: the really clock after divition */\n\thost->pm_state  = PMSG_RESUME;\n\thost->suspend   = 0;\n\thost->core_clkon = 0;\n\thost->card_clkon = 0;\n\thost->core_power = 0;\n\thost->power_mode = MMC_POWER_OFF;\n//    host->card_inserted = hw->flags & MSDC_REMOVABLE ? 0 : 1;\n\thost->timeout_ns = 0;\n\thost->timeout_clks = DEFAULT_DTOC * 65536;\n\n\thost->mrq = NULL;\n\t//init_MUTEX(&host->sem); /* we don't need to support multiple threads access */\n\n\tdma_coerce_mask_and_coherent(mmc_dev(mmc), DMA_BIT_MASK(32));\n\n\t/* using dma_alloc_coherent*/  /* todo: using 1, for all 4 slots */\n\thost->dma.gpd = dma_alloc_coherent(&pdev->dev,\n\t\t\t\t\t   MAX_GPD_NUM * sizeof(struct gpd),\n\t\t\t\t\t   &host->dma.gpd_addr, GFP_KERNEL);\n\thost->dma.bd =  dma_alloc_coherent(&pdev->dev,\n\t\t\t\t\t   MAX_BD_NUM  * sizeof(struct bd),\n\t\t\t\t\t   &host->dma.bd_addr,  GFP_KERNEL);\n\tif (!host->dma.gpd || !host->dma.bd) {\n\t\tret = -ENOMEM;\n\t\tgoto release_mem;\n\t}\n\tmsdc_init_gpd_bd(host, &host->dma);\n\n\tINIT_DELAYED_WORK(&host->card_delaywork, msdc_tasklet_card);\n\tspin_lock_init(&host->lock);\n\tmsdc_init_hw(host);\n\n\t/* TODO check weather flags 0 is correct, the mtk-sd driver uses\n\t * IRQF_TRIGGER_LOW | IRQF_ONESHOT for flags\n\t *\n\t * for flags 0 the trigger polarity is determined by the\n\t * device tree, but not the oneshot flag, but maybe it is also\n\t * not needed because the soc could be oneshot safe.\n\t */\n\tret = devm_request_irq(&pdev->dev, host->irq, msdc_irq, 0, pdev->name,\n\t\t\t       host);\n\tif (ret)\n\t\tgoto release;\n\n\tplatform_set_drvdata(pdev, mmc);\n\n\tret = mmc_add_host(mmc);\n\tif (ret)\n\t\tgoto release;\n\n\t/* Config card detection pin and enable interrupts */\n\tif (hw->flags & MSDC_CD_PIN_EN) {  /* set for card */\n\t\tmsdc_enable_cd_irq(host, 1);\n\t} else {\n\t\tmsdc_enable_cd_irq(host, 0);\n\t}\n\n\treturn 0;\n\nrelease:\n\tplatform_set_drvdata(pdev, NULL);\n\tmsdc_deinit_hw(host);\n\tcancel_delayed_work_sync(&host->card_delaywork);\n\nrelease_mem:\n\tif (host->dma.gpd)\n\t\tdma_free_coherent(&pdev->dev, MAX_GPD_NUM * sizeof(struct gpd),\n\t\t\t\t  host->dma.gpd, host->dma.gpd_addr);\n\tif (host->dma.bd)\n\t\tdma_free_coherent(&pdev->dev, MAX_BD_NUM * sizeof(struct bd),\n\t\t\t\t  host->dma.bd, host->dma.bd_addr);\nhost_free:\n\tmmc_free_host(mmc);\n\n\treturn ret;\n}\n\n/* 4 device share one driver, using \"drvdata\" to show difference */\nstatic int msdc_drv_remove(struct platform_device *pdev)\n{\n\tstruct mmc_host *mmc;\n\tstruct msdc_host *host;\n\n\tmmc  = platform_get_drvdata(pdev);\n\tBUG_ON(!mmc);\n\n\thost = mmc_priv(mmc);\n\tBUG_ON(!host);\n\n\tERR_MSG(\"removed !!!\");\n\n\tplatform_set_drvdata(pdev, NULL);\n\tmmc_remove_host(host->mmc);\n\tmsdc_deinit_hw(host);\n\n\tcancel_delayed_work_sync(&host->card_delaywork);\n\n\tdma_free_coherent(&pdev->dev, MAX_GPD_NUM * sizeof(struct gpd),\n\t\t\t  host->dma.gpd, host->dma.gpd_addr);\n\tdma_free_coherent(&pdev->dev, MAX_BD_NUM  * sizeof(struct bd),\n\t\t\t  host->dma.bd,  host->dma.bd_addr);\n\n\tmmc_free_host(host->mmc);\n\n\treturn 0;\n}\n\n/* Fix me: Power Flow */\n#ifdef CONFIG_PM\n\nstatic void msdc_drv_pm(struct platform_device *pdev, pm_message_t state)\n{\n\tstruct mmc_host *mmc = platform_get_drvdata(pdev);\n\tif (mmc) {\n\t\tstruct msdc_host *host = mmc_priv(mmc);\n\t\tmsdc_pm(state, (void *)host);\n\t}\n}\n\nstatic int msdc_drv_suspend(struct platform_device *pdev, pm_message_t state)\n{\n\tif (state.event == PM_EVENT_SUSPEND)\n\t\tmsdc_drv_pm(pdev, state);\n\treturn 0;\n}\n\nstatic int msdc_drv_resume(struct platform_device *pdev)\n{\n\tstruct pm_message state;\n\n\tstate.event = PM_EVENT_RESUME;\n\tmsdc_drv_pm(pdev, state);\n\treturn 0;\n}\n#endif\n\nstatic const struct of_device_id mt7620_sdhci_match[] = {\n\t{ .compatible = \"ralink,mt7620-sdhci\" },\n\t{},\n};\nMODULE_DEVICE_TABLE(of, mt7620_sdhci_match);\n\nstatic struct platform_driver mt_msdc_driver = {\n\t.probe   = msdc_drv_probe,\n\t.remove  = msdc_drv_remove,\n#ifdef CONFIG_PM\n\t.suspend = msdc_drv_suspend,\n\t.resume  = msdc_drv_resume,\n#endif\n\t.driver  = {\n\t\t.name  = DRV_NAME,\n\t\t.of_match_table = mt7620_sdhci_match,\n\t},\n};\n\n/*--------------------------------------------------------------------------*/\n/* module init/exit                                                      */\n/*--------------------------------------------------------------------------*/\nstatic int __init mt_msdc_init(void)\n{\n\tint ret;\n\n\tret = platform_driver_register(&mt_msdc_driver);\n\tif (ret) {\n\t\tprintk(KERN_ERR DRV_NAME \": Can't register driver\");\n\t\treturn ret;\n\t}\n\n#if defined(MT6575_SD_DEBUG)\n\tmsdc_debug_proc_init();\n#endif\n\treturn 0;\n}\n\nstatic void __exit mt_msdc_exit(void)\n{\n\tplatform_driver_unregister(&mt_msdc_driver);\n}\n\nmodule_init(mt_msdc_init);\nmodule_exit(mt_msdc_exit);\nMODULE_LICENSE(\"GPL\");\nMODULE_DESCRIPTION(\"MediaTek MT6575 SD/MMC Card Driver\");\nMODULE_AUTHOR(\"Infinity Chen <infinity.chen@mediatek.com>\");\n"
  },
  {
    "path": "target/linux/ramips/files/drivers/mtd/nand/raw/mt7621_nand.c",
    "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * MediaTek MT7621 NAND Flash Controller driver\n *\n * Copyright (C) 2020 MediaTek Inc. All Rights Reserved.\n *\n * Author: Weijie Gao <weijie.gao@mediatek.com>\n */\n\n#include <linux/io.h>\n#include <linux/clk.h>\n#include <linux/init.h>\n#include <linux/errno.h>\n#include <linux/sizes.h>\n#include <linux/iopoll.h>\n#include <linux/kernel.h>\n#include <linux/module.h>\n#include <linux/mtd/mtd.h>\n#include <linux/mtd/rawnand.h>\n#include <linux/mtd/partitions.h>\n#include <linux/mtd/mtk_bmt.h>\n#include <linux/platform_device.h>\n#include <asm/addrspace.h>\n\n/* NFI core registers */\n#define NFI_CNFG\t\t\t0x000\n#define   CNFG_OP_MODE_S\t\t12\n#define   CNFG_OP_MODE_M\t\tGENMASK(14, 12)\n#define     CNFG_OP_CUSTOM\t\t6\n#define   CNFG_AUTO_FMT_EN\t\tBIT(9)\n#define   CNFG_HW_ECC_EN\t\tBIT(8)\n#define   CNFG_BYTE_RW\t\t\tBIT(6)\n#define   CNFG_READ_MODE\t\tBIT(1)\n\n#define NFI_PAGEFMT\t\t\t0x004\n#define   PAGEFMT_FDM_ECC_S\t\t12\n#define   PAGEFMT_FDM_ECC_M\t\tGENMASK(15, 12)\n#define   PAGEFMT_FDM_S\t\t\t8\n#define   PAGEFMT_FDM_M\t\t\tGENMASK(11, 8)\n#define   PAGEFMT_SPARE_S\t\t4\n#define   PAGEFMT_SPARE_M\t\tGENMASK(5, 4)\n#define   PAGEFMT_PAGE_S\t\t0\n#define   PAGEFMT_PAGE_M\t\tGENMASK(1, 0)\n\n#define NFI_CON\t\t\t\t0x008\n#define   CON_NFI_SEC_S\t\t\t12\n#define   CON_NFI_SEC_M\t\t\tGENMASK(15, 12)\n#define   CON_NFI_BWR\t\t\tBIT(9)\n#define   CON_NFI_BRD\t\t\tBIT(8)\n#define   CON_NFI_RST\t\t\tBIT(1)\n#define   CON_FIFO_FLUSH\t\tBIT(0)\n\n#define NFI_ACCCON\t\t\t0x00c\n#define   ACCCON_POECS_S\t\t28\n#define   ACCCON_POECS_MAX\t\t0x0f\n#define   ACCCON_POECS_DEF\t\t3\n#define   ACCCON_PRECS_S\t\t22\n#define   ACCCON_PRECS_MAX\t\t0x3f\n#define   ACCCON_PRECS_DEF\t\t3\n#define   ACCCON_C2R_S\t\t\t16\n#define   ACCCON_C2R_MAX\t\t0x3f\n#define   ACCCON_C2R_DEF\t\t7\n#define   ACCCON_W2R_S\t\t\t12\n#define   ACCCON_W2R_MAX\t\t0x0f\n#define   ACCCON_W2R_DEF\t\t7\n#define   ACCCON_WH_S\t\t\t8\n#define   ACCCON_WH_MAX\t\t\t0x0f\n#define   ACCCON_WH_DEF\t\t\t15\n#define   ACCCON_WST_S\t\t\t4\n#define   ACCCON_WST_MAX\t\t0x0f\n#define   ACCCON_WST_DEF\t\t15\n#define   ACCCON_WST_MIN\t\t3\n#define   ACCCON_RLT_S\t\t\t0\n#define   ACCCON_RLT_MAX\t\t0x0f\n#define   ACCCON_RLT_DEF\t\t15\n#define   ACCCON_RLT_MIN\t\t3\n\n#define NFI_CMD\t\t\t\t0x020\n\n#define NFI_ADDRNOB\t\t\t0x030\n#define   ADDR_ROW_NOB_S\t\t4\n#define   ADDR_ROW_NOB_M\t\tGENMASK(6, 4)\n#define   ADDR_COL_NOB_S\t\t0\n#define   ADDR_COL_NOB_M\t\tGENMASK(2, 0)\n\n#define NFI_COLADDR\t\t\t0x034\n#define NFI_ROWADDR\t\t\t0x038\n\n#define NFI_STRDATA\t\t\t0x040\n#define   STR_DATA\t\t\tBIT(0)\n\n#define NFI_CNRNB\t\t\t0x044\n#define   CB2R_TIME_S\t\t\t4\n#define   CB2R_TIME_M\t\t\tGENMASK(7, 4)\n#define   STR_CNRNB\t\t\tBIT(0)\n\n#define NFI_DATAW\t\t\t0x050\n#define NFI_DATAR\t\t\t0x054\n\n#define NFI_PIO_DIRDY\t\t\t0x058\n#define   PIO_DIRDY\t\t\tBIT(0)\n\n#define NFI_STA\t\t\t\t0x060\n#define   STA_NFI_FSM_S\t\t\t16\n#define   STA_NFI_FSM_M\t\t\tGENMASK(19, 16)\n#define     STA_FSM_CUSTOM_DATA\t\t14\n#define   STA_BUSY\t\t\tBIT(8)\n#define   STA_ADDR\t\t\tBIT(1)\n#define   STA_CMD\t\t\tBIT(0)\n\n#define NFI_ADDRCNTR\t\t\t0x070\n#define   SEC_CNTR_S\t\t\t12\n#define   SEC_CNTR_M\t\t\tGENMASK(15, 12)\n#define   SEC_ADDR_S\t\t\t0\n#define   SEC_ADDR_M\t\t\tGENMASK(9, 0)\n\n#define NFI_CSEL\t\t\t0x090\n#define   CSEL_S\t\t\t0\n#define   CSEL_M\t\t\tGENMASK(1, 0)\n\n#define NFI_FDM0L\t\t\t0x0a0\n#define NFI_FDML(n)\t\t\t(0x0a0 + ((n) << 3))\n\n#define NFI_FDM0M\t\t\t0x0a4\n#define NFI_FDMM(n)\t\t\t(0x0a4 + ((n) << 3))\n\n#define NFI_MASTER_STA\t\t\t0x210\n#define   MAS_ADDR\t\t\tGENMASK(11, 9)\n#define   MAS_RD\t\t\tGENMASK(8, 6)\n#define   MAS_WR\t\t\tGENMASK(5, 3)\n#define   MAS_RDDLY\t\t\tGENMASK(2, 0)\n\n/* ECC engine registers */\n#define ECC_ENCCON\t\t\t0x000\n#define   ENC_EN\t\t\tBIT(0)\n\n#define ECC_ENCCNFG\t\t\t0x004\n#define   ENC_CNFG_MSG_S\t\t16\n#define   ENC_CNFG_MSG_M\t\tGENMASK(28, 16)\n#define   ENC_MODE_S\t\t\t4\n#define   ENC_MODE_M\t\t\tGENMASK(5, 4)\n#define     ENC_MODE_NFI\t\t1\n#define   ENC_TNUM_S\t\t\t0\n#define   ENC_TNUM_M\t\t\tGENMASK(2, 0)\n\n#define ECC_ENCIDLE\t\t\t0x00c\n#define   ENC_IDLE\t\t\tBIT(0)\n\n#define ECC_DECCON\t\t\t0x100\n#define   DEC_EN\t\t\tBIT(0)\n\n#define ECC_DECCNFG\t\t\t0x104\n#define   DEC_EMPTY_EN\t\t\tBIT(31)\n#define   DEC_CS_S\t\t\t16\n#define   DEC_CS_M\t\t\tGENMASK(28, 16)\n#define   DEC_CON_S\t\t\t12\n#define   DEC_CON_M\t\t\tGENMASK(13, 12)\n#define     DEC_CON_EL\t\t\t2\n#define   DEC_MODE_S\t\t\t4\n#define   DEC_MODE_M\t\t\tGENMASK(5, 4)\n#define     DEC_MODE_NFI\t\t1\n#define   DEC_TNUM_S\t\t\t0\n#define   DEC_TNUM_M\t\t\tGENMASK(2, 0)\n\n#define ECC_DECIDLE\t\t\t0x10c\n#define   DEC_IDLE\t\t\tBIT(1)\n\n#define ECC_DECENUM\t\t\t0x114\n#define   ERRNUM_S\t\t\t2\n#define   ERRNUM_M\t\t\tGENMASK(3, 0)\n\n#define ECC_DECDONE\t\t\t0x118\n#define   DEC_DONE7\t\t\tBIT(7)\n#define   DEC_DONE6\t\t\tBIT(6)\n#define   DEC_DONE5\t\t\tBIT(5)\n#define   DEC_DONE4\t\t\tBIT(4)\n#define   DEC_DONE3\t\t\tBIT(3)\n#define   DEC_DONE2\t\t\tBIT(2)\n#define   DEC_DONE1\t\t\tBIT(1)\n#define   DEC_DONE0\t\t\tBIT(0)\n\n#define ECC_DECEL(n)\t\t\t(0x11c + (n) * 4)\n#define   DEC_EL_ODD_S\t\t\t16\n#define   DEC_EL_EVEN_S\t\t\t0\n#define   DEC_EL_M\t\t\t0x1fff\n#define   DEC_EL_BYTE_POS_S\t\t3\n#define   DEC_EL_BIT_POS_M\t\tGENMASK(2, 0)\n\n#define ECC_FDMADDR\t\t\t0x13c\n\n/* ENCIDLE and DECIDLE */\n#define   ECC_IDLE\t\t\tBIT(0)\n\n#define ACCTIMING(tpoecs, tprecs, tc2r, tw2r, twh, twst, trlt) \\\n\t((tpoecs) << ACCCON_POECS_S | (tprecs) << ACCCON_PRECS_S | \\\n\t(tc2r) << ACCCON_C2R_S | (tw2r) << ACCCON_W2R_S | \\\n\t(twh) << ACCCON_WH_S | (twst) << ACCCON_WST_S | (trlt))\n\n#define MASTER_STA_MASK\t\t\t(MAS_ADDR | MAS_RD | MAS_WR | \\\n\t\t\t\t\t MAS_RDDLY)\n#define NFI_RESET_TIMEOUT\t\t1000000\n#define NFI_CORE_TIMEOUT\t\t500000\n#define ECC_ENGINE_TIMEOUT\t\t500000\n\n#define ECC_SECTOR_SIZE\t\t\t512\n#define ECC_PARITY_BITS\t\t\t13\n\n#define NFI_FDM_SIZE\t\t8\n\n#define MT7621_NFC_NAME\t\t\t\"mt7621-nand\"\n\nstruct mt7621_nfc {\n\tstruct nand_controller controller;\n\tstruct nand_chip nand;\n\tstruct clk *nfi_clk;\n\tstruct device *dev;\n\n\tu32 nfi_base;\n\tvoid __iomem *nfi_regs;\n\tvoid __iomem *ecc_regs;\n\n\tu32 spare_per_sector;\n};\n\nstatic const u16 mt7621_nfi_page_size[] = { SZ_512, SZ_2K, SZ_4K };\nstatic const u8 mt7621_nfi_spare_size[] = { 16, 26, 27, 28 };\nstatic const u8 mt7621_ecc_strength[] = { 4, 6, 8, 10, 12 };\n\nstatic inline u32 nfi_read32(struct mt7621_nfc *nfc, u32 reg)\n{\n\treturn readl(nfc->nfi_regs + reg);\n}\n\nstatic inline void nfi_write32(struct mt7621_nfc *nfc, u32 reg, u32 val)\n{\n\twritel(val, nfc->nfi_regs + reg);\n}\n\nstatic inline u16 nfi_read16(struct mt7621_nfc *nfc, u32 reg)\n{\n\treturn readw(nfc->nfi_regs + reg);\n}\n\nstatic inline void nfi_write16(struct mt7621_nfc *nfc, u32 reg, u16 val)\n{\n\twritew(val, nfc->nfi_regs + reg);\n}\n\nstatic inline void ecc_write16(struct mt7621_nfc *nfc, u32 reg, u16 val)\n{\n\twritew(val, nfc->ecc_regs + reg);\n}\n\nstatic inline u32 ecc_read32(struct mt7621_nfc *nfc, u32 reg)\n{\n\treturn readl(nfc->ecc_regs + reg);\n}\n\nstatic inline void ecc_write32(struct mt7621_nfc *nfc, u32 reg, u32 val)\n{\n\treturn writel(val, nfc->ecc_regs + reg);\n}\n\nstatic inline u8 *oob_fdm_ptr(struct nand_chip *nand, int sect)\n{\n\treturn nand->oob_poi + sect * NFI_FDM_SIZE;\n}\n\nstatic inline u8 *oob_ecc_ptr(struct mt7621_nfc *nfc, int sect)\n{\n\tstruct nand_chip *nand = &nfc->nand;\n\n\treturn nand->oob_poi + nand->ecc.steps * NFI_FDM_SIZE +\n\t\tsect * (nfc->spare_per_sector - NFI_FDM_SIZE);\n}\n\nstatic inline u8 *page_data_ptr(struct nand_chip *nand, const u8 *buf,\n\t\t\t\tint sect)\n{\n\treturn (u8 *)buf + sect * nand->ecc.size;\n}\n\nstatic int mt7621_ecc_wait_idle(struct mt7621_nfc *nfc, u32 reg)\n{\n\tstruct device *dev = nfc->dev;\n\tu32 val;\n\tint ret;\n\n\tret = readw_poll_timeout_atomic(nfc->ecc_regs + reg, val,\n\t\t\t\t\tval & ECC_IDLE, 10,\n\t\t\t\t\tECC_ENGINE_TIMEOUT);\n\tif (ret) {\n\t\tdev_warn(dev, \"ECC engine timed out entering idle mode\\n\");\n\t\treturn -EIO;\n\t}\n\n\treturn 0;\n}\n\nstatic int mt7621_ecc_decoder_wait_done(struct mt7621_nfc *nfc, u32 sect)\n{\n\tstruct device *dev = nfc->dev;\n\tu32 val;\n\tint ret;\n\n\tret = readw_poll_timeout_atomic(nfc->ecc_regs + ECC_DECDONE, val,\n\t\t\t\t\tval & (1 << sect), 10,\n\t\t\t\t\tECC_ENGINE_TIMEOUT);\n\n\tif (ret) {\n\t\tdev_warn(dev, \"ECC decoder for sector %d timed out\\n\",\n\t\t\t sect);\n\t\treturn -ETIMEDOUT;\n\t}\n\n\treturn 0;\n}\n\nstatic void mt7621_ecc_encoder_op(struct mt7621_nfc *nfc, bool enable)\n{\n\tmt7621_ecc_wait_idle(nfc, ECC_ENCIDLE);\n\tecc_write16(nfc, ECC_ENCCON, enable ? ENC_EN : 0);\n}\n\nstatic void mt7621_ecc_decoder_op(struct mt7621_nfc *nfc, bool enable)\n{\n\tmt7621_ecc_wait_idle(nfc, ECC_DECIDLE);\n\tecc_write16(nfc, ECC_DECCON, enable ? DEC_EN : 0);\n}\n\nstatic int mt7621_ecc_correct_check(struct mt7621_nfc *nfc, u8 *sector_buf,\n\t\t\t\t   u8 *fdm_buf, u32 sect)\n{\n\tstruct nand_chip *nand = &nfc->nand;\n\tu32 decnum, num_error_bits, fdm_end_bits;\n\tu32 error_locations, error_bit_loc;\n\tu32 error_byte_pos, error_bit_pos;\n\tint bitflips = 0;\n\tu32 i;\n\n\tdecnum = ecc_read32(nfc, ECC_DECENUM);\n\tnum_error_bits = (decnum >> (sect << ERRNUM_S)) & ERRNUM_M;\n\tfdm_end_bits = (nand->ecc.size + NFI_FDM_SIZE) << 3;\n\n\tif (!num_error_bits)\n\t\treturn 0;\n\n\tif (num_error_bits == ERRNUM_M)\n\t\treturn -1;\n\n\tfor (i = 0; i < num_error_bits; i++) {\n\t\terror_locations = ecc_read32(nfc, ECC_DECEL(i / 2));\n\t\terror_bit_loc = (error_locations >> ((i % 2) * DEC_EL_ODD_S)) &\n\t\t\t\tDEC_EL_M;\n\t\terror_byte_pos = error_bit_loc >> DEC_EL_BYTE_POS_S;\n\t\terror_bit_pos = error_bit_loc & DEC_EL_BIT_POS_M;\n\n\t\tif (error_bit_loc < (nand->ecc.size << 3)) {\n\t\t\tif (sector_buf) {\n\t\t\t\tsector_buf[error_byte_pos] ^=\n\t\t\t\t\t(1 << error_bit_pos);\n\t\t\t}\n\t\t} else if (error_bit_loc < fdm_end_bits) {\n\t\t\tif (fdm_buf) {\n\t\t\t\tfdm_buf[error_byte_pos - nand->ecc.size] ^=\n\t\t\t\t\t(1 << error_bit_pos);\n\t\t\t}\n\t\t}\n\n\t\tbitflips++;\n\t}\n\n\treturn bitflips;\n}\n\nstatic int mt7621_nfc_wait_write_completion(struct mt7621_nfc *nfc,\n\t\t\t\t\t    struct nand_chip *nand)\n{\n\tstruct device *dev = nfc->dev;\n\tu16 val;\n\tint ret;\n\n\tret = readw_poll_timeout_atomic(nfc->nfi_regs + NFI_ADDRCNTR, val,\n\t\t((val & SEC_CNTR_M) >> SEC_CNTR_S) >= nand->ecc.steps, 10,\n\t\tNFI_CORE_TIMEOUT);\n\n\tif (ret) {\n\t\tdev_warn(dev, \"NFI core write operation timed out\\n\");\n\t\treturn -ETIMEDOUT;\n\t}\n\n\treturn ret;\n}\n\nstatic void mt7621_nfc_hw_reset(struct mt7621_nfc *nfc)\n{\n\tu32 val;\n\tint ret;\n\n\t/* reset all registers and force the NFI master to terminate */\n\tnfi_write16(nfc, NFI_CON, CON_FIFO_FLUSH | CON_NFI_RST);\n\n\t/* wait for the master to finish the last transaction */\n\tret = readw_poll_timeout(nfc->nfi_regs + NFI_MASTER_STA, val,\n\t\t\t\t !(val & MASTER_STA_MASK), 50,\n\t\t\t\t NFI_RESET_TIMEOUT);\n\tif (ret) {\n\t\tdev_warn(nfc->dev, \"Failed to reset NFI master in %dms\\n\",\n\t\t\t NFI_RESET_TIMEOUT);\n\t}\n\n\t/* ensure any status register affected by the NFI master is reset */\n\tnfi_write16(nfc, NFI_CON, CON_FIFO_FLUSH | CON_NFI_RST);\n\tnfi_write16(nfc, NFI_STRDATA, 0);\n}\n\nstatic inline void mt7621_nfc_hw_init(struct mt7621_nfc *nfc)\n{\n\tu32 acccon;\n\n\t/*\n\t * CNRNB: nand ready/busy register\n\t * -------------------------------\n\t * 7:4: timeout register for polling the NAND busy/ready signal\n\t * 0  : poll the status of the busy/ready signal after [7:4]*16 cycles.\n\t */\n\tnfi_write16(nfc, NFI_CNRNB, CB2R_TIME_M | STR_CNRNB);\n\n\tmt7621_nfc_hw_reset(nfc);\n\n\t/* Apply default access timing */\n\tacccon = ACCTIMING(ACCCON_POECS_DEF, ACCCON_PRECS_DEF, ACCCON_C2R_DEF,\n\t\t\t   ACCCON_W2R_DEF, ACCCON_WH_DEF, ACCCON_WST_DEF,\n\t\t\t   ACCCON_RLT_DEF);\n\n\tnfi_write32(nfc, NFI_ACCCON, acccon);\n}\n\nstatic int mt7621_nfc_send_command(struct mt7621_nfc *nfc, u8 command)\n{\n\tstruct device *dev = nfc->dev;\n\tu32 val;\n\tint ret;\n\n\tnfi_write32(nfc, NFI_CMD, command);\n\n\tret = readl_poll_timeout_atomic(nfc->nfi_regs + NFI_STA, val,\n\t\t\t\t\t!(val & STA_CMD), 10,\n\t\t\t\t\tNFI_CORE_TIMEOUT);\n\tif (ret) {\n\t\tdev_warn(dev, \"NFI core timed out entering command mode\\n\");\n\t\treturn -EIO;\n\t}\n\n\treturn 0;\n}\n\nstatic int mt7621_nfc_send_address_byte(struct mt7621_nfc *nfc, int addr)\n{\n\tstruct device *dev = nfc->dev;\n\tu32 val;\n\tint ret;\n\n\tnfi_write32(nfc, NFI_COLADDR, addr);\n\tnfi_write32(nfc, NFI_ROWADDR, 0);\n\tnfi_write16(nfc, NFI_ADDRNOB, 1);\n\n\tret = readl_poll_timeout_atomic(nfc->nfi_regs + NFI_STA, val,\n\t\t\t\t\t!(val & STA_ADDR), 10,\n\t\t\t\t\tNFI_CORE_TIMEOUT);\n\tif (ret) {\n\t\tdev_warn(dev, \"NFI core timed out entering address mode\\n\");\n\t\treturn -EIO;\n\t}\n\n\treturn 0;\n}\n\nstatic int mt7621_nfc_send_address(struct mt7621_nfc *nfc, const u8 *addr,\n\t\t\t\t   unsigned int naddrs)\n{\n\tint ret;\n\n\twhile (naddrs) {\n\t\tret = mt7621_nfc_send_address_byte(nfc, *addr);\n\t\tif (ret)\n\t\t\treturn ret;\n\n\t\taddr++;\n\t\tnaddrs--;\n\t}\n\n\treturn 0;\n}\n\nstatic void mt7621_nfc_wait_pio_ready(struct mt7621_nfc *nfc)\n{\n\tstruct device *dev = nfc->dev;\n\tint ret;\n\tu16 val;\n\n\tret = readw_poll_timeout_atomic(nfc->nfi_regs + NFI_PIO_DIRDY, val,\n\t\t\t\t\tval & PIO_DIRDY, 10,\n\t\t\t\t\tNFI_CORE_TIMEOUT);\n\tif (ret < 0)\n\t\tdev_err(dev, \"NFI core PIO mode not ready\\n\");\n}\n\nstatic u32 mt7621_nfc_pio_read(struct mt7621_nfc *nfc, bool br)\n{\n\tu32 reg;\n\n\t/* after each byte read, the NFI_STA reg is reset by the hardware */\n\treg = (nfi_read32(nfc, NFI_STA) & STA_NFI_FSM_M) >> STA_NFI_FSM_S;\n\tif (reg != STA_FSM_CUSTOM_DATA) {\n\t\treg = nfi_read16(nfc, NFI_CNFG);\n\t\treg |= CNFG_READ_MODE | CNFG_BYTE_RW;\n\t\tif (!br)\n\t\t\treg &= ~CNFG_BYTE_RW;\n\t\tnfi_write16(nfc, NFI_CNFG, reg);\n\n\t\t/*\n\t\t * set to max sector to allow the HW to continue reading over\n\t\t * unaligned accesses\n\t\t */\n\t\tnfi_write16(nfc, NFI_CON, CON_NFI_SEC_M | CON_NFI_BRD);\n\n\t\t/* trigger to fetch data */\n\t\tnfi_write16(nfc, NFI_STRDATA, STR_DATA);\n\t}\n\n\tmt7621_nfc_wait_pio_ready(nfc);\n\n\treturn nfi_read32(nfc, NFI_DATAR);\n}\n\nstatic void mt7621_nfc_read_data(struct mt7621_nfc *nfc, u8 *buf, u32 len)\n{\n\twhile (((uintptr_t)buf & 3) && len) {\n\t\t*buf = mt7621_nfc_pio_read(nfc, true);\n\t\tbuf++;\n\t\tlen--;\n\t}\n\n\twhile (len >= 4) {\n\t\t*(u32 *)buf = mt7621_nfc_pio_read(nfc, false);\n\t\tbuf += 4;\n\t\tlen -= 4;\n\t}\n\n\twhile (len) {\n\t\t*buf = mt7621_nfc_pio_read(nfc, true);\n\t\tbuf++;\n\t\tlen--;\n\t}\n}\n\nstatic void mt7621_nfc_read_data_discard(struct mt7621_nfc *nfc, u32 len)\n{\n\twhile (len >= 4) {\n\t\tmt7621_nfc_pio_read(nfc, false);\n\t\tlen -= 4;\n\t}\n\n\twhile (len) {\n\t\tmt7621_nfc_pio_read(nfc, true);\n\t\tlen--;\n\t}\n}\n\nstatic void mt7621_nfc_pio_write(struct mt7621_nfc *nfc, u32 val, bool bw)\n{\n\tu32 reg;\n\n\treg = (nfi_read32(nfc, NFI_STA) & STA_NFI_FSM_M) >> STA_NFI_FSM_S;\n\tif (reg != STA_FSM_CUSTOM_DATA) {\n\t\treg = nfi_read16(nfc, NFI_CNFG);\n\t\treg &= ~(CNFG_READ_MODE | CNFG_BYTE_RW);\n\t\tif (bw)\n\t\t\treg |= CNFG_BYTE_RW;\n\t\tnfi_write16(nfc, NFI_CNFG, reg);\n\n\t\tnfi_write16(nfc, NFI_CON, CON_NFI_SEC_M | CON_NFI_BWR);\n\t\tnfi_write16(nfc, NFI_STRDATA, STR_DATA);\n\t}\n\n\tmt7621_nfc_wait_pio_ready(nfc);\n\tnfi_write32(nfc, NFI_DATAW, val);\n}\n\nstatic void mt7621_nfc_write_data(struct mt7621_nfc *nfc, const u8 *buf,\n\t\t\t\t  u32 len)\n{\n\twhile (((uintptr_t)buf & 3) && len) {\n\t\tmt7621_nfc_pio_write(nfc, *buf, true);\n\t\tbuf++;\n\t\tlen--;\n\t}\n\n\twhile (len >= 4) {\n\t\tmt7621_nfc_pio_write(nfc, *(const u32 *)buf, false);\n\t\tbuf += 4;\n\t\tlen -= 4;\n\t}\n\n\twhile (len) {\n\t\tmt7621_nfc_pio_write(nfc, *buf, true);\n\t\tbuf++;\n\t\tlen--;\n\t}\n}\n\nstatic void mt7621_nfc_write_data_empty(struct mt7621_nfc *nfc, u32 len)\n{\n\twhile (len >= 4) {\n\t\tmt7621_nfc_pio_write(nfc, 0xffffffff, false);\n\t\tlen -= 4;\n\t}\n\n\twhile (len) {\n\t\tmt7621_nfc_pio_write(nfc, 0xff, true);\n\t\tlen--;\n\t}\n}\n\nstatic int mt7621_nfc_dev_ready(struct mt7621_nfc *nfc,\n\t\t\t\tunsigned int timeout_ms)\n{\n\tu32 val;\n\n\treturn readl_poll_timeout_atomic(nfc->nfi_regs + NFI_STA, val,\n\t\t\t\t\t !(val & STA_BUSY), 10,\n\t\t\t\t\t timeout_ms * 1000);\n}\n\nstatic int mt7621_nfc_exec_instr(struct nand_chip *nand,\n\t\t\t\t const struct nand_op_instr *instr)\n{\n\tstruct mt7621_nfc *nfc = nand_get_controller_data(nand);\n\n\tswitch (instr->type) {\n\tcase NAND_OP_CMD_INSTR:\n\t\tmt7621_nfc_hw_reset(nfc);\n\t\tnfi_write16(nfc, NFI_CNFG, CNFG_OP_CUSTOM << CNFG_OP_MODE_S);\n\t\treturn mt7621_nfc_send_command(nfc, instr->ctx.cmd.opcode);\n\tcase NAND_OP_ADDR_INSTR:\n\t\treturn mt7621_nfc_send_address(nfc, instr->ctx.addr.addrs,\n\t\t\t\t\t       instr->ctx.addr.naddrs);\n\tcase NAND_OP_DATA_IN_INSTR:\n\t\tmt7621_nfc_read_data(nfc, instr->ctx.data.buf.in,\n\t\t\t\t     instr->ctx.data.len);\n\t\treturn 0;\n\tcase NAND_OP_DATA_OUT_INSTR:\n\t\tmt7621_nfc_write_data(nfc, instr->ctx.data.buf.out,\n\t\t\t\t      instr->ctx.data.len);\n\t\treturn 0;\n\tcase NAND_OP_WAITRDY_INSTR:\n\t\treturn mt7621_nfc_dev_ready(nfc,\n\t\t\t\t\t    instr->ctx.waitrdy.timeout_ms);\n\tdefault:\n\t\tWARN_ONCE(1, \"unsupported NAND instruction type: %d\\n\",\n\t\t\t  instr->type);\n\n\t\treturn -EINVAL;\n\t}\n}\n\nstatic int mt7621_nfc_exec_op(struct nand_chip *nand,\n\t\t\t      const struct nand_operation *op, bool check_only)\n{\n\tstruct mt7621_nfc *nfc = nand_get_controller_data(nand);\n\tint i, ret;\n\n\tif (check_only)\n\t\treturn 0;\n\n\t/* Only CS0 available */\n\tnfi_write16(nfc, NFI_CSEL, 0);\n\n\tfor (i = 0; i < op->ninstrs; i++) {\n\t\tret = mt7621_nfc_exec_instr(nand, &op->instrs[i]);\n\t\tif (ret)\n\t\t\treturn ret;\n\t}\n\n\treturn 0;\n}\n\nstatic int mt7621_nfc_setup_interface(struct nand_chip *nand, int csline,\n\t\t\t\t      const struct nand_interface_config *conf)\n{\n\tstruct mt7621_nfc *nfc = nand_get_controller_data(nand);\n\tconst struct nand_sdr_timings *timings;\n\tu32 acccon, temp, rate, tpoecs, tprecs, tc2r, tw2r, twh, twst, trlt;\n\n\tif (!nfc->nfi_clk)\n\t\treturn -ENOTSUPP;\n\n\ttimings = nand_get_sdr_timings(conf);\n\tif (IS_ERR(timings))\n\t\treturn -ENOTSUPP;\n\n\trate = clk_get_rate(nfc->nfi_clk);\n\n\t/* turn clock rate into KHZ */\n\trate /= 1000;\n\n\ttpoecs = max(timings->tALH_min, timings->tCLH_min) / 1000;\n\ttpoecs = DIV_ROUND_UP(tpoecs * rate, 1000000);\n\ttpoecs = min_t(u32, tpoecs, ACCCON_POECS_MAX);\n\n\ttprecs = max(timings->tCLS_min, timings->tALS_min) / 1000;\n\ttprecs = DIV_ROUND_UP(tprecs * rate, 1000000);\n\ttprecs = min_t(u32, tprecs, ACCCON_PRECS_MAX);\n\n\t/* sdr interface has no tCR which means CE# low to RE# low */\n\ttc2r = 0;\n\n\ttw2r = timings->tWHR_min / 1000;\n\ttw2r = DIV_ROUND_UP(tw2r * rate, 1000000);\n\ttw2r = DIV_ROUND_UP(tw2r - 1, 2);\n\ttw2r = min_t(u32, tw2r, ACCCON_W2R_MAX);\n\n\ttwh = max(timings->tREH_min, timings->tWH_min) / 1000;\n\ttwh = DIV_ROUND_UP(twh * rate, 1000000) - 1;\n\ttwh = min_t(u32, twh, ACCCON_WH_MAX);\n\n\t/* Calculate real WE#/RE# hold time in nanosecond */\n\ttemp = (twh + 1) * 1000000 / rate;\n\t/* nanosecond to picosecond */\n\ttemp *= 1000;\n\n\t/*\n\t * WE# low level time should be expaned to meet WE# pulse time\n\t * and WE# cycle time at the same time.\n\t */\n\tif (temp < timings->tWC_min)\n\t\ttwst = timings->tWC_min - temp;\n\telse\n\t\ttwst = 0;\n\ttwst = max(timings->tWP_min, twst) / 1000;\n\ttwst = DIV_ROUND_UP(twst * rate, 1000000) - 1;\n\ttwst = min_t(u32, twst, ACCCON_WST_MAX);\n\n\t/*\n\t * RE# low level time should be expaned to meet RE# pulse time\n\t * and RE# cycle time at the same time.\n\t */\n\tif (temp < timings->tRC_min)\n\t\ttrlt = timings->tRC_min - temp;\n\telse\n\t\ttrlt = 0;\n\ttrlt = max(trlt, timings->tRP_min) / 1000;\n\ttrlt = DIV_ROUND_UP(trlt * rate, 1000000) - 1;\n\ttrlt = min_t(u32, trlt, ACCCON_RLT_MAX);\n\n\tif (csline == NAND_DATA_IFACE_CHECK_ONLY) {\n\t\tif (twst < ACCCON_WST_MIN || trlt < ACCCON_RLT_MIN)\n\t\t\treturn -ENOTSUPP;\n\t}\n\n\tacccon = ACCTIMING(tpoecs, tprecs, tc2r, tw2r, twh, twst, trlt);\n\n\tdev_dbg(nfc->dev, \"Using programmed access timing: %08x\\n\", acccon);\n\n\tnfi_write32(nfc, NFI_ACCCON, acccon);\n\n\treturn 0;\n}\n\nstatic int mt7621_nfc_calc_ecc_strength(struct mt7621_nfc *nfc,\n\t\t\t\t\tu32 avail_ecc_bytes)\n{\n\tstruct nand_chip *nand = &nfc->nand;\n\tstruct mtd_info *mtd = nand_to_mtd(nand);\n\tu32 strength;\n\tint i;\n\n\tstrength = avail_ecc_bytes * 8 / ECC_PARITY_BITS;\n\n\t/* Find the closest supported ecc strength */\n\tfor (i = ARRAY_SIZE(mt7621_ecc_strength) - 1; i >= 0; i--) {\n\t\tif (mt7621_ecc_strength[i] <= strength)\n\t\t\tbreak;\n\t}\n\n\tif (unlikely(i < 0)) {\n\t\tdev_err(nfc->dev, \"OOB size (%u) is not supported\\n\",\n\t\t\tmtd->oobsize);\n\t\treturn -EINVAL;\n\t}\n\n\tnand->ecc.strength = mt7621_ecc_strength[i];\n\tnand->ecc.bytes =\n\t\tDIV_ROUND_UP(nand->ecc.strength * ECC_PARITY_BITS, 8);\n\n\tdev_info(nfc->dev, \"ECC strength adjusted to %u bits\\n\",\n\t\t nand->ecc.strength);\n\n\treturn i;\n}\n\nstatic int mt7621_nfc_set_spare_per_sector(struct mt7621_nfc *nfc)\n{\n\tstruct nand_chip *nand = &nfc->nand;\n\tstruct mtd_info *mtd = nand_to_mtd(nand);\n\tu32 size;\n\tint i;\n\n\tsize = nand->ecc.bytes + NFI_FDM_SIZE;\n\n\t/* Find the closest supported spare size */\n\tfor (i = 0; i < ARRAY_SIZE(mt7621_nfi_spare_size); i++) {\n\t\tif (mt7621_nfi_spare_size[i] >= size)\n\t\t\tbreak;\n\t}\n\n\tif (unlikely(i >= ARRAY_SIZE(mt7621_nfi_spare_size))) {\n\t\tdev_err(nfc->dev, \"OOB size (%u) is not supported\\n\",\n\t\t\tmtd->oobsize);\n\t\treturn -EINVAL;\n\t}\n\n\tnfc->spare_per_sector = mt7621_nfi_spare_size[i];\n\n\treturn i;\n}\n\nstatic int mt7621_nfc_ecc_init(struct mt7621_nfc *nfc)\n{\n\tstruct nand_chip *nand = &nfc->nand;\n\tstruct mtd_info *mtd = nand_to_mtd(nand);\n\tu32 spare_per_sector, encode_block_size, decode_block_size;\n\tu32 ecc_enccfg, ecc_deccfg;\n\tint ecc_cap;\n\n\t/* Only hardware ECC mode is supported */\n\tif (nand->ecc.engine_type != NAND_ECC_ENGINE_TYPE_ON_HOST) {\n\t\tdev_err(nfc->dev, \"Only hardware ECC mode is supported\\n\");\n\t\treturn -EINVAL;\n\t}\n\n\tnand->ecc.size = ECC_SECTOR_SIZE;\n\tnand->ecc.steps = mtd->writesize / nand->ecc.size;\n\n\tspare_per_sector = mtd->oobsize / nand->ecc.steps;\n\n\tecc_cap = mt7621_nfc_calc_ecc_strength(nfc,\n\t\tspare_per_sector - NFI_FDM_SIZE);\n\tif (ecc_cap < 0)\n\t\treturn ecc_cap;\n\n\t/* Sector + FDM */\n\tencode_block_size = (nand->ecc.size + NFI_FDM_SIZE) * 8;\n\tecc_enccfg = ecc_cap | (ENC_MODE_NFI << ENC_MODE_S) |\n\t\t     (encode_block_size << ENC_CNFG_MSG_S);\n\n\t/* Sector + FDM + ECC parity bits */\n\tdecode_block_size = ((nand->ecc.size + NFI_FDM_SIZE) * 8) +\n\t\t\t    nand->ecc.strength * ECC_PARITY_BITS;\n\tecc_deccfg = ecc_cap | (DEC_MODE_NFI << DEC_MODE_S) |\n\t\t     (decode_block_size << DEC_CS_S) |\n\t\t     (DEC_CON_EL << DEC_CON_S) | DEC_EMPTY_EN;\n\n\tecc_write32(nfc, ECC_FDMADDR, nfc->nfi_base + NFI_FDML(0));\n\n\tmt7621_ecc_encoder_op(nfc, false);\n\tecc_write32(nfc, ECC_ENCCNFG, ecc_enccfg);\n\n\tmt7621_ecc_decoder_op(nfc, false);\n\tecc_write32(nfc, ECC_DECCNFG, ecc_deccfg);\n\n\treturn 0;\n}\n\nstatic int mt7621_nfc_set_page_format(struct mt7621_nfc *nfc)\n{\n\tstruct nand_chip *nand = &nfc->nand;\n\tstruct mtd_info *mtd = nand_to_mtd(nand);\n\tint i, spare_size;\n\tu32 pagefmt;\n\n\tspare_size = mt7621_nfc_set_spare_per_sector(nfc);\n\tif (spare_size < 0)\n\t\treturn spare_size;\n\n\tfor (i = 0; i < ARRAY_SIZE(mt7621_nfi_page_size); i++) {\n\t\tif (mt7621_nfi_page_size[i] == mtd->writesize)\n\t\t\tbreak;\n\t}\n\n\tif (unlikely(i >= ARRAY_SIZE(mt7621_nfi_page_size))) {\n\t\tdev_err(nfc->dev, \"Page size (%u) is not supported\\n\",\n\t\t\tmtd->writesize);\n\t\treturn -EINVAL;\n\t}\n\n\tpagefmt = i | (spare_size << PAGEFMT_SPARE_S) |\n\t\t  (NFI_FDM_SIZE << PAGEFMT_FDM_S) |\n\t\t  (NFI_FDM_SIZE << PAGEFMT_FDM_ECC_S);\n\n\tnfi_write16(nfc, NFI_PAGEFMT, pagefmt);\n\n\treturn 0;\n}\n\nstatic int mt7621_nfc_attach_chip(struct nand_chip *nand)\n{\n\tstruct mt7621_nfc *nfc = nand_get_controller_data(nand);\n\tint ret;\n\n\tif (nand->options & NAND_BUSWIDTH_16) {\n\t\tdev_err(nfc->dev, \"16-bit buswidth is not supported\");\n\t\treturn -EINVAL;\n\t}\n\n\tret = mt7621_nfc_ecc_init(nfc);\n\tif (ret)\n\t\treturn ret;\n\n\treturn mt7621_nfc_set_page_format(nfc);\n}\n\nstatic const struct nand_controller_ops mt7621_nfc_controller_ops = {\n\t.attach_chip = mt7621_nfc_attach_chip,\n\t.exec_op = mt7621_nfc_exec_op,\n\t.setup_interface = mt7621_nfc_setup_interface,\n};\n\nstatic int mt7621_nfc_ooblayout_free(struct mtd_info *mtd, int section,\n\t\t\t\t     struct mtd_oob_region *oob_region)\n{\n\tstruct nand_chip *nand = mtd_to_nand(mtd);\n\n\tif (section >= nand->ecc.steps)\n\t\treturn -ERANGE;\n\n\toob_region->length = NFI_FDM_SIZE - 1;\n\toob_region->offset = section * NFI_FDM_SIZE + 1;\n\n\treturn 0;\n}\n\nstatic int mt7621_nfc_ooblayout_ecc(struct mtd_info *mtd, int section,\n\t\t\t\t    struct mtd_oob_region *oob_region)\n{\n\tstruct nand_chip *nand = mtd_to_nand(mtd);\n\n\tif (section)\n\t\treturn -ERANGE;\n\n\toob_region->offset = NFI_FDM_SIZE * nand->ecc.steps;\n\toob_region->length = mtd->oobsize - oob_region->offset;\n\n\treturn 0;\n}\n\nstatic const struct mtd_ooblayout_ops mt7621_nfc_ooblayout_ops = {\n\t.free = mt7621_nfc_ooblayout_free,\n\t.ecc = mt7621_nfc_ooblayout_ecc,\n};\n\nstatic void mt7621_nfc_write_fdm(struct mt7621_nfc *nfc)\n{\n\tstruct nand_chip *nand = &nfc->nand;\n\tu32 vall, valm;\n\tu8 *oobptr;\n\tint i, j;\n\n\tfor (i = 0; i < nand->ecc.steps; i++) {\n\t\tvall = 0;\n\t\tvalm = 0;\n\t\toobptr = oob_fdm_ptr(nand, i);\n\n\t\tfor (j = 0; j < 4; j++)\n\t\t\tvall |= (u32)oobptr[j] << (j * 8);\n\n\t\tfor (j = 0; j < 4; j++)\n\t\t\tvalm |= (u32)oobptr[j + 4] << (j * 8);\n\n\t\tnfi_write32(nfc, NFI_FDML(i), vall);\n\t\tnfi_write32(nfc, NFI_FDMM(i), valm);\n\t}\n}\n\nstatic void mt7621_nfc_read_sector_fdm(struct mt7621_nfc *nfc, u32 sect)\n{\n\tstruct nand_chip *nand = &nfc->nand;\n\tu32 vall, valm;\n\tu8 *oobptr;\n\tint i;\n\n\tvall = nfi_read32(nfc, NFI_FDML(sect));\n\tvalm = nfi_read32(nfc, NFI_FDMM(sect));\n\toobptr = oob_fdm_ptr(nand, sect);\n\n\tfor (i = 0; i < 4; i++)\n\t\toobptr[i] = (vall >> (i * 8)) & 0xff;\n\n\tfor (i = 0; i < 4; i++)\n\t\toobptr[i + 4] = (valm >> (i * 8)) & 0xff;\n}\n\nstatic int mt7621_nfc_read_page_hwecc(struct nand_chip *nand, uint8_t *buf,\n\t\t\t\t      int oob_required, int page)\n{\n\tstruct mt7621_nfc *nfc = nand_get_controller_data(nand);\n\tstruct mtd_info *mtd = nand_to_mtd(nand);\n\tint bitflips = 0;\n\tint rc, i;\n\n\tnand_read_page_op(nand, page, 0, NULL, 0);\n\n\tnfi_write16(nfc, NFI_CNFG, (CNFG_OP_CUSTOM << CNFG_OP_MODE_S) |\n\t\t    CNFG_READ_MODE | CNFG_AUTO_FMT_EN | CNFG_HW_ECC_EN);\n\n\tmt7621_ecc_decoder_op(nfc, true);\n\n\tnfi_write16(nfc, NFI_CON,\n\t\t    CON_NFI_BRD | (nand->ecc.steps << CON_NFI_SEC_S));\n\n\tfor (i = 0; i < nand->ecc.steps; i++) {\n\t\tif (buf)\n\t\t\tmt7621_nfc_read_data(nfc, page_data_ptr(nand, buf, i),\n\t\t\t\t\t     nand->ecc.size);\n\t\telse\n\t\t\tmt7621_nfc_read_data_discard(nfc, nand->ecc.size);\n\n\t\trc = mt7621_ecc_decoder_wait_done(nfc, i);\n\n\t\tmt7621_nfc_read_sector_fdm(nfc, i);\n\n\t\tif (rc < 0) {\n\t\t\tbitflips = -EIO;\n\t\t\tcontinue;\n\t\t}\n\n\t\trc = mt7621_ecc_correct_check(nfc,\n\t\t\tbuf ? page_data_ptr(nand, buf, i) : NULL,\n\t\t\toob_fdm_ptr(nand, i), i);\n\n\t\tif (rc < 0) {\n\t\t\tdev_dbg(nfc->dev,\n\t\t\t\t \"Uncorrectable ECC error at page %d.%d\\n\",\n\t\t\t\t page, i);\n\t\t\tbitflips = -EBADMSG;\n\t\t\tmtd->ecc_stats.failed++;\n\t\t} else if (bitflips >= 0) {\n\t\t\tbitflips += rc;\n\t\t\tmtd->ecc_stats.corrected += rc;\n\t\t}\n\t}\n\n\tmt7621_ecc_decoder_op(nfc, false);\n\n\tnfi_write16(nfc, NFI_CON, 0);\n\n\treturn bitflips;\n}\n\nstatic int mt7621_nfc_read_page_raw(struct nand_chip *nand, uint8_t *buf,\n\t\t\t\t    int oob_required, int page)\n{\n\tstruct mt7621_nfc *nfc = nand_get_controller_data(nand);\n\tint i;\n\n\tnand_read_page_op(nand, page, 0, NULL, 0);\n\n\tnfi_write16(nfc, NFI_CNFG, (CNFG_OP_CUSTOM << CNFG_OP_MODE_S) |\n\t\t    CNFG_READ_MODE);\n\n\tnfi_write16(nfc, NFI_CON,\n\t\t    CON_NFI_BRD | (nand->ecc.steps << CON_NFI_SEC_S));\n\n\tfor (i = 0; i < nand->ecc.steps; i++) {\n\t\t/* Read data */\n\t\tif (buf)\n\t\t\tmt7621_nfc_read_data(nfc, page_data_ptr(nand, buf, i),\n\t\t\t\t\t     nand->ecc.size);\n\t\telse\n\t\t\tmt7621_nfc_read_data_discard(nfc, nand->ecc.size);\n\n\t\t/* Read FDM */\n\t\tmt7621_nfc_read_data(nfc, oob_fdm_ptr(nand, i), NFI_FDM_SIZE);\n\n\t\t/* Read ECC parity data */\n\t\tmt7621_nfc_read_data(nfc, oob_ecc_ptr(nfc, i),\n\t\t\t\t     nfc->spare_per_sector - NFI_FDM_SIZE);\n\t}\n\n\tnfi_write16(nfc, NFI_CON, 0);\n\n\treturn 0;\n}\n\nstatic int mt7621_nfc_read_oob_hwecc(struct nand_chip *nand, int page)\n{\n\treturn mt7621_nfc_read_page_hwecc(nand, NULL, 1, page);\n}\n\nstatic int mt7621_nfc_read_oob_raw(struct nand_chip *nand, int page)\n{\n\treturn mt7621_nfc_read_page_raw(nand, NULL, 1, page);\n}\n\nstatic int mt7621_nfc_check_empty_page(struct nand_chip *nand, const u8 *buf)\n{\n\tstruct mtd_info *mtd = nand_to_mtd(nand);\n\tuint32_t i, j;\n\tu8 *oobptr;\n\n\tif (buf) {\n\t\tfor (i = 0; i < mtd->writesize; i++)\n\t\t\tif (buf[i] != 0xff)\n\t\t\t\treturn 0;\n\t}\n\n\tfor (i = 0; i < nand->ecc.steps; i++) {\n\t\toobptr = oob_fdm_ptr(nand, i);\n\t\tfor (j = 0; j < NFI_FDM_SIZE; j++)\n\t\t\tif (oobptr[j] != 0xff)\n\t\t\t\treturn 0;\n\t}\n\n\treturn 1;\n}\n\nstatic int mt7621_nfc_write_page_hwecc(struct nand_chip *nand,\n\t\t\t\t       const uint8_t *buf, int oob_required,\n\t\t\t\t       int page)\n{\n\tstruct mt7621_nfc *nfc = nand_get_controller_data(nand);\n\tstruct mtd_info *mtd = nand_to_mtd(nand);\n\n\tif (mt7621_nfc_check_empty_page(nand, buf)) {\n\t\t/*\n\t\t * MT7621 ECC engine always generates parity code for input\n\t\t * pages, even for empty pages. Doing so will write back ECC\n\t\t * parity code to the oob region, which means such pages will\n\t\t * no longer be empty pages.\n\t\t *\n\t\t * To avoid this, stop write operation if current page is an\n\t\t * empty page.\n\t\t */\n\t\treturn 0;\n\t}\n\n\tnand_prog_page_begin_op(nand, page, 0, NULL, 0);\n\n\tnfi_write16(nfc, NFI_CNFG, (CNFG_OP_CUSTOM << CNFG_OP_MODE_S) |\n\t\t   CNFG_AUTO_FMT_EN | CNFG_HW_ECC_EN);\n\n\tmt7621_ecc_encoder_op(nfc, true);\n\n\tmt7621_nfc_write_fdm(nfc);\n\n\tnfi_write16(nfc, NFI_CON,\n\t\t    CON_NFI_BWR | (nand->ecc.steps << CON_NFI_SEC_S));\n\n\tif (buf)\n\t\tmt7621_nfc_write_data(nfc, buf, mtd->writesize);\n\telse\n\t\tmt7621_nfc_write_data_empty(nfc, mtd->writesize);\n\n\tmt7621_nfc_wait_write_completion(nfc, nand);\n\n\tmt7621_ecc_encoder_op(nfc, false);\n\n\tnfi_write16(nfc, NFI_CON, 0);\n\n\treturn nand_prog_page_end_op(nand);\n}\n\nstatic int mt7621_nfc_write_page_raw(struct nand_chip *nand,\n\t\t\t\t     const uint8_t *buf, int oob_required,\n\t\t\t\t     int page)\n{\n\tstruct mt7621_nfc *nfc = nand_get_controller_data(nand);\n\tint i;\n\n\tnand_prog_page_begin_op(nand, page, 0, NULL, 0);\n\n\tnfi_write16(nfc, NFI_CNFG, (CNFG_OP_CUSTOM << CNFG_OP_MODE_S));\n\n\tnfi_write16(nfc, NFI_CON,\n\t\t    CON_NFI_BWR | (nand->ecc.steps << CON_NFI_SEC_S));\n\n\tfor (i = 0; i < nand->ecc.steps; i++) {\n\t\t/* Write data */\n\t\tif (buf)\n\t\t\tmt7621_nfc_write_data(nfc, page_data_ptr(nand, buf, i),\n\t\t\t\t\t      nand->ecc.size);\n\t\telse\n\t\t\tmt7621_nfc_write_data_empty(nfc, nand->ecc.size);\n\n\t\t/* Write FDM */\n\t\tmt7621_nfc_write_data(nfc, oob_fdm_ptr(nand, i),\n\t\t\t\t      NFI_FDM_SIZE);\n\n\t\t/* Write dummy ECC parity data */\n\t\tmt7621_nfc_write_data_empty(nfc, nfc->spare_per_sector -\n\t\t\t\t\t    NFI_FDM_SIZE);\n\t}\n\n\tmt7621_nfc_wait_write_completion(nfc, nand);\n\n\tnfi_write16(nfc, NFI_CON, 0);\n\n\treturn nand_prog_page_end_op(nand);\n}\n\nstatic int mt7621_nfc_write_oob_hwecc(struct nand_chip *nand, int page)\n{\n\treturn mt7621_nfc_write_page_hwecc(nand, NULL, 1, page);\n}\n\nstatic int mt7621_nfc_write_oob_raw(struct nand_chip *nand, int page)\n{\n\treturn mt7621_nfc_write_page_raw(nand, NULL, 1, page);\n}\n\nstatic int mt7621_nfc_init_chip(struct mt7621_nfc *nfc)\n{\n\tstruct nand_chip *nand = &nfc->nand;\n\tstruct mtd_info *mtd;\n\tint ret;\n\n\tnand->controller = &nfc->controller;\n\tnand_set_controller_data(nand, (void *)nfc);\n\tnand_set_flash_node(nand, nfc->dev->of_node);\n\n\tnand->options |= NAND_USES_DMA | NAND_NO_SUBPAGE_WRITE | NAND_SKIP_BBTSCAN;\n\tif (!nfc->nfi_clk)\n\t\tnand->options |= NAND_KEEP_TIMINGS;\n\n\tnand->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;\n\tnand->ecc.read_page = mt7621_nfc_read_page_hwecc;\n\tnand->ecc.read_page_raw = mt7621_nfc_read_page_raw;\n\tnand->ecc.write_page = mt7621_nfc_write_page_hwecc;\n\tnand->ecc.write_page_raw = mt7621_nfc_write_page_raw;\n\tnand->ecc.read_oob = mt7621_nfc_read_oob_hwecc;\n\tnand->ecc.read_oob_raw = mt7621_nfc_read_oob_raw;\n\tnand->ecc.write_oob = mt7621_nfc_write_oob_hwecc;\n\tnand->ecc.write_oob_raw = mt7621_nfc_write_oob_raw;\n\n\tmtd = nand_to_mtd(nand);\n\tmtd->owner = THIS_MODULE;\n\tmtd->dev.parent = nfc->dev;\n\tmtd->name = MT7621_NFC_NAME;\n\tmtd_set_ooblayout(mtd, &mt7621_nfc_ooblayout_ops);\n\n\tmt7621_nfc_hw_init(nfc);\n\n\tret = nand_scan(nand, 1);\n\tif (ret)\n\t\treturn ret;\n\n\tmtk_bmt_attach(mtd);\n\n\tret = mtd_device_register(mtd, NULL, 0);\n\tif (ret) {\n\t\tdev_err(nfc->dev, \"Failed to register MTD: %d\\n\", ret);\n\t\tmtk_bmt_detach(mtd);\n\t\tnand_cleanup(nand);\n\t\treturn ret;\n\t}\n\n\treturn 0;\n}\n\nstatic int mt7621_nfc_probe(struct platform_device *pdev)\n{\n\tstruct device *dev = &pdev->dev;\n\tstruct mt7621_nfc *nfc;\n\tstruct resource *res;\n\tint ret;\n\n\tnfc = devm_kzalloc(dev, sizeof(*nfc), GFP_KERNEL);\n\tif (!nfc)\n\t\treturn -ENOMEM;\n\n\tnand_controller_init(&nfc->controller);\n\tnfc->controller.ops = &mt7621_nfc_controller_ops;\n\tnfc->dev = dev;\n\n\tres = platform_get_resource_byname(pdev, IORESOURCE_MEM, \"nfi\");\n\tnfc->nfi_base = res->start;\n\tnfc->nfi_regs = devm_ioremap_resource(dev, res);\n\tif (IS_ERR(nfc->nfi_regs)) {\n\t\tret = PTR_ERR(nfc->nfi_regs);\n\t\treturn ret;\n\t}\n\n\tres = platform_get_resource_byname(pdev, IORESOURCE_MEM, \"ecc\");\n\tnfc->ecc_regs = devm_ioremap_resource(dev, res);\n\tif (IS_ERR(nfc->ecc_regs)) {\n\t\tret = PTR_ERR(nfc->ecc_regs);\n\t\treturn ret;\n\t}\n\n\tnfc->nfi_clk = devm_clk_get(dev, \"nfi_clk\");\n\tif (IS_ERR(nfc->nfi_clk)) {\n\t\tdev_warn(dev, \"nfi clk not provided\\n\");\n\t\tnfc->nfi_clk = NULL;\n\t} else {\n\t\tret = clk_prepare_enable(nfc->nfi_clk);\n\t\tif (ret) {\n\t\t\tdev_err(dev, \"Failed to enable nfi core clock\\n\");\n\t\t\treturn ret;\n\t\t}\n\t}\n\n\tplatform_set_drvdata(pdev, nfc);\n\n\tret = mt7621_nfc_init_chip(nfc);\n\tif (ret) {\n\t\tdev_err(dev, \"Failed to initialize nand chip\\n\");\n\t\tgoto clk_disable;\n\t}\n\n\treturn 0;\n\nclk_disable:\n\tclk_disable_unprepare(nfc->nfi_clk);\n\n\treturn ret;\n}\n\nstatic int mt7621_nfc_remove(struct platform_device *pdev)\n{\n\tstruct mt7621_nfc *nfc = platform_get_drvdata(pdev);\n\tstruct nand_chip *nand = &nfc->nand;\n\tstruct mtd_info *mtd = nand_to_mtd(nand);\n\n\tmtk_bmt_detach(mtd);\n\tmtd_device_unregister(mtd);\n\tnand_cleanup(nand);\n\tclk_disable_unprepare(nfc->nfi_clk);\n\n\treturn 0;\n}\n\nstatic const struct of_device_id mt7621_nfc_id_table[] = {\n\t{ .compatible = \"mediatek,mt7621-nfc\" },\n\t{ },\n};\nMODULE_DEVICE_TABLE(of, match);\n\nstatic struct platform_driver mt7621_nfc_driver = {\n\t.probe = mt7621_nfc_probe,\n\t.remove = mt7621_nfc_remove,\n\t.driver = {\n\t\t.name = MT7621_NFC_NAME,\n\t\t.owner = THIS_MODULE,\n\t\t.of_match_table = mt7621_nfc_id_table,\n\t},\n};\nmodule_platform_driver(mt7621_nfc_driver);\n\nMODULE_LICENSE(\"GPL\");\nMODULE_AUTHOR(\"Weijie Gao <weijie.gao@mediatek.com>\");\nMODULE_DESCRIPTION(\"MediaTek MT7621 NAND Flash Controller driver\");\n"
  },
  {
    "path": "target/linux/ramips/files/drivers/net/ethernet/ralink/Kconfig",
    "content": "config NET_VENDOR_RALINK\n\ttristate \"Ralink ethernet driver\"\n\tdepends on RALINK\n\thelp\n\t  This driver supports the ethernet mac inside Ralink WiSoCs\n\nconfig NET_RALINK_SOC\n\tdef_tristate NET_VENDOR_RALINK\n\nif NET_RALINK_SOC\nchoice\n\tprompt \"MAC type\"\n\nconfig NET_RALINK_RT2880\n\tbool \"RT2882\"\n\tdepends on MIPS && SOC_RT288X\n\nconfig NET_RALINK_RT3050\n\tbool \"RT3050/MT7628\"\n\tdepends on MIPS && (SOC_RT305X || SOC_MT7620)\n\nconfig NET_RALINK_RT3883\n\tbool \"RT3883\"\n\tdepends on MIPS && SOC_RT3883\n\nconfig NET_RALINK_MT7620\n\tbool \"MT7620\"\n\tdepends on MIPS && SOC_MT7620\n\nendchoice\n\nconfig NET_RALINK_HW_QOS\n\tdef_bool NET_RALINK_SOC\n\tdepends on NET_RALINK_MT7623\n\nconfig NET_RALINK_MDIO\n\tdef_bool NET_RALINK_SOC\n\tdepends on (NET_RALINK_RT2880 || NET_RALINK_RT3883 || NET_RALINK_MT7620)\n\tselect PHYLIB\n\nconfig NET_RALINK_MDIO_RT2880\n\tdef_bool NET_RALINK_SOC\n\tdepends on (NET_RALINK_RT2880 || NET_RALINK_RT3883)\n\tselect NET_RALINK_MDIO\n\nconfig NET_RALINK_MDIO_MT7620\n\tdef_bool NET_RALINK_SOC\n\tdepends on NET_RALINK_MT7620\n\tselect NET_RALINK_MDIO\n\nconfig NET_RALINK_ESW_RT3050\n\tdef_tristate NET_RALINK_SOC\n\tdepends on NET_RALINK_RT3050\n\nconfig NET_RALINK_GSW_MT7620\n\tdef_tristate NET_RALINK_SOC\n\tdepends on NET_RALINK_MT7620\nendif\n"
  },
  {
    "path": "target/linux/ramips/files/drivers/net/ethernet/ralink/Makefile",
    "content": "#\n# Makefile for the Ralink SoCs built-in ethernet macs\n#\n\nralink-eth-y\t\t\t\t\t+= mtk_eth_soc.o ethtool.o\n\nralink-eth-$(CONFIG_NET_RALINK_MDIO)\t\t+= mdio.o\nralink-eth-$(CONFIG_NET_RALINK_MDIO_RT2880)\t+= mdio_rt2880.o\nralink-eth-$(CONFIG_NET_RALINK_MDIO_MT7620)\t+= mdio_mt7620.o\n\nralink-eth-$(CONFIG_NET_RALINK_RT2880)\t+= soc_rt2880.o\nralink-eth-$(CONFIG_NET_RALINK_RT3050)\t+= soc_rt3050.o\nralink-eth-$(CONFIG_NET_RALINK_RT3883)\t+= soc_rt3883.o\nralink-eth-$(CONFIG_NET_RALINK_MT7620)\t+= soc_mt7620.o\n\nobj-$(CONFIG_NET_RALINK_ESW_RT3050)\t\t+= esw_rt3050.o\nobj-$(CONFIG_NET_RALINK_GSW_MT7620)\t\t+= gsw_mt7620.o mt7530.o\nobj-$(CONFIG_NET_RALINK_SOC)\t\t\t+= ralink-eth.o\n"
  },
  {
    "path": "target/linux/ramips/files/drivers/net/ethernet/ralink/esw_rt3050.c",
    "content": "/*   This program is free software; you can redistribute it and/or modify\n *   it under the terms of the GNU General Public License as published by\n *   the Free Software Foundation; version 2 of the License\n *\n *   This program is distributed in the hope that it will be useful,\n *   but WITHOUT ANY WARRANTY; without even the implied warranty of\n *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n *   GNU General Public License for more details.\n *\n *   Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>\n *   Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>\n *   Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>\n *   Copyright (C) 2016 Vittorio Gambaletta <openwrt@vittgam.net>\n */\n\n#include <linux/module.h>\n#include <linux/kernel.h>\n#include <linux/platform_device.h>\n#include <asm/mach-ralink/ralink_regs.h>\n#include <linux/of_device.h>\n#include <linux/of_irq.h>\n\n#include <linux/switch.h>\n#include <linux/reset.h>\n\n#include \"mtk_eth_soc.h\"\n#include \"esw_rt3050.h\"\n\n/* HW limitations for this switch:\n * - No large frame support (PKT_MAX_LEN at most 1536)\n * - Can't have untagged vlan and tagged vlan on one port at the same time,\n *   though this might be possible using the undocumented PPE.\n */\n\n#define RT305X_ESW_REG_ISR\t\t0x00\n#define RT305X_ESW_REG_IMR\t\t0x04\n#define RT305X_ESW_REG_FCT0\t\t0x08\n#define RT305X_ESW_REG_PFC1\t\t0x14\n#define RT305X_ESW_REG_ATS\t\t0x24\n#define RT305X_ESW_REG_ATS0\t\t0x28\n#define RT305X_ESW_REG_ATS1\t\t0x2c\n#define RT305X_ESW_REG_ATS2\t\t0x30\n#define RT305X_ESW_REG_PVIDC(_n)\t(0x40 + 4 * (_n))\n#define RT305X_ESW_REG_VLANI(_n)\t(0x50 + 4 * (_n))\n#define RT305X_ESW_REG_VMSC(_n)\t\t(0x70 + 4 * (_n))\n#define RT305X_ESW_REG_POA\t\t0x80\n#define RT305X_ESW_REG_FPA\t\t0x84\n#define RT305X_ESW_REG_SOCPC\t\t0x8c\n#define RT305X_ESW_REG_POC0\t\t0x90\n#define RT305X_ESW_REG_POC1\t\t0x94\n#define RT305X_ESW_REG_POC2\t\t0x98\n#define RT305X_ESW_REG_SGC\t\t0x9c\n#define RT305X_ESW_REG_STRT\t\t0xa0\n#define RT305X_ESW_REG_PCR0\t\t0xc0\n#define RT305X_ESW_REG_PCR1\t\t0xc4\n#define RT305X_ESW_REG_FPA2\t\t0xc8\n#define RT305X_ESW_REG_FCT2\t\t0xcc\n#define RT305X_ESW_REG_SGC2\t\t0xe4\n#define RT305X_ESW_REG_P0LED\t\t0xa4\n#define RT305X_ESW_REG_P1LED\t\t0xa8\n#define RT305X_ESW_REG_P2LED\t\t0xac\n#define RT305X_ESW_REG_P3LED\t\t0xb0\n#define RT305X_ESW_REG_P4LED\t\t0xb4\n#define RT305X_ESW_REG_PXPC(_x)\t\t(0xe8 + (4 * _x))\n#define RT305X_ESW_REG_P1PC\t\t0xec\n#define RT305X_ESW_REG_P2PC\t\t0xf0\n#define RT305X_ESW_REG_P3PC\t\t0xf4\n#define RT305X_ESW_REG_P4PC\t\t0xf8\n#define RT305X_ESW_REG_P5PC\t\t0xfc\n\n#define RT305X_ESW_LED_LINK\t\t0\n#define RT305X_ESW_LED_100M\t\t1\n#define RT305X_ESW_LED_DUPLEX\t\t2\n#define RT305X_ESW_LED_ACTIVITY\t\t3\n#define RT305X_ESW_LED_COLLISION\t4\n#define RT305X_ESW_LED_LINKACT\t\t5\n#define RT305X_ESW_LED_DUPLCOLL\t\t6\n#define RT305X_ESW_LED_10MACT\t\t7\n#define RT305X_ESW_LED_100MACT\t\t8\n/* Additional led states not in datasheet: */\n#define RT305X_ESW_LED_BLINK\t\t10\n#define RT305X_ESW_LED_OFF\t\t11\n#define RT305X_ESW_LED_ON\t\t12\n\n#define RT305X_ESW_LINK_S\t\t25\n#define RT305X_ESW_DUPLEX_S\t\t9\n#define RT305X_ESW_SPD_S\t\t0\n\n#define RT305X_ESW_PCR0_WT_NWAY_DATA_S\t16\n#define RT305X_ESW_PCR0_WT_PHY_CMD\tBIT(13)\n#define RT305X_ESW_PCR0_CPU_PHY_REG_S\t8\n\n#define RT305X_ESW_PCR1_WT_DONE\t\tBIT(0)\n\n#define RT305X_ESW_ATS_TIMEOUT\t\t(5 * HZ)\n#define RT305X_ESW_PHY_TIMEOUT\t\t(5 * HZ)\n\n#define RT305X_ESW_PVIDC_PVID_M\t\t0xfff\n#define RT305X_ESW_PVIDC_PVID_S\t\t12\n\n#define RT305X_ESW_VLANI_VID_M\t\t0xfff\n#define RT305X_ESW_VLANI_VID_S\t\t12\n\n#define RT305X_ESW_VMSC_MSC_M\t\t0xff\n#define RT305X_ESW_VMSC_MSC_S\t\t8\n\n#define RT305X_ESW_SOCPC_DISUN2CPU_S\t0\n#define RT305X_ESW_SOCPC_DISMC2CPU_S\t8\n#define RT305X_ESW_SOCPC_DISBC2CPU_S\t16\n#define RT305X_ESW_SOCPC_CRC_PADDING\tBIT(25)\n\n#define RT305X_ESW_POC0_EN_BP_S\t\t0\n#define RT305X_ESW_POC0_EN_FC_S\t\t8\n#define RT305X_ESW_POC0_DIS_RMC2CPU_S\t16\n#define RT305X_ESW_POC0_DIS_PORT_M\t0x7f\n#define RT305X_ESW_POC0_DIS_PORT_S\t23\n\n#define RT305X_ESW_POC2_UNTAG_EN_M\t0xff\n#define RT305X_ESW_POC2_UNTAG_EN_S\t0\n#define RT305X_ESW_POC2_ENAGING_S\t8\n#define RT305X_ESW_POC2_DIS_UC_PAUSE_S\t16\n\n#define RT305X_ESW_SGC2_DOUBLE_TAG_M\t0x7f\n#define RT305X_ESW_SGC2_DOUBLE_TAG_S\t0\n#define RT305X_ESW_SGC2_LAN_PMAP_M\t0x3f\n#define RT305X_ESW_SGC2_LAN_PMAP_S\t24\n\n#define RT305X_ESW_PFC1_EN_VLAN_M\t0xff\n#define RT305X_ESW_PFC1_EN_VLAN_S\t16\n#define RT305X_ESW_PFC1_EN_TOS_S\t24\n\n#define RT305X_ESW_VLAN_NONE\t\t0xfff\n\n#define RT305X_ESW_GSC_BC_STROM_MASK\t0x3\n#define RT305X_ESW_GSC_BC_STROM_SHIFT\t4\n\n#define RT305X_ESW_GSC_LED_FREQ_MASK\t0x3\n#define RT305X_ESW_GSC_LED_FREQ_SHIFT\t23\n\n#define RT305X_ESW_POA_LINK_MASK\t0x1f\n#define RT305X_ESW_POA_LINK_SHIFT\t25\n\n#define RT305X_ESW_PORT_ST_CHG\t\tBIT(26)\n#define RT305X_ESW_PORT0\t\t0\n#define RT305X_ESW_PORT1\t\t1\n#define RT305X_ESW_PORT2\t\t2\n#define RT305X_ESW_PORT3\t\t3\n#define RT305X_ESW_PORT4\t\t4\n#define RT305X_ESW_PORT5\t\t5\n#define RT305X_ESW_PORT6\t\t6\n\n#define RT305X_ESW_PORTS_NONE\t\t0\n\n#define RT305X_ESW_PMAP_LLLLLL\t\t0x3f\n#define RT305X_ESW_PMAP_LLLLWL\t\t0x2f\n#define RT305X_ESW_PMAP_WLLLLL\t\t0x3e\n\n#define RT305X_ESW_PORTS_INTERNAL\t\t\t\t\t\\\n\t\t(BIT(RT305X_ESW_PORT0) | BIT(RT305X_ESW_PORT1) |\t\\\n\t\t BIT(RT305X_ESW_PORT2) | BIT(RT305X_ESW_PORT3) |\t\\\n\t\t BIT(RT305X_ESW_PORT4))\n\n#define RT305X_ESW_PORTS_NOCPU\t\t\t\t\t\t\\\n\t\t(RT305X_ESW_PORTS_INTERNAL | BIT(RT305X_ESW_PORT5))\n\n#define RT305X_ESW_PORTS_CPU\tBIT(RT305X_ESW_PORT6)\n\n#define RT305X_ESW_PORTS_ALL\t\t\t\t\t\t\\\n\t\t(RT305X_ESW_PORTS_NOCPU | RT305X_ESW_PORTS_CPU)\n\n#define RT305X_ESW_NUM_VLANS\t\t16\n#define RT305X_ESW_NUM_VIDS\t\t4096\n#define RT305X_ESW_NUM_PORTS\t\t7\n#define RT305X_ESW_NUM_LANWAN\t\t6\n#define RT305X_ESW_NUM_LEDS\t\t5\n\n#define RT5350_ESW_REG_PXTPC(_x)\t(0x150 + (4 * _x))\n#define RT5350_EWS_REG_LED_CONTROL\t0x168\n\nenum {\n\t/* Global attributes. */\n\tRT305X_ESW_ATTR_ENABLE_VLAN,\n\tRT305X_ESW_ATTR_ALT_VLAN_DISABLE,\n\tRT305X_ESW_ATTR_BC_STATUS,\n\tRT305X_ESW_ATTR_LED_FREQ,\n\t/* Port attributes. */\n\tRT305X_ESW_ATTR_PORT_DISABLE,\n\tRT305X_ESW_ATTR_PORT_DOUBLETAG,\n\tRT305X_ESW_ATTR_PORT_UNTAG,\n\tRT305X_ESW_ATTR_PORT_LED,\n\tRT305X_ESW_ATTR_PORT_LAN,\n\tRT305X_ESW_ATTR_PORT_RECV_BAD,\n\tRT305X_ESW_ATTR_PORT_RECV_GOOD,\n\tRT5350_ESW_ATTR_PORT_TR_BAD,\n\tRT5350_ESW_ATTR_PORT_TR_GOOD,\n};\n\nstruct esw_port {\n\tbool\tdisable;\n\tbool\tdoubletag;\n\tbool\tuntag;\n\tu8\tled;\n\tu16\tpvid;\n};\n\nstruct esw_vlan {\n\tu8\tports;\n\tu16\tvid;\n};\n\nenum {\n\tRT305X_ESW_VLAN_CONFIG_NONE = 0,\n\tRT305X_ESW_VLAN_CONFIG_LLLLW,\n\tRT305X_ESW_VLAN_CONFIG_WLLLL,\n};\n\nstruct rt305x_esw {\n\tstruct device\t\t*dev;\n\tvoid __iomem\t\t*base;\n\tint\t\t\tirq;\n\tstruct fe_priv\t\t*priv;\n\n\t/* Protects against concurrent register r/w operations. */\n\tspinlock_t\t\treg_rw_lock;\n\n\tunsigned char\t\tport_map;\n\tunsigned char\t\tport_disable;\n\tunsigned int\t\treg_initval_fct2;\n\tunsigned int\t\treg_initval_fpa2;\n\tunsigned int\t\treg_led_polarity;\n\tunsigned int\t\treg_led_source;\n\n\tstruct switch_dev\tswdev;\n\tbool\t\t\tglobal_vlan_enable;\n\tbool\t\t\talt_vlan_disable;\n\tint\t\t\tbc_storm_protect;\n\tint\t\t\tled_frequency;\n\tstruct esw_vlan vlans[RT305X_ESW_NUM_VLANS];\n\tstruct esw_port ports[RT305X_ESW_NUM_PORTS];\n\tstruct reset_control\t*rst_esw;\n\tstruct reset_control\t*rst_ephy;\n\n};\n\nstatic inline void esw_w32(struct rt305x_esw *esw, u32 val, unsigned reg)\n{\n\t__raw_writel(val, esw->base + reg);\n}\n\nstatic inline u32 esw_r32(struct rt305x_esw *esw, unsigned reg)\n{\n\treturn __raw_readl(esw->base + reg);\n}\n\nstatic inline void esw_rmw_raw(struct rt305x_esw *esw, unsigned reg,\n\t\t\t       unsigned long mask, unsigned long val)\n{\n\tunsigned long t;\n\n\tt = __raw_readl(esw->base + reg) & ~mask;\n\t__raw_writel(t | val, esw->base + reg);\n}\n\nstatic void esw_reset(struct rt305x_esw *esw)\n{\n\tif (!esw->rst_esw)\n\t\treturn;\n\n\treset_control_assert(esw->rst_esw);\n\tusleep_range(60, 120);\n\treset_control_deassert(esw->rst_esw);\n\t/* the esw takes long to reset otherwise the board hang */\n\tmsleep(10);\n}\n\nstatic void esw_reset_ephy(struct rt305x_esw *esw)\n{\n\tif (!esw->rst_ephy)\n\t\treturn;\n\n\treset_control_assert(esw->rst_ephy);\n\tusleep_range(60, 120);\n\treset_control_deassert(esw->rst_ephy);\n\tusleep_range(60, 120);\n}\n\nstatic void esw_rmw(struct rt305x_esw *esw, unsigned reg,\n\t\t    unsigned long mask, unsigned long val)\n{\n\tunsigned long flags;\n\n\tspin_lock_irqsave(&esw->reg_rw_lock, flags);\n\tesw_rmw_raw(esw, reg, mask, val);\n\tspin_unlock_irqrestore(&esw->reg_rw_lock, flags);\n}\n\nstatic u32 rt305x_mii_write(struct rt305x_esw *esw, u32 phy_addr,\n\t\t\t    u32 phy_register, u32 write_data)\n{\n\tunsigned long t_start = jiffies;\n\tint ret = 0;\n\n\twhile (1) {\n\t\tif (!(esw_r32(esw, RT305X_ESW_REG_PCR1) &\n\t\t      RT305X_ESW_PCR1_WT_DONE))\n\t\t\tbreak;\n\t\tif (time_after(jiffies, t_start + RT305X_ESW_PHY_TIMEOUT)) {\n\t\t\tret = 1;\n\t\t\tgoto out;\n\t\t}\n\t}\n\n\twrite_data &= 0xffff;\n\tesw_w32(esw, (write_data << RT305X_ESW_PCR0_WT_NWAY_DATA_S) |\n\t\t      (phy_register << RT305X_ESW_PCR0_CPU_PHY_REG_S) |\n\t\t      (phy_addr) | RT305X_ESW_PCR0_WT_PHY_CMD,\n\t\tRT305X_ESW_REG_PCR0);\n\n\tt_start = jiffies;\n\twhile (1) {\n\t\tif (esw_r32(esw, RT305X_ESW_REG_PCR1) &\n\t\t\t    RT305X_ESW_PCR1_WT_DONE)\n\t\t\tbreak;\n\n\t\tif (time_after(jiffies, t_start + RT305X_ESW_PHY_TIMEOUT)) {\n\t\t\tret = 1;\n\t\t\tbreak;\n\t\t}\n\t}\nout:\n\tif (ret)\n\t\tdev_err(esw->dev, \"ramips_eth: MDIO timeout\\n\");\n\treturn ret;\n}\n\nstatic unsigned esw_get_vlan_id(struct rt305x_esw *esw, unsigned vlan)\n{\n\tunsigned s;\n\tunsigned val;\n\n\ts = RT305X_ESW_VLANI_VID_S * (vlan % 2);\n\tval = esw_r32(esw, RT305X_ESW_REG_VLANI(vlan / 2));\n\tval = (val >> s) & RT305X_ESW_VLANI_VID_M;\n\n\treturn val;\n}\n\nstatic void esw_set_vlan_id(struct rt305x_esw *esw, unsigned vlan, unsigned vid)\n{\n\tunsigned s;\n\n\ts = RT305X_ESW_VLANI_VID_S * (vlan % 2);\n\tesw_rmw(esw,\n\t\t       RT305X_ESW_REG_VLANI(vlan / 2),\n\t\t       RT305X_ESW_VLANI_VID_M << s,\n\t\t       (vid & RT305X_ESW_VLANI_VID_M) << s);\n}\n\nstatic unsigned esw_get_pvid(struct rt305x_esw *esw, unsigned port)\n{\n\tunsigned s, val;\n\n\ts = RT305X_ESW_PVIDC_PVID_S * (port % 2);\n\tval = esw_r32(esw, RT305X_ESW_REG_PVIDC(port / 2));\n\treturn (val >> s) & RT305X_ESW_PVIDC_PVID_M;\n}\n\nstatic void esw_set_pvid(struct rt305x_esw *esw, unsigned port, unsigned pvid)\n{\n\tunsigned s;\n\n\ts = RT305X_ESW_PVIDC_PVID_S * (port % 2);\n\tesw_rmw(esw,\n\t\t       RT305X_ESW_REG_PVIDC(port / 2),\n\t\t       RT305X_ESW_PVIDC_PVID_M << s,\n\t\t       (pvid & RT305X_ESW_PVIDC_PVID_M) << s);\n}\n\nstatic unsigned esw_get_vmsc(struct rt305x_esw *esw, unsigned vlan)\n{\n\tunsigned s, val;\n\n\ts = RT305X_ESW_VMSC_MSC_S * (vlan % 4);\n\tval = esw_r32(esw, RT305X_ESW_REG_VMSC(vlan / 4));\n\tval = (val >> s) & RT305X_ESW_VMSC_MSC_M;\n\n\treturn val;\n}\n\nstatic void esw_set_vmsc(struct rt305x_esw *esw, unsigned vlan, unsigned msc)\n{\n\tunsigned s;\n\n\ts = RT305X_ESW_VMSC_MSC_S * (vlan % 4);\n\tesw_rmw(esw,\n\t\t       RT305X_ESW_REG_VMSC(vlan / 4),\n\t\t       RT305X_ESW_VMSC_MSC_M << s,\n\t\t       (msc & RT305X_ESW_VMSC_MSC_M) << s);\n}\n\nstatic unsigned esw_get_port_disable(struct rt305x_esw *esw)\n{\n\tunsigned reg;\n\n\treg = esw_r32(esw, RT305X_ESW_REG_POC0);\n\treturn (reg >> RT305X_ESW_POC0_DIS_PORT_S) &\n\t       RT305X_ESW_POC0_DIS_PORT_M;\n}\n\nstatic void esw_set_port_disable(struct rt305x_esw *esw, unsigned disable_mask)\n{\n\tunsigned old_mask;\n\tunsigned enable_mask;\n\tunsigned changed;\n\tint i;\n\n\told_mask = esw_get_port_disable(esw);\n\tchanged = old_mask ^ disable_mask;\n\tenable_mask = old_mask & disable_mask;\n\n\t/* enable before writing to MII */\n\tesw_rmw(esw, RT305X_ESW_REG_POC0,\n\t\t       (RT305X_ESW_POC0_DIS_PORT_M <<\n\t\t\tRT305X_ESW_POC0_DIS_PORT_S),\n\t\t       enable_mask << RT305X_ESW_POC0_DIS_PORT_S);\n\n\tfor (i = 0; i < RT305X_ESW_NUM_LEDS; i++) {\n\t\tif (!(changed & (1 << i)))\n\t\t\tcontinue;\n\t\tif (disable_mask & (1 << i)) {\n\t\t\t/* disable */\n\t\t\trt305x_mii_write(esw, i, MII_BMCR,\n\t\t\t\t\t BMCR_PDOWN);\n\t\t} else {\n\t\t\t/* enable */\n\t\t\trt305x_mii_write(esw, i, MII_BMCR,\n\t\t\t\t\t BMCR_FULLDPLX |\n\t\t\t\t\t BMCR_ANENABLE |\n\t\t\t\t\t BMCR_ANRESTART |\n\t\t\t\t\t BMCR_SPEED100);\n\t\t}\n\t}\n\n\t/* disable after writing to MII */\n\tesw_rmw(esw, RT305X_ESW_REG_POC0,\n\t\t       (RT305X_ESW_POC0_DIS_PORT_M <<\n\t\t\tRT305X_ESW_POC0_DIS_PORT_S),\n\t\t       disable_mask << RT305X_ESW_POC0_DIS_PORT_S);\n}\n\nstatic void esw_set_gsc(struct rt305x_esw *esw)\n{\n\tesw_rmw(esw, RT305X_ESW_REG_SGC,\n\t\tRT305X_ESW_GSC_BC_STROM_MASK << RT305X_ESW_GSC_BC_STROM_SHIFT,\n\t\tesw->bc_storm_protect << RT305X_ESW_GSC_BC_STROM_SHIFT);\n\tesw_rmw(esw, RT305X_ESW_REG_SGC,\n\t\tRT305X_ESW_GSC_LED_FREQ_MASK << RT305X_ESW_GSC_LED_FREQ_SHIFT,\n\t\tesw->led_frequency << RT305X_ESW_GSC_LED_FREQ_SHIFT);\n}\n\nstatic int esw_apply_config(struct switch_dev *dev);\n\nstatic void esw_hw_init(struct rt305x_esw *esw)\n{\n\tint i;\n\tu8 port_disable = 0;\n\tu8 port_map = RT305X_ESW_PMAP_LLLLLL;\n\n\tesw_reset(esw);\n\n\t/* vodoo from original driver */\n\tesw_w32(esw, 0xC8A07850, RT305X_ESW_REG_FCT0);\n\tesw_w32(esw, 0x00000000, RT305X_ESW_REG_SGC2);\n\t/* Port priority 1 for all ports, vlan enabled. */\n\tesw_w32(esw, 0x00005555 |\n\t\t     (RT305X_ESW_PORTS_ALL << RT305X_ESW_PFC1_EN_VLAN_S),\n\t\tRT305X_ESW_REG_PFC1);\n\n\t/* Enable all ports, Back Pressure and Flow Control */\n\tesw_w32(esw, ((RT305X_ESW_PORTS_ALL << RT305X_ESW_POC0_EN_BP_S) |\n\t\t      (RT305X_ESW_PORTS_ALL << RT305X_ESW_POC0_EN_FC_S)),\n\t\tRT305X_ESW_REG_POC0);\n\n\t/* Enable Aging, and VLAN TAG removal */\n\tesw_w32(esw, ((RT305X_ESW_PORTS_ALL << RT305X_ESW_POC2_ENAGING_S) |\n\t\t      (RT305X_ESW_PORTS_NOCPU << RT305X_ESW_POC2_UNTAG_EN_S)),\n\t\tRT305X_ESW_REG_POC2);\n\n\tif (esw->reg_initval_fct2)\n\t\tesw_w32(esw, esw->reg_initval_fct2, RT305X_ESW_REG_FCT2);\n\telse\n\t\tesw_w32(esw, 0x0002500c, RT305X_ESW_REG_FCT2);\n\n\t/* 300s aging timer, max packet len 1536, broadcast storm prevention\n\t * disabled, disable collision abort, mac xor48 hash, 10 packet back\n\t * pressure jam, GMII disable was_transmit, back pressure disabled,\n\t * 30ms led flash, unmatched IGMP as broadcast, rmc tb fault to all\n\t * ports.\n\t */\n\tesw_w32(esw, 0x0008a301, RT305X_ESW_REG_SGC);\n\n\t/* Setup SoC Port control register */\n\tesw_w32(esw,\n\t\t(RT305X_ESW_SOCPC_CRC_PADDING |\n\t\t(RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISUN2CPU_S) |\n\t\t(RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISMC2CPU_S) |\n\t\t(RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISBC2CPU_S)),\n\t\tRT305X_ESW_REG_SOCPC);\n\n\t/* ext phy base addr 31, enable port 5 polling, rx/tx clock skew 1,\n\t * turbo mii off, rgmi 3.3v off\n\t * port5: disabled\n\t * port6: enabled, gige, full-duplex, rx/tx-flow-control\n\t */\n\tif (esw->reg_initval_fpa2)\n\t\tesw_w32(esw, esw->reg_initval_fpa2, RT305X_ESW_REG_FPA2);\n\telse\n\t\tesw_w32(esw, 0x3f502b28, RT305X_ESW_REG_FPA2);\n\tesw_w32(esw, 0x00000000, RT305X_ESW_REG_FPA);\n\n\t/* Force Link/Activity on ports */\n\tesw_w32(esw, RT305X_ESW_LED_LINKACT, RT305X_ESW_REG_P0LED);\n\tesw_w32(esw, RT305X_ESW_LED_LINKACT, RT305X_ESW_REG_P1LED);\n\tesw_w32(esw, RT305X_ESW_LED_LINKACT, RT305X_ESW_REG_P2LED);\n\tesw_w32(esw, RT305X_ESW_LED_LINKACT, RT305X_ESW_REG_P3LED);\n\tesw_w32(esw, RT305X_ESW_LED_LINKACT, RT305X_ESW_REG_P4LED);\n\n\t/* Copy disabled port configuration from device tree setup */\n\tport_disable = esw->port_disable;\n\n\t/* Disable nonexistent ports by reading the switch config\n\t * after having enabled all possible ports above\n\t */\n\tport_disable |= esw_get_port_disable(esw);\n\n\tfor (i = 0; i < 6; i++)\n\t\tesw->ports[i].disable = (port_disable & (1 << i)) != 0;\n\n\tif (ralink_soc == RT305X_SOC_RT3352) {\n\t\tesw_reset_ephy(esw);\n\n\t\trt305x_mii_write(esw, 0, 31, 0x8000);\n\t\tfor (i = 0; i < 5; i++) {\n\t\t\tif (esw->ports[i].disable) {\n\t\t\t\trt305x_mii_write(esw, i, MII_BMCR, BMCR_PDOWN);\n\t\t\t} else {\n\t\t\t\trt305x_mii_write(esw, i, MII_BMCR,\n\t\t\t\t\t\t BMCR_FULLDPLX |\n\t\t\t\t\t\t BMCR_ANENABLE |\n\t\t\t\t\t\t BMCR_SPEED100);\n\t\t\t}\n\t\t\t/* TX10 waveform coefficient LSB=0 disable PHY */\n\t\t\trt305x_mii_write(esw, i, 26, 0x1601);\n\t\t\t/* TX100/TX10 AD/DA current bias */\n\t\t\trt305x_mii_write(esw, i, 29, 0x7016);\n\t\t\t/* TX100 slew rate control */\n\t\t\trt305x_mii_write(esw, i, 30, 0x0038);\n\t\t}\n\n\t\t/* select global register */\n\t\trt305x_mii_write(esw, 0, 31, 0x0);\n\t\t/* enlarge agcsel threshold 3 and threshold 2 */\n\t\trt305x_mii_write(esw, 0, 1, 0x4a40);\n\t\t/* enlarge agcsel threshold 5 and threshold 4 */\n\t\trt305x_mii_write(esw, 0, 2, 0x6254);\n\t\t/* enlarge agcsel threshold  */\n\t\trt305x_mii_write(esw, 0, 3, 0xa17f);\n\t\trt305x_mii_write(esw, 0, 12, 0x7eaa);\n\t\t/* longer TP_IDL tail length */\n\t\trt305x_mii_write(esw, 0, 14, 0x65);\n\t\t/* increased squelch pulse count threshold. */\n\t\trt305x_mii_write(esw, 0, 16, 0x0684);\n\t\t/* set TX10 signal amplitude threshold to minimum */\n\t\trt305x_mii_write(esw, 0, 17, 0x0fe0);\n\t\t/* set squelch amplitude to higher threshold */\n\t\trt305x_mii_write(esw, 0, 18, 0x40ba);\n\t\t/* tune TP_IDL tail and head waveform, enable power\n\t\t * down slew rate control\n\t\t */\n\t\trt305x_mii_write(esw, 0, 22, 0x253f);\n\t\t/* set PLL/Receive bias current are calibrated */\n\t\trt305x_mii_write(esw, 0, 27, 0x2fda);\n\t\t/* change PLL/Receive bias current to internal(RT3350) */\n\t\trt305x_mii_write(esw, 0, 28, 0xc410);\n\t\t/* change PLL bias current to internal(RT3052_MP3) */\n\t\trt305x_mii_write(esw, 0, 29, 0x598b);\n\t\t/* select local register */\n\t\trt305x_mii_write(esw, 0, 31, 0x8000);\n\t} else if (ralink_soc == RT305X_SOC_RT5350) {\n\t\tesw_reset_ephy(esw);\n\n\t\t/* set the led polarity */\n\t\tesw_w32(esw, esw->reg_led_polarity & 0x1F,\n\t\t\tRT5350_EWS_REG_LED_CONTROL);\n\n\t\t/* local registers */\n\t\trt305x_mii_write(esw, 0, 31, 0x8000);\n\t\tfor (i = 0; i < 5; i++) {\n\t\t\tif (esw->ports[i].disable) {\n\t\t\t\trt305x_mii_write(esw, i, MII_BMCR, BMCR_PDOWN);\n\t\t\t} else {\n\t\t\t\trt305x_mii_write(esw, i, MII_BMCR,\n\t\t\t\t\t\t BMCR_FULLDPLX |\n\t\t\t\t\t\t BMCR_ANENABLE |\n\t\t\t\t\t\t BMCR_SPEED100);\n\t\t\t}\n\t\t\t/* TX10 waveform coefficient LSB=0 disable PHY */\n\t\t\trt305x_mii_write(esw, i, 26, 0x1601);\n\t\t\t/* TX100/TX10 AD/DA current bias */\n\t\t\trt305x_mii_write(esw, i, 29, 0x7015);\n\t\t\t/* TX100 slew rate control */\n\t\t\trt305x_mii_write(esw, i, 30, 0x0038);\n\t\t}\n\n\t\t/* global registers */\n\t\trt305x_mii_write(esw, 0, 31, 0x0);\n\t\t/* enlarge agcsel threshold 3 and threshold 2 */\n\t\trt305x_mii_write(esw, 0, 1, 0x4a40);\n\t\t/* enlarge agcsel threshold 5 and threshold 4 */\n\t\trt305x_mii_write(esw, 0, 2, 0x6254);\n\t\t/* enlarge agcsel threshold 6 */\n\t\trt305x_mii_write(esw, 0, 3, 0xa17f);\n\t\trt305x_mii_write(esw, 0, 12, 0x7eaa);\n\t\t/* longer TP_IDL tail length */\n\t\trt305x_mii_write(esw, 0, 14, 0x65);\n\t\t/* increased squelch pulse count threshold. */\n\t\trt305x_mii_write(esw, 0, 16, 0x0684);\n\t\t/* set TX10 signal amplitude threshold to minimum */\n\t\trt305x_mii_write(esw, 0, 17, 0x0fe0);\n\t\t/* set squelch amplitude to higher threshold */\n\t\trt305x_mii_write(esw, 0, 18, 0x40ba);\n\t\t/* tune TP_IDL tail and head waveform, enable power\n\t\t * down slew rate control\n\t\t */\n\t\trt305x_mii_write(esw, 0, 22, 0x253f);\n\t\t/* set PLL/Receive bias current are calibrated */\n\t\trt305x_mii_write(esw, 0, 27, 0x2fda);\n\t\t/* change PLL/Receive bias current to internal(RT3350) */\n\t\trt305x_mii_write(esw, 0, 28, 0xc410);\n\t\t/* change PLL bias current to internal(RT3052_MP3) */\n\t\trt305x_mii_write(esw, 0, 29, 0x598b);\n\t\t/* select local register */\n\t\trt305x_mii_write(esw, 0, 31, 0x8000);\n\t} else if (ralink_soc == MT762X_SOC_MT7628AN || ralink_soc == MT762X_SOC_MT7688) {\n\t\tint i;\n\n\t\tesw_reset_ephy(esw);\n\n\t\t/* set the led polarity and led source */\n\t\tesw_w32(esw, (esw->reg_led_polarity & 0x1F) |\n\t\t\t\t((esw->reg_led_source << 8) & 0x700),\n\t\t\t\tRT5350_EWS_REG_LED_CONTROL);\n\n\t\trt305x_mii_write(esw, 0, 31, 0x2000); /* change G2 page */\n\t\trt305x_mii_write(esw, 0, 26, 0x0020);\n\n\t\tfor (i = 0; i < 5; i++) {\n\t\t\trt305x_mii_write(esw, i, 31, 0x8000);\n\t\t\trt305x_mii_write(esw, i,  0, 0x3100);\n\t\t\trt305x_mii_write(esw, i, 30, 0xa000);\n\t\t\trt305x_mii_write(esw, i, 31, 0xa000);\n\t\t\trt305x_mii_write(esw, i, 16, 0x0606);\n\t\t\trt305x_mii_write(esw, i, 23, 0x0f0e);\n\t\t\trt305x_mii_write(esw, i, 24, 0x1610);\n\t\t\trt305x_mii_write(esw, i, 30, 0x1f15);\n\t\t\trt305x_mii_write(esw, i, 28, 0x6111);\n\t\t\trt305x_mii_write(esw, i, 31, 0x2000);\n\t\t\trt305x_mii_write(esw, i, 26, 0x0000);\n\t\t}\n\n\t\t/* 100Base AOI setting */\n\t\trt305x_mii_write(esw, 0, 31, 0x5000);\n\t\trt305x_mii_write(esw, 0, 19, 0x004a);\n\t\trt305x_mii_write(esw, 0, 20, 0x015a);\n\t\trt305x_mii_write(esw, 0, 21, 0x00ee);\n\t\trt305x_mii_write(esw, 0, 22, 0x0033);\n\t\trt305x_mii_write(esw, 0, 23, 0x020a);\n\t\trt305x_mii_write(esw, 0, 24, 0x0000);\n\t\trt305x_mii_write(esw, 0, 25, 0x024a);\n\t\trt305x_mii_write(esw, 0, 26, 0x035a);\n\t\trt305x_mii_write(esw, 0, 27, 0x02ee);\n\t\trt305x_mii_write(esw, 0, 28, 0x0233);\n\t\trt305x_mii_write(esw, 0, 29, 0x000a);\n\t\trt305x_mii_write(esw, 0, 30, 0x0000);\n\t} else {\n\t\trt305x_mii_write(esw, 0, 31, 0x8000);\n\t\tfor (i = 0; i < 5; i++) {\n\t\t\tif (esw->ports[i].disable) {\n\t\t\t\trt305x_mii_write(esw, i, MII_BMCR, BMCR_PDOWN);\n\t\t\t} else {\n\t\t\t\trt305x_mii_write(esw, i, MII_BMCR,\n\t\t\t\t\t\t BMCR_FULLDPLX |\n\t\t\t\t\t\t BMCR_ANENABLE |\n\t\t\t\t\t\t BMCR_SPEED100);\n\t\t\t}\n\t\t\t/* TX10 waveform coefficient */\n\t\t\trt305x_mii_write(esw, i, 26, 0x1601);\n\t\t\t/* TX100/TX10 AD/DA current bias */\n\t\t\trt305x_mii_write(esw, i, 29, 0x7058);\n\t\t\t/* TX100 slew rate control */\n\t\t\trt305x_mii_write(esw, i, 30, 0x0018);\n\t\t}\n\n\t\t/* PHY IOT */\n\t\t/* select global register */\n\t\trt305x_mii_write(esw, 0, 31, 0x0);\n\t\t/* tune TP_IDL tail and head waveform */\n\t\trt305x_mii_write(esw, 0, 22, 0x052f);\n\t\t/* set TX10 signal amplitude threshold to minimum */\n\t\trt305x_mii_write(esw, 0, 17, 0x0fe0);\n\t\t/* set squelch amplitude to higher threshold */\n\t\trt305x_mii_write(esw, 0, 18, 0x40ba);\n\t\t/* longer TP_IDL tail length */\n\t\trt305x_mii_write(esw, 0, 14, 0x65);\n\t\t/* select local register */\n\t\trt305x_mii_write(esw, 0, 31, 0x8000);\n\t}\n\n\tif (esw->port_map)\n\t\tport_map = esw->port_map;\n\telse\n\t\tport_map = RT305X_ESW_PMAP_LLLLLL;\n\n\t/* Unused HW feature, but still nice to be consistent here...\n\t * This is also exported to userspace ('lan' attribute) so it's\n\t * conveniently usable to decide which ports go into the wan vlan by\n\t * default.\n\t */\n\tesw_rmw(esw, RT305X_ESW_REG_SGC2,\n\t\tRT305X_ESW_SGC2_LAN_PMAP_M << RT305X_ESW_SGC2_LAN_PMAP_S,\n\t\tport_map << RT305X_ESW_SGC2_LAN_PMAP_S);\n\n\t/* make the switch leds blink */\n\tfor (i = 0; i < RT305X_ESW_NUM_LEDS; i++)\n\t\tesw->ports[i].led = 0x05;\n\n\t/* Apply the empty config. */\n\tesw_apply_config(&esw->swdev);\n\n\t/* Only unmask the port change interrupt */\n\tesw_w32(esw, ~RT305X_ESW_PORT_ST_CHG, RT305X_ESW_REG_IMR);\n}\n\n\nint rt3050_esw_has_carrier(struct fe_priv *priv)\n{\n\tstruct rt305x_esw *esw = priv->soc->swpriv;\n\tu32 link;\n\tint i;\n\tbool cpuport;\n\n\tlink = esw_r32(esw, RT305X_ESW_REG_POA);\n\tlink >>= RT305X_ESW_POA_LINK_SHIFT;\n\tcpuport = link & BIT(RT305X_ESW_PORT6);\n\tlink &= RT305X_ESW_POA_LINK_MASK;\n\tfor (i = 0; i <= RT305X_ESW_PORT5; i++) {\n\t\tif (priv->link[i] != (link & BIT(i)))\n\t\t\tdev_info(esw->dev, \"port %d link %s\\n\", i, link & BIT(i) ? \"up\" : \"down\");\n\t\tpriv->link[i] = link & BIT(i);\n\t}\n\n\treturn !!link && cpuport;\n}\n\nstatic irqreturn_t esw_interrupt(int irq, void *_esw)\n{\n\tstruct rt305x_esw *esw = (struct rt305x_esw *) _esw;\n\tu32 status;\n\tint i;\n\n\tstatus = esw_r32(esw, RT305X_ESW_REG_ISR);\n\tif (status & RT305X_ESW_PORT_ST_CHG) {\n\t\tif (!esw->priv)\n\t\t\tgoto out;\n\t\tif (rt3050_esw_has_carrier(esw->priv))\n\t\t\tnetif_carrier_on(esw->priv->netdev);\n\t\telse\n\t\t\tnetif_carrier_off(esw->priv->netdev);\n\t}\n\nout:\n\tesw_w32(esw, status, RT305X_ESW_REG_ISR);\n\n\treturn IRQ_HANDLED;\n}\n\nstatic int esw_apply_config(struct switch_dev *dev)\n{\n\tstruct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);\n\tint i;\n\tu8 disable = 0;\n\tu8 doubletag = 0;\n\tu8 en_vlan = 0;\n\tu8 untag = 0;\n\n\tfor (i = 0; i < RT305X_ESW_NUM_VLANS; i++) {\n\t\tu32 vid, vmsc;\n\t\tif (esw->global_vlan_enable) {\n\t\t\tvid = esw->vlans[i].vid;\n\t\t\tvmsc = esw->vlans[i].ports;\n\t\t} else {\n\t\t\tvid = RT305X_ESW_VLAN_NONE;\n\t\t\tvmsc = RT305X_ESW_PORTS_NONE;\n\t\t}\n\t\tesw_set_vlan_id(esw, i, vid);\n\t\tesw_set_vmsc(esw, i, vmsc);\n\t}\n\n\tfor (i = 0; i < RT305X_ESW_NUM_PORTS; i++) {\n\t\tu32 pvid;\n\t\tdisable |= esw->ports[i].disable << i;\n\t\tif (esw->global_vlan_enable) {\n\t\t\tdoubletag |= esw->ports[i].doubletag << i;\n\t\t\ten_vlan   |= 1                       << i;\n\t\t\tuntag     |= esw->ports[i].untag     << i;\n\t\t\tpvid       = esw->ports[i].pvid;\n\t\t} else {\n\t\t\tint x = esw->alt_vlan_disable ? 0 : 1;\n\t\t\tdoubletag |= x << i;\n\t\t\ten_vlan   |= x << i;\n\t\t\tuntag     |= x << i;\n\t\t\tpvid       = 0;\n\t\t}\n\t\tesw_set_pvid(esw, i, pvid);\n\t\tif (i < RT305X_ESW_NUM_LEDS)\n\t\t\tesw_w32(esw, esw->ports[i].led,\n\t\t\t\t      RT305X_ESW_REG_P0LED + 4*i);\n\t}\n\n\tesw_set_gsc(esw);\n\tesw_set_port_disable(esw, disable);\n\tesw_rmw(esw, RT305X_ESW_REG_SGC2,\n\t\t       (RT305X_ESW_SGC2_DOUBLE_TAG_M <<\n\t\t\tRT305X_ESW_SGC2_DOUBLE_TAG_S),\n\t\t       doubletag << RT305X_ESW_SGC2_DOUBLE_TAG_S);\n\tesw_rmw(esw, RT305X_ESW_REG_PFC1,\n\t\t       RT305X_ESW_PFC1_EN_VLAN_M << RT305X_ESW_PFC1_EN_VLAN_S,\n\t\t       en_vlan << RT305X_ESW_PFC1_EN_VLAN_S);\n\tesw_rmw(esw, RT305X_ESW_REG_POC2,\n\t\t       RT305X_ESW_POC2_UNTAG_EN_M << RT305X_ESW_POC2_UNTAG_EN_S,\n\t\t       untag << RT305X_ESW_POC2_UNTAG_EN_S);\n\n\tif (!esw->global_vlan_enable) {\n\t\t/*\n\t\t * Still need to put all ports into vlan 0 or they'll be\n\t\t * isolated.\n\t\t * NOTE: vlan 0 is special, no vlan tag is prepended\n\t\t */\n\t\tesw_set_vlan_id(esw, 0, 0);\n\t\tesw_set_vmsc(esw, 0, RT305X_ESW_PORTS_ALL);\n\t}\n\n\treturn 0;\n}\n\nstatic int esw_reset_switch(struct switch_dev *dev)\n{\n\tstruct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);\n\n\tesw->global_vlan_enable = 0;\n\tmemset(esw->ports, 0, sizeof(esw->ports));\n\tmemset(esw->vlans, 0, sizeof(esw->vlans));\n\tesw_hw_init(esw);\n\n\treturn 0;\n}\n\nstatic int esw_get_vlan_enable(struct switch_dev *dev,\n\t\t\t   const struct switch_attr *attr,\n\t\t\t   struct switch_val *val)\n{\n\tstruct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);\n\n\tval->value.i = esw->global_vlan_enable;\n\n\treturn 0;\n}\n\nstatic int esw_set_vlan_enable(struct switch_dev *dev,\n\t\t\t   const struct switch_attr *attr,\n\t\t\t   struct switch_val *val)\n{\n\tstruct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);\n\n\tesw->global_vlan_enable = val->value.i != 0;\n\n\treturn 0;\n}\n\nstatic int esw_get_alt_vlan_disable(struct switch_dev *dev,\n\t\t\t\tconst struct switch_attr *attr,\n\t\t\t\tstruct switch_val *val)\n{\n\tstruct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);\n\n\tval->value.i = esw->alt_vlan_disable;\n\n\treturn 0;\n}\n\nstatic int esw_set_alt_vlan_disable(struct switch_dev *dev,\n\t\t\t\tconst struct switch_attr *attr,\n\t\t\t\tstruct switch_val *val)\n{\n\tstruct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);\n\n\tesw->alt_vlan_disable = val->value.i != 0;\n\n\treturn 0;\n}\n\nstatic int\nrt305x_esw_set_bc_status(struct switch_dev *dev,\n\t\t\tconst struct switch_attr *attr,\n\t\t\tstruct switch_val *val)\n{\n\tstruct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);\n\n\tesw->bc_storm_protect = val->value.i & RT305X_ESW_GSC_BC_STROM_MASK;\n\n\treturn 0;\n}\n\nstatic int\nrt305x_esw_get_bc_status(struct switch_dev *dev,\n\t\t\tconst struct switch_attr *attr,\n\t\t\tstruct switch_val *val)\n{\n\tstruct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);\n\n\tval->value.i = esw->bc_storm_protect;\n\n\treturn 0;\n}\n\nstatic int\nrt305x_esw_set_led_freq(struct switch_dev *dev,\n\t\t\tconst struct switch_attr *attr,\n\t\t\tstruct switch_val *val)\n{\n\tstruct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);\n\n\tesw->led_frequency = val->value.i & RT305X_ESW_GSC_LED_FREQ_MASK;\n\n\treturn 0;\n}\n\nstatic int\nrt305x_esw_get_led_freq(struct switch_dev *dev,\n\t\t\tconst struct switch_attr *attr,\n\t\t\tstruct switch_val *val)\n{\n\tstruct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);\n\n\tval->value.i = esw->led_frequency;\n\n\treturn 0;\n}\n\nstatic int esw_get_port_link(struct switch_dev *dev,\n\t\t\t int port,\n\t\t\t struct switch_port_link *link)\n{\n\tstruct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);\n\tu32 speed, poa;\n\n\tif (port < 0 || port >= RT305X_ESW_NUM_PORTS)\n\t\treturn -EINVAL;\n\n\tpoa = esw_r32(esw, RT305X_ESW_REG_POA) >> port;\n\n\tlink->link = (poa >> RT305X_ESW_LINK_S) & 1;\n\tlink->duplex = (poa >> RT305X_ESW_DUPLEX_S) & 1;\n\tif (port < RT305X_ESW_NUM_LEDS) {\n\t\tspeed = (poa >> RT305X_ESW_SPD_S) & 1;\n\t} else {\n\t\tif (port == RT305X_ESW_NUM_PORTS - 1)\n\t\t\tpoa >>= 1;\n\t\tspeed = (poa >> RT305X_ESW_SPD_S) & 3;\n\t}\n\tswitch (speed) {\n\tcase 0:\n\t\tlink->speed = SWITCH_PORT_SPEED_10;\n\t\tbreak;\n\tcase 1:\n\t\tlink->speed = SWITCH_PORT_SPEED_100;\n\t\tbreak;\n\tcase 2:\n\tcase 3: /* forced gige speed can be 2 or 3 */\n\t\tlink->speed = SWITCH_PORT_SPEED_1000;\n\t\tbreak;\n\tdefault:\n\t\tlink->speed = SWITCH_PORT_SPEED_UNKNOWN;\n\t\tbreak;\n\t}\n\n\treturn 0;\n}\n\nstatic int esw_get_port_bool(struct switch_dev *dev,\n\t\t\t const struct switch_attr *attr,\n\t\t\t struct switch_val *val)\n{\n\tstruct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);\n\tint idx = val->port_vlan;\n\tu32 x, reg, shift;\n\n\tif (idx < 0 || idx >= RT305X_ESW_NUM_PORTS)\n\t\treturn -EINVAL;\n\n\tswitch (attr->id) {\n\tcase RT305X_ESW_ATTR_PORT_DISABLE:\n\t\treg = RT305X_ESW_REG_POC0;\n\t\tshift = RT305X_ESW_POC0_DIS_PORT_S;\n\t\tbreak;\n\tcase RT305X_ESW_ATTR_PORT_DOUBLETAG:\n\t\treg = RT305X_ESW_REG_SGC2;\n\t\tshift = RT305X_ESW_SGC2_DOUBLE_TAG_S;\n\t\tbreak;\n\tcase RT305X_ESW_ATTR_PORT_UNTAG:\n\t\treg = RT305X_ESW_REG_POC2;\n\t\tshift = RT305X_ESW_POC2_UNTAG_EN_S;\n\t\tbreak;\n\tcase RT305X_ESW_ATTR_PORT_LAN:\n\t\treg = RT305X_ESW_REG_SGC2;\n\t\tshift = RT305X_ESW_SGC2_LAN_PMAP_S;\n\t\tif (idx >= RT305X_ESW_NUM_LANWAN)\n\t\t\treturn -EINVAL;\n\t\tbreak;\n\tdefault:\n\t\treturn -EINVAL;\n\t}\n\n\tx = esw_r32(esw, reg);\n\tval->value.i = (x >> (idx + shift)) & 1;\n\n\treturn 0;\n}\n\nstatic int esw_set_port_bool(struct switch_dev *dev,\n\t\t\t const struct switch_attr *attr,\n\t\t\t struct switch_val *val)\n{\n\tstruct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);\n\tint idx = val->port_vlan;\n\n\tif (idx < 0 || idx >= RT305X_ESW_NUM_PORTS ||\n\t    val->value.i < 0 || val->value.i > 1)\n\t\treturn -EINVAL;\n\n\tswitch (attr->id) {\n\tcase RT305X_ESW_ATTR_PORT_DISABLE:\n\t\tesw->ports[idx].disable = val->value.i;\n\t\tbreak;\n\tcase RT305X_ESW_ATTR_PORT_DOUBLETAG:\n\t\tesw->ports[idx].doubletag = val->value.i;\n\t\tbreak;\n\tcase RT305X_ESW_ATTR_PORT_UNTAG:\n\t\tesw->ports[idx].untag = val->value.i;\n\t\tbreak;\n\tdefault:\n\t\treturn -EINVAL;\n\t}\n\n\treturn 0;\n}\n\nstatic int esw_get_port_recv_badgood(struct switch_dev *dev,\n\t\t\t\t const struct switch_attr *attr,\n\t\t\t\t struct switch_val *val)\n{\n\tstruct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);\n\tint idx = val->port_vlan;\n\tint shift = attr->id == RT305X_ESW_ATTR_PORT_RECV_GOOD ? 0 : 16;\n\tu32 reg;\n\n\tif (idx < 0 || idx >= RT305X_ESW_NUM_LANWAN)\n\t\treturn -EINVAL;\n\treg = esw_r32(esw, RT305X_ESW_REG_PXPC(idx));\n\tval->value.i = (reg >> shift) & 0xffff;\n\n\treturn 0;\n}\n\nstatic int\nesw_get_port_tr_badgood(struct switch_dev *dev,\n\t\t\t\t const struct switch_attr *attr,\n\t\t\t\t struct switch_val *val)\n{\n\tstruct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);\n\n\tint idx = val->port_vlan;\n\tint shift = attr->id == RT5350_ESW_ATTR_PORT_TR_GOOD ? 0 : 16;\n\tu32 reg;\n\n\tif ((ralink_soc != RT305X_SOC_RT5350) && (ralink_soc != MT762X_SOC_MT7628AN) && (ralink_soc != MT762X_SOC_MT7688))\n\t\treturn -EINVAL;\n\n\tif (idx < 0 || idx >= RT305X_ESW_NUM_LANWAN)\n\t\treturn -EINVAL;\n\n\treg = esw_r32(esw, RT5350_ESW_REG_PXTPC(idx));\n\tval->value.i = (reg >> shift) & 0xffff;\n\n\treturn 0;\n}\n\nstatic int esw_get_port_led(struct switch_dev *dev,\n\t\t\tconst struct switch_attr *attr,\n\t\t\tstruct switch_val *val)\n{\n\tstruct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);\n\tint idx = val->port_vlan;\n\n\tif (idx < 0 || idx >= RT305X_ESW_NUM_PORTS ||\n\t    idx >= RT305X_ESW_NUM_LEDS)\n\t\treturn -EINVAL;\n\n\tval->value.i = esw_r32(esw, RT305X_ESW_REG_P0LED + 4*idx);\n\n\treturn 0;\n}\n\nstatic int esw_set_port_led(struct switch_dev *dev,\n\t\t\tconst struct switch_attr *attr,\n\t\t\tstruct switch_val *val)\n{\n\tstruct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);\n\tint idx = val->port_vlan;\n\n\tif (idx < 0 || idx >= RT305X_ESW_NUM_LEDS)\n\t\treturn -EINVAL;\n\n\tesw->ports[idx].led = val->value.i;\n\n\treturn 0;\n}\n\nstatic int esw_get_port_pvid(struct switch_dev *dev, int port, int *val)\n{\n\tstruct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);\n\n\tif (port >= RT305X_ESW_NUM_PORTS)\n\t\treturn -EINVAL;\n\n\t*val = esw_get_pvid(esw, port);\n\n\treturn 0;\n}\n\nstatic int esw_set_port_pvid(struct switch_dev *dev, int port, int val)\n{\n\tstruct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);\n\n\tif (port >= RT305X_ESW_NUM_PORTS)\n\t\treturn -EINVAL;\n\n\tesw->ports[port].pvid = val;\n\n\treturn 0;\n}\n\nstatic int esw_get_vlan_ports(struct switch_dev *dev, struct switch_val *val)\n{\n\tstruct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);\n\tu32 vmsc, poc2;\n\tint vlan_idx = -1;\n\tint i;\n\n\tval->len = 0;\n\n\tif (val->port_vlan < 0 || val->port_vlan >= RT305X_ESW_NUM_VIDS)\n\t\treturn -EINVAL;\n\n\t/* valid vlan? */\n\tfor (i = 0; i < RT305X_ESW_NUM_VLANS; i++) {\n\t\tif (esw_get_vlan_id(esw, i) == val->port_vlan &&\n\t\t    esw_get_vmsc(esw, i) != RT305X_ESW_PORTS_NONE) {\n\t\t\tvlan_idx = i;\n\t\t\tbreak;\n\t\t}\n\t}\n\n\tif (vlan_idx == -1)\n\t\treturn -EINVAL;\n\n\tvmsc = esw_get_vmsc(esw, vlan_idx);\n\tpoc2 = esw_r32(esw, RT305X_ESW_REG_POC2);\n\n\tfor (i = 0; i < RT305X_ESW_NUM_PORTS; i++) {\n\t\tstruct switch_port *p;\n\t\tint port_mask = 1 << i;\n\n\t\tif (!(vmsc & port_mask))\n\t\t\tcontinue;\n\n\t\tp = &val->value.ports[val->len++];\n\t\tp->id = i;\n\t\tif (poc2 & (port_mask << RT305X_ESW_POC2_UNTAG_EN_S))\n\t\t\tp->flags = 0;\n\t\telse\n\t\t\tp->flags = 1 << SWITCH_PORT_FLAG_TAGGED;\n\t}\n\n\treturn 0;\n}\n\nstatic int esw_set_vlan_ports(struct switch_dev *dev, struct switch_val *val)\n{\n\tstruct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);\n\tint ports;\n\tint vlan_idx = -1;\n\tint i;\n\n\tif (val->port_vlan < 0 || val->port_vlan >= RT305X_ESW_NUM_VIDS ||\n\t    val->len > RT305X_ESW_NUM_PORTS)\n\t\treturn -EINVAL;\n\n\t/* one of the already defined vlans? */\n\tfor (i = 0; i < RT305X_ESW_NUM_VLANS; i++) {\n\t\tif (esw->vlans[i].vid == val->port_vlan &&\n\t\t    esw->vlans[i].ports != RT305X_ESW_PORTS_NONE) {\n\t\t\tvlan_idx = i;\n\t\t\tbreak;\n\t\t}\n\t}\n\n\t/* select a free slot */\n\tfor (i = 0; vlan_idx == -1 && i < RT305X_ESW_NUM_VLANS; i++) {\n\t\tif (esw->vlans[i].ports == RT305X_ESW_PORTS_NONE)\n\t\t\tvlan_idx = i;\n\t}\n\n\t/* bail if all slots are in use */\n\tif (vlan_idx == -1)\n\t\treturn -EINVAL;\n\n\tports = RT305X_ESW_PORTS_NONE;\n\tfor (i = 0; i < val->len; i++) {\n\t\tstruct switch_port *p = &val->value.ports[i];\n\t\tint port_mask = 1 << p->id;\n\t\tbool untagged = !(p->flags & (1 << SWITCH_PORT_FLAG_TAGGED));\n\n\t\tif (p->id >= RT305X_ESW_NUM_PORTS)\n\t\t\treturn -EINVAL;\n\n\t\tports |= port_mask;\n\t\tesw->ports[p->id].untag = untagged;\n\t}\n\tesw->vlans[vlan_idx].ports = ports;\n\tif (ports == RT305X_ESW_PORTS_NONE)\n\t\tesw->vlans[vlan_idx].vid = RT305X_ESW_VLAN_NONE;\n\telse\n\t\tesw->vlans[vlan_idx].vid = val->port_vlan;\n\n\treturn 0;\n}\n\nstatic const struct switch_attr esw_global[] = {\n\t{\n\t\t.type = SWITCH_TYPE_INT,\n\t\t.name = \"enable_vlan\",\n\t\t.description = \"VLAN mode (1:enabled)\",\n\t\t.max = 1,\n\t\t.id = RT305X_ESW_ATTR_ENABLE_VLAN,\n\t\t.get = esw_get_vlan_enable,\n\t\t.set = esw_set_vlan_enable,\n\t},\n\t{\n\t\t.type = SWITCH_TYPE_INT,\n\t\t.name = \"alternate_vlan_disable\",\n\t\t.description = \"Use en_vlan instead of doubletag to disable\"\n\t\t\t\t\" VLAN mode\",\n\t\t.max = 1,\n\t\t.id = RT305X_ESW_ATTR_ALT_VLAN_DISABLE,\n\t\t.get = esw_get_alt_vlan_disable,\n\t\t.set = esw_set_alt_vlan_disable,\n\t},\n\t{\n\t\t.type = SWITCH_TYPE_INT,\n\t\t.name = \"bc_storm_protect\",\n\t\t.description = \"Global broadcast storm protection (0:Disable, 1:64 blocks, 2:96 blocks, 3:128 blocks)\",\n\t\t.max = 3,\n\t\t.id = RT305X_ESW_ATTR_BC_STATUS,\n\t\t.get = rt305x_esw_get_bc_status,\n\t\t.set = rt305x_esw_set_bc_status,\n\t},\n\t{\n\t\t.type = SWITCH_TYPE_INT,\n\t\t.name = \"led_frequency\",\n\t\t.description = \"LED Flash frequency (0:30mS, 1:60mS, 2:240mS, 3:480mS)\",\n\t\t.max = 3,\n\t\t.id = RT305X_ESW_ATTR_LED_FREQ,\n\t\t.get = rt305x_esw_get_led_freq,\n\t\t.set = rt305x_esw_set_led_freq,\n\t}\n};\n\nstatic const struct switch_attr esw_port[] = {\n\t{\n\t\t.type = SWITCH_TYPE_INT,\n\t\t.name = \"disable\",\n\t\t.description = \"Port state (1:disabled)\",\n\t\t.max = 1,\n\t\t.id = RT305X_ESW_ATTR_PORT_DISABLE,\n\t\t.get = esw_get_port_bool,\n\t\t.set = esw_set_port_bool,\n\t},\n\t{\n\t\t.type = SWITCH_TYPE_INT,\n\t\t.name = \"doubletag\",\n\t\t.description = \"Double tagging for incoming vlan packets \"\n\t\t\t\t\"(1:enabled)\",\n\t\t.max = 1,\n\t\t.id = RT305X_ESW_ATTR_PORT_DOUBLETAG,\n\t\t.get = esw_get_port_bool,\n\t\t.set = esw_set_port_bool,\n\t},\n\t{\n\t\t.type = SWITCH_TYPE_INT,\n\t\t.name = \"untag\",\n\t\t.description = \"Untag (1:strip outgoing vlan tag)\",\n\t\t.max = 1,\n\t\t.id = RT305X_ESW_ATTR_PORT_UNTAG,\n\t\t.get = esw_get_port_bool,\n\t\t.set = esw_set_port_bool,\n\t},\n\t{\n\t\t.type = SWITCH_TYPE_INT,\n\t\t.name = \"led\",\n\t\t.description = \"LED mode (0:link, 1:100m, 2:duplex, 3:activity,\"\n\t\t\t\t\" 4:collision, 5:linkact, 6:duplcoll, 7:10mact,\"\n\t\t\t\t\" 8:100mact, 10:blink, 11:off, 12:on)\",\n\t\t.max = 15,\n\t\t.id = RT305X_ESW_ATTR_PORT_LED,\n\t\t.get = esw_get_port_led,\n\t\t.set = esw_set_port_led,\n\t},\n\t{\n\t\t.type = SWITCH_TYPE_INT,\n\t\t.name = \"lan\",\n\t\t.description = \"HW port group (0:wan, 1:lan)\",\n\t\t.max = 1,\n\t\t.id = RT305X_ESW_ATTR_PORT_LAN,\n\t\t.get = esw_get_port_bool,\n\t},\n\t{\n\t\t.type = SWITCH_TYPE_INT,\n\t\t.name = \"recv_bad\",\n\t\t.description = \"Receive bad packet counter\",\n\t\t.id = RT305X_ESW_ATTR_PORT_RECV_BAD,\n\t\t.get = esw_get_port_recv_badgood,\n\t},\n\t{\n\t\t.type = SWITCH_TYPE_INT,\n\t\t.name = \"recv_good\",\n\t\t.description = \"Receive good packet counter\",\n\t\t.id = RT305X_ESW_ATTR_PORT_RECV_GOOD,\n\t\t.get = esw_get_port_recv_badgood,\n\t},\n\t{\n\t\t.type = SWITCH_TYPE_INT,\n\t\t.name = \"tr_bad\",\n\n\t\t.description = \"Transmit bad packet counter. rt5350 only\",\n\t\t.id = RT5350_ESW_ATTR_PORT_TR_BAD,\n\t\t.get = esw_get_port_tr_badgood,\n\t},\n\t{\n\t\t.type = SWITCH_TYPE_INT,\n\t\t.name = \"tr_good\",\n\n\t\t.description = \"Transmit good packet counter. rt5350 only\",\n\t\t.id = RT5350_ESW_ATTR_PORT_TR_GOOD,\n\t\t.get = esw_get_port_tr_badgood,\n\t},\n};\n\nstatic const struct switch_attr esw_vlan[] = {\n};\n\nstatic const struct switch_dev_ops esw_ops = {\n\t.attr_global = {\n\t\t.attr = esw_global,\n\t\t.n_attr = ARRAY_SIZE(esw_global),\n\t},\n\t.attr_port = {\n\t\t.attr = esw_port,\n\t\t.n_attr = ARRAY_SIZE(esw_port),\n\t},\n\t.attr_vlan = {\n\t\t.attr = esw_vlan,\n\t\t.n_attr = ARRAY_SIZE(esw_vlan),\n\t},\n\t.get_vlan_ports = esw_get_vlan_ports,\n\t.set_vlan_ports = esw_set_vlan_ports,\n\t.get_port_pvid = esw_get_port_pvid,\n\t.set_port_pvid = esw_set_port_pvid,\n\t.get_port_link = esw_get_port_link,\n\t.apply_config = esw_apply_config,\n\t.reset_switch = esw_reset_switch,\n};\n\nstatic int esw_probe(struct platform_device *pdev)\n{\n\tstruct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);\n\tstruct device_node *np = pdev->dev.of_node;\n\tconst __be32 *port_map, *port_disable, *reg_init;\n\tstruct rt305x_esw *esw;\n\n\tesw = devm_kzalloc(&pdev->dev, sizeof(*esw), GFP_KERNEL);\n\tif (!esw)\n\t\treturn -ENOMEM;\n\n\tesw->dev = &pdev->dev;\n\tesw->irq = irq_of_parse_and_map(np, 0);\n\tesw->base = devm_ioremap_resource(&pdev->dev, res);\n\tif (IS_ERR(esw->base))\n\t\treturn PTR_ERR(esw->base);\n\n\tport_map = of_get_property(np, \"mediatek,portmap\", NULL);\n\tif (port_map)\n\t\tesw->port_map = be32_to_cpu(*port_map);\n\n\tport_disable = of_get_property(np, \"mediatek,portdisable\", NULL);\n\tif (port_disable)\n\t\tesw->port_disable = be32_to_cpu(*port_disable);\n\n\treg_init = of_get_property(np, \"ralink,fct2\", NULL);\n\tif (reg_init)\n\t\tesw->reg_initval_fct2 = be32_to_cpu(*reg_init);\n\n\treg_init = of_get_property(np, \"ralink,fpa2\", NULL);\n\tif (reg_init)\n\t\tesw->reg_initval_fpa2 = be32_to_cpu(*reg_init);\n\n\treg_init = of_get_property(np, \"mediatek,led_polarity\", NULL);\n\tif (reg_init)\n\t\tesw->reg_led_polarity = be32_to_cpu(*reg_init);\n\n\treg_init = of_get_property(np, \"mediatek,led_source\", NULL);\n\tif (reg_init)\n\t\tesw->reg_led_source = be32_to_cpu(*reg_init);\n\n\tesw->rst_esw = devm_reset_control_get(&pdev->dev, \"esw\");\n\tif (IS_ERR(esw->rst_esw))\n\t\tesw->rst_esw = NULL;\n\tesw->rst_ephy = devm_reset_control_get(&pdev->dev, \"ephy\");\n\tif (IS_ERR(esw->rst_ephy))\n\t\tesw->rst_ephy = NULL;\n\n\tspin_lock_init(&esw->reg_rw_lock);\n\tplatform_set_drvdata(pdev, esw);\n\n\treturn 0;\n}\n\nstatic int esw_remove(struct platform_device *pdev)\n{\n\tstruct rt305x_esw *esw = platform_get_drvdata(pdev);\n\n\tif (esw) {\n\t\tesw_w32(esw, ~0, RT305X_ESW_REG_IMR);\n\t\tplatform_set_drvdata(pdev, NULL);\n\t}\n\n\treturn 0;\n}\n\nstatic const struct of_device_id ralink_esw_match[] = {\n\t{ .compatible = \"ralink,rt3050-esw\" },\n\t{},\n};\nMODULE_DEVICE_TABLE(of, ralink_esw_match);\n\n/* called by the ethernet driver to bound with the switch driver */\nint rt3050_esw_init(struct fe_priv *priv)\n{\n\tstruct device_node *np = priv->switch_np;\n\tstruct platform_device *pdev = of_find_device_by_node(np);\n\tstruct switch_dev *swdev;\n\tstruct rt305x_esw *esw;\n\tconst __be32 *rgmii;\n\tint ret;\n\n\tif (!pdev)\n\t\treturn -ENODEV;\n\n\tif (!of_device_is_compatible(np, ralink_esw_match->compatible))\n\t\treturn -EINVAL;\n\n\tesw = platform_get_drvdata(pdev);\n\tif (!esw)\n\t\treturn -EPROBE_DEFER;\n\n\tpriv->soc->swpriv = esw;\n\tesw->priv = priv;\n\n\tesw_hw_init(esw);\n\n\trgmii = of_get_property(np, \"ralink,rgmii\", NULL);\n\tif (rgmii && be32_to_cpu(*rgmii) == 1) {\n\t\t/*\n\t\t * External switch connected to RGMII interface.\n\t\t * Unregister the switch device after initialization.\n\t\t */\n\t\tdev_err(&pdev->dev, \"RGMII mode, not exporting switch device.\\n\");\n\t\tunregister_switch(&esw->swdev);\n\t\tplatform_set_drvdata(pdev, NULL);\n\t\treturn -ENODEV;\n\t}\n\n\tswdev = &esw->swdev;\n\tswdev->of_node = pdev->dev.of_node;\n\tswdev->name = \"rt305x-esw\";\n\tswdev->alias = \"rt305x\";\n\tswdev->cpu_port = RT305X_ESW_PORT6;\n\tswdev->ports = RT305X_ESW_NUM_PORTS;\n\tswdev->vlans = RT305X_ESW_NUM_VIDS;\n\tswdev->ops = &esw_ops;\n\n\tret = register_switch(swdev, NULL);\n\tif (ret < 0) {\n\t\tdev_err(&pdev->dev, \"register_switch failed\\n\");\n\t\treturn ret;\n\t}\n\n\tret = devm_request_irq(&pdev->dev, esw->irq, esw_interrupt, 0, \"esw\",\n\t\t\tesw);\n\tif (!ret) {\n\t\tesw_w32(esw, RT305X_ESW_PORT_ST_CHG, RT305X_ESW_REG_ISR);\n\t\tesw_w32(esw, ~RT305X_ESW_PORT_ST_CHG, RT305X_ESW_REG_IMR);\n\t}\n\n\tdev_info(&pdev->dev, \"mediatek esw at 0x%08lx, irq %d initialized\\n\",\n\t\t   esw->base, esw->irq);\n\n\treturn 0;\n}\n\nstatic struct platform_driver esw_driver = {\n\t.probe = esw_probe,\n\t.remove = esw_remove,\n\t.driver = {\n\t\t.name = \"rt3050-esw\",\n\t\t.owner = THIS_MODULE,\n\t\t.of_match_table = ralink_esw_match,\n\t},\n};\n\nmodule_platform_driver(esw_driver);\n\nMODULE_LICENSE(\"GPL\");\nMODULE_AUTHOR(\"John Crispin <blogic@openwrt.org>\");\nMODULE_DESCRIPTION(\"Switch driver for RT305X SoC\");\nMODULE_VERSION(MTK_FE_DRV_VERSION);\n"
  },
  {
    "path": "target/linux/ramips/files/drivers/net/ethernet/ralink/esw_rt3050.h",
    "content": "/*   This program is free software; you can redistribute it and/or modify\n *   it under the terms of the GNU General Public License as published by\n *   the Free Software Foundation; version 2 of the License\n *\n *   This program is distributed in the hope that it will be useful,\n *   but WITHOUT ANY WARRANTY; without even the implied warranty of\n *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n *   GNU General Public License for more details.\n *\n *   Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>\n *   Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>\n *   Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>\n */\n\n#ifndef _RALINK_ESW_RT3052_H__\n#define _RALINK_ESW_RT3052_H__\n\n#ifdef CONFIG_NET_RALINK_ESW_RT3052\n\nint __init mtk_switch_init(void);\nvoid mtk_switch_exit(void);\n\n#else\n\nstatic inline int __init mtk_switch_init(void) { return 0; }\nstatic inline void mtk_switch_exit(void) { }\n\n#endif\n\nint rt3050_esw_init(struct fe_priv *priv);\nint rt3050_esw_has_carrier(struct fe_priv *priv);\n#endif\n"
  },
  {
    "path": "target/linux/ramips/files/drivers/net/ethernet/ralink/ethtool.c",
    "content": "/*   This program is free software; you can redistribute it and/or modify\n *   it under the terms of the GNU General Public License as published by\n *   the Free Software Foundation; version 2 of the License\n *\n *   This program is distributed in the hope that it will be useful,\n *   but WITHOUT ANY WARRANTY; without even the implied warranty of\n *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n *   GNU General Public License for more details.\n *\n *   Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>\n *   Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>\n *   Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>\n */\n\n#include \"mtk_eth_soc.h\"\n\nstatic const char fe_gdma_str[][ETH_GSTRING_LEN] = {\n#define _FE(x...)\t# x,\nFE_STAT_REG_DECLARE\n#undef _FE\n};\n\nstatic int fe_get_link_ksettings(struct net_device *ndev,\n\t\t\t   struct ethtool_link_ksettings *cmd)\n{\n\tstruct fe_priv *priv = netdev_priv(ndev);\n\n\tif (!priv->phy_dev)\n\t\treturn -ENODEV;\n\n\tif (priv->phy_flags == FE_PHY_FLAG_ATTACH) {\n\t\tif (phy_read_status(priv->phy_dev))\n\t\t\treturn -ENODEV;\n\t}\n\n\tphy_ethtool_ksettings_get(ndev->phydev, cmd);\n\n\treturn 0;\n}\n\nstatic int fe_set_link_ksettings(struct net_device *ndev,\n\t\t\t   const struct ethtool_link_ksettings *cmd)\n{\n\tstruct fe_priv *priv = netdev_priv(ndev);\n\n\tif (!priv->phy_dev)\n\t\tgoto out_sset;\n\n\tif (cmd->base.phy_address != priv->phy_dev->mdio.addr) {\n\t\tif (priv->phy->phy_node[cmd->base.phy_address]) {\n\t\t\tpriv->phy_dev = priv->phy->phy[cmd->base.phy_address];\n\t\t\tpriv->phy_flags = FE_PHY_FLAG_PORT;\n\t\t} else if (priv->mii_bus && mdiobus_get_phy(priv->mii_bus, cmd->base.phy_address)) {\n\t\t\tpriv->phy_dev = mdiobus_get_phy(priv->mii_bus, cmd->base.phy_address);\n\t\t\tpriv->phy_flags = FE_PHY_FLAG_ATTACH;\n\t\t} else {\n\t\t\tgoto out_sset;\n\t\t}\n\t}\n\n\treturn phy_ethtool_ksettings_set(ndev->phydev, cmd);\n\nout_sset:\n\treturn -ENODEV;\n}\n\nstatic void fe_get_drvinfo(struct net_device *dev,\n\t\t\t   struct ethtool_drvinfo *info)\n{\n\tstruct fe_priv *priv = netdev_priv(dev);\n\tstruct fe_soc_data *soc = priv->soc;\n\n\tstrlcpy(info->driver, priv->dev->driver->name, sizeof(info->driver));\n\tstrlcpy(info->version, MTK_FE_DRV_VERSION, sizeof(info->version));\n\tstrlcpy(info->bus_info, dev_name(priv->dev), sizeof(info->bus_info));\n\n\tif (soc->reg_table[FE_REG_FE_COUNTER_BASE])\n\t\tinfo->n_stats = ARRAY_SIZE(fe_gdma_str);\n}\n\nstatic u32 fe_get_msglevel(struct net_device *dev)\n{\n\tstruct fe_priv *priv = netdev_priv(dev);\n\n\treturn priv->msg_enable;\n}\n\nstatic void fe_set_msglevel(struct net_device *dev, u32 value)\n{\n\tstruct fe_priv *priv = netdev_priv(dev);\n\n\tpriv->msg_enable = value;\n}\n\nstatic int fe_nway_reset(struct net_device *dev)\n{\n\tstruct fe_priv *priv = netdev_priv(dev);\n\n\tif (!priv->phy_dev)\n\t\tgoto out_nway_reset;\n\n\treturn genphy_restart_aneg(priv->phy_dev);\n\nout_nway_reset:\n\treturn -EOPNOTSUPP;\n}\n\nstatic u32 fe_get_link(struct net_device *dev)\n{\n\tstruct fe_priv *priv = netdev_priv(dev);\n\tint err;\n\n\tif (!priv->phy_dev)\n\t\tgoto out_get_link;\n\n\tif (priv->phy_flags == FE_PHY_FLAG_ATTACH) {\n\t\terr = genphy_update_link(priv->phy_dev);\n\t\tif (err)\n\t\t\tgoto out_get_link;\n\t}\n\n\treturn priv->phy_dev->link;\n\nout_get_link:\n\treturn ethtool_op_get_link(dev);\n}\n\nstatic int fe_set_ringparam(struct net_device *dev,\n\t\t\t    struct ethtool_ringparam *ring)\n{\n\tstruct fe_priv *priv = netdev_priv(dev);\n\n\tif ((ring->tx_pending < 2) ||\n\t    (ring->rx_pending < 2) ||\n\t    (ring->rx_pending > MAX_DMA_DESC) ||\n\t    (ring->tx_pending > MAX_DMA_DESC))\n\t\treturn -EINVAL;\n\n\tdev->netdev_ops->ndo_stop(dev);\n\n\tpriv->tx_ring.tx_ring_size = BIT(fls(ring->tx_pending) - 1);\n\tpriv->rx_ring.rx_ring_size = BIT(fls(ring->rx_pending) - 1);\n\n\tdev->netdev_ops->ndo_open(dev);\n\n\treturn 0;\n}\n\nstatic void fe_get_ringparam(struct net_device *dev,\n\t\t\t     struct ethtool_ringparam *ring)\n{\n\tstruct fe_priv *priv = netdev_priv(dev);\n\n\tring->rx_max_pending = MAX_DMA_DESC;\n\tring->tx_max_pending = MAX_DMA_DESC;\n\tring->rx_pending = priv->rx_ring.rx_ring_size;\n\tring->tx_pending = priv->tx_ring.tx_ring_size;\n}\n\nstatic void fe_get_strings(struct net_device *dev, u32 stringset, u8 *data)\n{\n\tswitch (stringset) {\n\tcase ETH_SS_STATS:\n\t\tmemcpy(data, *fe_gdma_str, sizeof(fe_gdma_str));\n\t\tbreak;\n\t}\n}\n\nstatic int fe_get_sset_count(struct net_device *dev, int sset)\n{\n\tswitch (sset) {\n\tcase ETH_SS_STATS:\n\t\treturn ARRAY_SIZE(fe_gdma_str);\n\tdefault:\n\t\treturn -EOPNOTSUPP;\n\t}\n}\n\nstatic void fe_get_ethtool_stats(struct net_device *dev,\n\t\t\t\t struct ethtool_stats *stats, u64 *data)\n{\n\tstruct fe_priv *priv = netdev_priv(dev);\n\tstruct fe_hw_stats *hwstats = priv->hw_stats;\n\tu64 *data_src, *data_dst;\n\tunsigned int start;\n\tint i;\n\n\tif (netif_running(dev) && netif_device_present(dev)) {\n\t\tif (spin_trylock(&hwstats->stats_lock)) {\n\t\t\tfe_stats_update(priv);\n\t\t\tspin_unlock(&hwstats->stats_lock);\n\t\t}\n\t}\n\n\tdo {\n\t\tdata_src = &hwstats->tx_bytes;\n\t\tdata_dst = data;\n\t\tstart = u64_stats_fetch_begin_irq(&hwstats->syncp);\n\n\t\tfor (i = 0; i < ARRAY_SIZE(fe_gdma_str); i++)\n\t\t\t*data_dst++ = *data_src++;\n\n\t} while (u64_stats_fetch_retry_irq(&hwstats->syncp, start));\n}\n\nstatic struct ethtool_ops fe_ethtool_ops = {\n\t.get_link_ksettings\t= fe_get_link_ksettings,\n\t.set_link_ksettings\t= fe_set_link_ksettings,\n\t.get_drvinfo\t\t= fe_get_drvinfo,\n\t.get_msglevel\t\t= fe_get_msglevel,\n\t.set_msglevel\t\t= fe_set_msglevel,\n\t.nway_reset\t\t= fe_nway_reset,\n\t.get_link\t\t= fe_get_link,\n\t.set_ringparam\t\t= fe_set_ringparam,\n\t.get_ringparam\t\t= fe_get_ringparam,\n};\n\nvoid fe_set_ethtool_ops(struct net_device *netdev)\n{\n\tstruct fe_priv *priv = netdev_priv(netdev);\n\tstruct fe_soc_data *soc = priv->soc;\n\n\tif (soc->reg_table[FE_REG_FE_COUNTER_BASE]) {\n\t\tfe_ethtool_ops.get_strings = fe_get_strings;\n\t\tfe_ethtool_ops.get_sset_count = fe_get_sset_count;\n\t\tfe_ethtool_ops.get_ethtool_stats = fe_get_ethtool_stats;\n\t}\n\n\tnetdev->ethtool_ops = &fe_ethtool_ops;\n}\n"
  },
  {
    "path": "target/linux/ramips/files/drivers/net/ethernet/ralink/ethtool.h",
    "content": "/*   This program is free software; you can redistribute it and/or modify\n *   it under the terms of the GNU General Public License as published by\n *   the Free Software Foundation; version 2 of the License\n *\n *   This program is distributed in the hope that it will be useful,\n *   but WITHOUT ANY WARRANTY; without even the implied warranty of\n *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n *   GNU General Public License for more details.\n *\n *   Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>\n *   Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>\n *   Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>\n */\n\n#ifndef FE_ETHTOOL_H\n#define FE_ETHTOOL_H\n\n#include <linux/ethtool.h>\n\nvoid fe_set_ethtool_ops(struct net_device *netdev);\n\n#endif /* FE_ETHTOOL_H */\n"
  },
  {
    "path": "target/linux/ramips/files/drivers/net/ethernet/ralink/gsw_mt7620.c",
    "content": "/*   This program is free software; you can redistribute it and/or modify\n *   it under the terms of the GNU General Public License as published by\n *   the Free Software Foundation; version 2 of the License\n *\n *   This program is distributed in the hope that it will be useful,\n *   but WITHOUT ANY WARRANTY; without even the implied warranty of\n *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n *   GNU General Public License for more details.\n *\n *   Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>\n *   Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>\n *   Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>\n */\n\n#include <linux/module.h>\n#include <linux/mii.h>\n#include <linux/kernel.h>\n#include <linux/types.h>\n#include <linux/platform_device.h>\n#include <linux/of_device.h>\n#include <linux/of_irq.h>\n\n#include <ralink_regs.h>\n\n#include \"mtk_eth_soc.h\"\n#include \"gsw_mt7620.h\"\n\nvoid mtk_switch_w32(struct mt7620_gsw *gsw, u32 val, unsigned reg)\n{\n\tiowrite32(val, gsw->base + reg);\n}\n\nu32 mtk_switch_r32(struct mt7620_gsw *gsw, unsigned reg)\n{\n\treturn ioread32(gsw->base + reg);\n}\n\nstatic irqreturn_t gsw_interrupt_mt7620(int irq, void *_priv)\n{\n\tstruct fe_priv *priv = (struct fe_priv *)_priv;\n\tstruct mt7620_gsw *gsw = (struct mt7620_gsw *)priv->soc->swpriv;\n\tu32 status;\n\tint i, max = (gsw->port4_ephy) ? (4) : (3);\n\n\tstatus = mtk_switch_r32(gsw, GSW_REG_ISR);\n\tif (status & PORT_IRQ_ST_CHG)\n\t\tfor (i = 0; i <= max; i++) {\n\t\t\tu32 status = mtk_switch_r32(gsw, GSW_REG_PORT_STATUS(i));\n\t\t\tint link = status & 0x1;\n\n\t\t\tif (link != priv->link[i])\n\t\t\t\tmt7620_print_link_state(priv, i, link,\n\t\t\t\t\t\t\t(status >> 2) & 3,\n\t\t\t\t\t\t\t(status & 0x2));\n\n\t\t\tpriv->link[i] = link;\n\t\t}\n\tmt7620_handle_carrier(priv);\n\tmtk_switch_w32(gsw, status, GSW_REG_ISR);\n\n\treturn IRQ_HANDLED;\n}\n\nstatic void mt7620_hw_init(struct mt7620_gsw *gsw)\n{\n\tu32 i;\n\tu32 val;\n\tu32 is_BGA = (rt_sysc_r32(SYSC_REG_CHIP_REV_ID) >> 16) & 1;\n\n\t/* Internal ethernet requires PCIe RC mode */\n\trt_sysc_w32(rt_sysc_r32(SYSC_REG_CFG1) | PCIE_RC_MODE, SYSC_REG_CFG1);\n\n\tmtk_switch_w32(gsw, mtk_switch_r32(gsw, GSW_REG_CKGCR) & ~(0x3 << 4), GSW_REG_CKGCR);\n\n\t/* Enable MIB stats */\n\tmtk_switch_w32(gsw, mtk_switch_r32(gsw, GSW_REG_MIB_CNT_EN) | (1 << 1), GSW_REG_MIB_CNT_EN);\n\n\tif (gsw->ephy_disable) {\n\t\tmtk_switch_w32(gsw, mtk_switch_r32(gsw, GSW_REG_GPC1) |\n\t\t\t(gsw->ephy_base << 16) | (0x1f << 24),\n\t\t\tGSW_REG_GPC1);\n\n\t\tpr_info(\"gsw: internal ephy disabled\\n\");\n\t} else if (gsw->ephy_base) {\n\t\tmtk_switch_w32(gsw, mtk_switch_r32(gsw, GSW_REG_GPC1) |\n\t\t\t(gsw->ephy_base << 16),\n\t\t\tGSW_REG_GPC1);\n\t\tfe_reset(MT7620A_RESET_EPHY);\n\n\t\tpr_info(\"gsw: ephy base address: %d\\n\", gsw->ephy_base);\n\t}\n\n\t/* global page 4 */\n\t_mt7620_mii_write(gsw, gsw->ephy_base + 1, 31, 0x4000);\n\n\t_mt7620_mii_write(gsw, gsw->ephy_base + 1, 17, 0x7444);\n\tif (is_BGA)\n\t\t_mt7620_mii_write(gsw, gsw->ephy_base + 1, 19, 0x0114);\n\telse\n\t\t_mt7620_mii_write(gsw, gsw->ephy_base + 1, 19, 0x0117);\n\n\t_mt7620_mii_write(gsw, gsw->ephy_base + 1, 22, 0x10cf);\n\t_mt7620_mii_write(gsw, gsw->ephy_base + 1, 25, 0x6212);\n\t_mt7620_mii_write(gsw, gsw->ephy_base + 1, 26, 0x0777);\n\t_mt7620_mii_write(gsw, gsw->ephy_base + 1, 29, 0x4000);\n\t_mt7620_mii_write(gsw, gsw->ephy_base + 1, 28, 0xc077);\n\t_mt7620_mii_write(gsw, gsw->ephy_base + 1, 24, 0x0000);\n\n\t/* global page 3 */\n\t_mt7620_mii_write(gsw, gsw->ephy_base + 1, 31, 0x3000);\n\t_mt7620_mii_write(gsw, gsw->ephy_base + 1, 17, 0x4838);\n\n\t/* global page 2 */\n\t_mt7620_mii_write(gsw, gsw->ephy_base + 1, 31, 0x2000);\n\tif (is_BGA) {\n\t\t_mt7620_mii_write(gsw, gsw->ephy_base + 1, 21, 0x0515);\n\t\t_mt7620_mii_write(gsw, gsw->ephy_base + 1, 22, 0x0053);\n\t\t_mt7620_mii_write(gsw, gsw->ephy_base + 1, 23, 0x00bf);\n\t\t_mt7620_mii_write(gsw, gsw->ephy_base + 1, 24, 0x0aaf);\n\t\t_mt7620_mii_write(gsw, gsw->ephy_base + 1, 25, 0x0fad);\n\t\t_mt7620_mii_write(gsw, gsw->ephy_base + 1, 26, 0x0fc1);\n\t} else {\n\t\t_mt7620_mii_write(gsw, gsw->ephy_base + 1, 21, 0x0517);\n\t\t_mt7620_mii_write(gsw, gsw->ephy_base + 1, 22, 0x0fd2);\n\t\t_mt7620_mii_write(gsw, gsw->ephy_base + 1, 23, 0x00bf);\n\t\t_mt7620_mii_write(gsw, gsw->ephy_base + 1, 24, 0x0aab);\n\t\t_mt7620_mii_write(gsw, gsw->ephy_base + 1, 25, 0x00ae);\n\t\t_mt7620_mii_write(gsw, gsw->ephy_base + 1, 26, 0x0fff);\n\t}\n\t/* global page 1 */\n\t_mt7620_mii_write(gsw, gsw->ephy_base + 1, 31, 0x1000);\n\t_mt7620_mii_write(gsw, gsw->ephy_base + 1, 17, 0xe7f8);\n\n\t/* turn on all PHYs */\n\tfor (i = 0; i <= 4; i++) {\n\t\tval = _mt7620_mii_read(gsw, gsw->ephy_base + i, MII_BMCR);\n\t\tval &= ~BMCR_PDOWN;\n\t\tval |= BMCR_ANRESTART | BMCR_ANENABLE | BMCR_SPEED100;\n\t\t_mt7620_mii_write(gsw, gsw->ephy_base + i, MII_BMCR, val);\n\t}\n\n\t/* global page 0 */\n\t_mt7620_mii_write(gsw, gsw->ephy_base + 1, 31, 0x8000);\n\t_mt7620_mii_write(gsw, gsw->ephy_base + 0, 30, 0xa000);\n\t_mt7620_mii_write(gsw, gsw->ephy_base + 1, 30, 0xa000);\n\t_mt7620_mii_write(gsw, gsw->ephy_base + 2, 30, 0xa000);\n\t_mt7620_mii_write(gsw, gsw->ephy_base + 3, 30, 0xa000);\n\n\t_mt7620_mii_write(gsw, gsw->ephy_base + 0, 4, 0x05e1);\n\t_mt7620_mii_write(gsw, gsw->ephy_base + 1, 4, 0x05e1);\n\t_mt7620_mii_write(gsw, gsw->ephy_base + 2, 4, 0x05e1);\n\t_mt7620_mii_write(gsw, gsw->ephy_base + 3, 4, 0x05e1);\n\n\t/* global page 2 */\n\t_mt7620_mii_write(gsw, gsw->ephy_base + 1, 31, 0xa000);\n\t_mt7620_mii_write(gsw, gsw->ephy_base + 0, 16, 0x1111);\n\t_mt7620_mii_write(gsw, gsw->ephy_base + 1, 16, 0x1010);\n\t_mt7620_mii_write(gsw, gsw->ephy_base + 2, 16, 0x1515);\n\t_mt7620_mii_write(gsw, gsw->ephy_base + 3, 16, 0x0f0f);\n\n\t/* CPU Port6 Force Link 1G, FC ON */\n\tmtk_switch_w32(gsw, 0x5e33b, GSW_REG_PORT_PMCR(6));\n\n\t/* Set Port 6 as CPU Port */\n\tmtk_switch_w32(gsw, 0x7f7f7fe0, 0x0010);\n\n\t/* setup port 4 */\n\tif (gsw->port4_ephy) {\n\t\tval = rt_sysc_r32(SYSC_REG_CFG1);\n\n\t\tval |= 3 << 14;\n\t\trt_sysc_w32(val, SYSC_REG_CFG1);\n\t\t_mt7620_mii_write(gsw, gsw->ephy_base + 4, 30, 0xa000);\n\t\t_mt7620_mii_write(gsw, gsw->ephy_base + 4, 4, 0x05e1);\n\t\t_mt7620_mii_write(gsw, gsw->ephy_base + 4, 16, 0x1313);\n\t\tpr_info(\"gsw: setting port4 to ephy mode\\n\");\n\t}\n}\n\nstatic const struct of_device_id mediatek_gsw_match[] = {\n\t{ .compatible = \"mediatek,mt7620-gsw\" },\n\t{},\n};\nMODULE_DEVICE_TABLE(of, mediatek_gsw_match);\n\nint mtk_gsw_init(struct fe_priv *priv)\n{\n\tstruct device_node *eth_node = priv->dev->of_node;\n\tstruct device_node *phy_node, *mdiobus_node;\n\tstruct device_node *np = priv->switch_np;\n\tstruct platform_device *pdev = of_find_device_by_node(np);\n\tstruct mt7620_gsw *gsw;\n\tconst __be32 *id;\n\tu8 val;\n\n\tif (!pdev)\n\t\treturn -ENODEV;\n\n\tif (!of_device_is_compatible(np, mediatek_gsw_match->compatible))\n\t\treturn -EINVAL;\n\n\tgsw = platform_get_drvdata(pdev);\n\tpriv->soc->swpriv = gsw;\n\n\tgsw->ephy_disable = of_property_read_bool(np, \"mediatek,ephy-disable\");\n\n\tmdiobus_node = of_get_child_by_name(eth_node, \"mdio-bus\");\n\tif (mdiobus_node) {\n\t\tfor_each_child_of_node(mdiobus_node, phy_node) {\n\t\t\tid = of_get_property(phy_node, \"reg\", NULL);\n\t\t\tif (id && (be32_to_cpu(*id) == 0x1f))\n\t\t\t\tgsw->ephy_disable = true;\n\t\t}\n\n\t\tof_node_put(mdiobus_node);\n\t}\n\n\tgsw->port4_ephy = !of_property_read_bool(np, \"mediatek,port4-gmac\");\n\n\tif (of_property_read_u8(np, \"mediatek,ephy-base\", &val) == 0)\n\t\tgsw->ephy_base = val;\n\telse\n\t\tgsw->ephy_base = 0;\n\n\tmt7620_hw_init(gsw);\n\n\tif (gsw->irq) {\n\t\trequest_irq(gsw->irq, gsw_interrupt_mt7620, 0,\n\t\t\t    \"gsw\", priv);\n\t\tmtk_switch_w32(gsw, ~PORT_IRQ_ST_CHG, GSW_REG_IMR);\n\t}\n\n\treturn 0;\n}\n\nstatic int mt7620_gsw_probe(struct platform_device *pdev)\n{\n\tstruct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);\n\tstruct mt7620_gsw *gsw;\n\n\tgsw = devm_kzalloc(&pdev->dev, sizeof(struct mt7620_gsw), GFP_KERNEL);\n\tif (!gsw)\n\t\treturn -ENOMEM;\n\n\tgsw->base = devm_ioremap_resource(&pdev->dev, res);\n\tif (IS_ERR(gsw->base))\n\t\treturn PTR_ERR(gsw->base);\n\n\tgsw->dev = &pdev->dev;\n\n\tgsw->irq = platform_get_irq(pdev, 0);\n\n\tplatform_set_drvdata(pdev, gsw);\n\n\treturn 0;\n}\n\nstatic int mt7620_gsw_remove(struct platform_device *pdev)\n{\n\tplatform_set_drvdata(pdev, NULL);\n\n\treturn 0;\n}\n\nstatic struct platform_driver gsw_driver = {\n\t.probe = mt7620_gsw_probe,\n\t.remove = mt7620_gsw_remove,\n\t.driver = {\n\t\t.name = \"mt7620-gsw\",\n\t\t.owner = THIS_MODULE,\n\t\t.of_match_table = mediatek_gsw_match,\n\t},\n};\n\nmodule_platform_driver(gsw_driver);\n\nMODULE_LICENSE(\"GPL\");\nMODULE_AUTHOR(\"John Crispin <blogic@openwrt.org>\");\nMODULE_DESCRIPTION(\"GBit switch driver for Mediatek MT7620 SoC\");\nMODULE_VERSION(MTK_FE_DRV_VERSION);\n"
  },
  {
    "path": "target/linux/ramips/files/drivers/net/ethernet/ralink/gsw_mt7620.h",
    "content": "/*   This program is free software; you can redistribute it and/or modify\n *   it under the terms of the GNU General Public License as published by\n *   the Free Software Foundation; version 2 of the License\n *\n *   This program is distributed in the hope that it will be useful,\n *   but WITHOUT ANY WARRANTY; without even the implied warranty of\n *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n *   GNU General Public License for more details.\n *\n *   Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>\n *   Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>\n *   Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>\n */\n\n#ifndef _RALINK_GSW_MT7620_H__\n#define _RALINK_GSW_MT7620_H__\n\n#define GSW_REG_PHY_TIMEOUT\t(5 * HZ)\n\n#define MT7620A_GSW_REG_PIAC\t0x7004\n\n#define GSW_NUM_VLANS\t\t16\n#define GSW_NUM_VIDS\t\t4096\n#define GSW_NUM_PORTS\t\t7\n#define GSW_PORT6\t\t6\n\n#define GSW_MDIO_ACCESS\t\tBIT(31)\n#define GSW_MDIO_READ\t\tBIT(19)\n#define GSW_MDIO_WRITE\t\tBIT(18)\n#define GSW_MDIO_START\t\tBIT(16)\n#define GSW_MDIO_ADDR_SHIFT\t20\n#define GSW_MDIO_REG_SHIFT\t25\n\n#define GSW_REG_MIB_CNT_EN\t0x4000\n\n#define GSW_REG_PORT_PMCR(x)\t(0x3000 + (x * 0x100))\n#define GSW_REG_PORT_STATUS(x)\t(0x3008 + (x * 0x100))\n#define GSW_REG_SMACCR0\t\t0x3fE4\n#define GSW_REG_SMACCR1\t\t0x3fE8\n#define GSW_REG_CKGCR\t\t0x3ff0\n\n#define GSW_REG_IMR\t\t0x7008\n#define GSW_REG_ISR\t\t0x700c\n#define GSW_REG_GPC1\t\t0x7014\n#define GSW_REG_GPC2\t\t0x701c\n\n#define GSW_REG_GPCx_TXDELAY\tBIT(3)\n#define GSW_REG_GPCx_RXDELAY\tBIT(2)\n\n#define GSW_REG_MAC_P0_MCR\t0x100\n#define GSW_REG_MAC_P1_MCR\t0x200\n\n// Global MAC control register\n#define GSW_REG_GMACCR\t\t0x30E0\n\n#define SYSC_REG_CHIP_REV_ID\t0x0c\n#define SYSC_REG_CFG1\t\t0x14\n#define PCIE_RC_MODE\t\tBIT(8)\n#define SYSC_PAD_RGMII2_MDIO\t0x58\n#define SYSC_GPIO_MODE\t\t0x60\n\n#define PORT_IRQ_ST_CHG\t\t0x7f\n\n#define ESW_PHY_POLLING\t\t0x7000\n\n#define\tPMCR_IPG\t\tBIT(18)\n#define\tPMCR_MAC_MODE\t\tBIT(16)\n#define\tPMCR_FORCE\t\tBIT(15)\n#define\tPMCR_TX_EN\t\tBIT(14)\n#define\tPMCR_RX_EN\t\tBIT(13)\n#define\tPMCR_BACKOFF\t\tBIT(9)\n#define\tPMCR_BACKPRES\t\tBIT(8)\n#define\tPMCR_RX_FC\t\tBIT(5)\n#define\tPMCR_TX_FC\t\tBIT(4)\n#define\tPMCR_SPEED(_x)\t\t(_x << 2)\n#define\tPMCR_DUPLEX\t\tBIT(1)\n#define\tPMCR_LINK\t\tBIT(0)\n\n#define PHY_AN_EN\t\tBIT(31)\n#define PHY_PRE_EN\t\tBIT(30)\n#define PMY_MDC_CONF(_x)\t((_x & 0x3f) << 24)\n\n\nenum {\n\t/* Global attributes. */\n\tGSW_ATTR_ENABLE_VLAN,\n\t/* Port attributes. */\n\tGSW_ATTR_PORT_UNTAG,\n};\n\nstruct mt7620_gsw {\n\tstruct device\t\t*dev;\n\tvoid __iomem\t\t*base;\n\tint\t\t\tirq;\n\tbool\t\t\tephy_disable;\n\tbool\t\t\tport4_ephy;\n\tunsigned long int\tautopoll;\n\tu16\t\t\tephy_base;\n};\n\nvoid mtk_switch_w32(struct mt7620_gsw *gsw, u32 val, unsigned reg);\nu32 mtk_switch_r32(struct mt7620_gsw *gsw, unsigned reg);\nint mtk_gsw_init(struct fe_priv *priv);\n\nint mt7620_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val);\nint mt7620_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg);\nvoid mt7620_mdio_link_adjust(struct fe_priv *priv, int port);\nint mt7620_has_carrier(struct fe_priv *priv);\nvoid mt7620_print_link_state(struct fe_priv *priv, int port, int link,\n\t\t\t     int speed, int duplex);\n\nvoid mt7530_mdio_w32(struct mt7620_gsw *gsw, u32 reg, u32 val);\nu32 mt7530_mdio_r32(struct mt7620_gsw *gsw, u32 reg);\n\nu32 _mt7620_mii_write(struct mt7620_gsw *gsw, u32 phy_addr,\n\t\t\t     u32 phy_register, u32 write_data);\nu32 _mt7620_mii_read(struct mt7620_gsw *gsw, int phy_addr, int phy_reg);\nvoid mt7620_handle_carrier(struct fe_priv *priv);\n\n#endif\n"
  },
  {
    "path": "target/linux/ramips/files/drivers/net/ethernet/ralink/mdio.c",
    "content": "/*   This program is free software; you can redistribute it and/or modify\n *   it under the terms of the GNU General Public License as published by\n *   the Free Software Foundation; version 2 of the License\n *\n *   Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>\n *   Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>\n *   Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>\n */\n\n#include <linux/module.h>\n#include <linux/kernel.h>\n#include <linux/phy.h>\n#include <linux/of_net.h>\n#include <linux/of_mdio.h>\n\n#include \"mtk_eth_soc.h\"\n#include \"mdio.h\"\n\nstatic int fe_mdio_reset(struct mii_bus *bus)\n{\n\t/* TODO */\n\treturn 0;\n}\n\nstatic void fe_phy_link_adjust(struct net_device *dev)\n{\n\tstruct fe_priv *priv = netdev_priv(dev);\n\tunsigned long flags;\n\tint i;\n\n\tspin_lock_irqsave(&priv->phy->lock, flags);\n\tfor (i = 0; i < 8; i++) {\n\t\tif (priv->phy->phy_node[i]) {\n\t\t\tstruct phy_device *phydev = priv->phy->phy[i];\n\t\t\tint status_change = 0;\n\n\t\t\tif (phydev->link)\n\t\t\t\tif (priv->phy->duplex[i] != phydev->duplex ||\n\t\t\t\t    priv->phy->speed[i] != phydev->speed)\n\t\t\t\t\tstatus_change = 1;\n\n\t\t\tif (phydev->link != priv->link[i])\n\t\t\t\tstatus_change = 1;\n\n\t\t\tswitch (phydev->speed) {\n\t\t\tcase SPEED_1000:\n\t\t\tcase SPEED_100:\n\t\t\tcase SPEED_10:\n\t\t\t\tpriv->link[i] = phydev->link;\n\t\t\t\tpriv->phy->duplex[i] = phydev->duplex;\n\t\t\t\tpriv->phy->speed[i] = phydev->speed;\n\n\t\t\t\tif (status_change &&\n\t\t\t\t    priv->soc->mdio_adjust_link)\n\t\t\t\t\tpriv->soc->mdio_adjust_link(priv, i);\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t}\n\tspin_unlock_irqrestore(&priv->phy->lock, flags);\n}\n\nint fe_connect_phy_node(struct fe_priv *priv, struct device_node *phy_node, int port)\n{\n\tconst __be32 *_phy_addr = NULL;\n\tstruct phy_device *phydev;\n#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0)\n\tint phy_mode;\n#else\n\tphy_interface_t phy_mode = PHY_INTERFACE_MODE_NA;\n#endif\n\n\t_phy_addr = of_get_property(phy_node, \"reg\", NULL);\n\n\tif (!_phy_addr || (be32_to_cpu(*_phy_addr) >= 0x20)) {\n\t\tpr_err(\"%s: invalid phy id\\n\", phy_node->name);\n\t\treturn -EINVAL;\n\t}\n\n#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0)\n\tphy_mode = of_get_phy_mode(phy_node);\n\tif (phy_mode < 0) {\n#else\n\tof_get_phy_mode(phy_node, &phy_mode);\n\tif (phy_mode == PHY_INTERFACE_MODE_NA) {\n#endif\n\t\tdev_err(priv->dev, \"incorrect phy-mode %d\\n\", phy_mode);\n\t\tpriv->phy->phy_node[port] = NULL;\n\t\treturn -EINVAL;\n\t}\n\n\tphydev = of_phy_connect(priv->netdev, phy_node, fe_phy_link_adjust,\n\t\t\t\t0, phy_mode);\n\tif (!phydev) {\n\t\tdev_err(priv->dev, \"could not connect to PHY\\n\");\n\t\tpriv->phy->phy_node[port] = NULL;\n\t\treturn -ENODEV;\n\t}\n\n\tphy_set_max_speed(phydev, SPEED_1000);\n\tlinkmode_copy(phydev->advertising, phydev->supported);\n\tphydev->no_auto_carrier_off = 1;\n\n\tdev_info(priv->dev,\n\t\t \"connected port %d to PHY at %s [uid=%08x, driver=%s]\\n\",\n\t\t port, dev_name(&phydev->mdio.dev), phydev->phy_id,\n\t\t phydev->drv->name);\n\n\tpriv->phy->phy[port] = phydev;\n\tpriv->link[port] = 0;\n\n\treturn 0;\n}\n\nstatic void phy_init(struct fe_priv *priv, struct phy_device *phy)\n{\n\tphy_attach(priv->netdev, dev_name(&phy->mdio.dev), PHY_INTERFACE_MODE_MII);\n\n\tphy->autoneg = AUTONEG_ENABLE;\n\tphy->speed = 0;\n\tphy->duplex = 0;\n\n\tphy_set_max_speed(phy, IS_ENABLED(CONFIG_NET_RALINK_MDIO_MT7620) ?\n\t\t\t\t       SPEED_1000 :\n\t\t\t\t       SPEED_100);\n\tlinkmode_copy(phy->advertising, phy->supported);\n\tlinkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phy->advertising);\n\n\tphy_start_aneg(phy);\n}\n\nstatic int fe_phy_connect(struct fe_priv *priv)\n{\n\tint i;\n\n\tfor (i = 0; i < 8; i++) {\n\t\tif (priv->phy->phy_node[i]) {\n\t\t\tif (!priv->phy_dev) {\n\t\t\t\tpriv->phy_dev = priv->phy->phy[i];\n\t\t\t\tpriv->phy_flags = FE_PHY_FLAG_PORT;\n\t\t\t}\n\t\t} else if (priv->mii_bus) {\n\t\t\tstruct phy_device *phydev;\n\n\t\t\tphydev = mdiobus_get_phy(priv->mii_bus, i);\n\t\t\tif (!phydev || phydev->attached_dev)\n\t\t\t\tcontinue;\n\n\t\t\tphy_init(priv, phydev);\n\t\t\tif (!priv->phy_dev) {\n\t\t\t\tpriv->phy_dev = mdiobus_get_phy(priv->mii_bus, i);\n\t\t\t\tpriv->phy_flags = FE_PHY_FLAG_ATTACH;\n\t\t\t}\n\t\t}\n\t}\n\n\treturn 0;\n}\n\nstatic void fe_phy_disconnect(struct fe_priv *priv)\n{\n\tunsigned long flags;\n\tint i;\n\n\tfor (i = 0; i < 8; i++)\n\t\tif (priv->phy->phy_fixed[i]) {\n\t\t\tspin_lock_irqsave(&priv->phy->lock, flags);\n\t\t\tpriv->link[i] = 0;\n\t\t\tif (priv->soc->mdio_adjust_link)\n\t\t\t\tpriv->soc->mdio_adjust_link(priv, i);\n\t\t\tspin_unlock_irqrestore(&priv->phy->lock, flags);\n\t\t} else if (priv->phy->phy[i]) {\n\t\t\tphy_disconnect(priv->phy->phy[i]);\n\t\t} else if (priv->mii_bus && mdiobus_get_phy(priv->mii_bus, i)) {\n\t\t\tphy_detach(mdiobus_get_phy(priv->mii_bus, i));\n\t\t}\n}\n\nstatic void fe_phy_start(struct fe_priv *priv)\n{\n\tunsigned long flags;\n\tint i;\n\n\tfor (i = 0; i < 8; i++) {\n\t\tif (priv->phy->phy_fixed[i]) {\n\t\t\tspin_lock_irqsave(&priv->phy->lock, flags);\n\t\t\tpriv->link[i] = 1;\n\t\t\tif (priv->soc->mdio_adjust_link)\n\t\t\t\tpriv->soc->mdio_adjust_link(priv, i);\n\t\t\tspin_unlock_irqrestore(&priv->phy->lock, flags);\n\t\t} else if (priv->phy->phy[i]) {\n\t\t\tphy_start(priv->phy->phy[i]);\n\t\t}\n\t}\n}\n\nstatic void fe_phy_stop(struct fe_priv *priv)\n{\n\tunsigned long flags;\n\tint i;\n\n\tfor (i = 0; i < 8; i++)\n\t\tif (priv->phy->phy_fixed[i]) {\n\t\t\tspin_lock_irqsave(&priv->phy->lock, flags);\n\t\t\tpriv->link[i] = 0;\n\t\t\tif (priv->soc->mdio_adjust_link)\n\t\t\t\tpriv->soc->mdio_adjust_link(priv, i);\n\t\t\tspin_unlock_irqrestore(&priv->phy->lock, flags);\n\t\t} else if (priv->phy->phy[i]) {\n\t\t\tphy_stop(priv->phy->phy[i]);\n\t\t}\n}\n\nstatic struct fe_phy phy_ralink = {\n\t.connect = fe_phy_connect,\n\t.disconnect = fe_phy_disconnect,\n\t.start = fe_phy_start,\n\t.stop = fe_phy_stop,\n};\n\nint fe_mdio_init(struct fe_priv *priv)\n{\n\tstruct device_node *mii_np;\n\tint err;\n\n\tif (!priv->soc->mdio_read || !priv->soc->mdio_write)\n\t\treturn 0;\n\n\tspin_lock_init(&phy_ralink.lock);\n\tpriv->phy = &phy_ralink;\n\n\tmii_np = of_get_child_by_name(priv->dev->of_node, \"mdio-bus\");\n\tif (!mii_np) {\n\t\tdev_err(priv->dev, \"no %s child node found\", \"mdio-bus\");\n\t\terr = 0;\n\t\tgoto err_no_bus;\n\t}\n\n\tif (!of_device_is_available(mii_np)) {\n\t\terr = 0;\n\t\tgoto err_put_node;\n\t}\n\n\tpriv->mii_bus = mdiobus_alloc();\n\tif (!priv->mii_bus) {\n\t\terr = -ENOMEM;\n\t\tgoto err_put_node;\n\t}\n\n\tpriv->mii_bus->name = \"mdio\";\n\tpriv->mii_bus->read = priv->soc->mdio_read;\n\tpriv->mii_bus->write = priv->soc->mdio_write;\n\tpriv->mii_bus->reset = fe_mdio_reset;\n\tpriv->mii_bus->priv = priv;\n\tpriv->mii_bus->parent = priv->dev;\n\n\tsnprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, \"%s\", mii_np->name);\n\terr = of_mdiobus_register(priv->mii_bus, mii_np);\n\tif (err)\n\t\tgoto err_free_bus;\n\n\treturn 0;\n\nerr_free_bus:\n\tkfree(priv->mii_bus);\nerr_put_node:\n\tof_node_put(mii_np);\nerr_no_bus:\n\tdev_err(priv->dev, \"%s disabled\", \"mdio-bus\");\n\tpriv->mii_bus = NULL;\n\treturn err;\n}\n\nvoid fe_mdio_cleanup(struct fe_priv *priv)\n{\n\tif (!priv->mii_bus)\n\t\treturn;\n\n\tmdiobus_unregister(priv->mii_bus);\n\tof_node_put(priv->mii_bus->dev.of_node);\n\tkfree(priv->mii_bus);\n}\n"
  },
  {
    "path": "target/linux/ramips/files/drivers/net/ethernet/ralink/mdio.h",
    "content": "/*   This program is free software; you can redistribute it and/or modify\n *   it under the terms of the GNU General Public License as published by\n *   the Free Software Foundation; version 2 of the License\n *\n *   This program is distributed in the hope that it will be useful,\n *   but WITHOUT ANY WARRANTY; without even the implied warranty of\n *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n *   GNU General Public License for more details.\n *\n *   Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>\n *   Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>\n *   Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>\n */\n\n#ifndef _RALINK_MDIO_H__\n#define _RALINK_MDIO_H__\n\n#ifdef CONFIG_NET_RALINK_MDIO\nint fe_mdio_init(struct fe_priv *priv);\nvoid fe_mdio_cleanup(struct fe_priv *priv);\nint fe_connect_phy_node(struct fe_priv *priv,\n\t\t\tstruct device_node *phy_node,\n\t\t\tint port);\n#else\nstatic inline int fe_mdio_init(struct fe_priv *priv) { return 0; }\nstatic inline void fe_mdio_cleanup(struct fe_priv *priv) {}\n#endif\n#endif\n"
  },
  {
    "path": "target/linux/ramips/files/drivers/net/ethernet/ralink/mdio_mt7620.c",
    "content": "/*   This program is free software; you can redistribute it and/or modify\n *   it under the terms of the GNU General Public License as published by\n *   the Free Software Foundation; version 2 of the License\n *\n *   This program is distributed in the hope that it will be useful,\n *   but WITHOUT ANY WARRANTY; without even the implied warranty of\n *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n *   GNU General Public License for more details.\n *\n *   Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>\n *   Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>\n *   Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>\n */\n\n#include <linux/module.h>\n#include <linux/kernel.h>\n#include <linux/types.h>\n\n#include \"mtk_eth_soc.h\"\n#include \"gsw_mt7620.h\"\n#include \"mdio.h\"\n\nstatic int mt7620_mii_busy_wait(struct mt7620_gsw *gsw)\n{\n\tunsigned long t_start = jiffies;\n\n\twhile (1) {\n\t\tif (!(mtk_switch_r32(gsw, MT7620A_GSW_REG_PIAC) & GSW_MDIO_ACCESS))\n\t\t\treturn 0;\n\t\tif (time_after(jiffies, t_start + GSW_REG_PHY_TIMEOUT))\n\t\t\tbreak;\n\t}\n\n\tdev_err(gsw->dev, \"mdio: MDIO timeout\\n\");\n\treturn -1;\n}\n\nu32 _mt7620_mii_write(struct mt7620_gsw *gsw, u32 phy_addr,\n\t\t\t     u32 phy_register, u32 write_data)\n{\n\tif (mt7620_mii_busy_wait(gsw))\n\t\treturn -1;\n\n\twrite_data &= 0xffff;\n\n\tmtk_switch_w32(gsw, GSW_MDIO_ACCESS | GSW_MDIO_START | GSW_MDIO_WRITE |\n\t\t(phy_register << GSW_MDIO_REG_SHIFT) |\n\t\t(phy_addr << GSW_MDIO_ADDR_SHIFT) | write_data,\n\t\tMT7620A_GSW_REG_PIAC);\n\n\tif (mt7620_mii_busy_wait(gsw))\n\t\treturn -1;\n\n\treturn 0;\n}\n\nu32 _mt7620_mii_read(struct mt7620_gsw *gsw, int phy_addr, int phy_reg)\n{\n\tu32 d;\n\n\tif (mt7620_mii_busy_wait(gsw))\n\t\treturn 0xffff;\n\n\tmtk_switch_w32(gsw, GSW_MDIO_ACCESS | GSW_MDIO_START | GSW_MDIO_READ |\n\t\t(phy_reg << GSW_MDIO_REG_SHIFT) |\n\t\t(phy_addr << GSW_MDIO_ADDR_SHIFT),\n\t\tMT7620A_GSW_REG_PIAC);\n\n\tif (mt7620_mii_busy_wait(gsw))\n\t\treturn 0xffff;\n\n\td = mtk_switch_r32(gsw, MT7620A_GSW_REG_PIAC) & 0xffff;\n\n\treturn d;\n}\n\nint mt7620_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val)\n{\n\tstruct fe_priv *priv = bus->priv;\n\tstruct mt7620_gsw *gsw = (struct mt7620_gsw *)priv->soc->swpriv;\n\n\treturn _mt7620_mii_write(gsw, phy_addr, phy_reg, val);\n}\n\nint mt7620_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg)\n{\n\tstruct fe_priv *priv = bus->priv;\n\tstruct mt7620_gsw *gsw = (struct mt7620_gsw *)priv->soc->swpriv;\n\n\treturn _mt7620_mii_read(gsw, phy_addr, phy_reg);\n}\n\nvoid mt7530_mdio_w32(struct mt7620_gsw *gsw, u32 reg, u32 val)\n{\n\t_mt7620_mii_write(gsw, 0x1f, 0x1f, (reg >> 6) & 0x3ff);\n\t_mt7620_mii_write(gsw, 0x1f, (reg >> 2) & 0xf,  val & 0xffff);\n\t_mt7620_mii_write(gsw, 0x1f, 0x10, val >> 16);\n}\n\nu32 mt7530_mdio_r32(struct mt7620_gsw *gsw, u32 reg)\n{\n\tu16 high, low;\n\n\t_mt7620_mii_write(gsw, 0x1f, 0x1f, (reg >> 6) & 0x3ff);\n\tlow = _mt7620_mii_read(gsw, 0x1f, (reg >> 2) & 0xf);\n\thigh = _mt7620_mii_read(gsw, 0x1f, 0x10);\n\n\treturn (high << 16) | (low & 0xffff);\n}\n\nstatic unsigned char *fe_speed_str(int speed)\n{\n\tswitch (speed) {\n\tcase 2:\n\tcase SPEED_1000:\n\t\treturn \"1000\";\n\tcase 1:\n\tcase SPEED_100:\n\t\treturn \"100\";\n\tcase 0:\n\tcase SPEED_10:\n\t\treturn \"10\";\n\t}\n\n\treturn \"? \";\n}\n\nint mt7620_has_carrier(struct fe_priv *priv)\n{\n\tstruct mt7620_gsw *gsw = (struct mt7620_gsw *)priv->soc->swpriv;\n\tint i;\n\n\tfor (i = 0; i < GSW_PORT6; i++)\n\t\tif (mtk_switch_r32(gsw, GSW_REG_PORT_STATUS(i)) & 0x1)\n\t\t\treturn 1;\n\treturn 0;\n}\n\n\nvoid mt7620_handle_carrier(struct fe_priv *priv)\n{\n\tif (!priv->phy)\n\t\treturn;\n\n\tif (mt7620_has_carrier(priv))\n\t\tnetif_carrier_on(priv->netdev);\n\telse\n\t\tnetif_carrier_off(priv->netdev);\n}\n\nvoid mt7620_print_link_state(struct fe_priv *priv, int port, int link,\n\t\t\t     int speed, int duplex)\n{\n\tif (link)\n\t\tnetdev_info(priv->netdev, \"port %d link up (%sMbps/%s duplex)\\n\",\n\t\t\t    port, fe_speed_str(speed),\n\t\t\t    (duplex) ? \"Full\" : \"Half\");\n\telse\n\t\tnetdev_info(priv->netdev, \"port %d link down\\n\", port);\n}\n\nvoid mt7620_mdio_link_adjust(struct fe_priv *priv, int port)\n{\n\tmt7620_print_link_state(priv, port, priv->link[port],\n\t\t\t\tpriv->phy->speed[port],\n\t\t\t\t(priv->phy->duplex[port] == DUPLEX_FULL));\n\tmt7620_handle_carrier(priv);\n}\n"
  },
  {
    "path": "target/linux/ramips/files/drivers/net/ethernet/ralink/mdio_rt2880.c",
    "content": "/*   This program is free software; you can redistribute it and/or modify\n *   it under the terms of the GNU General Public License as published by\n *   the Free Software Foundation; version 2 of the License\n *\n *   This program is distributed in the hope that it will be useful,\n *   but WITHOUT ANY WARRANTY; without even the implied warranty of\n *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n *   GNU General Public License for more details.\n *\n *   Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>\n *   Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>\n *   Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>\n */\n\n#include <linux/module.h>\n#include <linux/kernel.h>\n#include <linux/types.h>\n#include <linux/of_net.h>\n#include <linux/of_mdio.h>\n\n#include \"mtk_eth_soc.h\"\n#include \"mdio_rt2880.h\"\n#include \"mdio.h\"\n\n#define FE_MDIO_RETRY\t1000\n\nstatic unsigned char *rt2880_speed_str(struct fe_priv *priv)\n{\n\tswitch (priv->phy->speed[0]) {\n\tcase SPEED_1000:\n\t\treturn \"1000\";\n\tcase SPEED_100:\n\t\treturn \"100\";\n\tcase SPEED_10:\n\t\treturn \"10\";\n\t}\n\n\treturn \"?\";\n}\n\nvoid rt2880_mdio_link_adjust(struct fe_priv *priv, int port)\n{\n\tu32 mdio_cfg;\n\n\tif (!priv->link[0]) {\n\t\tnetif_carrier_off(priv->netdev);\n\t\tnetdev_info(priv->netdev, \"link down\\n\");\n\t\treturn;\n\t}\n\n\tmdio_cfg = FE_MDIO_CFG_TX_CLK_SKEW_200 |\n\t\t   FE_MDIO_CFG_RX_CLK_SKEW_200 |\n\t\t   FE_MDIO_CFG_GP1_FRC_EN;\n\n\tif (priv->phy->duplex[0] == DUPLEX_FULL)\n\t\tmdio_cfg |= FE_MDIO_CFG_GP1_DUPLEX;\n\n\tif (priv->phy->tx_fc[0])\n\t\tmdio_cfg |= FE_MDIO_CFG_GP1_FC_TX;\n\n\tif (priv->phy->rx_fc[0])\n\t\tmdio_cfg |= FE_MDIO_CFG_GP1_FC_RX;\n\n\tswitch (priv->phy->speed[0]) {\n\tcase SPEED_10:\n\t\tmdio_cfg |= FE_MDIO_CFG_GP1_SPEED_10;\n\t\tbreak;\n\tcase SPEED_100:\n\t\tmdio_cfg |= FE_MDIO_CFG_GP1_SPEED_100;\n\t\tbreak;\n\tcase SPEED_1000:\n\t\tmdio_cfg |= FE_MDIO_CFG_GP1_SPEED_1000;\n\t\tbreak;\n\tdefault:\n\t\tBUG();\n\t}\n\n\tfe_w32(mdio_cfg, FE_MDIO_CFG);\n\n\tnetif_carrier_on(priv->netdev);\n\tnetdev_info(priv->netdev, \"link up (%sMbps/%s duplex)\\n\",\n\t\t    rt2880_speed_str(priv),\n\t\t    (priv->phy->duplex[0] == DUPLEX_FULL) ? \"Full\" : \"Half\");\n}\n\nstatic int rt2880_mdio_wait_ready(struct fe_priv *priv)\n{\n\tint retries;\n\n\tretries = FE_MDIO_RETRY;\n\twhile (1) {\n\t\tu32 t;\n\n\t\tt = fe_r32(FE_MDIO_ACCESS);\n\t\tif ((t & BIT(31)) == 0)\n\t\t\treturn 0;\n\n\t\tif (retries-- == 0)\n\t\t\tbreak;\n\n\t\tudelay(1);\n\t}\n\n\tdev_err(priv->dev, \"MDIO operation timed out\\n\");\n\treturn -ETIMEDOUT;\n}\n\nint rt2880_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg)\n{\n\tstruct fe_priv *priv = bus->priv;\n\tint err;\n\tu32 t;\n\n\terr = rt2880_mdio_wait_ready(priv);\n\tif (err)\n\t\treturn 0xffff;\n\n\tt = (phy_addr << 24) | (phy_reg << 16);\n\tfe_w32(t, FE_MDIO_ACCESS);\n\tt |= BIT(31);\n\tfe_w32(t, FE_MDIO_ACCESS);\n\n\terr = rt2880_mdio_wait_ready(priv);\n\tif (err)\n\t\treturn 0xffff;\n\n\tpr_debug(\"%s: addr=%04x, reg=%04x, value=%04x\\n\", __func__,\n\t\t phy_addr, phy_reg, fe_r32(FE_MDIO_ACCESS) & 0xffff);\n\n\treturn fe_r32(FE_MDIO_ACCESS) & 0xffff;\n}\n\nint rt2880_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val)\n{\n\tstruct fe_priv *priv = bus->priv;\n\tint err;\n\tu32 t;\n\n\tpr_debug(\"%s: addr=%04x, reg=%04x, value=%04x\\n\", __func__,\n\t\t phy_addr, phy_reg, fe_r32(FE_MDIO_ACCESS) & 0xffff);\n\n\terr = rt2880_mdio_wait_ready(priv);\n\tif (err)\n\t\treturn err;\n\n\tt = (1 << 30) | (phy_addr << 24) | (phy_reg << 16) | val;\n\tfe_w32(t, FE_MDIO_ACCESS);\n\tt |= BIT(31);\n\tfe_w32(t, FE_MDIO_ACCESS);\n\n\treturn rt2880_mdio_wait_ready(priv);\n}\n\nvoid rt2880_port_init(struct fe_priv *priv, struct device_node *np)\n{\n\tconst __be32 *id = of_get_property(np, \"reg\", NULL);\n\tconst __be32 *link;\n\tint size;\n#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0)\n\tint phy_mode;\n#else\n\tphy_interface_t phy_mode = PHY_INTERFACE_MODE_NA;\n#endif\n\n\tif (!id || (be32_to_cpu(*id) != 0)) {\n\t\tpr_err(\"%s: invalid port id\\n\", np->name);\n\t\treturn;\n\t}\n\n\tpriv->phy->phy_fixed[0] = of_get_property(np,\n\t\t\t\t\t\t  \"mediatek,fixed-link\", &size);\n\tif (priv->phy->phy_fixed[0] &&\n\t    (size != (4 * sizeof(*priv->phy->phy_fixed[0])))) {\n\t\tpr_err(\"%s: invalid fixed link property\\n\", np->name);\n\t\tpriv->phy->phy_fixed[0] = NULL;\n\t\treturn;\n\t}\n\n#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0)\n\tphy_mode = of_get_phy_mode(np);\n#else\n\tof_get_phy_mode(np, &phy_mode);\n#endif\n\tswitch (phy_mode) {\n\tcase PHY_INTERFACE_MODE_RGMII:\n\t\tbreak;\n\tcase PHY_INTERFACE_MODE_MII:\n\t\tbreak;\n\tcase PHY_INTERFACE_MODE_RMII:\n\t\tbreak;\n\tdefault:\n\t\tif (!priv->phy->phy_fixed[0])\n\t\t\tdev_err(priv->dev, \"port %d - invalid phy mode\\n\",\n\t\t\t\tpriv->phy->speed[0]);\n\t\tbreak;\n\t}\n\n\tpriv->phy->phy_node[0] = of_parse_phandle(np, \"phy-handle\", 0);\n\tif (!priv->phy->phy_node[0] && !priv->phy->phy_fixed[0])\n\t\treturn;\n\n\tif (priv->phy->phy_fixed[0]) {\n\t\tlink = priv->phy->phy_fixed[0];\n\t\tpriv->phy->speed[0] = be32_to_cpup(link++);\n\t\tpriv->phy->duplex[0] = be32_to_cpup(link++);\n\t\tpriv->phy->tx_fc[0] = be32_to_cpup(link++);\n\t\tpriv->phy->rx_fc[0] = be32_to_cpup(link++);\n\n\t\tpriv->link[0] = 1;\n\t\tswitch (priv->phy->speed[0]) {\n\t\tcase SPEED_10:\n\t\t\tbreak;\n\t\tcase SPEED_100:\n\t\t\tbreak;\n\t\tcase SPEED_1000:\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tdev_err(priv->dev, \"invalid link speed: %d\\n\",\n\t\t\t\tpriv->phy->speed[0]);\n\t\t\tpriv->phy->phy_fixed[0] = 0;\n\t\t\treturn;\n\t\t}\n\t\tdev_info(priv->dev, \"using fixed link parameters\\n\");\n\t\trt2880_mdio_link_adjust(priv, 0);\n\t\treturn;\n\t}\n\n\tif (priv->phy->phy_node[0] && mdiobus_get_phy(priv->mii_bus, 0))\n\t\tfe_connect_phy_node(priv, priv->phy->phy_node[0], 0);\n}\n"
  },
  {
    "path": "target/linux/ramips/files/drivers/net/ethernet/ralink/mdio_rt2880.h",
    "content": "/*   This program is free software; you can redistribute it and/or modify\n *   it under the terms of the GNU General Public License as published by\n *   the Free Software Foundation; version 2 of the License\n *\n *   This program is distributed in the hope that it will be useful,\n *   but WITHOUT ANY WARRANTY; without even the implied warranty of\n *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n *   GNU General Public License for more details.\n *\n *   Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>\n *   Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>\n *   Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>\n */\n\n#ifndef _RALINK_MDIO_RT2880_H__\n#define _RALINK_MDIO_RT2880_H__\n\nvoid rt2880_mdio_link_adjust(struct fe_priv *priv, int port);\nint rt2880_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg);\nint rt2880_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val);\nvoid rt2880_port_init(struct fe_priv *priv, struct device_node *np);\n\n#endif\n"
  },
  {
    "path": "target/linux/ramips/files/drivers/net/ethernet/ralink/mt7530.c",
    "content": "/*\n * This program is free software; you can redistribute it and/or\n * modify it under the terms of the GNU General Public License\n * as published by the Free Software Foundation; either version 2\n * of the License, or (at your option) any later version.\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n * GNU General Public License for more details.\n *\n * Copyright (C) 2013 John Crispin <blogic@openwrt.org>\n * Copyright (C) 2016 Vitaly Chekryzhev <13hakta@gmail.com>\n */\n\n#include <linux/if.h>\n#include <linux/module.h>\n#include <linux/init.h>\n#include <linux/list.h>\n#include <linux/if_ether.h>\n#include <linux/skbuff.h>\n#include <linux/netdevice.h>\n#include <linux/netlink.h>\n#include <linux/bitops.h>\n#include <net/genetlink.h>\n#include <linux/switch.h>\n#include <linux/delay.h>\n#include <linux/phy.h>\n#include <linux/netdevice.h>\n#include <linux/etherdevice.h>\n#include <linux/lockdep.h>\n#include <linux/workqueue.h>\n#include <linux/of_device.h>\n#include <asm/byteorder.h>\n\n#include \"mt7530.h\"\n\n#define MT7530_CPU_PORT\t\t6\n#define MT7530_NUM_PORTS\t8\n#define MT7530_NUM_VLANS\t16\n#define MT7530_MAX_VID\t\t4095\n#define MT7530_MIN_VID\t\t0\n#define MT7530_NUM_ARL_RECORDS 2048\n#define ARL_LINE_LENGTH\t\t30\n\n#define MT7530_PORT_MIB_TXB_ID\t2\t/* TxGOC */\n#define MT7530_PORT_MIB_RXB_ID\t6\t/* RxGOC */\n\n/* registers */\n#define REG_ESW_WT_MAC_MFC\t\t0x10\n\n#define REG_ESW_WT_MAC_MFC_MIRROR_ENABLE\tBIT(3)\n#define REG_ESW_WT_MAC_MFC_MIRROR_DEST_MASK\t0x07\n\n#define REG_ESW_VLAN_VTCR\t\t0x90\n#define REG_ESW_VLAN_VAWD1\t\t0x94\n#define REG_ESW_VLAN_VAWD2\t\t0x98\n#define REG_ESW_VLAN_VTIM(x)\t(0x100 + 4 * ((x) / 2))\n\n#define REG_ESW_WT_MAC_ATC  0x80\n#define REG_ESW_TABLE_ATRD  0x8C\n#define REG_ESW_TABLE_TSRA1 0x84\n#define REG_ESW_TABLE_TSRA2 0x88\n\n#define REG_MAC_ATC_START  0x8004\n#define REG_MAC_ATC_NEXT   0x8005\n\n#define REG_MAC_ATC_BUSY      0x8000U\n#define REG_MAC_ATC_SRCH_HIT  0x2000U\n#define REG_MAC_ATC_SRCH_END  0x4000U\n#define REG_ATRD_VALID        0xff000000U\n#define REG_ATRD_PORT_MASK    0xff0U\n\n#define REG_ESW_VLAN_VAWD1_IVL_MAC\tBIT(30)\n#define REG_ESW_VLAN_VAWD1_VTAG_EN\tBIT(28)\n#define REG_ESW_VLAN_VAWD1_VALID\tBIT(0)\n\n/* vlan egress mode */\nenum {\n\tETAG_CTRL_UNTAG\t= 0,\n\tETAG_CTRL_TAG\t= 2,\n\tETAG_CTRL_SWAP\t= 1,\n\tETAG_CTRL_STACK\t= 3,\n};\n\n#define REG_ESW_PORT_PCR(x)\t(0x2004 | ((x) << 8))\n#define REG_ESW_PORT_PVC(x)\t(0x2010 | ((x) << 8))\n#define REG_ESW_PORT_PPBV1(x)\t(0x2014 | ((x) << 8))\n\n#define REG_ESW_PORT_PCR_MIRROR_SRC_RX_BIT\tBIT(8)\n#define REG_ESW_PORT_PCR_MIRROR_SRC_TX_BIT\tBIT(9)\n#define REG_ESW_PORT_PCR_MIRROR_SRC_RX_MASK\t0x0100\n#define REG_ESW_PORT_PCR_MIRROR_SRC_TX_MASK\t0x0200\n\n#define REG_HWTRAP\t\t0x7804\n\n#define MIB_DESC(_s , _o, _n)   \\\n\t{                       \\\n\t\t.size = (_s),   \\\n\t\t.offset = (_o), \\\n\t\t.name = (_n),   \\\n\t}\n\nstruct mt7xxx_mib_desc {\n\tunsigned int size;\n\tunsigned int offset;\n\tconst char *name;\n};\n\nstatic const struct mt7xxx_mib_desc mt7620_mibs[] = {\n\tMIB_DESC(1, MT7620_MIB_STATS_PPE_AC_BCNT0, \"PPE_AC_BCNT0\"),\n\tMIB_DESC(1, MT7620_MIB_STATS_PPE_AC_PCNT0, \"PPE_AC_PCNT0\"),\n\tMIB_DESC(1, MT7620_MIB_STATS_PPE_AC_BCNT63, \"PPE_AC_BCNT63\"),\n\tMIB_DESC(1, MT7620_MIB_STATS_PPE_AC_PCNT63, \"PPE_AC_PCNT63\"),\n\tMIB_DESC(1, MT7620_MIB_STATS_PPE_MTR_CNT0, \"PPE_MTR_CNT0\"),\n\tMIB_DESC(1, MT7620_MIB_STATS_PPE_MTR_CNT63, \"PPE_MTR_CNT63\"),\n\tMIB_DESC(1, MT7620_MIB_STATS_GDM1_TX_GBCNT, \"GDM1_TX_GBCNT\"),\n\tMIB_DESC(1, MT7620_MIB_STATS_GDM1_TX_GPCNT, \"GDM1_TX_GPCNT\"),\n\tMIB_DESC(1, MT7620_MIB_STATS_GDM1_TX_SKIPCNT, \"GDM1_TX_SKIPCNT\"),\n\tMIB_DESC(1, MT7620_MIB_STATS_GDM1_TX_COLCNT, \"GDM1_TX_COLCNT\"),\n\tMIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_GBCNT1, \"GDM1_RX_GBCNT1\"),\n\tMIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_GPCNT1, \"GDM1_RX_GPCNT1\"),\n\tMIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_OERCNT, \"GDM1_RX_OERCNT\"),\n\tMIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_FERCNT, \"GDM1_RX_FERCNT\"),\n\tMIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_SERCNT, \"GDM1_RX_SERCNT\"),\n\tMIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_LERCNT, \"GDM1_RX_LERCNT\"),\n\tMIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_CERCNT, \"GDM1_RX_CERCNT\"),\n\tMIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_FCCNT, \"GDM1_RX_FCCNT\"),\n\tMIB_DESC(1, MT7620_MIB_STATS_GDM2_TX_GBCNT, \"GDM2_TX_GBCNT\"),\n\tMIB_DESC(1, MT7620_MIB_STATS_GDM2_TX_GPCNT, \"GDM2_TX_GPCNT\"),\n\tMIB_DESC(1, MT7620_MIB_STATS_GDM2_TX_SKIPCNT, \"GDM2_TX_SKIPCNT\"),\n\tMIB_DESC(1, MT7620_MIB_STATS_GDM2_TX_COLCNT, \"GDM2_TX_COLCNT\"),\n\tMIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_GBCNT, \"GDM2_RX_GBCNT\"),\n\tMIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_GPCNT, \"GDM2_RX_GPCNT\"),\n\tMIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_OERCNT, \"GDM2_RX_OERCNT\"),\n\tMIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_FERCNT, \"GDM2_RX_FERCNT\"),\n\tMIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_SERCNT, \"GDM2_RX_SERCNT\"),\n\tMIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_LERCNT, \"GDM2_RX_LERCNT\"),\n\tMIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_CERCNT, \"GDM2_RX_CERCNT\"),\n\tMIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_FCCNT, \"GDM2_RX_FCCNT\")\n};\n\nstatic const struct mt7xxx_mib_desc mt7620_port_mibs[] = {\n\tMIB_DESC(1, MT7620_MIB_STATS_PORT_TGPCN,  \"TxGPC\"),\n\tMIB_DESC(1, MT7620_MIB_STATS_PORT_TBOCN,  \"TxBOC\"),\n\tMIB_DESC(1, MT7620_MIB_STATS_PORT_TGOCN,  \"TxGOC\"),\n\tMIB_DESC(1, MT7620_MIB_STATS_PORT_TEPCN,  \"TxEPC\"),\n\tMIB_DESC(1, MT7620_MIB_STATS_PORT_RGPCN,  \"RxGPC\"),\n\tMIB_DESC(1, MT7620_MIB_STATS_PORT_RBOCN,  \"RxBOC\"),\n\tMIB_DESC(1, MT7620_MIB_STATS_PORT_RGOCN,  \"RxGOC\"),\n\tMIB_DESC(1, MT7620_MIB_STATS_PORT_REPC1N, \"RxEPC1\"),\n\tMIB_DESC(1, MT7620_MIB_STATS_PORT_REPC2N, \"RxEPC2\")\n};\n\nenum {\n\t/* Global attributes. */\n\tMT7530_ATTR_ENABLE_VLAN,\n};\n\nstruct mt7530_port_entry {\n\tu16\tpvid;\n\tbool\tmirror_rx;\n\tbool\tmirror_tx;\n};\n\nstruct mt7530_vlan_entry {\n\tu16\tvid;\n\tu8\tmember;\n\tu8\tetags;\n};\n\nstruct mt7530_priv {\n\tvoid __iomem\t\t*base;\n\tstruct mii_bus\t\t*bus;\n\tstruct switch_dev\tswdev;\n\n\tu8\t\t\tmirror_dest_port;\n\tbool\t\t\tglobal_vlan_enable;\n\tstruct mt7530_vlan_entry\tvlan_entries[MT7530_NUM_VLANS];\n\tstruct mt7530_port_entry\tport_entries[MT7530_NUM_PORTS];\n\tchar arl_buf[MT7530_NUM_ARL_RECORDS * ARL_LINE_LENGTH + 1];\n};\n\nstruct mt7530_mapping {\n\tchar\t*name;\n\tu16\tpvids[MT7530_NUM_PORTS];\n\tu8\tmembers[MT7530_NUM_VLANS];\n\tu8\tetags[MT7530_NUM_VLANS];\n\tu16\tvids[MT7530_NUM_VLANS];\n} mt7530_defaults[] = {\n\t{\n\t\t.name = \"llllw\",\n\t\t.pvids = { 1, 1, 1, 1, 2, 1, 1 },\n\t\t.members = { 0, 0x6f, 0x50 },\n\t\t.etags = { 0, 0x40, 0x40 },\n\t\t.vids = { 0, 1, 2 },\n\t}, {\n\t\t.name = \"wllll\",\n\t\t.pvids = { 2, 1, 1, 1, 1, 1, 1 },\n\t\t.members = { 0, 0x7e, 0x41 },\n\t\t.etags = { 0, 0x40, 0x40 },\n\t\t.vids = { 0, 1, 2 },\n\t}, {\n\t\t.name = \"lwlll\",\n\t\t.pvids = { 1, 2, 1, 1, 1, 1, 1 },\n\t\t.members = { 0, 0x7d, 0x42 },\n\t\t.etags = { 0, 0x40, 0x40 },\n\t\t.vids = { 0, 1, 2 },\n\t},\n};\n\nstruct mt7530_mapping*\nmt7530_find_mapping(struct device_node *np)\n{\n\tconst char *map;\n\tint i;\n\n\tif (of_property_read_string(np, \"mediatek,portmap\", &map))\n\t\treturn NULL;\n\n\tfor (i = 0; i < ARRAY_SIZE(mt7530_defaults); i++)\n\t\tif (!strcmp(map, mt7530_defaults[i].name))\n\t\t\treturn &mt7530_defaults[i];\n\n\treturn NULL;\n}\n\nstatic void\nmt7530_apply_mapping(struct mt7530_priv *mt7530, struct mt7530_mapping *map)\n{\n\tint i = 0;\n\n\tfor (i = 0; i < MT7530_NUM_PORTS; i++)\n\t\tmt7530->port_entries[i].pvid = map->pvids[i];\n\n\tfor (i = 0; i < MT7530_NUM_VLANS; i++) {\n\t\tmt7530->vlan_entries[i].member = map->members[i];\n\t\tmt7530->vlan_entries[i].etags = map->etags[i];\n\t\tmt7530->vlan_entries[i].vid = map->vids[i];\n\t}\n}\n\nstatic int\nmt7530_reset_switch(struct switch_dev *dev)\n{\n\tstruct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);\n\tint i;\n\n\tmemset(priv->port_entries, 0, sizeof(priv->port_entries));\n\tmemset(priv->vlan_entries, 0, sizeof(priv->vlan_entries));\n\n\t/* set default vid of each vlan to the same number of vlan, so the vid\n\t * won't need be set explicitly.\n\t */\n\tfor (i = 0; i < MT7530_NUM_VLANS; i++) {\n\t\tpriv->vlan_entries[i].vid = i;\n\t}\n\n\treturn 0;\n}\n\nstatic int\nmt7530_get_vlan_enable(struct switch_dev *dev,\n\t\t\t   const struct switch_attr *attr,\n\t\t\t   struct switch_val *val)\n{\n\tstruct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);\n\n\tval->value.i = priv->global_vlan_enable;\n\n\treturn 0;\n}\n\nstatic int\nmt7530_set_vlan_enable(struct switch_dev *dev,\n\t\t\t   const struct switch_attr *attr,\n\t\t\t   struct switch_val *val)\n{\n\tstruct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);\n\n\tpriv->global_vlan_enable = val->value.i != 0;\n\n\treturn 0;\n}\n\nstatic u32\nmt7530_r32(struct mt7530_priv *priv, u32 reg)\n{\n\tu32 val;\n\tif (priv->bus) {\n\t\tu16 high, low;\n\n\t\tmutex_lock(&priv->bus->mdio_lock);\n\t\t__mdiobus_write(priv->bus, 0x1f, 0x1f, (reg >> 6) & 0x3ff);\n\t\tlow = __mdiobus_read(priv->bus, 0x1f, (reg >> 2) & 0xf);\n\t\thigh = __mdiobus_read(priv->bus, 0x1f, 0x10);\n\t\tmutex_unlock(&priv->bus->mdio_lock);\n\n\t\treturn (high << 16) | (low & 0xffff);\n\t}\n\n\tval = ioread32(priv->base + reg);\n\tpr_debug(\"MT7530 MDIO Read [%04x]=%08x\\n\", reg, val);\n\n\treturn val;\n}\n\nstatic void\nmt7530_w32(struct mt7530_priv *priv, u32 reg, u32 val)\n{\n\tif (priv->bus) {\n\t\tmutex_lock(&priv->bus->mdio_lock);\n\t\t__mdiobus_write(priv->bus, 0x1f, 0x1f, (reg >> 6) & 0x3ff);\n\t\t__mdiobus_write(priv->bus, 0x1f, (reg >> 2) & 0xf,  val & 0xffff);\n\t\t__mdiobus_write(priv->bus, 0x1f, 0x10, val >> 16);\n\t\tmutex_unlock(&priv->bus->mdio_lock);\n\t\treturn;\n\t}\n\n\tpr_debug(\"MT7530 MDIO Write[%04x]=%08x\\n\", reg, val);\n\tiowrite32(val, priv->base + reg);\n}\n\nstatic void\nmt7530_vtcr(struct mt7530_priv *priv, u32 cmd, u32 val)\n{\n\tint i;\n\n\tmt7530_w32(priv, REG_ESW_VLAN_VTCR, BIT(31) | (cmd << 12) | val);\n\n\tfor (i = 0; i < 20; i++) {\n\t\tu32 val = mt7530_r32(priv, REG_ESW_VLAN_VTCR);\n\n\t\tif ((val & BIT(31)) == 0)\n\t\t\tbreak;\n\n\t\tudelay(1000);\n\t}\n\tif (i == 20)\n\t\tprintk(\"mt7530: vtcr timeout\\n\");\n}\n\nstatic int\nmt7530_get_port_pvid(struct switch_dev *dev, int port, int *val)\n{\n\tstruct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);\n\n\tif (port >= MT7530_NUM_PORTS)\n\t\treturn -EINVAL;\n\n\t*val = mt7530_r32(priv, REG_ESW_PORT_PPBV1(port));\n\t*val &= 0xfff;\n\n\treturn 0;\n}\n\nstatic int\nmt7530_set_port_pvid(struct switch_dev *dev, int port, int pvid)\n{\n\tstruct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);\n\n\tif (port >= MT7530_NUM_PORTS)\n\t\treturn -EINVAL;\n\n\tif (pvid < MT7530_MIN_VID || pvid > MT7530_MAX_VID)\n\t\treturn -EINVAL;\n\n\tpriv->port_entries[port].pvid = pvid;\n\n\treturn 0;\n}\n\nstatic int\nmt7530_get_vlan_ports(struct switch_dev *dev, struct switch_val *val)\n{\n\tstruct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);\n\tu32 member;\n\tu32 etags;\n\tint i;\n\n\tval->len = 0;\n\n\tif (val->port_vlan < 0 || val->port_vlan >= MT7530_NUM_VLANS)\n\t\treturn -EINVAL;\n\n\tmt7530_vtcr(priv, 0, val->port_vlan);\n\n\tmember = mt7530_r32(priv, REG_ESW_VLAN_VAWD1);\n\tmember >>= 16;\n\tmember &= 0xff;\n\n\tetags = mt7530_r32(priv, REG_ESW_VLAN_VAWD2);\n\n\tfor (i = 0; i < MT7530_NUM_PORTS; i++) {\n\t\tstruct switch_port *p;\n\t\tint etag;\n\n\t\tif (!(member & BIT(i)))\n\t\t\tcontinue;\n\n\t\tp = &val->value.ports[val->len++];\n\t\tp->id = i;\n\n\t\tetag = (etags >> (i * 2)) & 0x3;\n\n\t\tif (etag == ETAG_CTRL_TAG)\n\t\t\tp->flags |= BIT(SWITCH_PORT_FLAG_TAGGED);\n\t\telse if (etag != ETAG_CTRL_UNTAG)\n\t\t\tprintk(\"vlan %d port %d egress tag control neither untag nor tag: %d.\\n\",\n\t\t\t\t\tval->port_vlan, i, etag);\n\t}\n\n\treturn 0;\n}\n\nstatic int\nmt7530_set_vlan_ports(struct switch_dev *dev, struct switch_val *val)\n{\n\tstruct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);\n\tu8 member = 0;\n\tu8 etags = 0;\n\tint i;\n\n\tif (val->port_vlan < 0 || val->port_vlan >= MT7530_NUM_VLANS ||\n\t\t\tval->len > MT7530_NUM_PORTS)\n\t\treturn -EINVAL;\n\n\tfor (i = 0; i < val->len; i++) {\n\t\tstruct switch_port *p = &val->value.ports[i];\n\n\t\tif (p->id >= MT7530_NUM_PORTS)\n\t\t\treturn -EINVAL;\n\n\t\tmember |= BIT(p->id);\n\n\t\tif (p->flags & BIT(SWITCH_PORT_FLAG_TAGGED))\n\t\t\tetags |= BIT(p->id);\n\t}\n\tpriv->vlan_entries[val->port_vlan].member = member;\n\tpriv->vlan_entries[val->port_vlan].etags = etags;\n\n\treturn 0;\n}\n\nstatic int\nmt7530_set_vid(struct switch_dev *dev, const struct switch_attr *attr,\n\t\tstruct switch_val *val)\n{\n\tstruct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);\n\tint vlan;\n\tu16 vid;\n\n\tvlan = val->port_vlan;\n\tvid = (u16)val->value.i;\n\n\tif (vlan < 0 || vlan >= MT7530_NUM_VLANS)\n\t\treturn -EINVAL;\n\n\tif (vid < MT7530_MIN_VID || vid > MT7530_MAX_VID)\n\t\treturn -EINVAL;\n\n\tpriv->vlan_entries[vlan].vid = vid;\n\treturn 0;\n}\n\nstatic int\nmt7530_get_vid(struct switch_dev *dev, const struct switch_attr *attr,\n\t\tstruct switch_val *val)\n{\n\tstruct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);\n\tu32 vid;\n\tint vlan;\n\n\tvlan = val->port_vlan;\n\n\tvid = mt7530_r32(priv, REG_ESW_VLAN_VTIM(vlan));\n\tif (vlan & 1)\n\t\tvid = vid >> 12;\n\tvid &= 0xfff;\n\n\tval->value.i = vid;\n\treturn 0;\n}\n\nstatic int\nmt7530_get_mirror_monitor_port(struct switch_dev *dev, const struct switch_attr *attr,\n\t\tstruct switch_val *val)\n{\n\tstruct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);\n\n\tval->value.i = priv->mirror_dest_port;\n\n\treturn 0;\n}\n\nstatic int\nmt7530_set_mirror_monitor_port(struct switch_dev *dev, const struct switch_attr *attr,\n\t\tstruct switch_val *val)\n{\n\tstruct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);\n\n\tpriv->mirror_dest_port = val->value.i;\n\n\treturn 0;\n}\n\nstatic int\nmt7530_get_port_mirror_rx(struct switch_dev *dev, const struct switch_attr *attr,\n\t\tstruct switch_val *val)\n{\n\tstruct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);\n\n\tval->value.i =  priv->port_entries[val->port_vlan].mirror_rx;\n\n\treturn 0;\n}\n\nstatic int\nmt7530_set_port_mirror_rx(struct switch_dev *dev, const struct switch_attr *attr,\n\t\tstruct switch_val *val)\n{\n\tstruct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);\n\n\tpriv->port_entries[val->port_vlan].mirror_rx = val->value.i;\n\n\treturn 0;\n}\n\nstatic int\nmt7530_get_port_mirror_tx(struct switch_dev *dev, const struct switch_attr *attr,\n\t\tstruct switch_val *val)\n{\n\tstruct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);\n\n\tval->value.i =  priv->port_entries[val->port_vlan].mirror_tx;\n\n\treturn 0;\n}\n\nstatic int\nmt7530_set_port_mirror_tx(struct switch_dev *dev, const struct switch_attr *attr,\n\t\tstruct switch_val *val)\n{\n\tstruct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);\n\n\tpriv->port_entries[val->port_vlan].mirror_tx = val->value.i;\n\n\treturn 0;\n}\n\nstatic void\nmt7530_write_vlan_entry(struct mt7530_priv *priv, int vlan, u16 vid,\n\t                    u8 ports, u8 etags)\n{\n\tint port;\n\tu32 val;\n\n\t/* vid of vlan */\n\tval = mt7530_r32(priv, REG_ESW_VLAN_VTIM(vlan));\n\tif (vlan % 2 == 0) {\n\t\tval &= 0xfff000;\n\t\tval |= vid;\n\t} else {\n\t\tval &= 0xfff;\n\t\tval |= (vid << 12);\n\t}\n\tmt7530_w32(priv, REG_ESW_VLAN_VTIM(vlan), val);\n\n\t/* vlan port membership */\n\tif (ports)\n\t\tmt7530_w32(priv, REG_ESW_VLAN_VAWD1, REG_ESW_VLAN_VAWD1_IVL_MAC |\n\t\t\tREG_ESW_VLAN_VAWD1_VTAG_EN | (ports << 16) |\n\t\t\tREG_ESW_VLAN_VAWD1_VALID);\n\telse\n\t\tmt7530_w32(priv, REG_ESW_VLAN_VAWD1, 0);\n\n\t/* egress mode */\n\tval = 0;\n\tfor (port = 0; port < MT7530_NUM_PORTS; port++) {\n\t\tif (etags & BIT(port))\n\t\t\tval |= ETAG_CTRL_TAG << (port * 2);\n\t\telse\n\t\t\tval |= ETAG_CTRL_UNTAG << (port * 2);\n\t}\n\tmt7530_w32(priv, REG_ESW_VLAN_VAWD2, val);\n\n\t/* write to vlan table */\n\tmt7530_vtcr(priv, 1, vlan);\n}\n\nstatic int\nmt7530_apply_config(struct switch_dev *dev)\n{\n\tstruct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);\n\tint i, j;\n\tu8 tag_ports;\n\tu8 untag_ports;\n\tbool is_mirror = false;\n\n\tif (!priv->global_vlan_enable) {\n\t\tfor (i = 0; i < MT7530_NUM_PORTS; i++)\n\t\t\tmt7530_w32(priv, REG_ESW_PORT_PCR(i), 0x00400000);\n\n\t\tmt7530_w32(priv, REG_ESW_PORT_PCR(MT7530_CPU_PORT), 0x00ff0000);\n\n\t\tfor (i = 0; i < MT7530_NUM_PORTS; i++)\n\t\t\tmt7530_w32(priv, REG_ESW_PORT_PVC(i), 0x810000c0);\n\n\t\treturn 0;\n\t}\n\n\t/* set all ports as security mode */\n\tfor (i = 0; i < MT7530_NUM_PORTS; i++)\n\t\tmt7530_w32(priv, REG_ESW_PORT_PCR(i), 0x00ff0003);\n\n\t/* check if a port is used in tag/untag vlan egress mode */\n\ttag_ports = 0;\n\tuntag_ports = 0;\n\n\tfor (i = 0; i < MT7530_NUM_VLANS; i++) {\n\t\tu8 member = priv->vlan_entries[i].member;\n\t\tu8 etags = priv->vlan_entries[i].etags;\n\n\t\tif (!member)\n\t\t\tcontinue;\n\n\t\tfor (j = 0; j < MT7530_NUM_PORTS; j++) {\n\t\t\tif (!(member & BIT(j)))\n\t\t\t\tcontinue;\n\n\t\t\tif (etags & BIT(j))\n\t\t\t\ttag_ports |= 1u << j;\n\t\t\telse\n\t\t\t\tuntag_ports |= 1u << j;\n\t\t}\n\t}\n\n\t/* set all untag-only ports as transparent and the rest as user port */\n\tfor (i = 0; i < MT7530_NUM_PORTS; i++) {\n\t\tu32 pvc_mode = 0x81000000;\n\n\t\tif (untag_ports & BIT(i) && !(tag_ports & BIT(i)))\n\t\t\tpvc_mode = 0x810000c0;\n\n\t\tmt7530_w32(priv, REG_ESW_PORT_PVC(i), pvc_mode);\n\t}\n\n\t/* first clear the swtich vlan table */\n\tfor (i = 0; i < MT7530_NUM_VLANS; i++)\n\t\tmt7530_write_vlan_entry(priv, i, i, 0, 0);\n\n\t/* now program only vlans with members to avoid\n\t   clobbering remapped entries in later iterations */\n\tfor (i = 0; i < MT7530_NUM_VLANS; i++) {\n\t\tu16 vid = priv->vlan_entries[i].vid;\n\t\tu8 member = priv->vlan_entries[i].member;\n\t\tu8 etags = priv->vlan_entries[i].etags;\n\n\t\tif (member)\n\t\t\tmt7530_write_vlan_entry(priv, i, vid, member, etags);\n\t}\n\n\t/* Port Default PVID */\n\tfor (i = 0; i < MT7530_NUM_PORTS; i++) {\n\t\tint vlan = priv->port_entries[i].pvid;\n\t\tu16 pvid = 0;\n\t\tu32 val;\n\n\t\tif (vlan < MT7530_NUM_VLANS && priv->vlan_entries[vlan].member)\n\t\t\tpvid = priv->vlan_entries[vlan].vid;\n\n\t\tval = mt7530_r32(priv, REG_ESW_PORT_PPBV1(i));\n\t\tval &= ~0xfff;\n\t\tval |= pvid;\n\t\tmt7530_w32(priv, REG_ESW_PORT_PPBV1(i), val);\n\t}\n\n\t/* set mirroring source port */\n\tfor (i = 0; i < MT7530_NUM_PORTS; i++)\t{\n\t\tu32 val = mt7530_r32(priv, REG_ESW_PORT_PCR(i));\n\t\tif (priv->port_entries[i].mirror_rx) {\n\t\t\tval |= REG_ESW_PORT_PCR_MIRROR_SRC_RX_BIT;\n\t\t\tis_mirror = true;\n\t\t}\n\n\t\tif (priv->port_entries[i].mirror_tx) {\n\t\t\tval |= REG_ESW_PORT_PCR_MIRROR_SRC_TX_BIT;\n\t\t\tis_mirror = true;\n\t\t}\n\n\t\tmt7530_w32(priv, REG_ESW_PORT_PCR(i), val);\n\t}\n\n\t/* set mirroring monitor port */\n\tif (is_mirror) {\n\t\tu32 val = mt7530_r32(priv, REG_ESW_WT_MAC_MFC);\n\t\tval |= REG_ESW_WT_MAC_MFC_MIRROR_ENABLE;\n\t\tval &= ~REG_ESW_WT_MAC_MFC_MIRROR_DEST_MASK;\n\t\tval |= priv->mirror_dest_port;\n\t\tmt7530_w32(priv, REG_ESW_WT_MAC_MFC, val);\n\t}\n\n\treturn 0;\n}\n\nstatic int\nmt7530_get_port_link(struct switch_dev *dev,  int port,\n\t\t\tstruct switch_port_link *link)\n{\n\tstruct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);\n\tu32 speed, pmsr;\n\n\tif (port < 0 || port >= MT7530_NUM_PORTS)\n\t\treturn -EINVAL;\n\n\tpmsr = mt7530_r32(priv, 0x3008 + (0x100 * port));\n\n\tlink->link = pmsr & 1;\n\tlink->duplex = (pmsr >> 1) & 1;\n\tspeed = (pmsr >> 2) & 3;\n\n\tswitch (speed) {\n\tcase 0:\n\t\tlink->speed = SWITCH_PORT_SPEED_10;\n\t\tbreak;\n\tcase 1:\n\t\tlink->speed = SWITCH_PORT_SPEED_100;\n\t\tbreak;\n\tcase 2:\n\tcase 3: /* forced gige speed can be 2 or 3 */\n\t\tlink->speed = SWITCH_PORT_SPEED_1000;\n\t\tbreak;\n\tdefault:\n\t\tlink->speed = SWITCH_PORT_SPEED_UNKNOWN;\n\t\tbreak;\n\t}\n\n\treturn 0;\n}\n\nstatic u64 get_mib_counter_7620(struct mt7530_priv *priv, int i)\n{\n\treturn mt7530_r32(priv, MT7620_MIB_COUNTER_BASE + mt7620_mibs[i].offset);\n}\n\nstatic u64 get_mib_counter_port_7620(struct mt7530_priv *priv, int i, int port)\n{\n\treturn mt7530_r32(priv,\n\t\t\tMT7620_MIB_COUNTER_BASE_PORT +\n\t\t\t(MT7620_MIB_COUNTER_PORT_OFFSET * port) +\n\t\t\tmt7620_port_mibs[i].offset);\n}\n\nstatic int mt7530_sw_get_mib(struct switch_dev *dev,\n\t\t\t\t  const struct switch_attr *attr,\n\t\t\t\t  struct switch_val *val)\n{\n\tstatic char buf[4096];\n\tstruct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);\n\tint i, len = 0;\n\n\tlen += snprintf(buf + len, sizeof(buf) - len, \"Switch MIB counters\\n\");\n\n\tfor (i = 0; i < ARRAY_SIZE(mt7620_mibs); ++i) {\n\t\tu64 counter;\n\t\tlen += snprintf(buf + len, sizeof(buf) - len,\n\t\t\t\t\"%-11s: \", mt7620_mibs[i].name);\n\t\tcounter = get_mib_counter_7620(priv, i);\n\t\tlen += snprintf(buf + len, sizeof(buf) - len, \"%llu\\n\",\n\t\t\t\tcounter);\n\t}\n\n\tval->value.s = buf;\n\tval->len = len;\n\treturn 0;\n}\n\nstatic char *mt7530_print_arl_table_row(u32 atrd,\n\t\t\t\t\tu32 mac1,\n\t\t\t\t\tu32 mac2,\n\t\t\t\t\tchar *buf,\n\t\t\t\t\tsize_t *size)\n{\n\tint ret;\n\tsize_t port;\n\tsize_t i;\n\tu8 port_map;\n\tu8 mac[ETH_ALEN];\n\n\tmac1 = ntohl(mac1);\n\tmac2 = ntohl(mac2);\n\tport_map = (u8)((atrd & REG_ATRD_PORT_MASK) >> 4);\n\tmemcpy(mac, &mac1, sizeof(mac1));\n\tmemcpy(mac + sizeof(mac1), &mac2, sizeof(mac) - sizeof(mac1));\n\tfor (port = 0, i = 1; port < MT7530_NUM_PORTS; ++port, i <<= 1) {\n\t\tif (port_map & i) {\n\t\t\tret = snprintf(buf, *size, \"Port %d: MAC %pM\\n\", port, mac);\n\t\t\tif (ret >= *size || ret <= 0) {\n\t\t\t\t*buf = 0;\n\t\t\t\tbuf = NULL;\n\t\t\t\tgoto out;\n\t\t\t}\n\t\t\tbuf += ret;\n\t\t\t*size = *size - ret;\n\t\t}\n\t}\nout:\n\treturn buf;\n}\n\nstatic int mt7530_get_arl_table(struct switch_dev *dev,\n\t\t\t\tconst struct switch_attr *attr,\n\t\t\t\tstruct switch_val *val)\n{\n\tstruct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);\n\tchar *buf = priv->arl_buf;\n\tsize_t size = sizeof(priv->arl_buf);\n\tsize_t count = 0;\n\tsize_t retry_times = 100;\n\tint ret;\n\tu32 atc;\n\n\tret = snprintf(buf, size, \"address resolution table\\n\");\n\tif (ret >= size || ret <= 0) {\n\t\tpriv->arl_buf[0] = 0;\n\t\tgoto out;\n\t}\n\tbuf += ret;\n\tsize = size - ret;\n\n\tmt7530_w32(priv, REG_ESW_WT_MAC_ATC, REG_MAC_ATC_START);\n\n\tdo {\n\t\tatc = mt7530_r32(priv, REG_ESW_WT_MAC_ATC);\n\t\tif (atc & REG_MAC_ATC_SRCH_HIT && !(atc & REG_MAC_ATC_BUSY)) {\n\t\t\tu32 atrd;\n\n\t\t\t++count;\n\t\t\tatrd = mt7530_r32(priv, REG_ESW_TABLE_ATRD);\n\t\t\tif (atrd & REG_ATRD_VALID) {\n\t\t\t\tu32 mac1;\n\t\t\t\tu32 mac2;\n\n\t\t\t\tmac1 = mt7530_r32(priv, REG_ESW_TABLE_TSRA1);\n\t\t\t\tmac2 = mt7530_r32(priv, REG_ESW_TABLE_TSRA2);\n\n\t\t\t\tif (!(atc & REG_MAC_ATC_SRCH_END))\n\t\t\t\t\tmt7530_w32(priv, REG_ESW_WT_MAC_ATC, REG_MAC_ATC_NEXT);\n\n\t\t\t\tbuf = mt7530_print_arl_table_row(atrd, mac1, mac2, buf, &size);\n\t\t\t\tif (!buf) {\n\t\t\t\t\tpr_warn(\"%s: too many addresses\\n\", __func__);\n\t\t\t\t\tgoto out;\n\t\t\t\t}\n\t\t\t} else if (!(atc & REG_MAC_ATC_SRCH_END)) {\n\t\t\t\tmt7530_w32(priv, REG_ESW_WT_MAC_ATC, REG_MAC_ATC_NEXT);\n\t\t\t}\n\t\t} else {\n\t\t\t--retry_times;\n\t\t\tusleep_range(1000, 5000);\n\t\t}\n\t} while (!(atc & REG_MAC_ATC_SRCH_END) &&\n\t\t count < MT7530_NUM_ARL_RECORDS &&\n\t\t retry_times > 0);\nout:\n\tval->value.s = priv->arl_buf;\n\tval->len = strlen(priv->arl_buf);\n\n\treturn 0;\n}\n\nstatic int mt7530_sw_get_port_mib(struct switch_dev *dev,\n\t\t\t\t  const struct switch_attr *attr,\n\t\t\t\t  struct switch_val *val)\n{\n\tstatic char buf[4096];\n\tstruct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);\n\tint i, len = 0;\n\n\tif (val->port_vlan >= MT7530_NUM_PORTS)\n\t\treturn -EINVAL;\n\n\tlen += snprintf(buf + len, sizeof(buf) - len,\n\t\t\t\"Port %d MIB counters\\n\", val->port_vlan);\n\n\tfor (i = 0; i < ARRAY_SIZE(mt7620_port_mibs); ++i) {\n\t\tu64 counter;\n\t\tlen += snprintf(buf + len, sizeof(buf) - len,\n\t\t\t\t\"%-11s: \", mt7620_port_mibs[i].name);\n\t\tcounter = get_mib_counter_port_7620(priv, i, val->port_vlan);\n\t\tlen += snprintf(buf + len, sizeof(buf) - len, \"%llu\\n\",\n\t\t\t\tcounter);\n\t}\n\n\tval->value.s = buf;\n\tval->len = len;\n\treturn 0;\n}\n\nstatic int mt7530_get_port_stats(struct switch_dev *dev, int port,\n\t\t\t\t\tstruct switch_port_stats *stats)\n{\n\tstruct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);\n\n\tif (port < 0 || port >= MT7530_NUM_PORTS)\n\t\treturn -EINVAL;\n\n\tstats->tx_bytes = get_mib_counter_port_7620(priv, MT7530_PORT_MIB_TXB_ID, port);\n\tstats->rx_bytes = get_mib_counter_port_7620(priv, MT7530_PORT_MIB_RXB_ID, port);\n\n\treturn 0;\n}\n\nstatic const struct switch_attr mt7530_global[] = {\n\t{\n\t\t.type = SWITCH_TYPE_INT,\n\t\t.name = \"enable_vlan\",\n\t\t.description = \"VLAN mode (1:enabled)\",\n\t\t.max = 1,\n\t\t.id = MT7530_ATTR_ENABLE_VLAN,\n\t\t.get = mt7530_get_vlan_enable,\n\t\t.set = mt7530_set_vlan_enable,\n\t}, {\n\t\t.type = SWITCH_TYPE_STRING,\n\t\t.name = \"mib\",\n\t\t.description = \"Get MIB counters for switch\",\n\t\t.get = mt7530_sw_get_mib,\n\t\t.set = NULL,\n\t}, {\n\t\t.type = SWITCH_TYPE_INT,\n\t\t.name = \"mirror_monitor_port\",\n\t\t.description = \"Mirror monitor port\",\n\t\t.set = mt7530_set_mirror_monitor_port,\n\t\t.get = mt7530_get_mirror_monitor_port,\n\t\t.max = MT7530_NUM_PORTS - 1\n\t},\n\t{\n\t\t.type = SWITCH_TYPE_STRING,\n\t\t.name = \"arl_table\",\n\t\t.description = \"Get ARL table\",\n\t\t.set = NULL,\n\t\t.get = mt7530_get_arl_table,\n\t},\n};\n\nstatic const struct switch_attr mt7530_port[] = {\n\t{\n\t\t.type = SWITCH_TYPE_STRING,\n\t\t.name = \"mib\",\n\t\t.description = \"Get MIB counters for port\",\n\t\t.get = mt7530_sw_get_port_mib,\n\t\t.set = NULL,\n\t}, {\n\t\t.type = SWITCH_TYPE_INT,\n\t\t.name = \"enable_mirror_rx\",\n\t\t.description = \"Enable mirroring of RX packets\",\n\t\t.set = mt7530_set_port_mirror_rx,\n\t\t.get = mt7530_get_port_mirror_rx,\n\t\t.max = 1,\n\t}, {\n\t\t.type = SWITCH_TYPE_INT,\n\t\t.name = \"enable_mirror_tx\",\n\t\t.description = \"Enable mirroring of TX packets\",\n\t\t.set = mt7530_set_port_mirror_tx,\n\t\t.get = mt7530_get_port_mirror_tx,\n\t\t.max = 1,\n\t},\n};\n\nstatic const struct switch_attr mt7530_vlan[] = {\n\t{\n\t\t.type = SWITCH_TYPE_INT,\n\t\t.name = \"vid\",\n\t\t.description = \"VLAN ID (0-4094)\",\n\t\t.set = mt7530_set_vid,\n\t\t.get = mt7530_get_vid,\n\t\t.max = 4094,\n\t},\n};\n\nstatic const struct switch_dev_ops mt7530_ops = {\n\t.attr_global = {\n\t\t.attr = mt7530_global,\n\t\t.n_attr = ARRAY_SIZE(mt7530_global),\n\t},\n\t.attr_port = {\n\t\t.attr = mt7530_port,\n\t\t.n_attr = ARRAY_SIZE(mt7530_port),\n\t},\n\t.attr_vlan = {\n\t\t.attr = mt7530_vlan,\n\t\t.n_attr = ARRAY_SIZE(mt7530_vlan),\n\t},\n\t.get_vlan_ports = mt7530_get_vlan_ports,\n\t.set_vlan_ports = mt7530_set_vlan_ports,\n\t.get_port_pvid = mt7530_get_port_pvid,\n\t.set_port_pvid = mt7530_set_port_pvid,\n\t.get_port_link = mt7530_get_port_link,\n\t.get_port_stats = mt7530_get_port_stats,\n\t.apply_config = mt7530_apply_config,\n\t.reset_switch = mt7530_reset_switch,\n};\n\nint\nmt7530_probe(struct device *dev, void __iomem *base, struct mii_bus *bus, int vlan)\n{\n\tstruct switch_dev *swdev;\n\tstruct mt7530_priv *mt7530;\n\tstruct mt7530_mapping *map;\n\tint ret;\n\n\tmt7530 = devm_kzalloc(dev, sizeof(struct mt7530_priv), GFP_KERNEL);\n\tif (!mt7530)\n\t\treturn -ENOMEM;\n\n\tmt7530->base = base;\n\tmt7530->bus = bus;\n\tmt7530->global_vlan_enable = vlan;\n\n\tswdev = &mt7530->swdev;\n\tif (bus) {\n\t\tswdev->alias = \"mt7530\";\n\t\tswdev->name = \"mt7530\";\n\t} else {\n\t\tswdev->alias = \"mt7620\";\n\t\tswdev->name = \"mt7620\";\n\t}\n\tswdev->cpu_port = MT7530_CPU_PORT;\n\tswdev->ports = MT7530_NUM_PORTS;\n\tswdev->vlans = MT7530_NUM_VLANS;\n\tswdev->ops = &mt7530_ops;\n\n\tret = register_switch(swdev, NULL);\n\tif (ret) {\n\t\tdev_err(dev, \"failed to register mt7530\\n\");\n\t\treturn ret;\n\t}\n\n\n\tmap = mt7530_find_mapping(dev->of_node);\n\tif (map)\n\t\tmt7530_apply_mapping(mt7530, map);\n\tmt7530_apply_config(swdev);\n\n\t/* magic vodoo */\n\tif (bus && mt7530_r32(mt7530, REG_HWTRAP) !=  0x1117edf) {\n\t\tdev_info(dev, \"fixing up MHWTRAP register - bootloader probably played with it\\n\");\n\t\tmt7530_w32(mt7530, REG_HWTRAP, 0x1117edf);\n\t}\n\tdev_info(dev, \"loaded %s driver\\n\", swdev->name);\n\n\treturn 0;\n}\n"
  },
  {
    "path": "target/linux/ramips/files/drivers/net/ethernet/ralink/mt7530.h",
    "content": "/*\n * This program is free software; you can redistribute it and/or\n * modify it under the terms of the GNU General Public License\n * as published by the Free Software Foundation; either version 2\n * of the License, or (at your option) any later version.\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n * GNU General Public License for more details.\n *\n * Copyright (C) 2013 John Crispin <blogic@openwrt.org>\n * Copyright (C) 2016 Vitaly Chekryzhev <13hakta@gmail.com>\n */\n\n#ifndef _MT7530_H__\n#define _MT7530_H__\n\n#define MT7620_MIB_COUNTER_BASE_PORT\t0x4000\n#define MT7620_MIB_COUNTER_PORT_OFFSET\t0x100\n#define MT7620_MIB_COUNTER_BASE\t0x1010\n\n/* PPE Accounting Group #0 Byte Counter */\n#define MT7620_MIB_STATS_PPE_AC_BCNT0\t0x000\n\n/* PPE Accounting Group #0 Packet Counter */\n#define MT7620_MIB_STATS_PPE_AC_PCNT0\t0x004\n\n/* PPE Accounting Group #63 Byte Counter */\n#define MT7620_MIB_STATS_PPE_AC_BCNT63\t0x1F8\n\n/* PPE Accounting Group #63 Packet Counter */\n#define MT7620_MIB_STATS_PPE_AC_PCNT63\t0x1FC\n\n/* PPE Meter Group #0 */\n#define MT7620_MIB_STATS_PPE_MTR_CNT0\t0x200\n\n/* PPE Meter Group #63 */\n#define MT7620_MIB_STATS_PPE_MTR_CNT63\t0x2FC\n\n/* Transmit good byte count for CPU GDM */\n#define MT7620_MIB_STATS_GDM1_TX_GBCNT\t0x300\n\n/* Transmit good packet count for CPU GDM (exclude flow control frames) */\n#define MT7620_MIB_STATS_GDM1_TX_GPCNT\t0x304\n\n/* Transmit abort count for CPU GDM */\n#define MT7620_MIB_STATS_GDM1_TX_SKIPCNT\t0x308\n\n/* Transmit collision count for CPU GDM */\n#define MT7620_MIB_STATS_GDM1_TX_COLCNT\t0x30C\n\n/* Received good byte count for CPU GDM */\n#define MT7620_MIB_STATS_GDM1_RX_GBCNT1\t0x320\n\n/* Received good packet count for CPU GDM (exclude flow control frame) */\n#define MT7620_MIB_STATS_GDM1_RX_GPCNT1\t0x324\n\n/* Received overflow error packet count for CPU GDM */\n#define MT7620_MIB_STATS_GDM1_RX_OERCNT\t0x328\n\n/* Received FCS error packet count for CPU GDM */\n#define MT7620_MIB_STATS_GDM1_RX_FERCNT\t0x32C\n\n/* Received too short error packet count for CPU GDM */\n#define MT7620_MIB_STATS_GDM1_RX_SERCNT\t0x330\n\n/* Received too long error packet count for CPU GDM */\n#define MT7620_MIB_STATS_GDM1_RX_LERCNT\t0x334\n\n/* Received IP/TCP/UDP checksum error packet count for CPU GDM */\n#define MT7620_MIB_STATS_GDM1_RX_CERCNT\t0x338\n\n/* Received flow control pkt count for CPU GDM */\n#define MT7620_MIB_STATS_GDM1_RX_FCCNT\t0x33C\n\n/* Transmit good byte count for PPE GDM */\n#define MT7620_MIB_STATS_GDM2_TX_GBCNT\t0x340\n\n/* Transmit good packet count for PPE GDM (exclude flow control frames) */\n#define MT7620_MIB_STATS_GDM2_TX_GPCNT\t0x344\n\n/* Transmit abort count for PPE GDM */\n#define MT7620_MIB_STATS_GDM2_TX_SKIPCNT\t0x348\n\n/* Transmit collision count for PPE GDM */\n#define MT7620_MIB_STATS_GDM2_TX_COLCNT\t0x34C\n\n/* Received good byte count for PPE GDM */\n#define MT7620_MIB_STATS_GDM2_RX_GBCNT\t0x360\n\n/* Received good packet count for PPE GDM (exclude flow control frame) */\n#define MT7620_MIB_STATS_GDM2_RX_GPCNT\t0x364\n\n/* Received overflow error packet count for PPE GDM */\n#define MT7620_MIB_STATS_GDM2_RX_OERCNT\t0x368\n\n/* Received FCS error packet count for PPE GDM */\n#define MT7620_MIB_STATS_GDM2_RX_FERCNT\t0x36C\n\n/* Received too short error packet count for PPE GDM */\n#define MT7620_MIB_STATS_GDM2_RX_SERCNT\t0x370\n\n/* Received too long error packet count for PPE GDM */\n#define MT7620_MIB_STATS_GDM2_RX_LERCNT\t0x374\n\n/* Received IP/TCP/UDP checksum error packet count for PPE GDM */\n#define MT7620_MIB_STATS_GDM2_RX_CERCNT\t0x378\n\n/* Received flow control pkt count for PPE GDM */\n#define MT7620_MIB_STATS_GDM2_RX_FCCNT\t0x37C\n\n/* Tx Packet Counter of Port n */\n#define MT7620_MIB_STATS_PORT_TGPCN\t0x10\n\n/* Tx Bad Octet Counter of Port n */\n#define MT7620_MIB_STATS_PORT_TBOCN\t0x14\n\n/* Tx Good Octet Counter of Port n */\n#define MT7620_MIB_STATS_PORT_TGOCN\t0x18\n\n/* Tx Event Packet Counter of Port n */\n#define MT7620_MIB_STATS_PORT_TEPCN\t0x1C\n\n/* Rx Packet Counter of Port n */\n#define MT7620_MIB_STATS_PORT_RGPCN\t0x20\n\n/* Rx Bad Octet Counter of Port n */\n#define MT7620_MIB_STATS_PORT_RBOCN\t0x24\n\n/* Rx Good Octet Counter of Port n */\n#define MT7620_MIB_STATS_PORT_RGOCN\t0x28\n\n/* Rx Event Packet Counter of Port n */\n#define MT7620_MIB_STATS_PORT_REPC1N\t0x2C\n\n/* Rx Event Packet Counter of Port n */\n#define MT7620_MIB_STATS_PORT_REPC2N\t0x30\n\nint mt7530_probe(struct device *dev, void __iomem *base, struct mii_bus *bus, int vlan);\n\n#endif\n"
  },
  {
    "path": "target/linux/ramips/files/drivers/net/ethernet/ralink/mtk_eth_soc.c",
    "content": "/*   This program is free software; you can redistribute it and/or modify\n *   it under the terms of the GNU General Public License as published by\n *   the Free Software Foundation; version 2 of the License\n *\n *   This program is distributed in the hope that it will be useful,\n *   but WITHOUT ANY WARRANTY; without even the implied warranty of\n *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n *   GNU General Public License for more details.\n *\n *   Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>\n *   Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>\n *   Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>\n */\n\n#include <linux/module.h>\n#include <linux/kernel.h>\n#include <linux/types.h>\n#include <linux/dma-mapping.h>\n#include <linux/init.h>\n#include <linux/skbuff.h>\n#include <linux/etherdevice.h>\n#include <linux/ethtool.h>\n#include <linux/platform_device.h>\n#include <linux/of_device.h>\n#include <linux/clk.h>\n#include <linux/of_net.h>\n#include <linux/of_mdio.h>\n#include <linux/if_vlan.h>\n#include <linux/reset.h>\n#include <linux/tcp.h>\n#include <linux/io.h>\n#include <linux/bug.h>\n#include <linux/netfilter.h>\n#include <net/netfilter/nf_flow_table.h>\n#include <linux/of_gpio.h>\n#include <linux/gpio.h>\n#include <linux/gpio/consumer.h>\n\n#include <asm/mach-ralink/ralink_regs.h>\n\n#include \"mtk_eth_soc.h\"\n#include \"mdio.h\"\n#include \"ethtool.h\"\n\n#define\tMAX_RX_LENGTH\t\t1536\n#define FE_RX_ETH_HLEN\t\t(VLAN_ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN)\n#define FE_RX_HLEN\t\t(NET_SKB_PAD + FE_RX_ETH_HLEN + NET_IP_ALIGN)\n#define DMA_DUMMY_DESC\t\t0xffffffff\n#define FE_DEFAULT_MSG_ENABLE \\\n\t\t(NETIF_MSG_DRV | \\\n\t\tNETIF_MSG_PROBE | \\\n\t\tNETIF_MSG_LINK | \\\n\t\tNETIF_MSG_TIMER | \\\n\t\tNETIF_MSG_IFDOWN | \\\n\t\tNETIF_MSG_IFUP | \\\n\t\tNETIF_MSG_RX_ERR | \\\n\t\tNETIF_MSG_TX_ERR)\n\n#define TX_DMA_DESP2_DEF\t(TX_DMA_LS0 | TX_DMA_DONE)\n#define TX_DMA_DESP4_DEF\t(TX_DMA_QN(3) | TX_DMA_PN(1))\n#define NEXT_TX_DESP_IDX(X)\t(((X) + 1) & (ring->tx_ring_size - 1))\n#define NEXT_RX_DESP_IDX(X)\t(((X) + 1) & (ring->rx_ring_size - 1))\n\n#define SYSC_REG_RSTCTRL\t0x34\n\nstatic int fe_msg_level = -1;\nmodule_param_named(msg_level, fe_msg_level, int, 0);\nMODULE_PARM_DESC(msg_level, \"Message level (-1=defaults,0=none,...,16=all)\");\n\nstatic const u16 fe_reg_table_default[FE_REG_COUNT] = {\n\t[FE_REG_PDMA_GLO_CFG] = FE_PDMA_GLO_CFG,\n\t[FE_REG_PDMA_RST_CFG] = FE_PDMA_RST_CFG,\n\t[FE_REG_DLY_INT_CFG] = FE_DLY_INT_CFG,\n\t[FE_REG_TX_BASE_PTR0] = FE_TX_BASE_PTR0,\n\t[FE_REG_TX_MAX_CNT0] = FE_TX_MAX_CNT0,\n\t[FE_REG_TX_CTX_IDX0] = FE_TX_CTX_IDX0,\n\t[FE_REG_TX_DTX_IDX0] = FE_TX_DTX_IDX0,\n\t[FE_REG_RX_BASE_PTR0] = FE_RX_BASE_PTR0,\n\t[FE_REG_RX_MAX_CNT0] = FE_RX_MAX_CNT0,\n\t[FE_REG_RX_CALC_IDX0] = FE_RX_CALC_IDX0,\n\t[FE_REG_RX_DRX_IDX0] = FE_RX_DRX_IDX0,\n\t[FE_REG_FE_INT_ENABLE] = FE_FE_INT_ENABLE,\n\t[FE_REG_FE_INT_STATUS] = FE_FE_INT_STATUS,\n\t[FE_REG_FE_DMA_VID_BASE] = FE_DMA_VID0,\n\t[FE_REG_FE_COUNTER_BASE] = FE_GDMA1_TX_GBCNT,\n\t[FE_REG_FE_RST_GL] = FE_FE_RST_GL,\n};\n\nstatic const u16 *fe_reg_table = fe_reg_table_default;\n\nstruct fe_work_t {\n\tint bitnr;\n\tvoid (*action)(struct fe_priv *);\n};\n\nstatic void __iomem *fe_base;\n\nvoid fe_w32(u32 val, unsigned reg)\n{\n\t__raw_writel(val, fe_base + reg);\n}\n\nu32 fe_r32(unsigned reg)\n{\n\treturn __raw_readl(fe_base + reg);\n}\n\nvoid fe_reg_w32(u32 val, enum fe_reg reg)\n{\n\tfe_w32(val, fe_reg_table[reg]);\n}\n\nu32 fe_reg_r32(enum fe_reg reg)\n{\n\treturn fe_r32(fe_reg_table[reg]);\n}\n\nvoid fe_m32(struct fe_priv *eth, u32 clear, u32 set, unsigned reg)\n{\n\tu32 val;\n\n\tspin_lock(&eth->page_lock);\n\tval = __raw_readl(fe_base + reg);\n\tval &= ~clear;\n\tval |= set;\n\t__raw_writel(val, fe_base + reg);\n\tspin_unlock(&eth->page_lock);\n}\n\nvoid fe_reset(u32 reset_bits)\n{\n\tu32 t;\n\n\tt = rt_sysc_r32(SYSC_REG_RSTCTRL);\n\tt |= reset_bits;\n\trt_sysc_w32(t, SYSC_REG_RSTCTRL);\n\tusleep_range(10, 20);\n\n\tt &= ~reset_bits;\n\trt_sysc_w32(t, SYSC_REG_RSTCTRL);\n\tusleep_range(10, 20);\n}\n\nvoid fe_reset_fe(struct fe_priv *priv)\n{\n\tif (!priv->rst_fe)\n\t\treturn;\n\n\treset_control_assert(priv->rst_fe);\n\tusleep_range(60, 120);\n\treset_control_deassert(priv->rst_fe);\n\tusleep_range(60, 120);\n}\n\nstatic inline void fe_int_disable(u32 mask)\n{\n\tfe_reg_w32(fe_reg_r32(FE_REG_FE_INT_ENABLE) & ~mask,\n\t\t   FE_REG_FE_INT_ENABLE);\n\t/* flush write */\n\tfe_reg_r32(FE_REG_FE_INT_ENABLE);\n}\n\nstatic inline void fe_int_enable(u32 mask)\n{\n\tfe_reg_w32(fe_reg_r32(FE_REG_FE_INT_ENABLE) | mask,\n\t\t   FE_REG_FE_INT_ENABLE);\n\t/* flush write */\n\tfe_reg_r32(FE_REG_FE_INT_ENABLE);\n}\n\nstatic inline void fe_hw_set_macaddr(struct fe_priv *priv, unsigned char *mac)\n{\n\tunsigned long flags;\n\n\tspin_lock_irqsave(&priv->page_lock, flags);\n\tfe_w32((mac[0] << 8) | mac[1], FE_GDMA1_MAC_ADRH);\n\tfe_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],\n\t       FE_GDMA1_MAC_ADRL);\n\tspin_unlock_irqrestore(&priv->page_lock, flags);\n}\n\nstatic int fe_set_mac_address(struct net_device *dev, void *p)\n{\n\tint ret = eth_mac_addr(dev, p);\n\n\tif (!ret) {\n\t\tstruct fe_priv *priv = netdev_priv(dev);\n\n\t\tif (priv->soc->set_mac)\n\t\t\tpriv->soc->set_mac(priv, dev->dev_addr);\n\t\telse\n\t\t\tfe_hw_set_macaddr(priv, p);\n\t}\n\n\treturn ret;\n}\n\nstatic inline int fe_max_frag_size(int mtu)\n{\n\t/* make sure buf_size will be at least MAX_RX_LENGTH */\n\tif (mtu + FE_RX_ETH_HLEN < MAX_RX_LENGTH)\n\t\tmtu = MAX_RX_LENGTH - FE_RX_ETH_HLEN;\n\n\treturn SKB_DATA_ALIGN(FE_RX_HLEN + mtu) +\n\t\tSKB_DATA_ALIGN(sizeof(struct skb_shared_info));\n}\n\nstatic inline int fe_max_buf_size(int frag_size)\n{\n\tint buf_size = frag_size - NET_SKB_PAD - NET_IP_ALIGN -\n\t\t       SKB_DATA_ALIGN(sizeof(struct skb_shared_info));\n\n\tBUG_ON(buf_size < MAX_RX_LENGTH);\n\treturn buf_size;\n}\n\nstatic inline void fe_get_rxd(struct fe_rx_dma *rxd, struct fe_rx_dma *dma_rxd)\n{\n\trxd->rxd1 = dma_rxd->rxd1;\n\trxd->rxd2 = dma_rxd->rxd2;\n\trxd->rxd3 = dma_rxd->rxd3;\n\trxd->rxd4 = dma_rxd->rxd4;\n}\n\nstatic inline void fe_set_txd(struct fe_tx_dma *txd, struct fe_tx_dma *dma_txd)\n{\n\tdma_txd->txd1 = txd->txd1;\n\tdma_txd->txd3 = txd->txd3;\n\tdma_txd->txd4 = txd->txd4;\n\t/* clean dma done flag last */\n\tdma_txd->txd2 = txd->txd2;\n}\n\nstatic void fe_clean_rx(struct fe_priv *priv)\n{\n\tstruct fe_rx_ring *ring = &priv->rx_ring;\n\tstruct page *page;\n\tint i;\n\n\tif (ring->rx_data) {\n\t\tfor (i = 0; i < ring->rx_ring_size; i++)\n\t\t\tif (ring->rx_data[i]) {\n\t\t\t\tif (ring->rx_dma && ring->rx_dma[i].rxd1)\n\t\t\t\t\tdma_unmap_single(priv->dev,\n\t\t\t\t\t\t\t ring->rx_dma[i].rxd1,\n\t\t\t\t\t\t\t ring->rx_buf_size,\n\t\t\t\t\t\t\t DMA_FROM_DEVICE);\n\t\t\t\tskb_free_frag(ring->rx_data[i]);\n\t\t\t}\n\n\t\tkfree(ring->rx_data);\n\t\tring->rx_data = NULL;\n\t}\n\n\tif (ring->rx_dma) {\n\t\tdma_free_coherent(priv->dev,\n\t\t\t\t  ring->rx_ring_size * sizeof(*ring->rx_dma),\n\t\t\t\t  ring->rx_dma,\n\t\t\t\t  ring->rx_phys);\n\t\tring->rx_dma = NULL;\n\t}\n\n\tif (!ring->frag_cache.va)\n\t    return;\n\n\tpage = virt_to_page(ring->frag_cache.va);\n\t__page_frag_cache_drain(page, ring->frag_cache.pagecnt_bias);\n\tmemset(&ring->frag_cache, 0, sizeof(ring->frag_cache));\n}\n\nstatic int fe_alloc_rx(struct fe_priv *priv)\n{\n\tstruct fe_rx_ring *ring = &priv->rx_ring;\n\tint i, pad;\n\n\tring->rx_data = kcalloc(ring->rx_ring_size, sizeof(*ring->rx_data),\n\t\t\tGFP_KERNEL);\n\tif (!ring->rx_data)\n\t\tgoto no_rx_mem;\n\n\tfor (i = 0; i < ring->rx_ring_size; i++) {\n\t\tring->rx_data[i] = page_frag_alloc(&ring->frag_cache,\n\t\t\t\t\t\t   ring->frag_size,\n\t\t\t\t\t\t   GFP_KERNEL);\n\t\tif (!ring->rx_data[i])\n\t\t\tgoto no_rx_mem;\n\t}\n\n\tring->rx_dma = dma_alloc_coherent(priv->dev,\n\t\t\tring->rx_ring_size * sizeof(*ring->rx_dma),\n\t\t\t&ring->rx_phys,\n\t\t\tGFP_ATOMIC | __GFP_ZERO);\n\tif (!ring->rx_dma)\n\t\tgoto no_rx_mem;\n\n\tif (priv->flags & FE_FLAG_RX_2B_OFFSET)\n\t\tpad = 0;\n\telse\n\t\tpad = NET_IP_ALIGN;\n\tfor (i = 0; i < ring->rx_ring_size; i++) {\n\t\tdma_addr_t dma_addr = dma_map_single(priv->dev,\n\t\t\t\tring->rx_data[i] + NET_SKB_PAD + pad,\n\t\t\t\tring->rx_buf_size,\n\t\t\t\tDMA_FROM_DEVICE);\n\t\tif (unlikely(dma_mapping_error(priv->dev, dma_addr)))\n\t\t\tgoto no_rx_mem;\n\t\tring->rx_dma[i].rxd1 = (unsigned int)dma_addr;\n\n\t\tif (priv->flags & FE_FLAG_RX_SG_DMA)\n\t\t\tring->rx_dma[i].rxd2 = RX_DMA_PLEN0(ring->rx_buf_size);\n\t\telse\n\t\t\tring->rx_dma[i].rxd2 = RX_DMA_LSO;\n\t}\n\tring->rx_calc_idx = ring->rx_ring_size - 1;\n\t/* make sure that all changes to the dma ring are flushed before we\n\t * continue\n\t */\n\twmb();\n\n\tfe_reg_w32(ring->rx_phys, FE_REG_RX_BASE_PTR0);\n\tfe_reg_w32(ring->rx_ring_size, FE_REG_RX_MAX_CNT0);\n\tfe_reg_w32(ring->rx_calc_idx, FE_REG_RX_CALC_IDX0);\n\tfe_reg_w32(FE_PST_DRX_IDX0, FE_REG_PDMA_RST_CFG);\n\n\treturn 0;\n\nno_rx_mem:\n\treturn -ENOMEM;\n}\n\nstatic void fe_txd_unmap(struct device *dev, struct fe_tx_buf *tx_buf)\n{\n\tif (dma_unmap_len(tx_buf, dma_len0))\n\t\tdma_unmap_page(dev,\n\t\t\t       dma_unmap_addr(tx_buf, dma_addr0),\n\t\t\t       dma_unmap_len(tx_buf, dma_len0),\n\t\t\t       DMA_TO_DEVICE);\n\n\tif (dma_unmap_len(tx_buf, dma_len1))\n\t\tdma_unmap_page(dev,\n\t\t\t       dma_unmap_addr(tx_buf, dma_addr1),\n\t\t\t       dma_unmap_len(tx_buf, dma_len1),\n\t\t\t       DMA_TO_DEVICE);\n\n\tdma_unmap_len_set(tx_buf, dma_addr0, 0);\n\tdma_unmap_len_set(tx_buf, dma_addr1, 0);\n\tif (tx_buf->skb && (tx_buf->skb != (struct sk_buff *)DMA_DUMMY_DESC))\n\t\tdev_kfree_skb_any(tx_buf->skb);\n\ttx_buf->skb = NULL;\n}\n\nstatic void fe_clean_tx(struct fe_priv *priv)\n{\n\tint i;\n\tstruct device *dev = priv->dev;\n\tstruct fe_tx_ring *ring = &priv->tx_ring;\n\n\tif (ring->tx_buf) {\n\t\tfor (i = 0; i < ring->tx_ring_size; i++)\n\t\t\tfe_txd_unmap(dev, &ring->tx_buf[i]);\n\t\tkfree(ring->tx_buf);\n\t\tring->tx_buf = NULL;\n\t}\n\n\tif (ring->tx_dma) {\n\t\tdma_free_coherent(dev,\n\t\t\t\t  ring->tx_ring_size * sizeof(*ring->tx_dma),\n\t\t\t\t  ring->tx_dma,\n\t\t\t\t  ring->tx_phys);\n\t\tring->tx_dma = NULL;\n\t}\n\n\tnetdev_reset_queue(priv->netdev);\n}\n\nstatic int fe_alloc_tx(struct fe_priv *priv)\n{\n\tint i;\n\tstruct fe_tx_ring *ring = &priv->tx_ring;\n\n\tring->tx_free_idx = 0;\n\tring->tx_next_idx = 0;\n\tring->tx_thresh = max((unsigned long)ring->tx_ring_size >> 2,\n\t\t\t      MAX_SKB_FRAGS);\n\n\tring->tx_buf = kcalloc(ring->tx_ring_size, sizeof(*ring->tx_buf),\n\t\t\tGFP_KERNEL);\n\tif (!ring->tx_buf)\n\t\tgoto no_tx_mem;\n\n\tring->tx_dma = dma_alloc_coherent(priv->dev,\n\t\t\tring->tx_ring_size * sizeof(*ring->tx_dma),\n\t\t\t&ring->tx_phys,\n\t\t\tGFP_ATOMIC | __GFP_ZERO);\n\tif (!ring->tx_dma)\n\t\tgoto no_tx_mem;\n\n\tfor (i = 0; i < ring->tx_ring_size; i++) {\n\t\tif (priv->soc->tx_dma)\n\t\t\tpriv->soc->tx_dma(&ring->tx_dma[i]);\n\t\tring->tx_dma[i].txd2 = TX_DMA_DESP2_DEF;\n\t}\n\t/* make sure that all changes to the dma ring are flushed before we\n\t * continue\n\t */\n\twmb();\n\n\tfe_reg_w32(ring->tx_phys, FE_REG_TX_BASE_PTR0);\n\tfe_reg_w32(ring->tx_ring_size, FE_REG_TX_MAX_CNT0);\n\tfe_reg_w32(0, FE_REG_TX_CTX_IDX0);\n\tfe_reg_w32(FE_PST_DTX_IDX0, FE_REG_PDMA_RST_CFG);\n\n\treturn 0;\n\nno_tx_mem:\n\treturn -ENOMEM;\n}\n\nstatic int fe_init_dma(struct fe_priv *priv)\n{\n\tint err;\n\n\terr = fe_alloc_tx(priv);\n\tif (err)\n\t\treturn err;\n\n\terr = fe_alloc_rx(priv);\n\tif (err)\n\t\treturn err;\n\n\treturn 0;\n}\n\nstatic void fe_free_dma(struct fe_priv *priv)\n{\n\tfe_clean_tx(priv);\n\tfe_clean_rx(priv);\n}\n\nvoid fe_stats_update(struct fe_priv *priv)\n{\n\tstruct fe_hw_stats *hwstats = priv->hw_stats;\n\tunsigned int base = fe_reg_table[FE_REG_FE_COUNTER_BASE];\n\tu64 stats;\n\n\tu64_stats_update_begin(&hwstats->syncp);\n\n\tif (IS_ENABLED(CONFIG_SOC_MT7621)) {\n\t\thwstats->rx_bytes\t\t\t+= fe_r32(base);\n\t\tstats\t\t\t\t\t=  fe_r32(base + 0x04);\n\t\tif (stats)\n\t\t\thwstats->rx_bytes\t\t+= (stats << 32);\n\t\thwstats->rx_packets\t\t\t+= fe_r32(base + 0x08);\n\t\thwstats->rx_overflow\t\t\t+= fe_r32(base + 0x10);\n\t\thwstats->rx_fcs_errors\t\t\t+= fe_r32(base + 0x14);\n\t\thwstats->rx_short_errors\t\t+= fe_r32(base + 0x18);\n\t\thwstats->rx_long_errors\t\t\t+= fe_r32(base + 0x1c);\n\t\thwstats->rx_checksum_errors\t\t+= fe_r32(base + 0x20);\n\t\thwstats->rx_flow_control_packets\t+= fe_r32(base + 0x24);\n\t\thwstats->tx_skip\t\t\t+= fe_r32(base + 0x28);\n\t\thwstats->tx_collisions\t\t\t+= fe_r32(base + 0x2c);\n\t\thwstats->tx_bytes\t\t\t+= fe_r32(base + 0x30);\n\t\tstats\t\t\t\t\t=  fe_r32(base + 0x34);\n\t\tif (stats)\n\t\t\thwstats->tx_bytes\t\t+= (stats << 32);\n\t\thwstats->tx_packets\t\t\t+= fe_r32(base + 0x38);\n\t} else {\n\t\thwstats->tx_bytes\t\t\t+= fe_r32(base);\n\t\thwstats->tx_packets\t\t\t+= fe_r32(base + 0x04);\n\t\thwstats->tx_skip\t\t\t+= fe_r32(base + 0x08);\n\t\thwstats->tx_collisions\t\t\t+= fe_r32(base + 0x0c);\n\t\thwstats->rx_bytes\t\t\t+= fe_r32(base + 0x20);\n\t\thwstats->rx_packets\t\t\t+= fe_r32(base + 0x24);\n\t\thwstats->rx_overflow\t\t\t+= fe_r32(base + 0x28);\n\t\thwstats->rx_fcs_errors\t\t\t+= fe_r32(base + 0x2c);\n\t\thwstats->rx_short_errors\t\t+= fe_r32(base + 0x30);\n\t\thwstats->rx_long_errors\t\t\t+= fe_r32(base + 0x34);\n\t\thwstats->rx_checksum_errors\t\t+= fe_r32(base + 0x38);\n\t\thwstats->rx_flow_control_packets\t+= fe_r32(base + 0x3c);\n\t}\n\n\tu64_stats_update_end(&hwstats->syncp);\n}\n\nstatic void fe_get_stats64(struct net_device *dev,\n\t\t\t\tstruct rtnl_link_stats64 *storage)\n{\n\tstruct fe_priv *priv = netdev_priv(dev);\n\tstruct fe_hw_stats *hwstats = priv->hw_stats;\n\tunsigned int base = fe_reg_table[FE_REG_FE_COUNTER_BASE];\n\tunsigned int start;\n\n\tif (!base) {\n\t\tnetdev_stats_to_stats64(storage, &dev->stats);\n\t\treturn;\n\t}\n\n\tif (netif_running(dev) && netif_device_present(dev)) {\n\t\tif (spin_trylock_bh(&hwstats->stats_lock)) {\n\t\t\tfe_stats_update(priv);\n\t\t\tspin_unlock_bh(&hwstats->stats_lock);\n\t\t}\n\t}\n\n\tdo {\n\t\tstart = u64_stats_fetch_begin_irq(&hwstats->syncp);\n\t\tstorage->rx_packets = hwstats->rx_packets;\n\t\tstorage->tx_packets = hwstats->tx_packets;\n\t\tstorage->rx_bytes = hwstats->rx_bytes;\n\t\tstorage->tx_bytes = hwstats->tx_bytes;\n\t\tstorage->collisions = hwstats->tx_collisions;\n\t\tstorage->rx_length_errors = hwstats->rx_short_errors +\n\t\t\thwstats->rx_long_errors;\n\t\tstorage->rx_over_errors = hwstats->rx_overflow;\n\t\tstorage->rx_crc_errors = hwstats->rx_fcs_errors;\n\t\tstorage->rx_errors = hwstats->rx_checksum_errors;\n\t\tstorage->tx_aborted_errors = hwstats->tx_skip;\n\t} while (u64_stats_fetch_retry_irq(&hwstats->syncp, start));\n\n\tstorage->tx_errors = priv->netdev->stats.tx_errors;\n\tstorage->rx_dropped = priv->netdev->stats.rx_dropped;\n\tstorage->tx_dropped = priv->netdev->stats.tx_dropped;\n}\n\nstatic int fe_vlan_rx_add_vid(struct net_device *dev,\n\t\t\t      __be16 proto, u16 vid)\n{\n\tstruct fe_priv *priv = netdev_priv(dev);\n\tu32 idx = (vid & 0xf);\n\tu32 vlan_cfg;\n\n\tif (!((fe_reg_table[FE_REG_FE_DMA_VID_BASE]) &&\n\t      (dev->features & NETIF_F_HW_VLAN_CTAG_TX)))\n\t\treturn 0;\n\n\tif (test_bit(idx, &priv->vlan_map)) {\n\t\tnetdev_warn(dev, \"disable tx vlan offload\\n\");\n\t\tdev->wanted_features &= ~NETIF_F_HW_VLAN_CTAG_TX;\n\t\tnetdev_update_features(dev);\n\t} else {\n\t\tvlan_cfg = fe_r32(fe_reg_table[FE_REG_FE_DMA_VID_BASE] +\n\t\t\t\t((idx >> 1) << 2));\n\t\tif (idx & 0x1) {\n\t\t\tvlan_cfg &= 0xffff;\n\t\t\tvlan_cfg |= (vid << 16);\n\t\t} else {\n\t\t\tvlan_cfg &= 0xffff0000;\n\t\t\tvlan_cfg |= vid;\n\t\t}\n\t\tfe_w32(vlan_cfg, fe_reg_table[FE_REG_FE_DMA_VID_BASE] +\n\t\t\t\t((idx >> 1) << 2));\n\t\tset_bit(idx, &priv->vlan_map);\n\t}\n\n\treturn 0;\n}\n\nstatic int fe_vlan_rx_kill_vid(struct net_device *dev,\n\t\t\t       __be16 proto, u16 vid)\n{\n\tstruct fe_priv *priv = netdev_priv(dev);\n\tu32 idx = (vid & 0xf);\n\n\tif (!((fe_reg_table[FE_REG_FE_DMA_VID_BASE]) &&\n\t      (dev->features & NETIF_F_HW_VLAN_CTAG_TX)))\n\t\treturn 0;\n\n\tclear_bit(idx, &priv->vlan_map);\n\n\treturn 0;\n}\n\nstatic inline u32 fe_empty_txd(struct fe_tx_ring *ring)\n{\n\tbarrier();\n\treturn (u32)(ring->tx_ring_size -\n\t\t\t((ring->tx_next_idx - ring->tx_free_idx) &\n\t\t\t (ring->tx_ring_size - 1)));\n}\n\nstruct fe_map_state {\n\tstruct device *dev;\n\tstruct fe_tx_dma txd;\n\tu32 def_txd4;\n\tint ring_idx;\n\tint i;\n};\n\nstatic void fe_tx_dma_write_desc(struct fe_tx_ring *ring, struct fe_map_state *st)\n{\n\tfe_set_txd(&st->txd, &ring->tx_dma[st->ring_idx]);\n\tmemset(&st->txd, 0, sizeof(st->txd));\n\tst->txd.txd4 = st->def_txd4;\n\tst->ring_idx = NEXT_TX_DESP_IDX(st->ring_idx);\n}\n\nstatic int __fe_tx_dma_map_page(struct fe_tx_ring *ring, struct fe_map_state *st,\n\t\t\t\tstruct page *page, size_t offset, size_t size)\n{\n\tstruct device *dev = st->dev;\n\tstruct fe_tx_buf *tx_buf;\n\tdma_addr_t mapped_addr;\n\n\tmapped_addr = dma_map_page(dev, page, offset, size, DMA_TO_DEVICE);\n\tif (unlikely(dma_mapping_error(dev, mapped_addr)))\n\t\treturn -EIO;\n\n\tif (st->i && !(st->i & 1))\n\t    fe_tx_dma_write_desc(ring, st);\n\n\ttx_buf = &ring->tx_buf[st->ring_idx];\n\tif (st->i & 1) {\n\t\tst->txd.txd3 = mapped_addr;\n\t\tst->txd.txd2 |= TX_DMA_PLEN1(size);\n\t\tdma_unmap_addr_set(tx_buf, dma_addr1, mapped_addr);\n\t\tdma_unmap_len_set(tx_buf, dma_len1, size);\n\t} else {\n\t\ttx_buf->skb = (struct sk_buff *)DMA_DUMMY_DESC;\n\t\tst->txd.txd1 = mapped_addr;\n\t\tst->txd.txd2 = TX_DMA_PLEN0(size);\n\t\tdma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr);\n\t\tdma_unmap_len_set(tx_buf, dma_len0, size);\n\t}\n\tst->i++;\n\n\treturn 0;\n}\n\nstatic int fe_tx_dma_map_page(struct fe_tx_ring *ring, struct fe_map_state *st,\n\t\t\t      struct page *page, size_t offset, size_t size)\n{\n\tint cur_size;\n\tint ret;\n\n\twhile (size > 0) {\n\t\tcur_size = min_t(size_t, size, TX_DMA_BUF_LEN);\n\n\t\tret = __fe_tx_dma_map_page(ring, st, page, offset, cur_size);\n\t\tif (ret)\n\t\t\treturn ret;\n\n\t\tsize -= cur_size;\n\t\toffset += cur_size;\n\t}\n\n\treturn 0;\n}\n\nstatic int fe_tx_dma_map_skb(struct fe_tx_ring *ring, struct fe_map_state *st,\n\t\t\t     struct sk_buff *skb)\n{\n\tstruct page *page = virt_to_page(skb->data);\n\tsize_t offset = offset_in_page(skb->data);\n\tsize_t size = skb_headlen(skb);\n\n\treturn fe_tx_dma_map_page(ring, st, page, offset, size);\n}\n\nstatic inline struct sk_buff *\nfe_next_frag(struct sk_buff *head, struct sk_buff *skb)\n{\n\tif (skb != head)\n\t\treturn skb->next;\n\n\tif (skb_has_frag_list(skb))\n\t\treturn skb_shinfo(skb)->frag_list;\n\n\treturn NULL;\n}\n\n\nstatic int fe_tx_map_dma(struct sk_buff *skb, struct net_device *dev,\n\t\t\t int tx_num, struct fe_tx_ring *ring)\n{\n\tstruct fe_priv *priv = netdev_priv(dev);\n\tstruct fe_map_state st = {\n\t\t.dev = priv->dev,\n\t\t.ring_idx = ring->tx_next_idx,\n\t};\n\tstruct sk_buff *head = skb;\n\tstruct fe_tx_buf *tx_buf;\n\tunsigned int nr_frags;\n\tint i, j;\n\n\t/* init tx descriptor */\n\tif (priv->soc->tx_dma)\n\t\tpriv->soc->tx_dma(&st.txd);\n\telse\n\t\tst.txd.txd4 = TX_DMA_DESP4_DEF;\n\tst.def_txd4 = st.txd.txd4;\n\n\t/* TX Checksum offload */\n\tif (skb->ip_summed == CHECKSUM_PARTIAL)\n\t\tst.txd.txd4 |= TX_DMA_CHKSUM;\n\n\t/* VLAN header offload */\n\tif (skb_vlan_tag_present(skb)) {\n\t\tu16 tag = skb_vlan_tag_get(skb);\n\n\t\tif (IS_ENABLED(CONFIG_SOC_MT7621))\n\t\t\tst.txd.txd4 |= TX_DMA_INS_VLAN_MT7621 | tag;\n\t\telse\n\t\t\tst.txd.txd4 |= TX_DMA_INS_VLAN |\n\t\t\t\t((tag >> VLAN_PRIO_SHIFT) << 4) |\n\t\t\t\t(tag & 0xF);\n\t}\n\n\t/* TSO: fill MSS info in tcp checksum field */\n\tif (skb_is_gso(skb)) {\n\t\tif (skb_cow_head(skb, 0)) {\n\t\t\tnetif_warn(priv, tx_err, dev,\n\t\t\t\t   \"GSO expand head fail.\\n\");\n\t\t\tgoto err_out;\n\t\t}\n\t\tif (skb_shinfo(skb)->gso_type &\n\t\t\t\t(SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {\n\t\t\tst.txd.txd4 |= TX_DMA_TSO;\n\t\t\ttcp_hdr(skb)->check = htons(skb_shinfo(skb)->gso_size);\n\t\t}\n\t}\n\nnext_frag:\n\tif (skb_headlen(skb) && fe_tx_dma_map_skb(ring, &st, skb))\n\t\tgoto err_dma;\n\n\t/* TX SG offload */\n\tnr_frags = skb_shinfo(skb)->nr_frags;\n\tfor (i = 0; i < nr_frags; i++) {\n\t\tskb_frag_t *frag;\n\n\t\tfrag = &skb_shinfo(skb)->frags[i];\n\t\tif (fe_tx_dma_map_page(ring, &st, skb_frag_page(frag),\n\t\t\t\t       skb_frag_off(frag), skb_frag_size(frag)))\n\t\t\tgoto err_dma;\n\t}\n\n\tskb = fe_next_frag(head, skb);\n\tif (skb)\n\t\tgoto next_frag;\n\n\t/* set last segment */\n\tif (st.i & 0x1)\n\t\tst.txd.txd2 |= TX_DMA_LS0;\n\telse\n\t\tst.txd.txd2 |= TX_DMA_LS1;\n\n\t/* store skb to cleanup */\n\ttx_buf = &ring->tx_buf[st.ring_idx];\n\ttx_buf->skb = head;\n\n\tnetdev_sent_queue(dev, head->len);\n\tskb_tx_timestamp(head);\n\n\tfe_tx_dma_write_desc(ring, &st);\n\tring->tx_next_idx = st.ring_idx;\n\n\t/* make sure that all changes to the dma ring are flushed before we\n\t * continue\n\t */\n\twmb();\n\tif (unlikely(fe_empty_txd(ring) <= ring->tx_thresh)) {\n\t\tnetif_stop_queue(dev);\n\t\tsmp_mb();\n\t\tif (unlikely(fe_empty_txd(ring) > ring->tx_thresh))\n\t\t\tnetif_wake_queue(dev);\n\t}\n\n\tif (netif_xmit_stopped(netdev_get_tx_queue(dev, 0)) || !netdev_xmit_more())\n\t\tfe_reg_w32(ring->tx_next_idx, FE_REG_TX_CTX_IDX0);\n\n\treturn 0;\n\nerr_dma:\n\tj = ring->tx_next_idx;\n\tfor (i = 0; i < tx_num; i++) {\n\t\t/* unmap dma */\n\t\tfe_txd_unmap(priv->dev, &ring->tx_buf[j]);\n\t\tring->tx_dma[j].txd2 = TX_DMA_DESP2_DEF;\n\n\t\tj = NEXT_TX_DESP_IDX(j);\n\t}\n\t/* make sure that all changes to the dma ring are flushed before we\n\t * continue\n\t */\n\twmb();\n\nerr_out:\n\treturn -1;\n}\n\nstatic inline int fe_skb_padto(struct sk_buff *skb, struct fe_priv *priv)\n{\n\tunsigned int len;\n\tint ret;\n\n\tret = 0;\n\tif (unlikely(skb->len < VLAN_ETH_ZLEN)) {\n\t\tif ((priv->flags & FE_FLAG_PADDING_64B) &&\n\t\t    !(priv->flags & FE_FLAG_PADDING_BUG))\n\t\t\treturn ret;\n\n\t\tif (skb_vlan_tag_present(skb))\n\t\t\tlen = ETH_ZLEN;\n\t\telse if (skb->protocol == cpu_to_be16(ETH_P_8021Q))\n\t\t\tlen = VLAN_ETH_ZLEN;\n\t\telse if (!(priv->flags & FE_FLAG_PADDING_64B))\n\t\t\tlen = ETH_ZLEN;\n\t\telse\n\t\t\treturn ret;\n\n\t\tif (skb->len < len) {\n\t\t\tret = skb_pad(skb, len - skb->len);\n\t\t\tif (ret < 0)\n\t\t\t\treturn ret;\n\t\t\tskb->len = len;\n\t\t\tskb_set_tail_pointer(skb, len);\n\t\t}\n\t}\n\n\treturn ret;\n}\n\nstatic inline int fe_cal_txd_req(struct sk_buff *skb)\n{\n\tstruct sk_buff *head = skb;\n\tint i, nfrags = 0;\n\tskb_frag_t *frag;\n\nnext_frag:\n\tnfrags++;\n\tif (skb_is_gso(skb)) {\n\t\tfor (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {\n\t\t\tfrag = &skb_shinfo(skb)->frags[i];\n\t\t\tnfrags += DIV_ROUND_UP(skb_frag_size(frag), TX_DMA_BUF_LEN);\n\t\t}\n\t} else {\n\t\tnfrags += skb_shinfo(skb)->nr_frags;\n\t}\n\n\tskb = fe_next_frag(head, skb);\n\tif (skb)\n\t\tgoto next_frag;\n\n\treturn DIV_ROUND_UP(nfrags, 2);\n}\n\nstatic int fe_start_xmit(struct sk_buff *skb, struct net_device *dev)\n{\n\tstruct fe_priv *priv = netdev_priv(dev);\n\tstruct fe_tx_ring *ring = &priv->tx_ring;\n\tstruct net_device_stats *stats = &dev->stats;\n\tint tx_num;\n\tint len = skb->len;\n\n\tif (fe_skb_padto(skb, priv)) {\n\t\tnetif_warn(priv, tx_err, dev, \"tx padding failed!\\n\");\n\t\treturn NETDEV_TX_OK;\n\t}\n\n\ttx_num = fe_cal_txd_req(skb);\n\tif (unlikely(fe_empty_txd(ring) <= tx_num)) {\n\t\tnetif_stop_queue(dev);\n\t\tnetif_err(priv, tx_queued, dev,\n\t\t\t  \"Tx Ring full when queue awake!\\n\");\n\t\treturn NETDEV_TX_BUSY;\n\t}\n\n\tif (fe_tx_map_dma(skb, dev, tx_num, ring) < 0) {\n\t\tstats->tx_dropped++;\n\t} else {\n\t\tstats->tx_packets++;\n\t\tstats->tx_bytes += len;\n\t}\n\n\treturn NETDEV_TX_OK;\n}\n\nstatic int fe_poll_rx(struct napi_struct *napi, int budget,\n\t\t      struct fe_priv *priv, u32 rx_intr)\n{\n\tstruct net_device *netdev = priv->netdev;\n\tstruct net_device_stats *stats = &netdev->stats;\n\tstruct fe_soc_data *soc = priv->soc;\n\tstruct fe_rx_ring *ring = &priv->rx_ring;\n\tint idx = ring->rx_calc_idx;\n\tu32 checksum_bit;\n\tstruct sk_buff *skb;\n\tu8 *data, *new_data;\n\tstruct fe_rx_dma *rxd, trxd;\n\tint done = 0, pad;\n\n\tif (netdev->features & NETIF_F_RXCSUM)\n\t\tchecksum_bit = soc->checksum_bit;\n\telse\n\t\tchecksum_bit = 0;\n\n\tif (priv->flags & FE_FLAG_RX_2B_OFFSET)\n\t\tpad = 0;\n\telse\n\t\tpad = NET_IP_ALIGN;\n\n\twhile (done < budget) {\n\t\tunsigned int pktlen;\n\t\tdma_addr_t dma_addr;\n\n\t\tidx = NEXT_RX_DESP_IDX(idx);\n\t\trxd = &ring->rx_dma[idx];\n\t\tdata = ring->rx_data[idx];\n\n\t\tfe_get_rxd(&trxd, rxd);\n\t\tif (!(trxd.rxd2 & RX_DMA_DONE))\n\t\t\tbreak;\n\n\t\t/* alloc new buffer */\n\t\tnew_data = page_frag_alloc(&ring->frag_cache, ring->frag_size,\n\t\t\t\t\t   GFP_ATOMIC);\n\t\tif (unlikely(!new_data)) {\n\t\t\tstats->rx_dropped++;\n\t\t\tgoto release_desc;\n\t\t}\n\t\tdma_addr = dma_map_single(priv->dev,\n\t\t\t\t\t  new_data + NET_SKB_PAD + pad,\n\t\t\t\t\t  ring->rx_buf_size,\n\t\t\t\t\t  DMA_FROM_DEVICE);\n\t\tif (unlikely(dma_mapping_error(priv->dev, dma_addr))) {\n\t\t\tskb_free_frag(new_data);\n\t\t\tgoto release_desc;\n\t\t}\n\n\t\t/* receive data */\n\t\tskb = build_skb(data, ring->frag_size);\n\t\tif (unlikely(!skb)) {\n\t\t\tskb_free_frag(new_data);\n\t\t\tgoto release_desc;\n\t\t}\n\t\tskb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN);\n\n\t\tdma_unmap_single(priv->dev, trxd.rxd1,\n\t\t\t\t ring->rx_buf_size, DMA_FROM_DEVICE);\n\t\tpktlen = RX_DMA_GET_PLEN0(trxd.rxd2);\n\t\tskb->dev = netdev;\n\t\tskb_put(skb, pktlen);\n\t\tif (trxd.rxd4 & checksum_bit)\n\t\t\tskb->ip_summed = CHECKSUM_UNNECESSARY;\n\t\telse\n\t\t\tskb_checksum_none_assert(skb);\n\t\tskb->protocol = eth_type_trans(skb, netdev);\n\n\t\tif (netdev->features & NETIF_F_HW_VLAN_CTAG_RX &&\n\t\t    RX_DMA_VID(trxd.rxd3))\n\t\t\t__vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),\n\t\t\t\t\t       RX_DMA_VID(trxd.rxd3));\n\n\t\tstats->rx_packets++;\n\t\tstats->rx_bytes += pktlen;\n\n\t\tnapi_gro_receive(napi, skb);\n\n\t\tring->rx_data[idx] = new_data;\n\t\trxd->rxd1 = (unsigned int)dma_addr;\n\nrelease_desc:\n\t\tif (priv->flags & FE_FLAG_RX_SG_DMA)\n\t\t\trxd->rxd2 = RX_DMA_PLEN0(ring->rx_buf_size);\n\t\telse\n\t\t\trxd->rxd2 = RX_DMA_LSO;\n\n\t\tring->rx_calc_idx = idx;\n\t\t/* make sure that all changes to the dma ring are flushed before\n\t\t * we continue\n\t\t */\n\t\twmb();\n\t\tfe_reg_w32(ring->rx_calc_idx, FE_REG_RX_CALC_IDX0);\n\t\tdone++;\n\t}\n\n\tif (done < budget)\n\t\tfe_reg_w32(rx_intr, FE_REG_FE_INT_STATUS);\n\n\treturn done;\n}\n\nstatic int fe_poll_tx(struct fe_priv *priv, int budget, u32 tx_intr,\n\t\t      int *tx_again)\n{\n\tstruct net_device *netdev = priv->netdev;\n\tunsigned int bytes_compl = 0;\n\tstruct sk_buff *skb;\n\tstruct fe_tx_buf *tx_buf;\n\tint done = 0;\n\tu32 idx, hwidx;\n\tstruct fe_tx_ring *ring = &priv->tx_ring;\n\n\tidx = ring->tx_free_idx;\n\thwidx = fe_reg_r32(FE_REG_TX_DTX_IDX0);\n\n\twhile ((idx != hwidx) && budget) {\n\t\ttx_buf = &ring->tx_buf[idx];\n\t\tskb = tx_buf->skb;\n\n\t\tif (!skb)\n\t\t\tbreak;\n\n\t\tif (skb != (struct sk_buff *)DMA_DUMMY_DESC) {\n\t\t\tbytes_compl += skb->len;\n\t\t\tdone++;\n\t\t\tbudget--;\n\t\t}\n\t\tfe_txd_unmap(priv->dev, tx_buf);\n\t\tidx = NEXT_TX_DESP_IDX(idx);\n\t}\n\tring->tx_free_idx = idx;\n\n\tif (idx == hwidx) {\n\t\t/* read hw index again make sure no new tx packet */\n\t\thwidx = fe_reg_r32(FE_REG_TX_DTX_IDX0);\n\t\tif (idx == hwidx)\n\t\t\tfe_reg_w32(tx_intr, FE_REG_FE_INT_STATUS);\n\t\telse\n\t\t\t*tx_again = 1;\n\t} else {\n\t\t*tx_again = 1;\n\t}\n\n\tif (done) {\n\t\tnetdev_completed_queue(netdev, done, bytes_compl);\n\t\tsmp_mb();\n\t\tif (unlikely(netif_queue_stopped(netdev) &&\n\t\t\t     (fe_empty_txd(ring) > ring->tx_thresh)))\n\t\t\tnetif_wake_queue(netdev);\n\t}\n\n\treturn done;\n}\n\nstatic int fe_poll(struct napi_struct *napi, int budget)\n{\n\tstruct fe_priv *priv = container_of(napi, struct fe_priv, rx_napi);\n\tstruct fe_hw_stats *hwstat = priv->hw_stats;\n\tint tx_done, rx_done, tx_again;\n\tu32 status, fe_status, status_reg, mask;\n\tu32 tx_intr, rx_intr, status_intr;\n\n\tstatus = fe_reg_r32(FE_REG_FE_INT_STATUS);\n\tfe_status = status;\n\ttx_intr = priv->soc->tx_int;\n\trx_intr = priv->soc->rx_int;\n\tstatus_intr = priv->soc->status_int;\n\ttx_done = 0;\n\trx_done = 0;\n\ttx_again = 0;\n\n\tif (fe_reg_table[FE_REG_FE_INT_STATUS2]) {\n\t\tfe_status = fe_reg_r32(FE_REG_FE_INT_STATUS2);\n\t\tstatus_reg = FE_REG_FE_INT_STATUS2;\n\t} else {\n\t\tstatus_reg = FE_REG_FE_INT_STATUS;\n\t}\n\n\tif (status & tx_intr)\n\t\ttx_done = fe_poll_tx(priv, budget, tx_intr, &tx_again);\n\n\tif (status & rx_intr)\n\t\trx_done = fe_poll_rx(napi, budget, priv, rx_intr);\n\n\tif (unlikely(fe_status & status_intr)) {\n\t\tif (hwstat && spin_trylock(&hwstat->stats_lock)) {\n\t\t\tfe_stats_update(priv);\n\t\t\tspin_unlock(&hwstat->stats_lock);\n\t\t}\n\t\tfe_reg_w32(status_intr, status_reg);\n\t}\n\n\tif (unlikely(netif_msg_intr(priv))) {\n\t\tmask = fe_reg_r32(FE_REG_FE_INT_ENABLE);\n\t\tnetdev_info(priv->netdev,\n\t\t\t    \"done tx %d, rx %d, intr 0x%08x/0x%x\\n\",\n\t\t\t    tx_done, rx_done, status, mask);\n\t}\n\n\tif (!tx_again && (rx_done < budget)) {\n\t\tstatus = fe_reg_r32(FE_REG_FE_INT_STATUS);\n\t\tif (status & (tx_intr | rx_intr)) {\n\t\t\t/* let napi poll again */\n\t\t\trx_done = budget;\n\t\t\tgoto poll_again;\n\t\t}\n\n\t\tnapi_complete_done(napi, rx_done);\n\t\tfe_int_enable(tx_intr | rx_intr);\n\t} else {\n\t\trx_done = budget;\n\t}\n\npoll_again:\n\treturn rx_done;\n}\n\n#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0)\nstatic void fe_tx_timeout(struct net_device *dev)\n#else\nstatic void fe_tx_timeout(struct net_device *dev, unsigned int txqueue)\n#endif\n{\n\tstruct fe_priv *priv = netdev_priv(dev);\n\tstruct fe_tx_ring *ring = &priv->tx_ring;\n\n\tpriv->netdev->stats.tx_errors++;\n\tnetif_err(priv, tx_err, dev,\n\t\t  \"transmit timed out\\n\");\n\tnetif_info(priv, drv, dev, \"dma_cfg:%08x\\n\",\n\t\t   fe_reg_r32(FE_REG_PDMA_GLO_CFG));\n\tnetif_info(priv, drv, dev, \"tx_ring=%d, \"\n\t\t   \"base=%08x, max=%u, ctx=%u, dtx=%u, fdx=%hu, next=%hu\\n\",\n\t\t   0, fe_reg_r32(FE_REG_TX_BASE_PTR0),\n\t\t   fe_reg_r32(FE_REG_TX_MAX_CNT0),\n\t\t   fe_reg_r32(FE_REG_TX_CTX_IDX0),\n\t\t   fe_reg_r32(FE_REG_TX_DTX_IDX0),\n\t\t   ring->tx_free_idx,\n\t\t   ring->tx_next_idx);\n\tnetif_info(priv, drv, dev,\n\t\t   \"rx_ring=%d, base=%08x, max=%u, calc=%u, drx=%u\\n\",\n\t\t   0, fe_reg_r32(FE_REG_RX_BASE_PTR0),\n\t\t   fe_reg_r32(FE_REG_RX_MAX_CNT0),\n\t\t   fe_reg_r32(FE_REG_RX_CALC_IDX0),\n\t\t   fe_reg_r32(FE_REG_RX_DRX_IDX0));\n\n\tif (!test_and_set_bit(FE_FLAG_RESET_PENDING, priv->pending_flags))\n\t\tschedule_work(&priv->pending_work);\n}\n\nstatic irqreturn_t fe_handle_irq(int irq, void *dev)\n{\n\tstruct fe_priv *priv = netdev_priv(dev);\n\tu32 status, int_mask;\n\n\tstatus = fe_reg_r32(FE_REG_FE_INT_STATUS);\n\n\tif (unlikely(!status))\n\t\treturn IRQ_NONE;\n\n\tint_mask = (priv->soc->rx_int | priv->soc->tx_int);\n\tif (likely(status & int_mask)) {\n\t\tif (likely(napi_schedule_prep(&priv->rx_napi))) {\n\t\t\tfe_int_disable(int_mask);\n\t\t\t__napi_schedule(&priv->rx_napi);\n\t\t}\n\t} else {\n\t\tfe_reg_w32(status, FE_REG_FE_INT_STATUS);\n\t}\n\n\treturn IRQ_HANDLED;\n}\n\n#ifdef CONFIG_NET_POLL_CONTROLLER\nstatic void fe_poll_controller(struct net_device *dev)\n{\n\tstruct fe_priv *priv = netdev_priv(dev);\n\tu32 int_mask = priv->soc->tx_int | priv->soc->rx_int;\n\n\tfe_int_disable(int_mask);\n\tfe_handle_irq(dev->irq, dev);\n\tfe_int_enable(int_mask);\n}\n#endif\n\nint fe_set_clock_cycle(struct fe_priv *priv)\n{\n\tunsigned long sysclk = priv->sysclk;\n\n\tsysclk /= FE_US_CYC_CNT_DIVISOR;\n\tsysclk <<= FE_US_CYC_CNT_SHIFT;\n\n\tfe_w32((fe_r32(FE_FE_GLO_CFG) &\n\t\t\t~(FE_US_CYC_CNT_MASK << FE_US_CYC_CNT_SHIFT)) |\n\t\t\tsysclk,\n\t\t\tFE_FE_GLO_CFG);\n\treturn 0;\n}\n\nvoid fe_fwd_config(struct fe_priv *priv)\n{\n\tu32 fwd_cfg;\n\n\tfwd_cfg = fe_r32(FE_GDMA1_FWD_CFG);\n\n\t/* disable jumbo frame */\n\tif (priv->flags & FE_FLAG_JUMBO_FRAME)\n\t\tfwd_cfg &= ~FE_GDM1_JMB_EN;\n\n\t/* set unicast/multicast/broadcast frame to cpu */\n\tfwd_cfg &= ~0xffff;\n\n\tfe_w32(fwd_cfg, FE_GDMA1_FWD_CFG);\n}\n\nstatic void fe_rxcsum_config(bool enable)\n{\n\tif (enable)\n\t\tfe_w32(fe_r32(FE_GDMA1_FWD_CFG) | (FE_GDM1_ICS_EN |\n\t\t\t\t\tFE_GDM1_TCS_EN | FE_GDM1_UCS_EN),\n\t\t\t\tFE_GDMA1_FWD_CFG);\n\telse\n\t\tfe_w32(fe_r32(FE_GDMA1_FWD_CFG) & ~(FE_GDM1_ICS_EN |\n\t\t\t\t\tFE_GDM1_TCS_EN | FE_GDM1_UCS_EN),\n\t\t\t\tFE_GDMA1_FWD_CFG);\n}\n\nstatic void fe_txcsum_config(bool enable)\n{\n\tif (enable)\n\t\tfe_w32(fe_r32(FE_CDMA_CSG_CFG) | (FE_ICS_GEN_EN |\n\t\t\t\t\tFE_TCS_GEN_EN | FE_UCS_GEN_EN),\n\t\t\t\tFE_CDMA_CSG_CFG);\n\telse\n\t\tfe_w32(fe_r32(FE_CDMA_CSG_CFG) & ~(FE_ICS_GEN_EN |\n\t\t\t\t\tFE_TCS_GEN_EN | FE_UCS_GEN_EN),\n\t\t\t\tFE_CDMA_CSG_CFG);\n}\n\nvoid fe_csum_config(struct fe_priv *priv)\n{\n\tstruct net_device *dev = priv_netdev(priv);\n\n\tfe_txcsum_config((dev->features & NETIF_F_IP_CSUM));\n\tfe_rxcsum_config((dev->features & NETIF_F_RXCSUM));\n}\n\nstatic int fe_hw_init(struct net_device *dev)\n{\n\tstruct fe_priv *priv = netdev_priv(dev);\n\tint i, err;\n\n\terr = devm_request_irq(priv->dev, dev->irq, fe_handle_irq, 0,\n\t\t\t       dev_name(priv->dev), dev);\n\tif (err)\n\t\treturn err;\n\n\tif (priv->soc->set_mac)\n\t\tpriv->soc->set_mac(priv, dev->dev_addr);\n\telse\n\t\tfe_hw_set_macaddr(priv, dev->dev_addr);\n\n\t/* disable delay interrupt */\n\tfe_reg_w32(0, FE_REG_DLY_INT_CFG);\n\n\tfe_int_disable(priv->soc->tx_int | priv->soc->rx_int);\n\n\t/* frame engine will push VLAN tag regarding to VIDX feild in Tx desc */\n\tif (fe_reg_table[FE_REG_FE_DMA_VID_BASE])\n\t\tfor (i = 0; i < 16; i += 2)\n\t\t\tfe_w32(((i + 1) << 16) + i,\n\t\t\t       fe_reg_table[FE_REG_FE_DMA_VID_BASE] +\n\t\t\t       (i * 2));\n\n\tif (priv->soc->fwd_config(priv))\n\t\tnetdev_err(dev, \"unable to get clock\\n\");\n\n\tif (fe_reg_table[FE_REG_FE_RST_GL]) {\n\t\tfe_reg_w32(1, FE_REG_FE_RST_GL);\n\t\tfe_reg_w32(0, FE_REG_FE_RST_GL);\n\t}\n\n\treturn 0;\n}\n\nstatic int fe_open(struct net_device *dev)\n{\n\tstruct fe_priv *priv = netdev_priv(dev);\n\tunsigned long flags;\n\tu32 val;\n\tint err;\n\n\terr = fe_init_dma(priv);\n\tif (err) {\n\t\tfe_free_dma(priv);\n\t\treturn err;\n\t}\n\n\tspin_lock_irqsave(&priv->page_lock, flags);\n\n\tval = FE_TX_WB_DDONE | FE_RX_DMA_EN | FE_TX_DMA_EN;\n\tif (priv->flags & FE_FLAG_RX_2B_OFFSET)\n\t\tval |= FE_RX_2B_OFFSET;\n\tval |= priv->soc->pdma_glo_cfg;\n\tfe_reg_w32(val, FE_REG_PDMA_GLO_CFG);\n\n\tspin_unlock_irqrestore(&priv->page_lock, flags);\n\n\tif (priv->phy)\n\t\tpriv->phy->start(priv);\n\n\tif (priv->soc->has_carrier && priv->soc->has_carrier(priv))\n\t\tnetif_carrier_on(dev);\n\n\tnapi_enable(&priv->rx_napi);\n\tfe_int_enable(priv->soc->tx_int | priv->soc->rx_int);\n\tnetif_start_queue(dev);\n\n\treturn 0;\n}\n\nstatic int fe_stop(struct net_device *dev)\n{\n\tstruct fe_priv *priv = netdev_priv(dev);\n\tunsigned long flags;\n\tint i;\n\n\tnetif_tx_disable(dev);\n\tfe_int_disable(priv->soc->tx_int | priv->soc->rx_int);\n\tnapi_disable(&priv->rx_napi);\n\n\tif (priv->phy)\n\t\tpriv->phy->stop(priv);\n\n\tspin_lock_irqsave(&priv->page_lock, flags);\n\n\tfe_reg_w32(fe_reg_r32(FE_REG_PDMA_GLO_CFG) &\n\t\t     ~(FE_TX_WB_DDONE | FE_RX_DMA_EN | FE_TX_DMA_EN),\n\t\t     FE_REG_PDMA_GLO_CFG);\n\tspin_unlock_irqrestore(&priv->page_lock, flags);\n\n\t/* wait dma stop */\n\tfor (i = 0; i < 10; i++) {\n\t\tif (fe_reg_r32(FE_REG_PDMA_GLO_CFG) &\n\t\t\t\t(FE_TX_DMA_BUSY | FE_RX_DMA_BUSY)) {\n\t\t\tmsleep(20);\n\t\t\tcontinue;\n\t\t}\n\t\tbreak;\n\t}\n\n\tfe_free_dma(priv);\n\n\treturn 0;\n}\n\nstatic void fe_reset_phy(struct fe_priv *priv)\n{\n\tint err, msec = 30;\n\tstruct gpio_desc *phy_reset;\n\n\tphy_reset = devm_gpiod_get_optional(priv->dev, \"phy-reset\",\n\t\t\t\t\t    GPIOD_OUT_HIGH);\n\tif (!phy_reset)\n\t\treturn;\n\n\tif (IS_ERR(phy_reset)) {\n\t\tdev_err(priv->dev, \"Error acquiring reset gpio pins: %ld\\n\",\n\t\t\tPTR_ERR(phy_reset));\n\t\treturn;\n\t}\n\n\terr = of_property_read_u32(priv->dev->of_node, \"phy-reset-duration\",\n\t\t\t\t   &msec);\n\tif (!err && msec > 1000)\n\t\tmsec = 30;\n\n\tif (msec > 20)\n\t\tmsleep(msec);\n\telse\n\t\tusleep_range(msec * 1000, msec * 1000 + 1000);\n\n\tgpiod_set_value(phy_reset, 0);\n}\n\nstatic int __init fe_init(struct net_device *dev)\n{\n\tstruct fe_priv *priv = netdev_priv(dev);\n\tstruct device_node *port;\n\tint err;\n\n\tif (priv->soc->reset_fe)\n\t\tpriv->soc->reset_fe(priv);\n\telse\n\t\tfe_reset_fe(priv);\n\n\tif (priv->soc->switch_init) {\n\t\terr = priv->soc->switch_init(priv);\n\t\tif (err) {\n\t\t\tif (err == -EPROBE_DEFER)\n\t\t\t\treturn err;\n\n\t\t\tnetdev_err(dev, \"failed to initialize switch core\\n\");\n\t\t\treturn -ENODEV;\n\t\t}\n\t}\n\n\tfe_reset_phy(priv);\n\n\tof_get_mac_address(priv->dev->of_node, dev->dev_addr);\n\n\t/* If the mac address is invalid, use random mac address  */\n\tif (!is_valid_ether_addr(dev->dev_addr)) {\n\t\teth_hw_addr_random(dev);\n\t\tdev_err(priv->dev, \"generated random MAC address %pM\\n\",\n\t\t\tdev->dev_addr);\n\t}\n\n\terr = fe_mdio_init(priv);\n\tif (err)\n\t\treturn err;\n\n\tif (priv->soc->port_init)\n\t\tfor_each_child_of_node(priv->dev->of_node, port)\n\t\t\tif (of_device_is_compatible(port, \"mediatek,eth-port\") &&\n\t\t\t    of_device_is_available(port))\n\t\t\t\tpriv->soc->port_init(priv, port);\n\n\tif (priv->phy) {\n\t\terr = priv->phy->connect(priv);\n\t\tif (err)\n\t\t\tgoto err_phy_disconnect;\n\t}\n\n\terr = fe_hw_init(dev);\n\tif (err)\n\t\tgoto err_phy_disconnect;\n\n\tif ((priv->flags & FE_FLAG_HAS_SWITCH) && priv->soc->switch_config)\n\t\tpriv->soc->switch_config(priv);\n\n\treturn 0;\n\nerr_phy_disconnect:\n\tif (priv->phy)\n\t\tpriv->phy->disconnect(priv);\n\tfe_mdio_cleanup(priv);\n\n\treturn err;\n}\n\nstatic void fe_uninit(struct net_device *dev)\n{\n\tstruct fe_priv *priv = netdev_priv(dev);\n\n\tif (priv->phy)\n\t\tpriv->phy->disconnect(priv);\n\tfe_mdio_cleanup(priv);\n\n\tfe_reg_w32(0, FE_REG_FE_INT_ENABLE);\n\tfree_irq(dev->irq, dev);\n}\n\nstatic int fe_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)\n{\n\tstruct fe_priv *priv = netdev_priv(dev);\n\n\tif (!priv->phy_dev)\n\t\treturn -ENODEV;\n\n\n\treturn phy_mii_ioctl(priv->phy_dev, ifr, cmd);\n}\n\nstatic int fe_change_mtu(struct net_device *dev, int new_mtu)\n{\n\tstruct fe_priv *priv = netdev_priv(dev);\n\tint frag_size, old_mtu;\n\tu32 fwd_cfg;\n\n\told_mtu = dev->mtu;\n\tdev->mtu = new_mtu;\n\n\tif (!(priv->flags & FE_FLAG_JUMBO_FRAME))\n\t\treturn 0;\n\n\t/* return early if the buffer sizes will not change */\n\tif (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)\n\t\treturn 0;\n\tif (old_mtu > ETH_DATA_LEN && new_mtu > ETH_DATA_LEN)\n\t\treturn 0;\n\n\tif (new_mtu <= ETH_DATA_LEN)\n\t\tpriv->rx_ring.frag_size = fe_max_frag_size(ETH_DATA_LEN);\n\telse\n\t\tpriv->rx_ring.frag_size = PAGE_SIZE;\n\tpriv->rx_ring.rx_buf_size = fe_max_buf_size(priv->rx_ring.frag_size);\n\n\tif (!netif_running(dev))\n\t\treturn 0;\n\n\tfe_stop(dev);\n\tif (!IS_ENABLED(CONFIG_SOC_MT7621)) {\n\t\tfwd_cfg = fe_r32(FE_GDMA1_FWD_CFG);\n\t\tif (new_mtu <= ETH_DATA_LEN) {\n\t\t\tfwd_cfg &= ~FE_GDM1_JMB_EN;\n\t\t} else {\n\t\t\tfrag_size = fe_max_frag_size(new_mtu);\n\t\t\tfwd_cfg &= ~(FE_GDM1_JMB_LEN_MASK << FE_GDM1_JMB_LEN_SHIFT);\n\t\t\tfwd_cfg |= (DIV_ROUND_UP(frag_size, 1024) <<\n\t\t\tFE_GDM1_JMB_LEN_SHIFT) | FE_GDM1_JMB_EN;\n\t\t}\n\t\tfe_w32(fwd_cfg, FE_GDMA1_FWD_CFG);\n\t}\n\n\treturn fe_open(dev);\n}\n\nstatic const struct net_device_ops fe_netdev_ops = {\n\t.ndo_init\t\t= fe_init,\n\t.ndo_uninit\t\t= fe_uninit,\n\t.ndo_open\t\t= fe_open,\n\t.ndo_stop\t\t= fe_stop,\n\t.ndo_start_xmit\t\t= fe_start_xmit,\n\t.ndo_set_mac_address\t= fe_set_mac_address,\n\t.ndo_validate_addr\t= eth_validate_addr,\n\t.ndo_do_ioctl\t\t= fe_do_ioctl,\n\t.ndo_change_mtu\t\t= fe_change_mtu,\n\t.ndo_tx_timeout\t\t= fe_tx_timeout,\n\t.ndo_get_stats64        = fe_get_stats64,\n\t.ndo_vlan_rx_add_vid\t= fe_vlan_rx_add_vid,\n\t.ndo_vlan_rx_kill_vid\t= fe_vlan_rx_kill_vid,\n#ifdef CONFIG_NET_POLL_CONTROLLER\n\t.ndo_poll_controller\t= fe_poll_controller,\n#endif\n};\n\nstatic void fe_reset_pending(struct fe_priv *priv)\n{\n\tstruct net_device *dev = priv->netdev;\n\tint err;\n\n\trtnl_lock();\n\tfe_stop(dev);\n\n\terr = fe_open(dev);\n\tif (err) {\n\t\tnetif_alert(priv, ifup, dev,\n\t\t\t    \"Driver up/down cycle failed, closing device.\\n\");\n\t\tdev_close(dev);\n\t}\n\trtnl_unlock();\n}\n\nstatic const struct fe_work_t fe_work[] = {\n\t{FE_FLAG_RESET_PENDING, fe_reset_pending},\n};\n\nstatic void fe_pending_work(struct work_struct *work)\n{\n\tstruct fe_priv *priv = container_of(work, struct fe_priv, pending_work);\n\tint i;\n\tbool pending;\n\n\tfor (i = 0; i < ARRAY_SIZE(fe_work); i++) {\n\t\tpending = test_and_clear_bit(fe_work[i].bitnr,\n\t\t\t\t\t     priv->pending_flags);\n\t\tif (pending)\n\t\t\tfe_work[i].action(priv);\n\t}\n}\n\nstatic int fe_probe(struct platform_device *pdev)\n{\n\tstruct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);\n\tconst struct of_device_id *match;\n\tstruct fe_soc_data *soc;\n\tstruct net_device *netdev;\n\tstruct fe_priv *priv;\n\tstruct clk *sysclk;\n\tint err, napi_weight;\n\n\tdevice_reset(&pdev->dev);\n\n\tmatch = of_match_device(of_fe_match, &pdev->dev);\n\tsoc = (struct fe_soc_data *)match->data;\n\n\tif (soc->reg_table)\n\t\tfe_reg_table = soc->reg_table;\n\telse\n\t\tsoc->reg_table = fe_reg_table;\n\n\tfe_base = devm_ioremap_resource(&pdev->dev, res);\n\tif (IS_ERR(fe_base)) {\n\t\terr = -EADDRNOTAVAIL;\n\t\tgoto err_out;\n\t}\n\n\tnetdev = alloc_etherdev(sizeof(*priv));\n\tif (!netdev) {\n\t\tdev_err(&pdev->dev, \"alloc_etherdev failed\\n\");\n\t\terr = -ENOMEM;\n\t\tgoto err_iounmap;\n\t}\n\n\tSET_NETDEV_DEV(netdev, &pdev->dev);\n\tnetdev->netdev_ops = &fe_netdev_ops;\n\tnetdev->base_addr = (unsigned long)fe_base;\n\n\tnetdev->irq = platform_get_irq(pdev, 0);\n\tif (netdev->irq < 0) {\n\t\tdev_err(&pdev->dev, \"no IRQ resource found\\n\");\n\t\terr = -ENXIO;\n\t\tgoto err_free_dev;\n\t}\n\n\tpriv = netdev_priv(netdev);\n\tspin_lock_init(&priv->page_lock);\n\tpriv->rst_fe = devm_reset_control_get(&pdev->dev, \"fe\");\n\tif (IS_ERR(priv->rst_fe))\n\t\tpriv->rst_fe = NULL;\n\n\tif (soc->init_data)\n\t\tsoc->init_data(soc, netdev);\n\tnetdev->vlan_features = netdev->hw_features &\n\t\t\t\t~(NETIF_F_HW_VLAN_CTAG_TX |\n\t\t\t\t  NETIF_F_HW_VLAN_CTAG_RX);\n\tnetdev->features |= netdev->hw_features;\n\n\tif (IS_ENABLED(CONFIG_SOC_MT7621))\n\t\tnetdev->max_mtu = 2048;\n\n\t/* fake rx vlan filter func. to support tx vlan offload func */\n\tif (fe_reg_table[FE_REG_FE_DMA_VID_BASE])\n\t\tnetdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;\n\n\tif (fe_reg_table[FE_REG_FE_COUNTER_BASE]) {\n\t\tpriv->hw_stats = kzalloc(sizeof(*priv->hw_stats), GFP_KERNEL);\n\t\tif (!priv->hw_stats) {\n\t\t\terr = -ENOMEM;\n\t\t\tgoto err_free_dev;\n\t\t}\n\t\tspin_lock_init(&priv->hw_stats->stats_lock);\n\t}\n\n\tsysclk = devm_clk_get(&pdev->dev, NULL);\n\tif (!IS_ERR(sysclk)) {\n\t\tpriv->sysclk = clk_get_rate(sysclk);\n\t} else if ((priv->flags & FE_FLAG_CALIBRATE_CLK)) {\n\t\tdev_err(&pdev->dev, \"this soc needs a clk for calibration\\n\");\n\t\terr = -ENXIO;\n\t\tgoto err_free_dev;\n\t}\n\n\tpriv->switch_np = of_parse_phandle(pdev->dev.of_node, \"mediatek,switch\", 0);\n\tif ((priv->flags & FE_FLAG_HAS_SWITCH) && !priv->switch_np) {\n\t\tdev_err(&pdev->dev, \"failed to read switch phandle\\n\");\n\t\terr = -ENODEV;\n\t\tgoto err_free_dev;\n\t}\n\n\tpriv->netdev = netdev;\n\tpriv->dev = &pdev->dev;\n\tpriv->soc = soc;\n\tpriv->msg_enable = netif_msg_init(fe_msg_level, FE_DEFAULT_MSG_ENABLE);\n\tpriv->rx_ring.frag_size = fe_max_frag_size(ETH_DATA_LEN);\n\tpriv->rx_ring.rx_buf_size = fe_max_buf_size(priv->rx_ring.frag_size);\n\tpriv->tx_ring.tx_ring_size = NUM_DMA_DESC;\n\tpriv->rx_ring.rx_ring_size = NUM_DMA_DESC;\n\tINIT_WORK(&priv->pending_work, fe_pending_work);\n\tu64_stats_init(&priv->hw_stats->syncp);\n\n\tnapi_weight = 16;\n\tif (priv->flags & FE_FLAG_NAPI_WEIGHT) {\n\t\tnapi_weight *= 4;\n\t\tpriv->tx_ring.tx_ring_size *= 4;\n\t\tpriv->rx_ring.rx_ring_size *= 4;\n\t}\n\tnetif_napi_add(netdev, &priv->rx_napi, fe_poll, napi_weight);\n\tfe_set_ethtool_ops(netdev);\n\n\terr = register_netdev(netdev);\n\tif (err) {\n\t\tdev_err(&pdev->dev, \"error bringing up device\\n\");\n\t\tgoto err_free_dev;\n\t}\n\n\tplatform_set_drvdata(pdev, netdev);\n\n\tnetif_info(priv, probe, netdev, \"mediatek frame engine at 0x%08lx, irq %d\\n\",\n\t\t   netdev->base_addr, netdev->irq);\n\n\treturn 0;\n\nerr_free_dev:\n\tfree_netdev(netdev);\nerr_iounmap:\n\tdevm_iounmap(&pdev->dev, fe_base);\nerr_out:\n\treturn err;\n}\n\nstatic int fe_remove(struct platform_device *pdev)\n{\n\tstruct net_device *dev = platform_get_drvdata(pdev);\n\tstruct fe_priv *priv = netdev_priv(dev);\n\n\tnetif_napi_del(&priv->rx_napi);\n\tkfree(priv->hw_stats);\n\n\tcancel_work_sync(&priv->pending_work);\n\n\tunregister_netdev(dev);\n\tfree_netdev(dev);\n\tplatform_set_drvdata(pdev, NULL);\n\n\treturn 0;\n}\n\nstatic struct platform_driver fe_driver = {\n\t.probe = fe_probe,\n\t.remove = fe_remove,\n\t.driver = {\n\t\t.name = \"mtk_soc_eth\",\n\t\t.owner = THIS_MODULE,\n\t\t.of_match_table = of_fe_match,\n\t},\n};\n\nmodule_platform_driver(fe_driver);\n\nMODULE_LICENSE(\"GPL\");\nMODULE_AUTHOR(\"John Crispin <blogic@openwrt.org>\");\nMODULE_DESCRIPTION(\"Ethernet driver for Ralink SoC\");\nMODULE_VERSION(MTK_FE_DRV_VERSION);\n"
  },
  {
    "path": "target/linux/ramips/files/drivers/net/ethernet/ralink/mtk_eth_soc.h",
    "content": "/*   This program is free software; you can redistribute it and/or modify\n *   it under the terms of the GNU General Public License as published by\n *   the Free Software Foundation; version 2 of the License\n *\n *   This program is distributed in the hope that it will be useful,\n *   but WITHOUT ANY WARRANTY; without even the implied warranty of\n *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n *   GNU General Public License for more details.\n *\n *   Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>\n *   Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>\n *   Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>\n */\n\n#ifndef FE_ETH_H\n#define FE_ETH_H\n\n#include <linux/mii.h>\n#include <linux/interrupt.h>\n#include <linux/netdevice.h>\n#include <linux/dma-mapping.h>\n#include <linux/phy.h>\n#include <linux/ethtool.h>\n#include <linux/version.h>\n\nenum fe_reg {\n\tFE_REG_PDMA_GLO_CFG = 0,\n\tFE_REG_PDMA_RST_CFG,\n\tFE_REG_DLY_INT_CFG,\n\tFE_REG_TX_BASE_PTR0,\n\tFE_REG_TX_MAX_CNT0,\n\tFE_REG_TX_CTX_IDX0,\n\tFE_REG_TX_DTX_IDX0,\n\tFE_REG_RX_BASE_PTR0,\n\tFE_REG_RX_MAX_CNT0,\n\tFE_REG_RX_CALC_IDX0,\n\tFE_REG_RX_DRX_IDX0,\n\tFE_REG_FE_INT_ENABLE,\n\tFE_REG_FE_INT_STATUS,\n\tFE_REG_FE_DMA_VID_BASE,\n\tFE_REG_FE_COUNTER_BASE,\n\tFE_REG_FE_RST_GL,\n\tFE_REG_FE_INT_STATUS2,\n\tFE_REG_COUNT\n};\n\nenum fe_work_flag {\n\tFE_FLAG_RESET_PENDING,\n\tFE_FLAG_MAX\n};\n\n#define MTK_FE_DRV_VERSION\t\t\"0.2\"\n\n/* power of 2 to let NEXT_TX_DESP_IDX work */\n#define NUM_DMA_DESC\t\tBIT(10)\n#define MAX_DMA_DESC\t\t0xfff\n\n#define FE_DELAY_EN_INT\t\t0x80\n#define FE_DELAY_MAX_INT\t0x04\n#define FE_DELAY_MAX_TOUT\t0x04\n#define FE_DELAY_TIME\t\t20\n#define FE_DELAY_CHAN\t\t(((FE_DELAY_EN_INT | FE_DELAY_MAX_INT) << 8) | \\\n\t\t\t\t FE_DELAY_MAX_TOUT)\n#define FE_DELAY_INIT\t\t((FE_DELAY_CHAN << 16) | FE_DELAY_CHAN)\n#define FE_PSE_FQFC_CFG_INIT\t0x80504000\n#define FE_PSE_FQFC_CFG_256Q\t0xff908000\n\n/* interrupt bits */\n#define FE_CNT_PPE_AF\t\tBIT(31)\n#define FE_CNT_GDM_AF\t\tBIT(29)\n#define FE_PSE_P2_FC\t\tBIT(26)\n#define FE_PSE_BUF_DROP\t\tBIT(24)\n#define FE_GDM_OTHER_DROP\tBIT(23)\n#define FE_PSE_P1_FC\t\tBIT(22)\n#define FE_PSE_P0_FC\t\tBIT(21)\n#define FE_PSE_FQ_EMPTY\t\tBIT(20)\n#define FE_GE1_STA_CHG\t\tBIT(18)\n#define FE_TX_COHERENT\t\tBIT(17)\n#define FE_RX_COHERENT\t\tBIT(16)\n#define FE_TX_DONE_INT3\t\tBIT(11)\n#define FE_TX_DONE_INT2\t\tBIT(10)\n#define FE_TX_DONE_INT1\t\tBIT(9)\n#define FE_TX_DONE_INT0\t\tBIT(8)\n#define FE_RX_DONE_INT0\t\tBIT(2)\n#define FE_TX_DLY_INT\t\tBIT(1)\n#define FE_RX_DLY_INT\t\tBIT(0)\n\n#define FE_RX_DONE_INT\t\tFE_RX_DONE_INT0\n#define FE_TX_DONE_INT\t\t(FE_TX_DONE_INT0 | FE_TX_DONE_INT1 | \\\n\t\t\t\t FE_TX_DONE_INT2 | FE_TX_DONE_INT3)\n\n#define RT5350_RX_DLY_INT\tBIT(30)\n#define RT5350_TX_DLY_INT\tBIT(28)\n#define RT5350_RX_DONE_INT1\tBIT(17)\n#define RT5350_RX_DONE_INT0\tBIT(16)\n#define RT5350_TX_DONE_INT3\tBIT(3)\n#define RT5350_TX_DONE_INT2\tBIT(2)\n#define RT5350_TX_DONE_INT1\tBIT(1)\n#define RT5350_TX_DONE_INT0\tBIT(0)\n\n#define RT5350_RX_DONE_INT\t(RT5350_RX_DONE_INT0 | RT5350_RX_DONE_INT1)\n#define RT5350_TX_DONE_INT\t(RT5350_TX_DONE_INT0 | RT5350_TX_DONE_INT1 | \\\n\t\t\t\t RT5350_TX_DONE_INT2 | RT5350_TX_DONE_INT3)\n\n/* registers */\n#define FE_FE_OFFSET\t\t0x0000\n#define FE_GDMA_OFFSET\t\t0x0020\n#define FE_PSE_OFFSET\t\t0x0040\n#define FE_GDMA2_OFFSET\t\t0x0060\n#define FE_CDMA_OFFSET\t\t0x0080\n#define FE_DMA_VID0\t\t0x00a8\n#define FE_PDMA_OFFSET\t\t0x0100\n#define FE_PPE_OFFSET\t\t0x0200\n#define FE_CMTABLE_OFFSET\t0x0400\n#define FE_POLICYTABLE_OFFSET\t0x1000\n\n#define RT5350_PDMA_OFFSET\t0x0800\n#define RT5350_SDM_OFFSET\t0x0c00\n\n#define FE_MDIO_ACCESS\t\t(FE_FE_OFFSET + 0x00)\n#define FE_MDIO_CFG\t\t(FE_FE_OFFSET + 0x04)\n#define FE_FE_GLO_CFG\t\t(FE_FE_OFFSET + 0x08)\n#define FE_FE_RST_GL\t\t(FE_FE_OFFSET + 0x0C)\n#define FE_FE_INT_STATUS\t(FE_FE_OFFSET + 0x10)\n#define FE_FE_INT_ENABLE\t(FE_FE_OFFSET + 0x14)\n#define FE_MDIO_CFG2\t\t(FE_FE_OFFSET + 0x18)\n#define FE_FOC_TS_T\t\t(FE_FE_OFFSET + 0x1C)\n\n#define\tFE_GDMA1_FWD_CFG\t(FE_GDMA_OFFSET + 0x00)\n#define FE_GDMA1_SCH_CFG\t(FE_GDMA_OFFSET + 0x04)\n#define FE_GDMA1_SHPR_CFG\t(FE_GDMA_OFFSET + 0x08)\n#define FE_GDMA1_MAC_ADRL\t(FE_GDMA_OFFSET + 0x0C)\n#define FE_GDMA1_MAC_ADRH\t(FE_GDMA_OFFSET + 0x10)\n\n#define\tFE_GDMA2_FWD_CFG\t(FE_GDMA2_OFFSET + 0x00)\n#define FE_GDMA2_SCH_CFG\t(FE_GDMA2_OFFSET + 0x04)\n#define FE_GDMA2_SHPR_CFG\t(FE_GDMA2_OFFSET + 0x08)\n#define FE_GDMA2_MAC_ADRL\t(FE_GDMA2_OFFSET + 0x0C)\n#define FE_GDMA2_MAC_ADRH\t(FE_GDMA2_OFFSET + 0x10)\n\n#define FE_PSE_FQ_CFG\t\t(FE_PSE_OFFSET + 0x00)\n#define FE_CDMA_FC_CFG\t\t(FE_PSE_OFFSET + 0x04)\n#define FE_GDMA1_FC_CFG\t\t(FE_PSE_OFFSET + 0x08)\n#define FE_GDMA2_FC_CFG\t\t(FE_PSE_OFFSET + 0x0C)\n\n#define FE_CDMA_CSG_CFG\t\t(FE_CDMA_OFFSET + 0x00)\n#define FE_CDMA_SCH_CFG\t\t(FE_CDMA_OFFSET + 0x04)\n\n#ifdef CONFIG_SOC_MT7621\n#define MT7620A_GDMA_OFFSET\t\t0x0500\n#else\n#define MT7620A_GDMA_OFFSET\t\t0x0600\n#endif\n#define\tMT7620A_GDMA1_FWD_CFG\t\t(MT7620A_GDMA_OFFSET + 0x00)\n#define MT7620A_FE_GDMA1_SCH_CFG\t(MT7620A_GDMA_OFFSET + 0x04)\n#define MT7620A_FE_GDMA1_SHPR_CFG\t(MT7620A_GDMA_OFFSET + 0x08)\n#define MT7620A_FE_GDMA1_MAC_ADRL\t(MT7620A_GDMA_OFFSET + 0x0C)\n#define MT7620A_FE_GDMA1_MAC_ADRH\t(MT7620A_GDMA_OFFSET + 0x10)\n\n#define MT7620A_RESET_FE\tBIT(21)\n#define MT7620A_RESET_ESW\tBIT(23)\n#define MT7620A_RESET_EPHY\tBIT(24)\n\n#define RT5350_TX_BASE_PTR0\t(RT5350_PDMA_OFFSET + 0x00)\n#define RT5350_TX_MAX_CNT0\t(RT5350_PDMA_OFFSET + 0x04)\n#define RT5350_TX_CTX_IDX0\t(RT5350_PDMA_OFFSET + 0x08)\n#define RT5350_TX_DTX_IDX0\t(RT5350_PDMA_OFFSET + 0x0C)\n#define RT5350_TX_BASE_PTR1\t(RT5350_PDMA_OFFSET + 0x10)\n#define RT5350_TX_MAX_CNT1\t(RT5350_PDMA_OFFSET + 0x14)\n#define RT5350_TX_CTX_IDX1\t(RT5350_PDMA_OFFSET + 0x18)\n#define RT5350_TX_DTX_IDX1\t(RT5350_PDMA_OFFSET + 0x1C)\n#define RT5350_TX_BASE_PTR2\t(RT5350_PDMA_OFFSET + 0x20)\n#define RT5350_TX_MAX_CNT2\t(RT5350_PDMA_OFFSET + 0x24)\n#define RT5350_TX_CTX_IDX2\t(RT5350_PDMA_OFFSET + 0x28)\n#define RT5350_TX_DTX_IDX2\t(RT5350_PDMA_OFFSET + 0x2C)\n#define RT5350_TX_BASE_PTR3\t(RT5350_PDMA_OFFSET + 0x30)\n#define RT5350_TX_MAX_CNT3\t(RT5350_PDMA_OFFSET + 0x34)\n#define RT5350_TX_CTX_IDX3\t(RT5350_PDMA_OFFSET + 0x38)\n#define RT5350_TX_DTX_IDX3\t(RT5350_PDMA_OFFSET + 0x3C)\n#define RT5350_RX_BASE_PTR0\t(RT5350_PDMA_OFFSET + 0x100)\n#define RT5350_RX_MAX_CNT0\t(RT5350_PDMA_OFFSET + 0x104)\n#define RT5350_RX_CALC_IDX0\t(RT5350_PDMA_OFFSET + 0x108)\n#define RT5350_RX_DRX_IDX0\t(RT5350_PDMA_OFFSET + 0x10C)\n#define RT5350_RX_BASE_PTR1\t(RT5350_PDMA_OFFSET + 0x110)\n#define RT5350_RX_MAX_CNT1\t(RT5350_PDMA_OFFSET + 0x114)\n#define RT5350_RX_CALC_IDX1\t(RT5350_PDMA_OFFSET + 0x118)\n#define RT5350_RX_DRX_IDX1\t(RT5350_PDMA_OFFSET + 0x11C)\n#define RT5350_PDMA_GLO_CFG\t(RT5350_PDMA_OFFSET + 0x204)\n#define RT5350_PDMA_RST_CFG\t(RT5350_PDMA_OFFSET + 0x208)\n#define RT5350_DLY_INT_CFG\t(RT5350_PDMA_OFFSET + 0x20c)\n#define RT5350_FE_INT_STATUS\t(RT5350_PDMA_OFFSET + 0x220)\n#define RT5350_FE_INT_ENABLE\t(RT5350_PDMA_OFFSET + 0x228)\n#define RT5350_PDMA_SCH_CFG\t(RT5350_PDMA_OFFSET + 0x280)\n\n#define FE_PDMA_GLO_CFG\t\t(FE_PDMA_OFFSET + 0x00)\n#define FE_PDMA_RST_CFG\t\t(FE_PDMA_OFFSET + 0x04)\n#define FE_PDMA_SCH_CFG\t\t(FE_PDMA_OFFSET + 0x08)\n#define FE_DLY_INT_CFG\t\t(FE_PDMA_OFFSET + 0x0C)\n#define FE_TX_BASE_PTR0\t\t(FE_PDMA_OFFSET + 0x10)\n#define FE_TX_MAX_CNT0\t\t(FE_PDMA_OFFSET + 0x14)\n#define FE_TX_CTX_IDX0\t\t(FE_PDMA_OFFSET + 0x18)\n#define FE_TX_DTX_IDX0\t\t(FE_PDMA_OFFSET + 0x1C)\n#define FE_TX_BASE_PTR1\t\t(FE_PDMA_OFFSET + 0x20)\n#define FE_TX_MAX_CNT1\t\t(FE_PDMA_OFFSET + 0x24)\n#define FE_TX_CTX_IDX1\t\t(FE_PDMA_OFFSET + 0x28)\n#define FE_TX_DTX_IDX1\t\t(FE_PDMA_OFFSET + 0x2C)\n#define FE_RX_BASE_PTR0\t\t(FE_PDMA_OFFSET + 0x30)\n#define FE_RX_MAX_CNT0\t\t(FE_PDMA_OFFSET + 0x34)\n#define FE_RX_CALC_IDX0\t\t(FE_PDMA_OFFSET + 0x38)\n#define FE_RX_DRX_IDX0\t\t(FE_PDMA_OFFSET + 0x3C)\n#define FE_TX_BASE_PTR2\t\t(FE_PDMA_OFFSET + 0x40)\n#define FE_TX_MAX_CNT2\t\t(FE_PDMA_OFFSET + 0x44)\n#define FE_TX_CTX_IDX2\t\t(FE_PDMA_OFFSET + 0x48)\n#define FE_TX_DTX_IDX2\t\t(FE_PDMA_OFFSET + 0x4C)\n#define FE_TX_BASE_PTR3\t\t(FE_PDMA_OFFSET + 0x50)\n#define FE_TX_MAX_CNT3\t\t(FE_PDMA_OFFSET + 0x54)\n#define FE_TX_CTX_IDX3\t\t(FE_PDMA_OFFSET + 0x58)\n#define FE_TX_DTX_IDX3\t\t(FE_PDMA_OFFSET + 0x5C)\n#define FE_RX_BASE_PTR1\t\t(FE_PDMA_OFFSET + 0x60)\n#define FE_RX_MAX_CNT1\t\t(FE_PDMA_OFFSET + 0x64)\n#define FE_RX_CALC_IDX1\t\t(FE_PDMA_OFFSET + 0x68)\n#define FE_RX_DRX_IDX1\t\t(FE_PDMA_OFFSET + 0x6C)\n\n/* Switch DMA configuration */\n#define RT5350_SDM_CFG\t\t(RT5350_SDM_OFFSET + 0x00)\n#define RT5350_SDM_RRING\t(RT5350_SDM_OFFSET + 0x04)\n#define RT5350_SDM_TRING\t(RT5350_SDM_OFFSET + 0x08)\n#define RT5350_SDM_MAC_ADRL\t(RT5350_SDM_OFFSET + 0x0C)\n#define RT5350_SDM_MAC_ADRH\t(RT5350_SDM_OFFSET + 0x10)\n#define RT5350_SDM_TPCNT\t(RT5350_SDM_OFFSET + 0x100)\n#define RT5350_SDM_TBCNT\t(RT5350_SDM_OFFSET + 0x104)\n#define RT5350_SDM_RPCNT\t(RT5350_SDM_OFFSET + 0x108)\n#define RT5350_SDM_RBCNT\t(RT5350_SDM_OFFSET + 0x10C)\n#define RT5350_SDM_CS_ERR\t(RT5350_SDM_OFFSET + 0x110)\n\n#define RT5350_SDM_ICS_EN\tBIT(16)\n#define RT5350_SDM_TCS_EN\tBIT(17)\n#define RT5350_SDM_UCS_EN\tBIT(18)\n\n/* MDIO_CFG register bits */\n#define FE_MDIO_CFG_AUTO_POLL_EN\tBIT(29)\n#define FE_MDIO_CFG_GP1_BP_EN\t\tBIT(16)\n#define FE_MDIO_CFG_GP1_FRC_EN\t\tBIT(15)\n#define FE_MDIO_CFG_GP1_SPEED_10\t(0 << 13)\n#define FE_MDIO_CFG_GP1_SPEED_100\t(1 << 13)\n#define FE_MDIO_CFG_GP1_SPEED_1000\t(2 << 13)\n#define FE_MDIO_CFG_GP1_DUPLEX\t\tBIT(12)\n#define FE_MDIO_CFG_GP1_FC_TX\t\tBIT(11)\n#define FE_MDIO_CFG_GP1_FC_RX\t\tBIT(10)\n#define FE_MDIO_CFG_GP1_LNK_DWN\t\tBIT(9)\n#define FE_MDIO_CFG_GP1_AN_FAIL\t\tBIT(8)\n#define FE_MDIO_CFG_MDC_CLK_DIV_1\t(0 << 6)\n#define FE_MDIO_CFG_MDC_CLK_DIV_2\t(1 << 6)\n#define FE_MDIO_CFG_MDC_CLK_DIV_4\t(2 << 6)\n#define FE_MDIO_CFG_MDC_CLK_DIV_8\t(3 << 6)\n#define FE_MDIO_CFG_TURBO_MII_FREQ\tBIT(5)\n#define FE_MDIO_CFG_TURBO_MII_MODE\tBIT(4)\n#define FE_MDIO_CFG_RX_CLK_SKEW_0\t(0 << 2)\n#define FE_MDIO_CFG_RX_CLK_SKEW_200\t(1 << 2)\n#define FE_MDIO_CFG_RX_CLK_SKEW_400\t(2 << 2)\n#define FE_MDIO_CFG_RX_CLK_SKEW_INV\t(3 << 2)\n#define FE_MDIO_CFG_TX_CLK_SKEW_0\t0\n#define FE_MDIO_CFG_TX_CLK_SKEW_200\t1\n#define FE_MDIO_CFG_TX_CLK_SKEW_400\t2\n#define FE_MDIO_CFG_TX_CLK_SKEW_INV\t3\n\n/* uni-cast port */\n#define FE_GDM1_JMB_LEN_MASK\t0xf\n#define FE_GDM1_JMB_LEN_SHIFT\t28\n#define FE_GDM1_ICS_EN\t\tBIT(22)\n#define FE_GDM1_TCS_EN\t\tBIT(21)\n#define FE_GDM1_UCS_EN\t\tBIT(20)\n#define FE_GDM1_JMB_EN\t\tBIT(19)\n#define FE_GDM1_STRPCRC\t\tBIT(16)\n#define FE_GDM1_UFRC_P_CPU\t(0 << 12)\n#define FE_GDM1_UFRC_P_GDMA1\t(1 << 12)\n#define FE_GDM1_UFRC_P_PPE\t(6 << 12)\n\n/* checksums */\n#define FE_ICS_GEN_EN\t\tBIT(2)\n#define FE_UCS_GEN_EN\t\tBIT(1)\n#define FE_TCS_GEN_EN\t\tBIT(0)\n\n/* dma ring */\n#define FE_PST_DRX_IDX0\t\tBIT(16)\n#define FE_PST_DTX_IDX3\t\tBIT(3)\n#define FE_PST_DTX_IDX2\t\tBIT(2)\n#define FE_PST_DTX_IDX1\t\tBIT(1)\n#define FE_PST_DTX_IDX0\t\tBIT(0)\n\n#define FE_RX_2B_OFFSET\t\tBIT(31)\n#define FE_TX_WB_DDONE\t\tBIT(6)\n#define FE_RX_DMA_BUSY\t\tBIT(3)\n#define FE_TX_DMA_BUSY\t\tBIT(1)\n#define FE_RX_DMA_EN\t\tBIT(2)\n#define FE_TX_DMA_EN\t\tBIT(0)\n\n#define FE_PDMA_SIZE_4DWORDS\t(0 << 4)\n#define FE_PDMA_SIZE_8DWORDS\t(1 << 4)\n#define FE_PDMA_SIZE_16DWORDS\t(2 << 4)\n\n#define FE_US_CYC_CNT_MASK\t0xff\n#define FE_US_CYC_CNT_SHIFT\t0x8\n#define FE_US_CYC_CNT_DIVISOR\t1000000\n\n/* rxd2 */\n#define RX_DMA_DONE\t\tBIT(31)\n#define RX_DMA_LSO\t\tBIT(30)\n#define RX_DMA_PLEN0(_x)\t(((_x) & 0x3fff) << 16)\n#define RX_DMA_GET_PLEN0(_x)\t(((_x) >> 16) & 0x3fff)\n#define RX_DMA_TAG\t\tBIT(15)\n/* rxd3 */\n#define RX_DMA_TPID(_x)\t\t(((_x) >> 16) & 0xffff)\n#define RX_DMA_VID(_x)\t\t((_x) & 0xffff)\n/* rxd4 */\n#define RX_DMA_L4VALID\t\tBIT(30)\n\nstruct fe_rx_dma {\n\tunsigned int rxd1;\n\tunsigned int rxd2;\n\tunsigned int rxd3;\n\tunsigned int rxd4;\n} __packed __aligned(4);\n\n#define TX_DMA_BUF_LEN\t\t0x3fff\n#define TX_DMA_PLEN0_MASK\t(TX_DMA_BUF_LEN << 16)\n#define TX_DMA_PLEN0(_x)\t(((_x) & TX_DMA_BUF_LEN) << 16)\n#define TX_DMA_PLEN1(_x)\t((_x) & TX_DMA_BUF_LEN)\n#define TX_DMA_GET_PLEN0(_x)    (((_x) >> 16) & TX_DMA_BUF_LEN)\n#define TX_DMA_GET_PLEN1(_x)    ((_x) & TX_DMA_BUF_LEN)\n#define TX_DMA_LS1\t\tBIT(14)\n#define TX_DMA_LS0\t\tBIT(30)\n#define TX_DMA_DONE\t\tBIT(31)\n\n#define TX_DMA_INS_VLAN_MT7621\tBIT(16)\n#define TX_DMA_INS_VLAN\t\tBIT(7)\n#define TX_DMA_INS_PPPOE\tBIT(12)\n#define TX_DMA_QN(_x)\t\t((_x) << 16)\n#define TX_DMA_PN(_x)\t\t((_x) << 24)\n#define TX_DMA_QN_MASK\t\tTX_DMA_QN(0x7)\n#define TX_DMA_PN_MASK\t\tTX_DMA_PN(0x7)\n#define TX_DMA_UDF\t\tBIT(20)\n#define TX_DMA_CHKSUM\t\t(0x7 << 29)\n#define TX_DMA_TSO\t\tBIT(28)\n\n/* frame engine counters */\n#define FE_PPE_AC_BCNT0\t\t(FE_CMTABLE_OFFSET + 0x00)\n#define FE_GDMA1_TX_GBCNT\t(FE_CMTABLE_OFFSET + 0x300)\n#define FE_GDMA2_TX_GBCNT\t(FE_GDMA1_TX_GBCNT + 0x40)\n\n/* phy device flags */\n#define FE_PHY_FLAG_PORT\tBIT(0)\n#define FE_PHY_FLAG_ATTACH\tBIT(1)\n\nstruct fe_tx_dma {\n\tunsigned int txd1;\n\tunsigned int txd2;\n\tunsigned int txd3;\n\tunsigned int txd4;\n} __packed __aligned(4);\n\nstruct fe_priv;\n\nstruct fe_phy {\n\t/* make sure that phy operations are atomic */\n\tspinlock_t\t\tlock;\n\n\tstruct phy_device\t*phy[8];\n\tstruct device_node\t*phy_node[8];\n\tconst __be32\t\t*phy_fixed[8];\n\tint\t\t\tduplex[8];\n\tint\t\t\tspeed[8];\n\tint\t\t\ttx_fc[8];\n\tint\t\t\trx_fc[8];\n\tint (*connect)(struct fe_priv *priv);\n\tvoid (*disconnect)(struct fe_priv *priv);\n\tvoid (*start)(struct fe_priv *priv);\n\tvoid (*stop)(struct fe_priv *priv);\n};\n\nstruct fe_soc_data {\n\tconst u16 *reg_table;\n\n\tvoid (*init_data)(struct fe_soc_data *data, struct net_device *netdev);\n\tvoid (*reset_fe)(struct fe_priv *priv);\n\tvoid (*set_mac)(struct fe_priv *priv, unsigned char *mac);\n\tint (*fwd_config)(struct fe_priv *priv);\n\tvoid (*tx_dma)(struct fe_tx_dma *txd);\n\tint (*switch_init)(struct fe_priv *priv);\n\tint (*switch_config)(struct fe_priv *priv);\n\tvoid (*port_init)(struct fe_priv *priv, struct device_node *port);\n\tint (*has_carrier)(struct fe_priv *priv);\n\tint (*mdio_init)(struct fe_priv *priv);\n\tvoid (*mdio_cleanup)(struct fe_priv *priv);\n\tint (*mdio_write)(struct mii_bus *bus, int phy_addr, int phy_reg,\n\t\t\t  u16 val);\n\tint (*mdio_read)(struct mii_bus *bus, int phy_addr, int phy_reg);\n\tvoid (*mdio_adjust_link)(struct fe_priv *priv, int port);\n\n\tvoid *swpriv;\n\tu32 pdma_glo_cfg;\n\tu32 rx_int;\n\tu32 tx_int;\n\tu32 status_int;\n\tu32 checksum_bit;\n};\n\n#define FE_FLAG_PADDING_64B\t\tBIT(0)\n#define FE_FLAG_PADDING_BUG\t\tBIT(1)\n#define FE_FLAG_JUMBO_FRAME\t\tBIT(2)\n#define FE_FLAG_RX_2B_OFFSET\t\tBIT(3)\n#define FE_FLAG_RX_SG_DMA\t\tBIT(4)\n#define FE_FLAG_NAPI_WEIGHT\t\tBIT(6)\n#define FE_FLAG_CALIBRATE_CLK\t\tBIT(7)\n#define FE_FLAG_HAS_SWITCH\t\tBIT(8)\n\n#define FE_STAT_REG_DECLARE\t\t\\\n\t_FE(tx_bytes)\t\t\t\\\n\t_FE(tx_packets)\t\t\t\\\n\t_FE(tx_skip)\t\t\t\\\n\t_FE(tx_collisions)\t\t\\\n\t_FE(rx_bytes)\t\t\t\\\n\t_FE(rx_packets)\t\t\t\\\n\t_FE(rx_overflow)\t\t\\\n\t_FE(rx_fcs_errors)\t\t\\\n\t_FE(rx_short_errors)\t\t\\\n\t_FE(rx_long_errors)\t\t\\\n\t_FE(rx_checksum_errors)\t\t\\\n\t_FE(rx_flow_control_packets)\n\nstruct fe_hw_stats {\n\t/* make sure that stats operations are atomic */\n\tspinlock_t stats_lock;\n\n\tstruct u64_stats_sync syncp;\n#define _FE(x) u64 x;\n\tFE_STAT_REG_DECLARE\n#undef _FE\n};\n\nstruct fe_tx_buf {\n\tstruct sk_buff *skb;\n\tDEFINE_DMA_UNMAP_ADDR(dma_addr0);\n\tDEFINE_DMA_UNMAP_ADDR(dma_addr1);\n\tu16 dma_len0;\n\tu16 dma_len1;\n};\n\nstruct fe_tx_ring {\n\tstruct fe_tx_dma *tx_dma;\n\tstruct fe_tx_buf *tx_buf;\n\tdma_addr_t tx_phys;\n\tu16 tx_ring_size;\n\tu16 tx_free_idx;\n\tu16 tx_next_idx;\n\tu16 tx_thresh;\n};\n\nstruct fe_rx_ring {\n\tstruct page_frag_cache frag_cache;\n\tstruct fe_rx_dma *rx_dma;\n\tu8 **rx_data;\n\tdma_addr_t rx_phys;\n\tu16 rx_ring_size;\n\tu16 frag_size;\n\tu16 rx_buf_size;\n\tu16 rx_calc_idx;\n};\n\nstruct fe_priv {\n\t/* make sure that register operations are atomic */\n\tspinlock_t\t\t\tpage_lock;\n\n\tstruct fe_soc_data\t\t*soc;\n\tstruct net_device\t\t*netdev;\n\tstruct device_node\t\t*switch_np;\n\tu32\t\t\t\tmsg_enable;\n\tu32\t\t\t\tflags;\n\n\tstruct device\t\t\t*dev;\n\tunsigned long\t\t\tsysclk;\n\n\tstruct fe_rx_ring\t\trx_ring;\n\tstruct napi_struct\t\trx_napi;\n\n\tstruct fe_tx_ring               tx_ring;\n\n\tstruct fe_phy\t\t\t*phy;\n\tstruct mii_bus\t\t\t*mii_bus;\n\tstruct phy_device\t\t*phy_dev;\n\tu32\t\t\t\tphy_flags;\n\n\tint\t\t\t\tlink[8];\n\n\tstruct fe_hw_stats\t\t*hw_stats;\n\tunsigned long\t\t\tvlan_map;\n\tstruct work_struct\t\tpending_work;\n\tDECLARE_BITMAP(pending_flags, FE_FLAG_MAX);\n\n\tstruct reset_control\t\t*rst_ppe;\n\tstruct reset_control\t\t*rst_fe;\n\tstruct mtk_foe_entry\t\t*foe_table;\n\tdma_addr_t\t\t\tfoe_table_phys;\n\tstruct flow_offload __rcu\t**foe_flow_table;\n};\n\nextern const struct of_device_id of_fe_match[];\n\nvoid fe_w32(u32 val, unsigned reg);\nvoid fe_m32(struct fe_priv *priv, u32 clear, u32 set, unsigned reg);\nu32 fe_r32(unsigned reg);\n\nint fe_set_clock_cycle(struct fe_priv *priv);\nvoid fe_csum_config(struct fe_priv *priv);\nvoid fe_stats_update(struct fe_priv *priv);\nvoid fe_fwd_config(struct fe_priv *priv);\nvoid fe_reg_w32(u32 val, enum fe_reg reg);\nu32 fe_reg_r32(enum fe_reg reg);\n\nvoid fe_reset(u32 reset_bits);\nvoid fe_reset_fe(struct fe_priv *priv);\n\nstatic inline void *priv_netdev(struct fe_priv *priv)\n{\n\treturn (char *)priv - ALIGN(sizeof(struct net_device), NETDEV_ALIGN);\n}\n\n\n#endif /* FE_ETH_H */\n"
  },
  {
    "path": "target/linux/ramips/files/drivers/net/ethernet/ralink/soc_mt7620.c",
    "content": "/*   This program is free software; you can redistribute it and/or modify\n *   it under the terms of the GNU General Public License as published by\n *   the Free Software Foundation; version 2 of the License\n *\n *   This program is distributed in the hope that it will be useful,\n *   but WITHOUT ANY WARRANTY; without even the implied warranty of\n *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n *   GNU General Public License for more details.\n *\n *   Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>\n *   Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>\n *   Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>\n */\n\n#include <linux/module.h>\n#include <linux/platform_device.h>\n#include <linux/if_vlan.h>\n#include <linux/of_net.h>\n\n#include <asm/mach-ralink/ralink_regs.h>\n\n#include <mt7620.h>\n#include \"mtk_eth_soc.h\"\n#include \"gsw_mt7620.h\"\n#include \"mt7530.h\"\n#include \"mdio.h\"\n\n#define MT7620A_CDMA_CSG_CFG\t0x400\n#define MT7620_DMA_VID\t\t(MT7620A_CDMA_CSG_CFG | 0x30)\n#define MT7620_L4_VALID\t\tBIT(23)\n\n#define MT7620_TX_DMA_UDF\tBIT(15)\n#define TX_DMA_FP_BMAP\t\t((0xff) << 19)\n\n#define CDMA_ICS_EN\t\tBIT(2)\n#define CDMA_UCS_EN\t\tBIT(1)\n#define CDMA_TCS_EN\t\tBIT(0)\n\n#define GDMA_ICS_EN\t\tBIT(22)\n#define GDMA_TCS_EN\t\tBIT(21)\n#define GDMA_UCS_EN\t\tBIT(20)\n\n/* frame engine counters */\n#define MT7620_REG_MIB_OFFSET\t0x1000\n#define MT7620_PPE_AC_BCNT0\t(MT7620_REG_MIB_OFFSET + 0x00)\n#define MT7620_GDM1_TX_GBCNT\t(MT7620_REG_MIB_OFFSET + 0x300)\n#define MT7620_GDM2_TX_GBCNT\t(MT7620_GDM1_TX_GBCNT + 0x40)\n\n#define GSW_REG_GDMA1_MAC_ADRL\t0x508\n#define GSW_REG_GDMA1_MAC_ADRH\t0x50C\n\n#define MT7621_FE_RST_GL\t(FE_FE_OFFSET + 0x04)\n#define MT7620_FE_INT_STATUS2\t(FE_FE_OFFSET + 0x08)\n\n/* FE_INT_STATUS reg on mt7620 define CNT_GDM1_AF at BIT(29)\n * but after test it should be BIT(13).\n */\n#define MT7620_FE_GDM1_AF\tBIT(13)\n\nstatic const u16 mt7620_reg_table[FE_REG_COUNT] = {\n\t[FE_REG_PDMA_GLO_CFG] = RT5350_PDMA_GLO_CFG,\n\t[FE_REG_PDMA_RST_CFG] = RT5350_PDMA_RST_CFG,\n\t[FE_REG_DLY_INT_CFG] = RT5350_DLY_INT_CFG,\n\t[FE_REG_TX_BASE_PTR0] = RT5350_TX_BASE_PTR0,\n\t[FE_REG_TX_MAX_CNT0] = RT5350_TX_MAX_CNT0,\n\t[FE_REG_TX_CTX_IDX0] = RT5350_TX_CTX_IDX0,\n\t[FE_REG_TX_DTX_IDX0] = RT5350_TX_DTX_IDX0,\n\t[FE_REG_RX_BASE_PTR0] = RT5350_RX_BASE_PTR0,\n\t[FE_REG_RX_MAX_CNT0] = RT5350_RX_MAX_CNT0,\n\t[FE_REG_RX_CALC_IDX0] = RT5350_RX_CALC_IDX0,\n\t[FE_REG_RX_DRX_IDX0] = RT5350_RX_DRX_IDX0,\n\t[FE_REG_FE_INT_ENABLE] = RT5350_FE_INT_ENABLE,\n\t[FE_REG_FE_INT_STATUS] = RT5350_FE_INT_STATUS,\n\t[FE_REG_FE_DMA_VID_BASE] = MT7620_DMA_VID,\n\t[FE_REG_FE_COUNTER_BASE] = MT7620_GDM1_TX_GBCNT,\n\t[FE_REG_FE_RST_GL] = MT7621_FE_RST_GL,\n\t[FE_REG_FE_INT_STATUS2] = MT7620_FE_INT_STATUS2,\n};\n\nstatic int mt7620_gsw_config(struct fe_priv *priv)\n{\n\tstruct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;\n\tu32 val;\n\n\t/* is the mt7530 internal or external */\n\tif (priv->mii_bus && mdiobus_get_phy(priv->mii_bus, 0x1f)) {\n\t\tmt7530_probe(priv->dev, gsw->base, NULL, 0);\n\t\tmt7530_probe(priv->dev, NULL, priv->mii_bus, 1);\n\n\t\t/* magic values from original SDK */\n\t\tval = mt7530_mdio_r32(gsw, 0x7830);\n\t\tval &= ~BIT(0);\n\t\tval |= BIT(1);\n\t\tmt7530_mdio_w32(gsw, 0x7830, val);\n\n\t\tval = mt7530_mdio_r32(gsw, 0x7a40);\n\t\tval &= ~BIT(30);\n\t\tmt7530_mdio_w32(gsw, 0x7a40, val);\n\n\t\tmt7530_mdio_w32(gsw, 0x7a78, 0x855);\n\n\t\tpr_info(\"mt7530: mdio central align\\n\");\n\t} else {\n\t\tmt7530_probe(priv->dev, gsw->base, NULL, 1);\n\t}\n\n\treturn 0;\n}\n\nstatic void mt7620_set_mac(struct fe_priv *priv, unsigned char *mac)\n{\n\tstruct mt7620_gsw *gsw = (struct mt7620_gsw *)priv->soc->swpriv;\n\tunsigned long flags;\n\n\tspin_lock_irqsave(&priv->page_lock, flags);\n\tmtk_switch_w32(gsw, (mac[0] << 8) | mac[1], GSW_REG_SMACCR1);\n\tmtk_switch_w32(gsw, (mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],\n\t\tGSW_REG_SMACCR0);\n\tspin_unlock_irqrestore(&priv->page_lock, flags);\n}\n\nstatic void mt7620_auto_poll(struct mt7620_gsw *gsw, int port)\n{\n\tint phy;\n\tint lsb = -1, msb = 0;\n\n\tfor_each_set_bit(phy, &gsw->autopoll, 32) {\n\t\tif (lsb < 0)\n\t\t\tlsb = phy;\n\t\tmsb = phy;\n\t}\n\n\tif (lsb == msb && port ==  4)\n\t\tmsb++;\n\telse if (lsb == msb && port ==  5)\n\t\tlsb--;\n\n\tmtk_switch_w32(gsw, PHY_AN_EN | PHY_PRE_EN | PMY_MDC_CONF(5) |\n\t\t(msb << 8) | lsb, ESW_PHY_POLLING);\n}\n\nstatic void mt7620_port_init(struct fe_priv *priv, struct device_node *np)\n{\n\tstruct mt7620_gsw *gsw = (struct mt7620_gsw *)priv->soc->swpriv;\n\tconst __be32 *_id = of_get_property(np, \"reg\", NULL);\n\tconst __be32 *phy_addr;\n#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0)\n\tint phy_mode;\n#else\n\tphy_interface_t phy_mode = PHY_INTERFACE_MODE_NA;\n#endif\n\tint size, id;\n\tint shift = 12;\n\tu32 val, mask = 0;\n\tu32 val_delay = 0;\n\tu32 mask_delay = GSW_REG_GPCx_TXDELAY | GSW_REG_GPCx_RXDELAY;\n\tint min = (gsw->port4_ephy) ? (5) : (4);\n\n\tif (!_id || (be32_to_cpu(*_id) < min) || (be32_to_cpu(*_id) > 5)) {\n\t\tif (_id)\n\t\t\tpr_err(\"%s: invalid port id %d\\n\", np->name,\n\t\t\t       be32_to_cpu(*_id));\n\t\telse\n\t\t\tpr_err(\"%s: invalid port id\\n\", np->name);\n\t\treturn;\n\t}\n\n\tid = be32_to_cpu(*_id);\n\n\tif (id == 4)\n\t\tshift = 14;\n\n\tpriv->phy->phy_fixed[id] = of_get_property(np, \"mediatek,fixed-link\",\n\t\t\t\t\t\t   &size);\n\tif (priv->phy->phy_fixed[id] &&\n\t    (size != (4 * sizeof(*priv->phy->phy_fixed[id])))) {\n\t\tpr_err(\"%s: invalid fixed link property\\n\", np->name);\n\t\tpriv->phy->phy_fixed[id] = NULL;\n\t}\n\n#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0)\n\tphy_mode = of_get_phy_mode(np);\n#else\n\tof_get_phy_mode(np, &phy_mode);\n#endif\n\tswitch (phy_mode) {\n\tcase PHY_INTERFACE_MODE_RGMII:\n\t\tmask = 0;\n\t\t/* Do not touch rx/tx delay in this state to avoid problems with\n\t\t * backward compability.\n\t\t */\n\t\tmask_delay = 0;\n\t\tbreak;\n\tcase PHY_INTERFACE_MODE_RGMII_ID:\n\t\tmask = 0;\n\t\tval_delay |= GSW_REG_GPCx_TXDELAY;\n\t\tval_delay &= ~GSW_REG_GPCx_RXDELAY;\n\t\tbreak;\n\tcase PHY_INTERFACE_MODE_RGMII_RXID:\n\t\tmask = 0;\n\t\tval_delay &= ~GSW_REG_GPCx_TXDELAY;\n\t\tval_delay &= ~GSW_REG_GPCx_RXDELAY;\n\t\tbreak;\n\tcase PHY_INTERFACE_MODE_RGMII_TXID:\n\t\tmask = 0;\n\t\tval_delay |= GSW_REG_GPCx_TXDELAY;\n\t\tval_delay |= GSW_REG_GPCx_RXDELAY;\n\t\tbreak;\n\tcase PHY_INTERFACE_MODE_MII:\n\t\tmask = 1;\n\t\tbreak;\n\tcase PHY_INTERFACE_MODE_RMII:\n\t\tmask = 2;\n\t\tbreak;\n\tdefault:\n\t\tdev_err(priv->dev, \"port %d - invalid phy mode\\n\", id);\n\t\treturn;\n\t}\n\n\tval = rt_sysc_r32(SYSC_REG_CFG1);\n\tval &= ~(3 << shift);\n\tval |= mask << shift;\n\trt_sysc_w32(val, SYSC_REG_CFG1);\n\n\tif (id == 4) {\n\t\tval = mtk_switch_r32(gsw, GSW_REG_GPC2);\n\t\tval &= ~(mask_delay);\n\t\tval |= val_delay & mask_delay;\n\t\tmtk_switch_w32(gsw, val, GSW_REG_GPC2);\n\t}\n\telse if (id == 5) {\n\t\tval = mtk_switch_r32(gsw, GSW_REG_GPC1);\n\t\tval &= ~(mask_delay);\n\t\tval |= val_delay & mask_delay;\n\t\tmtk_switch_w32(gsw, val, GSW_REG_GPC1);\n\t}\n\n\tif (priv->phy->phy_fixed[id]) {\n\t\tconst __be32 *link = priv->phy->phy_fixed[id];\n\t\tint tx_fc, rx_fc;\n\t\tu32 val = 0;\n\n\t\tpriv->phy->speed[id] = be32_to_cpup(link++);\n\t\ttx_fc = be32_to_cpup(link++);\n\t\trx_fc = be32_to_cpup(link++);\n\t\tpriv->phy->duplex[id] = be32_to_cpup(link++);\n\t\tpriv->link[id] = 1;\n\n\t\tswitch (priv->phy->speed[id]) {\n\t\tcase SPEED_10:\n\t\t\tval = 0;\n\t\t\tbreak;\n\t\tcase SPEED_100:\n\t\t\tval = 1;\n\t\t\tbreak;\n\t\tcase SPEED_1000:\n\t\t\tval = 2;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tdev_err(priv->dev, \"port %d - invalid link speed: %d\\n\",\n\t\t\t\tid, priv->phy->speed[id]);\n\t\t\tpriv->phy->phy_fixed[id] = 0;\n\t\t\treturn;\n\t\t}\n\t\tval = PMCR_SPEED(val);\n\t\tval |= PMCR_LINK | PMCR_BACKPRES | PMCR_BACKOFF | PMCR_RX_EN |\n\t\t\tPMCR_TX_EN | PMCR_FORCE | PMCR_MAC_MODE | PMCR_IPG;\n\t\tif (tx_fc)\n\t\t\tval |= PMCR_TX_FC;\n\t\tif (rx_fc)\n\t\t\tval |= PMCR_RX_FC;\n\t\tif (priv->phy->duplex[id])\n\t\t\tval |= PMCR_DUPLEX;\n\t\tmtk_switch_w32(gsw, val, GSW_REG_PORT_PMCR(id));\n\t\tdev_info(priv->dev, \"port %d - using fixed link parameters\\n\", id);\n\t\treturn;\n\t}\n\n\tpriv->phy->phy_node[id] = of_parse_phandle(np, \"phy-handle\", 0);\n\tif (!priv->phy->phy_node[id]) {\n\t\tdev_err(priv->dev, \"port %d - missing phy handle\\n\", id);\n\t\treturn;\n\t}\n\n\tphy_addr = of_get_property(priv->phy->phy_node[id], \"reg\", NULL);\n\tif (phy_addr && mdiobus_get_phy(priv->mii_bus, be32_to_cpup(phy_addr))) {\n\t\tu32 val = PMCR_BACKPRES | PMCR_BACKOFF | PMCR_RX_EN |\n\t\t\tPMCR_TX_EN |  PMCR_MAC_MODE | PMCR_IPG;\n\n\t\tmtk_switch_w32(gsw, val, GSW_REG_PORT_PMCR(id));\n\t\tfe_connect_phy_node(priv, priv->phy->phy_node[id], id);\n\t\tgsw->autopoll |= BIT(be32_to_cpup(phy_addr));\n\t\tmt7620_auto_poll(gsw,id);\n\t}\n}\n\nstatic void mt7620_fe_reset(struct fe_priv *priv)\n{\n\tfe_reset(MT7620A_RESET_FE | MT7620A_RESET_ESW);\n}\n\nstatic void mt7620_rxcsum_config(bool enable)\n{\n\tif (enable)\n\t\tfe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) | (GDMA_ICS_EN |\n\t\t\t\t\tGDMA_TCS_EN | GDMA_UCS_EN),\n\t\t\t\tMT7620A_GDMA1_FWD_CFG);\n\telse\n\t\tfe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) & ~(GDMA_ICS_EN |\n\t\t\t\t\tGDMA_TCS_EN | GDMA_UCS_EN),\n\t\t\t\tMT7620A_GDMA1_FWD_CFG);\n}\n\nstatic void mt7620_txcsum_config(bool enable)\n{\n\tif (enable)\n\t\tfe_w32(fe_r32(MT7620A_CDMA_CSG_CFG) | (CDMA_ICS_EN |\n\t\t\t\t\tCDMA_UCS_EN | CDMA_TCS_EN),\n\t\t\t\tMT7620A_CDMA_CSG_CFG);\n\telse\n\t\tfe_w32(fe_r32(MT7620A_CDMA_CSG_CFG) & ~(CDMA_ICS_EN |\n\t\t\t\t\tCDMA_UCS_EN | CDMA_TCS_EN),\n\t\t\t\tMT7620A_CDMA_CSG_CFG);\n}\n\nstatic int mt7620_fwd_config(struct fe_priv *priv)\n{\n\tstruct net_device *dev = priv_netdev(priv);\n\n\tfe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) & ~7, MT7620A_GDMA1_FWD_CFG);\n\n\tmt7620_txcsum_config((dev->features & NETIF_F_IP_CSUM));\n\tmt7620_rxcsum_config((dev->features & NETIF_F_RXCSUM));\n\n\treturn 0;\n}\n\nstatic void mt7620_tx_dma(struct fe_tx_dma *txd)\n{\n}\n\nstatic void mt7620_init_data(struct fe_soc_data *data,\n\t\t\t     struct net_device *netdev)\n{\n\tstruct fe_priv *priv = netdev_priv(netdev);\n\n\tpriv->flags = FE_FLAG_PADDING_64B | FE_FLAG_RX_2B_OFFSET |\n\t\tFE_FLAG_RX_SG_DMA | FE_FLAG_HAS_SWITCH;\n\n\tnetdev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM |\n\t\tNETIF_F_HW_VLAN_CTAG_TX;\n\tif (mt7620_get_eco() >= 5)\n\t\tnetdev->hw_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6 |\n\t\t\tNETIF_F_IPV6_CSUM;\n}\n\nstatic struct fe_soc_data mt7620_data = {\n\t.init_data = mt7620_init_data,\n\t.reset_fe = mt7620_fe_reset,\n\t.set_mac = mt7620_set_mac,\n\t.fwd_config = mt7620_fwd_config,\n\t.tx_dma = mt7620_tx_dma,\n\t.switch_init = mtk_gsw_init,\n\t.switch_config = mt7620_gsw_config,\n\t.port_init = mt7620_port_init,\n\t.reg_table = mt7620_reg_table,\n\t.pdma_glo_cfg = FE_PDMA_SIZE_16DWORDS,\n\t.rx_int = RT5350_RX_DONE_INT,\n\t.tx_int = RT5350_TX_DONE_INT,\n\t.status_int = MT7620_FE_GDM1_AF,\n\t.checksum_bit = MT7620_L4_VALID,\n\t.has_carrier = mt7620_has_carrier,\n\t.mdio_read = mt7620_mdio_read,\n\t.mdio_write = mt7620_mdio_write,\n\t.mdio_adjust_link = mt7620_mdio_link_adjust,\n};\n\nconst struct of_device_id of_fe_match[] = {\n\t{ .compatible = \"mediatek,mt7620-eth\", .data = &mt7620_data },\n\t{},\n};\n\nMODULE_DEVICE_TABLE(of, of_fe_match);\n"
  },
  {
    "path": "target/linux/ramips/files/drivers/net/ethernet/ralink/soc_rt2880.c",
    "content": "/*   This program is free software; you can redistribute it and/or modify\n *   it under the terms of the GNU General Public License as published by\n *   the Free Software Foundation; version 2 of the License\n *\n *   This program is distributed in the hope that it will be useful,\n *   but WITHOUT ANY WARRANTY; without even the implied warranty of\n *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n *   GNU General Public License for more details.\n *\n *   Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>\n *   Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>\n *   Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>\n */\n\n#include <linux/module.h>\n\n#include <asm/mach-ralink/ralink_regs.h>\n\n#include \"mtk_eth_soc.h\"\n#include \"mdio_rt2880.h\"\n\nstatic void rt2880_init_data(struct fe_soc_data *data,\n\t\t\t     struct net_device *netdev)\n{\n\tstruct fe_priv *priv = netdev_priv(netdev);\n\n\tpriv->flags = FE_FLAG_PADDING_64B | FE_FLAG_PADDING_BUG |\n\t\tFE_FLAG_JUMBO_FRAME | FE_FLAG_CALIBRATE_CLK;\n\tnetdev->hw_features = NETIF_F_SG | NETIF_F_HW_VLAN_CTAG_TX;\n\t/* this should work according to the datasheet but actually does not*/\n\t/* netdev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_RXCSUM; */\n}\n\nstatic int rt2880_fwd_config(struct fe_priv *priv)\n{\n\tint ret;\n\n\tret = fe_set_clock_cycle(priv);\n\tif (ret)\n\t\treturn ret;\n\n\tfe_fwd_config(priv);\n\tfe_w32(FE_PSE_FQFC_CFG_INIT, FE_PSE_FQ_CFG);\n\tfe_csum_config(priv);\n\n\treturn ret;\n}\n\nstruct fe_soc_data rt2880_data = {\n\t.init_data = rt2880_init_data,\n\t.fwd_config = rt2880_fwd_config,\n\t.pdma_glo_cfg = FE_PDMA_SIZE_8DWORDS,\n\t.checksum_bit = RX_DMA_L4VALID,\n\t.rx_int = FE_RX_DONE_INT,\n\t.tx_int = FE_TX_DONE_INT,\n\t.status_int = FE_CNT_GDM_AF,\n\t.mdio_read = rt2880_mdio_read,\n\t.mdio_write = rt2880_mdio_write,\n\t.mdio_adjust_link = rt2880_mdio_link_adjust,\n\t.port_init = rt2880_port_init,\n};\n\nconst struct of_device_id of_fe_match[] = {\n\t{ .compatible = \"ralink,rt2880-eth\", .data = &rt2880_data },\n\t{},\n};\n\nMODULE_DEVICE_TABLE(of, of_fe_match);\n"
  },
  {
    "path": "target/linux/ramips/files/drivers/net/ethernet/ralink/soc_rt3050.c",
    "content": "/*   This program is free software; you can redistribute it and/or modify\n *   it under the terms of the GNU General Public License as published by\n *   the Free Software Foundation; version 2 of the License\n *\n *   This program is distributed in the hope that it will be useful,\n *   but WITHOUT ANY WARRANTY; without even the implied warranty of\n *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n *   GNU General Public License for more details.\n *\n *   Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>\n *   Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>\n *   Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>\n */\n\n#include <linux/module.h>\n\n#include <asm/mach-ralink/ralink_regs.h>\n\n#include \"mtk_eth_soc.h\"\n#include \"esw_rt3050.h\"\n#include \"mdio_rt2880.h\"\n\nstatic const u16 rt5350_reg_table[FE_REG_COUNT] = {\n\t[FE_REG_PDMA_GLO_CFG] = RT5350_PDMA_GLO_CFG,\n\t[FE_REG_PDMA_RST_CFG] = RT5350_PDMA_RST_CFG,\n\t[FE_REG_DLY_INT_CFG] = RT5350_DLY_INT_CFG,\n\t[FE_REG_TX_BASE_PTR0] = RT5350_TX_BASE_PTR0,\n\t[FE_REG_TX_MAX_CNT0] = RT5350_TX_MAX_CNT0,\n\t[FE_REG_TX_CTX_IDX0] = RT5350_TX_CTX_IDX0,\n\t[FE_REG_TX_DTX_IDX0] = RT5350_TX_DTX_IDX0,\n\t[FE_REG_RX_BASE_PTR0] = RT5350_RX_BASE_PTR0,\n\t[FE_REG_RX_MAX_CNT0] = RT5350_RX_MAX_CNT0,\n\t[FE_REG_RX_CALC_IDX0] = RT5350_RX_CALC_IDX0,\n\t[FE_REG_RX_DRX_IDX0] = RT5350_RX_DRX_IDX0,\n\t[FE_REG_FE_INT_ENABLE] = RT5350_FE_INT_ENABLE,\n\t[FE_REG_FE_INT_STATUS] = RT5350_FE_INT_STATUS,\n\t[FE_REG_FE_RST_GL] = 0,\n\t[FE_REG_FE_DMA_VID_BASE] = 0,\n};\n\nstatic void rt305x_init_data(struct fe_soc_data *data,\n\t\t\t     struct net_device *netdev)\n{\n\tstruct fe_priv *priv = netdev_priv(netdev);\n\n\tpriv->flags = FE_FLAG_PADDING_64B | FE_FLAG_PADDING_BUG |\n\t\tFE_FLAG_CALIBRATE_CLK | FE_FLAG_HAS_SWITCH;\n\tnetdev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM |\n\t\tNETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX;\n}\n\nstatic int rt3050_fwd_config(struct fe_priv *priv)\n{\n\tint ret;\n\n\tif (ralink_soc != RT305X_SOC_RT3052) {\n\t\tret = fe_set_clock_cycle(priv);\n\t\tif (ret)\n\t\t\treturn ret;\n\t}\n\n\tfe_fwd_config(priv);\n\tif (ralink_soc != RT305X_SOC_RT3352)\n\t\tfe_w32(FE_PSE_FQFC_CFG_INIT, FE_PSE_FQ_CFG);\n\tfe_csum_config(priv);\n\n\treturn 0;\n}\n\nstatic void rt5350_init_data(struct fe_soc_data *data,\n\t\t\t     struct net_device *netdev)\n{\n\tstruct fe_priv *priv = netdev_priv(netdev);\n\n\tpriv->flags = FE_FLAG_HAS_SWITCH;\n\tnetdev->hw_features = NETIF_F_SG | NETIF_F_RXCSUM;\n}\n\nstatic void rt5350_set_mac(struct fe_priv *priv, unsigned char *mac)\n{\n\tunsigned long flags;\n\n\tspin_lock_irqsave(&priv->page_lock, flags);\n\tfe_w32((mac[0] << 8) | mac[1], RT5350_SDM_MAC_ADRH);\n\tfe_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],\n\t       RT5350_SDM_MAC_ADRL);\n\tspin_unlock_irqrestore(&priv->page_lock, flags);\n}\n\nstatic void rt5350_rxcsum_config(bool enable)\n{\n\tif (enable)\n\t\tfe_w32(fe_r32(RT5350_SDM_CFG) | (RT5350_SDM_ICS_EN |\n\t\t\t\tRT5350_SDM_TCS_EN | RT5350_SDM_UCS_EN),\n\t\t\t\tRT5350_SDM_CFG);\n\telse\n\t\tfe_w32(fe_r32(RT5350_SDM_CFG) & ~(RT5350_SDM_ICS_EN |\n\t\t\t\tRT5350_SDM_TCS_EN | RT5350_SDM_UCS_EN),\n\t\t\t\tRT5350_SDM_CFG);\n}\n\nstatic int rt5350_fwd_config(struct fe_priv *priv)\n{\n\tstruct net_device *dev = priv_netdev(priv);\n\n\trt5350_rxcsum_config((dev->features & NETIF_F_RXCSUM));\n\n\treturn 0;\n}\n\nstatic void rt5350_tx_dma(struct fe_tx_dma *txd)\n{\n\ttxd->txd4 = 0;\n}\n\nstatic struct fe_soc_data rt3050_data = {\n\t.init_data = rt305x_init_data,\n\t.fwd_config = rt3050_fwd_config,\n\t.switch_init = rt3050_esw_init,\n\t.pdma_glo_cfg = FE_PDMA_SIZE_8DWORDS,\n\t.checksum_bit = RX_DMA_L4VALID,\n\t.rx_int = FE_RX_DONE_INT,\n\t.tx_int = FE_TX_DONE_INT,\n\t.status_int = FE_CNT_GDM_AF,\n};\n\nstatic struct fe_soc_data rt5350_data = {\n\t.init_data = rt5350_init_data,\n\t.reg_table = rt5350_reg_table,\n\t.set_mac = rt5350_set_mac,\n\t.fwd_config = rt5350_fwd_config,\n\t.switch_init = rt3050_esw_init,\n\t.tx_dma = rt5350_tx_dma,\n\t.pdma_glo_cfg = FE_PDMA_SIZE_8DWORDS,\n\t.checksum_bit = RX_DMA_L4VALID,\n\t.rx_int = RT5350_RX_DONE_INT,\n\t.tx_int = RT5350_TX_DONE_INT,\n};\n\nconst struct of_device_id of_fe_match[] = {\n\t{ .compatible = \"ralink,rt3050-eth\", .data = &rt3050_data },\n\t{ .compatible = \"ralink,rt5350-eth\", .data = &rt5350_data },\n\t{},\n};\n\nMODULE_DEVICE_TABLE(of, of_fe_match);\n"
  },
  {
    "path": "target/linux/ramips/files/drivers/net/ethernet/ralink/soc_rt3883.c",
    "content": "/*   This program is free software; you can redistribute it and/or modify\n *   it under the terms of the GNU General Public License as published by\n *   the Free Software Foundation; version 2 of the License\n *\n *   This program is distributed in the hope that it will be useful,\n *   but WITHOUT ANY WARRANTY; without even the implied warranty of\n *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n *   GNU General Public License for more details.\n *\n *   Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>\n *   Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>\n *   Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>\n */\n\n#include <linux/module.h>\n\n#include <asm/mach-ralink/ralink_regs.h>\n\n#include \"mtk_eth_soc.h\"\n#include \"mdio_rt2880.h\"\n\nstatic int rt3883_fwd_config(struct fe_priv *priv)\n{\n\tint ret;\n\n\tret = fe_set_clock_cycle(priv);\n\tif (ret)\n\t\treturn ret;\n\n\tfe_fwd_config(priv);\n\tfe_w32(FE_PSE_FQFC_CFG_256Q, FE_PSE_FQ_CFG);\n\tfe_csum_config(priv);\n\n\treturn ret;\n}\n\nstatic void rt3883_init_data(struct fe_soc_data *data,\n\t\t\t     struct net_device *netdev)\n{\n\tstruct fe_priv *priv = netdev_priv(netdev);\n\n\tpriv->flags = FE_FLAG_PADDING_64B | FE_FLAG_PADDING_BUG |\n\t\tFE_FLAG_JUMBO_FRAME | FE_FLAG_CALIBRATE_CLK;\n\tnetdev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM |\n\t\tNETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX;\n}\n\nstatic struct fe_soc_data rt3883_data = {\n\t.init_data = rt3883_init_data,\n\t.fwd_config = rt3883_fwd_config,\n\t.pdma_glo_cfg = FE_PDMA_SIZE_8DWORDS,\n\t.rx_int = FE_RX_DONE_INT,\n\t.tx_int = FE_TX_DONE_INT,\n\t.status_int = FE_CNT_GDM_AF,\n\t.checksum_bit = RX_DMA_L4VALID,\n\t.mdio_read = rt2880_mdio_read,\n\t.mdio_write = rt2880_mdio_write,\n\t.mdio_adjust_link = rt2880_mdio_link_adjust,\n\t.port_init = rt2880_port_init,\n};\n\nconst struct of_device_id of_fe_match[] = {\n\t{ .compatible = \"ralink,rt3883-eth\", .data = &rt3883_data },\n\t{},\n};\n\nMODULE_DEVICE_TABLE(of, of_fe_match);\n"
  },
  {
    "path": "target/linux/ramips/files/drivers/pinctrl/pinctrl-aw9523.c",
    "content": "// SPDX-License-Identifier: GPL-2.0-only\n/*\n * Awinic AW9523B i2c pin controller driver\n * Copyright (c) 2020, AngeloGioacchino Del Regno\n *                     <angelogioacchino.delregno@somainline.org>\n */\n\n#include <linux/bitfield.h>\n#include <linux/regmap.h>\n#include <linux/i2c.h>\n#include <linux/init.h>\n#include <linux/interrupt.h>\n#include <linux/irq.h>\n#include <linux/mutex.h>\n#include <linux/module.h>\n#include <linux/slab.h>\n#include <linux/of.h>\n#include <linux/of_device.h>\n#include <linux/version.h>\n#include <linux/gpio/consumer.h>\n#include <linux/gpio/driver.h>\n#include <linux/pinctrl/pinconf.h>\n#include <linux/pinctrl/pinctrl.h>\n#include <linux/pinctrl/pinmux.h>\n#include <linux/pinctrl/pinconf-generic.h>\n#include <linux/regulator/consumer.h>\n\n#include \"core.h\"\n#include \"pinconf.h\"\n#include \"pinctrl-utils.h\"\n\n#define AW9523_MAX_FUNCS\t\t2\n#define AW9523_NUM_PORTS\t\t2\n#define AW9523_PINS_PER_PORT\t\t8\n\n/*\n * HW needs at least 20uS for reset and at least 1-2uS to recover from\n * reset, but we have to account for eventual board quirks, if any:\n * for this reason, keep reset asserted for 50uS and wait for 20uS\n * to recover from the reset.\n */\n#define AW9523_HW_RESET_US\t\t50\n#define AW9523_HW_RESET_RECOVERY_US\t20\n\n/* Port 0: P0_0...P0_7 - Port 1: P1_0...P1_7 */\n#define AW9523_PIN_TO_PORT(pin)\t\t(pin >> 3)\n#define AW9523_REG_IN_STATE(pin)\t(0x00 + AW9523_PIN_TO_PORT(pin))\n#define AW9523_REG_OUT_STATE(pin)\t(0x02 + AW9523_PIN_TO_PORT(pin))\n#define AW9523_REG_CONF_STATE(pin)\t(0x04 + AW9523_PIN_TO_PORT(pin))\n#define AW9523_REG_INTR_DIS(pin)\t(0x06 + AW9523_PIN_TO_PORT(pin))\n#define AW9523_REG_CHIPID\t\t0x10\n#define AW9523_VAL_EXPECTED_CHIPID\t0x23\n\n#define AW9523_REG_GCR\t\t\t0x11\n#define AW9523_GCR_ISEL_MASK\t\tGENMASK(0, 1)\n#define AW9523_GCR_GPOMD_MASK\t\tBIT(4)\n\n#define AW9523_REG_PORT_MODE(pin)\t(0x12 + AW9523_PIN_TO_PORT(pin))\n#define AW9523_REG_SOFT_RESET\t\t0x7f\n#define AW9523_VAL_RESET\t\t0x00\n\n/*\n * struct aw9523_irq - Interrupt controller structure\n * @lock: mutex locking for the irq bus\n * @irqchip: structure holding irqchip params\n * @cached_gpio: stores the previous gpio status for bit comparison\n */\nstruct aw9523_irq {\n\tstruct mutex lock;\n\tstruct irq_chip *irqchip;\n\tu16 cached_gpio;\n};\n\n/*\n * struct aw9523_pinmux - Pin mux params\n * @name: Name of the mux\n * @grps: Groups of the mux\n * @num_grps: Number of groups (sizeof array grps)\n */\nstruct aw9523_pinmux {\n\tconst char *name;\n\tconst char * const *grps;\n\tconst u8 num_grps;\n};\n\n/*\n * struct aw9523 - Main driver structure\n * @dev: device handle\n * @regmap: regmap handle for current device\n * @i2c_lock: Mutex lock for i2c operations\n * @reset_gpio: Hardware reset (RSTN) signal GPIO\n * @vio_vreg: VCC regulator (Optional)\n * @pctl: pinctrl handle for current device\n * @gpio: structure holding gpiochip params\n * @irq: Interrupt controller structure\n */\nstruct aw9523 {\n\tstruct device *dev;\n\tstruct regmap *regmap;\n\tstruct mutex i2c_lock;\n\tstruct gpio_desc *reset_gpio;\n\tstruct regulator *vio_vreg;\n\tstruct pinctrl_dev *pctl;\n\tstruct gpio_chip gpio;\n\tstruct aw9523_irq *irq;\n};\n\nstatic const struct pinctrl_pin_desc aw9523_pins[] = {\n\t/* Port 0 */\n\tPINCTRL_PIN(0, \"gpio0\"),\n\tPINCTRL_PIN(1, \"gpio1\"),\n\tPINCTRL_PIN(2, \"gpio2\"),\n\tPINCTRL_PIN(3, \"gpio3\"),\n\tPINCTRL_PIN(4, \"gpio4\"),\n\tPINCTRL_PIN(5, \"gpio5\"),\n\tPINCTRL_PIN(6, \"gpio6\"),\n\tPINCTRL_PIN(7, \"gpio7\"),\n\n\t/* Port 1 */\n\tPINCTRL_PIN(8, \"gpio8\"),\n\tPINCTRL_PIN(9, \"gpio9\"),\n\tPINCTRL_PIN(10, \"gpio10\"),\n\tPINCTRL_PIN(11, \"gpio11\"),\n\tPINCTRL_PIN(12, \"gpio12\"),\n\tPINCTRL_PIN(13, \"gpio13\"),\n\tPINCTRL_PIN(14, \"gpio14\"),\n\tPINCTRL_PIN(15, \"gpio15\"),\n};\n\nstatic int aw9523_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)\n{\n\treturn ARRAY_SIZE(aw9523_pins);\n}\n\nstatic const char *aw9523_pinctrl_get_group_name(struct pinctrl_dev *pctldev,\n\t\t\t\t\t\t unsigned int selector)\n{\n\treturn aw9523_pins[selector].name;\n}\n\nstatic int aw9523_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,\n\t\t\t\t\t unsigned int selector,\n\t\t\t\t\t const unsigned int **pins,\n\t\t\t\t\t unsigned int *num_pins)\n{\n\t*pins = &aw9523_pins[selector].number;\n\t*num_pins = 1;\n\treturn 0;\n}\n\nstatic const struct pinctrl_ops aw9523_pinctrl_ops = {\n\t.get_groups_count = aw9523_pinctrl_get_groups_count,\n\t.get_group_pins = aw9523_pinctrl_get_group_pins,\n\t.get_group_name = aw9523_pinctrl_get_group_name,\n\t.dt_node_to_map = pinconf_generic_dt_node_to_map_pin,\n\t.dt_free_map = pinconf_generic_dt_free_map,\n};\n\nstatic const char * const gpio_pwm_groups[] = {\n\t\"gpio0\", \"gpio1\", \"gpio2\", \"gpio3\", \"gpio4\", \"gpio5\",\n\t\"gpio6\", \"gpio7\", \"gpio8\", \"gpio9\", \"gpio10\", \"gpio11\",\n\t\"gpio12\", \"gpio13\", \"gpio14\", \"gpio15\"\n};\n\n/* Warning: Do NOT reorder this array */\nstatic const struct aw9523_pinmux aw9523_pmx[] = {\n\t{\n\t\t.name = \"pwm\",\n\t\t.grps = gpio_pwm_groups,\n\t\t.num_grps = ARRAY_SIZE(gpio_pwm_groups),\n\t},\n\t{\n\t\t.name = \"gpio\",\n\t\t.grps = gpio_pwm_groups,\n\t\t.num_grps = ARRAY_SIZE(gpio_pwm_groups),\n\t},\n};\n\nstatic int aw9523_pmx_get_funcs_count(struct pinctrl_dev *pctl)\n{\n\treturn ARRAY_SIZE(aw9523_pmx);\n}\n\nstatic const char *aw9523_pmx_get_fname(struct pinctrl_dev *pctl,\n\t\t\t\t\tunsigned int sel)\n{\n\treturn aw9523_pmx[sel].name;\n}\n\nstatic int aw9523_pmx_get_groups(struct pinctrl_dev *pctl, unsigned int sel,\n\t\t\t\t const char * const **groups,\n\t\t\t\t unsigned int * const num_groups)\n{\n\t*groups = aw9523_pmx[sel].grps;\n\t*num_groups = aw9523_pmx[sel].num_grps;\n\treturn 0;\n}\n\nstatic int aw9523_pmx_set_mux(struct pinctrl_dev *pctl, unsigned int fsel,\n\t\t\t      unsigned int grp)\n{\n\tstruct aw9523 *awi = pinctrl_dev_get_drvdata(pctl);\n\tint ret, pin = aw9523_pins[grp].number % AW9523_PINS_PER_PORT;\n\n\tif (fsel >= ARRAY_SIZE(aw9523_pmx))\n\t\treturn -EINVAL;\n\n\t/*\n\t * This maps directly to the aw9523_pmx array: programming a\n\t * high bit means \"gpio\" and a low bit means \"pwm\".\n\t */\n\tmutex_lock(&awi->i2c_lock);\n\tret = regmap_update_bits(awi->regmap, AW9523_REG_PORT_MODE(pin),\n\t\t\t\t BIT(pin), (fsel ? BIT(pin) : 0));\n\tmutex_unlock(&awi->i2c_lock);\n\treturn ret;\n}\n\nstatic const struct pinmux_ops aw9523_pinmux_ops = {\n\t.get_functions_count\t= aw9523_pmx_get_funcs_count,\n\t.get_function_name\t= aw9523_pmx_get_fname,\n\t.get_function_groups\t= aw9523_pmx_get_groups,\n\t.set_mux\t\t= aw9523_pmx_set_mux,\n};\n\nstatic int aw9523_pcfg_param_to_reg(enum pin_config_param pcp, int pin, u8 *r)\n{\n\tu8 reg;\n\n\tswitch (pcp) {\n\tcase PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:\n\tcase PIN_CONFIG_BIAS_PULL_DOWN:\n\tcase PIN_CONFIG_BIAS_PULL_UP:\n\t\treg = AW9523_REG_IN_STATE(pin);\n\t\tbreak;\n\tcase PIN_CONFIG_DRIVE_OPEN_DRAIN:\n\tcase PIN_CONFIG_DRIVE_PUSH_PULL:\n\t\treg = AW9523_REG_GCR;\n\t\tbreak;\n\tcase PIN_CONFIG_INPUT_ENABLE:\n\tcase PIN_CONFIG_OUTPUT_ENABLE:\n\t\treg = AW9523_REG_CONF_STATE(pin);\n\t\tbreak;\n\tcase PIN_CONFIG_OUTPUT:\n\t\treg = AW9523_REG_OUT_STATE(pin);\n\t\tbreak;\n\tdefault:\n\t\treturn -ENOTSUPP;\n\t}\n\t*r = reg;\n\n\treturn 0;\n}\n\nstatic int aw9523_pconf_get(struct pinctrl_dev *pctldev, unsigned int pin,\n\t\t\t    unsigned long *config)\n{\n\tstruct aw9523 *awi = pinctrl_dev_get_drvdata(pctldev);\n\tenum pin_config_param param = pinconf_to_config_param(*config);\n\tint regbit = pin % AW9523_PINS_PER_PORT;\n\tunsigned int val;\n\tu8 reg;\n\tint rc;\n\n\trc = aw9523_pcfg_param_to_reg(param, pin, &reg);\n\tif (rc)\n\t\treturn rc;\n\n\tmutex_lock(&awi->i2c_lock);\n\trc = regmap_read(awi->regmap, reg, &val);\n\tmutex_unlock(&awi->i2c_lock);\n\tif (rc)\n\t\treturn rc;\n\n\tswitch (param) {\n\tcase PIN_CONFIG_BIAS_PULL_UP:\n\tcase PIN_CONFIG_INPUT_ENABLE:\n\tcase PIN_CONFIG_OUTPUT:\n\t\tval &= BIT(regbit);\n\t\tbreak;\n\tcase PIN_CONFIG_BIAS_PULL_DOWN:\n\tcase PIN_CONFIG_OUTPUT_ENABLE:\n\t\tval &= BIT(regbit);\n\t\tval = !val;\n\t\tbreak;\n\tcase PIN_CONFIG_DRIVE_OPEN_DRAIN:\n\t\tif (pin >= AW9523_PINS_PER_PORT)\n\t\t\tval = 0;\n\t\telse\n\t\t\tval = !FIELD_GET(AW9523_GCR_GPOMD_MASK, val);\n\t\tbreak;\n\tcase PIN_CONFIG_DRIVE_PUSH_PULL:\n\t\tif (pin >= AW9523_PINS_PER_PORT)\n\t\t\tval = 1;\n\t\telse\n\t\t\tval = FIELD_GET(AW9523_GCR_GPOMD_MASK, val);\n\t\tbreak;\n\tdefault:\n\t\treturn -ENOTSUPP;\n\t}\n\tif (val < 1)\n\t\treturn -EINVAL;\n\n\t*config = pinconf_to_config_packed(param, !!val);\n\n\treturn rc;\n}\n\nstatic int aw9523_pconf_set(struct pinctrl_dev *pctldev, unsigned int pin,\n\t\t\t    unsigned long *configs, unsigned int num_configs)\n{\n\tstruct aw9523 *awi = pinctrl_dev_get_drvdata(pctldev);\n\tenum pin_config_param param;\n\tint regbit = pin % AW9523_PINS_PER_PORT;\n\tu32 arg;\n\tu8 reg;\n\tunsigned int mask, val;\n\tint i, rc;\n\n\tmutex_lock(&awi->i2c_lock);\n\tfor (i = 0; i < num_configs; i++) {\n\t\tparam = pinconf_to_config_param(configs[i]);\n\t\targ = pinconf_to_config_argument(configs[i]);\n\n\t\trc = aw9523_pcfg_param_to_reg(param, pin, &reg);\n\t\tif (rc)\n\t\t\tgoto end;\n\n\t\tswitch (param) {\n\t\tcase PIN_CONFIG_OUTPUT:\n\t\t\t/* First, enable pin output */\n\t\t\trc = regmap_update_bits(awi->regmap,\n\t\t\t\t\t\tAW9523_REG_CONF_STATE(pin),\n\t\t\t\t\t\tBIT(regbit), 0);\n\t\t\tif (rc)\n\t\t\t\tgoto end;\n\n\t\t\t/* Then, fall through to config output level */\n\t\t\tfallthrough;\n\t\tcase PIN_CONFIG_OUTPUT_ENABLE:\n\t\t\targ = !arg;\n\t\t\tfallthrough;\n\t\tcase PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:\n\t\tcase PIN_CONFIG_BIAS_PULL_DOWN:\n\t\tcase PIN_CONFIG_BIAS_PULL_UP:\n\t\tcase PIN_CONFIG_INPUT_ENABLE:\n\t\t\tmask = BIT(regbit);\n\t\t\tval = arg ? BIT(regbit) : 0;\n\t\t\tbreak;\n\t\tcase PIN_CONFIG_DRIVE_OPEN_DRAIN:\n\t\t\t/* Open-Drain is supported only on port 0 */\n\t\t\tif (pin >= AW9523_PINS_PER_PORT) {\n\t\t\t\trc = -ENOTSUPP;\n\t\t\t\tgoto end;\n\t\t\t}\n\t\t\tmask = AW9523_GCR_GPOMD_MASK;\n\t\t\tval = 0;\n\t\t\tbreak;\n\t\tcase PIN_CONFIG_DRIVE_PUSH_PULL:\n\t\t\t/* Port 1 is always Push-Pull */\n\t\t\tif (pin >= AW9523_PINS_PER_PORT) {\n\t\t\t\tmask = 0;\n\t\t\t\tval = 0;\n\t\t\t\tcontinue;\n\t\t\t}\n\t\t\tmask = AW9523_GCR_GPOMD_MASK;\n\t\t\tval = AW9523_GCR_GPOMD_MASK;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\trc = -ENOTSUPP;\n\t\t\tgoto end;\n\t\t}\n\n\t\trc = regmap_update_bits(awi->regmap, reg, mask, val);\n\t\tif (rc)\n\t\t\tgoto end;\n\t}\nend:\n\tmutex_unlock(&awi->i2c_lock);\n\treturn rc;\n}\n\nstatic const struct pinconf_ops aw9523_pinconf_ops = {\n\t.pin_config_get = aw9523_pconf_get,\n\t.pin_config_set = aw9523_pconf_set,\n\t.is_generic = true,\n};\n\n#if LINUX_VERSION_CODE <= KERNEL_VERSION(5, 5, 0)\n#define GPIO_LINE_DIRECTION_IN\t1\n#define GPIO_LINE_DIRECTION_OUT\t0\n#endif\n\n/*\n * aw9523_get_pin_direction - Get pin direction\n * @regmap: Regmap structure\n * @pin: gpiolib pin number\n * @n:   pin index in port register\n *\n * Return: Pin direction for success or negative number for error\n */\nstatic int aw9523_get_pin_direction(struct regmap *regmap, u8 pin, u8 n)\n{\n\tint val, ret;\n\n\tret = regmap_read(regmap, AW9523_REG_CONF_STATE(pin), &val);\n\tif (ret < 0)\n\t\treturn ret;\n\n\treturn (val & BIT(n)) == BIT(n);\n}\n\n/*\n * aw9523_get_port_state - Get input or output state for entire port\n * @regmap: Regmap structure\n * @pin:    gpiolib pin number\n * @regbit: hw pin index, used to retrieve port number\n * @state:  returned port state\n *\n * Return: Zero for success or negative number for error\n */\nstatic int aw9523_get_port_state(struct regmap *regmap, u8 pin,\n\t\t\t\t   u8 regbit, unsigned int *state)\n{\n\tu8 reg;\n\tint dir;\n\n\tdir = aw9523_get_pin_direction(regmap, pin, regbit);\n\tif (dir < 0)\n\t\treturn dir;\n\n\tif (dir == GPIO_LINE_DIRECTION_IN)\n\t\treg = AW9523_REG_IN_STATE(pin);\n\telse\n\t\treg = AW9523_REG_OUT_STATE(pin);\n\n\treturn regmap_read(regmap, reg, state);\n}\n\n#if LINUX_VERSION_CODE <= KERNEL_VERSION(5, 5, 0)\n#undef GPIO_LINE_DIRECTION_IN\n#undef GPIO_LINE_DIRECTION_OUT\n#endif\n\nstatic int aw9523_gpio_irq_type(struct irq_data *d, unsigned int type)\n{\n\tswitch (type) {\n\tcase IRQ_TYPE_NONE:\n\tcase IRQ_TYPE_EDGE_BOTH:\n\t\treturn 0;\n\tdefault:\n\t\treturn -EINVAL;\n\t};\n}\n\n/*\n * aw9523_irq_mask - Mask interrupt\n * @d: irq data\n *\n * Sets which interrupt to mask in the bitmap;\n * The interrupt will be masked when unlocking the irq bus.\n */\nstatic void aw9523_irq_mask(struct irq_data *d)\n{\n\tstruct aw9523 *awi = gpiochip_get_data(irq_data_get_irq_chip_data(d));\n\tunsigned int n = d->hwirq % AW9523_PINS_PER_PORT;\n\n\tregmap_update_bits(awi->regmap,\n\t\t\t   AW9523_REG_INTR_DIS(d->hwirq),\n\t\t\t   BIT(n), BIT(n));\n}\n\n/*\n * aw9523_irq_unmask - Unmask interrupt\n * @d: irq data\n *\n * Sets which interrupt to unmask in the bitmap;\n * The interrupt will be masked when unlocking the irq bus.\n */\nstatic void aw9523_irq_unmask(struct irq_data *d)\n{\n\tstruct aw9523 *awi = gpiochip_get_data(irq_data_get_irq_chip_data(d));\n\tunsigned int n = d->hwirq % AW9523_PINS_PER_PORT;\n\n\tregmap_update_bits(awi->regmap,\n\t\t\t   AW9523_REG_INTR_DIS(d->hwirq),\n\t\t\t   BIT(n), 0);\n}\n\nstatic irqreturn_t aw9523_irq_thread_func(int irq, void *dev_id)\n{\n\tstruct aw9523 *awi = (struct aw9523 *)dev_id;\n\tunsigned long n, val = 0;\n\tunsigned long changed_gpio;\n\tunsigned int tmp, port_pin, i, ret;\n\n\tfor (i = 0; i < AW9523_NUM_PORTS; i++) {\n\t\tport_pin = i * AW9523_PINS_PER_PORT;\n\t\tret = regmap_read(awi->regmap,\n\t\t\t\t  AW9523_REG_IN_STATE(port_pin),\n\t\t\t\t  &tmp);\n\t\tif (ret)\n\t\t\treturn ret;\n\t\tval |= (u8)tmp << (i * 8);\n\t}\n\n\t/* Handle GPIO input release interrupt as well */\n\tchanged_gpio = awi->irq->cached_gpio ^ val;\n\tawi->irq->cached_gpio = val;\n\n\t/*\n\t * To avoid up to four *slow* i2c reads from any driver hooked\n\t * up to our interrupts, just check for the irq_find_mapping\n\t * result: if the interrupt is not mapped, then we don't want\n\t * to care about it.\n\t */\n\tfor_each_set_bit(n, &changed_gpio, awi->gpio.ngpio) {\n\t\ttmp = irq_find_mapping(awi->gpio.irq.domain, n);\n\t\tif (tmp <= 0)\n\t\t\tcontinue;\n\t\thandle_nested_irq(tmp);\n\t}\n\n\treturn IRQ_HANDLED;\n}\n\n/*\n * aw9523_irq_bus_lock - Grab lock for interrupt operation\n * @d: irq data\n */\nstatic void aw9523_irq_bus_lock(struct irq_data *d)\n{\n\tstruct aw9523 *awi = gpiochip_get_data(irq_data_get_irq_chip_data(d));\n\n\tmutex_lock(&awi->irq->lock);\n\tregcache_cache_only(awi->regmap, true);\n}\n\n/*\n * aw9523_irq_bus_sync_unlock - Synchronize state and unlock\n * @d: irq data\n *\n * Writes the interrupt mask bits (found in the bit map) to the\n * hardware, then unlocks the bus.\n */\nstatic void aw9523_irq_bus_sync_unlock(struct irq_data *d)\n{\n\tstruct aw9523 *awi = gpiochip_get_data(irq_data_get_irq_chip_data(d));\n\n\tregcache_cache_only(awi->regmap, false);\n\tregcache_sync(awi->regmap);\n\tmutex_unlock(&awi->irq->lock);\n}\n\nstatic int aw9523_gpio_get_direction(struct gpio_chip *chip,\n\t\t\t\t     unsigned int offset)\n{\n\tstruct aw9523 *awi = gpiochip_get_data(chip);\n\tu8 regbit = offset % AW9523_PINS_PER_PORT;\n\tint ret;\n\n\tmutex_lock(&awi->i2c_lock);\n\tret = aw9523_get_pin_direction(awi->regmap, offset, regbit);\n\tmutex_unlock(&awi->i2c_lock);\n\n\treturn ret;\n}\n\nstatic int aw9523_gpio_get(struct gpio_chip *chip, unsigned int offset)\n{\n\tstruct aw9523 *awi = gpiochip_get_data(chip);\n\tu8 regbit = offset % AW9523_PINS_PER_PORT;\n\tunsigned int val;\n\tint ret;\n\n\tmutex_lock(&awi->i2c_lock);\n\tret = aw9523_get_port_state(awi->regmap, offset, regbit, &val);\n\tmutex_unlock(&awi->i2c_lock);\n\tif (ret)\n\t\treturn ret;\n\n\treturn !!(val & BIT(regbit));\n}\n\n/**\n * _aw9523_gpio_get_multiple - Get I/O state for an entire port\n * @regmap: Regmap structure\n * @pin: gpiolib pin number\n * @regbit: hw pin index, used to retrieve port number\n * @state: returned port I/O state\n *\n * Return: Zero for success or negative number for error\n */\nstatic int _aw9523_gpio_get_multiple(struct aw9523 *awi, u8 regbit,\n\t\t\t\t     u8 *state, u8 mask)\n{\n\tu32 dir_in, val;\n\tu8 m;\n\tint ret;\n\n\t/* Registers are 8-bits wide */\n\tret = regmap_read(awi->regmap, AW9523_REG_CONF_STATE(regbit), &dir_in);\n\tif (ret)\n\t\treturn ret;\n\t*state = 0;\n\n\tm = mask & dir_in;\n\tif (m) {\n\t\tret = regmap_read(awi->regmap, AW9523_REG_IN_STATE(regbit),\n\t\t\t\t  &val);\n\t\tif (ret)\n\t\t\treturn ret;\n\t\t*state |= (u8)val & m;\n\t}\n\n\tm = mask & ~dir_in;\n\tif (m) {\n\t\tret = regmap_read(awi->regmap, AW9523_REG_OUT_STATE(regbit),\n\t\t\t\t  &val);\n\t\tif (ret)\n\t\t\treturn ret;\n\t\t*state |= (u8)val & m;\n\t}\n\n\treturn 0;\n}\n\nstatic int aw9523_gpio_get_multiple(struct gpio_chip *chip,\n\t\t\t\t    unsigned long *mask,\n\t\t\t\t    unsigned long *bits)\n{\n\tstruct aw9523 *awi = gpiochip_get_data(chip);\n\tu8 m, state = 0;\n\tint ret;\n\n\tmutex_lock(&awi->i2c_lock);\n\n\t/* Port 0 (gpio 0-7) */\n\tm = *mask & U8_MAX;\n\tif (m) {\n\t\tret = _aw9523_gpio_get_multiple(awi, 0, &state, m);\n\t\tif (ret)\n\t\t\tgoto out;\n\t}\n\t*bits = state;\n\n\t/* Port 1 (gpio 8-15) */\n\tm = (*mask >> 8) & U8_MAX;\n\tif (m) {\n\t\tret = _aw9523_gpio_get_multiple(awi, AW9523_PINS_PER_PORT,\n\t\t\t\t\t\t&state, m);\n\t\tif (ret)\n\t\t\tgoto out;\n\n\t\t*bits |= (state << 8);\n\t}\nout:\n\tmutex_unlock(&awi->i2c_lock);\n\treturn ret;\n}\n\nstatic void aw9523_gpio_set_multiple(struct gpio_chip *chip,\n\t\t\t\t    unsigned long *mask,\n\t\t\t\t    unsigned long *bits)\n{\n\tstruct aw9523 *awi = gpiochip_get_data(chip);\n\tu8 mask_lo, mask_hi, bits_lo, bits_hi;\n\tunsigned int reg;\n\tint ret = 0;\n\n\tmask_lo = *mask & U8_MAX;\n\tmask_hi = (*mask >> 8) & U8_MAX;\n\tmutex_lock(&awi->i2c_lock);\n\tif (mask_hi) {\n\t\treg = AW9523_REG_OUT_STATE(AW9523_PINS_PER_PORT);\n\t\tbits_hi = (*bits >> 8) & U8_MAX;\n\n\t\tret = regmap_write_bits(awi->regmap, reg, mask_hi, bits_hi);\n\t\tif (ret) {\n\t\t\tdev_warn(awi->dev, \"Cannot write port1 out level\\n\");\n\t\t\tgoto out;\n\t\t}\n\t}\n\tif (mask_lo) {\n\t\treg = AW9523_REG_OUT_STATE(0);\n\t\tbits_lo = *bits & U8_MAX;\n\t\tret = regmap_write_bits(awi->regmap, reg, mask_lo, bits_lo);\n\t\tif (ret)\n\t\t\tdev_warn(awi->dev, \"Cannot write port0 out level\\n\");\n\t}\nout:\n\tmutex_unlock(&awi->i2c_lock);\n}\n\nstatic void aw9523_gpio_set(struct gpio_chip *chip,\n\t\t\t    unsigned int offset, int value)\n{\n\tstruct aw9523 *awi = gpiochip_get_data(chip);\n\tu8 regbit = offset % AW9523_PINS_PER_PORT;\n\n\tmutex_lock(&awi->i2c_lock);\n\tregmap_update_bits(awi->regmap, AW9523_REG_OUT_STATE(offset),\n\t\t\t   BIT(regbit), value ? BIT(regbit) : 0);\n\tmutex_unlock(&awi->i2c_lock);\n}\n\n\nstatic int aw9523_direction_input(struct gpio_chip *chip, unsigned int offset)\n{\n\tstruct aw9523 *awi = gpiochip_get_data(chip);\n\tu8 regbit = offset % AW9523_PINS_PER_PORT;\n\tint ret;\n\n\tmutex_lock(&awi->i2c_lock);\n\tret = regmap_update_bits(awi->regmap, AW9523_REG_CONF_STATE(offset),\n\t\t\t\t BIT(regbit), BIT(regbit));\n\tmutex_unlock(&awi->i2c_lock);\n\n\treturn ret;\n}\n\nstatic int aw9523_direction_output(struct gpio_chip *chip,\n\t\t\t\t   unsigned int offset, int value)\n{\n\tstruct aw9523 *awi = gpiochip_get_data(chip);\n\tu8 regbit = offset % AW9523_PINS_PER_PORT;\n\tint ret;\n\n\tmutex_lock(&awi->i2c_lock);\n\tret = regmap_update_bits(awi->regmap, AW9523_REG_OUT_STATE(offset),\n\t\t\t\t BIT(regbit), value ? BIT(regbit) : 0);\n\tif (ret)\n\t\tgoto end;\n\n\tret = regmap_update_bits(awi->regmap, AW9523_REG_CONF_STATE(offset),\n\t\t\t\t BIT(regbit), 0);\nend:\n\tmutex_unlock(&awi->i2c_lock);\n\treturn ret;\n}\n\nstatic int aw9523_drive_reset_gpio(struct aw9523 *awi)\n{\n\tunsigned int chip_id;\n\tint ret;\n\n\t/*\n\t * If the chip is already configured for any reason, then we\n\t * will probably succeed in sending the soft reset signal to\n\t * the hardware through I2C: this operation takes less time\n\t * compared to a full HW reset and it gives the same results.\n\t */\n\tret = regmap_write(awi->regmap, AW9523_REG_SOFT_RESET, 0);\n\tif (ret == 0)\n\t\tgoto done;\n\n\tdev_dbg(awi->dev, \"Cannot execute soft reset: trying hard reset\\n\");\n\tret = gpiod_direction_output(awi->reset_gpio, 0);\n\tif (ret)\n\t\treturn ret;\n\n\t/* The reset pulse has to be longer than 20uS due to deglitch */\n\tusleep_range(AW9523_HW_RESET_US, AW9523_HW_RESET_US + 1);\n\n\tret = gpiod_direction_output(awi->reset_gpio, 1);\n\tif (ret)\n\t\treturn ret;\ndone:\n\t/* The HW needs at least 1uS to reliably recover after reset */\n\tusleep_range(AW9523_HW_RESET_RECOVERY_US,\n\t\t     AW9523_HW_RESET_RECOVERY_US + 1);\n\n\t/* Check the ChipID */\n\tret = regmap_read(awi->regmap, AW9523_REG_CHIPID, &chip_id);\n\tif (ret) {\n\t\tdev_err(awi->dev, \"Cannot read Chip ID: %d\\n\", ret);\n\t\treturn ret;\n\t}\n\tif (chip_id != AW9523_VAL_EXPECTED_CHIPID) {\n\t\tdev_err(awi->dev, \"Bad ChipID; read 0x%x, expected 0x%x\\n\",\n\t\t\tchip_id, AW9523_VAL_EXPECTED_CHIPID);\n\t\treturn -EINVAL;\n\t}\n\n\treturn 0;\n}\n\nstatic int aw9523_hw_reset(struct aw9523 *awi)\n{\n\tint ret, max_retries = 2;\n\n\t/* Sometimes the chip needs more than one reset cycle */\n\tdo {\n\t\tret = aw9523_drive_reset_gpio(awi);\n\t\tif (ret == 0)\n\t\t\tbreak;\n\t\tmax_retries--;\n\t} while (max_retries);\n\n\treturn ret;\n}\n\nstatic int aw9523_init_gpiochip(struct aw9523 *awi, unsigned int npins)\n{\n\tstruct device *dev = awi->dev;\n\tstruct gpio_chip *gpiochip = &awi->gpio;\n\n\tgpiochip->label = devm_kstrdup(dev, dev_name(dev), GFP_KERNEL);\n\tif (!gpiochip->label)\n\t\treturn -ENOMEM;\n\n\tgpiochip->base = -1;\n\tgpiochip->ngpio = npins;\n\tgpiochip->get_direction = aw9523_gpio_get_direction;\n\tgpiochip->direction_input = aw9523_direction_input;\n\tgpiochip->direction_output = aw9523_direction_output;\n\tgpiochip->get = aw9523_gpio_get;\n\tgpiochip->get_multiple = aw9523_gpio_get_multiple;\n\tgpiochip->set = aw9523_gpio_set;\n\tgpiochip->set_multiple = aw9523_gpio_set_multiple;\n\tgpiochip->set_config = gpiochip_generic_config;\n\tgpiochip->parent = dev;\n\tgpiochip->of_node = dev->of_node;\n\tgpiochip->owner = THIS_MODULE;\n\tgpiochip->can_sleep = true;\n\n\treturn 0;\n}\n\nstatic int aw9523_init_irq(struct aw9523 *awi, int irq)\n{\n\tstruct device *dev = awi->dev;\n\tstruct gpio_irq_chip *gpioirq;\n\tstruct irq_chip *irqchip;\n\tint ret;\n\n\tif (!device_property_read_bool(dev, \"interrupt-controller\"))\n\t\treturn 0;\n\n\tirqchip = devm_kzalloc(dev, sizeof(*irqchip), GFP_KERNEL);\n\tif (!irqchip)\n\t\treturn -ENOMEM;\n\n\tawi->irq = devm_kzalloc(dev, sizeof(*awi->irq), GFP_KERNEL);\n\tif (!awi->irq)\n\t\treturn -ENOMEM;\n\n\tirqchip->name = devm_kstrdup(dev, dev_name(dev), GFP_KERNEL);\n\tif (!irqchip->name)\n\t\treturn -ENOMEM;\n\n\tirqchip->irq_mask = aw9523_irq_mask;\n\tirqchip->irq_unmask = aw9523_irq_unmask;\n\tirqchip->irq_bus_lock = aw9523_irq_bus_lock;\n\tirqchip->irq_bus_sync_unlock = aw9523_irq_bus_sync_unlock;\n\tirqchip->irq_set_type = aw9523_gpio_irq_type;\n\tawi->irq->irqchip = irqchip;\n\tmutex_init(&awi->irq->lock);\n\n\tret = devm_request_threaded_irq(dev, irq, NULL, aw9523_irq_thread_func,\n\t\t\t\t\tIRQF_ONESHOT, dev_name(dev), awi);\n\tif (ret) {\n\t\tdev_err(dev, \"Failed to request irq %d\\n\", irq);\n\t\treturn ret;\n\t}\n\n\tgpioirq = &awi->gpio.irq;\n\tgpioirq->chip = irqchip;\n\tgpioirq->parent_handler = NULL;\n\tgpioirq->num_parents = 0;\n\tgpioirq->parents = NULL;\n\tgpioirq->default_type = IRQ_TYPE_LEVEL_MASK;\n\tgpioirq->handler = handle_simple_irq;\n\tgpioirq->threaded = true;\n\tgpioirq->first = 0;\n\n\treturn 0;\n}\n\nstatic bool aw9523_is_reg_hole(unsigned int reg)\n{\n\treturn (reg > AW9523_REG_PORT_MODE(AW9523_PINS_PER_PORT) &&\n\t\treg < AW9523_REG_SOFT_RESET) ||\n\t       (reg > AW9523_REG_INTR_DIS(AW9523_PINS_PER_PORT) &&\n\t\treg < AW9523_REG_CHIPID);\n}\n\nstatic bool aw9523_readable_reg(struct device *dev, unsigned int reg)\n{\n\t/* All available registers (minus holes) can be read */\n\treturn !aw9523_is_reg_hole(reg);\n}\n\nstatic bool aw9523_volatile_reg(struct device *dev, unsigned int reg)\n{\n\treturn aw9523_is_reg_hole(reg) ||\n\t       reg == AW9523_REG_IN_STATE(0) ||\n\t       reg == AW9523_REG_IN_STATE(AW9523_PINS_PER_PORT) ||\n\t       reg == AW9523_REG_CHIPID ||\n\t       reg == AW9523_REG_SOFT_RESET;\n}\n\nstatic bool aw9523_writeable_reg(struct device *dev, unsigned int reg)\n{\n\treturn !aw9523_is_reg_hole(reg) && reg != AW9523_REG_CHIPID;\n}\n\nstatic bool aw9523_precious_reg(struct device *dev, unsigned int reg)\n{\n\t/* Reading AW9523_REG_IN_STATE clears interrupt status */\n\treturn aw9523_is_reg_hole(reg) ||\n\t       reg == AW9523_REG_IN_STATE(0) ||\n\t       reg == AW9523_REG_IN_STATE(AW9523_PINS_PER_PORT);\n}\n\nstatic const struct regmap_config aw9523_regmap = {\n\t.reg_bits = 8,\n\t.val_bits = 8,\n\t.reg_stride = 1,\n\n\t.precious_reg = aw9523_precious_reg,\n\t.readable_reg = aw9523_readable_reg,\n\t.volatile_reg = aw9523_volatile_reg,\n\t.writeable_reg = aw9523_writeable_reg,\n\n\t.cache_type = REGCACHE_FLAT,\n\t.disable_locking = true,\n\n\t.num_reg_defaults_raw = AW9523_REG_SOFT_RESET,\n};\n\nstatic int aw9523_hw_init(struct aw9523 *awi)\n{\n\tu8 p1_pin = AW9523_PINS_PER_PORT;\n\tunsigned int val;\n\tint ret;\n\n\t/* No register caching during initialization */\n\tregcache_cache_bypass(awi->regmap, true);\n\n\t/* Bring up the chip */\n\tret = aw9523_hw_reset(awi);\n\tif (ret) {\n\t\tdev_err(awi->dev, \"HW Reset failed: %d\\n\", ret);\n\t\treturn ret;\n\t}\n\n\t/*\n\t * This is the expected chip and it is running: it's time to\n\t * set a safe default configuration in case the user doesn't\n\t * configure (all of the available) pins in this chip.\n\t * P.S.: The writes order doesn't matter.\n\t */\n\n\t/* Set all pins as GPIO */\n\tret = regmap_write(awi->regmap, AW9523_REG_PORT_MODE(0), U8_MAX);\n\tif (ret)\n\t\treturn ret;\n\tret = regmap_write(awi->regmap, AW9523_REG_PORT_MODE(p1_pin), U8_MAX);\n\tif (ret)\n\t\treturn ret;\n\n\t/* Set Open-Drain mode on Port 0 (Port 1 is always P-P) */\n\tret = regmap_write(awi->regmap, AW9523_REG_GCR, 0);\n\tif (ret)\n\t\treturn ret;\n\n\t/* Set all pins as inputs */\n\tret = regmap_write(awi->regmap, AW9523_REG_CONF_STATE(0), U8_MAX);\n\tif (ret)\n\t\treturn ret;\n\tret = regmap_write(awi->regmap, AW9523_REG_CONF_STATE(p1_pin), U8_MAX);\n\tif (ret)\n\t\treturn ret;\n\n\t/* Disable all interrupts to avoid unreasoned wakeups */\n\tret = regmap_write(awi->regmap, AW9523_REG_INTR_DIS(0), U8_MAX);\n\tif (ret)\n\t\treturn ret;\n\tret = regmap_write(awi->regmap, AW9523_REG_INTR_DIS(p1_pin), U8_MAX);\n\tif (ret)\n\t\treturn ret;\n\n\t/* Clear setup-generated interrupts by performing a port state read */\n\tret = aw9523_get_port_state(awi->regmap, 0, 0, &val);\n\tif (ret)\n\t\treturn ret;\n\tret = aw9523_get_port_state(awi->regmap, p1_pin, 0, &val);\n\tif (ret)\n\t\treturn ret;\n\n\t/* Everything went fine: activate and reinitialize register cache */\n\tregcache_cache_bypass(awi->regmap, false);\n\treturn regmap_reinit_cache(awi->regmap, &aw9523_regmap);\n}\n\nstatic int aw9523_probe(struct i2c_client *client,\n\t\t\tconst struct i2c_device_id *id)\n{\n\tstruct device *dev = &client->dev;\n\tstruct pinctrl_desc *pdesc;\n\tstruct aw9523 *awi;\n\tint ret;\n\n\tawi = devm_kzalloc(dev, sizeof(*awi), GFP_KERNEL);\n\tif (!awi)\n\t\treturn -ENOMEM;\n\n\ti2c_set_clientdata(client, awi);\n\n\tawi->dev = dev;\n\tawi->reset_gpio = devm_gpiod_get(dev, \"reset\", GPIOD_OUT_HIGH);\n\tif (IS_ERR(awi->reset_gpio))\n\t\treturn PTR_ERR(awi->reset_gpio);\n\tgpiod_set_consumer_name(awi->reset_gpio, \"aw9523 reset\");\n\n\tawi->regmap = devm_regmap_init_i2c(client, &aw9523_regmap);\n\tif (IS_ERR(awi->regmap))\n\t\treturn PTR_ERR(awi->regmap);\n\n\tawi->vio_vreg = devm_regulator_get_optional(dev, \"vio\");\n\tif (IS_ERR(awi->vio_vreg)) {\n\t\tif (PTR_ERR(awi->vio_vreg) == -EPROBE_DEFER)\n\t\t\treturn -EPROBE_DEFER;\n\t\tawi->vio_vreg = NULL;\n\t} else {\n\t\tret = regulator_enable(awi->vio_vreg);\n\t\tif (ret)\n\t\t\treturn ret;\n\t}\n\n\tmutex_init(&awi->i2c_lock);\n\tlockdep_set_subclass(&awi->i2c_lock,\n\t\t\t     i2c_adapter_depth(client->adapter));\n\n\tpdesc = devm_kzalloc(dev, sizeof(*pdesc), GFP_KERNEL);\n\tif (!pdesc)\n\t\treturn -ENOMEM;\n\n\tret = aw9523_hw_init(awi);\n\tif (ret)\n\t\tgoto err_disable_vregs;\n\n\tpdesc->name = dev_name(dev);\n\tpdesc->owner = THIS_MODULE;\n\tpdesc->pctlops = &aw9523_pinctrl_ops;\n\tpdesc->pmxops  = &aw9523_pinmux_ops;\n\tpdesc->confops = &aw9523_pinconf_ops;\n\tpdesc->pins = aw9523_pins;\n\tpdesc->npins = ARRAY_SIZE(aw9523_pins);\n\n\tret = aw9523_init_gpiochip(awi, pdesc->npins);\n\tif (ret)\n\t\tgoto err_disable_vregs;\n\n\tif (client->irq) {\n\t\tret = aw9523_init_irq(awi, client->irq);\n\t\tif (ret)\n\t\t\tgoto err_disable_vregs;\n\t}\n\n\tawi->pctl = devm_pinctrl_register(dev, pdesc, awi);\n\tif (IS_ERR(awi->pctl)) {\n\t\tret = PTR_ERR(awi->pctl);\n\t\tdev_err(dev, \"Cannot register pinctrl: %d\", ret);\n\t\tgoto err_disable_vregs;\n\t}\n\n\tret = devm_gpiochip_add_data(dev, &awi->gpio, awi);\n\tif (ret)\n\t\tgoto err_disable_vregs;\n\n\treturn ret;\n\nerr_disable_vregs:\n\tif (awi->vio_vreg)\n\t\tregulator_disable(awi->vio_vreg);\n\tmutex_destroy(&awi->i2c_lock);\n\treturn ret;\n}\n\nstatic int aw9523_remove(struct i2c_client *client)\n{\n\tstruct aw9523 *awi = i2c_get_clientdata(client);\n\tint ret;\n\n\tif (!awi)\n\t\treturn 0;\n\n\t/*\n\t * If the chip VIO is connected to a regulator that we can turn\n\t * off, life is easy... otherwise, reinitialize the chip and\n\t * set the pins to hardware defaults before removing the driver\n\t * to leave it in a clean, safe and predictable state.\n\t */\n\tif (awi->vio_vreg) {\n\t\tregulator_disable(awi->vio_vreg);\n\t} else {\n\t\tmutex_lock(&awi->i2c_lock);\n\t\tret = aw9523_hw_init(awi);\n\t\tmutex_unlock(&awi->i2c_lock);\n\t\tif (ret)\n\t\t\treturn ret;\n\t}\n\n\tmutex_destroy(&awi->i2c_lock);\n\treturn 0;\n}\n\nstatic const struct i2c_device_id aw9523_i2c_id_table[] = {\n\t{ \"aw9523_i2c\", 0 },\n\t{ }\n};\nMODULE_DEVICE_TABLE(i2c, aw9523_i2c_id_table);\n\nstatic const struct of_device_id of_aw9523_i2c_match[] = {\n\t{ .compatible = \"awinic,aw9523-pinctrl\", },\n};\nMODULE_DEVICE_TABLE(of, of_aw9523_i2c_match);\n\nstatic struct i2c_driver aw9523_driver = {\n\t.driver = {\n\t\t.name = \"aw9523-pinctrl\",\n\t\t.of_match_table = of_aw9523_i2c_match,\n\t},\n\t.probe = aw9523_probe,\n\t.remove = aw9523_remove,\n\t.id_table = aw9523_i2c_id_table,\n};\nmodule_i2c_driver(aw9523_driver);\n\nMODULE_DESCRIPTION(\"Awinic AW9523 I2C GPIO Expander driver\");\nMODULE_AUTHOR(\"AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>\");\nMODULE_LICENSE(\"GPL v2\");\nMODULE_ALIAS(\"platform:aw9523\");\n"
  },
  {
    "path": "target/linux/ramips/image/Makefile",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2008-2011 OpenWrt.org\n\ninclude $(TOPDIR)/rules.mk\ninclude $(INCLUDE_DIR)/image.mk\n\nDEVICE_VARS += LOADER_TYPE LOADER_FLASH_OFFS\nDEVICE_VARS += NETGEAR_BOARD_ID NETGEAR_HW_ID\nDEVICE_VARS += BUFFALO_TAG_PLATFORM BUFFALO_TAG_VERSION BUFFALO_TAG_MINOR\nDEVICE_VARS += SEAMA_SIGNATURE SEAMA_MTDBLOCK\nDEVICE_VARS += SERCOMM_HWNAME SERCOMM_HWID SERCOMM_HWVER SERCOMM_SWVER\nDEVICE_VARS += SERCOMM_PAD JCG_MAXSIZE\n\nloadaddr-y := 0x80000000\nloadaddr-$(CONFIG_TARGET_ramips_rt288x) := 0x88000000\nloadaddr-$(CONFIG_TARGET_ramips_mt7621) := 0x80001000\n\nldrplatform-y := ralink\nldrplatform-$(CONFIG_TARGET_ramips_mt7621) := mt7621\n\nldrflashstart-y := 0x1c000000\nldrflashstart-$(CONFIG_TARGET_ramips_mt7621) := 0x1fc00000\n\nLOADER_PLATFORM := $(ldrplatform-y)\nLOADER_FLASH_START := $(ldrflashstart-y)\n\nKERNEL_DTB = kernel-bin | append-dtb | lzma\n\ndefine Build/edimax-header\n\t$(STAGING_DIR_HOST)/bin/mkedimaximg -i $@ -o $@.new $(1)\n\t@mv $@.new $@\nendef\n\ndefine Build/jcg-header\n\t$(STAGING_DIR_HOST)/bin/jcgimage -v $(1) \\\n\t\t$(if $(JCG_MAXSIZE), -m $$(($(subst k, * 1024,$(JCG_MAXSIZE)))),) \\\n\t\t-u $@ -o $@.new\n\tmv $@.new $@\nendef\n\ndefine Build/loader-common\n\trm -rf $@.src\n\t$(MAKE) -C lzma-loader \\\n\t\tPKG_BUILD_DIR=\"$@.src\" \\\n\t\tTARGET_DIR=\"$(dir $@)\" LOADER_NAME=\"$(notdir $@)\" \\\n\t\tBOARD=\"$(BOARDNAME)\" PLATFORM=\"$(LOADER_PLATFORM)\" \\\n\t\tLZMA_TEXT_START=0x81800000 LOADADDR=$(KERNEL_LOADADDR) \\\n\t\t$(1) compile loader.$(LOADER_TYPE)\n\tmv \"$@.$(LOADER_TYPE)\" \"$@\"\n\trm -rf $@.src\nendef\n\ndefine Build/loader-kernel\n\t$(call Build/loader-common,LOADER_DATA=\"$@\")\nendef\n\ndefine Build/loader-okli-compile\n\t$(call Build/loader-common, \\\n\t\tFLASH_START=$(LOADER_FLASH_START) \\\n\t\tFLASH_OFFS=$(LOADER_FLASH_OFFS) \\\n\t\tFLASH_MAX=0 \\\n\t)\nendef\n\ndefine Build/append-loader-okli\n\tcat \"$(KDIR)/loader-$(word 1,$(1)).$(LOADER_TYPE)\" >> \"$@\"\nendef\n\n# combine kernel and rootfs into one image\n# mkdlinkfw <type> <optional extra arguments to mkdlinkfw binary>\ndefine Build/mkdlinkfw\n\t-$(STAGING_DIR_HOST)/bin/mkdlinkfw \\\n\t\t-k $(IMAGE_KERNEL) \\\n\t\t-r $(IMAGE_ROOTFS) \\\n\t\t-o $@ \\\n\t\t$(if $(DLINK_IMAGE_OFFSET), -O $(DLINK_IMAGE_OFFSET)) \\\n\t\t-s $(DLINK_FIRMWARE_SIZE)\nendef\n\ndefine Build/mkdlinkfw-factory\n\t-$(STAGING_DIR_HOST)/bin/mkdlinkfw \\\n\t\t-m $(DLINK_ROM_ID) -f $(DLINK_FAMILY_MEMBER) \\\n\t\t-F $@ \\\n\t\t-o $@.new \\\n\t\t$(if $(DLINK_IMAGE_OFFSET), -O $(DLINK_IMAGE_OFFSET)) \\\n\t\t-s $(DLINK_FIRMWARE_SIZE)\n\tmv $@.new $@\nendef\n\ndefine Build/mkdlinkfw-loader\n\t-$(STAGING_DIR_HOST)/bin/mkdlinkfw \\\n\t\t-k $(KDIR)/loader-$(DEVICE_NAME).bin \\\n\t\t-r $@ \\\n\t\t-o $@.new \\\n\t\t$(if $(DLINK_IMAGE_OFFSET), -O $(DLINK_IMAGE_OFFSET)) \\\n\t\t-s $(DLINK_FIRMWARE_SIZE)\n\tmv $@.new $@\nendef\n\ndefine Build/netis-tail\n\techo -n $(1) >> $@\n\techo -n $(UIMAGE_NAME)-yun | $(MKHASH) md5 | \\\n\t\tsed 's/../\\\\\\\\x&/g' | xargs echo -ne >> $@\nendef\n\ndefine Build/poray-header\n\t$(STAGING_DIR_HOST)/bin/mkporayfw $(1) -f $@ -o $@.new\n\tmv $@.new $@\nendef\n\ndefine Build/relocate-kernel\n\trm -rf $@.relocate\n\t$(CP) ../../generic/image/relocate $@.relocate\n\t$(MAKE) -C $@.relocate KERNEL_ADDR=$(if $(1),$(1),$(KERNEL_LOADADDR)) CROSS_COMPILE=$(TARGET_CROSS)\n\t( \\\n\t\tdd if=$@.relocate/loader.bin bs=32 conv=sync && \\\n\t\tperl -e '@s = stat(\"$@\"); print pack(\"V\", @s[7])' && \\\n\t\tcat $@ \\\n\t) > $@.new\n\tmv $@.new $@\n\trm -rf $@.relocate\nendef\n\ndefine Build/sercom-footer\n\t$(call Build/sercom-seal,-f)\nendef\n\ndefine Build/sercom-seal\n\t$(STAGING_DIR_HOST)/bin/mksercommfw \\\n\t\t-i $@ \\\n\t\t-b $(SERCOMM_HWID) \\\n\t\t-r $(SERCOMM_HWVER) \\\n\t\t-v $(SERCOMM_SWVER) \\\n\t\t$(1)\nendef\n\ndefine Build/sign-dlink-ru\n\tsign_dlink_ru $@ $1 $2\n\tmv $@.new $@\nendef\n\ndefine Build/trx\n\t$(STAGING_DIR_HOST)/bin/trx $(1) \\\n\t\t-o $@ \\\n\t\t-m $$(($(subst k, * 1024,$(IMAGE_SIZE)))) \\\n\t\t-f $(IMAGE_KERNEL) \\\n\t\t-a 4 -f $(IMAGE_ROOTFS)\nendef\n\ndefine Build/uimage-padhdr\n\tuimage_padhdr $(if $(1),-l $(1)) -i $@ -o $@.new\n\tmv $@.new $@\nendef\n\ndefine Build/uimage-sgehdr\n\tuimage_sgehdr -i $@ -o $@.new -m $(DEVICE_MODEL) \\\n\t\t-h $(DEVICE_VARIANT) -s V1.00000\n\tmv $@.new $@\nendef\n\ndefine Build/umedia-header\n\tfix-u-media-header -T 0x46 -B $(1) -i $@ -o $@.new && mv $@.new $@\nendef\n\ndefine Build/wrg-header\n\tmkwrgimg -i $@ -d \"/dev/mtdblock/2\" -s $(1) -o $@.new\n\tmv $@.new $@\nendef\n\ndefine Build/zyimage\n\t$(STAGING_DIR_HOST)/bin/zyimage $(1) $@\nendef\n\ndefine Device/Default\n  PROFILES = Default\n  KERNEL := $(KERNEL_DTB) | uImage lzma\n  KERNEL_LOADADDR := $(loadaddr-y)\n  SOC := $(DEFAULT_SOC)\n  DEVICE_DTS_DIR := ../dts\n  DEVICE_DTS = $$(SOC)_$(1)\n  IMAGES := sysupgrade.bin\n  COMPILE :=\n  sysupgrade_bin := append-kernel | append-rootfs | pad-rootfs\n  IMAGE/sysupgrade.bin := append-kernel | append-rootfs | pad-rootfs | check-size | append-metadata\nendef\n\ndefine Device/netgear_sercomm_nor\n  BLOCKSIZE := 64k\n  DEVICE_VENDOR := NETGEAR\n  IMAGES += factory.img\n  IMAGE/default := append-kernel | pad-to $$$$(BLOCKSIZE) | append-rootfs | \\\n\tpad-rootfs\n  IMAGE/sysupgrade.bin := $$(IMAGE/default) | check-size | append-metadata\n  IMAGE/factory.img := pad-extra $$$$(SERCOMM_PAD) | $$(IMAGE/default) | \\\n\tpad-to $$$$(BLOCKSIZE) | sercom-footer | pad-to 128 | \\\n\tzip $$$$(SERCOMM_HWNAME).bin | sercom-seal\nendef\n\ndefine Device/seama\n  BLOCKSIZE := 64k\n  SEAMA_MTDBLOCK := 2\n  IMAGES += factory.bin\n\n  # 64 bytes offset:\n  # - 28 bytes seama_header\n  # - 36 bytes of META data (4-bytes aligned)\n  IMAGE/default := append-kernel | pad-offset $$$$(BLOCKSIZE) 64 | append-rootfs\n  IMAGE/sysupgrade.bin := \\\n\t$$(IMAGE/default) | seama | pad-rootfs | check-size | append-metadata\n  IMAGE/factory.bin := \\\n\t$$(IMAGE/default) | pad-rootfs -x 64 | seama | seama-seal | check-size\n  SEAMA_SIGNATURE :=\nendef\n\ndefine Device/uimage-lzma-loader\n  LOADER_TYPE := bin\n  KERNEL := kernel-bin | append-dtb | lzma | loader-kernel | uImage none\nendef\n\ninclude $(SUBTARGET).mk\n\n$(eval $(call BuildImage))\n"
  },
  {
    "path": "target/linux/ramips/image/common-tp-link.mk",
    "content": "DEVICE_VARS += TPLINK_FLASHLAYOUT TPLINK_HWID TPLINK_HWREV TPLINK_HWREVADD\nDEVICE_VARS += TPLINK_HVERSION TPLINK_BOARD_ID TPLINK_HEADER_VERSION\n\ndefine Device/tplink-v1\n  DEVICE_VENDOR := TP-Link\n  TPLINK_FLASHLAYOUT :=\n  TPLINK_HWID :=\n  TPLINK_HWREV := 0x1\n  TPLINK_HEADER_VERSION := 1\n  KERNEL := $(KERNEL_DTB)\n  KERNEL_INITRAMFS := $(KERNEL_DTB) | tplink-v1-header -e -O\n  IMAGES += factory.bin\n  IMAGE/factory.bin := tplink-v1-image factory -e -O\n  IMAGE/sysupgrade.bin := tplink-v1-image sysupgrade -e -O | check-size | \\\n\tappend-metadata\nendef\n\ndefine Device/tplink-v2\n  DEVICE_VENDOR := TP-Link\n  TPLINK_FLASHLAYOUT :=\n  TPLINK_HWID :=\n  TPLINK_HWREV := 0x1\n  TPLINK_HWREVADD := 0x0\n  TPLINK_HVERSION := 3\n  KERNEL := $(KERNEL_DTB)\n  KERNEL_INITRAMFS := $(KERNEL_DTB) | tplink-v2-header -e\n  IMAGES += factory.bin\n  IMAGE/factory.bin := tplink-v2-image -e\n  IMAGE/sysupgrade.bin := tplink-v2-image -s -e | check-size | \\\n\tappend-metadata\nendef\n\ndefine Device/tplink-safeloader\n  DEVICE_VENDOR := TP-Link\n  TPLINK_BOARD_ID :=\n  TPLINK_HWID := 0x0\n  TPLINK_HWREV := 0x0\n  TPLINK_HEADER_VERSION := 1\n  KERNEL := $(KERNEL_DTB) | tplink-v1-header -e -O\n  IMAGES += factory.bin\n  IMAGE/sysupgrade.bin := append-rootfs | tplink-safeloader sysupgrade | \\\n\tcheck-size | append-metadata\n  IMAGE/factory.bin := append-rootfs | tplink-safeloader factory\nendef\n"
  },
  {
    "path": "target/linux/ramips/image/lzma-loader/Makefile",
    "content": "#\n# Copyright (C) 2011 OpenWrt.org\n# Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nLZMA_TEXT_START\t:= 0x80a00000\nLOADER\t\t:= loader.bin\nLOADER_NAME\t:= $(basename $(notdir $(LOADER)))\nLOADER_DATA \t:=\nTARGET_DIR\t:=\nFLASH_START\t:=\nFLASH_OFFS\t:=\nFLASH_MAX\t:=\nBOARD\t\t:=\nPLATFORM\t:=\n\nifeq ($(TARGET_DIR),)\nTARGET_DIR\t:= $(KDIR)\nendif\n\nLOADER_BIN\t:= $(TARGET_DIR)/$(LOADER_NAME).bin\nLOADER_GZ\t:= $(TARGET_DIR)/$(LOADER_NAME).gz\nLOADER_ELF\t:= $(TARGET_DIR)/$(LOADER_NAME).elf\n\nPKG_NAME := lzma-loader\nPKG_BUILD_DIR := $(KDIR)/$(PKG_NAME)\n\n.PHONY : loader-compile loader.bin loader.elf loader.gz\n\n$(PKG_BUILD_DIR)/.prepared:\n\tmkdir $(PKG_BUILD_DIR)\n\t$(CP) ./src/* $(PKG_BUILD_DIR)/\n\ttouch $@\n\nloader-compile: $(PKG_BUILD_DIR)/.prepared\n\t$(MAKE) -C $(PKG_BUILD_DIR) CROSS_COMPILE=\"$(TARGET_CROSS)\" \\\n\t\tLZMA_TEXT_START=$(LZMA_TEXT_START) \\\n\t\tLOADER_DATA=$(LOADER_DATA) \\\n\t\tFLASH_START=$(FLASH_START) \\\n\t\tFLASH_OFFS=$(FLASH_OFFS) \\\n\t\tFLASH_MAX=$(FLASH_MAX) \\\n\t\tBOARD=\"$(BOARD)\" \\\n\t\tPLATFORM=\"$(PLATFORM)\" \\\n\t\tclean all\n\nloader.gz: $(PKG_BUILD_DIR)/loader.bin\n\tgzip -nc9 $< > $(LOADER_GZ)\n\nloader.elf: $(PKG_BUILD_DIR)/loader.elf\n\t$(CP) $< $(LOADER_ELF)\n\nloader.bin: $(PKG_BUILD_DIR)/loader.bin\n\t$(CP) $< $(LOADER_BIN)\n\ndownload:\nprepare: $(PKG_BUILD_DIR)/.prepared\ncompile: loader-compile\n\ninstall:\n\nclean:\n\trm -rf $(PKG_BUILD_DIR)\n\n"
  },
  {
    "path": "target/linux/ramips/image/lzma-loader/src/LzmaDecode.c",
    "content": "/*\n  LzmaDecode.c\n  LZMA Decoder (optimized for Speed version)\n  \n  LZMA SDK 4.40 Copyright (c) 1999-2006 Igor Pavlov (2006-05-01)\n  http://www.7-zip.org/\n\n  LZMA SDK is licensed under two licenses:\n  1) GNU Lesser General Public License (GNU LGPL)\n  2) Common Public License (CPL)\n  It means that you can select one of these two licenses and \n  follow rules of that license.\n\n  SPECIAL EXCEPTION:\n  Igor Pavlov, as the author of this Code, expressly permits you to \n  statically or dynamically link your Code (or bind by name) to the \n  interfaces of this file without subjecting your linked Code to the \n  terms of the CPL or GNU LGPL. Any modifications or additions \n  to this file, however, are subject to the LGPL or CPL terms.\n*/\n\n#include \"LzmaDecode.h\"\n\n#define kNumTopBits 24\n#define kTopValue ((UInt32)1 << kNumTopBits)\n\n#define kNumBitModelTotalBits 11\n#define kBitModelTotal (1 << kNumBitModelTotalBits)\n#define kNumMoveBits 5\n\n#define RC_READ_BYTE (*Buffer++)\n\n#define RC_INIT2 Code = 0; Range = 0xFFFFFFFF; \\\n  { int i; for(i = 0; i < 5; i++) { RC_TEST; Code = (Code << 8) | RC_READ_BYTE; }}\n\n#ifdef _LZMA_IN_CB\n\n#define RC_TEST { if (Buffer == BufferLim) \\\n  { SizeT size; int result = InCallback->Read(InCallback, &Buffer, &size); if (result != LZMA_RESULT_OK) return result; \\\n  BufferLim = Buffer + size; if (size == 0) return LZMA_RESULT_DATA_ERROR; }}\n\n#define RC_INIT Buffer = BufferLim = 0; RC_INIT2\n\n#else\n\n#define RC_TEST { if (Buffer == BufferLim) return LZMA_RESULT_DATA_ERROR; }\n\n#define RC_INIT(buffer, bufferSize) Buffer = buffer; BufferLim = buffer + bufferSize; RC_INIT2\n \n#endif\n\n#define RC_NORMALIZE if (Range < kTopValue) { RC_TEST; Range <<= 8; Code = (Code << 8) | RC_READ_BYTE; }\n\n#define IfBit0(p) RC_NORMALIZE; bound = (Range >> kNumBitModelTotalBits) * *(p); if (Code < bound)\n#define UpdateBit0(p) Range = bound; *(p) += (kBitModelTotal - *(p)) >> kNumMoveBits;\n#define UpdateBit1(p) Range -= bound; Code -= bound; *(p) -= (*(p)) >> kNumMoveBits;\n\n#define RC_GET_BIT2(p, mi, A0, A1) IfBit0(p) \\\n  { UpdateBit0(p); mi <<= 1; A0; } else \\\n  { UpdateBit1(p); mi = (mi + mi) + 1; A1; } \n  \n#define RC_GET_BIT(p, mi) RC_GET_BIT2(p, mi, ; , ;)               \n\n#define RangeDecoderBitTreeDecode(probs, numLevels, res) \\\n  { int i = numLevels; res = 1; \\\n  do { CProb *p = probs + res; RC_GET_BIT(p, res) } while(--i != 0); \\\n  res -= (1 << numLevels); }\n\n\n#define kNumPosBitsMax 4\n#define kNumPosStatesMax (1 << kNumPosBitsMax)\n\n#define kLenNumLowBits 3\n#define kLenNumLowSymbols (1 << kLenNumLowBits)\n#define kLenNumMidBits 3\n#define kLenNumMidSymbols (1 << kLenNumMidBits)\n#define kLenNumHighBits 8\n#define kLenNumHighSymbols (1 << kLenNumHighBits)\n\n#define LenChoice 0\n#define LenChoice2 (LenChoice + 1)\n#define LenLow (LenChoice2 + 1)\n#define LenMid (LenLow + (kNumPosStatesMax << kLenNumLowBits))\n#define LenHigh (LenMid + (kNumPosStatesMax << kLenNumMidBits))\n#define kNumLenProbs (LenHigh + kLenNumHighSymbols) \n\n\n#define kNumStates 12\n#define kNumLitStates 7\n\n#define kStartPosModelIndex 4\n#define kEndPosModelIndex 14\n#define kNumFullDistances (1 << (kEndPosModelIndex >> 1))\n\n#define kNumPosSlotBits 6\n#define kNumLenToPosStates 4\n\n#define kNumAlignBits 4\n#define kAlignTableSize (1 << kNumAlignBits)\n\n#define kMatchMinLen 2\n\n#define IsMatch 0\n#define IsRep (IsMatch + (kNumStates << kNumPosBitsMax))\n#define IsRepG0 (IsRep + kNumStates)\n#define IsRepG1 (IsRepG0 + kNumStates)\n#define IsRepG2 (IsRepG1 + kNumStates)\n#define IsRep0Long (IsRepG2 + kNumStates)\n#define PosSlot (IsRep0Long + (kNumStates << kNumPosBitsMax))\n#define SpecPos (PosSlot + (kNumLenToPosStates << kNumPosSlotBits))\n#define Align (SpecPos + kNumFullDistances - kEndPosModelIndex)\n#define LenCoder (Align + kAlignTableSize)\n#define RepLenCoder (LenCoder + kNumLenProbs)\n#define Literal (RepLenCoder + kNumLenProbs)\n\n#if Literal != LZMA_BASE_SIZE\nStopCompilingDueBUG\n#endif\n\nint LzmaDecodeProperties(CLzmaProperties *propsRes, const unsigned char *propsData, int size)\n{\n  unsigned char prop0;\n  if (size < LZMA_PROPERTIES_SIZE)\n    return LZMA_RESULT_DATA_ERROR;\n  prop0 = propsData[0];\n  if (prop0 >= (9 * 5 * 5))\n    return LZMA_RESULT_DATA_ERROR;\n  {\n    for (propsRes->pb = 0; prop0 >= (9 * 5); propsRes->pb++, prop0 -= (9 * 5));\n    for (propsRes->lp = 0; prop0 >= 9; propsRes->lp++, prop0 -= 9);\n    propsRes->lc = prop0;\n    /*\n    unsigned char remainder = (unsigned char)(prop0 / 9);\n    propsRes->lc = prop0 % 9;\n    propsRes->pb = remainder / 5;\n    propsRes->lp = remainder % 5;\n    */\n  }\n\n  #ifdef _LZMA_OUT_READ\n  {\n    int i;\n    propsRes->DictionarySize = 0;\n    for (i = 0; i < 4; i++)\n      propsRes->DictionarySize += (UInt32)(propsData[1 + i]) << (i * 8);\n    if (propsRes->DictionarySize == 0)\n      propsRes->DictionarySize = 1;\n  }\n  #endif\n  return LZMA_RESULT_OK;\n}\n\n#define kLzmaStreamWasFinishedId (-1)\n\nint LzmaDecode(CLzmaDecoderState *vs,\n    #ifdef _LZMA_IN_CB\n    ILzmaInCallback *InCallback,\n    #else\n    const unsigned char *inStream, SizeT inSize, SizeT *inSizeProcessed,\n    #endif\n    unsigned char *outStream, SizeT outSize, SizeT *outSizeProcessed)\n{\n  CProb *p = vs->Probs;\n  SizeT nowPos = 0;\n  Byte previousByte = 0;\n  UInt32 posStateMask = (1 << (vs->Properties.pb)) - 1;\n  UInt32 literalPosMask = (1 << (vs->Properties.lp)) - 1;\n  int lc = vs->Properties.lc;\n\n  #ifdef _LZMA_OUT_READ\n  \n  UInt32 Range = vs->Range;\n  UInt32 Code = vs->Code;\n  #ifdef _LZMA_IN_CB\n  const Byte *Buffer = vs->Buffer;\n  const Byte *BufferLim = vs->BufferLim;\n  #else\n  const Byte *Buffer = inStream;\n  const Byte *BufferLim = inStream + inSize;\n  #endif\n  int state = vs->State;\n  UInt32 rep0 = vs->Reps[0], rep1 = vs->Reps[1], rep2 = vs->Reps[2], rep3 = vs->Reps[3];\n  int len = vs->RemainLen;\n  UInt32 globalPos = vs->GlobalPos;\n  UInt32 distanceLimit = vs->DistanceLimit;\n\n  Byte *dictionary = vs->Dictionary;\n  UInt32 dictionarySize = vs->Properties.DictionarySize;\n  UInt32 dictionaryPos = vs->DictionaryPos;\n\n  Byte tempDictionary[4];\n\n  #ifndef _LZMA_IN_CB\n  *inSizeProcessed = 0;\n  #endif\n  *outSizeProcessed = 0;\n  if (len == kLzmaStreamWasFinishedId)\n    return LZMA_RESULT_OK;\n\n  if (dictionarySize == 0)\n  {\n    dictionary = tempDictionary;\n    dictionarySize = 1;\n    tempDictionary[0] = vs->TempDictionary[0];\n  }\n\n  if (len == kLzmaNeedInitId)\n  {\n    {\n      UInt32 numProbs = Literal + ((UInt32)LZMA_LIT_SIZE << (lc + vs->Properties.lp));\n      UInt32 i;\n      for (i = 0; i < numProbs; i++)\n        p[i] = kBitModelTotal >> 1; \n      rep0 = rep1 = rep2 = rep3 = 1;\n      state = 0;\n      globalPos = 0;\n      distanceLimit = 0;\n      dictionaryPos = 0;\n      dictionary[dictionarySize - 1] = 0;\n      #ifdef _LZMA_IN_CB\n      RC_INIT;\n      #else\n      RC_INIT(inStream, inSize);\n      #endif\n    }\n    len = 0;\n  }\n  while(len != 0 && nowPos < outSize)\n  {\n    UInt32 pos = dictionaryPos - rep0;\n    if (pos >= dictionarySize)\n      pos += dictionarySize;\n    outStream[nowPos++] = dictionary[dictionaryPos] = dictionary[pos];\n    if (++dictionaryPos == dictionarySize)\n      dictionaryPos = 0;\n    len--;\n  }\n  if (dictionaryPos == 0)\n    previousByte = dictionary[dictionarySize - 1];\n  else\n    previousByte = dictionary[dictionaryPos - 1];\n\n  #else /* if !_LZMA_OUT_READ */\n\n  int state = 0;\n  UInt32 rep0 = 1, rep1 = 1, rep2 = 1, rep3 = 1;\n  int len = 0;\n  const Byte *Buffer;\n  const Byte *BufferLim;\n  UInt32 Range;\n  UInt32 Code;\n\n  #ifndef _LZMA_IN_CB\n  *inSizeProcessed = 0;\n  #endif\n  *outSizeProcessed = 0;\n\n  {\n    UInt32 i;\n    UInt32 numProbs = Literal + ((UInt32)LZMA_LIT_SIZE << (lc + vs->Properties.lp));\n    for (i = 0; i < numProbs; i++)\n      p[i] = kBitModelTotal >> 1;\n  }\n  \n  #ifdef _LZMA_IN_CB\n  RC_INIT;\n  #else\n  RC_INIT(inStream, inSize);\n  #endif\n\n  #endif /* _LZMA_OUT_READ */\n\n  while(nowPos < outSize)\n  {\n    CProb *prob;\n    UInt32 bound;\n    int posState = (int)(\n        (nowPos \n        #ifdef _LZMA_OUT_READ\n        + globalPos\n        #endif\n        )\n        & posStateMask);\n\n    prob = p + IsMatch + (state << kNumPosBitsMax) + posState;\n    IfBit0(prob)\n    {\n      int symbol = 1;\n      UpdateBit0(prob)\n      prob = p + Literal + (LZMA_LIT_SIZE * \n        (((\n        (nowPos \n        #ifdef _LZMA_OUT_READ\n        + globalPos\n        #endif\n        )\n        & literalPosMask) << lc) + (previousByte >> (8 - lc))));\n\n      if (state >= kNumLitStates)\n      {\n        int matchByte;\n        #ifdef _LZMA_OUT_READ\n        UInt32 pos = dictionaryPos - rep0;\n        if (pos >= dictionarySize)\n          pos += dictionarySize;\n        matchByte = dictionary[pos];\n        #else\n        matchByte = outStream[nowPos - rep0];\n        #endif\n        do\n        {\n          int bit;\n          CProb *probLit;\n          matchByte <<= 1;\n          bit = (matchByte & 0x100);\n          probLit = prob + 0x100 + bit + symbol;\n          RC_GET_BIT2(probLit, symbol, if (bit != 0) break, if (bit == 0) break)\n        }\n        while (symbol < 0x100);\n      }\n      while (symbol < 0x100)\n      {\n        CProb *probLit = prob + symbol;\n        RC_GET_BIT(probLit, symbol)\n      }\n      previousByte = (Byte)symbol;\n\n      outStream[nowPos++] = previousByte;\n      #ifdef _LZMA_OUT_READ\n      if (distanceLimit < dictionarySize)\n        distanceLimit++;\n\n      dictionary[dictionaryPos] = previousByte;\n      if (++dictionaryPos == dictionarySize)\n        dictionaryPos = 0;\n      #endif\n      if (state < 4) state = 0;\n      else if (state < 10) state -= 3;\n      else state -= 6;\n    }\n    else             \n    {\n      UpdateBit1(prob);\n      prob = p + IsRep + state;\n      IfBit0(prob)\n      {\n        UpdateBit0(prob);\n        rep3 = rep2;\n        rep2 = rep1;\n        rep1 = rep0;\n        state = state < kNumLitStates ? 0 : 3;\n        prob = p + LenCoder;\n      }\n      else\n      {\n        UpdateBit1(prob);\n        prob = p + IsRepG0 + state;\n        IfBit0(prob)\n        {\n          UpdateBit0(prob);\n          prob = p + IsRep0Long + (state << kNumPosBitsMax) + posState;\n          IfBit0(prob)\n          {\n            #ifdef _LZMA_OUT_READ\n            UInt32 pos;\n            #endif\n            UpdateBit0(prob);\n            \n            #ifdef _LZMA_OUT_READ\n            if (distanceLimit == 0)\n            #else\n            if (nowPos == 0)\n            #endif\n              return LZMA_RESULT_DATA_ERROR;\n            \n            state = state < kNumLitStates ? 9 : 11;\n            #ifdef _LZMA_OUT_READ\n            pos = dictionaryPos - rep0;\n            if (pos >= dictionarySize)\n              pos += dictionarySize;\n            previousByte = dictionary[pos];\n            dictionary[dictionaryPos] = previousByte;\n            if (++dictionaryPos == dictionarySize)\n              dictionaryPos = 0;\n            #else\n            previousByte = outStream[nowPos - rep0];\n            #endif\n            outStream[nowPos++] = previousByte;\n            #ifdef _LZMA_OUT_READ\n            if (distanceLimit < dictionarySize)\n              distanceLimit++;\n            #endif\n\n            continue;\n          }\n          else\n          {\n            UpdateBit1(prob);\n          }\n        }\n        else\n        {\n          UInt32 distance;\n          UpdateBit1(prob);\n          prob = p + IsRepG1 + state;\n          IfBit0(prob)\n          {\n            UpdateBit0(prob);\n            distance = rep1;\n          }\n          else \n          {\n            UpdateBit1(prob);\n            prob = p + IsRepG2 + state;\n            IfBit0(prob)\n            {\n              UpdateBit0(prob);\n              distance = rep2;\n            }\n            else\n            {\n              UpdateBit1(prob);\n              distance = rep3;\n              rep3 = rep2;\n            }\n            rep2 = rep1;\n          }\n          rep1 = rep0;\n          rep0 = distance;\n        }\n        state = state < kNumLitStates ? 8 : 11;\n        prob = p + RepLenCoder;\n      }\n      {\n        int numBits, offset;\n        CProb *probLen = prob + LenChoice;\n        IfBit0(probLen)\n        {\n          UpdateBit0(probLen);\n          probLen = prob + LenLow + (posState << kLenNumLowBits);\n          offset = 0;\n          numBits = kLenNumLowBits;\n        }\n        else\n        {\n          UpdateBit1(probLen);\n          probLen = prob + LenChoice2;\n          IfBit0(probLen)\n          {\n            UpdateBit0(probLen);\n            probLen = prob + LenMid + (posState << kLenNumMidBits);\n            offset = kLenNumLowSymbols;\n            numBits = kLenNumMidBits;\n          }\n          else\n          {\n            UpdateBit1(probLen);\n            probLen = prob + LenHigh;\n            offset = kLenNumLowSymbols + kLenNumMidSymbols;\n            numBits = kLenNumHighBits;\n          }\n        }\n        RangeDecoderBitTreeDecode(probLen, numBits, len);\n        len += offset;\n      }\n\n      if (state < 4)\n      {\n        int posSlot;\n        state += kNumLitStates;\n        prob = p + PosSlot +\n            ((len < kNumLenToPosStates ? len : kNumLenToPosStates - 1) << \n            kNumPosSlotBits);\n        RangeDecoderBitTreeDecode(prob, kNumPosSlotBits, posSlot);\n        if (posSlot >= kStartPosModelIndex)\n        {\n          int numDirectBits = ((posSlot >> 1) - 1);\n          rep0 = (2 | ((UInt32)posSlot & 1));\n          if (posSlot < kEndPosModelIndex)\n          {\n            rep0 <<= numDirectBits;\n            prob = p + SpecPos + rep0 - posSlot - 1;\n          }\n          else\n          {\n            numDirectBits -= kNumAlignBits;\n            do\n            {\n              RC_NORMALIZE\n              Range >>= 1;\n              rep0 <<= 1;\n              if (Code >= Range)\n              {\n                Code -= Range;\n                rep0 |= 1;\n              }\n            }\n            while (--numDirectBits != 0);\n            prob = p + Align;\n            rep0 <<= kNumAlignBits;\n            numDirectBits = kNumAlignBits;\n          }\n          {\n            int i = 1;\n            int mi = 1;\n            do\n            {\n              CProb *prob3 = prob + mi;\n              RC_GET_BIT2(prob3, mi, ; , rep0 |= i);\n              i <<= 1;\n            }\n            while(--numDirectBits != 0);\n          }\n        }\n        else\n          rep0 = posSlot;\n        if (++rep0 == (UInt32)(0))\n        {\n          /* it's for stream version */\n          len = kLzmaStreamWasFinishedId;\n          break;\n        }\n      }\n\n      len += kMatchMinLen;\n      #ifdef _LZMA_OUT_READ\n      if (rep0 > distanceLimit) \n      #else\n      if (rep0 > nowPos)\n      #endif\n        return LZMA_RESULT_DATA_ERROR;\n\n      #ifdef _LZMA_OUT_READ\n      if (dictionarySize - distanceLimit > (UInt32)len)\n        distanceLimit += len;\n      else\n        distanceLimit = dictionarySize;\n      #endif\n\n      do\n      {\n        #ifdef _LZMA_OUT_READ\n        UInt32 pos = dictionaryPos - rep0;\n        if (pos >= dictionarySize)\n          pos += dictionarySize;\n        previousByte = dictionary[pos];\n        dictionary[dictionaryPos] = previousByte;\n        if (++dictionaryPos == dictionarySize)\n          dictionaryPos = 0;\n        #else\n        previousByte = outStream[nowPos - rep0];\n        #endif\n        len--;\n        outStream[nowPos++] = previousByte;\n      }\n      while(len != 0 && nowPos < outSize);\n    }\n  }\n  RC_NORMALIZE;\n\n  #ifdef _LZMA_OUT_READ\n  vs->Range = Range;\n  vs->Code = Code;\n  vs->DictionaryPos = dictionaryPos;\n  vs->GlobalPos = globalPos + (UInt32)nowPos;\n  vs->DistanceLimit = distanceLimit;\n  vs->Reps[0] = rep0;\n  vs->Reps[1] = rep1;\n  vs->Reps[2] = rep2;\n  vs->Reps[3] = rep3;\n  vs->State = state;\n  vs->RemainLen = len;\n  vs->TempDictionary[0] = tempDictionary[0];\n  #endif\n\n  #ifdef _LZMA_IN_CB\n  vs->Buffer = Buffer;\n  vs->BufferLim = BufferLim;\n  #else\n  *inSizeProcessed = (SizeT)(Buffer - inStream);\n  #endif\n  *outSizeProcessed = nowPos;\n  return LZMA_RESULT_OK;\n}\n"
  },
  {
    "path": "target/linux/ramips/image/lzma-loader/src/LzmaDecode.h",
    "content": "/* \n  LzmaDecode.h\n  LZMA Decoder interface\n\n  LZMA SDK 4.40 Copyright (c) 1999-2006 Igor Pavlov (2006-05-01)\n  http://www.7-zip.org/\n\n  LZMA SDK is licensed under two licenses:\n  1) GNU Lesser General Public License (GNU LGPL)\n  2) Common Public License (CPL)\n  It means that you can select one of these two licenses and \n  follow rules of that license.\n\n  SPECIAL EXCEPTION:\n  Igor Pavlov, as the author of this code, expressly permits you to \n  statically or dynamically link your code (or bind by name) to the \n  interfaces of this file without subjecting your linked code to the \n  terms of the CPL or GNU LGPL. Any modifications or additions \n  to this file, however, are subject to the LGPL or CPL terms.\n*/\n\n#ifndef __LZMADECODE_H\n#define __LZMADECODE_H\n\n#include \"LzmaTypes.h\"\n\n/* #define _LZMA_IN_CB */\n/* Use callback for input data */\n\n/* #define _LZMA_OUT_READ */\n/* Use read function for output data */\n\n/* #define _LZMA_PROB32 */\n/* It can increase speed on some 32-bit CPUs, \n   but memory usage will be doubled in that case */\n\n/* #define _LZMA_LOC_OPT */\n/* Enable local speed optimizations inside code */\n\n#ifdef _LZMA_PROB32\n#define CProb UInt32\n#else\n#define CProb UInt16\n#endif\n\n#define LZMA_RESULT_OK 0\n#define LZMA_RESULT_DATA_ERROR 1\n\n#ifdef _LZMA_IN_CB\ntypedef struct _ILzmaInCallback\n{\n  int (*Read)(void *object, const unsigned char **buffer, SizeT *bufferSize);\n} ILzmaInCallback;\n#endif\n\n#define LZMA_BASE_SIZE 1846\n#define LZMA_LIT_SIZE 768\n\n#define LZMA_PROPERTIES_SIZE 5\n\ntypedef struct _CLzmaProperties\n{\n  int lc;\n  int lp;\n  int pb;\n  #ifdef _LZMA_OUT_READ\n  UInt32 DictionarySize;\n  #endif\n}CLzmaProperties;\n\nint LzmaDecodeProperties(CLzmaProperties *propsRes, const unsigned char *propsData, int size);\n\n#define LzmaGetNumProbs(Properties) (LZMA_BASE_SIZE + (LZMA_LIT_SIZE << ((Properties)->lc + (Properties)->lp)))\n\n#define kLzmaNeedInitId (-2)\n\ntypedef struct _CLzmaDecoderState\n{\n  CLzmaProperties Properties;\n  CProb *Probs;\n\n  #ifdef _LZMA_IN_CB\n  const unsigned char *Buffer;\n  const unsigned char *BufferLim;\n  #endif\n\n  #ifdef _LZMA_OUT_READ\n  unsigned char *Dictionary;\n  UInt32 Range;\n  UInt32 Code;\n  UInt32 DictionaryPos;\n  UInt32 GlobalPos;\n  UInt32 DistanceLimit;\n  UInt32 Reps[4];\n  int State;\n  int RemainLen;\n  unsigned char TempDictionary[4];\n  #endif\n} CLzmaDecoderState;\n\n#ifdef _LZMA_OUT_READ\n#define LzmaDecoderInit(vs) { (vs)->RemainLen = kLzmaNeedInitId; }\n#endif\n\nint LzmaDecode(CLzmaDecoderState *vs,\n    #ifdef _LZMA_IN_CB\n    ILzmaInCallback *inCallback,\n    #else\n    const unsigned char *inStream, SizeT inSize, SizeT *inSizeProcessed,\n    #endif\n    unsigned char *outStream, SizeT outSize, SizeT *outSizeProcessed);\n\n#endif\n"
  },
  {
    "path": "target/linux/ramips/image/lzma-loader/src/LzmaTypes.h",
    "content": "/* \nLzmaTypes.h \n\nTypes for LZMA Decoder\n\nThis file written and distributed to public domain by Igor Pavlov.\nThis file is part of LZMA SDK 4.40 (2006-05-01)\n*/\n\n#ifndef __LZMATYPES_H\n#define __LZMATYPES_H\n\n#ifndef _7ZIP_BYTE_DEFINED\n#define _7ZIP_BYTE_DEFINED\ntypedef unsigned char Byte;\n#endif \n\n#ifndef _7ZIP_UINT16_DEFINED\n#define _7ZIP_UINT16_DEFINED\ntypedef unsigned short UInt16;\n#endif \n\n#ifndef _7ZIP_UINT32_DEFINED\n#define _7ZIP_UINT32_DEFINED\n#ifdef _LZMA_UINT32_IS_ULONG\ntypedef unsigned long UInt32;\n#else\ntypedef unsigned int UInt32;\n#endif\n#endif \n\n/* #define _LZMA_NO_SYSTEM_SIZE_T */\n/* You can use it, if you don't want <stddef.h> */\n\n#ifndef _7ZIP_SIZET_DEFINED\n#define _7ZIP_SIZET_DEFINED\n#ifdef _LZMA_NO_SYSTEM_SIZE_T\ntypedef UInt32 SizeT;\n#else\n#include <stddef.h>\ntypedef size_t SizeT;\n#endif\n#endif\n\n#endif\n"
  },
  {
    "path": "target/linux/ramips/image/lzma-loader/src/Makefile",
    "content": "#\n# Makefile for the LZMA compressed kernel loader for\n# Atheros AR7XXX/AR9XXX based boards\n#\n# Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>\n#\n# Some parts of this file was based on the OpenWrt specific lzma-loader\n# for the BCM47xx and ADM5120 based boards:\n#\tCopyright (C) 2004 Manuel Novoa III (mjn3@codepoet.org)\n#\tCopyright (C) 2005 Mineharu Takahara <mtakahar@yahoo.com>\n#\tCopyright (C) 2005 by Oleg I. Vdovikin <oleg@cs.msu.su>\n#\n# This program is free software; you can redistribute it and/or modify it\n# under the terms of the GNU General Public License version 2 as published\n# by the Free Software Foundation.\n#\n\nLOADADDR\t:=\nLZMA_TEXT_START\t:= 0x80a00000\nLOADER_DATA\t:=\nBOARD\t\t:=\nFLASH_START\t:=\nFLASH_OFFS\t:=\nFLASH_MAX\t:=\nPLATFORM\t:=\nCACHE_FLAGS\t:=\n\nCC\t\t:= $(CROSS_COMPILE)gcc\nLD\t\t:= $(CROSS_COMPILE)ld\nOBJCOPY\t\t:= $(CROSS_COMPILE)objcopy\nOBJDUMP\t\t:= $(CROSS_COMPILE)objdump\n\n\ninclude $(PLATFORM).mk\n\nBIN_FLAGS\t:= -O binary -R .reginfo -R .note -R .comment -R .mdebug \\\n\t\t   -R .MIPS.abiflags -S\n\nCFLAGS\t\t= -D__KERNEL__ -Wall -Wstrict-prototypes -Wno-trigraphs -Os \\\n\t\t  -fno-strict-aliasing -fno-common -fomit-frame-pointer -G 0 \\\n\t\t  -mno-abicalls -fno-pic -ffunction-sections -pipe -mlong-calls \\\n\t\t  -fno-common -ffreestanding -fhonour-copts -nostartfiles \\\n\t\t  -mabi=32 -march=mips32r2 \\\n\t\t  -Wa,-32 -Wa,-march=mips32r2 -Wa,-mips32r2 -Wa,--trap\nCFLAGS\t\t+= -D_LZMA_PROB32\nCFLAGS\t\t+= -flto\nCFLAGS\t\t+= $(CACHE_FLAGS)\n\nASFLAGS\t\t= $(CFLAGS) -D__ASSEMBLY__\n\nLDFLAGS\t\t= -static -Wl,--gc-sections -Wl,-no-warn-mismatch\nLDFLAGS\t\t+= -Wl,-e,startup -T loader.lds -Wl,-Ttext,$(LZMA_TEXT_START)\nLDFLAGS\t\t+= -flto -fwhole-program -Wl,-z,max-page-size=4096\n\nO_FORMAT \t= $(shell $(OBJDUMP) -i | head -2 | grep elf32)\n\nOBJECTS\t\t:= head.o loader.o cache.o board-$(PLATFORM).o printf.o LzmaDecode.o\n\nifneq ($(strip $(LOADER_DATA)),)\nOBJECTS\t\t+= data.o\nCFLAGS\t\t+= -DLZMA_WRAPPER=1 -DLOADADDR=$(LOADADDR)\nendif\n\nifneq ($(strip $(KERNEL_CMDLINE)),)\nCFLAGS\t\t+= -DCONFIG_KERNEL_CMDLINE='\"$(KERNEL_CMDLINE)\"'\nendif\n\nifneq ($(strip $(FLASH_START)),)\nCFLAGS\t\t+= -DCONFIG_FLASH_START=$(FLASH_START)\nendif\n\nifneq ($(strip $(FLASH_OFFS)),)\nCFLAGS\t\t+= -DCONFIG_FLASH_OFFS=$(FLASH_OFFS)\nendif\n\nifneq ($(strip $(FLASH_MAX)),)\nCFLAGS\t\t+= -DCONFIG_FLASH_MAX=$(FLASH_MAX)\nendif\n\nall: loader.elf\n\n# Don't build dependencies, this may die if $(CC) isn't gcc\ndep:\n\ninstall:\n\n%.o : %.c\n\t$(CC) $(CFLAGS) -c -o $@ $<\n\n%.o : %.S\n\t$(CC) $(ASFLAGS) -c -o $@ $<\n\ndata.o: $(LOADER_DATA)\n\t$(LD) -r -b binary --oformat $(O_FORMAT) -T lzma-data.lds -o $@ $<\n\nloader: $(OBJECTS)\n\t$(CC) $(CFLAGS) $(LDFLAGS) -o $@ $(OBJECTS)\n\nloader.bin: loader\n\t$(OBJCOPY) $(BIN_FLAGS) $< $@\n\nloader2.o: loader.bin\n\t$(LD) -r -b binary --oformat $(O_FORMAT) -o $@ $<\n\nloader.elf: loader2.o\n\t$(LD) -e startup -T loader2.lds -Ttext $(LOADADDR) -z max-page-size=4096 -o $@ $<\n\nmrproper: clean\n\nclean:\n\trm -f loader *.elf *.bin *.o\n\n\n\n"
  },
  {
    "path": "target/linux/ramips/image/lzma-loader/src/board-mt7621.c",
    "content": "/*\n * Arch specific code for mt7621 based boards, based on code for Ralink boards\n *\n * Copyright (C) 2018 Tobias Schramm <tobleminer@gmail.com>\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of the GNU General Public License version 2 as published\n * by the Free Software Foundation.\n */\n\n#include <stddef.h>\n#include <stdint.h>\n#include \"config.h\"\n\n#define READREG(r)\t\t*(volatile uint32_t *)(r)\n#define WRITEREG(r,v)\t\t*(volatile uint32_t *)(r) = v\n\n#define KSEG1ADDR(_x)\t\t(((_x) & 0x1fffffff) | 0xa0000000)\n\n#define UART_BASE\t\t0xBE000C00\n\n#define UART_TBR_OFFSET\t\t0x00\n#define UART_LSR_OFFSET\t\t0x14\n\n#define UART_LSR_TEMT\t\t(1 << 6)\n\n#define UART_READ(r)\t\tREADREG(UART_BASE + (r))\n#define UART_WRITE(r,v)\t\tWRITEREG(UART_BASE + (r), (v))\n\nvoid board_putc(int ch)\n{\n\twhile (((UART_READ(UART_LSR_OFFSET)) & UART_LSR_TEMT) == 0);\n\tUART_WRITE(UART_TBR_OFFSET, ch);\n\twhile (((UART_READ(UART_LSR_OFFSET)) & UART_LSR_TEMT) == 0);\n}\n\nvoid board_init(void)\n{\n}\n"
  },
  {
    "path": "target/linux/ramips/image/lzma-loader/src/board-ralink.c",
    "content": "/*\n * Arch specific code for Ralink based boards\n *\n * Copyright (C) 2013 John Crispin <blogic@openwrt.org>\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of the GNU General Public License version 2 as published\n * by the Free Software Foundation.\n */\n\n#include <stddef.h>\n#include \"config.h\"\n\n#define READREG(r)\t\t*(volatile unsigned int *)(r)\n#define WRITEREG(r,v)\t\t*(volatile unsigned int *)(r) = v\n\n#define KSEG1ADDR(_x)\t\t(((_x) & 0x1fffffff) | 0xa0000000)\n\n#ifdef CONFIG_SOC_RT288X\n#define UART_BASE\t\t0xb0300c00\n#else\n#define UART_BASE\t\t0xb0000c00\n#endif\n\n#define UART_TX\t\t\t1\n#define UART_LSR\t\t7\n\n#define UART_LSR_THRE\t\t0x20\n\n#define UART_READ(r)\t\tREADREG(UART_BASE + 4 * (r))\n#define UART_WRITE(r,v)\t\tWRITEREG(UART_BASE + 4 * (r), (v))\n\nvoid board_putc(int ch)\n{\n\twhile (((UART_READ(UART_LSR)) & UART_LSR_THRE) == 0);\n\tUART_WRITE(UART_TX, ch);\n\twhile (((UART_READ(UART_LSR)) & UART_LSR_THRE) == 0);\n}\n\nvoid board_init(void)\n{\n}\n"
  },
  {
    "path": "target/linux/ramips/image/lzma-loader/src/cache.c",
    "content": "/*\n * LZMA compressed kernel loader for Atheros AR7XXX/AR9XXX based boards\n *\n * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>\n *\n * The cache manipulation routine has been taken from the U-Boot project.\n *\t(C) Copyright 2003\n *\tWolfgang Denk, DENX Software Engineering, <wd@denx.de>\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of the GNU General Public License version 2 as published\n * by the Free Software Foundation.\n *\n */\n\n#include \"cache.h\"\n#include \"cacheops.h\"\n#include \"config.h\"\n\n#define cache_op(op,addr)\t\t\t\t\t\t\\\n\t__asm__ __volatile__(\t\t\t\t\t\t\\\n\t\"\t.set\tpush\t\t\t\t\t\\n\"\t\\\n\t\"\t.set\tnoreorder\t\t\t\t\\n\"\t\\\n\t\"\t.set\tmips3\\n\\t\t\t\t\t\\n\"\t\\\n\t\"\tcache\t%0, %1\t\t\t\t\t\\n\"\t\\\n\t\"\t.set\tpop\t\t\t\t\t\\n\"\t\\\n\t:\t\t\t\t\t\t\t\t\\\n\t: \"i\" (op), \"R\" (*(unsigned char *)(addr)))\n\nvoid flush_cache(unsigned long start_addr, unsigned long size)\n{\n\tunsigned long lsize = CONFIG_CACHELINE_SIZE;\n\tunsigned long addr = start_addr & ~(lsize - 1);\n\tunsigned long aend = (start_addr + size - 1) & ~(lsize - 1);\n\n\twhile (1) {\n\t\tcache_op(Hit_Writeback_Inv_D, addr);\n\t\tcache_op(Hit_Invalidate_I, addr);\n\t\tif (addr == aend)\n\t\t\tbreak;\n\t\taddr += lsize;\n\t}\n}\n"
  },
  {
    "path": "target/linux/ramips/image/lzma-loader/src/cache.h",
    "content": "/*\n * LZMA compressed kernel loader for Atheros AR7XXX/AR9XXX based boards\n *\n * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of the GNU General Public License version 2 as published\n * by the Free Software Foundation.\n *\n */\n\n#ifndef __CACHE_H\n#define __CACHE_H\n\nvoid flush_cache(unsigned long start_addr, unsigned long size);\n\n#endif /* __CACHE_H */\n"
  },
  {
    "path": "target/linux/ramips/image/lzma-loader/src/cacheops.h",
    "content": "/*\n * Cache operations for the cache instruction.\n *\n * This file is subject to the terms and conditions of the GNU General Public\n * License.  See the file \"COPYING\" in the main directory of this archive\n * for more details.\n *\n * (C) Copyright 1996, 97, 99, 2002, 03 Ralf Baechle\n * (C) Copyright 1999 Silicon Graphics, Inc.\n */\n#ifndef\t__ASM_CACHEOPS_H\n#define\t__ASM_CACHEOPS_H\n\n/*\n * Cache Operations available on all MIPS processors with R4000-style caches\n */\n#define Index_Invalidate_I      0x00\n#define Index_Writeback_Inv_D   0x01\n#define Index_Load_Tag_I\t0x04\n#define Index_Load_Tag_D\t0x05\n#define Index_Store_Tag_I\t0x08\n#define Index_Store_Tag_D\t0x09\n#if defined(CONFIG_CPU_LOONGSON2)\n#define Hit_Invalidate_I\t0x00\n#else\n#define Hit_Invalidate_I\t0x10\n#endif\n#define Hit_Invalidate_D\t0x11\n#define Hit_Writeback_Inv_D\t0x15\n\n/*\n * R4000-specific cacheops\n */\n#define Create_Dirty_Excl_D\t0x0d\n#define Fill\t\t\t0x14\n#define Hit_Writeback_I\t\t0x18\n#define Hit_Writeback_D\t\t0x19\n\n/*\n * R4000SC and R4400SC-specific cacheops\n */\n#define Index_Invalidate_SI     0x02\n#define Index_Writeback_Inv_SD  0x03\n#define Index_Load_Tag_SI\t0x06\n#define Index_Load_Tag_SD\t0x07\n#define Index_Store_Tag_SI\t0x0A\n#define Index_Store_Tag_SD\t0x0B\n#define Create_Dirty_Excl_SD\t0x0f\n#define Hit_Invalidate_SI\t0x12\n#define Hit_Invalidate_SD\t0x13\n#define Hit_Writeback_Inv_SD\t0x17\n#define Hit_Writeback_SD\t0x1b\n#define Hit_Set_Virtual_SI\t0x1e\n#define Hit_Set_Virtual_SD\t0x1f\n\n/*\n * R5000-specific cacheops\n */\n#define R5K_Page_Invalidate_S\t0x17\n\n/*\n * RM7000-specific cacheops\n */\n#define Page_Invalidate_T\t0x16\n\n/*\n * R10000-specific cacheops\n *\n * Cacheops 0x02, 0x06, 0x0a, 0x0c-0x0e, 0x16, 0x1a and 0x1e are unused.\n * Most of the _S cacheops are identical to the R4000SC _SD cacheops.\n */\n#define Index_Writeback_Inv_S\t0x03\n#define Index_Load_Tag_S\t0x07\n#define Index_Store_Tag_S\t0x0B\n#define Hit_Invalidate_S\t0x13\n#define Cache_Barrier\t\t0x14\n#define Hit_Writeback_Inv_S\t0x17\n#define Index_Load_Data_I\t0x18\n#define Index_Load_Data_D\t0x19\n#define Index_Load_Data_S\t0x1b\n#define Index_Store_Data_I\t0x1c\n#define Index_Store_Data_D\t0x1d\n#define Index_Store_Data_S\t0x1f\n\n#endif\t/* __ASM_CACHEOPS_H */\n"
  },
  {
    "path": "target/linux/ramips/image/lzma-loader/src/config.h",
    "content": "/*\n * LZMA compressed kernel loader for Atheros AR7XXX/AR9XXX based boards\n *\n * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of the GNU General Public License version 2 as published\n * by the Free Software Foundation.\n *\n */\n\n#ifndef _CONFIG_H_\n#define _CONFIG_H_\n\n#ifndef CONFIG_FLASH_OFFS\n#define CONFIG_FLASH_OFFS\t0\n#endif\n\n#ifndef CONFIG_FLASH_MAX\n#define CONFIG_FLASH_MAX\t0\n#endif\n\n#ifndef CONFIG_FLASH_STEP\n#define CONFIG_FLASH_STEP\t0x1000\n#endif\n\n#endif /* _CONFIG_H_ */\n"
  },
  {
    "path": "target/linux/ramips/image/lzma-loader/src/cp0regdef.h",
    "content": "/*\n * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle\n *\n * Copyright (C) 2001, Monta Vista Software\n * Author: jsun@mvista.com or jsun@junsun.net\n */\n#ifndef _cp0regdef_h_\n#define _cp0regdef_h_\n\n#define CP0_INDEX $0\n#define CP0_RANDOM $1\n#define CP0_ENTRYLO0 $2\n#define CP0_ENTRYLO1 $3\n#define CP0_CONTEXT $4\n#define CP0_PAGEMASK $5\n#define CP0_WIRED $6\n#define CP0_BADVADDR $8\n#define CP0_COUNT $9\n#define CP0_ENTRYHI $10\n#define CP0_COMPARE $11\n#define CP0_STATUS $12\n#define CP0_CAUSE $13\n#define CP0_EPC $14\n#define CP0_PRID $15\n#define CP0_CONFIG $16\n#define CP0_LLADDR $17\n#define CP0_WATCHLO $18\n#define CP0_WATCHHI $19\n#define CP0_XCONTEXT $20\n#define CP0_FRAMEMASK $21\n#define CP0_DIAGNOSTIC $22\n#define CP0_PERFORMANCE $25\n#define CP0_ECC $26\n#define CP0_CACHEERR $27\n#define CP0_TAGLO $28\n#define CP0_TAGHI $29\n#define CP0_ERROREPC $30\n\n#endif\n"
  },
  {
    "path": "target/linux/ramips/image/lzma-loader/src/head.S",
    "content": "/*\n * LZMA compressed kernel loader for Atheros AR7XXX/AR9XXX based boards\n *\n * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>\n *\n * Some parts of this code was based on the OpenWrt specific lzma-loader\n * for the BCM47xx and ADM5120 based boards:\n *\tCopyright (C) 2004 Manuel Novoa III (mjn3@codepoet.org)\n *\tCopyright (C) 2005 by Oleg I. Vdovikin <oleg@cs.msu.su>\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of the GNU General Public License version 2 as published\n * by the Free Software Foundation.\n */\n\n#include <asm/asm.h>\n#include <asm/regdef.h>\n#include \"cp0regdef.h\"\n#include \"cacheops.h\"\n#include \"config.h\"\n\n#define KSEG0\t\t0x80000000\n\n\t.macro\tehb\n\tsll     zero, 3\n\t.endm\n\n\t.text\n\nLEAF(startup)\n\t.set noreorder\n\t.set mips32\n\n\tmtc0\tzero, CP0_WATCHLO\t# clear watch registers\n\tmtc0\tzero, CP0_WATCHHI\n\tmtc0\tzero, CP0_CAUSE\t\t# clear before writing status register\n\n\tmfc0\tt0, CP0_STATUS\n\tli\tt1, 0x1000001f\n\tor\tt0, t1\n\txori\tt0, 0x1f\n\tmtc0\tt0, CP0_STATUS\n\tehb\n\n\tmtc0\tzero, CP0_COUNT\n\tmtc0\tzero, CP0_COMPARE\n\tehb\n\n\tla\tt0, __reloc_label\t# get linked address of label\n\tbal\t__reloc_label\t\t# branch and link to label to\n\tnop\t\t\t\t# get actual address\n__reloc_label:\n\tsubu\tt0, ra, t0\t\t# get reloc_delta\n\n\tbeqz\tt0, __reloc_done         # if delta is 0 we are in the right place\n\tnop\n\n\t/* Copy our code to the right place */\n\tla\tt1, _code_start\t\t# get linked address of _code_start\n\tla\tt2, _code_end\t\t# get linked address of _code_end\n\taddu\tt0, t0, t1\t\t# calculate actual address of _code_start\n\n__reloc_copy:\n\tlw\tt3, 0(t0)\n\tsw\tt3, 0(t1)\n\tadd\tt1, 4\n\tblt\tt1, t2, __reloc_copy\n\tadd\tt0, 4\n\n\t/* flush cache */\n\tla\tt0, _code_start\n\tla\tt1, _code_end\n\n\tli\tt2, ~(CONFIG_CACHELINE_SIZE - 1)\n\tand\tt0, t2\n\tand\tt1, t2\n\tli\tt2, CONFIG_CACHELINE_SIZE\n\n\tb\t__flush_check\n\tnop\n\n__flush_line:\n\tcache\tHit_Writeback_Inv_D, 0(t0)\n\tcache\tHit_Invalidate_I, 0(t0)\n\tadd\tt0, t2\n\n__flush_check:\n\tbne\tt0, t1, __flush_line\n\tnop\n\n\tsync\n\n__reloc_done:\n\n\t/* clear bss */\n\tla\tt0, _bss_start\n\tla\tt1, _bss_end\n\tb\t__bss_check\n\tnop\n\n__bss_fill:\n\tsw\tzero, 0(t0)\n\taddi\tt0, 4\n\n__bss_check:\n\tbne\tt0, t1, __bss_fill\n\tnop\n\n\t/* Setup new \"C\" stack */\n\tla\tsp, _stack\n\n\t/* reserve stack space for a0-a3 registers */\n\tsubu\tsp, 16\n\n\t/* jump to the decompressor routine */\n\tla\tt0, loader_main\n\tjr\tt0\n\tnop\n\n\t.set reorder\nEND(startup)\n"
  },
  {
    "path": "target/linux/ramips/image/lzma-loader/src/lantiq.mk",
    "content": "CACHE_FLAGS+=-DCONFIG_ICACHE_SIZE=\"(32 * 1024)\" -DCONFIG_DCACHE_SIZE=\"(32 * 1024)\" -DCONFIG_CACHELINE_SIZE=32\n"
  },
  {
    "path": "target/linux/ramips/image/lzma-loader/src/loader.c",
    "content": "/*\n * LZMA compressed kernel loader for Atheros AR7XXX/AR9XXX based boards\n *\n * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>\n *\n * Some parts of this code was based on the OpenWrt specific lzma-loader\n * for the BCM47xx and ADM5120 based boards:\n *\tCopyright (C) 2004 Manuel Novoa III (mjn3@codepoet.org)\n *\tCopyright (C) 2005 Mineharu Takahara <mtakahar@yahoo.com>\n *\tCopyright (C) 2005 by Oleg I. Vdovikin <oleg@cs.msu.su>\n *\n * The image_header structure has been taken from the U-Boot project.\n *\t(C) Copyright 2008 Semihalf\n *\t(C) Copyright 2000-2005\n *\tWolfgang Denk, DENX Software Engineering, wd@denx.de.\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of the GNU General Public License version 2 as published\n * by the Free Software Foundation.\n */\n\n#include <stddef.h>\n#include <stdint.h>\n#include <sys/types.h>\n\n#include \"config.h\"\n#include \"cache.h\"\n#include \"printf.h\"\n#include \"LzmaDecode.h\"\n\n#define KSEG0\t\t\t0x80000000\n#define KSEG1\t\t\t0xa0000000\n\n#define KSEG1ADDR(a)\t\t((((unsigned)(a)) & 0x1fffffffU) | KSEG1)\n\n#undef LZMA_DEBUG\n\n#ifdef LZMA_DEBUG\n#  define DBG(f, a...)\tprintf(f, ## a)\n#else\n#  define DBG(f, a...)\tdo {} while (0)\n#endif\n\n#define IH_MAGIC_OKLI\t\t0x4f4b4c49\t/* 'OKLI' */\n\n#define IH_NMLEN\t\t32\t/* Image Name Length\t\t*/\n\ntypedef struct image_header {\n\tuint32_t\tih_magic;\t/* Image Header Magic Number\t*/\n\tuint32_t\tih_hcrc;\t/* Image Header CRC Checksum\t*/\n\tuint32_t\tih_time;\t/* Image Creation Timestamp\t*/\n\tuint32_t\tih_size;\t/* Image Data Size\t\t*/\n\tuint32_t\tih_load;\t/* Data\t Load  Address\t\t*/\n\tuint32_t\tih_ep;\t\t/* Entry Point Address\t\t*/\n\tuint32_t\tih_dcrc;\t/* Image Data CRC Checksum\t*/\n\tuint8_t\t\tih_os;\t\t/* Operating System\t\t*/\n\tuint8_t\t\tih_arch;\t/* CPU architecture\t\t*/\n\tuint8_t\t\tih_type;\t/* Image Type\t\t\t*/\n\tuint8_t\t\tih_comp;\t/* Compression Type\t\t*/\n\tuint8_t\t\tih_name[IH_NMLEN];\t/* Image Name\t\t*/\n} image_header_t;\n\n/* beyond the image end, size not known in advance */\nextern unsigned char workspace[];\nextern void board_init(void);\n\nstatic CLzmaDecoderState lzma_state;\nstatic unsigned char *lzma_data;\nstatic unsigned long lzma_datasize;\nstatic unsigned long lzma_outsize;\nstatic unsigned long kernel_la;\n\n#ifdef CONFIG_KERNEL_CMDLINE\n#define kernel_argc\t2\nstatic const char kernel_cmdline[] = CONFIG_KERNEL_CMDLINE;\nstatic const char *kernel_argv[] = {\n\tNULL,\n\tkernel_cmdline,\n\tNULL,\n};\n#endif /* CONFIG_KERNEL_CMDLINE */\n\nstatic void halt(void)\n{\n\tprintf(\"\\nSystem halted!\\n\");\n\tfor(;;);\n}\n\nstatic __inline__ unsigned long get_be32(void *buf)\n{\n\tunsigned char *p = buf;\n\n\treturn (((unsigned long) p[0] << 24) +\n\t        ((unsigned long) p[1] << 16) +\n\t        ((unsigned long) p[2] << 8) +\n\t        (unsigned long) p[3]);\n}\n\nstatic __inline__ unsigned char lzma_get_byte(void)\n{\n\tunsigned char c;\n\n\tlzma_datasize--;\n\tc = *lzma_data++;\n\n\treturn c;\n}\n\nstatic int lzma_init_props(void)\n{\n\tunsigned char props[LZMA_PROPERTIES_SIZE];\n\tint res;\n\tint i;\n\n\t/* read lzma properties */\n\tfor (i = 0; i < LZMA_PROPERTIES_SIZE; i++)\n\t\tprops[i] = lzma_get_byte();\n\n\t/* read the lower half of uncompressed size in the header */\n\tlzma_outsize = ((SizeT) lzma_get_byte()) +\n\t\t       ((SizeT) lzma_get_byte() << 8) +\n\t\t       ((SizeT) lzma_get_byte() << 16) +\n\t\t       ((SizeT) lzma_get_byte() << 24);\n\n\t/* skip rest of the header (upper half of uncompressed size) */\n\tfor (i = 0; i < 4; i++)\n\t\tlzma_get_byte();\n\n\tres = LzmaDecodeProperties(&lzma_state.Properties, props,\n\t\t\t\t\tLZMA_PROPERTIES_SIZE);\n\treturn res;\n}\n\nstatic int lzma_decompress(unsigned char *outStream)\n{\n\tSizeT ip, op;\n\tint ret;\n\n\tlzma_state.Probs = (CProb *) workspace;\n\n\tret = LzmaDecode(&lzma_state, lzma_data, lzma_datasize, &ip, outStream,\n\t\t\t lzma_outsize, &op);\n\n\tif (ret != LZMA_RESULT_OK) {\n\t\tint i;\n\n\t\tDBG(\"LzmaDecode error %d at %08x, osize:%d ip:%d op:%d\\n\",\n\t\t    ret, lzma_data + ip, lzma_outsize, ip, op);\n\n\t\tfor (i = 0; i < 16; i++)\n\t\t\tDBG(\"%02x \", lzma_data[ip + i]);\n\n\t\tDBG(\"\\n\");\n\t}\n\n\treturn ret;\n}\n\n#if (LZMA_WRAPPER)\nstatic void lzma_init_data(void)\n{\n\textern unsigned char _lzma_data_start[];\n\textern unsigned char _lzma_data_end[];\n\n\tkernel_la = LOADADDR;\n\tlzma_data = _lzma_data_start;\n\tlzma_datasize = _lzma_data_end - _lzma_data_start;\n}\n#else\nstatic void lzma_init_data(void)\n{\n\tstruct image_header *hdr = NULL;\n\tunsigned char *flash_base;\n\tunsigned long flash_ofs;\n\tunsigned long kernel_ofs;\n\tunsigned long kernel_size;\n\n\tflash_base = (unsigned char *) KSEG1ADDR(CONFIG_FLASH_START);\n\n\tprintf(\"Looking for OpenWrt image... \");\n\n\tfor (flash_ofs = CONFIG_FLASH_OFFS;\n\t     flash_ofs <= (CONFIG_FLASH_OFFS + CONFIG_FLASH_MAX);\n\t     flash_ofs += CONFIG_FLASH_STEP) {\n\t\tunsigned long magic;\n\t\tunsigned char *p;\n\n\t\tp = flash_base + flash_ofs;\n\t\tmagic = get_be32(p);\n\t\tif (magic == IH_MAGIC_OKLI) {\n\t\t\thdr = (struct image_header *) p;\n\t\t\tbreak;\n\t\t}\n\t}\n\n\tif (hdr == NULL) {\n\t\tprintf(\"not found!\\n\");\n\t\thalt();\n\t}\n\n\tprintf(\"found at 0x%08x\\n\", flash_base + flash_ofs);\n\n\tkernel_ofs = sizeof(struct image_header);\n\tkernel_size = get_be32(&hdr->ih_size);\n\tkernel_la = get_be32(&hdr->ih_load);\n\n\tlzma_data = flash_base + flash_ofs + kernel_ofs;\n\tlzma_datasize = kernel_size;\n}\n#endif /* (LZMA_WRAPPER) */\n\nvoid loader_main(unsigned long reg_a0, unsigned long reg_a1,\n\t\t unsigned long reg_a2, unsigned long reg_a3)\n{\n\tvoid (*kernel_entry) (unsigned long, unsigned long, unsigned long,\n\t\t\t      unsigned long);\n\tint res;\n\n\tboard_init();\n\n\tprintf(\"\\n\\nOpenWrt kernel loader for MIPS based SoC\\n\");\n\tprintf(\"Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>\\n\");\n\n\tlzma_init_data();\n\n\tres = lzma_init_props();\n\tif (res != LZMA_RESULT_OK) {\n\t\tprintf(\"Incorrect LZMA stream properties!\\n\");\n\t\thalt();\n\t}\n\n\tprintf(\"Decompressing kernel... \");\n\n\tres = lzma_decompress((unsigned char *) kernel_la);\n\tif (res != LZMA_RESULT_OK) {\n\t\tprintf(\"failed, \");\n\t\tswitch (res) {\n\t\tcase LZMA_RESULT_DATA_ERROR:\n\t\t\tprintf(\"data error!\\n\");\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tprintf(\"unknown error %d!\\n\", res);\n\t\t}\n\t\thalt();\n\t} else {\n\t\tprintf(\"done!\\n\");\n\t}\n\n\tflush_cache(kernel_la, lzma_outsize);\n\n\tprintf(\"Starting kernel at %08x...\\n\\n\", kernel_la);\n\n#ifdef CONFIG_KERNEL_CMDLINE\n\treg_a0 = kernel_argc;\n\treg_a1 = (unsigned long) kernel_argv;\n\treg_a2 = 0;\n\treg_a3 = 0;\n#endif\n\n\tkernel_entry = (void *) kernel_la;\n\tkernel_entry(reg_a0, reg_a1, reg_a2, reg_a3);\n}\n"
  },
  {
    "path": "target/linux/ramips/image/lzma-loader/src/loader.lds",
    "content": "OUTPUT_ARCH(mips)\nSECTIONS {\n\t.text : {\n\t\t_code_start = .;\n\t\t*(.text)\n\t\t*(.text.*)\n\t\t*(.rodata)\n\t\t*(.rodata.*)\n\t\t*(.data.lzma)\n\t}\n\n\t. = ALIGN(32);\n\t.data : {\n\t\t*(.data)\n\t\t*(.data.*)\n\t\t. = . + 524288;\t\t/* workaround for buggy bootloaders */\n\t}\n\n\t. = ALIGN(32);\n\t_code_end = .;\n\n\t_bss_start = .;\n\t.bss : {\n\t\t*(.bss)\n\t\t*(.bss.*)\n\t}\n\n\t. = ALIGN(32);\n\t_bss_end = .;\n\n\t. = . + 8192;\n\t_stack = .;\n\n\tworkspace = .;\n}\n"
  },
  {
    "path": "target/linux/ramips/image/lzma-loader/src/loader2.lds",
    "content": "OUTPUT_ARCH(mips)\nSECTIONS {\n\t.text : {\n\t\tstartup = .;\n\t\t*(.text)\n\t\t*(.text.*)\n\t\t*(.data)\n\t\t*(.data.*)\n\t}\n}\n"
  },
  {
    "path": "target/linux/ramips/image/lzma-loader/src/lzma-data.lds",
    "content": "OUTPUT_ARCH(mips)\nSECTIONS {\n\t.data.lzma : {\n\t\t_lzma_data_start = .;\n\t\t*(.data)\n\t\t_lzma_data_end = .;\n\t}\n}\n"
  },
  {
    "path": "target/linux/ramips/image/lzma-loader/src/mt7621.mk",
    "content": "CACHE_FLAGS+=-DCONFIG_ICACHE_SIZE=\"(32 * 1024)\" -DCONFIG_DCACHE_SIZE=\"(16 * 1024)\" -DCONFIG_CACHELINE_SIZE=32\n"
  },
  {
    "path": "target/linux/ramips/image/lzma-loader/src/printf.c",
    "content": "/*\n * Copyright (C) 2001 MontaVista Software Inc.\n * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net\n *\n * This program is free software; you can redistribute  it and/or modify it\n * under  the terms of  the GNU General  Public License as published by the\n * Free Software Foundation;  either version 2 of the  License, or (at your\n * option) any later version.\n *\n */\n\n#include\t\"printf.h\"\n\nextern void board_putc(int ch);\n\n/* this is the maximum width for a variable */\n#define\t\tLP_MAX_BUF\t256\n\n/* macros */\n#define\t\tIsDigit(x)\t( ((x) >= '0') && ((x) <= '9') )\n#define\t\tCtod(x)\t\t( (x) - '0')\n\n/* forward declaration */\nstatic int PrintChar(char *, char, int, int);\nstatic int PrintString(char *, char *, int, int);\nstatic int PrintNum(char *, unsigned long, int, int, int, int, char, int);\n\n/* private variable */\nstatic const char theFatalMsg[] = \"fatal error in lp_Print!\";\n\n/* -*-\n * A low level printf() function.\n */\nstatic void\nlp_Print(void (*output)(void *, char *, int),\n\t void * arg,\n\t char *fmt,\n\t va_list ap)\n{\n\n#define \tOUTPUT(arg, s, l)  \\\n  { if (((l) < 0) || ((l) > LP_MAX_BUF)) { \\\n       (*output)(arg, (char*)theFatalMsg, sizeof(theFatalMsg)-1); for(;;); \\\n    } else { \\\n      (*output)(arg, s, l); \\\n    } \\\n  }\n\n    char buf[LP_MAX_BUF];\n\n    char c;\n    char *s;\n    long int num;\n\n    int longFlag;\n    int negFlag;\n    int width;\n    int prec;\n    int ladjust;\n    char padc;\n\n    int length;\n\n    for(;;) {\n\t{\n\t    /* scan for the next '%' */\n\t    char *fmtStart = fmt;\n\t    while ( (*fmt != '\\0') && (*fmt != '%')) {\n\t\tfmt ++;\n\t    }\n\n\t    /* flush the string found so far */\n\t    OUTPUT(arg, fmtStart, fmt-fmtStart);\n\n\t    /* are we hitting the end? */\n\t    if (*fmt == '\\0') break;\n\t}\n\n\t/* we found a '%' */\n\tfmt ++;\n\n\t/* check for long */\n\tif (*fmt == 'l') {\n\t    longFlag = 1;\n\t    fmt ++;\n\t} else {\n\t    longFlag = 0;\n\t}\n\n\t/* check for other prefixes */\n\twidth = 0;\n\tprec = -1;\n\tladjust = 0;\n\tpadc = ' ';\n\n\tif (*fmt == '-') {\n\t    ladjust = 1;\n\t    fmt ++;\n\t}\n\n\tif (*fmt == '0') {\n\t    padc = '0';\n\t    fmt++;\n\t}\n\n\tif (IsDigit(*fmt)) {\n\t    while (IsDigit(*fmt)) {\n\t\twidth = 10 * width + Ctod(*fmt++);\n\t    }\n\t}\n\n\tif (*fmt == '.') {\n\t    fmt ++;\n\t    if (IsDigit(*fmt)) {\n\t\tprec = 0;\n\t\twhile (IsDigit(*fmt)) {\n\t\t    prec = prec*10 + Ctod(*fmt++);\n\t\t}\n\t    }\n\t}\n\n\n\t/* check format flag */\n\tnegFlag = 0;\n\tswitch (*fmt) {\n\t case 'b':\n\t    if (longFlag) {\n\t\tnum = va_arg(ap, long int);\n\t    } else {\n\t\tnum = va_arg(ap, int);\n\t    }\n\t    length = PrintNum(buf, num, 2, 0, width, ladjust, padc, 0);\n\t    OUTPUT(arg, buf, length);\n\t    break;\n\n\t case 'd':\n\t case 'D':\n\t    if (longFlag) {\n\t\tnum = va_arg(ap, long int);\n\t    } else {\n\t\tnum = va_arg(ap, int);\n\t    }\n\t    if (num < 0) {\n\t\tnum = - num;\n\t\tnegFlag = 1;\n\t    }\n\t    length = PrintNum(buf, num, 10, negFlag, width, ladjust, padc, 0);\n\t    OUTPUT(arg, buf, length);\n\t    break;\n\n\t case 'o':\n\t case 'O':\n\t    if (longFlag) {\n\t\tnum = va_arg(ap, long int);\n\t    } else {\n\t\tnum = va_arg(ap, int);\n\t    }\n\t    length = PrintNum(buf, num, 8, 0, width, ladjust, padc, 0);\n\t    OUTPUT(arg, buf, length);\n\t    break;\n\n\t case 'u':\n\t case 'U':\n\t    if (longFlag) {\n\t\tnum = va_arg(ap, long int);\n\t    } else {\n\t\tnum = va_arg(ap, int);\n\t    }\n\t    length = PrintNum(buf, num, 10, 0, width, ladjust, padc, 0);\n\t    OUTPUT(arg, buf, length);\n\t    break;\n\n\t case 'x':\n\t    if (longFlag) {\n\t\tnum = va_arg(ap, long int);\n\t    } else {\n\t\tnum = va_arg(ap, int);\n\t    }\n\t    length = PrintNum(buf, num, 16, 0, width, ladjust, padc, 0);\n\t    OUTPUT(arg, buf, length);\n\t    break;\n\n\t case 'X':\n\t    if (longFlag) {\n\t\tnum = va_arg(ap, long int);\n\t    } else {\n\t\tnum = va_arg(ap, int);\n\t    }\n\t    length = PrintNum(buf, num, 16, 0, width, ladjust, padc, 1);\n\t    OUTPUT(arg, buf, length);\n\t    break;\n\n\t case 'c':\n\t    c = (char)va_arg(ap, int);\n\t    length = PrintChar(buf, c, width, ladjust);\n\t    OUTPUT(arg, buf, length);\n\t    break;\n\n\t case 's':\n\t    s = (char*)va_arg(ap, char *);\n\t    length = PrintString(buf, s, width, ladjust);\n\t    OUTPUT(arg, buf, length);\n\t    break;\n\n\t case '\\0':\n\t    fmt --;\n\t    break;\n\n\t default:\n\t    /* output this char as it is */\n\t    OUTPUT(arg, fmt, 1);\n\t}\t/* switch (*fmt) */\n\n\tfmt ++;\n    }\t\t/* for(;;) */\n\n    /* special termination call */\n    OUTPUT(arg, \"\\0\", 1);\n}\n\n\n/* --------------- local help functions --------------------- */\nstatic int\nPrintChar(char * buf, char c, int length, int ladjust)\n{\n    int i;\n\n    if (length < 1) length = 1;\n    if (ladjust) {\n\t*buf = c;\n\tfor (i=1; i< length; i++) buf[i] = ' ';\n    } else {\n\tfor (i=0; i< length-1; i++) buf[i] = ' ';\n\tbuf[length - 1] = c;\n    }\n    return length;\n}\n\nstatic int\nPrintString(char * buf, char* s, int length, int ladjust)\n{\n    int i;\n    int len=0;\n    char* s1 = s;\n    while (*s1++) len++;\n    if (length < len) length = len;\n\n    if (ladjust) {\n\tfor (i=0; i< len; i++) buf[i] = s[i];\n\tfor (i=len; i< length; i++) buf[i] = ' ';\n    } else {\n\tfor (i=0; i< length-len; i++) buf[i] = ' ';\n\tfor (i=length-len; i < length; i++) buf[i] = s[i-length+len];\n    }\n    return length;\n}\n\nstatic int\nPrintNum(char * buf, unsigned long u, int base, int negFlag,\n\t int length, int ladjust, char padc, int upcase)\n{\n    /* algorithm :\n     *  1. prints the number from left to right in reverse form.\n     *  2. fill the remaining spaces with padc if length is longer than\n     *     the actual length\n     *     TRICKY : if left adjusted, no \"0\" padding.\n     *\t\t    if negtive, insert  \"0\" padding between \"0\" and number.\n     *  3. if (!ladjust) we reverse the whole string including paddings\n     *  4. otherwise we only reverse the actual string representing the num.\n     */\n\n    int actualLength =0;\n    char *p = buf;\n    int i;\n\n    do {\n\tint tmp = u %base;\n\tif (tmp <= 9) {\n\t    *p++ = '0' + tmp;\n\t} else if (upcase) {\n\t    *p++ = 'A' + tmp - 10;\n\t} else {\n\t    *p++ = 'a' + tmp - 10;\n\t}\n\tu /= base;\n    } while (u != 0);\n\n    if (negFlag) {\n\t*p++ = '-';\n    }\n\n    /* figure out actual length and adjust the maximum length */\n    actualLength = p - buf;\n    if (length < actualLength) length = actualLength;\n\n    /* add padding */\n    if (ladjust) {\n\tpadc = ' ';\n    }\n    if (negFlag && !ladjust && (padc == '0')) {\n\tfor (i = actualLength-1; i< length-1; i++) buf[i] = padc;\n\tbuf[length -1] = '-';\n    } else {\n\tfor (i = actualLength; i< length; i++) buf[i] = padc;\n    }\n\n\n    /* prepare to reverse the string */\n    {\n\tint begin = 0;\n\tint end;\n\tif (ladjust) {\n\t    end = actualLength - 1;\n\t} else {\n\t    end = length -1;\n\t}\n\n\twhile (end > begin) {\n\t    char tmp = buf[begin];\n\t    buf[begin] = buf[end];\n\t    buf[end] = tmp;\n\t    begin ++;\n\t    end --;\n\t}\n    }\n\n    /* adjust the string pointer */\n    return length;\n}\n\nstatic void printf_output(void *arg, char *s, int l)\n{\n    int i;\n\n    // special termination call\n    if ((l==1) && (s[0] == '\\0')) return;\n\n    for (i=0; i< l; i++) {\n\tboard_putc(s[i]);\n\tif (s[i] == '\\n') board_putc('\\r');\n    }\n}\n\nvoid printf(char *fmt, ...)\n{\n    va_list ap;\n    va_start(ap, fmt);\n    lp_Print(printf_output, 0, fmt, ap);\n    va_end(ap);\n}\n"
  },
  {
    "path": "target/linux/ramips/image/lzma-loader/src/printf.h",
    "content": "/*\n * Copyright (C) 2001 MontaVista Software Inc.\n * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net\n *\n * This program is free software; you can redistribute  it and/or modify it\n * under  the terms of  the GNU General  Public License as published by the\n * Free Software Foundation;  either version 2 of the  License, or (at your\n * option) any later version.\n *\n */\n\n#ifndef _printf_h_\n#define _printf_h_\n\n#include <stdarg.h>\nvoid printf(char *fmt, ...);\n\n#endif /* _printf_h_ */\n"
  },
  {
    "path": "target/linux/ramips/image/lzma-loader/src/ralink.mk",
    "content": "CACHE_FLAGS+=-DCONFIG_ICACHE_SIZE=\"(32 * 1024)\" -DCONFIG_DCACHE_SIZE=\"(16 * 1024)\" -DCONFIG_CACHELINE_SIZE=32\n"
  },
  {
    "path": "target/linux/ramips/image/mt7620.mk",
    "content": "#\n# MT7620A Profiles\n#\n\ninclude ./common-tp-link.mk\n\nDEVICE_VARS += DLINK_ROM_ID DLINK_FAMILY_MEMBER DLINK_FIRMWARE_SIZE DLINK_IMAGE_OFFSET\n\ndefine Build/elecom-header\n\tcp $@ $(KDIR)/v_0.0.0.bin\n\t( \\\n\t\t$(MKHASH) md5 $(KDIR)/v_0.0.0.bin && \\\n\t\techo 458 \\\n\t) | $(MKHASH) md5 > $(KDIR)/v_0.0.0.md5\n\t$(STAGING_DIR_HOST)/bin/tar -c \\\n\t\t$(if $(SOURCE_DATE_EPOCH),--mtime=@$(SOURCE_DATE_EPOCH)) \\\n\t\t--owner=0 --group=0 -f $@ -C $(KDIR) v_0.0.0.bin v_0.0.0.md5\nendef\n\ndefine Device/aigale_ai-br100\n  SOC := mt7620a\n  IMAGE_SIZE := 7936k\n  DEVICE_VENDOR := Aigale\n  DEVICE_MODEL := Ai-BR100\n  DEVICE_PACKAGES:= kmod-usb2 kmod-usb-ohci\n  SUPPORTED_DEVICES += ai-br100\nendef\nTARGET_DEVICES += aigale_ai-br100\n\ndefine Device/alfa-network_ac1200rm\n  SOC := mt7620a\n  IMAGE_SIZE := 16064k\n  DEVICE_VENDOR := ALFA Network\n  DEVICE_MODEL := AC1200RM\n  DEVICE_PACKAGES := kmod-mt76x2 kmod-usb2 kmod-usb-ohci uboot-envtools\n  SUPPORTED_DEVICES += ac1200rm\nendef\nTARGET_DEVICES += alfa-network_ac1200rm\n\ndefine Device/alfa-network_r36m-e4g\n  SOC := mt7620a\n  IMAGE_SIZE := 16064k\n  DEVICE_VENDOR := ALFA Network\n  DEVICE_MODEL := R36M-E4G\n  DEVICE_PACKAGES := kmod-i2c-ralink kmod-usb2 kmod-usb-ohci uboot-envtools \\\n\tuqmi\n  SUPPORTED_DEVICES += r36m-e4g\nendef\nTARGET_DEVICES += alfa-network_r36m-e4g\n\ndefine Device/alfa-network_tube-e4g\n  SOC := mt7620a\n  IMAGE_SIZE := 16064k\n  DEVICE_VENDOR := ALFA Network\n  DEVICE_MODEL := Tube-E4G\n  DEVICE_PACKAGES := kmod-usb2 kmod-usb-ohci uboot-envtools uqmi -iwinfo \\\n\t-kmod-rt2800-soc -wpad-basic-wolfssl\n  SUPPORTED_DEVICES += tube-e4g\nendef\nTARGET_DEVICES += alfa-network_tube-e4g\n\ndefine Device/amit_jboot\n  DLINK_IMAGE_OFFSET := 0x10000\n  KERNEL := $(KERNEL_DTB) | uImage lzma -M 0x4f4b4c49\n  LOADER_FLASH_OFFS := 0x20000\n  LOADER_TYPE := bin\n  COMPILE := loader-$(1).bin\n  COMPILE/loader-$(1).bin := loader-okli-compile | pad-to 64k | lzma | \\\n\tpad-to 65480\n  IMAGES += factory.bin\n  IMAGE/sysupgrade.bin := append-kernel | append-rootfs | mkdlinkfw-loader | \\\n\tpad-rootfs | append-metadata\n  IMAGE/factory.bin := append-kernel | append-rootfs | mkdlinkfw-loader | \\\n\tpad-rootfs | mkdlinkfw-factory\n  DEVICE_PACKAGES := jboot-tools kmod-usb2 kmod-usb-ohci\nendef\n\ndefine Device/asus_rp-n53\n  SOC := mt7620a\n  IMAGE_SIZE := 7872k\n  DEVICE_VENDOR := Asus\n  DEVICE_MODEL := RP-N53\n  DEVICE_PACKAGES := kmod-rt2800-pci\n  SUPPORTED_DEVICES += rp-n53\nendef\nTARGET_DEVICES += asus_rp-n53\n\ndefine Device/asus_rt-ac51u\n  SOC := mt7620a\n  IMAGE_SIZE := 16064k\n  DEVICE_VENDOR := Asus\n  DEVICE_MODEL := RT-AC51U\n  DEVICE_PACKAGES := kmod-mt76x0e kmod-usb2 kmod-usb-ohci \\\n\tkmod-usb-ledtrig-usbport\n  SUPPORTED_DEVICES += rt-ac51u\nendef\nTARGET_DEVICES += asus_rt-ac51u\n\ndefine Device/asus_rt-ac54u\n  SOC := mt7620a\n  IMAGE_SIZE := 16064k\n  DEVICE_VENDOR := Asus\n  DEVICE_MODEL := RT-AC54U\n  DEVICE_PACKAGES := kmod-mt76x2 kmod-usb2 kmod-usb-ohci \\\n\tkmod-usb-ledtrig-usbport\nendef\nTARGET_DEVICES += asus_rt-ac54u\n\ndefine Device/asus_rt-n12p\n  SOC := mt7620n\n  IMAGE_SIZE := 16064k\n  DEVICE_VENDOR := Asus\n  DEVICE_MODEL := RT-N11P/RT-N12+/RT-N12Eb1\n  SUPPORTED_DEVICES += rt-n12p\nendef\nTARGET_DEVICES += asus_rt-n12p\n\ndefine Device/asus_rt-n14u\n  SOC := mt7620n\n  IMAGE_SIZE := 16064k\n  DEVICE_VENDOR := Asus\n  DEVICE_MODEL := RT-N14u\n  DEVICE_PACKAGES := kmod-usb2 kmod-usb-ohci\n  SUPPORTED_DEVICES += rt-n14u\nendef\nTARGET_DEVICES += asus_rt-n14u\n\ndefine Device/bdcom_wap2100-sk\n  SOC := mt7620a\n  IMAGE_SIZE := 15808k\n  DEVICE_VENDOR := BDCOM\n  DEVICE_MODEL := WAP2100-SK (ZTE ZXECS EBG3130)\n  DEVICE_PACKAGES := kmod-usb2 kmod-usb-ohci kmod-mt76x2 kmod-mt76x0e \\\n\tkmod-sdhci-mt7620 kmod-usb-ledtrig-usbport\nendef\nTARGET_DEVICES += bdcom_wap2100-sk\n\ndefine Device/buffalo_whr-1166d\n  SOC := mt7620a\n  IMAGE_SIZE := 16064k\n  DEVICE_VENDOR := Buffalo\n  DEVICE_MODEL := WHR-1166D\n  DEVICE_PACKAGES := kmod-mt76x2\n  SUPPORTED_DEVICES += whr-1166d\nendef\nTARGET_DEVICES += buffalo_whr-1166d\n\ndefine Device/buffalo_whr-300hp2\n  SOC := mt7620a\n  IMAGE_SIZE := 7872k\n  DEVICE_VENDOR := Buffalo\n  DEVICE_MODEL := WHR-300HP2\n  SUPPORTED_DEVICES += whr-300hp2\nendef\nTARGET_DEVICES += buffalo_whr-300hp2\n\ndefine Device/buffalo_whr-600d\n  SOC := mt7620a\n  IMAGE_SIZE := 7872k\n  DEVICE_VENDOR := Buffalo\n  DEVICE_MODEL := WHR-600D\n  DEVICE_PACKAGES := kmod-rt2800-pci\n  SUPPORTED_DEVICES += whr-600d\nendef\nTARGET_DEVICES += buffalo_whr-600d\n\ndefine Device/buffalo_wmr-300\n  SOC := mt7620n\n  IMAGE_SIZE := 7872k\n  DEVICE_VENDOR := Buffalo\n  DEVICE_MODEL := WMR-300\n  SUPPORTED_DEVICES += wmr-300\nendef\nTARGET_DEVICES += buffalo_wmr-300\n\ndefine Device/comfast_cf-wr800n\n  SOC := mt7620n\n  IMAGE_SIZE := 7872k\n  DEVICE_VENDOR := Comfast\n  DEVICE_MODEL := CF-WR800N\n  SUPPORTED_DEVICES += cf-wr800n\nendef\nTARGET_DEVICES += comfast_cf-wr800n\n\ndefine Device/dlink_dch-m225\n  $(Device/seama)\n  SOC := mt7620a\n  BLOCKSIZE := 4k\n  SEAMA_SIGNATURE := wapn22_dlink.2013gui_dap1320b\n  IMAGE_SIZE := 6848k\n  DEVICE_VENDOR := D-Link\n  DEVICE_MODEL := DCH-M225\n  DEVICE_PACKAGES := kmod-sound-core kmod-sound-mt7620 kmod-i2c-ralink\n  SUPPORTED_DEVICES += dch-m225\nendef\nTARGET_DEVICES += dlink_dch-m225\n\ndefine Device/dlink_dir-510l\n  $(Device/amit_jboot)\n  SOC := mt7620a\n  IMAGE_SIZE := 14208k\n  LOADER_FLASH_OFFS := 0x220000\n  DEVICE_VENDOR := D-Link\n  DEVICE_MODEL := DIR-510L\n  DEVICE_PACKAGES += kmod-mt76x0e\n  DLINK_ROM_ID := DLK6E3805001\n  DLINK_FAMILY_MEMBER := 0x6E38\n  DLINK_FIRMWARE_SIZE := 0xDE0000\n  DLINK_IMAGE_OFFSET := 0x210000\nendef\nTARGET_DEVICES += dlink_dir-510l\n\ndefine Device/dlink_dir-810l\n  SOC := mt7620a\n  DEVICE_PACKAGES := kmod-mt76x0e\n  DEVICE_VENDOR := D-Link\n  DEVICE_MODEL := DIR-810L\n  IMAGE_SIZE := 6720k\n  SUPPORTED_DEVICES += dir-810l\nendef\nTARGET_DEVICES += dlink_dir-810l\n\ndefine Device/dlink_dwr-116-a1\n  $(Device/amit_jboot)\n  SOC := mt7620n\n  IMAGE_SIZE := 8064k\n  DEVICE_VENDOR := D-Link\n  DEVICE_MODEL := DWR-116\n  DEVICE_VARIANT := A1/A2\n  DLINK_ROM_ID := DLK6E3803001\n  DLINK_FAMILY_MEMBER := 0x6E38\n  DLINK_FIRMWARE_SIZE := 0x7E0000\nendef\nTARGET_DEVICES += dlink_dwr-116-a1\n\ndefine Device/dlink_dwr-118-a1\n  $(Device/amit_jboot)\n  SOC := mt7620a\n  IMAGE_SIZE := 16256k\n  DEVICE_VENDOR := D-Link\n  DEVICE_MODEL := DWR-118\n  DEVICE_VARIANT := A1\n  DEVICE_PACKAGES += kmod-mt76x0e\n  DLINK_ROM_ID := DLK6E3811001\n  DLINK_FAMILY_MEMBER := 0x6E38\n  DLINK_FIRMWARE_SIZE := 0xFE0000\nendef\nTARGET_DEVICES += dlink_dwr-118-a1\n\ndefine Device/dlink_dwr-118-a2\n  $(Device/amit_jboot)\n  SOC := mt7620a\n  IMAGE_SIZE := 16256k\n  DEVICE_VENDOR := D-Link\n  DEVICE_MODEL := DWR-118\n  DEVICE_VARIANT := A2\n  DEVICE_PACKAGES += kmod-mt76x2\n  DLINK_ROM_ID := DLK6E3814001\n  DLINK_FAMILY_MEMBER := 0x6E38\n  DLINK_FIRMWARE_SIZE := 0xFE0000\nendef\nTARGET_DEVICES += dlink_dwr-118-a2\n\ndefine Device/dlink_dwr-921-c1\n  $(Device/amit_jboot)\n  SOC := mt7620n\n  IMAGE_SIZE := 16256k\n  DEVICE_VENDOR := D-Link\n  DEVICE_MODEL := DWR-921\n  DEVICE_VARIANT := C1\n  DLINK_ROM_ID := DLK6E2414001\n  DLINK_FAMILY_MEMBER := 0x6E24\n  DLINK_FIRMWARE_SIZE := 0xFE0000\n  DEVICE_PACKAGES += kmod-usb-net-qmi-wwan kmod-usb-serial-option uqmi\nendef\nTARGET_DEVICES += dlink_dwr-921-c1\n\ndefine Device/dlink_dwr-921-c3\n  $(Device/dlink_dwr-921-c1)\n  DEVICE_DTS := mt7620n_dlink_dwr-921-c1\n  DEVICE_VENDOR := D-Link\n  DEVICE_MODEL := DWR-921\n  DEVICE_VARIANT := C3\n  DLINK_ROM_ID := DLK6E2414009\n  SUPPORTED_DEVICES := dlink,dwr-921-c1\nendef\nTARGET_DEVICES += dlink_dwr-921-c3\n\ndefine Device/dlink_dwr-922-e2\n  $(Device/amit_jboot)\n  SOC := mt7620n\n  IMAGE_SIZE := 16256k\n  DEVICE_VENDOR := D-Link\n  DEVICE_MODEL := DWR-922\n  DEVICE_VARIANT := E2\n  DLINK_ROM_ID := DLK6E2414005\n  DLINK_FAMILY_MEMBER := 0x6E24\n  DLINK_FIRMWARE_SIZE := 0xFE0000\n  DEVICE_PACKAGES += kmod-usb-net-qmi-wwan kmod-usb-serial-option uqmi\nendef\nTARGET_DEVICES += dlink_dwr-922-e2\n\ndefine Device/dlink_dwr-960\n  $(Device/amit_jboot)\n  SOC := mt7620a\n  IMAGE_SIZE := 16256k\n  DEVICE_VENDOR := D-Link\n  DEVICE_MODEL := DWR-960\n  DLINK_ROM_ID := DLK6E2429001\n  DLINK_FAMILY_MEMBER := 0x6E24\n  DLINK_FIRMWARE_SIZE := 0xFE0000\n  DEVICE_PACKAGES += kmod-usb-net-qmi-wwan kmod-usb-serial-option uqmi \\\n\tkmod-mt76x0e\nendef\nTARGET_DEVICES += dlink_dwr-960\n\ndefine Device/dlink_dwr-961-a1\n  $(Device/amit_jboot)\n  SOC := mt7620a\n  IMAGE_SIZE := 16256k\n  DEVICE_VENDOR := D-Link\n  DEVICE_MODEL := DWR-961\n  DEVICE_VARIANT := A1\n  DLINK_ROM_ID := DLK6E3813001\n  DLINK_FAMILY_MEMBER := 0x6E38\n  DLINK_FIRMWARE_SIZE := 0xFE0000\n  DEVICE_PACKAGES += kmod-mt76x2 kmod-usb-net-qmi-wwan kmod-usb-serial-option \\\n\tuqmi\nendef\nTARGET_DEVICES += dlink_dwr-961-a1\n\ndefine Device/domywifi_dm202\n  SOC := mt7620a\n  IMAGE_SIZE := 16064k\n  DEVICE_VENDOR := DomyWifi\n  DEVICE_MODEL := DM202\n  DEVICE_PACKAGES := kmod-mt76x0e kmod-sdhci-mt7620 kmod-usb2 kmod-usb-ohci\nendef\nTARGET_DEVICES += domywifi_dm202\n\ndefine Device/domywifi_dm203\n  SOC := mt7620a\n  IMAGE_SIZE := 16064k\n  DEVICE_VENDOR := DomyWifi\n  DEVICE_MODEL := DM203\n  DEVICE_PACKAGES := kmod-mt76x0e kmod-sdhci-mt7620 kmod-usb2 kmod-usb-ohci\nendef\nTARGET_DEVICES += domywifi_dm203\n\ndefine Device/domywifi_dw22d\n  SOC := mt7620a\n  IMAGE_SIZE := 16064k\n  DEVICE_VENDOR := DomyWifi\n  DEVICE_MODEL := DW22D\n  DEVICE_PACKAGES := kmod-mt76x0e kmod-sdhci-mt7620 kmod-usb2 kmod-usb-ohci\nendef\nTARGET_DEVICES += domywifi_dw22d\n\ndefine Device/dovado_tiny-ac\n  SOC := mt7620a\n  IMAGE_SIZE := 7872k\n  DEVICE_VENDOR := Dovado\n  DEVICE_MODEL := Tiny AC\n  DEVICE_PACKAGES := kmod-mt76x0e kmod-usb2 kmod-usb-ohci\n  SUPPORTED_DEVICES += tiny-ac\nendef\nTARGET_DEVICES += dovado_tiny-ac\n\ndefine Device/edimax_br-6478ac-v2\n  SOC := mt7620a\n  DEVICE_VENDOR := Edimax\n  DEVICE_MODEL := BR-6478AC\n  DEVICE_VARIANT := V2\n  BLOCKSIZE := 64k\n  IMAGE_SIZE := 7744k\n  IMAGE/sysupgrade.bin := append-kernel | append-rootfs | \\\n\tedimax-header -s CSYS -m RN68 -f 0x70000 -S 0x01100000 | pad-rootfs | \\\n\tcheck-size | append-metadata\n  DEVICE_PACKAGES := kmod-mt76x2 kmod-usb2 kmod-usb-ohci \\\n\tkmod-usb-ledtrig-usbport\nendef\nTARGET_DEVICES += edimax_br-6478ac-v2\n\ndefine Device/edimax_ew-7476rpc\n  SOC := mt7620a\n  DEVICE_VENDOR := Edimax\n  DEVICE_MODEL := EW-7476RPC\n  BLOCKSIZE := 4k\n  IMAGE_SIZE := 7744k\n  IMAGE/sysupgrade.bin := append-kernel | append-rootfs | \\\n\tedimax-header -s CSYS -m RN79 -f 0x70000 -S 0x01100000 | pad-rootfs | \\\n\tcheck-size | append-metadata\n  DEVICE_PACKAGES := kmod-mt76x2 kmod-phy-realtek\nendef\nTARGET_DEVICES += edimax_ew-7476rpc\n\ndefine Device/edimax_ew-7478ac\n  SOC := mt7620a\n  DEVICE_VENDOR := Edimax\n  DEVICE_MODEL := EW-7478AC\n  BLOCKSIZE := 4k\n  IMAGE_SIZE := 7744k\n  IMAGE/sysupgrade.bin := append-kernel | append-rootfs | \\\n\tedimax-header -s CSYS -m RN70 -f 0x70000 -S 0x01100000 | pad-rootfs | \\\n\tcheck-size | append-metadata\n  DEVICE_PACKAGES := kmod-mt76x2 kmod-phy-realtek\nendef\nTARGET_DEVICES += edimax_ew-7478ac\n\ndefine Device/edimax_ew-7478apc\n  SOC := mt7620a\n  DEVICE_VENDOR := Edimax\n  DEVICE_MODEL := EW-7478APC\n  BLOCKSIZE := 4k\n  IMAGE_SIZE := 7744k\n  IMAGE/sysupgrade.bin := append-kernel | append-rootfs | \\\n\tedimax-header -s CSYS -m RN75 -f 0x70000 -S 0x01100000 | pad-rootfs | \\\n\tcheck-size | append-metadata\n  DEVICE_PACKAGES := kmod-mt76x2 kmod-usb2 kmod-usb-ohci \\\n\tkmod-usb-ledtrig-usbport\nendef\nTARGET_DEVICES += edimax_ew-7478apc\n\ndefine Device/elecom_wrh-300cr\n  SOC := mt7620n\n  IMAGE_SIZE := 14272k\n  IMAGES += factory.bin\n  IMAGE/factory.bin := $$(sysupgrade_bin) | check-size | elecom-header\n  DEVICE_VENDOR := Elecom\n  DEVICE_MODEL := WRH-300CR\n  DEVICE_PACKAGES := kmod-usb2 kmod-usb-ohci\n  SUPPORTED_DEVICES += wrh-300cr\nendef\nTARGET_DEVICES += elecom_wrh-300cr\n\ndefine Device/engenius_esr600\n  SOC := mt7620a\n  BLOCKSIZE := 64k\n  IMAGE_SIZE := 15616k\n  IMAGES += factory.dlf\n  IMAGE/factory.dlf := $$(sysupgrade_bin) | check-size | \\\n\tsenao-header -r 0x101 -p 0x57 -t 2\n  DEVICE_VENDOR := EnGenius\n  DEVICE_MODEL := ESR600\n  DEVICE_PACKAGES += kmod-rt2800-pci kmod-usb-storage kmod-usb-ohci \\\n\tkmod-usb-ehci\nendef\nTARGET_DEVICES += engenius_esr600\n\ndefine Device/fon_fon2601\n  SOC := mt7620a\n  IMAGE_SIZE := 15936k\n  DEVICE_VENDOR := Fon\n  DEVICE_MODEL := FON2601\n  DEVICE_PACKAGES := kmod-mt76x2 kmod-usb2 kmod-usb-ohci\n  KERNEL_INITRAMFS := $$(KERNEL) | uimage-padhdr\n  IMAGE/sysupgrade.bin := append-kernel | append-rootfs | uimage-padhdr | \\\n\tpad-rootfs | check-size | append-metadata\nendef\nTARGET_DEVICES += fon_fon2601\n\ndefine Device/glinet_gl-mt300a\n  SOC := mt7620a\n  IMAGE_SIZE := 15872k\n  DEVICE_VENDOR := GL.iNet\n  DEVICE_MODEL := GL-MT300A\n  DEVICE_PACKAGES := kmod-usb2 kmod-usb-ohci\n  SUPPORTED_DEVICES += gl-mt300a\nendef\nTARGET_DEVICES += glinet_gl-mt300a\n\ndefine Device/glinet_gl-mt300n\n  SOC := mt7620a\n  IMAGE_SIZE := 15872k\n  DEVICE_VENDOR := GL.iNet\n  DEVICE_MODEL := GL-MT300N\n  DEVICE_PACKAGES := kmod-usb2 kmod-usb-ohci\n  SUPPORTED_DEVICES += gl-mt300n\nendef\nTARGET_DEVICES += glinet_gl-mt300n\n\ndefine Device/glinet_gl-mt750\n  SOC := mt7620a\n  IMAGE_SIZE := 15872k\n  DEVICE_VENDOR := GL.iNet\n  DEVICE_MODEL := GL-MT750\n  DEVICE_PACKAGES := kmod-mt76x0e kmod-usb2 kmod-usb-ohci\n  SUPPORTED_DEVICES += gl-mt750\nendef\nTARGET_DEVICES += glinet_gl-mt750\n\ndefine Device/head-weblink_hdrm200\n  SOC := mt7620a\n  IMAGE_SIZE := 16064k\n  DEVICE_VENDOR := Head Weblink\n  DEVICE_MODEL := HDRM2000\n  DEVICE_PACKAGES := kmod-mt76x2 kmod-usb2 kmod-usb-ohci kmod-sdhci-mt7620 \\\n\tuqmi kmod-usb-serial-option\nendef\nTARGET_DEVICES += head-weblink_hdrm200\n\ndefine Device/hiwifi_hc5661\n  SOC := mt7620a\n  IMAGE_SIZE := 15808k\n  DEVICE_VENDOR := HiWiFi\n  DEVICE_MODEL := HC5661\n  DEVICE_PACKAGES := kmod-sdhci-mt7620\n  SUPPORTED_DEVICES += hc5661\nendef\nTARGET_DEVICES += hiwifi_hc5661\n\ndefine Device/hiwifi_hc5761\n  SOC := mt7620a\n  IMAGE_SIZE := 15808k\n  DEVICE_VENDOR := HiWiFi\n  DEVICE_MODEL := HC5761\n  DEVICE_PACKAGES := kmod-mt76x0e kmod-usb2 kmod-usb-ohci kmod-sdhci-mt7620 \\\n\tkmod-usb-ledtrig-usbport\n  SUPPORTED_DEVICES += hc5761\nendef\nTARGET_DEVICES += hiwifi_hc5761\n\ndefine Device/hiwifi_hc5861\n  SOC := mt7620a\n  IMAGE_SIZE := 15808k\n  DEVICE_VENDOR := HiWiFi\n  DEVICE_MODEL := HC5861\n  DEVICE_PACKAGES := kmod-mt76x2 kmod-usb2 kmod-usb-ohci kmod-sdhci-mt7620 \\\n\tkmod-usb-ledtrig-usbport\n  SUPPORTED_DEVICES += hc5861\nendef\nTARGET_DEVICES += hiwifi_hc5861\n\ndefine Device/hnet_c108\n  SOC := mt7620a\n  IMAGE_SIZE := 16064k\n  DEVICE_VENDOR := HNET\n  DEVICE_MODEL := C108\n  DEVICE_PACKAGES := kmod-usb2 kmod-usb-ohci kmod-sdhci-mt7620\n  SUPPORTED_DEVICES += c108\nendef\nTARGET_DEVICES += hnet_c108\n\ndefine Device/humax_e2\n  SOC := mt7620a\n  IMAGE_SIZE := 7744k\n  DEVICE_VENDOR := HUMAX\n  DEVICE_MODEL := E2\n  DEVICE_ALT0_VENDOR := HUMAX\n  DEVICE_ALT0_MODEL := QUANTUM E2\n  IMAGE/sysupgrade.bin := append-kernel | append-rootfs | \\\n\tedimax-header -s CSYS -m RN75 -f 0x70000 -S 0x01100000 | pad-rootfs | \\\n\tcheck-size | append-metadata\n  DEVICE_PACKAGES := kmod-mt76x0e\nendef\nTARGET_DEVICES += humax_e2\n\ndefine Device/sunvalley_filehub_common\n  SOC := mt7620n\n  IMAGE_SIZE := 6144k\n  DEVICE_PACKAGES := kmod-usb2 kmod-usb-ohci kmod-i2c-ralink\n  LOADER_TYPE := bin\n  LOADER_FLASH_OFFS := 0x200000\n  COMPILE := loader-$(1).bin\n  COMPILE/loader-$(1).bin := loader-okli-compile | pad-to 64k | lzma | \\\n\tuImage lzma\n  KERNEL := $(KERNEL_DTB) | uImage lzma -M 0x4f4b4c49\n  KERNEL_INITRAMFS := $(KERNEL_DTB) | uImage lzma\n  IMAGES += kernel.bin rootfs.bin\n  IMAGE/kernel.bin := append-loader-okli $(1) | check-size 64k\n  IMAGE/rootfs.bin := $$(sysupgrade_bin) | check-size\nendef\n\ndefine Device/hootoo_ht-tm05\n  $(Device/sunvalley_filehub_common)\n  DEVICE_VENDOR := HooToo\n  DEVICE_MODEL := HT-TM05\nendef\nTARGET_DEVICES += hootoo_ht-tm05\n\ndefine Device/iodata_wn-ac1167gr\n  SOC := mt7620a\n  DEVICE_VENDOR := I-O DATA\n  DEVICE_MODEL := WN-AC1167GR\n  IMAGE_SIZE := 6864k\n  IMAGES += factory.bin\n  IMAGE/factory.bin := $$(sysupgrade_bin) | check-size | \\\n\telx-header 01040016 8844A2D168B45A2D\n  DEVICE_PACKAGES := kmod-mt76x2\nendef\nTARGET_DEVICES += iodata_wn-ac1167gr\n\ndefine Device/iodata_wn-ac733gr3\n  SOC := mt7620a\n  DEVICE_VENDOR := I-O DATA\n  DEVICE_MODEL := WN-AC733GR3\n  IMAGE_SIZE := 6992k\n  IMAGES += factory.bin\n  IMAGE/factory.bin := $$(sysupgrade_bin) | check-size | \\\n\telx-header 01040006 8844A2D168B45A2D\n  DEVICE_PACKAGES := kmod-mt76x0e kmod-switch-rtl8367b\nendef\nTARGET_DEVICES += iodata_wn-ac733gr3\n\ndefine Device/iptime_a1004ns\n  SOC := mt7620a\n  IMAGE_SIZE := 16192k\n  UIMAGE_NAME := a1004ns\n  DEVICE_VENDOR := ipTIME\n  DEVICE_MODEL := A1004ns\n  DEVICE_PACKAGES := kmod-mt76x0e kmod-usb2 kmod-usb-ohci \\\n\tkmod-usb-ledtrig-usbport\nendef\nTARGET_DEVICES += iptime_a1004ns\n\ndefine Device/iptime_a104ns\n  SOC := mt7620a\n  IMAGE_SIZE := 8000k\n  UIMAGE_NAME := a104ns\n  DEVICE_VENDOR := ipTIME\n  DEVICE_MODEL := A104ns\n  DEVICE_PACKAGES := kmod-mt76x0e kmod-usb2 kmod-usb-ohci \\\n\tkmod-usb-ledtrig-usbport\nendef\nTARGET_DEVICES += iptime_a104ns\n\ndefine Device/kimax_u25awf-h1\n  SOC := mt7620a\n  IMAGE_SIZE := 16064k\n  DEVICE_VENDOR := Kimax\n  DEVICE_MODEL := U25AWF\n  DEVICE_VARIANT := H1\n  DEVICE_PACKAGES := kmod-usb2 kmod-usb-ohci kmod-usb-storage kmod-scsi-core \\\n\tkmod-fs-ext4 kmod-fs-vfat block-mount\n  SUPPORTED_DEVICES += u25awf-h1\nendef\nTARGET_DEVICES += kimax_u25awf-h1\n\ndefine Device/kimax_u35wf\n  SOC := mt7620n\n  IMAGE_SIZE := 16064k\n  DEVICE_VENDOR := Kimax\n  DEVICE_MODEL := U35WF\n  DEVICE_PACKAGES := kmod-usb2 kmod-usb-ohci kmod-usb-storage kmod-scsi-core \\\n\tkmod-fs-ext4 kmod-fs-vfat block-mount\nendef\nTARGET_DEVICES += kimax_u35wf\n\ndefine Device/kingston_mlw221\n  SOC := mt7620n\n  IMAGE_SIZE := 15744k\n  DEVICE_VENDOR := Kingston\n  DEVICE_MODEL := MLW221\n  DEVICE_PACKAGES := kmod-mt76x2 kmod-usb2 kmod-usb-ohci\n  SUPPORTED_DEVICES += mlw221\nendef\nTARGET_DEVICES += kingston_mlw221\n\ndefine Device/kingston_mlwg2\n  SOC := mt7620n\n  IMAGE_SIZE := 15744k\n  DEVICE_VENDOR := Kingston\n  DEVICE_MODEL := MLWG2\n  DEVICE_PACKAGES := kmod-mt76x2 kmod-usb2 kmod-usb-ohci\n  SUPPORTED_DEVICES += mlwg2\nendef\nTARGET_DEVICES += kingston_mlwg2\n\ndefine Device/lava_lr-25g001\n  $(Device/amit_jboot)\n  SOC := mt7620a\n  IMAGE_SIZE := 16256k\n  DEVICE_VENDOR := LAVA\n  DEVICE_MODEL := LR-25G001\n  DLINK_ROM_ID := LVA6E3804001\n  DLINK_FAMILY_MEMBER := 0x6E38\n  DLINK_FIRMWARE_SIZE := 0xFE0000\n  DEVICE_PACKAGES += kmod-mt76x0e\nendef\nTARGET_DEVICES += lava_lr-25g001\n\ndefine Device/lb-link_bl-w1200\n  SOC := mt7620a\n  DEVICE_VENDOR := LB-Link\n  DEVICE_MODEL := BL-W1200\n  IMAGE_SIZE := 7872k\n  DEVICE_PACKAGES := kmod-usb2 kmod-usb-ohci kmod-mt76x2\nendef\nTARGET_DEVICES += lb-link_bl-w1200\n\ndefine Device/lenovo_newifi-y1\n  SOC := mt7620a\n  IMAGE_SIZE := 16064k\n  DEVICE_VENDOR := Lenovo\n  DEVICE_MODEL := Y1\n  DEVICE_PACKAGES := kmod-mt76x2 kmod-usb2 kmod-usb-ohci\n  SUPPORTED_DEVICES += y1\nendef\nTARGET_DEVICES += lenovo_newifi-y1\n\ndefine Device/lenovo_newifi-y1s\n  SOC := mt7620a\n  IMAGE_SIZE := 16064k\n  DEVICE_VENDOR := Lenovo\n  DEVICE_MODEL := Y1S\n  DEVICE_PACKAGES := kmod-mt76x2 kmod-usb2 kmod-usb-ohci\n  SUPPORTED_DEVICES += y1s\nendef\nTARGET_DEVICES += lenovo_newifi-y1s\n\ndefine Device/linksys_e1700\n  SOC := mt7620a\n  IMAGE_SIZE := 7872k\n  IMAGES += factory.bin\n  IMAGE/factory.bin := $$(sysupgrade_bin) | check-size | umedia-header 0x013326\n  DEVICE_VENDOR := Linksys\n  DEVICE_MODEL := E1700\n  SUPPORTED_DEVICES += e1700\nendef\nTARGET_DEVICES += linksys_e1700\n\ndefine Device/microduino_microwrt\n  SOC := mt7620a\n  IMAGE_SIZE := 16128k\n  DEVICE_VENDOR := Microduino\n  DEVICE_MODEL := MicroWRT\n  DEVICE_PACKAGES := kmod-usb2 kmod-usb-ohci\n  SUPPORTED_DEVICES += microwrt\nendef\nTARGET_DEVICES += microduino_microwrt\n\ndefine Device/netgear_ex2700\n  SOC := mt7620a\n  NETGEAR_HW_ID := 29764623+4+0+32+2x2+0\n  NETGEAR_BOARD_ID := EX2700\n  BLOCKSIZE := 4k\n  IMAGE_SIZE := 3776k\n  IMAGES += factory.bin\n  KERNEL := $(KERNEL_DTB) | uImage lzma | pad-offset 64k 64 | \\\n\tappend-uImage-fakehdr filesystem\n  IMAGE/factory.bin := $$(sysupgrade_bin) | check-size | netgear-dni\n  DEVICE_VENDOR := NETGEAR\n  DEVICE_MODEL := EX2700\n  SUPPORTED_DEVICES += ex2700\n  DEFAULT := n\nendef\nTARGET_DEVICES += netgear_ex2700\n\ndefine Device/netgear_ex3700\n  SOC := mt7620a\n  NETGEAR_BOARD_ID := U12H319T00_NETGEAR\n  BLOCKSIZE := 4k\n  IMAGE_SIZE := 7744k\n  IMAGES += factory.chk\n  IMAGE/factory.chk := $$(sysupgrade_bin) | check-size | netgear-chk\n  DEVICE_PACKAGES := kmod-mt76x2\n  DEVICE_VENDOR := NETGEAR\n  DEVICE_MODEL := EX3700/EX3800\n  SUPPORTED_DEVICES += ex3700\nendef\nTARGET_DEVICES += netgear_ex3700\n\ndefine Device/netgear_ex6120\n  SOC := mt7620a\n  NETGEAR_BOARD_ID := U12H319T30_NETGEAR\n  BLOCKSIZE := 4k\n  IMAGE_SIZE := 7744k\n  IMAGES += factory.chk\n  IMAGE/factory.chk := $$(sysupgrade_bin) | check-size | netgear-chk\n  DEVICE_PACKAGES := kmod-mt76x2\n  DEVICE_VENDOR := NETGEAR\n  DEVICE_MODEL := EX6120\nendef\nTARGET_DEVICES += netgear_ex6120\n\ndefine Device/netgear_ex6130\n  SOC := mt7620a\n  NETGEAR_BOARD_ID := U12H319T50_NETGEAR\n  BLOCKSIZE := 4k\n  IMAGE_SIZE := 7744k\n  IMAGES += factory.chk\n  IMAGE/factory.chk := $$(sysupgrade_bin) | check-size | netgear-chk\n  DEVICE_PACKAGES := kmod-mt76x2\n  DEVICE_VENDOR := NETGEAR\n  DEVICE_MODEL := EX6130\nendef\nTARGET_DEVICES += netgear_ex6130\n\ndefine Device/netgear_jwnr2010-v5\n  $(Device/netgear_sercomm_nor)\n  SOC := mt7620n\n  BLOCKSIZE := 4k\n  IMAGE_SIZE := 3840k\n  DEVICE_MODEL := JWNR2010\n  DEVICE_VARIANT := v5\n  SERCOMM_HWNAME := N300\n  SERCOMM_HWID := ASW\n  SERCOMM_HWVER := A001\n  SERCOMM_SWVER := 0x0040\n  SERCOMM_PAD := 128k\n  DEFAULT := n\nendef\nTARGET_DEVICES += netgear_jwnr2010-v5\n\ndefine Device/netgear_wn3000rp-v3\n  SOC := mt7620a\n  IMAGE_SIZE := 7872k\n  NETGEAR_HW_ID := 29764836+8+0+32+2x2+0\n  NETGEAR_BOARD_ID := WN3000RPv3\n  BLOCKSIZE := 4k\n  IMAGES += factory.bin\n  KERNEL := $(KERNEL_DTB) | uImage lzma | pad-offset 64k 64 | \\\n\tappend-uImage-fakehdr filesystem\n  IMAGE/factory.bin := $$(sysupgrade_bin) | check-size | netgear-dni\n  DEVICE_VENDOR := NETGEAR\n  DEVICE_MODEL := WN3000RP\n  DEVICE_VARIANT := v3\n  SUPPORTED_DEVICES += wn3000rpv3\nendef\nTARGET_DEVICES += netgear_wn3000rp-v3\n\ndefine Device/netgear_wn3100rp-v2\n  SOC := mt7620a\n  IMAGE_SIZE := 7872k\n  NETGEAR_HW_ID := 29764883+8+0+32+2x2+0\n  NETGEAR_BOARD_ID := WN3100RPv2\n  BLOCKSIZE := 4k\n  IMAGES += factory.bin\n  KERNEL := $(KERNEL_DTB) | uImage lzma | pad-offset 64k 64 | \\\n\tappend-uImage-fakehdr filesystem\n  IMAGE/factory.bin := $$(sysupgrade_bin) | check-size | netgear-dni\n  DEVICE_VENDOR := NETGEAR\n  DEVICE_MODEL := WN3100RP\n  DEVICE_VARIANT := v2\nendef\nTARGET_DEVICES += netgear_wn3100rp-v2\n\ndefine Device/netis_wf2770\n  SOC := mt7620a\n  IMAGE_SIZE := 16064k\n  UIMAGE_NAME := WF2770_0.0.00\n  DEVICE_VENDOR := NETIS\n  DEVICE_MODEL := WF2770\n  DEVICE_PACKAGES := kmod-mt76x0e\n  KERNEL_INITRAMFS := $(KERNEL_DTB) | netis-tail WF2770 | uImage lzma\nendef\nTARGET_DEVICES += netis_wf2770\n\ndefine Device/nexx_wt3020-4m\n  SOC := mt7620n\n  BLOCKSIZE := 4k\n  IMAGE_SIZE := 3776k\n  IMAGES += factory.bin\n  IMAGE/factory.bin := $$(sysupgrade_bin) | check-size | \\\n\tporay-header -B WT3020 -F 4M\n  DEVICE_VENDOR := Nexx\n  DEVICE_MODEL := WT3020\n  DEVICE_VARIANT := 4M\n  SUPPORTED_DEVICES += wt3020 wt3020-4M\n  DEFAULT := n\nendef\nTARGET_DEVICES += nexx_wt3020-4m\n\ndefine Device/nexx_wt3020-8m\n  SOC := mt7620n\n  IMAGE_SIZE := 7872k\n  IMAGES += factory.bin\n  IMAGE/factory.bin := $$(sysupgrade_bin) | check-size | \\\n\tporay-header -B WT3020 -F 8M\n  DEVICE_VENDOR := Nexx\n  DEVICE_MODEL := WT3020\n  DEVICE_VARIANT := 8M\n  DEVICE_PACKAGES := kmod-usb2 kmod-usb-ohci\n  SUPPORTED_DEVICES += wt3020 wt3020-8M\nendef\nTARGET_DEVICES += nexx_wt3020-8m\n\ndefine Device/ohyeah_oy-0001\n  SOC := mt7620a\n  IMAGE_SIZE := 16064k\n  DEVICE_VENDOR := Oh Yeah\n  DEVICE_MODEL := OY-0001\n  DEVICE_PACKAGES := kmod-usb2 kmod-usb-ohci\n  SUPPORTED_DEVICES += oy-0001\nendef\nTARGET_DEVICES += ohyeah_oy-0001\n\ndefine Device/phicomm_k2-v22.4\n  SOC := mt7620a\n  IMAGE_SIZE := 7872k\n  DEVICE_VENDOR := Phicomm\n  DEVICE_MODEL := K2\n  DEVICE_VARIANT:= v22.4 or older\n  DEVICE_PACKAGES := kmod-mt76x2\n  SUPPORTED_DEVICES += psg1218 psg1218a phicomm,psg1218a\nendef\nTARGET_DEVICES += phicomm_k2-v22.4\n\ndefine Device/phicomm_k2-v22.5\n  SOC := mt7620a\n  IMAGE_SIZE := 7552k\n  DEVICE_VENDOR := Phicomm\n  DEVICE_MODEL := K2\n  DEVICE_VARIANT:= v22.5 or newer\n  DEVICE_PACKAGES := kmod-mt76x2\nendef\nTARGET_DEVICES += phicomm_k2-v22.5\n\ndefine Device/phicomm_k2g\n  SOC := mt7620a\n  IMAGE_SIZE := 7552k\n  DEVICE_VENDOR := Phicomm\n  DEVICE_MODEL := K2G\n  DEVICE_PACKAGES := kmod-mt76x2\nendef\nTARGET_DEVICES += phicomm_k2g\n\ndefine Device/phicomm_psg1208\n  SOC := mt7620a\n  IMAGE_SIZE := 7872k\n  DEVICE_VENDOR := Phicomm\n  DEVICE_MODEL := PSG1208\n  DEVICE_PACKAGES := kmod-mt76x2\n  SUPPORTED_DEVICES += psg1208\nendef\nTARGET_DEVICES += phicomm_psg1208\n\ndefine Device/phicomm_psg1218b\n  SOC := mt7620a\n  IMAGE_SIZE := 7872k\n  DEVICE_VENDOR := Phicomm\n  DEVICE_MODEL := PSG1218\n  DEVICE_VARIANT := Bx\n  DEVICE_PACKAGES := kmod-mt76x2\n  SUPPORTED_DEVICES += psg1218 psg1218b\nendef\nTARGET_DEVICES += phicomm_psg1218b\n\ndefine Device/planex_cs-qr10\n  SOC := mt7620a\n  IMAGE_SIZE := 7872k\n  DEVICE_VENDOR := Planex\n  DEVICE_MODEL := CS-QR10\n  DEVICE_PACKAGES := kmod-usb2 kmod-usb-ohci kmod-sound-core \\\n\tkmod-sound-mt7620 kmod-i2c-ralink kmod-sdhci-mt7620\n  SUPPORTED_DEVICES += cs-qr10\nendef\nTARGET_DEVICES += planex_cs-qr10\n\ndefine Device/planex_db-wrt01\n  SOC := mt7620a\n  IMAGE_SIZE := 7872k\n  DEVICE_VENDOR := Planex\n  DEVICE_MODEL := DB-WRT01\n  SUPPORTED_DEVICES += db-wrt01\nendef\nTARGET_DEVICES += planex_db-wrt01\n\ndefine Device/planex_mzk-750dhp\n  SOC := mt7620a\n  IMAGE_SIZE := 7872k\n  DEVICE_VENDOR := Planex\n  DEVICE_MODEL := MZK-750DHP\n  DEVICE_PACKAGES := kmod-mt76x0e\n  SUPPORTED_DEVICES += mzk-750dhp\nendef\nTARGET_DEVICES += planex_mzk-750dhp\n\ndefine Device/planex_mzk-ex300np\n  SOC := mt7620a\n  IMAGE_SIZE := 7360k\n  DEVICE_VENDOR := Planex\n  DEVICE_MODEL := MZK-EX300NP\n  SUPPORTED_DEVICES += mzk-ex300np\nendef\nTARGET_DEVICES += planex_mzk-ex300np\n\ndefine Device/planex_mzk-ex750np\n  SOC := mt7620a\n  IMAGE_SIZE := 7360k\n  DEVICE_VENDOR := Planex\n  DEVICE_MODEL := MZK-EX750NP\n  DEVICE_PACKAGES := kmod-mt76x2\n  SUPPORTED_DEVICES += mzk-ex750np\nendef\nTARGET_DEVICES += planex_mzk-ex750np\n\ndefine Device/ralink_mt7620a-evb\n  SOC := mt7620a\n  IMAGE_SIZE := 7872k\n  DEVICE_VENDOR := MediaTek\n  DEVICE_MODEL := MT7620a EVB\nendef\nTARGET_DEVICES += ralink_mt7620a-evb\n\ndefine Device/ralink_mt7620a-mt7530-evb\n  SOC := mt7620a\n  IMAGE_SIZE := 7872k\n  DEVICE_VENDOR := MediaTek\n  DEVICE_MODEL := MT7620a + MT7530 EVB\n  SUPPORTED_DEVICES += mt7620a_mt7530\nendef\nTARGET_DEVICES += ralink_mt7620a-mt7530-evb\n\ndefine Device/ralink_mt7620a-mt7610e-evb\n  SOC := mt7620a\n  IMAGE_SIZE := 7872k\n  DEVICE_VENDOR := MediaTek\n  DEVICE_MODEL := MT7620a + MT7610e EVB\n  DEVICE_PACKAGES := kmod-mt76x0e\n  SUPPORTED_DEVICES += mt7620a_mt7610e\nendef\nTARGET_DEVICES += ralink_mt7620a-mt7610e-evb\n\ndefine Device/ralink_mt7620a-v22sg-evb\n  SOC := mt7620a\n  IMAGE_SIZE := 130560k\n  DEVICE_VENDOR := MediaTek\n  DEVICE_MODEL := MT7620a V22SG\n  SUPPORTED_DEVICES += mt7620a_v22sg\nendef\nTARGET_DEVICES += ralink_mt7620a-v22sg-evb\n\ndefine Device/ravpower_rp-wd03\n  $(Device/sunvalley_filehub_common)\n  DEVICE_VENDOR := RAVPower\n  DEVICE_MODEL := RP-WD03\n  SUPPORTED_DEVICES += ravpower,wd03\n  DEVICE_COMPAT_VERSION := 2.0\n  DEVICE_COMPAT_MESSAGE := Partition design has changed compared to older versions (up to 19.07) due to kernel size restrictions. \\\n\tUpgrade via sysupgrade mechanism is not possible, so new installation via TFTP is required.\nendef\nTARGET_DEVICES += ravpower_rp-wd03\n\ndefine Device/sanlinking_d240\n  SOC := mt7620a\n  IMAGE_SIZE := 16064k\n  DEVICE_VENDOR := Sanlinking Technologies\n  DEVICE_MODEL := D240\n  DEVICE_PACKAGES := kmod-mt76x2 kmod-usb2 kmod-usb-ohci kmod-sdhci-mt7620\n  SUPPORTED_DEVICES += d240\nendef\nTARGET_DEVICES += sanlinking_d240\n\ndefine Device/sercomm_na930\n  SOC := mt7620a\n  IMAGE_SIZE := 20480k\n  DEVICE_VENDOR := Sercomm\n  DEVICE_MODEL := NA930\n  DEVICE_PACKAGES := kmod-usb2 kmod-usb-ohci\n  SUPPORTED_DEVICES += na930\nendef\nTARGET_DEVICES += sercomm_na930\n\ndefine Device/sitecom_wlr-4100-v1-002\n  SOC := mt7620a\n  BLOCKSIZE := 4k\n  IMAGE_SIZE := 7744k\n  IMAGES += factory.dlf\n  IMAGE/factory.dlf := $$(sysupgrade_bin) | check-size | \\\n\tsenao-header -r 0x0222 -p 0x104A -t 2\n  DEVICE_VENDOR := Sitecom\n  DEVICE_MODEL := WLR-4100\n  DEVICE_VARIANT := v1 002\n  DEVICE_PACKAGES := kmod-usb2 kmod-usb-ohci uboot-envtools\nendef\nTARGET_DEVICES += sitecom_wlr-4100-v1-002\n\ndefine Device/tplink_archer-c20i\n  $(Device/tplink-v2)\n  SOC := mt7620a\n  IMAGE_SIZE := 7808k\n  TPLINK_FLASHLAYOUT := 8Mmtk\n  TPLINK_HWID := 0xc2000001\n  TPLINK_HWREV := 58\n  DEVICE_MODEL := Archer C20i\n  DEVICE_PACKAGES := kmod-mt76x0e kmod-usb2 kmod-usb-ohci\n  SUPPORTED_DEVICES += c20i\nendef\nTARGET_DEVICES += tplink_archer-c20i\n\ndefine Device/tplink_archer-c20-v1\n  $(Device/tplink-v2)\n  SOC := mt7620a\n  IMAGE_SIZE := 7808k\n  SUPPORTED_DEVICES += tplink,c20-v1\n  TPLINK_FLASHLAYOUT := 8Mmtk\n  TPLINK_HWID := 0xc2000001\n  TPLINK_HWREV := 0x44\n  TPLINK_HWREVADD := 0x1\n  IMAGES := sysupgrade.bin\n  DEVICE_MODEL := Archer C20\n  DEVICE_VARIANT := v1\n  DEVICE_PACKAGES := kmod-mt76x0e kmod-usb2 kmod-usb-ohci \\\n\tkmod-usb-ledtrig-usbport\nendef\nTARGET_DEVICES += tplink_archer-c20-v1\n\ndefine Device/tplink_archer-c2-v1\n  $(Device/tplink-v2)\n  SOC := mt7620a\n  IMAGE_SIZE := 7808k\n  SUPPORTED_DEVICES += tplink,c2-v1\n  TPLINK_FLASHLAYOUT := 8Mmtk\n  TPLINK_HWID := 0xc7500001\n  TPLINK_HWREV := 50\n  IMAGES := sysupgrade.bin\n  DEVICE_MODEL := Archer C2\n  DEVICE_VARIANT := v1\n  DEVICE_PACKAGES := kmod-mt76x0e kmod-usb2 kmod-usb-ohci \\\n\tkmod-usb-ledtrig-usbport kmod-switch-rtl8366-smi kmod-switch-rtl8367b\nendef\nTARGET_DEVICES += tplink_archer-c2-v1\n\ndefine Device/tplink_archer-c50-v1\n  $(Device/tplink-v2)\n  SOC := mt7620a\n  IMAGE_SIZE := 7808k\n  TPLINK_FLASHLAYOUT := 8Mmtk\n  TPLINK_HWID := 0xc7500001\n  TPLINK_HWREV := 69\n  IMAGES := sysupgrade.bin factory-us.bin factory-eu.bin\n  IMAGE/factory-us.bin := tplink-v2-image -e -w 0\n  IMAGE/factory-eu.bin := tplink-v2-image -e -w 2\n  DEVICE_MODEL := Archer C50\n  DEVICE_VARIANT := v1\n  DEVICE_PACKAGES := kmod-mt76x2 kmod-usb2 kmod-usb-ohci\n  SUPPORTED_DEVICES += c50\nendef\nTARGET_DEVICES += tplink_archer-c50-v1\n\ndefine Device/tplink_archer-mr200\n  $(Device/tplink-v2)\n  SOC := mt7620a\n  IMAGE_SIZE := 7872k\n  TPLINK_FLASHLAYOUT := 8MLmtk\n  TPLINK_HWID := 0xd7500001\n  TPLINK_HWREV := 0x4a\n  IMAGES := sysupgrade.bin\n  DEVICE_PACKAGES := kmod-mt76x0e kmod-usb2 kmod-usb-net-rndis \\\n\tkmod-usb-serial-option adb-enablemodem\n  DEVICE_MODEL := Archer MR200\n  SUPPORTED_DEVICES += mr200\nendef\nTARGET_DEVICES += tplink_archer-mr200\n\ndefine Device/tplink_re200-v1\n  $(Device/tplink-v1)\n  SOC := mt7620a\n  DEVICE_MODEL := RE200\n  DEVICE_VARIANT := v1\n  DEVICE_PACKAGES := kmod-mt76x0e\n  IMAGE_SIZE := 7936k\n  TPLINK_HWID := 0x02000001\n  TPLINK_FLASHLAYOUT := 8Mmtk\nendef\nTARGET_DEVICES += tplink_re200-v1\n\ndefine Device/tplink_re210-v1\n  $(Device/tplink-v1)\n  SOC := mt7620a\n  DEVICE_MODEL := RE210\n  DEVICE_VARIANT := v1\n  DEVICE_PACKAGES := kmod-mt76x0e\n  IMAGE_SIZE := 7936k\n  TPLINK_HWID := 0x02100001\n  TPLINK_FLASHLAYOUT := 8Mmtk\nendef\nTARGET_DEVICES += tplink_re210-v1\n\ndefine Device/trendnet_tew-810dr\n  SOC := mt7620a\n  DEVICE_PACKAGES := kmod-mt76x0e\n  DEVICE_VENDOR := TRENDnet\n  DEVICE_MODEL := TEW-810DR\n  IMAGE_SIZE := 6720k\nendef\nTARGET_DEVICES += trendnet_tew-810dr\n\ndefine Device/vonets_var11n-300\n  SOC := mt7620n\n  IMAGE_SIZE := 3776k\n  BLOCKSIZE := 4k\n  DEVICE_VENDOR := Vonets\n  DEVICE_MODEL := VAR11N-300\n  DEFAULT := n\nendef\nTARGET_DEVICES += vonets_var11n-300\n\ndefine Device/wavlink_wl-wn530hg4\n  SOC := mt7620a\n  IMAGE_SIZE := 7872k\n  DEVICE_VENDOR := Wavlink\n  DEVICE_MODEL := WL-WN530HG4\n  DEVICE_PACKAGES := kmod-mt76x2\nendef\nTARGET_DEVICES += wavlink_wl-wn530hg4\n\ndefine Device/wavlink_wl-wn535k1\n  SOC := mt7620a\n  IMAGE_SIZE := 7360k\n  DEVICE_VENDOR := Wavlink\n  DEVICE_MODEL := WL-WN535K1\n  DEVICE_ALT0_VENDOR := Talius\n  DEVICE_ALT0_MODEL := TAL-WMESH1\n  KERNEL_INITRAMFS_SUFFIX := -WN535K1$$(KERNEL_SUFFIX)\n  DEVICE_PACKAGES := kmod-mt76x2 kmod-phy-realtek\nendef\nTARGET_DEVICES += wavlink_wl-wn535k1\n\ndefine Device/wavlink_wl-wn579x3\n  SOC := mt7620a\n  IMAGE_SIZE := 7744k\n  DEVICE_VENDOR := Wavlink\n  DEVICE_MODEL := WL-WN579X3\n  DEVICE_PACKAGES := kmod-mt76x2 kmod-phy-realtek\nendef\nTARGET_DEVICES += wavlink_wl-wn579x3\n\ndefine Device/wevo_air-duo\n  SOC := mt7620a\n  IMAGE_SIZE := 15040k\n  UIMAGE_NAME := AIR DUO(0.0.0)\n  KERNEL_INITRAMFS_SUFFIX := .upload\n  DEVICE_VENDOR := WeVO\n  DEVICE_MODEL := AIR DUO\n  DEVICE_PACKAGES := kmod-mt76x2 kmod-usb2 kmod-usb-ohci kmod-usb-storage-uas\nendef\nTARGET_DEVICES += wevo_air-duo\n\ndefine Device/wrtnode_wrtnode\n  SOC := mt7620n\n  IMAGE_SIZE := 16064k\n  DEVICE_VENDOR := WRTNode\n  DEVICE_MODEL := WRTNode\n  DEVICE_PACKAGES := kmod-usb2 kmod-usb-ohci\n  SUPPORTED_DEVICES += wrtnode\nendef\nTARGET_DEVICES += wrtnode_wrtnode\n\ndefine Device/xiaomi_miwifi-mini\n  SOC := mt7620a\n  IMAGE_SIZE := 15872k\n  DEVICE_VENDOR := Xiaomi\n  DEVICE_MODEL := MiWiFi Mini\n  DEVICE_PACKAGES := kmod-mt76x2 kmod-usb2 kmod-usb-ohci\n  SUPPORTED_DEVICES += miwifi-mini\nendef\nTARGET_DEVICES += xiaomi_miwifi-mini\n\ndefine Device/youku_yk-l1\n  SOC := mt7620a\n  IMAGE_SIZE := 32448k\n  DEVICE_VENDOR := Youku\n  DEVICE_MODEL := YK-L1\n  DEVICE_PACKAGES := kmod-usb2 kmod-usb-ohci kmod-sdhci-mt7620 \\\n\tkmod-usb-ledtrig-usbport\n  SUPPORTED_DEVICES += youku-yk1 youku,yk1\nendef\nTARGET_DEVICES += youku_yk-l1\n\ndefine Device/youku_yk-l1c\n  SOC := mt7620a\n  IMAGE_SIZE := 16064k\n  DEVICE_VENDOR := Youku\n  DEVICE_MODEL := YK-L1c\n  DEVICE_PACKAGES := kmod-usb2 kmod-usb-ohci kmod-sdhci-mt7620 \\\n\tkmod-usb-ledtrig-usbport\nendef\nTARGET_DEVICES += youku_yk-l1c\n\ndefine Device/yukai_bocco\n  SOC := mt7620a\n  IMAGE_SIZE := 7872k\n  DEVICE_VENDOR := YUKAI Engineering\n  DEVICE_MODEL := BOCCO\n  DEVICE_PACKAGES := kmod-sound-core kmod-sound-mt7620 kmod-i2c-ralink\n  SUPPORTED_DEVICES += bocco\nendef\nTARGET_DEVICES += yukai_bocco\n\ndefine Device/zbtlink_zbt-ape522ii\n  SOC := mt7620a\n  IMAGE_SIZE := 15872k\n  DEVICE_VENDOR := Zbtlink\n  DEVICE_MODEL := ZBT-APE522II\n  DEVICE_PACKAGES := kmod-mt76x2\n  SUPPORTED_DEVICES += zbt-ape522ii\nendef\nTARGET_DEVICES += zbtlink_zbt-ape522ii\n\ndefine Device/zbtlink_zbt-cpe102\n  SOC := mt7620n\n  IMAGE_SIZE := 7552k\n  DEVICE_VENDOR := Zbtlink\n  DEVICE_MODEL := ZBT-CPE102\n  DEVICE_PACKAGES := kmod-usb2 kmod-usb-ohci\n  SUPPORTED_DEVICES += zbt-cpe102\nendef\nTARGET_DEVICES += zbtlink_zbt-cpe102\n\ndefine Device/zbtlink_zbt-wa05\n  SOC := mt7620n\n  IMAGE_SIZE := 7552k\n  DEVICE_VENDOR := Zbtlink\n  DEVICE_MODEL := ZBT-WA05\n  DEVICE_PACKAGES := kmod-usb2 kmod-usb-ohci\n  SUPPORTED_DEVICES += zbt-wa05\nendef\nTARGET_DEVICES += zbtlink_zbt-wa05\n\ndefine Device/zbtlink_zbt-we1026-5g-16m\n  SOC := mt7620a\n  IMAGE_SIZE := 16064k\n  DEVICE_VENDOR := Zbtlink\n  DEVICE_MODEL := ZBT-WE1026-5G\n  DEVICE_VARIANT := 16M\n  DEVICE_PACKAGES := kmod-mt76x2 kmod-usb2 kmod-usb-ohci kmod-sdhci-mt7620\n  SUPPORTED_DEVICES += we1026-5g-16m zbtlink,we1026-5g-16m\nendef\nTARGET_DEVICES += zbtlink_zbt-we1026-5g-16m\n\ndefine Device/zbtlink_zbt-we1026-h-32m\n  SOC := mt7620a\n  IMAGE_SIZE := 32448k\n  DEVICE_VENDOR := Zbtlink\n  DEVICE_MODEL := ZBT-WE1026-H\n  DEVICE_VARIANT := 32M\n  DEVICE_PACKAGES := kmod-usb2 kmod-usb-ohci kmod-sdhci-mt7620\nendef\nTARGET_DEVICES += zbtlink_zbt-we1026-h-32m\n\ndefine Device/zbtlink_zbt-we2026\n  SOC := mt7620n\n  IMAGE_SIZE := 7552k\n  DEVICE_VENDOR := Zbtlink\n  DEVICE_MODEL := ZBT-WE2026\n  SUPPORTED_DEVICES += zbt-we2026\nendef\nTARGET_DEVICES += zbtlink_zbt-we2026\n\ndefine Device/zbtlink_zbt-we826-16m\n  SOC := mt7620a\n  IMAGE_SIZE := 16064k\n  DEVICE_VENDOR := Zbtlink\n  DEVICE_MODEL := ZBT-WE826\n  DEVICE_VARIANT := 16M\n  DEVICE_PACKAGES := kmod-mt76x2 kmod-usb2 kmod-usb-ohci kmod-sdhci-mt7620\n  SUPPORTED_DEVICES += zbt-we826 zbt-we826-16M\nendef\nTARGET_DEVICES += zbtlink_zbt-we826-16m\n\ndefine Device/zbtlink_zbt-we826-32m\n  SOC := mt7620a\n  IMAGE_SIZE := 32448k\n  DEVICE_VENDOR := Zbtlink\n  DEVICE_MODEL := ZBT-WE826\n  DEVICE_VARIANT := 32M\n  DEVICE_PACKAGES := kmod-mt76x2 kmod-usb2 kmod-usb-ohci kmod-sdhci-mt7620\n  SUPPORTED_DEVICES += zbt-we826-32M\nendef\nTARGET_DEVICES += zbtlink_zbt-we826-32m\n\ndefine Device/zbtlink_zbt-we826-e\n  SOC := mt7620a\n  IMAGE_SIZE := 32448k\n  DEVICE_VENDOR := Zbtlink\n  DEVICE_MODEL := ZBT-WE826-E\n  DEVICE_PACKAGES := kmod-usb2 kmod-usb-ohci kmod-sdhci-mt7620 uqmi \\\n\tkmod-usb-serial-option\nendef\nTARGET_DEVICES += zbtlink_zbt-we826-e\n\ndefine Device/zbtlink_zbt-wr8305rt\n  SOC := mt7620n\n  IMAGE_SIZE := 7872k\n  DEVICE_VENDOR := Zbtlink\n  DEVICE_MODEL := ZBT-WR8305RT\n  DEVICE_PACKAGES := kmod-usb2 kmod-usb-ohci\n  SUPPORTED_DEVICES += zbt-wr8305rt\nendef\nTARGET_DEVICES += zbtlink_zbt-wr8305rt\n\ndefine Device/zte_q7\n  SOC := mt7620a\n  IMAGE_SIZE := 7872k\n  DEVICE_VENDOR := ZTE\n  DEVICE_MODEL := Q7\n  DEVICE_PACKAGES := kmod-usb2 kmod-usb-ohci\n  SUPPORTED_DEVICES += zte-q7\nendef\nTARGET_DEVICES += zte_q7\n\ndefine Device/zyxel_keenetic-omni\n  SOC := mt7620n\n  IMAGE_SIZE := 7872k\n  DEVICE_VENDOR := ZyXEL\n  DEVICE_MODEL := Keenetic Omni\n  DEVICE_PACKAGES := kmod-usb2 kmod-usb-ohci kmod-usb-ledtrig-usbport\n  IMAGES += factory.bin\n  IMAGE/factory.bin := $$(sysupgrade_bin) | pad-to 64k | check-size | \\\n\tzyimage -d 4882 -v \"ZyXEL Keenetic Omni\"\n  SUPPORTED_DEVICES += kn_rc\nendef\nTARGET_DEVICES += zyxel_keenetic-omni\n\ndefine Device/zyxel_keenetic-omni-ii\n  SOC := mt7620n\n  IMAGE_SIZE := 7872k\n  DEVICE_VENDOR := ZyXEL\n  DEVICE_MODEL := Keenetic Omni II\n  DEVICE_PACKAGES := kmod-usb2 kmod-usb-ohci kmod-usb-ledtrig-usbport\n  IMAGES += factory.bin\n  IMAGE/factory.bin := $$(sysupgrade_bin) | pad-to 64k | check-size | \\\n\tzyimage -d 2102034 -v \"ZyXEL Keenetic Omni II\"\n  SUPPORTED_DEVICES += kn_rf\nendef\nTARGET_DEVICES += zyxel_keenetic-omni-ii\n\ndefine Device/zyxel_keenetic-viva\n  SOC := mt7620a\n  IMAGE_SIZE := 16064k\n  DEVICE_VENDOR := ZyXEL\n  DEVICE_MODEL := Keenetic Viva\n  DEVICE_PACKAGES := kmod-usb2 kmod-usb-ohci kmod-usb-ledtrig-usbport \\\n\tkmod-switch-rtl8366-smi kmod-switch-rtl8367b\n  IMAGES += factory.bin\n  IMAGE/factory.bin := $$(sysupgrade_bin) | pad-to 64k | check-size | \\\n\tzyimage -d 8997 -v \"ZyXEL Keenetic Viva\"\n  SUPPORTED_DEVICES += kng_rc\nendef\nTARGET_DEVICES += zyxel_keenetic-viva\n"
  },
  {
    "path": "target/linux/ramips/image/mt7621.mk",
    "content": "#\n# MT7621 Profiles\n#\n\ninclude ./common-tp-link.mk\n\nDEFAULT_SOC := mt7621\n\nKERNEL_DTB += -d21\nDEVICE_VARS += ELECOM_HWNAME LINKSYS_HWNAME\n\nifdef CONFIG_LINUX_5_10\n  DTS_CPPFLAGS += -DDTS_LEGACY\nendif\n\ndefine Build/beeline-trx\n\techo -ne \"hsqs\" > $@.hsqs\n\t$(STAGING_DIR_HOST)/bin/otrx create $@.trx -M 0x746f435d -f $@ \\\n\t\t-a 0x20000 -b 0x420000 -f $@.hsqs -a 1000\n\tmv $@.trx $@\n\tdd if=/dev/zero bs=1024 count=1 >> $@.tail\n\techo -ne \"HDR0\" | dd of=$@.tail bs=1 seek=$$((0x10c)) count=4 \\\n\t\tconv=notrunc 2>/dev/null\n\tdd if=$@.tail >> $@ 2>/dev/null\n\trm $@.hsqs $@.tail\nendef\n\ndefine Build/gemtek-trailer\n\tprintf \"%s%08X\" \".GEMTEK.\" \"$$(cksum $@ | cut -d ' ' -f1)\" >> $@\nendef\n\ndefine Build/iodata-factory\n\t$(eval fw_size=$(word 1,$(1)))\n\t$(eval fw_type=$(word 2,$(1)))\n\t$(eval product=$(word 3,$(1)))\n\t$(eval factory_bin=$(word 4,$(1)))\n\tif [ -e $(KDIR)/tmp/$(KERNEL_INITRAMFS_IMAGE) -a \"$$(stat -c%s $@)\" -lt \"$(fw_size)\" ]; then \\\n\t\t$(CP) $(KDIR)/tmp/$(KERNEL_INITRAMFS_IMAGE) $(factory_bin); \\\n\t\t$(STAGING_DIR_HOST)/bin/mksenaofw \\\n\t\t\t-r 0x30a -p $(product) -t $(fw_type) \\\n\t\t\t-e $(factory_bin) -o $(factory_bin).new; \\\n\t\tmv $(factory_bin).new $(factory_bin); \\\n\t\t$(CP) $(factory_bin) $(BIN_DIR)/; \\\n\telse \\\n\t\techo \"WARNING: initramfs kernel image too big, cannot generate factory image (actual $$(stat -c%s $@); max $(fw_size))\" >&2; \\\n\tfi\nendef\n\ndefine Build/iodata-mstc-header\n\t( \\\n\t\tdata_size_crc=\"$$(dd if=$@ ibs=64 skip=1 2>/dev/null | gzip -c | \\\n\t\t\ttail -c 8 | od -An -tx8 --endian little | tr -d ' \\n')\"; \\\n\t\techo -ne \"$$(echo $$data_size_crc | sed 's/../\\\\x&/g')\" | \\\n\t\t\tdd of=$@ bs=8 count=1 seek=7 conv=notrunc 2>/dev/null; \\\n\t)\n\tdd if=/dev/zero of=$@ bs=4 count=1 seek=1 conv=notrunc 2>/dev/null\n\t( \\\n\t\theader_crc=\"$$(dd if=$@ bs=64 count=1 2>/dev/null | gzip -c | \\\n\t\t\ttail -c 8 | od -An -N4 -tx4 --endian little | tr -d ' \\n')\"; \\\n\t\techo -ne \"$$(echo $$header_crc | sed 's/../\\\\x&/g')\" | \\\n\t\t\tdd of=$@ bs=4 count=1 seek=1 conv=notrunc 2>/dev/null; \\\n\t)\nendef\n\ndefine Build/ubnt-erx-factory-image\n\tif [ -e $(KDIR)/tmp/$(KERNEL_INITRAMFS_IMAGE) -a \"$$(stat -c%s $@)\" -lt \"$(KERNEL_SIZE)\" ]; then \\\n\t\techo '21001:7' > $(1).compat; \\\n\t\t$(TAR) -cf $(1) --transform='s/^.*/compat/' $(1).compat; \\\n\t\t\\\n\t\t$(TAR) -rf $(1) --transform='s/^.*/vmlinux.tmp/' $(KDIR)/tmp/$(KERNEL_INITRAMFS_IMAGE); \\\n\t\t$(MKHASH) md5 $(KDIR)/tmp/$(KERNEL_INITRAMFS_IMAGE) > $(1).md5; \\\n\t\t$(TAR) -rf $(1) --transform='s/^.*/vmlinux.tmp.md5/' $(1).md5; \\\n\t\t\\\n\t\techo \"dummy\" > $(1).rootfs; \\\n\t\t$(TAR) -rf $(1) --transform='s/^.*/squashfs.tmp/' $(1).rootfs; \\\n\t\t\\\n\t\t$(MKHASH) md5 $(1).rootfs > $(1).md5; \\\n\t\t$(TAR) -rf $(1) --transform='s/^.*/squashfs.tmp.md5/' $(1).md5; \\\n\t\t\\\n\t\techo '$(BOARD) $(VERSION_CODE) $(VERSION_NUMBER)' > $(1).version; \\\n\t\t$(TAR) -rf $(1) --transform='s/^.*/version.tmp/' $(1).version; \\\n\t\t\\\n\t\t$(CP) $(1) $(BIN_DIR)/; \\\n\telse \\\n\t\techo \"WARNING: initramfs kernel image too big, cannot generate factory image (actual $$(stat -c%s $@); max $(KERNEL_SIZE))\" >&2; \\\n\tfi\nendef\n\ndefine Build/zytrx-header\n\t$(eval board=$(word 1,$(1)))\n\t$(eval version=$(word 2,$(1)))\n\t$(STAGING_DIR_HOST)/bin/zytrx -B '$(board)' -v '$(version)' -i $@ -o $@.new\n\tmv $@.new $@\nendef\n\ndefine Device/dsa-migration\n  DEVICE_COMPAT_VERSION := 1.1\n  DEVICE_COMPAT_MESSAGE := Config cannot be migrated from swconfig to DSA\nendef\n\ndefine Device/adslr_g7\n  $(Device/dsa-migration)\n  IMAGE_SIZE := 16064k\n  DEVICE_VENDOR := ADSLR\n  DEVICE_MODEL := G7\n  DEVICE_PACKAGES := kmod-mt7615e kmod-mt7615-firmware\nendef\nTARGET_DEVICES += adslr_g7\n\ndefine Device/afoundry_ew1200\n  $(Device/dsa-migration)\n  IMAGE_SIZE := 16064k\n  DEVICE_VENDOR := AFOUNDRY\n  DEVICE_MODEL := EW1200\n  DEVICE_PACKAGES := kmod-ata-ahci kmod-mt76x2 kmod-mt7603 kmod-usb3 \\\n\tkmod-usb-ledtrig-usbport\n  SUPPORTED_DEVICES += ew1200\nendef\nTARGET_DEVICES += afoundry_ew1200\n\ndefine Device/alfa-network_quad-e4g\n  $(Device/dsa-migration)\n  IMAGE_SIZE := 16064k\n  DEVICE_VENDOR := ALFA Network\n  DEVICE_MODEL := Quad-E4G\n  DEVICE_PACKAGES := kmod-ata-ahci kmod-sdhci-mt7620 kmod-usb3 uboot-envtools \\\n\t-wpad-basic-wolfssl\n  SUPPORTED_DEVICES += quad-e4g\nendef\nTARGET_DEVICES += alfa-network_quad-e4g\n\ndefine Device/ampedwireless_ally_common\n  $(Device/dsa-migration)\n  DEVICE_VENDOR := Amped Wireless\n  DEVICE_PACKAGES := kmod-mt7615e kmod-mt7615-firmware uboot-envtools\n  IMAGE_SIZE := 32768k\n  KERNEL_SIZE := 4096k\n  BLOCKSIZE := 128k\n  PAGESIZE := 2048\n  UBINIZE_OPTS := -E 5\n  KERNEL_INITRAMFS := $(KERNEL_DTB) | uImage lzma -n 'flashable-initramfs' |\\\n\tedimax-header -s CSYS -m RN68 -f 0x001c0000 -S 0x01100000\n  IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata\nendef\n\ndefine Device/ampedwireless_ally-r1900k\n  $(Device/ampedwireless_ally_common)\n  DEVICE_MODEL := ALLY-R1900K\n  DEVICE_PACKAGES += kmod-usb3\nendef\nTARGET_DEVICES += ampedwireless_ally-r1900k\n\ndefine Device/ampedwireless_ally-00x19k\n  $(Device/ampedwireless_ally_common)\n  DEVICE_MODEL := ALLY-00X19K\nendef\nTARGET_DEVICES += ampedwireless_ally-00x19k\n\ndefine Device/asiarf_ap7621-001\n  $(Device/dsa-migration)\n  IMAGE_SIZE := 16000k\n  DEVICE_VENDOR := AsiaRF\n  DEVICE_MODEL := AP7621-001\n  DEVICE_PACKAGES := kmod-sdhci-mt7620 kmod-mt76x2 kmod-usb3 -wpad-basic-wolfssl\nendef\nTARGET_DEVICES += asiarf_ap7621-001\n\ndefine Device/asiarf_ap7621-nv1\n  $(Device/dsa-migration)\n  IMAGE_SIZE := 16000k\n  DEVICE_VENDOR := AsiaRF\n  DEVICE_MODEL := AP7621-NV1\n  DEVICE_PACKAGES := kmod-sdhci-mt7620 kmod-mt76x2 kmod-usb3 -wpad-basic-wolfssl\nendef\nTARGET_DEVICES += asiarf_ap7621-nv1\n\ndefine Device/asus_rt-ac57u\n  $(Device/dsa-migration)\n  DEVICE_VENDOR := ASUS\n  DEVICE_MODEL := RT-AC57U\n  DEVICE_ALT0_VENDOR := ASUS\n  DEVICE_ALT0_MODEL := RT-AC1200GU\n  IMAGE_SIZE := 16064k\n  DEVICE_PACKAGES := kmod-mt7603 kmod-mt76x2 kmod-usb3 \\\n\tkmod-usb-ledtrig-usbport\nendef\nTARGET_DEVICES += asus_rt-ac57u\n\ndefine Device/asus_rt-ac65p\n  $(Device/dsa-migration)\n  DEVICE_VENDOR := ASUS\n  DEVICE_MODEL := RT-AC65P\n  IMAGE_SIZE := 51200k\n  UBINIZE_OPTS := -E 5\n  BLOCKSIZE := 128k\n  PAGESIZE := 2048\n  KERNEL_SIZE := 4096k\n  IMAGES += factory.bin\n  IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata\n  IMAGE/factory.bin := append-kernel | pad-to $$(KERNEL_SIZE) | append-ubi | \\\n\tcheck-size\n  DEVICE_PACKAGES := kmod-usb3 kmod-mt7615e kmod-mt7615-firmware uboot-envtools\nendef\nTARGET_DEVICES += asus_rt-ac65p\n\ndefine Device/asus_rt-ac85p\n  $(Device/dsa-migration)\n  DEVICE_VENDOR := ASUS\n  DEVICE_MODEL := RT-AC85P\n  IMAGE_SIZE := 51200k\n  UBINIZE_OPTS := -E 5\n  BLOCKSIZE := 128k\n  PAGESIZE := 2048\n  KERNEL_SIZE := 4096k\n  IMAGES += factory.bin\n  IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata\n  IMAGE/factory.bin := append-kernel | pad-to $$(KERNEL_SIZE) | append-ubi | \\\n\tcheck-size\n  DEVICE_PACKAGES := kmod-usb3 kmod-mt7615e kmod-mt7615-firmware uboot-envtools\nendef\nTARGET_DEVICES += asus_rt-ac85p\n\ndefine Device/asus_rt-n56u-b1\n  $(Device/dsa-migration)\n  DEVICE_VENDOR := ASUS\n  DEVICE_MODEL := RT-N56U\n  DEVICE_VARIANT := B1\n  IMAGE_SIZE := 16064k\n  DEVICE_PACKAGES := kmod-mt7603 kmod-mt76x2 kmod-usb3 \\\n\tkmod-usb-ledtrig-usbport\nendef\nTARGET_DEVICES += asus_rt-n56u-b1\n\ndefine Device/beeline_smartbox-flash\n  $(Device/dsa-migration)\n  $(Device/uimage-lzma-loader)\n  DEVICE_VENDOR := Beeline\n  DEVICE_MODEL := SmartBox Flash\n  IMAGE_SIZE := 32768k\n  KERNEL_SIZE := 4352k\n  UBINIZE_OPTS := -E 5\n  BLOCKSIZE := 128k\n  PAGESIZE := 2048\n  KERNEL := kernel-bin | append-dtb | lzma | loader-kernel | \\\n\tuImage none | beeline-trx | pad-to $$(KERNEL_SIZE)\n  KERNEL_INITRAMFS := kernel-bin | append-dtb | lzma | loader-kernel | \\\n\tuImage none\n  IMAGES += factory.trx\n  IMAGE/factory.trx := append-kernel | append-ubi | check-size\n  IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata\n  DEVICE_PACKAGES := kmod-usb3 kmod-mt7615e kmod-mt7615-firmware \\\n\tuboot-envtools\nendef\nTARGET_DEVICES += beeline_smartbox-flash\n\ndefine Device/buffalo_wsr-1166dhp\n  $(Device/dsa-migration)\n  $(Device/uimage-lzma-loader)\n  IMAGE/sysupgrade.bin := trx | pad-rootfs | append-metadata\n  IMAGE_SIZE := 15936k\n  DEVICE_VENDOR := Buffalo\n  DEVICE_MODEL := WSR-1166DHP\n  DEVICE_PACKAGES := kmod-mt7603 kmod-mt76x2\n  SUPPORTED_DEVICES += wsr-1166\nendef\nTARGET_DEVICES += buffalo_wsr-1166dhp\n\ndefine Device/buffalo_wsr-2533dhpl\n  $(Device/dsa-migration)\n  $(Device/uimage-lzma-loader)\n  IMAGE_SIZE := 7936k\n  DEVICE_VENDOR := Buffalo\n  DEVICE_MODEL := WSR-2533DHPL\n  DEVICE_ALT0_VENDOR := Buffalo\n  DEVICE_ALT0_MODEL := WSR-2533DHP\n  IMAGE/sysupgrade.bin := trx | pad-rootfs | append-metadata\n  DEVICE_PACKAGES := kmod-mt7615e kmod-mt7615-firmware\nendef\nTARGET_DEVICES += buffalo_wsr-2533dhpl\n\ndefine Device/buffalo_wsr-600dhp\n  $(Device/dsa-migration)\n  IMAGE_SIZE := 16064k\n  DEVICE_VENDOR := Buffalo\n  DEVICE_MODEL := WSR-600DHP\n  DEVICE_PACKAGES := kmod-mt7603 kmod-rt2800-pci\n  SUPPORTED_DEVICES += wsr-600\nendef\nTARGET_DEVICES += buffalo_wsr-600dhp\n\ndefine Device/bolt_arion\n  $(Device/dsa-migration)\n  $(Device/uimage-lzma-loader)\n  IMAGE_SIZE := 32448k\n  DEVICE_VENDOR := BOLT\n  DEVICE_MODEL := Arion\n  DEVICE_PACKAGES := kmod-mt7603 kmod-mt76x2 uboot-envtools\nendef\nTARGET_DEVICES += bolt_arion\n\ndefine Device/cudy_wr1300\n  $(Device/dsa-migration)\n  IMAGE_SIZE := 15872k\n  DEVICE_VENDOR := Cudy\n  DEVICE_MODEL := WR1300\n  DEVICE_PACKAGES := kmod-mt7603 kmod-mt76x2 kmod-usb2 kmod-usb3 \\\n\tkmod-usb-ledtrig-usbport\nendef\nTARGET_DEVICES += cudy_wr1300\n\ndefine Device/cudy_wr2100\n  $(Device/dsa-migration)\n  DEVICE_VENDOR := Cudy\n  DEVICE_MODEL := WR2100\n  IMAGE_SIZE := 15872k\n  UIMAGE_NAME := R11\n  DEVICE_PACKAGES := kmod-mt7603 kmod-mt7615e kmod-mt7615-firmware\nendef\nTARGET_DEVICES += cudy_wr2100\n\ndefine Device/cudy_x6\n  $(Device/dsa-migration)\n  IMAGE_SIZE := 32256k\n  DEVICE_VENDOR := Cudy\n  DEVICE_MODEL := X6\n  UIMAGE_NAME := R13\n  DEVICE_PACKAGES := kmod-mt7915e\nendef\nTARGET_DEVICES += cudy_x6\n\ndefine Device/dlink_dir-8xx-a1\n  $(Device/dsa-migration)\n  IMAGE_SIZE := 16000k\n  DEVICE_VENDOR := D-Link\n  DEVICE_PACKAGES := kmod-mt7615e kmod-mt7615-firmware\n  KERNEL := $$(KERNEL) | uimage-sgehdr\n  IMAGES += factory.bin\n  IMAGE/sysupgrade.bin := append-kernel | append-rootfs | pad-rootfs | \\\n\tcheck-size | append-metadata\n  IMAGE/factory.bin := append-kernel | append-rootfs | check-size\nendef\n\ndefine Device/dlink_dir-8xx-r1\n  $(Device/dsa-migration)\n  IMAGE_SIZE := 16064k\n  DEVICE_VENDOR := D-Link\n  DEVICE_PACKAGES := kmod-mt7615e kmod-mt7615-firmware\n  KERNEL_INITRAMFS := $$(KERNEL)\n  IMAGE/sysupgrade.bin := append-kernel | append-rootfs | pad-rootfs | \\\n\tcheck-size | append-metadata\nendef\n\ndefine Device/dlink_dir-xx60-a1\n  $(Device/dsa-migration)\n  BLOCKSIZE := 128k\n  PAGESIZE := 2048\n  KERNEL_SIZE := 4096k\n  IMAGE_SIZE := 40960k\n  UBINIZE_OPTS := -E 5\n  DEVICE_VENDOR := D-Link\n  DEVICE_PACKAGES := kmod-mt7615e kmod-mt7615-firmware kmod-usb3 \\\n\tkmod-usb-ledtrig-usbport\n  KERNEL := $$(KERNEL) | uimage-sgehdr\n  IMAGES += factory.bin\n  IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata\n  IMAGE/factory.bin := append-kernel | pad-to $$(KERNEL_SIZE) | append-ubi | \\\n\tcheck-size\nendef\n\ndefine Device/dlink_dir-1960-a1\n  $(Device/dlink_dir-xx60-a1)\n  DEVICE_MODEL := DIR-1960\n  DEVICE_VARIANT := A1\nendef\nTARGET_DEVICES += dlink_dir-1960-a1\n\ndefine Device/dlink_dir-2640-a1\n  $(Device/dlink_dir-xx60-a1)\n  DEVICE_MODEL := DIR-2640\n  DEVICE_VARIANT := A1\nendef\nTARGET_DEVICES += dlink_dir-2640-a1\n\ndefine Device/dlink_dir-2660-a1\n  $(Device/dlink_dir-xx60-a1)\n  DEVICE_MODEL := DIR-2660\n  DEVICE_VARIANT := A1\nendef\nTARGET_DEVICES += dlink_dir-2660-a1\n\ndefine Device/dlink_dir-853-a3\n  $(Device/dlink_dir-xx60-a1)\n  DEVICE_MODEL := DIR-853\n  DEVICE_VARIANT := A3\nendef\nTARGET_DEVICES += dlink_dir-853-a3\n\ndefine Device/dlink_dir-853-r1\n  $(Device/dlink_dir-8xx-r1)\n  DEVICE_MODEL := DIR-853\n  DEVICE_VARIANT := R1\n  DEVICE_PACKAGES += kmod-usb3 kmod-usb-ledtrig-usbport\nendef\nTARGET_DEVICES += dlink_dir-853-r1\n\ndefine Device/dlink_dir-860l-b1\n  $(Device/dsa-migration)\n  $(Device/seama)\n  SEAMA_SIGNATURE := wrgac13_dlink.2013gui_dir860lb\n  LOADER_TYPE := bin\n  KERNEL := kernel-bin | append-dtb | lzma | loader-kernel | relocate-kernel | \\\n\tlzma -a0 | uImage lzma\n  IMAGE_SIZE := 16064k\n  DEVICE_VENDOR := D-Link\n  DEVICE_MODEL := DIR-860L\n  DEVICE_VARIANT := B1\n  DEVICE_PACKAGES := kmod-mt76x2 kmod-usb3 kmod-usb-ledtrig-usbport\n  SUPPORTED_DEVICES += dir-860l-b1\nendef\nTARGET_DEVICES += dlink_dir-860l-b1\n\ndefine Device/dlink_dir-867-a1\n  $(Device/dlink_dir-8xx-a1)\n  DEVICE_MODEL := DIR-867\n  DEVICE_VARIANT := A1\nendef\nTARGET_DEVICES += dlink_dir-867-a1\n\ndefine Device/dlink_dir-878-a1\n  $(Device/dlink_dir-8xx-a1)\n  DEVICE_MODEL := DIR-878\n  DEVICE_VARIANT := A1\nendef\nTARGET_DEVICES += dlink_dir-878-a1\n\ndefine Device/dlink_dir-878-r1\n  $(Device/dlink_dir-8xx-r1)\n  DEVICE_MODEL := DIR-878\n  DEVICE_VARIANT := R1\n  IMAGES += factory.bin\n  IMAGE/factory.bin := append-kernel | append-rootfs | check-size | \\\n\tsign-dlink-ru 57c5375741c30ca9ebcb36713db4ba51 \\\n\tab0dff19af8842cdb70a86b4b68d23f7\nendef\nTARGET_DEVICES += dlink_dir-878-r1\n\ndefine Device/dlink_dir-882-a1\n  $(Device/dlink_dir-8xx-a1)\n  DEVICE_MODEL := DIR-882\n  DEVICE_VARIANT := A1\n  DEVICE_PACKAGES += kmod-usb3 kmod-usb-ledtrig-usbport\nendef\nTARGET_DEVICES += dlink_dir-882-a1\n\ndefine Device/dlink_dir-882-r1\n  $(Device/dlink_dir-8xx-r1)\n  DEVICE_MODEL := DIR-882\n  DEVICE_VARIANT := R1\n  DEVICE_PACKAGES += kmod-usb3 kmod-usb-ledtrig-usbport\n  IMAGES += factory.bin\n  IMAGE/factory.bin := append-kernel | append-rootfs | check-size | \\\n\tsign-dlink-ru 57c5375741c30ca9ebcb36713db4ba51 \\\n\tab0dff19af8842cdb70a86b4b68d23f7\nendef\nTARGET_DEVICES += dlink_dir-882-r1\n\ndefine Device/dual-q_h721\n  $(Device/dsa-migration)\n  $(Device/uimage-lzma-loader)\n  IMAGE_SIZE := 16064k\n  DEVICE_VENDOR := Dual-Q\n  DEVICE_MODEL := H721\n  DEVICE_PACKAGES := kmod-ata-ahci kmod-sdhci-mt7620 kmod-usb3 -wpad-basic-wolfssl\nendef\nTARGET_DEVICES += dual-q_h721\n\ndefine Device/d-team_newifi-d2\n  $(Device/dsa-migration)\n  $(Device/uimage-lzma-loader)\n  IMAGE_SIZE := 32448k\n  DEVICE_VENDOR := Newifi\n  DEVICE_MODEL := D2\n  DEVICE_PACKAGES := kmod-mt7603 kmod-mt76x2 kmod-usb3 \\\n\tkmod-usb-ledtrig-usbport\nendef\nTARGET_DEVICES += d-team_newifi-d2\n\ndefine Device/d-team_pbr-m1\n  $(Device/dsa-migration)\n  IMAGE_SIZE := 32448k\n  DEVICE_VENDOR := PandoraBox\n  DEVICE_MODEL := PBR-M1\n  DEVICE_PACKAGES := kmod-ata-ahci kmod-mt7603 kmod-mt76x2 kmod-sdhci-mt7620 \\\n\tkmod-usb3 kmod-usb-ledtrig-usbport\n  SUPPORTED_DEVICES += pbr-m1\nendef\nTARGET_DEVICES += d-team_pbr-m1\n\ndefine Device/edimax_ra21s\n  $(Device/dsa-migration)\n  $(Device/uimage-lzma-loader)\n  IMAGE_SIZE := 16064k\n  DEVICE_VENDOR := Edimax\n  DEVICE_MODEL := RA21S\n  DEVICE_ALT0_VENDOR := Edimax\n  DEVICE_ALT0_MODEL := Gemini RA21S\n  IMAGES += factory.bin\n  IMAGE/factory.bin := $$(sysupgrade_bin) | check-size | \\\n\telx-header 02020040 8844A2D168B45A2D\n  DEVICE_PACKAGES := kmod-mt7615e kmod-mt7615-firmware\nendef\nTARGET_DEVICES += edimax_ra21s\n\ndefine Device/edimax_re23s\n  $(Device/dsa-migration)\n  $(Device/uimage-lzma-loader)\n  IMAGE_SIZE := 15680k\n  DEVICE_VENDOR := Edimax\n  DEVICE_MODEL := RE23S\n  DEVICE_ALT0_VENDOR := Edimax\n  DEVICE_ALT0_MODEL := Gemini RE23S\n  IMAGE/sysupgrade.bin := append-kernel | append-rootfs | \\\n\tedimax-header -s CSYS -m RN76 -f 0x70000 -S 0x01100000 | pad-rootfs | \\\n\tcheck-size | append-metadata\n  IMAGES += factory.bin\n  IMAGE/factory.bin := append-kernel | append-rootfs | \\\n\tedimax-header -s CSYS -m RN76 -f 0x70000 -S 0x01100000 | pad-rootfs | \\\n\tcheck-size\n  DEVICE_PACKAGES := kmod-mt7615e kmod-mt7615-firmware\nendef\nTARGET_DEVICES += edimax_re23s\n\ndefine Device/edimax_rg21s\n  $(Device/dsa-migration)\n  $(Device/uimage-lzma-loader)\n  IMAGE_SIZE := 16064k\n  DEVICE_VENDOR := Edimax\n  DEVICE_MODEL := Gemini AC2600 RG21S\n  IMAGES += factory.bin\n  IMAGE/factory.bin := $$(sysupgrade_bin) | check-size | \\\n\telx-header 02020038 8844A2D168B45A2D\n  DEVICE_PACKAGES := kmod-mt7615e kmod-mt7615-firmware\nendef\nTARGET_DEVICES += edimax_rg21s\n\ndefine Device/elecom_wrc-1167ghbk2-s\n  $(Device/dsa-migration)\n  IMAGE_SIZE := 15488k\n  DEVICE_VENDOR := ELECOM\n  DEVICE_MODEL := WRC-1167GHBK2-S\n  IMAGES += factory.bin\n  IMAGE/factory.bin := $$(sysupgrade_bin) | check-size | \\\n\telecom-wrc-gs-factory WRC-1167GHBK2-S 0.00\n  DEVICE_PACKAGES := kmod-mt7615e kmod-mt7615-firmware\nendef\nTARGET_DEVICES += elecom_wrc-1167ghbk2-s\n\ndefine Device/elecom_wrc-gs\n  $(Device/dsa-migration)\n  $(Device/uimage-lzma-loader)\n  DEVICE_VENDOR := ELECOM\n  IMAGES += factory.bin\n  IMAGE/factory.bin := $$(sysupgrade_bin) | check-size | \\\n\telecom-wrc-gs-factory $$$$(ELECOM_HWNAME) 0.00 -N | \\\n\tappend-string MT7621_ELECOM_$$$$(ELECOM_HWNAME)\n  DEVICE_PACKAGES := kmod-mt7615e kmod-mt7615-firmware\nendef\n\ndefine Device/elecom_wrc-1167gs2-b\n  $(Device/elecom_wrc-gs)\n  IMAGE_SIZE := 11264k\n  DEVICE_MODEL := WRC-1167GS2-B\n  ELECOM_HWNAME := WRC-1167GS2\nendef\nTARGET_DEVICES += elecom_wrc-1167gs2-b\n\ndefine Device/elecom_wrc-1167gst2\n  $(Device/elecom_wrc-gs)\n  IMAGE_SIZE := 24576k\n  DEVICE_MODEL := WRC-1167GST2\n  ELECOM_HWNAME := WRC-1167GST2\nendef\nTARGET_DEVICES += elecom_wrc-1167gst2\n\ndefine Device/elecom_wrc-1750gs\n  $(Device/elecom_wrc-gs)\n  IMAGE_SIZE := 11264k\n  DEVICE_MODEL := WRC-1750GS\n  ELECOM_HWNAME := WRC-1750GS\nendef\nTARGET_DEVICES += elecom_wrc-1750gs\n\ndefine Device/elecom_wrc-1750gst2\n  $(Device/elecom_wrc-gs)\n  IMAGE_SIZE := 24576k\n  DEVICE_MODEL := WRC-1750GST2\n  ELECOM_HWNAME := WRC-1750GST2\nendef\nTARGET_DEVICES += elecom_wrc-1750gst2\n\ndefine Device/elecom_wrc-1750gsv\n  $(Device/elecom_wrc-gs)\n  IMAGE_SIZE := 11264k\n  DEVICE_MODEL := WRC-1750GSV\n  ELECOM_HWNAME := WRC-1750GSV\nendef\nTARGET_DEVICES += elecom_wrc-1750gsv\n\ndefine Device/elecom_wrc-1900gst\n  $(Device/elecom_wrc-gs)\n  IMAGE_SIZE := 11264k\n  DEVICE_MODEL := WRC-1900GST\n  ELECOM_HWNAME := WRC-1900GST\nendef\nTARGET_DEVICES += elecom_wrc-1900gst\n\ndefine Device/elecom_wrc-2533ghbk-i\n  $(Device/dsa-migration)\n  $(Device/uimage-lzma-loader)\n  DEVICE_VENDOR := ELECOM\n  DEVICE_MODEL := WRC-2533GHBK-I\n  IMAGE_SIZE := 9856k\n  IMAGES += factory.bin\n  IMAGE/factory.bin := $$(sysupgrade_bin) | check-size | \\\n\telx-header 0107002d 8844A2D168B45A2D | \\\n\telecom-product-header WRC-2533GHBK-I\n  DEVICE_PACKAGES := kmod-mt7615e kmod-mt7615-firmware\nendef\nTARGET_DEVICES += elecom_wrc-2533ghbk-i\n\ndefine Device/elecom_wrc-2533gs2\n  $(Device/elecom_wrc-gs)\n  IMAGE_SIZE := 11264k\n  DEVICE_MODEL := WRC-2533GS2\n  ELECOM_HWNAME := WRC-2533GS2\nendef\nTARGET_DEVICES += elecom_wrc-2533gs2\n\ndefine Device/elecom_wrc-2533gst\n  $(Device/elecom_wrc-gs)\n  IMAGE_SIZE := 11264k\n  DEVICE_MODEL := WRC-2533GST\n  ELECOM_HWNAME := WRC-2533GST\nendef\nTARGET_DEVICES += elecom_wrc-2533gst\n\ndefine Device/elecom_wrc-2533gst2\n  $(Device/elecom_wrc-gs)\n  IMAGE_SIZE := 24576k\n  DEVICE_MODEL := WRC-2533GST2\n  ELECOM_HWNAME := WRC-2533GST2\nendef\nTARGET_DEVICES += elecom_wrc-2533gst2\n\ndefine Device/firefly_firewrt\n  $(Device/dsa-migration)\n  IMAGE_SIZE := 16064k\n  DEVICE_VENDOR := Firefly\n  DEVICE_MODEL := FireWRT\n  DEVICE_PACKAGES := kmod-mt76x2 kmod-usb3 kmod-usb-ledtrig-usbport\n  SUPPORTED_DEVICES += firewrt\nendef\nTARGET_DEVICES += firefly_firewrt\n\ndefine Device/gehua_ghl-r-001\n  $(Device/dsa-migration)\n  IMAGE_SIZE := 32448k\n  DEVICE_VENDOR := GeHua\n  DEVICE_MODEL := GHL-R-001\n  DEVICE_PACKAGES := kmod-mt7603 kmod-mt76x2 kmod-usb3 \\\n\tkmod-usb-ledtrig-usbport\nendef\nTARGET_DEVICES += gehua_ghl-r-001\n\ndefine Device/glinet_gl-mt1300\n  $(Device/dsa-migration)\n  IMAGE_SIZE := 32448k\n  DEVICE_VENDOR := GL.iNet\n  DEVICE_MODEL := GL-MT1300\n  DEVICE_PACKAGES := kmod-mt7615e kmod-mt7615-firmware kmod-usb3\nendef\nTARGET_DEVICES += glinet_gl-mt1300\n\ndefine Device/gnubee_gb-pc1\n  $(Device/dsa-migration)\n  DEVICE_VENDOR := GnuBee\n  DEVICE_MODEL := Personal Cloud One\n  DEVICE_PACKAGES := kmod-ata-ahci kmod-usb3 kmod-sdhci-mt7620 -wpad-basic-wolfssl\n  IMAGE_SIZE := 32448k\nendef\nTARGET_DEVICES += gnubee_gb-pc1\n\ndefine Device/gnubee_gb-pc2\n  $(Device/dsa-migration)\n  DEVICE_VENDOR := GnuBee\n  DEVICE_MODEL := Personal Cloud Two\n  DEVICE_PACKAGES := kmod-ata-ahci kmod-usb3 kmod-sdhci-mt7620 -wpad-basic-wolfssl\n  IMAGE_SIZE := 32448k\nendef\nTARGET_DEVICES += gnubee_gb-pc2\n\ndefine Device/hilink_hlk-7621a-evb\n  $(Device/dsa-migration)\n  $(Device/uimage-lzma-loader)\n  DEVICE_VENDOR := HiLink\n  DEVICE_MODEL := HLK-7621A evaluation board\n  DEVICE_PACKAGES += kmod-mt76x2 kmod-usb3\n  IMAGE_SIZE := 32448k\nendef\nTARGET_DEVICES += hilink_hlk-7621a-evb\n\ndefine Device/hiwifi_hc5962\n  $(Device/dsa-migration)\n  BLOCKSIZE := 128k\n  PAGESIZE := 2048\n  KERNEL_SIZE := 4096k\n  UBINIZE_OPTS := -E 5\n  IMAGE_SIZE := 32768k\n  IMAGES += factory.bin\n  IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata\n  IMAGE/factory.bin := append-kernel | pad-to $$(KERNEL_SIZE) | append-ubi | \\\n\tcheck-size\n  DEVICE_VENDOR := HiWiFi\n  DEVICE_MODEL := HC5962\n  DEVICE_PACKAGES := kmod-mt7603 kmod-mt76x2 kmod-usb3\nendef\nTARGET_DEVICES += hiwifi_hc5962\n\ndefine Device/humax_e10\n  $(Device/dsa-migration)\n  $(Device/uimage-lzma-loader)\n  IMAGE_SIZE := 15936k\n  DEVICE_VENDOR := HUMAX\n  DEVICE_MODEL := E10\n  DEVICE_ALT0_VENDOR := HUMAX\n  DEVICE_ALT0_MODEL := QUANTUM E10\n  IMAGE/sysupgrade.bin := append-kernel | append-rootfs | \\\n\tedimax-header -s CSYS -m EA03 -f 0x70000 -S 0x01100000 | pad-rootfs | \\\n\tcheck-size | append-metadata\n  IMAGES += factory.bin\n  IMAGE/factory.bin := append-kernel | append-rootfs | pad-rootfs | \\\n\tedimax-header -s CSYS -m EA03 -f 0x70000 -S 0x01100000 | \\\n\tcheck-size | zip upg -P f013c26cf0a320fb71d03356dcb6bb63\n  DEVICE_PACKAGES := kmod-mt7615e kmod-mt7615-firmware kmod-usb3\nendef\nTARGET_DEVICES += humax_e10\n\ndefine Device/iodata_wn-ax1167gr\n  $(Device/dsa-migration)\n  $(Device/uimage-lzma-loader)\n  IMAGE_SIZE := 15552k\n  KERNEL_INITRAMFS := $$(KERNEL) | \\\n\tiodata-factory 7864320 4 0x1055 $(KDIR)/tmp/$$(KERNEL_INITRAMFS_PREFIX)-factory.bin\n  DEVICE_VENDOR := I-O DATA\n  DEVICE_MODEL := WN-AX1167GR\n  DEVICE_PACKAGES := kmod-mt7603 kmod-mt76x2\nendef\nTARGET_DEVICES += iodata_wn-ax1167gr\n\ndefine Device/iodata_nand\n  $(Device/dsa-migration)\n  DEVICE_VENDOR := I-O DATA\n  BLOCKSIZE := 128k\n  PAGESIZE := 2048\n  UBINIZE_OPTS := -E 5\n  KERNEL_SIZE := 4096k\n  IMAGE_SIZE := 51200k\n  LOADER_TYPE := bin\n  KERNEL := kernel-bin | append-dtb | lzma | loader-kernel | lzma | uImage lzma\n  IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata\nendef\n\n# The OEM webinterface expects an kernel with initramfs which has the uImage\n# header field ih_name.\n# We don't want to set the header name field for the kernel include in the\n# sysupgrade image as well, as this image shouldn't be accepted by the OEM\n# webinterface. It will soft-brick the board.\n\ndefine Device/iodata_wn-ax1167gr2\n  $(Device/iodata_nand)\n  DEVICE_MODEL := WN-AX1167GR2\n  KERNEL_INITRAMFS := $(KERNEL_DTB) | loader-kernel | lzma | \\\n\tuImage lzma -M 0x434f4d42 -n '3.10(XBC.1)b10' | iodata-mstc-header\n  DEVICE_PACKAGES := kmod-mt7615e kmod-mt7615-firmware\nendef\nTARGET_DEVICES += iodata_wn-ax1167gr2\n\ndefine Device/iodata_wn-ax2033gr\n  $(Device/iodata_nand)\n  DEVICE_MODEL := WN-AX2033GR\n  KERNEL_INITRAMFS := $(KERNEL_DTB) | loader-kernel | lzma | \\\n\tuImage lzma -M 0x434f4d42 -n '3.10(VST.1)C10' | iodata-mstc-header\n  DEVICE_PACKAGES := kmod-mt7603 kmod-mt7615e kmod-mt7615-firmware\nendef\nTARGET_DEVICES += iodata_wn-ax2033gr\n\ndefine Device/iodata_wn-dx1167r\n  $(Device/iodata_nand)\n  DEVICE_MODEL := WN-DX1167R\n  KERNEL_INITRAMFS := $(KERNEL_DTB) | loader-kernel | lzma | \\\n\tuImage lzma -M 0x434f4d43 -n '3.10(XIK.1)b10' | iodata-mstc-header\n  DEVICE_PACKAGES := kmod-mt7615e kmod-mt7615-firmware\nendef\nTARGET_DEVICES += iodata_wn-dx1167r\n\ndefine Device/iodata_wn-dx1200gr\n  $(Device/iodata_nand)\n  DEVICE_MODEL := WN-DX1200GR\n  KERNEL_INITRAMFS := $(KERNEL_DTB) | loader-kernel | lzma | \\\n\tuImage lzma -M 0x434f4d43 -n '3.10(XIQ.0)b20' | iodata-mstc-header\n  DEVICE_PACKAGES := kmod-mt7603 kmod-mt7615e kmod-mt7663-firmware-ap\nendef\nTARGET_DEVICES += iodata_wn-dx1200gr\n\ndefine Device/iodata_wn-dx2033gr\n  $(Device/iodata_nand)\n  DEVICE_MODEL := WN-DX2033GR\n  KERNEL_INITRAMFS := $(KERNEL_DTB) | loader-kernel | lzma | \\\n\tuImage lzma -M 0x434f4d42 -n '3.10(XID.0)b30' | iodata-mstc-header\n  DEVICE_PACKAGES := kmod-mt7603 kmod-mt7615e kmod-mt7615-firmware\nendef\nTARGET_DEVICES += iodata_wn-dx2033gr\n\ndefine Device/iodata_wn-gx300gr\n  $(Device/dsa-migration)\n  $(Device/uimage-lzma-loader)\n  IMAGE_SIZE := 7616k\n  DEVICE_VENDOR := I-O DATA\n  DEVICE_MODEL := WN-GX300GR\n  DEVICE_PACKAGES := kmod-mt7603\nendef\nTARGET_DEVICES += iodata_wn-gx300gr\n\ndefine Device/iodata_wnpr2600g\n  $(Device/dsa-migration)\n  $(Device/uimage-lzma-loader)\n  DEVICE_VENDOR := I-O DATA\n  DEVICE_MODEL := WNPR2600G\n  IMAGE_SIZE := 13952k\n  IMAGES += factory.bin\n  IMAGE/factory.bin := $$(sysupgrade_bin) | check-size | \\\n\telx-header 0104003a 8844A2D168B45A2D\n  DEVICE_PACKAGES := kmod-mt7615e kmod-mt7615-firmware\nendef\nTARGET_DEVICES += iodata_wnpr2600g\n\ndefine Device/iptime_a3002mesh\n  $(Device/dsa-migration)\n  IMAGE_SIZE := 16128k\n  UIMAGE_NAME := a3002me\n  DEVICE_VENDOR := ipTIME\n  DEVICE_MODEL := A3002MESH\n  DEVICE_PACKAGES := kmod-mt7615e kmod-mt7615-firmware\nendef\nTARGET_DEVICES += iptime_a3002mesh\n\ndefine Device/iptime_a3004ns-dual\n  $(Device/dsa-migration)\n  $(Device/uimage-lzma-loader)\n  IMAGE_SIZE := 16128k\n  UIMAGE_NAME := a3004nd\n  DEVICE_VENDOR := ipTIME\n  DEVICE_MODEL := A3004NS-dual\n  DEVICE_PACKAGES := kmod-usb3 kmod-mt76x2 kmod-usb-ledtrig-usbport\nendef\nTARGET_DEVICES += iptime_a3004ns-dual\n\ndefine Device/iptime_a3004t\n  $(Device/dsa-migration)\n  $(Device/uimage-lzma-loader)\n  BLOCKSIZE := 128k\n  PAGESIZE := 2048\n  FILESYSTEMS := squashfs\n  KERNEL_SIZE := 4096k\n  IMAGE_SIZE := 129280k\n  UIMAGE_NAME := a3004t\n  UBINIZE_OPTS := -E 5\n  IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata\n  DEVICE_VENDOR := ipTIME\n  DEVICE_MODEL := A3004T\n  DEVICE_PACKAGES := kmod-mt7615e kmod-mt7615-firmware kmod-usb3\nendef\nTARGET_DEVICES += iptime_a3004t\n\ndefine Device/iptime_a6004ns-m\n  $(Device/dsa-migration)\n  IMAGE_SIZE := 16128k\n  UIMAGE_NAME := a6004nm\n  DEVICE_VENDOR := ipTIME\n  DEVICE_MODEL := A6004NS-M\n  DEVICE_PACKAGES := kmod-mt7615e kmod-mt7615-firmware kmod-usb3 \\\n\tkmod-usb-ledtrig-usbport\nendef\nTARGET_DEVICES += iptime_a6004ns-m\n\ndefine Device/iptime_a6ns-m\n  $(Device/dsa-migration)\n  IMAGE_SIZE := 16128k\n  UIMAGE_NAME := a6nm\n  DEVICE_VENDOR := ipTIME\n  DEVICE_MODEL := A6ns-M\n  DEVICE_PACKAGES := kmod-mt7615e kmod-mt7615-firmware kmod-usb3 \\\n\tkmod-usb-ledtrig-usbport\nendef\nTARGET_DEVICES += iptime_a6ns-m\n\ndefine Device/iptime_a8004t\n  $(Device/dsa-migration)\n  IMAGE_SIZE := 16128k\n  UIMAGE_NAME := a8004t\n  DEVICE_VENDOR := ipTIME\n  DEVICE_MODEL := A8004T\n  DEVICE_PACKAGES := kmod-mt7615e kmod-mt7615-firmware kmod-usb3\nendef\nTARGET_DEVICES += iptime_a8004t\n\ndefine Device/iptime_ax2004m\n  $(Device/dsa-migration)\n  BLOCKSIZE := 128k\n  PAGESIZE := 2048\n  KERNEL_SIZE := 4096k\n  IMAGE_SIZE := 121344k\n  UBINIZE_OPTS := -E 5\n  KERNEL_LOADADDR := 0x82000000\n  KERNEL := kernel-bin | relocate-kernel 0x80001000 | lzma | \\\n\tfit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb\n  IMAGES += recovery.bin\n  IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata\n  IMAGE/recovery.bin := append-kernel | pad-to $$(KERNEL_SIZE) | append-ubi | \\\n\tcheck-size | iptime-crc32 ax2004m\n  DEVICE_VENDOR := ipTIME\n  DEVICE_MODEL := AX2004M\n  DEVICE_PACKAGES := kmod-mt7915e kmod-usb3\nendef\nTARGET_DEVICES += iptime_ax2004m\n\ndefine Device/iptime_t5004\n  $(Device/dsa-migration)\n  BLOCKSIZE := 128k\n  PAGESIZE := 2048\n  KERNEL_SIZE := 4096k\n  IMAGE_SIZE := 129280k\n  UBINIZE_OPTS := -E 5\n  UIMAGE_NAME := t5004\n  IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata\n  DEVICE_VENDOR := ipTIME\n  DEVICE_MODEL := T5004\n  DEVICE_PACKAGES := -wpad-basic-wolfssl\nendef\nTARGET_DEVICES += iptime_t5004\n\ndefine Device/jcg_jhr-ac876m\n  $(Device/dsa-migration)\n  IMAGE_SIZE := 16064k\n  IMAGES += factory.bin\n  IMAGE/factory.bin := $$(sysupgrade_bin) | check-size | jcg-header 89.1\n  JCG_MAXSIZE := 16064k\n  DEVICE_VENDOR := JCG\n  DEVICE_MODEL := JHR-AC876M\n  DEVICE_PACKAGES := kmod-mt7615e kmod-mt7615-firmware kmod-usb3 \\\n\tkmod-usb-ledtrig-usbport\nendef\nTARGET_DEVICES += jcg_jhr-ac876m\n\ndefine Device/jcg_q20\n  $(Device/dsa-migration)\n  BLOCKSIZE := 128k\n  PAGESIZE := 2048\n  UBINIZE_OPTS := -E 5\n  KERNEL_SIZE := 4096k\n  IMAGE_SIZE := 91136k\n  IMAGES += factory.bin\n  IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata\n  IMAGE/factory.bin := append-kernel | pad-to $$(KERNEL_SIZE) | append-ubi | \\\n\tcheck-size\n  DEVICE_VENDOR := JCG\n  DEVICE_MODEL := Q20\n  DEVICE_PACKAGES := kmod-mt7915e uboot-envtools\nendef\nTARGET_DEVICES += jcg_q20\n\ndefine Device/jcg_y2\n  $(Device/dsa-migration)\n  $(Device/uimage-lzma-loader)\n  IMAGE_SIZE := 16064k\n  IMAGES += factory.bin\n  IMAGE/factory.bin := $$(sysupgrade_bin) | check-size | jcg-header 95.1\n  JCG_MAXSIZE := 16064k\n  DEVICE_VENDOR := JCG\n  DEVICE_MODEL := Y2\n  DEVICE_PACKAGES := kmod-mt7615e kmod-mt7615-firmware kmod-usb3\nendef\nTARGET_DEVICES += jcg_y2\n\ndefine Device/lenovo_newifi-d1\n  $(Device/dsa-migration)\n  $(Device/uimage-lzma-loader)\n  IMAGE_SIZE := 32448k\n  DEVICE_VENDOR := Newifi\n  DEVICE_MODEL := D1\n  DEVICE_PACKAGES := kmod-mt7603 kmod-mt76x2 kmod-usb3 kmod-sdhci-mt7620 \\\n\tkmod-usb-ledtrig-usbport\n  SUPPORTED_DEVICES += newifi-d1\nendef\nTARGET_DEVICES += lenovo_newifi-d1\n\ndefine Device/linksys_e5600\n  $(Device/dsa-migration)\n  $(Device/uimage-lzma-loader)\n  BLOCKSIZE := 128k\n  PAGESIZE := 2048\n  KERNEL_SIZE := 4096k\n  IMAGE_SIZE := 26624k\n  DEVICE_VENDOR := Linksys\n  DEVICE_MODEL := E5600\n  DEVICE_PACKAGES := kmod-mt7603 kmod-mt7615e kmod-mt7663-firmware-ap \\\n\tuboot-envtools\n  UBINIZE_OPTS := -E 5\n  IMAGES += factory.bin\n  IMAGE/sysupgrade.bin := sysupgrade-tar | check-size | append-metadata\n  IMAGE/factory.bin := append-kernel | pad-to $$$$(KERNEL_SIZE) | \\\n\tappend-ubi | check-size | gemtek-trailer\nendef\nTARGET_DEVICES += linksys_e5600\n\ndefine Device/linksys_ea7xxx\n  $(Device/dsa-migration)\n  $(Device/uimage-lzma-loader)\n  BLOCKSIZE := 128k\n  PAGESIZE := 2048\n  KERNEL_SIZE := 4096k\n  IMAGE_SIZE := 36864k\n  DEVICE_VENDOR := Linksys\n  DEVICE_PACKAGES := kmod-usb3 kmod-mt7615e kmod-mt7615-firmware \\\n\tuboot-envtools\n  UBINIZE_OPTS := -E 5\n  IMAGES := sysupgrade.bin factory.bin\n  IMAGE/sysupgrade.bin := sysupgrade-tar | check-size | append-metadata\n  IMAGE/factory.bin := append-kernel | pad-to $$$$(KERNEL_SIZE) | \\\n\tappend-ubi | check-size | linksys-image type=$$$$(LINKSYS_HWNAME)\nendef\n\ndefine Device/linksys_ea6350-v4\n  $(Device/linksys_ea7xxx)\n  DEVICE_MODEL := EA6350\n  DEVICE_VARIANT := v4\n  LINKSYS_HWNAME := EA6350\n  DEVICE_PACKAGES += kmod-mt7603 kmod-mt7663-firmware-ap\nendef\nTARGET_DEVICES += linksys_ea6350-v4\n\ndefine Device/linksys_ea7300-v1\n  $(Device/linksys_ea7xxx)\n  DEVICE_MODEL := EA7300\n  DEVICE_VARIANT := v1\n  LINKSYS_HWNAME := EA7300\nendef\nTARGET_DEVICES += linksys_ea7300-v1\n\ndefine Device/linksys_ea7300-v2\n  $(Device/linksys_ea7xxx)\n  DEVICE_MODEL := EA7300\n  DEVICE_VARIANT := v2\n  LINKSYS_HWNAME := EA7300v2\n  DEVICE_PACKAGES += kmod-mt7603\nendef\nTARGET_DEVICES += linksys_ea7300-v2\n\ndefine Device/linksys_ea7500-v2\n  $(Device/linksys_ea7xxx)\n  DEVICE_MODEL := EA7500\n  DEVICE_VARIANT := v2\n  LINKSYS_HWNAME := EA7500v2\nendef\nTARGET_DEVICES += linksys_ea7500-v2\n\ndefine Device/linksys_ea8100-v1\n  $(Device/linksys_ea7xxx)\n  DEVICE_MODEL := EA8100\n  DEVICE_VARIANT := v1\n  LINKSYS_HWNAME := EA8100\nendef\nTARGET_DEVICES += linksys_ea8100-v1\n\ndefine Device/linksys_ea8100-v2\n  $(Device/linksys_ea7xxx)\n  DEVICE_MODEL := EA8100\n  DEVICE_VARIANT := v2\n  LINKSYS_HWNAME := EA8100v2\nendef\nTARGET_DEVICES += linksys_ea8100-v2\n\ndefine Device/linksys_re6500\n  $(Device/dsa-migration)\n  IMAGE_SIZE := 7872k\n  DEVICE_VENDOR := Linksys\n  DEVICE_MODEL := RE6500\n  DEVICE_PACKAGES := kmod-mt76x2\n  SUPPORTED_DEVICES += re6500\nendef\nTARGET_DEVICES += linksys_re6500\n\ndefine Device/mediatek_ap-mt7621a-v60\n  $(Device/dsa-migration)\n  IMAGE_SIZE := 7872k\n  DEVICE_VENDOR := Mediatek\n  DEVICE_MODEL := AP-MT7621A-V60 EVB\n  DEVICE_PACKAGES := kmod-usb3 kmod-sdhci-mt7620 kmod-sound-mt7620 -wpad-basic-wolfssl\nendef\nTARGET_DEVICES += mediatek_ap-mt7621a-v60\n\ndefine Device/mediatek_mt7621-eval-board\n  $(Device/dsa-migration)\n  BLOCKSIZE := 64k\n  IMAGE_SIZE := 15104k\n  DEVICE_VENDOR := MediaTek\n  DEVICE_MODEL := MT7621 EVB\n  DEVICE_PACKAGES := -wpad-basic-wolfssl\n  SUPPORTED_DEVICES += mt7621\nendef\nTARGET_DEVICES += mediatek_mt7621-eval-board\n\ndefine Device/MikroTik\n  $(Device/dsa-migration)\n  DEVICE_VENDOR := MikroTik\n  BLOCKSIZE := 64k\n  IMAGE_SIZE := 16128k\n  DEVICE_PACKAGES := kmod-usb3\n  KERNEL_NAME := vmlinuz\n  KERNEL := kernel-bin | append-dtb-elf\n  IMAGE/sysupgrade.bin := append-kernel | kernel2minor -s 1024 | \\\n\tpad-to $$$$(BLOCKSIZE) | append-rootfs | pad-rootfs | check-size | \\\n\tappend-metadata\nendef\n\ndefine Device/mikrotik_routerboard-750gr3\n  $(Device/MikroTik)\n  DEVICE_MODEL := RouterBOARD 750Gr3\n  DEVICE_PACKAGES += -wpad-basic-wolfssl\n  SUPPORTED_DEVICES += mikrotik,rb750gr3\nendef\nTARGET_DEVICES += mikrotik_routerboard-750gr3\n\ndefine Device/mikrotik_routerboard-760igs\n  $(Device/MikroTik)\n  DEVICE_MODEL := RouterBOARD 760iGS\n  DEVICE_PACKAGES += kmod-sfp -wpad-basic-wolfssl\nendef\nTARGET_DEVICES += mikrotik_routerboard-760igs\n\ndefine Device/mikrotik_routerboard-m11g\n  $(Device/MikroTik)\n  DEVICE_MODEL := RouterBOARD M11G\n  DEVICE_PACKAGES := -wpad-basic-wolfssl\n  SUPPORTED_DEVICES += mikrotik,rbm11g\nendef\nTARGET_DEVICES += mikrotik_routerboard-m11g\n\ndefine Device/mikrotik_routerboard-m33g\n  $(Device/MikroTik)\n  DEVICE_MODEL := RouterBOARD M33G\n  DEVICE_PACKAGES := -wpad-basic-wolfssl\n  SUPPORTED_DEVICES += mikrotik,rbm33g\nendef\nTARGET_DEVICES += mikrotik_routerboard-m33g\n\ndefine Device/mqmaker_witi\n  $(Device/dsa-migration)\n  $(Device/uimage-lzma-loader)\n  IMAGE_SIZE := 16064k\n  DEVICE_VENDOR := MQmaker\n  DEVICE_MODEL := WiTi\n  DEVICE_PACKAGES := kmod-ata-ahci kmod-mt76x2 kmod-sdhci-mt7620 kmod-usb3 \\\n\tkmod-usb-ledtrig-usbport\n  SUPPORTED_DEVICES += witi mqmaker,witi-256m mqmaker,witi-512m\nendef\nTARGET_DEVICES += mqmaker_witi\n\ndefine Device/mtc_wr1201\n  $(Device/dsa-migration)\n  $(Device/uimage-lzma-loader)\n  IMAGE_SIZE := 16000k\n  DEVICE_VENDOR := MTC\n  DEVICE_MODEL := Wireless Router WR1201\n  KERNEL_INITRAMFS := $(KERNEL_DTB) | uImage lzma -n 'WR1201_8_128'\n  DEVICE_PACKAGES := kmod-sdhci-mt7620 kmod-mt76x2 kmod-usb3 \\\n\tkmod-usb-ledtrig-usbport\nendef\nTARGET_DEVICES += mtc_wr1201\n\ndefine Device/netgear_ex6150\n  $(Device/dsa-migration)\n  DEVICE_VENDOR := NETGEAR\n  DEVICE_MODEL := EX6150\n  DEVICE_PACKAGES := kmod-mt76x2\n  NETGEAR_BOARD_ID := U12H318T00_NETGEAR\n  IMAGE_SIZE := 14848k\n  IMAGES += factory.chk\n  IMAGE/factory.chk := $$(sysupgrade_bin) | check-size | netgear-chk\nendef\nTARGET_DEVICES += netgear_ex6150\n\ndefine Device/netgear_sercomm_nand\n  $(Device/dsa-migration)\n  $(Device/uimage-lzma-loader)\n  BLOCKSIZE := 128k\n  PAGESIZE := 2048\n  KERNEL_SIZE := 4096k\n  UBINIZE_OPTS := -E 5\n  IMAGES += factory.img kernel.bin rootfs.bin\n  IMAGE/factory.img := pad-extra 2048k | append-kernel | pad-to 6144k | \\\n\tappend-ubi | pad-to $$$$(BLOCKSIZE) | sercom-footer | pad-to 128 | \\\n\tzip $$$$(SERCOMM_HWNAME).bin | sercom-seal\n  IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata\n  IMAGE/kernel.bin := append-kernel\n  IMAGE/rootfs.bin := append-ubi | check-size\n  DEVICE_VENDOR := NETGEAR\n  DEVICE_PACKAGES := kmod-mt7603 kmod-usb3 kmod-usb-ledtrig-usbport\nendef\n\ndefine Device/netgear_r6220\n  $(Device/netgear_sercomm_nand)\n  DEVICE_MODEL := R6220\n  SERCOMM_HWNAME := R6220\n  SERCOMM_HWID := AYA\n  SERCOMM_HWVER := A001\n  SERCOMM_SWVER := 0x0086\n  IMAGE_SIZE := 28672k\n  DEVICE_PACKAGES += kmod-mt76x2\n  SUPPORTED_DEVICES += r6220\nendef\nTARGET_DEVICES += netgear_r6220\n\n\ndefine Device/netgear_r6260\n  $(Device/netgear_sercomm_nand)\n  DEVICE_MODEL := R6260\n  SERCOMM_HWNAME := R6260\n  SERCOMM_HWID := CHJ\n  SERCOMM_HWVER := A001\n  SERCOMM_SWVER := 0x0052\n  IMAGE_SIZE := 40960k\n  DEVICE_PACKAGES += kmod-mt7615e kmod-mt7615-firmware\nendef\nTARGET_DEVICES += netgear_r6260\n\ndefine Device/netgear_r6350\n  $(Device/netgear_sercomm_nand)\n  DEVICE_MODEL := R6350\n  SERCOMM_HWNAME := R6350\n  SERCOMM_HWID := CHJ\n  SERCOMM_HWVER := A001\n  SERCOMM_SWVER := 0x0052\n  IMAGE_SIZE := 40960k\n  DEVICE_PACKAGES += kmod-mt7615e kmod-mt7615-firmware\nendef\nTARGET_DEVICES += netgear_r6350\n\ndefine Device/netgear_r6700-v2\n  $(Device/netgear_sercomm_nand)\n  DEVICE_MODEL := R6700\n  DEVICE_VARIANT := v2\n  DEVICE_ALT0_VENDOR := NETGEAR\n  DEVICE_ALT0_MODEL := Nighthawk AC2400\n  DEVICE_ALT0_VARIANT := v1\n  DEVICE_ALT1_VENDOR := NETGEAR\n  DEVICE_ALT1_MODEL := Nighthawk AC2100\n  DEVICE_ALT1_VARIANT := v1\n  SERCOMM_HWNAME := R6950\n  SERCOMM_HWID := BZV\n  SERCOMM_HWVER := A001\n  SERCOMM_SWVER := 0x1032\n  IMAGE_SIZE := 40960k\n  DEVICE_PACKAGES += kmod-mt7615e kmod-mt7615-firmware\nendef\nTARGET_DEVICES += netgear_r6700-v2\n\ndefine Device/netgear_r6800\n  $(Device/netgear_sercomm_nand)\n  DEVICE_MODEL := R6800\n  SERCOMM_HWNAME := R6950\n  SERCOMM_HWID := BZV\n  SERCOMM_HWVER := A001\n  SERCOMM_SWVER := 0x0062\n  IMAGE_SIZE := 40960k\n  DEVICE_PACKAGES += kmod-mt7615e kmod-mt7615-firmware\nendef\nTARGET_DEVICES += netgear_r6800\n\ndefine Device/netgear_r6850\n  $(Device/netgear_sercomm_nand)\n  DEVICE_MODEL := R6850\n  SERCOMM_HWNAME := R6850\n  SERCOMM_HWID := CHJ\n  SERCOMM_HWVER := A001\n  SERCOMM_SWVER := 0x0052\n  IMAGE_SIZE := 40960k\n  DEVICE_PACKAGES += kmod-mt7615e kmod-mt7615-firmware\nendef\nTARGET_DEVICES += netgear_r6850\n\ndefine Device/netgear_r6900-v2\n  $(Device/netgear_sercomm_nand)\n  DEVICE_MODEL := R6900\n  DEVICE_VARIANT := v2\n  SERCOMM_HWNAME := R6950\n  SERCOMM_HWID := BZV\n  SERCOMM_HWVER := A001\n  SERCOMM_SWVER := 0x1032\n  IMAGE_SIZE := 40960k\n  DEVICE_PACKAGES += kmod-mt7615e kmod-mt7615-firmware\nendef\nTARGET_DEVICES += netgear_r6900-v2\n\ndefine Device/netgear_r7200\n  $(Device/netgear_sercomm_nand)\n  DEVICE_MODEL := R7200\n  SERCOMM_HWNAME := R6950\n  SERCOMM_HWID := BZV\n  SERCOMM_HWVER := A001\n  SERCOMM_SWVER := 0x1032\n  IMAGE_SIZE := 40960k\n  DEVICE_PACKAGES += kmod-mt7615e kmod-mt7615-firmware\nendef\nTARGET_DEVICES += netgear_r7200\n\ndefine Device/netgear_r7450\n  $(Device/netgear_sercomm_nand)\n  DEVICE_MODEL := R7450\n  SERCOMM_HWNAME := R6950\n  SERCOMM_HWID := BZV\n  SERCOMM_HWVER := A001\n  SERCOMM_SWVER := 0x1032\n  IMAGE_SIZE := 40960k\n  DEVICE_PACKAGES += kmod-mt7615e kmod-mt7615-firmware\nendef\nTARGET_DEVICES += netgear_r7450\n\ndefine Device/netgear_wac104\n  $(Device/netgear_sercomm_nand)\n  DEVICE_MODEL := WAC104\n  SERCOMM_HWNAME := WAC104\n  SERCOMM_HWID := CAY\n  SERCOMM_HWVER := A001\n  SERCOMM_SWVER := 0x0006\n  IMAGE_SIZE := 28672k\n  DEVICE_PACKAGES += kmod-mt76x2\nendef\nTARGET_DEVICES += netgear_wac104\n\ndefine Device/netgear_wac124\n  $(Device/netgear_sercomm_nand)\n  DEVICE_MODEL := WAC124\n  SERCOMM_HWNAME := WAC124\n  SERCOMM_HWID := CTL\n  SERCOMM_HWVER := A003\n  SERCOMM_SWVER := 0x0402\n  IMAGE_SIZE := 40960k\n  DEVICE_PACKAGES += kmod-mt7615e kmod-mt7615-firmware\nendef\nTARGET_DEVICES += netgear_wac124\n\ndefine Device/netgear_wndr3700-v5\n  $(Device/dsa-migration)\n  $(Device/netgear_sercomm_nor)\n  $(Device/uimage-lzma-loader)\n  IMAGE_SIZE := 15232k\n  DEVICE_MODEL := WNDR3700\n  DEVICE_VARIANT := v5\n  SERCOMM_HWNAME := WNDR3700v5\n  SERCOMM_HWID := AYB\n  SERCOMM_HWVER := A001\n  SERCOMM_SWVER := 0x1054\n  SERCOMM_PAD := 320k\n  DEVICE_PACKAGES := kmod-mt7603 kmod-mt76x2 kmod-usb3 \\\n\tkmod-usb-ledtrig-usbport\n  SUPPORTED_DEVICES += wndr3700v5\nendef\nTARGET_DEVICES += netgear_wndr3700-v5\n\ndefine Device/netis_wf2881\n  $(Device/dsa-migration)\n  BLOCKSIZE := 128k\n  PAGESIZE := 2048\n  FILESYSTEMS := squashfs\n  KERNEL_SIZE := 4096k\n  IMAGE_SIZE := 129280k\n  UBINIZE_OPTS := -E 5\n  UIMAGE_NAME := WF2881_0.0.00\n  KERNEL_INITRAMFS := $(KERNEL_DTB) | netis-tail WF2881 | uImage lzma\n  IMAGES += factory.bin\n  IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata\n  IMAGE/factory.bin := append-kernel | pad-to $$$$(KERNEL_SIZE) | append-ubi | \\\n\tcheck-size\n  DEVICE_VENDOR := NETIS\n  DEVICE_MODEL := WF2881\n  DEVICE_PACKAGES := kmod-mt76x2 kmod-usb3 kmod-usb-ledtrig-usbport\nendef\nTARGET_DEVICES += netis_wf2881\n\ndefine Device/oraybox_x3a\n  $(Device/dsa-migration)\n  $(Device/uimage-lzma-loader)\n  IMAGE_SIZE := 15360k\n  DEVICE_VENDOR := OrayBox\n  DEVICE_MODEL := X3A\n  DEVICE_PACKAGES := kmod-mt7615e kmod-mt7615-firmware\nendef\nTARGET_DEVICES += oraybox_x3a\n\ndefine Device/phicomm_k2p\n  $(Device/dsa-migration)\n  IMAGE_SIZE := 15744k\n  DEVICE_VENDOR := Phicomm\n  DEVICE_MODEL := K2P\n  DEVICE_ALT0_VENDOR := Phicomm\n  DEVICE_ALT0_MODEL := KE 2P\n  SUPPORTED_DEVICES += k2p\n  DEVICE_PACKAGES := kmod-mt7615e kmod-mt7615-firmware\nendef\nTARGET_DEVICES += phicomm_k2p\n\ndefine Device/planex_vr500\n  $(Device/dsa-migration)\n  $(Device/uimage-lzma-loader)\n  IMAGE_SIZE := 65216k\n  DEVICE_VENDOR := Planex\n  DEVICE_MODEL := VR500\n  DEVICE_PACKAGES := kmod-usb3 -wpad-basic-wolfssl\n  SUPPORTED_DEVICES += vr500\nendef\nTARGET_DEVICES += planex_vr500\n\ndefine Device/raisecom_msg1500-x-00\n  $(Device/dsa-migration)\n  $(Device/uimage-lzma-loader)\n  BLOCKSIZE := 128k\n  PAGESIZE := 2048\n  KERNEL_SIZE := 4096k\n  IMAGE_SIZE := 129280k\n  UBINIZE_OPTS := -E 5\n  IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata\n  DEVICE_VENDOR := RAISECOM\n  DEVICE_MODEL := MSG1500\n  DEVICE_VARIANT := X.00\n  DEVICE_PACKAGES := kmod-mt7615e kmod-mt7615-firmware kmod-usb3 \\\n\tkmod-usb-ledtrig-usbport uboot-envtools\nendef\nTARGET_DEVICES += raisecom_msg1500-x-00\n\ndefine Device/renkforce_ws-wn530hp3-a\n  $(Device/dsa-migration)\n  DEVICE_VENDOR := Renkforce\n  DEVICE_MODEL := WS-WN530HP3-A\n  DEVICE_PACKAGES += kmod-mt7603 kmod-mt7615e kmod-mt7663-firmware-ap\n  IMAGE/sysupgrade.bin := append-kernel | pad-to 65536 | append-rootfs | \\\n\tcheck-size | append-metadata\n  IMAGE_SIZE := 15040k\nendef\nTARGET_DEVICES += renkforce_ws-wn530hp3-a\n\ndefine Device/samknows_whitebox-v8\n  $(Device/dsa-migration)\n  $(Device/uimage-lzma-loader)\n  IMAGE_SIZE := 16064k\n  DEVICE_VENDOR := SamKnows\n  DEVICE_MODEL := Whitebox 8\n  DEVICE_PACKAGES := kmod-mt7603 kmod-mt76x2 kmod-usb3 \\\n\tkmod-usb-ledtrig-usbport uboot-envtools\n  SUPPORTED_DEVICES += sk-wb8\nendef\nTARGET_DEVICES += samknows_whitebox-v8\n\ndefine Device/sercomm_na502\n  $(Device/uimage-lzma-loader)\n  BLOCKSIZE := 128k\n  PAGESIZE := 2048\n  IMAGE_SIZE := 20480k\n  IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata\n  UBINIZE_OPTS := -E 5\n  KERNEL_SIZE := 4096k\n  DEVICE_VENDOR := SERCOMM\n  DEVICE_MODEL := NA502\n  DEVICE_PACKAGES := kmod-mt76x2 kmod-mt7603 kmod-usb3\nendef\nTARGET_DEVICES += sercomm_na502\n\ndefine Device/storylink_sap-g3200u3\n  $(Device/dsa-migration)\n  IMAGE_SIZE := 7872k\n  DEVICE_VENDOR := STORYLiNK\n  DEVICE_MODEL := SAP-G3200U3\n  DEVICE_PACKAGES := kmod-mt76x2 kmod-usb3 kmod-usb-ledtrig-usbport\n  SUPPORTED_DEVICES += sap-g3200u3\nendef\nTARGET_DEVICES += storylink_sap-g3200u3\n\ndefine Device/telco-electronics_x1\n  $(Device/dsa-migration)\n  IMAGE_SIZE := 16064k\n  DEVICE_VENDOR := Telco Electronics\n  DEVICE_MODEL := X1\n  DEVICE_PACKAGES := kmod-usb3 kmod-mt76\nendef\nTARGET_DEVICES += telco-electronics_x1\n\ndefine Device/tenbay_t-mb5eu-v01\n  $(Device/dsa-migration)\n  DEVICE_VENDOR := Tenbay\n  DEVICE_MODEL := T-MB5EU-V01\n  DEVICE_DTS_CONFIG := config@1\n  DEVICE_PACKAGES += kmod-mt7915e kmod-usb3\n  KERNEL := kernel-bin | lzma | fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb\n  IMAGE_SIZE := 15808k\n  SUPPORTED_DEVICES += mt7621-dm2-t-mb5eu-v01-nor\nendef\nTARGET_DEVICES += tenbay_t-mb5eu-v01\n\ndefine Device/thunder_timecloud\n  $(Device/dsa-migration)\n  $(Device/uimage-lzma-loader)\n  IMAGE_SIZE := 16064k\n  DEVICE_VENDOR := Thunder\n  DEVICE_MODEL := Timecloud\n  DEVICE_PACKAGES := kmod-usb3 -wpad-basic-wolfssl\n  SUPPORTED_DEVICES += timecloud\nendef\nTARGET_DEVICES += thunder_timecloud\n\ndefine Device/totolink_a7000r\n  $(Device/dsa-migration)\n  IMAGE_SIZE := 16064k\n  UIMAGE_NAME := C8340R1C-9999\n  DEVICE_VENDOR := TOTOLINK\n  DEVICE_MODEL := A7000R\n  DEVICE_PACKAGES := kmod-mt7615e kmod-mt7615-firmware\nendef\nTARGET_DEVICES += totolink_a7000r\n\ndefine Device/totolink_x5000r\n  $(Device/dsa-migration)\n  IMAGE_SIZE := 16064k\n  UIMAGE_NAME := C8343R-9999\n  DEVICE_VENDOR := TOTOLINK\n  DEVICE_MODEL := X5000R\n  DEVICE_PACKAGES := kmod-mt7915e\nendef\nTARGET_DEVICES += totolink_x5000r\n\ndefine Device/tplink_archer-a6-v3\n  $(Device/dsa-migration)\n  $(Device/tplink-safeloader)\n  DEVICE_MODEL := Archer A6\n  DEVICE_VARIANT := V3\n  DEVICE_PACKAGES := kmod-mt7603 kmod-mt7615e \\\n\tkmod-mt7663-firmware-ap\n  TPLINK_BOARD_ID := ARCHER-A6-V3\n  KERNEL := $(KERNEL_DTB) | uImage lzma\n  IMAGE_SIZE := 15744k\nendef\nTARGET_DEVICES += tplink_archer-a6-v3\n\ndefine Device/tplink_archer-c6-v3\n  $(Device/dsa-migration)\n  $(Device/tplink-safeloader)\n  DEVICE_MODEL := Archer C6\n  DEVICE_VARIANT := V3\n  DEVICE_PACKAGES := kmod-mt7603 kmod-mt7615e \\\n\tkmod-mt7663-firmware-ap\n  TPLINK_BOARD_ID := ARCHER-C6-V3\n  KERNEL := $(KERNEL_DTB) | uImage lzma\n  IMAGE_SIZE := 15744k\nendef\nTARGET_DEVICES += tplink_archer-c6-v3\n\ndefine Device/tplink_archer-c6u-v1\n  $(Device/dsa-migration)\n  $(Device/tplink-safeloader)\n  DEVICE_MODEL := Archer C6U\n  DEVICE_VARIANT := v1\n  DEVICE_PACKAGES := kmod-mt7603 \\\n\tkmod-mt7615e kmod-mt7663-firmware-ap \\\n\tkmod-usb3 kmod-usb-ledtrig-usbport\n  KERNEL := $(KERNEL_DTB) | uImage lzma\n  TPLINK_BOARD_ID := ARCHER-C6U-V1\n  IMAGE_SIZE := 15744k\nendef\nTARGET_DEVICES += tplink_archer-c6u-v1\n\ndefine Device/tplink_eap235-wall-v1\n  $(Device/dsa-migration)\n  $(Device/tplink-safeloader)\n  DEVICE_MODEL := EAP235-Wall\n  DEVICE_VARIANT := v1\n  DEVICE_PACKAGES := kmod-mt7603 kmod-mt7615e kmod-mt7663-firmware-ap\n  TPLINK_BOARD_ID := EAP235-WALL-V1\n  IMAGE_SIZE := 13440k\n  IMAGE/factory.bin := append-rootfs | tplink-safeloader factory | \\\n\tpad-extra 128\nendef\nTARGET_DEVICES += tplink_eap235-wall-v1\n\ndefine Device/tplink_eap615-wall-v1\n  $(Device/dsa-migration)\n  $(Device/tplink-safeloader)\n  DEVICE_MODEL := EAP615-Wall\n  DEVICE_VARIANT := v1\n  DEVICE_PACKAGES := kmod-mt7915e\n  TPLINK_BOARD_ID := EAP615-WALL-V1\n  KERNEL := kernel-bin | lzma | fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb | pad-to 64k\n  KERNEL_INITRAMFS := kernel-bin | lzma | fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd\n  IMAGE_SIZE := 13248k\nendef\nTARGET_DEVICES += tplink_eap615-wall-v1\n\ndefine Device/tplink_re350-v1\n  $(Device/dsa-migration)\n  $(Device/tplink-safeloader)\n  DEVICE_MODEL := RE350\n  DEVICE_VARIANT := v1\n  DEVICE_PACKAGES := kmod-mt7603 kmod-mt76x2\n  TPLINK_BOARD_ID := RE350-V1\n  IMAGE_SIZE := 6016k\n  SUPPORTED_DEVICES += re350-v1\nendef\nTARGET_DEVICES += tplink_re350-v1\n\ndefine Device/tplink_re500-v1\n  $(Device/dsa-migration)\n  $(Device/tplink-safeloader)\n  DEVICE_MODEL := RE500\n  DEVICE_VARIANT := v1\n  DEVICE_PACKAGES := kmod-mt7615e kmod-mt7615-firmware\n  TPLINK_BOARD_ID := RE500-V1\n  IMAGE_SIZE := 14208k\nendef\nTARGET_DEVICES += tplink_re500-v1\n\ndefine Device/tplink_re650-v1\n  $(Device/dsa-migration)\n  $(Device/tplink-safeloader)\n  DEVICE_MODEL := RE650\n  DEVICE_VARIANT := v1\n  DEVICE_PACKAGES := kmod-mt7615e kmod-mt7615-firmware\n  TPLINK_BOARD_ID := RE650-V1\n  IMAGE_SIZE := 14208k\nendef\nTARGET_DEVICES += tplink_re650-v1\n\ndefine Device/tplink_re650-v2\n  $(Device/dsa-migration)\n  $(Device/tplink-safeloader)\n  DEVICE_MODEL := RE650\n  DEVICE_VARIANT := v2\n  DEVICE_PACKAGES := kmod-mt7615e kmod-mt7615-firmware\n  TPLINK_BOARD_ID := RE650-V2\n  IMAGE_SIZE := 7994k\nendef\nTARGET_DEVICES += tplink_re650-v2\n\ndefine Device/tplink_tl-wpa8631p-v3\n  $(Device/dsa-migration)\n  $(Device/tplink-safeloader)\n  DEVICE_MODEL := TL-WPA8631P\n  DEVICE_VARIANT := v3\n  DEVICE_PACKAGES := kmod-mt7603 kmod-mt7615e kmod-mt7663-firmware-ap\n  TPLINK_BOARD_ID := TL-WPA8631P-V3\n  IMAGE_SIZE := 7232k\nendef\nTARGET_DEVICES += tplink_tl-wpa8631p-v3\n\ndefine Device/ubnt_edgerouter_common\n  $(Device/dsa-migration)\n  $(Device/uimage-lzma-loader)\n  DEVICE_VENDOR := Ubiquiti\n  IMAGE_SIZE := 256768k\n  FILESYSTEMS := squashfs\n  KERNEL_SIZE := 3145728\n  KERNEL_INITRAMFS := $$(KERNEL) | \\\n\tubnt-erx-factory-image $(KDIR)/tmp/$$(KERNEL_INITRAMFS_PREFIX)-factory.tar\n  IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata\n  DEVICE_PACKAGES += -wpad-basic-wolfssl\nendef\n\ndefine Device/ubnt_edgerouter-x\n  $(Device/ubnt_edgerouter_common)\n  DEVICE_MODEL := EdgeRouter X\n  SUPPORTED_DEVICES += ubnt-erx ubiquiti,edgerouterx\nendef\nTARGET_DEVICES += ubnt_edgerouter-x\n\ndefine Device/ubnt_edgerouter-x-sfp\n  $(Device/ubnt_edgerouter_common)\n  DEVICE_MODEL := EdgeRouter X SFP\n  DEVICE_ALT0_VENDOR := Ubiquiti\n  DEVICE_ALT0_MODEL := EdgePoint R6\n  DEVICE_PACKAGES += kmod-i2c-algo-pca kmod-gpio-pca953x kmod-sfp\n  SUPPORTED_DEVICES += ubnt-erx-sfp ubiquiti,edgerouterx-sfp\nendef\nTARGET_DEVICES += ubnt_edgerouter-x-sfp\n\ndefine Device/ubnt_unifi-6-lite\n  $(Device/dsa-migration)\n  DEVICE_VENDOR := Ubiquiti\n  DEVICE_MODEL := UniFi 6 Lite\n  DEVICE_DTS_CONFIG := config@1\n  DEVICE_PACKAGES += kmod-mt7603 kmod-mt7915e\n  KERNEL := kernel-bin | lzma | fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb\n  IMAGE_SIZE := 15424k\nendef\nTARGET_DEVICES += ubnt_unifi-6-lite\n\ndefine Device/ubnt_unifi-nanohd\n  $(Device/dsa-migration)\n  DEVICE_VENDOR := Ubiquiti\n  DEVICE_MODEL := UniFi nanoHD\n  DEVICE_PACKAGES += kmod-mt7603 kmod-mt7615e kmod-mt7615-firmware\n  IMAGE_SIZE := 15552k\nendef\nTARGET_DEVICES += ubnt_unifi-nanohd\n\ndefine Device/ubnt_usw-flex\n  $(Device/dsa-migration)\n  DEVICE_VENDOR := Ubiquiti\n  DEVICE_MODEL := UniFi Switch Flex\n  DEVICE_DTS_CONFIG := config@1\n  KERNEL := kernel-bin | lzma | fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb\n  IMAGE_SIZE := 7360k\nendef\nTARGET_DEVICES += ubnt_usw-flex\n\ndefine Device/unielec_u7621-01-16m\n  $(Device/dsa-migration)\n  $(Device/uimage-lzma-loader)\n  IMAGE_SIZE := 16064k\n  DEVICE_VENDOR := UniElec\n  DEVICE_MODEL := U7621-01\n  DEVICE_VARIANT := 16M\n  DEVICE_PACKAGES := kmod-mt7603 kmod-mt76x2 kmod-usb3\nendef\nTARGET_DEVICES += unielec_u7621-01-16m\n\ndefine Device/unielec_u7621-06-16m\n  $(Device/dsa-migration)\n  $(Device/uimage-lzma-loader)\n  IMAGE_SIZE := 16064k\n  DEVICE_VENDOR := UniElec\n  DEVICE_MODEL := U7621-06\n  DEVICE_VARIANT := 16M\n  DEVICE_PACKAGES := kmod-ata-ahci kmod-sdhci-mt7620 kmod-usb3 -wpad-basic-wolfssl\n  SUPPORTED_DEVICES += u7621-06-256M-16M unielec,u7621-06-256m-16m\nendef\nTARGET_DEVICES += unielec_u7621-06-16m\n\ndefine Device/unielec_u7621-06-64m\n  $(Device/dsa-migration)\n  $(Device/uimage-lzma-loader)\n  IMAGE_SIZE := 65216k\n  DEVICE_VENDOR := UniElec\n  DEVICE_MODEL := U7621-06\n  DEVICE_VARIANT := 64M\n  DEVICE_PACKAGES := kmod-ata-ahci kmod-sdhci-mt7620 kmod-usb3 -wpad-basic-wolfssl\n  SUPPORTED_DEVICES += unielec,u7621-06-512m-64m\nendef\nTARGET_DEVICES += unielec_u7621-06-64m\n\ndefine Device/wavlink_wl-wn531a6\n  $(Device/dsa-migration)\n  DEVICE_VENDOR := Wavlink\n  DEVICE_MODEL := WL-WN531A6\n  DEVICE_PACKAGES := kmod-mt7603 kmod-mt7615e kmod-mt7615-firmware kmod-usb3\n  IMAGE_SIZE := 15040k\nendef\nTARGET_DEVICES += wavlink_wl-wn531a6\n\ndefine Device/wavlink_wl-wn533a8\n  $(Device/dsa-migration)\n  DEVICE_VENDOR := Wavlink\n  DEVICE_MODEL := WL-WN533A8\n  KERNEL_INITRAMFS_SUFFIX := -WN533A8$$(KERNEL_SUFFIX)\n  DEVICE_PACKAGES := kmod-mt7615e kmod-mt7615-firmware kmod-usb3\n  IMAGE_SIZE := 15040k\nendef\nTARGET_DEVICES += wavlink_wl-wn533a8\n\ndefine Device/wevo_11acnas\n  $(Device/dsa-migration)\n  $(Device/uimage-lzma-loader)\n  IMAGE_SIZE := 16064k\n  UIMAGE_NAME := 11AC-NAS-Router(0.0.0)\n  DEVICE_VENDOR := WeVO\n  DEVICE_MODEL := 11AC NAS Router\n  DEVICE_PACKAGES := kmod-mt7603 kmod-mt76x2 kmod-usb3 \\\n\tkmod-usb-ledtrig-usbport\n  SUPPORTED_DEVICES += 11acnas\nendef\nTARGET_DEVICES += wevo_11acnas\n\ndefine Device/wevo_w2914ns-v2\n  $(Device/dsa-migration)\n  $(Device/uimage-lzma-loader)\n  IMAGE_SIZE := 16064k\n  UIMAGE_NAME := W2914NS-V2(0.0.0)\n  DEVICE_VENDOR := WeVO\n  DEVICE_MODEL := W2914NS\n  DEVICE_VARIANT := v2\n  DEVICE_PACKAGES := kmod-mt7603 kmod-mt76x2 kmod-usb3 \\\n\tkmod-usb-ledtrig-usbport\n  SUPPORTED_DEVICES += w2914nsv2\nendef\nTARGET_DEVICES += wevo_w2914ns-v2\n\ndefine Device/winstars_ws-wn583a6\n  $(Device/dsa-migration)\n  $(Device/uimage-lzma-loader)\n  IMAGE_SIZE := 7872k\n  DEVICE_VENDOR := Winstars\n  DEVICE_MODEL := WS-WN583A6\n  DEVICE_ALT0_VENDOR := Gemeita\n  DEVICE_ALT0_MODEL := AC2100\n  KERNEL_INITRAMFS_SUFFIX := -WN583A6$$(KERNEL_SUFFIX)\n  DEVICE_PACKAGES := kmod-mt7603 kmod-mt7615e kmod-mt7615-firmware\nendef\nTARGET_DEVICES += winstars_ws-wn583a6\n\ndefine Device/xiaomi_nand_separate\n  $(Device/dsa-migration)\n  $(Device/uimage-lzma-loader)\n  DEVICE_VENDOR := Xiaomi\n  DEVICE_PACKAGES := uboot-envtools\n  BLOCKSIZE := 128k\n  PAGESIZE := 2048\n  KERNEL_SIZE := 4096k\n  UBINIZE_OPTS := -E 5\n  IMAGES += kernel1.bin rootfs0.bin\n  IMAGE/kernel1.bin := append-kernel\n  IMAGE/rootfs0.bin := append-ubi | check-size\n  IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata\nendef\n\ndefine Device/xiaomi_mi-router-3g\n  $(Device/xiaomi_nand_separate)\n  DEVICE_MODEL := Mi Router 3G\n  IMAGE_SIZE := 124416k\n  DEVICE_PACKAGES += kmod-mt7603 kmod-mt76x2 kmod-usb3 \\\n\tkmod-usb-ledtrig-usbport\n  SUPPORTED_DEVICES += R3G mir3g xiaomi,mir3g\nendef\nTARGET_DEVICES += xiaomi_mi-router-3g\n\ndefine Device/xiaomi_mi-router-3g-v2\n  $(Device/dsa-migration)\n  $(Device/uimage-lzma-loader)\n  IMAGE_SIZE := 14848k\n  DEVICE_VENDOR := Xiaomi\n  DEVICE_MODEL := Mi Router 3G\n  DEVICE_VARIANT := v2\n  DEVICE_PACKAGES := kmod-mt7603 kmod-mt76x2\n  SUPPORTED_DEVICES += xiaomi,mir3g-v2\nendef\nTARGET_DEVICES += xiaomi_mi-router-3g-v2\n\ndefine Device/xiaomi_mi-router-3-pro\n  $(Device/dsa-migration)\n  $(Device/uimage-lzma-loader)\n  BLOCKSIZE := 128k\n  PAGESIZE := 2048\n  KERNEL_SIZE:= 4096k\n  UBINIZE_OPTS := -E 5\n  IMAGE_SIZE := 255488k\n  DEVICE_VENDOR := Xiaomi\n  DEVICE_MODEL := Mi Router 3 Pro\n  IMAGES += factory.bin\n  IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata\n  IMAGE/factory.bin := append-kernel | pad-to $$(KERNEL_SIZE) | append-ubi | \\\n\tcheck-size\n  DEVICE_PACKAGES := kmod-mt7615e kmod-mt7615-firmware kmod-usb3 \\\n\tkmod-usb-ledtrig-usbport uboot-envtools\n  SUPPORTED_DEVICES += xiaomi,mir3p\nendef\nTARGET_DEVICES += xiaomi_mi-router-3-pro\n\ndefine Device/xiaomi_mi-router-4\n  $(Device/xiaomi_nand_separate)\n  DEVICE_MODEL := Mi Router 4\n  IMAGE_SIZE := 124416k\n  DEVICE_PACKAGES += kmod-mt7603 kmod-mt76x2\nendef\nTARGET_DEVICES += xiaomi_mi-router-4\n\ndefine Device/xiaomi_mi-router-4a-gigabit\n  $(Device/dsa-migration)\n  $(Device/uimage-lzma-loader)\n  IMAGE_SIZE := 14848k\n  DEVICE_VENDOR := Xiaomi\n  DEVICE_MODEL := Mi Router 4A\n  DEVICE_VARIANT := Gigabit Edition\n  DEVICE_PACKAGES := kmod-mt7603 kmod-mt76x2\nendef\nTARGET_DEVICES += xiaomi_mi-router-4a-gigabit\n\ndefine Device/xiaomi_mi-router-ac2100\n  $(Device/xiaomi_nand_separate)\n  DEVICE_MODEL := Mi Router AC2100\n  IMAGE_SIZE := 120320k\n  DEVICE_PACKAGES += kmod-mt7603 kmod-mt7615e kmod-mt7615-firmware\nendef\nTARGET_DEVICES += xiaomi_mi-router-ac2100\n\ndefine Device/xiaomi_mi-router-cr660x\n  $(Device/dsa-migration)\n  $(Device/uimage-lzma-loader)\n  DEVICE_VENDOR := Xiaomi\n  BLOCKSIZE := 128k\n  PAGESIZE := 2048\n  KERNEL_SIZE := 4096k\n  UBINIZE_OPTS := -E 5\n  IMAGE_SIZE := 128512k\n  IMAGES += firmware.bin\n  IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata\n  IMAGE/firmware.bin := append-kernel | pad-to $$(KERNEL_SIZE) | append-ubi | \\\n\tcheck-size\n  DEVICE_PACKAGES += kmod-mt7915e uboot-envtools\nendef\n\ndefine Device/xiaomi_mi-router-cr6606\n  $(Device/xiaomi_mi-router-cr660x)\n  DEVICE_MODEL := Mi Router CR6606\nendef\nTARGET_DEVICES += xiaomi_mi-router-cr6606\n\ndefine Device/xiaomi_mi-router-cr6608\n  $(Device/xiaomi_mi-router-cr660x)\n  DEVICE_MODEL := Mi Router CR6608\nendef\nTARGET_DEVICES += xiaomi_mi-router-cr6608\n\ndefine Device/xiaomi_mi-router-cr6609\n  $(Device/xiaomi_mi-router-cr660x)\n  DEVICE_MODEL := Mi Router CR6609\nendef\nTARGET_DEVICES += xiaomi_mi-router-cr6609\n\ndefine Device/xiaomi_redmi-router-ac2100\n  $(Device/xiaomi_nand_separate)\n  DEVICE_MODEL := Redmi Router AC2100\n  IMAGE_SIZE := 120320k\n  DEVICE_PACKAGES += kmod-mt7603 kmod-mt7615e kmod-mt7615-firmware\nendef\nTARGET_DEVICES += xiaomi_redmi-router-ac2100\n\ndefine Device/xiaoyu_xy-c5\n  $(Device/dsa-migration)\n  IMAGE_SIZE := 32448k\n  DEVICE_VENDOR := XiaoYu\n  DEVICE_MODEL := XY-C5\n  DEVICE_PACKAGES := kmod-ata-ahci kmod-usb3 -wpad-basic-wolfssl\nendef\nTARGET_DEVICES += xiaoyu_xy-c5\n\ndefine Device/xzwifi_creativebox-v1\n  $(Device/dsa-migration)\n  IMAGE_SIZE := 32448k\n  DEVICE_VENDOR := CreativeBox\n  DEVICE_MODEL := v1\n  DEVICE_PACKAGES := kmod-ata-ahci kmod-mt7603 kmod-mt76x2 kmod-sdhci-mt7620 \\\n\tkmod-usb3 -wpad-basic-wolfssl\nendef\nTARGET_DEVICES += xzwifi_creativebox-v1\n\ndefine Device/youhua_wr1200js\n  $(Device/dsa-migration)\n  IMAGE_SIZE := 16064k\n  DEVICE_VENDOR := YouHua\n  DEVICE_MODEL := WR1200JS\n  DEVICE_PACKAGES := kmod-mt7603 kmod-mt76x2 kmod-usb3 \\\n\tkmod-usb-ledtrig-usbport\nendef\nTARGET_DEVICES += youhua_wr1200js\n\ndefine Device/youku_yk-l2\n  $(Device/dsa-migration)\n  IMAGE_SIZE := 16064k\n  DEVICE_VENDOR := Youku\n  DEVICE_MODEL := YK-L2\n  DEVICE_PACKAGES := kmod-mt7603 kmod-mt76x2 kmod-usb3 \\\n\tkmod-usb-ledtrig-usbport\nendef\nTARGET_DEVICES += youku_yk-l2\n\ndefine Device/yuncore_ax820\n  $(Device/dsa-migration)\n  IMAGE_SIZE := 15808k\n  DEVICE_VENDOR := YunCore\n  DEVICE_MODEL := AX820\n  DEVICE_PACKAGES := kmod-mt7915e\nendef\nTARGET_DEVICES += yuncore_ax820\n\ndefine Device/zbtlink_zbt-we1326\n  $(Device/dsa-migration)\n  $(Device/uimage-lzma-loader)\n  IMAGE_SIZE := 16064k\n  DEVICE_VENDOR := Zbtlink\n  DEVICE_MODEL := ZBT-WE1326\n  DEVICE_PACKAGES := kmod-mt7603 kmod-mt76x2 kmod-usb3 kmod-sdhci-mt7620\n  SUPPORTED_DEVICES += zbt-we1326\nendef\nTARGET_DEVICES += zbtlink_zbt-we1326\n\ndefine Device/zbtlink_zbt-we3526\n  $(Device/dsa-migration)\n  $(Device/uimage-lzma-loader)\n  IMAGE_SIZE := 16064k\n  DEVICE_VENDOR := Zbtlink\n  DEVICE_MODEL := ZBT-WE3526\n  DEVICE_PACKAGES := kmod-sdhci-mt7620 kmod-mt7603 kmod-mt76x2 kmod-usb3 \\\n\tkmod-usb-ledtrig-usbport\nendef\nTARGET_DEVICES += zbtlink_zbt-we3526\n\ndefine Device/zbtlink_zbt-wg1602-16m\n  $(Device/dsa-migration)\n  $(Device/uimage-lzma-loader)\n  IMAGE_SIZE := 16064k\n  DEVICE_VENDOR := Zbtlink\n  DEVICE_MODEL := ZBT-WG1602\n  DEVICE_VARIANT := 16M\n  DEVICE_PACKAGES := kmod-sdhci-mt7620 kmod-mt7603 kmod-mt76x2 kmod-usb3 \\\n\tkmod-usb-ledtrig-usbport\nendef\nTARGET_DEVICES += zbtlink_zbt-wg1602-16m\n\ndefine Device/zbtlink_zbt-wg1608-16m\n  $(Device/dsa-migration)\n  $(Device/uimage-lzma-loader)\n  IMAGE_SIZE := 16064k\n  DEVICE_VENDOR := Zbtlink\n  DEVICE_MODEL := ZBT-WG1608\n  DEVICE_VARIANT := 16M\n  DEVICE_PACKAGES := kmod-sdhci-mt7620 kmod-mt7603 kmod-mt7615e \\\n\tkmod-mt7663-firmware-ap kmod-usb3 kmod-usb-ledtrig-usbport\nendef\nTARGET_DEVICES += zbtlink_zbt-wg1608-16m\n\ndefine Device/zbtlink_zbt-wg2626\n  $(Device/dsa-migration)\n  $(Device/uimage-lzma-loader)\n  IMAGE_SIZE := 16064k\n  DEVICE_VENDOR := Zbtlink\n  DEVICE_MODEL := ZBT-WG2626\n  DEVICE_PACKAGES := kmod-ata-ahci kmod-sdhci-mt7620 kmod-mt76x2 kmod-usb3 \\\n\tkmod-usb-ledtrig-usbport\n  SUPPORTED_DEVICES += zbt-wg2626\nendef\nTARGET_DEVICES += zbtlink_zbt-wg2626\n\ndefine Device/zbtlink_zbt-wg3526-16m\n  $(Device/dsa-migration)\n  $(Device/uimage-lzma-loader)\n  IMAGE_SIZE := 16064k\n  DEVICE_VENDOR := Zbtlink\n  DEVICE_MODEL := ZBT-WG3526\n  DEVICE_VARIANT := 16M\n  DEVICE_PACKAGES := kmod-ata-ahci kmod-sdhci-mt7620 kmod-mt7603 kmod-mt76x2 \\\n\tkmod-usb3 kmod-usb-ledtrig-usbport\n  SUPPORTED_DEVICES += zbt-wg3526 zbt-wg3526-16M\nendef\nTARGET_DEVICES += zbtlink_zbt-wg3526-16m\n\ndefine Device/zbtlink_zbt-wg3526-32m\n  $(Device/dsa-migration)\n  $(Device/uimage-lzma-loader)\n  IMAGE_SIZE := 32448k\n  DEVICE_VENDOR := Zbtlink\n  DEVICE_MODEL := ZBT-WG3526\n  DEVICE_VARIANT := 32M\n  DEVICE_PACKAGES := kmod-ata-ahci kmod-sdhci-mt7620 kmod-mt7603 kmod-mt76x2 \\\n\tkmod-usb3 kmod-usb-ledtrig-usbport\n  SUPPORTED_DEVICES += ac1200pro zbt-wg3526-32M\nendef\nTARGET_DEVICES += zbtlink_zbt-wg3526-32m\n\ndefine Device/zio_freezio\n  $(Device/dsa-migration)\n  IMAGE_SIZE := 16064k\n  DEVICE_VENDOR := ZIO\n  DEVICE_MODEL := FREEZIO\n  DEVICE_PACKAGES := kmod-mt7603 kmod-mt76x2 kmod-usb3 \\\n\tkmod-usb-ledtrig-usbport\nendef\nTARGET_DEVICES += zio_freezio\n\ndefine Device/zyxel_nr7101\n  $(Device/dsa-migration)\n  BLOCKSIZE := 128k\n  PAGESIZE := 2048\n  UBINIZE_OPTS := -E 5\n  DEVICE_VENDOR := ZyXEL\n  DEVICE_MODEL := NR7101\n  DEVICE_PACKAGES := kmod-mt7603 kmod-usb3 uboot-envtools kmod-usb-net-qmi-wwan kmod-usb-serial-option uqmi\n  KERNEL := $(KERNEL_DTB) | uImage lzma | zytrx-header $$(DEVICE_MODEL) $$(VERSION_DIST)-$$(REVISION)\n  KERNEL_INITRAMFS := $(KERNEL_DTB) | uImage lzma | zytrx-header $$(DEVICE_MODEL) 9.99(ABUV.9)$$(VERSION_DIST)-recovery\n  KERNEL_INITRAMFS_SUFFIX := -recovery.bin\n  IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata\nendef\nTARGET_DEVICES += zyxel_nr7101\n\ndefine Device/zyxel_wap6805\n  $(Device/dsa-migration)\n  BLOCKSIZE := 128k\n  PAGESIZE := 2048\n  KERNEL_SIZE := 4096k\n  UBINIZE_OPTS := -E 5\n  IMAGE_SIZE := 32448k\n  DEVICE_VENDOR := ZyXEL\n  DEVICE_MODEL := WAP6805\n  DEVICE_PACKAGES := kmod-mt7603 kmod-mt7621-qtn-rgmii\n  KERNEL := $(KERNEL_DTB) | uImage lzma | uimage-padhdr 160\n  IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata\nendef\nTARGET_DEVICES += zyxel_wap6805\n"
  },
  {
    "path": "target/linux/ramips/image/mt76x8.mk",
    "content": "#\n# MT76x8 Profiles\n#\n\ninclude ./common-tp-link.mk\n\nDEFAULT_SOC := mt7628an\n\ndefine Build/elecom-header\n\t$(eval model_id=$(1))\n\t( \\\n\t\tfw_size=\"$$(printf '%08x' $$(stat -c%s $@))\"; \\\n\t\techo -ne \"$$(echo \"031d6129$${fw_size}06000000$(model_id)\" | \\\n\t\t\tsed 's/../\\\\x&/g')\"; \\\n\t\tdd if=/dev/zero bs=92 count=1; \\\n\t\tdata_crc=\"$$(dd if=$@ | gzip -c | tail -c 8 | \\\n\t\t\tod -An -N4 -tx4 --endian little | tr -d ' \\n')\"; \\\n\t\techo -ne \"$$(echo \"$${data_crc}00000000\" | sed 's/../\\\\x&/g')\"; \\\n\t\tdd if=$@; \\\n\t) > $@.new\n\tmv $@.new $@\nendef\n\ndefine Build/ravpower-wd009-factory\n\tmkimage -A mips -T standalone -C none -a 0x80010000 -e 0x80010000 \\\n\t\t-n \"OpenWrt Bootloader\" -d $(UBOOT_PATH) $@.new\n\tcat $@ >> $@.new\n\t@mv $@.new $@\nendef\n\n\ndefine Device/alfa-network_awusfree1\n  IMAGE_SIZE := 7872k\n  DEVICE_VENDOR := ALFA Network\n  DEVICE_MODEL := AWUSFREE1\n  DEVICE_PACKAGES := uboot-envtools\n  SUPPORTED_DEVICES += awusfree1\nendef\nTARGET_DEVICES += alfa-network_awusfree1\n\ndefine Device/asus_rt-ac1200\n  IMAGE_SIZE := 16064k\n  DEVICE_VENDOR := Asus\n  DEVICE_MODEL := RT-AC1200\n  DEVICE_PACKAGES := kmod-mt76x2 kmod-usb2 kmod-usb-ohci \\\n\tkmod-usb-ledtrig-usbport\nendef\nTARGET_DEVICES += asus_rt-ac1200\n\ndefine Device/asus_rt-ac1200-v2\n  BLOCKSIZE := 64k\n  IMAGE_SIZE := 16064k\n  DEVICE_VENDOR := Asus\n  DEVICE_MODEL := RT-AC1200\n  DEVICE_VARIANT := V2\n  IMAGES += factory.bin\n  IMAGE/factory.bin := append-kernel | pad-to $$$$(BLOCKSIZE) | \\\n\tappend-rootfs | pad-rootfs\n  DEVICE_PACKAGES := kmod-mt7615e kmod-mt7663-firmware-ap\nendef\nTARGET_DEVICES += asus_rt-ac1200-v2\n\ndefine Device/asus_rt-n10p-v3\n  IMAGE_SIZE := 7872k\n  DEVICE_VENDOR := Asus\n  DEVICE_MODEL := RT-N10P\n  DEVICE_VARIANT := V3\nendef\nTARGET_DEVICES += asus_rt-n10p-v3\n\ndefine Device/asus_rt-n11p-b1\n  IMAGE_SIZE := 7872k\n  DEVICE_VENDOR := Asus\n  DEVICE_MODEL := RT-N11P\n  DEVICE_VARIANT := B1\nendef\nTARGET_DEVICES += asus_rt-n11p-b1\n\ndefine Device/asus_rt-n12-vp-b1\n  IMAGE_SIZE := 7872k\n  DEVICE_VENDOR := Asus\n  DEVICE_MODEL := RT-N12 VP\n  DEVICE_VARIANT := B1\nendef\nTARGET_DEVICES += asus_rt-n12-vp-b1\n\ndefine Device/buffalo_wcr-1166ds\n  IMAGE_SIZE := 7936k\n  BUFFALO_TAG_PLATFORM := MTK\n  BUFFALO_TAG_VERSION := 9.99\n  BUFFALO_TAG_MINOR := 9.99\n  IMAGES += factory.bin\n  IMAGE/sysupgrade.bin := trx -M 0x746f435c | pad-rootfs | append-metadata\n  IMAGE/factory.bin := trx -M 0x746f435c | pad-rootfs | append-metadata | \\\n\tbuffalo-enc WCR-1166DS $$(BUFFALO_TAG_VERSION) -l | \\\n\tbuffalo-tag-dhp WCR-1166DS JP JP | buffalo-enc-tag -l | buffalo-dhp-image\n  DEVICE_VENDOR := Buffalo\n  DEVICE_MODEL := WCR-1166DS\n  DEVICE_PACKAGES := kmod-mt76x2\n  SUPPORTED_DEVICES += wcr-1166ds\nendef\nTARGET_DEVICES += buffalo_wcr-1166ds\n\ndefine Device/comfast_cf-wr758ac\n  IMAGE_SIZE := 7872k\n  DEVICE_VENDOR := COMFAST\n  DEVICE_MODEL := CF-WR758AC\n  DEVICE_ALT0_VENDOR := Joowin\n  DEVICE_ALT0_MODEL := JW-WR758AC\nendef\n\ndefine Device/comfast_cf-wr758ac-v1\n  $(Device/comfast_cf-wr758ac)\n  DEVICE_PACKAGES := kmod-mt76x2\n  DEVICE_VARIANT := V1\n  DEVICE_ALT0_VARIANT := V1\n  SUPPORTED_DEVICES += joowin,jw-wr758ac-v1\nendef\nTARGET_DEVICES += comfast_cf-wr758ac-v1\n\ndefine Device/comfast_cf-wr758ac-v2\n  $(Device/comfast_cf-wr758ac)\n  DEVICE_PACKAGES := kmod-mt7615e kmod-mt7663-firmware-ap\n  DEVICE_VARIANT := V2\n  DEVICE_ALT0_VARIANT := V2\n  SUPPORTED_DEVICES += joowin,jw-wr758ac-v2\nendef\nTARGET_DEVICES += comfast_cf-wr758ac-v2\n\ndefine Device/cudy_wr1000\n  IMAGE_SIZE := 7872k\n  IMAGES += factory.bin\n  IMAGE/factory.bin := $$(sysupgrade_bin) | check-size | jcg-header 92.122\n  JCG_MAXSIZE := 7872k\n  DEVICE_VENDOR := Cudy\n  DEVICE_MODEL := WR1000\n  DEVICE_PACKAGES := kmod-mt76x2\n  SUPPORTED_DEVICES += wr1000\nendef\nTARGET_DEVICES += cudy_wr1000\n\ndefine Device/d-team_pbr-d1\n  IMAGE_SIZE := 16064k\n  DEVICE_VENDOR := PandoraBox\n  DEVICE_MODEL := PBR-D1\n  DEVICE_PACKAGES := kmod-usb2 kmod-usb-ohci\n  SUPPORTED_DEVICES += pbr-d1\nendef\nTARGET_DEVICES += d-team_pbr-d1\n\ndefine Device/dlink_dap-1325-a1\n  IMAGE_SIZE := 7872k\n  DEVICE_VENDOR := D-Link\n  DEVICE_MODEL := DAP-1325 A1\nendef\nTARGET_DEVICES += dlink_dap-1325-a1\n\ndefine Device/duzun_dm06\n  IMAGE_SIZE := 7872k\n  DEVICE_VENDOR := DuZun\n  DEVICE_MODEL := DM06\n  DEVICE_PACKAGES := kmod-usb2 kmod-usb-ohci kmod-usb-ledtrig-usbport\n  SUPPORTED_DEVICES += duzun-dm06\nendef\nTARGET_DEVICES += duzun_dm06\n\ndefine Device/elecom_wrc-1167fs\n  IMAGE_SIZE := 7360k\n  DEVICE_VENDOR := ELECOM\n  DEVICE_MODEL := WRC-1167FS\n  IMAGES += factory.bin\n  IMAGE/factory.bin := $$(sysupgrade_bin) | pad-to 64k | check-size | \\\n\txor-image -p 29944A25 -x | elecom-header 00228000 | \\\n\telecom-product-header WRC-1167FS\n  DEVICE_PACKAGES := kmod-mt76x2\nendef\nTARGET_DEVICES += elecom_wrc-1167fs\n\ndefine Device/glinet_gl-mt300n-v2\n  IMAGE_SIZE := 16064k\n  DEVICE_VENDOR := GL.iNet\n  DEVICE_MODEL := GL-MT300N\n  DEVICE_VARIANT := V2\n  DEVICE_PACKAGES := kmod-usb2 kmod-usb-ohci\n  SUPPORTED_DEVICES += gl-mt300n-v2\nendef\nTARGET_DEVICES += glinet_gl-mt300n-v2\n\ndefine Device/glinet_microuter-n300\n  IMAGE_SIZE := 16064k\n  DEVICE_VENDOR := GL.iNet\n  DEVICE_MODEL := microuter-N300\n  SUPPORTED_DEVICES += microuter-n300\nendef\nTARGET_DEVICES += glinet_microuter-n300\n\ndefine Device/glinet_vixmini\n  IMAGE_SIZE := 7872k\n  DEVICE_VENDOR := GL.iNet\n  DEVICE_MODEL := VIXMINI\n  SUPPORTED_DEVICES += vixmini\nendef\nTARGET_DEVICES += glinet_vixmini\n\ndefine Device/hak5_wifi-pineapple-mk7\n  IMAGE_SIZE := 32448k\n  DEVICE_VENDOR := Hak5\n  DEVICE_MODEL := WiFi Pineapple Mark 7\n  DEVICE_PACKAGES := kmod-usb2 kmod-usb-ohci\n  SUPPORTED_DEVICES += wifi-pineapple-mk7\nendef\nTARGET_DEVICES += hak5_wifi-pineapple-mk7\n\ndefine Device/hilink_hlk-7628n\n  IMAGE_SIZE := 32448k\n  DEVICE_VENDOR := HILINK\n  DEVICE_MODEL := HLK-7628N\nendef\nTARGET_DEVICES += hilink_hlk-7628n\n\ndefine Device/hilink_hlk-7688a\n  IMAGE_SIZE := 32448k\n  DEVICE_VENDOR := Hi-Link\n  DEVICE_MODEL := HLK-7688A\n  DEVICE_PACKAGES := kmod-usb2 kmod-usb-ohci kmod-usb-ledtrig-usbport\nendef\nTARGET_DEVICES += hilink_hlk-7688a\n\ndefine Device/hiwifi_hc5661a\n  IMAGE_SIZE := 15808k\n  DEVICE_VENDOR := HiWiFi\n  DEVICE_MODEL := HC5661A\n  SUPPORTED_DEVICES += hc5661a\nendef\nTARGET_DEVICES += hiwifi_hc5661a\n\ndefine Device/hiwifi_hc5761a\n  IMAGE_SIZE := 15808k\n  DEVICE_VENDOR := HiWiFi\n  DEVICE_MODEL := HC5761A\n  DEVICE_PACKAGES := kmod-mt76x0e kmod-usb2 kmod-usb-ohci\nendef\nTARGET_DEVICES += hiwifi_hc5761a\n\ndefine Device/hiwifi_hc5861b\n  IMAGE_SIZE := 15808k\n  DEVICE_VENDOR := HiWiFi\n  DEVICE_MODEL := HC5861B\n  DEVICE_PACKAGES := kmod-mt76x2\nendef\nTARGET_DEVICES += hiwifi_hc5861b\n\ndefine Device/iptime_a3\n  IMAGE_SIZE := 7936k\n  UIMAGE_NAME := a3\n  DEVICE_VENDOR := ipTIME\n  DEVICE_MODEL := A3\n  DEVICE_PACKAGES := kmod-mt76x2\nendef\nTARGET_DEVICES += iptime_a3\n\ndefine Device/iptime_a604m\n  IMAGE_SIZE := 7936k\n  UIMAGE_NAME := a604m\n  DEVICE_VENDOR := ipTIME\n  DEVICE_MODEL := A604M\n  DEVICE_PACKAGES := kmod-mt76x2\nendef\nTARGET_DEVICES += iptime_a604m\n\ndefine Device/jotale_js76x8\n  DEVICE_VENDOR := Jotale\n  DEVICE_MODEL := JS76x8\n  DEVICE_PACKAGES := kmod-usb2 kmod-usb-ohci\nendef\n\ndefine Device/jotale_js76x8-8m\n  $(Device/jotale_js76x8)\n  IMAGE_SIZE := 7872k\n  DEVICE_VARIANT := 8M\nendef\nTARGET_DEVICES += jotale_js76x8-8m\n\ndefine Device/jotale_js76x8-16m\n  $(Device/jotale_js76x8)\n  IMAGE_SIZE := 16064k\n  DEVICE_VARIANT := 16M\nendef\nTARGET_DEVICES += jotale_js76x8-16m\n\ndefine Device/jotale_js76x8-32m\n  $(Device/jotale_js76x8)\n  IMAGE_SIZE := 32448k\n  DEVICE_VARIANT := 32M\nendef\nTARGET_DEVICES += jotale_js76x8-32m\n\ndefine Device/mediatek_linkit-smart-7688\n  IMAGE_SIZE := 32448k\n  DEVICE_VENDOR := MediaTek\n  DEVICE_MODEL := LinkIt Smart 7688\n  DEVICE_PACKAGES:= kmod-usb2 kmod-usb-ohci uboot-envtools kmod-sdhci-mt7620\n  SUPPORTED_DEVICES += linkits7688 linkits7688d\nendef\nTARGET_DEVICES += mediatek_linkit-smart-7688\n\ndefine Device/mediatek_mt7628an-eval-board\n  BLOCKSIZE := 64k\n  IMAGE_SIZE := 7872k\n  DEVICE_VENDOR := MediaTek\n  DEVICE_MODEL := MT7628 EVB\n  DEVICE_PACKAGES := kmod-usb2 kmod-usb-ohci kmod-usb-ledtrig-usbport\n  SUPPORTED_DEVICES += mt7628\nendef\nTARGET_DEVICES += mediatek_mt7628an-eval-board\n\ndefine Device/mercury_mac1200r-v2\n  IMAGE_SIZE := 7936k\n  DEVICE_VENDOR := Mercury\n  DEVICE_MODEL := MAC1200R\n  DEVICE_VARIANT := v2.0\n  DEVICE_PACKAGES := kmod-mt76x2\n  SUPPORTED_DEVICES += mac1200rv2\nendef\nTARGET_DEVICES += mercury_mac1200r-v2\n\ndefine Device/minew_g1-c\n  IMAGE_SIZE := 15744k\n  DEVICE_VENDOR := Minew\n  DEVICE_MODEL := G1-C\n  DEVICE_PACKAGES := kmod-usb2 kmod-usb-ohci kmod-usb-ledtrig-usbport kmod-usb-serial-cp210x\n  SUPPORTED_DEVICES += minew-g1c\nendef\nTARGET_DEVICES += minew_g1-c\n\ndefine Device/motorola_mwr03\n  IMAGE_SIZE := 7872k\n  DEVICE_VENDOR := Motorola\n  DEVICE_MODEL := MWR03\n  DEVICE_PACKAGES := kmod-mt76x2\nendef\nTARGET_DEVICES += motorola_mwr03\n\ndefine Device/netgear_r6020\n  $(Device/netgear_sercomm_nor)\n  IMAGE_SIZE := 7104k\n  DEVICE_MODEL := R6020\n  DEVICE_PACKAGES := kmod-mt76x2\n  SERCOMM_HWNAME := R6020\n  SERCOMM_HWID := CFR\n  SERCOMM_HWVER := A001\n  SERCOMM_SWVER := 0x0040\n  SERCOMM_PAD := 576k\nendef\nTARGET_DEVICES += netgear_r6020\n\ndefine Device/netgear_r6080\n  $(Device/netgear_sercomm_nor)\n  IMAGE_SIZE := 7552k\n  DEVICE_MODEL := R6080\n  DEVICE_PACKAGES := kmod-mt76x2\n  SERCOMM_HWNAME := R6080\n  SERCOMM_HWID := CFR\n  SERCOMM_HWVER := A001\n  SERCOMM_SWVER := 0x0040\n  SERCOMM_PAD := 576k\nendef\nTARGET_DEVICES += netgear_r6080\n\ndefine Device/netgear_r6120\n  $(Device/netgear_sercomm_nor)\n  IMAGE_SIZE := 15744k\n  DEVICE_MODEL := R6120\n  DEVICE_PACKAGES := kmod-mt76x2 kmod-usb2 kmod-usb-ohci\n  SERCOMM_HWNAME := R6120\n  SERCOMM_HWID := CGQ\n  SERCOMM_HWVER := A001\n  SERCOMM_SWVER := 0x0040\n  SERCOMM_PAD := 576k\nendef\nTARGET_DEVICES += netgear_r6120\n\ndefine Device/onion_omega2\n  IMAGE_SIZE := 16064k\n  DEVICE_VENDOR := Onion\n  DEVICE_MODEL := Omega2\n  DEVICE_PACKAGES:= kmod-usb2 kmod-usb-ohci uboot-envtools\n  SUPPORTED_DEVICES += omega2\nendef\nTARGET_DEVICES += onion_omega2\n\ndefine Device/onion_omega2p\n  IMAGE_SIZE := 32448k\n  DEVICE_VENDOR := Onion\n  DEVICE_MODEL := Omega2+\n  DEVICE_PACKAGES:= kmod-usb2 kmod-usb-ohci uboot-envtools kmod-sdhci-mt7620\n  SUPPORTED_DEVICES += omega2p\nendef\nTARGET_DEVICES += onion_omega2p\n\ndefine Device/rakwireless_rak633\n  IMAGE_SIZE := 7872k\n  DEVICE_VENDOR := Rakwireless\n  DEVICE_MODEL := RAK633\n  DEVICE_PACKAGES := kmod-usb2 kmod-usb-ohci\nendef\nTARGET_DEVICES += rakwireless_rak633\n\ndefine Device/ravpower_rp-wd009\n  IMAGE_SIZE := 14272k\n  DEVICE_VENDOR := RAVPower\n  DEVICE_MODEL := RP-WD009\n  UBOOT_PATH := $(STAGING_DIR_IMAGE)/ravpower_rp-wd009-u-boot.bin\n  DEVICE_PACKAGES := kmod-mt76x0e kmod-usb2 kmod-usb-ohci \\\n\tkmod-sdhci-mt7620 kmod-i2c-mt7628 ravpower-mcu\n  IMAGES += factory.bin\n  IMAGE/factory.bin := $$(sysupgrade_bin) | ravpower-wd009-factory\nendef\nTARGET_DEVICES += ravpower_rp-wd009\n\ndefine Device/skylab_skw92a\n  IMAGE_SIZE := 16064k\n  DEVICE_VENDOR := Skylab\n  DEVICE_MODEL := SKW92A\n  DEVICE_PACKAGES := kmod-usb2 kmod-usb-ohci\nendef\nTARGET_DEVICES += skylab_skw92a\n\ndefine Device/tama_w06\n  IMAGE_SIZE := 15040k\n  DEVICE_VENDOR := Tama\n  DEVICE_MODEL := W06\n  DEVICE_PACKAGES := kmod-usb2 kmod-usb-ohci\nendef\nTARGET_DEVICES += tama_w06\n\ndefine Device/totolink_a3\n  IMAGE_SIZE := 7936k\n  UIMAGE_NAME := za3\n  DEVICE_VENDOR := TOTOLINK\n  DEVICE_MODEL := A3\n  DEVICE_PACKAGES := kmod-mt76x2\nendef\nTARGET_DEVICES += totolink_a3\n\ndefine Device/totolink_lr1200\n  IMAGE_SIZE := 7872k\n  DEVICE_VENDOR := TOTOLINK\n  DEVICE_MODEL := LR1200\n  DEVICE_PACKAGES := kmod-mt76x2 kmod-usb2 uqmi\nendef\nTARGET_DEVICES += totolink_lr1200\n\ndefine Device/tplink_archer-c20-v4\n  $(Device/tplink-v2)\n  IMAGE_SIZE := 7808k\n  DEVICE_MODEL := Archer C20\n  DEVICE_VARIANT := v4\n  TPLINK_FLASHLAYOUT := 8Mmtk\n  TPLINK_HWID := 0xc200004\n  TPLINK_HWREVADD := 0x4\n  DEVICE_PACKAGES := kmod-mt76x0e\n  IMAGES := sysupgrade.bin tftp-recovery.bin\n  IMAGE/tftp-recovery.bin := pad-extra 128k | $$(IMAGE/factory.bin)\n  SUPPORTED_DEVICES += tplink,c20-v4\nendef\nTARGET_DEVICES += tplink_archer-c20-v4\n\ndefine Device/tplink_archer-c20-v5\n  $(Device/tplink-v2)\n  IMAGE_SIZE := 7616k\n  DEVICE_MODEL := Archer C20\n  DEVICE_VARIANT := v5\n  TPLINK_FLASHLAYOUT := 8MSUmtk\n  TPLINK_HWID := 0xc200005\n  TPLINK_HWREVADD := 0x5\n  DEVICE_PACKAGES := kmod-mt76x0e\n  IMAGES := sysupgrade.bin\nendef\nTARGET_DEVICES += tplink_archer-c20-v5\n\ndefine Device/tplink_archer-c50-v3\n  $(Device/tplink-v2)\n  IMAGE_SIZE := 7808k\n  DEVICE_MODEL := Archer C50\n  DEVICE_VARIANT := v3\n  TPLINK_FLASHLAYOUT := 8Mmtk\n  TPLINK_HWID := 0x001D9BA4\n  TPLINK_HWREV := 0x79\n  TPLINK_HWREVADD := 0x1\n  DEVICE_PACKAGES := kmod-mt76x2\n  IMAGES := sysupgrade.bin tftp-recovery.bin\n  IMAGE/tftp-recovery.bin := pad-extra 128k | $$(IMAGE/factory.bin)\n  SUPPORTED_DEVICES += tplink,c50-v3\nendef\nTARGET_DEVICES += tplink_archer-c50-v3\n\ndefine Device/tplink_archer-c50-v4\n  $(Device/tplink-v2)\n  IMAGE_SIZE := 7616k\n  DEVICE_MODEL := Archer C50\n  DEVICE_VARIANT := v4\n  TPLINK_FLASHLAYOUT := 8MSUmtk\n  TPLINK_HWID := 0x001D589B\n  TPLINK_HWREV := 0x93\n  TPLINK_HWREVADD := 0x2\n  DEVICE_PACKAGES := kmod-mt76x2\n  IMAGES := sysupgrade.bin\n  SUPPORTED_DEVICES += tplink,c50-v4\nendef\nTARGET_DEVICES += tplink_archer-c50-v4\n\ndefine Device/tplink_re200-v2\n  $(Device/tplink-safeloader)\n  IMAGE_SIZE := 7808k\n  DEVICE_MODEL := RE200\n  DEVICE_VARIANT := v2\n  DEVICE_PACKAGES := kmod-mt76x0e\n  TPLINK_BOARD_ID := RE200-V2\nendef\nTARGET_DEVICES += tplink_re200-v2\n\ndefine Device/tplink_re200-v3\n  $(Device/tplink-safeloader)\n  IMAGE_SIZE := 7808k\n  DEVICE_MODEL := RE200\n  DEVICE_VARIANT := v3\n  DEVICE_PACKAGES := kmod-mt76x0e\n  TPLINK_BOARD_ID := RE200-V3\nendef\nTARGET_DEVICES += tplink_re200-v3\n\ndefine Device/tplink_re200-v4\n  $(Device/tplink-safeloader)\n  IMAGE_SIZE := 7808k\n  DEVICE_MODEL := RE200\n  DEVICE_VARIANT := v4\n  DEVICE_PACKAGES := kmod-mt76x0e\n  TPLINK_BOARD_ID := RE200-V4\nendef\nTARGET_DEVICES += tplink_re200-v4\n\ndefine Device/tplink_re220-v2\n  $(Device/tplink-safeloader)\n  IMAGE_SIZE := 7808k\n  DEVICE_MODEL := RE220\n  DEVICE_VARIANT := v2\n  DEVICE_PACKAGES := kmod-mt76x0e\n  TPLINK_BOARD_ID := RE220-V2\nendef\nTARGET_DEVICES += tplink_re220-v2\n\ndefine Device/tplink_re305-v1\n  $(Device/tplink-safeloader)\n  IMAGE_SIZE := 6016k\n  DEVICE_MODEL := RE305\n  DEVICE_VARIANT := v1\n  DEVICE_PACKAGES := kmod-mt76x2\n  TPLINK_BOARD_ID := RE305-V1\nendef\nTARGET_DEVICES += tplink_re305-v1\n\ndefine Device/tplink_re305-v3\n  $(Device/tplink-safeloader)\n  IMAGE_SIZE := 7808k\n  DEVICE_MODEL := RE305\n  DEVICE_VARIANT := v3\n  DEVICE_PACKAGES := kmod-mt76x2\n  TPLINK_BOARD_ID := RE305-V3\nendef\nTARGET_DEVICES += tplink_re305-v3\n\ndefine Device/tplink_tl-mr3020-v3\n  $(Device/tplink-v2)\n  IMAGE_SIZE := 7808k\n  DEVICE_MODEL := TL-MR3020\n  DEVICE_VARIANT := v3\n  TPLINK_FLASHLAYOUT := 8Mmtk\n  TPLINK_HWID := 0x30200003\n  TPLINK_HWREV := 0x3\n  TPLINK_HWREVADD := 0x3\n  DEVICE_PACKAGES := kmod-usb2 kmod-usb-ohci kmod-usb-ledtrig-usbport\n  IMAGES := sysupgrade.bin tftp-recovery.bin\n  IMAGE/tftp-recovery.bin := pad-extra 128k | $$(IMAGE/factory.bin)\nendef\nTARGET_DEVICES += tplink_tl-mr3020-v3\n\ndefine Device/tplink_tl-mr3420-v5\n  $(Device/tplink-v2)\n  IMAGE_SIZE := 7808k\n  DEVICE_MODEL := TL-MR3420\n  DEVICE_VARIANT := v5\n  TPLINK_FLASHLAYOUT := 8Mmtk\n  TPLINK_HWID := 0x34200005\n  TPLINK_HWREV := 0x5\n  TPLINK_HWREVADD := 0x5\n  DEVICE_PACKAGES := kmod-usb2 kmod-usb-ohci kmod-usb-ledtrig-usbport\n  IMAGES := sysupgrade.bin tftp-recovery.bin\n  IMAGE/tftp-recovery.bin := pad-extra 128k | $$(IMAGE/factory.bin)\nendef\nTARGET_DEVICES += tplink_tl-mr3420-v5\n\ndefine Device/tplink_tl-mr6400-v4\n  $(Device/tplink-v2)\n  IMAGE_SIZE := 7808k\n  DEVICE_MODEL := TL-MR6400\n  DEVICE_VARIANT := v4\n  TPLINK_FLASHLAYOUT := 8Mmtk\n  TPLINK_HWID := 0x64000004\n  TPLINK_HWREV := 0x4\n  TPLINK_HWREVADD := 0x4\n  DEVICE_PACKAGES := kmod-usb2 kmod-usb-ohci kmod-usb-ledtrig-usbport \\\n\tkmod-usb-serial-option kmod-usb-net-qmi-wwan uqmi\n  IMAGES := sysupgrade.bin tftp-recovery.bin\n  IMAGE/tftp-recovery.bin := pad-extra 128k | $$(IMAGE/factory.bin)\nendef\nTARGET_DEVICES += tplink_tl-mr6400-v4\n\ndefine Device/tplink_tl-mr6400-v5\n  $(Device/tplink-v2)\n  IMAGE_SIZE := 7808k\n  DEVICE_MODEL := TL-MR6400\n  DEVICE_VARIANT := v5\n  TPLINK_FLASHLAYOUT := 8Mmtk\n  TPLINK_HWID := 0x64000005\n  TPLINK_HWREV := 0x5\n  TPLINK_HWREVADD := 0x5\n  DEVICE_PACKAGES := kmod-usb2 kmod-usb-ohci kmod-usb-ledtrig-usbport \\\n\tkmod-usb-serial-option kmod-usb-net-qmi-wwan uqmi\n  IMAGES := sysupgrade.bin tftp-recovery.bin\n  IMAGE/tftp-recovery.bin := pad-extra 128k | $$(IMAGE/factory.bin)\nendef\nTARGET_DEVICES += tplink_tl-mr6400-v5\n\ndefine Device/tplink_tl-wa801nd-v5\n  $(Device/tplink-v2)\n  IMAGE_SIZE := 7808k\n  DEVICE_MODEL := TL-WA801ND\n  DEVICE_VARIANT := v5\n  TPLINK_FLASHLAYOUT := 8Mmtk\n  TPLINK_HWID := 0x08010005\n  TPLINK_HWREVADD := 0x5\n  IMAGES := sysupgrade.bin tftp-recovery.bin\n  IMAGE/tftp-recovery.bin := pad-extra 128k | $$(IMAGE/factory.bin)\nendef\nTARGET_DEVICES += tplink_tl-wa801nd-v5\n\ndefine Device/tplink_tl-wr802n-v4\n  $(Device/tplink-v2)\n  IMAGE_SIZE := 7808k\n  DEVICE_MODEL := TL-WR802N\n  DEVICE_VARIANT := v4\n  TPLINK_FLASHLAYOUT := 8Mmtk\n  TPLINK_HWID := 0x08020004\n  TPLINK_HWREVADD := 0x4\n  IMAGES := sysupgrade.bin tftp-recovery.bin\n  IMAGE/tftp-recovery.bin := pad-extra 128k | $$(IMAGE/factory.bin)\nendef\nTARGET_DEVICES += tplink_tl-wr802n-v4\n\ndefine Device/tplink_tl-wr840n-v4\n  $(Device/tplink-v2)\n  IMAGE_SIZE := 7808k\n  DEVICE_MODEL := TL-WR840N\n  DEVICE_VARIANT := v4\n  TPLINK_FLASHLAYOUT := 8Mmtk\n  TPLINK_HWID := 0x08400004\n  TPLINK_HWREVADD := 0x4\n  IMAGES := sysupgrade.bin tftp-recovery.bin\n  IMAGE/tftp-recovery.bin := pad-extra 128k | $$(IMAGE/factory.bin)\n  SUPPORTED_DEVICES += tl-wr840n-v4\nendef\nTARGET_DEVICES += tplink_tl-wr840n-v4\n\ndefine Device/tplink_tl-wr840n-v5\n  $(Device/tplink-v2)\n  IMAGE_SIZE := 3904k\n  DEVICE_MODEL := TL-WR840N\n  DEVICE_VARIANT := v5\n  TPLINK_FLASHLAYOUT := 4Mmtk\n  TPLINK_HWID := 0x08400005\n  TPLINK_HWREVADD := 0x5\n  IMAGES := sysupgrade.bin\n  SUPPORTED_DEVICES += tl-wr840n-v5\n  DEFAULT := n\nendef\nTARGET_DEVICES += tplink_tl-wr840n-v5\n\ndefine Device/tplink_tl-wr841n-v13\n  $(Device/tplink-v2)\n  IMAGE_SIZE := 7808k\n  DEVICE_MODEL := TL-WR841N\n  DEVICE_VARIANT := v13\n  TPLINK_FLASHLAYOUT := 8Mmtk\n  TPLINK_HWID := 0x08410013\n  TPLINK_HWREV := 0x268\n  TPLINK_HWREVADD := 0x13\n  IMAGES := sysupgrade.bin tftp-recovery.bin\n  IMAGE/tftp-recovery.bin := pad-extra 128k | $$(IMAGE/factory.bin)\n  SUPPORTED_DEVICES += tl-wr841n-v13\nendef\nTARGET_DEVICES += tplink_tl-wr841n-v13\n\ndefine Device/tplink_tl-wr841n-v14\n  $(Device/tplink-v2)\n  IMAGE_SIZE := 3968k\n  DEVICE_MODEL := TL-WR841N\n  DEVICE_VARIANT := v14\n  TPLINK_FLASHLAYOUT := 4MLmtk\n  TPLINK_HWID := 0x08410014\n  TPLINK_HWREVADD := 0x14\n  IMAGES := sysupgrade.bin tftp-recovery.bin\n  IMAGE/tftp-recovery.bin := pad-extra 64k | $$(IMAGE/factory.bin)\n  DEFAULT := n\nendef\nTARGET_DEVICES += tplink_tl-wr841n-v14\n\ndefine Device/tplink_tl-wr842n-v5\n  $(Device/tplink-v2)\n  IMAGE_SIZE := 7808k\n  DEVICE_MODEL := TL-WR842N\n  DEVICE_VARIANT := v5\n  TPLINK_FLASHLAYOUT := 8Mmtk\n  TPLINK_HWID := 0x08420005\n  TPLINK_HWREV := 0x5\n  TPLINK_HWREVADD := 0x5\n  DEVICE_PACKAGES := kmod-usb2 kmod-usb-ohci kmod-usb-ledtrig-usbport\n  IMAGES := sysupgrade.bin tftp-recovery.bin\n  IMAGE/tftp-recovery.bin := pad-extra 128k | $$(IMAGE/factory.bin)\nendef\nTARGET_DEVICES += tplink_tl-wr842n-v5\n\ndefine Device/tplink_tl-wr850n-v2\n  $(Device/tplink-v2)\n  IMAGE_SIZE := 7808k\n  DEVICE_MODEL := TL-WR850N\n  DEVICE_VARIANT := v2\n  TPLINK_FLASHLAYOUT := 8Mmtk\n  TPLINK_HWID := 0x08500002\n  TPLINK_HWREVADD := 0x2\n  IMAGES := sysupgrade.bin tftp-recovery.bin\n  IMAGE/tftp-recovery.bin := pad-extra 128k | $$(IMAGE/factory.bin)\nendef\nTARGET_DEVICES += tplink_tl-wr850n-v2\n\ndefine Device/tplink_tl-wr902ac-v3\n  $(Device/tplink-v2)\n  IMAGE_SIZE := 7808k\n  DEVICE_MODEL := TL-WR902AC\n  DEVICE_VARIANT := v3\n  TPLINK_FLASHLAYOUT := 8Mmtk\n  TPLINK_HWID := 0x000dc88f\n  TPLINK_HWREV := 0x89\n  TPLINK_HWREVADD := 0x1\n  DEVICE_PACKAGES := kmod-mt76x0e kmod-usb2 kmod-usb-ohci \\\n\tkmod-usb-ledtrig-usbport\n  IMAGES := sysupgrade.bin tftp-recovery.bin\n  IMAGE/tftp-recovery.bin := pad-extra 128k | $$(IMAGE/factory.bin)\nendef\nTARGET_DEVICES += tplink_tl-wr902ac-v3\n\ndefine Device/unielec_u7628-01-16m\n  IMAGE_SIZE := 16064k\n  DEVICE_VENDOR := UniElec\n  DEVICE_MODEL := U7628-01\n  DEVICE_VARIANT := 16M\n  DEVICE_PACKAGES := kmod-usb2 kmod-usb-ohci kmod-usb-ledtrig-usbport\n  SUPPORTED_DEVICES += u7628-01-128M-16M unielec,u7628-01-128m-16m\nendef\nTARGET_DEVICES += unielec_u7628-01-16m\n\ndefine Device/vocore_vocore2\n  IMAGE_SIZE := 16064k\n  DEVICE_VENDOR := VoCore\n  DEVICE_MODEL := VoCore2\n  DEVICE_PACKAGES := kmod-usb2 kmod-usb-ohci kmod-usb-ledtrig-usbport \\\n\tkmod-sdhci-mt7620\n  SUPPORTED_DEVICES += vocore2\nendef\nTARGET_DEVICES += vocore_vocore2\n\ndefine Device/vocore_vocore2-lite\n  IMAGE_SIZE := 7872k\n  DEVICE_VENDOR := VoCore\n  DEVICE_MODEL := VoCore2-Lite\n  DEVICE_PACKAGES := kmod-usb2 kmod-usb-ohci kmod-usb-ledtrig-usbport \\\n\tkmod-sdhci-mt7620\n  SUPPORTED_DEVICES += vocore2lite\nendef\nTARGET_DEVICES += vocore_vocore2-lite\n\ndefine Device/wavlink_wl-wn531a3\n  IMAGE_SIZE := 7872k\n  DEVICE_VENDOR := Wavlink\n  DEVICE_MODEL := WL-WN531A3\n  DEVICE_ALT0_VENDOR := Wavlink\n  DEVICE_ALT0_MODEL := QUANTUM D4\n  DEVICE_PACKAGES := kmod-mt76x2 kmod-usb2 kmod-usb-ohci\n  SUPPORTED_DEVICES += wl-wn531a3\nendef\nTARGET_DEVICES += wavlink_wl-wn531a3\n\ndefine Device/wavlink_wl-wn570ha1\n  IMAGE_SIZE := 7872k\n  DEVICE_VENDOR := Wavlink\n  DEVICE_MODEL := WL-WN570HA1\n  DEVICE_PACKAGES := kmod-mt76x0e\nendef\nTARGET_DEVICES += wavlink_wl-wn570ha1\n\ndefine Device/wavlink_wl-wn575a3\n  IMAGE_SIZE := 7872k\n  DEVICE_VENDOR := Wavlink\n  DEVICE_MODEL := WL-WN575A3\n  DEVICE_PACKAGES := kmod-mt76x2\n  SUPPORTED_DEVICES += wl-wn575a3\nendef\nTARGET_DEVICES += wavlink_wl-wn575a3\n\ndefine Device/wavlink_wl-wn576a2\n  IMAGE_SIZE := 7872k\n  DEVICE_VENDOR := Wavlink\n  DEVICE_MODEL := WL-WN576A2\n  DEVICE_ALT0_VENDOR := Silvercrest\n  DEVICE_ALT0_MODEL := SWV 733 B1\n  DEVICE_PACKAGES := kmod-mt76x0e\nendef\nTARGET_DEVICES += wavlink_wl-wn576a2\n\ndefine Device/wavlink_wl-wn577a2\n  IMAGE_SIZE := 7872k\n  DEVICE_VENDOR := Wavlink\n  DEVICE_MODEL := WL-WN577A2\n  DEVICE_ALT0_VENDOR := Maginon\n  DEVICE_ALT0_MODEL := WLR-755\n  DEVICE_PACKAGES := kmod-mt76x0e\nendef\nTARGET_DEVICES += wavlink_wl-wn577a2\n\ndefine Device/wavlink_wl-wn578a2\n  IMAGE_SIZE := 7872k\n  DEVICE_VENDOR := Wavlink\n  DEVICE_MODEL := WL-WN578A2\n  DEVICE_ALT0_VENDOR := SilverCrest\n  DEVICE_ALT0_MODEL := SWV 733 A2\n  DEVICE_PACKAGES := kmod-mt76x0e\nendef\nTARGET_DEVICES += wavlink_wl-wn578a2\n\ndefine Device/widora_neo-16m\n  IMAGE_SIZE := 16064k\n  DEVICE_VENDOR := Widora\n  DEVICE_MODEL := Widora-NEO\n  DEVICE_VARIANT := 16M\n  DEVICE_PACKAGES := kmod-usb2 kmod-usb-ohci\n  SUPPORTED_DEVICES += widora-neo\nendef\nTARGET_DEVICES += widora_neo-16m\n\ndefine Device/widora_neo-32m\n  IMAGE_SIZE := 32448k\n  DEVICE_VENDOR := Widora\n  DEVICE_MODEL := Widora-NEO\n  DEVICE_VARIANT := 32M\n  DEVICE_PACKAGES := kmod-usb2 kmod-usb-ohci\nendef\nTARGET_DEVICES += widora_neo-32m\n\ndefine Device/wiznet_wizfi630s\n  IMAGE_SIZE := 32448k\n  DEVICE_VENDOR := WIZnet\n  DEVICE_MODEL := WizFi630S\n  SUPPORTED_DEVICES += wizfi630s\nendef\nTARGET_DEVICES += wiznet_wizfi630s\n\ndefine Device/wrtnode_wrtnode2p\n  IMAGE_SIZE := 32448k\n  DEVICE_VENDOR := WRTnode\n  DEVICE_MODEL := WRTnode 2P\n  DEVICE_PACKAGES := kmod-usb2 kmod-usb-ohci kmod-usb-ledtrig-usbport\n  SUPPORTED_DEVICES += wrtnode2p\nendef\nTARGET_DEVICES += wrtnode_wrtnode2p\n\ndefine Device/wrtnode_wrtnode2r\n  IMAGE_SIZE := 32448k\n  DEVICE_VENDOR := WRTnode\n  DEVICE_MODEL := WRTnode 2R\n  DEVICE_PACKAGES := kmod-usb2 kmod-usb-ohci\n  SUPPORTED_DEVICES += wrtnode2r\nendef\nTARGET_DEVICES += wrtnode_wrtnode2r\n\ndefine Device/xiaomi_mi-router-4a-100m\n  IMAGE_SIZE := 14976k\n  DEVICE_VENDOR := Xiaomi\n  DEVICE_MODEL := Mi Router 4A\n  DEVICE_VARIANT := 100M Edition\n  DEVICE_PACKAGES := kmod-mt76x2\n  SUPPORTED_DEVICES += xiaomi,mir4a-100m\nendef\nTARGET_DEVICES += xiaomi_mi-router-4a-100m\n\ndefine Device/xiaomi_mi-router-4c\n  IMAGE_SIZE := 14976k\n  DEVICE_VENDOR := Xiaomi\n  DEVICE_MODEL := Mi Router 4C\n  DEVICE_PACKAGES := uboot-envtools\nendef\nTARGET_DEVICES += xiaomi_mi-router-4c\n\ndefine Device/xiaomi_miwifi-3c\n  IMAGE_SIZE := 15104k\n  DEVICE_VENDOR := Xiaomi\n  DEVICE_MODEL := MiWiFi 3C\n  DEVICE_PACKAGES := uboot-envtools\nendef\nTARGET_DEVICES += xiaomi_miwifi-3c\n\ndefine Device/xiaomi_miwifi-nano\n  IMAGE_SIZE := 16064k\n  DEVICE_VENDOR := Xiaomi\n  DEVICE_MODEL := MiWiFi Nano\n  DEVICE_PACKAGES := uboot-envtools\n  SUPPORTED_DEVICES += miwifi-nano\nendef\nTARGET_DEVICES += xiaomi_miwifi-nano\n\ndefine Device/zbtlink_zbt-we1226\n  IMAGE_SIZE := 7872k\n  DEVICE_VENDOR := Zbtlink\n  DEVICE_MODEL := ZBT-WE1226\nendef\nTARGET_DEVICES += zbtlink_zbt-we1226\n\ndefine Device/zyxel_keenetic-extra-ii\n  IMAGE_SIZE := 14912k\n  BLOCKSIZE := 64k\n  DEVICE_VENDOR := ZyXEL\n  DEVICE_MODEL := Keenetic Extra II\n  DEVICE_PACKAGES := kmod-mt76x2 kmod-usb2 kmod-usb-ohci \\\n\tkmod-usb-ledtrig-usbport\n  IMAGES += factory.bin\n  IMAGE/factory.bin := $$(sysupgrade_bin) | pad-to $$$$(BLOCKSIZE) | \\\n\tcheck-size | zyimage -d 6162 -v \"ZyXEL Keenetic Extra II\"\nendef\nTARGET_DEVICES += zyxel_keenetic-extra-ii\n"
  },
  {
    "path": "target/linux/ramips/image/rt288x.mk",
    "content": "#\n# RT288X Profiles\n#\n\nDEFAULT_SOC := rt2880\n\ndefine Build/gemtek-header\n\tif [ -f $@ ]; then \\\n\t\tmkheader_gemtek $@ $@.new $(1) && \\\n\t\tmv $@.new $@; \\\n\tfi\nendef\n\ndefine Device/airlink101_ar670w\n  BLOCKSIZE := 64k\n  DEVICE_VENDOR := Airlink\n  DEVICE_MODEL := AR670W\n  IMAGE_SIZE := 3840k\n  KERNEL := $(KERNEL_DTB) | pad-to $$(BLOCKSIZE)\n  IMAGES += factory.bin\n  IMAGE/factory.bin := $$(sysupgrade_bin) | check-size | \\\n\twrg-header wrgn16a_airlink_ar670w\n  SUPPORTED_DEVICES += ar670w\n  DEFAULT := n\nendef\nTARGET_DEVICES += airlink101_ar670w\n\ndefine Device/airlink101_ar725w\n  IMAGE_SIZE := 3776k\n  DEVICE_VENDOR := Airlink\n  DEVICE_MODEL := AR725W\n  IMAGES += factory.bin\n  IMAGE/factory.bin := $$(sysupgrade_bin) | check-size 3328k | \\\n\tgemtek-header ar725w\n  SUPPORTED_DEVICES += ar725w\n  DEFAULT := n\nendef\nTARGET_DEVICES += airlink101_ar725w\n\ndefine Device/asus_rt-n15\n  BLOCKSIZE := 64k\n  IMAGE_SIZE := 3776k\n  DEVICE_VENDOR := Asus\n  DEVICE_MODEL := RT-N15\n  DEVICE_PACKAGES := kmod-switch-rtl8366s\n  SUPPORTED_DEVICES += rt-n15\n  DEFAULT := n\nendef\nTARGET_DEVICES += asus_rt-n15\n\ndefine Device/belkin_f5d8235-v1\n  IMAGE_SIZE := 7872k\n  DEVICE_VENDOR := Belkin\n  DEVICE_MODEL := F5D8235\n  DEVICE_VARIANT := V1\n  DEVICE_PACKAGES := kmod-switch-rtl8366s kmod-usb-ohci kmod-usb-ohci-pci \\\n\tkmod-usb2 kmod-usb2-pci kmod-usb-ledtrig-usbport\n  SUPPORTED_DEVICES += f5d8235-v1\nendef\nTARGET_DEVICES += belkin_f5d8235-v1\n\ndefine Device/buffalo_wli-tx4-ag300n\n  BLOCKSIZE := 64k\n  IMAGE_SIZE := 3776k\n  DEVICE_VENDOR := Buffalo\n  DEVICE_MODEL := WLI-TX4-AG300N\n  DEVICE_PACKAGES := kmod-switch-ip17xx\n  SUPPORTED_DEVICES += wli-tx4-ag300n\n  DEFAULT := n\nendef\nTARGET_DEVICES += buffalo_wli-tx4-ag300n\n\ndefine Device/buffalo_wzr-agl300nh\n  BLOCKSIZE := 64k\n  IMAGE_SIZE := 3776k\n  DEVICE_VENDOR := Buffalo\n  DEVICE_MODEL := WZR-AGL300NH\n  DEVICE_PACKAGES := kmod-switch-rtl8366s\n  SUPPORTED_DEVICES += wzr-agl300nh\n  DEFAULT := n\nendef\nTARGET_DEVICES += buffalo_wzr-agl300nh\n\ndefine Device/dlink_dap-1522-a1\n  BLOCKSIZE := 64k\n  IMAGE_SIZE := 3712k\n  DEVICE_VENDOR := D-Link\n  DEVICE_MODEL := DAP-1522\n  DEVICE_VARIANT := A1\n  DEVICE_PACKAGES := kmod-switch-rtl8366s\n  KERNEL := $(KERNEL_DTB)\n  IMAGES += factory.bin\n  IMAGE/factory.bin := append-kernel | pad-offset $$$$(BLOCKSIZE) 96 | \\\n\tappend-rootfs | pad-rootfs -x 96 | wrg-header wapnd01_dlink_dap1522 | \\\n\tcheck-size\n  DEFAULT := n\nendef\nTARGET_DEVICES += dlink_dap-1522-a1\n\ndefine Device/ralink_v11st-fe\n  BLOCKSIZE := 64k\n  IMAGE_SIZE := 3776k\n  DEVICE_VENDOR := Ralink\n  DEVICE_MODEL := V11ST-FE\n  SUPPORTED_DEVICES += v11st-fe\n  DEFAULT := n\nendef\nTARGET_DEVICES += ralink_v11st-fe\n"
  },
  {
    "path": "target/linux/ramips/image/rt305x.mk",
    "content": "#\n# RT305X Profiles\n#\ndefine Build/buffalo-tftp-header\n\t( \\\n\t\techo -n -e \"# Airstation FirmWare\\nrun u_fw\\nreset\\n\\n\" | \\\n\t\t\tdd bs=512 count=1 conv=sync; \\\n\t\tdd if=$@; \\\n\t) > $@.tmp && \\\n\t$(STAGING_DIR_HOST)/bin/buffalo-tftp -i $@.tmp -o $@.new\n\tmv $@.new $@\nendef\n\ndefine Build/dap-header\n\t$(STAGING_DIR_HOST)/bin/mkdapimg $(1) -i $@ -o $@.new\n\tmv $@.new $@\nendef\n\ndefine Build/hilink-header\n\t$(STAGING_DIR_HOST)/bin/mkhilinkfw -e -i $@ -o $@.new\n\tmv $@.new $@\nendef\n\ndefine Device/7links_px-4885-4m\n  SOC := rt5350\n  IMAGE_SIZE := 3776k\n  DEVICE_VENDOR := 7Links\n  DEVICE_MODEL := PX-4885\n  DEVICE_VARIANT := 4M\n  DEVICE_PACKAGES := kmod-usb-dwc2 kmod-usb2 kmod-usb-ohci \\\n\tkmod-usb-ledtrig-usbport kmod-leds-gpio\n  SUPPORTED_DEVICES += px-4885-4M\n  DEFAULT := n\nendef\nTARGET_DEVICES += 7links_px-4885-4m\n\ndefine Device/7links_px-4885-8m\n  SOC := rt5350\n  IMAGE_SIZE := 7872k\n  DEVICE_VENDOR := 7Links\n  DEVICE_MODEL := PX-4885\n  DEVICE_VARIANT := 8M\n  DEVICE_PACKAGES := kmod-usb-dwc2 kmod-usb2 kmod-usb-ohci \\\n\tkmod-usb-ledtrig-usbport kmod-leds-gpio\n  SUPPORTED_DEVICES += px-4885-8M\nendef\nTARGET_DEVICES += 7links_px-4885-8m\n\ndefine Device/8devices_carambola\n  SOC := rt3050\n  IMAGE_SIZE := 7872k\n  DEVICE_VENDOR := 8devices\n  DEVICE_MODEL := Carambola\n  DEVICE_PACKAGES :=\n  SUPPORTED_DEVICES += carambola\nendef\nTARGET_DEVICES += 8devices_carambola\n\ndefine Device/accton_wr6202\n  SOC := rt3052\n  IMAGE_SIZE := 7872k\n  DEVICE_VENDOR := Accton\n  DEVICE_MODEL := WR6202\n  SUPPORTED_DEVICES += wr6202\nendef\nTARGET_DEVICES += accton_wr6202\n\ndefine Device/airlive_air3gii\n  SOC := rt5350\n  BLOCKSIZE := 64k\n  IMAGE_SIZE := 3776k\n  DEVICE_VENDOR := AirLive\n  DEVICE_MODEL := Air3GII\n  SUPPORTED_DEVICES += air3gii\n  DEFAULT := n\nendef\nTARGET_DEVICES += airlive_air3gii\n\ndefine Device/alfa-network_w502u\n  SOC := rt3052\n  IMAGE_SIZE := 7872k\n  DEVICE_VENDOR := ALFA\n  DEVICE_MODEL := Networks W502U\n  SUPPORTED_DEVICES += w502u\nendef\nTARGET_DEVICES += alfa-network_w502u\n\ndefine Device/allnet_all0256n-4m\n  SOC := rt3050\n  IMAGE_SIZE := 3776k\n  DEVICE_VENDOR := Allnet\n  DEVICE_MODEL := ALL0256N\n  DEVICE_VARIANT := 4M\n  DEVICE_PACKAGES := rssileds\n  SUPPORTED_DEVICES += all0256n-4M\n  DEFAULT := n\nendef\nTARGET_DEVICES += allnet_all0256n-4m\n\ndefine Device/allnet_all0256n-8m\n  SOC := rt3050\n  IMAGE_SIZE := 7872k\n  DEVICE_VENDOR := Allnet\n  DEVICE_MODEL := ALL0256N\n  DEVICE_VARIANT := 8M\n  DEVICE_PACKAGES := rssileds\n  SUPPORTED_DEVICES += all0256n-8M\nendef\nTARGET_DEVICES += allnet_all0256n-8m\n\ndefine Device/allnet_all5002\n  SOC := rt3352\n  IMAGE_SIZE := 32448k\n  DEVICE_VENDOR := Allnet\n  DEVICE_MODEL := ALL5002\n  DEVICE_PACKAGES := kmod-usb-ohci kmod-usb2 kmod-usb-ledtrig-usbport \\\n\tkmod-i2c-gpio kmod-hwmon-lm92 kmod-gpio-pcf857x\n  SUPPORTED_DEVICES += all5002\nendef\nTARGET_DEVICES += allnet_all5002\n\ndefine Device/allnet_all5003\n  SOC := rt5350\n  IMAGE_SIZE := 32448k\n  DEVICE_VENDOR := Allnet\n  DEVICE_MODEL := ALL5003\n  DEVICE_PACKAGES := kmod-usb-ohci kmod-usb2 kmod-usb-ledtrig-usbport \\\n\tkmod-i2c-gpio kmod-hwmon-lm92 kmod-gpio-pcf857x\n  SUPPORTED_DEVICES += all5003\nendef\nTARGET_DEVICES += allnet_all5003\n\ndefine Device/alphanetworks_asl26555-16m\n  SOC := rt3050\n  IMAGE_SIZE := 15872k\n  DEVICE_VENDOR := Alpha\n  DEVICE_MODEL := ASL26555\n  DEVICE_VARIANT := 16M\n  DEVICE_PACKAGES := kmod-usb-dwc2 kmod-usb-ledtrig-usbport\n  SUPPORTED_DEVICES += asl26555 asl26555-16M\nendef\nTARGET_DEVICES += alphanetworks_asl26555-16m\n\ndefine Device/alphanetworks_asl26555-8m\n  SOC := rt3050\n  IMAGE_SIZE := 7744k\n  DEVICE_VENDOR := Alpha\n  DEVICE_MODEL := ASL26555\n  DEVICE_PACKAGES := kmod-usb-dwc2 kmod-usb-ledtrig-usbport\n  SUPPORTED_DEVICES += asl26555 asl26555-8M\nendef\nTARGET_DEVICES += alphanetworks_asl26555-8m\n\ndefine Device/arcwireless_freestation5\n  SOC := rt3050\n  IMAGE_SIZE := 7872k\n  DEVICE_VENDOR := ARC Wireless\n  DEVICE_MODEL := FreeStation\n  DEVICE_PACKAGES := kmod-usb-dwc2 kmod-rt2500-usb kmod-rt2800-usb \\\n\tkmod-rt2x00-usb\n  SUPPORTED_DEVICES += freestation5\nendef\nTARGET_DEVICES += arcwireless_freestation5\n\ndefine Device/argus_atp-52b\n  SOC := rt3052\n  IMAGE_SIZE := 7808k\n  DEVICE_VENDOR := Argus\n  DEVICE_MODEL := ATP-52B\n  SUPPORTED_DEVICES += atp-52b\nendef\nTARGET_DEVICES += argus_atp-52b\n\ndefine Device/asiarf_awapn2403\n  SOC := rt3052\n  BLOCKSIZE := 4k\n  IMAGE_SIZE := 3776k\n  DEVICE_VENDOR := AsiaRF\n  DEVICE_MODEL := AWAPN2403\n  SUPPORTED_DEVICES += awapn2403\n  DEFAULT := n\nendef\nTARGET_DEVICES += asiarf_awapn2403\n\ndefine Device/asiarf_awm002-evb-4m\n  SOC := rt5350\n  IMAGE_SIZE := 3776k\n  DEVICE_VENDOR := AsiaRF\n  DEVICE_MODEL := AWM002-EVB\n  DEVICE_VARIANT := 4M\n  DEVICE_PACKAGES := kmod-usb-ohci kmod-usb2 kmod-i2c-gpio\n  SUPPORTED_DEVICES += awm002-evb-4M\n  DEFAULT := n\nendef\nTARGET_DEVICES += asiarf_awm002-evb-4m\n\ndefine Device/asiarf_awm002-evb-8m\n  SOC := rt5350\n  IMAGE_SIZE := 7872k\n  DEVICE_VENDOR := AsiaRF\n  DEVICE_MODEL := AWM002-EVB/AWM003-EVB\n  DEVICE_VARIANT := 8M\n  DEVICE_PACKAGES := kmod-usb-ohci kmod-usb2 kmod-i2c-gpio\n  SUPPORTED_DEVICES += awm002-evb-8M\nendef\nTARGET_DEVICES += asiarf_awm002-evb-8m\n\ndefine Device/asus_rt-g32-b1\n  SOC := rt3050\n  BLOCKSIZE := 4k\n  IMAGE_SIZE := 3776k\n  DEVICE_VENDOR := Asus\n  DEVICE_MODEL := RT-G32\n  DEVICE_VARIANT := B1\n  SUPPORTED_DEVICES += rt-g32-b1\n  DEFAULT := n\nendef\nTARGET_DEVICES += asus_rt-g32-b1\n\ndefine Device/asus_rt-n10-plus\n  SOC := rt3050\n  BLOCKSIZE := 64k\n  IMAGE_SIZE := 3776k\n  DEVICE_VENDOR := Asus\n  DEVICE_MODEL := RT-N10+\n  SUPPORTED_DEVICES += rt-n10-plus\n  DEFAULT := n\nendef\nTARGET_DEVICES += asus_rt-n10-plus\n\ndefine Device/asus_rt-n13u\n  SOC := rt3052\n  IMAGE_SIZE := 7872k\n  DEVICE_VENDOR := Asus\n  DEVICE_MODEL := RT-N13U\n  DEVICE_PACKAGES := kmod-leds-gpio kmod-rt2800-pci kmod-usb-dwc2\n  SUPPORTED_DEVICES += rt-n13u\nendef\nTARGET_DEVICES += asus_rt-n13u\n\ndefine Device/asus_wl-330n\n  SOC := rt3050\n  BLOCKSIZE := 4k\n  IMAGE_SIZE := 3776k\n  DEVICE_VENDOR := Asus\n  DEVICE_MODEL := WL-330N\n  SUPPORTED_DEVICES += wl-330n\n  DEFAULT := n\nendef\nTARGET_DEVICES += asus_wl-330n\n\ndefine Device/asus_wl-330n3g\n  SOC := rt3050\n  BLOCKSIZE := 4k\n  IMAGE_SIZE := 3776k\n  DEVICE_VENDOR := Asus\n  DEVICE_MODEL := WL-330N3G\n  DEVICE_PACKAGES :=\n  SUPPORTED_DEVICES += wl-330n3g\n  DEFAULT := n\nendef\nTARGET_DEVICES += asus_wl-330n3g\n\ndefine Device/aximcom_mr-102n\n  SOC := rt3052\n  IMAGE_SIZE := 7744k\n  DEVICE_VENDOR := AXIMCom\n  DEVICE_MODEL := MR-102N\n  SUPPORTED_DEVICES += mr-102n\nendef\nTARGET_DEVICES += aximcom_mr-102n\n\ndefine Device/aztech_hw550-3g\n  SOC := rt3052\n  IMAGE_SIZE := 7872k\n  DEVICE_VENDOR := Aztech\n  DEVICE_MODEL := HW550-3G\n  DEVICE_ALT0_VENDOR := Allnet\n  DEVICE_ALT0_MODEL := ALL0239-3G\n  DEVICE_PACKAGES := kmod-usb-dwc2 kmod-usb-ledtrig-usbport\n  SUPPORTED_DEVICES += hw550-3g\nendef\nTARGET_DEVICES += aztech_hw550-3g\n\ndefine Device/belkin_f5d8235-v2\n  SOC := rt3052\n  IMAGE_SIZE := 7744k\n  DEVICE_VENDOR := Belkin\n  DEVICE_MODEL := F5D8235\n  DEVICE_VARIANT := v2\n  DEVICE_PACKAGES := kmod-switch-rtl8366rb\n  SUPPORTED_DEVICES += f5d8235-v2\nendef\nTARGET_DEVICES += belkin_f5d8235-v2\n\ndefine Device/belkin_f7c027\n  SOC := rt5350\n  IMAGE_SIZE := 7616k\n  DEVICE_VENDOR := Belkin\n  DEVICE_MODEL := F7C027\n  SUPPORTED_DEVICES += f7c027\nendef\nTARGET_DEVICES += belkin_f7c027\n\ndefine Device/buffalo_whr-g300n\n  SOC := rt3052\n  BLOCKSIZE := 64k\n  IMAGE_SIZE := 3712k\n  DEVICE_VENDOR := Buffalo\n  DEVICE_MODEL := WHR-G300N\n  IMAGES += tftp.bin\n  IMAGE/tftp.bin := $$(sysupgrade_bin) | check-size | buffalo-tftp-header\n  SUPPORTED_DEVICES += whr-g300n\n  DEFAULT := n\nendef\nTARGET_DEVICES += buffalo_whr-g300n\n\ndefine Device/dlink_dap-1350\n  SOC := rt3052\n  IMAGES += factory.bin factory-NA.bin\n  IMAGE_SIZE := 7488k\n  IMAGE/factory.bin := $$(sysupgrade_bin) | check-size | \\\n\tdap-header -s RT3052-AP-DAP1350WW-3\n  IMAGE/factory-NA.bin := $$(sysupgrade_bin) | check-size | \\\n\tdap-header -s RT3052-AP-DAP1350-3\n  DEVICE_VENDOR := D-Link\n  DEVICE_MODEL := DAP-1350\n  SUPPORTED_DEVICES += dap-1350\nendef\nTARGET_DEVICES += dlink_dap-1350\n\ndefine Device/dlink_dcs-930\n  SOC := rt3050\n  IMAGE_SIZE := 3776k\n  DEVICE_VENDOR := D-Link\n  DEVICE_MODEL := DCS-930\n  DEVICE_PACKAGES := kmod-video-core kmod-video-uvc kmod-sound-core \\\n\tkmod-usb-audio kmod-usb-dwc2\n  SUPPORTED_DEVICES += dcs-930\n  DEFAULT := n\nendef\nTARGET_DEVICES += dlink_dcs-930\n\ndefine Device/dlink_dcs-930l-b1\n  SOC := rt5350\n  IMAGE_SIZE := 3776k\n  DEVICE_VENDOR := D-Link\n  DEVICE_MODEL := DCS-930L\n  DEVICE_VARIANT := B1\n  DEVICE_PACKAGES := kmod-video-core kmod-video-uvc kmod-sound-core \\\n\tkmod-usb-audio kmod-usb-ohci kmod-usb2\n  SUPPORTED_DEVICES += dcs-930l-b1\n  DEFAULT := n\nendef\nTARGET_DEVICES += dlink_dcs-930l-b1\n\ndefine Device/dlink_dir-300-b1\n  SOC := rt3050\n  IMAGE_SIZE := 3776k\n  IMAGES += factory.bin\n  IMAGE/factory.bin := $$(sysupgrade_bin) | check-size | \\\n\twrg-header wrgn23_dlwbr_dir300b\n  DEVICE_VENDOR := D-Link\n  DEVICE_MODEL := DIR-300\n  DEVICE_VARIANT := B1\n  SUPPORTED_DEVICES += dir-300-b1\n  DEFAULT := n\nendef\nTARGET_DEVICES += dlink_dir-300-b1\n\ndefine Device/dlink_dir-300-b7\n  SOC := rt5350\n  BLOCKSIZE := 4k\n  IMAGE_SIZE := 7872k\n  DEVICE_VENDOR := D-Link\n  DEVICE_MODEL := DIR-300\n  DEVICE_VARIANT := B7\n  SUPPORTED_DEVICES += dir-300-b7\nendef\nTARGET_DEVICES += dlink_dir-300-b7\n\ndefine Device/dlink_dir-320-b1\n  SOC := rt5350\n  IMAGE_SIZE := 7872k\n  DEVICE_VENDOR := D-Link\n  DEVICE_MODEL := DIR-320\n  DEVICE_VARIANT := B1\n  SUPPORTED_DEVICES += dir-320-b1\nendef\nTARGET_DEVICES += dlink_dir-320-b1\n\ndefine Device/dlink_dir-600-b1\n  SOC := rt3050\n  IMAGE_SIZE := 3776k\n  IMAGES += factory.bin\n  IMAGE/factory.bin := $$(sysupgrade_bin) | check-size | \\\n\twrg-header wrgn23_dlwbr_dir600b\n  DEVICE_VENDOR := D-Link\n  DEVICE_MODEL := DIR-600\n  DEVICE_VARIANT := B1/B2\n  SUPPORTED_DEVICES += dir-600-b1 dir-600-b2\n  DEFAULT := n\nendef\nTARGET_DEVICES += dlink_dir-600-b1\n\ndefine Device/dlink_dir-610-a1\n  $(Device/seama)\n  SOC := rt5350\n  BLOCKSIZE := 4k\n  SEAMA_SIGNATURE := wrgn59_dlob.hans_dir610\n  KERNEL := $(KERNEL_DTB)\n  IMAGE_SIZE := 3776k\n  DEVICE_VENDOR := D-Link\n  DEVICE_MODEL := DIR-610\n  DEVICE_VARIANT := A1\n  SUPPORTED_DEVICES += dir-610-a1\n  DEFAULT := n\nendef\nTARGET_DEVICES += dlink_dir-610-a1\n\ndefine Device/dlink_dir-615-d\n  SOC := rt3050\n  IMAGE_SIZE := 3776k\n  IMAGES += factory.bin\n  IMAGE/factory.bin := $$(sysupgrade_bin) | check-size | \\\n\twrg-header wrgn23_dlwbr_dir615d\n  DEVICE_VENDOR := D-Link\n  DEVICE_MODEL := DIR-615\n  DEVICE_VARIANT := D\n  SUPPORTED_DEVICES += dir-615-d\n  DEFAULT := n\nendef\nTARGET_DEVICES += dlink_dir-615-d\n\ndefine Device/dlink_dir-615-h1\n  $(Device/uimage-lzma-loader)\n  SOC := rt3352\n  BLOCKSIZE := 4k\n  IMAGES += factory.bin\n  IMAGE_SIZE := 3776k\n  IMAGE/factory.bin := $$(sysupgrade_bin) | senao-header -r 0x218 -p 0x30 -t 3\n  DEVICE_VENDOR := D-Link\n  DEVICE_MODEL := DIR-615\n  DEVICE_VARIANT := H1\n  SUPPORTED_DEVICES += dir-615-h1\n  DEFAULT := n\nendef\nTARGET_DEVICES += dlink_dir-615-h1\n\ndefine Device/dlink_dir-620-a1\n  SOC := rt3050\n  IMAGE_SIZE := 7872k\n  DEVICE_VENDOR := D-Link\n  DEVICE_MODEL := DIR-620\n  DEVICE_VARIANT := A1\n  SUPPORTED_DEVICES += dir-620-a1\nendef\nTARGET_DEVICES += dlink_dir-620-a1\n\ndefine Device/dlink_dir-620-d1\n  SOC := rt3352\n  IMAGE_SIZE := 7872k\n  DEVICE_VENDOR := D-Link\n  DEVICE_MODEL := DIR-620\n  DEVICE_VARIANT := D1\n  SUPPORTED_DEVICES += dir-620-d1\nendef\nTARGET_DEVICES += dlink_dir-620-d1\n\ndefine Device/dlink_dwr-512-b\n  SOC := rt5350\n  IMAGE_SIZE := 8064k\n  DEVICE_VENDOR := D-Link\n  DEVICE_MODEL := DWR-512\n  DEVICE_VARIANT := B\n  DEVICE_PACKAGES := jboot-tools kmod-usb2 kmod-spi-dev \\\n\tkmod-usb-serial-option kmod-usb-net-cdc-ether comgt-ncm\n  DLINK_ROM_ID := DLK6E2412001\n  DLINK_FAMILY_MEMBER := 0x6E24\n  DLINK_FIRMWARE_SIZE := 0x7E0000\n  KERNEL := $(KERNEL_DTB)\n  IMAGES += factory.bin\n  IMAGE/sysupgrade.bin := mkdlinkfw | pad-rootfs | append-metadata\n  IMAGE/factory.bin := mkdlinkfw | pad-rootfs | mkdlinkfw-factory\n  SUPPORTED_DEVICES += dwr-512-b\nendef\nTARGET_DEVICES += dlink_dwr-512-b\n\ndefine Device/easyacc_wizard-8800\n  SOC := rt5350\n  IMAGE_SIZE := 7872k\n  UIMAGE_NAME:= Linux Kernel Image\n  DEVICE_VENDOR := EasyAcc\n  DEVICE_MODEL := WIZARD 8800\n  SUPPORTED_DEVICES += wizard8800\nendef\nTARGET_DEVICES += easyacc_wizard-8800\n\ndefine Device/edimax_3g-6200n\n  SOC := rt3050\n  IMAGE_SIZE := 3648k\n  IMAGE/sysupgrade.bin := append-kernel | append-rootfs | \\\n\tedimax-header -s CSYS -m 3G62 -f 0x50000 -S 0x01100000 | pad-rootfs | \\\n\tcheck-size | append-metadata\n  DEVICE_VENDOR := Edimax\n  DEVICE_MODEL := 3g-6200n\n  SUPPORTED_DEVICES += 3g-6200n\n  DEFAULT := n\nendef\nTARGET_DEVICES += edimax_3g-6200n\n\ndefine Device/edimax_3g-6200nl\n  SOC := rt3050\n  IMAGE_SIZE := 3648k\n  IMAGE/sysupgrade.bin := append-kernel | append-rootfs | \\\n\tedimax-header -s CSYS -m 3G62 -f 0x50000 -S 0x01100000 | pad-rootfs | \\\n\tcheck-size | append-metadata\n  DEVICE_VENDOR := Edimax\n  DEVICE_MODEL := 3g-6200nl\n  SUPPORTED_DEVICES += 3g-6200nl\n  DEFAULT := n\nendef\nTARGET_DEVICES += edimax_3g-6200nl\n\ndefine Device/engenius_esr-9753\n  SOC := rt3052\n  BLOCKSIZE := 64k\n  IMAGE_SIZE := 3776k\n  DEVICE_VENDOR := EnGenius\n  DEVICE_MODEL := ESR-9753\n  SUPPORTED_DEVICES += esr-9753\n  DEFAULT := n\nendef\nTARGET_DEVICES += engenius_esr-9753\n\ndefine Device/fon_fonera-20n\n  SOC := rt3052\n  IMAGE_SIZE := 7872k\n  IMAGES += factory.bin\n  IMAGE/factory.bin := $$(sysupgrade_bin) | \\\n\tedimax-header -s RSDK -m NL1T -f 0x50000 -S 0xc0000\n  DEVICE_VENDOR := Fon\n  DEVICE_MODEL := Fonera 2.0N\n  DEVICE_PACKAGES := kmod-usb-dwc2 kmod-usb-ledtrig-usbport\n  SUPPORTED_DEVICES += fonera20n\nendef\nTARGET_DEVICES += fon_fonera-20n\n\ndefine Device/hame_mpr-a1\n  SOC := rt5350\n  BLOCKSIZE := 4k\n  IMAGE_SIZE := 3776k\n  UIMAGE_NAME:= Linux Kernel Image\n  DEVICE_VENDOR := HAME\n  DEVICE_MODEL := MPR\n  DEVICE_VARIANT := A1\n  DEVICE_PACKAGES := kmod-usb-ohci kmod-usb2\n  SUPPORTED_DEVICES += mpr-a1\n  DEFAULT := n\nendef\nTARGET_DEVICES += hame_mpr-a1\n\ndefine Device/hame_mpr-a2\n  SOC := rt5350\n  IMAGE_SIZE := 7872k\n  UIMAGE_NAME:= Linux Kernel Image\n  DEVICE_VENDOR := HAME\n  DEVICE_MODEL := MPR\n  DEVICE_VARIANT := A2\n  DEVICE_PACKAGES := kmod-usb-ohci kmod-usb2\n  SUPPORTED_DEVICES += mpr-a2\nendef\nTARGET_DEVICES += hame_mpr-a2\n\ndefine Device/hauppauge_broadway\n  SOC := rt3052\n  IMAGE_SIZE := 7744k\n  UIMAGE_NAME:= Broadway Kernel Image\n  DEVICE_VENDOR := Hauppauge\n  DEVICE_MODEL := Broadway\n  DEVICE_PACKAGES := kmod-usb-dwc2 kmod-usb-ledtrig-usbport\n  SUPPORTED_DEVICES += broadway\nendef\nTARGET_DEVICES += hauppauge_broadway\n\ndefine Device/hilink_hlk-rm04\n  SOC := rt5350\n  IMAGE_SIZE := 3776k\n  IMAGES += factory.bin\n  IMAGE/factory.bin := $$(sysupgrade_bin) | check-size | hilink-header\n  DEVICE_VENDOR := Hi-Link\n  DEVICE_MODEL := HLK-RM04\n  SUPPORTED_DEVICES += hlk-rm04\n  DEFAULT := n\nendef\nTARGET_DEVICES += hilink_hlk-rm04\n\ndefine Device/hootoo_ht-tm02\n  SOC := rt5350\n  IMAGE_SIZE := 7872k\n  DEVICE_VENDOR := HooToo\n  DEVICE_MODEL := HT-TM02\n  DEVICE_PACKAGES := kmod-usb-ohci kmod-usb2 kmod-usb-ledtrig-usbport\n  SUPPORTED_DEVICES += ht-tm02\n  DEFAULT := n\nendef\nTARGET_DEVICES += hootoo_ht-tm02\n\ndefine Device/huawei_d105\n  SOC := rt3050\n  BLOCKSIZE := 64k\n  IMAGE_SIZE := 3776k\n  DEVICE_VENDOR := Huawei\n  DEVICE_MODEL := D105\n  SUPPORTED_DEVICES += d105\n  DEFAULT := n\nendef\nTARGET_DEVICES += huawei_d105\n\ndefine Device/huawei_hg255d\n  SOC := rt3052\n  IMAGE_SIZE := 15744k\n  DEVICE_VENDOR := HuaWei\n  DEVICE_MODEL := HG255D\n  SUPPORTED_DEVICES += hg255d\nendef\nTARGET_DEVICES += huawei_hg255d\n\ndefine Device/intenso_memory2move\n  SOC := rt5350\n  IMAGE_SIZE := 7872k\n  UIMAGE_NAME:= Linux Kernel Image\n  DEVICE_VENDOR := Intenso\n  DEVICE_MODEL := Memory 2 Move\n  DEVICE_PACKAGES := kmod-usb2 kmod-usb-storage kmod-scsi-core kmod-fs-ext4 \\\n\tkmod-fs-vfat block-mount\n  SUPPORTED_DEVICES += m2m\nendef\nTARGET_DEVICES += intenso_memory2move\n\ndefine Device/jcg_jhr-n805r\n  SOC := rt3050\n  IMAGE_SIZE := 3776k\n  IMAGES += factory.bin\n  IMAGE/factory.bin := $$(sysupgrade_bin) | check-size | jcg-header 29.24\n  DEVICE_VENDOR := JCG\n  DEVICE_MODEL := JHR-N805R\n  SUPPORTED_DEVICES += jhr-n805r\n  DEFAULT := n\nendef\nTARGET_DEVICES += jcg_jhr-n805r\n\ndefine Device/jcg_jhr-n825r\n  SOC := rt3052\n  IMAGE_SIZE := 3776k\n  IMAGES += factory.bin\n  IMAGE/factory.bin := $$(sysupgrade_bin) | check-size | jcg-header 23.24\n  DEVICE_VENDOR := JCG\n  DEVICE_MODEL := JHR-N825R\n  SUPPORTED_DEVICES += jhr-n825r\n  DEFAULT := n\nendef\nTARGET_DEVICES += jcg_jhr-n825r\n\ndefine Device/jcg_jhr-n926r\n  SOC := rt3052\n  IMAGE_SIZE := 3776k\n  IMAGES += factory.bin\n  IMAGE/factory.bin := $$(sysupgrade_bin) | check-size | jcg-header 25.24\n  DEVICE_VENDOR := JCG\n  DEVICE_MODEL := JHR-N926R\n  SUPPORTED_DEVICES += jhr-n926r\n  DEFAULT := n\nendef\nTARGET_DEVICES += jcg_jhr-n926r\n\ndefine Device/mofinetwork_mofi3500-3gn\n  SOC := rt3052\n  IMAGE_SIZE := 7872k\n  DEVICE_VENDOR := MoFi Network\n  DEVICE_MODEL := MOFI3500-3GN\n  SUPPORTED_DEVICES += mofi3500-3gn\nendef\nTARGET_DEVICES += mofinetwork_mofi3500-3gn\n\ndefine Device/netcore_nw718\n  SOC := rt3050\n  IMAGE_SIZE := 3712k\n  UIMAGE_NAME:= ARA1B4NCRNW718;1\n  DEVICE_VENDOR := Netcore\n  DEVICE_MODEL := NW718\n  SUPPORTED_DEVICES += nw718\n  DEFAULT := n\nendef\nTARGET_DEVICES += netcore_nw718\n\ndefine Device/netgear_wnce2001\n  SOC := rt3052\n  IMAGE_SIZE := 3392k\n  IMAGES += factory.bin factory-NA.bin\n  IMAGE/factory.bin := $$(sysupgrade_bin) | check-size | \\\n\tdap-header -s RT3052-AP-WNCE2001-3 -r WW -v 1.0.0.99\n  IMAGE/factory-NA.bin := $$(sysupgrade_bin) | check-size | \\\n\tdap-header -s RT3052-AP-WNCE2001-3 -r NA -v 1.0.0.99\n  DEVICE_VENDOR := NETGEAR\n  DEVICE_MODEL := WNCE2001\n  SUPPORTED_DEVICES += wnce2001\n  DEFAULT := n\nendef\nTARGET_DEVICES += netgear_wnce2001\n\ndefine Device/nexaira_bc2\n  SOC := rt3052\n  IMAGE_SIZE := 7872k\n  DEVICE_VENDOR := NexAira\n  DEVICE_MODEL := BC2\n  SUPPORTED_DEVICES += bc2\nendef\nTARGET_DEVICES += nexaira_bc2\n\ndefine Device/nexx_wt1520-4m\n  SOC := rt5350\n  IMAGE_SIZE := 3776k\n  IMAGES += factory.bin\n  IMAGE/factory.bin := $$(sysupgrade_bin) | check-size | \\\n\tporay-header -B WT1520 -F 4M\n  DEVICE_VENDOR := Nexx\n  DEVICE_MODEL := WT1520\n  DEVICE_VARIANT := 4M\n  SUPPORTED_DEVICES += wt1520-4M\n  DEFAULT := n\nendef\nTARGET_DEVICES += nexx_wt1520-4m\n\ndefine Device/nexx_wt1520-8m\n  SOC := rt5350\n  IMAGE_SIZE := 7872k\n  IMAGES += factory.bin\n  IMAGE/factory.bin := $$(sysupgrade_bin) | check-size | \\\n\tporay-header -B WT1520 -F 8M\n  DEVICE_VENDOR := Nexx\n  DEVICE_MODEL := WT1520\n  DEVICE_VARIANT := 8M\n  SUPPORTED_DEVICES += wt1520-8M\nendef\nTARGET_DEVICES += nexx_wt1520-8m\n\ndefine Device/nixcore_x1-16m\n  SOC := rt5350\n  IMAGE_SIZE := 16064k\n  DEVICE_VENDOR := Nixcore\n  DEVICE_MODEL := X1\n  DEVICE_VARIANT := 16M\n  DEVICE_PACKAGES := kmod-usb-ohci kmod-usb2 kmod-i2c-ralink kmod-spi-dev\n  SUPPORTED_DEVICES += nixcore-x1 nixcore-x1-16M\nendef\nTARGET_DEVICES += nixcore_x1-16m\n\ndefine Device/nixcore_x1-8m\n  SOC := rt5350\n  IMAGE_SIZE := 7872k\n  DEVICE_VENDOR := Nixcore\n  DEVICE_MODEL := X1\n  DEVICE_VARIANT := 8M\n  DEVICE_PACKAGES := kmod-usb-ohci kmod-usb2 kmod-i2c-ralink kmod-spi-dev\n  SUPPORTED_DEVICES += nixcore-x1 nixcore-x1-8M\nendef\nTARGET_DEVICES += nixcore_x1-8m\n\ndefine Device/olimex_rt5350f-olinuxino\n  $(Device/uimage-lzma-loader)\n  SOC := rt5350\n  IMAGE_SIZE := 7872k\n  DEVICE_VENDOR := OLIMEX\n  DEVICE_MODEL := RT5350F-OLinuXino\n  DEVICE_PACKAGES := kmod-usb-ohci kmod-usb2 kmod-i2c-ralink kmod-spi-dev\n  SUPPORTED_DEVICES += rt5350f-olinuxino\nendef\nTARGET_DEVICES += olimex_rt5350f-olinuxino\n\ndefine Device/olimex_rt5350f-olinuxino-evb\n  $(Device/uimage-lzma-loader)\n  SOC := rt5350\n  IMAGE_SIZE := 7872k\n  DEVICE_VENDOR := OLIMEX\n  DEVICE_MODEL := RT5350F-OLinuXino-EVB\n  DEVICE_PACKAGES := kmod-usb-ohci kmod-usb2 kmod-i2c-ralink kmod-spi-dev\n  SUPPORTED_DEVICES += rt5350f-olinuxino-evb\nendef\nTARGET_DEVICES += olimex_rt5350f-olinuxino-evb\n\ndefine Device/omnima_miniembplug\n  SOC := rt5350\n  IMAGE_SIZE := 7872k\n  DEVICE_VENDOR := Omnima\n  DEVICE_MODEL := MiniEMBPlug\n  SUPPORTED_DEVICES += miniembplug\nendef\nTARGET_DEVICES += omnima_miniembplug\n\ndefine Device/omnima_miniembwifi\n  SOC := rt3052\n  IMAGE_SIZE := 7872k\n  DEVICE_VENDOR := Omnima\n  DEVICE_MODEL := MiniEMBWiFi\n  SUPPORTED_DEVICES += miniembwifi\nendef\nTARGET_DEVICES += omnima_miniembwifi\n\ndefine Device/petatel_psr-680w\n  SOC := rt3052\n  BLOCKSIZE := 64k\n  IMAGE_SIZE := 3776k\n  DEVICE_VENDOR := Petatel\n  DEVICE_MODEL := PSR-680W Wireless 3G Router\n  SUPPORTED_DEVICES += psr-680w\n  DEFAULT := n\nendef\nTARGET_DEVICES += petatel_psr-680w\n\ndefine Device/planex_mzk-dp150n\n  SOC := rt5350\n  BLOCKSIZE := 64k\n  IMAGE_SIZE := 3776k\n  DEVICE_VENDOR := Planex\n  DEVICE_MODEL := MZK-DP150N\n  DEVICE_PACKAGES := kmod-spi-dev\n  SUPPORTED_DEVICES += mzk-dp150n\n  DEFAULT := n\nendef\nTARGET_DEVICES += planex_mzk-dp150n\n\ndefine Device/planex_mzk-w300nh2\n  SOC := rt3052\n  IMAGE_SIZE := 3648k\n  IMAGES += factory.bin\n  IMAGE/factory.bin := $$(sysupgrade_bin) | \\\n\tedimax-header -s CSYS -m RN52 -f 0x50000 -S 0xc0000\n  DEVICE_VENDOR := Planex\n  DEVICE_MODEL := MZK-W300NH2\n  SUPPORTED_DEVICES += mzk-w300nh2\n  DEFAULT := n\nendef\nTARGET_DEVICES += planex_mzk-w300nh2\n\ndefine Device/planex_mzk-wdpr\n  SOC := rt3052\n  IMAGE_SIZE := 6656k\n  DEVICE_VENDOR := Planex\n  DEVICE_MODEL := MZK-WDPR\n  SUPPORTED_DEVICES += mzk-wdpr\nendef\nTARGET_DEVICES += planex_mzk-wdpr\n\ndefine Device/poray_ip2202\n  SOC := rt3052\n  IMAGE_SIZE := 7872k\n  DEVICE_VENDOR := Poray\n  DEVICE_MODEL := IP2202\n  SUPPORTED_DEVICES += ip2202\nendef\nTARGET_DEVICES += poray_ip2202\n\ndefine Device/poray_m3\n  SOC := rt5350\n  IMAGE_SIZE := 3776k\n  IMAGES += factory.bin\n  IMAGE/factory.bin := $$(sysupgrade_bin) | check-size | \\\n\tporay-header -B M3 -F 4M\n  DEVICE_VENDOR := Poray\n  DEVICE_MODEL := M3\n  DEVICE_PACKAGES := kmod-usb2\n  SUPPORTED_DEVICES += m3\n  DEFAULT := n\nendef\nTARGET_DEVICES += poray_m3\n\ndefine Device/poray_m4-4m\n  SOC := rt5350\n  IMAGE_SIZE := 3776k\n  IMAGES += factory.bin\n  IMAGE/factory.bin := $$(sysupgrade_bin) | check-size | \\\n\tporay-header -B M4 -F 4M\n  DEVICE_VENDOR := Poray\n  DEVICE_MODEL := M4\n  DEVICE_VARIANT := 4M\n  DEVICE_PACKAGES := kmod-usb2\n  SUPPORTED_DEVICES += m4-4M\n  DEFAULT := n\nendef\nTARGET_DEVICES += poray_m4-4m\n\ndefine Device/poray_m4-8m\n  SOC := rt5350\n  IMAGE_SIZE := 7872k\n  IMAGES += factory.bin\n  IMAGE/factory.bin := $$(sysupgrade_bin) | check-size | \\\n\tporay-header -B M4 -F 8M\n  DEVICE_VENDOR := Poray\n  DEVICE_MODEL := M4\n  DEVICE_VARIANT := 8M\n  DEVICE_PACKAGES := kmod-usb2\n  SUPPORTED_DEVICES += m4-8M\nendef\nTARGET_DEVICES += poray_m4-8m\n\ndefine Device/poray_x5\n  SOC := rt5350\n  IMAGE_SIZE := 7872k\n  IMAGES += factory.bin\n  IMAGE/factory.bin := $$(sysupgrade_bin) | check-size | \\\n\tporay-header -B X5 -F 8M\n  DEVICE_VENDOR := Poray\n  DEVICE_MODEL := X5/X6\n  DEVICE_PACKAGES := kmod-usb2\n  SUPPORTED_DEVICES += x5\nendef\nTARGET_DEVICES += poray_x5\n\ndefine Device/poray_x8\n  SOC := rt5350\n  IMAGE_SIZE := 7872k\n  IMAGES += factory.bin\n  IMAGE/factory.bin := $$(sysupgrade_bin) | check-size | \\\n\tporay-header -B X8 -F 8M\n  DEVICE_VENDOR := Poray\n  DEVICE_MODEL := X8\n  DEVICE_PACKAGES := kmod-usb2\n  SUPPORTED_DEVICES += x8\nendef\nTARGET_DEVICES += poray_x8\n\ndefine Device/prolink_pwh2004\n  SOC := rt3052\n  IMAGE_SIZE := 7872k\n  DEVICE_VENDOR := Prolink\n  DEVICE_MODEL := PWH2004\n  DEVICE_PACKAGES :=\n  SUPPORTED_DEVICES += pwh2004\nendef\nTARGET_DEVICES += prolink_pwh2004\n\ndefine Device/ralink_v22rw-2x2\n  SOC := rt3052\n  BLOCKSIZE := 64k\n  IMAGE_SIZE := 3776k\n  DEVICE_VENDOR := Ralink\n  DEVICE_MODEL := AP-RT3052-V22RW-2X2\n  SUPPORTED_DEVICES += v22rw-2x2\n  DEFAULT := n\nendef\nTARGET_DEVICES += ralink_v22rw-2x2\n\ndefine Device/sitecom_wl-351\n  SOC := rt3052\n  BLOCKSIZE := 64k\n  IMAGE_SIZE := 3776k\n  DEVICE_VENDOR := Sitecom\n  DEVICE_MODEL := WL-351 v1\n  DEVICE_PACKAGES := kmod-switch-rtl8366rb\n  SUPPORTED_DEVICES += wl-351\n  DEFAULT := n\nendef\nTARGET_DEVICES += sitecom_wl-351\n\ndefine Device/skyline_sl-r7205\n  SOC := rt3052\n  BLOCKSIZE := 64k\n  IMAGE_SIZE := 3776k\n  DEVICE_VENDOR := Skyline\n  DEVICE_MODEL := SL-R7205 Wireless 3G Router\n  SUPPORTED_DEVICES += sl-r7205\n  DEFAULT := n\nendef\nTARGET_DEVICES += skyline_sl-r7205\n\ndefine Device/sparklan_wcr-150gn\n  SOC := rt3050\n  BLOCKSIZE := 64k\n  IMAGE_SIZE := 3776k\n  DEVICE_VENDOR := Sparklan\n  DEVICE_MODEL := WCR-150GN\n  SUPPORTED_DEVICES += wcr-150gn\n  DEFAULT := n\nendef\nTARGET_DEVICES += sparklan_wcr-150gn\n\ndefine Device/teltonika_rut5xx\n  SOC := rt3050\n  IMAGE_SIZE := 16064k\n  DEVICE_VENDOR := Teltonika\n  DEVICE_MODEL := RUT5XX\n  SUPPORTED_DEVICES += rut5xx\nendef\nTARGET_DEVICES += teltonika_rut5xx\n\ndefine Device/tenda_3g150b\n  SOC := rt5350\n  BLOCKSIZE := 4k\n  IMAGE_SIZE := 3776k\n  UIMAGE_NAME:= Linux Kernel Image\n  DEVICE_VENDOR := Tenda\n  DEVICE_MODEL := 3G150B\n  DEVICE_PACKAGES := kmod-usb-dwc2 kmod-usb-ledtrig-usbport\n  SUPPORTED_DEVICES += 3g150b\n  DEFAULT := n\nendef\nTARGET_DEVICES += tenda_3g150b\n\ndefine Device/tenda_3g300m\n  SOC := rt3052\n  IMAGE_SIZE := 3776k\n  UIMAGE_NAME := 3G150M_SPI Kernel Image\n  DEVICE_VENDOR := Tenda\n  DEVICE_MODEL := 3G300M\n  DEVICE_PACKAGES := kmod-usb-dwc2 kmod-usb-ledtrig-usbport\n  SUPPORTED_DEVICES += 3g300m\n  DEFAULT := n\nendef\nTARGET_DEVICES += tenda_3g300m\n\ndefine Device/tenda_w150m\n  SOC := rt3050\n  IMAGE_SIZE := 3776k\n  UIMAGE_NAME:= W150M Kernel Image\n  DEVICE_VENDOR := Tenda\n  DEVICE_MODEL := W150M\n  SUPPORTED_DEVICES += w150m\n  DEFAULT := n\nendef\nTARGET_DEVICES += tenda_w150m\n\ndefine Device/tenda_w306r-v2\n  SOC := rt3052\n  IMAGE_SIZE := 3776k\n  UIMAGE_NAME:= linkn Kernel Image\n  DEVICE_VENDOR := Tenda\n  DEVICE_MODEL := W306R\n  DEVICE_VARIANT := V2.0\n  SUPPORTED_DEVICES += w306r-v20\n  DEFAULT := n\nendef\nTARGET_DEVICES += tenda_w306r-v2\n\ndefine Device/trendnet_tew-638apb-v2\n  SOC := rt3050\n  BLOCKSIZE := 64k\n  IMAGE_SIZE := 3776k\n  IMAGE/sysupgrade.bin := $$(sysupgrade_bin) | umedia-header 0x026382 | \\\n\tcheck-size | append-metadata\n  DEVICE_VENDOR := TRENDnet\n  DEVICE_MODEL := TEW-638APB\n  DEVICE_VARIANT := v2\n  SUPPORTED_DEVICES += tew-638apb-v2\n  DEFAULT := n\nendef\nTARGET_DEVICES += trendnet_tew-638apb-v2\n\ndefine Device/trendnet_tew-714tru\n  SOC := rt5350\n  IMAGE_SIZE := 7872k\n  DEVICE_VENDOR := TRENDnet\n  DEVICE_MODEL := TEW-714TRU\n  SUPPORTED_DEVICES += tew-714tru\nendef\nTARGET_DEVICES += trendnet_tew-714tru\n\ndefine Device/unbranded_a5-v11\n  SOC := rt5350\n  IMAGE_SIZE := 3776k\n  IMAGES += factory.bin\n  IMAGE/factory.bin := $$(sysupgrade_bin) | check-size | \\\n\tporay-header -B A5-V11 -F 4M\n  DEVICE_VENDOR := Unbranded\n  DEVICE_MODEL := A5-V11\n  DEVICE_PACKAGES := kmod-usb-ohci kmod-usb2\n  SUPPORTED_DEVICES += a5-v11\n  DEFAULT := n\nendef\nTARGET_DEVICES += unbranded_a5-v11\n\ndefine Device/unbranded_wr512-3gn-4m\n  SOC := rt3052\n  IMAGE_SIZE := 3776k\n  DEVICE_VENDOR := Unbranded\n  DEVICE_MODEL := WR512-3GN\n  DEVICE_VARIANT := 4M\n  SUPPORTED_DEVICES += wr512-3gn-4M\n  DEFAULT := n\nendef\nTARGET_DEVICES += unbranded_wr512-3gn-4m\n\ndefine Device/unbranded_wr512-3gn-8m\n  SOC := rt3052\n  IMAGE_SIZE := 7872k\n  DEVICE_VENDOR := Unbranded\n  DEVICE_MODEL := WR512-3GN\n  DEVICE_VARIANT := 8M\n  SUPPORTED_DEVICES += wr512-3gn-8M\nendef\nTARGET_DEVICES += unbranded_wr512-3gn-8m\n\ndefine Device/unbranded_xdx-rn502j\n  SOC := rt3052\n  BLOCKSIZE := 64k\n  IMAGE_SIZE := 3776k\n  DEVICE_VENDOR := Unbranded\n  DEVICE_MODEL := XDX-RN502J\n  SUPPORTED_DEVICES += xdxrn502j\n  DEFAULT := n\nendef\nTARGET_DEVICES += unbranded_xdx-rn502j\n\ndefine Device/upvel_ur-326n4g\n  SOC := rt3052\n  BLOCKSIZE := 64k\n  IMAGE_SIZE := 3776k\n  DEVICE_VENDOR := UPVEL\n  DEVICE_MODEL := UR-326N4G\n  DEVICE_PACKAGES := kmod-usb-dwc2 kmod-usb-ledtrig-usbport\n  SUPPORTED_DEVICES += ur-326n4g\n  DEFAULT := n\nendef\nTARGET_DEVICES += upvel_ur-326n4g\n\ndefine Device/upvel_ur-336un\n  SOC := rt3052\n  IMAGE_SIZE := 7872k\n  DEVICE_VENDOR := UPVEL\n  DEVICE_MODEL := UR-336UN\n  DEVICE_PACKAGES := kmod-usb-dwc2 kmod-usb-ledtrig-usbport\n  SUPPORTED_DEVICES += ur-336un\nendef\nTARGET_DEVICES += upvel_ur-336un\n\ndefine Device/vocore_vocore-16m\n  SOC := rt5350\n  IMAGE_SIZE := 16064k\n  DEVICE_VENDOR := VoCore\n  DEVICE_MODEL := VoCore\n  DEVICE_VARIANT := 16M\n  DEVICE_PACKAGES := kmod-usb-ohci kmod-usb2 kmod-i2c-ralink kmod-spi-dev\n  SUPPORTED_DEVICES += vocore vocore-16M\nendef\nTARGET_DEVICES += vocore_vocore-16m\n\ndefine Device/vocore_vocore-8m\n  SOC := rt5350\n  IMAGE_SIZE := 7872k\n  DEVICE_VENDOR := VoCore\n  DEVICE_MODEL := VoCore\n  DEVICE_VARIANT := 8M\n  DEVICE_PACKAGES := kmod-usb-ohci kmod-usb2 kmod-i2c-ralink kmod-spi-dev\n  SUPPORTED_DEVICES += vocore vocore-8M\nendef\nTARGET_DEVICES += vocore_vocore-8m\n\ndefine Device/wansview_ncs601w\n  SOC := rt5350\n  IMAGE_SIZE := 7872k\n  DEVICE_VENDOR := Wansview\n  DEVICE_MODEL := NCS601W\n  DEVICE_PACKAGES := kmod-video-core kmod-video-uvc kmod-usb-ohci\n  SUPPORTED_DEVICES += ncs601w\nendef\nTARGET_DEVICES += wansview_ncs601w\n\ndefine Device/wiznet_wizfi630a\n  SOC := rt5350\n  IMAGE_SIZE := 16064k\n  DEVICE_VENDOR := WIZnet\n  DEVICE_MODEL := WizFi630A\n  SUPPORTED_DEVICES += wizfi630a\nendef\nTARGET_DEVICES += wiznet_wizfi630a\n\ndefine Device/zorlik_zl5900v2\n  SOC := rt5350\n  IMAGE_SIZE := 7872k\n  DEVICE_VENDOR := Zorlik\n  DEVICE_MODEL := ZL5900V2\n  DEVICE_PACKAGES := kmod-usb-ohci kmod-usb2\nendef\nTARGET_DEVICES += zorlik_zl5900v2\n\ndefine Device/zte_mf283plus\n  $(Device/uimage-lzma-loader)\n  SOC := rt3352\n  IMAGE_SIZE := 15872k\n  DEVICE_VENDOR := ZTE\n  DEVICE_MODEL := MF283+\n  DEVICE_PACKAGES := kmod-usb-ohci kmod-usb2 kmod-usb-net-qmi-wwan uqmi \\\n\tkmod-usb-serial kmod-usb-serial-option\nendef\nTARGET_DEVICES += zte_mf283plus\n\ndefine Device/zyxel_keenetic\n  SOC := rt3052\n  BLOCKSIZE := 64k\n  IMAGE_SIZE := 7872k\n  DEVICE_VENDOR := ZyXEL\n  DEVICE_MODEL := Keenetic\n  DEVICE_PACKAGES := kmod-usb2 kmod-usb-ehci kmod-usb-ledtrig-usbport \\\n\tkmod-usb-dwc2\n  SUPPORTED_DEVICES += kn\nendef\nTARGET_DEVICES += zyxel_keenetic\n\ndefine Device/zyxel_keenetic-lite-b\n  $(Device/uimage-lzma-loader)\n  SOC := rt5350\n  IMAGE_SIZE := 7872k\n  DEVICE_VENDOR := ZyXEL\n  DEVICE_MODEL := Keenetic Lite\n  DEVICE_VARIANT := B\nendef\nTARGET_DEVICES += zyxel_keenetic-lite-b\n\ndefine Device/zyxel_keenetic-start\n  SOC := rt5350\n  IMAGE_SIZE := 3776k\n  DEVICE_VENDOR := ZyXEL\n  DEVICE_MODEL := Keenetic Start\n  DEFAULT := n\nendef\nTARGET_DEVICES += zyxel_keenetic-start\n\ndefine Device/zyxel_nbg-419n\n  SOC := rt3052\n  BLOCKSIZE := 64k\n  IMAGE_SIZE := 3776k\n  DEVICE_VENDOR := ZyXEL\n  DEVICE_MODEL := NBG-419N\n  SUPPORTED_DEVICES += nbg-419n\n  DEFAULT := n\nendef\nTARGET_DEVICES += zyxel_nbg-419n\n\ndefine Device/zyxel_nbg-419n-v2\n  SOC := rt3352\n  IMAGE_SIZE := 7872k\n  DEVICE_VENDOR := ZyXEL\n  DEVICE_MODEL := NBG-419N\n  DEVICE_VARIANT := v2\n  SUPPORTED_DEVICES += nbg-419n2\nendef\nTARGET_DEVICES += zyxel_nbg-419n-v2\n"
  },
  {
    "path": "target/linux/ramips/image/rt3883.mk",
    "content": "#\n# RT3662/RT3883 Profiles\n#\ndefine Build/mkrtn56uimg\n\t$(STAGING_DIR_HOST)/bin/mkrtn56uimg $(1) $@\nendef\n\ndefine Device/asus_rt-n56u\n  SOC := rt3662\n  BLOCKSIZE := 64k\n  IMAGE_SIZE := 7872k\n  IMAGE/sysupgrade.bin += | mkrtn56uimg -s\n  DEVICE_VENDOR := Asus\n  DEVICE_MODEL := RT-N56U\n  DEVICE_PACKAGES := kmod-usb-ohci kmod-usb2\n  SUPPORTED_DEVICES += rt-n56u\nendef\nTARGET_DEVICES += asus_rt-n56u\n\ndefine Device/belkin_f9k1109v1\n  SOC := rt3883\n  BLOCKSIZE := 64k\n  DEVICE_VENDOR := Belkin\n  DEVICE_MODEL := F9K1109\n  DEVICE_VARIANT := Version 1.0\n  DEVICE_PACKAGES := kmod-usb-ohci kmod-usb2 kmod-usb-ledtrig-usbport\n  IMAGE_SIZE := 7808k\n  KERNEL := kernel-bin | append-dtb | lzma -d16 | uImage lzma\n  # Stock firmware checks for this uImage image name during upload.\n  UIMAGE_NAME := N750F9K1103VB\nendef\nTARGET_DEVICES += belkin_f9k1109v1\n\ndefine Device/dlink_dir-645\n  $(Device/seama)\n  $(Device/uimage-lzma-loader)\n  SOC := rt3662\n  BLOCKSIZE := 4k\n  IMAGE_SIZE := 7872k\n  KERNEL := kernel-bin | append-dtb | lzma -d10\n  SEAMA_SIGNATURE := wrgn39_dlob.hans_dir645\n  DEVICE_VENDOR := D-Link\n  DEVICE_MODEL := DIR-645\n  DEVICE_PACKAGES := kmod-usb-ohci kmod-usb2\n  SUPPORTED_DEVICES += dir-645\nendef\nTARGET_DEVICES += dlink_dir-645\n\ndefine Device/edimax_br-6475nd\n  SOC := rt3662\n  BLOCKSIZE := 64k\n  IMAGE_SIZE := 7744k\n  IMAGE/sysupgrade.bin := append-kernel | append-rootfs | \\\n\tedimax-header -s CSYS -m RN54 -f 0x70000 -S 0x01100000 | pad-rootfs | \\\n\tcheck-size | append-metadata\n  DEVICE_VENDOR := Edimax\n  DEVICE_MODEL := BR-6475nD\n  SUPPORTED_DEVICES += br-6475nd\nendef\nTARGET_DEVICES += edimax_br-6475nd\n\ndefine Device/engenius_esr600h\n  $(Device/uimage-lzma-loader)\n  SOC := rt3662\n  BLOCKSIZE := 4k\n  IMAGE_SIZE := 7872k\n  IMAGES += factory.dlf\n  IMAGE/factory.dlf := $$(sysupgrade_bin) | check-size | \\\n\tsenao-header -r 0x101 -p 0x44 -t 2\n  DEVICE_VENDOR := EnGenius\n  DEVICE_MODEL := ESR600H\n  DEVICE_PACKAGES := kmod-usb-ohci kmod-usb2 uboot-envtools\nendef\nTARGET_DEVICES += engenius_esr600h\n\ndefine Device/loewe_wmdr-143n\n  SOC := rt3662\n  BLOCKSIZE := 64k\n  IMAGE_SIZE := 7872k\n  DEVICE_VENDOR := Loewe\n  DEVICE_MODEL := WMDR-143N\n  SUPPORTED_DEVICES += wmdr-143n\nendef\nTARGET_DEVICES += loewe_wmdr-143n\n\ndefine Device/omnima_hpm\n  SOC := rt3662\n  BLOCKSIZE := 64k\n  IMAGE_SIZE := 16064k\n  DEVICE_VENDOR := Omnima\n  DEVICE_MODEL := HPM\n  DEVICE_PACKAGES := kmod-usb-ohci kmod-usb2\n  SUPPORTED_DEVICES += hpm\nendef\nTARGET_DEVICES += omnima_hpm\n\ndefine Device/samsung_cy-swr1100\n  $(Device/seama)\n  SOC := rt3662\n  IMAGE_SIZE := 7872k\n  KERNEL := $(KERNEL_DTB)\n  SEAMA_SIGNATURE := wrgnd10_samsung_ss815\n  DEVICE_VENDOR := Samsung\n  DEVICE_MODEL := CY-SWR1100\n  DEVICE_PACKAGES := kmod-usb-ohci kmod-usb2 kmod-usb-ledtrig-usbport\n  SUPPORTED_DEVICES += cy-swr1100\nendef\nTARGET_DEVICES += samsung_cy-swr1100\n\ndefine Device/sitecom_wlr-6000\n  SOC := rt3883\n  BLOCKSIZE := 4k\n  IMAGE_SIZE := 7244k\n  IMAGES += factory.dlf\n  IMAGE/factory.dlf := $$(sysupgrade_bin) | check-size | \\\n\tsenao-header -r 0x0202 -p 0x41 -t 2\n  DEVICE_VENDOR := Sitecom\n  DEVICE_MODEL := WLR-6000\n  DEVICE_PACKAGES := kmod-usb-ohci kmod-usb2\n  SUPPORTED_DEVICES += wlr-6000\nendef\nTARGET_DEVICES += sitecom_wlr-6000\n\ndefine Device/trendnet_tew-691gr\n  SOC := rt3883\n  BLOCKSIZE := 64k\n  IMAGE_SIZE := 7872k\n  IMAGES += factory.bin\n  IMAGE/factory.bin := $$(sysupgrade_bin) | check-size | umedia-header 0x026910\n  DEVICE_VENDOR := TRENDnet\n  DEVICE_MODEL := TEW-691GR\n  SUPPORTED_DEVICES += tew-691gr\nendef\nTARGET_DEVICES += trendnet_tew-691gr\n\ndefine Device/trendnet_tew-692gr\n  SOC := rt3883\n  BLOCKSIZE := 64k\n  IMAGE_SIZE := 7872k\n  IMAGES += factory.bin\n  IMAGE/factory.bin := $$(sysupgrade_bin) | check-size | umedia-header 0x026920\n  DEVICE_VENDOR := TRENDnet\n  DEVICE_MODEL := TEW-692GR\n  SUPPORTED_DEVICES += tew-692gr\nendef\nTARGET_DEVICES += trendnet_tew-692gr\n"
  },
  {
    "path": "target/linux/ramips/modules.mk",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2006-2016 OpenWrt.org\n\nOTHER_MENU:=Other modules\n\ndefine KernelPackage/pwm-mediatek-ramips\n  SUBMENU:=Other modules\n  TITLE:=MT7628 PWM\n  DEPENDS:=@(TARGET_ramips_mt76x8)\n  KCONFIG:= \\\n\tCONFIG_PWM=y \\\n\tCONFIG_PWM_MEDIATEK_RAMIPS \\\n\tCONFIG_PWM_SYSFS=y\n  FILES:= \\\n\t$(LINUX_DIR)/drivers/pwm/pwm-mediatek-ramips.ko\n  AUTOLOAD:=$(call AutoProbe,pwm-mediatek-ramips)\nendef\n\ndefine KernelPackage/pwm-mediatek-ramips/description\n  Kernel modules for MediaTek Pulse Width Modulator\nendef\n\n$(eval $(call KernelPackage,pwm-mediatek-ramips))\n\ndefine KernelPackage/sdhci-mt7620\n  SUBMENU:=Other modules\n  TITLE:=MT7620 SDCI\n  DEPENDS:=@(TARGET_ramips_mt7620||TARGET_ramips_mt76x8||TARGET_ramips_mt7621) +kmod-mmc\n  KCONFIG:= \\\n\tCONFIG_MTK_MMC \\\n\tCONFIG_MTK_AEE_KDUMP=n \\\n\tCONFIG_MTK_MMC_CD_POLL=n\n  FILES:= \\\n\t$(LINUX_DIR)/drivers/mmc/host/mtk-mmc/mtk_sd.ko\n  AUTOLOAD:=$(call AutoProbe,mtk_sd,1)\nendef\n\n$(eval $(call KernelPackage,sdhci-mt7620))\n\nI2C_RALINK_MODULES:= \\\n  CONFIG_I2C_RALINK:drivers/i2c/busses/i2c-ralink\n\ndefine KernelPackage/i2c-ralink\n  $(call i2c_defaults,$(I2C_RALINK_MODULES),59)\n  TITLE:=Ralink I2C Controller\n  DEPENDS:=+kmod-i2c-core @TARGET_ramips \\\n\t@!(TARGET_ramips_mt7621||TARGET_ramips_mt76x8)\nendef\n\ndefine KernelPackage/i2c-ralink/description\n Kernel modules for enable ralink i2c controller.\nendef\n\n$(eval $(call KernelPackage,i2c-ralink))\n\n\nI2C_MT7621_MODULES:= \\\n  CONFIG_I2C_MT7621:drivers/i2c/busses/i2c-mt7621\n\ndefine KernelPackage/i2c-mt7628\n  $(call i2c_defaults,$(I2C_MT7621_MODULES),59)\n  TITLE:=MT7628/88 I2C Controller\n  DEPENDS:=+kmod-i2c-core \\\n\t@(TARGET_ramips_mt76x8)\nendef\n\ndefine KernelPackage/i2c-mt7628/description\n Kernel modules for enable mt7621 i2c controller.\nendef\n\n$(eval $(call KernelPackage,i2c-mt7628))\n\ndefine KernelPackage/dma-ralink\n  SUBMENU:=Other modules\n  TITLE:=Ralink GDMA Engine\n  DEPENDS:=@TARGET_ramips\n  KCONFIG:= \\\n\tCONFIG_DMADEVICES=y \\\n\tCONFIG_DW_DMAC_PCI=n \\\n\tCONFIG_DMA_RALINK\n  FILES:= \\\n\t$(LINUX_DIR)/drivers/dma/virt-dma.ko \\\n\t$(LINUX_DIR)/drivers/staging/ralink-gdma/ralink-gdma.ko\n  AUTOLOAD:=$(call AutoLoad,52,ralink-gdma)\nendef\n\ndefine KernelPackage/dma-ralink/description\n Kernel modules for enable ralink dma engine.\nendef\n\n$(eval $(call KernelPackage,dma-ralink))\n\ndefine KernelPackage/hsdma-mtk\n  SUBMENU:=Other modules\n  TITLE:=MediaTek HSDMA Engine\n  DEPENDS:=@TARGET_ramips @TARGET_ramips_mt7621\n  KCONFIG:= \\\n\tCONFIG_DMADEVICES=y \\\n\tCONFIG_DW_DMAC_PCI=n \\\n\tCONFIG_MTK_HSDMA\n  FILES:= \\\n\t$(LINUX_DIR)/drivers/dma/virt-dma.ko \\\n\t$(LINUX_DIR)/drivers/staging/mt7621-dma/hsdma-mt7621.ko\n  AUTOLOAD:=$(call AutoLoad,53,hsdma-mt7621)\nendef\n\ndefine KernelPackage/hsdma-mtk/description\n Kernel modules for enable MediaTek hsdma engine.\nendef\n\n$(eval $(call KernelPackage,hsdma-mtk))\n\ndefine KernelPackage/sound-mt7620\n  TITLE:=MT7620 PCM/I2S Alsa Driver\n  DEPENDS:=@TARGET_ramips +kmod-sound-soc-core +kmod-regmap-i2c +kmod-dma-ralink @!TARGET_ramips_rt288x\n  KCONFIG:= \\\n\tCONFIG_SND_RALINK_SOC_I2S \\\n\tCONFIG_SND_SIMPLE_CARD \\\n\tCONFIG_SND_SIMPLE_CARD_UTILS \\\n\tCONFIG_SND_SOC_WM8960\n  FILES:= \\\n\t$(LINUX_DIR)/sound/soc/ralink/snd-soc-ralink-i2s.ko \\\n\t$(LINUX_DIR)/sound/soc/generic/snd-soc-simple-card.ko \\\n\t$(LINUX_DIR)/sound/soc/generic/snd-soc-simple-card-utils.ko \\\n\t$(LINUX_DIR)/sound/soc/codecs/snd-soc-wm8960.ko\n  AUTOLOAD:=$(call AutoLoad,90,snd-soc-wm8960 snd-soc-ralink-i2s snd-soc-simple-card)\n  $(call AddDepends/sound)\nendef\n\ndefine KernelPackage/sound-mt7620/description\n Alsa modules for ralink i2s controller.\nendef\n\n$(eval $(call KernelPackage,sound-mt7620))\n"
  },
  {
    "path": "target/linux/ramips/mt7620/base-files/etc/board.d/01_leds",
    "content": "\n. /lib/functions/leds.sh\n. /lib/functions/uci-defaults.sh\n\nboard=$(board_name)\n\nboard_config_update\n\ncase $board in\naigale,ai-br100)\n\tucidef_set_led_netdev \"wan\" \"wan\" \"blue:wan\" \"eth0.2\"\n\tucidef_set_led_netdev \"wifi_led\" \"wifi\" \"blue:wlan\" \"wlan0\"\n\t;;\nalfa-network,ac1200rm)\n\tucidef_set_led_netdev \"wifi_led\" \"wifi\" \"green:wlan2g\" \"wlan1\"\n\t;;\nalfa-network,r36m-e4g)\n\tucidef_set_led_netdev \"4g\" \"4g\" \"orange:4g\" \"wwan0\"\n\tucidef_set_led_switch \"lan\" \"lan\" \"green:lan\" \"switch0\" \"0x8\"\n\tucidef_set_led_switch \"wan\" \"wan\" \"green:wan\" \"switch0\" \"0x10\"\n\t;;\nalfa-network,tube-e4g)\n\tucidef_set_led_netdev \"4g\" \"4g\" \"green:4g\" \"wwan0\"\n\tucidef_set_led_netdev \"lan\" \"lan\" \"blue:lan\" \"eth0\"\n\t;;\nasus,rp-n53)\n\tucidef_set_led_netdev \"eth\" \"Network\" \"white:back\" \"eth0\"\n\tucidef_set_led_netdev \"wifi_led\" \"wifi\" \"blue:wifi\" \"wlan0\"\n\t;;\nasus,rt-n12p)\n\tucidef_set_led_netdev \"lan\" \"lan\" \"green:lan\" eth0.1\n\tucidef_set_led_netdev \"wan\" \"wan\" \"green:wan\" eth0.2\n\tucidef_set_led_netdev \"wifi_led\" \"wifi\" \"green:air\" \"wlan0\"\n\t;;\nasus,rt-n14u)\n\tucidef_set_led_netdev \"lan\" \"lan\" \"blue:lan\" eth0.1\n\tucidef_set_led_netdev \"wan\" \"wan\" \"blue:wan\" eth0.2\n\tucidef_set_led_netdev \"wifi_led\" \"wifi\" \"blue:air\" \"wlan0\"\n\t;;\nbdcom,wap2100-sk)\n\tucidef_set_led_netdev \"wifi_led\" \"wifi\" \"green:wlan2g\" \"wlan0\"\n\t;;\ncomfast,cf-wr800n)\n\tucidef_set_led_netdev \"lan\" \"lan\" \"white:ethernet\" eth0.1\n\tucidef_set_led_netdev \"wifi_led\" \"wifi\" \"white:wifi\" \"wlan0\"\n\t;;\ndlink,dir-810l|\\\ntrendnet,tew-810dr)\n\tucidef_set_led_switch \"wan\" \"wan\" \"green:wan\" \"switch0\" \"0x10\"\n\t;;\ndlink,dwr-116-a1|\\\nhead-weblink,hdrm200|\\\nohyeah,oy-0001|\\\nplanex,mzk-ex300np|\\\nzbtlink,zbt-we826-16m|\\\nzbtlink,zbt-we826-32m|\\\nzbtlink,zbt-wr8305rt|\\\nzyxel,keenetic-omni|\\\nzyxel,keenetic-omni-ii|\\\nzyxel,keenetic-viva)\n\tucidef_set_led_netdev \"wifi_led\" \"wifi\" \"green:wifi\" \"wlan0\"\n\t;;\ndlink,dwr-118-a1)\n\tucidef_set_led_switch \"lan\" \"lan\" \"green:lan\" \"switch0\" \"0x1f\"\n\tucidef_set_led_switch \"wan\" \"wan\" \"green:wan\" \"switch0\" \"0x20\"\n\tucidef_set_led_netdev \"wifi_led\" \"wifi\" \"green:wlan2g\" \"wlan1\"\n\t;;\ndlink,dwr-118-a2)\n\tucidef_set_led_switch \"lan\" \"lan\" \"green:lan\" \"switch0\" \"0x1e\"\n\tucidef_set_led_switch \"wan\" \"wan\" \"green:wan\" \"switch0\" \"0x01\"\n\tucidef_set_led_netdev \"wifi_led\" \"wifi\" \"green:wlan2g\" \"wlan1\"\n\t;;\ndlink,dwr-921-c1|\\\ndlink,dwr-922-e2)\n\tucidef_set_led_switch \"lan\" \"lan\" \"green:lan\" \"switch0\" \"0x0f\"\n\tucidef_set_led_netdev \"signalstrength\" \"signalstrength\" \"green:sigstrength\" \"wwan0\" \"link\"\n\tucidef_set_led_netdev \"4g\" \"4g\" \"green:4g\" \"wwan0\" \"tx rx\"\n\tucidef_set_led_netdev \"wifi_led\" \"wifi\" \"green:wifi\" \"wlan0\"\n\t;;\ndlink,dwr-960)\n\tucidef_set_led_switch \"lan\" \"lan\" \"green:lan\" \"switch0\" \"0x2e\"\n\tucidef_set_led_switch \"wan\" \"wan\" \"green:wan\" \"switch0\" \"0x01\"\n\t;;\ndlink,dwr-961-a1)\n\tucidef_set_led_switch \"lan\" \"lan\" \"green:lan\" \"switch0\" \"0x3c\"\n\tucidef_set_led_switch \"wan\" \"wan\" \"green:wan\" \"switch0\" \"0x02\"\n\t;;\ndomywifi,dm202|\\\ndomywifi,dm203|\\\ndomywifi,dw22d)\n\tucidef_set_led_switch \"lan1\" \"lan1\" \"amber:lan1\" \"switch0\" \"0x02\"\n\tucidef_set_led_switch \"lan2\" \"lan2\" \"amber:lan2\" \"switch0\" \"0x04\"\n\tucidef_set_led_switch \"lan3\" \"lan3\" \"amber:lan3\" \"switch0\" \"0x08\"\n\tucidef_set_led_switch \"lan4\" \"lan4\" \"amber:lan4\" \"switch0\" \"0x10\"\n\tucidef_set_led_switch \"wan\" \"wan\" \"amber:wan\" \"switch0\" \"0x01\"\n\t\t;;\ndovado,tiny-ac)\n\tucidef_set_led_netdev \"wifi_led\" \"wifi\" \"orange:wifi\" \"wlan0\"\n\t;;\nedimax,br-6478ac-v2|\\\nedimax,ew-7478apc)\n\tucidef_set_led_netdev \"wifi_led\" \"wifi\" \"blue:wlan\" \"wlan0\"\n\t;;\nedimax,ew-7476rpc|\\\nedimax,ew-7478ac)\n\tucidef_set_led_switch \"lan\" \"lan\" \"green:lan\"  \"switch0\" \"0x20\"\n\t;;\nelecom,wrh-300cr)\n\tucidef_set_led_netdev \"lan\" \"lan\" \"green:ethernet\" \"eth0\"\n\tucidef_set_led_netdev \"wifi_led\" \"wifi\" \"green:wlan\" \"wlan0\"\n\t;;\nengenius,esr600)\n\tucidef_set_led_netdev \"wlan5g\" \"5.0GHz\" \"blue:wlan5g\" \"wlan0\"\n\tucidef_set_led_netdev \"wlan2g\" \"2.4GHz\" \"blue:wlan2g\" \"wlan1\"\n\t;;\nglinet,gl-mt300a|\\\nglinet,gl-mt300n|\\\nglinet,gl-mt750)\n\tucidef_set_led_netdev \"wifi_led\" \"wifi\" \"wlan\" \"wlan0\"\n\t;;\nhiwifi,hc5661|\\\nhiwifi,hc5761)\n\tucidef_set_led_switch \"internet\" \"internet\" \"blue:internet\" \"switch0\" \"0x01\"\n\t;;\nhiwifi,hc5861)\n\tucidef_set_led_switch \"internet\" \"internet\" \"blue:internet\" \"switch0\" \"0x20\"\n\t;;\nhnet,c108)\n\tucidef_set_led_netdev \"lan\" \"lan\" \"green:lan\" \"eth0\"\n\tucidef_set_led_netdev \"modem\" \"modem\" \"green:modem\" \"wwan0\"\n\t;;\nhumax,e2)\n\tucidef_set_led_netdev \"lan\" \"lan\" \"green:lan\" \"eth0\"\n\t;;\niodata,wn-ac1167gr|\\\niodata,wn-ac733gr3)\n\tucidef_set_led_wlan \"wlan5g\" \"WLAN5G\" \"green:wlan5g\" \"phy0radio\"\n\tucidef_set_led_wlan \"wlan2g\" \"WLAN2G\" \"green:wlan2g\" \"phy1radio\"\n\t;;\nkimax,u25awf-h1)\n\tucidef_set_led_netdev \"eth\" \"eth\" \"green:lan\" \"eth0\"\n\tucidef_set_led_netdev \"wifi_led\" \"wifi\" \"red:wifi\" \"wlan0\"\n\t;;\nkimax,u35wf)\n\tucidef_set_led_netdev \"eth\" \"ETH\" \"green:eth\" \"eth0\"\n\tucidef_set_led_netdev \"wifi_led\" \"wifi\" \"blue:wifi\" \"wlan0\"\n\t;;\nkingston,mlw221|\\\nkingston,mlwg2|\\\nsanlinking,d240)\n\tucidef_set_led_netdev \"wifi_led\" \"wifi\" \"blue:wifi\" \"wlan0\"\n\t;;\nlenovo,newifi-y1)\n\tucidef_set_led_netdev \"wifi\" \"WIFI\" \"blue:wifi\" \"wlan1\"\n\tucidef_set_led_netdev \"wifi5g\" \"WIFI5G\" \"blue:wifi5g\" \"wlan0\"\n\tucidef_set_led_switch \"lan\" \"LAN\" \"blue:lan\" \"switch0\" \"0x03\"\n\t;;\nlenovo,newifi-y1s)\n\tucidef_set_led_netdev \"wifi\" \"WIFI\" \"yellow:wifi\" \"wlan1\"\n\tucidef_set_led_netdev \"wifi5g\" \"WIFI5G\" \"blue:wifi\" \"wlan0\"\n\tucidef_set_led_netdev \"wan\" \"WAN\" \"blue:internet\" \"eth0.2\" \"tx rx\"\n\t;;\nnetgear,ex2700|\\\nnetgear,wn3000rp-v3|\\\nnetgear,wn3100rp-v2)\n\tucidef_set_led_netdev \"wifi_led\" \"wifi\" \"green:router\" \"wlan0\"\n\t;;\nnetgear,ex3700|\\\nnetgear,ex6130)\n\tucidef_set_led_netdev \"wlan5g\" \"ROUTER (green)\" \"green:router\" \"wlan0\"\n\tucidef_set_led_netdev \"wlan2g\" \"DEVICE (green)\" \"green:device\" \"wlan1\"\n\t;;\nnetgear,jwnr2010-v5)\n\tucidef_set_led_switch \"lan1\" \"lan1\" \"green:lan1\" \"switch0\" \"0x08\"\n\tucidef_set_led_switch \"lan2\" \"lan2\" \"green:lan2\" \"switch0\" \"0x04\"\n\tucidef_set_led_switch \"lan3\" \"lan3\" \"green:lan3\" \"switch0\" \"0x02\"\n\tucidef_set_led_switch \"lan4\" \"lan4\" \"green:lan4\" \"switch0\" \"0x01\"\n\tucidef_set_led_switch \"wan\" \"wan\" \"green:wan\" \"switch0\" \"0x10\"\n\t;;\nphicomm,psg1208)\n\tucidef_set_led_netdev \"wifi_led\" \"wifi\" \"white:wlan2g\" \"wlan0\"\n\t;;\nplanex,mzk-ex750np|\\\nzbtlink,zbt-we826-e)\n\tucidef_set_led_netdev \"wifi_led\" \"wifi\" \"red:wifi\" \"wlan0\"\n\t;;\nravpower,rp-wd03)\n\tucidef_set_led_netdev \"internet\" \"internet\" \"green:wifi\" \"eth0\"\n\t;;\ntplink,archer-c2-v1)\n\tucidef_set_led_switch \"lan\" \"lan\" \"green:lan\" \"switch1\" \"0x1e\"\n\tucidef_set_led_switch \"wan\" \"wan\" \"green:wan\" \"switch1\" \"0x01\"\n\t;;\ntplink,archer-c20-v1|\\\ntplink,archer-c20i)\n\tucidef_set_led_switch \"lan\" \"lan\" \"blue:lan\" \"switch0\" \"0x1e\"\n\tucidef_set_led_switch \"wan\" \"wan\" \"blue:wan\" \"switch0\" \"0x01\"\n\t;;\ntplink,archer-c50-v1)\n\tucidef_set_led_switch \"lan\" \"lan\" \"green:lan\" \"switch0\" \"0x1e\"\n\tucidef_set_led_switch \"wan\" \"wan\" \"green:wan\" \"switch0\" \"0x01\"\n\t;;\ntplink,archer-mr200)\n\tucidef_set_led_netdev \"lan\" \"lan\" \"white:lan\" \"eth0.1\"\n\tucidef_set_led_netdev \"wan\" \"wan\" \"white:wan\" \"usb0\"\n\t;;\ntplink,re200-v1)\n\tucidef_set_led_netdev \"lan\" \"lan\" \"green:lan\" \"eth0\"\n\t;;\nwavlink,wl-wn535k1)\n\tucidef_set_led_switch \"lan1\" \"lan2\" \"green:lan1\" \"switch0\" \"0x04\"\n\tucidef_set_led_switch \"lan2\" \"lan2\" \"green:lan2\" \"switch0\" \"0x20\"\n\tucidef_set_led_switch \"wan\" \"wan\" \"green:wan\" \"switch0\" \"0x10\"\n\t;;\nwavlink,wl-wn579x3)\n\tucidef_set_led_switch \"lan\" \"lan\" \"blue:lan\" \"switch0\" \"0x20\"\n\tucidef_set_led_switch \"wan\" \"wan\" \"blue:wan\" \"switch0\" \"0x10\"\n\t;;\nxiaomi,miwifi-mini)\n\tucidef_set_led_switch \"lan1\" \"lan1\" \"green:lan1\" \"switch0\" \"0x02\"\n\tucidef_set_led_switch \"lan2\" \"lan2\" \"green:lan2\" \"switch0\" \"0x01\"\n\tucidef_set_led_switch \"wan\" \"wan\" \"green:wan\" \"switch0\" \"0x10\"\n\t;;\nzbtlink,zbt-ape522ii)\n\tucidef_set_led_netdev \"wlan2g4\" \"wlan1-link\" \"green:wlan2g4\" \"wlan1\"\n\tucidef_set_led_netdev \"sys1\" \"wlan1\" \"green:sys1\" \"wlan1\" \"tx rx\"\n\tucidef_set_led_netdev \"sys2\" \"wlan0\" \"green:sys2\" \"wlan0\" \"tx rx\"\n\t;;\nzbtlink,zbt-wa05)\n\tucidef_set_led_netdev \"wifi_led\" \"wifi\" \"blue:air\" \"wlan0\"\n\t;;\nzbtlink,zbt-we1026-5g-16m)\n\tucidef_set_led_netdev \"lan\" \"LAN\" \"green:lan\" \"eth0\"\n\tucidef_set_led_netdev \"wifi_led\" \"wifi\" \"green:wifi\" \"wlan0\"\n\t;;\nzbtlink,zbt-we1026-h-32m)\n\tucidef_set_led_switch \"lan\" \"lan\" \"green:lan\" \"switch0\" \"0x8\"\n\tucidef_set_led_switch \"wan\" \"wan\" \"green:wan\" \"switch0\" \"0x10\"\n\tucidef_set_led_netdev \"wifi_led\" \"wifi\" \"green:wifi\" \"wlan0\"\n\t;;\nzbtlink,zbt-we2026)\n\tucidef_set_led_netdev \"wifi_led\" \"wifi\" \"green:wlan\" \"wlan0\"\n\t;;\nesac\n\nboard_config_flush\n\nexit 0\n"
  },
  {
    "path": "target/linux/ramips/mt7620/base-files/etc/board.d/02_network",
    "content": "\n. /lib/functions.sh\n. /lib/functions/uci-defaults.sh\n. /lib/functions/system.sh\n\nramips_setup_interfaces()\n{\n\tlocal board=\"$1\"\n\n\tcase $board in\n\taigale,ai-br100|\\\n\talfa-network,ac1200rm|\\\n\tasus,rt-n12p|\\\n\tdlink,dwr-116-a1|\\\n\tdlink,dwr-921-c1|\\\n\tdlink,dwr-922-e2|\\\n\tdovado,tiny-ac|\\\n\tohyeah,oy-0001|\\\n\tphicomm,psg1208|\\\n\tplanex,db-wrt01|\\\n\tplanex,mzk-750dhp|\\\n\tralink,mt7620a-evb|\\\n\tralink,mt7620a-mt7610e-evb|\\\n\tralink,mt7620a-v22sg-evb|\\\n\tsanlinking,d240|\\\n\tzbtlink,zbt-ape522ii|\\\n\tzbtlink,zbt-we826-16m|\\\n\tzbtlink,zbt-we826-32m|\\\n\tzbtlink,zbt-we826-e|\\\n\tzbtlink,zbt-wr8305rt|\\\n\tzyxel,keenetic-omni)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0:lan\" \"1:lan\" \"2:lan\" \"3:lan\" \"4:wan\" \"6@eth0\"\n\t\t;;\n\talfa-network,r36m-e4g|\\\n\tzbtlink,zbt-we1026-h-32m)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"3:lan\" \"4:wan\" \"6@eth0\"\n\t\t;;\n\talfa-network,tube-e4g|\\\n\tbuffalo,wmr-300|\\\n\tdlink,dch-m225|\\\n\tedimax,ew-7476rpc|\\\n\tedimax,ew-7478ac|\\\n\telecom,wrh-300cr|\\\n\thootoo,ht-tm05|\\\n\tkimax,u25awf-h1|\\\n\tkimax,u35wf|\\\n\tkingston,mlw221|\\\n\tkingston,mlwg2|\\\n\tmicroduino,microwrt|\\\n\tnetgear,ex2700|\\\n\tnetgear,ex3700|\\\n\tnetgear,ex6120|\\\n\tnetgear,ex6130|\\\n\tnetgear,wn3000rp-v3|\\\n\tnetgear,wn3100rp-v2|\\\n\tplanex,cs-qr10|\\\n\tplanex,mzk-ex300np|\\\n\tplanex,mzk-ex750np|\\\n\travpower,rp-wd03|\\\n\tsercomm,na930|\\\n\ttplink,re200-v1|\\\n\ttplink,re210-v1|\\\n\tyukai,bocco|\\\n\tzbtlink,zbt-cpe102|\\\n\tzte,q7)\n\t\tucidef_add_switch \"switch0\"\n\t\tucidef_add_switch_attr \"switch0\" \"enable\" \"false\"\n\t\tucidef_set_interface_lan \"eth0\"\n\t\t;;\n\tasus,rp-n53)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"1:lan\" \"2:lan\" \"3:lan\" \"4:lan\" \"6t@eth0\"\n\t\t;;\n\tasus,rt-ac51u|\\\n\tasus,rt-ac54u|\\\n\tasus,rt-n14u|\\\n\tbdcom,wap2100-sk|\\\n\tdomywifi,dm202|\\\n\tdomywifi,dm203|\\\n\tdomywifi,dw22d|\\\n\tedimax,ew-7478apc|\\\n\tglinet,gl-mt300a|\\\n\tglinet,gl-mt300n|\\\n\tglinet,gl-mt750|\\\n\thiwifi,hc5661|\\\n\twrtnode,wrtnode|\\\n\tzbtlink,zbt-wa05|\\\n\tzyxel,keenetic-omni-ii)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"1:lan\" \"2:lan\" \"3:lan\" \"4:lan\" \"0:wan\" \"6@eth0\"\n\t\t;;\n\tbuffalo,whr-1166d)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0:lan\" \"1:lan\" \"2:lan\" \"3:lan\" \"5:wan\" \"6@eth0\"\n\t\t;;\n\tbuffalo,whr-300hp2|\\\n\tbuffalo,whr-600d)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0:lan:1\" \"1:lan:2\" \"2:lan:3\" \"3:lan:4\" \"4:wan:5\" \"6@eth0\"\n\t\t;;\n\tcomfast,cf-wr800n|\\\n\thnet,c108|\\\n\thumax,e2)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"4:lan\" \"6@eth0\"\n\t\t;;\n\tdlink,dir-510l)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0:lan\" \"6@eth0\"\n\t\t;;\n\tdlink,dir-810l|\\\n\tnetgear,jwnr2010-v5|\\\n\tphicomm,k2-v22.4|\\\n\tphicomm,k2-v22.5|\\\n\ttrendnet,tew-810dr|\\\n\tzbtlink,zbt-we2026)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0:lan:4\" \"1:lan:3\" \"2:lan:2\" \"3:lan:1\" \"4:wan\" \"6@eth0\"\n\t\t;;\n\tdlink,dwr-118-a1)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"1:lan:2\" \"2:lan:3\" \"3:lan:1\" \"4:lan:0\" \"5:wan\" \"6@eth0\"\n\t\t;;\n\tdlink,dwr-118-a2)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"1:lan:2\" \"2:lan:1\" \"3:lan:3\" \"4:lan\" \"0:wan\" \"6@eth0\"\n\t\t;;\n\tdlink,dwr-960)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"1:lan\" \"2:lan\" \"3:lan\" \"5:lan\" \"0:wan\" \"6@eth0\"\n\t\t;;\n\tdlink,dwr-961-a1)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"2:lan:1\" \"3:lan:2\" \"4:lan:3\" \"5:lan:4\" \"1:wan\" \"0@eth0\"\n\t\tucidef_add_switch \"switch1\" \\\n\t\t\t\"5:lan\" \"6@eth0\"\n\t\tucidef_add_switch_attr \"switch1\" \"enable\" \"false\"\n\t\t;;\n\tedimax,br-6478ac-v2|\\\n\tlb-link,bl-w1200|\\\n\ttplink,archer-c2-v1)\n\t\tucidef_add_switch \"switch0\"\n\t\tucidef_add_switch_attr \"switch0\" \"enable\" \"false\"\n\t\tucidef_add_switch \"switch1\" \\\n\t\t\t\"1:lan\" \"2:lan\" \"3:lan\" \"4:lan\" \"0:wan\" \"6@eth0\"\n\t\t;;\n\tengenius,esr600|\\\n\tlava,lr-25g001|\\\n\tsitecom,wlr-4100-v1-002)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"1:lan:4\" \"2:lan:3\" \"3:lan:2\" \"4:lan:1\" \"5:wan\" \"0@eth0\"\n\t\tucidef_add_switch \"switch1\" \\\n\t\t\t\"5:lan\" \"6@eth0\"\n\t\tucidef_add_switch_attr \"switch1\" \"enable\" \"false\"\n\t\t;;\n\tfon,fon2601|\\\n\tvonets,var11n-300)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0:lan\" \"4:wan\" \"6@eth0\"\n\t\t;;\n\thead-weblink,hdrm200)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"1:lan\" \"2:lan\" \"3:lan\" \"4:lan\" \"5:lan\" \"0:wan\" \"6@eth0\"\n\t\t;;\n\thiwifi,hc5761)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"1:lan\" \"4:lan\" \"0:wan\" \"6@eth0\"\n\t\t;;\n\thiwifi,hc5861)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0:lan\" \"1:lan\" \"5:wan\" \"6@eth0\"\n\t\t;;\n\tiodata,wn-ac1167gr|\\\n\tiodata,wn-ac733gr3|\\\n\tiptime,a1004ns)\n\t\tucidef_add_switch \"switch0\"\n\t\tucidef_add_switch_attr \"switch0\" \"enable\" \"false\"\n\t\tucidef_add_switch \"switch1\" \\\n\t\t\t\"1:lan:4\" \"2:lan:3\" \"3:lan:2\" \"4:lan:1\" \"0:wan\" \"6@eth0\"\n\t\t;;\n\tiptime,a104ns)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"1:lan:4\" \"2:lan:3\" \"3:lan:2\" \"4:lan:1\" \"0:wan\" \"6@eth0\"\n\t\t;;\n\tlenovo,newifi-y1|\\\n\txiaomi,miwifi-mini)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0:lan:2\" \"1:lan:1\" \"4:wan\" \"6@eth0\"\n\t\t;;\n\tlenovo,newifi-y1s)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"1:lan:4\" \"2:lan:3\" \"4:lan:2\" \"5:lan:1\" \"0:wan\" \"6@eth0\"\n\t\t;;\n\tlinksys,e1700|\\\n\tnetis,wf2770|\\\n\tralink,mt7620a-mt7530-evb|\\\n\twevo,air-duo)\n\t\tucidef_add_switch \"switch0\"\n\t\tucidef_add_switch_attr \"switch0\" \"enable\" \"false\"\n\t\tucidef_add_switch \"switch1\" \\\n\t\t\t\"0:lan\" \"1:lan\" \"2:lan\" \"3:lan\" \"4:wan\" \"6@eth0\"\n\t\t;;\n\tnexx,wt3020-4m|\\\n\tnexx,wt3020-8m)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"4:lan\" \"0:wan\" \"6@eth0\"\n\t\t;;\n\tphicomm,k2g|\\\n\twavlink,wl-wn530hg4)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0:lan:4\" \"1:lan:3\" \"2:lan:2\" \"3:lan:1\" \"5:wan\" \"6@eth0\"\n\t\t;;\n\tphicomm,psg1218b)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0:lan:3\" \"1:lan:2\" \"2:lan:1\" \"3:wan\" \"6@eth0\"\n\t\t;;\n\ttplink,archer-c20-v1|\\\n\ttplink,archer-c20i|\\\n\ttplink,archer-c50-v1)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"1:lan:3\" \"2:lan:4\" \"3:lan:1\" \"4:lan:2\" \"0:wan\" \"6@eth0\"\n\t\t;;\n\ttplink,archer-mr200)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0:lan\" \"1:lan\" \"2:lan\" \"3:lan\" \"6t@eth0\"\n\t\tucidef_set_interface_wan \"usb0\"\n\t\t;;\n\twavlink,wl-wn535k1)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"2:lan\" \"5:lan\" \"4:wan\" \"6@eth0\"\n\t\t;;\n\twavlink,wl-wn579x3)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"5:lan\" \"4:wan\" \"6@eth0\"\n\t\t;;\n\tyouku,yk-l1|\\\n\tyouku,yk-l1c)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0:lan\" \"1:lan\" \"4:wan\" \"6@eth0\"\n\t\t;;\n\tzbtlink,zbt-we1026-5g-16m)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0:lan\" \"6t@eth0\"\n\t\t;;\n\tzyxel,keenetic-viva)\n\t\tucidef_add_switch \"switch1\" \\\n\t\t\t\"0:lan\" \"1:lan\" \"2:lan\" \"3:lan\" \"4:wan\" \"7t@eth0\"\n\t\t;;\n\tesac\n}\n\nramips_setup_macs()\n{\n\tlocal board=\"$1\"\n\tlocal lan_mac=\"\"\n\tlocal wan_mac=\"\"\n\tlocal label_mac=\"\"\n\n\tcase $board in\n\taigale,ai-br100|\\\n\tasus,rt-n12p|\\\n\tasus,rt-n14u|\\\n\tbdcom,wap2100-sk|\\\n\tedimax,ew-7478apc|\\\n\tfon,fon2601|\\\n\thead-weblink,hdrm200|\\\n\tnetgear,jwnr2010-v5|\\\n\tnexx,wt3020-4m|\\\n\tnexx,wt3020-8m|\\\n\tphicomm,psg1208|\\\n\tplanex,db-wrt01|\\\n\tplanex,mzk-750dhp|\\\n\tsanlinking,d240|\\\n\tvonets,var11n-300|\\\n\twrtnode,wrtnode|\\\n\tzbtlink,zbt-ape522ii|\\\n\tzbtlink,zbt-wa05|\\\n\tzbtlink,zbt-we2026|\\\n\tzbtlink,zbt-we826-16m|\\\n\tzbtlink,zbt-we826-32m|\\\n\tzbtlink,zbt-we826-e|\\\n\tzbtlink,zbt-wr8305rt)\n\t\twan_mac=$(macaddr_add \"$(mtd_get_mac_binary factory 0x4)\" 1)\n\t\t;;\n\talfa-network,ac1200rm|\\\n\tdlink,dir-810l|\\\n\ttrendnet,tew-810dr)\n\t\twan_mac=$(macaddr_add \"$(mtd_get_mac_binary factory 0x28)\" 1)\n\t\t;;\n\talfa-network,r36m-e4g|\\\n\tdomywifi,dm202|\\\n\tdomywifi,dm203|\\\n\tdomywifi,dw22d|\\\n\tzbtlink,zbt-we1026-h-32m)\n\t\twan_mac=$(mtd_get_mac_binary factory 0x2e)\n\t\tlabel_mac=$(mtd_get_mac_binary factory 0x4)\n\t\t;;\n\tasus,rt-ac51u|\\\n\tasus,rt-ac54u)\n\t\tlan_mac=$(mtd_get_mac_binary factory 0x22)\n\t\t;;\n\tdlink,dch-m225)\n\t\tlan_mac=$(mtd_get_mac_ascii factory lanmac)\n\t\t;;\n\tdlink,dir-510l|\\\n\tdlink,dwr-116-a1|\\\n\tdlink,dwr-118-a1|\\\n\tdlink,dwr-118-a2|\\\n\tdlink,dwr-921-c1|\\\n\tdlink,dwr-922-e2|\\\n\tdlink,dwr-960|\\\n\tdlink,dwr-961-a1|\\\n\tlava,lr-25g001)\n\t\twan_mac=$(jboot_config_read -m -i $(find_mtd_part \"config\") -o 0xE000)\n\t\tlan_mac=$(macaddr_add \"$wan_mac\" 1)\n\t\tlabel_mac=$wan_mac\n\t\t;;\n\tdovado,tiny-ac)\n\t\tlan_mac=$(mtd_get_mac_ascii u-boot-env LAN_MAC_ADDR)\n\t\twan_mac=$(mtd_get_mac_ascii u-boot-env WAN_MAC_ADDR)\n\t\t;;\n\tedimax,br-6478ac-v2)\n\t\twan_mac=$(macaddr_add \"$(mtd_get_mac_binary factory 0x4)\" 2)\n\t\t;;\n\tengenius,esr600)\n\t\tlan_mac=$(mtd_get_mac_ascii u-boot-env ethaddr)\n\t\twan_mac=$(mtd_get_mac_ascii u-boot-env wanaddr)\n\t\t;;\n\tglinet,gl-mt300a|\\\n\tglinet,gl-mt300n|\\\n\tglinet,gl-mt750)\n\t\twan_mac=$(macaddr_add \"$(mtd_get_mac_binary factory 0x4000)\" 1)\n\t\tlabel_mac=$(mtd_get_mac_binary factory 0x4)\n\t\t;;\n\thiwifi,hc5661|\\\n\thiwifi,hc5761|\\\n\thiwifi,hc5861)\n\t\tlan_mac=$(mtd_get_mac_ascii bdinfo \"Vfac_mac \")\n\t\tlabel_mac=$lan_mac\n\t\t[ -n \"$lan_mac\" ] || lan_mac=$(cat /sys/class/net/eth0/address)\n\t\twan_mac=$(macaddr_add \"$lan_mac\" 1)\n\t\t;;\n\tiodata,wn-ac1167gr|\\\n\tiodata,wn-ac733gr3)\n\t\twan_mac=$(mtd_get_mac_ascii u-boot-env wanaddr)\n\t\t;;\n\tiptime,a1004ns)\n\t\twan_mac=$(mtd_get_mac_binary u-boot 0x1fc40)\n\t\t;;\n\tiptime,a104ns)\n\t\twan_mac=$(macaddr_add \"$(mtd_get_mac_binary u-boot 0x1fc20)\" 2)\n\t\t;;\n\tlb-link,bl-w1200|\\\n\tnetis,wf2770|\\\n\tphicomm,k2-v22.4|\\\n\tphicomm,k2-v22.5|\\\n\tphicomm,k2g|\\\n\tphicomm,psg1218b)\n\t\twan_mac=$(mtd_get_mac_binary factory 0x2e)\n\t\tlabel_mac=$wan_mac\n\t\t;;\n\tlenovo,newifi-y1|\\\n\tlenovo,newifi-y1s|\\\n\tohyeah,oy-0001|\\\n\twavlink,wl-wn530hg4|\\\n\twevo,air-duo|\\\n\tyouku,yk-l1|\\\n\tyouku,yk-l1c)\n\t\twan_mac=$(mtd_get_mac_binary factory 0x2e)\n\t\t;;\n\tlinksys,e1700)\n\t\twan_mac=$(mtd_get_mac_ascii config WAN_MAC_ADDR)\n\t\t;;\n\ttplink,archer-c2-v1|\\\n\ttplink,archer-c20-v1|\\\n\ttplink,archer-c20i|\\\n\ttplink,archer-c50-v1|\\\n\ttplink,archer-mr200)\n\t\twan_mac=$(macaddr_add \"$(mtd_get_mac_binary rom 0xf100)\" 1)\n\t\t;;\n\twavlink,wl-wn535k1)\n\t\twan_mac=$(mtd_get_mac_binary factory 0x2e)\n\t\tlabel_mac=$(mtd_get_mac_binary factory 0x8004)\n\t\t;;\n\tzbtlink,zbt-we1026-5g-16m)\n\t\tlabel_mac=$(mtd_get_mac_binary factory 0x4)\n\t\t;;\n\tzyxel,keenetic-omni|\\\n\tzyxel,keenetic-omni-ii|\\\n\tzyxel,keenetic-viva)\n\t\twan_mac=$(mtd_get_mac_binary factory 0x28)\n\t\t;;\n\tesac\n\n\t[ -n \"$lan_mac\" ] && ucidef_set_interface_macaddr \"lan\" $lan_mac\n\t[ -n \"$wan_mac\" ] && ucidef_set_interface_macaddr \"wan\" $wan_mac\n\t[ -n \"$label_mac\" ] && ucidef_set_label_macaddr $label_mac\n}\n\nboard_config_update\nboard=$(board_name)\nramips_setup_interfaces $board\nramips_setup_macs $board\nboard_config_flush\n\nexit 0\n"
  },
  {
    "path": "target/linux/ramips/mt7620/base-files/etc/board.d/03_gpio_switches",
    "content": "\n. /lib/functions/uci-defaults.sh\n\nboard_config_update\n\nboard=$(board_name)\n\ncase \"$board\" in\ndlink,dir-510l)\n\tucidef_add_gpio_switch \"usb_enable1\" \"USB 1A enable\" \"12\" \"0\"\n\tucidef_add_gpio_switch \"usb_enable05\" \"USB 0.5A enable\" \"13\" \"1\"\n\t;;\ndlink,dwr-960|\\\ndlink,dwr-961-a1)\n\tucidef_add_gpio_switch \"power_mpcie\" \"mPCIe power\" \"0\" \"1\"\n\t;;\nhead-weblink,hdrm200)\n\tucidef_add_gpio_switch \"sim_switch\" \"SIM slot switch\" \"0\"\n\tucidef_add_gpio_switch \"io1\" \"I/O 1\" \"1\"\n\tucidef_add_gpio_switch \"io2\" \"I/O 2\" \"2\"\n\tucidef_add_gpio_switch \"io3\" \"I/O 3\" \"11\"\n\tucidef_add_gpio_switch \"io4\" \"I/O 4\" \"14\"\n\tucidef_add_gpio_switch \"power_mpcie\" \"mPCIe power\" \"21\" \"1\"\n\t;;\nlb-link,bl-w1200)\n\tucidef_add_gpio_switch \"eth_leds_enable\" \"ETH LEDs enable\" \"10\" \"1\"\n\t;;\nzbtlink,zbt-we826-e)\n\tucidef_add_gpio_switch \"sim_switch\" \"SIM slot switch\" \"13\"\n\tucidef_add_gpio_switch \"power_mpcie\" \"mPCIe power\" \"14\" \"1\"\n\t;;\nesac\n\nboard_config_flush\n\nexit 0\n"
  },
  {
    "path": "target/linux/ramips/mt7620/base-files/etc/hotplug.d/firmware/10-rt2x00-eeprom",
    "content": "#!/bin/sh\n\n[ -e /lib/firmware/$FIRMWARE ] && exit 0\n\n. /lib/functions/caldata.sh\n\njboot_eeprom_extract() {\n\tlocal part=$1\n\tlocal offset=$2\n\tlocal mtd\n\n\tmtd=$(find_mtd_part $part)\n\t[ -n \"$mtd\" ] || \\\n\t\tcaldata_die \"no mtd device found for partition $part\"\n\n\tjboot_config_read -i $mtd -o $offset -e /lib/firmware/$FIRMWARE  2>/dev/null || \\\n\t\tcaldata_die \"failed to extract from $mtd\"\n}\n\nboard=$(board_name)\n\ncase \"$FIRMWARE\" in\n\"soc_wmac.eeprom\")\n\tcase $board in\n\tdlink,dir-510l|\\\n\tdlink,dwr-116-a1|\\\n\tdlink,dwr-118-a1|\\\n\tdlink,dwr-118-a2|\\\n\tdlink,dwr-921-c1|\\\n\tdlink,dwr-922-e2|\\\n\tdlink,dwr-960|\\\n\tdlink,dwr-961-a1|\\\n\tlava,lr-25g001)\n\t\twan_mac=$(jboot_config_read -m -i $(find_mtd_part \"config\") -o 0xE000)\n\t\twifi_mac=$(macaddr_add \"$wan_mac\" 1)\n\t\tjboot_eeprom_extract \"config\" 0xE000\n\t\tcaldata_patch_mac $wifi_mac 0x4\n\t\t;;\n\tdovado,tiny-ac)\n\t\twifi_mac=$(mtd_get_mac_ascii u-boot-env INIC_MAC_ADDR)\n\t\tcaldata_extract \"factory\" 0x0 0x200\n\t\tcaldata_patch_mac $wifi_mac 0x4\n\t\t;;\n\t*)\n\t\tcaldata_die \"Please define mtd-eeprom in $board DTS file!\"\n\t\t;;\n\tesac\n\t;;\nesac\n"
  },
  {
    "path": "target/linux/ramips/mt7620/base-files/etc/hotplug.d/ieee80211/10_fix_wifi_mac",
    "content": "[ \"$ACTION\" == \"add\" ] || exit 0\n\nPHYNBR=${DEVPATH##*/phy}\n\n[ -n $PHYNBR ] || exit 0\n\n. /lib/functions.sh\n. /lib/functions/system.sh\n\nboard=$(board_name)\n\ncase \"$board\" in\n\thiwifi,hc5661)\n\t\tlabel_mac=$(mtd_get_mac_ascii bdinfo \"Vfac_mac \")\n\t\t[ \"$PHYNBR\" = \"0\" ] && [ -n \"$label_mac\" ] && \\\n\t\techo -n \"$label_mac\" > /sys${DEVPATH}/macaddress\n\t\t;;\n\thiwifi,hc5761|\\\n\thiwifi,hc5861)\n\t\tlabel_mac=$(mtd_get_mac_ascii bdinfo \"Vfac_mac \")\n\t\t[ \"$PHYNBR\" = \"1\" ] && [ -n \"$label_mac\" ] && \\\n\t\techo -n \"$label_mac\" > /sys${DEVPATH}/macaddress\n\t\t[ \"$PHYNBR\" = \"0\" ] && [ -n \"$label_mac\" ] && \\\n\t\tmacaddr_unsetbit \"$label_mac\" 6 > /sys${DEVPATH}/macaddress\n\t\t;;\nesac\n"
  },
  {
    "path": "target/linux/ramips/mt7620/base-files/etc/init.d/bootcount",
    "content": "#!/bin/sh /etc/rc.common\n\nSTART=99\n\nboot() {\n\tcase $(board_name) in\n\talfa-network,ac1200rm|\\\n\talfa-network,r36m-e4g|\\\n\talfa-network,tube-e4g)\n\t\t[ -n \"$(fw_printenv bootcount bootchanged 2>/dev/null)\" ] &&\\\n\t\t\techo -e \"bootcount\\nbootchanged\\n\" | /usr/sbin/fw_setenv -s -\n\t\t;;\n\tesac\n}\n"
  },
  {
    "path": "target/linux/ramips/mt7620/base-files/etc/uci-defaults/05_fix-compat-version",
    "content": ". /lib/functions.sh\n\ncase \"$(board_name)\" in\n\travpower,rp-wd03)\n\t\tuci set system.@system[0].compat_version=\"2.0\"\n\t\tuci commit system\n\t\t;;\nesac\n\nexit 0\n"
  },
  {
    "path": "target/linux/ramips/mt7620/base-files/lib/upgrade/platform.sh",
    "content": "#\n# Copyright (C) 2010 OpenWrt.org\n#\n\nPART_NAME=firmware\nREQUIRE_IMAGE_METADATA=1\n\nRAMFS_COPY_BIN='fw_printenv fw_setenv'\nRAMFS_COPY_DATA='/etc/fw_env.config /var/lock/fw_printenv.lock'\n\nplatform_check_image() {\n\treturn 0\n}\n\nplatform_do_upgrade() {\n\tlocal board=$(board_name)\n\n\tcase \"$board\" in\n\talfa-network,ac1200rm|\\\n\talfa-network,r36m-e4g|\\\n\talfa-network,tube-e4g)\n\t\t[ \"$(fw_printenv -n dual_image 2>/dev/null)\" = \"1\" ] &&\\\n\t\t[ -n \"$(find_mtd_part backup)\" ] && {\n\t\t\tPART_NAME=backup\n\t\t\tif [ \"$(fw_printenv -n bootactive 2>/dev/null)\" = \"1\" ]; then\n\t\t\t\tfw_setenv bootactive 2 || exit 1\n\t\t\telse\n\t\t\t\tfw_setenv bootactive 1 || exit 1\n\t\t\tfi\n\t\t}\n\t\tdefault_do_upgrade \"$1\"\n\t\t;;\n\t*)\n\t\tdefault_do_upgrade \"$1\"\n\t\t;;\n\tesac\n}\n"
  },
  {
    "path": "target/linux/ramips/mt7620/config-5.10",
    "content": "CONFIG_AR8216_PHY=y\nCONFIG_ARCH_32BIT_OFF_T=y\nCONFIG_ARCH_HIBERNATION_POSSIBLE=y\nCONFIG_ARCH_MMAP_RND_BITS_MAX=15\nCONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15\nCONFIG_ARCH_SUSPEND_POSSIBLE=y\nCONFIG_BLK_MQ_PCI=y\nCONFIG_CEVT_R4K=y\nCONFIG_CEVT_SYSTICK_QUIRK=y\nCONFIG_CLKDEV_LOOKUP=y\nCONFIG_CLKEVT_RT3352=y\nCONFIG_CLKSRC_MMIO=y\nCONFIG_CLONE_BACKWARDS=y\nCONFIG_CMDLINE=\"rootfstype=squashfs,jffs2\"\nCONFIG_CMDLINE_BOOL=y\n# CONFIG_CMDLINE_OVERRIDE is not set\nCONFIG_COMPAT_32BIT_TIME=y\nCONFIG_CPU_GENERIC_DUMP_TLB=y\nCONFIG_CPU_HAS_DIEI=y\nCONFIG_CPU_HAS_PREFETCH=y\nCONFIG_CPU_HAS_RIXI=y\nCONFIG_CPU_HAS_SYNC=y\nCONFIG_CPU_MIPS32=y\n# CONFIG_CPU_MIPS32_R1 is not set\nCONFIG_CPU_MIPS32_R2=y\nCONFIG_CPU_MIPSR2=y\nCONFIG_CPU_MIPSR2_IRQ_VI=y\nCONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y\nCONFIG_CPU_R4K_CACHE_TLB=y\nCONFIG_CPU_SUPPORTS_32BIT_KERNEL=y\nCONFIG_CPU_SUPPORTS_HIGHMEM=y\nCONFIG_CPU_SUPPORTS_MSA=y\nCONFIG_CRYPTO_LIB_POLY1305_RSIZE=2\nCONFIG_CRYPTO_RNG2=y\nCONFIG_CSRC_R4K=y\nCONFIG_DEBUG_PINCTRL=y\nCONFIG_DMA_NONCOHERENT=y\n# CONFIG_DTB_MT7620A_EVAL is not set\n# CONFIG_DTB_OMEGA2P is not set\nCONFIG_DTB_RT_NONE=y\n# CONFIG_DTB_VOCORE2 is not set\nCONFIG_DTC=y\nCONFIG_EARLY_PRINTK=y\nCONFIG_ETHERNET_PACKET_MANGLE=y\nCONFIG_FIXED_PHY=y\nCONFIG_FW_LOADER_PAGED_BUF=y\nCONFIG_GENERIC_ATOMIC64=y\nCONFIG_GENERIC_CLOCKEVENTS=y\nCONFIG_GENERIC_CMOS_UPDATE=y\nCONFIG_GENERIC_CPU_AUTOPROBE=y\nCONFIG_GENERIC_GETTIMEOFDAY=y\nCONFIG_GENERIC_IOMAP=y\nCONFIG_GENERIC_IRQ_CHIP=y\nCONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y\nCONFIG_GENERIC_IRQ_SHOW=y\nCONFIG_GENERIC_LIB_ASHLDI3=y\nCONFIG_GENERIC_LIB_ASHRDI3=y\nCONFIG_GENERIC_LIB_CMPDI2=y\nCONFIG_GENERIC_LIB_LSHRDI3=y\nCONFIG_GENERIC_LIB_UCMPDI2=y\nCONFIG_GENERIC_PCI_IOMAP=y\nCONFIG_GENERIC_PHY=y\nCONFIG_GENERIC_PINCONF=y\nCONFIG_GENERIC_SCHED_CLOCK=y\nCONFIG_GENERIC_SMP_IDLE_THREAD=y\nCONFIG_GENERIC_TIME_VSYSCALL=y\nCONFIG_GPIOLIB=y\n# CONFIG_GPIO_MT7621 is not set\nCONFIG_GPIO_RALINK=y\nCONFIG_GPIO_WATCHDOG=y\n# CONFIG_GPIO_WATCHDOG_ARCH_INITCALL is not set\nCONFIG_HANDLE_DOMAIN_IRQ=y\nCONFIG_HARDWARE_WATCHPOINTS=y\nCONFIG_HAS_DMA=y\nCONFIG_HAS_IOMEM=y\nCONFIG_HAS_IOPORT_MAP=y\nCONFIG_HZ_PERIODIC=y\nCONFIG_ICPLUS_PHY=y\nCONFIG_INITRAMFS_SOURCE=\"\"\nCONFIG_IRQCHIP=y\nCONFIG_IRQ_DOMAIN=y\nCONFIG_IRQ_FORCED_THREADING=y\nCONFIG_IRQ_INTC=y\nCONFIG_IRQ_MIPS_CPU=y\nCONFIG_IRQ_WORK=y\n# CONFIG_KERNEL_ZSTD is not set\nCONFIG_LIBFDT=y\nCONFIG_LOCK_DEBUGGING_SUPPORT=y\nCONFIG_MARVELL_PHY=y\nCONFIG_MDIO_BUS=y\nCONFIG_MDIO_DEVICE=y\nCONFIG_MEMFD_CREATE=y\nCONFIG_MFD_SYSCON=y\nCONFIG_MIGRATION=y\nCONFIG_MIPS=y\nCONFIG_MIPS_ASID_BITS=8\nCONFIG_MIPS_ASID_SHIFT=0\nCONFIG_MIPS_CBPF_JIT=y\nCONFIG_MIPS_CLOCK_VSYSCALL=y\n# CONFIG_MIPS_CMDLINE_BUILTIN_EXTEND is not set\n# CONFIG_MIPS_CMDLINE_DTB_EXTEND is not set\n# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set\nCONFIG_MIPS_CMDLINE_FROM_DTB=y\n# CONFIG_MIPS_ELF_APPENDED_DTB is not set\nCONFIG_MIPS_L1_CACHE_SHIFT=5\nCONFIG_MIPS_LD_CAN_LINK_VDSO=y\n# CONFIG_MIPS_NO_APPENDED_DTB is not set\nCONFIG_MIPS_RAW_APPENDED_DTB=y\nCONFIG_MIPS_SPRAM=y\nCONFIG_MODULES_USE_ELF_REL=y\n# CONFIG_MT7621_WDT is not set\n# CONFIG_MTD_CFI_INTELEXT is not set\nCONFIG_MTD_CMDLINE_PARTS=y\nCONFIG_MTD_PHYSMAP=y\nCONFIG_MTD_SPI_NOR=y\nCONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y\nCONFIG_MTD_SPI_NOR_USE_4K_SECTORS_LIMIT=16384\nCONFIG_MTD_SPLIT_JIMAGE_FW=y\nCONFIG_MTD_SPLIT_SEAMA_FW=y\nCONFIG_MTD_SPLIT_TPLINK_FW=y\nCONFIG_MTD_SPLIT_UIMAGE_FW=y\nCONFIG_MTD_VIRT_CONCAT=y\nCONFIG_NEED_DMA_MAP_STATE=y\nCONFIG_NEED_PER_CPU_KM=y\nCONFIG_NET_RALINK_GSW_MT7620=y\nCONFIG_NET_RALINK_MDIO=y\nCONFIG_NET_RALINK_MDIO_MT7620=y\nCONFIG_NET_RALINK_MT7620=y\n# CONFIG_NET_RALINK_RT3050 is not set\nCONFIG_NET_RALINK_SOC=y\n# CONFIG_NET_VENDOR_MEDIATEK is not set\nCONFIG_NET_VENDOR_RALINK=y\nCONFIG_NO_GENERIC_PCI_IOPORT_MAP=y\nCONFIG_NVMEM=y\nCONFIG_OF=y\nCONFIG_OF_ADDRESS=y\nCONFIG_OF_EARLY_FLATTREE=y\nCONFIG_OF_FLATTREE=y\nCONFIG_OF_GPIO=y\nCONFIG_OF_IRQ=y\nCONFIG_OF_KOBJ=y\nCONFIG_OF_MDIO=y\nCONFIG_OF_NET=y\nCONFIG_PCI=y\nCONFIG_PCI_DOMAINS=y\nCONFIG_PCI_DRIVERS_LEGACY=y\n# CONFIG_PCI_MT7621 is not set\n# CONFIG_PCI_MT7621_PHY is not set\nCONFIG_PERF_USE_VMALLOC=y\nCONFIG_PGTABLE_LEVELS=2\nCONFIG_PHYLIB=y\nCONFIG_PHY_RALINK_USB=y\nCONFIG_PINCTRL=y\n# CONFIG_PINCTRL_AW9523 is not set\nCONFIG_PINCTRL_RT2880=y\n# CONFIG_PINCTRL_SINGLE is not set\nCONFIG_RALINK=y\nCONFIG_RALINK_WDT=y\nCONFIG_REGMAP=y\nCONFIG_REGMAP_MMIO=y\nCONFIG_RESET_CONTROLLER=y\nCONFIG_SERIAL_8250_RT288X=y\nCONFIG_SERIAL_MCTRL_GPIO=y\nCONFIG_SERIAL_OF_PLATFORM=y\nCONFIG_SOC_MT7620=y\n# CONFIG_SOC_MT7621 is not set\n# CONFIG_SOC_RT288X is not set\n# CONFIG_SOC_RT305X is not set\n# CONFIG_SOC_RT3883 is not set\nCONFIG_SPI=y\nCONFIG_SPI_MASTER=y\nCONFIG_SPI_MEM=y\n# CONFIG_SPI_MT7621 is not set\nCONFIG_SPI_RT2880=y\nCONFIG_SRCU=y\nCONFIG_SWCONFIG=y\nCONFIG_SWCONFIG_LEDS=y\nCONFIG_SWPHY=y\nCONFIG_SYSCTL_EXCEPTION_TRACE=y\nCONFIG_SYS_HAS_CPU_MIPS32_R1=y\nCONFIG_SYS_HAS_CPU_MIPS32_R2=y\nCONFIG_SYS_HAS_EARLY_PRINTK=y\nCONFIG_SYS_SUPPORTS_32BIT_KERNEL=y\nCONFIG_SYS_SUPPORTS_ARBIT_HZ=y\nCONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y\nCONFIG_SYS_SUPPORTS_MIPS16=y\nCONFIG_SYS_SUPPORTS_ZBOOT=y\nCONFIG_TARGET_ISA_REV=2\nCONFIG_TICK_CPU_ACCOUNTING=y\nCONFIG_TIMER_OF=y\nCONFIG_TIMER_PROBE=y\nCONFIG_TINY_SRCU=y\nCONFIG_USB_SUPPORT=y\nCONFIG_USE_OF=y\nCONFIG_WATCHDOG_CORE=y\n"
  },
  {
    "path": "target/linux/ramips/mt7620/target.mk",
    "content": "#\n# Copyright (C) 2009 OpenWrt.org\n#\n\nSUBTARGET:=mt7620\nBOARDNAME:=MT7620 based boards\nFEATURES+=usb ramdisk\nCPU_TYPE:=24kc\n\nDEFAULT_PACKAGES += kmod-rt2800-soc wpad-basic-wolfssl swconfig\n\ndefine Target/Description\n\tBuild firmware images for Ralink MT7620 based boards.\nendef\n\n"
  },
  {
    "path": "target/linux/ramips/mt7621/base-files/etc/board.d/01_leds",
    "content": "\n. /lib/functions/leds.sh\n. /lib/functions/uci-defaults.sh\n\nboard=$(board_name)\n\nboard_config_update\n\ncase $board in\nasus,rt-n56u-b1)\n\tucidef_set_led_netdev \"lan\" \"LAN link\" \"blue:lan\" \"br-lan\"\n\tucidef_set_led_netdev \"wan\" \"WAN link\" \"blue:wan\" \"wan\"\n\t;;\nbeeline,smartbox-flash)\n\tucidef_set_led_netdev \"wan\" \"wan\" \"blue:wan\" \"wan\"\n\t;;\ncudy,wr2100)\n\tucidef_set_led_netdev \"lan1\" \"lan1\" \"green:lan1\" \"lan1\"\n\tucidef_set_led_netdev \"lan2\" \"lan2\" \"green:lan2\" \"lan2\"\n\tucidef_set_led_netdev \"lan3\" \"lan3\" \"green:lan3\" \"lan3\"\n\tucidef_set_led_netdev \"lan4\" \"lan4\" \"green:lan4\" \"lan4\"\n\tucidef_set_led_netdev \"wan\" \"wan\" \"green:wan\" \"wan\"\n\t;;\nd-team,newifi-d2)\n\tucidef_set_led_netdev \"internet\" \"internet\" \"amber:internet\" \"wan\"\n\tucidef_set_led_netdev \"wlan2g\" \"WiFi 2.4GHz\" \"blue:wlan2g\" \"wlan0\"\n\tucidef_set_led_netdev \"wlan5g\" \"WiFi 5GHz\" \"blue:wlan5g\" \"wlan1\"\n\t;;\nd-team,pbr-m1|\\\ngehua,ghl-r-001|\\\njcg,y2|\\\nxzwifi,creativebox-v1)\n\tucidef_set_led_netdev \"internet\" \"internet\" \"blue:internet\" \"wan\"\n\t;;\ndlink,dir-1960-a1|\\\ndlink,dir-2640-a1|\\\ndlink,dir-2660-a1)\n\tucidef_set_led_netdev \"wan\" \"wan\" \"white:net\" \"wan\"\n\t;;\ndlink,dir-853-a3)\n\tucidef_set_led_netdev \"wan\" \"wan\" \"blue:net\" \"wan\"\n\t;;\ndlink,dir-853-r1)\n\tucidef_set_led_netdev \"internet\" \"internet\" \"blue:net\" \"wan\"\n\t;;\ndlink,dir-860l-b1|\\\ndlink,dir-867-a1|\\\ndlink,dir-878-a1|\\\ndlink,dir-882-a1|\\\ndlink,dir-882-r1)\n\tucidef_set_led_netdev \"wan\" \"wan\" \"green:net\" \"wan\"\n\t;;\ngnubee,gb-pc1|\\\ngnubee,gb-pc2)\n\tucidef_set_led_netdev \"lan1\" \"lan1\" \"green:lan1\" \"lan1\"\n\tucidef_set_led_netdev \"lan2\" \"lan2\" \"green:lan2\" \"lan2\"\n\t;;\nlinksys,e5600)\n\tucidef_set_led_netdev \"wan\" \"wan link\" \"blue:wan\" \"wan\" \"link\"\n\t;;\nlinksys,ea6350-v4|\\\nlinksys,ea7300-v1|\\\nlinksys,ea7300-v2|\\\nlinksys,ea7500-v2|\\\nlinksys,ea8100-v1|\\\nlinksys,ea8100-v2)\n\tucidef_set_led_netdev \"lan1\" \"lan1 link\" \"green:lan1\" \"lan1\" \"link\"\n\tucidef_set_led_netdev \"lan2\" \"lan2 link\" \"green:lan2\" \"lan2\" \"link\"\n\tucidef_set_led_netdev \"lan3\" \"lan3 link\" \"green:lan3\" \"lan3\" \"link\"\n\tucidef_set_led_netdev \"lan4\" \"lan4 link\" \"green:lan4\" \"lan4\" \"link\"\n\tucidef_set_led_netdev \"wan\" \"wan link\" \"green:wan\" \"wan\" \"link\"\n\t;;\nmikrotik,routerboard-760igs)\n\tucidef_set_led_netdev \"sfp\" \"SFP\" \"blue:sfp\" \"sfp\"\n\t;;\nmikrotik,routerboard-m11g)\n\tucidef_set_rssimon \"wlan0\" \"200000\" \"1\"\n\tucidef_set_led_rssi \"rssilow\" \"RSSILOW\" \"green:rssi0\" \"wlan0\" \"1\" \"100\"\n\tucidef_set_led_rssi \"rssimediumlow\" \"RSSIMEDIUMLOW\" \"green:rssi1\" \"wlan0\" \"20\" \"100\"\n\tucidef_set_led_rssi \"rssimediumhigh\" \"RSSIMEDIUMHIGH\" \"green:rssi2\" \"wlan0\" \"40\" \"100\"\n\tucidef_set_led_rssi \"rssihigh\" \"RSSIHIGH\" \"green:rssi3\" \"wlan0\" \"60\" \"100\"\n\tucidef_set_led_rssi \"rssiveryhigh\" \"RSSIVERYHIGH\" \"green:rssi4\" \"wlan0\" \"80\" \"100\"\n\t;;\nmtc,wr1201)\n\tucidef_set_led_netdev \"eth_link\" \"LAN link\" \"green:eth_link\" \"br-lan\"\n\t;;\nnetgear,r6220|\\\nnetgear,r6260|\\\nnetgear,r6350|\\\nnetgear,r6850|\\\nnetgear,wac124|\\\nnetgear,wndr3700-v5)\n\tucidef_set_led_netdev \"wan\" \"wan\" \"green:wan\" \"wan\"\n\t;;\nnetgear,r6700-v2|\\\nnetgear,r6800|\\\nnetgear,r6900-v2|\\\nnetgear,r7200|\\\nnetgear,r7450)\n\tucidef_set_led_netdev \"wan\" \"WAN\" \"white:wan\" \"wan\"\n\tucidef_set_led_netdev \"lan1\" \"LAN1\" \"white:lan1\" \"lan1\"\n\tucidef_set_led_netdev \"lan2\" \"LAN2\" \"white:lan2\" \"lan2\"\n\tucidef_set_led_netdev \"lan3\" \"LAN3\" \"white:lan3\" \"lan3\"\n\tucidef_set_led_netdev \"lan4\" \"LAN4\" \"white:lan4\" \"lan4\"\n\t;;\noraybox,x3a)\n\tucidef_set_led_netdev \"wan\" \"wan link\" \"red:status\" \"wan\"\n\tucidef_set_led_netdev \"lan\" \"lan link\" \"green:status\" \"br-lan\"\n\t;;\ntplink,archer-a6-v3|\\\ntplink,archer-c6-v3|\\\ntplink,archer-c6u-v1)\n\tucidef_set_led_netdev \"lan\" \"LAN\" \"green:lan\" \"br-lan\"\n\tucidef_set_led_netdev \"wan\" \"WAN\" \"green:wan\" \"wan\"\n\t;;\ntplink,re350-v1)\n\tucidef_set_led_netdev \"wifi2g\" \"Wifi 2.4G\" \"blue:wifi2G\" \"wlan0\"\n\tucidef_set_led_netdev \"wifi5g\" \"Wifi 5G\" \"blue:wifi5G\" \"wlan1\"\n\tucidef_set_led_netdev \"eth_act\" \"LAN act\" \"green:eth_act\" \"lan\" \"tx rx\"\n\tucidef_set_led_netdev \"eth_link\" \"LAN link\" \"green:eth_link\" \"lan\" \"link\"\n\t;;\ntplink,re500-v1|\\\ntplink,re650-v1|\\\ntplink,re650-v2)\n\tucidef_set_led_netdev \"eth_act\" \"LAN act\" \"green:eth_act\" \"lan\" \"tx rx\"\n\tucidef_set_led_netdev \"eth_link\" \"LAN link\" \"green:eth_link\" \"lan\" \"link\"\n\t;;\ntplink,tl-wpa8631p-v3)\n\tucidef_set_led_netdev \"lan\" \"LAN\" \"green:lan\" \"br-lan\"\n\t;;\nxiaomi,mi-router-ac2100)\n\tucidef_set_led_netdev \"wan-blue\" \"WAN (blue)\" \"blue:wan\" \"wan\"\n\t;;\nxiaomi,mi-router-cr6606|\\\nxiaomi,mi-router-cr6608|\\\nxiaomi,mi-router-cr6609)\n\tucidef_set_led_netdev \"internet\" \"Internet\" \"blue:net\" \"wan\"\n\t;;\nxiaomi,redmi-router-ac2100)\n\tucidef_set_led_netdev \"wan\" \"wan\" \"white:wan\" \"wan\"\n\t;;\nyouhua,wr1200js)\n\tucidef_set_led_netdev \"internet\" \"INTERNET\" \"green:wan\" \"wan\"\n\t;;\nzbtlink,zbt-wg1608-16m)\n\tucidef_set_led_netdev \"lan1\" \"LAN1\" \"green:lan-1\" \"lan1\"\n\tucidef_set_led_netdev \"lan2\" \"LAN2\" \"green:lan-2\" \"lan2\"\n\tucidef_set_led_netdev \"lan3\" \"LAN3\" \"green:lan-3\" \"lan3\"\n\tucidef_set_led_netdev \"lan4\" \"LAN4\" \"green:lan-4\" \"lan4\"\n\tucidef_set_led_netdev \"wan\" \"WAN\" \"green:wan\" \"wan\"\n\t;;\nesac\n\nboard_config_flush\n\nexit 0\n"
  },
  {
    "path": "target/linux/ramips/mt7621/base-files/etc/board.d/02_network",
    "content": "\n. /lib/functions.sh\n. /lib/functions/uci-defaults.sh\n. /lib/functions/system.sh\n\nramips_setup_interfaces()\n{\n\tlocal board=\"$1\"\n\n\tcase $board in\n\tampedwireless,ally-00x19k|\\\n\tedimax,re23s|\\\n\tmikrotik,routerboard-m11g|\\\n\tnetgear,ex6150|\\\n\tsercomm,na502|\\\n\tthunder,timecloud|\\\n\ttplink,re350-v1|\\\n\ttplink,re500-v1|\\\n\ttplink,re650-v1|\\\n\ttplink,re650-v2|\\\n\tubnt,unifi-6-lite|\\\n\tubnt,unifi-nanohd)\n\t\tucidef_set_interface_lan \"lan\"\n\t\t;;\n\tampedwireless,ally-r1900k|\\\n\tgehua,ghl-r-001|\\\n\thiwifi,hc5962|\\\n\txiaomi,mi-router-3-pro|\\\n\txiaomi,mi-router-ac2100|\\\n\txiaomi,mi-router-cr6606|\\\n\txiaomi,mi-router-cr6608|\\\n\txiaomi,mi-router-cr6609|\\\n\txiaomi,redmi-router-ac2100)\n\t\tucidef_set_interfaces_lan_wan \"lan1 lan2 lan3\" \"wan\"\n\t\t;;\n\tasiarf,ap7621-001|\\\n\thumax,e10|\\\n\twinstars,ws-wn583a6)\n\t\tucidef_set_interfaces_lan_wan \"lan\" \"wan\"\n\t\t;;\n\tasiarf,ap7621-nv1|\\\n\tbeeline,smartbox-flash|\\\n\tglinet,gl-mt1300|\\\n\tiptime,a3002mesh|\\\n\tjcg,q20|\\\n\tlenovo,newifi-d1|\\\n\tmikrotik,routerboard-m33g|\\\n\toraybox,x3a|\\\n\trenkforce,ws-wn530hp3-a|\\\n\txiaomi,mi-router-3g|\\\n\txiaomi,mi-router-3g-v2|\\\n\txiaomi,mi-router-4|\\\n\txiaomi,mi-router-4a-gigabit)\n\t\tucidef_set_interfaces_lan_wan \"lan1 lan2\" \"wan\"\n\t\t;;\n\tbolt,arion)\n\t\tucidef_set_interfaces_lan_wan \"lan\" \"wan\"\n\t\tucidef_set_interface \"eth_data\" device \"modem.103\" protocol \"static\" ipaddr \"10.22.127.222\" netmask \"255.255.255.255\"\n\t\tucidef_set_interface \"eth_om\" device \"modem.4094\" protocol \"static\" ipaddr \"169.254.0.2\" netmask \"255.255.255.252\"\n\t\tuci add_list firewall.@zone[1].network='eth_data'\n\t\tuci add_list firewall.@zone[1].network='eth_om'\n\t\t;;\n\tgnubee,gb-pc1|\\\n\tgnubee,gb-pc2)\n\t\tucidef_set_interface_lan \"lan1 lan2\"\n\t\t;;\n\tlinksys,re6500|\\\n\tnetgear,wac104)\n\t\tucidef_set_interface_lan \"lan1 lan2 lan3 lan4\"\n\t\t;;\n\tmikrotik,routerboard-750gr3)\n\t\tucidef_set_interfaces_lan_wan \"lan2 lan3 lan4 lan5\" \"wan\"\n\t\t;;\n\tmikrotik,routerboard-760igs)\n\t\tucidef_set_interfaces_lan_wan \"lan2 lan3 lan4 lan5\" \"wan sfp\"\n\t\t;;\n\ttplink,eap235-wall-v1|\\\n\ttplink,eap615-wall-v1)\n\t\tucidef_set_interface_lan \"lan0 lan1 lan2 lan3\"\n\t\t;;\n\ttplink,tl-wpa8631p-v3)\n\t\tucidef_set_interface_lan \"lan1 lan2 lan3 plc0\"\n\t\t;;\n\tubnt,edgerouter-x)\n\t\tucidef_set_interfaces_lan_wan \"eth1 eth2 eth3 eth4\" \"eth0\"\n\t\t;;\n\tubnt,edgerouter-x-sfp)\n\t\tucidef_set_interfaces_lan_wan \"eth1 eth2 eth3 eth4 eth5\" \"eth0\"\n\t\t;;\n\tubnt,usw-flex)\n\t\tucidef_set_interface_lan \"lan1 lan2 lan3 lan4 lan5\"\n\t\t;;\n\tyuncore,ax820|\\\n\tzyxel,nr7101)\n\t\tucidef_set_interfaces_lan_wan \"lan\" \"wan\"\n\t\t;;\n\tzyxel,wap6805)\n\t\tucidef_set_interface_lan \"lan1 lan2 lan3 lan4\"\n\t\tucidef_set_interface \"qtn\" ifname \"eth1\" protocol \"static\" ipaddr \"1.1.1.1\" netmask \"255.255.255.0\"\n\t\t;;\n\t*)\n\t\tucidef_set_interfaces_lan_wan \"lan1 lan2 lan3 lan4\" \"wan\"\n\t\t;;\n\tesac\n}\n\nramips_setup_macs()\n{\n\tlocal board=\"$1\"\n\tlocal lan_mac=\"\"\n\tlocal wan_mac=\"\"\n\tlocal label_mac=\"\"\n\n\tcase $board in\n\tampedwireless,ally-00x19k)\n\t\tlan_mac=$(mtd_get_mac_ascii hwconfig HW.LAN.MAC.Address)\n\t\tlabel_mac=$lan_mac\n\t\t;;\n\tampedwireless,ally-r1900k)\n\t\tlan_mac=$(mtd_get_mac_ascii hwconfig HW.LAN.MAC.Address)\n\t\twan_mac=$(mtd_get_mac_ascii hwconfig HW.WAN.MAC.Address)\n\t\tlabel_mac=$lan_mac\n\t\t;;\n\tasus,rt-ac65p|\\\n\tasus,rt-ac85p)\n\t\twan_mac=$(mtd_get_mac_ascii u-boot-env et1macaddr)\n\t\tlabel_mac=$(mtd_get_mac_binary factory 0x4)\n\t\t;;\n\tbeeline,smartbox-flash)\n\t\tlan_mac=$(mtd_get_mac_ascii u-boot-env eth2macaddr)\n\t\twan_mac=$(mtd_get_mac_ascii u-boot-env eth3macaddr)\n\t\tlabel_mac=$lan_mac\n\t\t;;\n\tbuffalo,wsr-1166dhp)\n\t\tlocal index=\"$(find_mtd_index \"board_data\")\"\n\t\twan_mac=\"$(grep -m1 mac= \"/dev/mtd${index}\" | cut -d= -f2)\"\n\t\tlan_mac=$wan_mac\n\t\t;;\n\tdlink,dir-860l-b1)\n\t\tlan_mac=$(mtd_get_mac_ascii factory lanmac)\n\t\twan_mac=$(mtd_get_mac_ascii factory wanmac)\n\t\t;;\n\tedimax,ra21s|\\\n\tedimax,rg21s)\n\t\tlan_mac=$(mtd_get_mac_ascii u-boot-env ethaddr)\n\t\twan_mac=$(mtd_get_mac_ascii u-boot-env wanaddr)\n\t\t;;\n\telecom,wrc-2533ghbk-i)\n\t\tlan_mac=$(mtd_get_mac_ascii u-boot-env ethaddr)\n\t\twan_mac=$(mtd_get_mac_ascii u-boot-env wanaddr)\n\t\tlabel_mac=$wan_mac\n\t\t;;\n\thiwifi,hc5962)\n\t\tlan_mac=$(mtd_get_mac_ascii bdinfo \"Vfac_mac \")\n\t\tlabel_mac=$lan_mac\n\t\t[ -n \"$lan_mac\" ] || lan_mac=$(cat /sys/class/net/eth0/address)\n\t\twan_mac=$(macaddr_add \"$lan_mac\" 1)\n\t\t;;\n\tiodata,wnpr2600g)\n\t\twan_mac=$(mtd_get_mac_ascii u-boot-env wanaddr)\n\t\tlabel_mac=$wan_mac\n\t\t;;\n\tiptime,t5004)\n\t\tlan_mac=$(mtd_get_mac_ascii config ethaddr)\n\t\twan_mac=$(macaddr_add \"$lan_mac\" 1)\n\t\t;;\n\tjcg,y2|\\\n\twavlink,wl-wn531a6|\\\n\twavlink,wl-wn533a8|\\\n\twinstars,ws-wn583a6|\\\n\tzbtlink,zbt-we1326|\\\n\tzbtlink,zbt-wg3526-16m|\\\n\tzbtlink,zbt-wg3526-32m)\n\t\tlabel_mac=$(mtd_get_mac_binary factory 0x4)\n\t\t;;\n\tlinksys,e5600|\\\n\tlinksys,ea6350-v4|\\\n\tlinksys,ea7300-v1|\\\n\tlinksys,ea7300-v2|\\\n\tlinksys,ea7500-v2|\\\n\tlinksys,ea8100-v1|\\\n\tlinksys,ea8100-v2)\n\t\tlan_mac=$(mtd_get_mac_ascii devinfo hw_mac_addr)\n\t\twan_mac=$lan_mac\n\t\tlabel_mac=$lan_mac\n\t\t;;\n\tmikrotik,routerboard-750gr3|\\\n\tmikrotik,routerboard-760igs|\\\n\tmikrotik,routerboard-m11g|\\\n\tmikrotik,routerboard-m33g)\n\t\tlabel_mac=$(cat \"/sys/firmware/mikrotik/hard_config/mac_base\")\n\t\twan_mac=$label_mac\n\t\tlan_mac=$(macaddr_add $label_mac 1)\n\t\t;;\n\traisecom,msg1500-x-00)\n\t\tlan_mac=$(mtd_get_mac_ascii Config protest_lan_mac)\n\t\twan_mac=$(mtd_get_mac_ascii Config protest_wan_mac)\n\t\tlabel_mac=$lan_mac\n\t\t;;\n\tyuncore,ax820)\n\t\tlabel_mac=$(mtd_get_mac_binary Factory 0x4)\n\t\t;;\n\tesac\n\n\t[ -n \"$lan_mac\" ] && ucidef_set_interface_macaddr \"lan\" $lan_mac\n\t[ -n \"$wan_mac\" ] && ucidef_set_interface_macaddr \"wan\" $wan_mac\n\t[ -n \"$label_mac\" ] && ucidef_set_label_macaddr $label_mac\n}\n\nboard_config_update\nboard=$(board_name)\nramips_setup_interfaces $board\nramips_setup_macs $board\nboard_config_flush\n\nexit 0\n"
  },
  {
    "path": "target/linux/ramips/mt7621/base-files/etc/board.d/03_gpio_switches",
    "content": "\n. /lib/functions/uci-defaults.sh\n\nboard_config_update\n\nboard=$(board_name)\n\ncase \"$board\" in\nmikrotik,routerboard-760igs)\n\tucidef_add_gpio_switch \"poe_passthrough\" \"PoE Passthrough\" \"497\"\n\t;;\ntelco-electronics,x1)\n\tucidef_add_gpio_switch \"modem_reset\" \"Modem Reset\" \"496\"\n\t;;\nubnt,edgerouter-x)\n\tucidef_add_gpio_switch \"poe_passthrough\" \"PoE Passthrough\" \"480\"\n\t;;\nubnt,edgerouter-x-sfp)\n\tucidef_add_gpio_switch \"poe_power_port0\" \"PoE Power Port0\" \"400\"\n\tucidef_add_gpio_switch \"poe_power_port1\" \"PoE Power Port1\" \"401\"\n\tucidef_add_gpio_switch \"poe_power_port2\" \"PoE Power Port2\" \"402\"\n\tucidef_add_gpio_switch \"poe_power_port3\" \"PoE Power Port3\" \"403\"\n\tucidef_add_gpio_switch \"poe_power_port4\" \"PoE Power Port4\" \"404\"\n\t;;\nzyxel,nr7101)\n\tucidef_add_gpio_switch \"lte_reset\" \"Reset LTE/5G modem\" \"483\"\n\t;;\nzyxel,wap6805)\n\tucidef_add_gpio_switch \"qtn_power\" \"Quantenna Module Power\" \"496\" \"1\"\n\t;;\nesac\n\nboard_config_flush\n\nexit 0\n"
  },
  {
    "path": "target/linux/ramips/mt7621/base-files/etc/board.d/05_compat-version",
    "content": "#\n# Copyright (C) 2020 OpenWrt.org\n#\n\n. /lib/functions.sh\n. /lib/functions/uci-defaults.sh\n\nboard_config_update\n\ncase \"$(board_name)\" in\n\t*)\n\t\tucidef_set_compat_version \"1.1\"\n\t\t;;\nesac\n\nboard_config_flush\n\nexit 0\n"
  },
  {
    "path": "target/linux/ramips/mt7621/base-files/etc/hotplug.d/ieee80211/10_fix_wifi_mac",
    "content": "[ \"$ACTION\" == \"add\" ] || exit 0\n\nPHYNBR=${DEVPATH##*/phy}\n\n[ -n $PHYNBR ] || exit 0\n\n. /lib/functions.sh\n. /lib/functions/system.sh\n\nboard=$(board_name)\n\ncase \"$board\" in\n\tbeeline,smartbox-flash)\n\t\thw_mac_addr_ra0=\"$(mtd_get_mac_ascii u-boot-env ra0macaddr)\"\n\t\thw_mac_addr_rax0=\"$(mtd_get_mac_ascii u-boot-env rax0macaddr)\"\n\t\t[ \"$PHYNBR\" = \"0\" ] && echo -n $hw_mac_addr_ra0 > /sys${DEVPATH}/macaddress\n\t\t[ \"$PHYNBR\" = \"1\" ] && echo -n $hw_mac_addr_rax0 > /sys${DEVPATH}/macaddress\n\t\t;;\n\tcudy,x6)\n\t\thw_mac_addr=\"$(mtd_get_mac_binary factory 0x4)\"\n\t\tmacaddr_add $hw_mac_addr \"$PHYNBR\" > /sys${DEVPATH}/macaddress\n\t\t;;\n\tdlink,dir-853-a3)\n\t\t[ \"$PHYNBR\" = \"0\" ] && \\\n\t\t\tmacaddr_setbit_la \"$(mtd_get_mac_binary factory 0xe000)\" \\\n\t\t\t\t> /sys${DEVPATH}/macaddress\n\t\t;;\n\tdlink,dir-853-r1|\\\n\tphicomm,k2p)\n\t\tif [ \"$PHYNBR\" = \"0\" ]; then\n\t\t\tbase_mac=$(macaddr_add \"$(mtd_get_mac_binary factory 0x4)\" -1)\n\t\t\tmacaddr_setbit_la \"$base_mac\" > /sys${DEVPATH}/macaddress\n\t\tfi\n\t\t;;\n\tglinet,gl-mt1300)\n\t\t[ \"$PHYNBR\" = \"1\" ] && \\\n\t\t\tmacaddr_add \"$(mtd_get_mac_binary factory 0x4)\" 1 > /sys${DEVPATH}/macaddress\n\t\t;;\n\thiwifi,hc5962)\n\t\tlabel_mac=$(mtd_get_mac_ascii bdinfo \"Vfac_mac \")\n\t\t[ \"$PHYNBR\" = \"0\" ] && [ -n \"$label_mac\" ] && \\\n\t\techo -n \"$label_mac\" > /sys${DEVPATH}/macaddress\n\t\t[ \"$PHYNBR\" = \"1\" ] && [ -n \"$label_mac\" ] && \\\n\t\tmacaddr_unsetbit \"$label_mac\" 6 > /sys${DEVPATH}/macaddress\n\t\t;;\n\tiptime,a3002mesh|\\\n\tiptime,a3004t)\n\t\thw_mac_addr=\"$(mtd_get_mac_binary factory 0x4)\"\n\t\t[ \"$PHYNBR\" = \"0\" ] && \\\n\t\t\tmacaddr_setbit_la \"$(macaddr_add $hw_mac_addr 3)\" > /sys${DEVPATH}/macaddress\n\t\t[ \"$PHYNBR\" = \"1\" ] && echo -n \"$hw_mac_addr\" > /sys${DEVPATH}/macaddress\n\t\t;;\n\tiptime,ax2004m)\n\t\tif [ \"$PHYNBR\" = \"1\" ]; then\n\t\t\thw_mac_addr=\"$(mtd_get_mac_binary factory 0x4)\"\n\t\t\tmacaddr_setbit_la \"$(macaddr_add $hw_mac_addr 3)\" > /sys${DEVPATH}/macaddress\n\t\tfi\n\t\t;;\n\tjcg,q20)\n\t\t[ \"$PHYNBR\" = \"1\" ] && \\\n\t\t\tmacaddr_setbit_la \"$(mtd_get_mac_binary Factory 0x4)\" > /sys${DEVPATH}/macaddress\n\t\t;;\n\tjcg,y2)\n\t\t[ \"$PHYNBR\" = \"1\" ] && \\\n\t\t\tmacaddr_setbit_la \"$(mtd_get_mac_binary factory 0x4)\" > /sys${DEVPATH}/macaddress\n\t\t;;\n\tlinksys,e5600|\\\n\tlinksys,ea6350-v4|\\\n\tlinksys,ea7300-v1|\\\n\tlinksys,ea7300-v2|\\\n\tlinksys,ea7500-v2|\\\n\tlinksys,ea8100-v1|\\\n\tlinksys,ea8100-v2)\n\t\thw_mac_addr=$(mtd_get_mac_ascii devinfo hw_mac_addr)\n\t\t[ \"$PHYNBR\" = \"0\" ] && macaddr_add $hw_mac_addr 1 > /sys${DEVPATH}/macaddress\n\t\t[ \"$PHYNBR\" = \"1\" ] && macaddr_add $hw_mac_addr 2 > /sys${DEVPATH}/macaddress\n\t\t;;\n\toraybox,x3a)\n\t\tif [ \"$PHYNBR\" = \"1\" ]; then\n\t\t\thw_mac_addr=\"$(mtd_get_mac_binary factory 0x4)\"\n\t\t\tmacaddr_setbit_la \"$(macaddr_add $hw_mac_addr 0x100000)\" > /sys${DEVPATH}/macaddress\n\t\tfi\n\t\t;;\n\traisecom,msg1500-x-00)\n\t\t[ \"$PHYNBR\" = \"0\" ] && \\\n\t\t\tmacaddr_setbit_la \"$(mtd_get_mac_ascii Config protest_lan_mac)\" \\\n\t\t\t\t> /sys${DEVPATH}/macaddress\n\t\t;;\n\ttenbay,t-mb5eu-v01)\n\t\thw_mac_addr=\"$(mtd_get_mac_binary factory 0x4)\"\n\t\t[ \"$PHYNBR\" = \"1\" ] &&  macaddr_add $hw_mac_addr \"0x100000\" > /sys${DEVPATH}/macaddress\n\t\t;;\n\tyuncore,ax820)\n\t\t[ \"$PHYNBR\" = \"1\" ] && \\\n\t\t\tmacaddr_setbit_la \"$(mtd_get_mac_binary Factory 0xe000)\" > /sys${DEVPATH}/macaddress\n\t\t;;\nesac\n"
  },
  {
    "path": "target/linux/ramips/mt7621/base-files/etc/init.d/bootcount",
    "content": "#!/bin/sh /etc/rc.common\n\nSTART=99\n\nboot() {\n\tcase $(board_name) in\n\talfa-network,quad-e4g)\n\t\t[ -n \"$(fw_printenv bootcount bootchanged 2>/dev/null)\" ] &&\\\n\t\t\techo -e \"bootcount\\nbootchanged\\n\" | /usr/sbin/fw_setenv -s -\n\t\t;;\n\tlinksys,e5600|\\\n\tlinksys,ea6350-v4|\\\n\tlinksys,ea7300-v1|\\\n\tlinksys,ea7300-v2|\\\n\tlinksys,ea7500-v2|\\\n\tlinksys,ea8100-v1|\\\n\tlinksys,ea8100-v2)\n\t\tmtd resetbc s_env || true\n\t\t;;\n\tsamknows,whitebox-v8)\n\t\tfw_setenv bootcount 0\n\t\t;;\n\tzyxel,nr7101)\n\t\t[ $(printf %d $(fw_printenv -n DebugFlag)) -gt 0 ] || fw_setenv DebugFlag 0x1\n\t\t[ $(printf %d $(fw_printenv -n Image1Stable)) -gt 0 ] || fw_setenv Image1Stable 1\n\t\t[ $(printf %d $(fw_printenv -n Image1Try)) -gt 0 ] && fw_setenv Image1Try 0\n\t\t;;\n\tesac\n}\n"
  },
  {
    "path": "target/linux/ramips/mt7621/base-files/etc/init.d/set-irq-affinity",
    "content": "#!/bin/sh /etc/rc.common\n\nSTART=99\n\nstart() {\n\tif grep -q 'processor.*: 2' /proc/cpuinfo; then\n\t\tmask=4\n\telif grep -q 'processor.*: 1' /proc/cpuinfo; then\n\t\tmask=2\n\telse\n\t\treturn\n\tfi\n\n\tfor irq in $(grep \"mt76..e\" /proc/interrupts | cut -d: -f1 | sed 's, *,,')\n\tdo\n\t\techo \"$mask\" > \"/proc/irq/$irq/smp_affinity\"\n\t\t[ $mask = 4 ] && mask=8\n\tdone\n}\n"
  },
  {
    "path": "target/linux/ramips/mt7621/base-files/etc/uci-defaults/01_enable_packet_steering",
    "content": "uci -q get network.globals.packet_steering > /dev/null || {\n\tuci set network.globals='globals'\n\tuci set network.globals.packet_steering=1\n\tuci commit network\n}\n"
  },
  {
    "path": "target/linux/ramips/mt7621/base-files/lib/upgrade/iodata.sh",
    "content": "#\n# Copyright (C) 2019 OpenWrt.org\n#\n\n. /lib/functions.sh\n\niodata_mstc_prepare_fail() {\n\techo \"failed to check and prepare the environment, rebooting...\"\n\tumount -a\n\treboot -f\n}\n\n# I-O DATA devices manufactured by MSTC (MitraStar Technology Corp.)\n# have two important flags:\n# - bootnum: switch between two os images\n#     use 1st image in OpenWrt\n# - debugflag: enable/disable debug\n#     users can interrupt Z-Loader for recovering the device if enabled\n#\n# parameters:\n# - $1: the offset of \"debugflag\"\niodata_mstc_upgrade_prepare() {\n\tlocal persist_mtd=\"$(find_mtd_part persist)\"\n\tlocal factory_mtd=\"$(find_mtd_part factory)\"\n\tlocal dflag_offset=\"$1\"\n\n\tif [ -z \"$dflag_offset\" ]; then\n\t\techo 'no debugflag offset provided'\n\t\tiodata_mstc_prepare_fail\n\tfi\n\n\tif [ -z \"$persist_mtd\" ] || [ -z \"$factory_mtd\" ]; then\n\t\techo 'cannot find mtd partition(s), \"factory\" or \"persist\"'\n\t\tiodata_mstc_prepare_fail\n\tfi\n\n\tlocal bootnum=$(hexdump -s 4 -n 1 -e '\"%x\"' ${persist_mtd})\n\tlocal debugflag=$(hexdump -s $((dflag_offset)) -n 1 -e '\"%x\"' ${factory_mtd})\n\n\tif [ \"$bootnum\" != \"1\" ] && [ \"$bootnum\" != \"2\" ]; then\n\t\techo \"failed to get bootnum, please check the value at 0x4 in ${persist_mtd}\"\n\t\tiodata_mstc_prepare_fail\n\tfi\n\tif [ \"$debugflag\" != \"0\" ] && [ \"$debugflag\" != \"1\" ]; then\n\t\techo \"failed to get debugflag, please check the value at ${dflag_offset} in ${factory_mtd}\"\n\t\tiodata_mstc_prepare_fail\n\tfi\n\techo \"current: bootnum => ${bootnum}, debugflag => ${debugflag}\"\n\n\tif [ \"$bootnum\" = \"2\" ]; then\n\t\tif ! (echo -ne \"\\x01\" | dd bs=1 count=1 seek=4 conv=notrunc of=${persist_mtd} 2>/dev/null); then\n\t\t\techo \"failed to set bootnum\"\n\t\t\tiodata_mstc_prepare_fail\n\t\tfi\n\t\techo \"### switch to 1st os-image on next boot ###\"\n\tfi\n\tif [ \"$debugflag\" = \"0\" ]; then\n\t\tif ! (echo -ne \"\\x01\" | dd bs=1 count=1 seek=$((dflag_offset)) conv=notrunc of=${factory_mtd} 2>/dev/null); then\n\t\t\techo \"failed to set debugflag\"\n\t\t\tiodata_mstc_prepare_fail\n\t\tfi\n\t\techo \"### enable debug ###\"\n\tfi\n}\n"
  },
  {
    "path": "target/linux/ramips/mt7621/base-files/lib/upgrade/platform.sh",
    "content": "#\n# Copyright (C) 2010 OpenWrt.org\n#\n\nPART_NAME=firmware\nREQUIRE_IMAGE_METADATA=1\n\nRAMFS_COPY_BIN='fw_printenv fw_setenv'\nRAMFS_COPY_DATA='/etc/fw_env.config /var/lock/fw_printenv.lock'\n\nplatform_check_image() {\n\treturn 0\n}\n\nplatform_do_upgrade() {\n\tlocal board=$(board_name)\n\n\tcase \"$board\" in\n\talfa-network,quad-e4g)\n\t\t[ \"$(fw_printenv -n dual_image 2>/dev/null)\" = \"1\" ] &&\\\n\t\t[ -n \"$(find_mtd_part backup)\" ] && {\n\t\t\tPART_NAME=backup\n\t\t\tif [ \"$(fw_printenv -n bootactive 2>/dev/null)\" = \"1\" ]; then\n\t\t\t\tfw_setenv bootactive 2 || exit 1\n\t\t\telse\n\t\t\t\tfw_setenv bootactive 1 || exit 1\n\t\t\tfi\n\t\t}\n\t\t;;\n\tampedwireless,ally-00x19k|\\\n\tampedwireless,ally-r1900k)\n\t\tif [ \"$(fw_printenv --lock / -n bootImage 2>/dev/null)\" != \"0\" ]; then\n\t\t\tfw_setenv --lock / bootImage 0 || exit 1\n\t\tfi\n\t\t;;\n\tmikrotik,routerboard-750gr3|\\\n\tmikrotik,routerboard-760igs|\\\n\tmikrotik,routerboard-m11g|\\\n\tmikrotik,routerboard-m33g)\n\t\t[ \"$(rootfs_type)\" = \"tmpfs\" ] && mtd erase firmware\n\t\t;;\n\tasus,rt-ac65p|\\\n\tasus,rt-ac85p)\n\t\techo \"Backing up firmware\"\n\t\tdd if=/dev/mtd4 bs=1024 count=4096  > /tmp/backup_firmware.bin\n\t\tdd if=/dev/mtd5 bs=1024 count=52224 >> /tmp/backup_firmware.bin\n\t\tmtd -e firmware2 write /tmp/backup_firmware.bin firmware2\n\t\t;;\n\tesac\n\n\tcase \"$board\" in\n\tampedwireless,ally-00x19k|\\\n\tampedwireless,ally-r1900k|\\\n\tasus,rt-ac65p|\\\n\tasus,rt-ac85p|\\\n\tbeeline,smartbox-flash|\\\n\tdlink,dir-1960-a1|\\\n\tdlink,dir-2640-a1|\\\n\tdlink,dir-2660-a1|\\\n\tdlink,dir-853-a3|\\\n\thiwifi,hc5962|\\\n\tiptime,a3004t|\\\n\tiptime,ax2004m|\\\n\tiptime,t5004|\\\n\tjcg,q20|\\\n\tlinksys,e5600|\\\n\tlinksys,ea6350-v4|\\\n\tlinksys,ea7300-v1|\\\n\tlinksys,ea7300-v2|\\\n\tlinksys,ea7500-v2|\\\n\tlinksys,ea8100-v1|\\\n\tlinksys,ea8100-v2|\\\n\tnetgear,r6220|\\\n\tnetgear,r6260|\\\n\tnetgear,r6350|\\\n\tnetgear,r6700-v2|\\\n\tnetgear,r6800|\\\n\tnetgear,r6850|\\\n\tnetgear,r6900-v2|\\\n\tnetgear,r7200|\\\n\tnetgear,r7450|\\\n\tnetgear,wac104|\\\n\tnetgear,wac124|\\\n\tnetis,wf2881|\\\n\traisecom,msg1500-x-00|\\\n\tsercomm,na502|\\\n\txiaomi,mi-router-3g|\\\n\txiaomi,mi-router-3-pro|\\\n\txiaomi,mi-router-4|\\\n\txiaomi,mi-router-ac2100|\\\n\txiaomi,mi-router-cr6606|\\\n\txiaomi,mi-router-cr6608|\\\n\txiaomi,mi-router-cr6609|\\\n\txiaomi,redmi-router-ac2100)\n\t\tnand_do_upgrade \"$1\"\n\t\t;;\n\tiodata,wn-ax1167gr2|\\\n\tiodata,wn-ax2033gr|\\\n\tiodata,wn-dx1167r|\\\n\tiodata,wn-dx2033gr)\n\t\tiodata_mstc_upgrade_prepare \"0xfe75\"\n\t\tnand_do_upgrade \"$1\"\n\t\t;;\n\tiodata,wn-dx1200gr)\n\t\tiodata_mstc_upgrade_prepare \"0x1fe75\"\n\t\tnand_do_upgrade \"$1\"\n\t\t;;\n\tubnt,edgerouter-x|\\\n\tubnt,edgerouter-x-sfp)\n\t\tplatform_upgrade_ubnt_erx \"$1\"\n\t\t;;\n\tzyxel,nr7101)\n\t\tfw_setenv CheckBypass 0\n\t\tfw_setenv Image1Stable 0\n\t\tCI_KERNPART=\"Kernel\"\n\t\tnand_do_upgrade \"$1\"\n\t\t;;\n\tzyxel,wap6805)\n\t\tlocal kernel2_mtd=\"$(find_mtd_part Kernel2)\"\n\t\t[ \"$(hexdump -n 4 -e '\"%x\"' $kernel2_mtd)\" = \"56190527\" ] &&\\\n\t\t[ \"$(hexdump -n 4 -s 104 -e '\"%x\"' $kernel2_mtd)\" != \"0\" ] &&\\\n\t\tdd bs=4 count=1 seek=26 conv=notrunc if=/dev/zero of=$kernel2_mtd 2>/dev/null &&\\\n\t\techo \"Kernel2 sequence number was reset to 0\"\n\t\tCI_KERNPART=\"Kernel\"\n\t\tnand_do_upgrade \"$1\"\n\t\t;;\n\t*)\n\t\tdefault_do_upgrade \"$1\"\n\t\t;;\n\tesac\n}\n"
  },
  {
    "path": "target/linux/ramips/mt7621/base-files/lib/upgrade/ubnt.sh",
    "content": "#\n# Copyright (C) 2015 OpenWrt.org\n#\n\n. /lib/functions.sh\n#Note: this code also uses some functions from nand.sh, but it is expected to be run by nand.sh, so we are not\n#sourcing it explicitly here\n\nUBNT_ERX_KERNEL_INDEX_OFFSET=160\n\nubnt_get_target_kernel() {\n\tlocal factory_mtd=$1\n\tlocal current_kernel_index=$(hexdump -s $UBNT_ERX_KERNEL_INDEX_OFFSET -n 1 -e '/1 \"%X \"' ${factory_mtd})\n\n\tif [ $current_kernel_index == \"0\" ]; then\n\t\techo 'kernel2'\n\telif [ $current_kernel_index == \"1\" ]; then\n\t\techo 'kernel1'\n\tfi\n}\n\nubnt_update_target_kernel() {\n\tlocal factory_mtd=$1\n\tlocal kernel_part=$2\n\n\tlocal new_kernel_index\n\tif [ $kernel_part == \"kernel1\" ]; then\n\t\tnew_kernel_index=\"\\x00\"\n\telif [ $kernel_part == \"kernel2\" ]; then\n\t\tnew_kernel_index=\"\\x01\"\n\telse\n\t\techo 'Unknown kernel image index' >&2\n\t\treturn 1\n\tfi\n\n\tif ! (echo -e $new_kernel_index | dd of=${factory_mtd} bs=1 count=1 seek=$UBNT_ERX_KERNEL_INDEX_OFFSET); then\n\t\techo 'Failed to update kernel bootup index' >&2\n\t\treturn 1\n\tfi\n}\n\nplatform_upgrade_ubnt_erx() {\n\tlocal factory_mtd=$(find_mtd_part factory)\n\tif [ -z \"$factory_mtd\" ]; then\n\t\techo \"cannot find factory partition\" >&2\n\t\texit 1\n\tfi\n\n\tlocal kernel_part=\"$(ubnt_get_target_kernel ${factory_mtd})\"\n\tif [ -z \"$kernel_part\" ]; then\n\t\techo \"cannot find factory partition\" >&2\n\t\texit 1\n\tfi\n\n\t# This is a global defined in nand.sh, sets partition kernel will be flashed into\n\tCI_KERNPART=${kernel_part}\n\n\t#Remove volume possibly left over from stock firmware\n\tlocal ubidev=\"$( nand_find_ubi \"$CI_UBIPART\" )\"\n\tif [ -z \"$ubidev\" ]; then\n\t\tlocal mtdnum=\"$( find_mtd_index \"$CI_UBIPART\" )\"\n\t\tif [ -z \"$mtdnum\" ]; then\n\t\t\techo \"cannot find ubi mtd partition $CI_UBIPART\" >&2\n\t\t\texit 1\n\t\tfi\n\t\tubiattach -m \"$mtdnum\"\n\t\tsync\n\t\tubidev=\"$( nand_find_ubi \"$CI_UBIPART\" )\"\n\tfi\n\tif [ -n \"$ubidev\" ]; then\n\t\tlocal troot_ubivol=\"$( nand_find_volume $ubidev troot )\"\n\t\t[ -n \"$troot_ubivol\" ] && ubirmvol /dev/$ubidev -N troot || true\n\tfi\n\n\tubnt_update_target_kernel ${factory_mtd} ${kernel_part} || exit 1\n\n\tnand_do_upgrade \"$1\"\n}\n"
  },
  {
    "path": "target/linux/ramips/mt7621/base-files/sbin/fixup-mac-address",
    "content": "#!/bin/sh\n. /lib/functions.sh\n. /lib/functions/system.sh\n\npartname=\"\"\noffset=\"\"\nNEW_MAC=\nYES=\n\nboard=$(board_name)\ncase $board in\n\tmqmaker,witi)\n\t\tpartname=factory\n\t\toffset=$((0xe000))\n\t;;\n\t*)\n\t\techo \"Unsupported board\"\n\t\texit 1\n\t;;\nesac\n\nwhile [ -n \"$1\" ]; do\n\tcase \"$1\" in\n\t\t??:??:??:??:??:??) NEW_MAC=\"$1\";;\n\t\t-y) YES=1;;\n\t\t*)\n\t\t\tcat <<EOF\nUnknown option/argument '$1'\nUsage: $0 [-y] [<macaddr>]\nEOF\n\t\t\texit 1\n\t\t;;\n\tesac\n\tshift\ndone\n\nask_bool() {\n\tlocal message=\"$1\"\n\tlocal default=\"$((! ${2:-0}))\"\n\t[ -n \"$YES\" ] && return 0\n\techo -n \"$message \"\n\tread opt\n\tcase \"$opt\" in\n\t\ty|Y) return 0;;\n\t\tn|N) return 1;;\n\t\t*) return $default;;\n\tesac\n}\n\nconvert_hex() {\n\thexdump -e '/1 \"%02x \"'\n}\n\ngen_mac() {\n\tdd if=/dev/urandom bs=6 count=1 2>/dev/null\n}\n\nmac=\"$(mtd_get_mac_binary $partname $offset)\"\ncase \"$mac\" in\n\t00:00:00:00:00:00);;\n\tff:ff:ff:ff:ff:ff);;\n\t*)\n\t\techo \"Current MAC address: $mac\"\n\t\task_bool \"Overwrite (y/N)?\" 0 || exit\n\t;;\nesac\n\nif [ -n \"$NEW_MAC\" ]; then\n\tset -- $(echo \"$NEW_MAC\" | sed 's,:, ,g')\nelse\n\tset -- $(gen_mac | convert_hex)\n\tset -- $(printf %02x $(( (0x$1 & 0xfe) | 0x02 ))) $2 $3 $4 $5 $6\nfi\necho \"New MAC address: $1:$2:$3:$4:$5:$6\"\nask_bool \"Write to EEPROM (y/N)?\" || exit\n\npart=$(find_mtd_part \"$partname\")\n[ -n \"$part\" ] || exit\necho -ne \"\\x$1\\x$2\\x$3\\x$4\\x$5\\x$6\" | dd of=$part conv=notrunc bs=1 count=6 seek=$offset 2>/dev/null\necho \"Done\"\n"
  },
  {
    "path": "target/linux/ramips/mt7621/config-5.10",
    "content": "CONFIG_ARCH_32BIT_OFF_T=y\nCONFIG_ARCH_HIBERNATION_POSSIBLE=y\nCONFIG_ARCH_MMAP_RND_BITS_MAX=15\nCONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15\nCONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED=y\nCONFIG_ARCH_SUSPEND_POSSIBLE=y\nCONFIG_AT803X_PHY=y\nCONFIG_BLK_MQ_PCI=y\nCONFIG_BOARD_SCACHE=y\nCONFIG_BOUNCE=y\nCONFIG_CEVT_R4K=y\nCONFIG_CLKDEV_LOOKUP=y\nCONFIG_CLKSRC_MIPS_GIC=y\nCONFIG_CLOCKSOURCE_WATCHDOG=y\nCONFIG_CLONE_BACKWARDS=y\nCONFIG_CMDLINE=\"rootfstype=squashfs,jffs2\"\nCONFIG_CMDLINE_BOOL=y\n# CONFIG_CMDLINE_OVERRIDE is not set\nCONFIG_COMMON_CLK=y\n# CONFIG_COMMON_CLK_BOSTON is not set\nCONFIG_COMPAT_32BIT_TIME=y\nCONFIG_CPU_GENERIC_DUMP_TLB=y\nCONFIG_CPU_HAS_DIEI=y\nCONFIG_CPU_HAS_PREFETCH=y\nCONFIG_CPU_HAS_RIXI=y\nCONFIG_CPU_HAS_SYNC=y\nCONFIG_CPU_IDLE=y\n# CONFIG_CPU_IDLE_GOV_LADDER is not set\nCONFIG_CPU_IDLE_GOV_TEO=y\nCONFIG_CPU_MIPS32=y\n# CONFIG_CPU_MIPS32_R1 is not set\nCONFIG_CPU_MIPS32_R2=y\nCONFIG_CPU_MIPSR2=y\nCONFIG_CPU_MIPSR2_IRQ_EI=y\nCONFIG_CPU_MIPSR2_IRQ_VI=y\nCONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y\nCONFIG_CPU_PM=y\nCONFIG_CPU_R4K_CACHE_TLB=y\nCONFIG_CPU_RMAP=y\nCONFIG_CPU_SUPPORTS_32BIT_KERNEL=y\nCONFIG_CPU_SUPPORTS_HIGHMEM=y\nCONFIG_CPU_SUPPORTS_MSA=y\nCONFIG_CRC16=y\nCONFIG_CRYPTO_ACOMP2=y\nCONFIG_CRYPTO_DEFLATE=y\nCONFIG_CRYPTO_HASH_INFO=y\nCONFIG_CRYPTO_LIB_POLY1305_RSIZE=2\nCONFIG_CRYPTO_LZO=y\nCONFIG_CRYPTO_RNG2=y\nCONFIG_CSRC_R4K=y\nCONFIG_DEBUG_PINCTRL=y\nCONFIG_DIMLIB=y\nCONFIG_DMA_NONCOHERENT=y\n# CONFIG_DTB_GNUBEE1 is not set\n# CONFIG_DTB_GNUBEE2 is not set\nCONFIG_DTB_RT_NONE=y\nCONFIG_DTC=y\nCONFIG_EARLY_PRINTK=y\nCONFIG_FIXED_PHY=y\nCONFIG_FW_LOADER_PAGED_BUF=y\nCONFIG_GENERIC_ATOMIC64=y\nCONFIG_GENERIC_CLOCKEVENTS=y\nCONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y\nCONFIG_GENERIC_CMOS_UPDATE=y\nCONFIG_GENERIC_CPU_AUTOPROBE=y\nCONFIG_GENERIC_GETTIMEOFDAY=y\nCONFIG_GENERIC_IOMAP=y\nCONFIG_GENERIC_IRQ_CHIP=y\nCONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y\nCONFIG_GENERIC_IRQ_SHOW=y\nCONFIG_GENERIC_LIB_ASHLDI3=y\nCONFIG_GENERIC_LIB_ASHRDI3=y\nCONFIG_GENERIC_LIB_CMPDI2=y\nCONFIG_GENERIC_LIB_LSHRDI3=y\nCONFIG_GENERIC_LIB_UCMPDI2=y\nCONFIG_GENERIC_PCI_IOMAP=y\nCONFIG_GENERIC_PHY=y\nCONFIG_GENERIC_PINCONF=y\nCONFIG_GENERIC_SCHED_CLOCK=y\nCONFIG_GENERIC_SMP_IDLE_THREAD=y\nCONFIG_GENERIC_TIME_VSYSCALL=y\nCONFIG_GLOB=y\nCONFIG_GPIOLIB=y\nCONFIG_GPIOLIB_IRQCHIP=y\nCONFIG_GPIO_GENERIC=y\nCONFIG_GPIO_MT7621=y\n# CONFIG_GPIO_RALINK is not set\nCONFIG_GPIO_WATCHDOG=y\n# CONFIG_GPIO_WATCHDOG_ARCH_INITCALL is not set\nCONFIG_GRO_CELLS=y\nCONFIG_HANDLE_DOMAIN_IRQ=y\nCONFIG_HARDWARE_WATCHPOINTS=y\nCONFIG_HAS_DMA=y\nCONFIG_HAS_IOMEM=y\nCONFIG_HAS_IOPORT_MAP=y\nCONFIG_HIGHMEM=y\nCONFIG_I2C=y\nCONFIG_I2C_BOARDINFO=y\nCONFIG_I2C_CHARDEV=y\nCONFIG_I2C_GPIO=y\nCONFIG_I2C_MT7621=y\nCONFIG_INITRAMFS_SOURCE=\"\"\nCONFIG_IRQCHIP=y\nCONFIG_IRQ_DOMAIN=y\nCONFIG_IRQ_DOMAIN_HIERARCHY=y\nCONFIG_IRQ_FORCED_THREADING=y\nCONFIG_IRQ_MIPS_CPU=y\nCONFIG_IRQ_WORK=y\n# CONFIG_KERNEL_ZSTD is not set\nCONFIG_LED_TRIGGER_PHY=y\nCONFIG_LIBFDT=y\nCONFIG_LOCK_DEBUGGING_SUPPORT=y\nCONFIG_LZO_COMPRESS=y\nCONFIG_LZO_DECOMPRESS=y\nCONFIG_MDIO_BUS=y\nCONFIG_MDIO_DEVICE=y\nCONFIG_MEDIATEK_GE_PHY=y\nCONFIG_MEMFD_CREATE=y\nCONFIG_MFD_SYSCON=y\nCONFIG_MIGRATION=y\nCONFIG_MIKROTIK=y\nCONFIG_MIKROTIK_RB_SYSFS=y\nCONFIG_MIPS=y\nCONFIG_MIPS_ASID_BITS=8\nCONFIG_MIPS_ASID_SHIFT=0\nCONFIG_MIPS_CBPF_JIT=y\nCONFIG_MIPS_CLOCK_VSYSCALL=y\nCONFIG_MIPS_CM=y\n# CONFIG_MIPS_CMDLINE_BUILTIN_EXTEND is not set\n# CONFIG_MIPS_CMDLINE_DTB_EXTEND is not set\n# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set\nCONFIG_MIPS_CMDLINE_FROM_DTB=y\nCONFIG_MIPS_CPC=y\nCONFIG_MIPS_CPS=y\nCONFIG_MIPS_CPS_CPUIDLE=y\n# CONFIG_MIPS_CPS_NS16550_BOOL is not set\nCONFIG_MIPS_CPS_PM=y\nCONFIG_MIPS_CPU_SCACHE=y\n# CONFIG_MIPS_ELF_APPENDED_DTB is not set\nCONFIG_MIPS_GIC=y\nCONFIG_MIPS_L1_CACHE_SHIFT=5\nCONFIG_MIPS_LD_CAN_LINK_VDSO=y\nCONFIG_MIPS_MT=y\nCONFIG_MIPS_MT_FPAFF=y\nCONFIG_MIPS_MT_SMP=y\n# CONFIG_MIPS_NO_APPENDED_DTB is not set\nCONFIG_MIPS_NR_CPU_NR_MAP=4\nCONFIG_MIPS_PERF_SHARED_TC_COUNTERS=y\nCONFIG_MIPS_RAW_APPENDED_DTB=y\nCONFIG_MIPS_SPRAM=y\nCONFIG_MODULES_USE_ELF_REL=y\nCONFIG_MT7621_WDT=y\n# CONFIG_MTD_CFI_INTELEXT is not set\nCONFIG_MTD_CMDLINE_PARTS=y\nCONFIG_MTD_NAND_CORE=y\nCONFIG_MTD_NAND_ECC=y\nCONFIG_MTD_NAND_ECC_SW_HAMMING=y\nCONFIG_MTD_NAND_MT7621=y\nCONFIG_MTD_NAND_MTK_BMT=y\nCONFIG_MTD_PHYSMAP=y\nCONFIG_MTD_RAW_NAND=y\nCONFIG_MTD_ROUTERBOOT_PARTS=y\nCONFIG_MTD_SPI_NOR=y\nCONFIG_MTD_SPI_NOR_USE_VARIABLE_ERASE=y\nCONFIG_MTD_SPLIT_FIT_FW=y\nCONFIG_MTD_SPLIT_MINOR_FW=y\nCONFIG_MTD_SPLIT_SEAMA_FW=y\nCONFIG_MTD_SPLIT_TPLINK_FW=y\nCONFIG_MTD_SPLIT_TRX_FW=y\nCONFIG_MTD_SPLIT_UIMAGE_FW=y\nCONFIG_MTD_UBI=y\nCONFIG_MTD_UBI_BEB_LIMIT=20\nCONFIG_MTD_UBI_BLOCK=y\nCONFIG_MTD_UBI_WL_THRESHOLD=4096\nCONFIG_MTD_VIRT_CONCAT=y\n# CONFIG_MTK_HSDMA is not set\nCONFIG_NEED_DMA_MAP_STATE=y\nCONFIG_NET_DEVLINK=y\nCONFIG_NET_DSA=y\nCONFIG_NET_DSA_MT7530=y\nCONFIG_NET_DSA_TAG_MTK=y\nCONFIG_NET_FLOW_LIMIT=y\nCONFIG_NET_MEDIATEK_SOC=y\nCONFIG_NET_SWITCHDEV=y\nCONFIG_NET_VENDOR_MEDIATEK=y\n# CONFIG_NET_VENDOR_RALINK is not set\nCONFIG_NO_HZ_COMMON=y\nCONFIG_NO_HZ_IDLE=y\nCONFIG_NR_CPUS=4\nCONFIG_NVMEM=y\nCONFIG_OF=y\nCONFIG_OF_ADDRESS=y\nCONFIG_OF_EARLY_FLATTREE=y\nCONFIG_OF_FLATTREE=y\nCONFIG_OF_GPIO=y\nCONFIG_OF_IRQ=y\nCONFIG_OF_KOBJ=y\nCONFIG_OF_MDIO=y\nCONFIG_OF_NET=y\nCONFIG_PADATA=y\nCONFIG_PCI=y\nCONFIG_PCI_DISABLE_COMMON_QUIRKS=y\nCONFIG_PCI_DOMAINS=y\nCONFIG_PCI_DOMAINS_GENERIC=y\nCONFIG_PCI_DRIVERS_GENERIC=y\nCONFIG_PCI_MT7621=y\nCONFIG_PCI_MT7621_PHY=y\nCONFIG_PERF_USE_VMALLOC=y\nCONFIG_PGTABLE_LEVELS=2\nCONFIG_PHYLIB=y\nCONFIG_PHYLINK=y\n# CONFIG_PHY_RALINK_USB is not set\nCONFIG_PINCTRL=y\nCONFIG_PINCTRL_AW9523=y\nCONFIG_PINCTRL_RT2880=y\n# CONFIG_PINCTRL_SINGLE is not set\nCONFIG_PINCTRL_SX150X=y\nCONFIG_POWER_RESET=y\nCONFIG_POWER_RESET_GPIO=y\nCONFIG_POWER_SUPPLY=y\nCONFIG_QUEUED_RWLOCKS=y\nCONFIG_QUEUED_SPINLOCKS=y\nCONFIG_RALINK=y\n# CONFIG_RALINK_WDT is not set\nCONFIG_RATIONAL=y\nCONFIG_REGMAP=y\nCONFIG_REGMAP_MMIO=y\nCONFIG_REGULATOR=y\nCONFIG_REGULATOR_FIXED_VOLTAGE=y\nCONFIG_RESET_CONTROLLER=y\nCONFIG_RFS_ACCEL=y\nCONFIG_RPS=y\nCONFIG_RTC_CLASS=y\nCONFIG_RTC_DRV_BQ32K=y\nCONFIG_RTC_DRV_PCF8563=y\nCONFIG_RTC_I2C_AND_SPI=y\nCONFIG_RTC_MC146818_LIB=y\nCONFIG_SCHED_SMT=y\nCONFIG_SERIAL_8250_NR_UARTS=3\nCONFIG_SERIAL_8250_RUNTIME_UARTS=3\nCONFIG_SERIAL_MCTRL_GPIO=y\nCONFIG_SERIAL_OF_PLATFORM=y\nCONFIG_SGL_ALLOC=y\nCONFIG_SMP=y\nCONFIG_SMP_UP=y\nCONFIG_SOC_BUS=y\n# CONFIG_SOC_MT7620 is not set\nCONFIG_SOC_MT7621=y\n# CONFIG_SOC_RT288X is not set\n# CONFIG_SOC_RT305X is not set\n# CONFIG_SOC_RT3883 is not set\nCONFIG_SPI=y\nCONFIG_SPI_MASTER=y\nCONFIG_SPI_MEM=y\nCONFIG_SPI_MT7621=y\n# CONFIG_SPI_RT2880 is not set\nCONFIG_SRCU=y\nCONFIG_SWPHY=y\nCONFIG_SYNC_R4K=y\nCONFIG_SYSCTL_EXCEPTION_TRACE=y\nCONFIG_SYS_HAS_CPU_MIPS32_R1=y\nCONFIG_SYS_HAS_CPU_MIPS32_R2=y\nCONFIG_SYS_HAS_EARLY_PRINTK=y\nCONFIG_SYS_SUPPORTS_32BIT_KERNEL=y\nCONFIG_SYS_SUPPORTS_ARBIT_HZ=y\nCONFIG_SYS_SUPPORTS_HIGHMEM=y\nCONFIG_SYS_SUPPORTS_HOTPLUG_CPU=y\nCONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y\nCONFIG_SYS_SUPPORTS_MIPS16=y\nCONFIG_SYS_SUPPORTS_MIPS_CPS=y\nCONFIG_SYS_SUPPORTS_MULTITHREADING=y\nCONFIG_SYS_SUPPORTS_SCHED_SMT=y\nCONFIG_SYS_SUPPORTS_SMP=y\nCONFIG_SYS_SUPPORTS_ZBOOT=y\nCONFIG_TARGET_ISA_REV=2\nCONFIG_TICK_CPU_ACCOUNTING=y\nCONFIG_TIMER_OF=y\nCONFIG_TIMER_PROBE=y\nCONFIG_TREE_RCU=y\nCONFIG_TREE_SRCU=y\nCONFIG_UBIFS_FS=y\nCONFIG_USB_SUPPORT=y\nCONFIG_USE_OF=y\nCONFIG_WATCHDOG_CORE=y\nCONFIG_WEAK_ORDERING=y\nCONFIG_WEAK_REORDERING_BEYOND_LLSC=y\nCONFIG_XPS=y\nCONFIG_ZLIB_DEFLATE=y\nCONFIG_ZLIB_INFLATE=y\n"
  },
  {
    "path": "target/linux/ramips/mt7621/config-5.15",
    "content": "CONFIG_ARCH_32BIT_OFF_T=y\nCONFIG_ARCH_HIBERNATION_POSSIBLE=y\nCONFIG_ARCH_KEEP_MEMBLOCK=y\nCONFIG_ARCH_MMAP_RND_BITS_MAX=15\nCONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15\nCONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED=y\nCONFIG_ARCH_SUSPEND_POSSIBLE=y\nCONFIG_AT803X_PHY=y\nCONFIG_BLK_MQ_PCI=y\nCONFIG_BOARD_SCACHE=y\nCONFIG_BOUNCE=y\nCONFIG_CEVT_R4K=y\nCONFIG_CLKSRC_MIPS_GIC=y\n# CONFIG_CLKSRC_PISTACHIO is not set\nCONFIG_CLK_MT7621=y\nCONFIG_CLOCKSOURCE_WATCHDOG=y\nCONFIG_CLONE_BACKWARDS=y\nCONFIG_CMDLINE=\"rootfstype=squashfs,jffs2\"\nCONFIG_CMDLINE_BOOL=y\n# CONFIG_CMDLINE_OVERRIDE is not set\nCONFIG_COMMON_CLK=y\n# CONFIG_COMMON_CLK_PISTACHIO is not set\nCONFIG_COMPAT_32BIT_TIME=y\nCONFIG_CPU_GENERIC_DUMP_TLB=y\nCONFIG_CPU_HAS_DIEI=y\nCONFIG_CPU_HAS_PREFETCH=y\nCONFIG_CPU_HAS_RIXI=y\nCONFIG_CPU_HAS_SYNC=y\nCONFIG_CPU_IDLE=y\nCONFIG_CPU_IDLE_GOV_TEO=y\nCONFIG_CPU_MIPS32=y\n# CONFIG_CPU_MIPS32_R1 is not set\nCONFIG_CPU_MIPS32_R2=y\nCONFIG_CPU_MIPSR2=y\nCONFIG_CPU_MIPSR2_IRQ_EI=y\nCONFIG_CPU_MIPSR2_IRQ_VI=y\nCONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y\nCONFIG_CPU_PM=y\nCONFIG_CPU_R4K_CACHE_TLB=y\nCONFIG_CPU_RMAP=y\nCONFIG_CPU_SUPPORTS_32BIT_KERNEL=y\nCONFIG_CPU_SUPPORTS_HIGHMEM=y\nCONFIG_CPU_SUPPORTS_MSA=y\nCONFIG_CRC16=y\nCONFIG_CRYPTO_DEFLATE=y\nCONFIG_CRYPTO_HASH_INFO=y\nCONFIG_CRYPTO_LIB_POLY1305_RSIZE=2\nCONFIG_CRYPTO_LZO=y\nCONFIG_CRYPTO_RNG2=y\nCONFIG_CRYPTO_ZSTD=y\nCONFIG_CSRC_R4K=y\nCONFIG_DEBUG_PINCTRL=y\nCONFIG_DIMLIB=y\nCONFIG_DMA_NONCOHERENT=y\n# CONFIG_DTB_GNUBEE1 is not set\n# CONFIG_DTB_GNUBEE2 is not set\nCONFIG_DTB_RT_NONE=y\nCONFIG_DTC=y\nCONFIG_EARLY_PRINTK=y\nCONFIG_FIXED_PHY=y\nCONFIG_FWNODE_MDIO=y\nCONFIG_FW_LOADER_PAGED_BUF=y\nCONFIG_GENERIC_ATOMIC64=y\nCONFIG_GENERIC_CLOCKEVENTS=y\nCONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y\nCONFIG_GENERIC_CMOS_UPDATE=y\nCONFIG_GENERIC_CPU_AUTOPROBE=y\nCONFIG_GENERIC_FIND_FIRST_BIT=y\nCONFIG_GENERIC_GETTIMEOFDAY=y\nCONFIG_GENERIC_IOMAP=y\nCONFIG_GENERIC_IRQ_CHIP=y\nCONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y\nCONFIG_GENERIC_IRQ_SHOW=y\nCONFIG_GENERIC_LIB_ASHLDI3=y\nCONFIG_GENERIC_LIB_ASHRDI3=y\nCONFIG_GENERIC_LIB_CMPDI2=y\nCONFIG_GENERIC_LIB_LSHRDI3=y\nCONFIG_GENERIC_LIB_UCMPDI2=y\nCONFIG_GENERIC_PCI_IOMAP=y\nCONFIG_GENERIC_PHY=y\nCONFIG_GENERIC_PINCONF=y\nCONFIG_GENERIC_SCHED_CLOCK=y\nCONFIG_GENERIC_SMP_IDLE_THREAD=y\nCONFIG_GENERIC_TIME_VSYSCALL=y\nCONFIG_GLOB=y\nCONFIG_GPIOLIB=y\nCONFIG_GPIOLIB_IRQCHIP=y\nCONFIG_GPIO_CDEV=y\nCONFIG_GPIO_GENERIC=y\nCONFIG_GPIO_MT7621=y\n# CONFIG_GPIO_RALINK is not set\nCONFIG_GPIO_WATCHDOG=y\n# CONFIG_GPIO_WATCHDOG_ARCH_INITCALL is not set\nCONFIG_GRO_CELLS=y\nCONFIG_HANDLE_DOMAIN_IRQ=y\nCONFIG_HARDWARE_WATCHPOINTS=y\nCONFIG_HAS_DMA=y\nCONFIG_HAS_IOMEM=y\nCONFIG_HAS_IOPORT_MAP=y\nCONFIG_HIGHMEM=y\nCONFIG_I2C=y\nCONFIG_I2C_ALGOBIT=y\nCONFIG_I2C_BOARDINFO=y\nCONFIG_I2C_CHARDEV=y\nCONFIG_I2C_GPIO=y\nCONFIG_I2C_MT7621=y\n# CONFIG_INGENIC_CGU_JZ4760 is not set\nCONFIG_INITRAMFS_SOURCE=\"\"\nCONFIG_IRQCHIP=y\nCONFIG_IRQ_DOMAIN=y\nCONFIG_IRQ_DOMAIN_HIERARCHY=y\nCONFIG_IRQ_FORCED_THREADING=y\nCONFIG_IRQ_MIPS_CPU=y\nCONFIG_IRQ_WORK=y\nCONFIG_KMAP_LOCAL=y\nCONFIG_LED_TRIGGER_PHY=y\nCONFIG_LIBFDT=y\nCONFIG_LOCK_DEBUGGING_SUPPORT=y\nCONFIG_LZO_COMPRESS=y\nCONFIG_LZO_DECOMPRESS=y\n# CONFIG_MACH_NINTENDO64 is not set\n# CONFIG_MACH_REALTEK_RTL is not set\nCONFIG_MDIO_BUS=y\nCONFIG_MDIO_DEVICE=y\nCONFIG_MDIO_DEVRES=y\nCONFIG_MEDIATEK_GE_PHY=y\nCONFIG_MEMFD_CREATE=y\nCONFIG_MFD_SYSCON=y\nCONFIG_MIGRATION=y\nCONFIG_MIKROTIK=y\nCONFIG_MIKROTIK_RB_SYSFS=y\nCONFIG_MIPS=y\nCONFIG_MIPS_ASID_BITS=8\nCONFIG_MIPS_ASID_SHIFT=0\nCONFIG_MIPS_CLOCK_VSYSCALL=y\nCONFIG_MIPS_CM=y\n# CONFIG_MIPS_CMDLINE_BUILTIN_EXTEND is not set\n# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set\nCONFIG_MIPS_CMDLINE_FROM_DTB=y\nCONFIG_MIPS_CPC=y\nCONFIG_MIPS_CPS=y\nCONFIG_MIPS_CPS_CPUIDLE=y\n# CONFIG_MIPS_CPS_NS16550_BOOL is not set\nCONFIG_MIPS_CPS_PM=y\nCONFIG_MIPS_CPU_SCACHE=y\nCONFIG_MIPS_EBPF_JIT=y\nCONFIG_MIPS_GIC=y\nCONFIG_MIPS_L1_CACHE_SHIFT=5\nCONFIG_MIPS_LD_CAN_LINK_VDSO=y\nCONFIG_MIPS_MT=y\nCONFIG_MIPS_MT_FPAFF=y\nCONFIG_MIPS_MT_SMP=y\n# CONFIG_MIPS_NO_APPENDED_DTB is not set\nCONFIG_MIPS_NR_CPU_NR_MAP=4\nCONFIG_MIPS_PERF_SHARED_TC_COUNTERS=y\nCONFIG_MIPS_RAW_APPENDED_DTB=y\nCONFIG_MIPS_SPRAM=y\nCONFIG_MODULES_USE_ELF_REL=y\nCONFIG_MT7621_WDT=y\n# CONFIG_MTD_CFI_INTELEXT is not set\nCONFIG_MTD_CMDLINE_PARTS=y\nCONFIG_MTD_NAND_CORE=y\nCONFIG_MTD_NAND_ECC=y\nCONFIG_MTD_NAND_ECC_SW_HAMMING=y\nCONFIG_MTD_NAND_MT7621=y\nCONFIG_MTD_NAND_MTK_BMT=y\nCONFIG_MTD_PHYSMAP=y\nCONFIG_MTD_RAW_NAND=y\nCONFIG_MTD_ROUTERBOOT_PARTS=y\nCONFIG_MTD_SPI_NOR=y\nCONFIG_MTD_SPI_NOR_USE_VARIABLE_ERASE=y\nCONFIG_MTD_SPLIT_FIT_FW=y\nCONFIG_MTD_SPLIT_MINOR_FW=y\nCONFIG_MTD_SPLIT_SEAMA_FW=y\nCONFIG_MTD_SPLIT_TPLINK_FW=y\nCONFIG_MTD_SPLIT_TRX_FW=y\nCONFIG_MTD_SPLIT_UIMAGE_FW=y\nCONFIG_MTD_UBI=y\nCONFIG_MTD_UBI_BEB_LIMIT=20\nCONFIG_MTD_UBI_BLOCK=y\nCONFIG_MTD_UBI_WL_THRESHOLD=4096\nCONFIG_MTD_VIRT_CONCAT=y\n# CONFIG_MTK_HSDMA is not set\nCONFIG_NEED_DMA_MAP_STATE=y\nCONFIG_NET_DEVLINK=y\nCONFIG_NET_DSA=y\nCONFIG_NET_DSA_MT7530=y\nCONFIG_NET_DSA_TAG_MTK=y\nCONFIG_NET_FLOW_LIMIT=y\nCONFIG_NET_MEDIATEK_SOC=y\nCONFIG_NET_SELFTESTS=y\nCONFIG_NET_SWITCHDEV=y\nCONFIG_NET_VENDOR_MEDIATEK=y\n# CONFIG_NET_VENDOR_RALINK is not set\nCONFIG_NO_HZ_COMMON=y\nCONFIG_NO_HZ_IDLE=y\nCONFIG_NR_CPUS=4\nCONFIG_NVMEM=y\nCONFIG_OF=y\nCONFIG_OF_ADDRESS=y\nCONFIG_OF_EARLY_FLATTREE=y\nCONFIG_OF_FLATTREE=y\nCONFIG_OF_GPIO=y\nCONFIG_OF_IRQ=y\nCONFIG_OF_KOBJ=y\nCONFIG_OF_MDIO=y\nCONFIG_PADATA=y\nCONFIG_PCI=y\nCONFIG_PCIE_MT7621=y\nCONFIG_PCI_DISABLE_COMMON_QUIRKS=y\nCONFIG_PCI_DOMAINS=y\nCONFIG_PCI_DOMAINS_GENERIC=y\nCONFIG_PCI_DRIVERS_GENERIC=y\nCONFIG_PERF_USE_VMALLOC=y\nCONFIG_PGTABLE_LEVELS=2\nCONFIG_PHYLIB=y\nCONFIG_PHYLINK=y\n# CONFIG_PHY_INGENIC_USB is not set\nCONFIG_PHY_MT7621_PCI=y\n# CONFIG_PHY_PISTACHIO_USB is not set\n# CONFIG_PHY_RALINK_USB is not set\nCONFIG_PINCTRL=y\nCONFIG_PINCTRL_AW9523=y\nCONFIG_PINCTRL_MT7621=y\n# CONFIG_PINCTRL_PISTACHIO is not set\nCONFIG_PINCTRL_RALINK=y\nCONFIG_PINCTRL_RT2880=y\n# CONFIG_PINCTRL_SINGLE is not set\nCONFIG_PINCTRL_SX150X=y\nCONFIG_POWER_RESET=y\nCONFIG_POWER_RESET_GPIO=y\nCONFIG_POWER_SUPPLY=y\nCONFIG_PTP_1588_CLOCK_OPTIONAL=y\nCONFIG_QUEUED_RWLOCKS=y\nCONFIG_QUEUED_SPINLOCKS=y\nCONFIG_RALINK=y\n# CONFIG_RALINK_WDT is not set\nCONFIG_RATIONAL=y\nCONFIG_REGMAP=y\nCONFIG_REGMAP_I2C=y\nCONFIG_REGMAP_MMIO=y\nCONFIG_REGULATOR=y\nCONFIG_REGULATOR_FIXED_VOLTAGE=y\nCONFIG_RESET_CONTROLLER=y\nCONFIG_RFS_ACCEL=y\nCONFIG_RPS=y\nCONFIG_RTC_CLASS=y\nCONFIG_RTC_DRV_BQ32K=y\nCONFIG_RTC_DRV_PCF8563=y\nCONFIG_RTC_I2C_AND_SPI=y\nCONFIG_RTC_MC146818_LIB=y\n# CONFIG_SCHED_CORE is not set\nCONFIG_SCHED_SMT=y\nCONFIG_SERIAL_8250_NR_UARTS=3\nCONFIG_SERIAL_8250_RUNTIME_UARTS=3\nCONFIG_SERIAL_MCTRL_GPIO=y\nCONFIG_SERIAL_OF_PLATFORM=y\nCONFIG_SGL_ALLOC=y\nCONFIG_SMP=y\nCONFIG_SMP_UP=y\nCONFIG_SOCK_RX_QUEUE_MAPPING=y\nCONFIG_SOC_BUS=y\n# CONFIG_SOC_MT7620 is not set\nCONFIG_SOC_MT7621=y\n# CONFIG_SOC_RT288X is not set\n# CONFIG_SOC_RT305X is not set\n# CONFIG_SOC_RT3883 is not set\nCONFIG_SPI=y\nCONFIG_SPI_MASTER=y\nCONFIG_SPI_MEM=y\nCONFIG_SPI_MT7621=y\n# CONFIG_SPI_RT2880 is not set\nCONFIG_SRCU=y\nCONFIG_SWPHY=y\nCONFIG_SYNC_R4K=y\nCONFIG_SYSCTL_EXCEPTION_TRACE=y\nCONFIG_SYS_HAS_CPU_MIPS32_R1=y\nCONFIG_SYS_HAS_CPU_MIPS32_R2=y\nCONFIG_SYS_HAS_EARLY_PRINTK=y\nCONFIG_SYS_SUPPORTS_32BIT_KERNEL=y\nCONFIG_SYS_SUPPORTS_ARBIT_HZ=y\nCONFIG_SYS_SUPPORTS_HIGHMEM=y\nCONFIG_SYS_SUPPORTS_HOTPLUG_CPU=y\nCONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y\nCONFIG_SYS_SUPPORTS_MIPS16=y\nCONFIG_SYS_SUPPORTS_MIPS_CPS=y\nCONFIG_SYS_SUPPORTS_MULTITHREADING=y\nCONFIG_SYS_SUPPORTS_SCHED_SMT=y\nCONFIG_SYS_SUPPORTS_SMP=y\nCONFIG_SYS_SUPPORTS_ZBOOT=y\nCONFIG_TARGET_ISA_REV=2\nCONFIG_TICK_CPU_ACCOUNTING=y\nCONFIG_TIMER_OF=y\nCONFIG_TIMER_PROBE=y\nCONFIG_TREE_RCU=y\nCONFIG_TREE_SRCU=y\nCONFIG_UBIFS_FS=y\nCONFIG_USB_SUPPORT=y\nCONFIG_USE_OF=y\nCONFIG_WATCHDOG_CORE=y\nCONFIG_WEAK_ORDERING=y\nCONFIG_XPS=y\nCONFIG_XXHASH=y\nCONFIG_ZLIB_DEFLATE=y\nCONFIG_ZLIB_INFLATE=y\nCONFIG_ZSTD_COMPRESS=y\nCONFIG_ZSTD_DECOMPRESS=y\n"
  },
  {
    "path": "target/linux/ramips/mt7621/target.mk",
    "content": "#\n# Copyright (C) 2009 OpenWrt.org\n#\n\nSUBTARGET:=mt7621\nBOARDNAME:=MT7621 based boards\nFEATURES+=nand ramdisk rtc usb minor\nCPU_TYPE:=24kc\nKERNELNAME:=vmlinux vmlinuz\n# make Kernel/CopyImage use $LINUX_DIR/vmlinuz\nIMAGES_DIR:=../../..\n\nDEFAULT_PACKAGES += wpad-basic-wolfssl\n\ndefine Target/Description\n\tBuild firmware images for Ralink MT7621 based boards.\nendef\n\n"
  },
  {
    "path": "target/linux/ramips/mt76x8/base-files/etc/board.d/01_leds",
    "content": "\n. /lib/functions/leds.sh\n. /lib/functions/uci-defaults.sh\n\nboard=$(board_name)\n\nboard_config_update\n\ncase $board in\nalfa-network,awusfree1)\n\tucidef_set_led_netdev \"wifi_led\" \"wifi\" \"blue:wlan\" \"wlan0\"\n\t;;\nasus,rt-n10p-v3|\\\nasus,rt-n11p-b1|\\\nasus,rt-n12-vp-b1|\\\nnetgear,r6020|\\\nnetgear,r6080|\\\nnetgear,r6120)\n\tucidef_set_led_switch \"lan\" \"lan\" \"green:lan\" \"switch0\" \"0xf\"\n\tucidef_set_led_switch \"wan\" \"wan\" \"green:wan\" \"switch0\" \"0x10\"\n\t;;\ncudy,wr1000)\n\tucidef_set_led_switch \"wan\" \"wan\" \"blue:wan\" \"switch0\" \"0x10\"\n\tucidef_set_led_switch \"lan1\" \"lan1\" \"blue:lan1\" \"switch0\" \"0x08\"\n\tucidef_set_led_switch \"lan2\" \"lan2\" \"blue:lan2\" \"switch0\" \"0x04\"\n\t;;\ndlink,dap-1325-a1)\n\tucidef_set_rssimon \"wlan0\" \"200000\" \"1\"\n\tucidef_set_led_rssi \"wifi-verylow\" \"wifi-verylow\" \"red:wifi-verylow\" \"wlan0\" \"1\" \"24\"\n\tucidef_set_led_rssi \"wifi-low\" \"wifi-low\" \"green:wifi-low\" \"wlan0\" \"25\" \"100\"\n\tucidef_set_led_rssi \"wifi-med\" \"wifi-med\" \"green:wifi-mid\" \"wlan0\" \"50\" \"100\"\n\tucidef_set_led_rssi \"wifi-high\" \"wifi-high\" \"green:wifi-high\" \"wlan0\" \"75\" \"100\"\n\t;;\nelecom,wrc-1167fs)\n\tucidef_set_led_switch \"lan\" \"lan\" \"green:lan\" \"switch0\" \"0x8\"\n\tucidef_set_led_switch \"internet\" \"internet\" \"green:internet\" \"switch0\" \"0x10\"\n\t;;\nglinet,gl-mt300n-v2)\n\tucidef_set_led_netdev \"wifi_led\" \"wifi\" \"red:wlan\" \"wlan0\"\n\tucidef_set_led_switch \"wan\" \"wan\" \"green:wan\" \"switch0\" \"0x1\"\n\t;;\nhilink,hlk-7628n|\\\nskylab,skw92a)\n\tucidef_set_led_netdev \"wifi_led\" \"wifi\" \"green:wlan\" \"wlan0\"\n\t;;\nhilink,hlk-7688a)\n\tucidef_set_led_wlan \"wlan\" \"WLAN\" \"green:wlan\" \"phy0tpt\"\n\t;;\nhiwifi,hc5661a|\\\nhiwifi,hc5761a)\n\tucidef_set_led_switch \"internet\" \"internet\" \"blue:internet\" \"switch0\" \"0x10\"\n\t;;\nmediatek,linkit-smart-7688)\n\tucidef_set_led_wlan \"wifi\" \"wifi\" \"orange:wifi\" \"phy0tpt\"\n\t;;\nrakwireless,rak633)\n\tucidef_set_led_netdev \"wifi_led\" \"wifi\" \"blue:wifi\" \"wlan0\"\n\t;;\ntama,w06)\n\tucidef_set_led_netdev \"wan\" \"WAN\" \"green:wan\" \"eth0\"\n\tucidef_set_led_wlan \"wlan\" \"WLAN\" \"green:wlan\" \"phy0tpt\"\n\t;;\ntplink,archer-c20-v4|\\\ntplink,archer-c20-v5|\\\ntplink,tl-wr850n-v2)\n\tucidef_set_led_switch \"lan\" \"lan\" \"green:lan\" \"switch0\" \"0x1e\"\n\tucidef_set_led_switch \"wan\" \"wan\" \"green:wan\" \"switch0\" \"0x01\"\n\t;;\ntplink,archer-c50-v3|\\\ntplink,archer-c50-v4)\n\tucidef_set_led_switch \"lan\" \"lan\" \"green:lan\" \"switch0\" \"0x1e\"\n\tucidef_set_led_switch \"wan\" \"wan\" \"green:wan\" \"switch0\" \"0x01\"\n\tucidef_set_led_wlan \"wlan2g\" \"wlan2g\" \"green:wlan2g\" \"phy0tpt\"\n\tucidef_set_led_wlan \"wlan5g\" \"wlan5g\" \"green:wlan5g\" \"phy1tpt\"\n\t;;\ntplink,re200-v2|\\\ntplink,re200-v3|\\\ntplink,re200-v4|\\\ntplink,re220-v2|\\\ntplink,tl-mr3020-v3|\\\ntplink,tl-wa801nd-v5)\n\tucidef_set_led_netdev \"lan\" \"lan\" \"green:lan\" \"eth0\"\n\t;;\ntplink,tl-mr3420-v5|\\\ntplink,tl-wr840n-v4|\\\ntplink,tl-wr842n-v5)\n\tucidef_set_led_wlan \"wlan2g\" \"wlan2g\" \"green:wlan\" \"phy0tpt\"\n\tucidef_set_led_switch \"lan\" \"lan\" \"green:lan\" \"switch0\" \"0x1e\"\n\tucidef_set_led_switch \"wan\" \"wan\" \"green:wan\" \"switch0\" \"0x01\"\n\t;;\ntplink,tl-mr6400-v4)\n\tucidef_set_led_switch \"lan\" \"lan\" \"white:lan\" \"switch0\" \"0x0e\"\n\tucidef_set_led_switch \"wan\" \"wan\" \"white:wan\" \"switch0\" \"0x10\"\n\t;;\ntplink,tl-mr6400-v5)\n\tucidef_set_led_switch \"lan\" \"lan\" \"white:lan\" \"switch0\" \"0x07\"\n\tucidef_set_led_switch \"wan\" \"wan\" \"white:wan\" \"switch0\" \"0x08\"\n\t;;\ntplink,tl-wr841n-v13)\n\tucidef_set_led_wlan \"wlan2g\" \"wlan2g\" \"green:wlan\" \"phy0tpt\"\n\tucidef_set_led_switch \"lan1\" \"lan1\" \"green:lan1\" \"switch0\" \"0x2\"\n\tucidef_set_led_switch \"lan2\" \"lan2\" \"green:lan2\" \"switch0\" \"0x4\"\n\tucidef_set_led_switch \"lan3\" \"lan3\" \"green:lan3\" \"switch0\" \"0x8\"\n\tucidef_set_led_switch \"lan4\" \"lan4\" \"green:lan4\" \"switch0\" \"0x10\"\n\tucidef_set_led_switch \"wan\" \"wan\" \"green:wan\" \"switch0\" \"0x01\"\n\t;;\ntplink,tl-wr841n-v14)\n\tucidef_set_led_switch \"lan\" \"lan\" \"green:lan\" \"switch0\" \"0x1e\"\n\tucidef_set_led_switch \"wan\" \"wan\" \"green:wan\" \"switch0\" \"0x01\"\n\tucidef_set_led_wlan \"wifi_led\" \"wifi\" \"green:wlan\" \"phy0tpt\"\n\t;;\ntplink,tl-wr902ac-v3)\n\tucidef_set_led_wlan \"wlan2g\" \"wlan2g\" \"green:wlan\" \"phy0tpt\"\n\tucidef_set_led_switch \"lan\" \"lan\" \"green:lan\" \"switch0\" \"0x10\"\n\tucidef_set_led_switch \"wan\" \"wan\" \"green:wan\" \"switch0\" \"0x10\"\n\t;;\nunielec,u7628-01-16m)\n\tucidef_set_led_switch \"lan1\" \"lan1\" \"green:lan1\" \"switch0\" \"0x2\"\n\tucidef_set_led_switch \"lan2\" \"lan2\" \"green:lan2\" \"switch0\" \"0x4\"\n\tucidef_set_led_switch \"lan3\" \"lan3\" \"green:lan3\" \"switch0\" \"0x8\"\n\tucidef_set_led_switch \"lan4\" \"lan4\" \"green:lan4\" \"switch0\" \"0x10\"\n\tucidef_set_led_switch \"wan\" \"wan\" \"green:wan\" \"switch0\" \"0x01\"\n\tucidef_set_led_netdev \"wifi_led\" \"wifi\" \"green:wlan\" \"wlan0\"\n\t;;\nwavlink,wl-wn570ha1)\n\tucidef_set_led_switch \"wan\" \"wan\" \"green:wan\" \"switch0\" \"0x01\"\n\tucidef_set_rssimon \"wlan0\" \"200000\" \"1\"\n\tucidef_set_led_rssi \"wifi-low\" \"wifi-low\" \"green:wifi-low\" \"wlan0\" \"1\" \"49\"\n\tucidef_set_led_rssi \"wifi-med\" \"wifi-med\" \"green:wifi-med\" \"wlan0\" \"50\" \"84\"\n\tucidef_set_led_rssi \"wifi-high\" \"wifi-high\" \"green:wifi-high\" \"wlan0\" \"85\" \"100\"\n\tucidef_set_led_netdev \"wifi_led\" \"wifi\" \"green:wifi\" \"wlan0\"\n\t;;\nwavlink,wl-wn575a3)\n\tucidef_set_rssimon \"wlan1\" \"200000\" \"1\"\n\tucidef_set_led_rssi \"wifi-low\" \"wifi-low\" \"green:wifi-low\" \"wlan1\" \"1\" \"49\"\n\tucidef_set_led_rssi \"wifi-med\" \"wifi-med\" \"green:wifi-med\" \"wlan1\" \"50\" \"84\"\n\tucidef_set_led_rssi \"wifi-high\" \"wifi-high\" \"green:wifi-high\" \"wlan1\" \"85\" \"100\"\n\t;;\nwavlink,wl-wn576a2)\n\tucidef_set_led_switch \"lan\" \"lan\" \"blue:lan\" \"switch0\" \"0x10\"\n\t;;\nwavlink,wl-wn577a2|\\\nwavlink,wl-wn578a2)\n\tucidef_set_led_switch \"lan\" \"lan\" \"green:lan\" \"switch0\" \"0x8\"\n\tucidef_set_led_switch \"wan\" \"wan\" \"green:wan\" \"switch0\" \"0x10\"\n\t;;\nzbtlink,zbt-we1226)\n\tucidef_set_led_netdev \"wifi_led\" \"wifi\" \"green:wlan\" \"wlan0\"\n\tucidef_set_led_switch \"lan1\" \"LAN1\" \"green:lan1\" \"switch0\" \"0x01\"\n\tucidef_set_led_switch \"lan2\" \"LAN2\" \"green:lan2\" \"switch0\" \"0x02\"\n\tucidef_set_led_switch \"wan\" \"WAN\" \"green:wan\" \"switch0\" \"0x10\"\n\t;;\nzyxel,keenetic-extra-ii)\n\tucidef_set_led_netdev \"wifi_led\" \"wifi\" \"green:wifi\" \"wlan0\"\n\tucidef_set_led_switch \"internet\" \"internet\" \"green:internet\" \"switch0\" \"0x01\"\n\t;;\nesac\n\nboard_config_flush\n\nexit 0\n"
  },
  {
    "path": "target/linux/ramips/mt76x8/base-files/etc/board.d/02_network",
    "content": "\n. /lib/functions.sh\n. /lib/functions/uci-defaults.sh\n. /lib/functions/system.sh\n\nramips_setup_interfaces()\n{\n\tlocal board=\"$1\"\n\n\tcase $board in\n\talfa-network,awusfree1|\\\n\td-team,pbr-d1|\\\n\tdlink,dap-1325-a1|\\\n\tglinet,microuter-n300|\\\n\tglinet,vixmini|\\\n\thak5,wifi-pineapple-mk7|\\\n\tmediatek,linkit-smart-7688|\\\n\tminew,g1-c|\\\n\tonion,omega2p|\\\n\tonion,omega2|\\\n\travpower,rp-wd009|\\\n\ttama,w06|\\\n\ttplink,re200-v2|\\\n\ttplink,re200-v3|\\\n\ttplink,re200-v4|\\\n\ttplink,re220-v2|\\\n\ttplink,re305-v1|\\\n\ttplink,re305-v3|\\\n\ttplink,tl-wr802n-v4|\\\n\ttplink,tl-wa801nd-v5|\\\n\twidora,neo-16m|\\\n\twidora,neo-32m)\n\t\tucidef_add_switch \"switch0\"\n\t\tucidef_add_switch_attr \"switch0\" \"enable\" \"false\"\n\t\tucidef_set_interface_lan \"eth0\"\n\t\t;;\n\tasus,rt-ac1200|\\\n\tasus,rt-ac1200-v2|\\\n\thilink,hlk-7628n|\\\n\thilink,hlk-7688a|\\\n\thiwifi,hc5861b|\\\n\tskylab,skw92a|\\\n\ttplink,archer-c20-v4|\\\n\ttplink,archer-c20-v5|\\\n\ttplink,archer-c50-v3|\\\n\ttplink,archer-c50-v4|\\\n\ttplink,tl-mr3420-v5|\\\n\ttplink,tl-wr840n-v4|\\\n\ttplink,tl-wr840n-v5|\\\n\ttplink,tl-wr841n-v13|\\\n\ttplink,tl-wr841n-v14|\\\n\ttplink,tl-wr842n-v5|\\\n\ttplink,tl-wr850n-v2|\\\n\tunielec,u7628-01-16m|\\\n\twrtnode,wrtnode2p|\\\n\twrtnode,wrtnode2r|\\\n\tzyxel,keenetic-extra-ii)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"1:lan\" \"2:lan\" \"3:lan\" \"4:lan\" \"0:wan\" \"6@eth0\"\n\t\t;;\n\tasus,rt-n10p-v3|\\\n\tasus,rt-n11p-b1|\\\n\tasus,rt-n12-vp-b1|\\\n\thiwifi,hc5661a|\\\n\tmediatek,mt7628an-eval-board|\\\n\tmercury,mac1200r-v2|\\\n\ttotolink,lr1200|\\\n\twavlink,wl-wn570ha1|\\\n\twavlink,wl-wn575a3)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0:lan\" \"1:lan\" \"2:lan\" \"3:lan\" \"4:wan\" \"6@eth0\"\n\t\t;;\n\tbuffalo,wcr-1166ds|\\\n\telecom,wrc-1167fs|\\\n\twavlink,wl-wn577a2|\\\n\twavlink,wl-wn578a2)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"3:lan\" \"4:wan\" \"6@eth0\"\n\t\t;;\n\tcomfast,cf-wr758ac-v1|\\\n\tcomfast,cf-wr758ac-v2|\\\n\ttplink,tl-wr902ac-v3|\\\n\twavlink,wl-wn576a2)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"4:lan\" \"6@eth0\"\n\t\t;;\n\tcudy,wr1000)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"2:lan:2\" \"3:lan:1\" \"4:wan\" \"6@eth0\"\n\t\t;;\n\tduzun,dm06|\\\n\tglinet,gl-mt300n-v2)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"1:lan\" \"0:wan\" \"6@eth0\"\n\t\t;;\n\thiwifi,hc5761a)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0:lan\" \"1:lan\" \"4:wan\" \"6@eth0\"\n\t\t;;\n\tiptime,a3|\\\n\ttotolink,a3)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"2:lan:2\" \"3:lan:1\" \"0:wan\" \"6@eth0\"\n\t\t;;\n\tiptime,a604m)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"1:lan:4\" \"2:lan:3\" \"3:lan:2\" \"4:lan:1\" \"0:wan\" \"6@eth0\"\n\t\t;;\n\tjotale,js76x8-8m|\\\n\tjotale,js76x8-16m|\\\n\tjotale,js76x8-32m)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0:lan\" \"1:lan\" \"2:lan\" \"6@eth0\"\n\t\t;;\n\tmotorola,mwr03)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"1:lan\" \"2:lan\" \"3:lan\" \"0:wan\" \"6@eth0\"\n\t\t;;\n\tnetgear,r6020|\\\n\tnetgear,r6080|\\\n\tnetgear,r6120|\\\n\twavlink,wl-wn531a3)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0:lan:4\" \"1:lan:3\" \"2:lan:2\" \"3:lan:1\" \"4:wan\" \"6@eth0\"\n\t\t;;\n\trakwireless,rak633)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0:wan\" \"1:lan\" \"2:lan\" \"3:lan\" \"4:lan\" \"6t@eth0\"\n\t\t;;\n\ttplink,tl-mr3020-v3)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0:lan\" \"6@eth0\"\n\t\t;;\n\ttplink,tl-mr6400-v4)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"1:lan\" \"2:lan\" \"3:lan\" \"4:wan\" \"6@eth0\"\n\t\t;;\n\ttplink,tl-mr6400-v5)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0:lan\" \"1:lan\" \"2:lan\" \"3:wan\" \"6@eth0\"\n\t\t;;\n\tvocore,vocore2|\\\n\tvocore,vocore2-lite)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0:lan\" \"2:lan\" \"6t@eth0\"\n\t\t;;\n\twiznet,wizfi630s)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0:wan\" \"3:lan\" \"4:lan\" \"6@eth0\"\n\t\t;;\n\txiaomi,mi-router-4a-100m)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"4:lan:1\" \"2:lan:2\" \"0:wan\" \"6@eth0\"\n\t\t;;\n\txiaomi,mi-router-4c)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"4:lan:1\" \"2:lan:2\" \"1:wan\" \"6@eth0\"\n\t\t;;\n\txiaomi,miwifi-3c)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0:wan\" \"2:lan:2\" \"4:lan:1\" \"6@eth0\"\n\t\t;;\n\txiaomi,miwifi-nano)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0:lan:2\" \"2:lan:1\" \"4:wan\" \"6@eth0\"\n\t\t;;\n\tzbtlink,zbt-we1226)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0:lan:2\" \"1:lan:1\" \"4:wan\" \"6@eth0\"\n\t\t;;\n\tesac\n}\n\nramips_setup_macs()\n{\n\tlocal board=\"$1\"\n\tlocal lan_mac=\"\"\n\tlocal wan_mac=\"\"\n\tlocal label_mac=\"\"\n\n\tcase $board in\n\tasus,rt-ac1200)\n\t\twan_mac=$(mtd_get_mac_binary factory 0x22)\n\t\t;;\n\telecom,wrc-1167fs)\n\t\twan_mac=$(mtd_get_mac_binary factory 0x22)\n\t\tlabel_mac=$wan_mac\n\t\t;;\n\tbuffalo,wcr-1166ds)\n\t\twan_mac=$(mtd_get_mac_ascii board_data \"mac\")\n\t\tlan_mac=$wan_mac\n\t\tlabel_mac=$wan_mac\n\t\t;;\n\tcudy,wr1000|\\\n\thilink,hlk-7628n|\\\n\thilink,hlk-7688a|\\\n\twavlink,wl-wn531a3|\\\n\twavlink,wl-wn577a2|\\\n\twavlink,wl-wn578a2)\n\t\twan_mac=$(mtd_get_mac_binary factory 0x2e)\n\t\tlabel_mac=$(mtd_get_mac_binary factory 0x4)\n\t\t;;\n\tduzun,dm06|\\\n\tnetgear,r6020|\\\n\tnetgear,r6080|\\\n\tnetgear,r6120|\\\n\twrtnode,wrtnode2p|\\\n\twrtnode,wrtnode2r|\\\n\tzyxel,keenetic-extra-ii)\n\t\twan_mac=$(macaddr_add \"$(mtd_get_mac_binary factory 0x4)\" 1)\n\t\t;;\n\thiwifi,hc5661a|\\\n\thiwifi,hc5761a|\\\n\thiwifi,hc5861b)\n\t\tlan_mac=$(mtd_get_mac_ascii bdinfo \"Vfac_mac \")\n\t\tlabel_mac=$lan_mac\n\t\t[ -n \"$lan_mac\" ] || lan_mac=$(cat /sys/class/net/eth0/address)\n\t\twan_mac=$(macaddr_add \"$lan_mac\" 1)\n\t\t;;\n\tiptime,a3|\\\n\tiptime,a604m|\\\n\ttotolink,a3)\n\t\twan_mac=$(mtd_get_mac_binary u-boot 0x1fc40)\n\t\t;;\n\tjotale,js76x8-8m|\\\n\tjotale,js76x8-16m|\\\n\tjotale,js76x8-32m|\\\n\tskylab,skw92a|\\\n\ttotolink,lr1200)\n\t\twan_mac=$(mtd_get_mac_binary factory 0x2e)\n\t\t;;\n\tmercury,mac1200r-v2)\n\t\twan_mac=$(macaddr_add \"$(mtd_get_mac_binary factory_info 0xd)\" 1)\n\t\t;;\n\tmotorola,mwr03)\n\t\tlabel_mac=$(mtd_get_mac_binary factory 0x4)\n\t\twan_mac=$(macaddr_add \"$label_mac\" 2)\n\t\t;;\n\tonion,omega2|\\\n\tonion,omega2p|\\\n\tvocore,vocore2|\\\n\tvocore,vocore2-lite|\\\n\twavlink,wl-wn576a2)\n\t\tlabel_mac=$(mtd_get_mac_binary factory 0x4)\n\t\t;;\n\trakwireless,rak633|\\\n\tunielec,u7628-01-16m|\\\n\twavlink,wl-wn575a3)\n\t\twan_mac=$(macaddr_add \"$(mtd_get_mac_binary factory 0x28)\" 1)\n\t\t;;\n\ttplink,archer-c20-v4|\\\n\ttplink,archer-c50-v3|\\\n\ttplink,tl-mr3420-v5|\\\n\ttplink,tl-wr840n-v4|\\\n\ttplink,tl-wr840n-v5|\\\n\ttplink,tl-wr841n-v13|\\\n\ttplink,tl-wr841n-v14|\\\n\ttplink,tl-wr842n-v5|\\\n\ttplink,tl-wr850n-v2)\n\t\twan_mac=$(macaddr_add \"$(mtd_get_mac_binary factory 0xf100)\" 1)\n\t\t;;\n\ttplink,archer-c20-v5|\\\n\ttplink,archer-c50-v4)\n\t\twan_mac=$(macaddr_add \"$(mtd_get_mac_binary rom 0xf100)\" 1)\n\t\t;;\n\twavlink,wl-wn570ha1|\\\n\tzbtlink,zbt-we1226)\n\t\twan_mac=$(macaddr_add \"$(mtd_get_mac_binary factory 0x2e)\" 1)\n\t\t;;\n\twiznet,wizfi630s)\n\t\tlabel_mac=$(mtd_get_mac_binary factory 0x4)\n\t\twan_mac=$(mtd_get_mac_binary factory 0x28)\n\t\t;;\n\txiaomi,mi-router-4a-100m|\\\n\txiaomi,mi-router-4c)\n\t\twan_mac=$(mtd_get_mac_binary factory 0x4)\n\t\t;;\n\tesac\n\n\t[ -n \"$lan_mac\" ] && ucidef_set_interface_macaddr \"lan\" $lan_mac\n\t[ -n \"$wan_mac\" ] && ucidef_set_interface_macaddr \"wan\" $wan_mac\n\t[ -n \"$label_mac\" ] && ucidef_set_label_macaddr $label_mac\n}\n\nboard_config_update\nboard=$(board_name)\nramips_setup_interfaces $board\nramips_setup_macs $board\nboard_config_flush\n\nexit 0\n"
  },
  {
    "path": "target/linux/ramips/mt76x8/base-files/etc/hotplug.d/ieee80211/10_fix_wifi_mac",
    "content": "[ \"$ACTION\" == \"add\" ] || exit 0\n\nPHYNBR=${DEVPATH##*/phy}\n\n[ -n $PHYNBR ] || exit 0\n\n. /lib/functions.sh\n. /lib/functions/system.sh\n\nboard=$(board_name)\n\ncase \"$board\" in\n\thiwifi,hc5661a|\\\n\thiwifi,hc5761a|\\\n\thiwifi,hc5861b)\n\t\tlabel_mac=$(mtd_get_mac_ascii bdinfo \"Vfac_mac \")\n\t\t[ \"$PHYNBR\" = \"0\" ] && [ -n \"$label_mac\" ] && \\\n\t\techo -n \"$label_mac\" > /sys${DEVPATH}/macaddress\n\t\t[ \"$PHYNBR\" = \"1\" ] && [ -n \"$label_mac\" ] && \\\n\t\tmacaddr_unsetbit \"$label_mac\" 6 > /sys${DEVPATH}/macaddress\n\t\t;;\nesac\n"
  },
  {
    "path": "target/linux/ramips/mt76x8/base-files/etc/init.d/bootcount",
    "content": "#!/bin/sh /etc/rc.common\n\nSTART=99\n\nboot() {\n\tcase $(board_name) in\n\talfa-network,awusfree1)\n\t\t[ -n \"$(fw_printenv bootcount bootchanged 2>/dev/null)\" ] &&\\\n\t\t\techo -e \"bootcount\\nbootchanged\\n\" | /usr/sbin/fw_setenv -s -\n\t\t;;\n\txiaomi,mi-router-4c|\\\n\txiaomi,miwifi-nano)\n\t\tfw_setenv flag_boot_success 1\n\t\t;;\n\tesac\n}\n"
  },
  {
    "path": "target/linux/ramips/mt76x8/base-files/lib/upgrade/platform.sh",
    "content": "#\n# Copyright (C) 2010 OpenWrt.org\n#\n\nPART_NAME=firmware\nREQUIRE_IMAGE_METADATA=1\n\nRAMFS_COPY_BIN='fw_printenv fw_setenv'\nRAMFS_COPY_DATA='/etc/fw_env.config /var/lock/fw_printenv.lock'\n\nplatform_check_image() {\n\treturn 0\n}\n\nplatform_do_upgrade() {\n\tlocal board=$(board_name)\n\n\tcase \"$board\" in\n\talfa-network,awusfree1)\n\t\t[ \"$(fw_printenv -n dual_image 2>/dev/null)\" = \"1\" ] &&\\\n\t\t[ -n \"$(find_mtd_part backup)\" ] && {\n\t\t\tPART_NAME=backup\n\t\t\tif [ \"$(fw_printenv -n bootactive 2>/dev/null)\" = \"1\" ]; then\n\t\t\t\tfw_setenv bootactive 2 || exit 1\n\t\t\telse\n\t\t\t\tfw_setenv bootactive 1 || exit 1\n\t\t\tfi\n\t\t}\n\t\tdefault_do_upgrade \"$1\"\n\t\t;;\n\ttplink,archer-c20-v5|\\\n\ttplink,archer-c50-v4)\n\t\tMTD_ARGS=\"-t romfile\"\n\t\tdefault_do_upgrade \"$1\"\n\t\t;;\n\t*)\n\t\tdefault_do_upgrade \"$1\"\n\t\t;;\n\tesac\n}\n"
  },
  {
    "path": "target/linux/ramips/mt76x8/config-5.10",
    "content": "CONFIG_ARCH_32BIT_OFF_T=y\nCONFIG_ARCH_HIBERNATION_POSSIBLE=y\nCONFIG_ARCH_MMAP_RND_BITS_MAX=15\nCONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15\nCONFIG_ARCH_SUSPEND_POSSIBLE=y\nCONFIG_AT803X_PHY=y\nCONFIG_BLK_MQ_PCI=y\nCONFIG_CEVT_R4K=y\nCONFIG_CEVT_SYSTICK_QUIRK=y\nCONFIG_CLKDEV_LOOKUP=y\nCONFIG_CLKEVT_RT3352=y\nCONFIG_CLKSRC_MMIO=y\nCONFIG_CLONE_BACKWARDS=y\nCONFIG_CMDLINE=\"rootfstype=squashfs,jffs2\"\nCONFIG_CMDLINE_BOOL=y\n# CONFIG_CMDLINE_OVERRIDE is not set\nCONFIG_COMPAT_32BIT_TIME=y\nCONFIG_CPU_GENERIC_DUMP_TLB=y\nCONFIG_CPU_HAS_DIEI=y\nCONFIG_CPU_HAS_PREFETCH=y\nCONFIG_CPU_HAS_RIXI=y\nCONFIG_CPU_HAS_SYNC=y\nCONFIG_CPU_MIPS32=y\n# CONFIG_CPU_MIPS32_R1 is not set\nCONFIG_CPU_MIPS32_R2=y\nCONFIG_CPU_MIPSR2=y\nCONFIG_CPU_MIPSR2_IRQ_VI=y\nCONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y\nCONFIG_CPU_R4K_CACHE_TLB=y\nCONFIG_CPU_SUPPORTS_32BIT_KERNEL=y\nCONFIG_CPU_SUPPORTS_HIGHMEM=y\nCONFIG_CPU_SUPPORTS_MSA=y\nCONFIG_CRYPTO_LIB_POLY1305_RSIZE=2\nCONFIG_CRYPTO_RNG2=y\nCONFIG_CSRC_R4K=y\nCONFIG_DEBUG_PINCTRL=y\nCONFIG_DMA_NONCOHERENT=y\n# CONFIG_DTB_MT7620A_EVAL is not set\n# CONFIG_DTB_OMEGA2P is not set\nCONFIG_DTB_RT_NONE=y\n# CONFIG_DTB_VOCORE2 is not set\nCONFIG_DTC=y\nCONFIG_EARLY_PRINTK=y\nCONFIG_FIXED_PHY=y\nCONFIG_FW_LOADER_PAGED_BUF=y\nCONFIG_GENERIC_ATOMIC64=y\nCONFIG_GENERIC_CLOCKEVENTS=y\nCONFIG_GENERIC_CMOS_UPDATE=y\nCONFIG_GENERIC_CPU_AUTOPROBE=y\nCONFIG_GENERIC_GETTIMEOFDAY=y\nCONFIG_GENERIC_IOMAP=y\nCONFIG_GENERIC_IRQ_CHIP=y\nCONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y\nCONFIG_GENERIC_IRQ_SHOW=y\nCONFIG_GENERIC_LIB_ASHLDI3=y\nCONFIG_GENERIC_LIB_ASHRDI3=y\nCONFIG_GENERIC_LIB_CMPDI2=y\nCONFIG_GENERIC_LIB_LSHRDI3=y\nCONFIG_GENERIC_LIB_UCMPDI2=y\nCONFIG_GENERIC_PCI_IOMAP=y\nCONFIG_GENERIC_PHY=y\nCONFIG_GENERIC_PINCONF=y\nCONFIG_GENERIC_SCHED_CLOCK=y\nCONFIG_GENERIC_SMP_IDLE_THREAD=y\nCONFIG_GENERIC_TIME_VSYSCALL=y\nCONFIG_GPIOLIB=y\nCONFIG_GPIOLIB_IRQCHIP=y\nCONFIG_GPIO_GENERIC=y\nCONFIG_GPIO_MT7621=y\n# CONFIG_GPIO_RALINK is not set\nCONFIG_HANDLE_DOMAIN_IRQ=y\nCONFIG_HARDWARE_WATCHPOINTS=y\nCONFIG_HAS_DMA=y\nCONFIG_HAS_IOMEM=y\nCONFIG_HAS_IOPORT_MAP=y\nCONFIG_HZ_PERIODIC=y\nCONFIG_ICPLUS_PHY=y\nCONFIG_INITRAMFS_SOURCE=\"\"\nCONFIG_IRQCHIP=y\nCONFIG_IRQ_DOMAIN=y\nCONFIG_IRQ_FORCED_THREADING=y\nCONFIG_IRQ_INTC=y\nCONFIG_IRQ_MIPS_CPU=y\nCONFIG_IRQ_WORK=y\n# CONFIG_KERNEL_ZSTD is not set\nCONFIG_LIBFDT=y\nCONFIG_LOCK_DEBUGGING_SUPPORT=y\nCONFIG_MDIO_BUS=y\nCONFIG_MDIO_DEVICE=y\nCONFIG_MEMFD_CREATE=y\nCONFIG_MFD_SYSCON=y\nCONFIG_MIGRATION=y\nCONFIG_MIPS=y\nCONFIG_MIPS_ASID_BITS=8\nCONFIG_MIPS_ASID_SHIFT=0\nCONFIG_MIPS_CBPF_JIT=y\nCONFIG_MIPS_CLOCK_VSYSCALL=y\n# CONFIG_MIPS_CMDLINE_BUILTIN_EXTEND is not set\n# CONFIG_MIPS_CMDLINE_DTB_EXTEND is not set\n# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set\nCONFIG_MIPS_CMDLINE_FROM_DTB=y\n# CONFIG_MIPS_ELF_APPENDED_DTB is not set\nCONFIG_MIPS_L1_CACHE_SHIFT=5\nCONFIG_MIPS_LD_CAN_LINK_VDSO=y\n# CONFIG_MIPS_NO_APPENDED_DTB is not set\nCONFIG_MIPS_RAW_APPENDED_DTB=y\nCONFIG_MIPS_SPRAM=y\nCONFIG_MODULES_USE_ELF_REL=y\nCONFIG_MT7621_WDT=y\n# CONFIG_MTD_CFI_INTELEXT is not set\nCONFIG_MTD_CMDLINE_PARTS=y\nCONFIG_MTD_PARSER_TRX=y\nCONFIG_MTD_PHYSMAP=y\nCONFIG_MTD_SPI_NOR=y\nCONFIG_MTD_SPLIT_TPLINK_FW=y\nCONFIG_MTD_SPLIT_UIMAGE_FW=y\nCONFIG_NEED_DMA_MAP_STATE=y\nCONFIG_NEED_PER_CPU_KM=y\nCONFIG_NET_RALINK_ESW_RT3050=y\n# CONFIG_NET_RALINK_MT7620 is not set\nCONFIG_NET_RALINK_RT3050=y\nCONFIG_NET_RALINK_SOC=y\n# CONFIG_NET_VENDOR_MEDIATEK is not set\nCONFIG_NET_VENDOR_RALINK=y\nCONFIG_NO_GENERIC_PCI_IOPORT_MAP=y\nCONFIG_NVMEM=y\nCONFIG_OF=y\nCONFIG_OF_ADDRESS=y\nCONFIG_OF_EARLY_FLATTREE=y\nCONFIG_OF_FLATTREE=y\nCONFIG_OF_GPIO=y\nCONFIG_OF_IRQ=y\nCONFIG_OF_KOBJ=y\nCONFIG_OF_MDIO=y\nCONFIG_OF_NET=y\nCONFIG_PCI=y\nCONFIG_PCI_DOMAINS=y\nCONFIG_PCI_DRIVERS_LEGACY=y\n# CONFIG_PCI_MT7621 is not set\n# CONFIG_PCI_MT7621_PHY is not set\nCONFIG_PERF_USE_VMALLOC=y\nCONFIG_PGTABLE_LEVELS=2\nCONFIG_PHYLIB=y\nCONFIG_PHY_RALINK_USB=y\nCONFIG_PINCTRL=y\n# CONFIG_PINCTRL_AW9523 is not set\nCONFIG_PINCTRL_RT2880=y\n# CONFIG_PINCTRL_SINGLE is not set\n# CONFIG_PWM_MEDIATEK is not set\nCONFIG_RALINK=y\n# CONFIG_RALINK_WDT is not set\nCONFIG_REGMAP=y\nCONFIG_REGMAP_MMIO=y\nCONFIG_REGULATOR=y\nCONFIG_REGULATOR_FIXED_VOLTAGE=y\nCONFIG_RESET_CONTROLLER=y\nCONFIG_SERIAL_8250_NR_UARTS=3\nCONFIG_SERIAL_8250_RUNTIME_UARTS=3\nCONFIG_SERIAL_MCTRL_GPIO=y\nCONFIG_SERIAL_OF_PLATFORM=y\nCONFIG_SOC_MT7620=y\n# CONFIG_SOC_MT7621 is not set\n# CONFIG_SOC_RT288X is not set\n# CONFIG_SOC_RT305X is not set\n# CONFIG_SOC_RT3883 is not set\nCONFIG_SPI=y\nCONFIG_SPI_MASTER=y\nCONFIG_SPI_MEM=y\nCONFIG_SPI_MT7621=y\n# CONFIG_SPI_RT2880 is not set\nCONFIG_SRCU=y\nCONFIG_SWCONFIG=y\nCONFIG_SWCONFIG_LEDS=y\nCONFIG_SWPHY=y\nCONFIG_SYSCTL_EXCEPTION_TRACE=y\nCONFIG_SYS_HAS_CPU_MIPS32_R1=y\nCONFIG_SYS_HAS_CPU_MIPS32_R2=y\nCONFIG_SYS_HAS_EARLY_PRINTK=y\nCONFIG_SYS_SUPPORTS_32BIT_KERNEL=y\nCONFIG_SYS_SUPPORTS_ARBIT_HZ=y\nCONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y\nCONFIG_SYS_SUPPORTS_MIPS16=y\nCONFIG_SYS_SUPPORTS_ZBOOT=y\nCONFIG_TARGET_ISA_REV=2\nCONFIG_TICK_CPU_ACCOUNTING=y\nCONFIG_TIMER_OF=y\nCONFIG_TIMER_PROBE=y\nCONFIG_TINY_SRCU=y\nCONFIG_USB_SUPPORT=y\nCONFIG_USE_OF=y\nCONFIG_WATCHDOG_CORE=y\n"
  },
  {
    "path": "target/linux/ramips/mt76x8/target.mk",
    "content": "#\n# Copyright (C) 2009 OpenWrt.org\n#\n\nSUBTARGET:=mt76x8\nBOARDNAME:=MT76x8 based boards\nFEATURES+=usb ramdisk\nCPU_TYPE:=24kc\n\nDEFAULT_PACKAGES += kmod-mt7603 wpad-basic-wolfssl swconfig\n\ndefine Target/Description\n\tBuild firmware images for Ralink MT76x8 based boards.\nendef\n\n"
  },
  {
    "path": "target/linux/ramips/patches-5.10/020-mips-ralink-manage-low-reset-lines.patch",
    "content": "From 3f9ef7785a9cd69cb75f5e2ea4ca79a24752e496 Mon Sep 17 00:00:00 2001\nFrom: Sander Vanheule <sander@svanheule.net>\nDate: Wed, 3 Feb 2021 10:21:41 +0100\nSubject: MIPS: ralink: manage low reset lines\n\nReset lines with indices smaller than 8 are currently considered invalid\nby the rt2880-reset reset controller.\n\nThe MT7621 SoC uses a number of these low reset lines. The DTS defines\nreset lines \"hsdma\", \"fe\", and \"mcm\" with respective values 5, 6, and 2.\nAs a result of the above restriction, these resets cannot be asserted or\nde-asserted by the reset controller. In cases where the bootloader does\nnot de-assert these lines, this results in e.g. the MT7621's internal\nswitch staying in reset.\n\nChange the reset controller to only ignore the system reset, so all\nreset lines with index greater than 0 are considered valid.\n\nSigned-off-by: Sander Vanheule <sander@svanheule.net>\nAcked-by: John Crispin <john@phrozen.org>\nSigned-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>\n---\n arch/mips/ralink/reset.c | 4 ++--\n 1 file changed, 2 insertions(+), 2 deletions(-)\n\n--- a/arch/mips/ralink/reset.c\n+++ b/arch/mips/ralink/reset.c\n@@ -27,7 +27,7 @@ static int ralink_assert_device(struct r\n {\n \tu32 val;\n \n-\tif (id < 8)\n+\tif (id == 0)\n \t\treturn -1;\n \n \tval = rt_sysc_r32(SYSC_REG_RESET_CTRL);\n@@ -42,7 +42,7 @@ static int ralink_deassert_device(struct\n {\n \tu32 val;\n \n-\tif (id < 8)\n+\tif (id == 0)\n \t\treturn -1;\n \n \tval = rt_sysc_r32(SYSC_REG_RESET_CTRL);\n"
  },
  {
    "path": "target/linux/ramips/patches-5.10/200-add-ralink-eth.patch",
    "content": "--- a/drivers/net/ethernet/Kconfig\n+++ b/drivers/net/ethernet/Kconfig\n@@ -159,6 +159,7 @@ source \"drivers/net/ethernet/pasemi/Kcon\n source \"drivers/net/ethernet/pensando/Kconfig\"\n source \"drivers/net/ethernet/qlogic/Kconfig\"\n source \"drivers/net/ethernet/qualcomm/Kconfig\"\n+source \"drivers/net/ethernet/ralink/Kconfig\"\n source \"drivers/net/ethernet/rdc/Kconfig\"\n source \"drivers/net/ethernet/realtek/Kconfig\"\n source \"drivers/net/ethernet/renesas/Kconfig\"\n--- a/drivers/net/ethernet/Makefile\n+++ b/drivers/net/ethernet/Makefile\n@@ -71,6 +71,7 @@ obj-$(CONFIG_NET_VENDOR_PACKET_ENGINES)\n obj-$(CONFIG_NET_VENDOR_PASEMI) += pasemi/\n obj-$(CONFIG_NET_VENDOR_QLOGIC) += qlogic/\n obj-$(CONFIG_NET_VENDOR_QUALCOMM) += qualcomm/\n+obj-$(CONFIG_NET_VENDOR_RALINK) += ralink/\n obj-$(CONFIG_NET_VENDOR_REALTEK) += realtek/\n obj-$(CONFIG_NET_VENDOR_RENESAS) += renesas/\n obj-$(CONFIG_NET_VENDOR_RDC) += rdc/\n"
  },
  {
    "path": "target/linux/ramips/patches-5.10/201-MIPS-ralink-rt288x-select-MIPS_AUTO_PFN_OFFSET.patch",
    "content": "From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001\nFrom: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com>\nDate: Sat, 3 Apr 2021 18:51:44 -0700\nSubject: [PATCH] MIPS: ralink: rt288x: select MIPS_AUTO_PFN_OFFSET\n\nRT288X systems may have a non-zero ramstart causing problems with memory\nreservations and boot hangs, as well as messages like:\n  Wasting 1048576 bytes for tracking 32768 unused pages\n\nBoth are alleviated by selecting MIPS_AUTO_PFN_OFFSET for such\nplatforms.\n\nTested on a Belkin F5D8235 v1 RT2880 device.\n\nLink: https://lore.kernel.org/linux-mips/20180820233111.xww5232dxbuouf4n@pburton-laptop/\n\nSigned-off-by: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com>\nCc: Mike Rapoport <rppt@kernel.org>\n---\n arch/mips/ralink/Kconfig | 1 +\n 1 file changed, 1 insertion(+)\n\n--- a/arch/mips/ralink/Kconfig\n+++ b/arch/mips/ralink/Kconfig\n@@ -26,6 +26,7 @@ choice\n \n \tconfig SOC_RT288X\n \t\tbool \"RT288x\"\n+\t\tselect MIPS_AUTO_PFN_OFFSET\n \t\tselect MIPS_L1_CACHE_SHIFT_4\n \t\tselect HAVE_LEGACY_CLK\n \t\tselect HAVE_PCI\n"
  },
  {
    "path": "target/linux/ramips/patches-5.10/203-staging-mt7621-pci-phy-kconfig-select-regmap-mmio.patch",
    "content": "--- a/drivers/staging/mt7621-pci-phy/Kconfig\n+++ b/drivers/staging/mt7621-pci-phy/Kconfig\n@@ -3,6 +3,7 @@ config PCI_MT7621_PHY\n \ttristate \"MediaTek MT7621 PCI PHY Driver\"\n \tdepends on RALINK && OF\n \tselect GENERIC_PHY\n+\tselect REGMAP_MMIO\n \thelp\n \t  Say 'Y' here to add support for MediaTek MT7621 PCI PHY driver,\n \n"
  },
  {
    "path": "target/linux/ramips/patches-5.10/300-mt7620-export-chip-version-and-pkg.patch",
    "content": "--- a/arch/mips/include/asm/mach-ralink/mt7620.h\n+++ b/arch/mips/include/asm/mach-ralink/mt7620.h\n@@ -135,4 +135,16 @@ static inline int mt7620_get_eco(void)\n \treturn rt_sysc_r32(SYSC_REG_CHIP_REV) & CHIP_REV_ECO_MASK;\n }\n \n+static inline int mt7620_get_chipver(void)\n+{\n+\treturn (rt_sysc_r32(SYSC_REG_CHIP_REV) >> CHIP_REV_VER_SHIFT) &\n+\t\tCHIP_REV_VER_MASK;\n+}\n+\n+static inline int mt7620_get_pkg(void)\n+{\n+\treturn (rt_sysc_r32(SYSC_REG_CHIP_REV) >> CHIP_REV_PKG_SHIFT) &\n+\t\tCHIP_REV_PKG_MASK;\n+}\n+\n #endif\n"
  },
  {
    "path": "target/linux/ramips/patches-5.10/311-MIPS-use-set_mode-to-enable-disable-the-cevt-r4k-irq.patch",
    "content": "From ce3d4a4111a5f7e6b4e74bceae5faa6ce388e8ec Mon Sep 17 00:00:00 2001\nFrom: John Crispin <blogic@openwrt.org>\nDate: Sun, 14 Jul 2013 23:08:11 +0200\nSubject: [PATCH 05/53] MIPS: use set_mode() to enable/disable the cevt-r4k\n irq\n\nSigned-off-by: John Crispin <blogic@openwrt.org>\n---\n arch/mips/ralink/Kconfig |    5 +++++\n 1 file changed, 5 insertions(+)\n\n--- a/arch/mips/ralink/Kconfig\n+++ b/arch/mips/ralink/Kconfig\n@@ -1,12 +1,17 @@\n # SPDX-License-Identifier: GPL-2.0\n if RALINK\n \n+config CEVT_SYSTICK_QUIRK\n+\tbool\n+\tdefault n\n+\n config CLKEVT_RT3352\n \tbool\n \tdepends on SOC_RT305X || SOC_MT7620\n \tdefault y\n \tselect TIMER_OF\n \tselect CLKSRC_MMIO\n+\tselect CEVT_SYSTICK_QUIRK\n \n config RALINK_ILL_ACC\n \tbool\n--- a/arch/mips/kernel/cevt-r4k.c\n+++ b/arch/mips/kernel/cevt-r4k.c\n@@ -16,6 +16,31 @@\n #include <asm/time.h>\n #include <asm/cevt-r4k.h>\n \n+#ifdef CONFIG_CEVT_SYSTICK_QUIRK\n+static int mips_state_oneshot(struct clock_event_device *evt)\n+{\n+\tunsigned long flags = IRQF_PERCPU | IRQF_TIMER | IRQF_SHARED;\n+\tif (!cp0_timer_irq_installed) {\n+\t\tcp0_timer_irq_installed = 1;\n+\t\tif (request_irq(evt->irq, c0_compare_interrupt, flags, \"timer\",\n+\t\t\t\t\tc0_compare_interrupt))\n+\t\t\tpr_err(\"Failed to request irq %d (timer)\\n\", evt->irq);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int mips_state_shutdown(struct clock_event_device *evt)\n+{\n+\tif (cp0_timer_irq_installed) {\n+\t\tcp0_timer_irq_installed = 0;\n+\t\tfree_irq(evt->irq, NULL);\n+\t}\n+\n+\treturn 0;\n+}\n+#endif\n+\n static int mips_next_event(unsigned long delta,\n \t\t\t   struct clock_event_device *evt)\n {\n@@ -296,7 +321,9 @@ core_initcall(r4k_register_cpufreq_notif\n \n int r4k_clockevent_init(void)\n {\n+#ifndef CONFIG_CEVT_SYSTICK_QUIRK\n \tunsigned long flags = IRQF_PERCPU | IRQF_TIMER | IRQF_SHARED;\n+#endif\n \tunsigned int cpu = smp_processor_id();\n \tstruct clock_event_device *cd;\n \tunsigned int irq, min_delta;\n@@ -326,11 +353,16 @@ int r4k_clockevent_init(void)\n \tcd->rating\t\t= 300;\n \tcd->irq\t\t\t= irq;\n \tcd->cpumask\t\t= cpumask_of(cpu);\n+#ifdef CONFIG_CEVT_SYSTICK_QUIRK\n+\tcd->set_state_shutdown\t= mips_state_shutdown;\n+\tcd->set_state_oneshot\t= mips_state_oneshot;\n+#endif\n \tcd->set_next_event\t= mips_next_event;\n \tcd->event_handler\t= mips_event_handler;\n \n \tclockevents_config_and_register(cd, mips_hpt_frequency, min_delta, 0x7fffffff);\n \n+#ifndef CONFIG_CEVT_SYSTICK_QUIRK\n \tif (cp0_timer_irq_installed)\n \t\treturn 0;\n \n@@ -339,6 +371,7 @@ int r4k_clockevent_init(void)\n \tif (request_irq(irq, c0_compare_interrupt, flags, \"timer\",\n \t\t\tc0_compare_interrupt))\n \t\tpr_err(\"Failed to request irq %d (timer)\\n\", irq);\n+#endif\n \n \treturn 0;\n }\n"
  },
  {
    "path": "target/linux/ramips/patches-5.10/312-MIPS-ralink-add-cpu-frequency-scaling.patch",
    "content": "From bd30f19a006fb52bac80c6463c49dd2f4159f4ac Mon Sep 17 00:00:00 2001\nFrom: John Crispin <blogic@openwrt.org>\nDate: Sun, 28 Jul 2013 16:26:41 +0200\nSubject: [PATCH 06/53] MIPS: ralink: add cpu frequency scaling\n\nThis feature will break udelay() and cause the delay loop to have longer delays\nwhen the frequency is scaled causing a performance hit.\n\nSigned-off-by: John Crispin <blogic@openwrt.org>\n---\n arch/mips/ralink/cevt-rt3352.c |   38 ++++++++++++++++++++++++++++++++++++++\n 1 file changed, 38 insertions(+)\n\n--- a/arch/mips/ralink/cevt-rt3352.c\n+++ b/arch/mips/ralink/cevt-rt3352.c\n@@ -29,6 +29,10 @@\n /* enable the counter */\n #define CFG_CNT_EN\t\t0x1\n \n+/* mt7620 frequency scaling defines */\n+#define CLK_LUT_CFG\t0x40\n+#define SLEEP_EN\tBIT(31)\n+\n struct systick_device {\n \tvoid __iomem *membase;\n \tstruct clock_event_device dev;\n@@ -36,21 +40,53 @@ struct systick_device {\n \tint freq_scale;\n };\n \n+static void (*systick_freq_scaling)(struct systick_device *sdev, int status);\n+\n static int systick_set_oneshot(struct clock_event_device *evt);\n static int systick_shutdown(struct clock_event_device *evt);\n \n+static inline void mt7620_freq_scaling(struct systick_device *sdev, int status)\n+{\n+\tif (sdev->freq_scale == status)\n+\t\treturn;\n+\n+\tsdev->freq_scale = status;\n+\n+\tpr_info(\"%s: %s autosleep mode\\n\", sdev->dev.name,\n+\t\t\t(status) ? (\"enable\") : (\"disable\"));\n+\tif (status)\n+\t\trt_sysc_w32(rt_sysc_r32(CLK_LUT_CFG) | SLEEP_EN, CLK_LUT_CFG);\n+\telse\n+\t\trt_sysc_w32(rt_sysc_r32(CLK_LUT_CFG) & ~SLEEP_EN, CLK_LUT_CFG);\n+}\n+\n+static inline unsigned int read_count(struct systick_device *sdev)\n+{\n+\treturn ioread32(sdev->membase + SYSTICK_COUNT);\n+}\n+\n+static inline unsigned int read_compare(struct systick_device *sdev)\n+{\n+\treturn ioread32(sdev->membase + SYSTICK_COMPARE);\n+}\n+\n+static inline void write_compare(struct systick_device *sdev, unsigned int val)\n+{\n+\tiowrite32(val, sdev->membase + SYSTICK_COMPARE);\n+}\n+\n static int systick_next_event(unsigned long delta,\n \t\t\t\tstruct clock_event_device *evt)\n {\n \tstruct systick_device *sdev;\n-\tu32 count;\n+\tint res;\n \n \tsdev = container_of(evt, struct systick_device, dev);\n-\tcount = ioread32(sdev->membase + SYSTICK_COUNT);\n-\tcount = (count + delta) % SYSTICK_FREQ;\n-\tiowrite32(count, sdev->membase + SYSTICK_COMPARE);\n+\tdelta += read_count(sdev);\n+\twrite_compare(sdev, delta);\n+\tres = ((int)(read_count(sdev) - delta) >= 0) ? -ETIME : 0;\n \n-\treturn 0;\n+\treturn res;\n }\n \n static void systick_event_handler(struct clock_event_device *dev)\n@@ -60,20 +96,25 @@ static void systick_event_handler(struct\n \n static irqreturn_t systick_interrupt(int irq, void *dev_id)\n {\n-\tstruct clock_event_device *dev = (struct clock_event_device *) dev_id;\n+\tint ret = 0;\n+\tstruct clock_event_device *cdev;\n+\tstruct systick_device *sdev;\n \n-\tdev->event_handler(dev);\n+\tif (read_c0_cause() & STATUSF_IP7) {\n+\t\tcdev = (struct clock_event_device *) dev_id;\n+\t\tsdev = container_of(cdev, struct systick_device, dev);\n+\n+\t\t/* Clear Count/Compare Interrupt */\n+\t\twrite_compare(sdev, read_compare(sdev));\n+\t\tcdev->event_handler(cdev);\n+\t\tret = 1;\n+\t}\n \n-\treturn IRQ_HANDLED;\n+\treturn IRQ_RETVAL(ret);\n }\n \n static struct systick_device systick = {\n \t.dev = {\n-\t\t/*\n-\t\t * cevt-r4k uses 300, make sure systick\n-\t\t * gets used if available\n-\t\t */\n-\t\t.rating\t\t\t= 310,\n \t\t.features\t\t= CLOCK_EVT_FEAT_ONESHOT,\n \t\t.set_next_event\t\t= systick_next_event,\n \t\t.set_state_shutdown\t= systick_shutdown,\n@@ -91,7 +132,13 @@ static int systick_shutdown(struct clock\n \tif (sdev->irq_requested)\n \t\tfree_irq(systick.dev.irq, &systick.dev);\n \tsdev->irq_requested = 0;\n-\tiowrite32(0, systick.membase + SYSTICK_CONFIG);\n+\tiowrite32(CFG_CNT_EN, systick.membase + SYSTICK_CONFIG);\n+\n+\tif (systick_freq_scaling)\n+\t\tsystick_freq_scaling(sdev, 0);\n+\n+\tif (systick_freq_scaling)\n+\t\tsystick_freq_scaling(sdev, 1);\n \n \treturn 0;\n }\n@@ -116,33 +163,46 @@ static int systick_set_oneshot(struct cl\n \treturn 0;\n }\n \n+static const struct of_device_id systick_match[] = {\n+\t{ .compatible = \"ralink,mt7620a-systick\", .data = mt7620_freq_scaling},\n+\t{},\n+};\n+\n static int __init ralink_systick_init(struct device_node *np)\n {\n-\tint ret;\n+\tconst struct of_device_id *match;\n+\tint rating = 200;\n \n \tsystick.membase = of_iomap(np, 0);\n \tif (!systick.membase)\n \t\treturn -ENXIO;\n \n-\tsystick.dev.name = np->name;\n-\tclockevents_calc_mult_shift(&systick.dev, SYSTICK_FREQ, 60);\n-\tsystick.dev.max_delta_ns = clockevent_delta2ns(0x7fff, &systick.dev);\n-\tsystick.dev.max_delta_ticks = 0x7fff;\n-\tsystick.dev.min_delta_ns = clockevent_delta2ns(0x3, &systick.dev);\n-\tsystick.dev.min_delta_ticks = 0x3;\n+\tmatch = of_match_node(systick_match, np);\n+\tif (match) {\n+\t\tsystick_freq_scaling = match->data;\n+\t\t/*\n+\t\t * cevt-r4k uses 300, make sure systick\n+\t\t * gets used if available\n+\t\t */\n+\t\trating = 310;\n+\t}\n+\n+\t/* enable counter than register clock source */\n+\tiowrite32(CFG_CNT_EN, systick.membase + SYSTICK_CONFIG);\n+\tclocksource_mmio_init(systick.membase + SYSTICK_COUNT, np->name,\n+\t\t\tSYSTICK_FREQ, rating, 16, clocksource_mmio_readl_up);\n+\n+\t/* register clock event */\n \tsystick.dev.irq = irq_of_parse_and_map(np, 0);\n \tif (!systick.dev.irq) {\n \t\tpr_err(\"%pOFn: request_irq failed\", np);\n \t\treturn -EINVAL;\n \t}\n \n-\tret = clocksource_mmio_init(systick.membase + SYSTICK_COUNT, np->name,\n-\t\t\t\t    SYSTICK_FREQ, 301, 16,\n-\t\t\t\t    clocksource_mmio_readl_up);\n-\tif (ret)\n-\t\treturn ret;\n-\n-\tclockevents_register_device(&systick.dev);\n+\tsystick.dev.name = np->name;\n+\tsystick.dev.rating = rating;\n+\tsystick.dev.cpumask = cpumask_of(0);\n+\tclockevents_config_and_register(&systick.dev, SYSTICK_FREQ, 0x3, 0x7fff);\n \n \tpr_info(\"%pOFn: running - mult: %d, shift: %d\\n\",\n \t\t\tnp, systick.dev.mult, systick.dev.shift);\n"
  },
  {
    "path": "target/linux/ramips/patches-5.10/314-MIPS-add-bootargs-override-property.patch",
    "content": "From f15d27f9c90ede4b16eb37f9ae573ef81c2b6996 Mon Sep 17 00:00:00 2001\nFrom: David Bauer <mail@david-bauer.net>\nDate: Thu, 31 Dec 2020 18:49:12 +0100\nSubject: [PATCH] MIPS: add bootargs-override property\n\nAdd support for the bootargs-override property to the chosen node\nsimilar to the one used on ipq806x or mpc85xx.\n\nThis is necessary, as the U-Boot used on some boards, notably the\nUbiquiti UniFi 6 Lite, overwrite the bootargs property of the chosen\nnode leading to a kernel panic when loading OpenWrt.\n\nSigned-off-by: David Bauer <mail@david-bauer.net>\n---\n arch/mips/kernel/setup.c | 30 ++++++++++++++++++++++++++++++\n 1 file changed, 30 insertions(+)\n\n--- a/arch/mips/kernel/setup.c\n+++ b/arch/mips/kernel/setup.c\n@@ -542,8 +542,28 @@ static int __init bootcmdline_scan_chose\n \n #endif /* CONFIG_OF_EARLY_FLATTREE */\n \n+static int __init bootcmdline_scan_chosen_override(unsigned long node, const char *uname,\n+\t\t\t\t\t\t   int depth, void *data)\n+{\n+\tbool *dt_bootargs = data;\n+\tconst char *p;\n+\tint l;\n+\n+\tif (depth != 1 || !data || strcmp(uname, \"chosen\") != 0)\n+\t\treturn 0;\n+\n+\tp = of_get_flat_dt_prop(node, \"bootargs-override\", &l);\n+\tif (p != NULL && l > 0) {\n+\t\tstrlcpy(boot_command_line, p, COMMAND_LINE_SIZE);\n+\t\t*dt_bootargs = true;\n+\t}\n+\n+\treturn 1;\n+}\n+\n static void __init bootcmdline_init(void)\n {\n+\tbool dt_bootargs_override = false;\n \tbool dt_bootargs = false;\n \n \t/*\n@@ -557,6 +577,14 @@ static void __init bootcmdline_init(void\n \t}\n \n \t/*\n+\t * If bootargs-override in the chosen node is set, use this as the\n+\t * command line\n+\t */\n+\tof_scan_flat_dt(bootcmdline_scan_chosen_override, &dt_bootargs_override);\n+\tif (dt_bootargs_override)\n+\t\treturn;\n+\n+\t/*\n \t * If the user specified a built-in command line &\n \t * MIPS_CMDLINE_BUILTIN_EXTEND, then the built-in command line is\n \t * prepended to arguments from the bootloader or DT so we'll copy them\n"
  },
  {
    "path": "target/linux/ramips/patches-5.10/315-owrt-hack-fix-mt7688-cache-issue.patch",
    "content": "From 5ede027f6c4a57ed25da872420508b7f1168b36b Mon Sep 17 00:00:00 2001\nFrom: John Crispin <blogic@openwrt.org>\nDate: Mon, 7 Dec 2015 17:15:32 +0100\nSubject: [PATCH 13/53] owrt: hack: fix mt7688 cache issue\n\nSigned-off-by: John Crispin <blogic@openwrt.org>\n---\n arch/mips/kernel/setup.c |    2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/arch/mips/kernel/setup.c\n+++ b/arch/mips/kernel/setup.c\n@@ -694,8 +694,6 @@ static void __init arch_mem_init(char **\n \tif (crashk_res.start != crashk_res.end)\n \t\tmemblock_reserve(crashk_res.start, resource_size(&crashk_res));\n #endif\n-\tdevice_tree_init();\n-\n \t/*\n \t * In order to reduce the possibility of kernel panic when failed to\n \t * get IO TLB memory under CONFIG_SWIOTLB, it is better to allocate\n@@ -815,6 +813,7 @@ void __init setup_arch(char **cmdline_p)\n \n \tcpu_cache_init();\n \tpaging_init();\n+\tdevice_tree_init();\n }\n \n unsigned long kernelsp[NR_CPUS];\n"
  },
  {
    "path": "target/linux/ramips/patches-5.10/316-arch-mips-do-not-select-illegal-access-driver-by-def.patch",
    "content": "From 9e6ce539092a1dd605a20bf73c655a9de58d8641 Mon Sep 17 00:00:00 2001\nFrom: John Crispin <blogic@openwrt.org>\nDate: Mon, 7 Dec 2015 17:18:05 +0100\nSubject: [PATCH 15/53] arch: mips: do not select illegal access driver by\n default\n\nSigned-off-by: John Crispin <blogic@openwrt.org>\n---\n arch/mips/ralink/Kconfig |    4 ++--\n 1 file changed, 2 insertions(+), 2 deletions(-)\n\n--- a/arch/mips/ralink/Kconfig\n+++ b/arch/mips/ralink/Kconfig\n@@ -14,9 +14,9 @@ config CLKEVT_RT3352\n \tselect CEVT_SYSTICK_QUIRK\n \n config RALINK_ILL_ACC\n-\tbool\n+\tbool \"illegal access irq\"\n \tdepends on SOC_RT305X\n-\tdefault y\n+\tdefault n\n \n config IRQ_INTC\n \tbool\n"
  },
  {
    "path": "target/linux/ramips/patches-5.10/320-MIPS-add-support-for-buggy-MT7621S-core-detection.patch",
    "content": "From 6decd1aad15f56b169217789630a0098b496de0e Mon Sep 17 00:00:00 2001\nFrom: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com>\nDate: Wed, 7 Apr 2021 13:07:38 -0700\nSubject: [PATCH] MIPS: add support for buggy MT7621S core detection\n\nMost MT7621 SoCs have 2 cores, which is detected and supported properly\nby CPS.\n\nUnfortunately, MT7621 SoC has a less common S variant with only one core.\nOn MT7621S, GCR_CONFIG still reports 2 cores, which leads to hangs when\nstarting SMP. CPULAUNCH registers can be used in that case to detect the\nabsence of the second core and override the GCR_CONFIG PCORES field.\n\nRework a long-standing OpenWrt patch to override the value of\nmips_cps_numcores on single-core MT7621 systems.\n\nTested on a dual-core MT7621 device (Ubiquiti ER-X) and a single-core\nMT7621 device (Netgear R6220).\n\nOriginal 4.14 OpenWrt patch:\nLink: https://git.openwrt.org/?p=openwrt/openwrt.git;a=commitdiff;h=4cdbc90a376dd0555201c1434a2081e055e9ceb7\nCurrent 5.10 OpenWrt patch:\nLink: https://git.openwrt.org/?p=openwrt/openwrt.git;a=blob;f=target/linux/ramips/patches-5.10/320-mt7621-core-detect-hack.patch;h=c63f0f4c1ec742e24d8480e80553863744b58f6a;hb=10267e17299806f9885d086147878f6c492cb904\n\nSuggested-by: Felix Fietkau <nbd@nbd.name>\nSigned-off-by: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com>\nSigned-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>\n---\n arch/mips/include/asm/mips-cps.h | 23 ++++++++++++++++++++++-\n 1 file changed, 22 insertions(+), 1 deletion(-)\n\n--- a/arch/mips/include/asm/mips-cps.h\n+++ b/arch/mips/include/asm/mips-cps.h\n@@ -10,6 +10,8 @@\n #include <linux/io.h>\n #include <linux/types.h>\n \n+#include <asm/mips-boards/launch.h>\n+\n extern unsigned long __cps_access_bad_size(void)\n \t__compiletime_error(\"Bad size for CPS accessor\");\n \n@@ -165,11 +167,30 @@ static inline uint64_t mips_cps_cluster_\n  */\n static inline unsigned int mips_cps_numcores(unsigned int cluster)\n {\n+\tunsigned int ncores;\n+\n \tif (!mips_cm_present())\n \t\treturn 0;\n \n \t/* Add one before masking to handle 0xff indicating no cores */\n-\treturn (mips_cps_cluster_config(cluster) + 1) & CM_GCR_CONFIG_PCORES;\n+\tncores = (mips_cps_cluster_config(cluster) + 1) & CM_GCR_CONFIG_PCORES;\n+\n+\tif (IS_ENABLED(CONFIG_SOC_MT7621)) {\n+\t\tstruct cpulaunch *launch;\n+\n+\t\t/*\n+\t\t * Ralink MT7621S SoC is single core, but the GCR_CONFIG method\n+\t\t * always reports 2 cores. Check the second core's LAUNCH_FREADY\n+\t\t * flag to detect if the second core is missing. This method\n+\t\t * only works before the core has been started.\n+\t\t */\n+\t\tlaunch = (struct cpulaunch *)CKSEG0ADDR(CPULAUNCH);\n+\t\tlaunch += 2; /* MT7621 has 2 VPEs per core */\n+\t\tif (!(launch->flags & LAUNCH_FREADY))\n+\t\t\tncores = 1;\n+\t}\n+\n+\treturn ncores;\n }\n \n /**\n"
  },
  {
    "path": "target/linux/ramips/patches-5.10/322-mt7621-fix-cpu-clk-add-clkdev.patch",
    "content": "--- a/arch/mips/include/asm/mach-ralink/mt7621.h\n+++ b/arch/mips/include/asm/mach-ralink/mt7621.h\n@@ -17,6 +17,10 @@\n #define SYSC_REG_CHIP_REV\t\t0x0c\n #define SYSC_REG_SYSTEM_CONFIG0\t\t0x10\n #define SYSC_REG_SYSTEM_CONFIG1\t\t0x14\n+#define SYSC_REG_CLKCFG0\t\t0x2c\n+#define SYSC_REG_CUR_CLK_STS\t\t0x44\n+\n+#define MEMC_REG_CPU_PLL\t\t0x648\n \n #define CHIP_REV_PKG_MASK\t\t0x1\n #define CHIP_REV_PKG_SHIFT\t\t16\n@@ -24,6 +28,22 @@\n #define CHIP_REV_VER_SHIFT\t\t8\n #define CHIP_REV_ECO_MASK\t\t0xf\n \n+#define XTAL_MODE_SEL_MASK\t\t0x7\n+#define XTAL_MODE_SEL_SHIFT\t\t6\n+\n+#define CPU_CLK_SEL_MASK\t\t0x3\n+#define CPU_CLK_SEL_SHIFT\t\t30\n+\n+#define CUR_CPU_FDIV_MASK\t\t0x1f\n+#define CUR_CPU_FDIV_SHIFT\t\t8\n+#define CUR_CPU_FFRAC_MASK\t\t0x1f\n+#define CUR_CPU_FFRAC_SHIFT\t\t0\n+\n+#define CPU_PLL_PREDIV_MASK\t\t0x3\n+#define CPU_PLL_PREDIV_SHIFT\t\t12\n+#define CPU_PLL_FBDIV_MASK\t\t0x7f\n+#define CPU_PLL_FBDIV_SHIFT\t\t4\n+\n #define MT7621_DRAM_BASE                0x0\n #define MT7621_DDR2_SIZE_MIN\t\t32\n #define MT7621_DDR2_SIZE_MAX\t\t256\n--- a/arch/mips/ralink/mt7621.c\n+++ b/arch/mips/ralink/mt7621.c\n@@ -9,12 +9,17 @@\n #include <linux/init.h>\n #include <linux/slab.h>\n #include <linux/sys_soc.h>\n+#include <linux/clk.h>\n+#include <linux/clkdev.h>\n+#include <linux/clk-provider.h>\n+#include <dt-bindings/clock/mt7621-clk.h>\n \n #include <asm/mipsregs.h>\n #include <asm/smp-ops.h>\n #include <asm/mips-cps.h>\n #include <asm/mach-ralink/ralink_regs.h>\n #include <asm/mach-ralink/mt7621.h>\n+#include <asm/time.h>\n \n #include <pinmux.h>\n \n@@ -105,11 +110,89 @@ static struct rt2880_pmx_group mt7621_pi\n \t{ 0 }\n };\n \n+static struct clk *clks[MT7621_CLK_MAX];\n+static struct clk_onecell_data clk_data = {\n+\t.clks = clks,\n+\t.clk_num = ARRAY_SIZE(clks),\n+};\n+\n phys_addr_t mips_cpc_default_phys_base(void)\n {\n \tpanic(\"Cannot detect cpc address\");\n }\n \n+static struct clk *__init mt7621_add_sys_clkdev(\n+\tconst char *id, unsigned long rate)\n+{\n+\tstruct clk *clk;\n+\tint err;\n+\n+\tclk = clk_register_fixed_rate(NULL, id, NULL, 0, rate);\n+\tif (IS_ERR(clk))\n+\t\tpanic(\"failed to allocate %s clock structure\", id);\n+\n+\terr = clk_register_clkdev(clk, id, NULL);\n+\tif (err)\n+\t\tpanic(\"unable to register %s clock device\", id);\n+\n+\treturn clk;\n+}\n+\n+void __init ralink_clk_init(void)\n+{\n+\tu32 syscfg, xtal_sel, clkcfg, clk_sel, curclk, ffiv, ffrac;\n+\tu32 pll, prediv, fbdiv;\n+\tu32 xtal_clk, cpu_clk, bus_clk;\n+\tconst static u32 prediv_tbl[] = {0, 1, 2, 2};\n+\n+\tsyscfg = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG0);\n+\txtal_sel = (syscfg >> XTAL_MODE_SEL_SHIFT) & XTAL_MODE_SEL_MASK;\n+\n+\tclkcfg = rt_sysc_r32(SYSC_REG_CLKCFG0);\n+\tclk_sel = (clkcfg >> CPU_CLK_SEL_SHIFT) & CPU_CLK_SEL_MASK;\n+\n+\tcurclk = rt_sysc_r32(SYSC_REG_CUR_CLK_STS);\n+\tffiv = (curclk >> CUR_CPU_FDIV_SHIFT) & CUR_CPU_FDIV_MASK;\n+\tffrac = (curclk >> CUR_CPU_FFRAC_SHIFT) & CUR_CPU_FFRAC_MASK;\n+\n+\tif (xtal_sel <= 2)\n+\t\txtal_clk = 20 * 1000 * 1000;\n+\telse if (xtal_sel <= 5)\n+\t\txtal_clk = 40 * 1000 * 1000;\n+\telse\n+\t\txtal_clk = 25 * 1000 * 1000;\n+\n+\tswitch (clk_sel) {\n+\tcase 0:\n+\t\tcpu_clk = 500 * 1000 * 1000;\n+\t\tbreak;\n+\tcase 1:\n+\t\tpll = rt_memc_r32(MEMC_REG_CPU_PLL);\n+\t\tfbdiv = (pll >> CPU_PLL_FBDIV_SHIFT) & CPU_PLL_FBDIV_MASK;\n+\t\tprediv = (pll >> CPU_PLL_PREDIV_SHIFT) & CPU_PLL_PREDIV_MASK;\n+\t\tcpu_clk = ((fbdiv + 1) * xtal_clk) >> prediv_tbl[prediv];\n+\t\tbreak;\n+\tdefault:\n+\t\tcpu_clk = xtal_clk;\n+\t}\n+\n+\tcpu_clk = cpu_clk / ffiv * ffrac;\n+\tbus_clk = cpu_clk / 4;\n+\n+\tclks[MT7621_CLK_CPU] = mt7621_add_sys_clkdev(\"cpu\", cpu_clk);\n+\tclks[MT7621_CLK_BUS] = mt7621_add_sys_clkdev(\"bus\", bus_clk);\n+\n+\tpr_info(\"CPU Clock: %dMHz\\n\", cpu_clk / 1000000);\n+\tmips_hpt_frequency = cpu_clk / 2;\n+}\n+\n+static void __init mt7621_clocks_init_dt(struct device_node *np)\n+{\n+\tof_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);\n+}\n+\n+CLK_OF_DECLARE(mt7621, \"mediatek,mt7621-pll\", mt7621_clocks_init_dt);\n+\n void __init ralink_of_remap(void)\n {\n \trt_sysc_membase = plat_of_remap_node(\"mtk,mt7621-sysc\");\n--- a/arch/mips/ralink/timer-gic.c\n+++ b/arch/mips/ralink/timer-gic.c\n@@ -9,14 +9,14 @@\n \n #include <linux/of.h>\n #include <linux/of_clk.h>\n-#include <linux/clocksource.h>\n+#include <asm/time.h>\n \n #include \"common.h\"\n \n void __init plat_time_init(void)\n {\n \tralink_of_remap();\n-\n+\tralink_clk_init();\n \tof_clk_init(NULL);\n \ttimer_probe();\n }\n--- /dev/null\n+++ b/include/dt-bindings/clock/mt7621-clk.h\n@@ -0,0 +1,18 @@\n+/*\n+ * Copyright (C) 2018 Weijie Gao <hackpascal@gmail.com>\n+ *\n+ * This program is free software; you can redistribute it and/or modify\n+ * it under the terms of the GNU General Public License version 2 as\n+ * published by the Free Software Foundation.\n+ *\n+ */\n+\n+#ifndef __DT_BINDINGS_MT7621_CLK_H\n+#define __DT_BINDINGS_MT7621_CLK_H\n+\n+#define MT7621_CLK_CPU\t\t0\n+#define MT7621_CLK_BUS\t\t1\n+\n+#define MT7621_CLK_MAX\t\t2\n+\n+#endif /* __DT_BINDINGS_MT7621_CLK_H */\n"
  },
  {
    "path": "target/linux/ramips/patches-5.10/323-mt7621-memory-detect.patch",
    "content": "From b5a52351a66f3c2a7a207548aa87d78ff2d336c0 Mon Sep 17 00:00:00 2001\nFrom: Chuanhong Guo <gch981213@gmail.com>\nDate: Wed, 10 Jul 2019 00:24:48 +0800\nSubject: [PATCH] MIPS: ralink: mt7621: add memory detection support\n\nmt7621 has the following memory map:\n0x0-0x1c000000: lower 448m memory\n0x1c000000-0x2000000: peripheral registers\n0x20000000-0x2400000: higher 64m memory\n\ndetect_memory_region in arch/mips/kernel/setup.c only add the first\nmemory region and isn't suitable for 512m memory detection because\nit may accidentally read the memory area for peripheral registers.\n\nThis commit adds memory detection capability for mt7621:\n1. add the highmem area when 512m is detected.\n2. guard memcmp from accessing peripheral registers:\n     This only happens when some weird user decided to change\n     kernel load address to 256m or higher address. Since this\n     is a quite unusual case, we just skip 512m testing and return\n     256m as memory size.\n\nSigned-off-by: Chuanhong Guo <gch981213@gmail.com>\n---\n arch/mips/include/asm/mach-ralink/mt7621.h |  7 ++---\n arch/mips/ralink/mt7621.c                  | 30 +++++++++++++++++++---\n 2 files changed, 30 insertions(+), 7 deletions(-)\n\n--- a/arch/mips/include/asm/mach-ralink/mt7621.h\n+++ b/arch/mips/include/asm/mach-ralink/mt7621.h\n@@ -44,9 +44,10 @@\n #define CPU_PLL_FBDIV_MASK\t\t0x7f\n #define CPU_PLL_FBDIV_SHIFT\t\t4\n \n-#define MT7621_DRAM_BASE                0x0\n-#define MT7621_DDR2_SIZE_MIN\t\t32\n-#define MT7621_DDR2_SIZE_MAX\t\t256\n+#define MT7621_LOWMEM_BASE\t\t0x0\n+#define MT7621_LOWMEM_MAX_SIZE\t\t0x1C000000\n+#define MT7621_HIGHMEM_BASE\t\t0x20000000\n+#define MT7621_HIGHMEM_SIZE\t\t0x4000000\n \n #define MT7621_CHIP_NAME0\t\t0x3637544D\n #define MT7621_CHIP_NAME1\t\t0x20203132\n--- a/arch/mips/ralink/mt7621.c\n+++ b/arch/mips/ralink/mt7621.c\n@@ -9,11 +9,13 @@\n #include <linux/init.h>\n #include <linux/slab.h>\n #include <linux/sys_soc.h>\n+#include <linux/memblock.h>\n #include <linux/clk.h>\n #include <linux/clkdev.h>\n #include <linux/clk-provider.h>\n #include <dt-bindings/clock/mt7621-clk.h>\n \n+#include <asm/bootinfo.h>\n #include <asm/mipsregs.h>\n #include <asm/smp-ops.h>\n #include <asm/mips-cps.h>\n@@ -54,6 +56,8 @@\n #define MT7621_GPIO_MODE_SDHCI_SHIFT\t18\n #define MT7621_GPIO_MODE_SDHCI_GPIO\t1\n \n+static void *detect_magic __initdata = detect_memory_region;\n+\n static struct rt2880_pmx_func uart1_grp[] =  { FUNC(\"uart1\", 0, 1, 2) };\n static struct rt2880_pmx_func i2c_grp[] =  { FUNC(\"i2c\", 0, 3, 2) };\n static struct rt2880_pmx_func uart3_grp[] = {\n@@ -138,6 +142,26 @@ static struct clk *__init mt7621_add_sys\n \treturn clk;\n }\n \n+void __init mt7621_memory_detect(void)\n+{\n+\tvoid *dm = &detect_magic;\n+\tphys_addr_t size;\n+\n+\tfor (size = 32 * SZ_1M; size < 256 * SZ_1M; size <<= 1) {\n+\t\tif (!__builtin_memcmp(dm, dm + size, sizeof(detect_magic)))\n+\t\t\tbreak;\n+\t}\n+\n+\tif ((size == 256 * SZ_1M) &&\n+\t    (CPHYSADDR(dm + size) < MT7621_LOWMEM_MAX_SIZE) &&\n+\t    __builtin_memcmp(dm, dm + size, sizeof(detect_magic))) {\n+\t\tmemblock_add(MT7621_LOWMEM_BASE, MT7621_LOWMEM_MAX_SIZE);\n+\t\tmemblock_add(MT7621_HIGHMEM_BASE, MT7621_HIGHMEM_SIZE);\n+\t} else {\n+\t\tmemblock_add(MT7621_LOWMEM_BASE, size);\n+\t}\n+}\n+\n void __init ralink_clk_init(void)\n {\n \tu32 syscfg, xtal_sel, clkcfg, clk_sel, curclk, ffiv, ffrac;\n@@ -277,10 +301,7 @@ void prom_soc_init(struct ralink_soc_inf\n \t\t(rev >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK,\n \t\t(rev & CHIP_REV_ECO_MASK));\n \n-\tsoc_info->mem_size_min = MT7621_DDR2_SIZE_MIN;\n-\tsoc_info->mem_size_max = MT7621_DDR2_SIZE_MAX;\n-\tsoc_info->mem_base = MT7621_DRAM_BASE;\n-\n+\tsoc_info->mem_detect = mt7621_memory_detect;\n \trt2880_pinmux_data = mt7621_pinmux_data;\n \n \tsoc_dev_init(soc_info, rev);\n--- a/arch/mips/ralink/common.h\n+++ b/arch/mips/ralink/common.h\n@@ -17,6 +17,7 @@ struct ralink_soc_info {\n \tunsigned long mem_size;\n \tunsigned long mem_size_min;\n \tunsigned long mem_size_max;\n+\tvoid (*mem_detect)(void);\n };\n extern struct ralink_soc_info soc_info;\n \n--- a/arch/mips/ralink/of.c\n+++ b/arch/mips/ralink/of.c\n@@ -85,6 +85,8 @@ void __init plat_mem_setup(void)\n \tof_scan_flat_dt(early_init_dt_find_memory, NULL);\n \tif (memory_dtb)\n \t\tof_scan_flat_dt(early_init_dt_scan_memory, NULL);\n+\telse if (soc_info.mem_detect)\n+\t\tsoc_info.mem_detect();\n \telse if (soc_info.mem_size)\n \t\tmemblock_add(soc_info.mem_base, soc_info.mem_size * SZ_1M);\n \telse\n"
  },
  {
    "path": "target/linux/ramips/patches-5.10/324-mt7621-perfctr-fix.patch",
    "content": "--- a/arch/mips/ralink/irq-gic.c\n+++ b/arch/mips/ralink/irq-gic.c\n@@ -13,6 +13,12 @@\n \n int get_c0_perfcount_int(void)\n {\n+\t/*\n+\t * Performance counter events are routed through GIC.\n+\t * Prevent them from firing on CPU IRQ7 as well\n+\t */\n+\tclear_c0_status(IE_SW0 << 7);\n+\n \treturn gic_get_c0_perfcount_int();\n }\n EXPORT_SYMBOL_GPL(get_c0_perfcount_int);\n"
  },
  {
    "path": "target/linux/ramips/patches-5.10/325-mt7621-fix-memory-detect.patch",
    "content": "--- a/arch/mips/ralink/mt7621.c\n+++ b/arch/mips/ralink/mt7621.c\n@@ -56,7 +56,9 @@\n #define MT7621_GPIO_MODE_SDHCI_SHIFT\t18\n #define MT7621_GPIO_MODE_SDHCI_GPIO\t1\n \n-static void *detect_magic __initdata = detect_memory_region;\n+#define MT7621_MEM_TEST_PATTERN         0xaa5555aa\n+\n+static u32 detect_magic __initdata;\n \n static struct rt2880_pmx_func uart1_grp[] =  { FUNC(\"uart1\", 0, 1, 2) };\n static struct rt2880_pmx_func i2c_grp[] =  { FUNC(\"i2c\", 0, 3, 2) };\n@@ -142,24 +144,32 @@ static struct clk *__init mt7621_add_sys\n \treturn clk;\n }\n \n+static bool __init mt7621_addr_wraparound_test(phys_addr_t size)\n+{\n+\tvoid *dm = (void *)KSEG1ADDR(&detect_magic);\n+\tif (CPHYSADDR(dm + size) >= MT7621_LOWMEM_MAX_SIZE)\n+\t\treturn true;\n+\t__raw_writel(MT7621_MEM_TEST_PATTERN, dm);\n+\tif (__raw_readl(dm) != __raw_readl(dm + size))\n+\t\treturn false;\n+\t__raw_writel(!MT7621_MEM_TEST_PATTERN, dm);\n+\treturn __raw_readl(dm) == __raw_readl(dm + size);\n+}\n+\n void __init mt7621_memory_detect(void)\n {\n-\tvoid *dm = &detect_magic;\n \tphys_addr_t size;\n \n-\tfor (size = 32 * SZ_1M; size < 256 * SZ_1M; size <<= 1) {\n-\t\tif (!__builtin_memcmp(dm, dm + size, sizeof(detect_magic)))\n-\t\t\tbreak;\n+\tfor (size = 32 * SZ_1M; size <= 256 * SZ_1M; size <<= 1) {\n+\t\tif (mt7621_addr_wraparound_test(size)) {\n+\t\t\tmemblock_add(MT7621_LOWMEM_BASE, size);\n+\t\t\treturn;\n+\t\t}\n \t}\n \n-\tif ((size == 256 * SZ_1M) &&\n-\t    (CPHYSADDR(dm + size) < MT7621_LOWMEM_MAX_SIZE) &&\n-\t    __builtin_memcmp(dm, dm + size, sizeof(detect_magic))) {\n-\t\tmemblock_add(MT7621_LOWMEM_BASE, MT7621_LOWMEM_MAX_SIZE);\n-\t\tmemblock_add(MT7621_HIGHMEM_BASE, MT7621_HIGHMEM_SIZE);\n-\t} else {\n-\t\tmemblock_add(MT7621_LOWMEM_BASE, size);\n-\t}\n+\t/* addr doesn't wrap around at dm + 256M, assume 512M memory. */\n+\tmemblock_add(MT7621_LOWMEM_BASE, MT7621_LOWMEM_MAX_SIZE);\n+\tmemblock_add(MT7621_HIGHMEM_BASE, MT7621_HIGHMEM_SIZE);\n }\n \n void __init ralink_clk_init(void)\n"
  },
  {
    "path": "target/linux/ramips/patches-5.10/400-mtd-cfi-cmdset-0002-force-word-write.patch",
    "content": "From ee9081b2726a5ca8cde5497afdc5425e21ff8f8b Mon Sep 17 00:00:00 2001\nFrom: John Crispin <blogic@openwrt.org>\nDate: Mon, 15 Jul 2013 00:39:21 +0200\nSubject: [PATCH 37/53] mtd: cfi cmdset 0002 force word write\n\n---\n drivers/mtd/chips/cfi_cmdset_0002.c |    9 +++++++--\n 1 file changed, 7 insertions(+), 2 deletions(-)\n\n--- a/drivers/mtd/chips/cfi_cmdset_0002.c\n+++ b/drivers/mtd/chips/cfi_cmdset_0002.c\n@@ -40,7 +40,7 @@\n #include <linux/mtd/xip.h>\n \n #define AMD_BOOTLOC_BUG\n-#define FORCE_WORD_WRITE 0\n+#define FORCE_WORD_WRITE 1\n \n #define MAX_RETRIES 3\n \n"
  },
  {
    "path": "target/linux/ramips/patches-5.10/405-mtd-spi-nor-Add-support-for-BoHong-bh25q128as.patch",
    "content": "From 52d14545d2fc276b1bf9ccf48d4612fab6edfb6a Mon Sep 17 00:00:00 2001\nFrom: David Bauer <mail@david-bauer.net>\nDate: Thu, 6 May 2021 17:49:55 +0200\nSubject: [PATCH] mtd: spi-nor: Add support for BoHong bh25q128as\n\nAdd MTD support for the BoHong bh25q128as SPI NOR chip.\nThe chip has 16MB of total capacity, divided into a total of 256\nsectors, each 64KB sized. The chip also supports 4KB sectors.\nAdditionally, it supports dual and quad read modes.\n\nFunctionality was verified on an Tenbay WR1800K / MTK MT7621 board.\n\nSigned-off-by: David Bauer <mail@david-bauer.net>\n---\n drivers/mtd/spi-nor/Makefile |  1 +\n drivers/mtd/spi-nor/bohong.c | 21 +++++++++++++++++++++\n drivers/mtd/spi-nor/core.c   |  1 +\n drivers/mtd/spi-nor/core.h   |  1 +\n 4 files changed, 24 insertions(+)\n create mode 100644 drivers/mtd/spi-nor/bohong.c\n\n--- a/drivers/mtd/spi-nor/Makefile\n+++ b/drivers/mtd/spi-nor/Makefile\n@@ -2,6 +2,7 @@\n \n spi-nor-objs\t\t\t:= core.o sfdp.o\n spi-nor-objs\t\t\t+= atmel.o\n+spi-nor-objs\t\t\t+= bohong.o\n spi-nor-objs\t\t\t+= catalyst.o\n spi-nor-objs\t\t\t+= eon.o\n spi-nor-objs\t\t\t+= esmt.o\n--- /dev/null\n+++ b/drivers/mtd/spi-nor/bohong.c\n@@ -0,0 +1,21 @@\n+// SPDX-License-Identifier: GPL-2.0\n+/*\n+ * Copyright (C) 2005, Intec Automation Inc.\n+ * Copyright (C) 2014, Freescale Semiconductor, Inc.\n+ */\n+\n+#include <linux/mtd/spi-nor.h>\n+\n+#include \"core.h\"\n+\n+static const struct flash_info bohong_parts[] = {\n+\t/* BoHong Microelectronics */\n+\t{ \"bh25q128as\", INFO(0x684018, 0, 64 * 1024, 256,\n+\t\t\t    SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },\n+};\n+\n+const struct spi_nor_manufacturer spi_nor_bohong = {\n+\t.name = \"bohong\",\n+\t.parts = bohong_parts,\n+\t.nparts = ARRAY_SIZE(bohong_parts),\n+};\n--- a/drivers/mtd/spi-nor/core.c\n+++ b/drivers/mtd/spi-nor/core.c\n@@ -2012,6 +2012,7 @@ int spi_nor_sr2_bit7_quad_enable(struct\n \n static const struct spi_nor_manufacturer *manufacturers[] = {\n \t&spi_nor_atmel,\n+\t&spi_nor_bohong,\n \t&spi_nor_catalyst,\n \t&spi_nor_eon,\n \t&spi_nor_esmt,\n--- a/drivers/mtd/spi-nor/core.h\n+++ b/drivers/mtd/spi-nor/core.h\n@@ -382,6 +382,7 @@ struct spi_nor_manufacturer {\n \n /* Manufacturer drivers. */\n extern const struct spi_nor_manufacturer spi_nor_atmel;\n+extern const struct spi_nor_manufacturer spi_nor_bohong;\n extern const struct spi_nor_manufacturer spi_nor_catalyst;\n extern const struct spi_nor_manufacturer spi_nor_eon;\n extern const struct spi_nor_manufacturer spi_nor_esmt;\n"
  },
  {
    "path": "target/linux/ramips/patches-5.10/410-mtd-rawnand-add-driver-support-for-MT7621-nand-flash.patch",
    "content": "From e84e2430ee0e483842b4ff013ae8a6e7e2fa2734 Mon Sep 17 00:00:00 2001\nFrom: Weijie Gao <weijie.gao@mediatek.com>\nDate: Wed, 1 Apr 2020 02:07:58 +0800\nSubject: [PATCH 1/2] mtd: rawnand: add driver support for MT7621 nand\n flash controller\n\nThis patch adds NAND flash controller driver for MediaTek MT7621 SoC.\n\nThe NAND flash controller is similar with controllers described in\nmtk_nand.c, except that the controller from MT7621 doesn't support DMA\ntransmission, and some registers' offset and fields are different.\n\nSigned-off-by: Weijie Gao <weijie.gao@mediatek.com>\n---\n drivers/mtd/nand/raw/Kconfig       |    8 +\n drivers/mtd/nand/raw/Makefile      |    1 +\n drivers/mtd/nand/raw/mt7621_nand.c | 1348 ++++++++++++++++++++++++++++++++++++\n 3 files changed, 1357 insertions(+)\n create mode 100644 drivers/mtd/nand/raw/mt7621_nand.c\n\n--- a/drivers/mtd/nand/raw/Kconfig\n+++ b/drivers/mtd/nand/raw/Kconfig\n@@ -387,6 +387,14 @@ config MTD_NAND_QCOM\n \t  Enables support for NAND flash chips on SoCs containing the EBI2 NAND\n \t  controller. This controller is found on IPQ806x SoC.\n \n+config MTD_NAND_MT7621\n+\ttristate \"MT7621 NAND controller\"\n+\tdepends on SOC_MT7621 || COMPILE_TEST\n+\tdepends on HAS_IOMEM\n+\thelp\n+\t  Enables support for NAND controller on MT7621 SoC.\n+\t  This driver uses PIO mode for data transmission instead of DMA mode.\n+\n config MTD_NAND_MTK\n \ttristate \"MTK NAND controller\"\n \tdepends on ARCH_MEDIATEK || COMPILE_TEST\n--- a/drivers/mtd/nand/raw/Makefile\n+++ b/drivers/mtd/nand/raw/Makefile\n@@ -51,6 +51,7 @@ obj-$(CONFIG_MTD_NAND_SUNXI)\t\t+= sunxi_n\n obj-$(CONFIG_MTD_NAND_HISI504)\t        += hisi504_nand.o\n obj-$(CONFIG_MTD_NAND_BRCMNAND)\t\t+= brcmnand/\n obj-$(CONFIG_MTD_NAND_QCOM)\t\t+= qcom_nandc.o\n+obj-$(CONFIG_MTD_NAND_MT7621)\t\t+= mt7621_nand.o\n obj-$(CONFIG_MTD_NAND_MTK)\t\t+= mtk_ecc.o mtk_nand.o\n obj-$(CONFIG_MTD_NAND_MXIC)\t\t+= mxic_nand.o\n obj-$(CONFIG_MTD_NAND_TEGRA)\t\t+= tegra_nand.o\n"
  },
  {
    "path": "target/linux/ramips/patches-5.10/411-dt-bindings-add-documentation-for-mt7621-nand-driver.patch",
    "content": "From 3d5f4da8296b23eb3abf8b13122b0d06a215e79c Mon Sep 17 00:00:00 2001\nFrom: Weijie Gao <weijie.gao@mediatek.com>\nDate: Wed, 1 Apr 2020 02:07:59 +0800\nSubject: [PATCH 2/2] dt-bindings: add documentation for mt7621-nand driver\n\nThis patch adds documentation for MediaTek MT7621 NAND flash controller\ndriver.\n\nSigned-off-by: Weijie Gao <weijie.gao@mediatek.com>\n---\n .../bindings/mtd/mediatek,mt7621-nfc.yaml          | 68 ++++++++++++++++++++++\n 1 file changed, 68 insertions(+)\n create mode 100644 Documentation/devicetree/bindings/mtd/mediatek,mt7621-nfc.yaml\n\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/mtd/mediatek,mt7621-nfc.yaml\n@@ -0,0 +1,68 @@\n+# SPDX-License-Identifier: GPL-2.0\n+%YAML 1.2\n+---\n+$id: http://devicetree.org/schemas/mtd/mediatek,mt7621-nfc.yaml#\n+$schema: http://devicetree.org/meta-schemas/core.yaml#\n+\n+title: MediaTek MT7621 SoC NAND Flash Controller (NFC) DT binding\n+\n+maintainers:\n+  - Weijie Gao <weijie.gao@mediatek.com>\n+\n+description: |\n+  This driver uses a single node to describe both NAND Flash controller\n+  interface (NFI) and ECC engine for MT7621 SoC.\n+  MT7621 supports only one chip select.\n+\n+properties:\n+  \"#address-cells\": false\n+  \"#size-cells\": false\n+\n+  compatible:\n+    enum:\n+      - mediatek,mt7621-nfc\n+\n+  reg:\n+    items:\n+      - description: Register base of NFI core\n+      - description: Register base of ECC engine\n+\n+  reg-names:\n+    items:\n+      - const: nfi\n+      - const: ecc\n+\n+  clocks:\n+    items:\n+      - description: Source clock for NFI core, fixed 125MHz\n+\n+  clock-names:\n+    items:\n+      - const: nfi_clk\n+\n+required:\n+  - compatible\n+  - reg\n+  - reg-names\n+  - clocks\n+  - clock-names\n+\n+examples:\n+  - |\n+    nficlock: nficlock {\n+    \t#clock-cells = <0>;\n+    \tcompatible = \"fixed-clock\";\n+\n+    \tclock-frequency = <125000000>;\n+    };\n+\n+    nand@1e003000 {\n+    \tcompatible = \"mediatek,mt7621-nfc\";\n+\n+    \treg = <0x1e003000 0x800\n+    \t       0x1e003800 0x800>;\n+    \treg-names = \"nfi\", \"ecc\";\n+\n+    \tclocks = <&nficlock>;\n+    \tclock-names = \"nfi_clk\";\n+    };\n"
  },
  {
    "path": "target/linux/ramips/patches-5.10/700-net-ethernet-mediatek-support-net-labels.patch",
    "content": "From bd0f89de5476ca25e73fae829ba3e1dafae1d90d Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Ren=C3=A9=20van=20Dorst?= <opensource@vdorst.com>\nDate: Fri, 21 Jun 2019 10:04:05 +0200\nSubject: [PATCH] net: ethernet: mediatek: support net-labels\n\nWith this patch, device name can be set within dts file in the same way as dsa\nport can.\nAdd: label = \"wan\"; to GMAC node.\n\nSigned-off-by: René van Dorst <opensource@vdorst.com>\n---\n drivers/net/ethernet/mediatek/mtk_eth_soc.c | 4 ++++\n 1 file changed, 4 insertions(+)\n\n--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c\n+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c\n@@ -2955,6 +2955,7 @@ static const struct net_device_ops mtk_n\n \n static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np)\n {\n+\tconst char *name = of_get_property(np, \"label\", NULL);\n \tconst __be32 *_id = of_get_property(np, \"reg\", NULL);\n \tphy_interface_t phy_mode;\n \tstruct phylink *phylink;\n@@ -3050,6 +3051,9 @@ static int mtk_add_mac(struct mtk_eth *e\n \telse\n \t\teth->netdev[id]->max_mtu = MTK_MAX_RX_LENGTH_2K - MTK_RX_ETH_HLEN;\n \n+\tif (name)\n+\t\tstrlcpy(eth->netdev[id]->name, name, IFNAMSIZ);\n+\n \treturn 0;\n \n free_netdev:\n"
  },
  {
    "path": "target/linux/ramips/patches-5.10/710-at803x.patch",
    "content": "From 924453aa9d2324e5611f8e2b71df746d8f0c79f1 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Ren=C3=A9=20van=20Dorst?= <opensource@vdorst.com>\nDate: Fri, 13 Nov 2020 16:11:32 +0100\nSubject: [PATCH] net: phy: at803x: add support for SFP module in\n RGMII-to-x-base mode\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nSigned-off-by: René van Dorst <opensource@vdorst.com>\n---\n drivers/net/phy/at803x.c | 91 ++++++++++++++++++++++++++++++++++++++++\n 1 file changed, 91 insertions(+)\n\n--- a/drivers/net/phy/at803x.c\n+++ b/drivers/net/phy/at803x.c\n@@ -20,6 +20,8 @@\n #include <linux/regulator/driver.h>\n #include <linux/regulator/consumer.h>\n #include <dt-bindings/net/qca-ar803x.h>\n+#include <linux/sfp.h>\n+#include <linux/phylink.h>\n \n #define AT803X_SPECIFIC_FUNCTION_CONTROL\t0x10\n #define AT803X_SFC_ASSERT_CRS\t\t\tBIT(11)\n@@ -82,9 +84,18 @@\n \n #define AT803X_MODE_CFG_MASK\t\t\t0x0F\n #define AT803X_MODE_CFG_SGMII\t\t\t0x01\n+#define AT803X_MODE_CFG_BX1000_RGMII_50\t\t0x02\n+#define AT803X_MODE_CFG_BX1000_RGMII_75\t\t0x03\n+#define AT803X_MODE_FIBER\t\t\t0x01\n+#define AT803X_MODE_COPPER\t\t\t0x00\n \n #define AT803X_PSSR\t\t\t0x11\t/*PHY-Specific Status Register*/\n #define AT803X_PSSR_MR_AN_COMPLETE\t0x0200\n+#define\t PSSR_LINK\t\t\tBIT(10)\n+#define\t PSSR_SYNC_STATUS\t\tBIT(8)\n+#define\t PSSR_DUPLEX\t\t\tBIT(13)\n+#define\t PSSR_SPEED_1000\t\tBIT(15)\n+#define\t PSSR_SPEED_100\t\t\tBIT(14)\n \n #define AT803X_DEBUG_ANALOG_TEST_CTRL\t\t0x00\n #define QCA8327_DEBUG_MANU_CTRL_EN\t\tBIT(2)\n@@ -629,12 +640,75 @@ static int at803x_parse_dt(struct phy_de\n \treturn 0;\n }\n \n+static int at803x_mode(struct phy_device *phydev)\n+{\n+\tint mode;\n+\n+\tmode = phy_read(phydev, AT803X_REG_CHIP_CONFIG) & AT803X_MODE_CFG_MASK;\n+\n+\tif (mode == AT803X_MODE_CFG_BX1000_RGMII_50 ||\n+\t    mode == AT803X_MODE_CFG_BX1000_RGMII_75)\n+\t\treturn AT803X_MODE_FIBER;\n+\treturn AT803X_MODE_COPPER;\n+}\n+\n+static int at803x_sfp_insert(void *upstream, const struct sfp_eeprom_id *id)\n+{\n+\t__ETHTOOL_DECLARE_LINK_MODE_MASK(at803x_support) = { 0, };\n+\t__ETHTOOL_DECLARE_LINK_MODE_MASK(support) = { 0, };\n+\tstruct phy_device *phydev = upstream;\n+\tphy_interface_t iface;\n+\n+\tphylink_set(at803x_support, 1000baseX_Full);\n+\t/* AT803x only support 1000baseX but SGMII works fine when module runs\n+\t * at 1Gbit.\n+\t */\n+\tphylink_set(at803x_support, 1000baseT_Full);\n+\n+\tsfp_parse_support(phydev->sfp_bus, id, support);\n+\n+\t// Limit to interfaces that both sides support\n+\tlinkmode_and(support, support, at803x_support);\n+\n+\tif (linkmode_empty(support))\n+\t\tgoto unsupported_mode;\n+\n+\tiface = sfp_select_interface(phydev->sfp_bus, support);\n+\n+\tif (iface != PHY_INTERFACE_MODE_SGMII &&\n+\t    iface != PHY_INTERFACE_MODE_1000BASEX)\n+\t\tgoto unsupported_mode;\n+\n+\tdev_info(&phydev->mdio.dev, \"SFP interface %s\", phy_modes(iface));\n+\n+\treturn 0;\n+\n+unsupported_mode:\n+\tdev_info(&phydev->mdio.dev, \"incompatible SFP module inserted;\"\n+\t\t \"Only SGMII at 1Gbit/1000BASEX are supported!\\n\");\n+\treturn -EINVAL;\n+}\n+\n+static const struct sfp_upstream_ops at803x_sfp_ops = {\n+\t.attach = phy_sfp_attach,\n+\t.detach = phy_sfp_detach,\n+\t.module_insert = at803x_sfp_insert,\n+};\n+\n+\n static int at803x_probe(struct phy_device *phydev)\n {\n \tstruct device *dev = &phydev->mdio.dev;\n \tstruct at803x_priv *priv;\n \tint ret;\n \n+\n+\tif (at803x_mode(phydev) == AT803X_MODE_FIBER) {\n+\t\tret = phy_sfp_probe(phydev, &at803x_sfp_ops);\n+\t\tif (ret < 0)\n+\t\t\treturn ret;\n+\t}\n+\n \tpriv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);\n \tif (!priv)\n \t\treturn -ENOMEM;\n@@ -651,6 +725,7 @@ static int at803x_probe(struct phy_devic\n \t\t\treturn ret;\n \t}\n \n+#if 0\n \t/* Some bootloaders leave the fiber page selected.\n \t * Switch to the copper page, as otherwise we read\n \t * the PHY capabilities from the fiber side.\n@@ -662,6 +737,7 @@ static int at803x_probe(struct phy_devic\n \t\tif (ret)\n \t\t\tgoto err;\n \t}\n+#endif\n \n \treturn 0;\n \n@@ -841,6 +917,10 @@ static int at803x_read_status(struct phy\n {\n \tint ss, err, old_link = phydev->link;\n \n+\t/* Handle (Fiber) SGMII to RGMII mode */\n+\tif (at803x_mode(phydev) == AT803X_MODE_FIBER)\n+\t\treturn genphy_c37_read_status(phydev);\n+\n \t/* Update the link, but return if there was an error */\n \terr = genphy_update_link(phydev);\n \tif (err)\n@@ -941,6 +1021,12 @@ static int at803x_config_aneg(struct phy\n {\n \tint ret;\n \n+\t/* Handle (Fiber) SerDes to RGMII mode */\n+\tif (at803x_mode(phydev) == AT803X_MODE_FIBER) {\n+\t\tpr_warn(\"%s: fiber\\n\", __func__);\n+\t\treturn genphy_c37_config_aneg(phydev);\n+\t}\n+\n \tret = at803x_config_mdix(phydev, phydev->mdix_ctrl);\n \tif (ret < 0)\n \t\treturn ret;\n@@ -1040,6 +1126,7 @@ static int at803x_get_features(struct ph\n \tif (err)\n \t\treturn err;\n \n+#if 0\n \tif (!at803x_match_phy_id(phydev, ATH8031_PHY_ID))\n \t\treturn 0;\n \n@@ -1057,6 +1144,7 @@ static int at803x_get_features(struct ph\n \t */\n \tlinkmode_clear_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT,\n \t\t\t   phydev->supported);\n+#endif\n \treturn 0;\n }\n \n@@ -1381,6 +1469,7 @@ static struct phy_driver at803x_driver[]\n \t/* Qualcomm Atheros AR8031/AR8033 */\n \tPHY_ID_MATCH_EXACT(ATH8031_PHY_ID),\n \t.name\t\t\t= \"Qualcomm Atheros AR8031/AR8033\",\n+\t.config_aneg\t\t= at803x_config_aneg,\n \t.flags\t\t\t= PHY_POLL_CABLE_TEST,\n \t.probe\t\t\t= at803x_probe,\n \t.remove\t\t\t= at803x_remove,\n"
  },
  {
    "path": "target/linux/ramips/patches-5.10/720-Revert-net-phy-simplify-phy_link_change-arguments.patch",
    "content": "From ffbb1b37a3e1ce1a5c574a6bd4f5aede8bc468ac Mon Sep 17 00:00:00 2001\nFrom: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com>\nDate: Sat, 27 Feb 2021 20:20:07 -0800\nSubject: [PATCH] Revert \"net: phy: simplify phy_link_change arguments\"\n\nThis reverts commit a307593a644443db12888f45eed0dafb5869e2cc.\n\nThis brings back the do_carrier flags used by the (hacky) next patch,\nstill required by target/linux/ramips/files/drivers/net/ethernet/ralink/mdio.c\n---\n drivers/net/phy/phy.c        | 12 ++++++------\n drivers/net/phy/phy_device.c | 12 +++++++-----\n drivers/net/phy/phylink.c    |  3 ++-\n include/linux/phy.h          |  2 +-\n 4 files changed, 16 insertions(+), 13 deletions(-)\n\n--- a/drivers/net/phy/phy.c\n+++ b/drivers/net/phy/phy.c\n@@ -58,13 +58,13 @@ static const char *phy_state_to_str(enum\n \n static void phy_link_up(struct phy_device *phydev)\n {\n-\tphydev->phy_link_change(phydev, true);\n+\tphydev->phy_link_change(phydev, true, true);\n \tphy_led_trigger_change_speed(phydev);\n }\n \n-static void phy_link_down(struct phy_device *phydev)\n+static void phy_link_down(struct phy_device *phydev, bool do_carrier)\n {\n-\tphydev->phy_link_change(phydev, false);\n+\tphydev->phy_link_change(phydev, false, do_carrier);\n \tphy_led_trigger_change_speed(phydev);\n }\n \n@@ -567,7 +567,7 @@ int phy_start_cable_test(struct phy_devi\n \t\tgoto out;\n \n \t/* Mark the carrier down until the test is complete */\n-\tphy_link_down(phydev);\n+\tphy_link_down(phydev, true);\n \n \tnetif_testing_on(dev);\n \terr = phydev->drv->cable_test_start(phydev);\n@@ -638,7 +638,7 @@ int phy_start_cable_test_tdr(struct phy_\n \t\tgoto out;\n \n \t/* Mark the carrier down until the test is complete */\n-\tphy_link_down(phydev);\n+\tphy_link_down(phydev, true);\n \n \tnetif_testing_on(dev);\n \terr = phydev->drv->cable_test_tdr_start(phydev, config);\n@@ -709,7 +709,7 @@ static int phy_check_link_status(struct\n \t\tphy_link_up(phydev);\n \t} else if (!phydev->link && phydev->state != PHY_NOLINK) {\n \t\tphydev->state = PHY_NOLINK;\n-\t\tphy_link_down(phydev);\n+\t\tphy_link_down(phydev, true);\n \t}\n \n \treturn 0;\n@@ -1191,7 +1191,7 @@ void phy_state_machine(struct work_struc\n \tcase PHY_HALTED:\n \t\tif (phydev->link) {\n \t\t\tphydev->link = 0;\n-\t\t\tphy_link_down(phydev);\n+\t\t\tphy_link_down(phydev, true);\n \t\t}\n \t\tdo_suspend = true;\n \t\tbreak;\n--- a/drivers/net/phy/phy_device.c\n+++ b/drivers/net/phy/phy_device.c\n@@ -936,14 +936,16 @@ struct phy_device *phy_find_first(struct\n }\n EXPORT_SYMBOL(phy_find_first);\n \n-static void phy_link_change(struct phy_device *phydev, bool up)\n+static void phy_link_change(struct phy_device *phydev, bool up, bool do_carrier)\n {\n \tstruct net_device *netdev = phydev->attached_dev;\n \n-\tif (up)\n-\t\tnetif_carrier_on(netdev);\n-\telse\n-\t\tnetif_carrier_off(netdev);\n+\tif (do_carrier) {\n+\t\tif (up)\n+\t\t\tnetif_carrier_on(netdev);\n+\t\telse\n+\t\t\tnetif_carrier_off(netdev);\n+\t}\n \tphydev->adjust_link(netdev);\n \tif (phydev->mii_ts && phydev->mii_ts->link_state)\n \t\tphydev->mii_ts->link_state(phydev->mii_ts, phydev);\n--- a/drivers/net/phy/phylink.c\n+++ b/drivers/net/phy/phylink.c\n@@ -931,7 +931,8 @@ void phylink_destroy(struct phylink *pl)\n }\n EXPORT_SYMBOL_GPL(phylink_destroy);\n \n-static void phylink_phy_change(struct phy_device *phydev, bool up)\n+static void phylink_phy_change(struct phy_device *phydev, bool up,\n+\t\t\t       bool do_carrier)\n {\n \tstruct phylink *pl = phydev->phylink;\n \tbool tx_pause, rx_pause;\n--- a/include/linux/phy.h\n+++ b/include/linux/phy.h\n@@ -642,7 +642,7 @@ struct phy_device {\n \tu8 mdix;\n \tu8 mdix_ctrl;\n \n-\tvoid (*phy_link_change)(struct phy_device *phydev, bool up);\n+\tvoid (*phy_link_change)(struct phy_device *, bool up, bool do_carrier);\n \tvoid (*adjust_link)(struct net_device *dev);\n \n #if IS_ENABLED(CONFIG_MACSEC)\n"
  },
  {
    "path": "target/linux/ramips/patches-5.10/721-NET-no-auto-carrier-off-support.patch",
    "content": "From 0b6eb1e68290243d439ee330ea8d0b239a5aec69 Mon Sep 17 00:00:00 2001\nFrom: John Crispin <blogic@openwrt.org>\nDate: Sun, 27 Jul 2014 09:38:50 +0100\nSubject: [PATCH 34/53] NET: multi phy support\n\nSigned-off-by: John Crispin <blogic@openwrt.org>\n---\n drivers/net/phy/phy.c |    9 ++++++---\n include/linux/phy.h   |    1 +\n 2 files changed, 7 insertions(+), 3 deletions(-)\n\n--- a/drivers/net/phy/phy.c\n+++ b/drivers/net/phy/phy.c\n@@ -709,7 +709,10 @@ static int phy_check_link_status(struct\n \t\tphy_link_up(phydev);\n \t} else if (!phydev->link && phydev->state != PHY_NOLINK) {\n \t\tphydev->state = PHY_NOLINK;\n-\t\tphy_link_down(phydev, true);\n+\t\tif (!phydev->no_auto_carrier_off)\n+\t\t\tphy_link_down(phydev, true);\n+\t\telse\n+\t\t\tphy_link_down(phydev, false);\n \t}\n \n \treturn 0;\n@@ -1191,7 +1194,10 @@ void phy_state_machine(struct work_struc\n \tcase PHY_HALTED:\n \t\tif (phydev->link) {\n \t\t\tphydev->link = 0;\n-\t\t\tphy_link_down(phydev, true);\n+\t\t\tif (!phydev->no_auto_carrier_off)\n+\t\t\t\tphy_link_down(phydev, true);\n+\t\t\telse\n+\t\t\t\tphy_link_down(phydev, false);\n \t\t}\n \t\tdo_suspend = true;\n \t\tbreak;\n--- a/include/linux/phy.h\n+++ b/include/linux/phy.h\n@@ -561,6 +561,7 @@ struct phy_device {\n \tunsigned sysfs_links:1;\n \tunsigned loopback_enabled:1;\n \tunsigned downshifted_rate:1;\n+\tunsigned no_auto_carrier_off:1;\n \n \tunsigned autoneg:1;\n \t/* The most recently read link state */\n"
  },
  {
    "path": "target/linux/ramips/patches-5.10/801-DT-Add-documentation-for-gpio-ralink.patch",
    "content": "From d410e5478c622c01fcf31427533df5f433df9146 Mon Sep 17 00:00:00 2001\nFrom: John Crispin <blogic@openwrt.org>\nDate: Sun, 28 Jul 2013 19:45:30 +0200\nSubject: [PATCH 26/53] DT: Add documentation for gpio-ralink\n\nDescribe gpio-ralink binding.\n\nSigned-off-by: John Crispin <blogic@openwrt.org>\nCc: linux-mips@linux-mips.org\nCc: devicetree@vger.kernel.org\nCc: linux-gpio@vger.kernel.org\n---\n .../devicetree/bindings/gpio/gpio-ralink.txt       |   40 ++++++++++++++++++++\n 1 file changed, 40 insertions(+)\n create mode 100644 Documentation/devicetree/bindings/gpio/gpio-ralink.txt\n\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/gpio/gpio-ralink.txt\n@@ -0,0 +1,40 @@\n+Ralink SoC GPIO controller bindings\n+\n+Required properties:\n+- compatible:\n+  - \"ralink,rt2880-gpio\" for Ralink controllers\n+- #gpio-cells : Should be two.\n+  - first cell is the pin number\n+  - second cell is used to specify optional parameters (unused)\n+- gpio-controller : Marks the device node as a GPIO controller\n+- reg : Physical base address and length of the controller's registers\n+- interrupt-parent: phandle to the INTC device node\n+- interrupts : Specify the INTC interrupt number\n+- ngpios : Specify the number of GPIOs\n+- ralink,register-map : The register layout depends on the GPIO bank and actual\n+\t\tSoC type. Register offsets need to be in this order.\n+\t\t[ INT, EDGE, RENA, FENA, DATA, DIR, POL, SET, RESET, TOGGLE ]\n+\n+Optional properties:\n+- ralink,gpio-base : Specify the GPIO chips base number\n+\n+Example:\n+\n+\tgpio0: gpio@600 {\n+\t\tcompatible = \"ralink,rt5350-gpio\", \"ralink,rt2880-gpio\";\n+\n+\t\t#gpio-cells = <2>;\n+\t\tgpio-controller;\n+\n+\t\treg = <0x600 0x34>;\n+\n+\t\tinterrupt-parent = <&intc>;\n+\t\tinterrupts = <6>;\n+\n+\t\tngpios = <24>;\n+\t\tralink,gpio-base = <0>;\n+\t\tralink,register-map = [ 00 04 08 0c\n+\t\t\t\t20 24 28 2c\n+\t\t\t\t30 34 ];\n+\n+\t};\n"
  },
  {
    "path": "target/linux/ramips/patches-5.10/802-GPIO-MIPS-ralink-add-gpio-driver-for-ralink-SoC.patch",
    "content": "From 69fdd2c4f937796b934e89c33acde9d082e27bfd Mon Sep 17 00:00:00 2001\nFrom: John Crispin <blogic@openwrt.org>\nDate: Mon, 4 Aug 2014 20:36:29 +0200\nSubject: [PATCH 27/53] GPIO: MIPS: ralink: add gpio driver for ralink SoC\n\nAdd gpio driver for Ralink SoC. This driver makes the gpio core on\nRT2880, RT305x, rt3352, rt3662, rt3883, rt5350 and mt7620 work.\n\nSigned-off-by: John Crispin <blogic@openwrt.org>\nCc: linux-mips@linux-mips.org\nCc: linux-gpio@vger.kernel.org\n---\n arch/mips/include/asm/mach-ralink/gpio.h |   24 ++\n drivers/gpio/Kconfig                     |    6 +\n drivers/gpio/Makefile                    |    1 +\n drivers/gpio/gpio-ralink.c               |  355 ++++++++++++++++++++++++++++++\n 4 files changed, 386 insertions(+)\n create mode 100644 arch/mips/include/asm/mach-ralink/gpio.h\n create mode 100644 drivers/gpio/gpio-ralink.c\n\n--- /dev/null\n+++ b/arch/mips/include/asm/mach-ralink/gpio.h\n@@ -0,0 +1,24 @@\n+/*\n+ *  Ralink SoC GPIO API support\n+ *\n+ *  Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>\n+ *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>\n+ *\n+ *  This program is free software; you can redistribute it and/or modify it\n+ *  under the terms of the GNU General Public License version 2 as published\n+ *  by the Free Software Foundation.\n+ *\n+ */\n+\n+#ifndef __ASM_MACH_RALINK_GPIO_H\n+#define __ASM_MACH_RALINK_GPIO_H\n+\n+#define ARCH_NR_GPIOS\t128\n+#include <asm-generic/gpio.h>\n+\n+#define gpio_get_value\t__gpio_get_value\n+#define gpio_set_value\t__gpio_set_value\n+#define gpio_cansleep\t__gpio_cansleep\n+#define gpio_to_irq\t__gpio_to_irq\n+\n+#endif /* __ASM_MACH_RALINK_GPIO_H */\n--- a/drivers/gpio/Kconfig\n+++ b/drivers/gpio/Kconfig\n@@ -535,6 +535,12 @@ config GPIO_SNPS_CREG\n \t  where only several fields in register belong to GPIO lines and\n \t  each GPIO line owns a field with different length and on/off value.\n \n+config GPIO_RALINK\n+\tbool \"Ralink GPIO Support\"\n+\tdepends on RALINK\n+\thelp\n+\t  Say yes here to support the Ralink SoC GPIO device\n+\n config GPIO_SPEAR_SPICS\n \tbool \"ST SPEAr13xx SPI Chip Select as GPIO support\"\n \tdepends on PLAT_SPEAR\n--- a/drivers/gpio/Makefile\n+++ b/drivers/gpio/Makefile\n@@ -120,6 +120,7 @@ obj-$(CONFIG_GPIO_PISOSR)\t\t+= gpio-pisos\n obj-$(CONFIG_GPIO_PL061)\t\t+= gpio-pl061.o\n obj-$(CONFIG_GPIO_PMIC_EIC_SPRD)\t+= gpio-pmic-eic-sprd.o\n obj-$(CONFIG_GPIO_PXA)\t\t\t+= gpio-pxa.o\n+obj-$(CONFIG_GPIO_RALINK)\t\t+= gpio-ralink.o\n obj-$(CONFIG_GPIO_RASPBERRYPI_EXP)\t+= gpio-raspberrypi-exp.o\n obj-$(CONFIG_GPIO_RC5T583)\t\t+= gpio-rc5t583.o\n obj-$(CONFIG_GPIO_RCAR)\t\t\t+= gpio-rcar.o\n--- /dev/null\n+++ b/drivers/gpio/gpio-ralink.c\n@@ -0,0 +1,341 @@\n+/*\n+ * This program is free software; you can redistribute it and/or modify it\n+ * under the terms of the GNU General Public License version 2 as published\n+ * by the Free Software Foundation.\n+ *\n+ * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>\n+ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>\n+ */\n+\n+#include <linux/module.h>\n+#include <linux/io.h>\n+#include <linux/gpio.h>\n+#include <linux/spinlock.h>\n+#include <linux/platform_device.h>\n+#include <linux/of_irq.h>\n+#include <linux/irqdomain.h>\n+#include <linux/interrupt.h>\n+\n+enum ralink_gpio_reg {\n+\tGPIO_REG_INT = 0,\n+\tGPIO_REG_EDGE,\n+\tGPIO_REG_RENA,\n+\tGPIO_REG_FENA,\n+\tGPIO_REG_DATA,\n+\tGPIO_REG_DIR,\n+\tGPIO_REG_POL,\n+\tGPIO_REG_SET,\n+\tGPIO_REG_RESET,\n+\tGPIO_REG_TOGGLE,\n+\tGPIO_REG_MAX\n+};\n+\n+struct ralink_gpio_chip {\n+\tstruct gpio_chip chip;\n+\tu8 regs[GPIO_REG_MAX];\n+\n+\tspinlock_t lock;\n+\tvoid __iomem *membase;\n+\tstruct irq_domain *domain;\n+\tint irq;\n+\n+\tu32 rising;\n+\tu32 falling;\n+};\n+\n+#define MAP_MAX\t4\n+static struct irq_domain *irq_map[MAP_MAX];\n+static int irq_map_count;\n+static atomic_t irq_refcount = ATOMIC_INIT(0);\n+\n+static inline struct ralink_gpio_chip *to_ralink_gpio(struct gpio_chip *chip)\n+{\n+\tstruct ralink_gpio_chip *rg;\n+\n+\trg = container_of(chip, struct ralink_gpio_chip, chip);\n+\n+\treturn rg;\n+}\n+\n+static inline void rt_gpio_w32(struct ralink_gpio_chip *rg, u8 reg, u32 val)\n+{\n+\tiowrite32(val, rg->membase + rg->regs[reg]);\n+}\n+\n+static inline u32 rt_gpio_r32(struct ralink_gpio_chip *rg, u8 reg)\n+{\n+\treturn ioread32(rg->membase + rg->regs[reg]);\n+}\n+\n+static void ralink_gpio_set(struct gpio_chip *chip, unsigned offset, int value)\n+{\n+\tstruct ralink_gpio_chip *rg = to_ralink_gpio(chip);\n+\n+\trt_gpio_w32(rg, (value) ? GPIO_REG_SET : GPIO_REG_RESET, BIT(offset));\n+}\n+\n+static int ralink_gpio_get(struct gpio_chip *chip, unsigned offset)\n+{\n+\tstruct ralink_gpio_chip *rg = to_ralink_gpio(chip);\n+\n+\treturn !!(rt_gpio_r32(rg, GPIO_REG_DATA) & BIT(offset));\n+}\n+\n+static int ralink_gpio_direction_input(struct gpio_chip *chip, unsigned offset)\n+{\n+\tstruct ralink_gpio_chip *rg = to_ralink_gpio(chip);\n+\tunsigned long flags;\n+\tu32 t;\n+\n+\tspin_lock_irqsave(&rg->lock, flags);\n+\tt = rt_gpio_r32(rg, GPIO_REG_DIR);\n+\tt &= ~BIT(offset);\n+\trt_gpio_w32(rg, GPIO_REG_DIR, t);\n+\tspin_unlock_irqrestore(&rg->lock, flags);\n+\n+\treturn 0;\n+}\n+\n+static int ralink_gpio_direction_output(struct gpio_chip *chip,\n+\t\t\t\t\tunsigned offset, int value)\n+{\n+\tstruct ralink_gpio_chip *rg = to_ralink_gpio(chip);\n+\tunsigned long flags;\n+\tu32 t;\n+\n+\tspin_lock_irqsave(&rg->lock, flags);\n+\tralink_gpio_set(chip, offset, value);\n+\tt = rt_gpio_r32(rg, GPIO_REG_DIR);\n+\tt |= BIT(offset);\n+\trt_gpio_w32(rg, GPIO_REG_DIR, t);\n+\tspin_unlock_irqrestore(&rg->lock, flags);\n+\n+\treturn 0;\n+}\n+\n+static int ralink_gpio_to_irq(struct gpio_chip *chip, unsigned pin)\n+{\n+\tstruct ralink_gpio_chip *rg = to_ralink_gpio(chip);\n+\n+\tif (rg->irq < 1)\n+\t\treturn -1;\n+\n+\treturn irq_create_mapping(rg->domain, pin);\n+}\n+\n+static void ralink_gpio_irq_handler(struct irq_desc *desc)\n+{\n+\tint i;\n+\n+\tfor (i = 0; i < irq_map_count; i++) {\n+\t\tstruct irq_domain *domain = irq_map[i];\n+\t\tstruct ralink_gpio_chip *rg;\n+\t\tunsigned long pending;\n+\t\tint bit;\n+\n+\t\trg = (struct ralink_gpio_chip *) domain->host_data;\n+\t\tpending = rt_gpio_r32(rg, GPIO_REG_INT);\n+\n+\t\tfor_each_set_bit(bit, &pending, rg->chip.ngpio) {\n+\t\t\tu32 map = irq_find_mapping(domain, bit);\n+\t\t\tgeneric_handle_irq(map);\n+\t\t\trt_gpio_w32(rg, GPIO_REG_INT, BIT(bit));\n+\t\t}\n+\t}\n+}\n+\n+static void ralink_gpio_irq_unmask(struct irq_data *d)\n+{\n+\tstruct ralink_gpio_chip *rg;\n+\tunsigned long flags;\n+\tu32 rise, fall;\n+\n+\trg = (struct ralink_gpio_chip *) d->domain->host_data;\n+\trise = rt_gpio_r32(rg, GPIO_REG_RENA);\n+\tfall = rt_gpio_r32(rg, GPIO_REG_FENA);\n+\n+\tspin_lock_irqsave(&rg->lock, flags);\n+\trt_gpio_w32(rg, GPIO_REG_RENA, rise | (BIT(d->hwirq) & rg->rising));\n+\trt_gpio_w32(rg, GPIO_REG_FENA, fall | (BIT(d->hwirq) & rg->falling));\n+\tspin_unlock_irqrestore(&rg->lock, flags);\n+}\n+\n+static void ralink_gpio_irq_mask(struct irq_data *d)\n+{\n+\tstruct ralink_gpio_chip *rg;\n+\tunsigned long flags;\n+\tu32 rise, fall;\n+\n+\trg = (struct ralink_gpio_chip *) d->domain->host_data;\n+\trise = rt_gpio_r32(rg, GPIO_REG_RENA);\n+\tfall = rt_gpio_r32(rg, GPIO_REG_FENA);\n+\n+\tspin_lock_irqsave(&rg->lock, flags);\n+\trt_gpio_w32(rg, GPIO_REG_FENA, fall & ~BIT(d->hwirq));\n+\trt_gpio_w32(rg, GPIO_REG_RENA, rise & ~BIT(d->hwirq));\n+\tspin_unlock_irqrestore(&rg->lock, flags);\n+}\n+\n+static int ralink_gpio_irq_type(struct irq_data *d, unsigned int type)\n+{\n+\tstruct ralink_gpio_chip *rg;\n+\tu32 mask = BIT(d->hwirq);\n+\n+\trg = (struct ralink_gpio_chip *) d->domain->host_data;\n+\n+\tif (type == IRQ_TYPE_PROBE) {\n+\t\tif ((rg->rising | rg->falling) & mask)\n+\t\t\treturn 0;\n+\n+\t\ttype = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;\n+\t}\n+\n+\tif (type & IRQ_TYPE_EDGE_RISING)\n+\t\trg->rising |= mask;\n+\telse\n+\t\trg->rising &= ~mask;\n+\n+\tif (type & IRQ_TYPE_EDGE_FALLING)\n+\t\trg->falling |= mask;\n+\telse\n+\t\trg->falling &= ~mask;\n+\n+\treturn 0;\n+}\n+\n+static struct irq_chip ralink_gpio_irq_chip = {\n+\t.name\t\t= \"GPIO\",\n+\t.irq_unmask\t= ralink_gpio_irq_unmask,\n+\t.irq_mask\t= ralink_gpio_irq_mask,\n+\t.irq_mask_ack\t= ralink_gpio_irq_mask,\n+\t.irq_set_type\t= ralink_gpio_irq_type,\n+};\n+\n+static int gpio_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)\n+{\n+\tirq_set_chip_and_handler(irq, &ralink_gpio_irq_chip, handle_level_irq);\n+\tirq_set_handler_data(irq, d);\n+\n+\treturn 0;\n+}\n+\n+static const struct irq_domain_ops irq_domain_ops = {\n+\t.xlate = irq_domain_xlate_onecell,\n+\t.map = gpio_map,\n+};\n+\n+static void ralink_gpio_irq_init(struct device_node *np,\n+\t\t\t\t struct ralink_gpio_chip *rg)\n+{\n+\tif (irq_map_count >= MAP_MAX)\n+\t\treturn;\n+\n+\trg->irq = irq_of_parse_and_map(np, 0);\n+\tif (!rg->irq)\n+\t\treturn;\n+\n+\trg->domain = irq_domain_add_linear(np, rg->chip.ngpio,\n+\t\t\t\t\t   &irq_domain_ops, rg);\n+\tif (!rg->domain) {\n+\t\tdev_err(rg->chip.parent, \"irq_domain_add_linear failed\\n\");\n+\t\treturn;\n+\t}\n+\n+\tirq_map[irq_map_count++] = rg->domain;\n+\n+\trt_gpio_w32(rg, GPIO_REG_RENA, 0x0);\n+\trt_gpio_w32(rg, GPIO_REG_FENA, 0x0);\n+\n+\tif (!atomic_read(&irq_refcount))\n+\t\tirq_set_chained_handler(rg->irq, ralink_gpio_irq_handler);\n+\tatomic_inc(&irq_refcount);\n+\n+\tdev_info(rg->chip.parent, \"registering %d irq handlers\\n\", rg->chip.ngpio);\n+}\n+\n+static int ralink_gpio_probe(struct platform_device *pdev)\n+{\n+\tstruct device_node *np = pdev->dev.of_node;\n+\tstruct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);\n+\tstruct ralink_gpio_chip *rg;\n+\tconst __be32 *ngpio, *gpiobase;\n+\n+\tif (!res) {\n+\t\tdev_err(&pdev->dev, \"failed to find resource\\n\");\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\trg = devm_kzalloc(&pdev->dev,\n+\t\t\tsizeof(struct ralink_gpio_chip), GFP_KERNEL);\n+\tif (!rg)\n+\t\treturn -ENOMEM;\n+\n+\trg->membase = devm_ioremap_resource(&pdev->dev, res);\n+\tif (!rg->membase) {\n+\t\tdev_err(&pdev->dev, \"cannot remap I/O memory region\\n\");\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\tif (of_property_read_u8_array(np, \"ralink,register-map\",\n+\t\t\trg->regs, GPIO_REG_MAX)) {\n+\t\tdev_err(&pdev->dev, \"failed to read register definition\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tngpio = of_get_property(np, \"ngpios\", NULL);\n+\tif (!ngpio) {\n+\t\tdev_err(&pdev->dev, \"failed to read number of pins\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tgpiobase = of_get_property(np, \"ralink,gpio-base\", NULL);\n+\tif (gpiobase)\n+\t\trg->chip.base = be32_to_cpu(*gpiobase);\n+\telse\n+\t\trg->chip.base = -1;\n+\n+\tspin_lock_init(&rg->lock);\n+\n+\trg->chip.parent = &pdev->dev;\n+\trg->chip.label = dev_name(&pdev->dev);\n+\trg->chip.of_node = np;\n+\trg->chip.ngpio = be32_to_cpu(*ngpio);\n+\trg->chip.direction_input = ralink_gpio_direction_input;\n+\trg->chip.direction_output = ralink_gpio_direction_output;\n+\trg->chip.get = ralink_gpio_get;\n+\trg->chip.set = ralink_gpio_set;\n+\trg->chip.request = gpiochip_generic_request;\n+\trg->chip.to_irq = ralink_gpio_to_irq;\n+\trg->chip.free = gpiochip_generic_free;\n+\n+\t/* set polarity to low for all lines */\n+\trt_gpio_w32(rg, GPIO_REG_POL, 0);\n+\n+\tdev_info(&pdev->dev, \"registering %d gpios\\n\", rg->chip.ngpio);\n+\n+\tralink_gpio_irq_init(np, rg);\n+\n+\treturn gpiochip_add(&rg->chip);\n+}\n+\n+static const struct of_device_id ralink_gpio_match[] = {\n+\t{ .compatible = \"ralink,rt2880-gpio\" },\n+\t{},\n+};\n+MODULE_DEVICE_TABLE(of, ralink_gpio_match);\n+\n+static struct platform_driver ralink_gpio_driver = {\n+\t.probe = ralink_gpio_probe,\n+\t.driver = {\n+\t\t.name = \"rt2880_gpio\",\n+\t\t.owner = THIS_MODULE,\n+\t\t.of_match_table = ralink_gpio_match,\n+\t},\n+};\n+\n+static int __init ralink_gpio_init(void)\n+{\n+\treturn platform_driver_register(&ralink_gpio_driver);\n+}\n+\n+subsys_initcall(ralink_gpio_init);\n"
  },
  {
    "path": "target/linux/ramips/patches-5.10/803-gpio-ralink-Add-support-for-GPIO-as-interrupt-contro.patch",
    "content": "From 57fa7f2f4ef6f78ce1d30509c0d111aa3791b524 Mon Sep 17 00:00:00 2001\nFrom: Daniel Santos <daniel.santos@pobox.com>\nDate: Sun, 4 Nov 2018 20:24:32 -0600\nSubject: gpio-ralink: Add support for GPIO as interrupt-controller\n\nSigned-off-by: Daniel Santos <daniel.santos@pobox.com>\n---\n Documentation/devicetree/bindings/gpio/gpio-ralink.txt | 6 ++++++\n drivers/gpio/gpio-ralink.c                             | 2 +-\n 2 files changed, 7 insertions(+), 1 deletion(-)\n\n--- a/Documentation/devicetree/bindings/gpio/gpio-ralink.txt\n+++ b/Documentation/devicetree/bindings/gpio/gpio-ralink.txt\n@@ -17,6 +17,9 @@ Required properties:\n \n Optional properties:\n - ralink,gpio-base : Specify the GPIO chips base number\n+- interrupt-controller : marks this as an interrupt controller\n+- #interrupt-cells : a standard two-cell interrupt flag, see\n+  interrupt-controller/interrupts.txt\n \n Example:\n \n@@ -28,6 +31,9 @@ Example:\n \n \t\treg = <0x600 0x34>;\n \n+\t\tinterrupt-controller;\n+\t\t#interrupt-cells = <2>;\n+\n \t\tinterrupt-parent = <&intc>;\n \t\tinterrupts = <6>;\n \n--- a/drivers/gpio/gpio-ralink.c\n+++ b/drivers/gpio/gpio-ralink.c\n@@ -220,7 +220,7 @@ static int gpio_map(struct irq_domain *d\n }\n \n static const struct irq_domain_ops irq_domain_ops = {\n-\t.xlate = irq_domain_xlate_onecell,\n+\t.xlate = irq_domain_xlate_twocell,\n \t.map = gpio_map,\n };\n \n"
  },
  {
    "path": "target/linux/ramips/patches-5.10/804-staging-mt7621-pinctrl-use-ngpios-not-num-gpios.patch",
    "content": "--- a/drivers/staging/mt7621-pinctrl/pinctrl-rt2880.c\n+++ b/drivers/staging/mt7621-pinctrl/pinctrl-rt2880.c\n@@ -354,7 +354,7 @@ static int rt2880_pinmux_probe(struct pl\n \t\tif (!of_device_is_available(np))\n \t\t\tcontinue;\n \n-\t\tngpio = of_get_property(np, \"ralink,num-gpios\", NULL);\n+\t\tngpio = of_get_property(np, \"ngpios\", NULL);\n \t\tgpiobase = of_get_property(np, \"ralink,gpio-base\", NULL);\n \t\tif (!ngpio || !gpiobase) {\n \t\t\tdev_err(&pdev->dev, \"failed to load chip info\\n\");\n"
  },
  {
    "path": "target/linux/ramips/patches-5.10/805-pinctrl-AW9523.patch",
    "content": "From: AngeloGioacchino Del Regno\n        <angelogioacchino.delregno@somainline.org>\nTo: linus.walleij@linaro.org\nCc: linux-kernel@vger.kernel.org, konrad.dybcio@somainline.org,\n        marijn.suijten@somainline.org, martin.botka@somainline.org,\n        phone-devel@vger.kernel.org, linux-gpio@vger.kernel.org,\n        devicetree@vger.kernel.org, robh+dt@kernel.org,\n        AngeloGioacchino Del Regno\n        <angelogioacchino.delregno@somainline.org>\nSubject: [PATCH v5 1/2] pinctrl: Add driver for Awinic AW9523/B I2C GPIO\n Expander\nDate: Mon, 25 Jan 2021 19:22:18 +0100\n\nThe Awinic AW9523(B) is a multi-function I2C gpio expander in a\nTQFN-24L package, featuring PWM (max 37mA per pin, or total max\npower 3.2Watts) for LED driving capability.\n\nIt has two ports with 8 pins per port (for a total of 16 pins),\nconfigurable as either PWM with 1/256 stepping or GPIO input/output,\n1.8V logic input; each GPIO can be configured as input or output\nindependently from each other.\n\nThis IC also has an internal interrupt controller, which is capable\nof generating an interrupt for each GPIO, depending on the\nconfiguration, and will raise an interrupt on the INTN pin to\nadvertise this to an external interrupt controller.\n\nSigned-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>\n---\n drivers/pinctrl/Kconfig          |   17 +\n drivers/pinctrl/Makefile         |    1 +\n drivers/pinctrl/pinctrl-aw9523.c | 1122 ++++++++++++++++++++++++++++++\n 3 files changed, 1140 insertions(+)\n create mode 100644 drivers/pinctrl/pinctrl-aw9523.c\n\n--- a/drivers/pinctrl/Kconfig\n+++ b/drivers/pinctrl/Kconfig\n@@ -110,6 +110,24 @@ config PINCTRL_AMD\n \t  Requires ACPI/FDT device enumeration code to set up a platform\n \t  device.\n \n+config PINCTRL_AW9523\n+\tbool \"Awinic AW9523/AW9523B I2C GPIO expander pinctrl driver\"\n+\tdepends on OF && I2C\n+\tselect PINMUX\n+\tselect PINCONF\n+\tselect GENERIC_PINCONF\n+\tselect GPIOLIB\n+\tselect GPIOLIB_IRQCHIP\n+\tselect REGMAP\n+\tselect REGMAP_I2C\n+\thelp\n+\t  The Awinic AW9523/AW9523B is a multi-function I2C GPIO\n+\t  expander with PWM functionality. This driver bundles a\n+\t  pinctrl driver to select the function muxing and a GPIO\n+\t  driver to handle GPIO, when the GPIO function is selected.\n+\n+\t  Say yes to enable pinctrl and GPIO support for the AW9523(B).\n+\n config PINCTRL_BM1880\n \tbool \"Bitmain BM1880 Pinctrl driver\"\n \tdepends on OF && (ARCH_BITMAIN || COMPILE_TEST)\n--- a/drivers/pinctrl/Makefile\n+++ b/drivers/pinctrl/Makefile\n@@ -14,6 +14,7 @@ obj-$(CONFIG_PINCTRL_AXP209)\t+= pinctrl-\n obj-$(CONFIG_PINCTRL_AT91)\t+= pinctrl-at91.o\n obj-$(CONFIG_PINCTRL_AT91PIO4)\t+= pinctrl-at91-pio4.o\n obj-$(CONFIG_PINCTRL_AMD)\t+= pinctrl-amd.o\n+obj-$(CONFIG_PINCTRL_AW9523)\t+= pinctrl-aw9523.o\n obj-$(CONFIG_PINCTRL_BM1880)\t+= pinctrl-bm1880.o\n obj-$(CONFIG_PINCTRL_DA850_PUPD) += pinctrl-da850-pupd.o\n obj-$(CONFIG_PINCTRL_DA9062)\t+= pinctrl-da9062.o\n"
  },
  {
    "path": "target/linux/ramips/patches-5.10/810-uvc-add-iPassion-iP2970-support.patch",
    "content": "From 975e76214cd2516eb6cfff4c3eec581872645e88 Mon Sep 17 00:00:00 2001\nFrom: John Crispin <blogic@openwrt.org>\nDate: Thu, 19 Sep 2013 01:50:59 +0200\nSubject: [PATCH 31/53] uvc: add iPassion iP2970 support\n\nSigned-off-by: John Crispin <blogic@openwrt.org>\n---\n drivers/media/usb/uvc/uvc_driver.c |   12 +++\n drivers/media/usb/uvc/uvc_status.c |    2 +\n drivers/media/usb/uvc/uvc_video.c  |  147 ++++++++++++++++++++++++++++++++++++\n drivers/media/usb/uvc/uvcvideo.h   |    5 +-\n 4 files changed, 165 insertions(+), 1 deletion(-)\n\n--- a/drivers/media/usb/uvc/uvc_driver.c\n+++ b/drivers/media/usb/uvc/uvc_driver.c\n@@ -3004,6 +3004,18 @@ static const struct usb_device_id uvc_id\n \t  .bInterfaceSubClass\t= 1,\n \t  .bInterfaceProtocol\t= 0,\n \t  .driver_info\t\t= UVC_INFO_META(V4L2_META_FMT_D4XX) },\n+\t/* iPassion iP2970 */\n+\t{ .match_flags          = USB_DEVICE_ID_MATCH_DEVICE\n+\t\t\t\t| USB_DEVICE_ID_MATCH_INT_INFO,\n+\t .idVendor\t\t= 0x1B3B,\n+\t .idProduct\t\t= 0x2970,\n+\t .bInterfaceClass\t= USB_CLASS_VIDEO,\n+\t .bInterfaceSubClass\t= 1,\n+\t .bInterfaceProtocol\t= 0,\n+\t .driver_info\t\t= UVC_QUIRK_PROBE_MINMAX\n+\t\t\t\t| UVC_QUIRK_STREAM_NO_FID\n+\t\t\t\t| UVC_QUIRK_MOTION\n+\t\t\t\t| UVC_QUIRK_SINGLE_ISO },\n \t/* Generic USB Video Class */\n \t{ USB_INTERFACE_INFO(USB_CLASS_VIDEO, 1, UVC_PC_PROTOCOL_UNDEFINED) },\n \t{ USB_INTERFACE_INFO(USB_CLASS_VIDEO, 1, UVC_PC_PROTOCOL_15) },\n--- a/drivers/media/usb/uvc/uvc_status.c\n+++ b/drivers/media/usb/uvc/uvc_status.c\n@@ -223,6 +223,7 @@ static void uvc_status_complete(struct u\n \t\t\tif (uvc_event_control(urb, status, len))\n \t\t\t\t/* The URB will be resubmitted in work context. */\n \t\t\t\treturn;\n+\t\t\tdev->motion = 1;\n \t\t\tbreak;\n \t\t}\n \n@@ -271,6 +272,7 @@ int uvc_status_init(struct uvc_device *d\n \t}\n \n \tpipe = usb_rcvintpipe(dev->udev, ep->desc.bEndpointAddress);\n+\tdev->motion = 0;\n \n \t/* For high-speed interrupt endpoints, the bInterval value is used as\n \t * an exponent of two. Some developers forgot about it.\n--- a/drivers/media/usb/uvc/uvc_video.c\n+++ b/drivers/media/usb/uvc/uvc_video.c\n@@ -16,6 +16,11 @@\n #include <linux/wait.h>\n #include <linux/atomic.h>\n #include <asm/unaligned.h>\n+#include <linux/skbuff.h>\n+#include <linux/kobject.h>\n+#include <linux/netlink.h>\n+#include <linux/kobject.h>\n+#include <linux/workqueue.h>\n \n #include <media/v4l2-common.h>\n \n@@ -1188,9 +1193,149 @@ static void uvc_video_decode_data(struct\n \tuvc_urb->async_operations++;\n }\n \n+struct bh_priv {\n+\tunsigned long\tseen;\n+};\n+\n+struct bh_event {\n+\tconst char\t\t*name;\n+\tstruct sk_buff\t\t*skb;\n+\tstruct work_struct\twork;\n+};\n+\n+#define BH_ERR(fmt, args...) printk(KERN_ERR \"%s: \" fmt, \"webcam\", ##args )\n+#define BH_DBG(fmt, args...) do {} while (0)\n+#define BH_SKB_SIZE     2048\n+\n+extern u64 uevent_next_seqnum(void);\n+static int seen = 0;\n+\n+static int bh_event_add_var(struct bh_event *event, int argv,\n+\t\tconst char *format, ...)\n+{\n+\tstatic char buf[128];\n+\tchar *s;\n+\tva_list args;\n+\tint len;\n+\n+\tif (argv)\n+\t\treturn 0;\n+\n+\tva_start(args, format);\n+\tlen = vsnprintf(buf, sizeof(buf), format, args);\n+\tva_end(args);\n+\n+\tif (len >= sizeof(buf)) {\n+\t\tBH_ERR(\"buffer size too small\\n\");\n+\t\tWARN_ON(1);\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\ts = skb_put(event->skb, len + 1);\n+\tstrcpy(s, buf);\n+\n+\tBH_DBG(\"added variable '%s'\\n\", s);\n+\n+\treturn 0;\n+}\n+\n+static int motion_hotplug_fill_event(struct bh_event *event)\n+{\n+\tint s = jiffies;\n+\tint ret;\n+\n+\tif (!seen)\n+\t\tseen = jiffies;\n+\n+\tret = bh_event_add_var(event, 0, \"HOME=%s\", \"/\");\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = bh_event_add_var(event, 0, \"PATH=%s\",\n+\t\t\"/sbin:/bin:/usr/sbin:/usr/bin\");\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = bh_event_add_var(event, 0, \"SUBSYSTEM=usb\");\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = bh_event_add_var(event, 0, \"ACTION=motion\");\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = bh_event_add_var(event, 0, \"SEEN=%d\", s - seen);\n+\tif (ret)\n+\t\treturn ret;\n+\tseen = s;\n+\n+\tret = bh_event_add_var(event, 0, \"SEQNUM=%llu\", uevent_next_seqnum());\n+\n+\treturn ret;\n+}\n+\n+static void motion_hotplug_work(struct work_struct *work)\n+{\n+\tstruct bh_event *event = container_of(work, struct bh_event, work);\n+\tint ret = 0;\n+\n+\tevent->skb = alloc_skb(BH_SKB_SIZE, GFP_KERNEL);\n+\tif (!event->skb)\n+\t\tgoto out_free_event;\n+\n+\tret = bh_event_add_var(event, 0, \"%s@\", \"add\");\n+\tif (ret)\n+\t\tgoto out_free_skb;\n+\n+\tret = motion_hotplug_fill_event(event);\n+\tif (ret)\n+\t\tgoto out_free_skb;\n+\n+\tNETLINK_CB(event->skb).dst_group = 1;\n+\tbroadcast_uevent(event->skb, 0, 1, GFP_KERNEL);\n+\n+out_free_skb:\n+\tif (ret) {\n+\t\tBH_ERR(\"work error %d\\n\", ret);\n+\t\tkfree_skb(event->skb);\n+\t}\n+out_free_event:\n+\tkfree(event);\n+}\n+\n+static int motion_hotplug_create_event(void)\n+{\n+\tstruct bh_event *event;\n+\n+\tevent = kzalloc(sizeof(*event), GFP_KERNEL);\n+\tif (!event)\n+\t\treturn -ENOMEM;\n+\n+\tevent->name = \"motion\";\n+\n+\tINIT_WORK(&event->work, (void *)(void *)motion_hotplug_work);\n+\tschedule_work(&event->work);\n+\n+\treturn 0;\n+}\n+\n+#define MOTION_FLAG_OFFSET\t4\n static void uvc_video_decode_end(struct uvc_streaming *stream,\n \t\tstruct uvc_buffer *buf, const u8 *data, int len)\n {\n+\tif ((stream->dev->quirks & UVC_QUIRK_MOTION) &&\n+\t\t\t(data[len - 2] == 0xff) && (data[len - 1] == 0xd9)) {\n+\t\tu8 *mem;\n+\t\tbuf->state = UVC_BUF_STATE_READY;\n+\t\tmem = (u8 *) (buf->mem + MOTION_FLAG_OFFSET);\n+\t\tif ( stream->dev->motion ) {\n+\t\t\tstream->dev->motion = 0;\n+\t\t\tmotion_hotplug_create_event();\n+\t\t} else {\n+\t\t\t*mem &= 0x7f;\n+\t\t}\n+\t}\n+\n \t/* Mark the buffer as done if the EOF marker is set. */\n \tif (data[1] & UVC_STREAM_EOF && buf->bytesused != 0) {\n \t\tuvc_trace(UVC_TRACE_FRAME, \"Frame complete (EOF found).\\n\");\n@@ -1747,6 +1892,8 @@ static int uvc_init_video_isoc(struct uv\n \tif (npackets == 0)\n \t\treturn -ENOMEM;\n \n+\tif (stream->dev->quirks & UVC_QUIRK_SINGLE_ISO)\n+\t\tnpackets = 1;\n \tsize = npackets * psize;\n \n \tfor_each_uvc_urb(uvc_urb, stream) {\n--- a/drivers/media/usb/uvc/uvcvideo.h\n+++ b/drivers/media/usb/uvc/uvcvideo.h\n@@ -203,7 +203,9 @@\n #define UVC_QUIRK_RESTORE_CTRLS_ON_INIT\t0x00000400\n #define UVC_QUIRK_FORCE_Y8\t\t0x00000800\n #define UVC_QUIRK_FORCE_BPP\t\t0x00001000\n-\n+#define UVC_QUIRK_MOTION\t\t0x00001000\n+#define UVC_QUIRK_SINGLE_ISO\t\t0x00002000\n+ \n /* Format flags */\n #define UVC_FMT_FLAG_COMPRESSED\t\t0x00000001\n #define UVC_FMT_FLAG_STREAM\t\t0x00000002\n@@ -672,6 +674,7 @@ struct uvc_device {\n \tu8 *status;\n \tstruct input_dev *input;\n \tchar input_phys[64];\n+\tint motion;\n \n \tstruct uvc_ctrl_work {\n \t\tstruct work_struct work;\n"
  },
  {
    "path": "target/linux/ramips/patches-5.10/820-DT-Add-documentation-for-spi-rt2880.patch",
    "content": "From da6015e7f19d749f135f7ac55c4ec47b06faa868 Mon Sep 17 00:00:00 2001\nFrom: John Crispin <blogic@openwrt.org>\nDate: Fri, 9 Aug 2013 20:12:59 +0200\nSubject: [PATCH 41/53] DT: Add documentation for spi-rt2880\n\nDescribe the SPI master found on the MIPS based Ralink RT2880 SoC.\n\nSigned-off-by: John Crispin <blogic@openwrt.org>\n---\n .../devicetree/bindings/spi/spi-rt2880.txt         |   28 ++++++++++++++++++++\n 1 file changed, 28 insertions(+)\n create mode 100644 Documentation/devicetree/bindings/spi/spi-rt2880.txt\n\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/spi/spi-rt2880.txt\n@@ -0,0 +1,28 @@\n+Ralink SoC RT2880 SPI master controller.\n+\n+This SPI controller is found on most wireless SoCs made by ralink.\n+\n+Required properties:\n+- compatible : \"ralink,rt2880-spi\"\n+- reg : The register base for the controller.\n+- #address-cells : <1>, as required by generic SPI binding.\n+- #size-cells : <0>, also as required by generic SPI binding.\n+\n+Child nodes as per the generic SPI binding.\n+\n+Example:\n+\n+\tspi@b00 {\n+\t\tcompatible = \"ralink,rt2880-spi\";\n+\t\treg = <0xb00 0x100>;\n+\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\n+\t\tm25p80@0 {\n+\t\t\tcompatible = \"m25p80\";\n+\t\t\treg = <0>;\n+\t\t\tspi-max-frequency = <10000000>;\n+\t\t};\n+\t};\n+\n"
  },
  {
    "path": "target/linux/ramips/patches-5.10/821-SPI-ralink-add-Ralink-SoC-spi-driver.patch",
    "content": "From 683af4ebb91a1600df1946ac4769d916b8a1be65 Mon Sep 17 00:00:00 2001\nFrom: John Crispin <blogic@openwrt.org>\nDate: Sun, 27 Jul 2014 11:15:12 +0100\nSubject: [PATCH 42/53] SPI: ralink: add Ralink SoC spi driver\n\nAdd the driver needed to make SPI work on Ralink SoC.\n\nSigned-off-by: Gabor Juhos <juhosg@openwrt.org>\nAcked-by: John Crispin <blogic@openwrt.org>\n---\n drivers/spi/Kconfig      |    6 +\n drivers/spi/Makefile     |    1 +\n drivers/spi/spi-rt2880.c |  530 ++++++++++++++++++++++++++++++++++++++++++++++\n 3 files changed, 537 insertions(+)\n create mode 100644 drivers/spi/spi-rt2880.c\n\n--- a/drivers/spi/Kconfig\n+++ b/drivers/spi/Kconfig\n@@ -689,6 +689,12 @@ config SPI_QCOM_GENI\n \t  This driver can also be built as a module.  If so, the module\n \t  will be called spi-geni-qcom.\n \n+config SPI_RT2880\n+\ttristate \"Ralink RT288x SPI Controller\"\n+\tdepends on RALINK\n+\thelp\n+\t  This selects a driver for the Ralink RT288x/RT305x SPI Controller.\n+\n config SPI_S3C24XX\n \ttristate \"Samsung S3C24XX series SPI\"\n \tdepends on ARCH_S3C24XX\n--- a/drivers/spi/Makefile\n+++ b/drivers/spi/Makefile\n@@ -96,6 +96,7 @@ obj-$(CONFIG_SPI_ROCKCHIP)\t\t+= spi-rockc\n obj-$(CONFIG_SPI_RB4XX)\t\t\t+= spi-rb4xx.o\n obj-$(CONFIG_SPI_RPCIF)\t\t\t+= spi-rpc-if.o\n obj-$(CONFIG_SPI_RSPI)\t\t\t+= spi-rspi.o\n+obj-$(CONFIG_SPI_RT2880)\t\t+= spi-rt2880.o\n obj-$(CONFIG_SPI_S3C24XX)\t\t+= spi-s3c24xx-hw.o\n spi-s3c24xx-hw-y\t\t\t:= spi-s3c24xx.o\n obj-$(CONFIG_SPI_S3C64XX)\t\t+= spi-s3c64xx.o\n--- /dev/null\n+++ b/drivers/spi/spi-rt2880.c\n@@ -0,0 +1,530 @@\n+/*\n+ * spi-rt2880.c -- Ralink RT288x/RT305x SPI controller driver\n+ *\n+ * Copyright (C) 2011 Sergiy <piratfm@gmail.com>\n+ * Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>\n+ *\n+ * Some parts are based on spi-orion.c:\n+ *   Author: Shadi Ammouri <shadi@marvell.com>\n+ *   Copyright (C) 2007-2008 Marvell Ltd.\n+ *\n+ * This program is free software; you can redistribute it and/or modify\n+ * it under the terms of the GNU General Public License version 2 as\n+ * published by the Free Software Foundation.\n+ */\n+\n+#include <linux/init.h>\n+#include <linux/module.h>\n+#include <linux/clk.h>\n+#include <linux/err.h>\n+#include <linux/delay.h>\n+#include <linux/io.h>\n+#include <linux/reset.h>\n+#include <linux/spi/spi.h>\n+#include <linux/platform_device.h>\n+#include <linux/gpio.h>\n+\n+#define DRIVER_NAME\t\t\t\"spi-rt2880\"\n+\n+#define RAMIPS_SPI_STAT\t\t\t0x00\n+#define RAMIPS_SPI_CFG\t\t\t0x10\n+#define RAMIPS_SPI_CTL\t\t\t0x14\n+#define RAMIPS_SPI_DATA\t\t\t0x20\n+#define RAMIPS_SPI_ADDR\t\t\t0x24\n+#define RAMIPS_SPI_BS\t\t\t0x28\n+#define RAMIPS_SPI_USER\t\t\t0x2C\n+#define RAMIPS_SPI_TXFIFO\t\t0x30\n+#define RAMIPS_SPI_RXFIFO\t\t0x34\n+#define RAMIPS_SPI_FIFO_STAT\t\t0x38\n+#define RAMIPS_SPI_MODE\t\t\t0x3C\n+#define RAMIPS_SPI_DEV_OFFSET\t\t0x40\n+#define RAMIPS_SPI_DMA\t\t\t0x80\n+#define RAMIPS_SPI_DMASTAT\t\t0x84\n+#define RAMIPS_SPI_ARBITER\t\t0xF0\n+\n+/* SPISTAT register bit field */\n+#define SPISTAT_BUSY\t\t\tBIT(0)\n+\n+/* SPICFG register bit field */\n+#define SPICFG_ADDRMODE\t\t\tBIT(12)\n+#define SPICFG_RXENVDIS\t\t\tBIT(11)\n+#define SPICFG_RXCAP\t\t\tBIT(10)\n+#define SPICFG_SPIENMODE\t\tBIT(9)\n+#define SPICFG_MSBFIRST\t\t\tBIT(8)\n+#define SPICFG_SPICLKPOL\t\tBIT(6)\n+#define SPICFG_RXCLKEDGE_FALLING\tBIT(5)\n+#define SPICFG_TXCLKEDGE_FALLING\tBIT(4)\n+#define SPICFG_HIZSPI\t\t\tBIT(3)\n+#define SPICFG_SPICLK_PRESCALE_MASK\t0x7\n+#define SPICFG_SPICLK_DIV2\t\t0\n+#define SPICFG_SPICLK_DIV4\t\t1\n+#define SPICFG_SPICLK_DIV8\t\t2\n+#define SPICFG_SPICLK_DIV16\t\t3\n+#define SPICFG_SPICLK_DIV32\t\t4\n+#define SPICFG_SPICLK_DIV64\t\t5\n+#define SPICFG_SPICLK_DIV128\t\t6\n+#define SPICFG_SPICLK_DISABLE\t\t7\n+\n+/* SPICTL register bit field */\n+#define SPICTL_START\t\t\tBIT(4)\n+#define SPICTL_HIZSDO\t\t\tBIT(3)\n+#define SPICTL_STARTWR\t\t\tBIT(2)\n+#define SPICTL_STARTRD\t\t\tBIT(1)\n+#define SPICTL_SPIENA\t\t\tBIT(0)\n+\n+/* SPIUSER register bit field */\n+#define SPIUSER_USERMODE\t\tBIT(21)\n+#define SPIUSER_INSTR_PHASE\t\tBIT(20)\n+#define SPIUSER_ADDR_PHASE_MASK\t\t0x7\n+#define SPIUSER_ADDR_PHASE_OFFSET\t17\n+#define SPIUSER_MODE_PHASE\t\tBIT(16)\n+#define SPIUSER_DUMMY_PHASE_MASK\t0x3\n+#define SPIUSER_DUMMY_PHASE_OFFSET\t14\n+#define SPIUSER_DATA_PHASE_MASK\t\t0x3\n+#define SPIUSER_DATA_PHASE_OFFSET\t12\n+#define SPIUSER_DATA_READ\t\t(BIT(0) << SPIUSER_DATA_PHASE_OFFSET)\n+#define SPIUSER_DATA_WRITE\t\t(BIT(1) << SPIUSER_DATA_PHASE_OFFSET)\n+#define SPIUSER_ADDR_TYPE_OFFSET\t9\n+#define SPIUSER_MODE_TYPE_OFFSET\t6\n+#define SPIUSER_DUMMY_TYPE_OFFSET\t3\n+#define SPIUSER_DATA_TYPE_OFFSET\t0\n+#define SPIUSER_TRANSFER_MASK\t\t0x7\n+#define SPIUSER_TRANSFER_SINGLE\t\tBIT(0)\n+#define SPIUSER_TRANSFER_DUAL\t\tBIT(1)\n+#define SPIUSER_TRANSFER_QUAD\t\tBIT(2)\n+\n+#define SPIUSER_TRANSFER_TYPE(type) ( \\\n+\t(type << SPIUSER_ADDR_TYPE_OFFSET) | \\\n+\t(type << SPIUSER_MODE_TYPE_OFFSET) | \\\n+\t(type << SPIUSER_DUMMY_TYPE_OFFSET) | \\\n+\t(type << SPIUSER_DATA_TYPE_OFFSET) \\\n+)\n+\n+/* SPIFIFOSTAT register bit field */\n+#define SPIFIFOSTAT_TXEMPTY\t\tBIT(19)\n+#define SPIFIFOSTAT_RXEMPTY\t\tBIT(18)\n+#define SPIFIFOSTAT_TXFULL\t\tBIT(17)\n+#define SPIFIFOSTAT_RXFULL\t\tBIT(16)\n+#define SPIFIFOSTAT_FIFO_MASK\t\t0xff\n+#define SPIFIFOSTAT_TX_OFFSET\t\t8\n+#define SPIFIFOSTAT_RX_OFFSET\t\t0\n+\n+#define SPI_FIFO_DEPTH\t\t\t16\n+\n+/* SPIMODE register bit field */\n+#define SPIMODE_MODE_OFFSET\t\t24\n+#define SPIMODE_DUMMY_OFFSET\t\t0\n+\n+/* SPIARB register bit field */\n+#define SPICTL_ARB_EN\t\t\tBIT(31)\n+#define SPICTL_CSCTL1\t\t\tBIT(16)\n+#define SPI1_POR\t\t\tBIT(1)\n+#define SPI0_POR\t\t\tBIT(0)\n+\n+#define RT2880_SPI_MODE_BITS\t(SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | \\\n+\t\tSPI_CS_HIGH)\n+\n+static atomic_t hw_reset_count = ATOMIC_INIT(0);\n+\n+struct rt2880_spi {\n+\tstruct spi_master\t*master;\n+\tvoid __iomem\t\t*base;\n+\tu32\t\t\tspeed;\n+\tu16\t\t\twait_loops;\n+\tu16\t\t\tmode;\n+\tstruct clk\t\t*clk;\n+};\n+\n+static inline struct rt2880_spi *spidev_to_rt2880_spi(struct spi_device *spi)\n+{\n+\treturn spi_master_get_devdata(spi->master);\n+}\n+\n+static inline u32 rt2880_spi_read(struct rt2880_spi *rs, u32 reg)\n+{\n+\treturn ioread32(rs->base + reg);\n+}\n+\n+static inline void rt2880_spi_write(struct rt2880_spi *rs, u32 reg,\n+\t\tconst u32 val)\n+{\n+\tiowrite32(val, rs->base + reg);\n+}\n+\n+static inline void rt2880_spi_setbits(struct rt2880_spi *rs, u32 reg, u32 mask)\n+{\n+\tvoid __iomem *addr = rs->base + reg;\n+\n+\tiowrite32((ioread32(addr) | mask), addr);\n+}\n+\n+static inline void rt2880_spi_clrbits(struct rt2880_spi *rs, u32 reg, u32 mask)\n+{\n+\tvoid __iomem *addr = rs->base + reg;\n+\n+\tiowrite32((ioread32(addr) & ~mask), addr);\n+}\n+\n+static u32 rt2880_spi_baudrate_get(struct spi_device *spi, unsigned int speed)\n+{\n+\tstruct rt2880_spi *rs = spidev_to_rt2880_spi(spi);\n+\tu32 rate;\n+\tu32 prescale;\n+\n+\t/*\n+\t * the supported rates are: 2, 4, 8, ... 128\n+\t * round up as we look for equal or less speed\n+\t */\n+\trate = DIV_ROUND_UP(clk_get_rate(rs->clk), speed);\n+\trate = roundup_pow_of_two(rate);\n+\n+\t/* Convert the rate to SPI clock divisor value.\t*/\n+\tprescale = ilog2(rate / 2);\n+\n+\t/* some tolerance. double and add 100 */\n+\trs->wait_loops = (8 * HZ * loops_per_jiffy) /\n+\t\t(clk_get_rate(rs->clk) / rate);\n+\trs->wait_loops = (rs->wait_loops << 1) + 100;\n+\trs->speed = speed;\n+\n+\tdev_dbg(&spi->dev, \"speed: %lu/%u, rate: %u, prescal: %u, loops: %hu\\n\",\n+\t\t\tclk_get_rate(rs->clk) / rate, speed, rate, prescale,\n+\t\t\trs->wait_loops);\n+\n+\treturn prescale;\n+}\n+\n+static u32 get_arbiter_offset(struct spi_master *master)\n+{\n+\tu32 offset;\n+\n+\toffset = RAMIPS_SPI_ARBITER;\n+\tif (master->bus_num == 1)\n+\t\toffset -= RAMIPS_SPI_DEV_OFFSET;\n+\n+\treturn offset;\n+}\n+\n+static void rt2880_spi_set_cs(struct spi_device *spi, bool enable)\n+{\n+\tstruct rt2880_spi *rs = spidev_to_rt2880_spi(spi);\n+\n+\tif (enable)\n+\t\trt2880_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_SPIENA);\n+\telse\n+\t\trt2880_spi_clrbits(rs, RAMIPS_SPI_CTL, SPICTL_SPIENA);\n+}\n+\n+static int rt2880_spi_wait_ready(struct rt2880_spi *rs, int len)\n+{\n+\tint loop = rs->wait_loops * len;\n+\n+\twhile ((rt2880_spi_read(rs, RAMIPS_SPI_STAT) & SPISTAT_BUSY) && --loop)\n+\t\tcpu_relax();\n+\n+\tif (loop)\n+\t\treturn 0;\n+\n+\treturn -ETIMEDOUT;\n+}\n+\n+static void rt2880_dump_reg(struct spi_master *master)\n+{\n+\tstruct rt2880_spi *rs = spi_master_get_devdata(master);\n+\n+\tdev_dbg(&master->dev, \"stat: %08x, cfg: %08x, ctl: %08x, \" \\\n+\t\t\t\"data: %08x, arb: %08x\\n\",\n+\t\t\trt2880_spi_read(rs, RAMIPS_SPI_STAT),\n+\t\t\trt2880_spi_read(rs, RAMIPS_SPI_CFG),\n+\t\t\trt2880_spi_read(rs, RAMIPS_SPI_CTL),\n+\t\t\trt2880_spi_read(rs, RAMIPS_SPI_DATA),\n+\t\t\trt2880_spi_read(rs, get_arbiter_offset(master)));\n+}\n+\n+static int rt2880_spi_transfer_one(struct spi_master *master,\n+\t\tstruct spi_device *spi, struct spi_transfer *xfer)\n+{\n+\tstruct rt2880_spi *rs = spi_master_get_devdata(master);\n+\tunsigned len;\n+\tconst u8 *tx = xfer->tx_buf;\n+\tu8 *rx = xfer->rx_buf;\n+\tint err = 0;\n+\n+\t/* change clock speed  */\n+\tif (unlikely(rs->speed != xfer->speed_hz)) {\n+\t\tu32 reg;\n+\t\treg = rt2880_spi_read(rs, RAMIPS_SPI_CFG);\n+\t\treg &= ~SPICFG_SPICLK_PRESCALE_MASK;\n+\t\treg |= rt2880_spi_baudrate_get(spi, xfer->speed_hz);\n+\t\trt2880_spi_write(rs, RAMIPS_SPI_CFG, reg);\n+\t}\n+\n+\tif (tx) {\n+\t\tlen = xfer->len;\n+\t\twhile (len-- > 0) {\n+\t\t\trt2880_spi_write(rs, RAMIPS_SPI_DATA, *tx++);\n+\t\t\trt2880_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_STARTWR);\n+\t\t\terr = rt2880_spi_wait_ready(rs, 1);\n+\t\t\tif (err) {\n+\t\t\t\tdev_err(&spi->dev, \"TX failed, err=%d\\n\", err);\n+\t\t\t\tgoto out;\n+\t\t\t}\n+\t\t}\n+\t}\n+\n+\tif (rx) {\n+\t\tlen = xfer->len;\n+\t\twhile (len-- > 0) {\n+\t\t\trt2880_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_STARTRD);\n+\t\t\terr = rt2880_spi_wait_ready(rs, 1);\n+\t\t\tif (err) {\n+\t\t\t\tdev_err(&spi->dev, \"RX failed, err=%d\\n\", err);\n+\t\t\t\tgoto out;\n+\t\t\t}\n+\t\t\t*rx++ = (u8) rt2880_spi_read(rs, RAMIPS_SPI_DATA);\n+\t\t}\n+\t}\n+\n+out:\n+\treturn err;\n+}\n+\n+/* copy from spi.c */\n+static void spi_set_cs(struct spi_device *spi, bool enable)\n+{\n+\tif (spi->mode & SPI_CS_HIGH)\n+\t\tenable = !enable;\n+\n+\tif (spi->cs_gpio >= 0)\n+\t\tgpio_set_value(spi->cs_gpio, !enable);\n+\telse if (spi->master->set_cs)\n+\t\tspi->master->set_cs(spi, !enable);\n+}\n+\n+static int rt2880_spi_setup(struct spi_device *spi)\n+{\n+\tstruct spi_master *master = spi->master;\n+\tstruct rt2880_spi *rs = spi_master_get_devdata(master);\n+\tu32 reg, old_reg, arbit_off;\n+\n+\tif ((spi->max_speed_hz > master->max_speed_hz) ||\n+\t\t\t(spi->max_speed_hz < master->min_speed_hz)) {\n+\t\tdev_err(&spi->dev, \"invalide requested speed %d Hz\\n\",\n+\t\t\t\tspi->max_speed_hz);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (!(master->bits_per_word_mask &\n+\t\t\t\tBIT(spi->bits_per_word - 1))) {\n+\t\tdev_err(&spi->dev, \"invalide bits_per_word %d\\n\",\n+\t\t\t\tspi->bits_per_word);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\t/* the hardware seems can't work on mode0 force it to mode3 */\n+\tif ((spi->mode & (SPI_CPOL | SPI_CPHA)) == SPI_MODE_0) {\n+\t\tdev_warn(&spi->dev, \"force spi mode3\\n\");\n+\t\tspi->mode |= SPI_MODE_3;\n+\t}\n+\n+\t/* chip polarity */\n+\tarbit_off = get_arbiter_offset(master);\n+\treg = old_reg = rt2880_spi_read(rs, arbit_off);\n+\tif (spi->mode & SPI_CS_HIGH) {\n+\t\tswitch (master->bus_num) {\n+\t\tcase 1:\n+\t\t\treg |= SPI1_POR;\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\treg |= SPI0_POR;\n+\t\t\tbreak;\n+\t\t}\n+\t} else {\n+\t\tswitch (master->bus_num) {\n+\t\tcase 1:\n+\t\t\treg &= ~SPI1_POR;\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\treg &= ~SPI0_POR;\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\n+\t/* enable spi1 */\n+\tif (master->bus_num == 1)\n+\t\treg |= SPICTL_ARB_EN;\n+\n+\tif (reg != old_reg)\n+\t\trt2880_spi_write(rs, arbit_off, reg);\n+\n+\t/* deselected the spi device */\n+\tspi_set_cs(spi, false);\n+\n+\trt2880_dump_reg(master);\n+\n+\treturn 0;\n+}\n+\n+static int rt2880_spi_prepare_message(struct spi_master *master,\n+\t\tstruct spi_message *msg)\n+{\n+\tstruct rt2880_spi *rs = spi_master_get_devdata(master);\n+\tstruct spi_device *spi = msg->spi;\n+\tu32 reg;\n+\n+\tif ((rs->mode == spi->mode) && (rs->speed == spi->max_speed_hz))\n+\t\treturn 0;\n+\n+#if 0\n+\t/* set spido to tri-state */\n+\trt2880_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_HIZSDO);\n+#endif\n+\n+\treg = rt2880_spi_read(rs, RAMIPS_SPI_CFG);\n+\n+\treg &= ~(SPICFG_MSBFIRST | SPICFG_SPICLKPOL |\n+\t\t\tSPICFG_RXCLKEDGE_FALLING |\n+\t\t\tSPICFG_TXCLKEDGE_FALLING |\n+\t\t\tSPICFG_SPICLK_PRESCALE_MASK);\n+\n+\t/* MSB */\n+\tif (!(spi->mode & SPI_LSB_FIRST))\n+\t\treg |= SPICFG_MSBFIRST;\n+\n+\t/* spi mode */\n+\tswitch (spi->mode & (SPI_CPOL | SPI_CPHA)) {\n+\tcase SPI_MODE_0:\n+\t\treg |= SPICFG_TXCLKEDGE_FALLING;\n+\t\tbreak;\n+\tcase SPI_MODE_1:\n+\t\treg |= SPICFG_RXCLKEDGE_FALLING;\n+\t\tbreak;\n+\tcase SPI_MODE_2:\n+\t\treg |= SPICFG_SPICLKPOL | SPICFG_RXCLKEDGE_FALLING;\n+\t\tbreak;\n+\tcase SPI_MODE_3:\n+\t\treg |= SPICFG_SPICLKPOL | SPICFG_TXCLKEDGE_FALLING;\n+\t\tbreak;\n+\t}\n+\trs->mode = spi->mode;\n+\n+#if 0\n+\t/* set spiclk and spiena to tri-state */\n+\treg |= SPICFG_HIZSPI;\n+#endif\n+\n+\t/* clock divide */\n+\treg |= rt2880_spi_baudrate_get(spi, spi->max_speed_hz);\n+\n+\trt2880_spi_write(rs, RAMIPS_SPI_CFG, reg);\n+\n+\treturn 0;\n+}\n+\n+static int rt2880_spi_probe(struct platform_device *pdev)\n+{\n+\tstruct spi_master *master;\n+\tstruct rt2880_spi *rs;\n+\tvoid __iomem *base;\n+\tstruct resource *r;\n+\tstruct clk *clk;\n+\tint ret;\n+\n+\tr = platform_get_resource(pdev, IORESOURCE_MEM, 0);\n+\tbase = devm_ioremap_resource(&pdev->dev, r);\n+\tif (IS_ERR(base))\n+\t\treturn PTR_ERR(base);\n+\n+\tclk = devm_clk_get(&pdev->dev, NULL);\n+\tif (IS_ERR(clk)) {\n+\t\tdev_err(&pdev->dev, \"unable to get SYS clock\\n\");\n+\t\treturn PTR_ERR(clk);\n+\t}\n+\n+\tret = clk_prepare_enable(clk);\n+\tif (ret)\n+\t\tgoto err_clk;\n+\n+\tmaster = spi_alloc_master(&pdev->dev, sizeof(*rs));\n+\tif (master == NULL) {\n+\t\tdev_dbg(&pdev->dev, \"master allocation failed\\n\");\n+\t\tret = -ENOMEM;\n+\t\tgoto err_clk;\n+\t}\n+\n+\tmaster->dev.of_node = pdev->dev.of_node;\n+\tmaster->mode_bits = RT2880_SPI_MODE_BITS;\n+\tmaster->bits_per_word_mask = SPI_BPW_MASK(8);\n+\tmaster->min_speed_hz = clk_get_rate(clk) / 128;\n+\tmaster->max_speed_hz = clk_get_rate(clk) / 2;\n+\tmaster->flags = SPI_MASTER_HALF_DUPLEX;\n+\tmaster->setup = rt2880_spi_setup;\n+\tmaster->prepare_message = rt2880_spi_prepare_message;\n+\tmaster->set_cs = rt2880_spi_set_cs;\n+\tmaster->transfer_one = rt2880_spi_transfer_one,\n+\n+\tdev_set_drvdata(&pdev->dev, master);\n+\n+\trs = spi_master_get_devdata(master);\n+\trs->master = master;\n+\trs->base = base;\n+\trs->clk = clk;\n+\n+\tif (atomic_inc_return(&hw_reset_count) == 1)\n+\t\tdevice_reset(&pdev->dev);\n+\n+\tret = devm_spi_register_master(&pdev->dev, master);\n+\tif (ret < 0) {\n+\t\tdev_err(&pdev->dev, \"devm_spi_register_master error.\\n\");\n+\t\tgoto err_master;\n+\t}\n+\n+\treturn ret;\n+\n+err_master:\n+\tspi_master_put(master);\n+\tkfree(master);\n+err_clk:\n+\tclk_disable_unprepare(clk);\n+\n+\treturn ret;\n+}\n+\n+static int rt2880_spi_remove(struct platform_device *pdev)\n+{\n+\tstruct spi_master *master;\n+\tstruct rt2880_spi *rs;\n+\n+\tmaster = dev_get_drvdata(&pdev->dev);\n+\trs = spi_master_get_devdata(master);\n+\n+\tclk_disable_unprepare(rs->clk);\n+\tatomic_dec(&hw_reset_count);\n+\n+\treturn 0;\n+}\n+\n+MODULE_ALIAS(\"platform:\" DRIVER_NAME);\n+\n+static const struct of_device_id rt2880_spi_match[] = {\n+\t{ .compatible = \"ralink,rt2880-spi\" },\n+\t{},\n+};\n+MODULE_DEVICE_TABLE(of, rt2880_spi_match);\n+\n+static struct platform_driver rt2880_spi_driver = {\n+\t.driver = {\n+\t\t.name = DRIVER_NAME,\n+\t\t.owner = THIS_MODULE,\n+\t\t.of_match_table = rt2880_spi_match,\n+\t},\n+\t.probe = rt2880_spi_probe,\n+\t.remove = rt2880_spi_remove,\n+};\n+\n+module_platform_driver(rt2880_spi_driver);\n+\n+MODULE_DESCRIPTION(\"Ralink SPI driver\");\n+MODULE_AUTHOR(\"Sergiy <piratfm@gmail.com>\");\n+MODULE_AUTHOR(\"Gabor Juhos <juhosg@openwrt.org>\");\n+MODULE_LICENSE(\"GPL\");\n"
  },
  {
    "path": "target/linux/ramips/patches-5.10/825-i2c-MIPS-adds-ralink-I2C-driver.patch",
    "content": "From 723b8beaabf3c3c4b1ce69480141f1e926f3f3b2 Mon Sep 17 00:00:00 2001\nFrom: John Crispin <blogic@openwrt.org>\nDate: Sun, 27 Jul 2014 09:52:56 +0100\nSubject: [PATCH 44/53] i2c: MIPS: adds ralink I2C driver\n\nSigned-off-by: John Crispin <blogic@openwrt.org>\n---\n .../devicetree/bindings/i2c/i2c-ralink.txt         |   27 ++\n drivers/i2c/busses/Kconfig                         |    4 +\n drivers/i2c/busses/Makefile                        |    1 +\n drivers/i2c/busses/i2c-ralink.c                    |  327 ++++++++++++++++++++\n 4 files changed, 359 insertions(+)\n create mode 100644 Documentation/devicetree/bindings/i2c/i2c-ralink.txt\n create mode 100644 drivers/i2c/busses/i2c-ralink.c\n\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/i2c/i2c-ralink.txt\n@@ -0,0 +1,27 @@\n+I2C for Ralink platforms\n+\n+Required properties :\n+- compatible : Must be \"link,rt3052-i2c\"\n+- reg: physical base address of the controller and length of memory mapped\n+     region.\n+- #address-cells = <1>;\n+- #size-cells = <0>;\n+\n+Optional properties:\n+- Child nodes conforming to i2c bus binding\n+\n+Example :\n+\n+palmbus@10000000 {\n+\ti2c@900 {\n+\t\tcompatible = \"link,rt3052-i2c\";\n+\t\treg = <0x900 0x100>;\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\n+\t\thwmon@4b {\n+\t\t\tcompatible = \"national,lm92\";\n+\t\t\treg = <0x4b>;\n+\t\t};\n+\t};\n+};\n--- a/drivers/i2c/busses/Kconfig\n+++ b/drivers/i2c/busses/Kconfig\n@@ -954,6 +954,11 @@ config I2C_RK3X\n \t  This driver can also be built as a module. If so, the module will\n \t  be called i2c-rk3x.\n \n+config I2C_RALINK\n+\ttristate \"Ralink I2C Controller\"\n+\tdepends on RALINK && !SOC_MT7621\n+\tselect OF_I2C\n+\n config HAVE_S3C2410_I2C\n \tbool\n \thelp\n--- a/drivers/i2c/busses/Makefile\n+++ b/drivers/i2c/busses/Makefile\n@@ -90,6 +90,7 @@ obj-$(CONFIG_I2C_PMCMSP)\t+= i2c-pmcmsp.o\n obj-$(CONFIG_I2C_PNX)\t\t+= i2c-pnx.o\n obj-$(CONFIG_I2C_PXA)\t\t+= i2c-pxa.o\n obj-$(CONFIG_I2C_PXA_PCI)\t+= i2c-pxa-pci.o\n+obj-$(CONFIG_I2C_RALINK)\t+= i2c-ralink.o\n obj-$(CONFIG_I2C_QCOM_CCI)\t+= i2c-qcom-cci.o\n obj-$(CONFIG_I2C_QCOM_GENI)\t+= i2c-qcom-geni.o\n obj-$(CONFIG_I2C_QUP)\t\t+= i2c-qup.o\n--- /dev/null\n+++ b/drivers/i2c/busses/i2c-ralink.c\n@@ -0,0 +1,435 @@\n+/*\n+ * drivers/i2c/busses/i2c-ralink.c\n+ *\n+ * Copyright (C) 2013 Steven Liu <steven_liu@mediatek.com>\n+ * Copyright (C) 2016 Michael Lee <igvtee@gmail.com>\n+ *\n+ * Improve driver for i2cdetect from i2c-tools to detect i2c devices on the bus.\n+ * (C) 2014 Sittisak <sittisaks@hotmail.com>\n+ *\n+ * This software is licensed under the terms of the GNU General Public\n+ * License version 2, as published by the Free Software Foundation, and\n+ * may be copied, distributed, and modified under those terms.\n+ *\n+ * This program is distributed in the hope that it will be useful,\n+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\n+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n+ * GNU General Public License for more details.\n+ *\n+ */\n+\n+#include <linux/interrupt.h>\n+#include <linux/kernel.h>\n+#include <linux/module.h>\n+#include <linux/reset.h>\n+#include <linux/delay.h>\n+#include <linux/slab.h>\n+#include <linux/init.h>\n+#include <linux/errno.h>\n+#include <linux/platform_device.h>\n+#include <linux/of_platform.h>\n+#include <linux/i2c.h>\n+#include <linux/io.h>\n+#include <linux/err.h>\n+#include <linux/clk.h>\n+\n+#define REG_CONFIG_REG\t\t0x00\n+#define REG_CLKDIV_REG\t\t0x04\n+#define REG_DEVADDR_REG\t\t0x08\n+#define REG_ADDR_REG\t\t0x0C\n+#define REG_DATAOUT_REG\t\t0x10\n+#define REG_DATAIN_REG\t\t0x14\n+#define REG_STATUS_REG\t\t0x18\n+#define REG_STARTXFR_REG\t0x1C\n+#define REG_BYTECNT_REG\t\t0x20\n+\n+/* REG_CONFIG_REG */\n+#define I2C_ADDRLEN_OFFSET\t5\n+#define I2C_DEVADLEN_OFFSET\t2\n+#define I2C_ADDRLEN_MASK\t0x3\n+#define I2C_ADDR_DIS\t\tBIT(1)\n+#define I2C_DEVADDR_DIS\t\tBIT(0)\n+#define I2C_ADDRLEN_8\t\t(7 << I2C_ADDRLEN_OFFSET)\n+#define I2C_DEVADLEN_7\t\t(6 << I2C_DEVADLEN_OFFSET)\n+#define I2C_CONF_DEFAULT\t(I2C_ADDRLEN_8 | I2C_DEVADLEN_7)\n+\n+/* REG_CLKDIV_REG */\n+#define I2C_CLKDIV_MASK\t\t0xffff\n+\n+/* REG_DEVADDR_REG */\n+#define I2C_DEVADDR_MASK\t0x7f\n+\n+/* REG_ADDR_REG */\n+#define I2C_ADDR_MASK\t\t0xff\n+\n+/* REG_STATUS_REG */\n+#define I2C_STARTERR\t\tBIT(4)\n+#define I2C_ACKERR\t\tBIT(3)\n+#define I2C_DATARDY\t\tBIT(2)\n+#define I2C_SDOEMPTY\t\tBIT(1)\n+#define I2C_BUSY\t\tBIT(0)\n+\n+/* REG_STARTXFR_REG */\n+#define NOSTOP_CMD\t\tBIT(2)\n+#define NODATA_CMD\t\tBIT(1)\n+#define READ_CMD\t\tBIT(0)\n+\n+/* REG_BYTECNT_REG */\n+#define BYTECNT_MAX\t\t64\n+#define SET_BYTECNT(x)\t\t(x - 1)\n+\n+/* timeout waiting for I2C devices to respond (clock streching) */\n+#define TIMEOUT_MS              1000\n+#define DELAY_INTERVAL_US       100\n+\n+struct rt_i2c {\n+\tvoid __iomem *base;\n+\tstruct clk *clk;\n+\tstruct device *dev;\n+\tstruct i2c_adapter adap;\n+\tu32 cur_clk;\n+\tu32 clk_div;\n+\tu32 flags;\n+};\n+\n+static void rt_i2c_w32(struct rt_i2c *i2c, u32 val, unsigned reg)\n+{\n+\tiowrite32(val, i2c->base + reg);\n+}\n+\n+static u32 rt_i2c_r32(struct rt_i2c *i2c, unsigned reg)\n+{\n+\treturn ioread32(i2c->base + reg);\n+}\n+\n+static int poll_down_timeout(void __iomem *addr, u32 mask)\n+{\n+\tunsigned long timeout = jiffies + msecs_to_jiffies(TIMEOUT_MS);\n+\n+\tdo {\n+\t\tif (!(readl_relaxed(addr) & mask))\n+\t\t\treturn 0;\n+\n+\t\tusleep_range(DELAY_INTERVAL_US, DELAY_INTERVAL_US + 50);\n+\t} while (time_before(jiffies, timeout));\n+\n+\treturn (readl_relaxed(addr) & mask) ? -EAGAIN : 0;\n+}\n+\n+static int rt_i2c_wait_idle(struct rt_i2c *i2c)\n+{\n+\tint ret;\n+\n+\tret = poll_down_timeout(i2c->base + REG_STATUS_REG, I2C_BUSY);\n+\tif (ret < 0)\n+\t\tdev_dbg(i2c->dev, \"idle err(%d)\\n\", ret);\n+\n+\treturn ret;\n+}\n+\n+static int poll_up_timeout(void __iomem *addr, u32 mask)\n+{\n+\tunsigned long timeout = jiffies + msecs_to_jiffies(TIMEOUT_MS);\n+\tu32 status;\n+\n+\tdo {\n+\t\tstatus = readl_relaxed(addr);\n+\n+\t\t/* check error status */\n+\t\tif (status & I2C_STARTERR)\n+\t\t\treturn -EAGAIN;\n+\t\telse if (status & I2C_ACKERR)\n+\t\t\treturn -ENXIO;\n+\t\telse if (status & mask)\n+\t\t\treturn 0;\n+\n+\t\tusleep_range(DELAY_INTERVAL_US, DELAY_INTERVAL_US + 50);\n+\t} while (time_before(jiffies, timeout));\n+\n+\treturn -ETIMEDOUT;\n+}\n+\n+static int rt_i2c_wait_rx_done(struct rt_i2c *i2c)\n+{\n+\tint ret;\n+\n+\tret = poll_up_timeout(i2c->base + REG_STATUS_REG, I2C_DATARDY);\n+\tif (ret < 0)\n+\t\tdev_dbg(i2c->dev, \"rx err(%d)\\n\", ret);\n+\n+\treturn ret;\n+}\n+\n+static int rt_i2c_wait_tx_done(struct rt_i2c *i2c)\n+{\n+\tint ret;\n+\n+\tret = poll_up_timeout(i2c->base + REG_STATUS_REG, I2C_SDOEMPTY);\n+\tif (ret < 0)\n+\t\tdev_dbg(i2c->dev, \"tx err(%d)\\n\", ret);\n+\n+\treturn ret;\n+}\n+\n+static void rt_i2c_reset(struct rt_i2c *i2c)\n+{\n+\tdevice_reset(i2c->adap.dev.parent);\n+\tbarrier();\n+\trt_i2c_w32(i2c, i2c->clk_div, REG_CLKDIV_REG);\n+}\n+\n+static void rt_i2c_dump_reg(struct rt_i2c *i2c)\n+{\n+\tdev_dbg(i2c->dev, \"conf %08x, clkdiv %08x, devaddr %08x, \" \\\n+\t\t\t\"addr %08x, dataout %08x, datain %08x, \" \\\n+\t\t\t\"status %08x, startxfr %08x, bytecnt %08x\\n\",\n+\t\t\trt_i2c_r32(i2c, REG_CONFIG_REG),\n+\t\t\trt_i2c_r32(i2c, REG_CLKDIV_REG),\n+\t\t\trt_i2c_r32(i2c, REG_DEVADDR_REG),\n+\t\t\trt_i2c_r32(i2c, REG_ADDR_REG),\n+\t\t\trt_i2c_r32(i2c, REG_DATAOUT_REG),\n+\t\t\trt_i2c_r32(i2c, REG_DATAIN_REG),\n+\t\t\trt_i2c_r32(i2c, REG_STATUS_REG),\n+\t\t\trt_i2c_r32(i2c, REG_STARTXFR_REG),\n+\t\t\trt_i2c_r32(i2c, REG_BYTECNT_REG));\n+}\n+\n+static int rt_i2c_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,\n+\t\tint num)\n+{\n+\tstruct rt_i2c *i2c;\n+\tstruct i2c_msg *pmsg;\n+\tunsigned char addr;\n+\tint i, j, ret;\n+\tu32 cmd;\n+\n+\ti2c = i2c_get_adapdata(adap);\n+\n+\tfor (i = 0; i < num; i++) {\n+\t\tpmsg = &msgs[i];\n+\t\tif (i == (num - 1))\n+\t\t\tcmd = 0;\n+\t\telse\n+\t\t\tcmd = NOSTOP_CMD;\n+\n+\t\tdev_dbg(i2c->dev, \"addr: 0x%x, len: %d, flags: 0x%x, stop: %d\\n\",\n+\t\t\t\tpmsg->addr, pmsg->len, pmsg->flags,\n+\t\t\t\t(cmd == 0)? 1 : 0);\n+\n+\t\t/* wait hardware idle */\n+\t\tif ((ret = rt_i2c_wait_idle(i2c)))\n+\t\t\tgoto err_timeout;\n+\n+\t\tif (pmsg->flags & I2C_M_TEN) {\n+\t\t\trt_i2c_w32(i2c, I2C_CONF_DEFAULT, REG_CONFIG_REG);\n+\t\t\t/* 10 bits address */\n+\t\t\taddr = 0x78 | ((pmsg->addr >> 8) & 0x03);\n+\t\t\trt_i2c_w32(i2c, addr & I2C_DEVADDR_MASK,\n+\t\t\t\t\tREG_DEVADDR_REG);\n+\t\t\trt_i2c_w32(i2c, pmsg->addr & I2C_ADDR_MASK,\n+\t\t\t\t\tREG_ADDR_REG);\n+\t\t} else {\n+\t\t\trt_i2c_w32(i2c, I2C_CONF_DEFAULT | I2C_ADDR_DIS,\n+\t\t\t\t\tREG_CONFIG_REG);\n+\t\t\t/* 7 bits address */\n+\t\t\trt_i2c_w32(i2c, pmsg->addr & I2C_DEVADDR_MASK,\n+\t\t\t\t\tREG_DEVADDR_REG);\n+\t\t}\n+\n+\t\t/* buffer length */\n+\t\tif (pmsg->len == 0)\n+\t\t\tcmd |= NODATA_CMD;\n+\t\telse\n+\t\t\trt_i2c_w32(i2c, SET_BYTECNT(pmsg->len),\n+\t\t\t\t\tREG_BYTECNT_REG);\n+\n+\t\tj = 0;\n+\t\tif (pmsg->flags & I2C_M_RD) {\n+\t\t\tcmd |= READ_CMD;\n+\t\t\t/* start transfer */\n+\t\t\tbarrier();\n+\t\t\trt_i2c_w32(i2c, cmd, REG_STARTXFR_REG);\n+\t\t\tdo {\n+\t\t\t\t/* wait */\n+\t\t\t\tif ((ret = rt_i2c_wait_rx_done(i2c)))\n+\t\t\t\t\tgoto err_timeout;\n+\t\t\t\t/* read data */\n+\t\t\t\tif (pmsg->len)\n+\t\t\t\t\tpmsg->buf[j] = rt_i2c_r32(i2c,\n+\t\t\t\t\t\t\tREG_DATAIN_REG);\n+\t\t\t\tj++;\n+\t\t\t} while (j < pmsg->len);\n+\t\t} else {\n+\t\t\tdo {\n+\t\t\t\t/* write data */\n+\t\t\t\tif (pmsg->len)\n+\t\t\t\t\trt_i2c_w32(i2c, pmsg->buf[j],\n+\t\t\t\t\t\t\tREG_DATAOUT_REG);\n+\t\t\t\t/* start transfer */\n+\t\t\t\tif (j == 0) {\n+\t\t\t\t\tbarrier();\n+\t\t\t\t\trt_i2c_w32(i2c, cmd, REG_STARTXFR_REG);\n+\t\t\t\t}\n+\t\t\t\t/* wait */\n+\t\t\t\tif ((ret = rt_i2c_wait_tx_done(i2c)))\n+\t\t\t\t\tgoto err_timeout;\n+\t\t\t\tj++;\n+\t\t\t} while (j < pmsg->len);\n+\t\t}\n+\t}\n+\t/* the return value is number of executed messages */\n+\tret = i;\n+\n+\treturn ret;\n+\n+err_timeout:\n+\trt_i2c_dump_reg(i2c);\n+\trt_i2c_reset(i2c);\n+\treturn ret;\n+}\n+\n+static u32 rt_i2c_func(struct i2c_adapter *a)\n+{\n+\treturn I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;\n+}\n+\n+static const struct i2c_algorithm rt_i2c_algo = {\n+\t.master_xfer\t= rt_i2c_master_xfer,\n+\t.functionality\t= rt_i2c_func,\n+};\n+\n+static const struct of_device_id i2c_rt_dt_ids[] = {\n+\t{ .compatible = \"ralink,rt2880-i2c\" },\n+\t{ /* sentinel */ }\n+};\n+\n+MODULE_DEVICE_TABLE(of, i2c_rt_dt_ids);\n+\n+static struct i2c_adapter_quirks rt_i2c_quirks = {\n+        .max_write_len = BYTECNT_MAX,\n+        .max_read_len = BYTECNT_MAX,\n+};\n+\n+static int rt_i2c_init(struct rt_i2c *i2c)\n+{\n+\tu32 reg;\n+\n+\t/* i2c_sclk = periph_clk / ((2 * clk_div) + 5) */\n+\ti2c->clk_div = (clk_get_rate(i2c->clk) - (5 * i2c->cur_clk)) /\n+\t\t(2 * i2c->cur_clk);\n+\tif (i2c->clk_div < 8)\n+\t\ti2c->clk_div = 8;\n+\tif (i2c->clk_div > I2C_CLKDIV_MASK)\n+\t\ti2c->clk_div = I2C_CLKDIV_MASK;\n+\n+\t/* check support combinde/repeated start message */\n+\trt_i2c_w32(i2c, NOSTOP_CMD, REG_STARTXFR_REG);\n+\treg = rt_i2c_r32(i2c, REG_STARTXFR_REG) & NOSTOP_CMD;\n+\n+\trt_i2c_reset(i2c);\n+\n+\treturn reg;\n+}\n+\n+static int rt_i2c_probe(struct platform_device *pdev)\n+{\n+\tstruct resource *res;\n+\tstruct rt_i2c *i2c;\n+\tstruct i2c_adapter *adap;\n+\tconst struct of_device_id *match;\n+\tint ret, restart;\n+\n+\tmatch = of_match_device(i2c_rt_dt_ids, &pdev->dev);\n+\n+\tres = platform_get_resource(pdev, IORESOURCE_MEM, 0);\n+\tif (!res) {\n+\t\tdev_err(&pdev->dev, \"no memory resource found\\n\");\n+\t\treturn -ENODEV;\n+\t}\n+\n+\ti2c = devm_kzalloc(&pdev->dev, sizeof(struct rt_i2c), GFP_KERNEL);\n+\tif (!i2c) {\n+\t\tdev_err(&pdev->dev, \"failed to allocate i2c_adapter\\n\");\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\ti2c->base = devm_ioremap_resource(&pdev->dev, res);\n+\tif (IS_ERR(i2c->base))\n+\t\treturn PTR_ERR(i2c->base);\n+\n+\ti2c->clk = devm_clk_get(&pdev->dev, NULL);\n+\tif (IS_ERR(i2c->clk)) {\n+\t\tdev_err(&pdev->dev, \"no clock defined\\n\");\n+\t\treturn -ENODEV;\n+\t}\n+\tclk_prepare_enable(i2c->clk);\n+\ti2c->dev = &pdev->dev;\n+\n+\tif (of_property_read_u32(pdev->dev.of_node,\n+\t\t\t\t\"clock-frequency\", &i2c->cur_clk))\n+\t\ti2c->cur_clk = 100000;\n+\n+\tadap = &i2c->adap;\n+\tadap->owner = THIS_MODULE;\n+\tadap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;\n+\tadap->algo = &rt_i2c_algo;\n+\tadap->retries = 3;\n+\tadap->dev.parent = &pdev->dev;\n+\ti2c_set_adapdata(adap, i2c);\n+\tadap->dev.of_node = pdev->dev.of_node;\n+\tstrlcpy(adap->name, dev_name(&pdev->dev), sizeof(adap->name));\n+\tadap->quirks = &rt_i2c_quirks;\n+\n+\tplatform_set_drvdata(pdev, i2c);\n+\n+\trestart = rt_i2c_init(i2c);\n+\n+\tret = i2c_add_adapter(adap);\n+\tif (ret < 0) {\n+\t\tdev_err(&pdev->dev, \"failed to add adapter\\n\");\n+\t\tclk_disable_unprepare(i2c->clk);\n+\t\treturn ret;\n+\t}\n+\n+\tdev_info(&pdev->dev, \"clock %uKHz, re-start %ssupport\\n\",\n+\t\t\ti2c->cur_clk/1000, restart ? \"\" : \"not \");\n+\n+\treturn ret;\n+}\n+\n+static int rt_i2c_remove(struct platform_device *pdev)\n+{\n+\tstruct rt_i2c *i2c = platform_get_drvdata(pdev);\n+\n+\ti2c_del_adapter(&i2c->adap);\n+\tclk_disable_unprepare(i2c->clk);\n+\n+\treturn 0;\n+}\n+\n+static struct platform_driver rt_i2c_driver = {\n+\t.probe\t\t= rt_i2c_probe,\n+\t.remove\t\t= rt_i2c_remove,\n+\t.driver\t\t= {\n+\t\t.owner\t= THIS_MODULE,\n+\t\t.name\t= \"i2c-ralink\",\n+\t\t.of_match_table = i2c_rt_dt_ids,\n+\t},\n+};\n+\n+static int __init i2c_rt_init (void)\n+{\n+\treturn platform_driver_register(&rt_i2c_driver);\n+}\n+subsys_initcall(i2c_rt_init);\n+\n+static void __exit i2c_rt_exit (void)\n+{\n+\tplatform_driver_unregister(&rt_i2c_driver);\n+}\n+module_exit(i2c_rt_exit);\n+\n+MODULE_AUTHOR(\"Steven Liu <steven_liu@mediatek.com>\");\n+MODULE_DESCRIPTION(\"Ralink I2c host driver\");\n+MODULE_LICENSE(\"GPL\");\n+MODULE_ALIAS(\"platform:Ralink-I2C\");\n"
  },
  {
    "path": "target/linux/ramips/patches-5.10/830-mmc-MIPS-ralink-add-sdhci-for-mt7620a-SoC.patch",
    "content": "From 23147af14531cbdada194b94120ef8774f46292d Mon Sep 17 00:00:00 2001\nFrom: John Crispin <blogic@openwrt.org>\nDate: Thu, 13 Nov 2014 19:08:40 +0100\nSubject: [PATCH 46/53] mmc: MIPS: ralink: add sdhci for mt7620a SoC\n\nSigned-off-by: John Crispin <blogic@openwrt.org>\n---\n drivers/mmc/host/Kconfig             |    2 +\n drivers/mmc/host/Makefile            |    1 +\n drivers/mmc/host/mtk-mmc/Kconfig     |   16 +\n drivers/mmc/host/mtk-mmc/Makefile    |   42 +\n drivers/mmc/host/mtk-mmc/board.h     |  137 ++\n drivers/mmc/host/mtk-mmc/dbg.c       |  347 ++++\n drivers/mmc/host/mtk-mmc/dbg.h       |  156 ++\n drivers/mmc/host/mtk-mmc/mt6575_sd.h | 1001 +++++++++++\n drivers/mmc/host/mtk-mmc/sd.c        | 3060 ++++++++++++++++++++++++++++++++++\n 9 files changed, 4762 insertions(+)\n create mode 100644 drivers/mmc/host/mtk-mmc/Kconfig\n create mode 100644 drivers/mmc/host/mtk-mmc/Makefile\n create mode 100644 drivers/mmc/host/mtk-mmc/board.h\n create mode 100644 drivers/mmc/host/mtk-mmc/dbg.c\n create mode 100644 drivers/mmc/host/mtk-mmc/dbg.h\n create mode 100644 drivers/mmc/host/mtk-mmc/mt6575_sd.h\n create mode 100644 drivers/mmc/host/mtk-mmc/sd.c\n\n--- a/drivers/mmc/host/Kconfig\n+++ b/drivers/mmc/host/Kconfig\n@@ -1101,3 +1101,5 @@ config MMC_OWL\n \n config MMC_SDHCI_EXTERNAL_DMA\n \tbool\n+\n+source \"drivers/mmc/host/mtk-mmc/Kconfig\"\n--- a/drivers/mmc/host/Makefile\n+++ b/drivers/mmc/host/Makefile\n@@ -3,6 +3,7 @@\n # Makefile for MMC/SD host controller drivers\n #\n \n+obj-$(CONFIG_MTK_MMC) \t\t+= mtk-mmc/\n obj-$(CONFIG_MMC_ARMMMCI) += armmmci.o\n armmmci-y := mmci.o\n armmmci-$(CONFIG_MMC_QCOM_DML) += mmci_qcom_dml.o\n"
  },
  {
    "path": "target/linux/ramips/patches-5.10/835-asoc-add-mt7620-support.patch",
    "content": "From 7f29222b1731e8182ba94a331531dec18865a1e4 Mon Sep 17 00:00:00 2001\nFrom: John Crispin <blogic@openwrt.org>\nDate: Sun, 27 Jul 2014 09:31:47 +0100\nSubject: [PATCH 48/53] asoc: add mt7620 support\n\nSigned-off-by: John Crispin <blogic@openwrt.org>\n---\n arch/mips/ralink/of.c            |    2 +\n sound/soc/Kconfig                |    1 +\n sound/soc/Makefile               |    1 +\n sound/soc/ralink/Kconfig         |   15 ++\n sound/soc/ralink/Makefile        |   11 +\n sound/soc/ralink/mt7620-i2s.c    |  436 ++++++++++++++++++++++++++++++++++++++\n sound/soc/ralink/mt7620-wm8960.c |  233 ++++++++++++++++++++\n 7 files changed, 699 insertions(+)\n create mode 100644 sound/soc/ralink/Kconfig\n create mode 100644 sound/soc/ralink/Makefile\n create mode 100644 sound/soc/ralink/mt7620-i2s.c\n create mode 100644 sound/soc/ralink/mt7620-wm8960.c\n\n--- a/sound/soc/Kconfig\n+++ b/sound/soc/Kconfig\n@@ -60,6 +60,7 @@ source \"sound/soc/mxs/Kconfig\"\n source \"sound/soc/pxa/Kconfig\"\n source \"sound/soc/qcom/Kconfig\"\n source \"sound/soc/rockchip/Kconfig\"\n+source \"sound/soc/ralink/Kconfig\"\n source \"sound/soc/samsung/Kconfig\"\n source \"sound/soc/sh/Kconfig\"\n source \"sound/soc/sirf/Kconfig\"\n--- a/sound/soc/Makefile\n+++ b/sound/soc/Makefile\n@@ -43,6 +43,7 @@ obj-$(CONFIG_SND_SOC)\t+= kirkwood/\n obj-$(CONFIG_SND_SOC)\t+= pxa/\n obj-$(CONFIG_SND_SOC)\t+= qcom/\n obj-$(CONFIG_SND_SOC)\t+= rockchip/\n+obj-$(CONFIG_SND_SOC)\t+= ralink/\n obj-$(CONFIG_SND_SOC)\t+= samsung/\n obj-$(CONFIG_SND_SOC)\t+= sh/\n obj-$(CONFIG_SND_SOC)\t+= sirf/\n--- /dev/null\n+++ b/sound/soc/ralink/Kconfig\n@@ -0,0 +1,8 @@\n+config SND_RALINK_SOC_I2S\n+\tdepends on RALINK && SND_SOC && !SOC_RT288X\n+\tselect SND_SOC_GENERIC_DMAENGINE_PCM\n+\tselect REGMAP_MMIO\n+\ttristate \"SoC Audio (I2S protocol) for Ralink SoC\"\n+\thelp\n+\t  Say Y if you want to use I2S protocol and I2S codec on Ralink/MediaTek\n+\t  based boards.\n--- /dev/null\n+++ b/sound/soc/ralink/Makefile\n@@ -0,0 +1,6 @@\n+#\n+# Ralink/MediaTek Platform Support\n+#\n+snd-soc-ralink-i2s-objs := ralink-i2s.o\n+\n+obj-$(CONFIG_SND_RALINK_SOC_I2S) += snd-soc-ralink-i2s.o\n--- /dev/null\n+++ b/sound/soc/ralink/ralink-i2s.c\n@@ -0,0 +1,966 @@\n+/*\n+ *  Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>\n+ *  Copyright (C) 2016 Michael Lee <igvtee@gmail.com>\n+ *\n+ *  This program is free software; you can redistribute it and/or modify it\n+ *  under  the terms of the GNU General  Public License as published by the\n+ *  Free Software Foundation;  either version 2 of the License, or (at your\n+ *  option) any later version.\n+ *\n+ *  You should have received a copy of the GNU General Public License along\n+ *  with this program; if not, write to the Free Software Foundation, Inc.,\n+ *  675 Mass Ave, Cambridge, MA 02139, USA.\n+ *\n+ */\n+\n+#include <linux/module.h>\n+#include <linux/platform_device.h>\n+#include <linux/clk.h>\n+#include <linux/regmap.h>\n+#include <linux/reset.h>\n+#include <linux/debugfs.h>\n+#include <linux/of_device.h>\n+#include <sound/pcm_params.h>\n+#include <sound/dmaengine_pcm.h>\n+\n+#include <asm/mach-ralink/ralink_regs.h>\n+\n+#define DRV_NAME \"ralink-i2s\"\n+\n+#define I2S_REG_CFG0\t\t0x00\n+#define I2S_REG_INT_STATUS\t0x04\n+#define I2S_REG_INT_EN\t\t0x08\n+#define I2S_REG_FF_STATUS\t0x0c\n+#define I2S_REG_WREG\t\t0x10\n+#define I2S_REG_RREG\t\t0x14\n+#define I2S_REG_CFG1\t\t0x18\n+#define I2S_REG_DIVCMP\t\t0x20\n+#define I2S_REG_DIVINT\t\t0x24\n+\n+/* I2S_REG_CFG0 */\n+#define I2S_REG_CFG0_EN\t\tBIT(31)\n+#define I2S_REG_CFG0_DMA_EN\tBIT(30)\n+#define I2S_REG_CFG0_BYTE_SWAP\tBIT(28)\n+#define I2S_REG_CFG0_TX_EN\tBIT(24)\n+#define I2S_REG_CFG0_RX_EN\tBIT(20)\n+#define I2S_REG_CFG0_SLAVE\tBIT(16)\n+#define I2S_REG_CFG0_RX_THRES\t12\n+#define I2S_REG_CFG0_TX_THRES\t4\n+#define I2S_REG_CFG0_THRES_MASK\t(0xf << I2S_REG_CFG0_RX_THRES) | \\\n+\t(4 << I2S_REG_CFG0_TX_THRES)\n+#define I2S_REG_CFG0_DFT_THRES\t(4 << I2S_REG_CFG0_RX_THRES) | \\\n+\t(4 << I2S_REG_CFG0_TX_THRES)\n+/* RT305x */\n+#define I2S_REG_CFG0_CLK_DIS\tBIT(8)\n+#define I2S_REG_CFG0_TXCH_SWAP\tBIT(3)\n+#define I2S_REG_CFG0_TXCH1_OFF\tBIT(2)\n+#define I2S_REG_CFG0_TXCH0_OFF\tBIT(1)\n+#define I2S_REG_CFG0_SLAVE_EN\tBIT(0)\n+/* RT3883 */\n+#define I2S_REG_CFG0_RXCH_SWAP\tBIT(11)\n+#define I2S_REG_CFG0_RXCH1_OFF\tBIT(10)\n+#define I2S_REG_CFG0_RXCH0_OFF\tBIT(9)\n+#define I2S_REG_CFG0_WS_INV\tBIT(0)\n+/* MT7628 */\n+#define I2S_REG_CFG0_FMT_LE\tBIT(29)\n+#define I2S_REG_CFG0_SYS_BE\tBIT(28)\n+#define I2S_REG_CFG0_NORM_24\tBIT(18)\n+#define I2S_REG_CFG0_DATA_24\tBIT(17)\n+\n+/* I2S_REG_INT_STATUS */\n+#define I2S_REG_INT_RX_FAULT\tBIT(7)\n+#define I2S_REG_INT_RX_OVRUN\tBIT(6)\n+#define I2S_REG_INT_RX_UNRUN\tBIT(5)\n+#define I2S_REG_INT_RX_THRES\tBIT(4)\n+#define I2S_REG_INT_TX_FAULT\tBIT(3)\n+#define I2S_REG_INT_TX_OVRUN\tBIT(2)\n+#define I2S_REG_INT_TX_UNRUN\tBIT(1)\n+#define I2S_REG_INT_TX_THRES\tBIT(0)\n+#define I2S_REG_INT_TX_MASK\t0xf\n+#define I2S_REG_INT_RX_MASK\t0xf0\n+\n+/* I2S_REG_INT_STATUS */\n+#define I2S_RX_AVCNT(x)\t\t((x >> 4) & 0xf)\n+#define I2S_TX_AVCNT(x)\t\t(x & 0xf)\n+/* MT7628 */\n+#define MT7628_I2S_RX_AVCNT(x)\t((x >> 8) & 0x1f)\n+#define MT7628_I2S_TX_AVCNT(x)\t(x & 0x1f)\n+\n+/* I2S_REG_CFG1 */\n+#define I2S_REG_CFG1_LBK\tBIT(31)\n+#define I2S_REG_CFG1_EXTLBK\tBIT(30)\n+/* RT3883 */\n+#define I2S_REG_CFG1_LEFT_J\tBIT(0)\n+#define I2S_REG_CFG1_RIGHT_J\tBIT(1)\n+#define I2S_REG_CFG1_FMT_MASK\t0x3\n+\n+/* I2S_REG_DIVCMP */\n+#define I2S_REG_DIVCMP_CLKEN\tBIT(31)\n+#define I2S_REG_DIVCMP_DIVCOMP_MASK\t0x1ff\n+\n+/* I2S_REG_DIVINT */\n+#define I2S_REG_DIVINT_MASK\t0x3ff\n+\n+/* BCLK dividers */\n+#define RALINK_I2S_DIVCMP\t0\n+#define RALINK_I2S_DIVINT\t1\n+\n+/* FIFO */\n+#define RALINK_I2S_FIFO_SIZE\t32\n+\n+/* feature flags */\n+#define RALINK_FLAGS_TXONLY\tBIT(0)\n+#define RALINK_FLAGS_LEFT_J\tBIT(1)\n+#define RALINK_FLAGS_RIGHT_J\tBIT(2)\n+#define RALINK_FLAGS_ENDIAN\tBIT(3)\n+#define RALINK_FLAGS_24BIT\tBIT(4)\n+\n+#define RALINK_I2S_INT_EN\t0\n+\n+struct ralink_i2s_stats {\n+\tu32 dmafault;\n+\tu32 overrun;\n+\tu32 underrun;\n+\tu32 belowthres;\n+};\n+\n+struct ralink_i2s {\n+\tstruct device *dev;\n+\tvoid __iomem *regs;\n+\tstruct clk *clk;\n+\tstruct regmap *regmap;\n+\tu32 flags;\n+\tunsigned int fmt;\n+\tu16 txdma_req;\n+\tu16 rxdma_req;\n+\n+\tstruct snd_dmaengine_dai_dma_data playback_dma_data;\n+\tstruct snd_dmaengine_dai_dma_data capture_dma_data;\n+\n+\tstruct dentry *dbg_dir;\n+        struct dentry *dbg_stats;\n+\tstruct ralink_i2s_stats txstats;\n+\tstruct ralink_i2s_stats rxstats;\n+};\n+\n+static void ralink_i2s_dump_regs(struct ralink_i2s *i2s)\n+{\n+\tu32 buf[10];\n+\tint ret;\n+\n+\tret = regmap_bulk_read(i2s->regmap, I2S_REG_CFG0,\n+\t\t\tbuf, ARRAY_SIZE(buf));\n+\n+\tdev_dbg(i2s->dev, \"CFG0: %08x, INTSTAT: %08x, INTEN: %08x, \" \\\n+\t\t\t\"FFSTAT: %08x, WREG: %08x, RREG: %08x, \" \\\n+\t\t\t\"CFG1: %08x, DIVCMP: %08x, DIVINT: %08x\\n\",\n+\t\t\tbuf[0], buf[1], buf[2], buf[3], buf[4],\n+\t\t\tbuf[5], buf[6], buf[8], buf[9]);\n+}\n+\n+static int ralink_i2s_set_sysclk(struct snd_soc_dai *dai,\n+                              int clk_id, unsigned int freq, int dir)\n+{\n+\treturn 0;\n+}\n+\n+static int ralink_i2s_set_sys_bclk(struct snd_soc_dai *dai, int width, int rate)\n+{\n+\tstruct ralink_i2s *i2s = snd_soc_dai_get_drvdata(dai);\n+\tunsigned long clk = clk_get_rate(i2s->clk);\n+\tint div;\n+\tuint32_t data;\n+\n+\t/* disable clock at slave mode */\n+\tif ((i2s->fmt & SND_SOC_DAIFMT_MASTER_MASK) ==\n+\t\t\tSND_SOC_DAIFMT_CBM_CFM) {\n+\t\tregmap_update_bits(i2s->regmap, I2S_REG_CFG0,\n+\t\t\t\tI2S_REG_CFG0_CLK_DIS,\n+\t\t\t\tI2S_REG_CFG0_CLK_DIS);\n+\t\treturn 0;\n+\t}\n+\n+\t/* FREQOUT = FREQIN / (I2S_CLK_DIV + 1) */\n+\tdiv = (clk / rate ) - 1;\n+\n+\tdata = rt_sysc_r32(0x30);\n+\tdata &= (0xff << 8);\n+\tdata |= (0x1 << 15) | (div << 8);\n+\trt_sysc_w32(data, 0x30);\n+\n+\t/* enable clock */\n+\tregmap_update_bits(i2s->regmap, I2S_REG_CFG0, I2S_REG_CFG0_CLK_DIS, 0);\n+\n+\tdev_dbg(i2s->dev, \"clk: %lu, rate: %u, div: %d\\n\",\n+\t\t\tclk, rate, div);\n+\n+\treturn 0;\n+}\n+\n+static int ralink_i2s_set_bclk(struct snd_soc_dai *dai, int width, int rate)\n+{\n+\tstruct ralink_i2s *i2s = snd_soc_dai_get_drvdata(dai);\n+\tunsigned long clk = clk_get_rate(i2s->clk);\n+\tint divint, divcomp;\n+\n+\t/* disable clock at slave mode */\n+\tif ((i2s->fmt & SND_SOC_DAIFMT_MASTER_MASK) ==\n+\t\t\tSND_SOC_DAIFMT_CBM_CFM) {\n+\t\tregmap_update_bits(i2s->regmap, I2S_REG_DIVCMP,\n+\t\t\t\tI2S_REG_DIVCMP_CLKEN, 0);\n+\t\treturn 0;\n+\t}\n+\n+\t/* FREQOUT = FREQIN * (1/2) * (1/(DIVINT + DIVCOMP/512)) */\n+\tclk = clk / (2 * 2 * width);\n+\tdivint = clk / rate;\n+\tdivcomp = ((clk % rate) * 512) / rate;\n+\n+\tif ((divint > I2S_REG_DIVINT_MASK) ||\n+\t\t\t(divcomp > I2S_REG_DIVCMP_DIVCOMP_MASK))\n+\t\treturn -EINVAL;\n+\n+\tregmap_update_bits(i2s->regmap, I2S_REG_DIVINT,\n+\t\t\tI2S_REG_DIVINT_MASK, divint);\n+\tregmap_update_bits(i2s->regmap, I2S_REG_DIVCMP,\n+\t\t\tI2S_REG_DIVCMP_DIVCOMP_MASK, divcomp);\n+\n+\t/* enable clock */\n+\tregmap_update_bits(i2s->regmap, I2S_REG_DIVCMP, I2S_REG_DIVCMP_CLKEN,\n+\t\t\tI2S_REG_DIVCMP_CLKEN);\n+\n+\tdev_dbg(i2s->dev, \"clk: %lu, rate: %u, int: %d, comp: %d\\n\",\n+\t\t\tclk_get_rate(i2s->clk), rate, divint, divcomp);\n+\n+\treturn 0;\n+}\n+\n+static int ralink_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)\n+{\n+\tstruct ralink_i2s *i2s = snd_soc_dai_get_drvdata(dai);\n+\tunsigned int cfg0 = 0, cfg1 = 0;\n+\n+\t/* set master/slave audio interface */\n+\tswitch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {\n+\tcase SND_SOC_DAIFMT_CBM_CFM:\n+\t\tif (i2s->flags & RALINK_FLAGS_TXONLY)\n+\t\t\tcfg0 |= I2S_REG_CFG0_SLAVE_EN;\n+\t\telse\n+\t\t\tcfg0 |= I2S_REG_CFG0_SLAVE;\n+\t\tbreak;\n+\tcase SND_SOC_DAIFMT_CBS_CFS:\n+\t\tbreak;\n+\tdefault:\n+\t\treturn -EINVAL;\n+\t}\n+\n+\t/* interface format */\n+\tswitch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {\n+\tcase SND_SOC_DAIFMT_I2S:\n+\t\tbreak;\n+\tcase SND_SOC_DAIFMT_RIGHT_J:\n+\t\tif (i2s->flags & RALINK_FLAGS_RIGHT_J) {\n+\t\t\tcfg1 |= I2S_REG_CFG1_RIGHT_J;\n+\t\t\tbreak;\n+\t\t}\n+\t\treturn -EINVAL;\n+\tcase SND_SOC_DAIFMT_LEFT_J:\n+\t\tif (i2s->flags & RALINK_FLAGS_LEFT_J) {\n+\t\t\tcfg1 |= I2S_REG_CFG1_LEFT_J;\n+\t\t\tbreak;\n+\t\t}\n+\t\treturn -EINVAL;\n+\tdefault:\n+\t\treturn -EINVAL;\n+\t}\n+\n+\t/* clock inversion */\n+\tswitch (fmt & SND_SOC_DAIFMT_INV_MASK) {\n+\tcase SND_SOC_DAIFMT_NB_NF:\n+\t\tbreak;\n+\tdefault:\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (i2s->flags & RALINK_FLAGS_TXONLY) {\n+\t\tregmap_update_bits(i2s->regmap, I2S_REG_CFG0,\n+\t\t\t\tI2S_REG_CFG0_SLAVE_EN, cfg0);\n+\t} else {\n+\t\tregmap_update_bits(i2s->regmap, I2S_REG_CFG0,\n+\t\t\t\tI2S_REG_CFG0_SLAVE, cfg0);\n+\t}\n+\tregmap_update_bits(i2s->regmap, I2S_REG_CFG1,\n+\t\t\tI2S_REG_CFG1_FMT_MASK, cfg1);\n+\ti2s->fmt = fmt;\n+\n+\treturn 0;\n+}\n+\n+static int ralink_i2s_startup(struct snd_pcm_substream *substream,\n+\t\tstruct snd_soc_dai *dai)\n+{\n+\tstruct ralink_i2s *i2s = snd_soc_dai_get_drvdata(dai);\n+\n+\tif (snd_soc_dai_active(dai))\n+\t\treturn 0;\n+\n+\t/* setup status interrupt */\n+#if (RALINK_I2S_INT_EN)\n+\tregmap_write(i2s->regmap, I2S_REG_INT_EN, 0xff);\n+#else\n+\tregmap_write(i2s->regmap, I2S_REG_INT_EN, 0x0);\n+#endif\n+\n+\t/* enable */\n+\tregmap_update_bits(i2s->regmap, I2S_REG_CFG0,\n+\t\t\tI2S_REG_CFG0_EN | I2S_REG_CFG0_DMA_EN |\n+\t\t\tI2S_REG_CFG0_THRES_MASK,\n+\t\t\tI2S_REG_CFG0_EN | I2S_REG_CFG0_DMA_EN |\n+\t\t\tI2S_REG_CFG0_DFT_THRES);\n+\n+\treturn 0;\n+}\n+\n+static void ralink_i2s_shutdown(struct snd_pcm_substream *substream,\n+\t\tstruct snd_soc_dai *dai)\n+{\n+\tstruct ralink_i2s *i2s = snd_soc_dai_get_drvdata(dai);\n+\n+\t/* If both streams are stopped, disable module and clock */\n+\tif (snd_soc_dai_active(dai))\n+\t\treturn;\n+\n+\t/*\n+\t * datasheet mention when disable all control regs are cleared\n+\t * to initial values. need reinit at startup.\n+\t */\n+\tregmap_update_bits(i2s->regmap, I2S_REG_CFG0, I2S_REG_CFG0_EN, 0);\n+}\n+\n+static int ralink_i2s_hw_params(struct snd_pcm_substream *substream,\n+\t\tstruct snd_pcm_hw_params *params, struct snd_soc_dai *dai)\n+{\n+\tstruct ralink_i2s *i2s = snd_soc_dai_get_drvdata(dai);\n+\tint width;\n+\tint ret;\n+\n+\twidth = params_width(params);\n+\tswitch (width) {\n+\tcase 16:\n+\t\tif (i2s->flags & RALINK_FLAGS_24BIT)\n+\t\t\tregmap_update_bits(i2s->regmap, I2S_REG_CFG0,\n+\t\t\t\t\tI2S_REG_CFG0_DATA_24, 0);\n+\t\tbreak;\n+\tcase 24:\n+\t\tif (i2s->flags & RALINK_FLAGS_24BIT) {\n+\t\t\tregmap_update_bits(i2s->regmap, I2S_REG_CFG0,\n+\t\t\t\t\tI2S_REG_CFG0_DATA_24,\n+\t\t\t\t\tI2S_REG_CFG0_DATA_24);\n+\t\t\tbreak;\n+\t\t}\n+\t\treturn -EINVAL;\n+\tdefault:\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tswitch (params_channels(params)) {\n+\tcase 2:\n+\t\tbreak;\n+\tdefault:\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (i2s->flags & RALINK_FLAGS_ENDIAN) {\n+\t\t/* system endian */\n+#ifdef SNDRV_LITTLE_ENDIAN\n+\t\tregmap_update_bits(i2s->regmap, I2S_REG_CFG0,\n+\t\t\t\tI2S_REG_CFG0_SYS_BE, 0);\n+#else\n+\t\tregmap_update_bits(i2s->regmap, I2S_REG_CFG0,\n+\t\t\t\tI2S_REG_CFG0_SYS_BE,\n+\t\t\t\tI2S_REG_CFG0_SYS_BE);\n+#endif\n+\n+\t\t/* data endian */\n+\t\tswitch (params_format(params)) {\n+\t\tcase SNDRV_PCM_FORMAT_S16_LE:\n+\t\tcase SNDRV_PCM_FORMAT_S24_LE:\n+\t\t\tregmap_update_bits(i2s->regmap, I2S_REG_CFG0,\n+\t\t\t\t\tI2S_REG_CFG0_FMT_LE,\n+\t\t\t\t\tI2S_REG_CFG0_FMT_LE);\n+\t\t\tbreak;\n+\t\tcase SNDRV_PCM_FORMAT_S16_BE:\n+\t\tcase SNDRV_PCM_FORMAT_S24_BE:\n+\t\t\tregmap_update_bits(i2s->regmap, I2S_REG_CFG0,\n+\t\t\t\t\tI2S_REG_CFG0_FMT_LE, 0);\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t}\n+\n+\t/* setup bclk rate */\n+\tif (i2s->flags & RALINK_FLAGS_TXONLY)\n+\t\tret = ralink_i2s_set_sys_bclk(dai, width, params_rate(params));\n+\telse\n+\t\tret = ralink_i2s_set_bclk(dai, width, params_rate(params));\n+\n+\treturn ret;\n+}\n+\n+static int ralink_i2s_trigger(struct snd_pcm_substream *substream, int cmd,\n+\t\tstruct snd_soc_dai *dai)\n+{\n+\tstruct ralink_i2s *i2s = snd_soc_dai_get_drvdata(dai);\n+\tunsigned int mask, val;\n+\n+\tif (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)\n+\t\tmask = I2S_REG_CFG0_TX_EN;\n+\telse\n+\t\tmask = I2S_REG_CFG0_RX_EN;\n+\n+\tswitch (cmd) {\n+\tcase SNDRV_PCM_TRIGGER_START:\n+\tcase SNDRV_PCM_TRIGGER_RESUME:\n+\tcase SNDRV_PCM_TRIGGER_PAUSE_RELEASE:\n+\t\tval = mask;\n+\t\tbreak;\n+\tcase SNDRV_PCM_TRIGGER_STOP:\n+\tcase SNDRV_PCM_TRIGGER_SUSPEND:\n+\tcase SNDRV_PCM_TRIGGER_PAUSE_PUSH:\n+\t\tval = 0;\n+\t\tbreak;\n+\tdefault:\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tregmap_update_bits(i2s->regmap, I2S_REG_CFG0, mask, val);\n+\n+\treturn 0;\n+}\n+\n+static void ralink_i2s_init_dma_data(struct ralink_i2s *i2s,\n+\t\tstruct resource *res)\n+{\n+\tstruct snd_dmaengine_dai_dma_data *dma_data;\n+\n+\t/* Playback */\n+\tdma_data = &i2s->playback_dma_data;\n+\tdma_data->addr = res->start + I2S_REG_WREG;\n+\tdma_data->addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;\n+\tdma_data->maxburst = 1;\n+\tdma_data->slave_id = i2s->txdma_req;\n+\n+\tif (i2s->flags & RALINK_FLAGS_TXONLY)\n+\t\treturn;\n+\n+\t/* Capture */\n+\tdma_data = &i2s->capture_dma_data;\n+\tdma_data->addr = res->start + I2S_REG_RREG;\n+\tdma_data->addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;\n+\tdma_data->maxburst = 1;\n+\tdma_data->slave_id = i2s->rxdma_req;\n+}\n+\n+static int ralink_i2s_dai_probe(struct snd_soc_dai *dai)\n+{\n+\tstruct ralink_i2s *i2s = snd_soc_dai_get_drvdata(dai);\n+\n+\tsnd_soc_dai_init_dma_data(dai, &i2s->playback_dma_data,\n+\t\t\t&i2s->capture_dma_data);\n+\n+\treturn 0;\n+}\n+\n+static int ralink_i2s_dai_remove(struct snd_soc_dai *dai)\n+{\n+\treturn 0;\n+}\n+\n+static const struct snd_soc_dai_ops ralink_i2s_dai_ops = {\n+\t.set_sysclk = ralink_i2s_set_sysclk,\n+\t.set_fmt = ralink_i2s_set_fmt,\n+\t.startup = ralink_i2s_startup,\n+\t.shutdown = ralink_i2s_shutdown,\n+\t.hw_params = ralink_i2s_hw_params,\n+\t.trigger = ralink_i2s_trigger,\n+};\n+\n+static struct snd_soc_dai_driver ralink_i2s_dai = {\n+\t.name = DRV_NAME,\n+\t.probe = ralink_i2s_dai_probe,\n+\t.remove = ralink_i2s_dai_remove,\n+\t.ops = &ralink_i2s_dai_ops,\n+\t.capture = {\n+\t\t.stream_name = \"I2S Capture\",\n+\t\t.channels_min = 2,\n+\t\t.channels_max = 2,\n+\t\t.rate_min = 5512,\n+\t\t.rate_max = 192000,\n+\t\t.rates = SNDRV_PCM_RATE_CONTINUOUS,\n+\t\t.formats = SNDRV_PCM_FMTBIT_S16_LE,\n+\t},\n+\t.playback = {\n+\t\t.stream_name = \"I2S Playback\",\n+\t\t.channels_min = 2,\n+\t\t.channels_max = 2,\n+\t\t.rate_min = 5512,\n+\t\t.rate_max = 192000,\n+\t\t.rates = SNDRV_PCM_RATE_CONTINUOUS,\n+\t\t.formats = SNDRV_PCM_FMTBIT_S16_LE,\n+\t},\n+\t.symmetric_rates = 1,\n+};\n+\n+static struct snd_pcm_hardware ralink_pcm_hardware = {\n+\t.info = SNDRV_PCM_INFO_MMAP |\n+\t\tSNDRV_PCM_INFO_MMAP_VALID |\n+\t\tSNDRV_PCM_INFO_INTERLEAVED |\n+\t\tSNDRV_PCM_INFO_BLOCK_TRANSFER,\n+\t.formats = SNDRV_PCM_FMTBIT_S16_LE,\n+\t.channels_min\t\t= 2,\n+\t.channels_max\t\t= 2,\n+\t.period_bytes_min\t= PAGE_SIZE,\n+\t.period_bytes_max\t= PAGE_SIZE * 2,\n+\t.periods_min\t\t= 2,\n+\t.periods_max\t\t= 128,\n+\t.buffer_bytes_max\t= 128 * 1024,\n+\t.fifo_size\t\t= RALINK_I2S_FIFO_SIZE,\n+};\n+\n+static const struct snd_dmaengine_pcm_config ralink_dmaengine_pcm_config = {\n+\t.prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,\n+\t.pcm_hardware = &ralink_pcm_hardware,\n+\t.prealloc_buffer_size = 256 * PAGE_SIZE,\n+};\n+\n+static const struct snd_soc_component_driver ralink_i2s_component = {\n+\t.name = DRV_NAME,\n+};\n+\n+static bool ralink_i2s_readable_reg(struct device *dev, unsigned int reg)\n+{\n+\treturn true;\n+}\n+\n+static bool ralink_i2s_volatile_reg(struct device *dev, unsigned int reg)\n+{\n+\tswitch (reg) {\n+\tcase I2S_REG_INT_STATUS:\n+\tcase I2S_REG_FF_STATUS:\n+\t\treturn true;\n+\t}\n+\treturn false;\n+}\n+\n+static bool ralink_i2s_writeable_reg(struct device *dev, unsigned int reg)\n+{\n+\tswitch (reg) {\n+\tcase I2S_REG_FF_STATUS:\n+\tcase I2S_REG_RREG:\n+\t\treturn false;\n+\t}\n+\treturn true;\n+}\n+\n+static const struct regmap_config ralink_i2s_regmap_config = {\n+\t.reg_bits = 32,\n+\t.reg_stride = 4,\n+\t.val_bits = 32,\n+\t.writeable_reg = ralink_i2s_writeable_reg,\n+\t.readable_reg = ralink_i2s_readable_reg,\n+\t.volatile_reg = ralink_i2s_volatile_reg,\n+\t.max_register = I2S_REG_DIVINT,\n+};\n+\n+#if (RALINK_I2S_INT_EN)\n+static irqreturn_t ralink_i2s_irq(int irq, void *devid)\n+{\n+\tstruct ralink_i2s *i2s = devid;\n+\tu32 status;\n+\n+\tregmap_read(i2s->regmap, I2S_REG_INT_STATUS, &status);\n+\tif (unlikely(!status))\n+\t\treturn IRQ_NONE;\n+\n+\t/* tx stats */\n+\tif (status & I2S_REG_INT_TX_MASK) {\n+\t\tif (status & I2S_REG_INT_TX_THRES)\n+\t\t\ti2s->txstats.belowthres++;\n+\t\tif (status & I2S_REG_INT_TX_UNRUN)\n+\t\t\ti2s->txstats.underrun++;\n+\t\tif (status & I2S_REG_INT_TX_OVRUN)\n+\t\t\ti2s->txstats.overrun++;\n+\t\tif (status & I2S_REG_INT_TX_FAULT)\n+\t\t\ti2s->txstats.dmafault++;\n+\t}\n+\n+\t/* rx stats */\n+\tif (status & I2S_REG_INT_RX_MASK) {\n+\t\tif (status & I2S_REG_INT_RX_THRES)\n+\t\t\ti2s->rxstats.belowthres++;\n+\t\tif (status & I2S_REG_INT_RX_UNRUN)\n+\t\t\ti2s->rxstats.underrun++;\n+\t\tif (status & I2S_REG_INT_RX_OVRUN)\n+\t\t\ti2s->rxstats.overrun++;\n+\t\tif (status & I2S_REG_INT_RX_FAULT)\n+\t\t\ti2s->rxstats.dmafault++;\n+\t}\n+\n+\t/* clean status bits */\n+\tregmap_write(i2s->regmap, I2S_REG_INT_STATUS, status);\n+\n+\treturn IRQ_HANDLED;\n+}\n+#endif\n+\n+#if IS_ENABLED(CONFIG_DEBUG_FS)\n+static int ralink_i2s_stats_show(struct seq_file *s, void *unused)\n+{\n+        struct ralink_i2s *i2s = s->private;\n+\n+\tseq_printf(s, \"tx stats\\n\");\n+\tseq_printf(s, \"\\tbelow threshold\\t%u\\n\", i2s->txstats.belowthres);\n+\tseq_printf(s, \"\\tunder run\\t%u\\n\", i2s->txstats.underrun);\n+\tseq_printf(s, \"\\tover run\\t%u\\n\", i2s->txstats.overrun);\n+\tseq_printf(s, \"\\tdma fault\\t%u\\n\", i2s->txstats.dmafault);\n+\n+\tseq_printf(s, \"rx stats\\n\");\n+\tseq_printf(s, \"\\tbelow threshold\\t%u\\n\", i2s->rxstats.belowthres);\n+\tseq_printf(s, \"\\tunder run\\t%u\\n\", i2s->rxstats.underrun);\n+\tseq_printf(s, \"\\tover run\\t%u\\n\", i2s->rxstats.overrun);\n+\tseq_printf(s, \"\\tdma fault\\t%u\\n\", i2s->rxstats.dmafault);\n+\n+\tralink_i2s_dump_regs(i2s);\n+\n+\treturn 0;\n+}\n+\n+static int ralink_i2s_stats_open(struct inode *inode, struct file *file)\n+{\n+        return single_open(file, ralink_i2s_stats_show, inode->i_private);\n+}\n+\n+static const struct file_operations ralink_i2s_stats_ops = {\n+        .open = ralink_i2s_stats_open,\n+        .read = seq_read,\n+        .llseek = seq_lseek,\n+        .release = single_release,\n+};\n+\n+static inline int ralink_i2s_debugfs_create(struct ralink_i2s *i2s)\n+{\n+        i2s->dbg_dir = debugfs_create_dir(dev_name(i2s->dev), NULL);\n+        if (!i2s->dbg_dir)\n+                return -ENOMEM;\n+\n+        i2s->dbg_stats = debugfs_create_file(\"stats\", S_IRUGO,\n+                        i2s->dbg_dir, i2s, &ralink_i2s_stats_ops);\n+        if (!i2s->dbg_stats) {\n+                debugfs_remove(i2s->dbg_dir);\n+                return -ENOMEM;\n+        }\n+\n+        return 0;\n+}\n+\n+static inline void ralink_i2s_debugfs_remove(struct ralink_i2s *i2s)\n+{\n+\tdebugfs_remove(i2s->dbg_stats);\n+\tdebugfs_remove(i2s->dbg_dir);\n+}\n+#else\n+static inline int ralink_i2s_debugfs_create(struct ralink_i2s *i2s)\n+{\n+\treturn 0;\n+}\n+\n+static inline void ralink_i2s_debugfs_remove(struct ralink_i2s *i2s)\n+{\n+}\n+#endif\n+\n+/*\n+ * TODO: these refclk setup functions should use\n+ * clock framework instead. hardcode it now.\n+ */\n+static void rt3350_refclk_setup(void)\n+{\n+\tuint32_t data;\n+\n+\t/* set refclk output 12Mhz clock */\n+\tdata = rt_sysc_r32(0x2c);\n+\tdata |= (0x1 << 8);\n+\trt_sysc_w32(data, 0x2c);\n+}\n+\n+static void rt3883_refclk_setup(void)\n+{\n+\tuint32_t data;\n+\n+\t/* set refclk output 12Mhz clock */\n+\tdata = rt_sysc_r32(0x2c);\n+\tdata &= ~(0x3 << 13);\n+\tdata |= (0x1 << 13);\n+\trt_sysc_w32(data, 0x2c);\n+}\n+\n+static void rt3552_refclk_setup(void)\n+{\n+\tuint32_t data;\n+\n+\t/* set refclk output 12Mhz clock */\n+\tdata = rt_sysc_r32(0x2c);\n+\tdata &= ~(0xf << 8);\n+\tdata |= (0x3 << 8);\n+\trt_sysc_w32(data, 0x2c);\n+}\n+\n+static void mt7620_refclk_setup(void)\n+{\n+\tuint32_t data;\n+\n+\t/* set refclk output 12Mhz clock */\n+\tdata = rt_sysc_r32(0x2c);\n+\tdata &= ~(0x7 << 9);\n+\tdata |= 0x1 << 9;\n+\trt_sysc_w32(data, 0x2c);\n+}\n+\n+static void mt7621_refclk_setup(void)\n+{\n+\tuint32_t data;\n+\n+\t/* set refclk output 12Mhz clock */\n+\tdata = rt_sysc_r32(0x2c);\n+\tdata &= ~(0x1f << 18);\n+\tdata |= (0x19 << 18);\n+\tdata &= ~(0x1f << 12);\n+\tdata |= (0x1 << 12);\n+\tdata &= ~(0x7 << 9);\n+\tdata |= (0x5 << 9);\n+\trt_sysc_w32(data, 0x2c);\n+}\n+\n+static void mt7628_refclk_setup(void)\n+{\n+\tuint32_t data;\n+\n+\t/* set i2s and refclk digital pad */\n+\tdata = rt_sysc_r32(0x3c);\n+\tdata |= 0x1f;\n+\trt_sysc_w32(data, 0x3c);\n+\n+\t/* Adjust REFCLK0's driving strength */\n+\tdata = rt_sysc_r32(0x1354);\n+\tdata &= ~(0x1 << 5);\n+\trt_sysc_w32(data, 0x1354);\n+\tdata = rt_sysc_r32(0x1364);\n+\tdata |= ~(0x1 << 5);\n+\trt_sysc_w32(data, 0x1364);\n+\n+\t/* set refclk output 12Mhz clock */\n+\tdata = rt_sysc_r32(0x2c);\n+\tdata &= ~(0x7 << 9);\n+\tdata |= 0x1 << 9;\n+\trt_sysc_w32(data, 0x2c);\n+}\n+\n+struct rt_i2s_data {\n+\tu32 flags;\n+\tvoid (*refclk_setup)(void);\n+};\n+\n+struct rt_i2s_data rt3050_i2s_data = { .flags = RALINK_FLAGS_TXONLY };\n+struct rt_i2s_data rt3350_i2s_data = { .flags = RALINK_FLAGS_TXONLY,\n+\t.refclk_setup = rt3350_refclk_setup };\n+struct rt_i2s_data rt3883_i2s_data = {\n+\t.flags = (RALINK_FLAGS_LEFT_J | RALINK_FLAGS_RIGHT_J),\n+\t.refclk_setup = rt3883_refclk_setup };\n+struct rt_i2s_data rt3352_i2s_data = { .refclk_setup = rt3552_refclk_setup};\n+struct rt_i2s_data mt7620_i2s_data = { .refclk_setup = mt7620_refclk_setup};\n+struct rt_i2s_data mt7621_i2s_data = { .refclk_setup = mt7621_refclk_setup};\n+struct rt_i2s_data mt7628_i2s_data = {\n+\t.flags = (RALINK_FLAGS_ENDIAN | RALINK_FLAGS_24BIT |\n+\t\t\tRALINK_FLAGS_LEFT_J),\n+\t.refclk_setup = mt7628_refclk_setup};\n+\n+static const struct of_device_id ralink_i2s_match_table[] = {\n+\t{ .compatible = \"ralink,rt3050-i2s\",\n+\t\t.data = (void *)&rt3050_i2s_data },\n+\t{ .compatible = \"ralink,rt3350-i2s\",\n+\t\t.data = (void *)&rt3350_i2s_data },\n+\t{ .compatible = \"ralink,rt3883-i2s\",\n+\t\t.data = (void *)&rt3883_i2s_data },\n+\t{ .compatible = \"ralink,rt3352-i2s\",\n+\t\t.data = (void *)&rt3352_i2s_data },\n+\t{ .compatible = \"mediatek,mt7620-i2s\",\n+\t\t.data = (void *)&mt7620_i2s_data },\n+\t{ .compatible = \"mediatek,mt7621-i2s\",\n+\t\t.data = (void *)&mt7621_i2s_data },\n+\t{ .compatible = \"mediatek,mt7628-i2s\",\n+\t\t.data = (void *)&mt7628_i2s_data },\n+\t{},\n+};\n+MODULE_DEVICE_TABLE(of, ralink_i2s_match_table);\n+\n+static int ralink_i2s_probe(struct platform_device *pdev)\n+{\n+\tconst struct of_device_id *match;\n+\tstruct device_node *np = pdev->dev.of_node;\n+\tstruct ralink_i2s *i2s;\n+\tstruct resource *res;\n+\tint irq, ret;\n+\tu32 dma_req;\n+\tstruct rt_i2s_data *data;\n+\n+\ti2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);\n+\tif (!i2s)\n+\t\treturn -ENOMEM;\n+\n+\tplatform_set_drvdata(pdev, i2s);\n+\ti2s->dev = &pdev->dev;\n+\n+\tmatch = of_match_device(ralink_i2s_match_table, &pdev->dev);\n+\tif (!match)\n+\t\treturn -EINVAL;\n+\tdata = (struct rt_i2s_data *)match->data;\n+\ti2s->flags = data->flags;\n+\t/* setup out 12Mhz refclk to codec as mclk */\n+\tif (data->refclk_setup)\n+\t\tdata->refclk_setup();\n+\n+\tif (of_property_read_u32(np, \"txdma-req\", &dma_req)) {\n+\t\tdev_err(&pdev->dev, \"no txdma-req define\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\ti2s->txdma_req = (u16)dma_req;\n+\tif (!(i2s->flags & RALINK_FLAGS_TXONLY)) {\n+\t\tif (of_property_read_u32(np, \"rxdma-req\", &dma_req)) {\n+\t\t\tdev_err(&pdev->dev, \"no rxdma-req define\\n\");\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t\ti2s->rxdma_req = (u16)dma_req;\n+\t}\n+\n+\tres = platform_get_resource(pdev, IORESOURCE_MEM, 0);\n+\ti2s->regs = devm_ioremap_resource(&pdev->dev, res);\n+\tif (IS_ERR(i2s->regs))\n+\t\treturn PTR_ERR(i2s->regs);\n+\n+\ti2s->regmap = devm_regmap_init_mmio(&pdev->dev, i2s->regs,\n+\t\t\t&ralink_i2s_regmap_config);\n+\tif (IS_ERR(i2s->regmap)) {\n+\t\tdev_err(&pdev->dev, \"regmap init failed\\n\");\n+\t\treturn PTR_ERR(i2s->regmap);\n+\t}\n+\n+        irq = platform_get_irq(pdev, 0);\n+        if (irq < 0) {\n+                dev_err(&pdev->dev, \"failed to get irq\\n\");\n+                return -EINVAL;\n+        }\n+\n+#if (RALINK_I2S_INT_EN)\n+\tret = devm_request_irq(&pdev->dev, irq, ralink_i2s_irq,\n+\t\t\t0, dev_name(&pdev->dev), i2s);\n+\tif (ret) {\n+\t\tdev_err(&pdev->dev, \"failed to request irq\\n\");\n+\t\treturn ret;\n+\t}\n+#endif\n+\n+\ti2s->clk = devm_clk_get(&pdev->dev, NULL);\n+\tif (IS_ERR(i2s->clk)) {\n+\t\tdev_err(&pdev->dev, \"no clock defined\\n\");\n+\t\treturn PTR_ERR(i2s->clk);\n+\t}\n+\n+\tret = clk_prepare_enable(i2s->clk);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tralink_i2s_init_dma_data(i2s, res);\n+\n+\tdevice_reset(&pdev->dev);\n+\n+\tret = ralink_i2s_debugfs_create(i2s);\n+\tif (ret) {\n+\t\tdev_err(&pdev->dev, \"create debugfs failed\\n\");\n+\t\tgoto err_clk_disable;\n+\t}\n+\n+\t/* enable 24bits support */\n+\tif (i2s->flags & RALINK_FLAGS_24BIT) {\n+\t\tralink_i2s_dai.capture.formats |= SNDRV_PCM_FMTBIT_S24_LE;\n+\t\tralink_i2s_dai.playback.formats |= SNDRV_PCM_FMTBIT_S24_LE;\n+\t}\n+\n+\t/* enable big endian support */\n+\tif (i2s->flags & RALINK_FLAGS_ENDIAN) {\n+\t\tralink_i2s_dai.capture.formats |= SNDRV_PCM_FMTBIT_S16_BE;\n+\t\tralink_i2s_dai.playback.formats |= SNDRV_PCM_FMTBIT_S16_BE;\n+\t\tralink_pcm_hardware.formats |= SNDRV_PCM_FMTBIT_S16_BE;\n+\t\tif (i2s->flags & RALINK_FLAGS_24BIT) {\n+\t\t\tralink_i2s_dai.capture.formats |=\n+\t\t\t\tSNDRV_PCM_FMTBIT_S24_BE;\n+\t\t\tralink_i2s_dai.playback.formats |=\n+\t\t\t\tSNDRV_PCM_FMTBIT_S24_BE;\n+\t\t\tralink_pcm_hardware.formats |=\n+\t\t\t\tSNDRV_PCM_FMTBIT_S24_BE;\n+\t\t}\n+\t}\n+\n+\t/* disable capture support */\n+\tif (i2s->flags & RALINK_FLAGS_TXONLY)\n+\t\tmemset(&ralink_i2s_dai.capture, sizeof(ralink_i2s_dai.capture),\n+\t\t\t\t0);\n+\n+\tret = devm_snd_soc_register_component(&pdev->dev, &ralink_i2s_component,\n+\t\t\t&ralink_i2s_dai, 1);\n+\tif (ret)\n+\t\tgoto err_debugfs;\n+\n+\tret = devm_snd_dmaengine_pcm_register(&pdev->dev,\n+\t\t\t&ralink_dmaengine_pcm_config,\n+\t\t\tSND_DMAENGINE_PCM_FLAG_COMPAT);\n+\tif (ret)\n+\t\tgoto err_debugfs;\n+\n+\tdev_info(i2s->dev, \"mclk %luMHz\\n\", clk_get_rate(i2s->clk) / 1000000);\n+\n+\treturn 0;\n+\n+err_debugfs:\n+\tralink_i2s_debugfs_remove(i2s);\n+\n+err_clk_disable:\n+\tclk_disable_unprepare(i2s->clk);\n+\n+\treturn ret;\n+}\n+\n+static int ralink_i2s_remove(struct platform_device *pdev)\n+{\n+\tstruct ralink_i2s *i2s = platform_get_drvdata(pdev);\n+\n+\tralink_i2s_debugfs_remove(i2s);\n+\tclk_disable_unprepare(i2s->clk);\n+\n+\treturn 0;\n+}\n+\n+static struct platform_driver ralink_i2s_driver = {\n+\t.probe = ralink_i2s_probe,\n+\t.remove = ralink_i2s_remove,\n+\t.driver = {\n+\t\t.name = DRV_NAME,\n+\t\t.of_match_table = ralink_i2s_match_table,\n+\t},\n+};\n+module_platform_driver(ralink_i2s_driver);\n+\n+MODULE_AUTHOR(\"Lars-Peter Clausen, <lars@metafoo.de>\");\n+MODULE_DESCRIPTION(\"Ralink/MediaTek I2S driver\");\n+MODULE_LICENSE(\"GPL\");\n+MODULE_ALIAS(\"platform:\" DRV_NAME);\n"
  },
  {
    "path": "target/linux/ramips/patches-5.10/840-serial-add-ugly-custom-baud-rate-hack.patch",
    "content": "From a7eb46e0ea4a11e4dfb56ab129bf816d1059a6c5 Mon Sep 17 00:00:00 2001\nFrom: John Crispin <blogic@openwrt.org>\nDate: Mon, 7 Dec 2015 17:31:08 +0100\nSubject: [PATCH 51/53] serial: add ugly custom baud rate hack\n\nSigned-off-by: John Crispin <blogic@openwrt.org>\n---\n drivers/tty/serial/serial_core.c |    3 +++\n 1 file changed, 3 insertions(+)\n\n--- a/drivers/tty/serial/serial_core.c\n+++ b/drivers/tty/serial/serial_core.c\n@@ -425,6 +425,9 @@ uart_get_baud_rate(struct uart_port *por\n \t\tbreak;\n \t}\n \n+\tif (tty_termios_baud_rate(termios) == 2500000)\n+\t\treturn 250000;\n+\n \tfor (try = 0; try < 2; try++) {\n \t\tbaud = tty_termios_baud_rate(termios);\n \n"
  },
  {
    "path": "target/linux/ramips/patches-5.10/845-pwm-add-mediatek-support.patch",
    "content": "From fc8f96309c21c1bc3276427309cd7d361347d66e Mon Sep 17 00:00:00 2001\nFrom: John Crispin <blogic@openwrt.org>\nDate: Mon, 7 Dec 2015 17:16:50 +0100\nSubject: [PATCH 52/53] pwm: add mediatek support\n\nSigned-off-by: John Crispin <blogic@openwrt.org>\n---\n drivers/pwm/Kconfig        |    9 +++\n drivers/pwm/Makefile       |    1 +\n drivers/pwm/pwm-mediatek.c |  173 ++++++++++++++++++++++++++++++++++++++++++++\n 3 files changed, 183 insertions(+)\n create mode 100644 drivers/pwm/pwm-mediatek.c\n\n--- a/drivers/pwm/Kconfig\n+++ b/drivers/pwm/Kconfig\n@@ -339,6 +339,15 @@ config PWM_MEDIATEK\n \t  To compile this driver as a module, choose M here: the module\n \t  will be called pwm-mediatek.\n \n+config PWM_MEDIATEK_RAMIPS\n+\ttristate \"Mediatek PWM support\"\n+\tdepends on RALINK && OF\n+\thelp\n+\t  Generic PWM framework driver for Mediatek ARM SoC.\n+\n+\t  To compile this driver as a module, choose M here: the module\n+\t  will be called pwm-mxs.\n+\n config PWM_MXS\n \ttristate \"Freescale MXS PWM support\"\n \tdepends on OF\n--- a/drivers/pwm/Makefile\n+++ b/drivers/pwm/Makefile\n@@ -30,6 +30,7 @@ obj-$(CONFIG_PWM_LPSS_PCI)\t+= pwm-lpss-p\n obj-$(CONFIG_PWM_LPSS_PLATFORM)\t+= pwm-lpss-platform.o\n obj-$(CONFIG_PWM_MESON)\t\t+= pwm-meson.o\n obj-$(CONFIG_PWM_MEDIATEK)\t+= pwm-mediatek.o\n+obj-$(CONFIG_PWM_MEDIATEK_RAMIPS)\t+= pwm-mediatek-ramips.o\n obj-$(CONFIG_PWM_MTK_DISP)\t+= pwm-mtk-disp.o\n obj-$(CONFIG_PWM_MXS)\t\t+= pwm-mxs.o\n obj-$(CONFIG_PWM_OMAP_DMTIMER)\t+= pwm-omap-dmtimer.o\n--- /dev/null\n+++ b/drivers/pwm/pwm-mediatek-ramips.c\n@@ -0,0 +1,173 @@\n+/*\n+ * Mediatek Pulse Width Modulator driver\n+ *\n+ * Copyright (C) 2015 John Crispin <blogic@openwrt.org>\n+ *\n+ * This file is licensed under the terms of the GNU General Public\n+ * License version 2. This program is licensed \"as is\" without any\n+ * warranty of any kind, whether express or implied.\n+ */\n+\n+#include <linux/err.h>\n+#include <linux/io.h>\n+#include <linux/ioport.h>\n+#include <linux/kernel.h>\n+#include <linux/module.h>\n+#include <linux/of.h>\n+#include <linux/platform_device.h>\n+#include <linux/pwm.h>\n+#include <linux/slab.h>\n+#include <linux/types.h>\n+\n+#define NUM_PWM\t\t4\n+\n+/* PWM registers and bits definitions */\n+#define PWMCON\t\t\t0x00\n+#define PWMHDUR\t\t\t0x04\n+#define PWMLDUR\t\t\t0x08\n+#define PWMGDUR\t\t\t0x0c\n+#define PWMWAVENUM\t\t0x28\n+#define PWMDWIDTH\t\t0x2c\n+#define PWMTHRES\t\t0x30\n+\n+/**\n+ * struct mtk_pwm_chip - struct representing pwm chip\n+ *\n+ * @mmio_base: base address of pwm chip\n+ * @chip: linux pwm chip representation\n+ */\n+struct mtk_pwm_chip {\n+\tvoid __iomem *mmio_base;\n+\tstruct pwm_chip chip;\n+};\n+\n+static inline struct mtk_pwm_chip *to_mtk_pwm_chip(struct pwm_chip *chip)\n+{\n+\treturn container_of(chip, struct mtk_pwm_chip, chip);\n+}\n+\n+static inline u32 mtk_pwm_readl(struct mtk_pwm_chip *chip, unsigned int num,\n+\t\t\t\t  unsigned long offset)\n+{\n+\treturn ioread32(chip->mmio_base + 0x10 + (num * 0x40) + offset);\n+}\n+\n+static inline void mtk_pwm_writel(struct mtk_pwm_chip *chip,\n+\t\t\t\t    unsigned int num, unsigned long offset,\n+\t\t\t\t    unsigned long val)\n+{\n+\tiowrite32(val, chip->mmio_base + 0x10 + (num * 0x40) + offset);\n+}\n+\n+static int mtk_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,\n+\t\t\t    int duty_ns, int period_ns)\n+{\n+\tstruct mtk_pwm_chip *pc = to_mtk_pwm_chip(chip);\n+\tu32 resolution = 100 / 4;\n+\tu32 clkdiv = 0;\n+\n+\twhile (period_ns / resolution  > 8191) {\n+\t\tclkdiv++;\n+\t\tresolution *= 2;\n+\t}\n+\n+\tif (clkdiv > 7)\n+\t\treturn -1;\n+\n+\tmtk_pwm_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | BIT(3) | clkdiv);\n+\tmtk_pwm_writel(pc, pwm->hwpwm, PWMDWIDTH, period_ns / resolution);\n+\tmtk_pwm_writel(pc, pwm->hwpwm, PWMTHRES, duty_ns / resolution);\n+\treturn 0;\n+}\n+\n+static int mtk_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)\n+{\n+\tstruct mtk_pwm_chip *pc = to_mtk_pwm_chip(chip);\n+\tu32 val;\n+\n+\tval = ioread32(pc->mmio_base);\n+\tval |= BIT(pwm->hwpwm);\n+\tiowrite32(val, pc->mmio_base);\n+\n+\treturn 0;\n+}\n+\n+static void mtk_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)\n+{\n+\tstruct mtk_pwm_chip *pc = to_mtk_pwm_chip(chip);\n+\tu32 val;\n+\n+\tval = ioread32(pc->mmio_base);\n+\tval &= ~BIT(pwm->hwpwm);\n+\tiowrite32(val, pc->mmio_base);\n+}\n+\n+static const struct pwm_ops mtk_pwm_ops = {\n+\t.config = mtk_pwm_config,\n+\t.enable = mtk_pwm_enable,\n+\t.disable = mtk_pwm_disable,\n+\t.owner = THIS_MODULE,\n+};\n+\n+static int mtk_pwm_probe(struct platform_device *pdev)\n+{\n+\tstruct mtk_pwm_chip *pc;\n+\tstruct resource *r;\n+\tint ret;\n+\n+\tpc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);\n+\tif (!pc)\n+\t\treturn -ENOMEM;\n+\n+\tr = platform_get_resource(pdev, IORESOURCE_MEM, 0);\n+\tpc->mmio_base = devm_ioremap_resource(&pdev->dev, r);\n+\tif (IS_ERR(pc->mmio_base))\n+\t\treturn PTR_ERR(pc->mmio_base);\n+\n+\tplatform_set_drvdata(pdev, pc);\n+\n+\tpc->chip.dev = &pdev->dev;\n+\tpc->chip.ops = &mtk_pwm_ops;\n+\tpc->chip.base = -1;\n+\tpc->chip.npwm = NUM_PWM;\n+\n+\tret = pwmchip_add(&pc->chip);\n+\tif (ret < 0)\n+\t\tdev_err(&pdev->dev, \"pwmchip_add() failed: %d\\n\", ret);\n+\n+\treturn ret;\n+}\n+\n+static int mtk_pwm_remove(struct platform_device *pdev)\n+{\n+\tstruct mtk_pwm_chip *pc = platform_get_drvdata(pdev);\n+\tint i;\n+\n+\tfor (i = 0; i < NUM_PWM; i++)\n+\t\tpwm_disable(&pc->chip.pwms[i]);\n+\n+\treturn pwmchip_remove(&pc->chip);\n+}\n+\n+static const struct of_device_id mtk_pwm_of_match[] = {\n+\t{ .compatible = \"mediatek,mt7628-pwm\" },\n+\t{ }\n+};\n+\n+MODULE_DEVICE_TABLE(of, mtk_pwm_of_match);\n+\n+static struct platform_driver mtk_pwm_driver = {\n+\t.driver = {\n+\t\t.name = \"mtk-pwm\",\n+\t\t.owner = THIS_MODULE,\n+\t\t.of_match_table = mtk_pwm_of_match,\n+\t},\n+\t.probe = mtk_pwm_probe,\n+\t.remove = mtk_pwm_remove,\n+};\n+\n+module_platform_driver(mtk_pwm_driver);\n+\n+MODULE_LICENSE(\"GPL\");\n+MODULE_AUTHOR(\"John Crispin <blogic@openwrt.org>\");\n+MODULE_ALIAS(\"platform:mtk-pwm\");\n"
  },
  {
    "path": "target/linux/ramips/patches-5.10/850-awake-rt305x-dwc2-controller.patch",
    "content": "--- a/drivers/usb/dwc2/platform.c\n+++ b/drivers/usb/dwc2/platform.c\n@@ -477,6 +477,12 @@ static int dwc2_driver_probe(struct plat\n \tif (retval)\n \t\treturn retval;\n \n+\t/* Enable USB port before any regs access */\n+\tif (readl(hsotg->regs + PCGCTL) & 0x0f) {\n+\t\twritel(0x00, hsotg->regs + PCGCTL);\n+\t\t/* TODO: mdelay(25) here? vendor driver don't use it */\n+\t}\n+\n \thsotg->needs_byte_swap = dwc2_check_core_endianness(hsotg);\n \n \tretval = dwc2_get_dr_mode(hsotg);\n"
  },
  {
    "path": "target/linux/ramips/patches-5.10/855-linkit_bootstrap.patch",
    "content": "--- a/drivers/misc/Makefile\n+++ b/drivers/misc/Makefile\n@@ -50,6 +50,7 @@ obj-$(CONFIG_GENWQE)\t\t+= genwqe/\n obj-$(CONFIG_ECHO)\t\t+= echo/\n obj-$(CONFIG_CXL_BASE)\t\t+= cxl/\n obj-$(CONFIG_PCI_ENDPOINT_TEST)\t+= pci_endpoint_test.o\n+obj-$(CONFIG_SOC_MT7620)\t+= linkit.o\n obj-$(CONFIG_OCXL)\t\t+= ocxl/\n obj-y\t\t\t\t+= cardreader/\n obj-$(CONFIG_PVPANIC)   \t+= pvpanic.o\n--- /dev/null\n+++ b/drivers/misc/linkit.c\n@@ -0,0 +1,84 @@\n+/*\n+ *  This program is free software; you can redistribute it and/or modify\n+ *  it under the terms of the GNU General Public License version 2 as\n+ *  publishhed by the Free Software Foundation.\n+ *\n+ *  Copyright (C) 2015 John Crispin <blogic@openwrt.org>\n+ */\n+\n+#include <linux/module.h>\n+#include <linux/platform_device.h>\n+#include <linux/of.h>\n+#include <linux/mtd/mtd.h>\n+#include <linux/gpio.h>\n+\n+#define LINKIT_LATCH_GPIO\t11\n+\n+struct linkit_hw_data {\n+\tchar board[16];\n+\tchar rev[16];\n+};\n+\n+static void sanify_string(char *s)\n+{\n+\tint i;\n+\n+\tfor (i = 0; i < 15; i++)\n+\t\tif (s[i] <= 0x20)\n+\t\t\ts[i] = '\\0';\n+\ts[15] = '\\0';\n+}\n+\n+static int linkit_probe(struct platform_device *pdev)\n+{\n+\tstruct linkit_hw_data hw;\n+\tstruct mtd_info *mtd;\n+\tsize_t retlen;\n+\tint ret;\n+\n+\tmtd = get_mtd_device_nm(\"factory\");\n+\tif (IS_ERR(mtd))\n+\t\treturn PTR_ERR(mtd);\n+\n+\tret = mtd_read(mtd, 0x400, sizeof(hw), &retlen, (u_char *) &hw);\n+\tput_mtd_device(mtd);\n+\n+\tsanify_string(hw.board);\n+\tsanify_string(hw.rev);\n+\n+\tdev_info(&pdev->dev, \"Version  : %s\\n\", hw.board);\n+\tdev_info(&pdev->dev, \"Revision : %s\\n\", hw.rev);\n+\n+\tif (!strcmp(hw.board, \"LINKITS7688\")) {\n+\t\tdev_info(&pdev->dev, \"setting up bootstrap latch\\n\");\n+\n+\t\tif (devm_gpio_request(&pdev->dev, LINKIT_LATCH_GPIO, \"bootstrap\")) {\n+\t\t\tdev_err(&pdev->dev, \"failed to setup bootstrap gpio\\n\");\n+\t\t\treturn -1;\n+\t\t}\n+\t\tgpio_direction_output(LINKIT_LATCH_GPIO, 0);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static const struct of_device_id linkit_match[] = {\n+\t{ .compatible = \"mediatek,linkit\" },\n+\t{},\n+};\n+MODULE_DEVICE_TABLE(of, linkit_match);\n+\n+static struct platform_driver linkit_driver = {\n+\t.probe = linkit_probe,\n+\t.driver = {\n+\t\t.name = \"mtk-linkit\",\n+\t\t.owner = THIS_MODULE,\n+\t\t.of_match_table = linkit_match,\n+\t},\n+};\n+\n+int __init linkit_init(void)\n+{\n+\treturn platform_driver_register(&linkit_driver);\n+}\n+late_initcall_sync(linkit_init);\n"
  },
  {
    "path": "target/linux/ramips/patches-5.15/100-PCI-mt7621-Add-MediaTek-MT7621-PCIe-host-controller-.patch",
    "content": "From: Sergio Paracuellos <sergio.paracuellos@gmail.com>\nDate: Wed, 22 Sep 2021 07:00:34 +0200\nSubject: [PATCH] PCI: mt7621: Add MediaTek MT7621 PCIe host controller driver\n\nAdd driver for the PCIe controller of the MT7621 SoC.\n\n[bhelgaas: rename from pci-mt7621.c to pcie-mt7621.c; also rename Kconfig\nsymbol from PCI_MT7621 to PCIE_MT7621]\nLink: https://lore.kernel.org/r/20210922050035.18162-3-sergio.paracuellos@gmail.com\nSigned-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>\nSigned-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>\nSigned-off-by: Bjorn Helgaas <bhelgaas@google.com>\nAcked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>\n---\n rename drivers/{staging/mt7621-pci/pci-mt7621.c => pci/controller/pcie-mt7621.c} (95%)\n delete mode 100644 drivers/staging/mt7621-pci/Kconfig\n delete mode 100644 drivers/staging/mt7621-pci/Makefile\n delete mode 100644 drivers/staging/mt7621-pci/TODO\n delete mode 100644 drivers/staging/mt7621-pci/mediatek,mt7621-pci.txt\n\n--- a/arch/mips/ralink/Kconfig\n+++ b/arch/mips/ralink/Kconfig\n@@ -51,7 +51,8 @@ choice\n \t\tselect SYS_SUPPORTS_HIGHMEM\n \t\tselect MIPS_GIC\n \t\tselect CLKSRC_MIPS_GIC\n-\t\tselect HAVE_PCI if PCI_MT7621\n+\t\tselect HAVE_PCI\n+\t\tselect PCI_DRIVERS_GENERIC\n \t\tselect SOC_BUS\n endchoice\n \n--- a/drivers/pci/controller/Kconfig\n+++ b/drivers/pci/controller/Kconfig\n@@ -312,6 +312,14 @@ config PCIE_HISI_ERR\n \t  Say Y here if you want error handling support\n \t  for the PCIe controller's errors on HiSilicon HIP SoCs\n \n+config PCIE_MT7621\n+\ttristate \"MediaTek MT7621 PCIe Controller\"\n+\tdepends on (RALINK && SOC_MT7621) || (MIPS && COMPILE_TEST)\n+\tselect PHY_MT7621_PCI\n+\tdefault SOC_MT7621\n+\thelp\n+\t  This selects a driver for the MediaTek MT7621 PCIe Controller.\n+\n source \"drivers/pci/controller/dwc/Kconfig\"\n source \"drivers/pci/controller/mobiveil/Kconfig\"\n source \"drivers/pci/controller/cadence/Kconfig\"\n--- a/drivers/pci/controller/Makefile\n+++ b/drivers/pci/controller/Makefile\n@@ -37,6 +37,8 @@ obj-$(CONFIG_VMD) += vmd.o\n obj-$(CONFIG_PCIE_BRCMSTB) += pcie-brcmstb.o\n obj-$(CONFIG_PCI_LOONGSON) += pci-loongson.o\n obj-$(CONFIG_PCIE_HISI_ERR) += pcie-hisi-error.o\n+obj-$(CONFIG_PCIE_MT7621) += pcie-mt7621.o\n+\n # pcie-hisi.o quirks are needed even without CONFIG_PCIE_DW\n obj-y\t\t\t\t+= dwc/\n obj-y\t\t\t\t+= mobiveil/\n--- a/drivers/staging/Kconfig\n+++ b/drivers/staging/Kconfig\n@@ -86,8 +86,6 @@ source \"drivers/staging/vc04_services/Kc\n \n source \"drivers/staging/pi433/Kconfig\"\n \n-source \"drivers/staging/mt7621-pci/Kconfig\"\n-\n source \"drivers/staging/mt7621-dma/Kconfig\"\n \n source \"drivers/staging/ralink-gdma/Kconfig\"\n--- a/drivers/staging/Makefile\n+++ b/drivers/staging/Makefile\n@@ -33,7 +33,6 @@ obj-$(CONFIG_KS7010)\t\t+= ks7010/\n obj-$(CONFIG_GREYBUS)\t\t+= greybus/\n obj-$(CONFIG_BCM2835_VCHIQ)\t+= vc04_services/\n obj-$(CONFIG_PI433)\t\t+= pi433/\n-obj-$(CONFIG_PCI_MT7621)\t+= mt7621-pci/\n obj-$(CONFIG_SOC_MT7621)\t+= mt7621-dma/\n obj-$(CONFIG_DMA_RALINK)\t+= ralink-gdma/\n obj-$(CONFIG_SOC_MT7621)\t+= mt7621-dts/\n--- a/drivers/staging/mt7621-pci/Kconfig\n+++ /dev/null\n@@ -1,8 +0,0 @@\n-# SPDX-License-Identifier: GPL-2.0\n-config PCI_MT7621\n-\ttristate \"MediaTek MT7621 PCI Controller\"\n-\tdepends on RALINK\n-\tselect PCI_DRIVERS_GENERIC\n-\thelp\n-\t  This selects a driver for the MediaTek MT7621 PCI Controller.\n-\n--- a/drivers/staging/mt7621-pci/Makefile\n+++ /dev/null\n@@ -1,2 +0,0 @@\n-# SPDX-License-Identifier: GPL-2.0\n-obj-$(CONFIG_PCI_MT7621)       += pci-mt7621.o\n--- a/drivers/staging/mt7621-pci/TODO\n+++ /dev/null\n@@ -1,4 +0,0 @@\n-\n-- general code review and cleanup\n-\n-Cc: NeilBrown <neil@brown.name>\n--- a/drivers/staging/mt7621-pci/mediatek,mt7621-pci.txt\n+++ /dev/null\n@@ -1,104 +0,0 @@\n-MediaTek MT7621 PCIe controller\n-\n-Required properties:\n-- compatible: \"mediatek,mt7621-pci\"\n-- device_type: Must be \"pci\"\n-- reg: Base addresses and lengths of the PCIe subsys and root ports.\n-- bus-range: Range of bus numbers associated with this controller.\n-- #address-cells: Address representation for root ports (must be 3)\n-- pinctrl-names : The pin control state names.\n-- pinctrl-0: The \"default\" pinctrl state.\n-- #size-cells: Size representation for root ports (must be 2)\n-- ranges: Ranges for the PCI memory and I/O regions.\n-- #interrupt-cells: Must be 1\n-- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties.\n-  Please refer to the standard PCI bus binding document for a more detailed\n-  explanation.\n-- status: either \"disabled\" or \"okay\".\n-- resets: Must contain an entry for each entry in reset-names.\n-  See ../reset/reset.txt for details.\n-- reset-names: Must be \"pcie0\", \"pcie1\", \"pcieN\"... based on the number of\n-  root ports.\n-- clocks: Must contain an entry for each entry in clock-names.\n-  See ../clocks/clock-bindings.txt for details.\n-- clock-names: Must be \"pcie0\", \"pcie1\", \"pcieN\"... based on the number of\n-  root ports.\n-- reset-gpios: GPIO specs for the reset pins.\n-\n-In addition, the device tree node must have sub-nodes describing each PCIe port\n-interface, having the following mandatory properties:\n-\n-Required properties:\n-- reg: Only the first four bytes are used to refer to the correct bus number\n-      and device number.\n-- #address-cells: Must be 3\n-- #size-cells: Must be 2\n-- ranges: Sub-ranges distributed from the PCIe controller node. An empty\n-  property is sufficient.\n-- bus-range: Range of bus numbers associated with this port.\n-\n-Example for MT7621:\n-\n-\tpcie: pcie@1e140000 {\n-\t\tcompatible = \"mediatek,mt7621-pci\";\n-        reg = <0x1e140000 0x100    /* host-pci bridge registers */\n-               0x1e142000 0x100    /* pcie port 0 RC control registers */\n-               0x1e143000 0x100    /* pcie port 1 RC control registers */\n-               0x1e144000 0x100>;  /* pcie port 2 RC control registers */\n-\n-\t\t#address-cells = <3>;\n-\t\t#size-cells = <2>;\n-\n-\t\tpinctrl-names = \"default\";\n-\t\tpinctrl-0 = <&pcie_pins>;\n-\n-\t\tdevice_type = \"pci\";\n-\n-\t\tbus-range = <0 255>;\n-\t\tranges = <\n-\t\t\t0x02000000 0 0x00000000 0x60000000 0 0x10000000 /* pci memory */\n-\t\t\t0x01000000 0 0x00000000 0x1e160000 0 0x00010000 /* io space */\n-\t\t>;\n-\n-\t\t#interrupt-cells = <1>;\n-\t\tinterrupt-map-mask = <0xF0000 0 0 1>;\n-\t\tinterrupt-map = <0x10000 0 0 1 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>,\n-\t\t\t\t<0x20000 0 0 1 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>,\n-\t\t\t\t<0x30000 0 0 1 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;\n-\n-\t\tstatus = \"disabled\";\n-\n-\t\tresets = <&rstctrl 24 &rstctrl 25 &rstctrl 26>;\n-\t\treset-names = \"pcie0\", \"pcie1\", \"pcie2\";\n-\t\tclocks = <&clkctrl 24 &clkctrl 25 &clkctrl 26>;\n-\t\tclock-names = \"pcie0\", \"pcie1\", \"pcie2\";\n-\n-\t\treset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>,\n-\t\t\t\t<&gpio 8 GPIO_ACTIVE_LOW>,\n-\t\t\t\t<&gpio 7 GPIO_ACTIVE_LOW>;\n-\n-\t\tpcie@0,0 {\n-\t\t\treg = <0x0000 0 0 0 0>;\n-\t\t\t#address-cells = <3>;\n-\t\t\t#size-cells = <2>;\n-\t\t\tranges;\n-\t\t\tbus-range = <0x00 0xff>;\n-\t\t};\n-\n-\t\tpcie@1,0 {\n-\t\t\treg = <0x0800 0 0 0 0>;\n-\t\t\t#address-cells = <3>;\n-\t\t\t#size-cells = <2>;\n-\t\t\tranges;\n-\t\t\tbus-range = <0x00 0xff>;\n-\t\t};\n-\n-\t\tpcie@2,0 {\n-\t\t\treg = <0x1000 0 0 0 0>;\n-\t\t\t#address-cells = <3>;\n-\t\t\t#size-cells = <2>;\n-\t\t\tranges;\n-\t\t\tbus-range = <0x00 0xff>;\n-\t\t};\n-\t};\n-\n--- a/drivers/staging/mt7621-pci/pci-mt7621.c\n+++ /dev/null\n@@ -1,600 +0,0 @@\n-// SPDX-License-Identifier: GPL-2.0+\n-/*\n- * BRIEF MODULE DESCRIPTION\n- *     PCI init for Ralink RT2880 solution\n- *\n- * Copyright 2007 Ralink Inc. (bruce_chang@ralinktech.com.tw)\n- *\n- * May 2007 Bruce Chang\n- * Initial Release\n- *\n- * May 2009 Bruce Chang\n- * support RT2880/RT3883 PCIe\n- *\n- * May 2011 Bruce Chang\n- * support RT6855/MT7620 PCIe\n- */\n-\n-#include <linux/bitops.h>\n-#include <linux/clk.h>\n-#include <linux/delay.h>\n-#include <linux/gpio/consumer.h>\n-#include <linux/module.h>\n-#include <linux/of.h>\n-#include <linux/of_address.h>\n-#include <linux/of_pci.h>\n-#include <linux/of_platform.h>\n-#include <linux/pci.h>\n-#include <linux/phy/phy.h>\n-#include <linux/platform_device.h>\n-#include <linux/reset.h>\n-#include <linux/sys_soc.h>\n-\n-/* MediaTek specific configuration registers */\n-#define PCIE_FTS_NUM\t\t\t0x70c\n-#define PCIE_FTS_NUM_MASK\t\tGENMASK(15, 8)\n-#define PCIE_FTS_NUM_L0(x)\t\t(((x) & 0xff) << 8)\n-\n-/* Host-PCI bridge registers */\n-#define RALINK_PCI_PCICFG_ADDR\t\t0x0000\n-#define RALINK_PCI_PCIMSK_ADDR\t\t0x000C\n-#define RALINK_PCI_CONFIG_ADDR\t\t0x0020\n-#define RALINK_PCI_CONFIG_DATA\t\t0x0024\n-#define RALINK_PCI_MEMBASE\t\t0x0028\n-#define RALINK_PCI_IOBASE\t\t0x002C\n-\n-/* PCIe RC control registers */\n-#define RALINK_PCI_ID\t\t\t0x0030\n-#define RALINK_PCI_CLASS\t\t0x0034\n-#define RALINK_PCI_SUBID\t\t0x0038\n-#define RALINK_PCI_STATUS\t\t0x0050\n-\n-/* Some definition values */\n-#define PCIE_REVISION_ID\t\tBIT(0)\n-#define PCIE_CLASS_CODE\t\t\t(0x60400 << 8)\n-#define PCIE_BAR_MAP_MAX\t\tGENMASK(30, 16)\n-#define PCIE_BAR_ENABLE\t\t\tBIT(0)\n-#define PCIE_PORT_INT_EN(x)\t\tBIT(20 + (x))\n-#define PCIE_PORT_LINKUP\t\tBIT(0)\n-#define PCIE_PORT_CNT\t\t\t3\n-\n-#define PERST_DELAY_MS\t\t\t100\n-\n-/**\n- * struct mt7621_pcie_port - PCIe port information\n- * @base: I/O mapped register base\n- * @list: port list\n- * @pcie: pointer to PCIe host info\n- * @clk: pointer to the port clock gate\n- * @phy: pointer to PHY control block\n- * @pcie_rst: pointer to port reset control\n- * @gpio_rst: gpio reset\n- * @slot: port slot\n- * @enabled: indicates if port is enabled\n- */\n-struct mt7621_pcie_port {\n-\tvoid __iomem *base;\n-\tstruct list_head list;\n-\tstruct mt7621_pcie *pcie;\n-\tstruct clk *clk;\n-\tstruct phy *phy;\n-\tstruct reset_control *pcie_rst;\n-\tstruct gpio_desc *gpio_rst;\n-\tu32 slot;\n-\tbool enabled;\n-};\n-\n-/**\n- * struct mt7621_pcie - PCIe host information\n- * @base: IO Mapped Register Base\n- * @dev: Pointer to PCIe device\n- * @ports: pointer to PCIe port information\n- * @resets_inverted: depends on chip revision\n- * reset lines are inverted.\n- */\n-struct mt7621_pcie {\n-\tvoid __iomem *base;\n-\tstruct device *dev;\n-\tstruct list_head ports;\n-\tbool resets_inverted;\n-};\n-\n-static inline u32 pcie_read(struct mt7621_pcie *pcie, u32 reg)\n-{\n-\treturn readl_relaxed(pcie->base + reg);\n-}\n-\n-static inline void pcie_write(struct mt7621_pcie *pcie, u32 val, u32 reg)\n-{\n-\twritel_relaxed(val, pcie->base + reg);\n-}\n-\n-static inline void pcie_rmw(struct mt7621_pcie *pcie, u32 reg, u32 clr, u32 set)\n-{\n-\tu32 val = readl_relaxed(pcie->base + reg);\n-\n-\tval &= ~clr;\n-\tval |= set;\n-\twritel_relaxed(val, pcie->base + reg);\n-}\n-\n-static inline u32 pcie_port_read(struct mt7621_pcie_port *port, u32 reg)\n-{\n-\treturn readl_relaxed(port->base + reg);\n-}\n-\n-static inline void pcie_port_write(struct mt7621_pcie_port *port,\n-\t\t\t\t   u32 val, u32 reg)\n-{\n-\twritel_relaxed(val, port->base + reg);\n-}\n-\n-static inline u32 mt7621_pci_get_cfgaddr(unsigned int bus, unsigned int slot,\n-\t\t\t\t\t unsigned int func, unsigned int where)\n-{\n-\treturn (((where & 0xF00) >> 8) << 24) | (bus << 16) | (slot << 11) |\n-\t\t(func << 8) | (where & 0xfc) | 0x80000000;\n-}\n-\n-static void __iomem *mt7621_pcie_map_bus(struct pci_bus *bus,\n-\t\t\t\t\t unsigned int devfn, int where)\n-{\n-\tstruct mt7621_pcie *pcie = bus->sysdata;\n-\tu32 address = mt7621_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),\n-\t\t\t\t\t     PCI_FUNC(devfn), where);\n-\n-\twritel_relaxed(address, pcie->base + RALINK_PCI_CONFIG_ADDR);\n-\n-\treturn pcie->base + RALINK_PCI_CONFIG_DATA + (where & 3);\n-}\n-\n-struct pci_ops mt7621_pci_ops = {\n-\t.map_bus\t= mt7621_pcie_map_bus,\n-\t.read\t\t= pci_generic_config_read,\n-\t.write\t\t= pci_generic_config_write,\n-};\n-\n-static u32 read_config(struct mt7621_pcie *pcie, unsigned int dev, u32 reg)\n-{\n-\tu32 address = mt7621_pci_get_cfgaddr(0, dev, 0, reg);\n-\n-\tpcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR);\n-\treturn pcie_read(pcie, RALINK_PCI_CONFIG_DATA);\n-}\n-\n-static void write_config(struct mt7621_pcie *pcie, unsigned int dev,\n-\t\t\t u32 reg, u32 val)\n-{\n-\tu32 address = mt7621_pci_get_cfgaddr(0, dev, 0, reg);\n-\n-\tpcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR);\n-\tpcie_write(pcie, val, RALINK_PCI_CONFIG_DATA);\n-}\n-\n-static inline void mt7621_rst_gpio_pcie_assert(struct mt7621_pcie_port *port)\n-{\n-\tif (port->gpio_rst)\n-\t\tgpiod_set_value(port->gpio_rst, 1);\n-}\n-\n-static inline void mt7621_rst_gpio_pcie_deassert(struct mt7621_pcie_port *port)\n-{\n-\tif (port->gpio_rst)\n-\t\tgpiod_set_value(port->gpio_rst, 0);\n-}\n-\n-static inline bool mt7621_pcie_port_is_linkup(struct mt7621_pcie_port *port)\n-{\n-\treturn (pcie_port_read(port, RALINK_PCI_STATUS) & PCIE_PORT_LINKUP) != 0;\n-}\n-\n-static inline void mt7621_control_assert(struct mt7621_pcie_port *port)\n-{\n-\tstruct mt7621_pcie *pcie = port->pcie;\n-\n-\tif (pcie->resets_inverted)\n-\t\treset_control_assert(port->pcie_rst);\n-\telse\n-\t\treset_control_deassert(port->pcie_rst);\n-}\n-\n-static inline void mt7621_control_deassert(struct mt7621_pcie_port *port)\n-{\n-\tstruct mt7621_pcie *pcie = port->pcie;\n-\n-\tif (pcie->resets_inverted)\n-\t\treset_control_deassert(port->pcie_rst);\n-\telse\n-\t\treset_control_assert(port->pcie_rst);\n-}\n-\n-static int setup_cm_memory_region(struct pci_host_bridge *host)\n-{\n-\tstruct mt7621_pcie *pcie = pci_host_bridge_priv(host);\n-\tstruct device *dev = pcie->dev;\n-\tstruct resource_entry *entry;\n-\tresource_size_t mask;\n-\n-\tentry = resource_list_first_type(&host->windows, IORESOURCE_MEM);\n-\tif (!entry) {\n-\t\tdev_err(dev, \"Cannot get memory resource\\n\");\n-\t\treturn -EINVAL;\n-\t}\n-\n-\tif (mips_cps_numiocu(0)) {\n-\t\t/*\n-\t\t * FIXME: hardware doesn't accept mask values with 1s after\n-\t\t * 0s (e.g. 0xffef), so it would be great to warn if that's\n-\t\t * about to happen\n-\t\t */\n-\t\tmask = ~(entry->res->end - entry->res->start);\n-\n-\t\twrite_gcr_reg1_base(entry->res->start);\n-\t\twrite_gcr_reg1_mask(mask | CM_GCR_REGn_MASK_CMTGT_IOCU0);\n-\t\tdev_info(dev, \"PCI coherence region base: 0x%08llx, mask/settings: 0x%08llx\\n\",\n-\t\t\t (unsigned long long)read_gcr_reg1_base(),\n-\t\t\t (unsigned long long)read_gcr_reg1_mask());\n-\t}\n-\n-\treturn 0;\n-}\n-\n-static int mt7621_pcie_parse_port(struct mt7621_pcie *pcie,\n-\t\t\t\t  struct device_node *node,\n-\t\t\t\t  int slot)\n-{\n-\tstruct mt7621_pcie_port *port;\n-\tstruct device *dev = pcie->dev;\n-\tstruct platform_device *pdev = to_platform_device(dev);\n-\tchar name[10];\n-\tint err;\n-\n-\tport = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);\n-\tif (!port)\n-\t\treturn -ENOMEM;\n-\n-\tport->base = devm_platform_ioremap_resource(pdev, slot + 1);\n-\tif (IS_ERR(port->base))\n-\t\treturn PTR_ERR(port->base);\n-\n-\tport->clk = devm_get_clk_from_child(dev, node, NULL);\n-\tif (IS_ERR(port->clk)) {\n-\t\tdev_err(dev, \"failed to get pcie%d clock\\n\", slot);\n-\t\treturn PTR_ERR(port->clk);\n-\t}\n-\n-\tport->pcie_rst = of_reset_control_get_exclusive(node, NULL);\n-\tif (PTR_ERR(port->pcie_rst) == -EPROBE_DEFER) {\n-\t\tdev_err(dev, \"failed to get pcie%d reset control\\n\", slot);\n-\t\treturn PTR_ERR(port->pcie_rst);\n-\t}\n-\n-\tsnprintf(name, sizeof(name), \"pcie-phy%d\", slot);\n-\tport->phy = devm_of_phy_get(dev, node, name);\n-\tif (IS_ERR(port->phy)) {\n-\t\tdev_err(dev, \"failed to get pcie-phy%d\\n\", slot);\n-\t\terr = PTR_ERR(port->phy);\n-\t\tgoto remove_reset;\n-\t}\n-\n-\tport->gpio_rst = devm_gpiod_get_index_optional(dev, \"reset\", slot,\n-\t\t\t\t\t\t       GPIOD_OUT_LOW);\n-\tif (IS_ERR(port->gpio_rst)) {\n-\t\tdev_err(dev, \"Failed to get GPIO for PCIe%d\\n\", slot);\n-\t\terr = PTR_ERR(port->gpio_rst);\n-\t\tgoto remove_reset;\n-\t}\n-\n-\tport->slot = slot;\n-\tport->pcie = pcie;\n-\n-\tINIT_LIST_HEAD(&port->list);\n-\tlist_add_tail(&port->list, &pcie->ports);\n-\n-\treturn 0;\n-\n-remove_reset:\n-\treset_control_put(port->pcie_rst);\n-\treturn err;\n-}\n-\n-static int mt7621_pcie_parse_dt(struct mt7621_pcie *pcie)\n-{\n-\tstruct device *dev = pcie->dev;\n-\tstruct platform_device *pdev = to_platform_device(dev);\n-\tstruct device_node *node = dev->of_node, *child;\n-\tint err;\n-\n-\tpcie->base = devm_platform_ioremap_resource(pdev, 0);\n-\tif (IS_ERR(pcie->base))\n-\t\treturn PTR_ERR(pcie->base);\n-\n-\tfor_each_available_child_of_node(node, child) {\n-\t\tint slot;\n-\n-\t\terr = of_pci_get_devfn(child);\n-\t\tif (err < 0) {\n-\t\t\tof_node_put(child);\n-\t\t\tdev_err(dev, \"failed to parse devfn: %d\\n\", err);\n-\t\t\treturn err;\n-\t\t}\n-\n-\t\tslot = PCI_SLOT(err);\n-\n-\t\terr = mt7621_pcie_parse_port(pcie, child, slot);\n-\t\tif (err) {\n-\t\t\tof_node_put(child);\n-\t\t\treturn err;\n-\t\t}\n-\t}\n-\n-\treturn 0;\n-}\n-\n-static int mt7621_pcie_init_port(struct mt7621_pcie_port *port)\n-{\n-\tstruct mt7621_pcie *pcie = port->pcie;\n-\tstruct device *dev = pcie->dev;\n-\tu32 slot = port->slot;\n-\tint err;\n-\n-\terr = phy_init(port->phy);\n-\tif (err) {\n-\t\tdev_err(dev, \"failed to initialize port%d phy\\n\", slot);\n-\t\treturn err;\n-\t}\n-\n-\terr = phy_power_on(port->phy);\n-\tif (err) {\n-\t\tdev_err(dev, \"failed to power on port%d phy\\n\", slot);\n-\t\tphy_exit(port->phy);\n-\t\treturn err;\n-\t}\n-\n-\tport->enabled = true;\n-\n-\treturn 0;\n-}\n-\n-static void mt7621_pcie_reset_assert(struct mt7621_pcie *pcie)\n-{\n-\tstruct mt7621_pcie_port *port;\n-\n-\tlist_for_each_entry(port, &pcie->ports, list) {\n-\t\t/* PCIe RC reset assert */\n-\t\tmt7621_control_assert(port);\n-\n-\t\t/* PCIe EP reset assert */\n-\t\tmt7621_rst_gpio_pcie_assert(port);\n-\t}\n-\n-\tmsleep(PERST_DELAY_MS);\n-}\n-\n-static void mt7621_pcie_reset_rc_deassert(struct mt7621_pcie *pcie)\n-{\n-\tstruct mt7621_pcie_port *port;\n-\n-\tlist_for_each_entry(port, &pcie->ports, list)\n-\t\tmt7621_control_deassert(port);\n-}\n-\n-static void mt7621_pcie_reset_ep_deassert(struct mt7621_pcie *pcie)\n-{\n-\tstruct mt7621_pcie_port *port;\n-\n-\tlist_for_each_entry(port, &pcie->ports, list)\n-\t\tmt7621_rst_gpio_pcie_deassert(port);\n-\n-\tmsleep(PERST_DELAY_MS);\n-}\n-\n-static int mt7621_pcie_init_ports(struct mt7621_pcie *pcie)\n-{\n-\tstruct device *dev = pcie->dev;\n-\tstruct mt7621_pcie_port *port, *tmp;\n-\tu8 num_disabled = 0;\n-\tint err;\n-\n-\tmt7621_pcie_reset_assert(pcie);\n-\tmt7621_pcie_reset_rc_deassert(pcie);\n-\n-\tlist_for_each_entry_safe(port, tmp, &pcie->ports, list) {\n-\t\tu32 slot = port->slot;\n-\n-\t\tif (slot == 1) {\n-\t\t\tport->enabled = true;\n-\t\t\tcontinue;\n-\t\t}\n-\n-\t\terr = mt7621_pcie_init_port(port);\n-\t\tif (err) {\n-\t\t\tdev_err(dev, \"Initiating port %d failed\\n\", slot);\n-\t\t\tlist_del(&port->list);\n-\t\t}\n-\t}\n-\n-\tmt7621_pcie_reset_ep_deassert(pcie);\n-\n-\ttmp = NULL;\n-\tlist_for_each_entry(port, &pcie->ports, list) {\n-\t\tu32 slot = port->slot;\n-\n-\t\tif (!mt7621_pcie_port_is_linkup(port)) {\n-\t\t\tdev_err(dev, \"pcie%d no card, disable it (RST & CLK)\\n\",\n-\t\t\t\tslot);\n-\t\t\tmt7621_control_assert(port);\n-\t\t\tport->enabled = false;\n-\t\t\tnum_disabled++;\n-\n-\t\t\tif (slot == 0) {\n-\t\t\t\ttmp = port;\n-\t\t\t\tcontinue;\n-\t\t\t}\n-\n-\t\t\tif (slot == 1 && tmp && !tmp->enabled)\n-\t\t\t\tphy_power_off(tmp->phy);\n-\t\t}\n-\t}\n-\n-\treturn (num_disabled != PCIE_PORT_CNT) ? 0 : -ENODEV;\n-}\n-\n-static void mt7621_pcie_enable_port(struct mt7621_pcie_port *port)\n-{\n-\tstruct mt7621_pcie *pcie = port->pcie;\n-\tu32 slot = port->slot;\n-\tu32 val;\n-\n-\t/* enable pcie interrupt */\n-\tval = pcie_read(pcie, RALINK_PCI_PCIMSK_ADDR);\n-\tval |= PCIE_PORT_INT_EN(slot);\n-\tpcie_write(pcie, val, RALINK_PCI_PCIMSK_ADDR);\n-\n-\t/* map 2G DDR region */\n-\tpcie_port_write(port, PCIE_BAR_MAP_MAX | PCIE_BAR_ENABLE,\n-\t\t\tPCI_BASE_ADDRESS_0);\n-\n-\t/* configure class code and revision ID */\n-\tpcie_port_write(port, PCIE_CLASS_CODE | PCIE_REVISION_ID,\n-\t\t\tRALINK_PCI_CLASS);\n-\n-\t/* configure RC FTS number to 250 when it leaves L0s */\n-\tval = read_config(pcie, slot, PCIE_FTS_NUM);\n-\tval &= ~PCIE_FTS_NUM_MASK;\n-\tval |= PCIE_FTS_NUM_L0(0x50);\n-\twrite_config(pcie, slot, PCIE_FTS_NUM, val);\n-}\n-\n-static int mt7621_pcie_enable_ports(struct pci_host_bridge *host)\n-{\n-\tstruct mt7621_pcie *pcie = pci_host_bridge_priv(host);\n-\tstruct device *dev = pcie->dev;\n-\tstruct mt7621_pcie_port *port;\n-\tstruct resource_entry *entry;\n-\tint err;\n-\n-\tentry = resource_list_first_type(&host->windows, IORESOURCE_IO);\n-\tif (!entry) {\n-\t\tdev_err(dev, \"Cannot get io resource\\n\");\n-\t\treturn -EINVAL;\n-\t}\n-\n-\t/* Setup MEMWIN and IOWIN */\n-\tpcie_write(pcie, 0xffffffff, RALINK_PCI_MEMBASE);\n-\tpcie_write(pcie, entry->res->start, RALINK_PCI_IOBASE);\n-\n-\tlist_for_each_entry(port, &pcie->ports, list) {\n-\t\tif (port->enabled) {\n-\t\t\terr = clk_prepare_enable(port->clk);\n-\t\t\tif (err) {\n-\t\t\t\tdev_err(dev, \"enabling clk pcie%d\\n\",\n-\t\t\t\t\tport->slot);\n-\t\t\t\treturn err;\n-\t\t\t}\n-\n-\t\t\tmt7621_pcie_enable_port(port);\n-\t\t\tdev_info(dev, \"PCIE%d enabled\\n\", port->slot);\n-\t\t}\n-\t}\n-\n-\treturn 0;\n-}\n-\n-static int mt7621_pcie_register_host(struct pci_host_bridge *host)\n-{\n-\tstruct mt7621_pcie *pcie = pci_host_bridge_priv(host);\n-\n-\thost->ops = &mt7621_pci_ops;\n-\thost->sysdata = pcie;\n-\treturn pci_host_probe(host);\n-}\n-\n-static const struct soc_device_attribute mt7621_pci_quirks_match[] = {\n-\t{ .soc_id = \"mt7621\", .revision = \"E2\" }\n-};\n-\n-static int mt7621_pci_probe(struct platform_device *pdev)\n-{\n-\tstruct device *dev = &pdev->dev;\n-\tconst struct soc_device_attribute *attr;\n-\tstruct mt7621_pcie_port *port;\n-\tstruct mt7621_pcie *pcie;\n-\tstruct pci_host_bridge *bridge;\n-\tint err;\n-\n-\tif (!dev->of_node)\n-\t\treturn -ENODEV;\n-\n-\tbridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie));\n-\tif (!bridge)\n-\t\treturn -ENOMEM;\n-\n-\tpcie = pci_host_bridge_priv(bridge);\n-\tpcie->dev = dev;\n-\tplatform_set_drvdata(pdev, pcie);\n-\tINIT_LIST_HEAD(&pcie->ports);\n-\n-\tattr = soc_device_match(mt7621_pci_quirks_match);\n-\tif (attr)\n-\t\tpcie->resets_inverted = true;\n-\n-\terr = mt7621_pcie_parse_dt(pcie);\n-\tif (err) {\n-\t\tdev_err(dev, \"Parsing DT failed\\n\");\n-\t\treturn err;\n-\t}\n-\n-\terr = mt7621_pcie_init_ports(pcie);\n-\tif (err) {\n-\t\tdev_err(dev, \"Nothing connected in virtual bridges\\n\");\n-\t\treturn 0;\n-\t}\n-\n-\terr = mt7621_pcie_enable_ports(bridge);\n-\tif (err) {\n-\t\tdev_err(dev, \"Error enabling pcie ports\\n\");\n-\t\tgoto remove_resets;\n-\t}\n-\n-\terr = setup_cm_memory_region(bridge);\n-\tif (err) {\n-\t\tdev_err(dev, \"Error setting up iocu mem regions\\n\");\n-\t\tgoto remove_resets;\n-\t}\n-\n-\treturn mt7621_pcie_register_host(bridge);\n-\n-remove_resets:\n-\tlist_for_each_entry(port, &pcie->ports, list)\n-\t\treset_control_put(port->pcie_rst);\n-\n-\treturn err;\n-}\n-\n-static int mt7621_pci_remove(struct platform_device *pdev)\n-{\n-\tstruct mt7621_pcie *pcie = platform_get_drvdata(pdev);\n-\tstruct mt7621_pcie_port *port;\n-\n-\tlist_for_each_entry(port, &pcie->ports, list)\n-\t\treset_control_put(port->pcie_rst);\n-\n-\treturn 0;\n-}\n-\n-static const struct of_device_id mt7621_pci_ids[] = {\n-\t{ .compatible = \"mediatek,mt7621-pci\" },\n-\t{},\n-};\n-MODULE_DEVICE_TABLE(of, mt7621_pci_ids);\n-\n-static struct platform_driver mt7621_pci_driver = {\n-\t.probe = mt7621_pci_probe,\n-\t.remove = mt7621_pci_remove,\n-\t.driver = {\n-\t\t.name = \"mt7621-pci\",\n-\t\t.of_match_table = of_match_ptr(mt7621_pci_ids),\n-\t},\n-};\n-builtin_platform_driver(mt7621_pci_driver);\n--- /dev/null\n+++ b/drivers/pci/controller/pcie-mt7621.c\n@@ -0,0 +1,600 @@\n+// SPDX-License-Identifier: GPL-2.0+\n+/*\n+ * BRIEF MODULE DESCRIPTION\n+ *     PCI init for Ralink RT2880 solution\n+ *\n+ * Copyright 2007 Ralink Inc. (bruce_chang@ralinktech.com.tw)\n+ *\n+ * May 2007 Bruce Chang\n+ * Initial Release\n+ *\n+ * May 2009 Bruce Chang\n+ * support RT2880/RT3883 PCIe\n+ *\n+ * May 2011 Bruce Chang\n+ * support RT6855/MT7620 PCIe\n+ */\n+\n+#include <linux/bitops.h>\n+#include <linux/clk.h>\n+#include <linux/delay.h>\n+#include <linux/gpio/consumer.h>\n+#include <linux/module.h>\n+#include <linux/of.h>\n+#include <linux/of_address.h>\n+#include <linux/of_pci.h>\n+#include <linux/of_platform.h>\n+#include <linux/pci.h>\n+#include <linux/phy/phy.h>\n+#include <linux/platform_device.h>\n+#include <linux/reset.h>\n+#include <linux/sys_soc.h>\n+\n+/* MediaTek-specific configuration registers */\n+#define PCIE_FTS_NUM\t\t\t0x70c\n+#define PCIE_FTS_NUM_MASK\t\tGENMASK(15, 8)\n+#define PCIE_FTS_NUM_L0(x)\t\t(((x) & 0xff) << 8)\n+\n+/* Host-PCI bridge registers */\n+#define RALINK_PCI_PCICFG_ADDR\t\t0x0000\n+#define RALINK_PCI_PCIMSK_ADDR\t\t0x000c\n+#define RALINK_PCI_CONFIG_ADDR\t\t0x0020\n+#define RALINK_PCI_CONFIG_DATA\t\t0x0024\n+#define RALINK_PCI_MEMBASE\t\t0x0028\n+#define RALINK_PCI_IOBASE\t\t0x002c\n+\n+/* PCIe RC control registers */\n+#define RALINK_PCI_ID\t\t\t0x0030\n+#define RALINK_PCI_CLASS\t\t0x0034\n+#define RALINK_PCI_SUBID\t\t0x0038\n+#define RALINK_PCI_STATUS\t\t0x0050\n+\n+/* Some definition values */\n+#define PCIE_REVISION_ID\t\tBIT(0)\n+#define PCIE_CLASS_CODE\t\t\t(0x60400 << 8)\n+#define PCIE_BAR_MAP_MAX\t\tGENMASK(30, 16)\n+#define PCIE_BAR_ENABLE\t\t\tBIT(0)\n+#define PCIE_PORT_INT_EN(x)\t\tBIT(20 + (x))\n+#define PCIE_PORT_LINKUP\t\tBIT(0)\n+#define PCIE_PORT_CNT\t\t\t3\n+\n+#define PERST_DELAY_MS\t\t\t100\n+\n+/**\n+ * struct mt7621_pcie_port - PCIe port information\n+ * @base: I/O mapped register base\n+ * @list: port list\n+ * @pcie: pointer to PCIe host info\n+ * @clk: pointer to the port clock gate\n+ * @phy: pointer to PHY control block\n+ * @pcie_rst: pointer to port reset control\n+ * @gpio_rst: gpio reset\n+ * @slot: port slot\n+ * @enabled: indicates if port is enabled\n+ */\n+struct mt7621_pcie_port {\n+\tvoid __iomem *base;\n+\tstruct list_head list;\n+\tstruct mt7621_pcie *pcie;\n+\tstruct clk *clk;\n+\tstruct phy *phy;\n+\tstruct reset_control *pcie_rst;\n+\tstruct gpio_desc *gpio_rst;\n+\tu32 slot;\n+\tbool enabled;\n+};\n+\n+/**\n+ * struct mt7621_pcie - PCIe host information\n+ * @base: IO Mapped Register Base\n+ * @dev: Pointer to PCIe device\n+ * @ports: pointer to PCIe port information\n+ * @resets_inverted: depends on chip revision\n+ * reset lines are inverted.\n+ */\n+struct mt7621_pcie {\n+\tvoid __iomem *base;\n+\tstruct device *dev;\n+\tstruct list_head ports;\n+\tbool resets_inverted;\n+};\n+\n+static inline u32 pcie_read(struct mt7621_pcie *pcie, u32 reg)\n+{\n+\treturn readl_relaxed(pcie->base + reg);\n+}\n+\n+static inline void pcie_write(struct mt7621_pcie *pcie, u32 val, u32 reg)\n+{\n+\twritel_relaxed(val, pcie->base + reg);\n+}\n+\n+static inline void pcie_rmw(struct mt7621_pcie *pcie, u32 reg, u32 clr, u32 set)\n+{\n+\tu32 val = readl_relaxed(pcie->base + reg);\n+\n+\tval &= ~clr;\n+\tval |= set;\n+\twritel_relaxed(val, pcie->base + reg);\n+}\n+\n+static inline u32 pcie_port_read(struct mt7621_pcie_port *port, u32 reg)\n+{\n+\treturn readl_relaxed(port->base + reg);\n+}\n+\n+static inline void pcie_port_write(struct mt7621_pcie_port *port,\n+\t\t\t\t   u32 val, u32 reg)\n+{\n+\twritel_relaxed(val, port->base + reg);\n+}\n+\n+static inline u32 mt7621_pci_get_cfgaddr(unsigned int bus, unsigned int slot,\n+\t\t\t\t\t unsigned int func, unsigned int where)\n+{\n+\treturn (((where & 0xf00) >> 8) << 24) | (bus << 16) | (slot << 11) |\n+\t\t(func << 8) | (where & 0xfc) | 0x80000000;\n+}\n+\n+static void __iomem *mt7621_pcie_map_bus(struct pci_bus *bus,\n+\t\t\t\t\t unsigned int devfn, int where)\n+{\n+\tstruct mt7621_pcie *pcie = bus->sysdata;\n+\tu32 address = mt7621_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),\n+\t\t\t\t\t     PCI_FUNC(devfn), where);\n+\n+\twritel_relaxed(address, pcie->base + RALINK_PCI_CONFIG_ADDR);\n+\n+\treturn pcie->base + RALINK_PCI_CONFIG_DATA + (where & 3);\n+}\n+\n+struct pci_ops mt7621_pci_ops = {\n+\t.map_bus\t= mt7621_pcie_map_bus,\n+\t.read\t\t= pci_generic_config_read,\n+\t.write\t\t= pci_generic_config_write,\n+};\n+\n+static u32 read_config(struct mt7621_pcie *pcie, unsigned int dev, u32 reg)\n+{\n+\tu32 address = mt7621_pci_get_cfgaddr(0, dev, 0, reg);\n+\n+\tpcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR);\n+\treturn pcie_read(pcie, RALINK_PCI_CONFIG_DATA);\n+}\n+\n+static void write_config(struct mt7621_pcie *pcie, unsigned int dev,\n+\t\t\t u32 reg, u32 val)\n+{\n+\tu32 address = mt7621_pci_get_cfgaddr(0, dev, 0, reg);\n+\n+\tpcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR);\n+\tpcie_write(pcie, val, RALINK_PCI_CONFIG_DATA);\n+}\n+\n+static inline void mt7621_rst_gpio_pcie_assert(struct mt7621_pcie_port *port)\n+{\n+\tif (port->gpio_rst)\n+\t\tgpiod_set_value(port->gpio_rst, 1);\n+}\n+\n+static inline void mt7621_rst_gpio_pcie_deassert(struct mt7621_pcie_port *port)\n+{\n+\tif (port->gpio_rst)\n+\t\tgpiod_set_value(port->gpio_rst, 0);\n+}\n+\n+static inline bool mt7621_pcie_port_is_linkup(struct mt7621_pcie_port *port)\n+{\n+\treturn (pcie_port_read(port, RALINK_PCI_STATUS) & PCIE_PORT_LINKUP) != 0;\n+}\n+\n+static inline void mt7621_control_assert(struct mt7621_pcie_port *port)\n+{\n+\tstruct mt7621_pcie *pcie = port->pcie;\n+\n+\tif (pcie->resets_inverted)\n+\t\treset_control_assert(port->pcie_rst);\n+\telse\n+\t\treset_control_deassert(port->pcie_rst);\n+}\n+\n+static inline void mt7621_control_deassert(struct mt7621_pcie_port *port)\n+{\n+\tstruct mt7621_pcie *pcie = port->pcie;\n+\n+\tif (pcie->resets_inverted)\n+\t\treset_control_deassert(port->pcie_rst);\n+\telse\n+\t\treset_control_assert(port->pcie_rst);\n+}\n+\n+static int setup_cm_memory_region(struct pci_host_bridge *host)\n+{\n+\tstruct mt7621_pcie *pcie = pci_host_bridge_priv(host);\n+\tstruct device *dev = pcie->dev;\n+\tstruct resource_entry *entry;\n+\tresource_size_t mask;\n+\n+\tentry = resource_list_first_type(&host->windows, IORESOURCE_MEM);\n+\tif (!entry) {\n+\t\tdev_err(dev, \"cannot get memory resource\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (mips_cps_numiocu(0)) {\n+\t\t/*\n+\t\t * FIXME: hardware doesn't accept mask values with 1s after\n+\t\t * 0s (e.g. 0xffef), so it would be great to warn if that's\n+\t\t * about to happen\n+\t\t */\n+\t\tmask = ~(entry->res->end - entry->res->start);\n+\n+\t\twrite_gcr_reg1_base(entry->res->start);\n+\t\twrite_gcr_reg1_mask(mask | CM_GCR_REGn_MASK_CMTGT_IOCU0);\n+\t\tdev_info(dev, \"PCI coherence region base: 0x%08llx, mask/settings: 0x%08llx\\n\",\n+\t\t\t (unsigned long long)read_gcr_reg1_base(),\n+\t\t\t (unsigned long long)read_gcr_reg1_mask());\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int mt7621_pcie_parse_port(struct mt7621_pcie *pcie,\n+\t\t\t\t  struct device_node *node,\n+\t\t\t\t  int slot)\n+{\n+\tstruct mt7621_pcie_port *port;\n+\tstruct device *dev = pcie->dev;\n+\tstruct platform_device *pdev = to_platform_device(dev);\n+\tchar name[10];\n+\tint err;\n+\n+\tport = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);\n+\tif (!port)\n+\t\treturn -ENOMEM;\n+\n+\tport->base = devm_platform_ioremap_resource(pdev, slot + 1);\n+\tif (IS_ERR(port->base))\n+\t\treturn PTR_ERR(port->base);\n+\n+\tport->clk = devm_get_clk_from_child(dev, node, NULL);\n+\tif (IS_ERR(port->clk)) {\n+\t\tdev_err(dev, \"failed to get pcie%d clock\\n\", slot);\n+\t\treturn PTR_ERR(port->clk);\n+\t}\n+\n+\tport->pcie_rst = of_reset_control_get_exclusive(node, NULL);\n+\tif (PTR_ERR(port->pcie_rst) == -EPROBE_DEFER) {\n+\t\tdev_err(dev, \"failed to get pcie%d reset control\\n\", slot);\n+\t\treturn PTR_ERR(port->pcie_rst);\n+\t}\n+\n+\tsnprintf(name, sizeof(name), \"pcie-phy%d\", slot);\n+\tport->phy = devm_of_phy_get(dev, node, name);\n+\tif (IS_ERR(port->phy)) {\n+\t\tdev_err(dev, \"failed to get pcie-phy%d\\n\", slot);\n+\t\terr = PTR_ERR(port->phy);\n+\t\tgoto remove_reset;\n+\t}\n+\n+\tport->gpio_rst = devm_gpiod_get_index_optional(dev, \"reset\", slot,\n+\t\t\t\t\t\t       GPIOD_OUT_LOW);\n+\tif (IS_ERR(port->gpio_rst)) {\n+\t\tdev_err(dev, \"failed to get GPIO for PCIe%d\\n\", slot);\n+\t\terr = PTR_ERR(port->gpio_rst);\n+\t\tgoto remove_reset;\n+\t}\n+\n+\tport->slot = slot;\n+\tport->pcie = pcie;\n+\n+\tINIT_LIST_HEAD(&port->list);\n+\tlist_add_tail(&port->list, &pcie->ports);\n+\n+\treturn 0;\n+\n+remove_reset:\n+\treset_control_put(port->pcie_rst);\n+\treturn err;\n+}\n+\n+static int mt7621_pcie_parse_dt(struct mt7621_pcie *pcie)\n+{\n+\tstruct device *dev = pcie->dev;\n+\tstruct platform_device *pdev = to_platform_device(dev);\n+\tstruct device_node *node = dev->of_node, *child;\n+\tint err;\n+\n+\tpcie->base = devm_platform_ioremap_resource(pdev, 0);\n+\tif (IS_ERR(pcie->base))\n+\t\treturn PTR_ERR(pcie->base);\n+\n+\tfor_each_available_child_of_node(node, child) {\n+\t\tint slot;\n+\n+\t\terr = of_pci_get_devfn(child);\n+\t\tif (err < 0) {\n+\t\t\tof_node_put(child);\n+\t\t\tdev_err(dev, \"failed to parse devfn: %d\\n\", err);\n+\t\t\treturn err;\n+\t\t}\n+\n+\t\tslot = PCI_SLOT(err);\n+\n+\t\terr = mt7621_pcie_parse_port(pcie, child, slot);\n+\t\tif (err) {\n+\t\t\tof_node_put(child);\n+\t\t\treturn err;\n+\t\t}\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int mt7621_pcie_init_port(struct mt7621_pcie_port *port)\n+{\n+\tstruct mt7621_pcie *pcie = port->pcie;\n+\tstruct device *dev = pcie->dev;\n+\tu32 slot = port->slot;\n+\tint err;\n+\n+\terr = phy_init(port->phy);\n+\tif (err) {\n+\t\tdev_err(dev, \"failed to initialize port%d phy\\n\", slot);\n+\t\treturn err;\n+\t}\n+\n+\terr = phy_power_on(port->phy);\n+\tif (err) {\n+\t\tdev_err(dev, \"failed to power on port%d phy\\n\", slot);\n+\t\tphy_exit(port->phy);\n+\t\treturn err;\n+\t}\n+\n+\tport->enabled = true;\n+\n+\treturn 0;\n+}\n+\n+static void mt7621_pcie_reset_assert(struct mt7621_pcie *pcie)\n+{\n+\tstruct mt7621_pcie_port *port;\n+\n+\tlist_for_each_entry(port, &pcie->ports, list) {\n+\t\t/* PCIe RC reset assert */\n+\t\tmt7621_control_assert(port);\n+\n+\t\t/* PCIe EP reset assert */\n+\t\tmt7621_rst_gpio_pcie_assert(port);\n+\t}\n+\n+\tmsleep(PERST_DELAY_MS);\n+}\n+\n+static void mt7621_pcie_reset_rc_deassert(struct mt7621_pcie *pcie)\n+{\n+\tstruct mt7621_pcie_port *port;\n+\n+\tlist_for_each_entry(port, &pcie->ports, list)\n+\t\tmt7621_control_deassert(port);\n+}\n+\n+static void mt7621_pcie_reset_ep_deassert(struct mt7621_pcie *pcie)\n+{\n+\tstruct mt7621_pcie_port *port;\n+\n+\tlist_for_each_entry(port, &pcie->ports, list)\n+\t\tmt7621_rst_gpio_pcie_deassert(port);\n+\n+\tmsleep(PERST_DELAY_MS);\n+}\n+\n+static int mt7621_pcie_init_ports(struct mt7621_pcie *pcie)\n+{\n+\tstruct device *dev = pcie->dev;\n+\tstruct mt7621_pcie_port *port, *tmp;\n+\tu8 num_disabled = 0;\n+\tint err;\n+\n+\tmt7621_pcie_reset_assert(pcie);\n+\tmt7621_pcie_reset_rc_deassert(pcie);\n+\n+\tlist_for_each_entry_safe(port, tmp, &pcie->ports, list) {\n+\t\tu32 slot = port->slot;\n+\n+\t\tif (slot == 1) {\n+\t\t\tport->enabled = true;\n+\t\t\tcontinue;\n+\t\t}\n+\n+\t\terr = mt7621_pcie_init_port(port);\n+\t\tif (err) {\n+\t\t\tdev_err(dev, \"initializing port %d failed\\n\", slot);\n+\t\t\tlist_del(&port->list);\n+\t\t}\n+\t}\n+\n+\tmt7621_pcie_reset_ep_deassert(pcie);\n+\n+\ttmp = NULL;\n+\tlist_for_each_entry(port, &pcie->ports, list) {\n+\t\tu32 slot = port->slot;\n+\n+\t\tif (!mt7621_pcie_port_is_linkup(port)) {\n+\t\t\tdev_err(dev, \"pcie%d no card, disable it (RST & CLK)\\n\",\n+\t\t\t\tslot);\n+\t\t\tmt7621_control_assert(port);\n+\t\t\tport->enabled = false;\n+\t\t\tnum_disabled++;\n+\n+\t\t\tif (slot == 0) {\n+\t\t\t\ttmp = port;\n+\t\t\t\tcontinue;\n+\t\t\t}\n+\n+\t\t\tif (slot == 1 && tmp && !tmp->enabled)\n+\t\t\t\tphy_power_off(tmp->phy);\n+\t\t}\n+\t}\n+\n+\treturn (num_disabled != PCIE_PORT_CNT) ? 0 : -ENODEV;\n+}\n+\n+static void mt7621_pcie_enable_port(struct mt7621_pcie_port *port)\n+{\n+\tstruct mt7621_pcie *pcie = port->pcie;\n+\tu32 slot = port->slot;\n+\tu32 val;\n+\n+\t/* enable pcie interrupt */\n+\tval = pcie_read(pcie, RALINK_PCI_PCIMSK_ADDR);\n+\tval |= PCIE_PORT_INT_EN(slot);\n+\tpcie_write(pcie, val, RALINK_PCI_PCIMSK_ADDR);\n+\n+\t/* map 2G DDR region */\n+\tpcie_port_write(port, PCIE_BAR_MAP_MAX | PCIE_BAR_ENABLE,\n+\t\t\tPCI_BASE_ADDRESS_0);\n+\n+\t/* configure class code and revision ID */\n+\tpcie_port_write(port, PCIE_CLASS_CODE | PCIE_REVISION_ID,\n+\t\t\tRALINK_PCI_CLASS);\n+\n+\t/* configure RC FTS number to 250 when it leaves L0s */\n+\tval = read_config(pcie, slot, PCIE_FTS_NUM);\n+\tval &= ~PCIE_FTS_NUM_MASK;\n+\tval |= PCIE_FTS_NUM_L0(0x50);\n+\twrite_config(pcie, slot, PCIE_FTS_NUM, val);\n+}\n+\n+static int mt7621_pcie_enable_ports(struct pci_host_bridge *host)\n+{\n+\tstruct mt7621_pcie *pcie = pci_host_bridge_priv(host);\n+\tstruct device *dev = pcie->dev;\n+\tstruct mt7621_pcie_port *port;\n+\tstruct resource_entry *entry;\n+\tint err;\n+\n+\tentry = resource_list_first_type(&host->windows, IORESOURCE_IO);\n+\tif (!entry) {\n+\t\tdev_err(dev, \"cannot get io resource\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\t/* Setup MEMWIN and IOWIN */\n+\tpcie_write(pcie, 0xffffffff, RALINK_PCI_MEMBASE);\n+\tpcie_write(pcie, entry->res->start, RALINK_PCI_IOBASE);\n+\n+\tlist_for_each_entry(port, &pcie->ports, list) {\n+\t\tif (port->enabled) {\n+\t\t\terr = clk_prepare_enable(port->clk);\n+\t\t\tif (err) {\n+\t\t\t\tdev_err(dev, \"enabling clk pcie%d\\n\",\n+\t\t\t\t\tport->slot);\n+\t\t\t\treturn err;\n+\t\t\t}\n+\n+\t\t\tmt7621_pcie_enable_port(port);\n+\t\t\tdev_info(dev, \"PCIE%d enabled\\n\", port->slot);\n+\t\t}\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int mt7621_pcie_register_host(struct pci_host_bridge *host)\n+{\n+\tstruct mt7621_pcie *pcie = pci_host_bridge_priv(host);\n+\n+\thost->ops = &mt7621_pci_ops;\n+\thost->sysdata = pcie;\n+\treturn pci_host_probe(host);\n+}\n+\n+static const struct soc_device_attribute mt7621_pci_quirks_match[] = {\n+\t{ .soc_id = \"mt7621\", .revision = \"E2\" }\n+};\n+\n+static int mt7621_pci_probe(struct platform_device *pdev)\n+{\n+\tstruct device *dev = &pdev->dev;\n+\tconst struct soc_device_attribute *attr;\n+\tstruct mt7621_pcie_port *port;\n+\tstruct mt7621_pcie *pcie;\n+\tstruct pci_host_bridge *bridge;\n+\tint err;\n+\n+\tif (!dev->of_node)\n+\t\treturn -ENODEV;\n+\n+\tbridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie));\n+\tif (!bridge)\n+\t\treturn -ENOMEM;\n+\n+\tpcie = pci_host_bridge_priv(bridge);\n+\tpcie->dev = dev;\n+\tplatform_set_drvdata(pdev, pcie);\n+\tINIT_LIST_HEAD(&pcie->ports);\n+\n+\tattr = soc_device_match(mt7621_pci_quirks_match);\n+\tif (attr)\n+\t\tpcie->resets_inverted = true;\n+\n+\terr = mt7621_pcie_parse_dt(pcie);\n+\tif (err) {\n+\t\tdev_err(dev, \"parsing DT failed\\n\");\n+\t\treturn err;\n+\t}\n+\n+\terr = mt7621_pcie_init_ports(pcie);\n+\tif (err) {\n+\t\tdev_err(dev, \"nothing connected in virtual bridges\\n\");\n+\t\treturn 0;\n+\t}\n+\n+\terr = mt7621_pcie_enable_ports(bridge);\n+\tif (err) {\n+\t\tdev_err(dev, \"error enabling pcie ports\\n\");\n+\t\tgoto remove_resets;\n+\t}\n+\n+\terr = setup_cm_memory_region(bridge);\n+\tif (err) {\n+\t\tdev_err(dev, \"error setting up iocu mem regions\\n\");\n+\t\tgoto remove_resets;\n+\t}\n+\n+\treturn mt7621_pcie_register_host(bridge);\n+\n+remove_resets:\n+\tlist_for_each_entry(port, &pcie->ports, list)\n+\t\treset_control_put(port->pcie_rst);\n+\n+\treturn err;\n+}\n+\n+static int mt7621_pci_remove(struct platform_device *pdev)\n+{\n+\tstruct mt7621_pcie *pcie = platform_get_drvdata(pdev);\n+\tstruct mt7621_pcie_port *port;\n+\n+\tlist_for_each_entry(port, &pcie->ports, list)\n+\t\treset_control_put(port->pcie_rst);\n+\n+\treturn 0;\n+}\n+\n+static const struct of_device_id mt7621_pci_ids[] = {\n+\t{ .compatible = \"mediatek,mt7621-pci\" },\n+\t{},\n+};\n+MODULE_DEVICE_TABLE(of, mt7621_pci_ids);\n+\n+static struct platform_driver mt7621_pci_driver = {\n+\t.probe = mt7621_pci_probe,\n+\t.remove = mt7621_pci_remove,\n+\t.driver = {\n+\t\t.name = \"mt7621-pci\",\n+\t\t.of_match_table = of_match_ptr(mt7621_pci_ids),\n+\t},\n+};\n+builtin_platform_driver(mt7621_pci_driver);\n"
  },
  {
    "path": "target/linux/ramips/patches-5.15/101-PCI-mt7621-Rename-mt7621_pci_-to-mt7621_pcie_.patch",
    "content": "From: Bjorn Helgaas <bhelgaas@google.com>\nDate: Wed, 22 Dec 2021 19:10:48 -0600\nSubject: [PATCH] PCI: mt7621: Rename mt7621_pci_ to mt7621_pcie_\n\nRename mt7621_pci_* structs and functions to mt7621_pcie_* for consistency\nwith the rest of the file.\n\nLink: https://lore.kernel.org/r/20211223011054.1227810-18-helgaas@kernel.org\nSigned-off-by: Bjorn Helgaas <bhelgaas@google.com>\nReviewed-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>\nCc: Matthias Brugger <matthias.bgg@gmail.com>\n---\n\n--- a/drivers/pci/controller/pcie-mt7621.c\n+++ b/drivers/pci/controller/pcie-mt7621.c\n@@ -93,8 +93,8 @@ struct mt7621_pcie_port {\n  * reset lines are inverted.\n  */\n struct mt7621_pcie {\n-\tvoid __iomem *base;\n \tstruct device *dev;\n+\tvoid __iomem *base;\n \tstruct list_head ports;\n \tbool resets_inverted;\n };\n@@ -129,7 +129,7 @@ static inline void pcie_port_write(struc\n \twritel_relaxed(val, port->base + reg);\n }\n \n-static inline u32 mt7621_pci_get_cfgaddr(unsigned int bus, unsigned int slot,\n+static inline u32 mt7621_pcie_get_cfgaddr(unsigned int bus, unsigned int slot,\n \t\t\t\t\t unsigned int func, unsigned int where)\n {\n \treturn (((where & 0xf00) >> 8) << 24) | (bus << 16) | (slot << 11) |\n@@ -140,7 +140,7 @@ static void __iomem *mt7621_pcie_map_bus\n \t\t\t\t\t unsigned int devfn, int where)\n {\n \tstruct mt7621_pcie *pcie = bus->sysdata;\n-\tu32 address = mt7621_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),\n+\tu32 address = mt7621_pcie_get_cfgaddr(bus->number, PCI_SLOT(devfn),\n \t\t\t\t\t     PCI_FUNC(devfn), where);\n \n \twritel_relaxed(address, pcie->base + RALINK_PCI_CONFIG_ADDR);\n@@ -148,7 +148,7 @@ static void __iomem *mt7621_pcie_map_bus\n \treturn pcie->base + RALINK_PCI_CONFIG_DATA + (where & 3);\n }\n \n-struct pci_ops mt7621_pci_ops = {\n+struct pci_ops mt7621_pcie_ops = {\n \t.map_bus\t= mt7621_pcie_map_bus,\n \t.read\t\t= pci_generic_config_read,\n \t.write\t\t= pci_generic_config_write,\n@@ -156,7 +156,7 @@ struct pci_ops mt7621_pci_ops = {\n \n static u32 read_config(struct mt7621_pcie *pcie, unsigned int dev, u32 reg)\n {\n-\tu32 address = mt7621_pci_get_cfgaddr(0, dev, 0, reg);\n+\tu32 address = mt7621_pcie_get_cfgaddr(0, dev, 0, reg);\n \n \tpcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR);\n \treturn pcie_read(pcie, RALINK_PCI_CONFIG_DATA);\n@@ -165,7 +165,7 @@ static u32 read_config(struct mt7621_pci\n static void write_config(struct mt7621_pcie *pcie, unsigned int dev,\n \t\t\t u32 reg, u32 val)\n {\n-\tu32 address = mt7621_pci_get_cfgaddr(0, dev, 0, reg);\n+\tu32 address = mt7621_pcie_get_cfgaddr(0, dev, 0, reg);\n \n \tpcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR);\n \tpcie_write(pcie, val, RALINK_PCI_CONFIG_DATA);\n@@ -505,16 +505,16 @@ static int mt7621_pcie_register_host(str\n {\n \tstruct mt7621_pcie *pcie = pci_host_bridge_priv(host);\n \n-\thost->ops = &mt7621_pci_ops;\n+\thost->ops = &mt7621_pcie_ops;\n \thost->sysdata = pcie;\n \treturn pci_host_probe(host);\n }\n \n-static const struct soc_device_attribute mt7621_pci_quirks_match[] = {\n+static const struct soc_device_attribute mt7621_pcie_quirks_match[] = {\n \t{ .soc_id = \"mt7621\", .revision = \"E2\" }\n };\n \n-static int mt7621_pci_probe(struct platform_device *pdev)\n+static int mt7621_pcie_probe(struct platform_device *pdev)\n {\n \tstruct device *dev = &pdev->dev;\n \tconst struct soc_device_attribute *attr;\n@@ -535,7 +535,7 @@ static int mt7621_pci_probe(struct platf\n \tplatform_set_drvdata(pdev, pcie);\n \tINIT_LIST_HEAD(&pcie->ports);\n \n-\tattr = soc_device_match(mt7621_pci_quirks_match);\n+\tattr = soc_device_match(mt7621_pcie_quirks_match);\n \tif (attr)\n \t\tpcie->resets_inverted = true;\n \n@@ -572,7 +572,7 @@ remove_resets:\n \treturn err;\n }\n \n-static int mt7621_pci_remove(struct platform_device *pdev)\n+static int mt7621_pcie_remove(struct platform_device *pdev)\n {\n \tstruct mt7621_pcie *pcie = platform_get_drvdata(pdev);\n \tstruct mt7621_pcie_port *port;\n@@ -583,18 +583,18 @@ static int mt7621_pci_remove(struct plat\n \treturn 0;\n }\n \n-static const struct of_device_id mt7621_pci_ids[] = {\n+static const struct of_device_id mt7621_pcie_ids[] = {\n \t{ .compatible = \"mediatek,mt7621-pci\" },\n \t{},\n };\n-MODULE_DEVICE_TABLE(of, mt7621_pci_ids);\n+MODULE_DEVICE_TABLE(of, mt7621_pcie_ids);\n \n-static struct platform_driver mt7621_pci_driver = {\n-\t.probe = mt7621_pci_probe,\n-\t.remove = mt7621_pci_remove,\n+static struct platform_driver mt7621_pcie_driver = {\n+\t.probe = mt7621_pcie_probe,\n+\t.remove = mt7621_pcie_remove,\n \t.driver = {\n \t\t.name = \"mt7621-pci\",\n-\t\t.of_match_table = of_match_ptr(mt7621_pci_ids),\n+\t\t.of_match_table = of_match_ptr(mt7621_pcie_ids),\n \t},\n };\n-builtin_platform_driver(mt7621_pci_driver);\n+builtin_platform_driver(mt7621_pcie_driver);\n"
  },
  {
    "path": "target/linux/ramips/patches-5.15/102-PCI-mt7621-Declare-mt7621_pci_ops-static.patch",
    "content": "From: Sergio Paracuellos <sergio.paracuellos@gmail.com>\nDate: Wed, 17 Nov 2021 16:29:52 +0100\nSubject: [PATCH] PCI: mt7621: Declare mt7621_pci_ops static\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nSparse complains about mt7621_pci_ops symbol is not declared and asks if\nit should be declared as static instead. Sparse is right. Hence declare\nsymbol as static.\n\nLink: https://lore.kernel.org/r/20211117152952.12271-1-sergio.paracuellos@gmail.com\nReported-by: kernel test robot <lkp@intel.com>\nSigned-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>\nSigned-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>\nSigned-off-by: Bjorn Helgaas <bhelgaas@google.com>\nReviewed-by: Krzysztof Wilczyński <kw@linux.com>\n---\n\n--- a/drivers/pci/controller/pcie-mt7621.c\n+++ b/drivers/pci/controller/pcie-mt7621.c\n@@ -148,7 +148,7 @@ static void __iomem *mt7621_pcie_map_bus\n \treturn pcie->base + RALINK_PCI_CONFIG_DATA + (where & 3);\n }\n \n-struct pci_ops mt7621_pcie_ops = {\n+static struct pci_ops mt7621_pcie_ops = {\n \t.map_bus\t= mt7621_pcie_map_bus,\n \t.read\t\t= pci_generic_config_read,\n \t.write\t\t= pci_generic_config_write,\n"
  },
  {
    "path": "target/linux/ramips/patches-5.15/103-PCI-mt7621-Move-MIPS-setup-to-pcibios_root_bridge_pr.patch",
    "content": "From: Sergio Paracuellos <sergio.paracuellos@gmail.com>\nDate: Tue, 7 Dec 2021 11:49:21 +0100\nSubject: [PATCH] PCI: mt7621: Move MIPS setup to pcibios_root_bridge_prepare()\n\nOn the MIPS ralink mt7621 platform, we need to set up I/O coherency units\nbased on the host bridge apertures.\n\nTo remove this arch dependency from the driver itself, move the coherency\nsetup from the driver to pcibios_root_bridge_prepare().\n\n[bhelgaas: squash add/remove into one patch, commit log]\nLink: https://lore.kernel.org/r/20211207104924.21327-3-sergio.paracuellos@gmail.com\nLink: https://lore.kernel.org/r/20211207104924.21327-4-sergio.paracuellos@gmail.com\nSigned-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>\nSigned-off-by: Bjorn Helgaas <bhelgaas@google.com>\nReviewed-by: Guenter Roeck <linux@roeck-us.net>             # arch/mips\nAcked-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>   # arch/mips\n---\n\n--- a/arch/mips/ralink/mt7621.c\n+++ b/arch/mips/ralink/mt7621.c\n@@ -10,6 +10,8 @@\n #include <linux/slab.h>\n #include <linux/sys_soc.h>\n #include <linux/memblock.h>\n+#include <linux/pci.h>\n+#include <linux/bug.h>\n \n #include <asm/bootinfo.h>\n #include <asm/mipsregs.h>\n@@ -24,6 +26,35 @@\n \n static u32 detect_magic __initdata;\n \n+int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)\n+{\n+\tstruct resource_entry *entry;\n+\tresource_size_t mask;\n+\n+\tentry = resource_list_first_type(&bridge->windows, IORESOURCE_MEM);\n+\tif (!entry) {\n+\t\tpr_err(\"Cannot get memory resource\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (mips_cps_numiocu(0)) {\n+\t\t/*\n+\t\t * Hardware doesn't accept mask values with 1s after\n+\t\t * 0s (e.g. 0xffef), so warn if that's happen\n+\t\t */\n+\t\tmask = ~(entry->res->end - entry->res->start) & CM_GCR_REGn_MASK_ADDRMASK;\n+\t\tWARN_ON(mask && BIT(ffz(~mask)) - 1 != ~mask);\n+\n+\t\twrite_gcr_reg1_base(entry->res->start);\n+\t\twrite_gcr_reg1_mask(mask | CM_GCR_REGn_MASK_CMTGT_IOCU0);\n+\t\tpr_info(\"PCI coherence region base: 0x%08llx, mask/settings: 0x%08llx\\n\",\n+\t\t\t(unsigned long long)read_gcr_reg1_base(),\n+\t\t\t(unsigned long long)read_gcr_reg1_mask());\n+\t}\n+\n+\treturn 0;\n+}\n+\n phys_addr_t mips_cpc_default_phys_base(void)\n {\n \tpanic(\"Cannot detect cpc address\");\n--- a/drivers/pci/controller/pcie-mt7621.c\n+++ b/drivers/pci/controller/pcie-mt7621.c\n@@ -208,37 +208,6 @@ static inline void mt7621_control_deasse\n \t\treset_control_assert(port->pcie_rst);\n }\n \n-static int setup_cm_memory_region(struct pci_host_bridge *host)\n-{\n-\tstruct mt7621_pcie *pcie = pci_host_bridge_priv(host);\n-\tstruct device *dev = pcie->dev;\n-\tstruct resource_entry *entry;\n-\tresource_size_t mask;\n-\n-\tentry = resource_list_first_type(&host->windows, IORESOURCE_MEM);\n-\tif (!entry) {\n-\t\tdev_err(dev, \"cannot get memory resource\\n\");\n-\t\treturn -EINVAL;\n-\t}\n-\n-\tif (mips_cps_numiocu(0)) {\n-\t\t/*\n-\t\t * FIXME: hardware doesn't accept mask values with 1s after\n-\t\t * 0s (e.g. 0xffef), so it would be great to warn if that's\n-\t\t * about to happen\n-\t\t */\n-\t\tmask = ~(entry->res->end - entry->res->start);\n-\n-\t\twrite_gcr_reg1_base(entry->res->start);\n-\t\twrite_gcr_reg1_mask(mask | CM_GCR_REGn_MASK_CMTGT_IOCU0);\n-\t\tdev_info(dev, \"PCI coherence region base: 0x%08llx, mask/settings: 0x%08llx\\n\",\n-\t\t\t (unsigned long long)read_gcr_reg1_base(),\n-\t\t\t (unsigned long long)read_gcr_reg1_mask());\n-\t}\n-\n-\treturn 0;\n-}\n-\n static int mt7621_pcie_parse_port(struct mt7621_pcie *pcie,\n \t\t\t\t  struct device_node *node,\n \t\t\t\t  int slot)\n@@ -557,12 +526,6 @@ static int mt7621_pcie_probe(struct plat\n \t\tgoto remove_resets;\n \t}\n \n-\terr = setup_cm_memory_region(bridge);\n-\tif (err) {\n-\t\tdev_err(dev, \"error setting up iocu mem regions\\n\");\n-\t\tgoto remove_resets;\n-\t}\n-\n \treturn mt7621_pcie_register_host(bridge);\n \n remove_resets:\n"
  },
  {
    "path": "target/linux/ramips/patches-5.15/104-PCI-mt7621-Drop-of_match_ptr-to-avoid-unused-variabl.patch",
    "content": "From: Sergio Paracuellos <sergio.paracuellos@gmail.com>\nDate: Mon, 24 Jan 2022 12:30:02 +0100\nSubject: [PATCH] PCI: mt7621: Drop of_match_ptr() to avoid unused variable\n\nWe have stubs for most OF interfaces even when CONFIG_OF is not set, so we\nallow building of pcie-mt7621.c in that case for compile testing.\n\nWhen CONFIG_OF is not set, \"of_match_ptr(mt7621_pcie_ids)\" compiles to\nNULL, which leaves mt7621_pcie_ids unused:\n\n  $ make W=1\n  drivers/pci/controller/pcie-mt7621.c:549:34: warning: unused variable 'mt7621_pcie_ids' [-Wunused-const-variable]\n\nDrop of_match_ptr() to avoid the unused variable warning.\n\n[bhelgaas: commit log]\nFixes: 2bdd5238e756 (\"PCI: mt7621: Add MediaTek MT7621 PCIe host controller driver\")\nLink: https://lore.kernel.org/r/20220124113003.406224-2-sergio.paracuellos@gmail.com\nLink: https://lore.kernel.org/r/202201241754.igtHzgHv-lkp@intel.com\nReported-by: kernel test robot <lkp@intel.com>\nSigned-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>\nSigned-off-by: Bjorn Helgaas <bhelgaas@google.com>\n---\n\n--- a/drivers/pci/controller/pcie-mt7621.c\n+++ b/drivers/pci/controller/pcie-mt7621.c\n@@ -557,7 +557,7 @@ static struct platform_driver mt7621_pci\n \t.remove = mt7621_pcie_remove,\n \t.driver = {\n \t\t.name = \"mt7621-pci\",\n-\t\t.of_match_table = of_match_ptr(mt7621_pcie_ids),\n+\t\t.of_match_table = mt7621_pcie_ids,\n \t},\n };\n builtin_platform_driver(mt7621_pcie_driver);\n"
  },
  {
    "path": "target/linux/ramips/patches-5.15/105-PCI-mt7621-Remove-unused-function-pcie_rmw.patch",
    "content": "From: Sergio Paracuellos <sergio.paracuellos@gmail.com>\nDate: Mon, 24 Jan 2022 12:30:03 +0100\nSubject: [PATCH] PCI: mt7621: Remove unused function pcie_rmw()\n\nFunction pcie_rmw() is not being used at all and can be deleted. Hence get\nrid of it, which fixes this warning:\n\n  drivers/pci/controller/pcie-mt7621.c:112:20: warning: unused function 'pcie_rmw' [-Wunused-function]\n\nFixes: 2bdd5238e756 (\"PCI: mt7621: Add MediaTek MT7621 PCIe host controller driver\")\nLink: https://lore.kernel.org/r/20220124113003.406224-3-sergio.paracuellos@gmail.com\nLink: https://lore.kernel.org/all/202201241754.igtHzgHv-lkp@intel.com/\nReported-by: kernel test robot <lkp@intel.com>\nSigned-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>\nSigned-off-by: Bjorn Helgaas <bhelgaas@google.com>\n---\n\n--- a/drivers/pci/controller/pcie-mt7621.c\n+++ b/drivers/pci/controller/pcie-mt7621.c\n@@ -109,15 +109,6 @@ static inline void pcie_write(struct mt7\n \twritel_relaxed(val, pcie->base + reg);\n }\n \n-static inline void pcie_rmw(struct mt7621_pcie *pcie, u32 reg, u32 clr, u32 set)\n-{\n-\tu32 val = readl_relaxed(pcie->base + reg);\n-\n-\tval &= ~clr;\n-\tval |= set;\n-\twritel_relaxed(val, pcie->base + reg);\n-}\n-\n static inline u32 pcie_port_read(struct mt7621_pcie_port *port, u32 reg)\n {\n \treturn readl_relaxed(port->base + reg);\n"
  },
  {
    "path": "target/linux/ramips/patches-5.15/106-PCI-Let-pcibios_root_bridge_prepare-access-bridge-wi.patch",
    "content": "From: Sergio Paracuellos <sergio.paracuellos@gmail.com>\nDate: Tue, 7 Dec 2021 11:49:20 +0100\nSubject: [PATCH] PCI: Let pcibios_root_bridge_prepare() access bridge->windows\n\nWhen pci_register_host_bridge() is called, bridge->windows are already\navailable. However these windows are being moved temporarily from there.\n\nTo let pcibios_root_bridge_prepare() have access to these windows, move the\nwindows movement after calling this function. This is useful for the MIPS\nralink mt7621 platform so it can set up I/O coherence units and avoid\ncustom MIPS code in the mt7621 PCIe controller driver.\n\nLink: https://lore.kernel.org/r/20211207104924.21327-2-sergio.paracuellos@gmail.com\nSigned-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>\nSigned-off-by: Bjorn Helgaas <bhelgaas@google.com>\nAcked-by: Arnd Bergmann <arnd@arndb.de>\n---\n\n--- a/drivers/pci/probe.c\n+++ b/drivers/pci/probe.c\n@@ -898,8 +898,6 @@ static int pci_register_host_bridge(stru\n \n \tbridge->bus = bus;\n \n-\t/* Temporarily move resources off the list */\n-\tlist_splice_init(&bridge->windows, &resources);\n \tbus->sysdata = bridge->sysdata;\n \tbus->ops = bridge->ops;\n \tbus->number = bus->busn_res.start = bridge->busnr;\n@@ -925,6 +923,8 @@ static int pci_register_host_bridge(stru\n \tif (err)\n \t\tgoto free;\n \n+\t/* Temporarily move resources off the list */\n+\tlist_splice_init(&bridge->windows, &resources);\n \terr = device_add(&bridge->dev);\n \tif (err) {\n \t\tput_device(&bridge->dev);\n"
  },
  {
    "path": "target/linux/ramips/patches-5.15/110-reset_controller_driver.patch",
    "content": "--- a/arch/mips/ralink/reset.c\n+++ b/arch/mips/ralink/reset.c\n@@ -11,6 +11,7 @@\n #include <linux/of.h>\n #include <linux/delay.h>\n #include <linux/reset-controller.h>\n+#include <linux/platform_device.h>\n \n #include <asm/reboot.h>\n \n@@ -65,21 +66,39 @@ static const struct reset_control_ops re\n \t.deassert = ralink_deassert_device,\n };\n \n-static struct reset_controller_dev reset_dev = {\n-\t.ops\t\t\t= &reset_ops,\n-\t.owner\t\t\t= THIS_MODULE,\n-\t.nr_resets\t\t= 32,\n-\t.of_reset_n_cells\t= 1,\n+static int ralink_reset_probe(struct platform_device *pdev)\n+{\n+\tstruct reset_controller_dev *rcdev;\n+\n+\trcdev = devm_kzalloc(&pdev->dev, sizeof(*rcdev), GFP_KERNEL);\n+\tif (!rcdev)\n+\t\treturn -ENOMEM;\n+\n+\trcdev->ops = &reset_ops;\n+\trcdev->owner = THIS_MODULE;\n+\trcdev->nr_resets = 32;\n+\trcdev->of_reset_n_cells = 1;\n+\trcdev->of_node = pdev->dev.of_node;\n+\n+\treturn devm_reset_controller_register(&pdev->dev, rcdev);\n+}\n+\n+static const struct of_device_id ralink_reset_dt_ids[] = {\n+\t{ .compatible = \"ralink,rt2880-reset\" },\n+\t{}\n+};\n+\n+static struct platform_driver ralink_reset_driver = {\n+\t.probe = ralink_reset_probe,\n+\t.driver = {\n+\t\t.name = \"ralink-reset\",\n+\t\t.of_match_table = ralink_reset_dt_ids,\n+\t}\n };\n \n void ralink_rst_init(void)\n {\n-\treset_dev.of_node = of_find_compatible_node(NULL, NULL,\n-\t\t\t\t\t\t\"ralink,rt2880-reset\");\n-\tif (!reset_dev.of_node)\n-\t\tpr_err(\"Failed to find reset controller node\");\n-\telse\n-\t\treset_controller_register(&reset_dev);\n+\tplatform_driver_register(&ralink_reset_driver);\n }\n \n static void ralink_restart(char *command)\n"
  },
  {
    "path": "target/linux/ramips/patches-5.15/200-add-ralink-eth.patch",
    "content": "--- a/drivers/net/ethernet/Kconfig\n+++ b/drivers/net/ethernet/Kconfig\n@@ -162,6 +162,7 @@ source \"drivers/net/ethernet/pensando/Kc\n source \"drivers/net/ethernet/qlogic/Kconfig\"\n source \"drivers/net/ethernet/brocade/Kconfig\"\n source \"drivers/net/ethernet/qualcomm/Kconfig\"\n+source \"drivers/net/ethernet/ralink/Kconfig\"\n source \"drivers/net/ethernet/rdc/Kconfig\"\n source \"drivers/net/ethernet/realtek/Kconfig\"\n source \"drivers/net/ethernet/renesas/Kconfig\"\n--- a/drivers/net/ethernet/Makefile\n+++ b/drivers/net/ethernet/Makefile\n@@ -73,6 +73,7 @@ obj-$(CONFIG_NET_VENDOR_PACKET_ENGINES)\n obj-$(CONFIG_NET_VENDOR_PASEMI) += pasemi/\n obj-$(CONFIG_NET_VENDOR_QLOGIC) += qlogic/\n obj-$(CONFIG_NET_VENDOR_QUALCOMM) += qualcomm/\n+obj-$(CONFIG_NET_VENDOR_RALINK) += ralink/\n obj-$(CONFIG_NET_VENDOR_REALTEK) += realtek/\n obj-$(CONFIG_NET_VENDOR_RENESAS) += renesas/\n obj-$(CONFIG_NET_VENDOR_RDC) += rdc/\n"
  },
  {
    "path": "target/linux/ramips/patches-5.15/300-mt7620-export-chip-version-and-pkg.patch",
    "content": "--- a/arch/mips/include/asm/mach-ralink/mt7620.h\n+++ b/arch/mips/include/asm/mach-ralink/mt7620.h\n@@ -96,4 +96,16 @@ static inline int mt7620_get_eco(void)\n \treturn rt_sysc_r32(SYSC_REG_CHIP_REV) & CHIP_REV_ECO_MASK;\n }\n \n+static inline int mt7620_get_chipver(void)\n+{\n+\treturn (rt_sysc_r32(SYSC_REG_CHIP_REV) >> CHIP_REV_VER_SHIFT) &\n+\t\tCHIP_REV_VER_MASK;\n+}\n+\n+static inline int mt7620_get_pkg(void)\n+{\n+\treturn (rt_sysc_r32(SYSC_REG_CHIP_REV) >> CHIP_REV_PKG_SHIFT) &\n+\t\tCHIP_REV_PKG_MASK;\n+}\n+\n #endif\n"
  },
  {
    "path": "target/linux/ramips/patches-5.15/311-MIPS-use-set_mode-to-enable-disable-the-cevt-r4k-irq.patch",
    "content": "From ce3d4a4111a5f7e6b4e74bceae5faa6ce388e8ec Mon Sep 17 00:00:00 2001\nFrom: John Crispin <blogic@openwrt.org>\nDate: Sun, 14 Jul 2013 23:08:11 +0200\nSubject: [PATCH 05/53] MIPS: use set_mode() to enable/disable the cevt-r4k\n irq\n\nSigned-off-by: John Crispin <blogic@openwrt.org>\n---\n arch/mips/ralink/Kconfig |    5 +++++\n 1 file changed, 5 insertions(+)\n\n--- a/arch/mips/ralink/Kconfig\n+++ b/arch/mips/ralink/Kconfig\n@@ -1,12 +1,17 @@\n # SPDX-License-Identifier: GPL-2.0\n if RALINK\n \n+config CEVT_SYSTICK_QUIRK\n+\tbool\n+\tdefault n\n+\n config CLKEVT_RT3352\n \tbool\n \tdepends on SOC_RT305X || SOC_MT7620\n \tdefault y\n \tselect TIMER_OF\n \tselect CLKSRC_MMIO\n+\tselect CEVT_SYSTICK_QUIRK\n \n config RALINK_ILL_ACC\n \tbool\n--- a/arch/mips/kernel/cevt-r4k.c\n+++ b/arch/mips/kernel/cevt-r4k.c\n@@ -16,6 +16,31 @@\n #include <asm/time.h>\n #include <asm/cevt-r4k.h>\n \n+#ifdef CONFIG_CEVT_SYSTICK_QUIRK\n+static int mips_state_oneshot(struct clock_event_device *evt)\n+{\n+\tunsigned long flags = IRQF_PERCPU | IRQF_TIMER | IRQF_SHARED;\n+\tif (!cp0_timer_irq_installed) {\n+\t\tcp0_timer_irq_installed = 1;\n+\t\tif (request_irq(evt->irq, c0_compare_interrupt, flags, \"timer\",\n+\t\t\t\t\tc0_compare_interrupt))\n+\t\t\tpr_err(\"Failed to request irq %d (timer)\\n\", evt->irq);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int mips_state_shutdown(struct clock_event_device *evt)\n+{\n+\tif (cp0_timer_irq_installed) {\n+\t\tcp0_timer_irq_installed = 0;\n+\t\tfree_irq(evt->irq, NULL);\n+\t}\n+\n+\treturn 0;\n+}\n+#endif\n+\n static int mips_next_event(unsigned long delta,\n \t\t\t   struct clock_event_device *evt)\n {\n@@ -292,7 +317,9 @@ core_initcall(r4k_register_cpufreq_notif\n \n int r4k_clockevent_init(void)\n {\n+#ifndef CONFIG_CEVT_SYSTICK_QUIRK\n \tunsigned long flags = IRQF_PERCPU | IRQF_TIMER | IRQF_SHARED;\n+#endif\n \tunsigned int cpu = smp_processor_id();\n \tstruct clock_event_device *cd;\n \tunsigned int irq, min_delta;\n@@ -322,11 +349,16 @@ int r4k_clockevent_init(void)\n \tcd->rating\t\t= 300;\n \tcd->irq\t\t\t= irq;\n \tcd->cpumask\t\t= cpumask_of(cpu);\n+#ifdef CONFIG_CEVT_SYSTICK_QUIRK\n+\tcd->set_state_shutdown\t= mips_state_shutdown;\n+\tcd->set_state_oneshot\t= mips_state_oneshot;\n+#endif\n \tcd->set_next_event\t= mips_next_event;\n \tcd->event_handler\t= mips_event_handler;\n \n \tclockevents_config_and_register(cd, mips_hpt_frequency, min_delta, 0x7fffffff);\n \n+#ifndef CONFIG_CEVT_SYSTICK_QUIRK\n \tif (cp0_timer_irq_installed)\n \t\treturn 0;\n \n@@ -335,6 +367,7 @@ int r4k_clockevent_init(void)\n \tif (request_irq(irq, c0_compare_interrupt, flags, \"timer\",\n \t\t\tc0_compare_interrupt))\n \t\tpr_err(\"Failed to request irq %d (timer)\\n\", irq);\n+#endif\n \n \treturn 0;\n }\n"
  },
  {
    "path": "target/linux/ramips/patches-5.15/312-MIPS-ralink-add-cpu-frequency-scaling.patch",
    "content": "From bd30f19a006fb52bac80c6463c49dd2f4159f4ac Mon Sep 17 00:00:00 2001\nFrom: John Crispin <blogic@openwrt.org>\nDate: Sun, 28 Jul 2013 16:26:41 +0200\nSubject: [PATCH 06/53] MIPS: ralink: add cpu frequency scaling\n\nThis feature will break udelay() and cause the delay loop to have longer delays\nwhen the frequency is scaled causing a performance hit.\n\nSigned-off-by: John Crispin <blogic@openwrt.org>\n---\n arch/mips/ralink/cevt-rt3352.c |   38 ++++++++++++++++++++++++++++++++++++++\n 1 file changed, 38 insertions(+)\n\n--- a/arch/mips/ralink/cevt-rt3352.c\n+++ b/arch/mips/ralink/cevt-rt3352.c\n@@ -29,6 +29,10 @@\n /* enable the counter */\n #define CFG_CNT_EN\t\t0x1\n \n+/* mt7620 frequency scaling defines */\n+#define CLK_LUT_CFG\t0x40\n+#define SLEEP_EN\tBIT(31)\n+\n struct systick_device {\n \tvoid __iomem *membase;\n \tstruct clock_event_device dev;\n@@ -36,21 +40,53 @@ struct systick_device {\n \tint freq_scale;\n };\n \n+static void (*systick_freq_scaling)(struct systick_device *sdev, int status);\n+\n static int systick_set_oneshot(struct clock_event_device *evt);\n static int systick_shutdown(struct clock_event_device *evt);\n \n+static inline void mt7620_freq_scaling(struct systick_device *sdev, int status)\n+{\n+\tif (sdev->freq_scale == status)\n+\t\treturn;\n+\n+\tsdev->freq_scale = status;\n+\n+\tpr_info(\"%s: %s autosleep mode\\n\", sdev->dev.name,\n+\t\t\t(status) ? (\"enable\") : (\"disable\"));\n+\tif (status)\n+\t\trt_sysc_w32(rt_sysc_r32(CLK_LUT_CFG) | SLEEP_EN, CLK_LUT_CFG);\n+\telse\n+\t\trt_sysc_w32(rt_sysc_r32(CLK_LUT_CFG) & ~SLEEP_EN, CLK_LUT_CFG);\n+}\n+\n+static inline unsigned int read_count(struct systick_device *sdev)\n+{\n+\treturn ioread32(sdev->membase + SYSTICK_COUNT);\n+}\n+\n+static inline unsigned int read_compare(struct systick_device *sdev)\n+{\n+\treturn ioread32(sdev->membase + SYSTICK_COMPARE);\n+}\n+\n+static inline void write_compare(struct systick_device *sdev, unsigned int val)\n+{\n+\tiowrite32(val, sdev->membase + SYSTICK_COMPARE);\n+}\n+\n static int systick_next_event(unsigned long delta,\n \t\t\t\tstruct clock_event_device *evt)\n {\n \tstruct systick_device *sdev;\n-\tu32 count;\n+\tint res;\n \n \tsdev = container_of(evt, struct systick_device, dev);\n-\tcount = ioread32(sdev->membase + SYSTICK_COUNT);\n-\tcount = (count + delta) % SYSTICK_FREQ;\n-\tiowrite32(count, sdev->membase + SYSTICK_COMPARE);\n+\tdelta += read_count(sdev);\n+\twrite_compare(sdev, delta);\n+\tres = ((int)(read_count(sdev) - delta) >= 0) ? -ETIME : 0;\n \n-\treturn 0;\n+\treturn res;\n }\n \n static void systick_event_handler(struct clock_event_device *dev)\n@@ -60,20 +96,25 @@ static void systick_event_handler(struct\n \n static irqreturn_t systick_interrupt(int irq, void *dev_id)\n {\n-\tstruct clock_event_device *dev = (struct clock_event_device *) dev_id;\n+\tint ret = 0;\n+\tstruct clock_event_device *cdev;\n+\tstruct systick_device *sdev;\n \n-\tdev->event_handler(dev);\n+\tif (read_c0_cause() & STATUSF_IP7) {\n+\t\tcdev = (struct clock_event_device *) dev_id;\n+\t\tsdev = container_of(cdev, struct systick_device, dev);\n+\n+\t\t/* Clear Count/Compare Interrupt */\n+\t\twrite_compare(sdev, read_compare(sdev));\n+\t\tcdev->event_handler(cdev);\n+\t\tret = 1;\n+\t}\n \n-\treturn IRQ_HANDLED;\n+\treturn IRQ_RETVAL(ret);\n }\n \n static struct systick_device systick = {\n \t.dev = {\n-\t\t/*\n-\t\t * cevt-r4k uses 300, make sure systick\n-\t\t * gets used if available\n-\t\t */\n-\t\t.rating\t\t\t= 310,\n \t\t.features\t\t= CLOCK_EVT_FEAT_ONESHOT,\n \t\t.set_next_event\t\t= systick_next_event,\n \t\t.set_state_shutdown\t= systick_shutdown,\n@@ -91,7 +132,13 @@ static int systick_shutdown(struct clock\n \tif (sdev->irq_requested)\n \t\tfree_irq(systick.dev.irq, &systick.dev);\n \tsdev->irq_requested = 0;\n-\tiowrite32(0, systick.membase + SYSTICK_CONFIG);\n+\tiowrite32(CFG_CNT_EN, systick.membase + SYSTICK_CONFIG);\n+\n+\tif (systick_freq_scaling)\n+\t\tsystick_freq_scaling(sdev, 0);\n+\n+\tif (systick_freq_scaling)\n+\t\tsystick_freq_scaling(sdev, 1);\n \n \treturn 0;\n }\n@@ -116,33 +163,46 @@ static int systick_set_oneshot(struct cl\n \treturn 0;\n }\n \n+static const struct of_device_id systick_match[] = {\n+\t{ .compatible = \"ralink,mt7620a-systick\", .data = mt7620_freq_scaling},\n+\t{},\n+};\n+\n static int __init ralink_systick_init(struct device_node *np)\n {\n-\tint ret;\n+\tconst struct of_device_id *match;\n+\tint rating = 200;\n \n \tsystick.membase = of_iomap(np, 0);\n \tif (!systick.membase)\n \t\treturn -ENXIO;\n \n-\tsystick.dev.name = np->name;\n-\tclockevents_calc_mult_shift(&systick.dev, SYSTICK_FREQ, 60);\n-\tsystick.dev.max_delta_ns = clockevent_delta2ns(0x7fff, &systick.dev);\n-\tsystick.dev.max_delta_ticks = 0x7fff;\n-\tsystick.dev.min_delta_ns = clockevent_delta2ns(0x3, &systick.dev);\n-\tsystick.dev.min_delta_ticks = 0x3;\n+\tmatch = of_match_node(systick_match, np);\n+\tif (match) {\n+\t\tsystick_freq_scaling = match->data;\n+\t\t/*\n+\t\t * cevt-r4k uses 300, make sure systick\n+\t\t * gets used if available\n+\t\t */\n+\t\trating = 310;\n+\t}\n+\n+\t/* enable counter than register clock source */\n+\tiowrite32(CFG_CNT_EN, systick.membase + SYSTICK_CONFIG);\n+\tclocksource_mmio_init(systick.membase + SYSTICK_COUNT, np->name,\n+\t\t\tSYSTICK_FREQ, rating, 16, clocksource_mmio_readl_up);\n+\n+\t/* register clock event */\n \tsystick.dev.irq = irq_of_parse_and_map(np, 0);\n \tif (!systick.dev.irq) {\n \t\tpr_err(\"%pOFn: request_irq failed\", np);\n \t\treturn -EINVAL;\n \t}\n \n-\tret = clocksource_mmio_init(systick.membase + SYSTICK_COUNT, np->name,\n-\t\t\t\t    SYSTICK_FREQ, 301, 16,\n-\t\t\t\t    clocksource_mmio_readl_up);\n-\tif (ret)\n-\t\treturn ret;\n-\n-\tclockevents_register_device(&systick.dev);\n+\tsystick.dev.name = np->name;\n+\tsystick.dev.rating = rating;\n+\tsystick.dev.cpumask = cpumask_of(0);\n+\tclockevents_config_and_register(&systick.dev, SYSTICK_FREQ, 0x3, 0x7fff);\n \n \tpr_info(\"%pOFn: running - mult: %d, shift: %d\\n\",\n \t\t\tnp, systick.dev.mult, systick.dev.shift);\n"
  },
  {
    "path": "target/linux/ramips/patches-5.15/314-MIPS-add-bootargs-override-property.patch",
    "content": "From f15d27f9c90ede4b16eb37f9ae573ef81c2b6996 Mon Sep 17 00:00:00 2001\nFrom: David Bauer <mail@david-bauer.net>\nDate: Thu, 31 Dec 2020 18:49:12 +0100\nSubject: [PATCH] MIPS: add bootargs-override property\n\nAdd support for the bootargs-override property to the chosen node\nsimilar to the one used on ipq806x or mpc85xx.\n\nThis is necessary, as the U-Boot used on some boards, notably the\nUbiquiti UniFi 6 Lite, overwrite the bootargs property of the chosen\nnode leading to a kernel panic when loading OpenWrt.\n\nSigned-off-by: David Bauer <mail@david-bauer.net>\n---\n arch/mips/kernel/setup.c | 30 ++++++++++++++++++++++++++++++\n 1 file changed, 30 insertions(+)\n\n--- a/arch/mips/kernel/setup.c\n+++ b/arch/mips/kernel/setup.c\n@@ -544,8 +544,28 @@ static int __init bootcmdline_scan_chose\n \n #endif /* CONFIG_OF_EARLY_FLATTREE */\n \n+static int __init bootcmdline_scan_chosen_override(unsigned long node, const char *uname,\n+\t\t\t\t\t\t   int depth, void *data)\n+{\n+\tbool *dt_bootargs = data;\n+\tconst char *p;\n+\tint l;\n+\n+\tif (depth != 1 || !data || strcmp(uname, \"chosen\") != 0)\n+\t\treturn 0;\n+\n+\tp = of_get_flat_dt_prop(node, \"bootargs-override\", &l);\n+\tif (p != NULL && l > 0) {\n+\t\tstrlcpy(boot_command_line, p, COMMAND_LINE_SIZE);\n+\t\t*dt_bootargs = true;\n+\t}\n+\n+\treturn 1;\n+}\n+\n static void __init bootcmdline_init(void)\n {\n+\tbool dt_bootargs_override = false;\n \tbool dt_bootargs = false;\n \n \t/*\n@@ -559,6 +579,14 @@ static void __init bootcmdline_init(void\n \t}\n \n \t/*\n+\t * If bootargs-override in the chosen node is set, use this as the\n+\t * command line\n+\t */\n+\tof_scan_flat_dt(bootcmdline_scan_chosen_override, &dt_bootargs_override);\n+\tif (dt_bootargs_override)\n+\t\treturn;\n+\n+\t/*\n \t * If the user specified a built-in command line &\n \t * MIPS_CMDLINE_BUILTIN_EXTEND, then the built-in command line is\n \t * prepended to arguments from the bootloader or DT so we'll copy them\n"
  },
  {
    "path": "target/linux/ramips/patches-5.15/315-owrt-hack-fix-mt7688-cache-issue.patch",
    "content": "From 5ede027f6c4a57ed25da872420508b7f1168b36b Mon Sep 17 00:00:00 2001\nFrom: John Crispin <blogic@openwrt.org>\nDate: Mon, 7 Dec 2015 17:15:32 +0100\nSubject: [PATCH 13/53] owrt: hack: fix mt7688 cache issue\n\nSigned-off-by: John Crispin <blogic@openwrt.org>\n---\n arch/mips/kernel/setup.c |    2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/arch/mips/kernel/setup.c\n+++ b/arch/mips/kernel/setup.c\n@@ -686,7 +686,6 @@ static void __init arch_mem_init(char **\n \tmips_reserve_vmcore();\n \n \tmips_parse_crashkernel();\n-\tdevice_tree_init();\n \n \t/*\n \t * In order to reduce the possibility of kernel panic when failed to\n@@ -803,6 +802,7 @@ void __init setup_arch(char **cmdline_p)\n \n \tcpu_cache_init();\n \tpaging_init();\n+\tdevice_tree_init();\n \n \tmemblock_dump_all();\n }\n"
  },
  {
    "path": "target/linux/ramips/patches-5.15/316-arch-mips-do-not-select-illegal-access-driver-by-def.patch",
    "content": "From 9e6ce539092a1dd605a20bf73c655a9de58d8641 Mon Sep 17 00:00:00 2001\nFrom: John Crispin <blogic@openwrt.org>\nDate: Mon, 7 Dec 2015 17:18:05 +0100\nSubject: [PATCH 15/53] arch: mips: do not select illegal access driver by\n default\n\nSigned-off-by: John Crispin <blogic@openwrt.org>\n---\n arch/mips/ralink/Kconfig |    4 ++--\n 1 file changed, 2 insertions(+), 2 deletions(-)\n\n--- a/arch/mips/ralink/Kconfig\n+++ b/arch/mips/ralink/Kconfig\n@@ -14,9 +14,9 @@ config CLKEVT_RT3352\n \tselect CEVT_SYSTICK_QUIRK\n \n config RALINK_ILL_ACC\n-\tbool\n+\tbool \"illegal access irq\"\n \tdepends on SOC_RT305X\n-\tdefault y\n+\tdefault n\n \n config IRQ_INTC\n \tbool\n"
  },
  {
    "path": "target/linux/ramips/patches-5.15/320-MIPS-add-support-for-buggy-MT7621S-core-detection.patch",
    "content": "From 6decd1aad15f56b169217789630a0098b496de0e Mon Sep 17 00:00:00 2001\nFrom: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com>\nDate: Wed, 7 Apr 2021 13:07:38 -0700\nSubject: [PATCH] MIPS: add support for buggy MT7621S core detection\n\nMost MT7621 SoCs have 2 cores, which is detected and supported properly\nby CPS.\n\nUnfortunately, MT7621 SoC has a less common S variant with only one core.\nOn MT7621S, GCR_CONFIG still reports 2 cores, which leads to hangs when\nstarting SMP. CPULAUNCH registers can be used in that case to detect the\nabsence of the second core and override the GCR_CONFIG PCORES field.\n\nRework a long-standing OpenWrt patch to override the value of\nmips_cps_numcores on single-core MT7621 systems.\n\nTested on a dual-core MT7621 device (Ubiquiti ER-X) and a single-core\nMT7621 device (Netgear R6220).\n\nOriginal 4.14 OpenWrt patch:\nLink: https://git.openwrt.org/?p=openwrt/openwrt.git;a=commitdiff;h=4cdbc90a376dd0555201c1434a2081e055e9ceb7\nCurrent 5.10 OpenWrt patch:\nLink: https://git.openwrt.org/?p=openwrt/openwrt.git;a=blob;f=target/linux/ramips/patches-5.10/320-mt7621-core-detect-hack.patch;h=c63f0f4c1ec742e24d8480e80553863744b58f6a;hb=10267e17299806f9885d086147878f6c492cb904\n\nSuggested-by: Felix Fietkau <nbd@nbd.name>\nSigned-off-by: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com>\nSigned-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>\n---\n arch/mips/include/asm/mips-cps.h | 23 ++++++++++++++++++++++-\n 1 file changed, 22 insertions(+), 1 deletion(-)\n\n--- a/arch/mips/include/asm/mips-cps.h\n+++ b/arch/mips/include/asm/mips-cps.h\n@@ -10,6 +10,8 @@\n #include <linux/io.h>\n #include <linux/types.h>\n \n+#include <asm/mips-boards/launch.h>\n+\n extern unsigned long __cps_access_bad_size(void)\n \t__compiletime_error(\"Bad size for CPS accessor\");\n \n@@ -165,11 +167,30 @@ static inline uint64_t mips_cps_cluster_\n  */\n static inline unsigned int mips_cps_numcores(unsigned int cluster)\n {\n+\tunsigned int ncores;\n+\n \tif (!mips_cm_present())\n \t\treturn 0;\n \n \t/* Add one before masking to handle 0xff indicating no cores */\n-\treturn (mips_cps_cluster_config(cluster) + 1) & CM_GCR_CONFIG_PCORES;\n+\tncores = (mips_cps_cluster_config(cluster) + 1) & CM_GCR_CONFIG_PCORES;\n+\n+\tif (IS_ENABLED(CONFIG_SOC_MT7621)) {\n+\t\tstruct cpulaunch *launch;\n+\n+\t\t/*\n+\t\t * Ralink MT7621S SoC is single core, but the GCR_CONFIG method\n+\t\t * always reports 2 cores. Check the second core's LAUNCH_FREADY\n+\t\t * flag to detect if the second core is missing. This method\n+\t\t * only works before the core has been started.\n+\t\t */\n+\t\tlaunch = (struct cpulaunch *)CKSEG0ADDR(CPULAUNCH);\n+\t\tlaunch += 2; /* MT7621 has 2 VPEs per core */\n+\t\tif (!(launch->flags & LAUNCH_FREADY))\n+\t\t\tncores = 1;\n+\t}\n+\n+\treturn ncores;\n }\n \n /**\n"
  },
  {
    "path": "target/linux/ramips/patches-5.15/324-mt7621-perfctr-fix.patch",
    "content": "--- a/arch/mips/ralink/irq-gic.c\n+++ b/arch/mips/ralink/irq-gic.c\n@@ -13,6 +13,12 @@\n \n int get_c0_perfcount_int(void)\n {\n+\t/*\n+\t * Performance counter events are routed through GIC.\n+\t * Prevent them from firing on CPU IRQ7 as well\n+\t */\n+\tclear_c0_status(IE_SW0 << 7);\n+\n \treturn gic_get_c0_perfcount_int();\n }\n EXPORT_SYMBOL_GPL(get_c0_perfcount_int);\n"
  },
  {
    "path": "target/linux/ramips/patches-5.15/400-mtd-cfi-cmdset-0002-force-word-write.patch",
    "content": "From ee9081b2726a5ca8cde5497afdc5425e21ff8f8b Mon Sep 17 00:00:00 2001\nFrom: John Crispin <blogic@openwrt.org>\nDate: Mon, 15 Jul 2013 00:39:21 +0200\nSubject: [PATCH 37/53] mtd: cfi cmdset 0002 force word write\n\n---\n drivers/mtd/chips/cfi_cmdset_0002.c |    9 +++++++--\n 1 file changed, 7 insertions(+), 2 deletions(-)\n\n--- a/drivers/mtd/chips/cfi_cmdset_0002.c\n+++ b/drivers/mtd/chips/cfi_cmdset_0002.c\n@@ -40,7 +40,7 @@\n #include <linux/mtd/xip.h>\n \n #define AMD_BOOTLOC_BUG\n-#define FORCE_WORD_WRITE 0\n+#define FORCE_WORD_WRITE 1\n \n #define MAX_RETRIES 3\n \n"
  },
  {
    "path": "target/linux/ramips/patches-5.15/405-mtd-spi-nor-Add-support-for-BoHong-bh25q128as.patch",
    "content": "From 52d14545d2fc276b1bf9ccf48d4612fab6edfb6a Mon Sep 17 00:00:00 2001\nFrom: David Bauer <mail@david-bauer.net>\nDate: Thu, 6 May 2021 17:49:55 +0200\nSubject: [PATCH] mtd: spi-nor: Add support for BoHong bh25q128as\n\nAdd MTD support for the BoHong bh25q128as SPI NOR chip.\nThe chip has 16MB of total capacity, divided into a total of 256\nsectors, each 64KB sized. The chip also supports 4KB sectors.\nAdditionally, it supports dual and quad read modes.\n\nFunctionality was verified on an Tenbay WR1800K / MTK MT7621 board.\n\nSigned-off-by: David Bauer <mail@david-bauer.net>\n---\n drivers/mtd/spi-nor/Makefile |  1 +\n drivers/mtd/spi-nor/bohong.c | 21 +++++++++++++++++++++\n drivers/mtd/spi-nor/core.c   |  1 +\n drivers/mtd/spi-nor/core.h   |  1 +\n 4 files changed, 24 insertions(+)\n create mode 100644 drivers/mtd/spi-nor/bohong.c\n\n--- a/drivers/mtd/spi-nor/Makefile\n+++ b/drivers/mtd/spi-nor/Makefile\n@@ -2,6 +2,7 @@\n \n spi-nor-objs\t\t\t:= core.o sfdp.o swp.o otp.o sysfs.o\n spi-nor-objs\t\t\t+= atmel.o\n+spi-nor-objs\t\t\t+= bohong.o\n spi-nor-objs\t\t\t+= catalyst.o\n spi-nor-objs\t\t\t+= eon.o\n spi-nor-objs\t\t\t+= esmt.o\n--- /dev/null\n+++ b/drivers/mtd/spi-nor/bohong.c\n@@ -0,0 +1,21 @@\n+// SPDX-License-Identifier: GPL-2.0\n+/*\n+ * Copyright (C) 2005, Intec Automation Inc.\n+ * Copyright (C) 2014, Freescale Semiconductor, Inc.\n+ */\n+\n+#include <linux/mtd/spi-nor.h>\n+\n+#include \"core.h\"\n+\n+static const struct flash_info bohong_parts[] = {\n+\t/* BoHong Microelectronics */\n+\t{ \"bh25q128as\", INFO(0x684018, 0, 64 * 1024, 256,\n+\t\t\t    SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },\n+};\n+\n+const struct spi_nor_manufacturer spi_nor_bohong = {\n+\t.name = \"bohong\",\n+\t.parts = bohong_parts,\n+\t.nparts = ARRAY_SIZE(bohong_parts),\n+};\n--- a/drivers/mtd/spi-nor/core.c\n+++ b/drivers/mtd/spi-nor/core.c\n@@ -1832,6 +1832,7 @@ int spi_nor_sr2_bit7_quad_enable(struct\n \n static const struct spi_nor_manufacturer *manufacturers[] = {\n \t&spi_nor_atmel,\n+\t&spi_nor_bohong,\n \t&spi_nor_catalyst,\n \t&spi_nor_eon,\n \t&spi_nor_esmt,\n--- a/drivers/mtd/spi-nor/core.h\n+++ b/drivers/mtd/spi-nor/core.h\n@@ -473,6 +473,7 @@ struct sfdp {\n \n /* Manufacturer drivers. */\n extern const struct spi_nor_manufacturer spi_nor_atmel;\n+extern const struct spi_nor_manufacturer spi_nor_bohong;\n extern const struct spi_nor_manufacturer spi_nor_catalyst;\n extern const struct spi_nor_manufacturer spi_nor_eon;\n extern const struct spi_nor_manufacturer spi_nor_esmt;\n"
  },
  {
    "path": "target/linux/ramips/patches-5.15/410-mtd-rawnand-add-driver-support-for-MT7621-nand-flash.patch",
    "content": "From e84e2430ee0e483842b4ff013ae8a6e7e2fa2734 Mon Sep 17 00:00:00 2001\nFrom: Weijie Gao <weijie.gao@mediatek.com>\nDate: Wed, 1 Apr 2020 02:07:58 +0800\nSubject: [PATCH 1/2] mtd: rawnand: add driver support for MT7621 nand\n flash controller\n\nThis patch adds NAND flash controller driver for MediaTek MT7621 SoC.\n\nThe NAND flash controller is similar with controllers described in\nmtk_nand.c, except that the controller from MT7621 doesn't support DMA\ntransmission, and some registers' offset and fields are different.\n\nSigned-off-by: Weijie Gao <weijie.gao@mediatek.com>\n---\n drivers/mtd/nand/raw/Kconfig       |    8 +\n drivers/mtd/nand/raw/Makefile      |    1 +\n drivers/mtd/nand/raw/mt7621_nand.c | 1348 ++++++++++++++++++++++++++++++++++++\n 3 files changed, 1357 insertions(+)\n create mode 100644 drivers/mtd/nand/raw/mt7621_nand.c\n\n--- a/drivers/mtd/nand/raw/Kconfig\n+++ b/drivers/mtd/nand/raw/Kconfig\n@@ -358,6 +358,14 @@ config MTD_NAND_QCOM\n \t  Enables support for NAND flash chips on SoCs containing the EBI2 NAND\n \t  controller. This controller is found on IPQ806x SoC.\n \n+config MTD_NAND_MT7621\n+\ttristate \"MT7621 NAND controller\"\n+\tdepends on SOC_MT7621 || COMPILE_TEST\n+\tdepends on HAS_IOMEM\n+\thelp\n+\t  Enables support for NAND controller on MT7621 SoC.\n+\t  This driver uses PIO mode for data transmission instead of DMA mode.\n+\n config MTD_NAND_MTK\n \ttristate \"MTK NAND controller\"\n \tdepends on ARCH_MEDIATEK || COMPILE_TEST\n--- a/drivers/mtd/nand/raw/Makefile\n+++ b/drivers/mtd/nand/raw/Makefile\n@@ -48,6 +48,7 @@ obj-$(CONFIG_MTD_NAND_SUNXI)\t\t+= sunxi_n\n obj-$(CONFIG_MTD_NAND_HISI504)\t        += hisi504_nand.o\n obj-$(CONFIG_MTD_NAND_BRCMNAND)\t\t+= brcmnand/\n obj-$(CONFIG_MTD_NAND_QCOM)\t\t+= qcom_nandc.o\n+obj-$(CONFIG_MTD_NAND_MT7621)\t\t+= mt7621_nand.o\n obj-$(CONFIG_MTD_NAND_MTK)\t\t+= mtk_ecc.o mtk_nand.o\n obj-$(CONFIG_MTD_NAND_MXIC)\t\t+= mxic_nand.o\n obj-$(CONFIG_MTD_NAND_TEGRA)\t\t+= tegra_nand.o\n"
  },
  {
    "path": "target/linux/ramips/patches-5.15/411-dt-bindings-add-documentation-for-mt7621-nand-driver.patch",
    "content": "From 3d5f4da8296b23eb3abf8b13122b0d06a215e79c Mon Sep 17 00:00:00 2001\nFrom: Weijie Gao <weijie.gao@mediatek.com>\nDate: Wed, 1 Apr 2020 02:07:59 +0800\nSubject: [PATCH 2/2] dt-bindings: add documentation for mt7621-nand driver\n\nThis patch adds documentation for MediaTek MT7621 NAND flash controller\ndriver.\n\nSigned-off-by: Weijie Gao <weijie.gao@mediatek.com>\n---\n .../bindings/mtd/mediatek,mt7621-nfc.yaml          | 68 ++++++++++++++++++++++\n 1 file changed, 68 insertions(+)\n create mode 100644 Documentation/devicetree/bindings/mtd/mediatek,mt7621-nfc.yaml\n\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/mtd/mediatek,mt7621-nfc.yaml\n@@ -0,0 +1,68 @@\n+# SPDX-License-Identifier: GPL-2.0\n+%YAML 1.2\n+---\n+$id: http://devicetree.org/schemas/mtd/mediatek,mt7621-nfc.yaml#\n+$schema: http://devicetree.org/meta-schemas/core.yaml#\n+\n+title: MediaTek MT7621 SoC NAND Flash Controller (NFC) DT binding\n+\n+maintainers:\n+  - Weijie Gao <weijie.gao@mediatek.com>\n+\n+description: |\n+  This driver uses a single node to describe both NAND Flash controller\n+  interface (NFI) and ECC engine for MT7621 SoC.\n+  MT7621 supports only one chip select.\n+\n+properties:\n+  \"#address-cells\": false\n+  \"#size-cells\": false\n+\n+  compatible:\n+    enum:\n+      - mediatek,mt7621-nfc\n+\n+  reg:\n+    items:\n+      - description: Register base of NFI core\n+      - description: Register base of ECC engine\n+\n+  reg-names:\n+    items:\n+      - const: nfi\n+      - const: ecc\n+\n+  clocks:\n+    items:\n+      - description: Source clock for NFI core, fixed 125MHz\n+\n+  clock-names:\n+    items:\n+      - const: nfi_clk\n+\n+required:\n+  - compatible\n+  - reg\n+  - reg-names\n+  - clocks\n+  - clock-names\n+\n+examples:\n+  - |\n+    nficlock: nficlock {\n+    \t#clock-cells = <0>;\n+    \tcompatible = \"fixed-clock\";\n+\n+    \tclock-frequency = <125000000>;\n+    };\n+\n+    nand@1e003000 {\n+    \tcompatible = \"mediatek,mt7621-nfc\";\n+\n+    \treg = <0x1e003000 0x800\n+    \t       0x1e003800 0x800>;\n+    \treg-names = \"nfi\", \"ecc\";\n+\n+    \tclocks = <&nficlock>;\n+    \tclock-names = \"nfi_clk\";\n+    };\n"
  },
  {
    "path": "target/linux/ramips/patches-5.15/700-net-ethernet-mediatek-support-net-labels.patch",
    "content": "From bd0f89de5476ca25e73fae829ba3e1dafae1d90d Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Ren=C3=A9=20van=20Dorst?= <opensource@vdorst.com>\nDate: Fri, 21 Jun 2019 10:04:05 +0200\nSubject: [PATCH] net: ethernet: mediatek: support net-labels\n\nWith this patch, device name can be set within dts file in the same way as dsa\nport can.\nAdd: label = \"wan\"; to GMAC node.\n\nSigned-off-by: René van Dorst <opensource@vdorst.com>\n---\n drivers/net/ethernet/mediatek/mtk_eth_soc.c | 4 ++++\n 1 file changed, 4 insertions(+)\n\n--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c\n+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c\n@@ -2968,6 +2968,7 @@ static const struct net_device_ops mtk_n\n \n static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np)\n {\n+\tconst char *name = of_get_property(np, \"label\", NULL);\n \tconst __be32 *_id = of_get_property(np, \"reg\", NULL);\n \tphy_interface_t phy_mode;\n \tstruct phylink *phylink;\n@@ -3063,6 +3064,9 @@ static int mtk_add_mac(struct mtk_eth *e\n \telse\n \t\teth->netdev[id]->max_mtu = MTK_MAX_RX_LENGTH_2K - MTK_RX_ETH_HLEN;\n \n+\tif (name)\n+\t\tstrlcpy(eth->netdev[id]->name, name, IFNAMSIZ);\n+\n \treturn 0;\n \n free_netdev:\n"
  },
  {
    "path": "target/linux/ramips/patches-5.15/710-at803x.patch",
    "content": "From 924453aa9d2324e5611f8e2b71df746d8f0c79f1 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Ren=C3=A9=20van=20Dorst?= <opensource@vdorst.com>\nDate: Fri, 13 Nov 2020 16:11:32 +0100\nSubject: [PATCH] net: phy: at803x: add support for SFP module in\n RGMII-to-x-base mode\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nSigned-off-by: René van Dorst <opensource@vdorst.com>\n---\n drivers/net/phy/at803x.c | 91 ++++++++++++++++++++++++++++++++++++++++\n 1 file changed, 91 insertions(+)\n\n--- a/drivers/net/phy/at803x.c\n+++ b/drivers/net/phy/at803x.c\n@@ -20,6 +20,8 @@\n #include <linux/regulator/driver.h>\n #include <linux/regulator/consumer.h>\n #include <dt-bindings/net/qca-ar803x.h>\n+#include <linux/sfp.h>\n+#include <linux/phylink.h>\n \n #define AT803X_SPECIFIC_FUNCTION_CONTROL\t0x10\n #define AT803X_SFC_ASSERT_CRS\t\t\tBIT(11)\n@@ -82,9 +84,18 @@\n \n #define AT803X_MODE_CFG_MASK\t\t\t0x0F\n #define AT803X_MODE_CFG_SGMII\t\t\t0x01\n+#define AT803X_MODE_CFG_BX1000_RGMII_50\t\t0x02\n+#define AT803X_MODE_CFG_BX1000_RGMII_75\t\t0x03\n+#define AT803X_MODE_FIBER\t\t\t0x01\n+#define AT803X_MODE_COPPER\t\t\t0x00\n \n #define AT803X_PSSR\t\t\t\t0x11\t/*PHY-Specific Status Register*/\n #define AT803X_PSSR_MR_AN_COMPLETE\t\t0x0200\n+#define\t PSSR_LINK\t\t\tBIT(10)\n+#define\t PSSR_SYNC_STATUS\t\tBIT(8)\n+#define\t PSSR_DUPLEX\t\t\tBIT(13)\n+#define\t PSSR_SPEED_1000\t\tBIT(15)\n+#define\t PSSR_SPEED_100\t\t\tBIT(14)\n \n #define AT803X_DEBUG_ANALOG_TEST_CTRL\t\t0x00\n #define QCA8327_DEBUG_MANU_CTRL_EN\t\tBIT(2)\n@@ -652,12 +663,75 @@ static int at803x_parse_dt(struct phy_de\n \treturn 0;\n }\n \n+static int at803x_mode(struct phy_device *phydev)\n+{\n+\tint mode;\n+\n+\tmode = phy_read(phydev, AT803X_REG_CHIP_CONFIG) & AT803X_MODE_CFG_MASK;\n+\n+\tif (mode == AT803X_MODE_CFG_BX1000_RGMII_50 ||\n+\t    mode == AT803X_MODE_CFG_BX1000_RGMII_75)\n+\t\treturn AT803X_MODE_FIBER;\n+\treturn AT803X_MODE_COPPER;\n+}\n+\n+static int at803x_sfp_insert(void *upstream, const struct sfp_eeprom_id *id)\n+{\n+\t__ETHTOOL_DECLARE_LINK_MODE_MASK(at803x_support) = { 0, };\n+\t__ETHTOOL_DECLARE_LINK_MODE_MASK(support) = { 0, };\n+\tstruct phy_device *phydev = upstream;\n+\tphy_interface_t iface;\n+\n+\tphylink_set(at803x_support, 1000baseX_Full);\n+\t/* AT803x only support 1000baseX but SGMII works fine when module runs\n+\t * at 1Gbit.\n+\t */\n+\tphylink_set(at803x_support, 1000baseT_Full);\n+\n+\tsfp_parse_support(phydev->sfp_bus, id, support);\n+\n+\t// Limit to interfaces that both sides support\n+\tlinkmode_and(support, support, at803x_support);\n+\n+\tif (linkmode_empty(support))\n+\t\tgoto unsupported_mode;\n+\n+\tiface = sfp_select_interface(phydev->sfp_bus, support);\n+\n+\tif (iface != PHY_INTERFACE_MODE_SGMII &&\n+\t    iface != PHY_INTERFACE_MODE_1000BASEX)\n+\t\tgoto unsupported_mode;\n+\n+\tdev_info(&phydev->mdio.dev, \"SFP interface %s\", phy_modes(iface));\n+\n+\treturn 0;\n+\n+unsupported_mode:\n+\tdev_info(&phydev->mdio.dev, \"incompatible SFP module inserted;\"\n+\t\t \"Only SGMII at 1Gbit/1000BASEX are supported!\\n\");\n+\treturn -EINVAL;\n+}\n+\n+static const struct sfp_upstream_ops at803x_sfp_ops = {\n+\t.attach = phy_sfp_attach,\n+\t.detach = phy_sfp_detach,\n+\t.module_insert = at803x_sfp_insert,\n+};\n+\n+\n static int at803x_probe(struct phy_device *phydev)\n {\n \tstruct device *dev = &phydev->mdio.dev;\n \tstruct at803x_priv *priv;\n \tint ret;\n \n+\n+\tif (at803x_mode(phydev) == AT803X_MODE_FIBER) {\n+\t\tret = phy_sfp_probe(phydev, &at803x_sfp_ops);\n+\t\tif (ret < 0)\n+\t\t\treturn ret;\n+\t}\n+\n \tpriv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);\n \tif (!priv)\n \t\treturn -ENOMEM;\n@@ -693,6 +767,7 @@ static int at803x_get_features(struct ph\n \tif (err)\n \t\treturn err;\n \n+#if 0\n \tif (phydev->drv->phy_id != ATH8031_PHY_ID)\n \t\treturn 0;\n \n@@ -710,6 +785,7 @@ static int at803x_get_features(struct ph\n \t */\n \tlinkmode_clear_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT,\n \t\t\t   phydev->supported);\n+#endif\n \treturn 0;\n }\n \n@@ -775,6 +851,7 @@ static int at803x_config_init(struct phy\n {\n \tint ret;\n \n+#if 0\n \tif (phydev->drv->phy_id == ATH8031_PHY_ID) {\n \t\t/* Some bootloaders leave the fiber page selected.\n \t\t * Switch to the copper page, as otherwise we read\n@@ -790,6 +867,7 @@ static int at803x_config_init(struct phy\n \t\tif (ret < 0)\n \t\t\treturn ret;\n \t}\n+#endif\n \n \t/* The RX and TX delay default is:\n \t *   after HW reset: RX delay enabled and TX delay disabled\n@@ -925,6 +1003,10 @@ static int at803x_read_status(struct phy\n {\n \tint ss, err, old_link = phydev->link;\n \n+\t/* Handle (Fiber) SGMII to RGMII mode */\n+\tif (at803x_mode(phydev) == AT803X_MODE_FIBER)\n+\t\treturn genphy_c37_read_status(phydev);\n+\n \t/* Update the link, but return if there was an error */\n \terr = genphy_update_link(phydev);\n \tif (err)\n@@ -1025,6 +1107,12 @@ static int at803x_config_aneg(struct phy\n {\n \tint ret;\n \n+\t/* Handle (Fiber) SerDes to RGMII mode */\n+\tif (at803x_mode(phydev) == AT803X_MODE_FIBER) {\n+\t\tpr_warn(\"%s: fiber\\n\", __func__);\n+\t\treturn genphy_c37_config_aneg(phydev);\n+\t}\n+\n \tret = at803x_config_mdix(phydev, phydev->mdix_ctrl);\n \tif (ret < 0)\n \t\treturn ret;\n@@ -1437,6 +1525,7 @@ static struct phy_driver at803x_driver[]\n \t/* Qualcomm Atheros AR8031/AR8033 */\n \tPHY_ID_MATCH_EXACT(ATH8031_PHY_ID),\n \t.name\t\t\t= \"Qualcomm Atheros AR8031/AR8033\",\n+\t.config_aneg\t\t= at803x_config_aneg,\n \t.flags\t\t\t= PHY_POLL_CABLE_TEST,\n \t.probe\t\t\t= at803x_probe,\n \t.remove\t\t\t= at803x_remove,\n"
  },
  {
    "path": "target/linux/ramips/patches-5.15/720-Revert-net-phy-simplify-phy_link_change-arguments.patch",
    "content": "From ffbb1b37a3e1ce1a5c574a6bd4f5aede8bc468ac Mon Sep 17 00:00:00 2001\nFrom: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com>\nDate: Sat, 27 Feb 2021 20:20:07 -0800\nSubject: [PATCH] Revert \"net: phy: simplify phy_link_change arguments\"\n\nThis reverts commit a307593a644443db12888f45eed0dafb5869e2cc.\n\nThis brings back the do_carrier flags used by the (hacky) next patch,\nstill required by target/linux/ramips/files/drivers/net/ethernet/ralink/mdio.c\n---\n drivers/net/phy/phy.c        | 12 ++++++------\n drivers/net/phy/phy_device.c | 12 +++++++-----\n drivers/net/phy/phylink.c    |  3 ++-\n include/linux/phy.h          |  2 +-\n 4 files changed, 16 insertions(+), 13 deletions(-)\n\n--- a/drivers/net/phy/phy.c\n+++ b/drivers/net/phy/phy.c\n@@ -58,13 +58,13 @@ static const char *phy_state_to_str(enum\n \n static void phy_link_up(struct phy_device *phydev)\n {\n-\tphydev->phy_link_change(phydev, true);\n+\tphydev->phy_link_change(phydev, true, true);\n \tphy_led_trigger_change_speed(phydev);\n }\n \n-static void phy_link_down(struct phy_device *phydev)\n+static void phy_link_down(struct phy_device *phydev, bool do_carrier)\n {\n-\tphydev->phy_link_change(phydev, false);\n+\tphydev->phy_link_change(phydev, false, do_carrier);\n \tphy_led_trigger_change_speed(phydev);\n }\n \n@@ -550,7 +550,7 @@ int phy_start_cable_test(struct phy_devi\n \t\tgoto out;\n \n \t/* Mark the carrier down until the test is complete */\n-\tphy_link_down(phydev);\n+\tphy_link_down(phydev, true);\n \n \tnetif_testing_on(dev);\n \terr = phydev->drv->cable_test_start(phydev);\n@@ -621,7 +621,7 @@ int phy_start_cable_test_tdr(struct phy_\n \t\tgoto out;\n \n \t/* Mark the carrier down until the test is complete */\n-\tphy_link_down(phydev);\n+\tphy_link_down(phydev, true);\n \n \tnetif_testing_on(dev);\n \terr = phydev->drv->cable_test_tdr_start(phydev, config);\n@@ -693,7 +693,7 @@ static int phy_check_link_status(struct\n \t\tphy_link_up(phydev);\n \t} else if (!phydev->link && phydev->state != PHY_NOLINK) {\n \t\tphydev->state = PHY_NOLINK;\n-\t\tphy_link_down(phydev);\n+\t\tphy_link_down(phydev, true);\n \t}\n \n \treturn 0;\n@@ -1149,7 +1149,7 @@ void phy_state_machine(struct work_struc\n \tcase PHY_HALTED:\n \t\tif (phydev->link) {\n \t\t\tphydev->link = 0;\n-\t\t\tphy_link_down(phydev);\n+\t\t\tphy_link_down(phydev, true);\n \t\t}\n \t\tdo_suspend = true;\n \t\tbreak;\n--- a/drivers/net/phy/phy_device.c\n+++ b/drivers/net/phy/phy_device.c\n@@ -1000,14 +1000,16 @@ struct phy_device *phy_find_first(struct\n }\n EXPORT_SYMBOL(phy_find_first);\n \n-static void phy_link_change(struct phy_device *phydev, bool up)\n+static void phy_link_change(struct phy_device *phydev, bool up, bool do_carrier)\n {\n \tstruct net_device *netdev = phydev->attached_dev;\n \n-\tif (up)\n-\t\tnetif_carrier_on(netdev);\n-\telse\n-\t\tnetif_carrier_off(netdev);\n+\tif (do_carrier) {\n+\t\tif (up)\n+\t\t\tnetif_carrier_on(netdev);\n+\t\telse\n+\t\t\tnetif_carrier_off(netdev);\n+\t}\n \tphydev->adjust_link(netdev);\n \tif (phydev->mii_ts && phydev->mii_ts->link_state)\n \t\tphydev->mii_ts->link_state(phydev->mii_ts, phydev);\n--- a/drivers/net/phy/phylink.c\n+++ b/drivers/net/phy/phylink.c\n@@ -946,7 +946,8 @@ void phylink_destroy(struct phylink *pl)\n }\n EXPORT_SYMBOL_GPL(phylink_destroy);\n \n-static void phylink_phy_change(struct phy_device *phydev, bool up)\n+static void phylink_phy_change(struct phy_device *phydev, bool up,\n+\t\t\t       bool do_carrier)\n {\n \tstruct phylink *pl = phydev->phylink;\n \tbool tx_pause, rx_pause;\n--- a/include/linux/phy.h\n+++ b/include/linux/phy.h\n@@ -663,7 +663,7 @@ struct phy_device {\n \tu8 mdix;\n \tu8 mdix_ctrl;\n \n-\tvoid (*phy_link_change)(struct phy_device *phydev, bool up);\n+\tvoid (*phy_link_change)(struct phy_device *, bool up, bool do_carrier);\n \tvoid (*adjust_link)(struct net_device *dev);\n \n #if IS_ENABLED(CONFIG_MACSEC)\n"
  },
  {
    "path": "target/linux/ramips/patches-5.15/721-NET-no-auto-carrier-off-support.patch",
    "content": "From 0b6eb1e68290243d439ee330ea8d0b239a5aec69 Mon Sep 17 00:00:00 2001\nFrom: John Crispin <blogic@openwrt.org>\nDate: Sun, 27 Jul 2014 09:38:50 +0100\nSubject: [PATCH 34/53] NET: multi phy support\n\nSigned-off-by: John Crispin <blogic@openwrt.org>\n---\n drivers/net/phy/phy.c |    9 ++++++---\n include/linux/phy.h   |    1 +\n 2 files changed, 7 insertions(+), 3 deletions(-)\n\n--- a/drivers/net/phy/phy.c\n+++ b/drivers/net/phy/phy.c\n@@ -693,7 +693,10 @@ static int phy_check_link_status(struct\n \t\tphy_link_up(phydev);\n \t} else if (!phydev->link && phydev->state != PHY_NOLINK) {\n \t\tphydev->state = PHY_NOLINK;\n-\t\tphy_link_down(phydev, true);\n+\t\tif (!phydev->no_auto_carrier_off)\n+\t\t\tphy_link_down(phydev, true);\n+\t\telse\n+\t\t\tphy_link_down(phydev, false);\n \t}\n \n \treturn 0;\n@@ -1149,7 +1152,10 @@ void phy_state_machine(struct work_struc\n \tcase PHY_HALTED:\n \t\tif (phydev->link) {\n \t\t\tphydev->link = 0;\n-\t\t\tphy_link_down(phydev, true);\n+\t\t\tif (!phydev->no_auto_carrier_off)\n+\t\t\t\tphy_link_down(phydev, true);\n+\t\t\telse\n+\t\t\t\tphy_link_down(phydev, false);\n \t\t}\n \t\tdo_suspend = true;\n \t\tbreak;\n--- a/include/linux/phy.h\n+++ b/include/linux/phy.h\n@@ -582,6 +582,7 @@ struct phy_device {\n \tunsigned downshifted_rate:1;\n \tunsigned is_on_sfp_module:1;\n \tunsigned mac_managed_pm:1;\n+\tunsigned no_auto_carrier_off:1;\n \n \tunsigned autoneg:1;\n \t/* The most recently read link state */\n"
  },
  {
    "path": "target/linux/ramips/patches-5.15/801-DT-Add-documentation-for-gpio-ralink.patch",
    "content": "From d410e5478c622c01fcf31427533df5f433df9146 Mon Sep 17 00:00:00 2001\nFrom: John Crispin <blogic@openwrt.org>\nDate: Sun, 28 Jul 2013 19:45:30 +0200\nSubject: [PATCH 26/53] DT: Add documentation for gpio-ralink\n\nDescribe gpio-ralink binding.\n\nSigned-off-by: John Crispin <blogic@openwrt.org>\nCc: linux-mips@linux-mips.org\nCc: devicetree@vger.kernel.org\nCc: linux-gpio@vger.kernel.org\n---\n .../devicetree/bindings/gpio/gpio-ralink.txt       |   40 ++++++++++++++++++++\n 1 file changed, 40 insertions(+)\n create mode 100644 Documentation/devicetree/bindings/gpio/gpio-ralink.txt\n\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/gpio/gpio-ralink.txt\n@@ -0,0 +1,40 @@\n+Ralink SoC GPIO controller bindings\n+\n+Required properties:\n+- compatible:\n+  - \"ralink,rt2880-gpio\" for Ralink controllers\n+- #gpio-cells : Should be two.\n+  - first cell is the pin number\n+  - second cell is used to specify optional parameters (unused)\n+- gpio-controller : Marks the device node as a GPIO controller\n+- reg : Physical base address and length of the controller's registers\n+- interrupt-parent: phandle to the INTC device node\n+- interrupts : Specify the INTC interrupt number\n+- ngpios : Specify the number of GPIOs\n+- ralink,register-map : The register layout depends on the GPIO bank and actual\n+\t\tSoC type. Register offsets need to be in this order.\n+\t\t[ INT, EDGE, RENA, FENA, DATA, DIR, POL, SET, RESET, TOGGLE ]\n+\n+Optional properties:\n+- ralink,gpio-base : Specify the GPIO chips base number\n+\n+Example:\n+\n+\tgpio0: gpio@600 {\n+\t\tcompatible = \"ralink,rt5350-gpio\", \"ralink,rt2880-gpio\";\n+\n+\t\t#gpio-cells = <2>;\n+\t\tgpio-controller;\n+\n+\t\treg = <0x600 0x34>;\n+\n+\t\tinterrupt-parent = <&intc>;\n+\t\tinterrupts = <6>;\n+\n+\t\tngpios = <24>;\n+\t\tralink,gpio-base = <0>;\n+\t\tralink,register-map = [ 00 04 08 0c\n+\t\t\t\t20 24 28 2c\n+\t\t\t\t30 34 ];\n+\n+\t};\n"
  },
  {
    "path": "target/linux/ramips/patches-5.15/802-GPIO-MIPS-ralink-add-gpio-driver-for-ralink-SoC.patch",
    "content": "From 69fdd2c4f937796b934e89c33acde9d082e27bfd Mon Sep 17 00:00:00 2001\nFrom: John Crispin <blogic@openwrt.org>\nDate: Mon, 4 Aug 2014 20:36:29 +0200\nSubject: [PATCH 27/53] GPIO: MIPS: ralink: add gpio driver for ralink SoC\n\nAdd gpio driver for Ralink SoC. This driver makes the gpio core on\nRT2880, RT305x, rt3352, rt3662, rt3883, rt5350 and mt7620 work.\n\nSigned-off-by: John Crispin <blogic@openwrt.org>\nCc: linux-mips@linux-mips.org\nCc: linux-gpio@vger.kernel.org\n---\n arch/mips/include/asm/mach-ralink/gpio.h |   24 ++\n drivers/gpio/Kconfig                     |    6 +\n drivers/gpio/Makefile                    |    1 +\n drivers/gpio/gpio-ralink.c               |  355 ++++++++++++++++++++++++++++++\n 4 files changed, 386 insertions(+)\n create mode 100644 arch/mips/include/asm/mach-ralink/gpio.h\n create mode 100644 drivers/gpio/gpio-ralink.c\n\n--- /dev/null\n+++ b/arch/mips/include/asm/mach-ralink/gpio.h\n@@ -0,0 +1,24 @@\n+/*\n+ *  Ralink SoC GPIO API support\n+ *\n+ *  Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>\n+ *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>\n+ *\n+ *  This program is free software; you can redistribute it and/or modify it\n+ *  under the terms of the GNU General Public License version 2 as published\n+ *  by the Free Software Foundation.\n+ *\n+ */\n+\n+#ifndef __ASM_MACH_RALINK_GPIO_H\n+#define __ASM_MACH_RALINK_GPIO_H\n+\n+#define ARCH_NR_GPIOS\t128\n+#include <asm-generic/gpio.h>\n+\n+#define gpio_get_value\t__gpio_get_value\n+#define gpio_set_value\t__gpio_set_value\n+#define gpio_cansleep\t__gpio_cansleep\n+#define gpio_to_irq\t__gpio_to_irq\n+\n+#endif /* __ASM_MACH_RALINK_GPIO_H */\n--- a/drivers/gpio/Kconfig\n+++ b/drivers/gpio/Kconfig\n@@ -569,6 +569,12 @@ config GPIO_SNPS_CREG\n \t  where only several fields in register belong to GPIO lines and\n \t  each GPIO line owns a field with different length and on/off value.\n \n+config GPIO_RALINK\n+\tbool \"Ralink GPIO Support\"\n+\tdepends on RALINK\n+\thelp\n+\t  Say yes here to support the Ralink SoC GPIO device\n+\n config GPIO_SPEAR_SPICS\n \tbool \"ST SPEAr13xx SPI Chip Select as GPIO support\"\n \tdepends on PLAT_SPEAR\n--- a/drivers/gpio/Makefile\n+++ b/drivers/gpio/Makefile\n@@ -121,6 +121,7 @@ obj-$(CONFIG_GPIO_PISOSR)\t\t+= gpio-pisos\n obj-$(CONFIG_GPIO_PL061)\t\t+= gpio-pl061.o\n obj-$(CONFIG_GPIO_PMIC_EIC_SPRD)\t+= gpio-pmic-eic-sprd.o\n obj-$(CONFIG_GPIO_PXA)\t\t\t+= gpio-pxa.o\n+obj-$(CONFIG_GPIO_RALINK)\t\t+= gpio-ralink.o\n obj-$(CONFIG_GPIO_RASPBERRYPI_EXP)\t+= gpio-raspberrypi-exp.o\n obj-$(CONFIG_GPIO_RC5T583)\t\t+= gpio-rc5t583.o\n obj-$(CONFIG_GPIO_RCAR)\t\t\t+= gpio-rcar.o\n--- /dev/null\n+++ b/drivers/gpio/gpio-ralink.c\n@@ -0,0 +1,341 @@\n+/*\n+ * This program is free software; you can redistribute it and/or modify it\n+ * under the terms of the GNU General Public License version 2 as published\n+ * by the Free Software Foundation.\n+ *\n+ * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>\n+ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>\n+ */\n+\n+#include <linux/module.h>\n+#include <linux/io.h>\n+#include <linux/gpio.h>\n+#include <linux/spinlock.h>\n+#include <linux/platform_device.h>\n+#include <linux/of_irq.h>\n+#include <linux/irqdomain.h>\n+#include <linux/interrupt.h>\n+\n+enum ralink_gpio_reg {\n+\tGPIO_REG_INT = 0,\n+\tGPIO_REG_EDGE,\n+\tGPIO_REG_RENA,\n+\tGPIO_REG_FENA,\n+\tGPIO_REG_DATA,\n+\tGPIO_REG_DIR,\n+\tGPIO_REG_POL,\n+\tGPIO_REG_SET,\n+\tGPIO_REG_RESET,\n+\tGPIO_REG_TOGGLE,\n+\tGPIO_REG_MAX\n+};\n+\n+struct ralink_gpio_chip {\n+\tstruct gpio_chip chip;\n+\tu8 regs[GPIO_REG_MAX];\n+\n+\tspinlock_t lock;\n+\tvoid __iomem *membase;\n+\tstruct irq_domain *domain;\n+\tint irq;\n+\n+\tu32 rising;\n+\tu32 falling;\n+};\n+\n+#define MAP_MAX\t4\n+static struct irq_domain *irq_map[MAP_MAX];\n+static int irq_map_count;\n+static atomic_t irq_refcount = ATOMIC_INIT(0);\n+\n+static inline struct ralink_gpio_chip *to_ralink_gpio(struct gpio_chip *chip)\n+{\n+\tstruct ralink_gpio_chip *rg;\n+\n+\trg = container_of(chip, struct ralink_gpio_chip, chip);\n+\n+\treturn rg;\n+}\n+\n+static inline void rt_gpio_w32(struct ralink_gpio_chip *rg, u8 reg, u32 val)\n+{\n+\tiowrite32(val, rg->membase + rg->regs[reg]);\n+}\n+\n+static inline u32 rt_gpio_r32(struct ralink_gpio_chip *rg, u8 reg)\n+{\n+\treturn ioread32(rg->membase + rg->regs[reg]);\n+}\n+\n+static void ralink_gpio_set(struct gpio_chip *chip, unsigned offset, int value)\n+{\n+\tstruct ralink_gpio_chip *rg = to_ralink_gpio(chip);\n+\n+\trt_gpio_w32(rg, (value) ? GPIO_REG_SET : GPIO_REG_RESET, BIT(offset));\n+}\n+\n+static int ralink_gpio_get(struct gpio_chip *chip, unsigned offset)\n+{\n+\tstruct ralink_gpio_chip *rg = to_ralink_gpio(chip);\n+\n+\treturn !!(rt_gpio_r32(rg, GPIO_REG_DATA) & BIT(offset));\n+}\n+\n+static int ralink_gpio_direction_input(struct gpio_chip *chip, unsigned offset)\n+{\n+\tstruct ralink_gpio_chip *rg = to_ralink_gpio(chip);\n+\tunsigned long flags;\n+\tu32 t;\n+\n+\tspin_lock_irqsave(&rg->lock, flags);\n+\tt = rt_gpio_r32(rg, GPIO_REG_DIR);\n+\tt &= ~BIT(offset);\n+\trt_gpio_w32(rg, GPIO_REG_DIR, t);\n+\tspin_unlock_irqrestore(&rg->lock, flags);\n+\n+\treturn 0;\n+}\n+\n+static int ralink_gpio_direction_output(struct gpio_chip *chip,\n+\t\t\t\t\tunsigned offset, int value)\n+{\n+\tstruct ralink_gpio_chip *rg = to_ralink_gpio(chip);\n+\tunsigned long flags;\n+\tu32 t;\n+\n+\tspin_lock_irqsave(&rg->lock, flags);\n+\tralink_gpio_set(chip, offset, value);\n+\tt = rt_gpio_r32(rg, GPIO_REG_DIR);\n+\tt |= BIT(offset);\n+\trt_gpio_w32(rg, GPIO_REG_DIR, t);\n+\tspin_unlock_irqrestore(&rg->lock, flags);\n+\n+\treturn 0;\n+}\n+\n+static int ralink_gpio_to_irq(struct gpio_chip *chip, unsigned pin)\n+{\n+\tstruct ralink_gpio_chip *rg = to_ralink_gpio(chip);\n+\n+\tif (rg->irq < 1)\n+\t\treturn -1;\n+\n+\treturn irq_create_mapping(rg->domain, pin);\n+}\n+\n+static void ralink_gpio_irq_handler(struct irq_desc *desc)\n+{\n+\tint i;\n+\n+\tfor (i = 0; i < irq_map_count; i++) {\n+\t\tstruct irq_domain *domain = irq_map[i];\n+\t\tstruct ralink_gpio_chip *rg;\n+\t\tunsigned long pending;\n+\t\tint bit;\n+\n+\t\trg = (struct ralink_gpio_chip *) domain->host_data;\n+\t\tpending = rt_gpio_r32(rg, GPIO_REG_INT);\n+\n+\t\tfor_each_set_bit(bit, &pending, rg->chip.ngpio) {\n+\t\t\tu32 map = irq_find_mapping(domain, bit);\n+\t\t\tgeneric_handle_irq(map);\n+\t\t\trt_gpio_w32(rg, GPIO_REG_INT, BIT(bit));\n+\t\t}\n+\t}\n+}\n+\n+static void ralink_gpio_irq_unmask(struct irq_data *d)\n+{\n+\tstruct ralink_gpio_chip *rg;\n+\tunsigned long flags;\n+\tu32 rise, fall;\n+\n+\trg = (struct ralink_gpio_chip *) d->domain->host_data;\n+\trise = rt_gpio_r32(rg, GPIO_REG_RENA);\n+\tfall = rt_gpio_r32(rg, GPIO_REG_FENA);\n+\n+\tspin_lock_irqsave(&rg->lock, flags);\n+\trt_gpio_w32(rg, GPIO_REG_RENA, rise | (BIT(d->hwirq) & rg->rising));\n+\trt_gpio_w32(rg, GPIO_REG_FENA, fall | (BIT(d->hwirq) & rg->falling));\n+\tspin_unlock_irqrestore(&rg->lock, flags);\n+}\n+\n+static void ralink_gpio_irq_mask(struct irq_data *d)\n+{\n+\tstruct ralink_gpio_chip *rg;\n+\tunsigned long flags;\n+\tu32 rise, fall;\n+\n+\trg = (struct ralink_gpio_chip *) d->domain->host_data;\n+\trise = rt_gpio_r32(rg, GPIO_REG_RENA);\n+\tfall = rt_gpio_r32(rg, GPIO_REG_FENA);\n+\n+\tspin_lock_irqsave(&rg->lock, flags);\n+\trt_gpio_w32(rg, GPIO_REG_FENA, fall & ~BIT(d->hwirq));\n+\trt_gpio_w32(rg, GPIO_REG_RENA, rise & ~BIT(d->hwirq));\n+\tspin_unlock_irqrestore(&rg->lock, flags);\n+}\n+\n+static int ralink_gpio_irq_type(struct irq_data *d, unsigned int type)\n+{\n+\tstruct ralink_gpio_chip *rg;\n+\tu32 mask = BIT(d->hwirq);\n+\n+\trg = (struct ralink_gpio_chip *) d->domain->host_data;\n+\n+\tif (type == IRQ_TYPE_PROBE) {\n+\t\tif ((rg->rising | rg->falling) & mask)\n+\t\t\treturn 0;\n+\n+\t\ttype = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;\n+\t}\n+\n+\tif (type & IRQ_TYPE_EDGE_RISING)\n+\t\trg->rising |= mask;\n+\telse\n+\t\trg->rising &= ~mask;\n+\n+\tif (type & IRQ_TYPE_EDGE_FALLING)\n+\t\trg->falling |= mask;\n+\telse\n+\t\trg->falling &= ~mask;\n+\n+\treturn 0;\n+}\n+\n+static struct irq_chip ralink_gpio_irq_chip = {\n+\t.name\t\t= \"GPIO\",\n+\t.irq_unmask\t= ralink_gpio_irq_unmask,\n+\t.irq_mask\t= ralink_gpio_irq_mask,\n+\t.irq_mask_ack\t= ralink_gpio_irq_mask,\n+\t.irq_set_type\t= ralink_gpio_irq_type,\n+};\n+\n+static int gpio_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)\n+{\n+\tirq_set_chip_and_handler(irq, &ralink_gpio_irq_chip, handle_level_irq);\n+\tirq_set_handler_data(irq, d);\n+\n+\treturn 0;\n+}\n+\n+static const struct irq_domain_ops irq_domain_ops = {\n+\t.xlate = irq_domain_xlate_onecell,\n+\t.map = gpio_map,\n+};\n+\n+static void ralink_gpio_irq_init(struct device_node *np,\n+\t\t\t\t struct ralink_gpio_chip *rg)\n+{\n+\tif (irq_map_count >= MAP_MAX)\n+\t\treturn;\n+\n+\trg->irq = irq_of_parse_and_map(np, 0);\n+\tif (!rg->irq)\n+\t\treturn;\n+\n+\trg->domain = irq_domain_add_linear(np, rg->chip.ngpio,\n+\t\t\t\t\t   &irq_domain_ops, rg);\n+\tif (!rg->domain) {\n+\t\tdev_err(rg->chip.parent, \"irq_domain_add_linear failed\\n\");\n+\t\treturn;\n+\t}\n+\n+\tirq_map[irq_map_count++] = rg->domain;\n+\n+\trt_gpio_w32(rg, GPIO_REG_RENA, 0x0);\n+\trt_gpio_w32(rg, GPIO_REG_FENA, 0x0);\n+\n+\tif (!atomic_read(&irq_refcount))\n+\t\tirq_set_chained_handler(rg->irq, ralink_gpio_irq_handler);\n+\tatomic_inc(&irq_refcount);\n+\n+\tdev_info(rg->chip.parent, \"registering %d irq handlers\\n\", rg->chip.ngpio);\n+}\n+\n+static int ralink_gpio_probe(struct platform_device *pdev)\n+{\n+\tstruct device_node *np = pdev->dev.of_node;\n+\tstruct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);\n+\tstruct ralink_gpio_chip *rg;\n+\tconst __be32 *ngpio, *gpiobase;\n+\n+\tif (!res) {\n+\t\tdev_err(&pdev->dev, \"failed to find resource\\n\");\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\trg = devm_kzalloc(&pdev->dev,\n+\t\t\tsizeof(struct ralink_gpio_chip), GFP_KERNEL);\n+\tif (!rg)\n+\t\treturn -ENOMEM;\n+\n+\trg->membase = devm_ioremap_resource(&pdev->dev, res);\n+\tif (!rg->membase) {\n+\t\tdev_err(&pdev->dev, \"cannot remap I/O memory region\\n\");\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\tif (of_property_read_u8_array(np, \"ralink,register-map\",\n+\t\t\trg->regs, GPIO_REG_MAX)) {\n+\t\tdev_err(&pdev->dev, \"failed to read register definition\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tngpio = of_get_property(np, \"ngpios\", NULL);\n+\tif (!ngpio) {\n+\t\tdev_err(&pdev->dev, \"failed to read number of pins\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tgpiobase = of_get_property(np, \"ralink,gpio-base\", NULL);\n+\tif (gpiobase)\n+\t\trg->chip.base = be32_to_cpu(*gpiobase);\n+\telse\n+\t\trg->chip.base = -1;\n+\n+\tspin_lock_init(&rg->lock);\n+\n+\trg->chip.parent = &pdev->dev;\n+\trg->chip.label = dev_name(&pdev->dev);\n+\trg->chip.of_node = np;\n+\trg->chip.ngpio = be32_to_cpu(*ngpio);\n+\trg->chip.direction_input = ralink_gpio_direction_input;\n+\trg->chip.direction_output = ralink_gpio_direction_output;\n+\trg->chip.get = ralink_gpio_get;\n+\trg->chip.set = ralink_gpio_set;\n+\trg->chip.request = gpiochip_generic_request;\n+\trg->chip.to_irq = ralink_gpio_to_irq;\n+\trg->chip.free = gpiochip_generic_free;\n+\n+\t/* set polarity to low for all lines */\n+\trt_gpio_w32(rg, GPIO_REG_POL, 0);\n+\n+\tdev_info(&pdev->dev, \"registering %d gpios\\n\", rg->chip.ngpio);\n+\n+\tralink_gpio_irq_init(np, rg);\n+\n+\treturn gpiochip_add(&rg->chip);\n+}\n+\n+static const struct of_device_id ralink_gpio_match[] = {\n+\t{ .compatible = \"ralink,rt2880-gpio\" },\n+\t{},\n+};\n+MODULE_DEVICE_TABLE(of, ralink_gpio_match);\n+\n+static struct platform_driver ralink_gpio_driver = {\n+\t.probe = ralink_gpio_probe,\n+\t.driver = {\n+\t\t.name = \"rt2880_gpio\",\n+\t\t.owner = THIS_MODULE,\n+\t\t.of_match_table = ralink_gpio_match,\n+\t},\n+};\n+\n+static int __init ralink_gpio_init(void)\n+{\n+\treturn platform_driver_register(&ralink_gpio_driver);\n+}\n+\n+subsys_initcall(ralink_gpio_init);\n"
  },
  {
    "path": "target/linux/ramips/patches-5.15/803-gpio-ralink-Add-support-for-GPIO-as-interrupt-contro.patch",
    "content": "From 57fa7f2f4ef6f78ce1d30509c0d111aa3791b524 Mon Sep 17 00:00:00 2001\nFrom: Daniel Santos <daniel.santos@pobox.com>\nDate: Sun, 4 Nov 2018 20:24:32 -0600\nSubject: gpio-ralink: Add support for GPIO as interrupt-controller\n\nSigned-off-by: Daniel Santos <daniel.santos@pobox.com>\n---\n Documentation/devicetree/bindings/gpio/gpio-ralink.txt | 6 ++++++\n drivers/gpio/gpio-ralink.c                             | 2 +-\n 2 files changed, 7 insertions(+), 1 deletion(-)\n\n--- a/Documentation/devicetree/bindings/gpio/gpio-ralink.txt\n+++ b/Documentation/devicetree/bindings/gpio/gpio-ralink.txt\n@@ -17,6 +17,9 @@ Required properties:\n \n Optional properties:\n - ralink,gpio-base : Specify the GPIO chips base number\n+- interrupt-controller : marks this as an interrupt controller\n+- #interrupt-cells : a standard two-cell interrupt flag, see\n+  interrupt-controller/interrupts.txt\n \n Example:\n \n@@ -28,6 +31,9 @@ Example:\n \n \t\treg = <0x600 0x34>;\n \n+\t\tinterrupt-controller;\n+\t\t#interrupt-cells = <2>;\n+\n \t\tinterrupt-parent = <&intc>;\n \t\tinterrupts = <6>;\n \n--- a/drivers/gpio/gpio-ralink.c\n+++ b/drivers/gpio/gpio-ralink.c\n@@ -220,7 +220,7 @@ static int gpio_map(struct irq_domain *d\n }\n \n static const struct irq_domain_ops irq_domain_ops = {\n-\t.xlate = irq_domain_xlate_onecell,\n+\t.xlate = irq_domain_xlate_twocell,\n \t.map = gpio_map,\n };\n \n"
  },
  {
    "path": "target/linux/ramips/patches-5.15/805-pinctrl-AW9523.patch",
    "content": "From: AngeloGioacchino Del Regno\n        <angelogioacchino.delregno@somainline.org>\nTo: linus.walleij@linaro.org\nCc: linux-kernel@vger.kernel.org, konrad.dybcio@somainline.org,\n        marijn.suijten@somainline.org, martin.botka@somainline.org,\n        phone-devel@vger.kernel.org, linux-gpio@vger.kernel.org,\n        devicetree@vger.kernel.org, robh+dt@kernel.org,\n        AngeloGioacchino Del Regno\n        <angelogioacchino.delregno@somainline.org>\nSubject: [PATCH v5 1/2] pinctrl: Add driver for Awinic AW9523/B I2C GPIO\n Expander\nDate: Mon, 25 Jan 2021 19:22:18 +0100\n\nThe Awinic AW9523(B) is a multi-function I2C gpio expander in a\nTQFN-24L package, featuring PWM (max 37mA per pin, or total max\npower 3.2Watts) for LED driving capability.\n\nIt has two ports with 8 pins per port (for a total of 16 pins),\nconfigurable as either PWM with 1/256 stepping or GPIO input/output,\n1.8V logic input; each GPIO can be configured as input or output\nindependently from each other.\n\nThis IC also has an internal interrupt controller, which is capable\nof generating an interrupt for each GPIO, depending on the\nconfiguration, and will raise an interrupt on the INTN pin to\nadvertise this to an external interrupt controller.\n\nSigned-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>\n---\n drivers/pinctrl/Kconfig          |   17 +\n drivers/pinctrl/Makefile         |    1 +\n drivers/pinctrl/pinctrl-aw9523.c | 1122 ++++++++++++++++++++++++++++++\n 3 files changed, 1140 insertions(+)\n create mode 100644 drivers/pinctrl/pinctrl-aw9523.c\n\n--- a/drivers/pinctrl/Kconfig\n+++ b/drivers/pinctrl/Kconfig\n@@ -111,6 +111,24 @@ config PINCTRL_AMD\n \t  Requires ACPI/FDT device enumeration code to set up a platform\n \t  device.\n \n+config PINCTRL_AW9523\n+\tbool \"Awinic AW9523/AW9523B I2C GPIO expander pinctrl driver\"\n+\tdepends on OF && I2C\n+\tselect PINMUX\n+\tselect PINCONF\n+\tselect GENERIC_PINCONF\n+\tselect GPIOLIB\n+\tselect GPIOLIB_IRQCHIP\n+\tselect REGMAP\n+\tselect REGMAP_I2C\n+\thelp\n+\t  The Awinic AW9523/AW9523B is a multi-function I2C GPIO\n+\t  expander with PWM functionality. This driver bundles a\n+\t  pinctrl driver to select the function muxing and a GPIO\n+\t  driver to handle GPIO, when the GPIO function is selected.\n+\n+\t  Say yes to enable pinctrl and GPIO support for the AW9523(B).\n+\n config PINCTRL_BM1880\n \tbool \"Bitmain BM1880 Pinctrl driver\"\n \tdepends on OF && (ARCH_BITMAIN || COMPILE_TEST)\n--- a/drivers/pinctrl/Makefile\n+++ b/drivers/pinctrl/Makefile\n@@ -14,6 +14,7 @@ obj-$(CONFIG_PINCTRL_AXP209)\t+= pinctrl-\n obj-$(CONFIG_PINCTRL_AT91)\t+= pinctrl-at91.o\n obj-$(CONFIG_PINCTRL_AT91PIO4)\t+= pinctrl-at91-pio4.o\n obj-$(CONFIG_PINCTRL_AMD)\t+= pinctrl-amd.o\n+obj-$(CONFIG_PINCTRL_AW9523)\t+= pinctrl-aw9523.o\n obj-$(CONFIG_PINCTRL_BM1880)\t+= pinctrl-bm1880.o\n obj-$(CONFIG_PINCTRL_DA850_PUPD) += pinctrl-da850-pupd.o\n obj-$(CONFIG_PINCTRL_DA9062)\t+= pinctrl-da9062.o\n"
  },
  {
    "path": "target/linux/ramips/patches-5.15/810-uvc-add-iPassion-iP2970-support.patch",
    "content": "From 975e76214cd2516eb6cfff4c3eec581872645e88 Mon Sep 17 00:00:00 2001\nFrom: John Crispin <blogic@openwrt.org>\nDate: Thu, 19 Sep 2013 01:50:59 +0200\nSubject: [PATCH 31/53] uvc: add iPassion iP2970 support\n\nSigned-off-by: John Crispin <blogic@openwrt.org>\n---\n drivers/media/usb/uvc/uvc_driver.c |   12 +++\n drivers/media/usb/uvc/uvc_status.c |    2 +\n drivers/media/usb/uvc/uvc_video.c  |  147 ++++++++++++++++++++++++++++++++++++\n drivers/media/usb/uvc/uvcvideo.h   |    5 +-\n 4 files changed, 165 insertions(+), 1 deletion(-)\n\n--- a/drivers/media/usb/uvc/uvc_driver.c\n+++ b/drivers/media/usb/uvc/uvc_driver.c\n@@ -3164,6 +3164,18 @@ static const struct usb_device_id uvc_id\n \t  .bInterfaceSubClass\t= 1,\n \t  .bInterfaceProtocol\t= 0,\n \t  .driver_info\t\t= UVC_INFO_META(V4L2_META_FMT_D4XX) },\n+\t/* iPassion iP2970 */\n+\t{ .match_flags          = USB_DEVICE_ID_MATCH_DEVICE\n+\t\t\t\t| USB_DEVICE_ID_MATCH_INT_INFO,\n+\t .idVendor\t\t= 0x1B3B,\n+\t .idProduct\t\t= 0x2970,\n+\t .bInterfaceClass\t= USB_CLASS_VIDEO,\n+\t .bInterfaceSubClass\t= 1,\n+\t .bInterfaceProtocol\t= 0,\n+\t .driver_info\t\t= UVC_QUIRK_PROBE_MINMAX\n+\t\t\t\t| UVC_QUIRK_STREAM_NO_FID\n+\t\t\t\t| UVC_QUIRK_MOTION\n+\t\t\t\t| UVC_QUIRK_SINGLE_ISO },\n \t/* Generic USB Video Class */\n \t{ USB_INTERFACE_INFO(USB_CLASS_VIDEO, 1, UVC_PC_PROTOCOL_UNDEFINED) },\n \t{ USB_INTERFACE_INFO(USB_CLASS_VIDEO, 1, UVC_PC_PROTOCOL_15) },\n--- a/drivers/media/usb/uvc/uvc_status.c\n+++ b/drivers/media/usb/uvc/uvc_status.c\n@@ -223,6 +223,7 @@ static void uvc_status_complete(struct u\n \t\t\tif (uvc_event_control(urb, status, len))\n \t\t\t\t/* The URB will be resubmitted in work context. */\n \t\t\t\treturn;\n+\t\t\tdev->motion = 1;\n \t\t\tbreak;\n \t\t}\n \n@@ -271,6 +272,7 @@ int uvc_status_init(struct uvc_device *d\n \t}\n \n \tpipe = usb_rcvintpipe(dev->udev, ep->desc.bEndpointAddress);\n+\tdev->motion = 0;\n \n \t/* For high-speed interrupt endpoints, the bInterval value is used as\n \t * an exponent of two. Some developers forgot about it.\n--- a/drivers/media/usb/uvc/uvc_video.c\n+++ b/drivers/media/usb/uvc/uvc_video.c\n@@ -19,6 +19,11 @@\n #include <linux/wait.h>\n #include <linux/atomic.h>\n #include <asm/unaligned.h>\n+#include <linux/skbuff.h>\n+#include <linux/kobject.h>\n+#include <linux/netlink.h>\n+#include <linux/kobject.h>\n+#include <linux/workqueue.h>\n \n #include <media/v4l2-common.h>\n \n@@ -1214,9 +1219,149 @@ static void uvc_video_decode_data(struct\n \tuvc_urb->async_operations++;\n }\n \n+struct bh_priv {\n+\tunsigned long\tseen;\n+};\n+\n+struct bh_event {\n+\tconst char\t\t*name;\n+\tstruct sk_buff\t\t*skb;\n+\tstruct work_struct\twork;\n+};\n+\n+#define BH_ERR(fmt, args...) printk(KERN_ERR \"%s: \" fmt, \"webcam\", ##args )\n+#define BH_DBG(fmt, args...) do {} while (0)\n+#define BH_SKB_SIZE     2048\n+\n+extern u64 uevent_next_seqnum(void);\n+static int seen = 0;\n+\n+static int bh_event_add_var(struct bh_event *event, int argv,\n+\t\tconst char *format, ...)\n+{\n+\tstatic char buf[128];\n+\tchar *s;\n+\tva_list args;\n+\tint len;\n+\n+\tif (argv)\n+\t\treturn 0;\n+\n+\tva_start(args, format);\n+\tlen = vsnprintf(buf, sizeof(buf), format, args);\n+\tva_end(args);\n+\n+\tif (len >= sizeof(buf)) {\n+\t\tBH_ERR(\"buffer size too small\\n\");\n+\t\tWARN_ON(1);\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\ts = skb_put(event->skb, len + 1);\n+\tstrcpy(s, buf);\n+\n+\tBH_DBG(\"added variable '%s'\\n\", s);\n+\n+\treturn 0;\n+}\n+\n+static int motion_hotplug_fill_event(struct bh_event *event)\n+{\n+\tint s = jiffies;\n+\tint ret;\n+\n+\tif (!seen)\n+\t\tseen = jiffies;\n+\n+\tret = bh_event_add_var(event, 0, \"HOME=%s\", \"/\");\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = bh_event_add_var(event, 0, \"PATH=%s\",\n+\t\t\"/sbin:/bin:/usr/sbin:/usr/bin\");\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = bh_event_add_var(event, 0, \"SUBSYSTEM=usb\");\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = bh_event_add_var(event, 0, \"ACTION=motion\");\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = bh_event_add_var(event, 0, \"SEEN=%d\", s - seen);\n+\tif (ret)\n+\t\treturn ret;\n+\tseen = s;\n+\n+\tret = bh_event_add_var(event, 0, \"SEQNUM=%llu\", uevent_next_seqnum());\n+\n+\treturn ret;\n+}\n+\n+static void motion_hotplug_work(struct work_struct *work)\n+{\n+\tstruct bh_event *event = container_of(work, struct bh_event, work);\n+\tint ret = 0;\n+\n+\tevent->skb = alloc_skb(BH_SKB_SIZE, GFP_KERNEL);\n+\tif (!event->skb)\n+\t\tgoto out_free_event;\n+\n+\tret = bh_event_add_var(event, 0, \"%s@\", \"add\");\n+\tif (ret)\n+\t\tgoto out_free_skb;\n+\n+\tret = motion_hotplug_fill_event(event);\n+\tif (ret)\n+\t\tgoto out_free_skb;\n+\n+\tNETLINK_CB(event->skb).dst_group = 1;\n+\tbroadcast_uevent(event->skb, 0, 1, GFP_KERNEL);\n+\n+out_free_skb:\n+\tif (ret) {\n+\t\tBH_ERR(\"work error %d\\n\", ret);\n+\t\tkfree_skb(event->skb);\n+\t}\n+out_free_event:\n+\tkfree(event);\n+}\n+\n+static int motion_hotplug_create_event(void)\n+{\n+\tstruct bh_event *event;\n+\n+\tevent = kzalloc(sizeof(*event), GFP_KERNEL);\n+\tif (!event)\n+\t\treturn -ENOMEM;\n+\n+\tevent->name = \"motion\";\n+\n+\tINIT_WORK(&event->work, (void *)(void *)motion_hotplug_work);\n+\tschedule_work(&event->work);\n+\n+\treturn 0;\n+}\n+\n+#define MOTION_FLAG_OFFSET\t4\n static void uvc_video_decode_end(struct uvc_streaming *stream,\n \t\tstruct uvc_buffer *buf, const u8 *data, int len)\n {\n+\tif ((stream->dev->quirks & UVC_QUIRK_MOTION) &&\n+\t\t\t(data[len - 2] == 0xff) && (data[len - 1] == 0xd9)) {\n+\t\tu8 *mem;\n+\t\tbuf->state = UVC_BUF_STATE_READY;\n+\t\tmem = (u8 *) (buf->mem + MOTION_FLAG_OFFSET);\n+\t\tif ( stream->dev->motion ) {\n+\t\t\tstream->dev->motion = 0;\n+\t\t\tmotion_hotplug_create_event();\n+\t\t} else {\n+\t\t\t*mem &= 0x7f;\n+\t\t}\n+\t}\n+\n \t/* Mark the buffer as done if the EOF marker is set. */\n \tif (data[1] & UVC_STREAM_EOF && buf->bytesused != 0) {\n \t\tuvc_dbg(stream->dev, FRAME, \"Frame complete (EOF found)\\n\");\n@@ -1799,6 +1944,8 @@ static int uvc_init_video_isoc(struct uv\n \tif (npackets == 0)\n \t\treturn -ENOMEM;\n \n+\tif (stream->dev->quirks & UVC_QUIRK_SINGLE_ISO)\n+\t\tnpackets = 1;\n \tsize = npackets * psize;\n \n \tfor_each_uvc_urb(uvc_urb, stream) {\n--- a/drivers/media/usb/uvc/uvcvideo.h\n+++ b/drivers/media/usb/uvc/uvcvideo.h\n@@ -209,7 +209,9 @@\n #define UVC_QUIRK_RESTORE_CTRLS_ON_INIT\t0x00000400\n #define UVC_QUIRK_FORCE_Y8\t\t0x00000800\n #define UVC_QUIRK_FORCE_BPP\t\t0x00001000\n-\n+#define UVC_QUIRK_MOTION\t\t0x00001000\n+#define UVC_QUIRK_SINGLE_ISO\t\t0x00002000\n+ \n /* Format flags */\n #define UVC_FMT_FLAG_COMPRESSED\t\t0x00000001\n #define UVC_FMT_FLAG_STREAM\t\t0x00000002\n@@ -700,6 +702,7 @@ struct uvc_device {\n \tu8 *status;\n \tstruct input_dev *input;\n \tchar input_phys[64];\n+\tint motion;\n \n \tstruct uvc_ctrl_work {\n \t\tstruct work_struct work;\n"
  },
  {
    "path": "target/linux/ramips/patches-5.15/820-DT-Add-documentation-for-spi-rt2880.patch",
    "content": "From da6015e7f19d749f135f7ac55c4ec47b06faa868 Mon Sep 17 00:00:00 2001\nFrom: John Crispin <blogic@openwrt.org>\nDate: Fri, 9 Aug 2013 20:12:59 +0200\nSubject: [PATCH 41/53] DT: Add documentation for spi-rt2880\n\nDescribe the SPI master found on the MIPS based Ralink RT2880 SoC.\n\nSigned-off-by: John Crispin <blogic@openwrt.org>\n---\n .../devicetree/bindings/spi/spi-rt2880.txt         |   28 ++++++++++++++++++++\n 1 file changed, 28 insertions(+)\n create mode 100644 Documentation/devicetree/bindings/spi/spi-rt2880.txt\n\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/spi/spi-rt2880.txt\n@@ -0,0 +1,28 @@\n+Ralink SoC RT2880 SPI master controller.\n+\n+This SPI controller is found on most wireless SoCs made by ralink.\n+\n+Required properties:\n+- compatible : \"ralink,rt2880-spi\"\n+- reg : The register base for the controller.\n+- #address-cells : <1>, as required by generic SPI binding.\n+- #size-cells : <0>, also as required by generic SPI binding.\n+\n+Child nodes as per the generic SPI binding.\n+\n+Example:\n+\n+\tspi@b00 {\n+\t\tcompatible = \"ralink,rt2880-spi\";\n+\t\treg = <0xb00 0x100>;\n+\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\n+\t\tm25p80@0 {\n+\t\t\tcompatible = \"m25p80\";\n+\t\t\treg = <0>;\n+\t\t\tspi-max-frequency = <10000000>;\n+\t\t};\n+\t};\n+\n"
  },
  {
    "path": "target/linux/ramips/patches-5.15/821-SPI-ralink-add-Ralink-SoC-spi-driver.patch",
    "content": "From 683af4ebb91a1600df1946ac4769d916b8a1be65 Mon Sep 17 00:00:00 2001\nFrom: John Crispin <blogic@openwrt.org>\nDate: Sun, 27 Jul 2014 11:15:12 +0100\nSubject: [PATCH 42/53] SPI: ralink: add Ralink SoC spi driver\n\nAdd the driver needed to make SPI work on Ralink SoC.\n\nSigned-off-by: Gabor Juhos <juhosg@openwrt.org>\nAcked-by: John Crispin <blogic@openwrt.org>\n---\n drivers/spi/Kconfig      |    6 +\n drivers/spi/Makefile     |    1 +\n drivers/spi/spi-rt2880.c |  530 ++++++++++++++++++++++++++++++++++++++++++++++\n 3 files changed, 537 insertions(+)\n create mode 100644 drivers/spi/spi-rt2880.c\n\n--- a/drivers/spi/Kconfig\n+++ b/drivers/spi/Kconfig\n@@ -719,6 +719,12 @@ config SPI_QCOM_GENI\n \t  This driver can also be built as a module.  If so, the module\n \t  will be called spi-geni-qcom.\n \n+config SPI_RT2880\n+\ttristate \"Ralink RT288x SPI Controller\"\n+\tdepends on RALINK\n+\thelp\n+\t  This selects a driver for the Ralink RT288x/RT305x SPI Controller.\n+\n config SPI_S3C24XX\n \ttristate \"Samsung S3C24XX series SPI\"\n \tdepends on ARCH_S3C24XX\n--- a/drivers/spi/Makefile\n+++ b/drivers/spi/Makefile\n@@ -100,6 +100,7 @@ obj-$(CONFIG_SPI_RB4XX)\t\t\t+= spi-rb4xx.o\n obj-$(CONFIG_MACH_REALTEK_RTL)\t\t+= spi-realtek-rtl.o\n obj-$(CONFIG_SPI_RPCIF)\t\t\t+= spi-rpc-if.o\n obj-$(CONFIG_SPI_RSPI)\t\t\t+= spi-rspi.o\n+obj-$(CONFIG_SPI_RT2880)\t\t+= spi-rt2880.o\n obj-$(CONFIG_SPI_S3C24XX)\t\t+= spi-s3c24xx-hw.o\n spi-s3c24xx-hw-y\t\t\t:= spi-s3c24xx.o\n obj-$(CONFIG_SPI_S3C64XX)\t\t+= spi-s3c64xx.o\n--- /dev/null\n+++ b/drivers/spi/spi-rt2880.c\n@@ -0,0 +1,530 @@\n+/*\n+ * spi-rt2880.c -- Ralink RT288x/RT305x SPI controller driver\n+ *\n+ * Copyright (C) 2011 Sergiy <piratfm@gmail.com>\n+ * Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>\n+ *\n+ * Some parts are based on spi-orion.c:\n+ *   Author: Shadi Ammouri <shadi@marvell.com>\n+ *   Copyright (C) 2007-2008 Marvell Ltd.\n+ *\n+ * This program is free software; you can redistribute it and/or modify\n+ * it under the terms of the GNU General Public License version 2 as\n+ * published by the Free Software Foundation.\n+ */\n+\n+#include <linux/init.h>\n+#include <linux/module.h>\n+#include <linux/clk.h>\n+#include <linux/err.h>\n+#include <linux/delay.h>\n+#include <linux/io.h>\n+#include <linux/reset.h>\n+#include <linux/spi/spi.h>\n+#include <linux/platform_device.h>\n+#include <linux/gpio.h>\n+\n+#define DRIVER_NAME\t\t\t\"spi-rt2880\"\n+\n+#define RAMIPS_SPI_STAT\t\t\t0x00\n+#define RAMIPS_SPI_CFG\t\t\t0x10\n+#define RAMIPS_SPI_CTL\t\t\t0x14\n+#define RAMIPS_SPI_DATA\t\t\t0x20\n+#define RAMIPS_SPI_ADDR\t\t\t0x24\n+#define RAMIPS_SPI_BS\t\t\t0x28\n+#define RAMIPS_SPI_USER\t\t\t0x2C\n+#define RAMIPS_SPI_TXFIFO\t\t0x30\n+#define RAMIPS_SPI_RXFIFO\t\t0x34\n+#define RAMIPS_SPI_FIFO_STAT\t\t0x38\n+#define RAMIPS_SPI_MODE\t\t\t0x3C\n+#define RAMIPS_SPI_DEV_OFFSET\t\t0x40\n+#define RAMIPS_SPI_DMA\t\t\t0x80\n+#define RAMIPS_SPI_DMASTAT\t\t0x84\n+#define RAMIPS_SPI_ARBITER\t\t0xF0\n+\n+/* SPISTAT register bit field */\n+#define SPISTAT_BUSY\t\t\tBIT(0)\n+\n+/* SPICFG register bit field */\n+#define SPICFG_ADDRMODE\t\t\tBIT(12)\n+#define SPICFG_RXENVDIS\t\t\tBIT(11)\n+#define SPICFG_RXCAP\t\t\tBIT(10)\n+#define SPICFG_SPIENMODE\t\tBIT(9)\n+#define SPICFG_MSBFIRST\t\t\tBIT(8)\n+#define SPICFG_SPICLKPOL\t\tBIT(6)\n+#define SPICFG_RXCLKEDGE_FALLING\tBIT(5)\n+#define SPICFG_TXCLKEDGE_FALLING\tBIT(4)\n+#define SPICFG_HIZSPI\t\t\tBIT(3)\n+#define SPICFG_SPICLK_PRESCALE_MASK\t0x7\n+#define SPICFG_SPICLK_DIV2\t\t0\n+#define SPICFG_SPICLK_DIV4\t\t1\n+#define SPICFG_SPICLK_DIV8\t\t2\n+#define SPICFG_SPICLK_DIV16\t\t3\n+#define SPICFG_SPICLK_DIV32\t\t4\n+#define SPICFG_SPICLK_DIV64\t\t5\n+#define SPICFG_SPICLK_DIV128\t\t6\n+#define SPICFG_SPICLK_DISABLE\t\t7\n+\n+/* SPICTL register bit field */\n+#define SPICTL_START\t\t\tBIT(4)\n+#define SPICTL_HIZSDO\t\t\tBIT(3)\n+#define SPICTL_STARTWR\t\t\tBIT(2)\n+#define SPICTL_STARTRD\t\t\tBIT(1)\n+#define SPICTL_SPIENA\t\t\tBIT(0)\n+\n+/* SPIUSER register bit field */\n+#define SPIUSER_USERMODE\t\tBIT(21)\n+#define SPIUSER_INSTR_PHASE\t\tBIT(20)\n+#define SPIUSER_ADDR_PHASE_MASK\t\t0x7\n+#define SPIUSER_ADDR_PHASE_OFFSET\t17\n+#define SPIUSER_MODE_PHASE\t\tBIT(16)\n+#define SPIUSER_DUMMY_PHASE_MASK\t0x3\n+#define SPIUSER_DUMMY_PHASE_OFFSET\t14\n+#define SPIUSER_DATA_PHASE_MASK\t\t0x3\n+#define SPIUSER_DATA_PHASE_OFFSET\t12\n+#define SPIUSER_DATA_READ\t\t(BIT(0) << SPIUSER_DATA_PHASE_OFFSET)\n+#define SPIUSER_DATA_WRITE\t\t(BIT(1) << SPIUSER_DATA_PHASE_OFFSET)\n+#define SPIUSER_ADDR_TYPE_OFFSET\t9\n+#define SPIUSER_MODE_TYPE_OFFSET\t6\n+#define SPIUSER_DUMMY_TYPE_OFFSET\t3\n+#define SPIUSER_DATA_TYPE_OFFSET\t0\n+#define SPIUSER_TRANSFER_MASK\t\t0x7\n+#define SPIUSER_TRANSFER_SINGLE\t\tBIT(0)\n+#define SPIUSER_TRANSFER_DUAL\t\tBIT(1)\n+#define SPIUSER_TRANSFER_QUAD\t\tBIT(2)\n+\n+#define SPIUSER_TRANSFER_TYPE(type) ( \\\n+\t(type << SPIUSER_ADDR_TYPE_OFFSET) | \\\n+\t(type << SPIUSER_MODE_TYPE_OFFSET) | \\\n+\t(type << SPIUSER_DUMMY_TYPE_OFFSET) | \\\n+\t(type << SPIUSER_DATA_TYPE_OFFSET) \\\n+)\n+\n+/* SPIFIFOSTAT register bit field */\n+#define SPIFIFOSTAT_TXEMPTY\t\tBIT(19)\n+#define SPIFIFOSTAT_RXEMPTY\t\tBIT(18)\n+#define SPIFIFOSTAT_TXFULL\t\tBIT(17)\n+#define SPIFIFOSTAT_RXFULL\t\tBIT(16)\n+#define SPIFIFOSTAT_FIFO_MASK\t\t0xff\n+#define SPIFIFOSTAT_TX_OFFSET\t\t8\n+#define SPIFIFOSTAT_RX_OFFSET\t\t0\n+\n+#define SPI_FIFO_DEPTH\t\t\t16\n+\n+/* SPIMODE register bit field */\n+#define SPIMODE_MODE_OFFSET\t\t24\n+#define SPIMODE_DUMMY_OFFSET\t\t0\n+\n+/* SPIARB register bit field */\n+#define SPICTL_ARB_EN\t\t\tBIT(31)\n+#define SPICTL_CSCTL1\t\t\tBIT(16)\n+#define SPI1_POR\t\t\tBIT(1)\n+#define SPI0_POR\t\t\tBIT(0)\n+\n+#define RT2880_SPI_MODE_BITS\t(SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | \\\n+\t\tSPI_CS_HIGH)\n+\n+static atomic_t hw_reset_count = ATOMIC_INIT(0);\n+\n+struct rt2880_spi {\n+\tstruct spi_master\t*master;\n+\tvoid __iomem\t\t*base;\n+\tu32\t\t\tspeed;\n+\tu16\t\t\twait_loops;\n+\tu16\t\t\tmode;\n+\tstruct clk\t\t*clk;\n+};\n+\n+static inline struct rt2880_spi *spidev_to_rt2880_spi(struct spi_device *spi)\n+{\n+\treturn spi_master_get_devdata(spi->master);\n+}\n+\n+static inline u32 rt2880_spi_read(struct rt2880_spi *rs, u32 reg)\n+{\n+\treturn ioread32(rs->base + reg);\n+}\n+\n+static inline void rt2880_spi_write(struct rt2880_spi *rs, u32 reg,\n+\t\tconst u32 val)\n+{\n+\tiowrite32(val, rs->base + reg);\n+}\n+\n+static inline void rt2880_spi_setbits(struct rt2880_spi *rs, u32 reg, u32 mask)\n+{\n+\tvoid __iomem *addr = rs->base + reg;\n+\n+\tiowrite32((ioread32(addr) | mask), addr);\n+}\n+\n+static inline void rt2880_spi_clrbits(struct rt2880_spi *rs, u32 reg, u32 mask)\n+{\n+\tvoid __iomem *addr = rs->base + reg;\n+\n+\tiowrite32((ioread32(addr) & ~mask), addr);\n+}\n+\n+static u32 rt2880_spi_baudrate_get(struct spi_device *spi, unsigned int speed)\n+{\n+\tstruct rt2880_spi *rs = spidev_to_rt2880_spi(spi);\n+\tu32 rate;\n+\tu32 prescale;\n+\n+\t/*\n+\t * the supported rates are: 2, 4, 8, ... 128\n+\t * round up as we look for equal or less speed\n+\t */\n+\trate = DIV_ROUND_UP(clk_get_rate(rs->clk), speed);\n+\trate = roundup_pow_of_two(rate);\n+\n+\t/* Convert the rate to SPI clock divisor value.\t*/\n+\tprescale = ilog2(rate / 2);\n+\n+\t/* some tolerance. double and add 100 */\n+\trs->wait_loops = (8 * HZ * loops_per_jiffy) /\n+\t\t(clk_get_rate(rs->clk) / rate);\n+\trs->wait_loops = (rs->wait_loops << 1) + 100;\n+\trs->speed = speed;\n+\n+\tdev_dbg(&spi->dev, \"speed: %lu/%u, rate: %u, prescal: %u, loops: %hu\\n\",\n+\t\t\tclk_get_rate(rs->clk) / rate, speed, rate, prescale,\n+\t\t\trs->wait_loops);\n+\n+\treturn prescale;\n+}\n+\n+static u32 get_arbiter_offset(struct spi_master *master)\n+{\n+\tu32 offset;\n+\n+\toffset = RAMIPS_SPI_ARBITER;\n+\tif (master->bus_num == 1)\n+\t\toffset -= RAMIPS_SPI_DEV_OFFSET;\n+\n+\treturn offset;\n+}\n+\n+static void rt2880_spi_set_cs(struct spi_device *spi, bool enable)\n+{\n+\tstruct rt2880_spi *rs = spidev_to_rt2880_spi(spi);\n+\n+\tif (enable)\n+\t\trt2880_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_SPIENA);\n+\telse\n+\t\trt2880_spi_clrbits(rs, RAMIPS_SPI_CTL, SPICTL_SPIENA);\n+}\n+\n+static int rt2880_spi_wait_ready(struct rt2880_spi *rs, int len)\n+{\n+\tint loop = rs->wait_loops * len;\n+\n+\twhile ((rt2880_spi_read(rs, RAMIPS_SPI_STAT) & SPISTAT_BUSY) && --loop)\n+\t\tcpu_relax();\n+\n+\tif (loop)\n+\t\treturn 0;\n+\n+\treturn -ETIMEDOUT;\n+}\n+\n+static void rt2880_dump_reg(struct spi_master *master)\n+{\n+\tstruct rt2880_spi *rs = spi_master_get_devdata(master);\n+\n+\tdev_dbg(&master->dev, \"stat: %08x, cfg: %08x, ctl: %08x, \" \\\n+\t\t\t\"data: %08x, arb: %08x\\n\",\n+\t\t\trt2880_spi_read(rs, RAMIPS_SPI_STAT),\n+\t\t\trt2880_spi_read(rs, RAMIPS_SPI_CFG),\n+\t\t\trt2880_spi_read(rs, RAMIPS_SPI_CTL),\n+\t\t\trt2880_spi_read(rs, RAMIPS_SPI_DATA),\n+\t\t\trt2880_spi_read(rs, get_arbiter_offset(master)));\n+}\n+\n+static int rt2880_spi_transfer_one(struct spi_master *master,\n+\t\tstruct spi_device *spi, struct spi_transfer *xfer)\n+{\n+\tstruct rt2880_spi *rs = spi_master_get_devdata(master);\n+\tunsigned len;\n+\tconst u8 *tx = xfer->tx_buf;\n+\tu8 *rx = xfer->rx_buf;\n+\tint err = 0;\n+\n+\t/* change clock speed  */\n+\tif (unlikely(rs->speed != xfer->speed_hz)) {\n+\t\tu32 reg;\n+\t\treg = rt2880_spi_read(rs, RAMIPS_SPI_CFG);\n+\t\treg &= ~SPICFG_SPICLK_PRESCALE_MASK;\n+\t\treg |= rt2880_spi_baudrate_get(spi, xfer->speed_hz);\n+\t\trt2880_spi_write(rs, RAMIPS_SPI_CFG, reg);\n+\t}\n+\n+\tif (tx) {\n+\t\tlen = xfer->len;\n+\t\twhile (len-- > 0) {\n+\t\t\trt2880_spi_write(rs, RAMIPS_SPI_DATA, *tx++);\n+\t\t\trt2880_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_STARTWR);\n+\t\t\terr = rt2880_spi_wait_ready(rs, 1);\n+\t\t\tif (err) {\n+\t\t\t\tdev_err(&spi->dev, \"TX failed, err=%d\\n\", err);\n+\t\t\t\tgoto out;\n+\t\t\t}\n+\t\t}\n+\t}\n+\n+\tif (rx) {\n+\t\tlen = xfer->len;\n+\t\twhile (len-- > 0) {\n+\t\t\trt2880_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_STARTRD);\n+\t\t\terr = rt2880_spi_wait_ready(rs, 1);\n+\t\t\tif (err) {\n+\t\t\t\tdev_err(&spi->dev, \"RX failed, err=%d\\n\", err);\n+\t\t\t\tgoto out;\n+\t\t\t}\n+\t\t\t*rx++ = (u8) rt2880_spi_read(rs, RAMIPS_SPI_DATA);\n+\t\t}\n+\t}\n+\n+out:\n+\treturn err;\n+}\n+\n+/* copy from spi.c */\n+static void spi_set_cs(struct spi_device *spi, bool enable)\n+{\n+\tif (spi->mode & SPI_CS_HIGH)\n+\t\tenable = !enable;\n+\n+\tif (spi->cs_gpio >= 0)\n+\t\tgpio_set_value(spi->cs_gpio, !enable);\n+\telse if (spi->master->set_cs)\n+\t\tspi->master->set_cs(spi, !enable);\n+}\n+\n+static int rt2880_spi_setup(struct spi_device *spi)\n+{\n+\tstruct spi_master *master = spi->master;\n+\tstruct rt2880_spi *rs = spi_master_get_devdata(master);\n+\tu32 reg, old_reg, arbit_off;\n+\n+\tif ((spi->max_speed_hz > master->max_speed_hz) ||\n+\t\t\t(spi->max_speed_hz < master->min_speed_hz)) {\n+\t\tdev_err(&spi->dev, \"invalide requested speed %d Hz\\n\",\n+\t\t\t\tspi->max_speed_hz);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (!(master->bits_per_word_mask &\n+\t\t\t\tBIT(spi->bits_per_word - 1))) {\n+\t\tdev_err(&spi->dev, \"invalide bits_per_word %d\\n\",\n+\t\t\t\tspi->bits_per_word);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\t/* the hardware seems can't work on mode0 force it to mode3 */\n+\tif ((spi->mode & (SPI_CPOL | SPI_CPHA)) == SPI_MODE_0) {\n+\t\tdev_warn(&spi->dev, \"force spi mode3\\n\");\n+\t\tspi->mode |= SPI_MODE_3;\n+\t}\n+\n+\t/* chip polarity */\n+\tarbit_off = get_arbiter_offset(master);\n+\treg = old_reg = rt2880_spi_read(rs, arbit_off);\n+\tif (spi->mode & SPI_CS_HIGH) {\n+\t\tswitch (master->bus_num) {\n+\t\tcase 1:\n+\t\t\treg |= SPI1_POR;\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\treg |= SPI0_POR;\n+\t\t\tbreak;\n+\t\t}\n+\t} else {\n+\t\tswitch (master->bus_num) {\n+\t\tcase 1:\n+\t\t\treg &= ~SPI1_POR;\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\treg &= ~SPI0_POR;\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\n+\t/* enable spi1 */\n+\tif (master->bus_num == 1)\n+\t\treg |= SPICTL_ARB_EN;\n+\n+\tif (reg != old_reg)\n+\t\trt2880_spi_write(rs, arbit_off, reg);\n+\n+\t/* deselected the spi device */\n+\tspi_set_cs(spi, false);\n+\n+\trt2880_dump_reg(master);\n+\n+\treturn 0;\n+}\n+\n+static int rt2880_spi_prepare_message(struct spi_master *master,\n+\t\tstruct spi_message *msg)\n+{\n+\tstruct rt2880_spi *rs = spi_master_get_devdata(master);\n+\tstruct spi_device *spi = msg->spi;\n+\tu32 reg;\n+\n+\tif ((rs->mode == spi->mode) && (rs->speed == spi->max_speed_hz))\n+\t\treturn 0;\n+\n+#if 0\n+\t/* set spido to tri-state */\n+\trt2880_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_HIZSDO);\n+#endif\n+\n+\treg = rt2880_spi_read(rs, RAMIPS_SPI_CFG);\n+\n+\treg &= ~(SPICFG_MSBFIRST | SPICFG_SPICLKPOL |\n+\t\t\tSPICFG_RXCLKEDGE_FALLING |\n+\t\t\tSPICFG_TXCLKEDGE_FALLING |\n+\t\t\tSPICFG_SPICLK_PRESCALE_MASK);\n+\n+\t/* MSB */\n+\tif (!(spi->mode & SPI_LSB_FIRST))\n+\t\treg |= SPICFG_MSBFIRST;\n+\n+\t/* spi mode */\n+\tswitch (spi->mode & (SPI_CPOL | SPI_CPHA)) {\n+\tcase SPI_MODE_0:\n+\t\treg |= SPICFG_TXCLKEDGE_FALLING;\n+\t\tbreak;\n+\tcase SPI_MODE_1:\n+\t\treg |= SPICFG_RXCLKEDGE_FALLING;\n+\t\tbreak;\n+\tcase SPI_MODE_2:\n+\t\treg |= SPICFG_SPICLKPOL | SPICFG_RXCLKEDGE_FALLING;\n+\t\tbreak;\n+\tcase SPI_MODE_3:\n+\t\treg |= SPICFG_SPICLKPOL | SPICFG_TXCLKEDGE_FALLING;\n+\t\tbreak;\n+\t}\n+\trs->mode = spi->mode;\n+\n+#if 0\n+\t/* set spiclk and spiena to tri-state */\n+\treg |= SPICFG_HIZSPI;\n+#endif\n+\n+\t/* clock divide */\n+\treg |= rt2880_spi_baudrate_get(spi, spi->max_speed_hz);\n+\n+\trt2880_spi_write(rs, RAMIPS_SPI_CFG, reg);\n+\n+\treturn 0;\n+}\n+\n+static int rt2880_spi_probe(struct platform_device *pdev)\n+{\n+\tstruct spi_master *master;\n+\tstruct rt2880_spi *rs;\n+\tvoid __iomem *base;\n+\tstruct resource *r;\n+\tstruct clk *clk;\n+\tint ret;\n+\n+\tr = platform_get_resource(pdev, IORESOURCE_MEM, 0);\n+\tbase = devm_ioremap_resource(&pdev->dev, r);\n+\tif (IS_ERR(base))\n+\t\treturn PTR_ERR(base);\n+\n+\tclk = devm_clk_get(&pdev->dev, NULL);\n+\tif (IS_ERR(clk)) {\n+\t\tdev_err(&pdev->dev, \"unable to get SYS clock\\n\");\n+\t\treturn PTR_ERR(clk);\n+\t}\n+\n+\tret = clk_prepare_enable(clk);\n+\tif (ret)\n+\t\tgoto err_clk;\n+\n+\tmaster = spi_alloc_master(&pdev->dev, sizeof(*rs));\n+\tif (master == NULL) {\n+\t\tdev_dbg(&pdev->dev, \"master allocation failed\\n\");\n+\t\tret = -ENOMEM;\n+\t\tgoto err_clk;\n+\t}\n+\n+\tmaster->dev.of_node = pdev->dev.of_node;\n+\tmaster->mode_bits = RT2880_SPI_MODE_BITS;\n+\tmaster->bits_per_word_mask = SPI_BPW_MASK(8);\n+\tmaster->min_speed_hz = clk_get_rate(clk) / 128;\n+\tmaster->max_speed_hz = clk_get_rate(clk) / 2;\n+\tmaster->flags = SPI_MASTER_HALF_DUPLEX;\n+\tmaster->setup = rt2880_spi_setup;\n+\tmaster->prepare_message = rt2880_spi_prepare_message;\n+\tmaster->set_cs = rt2880_spi_set_cs;\n+\tmaster->transfer_one = rt2880_spi_transfer_one,\n+\n+\tdev_set_drvdata(&pdev->dev, master);\n+\n+\trs = spi_master_get_devdata(master);\n+\trs->master = master;\n+\trs->base = base;\n+\trs->clk = clk;\n+\n+\tif (atomic_inc_return(&hw_reset_count) == 1)\n+\t\tdevice_reset(&pdev->dev);\n+\n+\tret = devm_spi_register_master(&pdev->dev, master);\n+\tif (ret < 0) {\n+\t\tdev_err(&pdev->dev, \"devm_spi_register_master error.\\n\");\n+\t\tgoto err_master;\n+\t}\n+\n+\treturn ret;\n+\n+err_master:\n+\tspi_master_put(master);\n+\tkfree(master);\n+err_clk:\n+\tclk_disable_unprepare(clk);\n+\n+\treturn ret;\n+}\n+\n+static int rt2880_spi_remove(struct platform_device *pdev)\n+{\n+\tstruct spi_master *master;\n+\tstruct rt2880_spi *rs;\n+\n+\tmaster = dev_get_drvdata(&pdev->dev);\n+\trs = spi_master_get_devdata(master);\n+\n+\tclk_disable_unprepare(rs->clk);\n+\tatomic_dec(&hw_reset_count);\n+\n+\treturn 0;\n+}\n+\n+MODULE_ALIAS(\"platform:\" DRIVER_NAME);\n+\n+static const struct of_device_id rt2880_spi_match[] = {\n+\t{ .compatible = \"ralink,rt2880-spi\" },\n+\t{},\n+};\n+MODULE_DEVICE_TABLE(of, rt2880_spi_match);\n+\n+static struct platform_driver rt2880_spi_driver = {\n+\t.driver = {\n+\t\t.name = DRIVER_NAME,\n+\t\t.owner = THIS_MODULE,\n+\t\t.of_match_table = rt2880_spi_match,\n+\t},\n+\t.probe = rt2880_spi_probe,\n+\t.remove = rt2880_spi_remove,\n+};\n+\n+module_platform_driver(rt2880_spi_driver);\n+\n+MODULE_DESCRIPTION(\"Ralink SPI driver\");\n+MODULE_AUTHOR(\"Sergiy <piratfm@gmail.com>\");\n+MODULE_AUTHOR(\"Gabor Juhos <juhosg@openwrt.org>\");\n+MODULE_LICENSE(\"GPL\");\n"
  },
  {
    "path": "target/linux/ramips/patches-5.15/825-i2c-MIPS-adds-ralink-I2C-driver.patch",
    "content": "From 723b8beaabf3c3c4b1ce69480141f1e926f3f3b2 Mon Sep 17 00:00:00 2001\nFrom: John Crispin <blogic@openwrt.org>\nDate: Sun, 27 Jul 2014 09:52:56 +0100\nSubject: [PATCH 44/53] i2c: MIPS: adds ralink I2C driver\n\nSigned-off-by: John Crispin <blogic@openwrt.org>\n---\n .../devicetree/bindings/i2c/i2c-ralink.txt         |   27 ++\n drivers/i2c/busses/Kconfig                         |    4 +\n drivers/i2c/busses/Makefile                        |    1 +\n drivers/i2c/busses/i2c-ralink.c                    |  327 ++++++++++++++++++++\n 4 files changed, 359 insertions(+)\n create mode 100644 Documentation/devicetree/bindings/i2c/i2c-ralink.txt\n create mode 100644 drivers/i2c/busses/i2c-ralink.c\n\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/i2c/i2c-ralink.txt\n@@ -0,0 +1,27 @@\n+I2C for Ralink platforms\n+\n+Required properties :\n+- compatible : Must be \"link,rt3052-i2c\"\n+- reg: physical base address of the controller and length of memory mapped\n+     region.\n+- #address-cells = <1>;\n+- #size-cells = <0>;\n+\n+Optional properties:\n+- Child nodes conforming to i2c bus binding\n+\n+Example :\n+\n+palmbus@10000000 {\n+\ti2c@900 {\n+\t\tcompatible = \"link,rt3052-i2c\";\n+\t\treg = <0x900 0x100>;\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\n+\t\thwmon@4b {\n+\t\t\tcompatible = \"national,lm92\";\n+\t\t\treg = <0x4b>;\n+\t\t};\n+\t};\n+};\n--- a/drivers/i2c/busses/Kconfig\n+++ b/drivers/i2c/busses/Kconfig\n@@ -949,6 +949,11 @@ config I2C_RK3X\n \t  This driver can also be built as a module. If so, the module will\n \t  be called i2c-rk3x.\n \n+config I2C_RALINK\n+\ttristate \"Ralink I2C Controller\"\n+\tdepends on RALINK && !SOC_MT7621\n+\tselect OF_I2C\n+\n config HAVE_S3C2410_I2C\n \tbool\n \thelp\n--- a/drivers/i2c/busses/Makefile\n+++ b/drivers/i2c/busses/Makefile\n@@ -89,6 +89,7 @@ obj-$(CONFIG_I2C_PCA_PLATFORM)\t+= i2c-pc\n obj-$(CONFIG_I2C_PNX)\t\t+= i2c-pnx.o\n obj-$(CONFIG_I2C_PXA)\t\t+= i2c-pxa.o\n obj-$(CONFIG_I2C_PXA_PCI)\t+= i2c-pxa-pci.o\n+obj-$(CONFIG_I2C_RALINK)\t+= i2c-ralink.o\n obj-$(CONFIG_I2C_QCOM_CCI)\t+= i2c-qcom-cci.o\n obj-$(CONFIG_I2C_QCOM_GENI)\t+= i2c-qcom-geni.o\n obj-$(CONFIG_I2C_QUP)\t\t+= i2c-qup.o\n--- /dev/null\n+++ b/drivers/i2c/busses/i2c-ralink.c\n@@ -0,0 +1,435 @@\n+/*\n+ * drivers/i2c/busses/i2c-ralink.c\n+ *\n+ * Copyright (C) 2013 Steven Liu <steven_liu@mediatek.com>\n+ * Copyright (C) 2016 Michael Lee <igvtee@gmail.com>\n+ *\n+ * Improve driver for i2cdetect from i2c-tools to detect i2c devices on the bus.\n+ * (C) 2014 Sittisak <sittisaks@hotmail.com>\n+ *\n+ * This software is licensed under the terms of the GNU General Public\n+ * License version 2, as published by the Free Software Foundation, and\n+ * may be copied, distributed, and modified under those terms.\n+ *\n+ * This program is distributed in the hope that it will be useful,\n+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\n+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n+ * GNU General Public License for more details.\n+ *\n+ */\n+\n+#include <linux/interrupt.h>\n+#include <linux/kernel.h>\n+#include <linux/module.h>\n+#include <linux/reset.h>\n+#include <linux/delay.h>\n+#include <linux/slab.h>\n+#include <linux/init.h>\n+#include <linux/errno.h>\n+#include <linux/platform_device.h>\n+#include <linux/of_platform.h>\n+#include <linux/i2c.h>\n+#include <linux/io.h>\n+#include <linux/err.h>\n+#include <linux/clk.h>\n+\n+#define REG_CONFIG_REG\t\t0x00\n+#define REG_CLKDIV_REG\t\t0x04\n+#define REG_DEVADDR_REG\t\t0x08\n+#define REG_ADDR_REG\t\t0x0C\n+#define REG_DATAOUT_REG\t\t0x10\n+#define REG_DATAIN_REG\t\t0x14\n+#define REG_STATUS_REG\t\t0x18\n+#define REG_STARTXFR_REG\t0x1C\n+#define REG_BYTECNT_REG\t\t0x20\n+\n+/* REG_CONFIG_REG */\n+#define I2C_ADDRLEN_OFFSET\t5\n+#define I2C_DEVADLEN_OFFSET\t2\n+#define I2C_ADDRLEN_MASK\t0x3\n+#define I2C_ADDR_DIS\t\tBIT(1)\n+#define I2C_DEVADDR_DIS\t\tBIT(0)\n+#define I2C_ADDRLEN_8\t\t(7 << I2C_ADDRLEN_OFFSET)\n+#define I2C_DEVADLEN_7\t\t(6 << I2C_DEVADLEN_OFFSET)\n+#define I2C_CONF_DEFAULT\t(I2C_ADDRLEN_8 | I2C_DEVADLEN_7)\n+\n+/* REG_CLKDIV_REG */\n+#define I2C_CLKDIV_MASK\t\t0xffff\n+\n+/* REG_DEVADDR_REG */\n+#define I2C_DEVADDR_MASK\t0x7f\n+\n+/* REG_ADDR_REG */\n+#define I2C_ADDR_MASK\t\t0xff\n+\n+/* REG_STATUS_REG */\n+#define I2C_STARTERR\t\tBIT(4)\n+#define I2C_ACKERR\t\tBIT(3)\n+#define I2C_DATARDY\t\tBIT(2)\n+#define I2C_SDOEMPTY\t\tBIT(1)\n+#define I2C_BUSY\t\tBIT(0)\n+\n+/* REG_STARTXFR_REG */\n+#define NOSTOP_CMD\t\tBIT(2)\n+#define NODATA_CMD\t\tBIT(1)\n+#define READ_CMD\t\tBIT(0)\n+\n+/* REG_BYTECNT_REG */\n+#define BYTECNT_MAX\t\t64\n+#define SET_BYTECNT(x)\t\t(x - 1)\n+\n+/* timeout waiting for I2C devices to respond (clock streching) */\n+#define TIMEOUT_MS              1000\n+#define DELAY_INTERVAL_US       100\n+\n+struct rt_i2c {\n+\tvoid __iomem *base;\n+\tstruct clk *clk;\n+\tstruct device *dev;\n+\tstruct i2c_adapter adap;\n+\tu32 cur_clk;\n+\tu32 clk_div;\n+\tu32 flags;\n+};\n+\n+static void rt_i2c_w32(struct rt_i2c *i2c, u32 val, unsigned reg)\n+{\n+\tiowrite32(val, i2c->base + reg);\n+}\n+\n+static u32 rt_i2c_r32(struct rt_i2c *i2c, unsigned reg)\n+{\n+\treturn ioread32(i2c->base + reg);\n+}\n+\n+static int poll_down_timeout(void __iomem *addr, u32 mask)\n+{\n+\tunsigned long timeout = jiffies + msecs_to_jiffies(TIMEOUT_MS);\n+\n+\tdo {\n+\t\tif (!(readl_relaxed(addr) & mask))\n+\t\t\treturn 0;\n+\n+\t\tusleep_range(DELAY_INTERVAL_US, DELAY_INTERVAL_US + 50);\n+\t} while (time_before(jiffies, timeout));\n+\n+\treturn (readl_relaxed(addr) & mask) ? -EAGAIN : 0;\n+}\n+\n+static int rt_i2c_wait_idle(struct rt_i2c *i2c)\n+{\n+\tint ret;\n+\n+\tret = poll_down_timeout(i2c->base + REG_STATUS_REG, I2C_BUSY);\n+\tif (ret < 0)\n+\t\tdev_dbg(i2c->dev, \"idle err(%d)\\n\", ret);\n+\n+\treturn ret;\n+}\n+\n+static int poll_up_timeout(void __iomem *addr, u32 mask)\n+{\n+\tunsigned long timeout = jiffies + msecs_to_jiffies(TIMEOUT_MS);\n+\tu32 status;\n+\n+\tdo {\n+\t\tstatus = readl_relaxed(addr);\n+\n+\t\t/* check error status */\n+\t\tif (status & I2C_STARTERR)\n+\t\t\treturn -EAGAIN;\n+\t\telse if (status & I2C_ACKERR)\n+\t\t\treturn -ENXIO;\n+\t\telse if (status & mask)\n+\t\t\treturn 0;\n+\n+\t\tusleep_range(DELAY_INTERVAL_US, DELAY_INTERVAL_US + 50);\n+\t} while (time_before(jiffies, timeout));\n+\n+\treturn -ETIMEDOUT;\n+}\n+\n+static int rt_i2c_wait_rx_done(struct rt_i2c *i2c)\n+{\n+\tint ret;\n+\n+\tret = poll_up_timeout(i2c->base + REG_STATUS_REG, I2C_DATARDY);\n+\tif (ret < 0)\n+\t\tdev_dbg(i2c->dev, \"rx err(%d)\\n\", ret);\n+\n+\treturn ret;\n+}\n+\n+static int rt_i2c_wait_tx_done(struct rt_i2c *i2c)\n+{\n+\tint ret;\n+\n+\tret = poll_up_timeout(i2c->base + REG_STATUS_REG, I2C_SDOEMPTY);\n+\tif (ret < 0)\n+\t\tdev_dbg(i2c->dev, \"tx err(%d)\\n\", ret);\n+\n+\treturn ret;\n+}\n+\n+static void rt_i2c_reset(struct rt_i2c *i2c)\n+{\n+\tdevice_reset(i2c->adap.dev.parent);\n+\tbarrier();\n+\trt_i2c_w32(i2c, i2c->clk_div, REG_CLKDIV_REG);\n+}\n+\n+static void rt_i2c_dump_reg(struct rt_i2c *i2c)\n+{\n+\tdev_dbg(i2c->dev, \"conf %08x, clkdiv %08x, devaddr %08x, \" \\\n+\t\t\t\"addr %08x, dataout %08x, datain %08x, \" \\\n+\t\t\t\"status %08x, startxfr %08x, bytecnt %08x\\n\",\n+\t\t\trt_i2c_r32(i2c, REG_CONFIG_REG),\n+\t\t\trt_i2c_r32(i2c, REG_CLKDIV_REG),\n+\t\t\trt_i2c_r32(i2c, REG_DEVADDR_REG),\n+\t\t\trt_i2c_r32(i2c, REG_ADDR_REG),\n+\t\t\trt_i2c_r32(i2c, REG_DATAOUT_REG),\n+\t\t\trt_i2c_r32(i2c, REG_DATAIN_REG),\n+\t\t\trt_i2c_r32(i2c, REG_STATUS_REG),\n+\t\t\trt_i2c_r32(i2c, REG_STARTXFR_REG),\n+\t\t\trt_i2c_r32(i2c, REG_BYTECNT_REG));\n+}\n+\n+static int rt_i2c_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,\n+\t\tint num)\n+{\n+\tstruct rt_i2c *i2c;\n+\tstruct i2c_msg *pmsg;\n+\tunsigned char addr;\n+\tint i, j, ret;\n+\tu32 cmd;\n+\n+\ti2c = i2c_get_adapdata(adap);\n+\n+\tfor (i = 0; i < num; i++) {\n+\t\tpmsg = &msgs[i];\n+\t\tif (i == (num - 1))\n+\t\t\tcmd = 0;\n+\t\telse\n+\t\t\tcmd = NOSTOP_CMD;\n+\n+\t\tdev_dbg(i2c->dev, \"addr: 0x%x, len: %d, flags: 0x%x, stop: %d\\n\",\n+\t\t\t\tpmsg->addr, pmsg->len, pmsg->flags,\n+\t\t\t\t(cmd == 0)? 1 : 0);\n+\n+\t\t/* wait hardware idle */\n+\t\tif ((ret = rt_i2c_wait_idle(i2c)))\n+\t\t\tgoto err_timeout;\n+\n+\t\tif (pmsg->flags & I2C_M_TEN) {\n+\t\t\trt_i2c_w32(i2c, I2C_CONF_DEFAULT, REG_CONFIG_REG);\n+\t\t\t/* 10 bits address */\n+\t\t\taddr = 0x78 | ((pmsg->addr >> 8) & 0x03);\n+\t\t\trt_i2c_w32(i2c, addr & I2C_DEVADDR_MASK,\n+\t\t\t\t\tREG_DEVADDR_REG);\n+\t\t\trt_i2c_w32(i2c, pmsg->addr & I2C_ADDR_MASK,\n+\t\t\t\t\tREG_ADDR_REG);\n+\t\t} else {\n+\t\t\trt_i2c_w32(i2c, I2C_CONF_DEFAULT | I2C_ADDR_DIS,\n+\t\t\t\t\tREG_CONFIG_REG);\n+\t\t\t/* 7 bits address */\n+\t\t\trt_i2c_w32(i2c, pmsg->addr & I2C_DEVADDR_MASK,\n+\t\t\t\t\tREG_DEVADDR_REG);\n+\t\t}\n+\n+\t\t/* buffer length */\n+\t\tif (pmsg->len == 0)\n+\t\t\tcmd |= NODATA_CMD;\n+\t\telse\n+\t\t\trt_i2c_w32(i2c, SET_BYTECNT(pmsg->len),\n+\t\t\t\t\tREG_BYTECNT_REG);\n+\n+\t\tj = 0;\n+\t\tif (pmsg->flags & I2C_M_RD) {\n+\t\t\tcmd |= READ_CMD;\n+\t\t\t/* start transfer */\n+\t\t\tbarrier();\n+\t\t\trt_i2c_w32(i2c, cmd, REG_STARTXFR_REG);\n+\t\t\tdo {\n+\t\t\t\t/* wait */\n+\t\t\t\tif ((ret = rt_i2c_wait_rx_done(i2c)))\n+\t\t\t\t\tgoto err_timeout;\n+\t\t\t\t/* read data */\n+\t\t\t\tif (pmsg->len)\n+\t\t\t\t\tpmsg->buf[j] = rt_i2c_r32(i2c,\n+\t\t\t\t\t\t\tREG_DATAIN_REG);\n+\t\t\t\tj++;\n+\t\t\t} while (j < pmsg->len);\n+\t\t} else {\n+\t\t\tdo {\n+\t\t\t\t/* write data */\n+\t\t\t\tif (pmsg->len)\n+\t\t\t\t\trt_i2c_w32(i2c, pmsg->buf[j],\n+\t\t\t\t\t\t\tREG_DATAOUT_REG);\n+\t\t\t\t/* start transfer */\n+\t\t\t\tif (j == 0) {\n+\t\t\t\t\tbarrier();\n+\t\t\t\t\trt_i2c_w32(i2c, cmd, REG_STARTXFR_REG);\n+\t\t\t\t}\n+\t\t\t\t/* wait */\n+\t\t\t\tif ((ret = rt_i2c_wait_tx_done(i2c)))\n+\t\t\t\t\tgoto err_timeout;\n+\t\t\t\tj++;\n+\t\t\t} while (j < pmsg->len);\n+\t\t}\n+\t}\n+\t/* the return value is number of executed messages */\n+\tret = i;\n+\n+\treturn ret;\n+\n+err_timeout:\n+\trt_i2c_dump_reg(i2c);\n+\trt_i2c_reset(i2c);\n+\treturn ret;\n+}\n+\n+static u32 rt_i2c_func(struct i2c_adapter *a)\n+{\n+\treturn I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;\n+}\n+\n+static const struct i2c_algorithm rt_i2c_algo = {\n+\t.master_xfer\t= rt_i2c_master_xfer,\n+\t.functionality\t= rt_i2c_func,\n+};\n+\n+static const struct of_device_id i2c_rt_dt_ids[] = {\n+\t{ .compatible = \"ralink,rt2880-i2c\" },\n+\t{ /* sentinel */ }\n+};\n+\n+MODULE_DEVICE_TABLE(of, i2c_rt_dt_ids);\n+\n+static struct i2c_adapter_quirks rt_i2c_quirks = {\n+        .max_write_len = BYTECNT_MAX,\n+        .max_read_len = BYTECNT_MAX,\n+};\n+\n+static int rt_i2c_init(struct rt_i2c *i2c)\n+{\n+\tu32 reg;\n+\n+\t/* i2c_sclk = periph_clk / ((2 * clk_div) + 5) */\n+\ti2c->clk_div = (clk_get_rate(i2c->clk) - (5 * i2c->cur_clk)) /\n+\t\t(2 * i2c->cur_clk);\n+\tif (i2c->clk_div < 8)\n+\t\ti2c->clk_div = 8;\n+\tif (i2c->clk_div > I2C_CLKDIV_MASK)\n+\t\ti2c->clk_div = I2C_CLKDIV_MASK;\n+\n+\t/* check support combinde/repeated start message */\n+\trt_i2c_w32(i2c, NOSTOP_CMD, REG_STARTXFR_REG);\n+\treg = rt_i2c_r32(i2c, REG_STARTXFR_REG) & NOSTOP_CMD;\n+\n+\trt_i2c_reset(i2c);\n+\n+\treturn reg;\n+}\n+\n+static int rt_i2c_probe(struct platform_device *pdev)\n+{\n+\tstruct resource *res;\n+\tstruct rt_i2c *i2c;\n+\tstruct i2c_adapter *adap;\n+\tconst struct of_device_id *match;\n+\tint ret, restart;\n+\n+\tmatch = of_match_device(i2c_rt_dt_ids, &pdev->dev);\n+\n+\tres = platform_get_resource(pdev, IORESOURCE_MEM, 0);\n+\tif (!res) {\n+\t\tdev_err(&pdev->dev, \"no memory resource found\\n\");\n+\t\treturn -ENODEV;\n+\t}\n+\n+\ti2c = devm_kzalloc(&pdev->dev, sizeof(struct rt_i2c), GFP_KERNEL);\n+\tif (!i2c) {\n+\t\tdev_err(&pdev->dev, \"failed to allocate i2c_adapter\\n\");\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\ti2c->base = devm_ioremap_resource(&pdev->dev, res);\n+\tif (IS_ERR(i2c->base))\n+\t\treturn PTR_ERR(i2c->base);\n+\n+\ti2c->clk = devm_clk_get(&pdev->dev, NULL);\n+\tif (IS_ERR(i2c->clk)) {\n+\t\tdev_err(&pdev->dev, \"no clock defined\\n\");\n+\t\treturn -ENODEV;\n+\t}\n+\tclk_prepare_enable(i2c->clk);\n+\ti2c->dev = &pdev->dev;\n+\n+\tif (of_property_read_u32(pdev->dev.of_node,\n+\t\t\t\t\"clock-frequency\", &i2c->cur_clk))\n+\t\ti2c->cur_clk = 100000;\n+\n+\tadap = &i2c->adap;\n+\tadap->owner = THIS_MODULE;\n+\tadap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;\n+\tadap->algo = &rt_i2c_algo;\n+\tadap->retries = 3;\n+\tadap->dev.parent = &pdev->dev;\n+\ti2c_set_adapdata(adap, i2c);\n+\tadap->dev.of_node = pdev->dev.of_node;\n+\tstrlcpy(adap->name, dev_name(&pdev->dev), sizeof(adap->name));\n+\tadap->quirks = &rt_i2c_quirks;\n+\n+\tplatform_set_drvdata(pdev, i2c);\n+\n+\trestart = rt_i2c_init(i2c);\n+\n+\tret = i2c_add_adapter(adap);\n+\tif (ret < 0) {\n+\t\tdev_err(&pdev->dev, \"failed to add adapter\\n\");\n+\t\tclk_disable_unprepare(i2c->clk);\n+\t\treturn ret;\n+\t}\n+\n+\tdev_info(&pdev->dev, \"clock %uKHz, re-start %ssupport\\n\",\n+\t\t\ti2c->cur_clk/1000, restart ? \"\" : \"not \");\n+\n+\treturn ret;\n+}\n+\n+static int rt_i2c_remove(struct platform_device *pdev)\n+{\n+\tstruct rt_i2c *i2c = platform_get_drvdata(pdev);\n+\n+\ti2c_del_adapter(&i2c->adap);\n+\tclk_disable_unprepare(i2c->clk);\n+\n+\treturn 0;\n+}\n+\n+static struct platform_driver rt_i2c_driver = {\n+\t.probe\t\t= rt_i2c_probe,\n+\t.remove\t\t= rt_i2c_remove,\n+\t.driver\t\t= {\n+\t\t.owner\t= THIS_MODULE,\n+\t\t.name\t= \"i2c-ralink\",\n+\t\t.of_match_table = i2c_rt_dt_ids,\n+\t},\n+};\n+\n+static int __init i2c_rt_init (void)\n+{\n+\treturn platform_driver_register(&rt_i2c_driver);\n+}\n+subsys_initcall(i2c_rt_init);\n+\n+static void __exit i2c_rt_exit (void)\n+{\n+\tplatform_driver_unregister(&rt_i2c_driver);\n+}\n+module_exit(i2c_rt_exit);\n+\n+MODULE_AUTHOR(\"Steven Liu <steven_liu@mediatek.com>\");\n+MODULE_DESCRIPTION(\"Ralink I2c host driver\");\n+MODULE_LICENSE(\"GPL\");\n+MODULE_ALIAS(\"platform:Ralink-I2C\");\n"
  },
  {
    "path": "target/linux/ramips/patches-5.15/830-mmc-MIPS-ralink-add-sdhci-for-mt7620a-SoC.patch",
    "content": "From 23147af14531cbdada194b94120ef8774f46292d Mon Sep 17 00:00:00 2001\nFrom: John Crispin <blogic@openwrt.org>\nDate: Thu, 13 Nov 2014 19:08:40 +0100\nSubject: [PATCH 46/53] mmc: MIPS: ralink: add sdhci for mt7620a SoC\n\nSigned-off-by: John Crispin <blogic@openwrt.org>\n---\n drivers/mmc/host/Kconfig             |    2 +\n drivers/mmc/host/Makefile            |    1 +\n drivers/mmc/host/mtk-mmc/Kconfig     |   16 +\n drivers/mmc/host/mtk-mmc/Makefile    |   42 +\n drivers/mmc/host/mtk-mmc/board.h     |  137 ++\n drivers/mmc/host/mtk-mmc/dbg.c       |  347 ++++\n drivers/mmc/host/mtk-mmc/dbg.h       |  156 ++\n drivers/mmc/host/mtk-mmc/mt6575_sd.h | 1001 +++++++++++\n drivers/mmc/host/mtk-mmc/sd.c        | 3060 ++++++++++++++++++++++++++++++++++\n 9 files changed, 4762 insertions(+)\n create mode 100644 drivers/mmc/host/mtk-mmc/Kconfig\n create mode 100644 drivers/mmc/host/mtk-mmc/Makefile\n create mode 100644 drivers/mmc/host/mtk-mmc/board.h\n create mode 100644 drivers/mmc/host/mtk-mmc/dbg.c\n create mode 100644 drivers/mmc/host/mtk-mmc/dbg.h\n create mode 100644 drivers/mmc/host/mtk-mmc/mt6575_sd.h\n create mode 100644 drivers/mmc/host/mtk-mmc/sd.c\n\n--- a/drivers/mmc/host/Kconfig\n+++ b/drivers/mmc/host/Kconfig\n@@ -1091,3 +1091,5 @@ config MMC_OWL\n \n config MMC_SDHCI_EXTERNAL_DMA\n \tbool\n+\n+source \"drivers/mmc/host/mtk-mmc/Kconfig\"\n--- a/drivers/mmc/host/Makefile\n+++ b/drivers/mmc/host/Makefile\n@@ -3,6 +3,7 @@\n # Makefile for MMC/SD host controller drivers\n #\n \n+obj-$(CONFIG_MTK_MMC) \t\t+= mtk-mmc/\n obj-$(CONFIG_MMC_ARMMMCI) += armmmci.o\n armmmci-y := mmci.o\n armmmci-$(CONFIG_MMC_QCOM_DML) += mmci_qcom_dml.o\n"
  },
  {
    "path": "target/linux/ramips/patches-5.15/835-asoc-add-mt7620-support.patch",
    "content": "From 7f29222b1731e8182ba94a331531dec18865a1e4 Mon Sep 17 00:00:00 2001\nFrom: John Crispin <blogic@openwrt.org>\nDate: Sun, 27 Jul 2014 09:31:47 +0100\nSubject: [PATCH 48/53] asoc: add mt7620 support\n\nSigned-off-by: John Crispin <blogic@openwrt.org>\n---\n arch/mips/ralink/of.c            |    2 +\n sound/soc/Kconfig                |    1 +\n sound/soc/Makefile               |    1 +\n sound/soc/ralink/Kconfig         |   15 ++\n sound/soc/ralink/Makefile        |   11 +\n sound/soc/ralink/mt7620-i2s.c    |  436 ++++++++++++++++++++++++++++++++++++++\n sound/soc/ralink/mt7620-wm8960.c |  233 ++++++++++++++++++++\n 7 files changed, 699 insertions(+)\n create mode 100644 sound/soc/ralink/Kconfig\n create mode 100644 sound/soc/ralink/Makefile\n create mode 100644 sound/soc/ralink/mt7620-i2s.c\n create mode 100644 sound/soc/ralink/mt7620-wm8960.c\n\n--- a/sound/soc/Kconfig\n+++ b/sound/soc/Kconfig\n@@ -78,6 +78,7 @@ source \"sound/soc/mxs/Kconfig\"\n source \"sound/soc/pxa/Kconfig\"\n source \"sound/soc/qcom/Kconfig\"\n source \"sound/soc/rockchip/Kconfig\"\n+source \"sound/soc/ralink/Kconfig\"\n source \"sound/soc/samsung/Kconfig\"\n source \"sound/soc/sh/Kconfig\"\n source \"sound/soc/sof/Kconfig\"\n--- a/sound/soc/Makefile\n+++ b/sound/soc/Makefile\n@@ -48,6 +48,7 @@ obj-$(CONFIG_SND_SOC)\t+= kirkwood/\n obj-$(CONFIG_SND_SOC)\t+= pxa/\n obj-$(CONFIG_SND_SOC)\t+= qcom/\n obj-$(CONFIG_SND_SOC)\t+= rockchip/\n+obj-$(CONFIG_SND_SOC)\t+= ralink/\n obj-$(CONFIG_SND_SOC)\t+= samsung/\n obj-$(CONFIG_SND_SOC)\t+= sh/\n obj-$(CONFIG_SND_SOC)\t+= sof/\n--- /dev/null\n+++ b/sound/soc/ralink/Kconfig\n@@ -0,0 +1,8 @@\n+config SND_RALINK_SOC_I2S\n+\tdepends on RALINK && SND_SOC && !SOC_RT288X\n+\tselect SND_SOC_GENERIC_DMAENGINE_PCM\n+\tselect REGMAP_MMIO\n+\ttristate \"SoC Audio (I2S protocol) for Ralink SoC\"\n+\thelp\n+\t  Say Y if you want to use I2S protocol and I2S codec on Ralink/MediaTek\n+\t  based boards.\n--- /dev/null\n+++ b/sound/soc/ralink/Makefile\n@@ -0,0 +1,6 @@\n+#\n+# Ralink/MediaTek Platform Support\n+#\n+snd-soc-ralink-i2s-objs := ralink-i2s.o\n+\n+obj-$(CONFIG_SND_RALINK_SOC_I2S) += snd-soc-ralink-i2s.o\n--- /dev/null\n+++ b/sound/soc/ralink/ralink-i2s.c\n@@ -0,0 +1,966 @@\n+/*\n+ *  Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>\n+ *  Copyright (C) 2016 Michael Lee <igvtee@gmail.com>\n+ *\n+ *  This program is free software; you can redistribute it and/or modify it\n+ *  under  the terms of the GNU General  Public License as published by the\n+ *  Free Software Foundation;  either version 2 of the License, or (at your\n+ *  option) any later version.\n+ *\n+ *  You should have received a copy of the GNU General Public License along\n+ *  with this program; if not, write to the Free Software Foundation, Inc.,\n+ *  675 Mass Ave, Cambridge, MA 02139, USA.\n+ *\n+ */\n+\n+#include <linux/module.h>\n+#include <linux/platform_device.h>\n+#include <linux/clk.h>\n+#include <linux/regmap.h>\n+#include <linux/reset.h>\n+#include <linux/debugfs.h>\n+#include <linux/of_device.h>\n+#include <sound/pcm_params.h>\n+#include <sound/dmaengine_pcm.h>\n+\n+#include <asm/mach-ralink/ralink_regs.h>\n+\n+#define DRV_NAME \"ralink-i2s\"\n+\n+#define I2S_REG_CFG0\t\t0x00\n+#define I2S_REG_INT_STATUS\t0x04\n+#define I2S_REG_INT_EN\t\t0x08\n+#define I2S_REG_FF_STATUS\t0x0c\n+#define I2S_REG_WREG\t\t0x10\n+#define I2S_REG_RREG\t\t0x14\n+#define I2S_REG_CFG1\t\t0x18\n+#define I2S_REG_DIVCMP\t\t0x20\n+#define I2S_REG_DIVINT\t\t0x24\n+\n+/* I2S_REG_CFG0 */\n+#define I2S_REG_CFG0_EN\t\tBIT(31)\n+#define I2S_REG_CFG0_DMA_EN\tBIT(30)\n+#define I2S_REG_CFG0_BYTE_SWAP\tBIT(28)\n+#define I2S_REG_CFG0_TX_EN\tBIT(24)\n+#define I2S_REG_CFG0_RX_EN\tBIT(20)\n+#define I2S_REG_CFG0_SLAVE\tBIT(16)\n+#define I2S_REG_CFG0_RX_THRES\t12\n+#define I2S_REG_CFG0_TX_THRES\t4\n+#define I2S_REG_CFG0_THRES_MASK\t(0xf << I2S_REG_CFG0_RX_THRES) | \\\n+\t(4 << I2S_REG_CFG0_TX_THRES)\n+#define I2S_REG_CFG0_DFT_THRES\t(4 << I2S_REG_CFG0_RX_THRES) | \\\n+\t(4 << I2S_REG_CFG0_TX_THRES)\n+/* RT305x */\n+#define I2S_REG_CFG0_CLK_DIS\tBIT(8)\n+#define I2S_REG_CFG0_TXCH_SWAP\tBIT(3)\n+#define I2S_REG_CFG0_TXCH1_OFF\tBIT(2)\n+#define I2S_REG_CFG0_TXCH0_OFF\tBIT(1)\n+#define I2S_REG_CFG0_SLAVE_EN\tBIT(0)\n+/* RT3883 */\n+#define I2S_REG_CFG0_RXCH_SWAP\tBIT(11)\n+#define I2S_REG_CFG0_RXCH1_OFF\tBIT(10)\n+#define I2S_REG_CFG0_RXCH0_OFF\tBIT(9)\n+#define I2S_REG_CFG0_WS_INV\tBIT(0)\n+/* MT7628 */\n+#define I2S_REG_CFG0_FMT_LE\tBIT(29)\n+#define I2S_REG_CFG0_SYS_BE\tBIT(28)\n+#define I2S_REG_CFG0_NORM_24\tBIT(18)\n+#define I2S_REG_CFG0_DATA_24\tBIT(17)\n+\n+/* I2S_REG_INT_STATUS */\n+#define I2S_REG_INT_RX_FAULT\tBIT(7)\n+#define I2S_REG_INT_RX_OVRUN\tBIT(6)\n+#define I2S_REG_INT_RX_UNRUN\tBIT(5)\n+#define I2S_REG_INT_RX_THRES\tBIT(4)\n+#define I2S_REG_INT_TX_FAULT\tBIT(3)\n+#define I2S_REG_INT_TX_OVRUN\tBIT(2)\n+#define I2S_REG_INT_TX_UNRUN\tBIT(1)\n+#define I2S_REG_INT_TX_THRES\tBIT(0)\n+#define I2S_REG_INT_TX_MASK\t0xf\n+#define I2S_REG_INT_RX_MASK\t0xf0\n+\n+/* I2S_REG_INT_STATUS */\n+#define I2S_RX_AVCNT(x)\t\t((x >> 4) & 0xf)\n+#define I2S_TX_AVCNT(x)\t\t(x & 0xf)\n+/* MT7628 */\n+#define MT7628_I2S_RX_AVCNT(x)\t((x >> 8) & 0x1f)\n+#define MT7628_I2S_TX_AVCNT(x)\t(x & 0x1f)\n+\n+/* I2S_REG_CFG1 */\n+#define I2S_REG_CFG1_LBK\tBIT(31)\n+#define I2S_REG_CFG1_EXTLBK\tBIT(30)\n+/* RT3883 */\n+#define I2S_REG_CFG1_LEFT_J\tBIT(0)\n+#define I2S_REG_CFG1_RIGHT_J\tBIT(1)\n+#define I2S_REG_CFG1_FMT_MASK\t0x3\n+\n+/* I2S_REG_DIVCMP */\n+#define I2S_REG_DIVCMP_CLKEN\tBIT(31)\n+#define I2S_REG_DIVCMP_DIVCOMP_MASK\t0x1ff\n+\n+/* I2S_REG_DIVINT */\n+#define I2S_REG_DIVINT_MASK\t0x3ff\n+\n+/* BCLK dividers */\n+#define RALINK_I2S_DIVCMP\t0\n+#define RALINK_I2S_DIVINT\t1\n+\n+/* FIFO */\n+#define RALINK_I2S_FIFO_SIZE\t32\n+\n+/* feature flags */\n+#define RALINK_FLAGS_TXONLY\tBIT(0)\n+#define RALINK_FLAGS_LEFT_J\tBIT(1)\n+#define RALINK_FLAGS_RIGHT_J\tBIT(2)\n+#define RALINK_FLAGS_ENDIAN\tBIT(3)\n+#define RALINK_FLAGS_24BIT\tBIT(4)\n+\n+#define RALINK_I2S_INT_EN\t0\n+\n+struct ralink_i2s_stats {\n+\tu32 dmafault;\n+\tu32 overrun;\n+\tu32 underrun;\n+\tu32 belowthres;\n+};\n+\n+struct ralink_i2s {\n+\tstruct device *dev;\n+\tvoid __iomem *regs;\n+\tstruct clk *clk;\n+\tstruct regmap *regmap;\n+\tu32 flags;\n+\tunsigned int fmt;\n+\tu16 txdma_req;\n+\tu16 rxdma_req;\n+\n+\tstruct snd_dmaengine_dai_dma_data playback_dma_data;\n+\tstruct snd_dmaengine_dai_dma_data capture_dma_data;\n+\n+\tstruct dentry *dbg_dir;\n+        struct dentry *dbg_stats;\n+\tstruct ralink_i2s_stats txstats;\n+\tstruct ralink_i2s_stats rxstats;\n+};\n+\n+static void ralink_i2s_dump_regs(struct ralink_i2s *i2s)\n+{\n+\tu32 buf[10];\n+\tint ret;\n+\n+\tret = regmap_bulk_read(i2s->regmap, I2S_REG_CFG0,\n+\t\t\tbuf, ARRAY_SIZE(buf));\n+\n+\tdev_dbg(i2s->dev, \"CFG0: %08x, INTSTAT: %08x, INTEN: %08x, \" \\\n+\t\t\t\"FFSTAT: %08x, WREG: %08x, RREG: %08x, \" \\\n+\t\t\t\"CFG1: %08x, DIVCMP: %08x, DIVINT: %08x\\n\",\n+\t\t\tbuf[0], buf[1], buf[2], buf[3], buf[4],\n+\t\t\tbuf[5], buf[6], buf[8], buf[9]);\n+}\n+\n+static int ralink_i2s_set_sysclk(struct snd_soc_dai *dai,\n+                              int clk_id, unsigned int freq, int dir)\n+{\n+\treturn 0;\n+}\n+\n+static int ralink_i2s_set_sys_bclk(struct snd_soc_dai *dai, int width, int rate)\n+{\n+\tstruct ralink_i2s *i2s = snd_soc_dai_get_drvdata(dai);\n+\tunsigned long clk = clk_get_rate(i2s->clk);\n+\tint div;\n+\tuint32_t data;\n+\n+\t/* disable clock at slave mode */\n+\tif ((i2s->fmt & SND_SOC_DAIFMT_MASTER_MASK) ==\n+\t\t\tSND_SOC_DAIFMT_CBM_CFM) {\n+\t\tregmap_update_bits(i2s->regmap, I2S_REG_CFG0,\n+\t\t\t\tI2S_REG_CFG0_CLK_DIS,\n+\t\t\t\tI2S_REG_CFG0_CLK_DIS);\n+\t\treturn 0;\n+\t}\n+\n+\t/* FREQOUT = FREQIN / (I2S_CLK_DIV + 1) */\n+\tdiv = (clk / rate ) - 1;\n+\n+\tdata = rt_sysc_r32(0x30);\n+\tdata &= (0xff << 8);\n+\tdata |= (0x1 << 15) | (div << 8);\n+\trt_sysc_w32(data, 0x30);\n+\n+\t/* enable clock */\n+\tregmap_update_bits(i2s->regmap, I2S_REG_CFG0, I2S_REG_CFG0_CLK_DIS, 0);\n+\n+\tdev_dbg(i2s->dev, \"clk: %lu, rate: %u, div: %d\\n\",\n+\t\t\tclk, rate, div);\n+\n+\treturn 0;\n+}\n+\n+static int ralink_i2s_set_bclk(struct snd_soc_dai *dai, int width, int rate)\n+{\n+\tstruct ralink_i2s *i2s = snd_soc_dai_get_drvdata(dai);\n+\tunsigned long clk = clk_get_rate(i2s->clk);\n+\tint divint, divcomp;\n+\n+\t/* disable clock at slave mode */\n+\tif ((i2s->fmt & SND_SOC_DAIFMT_MASTER_MASK) ==\n+\t\t\tSND_SOC_DAIFMT_CBM_CFM) {\n+\t\tregmap_update_bits(i2s->regmap, I2S_REG_DIVCMP,\n+\t\t\t\tI2S_REG_DIVCMP_CLKEN, 0);\n+\t\treturn 0;\n+\t}\n+\n+\t/* FREQOUT = FREQIN * (1/2) * (1/(DIVINT + DIVCOMP/512)) */\n+\tclk = clk / (2 * 2 * width);\n+\tdivint = clk / rate;\n+\tdivcomp = ((clk % rate) * 512) / rate;\n+\n+\tif ((divint > I2S_REG_DIVINT_MASK) ||\n+\t\t\t(divcomp > I2S_REG_DIVCMP_DIVCOMP_MASK))\n+\t\treturn -EINVAL;\n+\n+\tregmap_update_bits(i2s->regmap, I2S_REG_DIVINT,\n+\t\t\tI2S_REG_DIVINT_MASK, divint);\n+\tregmap_update_bits(i2s->regmap, I2S_REG_DIVCMP,\n+\t\t\tI2S_REG_DIVCMP_DIVCOMP_MASK, divcomp);\n+\n+\t/* enable clock */\n+\tregmap_update_bits(i2s->regmap, I2S_REG_DIVCMP, I2S_REG_DIVCMP_CLKEN,\n+\t\t\tI2S_REG_DIVCMP_CLKEN);\n+\n+\tdev_dbg(i2s->dev, \"clk: %lu, rate: %u, int: %d, comp: %d\\n\",\n+\t\t\tclk_get_rate(i2s->clk), rate, divint, divcomp);\n+\n+\treturn 0;\n+}\n+\n+static int ralink_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)\n+{\n+\tstruct ralink_i2s *i2s = snd_soc_dai_get_drvdata(dai);\n+\tunsigned int cfg0 = 0, cfg1 = 0;\n+\n+\t/* set master/slave audio interface */\n+\tswitch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {\n+\tcase SND_SOC_DAIFMT_CBM_CFM:\n+\t\tif (i2s->flags & RALINK_FLAGS_TXONLY)\n+\t\t\tcfg0 |= I2S_REG_CFG0_SLAVE_EN;\n+\t\telse\n+\t\t\tcfg0 |= I2S_REG_CFG0_SLAVE;\n+\t\tbreak;\n+\tcase SND_SOC_DAIFMT_CBS_CFS:\n+\t\tbreak;\n+\tdefault:\n+\t\treturn -EINVAL;\n+\t}\n+\n+\t/* interface format */\n+\tswitch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {\n+\tcase SND_SOC_DAIFMT_I2S:\n+\t\tbreak;\n+\tcase SND_SOC_DAIFMT_RIGHT_J:\n+\t\tif (i2s->flags & RALINK_FLAGS_RIGHT_J) {\n+\t\t\tcfg1 |= I2S_REG_CFG1_RIGHT_J;\n+\t\t\tbreak;\n+\t\t}\n+\t\treturn -EINVAL;\n+\tcase SND_SOC_DAIFMT_LEFT_J:\n+\t\tif (i2s->flags & RALINK_FLAGS_LEFT_J) {\n+\t\t\tcfg1 |= I2S_REG_CFG1_LEFT_J;\n+\t\t\tbreak;\n+\t\t}\n+\t\treturn -EINVAL;\n+\tdefault:\n+\t\treturn -EINVAL;\n+\t}\n+\n+\t/* clock inversion */\n+\tswitch (fmt & SND_SOC_DAIFMT_INV_MASK) {\n+\tcase SND_SOC_DAIFMT_NB_NF:\n+\t\tbreak;\n+\tdefault:\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (i2s->flags & RALINK_FLAGS_TXONLY) {\n+\t\tregmap_update_bits(i2s->regmap, I2S_REG_CFG0,\n+\t\t\t\tI2S_REG_CFG0_SLAVE_EN, cfg0);\n+\t} else {\n+\t\tregmap_update_bits(i2s->regmap, I2S_REG_CFG0,\n+\t\t\t\tI2S_REG_CFG0_SLAVE, cfg0);\n+\t}\n+\tregmap_update_bits(i2s->regmap, I2S_REG_CFG1,\n+\t\t\tI2S_REG_CFG1_FMT_MASK, cfg1);\n+\ti2s->fmt = fmt;\n+\n+\treturn 0;\n+}\n+\n+static int ralink_i2s_startup(struct snd_pcm_substream *substream,\n+\t\tstruct snd_soc_dai *dai)\n+{\n+\tstruct ralink_i2s *i2s = snd_soc_dai_get_drvdata(dai);\n+\n+\tif (snd_soc_dai_active(dai))\n+\t\treturn 0;\n+\n+\t/* setup status interrupt */\n+#if (RALINK_I2S_INT_EN)\n+\tregmap_write(i2s->regmap, I2S_REG_INT_EN, 0xff);\n+#else\n+\tregmap_write(i2s->regmap, I2S_REG_INT_EN, 0x0);\n+#endif\n+\n+\t/* enable */\n+\tregmap_update_bits(i2s->regmap, I2S_REG_CFG0,\n+\t\t\tI2S_REG_CFG0_EN | I2S_REG_CFG0_DMA_EN |\n+\t\t\tI2S_REG_CFG0_THRES_MASK,\n+\t\t\tI2S_REG_CFG0_EN | I2S_REG_CFG0_DMA_EN |\n+\t\t\tI2S_REG_CFG0_DFT_THRES);\n+\n+\treturn 0;\n+}\n+\n+static void ralink_i2s_shutdown(struct snd_pcm_substream *substream,\n+\t\tstruct snd_soc_dai *dai)\n+{\n+\tstruct ralink_i2s *i2s = snd_soc_dai_get_drvdata(dai);\n+\n+\t/* If both streams are stopped, disable module and clock */\n+\tif (snd_soc_dai_active(dai))\n+\t\treturn;\n+\n+\t/*\n+\t * datasheet mention when disable all control regs are cleared\n+\t * to initial values. need reinit at startup.\n+\t */\n+\tregmap_update_bits(i2s->regmap, I2S_REG_CFG0, I2S_REG_CFG0_EN, 0);\n+}\n+\n+static int ralink_i2s_hw_params(struct snd_pcm_substream *substream,\n+\t\tstruct snd_pcm_hw_params *params, struct snd_soc_dai *dai)\n+{\n+\tstruct ralink_i2s *i2s = snd_soc_dai_get_drvdata(dai);\n+\tint width;\n+\tint ret;\n+\n+\twidth = params_width(params);\n+\tswitch (width) {\n+\tcase 16:\n+\t\tif (i2s->flags & RALINK_FLAGS_24BIT)\n+\t\t\tregmap_update_bits(i2s->regmap, I2S_REG_CFG0,\n+\t\t\t\t\tI2S_REG_CFG0_DATA_24, 0);\n+\t\tbreak;\n+\tcase 24:\n+\t\tif (i2s->flags & RALINK_FLAGS_24BIT) {\n+\t\t\tregmap_update_bits(i2s->regmap, I2S_REG_CFG0,\n+\t\t\t\t\tI2S_REG_CFG0_DATA_24,\n+\t\t\t\t\tI2S_REG_CFG0_DATA_24);\n+\t\t\tbreak;\n+\t\t}\n+\t\treturn -EINVAL;\n+\tdefault:\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tswitch (params_channels(params)) {\n+\tcase 2:\n+\t\tbreak;\n+\tdefault:\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (i2s->flags & RALINK_FLAGS_ENDIAN) {\n+\t\t/* system endian */\n+#ifdef SNDRV_LITTLE_ENDIAN\n+\t\tregmap_update_bits(i2s->regmap, I2S_REG_CFG0,\n+\t\t\t\tI2S_REG_CFG0_SYS_BE, 0);\n+#else\n+\t\tregmap_update_bits(i2s->regmap, I2S_REG_CFG0,\n+\t\t\t\tI2S_REG_CFG0_SYS_BE,\n+\t\t\t\tI2S_REG_CFG0_SYS_BE);\n+#endif\n+\n+\t\t/* data endian */\n+\t\tswitch (params_format(params)) {\n+\t\tcase SNDRV_PCM_FORMAT_S16_LE:\n+\t\tcase SNDRV_PCM_FORMAT_S24_LE:\n+\t\t\tregmap_update_bits(i2s->regmap, I2S_REG_CFG0,\n+\t\t\t\t\tI2S_REG_CFG0_FMT_LE,\n+\t\t\t\t\tI2S_REG_CFG0_FMT_LE);\n+\t\t\tbreak;\n+\t\tcase SNDRV_PCM_FORMAT_S16_BE:\n+\t\tcase SNDRV_PCM_FORMAT_S24_BE:\n+\t\t\tregmap_update_bits(i2s->regmap, I2S_REG_CFG0,\n+\t\t\t\t\tI2S_REG_CFG0_FMT_LE, 0);\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t}\n+\n+\t/* setup bclk rate */\n+\tif (i2s->flags & RALINK_FLAGS_TXONLY)\n+\t\tret = ralink_i2s_set_sys_bclk(dai, width, params_rate(params));\n+\telse\n+\t\tret = ralink_i2s_set_bclk(dai, width, params_rate(params));\n+\n+\treturn ret;\n+}\n+\n+static int ralink_i2s_trigger(struct snd_pcm_substream *substream, int cmd,\n+\t\tstruct snd_soc_dai *dai)\n+{\n+\tstruct ralink_i2s *i2s = snd_soc_dai_get_drvdata(dai);\n+\tunsigned int mask, val;\n+\n+\tif (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)\n+\t\tmask = I2S_REG_CFG0_TX_EN;\n+\telse\n+\t\tmask = I2S_REG_CFG0_RX_EN;\n+\n+\tswitch (cmd) {\n+\tcase SNDRV_PCM_TRIGGER_START:\n+\tcase SNDRV_PCM_TRIGGER_RESUME:\n+\tcase SNDRV_PCM_TRIGGER_PAUSE_RELEASE:\n+\t\tval = mask;\n+\t\tbreak;\n+\tcase SNDRV_PCM_TRIGGER_STOP:\n+\tcase SNDRV_PCM_TRIGGER_SUSPEND:\n+\tcase SNDRV_PCM_TRIGGER_PAUSE_PUSH:\n+\t\tval = 0;\n+\t\tbreak;\n+\tdefault:\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tregmap_update_bits(i2s->regmap, I2S_REG_CFG0, mask, val);\n+\n+\treturn 0;\n+}\n+\n+static void ralink_i2s_init_dma_data(struct ralink_i2s *i2s,\n+\t\tstruct resource *res)\n+{\n+\tstruct snd_dmaengine_dai_dma_data *dma_data;\n+\n+\t/* Playback */\n+\tdma_data = &i2s->playback_dma_data;\n+\tdma_data->addr = res->start + I2S_REG_WREG;\n+\tdma_data->addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;\n+\tdma_data->maxburst = 1;\n+\tdma_data->slave_id = i2s->txdma_req;\n+\n+\tif (i2s->flags & RALINK_FLAGS_TXONLY)\n+\t\treturn;\n+\n+\t/* Capture */\n+\tdma_data = &i2s->capture_dma_data;\n+\tdma_data->addr = res->start + I2S_REG_RREG;\n+\tdma_data->addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;\n+\tdma_data->maxburst = 1;\n+\tdma_data->slave_id = i2s->rxdma_req;\n+}\n+\n+static int ralink_i2s_dai_probe(struct snd_soc_dai *dai)\n+{\n+\tstruct ralink_i2s *i2s = snd_soc_dai_get_drvdata(dai);\n+\n+\tsnd_soc_dai_init_dma_data(dai, &i2s->playback_dma_data,\n+\t\t\t&i2s->capture_dma_data);\n+\n+\treturn 0;\n+}\n+\n+static int ralink_i2s_dai_remove(struct snd_soc_dai *dai)\n+{\n+\treturn 0;\n+}\n+\n+static const struct snd_soc_dai_ops ralink_i2s_dai_ops = {\n+\t.set_sysclk = ralink_i2s_set_sysclk,\n+\t.set_fmt = ralink_i2s_set_fmt,\n+\t.startup = ralink_i2s_startup,\n+\t.shutdown = ralink_i2s_shutdown,\n+\t.hw_params = ralink_i2s_hw_params,\n+\t.trigger = ralink_i2s_trigger,\n+};\n+\n+static struct snd_soc_dai_driver ralink_i2s_dai = {\n+\t.name = DRV_NAME,\n+\t.probe = ralink_i2s_dai_probe,\n+\t.remove = ralink_i2s_dai_remove,\n+\t.ops = &ralink_i2s_dai_ops,\n+\t.capture = {\n+\t\t.stream_name = \"I2S Capture\",\n+\t\t.channels_min = 2,\n+\t\t.channels_max = 2,\n+\t\t.rate_min = 5512,\n+\t\t.rate_max = 192000,\n+\t\t.rates = SNDRV_PCM_RATE_CONTINUOUS,\n+\t\t.formats = SNDRV_PCM_FMTBIT_S16_LE,\n+\t},\n+\t.playback = {\n+\t\t.stream_name = \"I2S Playback\",\n+\t\t.channels_min = 2,\n+\t\t.channels_max = 2,\n+\t\t.rate_min = 5512,\n+\t\t.rate_max = 192000,\n+\t\t.rates = SNDRV_PCM_RATE_CONTINUOUS,\n+\t\t.formats = SNDRV_PCM_FMTBIT_S16_LE,\n+\t},\n+\t.symmetric_rate = 1,\n+};\n+\n+static struct snd_pcm_hardware ralink_pcm_hardware = {\n+\t.info = SNDRV_PCM_INFO_MMAP |\n+\t\tSNDRV_PCM_INFO_MMAP_VALID |\n+\t\tSNDRV_PCM_INFO_INTERLEAVED |\n+\t\tSNDRV_PCM_INFO_BLOCK_TRANSFER,\n+\t.formats = SNDRV_PCM_FMTBIT_S16_LE,\n+\t.channels_min\t\t= 2,\n+\t.channels_max\t\t= 2,\n+\t.period_bytes_min\t= PAGE_SIZE,\n+\t.period_bytes_max\t= PAGE_SIZE * 2,\n+\t.periods_min\t\t= 2,\n+\t.periods_max\t\t= 128,\n+\t.buffer_bytes_max\t= 128 * 1024,\n+\t.fifo_size\t\t= RALINK_I2S_FIFO_SIZE,\n+};\n+\n+static const struct snd_dmaengine_pcm_config ralink_dmaengine_pcm_config = {\n+\t.prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,\n+\t.pcm_hardware = &ralink_pcm_hardware,\n+\t.prealloc_buffer_size = 256 * PAGE_SIZE,\n+};\n+\n+static const struct snd_soc_component_driver ralink_i2s_component = {\n+\t.name = DRV_NAME,\n+};\n+\n+static bool ralink_i2s_readable_reg(struct device *dev, unsigned int reg)\n+{\n+\treturn true;\n+}\n+\n+static bool ralink_i2s_volatile_reg(struct device *dev, unsigned int reg)\n+{\n+\tswitch (reg) {\n+\tcase I2S_REG_INT_STATUS:\n+\tcase I2S_REG_FF_STATUS:\n+\t\treturn true;\n+\t}\n+\treturn false;\n+}\n+\n+static bool ralink_i2s_writeable_reg(struct device *dev, unsigned int reg)\n+{\n+\tswitch (reg) {\n+\tcase I2S_REG_FF_STATUS:\n+\tcase I2S_REG_RREG:\n+\t\treturn false;\n+\t}\n+\treturn true;\n+}\n+\n+static const struct regmap_config ralink_i2s_regmap_config = {\n+\t.reg_bits = 32,\n+\t.reg_stride = 4,\n+\t.val_bits = 32,\n+\t.writeable_reg = ralink_i2s_writeable_reg,\n+\t.readable_reg = ralink_i2s_readable_reg,\n+\t.volatile_reg = ralink_i2s_volatile_reg,\n+\t.max_register = I2S_REG_DIVINT,\n+};\n+\n+#if (RALINK_I2S_INT_EN)\n+static irqreturn_t ralink_i2s_irq(int irq, void *devid)\n+{\n+\tstruct ralink_i2s *i2s = devid;\n+\tu32 status;\n+\n+\tregmap_read(i2s->regmap, I2S_REG_INT_STATUS, &status);\n+\tif (unlikely(!status))\n+\t\treturn IRQ_NONE;\n+\n+\t/* tx stats */\n+\tif (status & I2S_REG_INT_TX_MASK) {\n+\t\tif (status & I2S_REG_INT_TX_THRES)\n+\t\t\ti2s->txstats.belowthres++;\n+\t\tif (status & I2S_REG_INT_TX_UNRUN)\n+\t\t\ti2s->txstats.underrun++;\n+\t\tif (status & I2S_REG_INT_TX_OVRUN)\n+\t\t\ti2s->txstats.overrun++;\n+\t\tif (status & I2S_REG_INT_TX_FAULT)\n+\t\t\ti2s->txstats.dmafault++;\n+\t}\n+\n+\t/* rx stats */\n+\tif (status & I2S_REG_INT_RX_MASK) {\n+\t\tif (status & I2S_REG_INT_RX_THRES)\n+\t\t\ti2s->rxstats.belowthres++;\n+\t\tif (status & I2S_REG_INT_RX_UNRUN)\n+\t\t\ti2s->rxstats.underrun++;\n+\t\tif (status & I2S_REG_INT_RX_OVRUN)\n+\t\t\ti2s->rxstats.overrun++;\n+\t\tif (status & I2S_REG_INT_RX_FAULT)\n+\t\t\ti2s->rxstats.dmafault++;\n+\t}\n+\n+\t/* clean status bits */\n+\tregmap_write(i2s->regmap, I2S_REG_INT_STATUS, status);\n+\n+\treturn IRQ_HANDLED;\n+}\n+#endif\n+\n+#if IS_ENABLED(CONFIG_DEBUG_FS)\n+static int ralink_i2s_stats_show(struct seq_file *s, void *unused)\n+{\n+        struct ralink_i2s *i2s = s->private;\n+\n+\tseq_printf(s, \"tx stats\\n\");\n+\tseq_printf(s, \"\\tbelow threshold\\t%u\\n\", i2s->txstats.belowthres);\n+\tseq_printf(s, \"\\tunder run\\t%u\\n\", i2s->txstats.underrun);\n+\tseq_printf(s, \"\\tover run\\t%u\\n\", i2s->txstats.overrun);\n+\tseq_printf(s, \"\\tdma fault\\t%u\\n\", i2s->txstats.dmafault);\n+\n+\tseq_printf(s, \"rx stats\\n\");\n+\tseq_printf(s, \"\\tbelow threshold\\t%u\\n\", i2s->rxstats.belowthres);\n+\tseq_printf(s, \"\\tunder run\\t%u\\n\", i2s->rxstats.underrun);\n+\tseq_printf(s, \"\\tover run\\t%u\\n\", i2s->rxstats.overrun);\n+\tseq_printf(s, \"\\tdma fault\\t%u\\n\", i2s->rxstats.dmafault);\n+\n+\tralink_i2s_dump_regs(i2s);\n+\n+\treturn 0;\n+}\n+\n+static int ralink_i2s_stats_open(struct inode *inode, struct file *file)\n+{\n+        return single_open(file, ralink_i2s_stats_show, inode->i_private);\n+}\n+\n+static const struct file_operations ralink_i2s_stats_ops = {\n+        .open = ralink_i2s_stats_open,\n+        .read = seq_read,\n+        .llseek = seq_lseek,\n+        .release = single_release,\n+};\n+\n+static inline int ralink_i2s_debugfs_create(struct ralink_i2s *i2s)\n+{\n+        i2s->dbg_dir = debugfs_create_dir(dev_name(i2s->dev), NULL);\n+        if (!i2s->dbg_dir)\n+                return -ENOMEM;\n+\n+        i2s->dbg_stats = debugfs_create_file(\"stats\", S_IRUGO,\n+                        i2s->dbg_dir, i2s, &ralink_i2s_stats_ops);\n+        if (!i2s->dbg_stats) {\n+                debugfs_remove(i2s->dbg_dir);\n+                return -ENOMEM;\n+        }\n+\n+        return 0;\n+}\n+\n+static inline void ralink_i2s_debugfs_remove(struct ralink_i2s *i2s)\n+{\n+\tdebugfs_remove(i2s->dbg_stats);\n+\tdebugfs_remove(i2s->dbg_dir);\n+}\n+#else\n+static inline int ralink_i2s_debugfs_create(struct ralink_i2s *i2s)\n+{\n+\treturn 0;\n+}\n+\n+static inline void ralink_i2s_debugfs_remove(struct ralink_i2s *i2s)\n+{\n+}\n+#endif\n+\n+/*\n+ * TODO: these refclk setup functions should use\n+ * clock framework instead. hardcode it now.\n+ */\n+static void rt3350_refclk_setup(void)\n+{\n+\tuint32_t data;\n+\n+\t/* set refclk output 12Mhz clock */\n+\tdata = rt_sysc_r32(0x2c);\n+\tdata |= (0x1 << 8);\n+\trt_sysc_w32(data, 0x2c);\n+}\n+\n+static void rt3883_refclk_setup(void)\n+{\n+\tuint32_t data;\n+\n+\t/* set refclk output 12Mhz clock */\n+\tdata = rt_sysc_r32(0x2c);\n+\tdata &= ~(0x3 << 13);\n+\tdata |= (0x1 << 13);\n+\trt_sysc_w32(data, 0x2c);\n+}\n+\n+static void rt3552_refclk_setup(void)\n+{\n+\tuint32_t data;\n+\n+\t/* set refclk output 12Mhz clock */\n+\tdata = rt_sysc_r32(0x2c);\n+\tdata &= ~(0xf << 8);\n+\tdata |= (0x3 << 8);\n+\trt_sysc_w32(data, 0x2c);\n+}\n+\n+static void mt7620_refclk_setup(void)\n+{\n+\tuint32_t data;\n+\n+\t/* set refclk output 12Mhz clock */\n+\tdata = rt_sysc_r32(0x2c);\n+\tdata &= ~(0x7 << 9);\n+\tdata |= 0x1 << 9;\n+\trt_sysc_w32(data, 0x2c);\n+}\n+\n+static void mt7621_refclk_setup(void)\n+{\n+\tuint32_t data;\n+\n+\t/* set refclk output 12Mhz clock */\n+\tdata = rt_sysc_r32(0x2c);\n+\tdata &= ~(0x1f << 18);\n+\tdata |= (0x19 << 18);\n+\tdata &= ~(0x1f << 12);\n+\tdata |= (0x1 << 12);\n+\tdata &= ~(0x7 << 9);\n+\tdata |= (0x5 << 9);\n+\trt_sysc_w32(data, 0x2c);\n+}\n+\n+static void mt7628_refclk_setup(void)\n+{\n+\tuint32_t data;\n+\n+\t/* set i2s and refclk digital pad */\n+\tdata = rt_sysc_r32(0x3c);\n+\tdata |= 0x1f;\n+\trt_sysc_w32(data, 0x3c);\n+\n+\t/* Adjust REFCLK0's driving strength */\n+\tdata = rt_sysc_r32(0x1354);\n+\tdata &= ~(0x1 << 5);\n+\trt_sysc_w32(data, 0x1354);\n+\tdata = rt_sysc_r32(0x1364);\n+\tdata |= ~(0x1 << 5);\n+\trt_sysc_w32(data, 0x1364);\n+\n+\t/* set refclk output 12Mhz clock */\n+\tdata = rt_sysc_r32(0x2c);\n+\tdata &= ~(0x7 << 9);\n+\tdata |= 0x1 << 9;\n+\trt_sysc_w32(data, 0x2c);\n+}\n+\n+struct rt_i2s_data {\n+\tu32 flags;\n+\tvoid (*refclk_setup)(void);\n+};\n+\n+struct rt_i2s_data rt3050_i2s_data = { .flags = RALINK_FLAGS_TXONLY };\n+struct rt_i2s_data rt3350_i2s_data = { .flags = RALINK_FLAGS_TXONLY,\n+\t.refclk_setup = rt3350_refclk_setup };\n+struct rt_i2s_data rt3883_i2s_data = {\n+\t.flags = (RALINK_FLAGS_LEFT_J | RALINK_FLAGS_RIGHT_J),\n+\t.refclk_setup = rt3883_refclk_setup };\n+struct rt_i2s_data rt3352_i2s_data = { .refclk_setup = rt3552_refclk_setup};\n+struct rt_i2s_data mt7620_i2s_data = { .refclk_setup = mt7620_refclk_setup};\n+struct rt_i2s_data mt7621_i2s_data = { .refclk_setup = mt7621_refclk_setup};\n+struct rt_i2s_data mt7628_i2s_data = {\n+\t.flags = (RALINK_FLAGS_ENDIAN | RALINK_FLAGS_24BIT |\n+\t\t\tRALINK_FLAGS_LEFT_J),\n+\t.refclk_setup = mt7628_refclk_setup};\n+\n+static const struct of_device_id ralink_i2s_match_table[] = {\n+\t{ .compatible = \"ralink,rt3050-i2s\",\n+\t\t.data = (void *)&rt3050_i2s_data },\n+\t{ .compatible = \"ralink,rt3350-i2s\",\n+\t\t.data = (void *)&rt3350_i2s_data },\n+\t{ .compatible = \"ralink,rt3883-i2s\",\n+\t\t.data = (void *)&rt3883_i2s_data },\n+\t{ .compatible = \"ralink,rt3352-i2s\",\n+\t\t.data = (void *)&rt3352_i2s_data },\n+\t{ .compatible = \"mediatek,mt7620-i2s\",\n+\t\t.data = (void *)&mt7620_i2s_data },\n+\t{ .compatible = \"mediatek,mt7621-i2s\",\n+\t\t.data = (void *)&mt7621_i2s_data },\n+\t{ .compatible = \"mediatek,mt7628-i2s\",\n+\t\t.data = (void *)&mt7628_i2s_data },\n+\t{},\n+};\n+MODULE_DEVICE_TABLE(of, ralink_i2s_match_table);\n+\n+static int ralink_i2s_probe(struct platform_device *pdev)\n+{\n+\tconst struct of_device_id *match;\n+\tstruct device_node *np = pdev->dev.of_node;\n+\tstruct ralink_i2s *i2s;\n+\tstruct resource *res;\n+\tint irq, ret;\n+\tu32 dma_req;\n+\tstruct rt_i2s_data *data;\n+\n+\ti2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);\n+\tif (!i2s)\n+\t\treturn -ENOMEM;\n+\n+\tplatform_set_drvdata(pdev, i2s);\n+\ti2s->dev = &pdev->dev;\n+\n+\tmatch = of_match_device(ralink_i2s_match_table, &pdev->dev);\n+\tif (!match)\n+\t\treturn -EINVAL;\n+\tdata = (struct rt_i2s_data *)match->data;\n+\ti2s->flags = data->flags;\n+\t/* setup out 12Mhz refclk to codec as mclk */\n+\tif (data->refclk_setup)\n+\t\tdata->refclk_setup();\n+\n+\tif (of_property_read_u32(np, \"txdma-req\", &dma_req)) {\n+\t\tdev_err(&pdev->dev, \"no txdma-req define\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\ti2s->txdma_req = (u16)dma_req;\n+\tif (!(i2s->flags & RALINK_FLAGS_TXONLY)) {\n+\t\tif (of_property_read_u32(np, \"rxdma-req\", &dma_req)) {\n+\t\t\tdev_err(&pdev->dev, \"no rxdma-req define\\n\");\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t\ti2s->rxdma_req = (u16)dma_req;\n+\t}\n+\n+\tres = platform_get_resource(pdev, IORESOURCE_MEM, 0);\n+\ti2s->regs = devm_ioremap_resource(&pdev->dev, res);\n+\tif (IS_ERR(i2s->regs))\n+\t\treturn PTR_ERR(i2s->regs);\n+\n+\ti2s->regmap = devm_regmap_init_mmio(&pdev->dev, i2s->regs,\n+\t\t\t&ralink_i2s_regmap_config);\n+\tif (IS_ERR(i2s->regmap)) {\n+\t\tdev_err(&pdev->dev, \"regmap init failed\\n\");\n+\t\treturn PTR_ERR(i2s->regmap);\n+\t}\n+\n+        irq = platform_get_irq(pdev, 0);\n+        if (irq < 0) {\n+                dev_err(&pdev->dev, \"failed to get irq\\n\");\n+                return -EINVAL;\n+        }\n+\n+#if (RALINK_I2S_INT_EN)\n+\tret = devm_request_irq(&pdev->dev, irq, ralink_i2s_irq,\n+\t\t\t0, dev_name(&pdev->dev), i2s);\n+\tif (ret) {\n+\t\tdev_err(&pdev->dev, \"failed to request irq\\n\");\n+\t\treturn ret;\n+\t}\n+#endif\n+\n+\ti2s->clk = devm_clk_get(&pdev->dev, NULL);\n+\tif (IS_ERR(i2s->clk)) {\n+\t\tdev_err(&pdev->dev, \"no clock defined\\n\");\n+\t\treturn PTR_ERR(i2s->clk);\n+\t}\n+\n+\tret = clk_prepare_enable(i2s->clk);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tralink_i2s_init_dma_data(i2s, res);\n+\n+\tdevice_reset(&pdev->dev);\n+\n+\tret = ralink_i2s_debugfs_create(i2s);\n+\tif (ret) {\n+\t\tdev_err(&pdev->dev, \"create debugfs failed\\n\");\n+\t\tgoto err_clk_disable;\n+\t}\n+\n+\t/* enable 24bits support */\n+\tif (i2s->flags & RALINK_FLAGS_24BIT) {\n+\t\tralink_i2s_dai.capture.formats |= SNDRV_PCM_FMTBIT_S24_LE;\n+\t\tralink_i2s_dai.playback.formats |= SNDRV_PCM_FMTBIT_S24_LE;\n+\t}\n+\n+\t/* enable big endian support */\n+\tif (i2s->flags & RALINK_FLAGS_ENDIAN) {\n+\t\tralink_i2s_dai.capture.formats |= SNDRV_PCM_FMTBIT_S16_BE;\n+\t\tralink_i2s_dai.playback.formats |= SNDRV_PCM_FMTBIT_S16_BE;\n+\t\tralink_pcm_hardware.formats |= SNDRV_PCM_FMTBIT_S16_BE;\n+\t\tif (i2s->flags & RALINK_FLAGS_24BIT) {\n+\t\t\tralink_i2s_dai.capture.formats |=\n+\t\t\t\tSNDRV_PCM_FMTBIT_S24_BE;\n+\t\t\tralink_i2s_dai.playback.formats |=\n+\t\t\t\tSNDRV_PCM_FMTBIT_S24_BE;\n+\t\t\tralink_pcm_hardware.formats |=\n+\t\t\t\tSNDRV_PCM_FMTBIT_S24_BE;\n+\t\t}\n+\t}\n+\n+\t/* disable capture support */\n+\tif (i2s->flags & RALINK_FLAGS_TXONLY)\n+\t\tmemset(&ralink_i2s_dai.capture, sizeof(ralink_i2s_dai.capture),\n+\t\t\t\t0);\n+\n+\tret = devm_snd_soc_register_component(&pdev->dev, &ralink_i2s_component,\n+\t\t\t&ralink_i2s_dai, 1);\n+\tif (ret)\n+\t\tgoto err_debugfs;\n+\n+\tret = devm_snd_dmaengine_pcm_register(&pdev->dev,\n+\t\t\t&ralink_dmaengine_pcm_config,\n+\t\t\tSND_DMAENGINE_PCM_FLAG_COMPAT);\n+\tif (ret)\n+\t\tgoto err_debugfs;\n+\n+\tdev_info(i2s->dev, \"mclk %luMHz\\n\", clk_get_rate(i2s->clk) / 1000000);\n+\n+\treturn 0;\n+\n+err_debugfs:\n+\tralink_i2s_debugfs_remove(i2s);\n+\n+err_clk_disable:\n+\tclk_disable_unprepare(i2s->clk);\n+\n+\treturn ret;\n+}\n+\n+static int ralink_i2s_remove(struct platform_device *pdev)\n+{\n+\tstruct ralink_i2s *i2s = platform_get_drvdata(pdev);\n+\n+\tralink_i2s_debugfs_remove(i2s);\n+\tclk_disable_unprepare(i2s->clk);\n+\n+\treturn 0;\n+}\n+\n+static struct platform_driver ralink_i2s_driver = {\n+\t.probe = ralink_i2s_probe,\n+\t.remove = ralink_i2s_remove,\n+\t.driver = {\n+\t\t.name = DRV_NAME,\n+\t\t.of_match_table = ralink_i2s_match_table,\n+\t},\n+};\n+module_platform_driver(ralink_i2s_driver);\n+\n+MODULE_AUTHOR(\"Lars-Peter Clausen, <lars@metafoo.de>\");\n+MODULE_DESCRIPTION(\"Ralink/MediaTek I2S driver\");\n+MODULE_LICENSE(\"GPL\");\n+MODULE_ALIAS(\"platform:\" DRV_NAME);\n"
  },
  {
    "path": "target/linux/ramips/patches-5.15/840-serial-add-ugly-custom-baud-rate-hack.patch",
    "content": "From a7eb46e0ea4a11e4dfb56ab129bf816d1059a6c5 Mon Sep 17 00:00:00 2001\nFrom: John Crispin <blogic@openwrt.org>\nDate: Mon, 7 Dec 2015 17:31:08 +0100\nSubject: [PATCH 51/53] serial: add ugly custom baud rate hack\n\nSigned-off-by: John Crispin <blogic@openwrt.org>\n---\n drivers/tty/serial/serial_core.c |    3 +++\n 1 file changed, 3 insertions(+)\n\n--- a/drivers/tty/serial/serial_core.c\n+++ b/drivers/tty/serial/serial_core.c\n@@ -401,6 +401,9 @@ uart_get_baud_rate(struct uart_port *por\n \t\tbreak;\n \t}\n \n+\tif (tty_termios_baud_rate(termios) == 2500000)\n+\t\treturn 250000;\n+\n \tfor (try = 0; try < 2; try++) {\n \t\tbaud = tty_termios_baud_rate(termios);\n \n"
  },
  {
    "path": "target/linux/ramips/patches-5.15/845-pwm-add-mediatek-support.patch",
    "content": "From fc8f96309c21c1bc3276427309cd7d361347d66e Mon Sep 17 00:00:00 2001\nFrom: John Crispin <blogic@openwrt.org>\nDate: Mon, 7 Dec 2015 17:16:50 +0100\nSubject: [PATCH 52/53] pwm: add mediatek support\n\nSigned-off-by: John Crispin <blogic@openwrt.org>\n---\n drivers/pwm/Kconfig        |    9 +++\n drivers/pwm/Makefile       |    1 +\n drivers/pwm/pwm-mediatek.c |  173 ++++++++++++++++++++++++++++++++++++++++++++\n 3 files changed, 183 insertions(+)\n create mode 100644 drivers/pwm/pwm-mediatek.c\n\n--- a/drivers/pwm/Kconfig\n+++ b/drivers/pwm/Kconfig\n@@ -383,6 +383,15 @@ config PWM_MEDIATEK\n \t  To compile this driver as a module, choose M here: the module\n \t  will be called pwm-mediatek.\n \n+config PWM_MEDIATEK_RAMIPS\n+\ttristate \"Mediatek PWM support\"\n+\tdepends on RALINK && OF\n+\thelp\n+\t  Generic PWM framework driver for Mediatek ARM SoC.\n+\n+\t  To compile this driver as a module, choose M here: the module\n+\t  will be called pwm-mxs.\n+\n config PWM_MXS\n \ttristate \"Freescale MXS PWM support\"\n \tdepends on ARCH_MXS || COMPILE_TEST\n--- a/drivers/pwm/Makefile\n+++ b/drivers/pwm/Makefile\n@@ -33,6 +33,7 @@ obj-$(CONFIG_PWM_LPSS_PCI)\t+= pwm-lpss-p\n obj-$(CONFIG_PWM_LPSS_PLATFORM)\t+= pwm-lpss-platform.o\n obj-$(CONFIG_PWM_MESON)\t\t+= pwm-meson.o\n obj-$(CONFIG_PWM_MEDIATEK)\t+= pwm-mediatek.o\n+obj-$(CONFIG_PWM_MEDIATEK_RAMIPS)\t+= pwm-mediatek-ramips.o\n obj-$(CONFIG_PWM_MTK_DISP)\t+= pwm-mtk-disp.o\n obj-$(CONFIG_PWM_MXS)\t\t+= pwm-mxs.o\n obj-$(CONFIG_PWM_NTXEC)\t\t+= pwm-ntxec.o\n--- /dev/null\n+++ b/drivers/pwm/pwm-mediatek-ramips.c\n@@ -0,0 +1,173 @@\n+/*\n+ * Mediatek Pulse Width Modulator driver\n+ *\n+ * Copyright (C) 2015 John Crispin <blogic@openwrt.org>\n+ *\n+ * This file is licensed under the terms of the GNU General Public\n+ * License version 2. This program is licensed \"as is\" without any\n+ * warranty of any kind, whether express or implied.\n+ */\n+\n+#include <linux/err.h>\n+#include <linux/io.h>\n+#include <linux/ioport.h>\n+#include <linux/kernel.h>\n+#include <linux/module.h>\n+#include <linux/of.h>\n+#include <linux/platform_device.h>\n+#include <linux/pwm.h>\n+#include <linux/slab.h>\n+#include <linux/types.h>\n+\n+#define NUM_PWM\t\t4\n+\n+/* PWM registers and bits definitions */\n+#define PWMCON\t\t\t0x00\n+#define PWMHDUR\t\t\t0x04\n+#define PWMLDUR\t\t\t0x08\n+#define PWMGDUR\t\t\t0x0c\n+#define PWMWAVENUM\t\t0x28\n+#define PWMDWIDTH\t\t0x2c\n+#define PWMTHRES\t\t0x30\n+\n+/**\n+ * struct mtk_pwm_chip - struct representing pwm chip\n+ *\n+ * @mmio_base: base address of pwm chip\n+ * @chip: linux pwm chip representation\n+ */\n+struct mtk_pwm_chip {\n+\tvoid __iomem *mmio_base;\n+\tstruct pwm_chip chip;\n+};\n+\n+static inline struct mtk_pwm_chip *to_mtk_pwm_chip(struct pwm_chip *chip)\n+{\n+\treturn container_of(chip, struct mtk_pwm_chip, chip);\n+}\n+\n+static inline u32 mtk_pwm_readl(struct mtk_pwm_chip *chip, unsigned int num,\n+\t\t\t\t  unsigned long offset)\n+{\n+\treturn ioread32(chip->mmio_base + 0x10 + (num * 0x40) + offset);\n+}\n+\n+static inline void mtk_pwm_writel(struct mtk_pwm_chip *chip,\n+\t\t\t\t    unsigned int num, unsigned long offset,\n+\t\t\t\t    unsigned long val)\n+{\n+\tiowrite32(val, chip->mmio_base + 0x10 + (num * 0x40) + offset);\n+}\n+\n+static int mtk_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,\n+\t\t\t    int duty_ns, int period_ns)\n+{\n+\tstruct mtk_pwm_chip *pc = to_mtk_pwm_chip(chip);\n+\tu32 resolution = 100 / 4;\n+\tu32 clkdiv = 0;\n+\n+\twhile (period_ns / resolution  > 8191) {\n+\t\tclkdiv++;\n+\t\tresolution *= 2;\n+\t}\n+\n+\tif (clkdiv > 7)\n+\t\treturn -1;\n+\n+\tmtk_pwm_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | BIT(3) | clkdiv);\n+\tmtk_pwm_writel(pc, pwm->hwpwm, PWMDWIDTH, period_ns / resolution);\n+\tmtk_pwm_writel(pc, pwm->hwpwm, PWMTHRES, duty_ns / resolution);\n+\treturn 0;\n+}\n+\n+static int mtk_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)\n+{\n+\tstruct mtk_pwm_chip *pc = to_mtk_pwm_chip(chip);\n+\tu32 val;\n+\n+\tval = ioread32(pc->mmio_base);\n+\tval |= BIT(pwm->hwpwm);\n+\tiowrite32(val, pc->mmio_base);\n+\n+\treturn 0;\n+}\n+\n+static void mtk_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)\n+{\n+\tstruct mtk_pwm_chip *pc = to_mtk_pwm_chip(chip);\n+\tu32 val;\n+\n+\tval = ioread32(pc->mmio_base);\n+\tval &= ~BIT(pwm->hwpwm);\n+\tiowrite32(val, pc->mmio_base);\n+}\n+\n+static const struct pwm_ops mtk_pwm_ops = {\n+\t.config = mtk_pwm_config,\n+\t.enable = mtk_pwm_enable,\n+\t.disable = mtk_pwm_disable,\n+\t.owner = THIS_MODULE,\n+};\n+\n+static int mtk_pwm_probe(struct platform_device *pdev)\n+{\n+\tstruct mtk_pwm_chip *pc;\n+\tstruct resource *r;\n+\tint ret;\n+\n+\tpc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);\n+\tif (!pc)\n+\t\treturn -ENOMEM;\n+\n+\tr = platform_get_resource(pdev, IORESOURCE_MEM, 0);\n+\tpc->mmio_base = devm_ioremap_resource(&pdev->dev, r);\n+\tif (IS_ERR(pc->mmio_base))\n+\t\treturn PTR_ERR(pc->mmio_base);\n+\n+\tplatform_set_drvdata(pdev, pc);\n+\n+\tpc->chip.dev = &pdev->dev;\n+\tpc->chip.ops = &mtk_pwm_ops;\n+\tpc->chip.base = -1;\n+\tpc->chip.npwm = NUM_PWM;\n+\n+\tret = pwmchip_add(&pc->chip);\n+\tif (ret < 0)\n+\t\tdev_err(&pdev->dev, \"pwmchip_add() failed: %d\\n\", ret);\n+\n+\treturn ret;\n+}\n+\n+static int mtk_pwm_remove(struct platform_device *pdev)\n+{\n+\tstruct mtk_pwm_chip *pc = platform_get_drvdata(pdev);\n+\tint i;\n+\n+\tfor (i = 0; i < NUM_PWM; i++)\n+\t\tpwm_disable(&pc->chip.pwms[i]);\n+\n+\treturn pwmchip_remove(&pc->chip);\n+}\n+\n+static const struct of_device_id mtk_pwm_of_match[] = {\n+\t{ .compatible = \"mediatek,mt7628-pwm\" },\n+\t{ }\n+};\n+\n+MODULE_DEVICE_TABLE(of, mtk_pwm_of_match);\n+\n+static struct platform_driver mtk_pwm_driver = {\n+\t.driver = {\n+\t\t.name = \"mtk-pwm\",\n+\t\t.owner = THIS_MODULE,\n+\t\t.of_match_table = mtk_pwm_of_match,\n+\t},\n+\t.probe = mtk_pwm_probe,\n+\t.remove = mtk_pwm_remove,\n+};\n+\n+module_platform_driver(mtk_pwm_driver);\n+\n+MODULE_LICENSE(\"GPL\");\n+MODULE_AUTHOR(\"John Crispin <blogic@openwrt.org>\");\n+MODULE_ALIAS(\"platform:mtk-pwm\");\n"
  },
  {
    "path": "target/linux/ramips/patches-5.15/850-awake-rt305x-dwc2-controller.patch",
    "content": "--- a/drivers/usb/dwc2/platform.c\n+++ b/drivers/usb/dwc2/platform.c\n@@ -510,6 +510,12 @@ static int dwc2_driver_probe(struct plat\n \tif (retval)\n \t\treturn retval;\n \n+\t/* Enable USB port before any regs access */\n+\tif (readl(hsotg->regs + PCGCTL) & 0x0f) {\n+\t\twritel(0x00, hsotg->regs + PCGCTL);\n+\t\t/* TODO: mdelay(25) here? vendor driver don't use it */\n+\t}\n+\n \thsotg->needs_byte_swap = dwc2_check_core_endianness(hsotg);\n \n \tretval = dwc2_get_dr_mode(hsotg);\n"
  },
  {
    "path": "target/linux/ramips/patches-5.15/855-linkit_bootstrap.patch",
    "content": "--- a/drivers/misc/Makefile\n+++ b/drivers/misc/Makefile\n@@ -50,6 +50,7 @@ obj-$(CONFIG_ECHO)\t\t+= echo/\n obj-$(CONFIG_CXL_BASE)\t\t+= cxl/\n obj-$(CONFIG_DW_XDATA_PCIE)\t+= dw-xdata-pcie.o\n obj-$(CONFIG_PCI_ENDPOINT_TEST)\t+= pci_endpoint_test.o\n+obj-$(CONFIG_SOC_MT7620)\t+= linkit.o\n obj-$(CONFIG_OCXL)\t\t+= ocxl/\n obj-$(CONFIG_BCM_VK)\t\t+= bcm-vk/\n obj-y\t\t\t\t+= cardreader/\n--- /dev/null\n+++ b/drivers/misc/linkit.c\n@@ -0,0 +1,84 @@\n+/*\n+ *  This program is free software; you can redistribute it and/or modify\n+ *  it under the terms of the GNU General Public License version 2 as\n+ *  publishhed by the Free Software Foundation.\n+ *\n+ *  Copyright (C) 2015 John Crispin <blogic@openwrt.org>\n+ */\n+\n+#include <linux/module.h>\n+#include <linux/platform_device.h>\n+#include <linux/of.h>\n+#include <linux/mtd/mtd.h>\n+#include <linux/gpio.h>\n+\n+#define LINKIT_LATCH_GPIO\t11\n+\n+struct linkit_hw_data {\n+\tchar board[16];\n+\tchar rev[16];\n+};\n+\n+static void sanify_string(char *s)\n+{\n+\tint i;\n+\n+\tfor (i = 0; i < 15; i++)\n+\t\tif (s[i] <= 0x20)\n+\t\t\ts[i] = '\\0';\n+\ts[15] = '\\0';\n+}\n+\n+static int linkit_probe(struct platform_device *pdev)\n+{\n+\tstruct linkit_hw_data hw;\n+\tstruct mtd_info *mtd;\n+\tsize_t retlen;\n+\tint ret;\n+\n+\tmtd = get_mtd_device_nm(\"factory\");\n+\tif (IS_ERR(mtd))\n+\t\treturn PTR_ERR(mtd);\n+\n+\tret = mtd_read(mtd, 0x400, sizeof(hw), &retlen, (u_char *) &hw);\n+\tput_mtd_device(mtd);\n+\n+\tsanify_string(hw.board);\n+\tsanify_string(hw.rev);\n+\n+\tdev_info(&pdev->dev, \"Version  : %s\\n\", hw.board);\n+\tdev_info(&pdev->dev, \"Revision : %s\\n\", hw.rev);\n+\n+\tif (!strcmp(hw.board, \"LINKITS7688\")) {\n+\t\tdev_info(&pdev->dev, \"setting up bootstrap latch\\n\");\n+\n+\t\tif (devm_gpio_request(&pdev->dev, LINKIT_LATCH_GPIO, \"bootstrap\")) {\n+\t\t\tdev_err(&pdev->dev, \"failed to setup bootstrap gpio\\n\");\n+\t\t\treturn -1;\n+\t\t}\n+\t\tgpio_direction_output(LINKIT_LATCH_GPIO, 0);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static const struct of_device_id linkit_match[] = {\n+\t{ .compatible = \"mediatek,linkit\" },\n+\t{},\n+};\n+MODULE_DEVICE_TABLE(of, linkit_match);\n+\n+static struct platform_driver linkit_driver = {\n+\t.probe = linkit_probe,\n+\t.driver = {\n+\t\t.name = \"mtk-linkit\",\n+\t\t.owner = THIS_MODULE,\n+\t\t.of_match_table = linkit_match,\n+\t},\n+};\n+\n+int __init linkit_init(void)\n+{\n+\treturn platform_driver_register(&linkit_driver);\n+}\n+late_initcall_sync(linkit_init);\n"
  },
  {
    "path": "target/linux/ramips/rt288x/base-files/etc/board.d/01_leds",
    "content": "\n. /lib/functions/leds.sh\n. /lib/functions/uci-defaults.sh\n\nboard=$(board_name)\n\nboard_config_update\n\ncase $board in\nairlink101,ar670w|\\\nairlink101,ar725w)\n\tucidef_set_led_netdev \"wifi_led\" \"wifi\" \"rt2800soc-phy0::radio\" \"wlan0\"\n\t;;\nbelkin,f5d8235-v1)\n\tucidef_set_led_netdev \"wifi_led\" \"wifi\" \"blue:wireless\" \"wlan0\"\n\t;;\nralink,v11st-fe)\n\tucidef_set_led_netdev \"wifi_led\" \"wifi\" \"rt2800pci-phy0::radio\" \"wlan0\"\n\t;;\nesac\n\nboard_config_flush\n\nexit 0\n"
  },
  {
    "path": "target/linux/ramips/rt288x/base-files/etc/board.d/02_network",
    "content": "\n. /lib/functions.sh\n. /lib/functions/uci-defaults.sh\n. /lib/functions/system.sh\n\nramips_setup_interfaces()\n{\n\tlocal board=\"$1\"\n\n\tcase $board in\n\tairlink101,ar670w|\\\n\tairlink101,ar725w)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0:wan\" \"1:lan\" \"2:lan\" \"3:lan\" \"4:lan\" \"6t@eth0\"\n\t\t;;\n\tasus,rt-n15)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0:lan\" \"1:lan\" \"2:lan\" \"3:lan\" \"4:wan\" \"5@eth0\"\n\t\t;;\n\tbelkin,f5d8235-v1|\\\n\tbuffalo,wzr-agl300nh|\\\n\tralink,v11st-fe)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"1:lan\" \"2:lan\" \"3:lan\" \"4:lan\" \"0:wan\" \"5@eth0\"\n\t\t;;\n\tbuffalo,wli-tx4-ag300n|\\\n\tdlink,dap-1522-a1)\n\t\tucidef_set_interface_lan \"eth0\"\n\t\t;;\n\tesac\n}\n\nramips_setup_macs()\n{\n\tlocal board=\"$1\"\n\tlocal lan_mac=\"\"\n\tlocal wan_mac=\"\"\n\tlocal label_mac=\"\"\n\n\tcase $board in\n\tairlink101,ar670w)\n\t\twan_mac=$(macaddr_add \"$(mtd_get_mac_binary factory 0x2004)\" 1)\n\t\t;;\n\tairlink101,ar725w|\\\n\tasus,rt-n15|\\\n\tbelkin,f5d8235-v1|\\\n\tbuffalo,wzr-agl300nh)\n\t\twan_mac=$(macaddr_add \"$(mtd_get_mac_binary factory 0x4)\" 1)\n\t\t;;\n\tesac\n\n\t[ -n \"$lan_mac\" ] && ucidef_set_interface_macaddr \"lan\" $lan_mac\n\t[ -n \"$wan_mac\" ] && ucidef_set_interface_macaddr \"wan\" $wan_mac\n\t[ -n \"$label_mac\" ] && ucidef_set_label_macaddr $label_mac\n}\n\nboard_config_update\nboard=$(board_name)\nramips_setup_interfaces $board\nramips_setup_macs $board\nboard_config_flush\n\nexit 0\n"
  },
  {
    "path": "target/linux/ramips/rt288x/base-files/lib/upgrade/platform.sh",
    "content": "#\n# Copyright (C) 2010 OpenWrt.org\n#\n\nPART_NAME=firmware\nREQUIRE_IMAGE_METADATA=1\n\nplatform_check_image() {\n\treturn 0\n}\n\nplatform_do_upgrade() {\n\tlocal board=$(board_name)\n\n\tcase \"$board\" in\n\t*)\n\t\tdefault_do_upgrade \"$1\"\n\t\t;;\n\tesac\n}\n"
  },
  {
    "path": "target/linux/ramips/rt288x/config-5.10",
    "content": "CONFIG_ARCH_32BIT_OFF_T=y\nCONFIG_ARCH_HIBERNATION_POSSIBLE=y\nCONFIG_ARCH_MMAP_RND_BITS_MAX=15\nCONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15\nCONFIG_ARCH_SUSPEND_POSSIBLE=y\nCONFIG_BLK_MQ_PCI=y\nCONFIG_CEVT_R4K=y\nCONFIG_CLKDEV_LOOKUP=y\nCONFIG_CLONE_BACKWARDS=y\nCONFIG_CMDLINE=\"rootfstype=squashfs,jffs2\"\nCONFIG_CMDLINE_BOOL=y\n# CONFIG_CMDLINE_OVERRIDE is not set\nCONFIG_COMPAT_32BIT_TIME=y\nCONFIG_CPU_GENERIC_DUMP_TLB=y\nCONFIG_CPU_HAS_DIEI=y\nCONFIG_CPU_HAS_PREFETCH=y\nCONFIG_CPU_HAS_RIXI=y\nCONFIG_CPU_HAS_SYNC=y\nCONFIG_CPU_MIPS32=y\n# CONFIG_CPU_MIPS32_R1 is not set\nCONFIG_CPU_MIPS32_R2=y\nCONFIG_CPU_MIPSR2=y\nCONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y\nCONFIG_CPU_R4K_CACHE_TLB=y\nCONFIG_CPU_SUPPORTS_32BIT_KERNEL=y\nCONFIG_CPU_SUPPORTS_HIGHMEM=y\nCONFIG_CPU_SUPPORTS_MSA=y\nCONFIG_CRYPTO_LIB_POLY1305_RSIZE=2\nCONFIG_CRYPTO_RNG2=y\nCONFIG_CSRC_R4K=y\nCONFIG_DMA_NONCOHERENT=y\n# CONFIG_DTB_RT2880_EVAL is not set\nCONFIG_DTB_RT_NONE=y\nCONFIG_DTC=y\nCONFIG_EARLY_PRINTK=y\nCONFIG_FIXED_PHY=y\nCONFIG_FW_LOADER_PAGED_BUF=y\nCONFIG_GENERIC_ALLOCATOR=y\nCONFIG_GENERIC_ATOMIC64=y\nCONFIG_GENERIC_CLOCKEVENTS=y\nCONFIG_GENERIC_CMOS_UPDATE=y\nCONFIG_GENERIC_CPU_AUTOPROBE=y\nCONFIG_GENERIC_GETTIMEOFDAY=y\nCONFIG_GENERIC_IOMAP=y\nCONFIG_GENERIC_IRQ_CHIP=y\nCONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y\nCONFIG_GENERIC_IRQ_SHOW=y\nCONFIG_GENERIC_LIB_ASHLDI3=y\nCONFIG_GENERIC_LIB_ASHRDI3=y\nCONFIG_GENERIC_LIB_CMPDI2=y\nCONFIG_GENERIC_LIB_LSHRDI3=y\nCONFIG_GENERIC_LIB_UCMPDI2=y\nCONFIG_GENERIC_PCI_IOMAP=y\nCONFIG_GENERIC_PINCONF=y\nCONFIG_GENERIC_SCHED_CLOCK=y\nCONFIG_GENERIC_SMP_IDLE_THREAD=y\nCONFIG_GENERIC_TIME_VSYSCALL=y\nCONFIG_GPIOLIB=y\nCONFIG_GPIO_RALINK=y\nCONFIG_HANDLE_DOMAIN_IRQ=y\nCONFIG_HARDWARE_WATCHPOINTS=y\nCONFIG_HAS_DMA=y\nCONFIG_HAS_IOMEM=y\nCONFIG_HAS_IOPORT_MAP=y\nCONFIG_HZ_PERIODIC=y\nCONFIG_INITRAMFS_SOURCE=\"\"\nCONFIG_IP17XX_PHY=y\nCONFIG_IRQCHIP=y\nCONFIG_IRQ_DOMAIN=y\nCONFIG_IRQ_FORCED_THREADING=y\nCONFIG_IRQ_INTC=y\nCONFIG_IRQ_MIPS_CPU=y\nCONFIG_IRQ_WORK=y\n# CONFIG_KERNEL_ZSTD is not set\nCONFIG_LIBFDT=y\nCONFIG_LOCK_DEBUGGING_SUPPORT=y\nCONFIG_MDIO_BUS=y\nCONFIG_MDIO_DEVICE=y\nCONFIG_MEMFD_CREATE=y\nCONFIG_MIGRATION=y\nCONFIG_MIPS=y\nCONFIG_MIPS_ASID_BITS=8\nCONFIG_MIPS_ASID_SHIFT=0\nCONFIG_MIPS_CBPF_JIT=y\nCONFIG_MIPS_CLOCK_VSYSCALL=y\n# CONFIG_MIPS_CMDLINE_BUILTIN_EXTEND is not set\n# CONFIG_MIPS_CMDLINE_DTB_EXTEND is not set\n# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set\nCONFIG_MIPS_CMDLINE_FROM_DTB=y\n# CONFIG_MIPS_ELF_APPENDED_DTB is not set\nCONFIG_MIPS_L1_CACHE_SHIFT=4\nCONFIG_MIPS_L1_CACHE_SHIFT_4=y\nCONFIG_MIPS_LD_CAN_LINK_VDSO=y\n# CONFIG_MIPS_NO_APPENDED_DTB is not set\nCONFIG_MIPS_RAW_APPENDED_DTB=y\nCONFIG_MIPS_SPRAM=y\nCONFIG_MODULES_USE_ELF_REL=y\n# CONFIG_MTD_CFI_INTELEXT is not set\nCONFIG_MTD_CMDLINE_PARTS=y\nCONFIG_MTD_PHYSMAP=y\nCONFIG_MTD_SPI_NOR=y\nCONFIG_MTD_SPLIT_LZMA_FW=y\nCONFIG_MTD_SPLIT_UIMAGE_FW=y\nCONFIG_MTD_SPLIT_WRGG_FW=y\nCONFIG_NEED_DMA_MAP_STATE=y\nCONFIG_NEED_PER_CPU_KM=y\nCONFIG_NET_RALINK_MDIO=y\nCONFIG_NET_RALINK_MDIO_RT2880=y\nCONFIG_NET_RALINK_RT2880=y\nCONFIG_NET_RALINK_SOC=y\nCONFIG_NET_VENDOR_RALINK=y\nCONFIG_NLS=m\nCONFIG_NO_GENERIC_PCI_IOPORT_MAP=y\nCONFIG_NVMEM=y\nCONFIG_OF=y\nCONFIG_OF_ADDRESS=y\nCONFIG_OF_EARLY_FLATTREE=y\nCONFIG_OF_FLATTREE=y\nCONFIG_OF_GPIO=y\nCONFIG_OF_IRQ=y\nCONFIG_OF_KOBJ=y\nCONFIG_OF_MDIO=y\nCONFIG_OF_NET=y\nCONFIG_PCI=y\nCONFIG_PCI_DOMAINS=y\nCONFIG_PCI_DRIVERS_LEGACY=y\n# CONFIG_PCI_MT7621 is not set\n# CONFIG_PCI_MT7621_PHY is not set\nCONFIG_PERF_USE_VMALLOC=y\nCONFIG_PGTABLE_LEVELS=2\nCONFIG_PHYLIB=y\n# CONFIG_PHY_RALINK_USB is not set\nCONFIG_PINCTRL=y\n# CONFIG_PINCTRL_AW9523 is not set\nCONFIG_PINCTRL_RT2880=y\n# CONFIG_PINCTRL_SINGLE is not set\nCONFIG_RALINK=y\nCONFIG_RALINK_WDT=y\nCONFIG_RESET_CONTROLLER=y\nCONFIG_SERIAL_8250_RT288X=y\nCONFIG_SERIAL_MCTRL_GPIO=y\nCONFIG_SERIAL_OF_PLATFORM=y\n# CONFIG_SOC_MT7620 is not set\n# CONFIG_SOC_MT7621 is not set\nCONFIG_SOC_RT288X=y\n# CONFIG_SOC_RT305X is not set\n# CONFIG_SOC_RT3883 is not set\nCONFIG_SPI=y\nCONFIG_SPI_MASTER=y\nCONFIG_SPI_MEM=y\n# CONFIG_SPI_MT7621 is not set\nCONFIG_SPI_RT2880=y\nCONFIG_SRCU=y\nCONFIG_SWCONFIG=y\nCONFIG_SWPHY=y\nCONFIG_SYSCTL_EXCEPTION_TRACE=y\nCONFIG_SYS_HAS_CPU_MIPS32_R1=y\nCONFIG_SYS_HAS_CPU_MIPS32_R2=y\nCONFIG_SYS_HAS_EARLY_PRINTK=y\nCONFIG_SYS_SUPPORTS_32BIT_KERNEL=y\nCONFIG_SYS_SUPPORTS_ARBIT_HZ=y\nCONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y\nCONFIG_SYS_SUPPORTS_MIPS16=y\nCONFIG_SYS_SUPPORTS_ZBOOT=y\nCONFIG_TARGET_ISA_REV=2\nCONFIG_TICK_CPU_ACCOUNTING=y\nCONFIG_TINY_SRCU=y\nCONFIG_USB=m\nCONFIG_USB_COMMON=m\nCONFIG_USB_EHCI_HCD=m\nCONFIG_USB_EHCI_HCD_PLATFORM=m\nCONFIG_USB_OHCI_HCD=m\nCONFIG_USB_OHCI_HCD_PLATFORM=m\nCONFIG_USB_SUPPORT=y\nCONFIG_USE_OF=y\nCONFIG_WATCHDOG_CORE=y\n"
  },
  {
    "path": "target/linux/ramips/rt288x/target.mk",
    "content": "#\n# Copyright (C) 2009 OpenWrt.org\n#\n\nSUBTARGET:=rt288x\nBOARDNAME:=RT288x based boards\nFEATURES+=small_flash\nCPU_TYPE:=24kc\n\nDEFAULT_PACKAGES += kmod-rt2800-soc wpad-basic-wolfssl swconfig\n\ndefine Target/Description\n\tBuild firmware images for Ralink RT288x based boards.\nendef\n\n"
  },
  {
    "path": "target/linux/ramips/rt305x/base-files/etc/board.d/01_leds",
    "content": "\n. /lib/functions/leds.sh\n. /lib/functions/uci-defaults.sh\n\nboard=$(board_name)\n\nboard_config_update\n\ncase $board in\n7links,px-4885-4m|\\\n7links,px-4885-8m|\\\nfon,fonera-20n)\n\tucidef_set_led_netdev \"wifi_led\" \"wifi\" \"orange:wifi\" \"wlan0\"\n\t;;\nairlive,air3gii|\\\naximcom,mr-102n|\\\nedimax,3g-6200nl|\\\nnetgear,wnce2001)\n\tucidef_set_led_netdev \"wifi_led\" \"wifi\" \"green:wlan\" \"wlan0\"\n\t;;\nalfa-network,w502u|\\\ndlink,dir-300-b1|\\\ndlink,dir-300-b7|\\\ndlink,dir-320-b1|\\\ndlink,dir-600-b1|\\\ndlink,dir-610-a1|\\\ndlink,dir-615-h1|\\\ndlink,dir-620-a1|\\\nengenius,esr-9753|\\\nhilink,hlk-rm04|\\\nnexx,wt1520-4m|\\\nnexx,wt1520-8m|\\\nskyline,sl-r7205|\\\ntenda,w306r-v2|\\\nzyxel,keenetic-start|\\\nzyxel,keenetic|\\\nzyxel,nbg-419n-v2)\n\tucidef_set_led_netdev \"wifi_led\" \"wifi\" \"rt2800pci-phy0::radio\" \"wlan0\"\n\t;;\nallnet,all0256n-4m|\\\nallnet,all0256n-8m)\n\tucidef_set_rssimon \"wlan0\" \"200000\" \"1\"\n\tucidef_set_led_rssi \"rssilow\" \"RSSILOW\" \"green:rssilow\" \"wlan0\" \"1\" \"40\" \"0\" \"6\"\n\tucidef_set_led_rssi \"rssimedium\" \"RSSIMEDIUM\" \"green:rssimed\" \"wlan0\" \"30\" \"80\" \"-29\" \"5\"\n\tucidef_set_led_rssi \"rssihigh\" \"RSSIHIGH\" \"green:rssihigh\" \"wlan0\" \"70\" \"100\" \"-69\" \"8\"\n\tucidef_set_led_netdev \"wifi_led\" \"wifi\" \"rt2800pci-phy0::radio\" \"wlan0\"\n\t;;\nalphanetworks,asl26555-8m|\\\nalphanetworks,asl26555-16m)\n\tucidef_set_led_netdev \"eth\" \"ETH\" \"green:eth\" \"eth0\"\n\tucidef_set_led_netdev \"wifi_led\" \"wifi\" \"green:wlan\" \"wlan0\"\n\t;;\nasiarf,awapn2403)\n\tucidef_set_led_netdev \"wifi_led\" \"wifi\" \"rt2800soc-phy0::radio\" \"wlan0\"\n\t;;\ndlink,dcs-930l-b1)\n\tucidef_set_led_netdev \"wifi\" \"WiFi\" \"blue:wps\"\n\t;;\ndlink,dir-615-d)\n\tucidef_set_led_netdev \"wan\" \"WAN (green)\" \"green:wan\" \"eth0.2\"\n\tucidef_set_led_netdev \"wifi_led\" \"wifi\" \"rt2800soc-phy0::radio\" \"wlan0\"\n\t;;\ndlink,dir-620-d1|\\\ntrendnet,tew-714tru)\n\tucidef_set_led_netdev \"wifi_led\" \"wifi\" \"green:wifi\" \"wlan0\"\n\t;;\nedimax,3g-6200n|\\\nplanex,mzk-w300nh2)\n\tucidef_set_led_netdev \"wifi_led\" \"wifi\" \"amber:wlan\" \"wlan0\"\n\t;;\nhauppauge,broadway)\n\tucidef_set_led_netdev \"wifi_led\" \"wifi\" \"red:wps_active\" \"wlan0\"\n\t;;\nhootoo,ht-tm02)\n\tucidef_set_led_netdev \"eth\" \"Ethernet\" \"green:lan\" \"eth0\"\n\tucidef_set_led_netdev \"wifi_led\" \"wifi\" \"blue:wlan\" \"wlan0\"\n\t;;\nhuawei,hg255d)\n\tucidef_set_led_netdev \"wifi_led\" \"wifi\" \"green:wlan\" \"wlan0\"\n\tucidef_set_led_netdev \"internet\" \"internet\" \"green:internet\" \"eth0.2\"\n\t;;\nintenso,memory2move)\n\tucidef_set_led_netdev \"wifi_led\" \"wifi\" \"blue:wifi\" \"wlan0\"\n\tucidef_set_led_netdev \"eth\" \"Ethernet\" \"green:wan\" \"eth0\"\n\t;;\nomnima,miniembplug)\n\tucidef_set_led_netdev \"wifi_led\" \"wifi\" \"red:wlan\" \"wlan0\"\n\t;;\nvocore,vocore-8m|\\\nvocore,vocore-16m)\n\tucidef_set_led_netdev \"eth\" \"ETH\" \"orange:eth\" \"eth0\"\n\t;;\nzorlik,zl5900v2)\n\tucidef_set_led_netdev \"lan\" \"lan\" \"green:lan\" \"eth0\"\n\t;;\nzte,mf283plus)\n\tucidef_set_led_wlan \"wifi\" \"wifi\" \"rt2800soc-phy0::radio\" \"phy0tpt\"\n\tucidef_set_led_netdev \"wwan\" \"wwan\" \"blue:wwan\" \"wwan0\"\n\t;;\nesac\n\nboard_config_flush\n\nexit 0\n"
  },
  {
    "path": "target/linux/ramips/rt305x/base-files/etc/board.d/02_network",
    "content": "\n. /lib/functions.sh\n. /lib/functions/uci-defaults.sh\n. /lib/functions/system.sh\n\nramips_setup_interfaces()\n{\n\tlocal board=\"$1\"\n\n\tcase $board in\n\t7links,px-4885-4m|\\\n\t7links,px-4885-8m|\\\n\tallnet,all0256n-4m|\\\n\tallnet,all0256n-8m|\\\n\tallnet,all5002|\\\n\tallnet,all5003|\\\n\tbelkin,f7c027|\\\n\tdlink,dcs-930l-b1|\\\n\tdlink,dcs-930|\\\n\tedimax,3g-6200nl|\\\n\thame,mpr-a1|\\\n\thame,mpr-a2|\\\n\thauppauge,broadway|\\\n\thootoo,ht-tm02|\\\n\thuawei,d105|\\\n\tintenso,memory2move|\\\n\tnetgear,wnce2001|\\\n\ttenda,3g150b|\\\n\ttenda,3g300m|\\\n\ttenda,w150m|\\\n\ttrendnet,tew-714tru|\\\n\tunbranded,a5-v11|\\\n\twansview,ncs601w|\\\n\tzorlik,zl5900v2)\n\t\tucidef_add_switch \"switch0\"\n\t\tucidef_add_switch_attr \"switch0\" \"enable\" \"false\"\n\t\tucidef_set_interface_lan \"eth0\"\n\t\t;;\n\t8devices,carambola)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0:lan\" \"1:lan\" \"6@eth0\"\n\t\t;;\n\taccton,wr6202|\\\n\talfa-network,w502u|\\\n\targus,atp-52b|\\\n\tasiarf,awm002-evb-4m|\\\n\tasiarf,awm002-evb-8m|\\\n\tasus,rt-n10-plus|\\\n\tasus,wl-330n|\\\n\tasus,wl-330n3g|\\\n\taztech,hw550-3g|\\\n\tengenius,esr-9753|\\\n\tjcg,jhr-n805r|\\\n\tjcg,jhr-n825r|\\\n\tjcg,jhr-n926r|\\\n\tpetatel,psr-680w|\\\n\tplanex,mzk-wdpr|\\\n\tskyline,sl-r7205|\\\n\tteltonika,rut5xx|\\\n\ttenda,w306r-v2|\\\n\tunbranded,xdx-rn502j|\\\n\tupvel,ur-326n4g)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"1:lan\" \"2:lan\" \"3:lan\" \"4:lan\" \"0:wan\" \"6@eth0\"\n\t\t;;\n\tairlive,air3gii|\\\n\tasus,rt-g32-b1|\\\n\tasus,rt-n13u|\\\n\taximcom,mr-102n|\\\n\tbuffalo,whr-g300n|\\\n\tdlink,dap-1350|\\\n\tdlink,dir-300-b1|\\\n\tdlink,dir-300-b7|\\\n\tdlink,dir-320-b1|\\\n\tdlink,dir-600-b1|\\\n\tdlink,dir-610-a1|\\\n\tdlink,dir-615-d|\\\n\tdlink,dir-620-a1|\\\n\tdlink,dir-620-d1|\\\n\tdlink,dwr-512-b|\\\n\teasyacc,wizard-8800|\\\n\tedimax,3g-6200n|\\\n\tfon,fonera-20n|\\\n\thilink,hlk-rm04|\\\n\tmofinetwork,mofi3500-3gn|\\\n\tnetcore,nw718|\\\n\tnexaira,bc2|\\\n\tnixcore,x1-16m|\\\n\tnixcore,x1-8m|\\\n\tolimex,rt5350f-olinuxino|\\\n\tolimex,rt5350f-olinuxino-evb|\\\n\tomnima,miniembplug|\\\n\tomnima,miniembwifi|\\\n\tplanex,mzk-w300nh2|\\\n\tporay,ip2202|\\\n\tporay,m3|\\\n\tporay,m4-4m|\\\n\tporay,m4-8m|\\\n\tporay,x5|\\\n\tporay,x8|\\\n\tprolink,pwh2004|\\\n\tralink,v22rw-2x2|\\\n\tunbranded,wr512-3gn-4m|\\\n\tunbranded,wr512-3gn-8m|\\\n\tupvel,ur-336un|\\\n\tzyxel,keenetic|\\\n\tzyxel,nbg-419n|\\\n\tzyxel,nbg-419n-v2)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0:lan\" \"1:lan\" \"2:lan\" \"3:lan\" \"4:wan\" \"6@eth0\"\n\t\t;;\n\talphanetworks,asl26555-8m|\\\n\talphanetworks,asl26555-16m)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"1:lan\" \"2:lan\" \"3:lan\" \"4:lan\" \"6t@eth0\"\n\t\t;;\n\tarcwireless,freestation5)\n\t\t# FIXME: Which is the actual wan port?\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0:lan\" \"1:wan\" \"2:wan\" \"3:wan\" \"4:wan\" \"6@eth0\"\n\t\t;;\n\tasiarf,awapn2403)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0:lan\" \"1:wan\" \"6@eth0\"\n\t\t;;\n\taximcom,mr-102n|\\\n\ttrendnet,tew-638apb-v2)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"4:lan\" \"6@eth0\"\n\t\t;;\n\tbelkin,f5d8235-v2)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"1:lan\" \"2:lan\" \"3:lan\" \"4:lan\" \"0:wan\" \"5@eth0\"\n\t\t;;\n\tdlink,dir-615-h1)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0:lan:4\" \"1:lan:3\" \"2:lan:2\" \"3:lan:1\" \"4:wan:5\" \"6@eth0\"\n\t\t;;\n\thuawei,hg255d)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"1:lan:4\" \"2:lan:3\" \"3:lan:2\" \"4:lan:1\" \"0:wan\" \"6@eth0\"\n\t\t;;\n\tnexx,wt1520-4m|\\\n\tnexx,wt1520-8m)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0:lan\" \"4:wan\" \"6@eth0\"\n\t\t;;\n\tplanex,mzk-dp150n|\\\n\tvocore,vocore-8m|\\\n\tvocore,vocore-16m)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0:lan\" \"4:lan\" \"6t@eth0\"\n\t\t;;\n\tsitecom,wl-351)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0:lan\" \"1:lan\" \"2:lan\" \"3:lan\" \"4:wan\" \"5@eth0\"\n\t\t;;\n\tsparklan,wcr-150gn)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0:lan\" \"6t@eth0\"\n\t\t;;\n\twiznet,wizfi630a)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0:lan\" \"1:lan\" \"2:wan\" \"6@eth0\"\n\t\t;;\n\tzte,mf283plus)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0:lan\" \"1:lan\" \"2:lan\" \"3:lan\" \"6@eth0\"\n\t\t;;\n\tzyxel,keenetic-lite-b|\\\n\tzyxel,keenetic-start)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0:lan:3\" \"1:lan:2\" \"2:lan:1\" \"3:lan:0\" \"4:wan\" \"6@eth0\"\n\t\t;;\n\tesac\n}\n\nramips_setup_macs()\n{\n\tlocal board=\"$1\"\n\tlocal lan_mac=\"\"\n\tlocal wan_mac=\"\"\n\tlocal label_mac=\"\"\n\n\tcase $board in\n\t7links,px-4885-4m|\\\n\t7links,px-4885-8m)\n\t\twan_mac=$(macaddr_add \"$(mtd_get_mac_binary devconf 0x28)\" 1)\n\t\t;;\n\t8devices,carambola|\\\n\talfa-network,w502u|\\\n\tarcwireless,freestation5|\\\n\tnetgear,wnce2001)\n\t\twan_mac=$(mtd_get_mac_binary factory 0x2e)\n\t\t;;\n\taccton,wr6202|\\\n\tasiarf,awm002-evb-4m|\\\n\tasiarf,awm002-evb-8m|\\\n\tasus,rt-n13u|\\\n\taztech,hw550-3g|\\\n\tfon,fonera-20n|\\\n\thuawei,hg255d|\\\n\tomnima,miniembwifi|\\\n\tplanex,mzk-wdpr|\\\n\tporay,ip2202|\\\n\tteltonika,rut5xx|\\\n\tunbranded,xdx-rn502j|\\\n\tzyxel,keenetic|\\\n\tzyxel,nbg-419n|\\\n\tzyxel,nbg-419n-v2)\n\t\twan_mac=$(macaddr_add \"$(mtd_get_mac_binary factory 0x28)\" 1)\n\t\t;;\n\tairlive,air3gii|\\\n\targus,atp-52b|\\\n\tasus,wl-330n3g|\\\n\tdlink,dir-620-d1|\\\n\tedimax,3g-6200n|\\\n\tedimax,3g-6200nl|\\\n\tnetcore,nw718|\\\n\tnexx,wt1520-4m|\\\n\tnexx,wt1520-8m|\\\n\tnixcore,x1-16m|\\\n\tnixcore,x1-8m|\\\n\tomnima,miniembplug|\\\n\tplanex,mzk-w300nh2|\\\n\tsitecom,wl-351|\\\n\ttrendnet,tew-714tru)\n\t\twan_mac=$(macaddr_add \"$(mtd_get_mac_binary factory 0x4)\" 1)\n\t\t;;\n\tasus,rt-g32-b1|\\\n\tasus,rt-n10-plus)\n\t\twan_mac=$(macaddr_add \"$(mtd_get_mac_binary devconf 0x4)\" 1)\n\t\t;;\n\tbelkin,f5d8235-v2)\n\t\twan_mac=$(macaddr_add \"$(mtd_get_mac_binary uboot 0x40004)\" 1)\n\t\t;;\n\tdlink,dir-300-b7|\\\n\tdlink,dir-320-b1|\\\n\tdlink,dir-620-a1|\\\n\tengenius,esr-9753|\\\n\thame,mpr-a1|\\\n\thauppauge,broadway|\\\n\thuawei,d105|\\\n\thilink,hlk-rm04|\\\n\tnexaira,bc2|\\\n\tolimex,rt5350f-olinuxino|\\\n\tolimex,rt5350f-olinuxino-evb|\\\n\tpetatel,psr-680w|\\\n\tskyline,sl-r7205)\n\t\tlan_mac=$(macaddr_setbit_la \"$(cat /sys/class/net/eth0/address)\")\n\t\twan_mac=$(macaddr_add \"$lan_mac\" 1)\n\t\t;;\n\tdlink,dap-1350)\n\t\twan_mac=$(macaddr_add \"$(mtd_get_mac_binary devdata 0x2e)\" 1)\n\t\t;;\n\tdlink,dir-300-b1|\\\n\tdlink,dir-600-b1|\\\n\tdlink,dir-610-a1)\n\t\twan_mac=$(macaddr_add \"$(mtd_get_mac_binary devdata 0x4004)\" 1)\n\t\t;;\n\tdlink,dir-615-d)\n\t\tlabel_mac=$(mtd_get_mac_binary devdata 0x4004)\n\t\t;;\n\tdlink,dir-615-h1)\n\t\twan_mac=$(macaddr_add \"$(mtd_get_mac_binary factory 0x28)\" 1)\n\t\tlabel_mac=$(mtd_get_mac_binary factory 0x4)\n\t\t;;\n\tdlink,dwr-512-b)\n\t\twan_mac=$(macaddr_add \"$(mtd_get_mac_binary config 0xe07e)\" 1)\n\t\t;;\n\tjcg,jhr-n805r|\\\n\tjcg,jhr-n825r|\\\n\tjcg,jhr-n926r)\n\t\twan_mac=$(macaddr_add \"$(mtd_get_mac_binary factory 0x2e)\" 1)\n\t\t;;\n\tporay,m3|\\\n\tporay,m4-4m|\\\n\tporay,m4-8m|\\\n\tporay,x5|\\\n\tporay,x8)\n\t\tlan_mac=$(macaddr_add \"$(mtd_get_mac_binary factory 0x4)\" -2)\n\t\t;;\n\tsparklan,wcr-150gn|\\\n\twiznet,wizfi630a)\n\t\twan_mac=$(mtd_get_mac_binary factory 0x28)\n\t\t;;\n\ttenda,w306r-v2)\n\t\twan_mac=$(macaddr_add \"$(mtd_get_mac_binary factory 0x28)\" 5)\n\t\t;;\n\tupvel,ur-326n4g|\\\n\tupvel,ur-336un)\n\t\twan_mac=$(macaddr_add \"$(mtd_get_mac_binary factory 0x4004)\" 1)\n\t\t;;\n\tesac\n\n\t[ -n \"$lan_mac\" ] && ucidef_set_interface_macaddr \"lan\" $lan_mac\n\t[ -n \"$wan_mac\" ] && ucidef_set_interface_macaddr \"wan\" $wan_mac\n\t[ -n \"$label_mac\" ] && ucidef_set_label_macaddr $label_mac\n}\n\nboard_config_update\nboard=$(board_name)\nramips_setup_interfaces $board\nramips_setup_macs $board\nboard_config_flush\n\nexit 0\n"
  },
  {
    "path": "target/linux/ramips/rt305x/base-files/lib/preinit/04_handle_checksumming",
    "content": "# Netgear WNCE2001 has does a checksum check on boot and goes into recovery\n# tftp mode when the check fails.  Initializing the JFFS2 partition triggers\n# this, so we make sure to zero checksum and size to be checksummed before\n# that happens, so this needs to run very early during boot.\n\ndo_checksumming_disable() {\n\t. /lib/functions.sh\n\n\tlocal board=$(board_name)\n\n\tcase \"$board\" in\n\tnetgear,wnce2001)\n\t\techo \"Board is WNCE2001, updating checksum partition...\"\n\t\tlocal zeroes=/dev/zero\n\t\tlocal tmpfile=/tmp/wnce2001_checksum\n\t\tlocal partname=checksum\n\t\tlocal mtd=$(find_mtd_part $partname)\n\t\tdd if=$mtd of=$tmpfile bs=80 count=1 2>/dev/null\n\t\tsignature=$(dd if=$tmpfile bs=1 skip=24 count=20 2>/dev/null)\n\t\tchecksum=$(dd if=$tmpfile bs=1 count=4 2>/dev/null | hexdump -v -n 4 -e '1/1 \"%02x\"')\n\t\tif [ \"$signature\" != \"RT3052-AP-WNCE2001-3\" ]; then\n\t\t\techo \"Signature of checksum partition is wrong, bailing.\"\n\t\t\treturn 0\n\t\tfi\n\t\tif [ \"$checksum\" != \"00000000\" ]; then\n\t\t\techo \"Checksum is set, zeroing.\"\n\t\t\t# zero out checksum\n\t\t\tdd if=$zeroes of=$tmpfile conv=notrunc bs=1 seek=0 count=4 2>/dev/null\n\t\t\t# zero out bytecount to be checksummed\n\t\t\tdd if=$zeroes of=$tmpfile conv=notrunc bs=1 seek=60 count=4 2>/dev/null\n\t\t\tmtd write $tmpfile $partname\n\t\telse\n\t\t\techo \"Checksum is already zero, nothing to do.\"\n\t\tfi\n\t;;\n\tesac\n\n\treturn 0\n}\n\nboot_hook_add preinit_main do_checksumming_disable\n"
  },
  {
    "path": "target/linux/ramips/rt305x/base-files/lib/upgrade/platform.sh",
    "content": "#\n# Copyright (C) 2010 OpenWrt.org\n#\n\nPART_NAME=firmware\nREQUIRE_IMAGE_METADATA=1\n\nplatform_check_image() {\n\treturn 0\n}\n\nplatform_do_upgrade() {\n\tlocal board=$(board_name)\n\n\tcase \"$board\" in\n\t*)\n\t\tdefault_do_upgrade \"$1\"\n\t\t;;\n\tesac\n}\n"
  },
  {
    "path": "target/linux/ramips/rt305x/config-5.10",
    "content": "CONFIG_ARCH_32BIT_OFF_T=y\nCONFIG_ARCH_HIBERNATION_POSSIBLE=y\nCONFIG_ARCH_MMAP_RND_BITS_MAX=15\nCONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15\nCONFIG_ARCH_SUSPEND_POSSIBLE=y\nCONFIG_CEVT_R4K=y\nCONFIG_CEVT_SYSTICK_QUIRK=y\nCONFIG_CLKDEV_LOOKUP=y\nCONFIG_CLKEVT_RT3352=y\nCONFIG_CLKSRC_MMIO=y\nCONFIG_CLONE_BACKWARDS=y\nCONFIG_CMDLINE=\"rootfstype=squashfs,jffs2\"\nCONFIG_CMDLINE_BOOL=y\n# CONFIG_CMDLINE_OVERRIDE is not set\nCONFIG_COMPAT_32BIT_TIME=y\nCONFIG_CPU_GENERIC_DUMP_TLB=y\nCONFIG_CPU_HAS_DIEI=y\nCONFIG_CPU_HAS_PREFETCH=y\nCONFIG_CPU_HAS_RIXI=y\nCONFIG_CPU_HAS_SYNC=y\nCONFIG_CPU_MIPS32=y\n# CONFIG_CPU_MIPS32_R1 is not set\nCONFIG_CPU_MIPS32_R2=y\nCONFIG_CPU_MIPSR2=y\nCONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y\nCONFIG_CPU_R4K_CACHE_TLB=y\nCONFIG_CPU_SUPPORTS_32BIT_KERNEL=y\nCONFIG_CPU_SUPPORTS_HIGHMEM=y\nCONFIG_CPU_SUPPORTS_MSA=y\nCONFIG_CRYPTO_LIB_POLY1305_RSIZE=2\nCONFIG_CRYPTO_RNG2=y\nCONFIG_CSRC_R4K=y\nCONFIG_DEBUG_PINCTRL=y\nCONFIG_DMA_NONCOHERENT=y\n# CONFIG_DTB_RT305X_EVAL is not set\nCONFIG_DTB_RT_NONE=y\nCONFIG_DTC=y\nCONFIG_EARLY_PRINTK=y\nCONFIG_FIXED_PHY=y\nCONFIG_FW_LOADER_PAGED_BUF=y\nCONFIG_GENERIC_ATOMIC64=y\nCONFIG_GENERIC_CLOCKEVENTS=y\nCONFIG_GENERIC_CMOS_UPDATE=y\nCONFIG_GENERIC_CPU_AUTOPROBE=y\nCONFIG_GENERIC_GETTIMEOFDAY=y\nCONFIG_GENERIC_IOMAP=y\nCONFIG_GENERIC_IRQ_CHIP=y\nCONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y\nCONFIG_GENERIC_IRQ_SHOW=y\nCONFIG_GENERIC_LIB_ASHLDI3=y\nCONFIG_GENERIC_LIB_ASHRDI3=y\nCONFIG_GENERIC_LIB_CMPDI2=y\nCONFIG_GENERIC_LIB_LSHRDI3=y\nCONFIG_GENERIC_LIB_UCMPDI2=y\nCONFIG_GENERIC_PCI_IOMAP=y\nCONFIG_GENERIC_PHY=y\nCONFIG_GENERIC_PINCONF=y\nCONFIG_GENERIC_SCHED_CLOCK=y\nCONFIG_GENERIC_SMP_IDLE_THREAD=y\nCONFIG_GENERIC_TIME_VSYSCALL=y\nCONFIG_GPIOLIB=y\nCONFIG_GPIO_RALINK=y\nCONFIG_GPIO_WATCHDOG=y\n# CONFIG_GPIO_WATCHDOG_ARCH_INITCALL is not set\nCONFIG_HANDLE_DOMAIN_IRQ=y\nCONFIG_HARDWARE_WATCHPOINTS=y\nCONFIG_HAS_DMA=y\nCONFIG_HAS_IOMEM=y\nCONFIG_HAS_IOPORT_MAP=y\nCONFIG_HZ_PERIODIC=y\nCONFIG_INITRAMFS_SOURCE=\"\"\nCONFIG_IRQCHIP=y\nCONFIG_IRQ_DOMAIN=y\nCONFIG_IRQ_FORCED_THREADING=y\nCONFIG_IRQ_INTC=y\nCONFIG_IRQ_MIPS_CPU=y\nCONFIG_IRQ_WORK=y\n# CONFIG_KERNEL_ZSTD is not set\nCONFIG_LIBFDT=y\nCONFIG_LOCK_DEBUGGING_SUPPORT=y\nCONFIG_MDIO_BUS=y\nCONFIG_MDIO_DEVICE=y\nCONFIG_MEMFD_CREATE=y\nCONFIG_MFD_SYSCON=y\nCONFIG_MIGRATION=y\nCONFIG_MIPS=y\nCONFIG_MIPS_ASID_BITS=8\nCONFIG_MIPS_ASID_SHIFT=0\nCONFIG_MIPS_CBPF_JIT=y\nCONFIG_MIPS_CLOCK_VSYSCALL=y\n# CONFIG_MIPS_CMDLINE_BUILTIN_EXTEND is not set\n# CONFIG_MIPS_CMDLINE_DTB_EXTEND is not set\n# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set\nCONFIG_MIPS_CMDLINE_FROM_DTB=y\n# CONFIG_MIPS_ELF_APPENDED_DTB is not set\nCONFIG_MIPS_L1_CACHE_SHIFT=5\nCONFIG_MIPS_LD_CAN_LINK_VDSO=y\n# CONFIG_MIPS_NO_APPENDED_DTB is not set\nCONFIG_MIPS_RAW_APPENDED_DTB=y\nCONFIG_MIPS_SPRAM=y\nCONFIG_MODULES_USE_ELF_REL=y\n# CONFIG_MTD_CFI_INTELEXT is not set\nCONFIG_MTD_CMDLINE_PARTS=y\nCONFIG_MTD_PHYSMAP=y\nCONFIG_MTD_SPI_NOR=y\nCONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y\nCONFIG_MTD_SPI_NOR_USE_4K_SECTORS_LIMIT=16384\nCONFIG_MTD_SPLIT_JIMAGE_FW=y\nCONFIG_MTD_SPLIT_SEAMA_FW=y\nCONFIG_MTD_SPLIT_UIMAGE_FW=y\nCONFIG_NEED_DMA_MAP_STATE=y\nCONFIG_NEED_PER_CPU_KM=y\nCONFIG_NET_RALINK_ESW_RT3050=y\nCONFIG_NET_RALINK_RT3050=y\nCONFIG_NET_RALINK_SOC=y\nCONFIG_NET_VENDOR_RALINK=y\nCONFIG_NO_GENERIC_PCI_IOPORT_MAP=y\nCONFIG_NVMEM=y\nCONFIG_OF=y\nCONFIG_OF_ADDRESS=y\nCONFIG_OF_EARLY_FLATTREE=y\nCONFIG_OF_FLATTREE=y\nCONFIG_OF_GPIO=y\nCONFIG_OF_IRQ=y\nCONFIG_OF_KOBJ=y\nCONFIG_OF_MDIO=y\nCONFIG_OF_NET=y\nCONFIG_PCI_DRIVERS_LEGACY=y\n# CONFIG_PCI_MT7621 is not set\n# CONFIG_PCI_MT7621_PHY is not set\nCONFIG_PERF_USE_VMALLOC=y\nCONFIG_PGTABLE_LEVELS=2\nCONFIG_PHYLIB=y\nCONFIG_PHY_RALINK_USB=y\nCONFIG_PINCTRL=y\n# CONFIG_PINCTRL_AW9523 is not set\nCONFIG_PINCTRL_RT2880=y\n# CONFIG_PINCTRL_SINGLE is not set\nCONFIG_RALINK=y\n# CONFIG_RALINK_ILL_ACC is not set\nCONFIG_RALINK_WDT=y\nCONFIG_REGMAP=y\nCONFIG_REGMAP_MMIO=y\nCONFIG_RESET_CONTROLLER=y\nCONFIG_SERIAL_8250_RT288X=y\nCONFIG_SERIAL_MCTRL_GPIO=y\nCONFIG_SERIAL_OF_PLATFORM=y\n# CONFIG_SOC_MT7620 is not set\n# CONFIG_SOC_MT7621 is not set\n# CONFIG_SOC_RT288X is not set\nCONFIG_SOC_RT305X=y\n# CONFIG_SOC_RT3883 is not set\nCONFIG_SPI=y\nCONFIG_SPI_MASTER=y\nCONFIG_SPI_MEM=y\n# CONFIG_SPI_MT7621 is not set\nCONFIG_SPI_RT2880=y\nCONFIG_SRCU=y\nCONFIG_SWCONFIG=y\nCONFIG_SWPHY=y\nCONFIG_SYSCTL_EXCEPTION_TRACE=y\nCONFIG_SYS_HAS_CPU_MIPS32_R1=y\nCONFIG_SYS_HAS_CPU_MIPS32_R2=y\nCONFIG_SYS_HAS_EARLY_PRINTK=y\nCONFIG_SYS_SUPPORTS_32BIT_KERNEL=y\nCONFIG_SYS_SUPPORTS_ARBIT_HZ=y\nCONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y\nCONFIG_SYS_SUPPORTS_MIPS16=y\nCONFIG_SYS_SUPPORTS_ZBOOT=y\nCONFIG_TARGET_ISA_REV=2\nCONFIG_TICK_CPU_ACCOUNTING=y\nCONFIG_TIMER_OF=y\nCONFIG_TIMER_PROBE=y\nCONFIG_TINY_SRCU=y\nCONFIG_USB_SUPPORT=y\nCONFIG_USE_OF=y\nCONFIG_WATCHDOG_CORE=y\n"
  },
  {
    "path": "target/linux/ramips/rt305x/target.mk",
    "content": "#\n# Copyright (C) 2009 OpenWrt.org\n#\n\nSUBTARGET:=rt305x\nBOARDNAME:=RT3x5x/RT5350 based boards\nFEATURES+=usb ramdisk small_flash\nCPU_TYPE:=24kc\n\nDEFAULT_PACKAGES += kmod-rt2800-soc wpad-basic-wolfssl swconfig\n\ndefine Target/Description\n\tBuild firmware images for Ralink RT3x5x/RT5350 based boards.\nendef\n\n"
  },
  {
    "path": "target/linux/ramips/rt3883/base-files/etc/board.d/01_leds",
    "content": "\n. /lib/functions/leds.sh\n. /lib/functions/uci-defaults.sh\n\nboard=$(board_name)\n\nboard_config_update\n\ncase $board in\nbelkin,f9k1109v1)\n\tucidef_set_led_netdev \"lan\" \"lan\" \"blue:wps\" \"eth0\"\n\t;;\nedimax,br-6475nd)\n\tucidef_set_led_netdev \"wifi_led\" \"wifi\" \"amber:wlan\" \"wlan0\"\n\t;;\nomnima,hpm)\n\tucidef_set_led_netdev \"eth\" \"ETH\" \"green:eth\" \"eth0\"\n\tucidef_set_led_netdev \"wifi_led\" \"wifi\" \"green:wifi\" \"wlan0\"\n\t;;\nesac\n\nboard_config_flush\n\nexit 0\n"
  },
  {
    "path": "target/linux/ramips/rt3883/base-files/etc/board.d/02_network",
    "content": "\n. /lib/functions.sh\n. /lib/functions/uci-defaults.sh\n. /lib/functions/system.sh\n\nramips_setup_interfaces()\n{\n\tlocal board=\"$1\"\n\n\tcase $board in\n\tasus,rt-n56u)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0:lan\" \"1:lan\" \"2:lan\" \"3:lan\" \"4:wan\" \"8@eth0\"\n\t\t;;\n\tbelkin,f9k1109v1)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0:lan\" \"1:lan\" \"2:lan\" \"3:lan\" \"4:wan\" \"5@eth0\"\n\t\t;;\n\tdlink,dir-645)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"1:lan\" \"2:lan\" \"3:lan\" \"4:lan\" \"0:wan\" \"6@eth0\"\n\t\t;;\n\tedimax,br-6475nd)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"1:lan\" \"2:lan\" \"3:lan\" \"4:lan\" \"0:wan\" \"9@eth0\"\n\t\t;;\n\tengenius,esr600h|\\\n\tsitecom,wlr-6000|\\\n\ttrendnet,tew-691gr|\\\n\ttrendnet,tew-692gr)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"1:lan\" \"2:lan\" \"3:lan\" \"4:lan\" \"5:wan\" \"0@eth0\"\n\t\t;;\n\tloewe,wmdr-143n|\\\n\tomnima,hpm)\n\t\tucidef_set_interface_lan \"eth0\"\n\t\t;;\n\tsamsung,cy-swr1100)\n\t\tucidef_add_switch \"switch0\" \\\n\t\t\t\"0:lan\" \"1:lan\" \"2:lan\" \"3:lan\" \"4:wan\" \"9@eth0\"\n\t\t;;\n\tesac\n}\n\nramips_setup_macs()\n{\n\tlocal board=\"$1\"\n\tlocal lan_mac=\"\"\n\tlocal wan_mac=\"\"\n\tlocal label_mac=\"\"\n\n\tcase $board in\n\tasus,rt-n56u)\n\t\tlan_mac=$(macaddr_setbit_la \"$(cat /sys/class/net/eth0/address)\")\n\t\twan_mac=$(mtd_get_mac_binary factory 0x8004)\n\t\t;;\n\tbelkin,f9k1109v1)\n\t\twan_mac=$(mtd_get_mac_ascii uboot-env HW_WAN_MAC)\n\t\tlan_mac=$(mtd_get_mac_ascii uboot-env HW_LAN_MAC)\n\t\tlabel_mac=$wan_mac\n\t\t;;\n\tdlink,dir-645)\n\t\tlan_mac=$(mtd_get_mac_ascii nvram lanmac)\n\t\twan_mac=$(mtd_get_mac_ascii nvram wanmac)\n\t\t;;\n\tedimax,br-6475nd)\n\t\twan_mac=$(mtd_get_mac_binary devdata 0x7)\n\t\t;;\n\tengenius,esr600h)\n\t\twan_mac=$(mtd_get_mac_ascii u-boot-env wanaddr)\n\t\tlan_mac=$(macaddr_add \"$wan_mac\" 1)\n\t\tlabel_mac=$wan_mac\n\t\t;;\n\tsamsung,cy-swr1100)\n\t\tlan_mac=$(mtd_get_mac_ascii nvram lanmac)\n\t\twan_mac=$(mtd_get_mac_ascii nvram wanmac)\n\t\tlabel_mac=$wan_mac\n\t\t;;\n\tsitecom,wlr-6000)\n\t\twan_mac=$(macaddr_add \"$(mtd_get_mac_binary factory 0x8004)\" 2)\n\t\t;;\n\ttrendnet,tew-691gr)\n\t\twan_mac=$(macaddr_add \"$(mtd_get_mac_binary factory 0x4)\" 3)\n\t\t;;\n\ttrendnet,tew-692gr)\n\t\twan_mac=$(macaddr_add \"$(mtd_get_mac_binary factory 0x4)\" 1)\n\t\t;;\n\tesac\n\n\t[ -n \"$lan_mac\" ] && ucidef_set_interface_macaddr \"lan\" $lan_mac\n\t[ -n \"$wan_mac\" ] && ucidef_set_interface_macaddr \"wan\" $wan_mac\n\t[ -n \"$label_mac\" ] && ucidef_set_label_macaddr $label_mac\n}\n\nboard_config_update\nboard=$(board_name)\nramips_setup_interfaces $board\nramips_setup_macs $board\nboard_config_flush\n\nexit 0\n"
  },
  {
    "path": "target/linux/ramips/rt3883/base-files/lib/preinit/04_handle_checksumming",
    "content": "# Netgear WNCE2001 has does a checksum check on boot and goes into recovery\n# tftp mode when the check fails.  Initializing the JFFS2 partition triggers\n# this, so we make sure to zero checksum and size to be checksummed before\n# that happens, so this needs to run very early during boot.\n\ndo_checksumming_disable() {\n\t. /lib/functions.sh\n\n\tlocal board=$(board_name)\n\n\tcase \"$board\" in\n\tasus,rt-n56u)\n\t\techo \"Board is ASUS RT-N56U, replacing uImage header...\"\n\t\tlocal firmware_mtd=$(find_mtd_part firmware)\n\t\tlocal rootfs_mtd=$(find_mtd_part rootfs)\n\t\tlocal rootfs_data_mtd=$(find_mtd_part rootfs_data)\n\t\tlocal rootfs_len=$(grep \\\"rootfs\\\" /proc/mtd | awk -F' ' '{print \"0x\"$2}')\n\t\tlocal rootfs_data_len=$(grep \\\"rootfs_data\\\" /proc/mtd | awk -F' ' '{print \"0x\"$2}')\n\t\tlocal offset=$(echo \"$rootfs_len $rootfs_data_len 0x40\" | awk -F' ' '{printf \"%i\",$1-$2-$3}')\n\t\tlocal signature=$(dd if=$rootfs_mtd skip=$offset bs=1 count=4 2>/dev/null | hexdump -v -n 4 -e '1/1 \"%02x\"')\n\t\tif [ \"$signature\" = \"27051956\" ]; then\n\t\t\tdd conv=notrunc if=$rootfs_mtd skip=$offset of=$firmware_mtd bs=1 count=64 2>/dev/null\n\t\tfi\n\t;;\n\tesac\n\n\treturn 0\n}\n\nboot_hook_add preinit_main do_checksumming_disable\n"
  },
  {
    "path": "target/linux/ramips/rt3883/base-files/lib/upgrade/platform.sh",
    "content": "#\n# Copyright (C) 2010 OpenWrt.org\n#\n\nPART_NAME=firmware\nREQUIRE_IMAGE_METADATA=1\n\nplatform_check_image() {\n\treturn 0\n}\n\nplatform_do_upgrade() {\n\tlocal board=$(board_name)\n\n\tcase \"$board\" in\n\t*)\n\t\tdefault_do_upgrade \"$1\"\n\t\t;;\n\tesac\n}\n"
  },
  {
    "path": "target/linux/ramips/rt3883/config-5.10",
    "content": "CONFIG_AR8216_PHY=y\nCONFIG_ARCH_32BIT_OFF_T=y\nCONFIG_ARCH_HIBERNATION_POSSIBLE=y\nCONFIG_ARCH_MMAP_RND_BITS_MAX=15\nCONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15\nCONFIG_ARCH_SUSPEND_POSSIBLE=y\nCONFIG_BLK_MQ_PCI=y\nCONFIG_CEVT_R4K=y\nCONFIG_CLKDEV_LOOKUP=y\nCONFIG_CLONE_BACKWARDS=y\nCONFIG_CMDLINE=\"rootfstype=squashfs,jffs2\"\nCONFIG_CMDLINE_BOOL=y\n# CONFIG_CMDLINE_OVERRIDE is not set\nCONFIG_COMPAT_32BIT_TIME=y\nCONFIG_CPU_GENERIC_DUMP_TLB=y\nCONFIG_CPU_HAS_DIEI=y\nCONFIG_CPU_HAS_PREFETCH=y\nCONFIG_CPU_HAS_RIXI=y\nCONFIG_CPU_HAS_SYNC=y\nCONFIG_CPU_MIPS32=y\n# CONFIG_CPU_MIPS32_R1 is not set\nCONFIG_CPU_MIPS32_R2=y\nCONFIG_CPU_MIPSR2=y\nCONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y\nCONFIG_CPU_R4K_CACHE_TLB=y\nCONFIG_CPU_SUPPORTS_32BIT_KERNEL=y\nCONFIG_CPU_SUPPORTS_HIGHMEM=y\nCONFIG_CPU_SUPPORTS_MSA=y\nCONFIG_CRYPTO_LIB_POLY1305_RSIZE=2\nCONFIG_CRYPTO_RNG2=y\nCONFIG_CSRC_R4K=y\nCONFIG_DEBUG_PINCTRL=y\nCONFIG_DMA_NONCOHERENT=y\n# CONFIG_DTB_RT3883_EVAL is not set\nCONFIG_DTB_RT_NONE=y\nCONFIG_DTC=y\nCONFIG_EARLY_PRINTK=y\nCONFIG_ETHERNET_PACKET_MANGLE=y\nCONFIG_FIXED_PHY=y\nCONFIG_FW_LOADER_PAGED_BUF=y\nCONFIG_GENERIC_ATOMIC64=y\nCONFIG_GENERIC_CLOCKEVENTS=y\nCONFIG_GENERIC_CMOS_UPDATE=y\nCONFIG_GENERIC_CPU_AUTOPROBE=y\nCONFIG_GENERIC_GETTIMEOFDAY=y\nCONFIG_GENERIC_IOMAP=y\nCONFIG_GENERIC_IRQ_CHIP=y\nCONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y\nCONFIG_GENERIC_IRQ_SHOW=y\nCONFIG_GENERIC_LIB_ASHLDI3=y\nCONFIG_GENERIC_LIB_ASHRDI3=y\nCONFIG_GENERIC_LIB_CMPDI2=y\nCONFIG_GENERIC_LIB_LSHRDI3=y\nCONFIG_GENERIC_LIB_UCMPDI2=y\nCONFIG_GENERIC_PCI_IOMAP=y\nCONFIG_GENERIC_PHY=y\nCONFIG_GENERIC_PINCONF=y\nCONFIG_GENERIC_SCHED_CLOCK=y\nCONFIG_GENERIC_SMP_IDLE_THREAD=y\nCONFIG_GENERIC_TIME_VSYSCALL=y\nCONFIG_GPIOLIB=y\nCONFIG_GPIO_RALINK=y\nCONFIG_HANDLE_DOMAIN_IRQ=y\nCONFIG_HARDWARE_WATCHPOINTS=y\nCONFIG_HAS_DMA=y\nCONFIG_HAS_IOMEM=y\nCONFIG_HAS_IOPORT_MAP=y\nCONFIG_HZ_PERIODIC=y\nCONFIG_INITRAMFS_SOURCE=\"\"\nCONFIG_IRQCHIP=y\nCONFIG_IRQ_DOMAIN=y\nCONFIG_IRQ_FORCED_THREADING=y\nCONFIG_IRQ_INTC=y\nCONFIG_IRQ_MIPS_CPU=y\nCONFIG_IRQ_WORK=y\n# CONFIG_KERNEL_ZSTD is not set\nCONFIG_LIBFDT=y\nCONFIG_LOCK_DEBUGGING_SUPPORT=y\nCONFIG_MDIO_BUS=y\nCONFIG_MDIO_DEVICE=y\nCONFIG_MEMFD_CREATE=y\nCONFIG_MFD_SYSCON=y\nCONFIG_MIGRATION=y\nCONFIG_MIPS=y\nCONFIG_MIPS_ASID_BITS=8\nCONFIG_MIPS_ASID_SHIFT=0\nCONFIG_MIPS_CBPF_JIT=y\nCONFIG_MIPS_CLOCK_VSYSCALL=y\n# CONFIG_MIPS_CMDLINE_BUILTIN_EXTEND is not set\n# CONFIG_MIPS_CMDLINE_DTB_EXTEND is not set\n# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set\nCONFIG_MIPS_CMDLINE_FROM_DTB=y\n# CONFIG_MIPS_ELF_APPENDED_DTB is not set\nCONFIG_MIPS_L1_CACHE_SHIFT=5\nCONFIG_MIPS_LD_CAN_LINK_VDSO=y\n# CONFIG_MIPS_NO_APPENDED_DTB is not set\nCONFIG_MIPS_RAW_APPENDED_DTB=y\nCONFIG_MIPS_SPRAM=y\nCONFIG_MODULES_USE_ELF_REL=y\n# CONFIG_MTD_CFI_INTELEXT is not set\nCONFIG_MTD_CMDLINE_PARTS=y\nCONFIG_MTD_PHYSMAP=y\nCONFIG_MTD_SPI_NOR=y\nCONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y\nCONFIG_MTD_SPI_NOR_USE_4K_SECTORS_LIMIT=16384\nCONFIG_MTD_SPLIT_SEAMA_FW=y\nCONFIG_MTD_SPLIT_UIMAGE_FW=y\nCONFIG_NEED_DMA_MAP_STATE=y\nCONFIG_NEED_PER_CPU_KM=y\nCONFIG_NET_RALINK_MDIO=y\nCONFIG_NET_RALINK_MDIO_RT2880=y\nCONFIG_NET_RALINK_RT3883=y\nCONFIG_NET_RALINK_SOC=y\nCONFIG_NET_VENDOR_RALINK=y\nCONFIG_NO_GENERIC_PCI_IOPORT_MAP=y\nCONFIG_NVMEM=y\nCONFIG_OF=y\nCONFIG_OF_ADDRESS=y\nCONFIG_OF_EARLY_FLATTREE=y\nCONFIG_OF_FLATTREE=y\nCONFIG_OF_GPIO=y\nCONFIG_OF_IRQ=y\nCONFIG_OF_KOBJ=y\nCONFIG_OF_MDIO=y\nCONFIG_OF_NET=y\nCONFIG_PCI=y\nCONFIG_PCI_DOMAINS=y\nCONFIG_PCI_DRIVERS_LEGACY=y\n# CONFIG_PCI_MT7621 is not set\n# CONFIG_PCI_MT7621_PHY is not set\nCONFIG_PERF_USE_VMALLOC=y\nCONFIG_PGTABLE_LEVELS=2\nCONFIG_PHYLIB=y\nCONFIG_PHY_RALINK_USB=y\nCONFIG_PINCTRL=y\n# CONFIG_PINCTRL_AW9523 is not set\nCONFIG_PINCTRL_RT2880=y\n# CONFIG_PINCTRL_SINGLE is not set\nCONFIG_RALINK=y\nCONFIG_RALINK_WDT=y\nCONFIG_REGMAP=y\nCONFIG_REGMAP_MMIO=y\nCONFIG_RESET_CONTROLLER=y\nCONFIG_RTL8366_SMI=y\nCONFIG_RTL8367B_PHY=y\nCONFIG_RTL8367_PHY=y\nCONFIG_SERIAL_8250_RT288X=y\nCONFIG_SERIAL_MCTRL_GPIO=y\nCONFIG_SERIAL_OF_PLATFORM=y\n# CONFIG_SOC_MT7620 is not set\n# CONFIG_SOC_MT7621 is not set\n# CONFIG_SOC_RT288X is not set\n# CONFIG_SOC_RT305X is not set\nCONFIG_SOC_RT3883=y\nCONFIG_SPI=y\nCONFIG_SPI_MASTER=y\nCONFIG_SPI_MEM=y\n# CONFIG_SPI_MT7621 is not set\nCONFIG_SPI_RT2880=y\nCONFIG_SRCU=y\nCONFIG_SWCONFIG=y\nCONFIG_SWPHY=y\nCONFIG_SYSCTL_EXCEPTION_TRACE=y\nCONFIG_SYS_HAS_CPU_MIPS32_R1=y\nCONFIG_SYS_HAS_CPU_MIPS32_R2=y\nCONFIG_SYS_HAS_EARLY_PRINTK=y\nCONFIG_SYS_SUPPORTS_32BIT_KERNEL=y\nCONFIG_SYS_SUPPORTS_ARBIT_HZ=y\nCONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y\nCONFIG_SYS_SUPPORTS_MIPS16=y\nCONFIG_SYS_SUPPORTS_ZBOOT=y\nCONFIG_TARGET_ISA_REV=2\nCONFIG_TICK_CPU_ACCOUNTING=y\nCONFIG_TINY_SRCU=y\nCONFIG_USB_SUPPORT=y\nCONFIG_USE_OF=y\nCONFIG_WATCHDOG_CORE=y\n"
  },
  {
    "path": "target/linux/ramips/rt3883/target.mk",
    "content": "#\n# Copyright (C) 2011 OpenWrt.org\n#\n\nSUBTARGET:=rt3883\nBOARDNAME:=RT3662/RT3883 based boards\nFEATURES+=usb pci small_flash\nCPU_TYPE:=74kc\n\nDEFAULT_PACKAGES += kmod-rt2800-pci kmod-rt2800-soc wpad-basic-wolfssl swconfig\n\ndefine Target/Description\n\tBuild firmware images for Ralink RT3662/RT3883 based boards.\nendef\n\n"
  },
  {
    "path": "target/linux/realtek/Makefile",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n\ninclude $(TOPDIR)/rules.mk\n\nARCH:=mips\nBOARD:=realtek\nBOARDNAME:=Realtek MIPS\nDEVICE_TYPE:=basic\nFEATURES:=ramdisk squashfs\nSUBTARGETS:=rtl838x rtl839x rtl930x rtl931x\n\nKERNEL_PATCHVER:=5.10\n\ndefine Target/Description\n\tBuild firmware images for Realtek RTL83xx based boards.\nendef\n\ninclude $(INCLUDE_DIR)/target.mk\n\nDEFAULT_PACKAGES += uboot-envtools ethtool kmod-gpio-button-hotplug \\\n\tfirewall4 nftables kmod-nft-offload odhcp6c \\\n\tip-full ip-bridge tc-bpf\n\n$(eval $(call BuildTarget))\n"
  },
  {
    "path": "target/linux/realtek/base-files/etc/board.d/01_leds",
    "content": "\n. /lib/functions/uci-defaults.sh\n\nboard=$(board_name)\n\nboard_config_update\n\ncase $board in\nesac\n\nboard_config_flush\n\nexit 0\n"
  },
  {
    "path": "target/linux/realtek/base-files/etc/board.d/02_network",
    "content": "\n. /lib/functions.sh\n. /lib/functions/uci-defaults.sh\n. /lib/functions/system.sh\n\nucidef_set_poe() {\n\tjson_select_object poe\n\t\tjson_add_string \"budget\" \"$1\"\n\t\tjson_select_array ports\n\t\t\tfor port in $2; do\n\t\t\t\tjson_add_string \"\" \"$port\"\n\t\t\tdone\n\t\tjson_select ..\n\tjson_select ..\n}\n\nboard=$(board_name)\nboard_config_update\n\nlan_list=$(ls -1 -v -d /sys/class/net/lan* | xargs -n1 basename | xargs)\nucidef_set_bridge_device switch\nucidef_set_interface_lan \"$lan_list\"\n\nlan_mac=\"\"\nlan_mac_end=\"\"\nlabel_mac=\"\"\ncase $board in\n*)\n\tlan_mac=$(mtd_get_mac_ascii u-boot-env2 mac_start)\n\tlan_mac_end=$(mtd_get_mac_ascii u-boot-env2 mac_end)\n\tlabel_mac=$(mtd_get_mac_ascii u-boot-env ethaddr)\n\t[ -z \"$lan_mac\" ] && lan_mac=$label_mac\n\t;;\nesac\n\nucidef_set_interface_macaddr \"lan\" $lan_mac\nucidef_set_bridge_mac \"$lan_mac\"\nucidef_set_network_device_mac eth0 $lan_mac\nfor lan in $lan_list; do\n\tucidef_set_network_device_mac $lan $lan_mac\n\t[ -z \"$lan_mac_end\" ] || [ \"$lan_mac\" == \"$lan_mac_end\" ] && lan_mac=$(macaddr_setbit_la $lan_mac)\n\tlan_mac=$(macaddr_add $lan_mac 1)\ndone\n[ -n \"$label_mac\" ] && ucidef_set_label_macaddr $label_mac\n\ncase $board in\nnetgear,gs110tpp-v1)\n\tucidef_set_poe 130 \"$lan_list\"\n\t;;\nnetgear,gs310tp-v1)\n\tucidef_set_poe 55 \"$lan_list\"\n\t;;\nzyxel,gs1900-10hp)\n\tucidef_set_poe 77 \"$lan_list\"\n\t;;\nzyxel,gs1900-8hp-v1|\\\nzyxel,gs1900-8hp-v2)\n\tucidef_set_poe 70 \"$lan_list\"\n\t;;\nzyxel,gs1900-24hp-v1|\\\nzyxel,gs1900-24hp-v2)\n\tucidef_set_poe 170 \"$lan_list\"\n\t;;\nesac\n\nboard_config_flush\n\nexit 0\n"
  },
  {
    "path": "target/linux/realtek/base-files/etc/inittab",
    "content": "::sysinit:/etc/init.d/rcS S boot\n::shutdown:/etc/init.d/rcS K shutdown\n::askconsole:/usr/libexec/login.sh\n"
  },
  {
    "path": "target/linux/realtek/base-files/lib/upgrade/platform.sh",
    "content": "PART_NAME=firmware\nREQUIRE_IMAGE_METADATA=1\n\nRAMFS_COPY_BIN='fw_printenv fw_setenv'\nRAMFS_COPY_DATA='/etc/fw_env.config /var/lock/fw_printenv.lock'\n\nplatform_check_image() {\n\treturn 0\n}\n\nplatform_do_upgrade() {\n\tlocal board=$(board_name)\n\n\tcase \"$board\" in\n\t*)\n\t\tdefault_do_upgrade \"$1\"\n\t\t;;\n\tesac\n}\n"
  },
  {
    "path": "target/linux/realtek/dts-5.10/rtl8380_netgear_gigabit.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later\n\n#include \"rtl838x.dtsi\"\n\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/gpio/gpio.h>\n\n/ {\n\tcompatible = \"realtek,rtl838x-soc\";\n\n\tmemory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x0 0x8000000>;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\tmode {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tgpio-restart {\n\t\tcompatible = \"gpio-restart\";\n\t\tgpios = <&gpio0 13 GPIO_ACTIVE_LOW>;\n\t\topen-source;\n\t};\n\n\tgpio1: rtl8231-gpio {\n\t\tcompatible = \"realtek,rtl8231-gpio\";\n\t\t#gpio-cells = <2>;\n\t\tgpio-controller;\n\t\tindirect-access-bus-id = <31>;\n\t};\n};\n\n&ethernet0 {\n\tmdio: mdio-bus {\n\t\tcompatible = \"realtek,rtl838x-mdio\";\n\t\tregmap = <&ethernet0>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tINTERNAL_PHY(8)\n\t\tINTERNAL_PHY(9)\n\t\tINTERNAL_PHY(10)\n\t\tINTERNAL_PHY(11)\n\t\tINTERNAL_PHY(12)\n\t\tINTERNAL_PHY(13)\n\t\tINTERNAL_PHY(14)\n\t\tINTERNAL_PHY(15)\n\t};\n};\n\n&switch0 {\n\tports {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tSWITCH_PORT(8, 1, internal)\n\t\tSWITCH_PORT(9, 2, internal)\n\t\tSWITCH_PORT(10, 3, internal)\n\t\tSWITCH_PORT(11, 4, internal)\n\t\tSWITCH_PORT(12, 5, internal)\n\t\tSWITCH_PORT(13, 6, internal)\n\t\tSWITCH_PORT(14, 7, internal)\n\t\tSWITCH_PORT(15, 8, internal)\n\n\t\tport@28 {\n\t\t\tethernet = <&ethernet0>;\n\t\t\treg = <28>;\n\t\t\tphy-mode = \"internal\";\n\t\t\tfixed-link {\n\t\t\t\tspeed = <1000>;\n\t\t\t\tfull-duplex;\n\t\t\t};\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/realtek/dts-5.10/rtl8380_netgear_gigabit_1xx.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later\n\n#include \"rtl8380_netgear_gigabit.dtsi\"\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <50000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0000000 0x00e0000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@e0000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x00e0000 0x0010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@f0000 {\n\t\t\t\tlabel = \"u-boot-env2\";\n\t\t\t\treg = <0x00f0000 0x0010000>;\n\t\t\t};\n\n\t\t\tpartition@100000 {\n\t\t\t\tlabel = \"jffs\";\n\t\t\t\treg = <0x0100000 0x0100000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@200000 {\n\t\t\t\tlabel = \"jffs2\";\n\t\t\t\treg = <0x0200000 0x0100000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@300000 {\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\tcompatible = \"openwrt,uimage\", \"denx,uimage\";\n\t\t\t\topenwrt,ih-magic = <0x4e474520>;\n\t\t\t\treg = <0x0300000 0x0e80000>;\n\t\t\t};\n\n\t\t\tpartition@1180000 {\n\t\t\t\tlabel = \"runtime2\";\n\t\t\t\treg = <0x1180000 0x0e80000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/realtek/dts-5.10/rtl8380_netgear_gigabit_3xx.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later\n\n#include \"rtl8380_netgear_gigabit.dtsi\"\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <50000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0000000 0x00e0000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@e0000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x00e0000 0x0010000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@f0000 {\n\t\t\t\tlabel = \"u-boot-env2\";\n\t\t\t\treg = <0x00f0000 0x0010000>;\n\t\t\t};\n\n\t\t\tpartition@100000 {\n\t\t\t\tlabel = \"jffs\";\n\t\t\t\treg = <0x0100000 0x0100000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@200000 {\n\t\t\t\tlabel = \"jffs2\";\n\t\t\t\treg = <0x0200000 0x0100000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@300000 {\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\tcompatible = \"openwrt,uimage\", \"denx,uimage\";\n\t\t\t\topenwrt,ih-magic = <0x4e474335>;\n\t\t\t\treg = <0x0300000 0x0e80000>;\n\t\t\t};\n\n\t\t\tpartition@1180000 {\n\t\t\t\tlabel = \"runtime2\";\n\t\t\t\treg = <0x1180000 0x0e80000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/realtek/dts-5.10/rtl8380_netgear_gs108t-v3.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later\n\n#include \"rtl8380_netgear_gigabit_1xx.dtsi\"\n\n/ {\n\tcompatible = \"netgear,gs108t-v3\", \"realtek,rtl838x-soc\";\n\tmodel = \"Netgear GS108T v3\";\n};\n"
  },
  {
    "path": "target/linux/realtek/dts-5.10/rtl8380_netgear_gs110tpp-v1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later\n\n#include \"rtl8380_netgear_gigabit_1xx.dtsi\"\n#include <dt-bindings/leds/common.h>\n\n/ {\n\tcompatible = \"netgear,gs110tpp-v1\", \"realtek,rtl838x-soc\";\n\tmodel = \"Netgear GS110TPP v1\";\n\n\taliases {\n\t\tled-boot = &led_status_green;\n\t\tled-failsafe = &led_status_red;\n\t\tled-running = &led_status_green;\n\t\tled-upgrade = &led_status_blue;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_status_red: led-0 {\n\t\t\tlabel = \"red:status\";\n\t\t\tcolor = <LED_COLOR_ID_RED>;\n\t\t\tfunction = LED_FUNCTION_STATUS;\n\t\t\tgpios = <&gpio1 31 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_status_green: led-1 {\n\t\t\tlabel = \"green:status\";\n\t\t\tcolor = <LED_COLOR_ID_GREEN>;\n\t\t\tfunction = LED_FUNCTION_STATUS;\n\t\t\tgpios = <&gpio1 32 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tled_status_blue: led-2 {\n\t\t\tlabel = \"blue:status\";\n\t\t\tcolor = <LED_COLOR_ID_BLUE>;\n\t\t\tfunction = LED_FUNCTION_STATUS;\n\t\t\tgpios = <&gpio1 34 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&uart1 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/realtek/dts-5.10/rtl8380_netgear_gs308t-v1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later\n\n#include \"rtl8380_netgear_gigabit_3xx.dtsi\"\n\n/ {\n\tcompatible = \"netgear,gs308t-v1\", \"realtek,rtl838x-soc\";\n\tmodel = \"Netgear GS308T v1\";\n};\n"
  },
  {
    "path": "target/linux/realtek/dts-5.10/rtl8380_netgear_gs310tp-v1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later\n\n#include \"rtl8380_netgear_gigabit_3xx.dtsi\"\n\n/ {\n\tcompatible = \"netgear,gs310tp-v1\", \"realtek,rtl838x-soc\";\n\tmodel = \"Netgear GS310TP v1\";\n\n};\n\n&uart1 {\n\tstatus = \"okay\";\n};\n\n&mdio {\n\tINTERNAL_PHY(24)\n\tINTERNAL_PHY(26)\n};\n\n&switch0 {\n\tports {\n\t\tSWITCH_SFP_PORT(24, 9, rgmii-id)\n\t\tSWITCH_SFP_PORT(26, 10, rgmii-id)\n\t};\n};\n"
  },
  {
    "path": "target/linux/realtek/dts-5.10/rtl8380_panasonic_m8eg-pn28080k.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"rtl838x.dtsi\"\n#include \"rtl83xx_panasonic_mxxeg-pn28xx0k.dtsi\"\n\n#include <dt-bindings/interrupt-controller/irq.h>\n\n/ {\n\tcompatible = \"panasonic,m8eg-pn28080k\", \"realtek,rtl8380-soc\";\n\tmodel = \"Panasonic Switch-M8eG PN28080K\";\n\n\taliases {\n\t\tled-boot = &led_status_eco_green;\n\t\tled-failsafe = &led_status_eco_amber;\n\t\tled-running = &led_status_eco_green;\n\t\tled-upgrade = &led_status_eco_green;\n\t};\n\n\tsfp0: sfp-p9 {\n\t\tcompatible = \"sff,sfp\";\n\t\ti2c-bus = <&i2c0>;\n\t\ttx-fault-gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>;\n\t\ttx-disable-gpio = <&gpio1 1 GPIO_ACTIVE_HIGH>;\n\t\tmod-def0-gpio = <&gpio1 2 GPIO_ACTIVE_LOW>;\n\t\tlos-gpio = <&gpio1 3 GPIO_ACTIVE_HIGH>;\n\t};\n};\n\n&leds {\n\tled_status_eco_amber: led-5 {\n\t\tlabel = \"amber:status_eco\";\n\t\tgpios = <&gpio2 1 GPIO_ACTIVE_LOW>;\n\t\tcolor = <LED_COLOR_ID_AMBER>;\n\t\tfunction = LED_FUNCTION_STATUS;\n\t\tfunction-enumerator = <1>;\n\t};\n\n\tled_status_eco_green: led-6 {\n\t\tlabel = \"green:status_eco\";\n\t\tgpios = <&gpio2 2 GPIO_ACTIVE_LOW>;\n\t\tcolor = <LED_COLOR_ID_GREEN>;\n\t\tfunction = LED_FUNCTION_STATUS;\n\t\tfunction-enumerator = <2>;\n\t};\n};\n\n&i2c_gpio_0 {\n\tscl-gpios = <&gpio0 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\tsda-gpios = <&gpio0 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n};\n\n&i2c_gpio_1 {\n\tscl-gpios = <&gpio0 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\tsda-gpios = <&gpio0 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n};\n\n&gpio1 {\n\tinterrupt-controller;\n\t#interrupt-cells = <2>;\n\tinterrupt-parent = <&gpio0>;\n\tinterrupts = <2 IRQ_TYPE_EDGE_FALLING>;\n};\n\n&gpio2 {\n\tinterrupt-controller;\n\t#interrupt-cells = <2>;\n\tinterrupt-parent = <&gpio0>;\n\tinterrupts = <2 IRQ_TYPE_EDGE_FALLING>;\n};\n\n&i2c_switch {\n\ti2c0: i2c@0 {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\treg = <0>;\n\t};\n};\n\n&ethernet0 {\n\tmdio-bus {\n\t\tcompatible = \"realtek,rtl838x-mdio\";\n\t\tregmap = <&ethernet0>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tINTERNAL_PHY(8)\n\t\tINTERNAL_PHY(9)\n\t\tINTERNAL_PHY(10)\n\t\tINTERNAL_PHY(11)\n\t\tINTERNAL_PHY(12)\n\t\tINTERNAL_PHY(13)\n\t\tINTERNAL_PHY(14)\n\t\tINTERNAL_PHY(15)\n\n\t\tINTERNAL_PHY(24)\n\t};\n};\n\n&switch0 {\n\tports {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tSWITCH_PORT(8, 1, internal)\n\t\tSWITCH_PORT(9, 2, internal)\n\t\tSWITCH_PORT(10, 3, internal)\n\t\tSWITCH_PORT(11, 4, internal)\n\t\tSWITCH_PORT(12, 5, internal)\n\t\tSWITCH_PORT(13, 6, internal)\n\t\tSWITCH_PORT(14, 7, internal)\n\t\tSWITCH_PORT(15, 8, internal)\n\n\t\tport@24 {\n\t\t\treg = <24>;\n\t\t\tlabel = \"lan9\";\n\t\t\tphy-mode = \"1000base-x\";\n\t\t\tphy-handle = <&phy24>;\n\t\t\tmanaged = \"in-band-status\";\n\t\t\tsfp = <&sfp0>;\n\t\t};\n\n\t\tport@28 {\n\t\t\tethernet = <&ethernet0>;\n\t\t\treg = <28>;\n\t\t\tphy-mode = \"internal\";\n\n\t\t\tfixed-link {\n\t\t\t\tspeed = <1000>;\n\t\t\t\tfull-duplex;\n\t\t\t};\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/realtek/dts-5.10/rtl8380_zyxel_gs1900-10hp.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later\n\n#include \"rtl8380_zyxel_gs1900.dtsi\"\n\n/ {\n\tcompatible = \"zyxel,gs1900-10hp\", \"realtek,rtl838x-soc\";\n\tmodel = \"ZyXEL GS1900-10HP Switch\";\n\n\t/* i2c of the left SFP cage: port 9 */\n\ti2c0: i2c-gpio-0 {\n\t\tcompatible = \"i2c-gpio\";\n\t\tsda-gpios = <&gpio1 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\t\tscl-gpios = <&gpio1 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\t\ti2c-gpio,delay-us = <2>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t};\n\n\tsfp0: sfp-p9 {\n\t\tcompatible = \"sff,sfp\";\n\t\ti2c-bus = <&i2c0>;\n\t\tlos-gpio = <&gpio1 27 GPIO_ACTIVE_HIGH>;\n\t\ttx-fault-gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>;\n\t\tmod-def0-gpio = <&gpio1 26 GPIO_ACTIVE_LOW>;\n\t\ttx-disable-gpio = <&gpio1 23 GPIO_ACTIVE_HIGH>;\n\t};\n\n\t/* i2c of the right SFP cage: port 10 */\n\ti2c1: i2c-gpio-1 {\n\t\tcompatible = \"i2c-gpio\";\n\t\tsda-gpios = <&gpio1 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\t\tscl-gpios = <&gpio1 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\t\ti2c-gpio,delay-us = <2>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t};\n\n\tsfp1: sfp-p10 {\n\t\tcompatible = \"sff,sfp\";\n\t\ti2c-bus = <&i2c1>;\n\t\tlos-gpio = <&gpio1 33 GPIO_ACTIVE_HIGH>;\n\t\ttx-fault-gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>;\n\t\tmod-def0-gpio = <&gpio1 32 GPIO_ACTIVE_LOW>;\n\t\ttx-disable-gpio = <&gpio1 29 GPIO_ACTIVE_HIGH>;\n\t};\n};\n\n&uart1 {\n\tstatus = \"okay\";\n};\n\n&mdio {\n\tINTERNAL_PHY(24)\n\tINTERNAL_PHY(26)\n};\n\n&switch0 {\n\tports {\n\t\tport@24 {\n\t\t\treg = <24>;\n\t\t\tlabel = \"lan9\";\n\t\t\tphy-mode = \"1000base-x\";\n\t\t\tmanaged = \"in-band-status\";\n\t\t\tsfp = <&sfp0>;\n\t\t};\n\n\t\tport@26 {\n\t\t\treg = <26>;\n\t\t\tlabel = \"lan10\";\n\t\t\tphy-mode = \"1000base-x\";\n\t\t\tmanaged = \"in-band-status\";\n\t\t\tsfp = <&sfp1>;\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/realtek/dts-5.10/rtl8380_zyxel_gs1900-8.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later\n\n#include \"rtl8380_zyxel_gs1900.dtsi\"\n\n/ {\n\tcompatible = \"zyxel,gs1900-8\", \"realtek,rtl838x-soc\";\n\tmodel = \"ZyXEL GS1900-8 Switch\";\n};\n\n&gpio1 {\n\t/delete-node/ poe_enable;\n};\n"
  },
  {
    "path": "target/linux/realtek/dts-5.10/rtl8380_zyxel_gs1900-8hp-v1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later\n\n#include \"rtl8380_zyxel_gs1900.dtsi\"\n\n/ {\n\tcompatible = \"zyxel,gs1900-8hp-v1\", \"realtek,rtl838x-soc\";\n\tmodel = \"ZyXEL GS1900-8HP v1 Switch\";\n};\n\n&uart1 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/realtek/dts-5.10/rtl8380_zyxel_gs1900-8hp-v2.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later\n\n#include \"rtl8380_zyxel_gs1900.dtsi\"\n\n/ {\n\tcompatible = \"zyxel,gs1900-8hp-v2\", \"realtek,rtl838x-soc\";\n\tmodel = \"ZyXEL GS1900-8HP v2 Switch\";\n};\n\n&uart1 {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/realtek/dts-5.10/rtl8380_zyxel_gs1900.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later\n\n#include \"rtl838x.dtsi\"\n\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/gpio/gpio.h>\n\n/ {\n\taliases {\n\t\tled-boot = &led_sys;\n\t\tled-failsafe = &led_sys;\n\t\tled-running = &led_sys;\n\t\tled-upgrade = &led_sys;\n\t};\n\n\tmemory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x0 0x8000000>;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio1 3 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tleds {\n\t\tpinctrl-names = \"default\";\n\t\tpinctrl-0 = <&pinmux_disable_sys_led>;\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_sys: sys {\n\t\t\tlabel = \"green:sys\";\n\t\t\tgpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n\n\tgpio1: rtl8231-gpio {\n\t\tcompatible = \"realtek,rtl8231-gpio\";\n\t\t#gpio-cells = <2>;\n\t\tgpio-controller;\n\t\tindirect-access-bus-id = <0>;\n\n\t\tpoe_enable {\n\t\t\tgpio-hog;\n\t\t\tgpios = <13 GPIO_ACTIVE_HIGH>;\n\t\t\toutput-high;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x40000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@50000 {\n\t\t\t\tlabel = \"u-boot-env2\";\n\t\t\t\treg = <0x50000 0x10000>;\n\t\t\t};\n\t\t\tpartition@60000 {\n\t\t\t\tlabel = \"jffs\";\n\t\t\t\treg = <0x60000 0x100000>;\n\t\t\t};\n\t\t\tpartition@160000 {\n\t\t\t\tlabel = \"jffs2\";\n\t\t\t\treg = <0x160000 0x100000>;\n\t\t\t};\n\t\t\tpartition@b260000 {\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x260000 0x6d0000>;\n\t\t\t\tcompatible = \"openwrt,uimage\", \"denx,uimage\";\n\t\t\t\topenwrt,ih-magic = <0x83800000>;\n\t\t\t};\n\t\t\tpartition@930000 {\n\t\t\t\tlabel = \"runtime2\";\n\t\t\t\treg = <0x930000 0x6d0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&ethernet0 {\n\tmdio: mdio-bus {\n\t\tcompatible = \"realtek,rtl838x-mdio\";\n\t\tregmap = <&ethernet0>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tINTERNAL_PHY(8)\n\t\tINTERNAL_PHY(9)\n\t\tINTERNAL_PHY(10)\n\t\tINTERNAL_PHY(11)\n\t\tINTERNAL_PHY(12)\n\t\tINTERNAL_PHY(13)\n\t\tINTERNAL_PHY(14)\n\t\tINTERNAL_PHY(15)\n\t};\n};\n\n&switch0 {\n\tports {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tSWITCH_PORT(8, 1, internal)\n\t\tSWITCH_PORT(9, 2, internal)\n\t\tSWITCH_PORT(10, 3, internal)\n\t\tSWITCH_PORT(11, 4, internal)\n\t\tSWITCH_PORT(12, 5, internal)\n\t\tSWITCH_PORT(13, 6, internal)\n\t\tSWITCH_PORT(14, 7, internal)\n\t\tSWITCH_PORT(15, 8, internal)\n\n\t\tport@28 {\n\t\t\tethernet = <&ethernet0>;\n\t\t\treg = <28>;\n\t\t\tphy-mode = \"internal\";\n\n\t\t\tfixed-link {\n\t\t\t\tspeed = <1000>;\n\t\t\t\tfull-duplex;\n\t\t\t};\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/realtek/dts-5.10/rtl8382_allnet_all-sg8208m.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later\n\n#include \"rtl838x.dtsi\"\n\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/gpio/gpio.h>\n\n/ {\n\tcompatible = \"allnet,all-sg8208m\", \"realtek,rtl838x-soc\";\n\tmodel = \"ALLNET ALL-SG8208M\";\n\n\taliases {\n\t\tled-boot = &led_sys;\n\t\tled-failsafe = &led_sys;\n\t\tled-running = &led_sys;\n\t\tled-upgrade = &led_sys;\n\t};\n\n\tmemory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x0 0x8000000>;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <20>;\n\n\t\t/* is this pin 3 on the external RTL8231 (&gpio1)? */\n\t\t/*reset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 67 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};*/\n\t};\n\n\tleds {\n\t\tpinctrl-names = \"default\";\n\t\tpinctrl-0 = <&pinmux_disable_sys_led>;\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_sys: sys {\n\t\t\tlabel = \"green:sys\";\n\t\t\tgpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t\t// GPIO 25: power on/off all port leds\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x80000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@80000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x80000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@90000 {\n\t\t\t\tlabel = \"u-boot-env2\";\n\t\t\t\treg = <0x90000 0x10000>;\n\t\t\t};\n\n\t\t\tpartition@a0000 {\n\t\t\t\tlabel = \"jffs\";\n\t\t\t\treg = <0xa0000 0x100000>;\n\t\t\t};\n\n\t\t\tpartition@1a0000 {\n\t\t\t\tlabel = \"jffs2\";\n\t\t\t\treg = <0x1a0000 0x100000>;\n\t\t\t};\n\n\t\t\tpartition@2a0000 {\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x2a0000 0xd60000>;\n\t\t\t\tcompatible = \"openwrt,uimage\", \"denx,uimage\";\n\t\t\t\topenwrt,ih-magic = <0x00000006>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&ethernet0 {\n\tmdio: mdio-bus {\n\t\tcompatible = \"realtek,rtl838x-mdio\";\n\t\tregmap = <&ethernet0>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tINTERNAL_PHY(8)\n\t\tINTERNAL_PHY(9)\n\t\tINTERNAL_PHY(10)\n\t\tINTERNAL_PHY(11)\n\t\tINTERNAL_PHY(12)\n\t\tINTERNAL_PHY(13)\n\t\tINTERNAL_PHY(14)\n\t\tINTERNAL_PHY(15)\n\t};\n};\n\n&switch0 {\n\tports {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tSWITCH_PORT(8, 1, internal)\n\t\tSWITCH_PORT(9, 2, internal)\n\t\tSWITCH_PORT(10, 3, internal)\n\t\tSWITCH_PORT(11, 4, internal)\n\t\tSWITCH_PORT(12, 5, internal)\n\t\tSWITCH_PORT(13, 6, internal)\n\t\tSWITCH_PORT(14, 7, internal)\n\t\tSWITCH_PORT(15, 8, internal)\n\n\t\tport@28 {\n\t\t\tethernet = <&ethernet0>;\n\t\t\treg = <28>;\n\t\t\tphy-mode = \"internal\";\n\t\t\tfixed-link {\n\t\t\t\tspeed = <1000>;\n\t\t\t\tfull-duplex;\n\t\t\t};\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/realtek/dts-5.10/rtl8382_d-link_dgs-1210-10p.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"rtl838x.dtsi\"\n\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/gpio/gpio.h>\n\n/ {\n\tcompatible = \"d-link,dgs-1210-10p\", \"realtek,rtl838x-soc\";\n\tmodel = \"D-Link DGS-1210-10P\";\n\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tmemory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x0 0x8000000>;\n\t};\n\n\tleds {\n\t\tpinctrl-names = \"default\";\n\t\tpinctrl-0 = <&pinmux_disable_sys_led>;\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\t// GPIO 0 seems to provide power to the leds\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio0 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <20>;\n\n\t\t/* is this pin 30 on the external RTL8231 (&gpio1)? */\n\t\t/*mode {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 94 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};*/\n\t};\n\n\tgpio1: rtl8231-gpio {\n\t\tcompatible = \"realtek,rtl8231-gpio\";\n\t\t#gpio-cells = <2>;\n\t\tgpio-controller;\n\t\tindirect-access-bus-id = <0>;\n\t};\n};\n\n\n&spi0 {\n\tstatus = \"okay\";\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x00000000 0x80000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@80000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x00080000 0x40000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@c0000 {\n\t\t\t\tlabel = \"u-boot-env2\";\n\t\t\t\treg = <0x000c0000 0x40000>;\n\t\t\t};\n\t\t\tpartition@280000 {\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\treg = <0x00100000 0xd80000>;\n\t\t\t};\n\t\t\tpartition@be80000 {\n\t\t\t\tlabel = \"kernel2\";\n\t\t\t\treg = <0x00e80000 0x180000>;\n\t\t\t};\n\t\t\tpartition@1000000 {\n\t\t\t\tlabel = \"sysinfo\";\n\t\t\t\treg = <0x01000000 0x40000>;\n\t\t\t};\n\t\t\tpartition@1040000 {\n\t\t\t\tlabel = \"rootfs2\";\n\t\t\t\treg = <0x01040000 0xc00000>;\n\t\t\t};\n\t\t\tpartition@1c40000 {\n\t\t\t\tlabel = \"jffs2\";\n\t\t\t\treg = <0x01c40000 0x3c0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&uart1 {\n\tstatus = \"okay\";\n};\n\n&ethernet0 {\n\tmdio: mdio-bus {\n\t\tcompatible = \"realtek,rtl838x-mdio\";\n\t\tregmap = <&ethernet0>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tINTERNAL_PHY(8)\n\t\tINTERNAL_PHY(9)\n\t\tINTERNAL_PHY(10)\n\t\tINTERNAL_PHY(11)\n\t\tINTERNAL_PHY(12)\n\t\tINTERNAL_PHY(13)\n\t\tINTERNAL_PHY(14)\n\t\tINTERNAL_PHY(15)\n\t\tINTERNAL_PHY(24)\n\t\tINTERNAL_PHY(26)\n\t};\n};\n\n&switch0 {\n\tports {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tSWITCH_PORT(8, 1, internal)\n\t\tSWITCH_PORT(9, 2, internal)\n\t\tSWITCH_PORT(10, 3, internal)\n\t\tSWITCH_PORT(11, 4, internal)\n\t\tSWITCH_PORT(12, 5, internal)\n\t\tSWITCH_PORT(13, 6, internal)\n\t\tSWITCH_PORT(14, 7, internal)\n\t\tSWITCH_PORT(15, 8, internal)\n\t\tSWITCH_SFP_PORT(24, 9, rgmii-id)\n\t\tSWITCH_SFP_PORT(26, 10, rgmii-id)\n\n\t\tport@28 {\n\t\t\tethernet = <&ethernet0>;\n\t\t\treg = <28>;\n\t\t\tphy-mode = \"internal\";\n\t\t\tfixed-link {\n\t\t\t\tspeed = <1000>;\n\t\t\t\tfull-duplex;\n\t\t\t};\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/realtek/dts-5.10/rtl8382_d-link_dgs-1210-16.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"rtl8382_d-link_dgs-1210.dtsi\"\n\n/ {\n\tcompatible = \"d-link,dgs-1210-16\", \"realtek,rtl838x-soc\";\n\tmodel = \"D-Link DGS-1210-16\";\n};\n\n&ethernet0 {\n\tmdio: mdio-bus {\n\t\tcompatible = \"realtek,rtl838x-mdio\";\n\t\tregmap = <&ethernet0>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tEXTERNAL_PHY(0)\n\t\tEXTERNAL_PHY(1)\n\t\tEXTERNAL_PHY(2)\n\t\tEXTERNAL_PHY(3)\n\t\tEXTERNAL_PHY(4)\n\t\tEXTERNAL_PHY(5)\n\t\tEXTERNAL_PHY(6)\n\t\tEXTERNAL_PHY(7)\n\n\t\tINTERNAL_PHY(8)\n\t\tINTERNAL_PHY(9)\n\t\tINTERNAL_PHY(10)\n\t\tINTERNAL_PHY(11)\n\t\tINTERNAL_PHY(12)\n\t\tINTERNAL_PHY(13)\n\t\tINTERNAL_PHY(14)\n\t\tINTERNAL_PHY(15)\n\n\t\tEXTERNAL_SFP_PHY(24)\n\t\tEXTERNAL_SFP_PHY(25)\n\t\tEXTERNAL_SFP_PHY(26)\n\t\tEXTERNAL_SFP_PHY(27)\n\t};\n};\n\n&switch0 {\n\tports {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tSWITCH_PORT(0, 1, qsgmii)\n\t\tSWITCH_PORT(1, 2, qsgmii)\n\t\tSWITCH_PORT(2, 3, qsgmii)\n\t\tSWITCH_PORT(3, 4, qsgmii)\n\t\tSWITCH_PORT(4, 5, qsgmii)\n\t\tSWITCH_PORT(5, 6, qsgmii)\n\t\tSWITCH_PORT(6, 7, qsgmii)\n\t\tSWITCH_PORT(7, 8, qsgmii)\n\n\t\tSWITCH_PORT(8, 9, internal)\n\t\tSWITCH_PORT(9, 10, internal)\n\t\tSWITCH_PORT(10, 11, internal)\n\t\tSWITCH_PORT(11, 12, internal)\n\t\tSWITCH_PORT(12, 13, internal)\n\t\tSWITCH_PORT(13, 14, internal)\n\t\tSWITCH_PORT(14, 15, internal)\n\t\tSWITCH_PORT(15, 16, internal)\n\n\t\tSWITCH_PORT(24, 17, qsgmii)\n\t\tSWITCH_PORT(25, 18, qsgmii)\n\t\tSWITCH_PORT(26, 19, qsgmii)\n\t\tSWITCH_PORT(27, 20, qsgmii)\n\n\t\tport@28 {\n\t\t\tethernet = <&ethernet0>;\n\t\t\treg = <28>;\n\t\t\tphy-mode = \"internal\";\n\t\t\tfixed-link {\n\t\t\t\tspeed = <1000>;\n\t\t\t\tfull-duplex;\n\t\t\t};\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/realtek/dts-5.10/rtl8382_d-link_dgs-1210-28.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"rtl8382_d-link_dgs-1210.dtsi\"\n\n/ {\n\tcompatible = \"d-link,dgs-1210-28\", \"realtek,rtl838x-soc\";\n\tmodel = \"D-Link DGS-1210-28\";\n};\n\n&ethernet0 {\n\tmdio: mdio-bus {\n\t\tcompatible = \"realtek,rtl838x-mdio\";\n\t\tregmap = <&ethernet0>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tEXTERNAL_PHY(0)\n\t\tEXTERNAL_PHY(1)\n\t\tEXTERNAL_PHY(2)\n\t\tEXTERNAL_PHY(3)\n\t\tEXTERNAL_PHY(4)\n\t\tEXTERNAL_PHY(5)\n\t\tEXTERNAL_PHY(6)\n\t\tEXTERNAL_PHY(7)\n\n\t\tINTERNAL_PHY(8)\n\t\tINTERNAL_PHY(9)\n\t\tINTERNAL_PHY(10)\n\t\tINTERNAL_PHY(11)\n\t\tINTERNAL_PHY(12)\n\t\tINTERNAL_PHY(13)\n\t\tINTERNAL_PHY(14)\n\t\tINTERNAL_PHY(15)\n\n\t\tEXTERNAL_PHY(16)\n\t\tEXTERNAL_PHY(17)\n\t\tEXTERNAL_PHY(18)\n\t\tEXTERNAL_PHY(19)\n\t\tEXTERNAL_PHY(20)\n\t\tEXTERNAL_PHY(21)\n\t\tEXTERNAL_PHY(22)\n\t\tEXTERNAL_PHY(23)\n\n\t\tEXTERNAL_SFP_PHY(24)\n\t\tEXTERNAL_SFP_PHY(25)\n\t\tEXTERNAL_SFP_PHY(26)\n\t\tEXTERNAL_SFP_PHY(27)\n\t};\n};\n\n&switch0 {\n\tports {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tSWITCH_PORT(0, 1, qsgmii)\n\t\tSWITCH_PORT(1, 2, qsgmii)\n\t\tSWITCH_PORT(2, 3, qsgmii)\n\t\tSWITCH_PORT(3, 4, qsgmii)\n\t\tSWITCH_PORT(4, 5, qsgmii)\n\t\tSWITCH_PORT(5, 6, qsgmii)\n\t\tSWITCH_PORT(6, 7, qsgmii)\n\t\tSWITCH_PORT(7, 8, qsgmii)\n\n\t\tSWITCH_PORT(8, 9, internal)\n\t\tSWITCH_PORT(9, 10, internal)\n\t\tSWITCH_PORT(10, 11, internal)\n\t\tSWITCH_PORT(11, 12, internal)\n\t\tSWITCH_PORT(12, 13, internal)\n\t\tSWITCH_PORT(13, 14, internal)\n\t\tSWITCH_PORT(14, 15, internal)\n\t\tSWITCH_PORT(15, 16, internal)\n\n\t\tSWITCH_PORT(16, 17, qsgmii)\n\t\tSWITCH_PORT(17, 18, qsgmii)\n\t\tSWITCH_PORT(18, 19, qsgmii)\n\t\tSWITCH_PORT(19, 20, qsgmii)\n\t\tSWITCH_PORT(20, 21, qsgmii)\n\t\tSWITCH_PORT(21, 22, qsgmii)\n\t\tSWITCH_PORT(22, 23, qsgmii)\n\t\tSWITCH_PORT(23, 24, qsgmii)\n\n\t\tSWITCH_PORT(24, 25, qsgmii)\n\t\tSWITCH_PORT(25, 26, qsgmii)\n\t\tSWITCH_PORT(26, 27, qsgmii)\n\t\tSWITCH_PORT(27, 28, qsgmii)\n\n\t\tport@28 {\n\t\t\tethernet = <&ethernet0>;\n\t\t\treg = <28>;\n\t\t\tphy-mode = \"internal\";\n\t\t\tfixed-link {\n\t\t\t\tspeed = <1000>;\n\t\t\t\tfull-duplex;\n\t\t\t};\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/realtek/dts-5.10/rtl8382_d-link_dgs-1210.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"rtl838x.dtsi\"\n\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/gpio/gpio.h>\n\n/ {\n\taliases {\n\t\tled-boot = &led_power;\n\t\tled-failsafe = &led_power;\n\t\tled-running = &led_power;\n\t\tled-upgrade = &led_power;\n\t};\n\n\tmemory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x0 0x8000000>;\n\t};\n\n\tleds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_power: power {\n\t\t\tlabel = \"green:power\";\n\t\t\tgpios = <&gpio0 0 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&gpio0 {\n\tindirect-access-bus-id = <0>;\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x00000000 0x80000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@80000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x00080000 0x40000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@c0000 {\n\t\t\t\tlabel = \"u-boot-env2\";\n\t\t\t\treg = <0x000c0000 0x40000>;\n\t\t\t};\n\t\t\tpartition@280000 {\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\treg = <0x00100000 0xd80000>;\n\t\t\t};\n\t\t\tpartition@be80000 {\n\t\t\t\tlabel = \"kernel2\";\n\t\t\t\treg = <0x00e80000 0x180000>;\n\t\t\t};\n\t\t\tpartition@1000000 {\n\t\t\t\tlabel = \"sysinfo\";\n\t\t\t\treg = <0x01000000 0x40000>;\n\t\t\t};\n\t\t\tpartition@1040000 {\n\t\t\t\tlabel = \"rootfs2\";\n\t\t\t\treg = <0x01040000 0xc00000>;\n\t\t\t};\n\t\t\tpartition@1c40000 {\n\t\t\t\tlabel = \"jffs2\";\n\t\t\t\treg = <0x01c40000 0x3c0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/realtek/dts-5.10/rtl8382_inaba_aml2-17gp.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"rtl838x.dtsi\"\n\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/gpio/gpio.h>\n\n/ {\n\tcompatible = \"inaba,aml2-17gp\", \"realtek,rtl838x-soc\";\n\tmodel = \"INABA Abaniact AML2-17GP\";\n\n\tmemory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x0 0x8000000>;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 0 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x80000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@80000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x80000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@90000 {\n\t\t\t\tlabel = \"u-boot-env2\";\n\t\t\t\treg = <0x90000 0x10000>;\n\t\t\t};\n\n\t\t\tpartition@a0000 {\n\t\t\t\tlabel = \"jffs2_cfg\";\n\t\t\t\treg = <0xa0000 0x400000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@4a0000 {\n\t\t\t\tlabel = \"jffs2_log\";\n\t\t\t\treg = <0x4a0000 0x100000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@5a0000 {\n\t\t\t\tcompatible = \"openwrt,uimage\", \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x5a0000 0xd30000>;\n\t\t\t\topenwrt,ih-magic = <0x83800000>;\n\t\t\t};\n\n\t\t\tpartition@12d0000 {\n\t\t\t\tlabel = \"runtime2\";\n\t\t\t\treg = <0x12d0000 0xd30000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&ethernet0 {\n\tmdio-bus {\n\t\tcompatible = \"realtek,rtl838x-mdio\";\n\t\tregmap = <&ethernet0>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tINTERNAL_PHY(8)\n\t\tINTERNAL_PHY(9)\n\t\tINTERNAL_PHY(10)\n\t\tINTERNAL_PHY(11)\n\t\tINTERNAL_PHY(12)\n\t\tINTERNAL_PHY(13)\n\t\tINTERNAL_PHY(14)\n\t\tINTERNAL_PHY(15)\n\n\t\tEXTERNAL_PHY(16)\n\t\tEXTERNAL_PHY(17)\n\t\tEXTERNAL_PHY(18)\n\t\tEXTERNAL_PHY(19)\n\t\tEXTERNAL_PHY(20)\n\t\tEXTERNAL_PHY(21)\n\t\tEXTERNAL_PHY(22)\n\t\tEXTERNAL_PHY(23)\n\n\t\tEXTERNAL_PHY(24)\n\t};\n};\n\n&switch0 {\n\tports {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tSWITCH_PORT(8, 1, internal)\n\t\tSWITCH_PORT(9, 2, internal)\n\t\tSWITCH_PORT(10, 3, internal)\n\t\tSWITCH_PORT(11, 4, internal)\n\t\tSWITCH_PORT(12, 5, internal)\n\t\tSWITCH_PORT(13, 6, internal)\n\t\tSWITCH_PORT(14, 7, internal)\n\t\tSWITCH_PORT(15, 8, internal)\n\n\t\tSWITCH_PORT(16, 9, qsgmii)\n\t\tSWITCH_PORT(17, 10, qsgmii)\n\t\tSWITCH_PORT(18, 11, qsgmii)\n\t\tSWITCH_PORT(19, 12, qsgmii)\n\t\tSWITCH_PORT(20, 13, qsgmii)\n\t\tSWITCH_PORT(21, 14, qsgmii)\n\t\tSWITCH_PORT(22, 15, qsgmii)\n\t\tSWITCH_PORT(23, 16, qsgmii)\n\n\t\tport@24 {\n\t\t\treg = <24>;\n\t\t\tlabel = \"wan\";\n\t\t\tphy-handle = <&phy24>;\n\t\t\tphy-mode = \"qsgmii\";\n\t\t};\n\n\t\tport@28 {\n\t\t\tethernet = <&ethernet0>;\n\t\t\treg = <28>;\n\t\t\tphy-mode = \"internal\";\n\n\t\t\tfixed-link {\n\t\t\t\tspeed = <1000>;\n\t\t\t\tfull-duplex;\n\t\t\t};\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/realtek/dts-5.10/rtl8382_iodata_bsh-g24mb.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include \"rtl838x.dtsi\"\n\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/leds/common.h>\n\n/ {\n\tcompatible = \"iodata,bsh-g24mb\", \"realtek,rtl838x-soc\";\n\tmodel = \"I-O DATA BSH-G24MB\";\n\n\taliases {\n\t\tled-boot = &led_sys_loop;\n\t\tled-failsafe = &led_sys_loop;\n\t\tled-upgrade = &led_sys_loop;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200\";\n\t};\n\n\tmemory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x0 0x8000000>;\n\t};\n\n\tleds {\n\t\tpinctrl-names = \"default\";\n\t\tpinctrl-0 = <&pinmux_disable_sys_led>;\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_sys_loop: led {\n\t\t\tlabel = \"red:sys_loop\";\n\t\t\tgpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;\n\t\t\tcolor = <LED_COLOR_ID_RED>;\n\t\t\tfunction = LED_FUNCTION_STATUS;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <20>;\n\n\t\treset {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio1 3 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\tgpio1: rtl8231-gpio {\n\t\tcompatible = \"realtek,rtl8231-gpio\";\n\t\t#gpio-cells = <2>;\n\t\tgpio-controller;\n\t\tindirect-access-bus-id = <0>;\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x80000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@80000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x80000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@90000 {\n\t\t\t\tlabel = \"u-boot-env2\";\n\t\t\t\treg = <0x90000 0x10000>;\n\t\t\t};\n\n\t\t\tpartition@a0000 {\n\t\t\t\tlabel = \"jffs2_cfg\";\n\t\t\t\treg = <0xa0000 0x100000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@1a0000 {\n\t\t\t\tlabel = \"jffs2_log\";\n\t\t\t\treg = <0x1a0000 0x100000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\t/*\n\t\t\t * use 2x OS partitions in OpenWrt\n\t\t\t *\n\t\t\t * 0x2A0000-0x94FFFF: RUNTIME\n\t\t\t * 0x950000-0xFFFFFF: RUNTIME2 (not used in stock)\n\t\t\t */\n\t\t\tpartition@2a0000 {\n\t\t\t\tcompatible = \"openwrt,uimage\", \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x2a0000 0xd60000>;\n\t\t\t\topenwrt,ih-magic = <0x83800013>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&ethernet0 {\n\tmdio-bus {\n\t\tcompatible = \"realtek,rtl838x-mdio\";\n\t\tregmap = <&ethernet0>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tEXTERNAL_PHY(0)\n\t\tEXTERNAL_PHY(1)\n\t\tEXTERNAL_PHY(2)\n\t\tEXTERNAL_PHY(3)\n\t\tEXTERNAL_PHY(4)\n\t\tEXTERNAL_PHY(5)\n\t\tEXTERNAL_PHY(6)\n\t\tEXTERNAL_PHY(7)\n\n\t\tINTERNAL_PHY(8)\n\t\tINTERNAL_PHY(9)\n\t\tINTERNAL_PHY(10)\n\t\tINTERNAL_PHY(11)\n\t\tINTERNAL_PHY(12)\n\t\tINTERNAL_PHY(13)\n\t\tINTERNAL_PHY(14)\n\t\tINTERNAL_PHY(15)\n\n\t\tEXTERNAL_PHY(16)\n\t\tEXTERNAL_PHY(17)\n\t\tEXTERNAL_PHY(18)\n\t\tEXTERNAL_PHY(19)\n\t\tEXTERNAL_PHY(20)\n\t\tEXTERNAL_PHY(21)\n\t\tEXTERNAL_PHY(22)\n\t\tEXTERNAL_PHY(23)\n\t};\n};\n\n&switch0 {\n\tports {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tSWITCH_PORT(0, 1, qsgmii)\n\t\tSWITCH_PORT(1, 2, qsgmii)\n\t\tSWITCH_PORT(2, 3, qsgmii)\n\t\tSWITCH_PORT(3, 4, qsgmii)\n\t\tSWITCH_PORT(4, 5, qsgmii)\n\t\tSWITCH_PORT(5, 6, qsgmii)\n\t\tSWITCH_PORT(6, 7, qsgmii)\n\t\tSWITCH_PORT(7, 8, qsgmii)\n\n\t\tSWITCH_PORT(8, 9, internal)\n\t\tSWITCH_PORT(9, 10, internal)\n\t\tSWITCH_PORT(10, 11, internal)\n\t\tSWITCH_PORT(11, 12, internal)\n\t\tSWITCH_PORT(12, 13, internal)\n\t\tSWITCH_PORT(13, 14, internal)\n\t\tSWITCH_PORT(14, 15, internal)\n\t\tSWITCH_PORT(15, 16, internal)\n\n\t\tSWITCH_PORT(16, 17, qsgmii)\n\t\tSWITCH_PORT(17, 18, qsgmii)\n\t\tSWITCH_PORT(18, 19, qsgmii)\n\t\tSWITCH_PORT(19, 20, qsgmii)\n\t\tSWITCH_PORT(20, 21, qsgmii)\n\t\tSWITCH_PORT(21, 22, qsgmii)\n\t\tSWITCH_PORT(22, 23, qsgmii)\n\t\tSWITCH_PORT(23, 24, qsgmii)\n\n\t\tport@28 {\n\t\t\tethernet = <&ethernet0>;\n\t\t\treg = <28>;\n\t\t\tphy-mode = \"internal\";\n\n\t\t\tfixed-link {\n\t\t\t\tspeed = <1000>;\n\t\t\t\tfull-duplex;\n\t\t\t};\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/realtek/dts-5.10/rtl8382_zyxel_gs1900-16.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later\n\n#include \"rtl8380_zyxel_gs1900.dtsi\"\n\n/ {\n\tcompatible = \"zyxel,gs1900-16\", \"realtek,rtl838x-soc\";\n\tmodel = \"ZyXEL GS1900-16\";\n};\n\n&mdio {\n\tEXTERNAL_PHY(16)\n\tEXTERNAL_PHY(17)\n\tEXTERNAL_PHY(18)\n\tEXTERNAL_PHY(19)\n\tEXTERNAL_PHY(20)\n\tEXTERNAL_PHY(21)\n\tEXTERNAL_PHY(22)\n\tEXTERNAL_PHY(23)\n};\n\n&switch0 {\n\tports {\n\t\tSWITCH_PORT(16, 9, qsgmii)\n\t\tSWITCH_PORT(17, 10, qsgmii)\n\t\tSWITCH_PORT(18, 11, qsgmii)\n\t\tSWITCH_PORT(19, 12, qsgmii)\n\t\tSWITCH_PORT(20, 13, qsgmii)\n\t\tSWITCH_PORT(21, 14, qsgmii)\n\t\tSWITCH_PORT(22, 15, qsgmii)\n\t\tSWITCH_PORT(23, 16, qsgmii)\n\t};\n};\n\n&gpio1 {\n\t/delete-node/ poe_enable;\n};\n"
  },
  {
    "path": "target/linux/realtek/dts-5.10/rtl8382_zyxel_gs1900-24-v1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later\n\n#include \"rtl8380_zyxel_gs1900.dtsi\"\n\n/ {\n\tcompatible = \"zyxel,gs1900-24-v1\", \"realtek,rtl838x-soc\";\n\tmodel = \"ZyXEL GS1900-24 v1\";\n\n\tmemory@0 {\n\t\treg = <0x0 0x4000000>;\n\t};\n\n\t/* i2c of the left SFP cage: port 25 */\n\ti2c0: i2c-gpio-0 {\n\t\tcompatible = \"i2c-gpio\";\n\t\tsda-gpios = <&gpio1 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\t\tscl-gpios = <&gpio1 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\t\ti2c-gpio,delay-us = <2>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t};\n\n\tsfp0: sfp-p25 {\n\t\tcompatible = \"sff,sfp\";\n\t\ti2c-bus = <&i2c0>;\n\t\tlos-gpio = <&gpio1 27 GPIO_ACTIVE_HIGH>;\n\t\ttx-fault-gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>;\n\t\tmod-def0-gpio = <&gpio1 26 GPIO_ACTIVE_LOW>;\n\t\ttx-disable-gpio = <&gpio1 23 GPIO_ACTIVE_HIGH>;\n\t};\n\n\t/* i2c of the right SFP cage: port 26 */\n\ti2c1: i2c-gpio-1 {\n\t\tcompatible = \"i2c-gpio\";\n\t\tsda-gpios = <&gpio1 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\t\tscl-gpios = <&gpio1 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\t\ti2c-gpio,delay-us = <2>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t};\n\n\tsfp1: sfp-p26 {\n\t\tcompatible = \"sff,sfp\";\n\t\ti2c-bus = <&i2c1>;\n\t\tlos-gpio = <&gpio1 33 GPIO_ACTIVE_HIGH>;\n\t\ttx-fault-gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>;\n\t\tmod-def0-gpio = <&gpio1 32 GPIO_ACTIVE_LOW>;\n\t\ttx-disable-gpio = <&gpio1 29 GPIO_ACTIVE_HIGH>;\n\t};\n};\n\n&uart1 {\n\tstatus = \"okay\";\n};\n\n&mdio {\n\tEXTERNAL_PHY(0)\n\tEXTERNAL_PHY(1)\n\tEXTERNAL_PHY(2)\n\tEXTERNAL_PHY(3)\n\tEXTERNAL_PHY(4)\n\tEXTERNAL_PHY(5)\n\tEXTERNAL_PHY(6)\n\tEXTERNAL_PHY(7)\n\n\tEXTERNAL_PHY(16)\n\tEXTERNAL_PHY(17)\n\tEXTERNAL_PHY(18)\n\tEXTERNAL_PHY(19)\n\tEXTERNAL_PHY(20)\n\tEXTERNAL_PHY(21)\n\tEXTERNAL_PHY(22)\n\tEXTERNAL_PHY(23)\n\n\tINTERNAL_PHY(24)\n\tINTERNAL_PHY(26)\n};\n\n&switch0 {\n\tports {\n\t\tSWITCH_PORT(0, 1, qsgmii)\n\t\tSWITCH_PORT(1, 2, qsgmii)\n\t\tSWITCH_PORT(2, 3, qsgmii)\n\t\tSWITCH_PORT(3, 4, qsgmii)\n\t\tSWITCH_PORT(4, 5, qsgmii)\n\t\tSWITCH_PORT(5, 6, qsgmii)\n\t\tSWITCH_PORT(6, 7, qsgmii)\n\t\tSWITCH_PORT(7, 8, qsgmii)\n\n\t\tSWITCH_PORT(8, 9, internal)\n\t\tSWITCH_PORT(9, 10, internal)\n\t\tSWITCH_PORT(10, 11, internal)\n\t\tSWITCH_PORT(11, 12, internal)\n\t\tSWITCH_PORT(12, 13, internal)\n\t\tSWITCH_PORT(13, 14, internal)\n\t\tSWITCH_PORT(14, 15, internal)\n\t\tSWITCH_PORT(15, 16, internal)\n\n\t\tSWITCH_PORT(16, 17, qsgmii)\n\t\tSWITCH_PORT(17, 18, qsgmii)\n\t\tSWITCH_PORT(18, 19, qsgmii)\n\t\tSWITCH_PORT(19, 20, qsgmii)\n\t\tSWITCH_PORT(20, 21, qsgmii)\n\t\tSWITCH_PORT(21, 22, qsgmii)\n\t\tSWITCH_PORT(22, 23, qsgmii)\n\t\tSWITCH_PORT(23, 24, qsgmii)\n\n\t\tport@24 {\n\t\t\treg = <24>;\n\t\t\tlabel = \"lan25\";\n\t\t\tphy-mode = \"1000base-x\";\n\t\t\tmanaged = \"in-band-status\";\n\t\t\tsfp = <&sfp0>;\n\t\t};\n\n\t\tport@26 {\n\t\t\treg = <26>;\n\t\t\tlabel = \"lan26\";\n\t\t\tphy-mode = \"1000base-x\";\n\t\t\tmanaged = \"in-band-status\";\n\t\t\tsfp = <&sfp1>;\n\t\t};\n\t};\n};\n\n&gpio1 {\n\t/delete-node/ poe_enable;\n};\n"
  },
  {
    "path": "target/linux/realtek/dts-5.10/rtl8382_zyxel_gs1900-24hp-v1.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later\n\n#include \"rtl8380_zyxel_gs1900.dtsi\"\n\n/ {\n\tcompatible = \"zyxel,gs1900-24hp-v1\", \"realtek,rtl838x-soc\";\n\tmodel = \"ZyXEL GS1900-24HP v1\";\n\n\tmemory@0 {\n\t\treg = <0x0 0x4000000>;\n\t};\n\n\t/* i2c of the left SFP cage: port 25 */\n\ti2c0: i2c-gpio-0 {\n\t\tcompatible = \"i2c-gpio\";\n\t\tsda-gpios = <&gpio1 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\t\tscl-gpios = <&gpio1 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\t\ti2c-gpio,delay-us = <2>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t};\n\n\tsfp0: sfp-p25 {\n\t\tcompatible = \"sff,sfp\";\n\t\ti2c-bus = <&i2c0>;\n\t\tlos-gpio = <&gpio1 27 GPIO_ACTIVE_HIGH>;\n\t\ttx-fault-gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>;\n\t\tmod-def0-gpio = <&gpio1 26 GPIO_ACTIVE_LOW>;\n\t\ttx-disable-gpio = <&gpio1 23 GPIO_ACTIVE_HIGH>;\n\t};\n\n\t/* i2c of the right SFP cage: port 26 */\n\ti2c1: i2c-gpio-1 {\n\t\tcompatible = \"i2c-gpio\";\n\t\tsda-gpios = <&gpio1 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\t\tscl-gpios = <&gpio1 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\t\ti2c-gpio,delay-us = <2>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t};\n\n\tsfp1: sfp-p26 {\n\t\tcompatible = \"sff,sfp\";\n\t\ti2c-bus = <&i2c1>;\n\t\tlos-gpio = <&gpio1 33 GPIO_ACTIVE_HIGH>;\n\t\ttx-fault-gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>;\n\t\tmod-def0-gpio = <&gpio1 32 GPIO_ACTIVE_LOW>;\n\t\ttx-disable-gpio = <&gpio1 29 GPIO_ACTIVE_HIGH>;\n\t};\n};\n\n&uart1 {\n\tstatus = \"okay\";\n};\n\n&mdio {\n\tEXTERNAL_PHY(0)\n\tEXTERNAL_PHY(1)\n\tEXTERNAL_PHY(2)\n\tEXTERNAL_PHY(3)\n\tEXTERNAL_PHY(4)\n\tEXTERNAL_PHY(5)\n\tEXTERNAL_PHY(6)\n\tEXTERNAL_PHY(7)\n\n\tEXTERNAL_PHY(16)\n\tEXTERNAL_PHY(17)\n\tEXTERNAL_PHY(18)\n\tEXTERNAL_PHY(19)\n\tEXTERNAL_PHY(20)\n\tEXTERNAL_PHY(21)\n\tEXTERNAL_PHY(22)\n\tEXTERNAL_PHY(23)\n\n\tINTERNAL_PHY(24)\n\tINTERNAL_PHY(26)\n};\n\n&switch0 {\n\tports {\n\t\tSWITCH_PORT(0, 1, qsgmii)\n\t\tSWITCH_PORT(1, 2, qsgmii)\n\t\tSWITCH_PORT(2, 3, qsgmii)\n\t\tSWITCH_PORT(3, 4, qsgmii)\n\t\tSWITCH_PORT(4, 5, qsgmii)\n\t\tSWITCH_PORT(5, 6, qsgmii)\n\t\tSWITCH_PORT(6, 7, qsgmii)\n\t\tSWITCH_PORT(7, 8, qsgmii)\n\n\t\tSWITCH_PORT(8, 9, internal)\n\t\tSWITCH_PORT(9, 10, internal)\n\t\tSWITCH_PORT(10, 11, internal)\n\t\tSWITCH_PORT(11, 12, internal)\n\t\tSWITCH_PORT(12, 13, internal)\n\t\tSWITCH_PORT(13, 14, internal)\n\t\tSWITCH_PORT(14, 15, internal)\n\t\tSWITCH_PORT(15, 16, internal)\n\n\t\tSWITCH_PORT(16, 17, qsgmii)\n\t\tSWITCH_PORT(17, 18, qsgmii)\n\t\tSWITCH_PORT(18, 19, qsgmii)\n\t\tSWITCH_PORT(19, 20, qsgmii)\n\t\tSWITCH_PORT(20, 21, qsgmii)\n\t\tSWITCH_PORT(21, 22, qsgmii)\n\t\tSWITCH_PORT(22, 23, qsgmii)\n\t\tSWITCH_PORT(23, 24, qsgmii)\n\n\t\tport@24 {\n\t\t\treg = <24>;\n\t\t\tlabel = \"lan25\";\n\t\t\tphy-mode = \"1000base-x\";\n\t\t\tmanaged = \"in-band-status\";\n\t\t\tsfp = <&sfp0>;\n\t\t};\n\n\t\tport@26 {\n\t\t\treg = <26>;\n\t\t\tlabel = \"lan26\";\n\t\t\tphy-mode = \"1000base-x\";\n\t\t\tmanaged = \"in-band-status\";\n\t\t\tsfp = <&sfp1>;\n\t\t};\n\t};\n};\n\n"
  },
  {
    "path": "target/linux/realtek/dts-5.10/rtl8382_zyxel_gs1900-24hp-v2.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later\n\n#include \"rtl8380_zyxel_gs1900.dtsi\"\n\n/ {\n\tcompatible = \"zyxel,gs1900-24hp-v2\", \"realtek,rtl838x-soc\";\n\tmodel = \"ZyXEL GS1900-24HP v2 Switch\";\n\n\t/* i2c of the left SFP cage: port 25 */\n\ti2c0: i2c-gpio-0 {\n\t\tcompatible = \"i2c-gpio\";\n\t\tsda-gpios = <&gpio1 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\t\tscl-gpios = <&gpio1 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\t\ti2c-gpio,delay-us = <2>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t};\n\n\tsfp0: sfp-p25 {\n\t\tcompatible = \"sff,sfp\";\n\t\ti2c-bus = <&i2c0>;\n\t\tlos-gpio = <&gpio1 27 GPIO_ACTIVE_HIGH>;\n\t\ttx-fault-gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>;\n\t\tmod-def0-gpio = <&gpio1 26 GPIO_ACTIVE_LOW>;\n\t\ttx-disable-gpio = <&gpio1 23 GPIO_ACTIVE_HIGH>;\n\t};\n\n\t/* i2c of the right SFP cage: port 26 */\n\ti2c1: i2c-gpio-1 {\n\t\tcompatible = \"i2c-gpio\";\n\t\tsda-gpios = <&gpio1 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\t\tscl-gpios = <&gpio1 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\t\ti2c-gpio,delay-us = <2>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t};\n\n\tsfp1: sfp-p26 {\n\t\tcompatible = \"sff,sfp\";\n\t\ti2c-bus = <&i2c1>;\n\t\tlos-gpio = <&gpio1 33 GPIO_ACTIVE_HIGH>;\n\t\ttx-fault-gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>;\n\t\tmod-def0-gpio = <&gpio1 32 GPIO_ACTIVE_LOW>;\n\t\ttx-disable-gpio = <&gpio1 29 GPIO_ACTIVE_HIGH>;\n\t};\n};\n\n&uart1 {\n\tstatus = \"okay\";\n};\n\n&mdio {\n\tEXTERNAL_PHY(0)\n\tEXTERNAL_PHY(1)\n\tEXTERNAL_PHY(2)\n\tEXTERNAL_PHY(3)\n\tEXTERNAL_PHY(4)\n\tEXTERNAL_PHY(5)\n\tEXTERNAL_PHY(6)\n\tEXTERNAL_PHY(7)\n\n\tEXTERNAL_PHY(16)\n\tEXTERNAL_PHY(17)\n\tEXTERNAL_PHY(18)\n\tEXTERNAL_PHY(19)\n\tEXTERNAL_PHY(20)\n\tEXTERNAL_PHY(21)\n\tEXTERNAL_PHY(22)\n\tEXTERNAL_PHY(23)\n\n\tINTERNAL_PHY(24)\n\tINTERNAL_PHY(26)\n};\n\n&switch0 {\n\tports {\n\t\tSWITCH_PORT(0, 1, qsgmii)\n\t\tSWITCH_PORT(1, 2, qsgmii)\n\t\tSWITCH_PORT(2, 3, qsgmii)\n\t\tSWITCH_PORT(3, 4, qsgmii)\n\t\tSWITCH_PORT(4, 5, qsgmii)\n\t\tSWITCH_PORT(5, 6, qsgmii)\n\t\tSWITCH_PORT(6, 7, qsgmii)\n\t\tSWITCH_PORT(7, 8, qsgmii)\n\n\t\tSWITCH_PORT(8, 9, internal)\n\t\tSWITCH_PORT(9, 10, internal)\n\t\tSWITCH_PORT(10, 11, internal)\n\t\tSWITCH_PORT(11, 12, internal)\n\t\tSWITCH_PORT(12, 13, internal)\n\t\tSWITCH_PORT(13, 14, internal)\n\t\tSWITCH_PORT(14, 15, internal)\n\t\tSWITCH_PORT(15, 16, internal)\n\n\t\tSWITCH_PORT(16, 17, qsgmii)\n\t\tSWITCH_PORT(17, 18, qsgmii)\n\t\tSWITCH_PORT(18, 19, qsgmii)\n\t\tSWITCH_PORT(19, 20, qsgmii)\n\t\tSWITCH_PORT(20, 21, qsgmii)\n\t\tSWITCH_PORT(21, 22, qsgmii)\n\t\tSWITCH_PORT(22, 23, qsgmii)\n\t\tSWITCH_PORT(23, 24, qsgmii)\n\n\n\t\tport@24 {\n\t\t\treg = <24>;\n\t\t\tlabel = \"lan25\";\n\t\t\tphy-mode = \"1000base-x\";\n\t\t\tmanaged = \"in-band-status\";\n\t\t\tsfp = <&sfp0>;\n\t\t};\n\n\t\tport@26 {\n\t\t\treg = <26>;\n\t\t\tlabel = \"lan26\";\n\t\t\tphy-mode = \"1000base-x\";\n\t\t\tmanaged = \"in-band-status\";\n\t\t\tsfp = <&sfp1>;\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/realtek/dts-5.10/rtl838x.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n/dts-v1/;\n\n#define STRINGIZE(s) #s\n#define LAN_LABEL(p, s) STRINGIZE(p ## s)\n#define SWITCH_PORT_LABEL(n) LAN_LABEL(lan, n)\n\n#define INTERNAL_PHY(n) \\\n\tphy##n: ethernet-phy@##n { \\\n\t\treg = <##n>; \\\n\t\tcompatible = \"ethernet-phy-ieee802.3-c22\"; \\\n\t\tphy-is-integrated; \\\n\t};\n\n#define EXTERNAL_PHY(n) \\\n\tphy##n: ethernet-phy@##n { \\\n\t\treg = <##n>; \\\n\t\tcompatible = \"ethernet-phy-ieee802.3-c22\"; \\\n\t};\n\n#define EXTERNAL_SFP_PHY(n) \\\n\tphy##n: ethernet-phy@##n { \\\n\t\tcompatible = \"ethernet-phy-ieee802.3-c22\"; \\\n\t\tsfp; \\\n\t\tmedia = \"fibre\"; \\\n\t\treg = <##n>; \\\n\t};\n\n#define SWITCH_PORT(n, s, m) \\\n\tport@##n { \\\n\t\treg = <##n>; \\\n\t\tlabel = SWITCH_PORT_LABEL(s) ; \\\n\t\tphy-handle = <&phy##n>; \\\n\t\tphy-mode = #m ; \\\n\t};\n\n#define SWITCH_SFP_PORT(n, s, m) \\\n\tport@##n { \\\n\t\treg = <##n>; \\\n\t\tlabel = SWITCH_PORT_LABEL(s) ; \\\n\t\tphy-handle = <&phy##n>; \\\n\t\tphy-mode = #m ; \\\n\t\tfixed-link { \\\n\t\t\tspeed = <1000>; \\\n\t\t\tfull-duplex; \\\n\t\t}; \\\n\t};\n\n/ {\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tcompatible = \"realtek,rtl838x-soc\";\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tfrequency = <500000000>;\n\n\t\tcpu@0 {\n\t\t\tcompatible = \"mips,mips4KEc\";\n\t\t\treg = <0>;\n\t\t};\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200\";\n\t};\n\n\tlx_clk: lx_clk {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <200000000>;\n\t};\n\n\tcpuintc: cpuintc {\n\t\tcompatible = \"mti,cpu-interrupt-controller\";\n\t\t#address-cells = <0>;\n\t\t#interrupt-cells = <1>;\n\t\tinterrupt-controller;\n\t};\n\n\tsoc: soc {\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tranges = <0x0 0x18000000 0x10000>;\n\n\t\tintc: interrupt-controller@3000 {\n\t\t\tcompatible = \"realtek,rtl8380-intc\", \"realtek,rtl-intc\";\n\t\t\treg = <0x3000 0x18>;\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <2>;\n\n\t\t\tinterrupt-parent = <&cpuintc>;\n\t\t\tinterrupts = <2>, <3>, <4>, <5>, <6>;\n\t\t};\n\n\t\tspi0: spi@1200 {\n\t\t\tcompatible = \"realtek,rtl8380-spi\";\n\t\t\treg = <0x1200 0x100>;\n\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tuart0: uart@2000 {\n\t\t\tcompatible = \"ns16550a\";\n\t\t\treg = <0x2000 0x100>;\n\n\t\t\tclocks = <&lx_clk>;\n\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <31 1>;\n\n\t\t\treg-io-width = <1>;\n\t\t\treg-shift = <2>;\n\t\t\tfifo-size = <1>;\n\t\t\tno-loopback-test;\n\t\t};\n\n\t\tuart1: uart@2100 {\n\t\t\tpinctrl-names = \"default\";\n\t\t\tpinctrl-0 = <&enable_uart1>;\n\n\t\t\tcompatible = \"ns16550a\";\n\t\t\treg = <0x2100 0x100>;\n\n\t\t\tclocks = <&lx_clk>;\n\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <30 0>;\n\n\t\t\treg-io-width = <1>;\n\t\t\treg-shift = <2>;\n\t\t\tfifo-size = <1>;\n\t\t\tno-loopback-test;\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\twatchdog0: watchdog@3150 {\n\t\t\tcompatible = \"realtek,rtl8380-wdt\";\n\t\t\treg = <0x3150 0xc>;\n\n\t\t\trealtek,reset-mode = \"soc\";\n\n\t\t\tclocks = <&lx_clk>;\n\t\t\ttimeout-sec = <30>;\n\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupt-names = \"phase1\", \"phase2\";\n\t\t\tinterrupts = <19 3>, <18 4>;\n\t\t};\n\n\t\tgpio0: gpio-controller@3500 {\n\t\t\tcompatible = \"realtek,rtl8380-gpio\", \"realtek,otto-gpio\";\n\t\t\treg = <0x3500 0x20>;\n\n\t\t\tgpio-controller;\n\t\t\t#gpio-cells = <2>;\n\t\t\tngpios = <24>;\n\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <23 3>;\n\t\t};\n\t};\n\n\tpinmux: pinmux@1b001000 {\n\t\tcompatible = \"pinctrl-single\";\n\t\treg = <0x1b001000 0x4>;\n\n\t\tpinctrl-single,bit-per-mux;\n\t\tpinctrl-single,register-width = <32>;\n\t\tpinctrl-single,function-mask = <0x1>;\n\t\t#pinctrl-cells = <2>;\n\n\t\tenable_uart1: pinmux_enable_uart1 {\n\t\t\tpinctrl-single,bits = <0x0 0x10 0x10>;\n\t\t};\n\t};\n\n\t/* LED_GLB_CTRL */\n\tpinmux_led: pinmux@1b00a000 {\n\t\tcompatible = \"pinctrl-single\";\n\t\treg = <0x1b00a000 0x4>;\n\n\t\tpinctrl-single,bit-per-mux;\n\t\tpinctrl-single,register-width = <32>;\n\t\tpinctrl-single,function-mask = <0x1>;\n\t\t#pinctrl-cells = <2>;\n\n\t\t/* enable GPIO 0 */\n\t\tpinmux_disable_sys_led: disable_sys_led {\n\t\t\tpinctrl-single,bits = <0x0 0x0 0x8000>;\n\t\t};\n\t};\n\n\tethernet0: ethernet@1b00a300 {\n\t\tcompatible = \"realtek,rtl838x-eth\";\n\t\treg = <0x1b00a300 0x100>;\n\t\tinterrupt-parent = <&intc>;\n\t\tinterrupts = <24 3>;\n\t\t#interrupt-cells = <1>;\n\t\tphy-mode = \"internal\";\n\n\t\tfixed-link {\n\t\t\tspeed = <1000>;\n\t\t\tfull-duplex;\n\t\t};\n\t};\n\n\tswitch0: switch@1b000000 {\n\t\tcompatible = \"realtek,rtl83xx-switch\";\n\n\t\tinterrupt-parent = <&intc>;\n\t\tinterrupts = <20 2>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/realtek/dts-5.10/rtl8393_zyxel_gs1900-48.dts",
    "content": "/dts-v1/;\n\n#include \"rtl839x.dtsi\"\n\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/gpio/gpio.h>\n\n/ {\n\tcompatible = \"zyxel,gs1900-48\", \"realtek,rtl8393-soc\";\n\tmodel = \"Zyxel GS1900-48\";\n\n\taliases {\n\t\tled-boot = &led_sys;\n\t\tled-failsafe = &led_sys;\n\t\tled-running = &led_sys;\n\t\tled-upgrade = &led_sys;\n\t};\t\n\n\tmemory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x0 0x8000000>;\n\t};\n\n\tleds {\n\t\tpinctrl-names = \"default\";\n\t\tpinctrl-0 = <&pinmux_disable_sys_led>;\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled_sys: sys {\n\t\t\tlabel = \"green:sys\";\n\t\t\tgpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;\n\t\t};\n\t};\n\n\tgpio1: rtl8231-gpio {\n\t\tcompatible = \"realtek,rtl8231-gpio\";\n\t\t#gpio-cells = <2>;\n\t\tindirect-access-bus-id = <3>;\n\t\tgpio-controller;\n\t};\n\n\tgpio-restart {\n\t\tcompatible = \"gpio-restart\";\n\t\tgpios = <&gpio1 5 GPIO_ACTIVE_LOW>;\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys-polled\";\n\t\tpoll-interval = <20>;\n\n\t\tmode {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio1 3 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\t/* i2c of the left SFP cage: port 49 */\n\ti2c0: i2c-gpio-0 {\n\t\tcompatible = \"i2c-gpio\";\n\t\tsda-gpios = <&gpio1 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\t\tscl-gpios = <&gpio1 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\t\ti2c-gpio,delay-us = <2>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t};\n\n\tsfp0: sfp-p9 {\n\t\tcompatible = \"sff,sfp\";\n\t\ti2c-bus = <&i2c0>;\n\t\tlos-gpio = <&gpio1 27 GPIO_ACTIVE_HIGH>;\n\t\ttx-fault-gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>;\n\t\tmod-def0-gpio = <&gpio1 26 GPIO_ACTIVE_LOW>;\n\t\ttx-disable-gpio = <&gpio1 23 GPIO_ACTIVE_HIGH>;\n\t};\n\n\t/* i2c of the right SFP cage: port 50 */\n\ti2c1: i2c-gpio-1 {\n\t\tcompatible = \"i2c-gpio\";\n\t\tsda-gpios = <&gpio1 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\t\tscl-gpios = <&gpio1 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;\n\t\ti2c-gpio,delay-us = <2>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t};\n\n\tsfp1: sfp-p10 {\n\t\tcompatible = \"sff,sfp\";\n\t\ti2c-bus = <&i2c1>;\n\t\tlos-gpio = <&gpio1 33 GPIO_ACTIVE_HIGH>;\n\t\ttx-fault-gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>;\n\t\tmod-def0-gpio = <&gpio1 32 GPIO_ACTIVE_LOW>;\n\t\ttx-disable-gpio = <&gpio1 29 GPIO_ACTIVE_HIGH>;\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x40000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@40000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x40000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@50000 {\n\t\t\t\tlabel = \"u-boot-env2\";\n\t\t\t\treg = <0x50000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@60000 {\n\t\t\t\tlabel = \"jffs\";\n\t\t\t\treg = <0x60000 0x100000>;\n\t\t\t};\n\t\t\tpartition@160000 {\n\t\t\t\tlabel = \"jffs2\";\n\t\t\t\treg = <0x160000 0x100000>;\n\t\t\t};\n\t\t\tpartition@b260000 {\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x260000 0xda0000>;\n\t\t\t\tcompatible = \"openwrt,uimage\", \"denx,uimage\";\n\t\t\t\topenwrt,ih-magic = <0x83800000>;\n\t\t\t};\n\t\t\tpartition@930000 {\n\t\t\t\tlabel = \"runtime2\";\n\t\t\t\treg = <0x930000 0x6d0000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&ethernet0 {\n\tmdio: mdio-bus {\n\t\tcompatible = \"realtek,rtl838x-mdio\";\n\t\tregmap = <&ethernet0>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\t\n\t\t/* External phy RTL8218B #1 */\n\t\tEXTERNAL_PHY(0)\n\t\tEXTERNAL_PHY(1)\n\t\tEXTERNAL_PHY(2)\n\t\tEXTERNAL_PHY(3)\n\t\tEXTERNAL_PHY(4)\n\t\tEXTERNAL_PHY(5)\n\t\tEXTERNAL_PHY(6)\n\t\tEXTERNAL_PHY(7)\n\n\t\t/* External phy RTL8218B #2 */\n\t\tEXTERNAL_PHY(8)\n\t\tEXTERNAL_PHY(9)\n\t\tEXTERNAL_PHY(10)\n\t\tEXTERNAL_PHY(11)\n\t\tEXTERNAL_PHY(12)\n\t\tEXTERNAL_PHY(13)\n\t\tEXTERNAL_PHY(14)\n\t\tEXTERNAL_PHY(15)\n\n\t\t/* External phy RTL8218B #3 */\n\t\tEXTERNAL_PHY(16)\n\t\tEXTERNAL_PHY(17)\n\t\tEXTERNAL_PHY(18)\n\t\tEXTERNAL_PHY(19)\n\t\tEXTERNAL_PHY(20)\n\t\tEXTERNAL_PHY(21)\n\t\tEXTERNAL_PHY(22)\n\t\tEXTERNAL_PHY(23)\n\n\t\t/* External phy RTL8218B #4 */\n\t\tEXTERNAL_PHY(24)\n\t\tEXTERNAL_PHY(25)\n\t\tEXTERNAL_PHY(26)\n\t\tEXTERNAL_PHY(27)\n\t\tEXTERNAL_PHY(28)\n\t\tEXTERNAL_PHY(29)\n\t\tEXTERNAL_PHY(30)\n\t\tEXTERNAL_PHY(31)\n\n\t\t/* External phy RTL8218B #5 */\n\t\tEXTERNAL_PHY(32)\n\t\tEXTERNAL_PHY(33)\n\t\tEXTERNAL_PHY(34)\n\t\tEXTERNAL_PHY(35)\n\t\tEXTERNAL_PHY(36)\n\t\tEXTERNAL_PHY(37)\n\t\tEXTERNAL_PHY(38)\n\t\tEXTERNAL_PHY(39)\n\n\t\t/* External phy RTL8218B #6 */\n\t\tEXTERNAL_PHY(40)\n\t\tEXTERNAL_PHY(41)\n\t\tEXTERNAL_PHY(42)\n\t\tEXTERNAL_PHY(43)\n\t\tEXTERNAL_PHY(44)\n\t\tEXTERNAL_PHY(45)\n\t\tEXTERNAL_PHY(46)\n\t\tEXTERNAL_PHY(47)\n\n\t\t/* RTL8393 Internal SerDes */\n\t\tINTERNAL_PHY(48)\n\t\tINTERNAL_PHY(49)\n\t};\n};\n\n&switch0 {\n\tports {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tSWITCH_PORT(0, 01, qsgmii)\n\t\tSWITCH_PORT(1, 02, qsgmii)\n\t\tSWITCH_PORT(2, 03, qsgmii)\n\t\tSWITCH_PORT(3, 04, qsgmii)\n\t\tSWITCH_PORT(4, 05, qsgmii)\n\t\tSWITCH_PORT(5, 06, qsgmii)\n\t\tSWITCH_PORT(6, 07, qsgmii)\n\t\tSWITCH_PORT(7, 08, qsgmii)\n\n\t\tSWITCH_PORT(8, 09, qsgmii)\n\t\tSWITCH_PORT(9, 10, qsgmii)\n\t\tSWITCH_PORT(10, 11, qsgmii)\n\t\tSWITCH_PORT(11, 12, qsgmii)\n\t\tSWITCH_PORT(12, 13, qsgmii)\n\t\tSWITCH_PORT(13, 14, qsgmii)\n\t\tSWITCH_PORT(14, 15, qsgmii)\n\t\tSWITCH_PORT(15, 16, qsgmii)\n\n\t\tSWITCH_PORT(16, 17, qsgmii)\n\t\tSWITCH_PORT(17, 18, qsgmii)\n\t\tSWITCH_PORT(18, 19, qsgmii)\n\t\tSWITCH_PORT(19, 20, qsgmii)\n\t\tSWITCH_PORT(20, 21, qsgmii)\n\t\tSWITCH_PORT(21, 22, qsgmii)\n\t\tSWITCH_PORT(22, 23, qsgmii)\n\t\tSWITCH_PORT(23, 24, qsgmii)\n\n\t\tSWITCH_PORT(24, 25, qsgmii)\n\t\tSWITCH_PORT(25, 26, qsgmii)\n\t\tSWITCH_PORT(26, 27, qsgmii)\n\t\tSWITCH_PORT(27, 28, qsgmii)\n\t\tSWITCH_PORT(28, 29, qsgmii)\n\t\tSWITCH_PORT(29, 30, qsgmii)\n\t\tSWITCH_PORT(30, 31, qsgmii)\n\t\tSWITCH_PORT(31, 32, qsgmii)\n\n\t\tSWITCH_PORT(32, 33, qsgmii)\n\t\tSWITCH_PORT(33, 34, qsgmii)\n\t\tSWITCH_PORT(34, 35, qsgmii)\n\t\tSWITCH_PORT(35, 36, qsgmii)\n\t\tSWITCH_PORT(36, 37, qsgmii)\n\t\tSWITCH_PORT(37, 38, qsgmii)\n\t\tSWITCH_PORT(38, 39, qsgmii)\n\t\tSWITCH_PORT(39, 40, qsgmii)\n\n\t\tSWITCH_PORT(40, 41, qsgmii)\n\t\tSWITCH_PORT(41, 42, qsgmii)\n\t\tSWITCH_PORT(42, 43, qsgmii)\n\t\tSWITCH_PORT(43, 44, qsgmii)\n\t\tSWITCH_PORT(44, 45, qsgmii)\n\t\tSWITCH_PORT(45, 46, qsgmii)\n\t\tSWITCH_PORT(46, 47, qsgmii)\n\t\tSWITCH_PORT(47, 48, qsgmii)\n\n\t\t/* SFP cages */\n\t\tport@48 {\n\t\t\treg = <48>;\n\t\t\tlabel = \"lan49\";\n\t\t\tphy-mode = \"sgmii\";\n\t\t\tphy-handle = <&phy48>;\n\t\t\tsfp = <&sfp0>;\n\n\t\t\tfixed-link {\n\t\t\t\tspeed = <1000>;\n\t\t\t\tfull-duplex;\n\t\t\t\tpause;\n\t\t\t};\n\n\t\t};\n\n\t\tport@49 {\n\t\t\treg = <49>;\n\t\t\tlabel = \"lan50\";\n\t\t\tphy-mode = \"sgmii\";\n\t\t\tphy-handle = <&phy49>;\n\t\t\tsfp = <&sfp1>;\n\n\t\t\tfixed-link {\n\t\t\t\tspeed = <1000>;\n\t\t\t\tfull-duplex;\n\t\t\t\tpause;\n\t\t\t};\n\n\t\t};\n\n\t\t/* CPU-Port */\n\t\tport@52 {\n\t\t\tethernet = <&ethernet0>;\n\t\t\treg = <52>;\n\t\t\tphy-mode = \"qsgmii\";\n\t\t\tfixed-link {\n\t\t\t\tspeed = <1000>;\n\t\t\t\tfull-duplex;\n\t\t\t};\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/realtek/dts-5.10/rtl839x.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n/dts-v1/;\n\n#define STRINGIZE(s) #s\n#define LAN_LABEL(p, s) STRINGIZE(p ## s)\n#define SWITCH_PORT_LABEL(n) LAN_LABEL(lan, n)\n\n#define INTERNAL_PHY(n) \\\n\tphy##n: ethernet-phy@##n { \\\n\t\treg = <##n>; \\\n\t\tcompatible = \"ethernet-phy-ieee802.3-c22\"; \\\n\t\tphy-is-integrated; \\\n\t};\n\n#define EXTERNAL_PHY(n) \\\n\tphy##n: ethernet-phy@##n { \\\n\t\treg = <##n>; \\\n\t\tcompatible = \"ethernet-phy-ieee802.3-c22\"; \\\n\t};\n\n#define EXTERNAL_SFP_PHY(n) \\\n\tphy##n: ethernet-phy@##n { \\\n\t\tcompatible = \"ethernet-phy-ieee802.3-c22\"; \\\n\t\tsfp; \\\n\t\tmedia = \"fibre\"; \\\n\t\treg = <##n>; \\\n\t};\n\n#define SWITCH_PORT(n, s, m) \\\n\tport@##n { \\\n\t\treg = <##n>; \\\n\t\tlabel = SWITCH_PORT_LABEL(s) ; \\\n\t\tphy-handle = <&phy##n>; \\\n\t\tphy-mode = #m ; \\\n\t};\n\n#define SWITCH_SFP_PORT(n, s, m) \\\n\tport@##n { \\\n\t\treg = <##n>; \\\n\t\tlabel = SWITCH_PORT_LABEL(s) ; \\\n\t\tphy-handle = <&phy##n>; \\\n\t\tphy-mode = #m ; \\\n\t\tfixed-link { \\\n\t\t\tspeed = <1000>; \\\n\t\t\tfull-duplex; \\\n\t\t}; \\\n\t};\n\n/ {\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tcompatible = \"realtek,rtl839x-soc\";\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tfrequency = <700000000>;\n\n\t\tcpu@0 {\n\t\t\tcompatible = \"mips,mips34Kc\";\n\t\t\treg = <0>;\n\t\t};\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200\";\n\t};\n\n\tlx_clk: lx_clk {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <200000000>;\n\t};\n\n\tcpuintc: cpuintc {\n\t\tcompatible = \"mti,cpu-interrupt-controller\";\n\t\t#address-cells = <0>;\n\t\t#interrupt-cells = <1>;\n\t\tinterrupt-controller;\n\t};\n\n\tsoc: soc {\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tranges = <0x0 0x18000000 0x10000>;\n\n\t\tintc: interrupt-controller@3000 {\n\t\t\tcompatible = \"realtek,rtl8390-intc\", \"realtek,rtl-intc\";\n\t\t\treg = <0x3000 0x18>, <0x3018 0x18>;\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <2>;\n\n\t\t\tinterrupt-parent = <&cpuintc>;\n\t\t\tinterrupts = <2>, <3>, <4>, <5>, <6>;\n\t\t};\n\n\t\tspi0: spi@1200 {\n\t\t\tcompatible = \"realtek,rtl8380-spi\";\n\t\t\treg = <0x1200 0x100>;\n\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tuart0: uart@2000 {\n\t\t\tcompatible = \"ns16550a\";\n\t\t\treg = <0x2000 0x100>;\n\n\t\t\tclocks = <&lx_clk>;\n\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <31 1>;\n\n\t\t\treg-io-width = <1>;\n\t\t\treg-shift = <2>;\n\t\t\tfifo-size = <1>;\n\t\t\tno-loopback-test;\n\t\t};\n\n\t\tuart1: uart@2100 {\n\t\t\tpinctrl-names = \"default\";\n\t\t\tpinctrl-0 = <&enable_uart1>;\n\n\t\t\tcompatible = \"ns16550a\";\n\t\t\treg = <0x2100 0x100>;\n\n\t\t\tclocks = <&lx_clk>;\n\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <30 2>;\n\n\t\t\treg-io-width = <1>;\n\t\t\treg-shift = <2>;\n\t\t\tfifo-size = <1>;\n\t\t\tno-loopback-test;\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\tgpio0: gpio-controller@3500 {\n\t\t\tcompatible = \"realtek,rtl8390-gpio\", \"realtek,otto-gpio\";\n\t\t\treg = <0x3500 0x20>;\n\n\t\t\tgpio-controller;\n\t\t\t#gpio-cells = <2>;\n\t\t\tngpios = <24>;\n\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <23 2>;\n\t\t};\n\n\t\twatchdog0: watchdog@3150 {\n\t\t\tcompatible = \"realtek,rtl8390-wdt\";\n\t\t\treg = <0x3150 0xc>;\n\n\t\t\trealtek,reset-mode = \"soc\";\n\n\t\t\tclocks = <&lx_clk>;\n\t\t\ttimeout-sec = <30>;\n\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupt-names = \"phase1\", \"phase2\";\n\t\t\tinterrupts = <19 4>, <18 4>;\n\t\t};\n\n\t};\n\n\tpinmux@1b000004 {\n\t\tcompatible = \"pinctrl-single\";\n\t\treg = <0x1b000004 0x4>;\n\n\t\tpinctrl-single,bit-per-mux;\n\t\tpinctrl-single,register-width = <32>;\n\t\tpinctrl-single,function-mask = <0x1>;\n\t\t#pinctrl-cells = <2>;\n\n\t\tenable_uart1: pinmux_enable_uart1 {\n\t\t\tpinctrl-single,bits = <0x0 0x1 0x3>;\n\t\t};\n\t};\n\n\t/* LED_GLB_CTRL */\n\tpinmux@1b0000e4 {\n\t\tcompatible = \"pinctrl-single\";\n\t\treg = <0x1b0000e4 0x4>;\n\n\t\tpinctrl-single,bit-per-mux;\n\t\tpinctrl-single,register-width = <32>;\n\t\tpinctrl-single,function-mask = <0x1>;\n\t\t#pinctrl-cells = <2>;\n\n\t\t/* enable GPIO 0 */\n\t\tpinmux_disable_sys_led: disable_sys_led {\n\t\t\tpinctrl-single,bits = <0x0 0x0 0x4000>;\n\t\t};\n\t};\n\n\tethernet0: ethernet@1b00a300 {\n\t\tcompatible = \"realtek,rtl838x-eth\";\n\t\treg = <0x1b00a300 0x100>;\n\n\t\tinterrupt-parent = <&intc>;\n\t\tinterrupts = <24 3>;\n\n\t\tphy-mode = \"internal\";\n\n\t\tfixed-link {\n\t\t\tspeed = <1000>;\n\t\t\tfull-duplex;\n\t\t};\n\t};\n\n\tswitch0: switch@1b000000 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"realtek,rtl83xx-switch\";\n\n\t\tinterrupt-parent = <&intc>;\n\t\tinterrupts = <20 2>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/realtek/dts-5.10/rtl83xx_panasonic_mxxeg-pn28xx0k.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/gpio/gpio.h>\n#include <dt-bindings/leds/common.h>\n\n/ {\n\tchosen {\n\t\tbootargs = \"console=ttyS0,9600\";\n\t};\n\n\tmemory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x0 0x8000000>;\n\t};\n\n\tleds: leds {\n\t\tcompatible = \"gpio-leds\";\n\n\t\tled-0 {\n\t\t\tlabel = \"amber:any_col\";\n\t\t\tgpios = <&gpio2 0 GPIO_ACTIVE_LOW>;\n\t\t\tcolor = <LED_COLOR_ID_AMBER>;\n\t\t\tfunction = LED_FUNCTION_FAULT;\n\t\t};\n\n\t\tled-1 {\n\t\t\tlabel = \"green:giga\";\n\t\t\tgpios = <&gpio2 8 GPIO_ACTIVE_LOW>;\n\t\t\tcolor = <LED_COLOR_ID_GREEN>;\n\t\t\tfunction = LED_FUNCTION_INDICATOR;\n\t\t\tfunction-enumerator = <1>;\n\t\t};\n\n\t\tled-2 {\n\t\t\tlabel = \"green:100m\";\n\t\t\tgpios = <&gpio2 9 GPIO_ACTIVE_LOW>;\n\t\t\tcolor = <LED_COLOR_ID_GREEN>;\n\t\t\tfunction = LED_FUNCTION_INDICATOR;\n\t\t\tfunction-enumerator = <2>;\n\t\t};\n\n\t\tled-3 {\n\t\t\tlabel = \"green:full\";\n\t\t\tgpios = <&gpio2 10 GPIO_ACTIVE_LOW>;\n\t\t\tcolor = <LED_COLOR_ID_GREEN>;\n\t\t\tfunction = LED_FUNCTION_INDICATOR;\n\t\t\tfunction-enumerator = <3>;\n\t\t};\n\n\t\tled-4 {\n\t\t\tlabel = \"green:loop_history\";\n\t\t\tgpios = <&gpio2 11 GPIO_ACTIVE_LOW>;\n\t\t\tcolor = <LED_COLOR_ID_GREEN>;\n\t\t\tfunction = LED_FUNCTION_INDICATOR;\n\t\t\tfunction-enumerator = <4>;\n\t\t};\n\t};\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\tled_mode {\n\t\t\tlabel = \"led-mode\";\n\t\t\tgpios = <&gpio2 15 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <BTN_0>;\n\t\t};\n\t};\n\n\tgpio-restart {\n\t\tcompatible = \"gpio-restart\";\n\t\tgpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;\n\t};\n\n\ti2c_gpio_0: i2c-gpio-0 {\n\t\tcompatible = \"i2c-gpio\";\n\t\ti2c-gpio,delay-us = <2>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tgpio1: gpio@20 {\n\t\t\tcompatible = \"nxp,pca9555\";\n\t\t\treg = <0x20>;\n\t\t\tgpio-controller;\n\t\t\t#gpio-cells = <2>;\n\t\t};\n\n\t\tgpio2: gpio@75 {\n\t\t\tcompatible = \"nxp,pca9539\";\n\t\t\treg = <0x75>;\n\t\t\tgpio-controller;\n\t\t\t#gpio-cells = <2>;\n\n\t\t\t/*\n\t\t\t * GPIO14 (IO1_6): Shift Register RESET (port LED)\n\t\t\t * - Switch-M8eG  PN28080K:  3x 74HC164\n\t\t\t * - Switch-M24eG PN28240K:  6x 74HC164\n\t\t\t * - Switch-M48eG PN28480K: 12x 74HC164\n\t\t\t */\n\t\t\tportled_sregister_reset {\n\t\t\t\tgpio-hog;\n\t\t\t\tgpios = <14 GPIO_ACTIVE_HIGH>;\n\t\t\t\toutput-high;\n\t\t\t\tline-name = \"portled-sregister-reset\";\n\t\t\t};\n\t\t};\n\t};\n\n\ti2c_gpio_1: i2c-gpio-1 {\n\t\tcompatible = \"i2c-gpio\";\n\t\ti2c-gpio,delay-us = <2>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\ti2c_switch: i2c-switch@70 {\n\t\t\tcompatible = \"nxp,pca9545\";\n\t\t\treset-gpios = <&gpio2 13 GPIO_ACTIVE_LOW>;\n\t\t\treg = <0x70>;\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0x80000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@80000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0x80000 0x10000>;\n\t\t\t};\n\n\t\t\tpartition@90000 {\n\t\t\t\tlabel = \"u-boot-env2\";\n\t\t\t\treg = <0x90000 0x10000>;\n\t\t\t};\n\n\t\t\tpartition@a0000 {\n\t\t\t\tlabel = \"sysinfo\";\n\t\t\t\treg = <0xa0000 0x60000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\t/*\n\t\t\t * Filesystem area in stock firmware\n\t\t\t * (0x100000-0x1DFFFFF)\n\t\t\t *\n\t\t\t * stock firmware images are required to pass\n\t\t\t * the checking by the U-Boot, also for OpenWrt\n\t\t\t *\n\t\t\t * in OpenWrt:\n\t\t\t * - 0x100000-0xDFFFFF (13M): stock images\n\t\t\t * - 0xE00000-0x1DFFFFF(16M): OpenWrt image\n\t\t\t */\n\t\t\tpartition@100000 {\n\t\t\t\tlabel = \"fs_reserved\";\n\t\t\t\treg = <0x100000 0xd00000>;\n\t\t\t};\n\n\t\t\tpartition@e00000 {\n\t\t\t\tcompatible = \"denx,uimage\";\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0xe00000 0x1000000>;\n\t\t\t};\n\n\t\t\tpartition@1e00000 {\n\t\t\t\tlabel = \"vlog_data\";\n\t\t\t\treg = <0x1e00000 0x100000>;\n\t\t\t\tread-only;\n\t\t\t};\n\n\t\t\tpartition@1f00000 {\n\t\t\t\tlabel = \"elog_data\";\n\t\t\t\treg = <0x1f00000 0x100000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/realtek/dts-5.10/rtl9302_zyxel_xgs1250-12.dts",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later\n/dts-v1/;\n\n#include \"rtl930x.dtsi\"\n\n#include <dt-bindings/input/input.h>\n#include <dt-bindings/gpio/gpio.h>\n\n/ {\n\tcompatible = \"zyxel,xgs1250-12\", \"realtek,rtl838x-soc\";\n\tmodel = \"Zyxel XGS1250-12 Switch\";\n\n\tkeys {\n\t\tcompatible = \"gpio-keys\";\n\n\t\tmode {\n\t\t\tlabel = \"reset\";\n\t\t\tgpios = <&gpio0 22 GPIO_ACTIVE_LOW>;\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t};\n\t};\n\n\t/* i2c of the SFP cage: port 12 */\n\ti2c0: i2c-rtl9300 {\n\t\tcompatible = \"realtek,rtl9300-i2c\";\n\t\treg = <0x1b00036c 0x3c>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tsda-pin = <10>;\n\t\tscl-pin = <8>;\n\t\tclock-frequency = <100000>;\n\t};\n\n\n\tsfp0: sfp-p12 {\n\t\tcompatible = \"sff,sfp\";\n\t\ti2c-bus = <&i2c0>;\n\t\tlos-gpio = <&gpio0 17 GPIO_ACTIVE_HIGH>;\n\t\ttx-fault-gpio = <&gpio0 20 GPIO_ACTIVE_HIGH>;\n\t\tmod-def0-gpio = <&gpio0 16 GPIO_ACTIVE_LOW>;\n\t\ttx-disable-gpio = <&gpio0 15 GPIO_ACTIVE_HIGH>;\n\t};\n\n\tled_set: led_set@0 {\n\t\tcompatible = \"realtek,rtl9300-leds\";\n\t\tled_set0 = <0x0000 0xffff 0x0a20 0x0b80>; // LED set 0: 1000Mbps,  10/100Mbps\n\t\tled_set1 = <0x0a0b 0x0a28 0x0a82 0x0a0b>; // LED set 1: (10G, 5G, 2.5G) (2.5G, 1G)\n\t\t\t\t\t\t\t  // (5G, 10/100) (10G, 5G, 2.5G)\n\t\tled_set2 = <0x0000 0xffff 0x0a20 0x0a01>; // LED set 2: 1000MBit, 10GBit\n\t};\n};\n\n&spi0 {\n\tstatus = \"okay\";\n\tflash@0 {\n\t\tcompatible = \"jedec,spi-nor\";\n\t\treg = <0>;\n\t\tspi-max-frequency = <10000000>;\n\n\t\tpartitions {\n\t\t\tcompatible = \"fixed-partitions\";\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <1>;\n\n\t\t\tpartition@0 {\n\t\t\t\tlabel = \"u-boot\";\n\t\t\t\treg = <0x0 0xe0000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@e0000 {\n\t\t\t\tlabel = \"u-boot-env\";\n\t\t\t\treg = <0xe0000 0x10000>;\n\t\t\t};\n\t\t\tpartition@f0000 {\n\t\t\t\tlabel = \"u-boot-env2\";\n\t\t\t\treg = <0xf0000 0x10000>;\n\t\t\t\tread-only;\n\t\t\t};\n\t\t\tpartition@100000 {\n\t\t\t\tlabel = \"jffs\";\n\t\t\t\treg = <0x100000 0x100000>;\n\t\t\t};\n\t\t\tpartition@200000 {\n\t\t\t\tlabel = \"jffs2\";\n\t\t\t\treg = <0x200000 0x100000>;\n\t\t\t};\n\t\t\tpartition@b300000 {\n\t\t\t\tlabel = \"firmware\";\n\t\t\t\treg = <0x300000 0xce0000>;\n\t\t\t\tcompatible = \"openwrt,uimage\", \"denx,uimage\";\n\t\t\t\topenwrt,ih-magic = <0x93001250>;\n\t\t\t};\n\t\t\tpartition@fe0000 {\n\t\t\t\tlabel = \"log\";\n\t\t\t\treg = <0xfe0000 0x20000>;\n\t\t\t};\n\t\t};\n\t};\n};\n\n&ethernet0 {\n\tmdio: mdio-bus {\n\t\tcompatible = \"realtek,rtl838x-mdio\";\n\t\tregmap = <&ethernet0>;\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\t/* External RTL8218D PHY */\n\t\tphy0: ethernet-phy@0 {\n\t\t\treg = <0>;\n\t\t\tcompatible = \"ethernet-phy-ieee802.3-c22\";\n\t\t\trtl9300,smi-address = <0 0>;\n\t\t\tsds = < 2 >;\n\t\t\t// Disabled because we do not know how to bring up again\n\t\t\t// reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;\n\t\t};\n\t\tphy1: ethernet-phy@1 {\n\t\t\treg = <1>;\n\t\t\tcompatible = \"ethernet-phy-ieee802.3-c22\";\n\t\t\trtl9300,smi-address = <0 1>;\n\t\t};\n\t\tphy2: ethernet-phy@2 {\n\t\t\treg = <2>;\n\t\t\tcompatible = \"ethernet-phy-ieee802.3-c22\";\n\t\t\trtl9300,smi-address = <0 2>;\n\t\t};\n\t\tphy3: ethernet-phy@3 {\n\t\t\treg = <3>;\n\t\t\tcompatible = \"ethernet-phy-ieee802.3-c22\";\n\t\t\trtl9300,smi-address = <0 3>;\n\t\t};\n\t\tphy4: ethernet-phy@4 {\n\t\t\treg = <4>;\n\t\t\tcompatible = \"ethernet-phy-ieee802.3-c22\";\n\t\t\trtl9300,smi-address = <0 4>;\n\t\t};\n\t\tphy5: ethernet-phy@5 {\n\t\t\treg = <5>;\n\t\t\tcompatible = \"ethernet-phy-ieee802.3-c22\";\n\t\t\trtl9300,smi-address = <0 5>;\n\t\t};\n\t\tphy6: ethernet-phy@6 {\n\t\t\treg = <6>;\n\t\t\tcompatible = \"ethernet-phy-ieee802.3-c22\";\n\t\t\trtl9300,smi-address = <0 6>;\n\t\t};\n\t\tphy7: ethernet-phy@7 {\n\t\t\treg = <7>;\n\t\t\tcompatible = \"ethernet-phy-ieee802.3-c22\";\n\t\t\trtl9300,smi-address = <0 7>;\n\t\t};\n\n\t\t/* External Aquantia 113C PHYs */\n\t\tphy24: ethernet-phy@24 {\n\t\t\treg = <24>;\n\t\t\tcompatible = \"ethernet-phy-ieee802.3-c45\";\n\t\t\trtl9300,smi-address = <1 8>;\n\t\t\tsds = < 6 >;\n\t\t\t// Disabled because we do not know how to bring up again\n\t\t\t// reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tphy25: ethernet-phy@25 {\n\t\t\treg = <25>;\n\t\t\tcompatible = \"ethernet-phy-ieee802.3-c45\";\n\t\t\trtl9300,smi-address = <2 8>;\n\t\t\tsds = < 7 >;\n\t\t\t// Disabled because we do not know how to bring up again\n\t\t\t// reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\tphy26: ethernet-phy@26 {\n\t\t\treg = <26>;\n\t\t\tcompatible = \"ethernet-phy-ieee802.3-c45\";\n\t\t\trtl9300,smi-address = <3 8>;\n\t\t\tsds = < 8 >;\n\t\t\t// Disabled because we do not know how to bring up again\n\t\t\t// reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;\n\t\t};\n\n\t\t/* SFP Ports */\n\t\tphy27: ethernet-phy@27 {\n\t\t\tcompatible = \"ethernet-phy-ieee802.3-c22\";\n\t\t\tphy-is-integrated;\n\t\t\treg = <27>;\n\t\t\trtl9300,smi-address = <4 0>;\n\t\t\tsds = < 9 >;\n\t\t};\n\n\t};\n};\n\n&switch0 {\n\tports {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\tport@0 {\n\t\t\treg = <0>;\n\t\t\tlabel = \"lan1\";\n\t\t\tphy-handle = <&phy0>;\n\t\t\tphy-mode = \"xgmii\";\n\t\t\tled-set = <0>;\n\t\t};\n\t\tport@1 {\n\t\t\treg = <1>;\n\t\t\tlabel = \"lan2\";\n\t\t\tphy-handle = <&phy1>;\n\t\t\tphy-mode = \"xgmii\";\n\t\t\tled-set = <0>;\n\t\t};\n\t\tport@2 {\n\t\t\treg = <2>;\n\t\t\tlabel = \"lan3\";\n\t\t\tphy-handle = <&phy2>;\n\t\t\tphy-mode = \"xgmii\";\n\t\t\tled-set = <0>;\n\t\t};\n\t\tport@3 {\n\t\t\treg = <3>;\n\t\t\tlabel = \"lan4\";\n\t\t\tphy-handle = <&phy3>;\n\t\t\tphy-mode = \"xgmii\";\n\t\t\tled-set = <0>;\n\t\t};\n\t\tport@4 {\n\t\t\treg = <4>;\n\t\t\tlabel = \"lan5\";\n\t\t\tphy-handle = <&phy4>;\n\t\t\tphy-mode = \"xgmii\";\n\t\t\tled-set = <0>;\n\t\t};\n\t\tport@5 {\n\t\t\treg = <5>;\n\t\t\tlabel = \"lan6\";\n\t\t\tphy-handle = <&phy5>;\n\t\t\tphy-mode = \"xgmii\";\n\t\t\tled-set = <0>;\n\t\t};\n\t\tport@6 {\n\t\t\treg = <6>;\n\t\t\tlabel = \"lan7\";\n\t\t\tphy-handle = <&phy6>;\n\t\t\tphy-mode = \"xgmii\";\n\t\t\tled-set = <0>;\n\t\t};\n\t\tport@7 {\n\t\t\treg = <7>;\n\t\t\tlabel = \"lan8\";\n\t\t\tphy-handle = <&phy7>;\n\t\t\tphy-mode = \"xgmii\";\n\t\t\tled-set = <0>;\n\t\t};\n\n\t\tport@24 {\n\t\t\treg = <24>;\n\t\t\tlabel = \"lan9\";\n\t\t\tphy-mode = \"usxgmii\";\n\t\t\tphy-handle = <&phy24>;\n\t\t\tled-set = <1>;\n\t\t};\n\t\tport@25 {\n\t\t\treg = <25>;\n\t\t\tlabel = \"lan10\";\n\t\t\tphy-mode = \"usxgmii\";\n\t\t\tphy-handle = <&phy25>;\n\t\t\tled-set = <1>;\n\t\t};\n\t\tport@26 {\n\t\t\treg = <26>;\n\t\t\tlabel = \"lan11\";\n\t\t\tphy-mode = \"usxgmii\";\n\t\t\tphy-handle = <&phy26>;\n\t\t\tled-set = <1>;\n\t\t};\n\n\t\tport@27 {\n\t\t\treg = <27>;\n\t\t\tlabel = \"lan12\";\n\t\t\tphy-mode = \"10gbase-r\";\n\t\t\tphy-handle = <&phy27>;\n\t\t\tsfp = <&sfp0>;\n\t\t\tled-set = <2>;\n\n\t\t\tfixed-link {\n\t\t\t\tspeed = <10000>;\n\t\t\t\tfull-duplex;\n\t\t\t\tpause;\n\t\t\t};\n\n\t\t};\n\n\t\tport@28 {\n\t\t\tethernet = <&ethernet0>;\n\t\t\treg = <28>;\n\t\t\tphy-mode = \"internal\";\n\t\t\tfixed-link {\n\t\t\t\tspeed = <10000>;\n\t\t\t\tfull-duplex;\n\t\t\t};\n\t\t};\n\t};\n};\n"
  },
  {
    "path": "target/linux/realtek/dts-5.10/rtl930x.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n/dts-v1/;\n\n/ {\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\n\tcompatible = \"realtek,rtl838x-soc\";\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tfrequency = <800000000>;\n\n\t\tcpu@0 {\n\t\t\tcompatible = \"mips,mips34Kc\";\n\t\t\treg = <0>;\n\t\t};\n\t};\n\n\tmemory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x0 0x8000000>;\n\t};\n\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200\";\n\t};\n\n\tcpuintc: cpuintc {\n\t\tcompatible = \"mti,cpu-interrupt-controller\";\n\t\t#address-cells = <0>;\n\t\t#interrupt-cells = <1>;\n\t\tinterrupt-controller;\n\t};\n\n\tlx_clk: lx_clk {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency  = <175000000>;\n\t};\n\n\tsoc: soc {\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tranges = <0x0 0x18000000 0x10000>;\n\n\t\tintc: interrupt-controller@3000 {\n\t\t\tcompatible = \"realtek,rtl9300-intc\", \"realtek,rtl-intc\";\n\t\t\treg = <0x3000 0x18>, <0x3018 0x18>;\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <2>;\n\n\t\t\tinterrupt-parent = <&cpuintc>;\n\t\t\tinterrupts = <2>, <3>, <4>, <5>, <6>, <7>;\n\t\t};\n\n\t\trtl9300clock: rtl9300clock@3200 {\n\t\t\tcompatible = \"realtek,rtl9300clock\";\n\t\t\treg = <0x3200 0x10>, <0x3210 0x10>;\n\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <7 5>, <8 5>;\n\t\t};\n\n\t\tspi0: spi@1200 {\n\t\t\tcompatible = \"realtek,rtl8380-spi\";\n\t\t\treg = <0x1200 0x100>;\n\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\tuart0: uart@2000 {\n\t\t\tcompatible = \"ns16550a\";\n\t\t\treg = <0x2000 0x100>;\n\n\t\t\tclocks = <&lx_clk>;\n\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <30 1>;\n\n\t\t\treg-io-width = <1>;\n\t\t\treg-shift = <2>;\n\t\t\tfifo-size = <1>;\n\t\t\tno-loopback-test;\n\t\t};\n\n\t\tuart1: uart@2100 {\n\t\t\tcompatible = \"ns16550a\";\n\t\t\treg = <0x2100 0x100>;\n\n\t\t\tclocks = <&lx_clk>;\n\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <31 0>;\n\n\t\t\treg-io-width = <1>;\n\t\t\treg-shift = <2>;\n\t\t\tfifo-size = <1>;\n\t\t\tno-loopback-test;\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\n\t\twatchdog0: watchdog@3260 {\n\t\t\tcompatible = \"realtek,rtl9300-wdt\";\n\t\t\treg = <0x3260 0xc>;\n\n\t\t\trealtek,reset-mode = \"soc\";\n\n\t\t\tclocks = <&lx_clk>;\n\t\t\ttimeout-sec = <30>;\n\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupt-names = \"phase1\", \"phase2\";\n\t\t\tinterrupts = <5 4>, <6 4>;\n\t\t};\n\n\t\tgpio0: gpio-controller@3300 {\n\t\t\tcompatible = \"realtek,rtl9300-gpio\", \"realtek,otto-gpio\";\n\t\t\treg = <0x3300 0x1c>, <0x3338 0x8>;\n\n\t\t\tgpio-controller;\n\t\t\t#gpio-cells = <2>;\n\t\t\tngpios = <24>;\n\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <2>;\n\t\t\tinterrupt-parent = <&intc>;\n\t\t\tinterrupts = <13 1>;\n\t\t};\n\n\t};\n\n\tethernet0: ethernet@1b00a300 {\n\t\tcompatible = \"realtek,rtl838x-eth\";\n\t\treg = <0x1b00a300 0x100>;\n\n\t\tinterrupt-parent = <&intc>;\n\t\tinterrupts = <24 3>;\n\n\t\tphy-mode = \"internal\";\n\n\t\tfixed-link {\n\t\t\tspeed = <1000>;\n\t\t\tfull-duplex;\n\t\t};\n\t};\n\n\tswitch0: switch@1b000000 {\n\t\tcompatible = \"realtek,rtl83xx-switch\";\n\t\tstatus = \"okay\";\n\n\t\tinterrupt-parent = <&intc>;\n\t\tinterrupts = <23 2>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/realtek/dts-5.10/rtl931x.dtsi",
    "content": "// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n\n#include <dt-bindings/interrupt-controller/mips-gic.h>\n\n/ {\n\t#address-cells = <1>;\n\t#size-cells = <1>;\n\t\n\tcompatible = \"realtek,rtl838x-soc\";\n\n\tcpus {\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\t\tfrequency = <1000000000>;\n\n\t\tcpu@0 {\n\t\t\tcompatible = \"mti,interaptive\";\n\t\t\treg = <0>;\n\t\t};\n\n\t\tcpu@1 {\n\t\t\tcompatible = \"mti,interaptive\";\n\t\t\treg = <1>;\n\t\t};\n\t};\n\n\tmemory@0 {\n\t\tdevice_type = \"memory\";\n\t\treg = <0x0 0x10000000>;\n\t};\n\t\n\tchosen {\n\t\tbootargs = \"console=ttyS0,115200\";\n\t};\n\n\tlx_clk: lx_clk {\n\t\tcompatible = \"fixed-clock\";\n\t\t#clock-cells = <0>;\n\t\tclock-frequency = <200000000>;\n\t};\n\n\tcpuclock: cpuclock@0 {\n\t\t#clock-cells = <0>;\n\t\tcompatible = \"fixed-clock\";\n\n\t\t/* FIXME: there should be way to detect this */\n\t\tclock-frequency = <1000000000>;\n\t};\n\n\tcpuintc: cpuintc {\n\t\tcompatible = \"mti,cpu-interrupt-controller\";\n\t\t#address-cells = <0>;\n\t\t#interrupt-cells = <1>;\n\t\tinterrupt-controller;\n\t};\n\n\tgic: interrupt-controller@1ddc0000 {\n\t\tcompatible = \"mti,gic\";\n\t\treg = <0x1ddc0000 0x20000>;\n\n\t\tinterrupt-controller;\n\t\t#interrupt-cells = <3>;\n\n\t\t/*\n\t\t * Declare the interrupt-parent even though the mti,gic\n\t\t * binding doesn't require it, such that the kernel can\n\t\t * figure out that cpu_intc is the root interrupt\n\t\t * controller & should be probed first.\n\t\t */\n\t\tinterrupt-parent = <&cpuintc>;\n\n\t\ttimer {\n\t\t\tcompatible = \"mti,gic-timer\";\n\t\t\tinterrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;\n\t\t\tclocks = <&cpuclock>;\n\t\t};\n\t};\n\t\n\tsoc: soc {\n\t\tcompatible = \"simple-bus\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <1>;\n\t\tranges = <0x0 0x18000000 0x10000>;\n\n\t\tspi0: spi@1200 {\n\t\t\tstatus = \"okay\";\n\n\t\t\tcompatible = \"realtek,rtl8380-spi\";\n\t\t\treg = <0x1200 0x100>;\n\n\t\t\t#address-cells = <1>;\n\t\t\t#size-cells = <0>;\n\t\t};\n\n\t\twatchdog0: watchdog@3260 {\n\t\t\tcompatible = \"realtek,rtl9310-wdt\";\n\t\t\treg = <0x3260 0xc>;\n\n\t\t\trealtek,reset-mode = \"soc\";\n\n\t\t\tclocks = <&lx_clk>;\n\t\t\ttimeout-sec = <30>;\n\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupt-names = \"phase1\", \"phase2\";\n\t\t\tinterrupts = <GIC_SHARED 8 IRQ_TYPE_LEVEL_HIGH>, <GIC_SHARED 9 IRQ_TYPE_LEVEL_HIGH>;\n\t\t};\n\n\t\tgpio0: gpio-controller@3300 {\n\t\t\tcompatible = \"realtek,rtl9310-gpio\", \"realtek,otto-gpio\";\n\t\t\treg = <0x3300 0x1c>;\n\n\t\t\tgpio-controller;\n\t\t\t#gpio-cells = <2>;\n\t\t\tngpios = <32>;\n\n\t\t\tinterrupt-controller;\n\t\t\t#interrupt-cells = <3>;\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\tinterrupts = <GIC_SHARED 20 IRQ_TYPE_LEVEL_HIGH>;\n\t\t};\n\n\t\tuart0: uart@2000 {\n\t\t\tcompatible = \"ns16550a\";\n\t\t\treg = <0x2000 0x100>;\n\n\t\t\tclock-frequency = <200000000>;\n\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\t#interrupt-cells = <3>;\n\t\t\tinterrupts = <GIC_SHARED 22 IRQ_TYPE_LEVEL_HIGH>;\n\n\t\t\treg-io-width = <1>;\n\t\t\treg-shift = <2>;\n\t\t\tfifo-size = <1>;\n\t\t\tno-loopback-test;\n\t\t};\n\n\t\tuart1: uart@2100 {\n\t\t\tcompatible = \"ns16550a\";\n\t\t\treg = <0x2100 0x100>;\n\n\t\t\tclock-frequency = <200000000>;\n\n\t\t\tinterrupt-parent = <&gic>;\n\t\t\t#interrupt-cells = <3>;\n\t\t\tinterrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>;\n\n\t\t\treg-io-width = <1>;\n\t\t\treg-shift = <2>;\n\t\t\tfifo-size = <1>;\n\t\t\tno-loopback-test;\n\n\t\t\tstatus = \"disabled\";\n\t\t};\n\t};\n\n\n\tethernet0: ethernet@1b00a300 {\n\t\tstatus = \"okay\";\n\t\tcompatible = \"realtek,rtl838x-eth\";\n\t\treg = <0x1b00a300 0x100>;\n\t\tinterrupt-parent = <&gic>;\n\t\t#interrupt-cells = <3>;\n\t\tinterrupts = <GIC_SHARED 16 IRQ_TYPE_LEVEL_HIGH>;\n\t\tphy-mode = \"internal\";\n\t\tfixed-link {\n\t\t\tspeed = <1000>;\n\t\t\tfull-duplex;\n\t\t};\n\t};\n\n\tswitch0: switch@1b000000 {\n\t\tcompatible = \"realtek,rtl83xx-switch\";\n\t\tstatus = \"okay\";\n\n\t\tinterrupt-parent = <&gic>;\n\t\t#interrupt-cells = <3>;\n\t\tinterrupts = <GIC_SHARED 15 IRQ_TYPE_LEVEL_HIGH>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/realtek/files-5.10/arch/mips/include/asm/mach-rtl838x/ioremap.h",
    "content": "/* SPDX-License-Identifier: GPL-2.0-only */\n#ifndef RTL838X_IOREMAP_H_\n#define RTL838X_IOREMAP_H_\n\nstatic inline int is_rtl838x_internal_registers(phys_addr_t offset)\n{\n\t/* IO-Block */\n\tif (offset >= 0xb8000000 && offset < 0xb9000000)\n\t\treturn 1;\n\t/* Switch block */\n\tif (offset >= 0xbb000000 && offset < 0xbc000000)\n\t\treturn 1;\n\treturn 0;\n}\n\nstatic inline void __iomem *plat_ioremap(phys_addr_t offset, unsigned long size,\n\t\t\t\t\t unsigned long flags)\n{\n\tif (is_rtl838x_internal_registers(offset))\n\t\treturn (void __iomem *)offset;\n\treturn NULL;\n}\n\nstatic inline int plat_iounmap(const volatile void __iomem *addr)\n{\n\treturn is_rtl838x_internal_registers((unsigned long)addr);\n}\n\n#endif\n"
  },
  {
    "path": "target/linux/realtek/files-5.10/arch/mips/include/asm/mach-rtl838x/mach-rtl83xx.h",
    "content": "/* SPDX-License-Identifier: GPL-2.0-only */\n/*\n * Copyright (C) 2006-2012 Tony Wu (tonywu@realtek.com)\n * Copyright (C) 2020 B. Koblitz\n */\n#ifndef _MACH_RTL838X_H_\n#define _MACH_RTL838X_H_\n\n#include <asm/types.h>\n/*\n * Register access macros\n */\n\n#define RTL838X_SW_BASE\t\t((volatile void *) 0xBB000000)\n\n#define rtl83xx_r32(reg)\treadl(reg)\n#define rtl83xx_w32(val, reg)\twritel(val, reg)\n#define rtl83xx_w32_mask(clear, set, reg) rtl83xx_w32((rtl83xx_r32(reg) & ~(clear)) | (set), reg)\n\n#define rtl83xx_r8(reg)\t\treadb(reg)\n#define rtl83xx_w8(val, reg)\twriteb(val, reg)\n\n#define sw_r32(reg)\t\treadl(RTL838X_SW_BASE + reg)\n#define sw_w32(val, reg)\twritel(val, RTL838X_SW_BASE + reg)\n#define sw_w32_mask(clear, set, reg)\t\\\n\t\t\t\tsw_w32((sw_r32(reg) & ~(clear)) | (set), reg)\n#define sw_r64(reg)\t\t((((u64)readl(RTL838X_SW_BASE + reg)) << 32) | \\\n\t\t\t\treadl(RTL838X_SW_BASE + reg + 4))\n\n#define sw_w64(val, reg)\tdo { \\\n\t\t\t\t\twritel((u32)((val) >> 32), RTL838X_SW_BASE + reg); \\\n\t\t\t\t\twritel((u32)((val) & 0xffffffff), \\\n\t\t\t\t\t\t\tRTL838X_SW_BASE + reg + 4); \\\n\t\t\t\t} while (0)\n\n/*\n * SPRAM\n */\n#define RTL838X_ISPRAM_BASE\t0x0\n#define RTL838X_DSPRAM_BASE\t0x0\n\n/*\n * IRQ Controller\n */\n#define RTL838X_IRQ_CPU_BASE\t0\n#define RTL838X_IRQ_CPU_NUM\t8\n#define RTL838X_IRQ_ICTL_BASE\t(RTL838X_IRQ_CPU_BASE + RTL838X_IRQ_CPU_NUM)\n#define RTL838X_IRQ_ICTL_NUM\t32\n\n#define RTL83XX_IRQ_UART0\t\t31\n#define RTL83XX_IRQ_UART1\t\t30\n#define RTL83XX_IRQ_TC0\t\t\t29\n#define RTL83XX_IRQ_TC1\t\t\t28\n#define RTL83XX_IRQ_OCPTO\t\t27\n#define RTL83XX_IRQ_HLXTO\t\t26\n#define RTL83XX_IRQ_SLXTO\t\t25\n#define RTL83XX_IRQ_NIC\t\t\t24\n#define RTL83XX_IRQ_GPIO_ABCD\t\t23\n#define RTL83XX_IRQ_GPIO_EFGH\t\t22\n#define RTL83XX_IRQ_RTC\t\t\t21\n#define RTL83XX_IRQ_SWCORE\t\t20\n#define RTL83XX_IRQ_WDT_IP1\t\t19\n#define RTL83XX_IRQ_WDT_IP2\t\t18\n\n#define RTL9300_UART1_IRQ\t\t31\n#define RTL9300_UART0_IRQ\t\t30\n#define RTL9300_USB_H2_IRQ\t\t28\n#define RTL9300_NIC_IRQ\t\t\t24\n#define RTL9300_SWCORE_IRQ\t\t23\n#define RTL9300_GPIO_ABC_IRQ\t\t13\n#define RTL9300_TC4_IRQ\t\t\t11\n#define RTL9300_TC3_IRQ\t\t\t10\n#define RTL9300_TC2_IRQ\t\t\t 9\n#define RTL9300_TC1_IRQ\t\t\t 8\n#define RTL9300_TC0_IRQ\t\t\t 7\n\n\n/*\n * MIPS32R2 counter\n */\n#define RTL838X_COMPARE_IRQ\t(RTL838X_IRQ_CPU_BASE + 7)\n\n/*\n *  ICTL\n *  Base address 0xb8003000UL\n */\n#define RTL838X_ICTL1_IRQ\t(RTL838X_IRQ_CPU_BASE + 2)\n#define RTL838X_ICTL2_IRQ\t(RTL838X_IRQ_CPU_BASE + 3)\n#define RTL838X_ICTL3_IRQ\t(RTL838X_IRQ_CPU_BASE + 4)\n#define RTL838X_ICTL4_IRQ\t(RTL838X_IRQ_CPU_BASE + 5)\n#define RTL838X_ICTL5_IRQ\t(RTL838X_IRQ_CPU_BASE + 6)\n\n#define GIMR\t\t\t(0x00)\n#define UART0_IE\t\t(1 << 31)\n#define UART1_IE\t\t(1 << 30)\n#define TC0_IE\t\t\t(1 << 29)\n#define TC1_IE\t\t\t(1 << 28)\n#define OCPTO_IE\t\t(1 << 27)\n#define HLXTO_IE\t\t(1 << 26)\n#define SLXTO_IE\t\t(1 << 25)\n#define NIC_IE\t\t\t(1 << 24)\n#define GPIO_ABCD_IE\t\t(1 << 23)\n#define GPIO_EFGH_IE\t\t(1 << 22)\n#define RTC_IE\t\t\t(1 << 21)\n#define WDT_IP1_IE\t\t(1 << 19)\n#define WDT_IP2_IE\t\t(1 << 18)\n\n#define GISR\t\t\t(0x04)\n#define UART0_IP\t\t(1 << 31)\n#define UART1_IP\t\t(1 << 30)\n#define TC0_IP\t\t\t(1 << 29)\n#define TC1_IP\t\t\t(1 << 28)\n#define OCPTO_IP\t\t(1 << 27)\n#define HLXTO_IP\t\t(1 << 26)\n#define SLXTO_IP\t\t(1 << 25)\n#define NIC_IP\t\t\t(1 << 24)\n#define GPIO_ABCD_IP\t\t(1 << 23)\n#define GPIO_EFGH_IP\t\t(1 << 22)\n#define RTC_IP\t\t\t(1 << 21)\n#define WDT_IP1_IP\t\t(1 << 19)\n#define WDT_IP2_IP\t\t(1 << 18)\n\n\n/* Interrupt Routing Selection */\n#define UART0_RS\t\t2\n#define UART1_RS\t\t1\n#define TC0_RS\t\t\t5\n#define TC1_RS\t\t\t1\n#define OCPTO_RS\t\t1\n#define HLXTO_RS\t\t1\n#define SLXTO_RS\t\t1\n#define NIC_RS\t\t\t4\n#define GPIO_ABCD_RS\t\t4\n#define GPIO_EFGH_RS\t\t4\n#define RTC_RS\t\t\t4\n#define\tSWCORE_RS\t\t3\n#define WDT_IP1_RS\t\t4\n#define WDT_IP2_RS\t\t5\n\n/* Interrupt IRQ Assignments */\n#define UART0_IRQ\t\t31\n#define UART1_IRQ\t\t30\n#define TC0_IRQ\t\t\t29\n#define TC1_IRQ\t\t\t28\n#define OCPTO_IRQ\t\t27\n#define HLXTO_IRQ\t\t26\n#define SLXTO_IRQ\t\t25\n#define NIC_IRQ\t\t\t24\n#define GPIO_ABCD_IRQ\t\t23\n#define GPIO_EFGH_IRQ\t\t22\n#define RTC_IRQ\t\t\t21\n#define\tSWCORE_IRQ\t\t20\n#define WDT_IP1_IRQ\t\t19\n#define WDT_IP2_IRQ\t\t18\n\n#define SYSTEM_FREQ\t\t200000000\n#define RTL838X_UART0_BASE\t((volatile void *)(0xb8002000UL))\n#define RTL838X_UART0_BAUD\t38400  /* ex. 19200 or 38400 or 57600 or 115200 */\n#define RTL838X_UART0_FREQ\t(SYSTEM_FREQ - RTL838X_UART0_BAUD * 24)\n#define RTL838X_UART0_MAPBASE\t0x18002000UL\n#define RTL838X_UART0_MAPSIZE\t0x100\n#define RTL838X_UART0_IRQ\tUART0_IRQ\n\n#define RTL838X_UART1_BASE\t((volatile void *)(0xb8002100UL))\n#define RTL838X_UART1_BAUD\t38400  /* ex. 19200 or 38400 or 57600 or 115200 */\n#define RTL838X_UART1_FREQ\t(SYSTEM_FREQ - RTL838X_UART1_BAUD * 24)\n#define RTL838X_UART1_MAPBASE\t0x18002100UL\n#define RTL838X_UART1_MAPSIZE\t0x100\n#define RTL838X_UART1_IRQ\tUART1_IRQ\n\n#define UART0_RBR\t\t(RTL838X_UART0_BASE + 0x000)\n#define UART0_THR\t\t(RTL838X_UART0_BASE + 0x000)\n#define UART0_DLL\t\t(RTL838X_UART0_BASE + 0x000)\n#define UART0_IER\t\t(RTL838X_UART0_BASE + 0x004)\n#define UART0_DLM\t\t(RTL838X_UART0_BASE + 0x004)\n#define UART0_IIR\t\t(RTL838X_UART0_BASE + 0x008)\n#define UART0_FCR\t\t(RTL838X_UART0_BASE + 0x008)\n#define UART0_LCR\t\t(RTL838X_UART0_BASE + 0x00C)\n#define UART0_MCR\t\t(RTL838X_UART0_BASE + 0x010)\n#define UART0_LSR\t\t(RTL838X_UART0_BASE + 0x014)\n\n#define UART1_RBR\t\t(RTL838X_UART1_BASE + 0x000)\n#define UART1_THR\t\t(RTL838X_UART1_BASE + 0x000)\n#define UART1_DLL\t\t(RTL838X_UART1_BASE + 0x000)\n#define UART1_IER\t\t(RTL838X_UART1_BASE + 0x004)\n#define UART1_DLM\t\t(RTL838X_UART1_BASE + 0x004)\n#define UART1_IIR\t\t(RTL838X_UART1_BASE + 0x008)\n#define UART1_FCR\t\t(RTL838X_UART1_BASE + 0x008)\n#define UART1_LCR\t\t(RTL838X_UART1_BASE + 0x00C)\n#define UART1_MCR\t\t(RTL838X_UART1_BASE + 0x010)\n#define UART1_LSR\t\t(RTL838X_UART1_BASE + 0x014)\n\n/*\n * Memory Controller\n */\n#define MC_MCR\t\t\t0xB8001000\n#define MC_MCR_VAL\t\t0x00000000\n\n#define MC_DCR\t\t\t0xB8001004\n#define MC_DCR0_VAL\t\t0x54480000\n\n#define MC_DTCR\t\t\t0xB8001008\n#define MC_DTCR_VAL\t\t0xFFFF05C0\n\n/*\n * GPIO\n */\n#define GPIO_CTRL_REG_BASE\t\t((volatile void *) 0xb8003500)\n#define RTL838X_GPIO_PABC_CNR\t\t(GPIO_CTRL_REG_BASE + 0x0)\n#define RTL838X_GPIO_PABC_TYPE\t\t(GPIO_CTRL_REG_BASE + 0x04)\n#define RTL838X_GPIO_PABC_DIR\t\t(GPIO_CTRL_REG_BASE + 0x8)\n#define RTL838X_GPIO_PABC_DATA\t\t(GPIO_CTRL_REG_BASE + 0xc)\n#define RTL838X_GPIO_PABC_ISR\t\t(GPIO_CTRL_REG_BASE + 0x10)\n#define RTL838X_GPIO_PAB_IMR\t\t(GPIO_CTRL_REG_BASE + 0x14)\n#define RTL838X_GPIO_PC_IMR\t\t(GPIO_CTRL_REG_BASE + 0x18)\n\n#define RTL930X_GPIO_CTRL_REG_BASE      ((volatile void *) 0xb8003300)\n#define RTL930X_GPIO_PABCD_DIR          (RTL930X_GPIO_CTRL_REG_BASE + 0x8)\n#define RTL930X_GPIO_PABCD_DAT          (RTL930X_GPIO_CTRL_REG_BASE + 0xc)\n#define RTL930X_GPIO_PABCD_ISR          (RTL930X_GPIO_CTRL_REG_BASE + 0x10)\n#define RTL930X_GPIO_PAB_IMR            (RTL930X_GPIO_CTRL_REG_BASE + 0x14)\n#define RTL930X_GPIO_PCD_IMR            (RTL930X_GPIO_CTRL_REG_BASE + 0x18)\n\n#define RTL838X_MODEL_NAME_INFO\t\t(0x00D4)\n#define RTL839X_MODEL_NAME_INFO\t\t(0x0FF0)\n#define RTL93XX_MODEL_NAME_INFO\t\t(0x0004)\n#define RTL931X_CHIP_INFO_ADDR\t\t(0x0008)\n\n#define RTL838X_LED_GLB_CTRL\t\t(0xA000)\n#define RTL839X_LED_GLB_CTRL\t\t(0x00E4)\n#define RTL9302_LED_GLB_CTRL\t\t(0xcc00)\n#define RTL930X_LED_GLB_CTRL\t\t(0xCC00)\n#define RTL931X_LED_GLB_CTRL\t\t(0x0600)\n\n#define RTL838X_EXT_GPIO_DIR\t\t(0xA08C)\n#define RTL839X_EXT_GPIO_DIR\t\t(0x0214)\n#define RTL838X_EXT_GPIO_DATA\t\t(0xA094)\n#define RTL839X_EXT_GPIO_DATA\t\t(0x021c)\n#define RTL838X_EXT_GPIO_INDRT_ACCESS\t(0xA09C)\n#define RTL839X_EXT_GPIO_INDRT_ACCESS\t(0x0224)\n#define RTL838X_EXTRA_GPIO_CTRL\t\t(0xA0E0)\n#define RTL838X_DMY_REG5\t\t(0x0144)\n#define RTL838X_EXTRA_GPIO_CTRL\t\t(0xA0E0)\n\n#define RTL838X_GMII_INTF_SEL\t\t(0x1000)\n#define RTL838X_IO_DRIVING_ABILITY_CTRL\t(0x1010)\n\n#define RTL838X_GPIO_A7\t\t31\n#define RTL838X_GPIO_A6\t\t30\n#define RTL838X_GPIO_A5\t\t29\n#define RTL838X_GPIO_A4\t\t28\n#define RTL838X_GPIO_A3\t\t27\n#define RTL838X_GPIO_A2\t\t26\n#define RTL838X_GPIO_A1\t\t25\n#define RTL838X_GPIO_A0\t\t24\n#define RTL838X_GPIO_B7\t\t23\n#define RTL838X_GPIO_B6\t\t22\n#define RTL838X_GPIO_B5\t\t21\n#define RTL838X_GPIO_B4\t\t20\n#define RTL838X_GPIO_B3\t\t19\n#define RTL838X_GPIO_B2\t\t18\n#define RTL838X_GPIO_B1\t\t17\n#define RTL838X_GPIO_B0\t\t16\n#define RTL838X_GPIO_C7\t\t15\n#define RTL838X_GPIO_C6\t\t14\n#define RTL838X_GPIO_C5\t\t13\n#define RTL838X_GPIO_C4\t\t12\n#define RTL838X_GPIO_C3\t\t11\n#define RTL838X_GPIO_C2\t\t10\n#define RTL838X_GPIO_C1\t\t9\n#define RTL838X_GPIO_C0\t\t8\n\n#define RTL838X_INT_RW_CTRL\t\t(0x0058)\n#define RTL838X_EXT_VERSION\t\t(0x00D0)\n#define RTL838X_PLL_CML_CTRL\t\t(0x0FF8)\n#define RTL838X_STRAP_DBG\t\t(0x100C)\n\n/*\n * Reset\n */\n#define\tRGCR\t\t\t\t(0x1E70)\n#define RTL838X_RST_GLB_CTRL_0\t\t(0x003c)\n#define RTL838X_RST_GLB_CTRL_1\t\t(0x0040)\n#define RTL839X_RST_GLB_CTRL\t\t(0x0014)\n#define RTL930X_RST_GLB_CTRL_0\t\t(0x000c)\n#define RTL931X_RST_GLB_CTRL\t\t(0x0400)\n\n/* LED control by switch */\n#define RTL838X_LED_MODE_SEL\t\t(0x1004)\n#define RTL838X_LED_MODE_CTRL\t\t(0xA004)\n#define RTL838X_LED_P_EN_CTRL\t\t(0xA008)\n\n/* LED control by software */\n#define RTL838X_LED_SW_CTRL\t\t(0x0128)\n#define RTL839X_LED_SW_CTRL\t\t(0xA00C)\n#define RTL838X_LED_SW_P_EN_CTRL\t(0xA010)\n#define RTL839X_LED_SW_P_EN_CTRL\t(0x012C)\n#define RTL838X_LED0_SW_P_EN_CTRL\t(0xA010)\n#define RTL839X_LED0_SW_P_EN_CTRL\t(0x012C)\n#define RTL838X_LED1_SW_P_EN_CTRL\t(0xA014)\n#define RTL839X_LED1_SW_P_EN_CTRL\t(0x0130)\n#define RTL838X_LED2_SW_P_EN_CTRL\t(0xA018)\n#define RTL839X_LED2_SW_P_EN_CTRL\t(0x0134)\n#define RTL838X_LED_SW_P_CTRL\t\t(0xA01C)\n#define RTL839X_LED_SW_P_CTRL\t\t(0x0144)\n\n#define RTL839X_MAC_EFUSE_CTRL\t\t(0x02ac)\n\n/*\n * MDIO via Realtek's SMI interface\n */\n#define RTL838X_SMI_GLB_CTRL\t\t(0xa100)\n#define RTL838X_SMI_ACCESS_PHY_CTRL_0\t(0xa1b8)\n#define RTL838X_SMI_ACCESS_PHY_CTRL_1\t(0xa1bc)\n#define RTL838X_SMI_ACCESS_PHY_CTRL_2\t(0xa1c0)\n#define RTL838X_SMI_ACCESS_PHY_CTRL_3\t(0xa1c4)\n#define RTL838X_SMI_PORT0_5_ADDR_CTRL\t(0xa1c8)\n#define RTL838X_SMI_POLL_CTRL\t\t(0xa17c)\n\n#define RTL839X_SMI_GLB_CTRL\t\t(0x03f8)\n#define RTL839X_SMI_PORT_POLLING_CTRL\t(0x03fc)\n#define RTL839X_PHYREG_ACCESS_CTRL\t(0x03DC)\n#define RTL839X_PHYREG_CTRL\t\t(0x03E0)\n#define RTL839X_PHYREG_PORT_CTRL\t(0x03E4)\n#define RTL839X_PHYREG_DATA_CTRL\t(0x03F0)\n#define RTL839X_PHYREG_MMD_CTRL\t\t(0x3F4)\n\n#define RTL930X_SMI_GLB_CTRL\t\t(0xCA00)\n#define RTL930X_SMI_POLL_CTRL\t\t(0xca90)\n#define RTL930X_SMI_PORT0_15_POLLING_SEL (0xCA08)\n#define RTL930X_SMI_PORT16_27_POLLING_SEL (0xCA0C)\n#define RTL930X_SMI_PORT0_5_ADDR\t(0xCB80)\n#define RTL930X_SMI_ACCESS_PHY_CTRL_0\t(0xCB70)\n#define RTL930X_SMI_ACCESS_PHY_CTRL_1\t(0xCB74)\n#define RTL930X_SMI_ACCESS_PHY_CTRL_2\t(0xCB78)\n#define RTL930X_SMI_ACCESS_PHY_CTRL_3\t(0xCB7C)\n\n#define RTL931X_SMI_GLB_CTRL1\t\t(0x0CBC)\n#define RTL931X_SMI_GLB_CTRL0\t\t(0x0CC0)\n#define RTL931X_SMI_PORT_POLLING_CTRL\t(0x0CCC)\n#define RTL931X_SMI_PORT_ADDR\t\t(0x0C74)\n#define RTL931X_SMI_PORT_POLLING_SEL\t(0x0C9C)\n#define RTL9310_SMI_PORT_POLLING_CTRL\t(0x0CCC)\n#define RTL931X_SMI_INDRT_ACCESS_CTRL_0\t(0x0C00)\n#define RTL931X_SMI_INDRT_ACCESS_CTRL_1\t(0x0C04)\n#define RTL931X_SMI_INDRT_ACCESS_CTRL_2\t(0x0C08)\n#define RTL931X_SMI_INDRT_ACCESS_CTRL_3\t(0x0C10)\n#define RTL931X_SMI_INDRT_ACCESS_BC_PHYID_CTRL (0x0C14)\n#define RTL931X_SMI_INDRT_ACCESS_MMD_CTRL (0xC18)\n#define RTL931X_MAC_L2_GLOBAL_CTRL2\t(0x1358)\n#define RTL931X_MAC_L2_GLOBAL_CTRL1\t(0x5548)\n\n/*\n * Switch interrupts\n */\n#define RTL838X_IMR_GLB\t\t\t(0x1100)\n#define RTL838X_IMR_PORT_LINK_STS_CHG\t(0x1104)\n#define RTL838X_ISR_GLB_SRC\t\t(0x1148)\n#define RTL838X_ISR_PORT_LINK_STS_CHG\t(0x114C)\n\n#define RTL839X_IMR_GLB\t\t\t(0x0064)\n#define RTL839X_IMR_PORT_LINK_STS_CHG\t(0x0068)\n#define RTL839X_ISR_GLB_SRC\t\t(0x009c)\n#define RTL839X_ISR_PORT_LINK_STS_CHG\t(0x00a0)\n\n#define RTL930X_IMR_GLB\t\t\t(0xC628)\n#define RTL930X_IMR_PORT_LINK_STS_CHG\t(0xC62C)\n#define RTL930X_ISR_GLB\t\t\t(0xC658)\n#define RTL930X_ISR_PORT_LINK_STS_CHG\t(0xC660)\n\n// IMR_GLB does not exit on RTL931X\n#define RTL931X_IMR_PORT_LINK_STS_CHG\t(0x126C)\n#define RTL931X_ISR_GLB_SRC\t\t(0x12B4)\n#define RTL931X_ISR_PORT_LINK_STS_CHG\t(0x12B8)\n\n/* Definition of family IDs */\n#define RTL8389_FAMILY_ID   (0x8389)\n#define RTL8328_FAMILY_ID   (0x8328)\n#define RTL8390_FAMILY_ID   (0x8390)\n#define RTL8350_FAMILY_ID   (0x8350)\n#define RTL8380_FAMILY_ID   (0x8380)\n#define RTL8330_FAMILY_ID   (0x8330)\n#define RTL9300_FAMILY_ID   (0x9300)\n#define RTL9310_FAMILY_ID   (0x9310)\n\n/* SPI Support */\n#define RTL931X_SPI_CTRL0\t\t(0x103C)\n\n/* Basic SoC Features */\n#define RTL838X_CPU_PORT\t\t\t28\n#define RTL839X_CPU_PORT\t\t\t52\n#define RTL930X_CPU_PORT\t\t\t28\n#define RTL931X_CPU_PORT\t\t\t56\n\nstruct rtl83xx_soc_info {\n\tunsigned char *name;\n\tunsigned int id;\n\tunsigned int family;\n\tunsigned char *compatible;\n\tvolatile void *sw_base;\n\tvolatile void *icu_base;\n\tint cpu_port;\n};\n\n/* rtl83xx-related functions used across subsystems */\nint rtl838x_smi_wait_op(int timeout);\nint rtl838x_read_phy(u32 port, u32 page, u32 reg, u32 *val);\nint rtl838x_write_phy(u32 port, u32 page, u32 reg, u32 val);\nint rtl839x_read_phy(u32 port, u32 page, u32 reg, u32 *val);\nint rtl839x_write_phy(u32 port, u32 page, u32 reg, u32 val);\nint rtl930x_read_phy(u32 port, u32 page, u32 reg, u32 *val);\nint rtl930x_write_phy(u32 port, u32 page, u32 reg, u32 val);\nint rtl931x_read_phy(u32 port, u32 page, u32 reg, u32 *val);\nint rtl931x_write_phy(u32 port, u32 page, u32 reg, u32 val);\n\n#endif   /* _MACH_RTL838X_H_ */\n"
  },
  {
    "path": "target/linux/realtek/files-5.10/arch/mips/kernel/cevt-rtl9300.c",
    "content": "// SPDX-License-Identifier: GPL-2.0-only\n\n#include <linux/clockchips.h>\n#include <linux/init.h>\n#include <asm/time.h>\n#include <asm/idle.h>\n#include <linux/interrupt.h>\n#include <linux/of_address.h>\n#include <linux/of_irq.h>\n#include <linux/sched_clock.h>\n\n#include <mach-rtl83xx.h>\n\n/* \n * Timer registers\n * the RTL9300/9310 SoCs have 6 timers, each register block 0x10 apart\n */\n#define RTL9300_TC_DATA\t\t0x0\n#define RTL9300_TC_CNT\t\t0x4\n#define RTL9300_TC_CTRL\t\t0x8\n#define RTL9300_TC_CTRL_MODE\tBIT(24)\n#define RTL9300_TC_CTRL_EN\tBIT(28)\n#define RTL9300_TC_INT\t\t0xc\n#define RTL9300_TC_INT_IP\tBIT(16)\n#define RTL9300_TC_INT_IE\tBIT(20)\n\n// Timer modes\n#define TIMER_MODE_REPEAT\t1\n#define TIMER_MODE_ONCE\t\t0\n\n// Minimum divider is 2\n#define DIVISOR_RTL9300\t\t2\n\n#define N_BITS\t\t\t28\n\n#define RTL9300_CLOCK_RATE\t87500000\n\nstruct rtl9300_clk_dev {\n\tstruct clock_event_device clkdev;\n\tvoid __iomem *base;\n};\n\nstatic void __iomem *rtl9300_tc_base(struct clock_event_device *clk)\n{\n\tstruct rtl9300_clk_dev *rtl_clk = container_of(clk, struct rtl9300_clk_dev, clkdev);\n\n\treturn rtl_clk->base;\n}\n\nstatic irqreturn_t rtl9300_timer_interrupt(int irq, void *dev_id)\n{\n\tstruct rtl9300_clk_dev *rtl_clk = dev_id;\n\tstruct clock_event_device *clk = &rtl_clk->clkdev;\n\n\tu32 v = readl(rtl_clk->base + RTL9300_TC_INT);\n\n\t// Acknowledge the IRQ\n\tv |= RTL9300_TC_INT_IP;\n\twritel(v, rtl_clk->base + RTL9300_TC_INT);\n\n\tclk->event_handler(clk);\n\treturn IRQ_HANDLED;\n}\n\nstatic void rtl9300_clock_stop(void __iomem *base)\n{\n\tu32 v;\n\n\twritel(0, base + RTL9300_TC_CTRL);\n\n\t// Acknowledge possibly pending IRQ\n\tv = readl(base + RTL9300_TC_INT);\n\twritel(v | RTL9300_TC_INT_IP, base + RTL9300_TC_INT);\n}\n\nstatic void rtl9300_timer_start(void __iomem *base, bool periodic)\n{\n\tu32 v = (periodic ? RTL9300_TC_CTRL_MODE : 0) | RTL9300_TC_CTRL_EN | DIVISOR_RTL9300;\n\n\twritel(0, base + RTL9300_TC_CNT);\n\tpr_debug(\"------------- starting timer base %08x\\n\", (u32)base);\n\twritel(v, base + RTL9300_TC_CTRL);\n}\n\nstatic int rtl9300_next_event(unsigned long delta, struct clock_event_device *clk)\n{\n\tvoid __iomem *base = rtl9300_tc_base(clk);\n\n\trtl9300_clock_stop(base);\n\twritel(delta, base + RTL9300_TC_DATA);\n\trtl9300_timer_start(base, TIMER_MODE_ONCE);\n\n\treturn 0;\n}\n\nstatic int rtl9300_state_periodic(struct clock_event_device *clk)\n{\n\tvoid __iomem *base = rtl9300_tc_base(clk);\n\n\tpr_debug(\"------------- rtl9300_state_periodic %08x\\n\", (u32)base);\n\trtl9300_clock_stop(base);\n\twritel(RTL9300_CLOCK_RATE / HZ, base + RTL9300_TC_DATA);\n\trtl9300_timer_start(base, TIMER_MODE_REPEAT);\n\treturn 0;\n}\n\nstatic int rtl9300_state_oneshot(struct clock_event_device *clk)\n{\n\tvoid __iomem *base = rtl9300_tc_base(clk);\n\n\tpr_debug(\"------------- rtl9300_state_oneshot %08x\\n\", (u32)base);\n\trtl9300_clock_stop(base);\n\twritel(RTL9300_CLOCK_RATE / HZ, base + RTL9300_TC_DATA);\n\trtl9300_timer_start(base, TIMER_MODE_ONCE);\n\treturn 0;\n}\n\nstatic int rtl9300_shutdown(struct clock_event_device *clk)\n{\n\tvoid __iomem *base = rtl9300_tc_base(clk);\n\n\tpr_debug(\"------------- rtl9300_shutdown %08x\\n\", (u32)base);\n\trtl9300_clock_stop(base);\n\treturn 0;\n}\n\nstatic void rtl9300_clock_setup(void __iomem *base)\n{\n\tu32 v;\n\n\t// Disable timer\n\twritel(0, base + RTL9300_TC_CTRL);\n\n\t// Acknowledge possibly pending IRQ\n\tv = readl(base + RTL9300_TC_INT);\n\twritel(v | RTL9300_TC_INT_IP, base + RTL9300_TC_INT);\n\n\t// Setup maximum period (for use as clock-source)\n\twritel(0x0fffffff, base + RTL9300_TC_DATA);\n}\n\nstatic DEFINE_PER_CPU(struct rtl9300_clk_dev, rtl9300_clockevent);\nstatic DEFINE_PER_CPU(char [18], rtl9300_clock_name);\n\nvoid rtl9300_clockevent_init(void)\n{\n\tint cpu = smp_processor_id();\n\tint irq;\n\tstruct rtl9300_clk_dev *rtl_clk = &per_cpu(rtl9300_clockevent, cpu);\n\tstruct clock_event_device *cd = &rtl_clk->clkdev;\n\tunsigned char *name = per_cpu(rtl9300_clock_name, cpu);\n\tunsigned long flags =  IRQF_PERCPU | IRQF_TIMER;\n\tstruct device_node *node;\n\n\tpr_info(\"%s called for cpu%d\\n\", __func__, cpu);\n\tBUG_ON(cpu > 3);\t/* Only have 4 general purpose timers */\n\n\tnode = of_find_compatible_node(NULL, NULL, \"realtek,rtl9300clock\");\n\tif (!node) {\n\t\tpr_err(\"No DT entry found for realtek,rtl9300clock\\n\");\n\t\treturn;\n\t}\n\n\tirq = irq_of_parse_and_map(node, cpu);\n\tpr_info(\"%s using IRQ %d\\n\", __func__, irq);\n\n\trtl_clk->base = of_iomap(node, cpu);\n\tif (!rtl_clk->base) {\n\t\tpr_err(\"cannot map timer for cpu %d\", cpu);\n\t\treturn;\n\t}\n\n\trtl9300_clock_setup(rtl_clk->base);\n\n\tsprintf(name, \"rtl9300-counter-%d\", cpu);\n\tcd->name\t\t= name;\n\tcd->features\t\t= CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;\n\n\tclockevent_set_clock(cd, RTL9300_CLOCK_RATE);\n\n\tcd->max_delta_ns\t= clockevent_delta2ns(0x0fffffff, cd);\n\tcd->max_delta_ticks\t= 0x0fffffff;\n\tcd->min_delta_ns\t= clockevent_delta2ns(0x20, cd);\n\tcd->min_delta_ticks\t= 0x20;\n\tcd->rating\t\t= 300;\n\tcd->irq\t\t\t= irq;\n\tcd->cpumask\t\t= cpumask_of(cpu);\n\tcd->set_next_event\t= rtl9300_next_event;\n\tcd->set_state_shutdown\t= rtl9300_shutdown;\n\tcd->set_state_periodic\t= rtl9300_state_periodic;\n\tcd->set_state_oneshot\t= rtl9300_state_oneshot;\n\tclockevents_register_device(cd);\n\n\tirq_set_affinity(irq, cd->cpumask);\n\n\tif (request_irq(irq, rtl9300_timer_interrupt, flags, name, rtl_clk))\n\t\tpr_err(\"Failed to request irq %d (%s)\\n\", irq, name);\n\n\twritel(RTL9300_TC_INT_IE, rtl_clk->base + RTL9300_TC_INT);\n}\n"
  },
  {
    "path": "target/linux/realtek/files-5.10/arch/mips/rtl838x/Makefile",
    "content": "#\n# Makefile for the rtl838x specific parts of the kernel\n#\n\nobj-y := setup.o prom.o\n"
  },
  {
    "path": "target/linux/realtek/files-5.10/arch/mips/rtl838x/Platform",
    "content": "#\n# Realtek RTL838x SoCs\n#\ncflags-$(CONFIG_RTL83XX)   += -I$(srctree)/arch/mips/include/asm/mach-rtl838x/\nload-$(CONFIG_RTL83XX)     += 0xffffffff80000000\n"
  },
  {
    "path": "target/linux/realtek/files-5.10/arch/mips/rtl838x/prom.c",
    "content": "// SPDX-License-Identifier: GPL-2.0-only\n/*\n * prom.c\n * Early intialization code for the Realtek RTL838X SoC\n *\n * based on the original BSP by\n * Copyright (C) 2006-2012 Tony Wu (tonywu@realtek.com)\n * Copyright (C) 2020 B. Koblitz\n *\n */\n\n#include <linux/init.h>\n#include <linux/kernel.h>\n#include <linux/string.h>\n#include <linux/of_fdt.h>\n#include <linux/libfdt.h>\n#include <asm/bootinfo.h>\n#include <asm/addrspace.h>\n#include <asm/page.h>\n#include <asm/cpu.h>\n#include <asm/smp-ops.h>\n#include <asm/mips-cps.h>\n\n#include <mach-rtl83xx.h>\n\nextern char arcs_cmdline[];\nextern const char __appended_dtb;\n\nstruct rtl83xx_soc_info soc_info;\nconst void *fdt;\n\nconst char *get_system_type(void)\n{\n\treturn soc_info.name;\n}\n\nvoid __init prom_free_prom_memory(void)\n{\n\n}\n\nvoid __init device_tree_init(void)\n{\n\tif (!fdt_check_header(&__appended_dtb)) {\n\t\tfdt = &__appended_dtb;\n\t\tpr_info(\"Using appended Device Tree.\\n\");\n\t}\n\tinitial_boot_params = (void *)fdt;\n\tunflatten_and_copy_device_tree();\n}\n\nstatic void __init prom_init_cmdline(void)\n{\n\tint argc = fw_arg0;\n\tchar **argv = (char **) KSEG1ADDR(fw_arg1);\n\tint i;\n\n\tarcs_cmdline[0] = '\\0';\n\n\tfor (i = 0; i < argc; i++) {\n\t\tchar *p = (char *) KSEG1ADDR(argv[i]);\n\n\t\tif (CPHYSADDR(p) && *p) {\n\t\t\tstrlcat(arcs_cmdline, p, sizeof(arcs_cmdline));\n\t\t\tstrlcat(arcs_cmdline, \" \", sizeof(arcs_cmdline));\n\t\t}\n\t}\n\tpr_info(\"Kernel command line: %s\\n\", arcs_cmdline);\n}\n\nvoid __init identify_rtl9302(void)\n{\n\tswitch (sw_r32(RTL93XX_MODEL_NAME_INFO) & 0xfffffff0) {\n\tcase 0x93020810:\n\t\tsoc_info.name = \"RTL9302A 12x2.5G\";\n\t\tbreak;\n\tcase 0x93021010:\n\t\tsoc_info.name = \"RTL9302B 8x2.5G\";\n\t\tbreak;\n\tcase 0x93021810:\n\t\tsoc_info.name = \"RTL9302C 16x2.5G\";\n\t\tbreak;\n\tcase 0x93022010:\n\t\tsoc_info.name = \"RTL9302D 24x2.5G\";\n\t\tbreak;\n\tcase 0x93020800:\n\t\tsoc_info.name = \"RTL9302A\";\n\t\tbreak;\n\tcase 0x93021000:\n\t\tsoc_info.name = \"RTL9302B\";\n\t\tbreak;\n\tcase 0x93021800:\n\t\tsoc_info.name = \"RTL9302C\";\n\t\tbreak;\n\tcase 0x93022000:\n\t\tsoc_info.name = \"RTL9302D\";\n\t\tbreak;\n\tcase 0x93023001:\n\t\tsoc_info.name = \"RTL9302F\";\n\t\tbreak;\n\tdefault:\n\t\tsoc_info.name = \"RTL9302\";\n\t}\n}\n\nvoid __init prom_init(void)\n{\n\tuint32_t model;\n\n\t/* uart0 */\n\tsetup_8250_early_printk_port(0xb8002000, 2, 0);\n\n\tmodel = sw_r32(RTL838X_MODEL_NAME_INFO);\n\tpr_info(\"RTL838X model is %x\\n\", model);\n\tmodel = model >> 16 & 0xFFFF;\n\n\tif ((model != 0x8328) && (model != 0x8330) && (model != 0x8332)\n\t    && (model != 0x8380) && (model != 0x8382)) {\n\t\tmodel = sw_r32(RTL839X_MODEL_NAME_INFO);\n\t\tpr_info(\"RTL839X model is %x\\n\", model);\n\t\tmodel = model >> 16 & 0xFFFF;\n\t}\n\n\tif ((model & 0x8390) != 0x8380 && (model & 0x8390) != 0x8390) {\n\t\tmodel = sw_r32(RTL93XX_MODEL_NAME_INFO);\n\t\tpr_info(\"RTL93XX model is %x\\n\", model);\n\t\tmodel = model >> 16 & 0xFFFF;\n\t}\n\n\tsoc_info.id = model;\n\n\tswitch (model) {\n\tcase 0x8328:\n\t\tsoc_info.name = \"RTL8328\";\n\t\tsoc_info.family = RTL8328_FAMILY_ID;\n\t\tbreak;\n\tcase 0x8332:\n\t\tsoc_info.name = \"RTL8332\";\n\t\tsoc_info.family = RTL8380_FAMILY_ID;\n\t\tbreak;\n\tcase 0x8380:\n\t\tsoc_info.name = \"RTL8380\";\n\t\tsoc_info.family = RTL8380_FAMILY_ID;\n\t\tbreak;\n\tcase 0x8382:\n\t\tsoc_info.name = \"RTL8382\";\n\t\tsoc_info.family = RTL8380_FAMILY_ID;\n\t\tbreak;\n\tcase 0x8390:\n\t\tsoc_info.name = \"RTL8390\";\n\t\tsoc_info.family = RTL8390_FAMILY_ID;\n\t\tbreak;\n\tcase 0x8391:\n\t\tsoc_info.name = \"RTL8391\";\n\t\tsoc_info.family = RTL8390_FAMILY_ID;\n\t\tbreak;\n\tcase 0x8392:\n\t\tsoc_info.name = \"RTL8392\";\n\t\tsoc_info.family = RTL8390_FAMILY_ID;\n\t\tbreak;\n\tcase 0x8393:\n\t\tsoc_info.name = \"RTL8393\";\n\t\tsoc_info.family = RTL8390_FAMILY_ID;\n\t\tbreak;\n\tcase 0x9301:\n\t\tsoc_info.name = \"RTL9301\";\n\t\tsoc_info.family = RTL9300_FAMILY_ID;\n\t\tbreak;\n\tcase 0x9302:\n\t\tidentify_rtl9302();\n\t\tsoc_info.family = RTL9300_FAMILY_ID;\n\t\tbreak;\n\tcase 0x9303:\n\t\tsoc_info.name = \"RTL9303\";\n\t\tsoc_info.family = RTL9300_FAMILY_ID;\n\t\tbreak;\n\tcase 0x9313:\n\t\tsoc_info.name = \"RTL9313\";\n\t\tsoc_info.family = RTL9310_FAMILY_ID;\n\t\tbreak;\n\tdefault:\n\t\tsoc_info.name = \"DEFAULT\";\n\t\tsoc_info.family = 0;\n\t}\n\n\tpr_info(\"SoC Type: %s\\n\", get_system_type());\n\n\t/* Early detection of CMP support */\n\tif(soc_info.family == RTL9310_FAMILY_ID) {\n\t\tmips_cm_probe();\n\t\tmips_cpc_probe();\n\t}\n\n\tprom_init_cmdline();\n\n#ifdef  CONFIG_MIPS_CPS\n\tif (!register_cps_smp_ops()) {\n\t\treturn;\n\t}\n#endif\n#ifdef CONFIG_MIPS_MT_SMP\n\tif (!register_vsmp_smp_ops()) {\n\t\treturn;\n\t}\n#endif\n\tregister_up_smp_ops();\n}\n"
  },
  {
    "path": "target/linux/realtek/files-5.10/arch/mips/rtl838x/setup.c",
    "content": "// SPDX-License-Identifier: GPL-2.0-only\n/*\n * Setup for the Realtek RTL838X SoC:\n *\tMemory, Timer and Serial\n *\n * Copyright (C) 2020 B. Koblitz\n * based on the original BSP by\n * Copyright (C) 2006-2012 Tony Wu (tonywu@realtek.com)\n *\n */\n\n#include <linux/console.h>\n#include <linux/init.h>\n#include <linux/clkdev.h>\n#include <linux/clk-provider.h>\n#include <linux/delay.h>\n#include <linux/of_fdt.h>\n#include <linux/irqchip.h>\n\n#include <asm/addrspace.h>\n#include <asm/io.h>\n#include <asm/bootinfo.h>\n#include <asm/time.h>\n#include <asm/prom.h>\n#include <asm/smp-ops.h>\n\n#include \"mach-rtl83xx.h\"\n\nextern struct rtl83xx_soc_info soc_info;\n\nstatic void __init rtl838x_setup(void)\n{\n\t/* Setup System LED. Bit 15 then allows to toggle it */\n\tsw_w32_mask(0, 3 << 16, RTL838X_LED_GLB_CTRL);\n}\n\nstatic void __init rtl839x_setup(void)\n{\n\t/* Setup System LED. Bit 14 of RTL839X_LED_GLB_CTRL then allows to toggle it */\n\tsw_w32_mask(0, 3 << 15, RTL839X_LED_GLB_CTRL);\n}\n\nstatic void __init rtl930x_setup(void)\n{\n\tif (soc_info.id == 0x9302)\n\t\tsw_w32_mask(0, 3 << 13, RTL9302_LED_GLB_CTRL);\n\telse\n\t\tsw_w32_mask(0, 3 << 13, RTL930X_LED_GLB_CTRL);\n}\n\nstatic void __init rtl931x_setup(void)\n{\n\tsw_w32_mask(0, 3 << 12, RTL931X_LED_GLB_CTRL);\n}\n\nvoid __init plat_mem_setup(void)\n{\n\tvoid *dtb;\n\n\tset_io_port_base(KSEG1);\n\n\tif (fw_passed_dtb) /* UHI interface */\n\t\tdtb = (void *)fw_passed_dtb;\n\telse if (__dtb_start != __dtb_end)\n\t\tdtb = (void *)__dtb_start;\n\telse\n\t\tpanic(\"no dtb found\");\n\n\t/*\n\t * Load the devicetree. This causes the chosen node to be\n\t * parsed resulting in our memory appearing\n\t */\n\t__dt_setup_arch(dtb);\n\n\tswitch (soc_info.family) {\n\tcase RTL8380_FAMILY_ID:\n\t\trtl838x_setup();\n\t\tbreak;\n\tcase RTL8390_FAMILY_ID:\n\t\trtl839x_setup();\n\t\tbreak;\n\tcase RTL9300_FAMILY_ID:\n\t\trtl930x_setup();\n\t\tbreak;\n\tcase RTL9310_FAMILY_ID:\n\t\trtl931x_setup();\n\t\tbreak;\n\t}\n}\n\nvoid __init plat_time_init(void)\n{\n\tstruct device_node *np;\n\tu32 freq = 500000000;\n\n\tof_clk_init(NULL);\n\ttimer_probe();\n\n\tnp = of_find_node_by_name(NULL, \"cpus\");\n\tif (!np) {\n\t\tpr_err(\"Missing 'cpus' DT node, using default frequency.\");\n\t} else {\n\t\tif (of_property_read_u32(np, \"frequency\", &freq) < 0)\n\t\t\tpr_err(\"No 'frequency' property in DT, using default.\");\n\t\telse\n\t\t\tpr_info(\"CPU frequency from device tree: %dMHz\", freq / 1000000);\n\t\tof_node_put(np);\n\t}\n\n\tmips_hpt_frequency = freq / 2;\n}\n\nvoid __init arch_init_irq(void)\n{\n\tirqchip_init();\n}\n"
  },
  {
    "path": "target/linux/realtek/files-5.10/drivers/gpio/gpio-rtl8231.c",
    "content": "// SPDX-License-Identifier: GPL-2.0-only\n\n#include <linux/gpio/driver.h>\n#include <linux/module.h>\n#include <linux/platform_device.h>\n#include <linux/delay.h>\n#include <asm/mach-rtl838x/mach-rtl83xx.h>\n\n/* RTL8231 registers for LED control */\n#define RTL8231_LED_FUNC0\t\t\t0x0000\n#define RTL8231_LED_FUNC1\t\t\t0x0001\n#define RTL8231_READY_MASK\t\t\t0x03f0\n#define RTL8231_READY_VALUE\t\t\t0x0370\n#define RTL8231_GPIO_PIN_SEL(gpio)\t\t((0x0002) + ((gpio) >> 4))\n#define RTL8231_GPIO_DIR(gpio)\t\t\t((0x0005) + ((gpio) >> 4))\n#define RTL8231_GPIO_DATA(gpio)\t\t\t((0x001C) + ((gpio) >> 4))\n\n#define USEC_TIMEOUT 5000\n\n#define RTL8231_SMI_BUS_ID_MAX\t\t\t0x1F\n\nstruct rtl8231_gpios {\n\tstruct gpio_chip gc;\n\tstruct device *dev;\n\tu32 id;\n\tu32 smi_bus_id;\n\tu16 reg_shadow[0x20];\n\tu32 reg_cached;\n\tint ext_gpio_indrt_access;\n};\n\nextern struct mutex smi_lock;\nextern struct rtl83xx_soc_info soc_info;\n\nstatic u32 rtl8231_read(struct rtl8231_gpios *gpios, u32 reg)\n{\n\tu32 t = 0, n = 0;\n\n\treg &= 0x1f;\n\n\t/* Calculate read register address */\n\tt = (gpios->smi_bus_id << 2) | (reg << 7);\n\n\t/* Set execution bit: cleared when operation completed */\n\tt |= 1;\n\n\t// Start execution\n\tsw_w32(t, gpios->ext_gpio_indrt_access);\n\tdo {\n\t\tudelay(1);\n\t\tt = sw_r32(gpios->ext_gpio_indrt_access);\n\t\tn++;\n\t} while ((t & 1) && (n < USEC_TIMEOUT));\n\n\tif (n >= USEC_TIMEOUT)\n\t\treturn 0x80000000;\n\t\n\tpr_debug(\"%s: %x, %x, %x\\n\", __func__, gpios->smi_bus_id,\n\t\treg, (t & 0xffff0000) >> 16);\n\n\treturn (t & 0xffff0000) >> 16;\n}\n\nstatic int rtl8231_write(struct rtl8231_gpios *gpios, u32 reg, u32 data)\n{\n\tu32 t = 0, n = 0;\n\n\tpr_debug(\"%s: %x, %x, %x\\n\", __func__, gpios->smi_bus_id, reg, data);\n\treg &= 0x1f;\n\n\tt = (gpios->smi_bus_id << 2) | (reg << 7) | (data << 16);\n\t/* Set write bit */\n\tt |= 2;\n\n\t/* Set execution bit: cleared when operation completed */\n\tt |= 1;\n\n\t// Start execution\n\tsw_w32(t, gpios->ext_gpio_indrt_access);\n\tdo {\n\t\tudelay(1);\n\t\tt = sw_r32(gpios->ext_gpio_indrt_access);\n\t} while ((t & 1) && (n < USEC_TIMEOUT));\n\n\tif (n >= USEC_TIMEOUT)\n\t\treturn -1;\n\n\treturn 0;\n}\n\nstatic u32 rtl8231_read_cached(struct rtl8231_gpios *gpios, u32 reg)\n{\n\tif (reg > 0x1f)\n\t\treturn 0;\n\n\tif (gpios->reg_cached & (1 << reg))\n\t\treturn gpios->reg_shadow[reg];\n\n\treturn rtl8231_read(gpios, reg);\n}\n\n/* Set Direction of the RTL8231 pin:\n * dir 1: input\n * dir 0: output\n */\nstatic int rtl8231_pin_dir(struct rtl8231_gpios *gpios, u32 gpio, u32 dir)\n{\n\tu32 v;\n\tint pin_sel_addr = RTL8231_GPIO_PIN_SEL(gpio);\n\tint pin_dir_addr = RTL8231_GPIO_DIR(gpio);\n\tint dpin = gpio % 16;\n\n\tif (gpio > 31) {\n\t\tpr_debug(\"WARNING: HIGH pin\\n\");\n\t\tdpin += 5;\n\t\tpin_dir_addr = pin_sel_addr;\n\t}\n\n\tv = rtl8231_read_cached(gpios, pin_dir_addr);\n\tif (v & 0x80000000) {\n\t\tpr_err(\"Error reading RTL8231\\n\");\n\t\treturn -1;\n\t}\n\n\tv = (v & ~(1 << dpin)) | (dir << dpin);\n\trtl8231_write(gpios, pin_dir_addr, v);\n\tgpios->reg_shadow[pin_dir_addr] = v;\n\tgpios->reg_cached |= 1 << pin_dir_addr;\n\treturn 0;\n}\n\nstatic int rtl8231_pin_dir_get(struct rtl8231_gpios *gpios, u32 gpio, u32 *dir)\n{\n\t/* dir 1: input\n\t * dir 0: output\n\t */\n\n\tu32  v;\n\tint pin_dir_addr = RTL8231_GPIO_DIR(gpio);\n\tint pin = gpio % 16;\n\n\tif (gpio > 31) {\n\t\tpin_dir_addr = RTL8231_GPIO_PIN_SEL(gpio);\n\t\tpin += 5;\n\t}\n\n\tv = rtl8231_read(gpios, pin_dir_addr);\n\tif (v & (1 << pin))\n\t\t*dir = 1;\n\telse\n\t\t*dir = 0;\n\treturn 0;\n}\n\nstatic int rtl8231_pin_set(struct rtl8231_gpios *gpios, u32 gpio, u32 data)\n{\n\tu32 v = rtl8231_read(gpios, RTL8231_GPIO_DATA(gpio));\n\n\tpr_debug(\"%s: %d to %d\\n\", __func__, gpio, data);\n\tif (v & 0x80000000) {\n\t\tpr_err(\"Error reading RTL8231\\n\");\n\t\treturn -1;\n\t}\n\tv = (v & ~(1 << (gpio % 16))) | (data << (gpio % 16));\n\trtl8231_write(gpios, RTL8231_GPIO_DATA(gpio), v);\n\tgpios->reg_shadow[RTL8231_GPIO_DATA(gpio)] = v;\n\tgpios->reg_cached |= 1 << RTL8231_GPIO_DATA(gpio);\n\treturn 0;\n}\n\nstatic int rtl8231_pin_get(struct rtl8231_gpios *gpios, u32 gpio, u16 *state)\n{\n\tu32 v = rtl8231_read(gpios, RTL8231_GPIO_DATA(gpio));\n\n\tif (v & 0x80000000) {\n\t\tpr_err(\"Error reading RTL8231\\n\");\n\t\treturn -1;\n\t}\n\n\t*state = v & 0xffff;\n\treturn 0;\n}\n\nstatic int rtl8231_direction_input(struct gpio_chip *gc, unsigned int offset)\n{\n\tint err;\n\tstruct rtl8231_gpios *gpios = gpiochip_get_data(gc);\n\n\tpr_debug(\"%s: %d\\n\", __func__, offset);\n\tmutex_lock(&smi_lock);\n\terr = rtl8231_pin_dir(gpios, offset, 1);\n\tmutex_unlock(&smi_lock);\n\treturn err;\n}\n\nstatic int rtl8231_direction_output(struct gpio_chip *gc, unsigned int offset, int value)\n{\n\tint err;\n\tstruct rtl8231_gpios *gpios = gpiochip_get_data(gc);\n\n\tpr_debug(\"%s: %d\\n\", __func__, offset);\n\tmutex_lock(&smi_lock);\n\terr = rtl8231_pin_dir(gpios, offset, 0);\n\tmutex_unlock(&smi_lock);\n\tif (!err)\n\t\terr = rtl8231_pin_set(gpios, offset, value);\n\treturn err;\n}\n\nstatic int rtl8231_get_direction(struct gpio_chip *gc, unsigned int offset)\n{\n\tu32 v = 0;\n\tstruct rtl8231_gpios *gpios = gpiochip_get_data(gc);\n\n\tpr_debug(\"%s: %d\\n\", __func__, offset);\n\tmutex_lock(&smi_lock);\n\trtl8231_pin_dir_get(gpios, offset, &v);\n\tmutex_unlock(&smi_lock);\n\treturn v;\n}\n\nstatic int rtl8231_gpio_get(struct gpio_chip *gc, unsigned int offset)\n{\n\tu16 state = 0;\n\tstruct rtl8231_gpios *gpios = gpiochip_get_data(gc);\n\n\tmutex_lock(&smi_lock);\n\trtl8231_pin_get(gpios, offset, &state);\n\tmutex_unlock(&smi_lock);\n\tif (state & (1 << (offset % 16)))\n\t\treturn 1;\n\treturn 0;\n}\n\nvoid rtl8231_gpio_set(struct gpio_chip *gc, unsigned int offset, int value)\n{\n\tstruct rtl8231_gpios *gpios = gpiochip_get_data(gc);\n\n\trtl8231_pin_set(gpios, offset, value);\n}\n\nint rtl8231_init(struct rtl8231_gpios *gpios)\n{\n\tu32 ret;\n\n\tpr_info(\"%s called, MDIO bus ID: %d\\n\", __func__, gpios->smi_bus_id);\n\n\tgpios->reg_cached = 0;\n\n\tif (soc_info.family == RTL8390_FAMILY_ID) {\n\t\t// RTL8390: Enable external gpio in global led control register\n\t\tsw_w32_mask(0x7 << 18, 0x4 << 18, RTL839X_LED_GLB_CTRL);\n\t} else if (soc_info.family == RTL8380_FAMILY_ID) {\n\t\t// RTL8380: Enable RTL8231 indirect access mode\n\t\tsw_w32_mask(0, 1, RTL838X_EXTRA_GPIO_CTRL);\n\t\tsw_w32_mask(3, 1, RTL838X_DMY_REG5);\n\t}\n\n\tret = rtl8231_read(gpios, RTL8231_LED_FUNC1);\n\tif ((ret & 0x80000000) || ((ret & RTL8231_READY_MASK) != RTL8231_READY_VALUE))\n\t\treturn -ENXIO;\n\n\t/* Select GPIO functionality and force input direction for pins 0-36 */\n\trtl8231_write(gpios, RTL8231_GPIO_PIN_SEL(0), 0xffff);\n\trtl8231_write(gpios, RTL8231_GPIO_DIR(0), 0xffff);\n\trtl8231_write(gpios, RTL8231_GPIO_PIN_SEL(16), 0xffff);\n\trtl8231_write(gpios, RTL8231_GPIO_DIR(16), 0xffff);\n\trtl8231_write(gpios, RTL8231_GPIO_PIN_SEL(32), 0x03ff);\n\n\t/* Set LED_Start to enable drivers for output mode */\n\trtl8231_write(gpios, RTL8231_LED_FUNC0, 1 << 1);\n\n\treturn 0;\n}\n\nstatic const struct of_device_id rtl8231_gpio_of_match[] = {\n\t{ .compatible = \"realtek,rtl8231-gpio\" },\n\t{},\n};\n\nMODULE_DEVICE_TABLE(of, rtl8231_gpio_of_match);\n\nstatic int rtl8231_gpio_probe(struct platform_device *pdev)\n{\n\tstruct device *dev = &pdev->dev;\n\tstruct device_node *np = dev->of_node;\n\tstruct rtl8231_gpios *gpios;\n\tint err;\n\n\tpr_info(\"Probing RTL8231 GPIOs\\n\");\n\n\tif (!np) {\n\t\tdev_err(&pdev->dev, \"No DT found\\n\");\n\t\treturn -EINVAL;\n\t}\n\n\tgpios = devm_kzalloc(dev, sizeof(*gpios), GFP_KERNEL);\n\tif (!gpios)\n\t\treturn -ENOMEM;\n\n\tgpios->id = soc_info.id;\n\tif (soc_info.family == RTL8380_FAMILY_ID) {\n\t\tgpios->ext_gpio_indrt_access = RTL838X_EXT_GPIO_INDRT_ACCESS;\n\t}\n\n\tif (soc_info.family == RTL8390_FAMILY_ID) {\n\t\tgpios->ext_gpio_indrt_access = RTL839X_EXT_GPIO_INDRT_ACCESS;\n\t}\n\n\terr = of_property_read_u32(np, \"indirect-access-bus-id\", &gpios->smi_bus_id);\n\tif (!err && gpios->smi_bus_id > RTL8231_SMI_BUS_ID_MAX)\n\t\terr = -EINVAL;\n\n\tif (err) {\n\t\tdev_err(dev, \"invalid or missing indirect-access-bus-id\\n\");\n\t\treturn err;\n\t}\n\n\terr = rtl8231_init(gpios);\n\tif (err) {\n\t\tdev_err(dev, \"no device found at bus address %d\\n\", gpios->smi_bus_id);\n\t\treturn err;\n\t}\n\n\tgpios->dev = dev;\n\tgpios->gc.base = -1;\n\tgpios->gc.ngpio = 37;\n\tgpios->gc.label = \"rtl8231\";\n\tgpios->gc.parent = dev;\n\tgpios->gc.owner = THIS_MODULE;\n\tgpios->gc.can_sleep = true;\n\n\tgpios->gc.direction_input = rtl8231_direction_input;\n\tgpios->gc.direction_output = rtl8231_direction_output;\n\tgpios->gc.set = rtl8231_gpio_set;\n\tgpios->gc.get = rtl8231_gpio_get;\n\tgpios->gc.get_direction = rtl8231_get_direction;\n\n\terr = devm_gpiochip_add_data(dev, &gpios->gc, gpios);\n\treturn err;\n}\n\nstatic struct platform_driver rtl8231_gpio_driver = {\n\t.driver = {\n\t\t.name = \"rtl8231-gpio\",\n\t\t.of_match_table\t= rtl8231_gpio_of_match,\n\t},\n\t.probe = rtl8231_gpio_probe,\n};\n\nmodule_platform_driver(rtl8231_gpio_driver);\n\nMODULE_DESCRIPTION(\"Realtek RTL8231 GPIO expansion chip support\");\nMODULE_LICENSE(\"GPL v2\");\n"
  },
  {
    "path": "target/linux/realtek/files-5.10/drivers/i2c/busses/i2c-rtl9300.c",
    "content": "// SPDX-License-Identifier: GPL-2.0-only\n\n#include <linux/module.h>\n#include <linux/of_platform.h>\n#include \"i2c-rtl9300.h\"\n\n#define REG(i, x)\t(i->base + x + (i->scl_num ? i->mst2_offset : 0))\n#define REG_MASK(i, clear, set, reg)\t\\\n\t\t\twritel((readl(REG(i, reg)) & ~(clear)) | (set), REG(i, reg))\n\nstruct i2c_drv_data {\n\tint scl0_pin;\n\tint scl1_pin;\n\tint sda0_pin;\n\tstruct i2c_algorithm *algo;\n\tint (*read)(struct rtl9300_i2c *i2c, u8 *buf, int len);\n\tint (*write)(struct rtl9300_i2c *i2c, u8 *buf, int len);\n\tvoid (*reg_addr_set)(struct rtl9300_i2c *i2c, u32 reg, u16 len);\n\tint (*config_xfer)(struct rtl9300_i2c *i2c, u16 addr, u16 len);\n\tint (*execute_xfer)(struct rtl9300_i2c *i2c, char read_write, int size,\n\t\t\t    union i2c_smbus_data * data, int len);\n\tvoid (*writel)(struct rtl9300_i2c *i2c, u32 data);\n\tvoid (*config_io)(struct rtl9300_i2c *i2c, int scl_num, int sda_num);\n\tu32 mst2_offset;\n};\n\t\t\t\nDEFINE_MUTEX(i2c_lock);\n\nstatic void rtl9300_i2c_reg_addr_set(struct rtl9300_i2c *i2c, u32 reg, u16 len)\n{\n\t// Set register address width\n\tREG_MASK(i2c, 0x3 << RTL9300_I2C_CTRL2_MADDR_WIDTH, len << RTL9300_I2C_CTRL2_MADDR_WIDTH,\n\t\t RTL9300_I2C_CTRL2);\n\n\t// Set register address\n\tREG_MASK(i2c, 0xffffff << RTL9300_I2C_CTRL1_MEM_ADDR, reg << RTL9300_I2C_CTRL1_MEM_ADDR,\n\t\t RTL9300_I2C_CTRL1);\n}\n\nstatic void rtl9310_i2c_reg_addr_set(struct rtl9300_i2c *i2c, u32 reg, u16 len)\n{\n\t// Set register address width\n\tREG_MASK(i2c, 0x3 << RTL9310_I2C_CTRL_MADDR_WIDTH, len << RTL9310_I2C_CTRL_MADDR_WIDTH,\n\t\t RTL9310_I2C_CTRL);\n\n\t// Set register address\n\twritel(reg, REG(i2c, RTL9310_I2C_MEMADDR));\n}\n\nstatic void rtl9300_i2c_config_io(struct rtl9300_i2c *i2c, int scl_num, int sda_num)\n{\n\tu32 v;\n\n\t// Set SCL pin\n\tREG_MASK(i2c, 0, BIT(RTL9300_I2C_CTRL1_GPIO8_SCL_SEL), RTL9300_I2C_CTRL1);\n\n\t// Set SDA pin\n\tREG_MASK(i2c, 0x7 << RTL9300_I2C_CTRL1_SDA_OUT_SEL,\n\t\t i2c->sda_num << RTL9300_I2C_CTRL1_SDA_OUT_SEL, RTL9300_I2C_CTRL1);\n\n\t// Set SDA pin to I2C functionality\n\tv = readl(i2c->base + RTL9300_I2C_MST_GLB_CTRL);\n\tv |= BIT(i2c->sda_num);\n\twritel(v, i2c->base + RTL9300_I2C_MST_GLB_CTRL);\n}\n\nstatic void rtl9310_i2c_config_io(struct rtl9300_i2c *i2c, int scl_num, int sda_num)\n{\n\tu32 v;\n\n\t// Set SCL pin\n\tREG_MASK(i2c, 0, BIT(RTL9310_I2C_MST_IF_SEL_GPIO_SCL_SEL + scl_num), RTL9310_I2C_MST_IF_SEL);\n\n\t// Set SDA pin\n\tREG_MASK(i2c, 0x7 << RTL9310_I2C_CTRL_SDA_OUT_SEL,\n\t\t i2c->sda_num << RTL9310_I2C_CTRL_SDA_OUT_SEL, RTL9310_I2C_CTRL);\n\n\t// Set SDA pin to I2C functionality\n\tv = readl(i2c->base + RTL9310_I2C_MST_IF_SEL);\n\tv |= BIT(i2c->sda_num);\n\twritel(v, i2c->base + RTL9310_I2C_MST_IF_SEL);\n}\n\nstatic int rtl9300_i2c_config_xfer(struct rtl9300_i2c *i2c, u16 addr, u16 len)\n{\n\t// Set bus frequency\n\tREG_MASK(i2c, 0x3 << RTL9300_I2C_CTRL2_SCL_FREQ,\n\t\t i2c->bus_freq << RTL9300_I2C_CTRL2_SCL_FREQ, RTL9300_I2C_CTRL2);\n\n\t// Set slave device address\n\tREG_MASK(i2c, 0x7f << RTL9300_I2C_CTRL2_DEV_ADDR,\n\t\t addr << RTL9300_I2C_CTRL2_DEV_ADDR, RTL9300_I2C_CTRL2);\n\n\t// Set data length\n\tREG_MASK(i2c, 0xf << RTL9300_I2C_CTRL2_DATA_WIDTH,\n\t\t ((len - 1) & 0xf) << RTL9300_I2C_CTRL2_DATA_WIDTH, RTL9300_I2C_CTRL2);\n\n\t// Set read mode to random\n\tREG_MASK(i2c, 0x1 << RTL9300_I2C_CTRL2_READ_MODE, 0, RTL9300_I2C_CTRL2);\n\n\treturn 0;\n}\n\nstatic int rtl9310_i2c_config_xfer(struct rtl9300_i2c *i2c, u16 addr, u16 len)\n{\n\t// Set bus frequency\n\tREG_MASK(i2c, 0x3 << RTL9310_I2C_CTRL_SCL_FREQ,\n\t\t i2c->bus_freq << RTL9310_I2C_CTRL_SCL_FREQ, RTL9310_I2C_CTRL);\n\n\t// Set slave device address\n\tREG_MASK(i2c, 0x7f << RTL9310_I2C_CTRL_DEV_ADDR,\n\t\t addr << RTL9310_I2C_CTRL_DEV_ADDR, RTL9310_I2C_CTRL);\n\n\t// Set data length\n\tREG_MASK(i2c, 0xf << RTL9310_I2C_CTRL_DATA_WIDTH,\n\t\t ((len - 1) & 0xf) << RTL9310_I2C_CTRL_DATA_WIDTH, RTL9310_I2C_CTRL);\n\n\t// Set read mode to random\n\tREG_MASK(i2c, 0x1 << RTL9310_I2C_CTRL_READ_MODE, 0, RTL9310_I2C_CTRL);\n\n\treturn 0;\n}\n\nstatic int i2c_read(void __iomem *r0, u8 *buf, int len)\n{\n\tint i;\n\tu32 v;\n\n\tif (len > 16)\n\t\treturn -EIO;\n\n\tfor (i = 0; i < len; i++) {\n\t\tif (i % 4 == 0)\n\t\t\tv = readl(r0 + i);\n\t\tbuf[i] = v;\n\t\tv >>= 8;\n\t}\n\n\treturn len;\n}\n\nstatic int i2c_write(void __iomem *r0, u8 *buf, int len)\n{\n\tu32 v;\n\tint i;\n\n\tif (len > 16)\n\t\treturn -EIO;\n\n\tfor (i = 0; i < len; i++) {\n\t\tif (! (i % 4))\n\t\t\tv = 0;\n\t\tv <<= 8;\n\t\tv |= buf[i];\n\t\tif (i % 4 == 3 || i == len - 1)\n\t\t\twritel(v, r0 + (i / 4) * 4);\n\t}\n\n\treturn len;\n}\n\nstatic int rtl9300_i2c_read(struct rtl9300_i2c *i2c, u8 *buf, int len)\n{\n\treturn i2c_read(REG(i2c, RTL9300_I2C_DATA_WORD0), buf, len);\n}\n\nstatic int rtl9300_i2c_write(struct rtl9300_i2c *i2c, u8 *buf, int len)\n{\n\treturn i2c_write(REG(i2c, RTL9300_I2C_DATA_WORD0), buf, len);\n}\n\nstatic int rtl9310_i2c_read(struct rtl9300_i2c *i2c, u8 *buf, int len)\n{\n\treturn i2c_read(REG(i2c, RTL9310_I2C_DATA), buf, len);\n}\n\nstatic int rtl9310_i2c_write(struct rtl9300_i2c *i2c, u8 *buf, int len)\n{\n\treturn i2c_write(REG(i2c, RTL9310_I2C_DATA), buf, len);\n}\n\nstatic void rtl9300_writel(struct rtl9300_i2c *i2c, u32 data)\n{\n\twritel(data, REG(i2c, RTL9300_I2C_DATA_WORD0));\n}\n\nstatic void rtl9310_writel(struct rtl9300_i2c *i2c, u32 data)\n{\n\twritel(data, REG(i2c, RTL9310_I2C_DATA));\n}\n\n\nstatic int rtl9300_execute_xfer(struct rtl9300_i2c *i2c, char read_write,\n\t\t\t\tint size, union i2c_smbus_data * data, int len)\n{\n\tu32 v;\n\n\tif (read_write == I2C_SMBUS_READ)\n\t\tREG_MASK(i2c, BIT(RTL9300_I2C_CTRL1_RWOP), 0, RTL9300_I2C_CTRL1);\n\telse\n\t\tREG_MASK(i2c, 0, BIT(RTL9300_I2C_CTRL1_RWOP), RTL9300_I2C_CTRL1);\n\n\tREG_MASK(i2c, 0, BIT(RTL9300_I2C_CTRL1_I2C_TRIG), RTL9300_I2C_CTRL1);\n\tdo {\n\t\tv = readl(REG(i2c, RTL9300_I2C_CTRL1));\n\t} while (v & BIT(RTL9300_I2C_CTRL1_I2C_TRIG));\n\n\tif (v & BIT(RTL9300_I2C_CTRL1_I2C_FAIL))\n\t\treturn -EIO;\n\n\tif (read_write == I2C_SMBUS_READ) {\n\t\tif (size == I2C_SMBUS_BYTE || size == I2C_SMBUS_BYTE_DATA){\n\t\t\tdata->byte = readl(REG(i2c, RTL9300_I2C_DATA_WORD0));\n\t\t} else if (size == I2C_SMBUS_WORD_DATA) {\n\t\t\tdata->word = readl(REG(i2c, RTL9300_I2C_DATA_WORD0));\n\t\t} else if (len > 0) {\n\t\t\trtl9300_i2c_read(i2c, &data->block[0], len);\n\t\t}\n\t}\n\n\treturn 0;\n}\n\nstatic int rtl9310_execute_xfer(struct rtl9300_i2c *i2c, char read_write,\n\t\t\t\tint size, union i2c_smbus_data * data, int len)\n{\n\tu32 v;\n\n\tif (read_write == I2C_SMBUS_READ)\n\t\tREG_MASK(i2c, BIT(RTL9310_I2C_CTRL_RWOP), 0, RTL9310_I2C_CTRL);\n\telse\n\t\tREG_MASK(i2c, 0, BIT(RTL9310_I2C_CTRL_RWOP), RTL9310_I2C_CTRL);\n\n\tREG_MASK(i2c, 0, BIT(RTL9310_I2C_CTRL_I2C_TRIG), RTL9310_I2C_CTRL);\n\tdo {\n\t\tv = readl(REG(i2c, RTL9310_I2C_CTRL));\n\t} while (v & BIT(RTL9310_I2C_CTRL_I2C_TRIG));\n\n\tif (v & BIT(RTL9310_I2C_CTRL_I2C_FAIL))\n\t\treturn -EIO;\n\n\tif (read_write == I2C_SMBUS_READ) {\n\t\tif (size == I2C_SMBUS_BYTE || size == I2C_SMBUS_BYTE_DATA){\n\t\t\tdata->byte = readl(REG(i2c, RTL9310_I2C_DATA));\n\t\t} else if (size == I2C_SMBUS_WORD_DATA) {\n\t\t\tdata->word = readl(REG(i2c, RTL9310_I2C_DATA));\n\t\t} else if (len > 0) {\n\t\t\trtl9310_i2c_read(i2c, &data->block[0], len);\n\t\t}\n\t}\n\n\treturn 0;\n}\n\nstatic int rtl9300_i2c_smbus_xfer(struct i2c_adapter * adap, u16 addr,\n\t\t  unsigned short flags, char read_write,\n\t\t  u8 command, int size, union i2c_smbus_data * data)\n{\n\tstruct rtl9300_i2c *i2c = i2c_get_adapdata(adap);\n\tstruct i2c_drv_data *drv_data = (struct i2c_drv_data *)device_get_match_data(i2c->dev);\n\tint len = 0, ret;\n\n\tmutex_lock(&i2c_lock);\n\tswitch (size) {\n\tcase I2C_SMBUS_QUICK:\n\t\tdrv_data->config_xfer(i2c, addr, 0);\n\t\tdrv_data->reg_addr_set(i2c, 0, 0);\n\t\tbreak;\n\n\tcase I2C_SMBUS_BYTE:\n\t\tif (read_write == I2C_SMBUS_WRITE) {\n\t\t\tdrv_data->config_xfer(i2c, addr, 0);\n\t\t\tdrv_data->reg_addr_set(i2c, command, 1);\n\t\t} else {\n\t\t\tdrv_data->config_xfer(i2c, addr, 1);\n\t\t\tdrv_data->reg_addr_set(i2c, 0, 0);\n\t\t}\n\t\tbreak;\n\n\tcase I2C_SMBUS_BYTE_DATA:\n\t\tpr_debug(\"I2C_SMBUS_BYTE_DATA %02x, read %d cmd %02x\\n\", addr, read_write, command);\n\t\tdrv_data->reg_addr_set(i2c, command, 1);\n\t\tdrv_data->config_xfer(i2c, addr, 1);\n\n\t\tif (read_write == I2C_SMBUS_WRITE) {\n\t\t\tpr_debug(\"--> data %02x\\n\", data->byte);\n\t\t\tdrv_data->writel(i2c, data->byte);\n\t\t}\n\t\tbreak;\n\n\tcase I2C_SMBUS_WORD_DATA:\n\t\tpr_debug(\"I2C_SMBUS_WORD %02x, read %d\\n\", addr, read_write);\n\t\tdrv_data->reg_addr_set(i2c, command, 1);\n\t\tdrv_data->config_xfer(i2c, addr, 2);\n\t\tif (read_write == I2C_SMBUS_WRITE)\n\t\t\tdrv_data->writel(i2c, data->word);\n\t\tbreak;\n\n\tcase I2C_SMBUS_BLOCK_DATA:\n\t\tpr_debug(\"I2C_SMBUS_BLOCK_DATA %02x, read %d, len %d\\n\",\n\t\t\taddr, read_write, data->block[0]);\n\t\tdrv_data->reg_addr_set(i2c, command, 1);\n\t\tdrv_data->config_xfer(i2c, addr, data->block[0]);\n\t\tif (read_write == I2C_SMBUS_WRITE)\n\t\t\tdrv_data->write(i2c, &data->block[1], data->block[0]);\n\t\tlen = data->block[0];\n\t\tbreak;\n\n\tdefault:\n\t\tdev_warn(&adap->dev, \"Unsupported transaction %d\\n\", size);\n\t\treturn -EOPNOTSUPP;\n\t}\n\n\tret = drv_data->execute_xfer(i2c, read_write, size, data, len);\n\n\tmutex_unlock(&i2c_lock);\n\n\treturn ret;\n}\n\nstatic u32 rtl9300_i2c_func(struct i2c_adapter *a)\n{\n\treturn I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |\n\t       I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |\n\t       I2C_FUNC_SMBUS_BLOCK_DATA;\n}\n\nstatic const struct i2c_algorithm rtl9300_i2c_algo = {\n\t.smbus_xfer\t= rtl9300_i2c_smbus_xfer,\n\t.functionality\t= rtl9300_i2c_func,\n};\n\nstruct i2c_adapter_quirks rtl9300_i2c_quirks = {\n\t.flags\t\t= I2C_AQ_NO_CLK_STRETCH,\n\t.max_read_len\t= 16,\n\t.max_write_len\t= 16,\n};\n\nstatic int rtl9300_i2c_probe(struct platform_device *pdev)\n{\n\tstruct resource *res;\n\tstruct rtl9300_i2c *i2c;\n\tstruct i2c_adapter *adap;\n\tstruct i2c_drv_data *drv_data;\n\tstruct device_node *node = pdev->dev.of_node;\n\tu32 clock_freq, pin;\n\tint ret = 0;\n\n\tpr_info(\"%s probing I2C adapter\\n\", __func__);\n\t\n\tif (!node) {\n\t\tdev_err(i2c->dev, \"No DT found\\n\");\n\t\treturn -EINVAL;\n\t}\n\n\tres = platform_get_resource(pdev, IORESOURCE_MEM, 0);\n\n\tdrv_data = (struct i2c_drv_data *) device_get_match_data(&pdev->dev);\n\n\ti2c = devm_kzalloc(&pdev->dev, sizeof(struct rtl9300_i2c), GFP_KERNEL);\n\tif (!i2c)\n\t\treturn -ENOMEM;\n\n\ti2c->base = devm_ioremap_resource(&pdev->dev, res);\n\ti2c->mst2_offset = drv_data->mst2_offset;\n\tif (IS_ERR(i2c->base))\n\t\treturn PTR_ERR(i2c->base);\n\n\tpr_debug(\"%s base memory %08x\\n\", __func__, (u32)i2c->base);\n\ti2c->dev = &pdev->dev;\n\n\tif (of_property_read_u32(node, \"clock-frequency\", &clock_freq)) {\n\t\tclock_freq = I2C_MAX_STANDARD_MODE_FREQ;\n\t}\n\tswitch(clock_freq) {\n\tcase I2C_MAX_STANDARD_MODE_FREQ:\n\t\ti2c->bus_freq = RTL9300_I2C_STD_FREQ;\n\t\tbreak;\n\t\n\tcase I2C_MAX_FAST_MODE_FREQ:\n\t\ti2c->bus_freq = RTL9300_I2C_FAST_FREQ;\n\t\tbreak;\n\tdefault:\n\t\tdev_warn(i2c->dev, \"clock-frequency %d not supported\\n\", clock_freq);\n\t\treturn -EINVAL;\n\t}\n\n\tdev_info(&pdev->dev, \"SCL speed %d, mode is %d\\n\", clock_freq, i2c->bus_freq);\n\n\tif (of_property_read_u32(node, \"scl-pin\", &pin)) {\n\t\tdev_warn(i2c->dev, \"SCL pin not found in DT, using default\\n\");\n\t\tpin = drv_data->scl0_pin;\n\t}\n\tif (!(pin == drv_data->scl0_pin || pin == drv_data->scl1_pin)) {\n\t\tdev_warn(i2c->dev, \"SCL pin %d not supported\\n\", pin);\n\t\treturn -EINVAL;\n\t}\n\ti2c->scl_num = pin == drv_data->scl0_pin ? 0 : 1;\n\tpr_info(\"%s scl_num %d\\n\", __func__, i2c->scl_num);\n\n\tif (of_property_read_u32(node, \"sda-pin\", &pin)) {\n\t\tdev_warn(i2c->dev, \"SDA pin not found in DT, using default \\n\");\n\t\tpin = drv_data->sda0_pin;\n\t}\n\ti2c->sda_num = pin - drv_data->sda0_pin;\n\tif (i2c->sda_num < 0 || i2c->sda_num > 7) {\n\t\tdev_warn(i2c->dev, \"SDA pin %d not supported\\n\", pin);\n\t\treturn -EINVAL;\n\t}\n\tpr_info(\"%s sda_num %d\\n\", __func__, i2c->sda_num);\n\n\tadap = &i2c->adap;\n\tadap->owner = THIS_MODULE;\n\tadap->algo = &rtl9300_i2c_algo;\n\tadap->retries = 3;\n\tadap->dev.parent = &pdev->dev;\n\ti2c_set_adapdata(adap, i2c);\n\tadap->dev.of_node = node;\n\tstrlcpy(adap->name, dev_name(&pdev->dev), sizeof(adap->name));\n\n\tplatform_set_drvdata(pdev, i2c);\n\n\tdrv_data->config_io(i2c, i2c->scl_num, i2c->sda_num);\n\n\tret = i2c_add_adapter(adap);\n\n\treturn ret;\n}\n\nstatic int rtl9300_i2c_remove(struct platform_device *pdev)\n{\n\tstruct rtl9300_i2c *i2c = platform_get_drvdata(pdev);\n\n\ti2c_del_adapter(&i2c->adap);\n\n\treturn 0;\n}\n\nstruct i2c_drv_data rtl9300_i2c_drv_data = {\n\t.scl0_pin = 8,\n\t.scl1_pin = 17,\n\t.sda0_pin = 9,\n\t.read = rtl9300_i2c_read,\n\t.read = rtl9300_i2c_write,\n\t.reg_addr_set = rtl9300_i2c_reg_addr_set,\n\t.config_xfer = rtl9300_i2c_config_xfer,\n\t.execute_xfer = rtl9300_execute_xfer,\n\t.writel = rtl9300_writel,\n\t.config_io = rtl9300_i2c_config_io,\n\t.mst2_offset = 0x1c,\n};\n\nstruct i2c_drv_data rtl9310_i2c_drv_data = {\n\t.scl0_pin = 13, \n\t.scl1_pin = 14,\n\t.sda0_pin = 0,\n\t.read = rtl9310_i2c_read,\n\t.read = rtl9310_i2c_write,\n\t.reg_addr_set = rtl9310_i2c_reg_addr_set,\n\t.config_xfer = rtl9310_i2c_config_xfer,\n\t.execute_xfer = rtl9310_execute_xfer,\n\t.writel = rtl9310_writel,\n\t.config_io = rtl9310_i2c_config_io,\n\t.mst2_offset = 0x18,\n};\n\nstatic const struct of_device_id i2c_rtl9300_dt_ids[] = {\n\t{ .compatible = \"realtek,rtl9300-i2c\", .data = (void *) &rtl9300_i2c_drv_data },\n\t{ .compatible = \"realtek,rtl9310-i2c\", .data = (void *) &rtl9310_i2c_drv_data },\n\t{ /* sentinel */ }\n};\nMODULE_DEVICE_TABLE(of, rtl838x_eth_of_ids);\n\nstatic struct platform_driver rtl9300_i2c_driver = {\n\t.probe\t\t= rtl9300_i2c_probe,\n\t.remove\t\t= rtl9300_i2c_remove,\n\t.driver\t\t= {\n\t\t.name\t= \"i2c-rtl9300\",\n\t\t.pm \t= NULL,\n\t\t.of_match_table = i2c_rtl9300_dt_ids,\n\t},\n};\n\nmodule_platform_driver(rtl9300_i2c_driver);\n\nMODULE_AUTHOR(\"Birger Koblitz\");\nMODULE_DESCRIPTION(\"RTL9300 I2C host driver\");\nMODULE_LICENSE(\"GPL v2\");\n"
  },
  {
    "path": "target/linux/realtek/files-5.10/drivers/i2c/busses/i2c-rtl9300.h",
    "content": "#ifndef I2C_RTL9300_H\n#define I2C_RTL9300_H\n\n#include <linux/i2c.h>\n\n#define RTL9300_I2C_CTRL1\t\t\t0x00\n#define RTL9300_I2C_CTRL1_MEM_ADDR\t\t8\n#define RTL9300_I2C_CTRL1_SDA_OUT_SEL\t\t4\n#define RTL9300_I2C_CTRL1_GPIO8_SCL_SEL\t\t3\n#define RTL9300_I2C_CTRL1_RWOP\t\t\t2\n#define RTL9300_I2C_CTRL1_I2C_FAIL\t\t1\n#define RTL9300_I2C_CTRL1_I2C_TRIG\t\t0\n\n#define RTL9300_I2C_CTRL2\t\t\t0x04\n#define RTL9300_I2C_CTRL2_DRIVE_ACK_DELAY\t20\n#define RTL9300_I2C_CTRL2_CHECK_ACK_DELAY\t16\n#define RTL9300_I2C_CTRL2_READ_MODE\t\t15\n#define RTL9300_I2C_CTRL2_DEV_ADDR\t\t8\n#define RTL9300_I2C_CTRL2_DATA_WIDTH\t\t4\n#define RTL9300_I2C_CTRL2_MADDR_WIDTH\t\t2\n#define RTL9300_I2C_CTRL2_SCL_FREQ\t\t0\n\n#define RTL9300_I2C_DATA_WORD0\t\t\t0x08\n\n#define RTL9300_I2C_MST_GLB_CTRL\t\t0x18\n\n#define RTL9310_I2C_MST_IF_CTRL\t\t\t0x00\n\n#define RTL9310_I2C_MST_IF_SEL\t\t\t0x04\n#define RTL9310_I2C_MST_IF_SEL_GPIO_SCL_SEL\t12\n\n#define RTL9310_I2C_CTRL\t\t\t0x08\n#define RTL9310_I2C_CTRL_SCL_FREQ\t\t30\n#define RTL9310_I2C_CTRL_CHECK_ACK_DELAY\t26\n#define RTL9310_I2C_CTRL_DRIVE_ACK_DELAY\t22\n#define RTL9310_I2C_CTRL_SDA_OUT_SEL\t\t18\n#define RTL9310_I2C_CTRL_DEV_ADDR\t\t11\n#define RTL9310_I2C_CTRL_MADDR_WIDTH\t\t9\n#define RTL9310_I2C_CTRL_DATA_WIDTH\t\t5\n#define RTL9310_I2C_CTRL_READ_MODE\t\t4\n#define RTL9310_I2C_CTRL_RWOP\t\t\t2\n#define RTL9310_I2C_CTRL_I2C_FAIL\t\t1\n#define RTL9310_I2C_CTRL_I2C_TRIG\t\t0\n\n#define RTL9310_I2C_MEMADDR\t\t\t0x0c\n\n#define RTL9310_I2C_DATA\t\t\t0x10\n\n#define RTL9300_I2C_STD_FREQ\t\t0\n#define RTL9300_I2C_FAST_FREQ\t\t1\n\nstruct rtl9300_i2c {\n\tvoid __iomem *base;\n\tu32 mst2_offset;\n\tstruct device *dev;\n\tstruct i2c_adapter adap;\n\tu8 bus_freq;\n\tu8 sda_num;\t\t\t// SDA channel number\n\tu8 scl_num;\t\t\t// SCL channel, mapping to master 1 or 2\n};\n\n#endif\n"
  },
  {
    "path": "target/linux/realtek/files-5.10/drivers/i2c/muxes/i2c-mux-rtl9300.c",
    "content": "// SPDX-License-Identifier: GPL-2.0-only\n/*\n * I2C multiplexer for the 2 I2C Masters of the RTL9300\n * with up to 8 channels each, but which are not entirely\n * independent of each other\n */\n#include <linux/i2c-mux.h>\n#include <linux/module.h>\n#include <linux/mux/consumer.h>\n#include <linux/of_device.h>\n#include <linux/of_address.h>\n#include <linux/platform_device.h>\n\n#include \"../busses/i2c-rtl9300.h\"\n\n#define NUM_MASTERS\t\t2\n#define NUM_BUSSES\t\t8\n\n#define REG(mst, x)\t(mux->base + x + (mst ? mux->i2c->mst2_offset : 0))\n#define REG_MASK(mst, clear, set, reg)\t\\\n\t\t\twritel((readl(REG((mst),(reg))) & ~(clear)) | (set), REG((mst),(reg)))\n\nstruct channel {\n\tu8 sda_num;\n\tu8 scl_num;\n};\n\nstatic struct channel channels[NUM_MASTERS * NUM_BUSSES];\n\nstruct rtl9300_mux {\n\tvoid __iomem *base;\n\tstruct device *dev;\n\tstruct i2c_adapter *parent;\n\tstruct rtl9300_i2c * i2c;\n};\n\nstruct i2c_mux_data  {\n\tint scl0_pin;\n\tint scl1_pin;\n\tint sda0_pin;\n\tint sda_pins;\n\tint (*i2c_mux_select)(struct i2c_mux_core *muxc, u32 chan);\n\tint (*i2c_mux_deselect)(struct i2c_mux_core *muxc, u32 chan);\n\tvoid (*sda_sel)(struct i2c_mux_core *muxc, int pin);\n};\n\nstatic int rtl9300_i2c_mux_select(struct i2c_mux_core *muxc, u32 chan)\n{\n\tstruct rtl9300_mux *mux = i2c_mux_priv(muxc);\n\n\t// Set SCL pin\n\tREG_MASK(channels[chan].scl_num, 0,\n\t\t BIT(RTL9300_I2C_CTRL1_GPIO8_SCL_SEL), RTL9300_I2C_CTRL1);\n\n\t// Set SDA pin\n\tREG_MASK(channels[chan].scl_num, 0x7 << RTL9300_I2C_CTRL1_SDA_OUT_SEL,\n\t\t channels[chan].sda_num << RTL9300_I2C_CTRL1_SDA_OUT_SEL, RTL9300_I2C_CTRL1);\n\n\tmux->i2c->sda_num = channels[chan].sda_num;\n\tmux->i2c->scl_num = channels[chan].scl_num;\n\n\treturn 0;\n}\n\nstatic int rtl9310_i2c_mux_select(struct i2c_mux_core *muxc, u32 chan)\n{\n\tstruct rtl9300_mux *mux = i2c_mux_priv(muxc);\n\n\t// Set SCL pin\n\tREG_MASK(0, 0, BIT(RTL9310_I2C_MST_IF_SEL_GPIO_SCL_SEL + channels[chan].scl_num),\n\t\t RTL9310_I2C_MST_IF_SEL);\n\n\t// Set SDA pin\n\tREG_MASK(channels[chan].scl_num, 0xf << RTL9310_I2C_CTRL_SDA_OUT_SEL,\n\t\t channels[chan].sda_num << RTL9310_I2C_CTRL_SDA_OUT_SEL, RTL9310_I2C_CTRL);\n\n\tmux->i2c->sda_num = channels[chan].sda_num;\n\tmux->i2c->scl_num = channels[chan].scl_num;\n\n\treturn 0;\n}\n\nstatic int rtl9300_i2c_mux_deselect(struct i2c_mux_core *muxc, u32 chan)\n{\n\treturn 0;\n}\n\nstatic void rtl9300_sda_sel(struct i2c_mux_core *muxc, int pin)\n{\n\tstruct rtl9300_mux *mux = i2c_mux_priv(muxc);\n\tu32 v;\n\n\t// Set SDA pin to I2C functionality\n\tv = readl(REG(0, RTL9300_I2C_MST_GLB_CTRL));\n\tv |= BIT(pin);\n\twritel(v, REG(0, RTL9300_I2C_MST_GLB_CTRL));\n}\n\nstatic void rtl9310_sda_sel(struct i2c_mux_core *muxc, int pin)\n{\n\tstruct rtl9300_mux *mux = i2c_mux_priv(muxc);\n\tu32 v;\n\n\t// Set SDA pin to I2C functionality\n\tv = readl(REG(0, RTL9310_I2C_MST_IF_SEL));\n\tv |= BIT(pin);\n\twritel(v, REG(0, RTL9310_I2C_MST_IF_SEL));\n}\n\nstatic struct device_node *mux_parent_adapter(struct device *dev, struct rtl9300_mux *mux)\n{\n\tstruct device_node *node = dev->of_node;\n\tstruct device_node *parent_np;\n\tstruct i2c_adapter *parent;\n\n\tparent_np = of_parse_phandle(node, \"i2c-parent\", 0);\n\tif (!parent_np) {\n\t\tdev_err(dev, \"Cannot parse i2c-parent\\n\");\n\t\treturn ERR_PTR(-ENODEV);\n\t}\n\tparent = of_find_i2c_adapter_by_node(parent_np);\n\tof_node_put(parent_np);\n\tif (!parent)\n\t\treturn ERR_PTR(-EPROBE_DEFER);\n\n\tif (!(of_device_is_compatible(parent_np, \"realtek,rtl9300-i2c\")\n\t\t|| of_device_is_compatible(parent_np, \"realtek,rtl9310-i2c\"))){\n\t\tdev_err(dev, \"I2C parent not an RTL9300 I2C controller\\n\");\n\t\treturn ERR_PTR(-ENODEV);\n\t}\n\n\tmux->parent = parent;\n\tmux->i2c = (struct rtl9300_i2c *)i2c_get_adapdata(parent);\n\tmux->base = mux->i2c->base;\n\n\treturn parent_np;\n}\n\nstruct i2c_mux_data rtl9300_i2c_mux_data = {\n\t.scl0_pin = 8,\n\t.scl1_pin = 17,\n\t.sda0_pin = 9,\n\t.sda_pins = 8,\n\t.i2c_mux_select = rtl9300_i2c_mux_select,\n\t.i2c_mux_deselect = rtl9300_i2c_mux_deselect,\n\t.sda_sel = rtl9300_sda_sel,\n};\n\nstruct i2c_mux_data rtl9310_i2c_mux_data = {\n\t.scl0_pin = 13, \n\t.scl1_pin = 14,\n\t.sda0_pin = 0,\n\t.sda_pins = 16,\n\t.i2c_mux_select = rtl9310_i2c_mux_select,\n\t.i2c_mux_deselect = rtl9300_i2c_mux_deselect,\n\t.sda_sel = rtl9310_sda_sel,\n};\n\nstatic const struct of_device_id rtl9300_i2c_mux_of_match[] = {\n\t{ .compatible = \"realtek,i2c-mux-rtl9300\", .data = (void *) &rtl9300_i2c_mux_data},\n\t{ .compatible = \"realtek,i2c-mux-rtl9310\", .data = (void *) &rtl9310_i2c_mux_data},\n\t{},\n};\n\nMODULE_DEVICE_TABLE(of, rtl9300_i2c_mux_of_match);\n\nstatic int rtl9300_i2c_mux_probe(struct platform_device *pdev)\n{\n\tstruct device *dev = &pdev->dev;\n\tstruct device_node *node = dev->of_node;\n\tstruct device_node *parent_np;\n\tstruct device_node *child;\n\tstruct i2c_mux_core *muxc;\n\tstruct rtl9300_mux *mux;\n\tstruct i2c_mux_data *mux_data;\n\tint children;\n\tint ret;\n\n\tpr_info(\"%s probing I2C adapter\\n\", __func__);\n\t\n\tif (!node) {\n\t\tdev_err(dev, \"No DT found\\n\");\n\t\treturn -EINVAL;\n\t}\n\n\tmux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);\n\tif (!mux)\n\t\treturn -ENOMEM;\n\n\tmux->dev = dev;\n\n\tmux_data = (struct i2c_mux_data *) device_get_match_data(dev);\n\n\tparent_np = mux_parent_adapter(dev, mux);\n\tif (IS_ERR(parent_np))\n\t\treturn dev_err_probe(dev, PTR_ERR(parent_np), \"i2c-parent adapter not found\\n\");\n\n\tpr_info(\"%s base memory %08x\\n\", __func__, (u32)mux->base);\n\n\tchildren = of_get_child_count(node);\n\n\tmuxc = i2c_mux_alloc(mux->parent, dev, children, 0, 0,\n\t\t\t     mux_data->i2c_mux_select, mux_data->i2c_mux_deselect);\n\tif (!muxc) {\n\t\tret = -ENOMEM;\n\t\tgoto err_parent;\n\t}\n\tmuxc->priv = mux;\n\n\tplatform_set_drvdata(pdev, muxc);\n\n\tfor_each_child_of_node(node, child) {\n\t\tu32 chan;\n\t\tu32 pin;\n\n\t\tret = of_property_read_u32(child, \"reg\", &chan);\n\t\tif (ret < 0) {\n\t\t\tdev_err(dev, \"no reg property for node '%pOFn'\\n\",\n\t\t\t\tchild);\n\t\t\tgoto err_children;\n\t\t}\n\n\t\tif (chan >= NUM_MASTERS * NUM_BUSSES) {\n\t\t\tdev_err(dev, \"invalid reg %u\\n\", chan);\n\t\t\tret = -EINVAL;\n\t\t\tgoto err_children;\n\t\t}\n\n\t\tif (of_property_read_u32(child, \"scl-pin\", &pin)) {\n\t\t\tdev_warn(dev, \"SCL pin not found in DT, using default\\n\");\n\t\t\tpin = mux_data->scl0_pin;\n\t\t}\n\t\tif (!(pin == mux_data->scl0_pin || pin == mux_data->scl1_pin)) {\n\t\t\tdev_warn(dev, \"SCL pin %d not supported\\n\", pin);\n\t\t\tret = -EINVAL;\n\t\t\tgoto err_children;\n\t\t}\n\t\tchannels[chan].scl_num = pin == mux_data->scl0_pin ? 0 : 1;\n\t\tpr_info(\"%s channel %d scl_num %d\\n\", __func__, chan, channels[chan].scl_num);\n\n\t\tif (of_property_read_u32(child, \"sda-pin\", &pin)) {\n\t\t\tdev_warn(dev, \"SDA pin not found in DT, using default \\n\");\n\t\t\tpin = mux_data->sda0_pin;\n\t\t}\n\t\tchannels[chan].sda_num = pin - mux_data->sda0_pin;\n\t\tif (channels[chan].sda_num < 0 || channels[chan].sda_num >= mux_data->sda_pins) {\n\t\t\tdev_warn(dev, \"SDA pin %d not supported\\n\", pin);\n\t\t\treturn -EINVAL;\n\t\t}\n\t\tpr_info(\"%s channel %d sda_num %d\\n\", __func__, chan, channels[chan].sda_num);\n\n\t\tmux_data->sda_sel(muxc, channels[chan].sda_num);\n\n\t\tret = i2c_mux_add_adapter(muxc, 0, chan, 0);\n\t\tif (ret)\n\t\t\tgoto err_children;\n\t}\n\n\tdev_info(dev, \"%d-port mux on %s adapter\\n\", children, mux->parent->name);\n\n\treturn 0;\n\nerr_children:\n\ti2c_mux_del_adapters(muxc);\nerr_parent:\n\ti2c_put_adapter(mux->parent);\n\n\treturn ret;\n}\n\nstatic int rtl9300_i2c_mux_remove(struct platform_device *pdev)\n{\n\tstruct i2c_mux_core *muxc = platform_get_drvdata(pdev);\n\n\ti2c_mux_del_adapters(muxc);\n\ti2c_put_adapter(muxc->parent);\n\n\treturn 0;\n}\n\nstatic struct platform_driver i2c_mux_driver = {\n\t.probe\t= rtl9300_i2c_mux_probe,\n\t.remove\t= rtl9300_i2c_mux_remove,\n\t.driver\t= {\n\t\t.name\t= \"i2c-mux-rtl9300\",\n\t\t.of_match_table = rtl9300_i2c_mux_of_match,\n\t},\n};\nmodule_platform_driver(i2c_mux_driver);\n\nMODULE_DESCRIPTION(\"RTL9300 I2C multiplexer driver\");\nMODULE_AUTHOR(\"Birger Koblitz\");\nMODULE_LICENSE(\"GPL v2\");\n"
  },
  {
    "path": "target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/Kconfig",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\nconfig NET_DSA_RTL83XX\n\ttristate \"Realtek RTL838x/RTL839x switch support\"\n\tdepends on RTL83XX\n\tselect NET_DSA_TAG_TRAILER\n\thelp\n\t  This driver adds support for Realtek RTL83xx series switching.\n\n"
  },
  {
    "path": "target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/Makefile",
    "content": "# SPDX-License-Identifier: GPL-2.0\nobj-$(CONFIG_NET_DSA_RTL83XX)\t+= common.o dsa.o \\\n\trtl838x.o rtl839x.o rtl930x.o rtl931x.o debugfs.o qos.o tc.o\n"
  },
  {
    "path": "target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/common.c",
    "content": "// SPDX-License-Identifier: GPL-2.0-only\n\n#include <linux/of_mdio.h>\n#include <linux/of_platform.h>\n#include <net/arp.h>\n#include <net/nexthop.h>\n#include <net/neighbour.h>\n#include <net/netevent.h>\n#include <linux/inetdevice.h>\n#include <linux/rhashtable.h>\n#include <linux/of_net.h>\n\n#include <asm/mach-rtl838x/mach-rtl83xx.h>\n#include \"rtl83xx.h\"\n\nextern struct rtl83xx_soc_info soc_info;\n\nextern const struct rtl838x_reg rtl838x_reg;\nextern const struct rtl838x_reg rtl839x_reg;\nextern const struct rtl838x_reg rtl930x_reg;\nextern const struct rtl838x_reg rtl931x_reg;\n\nextern const struct dsa_switch_ops rtl83xx_switch_ops;\nextern const struct dsa_switch_ops rtl930x_switch_ops;\n\nDEFINE_MUTEX(smi_lock);\n\nint rtl83xx_port_get_stp_state(struct rtl838x_switch_priv *priv, int port)\n{\n\tu32 msti = 0;\n\tu32 port_state[4];\n\tint index, bit;\n\tint pos = port;\n\tint n = priv->port_width << 1;\n\n\t/* Ports above or equal CPU port can never be configured */\n\tif (port >= priv->cpu_port)\n\t\treturn -1;\n\n\tmutex_lock(&priv->reg_mutex);\n\n\t/* For the RTL839x and following, the bits are left-aligned in the 64/128 bit field */\n\tif (priv->family_id == RTL8390_FAMILY_ID)\n\t\tpos += 12;\n\tif (priv->family_id == RTL9300_FAMILY_ID)\n\t\tpos += 3;\n\tif (priv->family_id == RTL9310_FAMILY_ID)\n\t\tpos += 8;\n\n\tindex = n - (pos >> 4) - 1;\n\tbit = (pos << 1) % 32;\n\n\tpriv->r->stp_get(priv, msti, port_state);\n\n\tmutex_unlock(&priv->reg_mutex);\n\n\treturn (port_state[index] >> bit) & 3;\n}\n\nstatic struct table_reg rtl838x_tbl_regs[] = {\n\tTBL_DESC(0x6900, 0x6908, 3, 15, 13, 1),\t\t// RTL8380_TBL_L2\n\tTBL_DESC(0x6914, 0x6918, 18, 14, 12, 1),\t// RTL8380_TBL_0\n\tTBL_DESC(0xA4C8, 0xA4CC, 6, 14, 12, 1),\t\t// RTL8380_TBL_1\n\n\tTBL_DESC(0x1180, 0x1184, 3, 16, 14, 0),\t\t// RTL8390_TBL_L2\n\tTBL_DESC(0x1190, 0x1194, 17, 15, 12, 0),\t// RTL8390_TBL_0\n\tTBL_DESC(0x6B80, 0x6B84, 4, 14, 12, 0),\t\t// RTL8390_TBL_1\n\tTBL_DESC(0x611C, 0x6120, 9, 8, 6, 0),\t\t// RTL8390_TBL_2\n\n\tTBL_DESC(0xB320, 0xB334, 3, 18, 16, 0),\t\t// RTL9300_TBL_L2\n\tTBL_DESC(0xB340, 0xB344, 19, 16, 12, 0),\t// RTL9300_TBL_0\n\tTBL_DESC(0xB3A0, 0xB3A4, 20, 16, 13, 0),\t// RTL9300_TBL_1\n\tTBL_DESC(0xCE04, 0xCE08, 6, 14, 12, 0),\t\t// RTL9300_TBL_2\n\tTBL_DESC(0xD600, 0xD604, 30, 7, 6, 0),\t\t// RTL9300_TBL_HSB\n\tTBL_DESC(0x7880, 0x7884, 22, 9, 8, 0),\t\t// RTL9300_TBL_HSA\n\n\tTBL_DESC(0x8500, 0x8508, 8, 19, 15, 0),\t\t// RTL9310_TBL_0\n\tTBL_DESC(0x40C0, 0x40C4, 22, 16, 14, 0),\t// RTL9310_TBL_1\n\tTBL_DESC(0x8528, 0x852C, 6, 18, 14, 0),\t\t// RTL9310_TBL_2\n\tTBL_DESC(0x0200, 0x0204, 9, 15, 12, 0),\t\t// RTL9310_TBL_3\n\tTBL_DESC(0x20dc, 0x20e0, 29, 7, 6, 0),\t\t// RTL9310_TBL_4\n\tTBL_DESC(0x7e1c, 0x7e20, 53, 8, 6, 0),\t\t// RTL9310_TBL_5\n};\n\nvoid rtl_table_init(void)\n{\n\tint i;\n\n\tfor (i = 0; i < RTL_TBL_END; i++)\n\t\tmutex_init(&rtl838x_tbl_regs[i].lock);\n}\n\n/*\n * Request access to table t in table access register r\n * Returns a handle to a lock for that table\n */\nstruct table_reg *rtl_table_get(rtl838x_tbl_reg_t r, int t)\n{\n\tif (r >= RTL_TBL_END)\n\t\treturn NULL;\n\n\tif (t >= BIT(rtl838x_tbl_regs[r].c_bit-rtl838x_tbl_regs[r].t_bit))\n\t\treturn NULL;\n\n\tmutex_lock(&rtl838x_tbl_regs[r].lock);\n\trtl838x_tbl_regs[r].tbl = t;\n\n\treturn &rtl838x_tbl_regs[r];\n}\n\n/*\n * Release a table r, unlock the corresponding lock\n */\nvoid rtl_table_release(struct table_reg *r)\n{\n\tif (!r)\n\t\treturn;\n\n//\tpr_info(\"Unlocking %08x\\n\", (u32)r);\n\tmutex_unlock(&r->lock);\n//\tpr_info(\"Unlock done\\n\");\n}\n\n/*\n * Reads table index idx into the data registers of the table\n */\nvoid rtl_table_read(struct table_reg *r, int idx)\n{\n\tu32 cmd = r->rmode ? BIT(r->c_bit) : 0;\n\n\tcmd |= BIT(r->c_bit + 1) | (r->tbl << r->t_bit) | (idx & (BIT(r->t_bit) - 1));\n\tsw_w32(cmd, r->addr);\n\tdo { } while (sw_r32(r->addr) & BIT(r->c_bit + 1));\n}\n\n/*\n * Writes the content of the table data registers into the table at index idx\n */\nvoid rtl_table_write(struct table_reg *r, int idx)\n{\n\tu32 cmd = r->rmode ? 0 : BIT(r->c_bit);\n\n\tcmd |= BIT(r->c_bit + 1) | (r->tbl << r->t_bit) | (idx & (BIT(r->t_bit) - 1));\n\tsw_w32(cmd, r->addr);\n\tdo { } while (sw_r32(r->addr) & BIT(r->c_bit + 1));\n}\n\n/*\n * Returns the address of the ith data register of table register r\n * the address is relative to the beginning of the Switch-IO block at 0xbb000000\n */\ninline u16 rtl_table_data(struct table_reg *r, int i)\n{\n\tif (i >= r->max_data)\n\t\ti = r->max_data - 1;\n\treturn r->data + i * 4;\n}\n\ninline u32 rtl_table_data_r(struct table_reg *r, int i)\n{\n\treturn sw_r32(rtl_table_data(r, i));\n}\n\ninline void rtl_table_data_w(struct table_reg *r, u32 v, int i)\n{\n\tsw_w32(v, rtl_table_data(r, i));\n}\n\n/* Port register accessor functions for the RTL838x and RTL930X SoCs */\nvoid rtl838x_mask_port_reg(u64 clear, u64 set, int reg)\n{\n\tsw_w32_mask((u32)clear, (u32)set, reg);\n}\n\nvoid rtl838x_set_port_reg(u64 set, int reg)\n{\n\tsw_w32((u32)set, reg);\n}\n\nu64 rtl838x_get_port_reg(int reg)\n{\n\treturn ((u64) sw_r32(reg));\n}\n\n/* Port register accessor functions for the RTL839x and RTL931X SoCs */\nvoid rtl839x_mask_port_reg_be(u64 clear, u64 set, int reg)\n{\n\tsw_w32_mask((u32)(clear >> 32), (u32)(set >> 32), reg);\n\tsw_w32_mask((u32)(clear & 0xffffffff), (u32)(set & 0xffffffff), reg + 4);\n}\n\nu64 rtl839x_get_port_reg_be(int reg)\n{\n\tu64 v = sw_r32(reg);\n\n\tv <<= 32;\n\tv |= sw_r32(reg + 4);\n\treturn v;\n}\n\nvoid rtl839x_set_port_reg_be(u64 set, int reg)\n{\n\tsw_w32(set >> 32, reg);\n\tsw_w32(set & 0xffffffff, reg + 4);\n}\n\nvoid rtl839x_mask_port_reg_le(u64 clear, u64 set, int reg)\n{\n\tsw_w32_mask((u32)clear, (u32)set, reg);\n\tsw_w32_mask((u32)(clear >> 32), (u32)(set >> 32), reg + 4);\n}\n\nvoid rtl839x_set_port_reg_le(u64 set, int reg)\n{\n\tsw_w32(set, reg);\n\tsw_w32(set >> 32, reg + 4);\n}\n\nu64 rtl839x_get_port_reg_le(int reg)\n{\n\tu64 v = sw_r32(reg + 4);\n\n\tv <<= 32;\n\tv |= sw_r32(reg);\n\treturn v;\n}\n\nint read_phy(u32 port, u32 page, u32 reg, u32 *val)\n{\n\tswitch (soc_info.family) {\n\tcase RTL8380_FAMILY_ID:\n\t\treturn rtl838x_read_phy(port, page, reg, val);\n\tcase RTL8390_FAMILY_ID:\n\t\treturn rtl839x_read_phy(port, page, reg, val);\n\tcase RTL9300_FAMILY_ID:\n\t\treturn rtl930x_read_phy(port, page, reg, val);\n\tcase RTL9310_FAMILY_ID:\n\t\treturn rtl931x_read_phy(port, page, reg, val);\n\t}\n\treturn -1;\n}\n\nint write_phy(u32 port, u32 page, u32 reg, u32 val)\n{\n\tswitch (soc_info.family) {\n\tcase RTL8380_FAMILY_ID:\n\t\treturn rtl838x_write_phy(port, page, reg, val);\n\tcase RTL8390_FAMILY_ID:\n\t\treturn rtl839x_write_phy(port, page, reg, val);\n\tcase RTL9300_FAMILY_ID:\n\t\treturn rtl930x_write_phy(port, page, reg, val);\n\tcase RTL9310_FAMILY_ID:\n\t\treturn rtl931x_write_phy(port, page, reg, val);\n\t}\n\treturn -1;\n}\n\nstatic int __init rtl83xx_mdio_probe(struct rtl838x_switch_priv *priv)\n{\n\tstruct device *dev = priv->dev;\n\tstruct device_node *dn, *phy_node, *mii_np = dev->of_node;\n\tstruct mii_bus *bus;\n\tint ret;\n\tu32 pn;\n\n\tpr_debug(\"In %s\\n\", __func__);\n\tmii_np = of_find_compatible_node(NULL, NULL, \"realtek,rtl838x-mdio\");\n\tif (mii_np) {\n\t\tpr_debug(\"Found compatible MDIO node!\\n\");\n\t} else {\n\t\tdev_err(priv->dev, \"no %s child node found\", \"mdio-bus\");\n\t\treturn -ENODEV;\n\t}\n\n\tpriv->mii_bus = of_mdio_find_bus(mii_np);\n\tif (!priv->mii_bus) {\n\t\tpr_debug(\"Deferring probe of mdio bus\\n\");\n\t\treturn -EPROBE_DEFER;\n\t}\n\tif (!of_device_is_available(mii_np))\n\t\tret = -ENODEV;\n\n\tbus = devm_mdiobus_alloc(priv->ds->dev);\n\tif (!bus)\n\t\treturn -ENOMEM;\n\n\tbus->name = \"rtl838x slave mii\";\n\n\t/*\n\t * Since the NIC driver is loaded first, we can use the mdio rw functions\n\t * assigned there.\n\t */\n\tbus->read = priv->mii_bus->read;\n\tbus->write = priv->mii_bus->write;\n\tbus->read_paged = priv->mii_bus->read_paged;\n\tbus->write_paged = priv->mii_bus->write_paged;\n\tsnprintf(bus->id, MII_BUS_ID_SIZE, \"%s-%d\", bus->name, dev->id);\n\n\tbus->parent = dev;\n\tpriv->ds->slave_mii_bus = bus;\n\tpriv->ds->slave_mii_bus->priv = priv->mii_bus->priv;\n\tpriv->ds->slave_mii_bus->access_capabilities = priv->mii_bus->access_capabilities;\n\n\tret = mdiobus_register(priv->ds->slave_mii_bus);\n\tif (ret && mii_np) {\n\t\tof_node_put(dn);\n\t\treturn ret;\n\t}\n\n\tdn = of_find_compatible_node(NULL, NULL, \"realtek,rtl83xx-switch\");\n\tif (!dn) {\n\t\tdev_err(priv->dev, \"No RTL switch node in DTS\\n\");\n\t\treturn -ENODEV;\n\t}\n\n\tfor_each_node_by_name(dn, \"port\") {\n\t\tphy_interface_t interface;\n\t\tu32 led_set;\n\n\t\tif (of_property_read_u32(dn, \"reg\", &pn))\n\t\t\tcontinue;\n\n\t\tpr_info(\"%s found port %d\\n\", __func__, pn);\n\t\tphy_node = of_parse_phandle(dn, \"phy-handle\", 0);\n\t\tif (!phy_node) {\n\t\t\tif (pn != priv->cpu_port)\n\t\t\t\tdev_err(priv->dev, \"Port node %d misses phy-handle\\n\", pn);\n\t\t\tcontinue;\n\t\t}\n\n\t\tpr_info(\"%s port %d has phandle\\n\", __func__, pn);\n\t\tif (of_property_read_u32(phy_node, \"sds\", &priv->ports[pn].sds_num))\n\t\t\tpriv->ports[pn].sds_num = -1;\n\t\telse {\n\t\t\tpr_info(\"%s sds port %d is %d\\n\", __func__, pn,\n\t\t\t\tpriv->ports[pn].sds_num);\n\t\t}\n\t\tpr_info(\"%s port %d has SDS\\n\", __func__, priv->ports[pn].sds_num);\n\n\t\tif (of_get_phy_mode(dn, &interface))\n\t\t\tinterface = PHY_INTERFACE_MODE_NA;\n\t\tif (interface == PHY_INTERFACE_MODE_HSGMII)\n\t\t\tpriv->ports[pn].is2G5 = true;\n\t\tif (interface == PHY_INTERFACE_MODE_USXGMII)\n\t\t\tpriv->ports[pn].is2G5 = priv->ports[pn].is10G = true;\n\t\tif (interface == PHY_INTERFACE_MODE_10GBASER)\n\t\t\tpriv->ports[pn].is10G = true;\n\n\t\tif (of_property_read_u32(dn, \"led-set\", &led_set))\n\t\t\tled_set = 0;\n\t\tpriv->ports[pn].led_set = led_set;\n\n\t\t// Check for the integrated SerDes of the RTL8380M first\n\t\tif (of_property_read_bool(phy_node, \"phy-is-integrated\")\n\t\t    && priv->id == 0x8380 && pn >= 24) {\n\t\t\tpr_debug(\"----> FÓUND A SERDES\\n\");\n\t\t\tpriv->ports[pn].phy = PHY_RTL838X_SDS;\n\t\t\tcontinue;\n\t\t}\n\n\t\tif (priv->id >= 0x9300) {\n\t\t\tpriv->ports[pn].phy_is_integrated = false;\n\t\t\tif (of_property_read_bool(phy_node, \"phy-is-integrated\")) {\n\t\t\t\tpriv->ports[pn].phy_is_integrated = true;\n\t\t\t\tpriv->ports[pn].phy = PHY_RTL930X_SDS;\n\t\t\t}\n\t\t} else {\n\t\t\tif (of_property_read_bool(phy_node, \"phy-is-integrated\")\n\t\t\t\t&& !of_property_read_bool(phy_node, \"sfp\")) {\n\t\t\t\tpriv->ports[pn].phy = PHY_RTL8218B_INT;\n\t\t\t\tcontinue;\n\t\t\t}\n\t\t}\n\n\t\tif (!of_property_read_bool(phy_node, \"phy-is-integrated\")\n\t\t    && of_property_read_bool(phy_node, \"sfp\")) {\n\t\t\tpriv->ports[pn].phy = PHY_RTL8214FC;\n\t\t\tcontinue;\n\t\t}\n\n\t\tif (!of_property_read_bool(phy_node, \"phy-is-integrated\")\n\t\t    && !of_property_read_bool(phy_node, \"sfp\")) {\n\t\t\tpriv->ports[pn].phy = PHY_RTL8218B_EXT;\n\t\t\tcontinue;\n\t\t}\n\t}\n\n\t/* Disable MAC polling the PHY so that we can start configuration */\n\tpriv->r->set_port_reg_le(0ULL, priv->r->smi_poll_ctrl);\n\n\t/* Enable PHY control via SoC */\n\tif (priv->family_id == RTL8380_FAMILY_ID) {\n\t\t/* Enable SerDes NWAY and PHY control via SoC */\n\t\tsw_w32_mask(BIT(7), BIT(15), RTL838X_SMI_GLB_CTRL);\n\t} else if (priv->family_id == RTL8390_FAMILY_ID) {\n\t\t/* Disable PHY polling via SoC */\n\t\tsw_w32_mask(BIT(7), 0, RTL839X_SMI_GLB_CTRL);\n\t}\n\n\t/* Power on fibre ports and reset them if necessary */\n\tif (priv->ports[24].phy == PHY_RTL838X_SDS) {\n\t\tpr_debug(\"Powering on fibre ports & reset\\n\");\n\t\trtl8380_sds_power(24, 1);\n\t\trtl8380_sds_power(26, 1);\n\t}\n\n\tpr_debug(\"%s done\\n\", __func__);\n\treturn 0;\n}\n\nstatic int __init rtl83xx_get_l2aging(struct rtl838x_switch_priv *priv)\n{\n\tint t = sw_r32(priv->r->l2_ctrl_1);\n\n\tt &= priv->family_id == RTL8380_FAMILY_ID ? 0x7fffff : 0x1FFFFF;\n\n\tif (priv->family_id == RTL8380_FAMILY_ID)\n\t\tt = t * 128 / 625; /* Aging time in seconds. 0: L2 aging disabled */\n\telse\n\t\tt = (t * 3) / 5;\n\n\tpr_debug(\"L2 AGING time: %d sec\\n\", t);\n\tpr_debug(\"Dynamic aging for ports: %x\\n\", sw_r32(priv->r->l2_port_aging_out));\n\treturn t;\n}\n\n/* Caller must hold priv->reg_mutex */\nint rtl83xx_lag_add(struct dsa_switch *ds, int group, int port, struct netdev_lag_upper_info *info)\n{\n\tstruct rtl838x_switch_priv *priv = ds->priv;\n\tint i;\n\tu32 algomsk = 0;\n\tu32 algoidx = 0;\n\tif (info->tx_type != NETDEV_LAG_TX_TYPE_HASH) {\n\t\treturn -EINVAL;\n\t}\n\tpr_info(\"%s: Adding port %d to LA-group %d\\n\", __func__, port, group);\n\tif (group >= priv->n_lags) {\n\t\tpr_err(\"Link Agrregation group too large.\\n\");\n\t\treturn -EINVAL;\n\t}\n\n\tif (port >= priv->cpu_port) {\n\t\tpr_err(\"Invalid port number.\\n\");\n\t\treturn -EINVAL;\n\t}\n\n\tfor (i = 0; i < priv->n_lags; i++) {\n\t\tif (priv->lags_port_members[i] & BIT_ULL(port))\n\t\t\tbreak;\n\t}\n\tif (i != priv->n_lags) {\n\t\tpr_err(\"%s: Port already member of LAG: %d\\n\", __func__, i);\n\t\treturn -ENOSPC;\n\t}\n\tswitch(info->hash_type) {\n\tcase NETDEV_LAG_HASH_L2:\n\t\talgomsk |= TRUNK_DISTRIBUTION_ALGO_DMAC_BIT;\n\t\talgomsk |= TRUNK_DISTRIBUTION_ALGO_SMAC_BIT;\n\tbreak;\n\tcase NETDEV_LAG_HASH_L23:\n\t\talgomsk |= TRUNK_DISTRIBUTION_ALGO_DMAC_BIT;\n\t\talgomsk |= TRUNK_DISTRIBUTION_ALGO_SMAC_BIT;\n\t\talgomsk |= TRUNK_DISTRIBUTION_ALGO_SIP_BIT; //source ip\n\t\talgomsk |= TRUNK_DISTRIBUTION_ALGO_DIP_BIT; //dest ip\n\t\talgoidx = 1;\n\tbreak;\n\tcase NETDEV_LAG_HASH_L34:\n\t\talgomsk |= TRUNK_DISTRIBUTION_ALGO_SRC_L4PORT_BIT; //sport\n\t\talgomsk |= TRUNK_DISTRIBUTION_ALGO_DST_L4PORT_BIT; //dport\n\t\talgomsk |= TRUNK_DISTRIBUTION_ALGO_SIP_BIT; //source ip\n\t\talgomsk |= TRUNK_DISTRIBUTION_ALGO_DIP_BIT; //dest ip\n\t\talgoidx = 2;\n\tbreak;\n\tdefault:\n\t\talgomsk |= 0x7f;\n\t}\n\tpriv->r->set_distribution_algorithm(group, algoidx, algomsk);\n\tpriv->r->mask_port_reg_be(0, BIT_ULL(port), priv->r->trk_mbr_ctr(group));\n\tpriv->lags_port_members[group] |= BIT_ULL(port);\n\n\tpr_debug(\"lags_port_members %d now %016llx\\n\", group, priv->lags_port_members[group]);\n\treturn 0;\n}\n\n/* Caller must hold priv->reg_mutex */\nint rtl83xx_lag_del(struct dsa_switch *ds, int group, int port)\n{\n\tstruct rtl838x_switch_priv *priv = ds->priv;\n\n\tpr_info(\"%s: Removing port %d from LA-group %d\\n\", __func__, port, group);\n\n\tif (group >= priv->n_lags) {\n\t\tpr_err(\"Link Agrregation group too large.\\n\");\n\t\treturn -EINVAL;\n\t}\n\n\tif (port >= priv->cpu_port) {\n\t\tpr_err(\"Invalid port number.\\n\");\n\t\treturn -EINVAL;\n\t}\n\n\n\tif (!(priv->lags_port_members[group] & BIT_ULL(port))) {\n\t\tpr_err(\"%s: Port not member of LAG: %d\\n\", __func__, group);\n\t\treturn -ENOSPC;\n\t}\n\t// 0x7f algo mask all\n\tpriv->r->mask_port_reg_be(BIT_ULL(port), 0, priv->r->trk_mbr_ctr(group));\n\tpriv->lags_port_members[group] &= ~BIT_ULL(port);\n\n\tpr_info(\"lags_port_members %d now %016llx\\n\", group, priv->lags_port_members[group]);\n\treturn 0;\n}\n\n/*\n * Allocate a 64 bit octet counter located in the LOG HW table\n */\nstatic int rtl83xx_octet_cntr_alloc(struct rtl838x_switch_priv *priv)\n{\n\tint idx;\n\n\tmutex_lock(&priv->reg_mutex);\n\n\tidx = find_first_zero_bit(priv->octet_cntr_use_bm, MAX_COUNTERS);\n\tif (idx >= priv->n_counters) {\n\t\tmutex_unlock(&priv->reg_mutex);\n\t\treturn -1;\n\t}\n\n\tset_bit(idx, priv->octet_cntr_use_bm);\n\tmutex_unlock(&priv->reg_mutex);\n\n\treturn idx;\n}\n\n/*\n * Allocate a 32-bit packet counter\n * 2 32-bit packet counters share the location of a 64-bit octet counter\n * Initially there are no free packet counters and 2 new ones need to be freed\n * by allocating the corresponding octet counter\n */\nint rtl83xx_packet_cntr_alloc(struct rtl838x_switch_priv *priv)\n{\n\tint idx, j;\n\n\tmutex_lock(&priv->reg_mutex);\n\n\t/* Because initially no packet counters are free, the logic is reversed:\n\t * a 0-bit means the counter is already allocated (for octets)\n\t */\n\tidx = find_first_bit(priv->packet_cntr_use_bm, MAX_COUNTERS * 2);\n\tif (idx >= priv->n_counters * 2) {\n\t\tj = find_first_zero_bit(priv->octet_cntr_use_bm, MAX_COUNTERS);\n\t\tif (j >= priv->n_counters) {\n\t\t\tmutex_unlock(&priv->reg_mutex);\n\t\t\treturn -1;\n\t\t}\n\t\tset_bit(j, priv->octet_cntr_use_bm);\n\t\tidx = j * 2;\n\t\tset_bit(j * 2 + 1, priv->packet_cntr_use_bm);\n\n\t} else {\n\t\tclear_bit(idx, priv->packet_cntr_use_bm);\n\t}\n\n\tmutex_unlock(&priv->reg_mutex);\n\n\treturn idx;\n}\n\n/*\n * Add an L2 nexthop entry for the L3 routing system / PIE forwarding in the SoC\n * Use VID and MAC in rtl838x_l2_entry to identify either a free slot in the L2 hash table\n * or mark an existing entry as a nexthop by setting it's nexthop bit\n * Called from the L3 layer\n * The index in the L2 hash table is filled into nh->l2_id;\n */\nint rtl83xx_l2_nexthop_add(struct rtl838x_switch_priv *priv, struct rtl83xx_nexthop *nh)\n{\n\tstruct rtl838x_l2_entry e;\n\tu64 seed = priv->r->l2_hash_seed(nh->mac, nh->rvid);\n\tu32 key = priv->r->l2_hash_key(priv, seed);\n\tint i, idx = -1;\n\tu64 entry;\n\n\tpr_debug(\"%s searching for %08llx vid %d with key %d, seed: %016llx\\n\",\n\t\t__func__, nh->mac, nh->rvid, key, seed);\n\n\te.type = L2_UNICAST;\n\tu64_to_ether_addr(nh->mac, &e.mac[0]);\n\te.port = nh->port;\n\n\t// Loop over all entries in the hash-bucket and over the second block on 93xx SoCs\n\tfor (i = 0; i < priv->l2_bucket_size; i++) {\n\t\tentry = priv->r->read_l2_entry_using_hash(key, i, &e);\n\n\t\tif (!e.valid || ((entry & 0x0fffffffffffffffULL) == seed)) {\n\t\t\tidx = i > 3 ? ((key >> 14) & 0xffff) | i >> 1\n\t\t\t\t\t: ((key << 2) | i) & 0xffff;\n\t\t\tbreak;\n\t\t}\n\t}\n\n\tif (idx < 0) {\n\t\tpr_err(\"%s: No more L2 forwarding entries available\\n\", __func__);\n\t\treturn -1;\n\t}\n\n\t// Found an existing (e->valid is true) or empty entry, make it a nexthop entry\n\tnh->l2_id = idx;\n\tif (e.valid) {\n\t\tnh->port = e.port;\n\t\tnh->vid = e.vid;\t\t// Save VID\n\t\tnh->rvid = e.rvid;\n\t\tnh->dev_id = e.stack_dev;\n\t\t// If the entry is already a valid next hop entry, don't change it\n\t\tif (e.next_hop)\n\t\t\treturn 0;\n\t} else {\n\t\te.valid = true;\n\t\te.is_static = true;\n\t\te.rvid = nh->rvid;\n\t\te.is_ip_mc = false;\n\t\te.is_ipv6_mc = false;\n\t\te.block_da = false;\n\t\te.block_sa = false;\n\t\te.suspended = false;\n\t\te.age = 0;\t\t\t// With port-ignore\n\t\te.port = priv->port_ignore;\n\t\tu64_to_ether_addr(nh->mac, &e.mac[0]);\n\t}\n\te.next_hop = true;\n\te.nh_route_id = nh->id;\t\t\t// NH route ID takes place of VID\n\te.nh_vlan_target = false;\n\n\tpriv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);\n\n\treturn 0;\n}\n\n/*\n * Removes a Layer 2 next hop entry in the forwarding database\n * If it was static, the entire entry is removed, otherwise the nexthop bit is cleared\n * and we wait until the entry ages out\n */\nint rtl83xx_l2_nexthop_rm(struct rtl838x_switch_priv *priv, struct rtl83xx_nexthop *nh)\n{\n\tstruct rtl838x_l2_entry e;\n\tu32 key = nh->l2_id >> 2;\n\tint i = nh->l2_id & 0x3;\n\tu64 entry = entry = priv->r->read_l2_entry_using_hash(key, i, &e);\n\n\tpr_debug(\"%s: id %d, key %d, index %d\\n\", __func__, nh->l2_id, key, i);\n\tif (!e.valid) {\n\t\tdev_err(priv->dev, \"unknown nexthop, id %x\\n\", nh->l2_id);\n\t\treturn -1;\n\t}\n\n\tif (e.is_static)\n\t\te.valid = false;\n\te.next_hop = false;\n\te.vid = nh->vid;\t\t// Restore VID\n\te.rvid = nh->rvid;\n\n\tpriv->r->write_l2_entry_using_hash(key, i, &e);\n\n\treturn 0;\n}\n\nstatic int rtl83xx_handle_changeupper(struct rtl838x_switch_priv *priv,\n\t\t\t\t      struct net_device *ndev,\n\t\t\t\t      struct netdev_notifier_changeupper_info *info)\n{\n\tstruct net_device *upper = info->upper_dev;\n\tstruct netdev_lag_upper_info *lag_upper_info = NULL;\n\tint i, j, err;\n\n\tif (!netif_is_lag_master(upper))\n\t\treturn 0;\n\n\tmutex_lock(&priv->reg_mutex);\n\n\tfor (i = 0; i < priv->n_lags; i++) {\n\t\tif ((!priv->lag_devs[i]) || (priv->lag_devs[i] == upper))\n\t\t\tbreak;\n\t}\n\tfor (j = 0; j < priv->cpu_port; j++) {\n\t\tif (priv->ports[j].dp->slave == ndev)\n\t\t\tbreak;\n\t}\n\tif (j >= priv->cpu_port) {\n\t\terr = -EINVAL;\n\t\tgoto out;\n\t}\n\n\tif (info->linking) {\n\t\tlag_upper_info = info->upper_info;\n\t\tif (!priv->lag_devs[i])\n\t\t\tpriv->lag_devs[i] = upper;\n\t\terr = rtl83xx_lag_add(priv->ds, i, priv->ports[j].dp->index, lag_upper_info);\n\t\tif (err) {\n\t\t\terr = -EINVAL;\n\t\t\tgoto out;\n\t\t}\n\t} else {\n\t\tif (!priv->lag_devs[i])\n\t\t\terr = -EINVAL;\n\t\terr = rtl83xx_lag_del(priv->ds, i, priv->ports[j].dp->index);\n\t\tif (err) {\n\t\t\terr = -EINVAL;\n\t\t\tgoto out;\n\t\t}\n\t\tif (!priv->lags_port_members[i])\n\t\t\tpriv->lag_devs[i] = NULL;\n\t}\n\nout:\n\tmutex_unlock(&priv->reg_mutex);\n\treturn 0;\n}\n\n/*\n * Is the lower network device a DSA slave network device of our RTL930X-switch?\n * Unfortunately we cannot just follow dev->dsa_prt as this is only set for the\n * DSA master device.\n */\nint rtl83xx_port_is_under(const struct net_device * dev, struct rtl838x_switch_priv *priv)\n{\n\tint i;\n\n// TODO: On 5.12:\n// \tif(!dsa_slave_dev_check(dev)) {\n//\t\tnetdev_info(dev, \"%s: not a DSA device.\\n\", __func__);\n//\t\treturn -EINVAL;\n//\t}\n\n\tfor (i = 0; i < priv->cpu_port; i++) {\n\t\tif (!priv->ports[i].dp)\n\t\t\tcontinue;\n\t\tif (priv->ports[i].dp->slave == dev)\n\t\t\treturn i;\n\t}\n\treturn -EINVAL;\n}\n\nstatic int rtl83xx_netdevice_event(struct notifier_block *this,\n\t\t\t\t   unsigned long event, void *ptr)\n{\n\tstruct net_device *ndev = netdev_notifier_info_to_dev(ptr);\n\tstruct rtl838x_switch_priv *priv;\n\tint err;\n\n\tpr_debug(\"In: %s, event: %lu\\n\", __func__, event);\n\n\tif ((event != NETDEV_CHANGEUPPER) && (event != NETDEV_CHANGELOWERSTATE))\n\t\treturn NOTIFY_DONE;\n\n\tpriv = container_of(this, struct rtl838x_switch_priv, nb);\n\tswitch (event) {\n\tcase NETDEV_CHANGEUPPER:\n\t\terr = rtl83xx_handle_changeupper(priv, ndev, ptr);\n\t\tbreak;\n\t}\n\n\tif (err)\n\t\treturn err;\n\n\treturn NOTIFY_DONE;\n}\n\nconst static struct rhashtable_params route_ht_params = {\n\t.key_len     = sizeof(u32),\n\t.key_offset  = offsetof(struct rtl83xx_route, gw_ip),\n\t.head_offset = offsetof(struct rtl83xx_route, linkage),\n};\n\n/*\n * Updates an L3 next hop entry in the ROUTING table\n */\nstatic int rtl83xx_l3_nexthop_update(struct rtl838x_switch_priv *priv,  __be32 ip_addr, u64 mac)\n{\n\tstruct rtl83xx_route *r;\n\tstruct rhlist_head *tmp, *list;\n\n\trcu_read_lock();\n\tlist = rhltable_lookup(&priv->routes, &ip_addr, route_ht_params);\n\tif (!list) {\n\t\trcu_read_unlock();\n\t\treturn -ENOENT;\n\t}\n\n\trhl_for_each_entry_rcu(r, tmp, list, linkage) {\n\t\tpr_info(\"%s: Setting up fwding: ip %pI4, GW mac %016llx\\n\",\n\t\t\t__func__, &ip_addr, mac);\n\n\t\t// Reads the ROUTING table entry associated with the route\n\t\tpriv->r->route_read(r->id, r);\n\t\tpr_info(\"Route with id %d to %pI4 / %d\\n\", r->id, &r->dst_ip, r->prefix_len);\n\n\t\tr->nh.mac = r->nh.gw = mac;\n\t\tr->nh.port = priv->port_ignore;\n\t\tr->nh.id = r->id;\n\n\t\t// Do we need to explicitly add a DMAC entry with the route's nh index?\n\t\tif (priv->r->set_l3_egress_mac)\n\t\t\tpriv->r->set_l3_egress_mac(r->id, mac);\n\n\t\t// Update ROUTING table: map gateway-mac and switch-mac id to route id\n\t\trtl83xx_l2_nexthop_add(priv, &r->nh);\n\n\t\tr->attr.valid = true;\n\t\tr->attr.action = ROUTE_ACT_FORWARD;\n\t\tr->attr.type = 0;\n\t\tr->attr.hit = false; // Reset route-used indicator\n\n\t\t// Add PIE entry with dst_ip and prefix_len\n\t\tr->pr.dip = r->dst_ip;\n\t\tr->pr.dip_m = inet_make_mask(r->prefix_len);\n\n\t\tif (r->is_host_route) {\n\t\t\tint slot = priv->r->find_l3_slot(r, false);\n\n\t\t\tpr_info(\"%s: Got slot for route: %d\\n\", __func__, slot);\n\t\t\tpriv->r->host_route_write(slot, r);\n\t\t} else {\n\t\t\tpriv->r->route_write(r->id, r);\n\t\t\tr->pr.fwd_sel = true;\n\t\t\tr->pr.fwd_data = r->nh.l2_id;\n\t\t\tr->pr.fwd_act = PIE_ACT_ROUTE_UC;\n\t\t}\n\n\t\tif (priv->r->set_l3_nexthop)\n\t\t\tpriv->r->set_l3_nexthop(r->nh.id, r->nh.l2_id, r->nh.if_id);\n\n\t\tif (r->pr.id < 0) {\n\t\t\tr->pr.packet_cntr = rtl83xx_packet_cntr_alloc(priv);\n\t\t\tif (r->pr.packet_cntr >= 0) {\n\t\t\t\tpr_info(\"Using packet counter %d\\n\", r->pr.packet_cntr);\n\t\t\t\tr->pr.log_sel = true;\n\t\t\t\tr->pr.log_data = r->pr.packet_cntr;\n\t\t\t}\n\t\t\tpriv->r->pie_rule_add(priv, &r->pr);\n\t\t} else {\n\t\t\tint pkts = priv->r->packet_cntr_read(r->pr.packet_cntr);\n\t\t\tpr_info(\"%s: total packets: %d\\n\", __func__, pkts);\n\n\t\t\tpriv->r->pie_rule_write(priv, r->pr.id, &r->pr);\n\t\t}\n\t}\n\trcu_read_unlock();\n\treturn 0;\n}\n\nstatic int rtl83xx_port_ipv4_resolve(struct rtl838x_switch_priv *priv,\n\t\t\t\t     struct net_device *dev, __be32 ip_addr)\n{\n\tstruct neighbour *n = neigh_lookup(&arp_tbl, &ip_addr, dev);\n\tint err = 0;\n\tu64 mac;\n\n\tif (!n) {\n\t\tn = neigh_create(&arp_tbl, &ip_addr, dev);\n\t\tif (IS_ERR(n))\n\t\t\treturn PTR_ERR(n);\n\t}\n\n\t/* If the neigh is already resolved, then go ahead and\n\t * install the entry, otherwise start the ARP process to\n\t * resolve the neigh.\n\t */\n\tif (n->nud_state & NUD_VALID) {\n\t\tmac = ether_addr_to_u64(n->ha);\n\t\tpr_info(\"%s: resolved mac: %016llx\\n\", __func__, mac);\n\t\trtl83xx_l3_nexthop_update(priv, ip_addr, mac);\n\t} else {\n\t\tpr_info(\"%s: need to wait\\n\", __func__);\n\t\tneigh_event_send(n, NULL);\n\t}\n\n\tneigh_release(n);\n\treturn err;\n}\n\nstruct rtl83xx_walk_data {\n\tstruct rtl838x_switch_priv *priv;\n\tint port;\n};\n\nstatic int rtl83xx_port_lower_walk(struct net_device *lower, struct netdev_nested_priv *_priv)\n{\n\tstruct rtl83xx_walk_data *data = (struct rtl83xx_walk_data *)_priv->data;\n\tstruct rtl838x_switch_priv *priv = data->priv;\n\tint ret = 0;\n\tint index;\n\n\tindex = rtl83xx_port_is_under(lower, priv);\n\tdata->port = index;\n\tif (index >= 0) {\n\t\tpr_debug(\"Found DSA-port, index %d\\n\", index);\n\t\tret = 1;\n\t}\n\n\treturn ret;\n}\n\nint rtl83xx_port_dev_lower_find(struct net_device *dev, struct rtl838x_switch_priv *priv)\n{\n\tstruct rtl83xx_walk_data data;\n\tstruct netdev_nested_priv _priv;\n\n\tdata.priv = priv;\n\tdata.port = 0;\n\t_priv.data = (void *)&data;\n\n\tnetdev_walk_all_lower_dev(dev, rtl83xx_port_lower_walk, &_priv);\n\n\treturn data.port;\n}\n\nstatic struct rtl83xx_route *rtl83xx_route_alloc(struct rtl838x_switch_priv *priv, u32 ip)\n{\n\tstruct rtl83xx_route *r;\n\tint idx = 0, err;\n\n\tmutex_lock(&priv->reg_mutex);\n\n\tidx = find_first_zero_bit(priv->route_use_bm, MAX_ROUTES);\n\tpr_debug(\"%s id: %d, ip %pI4\\n\", __func__, idx, &ip);\n\n\tr = kzalloc(sizeof(*r), GFP_KERNEL);\n\tif (!r) {\n\t\tmutex_unlock(&priv->reg_mutex);\n\t\treturn r;\n\t}\n\n\tr->id = idx;\n\tr->gw_ip = ip;\n\tr->pr.id = -1; // We still need to allocate a rule in HW\n\tr->is_host_route = false;\n\n\terr = rhltable_insert(&priv->routes, &r->linkage, route_ht_params);\n\tif (err) {\n\t\tpr_err(\"Could not insert new rule\\n\");\n\t\tmutex_unlock(&priv->reg_mutex);\n\t\tgoto out_free;\n\t}\n\n\tset_bit(idx, priv->route_use_bm);\n\n\tmutex_unlock(&priv->reg_mutex);\n\n\treturn r;\n\nout_free:\n\tkfree(r);\n\treturn NULL;\n}\n\n\nstatic struct rtl83xx_route *rtl83xx_host_route_alloc(struct rtl838x_switch_priv *priv, u32 ip)\n{\n\tstruct rtl83xx_route *r;\n\tint idx = 0, err;\n\n\tmutex_lock(&priv->reg_mutex);\n\n\tidx = find_first_zero_bit(priv->host_route_use_bm, MAX_HOST_ROUTES);\n\tpr_debug(\"%s id: %d, ip %pI4\\n\", __func__, idx, &ip);\n\n\tr = kzalloc(sizeof(*r), GFP_KERNEL);\n\tif (!r) {\n\t\tmutex_unlock(&priv->reg_mutex);\n\t\treturn r;\n\t}\n\n\t/* We require a unique route ID irrespective of whether it is a prefix or host\n\t * route (on RTL93xx) as we use this ID to associate a DMAC and next-hop entry */\n\tr->id = idx + MAX_ROUTES;\n\n\tr->gw_ip = ip;\n\tr->pr.id = -1; // We still need to allocate a rule in HW\n\tr->is_host_route = true;\n\n\terr = rhltable_insert(&priv->routes, &r->linkage, route_ht_params);\n\tif (err) {\n\t\tpr_err(\"Could not insert new rule\\n\");\n\t\tmutex_unlock(&priv->reg_mutex);\n\t\tgoto out_free;\n\t}\n\n\tset_bit(idx, priv->host_route_use_bm);\n\n\tmutex_unlock(&priv->reg_mutex);\n\n\treturn r;\n\nout_free:\n\tkfree(r);\n\treturn NULL;\n}\n\n\n\nstatic void rtl83xx_route_rm(struct rtl838x_switch_priv *priv, struct rtl83xx_route *r)\n{\n\tint id;\n\n\tif (rhltable_remove(&priv->routes, &r->linkage, route_ht_params))\n\t\tdev_warn(priv->dev, \"Could not remove route\\n\");\n\n\tif (r->is_host_route) {\n\t\tid = priv->r->find_l3_slot(r, false);\n\t\tpr_debug(\"%s: Got id for host route: %d\\n\", __func__, id);\n\t\tr->attr.valid = false;\n\t\tpriv->r->host_route_write(id, r);\n\t\tclear_bit(r->id - MAX_ROUTES, priv->host_route_use_bm);\n\t} else {\n\t\t// If there is a HW representation of the route, delete it\n\t\tif (priv->r->route_lookup_hw) {\n\t\t\tid = priv->r->route_lookup_hw(r);\n\t\t\tpr_info(\"%s: Got id for prefix route: %d\\n\", __func__, id);\n\t\t\tr->attr.valid = false;\n\t\t\tpriv->r->route_write(id, r);\n\t\t}\n\t\tclear_bit(r->id, priv->route_use_bm);\n\t}\n\n\tkfree(r);\n}\n\nstatic int rtl83xx_fib4_del(struct rtl838x_switch_priv *priv,\n\t\t\t    struct fib_entry_notifier_info *info)\n{\n\tstruct fib_nh *nh = fib_info_nh(info->fi, 0);\n\tstruct rtl83xx_route *r;\n\tstruct rhlist_head *tmp, *list;\n\n\tpr_debug(\"In %s, ip %pI4, len %d\\n\", __func__, &info->dst, info->dst_len);\n\trcu_read_lock();\n\tlist = rhltable_lookup(&priv->routes, &nh->fib_nh_gw4, route_ht_params);\n\tif (!list) {\n\t\trcu_read_unlock();\n\t\tpr_err(\"%s: no such gateway: %pI4\\n\", __func__, &nh->fib_nh_gw4);\n\t\treturn -ENOENT;\n\t}\n\trhl_for_each_entry_rcu(r, tmp, list, linkage) {\n\t\tif (r->dst_ip == info->dst && r->prefix_len == info->dst_len) {\n\t\t\tpr_info(\"%s: found a route with id %d, nh-id %d\\n\",\n\t\t\t\t__func__, r->id, r->nh.id);\n\t\t\tbreak;\n\t\t}\n\t}\n\trcu_read_unlock();\n\n\trtl83xx_l2_nexthop_rm(priv, &r->nh);\n\n\tpr_debug(\"%s: Releasing packet counter %d\\n\", __func__, r->pr.packet_cntr);\n\tset_bit(r->pr.packet_cntr, priv->packet_cntr_use_bm);\n\tpriv->r->pie_rule_rm(priv, &r->pr);\n\n\trtl83xx_route_rm(priv, r);\n\n\tnh->fib_nh_flags &= ~RTNH_F_OFFLOAD;\n\n\treturn 0;\n}\n\n/*\n * On the RTL93xx, an L3 termination endpoint MAC address on which the router waits\n * for packets to be routed needs to be allocated.\n */\nstatic int rtl83xx_alloc_router_mac(struct rtl838x_switch_priv *priv, u64 mac)\n{\n\tint i, free_mac = -1;\n\tstruct rtl93xx_rt_mac m;\n\n\tmutex_lock(&priv->reg_mutex);\n\tfor (i = 0; i < MAX_ROUTER_MACS; i++) {\n\t\tpriv->r->get_l3_router_mac(i, &m);\n\t\tif (free_mac < 0 && !m.valid) {\n\t\t\tfree_mac = i;\n\t\t\tcontinue;\n\t\t}\n\t\tif (m.valid && m.mac == mac) {\n\t\t\tfree_mac = i;\n\t\t\tbreak;\n\t\t}\n\t}\n\n\tif (free_mac < 0) {\n\t\tpr_err(\"No free router MACs, cannot offload\\n\");\n\t\tmutex_unlock(&priv->reg_mutex);\n\t\treturn -1;\n\t}\n\n\tm.valid = true;\n\tm.mac = mac;\n\tm.p_type = 0; // An individual port, not a trunk port\n\tm.p_id = 0x3f;\t\t\t// Listen on any port\n\tm.p_id_mask = 0;\n\tm.vid = 0;\t\t\t// Listen on any VLAN...\n\tm.vid_mask = 0; \t\t// ... so mask needs to be 0\n\tm.mac_mask = 0xffffffffffffULL;\t// We want an exact match of the interface MAC\n\tm.action = L3_FORWARD;\t\t// Route the packet\n\tpriv->r->set_l3_router_mac(free_mac, &m);\n\n\tmutex_unlock(&priv->reg_mutex);\n\n\treturn 0;\n}\n\nstatic int rtl83xx_alloc_egress_intf(struct rtl838x_switch_priv *priv, u64 mac, int vlan)\n{\n\tint i, free_mac = -1;\n\tstruct rtl838x_l3_intf intf;\n\tu64 m;\n\n\tmutex_lock(&priv->reg_mutex);\n\tfor (i = 0; i < MAX_SMACS; i++) {\n\t\tm = priv->r->get_l3_egress_mac(L3_EGRESS_DMACS + i);\n\t\tif (free_mac < 0 && !m) {\n\t\t\tfree_mac = i;\n\t\t\tcontinue;\n\t\t}\n\t\tif (m == mac) {\n\t\t\tmutex_unlock(&priv->reg_mutex);\n\t\t\treturn i;\n\t\t}\n\t}\n\n\tif (free_mac < 0) {\n\t\tpr_err(\"No free egress interface, cannot offload\\n\");\n\t\treturn -1;\n\t}\n\n\t// Set up default egress interface 1\n\tintf.vid = vlan;\n\tintf.smac_idx = free_mac;\n\tintf.ip4_mtu_id = 1;\n\tintf.ip6_mtu_id = 1;\n\tintf.ttl_scope = 1; // TTL\n\tintf.hl_scope = 1;  // Hop Limit\n\tintf.ip4_icmp_redirect = intf.ip6_icmp_redirect = 2;  // FORWARD\n\tintf.ip4_pbr_icmp_redirect = intf.ip6_pbr_icmp_redirect = 2; // FORWARD;\n\tpriv->r->set_l3_egress_intf(free_mac, &intf);\n\n\tpriv->r->set_l3_egress_mac(L3_EGRESS_DMACS + free_mac, mac);\n\n\tmutex_unlock(&priv->reg_mutex);\n\n\treturn free_mac;\n}\n\nstatic int rtl83xx_fib4_add(struct rtl838x_switch_priv *priv,\n\t\t\t    struct fib_entry_notifier_info *info)\n{\n\tstruct fib_nh *nh = fib_info_nh(info->fi, 0);\n\tstruct net_device *dev = fib_info_nh(info->fi, 0)->fib_nh_dev;\n\tint port;\n\tstruct rtl83xx_route *r;\n\tbool to_localhost;\n\tint vlan = is_vlan_dev(dev) ? vlan_dev_vlan_id(dev) : 0;\n\n\tpr_debug(\"In %s, ip %pI4, len %d\\n\", __func__, &info->dst, info->dst_len);\n\tif (!info->dst) {\n\t\tpr_info(\"Not offloading default route for now\\n\");\n\t\treturn 0;\n\t}\n\n\tpr_debug(\"GW: %pI4, interface name %s, mac %016llx, vlan %d\\n\", &nh->fib_nh_gw4, dev->name,\n\t\tether_addr_to_u64(dev->dev_addr), vlan\n\t);\n\n\tport = rtl83xx_port_dev_lower_find(dev, priv);\n\tif (port < 0)\n\t\treturn -1;\n\n\t// For now we only work with routes that have a gateway and are not ourself\n//\tif ((!nh->fib_nh_gw4) && (info->dst_len != 32))\n//\t\treturn 0;\n\n\tif ((info->dst & 0xff) == 0xff)\n\t\treturn 0;\n\n\t// Do not offload routes to 192.168.100.x\n\tif ((info->dst & 0xffffff00) == 0xc0a86400)\n\t\treturn 0;\n\n\t// Do not offload routes to 127.x.x.x\n\tif ((info->dst & 0xff000000) == 0x7f000000)\n\t\treturn 0;\n\n\t// Allocate route or host-route (entry if hardware supports this)\n\tif (info->dst_len == 32 && priv->r->host_route_write)\n\t\tr = rtl83xx_host_route_alloc(priv, nh->fib_nh_gw4);\n\telse\n\t\tr = rtl83xx_route_alloc(priv, nh->fib_nh_gw4);\n\n\tif (!r) {\n\t\tpr_err(\"%s: No more free route entries\\n\", __func__);\n\t\treturn -1;\n\t}\n\n\tr->dst_ip = info->dst;\n\tr->prefix_len = info->dst_len;\n\tr->nh.rvid = vlan;\n\tto_localhost = !nh->fib_nh_gw4;\n\n\tif (priv->r->set_l3_router_mac) {\n\t\tu64 mac = ether_addr_to_u64(dev->dev_addr);\n\n\t\tpr_debug(\"Local route and router mac %016llx\\n\", mac);\n\n\t\tif (rtl83xx_alloc_router_mac(priv, mac))\n\t\t\tgoto out_free_rt;\n\n\t\t// vid = 0: Do not care about VID\n\t\tr->nh.if_id = rtl83xx_alloc_egress_intf(priv, mac, vlan);\n\t\tif (r->nh.if_id < 0)\n\t\t\tgoto out_free_rmac;\n\n\t\tif (to_localhost) {\n\t\t\tint slot;\n\n\t\t\tr->nh.mac = mac;\n\t\t\tr->nh.port = priv->port_ignore;\n\t\t\tr->attr.valid = true;\n\t\t\tr->attr.action = ROUTE_ACT_TRAP2CPU;\n\t\t\tr->attr.type = 0;\n\n\t\t\tslot = priv->r->find_l3_slot(r, false);\n\t\t\tpr_debug(\"%s: Got slot for route: %d\\n\", __func__, slot);\n\t\t\tpriv->r->host_route_write(slot, r);\n\t\t}\n\t}\n\n\t// We need to resolve the mac address of the GW\n\tif (!to_localhost)\n\t\trtl83xx_port_ipv4_resolve(priv, dev, nh->fib_nh_gw4);\n\n\tnh->fib_nh_flags |= RTNH_F_OFFLOAD;\n\n\treturn 0;\n\nout_free_rmac:\nout_free_rt:\n\treturn 0;\n}\n\nstatic int rtl83xx_fib6_add(struct rtl838x_switch_priv *priv,\n\t\t\t    struct fib6_entry_notifier_info *info)\n{\n\tpr_debug(\"In %s\\n\", __func__);\n//\tnh->fib_nh_flags |= RTNH_F_OFFLOAD;\n\treturn 0;\n}\n\nstruct net_event_work {\n\tstruct work_struct work;\n\tstruct rtl838x_switch_priv *priv;\n\tu64 mac;\n\tu32 gw_addr;\n};\n\nstatic void rtl83xx_net_event_work_do(struct work_struct *work)\n{\n\tstruct net_event_work *net_work =\n\t\tcontainer_of(work, struct net_event_work, work);\n\tstruct rtl838x_switch_priv *priv = net_work->priv;\n\n\trtl83xx_l3_nexthop_update(priv, net_work->gw_addr, net_work->mac);\n}\n\nstatic int rtl83xx_netevent_event(struct notifier_block *this,\n\t\t\t\t unsigned long event, void *ptr)\n{\n\tstruct rtl838x_switch_priv *priv;\n\tstruct net_device *dev;\n\tstruct neighbour *n = ptr;\n\tint err, port;\n\tstruct net_event_work *net_work;\n\n\tpriv = container_of(this, struct rtl838x_switch_priv, ne_nb);\n\n\tnet_work = kzalloc(sizeof(*net_work), GFP_ATOMIC);\n\tif (!net_work)\n\t\treturn NOTIFY_BAD;\n\n\tINIT_WORK(&net_work->work, rtl83xx_net_event_work_do);\n\tnet_work->priv = priv;\n\n\tswitch (event) {\n\tcase NETEVENT_NEIGH_UPDATE:\n\t\tif (n->tbl != &arp_tbl)\n\t\t\treturn NOTIFY_DONE;\n\t\tdev = n->dev;\n\t\tport = rtl83xx_port_dev_lower_find(dev, priv);\n\t\tif (port < 0 || !(n->nud_state & NUD_VALID)) {\n\t\t\tpr_debug(\"%s: Neigbour invalid, not updating\\n\", __func__);\n\t\t\tkfree(net_work);\n\t\t\treturn NOTIFY_DONE;\n\t\t}\n\n\t\tnet_work->mac = ether_addr_to_u64(n->ha);\n\t\tnet_work->gw_addr = *(__be32 *) n->primary_key;\n\n\t\tpr_debug(\"%s: updating neighbour on port %d, mac %016llx\\n\",\n\t\t\t__func__, port, net_work->mac);\n\t\tschedule_work(&net_work->work);\n\t\tif (err)\n\t\t\tnetdev_warn(dev, \"failed to handle neigh update (err %d)\\n\", err);\n\t\tbreak;\n\t}\n\n\treturn NOTIFY_DONE;\n}\n\nstruct rtl83xx_fib_event_work {\n\tstruct work_struct work;\n\tunion {\n\t\tstruct fib_entry_notifier_info fen_info;\n\t\tstruct fib6_entry_notifier_info fen6_info;\n\t\tstruct fib_rule_notifier_info fr_info;\n\t};\n\tstruct rtl838x_switch_priv *priv;\n\tbool is_fib6;\n\tunsigned long event;\n};\n\nstatic void rtl83xx_fib_event_work_do(struct work_struct *work)\n{\n\tstruct rtl83xx_fib_event_work *fib_work =\n\t\tcontainer_of(work, struct rtl83xx_fib_event_work, work);\n\tstruct rtl838x_switch_priv *priv = fib_work->priv;\n\tstruct fib_rule *rule;\n\tint err;\n\n\t/* Protect internal structures from changes */\n\trtnl_lock();\n\tpr_debug(\"%s: doing work, event %ld\\n\", __func__, fib_work->event);\n\tswitch (fib_work->event) {\n\tcase FIB_EVENT_ENTRY_ADD:\n\tcase FIB_EVENT_ENTRY_REPLACE:\n\tcase FIB_EVENT_ENTRY_APPEND:\n\t\tif (fib_work->is_fib6) {\n\t\t\terr = rtl83xx_fib6_add(priv, &fib_work->fen6_info);\n\t\t} else {\n\t\t\terr = rtl83xx_fib4_add(priv, &fib_work->fen_info);\n\t\t\tfib_info_put(fib_work->fen_info.fi);\n\t\t}\n\t\tif (err)\n\t\t\tpr_err(\"%s: FIB4 failed\\n\", __func__);\n\t\tbreak;\n\tcase FIB_EVENT_ENTRY_DEL:\n\t\trtl83xx_fib4_del(priv, &fib_work->fen_info);\n\t\tfib_info_put(fib_work->fen_info.fi);\n\t\tbreak;\n\tcase FIB_EVENT_RULE_ADD:\n\tcase FIB_EVENT_RULE_DEL:\n\t\trule = fib_work->fr_info.rule;\n\t\tif (!fib4_rule_default(rule))\n\t\t\tpr_err(\"%s: FIB4 default rule failed\\n\", __func__);\n\t\tfib_rule_put(rule);\n\t\tbreak;\n\t}\n\trtnl_unlock();\n\tkfree(fib_work);\n}\n\n/* Called with rcu_read_lock() */\nstatic int rtl83xx_fib_event(struct notifier_block *this, unsigned long event, void *ptr)\n{\n\tstruct fib_notifier_info *info = ptr;\n\tstruct rtl838x_switch_priv *priv;\n\tstruct rtl83xx_fib_event_work *fib_work;\n\n\tif ((info->family != AF_INET && info->family != AF_INET6 &&\n\t     info->family != RTNL_FAMILY_IPMR &&\n\t     info->family != RTNL_FAMILY_IP6MR))\n\t\treturn NOTIFY_DONE;\n\n\tpriv = container_of(this, struct rtl838x_switch_priv, fib_nb);\n\n\tfib_work = kzalloc(sizeof(*fib_work), GFP_ATOMIC);\n\tif (!fib_work)\n\t\treturn NOTIFY_BAD;\n\n\tINIT_WORK(&fib_work->work, rtl83xx_fib_event_work_do);\n\tfib_work->priv = priv;\n\tfib_work->event = event;\n\tfib_work->is_fib6 = false;\n\n\tswitch (event) {\n\tcase FIB_EVENT_ENTRY_ADD:\n\tcase FIB_EVENT_ENTRY_REPLACE:\n\tcase FIB_EVENT_ENTRY_APPEND:\n\tcase FIB_EVENT_ENTRY_DEL:\n\t\tpr_debug(\"%s: FIB_ENTRY ADD/DELL, event %ld\\n\", __func__, event);\n\t\tif (info->family == AF_INET) {\n\t\t\tstruct fib_entry_notifier_info *fen_info = ptr;\n\n\t\t\tif (fen_info->fi->fib_nh_is_v6) {\n\t\t\t\tNL_SET_ERR_MSG_MOD(info->extack,\n\t\t\t\t\t\"IPv6 gateway with IPv4 route is not supported\");\n\t\t\t\tkfree(fib_work);\n\t\t\t\treturn notifier_from_errno(-EINVAL);\n\t\t\t}\n\n\t\t\tmemcpy(&fib_work->fen_info, ptr, sizeof(fib_work->fen_info));\n\t\t\t/* Take referece on fib_info to prevent it from being\n\t\t\t* freed while work is queued. Release it afterwards.\n\t\t\t*/\n\t\t\tfib_info_hold(fib_work->fen_info.fi);\n\n\t\t} else if (info->family == AF_INET6) {\n\t\t\tstruct fib6_entry_notifier_info *fen6_info = ptr;\n\t\t\tpr_warn(\"%s: FIB_RULE ADD/DELL for IPv6 not supported\\n\", __func__);\n\t\t\tkfree(fib_work);\n\t\t\treturn NOTIFY_DONE;\n\t\t}\n\t\tbreak;\n\n\tcase FIB_EVENT_RULE_ADD:\n\tcase FIB_EVENT_RULE_DEL:\n\t\tpr_debug(\"%s: FIB_RULE ADD/DELL, event: %ld\\n\", __func__, event);\n\t\tmemcpy(&fib_work->fr_info, ptr, sizeof(fib_work->fr_info));\n\t\tfib_rule_get(fib_work->fr_info.rule);\n\t\tbreak;\n\t}\n\n\tschedule_work(&fib_work->work);\n\n\treturn NOTIFY_DONE;\n}\n\nstatic int __init rtl83xx_sw_probe(struct platform_device *pdev)\n{\n\tint err = 0, i;\n\tstruct rtl838x_switch_priv *priv;\n\tstruct device *dev = &pdev->dev;\n\tu64 bpdu_mask;\n\n\tpr_debug(\"Probing RTL838X switch device\\n\");\n\tif (!pdev->dev.of_node) {\n\t\tdev_err(dev, \"No DT found\\n\");\n\t\treturn -EINVAL;\n\t}\n\n\t// Initialize access to RTL switch tables\n\trtl_table_init();\n\n\tpriv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);\n\tif (!priv)\n\t\treturn -ENOMEM;\n\n\tpriv->ds = devm_kzalloc(dev, sizeof(*priv->ds), GFP_KERNEL);\n\n\tif (!priv->ds)\n\t\treturn -ENOMEM;\n\tpriv->ds->dev = dev;\n\tpriv->ds->priv = priv;\n\tpriv->ds->ops = &rtl83xx_switch_ops;\n\tpriv->dev = dev;\n\n\tmutex_init(&priv->reg_mutex);\n\n\tpriv->family_id = soc_info.family;\n\tpriv->id = soc_info.id;\n\tswitch(soc_info.family) {\n\tcase RTL8380_FAMILY_ID:\n\t\tpriv->ds->ops = &rtl83xx_switch_ops;\n\t\tpriv->cpu_port = RTL838X_CPU_PORT;\n\t\tpriv->port_mask = 0x1f;\n\t\tpriv->port_width = 1;\n\t\tpriv->irq_mask = 0x0FFFFFFF;\n\t\tpriv->r = &rtl838x_reg;\n\t\tpriv->ds->num_ports = 29;\n\t\tpriv->fib_entries = 8192;\n\t\trtl8380_get_version(priv);\n\t\tpriv->n_lags = 8;\n\t\tpriv->l2_bucket_size = 4;\n\t\tpriv->n_pie_blocks = 12;\n\t\tpriv->port_ignore = 0x1f;\n\t\tpriv->n_counters = 128;\n\t\tbreak;\n\tcase RTL8390_FAMILY_ID:\n\t\tpriv->ds->ops = &rtl83xx_switch_ops;\n\t\tpriv->cpu_port = RTL839X_CPU_PORT;\n\t\tpriv->port_mask = 0x3f;\n\t\tpriv->port_width = 2;\n\t\tpriv->irq_mask = 0xFFFFFFFFFFFFFULL;\n\t\tpriv->r = &rtl839x_reg;\n\t\tpriv->ds->num_ports = 53;\n\t\tpriv->fib_entries = 16384;\n\t\trtl8390_get_version(priv);\n\t\tpriv->n_lags = 16;\n\t\tpriv->l2_bucket_size = 4;\n\t\tpriv->n_pie_blocks = 18;\n\t\tpriv->port_ignore = 0x3f;\n\t\tpriv->n_counters = 1024;\n\t\tbreak;\n\tcase RTL9300_FAMILY_ID:\n\t\tpriv->ds->ops = &rtl930x_switch_ops;\n\t\tpriv->cpu_port = RTL930X_CPU_PORT;\n\t\tpriv->port_mask = 0x1f;\n\t\tpriv->port_width = 1;\n\t\tpriv->irq_mask = 0x0FFFFFFF;\n\t\tpriv->r = &rtl930x_reg;\n\t\tpriv->ds->num_ports = 29;\n\t\tpriv->fib_entries = 16384;\n\t\tpriv->version = RTL8390_VERSION_A;\n\t\tpriv->n_lags = 16;\n\t\tsw_w32(1, RTL930X_ST_CTRL);\n\t\tpriv->l2_bucket_size = 8;\n\t\tpriv->n_pie_blocks = 16;\n\t\tpriv->port_ignore = 0x3f;\n\t\tpriv->n_counters = 2048;\n\t\tbreak;\n\tcase RTL9310_FAMILY_ID:\n\t\tpriv->ds->ops = &rtl930x_switch_ops;\n\t\tpriv->cpu_port = RTL931X_CPU_PORT;\n\t\tpriv->port_mask = 0x3f;\n\t\tpriv->port_width = 2;\n\t\tpriv->irq_mask = 0xFFFFFFFFFFFFFULL;\n\t\tpriv->r = &rtl931x_reg;\n\t\tpriv->ds->num_ports = 57;\n\t\tpriv->fib_entries = 16384;\n\t\tpriv->version = RTL8390_VERSION_A;\n\t\tpriv->n_lags = 16;\n\t\tpriv->l2_bucket_size = 8;\n\t\tbreak;\n\t}\n\tpr_debug(\"Chip version %c\\n\", priv->version);\n\n\terr = rtl83xx_mdio_probe(priv);\n\tif (err) {\n\t\t/* Probing fails the 1st time because of missing ethernet driver\n\t\t * initialization. Use this to disable traffic in case the bootloader left if on\n\t\t */\n\t\treturn err;\n\t}\n\terr = dsa_register_switch(priv->ds);\n\tif (err) {\n\t\tdev_err(dev, \"Error registering switch: %d\\n\", err);\n\t\treturn err;\n\t}\n\n\t/*\n\t * dsa_to_port returns dsa_port from the port list in\n\t * dsa_switch_tree, the tree is built when the switch\n\t * is registered by dsa_register_switch\n\t */\n\tfor (i = 0; i <= priv->cpu_port; i++)\n\t\tpriv->ports[i].dp = dsa_to_port(priv->ds, i);\n\n\t/* Enable link and media change interrupts. Are the SERDES masks needed? */\n\tsw_w32_mask(0, 3, priv->r->isr_glb_src);\n\n\tpriv->r->set_port_reg_le(priv->irq_mask, priv->r->isr_port_link_sts_chg);\n\tpriv->r->set_port_reg_le(priv->irq_mask, priv->r->imr_port_link_sts_chg);\n\n\tpriv->link_state_irq = platform_get_irq(pdev, 0);\n\tpr_info(\"LINK state irq: %d\\n\", priv->link_state_irq);\n\tswitch (priv->family_id) {\n\tcase RTL8380_FAMILY_ID:\n\t\terr = request_irq(priv->link_state_irq, rtl838x_switch_irq,\n\t\t\t\tIRQF_SHARED, \"rtl838x-link-state\", priv->ds);\n\t\tbreak;\n\tcase RTL8390_FAMILY_ID:\n\t\terr = request_irq(priv->link_state_irq, rtl839x_switch_irq,\n\t\t\t\tIRQF_SHARED, \"rtl839x-link-state\", priv->ds);\n\t\tbreak;\n\tcase RTL9300_FAMILY_ID:\n\t\terr = request_irq(priv->link_state_irq, rtl930x_switch_irq,\n\t\t\t\tIRQF_SHARED, \"rtl930x-link-state\", priv->ds);\n\t\tbreak;\n\tcase RTL9310_FAMILY_ID:\n\t\terr = request_irq(priv->link_state_irq, rtl931x_switch_irq,\n\t\t\t\tIRQF_SHARED, \"rtl931x-link-state\", priv->ds);\n\t\tbreak;\n\t}\n\tif (err) {\n\t\tdev_err(dev, \"Error setting up switch interrupt.\\n\");\n\t\t/* Need to free allocated switch here */\n\t}\n\n\t/* Enable interrupts for switch, on RTL931x, the IRQ is always on globally */\n\tif (soc_info.family != RTL9310_FAMILY_ID)\n\t\tsw_w32(0x1, priv->r->imr_glb);\n\n\trtl83xx_get_l2aging(priv);\n\n\trtl83xx_setup_qos(priv);\n\n\tpriv->r->l3_setup(priv);\n\n\t/* Clear all destination ports for mirror groups */\n\tfor (i = 0; i < 4; i++)\n\t\tpriv->mirror_group_ports[i] = -1;\n\n\t/*\n\t * Register netdevice event callback to catch changes in link aggregation groups\n\t */\n\tpriv->nb.notifier_call = rtl83xx_netdevice_event;\n\tif (register_netdevice_notifier(&priv->nb)) {\n\t\tpriv->nb.notifier_call = NULL;\n\t\tdev_err(dev, \"Failed to register LAG netdev notifier\\n\");\n\t\tgoto err_register_nb;\n\t}\n\n\t// Initialize hash table for L3 routing\n\trhltable_init(&priv->routes, &route_ht_params);\n\n\t/*\n\t * Register netevent notifier callback to catch notifications about neighboring\n\t * changes to update nexthop entries for L3 routing.\n\t */\n\tpriv->ne_nb.notifier_call = rtl83xx_netevent_event;\n\tif (register_netevent_notifier(&priv->ne_nb)) {\n\t\tpriv->ne_nb.notifier_call = NULL;\n\t\tdev_err(dev, \"Failed to register netevent notifier\\n\");\n\t\tgoto err_register_ne_nb;\n\t}\n\n\tpriv->fib_nb.notifier_call = rtl83xx_fib_event;\n\n\t/*\n\t * Register Forwarding Information Base notifier to offload routes where\n\t * where possible\n\t * Only FIBs pointing to our own netdevs are programmed into\n\t * the device, so no need to pass a callback.\n\t */\n\terr = register_fib_notifier(&init_net, &priv->fib_nb, NULL, NULL);\n\tif (err)\n\t\tgoto err_register_fib_nb;\n\n\t// TODO: put this into l2_setup()\n\t// Flood BPDUs to all ports including cpu-port\n\tif (soc_info.family != RTL9300_FAMILY_ID) {\n\t\tbpdu_mask = soc_info.family == RTL8380_FAMILY_ID ? 0x1FFFFFFF : 0x1FFFFFFFFFFFFF;\n\t\tpriv->r->set_port_reg_be(bpdu_mask, priv->r->rma_bpdu_fld_pmask);\n\n\t\t// TRAP 802.1X frames (EAPOL) to the CPU-Port, bypass STP and VLANs\n\t\tsw_w32(7, priv->r->spcl_trap_eapol_ctrl);\n\n\t\trtl838x_dbgfs_init(priv);\n\t} else {\n\t\trtl930x_dbgfs_init(priv);\n\t}\n\n\treturn 0;\n\nerr_register_fib_nb:\n\tunregister_netevent_notifier(&priv->ne_nb);\nerr_register_ne_nb:\n\tunregister_netdevice_notifier(&priv->nb);\nerr_register_nb:\n\treturn err;\n}\n\nstatic int rtl83xx_sw_remove(struct platform_device *pdev)\n{\n\t// TODO:\n\tpr_debug(\"Removing platform driver for rtl83xx-sw\\n\");\n\treturn 0;\n}\n\nstatic const struct of_device_id rtl83xx_switch_of_ids[] = {\n\t{ .compatible = \"realtek,rtl83xx-switch\"},\n\t{ /* sentinel */ }\n};\n\n\nMODULE_DEVICE_TABLE(of, rtl83xx_switch_of_ids);\n\nstatic struct platform_driver rtl83xx_switch_driver = {\n\t.probe = rtl83xx_sw_probe,\n\t.remove = rtl83xx_sw_remove,\n\t.driver = {\n\t\t.name = \"rtl83xx-switch\",\n\t\t.pm = NULL,\n\t\t.of_match_table = rtl83xx_switch_of_ids,\n\t},\n};\n\nmodule_platform_driver(rtl83xx_switch_driver);\n\nMODULE_AUTHOR(\"B. Koblitz\");\nMODULE_DESCRIPTION(\"RTL83XX SoC Switch Driver\");\nMODULE_LICENSE(\"GPL\");\n"
  },
  {
    "path": "target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/debugfs.c",
    "content": "// SPDX-License-Identifier: GPL-2.0-only\n\n#include <linux/debugfs.h>\n#include <linux/kernel.h>\n\n#include <asm/mach-rtl838x/mach-rtl83xx.h>\n#include \"rtl83xx.h\"\n\n#define RTL838X_DRIVER_NAME \"rtl838x\"\n\n#define RTL8380_LED_GLB_CTRL\t\t\t(0xA000)\n#define RTL8380_LED_MODE_SEL\t\t\t(0x1004)\n#define RTL8380_LED_MODE_CTRL\t\t\t(0xA004)\n#define RTL8380_LED_P_EN_CTRL\t\t\t(0xA008)\n#define RTL8380_LED_SW_CTRL\t\t\t(0xA00C)\n#define RTL8380_LED0_SW_P_EN_CTRL\t\t(0xA010)\n#define RTL8380_LED1_SW_P_EN_CTRL\t\t(0xA014)\n#define RTL8380_LED2_SW_P_EN_CTRL\t\t(0xA018)\n#define RTL8380_LED_SW_P_CTRL(p)\t\t(0xA01C + (((p) << 2)))\n\n#define RTL8390_LED_GLB_CTRL\t\t\t(0x00E4)\n#define RTL8390_LED_SET_2_3_CTRL\t\t(0x00E8)\n#define RTL8390_LED_SET_0_1_CTRL\t\t(0x00EC)\n#define RTL8390_LED_COPR_SET_SEL_CTRL(p)\t(0x00F0 + (((p >> 4) << 2)))\n#define RTL8390_LED_FIB_SET_SEL_CTRL(p)\t\t(0x0100 + (((p >> 4) << 2)))\n#define RTL8390_LED_COPR_PMASK_CTRL(p)\t\t(0x0110 + (((p >> 5) << 2)))\n#define RTL8390_LED_FIB_PMASK_CTRL(p)\t\t(0x00118 + (((p >> 5) << 2)))\n#define RTL8390_LED_COMBO_CTRL(p)\t\t(0x0120 + (((p >> 5) << 2)))\n#define RTL8390_LED_SW_CTRL\t\t\t(0x0128)\n#define RTL8390_LED_SW_P_EN_CTRL(p)\t\t(0x012C + (((p / 10) << 2)))\n#define RTL8390_LED_SW_P_CTRL(p)\t\t(0x0144 + (((p) << 2)))\n\n#define RTL838X_MIR_QID_CTRL(grp)\t\t(0xAD44 + (((grp) << 2)))\n#define RTL838X_MIR_RSPAN_VLAN_CTRL(grp)\t(0xA340 + (((grp) << 2)))\n#define RTL838X_MIR_RSPAN_VLAN_CTRL_MAC(grp)\t(0xAA70 + (((grp) << 2)))\n#define RTL838X_MIR_RSPAN_TX_CTRL\t\t(0xA350)\n#define RTL838X_MIR_RSPAN_TX_TAG_RM_CTRL\t(0xAA80)\n#define RTL838X_MIR_RSPAN_TX_TAG_EN_CTRL\t(0xAA84)\n#define RTL839X_MIR_RSPAN_VLAN_CTRL(grp)\t(0xA340 + (((grp) << 2)))\n#define RTL839X_MIR_RSPAN_TX_CTRL\t\t(0x69b0)\n#define RTL839X_MIR_RSPAN_TX_TAG_RM_CTRL\t(0x2550)\n#define RTL839X_MIR_RSPAN_TX_TAG_EN_CTRL\t(0x2554)\n#define RTL839X_MIR_SAMPLE_RATE_CTRL\t\t(0x2558)\n\n#define RTL838X_STAT_PRVTE_DROP_COUNTERS\t(0x6A00)\n#define RTL839X_STAT_PRVTE_DROP_COUNTERS\t(0x3E00)\n#define RTL930X_STAT_PRVTE_DROP_COUNTERS\t(0xB5B8)\n#define RTL931X_STAT_PRVTE_DROP_COUNTERS\t(0xd800)\n\nint rtl83xx_port_get_stp_state(struct rtl838x_switch_priv *priv, int port);\nvoid rtl83xx_port_stp_state_set(struct dsa_switch *ds, int port, u8 state);\nvoid rtl83xx_fast_age(struct dsa_switch *ds, int port);\nu32 rtl838x_get_egress_rate(struct rtl838x_switch_priv *priv, int port);\nu32 rtl839x_get_egress_rate(struct rtl838x_switch_priv *priv, int port);\nint rtl838x_set_egress_rate(struct rtl838x_switch_priv *priv, int port, u32 rate);\nint rtl839x_set_egress_rate(struct rtl838x_switch_priv *priv, int port, u32 rate);\n\n\nconst char *rtl838x_drop_cntr[] = {\n    \"ALE_TX_GOOD_PKTS\", \"MAC_RX_DROP\", \"ACL_FWD_DROP\", \"HW_ATTACK_PREVENTION_DROP\",\n    \"RMA_DROP\", \"VLAN_IGR_FLTR_DROP\", \"INNER_OUTER_CFI_EQUAL_1_DROP\", \"PORT_MOVE_DROP\",\n    \"NEW_SA_DROP\", \"MAC_LIMIT_SYS_DROP\", \"MAC_LIMIT_VLAN_DROP\", \"MAC_LIMIT_PORT_DROP\",\n    \"SWITCH_MAC_DROP\", \"ROUTING_EXCEPTION_DROP\", \"DA_LKMISS_DROP\", \"RSPAN_DROP\",\n    \"ACL_LKMISS_DROP\", \"ACL_DROP\", \"INBW_DROP\", \"IGR_METER_DROP\",\n    \"ACCEPT_FRAME_TYPE_DROP\", \"STP_IGR_DROP\", \"INVALID_SA_DROP\", \"SA_BLOCKING_DROP\",\n    \"DA_BLOCKING_DROP\", \"L2_INVALID_DPM_DROP\", \"MCST_INVALID_DPM_DROP\", \"RX_FLOW_CONTROL_DROP\",\n    \"STORM_SPPRS_DROP\", \"LALS_DROP\", \"VLAN_EGR_FILTER_DROP\", \"STP_EGR_DROP\",\n    \"SRC_PORT_FILTER_DROP\", \"PORT_ISOLATION_DROP\", \"ACL_FLTR_DROP\", \"MIRROR_FLTR_DROP\",\n    \"TX_MAX_DROP\", \"LINK_DOWN_DROP\", \"FLOW_CONTROL_DROP\", \"BRIDGE .1d discards\"\n};\n\nconst char *rtl839x_drop_cntr[] = {\n    \"ALE_TX_GOOD_PKTS\", \"ERROR_PKTS\", \"EGR_ACL_DROP\", \"EGR_METER_DROP\",\n    \"OAM\", \"CFM\" \"VLAN_IGR_FLTR\", \"VLAN_ERR\",\n    \"INNER_OUTER_CFI_EQUAL_1\", \"VLAN_TAG_FORMAT\", \"SRC_PORT_SPENDING_TREE\", \"INBW\",\n    \"RMA\", \"HW_ATTACK_PREVENTION\", \"PROTO_STORM\", \"MCAST_SA\",\n    \"IGR_ACL_DROP\", \"IGR_METER_DROP\", \"DFLT_ACTION_FOR_MISS_ACL_AND_C2SC\", \"NEW_SA\",\n    \"PORT_MOVE\", \"SA_BLOCKING\", \"ROUTING_EXCEPTION\", \"SRC_PORT_SPENDING_TREE_NON_FWDING\",\n    \"MAC_LIMIT\", \"UNKNOW_STORM\", \"MISS_DROP\", \"CPU_MAC_DROP\",\n    \"DA_BLOCKING\", \"SRC_PORT_FILTER_BEFORE_EGR_ACL\", \"VLAN_EGR_FILTER\", \"SPANNING_TRE\",\n    \"PORT_ISOLATION\", \"OAM_EGRESS_DROP\", \"MIRROR_ISOLATION\", \"MAX_LEN_BEFORE_EGR_ACL\",\n    \"SRC_PORT_FILTER_BEFORE_MIRROR\", \"MAX_LEN_BEFORE_MIRROR\", \"SPECIAL_CONGEST_BEFORE_MIRROR\",\n    \"LINK_STATUS_BEFORE_MIRROR\",\n    \"WRED_BEFORE_MIRROR\", \"MAX_LEN_AFTER_MIRROR\", \"SPECIAL_CONGEST_AFTER_MIRROR\",\n    \"LINK_STATUS_AFTER_MIRROR\",\n    \"WRED_AFTER_MIRROR\"\n};\n\nconst char *rtl930x_drop_cntr[] = {\n\t\"OAM_PARSER\", \"UC_RPF\", \"DEI_CFI\", \"MAC_IP_SUBNET_BASED_VLAN\", \"VLAN_IGR_FILTER\",\n\t\"L2_UC_MC\", \"IPV_IP6_MC_BRIDGE\", \"PTP\", \"USER_DEF_0_3\", \"RESERVED\",\n\t\"RESERVED1\", \"RESERVED2\", \"BPDU_RMA\", \"LACP\", \"LLDP\",\n\t\"EAPOL\", \"XX_RMA\", \"L3_IPUC_NON_IP\", \"IP4_IP6_HEADER_ERROR\", \"L3_BAD_IP\",\n\t\"L3_DIP_DMAC_MISMATCH\", \"IP4_IP_OPTION\", \"IP_UC_MC_ROUTING_LOOK_UP_MISS\", \"L3_DST_NULL_INTF\",\n\t\"L3_PBR_NULL_INTF\",\n\t\"HOST_NULL_INTF\", \"ROUTE_NULL_INTF\", \"BRIDGING_ACTION\", \"ROUTING_ACTION\", \"IPMC_RPF\",\n\t\"L2_NEXTHOP_AGE_OUT\", \"L3_UC_TTL_FAIL\", \"L3_MC_TTL_FAIL\", \"L3_UC_MTU_FAIL\", \"L3_MC_MTU_FAIL\",\n\t\"L3_UC_ICMP_REDIR\", \"IP6_MLD_OTHER_ACT\", \"ND\", \"IP_MC_RESERVED\", \"IP6_HBH\",\n\t\"INVALID_SA\", \"L2_HASH_FULL\", \"NEW_SA\", \"PORT_MOVE_FORBID\", \"STATIC_PORT_MOVING\",\n\t\"DYNMIC_PORT_MOVING\", \"L3_CRC\", \"MAC_LIMIT\", \"ATTACK_PREVENT\", \"ACL_FWD_ACTION\",\n\t\"OAMPDU\", \"OAM_MUX\", \"TRUNK_FILTER\", \"ACL_DROP\", \"IGR_BW\",\n\t\"ACL_METER\", \"VLAN_ACCEPT_FRAME_TYPE\", \"MSTP_SRC_DROP_DISABLED_BLOCKING\", \"SA_BLOCK\", \"DA_BLOCK\",\n\t\"STORM_CONTROL\", \"VLAN_EGR_FILTER\", \"MSTP_DESTINATION_DROP\", \"SRC_PORT_FILTER\", \"PORT_ISOLATION\",\n\t\"TX_MAX_FRAME_SIZE\", \"EGR_LINK_STATUS\", \"MAC_TX_DISABLE\", \"MAC_PAUSE_FRAME\", \"MAC_RX_DROP\",\n\t\"MIRROR_ISOLATE\", \"RX_FC\", \"EGR_QUEUE\", \"HSM_RUNOUT\", \"ROUTING_DISABLE\", \"INVALID_L2_NEXTHOP_ENTRY\",\n\t\"L3_MC_SRC_FLT\", \"CPUTAG_FLT\", \"FWD_PMSK_NULL\", \"IPUC_ROUTING_LOOKUP_MISS\", \"MY_DEV_DROP\",\n\t\"STACK_NONUC_BLOCKING_PMSK\", \"STACK_PORT_NOT_FOUND\", \"ACL_LOOPBACK_DROP\", \"IP6_ROUTING_EXT_HEADER\"\n};\n\nconst char *rtl931x_drop_cntr[] = {\n\t\"ALE_RX_GOOD_PKTS\", \"RX_MAX_FRAME_SIZE\", \"MAC_RX_DROP\", \"OPENFLOW_IP_MPLS_TTL\", \"OPENFLOW_TBL_MISS\",\n\t\"IGR_BW\", \"SPECIAL_CONGEST\", \"EGR_QUEUE\", \"RESERVED\", \"EGR_LINK_STATUS\", \"STACK_UCAST_NONUCAST_TTL\", // 10\n\t\"STACK_NONUC_BLOCKING_PMSK\", \"L2_CRC\", \"SRC_PORT_FILTER\", \"PARSER_PACKET_TOO_LONG\", \"PARSER_MALFORM_PACKET\",\n\t\"MPLS_OVER_2_LBL\", \"EACL_METER\", \"IACL_METER\", \"PROTO_STORM\", \"INVALID_CAPWAP_HEADER\", // 20\n\t\"MAC_IP_SUBNET_BASED_VLAN\", \"OAM_PARSER\", \"UC_MC_RPF\", \"IP_MAC_BINDING_MATCH_MISMATCH\", \"SA_BLOCK\",\n\t\"TUNNEL_IP_ADDRESS_CHECK\", \"EACL_DROP\", \"IACL_DROP\", \"ATTACK_PREVENT\", \"SYSTEM_PORT_LIMIT_LEARN\", // 30,\n\t\"OAMPDU\", \"CCM_RX\", \"CFM_UNKNOWN_TYPE\", \"LBM_LBR_LTM_LTR\", \"Y_1731\", \"VLAN_LIMIT_LEARN\",\n\t\"VLAN_ACCEPT_FRAME_TYPE\", \"CFI_1\", \"STATIC_DYNAMIC_PORT_MOVING\", \"PORT_MOVE_FORBID\", // 40\n\t\"L3_CRC\", \"BPDU_PTP_LLDP_EAPOL_RMA\", \"MSTP_SRC_DROP_DISABLED_BLOCKING\", \"INVALID_SA\", \"NEW_SA\",\n\t\"VLAN_IGR_FILTER\", \"IGR_VLAN_CONVERT\", \"GRATUITOUS_ARP\", \"MSTP_SRC_DROP\", \"L2_HASH_FULL\", // 50\n\t\"MPLS_UNKNOWN_LBL\", \"L3_IPUC_NON_IP\", \"TTL\", \"MTU\", \"ICMP_REDIRECT\", \"STORM_CONTROL\", \"L3_DIP_DMAC_MISMATCH\",\n\t\"IP4_IP_OPTION\", \"IP6_HBH_EXT_HEADER\", \"IP4_IP6_HEADER_ERROR\", // 60\n\t\"ROUTING_IP_ADDR_CHECK\", \"ROUTING_EXCEPTION\", \"DA_BLOCK\", \"OAM_MUX\", \"PORT_ISOLATION\", \"VLAN_EGR_FILTER\",\n\t\"MIRROR_ISOLATE\", \"MSTP_DESTINATION_DROP\", \"L2_MC_BRIDGE\", \"IP_UC_MC_ROUTING_LOOK_UP_MISS\", // 70\n\t\"L2_UC\", \"L2_MC\", \"IP4_MC\", \"IP6_MC\", \"L3_UC_MC_ROUTE\", \"UNKNOWN_L2_UC_FLPM\", \"BC_FLPM\",\n\t\"VLAN_PRO_UNKNOWN_L2_MC_FLPM\", \"VLAN_PRO_UNKNOWN_IP4_MC_FLPM\", \"VLAN_PROFILE_UNKNOWN_IP6_MC_FLPM\" // 80,\n};\n\nstatic ssize_t rtl838x_common_read(char __user *buffer, size_t count,\n\t\t\t\t\tloff_t *ppos, unsigned int value)\n{\n\tchar *buf;\n\tssize_t len;\n\n\tif (*ppos != 0)\n\t\treturn 0;\n\n\tbuf = kasprintf(GFP_KERNEL, \"0x%08x\\n\", value);\n\tif (!buf)\n\t\treturn -ENOMEM;\n\n\tif (count < strlen(buf)) {\n\t\tkfree(buf);\n\t\treturn -ENOSPC;\n\t}\n\n\tlen = simple_read_from_buffer(buffer, count, ppos, buf, strlen(buf));\n\tkfree(buf);\n\n\treturn len;\n}\n\nstatic ssize_t rtl838x_common_write(const char __user *buffer, size_t count,\n\t\t\t\t loff_t *ppos, unsigned int *value)\n{\n\tchar b[32];\n\tssize_t len;\n\tint ret;\n\n\tif (*ppos != 0)\n\t\treturn -EINVAL;\n\n\tif (count >= sizeof(b))\n\t\treturn -ENOSPC;\n\n\tlen = simple_write_to_buffer(b, sizeof(b) - 1, ppos,\n\t\t\t\t     buffer, count);\n\tif (len < 0)\n\t\treturn len;\n\n\tb[len] = '\\0';\n\tret = kstrtouint(b, 16, value);\n\tif (ret)\n\t\treturn -EIO;\n\n\treturn len;\n}\n\nstatic ssize_t stp_state_read(struct file *filp, char __user *buffer, size_t count,\n\t\t\t     loff_t *ppos)\n{\n\tstruct rtl838x_port *p = filp->private_data;\n\tstruct dsa_switch *ds = p->dp->ds;\n\tint value = rtl83xx_port_get_stp_state(ds->priv, p->dp->index);\n\n\tif (value < 0)\n\t\treturn -EINVAL;\n\n\treturn rtl838x_common_read(buffer, count, ppos, (u32)value);\n}\n\nstatic ssize_t stp_state_write(struct file *filp, const char __user *buffer,\n\t\t\t\tsize_t count, loff_t *ppos)\n{\n\tstruct rtl838x_port *p = filp->private_data;\n\tu32 value;\n\tsize_t res = rtl838x_common_write(buffer, count, ppos, &value);\n\tif (res < 0)\n\t\treturn res;\n\n\trtl83xx_port_stp_state_set(p->dp->ds, p->dp->index, (u8)value);\n\n\treturn res;\n}\n\nstatic const struct file_operations stp_state_fops = {\n\t.owner = THIS_MODULE,\n\t.open = simple_open,\n\t.read = stp_state_read,\n\t.write = stp_state_write,\n};\n\nstatic ssize_t drop_counter_read(struct file *filp, char __user *buffer, size_t count,\n\t\t\t     loff_t *ppos)\n{\n\tstruct rtl838x_switch_priv *priv = filp->private_data;\n\tint i;\n\tconst char **d;\n\tu32 v;\n\tchar *buf;\n\tint n = 0, len, offset;\n\tint num;\n\n\tswitch (priv->family_id) {\n\tcase RTL8380_FAMILY_ID:\n\t\td = rtl838x_drop_cntr;\n\t\toffset = RTL838X_STAT_PRVTE_DROP_COUNTERS;\n\t\tnum = 40;\n\t\tbreak;\n\tcase RTL8390_FAMILY_ID:\n\t\td = rtl839x_drop_cntr;\n\t\toffset = RTL839X_STAT_PRVTE_DROP_COUNTERS;\n\t\tnum = 45;\n\t\tbreak;\n\tcase RTL9300_FAMILY_ID:\n\t\td = rtl930x_drop_cntr;\n\t\toffset = RTL930X_STAT_PRVTE_DROP_COUNTERS;\n\t\tnum = 85;\n\t\tbreak;\n\tcase RTL9310_FAMILY_ID:\n\t\td = rtl931x_drop_cntr;\n\t\toffset = RTL931X_STAT_PRVTE_DROP_COUNTERS;\n\t\tnum = 81;\n\t\tbreak;\n\t}\n\n\tbuf = kmalloc(30 * num, GFP_KERNEL);\n\tif (!buf)\n\t\treturn -ENOMEM;\n\n\tfor (i = 0; i < num; i++) {\n\t\tv = sw_r32(offset + (i << 2)) & 0xffff;\n\t\tn += sprintf(buf + n, \"%s: %d\\n\", d[i], v);\n\t}\n\n\tif (count < strlen(buf)) {\n\t\tkfree(buf);\n\t\treturn -ENOSPC;\n\t}\n\n\tlen = simple_read_from_buffer(buffer, count, ppos, buf, strlen(buf));\n\tkfree(buf);\n\n\treturn len;\n}\n\nstatic const struct file_operations drop_counter_fops = {\n\t.owner = THIS_MODULE,\n\t.open = simple_open,\n\t.read = drop_counter_read,\n};\n\nstatic ssize_t age_out_read(struct file *filp, char __user *buffer, size_t count,\n\t\t\t     loff_t *ppos)\n{\n\tstruct rtl838x_port *p = filp->private_data;\n\tstruct dsa_switch *ds = p->dp->ds;\n\tstruct rtl838x_switch_priv *priv = ds->priv;\n\tint value = sw_r32(priv->r->l2_port_aging_out);\n\n\tif (value < 0)\n\t\treturn -EINVAL;\n\n\treturn rtl838x_common_read(buffer, count, ppos, (u32)value);\n}\n\nstatic ssize_t age_out_write(struct file *filp, const char __user *buffer,\n\t\t\t\tsize_t count, loff_t *ppos)\n{\n\tstruct rtl838x_port *p = filp->private_data;\n\tu32 value;\n\tsize_t res = rtl838x_common_write(buffer, count, ppos, &value);\n\tif (res < 0)\n\t\treturn res;\n\n\trtl83xx_fast_age(p->dp->ds, p->dp->index);\n\n\treturn res;\n}\n\nstatic const struct file_operations age_out_fops = {\n\t.owner = THIS_MODULE,\n\t.open = simple_open,\n\t.read = age_out_read,\n\t.write = age_out_write,\n};\n\nstatic ssize_t port_egress_rate_read(struct file *filp, char __user *buffer, size_t count,\n\t\t\t\tloff_t *ppos)\n{\n\tstruct rtl838x_port *p = filp->private_data;\n\tstruct dsa_switch *ds = p->dp->ds;\n\tstruct rtl838x_switch_priv *priv = ds->priv;\n\tint value;\n\tif (priv->family_id == RTL8380_FAMILY_ID)\n\t\tvalue = rtl838x_get_egress_rate(priv, p->dp->index);\n\telse\n\t\tvalue = rtl839x_get_egress_rate(priv, p->dp->index);\n\n\tif (value < 0)\n\t\treturn -EINVAL;\n\n\treturn rtl838x_common_read(buffer, count, ppos, (u32)value);\n}\n\nstatic ssize_t port_egress_rate_write(struct file *filp, const char __user *buffer,\n\t\t\t\tsize_t count, loff_t *ppos)\n{\n\tstruct rtl838x_port *p = filp->private_data;\n\tstruct dsa_switch *ds = p->dp->ds;\n\tstruct rtl838x_switch_priv *priv = ds->priv;\n\tu32 value;\n\tsize_t res = rtl838x_common_write(buffer, count, ppos, &value);\n\tif (res < 0)\n\t\treturn res;\n\n\tif (priv->family_id == RTL8380_FAMILY_ID)\n\t\trtl838x_set_egress_rate(priv, p->dp->index, value);\n\telse\n\t\trtl839x_set_egress_rate(priv, p->dp->index, value);\n\n\treturn res;\n}\n\nstatic const struct file_operations port_egress_fops = {\n\t.owner = THIS_MODULE,\n\t.open = simple_open,\n\t.read = port_egress_rate_read,\n\t.write = port_egress_rate_write,\n};\n\n\nstatic const struct debugfs_reg32 port_ctrl_regs[] = {\n\t{ .name = \"port_isolation\", .offset = RTL838X_PORT_ISO_CTRL(0), },\n\t{ .name = \"mac_force_mode\", .offset = RTL838X_MAC_FORCE_MODE_CTRL, },\n};\n\nvoid rtl838x_dbgfs_cleanup(struct rtl838x_switch_priv *priv)\n{\n\tdebugfs_remove_recursive(priv->dbgfs_dir);\n\n//\tkfree(priv->dbgfs_entries);\n}\n\nstatic int rtl838x_dbgfs_port_init(struct dentry *parent, struct rtl838x_switch_priv *priv,\n\t\t\t\t   int port)\n{\n\tstruct dentry *port_dir;\n\tstruct debugfs_regset32 *port_ctrl_regset;\n\n\tport_dir = debugfs_create_dir(priv->ports[port].dp->name, parent);\n\n\tif (priv->family_id == RTL8380_FAMILY_ID) {\n\t\tdebugfs_create_x32(\"storm_rate_uc\", 0644, port_dir,\n\t\t\t\t(u32 *)(RTL838X_SW_BASE + RTL838X_STORM_CTRL_PORT_UC(port)));\n\n\t\tdebugfs_create_x32(\"storm_rate_mc\", 0644, port_dir,\n\t\t\t\t(u32 *)(RTL838X_SW_BASE + RTL838X_STORM_CTRL_PORT_MC(port)));\n\n\t\tdebugfs_create_x32(\"storm_rate_bc\", 0644, port_dir,\n\t\t\t\t(u32 *)(RTL838X_SW_BASE + RTL838X_STORM_CTRL_PORT_BC(port)));\n\n\t\tdebugfs_create_x32(\"vlan_port_tag_sts_ctrl\", 0644, port_dir,\n\t\t\t\t(u32 *)(RTL838X_SW_BASE + RTL838X_VLAN_PORT_TAG_STS_CTRL \n\t\t\t\t+ (port << 2)));\n\t} else {\n\t\tdebugfs_create_x32(\"storm_rate_uc\", 0644, port_dir,\n\t\t\t\t(u32 *)(RTL838X_SW_BASE + RTL839X_STORM_CTRL_PORT_UC_0(port)));\n\n\t\tdebugfs_create_x32(\"storm_rate_mc\", 0644, port_dir,\n\t\t\t\t(u32 *)(RTL838X_SW_BASE + RTL839X_STORM_CTRL_PORT_MC_0(port)));\n\n\t\tdebugfs_create_x32(\"storm_rate_bc\", 0644, port_dir,\n\t\t\t\t(u32 *)(RTL838X_SW_BASE + RTL839X_STORM_CTRL_PORT_BC_0(port)));\n\n\t\tdebugfs_create_x32(\"vlan_port_tag_sts_ctrl\", 0644, port_dir,\n\t\t\t\t(u32 *)(RTL838X_SW_BASE + RTL839X_VLAN_PORT_TAG_STS_CTRL\n\t\t\t\t+ (port << 2)));\n\t}\n\n\tdebugfs_create_u32(\"id\", 0444, port_dir, (u32 *)&priv->ports[port].dp->index);\n\n\tport_ctrl_regset = devm_kzalloc(priv->dev, sizeof(*port_ctrl_regset), GFP_KERNEL);\n\tif (!port_ctrl_regset)\n\t\treturn -ENOMEM;\n\n\tport_ctrl_regset->regs = port_ctrl_regs;\n\tport_ctrl_regset->nregs = ARRAY_SIZE(port_ctrl_regs);\n\tport_ctrl_regset->base = (void *)(RTL838X_SW_BASE + (port << 2));\n\tdebugfs_create_regset32(\"port_ctrl\", 0400, port_dir, port_ctrl_regset);\n\n\tdebugfs_create_file(\"stp_state\", 0600, port_dir, &priv->ports[port], &stp_state_fops);\n\tdebugfs_create_file(\"age_out\", 0600, port_dir, &priv->ports[port], &age_out_fops);\n\tdebugfs_create_file(\"port_egress_rate\", 0600, port_dir, &priv->ports[port],\n\t\t\t    &port_egress_fops);\n\treturn 0;\n}\n\nstatic int rtl838x_dbgfs_leds(struct dentry *parent, struct rtl838x_switch_priv *priv)\n{\n\tstruct dentry *led_dir;\n\tint p;\n\tchar led_sw_p_ctrl_name[20];\n\tchar port_led_name[20];\n\n\tled_dir = debugfs_create_dir(\"led\", parent);\n\n\tif (priv->family_id == RTL8380_FAMILY_ID) {\n\t\tdebugfs_create_x32(\"led_glb_ctrl\", 0644, led_dir,\n\t\t\t\t(u32 *)(RTL838X_SW_BASE + RTL8380_LED_GLB_CTRL));\n\t\tdebugfs_create_x32(\"led_mode_sel\", 0644, led_dir,\n\t\t\t\t(u32 *)(RTL838X_SW_BASE + RTL8380_LED_MODE_SEL));\n\t\tdebugfs_create_x32(\"led_mode_ctrl\", 0644, led_dir,\n\t\t\t\t(u32 *)(RTL838X_SW_BASE + RTL8380_LED_MODE_CTRL));\n\t\tdebugfs_create_x32(\"led_p_en_ctrl\", 0644, led_dir,\n\t\t\t\t(u32 *)(RTL838X_SW_BASE + RTL8380_LED_P_EN_CTRL));\n\t\tdebugfs_create_x32(\"led_sw_ctrl\", 0644, led_dir,\n\t\t\t\t(u32 *)(RTL838X_SW_BASE + RTL8380_LED_SW_CTRL));\n\t\tdebugfs_create_x32(\"led0_sw_p_en_ctrl\", 0644, led_dir,\n\t\t\t\t(u32 *)(RTL838X_SW_BASE + RTL8380_LED0_SW_P_EN_CTRL));\n\t\tdebugfs_create_x32(\"led1_sw_p_en_ctrl\", 0644, led_dir,\n\t\t\t\t(u32 *)(RTL838X_SW_BASE + RTL8380_LED1_SW_P_EN_CTRL));\n\t\tdebugfs_create_x32(\"led2_sw_p_en_ctrl\", 0644, led_dir,\n\t\t\t\t(u32 *)(RTL838X_SW_BASE + RTL8380_LED2_SW_P_EN_CTRL));\n\t\tfor (p = 0; p < 28; p++) {\n\t\t\tsnprintf(led_sw_p_ctrl_name, sizeof(led_sw_p_ctrl_name),\n\t\t\t\t \"led_sw_p_ctrl.%02d\", p);\n\t\t\tdebugfs_create_x32(led_sw_p_ctrl_name, 0644, led_dir,\n\t\t\t\t(u32 *)(RTL838X_SW_BASE + RTL8380_LED_SW_P_CTRL(p)));\n\t\t}\n\t} else if (priv->family_id == RTL8390_FAMILY_ID) {\n\t\tdebugfs_create_x32(\"led_glb_ctrl\", 0644, led_dir,\n\t\t\t\t(u32 *)(RTL838X_SW_BASE + RTL8390_LED_GLB_CTRL));\n\t\tdebugfs_create_x32(\"led_set_2_3\", 0644, led_dir,\n\t\t\t\t(u32 *)(RTL838X_SW_BASE + RTL8390_LED_SET_2_3_CTRL));\n\t\tdebugfs_create_x32(\"led_set_0_1\", 0644, led_dir,\n\t\t\t\t(u32 *)(RTL838X_SW_BASE + RTL8390_LED_SET_0_1_CTRL));\n\t\tfor (p = 0; p < 4; p++) {\n\t\t\tsnprintf(port_led_name, sizeof(port_led_name), \"led_copr_set_sel.%1d\", p);\n\t\t\tdebugfs_create_x32(port_led_name, 0644, led_dir,\n\t\t\t\t(u32 *)(RTL838X_SW_BASE + RTL8390_LED_COPR_SET_SEL_CTRL(p << 4)));\n\t\t\tsnprintf(port_led_name, sizeof(port_led_name), \"led_fib_set_sel.%1d\", p);\n\t\t\tdebugfs_create_x32(port_led_name, 0644, led_dir,\n\t\t\t\t(u32 *)(RTL838X_SW_BASE + RTL8390_LED_FIB_SET_SEL_CTRL(p << 4)));\n\t\t}\n\t\tdebugfs_create_x32(\"led_copr_pmask_ctrl_0\", 0644, led_dir,\n\t\t\t\t(u32 *)(RTL838X_SW_BASE + RTL8390_LED_COPR_PMASK_CTRL(0)));\n\t\tdebugfs_create_x32(\"led_copr_pmask_ctrl_1\", 0644, led_dir,\n\t\t\t\t(u32 *)(RTL838X_SW_BASE + RTL8390_LED_COPR_PMASK_CTRL(32)));\n\t\tdebugfs_create_x32(\"led_fib_pmask_ctrl_0\", 0644, led_dir,\n\t\t\t\t(u32 *)(RTL838X_SW_BASE + RTL8390_LED_FIB_PMASK_CTRL(0)));\n\t\tdebugfs_create_x32(\"led_fib_pmask_ctrl_1\", 0644, led_dir,\n\t\t\t\t(u32 *)(RTL838X_SW_BASE + RTL8390_LED_FIB_PMASK_CTRL(32)));\n\t\tdebugfs_create_x32(\"led_combo_ctrl_0\", 0644, led_dir,\n\t\t\t\t(u32 *)(RTL838X_SW_BASE + RTL8390_LED_COMBO_CTRL(0)));\n\t\tdebugfs_create_x32(\"led_combo_ctrl_1\", 0644, led_dir,\n\t\t\t\t(u32 *)(RTL838X_SW_BASE + RTL8390_LED_COMBO_CTRL(32)));\n\t\tdebugfs_create_x32(\"led_sw_ctrl\", 0644, led_dir,\n\t\t\t\t(u32 *)(RTL838X_SW_BASE + RTL8390_LED_SW_CTRL));\n\t\tfor (p = 0; p < 5; p++) {\n\t\t\tsnprintf(port_led_name, sizeof(port_led_name), \"led_sw_p_en_ctrl.%1d\", p);\n\t\t\tdebugfs_create_x32(port_led_name, 0644, led_dir,\n\t\t\t\t(u32 *)(RTL838X_SW_BASE + RTL8390_LED_SW_P_EN_CTRL(p * 10)));\n\t\t}\n\t\tfor (p = 0; p < 28; p++) {\n\t\t\tsnprintf(port_led_name, sizeof(port_led_name), \"led_sw_p_ctrl.%02d\", p);\n\t\t\tdebugfs_create_x32(port_led_name, 0644, led_dir,\n\t\t\t\t(u32 *)(RTL838X_SW_BASE + RTL8390_LED_SW_P_CTRL(p)));\n\t\t}\n\t}\n\treturn 0;\n}\n\nvoid rtl838x_dbgfs_init(struct rtl838x_switch_priv *priv)\n{\n\tstruct dentry *rtl838x_dir;\n\tstruct dentry *port_dir;\n\tstruct dentry *mirror_dir;\n\tstruct debugfs_regset32 *port_ctrl_regset;\n\tint ret, i;\n\tchar lag_name[10];\n\tchar mirror_name[10];\n\n\tpr_info(\"%s called\\n\", __func__);\n\trtl838x_dir = debugfs_lookup(RTL838X_DRIVER_NAME, NULL);\n\tif (!rtl838x_dir)\n\t\trtl838x_dir = debugfs_create_dir(RTL838X_DRIVER_NAME, NULL);\n\n\tpriv->dbgfs_dir = rtl838x_dir;\n\n\tdebugfs_create_u32(\"soc\", 0444, rtl838x_dir,\n\t\t\t   (u32 *)(RTL838X_SW_BASE + RTL838X_MODEL_NAME_INFO));\n\n\t/* Create one directory per port */\n\tfor (i = 0; i < priv->cpu_port; i++) {\n\t\tif (priv->ports[i].phy) {\n\t\t\tret = rtl838x_dbgfs_port_init(rtl838x_dir, priv, i);\n\t\t\tif (ret)\n\t\t\t\tgoto err;\n\t\t}\n\t}\n\n\t/* Create directory for CPU-port */\n\tport_dir = debugfs_create_dir(\"cpu_port\", rtl838x_dir);\n\tport_ctrl_regset = devm_kzalloc(priv->dev, sizeof(*port_ctrl_regset), GFP_KERNEL);\n\tif (!port_ctrl_regset) {\n\t\tret = -ENOMEM;\n\t\tgoto err;\n\t}\n\n\tport_ctrl_regset->regs = port_ctrl_regs;\n\tport_ctrl_regset->nregs = ARRAY_SIZE(port_ctrl_regs);\n\tport_ctrl_regset->base = (void *)(RTL838X_SW_BASE + (priv->cpu_port << 2));\n\tdebugfs_create_regset32(\"port_ctrl\", 0400, port_dir, port_ctrl_regset);\n\tdebugfs_create_u8(\"id\", 0444, port_dir, &priv->cpu_port);\n\n\t/* Create entries for LAGs */\n\tfor (i = 0; i < priv->n_lags; i++) {\n\t\tsnprintf(lag_name, sizeof(lag_name), \"lag.%02d\", i);\n\t\tif (priv->family_id == RTL8380_FAMILY_ID)\n\t\t\tdebugfs_create_x32(lag_name, 0644, rtl838x_dir,\n\t\t\t\t(u32 *)(RTL838X_SW_BASE + priv->r->trk_mbr_ctr(i)));\n\t\telse\n\t\t\tdebugfs_create_x64(lag_name, 0644, rtl838x_dir,\n\t\t\t\t(u64 *)(RTL838X_SW_BASE + priv->r->trk_mbr_ctr(i)));\n\t}\n\n\t/* Create directories for mirror groups */\n\tfor (i = 0; i < 4; i++) {\n\t\tsnprintf(mirror_name, sizeof(mirror_name), \"mirror.%1d\", i);\n\t\tmirror_dir = debugfs_create_dir(mirror_name, rtl838x_dir);\n\t\tif (priv->family_id == RTL8380_FAMILY_ID) {\n\t\t\tdebugfs_create_x32(\"ctrl\", 0644, mirror_dir,\n\t\t\t\t(u32 *)(RTL838X_SW_BASE + RTL838X_MIR_CTRL + i * 4));\n\t\t\tdebugfs_create_x32(\"ingress_pm\", 0644, mirror_dir,\n\t\t\t\t(u32 *)(RTL838X_SW_BASE + priv->r->mir_spm + i * 4));\n\t\t\tdebugfs_create_x32(\"egress_pm\", 0644, mirror_dir,\n\t\t\t\t(u32 *)(RTL838X_SW_BASE + priv->r->mir_dpm + i * 4));\n\t\t\tdebugfs_create_x32(\"qid\", 0644, mirror_dir,\n\t\t\t\t(u32 *)(RTL838X_SW_BASE + RTL838X_MIR_QID_CTRL(i)));\n\t\t\tdebugfs_create_x32(\"rspan_vlan\", 0644, mirror_dir,\n\t\t\t\t(u32 *)(RTL838X_SW_BASE + RTL838X_MIR_RSPAN_VLAN_CTRL(i)));\n\t\t\tdebugfs_create_x32(\"rspan_vlan_mac\", 0644, mirror_dir,\n\t\t\t\t(u32 *)(RTL838X_SW_BASE + RTL838X_MIR_RSPAN_VLAN_CTRL_MAC(i)));\n\t\t\tdebugfs_create_x32(\"rspan_tx\", 0644, mirror_dir,\n\t\t\t\t(u32 *)(RTL838X_SW_BASE + RTL838X_MIR_RSPAN_TX_CTRL));\n\t\t\tdebugfs_create_x32(\"rspan_tx_tag_rm\", 0644, mirror_dir,\n\t\t\t\t(u32 *)(RTL838X_SW_BASE + RTL838X_MIR_RSPAN_TX_TAG_RM_CTRL));\n\t\t\tdebugfs_create_x32(\"rspan_tx_tag_en\", 0644, mirror_dir,\n\t\t\t\t(u32 *)(RTL838X_SW_BASE + RTL838X_MIR_RSPAN_TX_TAG_EN_CTRL));\n\t\t} else {\n\t\t\tdebugfs_create_x32(\"ctrl\", 0644, mirror_dir,\n\t\t\t\t(u32 *)(RTL838X_SW_BASE + RTL839X_MIR_CTRL + i * 4));\n\t\t\tdebugfs_create_x64(\"ingress_pm\", 0644, mirror_dir,\n\t\t\t\t(u64 *)(RTL838X_SW_BASE + priv->r->mir_spm + i * 8));\n\t\t\tdebugfs_create_x64(\"egress_pm\", 0644, mirror_dir,\n\t\t\t\t(u64 *)(RTL838X_SW_BASE + priv->r->mir_dpm + i * 8));\n\t\t\tdebugfs_create_x32(\"rspan_vlan\", 0644, mirror_dir,\n\t\t\t\t(u32 *)(RTL838X_SW_BASE + RTL839X_MIR_RSPAN_VLAN_CTRL(i)));\n\t\t\tdebugfs_create_x32(\"rspan_tx\", 0644, mirror_dir,\n\t\t\t\t(u32 *)(RTL838X_SW_BASE + RTL839X_MIR_RSPAN_TX_CTRL));\n\t\t\tdebugfs_create_x32(\"rspan_tx_tag_rm\", 0644, mirror_dir,\n\t\t\t\t(u32 *)(RTL838X_SW_BASE + RTL839X_MIR_RSPAN_TX_TAG_RM_CTRL));\n\t\t\tdebugfs_create_x32(\"rspan_tx_tag_en\", 0644, mirror_dir,\n\t\t\t\t(u32 *)(RTL838X_SW_BASE + RTL839X_MIR_RSPAN_TX_TAG_EN_CTRL));\n\t\t\tdebugfs_create_x64(\"sample_rate\", 0644, mirror_dir,\n\t\t\t\t(u64 *)(RTL838X_SW_BASE + RTL839X_MIR_SAMPLE_RATE_CTRL));\n\t\t}\n\t}\n\n\tif (priv->family_id == RTL8380_FAMILY_ID)\n\t\tdebugfs_create_x32(\"bpdu_flood_mask\", 0644, rtl838x_dir,\n\t\t\t\t(u32 *)(RTL838X_SW_BASE + priv->r->rma_bpdu_fld_pmask));\n\telse\n\t\tdebugfs_create_x64(\"bpdu_flood_mask\", 0644, rtl838x_dir,\n\t\t\t\t(u64 *)(RTL838X_SW_BASE + priv->r->rma_bpdu_fld_pmask));\n\n\tif (priv->family_id == RTL8380_FAMILY_ID)\n\t\tdebugfs_create_x32(\"vlan_ctrl\", 0644, rtl838x_dir,\n\t\t\t\t(u32 *)(RTL838X_SW_BASE + RTL838X_VLAN_CTRL));\n\telse\n\t\tdebugfs_create_x32(\"vlan_ctrl\", 0644, rtl838x_dir,\n\t\t\t\t(u32 *)(RTL838X_SW_BASE + RTL839X_VLAN_CTRL));\n\n\tret = rtl838x_dbgfs_leds(rtl838x_dir, priv);\n\tif (ret)\n\t\tgoto err;\n\n\tdebugfs_create_file(\"drop_counters\", 0400, rtl838x_dir, priv, &drop_counter_fops);\n\n\treturn;\nerr:\n\trtl838x_dbgfs_cleanup(priv);\n}\n\nvoid rtl930x_dbgfs_init(struct rtl838x_switch_priv *priv)\n{\n\tstruct dentry *dbg_dir;\n\n\tpr_info(\"%s called\\n\", __func__);\n\tdbg_dir = debugfs_lookup(RTL838X_DRIVER_NAME, NULL);\n\tif (!dbg_dir)\n\t\tdbg_dir = debugfs_create_dir(RTL838X_DRIVER_NAME, NULL);\n\n\tpriv->dbgfs_dir = dbg_dir;\n\n\tdebugfs_create_file(\"drop_counters\", 0400, dbg_dir, priv, &drop_counter_fops);\n}\n"
  },
  {
    "path": "target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/dsa.c",
    "content": "// SPDX-License-Identifier: GPL-2.0-only\n\n#include <net/dsa.h>\n#include <linux/if_bridge.h>\n\n#include <asm/mach-rtl838x/mach-rtl83xx.h>\n#include \"rtl83xx.h\"\n\n\nextern struct rtl83xx_soc_info soc_info;\n\n\nstatic void rtl83xx_init_stats(struct rtl838x_switch_priv *priv)\n{\n\tmutex_lock(&priv->reg_mutex);\n\n\t/* Enable statistics module: all counters plus debug.\n\t * On RTL839x all counters are enabled by default\n\t */\n\tif (priv->family_id == RTL8380_FAMILY_ID)\n\t\tsw_w32_mask(0, 3, RTL838X_STAT_CTRL);\n\n\t/* Reset statistics counters */\n\tsw_w32_mask(0, 1, priv->r->stat_rst);\n\n\tmutex_unlock(&priv->reg_mutex);\n}\n\nstatic void rtl83xx_enable_phy_polling(struct rtl838x_switch_priv *priv)\n{\n\tint i;\n\tu64 v = 0;\n\n\tmsleep(1000);\n\t/* Enable all ports with a PHY, including the SFP-ports */\n\tfor (i = 0; i < priv->cpu_port; i++) {\n\t\tif (priv->ports[i].phy)\n\t\t\tv |= BIT_ULL(i);\n\t}\n\n\tpr_info(\"%s: %16llx\\n\", __func__, v);\n\tpriv->r->set_port_reg_le(v, priv->r->smi_poll_ctrl);\n\n\t/* PHY update complete, there is no global PHY polling enable bit on the 9300 */\n\tif (priv->family_id == RTL8390_FAMILY_ID)\n\t\tsw_w32_mask(0, BIT(7), RTL839X_SMI_GLB_CTRL);\n\telse if(priv->family_id == RTL9300_FAMILY_ID)\n\t\tsw_w32_mask(0, 0x8000, RTL838X_SMI_GLB_CTRL);\n}\n\nconst struct rtl83xx_mib_desc rtl83xx_mib[] = {\n\tMIB_DESC(2, 0xf8, \"ifInOctets\"),\n\tMIB_DESC(2, 0xf0, \"ifOutOctets\"),\n\tMIB_DESC(1, 0xec, \"dot1dTpPortInDiscards\"),\n\tMIB_DESC(1, 0xe8, \"ifInUcastPkts\"),\n\tMIB_DESC(1, 0xe4, \"ifInMulticastPkts\"),\n\tMIB_DESC(1, 0xe0, \"ifInBroadcastPkts\"),\n\tMIB_DESC(1, 0xdc, \"ifOutUcastPkts\"),\n\tMIB_DESC(1, 0xd8, \"ifOutMulticastPkts\"),\n\tMIB_DESC(1, 0xd4, \"ifOutBroadcastPkts\"),\n\tMIB_DESC(1, 0xd0, \"ifOutDiscards\"),\n\tMIB_DESC(1, 0xcc, \".3SingleCollisionFrames\"),\n\tMIB_DESC(1, 0xc8, \".3MultipleCollisionFrames\"),\n\tMIB_DESC(1, 0xc4, \".3DeferredTransmissions\"),\n\tMIB_DESC(1, 0xc0, \".3LateCollisions\"),\n\tMIB_DESC(1, 0xbc, \".3ExcessiveCollisions\"),\n\tMIB_DESC(1, 0xb8, \".3SymbolErrors\"),\n\tMIB_DESC(1, 0xb4, \".3ControlInUnknownOpcodes\"),\n\tMIB_DESC(1, 0xb0, \".3InPauseFrames\"),\n\tMIB_DESC(1, 0xac, \".3OutPauseFrames\"),\n\tMIB_DESC(1, 0xa8, \"DropEvents\"),\n\tMIB_DESC(1, 0xa4, \"tx_BroadcastPkts\"),\n\tMIB_DESC(1, 0xa0, \"tx_MulticastPkts\"),\n\tMIB_DESC(1, 0x9c, \"CRCAlignErrors\"),\n\tMIB_DESC(1, 0x98, \"tx_UndersizePkts\"),\n\tMIB_DESC(1, 0x94, \"rx_UndersizePkts\"),\n\tMIB_DESC(1, 0x90, \"rx_UndersizedropPkts\"),\n\tMIB_DESC(1, 0x8c, \"tx_OversizePkts\"),\n\tMIB_DESC(1, 0x88, \"rx_OversizePkts\"),\n\tMIB_DESC(1, 0x84, \"Fragments\"),\n\tMIB_DESC(1, 0x80, \"Jabbers\"),\n\tMIB_DESC(1, 0x7c, \"Collisions\"),\n\tMIB_DESC(1, 0x78, \"tx_Pkts64Octets\"),\n\tMIB_DESC(1, 0x74, \"rx_Pkts64Octets\"),\n\tMIB_DESC(1, 0x70, \"tx_Pkts65to127Octets\"),\n\tMIB_DESC(1, 0x6c, \"rx_Pkts65to127Octets\"),\n\tMIB_DESC(1, 0x68, \"tx_Pkts128to255Octets\"),\n\tMIB_DESC(1, 0x64, \"rx_Pkts128to255Octets\"),\n\tMIB_DESC(1, 0x60, \"tx_Pkts256to511Octets\"),\n\tMIB_DESC(1, 0x5c, \"rx_Pkts256to511Octets\"),\n\tMIB_DESC(1, 0x58, \"tx_Pkts512to1023Octets\"),\n\tMIB_DESC(1, 0x54, \"rx_Pkts512to1023Octets\"),\n\tMIB_DESC(1, 0x50, \"tx_Pkts1024to1518Octets\"),\n\tMIB_DESC(1, 0x4c, \"rx_StatsPkts1024to1518Octets\"),\n\tMIB_DESC(1, 0x48, \"tx_Pkts1519toMaxOctets\"),\n\tMIB_DESC(1, 0x44, \"rx_Pkts1519toMaxOctets\"),\n\tMIB_DESC(1, 0x40, \"rxMacDiscards\")\n};\n\n\n/* DSA callbacks */\n\n\nstatic enum dsa_tag_protocol rtl83xx_get_tag_protocol(struct dsa_switch *ds,\n\t\t\t\t\t\t      int port,\n\t\t\t\t\t\t      enum dsa_tag_protocol mprot)\n{\n\t/* The switch does not tag the frames, instead internally the header\n\t * structure for each packet is tagged accordingly.\n\t */\n\treturn DSA_TAG_PROTO_TRAILER;\n}\n\n/*\n * Initialize all VLANS\n */\nstatic void rtl83xx_vlan_setup(struct rtl838x_switch_priv *priv)\n{\n\tstruct rtl838x_vlan_info info;\n\tint i;\n\n\tpr_info(\"In %s\\n\", __func__);\n\n\tpriv->r->vlan_profile_setup(0);\n\tpriv->r->vlan_profile_setup(1);\n\tpr_info(\"UNKNOWN_MC_PMASK: %016llx\\n\", priv->r->read_mcast_pmask(UNKNOWN_MC_PMASK));\n\tpriv->r->vlan_profile_dump(0);\n\n\tinfo.fid = 0;\t\t\t// Default Forwarding ID / MSTI\n\tinfo.hash_uc_fid = false;\t// Do not build the L2 lookup hash with FID, but VID\n\tinfo.hash_mc_fid = false;\t// Do the same for Multicast packets\n\tinfo.profile_id = 0;\t\t// Use default Vlan Profile 0\n\tinfo.tagged_ports = 0;\t\t// Initially no port members\n\tif (priv->family_id == RTL9310_FAMILY_ID) {\n\t\tinfo.if_id = 0;\n\t\tinfo.multicast_grp_mask = 0;\n\t\tinfo.l2_tunnel_list_id = -1;\n\t}\n\n\t// Initialize all vlans 0-4095\n\tfor (i = 0; i < MAX_VLANS; i ++)\n\t\tpriv->r->vlan_set_tagged(i, &info);\n\n\t// reset PVIDs; defaults to 1 on reset\n\tfor (i = 0; i <= priv->ds->num_ports; i++) {\n\t\tpriv->r->vlan_port_pvid_set(i, PBVLAN_TYPE_INNER, 0);\n\t\tpriv->r->vlan_port_pvid_set(i, PBVLAN_TYPE_OUTER, 0);\n\t\tpriv->r->vlan_port_pvidmode_set(i, PBVLAN_TYPE_INNER, PBVLAN_MODE_UNTAG_AND_PRITAG);\n\t\tpriv->r->vlan_port_pvidmode_set(i, PBVLAN_TYPE_OUTER, PBVLAN_MODE_UNTAG_AND_PRITAG);\n\t}\n\n\t// Set forwarding action based on inner VLAN tag\n\tfor (i = 0; i < priv->cpu_port; i++)\n\t\tpriv->r->vlan_fwd_on_inner(i, true);\n}\n\nstatic void rtl83xx_setup_bpdu_traps(struct rtl838x_switch_priv *priv)\n{\n\tint i;\n\n\tfor (i = 0; i < priv->cpu_port; i++)\n\t\tpriv->r->set_receive_management_action(i, BPDU, COPY2CPU);\n}\n\nstatic int rtl83xx_setup(struct dsa_switch *ds)\n{\n\tint i;\n\tstruct rtl838x_switch_priv *priv = ds->priv;\n\tu64 port_bitmap = BIT_ULL(priv->cpu_port);\n\n\tpr_debug(\"%s called\\n\", __func__);\n\n\t/* Disable MAC polling the PHY so that we can start configuration */\n\tpriv->r->set_port_reg_le(0ULL, priv->r->smi_poll_ctrl);\n\n\tfor (i = 0; i < ds->num_ports; i++)\n\t\tpriv->ports[i].enable = false;\n\tpriv->ports[priv->cpu_port].enable = true;\n\n\t/* Isolate ports from each other: traffic only CPU <-> port */\n\t/* Setting bit j in register RTL838X_PORT_ISO_CTRL(i) allows\n\t * traffic from source port i to destination port j\n\t */\n\tfor (i = 0; i < priv->cpu_port; i++) {\n\t\tif (priv->ports[i].phy) {\n\t\t\tpriv->r->set_port_reg_be(BIT_ULL(priv->cpu_port) | BIT_ULL(i),\n\t\t\t\t\t      priv->r->port_iso_ctrl(i));\n\t\t\tport_bitmap |= BIT_ULL(i);\n\t\t}\n\t}\n\tpriv->r->set_port_reg_be(port_bitmap, priv->r->port_iso_ctrl(priv->cpu_port));\n\n\tif (priv->family_id == RTL8380_FAMILY_ID)\n\t\trtl838x_print_matrix();\n\telse\n\t\trtl839x_print_matrix();\n\n\trtl83xx_init_stats(priv);\n\n\trtl83xx_vlan_setup(priv);\n\n\trtl83xx_setup_bpdu_traps(priv);\n\n\tds->configure_vlan_while_not_filtering = true;\n\n\tpriv->r->l2_learning_setup();\n\n\t/*\n\t *  Make sure all frames sent to the switch's MAC are trapped to the CPU-port\n\t *  0: FWD, 1: DROP, 2: TRAP2CPU\n\t */\n\tif (priv->family_id == RTL8380_FAMILY_ID)\n\t\tsw_w32(0x2, RTL838X_SPCL_TRAP_SWITCH_MAC_CTRL);\n\telse\n\t\tsw_w32(0x2, RTL839X_SPCL_TRAP_SWITCH_MAC_CTRL);\n\n\t/* Enable MAC Polling PHY again */\n\trtl83xx_enable_phy_polling(priv);\n\tpr_debug(\"Please wait until PHY is settled\\n\");\n\tmsleep(1000);\n\tpriv->r->pie_init(priv);\n\n\treturn 0;\n}\n\nstatic int rtl93xx_setup(struct dsa_switch *ds)\n{\n\tint i;\n\tstruct rtl838x_switch_priv *priv = ds->priv;\n\tu32 port_bitmap = BIT(priv->cpu_port);\n\n\tpr_info(\"%s called\\n\", __func__);\n\n\t/* Disable MAC polling the PHY so that we can start configuration */\n\tif (priv->family_id == RTL9300_FAMILY_ID)\n\t\tsw_w32(0, RTL930X_SMI_POLL_CTRL);\n\n\tif (priv->family_id == RTL9310_FAMILY_ID) {\n\t\tsw_w32(0, RTL931X_SMI_PORT_POLLING_CTRL);\n\t\tsw_w32(0, RTL931X_SMI_PORT_POLLING_CTRL + 4);\n\t}\n\n\t// Disable all ports except CPU port\n\tfor (i = 0; i < ds->num_ports; i++)\n\t\tpriv->ports[i].enable = false;\n\tpriv->ports[priv->cpu_port].enable = true;\n\n\tfor (i = 0; i < priv->cpu_port; i++) {\n\t\tif (priv->ports[i].phy) {\n\t\t\tpriv->r->traffic_set(i, BIT_ULL(priv->cpu_port) | BIT_ULL(i));\n\t\t\tport_bitmap |= BIT_ULL(i);\n\t\t}\n\t}\n\tpriv->r->traffic_set(priv->cpu_port, port_bitmap);\n\n\trtl930x_print_matrix();\n\n\t// TODO: Initialize statistics\n\n\trtl83xx_vlan_setup(priv);\n\n\tds->configure_vlan_while_not_filtering = true;\n\n\tpriv->r->l2_learning_setup();\n\n\trtl83xx_enable_phy_polling(priv);\n\n\tpriv->r->pie_init(priv);\n\n\tpriv->r->led_init(priv);\n\n\treturn 0;\n}\n\nstatic int rtl93xx_get_sds(struct phy_device *phydev)\n{\n\tstruct device *dev = &phydev->mdio.dev;\n\tstruct device_node *dn;\n\tu32 sds_num;\n\n\tif (!dev)\n\t\treturn -1;\n\tif (dev->of_node) {\n\t\tdn = dev->of_node;\n\t\tif (of_property_read_u32(dn, \"sds\", &sds_num))\n\t\t\tsds_num = -1;\n\t} else {\n\t\tdev_err(dev, \"No DT node.\\n\");\n\t\treturn -1;\n\t}\n\n\treturn sds_num;\n}\n\nstatic void rtl83xx_phylink_validate(struct dsa_switch *ds, int port,\n\t\t\t\t     unsigned long *supported,\n\t\t\t\t     struct phylink_link_state *state)\n{\n\tstruct rtl838x_switch_priv *priv = ds->priv;\n\t__ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };\n\n\tpr_debug(\"In %s port %d, state is %d\", __func__, port, state->interface);\n\n\tif (!phy_interface_mode_is_rgmii(state->interface) &&\n\t    state->interface != PHY_INTERFACE_MODE_NA &&\n\t    state->interface != PHY_INTERFACE_MODE_1000BASEX &&\n\t    state->interface != PHY_INTERFACE_MODE_MII &&\n\t    state->interface != PHY_INTERFACE_MODE_REVMII &&\n\t    state->interface != PHY_INTERFACE_MODE_GMII &&\n\t    state->interface != PHY_INTERFACE_MODE_QSGMII &&\n\t    state->interface != PHY_INTERFACE_MODE_INTERNAL &&\n\t    state->interface != PHY_INTERFACE_MODE_SGMII) {\n\t\tbitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);\n\t\tdev_err(ds->dev,\n\t\t\t\"Unsupported interface: %d for port %d\\n\",\n\t\t\tstate->interface, port);\n\t\treturn;\n\t}\n\n\t/* Allow all the expected bits */\n\tphylink_set(mask, Autoneg);\n\tphylink_set_port_modes(mask);\n\tphylink_set(mask, Pause);\n\tphylink_set(mask, Asym_Pause);\n\n\t/* With the exclusion of MII and Reverse MII, we support Gigabit,\n\t * including Half duplex\n\t */\n\tif (state->interface != PHY_INTERFACE_MODE_MII &&\n\t    state->interface != PHY_INTERFACE_MODE_REVMII) {\n\t\tphylink_set(mask, 1000baseT_Full);\n\t\tphylink_set(mask, 1000baseT_Half);\n\t}\n\n\t/* On both the 8380 and 8382, ports 24-27 are SFP ports */\n\tif (port >= 24 && port <= 27 && priv->family_id == RTL8380_FAMILY_ID)\n\t\tphylink_set(mask, 1000baseX_Full);\n\n\t/* On the RTL839x family of SoCs, ports 48 to 51 are SFP ports */\n\tif (port >= 48 && port <= 51 && priv->family_id == RTL8390_FAMILY_ID)\n\t\tphylink_set(mask, 1000baseX_Full);\n\n\tphylink_set(mask, 10baseT_Half);\n\tphylink_set(mask, 10baseT_Full);\n\tphylink_set(mask, 100baseT_Half);\n\tphylink_set(mask, 100baseT_Full);\n\n\tbitmap_and(supported, supported, mask,\n\t\t   __ETHTOOL_LINK_MODE_MASK_NBITS);\n\tbitmap_and(state->advertising, state->advertising, mask,\n\t\t   __ETHTOOL_LINK_MODE_MASK_NBITS);\n}\n\nstatic void rtl93xx_phylink_validate(struct dsa_switch *ds, int port,\n\t\t\t\t     unsigned long *supported,\n\t\t\t\t     struct phylink_link_state *state)\n{\n\tstruct rtl838x_switch_priv *priv = ds->priv;\n\t__ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };\n\n\tpr_debug(\"In %s port %d, state is %d (%s)\", __func__, port, state->interface,\n\t\t phy_modes(state->interface));\n\n\tif (!phy_interface_mode_is_rgmii(state->interface) &&\n\t    state->interface != PHY_INTERFACE_MODE_NA &&\n\t    state->interface != PHY_INTERFACE_MODE_1000BASEX &&\n\t    state->interface != PHY_INTERFACE_MODE_MII &&\n\t    state->interface != PHY_INTERFACE_MODE_REVMII &&\n\t    state->interface != PHY_INTERFACE_MODE_GMII &&\n\t    state->interface != PHY_INTERFACE_MODE_QSGMII &&\n\t    state->interface != PHY_INTERFACE_MODE_XGMII &&\n\t    state->interface != PHY_INTERFACE_MODE_HSGMII &&\n\t    state->interface != PHY_INTERFACE_MODE_10GBASER &&\n\t    state->interface != PHY_INTERFACE_MODE_10GKR &&\n\t    state->interface != PHY_INTERFACE_MODE_USXGMII &&\n\t    state->interface != PHY_INTERFACE_MODE_INTERNAL &&\n\t    state->interface != PHY_INTERFACE_MODE_SGMII) {\n\t\tbitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);\n\t\tdev_err(ds->dev,\n\t\t\t\"Unsupported interface: %d for port %d\\n\",\n\t\t\tstate->interface, port);\n\t\treturn;\n\t}\n\n\t/* Allow all the expected bits */\n\tphylink_set(mask, Autoneg);\n\tphylink_set_port_modes(mask);\n\tphylink_set(mask, Pause);\n\tphylink_set(mask, Asym_Pause);\n\n\t/* With the exclusion of MII and Reverse MII, we support Gigabit,\n\t * including Half duplex\n\t */\n\tif (state->interface != PHY_INTERFACE_MODE_MII &&\n\t    state->interface != PHY_INTERFACE_MODE_REVMII) {\n\t\tphylink_set(mask, 1000baseT_Full);\n\t\tphylink_set(mask, 1000baseT_Half);\n\t}\n\n\t// Internal phys of the RTL93xx family provide 10G\n\tif (priv->ports[port].phy_is_integrated\n\t\t&& state->interface == PHY_INTERFACE_MODE_1000BASEX) {\n\t\tphylink_set(mask, 1000baseX_Full);\n\t} else if (priv->ports[port].phy_is_integrated) {\n\t\tphylink_set(mask, 1000baseX_Full);\n\t\tphylink_set(mask, 10000baseKR_Full);\n\t\tphylink_set(mask, 10000baseSR_Full);\n\t\tphylink_set(mask, 10000baseCR_Full);\n\t}\n\tif (state->interface == PHY_INTERFACE_MODE_INTERNAL) {\n\t\tphylink_set(mask, 1000baseX_Full);\n\t\tphylink_set(mask, 1000baseT_Full);\n\t\tphylink_set(mask, 10000baseKR_Full);\n\t\tphylink_set(mask, 10000baseT_Full);\n\t\tphylink_set(mask, 10000baseSR_Full);\n\t\tphylink_set(mask, 10000baseCR_Full);\n\t}\n\n\tif (state->interface == PHY_INTERFACE_MODE_USXGMII)\n\t\tphylink_set(mask, 10000baseT_Full);\n\n\tphylink_set(mask, 10baseT_Half);\n\tphylink_set(mask, 10baseT_Full);\n\tphylink_set(mask, 100baseT_Half);\n\tphylink_set(mask, 100baseT_Full);\n\n\tbitmap_and(supported, supported, mask,\n\t\t   __ETHTOOL_LINK_MODE_MASK_NBITS);\n\tbitmap_and(state->advertising, state->advertising, mask,\n\t\t   __ETHTOOL_LINK_MODE_MASK_NBITS);\n\tpr_debug(\"%s leaving supported: %*pb\", __func__, __ETHTOOL_LINK_MODE_MASK_NBITS, supported);\n}\n\nstatic int rtl83xx_phylink_mac_link_state(struct dsa_switch *ds, int port,\n\t\t\t\t\t  struct phylink_link_state *state)\n{\n\tstruct rtl838x_switch_priv *priv = ds->priv;\n\tu64 speed;\n\tu64 link;\n\n\tif (port < 0 || port > priv->cpu_port)\n\t\treturn -EINVAL;\n\n\tstate->link = 0;\n\tlink = priv->r->get_port_reg_le(priv->r->mac_link_sts);\n\tif (link & BIT_ULL(port))\n\t\tstate->link = 1;\n\tpr_debug(\"%s: link state port %d: %llx\\n\", __func__, port, link & BIT_ULL(port));\n\n\tstate->duplex = 0;\n\tif (priv->r->get_port_reg_le(priv->r->mac_link_dup_sts) & BIT_ULL(port))\n\t\tstate->duplex = 1;\n\n\tspeed = priv->r->get_port_reg_le(priv->r->mac_link_spd_sts(port));\n\tspeed >>= (port % 16) << 1;\n\tswitch (speed & 0x3) {\n\tcase 0:\n\t\tstate->speed = SPEED_10;\n\t\tbreak;\n\tcase 1:\n\t\tstate->speed = SPEED_100;\n\t\tbreak;\n\tcase 2:\n\t\tstate->speed = SPEED_1000;\n\t\tbreak;\n\tcase 3:\n\t\tif (priv->family_id == RTL9300_FAMILY_ID\n\t\t\t&& (port == 24 || port == 26)) /* Internal serdes */\n\t\t\tstate->speed = SPEED_2500;\n\t\telse\n\t\t\tstate->speed = SPEED_100; /* Is in fact 500Mbit */\n\t}\n\n\tstate->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX);\n\tif (priv->r->get_port_reg_le(priv->r->mac_rx_pause_sts) & BIT_ULL(port))\n\t\tstate->pause |= MLO_PAUSE_RX;\n\tif (priv->r->get_port_reg_le(priv->r->mac_tx_pause_sts) & BIT_ULL(port))\n\t\tstate->pause |= MLO_PAUSE_TX;\n\treturn 1;\n}\n\nstatic int rtl93xx_phylink_mac_link_state(struct dsa_switch *ds, int port,\n\t\t\t\t\t  struct phylink_link_state *state)\n{\n\tstruct rtl838x_switch_priv *priv = ds->priv;\n\tu64 speed;\n\tu64 link;\n\tu64 media;\n\n\tif (port < 0 || port > priv->cpu_port)\n\t\treturn -EINVAL;\n\n\t/*\n\t * On the RTL9300 for at least the RTL8226B PHY, the MAC-side link\n\t * state needs to be read twice in order to read a correct result.\n\t * This would not be necessary for ports connected e.g. to RTL8218D\n\t * PHYs.\n\t */\n\tstate->link = 0;\n\tlink = priv->r->get_port_reg_le(priv->r->mac_link_sts);\n\tlink = priv->r->get_port_reg_le(priv->r->mac_link_sts);\n\tif (link & BIT_ULL(port))\n\t\tstate->link = 1;\n\n\tif (priv->family_id == RTL9310_FAMILY_ID)\n\t\tmedia = priv->r->get_port_reg_le(RTL931X_MAC_LINK_MEDIA_STS);\n\n\tif (priv->family_id == RTL9300_FAMILY_ID)\n\t\tmedia = sw_r32(RTL930X_MAC_LINK_MEDIA_STS);\n\n\tif (media & BIT_ULL(port))\n\t\tstate->link = 1;\n\n\tpr_debug(\"%s: link state port %d: %llx, media %llx\\n\", __func__, port,\n\t\t link & BIT_ULL(port), media);\n\n\tstate->duplex = 0;\n\tif (priv->r->get_port_reg_le(priv->r->mac_link_dup_sts) & BIT_ULL(port))\n\t\tstate->duplex = 1;\n\n\tspeed = priv->r->get_port_reg_le(priv->r->mac_link_spd_sts(port));\n\tspeed >>= (port % 8) << 2;\n\tswitch (speed & 0xf) {\n\tcase 0:\n\t\tstate->speed = SPEED_10;\n\t\tbreak;\n\tcase 1:\n\t\tstate->speed = SPEED_100;\n\t\tbreak;\n\tcase 2:\n\tcase 7:\n\t\tstate->speed = SPEED_1000;\n\t\tbreak;\n\tcase 4:\n\t\tstate->speed = SPEED_10000;\n\t\tbreak;\n\tcase 5:\n\tcase 8:\n\t\tstate->speed = SPEED_2500;\n\t\tbreak;\n\tcase 6:\n\t\tstate->speed = SPEED_5000;\n\t\tbreak;\n\tdefault:\n\t\tpr_err(\"%s: unknown speed: %d\\n\", __func__, (u32)speed & 0xf);\n\t}\n\n\tif (priv->family_id == RTL9310_FAMILY_ID\n\t\t&& (port >= 52 || port <= 55)) { /* Internal serdes */\n\t\t\tstate->speed = SPEED_10000;\n\t\t\tstate->link = 1;\n\t\t\tstate->duplex = 1;\n\t}\n\n\tpr_debug(\"%s: speed is: %d %d\\n\", __func__, (u32)speed & 0xf, state->speed);\n\tstate->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX);\n\tif (priv->r->get_port_reg_le(priv->r->mac_rx_pause_sts) & BIT_ULL(port))\n\t\tstate->pause |= MLO_PAUSE_RX;\n\tif (priv->r->get_port_reg_le(priv->r->mac_tx_pause_sts) & BIT_ULL(port))\n\t\tstate->pause |= MLO_PAUSE_TX;\n\treturn 1;\n}\n\nstatic void rtl83xx_config_interface(int port, phy_interface_t interface)\n{\n\tu32 old, int_shift, sds_shift;\n\n\tswitch (port) {\n\tcase 24:\n\t\tint_shift = 0;\n\t\tsds_shift = 5;\n\t\tbreak;\n\tcase 26:\n\t\tint_shift = 3;\n\t\tsds_shift = 0;\n\t\tbreak;\n\tdefault:\n\t\treturn;\n\t}\n\n\told = sw_r32(RTL838X_SDS_MODE_SEL);\n\tswitch (interface) {\n\tcase PHY_INTERFACE_MODE_1000BASEX:\n\t\tif ((old >> sds_shift & 0x1f) == 4)\n\t\t\treturn;\n\t\tsw_w32_mask(0x7 << int_shift, 1 << int_shift, RTL838X_INT_MODE_CTRL);\n\t\tsw_w32_mask(0x1f << sds_shift, 4 << sds_shift, RTL838X_SDS_MODE_SEL);\n\t\tbreak;\n\tcase PHY_INTERFACE_MODE_SGMII:\n\t\tif ((old >> sds_shift & 0x1f) == 2)\n\t\t\treturn;\n\t\tsw_w32_mask(0x7 << int_shift, 2 << int_shift, RTL838X_INT_MODE_CTRL);\n\t\tsw_w32_mask(0x1f << sds_shift, 2 << sds_shift, RTL838X_SDS_MODE_SEL);\n\t\tbreak;\n\tdefault:\n\t\treturn;\n\t}\n\tpr_debug(\"configured port %d for interface %s\\n\", port, phy_modes(interface));\n}\n\nstatic void rtl83xx_phylink_mac_config(struct dsa_switch *ds, int port,\n\t\t\t\t\tunsigned int mode,\n\t\t\t\t\tconst struct phylink_link_state *state)\n{\n\tstruct rtl838x_switch_priv *priv = ds->priv;\n\tu32 reg;\n\tint speed_bit = priv->family_id == RTL8380_FAMILY_ID ? 4 : 3;\n\n\tpr_debug(\"%s port %d, mode %x\\n\", __func__, port, mode);\n\n\tif (port == priv->cpu_port) {\n\t\t/* Set Speed, duplex, flow control\n\t\t * FORCE_EN | LINK_EN | NWAY_EN | DUP_SEL\n\t\t * | SPD_SEL = 0b10 | FORCE_FC_EN | PHY_MASTER_SLV_MANUAL_EN\n\t\t * | MEDIA_SEL\n\t\t */\n\t\tif (priv->family_id == RTL8380_FAMILY_ID) {\n\t\t\tsw_w32(0x6192F, priv->r->mac_force_mode_ctrl(priv->cpu_port));\n\t\t\t/* allow CRC errors on CPU-port */\n\t\t\tsw_w32_mask(0, 0x8, RTL838X_MAC_PORT_CTRL(priv->cpu_port));\n\t\t} else {\n\t\t\tsw_w32_mask(0, 3, priv->r->mac_force_mode_ctrl(priv->cpu_port));\n\t\t}\n\t\treturn;\n\t}\n\n\treg = sw_r32(priv->r->mac_force_mode_ctrl(port));\n\t/* Auto-Negotiation does not work for MAC in RTL8390 */\n\tif (priv->family_id == RTL8380_FAMILY_ID) {\n\t\tif (mode == MLO_AN_PHY || phylink_autoneg_inband(mode)) {\n\t\t\tpr_debug(\"PHY autonegotiates\\n\");\n\t\t\treg |= RTL838X_NWAY_EN;\n\t\t\tsw_w32(reg, priv->r->mac_force_mode_ctrl(port));\n\t\t\trtl83xx_config_interface(port, state->interface);\n\t\t\treturn;\n\t\t}\n\t}\n\n\tif (mode != MLO_AN_FIXED)\n\t\tpr_debug(\"Fixed state.\\n\");\n\n\t/* Clear id_mode_dis bit, and the existing port mode, let\n\t\t * RGMII_MODE_EN bet set by mac_link_{up,down}  */\n\tif (priv->family_id == RTL8380_FAMILY_ID) {\n\t\treg &= ~(RTL838X_RX_PAUSE_EN | RTL838X_TX_PAUSE_EN);\n\t\tif (state->pause & MLO_PAUSE_TXRX_MASK) {\n\t\t\tif (state->pause & MLO_PAUSE_TX)\n\t\t\t\treg |= RTL838X_TX_PAUSE_EN;\n\t\t\treg |= RTL838X_RX_PAUSE_EN;\n\t\t}\n\t} else if (priv->family_id == RTL8390_FAMILY_ID) {\n\t\treg &= ~(RTL839X_RX_PAUSE_EN | RTL839X_TX_PAUSE_EN);\n\t\tif (state->pause & MLO_PAUSE_TXRX_MASK) {\n\t\t\tif (state->pause & MLO_PAUSE_TX)\n\t\t\t\treg |= RTL839X_TX_PAUSE_EN;\n\t\t\treg |= RTL839X_RX_PAUSE_EN;\n\t\t}\n\t}\n\n\n\treg &= ~(3 << speed_bit);\n\tswitch (state->speed) {\n\tcase SPEED_1000:\n\t\treg |= 2 << speed_bit;\n\t\tbreak;\n\tcase SPEED_100:\n\t\treg |= 1 << speed_bit;\n\t\tbreak;\n\tdefault:\n\t\tbreak; // Ignore, including 10MBit which has a speed value of 0\n\t}\n\n\tif (priv->family_id == RTL8380_FAMILY_ID) {\n\t\treg &= ~(RTL838X_DUPLEX_MODE | RTL838X_FORCE_LINK_EN);\n\t\tif (state->link)\n\t\t\treg |= RTL838X_FORCE_LINK_EN;\n\t\tif (state->duplex == RTL838X_DUPLEX_MODE)\n\t\t\treg |= RTL838X_DUPLEX_MODE;\n\t} else if (priv->family_id == RTL8390_FAMILY_ID) {\n\t\treg &= ~(RTL839X_DUPLEX_MODE | RTL839X_FORCE_LINK_EN);\n\t\tif (state->link)\n\t\t\treg |= RTL839X_FORCE_LINK_EN;\n\t\tif (state->duplex == RTL839X_DUPLEX_MODE)\n\t\t\treg |= RTL839X_DUPLEX_MODE;\n\t}\n\n\t// LAG members must use DUPLEX and we need to enable the link\n\tif (priv->lagmembers & BIT_ULL(port)) {\n\t\tswitch(priv->family_id) {\n\t\tcase RTL8380_FAMILY_ID:\n\t\t\treg |= (RTL838X_DUPLEX_MODE | RTL838X_FORCE_LINK_EN);\n\t\tbreak;\n\t\tcase RTL8390_FAMILY_ID:\n\t\t\treg |= (RTL839X_DUPLEX_MODE | RTL839X_FORCE_LINK_EN);\n\t\tbreak;\n\t\t}\n\t}\n\n\t// Disable AN\n\tif (priv->family_id == RTL8380_FAMILY_ID)\n\t\treg &= ~RTL838X_NWAY_EN;\n\tsw_w32(reg, priv->r->mac_force_mode_ctrl(port));\n}\n\nstatic void rtl931x_phylink_mac_config(struct dsa_switch *ds, int port,\n\t\t\t\t\tunsigned int mode,\n\t\t\t\t\tconst struct phylink_link_state *state)\n{\n\tstruct rtl838x_switch_priv *priv = ds->priv;\n\tint sds_num;\n\tu32 reg, band;\n\n\tsds_num = priv->ports[port].sds_num;\n\tpr_info(\"%s: speed %d sds_num %d\\n\", __func__, state->speed, sds_num);\n\n\tswitch (state->interface) {\n\tcase PHY_INTERFACE_MODE_HSGMII:\n\t\tpr_info(\"%s setting mode PHY_INTERFACE_MODE_HSGMII\\n\", __func__);\n\t\tband = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_HSGMII);\n\t\trtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_HSGMII);\n\t\tband = rtl931x_sds_cmu_band_set(sds_num, true, 62, PHY_INTERFACE_MODE_HSGMII);\n\t\tbreak;\n\tcase PHY_INTERFACE_MODE_1000BASEX:\n\t\tband = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_1000BASEX);\n\t\trtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_1000BASEX);\n\t\tbreak;\n\tcase PHY_INTERFACE_MODE_XGMII:\n\t\tband = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_XGMII);\n\t\trtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_XGMII);\n\t\tbreak;\n\tcase PHY_INTERFACE_MODE_10GBASER:\n\tcase PHY_INTERFACE_MODE_10GKR:\n\t\tband = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_10GBASER);\n\t\trtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_10GBASER);\n\t\tbreak;\n\tcase PHY_INTERFACE_MODE_USXGMII:\n\t\t// Translates to MII_USXGMII_10GSXGMII\n\t\tband = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_USXGMII);\n\t\trtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_USXGMII);\n\t\tbreak;\n\tcase PHY_INTERFACE_MODE_SGMII:\n\t\tpr_info(\"%s setting mode PHY_INTERFACE_MODE_SGMII\\n\", __func__);\n\t\tband = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_SGMII);\n\t\trtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_SGMII);\n\t\tband = rtl931x_sds_cmu_band_set(sds_num, true, 62, PHY_INTERFACE_MODE_SGMII);\n\t\tbreak;\n\tcase PHY_INTERFACE_MODE_QSGMII:\n\t\tband = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_QSGMII);\n\t\trtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_QSGMII);\n\t\tbreak;\n\tdefault:\n\t\tpr_err(\"%s: unknown serdes mode: %s\\n\",\n\t\t\t__func__, phy_modes(state->interface));\n\t\treturn;\n\t}\n\n\treg = sw_r32(priv->r->mac_force_mode_ctrl(port));\n\tpr_info(\"%s reading FORCE_MODE_CTRL: %08x\\n\", __func__, reg);\n\n\treg &= ~(RTL931X_DUPLEX_MODE | RTL931X_FORCE_EN | RTL931X_FORCE_LINK_EN);\n\n\treg &= ~(0xf << 12);\n\treg |= 0x2 << 12; // Set SMI speed to 0x2\n\n\treg |= RTL931X_TX_PAUSE_EN | RTL931X_RX_PAUSE_EN;\n\n\tif (priv->lagmembers & BIT_ULL(port))\n\t\treg |= RTL931X_DUPLEX_MODE;\n\n\tif (state->duplex == DUPLEX_FULL)\n\t\treg |= RTL931X_DUPLEX_MODE;\n\n\tsw_w32(reg, priv->r->mac_force_mode_ctrl(port));\n\n}\n\nstatic void rtl93xx_phylink_mac_config(struct dsa_switch *ds, int port,\n\t\t\t\t\tunsigned int mode,\n\t\t\t\t\tconst struct phylink_link_state *state)\n{\n\tstruct rtl838x_switch_priv *priv = ds->priv;\n\tint sds_num, sds_mode;\n\tu32 reg;\n\n\tpr_info(\"%s port %d, mode %x, phy-mode: %s, speed %d, link %d\\n\", __func__,\n\t\tport, mode, phy_modes(state->interface), state->speed, state->link);\n\n\t// Nothing to be done for the CPU-port\n\tif (port == priv->cpu_port)\n\t\treturn;\n\n\tif (priv->family_id == RTL9310_FAMILY_ID)\n\t\treturn rtl931x_phylink_mac_config(ds, port, mode, state);\n\n\tsds_num = priv->ports[port].sds_num;\n\tpr_info(\"%s SDS is %d\\n\", __func__, sds_num);\n\tif (sds_num >= 0) {\n\t\tswitch (state->interface) {\n\t\tcase PHY_INTERFACE_MODE_HSGMII:\n\t\t\tsds_mode = 0x12;\n\t\t\tbreak;\n\t\tcase PHY_INTERFACE_MODE_1000BASEX:\n\t\t\tsds_mode = 0x04;\n\t\t\tbreak;\n\t\tcase PHY_INTERFACE_MODE_XGMII:\n\t\t\tsds_mode = 0x10;\n\t\t\tbreak;\n\t\tcase PHY_INTERFACE_MODE_10GBASER:\n\t\tcase PHY_INTERFACE_MODE_10GKR:\n\t\t\tsds_mode = 0x1b; // 10G 1000X Auto\n\t\t\tbreak;\n\t\tcase PHY_INTERFACE_MODE_USXGMII:\n\t\t\tsds_mode = 0x0d;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tpr_err(\"%s: unknown serdes mode: %s\\n\",\n\t\t\t       __func__, phy_modes(state->interface));\n\t\t\treturn;\n\t\t}\n\t\tif (state->interface == PHY_INTERFACE_MODE_10GBASER)\n\t\t\trtl9300_serdes_setup(sds_num, state->interface);\n\t}\n\n\treg = sw_r32(priv->r->mac_force_mode_ctrl(port));\n\treg &= ~(0xf << 3);\n\n\tswitch (state->speed) {\n\tcase SPEED_10000:\n\t\treg |= 4 << 3;\n\t\tbreak;\n\tcase SPEED_5000:\n\t\treg |= 6 << 3;\n\t\tbreak;\n\tcase SPEED_2500:\n\t\treg |= 5 << 3;\n\t\tbreak;\n\tcase SPEED_1000:\n\t\treg |= 2 << 3;\n\t\tbreak;\n\tdefault:\n\t\treg |= 2 << 3;\n\t\tbreak;\n\t}\n\n\tif (state->link)\n\t\treg |= RTL930X_FORCE_LINK_EN;\n\n\tif (priv->lagmembers & BIT_ULL(port))\n\t\treg |= RTL930X_DUPLEX_MODE | RTL930X_FORCE_LINK_EN;\n\n\tif (state->duplex == DUPLEX_FULL)\n\t\treg |= RTL930X_DUPLEX_MODE;\n\n\tif (priv->ports[port].phy_is_integrated)\n\t\treg &= ~RTL930X_FORCE_EN; // Clear MAC_FORCE_EN to allow SDS-MAC link\n\telse\n\t\treg |= RTL930X_FORCE_EN;\n\n\tsw_w32(reg, priv->r->mac_force_mode_ctrl(port));\n}\n\nstatic void rtl83xx_phylink_mac_link_down(struct dsa_switch *ds, int port,\n\t\t\t\t     unsigned int mode,\n\t\t\t\t     phy_interface_t interface)\n{\n\tstruct rtl838x_switch_priv *priv = ds->priv;\n\tu32 v;\n\n\t/* Stop TX/RX to port */\n\tsw_w32_mask(0x3, 0, priv->r->mac_port_ctrl(port));\n\n\t// No longer force link\n\tif (priv->family_id == RTL9300_FAMILY_ID)\n\t\tv = RTL930X_FORCE_EN | RTL930X_FORCE_LINK_EN;\n\telse if (priv->family_id == RTL9310_FAMILY_ID)\n\t\tv = RTL931X_FORCE_EN | RTL931X_FORCE_LINK_EN;\n\tsw_w32_mask(v, 0, priv->r->mac_port_ctrl(port));\n}\n\nstatic void rtl93xx_phylink_mac_link_down(struct dsa_switch *ds, int port,\n\t\t\t\t     unsigned int mode,\n\t\t\t\t     phy_interface_t interface)\n{\n\tstruct rtl838x_switch_priv *priv = ds->priv;\n\t/* Stop TX/RX to port */\n\tsw_w32_mask(0x3, 0, priv->r->mac_port_ctrl(port));\n\n\t// No longer force link\n\tsw_w32_mask(3, 0, priv->r->mac_force_mode_ctrl(port));\n}\n\nstatic void rtl83xx_phylink_mac_link_up(struct dsa_switch *ds, int port,\n\t\t\t\t   unsigned int mode,\n\t\t\t\t   phy_interface_t interface,\n\t\t\t\t   struct phy_device *phydev,\n\t\t\t\t   int speed, int duplex,\n\t\t\t\t   bool tx_pause, bool rx_pause)\n{\n\tstruct rtl838x_switch_priv *priv = ds->priv;\n\t/* Restart TX/RX to port */\n\tsw_w32_mask(0, 0x3, priv->r->mac_port_ctrl(port));\n\t// TODO: Set speed/duplex/pauses\n}\n\nstatic void rtl93xx_phylink_mac_link_up(struct dsa_switch *ds, int port,\n\t\t\t\t   unsigned int mode,\n\t\t\t\t   phy_interface_t interface,\n\t\t\t\t   struct phy_device *phydev,\n\t\t\t\t   int speed, int duplex,\n\t\t\t\t   bool tx_pause, bool rx_pause)\n{\n\tstruct rtl838x_switch_priv *priv = ds->priv;\n\n\t/* Restart TX/RX to port */\n\tsw_w32_mask(0, 0x3, priv->r->mac_port_ctrl(port));\n\t// TODO: Set speed/duplex/pauses\n}\n\nstatic void rtl83xx_get_strings(struct dsa_switch *ds,\n\t\t\t\tint port, u32 stringset, u8 *data)\n{\n\tint i;\n\n\tif (stringset != ETH_SS_STATS)\n\t\treturn;\n\n\tfor (i = 0; i < ARRAY_SIZE(rtl83xx_mib); i++)\n\t\tstrncpy(data + i * ETH_GSTRING_LEN, rtl83xx_mib[i].name,\n\t\t\tETH_GSTRING_LEN);\n}\n\nstatic void rtl83xx_get_ethtool_stats(struct dsa_switch *ds, int port,\n\t\t\t\t      uint64_t *data)\n{\n\tstruct rtl838x_switch_priv *priv = ds->priv;\n\tconst struct rtl83xx_mib_desc *mib;\n\tint i;\n\tu64 h;\n\n\tfor (i = 0; i < ARRAY_SIZE(rtl83xx_mib); i++) {\n\t\tmib = &rtl83xx_mib[i];\n\n\t\tdata[i] = sw_r32(priv->r->stat_port_std_mib + (port << 8) + 252 - mib->offset);\n\t\tif (mib->size == 2) {\n\t\t\th = sw_r32(priv->r->stat_port_std_mib + (port << 8) + 248 - mib->offset);\n\t\t\tdata[i] |= h << 32;\n\t\t}\n\t}\n}\n\nstatic int rtl83xx_get_sset_count(struct dsa_switch *ds, int port, int sset)\n{\n\tif (sset != ETH_SS_STATS)\n\t\treturn 0;\n\n\treturn ARRAY_SIZE(rtl83xx_mib);\n}\n\nstatic int rtl83xx_mc_group_alloc(struct rtl838x_switch_priv *priv, int port)\n{\n\tint mc_group = find_first_zero_bit(priv->mc_group_bm, MAX_MC_GROUPS - 1);\n\tu64 portmask;\n\n\tif (mc_group >= MAX_MC_GROUPS - 1)\n\t\treturn -1;\n\n\tif (priv->is_lagmember[port]) {\n\t\tpr_info(\"%s: %d is lag slave. ignore\\n\", __func__, port);\n\t\treturn 0;\n\t}\n\n\tset_bit(mc_group, priv->mc_group_bm);\n\tmc_group++;  // We cannot use group 0, as this is used for lookup miss flooding\n\tportmask = BIT_ULL(port) | BIT_ULL(priv->cpu_port); \n\tpriv->r->write_mcast_pmask(mc_group, portmask);\n\n\treturn mc_group;\n}\n\nstatic u64 rtl83xx_mc_group_add_port(struct rtl838x_switch_priv *priv, int mc_group, int port)\n{\n\tu64 portmask = priv->r->read_mcast_pmask(mc_group);\n\n\tpr_debug(\"%s: %d\\n\", __func__, port);\n\tif (priv->is_lagmember[port]) {\n\t\tpr_info(\"%s: %d is lag slave. ignore\\n\", __func__, port);\n\t\treturn portmask;\n\t}\n\tportmask |= BIT_ULL(port);\n\tpriv->r->write_mcast_pmask(mc_group, portmask);\n\n\treturn portmask;\n}\n\nstatic u64 rtl83xx_mc_group_del_port(struct rtl838x_switch_priv *priv, int mc_group, int port)\n{\n\tu64 portmask = priv->r->read_mcast_pmask(mc_group);\n\n\tpr_debug(\"%s: %d\\n\", __func__, port);\n\tif (priv->is_lagmember[port]) {\n\t\tpr_info(\"%s: %d is lag slave. ignore\\n\", __func__, port);\n\t\treturn portmask;\n\t}\n\tpriv->r->write_mcast_pmask(mc_group, portmask);\n\tif (portmask == BIT_ULL(priv->cpu_port)) {\n\t\tportmask &= ~BIT_ULL(priv->cpu_port);\n\t\tpriv->r->write_mcast_pmask(mc_group, portmask);\n\t\tclear_bit(mc_group, priv->mc_group_bm);\n\t}\n\n\treturn portmask;\n}\n\nstatic void store_mcgroups(struct rtl838x_switch_priv *priv, int port)\n{\n\tint mc_group;\n\n\tfor (mc_group = 0; mc_group < MAX_MC_GROUPS; mc_group++) {\n\t\tu64 portmask = priv->r->read_mcast_pmask(mc_group);\n\t\tif (portmask & BIT_ULL(port)) {\n\t\t\tpriv->mc_group_saves[mc_group] = port;\n\t\t\trtl83xx_mc_group_del_port(priv, mc_group, port);\n\t\t}\n\t}\n}\n\nstatic void load_mcgroups(struct rtl838x_switch_priv *priv, int port)\n{\n\tint mc_group;\n\n\tfor (mc_group = 0; mc_group < MAX_MC_GROUPS; mc_group++) {\n\t\tif (priv->mc_group_saves[mc_group] == port) {\n\t\t\trtl83xx_mc_group_add_port(priv, mc_group, port);\n\t\t\tpriv->mc_group_saves[mc_group] = -1;\n\t\t}\n\t}\n}\n\nstatic int rtl83xx_port_enable(struct dsa_switch *ds, int port,\n\t\t\t\tstruct phy_device *phydev)\n{\n\tstruct rtl838x_switch_priv *priv = ds->priv;\n\tu64 v;\n\n\tpr_debug(\"%s: %x %d\", __func__, (u32) priv, port);\n\tpriv->ports[port].enable = true;\n\n\t/* enable inner tagging on egress, do not keep any tags */\n\tif (priv->family_id == RTL9310_FAMILY_ID)\n\t\tsw_w32(BIT(4), priv->r->vlan_port_tag_sts_ctrl + (port << 2));\n\telse\n\t\tsw_w32(1, priv->r->vlan_port_tag_sts_ctrl + (port << 2));\n\n\tif (dsa_is_cpu_port(ds, port))\n\t\treturn 0;\n\n\t/* add port to switch mask of CPU_PORT */\n\tpriv->r->traffic_enable(priv->cpu_port, port);\n\n\tload_mcgroups(priv, port);\n\n\tif (priv->is_lagmember[port]) {\n\t\tpr_debug(\"%s: %d is lag slave. ignore\\n\", __func__, port);\n\t\treturn 0;\n\t}\n\n\t/* add all other ports in the same bridge to switch mask of port */\n\tv = priv->r->traffic_get(port);\n\tv |= priv->ports[port].pm;\n\tpriv->r->traffic_set(port, v);\n\n\t// TODO: Figure out if this is necessary\n\tif (priv->family_id == RTL9300_FAMILY_ID) {\n\t\tsw_w32_mask(0, BIT(port), RTL930X_L2_PORT_SABLK_CTRL);\n\t\tsw_w32_mask(0, BIT(port), RTL930X_L2_PORT_DABLK_CTRL);\n\t}\n\n\tif (priv->ports[port].sds_num < 0)\n\t\tpriv->ports[port].sds_num = rtl93xx_get_sds(phydev);\n\n\treturn 0;\n}\n\nstatic void rtl83xx_port_disable(struct dsa_switch *ds, int port)\n{\n\tstruct rtl838x_switch_priv *priv = ds->priv;\n\tu64 v;\n\n\tpr_debug(\"%s %x: %d\", __func__, (u32)priv, port);\n\t/* you can only disable user ports */\n\tif (!dsa_is_user_port(ds, port))\n\t\treturn;\n\n\t// BUG: This does not work on RTL931X\n\t/* remove port from switch mask of CPU_PORT */\n\tpriv->r->traffic_disable(priv->cpu_port, port);\n\tstore_mcgroups(priv, port);\n\n\t/* remove all other ports in the same bridge from switch mask of port */\n\tv = priv->r->traffic_get(port);\n\tv &= ~priv->ports[port].pm;\n\tpriv->r->traffic_set(port, v);\n\n\tpriv->ports[port].enable = false;\n}\n\nstatic int rtl83xx_set_mac_eee(struct dsa_switch *ds, int port,\n\t\t\t       struct ethtool_eee *e)\n{\n\tstruct rtl838x_switch_priv *priv = ds->priv;\n\n\tif (e->eee_enabled && !priv->eee_enabled) {\n\t\tpr_info(\"Globally enabling EEE\\n\");\n\t\tpriv->r->init_eee(priv, true);\n\t}\n\n\tpriv->r->port_eee_set(priv, port, e->eee_enabled);\n\n\tif (e->eee_enabled)\n\t\tpr_info(\"Enabled EEE for port %d\\n\", port);\n\telse\n\t\tpr_info(\"Disabled EEE for port %d\\n\", port);\n\treturn 0;\n}\n\nstatic int rtl83xx_get_mac_eee(struct dsa_switch *ds, int port,\n\t\t\t       struct ethtool_eee *e)\n{\n\tstruct rtl838x_switch_priv *priv = ds->priv;\n\n\te->supported = SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Full;\n\n\tpriv->r->eee_port_ability(priv, e, port);\n\n\te->eee_enabled = priv->ports[port].eee_enabled;\n\n\te->eee_active = !!(e->advertised & e->lp_advertised);\n\n\treturn 0;\n}\n\nstatic int rtl93xx_get_mac_eee(struct dsa_switch *ds, int port,\n\t\t\t       struct ethtool_eee *e)\n{\n\tstruct rtl838x_switch_priv *priv = ds->priv;\n\n\te->supported = SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Full\n\t\t\t| SUPPORTED_2500baseX_Full;\n\n\tpriv->r->eee_port_ability(priv, e, port);\n\n\te->eee_enabled = priv->ports[port].eee_enabled;\n\n\te->eee_active = !!(e->advertised & e->lp_advertised);\n\n\treturn 0;\n}\n\nstatic int rtl83xx_set_ageing_time(struct dsa_switch *ds, unsigned int msec)\n{\n\tstruct rtl838x_switch_priv *priv = ds->priv;\n\n\tpriv->r->set_ageing_time(msec);\n\treturn 0;\n}\n\nstatic int rtl83xx_port_bridge_join(struct dsa_switch *ds, int port,\n\t\t\t\t\tstruct net_device *bridge)\n{\n\tstruct rtl838x_switch_priv *priv = ds->priv;\n\tu64 port_bitmap = BIT_ULL(priv->cpu_port), v;\n\tint i;\n\n\tpr_debug(\"%s %x: %d %llx\", __func__, (u32)priv, port, port_bitmap);\n\n\tif (priv->is_lagmember[port]) {\n\t\tpr_debug(\"%s: %d is lag slave. ignore\\n\", __func__, port);\n\t\treturn 0;\n\t}\n\n\tmutex_lock(&priv->reg_mutex);\n\tfor (i = 0; i < ds->num_ports; i++) {\n\t\t/* Add this port to the port matrix of the other ports in the\n\t\t * same bridge. If the port is disabled, port matrix is kept\n\t\t * and not being setup until the port becomes enabled.\n\t\t */\n\t\tif (dsa_is_user_port(ds, i) && !priv->is_lagmember[i] && i != port) {\n\t\t\tif (dsa_to_port(ds, i)->bridge_dev != bridge)\n\t\t\t\tcontinue;\n\t\t\tif (priv->ports[i].enable)\n\t\t\t\tpriv->r->traffic_enable(i, port);\n\n\t\t\tpriv->ports[i].pm |= BIT_ULL(port);\n\t\t\tport_bitmap |= BIT_ULL(i);\n\t\t}\n\t}\n\tload_mcgroups(priv, port);\n\n\t/* Add all other ports to this port matrix. */\n\tif (priv->ports[port].enable) {\n\t\tpriv->r->traffic_enable(priv->cpu_port, port);\n\t\tv = priv->r->traffic_get(port);\n\t\tv |= port_bitmap;\n\t\tpriv->r->traffic_set(port, v);\n\t}\n\tpriv->ports[port].pm |= port_bitmap;\n\tmutex_unlock(&priv->reg_mutex);\n\n\treturn 0;\n}\n\nstatic void rtl83xx_port_bridge_leave(struct dsa_switch *ds, int port,\n\t\t\t\t\tstruct net_device *bridge)\n{\n\tstruct rtl838x_switch_priv *priv = ds->priv;\n\tu64 port_bitmap = BIT_ULL(priv->cpu_port), v;\n\tint i;\n\n\tpr_debug(\"%s %x: %d\", __func__, (u32)priv, port);\n\tmutex_lock(&priv->reg_mutex);\n\tfor (i = 0; i < ds->num_ports; i++) {\n\t\t/* Remove this port from the port matrix of the other ports\n\t\t * in the same bridge. If the port is disabled, port matrix\n\t\t * is kept and not being setup until the port becomes enabled.\n\t\t * And the other port's port matrix cannot be broken when the\n\t\t * other port is still a VLAN-aware port.\n\t\t */\n\t\tif (dsa_is_user_port(ds, i) && i != port) {\n\t\t\tif (dsa_to_port(ds, i)->bridge_dev != bridge)\n\t\t\t\tcontinue;\n\t\t\tif (priv->ports[i].enable)\n\t\t\t\tpriv->r->traffic_disable(i, port);\n\n\t\t\tpriv->ports[i].pm |= BIT_ULL(port);\n\t\t\tport_bitmap &= ~BIT_ULL(i);\n\t\t}\n\t}\n\tstore_mcgroups(priv, port);\n\n\t/* Add all other ports to this port matrix. */\n\tif (priv->ports[port].enable) {\n\t\tv = priv->r->traffic_get(port);\n\t\tv |= port_bitmap;\n\t\tpriv->r->traffic_set(port, v);\n\t}\n\tpriv->ports[port].pm &= ~port_bitmap;\n\n\tmutex_unlock(&priv->reg_mutex);\n}\n\nvoid rtl83xx_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)\n{\n\tu32 msti = 0;\n\tu32 port_state[4];\n\tint index, bit;\n\tint pos = port;\n\tstruct rtl838x_switch_priv *priv = ds->priv;\n\tint n = priv->port_width << 1;\n\n\t/* Ports above or equal CPU port can never be configured */\n\tif (port >= priv->cpu_port)\n\t\treturn;\n\n\tmutex_lock(&priv->reg_mutex);\n\n\t/* For the RTL839x and following, the bits are left-aligned, 838x and 930x\n\t * have 64 bit fields, 839x and 931x have 128 bit fields\n\t */\n\tif (priv->family_id == RTL8390_FAMILY_ID)\n\t\tpos += 12;\n\tif (priv->family_id == RTL9300_FAMILY_ID)\n\t\tpos += 3;\n\tif (priv->family_id == RTL9310_FAMILY_ID)\n\t\tpos += 8;\n\n\tindex = n - (pos >> 4) - 1;\n\tbit = (pos << 1) % 32;\n\n\tpriv->r->stp_get(priv, msti, port_state);\n\n\tpr_debug(\"Current state, port %d: %d\\n\", port, (port_state[index] >> bit) & 3);\n\tport_state[index] &= ~(3 << bit);\n\n\tswitch (state) {\n\tcase BR_STATE_DISABLED: /* 0 */\n\t\tport_state[index] |= (0 << bit);\n\t\tbreak;\n\tcase BR_STATE_BLOCKING:  /* 4 */\n\tcase BR_STATE_LISTENING: /* 1 */\n\t\tport_state[index] |= (1 << bit);\n\t\tbreak;\n\tcase BR_STATE_LEARNING: /* 2 */\n\t\tport_state[index] |= (2 << bit);\n\t\tbreak;\n\tcase BR_STATE_FORWARDING: /* 3*/\n\t\tport_state[index] |= (3 << bit);\n\tdefault:\n\t\tbreak;\n\t}\n\n\tpriv->r->stp_set(priv, msti, port_state);\n\n\tmutex_unlock(&priv->reg_mutex);\n}\n\nvoid rtl83xx_fast_age(struct dsa_switch *ds, int port)\n{\n\tstruct rtl838x_switch_priv *priv = ds->priv;\n\tint s = priv->family_id == RTL8390_FAMILY_ID ? 2 : 0;\n\n\tpr_debug(\"FAST AGE port %d\\n\", port);\n\tmutex_lock(&priv->reg_mutex);\n\t/* RTL838X_L2_TBL_FLUSH_CTRL register bits, 839x has 1 bit larger\n\t * port fields:\n\t * 0-4: Replacing port\n\t * 5-9: Flushed/replaced port\n\t * 10-21: FVID\n\t * 22: Entry types: 1: dynamic, 0: also static\n\t * 23: Match flush port\n\t * 24: Match FVID\n\t * 25: Flush (0) or replace (1) L2 entries\n\t * 26: Status of action (1: Start, 0: Done)\n\t */\n\tsw_w32(1 << (26 + s) | 1 << (23 + s) | port << (5 + (s / 2)), priv->r->l2_tbl_flush_ctrl);\n\n\tdo { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & BIT(26 + s));\n\n\tmutex_unlock(&priv->reg_mutex);\n}\n\nvoid rtl931x_fast_age(struct dsa_switch *ds, int port)\n{\n\tstruct rtl838x_switch_priv *priv = ds->priv;\n\n\tpr_info(\"%s port %d\\n\", __func__, port);\n\tmutex_lock(&priv->reg_mutex);\n\tsw_w32(port << 11, RTL931X_L2_TBL_FLUSH_CTRL + 4);\n\n\tsw_w32(BIT(24) | BIT(28), RTL931X_L2_TBL_FLUSH_CTRL);\n\n\tdo { } while (sw_r32(RTL931X_L2_TBL_FLUSH_CTRL) & BIT (28));\n\n\tmutex_unlock(&priv->reg_mutex);\n}\n\nvoid rtl930x_fast_age(struct dsa_switch *ds, int port)\n{\n\tstruct rtl838x_switch_priv *priv = ds->priv;\n\n\tif (priv->family_id == RTL9310_FAMILY_ID)\n\t\treturn rtl931x_fast_age(ds, port);\n\n\tpr_debug(\"FAST AGE port %d\\n\", port);\n\tmutex_lock(&priv->reg_mutex);\n\tsw_w32(port << 11, RTL930X_L2_TBL_FLUSH_CTRL + 4);\n\n\tsw_w32(BIT(26) | BIT(30), RTL930X_L2_TBL_FLUSH_CTRL);\n\n\tdo { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & BIT(30));\n\n\tmutex_unlock(&priv->reg_mutex);\n}\n\nstatic int rtl83xx_vlan_filtering(struct dsa_switch *ds, int port,\n\t\t\t\t  bool vlan_filtering,\n\t\t\t\t  struct switchdev_trans *trans)\n{\n\tstruct rtl838x_switch_priv *priv = ds->priv;\n\n\tpr_debug(\"%s: port %d\\n\", __func__, port);\n\tmutex_lock(&priv->reg_mutex);\n\n\tif (vlan_filtering) {\n\t\t/* Enable ingress and egress filtering\n\t\t * The VLAN_PORT_IGR_FILTER register uses 2 bits for each port to define\n\t\t * the filter action:\n\t\t * 0: Always Forward\n\t\t * 1: Drop packet\n\t\t * 2: Trap packet to CPU port\n\t\t * The Egress filter used 1 bit per state (0: DISABLED, 1: ENABLED)\n\t\t */\n\t\tif (port != priv->cpu_port)\n\t\t\tpriv->r->set_vlan_igr_filter(port, IGR_DROP);\n\n\t\tpriv->r->set_vlan_egr_filter(port, EGR_ENABLE);\n\t} else {\n\t\t/* Disable ingress and egress filtering */\n\t\tif (port != priv->cpu_port)\n\t\t\tpriv->r->set_vlan_igr_filter(port, IGR_FORWARD);\n\n\t\tpriv->r->set_vlan_egr_filter(port, EGR_DISABLE);\n\t}\n\n\t/* Do we need to do something to the CPU-Port, too? */\n\tmutex_unlock(&priv->reg_mutex);\n\n\treturn 0;\n}\n\nstatic int rtl83xx_vlan_prepare(struct dsa_switch *ds, int port,\n\t\t\t\tconst struct switchdev_obj_port_vlan *vlan)\n{\n\tstruct rtl838x_vlan_info info;\n\tstruct rtl838x_switch_priv *priv = ds->priv;\n\n\tpriv->r->vlan_tables_read(0, &info);\n\n\tpr_debug(\"VLAN 0: Tagged ports %llx, untag %llx, profile %d, MC# %d, UC# %d, FID %x\\n\",\n\t\tinfo.tagged_ports, info.untagged_ports, info.profile_id,\n\t\tinfo.hash_mc_fid, info.hash_uc_fid, info.fid);\n\n\tpriv->r->vlan_tables_read(1, &info);\n\tpr_debug(\"VLAN 1: Tagged ports %llx, untag %llx, profile %d, MC# %d, UC# %d, FID %x\\n\",\n\t\tinfo.tagged_ports, info.untagged_ports, info.profile_id,\n\t\tinfo.hash_mc_fid, info.hash_uc_fid, info.fid);\n\tpriv->r->vlan_set_untagged(1, info.untagged_ports);\n\tpr_debug(\"SET: Untagged ports, VLAN %d: %llx\\n\", 1, info.untagged_ports);\n\n\tpriv->r->vlan_set_tagged(1, &info);\n\tpr_debug(\"SET: Tagged ports, VLAN %d: %llx\\n\", 1, info.tagged_ports);\n\n\treturn 0;\n}\n\nstatic void rtl83xx_vlan_add(struct dsa_switch *ds, int port,\n\t\t\t    const struct switchdev_obj_port_vlan *vlan)\n{\n\tstruct rtl838x_vlan_info info;\n\tstruct rtl838x_switch_priv *priv = ds->priv;\n\tint v;\n\n\tpr_debug(\"%s port %d, vid_end %d, vid_end %d, flags %x\\n\", __func__,\n\t\tport, vlan->vid_begin, vlan->vid_end, vlan->flags);\n\n\tif (vlan->vid_begin > 4095 || vlan->vid_end > 4095) {\n\t\tdev_err(priv->dev, \"VLAN out of range: %d - %d\",\n\t\t\tvlan->vid_begin, vlan->vid_end);\n\t\treturn;\n\t}\n\n\tmutex_lock(&priv->reg_mutex);\n\n\tif (vlan->flags & BRIDGE_VLAN_INFO_PVID) {\n\t\tfor (v = vlan->vid_begin; v <= vlan->vid_end; v++) {\n\t\t\tif (!v)\n\t\t\t\tcontinue;\n\t\t\t/* Set both inner and outer PVID of the port */\n\t\t\tpriv->r->vlan_port_pvid_set(port, PBVLAN_TYPE_INNER, v);\n\t\t\tpriv->r->vlan_port_pvid_set(port, PBVLAN_TYPE_OUTER, v);\n\t\t\tpriv->r->vlan_port_pvidmode_set(port, PBVLAN_TYPE_INNER,\n\t\t\t\t\t\t\tPBVLAN_MODE_UNTAG_AND_PRITAG);\n\t\t\tpriv->r->vlan_port_pvidmode_set(port, PBVLAN_TYPE_OUTER,\n\t\t\t\t\t\t\tPBVLAN_MODE_UNTAG_AND_PRITAG);\n\n\t\t\tpriv->ports[port].pvid = vlan->vid_end;\n\t\t}\n\t}\n\n\tfor (v = vlan->vid_begin; v <= vlan->vid_end; v++) {\n\t\t/* Get port memberships of this vlan */\n\t\tpriv->r->vlan_tables_read(v, &info);\n\n\t\t/* new VLAN? */\n\t\tif (!info.tagged_ports) {\n\t\t\tinfo.fid = 0;\n\t\t\tinfo.hash_mc_fid = false;\n\t\t\tinfo.hash_uc_fid = false;\n\t\t\tinfo.profile_id = 0;\n\t\t}\n\n\t\t/* sanitize untagged_ports - must be a subset */\n\t\tif (info.untagged_ports & ~info.tagged_ports)\n\t\t\tinfo.untagged_ports = 0;\n\n\t\tinfo.tagged_ports |= BIT_ULL(port);\n\t\tif (vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED)\n\t\t\tinfo.untagged_ports |= BIT_ULL(port);\n\n\t\tpriv->r->vlan_set_untagged(v, info.untagged_ports);\n\t\tpr_debug(\"Untagged ports, VLAN %d: %llx\\n\", v, info.untagged_ports);\n\n\t\tpriv->r->vlan_set_tagged(v, &info);\n\t\tpr_debug(\"Tagged ports, VLAN %d: %llx\\n\", v, info.tagged_ports);\n\t}\n\n\tmutex_unlock(&priv->reg_mutex);\n}\n\nstatic int rtl83xx_vlan_del(struct dsa_switch *ds, int port,\n\t\t\t    const struct switchdev_obj_port_vlan *vlan)\n{\n\tstruct rtl838x_vlan_info info;\n\tstruct rtl838x_switch_priv *priv = ds->priv;\n\tint v;\n\tu16 pvid;\n\n\tpr_debug(\"%s: port %d, vid_end %d, vid_end %d, flags %x\\n\", __func__,\n\t\tport, vlan->vid_begin, vlan->vid_end, vlan->flags);\n\n\tif (vlan->vid_begin > 4095 || vlan->vid_end > 4095) {\n\t\tdev_err(priv->dev, \"VLAN out of range: %d - %d\",\n\t\t\tvlan->vid_begin, vlan->vid_end);\n\t\treturn -ENOTSUPP;\n\t}\n\n\tmutex_lock(&priv->reg_mutex);\n\tpvid = priv->ports[port].pvid;\n\n\tfor (v = vlan->vid_begin; v <= vlan->vid_end; v++) {\n\t\t/* Reset to default if removing the current PVID */\n\t\tif (v == pvid) {\n\t\t\tpriv->r->vlan_port_pvid_set(port, PBVLAN_TYPE_INNER, 0);\n\t\t\tpriv->r->vlan_port_pvid_set(port, PBVLAN_TYPE_OUTER, 0);\n\t\t\tpriv->r->vlan_port_pvidmode_set(port, PBVLAN_TYPE_INNER,\n\t\t\t\t\t\t\tPBVLAN_MODE_UNTAG_AND_PRITAG);\n\t\t\tpriv->r->vlan_port_pvidmode_set(port, PBVLAN_TYPE_OUTER,\n\t\t\t\t\t\t\tPBVLAN_MODE_UNTAG_AND_PRITAG);\n\t\t}\n\t\t/* Get port memberships of this vlan */\n\t\tpriv->r->vlan_tables_read(v, &info);\n\n\t\t/* remove port from both tables */\n\t\tinfo.untagged_ports &= (~BIT_ULL(port));\n\t\tinfo.tagged_ports &= (~BIT_ULL(port));\n\n\t\tpriv->r->vlan_set_untagged(v, info.untagged_ports);\n\t\tpr_debug(\"Untagged ports, VLAN %d: %llx\\n\", v, info.untagged_ports);\n\n\t\tpriv->r->vlan_set_tagged(v, &info);\n\t\tpr_debug(\"Tagged ports, VLAN %d: %llx\\n\", v, info.tagged_ports);\n\t}\n\tmutex_unlock(&priv->reg_mutex);\n\n\treturn 0;\n}\n\nstatic void dump_l2_entry(struct rtl838x_l2_entry *e)\n{\n\tpr_info(\"MAC: %02x:%02x:%02x:%02x:%02x:%02x vid: %d, rvid: %d, port: %d, valid: %d\\n\",\n\t\te->mac[0], e->mac[1], e->mac[2], e->mac[3], e->mac[4], e->mac[5],\n\t\te->vid, e->rvid, e->port, e->valid);\n\n\tif (e->type != L2_MULTICAST) {\n\t\tpr_info(\"Type: %d, is_static: %d, is_ip_mc: %d, is_ipv6_mc: %d, block_da: %d\\n\",\n\t\t\te->type, e->is_static, e->is_ip_mc, e->is_ipv6_mc, e->block_da);\n\t\tpr_info(\"  block_sa: %d, susp: %d, nh: %d, age: %d, is_trunk: %d, trunk: %d\\n\",\n\t\te->block_sa, e->suspended, e->next_hop, e->age, e->is_trunk, e->trunk);\n\t}\n\tif (e->type == L2_MULTICAST)\n\t\tpr_info(\"  L2_MULTICAST mc_portmask_index: %d\\n\", e->mc_portmask_index);\n\tif (e->is_ip_mc || e->is_ipv6_mc)\n\t\tpr_info(\"  mc_portmask_index: %d, mc_gip: %d, mc_sip: %d\\n\",\n\t\t\te->mc_portmask_index, e->mc_gip, e->mc_sip);\n\tpr_info(\"  stack_dev: %d\\n\", e->stack_dev);\n\tif (e->next_hop)\n\t\tpr_info(\"  nh_route_id: %d\\n\", e->nh_route_id);\n}\n\nstatic void rtl83xx_setup_l2_uc_entry(struct rtl838x_l2_entry *e, int port, int vid, u64 mac)\n{\n\te->is_ip_mc = e->is_ipv6_mc  = false;\n\te->valid = true;\n\te->age = 3;\n\te->port = port,\n\te->vid = vid;\n\tu64_to_ether_addr(mac, e->mac);\n}\n\nstatic void rtl83xx_setup_l2_mc_entry(struct rtl838x_switch_priv *priv,\n\t\t\t\t      struct rtl838x_l2_entry *e, int vid, u64 mac, int mc_group)\n{\n\te->is_ip_mc = e->is_ipv6_mc  = false;\n\te->valid = true;\n\te->mc_portmask_index = mc_group;\n\te->type = L2_MULTICAST;\n\te->rvid = e->vid = vid;\n\tpr_debug(\"%s: vid: %d, rvid: %d\\n\", __func__, e->vid, e->rvid);\n\tu64_to_ether_addr(mac, e->mac);\n}\n\n/*\n * Uses the seed to identify a hash bucket in the L2 using the derived hash key and then loops\n * over the entries in the bucket until either a matching entry is found or an empty slot\n * Returns the filled in rtl838x_l2_entry and the index in the bucket when an entry was found\n * when an empty slot was found and must exist is false, the index of the slot is returned\n * when no slots are available returns -1\n */\nstatic int rtl83xx_find_l2_hash_entry(struct rtl838x_switch_priv *priv, u64 seed,\n\t\t\t\t     bool must_exist, struct rtl838x_l2_entry *e)\n{\n\tint i, idx = -1;\n\tu32 key = priv->r->l2_hash_key(priv, seed);\n\tu64 entry;\n\n\tpr_debug(\"%s: using key %x, for seed %016llx\\n\", __func__, key, seed);\n\t// Loop over all entries in the hash-bucket and over the second block on 93xx SoCs\n\tfor (i = 0; i < priv->l2_bucket_size; i++) {\n\t\tentry = priv->r->read_l2_entry_using_hash(key, i, e);\n\t\tpr_debug(\"valid %d, mac %016llx\\n\", e->valid, ether_addr_to_u64(&e->mac[0]));\n\t\tif (must_exist && !e->valid)\n\t\t\tcontinue;\n\t\tif (!e->valid || ((entry & 0x0fffffffffffffffULL) == seed)) {\n\t\t\tidx = i > 3 ? ((key >> 14) & 0xffff) | i >> 1 : ((key << 2) | i) & 0xffff;\n\t\t\tbreak;\n\t\t}\n\t}\n\n\treturn idx;\n}\n\n/*\n * Uses the seed to identify an entry in the CAM by looping over all its entries\n * Returns the filled in rtl838x_l2_entry and the index in the CAM when an entry was found\n * when an empty slot was found the index of the slot is returned\n * when no slots are available returns -1\n */\nstatic int rtl83xx_find_l2_cam_entry(struct rtl838x_switch_priv *priv, u64 seed,\n\t\t\t\t     bool must_exist, struct rtl838x_l2_entry *e)\n{\n\tint i, idx = -1;\n\tu64 entry;\n\n\tfor (i = 0; i < 64; i++) {\n\t\tentry = priv->r->read_cam(i, e);\n\t\tif (!must_exist && !e->valid) {\n\t\t\tif (idx < 0) /* First empty entry? */\n\t\t\t\tidx = i;\n\t\t\tbreak;\n\t\t} else if ((entry & 0x0fffffffffffffffULL) == seed) {\n\t\t\tpr_debug(\"Found entry in CAM\\n\");\n\t\t\tidx = i;\n\t\t\tbreak;\n\t\t}\n\t}\n\treturn idx;\n}\n\nstatic int rtl83xx_port_fdb_add(struct dsa_switch *ds, int port,\n\t\t\t\tconst unsigned char *addr, u16 vid)\n{\n\tstruct rtl838x_switch_priv *priv = ds->priv;\n\tu64 mac = ether_addr_to_u64(addr);\n\tstruct rtl838x_l2_entry e;\n\tint err = 0, idx;\n\tu64 seed = priv->r->l2_hash_seed(mac, vid);\n\n\tif (priv->is_lagmember[port]) {\n\t\tpr_debug(\"%s: %d is lag slave. ignore\\n\", __func__, port);\n\t\treturn 0;\n\t}\n\n\tmutex_lock(&priv->reg_mutex);\n\n\tidx = rtl83xx_find_l2_hash_entry(priv, seed, false, &e);\n\n\t// Found an existing or empty entry\n\tif (idx >= 0) {\n\t\trtl83xx_setup_l2_uc_entry(&e, port, vid, mac);\n\t\tpriv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);\n\t\tgoto out;\n\t}\n\n\t// Hash buckets full, try CAM\n\trtl83xx_find_l2_cam_entry(priv, seed, false, &e);\n\n\tif (idx >= 0) {\n\t\trtl83xx_setup_l2_uc_entry(&e, port, vid, mac);\n\t\tpriv->r->write_cam(idx, &e);\n\t\tgoto out;\n\t}\n\n\terr = -ENOTSUPP;\nout:\n\tmutex_unlock(&priv->reg_mutex);\n\treturn err;\n}\n\nstatic int rtl83xx_port_fdb_del(struct dsa_switch *ds, int port,\n\t\t\t   const unsigned char *addr, u16 vid)\n{\n\tstruct rtl838x_switch_priv *priv = ds->priv;\n\tu64 mac = ether_addr_to_u64(addr);\n\tstruct rtl838x_l2_entry e;\n\tint err = 0, idx;\n\tu64 seed = priv->r->l2_hash_seed(mac, vid);\n\n\tpr_info(\"In %s, mac %llx, vid: %d\\n\", __func__, mac, vid);\n\tmutex_lock(&priv->reg_mutex);\n\n\tidx = rtl83xx_find_l2_hash_entry(priv, seed, true, &e);\n\n\tpr_info(\"Found entry index %d, key %d and bucket %d\\n\", idx, idx >> 2, idx & 3);\n\tif (idx >= 0) {\n\t\te.valid = false;\n\t\tdump_l2_entry(&e);\n\t\tpriv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);\n\t\tgoto out;\n\t}\n\n\t/* Check CAM for spillover from hash buckets */\n\trtl83xx_find_l2_cam_entry(priv, seed, true, &e);\n\n\tif (idx >= 0) {\n\t\te.valid = false;\n\t\tpriv->r->write_cam(idx, &e);\n\t\tgoto out;\n\t}\n\terr = -ENOENT;\nout:\n\tmutex_unlock(&priv->reg_mutex);\n\treturn err;\n}\n\nstatic int rtl83xx_port_fdb_dump(struct dsa_switch *ds, int port,\n\t\t\t\t dsa_fdb_dump_cb_t *cb, void *data)\n{\n\tstruct rtl838x_l2_entry e;\n\tstruct rtl838x_switch_priv *priv = ds->priv;\n\tint i;\n\tu32 fid, pkey;\n\tu64 mac;\n\n\tmutex_lock(&priv->reg_mutex);\n\n\tfor (i = 0; i < priv->fib_entries; i++) {\n\t\tpriv->r->read_l2_entry_using_hash(i >> 2, i & 0x3, &e);\n\n\t\tif (!e.valid)\n\t\t\tcontinue;\n\n\t\tif (e.port == port || e.port == RTL930X_PORT_IGNORE) {\n\t\t\tu64 seed;\n\t\t\tu32 key;\n\n\t\t\tfid = ((i >> 2) & 0x3ff) | (e.rvid & ~0x3ff);\n\t\t\tmac = ether_addr_to_u64(&e.mac[0]);\n\t\t\tpkey = priv->r->l2_hash_key(priv, priv->r->l2_hash_seed(mac, fid));\n\t\t\tfid = (pkey & 0x3ff) | (fid & ~0x3ff);\n\t\t\tpr_info(\"-> index %d, key %x, bucket %d, dmac %016llx, fid: %x rvid: %x\\n\",\n\t\t\t\ti, i >> 2, i & 0x3, mac, fid, e.rvid);\n\t\t\tdump_l2_entry(&e);\n\t\t\tseed = priv->r->l2_hash_seed(mac, e.rvid);\n\t\t\tkey = priv->r->l2_hash_key(priv, seed);\n\t\t\tpr_info(\"seed: %016llx, key based on rvid: %08x\\n\", seed, key);\n\t\t\tcb(e.mac, e.vid, e.is_static, data);\n\t\t}\n\t\tif (e.type == L2_MULTICAST) {\n\t\t\tu64 portmask = priv->r->read_mcast_pmask(e.mc_portmask_index);\n\n\t\t\tif (portmask & BIT_ULL(port)) {\n\t\t\t\tdump_l2_entry(&e);\n\t\t\t\tpr_info(\"  PM: %016llx\\n\", portmask);\n\t\t\t}\n\t\t}\n\t}\n\n\tfor (i = 0; i < 64; i++) {\n\t\tpriv->r->read_cam(i, &e);\n\n\t\tif (!e.valid)\n\t\t\tcontinue;\n\n\t\tif (e.port == port)\n\t\t\tcb(e.mac, e.vid, e.is_static, data);\n\t}\n\n\tmutex_unlock(&priv->reg_mutex);\n\treturn 0;\n}\n\nstatic int rtl83xx_port_mdb_prepare(struct dsa_switch *ds, int port,\n\t\t\t\t\tconst struct switchdev_obj_port_mdb *mdb)\n{\n\tstruct rtl838x_switch_priv *priv = ds->priv;\n\n\tif (priv->id >= 0x9300)\n\t\treturn -EOPNOTSUPP;\n\n\treturn 0;\n}\n\nstatic void rtl83xx_port_mdb_add(struct dsa_switch *ds, int port,\n\t\t\tconst struct switchdev_obj_port_mdb *mdb)\n{\n\tstruct rtl838x_switch_priv *priv = ds->priv;\n\tu64 mac = ether_addr_to_u64(mdb->addr);\n\tstruct rtl838x_l2_entry e;\n\tint err = 0, idx;\n\tint vid = mdb->vid;\n\tu64 seed = priv->r->l2_hash_seed(mac, vid);\n\tint mc_group;\n\n\tpr_debug(\"In %s port %d, mac %llx, vid: %d\\n\", __func__, port, mac, vid);\n\n\tif (priv->is_lagmember[port]) {\n\t\tpr_debug(\"%s: %d is lag slave. ignore\\n\", __func__, port);\n\t\treturn;\n\t}\n\n\tmutex_lock(&priv->reg_mutex);\n\n\tidx = rtl83xx_find_l2_hash_entry(priv, seed, false, &e);\n\n\t// Found an existing or empty entry\n\tif (idx >= 0) {\n\t\tif (e.valid) {\n\t\t\tpr_debug(\"Found an existing entry %016llx, mc_group %d\\n\",\n\t\t\t\tether_addr_to_u64(e.mac), e.mc_portmask_index);\n\t\t\trtl83xx_mc_group_add_port(priv, e.mc_portmask_index, port);\n\t\t} else {\n\t\t\tpr_debug(\"New entry for seed %016llx\\n\", seed);\n\t\t\tmc_group = rtl83xx_mc_group_alloc(priv, port);\n\t\t\tif (mc_group < 0) {\n\t\t\t\terr = -ENOTSUPP;\n\t\t\t\tgoto out;\n\t\t\t}\n\t\t\trtl83xx_setup_l2_mc_entry(priv, &e, vid, mac, mc_group);\n\t\t\tpriv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);\n\t\t}\n\t\tgoto out;\n\t}\n\n\t// Hash buckets full, try CAM\n\trtl83xx_find_l2_cam_entry(priv, seed, false, &e);\n\n\tif (idx >= 0) {\n\t\tif (e.valid) {\n\t\t\tpr_debug(\"Found existing CAM entry %016llx, mc_group %d\\n\",\n\t\t\t\t ether_addr_to_u64(e.mac), e.mc_portmask_index);\n\t\t\trtl83xx_mc_group_add_port(priv, e.mc_portmask_index, port);\n\t\t} else {\n\t\t\tpr_debug(\"New entry\\n\");\n\t\t\tmc_group = rtl83xx_mc_group_alloc(priv, port);\n\t\t\tif (mc_group < 0) {\n\t\t\t\terr = -ENOTSUPP;\n\t\t\t\tgoto out;\n\t\t\t}\n\t\t\trtl83xx_setup_l2_mc_entry(priv, &e, vid, mac, mc_group);\n\t\t\tpriv->r->write_cam(idx, &e);\n\t\t}\n\t\tgoto out;\n\t}\n\n\terr = -ENOTSUPP;\nout:\n\tmutex_unlock(&priv->reg_mutex);\n\tif (err)\n\t\tdev_err(ds->dev, \"failed to add MDB entry\\n\");\n}\n\nint rtl83xx_port_mdb_del(struct dsa_switch *ds, int port,\n\t\t\tconst struct switchdev_obj_port_mdb *mdb)\n{\n\tstruct rtl838x_switch_priv *priv = ds->priv;\n\tu64 mac = ether_addr_to_u64(mdb->addr);\n\tstruct rtl838x_l2_entry e;\n\tint err = 0, idx;\n\tint vid = mdb->vid;\n\tu64 seed = priv->r->l2_hash_seed(mac, vid);\n\tu64 portmask;\n\n\tpr_debug(\"In %s, port %d, mac %llx, vid: %d\\n\", __func__, port, mac, vid);\n\n\tif (priv->is_lagmember[port]) {\n\t\tpr_info(\"%s: %d is lag slave. ignore\\n\", __func__, port);\n\t\treturn 0;\n\t}\n\n\tmutex_lock(&priv->reg_mutex);\n\n\tidx = rtl83xx_find_l2_hash_entry(priv, seed, true, &e);\n\n\tpr_debug(\"Found entry index %d, key %d and bucket %d\\n\", idx, idx >> 2, idx & 3);\n\tif (idx >= 0) {\n\t\tportmask = rtl83xx_mc_group_del_port(priv, e.mc_portmask_index, port);\n\t\tif (!portmask) {\n\t\t\te.valid = false;\n\t\t\t// dump_l2_entry(&e);\n\t\t\tpriv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);\n\t\t}\n\t\tgoto out;\n\t}\n\n\t/* Check CAM for spillover from hash buckets */\n\trtl83xx_find_l2_cam_entry(priv, seed, true, &e);\n\n\tif (idx >= 0) {\n\t\tportmask = rtl83xx_mc_group_del_port(priv, e.mc_portmask_index, port);\n\t\tif (!portmask) {\n\t\t\te.valid = false;\n\t\t\t// dump_l2_entry(&e);\n\t\t\tpriv->r->write_cam(idx, &e);\n\t\t}\n\t\tgoto out;\n\t}\n\t// TODO: Re-enable with a newer kernel: err = -ENOENT;\nout:\n\tmutex_unlock(&priv->reg_mutex);\n\treturn err;\n}\n\nstatic int rtl83xx_port_mirror_add(struct dsa_switch *ds, int port,\n\t\t\t\t   struct dsa_mall_mirror_tc_entry *mirror,\n\t\t\t\t   bool ingress)\n{\n\t/* We support 4 mirror groups, one destination port per group */\n\tint group;\n\tstruct rtl838x_switch_priv *priv = ds->priv;\n\tint ctrl_reg, dpm_reg, spm_reg;\t\n\n\tpr_debug(\"In %s\\n\", __func__);\n\n\tfor (group = 0; group < 4; group++) {\n\t\tif (priv->mirror_group_ports[group] == mirror->to_local_port)\n\t\t\tbreak;\n\t}\n\tif (group >= 4) {\n\t\tfor (group = 0; group < 4; group++) {\n\t\t\tif (priv->mirror_group_ports[group] < 0)\n\t\t\t\tbreak;\n\t\t}\n\t}\n\n\tif (group >= 4)\n\t\treturn -ENOSPC;\n\n\tctrl_reg = priv->r->mir_ctrl + group * 4;\n\tdpm_reg = priv->r->mir_dpm + group * 4 * priv->port_width;\n\tspm_reg = priv->r->mir_spm + group * 4 * priv->port_width;\n\n\tpr_debug(\"Using group %d\\n\", group);\n\tmutex_lock(&priv->reg_mutex);\n\n\tif (priv->family_id == RTL8380_FAMILY_ID) {\n\t\t/* Enable mirroring to port across VLANs (bit 11) */\n\t\tsw_w32(1 << 11 | (mirror->to_local_port << 4) | 1, ctrl_reg);\n\t} else {\n\t\t/* Enable mirroring to destination port */\n\t\tsw_w32((mirror->to_local_port << 4) | 1, ctrl_reg);\n\t}\n\n\tif (ingress && (priv->r->get_port_reg_be(spm_reg) & (1ULL << port))) {\n\t\tmutex_unlock(&priv->reg_mutex);\n\t\treturn -EEXIST;\n\t}\n\tif ((!ingress) && (priv->r->get_port_reg_be(dpm_reg) & (1ULL << port))) {\n\t\tmutex_unlock(&priv->reg_mutex);\n\t\treturn -EEXIST;\n\t}\n\n\tif (ingress)\n\t\tpriv->r->mask_port_reg_be(0, 1ULL << port, spm_reg);\n\telse\n\t\tpriv->r->mask_port_reg_be(0, 1ULL << port, dpm_reg);\n\n\tpriv->mirror_group_ports[group] = mirror->to_local_port;\n\tmutex_unlock(&priv->reg_mutex);\n\treturn 0;\n}\n\nstatic void rtl83xx_port_mirror_del(struct dsa_switch *ds, int port,\n\t\t\t\t    struct dsa_mall_mirror_tc_entry *mirror)\n{\n\tint group = 0;\n\tstruct rtl838x_switch_priv *priv = ds->priv;\n\tint ctrl_reg, dpm_reg, spm_reg;\n\n\tpr_debug(\"In %s\\n\", __func__);\n\tfor (group = 0; group < 4; group++) {\n\t\tif (priv->mirror_group_ports[group] == mirror->to_local_port)\n\t\t\tbreak;\n\t}\n\tif (group >= 4)\n\t\treturn;\n\n\tctrl_reg = priv->r->mir_ctrl + group * 4;\n\tdpm_reg = priv->r->mir_dpm + group * 4 * priv->port_width;\n\tspm_reg = priv->r->mir_spm + group * 4 * priv->port_width;\n\n\tmutex_lock(&priv->reg_mutex);\n\tif (mirror->ingress) {\n\t\t/* Ingress, clear source port matrix */\n\t\tpriv->r->mask_port_reg_be(1ULL << port, 0, spm_reg);\n\t} else {\n\t\t/* Egress, clear destination port matrix */\n\t\tpriv->r->mask_port_reg_be(1ULL << port, 0, dpm_reg);\n\t}\n\n\tif (!(sw_r32(spm_reg) || sw_r32(dpm_reg))) {\n\t\tpriv->mirror_group_ports[group] = -1;\n\t\tsw_w32(0, ctrl_reg);\n\t}\n\n\tmutex_unlock(&priv->reg_mutex);\n}\n\nstatic int rtl83xx_port_pre_bridge_flags(struct dsa_switch *ds, int port, unsigned long flags, struct netlink_ext_ack *extack)\n{\n\tstruct rtl838x_switch_priv *priv = ds->priv;\n\tunsigned long features = 0;\n\tpr_debug(\"%s: %d %lX\\n\", __func__, port, flags);\n\tif (priv->r->enable_learning)\n\t\tfeatures |= BR_LEARNING;\n\tif (priv->r->enable_flood)\n\t\tfeatures |= BR_FLOOD;\n\tif (priv->r->enable_mcast_flood)\n\t\tfeatures |= BR_MCAST_FLOOD;\n\tif (priv->r->enable_bcast_flood)\n\t\tfeatures |= BR_BCAST_FLOOD;\n\tif (flags & ~(features))\n\t\treturn -EINVAL;\n\n\treturn 0;\n}\n\nstatic int rtl83xx_port_bridge_flags(struct dsa_switch *ds, int port, unsigned long flags, struct netlink_ext_ack *extack)\n{\n\tstruct rtl838x_switch_priv *priv = ds->priv;\n\n\tpr_debug(\"%s: %d %lX\\n\", __func__, port, flags);\n\tif (priv->r->enable_learning)\n\t\tpriv->r->enable_learning(port, !!(flags & BR_LEARNING));\n\n\tif (priv->r->enable_flood)\n\t\tpriv->r->enable_flood(port, !!(flags & BR_FLOOD));\n\n\tif (priv->r->enable_mcast_flood)\n\t\tpriv->r->enable_mcast_flood(port, !!(flags & BR_MCAST_FLOOD));\n\n\tif (priv->r->enable_bcast_flood)\n\t\tpriv->r->enable_bcast_flood(port, !!(flags & BR_BCAST_FLOOD));\n\n\treturn 0;\n}\n\nstatic bool rtl83xx_lag_can_offload(struct dsa_switch *ds,\n\t\t\t\t      struct net_device *lag,\n\t\t\t\t      struct netdev_lag_upper_info *info)\n{\n\tint id;\n\n\tid = dsa_lag_id(ds->dst, lag);\n\tif (id < 0 || id >= ds->num_lag_ids)\n\t\treturn false;\n\n\tif (info->tx_type != NETDEV_LAG_TX_TYPE_HASH) {\n\t\treturn false;\n\t}\n\tif (info->hash_type != NETDEV_LAG_HASH_L2 && info->hash_type != NETDEV_LAG_HASH_L23)\n\t\treturn false;\n\n\treturn true;\n}\n\nstatic int rtl83xx_port_lag_change(struct dsa_switch *ds, int port)\n{\n\tstruct rtl838x_switch_priv *priv = ds->priv;\n\n\tpr_debug(\"%s: %d\\n\", __func__, port);\n\t// Nothing to be done...\n\n\treturn 0;\n}\n\nstatic int rtl83xx_port_lag_join(struct dsa_switch *ds, int port,\n\t\t\t\t   struct net_device *lag,\n\t\t\t\t   struct netdev_lag_upper_info *info)\n{\n\tstruct rtl838x_switch_priv *priv = ds->priv;\n\tint i, err = 0;\n\n\tif (!rtl83xx_lag_can_offload(ds, lag, info))\n\t\treturn -EOPNOTSUPP;\n\n\tmutex_lock(&priv->reg_mutex);\n\n\tfor (i = 0; i < priv->n_lags; i++) {\n\t\tif ((!priv->lag_devs[i]) || (priv->lag_devs[i] == lag))\n\t\t\tbreak;\n\t}\n\tif (port >= priv->cpu_port) {\n\t\terr = -EINVAL;\n\t\tgoto out;\n\t}\n\tpr_info(\"port_lag_join: group %d, port %d\\n\",i, port);\n\tif (!priv->lag_devs[i])\n\t\tpriv->lag_devs[i] = lag;\n\n\tif (priv->lag_primary[i]==-1) {\n\t\tpriv->lag_primary[i]=port;\n\t} else\n\t\tpriv->is_lagmember[port] = 1;\n\n\tpriv->lagmembers |= (1ULL << port);\n\n\tpr_debug(\"lag_members = %llX\\n\", priv->lagmembers);\n\terr = rtl83xx_lag_add(priv->ds, i, port, info);\n\tif (err) {\n\t\terr = -EINVAL;\n\t\tgoto out;\n\t}\n\nout:\n\tmutex_unlock(&priv->reg_mutex);\n\treturn err;\n\n}\n\nstatic int rtl83xx_port_lag_leave(struct dsa_switch *ds, int port,\n\t\t\t\t    struct net_device *lag)\n{\n\tint i, group = -1, err;\n\tstruct rtl838x_switch_priv *priv = ds->priv;\n\n\tmutex_lock(&priv->reg_mutex);\n\tfor (i=0;i<priv->n_lags;i++) {\n\t\tif (priv->lags_port_members[i] & BIT_ULL(port)) {\n\t\t\tgroup = i;\n\t\t\tbreak;\n\t\t}\n\t}\n\n\tif (group == -1) {\n\t\tpr_info(\"port_lag_leave: port %d is not a member\\n\", port);\n\t\terr = -EINVAL;\n\t\tgoto out;\n\t}\n\n\tif (port >= priv->cpu_port) {\n\t\terr = -EINVAL;\n\t\tgoto out;\n\t}\n\tpr_info(\"port_lag_del: group %d, port %d\\n\",group, port);\n\tpriv->lagmembers &=~ (1ULL << port);\n\tpriv->lag_primary[i] = -1;\n\tpriv->is_lagmember[port] = 0;\n\tpr_debug(\"lag_members = %llX\\n\", priv->lagmembers);\n\terr = rtl83xx_lag_del(priv->ds, group, port);\n\tif (err) {\n\t\terr = -EINVAL;\n\t\tgoto out;\n\t}\n\tif (!priv->lags_port_members[i])\n\t\tpriv->lag_devs[i] = NULL;\n\nout:\n\tmutex_unlock(&priv->reg_mutex);\n\treturn 0;\n}\n\nint dsa_phy_read(struct dsa_switch *ds, int phy_addr, int phy_reg)\n{\n\tu32 val;\n\tu32 offset = 0;\n\tstruct rtl838x_switch_priv *priv = ds->priv;\n\n\tif (phy_addr >= 24 && phy_addr <= 27\n\t\t&& priv->ports[24].phy == PHY_RTL838X_SDS) {\n\t\tif (phy_addr == 26)\n\t\t\toffset = 0x100;\n\t\tval = sw_r32(RTL838X_SDS4_FIB_REG0 + offset + (phy_reg << 2)) & 0xffff;\n\t\treturn val;\n\t}\n\n\tread_phy(phy_addr, 0, phy_reg, &val);\n\treturn val;\n}\n\nint dsa_phy_write(struct dsa_switch *ds, int phy_addr, int phy_reg, u16 val)\n{\n\tu32 offset = 0;\n\tstruct rtl838x_switch_priv *priv = ds->priv;\n\n\tif (phy_addr >= 24 && phy_addr <= 27\n\t     && priv->ports[24].phy == PHY_RTL838X_SDS) {\n\t\tif (phy_addr == 26)\n\t\t\toffset = 0x100;\n\t\tsw_w32(val, RTL838X_SDS4_FIB_REG0 + offset + (phy_reg << 2));\n\t\treturn 0;\n\t}\n\treturn write_phy(phy_addr, 0, phy_reg, val);\n}\n\nconst struct dsa_switch_ops rtl83xx_switch_ops = {\n\t.get_tag_protocol\t= rtl83xx_get_tag_protocol,\n\t.setup\t\t\t= rtl83xx_setup,\n\n\t.phy_read\t\t= dsa_phy_read,\n\t.phy_write\t\t= dsa_phy_write,\n\n\t.phylink_validate\t= rtl83xx_phylink_validate,\n\t.phylink_mac_link_state\t= rtl83xx_phylink_mac_link_state,\n\t.phylink_mac_config\t= rtl83xx_phylink_mac_config,\n\t.phylink_mac_link_down\t= rtl83xx_phylink_mac_link_down,\n\t.phylink_mac_link_up\t= rtl83xx_phylink_mac_link_up,\n\n\t.get_strings\t\t= rtl83xx_get_strings,\n\t.get_ethtool_stats\t= rtl83xx_get_ethtool_stats,\n\t.get_sset_count\t\t= rtl83xx_get_sset_count,\n\n\t.port_enable\t\t= rtl83xx_port_enable,\n\t.port_disable\t\t= rtl83xx_port_disable,\n\n\t.get_mac_eee\t\t= rtl83xx_get_mac_eee,\n\t.set_mac_eee\t\t= rtl83xx_set_mac_eee,\n\n\t.set_ageing_time\t= rtl83xx_set_ageing_time,\n\t.port_bridge_join\t= rtl83xx_port_bridge_join,\n\t.port_bridge_leave\t= rtl83xx_port_bridge_leave,\n\t.port_stp_state_set\t= rtl83xx_port_stp_state_set,\n\t.port_fast_age\t\t= rtl83xx_fast_age,\n\n\t.port_vlan_filtering\t= rtl83xx_vlan_filtering,\n\t.port_vlan_prepare\t= rtl83xx_vlan_prepare,\n\t.port_vlan_add\t\t= rtl83xx_vlan_add,\n\t.port_vlan_del\t\t= rtl83xx_vlan_del,\n\n\t.port_fdb_add\t\t= rtl83xx_port_fdb_add,\n\t.port_fdb_del\t\t= rtl83xx_port_fdb_del,\n\t.port_fdb_dump\t\t= rtl83xx_port_fdb_dump,\n\n\t.port_mdb_prepare\t= rtl83xx_port_mdb_prepare,\n\t.port_mdb_add\t\t= rtl83xx_port_mdb_add,\n\t.port_mdb_del\t\t= rtl83xx_port_mdb_del,\n\n\t.port_mirror_add\t= rtl83xx_port_mirror_add,\n\t.port_mirror_del\t= rtl83xx_port_mirror_del,\n\n\t.port_lag_change\t= rtl83xx_port_lag_change,\n\t.port_lag_join\t\t= rtl83xx_port_lag_join,\n\t.port_lag_leave\t\t= rtl83xx_port_lag_leave,\n\n\t.port_pre_bridge_flags\t= rtl83xx_port_pre_bridge_flags,\n\t.port_bridge_flags\t= rtl83xx_port_bridge_flags,\n};\n\nconst struct dsa_switch_ops rtl930x_switch_ops = {\n\t.get_tag_protocol\t= rtl83xx_get_tag_protocol,\n\t.setup\t\t\t= rtl93xx_setup,\n\n\t.phy_read\t\t= dsa_phy_read,\n\t.phy_write\t\t= dsa_phy_write,\n\n\t.phylink_validate\t= rtl93xx_phylink_validate,\n\t.phylink_mac_link_state\t= rtl93xx_phylink_mac_link_state,\n\t.phylink_mac_config\t= rtl93xx_phylink_mac_config,\n\t.phylink_mac_link_down\t= rtl93xx_phylink_mac_link_down,\n\t.phylink_mac_link_up\t= rtl93xx_phylink_mac_link_up,\n\n\t.get_strings\t\t= rtl83xx_get_strings,\n\t.get_ethtool_stats\t= rtl83xx_get_ethtool_stats,\n\t.get_sset_count\t\t= rtl83xx_get_sset_count,\n\n\t.port_enable\t\t= rtl83xx_port_enable,\n\t.port_disable\t\t= rtl83xx_port_disable,\n\n\t.get_mac_eee\t\t= rtl93xx_get_mac_eee,\n\t.set_mac_eee\t\t= rtl83xx_set_mac_eee,\n\n\t.set_ageing_time\t= rtl83xx_set_ageing_time,\n\t.port_bridge_join\t= rtl83xx_port_bridge_join,\n\t.port_bridge_leave\t= rtl83xx_port_bridge_leave,\n\t.port_stp_state_set\t= rtl83xx_port_stp_state_set,\n\t.port_fast_age\t\t= rtl930x_fast_age,\n\n\t.port_vlan_filtering\t= rtl83xx_vlan_filtering,\n\t.port_vlan_prepare\t= rtl83xx_vlan_prepare,\n\t.port_vlan_add\t\t= rtl83xx_vlan_add,\n\t.port_vlan_del\t\t= rtl83xx_vlan_del,\n\n\t.port_fdb_add\t\t= rtl83xx_port_fdb_add,\n\t.port_fdb_del\t\t= rtl83xx_port_fdb_del,\n\t.port_fdb_dump\t\t= rtl83xx_port_fdb_dump,\n\n\t.port_mdb_prepare\t= rtl83xx_port_mdb_prepare,\n\t.port_mdb_add\t\t= rtl83xx_port_mdb_add,\n\t.port_mdb_del\t\t= rtl83xx_port_mdb_del,\n\n\t.port_lag_change\t= rtl83xx_port_lag_change,\n\t.port_lag_join\t\t= rtl83xx_port_lag_join,\n\t.port_lag_leave\t\t= rtl83xx_port_lag_leave,\n\n\t.port_pre_bridge_flags\t= rtl83xx_port_pre_bridge_flags,\n\t.port_bridge_flags\t= rtl83xx_port_bridge_flags,\n};\n"
  },
  {
    "path": "target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/qos.c",
    "content": "// SPDX-License-Identifier: GPL-2.0-only\n\n#include <net/dsa.h>\n#include <linux/delay.h>\n\n#include <asm/mach-rtl838x/mach-rtl83xx.h>\n#include \"rtl83xx.h\"\n\nstatic struct rtl838x_switch_priv *switch_priv;\nextern struct rtl83xx_soc_info soc_info;\n\nenum scheduler_type {\n\tWEIGHTED_FAIR_QUEUE = 0,\n\tWEIGHTED_ROUND_ROBIN,\n};\n\nint max_available_queue[] = {0, 1, 2, 3, 4, 5, 6, 7};\nint default_queue_weights[] = {1, 1, 1, 1, 1, 1, 1, 1};\nint dot1p_priority_remapping[] = {0, 1, 2, 3, 4, 5, 6, 7};\n\nstatic void rtl839x_read_scheduling_table(int port)\n{\n\tu32 cmd = 1 << 9 /* Execute cmd */\n\t\t| 0 << 8 /* Read */\n\t\t| 0 << 6 /* Table type 0b00 */\n\t\t| (port & 0x3f);\n\trtl839x_exec_tbl2_cmd(cmd);\n}\n\nstatic void rtl839x_write_scheduling_table(int port)\n{\n\tu32 cmd = 1 << 9 /* Execute cmd */\n\t\t| 1 << 8 /* Write */\n\t\t| 0 << 6 /* Table type 0b00 */\n\t\t| (port & 0x3f);\n\trtl839x_exec_tbl2_cmd(cmd);\n}\n\nstatic void rtl839x_read_out_q_table(int port)\n{\n\tu32 cmd = 1 << 9 /* Execute cmd */\n\t\t| 0 << 8 /* Read */\n\t\t| 2 << 6 /* Table type 0b10 */\n\t\t| (port & 0x3f);\n\trtl839x_exec_tbl2_cmd(cmd);\n}\n\nstatic void rtl838x_storm_enable(struct rtl838x_switch_priv *priv, int port, bool enable)\n{\n\t// Enable Storm control for that port for UC, MC, and BC\n\tif (enable)\n\t\tsw_w32(0x7, RTL838X_STORM_CTRL_LB_CTRL(port));\n\telse\n\t\tsw_w32(0x0, RTL838X_STORM_CTRL_LB_CTRL(port));\n}\n\nu32 rtl838x_get_egress_rate(struct rtl838x_switch_priv *priv, int port)\n{\n\tu32 rate;\n\n\tif (port > priv->cpu_port)\n\t\treturn 0;\n\trate = sw_r32(RTL838X_SCHED_P_EGR_RATE_CTRL(port)) & 0x3fff;\n\treturn rate;\n}\n\n/* Sets the rate limit, 10MBit/s is equal to a rate value of 625 */\nint rtl838x_set_egress_rate(struct rtl838x_switch_priv *priv, int port, u32 rate)\n{\n\tu32 old_rate;\n\n\tif (port > priv->cpu_port)\n\t\treturn -1;\n\n\told_rate = sw_r32(RTL838X_SCHED_P_EGR_RATE_CTRL(port));\n\tsw_w32(rate, RTL838X_SCHED_P_EGR_RATE_CTRL(port));\n\n\treturn old_rate;\n}\n\n/* Set the rate limit for a particular queue in Bits/s\n * units of the rate is 16Kbps\n */\nvoid rtl838x_egress_rate_queue_limit(struct rtl838x_switch_priv *priv, int port,\n\t\t\t\t\t    int queue, u32 rate)\n{\n\tif (port > priv->cpu_port)\n\t\treturn;\n\tif (queue > 7)\n\t\treturn;\n\tsw_w32(rate, RTL838X_SCHED_Q_EGR_RATE_CTRL(port, queue));\n}\n\nstatic void rtl838x_rate_control_init(struct rtl838x_switch_priv *priv)\n{\n\tint i;\n\n\tpr_info(\"Enabling Storm control\\n\");\n\t// TICK_PERIOD_PPS\n\tif (priv->id == 0x8380)\n\t\tsw_w32_mask(0x3ff << 20, 434 << 20, RTL838X_SCHED_LB_TICK_TKN_CTRL_0);\n\n\t// Set burst rate\n\tsw_w32(0x00008000, RTL838X_STORM_CTRL_BURST_0); // UC\n\tsw_w32(0x80008000, RTL838X_STORM_CTRL_BURST_1); // MC and BC\n\n\t// Set burst Packets per Second to 32\n\tsw_w32(0x00000020, RTL838X_STORM_CTRL_BURST_PPS_0); // UC\n\tsw_w32(0x00200020, RTL838X_STORM_CTRL_BURST_PPS_1); // MC and BC\n\n\t// Include IFG in storm control, rate based on bytes/s (0 = packets)\n\tsw_w32_mask(0, 1 << 6 | 1 << 5, RTL838X_STORM_CTRL);\n\t// Bandwidth control includes preamble and IFG (10 Bytes)\n\tsw_w32_mask(0, 1, RTL838X_SCHED_CTRL);\n\n\t// On SoCs except RTL8382M, set burst size of port egress\n\tif (priv->id != 0x8382)\n\t\tsw_w32_mask(0xffff, 0x800, RTL838X_SCHED_LB_THR);\n\n\t/* Enable storm control on all ports with a PHY and limit rates,\n\t * for UC and MC for both known and unknown addresses */\n\tfor (i = 0; i < priv->cpu_port; i++) {\n\t\tif (priv->ports[i].phy) {\n\t\t\tsw_w32((1 << 18) | 0x8000, RTL838X_STORM_CTRL_PORT_UC(i));\n\t\t\tsw_w32((1 << 18) | 0x8000, RTL838X_STORM_CTRL_PORT_MC(i));\n\t\t\tsw_w32(0x8000, RTL838X_STORM_CTRL_PORT_BC(i));\n\t\t\trtl838x_storm_enable(priv, i, true);\n\t\t}\n\t}\n\n\t// Attack prevention, enable all attack prevention measures\n\t//sw_w32(0x1ffff, RTL838X_ATK_PRVNT_CTRL);\n\t/* Attack prevention, drop (bit = 0) problematic packets on all ports.\n\t * Setting bit = 1 means: trap to CPU\n\t */\n\t//sw_w32(0, RTL838X_ATK_PRVNT_ACT);\n\t// Enable attack prevention on all ports\n\t//sw_w32(0x0fffffff, RTL838X_ATK_PRVNT_PORT_EN);\n}\n\n/* Sets the rate limit, 10MBit/s is equal to a rate value of 625 */\nu32 rtl839x_get_egress_rate(struct rtl838x_switch_priv *priv, int port)\n{\n\tu32 rate;\n\n\tpr_debug(\"%s: Getting egress rate on port %d to %d\\n\", __func__, port, rate);\n\tif (port >= priv->cpu_port)\n\t\treturn 0;\n\n\tmutex_lock(&priv->reg_mutex);\n\n\trtl839x_read_scheduling_table(port);\n\n\trate = sw_r32(RTL839X_TBL_ACCESS_DATA_2(7));\n\trate <<= 12;\n\trate |= sw_r32(RTL839X_TBL_ACCESS_DATA_2(8)) >> 20;\n\n\tmutex_unlock(&priv->reg_mutex);\n\n\treturn rate;\n}\n\n/* Sets the rate limit, 10MBit/s is equal to a rate value of 625, returns previous rate */\nint rtl839x_set_egress_rate(struct rtl838x_switch_priv *priv, int port, u32 rate)\n{\n\tu32 old_rate;\n\n\tpr_debug(\"%s: Setting egress rate on port %d to %d\\n\", __func__, port, rate);\n\tif (port >= priv->cpu_port)\n\t\treturn -1;\n\n\tmutex_lock(&priv->reg_mutex);\n\n\trtl839x_read_scheduling_table(port);\n\n\told_rate = sw_r32(RTL839X_TBL_ACCESS_DATA_2(7)) & 0xff;\n\told_rate <<= 12;\n\told_rate |= sw_r32(RTL839X_TBL_ACCESS_DATA_2(8)) >> 20;\n\tsw_w32_mask(0xff, (rate >> 12) & 0xff, RTL839X_TBL_ACCESS_DATA_2(7));\n\tsw_w32_mask(0xfff << 20, rate << 20, RTL839X_TBL_ACCESS_DATA_2(8));\n\n\trtl839x_write_scheduling_table(port);\n\t\n\tmutex_unlock(&priv->reg_mutex);\n\n\treturn old_rate;\n}\n\n/* Set the rate limit for a particular queue in Bits/s\n * units of the rate is 16Kbps\n */\nvoid rtl839x_egress_rate_queue_limit(struct rtl838x_switch_priv *priv, int port,\n\t\t\t\t\tint queue, u32 rate)\n{\n\tint lsb = 128 + queue * 20;\n\tint low_byte = 8 - (lsb >> 5);\n\tint start_bit = lsb - (low_byte << 5);\n\tu32 high_mask = 0xfffff\t>> (32 - start_bit);\n\n\tpr_debug(\"%s: Setting egress rate on port %d, queue %d to %d\\n\",\n\t\t__func__, port, queue, rate);\n\tif (port >= priv->cpu_port)\n\t\treturn;\n\tif (queue > 7)\n\t\treturn;\n\n\tmutex_lock(&priv->reg_mutex);\n\n\trtl839x_read_scheduling_table(port);\n\n\tsw_w32_mask(0xfffff << start_bit, (rate & 0xfffff) << start_bit,\n\t\t    RTL839X_TBL_ACCESS_DATA_2(low_byte));\n\tif (high_mask)\n\t\tsw_w32_mask(high_mask, (rate & 0xfffff) >> (32- start_bit),\n\t\t\t    RTL839X_TBL_ACCESS_DATA_2(low_byte - 1));\n\n\trtl839x_write_scheduling_table(port);\n\n\tmutex_unlock(&priv->reg_mutex);\n}\n\nstatic void rtl839x_rate_control_init(struct rtl838x_switch_priv *priv)\n{\n\tint p, q;\n\n\tpr_info(\"%s: enabling rate control\\n\", __func__);\n\t/* Tick length and token size settings for SoC with 250MHz,\n\t * RTL8350 family would use 50MHz\n\t */\n\t// Set the special tick period\n\tsw_w32(976563, RTL839X_STORM_CTRL_SPCL_LB_TICK_TKN_CTRL);\n\t// Ingress tick period and token length 10G\n\tsw_w32(18 << 11 | 151, RTL839X_IGR_BWCTRL_LB_TICK_TKN_CTRL_0);\n\t// Ingress tick period and token length 1G\n\tsw_w32(245 << 11 | 129, RTL839X_IGR_BWCTRL_LB_TICK_TKN_CTRL_1);\n\t// Egress tick period 10G, bytes/token 10G and tick period 1G, bytes/token 1G\n\tsw_w32(18 << 24 | 151 << 16 | 185 << 8 | 97, RTL839X_SCHED_LB_TICK_TKN_CTRL);\n\t// Set the tick period of the CPU and the Token Len\n\tsw_w32(3815 << 8 | 1, RTL839X_SCHED_LB_TICK_TKN_PPS_CTRL);\n\n\t// Set the Weighted Fair Queueing burst size\n\tsw_w32_mask(0xffff, 4500, RTL839X_SCHED_LB_THR);\n\n\t// Storm-rate calculation is based on bytes/sec (bit 5), include IFG (bit 6)\n\tsw_w32_mask(0, 1 << 5 | 1 << 6, RTL839X_STORM_CTRL);\n\n\t/* Based on the rate control mode being bytes/s\n\t * set tick period and token length for 10G\n\t */\n\tsw_w32(18 << 10 | 151, RTL839X_STORM_CTRL_LB_TICK_TKN_CTRL_0);\n\t/* and for 1G ports */\n\tsw_w32(246 << 10 | 129, RTL839X_STORM_CTRL_LB_TICK_TKN_CTRL_1);\n\n\t/* Set default burst rates on all ports (the same for 1G / 10G) with a PHY\n\t * for UC, MC and BC\n\t * For 1G port, the minimum burst rate is 1700, maximum 65535,\n\t * For 10G ports it is 2650 and 1048575 respectively */\n\tfor (p = 0; p < priv->cpu_port; p++) {\n\t\tif (priv->ports[p].phy && !priv->ports[p].is10G) {\n\t\t\tsw_w32_mask(0xffff, 0x8000, RTL839X_STORM_CTRL_PORT_UC_1(p));\n\t\t\tsw_w32_mask(0xffff, 0x8000, RTL839X_STORM_CTRL_PORT_MC_1(p));\n\t\t\tsw_w32_mask(0xffff, 0x8000, RTL839X_STORM_CTRL_PORT_BC_1(p));\n\t\t}\n\t}\n\n\t/* Setup ingress/egress per-port rate control */\n\tfor (p = 0; p < priv->cpu_port; p++) {\n\t\tif (!priv->ports[p].phy)\n\t\t\tcontinue;\n\n\t\tif (priv->ports[p].is10G)\n\t\t\trtl839x_set_egress_rate(priv, p, 625000); // 10GB/s\n\t\telse\n\t\t\trtl839x_set_egress_rate(priv, p, 62500);  // 1GB/s\n\n\t\t// Setup queues: all RTL83XX SoCs have 8 queues, maximum rate\n\t\tfor (q = 0; q < 8; q++)\n\t\t\trtl839x_egress_rate_queue_limit(priv, p, q, 0xfffff);\n\n\t\tif (priv->ports[p].is10G) {\n\t\t\t// Set high threshold to maximum\n\t\t\tsw_w32_mask(0xffff, 0xffff, RTL839X_IGR_BWCTRL_PORT_CTRL_10G_0(p));\n\t\t} else {\n\t\t\t// Set high threshold to maximum\n\t\t\tsw_w32_mask(0xffff, 0xffff, RTL839X_IGR_BWCTRL_PORT_CTRL_1(p));\n\t\t}\n\t}\n\n\t// Set global ingress low watermark rate\n\tsw_w32(65532, RTL839X_IGR_BWCTRL_CTRL_LB_THR);\n}\n\n\n\nvoid rtl838x_setup_prio2queue_matrix(int *min_queues)\n{\n\tint i;\n\tu32 v;\n\n\tpr_info(\"Current Intprio2queue setting: %08x\\n\", sw_r32(RTL838X_QM_INTPRI2QID_CTRL));\n\tfor (i = 0; i < MAX_PRIOS; i++)\n\t\tv |= i << (min_queues[i] * 3);\n\tsw_w32(v, RTL838X_QM_INTPRI2QID_CTRL);\n}\n\nvoid rtl839x_setup_prio2queue_matrix(int *min_queues)\n{\n\tint i, q;\n\n\tpr_info(\"Current Intprio2queue setting: %08x\\n\", sw_r32(RTL839X_QM_INTPRI2QID_CTRL(0)));\n\tfor (i = 0; i < MAX_PRIOS; i++) {\n\t\tq = min_queues[i];\n\t\tsw_w32(i << (q * 3), RTL839X_QM_INTPRI2QID_CTRL(q));\n\t}\n}\n\n/* Sets the CPU queue depending on the internal priority of a packet */\nvoid rtl83xx_setup_prio2queue_cpu_matrix(int *max_queues)\n{\n\tint reg = soc_info.family == RTL8380_FAMILY_ID ? RTL838X_QM_PKT2CPU_INTPRI_MAP \n\t\t\t\t\t: RTL839X_QM_PKT2CPU_INTPRI_MAP;\n\tint i;\n\tu32 v;\n\n\tpr_info(\"QM_PKT2CPU_INTPRI_MAP: %08x\\n\", sw_r32(reg));\n\tfor (i = 0; i < MAX_PRIOS; i++)\n\t\tv |= max_queues[i] << (i * 3);\n\tsw_w32(v, reg);\n}\n\nvoid rtl83xx_setup_default_prio2queue(void)\n{\n\tif (soc_info.family == RTL8380_FAMILY_ID) {\n\t\trtl838x_setup_prio2queue_matrix(max_available_queue);\n\t} else {\n\t\trtl839x_setup_prio2queue_matrix(max_available_queue);\n\t}\n\trtl83xx_setup_prio2queue_cpu_matrix(max_available_queue);\n}\n\n/* Sets the output queue assigned to a port, the port can be the CPU-port */\nvoid rtl839x_set_egress_queue(int port, int queue)\n{\n\tsw_w32(queue << ((port % 10) *3), RTL839X_QM_PORT_QNUM(port));\n}\n\n/* Sets the priority assigned of an ingress port, the port can be the CPU-port */\nvoid rtl83xx_set_ingress_priority(int port, int priority)\n{\n\tif (soc_info.family == RTL8380_FAMILY_ID)\n\t\tsw_w32(priority << ((port % 10) *3), RTL838X_PRI_SEL_PORT_PRI(port));\n\telse\n\t\tsw_w32(priority << ((port % 10) *3), RTL839X_PRI_SEL_PORT_PRI(port));\n\t\n}\n\nint rtl839x_get_scheduling_algorithm(struct rtl838x_switch_priv *priv, int port)\n{\n\tu32 v;\n\n\tmutex_lock(&priv->reg_mutex);\n\n\trtl839x_read_scheduling_table(port);\n\tv = sw_r32(RTL839X_TBL_ACCESS_DATA_2(8));\n\n\tmutex_unlock(&priv->reg_mutex);\n\n\tif (v & BIT(19))\n\t\treturn WEIGHTED_ROUND_ROBIN;\n\treturn WEIGHTED_FAIR_QUEUE;\n}\n\nvoid rtl839x_set_scheduling_algorithm(struct rtl838x_switch_priv *priv, int port,\n\t\t\t\t      enum scheduler_type sched)\n{\n\tenum scheduler_type t = rtl839x_get_scheduling_algorithm(priv, port);\n\tu32 v, oam_state, oam_port_state;\n\tu32 count;\n\tint i, egress_rate;\n\n\tmutex_lock(&priv->reg_mutex);\n\t/* Check whether we need to empty the egress queue of that port due to Errata E0014503 */\n\tif (sched == WEIGHTED_FAIR_QUEUE && t == WEIGHTED_ROUND_ROBIN && port != priv->cpu_port) {\n\t\t// Read Operations, Adminstatrion and Management control register\n\t\toam_state = sw_r32(RTL839X_OAM_CTRL);\n\n\t\t// Get current OAM state\n\t\toam_port_state = sw_r32(RTL839X_OAM_PORT_ACT_CTRL(port));\n\t\n\t\t// Disable OAM to block traffice\n\t\tv = sw_r32(RTL839X_OAM_CTRL);\n\t\tsw_w32_mask(0, 1, RTL839X_OAM_CTRL);\n\t\tv = sw_r32(RTL839X_OAM_CTRL);\n\n\t\t// Set to trap action OAM forward (bits 1, 2) and OAM Mux Action Drop (bit 0)\n\t\tsw_w32(0x2, RTL839X_OAM_PORT_ACT_CTRL(port));\n\n\t\t// Set port egress rate to unlimited\n\t\tegress_rate = rtl839x_set_egress_rate(priv, port, 0xFFFFF);\n\t\n\t\t// Wait until the egress used page count of that port is 0\n\t\ti = 0;\n\t\tdo {\n\t\t\tusleep_range(100, 200);\n\t\t\trtl839x_read_out_q_table(port);\n\t\t\tcount = sw_r32(RTL839X_TBL_ACCESS_DATA_2(6));\n\t\t\tcount >>= 20;\n\t\t\ti++;\n\t\t} while (i < 3500 && count > 0);\n\t}\n\n\t// Actually set the scheduling algorithm\n\trtl839x_read_scheduling_table(port);\n\tsw_w32_mask(BIT(19), sched ? BIT(19) : 0, RTL839X_TBL_ACCESS_DATA_2(8));\n\trtl839x_write_scheduling_table(port);\n\n\tif (sched == WEIGHTED_FAIR_QUEUE && t == WEIGHTED_ROUND_ROBIN && port != priv->cpu_port) {\n\t\t// Restore OAM state to control register\n\t\tsw_w32(oam_state, RTL839X_OAM_CTRL);\n\n\t\t// Restore trap action state\n\t\tsw_w32(oam_port_state, RTL839X_OAM_PORT_ACT_CTRL(port));\n\n\t\t// Restore port egress rate\n\t\trtl839x_set_egress_rate(priv, port, egress_rate);\n\t}\n\n\tmutex_unlock(&priv->reg_mutex);\n}\n\nvoid rtl839x_set_scheduling_queue_weights(struct rtl838x_switch_priv *priv, int port,\n\t\t\t\t\t  int *queue_weights)\n{\n\tint i, lsb, low_byte, start_bit, high_mask;\n\n\tmutex_lock(&priv->reg_mutex);\n\n\trtl839x_read_scheduling_table(port);\n\n\tfor (i = 0; i < 8; i++) {\n\t\tlsb = 48 + i * 8;\n\t\tlow_byte = 8 - (lsb >> 5);\n\t\tstart_bit = lsb - (low_byte << 5);\n\t\thigh_mask = 0x3ff >> (32 - start_bit);\n\t\tsw_w32_mask(0x3ff << start_bit, (queue_weights[i] & 0x3ff) << start_bit,\n\t\t\t\tRTL839X_TBL_ACCESS_DATA_2(low_byte));\n\t\tif (high_mask)\n\t\t\tsw_w32_mask(high_mask, (queue_weights[i] & 0x3ff) >> (32- start_bit),\n\t\t\t\t\tRTL839X_TBL_ACCESS_DATA_2(low_byte - 1));\n\t}\n\n\trtl839x_write_scheduling_table(port);\n\tmutex_unlock(&priv->reg_mutex);\n}\n\nvoid rtl838x_config_qos(void)\n{\n\tint i, p;\n\tu32 v;\n\n\tpr_info(\"Setting up RTL838X QoS\\n\");\n\tpr_info(\"RTL838X_PRI_SEL_TBL_CTRL(i): %08x\\n\", sw_r32(RTL838X_PRI_SEL_TBL_CTRL(0)));\n\trtl83xx_setup_default_prio2queue();\n\n\t// Enable inner (bit 12) and outer (bit 13) priority remapping from DSCP\n\tsw_w32_mask(0, BIT(12) | BIT(13), RTL838X_PRI_DSCP_INVLD_CTRL0);\n\n\t/* Set default weight for calculating internal priority, in prio selection group 0\n\t * Port based (prio 3), Port outer-tag (4), DSCP (5), Inner Tag (6), Outer Tag (7)\n\t */\n\tv = 3 | (4 << 3) | (5 << 6) | (6 << 9) | (7 << 12);\n\tsw_w32(v, RTL838X_PRI_SEL_TBL_CTRL(0));\n\n\t// Set the inner and outer priority one-to-one to re-marked outer dot1p priority\n\tv = 0;\n\tfor (p = 0; p < 8; p++)\n\t\tv |= p << (3 * p);\n\tsw_w32(v, RTL838X_RMK_OPRI_CTRL);\n\tsw_w32(v, RTL838X_RMK_IPRI_CTRL);\n\n\tv = 0;\n\tfor (p = 0; p < 8; p++)\n\t\tv |= (dot1p_priority_remapping[p] & 0x7) << (p * 3);\n\tsw_w32(v, RTL838X_PRI_SEL_IPRI_REMAP);\n\n\t// On all ports set scheduler type to WFQ\n\tfor (i = 0; i <= soc_info.cpu_port; i++)\n\t\tsw_w32(0, RTL838X_SCHED_P_TYPE_CTRL(i));\n\n\t// Enable egress scheduler for CPU-Port\n\tsw_w32_mask(0, BIT(8), RTL838X_SCHED_LB_CTRL(soc_info.cpu_port));\n\n\t// Enable egress drop allways on\n\tsw_w32_mask(0, BIT(11), RTL838X_FC_P_EGR_DROP_CTRL(soc_info.cpu_port));\n\n\t// Give special trap frames priority 7 (BPDUs) and routing exceptions:\n\tsw_w32_mask(0, 7 << 3 | 7, RTL838X_QM_PKT2CPU_INTPRI_2);\n\t// Give RMA frames priority 7:\n\tsw_w32_mask(0, 7, RTL838X_QM_PKT2CPU_INTPRI_1);\n}\n\nvoid rtl839x_config_qos(void)\n{\n\tint port, p, q;\n\tu32 v;\n\tstruct rtl838x_switch_priv *priv = switch_priv;\n\n\tpr_info(\"Setting up RTL839X QoS\\n\");\n\tpr_info(\"RTL839X_PRI_SEL_TBL_CTRL(i): %08x\\n\", sw_r32(RTL839X_PRI_SEL_TBL_CTRL(0)));\n\trtl83xx_setup_default_prio2queue();\n\n\tfor (port = 0; port < soc_info.cpu_port; port++)\n\t\tsw_w32(7, RTL839X_QM_PORT_QNUM(port));\n\n\t// CPU-port gets queue number 7\n\tsw_w32(7, RTL839X_QM_PORT_QNUM(soc_info.cpu_port));\n\n\tfor (port = 0; port <= soc_info.cpu_port; port++) {\n\t\trtl83xx_set_ingress_priority(port, 0);\n\t\trtl839x_set_scheduling_algorithm(priv, port, WEIGHTED_FAIR_QUEUE);\n\t\trtl839x_set_scheduling_queue_weights(priv, port, default_queue_weights);\n\t\t// Do re-marking based on outer tag\n\t\tsw_w32_mask(0, BIT(port % 32), RTL839X_RMK_PORT_DEI_TAG_CTRL(port));\n\t}\n\n\t// Remap dot1p priorities to internal priority, for this the outer tag needs be re-marked\n\tv = 0;\n\tfor (p = 0; p < 8; p++)\n\t\tv |= (dot1p_priority_remapping[p] & 0x7) << (p * 3);\n\tsw_w32(v, RTL839X_PRI_SEL_IPRI_REMAP);\n\t\n\t/* Configure Drop Precedence for Drop Eligible Indicator (DEI)\n\t * Index 0: 0\n\t * Index 1: 2\n\t * Each indicator is 2 bits long\n\t */\n\tsw_w32(2 << 2, RTL839X_PRI_SEL_DEI2DP_REMAP);\n\n\t// Re-mark DEI: 4 bit-fields of 2 bits each, field 0 is bits 0-1, ...\n\tsw_w32((0x1 << 2) | (0x1 << 4), RTL839X_RMK_DEI_CTRL);\n\n\t/* Set Congestion avoidance drop probability to 0 for drop precedences 0-2 (bits 24-31)\n\t * low threshold (bits 0-11) to 4095 and high threshold (bits 12-23) to 4095\n\t * Weighted Random Early Detection (WRED) is used\n\t */\n\tsw_w32(4095 << 12| 4095, RTL839X_WRED_PORT_THR_CTRL(0));\n\tsw_w32(4095 << 12| 4095, RTL839X_WRED_PORT_THR_CTRL(1));\n\tsw_w32(4095 << 12| 4095, RTL839X_WRED_PORT_THR_CTRL(2));\n\n\t/* Set queue-based congestion avoidance properties, register fields are as\n\t * for forward RTL839X_WRED_PORT_THR_CTRL\n\t */\n\tfor (q = 0; q < 8; q++) {\n\t\tsw_w32(255 << 24 | 78 << 12 | 68, RTL839X_WRED_QUEUE_THR_CTRL(q, 0));\n\t\tsw_w32(255 << 24 | 74 << 12 | 64, RTL839X_WRED_QUEUE_THR_CTRL(q, 0));\n\t\tsw_w32(255 << 24 | 70 << 12 | 60, RTL839X_WRED_QUEUE_THR_CTRL(q, 0));\n\t}\n}\n\nvoid __init rtl83xx_setup_qos(struct rtl838x_switch_priv *priv)\n{\n\tswitch_priv = priv;\n\n\tpr_info(\"In %s\\n\", __func__);\n\n\tif (priv->family_id == RTL8380_FAMILY_ID)\n\t\treturn rtl838x_config_qos();\n\telse if (priv->family_id == RTL8390_FAMILY_ID)\n\t\treturn rtl839x_config_qos();\n\n\tif (priv->family_id == RTL8380_FAMILY_ID)\n\t\trtl838x_rate_control_init(priv);\n\telse if (priv->family_id == RTL8390_FAMILY_ID)\n\t\trtl839x_rate_control_init(priv);\n\t\n}\n"
  },
  {
    "path": "target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/rtl838x.c",
    "content": "// SPDX-License-Identifier: GPL-2.0-only\n\n#include <asm/mach-rtl838x/mach-rtl83xx.h>\n#include <net/nexthop.h>\n\n#include \"rtl83xx.h\"\n\nextern struct mutex smi_lock;\n\n// see_dal_maple_acl_log2PhyTmplteField and src/app/diag_v2/src/diag_acl.c\n/* Definition of the RTL838X-specific template field IDs as used in the PIE */\nenum template_field_id {\n\tTEMPLATE_FIELD_SPMMASK = 0,\n\tTEMPLATE_FIELD_SPM0 = 1,\t// Source portmask ports 0-15\n\tTEMPLATE_FIELD_SPM1 = 2,\t// Source portmask ports 16-28\n\tTEMPLATE_FIELD_RANGE_CHK = 3,\n\tTEMPLATE_FIELD_DMAC0 = 4,\t// Destination MAC [15:0]\n\tTEMPLATE_FIELD_DMAC1 = 5,\t// Destination MAC [31:16]\n\tTEMPLATE_FIELD_DMAC2 = 6,\t// Destination MAC [47:32]\n\tTEMPLATE_FIELD_SMAC0 = 7,\t// Source MAC [15:0]\n\tTEMPLATE_FIELD_SMAC1 = 8,\t// Source MAC [31:16]\n\tTEMPLATE_FIELD_SMAC2 = 9,\t// Source MAC [47:32]\n\tTEMPLATE_FIELD_ETHERTYPE = 10,\t// Ethernet typ\n\tTEMPLATE_FIELD_OTAG = 11,\t// Outer VLAN tag\n\tTEMPLATE_FIELD_ITAG = 12,\t// Inner VLAN tag\n\tTEMPLATE_FIELD_SIP0 = 13,\t// IPv4 or IPv6 source IP[15:0] or ARP/RARP\n\t\t\t\t\t// source protocol address in header\n\tTEMPLATE_FIELD_SIP1 = 14,\t// IPv4 or IPv6 source IP[31:16] or ARP/RARP\n\tTEMPLATE_FIELD_DIP0 = 15,\t// IPv4 or IPv6 destination IP[15:0]\n\tTEMPLATE_FIELD_DIP1 = 16,\t// IPv4 or IPv6 destination IP[31:16]\n\tTEMPLATE_FIELD_IP_TOS_PROTO = 17, // IPv4 TOS/IPv6 traffic class and\n\t\t\t\t\t  // IPv4 proto/IPv6 next header fields\n\tTEMPLATE_FIELD_L34_HEADER = 18,\t// packet with extra tag and IPv6 with auth, dest,\n\t\t\t\t\t// frag, route, hop-by-hop option header,\n\t\t\t\t\t// IGMP type, TCP flag\n\tTEMPLATE_FIELD_L4_SPORT = 19,\t// TCP/UDP source port\n\tTEMPLATE_FIELD_L4_DPORT = 20,\t// TCP/UDP destination port\n\tTEMPLATE_FIELD_ICMP_IGMP = 21,\n\tTEMPLATE_FIELD_IP_RANGE = 22,\n\tTEMPLATE_FIELD_FIELD_SELECTOR_VALID = 23, // Field selector mask\n\tTEMPLATE_FIELD_FIELD_SELECTOR_0 = 24,\n\tTEMPLATE_FIELD_FIELD_SELECTOR_1 = 25,\n\tTEMPLATE_FIELD_FIELD_SELECTOR_2 = 26,\n\tTEMPLATE_FIELD_FIELD_SELECTOR_3 = 27,\n\tTEMPLATE_FIELD_SIP2 = 28,\t// IPv6 source IP[47:32]\n\tTEMPLATE_FIELD_SIP3 = 29,\t// IPv6 source IP[63:48]\n\tTEMPLATE_FIELD_SIP4 = 30,\t// IPv6 source IP[79:64]\n\tTEMPLATE_FIELD_SIP5 = 31,\t// IPv6 source IP[95:80]\n\tTEMPLATE_FIELD_SIP6 = 32,\t// IPv6 source IP[111:96]\n\tTEMPLATE_FIELD_SIP7 = 33,\t// IPv6 source IP[127:112]\n\tTEMPLATE_FIELD_DIP2 = 34,\t// IPv6 destination IP[47:32]\n\tTEMPLATE_FIELD_DIP3 = 35,\t// IPv6 destination IP[63:48]\n\tTEMPLATE_FIELD_DIP4 = 36,\t// IPv6 destination IP[79:64]\n\tTEMPLATE_FIELD_DIP5 = 37,\t// IPv6 destination IP[95:80]\n\tTEMPLATE_FIELD_DIP6 = 38,\t// IPv6 destination IP[111:96]\n\tTEMPLATE_FIELD_DIP7 = 39,\t// IPv6 destination IP[127:112]\n\tTEMPLATE_FIELD_FWD_VID = 40,\t// Forwarding VLAN-ID\n\tTEMPLATE_FIELD_FLOW_LABEL = 41,\n};\n\n/*\n * The RTL838X SoCs use 5 fixed templates with definitions for which data fields are to\n * be copied from the Ethernet Frame header into the 12 User-definable fields of the Packet\n * Inspection Engine's buffer. The following defines the field contents for each of the fixed\n * templates. Additionally, 3 user-definable templates can be set up via the definitions\n * in RTL838X_ACL_TMPLTE_CTRL control registers.\n * TODO: See all src/app/diag_v2/src/diag_pie.c\n */\n#define N_FIXED_TEMPLATES 5\nstatic enum template_field_id fixed_templates[N_FIXED_TEMPLATES][N_FIXED_FIELDS] =\n{\n\t{\n\t  TEMPLATE_FIELD_SPM0, TEMPLATE_FIELD_SPM1, TEMPLATE_FIELD_OTAG,\n\t  TEMPLATE_FIELD_SMAC0, TEMPLATE_FIELD_SMAC1, TEMPLATE_FIELD_SMAC2,\n\t  TEMPLATE_FIELD_DMAC0, TEMPLATE_FIELD_DMAC1, TEMPLATE_FIELD_DMAC2,\n\t  TEMPLATE_FIELD_ETHERTYPE, TEMPLATE_FIELD_ITAG, TEMPLATE_FIELD_RANGE_CHK\n\t}, {\n\t  TEMPLATE_FIELD_SIP0, TEMPLATE_FIELD_SIP1, TEMPLATE_FIELD_DIP0,\n\t  TEMPLATE_FIELD_DIP1,TEMPLATE_FIELD_IP_TOS_PROTO, TEMPLATE_FIELD_L4_SPORT,\n\t  TEMPLATE_FIELD_L4_DPORT, TEMPLATE_FIELD_ICMP_IGMP, TEMPLATE_FIELD_ITAG,\n\t  TEMPLATE_FIELD_RANGE_CHK, TEMPLATE_FIELD_SPM0, TEMPLATE_FIELD_SPM1\n\t}, {\n\t  TEMPLATE_FIELD_DMAC0, TEMPLATE_FIELD_DMAC1, TEMPLATE_FIELD_DMAC2,\n\t  TEMPLATE_FIELD_ITAG, TEMPLATE_FIELD_ETHERTYPE, TEMPLATE_FIELD_IP_TOS_PROTO,\n\t  TEMPLATE_FIELD_L4_DPORT, TEMPLATE_FIELD_L4_SPORT, TEMPLATE_FIELD_SIP0,\n\t  TEMPLATE_FIELD_SIP1, TEMPLATE_FIELD_DIP0, TEMPLATE_FIELD_DIP1\n\t}, {\n\t  TEMPLATE_FIELD_DIP0, TEMPLATE_FIELD_DIP1, TEMPLATE_FIELD_DIP2,\n\t  TEMPLATE_FIELD_DIP3, TEMPLATE_FIELD_DIP4, TEMPLATE_FIELD_DIP5,\n\t  TEMPLATE_FIELD_DIP6, TEMPLATE_FIELD_DIP7, TEMPLATE_FIELD_L4_DPORT,\n\t  TEMPLATE_FIELD_L4_SPORT, TEMPLATE_FIELD_ICMP_IGMP, TEMPLATE_FIELD_IP_TOS_PROTO\n\t}, {\n\t  TEMPLATE_FIELD_SIP0, TEMPLATE_FIELD_SIP1, TEMPLATE_FIELD_SIP2,\n\t  TEMPLATE_FIELD_SIP3, TEMPLATE_FIELD_SIP4, TEMPLATE_FIELD_SIP5,\n\t  TEMPLATE_FIELD_SIP6, TEMPLATE_FIELD_SIP7, TEMPLATE_FIELD_ITAG,\n\t  TEMPLATE_FIELD_RANGE_CHK, TEMPLATE_FIELD_SPM0, TEMPLATE_FIELD_SPM1\n\t},\n};\n\nvoid rtl838x_print_matrix(void)\n{\n\tunsigned volatile int *ptr8;\n\tint i;\n\n\tptr8 = RTL838X_SW_BASE + RTL838X_PORT_ISO_CTRL(0);\n\tfor (i = 0; i < 28; i += 8)\n\t\tpr_debug(\"> %8x %8x %8x %8x %8x %8x %8x %8x\\n\",\n\t\t\tptr8[i + 0], ptr8[i + 1], ptr8[i + 2], ptr8[i + 3],\n\t\t\tptr8[i + 4], ptr8[i + 5], ptr8[i + 6], ptr8[i + 7]);\n\tpr_debug(\"CPU_PORT> %8x\\n\", ptr8[28]);\n}\n\nstatic inline int rtl838x_port_iso_ctrl(int p)\n{\n\treturn RTL838X_PORT_ISO_CTRL(p);\n}\n\nstatic inline void rtl838x_exec_tbl0_cmd(u32 cmd)\n{\n\tsw_w32(cmd, RTL838X_TBL_ACCESS_CTRL_0);\n\tdo { } while (sw_r32(RTL838X_TBL_ACCESS_CTRL_0) & BIT(15));\n}\n\nstatic inline void rtl838x_exec_tbl1_cmd(u32 cmd)\n{\n\tsw_w32(cmd, RTL838X_TBL_ACCESS_CTRL_1);\n\tdo { } while (sw_r32(RTL838X_TBL_ACCESS_CTRL_1) & BIT(15));\n}\n\nstatic inline int rtl838x_tbl_access_data_0(int i)\n{\n\treturn RTL838X_TBL_ACCESS_DATA_0(i);\n}\n\nstatic void rtl838x_vlan_tables_read(u32 vlan, struct rtl838x_vlan_info *info)\n{\n\tu32 v;\n\t// Read VLAN table (0) via register 0\n\tstruct table_reg *r = rtl_table_get(RTL8380_TBL_0, 0);\n\n\trtl_table_read(r, vlan);\n\tinfo->tagged_ports = sw_r32(rtl_table_data(r, 0));\n\tv = sw_r32(rtl_table_data(r, 1));\n\tpr_debug(\"VLAN_READ %d: %016llx %08x\\n\", vlan, info->tagged_ports, v);\n\trtl_table_release(r);\n\n\tinfo->profile_id = v & 0x7;\n\tinfo->hash_mc_fid = !!(v & 0x8);\n\tinfo->hash_uc_fid = !!(v & 0x10);\n\tinfo->fid = (v >> 5) & 0x3f;\n\n\t// Read UNTAG table (0) via table register 1\n\tr = rtl_table_get(RTL8380_TBL_1, 0);\n\trtl_table_read(r, vlan);\n\tinfo->untagged_ports = sw_r32(rtl_table_data(r, 0));\n\trtl_table_release(r);\n}\n\nstatic void rtl838x_vlan_set_tagged(u32 vlan, struct rtl838x_vlan_info *info)\n{\n\tu32 v;\n\t// Access VLAN table (0) via register 0\n\tstruct table_reg *r = rtl_table_get(RTL8380_TBL_0, 0);\n\n\tsw_w32(info->tagged_ports, rtl_table_data(r, 0));\n\n\tv = info->profile_id;\n\tv |= info->hash_mc_fid ? 0x8 : 0;\n\tv |= info->hash_uc_fid ? 0x10 : 0;\n\tv |= ((u32)info->fid) << 5;\n\tsw_w32(v, rtl_table_data(r, 1));\n\n\trtl_table_write(r, vlan);\n\trtl_table_release(r);\n}\n\nstatic void rtl838x_vlan_set_untagged(u32 vlan, u64 portmask)\n{\n\t// Access UNTAG table (0) via register 1\n\tstruct table_reg *r = rtl_table_get(RTL8380_TBL_1, 0);\n\n\tsw_w32(portmask & 0x1fffffff, rtl_table_data(r, 0));\n\trtl_table_write(r, vlan);\n\trtl_table_release(r);\n}\n\n/* Sets the L2 forwarding to be based on either the inner VLAN tag or the outer\n */\nstatic void rtl838x_vlan_fwd_on_inner(int port, bool is_set)\n{\n\tif (is_set)\n\t\tsw_w32_mask(BIT(port), 0, RTL838X_VLAN_PORT_FWD);\n\telse\n\t\tsw_w32_mask(0, BIT(port), RTL838X_VLAN_PORT_FWD);\n}\n\nstatic u64 rtl838x_l2_hash_seed(u64 mac, u32 vid)\n{\n\treturn mac << 12 | vid;\n}\n\n/*\n * Applies the same hash algorithm as the one used currently by the ASIC to the seed\n * and returns a key into the L2 hash table\n */\nstatic u32 rtl838x_l2_hash_key(struct rtl838x_switch_priv *priv, u64 seed)\n{\n\tu32 h1, h2, h3, h;\n\n\tif (sw_r32(priv->r->l2_ctrl_0) & 1) {\n\t\th1 = (seed >> 11) & 0x7ff;\n\t\th1 = ((h1 & 0x1f) << 6) | ((h1 >> 5) & 0x3f);\n\n\t\th2 = (seed >> 33) & 0x7ff;\n\t\th2 = ((h2 & 0x3f) << 5) | ((h2 >> 6) & 0x1f);\n\n\t\th3 = (seed >> 44) & 0x7ff;\n\t\th3 = ((h3 & 0x7f) << 4) | ((h3 >> 7) & 0xf);\n\n\t\th = h1 ^ h2 ^ h3 ^ ((seed >> 55) & 0x1ff);\n\t\th ^= ((seed >> 22) & 0x7ff) ^ (seed & 0x7ff);\n\t} else {\n\t\th = ((seed >> 55) & 0x1ff) ^ ((seed >> 44) & 0x7ff)\n\t\t\t^ ((seed >> 33) & 0x7ff) ^ ((seed >> 22) & 0x7ff)\n\t\t\t^ ((seed >> 11) & 0x7ff) ^ (seed & 0x7ff);\n\t}\n\n\treturn h;\n}\n\nstatic inline int rtl838x_mac_force_mode_ctrl(int p)\n{\n\treturn RTL838X_MAC_FORCE_MODE_CTRL + (p << 2);\n}\n\nstatic inline int rtl838x_mac_port_ctrl(int p)\n{\n\treturn RTL838X_MAC_PORT_CTRL(p);\n}\n\nstatic inline int rtl838x_l2_port_new_salrn(int p)\n{\n\treturn RTL838X_L2_PORT_NEW_SALRN(p);\n}\n\nstatic inline int rtl838x_l2_port_new_sa_fwd(int p)\n{\n\treturn RTL838X_L2_PORT_NEW_SA_FWD(p);\n}\n\nstatic inline int rtl838x_mac_link_spd_sts(int p)\n{\n\treturn RTL838X_MAC_LINK_SPD_STS(p);\n}\n\ninline static int rtl838x_trk_mbr_ctr(int group)\n{\n\treturn RTL838X_TRK_MBR_CTR + (group << 2);\n}\n\n/*\n * Fills an L2 entry structure from the SoC registers\n */\nstatic void rtl838x_fill_l2_entry(u32 r[], struct rtl838x_l2_entry *e)\n{\n\t/* Table contains different entry types, we need to identify the right one:\n\t * Check for MC entries, first\n\t * In contrast to the RTL93xx SoCs, there is no valid bit, use heuristics to\n\t * identify valid entries\n\t */\n\te->is_ip_mc = !!(r[0] & BIT(22));\n\te->is_ipv6_mc = !!(r[0] & BIT(21));\n\te->type = L2_INVALID;\n\n\tif (!e->is_ip_mc && !e->is_ipv6_mc) {\n\t\te->mac[0] = (r[1] >> 20);\n\t\te->mac[1] = (r[1] >> 12);\n\t\te->mac[2] = (r[1] >> 4);\n\t\te->mac[3] = (r[1] & 0xf) << 4 | (r[2] >> 28);\n\t\te->mac[4] = (r[2] >> 20);\n\t\te->mac[5] = (r[2] >> 12);\n\n\t\te->rvid = r[2] & 0xfff;\n\t\te->vid = r[0] & 0xfff;\n\n\t\t/* Is it a unicast entry? check multicast bit */\n\t\tif (!(e->mac[0] & 1)) {\n\t\t\te->is_static = !!((r[0] >> 19) & 1);\n\t\t\te->port = (r[0] >> 12) & 0x1f;\n\t\t\te->block_da = !!(r[1] & BIT(30));\n\t\t\te->block_sa = !!(r[1] & BIT(31));\n\t\t\te->suspended = !!(r[1] & BIT(29));\n\t\t\te->next_hop = !!(r[1] & BIT(28));\n\t\t\tif (e->next_hop) {\n\t\t\t\tpr_debug(\"Found next hop entry, need to read extra data\\n\");\n\t\t\t\te->nh_vlan_target = !!(r[0] & BIT(9));\n\t\t\t\te->nh_route_id = r[0] & 0x1ff;\n\t\t\t\te->vid = e->rvid;\n\t\t\t}\n\t\t\te->age = (r[0] >> 17) & 0x3;\n\t\t\te->valid = true;\n\t\t\t\n\t\t\t/* A valid entry has one of mutli-cast, aging, sa/da-blocking,\n\t\t\t * next-hop or static entry bit set */\n\t\t\tif (!(r[0] & 0x007c0000) && !(r[1] & 0xd0000000))\n\t\t\t\te->valid = false;\n\t\t\telse\n\t\t\t\te->type = L2_UNICAST;\n\t\t} else { // L2 multicast\n\t\t\tpr_debug(\"Got L2 MC entry: %08x %08x %08x\\n\", r[0], r[1], r[2]);\n\t\t\te->valid = true;\n\t\t\te->type = L2_MULTICAST;\n\t\t\te->mc_portmask_index = (r[0] >> 12) & 0x1ff;\n\t\t}\n\t} else { // IPv4 and IPv6 multicast\n\t\te->valid = true;\n\t\te->mc_portmask_index = (r[0] >> 12) & 0x1ff;\n\t\te->mc_gip = (r[1] << 20) | (r[2] >> 12);\n\t\te->rvid = r[2] & 0xfff;\n\t}\n\tif (e->is_ip_mc)\n\t\te->type = IP4_MULTICAST;\n\tif (e->is_ipv6_mc)\n\t\te->type = IP6_MULTICAST;\n}\n\n/*\n * Fills the 3 SoC table registers r[] with the information of in the rtl838x_l2_entry\n */\nstatic void rtl838x_fill_l2_row(u32 r[], struct rtl838x_l2_entry *e)\n{\n\tu64 mac = ether_addr_to_u64(e->mac);\n\n\tif (!e->valid) {\n\t\tr[0] = r[1] = r[2] = 0;\n\t\treturn;\n\t}\n\n\tr[0] = e->is_ip_mc ? BIT(22) : 0;\n\tr[0] |= e->is_ipv6_mc ? BIT(21) : 0;\n\n\tif (!e->is_ip_mc && !e->is_ipv6_mc) {\n\t\tr[1] = mac >> 20;\n\t\tr[2] = (mac & 0xfffff) << 12;\n\n\t\t/* Is it a unicast entry? check multicast bit */\n\t\tif (!(e->mac[0] & 1)) {\n\t\t\tr[0] |= e->is_static ? BIT(19) : 0;\n\t\t\tr[0] |= (e->port & 0x3f) << 12;\n\t\t\tr[0] |= e->vid;\n\t\t\tr[1] |= e->block_da ? BIT(30) : 0;\n\t\t\tr[1] |= e->block_sa ? BIT(31) : 0;\n\t\t\tr[1] |= e->suspended ? BIT(29) : 0;\n\t\t\tr[2] |= e->rvid & 0xfff;\n\t\t\tif (e->next_hop) {\n\t\t\t\tr[1] |= BIT(28);\n\t\t\t\tr[0] |= e->nh_vlan_target ? BIT(9) : 0;\n\t\t\t\tr[0] |= e->nh_route_id & 0x1ff;\n\t\t\t}\n\t\t\tr[0] |= (e->age & 0x3) << 17;\n\t\t} else { // L2 Multicast\n\t\t\tr[0] |= (e->mc_portmask_index & 0x1ff) << 12;\n\t\t\tr[2] |= e->rvid & 0xfff;\n\t\t\tr[0] |= e->vid & 0xfff;\n\t\t\tpr_debug(\"FILL MC: %08x %08x %08x\\n\", r[0], r[1], r[2]);\n\t\t}\n\t} else { // IPv4 and IPv6 multicast\n\t\tr[0] |= (e->mc_portmask_index & 0x1ff) << 12;\n\t\tr[1] = e->mc_gip >> 20;\n\t\tr[2] = e->mc_gip << 12;\n\t\tr[2] |= e->rvid;\n\t}\n}\n\n/*\n * Read an L2 UC or MC entry out of a hash bucket of the L2 forwarding table\n * hash is the id of the bucket and pos is the position of the entry in that bucket\n * The data read from the SoC is filled into rtl838x_l2_entry\n */\nstatic u64 rtl838x_read_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_l2_entry *e)\n{\n\tu64 entry;\n\tu32 r[3];\n\tstruct table_reg *q = rtl_table_get(RTL8380_TBL_L2, 0); // Access L2 Table 0\n\tu32 idx = (0 << 14) | (hash << 2) | pos; // Search SRAM, with hash and at pos in bucket\n\tint i;\n\n\trtl_table_read(q, idx);\n\tfor (i= 0; i < 3; i++)\n\t\tr[i] = sw_r32(rtl_table_data(q, i));\n\n\trtl_table_release(q);\n\n\trtl838x_fill_l2_entry(r, e);\n\tif (!e->valid)\n\t\treturn 0;\n\n\tentry = (((u64) r[1]) << 32) | (r[2]);  // mac and vid concatenated as hash seed\n\treturn entry;\n}\n\nstatic void rtl838x_write_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_l2_entry *e)\n{\n\tu32 r[3];\n\tstruct table_reg *q = rtl_table_get(RTL8380_TBL_L2, 0);\n\tint i;\n\n\tu32 idx = (0 << 14) | (hash << 2) | pos; // Access SRAM, with hash and at pos in bucket\n\n\trtl838x_fill_l2_row(r, e);\n\n\tfor (i= 0; i < 3; i++)\n\t\tsw_w32(r[i], rtl_table_data(q, i));\n\n\trtl_table_write(q, idx);\n\trtl_table_release(q);\n}\n\nstatic u64 rtl838x_read_cam(int idx, struct rtl838x_l2_entry *e)\n{\n\tu64 entry;\n\tu32 r[3];\n\tstruct table_reg *q = rtl_table_get(RTL8380_TBL_L2, 1); // Access L2 Table 1\n\tint i;\n\n\trtl_table_read(q, idx);\n\tfor (i= 0; i < 3; i++)\n\t\tr[i] = sw_r32(rtl_table_data(q, i));\n\n\trtl_table_release(q);\n\n\trtl838x_fill_l2_entry(r, e);\n\tif (!e->valid)\n\t\treturn 0;\n\n\tpr_debug(\"Found in CAM: R1 %x R2 %x R3 %x\\n\", r[0], r[1], r[2]);\n\n\t// Return MAC with concatenated VID ac concatenated ID\n\tentry = (((u64) r[1]) << 32) | r[2];\n\treturn entry;\n}\n\nstatic void rtl838x_write_cam(int idx, struct rtl838x_l2_entry *e)\n{\n\tu32 r[3];\n\tstruct table_reg *q = rtl_table_get(RTL8380_TBL_L2, 1); // Access L2 Table 1\n\tint i;\n\n\trtl838x_fill_l2_row(r, e);\n\n\tfor (i= 0; i < 3; i++)\n\t\tsw_w32(r[i], rtl_table_data(q, i));\n\n\trtl_table_write(q, idx);\n\trtl_table_release(q);\n}\n\nstatic u64 rtl838x_read_mcast_pmask(int idx)\n{\n\tu32 portmask;\n\t// Read MC_PMSK (2) via register RTL8380_TBL_L2\n\tstruct table_reg *q = rtl_table_get(RTL8380_TBL_L2, 2);\n\n\trtl_table_read(q, idx);\n\tportmask = sw_r32(rtl_table_data(q, 0));\n\trtl_table_release(q);\n\n\treturn portmask;\n}\n\nstatic void rtl838x_write_mcast_pmask(int idx, u64 portmask)\n{\n\t// Access MC_PMSK (2) via register RTL8380_TBL_L2\n\tstruct table_reg *q = rtl_table_get(RTL8380_TBL_L2, 2);\n\n\tsw_w32(((u32)portmask) & 0x1fffffff, rtl_table_data(q, 0));\n\trtl_table_write(q, idx);\n\trtl_table_release(q);\n}\n\nstatic void rtl838x_vlan_profile_setup(int profile)\n{\n\tu32 pmask_id = UNKNOWN_MC_PMASK;\n\t// Enable L2 Learning BIT 0, portmask UNKNOWN_MC_PMASK for unknown MC traffic flooding\n\tu32 p = 1 | pmask_id << 1 | pmask_id << 10 | pmask_id << 19;\n\n\tsw_w32(p, RTL838X_VLAN_PROFILE(profile));\n\n\t/* RTL8380 and RTL8390 use an index into the portmask table to set the\n\t * unknown multicast portmask, setup a default at a safe location\n\t * On RTL93XX, the portmask is directly set in the profile,\n\t * see e.g. rtl9300_vlan_profile_setup\n\t */\n\trtl838x_write_mcast_pmask(UNKNOWN_MC_PMASK, 0x1fffffff);\n}\n\nstatic void rtl838x_l2_learning_setup(void)\n{\n\t/* Set portmask for broadcast traffic and unknown unicast address flooding\n\t * to the reserved entry in the portmask table used also for\n\t * multicast flooding */\n\tsw_w32(UNKNOWN_MC_PMASK << 12 | UNKNOWN_MC_PMASK, RTL838X_L2_FLD_PMSK);\n\n\t/* Enable learning constraint system-wide (bit 0), per-port (bit 1)\n\t * and per vlan (bit 2) */\n\tsw_w32(0x7, RTL838X_L2_LRN_CONSTRT_EN);\n\n\t// Limit learning to maximum: 16k entries, after that just flood (bits 0-1)\n\tsw_w32((0x3fff << 2) | 0, RTL838X_L2_LRN_CONSTRT);\n\n\t// Do not trap ARP packets to CPU_PORT\n\tsw_w32(0, RTL838X_SPCL_TRAP_ARP_CTRL);\n}\n\nstatic void rtl838x_enable_learning(int port, bool enable)\n{\n\t// Limit learning to maximum: 32k entries, after that just flood (bits 0-1)\n\n\tif (enable)  {\n\t\t// flood after 32k entries\n\t\tsw_w32((0x3fff << 2) | 0, RTL838X_L2_PORT_LRN_CONSTRT + (port << 2));\n\t} else {\n\t\t// just forward\n\t\tsw_w32(0, RTL838X_L2_PORT_LRN_CONSTRT + (port << 2));\n\t}\n}\n\nstatic void rtl838x_enable_flood(int port, bool enable)\n{\n\tu32 flood_mask = sw_r32(RTL838X_L2_PORT_LRN_CONSTRT + (port << 2));\n\n\tif (enable)  {\n\t\t// flood\n\t\tflood_mask &= ~3;\n\t\tflood_mask |= 0;\n\t\tsw_w32(flood_mask, RTL838X_L2_PORT_LRN_CONSTRT + (port << 2));\n\t} else {\n\t\t// drop (bit 1)\n\t\tflood_mask &= ~3;\n\t\tflood_mask |= 1;\n\t\tsw_w32(flood_mask, RTL838X_L2_PORT_LRN_CONSTRT + (port << 2));\n\t}\n}\n\nstatic void rtl838x_enable_mcast_flood(int port, bool enable)\n{\n\n}\n\nstatic void rtl838x_enable_bcast_flood(int port, bool enable)\n{\n\n}\n\nstatic void rtl838x_stp_get(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[])\n{\n\tint i;\n\tu32 cmd = 1 << 15 /* Execute cmd */\n\t\t| 1 << 14 /* Read */\n\t\t| 2 << 12 /* Table type 0b10 */\n\t\t| (msti & 0xfff);\n\tpriv->r->exec_tbl0_cmd(cmd);\n\n\tfor (i = 0; i < 2; i++)\n\t\tport_state[i] = sw_r32(priv->r->tbl_access_data_0(i));\n}\n\nstatic void rtl838x_stp_set(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[])\n{\n\tint i;\n\tu32 cmd = 1 << 15 /* Execute cmd */\n\t\t| 0 << 14 /* Write */\n\t\t| 2 << 12 /* Table type 0b10 */\n\t\t| (msti & 0xfff);\n\n\tfor (i = 0; i < 2; i++)\n\t\tsw_w32(port_state[i], priv->r->tbl_access_data_0(i));\n\tpriv->r->exec_tbl0_cmd(cmd);\n}\n\nu64 rtl838x_traffic_get(int source)\n{\n\treturn rtl838x_get_port_reg(rtl838x_port_iso_ctrl(source));\n}\n\nvoid rtl838x_traffic_set(int source, u64 dest_matrix)\n{\n\trtl838x_set_port_reg(dest_matrix, rtl838x_port_iso_ctrl(source));\n}\n\nvoid rtl838x_traffic_enable(int source, int dest)\n{\n\trtl838x_mask_port_reg(0, BIT(dest), rtl838x_port_iso_ctrl(source));\n}\n\nvoid rtl838x_traffic_disable(int source, int dest)\n{\n\trtl838x_mask_port_reg(BIT(dest), 0, rtl838x_port_iso_ctrl(source));\n}\n\n/*\n * Enables or disables the EEE/EEEP capability of a port\n */\nstatic void rtl838x_port_eee_set(struct rtl838x_switch_priv *priv, int port, bool enable)\n{\n\tu32 v;\n\n\t// This works only for Ethernet ports, and on the RTL838X, ports from 24 are SFP\n\tif (port >= 24)\n\t\treturn;\n\n\tpr_debug(\"In %s: setting port %d to %d\\n\", __func__, port, enable);\n\tv = enable ? 0x3 : 0x0;\n\n\t// Set EEE state for 100 (bit 9) & 1000MBit (bit 10)\n\tsw_w32_mask(0x3 << 9, v << 9, priv->r->mac_force_mode_ctrl(port));\n\n\t// Set TX/RX EEE state\n\tif (enable) {\n\t\tsw_w32_mask(0, BIT(port), RTL838X_EEE_PORT_TX_EN);\n\t\tsw_w32_mask(0, BIT(port), RTL838X_EEE_PORT_RX_EN);\n\t} else {\n\t\tsw_w32_mask(BIT(port), 0, RTL838X_EEE_PORT_TX_EN);\n\t\tsw_w32_mask(BIT(port), 0, RTL838X_EEE_PORT_RX_EN);\n\t}\n\tpriv->ports[port].eee_enabled = enable;\n}\n\n\n/*\n * Get EEE own capabilities and negotiation result\n */\nstatic int rtl838x_eee_port_ability(struct rtl838x_switch_priv *priv,\n\t\t\t\t    struct ethtool_eee *e, int port)\n{\n\tu64 link;\n\n\tif (port >= 24)\n\t\treturn 0;\n\n\tlink = rtl839x_get_port_reg_le(RTL838X_MAC_LINK_STS);\n\tif (!(link & BIT(port)))\n\t\treturn 0;\n\n\tif (sw_r32(rtl838x_mac_force_mode_ctrl(port)) & BIT(9))\n\t\te->advertised |= ADVERTISED_100baseT_Full;\n\n\tif (sw_r32(rtl838x_mac_force_mode_ctrl(port)) & BIT(10))\n\t\te->advertised |= ADVERTISED_1000baseT_Full;\n\n\tif (sw_r32(RTL838X_MAC_EEE_ABLTY) & BIT(port)) {\n\t\te->lp_advertised = ADVERTISED_100baseT_Full;\n\t\te->lp_advertised |= ADVERTISED_1000baseT_Full;\n\t\treturn 1;\n\t}\n\n\treturn 0;\n}\n\nstatic void rtl838x_init_eee(struct rtl838x_switch_priv *priv, bool enable)\n{\n\tint i;\n\n\tpr_info(\"Setting up EEE, state: %d\\n\", enable);\n\tsw_w32_mask(0x4, 0, RTL838X_SMI_GLB_CTRL);\n\n\t/* Set timers for EEE */\n\tsw_w32(0x5001411, RTL838X_EEE_TX_TIMER_GIGA_CTRL);\n\tsw_w32(0x5001417, RTL838X_EEE_TX_TIMER_GELITE_CTRL);\n\n\t// Enable EEE MAC support on ports\n\tfor (i = 0; i < priv->cpu_port; i++) {\n\t\tif (priv->ports[i].phy)\n\t\t\trtl838x_port_eee_set(priv, i, enable);\n\t}\n\tpriv->eee_enabled = enable;\n}\n\nstatic void rtl838x_pie_lookup_enable(struct rtl838x_switch_priv *priv, int index)\n{\n\tint block = index / PIE_BLOCK_SIZE;\n\tu32 block_state = sw_r32(RTL838X_ACL_BLK_LOOKUP_CTRL);\n\n\t// Make sure rule-lookup is enabled in the block\n\tif (!(block_state & BIT(block)))\n\t\tsw_w32(block_state | BIT(block), RTL838X_ACL_BLK_LOOKUP_CTRL);\n}\n\nstatic void rtl838x_pie_rule_del(struct rtl838x_switch_priv *priv, int index_from, int index_to)\n{\n\tint block_from = index_from / PIE_BLOCK_SIZE;\n\tint block_to = index_to / PIE_BLOCK_SIZE;\n\tu32 v = (index_from << 1)| (index_to << 12 ) | BIT(0);\n\tint block;\n\tu32 block_state;\n\n\tpr_debug(\"%s: from %d to %d\\n\", __func__, index_from, index_to);\n\tmutex_lock(&priv->reg_mutex);\n\n\t// Remember currently active blocks\n\tblock_state = sw_r32(RTL838X_ACL_BLK_LOOKUP_CTRL);\n\n\t// Make sure rule-lookup is disabled in the relevant blocks\n\tfor (block = block_from; block <= block_to; block++) {\n\t\tif (block_state & BIT(block))\n\t\t\tsw_w32(block_state & (~BIT(block)), RTL838X_ACL_BLK_LOOKUP_CTRL);\n\t}\n\n\t// Write from-to and execute bit into control register\n\tsw_w32(v, RTL838X_ACL_CLR_CTRL);\n\n\t// Wait until command has completed\n\tdo {\n\t} while (sw_r32(RTL838X_ACL_CLR_CTRL) & BIT(0));\n\n\t// Re-enable rule lookup\n\tfor (block = block_from; block <= block_to; block++) {\n\t\tif (!(block_state & BIT(block)))\n\t\t\tsw_w32(block_state | BIT(block), RTL838X_ACL_BLK_LOOKUP_CTRL);\n\t}\n\n\tmutex_unlock(&priv->reg_mutex);\n}\n\n/*\n * Reads the intermediate representation of the templated match-fields of the\n * PIE rule in the pie_rule structure and fills in the raw data fields in the\n * raw register space r[].\n * The register space configuration size is identical for the RTL8380/90 and RTL9300,\n * however the RTL9310 has 2 more registers / fields and the physical field-ids\n * are specific to every platform.\n */\nstatic void rtl838x_write_pie_templated(u32 r[], struct pie_rule *pr, enum template_field_id t[])\n{\n\tint i;\n\tenum template_field_id field_type;\n\tu16 data, data_m;\n\n\tfor (i = 0; i < N_FIXED_FIELDS; i++) {\n\t\tfield_type = t[i];\n\t\tdata = data_m = 0;\n\n\t\tswitch (field_type) {\n\t\tcase TEMPLATE_FIELD_SPM0:\n\t\t\tdata = pr->spm;\n\t\t\tdata_m = pr->spm_m;\n\t\t\tbreak;\n\t\tcase TEMPLATE_FIELD_SPM1:\n\t\t\tdata = pr->spm >> 16;\n\t\t\tdata_m = pr->spm_m >> 16;\n\t\t\tbreak;\n\t\tcase TEMPLATE_FIELD_OTAG:\n\t\t\tdata = pr->otag;\n\t\t\tdata_m = pr->otag_m;\n\t\t\tbreak;\n\t\tcase TEMPLATE_FIELD_SMAC0:\n\t\t\tdata = pr->smac[4];\n\t\t\tdata = (data << 8) | pr->smac[5];\n\t\t\tdata_m = pr->smac_m[4];\n\t\t\tdata_m = (data_m << 8) | pr->smac_m[5];\n\t\t\tbreak;\n\t\tcase TEMPLATE_FIELD_SMAC1:\n\t\t\tdata = pr->smac[2];\n\t\t\tdata = (data << 8) | pr->smac[3];\n\t\t\tdata_m = pr->smac_m[2];\n\t\t\tdata_m = (data_m << 8) | pr->smac_m[3];\n\t\t\tbreak;\n\t\tcase TEMPLATE_FIELD_SMAC2:\n\t\t\tdata = pr->smac[0];\n\t\t\tdata = (data << 8) | pr->smac[1];\n\t\t\tdata_m = pr->smac_m[0];\n\t\t\tdata_m = (data_m << 8) | pr->smac_m[1];\n\t\t\tbreak;\n\t\tcase TEMPLATE_FIELD_DMAC0:\n\t\t\tdata = pr->dmac[4];\n\t\t\tdata = (data << 8) | pr->dmac[5];\n\t\t\tdata_m = pr->dmac_m[4];\n\t\t\tdata_m = (data_m << 8) | pr->dmac_m[5];\n\t\t\tbreak;\n\t\tcase TEMPLATE_FIELD_DMAC1:\n\t\t\tdata = pr->dmac[2];\n\t\t\tdata = (data << 8) | pr->dmac[3];\n\t\t\tdata_m = pr->dmac_m[2];\n\t\t\tdata_m = (data_m << 8) | pr->dmac_m[3];\n\t\t\tbreak;\n\t\tcase TEMPLATE_FIELD_DMAC2:\n\t\t\tdata = pr->dmac[0];\n\t\t\tdata = (data << 8) | pr->dmac[1];\n\t\t\tdata_m = pr->dmac_m[0];\n\t\t\tdata_m = (data_m << 8) | pr->dmac_m[1];\n\t\t\tbreak;\n\t\tcase TEMPLATE_FIELD_ETHERTYPE:\n\t\t\tdata = pr->ethertype;\n\t\t\tdata_m = pr->ethertype_m;\n\t\t\tbreak;\n\t\tcase TEMPLATE_FIELD_ITAG:\n\t\t\tdata = pr->itag;\n\t\t\tdata_m = pr->itag_m;\n\t\t\tbreak;\n\t\tcase TEMPLATE_FIELD_RANGE_CHK:\n\t\t\tdata = pr->field_range_check;\n\t\t\tdata_m = pr->field_range_check_m;\n\t\t\tbreak;\n\t\tcase TEMPLATE_FIELD_SIP0:\n\t\t\tif (pr->is_ipv6) {\n\t\t\t\tdata = pr->sip6.s6_addr16[7];\n\t\t\t\tdata_m = pr->sip6_m.s6_addr16[7];\n\t\t\t} else {\n\t\t\t\tdata = pr->sip;\n\t\t\t\tdata_m = pr->sip_m;\n\t\t\t}\n\t\t\tbreak;\n\t\tcase TEMPLATE_FIELD_SIP1:\n\t\t\tif (pr->is_ipv6) {\n\t\t\t\tdata = pr->sip6.s6_addr16[6];\n\t\t\t\tdata_m = pr->sip6_m.s6_addr16[6];\n\t\t\t} else {\n\t\t\t\tdata = pr->sip >> 16;\n\t\t\t\tdata_m = pr->sip_m >> 16;\n\t\t\t}\n\t\t\tbreak;\n\n\t\tcase TEMPLATE_FIELD_SIP2:\n\t\tcase TEMPLATE_FIELD_SIP3:\n\t\tcase TEMPLATE_FIELD_SIP4:\n\t\tcase TEMPLATE_FIELD_SIP5:\n\t\tcase TEMPLATE_FIELD_SIP6:\n\t\tcase TEMPLATE_FIELD_SIP7:\n\t\t\tdata = pr->sip6.s6_addr16[5 - (field_type - TEMPLATE_FIELD_SIP2)];\n\t\t\tdata_m = pr->sip6_m.s6_addr16[5 - (field_type - TEMPLATE_FIELD_SIP2)];\n\t\t\tbreak;\n\n\t\tcase TEMPLATE_FIELD_DIP0:\n\t\t\tif (pr->is_ipv6) {\n\t\t\t\tdata = pr->dip6.s6_addr16[7];\n\t\t\t\tdata_m = pr->dip6_m.s6_addr16[7];\n\t\t\t} else {\n\t\t\t\tdata = pr->dip;\n\t\t\t\tdata_m = pr->dip_m;\n\t\t\t}\n\t\t\tbreak;\n\n\t\tcase TEMPLATE_FIELD_DIP1:\n\t\t\tif (pr->is_ipv6) {\n\t\t\t\tdata = pr->dip6.s6_addr16[6];\n\t\t\t\tdata_m = pr->dip6_m.s6_addr16[6];\n\t\t\t} else {\n\t\t\t\tdata = pr->dip >> 16;\n\t\t\t\tdata_m = pr->dip_m >> 16;\n\t\t\t}\n\t\t\tbreak;\n\n\t\tcase TEMPLATE_FIELD_DIP2:\n\t\tcase TEMPLATE_FIELD_DIP3:\n\t\tcase TEMPLATE_FIELD_DIP4:\n\t\tcase TEMPLATE_FIELD_DIP5:\n\t\tcase TEMPLATE_FIELD_DIP6:\n\t\tcase TEMPLATE_FIELD_DIP7:\n\t\t\tdata = pr->dip6.s6_addr16[5 - (field_type - TEMPLATE_FIELD_DIP2)];\n\t\t\tdata_m = pr->dip6_m.s6_addr16[5 - (field_type - TEMPLATE_FIELD_DIP2)];\n\t\t\tbreak;\n\n\t\tcase TEMPLATE_FIELD_IP_TOS_PROTO:\n\t\t\tdata = pr->tos_proto;\n\t\t\tdata_m = pr->tos_proto_m;\n\t\t\tbreak;\n\t\tcase TEMPLATE_FIELD_L4_SPORT:\n\t\t\tdata = pr->sport;\n\t\t\tdata_m = pr->sport_m;\n\t\t\tbreak;\n\t\tcase TEMPLATE_FIELD_L4_DPORT:\n\t\t\tdata = pr->dport;\n\t\t\tdata_m = pr->dport_m;\n\t\t\tbreak;\n\t\tcase TEMPLATE_FIELD_ICMP_IGMP:\n\t\t\tdata = pr->icmp_igmp;\n\t\t\tdata_m = pr->icmp_igmp_m;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tpr_info(\"%s: unknown field %d\\n\", __func__, field_type);\n\t\t\tcontinue;\n\t\t}\n\t\tif (!(i % 2)) {\n\t\t\tr[5 - i / 2] = data;\n\t\t\tr[12 - i / 2] = data_m;\n\t\t} else {\n\t\t\tr[5 - i / 2] |= ((u32)data) << 16;\n\t\t\tr[12 - i / 2] |= ((u32)data_m) << 16;\n\t\t}\n\t}\n}\n\n/*\n * Creates the intermediate representation of the templated match-fields of the\n * PIE rule in the pie_rule structure by reading the raw data fields in the\n * raw register space r[].\n * The register space configuration size is identical for the RTL8380/90 and RTL9300,\n * however the RTL9310 has 2 more registers / fields and the physical field-ids\n */\nstatic void rtl838x_read_pie_templated(u32 r[], struct pie_rule *pr, enum template_field_id t[])\n{\n\tint i;\n\tenum template_field_id field_type;\n\tu16 data, data_m;\n\n\tfor (i = 0; i < N_FIXED_FIELDS; i++) {\n\t\tfield_type = t[i];\n\t\tif (!(i % 2)) {\n\t\t\tdata = r[5 - i / 2];\n\t\t\tdata_m = r[12 - i / 2];\n\t\t} else {\n\t\t\tdata = r[5 - i / 2] >> 16;\n\t\t\tdata_m = r[12 - i / 2] >> 16;\n\t\t}\n\n\t\tswitch (field_type) {\n\t\tcase TEMPLATE_FIELD_SPM0:\n\t\t\tpr->spm = (pr->spn << 16) | data;\n\t\t\tpr->spm_m = (pr->spn << 16) | data_m;\n\t\t\tbreak;\n\t\tcase TEMPLATE_FIELD_SPM1:\n\t\t\tpr->spm = data;\n\t\t\tpr->spm_m = data_m;\n\t\t\tbreak;\n\t\tcase TEMPLATE_FIELD_OTAG:\n\t\t\tpr->otag = data;\n\t\t\tpr->otag_m = data_m;\n\t\t\tbreak;\n\t\tcase TEMPLATE_FIELD_SMAC0:\n\t\t\tpr->smac[4] = data >> 8;\n\t\t\tpr->smac[5] = data;\n\t\t\tpr->smac_m[4] = data >> 8;\n\t\t\tpr->smac_m[5] = data;\n\t\t\tbreak;\n\t\tcase TEMPLATE_FIELD_SMAC1:\n\t\t\tpr->smac[2] = data >> 8;\n\t\t\tpr->smac[3] = data;\n\t\t\tpr->smac_m[2] = data >> 8;\n\t\t\tpr->smac_m[3] = data;\n\t\t\tbreak;\n\t\tcase TEMPLATE_FIELD_SMAC2:\n\t\t\tpr->smac[0] = data >> 8;\n\t\t\tpr->smac[1] = data;\n\t\t\tpr->smac_m[0] = data >> 8;\n\t\t\tpr->smac_m[1] = data;\n\t\t\tbreak;\n\t\tcase TEMPLATE_FIELD_DMAC0:\n\t\t\tpr->dmac[4] = data >> 8;\n\t\t\tpr->dmac[5] = data;\n\t\t\tpr->dmac_m[4] = data >> 8;\n\t\t\tpr->dmac_m[5] = data;\n\t\t\tbreak;\n\t\tcase TEMPLATE_FIELD_DMAC1:\n\t\t\tpr->dmac[2] = data >> 8;\n\t\t\tpr->dmac[3] = data;\n\t\t\tpr->dmac_m[2] = data >> 8;\n\t\t\tpr->dmac_m[3] = data;\n\t\t\tbreak;\n\t\tcase TEMPLATE_FIELD_DMAC2:\n\t\t\tpr->dmac[0] = data >> 8;\n\t\t\tpr->dmac[1] = data;\n\t\t\tpr->dmac_m[0] = data >> 8;\n\t\t\tpr->dmac_m[1] = data;\n\t\t\tbreak;\n\t\tcase TEMPLATE_FIELD_ETHERTYPE:\n\t\t\tpr->ethertype = data;\n\t\t\tpr->ethertype_m = data_m;\n\t\t\tbreak;\n\t\tcase TEMPLATE_FIELD_ITAG:\n\t\t\tpr->itag = data;\n\t\t\tpr->itag_m = data_m;\n\t\t\tbreak;\n\t\tcase TEMPLATE_FIELD_RANGE_CHK:\n\t\t\tpr->field_range_check = data;\n\t\t\tpr->field_range_check_m = data_m;\n\t\t\tbreak;\n\t\tcase TEMPLATE_FIELD_SIP0:\n\t\t\tpr->sip = data;\n\t\t\tpr->sip_m = data_m;\n\t\t\tbreak;\n\t\tcase TEMPLATE_FIELD_SIP1:\n\t\t\tpr->sip = (pr->sip << 16) | data;\n\t\t\tpr->sip_m = (pr->sip << 16) | data_m;\n\t\t\tbreak;\n\t\tcase TEMPLATE_FIELD_SIP2:\n\t\t\tpr->is_ipv6 = true;\n\t\t\t// Make use of limitiations on the position of the match values\n\t\t\tipv6_addr_set(&pr->sip6, pr->sip, r[5 - i / 2],\n\t\t\t\t      r[4 - i / 2], r[3 - i / 2]);\n\t\t\tipv6_addr_set(&pr->sip6_m, pr->sip_m, r[5 - i / 2],\n\t\t\t\t      r[4 - i / 2], r[3 - i / 2]);\n\t\tcase TEMPLATE_FIELD_SIP3:\n\t\tcase TEMPLATE_FIELD_SIP4:\n\t\tcase TEMPLATE_FIELD_SIP5:\n\t\tcase TEMPLATE_FIELD_SIP6:\n\t\tcase TEMPLATE_FIELD_SIP7:\n\t\t\tbreak;\n\n\t\tcase TEMPLATE_FIELD_DIP0:\n\t\t\tpr->dip = data;\n\t\t\tpr->dip_m = data_m;\n\t\t\tbreak;\n\t\tcase TEMPLATE_FIELD_DIP1:\n\t\t\tpr->dip = (pr->dip << 16) | data;\n\t\t\tpr->dip_m = (pr->dip << 16) | data_m;\n\t\t\tbreak;\n\t\tcase TEMPLATE_FIELD_DIP2:\n\t\t\tpr->is_ipv6 = true;\n\t\t\tipv6_addr_set(&pr->dip6, pr->dip, r[5 - i / 2],\n\t\t\t\t      r[4 - i / 2], r[3 - i / 2]);\n\t\t\tipv6_addr_set(&pr->dip6_m, pr->dip_m, r[5 - i / 2],\n\t\t\t\t      r[4 - i / 2], r[3 - i / 2]);\n\t\tcase TEMPLATE_FIELD_DIP3:\n\t\tcase TEMPLATE_FIELD_DIP4:\n\t\tcase TEMPLATE_FIELD_DIP5:\n\t\tcase TEMPLATE_FIELD_DIP6:\n\t\tcase TEMPLATE_FIELD_DIP7:\n\t\t\tbreak;\n\t\tcase TEMPLATE_FIELD_IP_TOS_PROTO:\n\t\t\tpr->tos_proto = data;\n\t\t\tpr->tos_proto_m = data_m;\n\t\t\tbreak;\n\t\tcase TEMPLATE_FIELD_L4_SPORT:\n\t\t\tpr->sport = data;\n\t\t\tpr->sport_m = data_m;\n\t\t\tbreak;\n\t\tcase TEMPLATE_FIELD_L4_DPORT:\n\t\t\tpr->dport = data;\n\t\t\tpr->dport_m = data_m;\n\t\t\tbreak;\n\t\tcase TEMPLATE_FIELD_ICMP_IGMP:\n\t\t\tpr->icmp_igmp = data;\n\t\t\tpr->icmp_igmp_m = data_m;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tpr_info(\"%s: unknown field %d\\n\", __func__, field_type);\n\t\t}\n\t}\n}\n\nstatic void rtl838x_read_pie_fixed_fields(u32 r[], struct pie_rule *pr)\n{\n\tpr->spmmask_fix = (r[6] >> 22) & 0x3;\n\tpr->spn = (r[6] >> 16) & 0x3f;\n\tpr->mgnt_vlan = (r[6] >> 15) & 1;\n\tpr->dmac_hit_sw = (r[6] >> 14) & 1;\n\tpr->not_first_frag = (r[6] >> 13) & 1;\n\tpr->frame_type_l4 = (r[6] >> 10) & 7;\n\tpr->frame_type = (r[6] >> 8) & 3;\n\tpr->otag_fmt = (r[6] >> 7) & 1;\n\tpr->itag_fmt = (r[6] >> 6) & 1;\n\tpr->otag_exist = (r[6] >> 5) & 1;\n\tpr->itag_exist = (r[6] >> 4) & 1;\n\tpr->frame_type_l2 = (r[6] >> 2) & 3;\n\tpr->tid = r[6] & 3;\n\n\tpr->spmmask_fix_m = (r[13] >> 22) & 0x3;\n\tpr->spn_m = (r[13] >> 16) & 0x3f;\n\tpr->mgnt_vlan_m = (r[13] >> 15) & 1;\n\tpr->dmac_hit_sw_m = (r[13] >> 14) & 1;\n\tpr->not_first_frag_m = (r[13] >> 13) & 1;\n\tpr->frame_type_l4_m = (r[13] >> 10) & 7;\n\tpr->frame_type_m = (r[13] >> 8) & 3;\n\tpr->otag_fmt_m = (r[13] >> 7) & 1;\n\tpr->itag_fmt_m = (r[13] >> 6) & 1;\n\tpr->otag_exist_m = (r[13] >> 5) & 1;\n\tpr->itag_exist_m = (r[13] >> 4) & 1;\n\tpr->frame_type_l2_m = (r[13] >> 2) & 3;\n\tpr->tid_m = r[13] & 3;\n\n\tpr->valid = r[14] & BIT(31);\n\tpr->cond_not = r[14] & BIT(30);\n\tpr->cond_and1 = r[14] & BIT(29);\n\tpr->cond_and2 = r[14] & BIT(28);\n\tpr->ivalid = r[14] & BIT(27);\n\n\tpr->drop = (r[17] >> 14) & 3;\n\tpr->fwd_sel = r[17] & BIT(13);\n\tpr->ovid_sel = r[17] & BIT(12);\n\tpr->ivid_sel = r[17] & BIT(11);\n\tpr->flt_sel = r[17] & BIT(10);\n\tpr->log_sel = r[17] & BIT(9);\n\tpr->rmk_sel = r[17] & BIT(8);\n\tpr->meter_sel = r[17] & BIT(7);\n\tpr->tagst_sel = r[17] & BIT(6);\n\tpr->mir_sel = r[17] & BIT(5);\n\tpr->nopri_sel = r[17] & BIT(4);\n\tpr->cpupri_sel = r[17] & BIT(3);\n\tpr->otpid_sel = r[17] & BIT(2);\n\tpr->itpid_sel = r[17] & BIT(1);\n\tpr->shaper_sel = r[17] & BIT(0);\n}\n\nstatic void rtl838x_write_pie_fixed_fields(u32 r[],  struct pie_rule *pr)\n{\n\tr[6] = ((u32) (pr->spmmask_fix & 0x3)) << 22;\n\tr[6] |= ((u32) (pr->spn & 0x3f)) << 16;\n\tr[6] |= pr->mgnt_vlan ? BIT(15) : 0;\n\tr[6] |= pr->dmac_hit_sw ? BIT(14) : 0;\n\tr[6] |= pr->not_first_frag ? BIT(13) : 0;\n\tr[6] |= ((u32) (pr->frame_type_l4 & 0x7)) << 10;\n\tr[6] |= ((u32) (pr->frame_type & 0x3)) << 8;\n\tr[6] |= pr->otag_fmt ? BIT(7) : 0;\n\tr[6] |= pr->itag_fmt ? BIT(6) : 0;\n\tr[6] |= pr->otag_exist ? BIT(5) : 0;\n\tr[6] |= pr->itag_exist ? BIT(4) : 0;\n\tr[6] |= ((u32) (pr->frame_type_l2 & 0x3)) << 2;\n\tr[6] |= ((u32) (pr->tid & 0x3));\n\n\tr[13] = ((u32) (pr->spmmask_fix_m & 0x3)) << 22;\n\tr[13] |= ((u32) (pr->spn_m & 0x3f)) << 16;\n\tr[13] |= pr->mgnt_vlan_m ? BIT(15) : 0;\n\tr[13] |= pr->dmac_hit_sw_m ? BIT(14) : 0;\n\tr[13] |= pr->not_first_frag_m ? BIT(13) : 0;\n\tr[13] |= ((u32) (pr->frame_type_l4_m & 0x7)) << 10;\n\tr[13] |= ((u32) (pr->frame_type_m & 0x3)) << 8;\n\tr[13] |= pr->otag_fmt_m ? BIT(7) : 0;\n\tr[13] |= pr->itag_fmt_m ? BIT(6) : 0;\n\tr[13] |= pr->otag_exist_m ? BIT(5) : 0;\n\tr[13] |= pr->itag_exist_m ? BIT(4) : 0;\n\tr[13] |= ((u32) (pr->frame_type_l2_m & 0x3)) << 2;\n\tr[13] |= ((u32) (pr->tid_m & 0x3));\n\n\tr[14] = pr->valid ? BIT(31) : 0;\n\tr[14] |= pr->cond_not ? BIT(30) : 0;\n\tr[14] |= pr->cond_and1 ? BIT(29) : 0;\n\tr[14] |= pr->cond_and2 ? BIT(28) : 0;\n\tr[14] |= pr->ivalid ? BIT(27) : 0;\n\n\tif (pr->drop)\n\t\tr[17] = 0x1 << 14;\t// Standard drop action\n\telse\n\t\tr[17] = 0;\n\tr[17] |= pr->fwd_sel ? BIT(13) : 0;\n\tr[17] |= pr->ovid_sel ? BIT(12) : 0;\n\tr[17] |= pr->ivid_sel ? BIT(11) : 0;\n\tr[17] |= pr->flt_sel ? BIT(10) : 0;\n\tr[17] |= pr->log_sel ? BIT(9) : 0;\n\tr[17] |= pr->rmk_sel ? BIT(8) : 0;\n\tr[17] |= pr->meter_sel ? BIT(7) : 0;\n\tr[17] |= pr->tagst_sel ? BIT(6) : 0;\n\tr[17] |= pr->mir_sel ? BIT(5) : 0;\n\tr[17] |= pr->nopri_sel ? BIT(4) : 0;\n\tr[17] |= pr->cpupri_sel ? BIT(3) : 0;\n\tr[17] |= pr->otpid_sel ? BIT(2) : 0;\n\tr[17] |= pr->itpid_sel ? BIT(1) : 0;\n\tr[17] |= pr->shaper_sel ? BIT(0) : 0;\n}\n\nstatic int rtl838x_write_pie_action(u32 r[],  struct pie_rule *pr)\n{\n\tu16 *aif = (u16 *)&r[17];\n\tu16 data;\n\tint fields_used = 0;\n\n\taif--;\n\n\tpr_debug(\"%s, at %08x\\n\", __func__, (u32)aif);\n\t/* Multiple actions can be linked to a match of a PIE rule,\n\t * they have different precedence depending on their type and this precedence\n\t * defines which Action Information Field (0-4) in the IACL table stores\n\t * the additional data of the action (like e.g. the port number a packet is\n\t * forwarded to) */\n\t// TODO: count bits in selectors to limit to a maximum number of actions\n\tif (pr->fwd_sel) { // Forwarding action\n\t\tdata = pr->fwd_act << 13;\n\t\tdata |= pr->fwd_data;\n\t\tdata |= pr->bypass_all ? BIT(12) : 0;\n\t\tdata |= pr->bypass_ibc_sc ? BIT(11) : 0;\n\t\tdata |= pr->bypass_igr_stp ? BIT(10) : 0;\n\t\t*aif-- = data;\n\t\tfields_used++;\n\t}\n\n\tif (pr->ovid_sel) { // Outer VID action\n\t\tdata = (pr->ovid_act & 0x3) << 12;\n\t\tdata |= pr->ovid_data;\n\t\t*aif-- = data;\n\t\tfields_used++;\n\t}\n\n\tif (pr->ivid_sel) { // Inner VID action\n\t\tdata = (pr->ivid_act & 0x3) << 12;\n\t\tdata |= pr->ivid_data;\n\t\t*aif-- = data;\n\t\tfields_used++;\n\t}\n\n\tif (pr->flt_sel) { // Filter action\n\t\t*aif-- = pr->flt_data;\n\t\tfields_used++;\n\t}\n\n\tif (pr->log_sel) { // Log action\n\t\tif (fields_used >= 4)\n\t\t\treturn -1;\n\t\t*aif-- = pr->log_data;\n\t\tfields_used++;\n\t}\n\n\tif (pr->rmk_sel) { // Remark action\n\t\tif (fields_used >= 4)\n\t\t\treturn -1;\n\t\t*aif-- = pr->rmk_data;\n\t\tfields_used++;\n\t}\n\n\tif (pr->meter_sel) { // Meter action\n\t\tif (fields_used >= 4)\n\t\t\treturn -1;\n\t\t*aif-- = pr->meter_data;\n\t\tfields_used++;\n\t}\n\n\tif (pr->tagst_sel) { // Egress Tag Status action\n\t\tif (fields_used >= 4)\n\t\t\treturn -1;\n\t\t*aif-- = pr->tagst_data;\n\t\tfields_used++;\n\t}\n\n\tif (pr->mir_sel) { // Mirror action\n\t\tif (fields_used >= 4)\n\t\t\treturn -1;\n\t\t*aif-- = pr->mir_data;\n\t\tfields_used++;\n\t}\n\n\tif (pr->nopri_sel) { // Normal Priority action\n\t\tif (fields_used >= 4)\n\t\t\treturn -1;\n\t\t*aif-- = pr->nopri_data;\n\t\tfields_used++;\n\t}\n\n\tif (pr->cpupri_sel) { // CPU Priority action\n\t\tif (fields_used >= 4)\n\t\t\treturn -1;\n\t\t*aif-- = pr->nopri_data;\n\t\tfields_used++;\n\t}\n\n\tif (pr->otpid_sel) { // OTPID action\n\t\tif (fields_used >= 4)\n\t\t\treturn -1;\n\t\t*aif-- = pr->otpid_data;\n\t\tfields_used++;\n\t}\n\n\tif (pr->itpid_sel) { // ITPID action\n\t\tif (fields_used >= 4)\n\t\t\treturn -1;\n\t\t*aif-- = pr->itpid_data;\n\t\tfields_used++;\n\t}\n\n\tif (pr->shaper_sel) { // Traffic shaper action\n\t\tif (fields_used >= 4)\n\t\t\treturn -1;\n\t\t*aif-- = pr->shaper_data;\n\t\tfields_used++;\n\t}\n\n\treturn 0;\n}\n\nstatic void rtl838x_read_pie_action(u32 r[],  struct pie_rule *pr)\n{\n\tu16 *aif = (u16 *)&r[17];\n\n\taif--;\n\n\tpr_debug(\"%s, at %08x\\n\", __func__, (u32)aif);\n\tif (pr->drop)\n\t\tpr_debug(\"%s: Action Drop: %d\", __func__, pr->drop);\n\n\tif (pr->fwd_sel){ // Forwarding action\n\t\tpr->fwd_act = *aif >> 13;\n\t\tpr->fwd_data = *aif--;\n\t\tpr->bypass_all = pr->fwd_data & BIT(12);\n\t\tpr->bypass_ibc_sc = pr->fwd_data & BIT(11);\n\t\tpr->bypass_igr_stp = pr->fwd_data & BIT(10);\n\t\tif (pr->bypass_all || pr->bypass_ibc_sc || pr->bypass_igr_stp)\n\t\t\tpr->bypass_sel = true;\n\t}\n\tif (pr->ovid_sel) // Outer VID action\n\t\tpr->ovid_data = *aif--;\n\tif (pr->ivid_sel) // Inner VID action\n\t\tpr->ivid_data = *aif--;\n\tif (pr->flt_sel) // Filter action\n\t\tpr->flt_data = *aif--;\n\tif (pr->log_sel) // Log action\n\t\tpr->log_data = *aif--;\n\tif (pr->rmk_sel) // Remark action\n\t\tpr->rmk_data = *aif--;\n\tif (pr->meter_sel) // Meter action\n\t\tpr->meter_data = *aif--;\n\tif (pr->tagst_sel) // Egress Tag Status action\n\t\tpr->tagst_data = *aif--;\n\tif (pr->mir_sel) // Mirror action\n\t\tpr->mir_data = *aif--;\n\tif (pr->nopri_sel) // Normal Priority action\n\t\tpr->nopri_data = *aif--;\n\tif (pr->cpupri_sel) // CPU Priority action\n\t\tpr->nopri_data = *aif--;\n\tif (pr->otpid_sel) // OTPID action\n\t\tpr->otpid_data = *aif--;\n\tif (pr->itpid_sel) // ITPID action\n\t\tpr->itpid_data = *aif--;\n\tif (pr->shaper_sel) // Traffic shaper action\n\t\tpr->shaper_data = *aif--;\n}\n\nstatic void rtl838x_pie_rule_dump_raw(u32 r[])\n{\n\tpr_info(\"Raw IACL table entry:\\n\");\n\tpr_info(\"Match  : %08x %08x %08x %08x %08x %08x\\n\", r[0], r[1], r[2], r[3], r[4], r[5]);\n\tpr_info(\"Fixed  : %08x\\n\", r[6]);\n\tpr_info(\"Match M: %08x %08x %08x %08x %08x %08x\\n\", r[7], r[8], r[9], r[10], r[11], r[12]);\n\tpr_info(\"Fixed M: %08x\\n\", r[13]);\n\tpr_info(\"AIF    : %08x %08x %08x\\n\", r[14], r[15], r[16]);\n\tpr_info(\"Sel    : %08x\\n\", r[17]);\n}\n\nstatic void rtl838x_pie_rule_dump(struct  pie_rule *pr)\n{\n\tpr_info(\"Drop: %d, fwd: %d, ovid: %d, ivid: %d, flt: %d, log: %d, rmk: %d, meter: %d tagst: %d, mir: %d, nopri: %d, cpupri: %d, otpid: %d, itpid: %d, shape: %d\\n\",\n\t\tpr->drop, pr->fwd_sel, pr->ovid_sel, pr->ivid_sel, pr->flt_sel, pr->log_sel, pr->rmk_sel, pr->log_sel, pr->tagst_sel, pr->mir_sel, pr->nopri_sel,\n\t\tpr->cpupri_sel, pr->otpid_sel, pr->itpid_sel, pr->shaper_sel);\n\tif (pr->fwd_sel)\n\t\tpr_info(\"FWD: %08x\\n\", pr->fwd_data);\n\tpr_info(\"TID: %x, %x\\n\", pr->tid, pr->tid_m);\n}\n\nstatic int rtl838x_pie_rule_read(struct rtl838x_switch_priv *priv, int idx, struct  pie_rule *pr)\n{\n\t// Read IACL table (1) via register 0\n\tstruct table_reg *q = rtl_table_get(RTL8380_TBL_0, 1);\n\tu32 r[18];\n\tint i;\n\tint block = idx / PIE_BLOCK_SIZE;\n\tu32 t_select = sw_r32(RTL838X_ACL_BLK_TMPLTE_CTRL(block));\n\n\tmemset(pr, 0, sizeof(*pr));\n\trtl_table_read(q, idx);\n\tfor (i = 0; i < 18; i++)\n\t\tr[i] = sw_r32(rtl_table_data(q, i));\n\n\trtl_table_release(q);\n\n\trtl838x_read_pie_fixed_fields(r, pr);\n\tif (!pr->valid)\n\t\treturn 0;\n\n\tpr_info(\"%s: template_selectors %08x, tid: %d\\n\", __func__, t_select, pr->tid);\n\trtl838x_pie_rule_dump_raw(r);\n\n\trtl838x_read_pie_templated(r, pr, fixed_templates[(t_select >> (pr->tid * 3)) & 0x7]);\n\n\trtl838x_read_pie_action(r, pr);\n\n\treturn 0;\n}\n\nstatic int rtl838x_pie_rule_write(struct rtl838x_switch_priv *priv, int idx, struct pie_rule *pr)\n{\n\t// Access IACL table (1) via register 0\n\tstruct table_reg *q = rtl_table_get(RTL8380_TBL_0, 1);\n\tu32 r[18];\n\tint i, err = 0;\n\tint block = idx / PIE_BLOCK_SIZE;\n\tu32 t_select = sw_r32(RTL838X_ACL_BLK_TMPLTE_CTRL(block));\n\n\tpr_debug(\"%s: %d, t_select: %08x\\n\", __func__, idx, t_select);\n\n\tfor (i = 0; i < 18; i++)\n\t\tr[i] = 0;\n\n\tif (!pr->valid)\n\t\tgoto err_out;\n\n\trtl838x_write_pie_fixed_fields(r, pr);\n\n\tpr_debug(\"%s: template %d\\n\", __func__, (t_select >> (pr->tid * 3)) & 0x7);\n\trtl838x_write_pie_templated(r, pr, fixed_templates[(t_select >> (pr->tid * 3)) & 0x7]);\n\n\tif (rtl838x_write_pie_action(r, pr)) {\n\t\tpr_err(\"Rule actions too complex\\n\");\n\t\tgoto err_out;\n\t}\n\n//\trtl838x_pie_rule_dump_raw(r);\n\n\tfor (i = 0; i < 18; i++)\n\t\tsw_w32(r[i], rtl_table_data(q, i));\n\nerr_out:\n\trtl_table_write(q, idx);\n\trtl_table_release(q);\n\n\treturn err;\n}\n\nstatic bool rtl838x_pie_templ_has(int t, enum template_field_id field_type)\n{\n\tint i;\n\tenum template_field_id ft;\n\n\tfor (i = 0; i < N_FIXED_FIELDS; i++) {\n\t\tft = fixed_templates[t][i];\n\t\tif (field_type == ft)\n\t\t\treturn true;\n\t}\n\n\treturn false;\n}\n\nstatic int rtl838x_pie_verify_template(struct rtl838x_switch_priv *priv,\n\t\t\t\t       struct pie_rule *pr, int t, int block)\n{\n\tint i;\n\n\tif (!pr->is_ipv6 && pr->sip_m && !rtl838x_pie_templ_has(t, TEMPLATE_FIELD_SIP0))\n\t\treturn -1;\n\n\tif (!pr->is_ipv6 && pr->dip_m && !rtl838x_pie_templ_has(t, TEMPLATE_FIELD_DIP0))\n\t\treturn -1;\n\n\tif (pr->is_ipv6) {\n\t\tif ((pr->sip6_m.s6_addr32[0] || pr->sip6_m.s6_addr32[1]\n\t\t\t|| pr->sip6_m.s6_addr32[2] || pr->sip6_m.s6_addr32[3])\n\t\t\t&& !rtl838x_pie_templ_has(t, TEMPLATE_FIELD_SIP2))\n\t\t\treturn -1;\n\t\tif ((pr->dip6_m.s6_addr32[0] || pr->dip6_m.s6_addr32[1]\n\t\t\t|| pr->dip6_m.s6_addr32[2] || pr->dip6_m.s6_addr32[3])\n\t\t\t&& !rtl838x_pie_templ_has(t, TEMPLATE_FIELD_DIP2))\n\t\t\treturn -1;\n\t}\n\n\tif (ether_addr_to_u64(pr->smac) && !rtl838x_pie_templ_has(t, TEMPLATE_FIELD_SMAC0))\n\t\treturn -1;\n\n\tif (ether_addr_to_u64(pr->dmac) && !rtl838x_pie_templ_has(t, TEMPLATE_FIELD_DMAC0))\n\t\treturn -1;\n\n\t// TODO: Check more\n\n\ti = find_first_zero_bit(&priv->pie_use_bm[block * 4], PIE_BLOCK_SIZE);\n\n\tif (i >= PIE_BLOCK_SIZE)\n\t\treturn -1;\n\n\treturn i + PIE_BLOCK_SIZE * block;\n}\n\nstatic int rtl838x_pie_rule_add(struct rtl838x_switch_priv *priv, struct pie_rule *pr)\n{\n\tint idx, block, j, t;\n\n\tpr_debug(\"In %s\\n\", __func__);\n\n\tmutex_lock(&priv->pie_mutex);\n\n\tfor (block = 0; block < priv->n_pie_blocks; block++) {\n\t\tfor (j = 0; j < 3; j++) {\n\t\t\tt = (sw_r32(RTL838X_ACL_BLK_TMPLTE_CTRL(block)) >> (j * 3)) & 0x7;\n\t\t\tpr_debug(\"Testing block %d, template %d, template id %d\\n\", block, j, t);\n\t\t\tidx = rtl838x_pie_verify_template(priv, pr, t, block);\n\t\t\tif (idx >= 0)\n\t\t\t\tbreak;\n\t\t}\n\t\tif (j < 3)\n\t\t\tbreak;\n\t}\n\n\tif (block >= priv->n_pie_blocks) {\n\t\tmutex_unlock(&priv->pie_mutex);\n\t\treturn -EOPNOTSUPP;\n\t}\n\n\tpr_debug(\"Using block: %d, index %d, template-id %d\\n\", block, idx, j);\n\tset_bit(idx, priv->pie_use_bm);\n\n\tpr->valid = true;\n\tpr->tid = j;  // Mapped to template number\n\tpr->tid_m = 0x3;\n\tpr->id = idx;\n\n\trtl838x_pie_lookup_enable(priv, idx);\n\trtl838x_pie_rule_write(priv, idx, pr);\n\n\tmutex_unlock(&priv->pie_mutex);\n\treturn 0;\n}\n\nstatic void rtl838x_pie_rule_rm(struct rtl838x_switch_priv *priv, struct pie_rule *pr)\n{\n\tint idx = pr->id;\n\n\trtl838x_pie_rule_del(priv, idx, idx);\n\tclear_bit(idx, priv->pie_use_bm);\n}\n\n/*\n * Initializes the Packet Inspection Engine:\n * powers it up, enables default matching templates for all blocks\n * and clears all rules possibly installed by u-boot\n */\nstatic void rtl838x_pie_init(struct rtl838x_switch_priv *priv)\n{\n\tint i;\n\tu32 template_selectors;\n\n\tmutex_init(&priv->pie_mutex);\n\n\t// Enable ACL lookup on all ports, including CPU_PORT\n\tfor (i = 0; i <= priv->cpu_port; i++)\n\t\tsw_w32(1, RTL838X_ACL_PORT_LOOKUP_CTRL(i));\n\n\t// Power on all PIE blocks\n\tfor (i = 0; i < priv->n_pie_blocks; i++)\n\t\tsw_w32_mask(0, BIT(i), RTL838X_ACL_BLK_PWR_CTRL);\n\n\t// Include IPG in metering\n\tsw_w32(1, RTL838X_METER_GLB_CTRL);\n\n\t// Delete all present rules\n\trtl838x_pie_rule_del(priv, 0, priv->n_pie_blocks * PIE_BLOCK_SIZE - 1);\n\n\t// Routing bypasses source port filter: disable write-protection, first\n\tsw_w32_mask(0, 3, RTL838X_INT_RW_CTRL);\n\tsw_w32_mask(0, 1, RTL838X_DMY_REG27);\n\tsw_w32_mask(3, 0, RTL838X_INT_RW_CTRL);\n\n\t// Enable predefined templates 0, 1 and 2 for even blocks\n\ttemplate_selectors = 0 | (1 << 3) | (2 << 6);\n\tfor (i = 0; i < 6; i += 2)\n\t\tsw_w32(template_selectors, RTL838X_ACL_BLK_TMPLTE_CTRL(i));\n\n\t// Enable predefined templates 0, 3 and 4 (IPv6 support) for odd blocks\n\ttemplate_selectors = 0 | (3 << 3) | (4 << 6);\n\tfor (i = 1; i < priv->n_pie_blocks; i += 2)\n\t\tsw_w32(template_selectors, RTL838X_ACL_BLK_TMPLTE_CTRL(i));\n\n\t// Group each pair of physical blocks together to a logical block\n\tsw_w32(0b10101010101, RTL838X_ACL_BLK_GROUP_CTRL);\n}\n\nstatic u32 rtl838x_packet_cntr_read(int counter)\n{\n\tu32 v;\n\n\t// Read LOG table (3) via register RTL8380_TBL_0\n\tstruct table_reg *r = rtl_table_get(RTL8380_TBL_0, 3);\n\n\tpr_debug(\"In %s, id %d\\n\", __func__, counter);\n\trtl_table_read(r, counter / 2);\n\n\tpr_debug(\"Registers: %08x %08x\\n\",\n\t\tsw_r32(rtl_table_data(r, 0)), sw_r32(rtl_table_data(r, 1)));\n\t// The table has a size of 2 registers\n\tif (counter % 2)\n\t\tv = sw_r32(rtl_table_data(r, 0));\n\telse\n\t\tv = sw_r32(rtl_table_data(r, 1));\n\n\trtl_table_release(r);\n\n\treturn v;\n}\n\nstatic void rtl838x_packet_cntr_clear(int counter)\n{\n\t// Access LOG table (3) via register RTL8380_TBL_0\n\tstruct table_reg *r = rtl_table_get(RTL8380_TBL_0, 3);\n\n\tpr_debug(\"In %s, id %d\\n\", __func__, counter);\n\t// The table has a size of 2 registers\n\tif (counter % 2)\n\t\tsw_w32(0, rtl_table_data(r, 0));\n\telse\n\t\tsw_w32(0, rtl_table_data(r, 1));\n\n\trtl_table_write(r, counter / 2);\n\n\trtl_table_release(r);\n}\n\nstatic void rtl838x_route_read(int idx, struct rtl83xx_route *rt)\n{\n\t// Read ROUTING table (2) via register RTL8380_TBL_1\n\tstruct table_reg *r = rtl_table_get(RTL8380_TBL_1, 2);\n\n\tpr_debug(\"In %s, id %d\\n\", __func__, idx);\n\trtl_table_read(r, idx);\n\n\t// The table has a size of 2 registers\n\trt->nh.gw = sw_r32(rtl_table_data(r, 0));\n\trt->nh.gw <<= 32;\n\trt->nh.gw |= sw_r32(rtl_table_data(r, 1));\n\n\trtl_table_release(r);\n}\n\nstatic void rtl838x_route_write(int idx, struct rtl83xx_route *rt)\n{\n\t// Access ROUTING table (2) via register RTL8380_TBL_1\n\tstruct table_reg *r = rtl_table_get(RTL8380_TBL_1, 2);\n\n\tpr_debug(\"In %s, id %d, gw: %016llx\\n\", __func__, idx, rt->nh.gw);\n\tsw_w32(rt->nh.gw >> 32, rtl_table_data(r, 0));\n\tsw_w32(rt->nh.gw, rtl_table_data(r, 1));\n\trtl_table_write(r, idx);\n\n\trtl_table_release(r);\n}\n\nstatic int rtl838x_l3_setup(struct rtl838x_switch_priv *priv)\n{\n\t// Nothing to be done\n\treturn 0;\n}\n\nvoid rtl838x_vlan_port_pvidmode_set(int port, enum pbvlan_type type, enum pbvlan_mode mode)\n{\n\tif (type == PBVLAN_TYPE_INNER)\n\t\tsw_w32_mask(0x3, mode, RTL838X_VLAN_PORT_PB_VLAN + (port << 2));\n\telse\n\t\tsw_w32_mask(0x3 << 14, mode << 14, RTL838X_VLAN_PORT_PB_VLAN + (port << 2));\n}\n\nvoid rtl838x_vlan_port_pvid_set(int port, enum pbvlan_type type, int pvid)\n{\n\tif (type == PBVLAN_TYPE_INNER)\n\t\tsw_w32_mask(0xfff << 2, pvid << 2, RTL838X_VLAN_PORT_PB_VLAN + (port << 2));\n\telse\n\t\tsw_w32_mask(0xfff << 16, pvid << 16, RTL838X_VLAN_PORT_PB_VLAN + (port << 2));\n}\n\nstatic int rtl838x_set_ageing_time(unsigned long msec)\n{\n\tint t = sw_r32(RTL838X_L2_CTRL_1);\n\n\tt &= 0x7FFFFF;\n\tt = t * 128 / 625; /* Aging time in seconds. 0: L2 aging disabled */\n\tpr_debug(\"L2 AGING time: %d sec\\n\", t);\n\n\tt = (msec * 625 + 127000) / 128000;\n\tt = t > 0x7FFFFF ? 0x7FFFFF : t;\n\tsw_w32_mask(0x7FFFFF, t, RTL838X_L2_CTRL_1);\n\tpr_debug(\"Dynamic aging for ports: %x\\n\", sw_r32(RTL838X_L2_PORT_AGING_OUT));\n\n\treturn 0;\n}\n\nstatic void rtl838x_set_igr_filter(int port, enum igr_filter state)\n{\n\tsw_w32_mask(0x3 << ((port & 0xf)<<1), state << ((port & 0xf)<<1),\n\t\t    RTL838X_VLAN_PORT_IGR_FLTR + (((port >> 4) << 2)));\n}\n\nstatic void rtl838x_set_egr_filter(int port, enum egr_filter state)\n{\n\tsw_w32_mask(0x1 << (port % 0x1d), state << (port % 0x1d),\n\t\t    RTL838X_VLAN_PORT_EGR_FLTR + (((port / 29) << 2)));\n}\n\nvoid rtl838x_set_distribution_algorithm(int group, int algoidx, u32 algomsk)\n{\n\talgoidx &= 1; // RTL838X only supports 2 concurrent algorithms\n\tsw_w32_mask(1 << (group % 8), algoidx << (group % 8),\n\t\t    RTL838X_TRK_HASH_IDX_CTRL + ((group >> 3) << 2));\n\tsw_w32(algomsk, RTL838X_TRK_HASH_CTRL + (algoidx << 2));\n}\n\nvoid rtl838x_set_receive_management_action(int port, rma_ctrl_t type, action_type_t action)\n{\n\tswitch(type) {\n\tcase BPDU:\n\t\tsw_w32_mask(3 << ((port & 0xf) << 1), (action & 0x3) << ((port & 0xf) << 1),\n\t\t\t    RTL838X_RMA_BPDU_CTRL + ((port >> 4) << 2));\n\tbreak;\n\tcase PTP:\n\t\tsw_w32_mask(3 << ((port & 0xf) << 1), (action & 0x3) << ((port & 0xf) << 1),\n\t\t\t    RTL838X_RMA_PTP_CTRL + ((port >> 4) << 2));\n\tbreak;\n\tcase LLTP:\n\t\tsw_w32_mask(3 << ((port & 0xf) << 1), (action & 0x3) << ((port & 0xf) << 1),\n\t\t\t    RTL838X_RMA_LLTP_CTRL + ((port >> 4) << 2));\n\tbreak;\n\tdefault:\n\tbreak;\n\t}\n}\n\nconst struct rtl838x_reg rtl838x_reg = {\n\t.mask_port_reg_be = rtl838x_mask_port_reg,\n\t.set_port_reg_be = rtl838x_set_port_reg,\n\t.get_port_reg_be = rtl838x_get_port_reg,\n\t.mask_port_reg_le = rtl838x_mask_port_reg,\n\t.set_port_reg_le = rtl838x_set_port_reg,\n\t.get_port_reg_le = rtl838x_get_port_reg,\n\t.stat_port_rst = RTL838X_STAT_PORT_RST,\n\t.stat_rst = RTL838X_STAT_RST,\n\t.stat_port_std_mib = RTL838X_STAT_PORT_STD_MIB,\n\t.port_iso_ctrl = rtl838x_port_iso_ctrl,\n\t.traffic_enable = rtl838x_traffic_enable,\n\t.traffic_disable = rtl838x_traffic_disable,\n\t.traffic_get = rtl838x_traffic_get,\n\t.traffic_set = rtl838x_traffic_set,\n\t.l2_ctrl_0 = RTL838X_L2_CTRL_0,\n\t.l2_ctrl_1 = RTL838X_L2_CTRL_1,\n\t.l2_port_aging_out = RTL838X_L2_PORT_AGING_OUT,\n\t.set_ageing_time = rtl838x_set_ageing_time,\n\t.smi_poll_ctrl = RTL838X_SMI_POLL_CTRL,\n\t.l2_tbl_flush_ctrl = RTL838X_L2_TBL_FLUSH_CTRL,\n\t.exec_tbl0_cmd = rtl838x_exec_tbl0_cmd,\n\t.exec_tbl1_cmd = rtl838x_exec_tbl1_cmd,\n\t.tbl_access_data_0 = rtl838x_tbl_access_data_0,\n\t.isr_glb_src = RTL838X_ISR_GLB_SRC,\n\t.isr_port_link_sts_chg = RTL838X_ISR_PORT_LINK_STS_CHG,\n\t.imr_port_link_sts_chg = RTL838X_IMR_PORT_LINK_STS_CHG,\n\t.imr_glb = RTL838X_IMR_GLB,\n\t.vlan_tables_read = rtl838x_vlan_tables_read,\n\t.vlan_set_tagged = rtl838x_vlan_set_tagged,\n\t.vlan_set_untagged = rtl838x_vlan_set_untagged,\n\t.mac_force_mode_ctrl = rtl838x_mac_force_mode_ctrl,\n\t.vlan_profile_dump = rtl838x_vlan_profile_dump,\n\t.vlan_profile_setup = rtl838x_vlan_profile_setup,\n\t.vlan_fwd_on_inner = rtl838x_vlan_fwd_on_inner,\n\t.set_vlan_igr_filter = rtl838x_set_igr_filter,\n\t.set_vlan_egr_filter = rtl838x_set_egr_filter,\n\t.enable_learning = rtl838x_enable_learning,\n\t.enable_flood = rtl838x_enable_flood,\n\t.enable_mcast_flood = rtl838x_enable_mcast_flood,\n\t.enable_bcast_flood = rtl838x_enable_bcast_flood,\n\t.stp_get = rtl838x_stp_get,\n\t.stp_set = rtl838x_stp_set,\n\t.mac_port_ctrl = rtl838x_mac_port_ctrl,\n\t.l2_port_new_salrn = rtl838x_l2_port_new_salrn,\n\t.l2_port_new_sa_fwd = rtl838x_l2_port_new_sa_fwd,\n\t.mir_ctrl = RTL838X_MIR_CTRL,\n\t.mir_dpm = RTL838X_MIR_DPM_CTRL,\n\t.mir_spm = RTL838X_MIR_SPM_CTRL,\n\t.mac_link_sts = RTL838X_MAC_LINK_STS,\n\t.mac_link_dup_sts = RTL838X_MAC_LINK_DUP_STS,\n\t.mac_link_spd_sts = rtl838x_mac_link_spd_sts,\n\t.mac_rx_pause_sts = RTL838X_MAC_RX_PAUSE_STS,\n\t.mac_tx_pause_sts = RTL838X_MAC_TX_PAUSE_STS,\n\t.read_l2_entry_using_hash = rtl838x_read_l2_entry_using_hash,\n\t.write_l2_entry_using_hash = rtl838x_write_l2_entry_using_hash,\n\t.read_cam = rtl838x_read_cam,\n\t.write_cam = rtl838x_write_cam,\n\t.vlan_port_tag_sts_ctrl = RTL838X_VLAN_PORT_TAG_STS_CTRL,\n\t.vlan_port_pvidmode_set = rtl838x_vlan_port_pvidmode_set,\n\t.vlan_port_pvid_set = rtl838x_vlan_port_pvid_set,\n\t.trk_mbr_ctr = rtl838x_trk_mbr_ctr,\n\t.rma_bpdu_fld_pmask = RTL838X_RMA_BPDU_FLD_PMSK,\n\t.spcl_trap_eapol_ctrl = RTL838X_SPCL_TRAP_EAPOL_CTRL,\n\t.init_eee = rtl838x_init_eee,\n\t.port_eee_set = rtl838x_port_eee_set,\n\t.eee_port_ability = rtl838x_eee_port_ability,\n\t.l2_hash_seed = rtl838x_l2_hash_seed, \n\t.l2_hash_key = rtl838x_l2_hash_key,\n\t.read_mcast_pmask = rtl838x_read_mcast_pmask,\n\t.write_mcast_pmask = rtl838x_write_mcast_pmask,\n\t.pie_init = rtl838x_pie_init,\n\t.pie_rule_read = rtl838x_pie_rule_read,\n\t.pie_rule_write = rtl838x_pie_rule_write,\n\t.pie_rule_add = rtl838x_pie_rule_add,\n\t.pie_rule_rm = rtl838x_pie_rule_rm,\n\t.l2_learning_setup = rtl838x_l2_learning_setup,\n\t.packet_cntr_read = rtl838x_packet_cntr_read,\n\t.packet_cntr_clear = rtl838x_packet_cntr_clear,\n\t.route_read = rtl838x_route_read,\n\t.route_write = rtl838x_route_write,\n\t.l3_setup = rtl838x_l3_setup,\n\t.set_distribution_algorithm = rtl838x_set_distribution_algorithm,\n\t.set_receive_management_action = rtl838x_set_receive_management_action,\n};\n\nirqreturn_t rtl838x_switch_irq(int irq, void *dev_id)\n{\n\tstruct dsa_switch *ds = dev_id;\n\tu32 status = sw_r32(RTL838X_ISR_GLB_SRC);\n\tu32 ports = sw_r32(RTL838X_ISR_PORT_LINK_STS_CHG);\n\tu32 link;\n\tint i;\n\n\t/* Clear status */\n\tsw_w32(ports, RTL838X_ISR_PORT_LINK_STS_CHG);\n\tpr_info(\"RTL8380 Link change: status: %x, ports %x\\n\", status, ports);\n\n\tfor (i = 0; i < 28; i++) {\n\t\tif (ports & BIT(i)) {\n\t\t\tlink = sw_r32(RTL838X_MAC_LINK_STS);\n\t\t\tif (link & BIT(i))\n\t\t\t\tdsa_port_phylink_mac_change(ds, i, true);\n\t\t\telse\n\t\t\t\tdsa_port_phylink_mac_change(ds, i, false);\n\t\t}\n\t}\n\treturn IRQ_HANDLED;\n}\n\nint rtl838x_smi_wait_op(int timeout)\n{\n\tdo {\n\t\ttimeout--;\n\t\tudelay(10);\n\t} while ((sw_r32(RTL838X_SMI_ACCESS_PHY_CTRL_1) & 0x1) && (timeout >= 0));\n\tif (timeout <= 0)\n\t\treturn -1;\n\treturn 0;\n}\n\n/*\n * Reads a register in a page from the PHY\n */\nint rtl838x_read_phy(u32 port, u32 page, u32 reg, u32 *val)\n{\n\tu32 v;\n\tu32 park_page;\n\n\tif (port > 31) {\n\t\t*val = 0xffff;\n\t\treturn 0;\n\t}\n\n\tif (page > 4095 || reg > 31)\n\t\treturn -ENOTSUPP;\n\n\tmutex_lock(&smi_lock);\n\n\tif (rtl838x_smi_wait_op(10000))\n\t\tgoto timeout;\n\n\tsw_w32_mask(0xffff0000, port << 16, RTL838X_SMI_ACCESS_PHY_CTRL_2);\n\n\tpark_page = sw_r32(RTL838X_SMI_ACCESS_PHY_CTRL_1) & ((0x1f << 15) | 0x2);\n\tv = reg << 20 | page << 3;\n\tsw_w32(v | park_page, RTL838X_SMI_ACCESS_PHY_CTRL_1);\n\tsw_w32_mask(0, 1, RTL838X_SMI_ACCESS_PHY_CTRL_1);\n\n\tif (rtl838x_smi_wait_op(10000))\n\t\tgoto timeout;\n\n\t*val = sw_r32(RTL838X_SMI_ACCESS_PHY_CTRL_2) & 0xffff;\n\n\tmutex_unlock(&smi_lock);\n\treturn 0;\n\ntimeout:\n\tmutex_unlock(&smi_lock);\n\treturn -ETIMEDOUT;\n}\n\n/*\n * Write to a register in a page of the PHY\n */\nint rtl838x_write_phy(u32 port, u32 page, u32 reg, u32 val)\n{\n\tu32 v;\n\tu32 park_page;\n\n\tval &= 0xffff;\n\tif (port > 31 || page > 4095 || reg > 31)\n\t\treturn -ENOTSUPP;\n\n\tmutex_lock(&smi_lock);\n\tif (rtl838x_smi_wait_op(10000))\n\t\tgoto timeout;\n\n\tsw_w32(BIT(port), RTL838X_SMI_ACCESS_PHY_CTRL_0);\n\tmdelay(10);\n\n\tsw_w32_mask(0xffff0000, val << 16, RTL838X_SMI_ACCESS_PHY_CTRL_2);\n\n\tpark_page = sw_r32(RTL838X_SMI_ACCESS_PHY_CTRL_1) & ((0x1f << 15) | 0x2);\n\tv = reg << 20 | page << 3 | 0x4;\n\tsw_w32(v | park_page, RTL838X_SMI_ACCESS_PHY_CTRL_1);\n\tsw_w32_mask(0, 1, RTL838X_SMI_ACCESS_PHY_CTRL_1);\n\n\tif (rtl838x_smi_wait_op(10000))\n\t\tgoto timeout;\n\n\tmutex_unlock(&smi_lock);\n\treturn 0;\n\ntimeout:\n\tmutex_unlock(&smi_lock);\n\treturn -ETIMEDOUT;\n}\n\n/*\n * Read an mmd register of a PHY\n */\nint rtl838x_read_mmd_phy(u32 port, u32 addr, u32 reg, u32 *val)\n{\n\tu32 v;\n\n\tmutex_lock(&smi_lock);\n\n\tif (rtl838x_smi_wait_op(10000))\n\t\tgoto timeout;\n\n\tsw_w32(1 << port, RTL838X_SMI_ACCESS_PHY_CTRL_0);\n\tmdelay(10);\n\n\tsw_w32_mask(0xffff0000, port << 16, RTL838X_SMI_ACCESS_PHY_CTRL_2);\n\n\tv = addr << 16 | reg;\n\tsw_w32(v, RTL838X_SMI_ACCESS_PHY_CTRL_3);\n\n\t/* mmd-access | read | cmd-start */\n\tv = 1 << 1 | 0 << 2 | 1;\n\tsw_w32(v, RTL838X_SMI_ACCESS_PHY_CTRL_1);\n\n\tif (rtl838x_smi_wait_op(10000))\n\t\tgoto timeout;\n\n\t*val = sw_r32(RTL838X_SMI_ACCESS_PHY_CTRL_2) & 0xffff;\n\n\tmutex_unlock(&smi_lock);\n\treturn 0;\n\ntimeout:\n\tmutex_unlock(&smi_lock);\n\treturn -ETIMEDOUT;\n}\n\n/*\n * Write to an mmd register of a PHY\n */\nint rtl838x_write_mmd_phy(u32 port, u32 addr, u32 reg, u32 val)\n{\n\tu32 v;\n\n\tpr_debug(\"MMD write: port %d, dev %d, reg %d, val %x\\n\", port, addr, reg, val);\n\tval &= 0xffff;\n\tmutex_lock(&smi_lock);\n\n\tif (rtl838x_smi_wait_op(10000))\n\t\tgoto timeout;\n\n\tsw_w32(1 << port, RTL838X_SMI_ACCESS_PHY_CTRL_0);\n\tmdelay(10);\n\n\tsw_w32_mask(0xffff0000, val << 16, RTL838X_SMI_ACCESS_PHY_CTRL_2);\n\n\tsw_w32_mask(0x1f << 16, addr << 16, RTL838X_SMI_ACCESS_PHY_CTRL_3);\n\tsw_w32_mask(0xffff, reg, RTL838X_SMI_ACCESS_PHY_CTRL_3);\n\t/* mmd-access | write | cmd-start */\n\tv = 1 << 1 | 1 << 2 | 1;\n\tsw_w32(v, RTL838X_SMI_ACCESS_PHY_CTRL_1);\n\n\tif (rtl838x_smi_wait_op(10000))\n\t\tgoto timeout;\n\n\tmutex_unlock(&smi_lock);\n\treturn 0;\n\ntimeout:\n\tmutex_unlock(&smi_lock);\n\treturn -ETIMEDOUT;\n}\n\nvoid rtl8380_get_version(struct rtl838x_switch_priv *priv)\n{\n\tu32 rw_save, info_save;\n\tu32 info;\n\n\trw_save = sw_r32(RTL838X_INT_RW_CTRL);\n\tsw_w32(rw_save | 0x3, RTL838X_INT_RW_CTRL);\n\n\tinfo_save = sw_r32(RTL838X_CHIP_INFO);\n\tsw_w32(info_save | 0xA0000000, RTL838X_CHIP_INFO);\n\n\tinfo = sw_r32(RTL838X_CHIP_INFO);\n\tsw_w32(info_save, RTL838X_CHIP_INFO);\n\tsw_w32(rw_save, RTL838X_INT_RW_CTRL);\n\n\tif ((info & 0xFFFF) == 0x6275) {\n\t\tif (((info >> 16) & 0x1F) == 0x1)\n\t\t\tpriv->version = RTL8380_VERSION_A;\n\t\telse if (((info >> 16) & 0x1F) == 0x2)\n\t\t\tpriv->version = RTL8380_VERSION_B;\n\t\telse\n\t\t\tpriv->version = RTL8380_VERSION_B;\n\t} else {\n\t\tpriv->version = '-';\n\t}\n}\n\nvoid rtl838x_vlan_profile_dump(int profile)\n{\n\tu32 p;\n\n\tif (profile < 0 || profile > 7)\n\t\treturn;\n\n\tp = sw_r32(RTL838X_VLAN_PROFILE(profile));\n\n\tpr_info(\"VLAN profile %d: L2 learning: %d, UNKN L2MC FLD PMSK %d, \\\n\t\tUNKN IPMC FLD PMSK %d, UNKN IPv6MC FLD PMSK: %d\",\n\t\tprofile, p & 1, (p >> 1) & 0x1ff, (p >> 10) & 0x1ff, (p >> 19) & 0x1ff);\n}\n\nvoid rtl8380_sds_rst(int mac)\n{\n\tu32 offset = (mac == 24) ? 0 : 0x100;\n\n\tsw_w32_mask(1 << 11, 0, RTL838X_SDS4_FIB_REG0 + offset);\n\tsw_w32_mask(0x3, 0, RTL838X_SDS4_REG28 + offset);\n\tsw_w32_mask(0x3, 0x3, RTL838X_SDS4_REG28 + offset);\n\tsw_w32_mask(0, 0x1 << 6, RTL838X_SDS4_DUMMY0 + offset);\n\tsw_w32_mask(0x1 << 6, 0, RTL838X_SDS4_DUMMY0 + offset);\n\tpr_debug(\"SERDES reset: %d\\n\", mac);\n}\n\nint rtl8380_sds_power(int mac, int val)\n{\n\tu32 mode = (val == 1) ? 0x4 : 0x9;\n\tu32 offset = (mac == 24) ? 5 : 0;\n\n\tif ((mac != 24) && (mac != 26)) {\n\t\tpr_err(\"%s: not a fibre port: %d\\n\", __func__, mac);\n\t\treturn -1;\n\t}\n\n\tsw_w32_mask(0x1f << offset, mode << offset, RTL838X_SDS_MODE_SEL);\n\n\trtl8380_sds_rst(mac);\n\n\treturn 0;\n}\n"
  },
  {
    "path": "target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/rtl838x.h",
    "content": "/* SPDX-License-Identifier: GPL-2.0-only */\n\n#ifndef _RTL838X_H\n#define _RTL838X_H\n\n#include <net/dsa.h>\n\n/*\n * Register definition\n */\n#define RTL838X_MAC_PORT_CTRL(port)\t\t(0xd560 + (((port) << 7)))\n#define RTL839X_MAC_PORT_CTRL(port)\t\t(0x8004 + (((port) << 7)))\n#define RTL930X_MAC_PORT_CTRL(port)\t\t(0x3260 + (((port) << 6)))\n#define RTL931X_MAC_PORT_CTRL\t\t\t(0x6004)\n\n#define RTL930X_MAC_L2_PORT_CTRL(port)\t\t(0x3268 + (((port) << 6)))\n#define RTL931X_MAC_L2_PORT_CTRL\t\t(0x6000)\n\n#define RTL838X_RST_GLB_CTRL_0\t\t\t(0x003c)\n\n#define RTL838X_MAC_FORCE_MODE_CTRL\t\t(0xa104)\n#define RTL839X_MAC_FORCE_MODE_CTRL\t\t(0x02bc)\n#define RTL930X_MAC_FORCE_MODE_CTRL\t\t(0xCA1C)\n#define RTL931X_MAC_FORCE_MODE_CTRL\t\t(0x0DCC)\n\n#define RTL838X_DMY_REG31\t\t\t(0x3b28)\n#define RTL838X_SDS_MODE_SEL\t\t\t(0x0028)\n#define RTL838X_SDS_CFG_REG\t\t\t(0x0034)\n#define RTL838X_INT_MODE_CTRL\t\t\t(0x005c)\n#define RTL838X_CHIP_INFO\t\t\t(0x00d8)\n#define RTL839X_CHIP_INFO\t\t\t(0x0ff4)\n#define RTL838X_PORT_ISO_CTRL(port)\t\t(0x4100 + ((port) << 2))\n#define RTL839X_PORT_ISO_CTRL(port)\t\t(0x1400 + ((port) << 3))\n\n/* Packet statistics */\n#define RTL838X_STAT_PORT_STD_MIB\t\t(0x1200)\n#define RTL839X_STAT_PORT_STD_MIB\t\t(0xC000)\n#define RTL930X_STAT_PORT_MIB_CNTR\t\t(0x0664)\n#define RTL838X_STAT_RST\t\t\t(0x3100)\n#define RTL839X_STAT_RST\t\t\t(0xF504)\n#define RTL930X_STAT_RST\t\t\t(0x3240)\n#define RTL931X_STAT_RST\t\t\t(0x7ef4)\n#define RTL838X_STAT_PORT_RST\t\t\t(0x3104)\n#define RTL839X_STAT_PORT_RST\t\t\t(0xF508)\n#define RTL930X_STAT_PORT_RST\t\t\t(0x3244)\n#define RTL931X_STAT_PORT_RST\t\t\t(0x7ef8)\n#define RTL838X_STAT_CTRL\t\t\t(0x3108)\n#define RTL839X_STAT_CTRL\t\t\t(0x04cc)\n#define RTL930X_STAT_CTRL\t\t\t(0x3248)\n#define RTL931X_STAT_CTRL\t\t\t(0x5720)\n\n/* Registers of the internal Serdes of the 8390 */\n#define RTL8390_SDS0_1_XSG0\t\t\t(0xA000)\n#define RTL8390_SDS0_1_XSG1\t\t\t(0xA100)\n#define RTL839X_SDS12_13_XSG0\t\t\t(0xB800)\n#define RTL839X_SDS12_13_XSG1\t\t\t(0xB900)\n#define RTL839X_SDS12_13_PWR0\t\t\t(0xb880)\n#define RTL839X_SDS12_13_PWR1\t\t\t(0xb980)\n\n/* Registers of the internal Serdes of the 8380 */\n#define RTL838X_SDS4_FIB_REG0\t\t\t(0xF800)\n#define RTL838X_SDS4_REG28\t\t\t(0xef80)\n#define RTL838X_SDS4_DUMMY0\t\t\t(0xef8c)\n#define RTL838X_SDS5_EXT_REG6\t\t\t(0xf18c)\n\n/* VLAN registers */\n#define RTL838X_VLAN_CTRL\t\t\t(0x3A74)\n#define RTL838X_VLAN_PROFILE(idx)\t\t(0x3A88 + ((idx) << 2))\n#define RTL838X_VLAN_PORT_EGR_FLTR\t\t(0x3A84)\n#define RTL838X_VLAN_PORT_PB_VLAN\t\t(0x3C00)\n#define RTL838X_VLAN_PORT_IGR_FLTR\t\t(0x3A7C)\n#define RTL838X_VLAN_PORT_TAG_STS_CTRL\t\t(0xA530)\n\n#define RTL839X_VLAN_PROFILE(idx)\t\t(0x25C0 + (((idx) << 3)))\n#define RTL839X_VLAN_CTRL\t\t\t(0x26D4)\n#define RTL839X_VLAN_PORT_PB_VLAN\t\t(0x26D8)\n#define RTL839X_VLAN_PORT_IGR_FLTR\t\t(0x27B4)\n#define RTL839X_VLAN_PORT_EGR_FLTR\t\t(0x27C4)\n#define RTL839X_VLAN_PORT_TAG_STS_CTRL\t\t(0x6828)\n#define RTL839X_VLAN_PORT_TAG_STS_CTRL\t\t(0x6828)\n\n#define RTL930X_VLAN_PROFILE_SET(idx)\t\t(0x9c60 + (((idx) * 20)))\n#define RTL930X_VLAN_CTRL\t\t\t(0x82D4)\n#define RTL930X_VLAN_PORT_PB_VLAN\t\t(0x82D8)\n#define RTL930X_VLAN_PORT_IGR_FLTR\t\t(0x83C0)\n#define RTL930X_VLAN_PORT_EGR_FLTR\t\t(0x83C8)\n#define RTL930X_VLAN_PORT_TAG_STS_CTRL\t\t(0xCE24)\n\n#define RTL931X_VLAN_PROFILE_SET(idx)\t\t(0x9800 + (((idx) * 28)))\n#define RTL931X_VLAN_CTRL\t\t\t(0x94E4)\n#define RTL931X_VLAN_PORT_IGR_CTRL\t\t(0x94E8)\n#define RTL931X_VLAN_PORT_IGR_FLTR\t\t(0x96B4)\n#define RTL931X_VLAN_PORT_EGR_FLTR\t\t(0x96C4)\n#define RTL931X_VLAN_PORT_TAG_CTRL\t\t(0x4860)\n\n/* Table access registers */\n#define RTL838X_TBL_ACCESS_CTRL_0\t\t(0x6914)\n#define RTL838X_TBL_ACCESS_DATA_0(idx)\t\t(0x6918 + ((idx) << 2))\n#define RTL838X_TBL_ACCESS_CTRL_1\t\t(0xA4C8)\n#define RTL838X_TBL_ACCESS_DATA_1(idx)\t\t(0xA4CC + ((idx) << 2))\n\n#define RTL839X_TBL_ACCESS_CTRL_0\t\t(0x1190)\n#define RTL839X_TBL_ACCESS_DATA_0(idx)\t\t(0x1194 + ((idx) << 2))\n#define RTL839X_TBL_ACCESS_CTRL_1\t\t(0x6b80)\n#define RTL839X_TBL_ACCESS_DATA_1(idx)\t\t(0x6b84 + ((idx) << 2))\n#define RTL839X_TBL_ACCESS_CTRL_2\t\t(0x611C)\n#define RTL839X_TBL_ACCESS_DATA_2(i)\t\t(0x6120 + (((i) << 2)))\n\n#define RTL930X_TBL_ACCESS_CTRL_0\t\t(0xB340)\n#define RTL930X_TBL_ACCESS_DATA_0(idx)\t\t(0xB344 + ((idx) << 2))\n#define RTL930X_TBL_ACCESS_CTRL_1\t\t(0xB3A0)\n#define RTL930X_TBL_ACCESS_DATA_1(idx)\t\t(0xB3A4 + ((idx) << 2))\n#define RTL930X_TBL_ACCESS_CTRL_2\t\t(0xCE04)\n#define RTL930X_TBL_ACCESS_DATA_2(i)\t\t(0xCE08 + (((i) << 2)))\n\n#define RTL931X_TBL_ACCESS_CTRL_0\t\t(0x8500)\n#define RTL931X_TBL_ACCESS_DATA_0(idx)\t\t(0x8508 + ((idx) << 2))\n#define RTL931X_TBL_ACCESS_CTRL_1\t\t(0x40C0)\n#define RTL931X_TBL_ACCESS_DATA_1(idx)\t\t(0x40C4 + ((idx) << 2))\n#define RTL931X_TBL_ACCESS_CTRL_2\t\t(0x8528)\n#define RTL931X_TBL_ACCESS_DATA_2(i)\t\t(0x852C + (((i) << 2)))\n#define RTL931X_TBL_ACCESS_CTRL_3\t\t(0x0200)\n#define RTL931X_TBL_ACCESS_DATA_3(i)\t\t(0x0204 + (((i) << 2)))\n#define RTL931X_TBL_ACCESS_CTRL_4\t\t(0x20DC)\n#define RTL931X_TBL_ACCESS_DATA_4(i)\t\t(0x20E0 + (((i) << 2)))\n#define RTL931X_TBL_ACCESS_CTRL_5\t\t(0x7E1C)\n#define RTL931X_TBL_ACCESS_DATA_5(i)\t\t(0x7E20 + (((i) << 2)))\n\n/* MAC handling */\n#define RTL838X_MAC_LINK_STS\t\t\t(0xa188)\n#define RTL839X_MAC_LINK_STS\t\t\t(0x0390)\n#define RTL930X_MAC_LINK_STS\t\t\t(0xCB10)\n#define RTL931X_MAC_LINK_STS\t\t\t(0x0EC0)\n#define RTL838X_MAC_LINK_SPD_STS(p)\t\t(0xa190 + (((p >> 4) << 2)))\n#define RTL839X_MAC_LINK_SPD_STS(p)\t\t(0x03a0 + (((p >> 4) << 2)))\n#define RTL930X_MAC_LINK_SPD_STS(p)\t\t(0xCB18 + (((p >> 3) << 2)))\n#define RTL931X_MAC_LINK_SPD_STS\t\t(0x0ED0)\n#define RTL838X_MAC_LINK_DUP_STS\t\t(0xa19c)\n#define RTL839X_MAC_LINK_DUP_STS\t\t(0x03b0)\n#define RTL930X_MAC_LINK_DUP_STS\t\t(0xCB28)\n#define RTL931X_MAC_LINK_DUP_STS\t\t(0x0EF0)\n#define RTL838X_MAC_TX_PAUSE_STS\t\t(0xa1a0)\n#define RTL839X_MAC_TX_PAUSE_STS\t\t(0x03b8)\n#define RTL930X_MAC_TX_PAUSE_STS\t\t(0xCB2C)\n#define RTL931X_MAC_TX_PAUSE_STS\t\t(0x0EF8)\n#define RTL838X_MAC_RX_PAUSE_STS\t\t(0xa1a4)\n#define RTL839X_MAC_RX_PAUSE_STS\t\t(0x03c0)\n#define RTL930X_MAC_RX_PAUSE_STS\t\t(0xCB30)\n#define RTL931X_MAC_RX_PAUSE_STS\t\t(0x0F00)\n#define RTL930X_MAC_LINK_MEDIA_STS\t\t(0xCB14)\n#define RTL931X_MAC_LINK_MEDIA_STS\t\t(0x0EC8)\n\n/* MAC link state bits */\n#define RTL838X_FORCE_EN\t\t\t(1 << 0)\n#define RTL838X_FORCE_LINK_EN\t\t\t(1 << 1)\n#define RTL838X_NWAY_EN\t\t\t\t(1 << 2)\n#define RTL838X_DUPLEX_MODE\t\t\t(1 << 3)\n#define RTL838X_TX_PAUSE_EN\t\t\t(1 << 6)\n#define RTL838X_RX_PAUSE_EN\t\t\t(1 << 7)\n#define RTL838X_MAC_FORCE_FC_EN\t\t\t(1 << 8)\n\n#define RTL839X_FORCE_EN\t\t\t(1 << 0)\n#define RTL839X_FORCE_LINK_EN\t\t\t(1 << 1)\n#define RTL839X_DUPLEX_MODE\t\t\t(1 << 2)\n#define RTL839X_TX_PAUSE_EN\t\t\t(1 << 5)\n#define RTL839X_RX_PAUSE_EN\t\t\t(1 << 6)\n#define RTL839X_MAC_FORCE_FC_EN\t\t\t(1 << 7)\n\n#define RTL930X_FORCE_EN\t\t\t(1 << 0)\n#define RTL930X_FORCE_LINK_EN\t\t\t(1 << 1)\n#define RTL930X_DUPLEX_MODE\t\t\t(1 << 2)\n#define RTL930X_TX_PAUSE_EN\t\t\t(1 << 7)\n#define RTL930X_RX_PAUSE_EN\t\t\t(1 << 8)\n#define RTL930X_MAC_FORCE_FC_EN\t\t\t(1 << 9)\n\n#define RTL931X_FORCE_EN\t\t\t(1 << 9)\n#define RTL931X_FORCE_LINK_EN\t\t\t(1 << 0)\n#define RTL931X_DUPLEX_MODE\t\t\t(1 << 2)\n#define RTL931X_MAC_FORCE_FC_EN\t\t\t(1 << 4)\n#define RTL931X_TX_PAUSE_EN\t\t\t(1 << 16)\n#define RTL931X_RX_PAUSE_EN\t\t\t(1 << 17)\n\n/* EEE */\n#define RTL838X_MAC_EEE_ABLTY\t\t\t(0xa1a8)\n#define RTL838X_EEE_PORT_TX_EN\t\t\t(0x014c)\n#define RTL838X_EEE_PORT_RX_EN\t\t\t(0x0150)\n#define RTL838X_EEE_CLK_STOP_CTRL\t\t(0x0148)\n#define RTL838X_EEE_TX_TIMER_GIGA_CTRL\t\t(0xaa04)\n#define RTL838X_EEE_TX_TIMER_GELITE_CTRL\t(0xaa08)\n\n#define RTL839X_EEE_TX_TIMER_GELITE_CTRL\t(0x042C)\n#define RTL839X_EEE_TX_TIMER_GIGA_CTRL\t\t(0x0430)\n#define RTL839X_EEE_TX_TIMER_10G_CTRL\t\t(0x0434)\n#define RTL839X_EEE_CTRL(p)\t\t\t(0x8008 + ((p) << 7))\n#define RTL839X_MAC_EEE_ABLTY\t\t\t(0x03C8)\n\n#define RTL930X_MAC_EEE_ABLTY\t\t\t(0xCB34)\n#define RTL930X_EEE_CTRL(p)\t\t\t(0x3274 + ((p) << 6))\n#define RTL930X_EEEP_PORT_CTRL(p)\t\t(0x3278 + ((p) << 6))\n\n/* L2 functionality */\n#define RTL838X_L2_CTRL_0\t\t\t(0x3200)\n#define RTL839X_L2_CTRL_0\t\t\t(0x3800)\n#define RTL930X_L2_CTRL\t\t\t\t(0x8FD8)\n#define RTL931X_L2_CTRL\t\t\t\t(0xC800)\n#define RTL838X_L2_CTRL_1\t\t\t(0x3204)\n#define RTL839X_L2_CTRL_1\t\t\t(0x3804)\n#define RTL930X_L2_AGE_CTRL\t\t\t(0x8FDC)\n#define RTL931X_L2_AGE_CTRL\t\t\t(0xC804)\n#define RTL838X_L2_PORT_AGING_OUT\t\t(0x3358)\n#define RTL839X_L2_PORT_AGING_OUT\t\t(0x3b74)\n#define\tRTL930X_L2_PORT_AGE_CTRL\t\t(0x8FE0)\n#define\tRTL931X_L2_PORT_AGE_CTRL\t\t(0xc808)\n#define RTL838X_TBL_ACCESS_L2_CTRL\t\t(0x6900)\n#define RTL839X_TBL_ACCESS_L2_CTRL\t\t(0x1180)\n#define RTL930X_TBL_ACCESS_L2_CTRL\t\t(0xB320)\n#define RTL930X_TBL_ACCESS_L2_METHOD_CTRL\t(0xB324)\n#define RTL838X_TBL_ACCESS_L2_DATA(idx)\t\t(0x6908 + ((idx) << 2))\n#define RTL839X_TBL_ACCESS_L2_DATA(idx)\t\t(0x1184 + ((idx) << 2))\n#define RTL930X_TBL_ACCESS_L2_DATA(idx)\t\t(0xab08 + ((idx) << 2))\n\n#define RTL838X_L2_TBL_FLUSH_CTRL\t\t(0x3370)\n#define RTL839X_L2_TBL_FLUSH_CTRL\t\t(0x3ba0)\n#define RTL930X_L2_TBL_FLUSH_CTRL\t\t(0x9404)\n#define RTL931X_L2_TBL_FLUSH_CTRL\t\t(0xCD9C)\n\n#define RTL838X_L2_LRN_CONSTRT\t\t\t(0x329C)\n#define RTL839X_L2_LRN_CONSTRT\t\t\t(0x3910)\n#define RTL930X_L2_LRN_CONSTRT_CTRL\t\t(0x909c)\n#define RTL931X_L2_LRN_CONSTRT_CTRL\t\t(0xC964)\n\n#define RTL838X_L2_FLD_PMSK\t\t\t(0x3288)\n#define RTL839X_L2_FLD_PMSK\t\t\t(0x38EC)\n#define RTL930X_L2_BC_FLD_PMSK\t\t\t(0x9068)\n#define RTL931X_L2_BC_FLD_PMSK\t\t\t(0xC8FC)\n\n#define RTL930X_L2_UNKN_UC_FLD_PMSK\t\t(0x9064)\n#define RTL931X_L2_UNKN_UC_FLD_PMSK\t\t(0xC8F4)\n\n#define RTL838X_L2_LRN_CONSTRT_EN\t\t(0x3368)\n#define RTL838X_L2_PORT_LRN_CONSTRT\t\t(0x32A0)\n#define RTL839X_L2_PORT_LRN_CONSTRT\t\t(0x3914)\n\n#define RTL838X_L2_PORT_NEW_SALRN(p)\t\t(0x328c + (((p >> 4) << 2)))\n#define RTL839X_L2_PORT_NEW_SALRN(p)\t\t(0x38F0 + (((p >> 4) << 2)))\n#define RTL930X_L2_PORT_SALRN(p)\t\t(0x8FEC + (((p >> 4) << 2)))\n#define RTL931X_L2_PORT_NEW_SALRN(p)\t\t(0xC820 + (((p >> 4) << 2)))\n#define RTL838X_L2_PORT_NEW_SA_FWD(p)\t\t(0x3294 + (((p >> 4) << 2)))\n#define RTL839X_L2_PORT_NEW_SA_FWD(p)\t\t(0x3900 + (((p >> 4) << 2)))\n#define RTL930X_L2_PORT_NEW_SA_FWD(p)\t\t(0x8FF4 + (((p / 10) << 2)))\n#define RTL931X_L2_PORT_NEW_SA_FWD(p)\t\t(0xC830 + (((p / 10) << 2)))\n\n#define RTL930X_ST_CTRL\t\t\t\t(0x8798)\n\n#define RTL930X_L2_PORT_SABLK_CTRL\t\t(0x905c)\n#define RTL930X_L2_PORT_DABLK_CTRL\t\t(0x9060)\n\n#define RTL838X_L2_PORT_LM_ACT(p)\t\t(0x3208 + ((p) << 2))\n#define RTL838X_VLAN_PORT_FWD\t\t\t(0x3A78)\n#define RTL839X_VLAN_PORT_FWD\t\t\t(0x27AC)\n#define RTL930X_VLAN_PORT_FWD\t\t\t(0x834C)\n#define RTL931X_VLAN_PORT_FWD\t\t\t(0x95CC)\n#define RTL838X_VLAN_FID_CTRL\t\t\t(0x3aa8)\n\n/* Port Mirroring */\n#define RTL838X_MIR_CTRL\t\t\t(0x5D00)\n#define RTL838X_MIR_DPM_CTRL\t\t\t(0x5D20)\n#define RTL838X_MIR_SPM_CTRL\t\t\t(0x5D10)\n\n#define RTL839X_MIR_CTRL\t\t\t(0x2500)\n#define RTL839X_MIR_DPM_CTRL\t\t\t(0x2530)\n#define RTL839X_MIR_SPM_CTRL\t\t\t(0x2510)\n\n#define RTL930X_MIR_CTRL\t\t\t(0xA2A0)\n#define RTL930X_MIR_DPM_CTRL\t\t\t(0xA2C0)\n#define RTL930X_MIR_SPM_CTRL\t\t\t(0xA2B0)\n\n#define RTL931X_MIR_CTRL\t\t\t(0xAF00)\n#define RTL931X_MIR_DPM_CTRL\t\t\t(0xAF30)\n#define RTL931X_MIR_SPM_CTRL\t\t\t(0xAF10)\n\n/* Storm/rate control and scheduling */\n#define RTL838X_STORM_CTRL\t\t\t(0x4700)\n#define RTL839X_STORM_CTRL\t\t\t(0x1800)\n#define RTL838X_STORM_CTRL_LB_CTRL(p)\t\t(0x4884 + (((p) << 2)))\n#define RTL838X_STORM_CTRL_BURST_PPS_0\t\t(0x4874)\n#define RTL838X_STORM_CTRL_BURST_PPS_1\t\t(0x4878)\n#define RTL838X_STORM_CTRL_BURST_0\t\t(0x487c)\n#define RTL838X_STORM_CTRL_BURST_1\t\t(0x4880)\n#define RTL839X_STORM_CTRL_LB_TICK_TKN_CTRL_0\t(0x1804)\n#define RTL839X_STORM_CTRL_LB_TICK_TKN_CTRL_1\t(0x1808)\n#define RTL838X_SCHED_CTRL\t\t\t(0xB980)\n#define RTL839X_SCHED_CTRL\t\t\t(0x60F4)\n#define RTL838X_SCHED_LB_TICK_TKN_CTRL_0\t(0xAD58)\n#define RTL838X_SCHED_LB_TICK_TKN_CTRL_1\t(0xAD5C)\n#define RTL839X_SCHED_LB_TICK_TKN_CTRL_0\t(0x1804)\n#define RTL839X_SCHED_LB_TICK_TKN_CTRL_1\t(0x1808)\n#define RTL839X_STORM_CTRL_SPCL_LB_TICK_TKN_CTRL (0x2000)\n#define RTL839X_IGR_BWCTRL_LB_TICK_TKN_CTRL_0\t(0x1604)\n#define RTL839X_IGR_BWCTRL_LB_TICK_TKN_CTRL_1\t(0x1608)\n#define RTL839X_SCHED_LB_TICK_TKN_CTRL\t\t(0x60F8)\n#define RTL839X_SCHED_LB_TICK_TKN_PPS_CTRL\t(0x6200)\n#define RTL838X_SCHED_LB_THR\t\t\t(0xB984)\n#define RTL839X_SCHED_LB_THR\t\t\t(0x60FC)\n#define RTL838X_SCHED_P_EGR_RATE_CTRL(p)\t(0xC008 + (((p) << 7)))\n#define RTL838X_SCHED_Q_EGR_RATE_CTRL(p, q)\t(0xC00C + (p << 7) + (((q) << 2)))\n#define RTL838X_STORM_CTRL_PORT_BC_EXCEED\t(0x470C)\n#define RTL838X_STORM_CTRL_PORT_MC_EXCEED\t(0x4710)\n#define RTL838X_STORM_CTRL_PORT_UC_EXCEED\t(0x4714)\n#define RTL839X_STORM_CTRL_PORT_BC_EXCEED(p)\t(0x180c + (((p >> 5) << 2)))\n#define RTL839X_STORM_CTRL_PORT_MC_EXCEED(p)\t(0x1814 + (((p >> 5) << 2)))\n#define RTL839X_STORM_CTRL_PORT_UC_EXCEED(p)\t(0x181c + (((p >> 5) << 2)))\n#define RTL838X_STORM_CTRL_PORT_UC(p)\t\t(0x4718 + (((p) << 2)))\n#define RTL838X_STORM_CTRL_PORT_MC(p)\t\t(0x478c + (((p) << 2)))\n#define RTL838X_STORM_CTRL_PORT_BC(p)\t\t(0x4800 + (((p) << 2)))\n#define RTL839X_STORM_CTRL_PORT_UC_0(p)\t\t(0x185C + (((p) << 3)))\n#define RTL839X_STORM_CTRL_PORT_UC_1(p)\t\t(0x1860 + (((p) << 3)))\n#define RTL839X_STORM_CTRL_PORT_MC_0(p)\t\t(0x19FC + (((p) << 3)))\n#define RTL839X_STORM_CTRL_PORT_MC_1(p)\t\t(0x1a00 + (((p) << 3)))\n#define RTL839X_STORM_CTRL_PORT_BC_0(p)\t\t(0x1B9C + (((p) << 3)))\n#define RTL839X_STORM_CTRL_PORT_BC_1(p)\t\t(0x1BA0 + (((p) << 3)))\n#define RTL839X_TBL_ACCESS_CTRL_2\t\t(0x611C)\n#define RTL839X_TBL_ACCESS_DATA_2(i)\t\t(0x6120 + (((i) << 2)))\n#define RTL839X_IGR_BWCTRL_PORT_CTRL_10G_0(p)\t(0x1618 + (((p) << 3)))\n#define RTL839X_IGR_BWCTRL_PORT_CTRL_10G_1(p)\t(0x161C + (((p) << 3)))\n#define RTL839X_IGR_BWCTRL_PORT_CTRL_0(p)\t(0x1640 + (((p) << 3)))\n#define RTL839X_IGR_BWCTRL_PORT_CTRL_1(p)\t(0x1644 + (((p) << 3)))\n#define RTL839X_IGR_BWCTRL_CTRL_LB_THR\t\t(0x1614)\n\n/* Link aggregation (Trunking) */\n#define TRUNK_DISTRIBUTION_ALGO_SPA_BIT         0x01\n#define TRUNK_DISTRIBUTION_ALGO_SMAC_BIT        0x02\n#define TRUNK_DISTRIBUTION_ALGO_DMAC_BIT        0x04\n#define TRUNK_DISTRIBUTION_ALGO_SIP_BIT         0x08\n#define TRUNK_DISTRIBUTION_ALGO_DIP_BIT         0x10\n#define TRUNK_DISTRIBUTION_ALGO_SRC_L4PORT_BIT  0x20\n#define TRUNK_DISTRIBUTION_ALGO_DST_L4PORT_BIT  0x40\n#define TRUNK_DISTRIBUTION_ALGO_MASKALL         0x7F\n\n#define TRUNK_DISTRIBUTION_ALGO_L2_SPA_BIT         0x01\n#define TRUNK_DISTRIBUTION_ALGO_L2_SMAC_BIT        0x02\n#define TRUNK_DISTRIBUTION_ALGO_L2_DMAC_BIT        0x04\n#define TRUNK_DISTRIBUTION_ALGO_L2_VLAN_BIT         0x08\n#define TRUNK_DISTRIBUTION_ALGO_L2_MASKALL         0xF\n\n#define TRUNK_DISTRIBUTION_ALGO_L3_SPA_BIT         0x01\n#define TRUNK_DISTRIBUTION_ALGO_L3_SMAC_BIT        0x02\n#define TRUNK_DISTRIBUTION_ALGO_L3_DMAC_BIT        0x04\n#define TRUNK_DISTRIBUTION_ALGO_L3_VLAN_BIT         0x08\n#define TRUNK_DISTRIBUTION_ALGO_L3_SIP_BIT         0x10\n#define TRUNK_DISTRIBUTION_ALGO_L3_DIP_BIT         0x20\n#define TRUNK_DISTRIBUTION_ALGO_L3_SRC_L4PORT_BIT  0x40\n#define TRUNK_DISTRIBUTION_ALGO_L3_DST_L4PORT_BIT  0x80\n#define TRUNK_DISTRIBUTION_ALGO_L3_PROTO_BIT  0x100\n#define TRUNK_DISTRIBUTION_ALGO_L3_FLOW_LABEL_BIT  0x200\n#define TRUNK_DISTRIBUTION_ALGO_L3_MASKALL         0x3FF\n\n#define RTL838X_TRK_MBR_CTR                     (0x3E00)\n#define RTL838X_TRK_HASH_IDX_CTRL               (0x3E20)\n#define RTL838X_TRK_HASH_CTRL                   (0x3E24)\n\n#define RTL839X_TRK_MBR_CTR                     (0x2200)\n#define RTL839X_TRK_HASH_IDX_CTRL               (0x2280)\n#define RTL839X_TRK_HASH_CTRL                   (0x2284)\n\n#define RTL930X_TRK_MBR_CTRL                    (0xA41C)\n#define RTL930X_TRK_HASH_CTRL                   (0x9F80)\n\n#define RTL931X_TRK_MBR_CTRL                    (0xB8D0)\n#define RTL931X_TRK_HASH_CTRL                   (0xBA70)\n\n/* Attack prevention */\n#define RTL838X_ATK_PRVNT_PORT_EN\t\t(0x5B00)\n#define RTL838X_ATK_PRVNT_CTRL\t\t\t(0x5B04)\n#define RTL838X_ATK_PRVNT_ACT\t\t\t(0x5B08)\n#define RTL838X_ATK_PRVNT_STS\t\t\t(0x5B1C)\n\n/* 802.1X */\n#define RTL838X_RMA_BPDU_FLD_PMSK\t\t(0x4348)\n#define RTL930X_RMA_BPDU_FLD_PMSK\t\t(0x9F18)\n#define RTL931X_RMA_BPDU_FLD_PMSK\t\t(0x8950)\n#define RTL839X_RMA_BPDU_FLD_PMSK\t\t(0x125C)\n\n#define RTL838X_SPCL_TRAP_CTRL\t\t\t(0x6980)\n#define RTL838X_SPCL_TRAP_EAPOL_CTRL\t\t(0x6988)\n#define RTL838X_SPCL_TRAP_ARP_CTRL\t\t(0x698C)\n#define RTL838X_SPCL_TRAP_IGMP_CTRL\t\t(0x6984)\n#define RTL838X_SPCL_TRAP_IPV6_CTRL\t\t(0x6994)\n#define RTL838X_SPCL_TRAP_SWITCH_MAC_CTRL\t(0x6998)\n\n#define RTL839X_SPCL_TRAP_CTRL\t\t\t(0x1054)\n#define RTL839X_SPCL_TRAP_EAPOL_CTRL\t\t(0x105C)\n#define RTL839X_SPCL_TRAP_ARP_CTRL\t\t(0x1060)\n#define RTL839X_SPCL_TRAP_IGMP_CTRL\t\t(0x1058)\n#define RTL839X_SPCL_TRAP_IPV6_CTRL\t\t(0x1064)\n#define RTL839X_SPCL_TRAP_SWITCH_MAC_CTRL\t(0x1068)\n#define RTL839X_SPCL_TRAP_SWITCH_IPV4_ADDR_CTRL\t(0x106C)\n#define RTL839X_SPCL_TRAP_CRC_CTRL\t\t(0x1070)\n/* special port action controls */\n/* \n    values:\n\t0 = FORWARD (default)\n\t1 = DROP\n\t2 = TRAP2CPU\n\t3 = FLOOD IN ALL PORT\n\n\tRegister encoding.\n\toffset = CTRL + (port >> 4) << 2\n\tvalue/mask = 3 << ((port&0xF) << 1)\n*/\n\ntypedef enum {\n\tBPDU = 0,\n\tPTP,\n\tPTP_UDP,\n\tPTP_ETH2,\n\tLLTP,\n\tEAPOL,\n\tGRATARP,\n} rma_ctrl_t;\n\ntypedef enum {\n\tFORWARD = 0,\n\tDROP,\n\tTRAP2CPU,\n\tFLOODALL,\n\tTRAP2MASTERCPU,\n\tCOPY2CPU,\n} action_type_t;\n\n#define RTL838X_RMA_BPDU_CTRL\t\t\t(0x4330) \n#define RTL839X_RMA_BPDU_CTRL\t\t\t(0x122C)\n#define RTL930X_RMA_BPDU_CTRL\t\t\t(0x9E7C)\n#define RTL931X_RMA_BPDU_CTRL\t\t\t(0x881C)\n\n#define RTL838X_RMA_PTP_CTRL\t\t\t(0x4338) \n#define RTL839X_RMA_PTP_CTRL\t\t\t(0x123C)\n#define RTL930X_RMA_PTP_CTRL\t\t\t(0x9E88)\n#define RTL931X_RMA_PTP_CTRL\t\t\t(0x8834)\n\n#define RTL838X_RMA_LLTP_CTRL\t\t\t(0x4340) \n#define RTL839X_RMA_LLTP_CTRL\t\t\t(0x124C)\n#define RTL930X_RMA_LLTP_CTRL\t\t\t(0x9EFC)\n#define RTL931X_RMA_LLTP_CTRL\t\t\t(0x8918)\n\n#define RTL930X_RMA_EAPOL_CTRL\t\t\t(0x9F08)\n#define RTL931X_RMA_EAPOL_CTRL\t\t\t(0x8930)\n#define RTL931X_TRAP_ARP_GRAT_PORT_ACT\t\t(0x8C04)\n\n/* QoS */\n#define RTL838X_QM_INTPRI2QID_CTRL\t\t(0x5F00)\n#define RTL839X_QM_INTPRI2QID_CTRL(q)\t\t(0x1110 + (q << 2))\n#define RTL839X_QM_PORT_QNUM(p)\t\t\t(0x1130 + (((p / 10) << 2)))\n#define RTL838X_PRI_SEL_PORT_PRI(p)\t\t(0x5FB8 + (((p / 10) << 2)))\n#define RTL839X_PRI_SEL_PORT_PRI(p)\t\t(0x10A8 + (((p / 10) << 2)))\n#define RTL838X_QM_PKT2CPU_INTPRI_MAP\t\t(0x5F10)\n#define RTL839X_QM_PKT2CPU_INTPRI_MAP\t\t(0x1154)\n#define RTL838X_PRI_SEL_CTRL\t\t\t(0x10E0)\n#define RTL839X_PRI_SEL_CTRL\t\t\t(0x10E0)\n#define RTL838X_PRI_SEL_TBL_CTRL(i)\t\t(0x5FD8 + (((i) << 2)))\n#define RTL839X_PRI_SEL_TBL_CTRL(i)\t\t(0x10D0 + (((i) << 2)))\n#define RTL838X_QM_PKT2CPU_INTPRI_0\t\t(0x5F04)\n#define RTL838X_QM_PKT2CPU_INTPRI_1\t\t(0x5F08)\n#define RTL838X_QM_PKT2CPU_INTPRI_2\t\t(0x5F0C)\n#define RTL839X_OAM_CTRL\t\t\t(0x2100)\n#define RTL839X_OAM_PORT_ACT_CTRL(p)\t \t(0x2104 + (((p) << 2)))\n#define RTL839X_RMK_PORT_DEI_TAG_CTRL(p)\t(0x6A9C + (((p >> 5) << 2)))\n#define RTL839X_PRI_SEL_IPRI_REMAP\t\t(0x1080)\n#define RTL838X_PRI_SEL_IPRI_REMAP\t\t(0x5F8C)\n#define RTL839X_PRI_SEL_DEI2DP_REMAP\t\t(0x10EC)\n#define RTL839X_PRI_SEL_DSCP2DP_REMAP_ADDR(i)\t(0x10F0 + (((i >> 4) << 2)))\n#define RTL839X_RMK_DEI_CTRL\t\t\t(0x6AA4)\n#define RTL839X_WRED_PORT_THR_CTRL(i)\t\t(0x6084 + ((i) << 2))\n#define RTL839X_WRED_QUEUE_THR_CTRL(q, i) \t(0x6090 + ((q) * 12) + ((i) << 2))\n#define RTL838X_PRI_DSCP_INVLD_CTRL0\t\t(0x5FE8)\n#define RTL838X_RMK_IPRI_CTRL\t\t\t(0xA460)\n#define RTL838X_RMK_OPRI_CTRL\t\t\t(0xA464)\n#define RTL838X_SCHED_P_TYPE_CTRL(p)\t\t(0xC04C + (((p) << 7)))\n#define RTL838X_SCHED_LB_CTRL(p)\t\t(0xC004 + (((p) << 7)))\n#define RTL838X_FC_P_EGR_DROP_CTRL(p)\t\t(0x6B1C + (((p) << 2)))\n\n/* Debug features */\n#define RTL930X_STAT_PRVTE_DROP_COUNTER0\t(0xB5B8)\n\n/* Packet Inspection Engine */\n#define RTL838X_METER_GLB_CTRL\t\t\t(0x4B08)\n#define RTL839X_METER_GLB_CTRL\t\t\t(0x1300)\n#define RTL930X_METER_GLB_CTRL\t\t\t(0xa0a0)\n#define RTL931X_METER_GLB_CTRL\t\t\t(0x411C)\n\n#define RTL839X_ACL_CTRL\t\t\t(0x1288)\n\n#define RTL838X_ACL_BLK_LOOKUP_CTRL\t\t(0x6100)\n#define RTL839X_ACL_BLK_LOOKUP_CTRL\t\t(0x1280)\n#define RTL930X_PIE_BLK_LOOKUP_CTRL\t\t(0xa5a0)\n#define RTL931X_PIE_BLK_LOOKUP_CTRL\t\t(0x4180)\n\n#define RTL838X_ACL_BLK_PWR_CTRL\t\t(0x6104)\n#define RTL839X_PS_ACL_PWR_CTRL\t\t\t(0x049c)\n\n#define RTL838X_ACL_BLK_TMPLTE_CTRL(block)\t(0x6108 + ((block) << 2))\n#define RTL839X_ACL_BLK_TMPLTE_CTRL(block)\t(0x128c + ((block) << 2))\n#define RTL930X_PIE_BLK_TMPLTE_CTRL(block)\t(0xa624 + ((block) << 2))\n#define RTL931X_PIE_BLK_TMPLTE_CTRL(block)\t(0x4214 + ((block) << 2))\n\n#define RTL838X_ACL_BLK_GROUP_CTRL\t\t(0x615C)\n#define RTL839X_ACL_BLK_GROUP_CTRL\t\t(0x12ec)\n\n#define RTL838X_ACL_CLR_CTRL\t\t\t(0x6168)\n#define RTL839X_ACL_CLR_CTRL\t\t\t(0x12fc)\n#define RTL930X_PIE_CLR_CTRL\t\t\t(0xa66c)\n#define RTL931X_PIE_CLR_CTRL\t\t\t(0x42D8)\n\n#define RTL838X_DMY_REG27\t\t\t(0x3378)\n\n#define RTL838X_ACL_PORT_LOOKUP_CTRL(p)\t\t(0x616C + (((p) << 2)))\n#define RTL930X_ACL_PORT_LOOKUP_CTRL(p)\t\t(0xA784 + (((p) << 2)))\n#define RTL931X_ACL_PORT_LOOKUP_CTRL(p)\t\t(0x44F8 + (((p) << 2)))\n\n#define RTL930X_PIE_BLK_PHASE_CTRL\t\t(0xA5A4)\n#define RTL931X_PIE_BLK_PHASE_CTRL\t\t(0x4184)\n\n// PIE actions\n#define PIE_ACT_COPY_TO_PORT\t2\n#define PIE_ACT_REDIRECT_TO_PORT 4\n#define PIE_ACT_ROUTE_UC\t6\n#define PIE_ACT_VID_ASSIGN\t0\n\n// L3 actions\n#define L3_FORWARD\t\t0\n#define L3_DROP\t\t\t1\n#define L3_TRAP2CPU\t\t2\n#define L3_COPY2CPU\t\t3\n#define L3_TRAP2MASTERCPU\t4\n#define L3_COPY2MASTERCPU\t5\n#define L3_HARDDROP\t\t6\n\n// Route actions\n#define ROUTE_ACT_FORWARD\t0\n#define ROUTE_ACT_TRAP2CPU\t1\n#define ROUTE_ACT_COPY2CPU\t2\n#define ROUTE_ACT_DROP\t\t3\n\n/* L3 Routing */\n#define RTL839X_ROUTING_SA_CTRL \t\t0x6afc\n#define RTL930X_L3_HOST_TBL_CTRL\t\t(0xAB48)\n#define RTL930X_L3_IPUC_ROUTE_CTRL\t\t(0xAB4C)\n#define RTL930X_L3_IP6UC_ROUTE_CTRL\t\t(0xAB50)\n#define RTL930X_L3_IPMC_ROUTE_CTRL\t\t(0xAB54)\n#define RTL930X_L3_IP6MC_ROUTE_CTRL\t\t(0xAB58)\n#define RTL930X_L3_IP_MTU_CTRL(i)\t\t(0xAB5C + ((i >> 1) << 2))\n#define RTL930X_L3_IP6_MTU_CTRL(i)\t\t(0xAB6C + ((i >> 1) << 2))\n#define RTL930X_L3_HW_LU_KEY_CTRL\t\t(0xAC9C)\n#define RTL930X_L3_HW_LU_KEY_IP_CTRL\t\t(0xACA0)\n#define RTL930X_L3_HW_LU_CTRL\t\t\t(0xACC0)\n#define RTL930X_L3_IP_ROUTE_CTRL\t\t0xab44\n\n/* Port LED Control */\n#define RTL930X_LED_PORT_NUM_CTRL(p)\t\t(0xCC04 + (((p >> 4) << 2)))\n#define RTL930X_LED_SET0_0_CTRL\t\t\t(0xCC28)\n#define RTL930X_LED_PORT_COPR_SET_SEL_CTRL(p)\t(0xCC2C + (((p >> 4) << 2)))\n#define RTL930X_LED_PORT_FIB_SET_SEL_CTRL(p)\t(0xCC34 + (((p >> 4) << 2)))\n#define RTL930X_LED_PORT_COPR_MASK_CTRL\t\t(0xCC3C)\n#define RTL930X_LED_PORT_FIB_MASK_CTRL\t\t(0xCC40)\n#define RTL930X_LED_PORT_COMBO_MASK_CTRL\t(0xCC44)\n\n#define RTL931X_LED_PORT_NUM_CTRL(p)\t\t(0x0604 + (((p >> 4) << 2)))\n#define RTL931X_LED_SET0_0_CTRL\t\t\t(0x0630)\n#define RTL931X_LED_PORT_COPR_SET_SEL_CTRL(p)\t(0x0634 + (((p >> 4) << 2)))\n#define RTL931X_LED_PORT_FIB_SET_SEL_CTRL(p)\t(0x0644 + (((p >> 4) << 2)))\n#define RTL931X_LED_PORT_COPR_MASK_CTRL\t\t(0x0654)\n#define RTL931X_LED_PORT_FIB_MASK_CTRL\t\t(0x065c)\n#define RTL931X_LED_PORT_COMBO_MASK_CTRL\t(0x0664)\n\n#define MAX_VLANS 4096\n#define MAX_LAGS 16\n#define MAX_PRIOS 8\n#define RTL930X_PORT_IGNORE 0x3f\n#define MAX_MC_GROUPS 512\n#define UNKNOWN_MC_PMASK (MAX_MC_GROUPS - 1)\n#define PIE_BLOCK_SIZE 128\n#define MAX_PIE_ENTRIES (18 * PIE_BLOCK_SIZE)\n#define N_FIXED_FIELDS 12\n#define N_FIXED_FIELDS_RTL931X 14\n#define MAX_COUNTERS 2048\n#define MAX_ROUTES 512\n#define MAX_HOST_ROUTES 1536\n#define MAX_INTF_MTUS 8\n#define DEFAULT_MTU 1536\n#define MAX_INTERFACES 100\n#define MAX_ROUTER_MACS 64\n#define L3_EGRESS_DMACS 2048\n#define MAX_SMACS 64\n\nenum phy_type {\n\tPHY_NONE = 0,\n\tPHY_RTL838X_SDS = 1,\n\tPHY_RTL8218B_INT = 2,\n\tPHY_RTL8218B_EXT = 3,\n\tPHY_RTL8214FC = 4,\n\tPHY_RTL839X_SDS = 5,\n\tPHY_RTL930X_SDS = 6,\n};\n\nenum pbvlan_type {\n\tPBVLAN_TYPE_INNER = 0,\n\tPBVLAN_TYPE_OUTER,\n};\n\nenum pbvlan_mode {\n\tPBVLAN_MODE_UNTAG_AND_PRITAG = 0,\n\tPBVLAN_MODE_UNTAG_ONLY,\n\tPBVLAN_MODE_ALL_PKT,\n};\n\nstruct rtl838x_port {\n\tbool enable;\n\tu64 pm;\n\tu16 pvid;\n\tbool eee_enabled;\n\tenum phy_type phy;\n\tbool phy_is_integrated;\n\tbool is10G;\n\tbool is2G5;\n\tint sds_num;\n\tint led_set;\n\tconst struct dsa_port *dp;\n};\n\nstruct rtl838x_vlan_info {\n\tu64 untagged_ports;\n\tu64 tagged_ports;\n\tu8 profile_id;\n\tbool hash_mc_fid;\n\tbool hash_uc_fid;\n\tu8 fid; // AKA MSTI\n\n\t// The following fields are used only by the RTL931X\n\tint if_id;\t\t// Interface (index in L3_EGR_INTF_IDX)\n\tu16 multicast_grp_mask;\n\tint l2_tunnel_list_id;\n};\n\nenum l2_entry_type {\n\tL2_INVALID = 0,\n\tL2_UNICAST = 1,\n\tL2_MULTICAST = 2,\n\tIP4_MULTICAST = 3,\n\tIP6_MULTICAST = 4,\n};\n\nstruct rtl838x_l2_entry {\n\tu8 mac[6];\n\tu16 vid;\n\tu16 rvid;\n\tu8 port;\n\tbool valid;\n\tenum l2_entry_type type;\n\tbool is_static;\n\tbool is_ip_mc;\n\tbool is_ipv6_mc;\n\tbool block_da;\n\tbool block_sa;\n\tbool suspended;\n\tbool next_hop;\n\tint age;\n\tu8 trunk;\n\tbool is_trunk;\n\tu8 stack_dev;\n\tu16 mc_portmask_index;\n\tu32 mc_gip;\n\tu32 mc_sip;\n\tu16 mc_mac_index;\n\tu16 nh_route_id;\n\tbool nh_vlan_target;  // Only RTL83xx: VLAN used for next hop\n\n\t// The following is only valid on RTL931x\n\tbool is_open_flow;\n\tbool is_pe_forward;\n\tbool is_local_forward;\n\tbool is_remote_forward;\n\tbool is_l2_tunnel;\n\tint l2_tunnel_id;\n\tint l2_tunnel_list_id;\n};\n\nenum fwd_rule_action {\n\tFWD_RULE_ACTION_NONE = 0,\n\tFWD_RULE_ACTION_FWD = 1,\n};\n\nenum pie_phase {\n\tPHASE_VACL = 0,\n\tPHASE_IACL = 1,\n};\n\nenum igr_filter {\n\tIGR_FORWARD = 0,\n\tIGR_DROP = 1,\n\tIGR_TRAP = 2,\n};\n\nenum egr_filter {\n\tEGR_DISABLE = 0,\n\tEGR_ENABLE = 1,\n};\n\n/* Intermediate representation of a  Packet Inspection Engine Rule\n * as suggested by the Kernel's tc flower offload subsystem\n * Field meaning is universal across SoC families, but data content is specific\n * to SoC family (e.g. because of different port ranges) */\nstruct pie_rule {\n\tint id;\n\tenum pie_phase phase;\t// Phase in which this template is applied\n\tint packet_cntr;\t// ID of a packet counter assigned to this rule\n\tint octet_cntr;\t\t// ID of a byte counter assigned to this rule\n\tu32 last_packet_cnt;\n\tu64 last_octet_cnt;\n\n\t// The following are requirements for the pie template\n\tbool is_egress;\n\tbool is_ipv6;\t\t// This is a rule with IPv6 fields\n\n\t// Fixed fields that are always matched against on RTL8380\n\tu8 spmmask_fix;\n\tu8 spn;\t\t\t// Source port number\n\tbool stacking_port;\t// Source port is stacking port\n\tbool mgnt_vlan;\t\t// Packet arrived on management VLAN\n\tbool dmac_hit_sw;\t// The packet's destination MAC matches one of the device's\n\tbool content_too_deep;\t// The content of the packet cannot be parsed: too many layers\n\tbool not_first_frag;\t// Not the first IP fragment\n\tu8 frame_type_l4;\t// 0: UDP, 1: TCP, 2: ICMP/ICMPv6, 3: IGMP\n\tu8 frame_type;\t\t// 0: ARP, 1: L2 only, 2: IPv4, 3: IPv6\n\tbool otag_fmt;\t\t// 0: outer tag packet, 1: outer priority tag or untagged\n\tbool itag_fmt;\t\t// 0: inner tag packet, 1: inner priority tag or untagged\n\tbool otag_exist;\t// packet with outer tag\n\tbool itag_exist;\t// packet with inner tag\n\tbool frame_type_l2;\t// 0: Ethernet, 1: LLC_SNAP, 2: LLC_Other, 3: Reserved\n\tbool igr_normal_port;\t// Ingress port is not cpu or stacking port\n\tu8 tid;\t\t\t// The template ID defining the what the templated fields mean\n\n\t// Masks for the fields that are always matched against on RTL8380\n\tu8 spmmask_fix_m;\n\tu8 spn_m;\n\tbool stacking_port_m;\n\tbool mgnt_vlan_m;\n\tbool dmac_hit_sw_m;\n\tbool content_too_deep_m;\n\tbool not_first_frag_m;\n\tu8 frame_type_l4_m;\n\tu8 frame_type_m;\n\tbool otag_fmt_m;\n\tbool itag_fmt_m;\n\tbool otag_exist_m;\n\tbool itag_exist_m;\n\tbool frame_type_l2_m;\n\tbool igr_normal_port_m;\n\tu8 tid_m;\n\n\t// Logical operations between rules, special rules for rule numbers apply\n\tbool valid;\n\tbool cond_not;\t\t// Matches when conditions not match\n\tbool cond_and1;\t\t// And this rule 2n with the next rule 2n+1 in same block\n\tbool cond_and2;\t\t// And this rule m in block 2n with rule m in block 2n+1\n\tbool ivalid;\n\n\t// Actions to be performed\n\tbool drop;\t\t// Drop the packet\n\tbool fwd_sel;\t\t// Forward packet: to port, portmask, dest route, next rule, drop\n\tbool ovid_sel;\t\t// So something to outer vlan-id: shift, re-assign\n\tbool ivid_sel;\t\t// Do something to inner vlan-id: shift, re-assign\n\tbool flt_sel;\t\t// Filter the packet when sending to certain ports\n\tbool log_sel;\t\t// Log the packet in one of the LOG-table counters\n\tbool rmk_sel;\t\t// Re-mark the packet, i.e. change the priority-tag\n\tbool meter_sel;\t\t// Meter the packet, i.e. limit rate of this type of packet\n\tbool tagst_sel;\t\t// Change the ergress tag\n\tbool mir_sel;\t\t// Mirror the packet to a Link Aggregation Group\n\tbool nopri_sel;\t\t// Change the normal priority\n\tbool cpupri_sel;\t// Change the CPU priority\n\tbool otpid_sel;\t\t// Change Outer Tag Protocol Identifier (802.1q)\n\tbool itpid_sel;\t\t// Change Inner Tag Protocol Identifier (802.1q)\n\tbool shaper_sel;\t// Apply traffic shaper\n\tbool mpls_sel;\t\t// MPLS actions\n\tbool bypass_sel;\t// Bypass actions\n\tbool fwd_sa_lrn;\t// Learn the source address when forwarding\n\tbool fwd_mod_to_cpu;\t// Forward the modified VLAN tag format to CPU-port\n\n\t// Fields used in predefined templates 0-2 on RTL8380 / 90 / 9300\n\tu64 spm;\t\t// Source Port Matrix\n\tu16 otag;\t\t// Outer VLAN-ID\n\tu8 smac[ETH_ALEN];\t// Source MAC address\n\tu8 dmac[ETH_ALEN];\t// Destination MAC address\n\tu16 ethertype;\t\t// Ethernet frame type field in ethernet header\n\tu16 itag;\t\t// Inner VLAN-ID\n\tu16 field_range_check;\n\tu32 sip;\t\t// Source IP\n\tstruct in6_addr sip6;\t// IPv6 Source IP\n\tu32 dip;\t\t// Destination IP\n\tstruct in6_addr dip6;\t// IPv6 Destination IP\n\tu16 tos_proto;\t\t// IPv4: TOS + Protocol fields, IPv6: Traffic class + next header\n\tu16 sport;\t\t// TCP/UDP source port\n\tu16 dport;\t\t// TCP/UDP destination port\n\tu16 icmp_igmp;\n\tu16 tcp_info;\n\tu16 dsap_ssap;\t\t// Destination / Source Service Access Point bytes (802.3)\n\n\tu64 spm_m;\n\tu16 otag_m;\n\tu8 smac_m[ETH_ALEN];\n\tu8 dmac_m[ETH_ALEN];\n\tu8 ethertype_m;\n\tu16 itag_m;\n\tu16 field_range_check_m;\n\tu32 sip_m;\n\tstruct in6_addr sip6_m;\t// IPv6 Source IP mask\n\tu32 dip_m;\n\tstruct in6_addr dip6_m;\t// IPv6 Destination IP mask\n\tu16 tos_proto_m;\n\tu16 sport_m;\n\tu16 dport_m;\n\tu16 icmp_igmp_m;\n\tu16 tcp_info_m;\n\tu16 dsap_ssap_m;\n\n\t// Data associated with actions\n\tu8 fwd_act;\t\t// Type of forwarding action\n\t\t\t\t// 0: permit, 1: drop, 2: copy to port id, 4: copy to portmask\n\t\t\t\t// 4: redirect to portid, 5: redirect to portmask\n\t\t\t\t// 6: route, 7: vlan leaky (only 8380)\n\tu16 fwd_data;\t\t// Additional data for forwarding action, e.g. destination port\n\tu8 ovid_act;\n\tu16 ovid_data;\t\t// Outer VLAN ID\n\tu8 ivid_act;\n\tu16 ivid_data;\t\t// Inner VLAN ID\n\tu16 flt_data;\t\t// Filtering data\n\tu16 log_data;\t\t// ID of packet or octet counter in LOG table, on RTL93xx\n\t\t\t\t// unnecessary since PIE-Rule-ID == LOG-counter-ID\n\tbool log_octets;\n\tu8 mpls_act;\t\t// MPLS action type\n\tu16 mpls_lib_idx;\t// MPLS action data\n\n\tu16 rmk_data;\t\t// Data for remarking\n\tu16 meter_data;\t\t// ID of meter for bandwidth control\n\tu16 tagst_data;\n\tu16 mir_data;\n\tu16 nopri_data;\n\tu16 cpupri_data;\n\tu16 otpid_data;\n\tu16 itpid_data;\n\tu16 shaper_data;\n\n\t// Bypass actions, ignored on RTL8380\n\tbool bypass_all;\t// Not clear\n\tbool bypass_igr_stp;\t// Bypass Ingress STP state\n\tbool bypass_ibc_sc;\t// Bypass Ingress Bandwidth Control and Storm Control\n};\n\nstruct rtl838x_l3_intf {\n\tu16 vid;\n\tu8 smac_idx;\n\tu8 ip4_mtu_id;\n\tu8 ip6_mtu_id;\n\tu16 ip4_mtu;\n\tu16 ip6_mtu;\n\tu8 ttl_scope;\n\tu8 hl_scope;\n\tu8 ip4_icmp_redirect;\n\tu8 ip6_icmp_redirect;\n\tu8 ip4_pbr_icmp_redirect;\n\tu8 ip6_pbr_icmp_redirect;\n};\n\n/*\n * An entry in the RTL93XX SoC's ROUTER_MAC tables setting up a termination point\n * for the L3 routing system. Packets arriving and matching an entry in this table\n * will be considered for routing.\n * Mask fields state whether the corresponding data fields matter for matching\n */\nstruct rtl93xx_rt_mac {\n\tbool valid;\t// Valid or not\n\tbool p_type;\t// Individual (0) or trunk (1) port\n\tbool p_mask;\t// Whether the port type is used\n\tu8 p_id;\n\tu8 p_id_mask;\t// Mask for the port\n\tu8 action;\t// Routing action performed: 0: FORWARD, 1: DROP, 2: TRAP2CPU\n\t\t\t//   3: COPY2CPU, 4: TRAP2MASTERCPU, 5: COPY2MASTERCPU, 6: HARDDROP\n\tu16 vid;\n\tu16 vid_mask;\n\tu64 mac;\t// MAC address used as source MAC in the routed packet\n\tu64 mac_mask;\n};\n\nstruct rtl83xx_nexthop {\n\tu16 id;\t\t// ID: L3_NEXT_HOP table-index or route-index set in L2_NEXT_HOP\n\tu32 dev_id;\n\tu16 port;\n\tu16 vid;\t// VLAN-ID for L2 table entry (saved from L2-UC entry)\n\tu16 rvid;\t// Relay VID/FID for the L2 table entry\n\tu64 mac;\t// The MAC address of the entry in the L2_NEXT_HOP table\n\tu16 mac_id;\n\tu16 l2_id;\t// Index of this next hop forwarding entry in L2 FIB table\n\tu64 gw;\t\t// The gateway MAC address packets are forwarded to\n\tint if_id;\t// Interface (into L3_EGR_INTF_IDX)\n};\n\nstruct rtl838x_switch_priv;\n\nstruct rtl83xx_flow {\n\tunsigned long cookie;\n\tstruct rhash_head node;\n\tstruct rcu_head rcu_head;\n\tstruct rtl838x_switch_priv *priv;\n\tstruct pie_rule rule;\n\tu32 flags;\n};\n\nstruct rtl93xx_route_attr {\n\tbool valid;\n\tbool hit;\n\tbool ttl_dec;\n\tbool ttl_check;\n\tbool dst_null;\n\tbool qos_as;\n\tu8 qos_prio;\n\tu8 type;\n\tu8 action;\n};\n\nstruct rtl83xx_route {\n\tu32 gw_ip;\t\t\t// IP of the route's gateway\n\tu32 dst_ip;\t\t\t// IP of the destination net\n\tstruct in6_addr dst_ip6;\n\tint prefix_len;\t\t\t// Network prefix len of the destination net\n\tbool is_host_route;\n\tint id;\t\t\t\t// ID number of this route\n\tstruct rhlist_head linkage;\n\tu16 switch_mac_id;\t\t// Index into switch's own MACs, RTL839X only\n\tstruct rtl83xx_nexthop nh;\n\tstruct pie_rule pr;\n\tstruct rtl93xx_route_attr attr;\n};\n\nstruct rtl838x_reg {\n\tvoid (*mask_port_reg_be)(u64 clear, u64 set, int reg);\n\tvoid (*set_port_reg_be)(u64 set, int reg);\n\tu64 (*get_port_reg_be)(int reg);\n\tvoid (*mask_port_reg_le)(u64 clear, u64 set, int reg);\n\tvoid (*set_port_reg_le)(u64 set, int reg);\n\tu64 (*get_port_reg_le)(int reg);\n\tint stat_port_rst;\n\tint stat_rst;\n\tint stat_port_std_mib;\n\tint (*port_iso_ctrl)(int p);\n\tvoid (*traffic_enable)(int source, int dest);\n\tvoid (*traffic_disable)(int source, int dest);\n\tvoid (*traffic_set)(int source, u64 dest_matrix);\n\tu64 (*traffic_get)(int source);\n\tint l2_ctrl_0;\n\tint l2_ctrl_1;\n\tint smi_poll_ctrl;\n\tu32 l2_port_aging_out;\n\tint l2_tbl_flush_ctrl;\n\tvoid (*exec_tbl0_cmd)(u32 cmd);\n\tvoid (*exec_tbl1_cmd)(u32 cmd);\n\tint (*tbl_access_data_0)(int i);\n\tint isr_glb_src;\n\tint isr_port_link_sts_chg;\n\tint imr_port_link_sts_chg;\n\tint imr_glb;\n\tvoid (*vlan_tables_read)(u32 vlan, struct rtl838x_vlan_info *info);\n\tvoid (*vlan_set_tagged)(u32 vlan, struct rtl838x_vlan_info *info);\n\tvoid (*vlan_set_untagged)(u32 vlan, u64 portmask);\n\tvoid (*vlan_profile_dump)(int index);\n\tvoid (*vlan_profile_setup)(int profile);\n\tvoid (*vlan_port_pvidmode_set)(int port, enum pbvlan_type type, enum pbvlan_mode mode);\n\tvoid (*vlan_port_pvid_set)(int port, enum pbvlan_type type, int pvid);\n\tvoid (*set_vlan_igr_filter)(int port, enum igr_filter state);\n\tvoid (*set_vlan_egr_filter)(int port, enum egr_filter state);\n\tvoid (*enable_learning)(int port, bool enable);\n\tvoid (*enable_flood)(int port, bool enable);\n\tvoid (*enable_mcast_flood)(int port, bool enable);\n\tvoid (*enable_bcast_flood)(int port, bool enable);\n\tvoid (*stp_get)(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[]);\n\tvoid (*stp_set)(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[]);\n\tint  (*mac_force_mode_ctrl)(int port);\n\tint  (*mac_port_ctrl)(int port);\n\tint  (*l2_port_new_salrn)(int port);\n\tint  (*l2_port_new_sa_fwd)(int port);\n\tint (*set_ageing_time)(unsigned long msec);\n\tint mir_ctrl;\n\tint mir_dpm;\n\tint mir_spm;\n\tint mac_link_sts;\n\tint mac_link_dup_sts;\n\tint  (*mac_link_spd_sts)(int port);\n\tint mac_rx_pause_sts;\n\tint mac_tx_pause_sts;\n\tu64 (*read_l2_entry_using_hash)(u32 hash, u32 position, struct rtl838x_l2_entry *e);\n\tvoid (*write_l2_entry_using_hash)(u32 hash, u32 pos, struct rtl838x_l2_entry *e);\n\tu64 (*read_cam)(int idx, struct rtl838x_l2_entry *e);\n\tvoid (*write_cam)(int idx, struct rtl838x_l2_entry *e);\n\tint vlan_port_tag_sts_ctrl;\n\tint (*rtl838x_vlan_port_tag_sts_ctrl)(int port);\n\tint (*trk_mbr_ctr)(int group);\n\tint rma_bpdu_fld_pmask;\n\tint spcl_trap_eapol_ctrl;\n\tvoid (*init_eee)(struct rtl838x_switch_priv *priv, bool enable);\n\tvoid (*port_eee_set)(struct rtl838x_switch_priv *priv, int port, bool enable);\n\tint (*eee_port_ability)(struct rtl838x_switch_priv *priv,\n\t\t\t\tstruct ethtool_eee *e, int port);\n\tu64 (*l2_hash_seed)(u64 mac, u32 vid);\n\tu32 (*l2_hash_key)(struct rtl838x_switch_priv *priv, u64 seed);\n\tu64 (*read_mcast_pmask)(int idx);\n\tvoid (*write_mcast_pmask)(int idx, u64 portmask);\n\tvoid (*vlan_fwd_on_inner)(int port, bool is_set);\n\tvoid (*pie_init)(struct rtl838x_switch_priv *priv);\n\tint (*pie_rule_read)(struct rtl838x_switch_priv *priv, int idx, struct  pie_rule *pr);\n\tint (*pie_rule_write)(struct rtl838x_switch_priv *priv, int idx, struct pie_rule *pr);\n\tint (*pie_rule_add)(struct rtl838x_switch_priv *priv, struct pie_rule *rule);\n\tvoid (*pie_rule_rm)(struct rtl838x_switch_priv *priv, struct pie_rule *rule);\n\tvoid (*l2_learning_setup)(void);\n\tu32 (*packet_cntr_read)(int counter);\n\tvoid (*packet_cntr_clear)(int counter);\n\tvoid (*route_read)(int idx, struct rtl83xx_route *rt);\n\tvoid (*route_write)(int idx, struct rtl83xx_route *rt);\n\tvoid (*host_route_write)(int idx, struct rtl83xx_route *rt);\n\tint (*l3_setup)(struct rtl838x_switch_priv *priv);\n\tvoid (*set_l3_nexthop)(int idx, u16 dmac_id, u16 interface);\n\tvoid (*get_l3_nexthop)(int idx, u16 *dmac_id, u16 *interface);\n\tu64 (*get_l3_egress_mac)(u32 idx);\n\tvoid (*set_l3_egress_mac)(u32 idx, u64 mac);\n\tint (*find_l3_slot)(struct rtl83xx_route *rt, bool must_exist);\n\tint (*route_lookup_hw)(struct rtl83xx_route *rt);\n\tvoid (*get_l3_router_mac)(u32 idx, struct rtl93xx_rt_mac *m);\n\tvoid (*set_l3_router_mac)(u32 idx, struct rtl93xx_rt_mac *m);\n\tvoid (*set_l3_egress_intf)(int idx, struct rtl838x_l3_intf *intf);\n\tvoid (*set_distribution_algorithm)(int group, int algoidx, u32 algomask);\n\tvoid (*set_receive_management_action)(int port, rma_ctrl_t type, action_type_t action);\n\tvoid (*led_init)(struct rtl838x_switch_priv *priv);\n};\n\nstruct rtl838x_switch_priv {\n\t/* Switch operation */\n\tstruct dsa_switch *ds;\n\tstruct device *dev;\n\tu16 id;\n\tu16 family_id;\n\tchar version;\n\tstruct rtl838x_port ports[57];\n\tstruct mutex reg_mutex;\t\t// Mutex for individual register manipulations\n\tstruct mutex pie_mutex;\t\t// Mutex for Packet Inspection Engine\n\tint link_state_irq;\n\tint mirror_group_ports[4];\n\tstruct mii_bus *mii_bus;\n\tconst struct rtl838x_reg *r;\n\tu8 cpu_port;\n\tu8 port_mask;\n\tu8 port_width;\n\tu8 port_ignore;\n\tu64 irq_mask;\n\tu32 fib_entries;\n\tint l2_bucket_size;\n\tstruct dentry *dbgfs_dir;\n\tint n_lags;\n\tu64 lags_port_members[MAX_LAGS];\n\tstruct net_device *lag_devs[MAX_LAGS];\n\tu32 lag_primary[MAX_LAGS];\n\tu32 is_lagmember[57];\n\tu64 lagmembers;\n\tstruct notifier_block nb;  // TODO: change to different name\n\tstruct notifier_block ne_nb;\n\tstruct notifier_block fib_nb;\n\tbool eee_enabled;\n\tunsigned long int mc_group_bm[MAX_MC_GROUPS >> 5];\n\tint mc_group_saves[MAX_MC_GROUPS];\n\tint n_pie_blocks;\n\tstruct rhashtable tc_ht;\n\tunsigned long int pie_use_bm[MAX_PIE_ENTRIES >> 5];\n\tint n_counters;\n\tunsigned long int octet_cntr_use_bm[MAX_COUNTERS >> 5];\n\tunsigned long int packet_cntr_use_bm[MAX_COUNTERS >> 4];\n\tstruct rhltable routes;\n\tunsigned long int route_use_bm[MAX_ROUTES >> 5];\n\tunsigned long int host_route_use_bm[MAX_HOST_ROUTES >> 5];\n\tstruct rtl838x_l3_intf *interfaces[MAX_INTERFACES];\n\tu16 intf_mtus[MAX_INTF_MTUS];\n\tint intf_mtu_count[MAX_INTF_MTUS];\n};\n\nvoid rtl838x_dbgfs_init(struct rtl838x_switch_priv *priv);\nvoid rtl930x_dbgfs_init(struct rtl838x_switch_priv *priv);\n\n#endif /* _RTL838X_H */\n"
  },
  {
    "path": "target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/rtl839x.c",
    "content": "// SPDX-License-Identifier: GPL-2.0-only\n\n#include <asm/mach-rtl838x/mach-rtl83xx.h>\n#include \"rtl83xx.h\"\n\nextern struct mutex smi_lock;\nextern struct rtl83xx_soc_info soc_info;\n\n/* Definition of the RTL839X-specific template field IDs as used in the PIE */\nenum template_field_id {\n\tTEMPLATE_FIELD_SPMMASK = 0,\n\tTEMPLATE_FIELD_SPM0 = 1,\t\t// Source portmask ports 0-15\n\tTEMPLATE_FIELD_SPM1 = 2,\t\t// Source portmask ports 16-31\n\tTEMPLATE_FIELD_SPM2 = 3,\t\t// Source portmask ports 32-47\n\tTEMPLATE_FIELD_SPM3 = 4,\t\t// Source portmask ports 48-56\n\tTEMPLATE_FIELD_DMAC0 = 5,\t\t// Destination MAC [15:0]\n\tTEMPLATE_FIELD_DMAC1 = 6,\t\t// Destination MAC [31:16]\n\tTEMPLATE_FIELD_DMAC2 = 7,\t\t// Destination MAC [47:32]\n\tTEMPLATE_FIELD_SMAC0 = 8,\t\t// Source MAC [15:0]\n\tTEMPLATE_FIELD_SMAC1 = 9,\t\t// Source MAC [31:16]\n\tTEMPLATE_FIELD_SMAC2 = 10,\t\t// Source MAC [47:32]\n\tTEMPLATE_FIELD_ETHERTYPE = 11,\t\t// Ethernet frame type field\n\t// Field-ID 12 is not used\n\tTEMPLATE_FIELD_OTAG = 13,\n\tTEMPLATE_FIELD_ITAG = 14,\n\tTEMPLATE_FIELD_SIP0 = 15,\n\tTEMPLATE_FIELD_SIP1 = 16,\n\tTEMPLATE_FIELD_DIP0 = 17,\n\tTEMPLATE_FIELD_DIP1 = 18,\n\tTEMPLATE_FIELD_IP_TOS_PROTO = 19,\n\tTEMPLATE_FIELD_IP_FLAG = 20,\n\tTEMPLATE_FIELD_L4_SPORT = 21,\n\tTEMPLATE_FIELD_L4_DPORT = 22,\n\tTEMPLATE_FIELD_L34_HEADER = 23,\n\tTEMPLATE_FIELD_ICMP_IGMP = 24,\n\tTEMPLATE_FIELD_VID_RANG0 = 25,\n\tTEMPLATE_FIELD_VID_RANG1 = 26,\n\tTEMPLATE_FIELD_L4_PORT_RANG = 27,\n\tTEMPLATE_FIELD_FIELD_SELECTOR_VALID = 28,\n\tTEMPLATE_FIELD_FIELD_SELECTOR_0 = 29,\n\tTEMPLATE_FIELD_FIELD_SELECTOR_1 = 30,\n\tTEMPLATE_FIELD_FIELD_SELECTOR_2 = 31,\n\tTEMPLATE_FIELD_FIELD_SELECTOR_3 = 32,\n\tTEMPLATE_FIELD_FIELD_SELECTOR_4 = 33,\n\tTEMPLATE_FIELD_FIELD_SELECTOR_5 = 34,\n\tTEMPLATE_FIELD_SIP2 = 35,\n\tTEMPLATE_FIELD_SIP3 = 36,\n\tTEMPLATE_FIELD_SIP4 = 37,\n\tTEMPLATE_FIELD_SIP5 = 38,\n\tTEMPLATE_FIELD_SIP6 = 39,\n\tTEMPLATE_FIELD_SIP7 = 40,\n\tTEMPLATE_FIELD_OLABEL = 41,\n\tTEMPLATE_FIELD_ILABEL = 42,\n\tTEMPLATE_FIELD_OILABEL = 43,\n\tTEMPLATE_FIELD_DPMMASK = 44,\n\tTEMPLATE_FIELD_DPM0 = 45,\n\tTEMPLATE_FIELD_DPM1 = 46,\n\tTEMPLATE_FIELD_DPM2 = 47,\n\tTEMPLATE_FIELD_DPM3 = 48,\n\tTEMPLATE_FIELD_L2DPM0 = 49,\n\tTEMPLATE_FIELD_L2DPM1 = 50,\n\tTEMPLATE_FIELD_L2DPM2 = 51,\n\tTEMPLATE_FIELD_L2DPM3 = 52,\n\tTEMPLATE_FIELD_IVLAN = 53,\n\tTEMPLATE_FIELD_OVLAN = 54,\n\tTEMPLATE_FIELD_FWD_VID = 55,\n\tTEMPLATE_FIELD_DIP2 = 56,\n\tTEMPLATE_FIELD_DIP3 = 57,\n\tTEMPLATE_FIELD_DIP4 = 58,\n\tTEMPLATE_FIELD_DIP5 = 59,\n\tTEMPLATE_FIELD_DIP6 = 60,\n\tTEMPLATE_FIELD_DIP7 = 61,\n};\n\n// Number of fixed templates predefined in the SoC\n#define N_FIXED_TEMPLATES 5\nstatic enum template_field_id fixed_templates[N_FIXED_TEMPLATES][N_FIXED_FIELDS] =\n{\n\t{\n\t  TEMPLATE_FIELD_SPM0, TEMPLATE_FIELD_SPM1, TEMPLATE_FIELD_ITAG,\n\t  TEMPLATE_FIELD_SMAC0, TEMPLATE_FIELD_SMAC1, TEMPLATE_FIELD_SMAC2,\n\t  TEMPLATE_FIELD_DMAC0, TEMPLATE_FIELD_DMAC1, TEMPLATE_FIELD_DMAC2,\n\t  TEMPLATE_FIELD_ETHERTYPE, TEMPLATE_FIELD_SPM2, TEMPLATE_FIELD_SPM3\n\t}, {\n\t  TEMPLATE_FIELD_SIP0, TEMPLATE_FIELD_SIP1, TEMPLATE_FIELD_DIP0,\n\t  TEMPLATE_FIELD_DIP1,TEMPLATE_FIELD_IP_TOS_PROTO, TEMPLATE_FIELD_L4_SPORT,\n\t  TEMPLATE_FIELD_L4_DPORT, TEMPLATE_FIELD_ICMP_IGMP, TEMPLATE_FIELD_SPM0,\n\t  TEMPLATE_FIELD_SPM1, TEMPLATE_FIELD_SPM2, TEMPLATE_FIELD_SPM3\n\t}, {\n\t  TEMPLATE_FIELD_DMAC0, TEMPLATE_FIELD_DMAC1, TEMPLATE_FIELD_DMAC2,\n\t  TEMPLATE_FIELD_ITAG, TEMPLATE_FIELD_ETHERTYPE, TEMPLATE_FIELD_IP_TOS_PROTO,\n\t  TEMPLATE_FIELD_L4_DPORT, TEMPLATE_FIELD_L4_SPORT, TEMPLATE_FIELD_SIP0,\n\t  TEMPLATE_FIELD_SIP1, TEMPLATE_FIELD_DIP0, TEMPLATE_FIELD_DIP1\n\t}, {\n\t  TEMPLATE_FIELD_DIP0, TEMPLATE_FIELD_DIP1, TEMPLATE_FIELD_DIP2,\n\t  TEMPLATE_FIELD_DIP3, TEMPLATE_FIELD_DIP4, TEMPLATE_FIELD_DIP5,\n\t  TEMPLATE_FIELD_DIP6, TEMPLATE_FIELD_DIP7, TEMPLATE_FIELD_L4_DPORT,\n\t  TEMPLATE_FIELD_L4_SPORT, TEMPLATE_FIELD_ICMP_IGMP, TEMPLATE_FIELD_IP_TOS_PROTO\n\t}, {\n\t  TEMPLATE_FIELD_SIP0, TEMPLATE_FIELD_SIP1, TEMPLATE_FIELD_SIP2,\n\t  TEMPLATE_FIELD_SIP3, TEMPLATE_FIELD_SIP4, TEMPLATE_FIELD_SIP5,\n\t  TEMPLATE_FIELD_SIP6, TEMPLATE_FIELD_SIP7, TEMPLATE_FIELD_SPM0,\n\t  TEMPLATE_FIELD_SPM1, TEMPLATE_FIELD_SPM2, TEMPLATE_FIELD_SPM3\n\t},\n};\n\nvoid rtl839x_print_matrix(void)\n{\n\tvolatile u64 *ptr9;\n\tint i;\n\n\tptr9 = RTL838X_SW_BASE + RTL839X_PORT_ISO_CTRL(0);\n\tfor (i = 0; i < 52; i += 4)\n\t\tpr_debug(\"> %16llx %16llx %16llx %16llx\\n\",\n\t\t\tptr9[i + 0], ptr9[i + 1], ptr9[i + 2], ptr9[i + 3]);\n\tpr_debug(\"CPU_PORT> %16llx\\n\", ptr9[52]);\n}\n\nstatic inline int rtl839x_port_iso_ctrl(int p)\n{\n\treturn RTL839X_PORT_ISO_CTRL(p);\n}\n\nstatic inline void rtl839x_exec_tbl0_cmd(u32 cmd)\n{\n\tsw_w32(cmd, RTL839X_TBL_ACCESS_CTRL_0);\n\tdo { } while (sw_r32(RTL839X_TBL_ACCESS_CTRL_0) & BIT(16));\n}\n\nstatic inline void rtl839x_exec_tbl1_cmd(u32 cmd)\n{\n\tsw_w32(cmd, RTL839X_TBL_ACCESS_CTRL_1);\n\tdo { } while (sw_r32(RTL839X_TBL_ACCESS_CTRL_1) & BIT(16));\n}\n\ninline void rtl839x_exec_tbl2_cmd(u32 cmd)\n{\n\tsw_w32(cmd, RTL839X_TBL_ACCESS_CTRL_2);\n\tdo { } while (sw_r32(RTL839X_TBL_ACCESS_CTRL_2) & (1 << 9));\n}\n\nstatic inline int rtl839x_tbl_access_data_0(int i)\n{\n\treturn RTL839X_TBL_ACCESS_DATA_0(i);\n}\n\nstatic void rtl839x_vlan_tables_read(u32 vlan, struct rtl838x_vlan_info *info)\n{\n\tu32 u, v, w;\n\t// Read VLAN table (0) via register 0\n\tstruct table_reg *r = rtl_table_get(RTL8390_TBL_0, 0);\n\n\trtl_table_read(r, vlan);\n\tu = sw_r32(rtl_table_data(r, 0));\n\tv = sw_r32(rtl_table_data(r, 1));\n\tw = sw_r32(rtl_table_data(r, 2));\n\trtl_table_release(r);\n\n\tinfo->tagged_ports = u;\n\tinfo->tagged_ports = (info->tagged_ports << 21) | ((v >> 11) & 0x1fffff);\n\tinfo->profile_id = w >> 30 | ((v & 1) << 2);\n\tinfo->hash_mc_fid = !!(w & BIT(2));\n\tinfo->hash_uc_fid = !!(w & BIT(3));\n\tinfo->fid = (v >> 3) & 0xff;\n\n\t// Read UNTAG table (0) via table register 1\n\tr = rtl_table_get(RTL8390_TBL_1, 0);\n\trtl_table_read(r, vlan);\n\tu = sw_r32(rtl_table_data(r, 0));\n\tv = sw_r32(rtl_table_data(r, 1));\n\trtl_table_release(r);\n\n\tinfo->untagged_ports = u;\n\tinfo->untagged_ports = (info->untagged_ports << 21) | ((v >> 11) & 0x1fffff);\n}\n\nstatic void rtl839x_vlan_set_tagged(u32 vlan, struct rtl838x_vlan_info *info)\n{\n\tu32 u, v, w;\n\t// Access VLAN table (0) via register 0\n\tstruct table_reg *r = rtl_table_get(RTL8390_TBL_0, 0);\n\n\tu = info->tagged_ports >> 21;\n\tv = info->tagged_ports << 11;\n\tv |= ((u32)info->fid) << 3;\n\tv |= info->hash_uc_fid ? BIT(2) : 0;\n\tv |= info->hash_mc_fid ? BIT(1) : 0;\n\tv |= (info->profile_id & 0x4) ? 1 : 0;\n\tw = ((u32)(info->profile_id & 3)) << 30;\n\n\tsw_w32(u, rtl_table_data(r, 0));\n\tsw_w32(v, rtl_table_data(r, 1));\n\tsw_w32(w, rtl_table_data(r, 2));\n\n\trtl_table_write(r, vlan);\n\trtl_table_release(r);\n}\n\nstatic void rtl839x_vlan_set_untagged(u32 vlan, u64 portmask)\n{\n\tu32 u, v;\n\n\t// Access UNTAG table (0) via table register 1\n\tstruct table_reg *r = rtl_table_get(RTL8390_TBL_1, 0);\n\n\tu = portmask >> 21;\n\tv = portmask << 11;\n\n\tsw_w32(u, rtl_table_data(r, 0));\n\tsw_w32(v, rtl_table_data(r, 1));\n\trtl_table_write(r, vlan);\n\n\trtl_table_release(r);\n}\n\n/* Sets the L2 forwarding to be based on either the inner VLAN tag or the outer\n */\nstatic void rtl839x_vlan_fwd_on_inner(int port, bool is_set)\n{\n\tif (is_set)\n\t\trtl839x_mask_port_reg_be(BIT_ULL(port), 0ULL, RTL839X_VLAN_PORT_FWD);\n\telse\n\t\trtl839x_mask_port_reg_be(0ULL, BIT_ULL(port), RTL839X_VLAN_PORT_FWD);\n}\n\n/*\n * Hash seed is vid (actually rvid) concatenated with the MAC address\n */\nstatic u64 rtl839x_l2_hash_seed(u64 mac, u32 vid)\n{\n\tu64 v = vid;\n\n\tv <<= 48;\n\tv |= mac;\n\n\treturn v;\n}\n\n/*\n * Applies the same hash algorithm as the one used currently by the ASIC to the seed\n * and returns a key into the L2 hash table\n */\nstatic u32 rtl839x_l2_hash_key(struct rtl838x_switch_priv *priv, u64 seed)\n{\n\tu32 h1, h2, h;\n\n\tif (sw_r32(priv->r->l2_ctrl_0) & 1) {\n\t\th1 = (u32) (((seed >> 60) & 0x3f) ^ ((seed >> 54) & 0x3f)\n\t\t\t\t^ ((seed >> 36) & 0x3f) ^ ((seed >> 30) & 0x3f)\n\t\t\t\t^ ((seed >> 12) & 0x3f) ^ ((seed >> 6) & 0x3f));\n\t\th2 = (u32) (((seed >> 48) & 0x3f) ^ ((seed >> 42) & 0x3f)\n\t\t\t\t^ ((seed >> 24) & 0x3f) ^ ((seed >> 18) & 0x3f)\n\t\t\t\t^ (seed & 0x3f));\n\t\th = (h1 << 6) | h2;\n\t} else {\n\t\th = (seed >> 60)\n\t\t\t^ ((((seed >> 48) & 0x3f) << 6) | ((seed >> 54) & 0x3f))\n\t\t\t^ ((seed >> 36) & 0xfff) ^ ((seed >> 24) & 0xfff)\n\t\t\t^ ((seed >> 12) & 0xfff) ^ (seed & 0xfff);\n\t}\n\n\treturn h;\n}\n\nstatic inline int rtl839x_mac_force_mode_ctrl(int p)\n{\n\treturn RTL839X_MAC_FORCE_MODE_CTRL + (p << 2);\n}\n\nstatic inline int rtl839x_mac_port_ctrl(int p)\n{\n\treturn RTL839X_MAC_PORT_CTRL(p);\n}\n\nstatic inline int rtl839x_l2_port_new_salrn(int p)\n{\n\treturn RTL839X_L2_PORT_NEW_SALRN(p);\n}\n\nstatic inline int rtl839x_l2_port_new_sa_fwd(int p)\n{\n\treturn RTL839X_L2_PORT_NEW_SA_FWD(p);\n}\n\nstatic inline int rtl839x_mac_link_spd_sts(int p)\n{\n\treturn RTL839X_MAC_LINK_SPD_STS(p);\n}\n\nstatic inline int rtl839x_trk_mbr_ctr(int group)\n{\n\treturn RTL839X_TRK_MBR_CTR + (group << 3);\n}\n\nstatic void rtl839x_fill_l2_entry(u32 r[], struct rtl838x_l2_entry *e)\n{\n\t/* Table contains different entry types, we need to identify the right one:\n\t * Check for MC entries, first\n\t */\n\te->is_ip_mc = !!(r[2] & BIT(31));\n\te->is_ipv6_mc = !!(r[2] & BIT(30));\n\te->type = L2_INVALID;\n\tif (!e->is_ip_mc && !e->is_ipv6_mc) {\n\t\te->mac[0] = (r[0] >> 12);\n\t\te->mac[1] = (r[0] >> 4);\n\t\te->mac[2] = ((r[1] >> 28) | (r[0] << 4));\n\t\te->mac[3] = (r[1] >> 20);\n\t\te->mac[4] = (r[1] >> 12);\n\t\te->mac[5] = (r[1] >> 4);\n\n\t\te->vid = (r[2] >> 4) & 0xfff;\n\t\te->rvid = (r[0] >> 20) & 0xfff;\n\n\t\t/* Is it a unicast entry? check multicast bit */\n\t\tif (!(e->mac[0] & 1)) {\n\t\t\te->is_static = !!((r[2] >> 18) & 1);\n\t\t\te->port = (r[2] >> 24) & 0x3f;\n\t\t\te->block_da = !!(r[2] & (1 << 19));\n\t\t\te->block_sa = !!(r[2] & (1 << 20));\n\t\t\te->suspended = !!(r[2] & (1 << 17));\n\t\t\te->next_hop = !!(r[2] & (1 << 16));\n\t\t\tif (e->next_hop) {\n\t\t\t\tpr_debug(\"Found next hop entry, need to read data\\n\");\n\t\t\t\te->nh_vlan_target = !!(r[2] & BIT(15));\n\t\t\t\te->nh_route_id = (r[2] >> 4) & 0x1ff;\n\t\t\t\te->vid = e->rvid;\n\t\t\t}\n\t\t\te->age = (r[2] >> 21) & 3;\n\t\t\te->valid = true;\n\t\t\tif (!(r[2] & 0xc0fd0000)) /* Check for valid entry */\n\t\t\t\te->valid = false;\n\t\t\telse\n\t\t\t\te->type = L2_UNICAST;\n\t\t} else {\n\t\t\te->valid = true;\n\t\t\te->type = L2_MULTICAST;\n\t\t\te->mc_portmask_index = (r[2] >> 6) & 0xfff;\n\t\t\te->vid = e->rvid;\n\t\t}\n\t} else { // IPv4 and IPv6 multicast\n\t\te->vid = e->rvid = (r[0] << 20) & 0xfff;\n\t\te->mc_gip = r[1];\n\t\te->mc_portmask_index = (r[2] >> 6) & 0xfff;\n\t}\n\tif (e->is_ip_mc) {\n\t\te->valid = true;\n\t\te->type = IP4_MULTICAST;\n\t}\n\tif (e->is_ipv6_mc) {\n\t\te->valid = true;\n\t\te->type = IP6_MULTICAST;\n\t}\n\t// pr_info(\"%s: vid %d, rvid: %d\\n\", __func__, e->vid, e->rvid);\n}\n\n/*\n * Fills the 3 SoC table registers r[] with the information in the rtl838x_l2_entry\n */\nstatic void rtl839x_fill_l2_row(u32 r[], struct rtl838x_l2_entry *e)\n{\n\tif (!e->valid) {\n\t\tr[0] = r[1] = r[2] = 0;\n\t\treturn;\n\t}\n\n\tr[2] = e->is_ip_mc ? BIT(31) : 0;\n\tr[2] |= e->is_ipv6_mc ? BIT(30) : 0;\n\n\tif (!e->is_ip_mc  && !e->is_ipv6_mc) {\n\t\tr[0] = ((u32)e->mac[0]) << 12;\n\t\tr[0] |= ((u32)e->mac[1]) << 4;\n\t\tr[0] |= ((u32)e->mac[2]) >> 4;\n\t\tr[1] = ((u32)e->mac[2]) << 28;\n\t\tr[1] |= ((u32)e->mac[3]) << 20;\n\t\tr[1] |= ((u32)e->mac[4]) << 12;\n\t\tr[1] |= ((u32)e->mac[5]) << 4;\n\n\t\tif (!(e->mac[0] & 1)) { // Not multicast\n\t\t\tr[2] |= e->is_static ? BIT(18) : 0;\n\t\t\tr[0] |= ((u32)e->rvid) << 20;\n\t\t\tr[2] |= e->port << 24;\n\t\t\tr[2] |= e->block_da ? BIT(19) : 0;\n\t\t\tr[2] |= e->block_sa ? BIT(20) : 0;\n\t\t\tr[2] |= e->suspended ? BIT(17) : 0;\n\t\t\tr[2] |= ((u32)e->age) << 21;\n\t\t\tif (e->next_hop) {\n\t\t\t\tr[2] |= BIT(16);\n\t\t\t\tr[2] |= e->nh_vlan_target ? BIT(15) : 0;\n\t\t\t\tr[2] |= (e->nh_route_id & 0x7ff) << 4;\n\t\t\t} else {\n\t\t\t\tr[2] |= e->vid << 4;\n\t\t\t}\n\t\t\tpr_debug(\"Write L2 NH: %08x %08x %08x\\n\", r[0], r[1], r[2]);\n\t\t} else {  // L2 Multicast\n\t\t\tr[0] |= ((u32)e->rvid) << 20;\n\t\t\tr[2] |= ((u32)e->mc_portmask_index) << 6;\n\t\t}\n\t} else { // IPv4 or IPv6 MC entry\n\t\tr[0] = ((u32)e->rvid) << 20;\n\t\tr[1] = e->mc_gip;\n\t\tr[2] |= ((u32)e->mc_portmask_index) << 6;\n\t}\n}\n\n/*\n * Read an L2 UC or MC entry out of a hash bucket of the L2 forwarding table\n * hash is the id of the bucket and pos is the position of the entry in that bucket\n * The data read from the SoC is filled into rtl838x_l2_entry\n */\nstatic u64 rtl839x_read_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_l2_entry *e)\n{\n\tu32 r[3];\n\tstruct table_reg *q = rtl_table_get(RTL8390_TBL_L2, 0);\n\tu32 idx = (0 << 14) | (hash << 2) | pos; // Search SRAM, with hash and at pos in bucket\n\tint i;\n\n\trtl_table_read(q, idx);\n\tfor (i= 0; i < 3; i++)\n\t\tr[i] = sw_r32(rtl_table_data(q, i));\n\n\trtl_table_release(q);\n\n\trtl839x_fill_l2_entry(r, e);\n\tif (!e->valid)\n\t\treturn 0;\n\n\treturn rtl839x_l2_hash_seed(ether_addr_to_u64(&e->mac[0]), e->rvid);\n}\n\nstatic void rtl839x_write_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_l2_entry *e)\n{\n\tu32 r[3];\n\tstruct table_reg *q = rtl_table_get(RTL8390_TBL_L2, 0);\n\tint i;\n\n\tu32 idx = (0 << 14) | (hash << 2) | pos; // Access SRAM, with hash and at pos in bucket\n\n\trtl839x_fill_l2_row(r, e);\n\n\tfor (i= 0; i < 3; i++)\n\t\tsw_w32(r[i], rtl_table_data(q, i));\n\n\trtl_table_write(q, idx);\n\trtl_table_release(q);\n}\n\nstatic u64 rtl839x_read_cam(int idx, struct rtl838x_l2_entry *e)\n{\n\tu32 r[3];\n\tstruct table_reg *q = rtl_table_get(RTL8390_TBL_L2, 1); // Access L2 Table 1\n\tint i;\n\n\trtl_table_read(q, idx);\n\tfor (i= 0; i < 3; i++)\n\t\tr[i] = sw_r32(rtl_table_data(q, i));\n\n\trtl_table_release(q);\n\n\trtl839x_fill_l2_entry(r, e);\n\tif (!e->valid)\n\t\treturn 0;\n\n\tpr_debug(\"Found in CAM: R1 %x R2 %x R3 %x\\n\", r[0], r[1], r[2]);\n\n\t// Return MAC with concatenated VID ac concatenated ID\n\treturn rtl839x_l2_hash_seed(ether_addr_to_u64(&e->mac[0]), e->rvid);\n}\n\nstatic void rtl839x_write_cam(int idx, struct rtl838x_l2_entry *e)\n{\n\tu32 r[3];\n\tstruct table_reg *q = rtl_table_get(RTL8390_TBL_L2, 1); // Access L2 Table 1\n\tint i;\n\n\trtl839x_fill_l2_row(r, e);\n\n\tfor (i= 0; i < 3; i++)\n\t\tsw_w32(r[i], rtl_table_data(q, i));\n\n\trtl_table_write(q, idx);\n\trtl_table_release(q);\n}\n\nstatic u64 rtl839x_read_mcast_pmask(int idx)\n{\n\tu64 portmask;\n\t// Read MC_PMSK (2) via register RTL8390_TBL_L2\n\tstruct table_reg *q = rtl_table_get(RTL8390_TBL_L2, 2);\n\n\trtl_table_read(q, idx);\n\tportmask = sw_r32(rtl_table_data(q, 0));\n\tportmask <<= 32;\n\tportmask |= sw_r32(rtl_table_data(q, 1));\n\tportmask >>= 11;  // LSB is bit 11 in data registers\n\trtl_table_release(q);\n\n\treturn portmask;\n}\n\nstatic void rtl839x_write_mcast_pmask(int idx, u64 portmask)\n{\n\t// Access MC_PMSK (2) via register RTL8380_TBL_L2\n\tstruct table_reg *q = rtl_table_get(RTL8390_TBL_L2, 2);\n\n\tportmask <<= 11; // LSB is bit 11 in data registers\n\tsw_w32((u32)(portmask >> 32), rtl_table_data(q, 0));\n\tsw_w32((u32)((portmask & 0xfffff800)), rtl_table_data(q, 1));\n\trtl_table_write(q, idx);\n\trtl_table_release(q);\n}\n\nstatic void rtl839x_vlan_profile_setup(int profile)\n{\n\tu32 p[2];\n\tu32 pmask_id = UNKNOWN_MC_PMASK;\n\n\tp[0] = pmask_id; // Use portmaks 0xfff for unknown IPv6 MC flooding\n\t// Enable L2 Learning BIT 0, portmask UNKNOWN_MC_PMASK for IP/L2-MC traffic flooding\n\tp[1] = 1 | pmask_id << 1 | pmask_id << 13;\n\n\tsw_w32(p[0], RTL839X_VLAN_PROFILE(profile));\n\tsw_w32(p[1], RTL839X_VLAN_PROFILE(profile) + 4);\n\n\trtl839x_write_mcast_pmask(UNKNOWN_MC_PMASK, 0x001fffffffffffff);\n}\n\nu64 rtl839x_traffic_get(int source)\n{\n\treturn rtl839x_get_port_reg_be(rtl839x_port_iso_ctrl(source));\n}\n\nvoid rtl839x_traffic_set(int source, u64 dest_matrix)\n{\n\trtl839x_set_port_reg_be(dest_matrix, rtl839x_port_iso_ctrl(source));\n}\n\nvoid rtl839x_traffic_enable(int source, int dest)\n{\n\trtl839x_mask_port_reg_be(0, BIT_ULL(dest), rtl839x_port_iso_ctrl(source));\n}\n\nvoid rtl839x_traffic_disable(int source, int dest)\n{\n\trtl839x_mask_port_reg_be(BIT_ULL(dest), 0, rtl839x_port_iso_ctrl(source));\n}\n\nstatic void rtl839x_l2_learning_setup(void)\n{\n\t/* Set portmask for broadcast (offset bit 12) and unknown unicast (offset 0)\n\t * address flooding to the reserved entry in the portmask table used\n\t * also for multicast flooding */\n\tsw_w32(UNKNOWN_MC_PMASK << 12 | UNKNOWN_MC_PMASK, RTL839X_L2_FLD_PMSK);\n\n\t// Limit learning to maximum: 32k entries, after that just flood (bits 0-1)\n\tsw_w32((0x7fff << 2) | 0, RTL839X_L2_LRN_CONSTRT);\n\n\t// Do not trap ARP packets to CPU_PORT\n\tsw_w32(0, RTL839X_SPCL_TRAP_ARP_CTRL);\n}\n\nstatic void rtl839x_enable_learning(int port, bool enable)\n{\n\t// Limit learning to maximum: 32k entries, after that just flood (bits 0-1)\n\n\tif (enable) {\n\t\t// flood after 32k entries\n\t\tsw_w32((0x7fff << 2) | 0, RTL839X_L2_PORT_LRN_CONSTRT + (port << 2));\n\t} else {\n\t\t// just forward\n\t\tsw_w32(0, RTL839X_L2_PORT_LRN_CONSTRT + (port << 2));\n\t}\n\n}\n\nstatic void rtl839x_enable_flood(int port, bool enable)\n{\n\tu32 flood_mask = sw_r32(RTL839X_L2_PORT_LRN_CONSTRT + (port << 2));\n\n\tif (enable)  {\n\t\t// flood\n\t\tflood_mask &= ~3;\n\t\tflood_mask |= 0;\n\t\tsw_w32(flood_mask, RTL839X_L2_PORT_LRN_CONSTRT + (port << 2));\n\t} else {\n\t\t// drop (bit 1)\n\t\tflood_mask &= ~3;\n\t\tflood_mask |= 1;\n\t\tsw_w32(flood_mask, RTL839X_L2_PORT_LRN_CONSTRT + (port << 2));\n\t}\n\n}\n\nstatic void rtl839x_enable_mcast_flood(int port, bool enable)\n{\n\n}\n\nstatic void rtl839x_enable_bcast_flood(int port, bool enable)\n{\n\n}\nirqreturn_t rtl839x_switch_irq(int irq, void *dev_id)\n{\n\tstruct dsa_switch *ds = dev_id;\n\tu32 status = sw_r32(RTL839X_ISR_GLB_SRC);\n\tu64 ports = rtl839x_get_port_reg_le(RTL839X_ISR_PORT_LINK_STS_CHG);\n\tu64 link;\n\tint i;\n\n\t/* Clear status */\n\trtl839x_set_port_reg_le(ports, RTL839X_ISR_PORT_LINK_STS_CHG);\n\tpr_debug(\"RTL8390 Link change: status: %x, ports %llx\\n\", status, ports);\n\n\tfor (i = 0; i < RTL839X_CPU_PORT; i++) {\n\t\tif (ports & BIT_ULL(i)) {\n\t\t\tlink = rtl839x_get_port_reg_le(RTL839X_MAC_LINK_STS);\n\t\t\tif (link & BIT_ULL(i))\n\t\t\t\tdsa_port_phylink_mac_change(ds, i, true);\n\t\t\telse\n\t\t\t\tdsa_port_phylink_mac_change(ds, i, false);\n\t\t}\n\t}\n\treturn IRQ_HANDLED;\n}\n\n// TODO: unused\nint rtl8390_sds_power(int mac, int val)\n{\n\tu32 offset = (mac == 48) ? 0x0 : 0x100;\n\tu32 mode = val ? 0 : 1;\n\n\tpr_debug(\"In %s: mac %d, set %d\\n\", __func__, mac, val);\n\n\tif ((mac != 48) && (mac != 49)) {\n\t\tpr_err(\"%s: not an SFP port: %d\\n\", __func__, mac);\n\t\treturn -1;\n\t}\n\n\t// Set bit 1003. 1000 starts at 7c\n\tsw_w32_mask(BIT(11), mode << 11, RTL839X_SDS12_13_PWR0 + offset);\n\n\treturn 0;\n}\n\nint rtl839x_read_phy(u32 port, u32 page, u32 reg, u32 *val)\n{\n\tu32 v;\n\n\tif (port > 63 || page > 4095 || reg > 31)\n\t\treturn -ENOTSUPP;\n\n\t// Take bug on RTL839x Rev <= C into account\n\tif (port >= RTL839X_CPU_PORT)\n\t\treturn -EIO;\n\n\tmutex_lock(&smi_lock);\n\n\tsw_w32_mask(0xffff0000, port << 16, RTL839X_PHYREG_DATA_CTRL);\n\tv = reg << 5 | page << 10 | ((page == 0x1fff) ? 0x1f : 0) << 23;\n\tsw_w32(v, RTL839X_PHYREG_ACCESS_CTRL);\n\n\tsw_w32(0x1ff, RTL839X_PHYREG_CTRL);\n\n\tv |= 1;\n\tsw_w32(v, RTL839X_PHYREG_ACCESS_CTRL);\n\n\tdo {\n\t} while (sw_r32(RTL839X_PHYREG_ACCESS_CTRL) & 0x1);\n\n\t*val = sw_r32(RTL839X_PHYREG_DATA_CTRL) & 0xffff;\n\n\tmutex_unlock(&smi_lock);\n\treturn 0;\n}\n\nint rtl839x_write_phy(u32 port, u32 page, u32 reg, u32 val)\n{\n\tu32 v;\n\tint err = 0;\n\n\tval &= 0xffff;\n\tif (port > 63 || page > 4095 || reg > 31)\n\t\treturn -ENOTSUPP;\n\n\t// Take bug on RTL839x Rev <= C into account\n\tif (port >= RTL839X_CPU_PORT)\n\t\treturn -EIO;\n\n\tmutex_lock(&smi_lock);\n\n\t// Set PHY to access\n\trtl839x_set_port_reg_le(BIT_ULL(port), RTL839X_PHYREG_PORT_CTRL);\n\n\tsw_w32_mask(0xffff0000, val << 16, RTL839X_PHYREG_DATA_CTRL);\n\n\tv = reg << 5 | page << 10 | ((page == 0x1fff) ? 0x1f : 0) << 23;\n\tsw_w32(v, RTL839X_PHYREG_ACCESS_CTRL);\n\n\tsw_w32(0x1ff, RTL839X_PHYREG_CTRL);\n\n\tv |= BIT(3) | 1; /* Write operation and execute */\n\tsw_w32(v, RTL839X_PHYREG_ACCESS_CTRL);\n\n\tdo {\n\t} while (sw_r32(RTL839X_PHYREG_ACCESS_CTRL) & 0x1);\n\n\tif (sw_r32(RTL839X_PHYREG_ACCESS_CTRL) & 0x2)\n\t\terr = -EIO;\n\n\tmutex_unlock(&smi_lock);\n\treturn err;\n}\n\n/*\n * Read an mmd register of the PHY\n */\nint rtl839x_read_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 *val)\n{\n\tint err = 0;\n\tu32 v;\n\n\t// Take bug on RTL839x Rev <= C into account\n\tif (port >= RTL839X_CPU_PORT)\n\t\treturn -EIO;\n\n\tmutex_lock(&smi_lock);\n\n\t// Set PHY to access\n\tsw_w32_mask(0xffff << 16, port << 16, RTL839X_PHYREG_DATA_CTRL);\n\n\t// Set MMD device number and register to write to\n\tsw_w32(devnum << 16 | (regnum & 0xffff), RTL839X_PHYREG_MMD_CTRL);\n\n\tv = BIT(2) | BIT(0); // MMD-access | EXEC\n\tsw_w32(v, RTL839X_PHYREG_ACCESS_CTRL);\n\n\tdo {\n\t\tv = sw_r32(RTL839X_PHYREG_ACCESS_CTRL);\n\t} while (v & BIT(0));\n\t// There is no error-checking via BIT 1 of v, as it does not seem to be set correctly\n\t*val = (sw_r32(RTL839X_PHYREG_DATA_CTRL) & 0xffff);\n\tpr_debug(\"%s: port %d, regnum: %x, val: %x (err %d)\\n\", __func__, port, regnum, *val, err);\n\n\tmutex_unlock(&smi_lock);\n\n\treturn err;\n}\n\n/*\n * Write to an mmd register of the PHY\n */\nint rtl839x_write_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 val)\n{\n\tint err = 0;\n\tu32 v;\n\n\t// Take bug on RTL839x Rev <= C into account\n\tif (port >= RTL839X_CPU_PORT)\n\t\treturn -EIO;\n\n\tmutex_lock(&smi_lock);\n\n\t// Set PHY to access\n\trtl839x_set_port_reg_le(BIT_ULL(port), RTL839X_PHYREG_PORT_CTRL);\n\n\t// Set data to write\n\tsw_w32_mask(0xffff << 16, val << 16, RTL839X_PHYREG_DATA_CTRL);\n\n\t// Set MMD device number and register to write to\n\tsw_w32(devnum << 16 | (regnum & 0xffff), RTL839X_PHYREG_MMD_CTRL);\n\n\tv = BIT(3) | BIT(2) | BIT(0); // WRITE | MMD-access | EXEC\n\tsw_w32(v, RTL839X_PHYREG_ACCESS_CTRL);\n\n\tdo {\n\t\tv = sw_r32(RTL839X_PHYREG_ACCESS_CTRL);\n\t} while (v & BIT(0));\n\n\tpr_debug(\"%s: port %d, regnum: %x, val: %x (err %d)\\n\", __func__, port, regnum, val, err);\n\tmutex_unlock(&smi_lock);\n\treturn err;\n}\n\nvoid rtl8390_get_version(struct rtl838x_switch_priv *priv)\n{\n\tu32 info, model;\n\n\tsw_w32_mask(0xf << 28, 0xa << 28, RTL839X_CHIP_INFO);\n\tinfo = sw_r32(RTL839X_CHIP_INFO);\n\n\tmodel = sw_r32(RTL839X_MODEL_NAME_INFO);\n\tpriv->version = RTL8390_VERSION_A + ((model & 0x3f) >> 1);\n\n\tpr_info(\"RTL839X Chip-Info: %x, version %c\\n\", info, priv->version);\n}\n\nvoid rtl839x_vlan_profile_dump(int profile)\n{\n\tu32 p[2];\n\n\tif (profile < 0 || profile > 7)\n\t\treturn;\n\n\tp[0] = sw_r32(RTL839X_VLAN_PROFILE(profile));\n\tp[1] = sw_r32(RTL839X_VLAN_PROFILE(profile) + 4);\n\n\tpr_info(\"VLAN profile %d: L2 learning: %d, UNKN L2MC FLD PMSK %d, \\\n\t\tUNKN IPMC FLD PMSK %d, UNKN IPv6MC FLD PMSK: %d\",\n\t\tprofile, p[1] & 1, (p[1] >> 1) & 0xfff, (p[1] >> 13) & 0xfff,\n\t\t(p[0]) & 0xfff);\n\tpr_info(\"VLAN profile %d: raw %08x, %08x\\n\", profile, p[0], p[1]);\n}\n\nstatic void rtl839x_stp_get(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[])\n{\n\tint i;\n\tu32 cmd = 1 << 16 /* Execute cmd */\n\t\t| 0 << 15 /* Read */\n\t\t| 5 << 12 /* Table type 0b101 */\n\t\t| (msti & 0xfff);\n\tpriv->r->exec_tbl0_cmd(cmd);\n\n\tfor (i = 0; i < 4; i++)\n\t\tport_state[i] = sw_r32(priv->r->tbl_access_data_0(i));\n}\n\nstatic void rtl839x_stp_set(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[])\n{\n\tint i;\n\tu32 cmd = 1 << 16 /* Execute cmd */\n\t\t| 1 << 15 /* Write */\n\t\t| 5 << 12 /* Table type 0b101 */\n\t\t| (msti & 0xfff);\n\tfor (i = 0; i < 4; i++)\n\t\tsw_w32(port_state[i], priv->r->tbl_access_data_0(i));\n\tpriv->r->exec_tbl0_cmd(cmd);\n}\n\n/*\n * Enables or disables the EEE/EEEP capability of a port\n */\nvoid rtl839x_port_eee_set(struct rtl838x_switch_priv *priv, int port, bool enable)\n{\n\tu32 v;\n\n\t// This works only for Ethernet ports, and on the RTL839X, ports above 47 are SFP\n\tif (port >= 48)\n\t\treturn;\n\n\tenable = true;\n\tpr_debug(\"In %s: setting port %d to %d\\n\", __func__, port, enable);\n\tv = enable ? 0xf : 0x0;\n\n\t// Set EEE for 100, 500, 1000MBit and 10GBit\n\tsw_w32_mask(0xf << 8, v << 8, rtl839x_mac_force_mode_ctrl(port));\n\n\t// Set TX/RX EEE state\n\tv = enable ? 0x3 : 0x0;\n\tsw_w32(v, RTL839X_EEE_CTRL(port));\n\n\tpriv->ports[port].eee_enabled = enable;\n}\n\n/*\n * Get EEE own capabilities and negotiation result\n */\nint rtl839x_eee_port_ability(struct rtl838x_switch_priv *priv, struct ethtool_eee *e, int port)\n{\n\tu64 link, a;\n\n\tif (port >= 48)\n\t\treturn 0;\n\n\tlink = rtl839x_get_port_reg_le(RTL839X_MAC_LINK_STS);\n\tif (!(link & BIT_ULL(port)))\n\t\treturn 0;\n\n\tif (sw_r32(rtl839x_mac_force_mode_ctrl(port)) & BIT(8))\n\t\te->advertised |= ADVERTISED_100baseT_Full;\n\n\tif (sw_r32(rtl839x_mac_force_mode_ctrl(port)) & BIT(10))\n\t\te->advertised |= ADVERTISED_1000baseT_Full;\n\n\ta = rtl839x_get_port_reg_le(RTL839X_MAC_EEE_ABLTY);\n\tpr_info(\"Link partner: %016llx\\n\", a);\n\tif (rtl839x_get_port_reg_le(RTL839X_MAC_EEE_ABLTY) & BIT_ULL(port)) {\n\t\te->lp_advertised = ADVERTISED_100baseT_Full;\n\t\te->lp_advertised |= ADVERTISED_1000baseT_Full;\n\t\treturn 1;\n\t}\n\n\treturn 0;\n}\n\nstatic void rtl839x_init_eee(struct rtl838x_switch_priv *priv, bool enable)\n{\n\tint i;\n\n\tpr_info(\"Setting up EEE, state: %d\\n\", enable);\n\n\t// Set wake timer for TX and pause timer both to 0x21\n\tsw_w32_mask(0xff << 20| 0xff, 0x21 << 20| 0x21, RTL839X_EEE_TX_TIMER_GELITE_CTRL);\n\t// Set pause wake timer for GIGA-EEE to 0x11\n\tsw_w32_mask(0xff << 20, 0x11 << 20, RTL839X_EEE_TX_TIMER_GIGA_CTRL);\n\t// Set pause wake timer for 10GBit ports to 0x11\n\tsw_w32_mask(0xff << 20, 0x11 << 20, RTL839X_EEE_TX_TIMER_10G_CTRL);\n\n\t// Setup EEE on all ports\n\tfor (i = 0; i < priv->cpu_port; i++) {\n\t\tif (priv->ports[i].phy)\n\t\t\trtl839x_port_eee_set(priv, i, enable);\n\t}\n\tpriv->eee_enabled = enable;\n}\n\nstatic void rtl839x_pie_lookup_enable(struct rtl838x_switch_priv *priv, int index)\n{\n\tint block = index / PIE_BLOCK_SIZE;\n\n\tsw_w32_mask(0, BIT(block), RTL839X_ACL_BLK_LOOKUP_CTRL);\n}\n\n/*\n * Delete a range of Packet Inspection Engine rules\n */\nstatic int rtl839x_pie_rule_del(struct rtl838x_switch_priv *priv, int index_from, int index_to)\n{\n\tu32 v = (index_from << 1)| (index_to << 13 ) | BIT(0);\n\n\tpr_debug(\"%s: from %d to %d\\n\", __func__, index_from, index_to);\n\tmutex_lock(&priv->reg_mutex);\n\n\t// Write from-to and execute bit into control register\n\tsw_w32(v, RTL839X_ACL_CLR_CTRL);\n\n\t// Wait until command has completed\n\tdo {\n\t} while (sw_r32(RTL839X_ACL_CLR_CTRL) & BIT(0));\n\n\tmutex_unlock(&priv->reg_mutex);\n\treturn 0;\n}\n\n/*\n * Reads the intermediate representation of the templated match-fields of the\n * PIE rule in the pie_rule structure and fills in the raw data fields in the\n * raw register space r[].\n * The register space configuration size is identical for the RTL8380/90 and RTL9300,\n * however the RTL9310 has 2 more registers / fields and the physical field-ids are different\n * on all SoCs\n * On the RTL8390 the template mask registers are not word-aligned!\n */\nstatic void rtl839x_write_pie_templated(u32 r[], struct pie_rule *pr, enum template_field_id t[])\n{\n\tint i;\n\tenum template_field_id field_type;\n\tu16 data, data_m;\n\n\tfor (i = 0; i < N_FIXED_FIELDS; i++) {\n\t\tfield_type = t[i];\n\t\tdata = data_m = 0;\n\n\t\tswitch (field_type) {\n\t\tcase TEMPLATE_FIELD_SPM0:\n\t\t\tdata = pr->spm;\n\t\t\tdata_m = pr->spm_m;\n\t\t\tbreak;\n\t\tcase TEMPLATE_FIELD_SPM1:\n\t\t\tdata = pr->spm >> 16;\n\t\t\tdata_m = pr->spm_m >> 16;\n\t\t\tbreak;\n\t\tcase TEMPLATE_FIELD_SPM2:\n\t\t\tdata = pr->spm >> 32;\n\t\t\tdata_m = pr->spm_m >> 32;\n\t\t\tbreak;\n\t\tcase TEMPLATE_FIELD_SPM3:\n\t\t\tdata = pr->spm >> 48;\n\t\t\tdata_m = pr->spm_m >> 48;\n\t\t\tbreak;\n\t\tcase TEMPLATE_FIELD_OTAG:\n\t\t\tdata = pr->otag;\n\t\t\tdata_m = pr->otag_m;\n\t\t\tbreak;\n\t\tcase TEMPLATE_FIELD_SMAC0:\n\t\t\tdata = pr->smac[4];\n\t\t\tdata = (data << 8) | pr->smac[5];\n\t\t\tdata_m = pr->smac_m[4];\n\t\t\tdata_m = (data_m << 8) | pr->smac_m[5];\n\t\t\tbreak;\n\t\tcase TEMPLATE_FIELD_SMAC1:\n\t\t\tdata = pr->smac[2];\n\t\t\tdata = (data << 8) | pr->smac[3];\n\t\t\tdata_m = pr->smac_m[2];\n\t\t\tdata_m = (data_m << 8) | pr->smac_m[3];\n\t\t\tbreak;\n\t\tcase TEMPLATE_FIELD_SMAC2:\n\t\t\tdata = pr->smac[0];\n\t\t\tdata = (data << 8) | pr->smac[1];\n\t\t\tdata_m = pr->smac_m[0];\n\t\t\tdata_m = (data_m << 8) | pr->smac_m[1];\n\t\t\tbreak;\n\t\tcase TEMPLATE_FIELD_DMAC0:\n\t\t\tdata = pr->dmac[4];\n\t\t\tdata = (data << 8) | pr->dmac[5];\n\t\t\tdata_m = pr->dmac_m[4];\n\t\t\tdata_m = (data_m << 8) | pr->dmac_m[5];\n\t\t\tbreak;\n\t\tcase TEMPLATE_FIELD_DMAC1:\n\t\t\tdata = pr->dmac[2];\n\t\t\tdata = (data << 8) | pr->dmac[3];\n\t\t\tdata_m = pr->dmac_m[2];\n\t\t\tdata_m = (data_m << 8) | pr->dmac_m[3];\n\t\t\tbreak;\n\t\tcase TEMPLATE_FIELD_DMAC2:\n\t\t\tdata = pr->dmac[0];\n\t\t\tdata = (data << 8) | pr->dmac[1];\n\t\t\tdata_m = pr->dmac_m[0];\n\t\t\tdata_m = (data_m << 8) | pr->dmac_m[1];\n\t\t\tbreak;\n\t\tcase TEMPLATE_FIELD_ETHERTYPE:\n\t\t\tdata = pr->ethertype;\n\t\t\tdata_m = pr->ethertype_m;\n\t\t\tbreak;\n\t\tcase TEMPLATE_FIELD_ITAG:\n\t\t\tdata = pr->itag;\n\t\t\tdata_m = pr->itag_m;\n\t\t\tbreak;\n\t\tcase TEMPLATE_FIELD_SIP0:\n\t\t\tif (pr->is_ipv6) {\n\t\t\t\tdata = pr->sip6.s6_addr16[7];\n\t\t\t\tdata_m = pr->sip6_m.s6_addr16[7];\n\t\t\t} else {\n\t\t\t\tdata = pr->sip;\n\t\t\t\tdata_m = pr->sip_m;\n\t\t\t}\n\t\t\tbreak;\n\t\tcase TEMPLATE_FIELD_SIP1:\n\t\t\tif (pr->is_ipv6) {\n\t\t\t\tdata = pr->sip6.s6_addr16[6];\n\t\t\t\tdata_m = pr->sip6_m.s6_addr16[6];\n\t\t\t} else {\n\t\t\t\tdata = pr->sip >> 16;\n\t\t\t\tdata_m = pr->sip_m >> 16;\n\t\t\t}\n\t\t\tbreak;\n\n\t\tcase TEMPLATE_FIELD_SIP2:\n\t\tcase TEMPLATE_FIELD_SIP3:\n\t\tcase TEMPLATE_FIELD_SIP4:\n\t\tcase TEMPLATE_FIELD_SIP5:\n\t\tcase TEMPLATE_FIELD_SIP6:\n\t\tcase TEMPLATE_FIELD_SIP7:\n\t\t\tdata = pr->sip6.s6_addr16[5 - (field_type - TEMPLATE_FIELD_SIP2)];\n\t\t\tdata_m = pr->sip6_m.s6_addr16[5 - (field_type - TEMPLATE_FIELD_SIP2)];\n\t\t\tbreak;\n\n\t\tcase TEMPLATE_FIELD_DIP0:\n\t\t\tif (pr->is_ipv6) {\n\t\t\t\tdata = pr->dip6.s6_addr16[7];\n\t\t\t\tdata_m = pr->dip6_m.s6_addr16[7];\n\t\t\t} else {\n\t\t\t\tdata = pr->dip;\n\t\t\t\tdata_m = pr->dip_m;\n\t\t\t}\n\t\t\tbreak;\n\n\t\tcase TEMPLATE_FIELD_DIP1:\n\t\t\tif (pr->is_ipv6) {\n\t\t\t\tdata = pr->dip6.s6_addr16[6];\n\t\t\t\tdata_m = pr->dip6_m.s6_addr16[6];\n\t\t\t} else {\n\t\t\t\tdata = pr->dip >> 16;\n\t\t\t\tdata_m = pr->dip_m >> 16;\n\t\t\t}\n\t\t\tbreak;\n\n\t\tcase TEMPLATE_FIELD_DIP2:\n\t\tcase TEMPLATE_FIELD_DIP3:\n\t\tcase TEMPLATE_FIELD_DIP4:\n\t\tcase TEMPLATE_FIELD_DIP5:\n\t\tcase TEMPLATE_FIELD_DIP6:\n\t\tcase TEMPLATE_FIELD_DIP7:\n\t\t\tdata = pr->dip6.s6_addr16[5 - (field_type - TEMPLATE_FIELD_DIP2)];\n\t\t\tdata_m = pr->dip6_m.s6_addr16[5 - (field_type - TEMPLATE_FIELD_DIP2)];\n\t\t\tbreak;\n\n\t\tcase TEMPLATE_FIELD_IP_TOS_PROTO:\n\t\t\tdata = pr->tos_proto;\n\t\t\tdata_m = pr->tos_proto_m;\n\t\t\tbreak;\n\t\tcase TEMPLATE_FIELD_L4_SPORT:\n\t\t\tdata = pr->sport;\n\t\t\tdata_m = pr->sport_m;\n\t\t\tbreak;\n\t\tcase TEMPLATE_FIELD_L4_DPORT:\n\t\t\tdata = pr->dport;\n\t\t\tdata_m = pr->dport_m;\n\t\t\tbreak;\n\t\tcase TEMPLATE_FIELD_ICMP_IGMP:\n\t\t\tdata = pr->icmp_igmp;\n\t\t\tdata_m = pr->icmp_igmp_m;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tpr_info(\"%s: unknown field %d\\n\", __func__, field_type);\n\t\t}\n\n\t\t// On the RTL8390, the mask fields are not word aligned!\n\t\tif (!(i % 2)) {\n\t\t\tr[5 - i / 2] = data;\n\t\t\tr[12 - i / 2] |= ((u32)data_m << 8);\n\t\t} else {\n\t\t\tr[5 - i / 2] |= ((u32)data) << 16;\n\t\t\tr[12 - i / 2] |= ((u32)data_m) << 24;\n\t\t\tr[11 - i / 2] |= ((u32)data_m) >> 8;\n\t\t}\n\t}\n}\n\n/*\n * Creates the intermediate representation of the templated match-fields of the\n * PIE rule in the pie_rule structure by reading the raw data fields in the\n * raw register space r[].\n * The register space configuration size is identical for the RTL8380/90 and RTL9300,\n * however the RTL9310 has 2 more registers / fields and the physical field-ids\n * On the RTL8390 the template mask registers are not word-aligned!\n */\nvoid rtl839x_read_pie_templated(u32 r[], struct pie_rule *pr, enum template_field_id t[])\n{\n\tint i;\n\tenum template_field_id field_type;\n\tu16 data, data_m;\n\n\tfor (i = 0; i < N_FIXED_FIELDS; i++) {\n\t\tfield_type = t[i];\n\t\tif (!(i % 2)) {\n\t\t\tdata = r[5 - i / 2];\n\t\t\tdata_m = r[12 - i / 2];\n\t\t} else {\n\t\t\tdata = r[5 - i / 2] >> 16;\n\t\t\tdata_m = r[12 - i / 2] >> 16;\n\t\t}\n\n\t\tswitch (field_type) {\n\t\tcase TEMPLATE_FIELD_SPM0:\n\t\t\tpr->spm = (pr->spn << 16) | data;\n\t\t\tpr->spm_m = (pr->spn << 16) | data_m;\n\t\t\tbreak;\n\t\tcase TEMPLATE_FIELD_SPM1:\n\t\t\tpr->spm = data;\n\t\t\tpr->spm_m = data_m;\n\t\t\tbreak;\n\t\tcase TEMPLATE_FIELD_OTAG:\n\t\t\tpr->otag = data;\n\t\t\tpr->otag_m = data_m;\n\t\t\tbreak;\n\t\tcase TEMPLATE_FIELD_SMAC0:\n\t\t\tpr->smac[4] = data >> 8;\n\t\t\tpr->smac[5] = data;\n\t\t\tpr->smac_m[4] = data >> 8;\n\t\t\tpr->smac_m[5] = data;\n\t\t\tbreak;\n\t\tcase TEMPLATE_FIELD_SMAC1:\n\t\t\tpr->smac[2] = data >> 8;\n\t\t\tpr->smac[3] = data;\n\t\t\tpr->smac_m[2] = data >> 8;\n\t\t\tpr->smac_m[3] = data;\n\t\t\tbreak;\n\t\tcase TEMPLATE_FIELD_SMAC2:\n\t\t\tpr->smac[0] = data >> 8;\n\t\t\tpr->smac[1] = data;\n\t\t\tpr->smac_m[0] = data >> 8;\n\t\t\tpr->smac_m[1] = data;\n\t\t\tbreak;\n\t\tcase TEMPLATE_FIELD_DMAC0:\n\t\t\tpr->dmac[4] = data >> 8;\n\t\t\tpr->dmac[5] = data;\n\t\t\tpr->dmac_m[4] = data >> 8;\n\t\t\tpr->dmac_m[5] = data;\n\t\t\tbreak;\n\t\tcase TEMPLATE_FIELD_DMAC1:\n\t\t\tpr->dmac[2] = data >> 8;\n\t\t\tpr->dmac[3] = data;\n\t\t\tpr->dmac_m[2] = data >> 8;\n\t\t\tpr->dmac_m[3] = data;\n\t\t\tbreak;\n\t\tcase TEMPLATE_FIELD_DMAC2:\n\t\t\tpr->dmac[0] = data >> 8;\n\t\t\tpr->dmac[1] = data;\n\t\t\tpr->dmac_m[0] = data >> 8;\n\t\t\tpr->dmac_m[1] = data;\n\t\t\tbreak;\n\t\tcase TEMPLATE_FIELD_ETHERTYPE:\n\t\t\tpr->ethertype = data;\n\t\t\tpr->ethertype_m = data_m;\n\t\t\tbreak;\n\t\tcase TEMPLATE_FIELD_ITAG:\n\t\t\tpr->itag = data;\n\t\t\tpr->itag_m = data_m;\n\t\t\tbreak;\n\t\tcase TEMPLATE_FIELD_SIP0:\n\t\t\tpr->sip = data;\n\t\t\tpr->sip_m = data_m;\n\t\t\tbreak;\n\t\tcase TEMPLATE_FIELD_SIP1:\n\t\t\tpr->sip = (pr->sip << 16) | data;\n\t\t\tpr->sip_m = (pr->sip << 16) | data_m;\n\t\t\tbreak;\n\t\tcase TEMPLATE_FIELD_SIP2:\n\t\t\tpr->is_ipv6 = true;\n\t\t\t// Make use of limitiations on the position of the match values\n\t\t\tipv6_addr_set(&pr->sip6, pr->sip, r[5 - i / 2],\n\t\t\t\t      r[4 - i / 2], r[3 - i / 2]);\n\t\t\tipv6_addr_set(&pr->sip6_m, pr->sip_m, r[5 - i / 2],\n\t\t\t\t      r[4 - i / 2], r[3 - i / 2]);\n\t\tcase TEMPLATE_FIELD_SIP3:\n\t\tcase TEMPLATE_FIELD_SIP4:\n\t\tcase TEMPLATE_FIELD_SIP5:\n\t\tcase TEMPLATE_FIELD_SIP6:\n\t\tcase TEMPLATE_FIELD_SIP7:\n\t\t\tbreak;\n\n\t\tcase TEMPLATE_FIELD_DIP0:\n\t\t\tpr->dip = data;\n\t\t\tpr->dip_m = data_m;\n\t\t\tbreak;\n\n\t\tcase TEMPLATE_FIELD_DIP1:\n\t\t\tpr->dip = (pr->dip << 16) | data;\n\t\t\tpr->dip_m = (pr->dip << 16) | data_m;\n\t\t\tbreak;\n\n\t\tcase TEMPLATE_FIELD_DIP2:\n\t\t\tpr->is_ipv6 = true;\n\t\t\tipv6_addr_set(&pr->dip6, pr->dip, r[5 - i / 2],\n\t\t\t\t      r[4 - i / 2], r[3 - i / 2]);\n\t\t\tipv6_addr_set(&pr->dip6_m, pr->dip_m, r[5 - i / 2],\n\t\t\t\t      r[4 - i / 2], r[3 - i / 2]);\n\t\tcase TEMPLATE_FIELD_DIP3:\n\t\tcase TEMPLATE_FIELD_DIP4:\n\t\tcase TEMPLATE_FIELD_DIP5:\n\t\tcase TEMPLATE_FIELD_DIP6:\n\t\tcase TEMPLATE_FIELD_DIP7:\n\t\t\tbreak;\n\t\tcase TEMPLATE_FIELD_IP_TOS_PROTO:\n\t\t\tpr->tos_proto = data;\n\t\t\tpr->tos_proto_m = data_m;\n\t\t\tbreak;\n\t\tcase TEMPLATE_FIELD_L4_SPORT:\n\t\t\tpr->sport = data;\n\t\t\tpr->sport_m = data_m;\n\t\t\tbreak;\n\t\tcase TEMPLATE_FIELD_L4_DPORT:\n\t\t\tpr->dport = data;\n\t\t\tpr->dport_m = data_m;\n\t\t\tbreak;\n\t\tcase TEMPLATE_FIELD_ICMP_IGMP:\n\t\t\tpr->icmp_igmp = data;\n\t\t\tpr->icmp_igmp_m = data_m;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tpr_info(\"%s: unknown field %d\\n\", __func__, field_type);\n\t\t}\n\t}\n}\n\nstatic void rtl839x_read_pie_fixed_fields(u32 r[], struct pie_rule *pr)\n{\n\tpr->spmmask_fix = (r[6] >> 30) & 0x3;\n\tpr->spn = (r[6] >> 24) & 0x3f;\n\tpr->mgnt_vlan = (r[6] >> 23) & 1;\n\tpr->dmac_hit_sw = (r[6] >> 22) & 1;\n\tpr->not_first_frag = (r[6] >> 21) & 1;\n\tpr->frame_type_l4 = (r[6] >> 18) & 7;\n\tpr->frame_type = (r[6] >> 16) & 3;\n\tpr->otag_fmt = (r[6] >> 15) & 1;\n\tpr->itag_fmt = (r[6] >> 14) & 1;\n\tpr->otag_exist = (r[6] >> 13) & 1;\n\tpr->itag_exist = (r[6] >> 12) & 1;\n\tpr->frame_type_l2 = (r[6] >> 10) & 3;\n\tpr->tid = (r[6] >> 8) & 3;\n\n\tpr->spmmask_fix_m = (r[12] >> 6) & 0x3;\n\tpr->spn_m = r[12]  & 0x3f;\n\tpr->mgnt_vlan_m = (r[13] >> 31) & 1;\n\tpr->dmac_hit_sw_m = (r[13] >> 30) & 1;\n\tpr->not_first_frag_m = (r[13] >> 29) & 1;\n\tpr->frame_type_l4_m = (r[13] >> 26) & 7;\n\tpr->frame_type_m = (r[13] >> 24) & 3;\n\tpr->otag_fmt_m = (r[13] >> 23) & 1;\n\tpr->itag_fmt_m = (r[13] >> 22) & 1;\n\tpr->otag_exist_m = (r[13] >> 21) & 1;\n\tpr->itag_exist_m = (r[13] >> 20) & 1;\n\tpr->frame_type_l2_m = (r[13] >> 18) & 3;\n\tpr->tid_m = (r[13] >> 16) & 3;\n\n\tpr->valid = r[13] & BIT(15);\n\tpr->cond_not = r[13] & BIT(14);\n\tpr->cond_and1 = r[13] & BIT(13);\n\tpr->cond_and2 = r[13] & BIT(12);\n}\n\nstatic void rtl839x_write_pie_fixed_fields(u32 r[],  struct pie_rule *pr)\n{\n\tr[6] = ((u32) (pr->spmmask_fix & 0x3)) << 30;\n\tr[6] |= ((u32) (pr->spn & 0x3f)) << 24;\n\tr[6] |= pr->mgnt_vlan ? BIT(23) : 0;\n\tr[6] |= pr->dmac_hit_sw ? BIT(22) : 0;\n\tr[6] |= pr->not_first_frag ? BIT(21) : 0;\n\tr[6] |= ((u32) (pr->frame_type_l4 & 0x7)) << 18;\n\tr[6] |= ((u32) (pr->frame_type & 0x3)) << 16;\n\tr[6] |= pr->otag_fmt ? BIT(15) : 0;\n\tr[6] |= pr->itag_fmt ? BIT(14) : 0;\n\tr[6] |= pr->otag_exist ? BIT(13) : 0;\n\tr[6] |= pr->itag_exist ? BIT(12) : 0;\n\tr[6] |= ((u32) (pr->frame_type_l2 & 0x3)) << 10;\n\tr[6] |= ((u32) (pr->tid & 0x3)) << 8;\n\n\tr[12] |= ((u32) (pr->spmmask_fix_m & 0x3)) << 6;\n\tr[12] |= (u32) (pr->spn_m & 0x3f);\n\tr[13] |= pr->mgnt_vlan_m ? BIT(31) : 0;\n\tr[13] |= pr->dmac_hit_sw_m ? BIT(30) : 0;\n\tr[13] |= pr->not_first_frag_m ? BIT(29) : 0;\n\tr[13] |= ((u32) (pr->frame_type_l4_m & 0x7)) << 26;\n\tr[13] |= ((u32) (pr->frame_type_m & 0x3)) << 24;\n\tr[13] |= pr->otag_fmt_m ? BIT(23) : 0;\n\tr[13] |= pr->itag_fmt_m ? BIT(22) : 0;\n\tr[13] |= pr->otag_exist_m ? BIT(21) : 0;\n\tr[13] |= pr->itag_exist_m ? BIT(20) : 0;\n\tr[13] |= ((u32) (pr->frame_type_l2_m & 0x3)) << 18;\n\tr[13] |= ((u32) (pr->tid_m & 0x3)) << 16;\n\n\tr[13] |= pr->valid ? BIT(15) : 0;\n\tr[13] |= pr->cond_not ? BIT(14) : 0;\n\tr[13] |= pr->cond_and1 ? BIT(13) : 0;\n\tr[13] |= pr->cond_and2 ? BIT(12) : 0;\n}\n\nstatic void rtl839x_write_pie_action(u32 r[],  struct pie_rule *pr)\n{\n\tif (pr->drop) {\n\t\tr[13] |= 0x9;\t// Set ACT_MASK_FWD & FWD_ACT = DROP\n\t\tr[13] |= BIT(3);\n\t} else {\n\t\tr[13] |= pr->fwd_sel ? BIT(3) : 0;\n\t\tr[13] |= pr->fwd_act;\n\t}\n\tr[13] |= pr->bypass_sel ? BIT(11) : 0;\n\tr[13] |= pr->mpls_sel ? BIT(10) : 0;\n\tr[13] |= pr->nopri_sel ? BIT(9) : 0;\n\tr[13] |= pr->ovid_sel ? BIT(8) : 0;\n\tr[13] |= pr->ivid_sel ? BIT(7) : 0;\n\tr[13] |= pr->meter_sel ? BIT(6) : 0;\n\tr[13] |= pr->mir_sel ? BIT(5) : 0;\n\tr[13] |= pr->log_sel ? BIT(4) : 0;\n\n\tr[14] |= ((u32)(pr->fwd_data & 0x3fff)) << 18;\n\tr[14] |= pr->log_octets ? BIT(17) : 0;\n\tr[14] |= ((u32)(pr->log_data & 0x7ff)) << 4;\n\tr[14] |= (pr->mir_data & 0x3) << 3;\n\tr[14] |= ((u32)(pr->meter_data >> 7)) & 0x7;\n\tr[15] |= (u32)(pr->meter_data) << 26;\n\tr[15] |= ((u32)(pr->ivid_act) << 23) & 0x3;\n\tr[15] |= ((u32)(pr->ivid_data) << 9) & 0xfff;\n\tr[15] |= ((u32)(pr->ovid_act) << 6) & 0x3;\n\tr[15] |= ((u32)(pr->ovid_data) >> 4) & 0xff;\n\tr[16] |= ((u32)(pr->ovid_data) & 0xf) << 28;\n\tr[16] |= ((u32)(pr->nopri_data) & 0x7) << 20;\n\tr[16] |= ((u32)(pr->mpls_act) & 0x7) << 20;\n\tr[16] |= ((u32)(pr->mpls_lib_idx) & 0x7) << 20;\n\tr[16] |= pr->bypass_all ? BIT(9) : 0;\n\tr[16] |= pr->bypass_igr_stp ? BIT(8) : 0;\n\tr[16] |= pr->bypass_ibc_sc ? BIT(7) : 0;\n}\n\nstatic void rtl839x_read_pie_action(u32 r[],  struct pie_rule *pr)\n{\n\tif (r[13] & BIT(3)) { // ACT_MASK_FWD set, is it a drop?\n\t\tif ((r[14] & 0x7) == 1) {\n\t\t\tpr->drop = true;\n\t\t} else {\n\t\t\tpr->fwd_sel = true;\n\t\t\tpr->fwd_act = r[14] & 0x7;\n\t\t}\n\t}\n\n\tpr->bypass_sel = r[13] & BIT(11);\n\tpr->mpls_sel = r[13] & BIT(10);\n\tpr->nopri_sel = r[13] & BIT(9);\n\tpr->ovid_sel = r[13] & BIT(8);\n\tpr->ivid_sel = r[13] & BIT(7);\n\tpr->meter_sel = r[13] & BIT(6);\n\tpr->mir_sel = r[13] & BIT(5);\n\tpr->log_sel = r[13] & BIT(4);\n\n\t// TODO: Read in data fields\n\n\tpr->bypass_all = r[16] & BIT(9);\n\tpr->bypass_igr_stp = r[16] & BIT(8);\n\tpr->bypass_ibc_sc = r[16] & BIT(7);\n}\n\nvoid rtl839x_pie_rule_dump_raw(u32 r[])\n{\n\tpr_info(\"Raw IACL table entry:\\n\");\n\tpr_info(\"Match  : %08x %08x %08x %08x %08x %08x\\n\", r[0], r[1], r[2], r[3], r[4], r[5]);\n\tpr_info(\"Fixed  : %06x\\n\", r[6] >> 8);\n\tpr_info(\"Match M: %08x %08x %08x %08x %08x %08x\\n\",\n\t\t(r[6] << 24) | (r[7] >> 8), (r[7] << 24) | (r[8] >> 8), (r[8] << 24) | (r[9] >> 8),\n\t\t(r[9] << 24) | (r[10] >> 8), (r[10] << 24) | (r[11] >> 8),\n\t\t(r[11] << 24) | (r[12] >> 8));\n\tpr_info(\"R[13]:   %08x\\n\", r[13]);\n\tpr_info(\"Fixed M: %06x\\n\", ((r[12] << 16) | (r[13] >> 16)) & 0xffffff);\n\tpr_info(\"Valid / not / and1 / and2 : %1x\\n\", (r[13] >> 12) & 0xf);\n\tpr_info(\"r 13-16: %08x %08x %08x %08x\\n\", r[13], r[14], r[15], r[16]);\n}\n\nvoid rtl839x_pie_rule_dump(struct  pie_rule *pr)\n{\n\tpr_info(\"Drop: %d, fwd: %d, ovid: %d, ivid: %d, flt: %d, log: %d, rmk: %d, meter: %d tagst: %d, mir: %d, nopri: %d, cpupri: %d, otpid: %d, itpid: %d, shape: %d\\n\",\n\t\tpr->drop, pr->fwd_sel, pr->ovid_sel, pr->ivid_sel, pr->flt_sel, pr->log_sel, pr->rmk_sel, pr->log_sel, pr->tagst_sel, pr->mir_sel, pr->nopri_sel,\n\t\tpr->cpupri_sel, pr->otpid_sel, pr->itpid_sel, pr->shaper_sel);\n\tif (pr->fwd_sel)\n\t\tpr_info(\"FWD: %08x\\n\", pr->fwd_data);\n\tpr_info(\"TID: %x, %x\\n\", pr->tid, pr->tid_m);\n}\n\nstatic int rtl839x_pie_rule_read(struct rtl838x_switch_priv *priv, int idx, struct  pie_rule *pr)\n{\n\t// Read IACL table (2) via register 0\n\tstruct table_reg *q = rtl_table_get(RTL8380_TBL_0, 2);\n\tu32 r[17];\n\tint i;\n\tint block = idx / PIE_BLOCK_SIZE;\n\tu32 t_select = sw_r32(RTL839X_ACL_BLK_TMPLTE_CTRL(block));\n\n\tmemset(pr, 0, sizeof(*pr));\n\trtl_table_read(q, idx);\n\tfor (i = 0; i < 17; i++)\n\t\tr[i] = sw_r32(rtl_table_data(q, i));\n\n\trtl_table_release(q);\n\n\trtl839x_read_pie_fixed_fields(r, pr);\n\tif (!pr->valid)\n\t\treturn 0;\n\n\tpr_debug(\"%s: template_selectors %08x, tid: %d\\n\", __func__, t_select, pr->tid);\n\trtl839x_pie_rule_dump_raw(r);\n\n\trtl839x_read_pie_templated(r, pr, fixed_templates[(t_select >> (pr->tid * 3)) & 0x7]);\n\n\trtl839x_read_pie_action(r, pr);\n\n\treturn 0;\n}\n\nstatic int rtl839x_pie_rule_write(struct rtl838x_switch_priv *priv, int idx, struct pie_rule *pr)\n{\n\t// Access IACL table (2) via register 0\n\tstruct table_reg *q = rtl_table_get(RTL8390_TBL_0, 2);\n\tu32 r[17];\n\tint i;\n\tint block = idx / PIE_BLOCK_SIZE;\n\tu32 t_select = sw_r32(RTL839X_ACL_BLK_TMPLTE_CTRL(block));\n\n\tpr_debug(\"%s: %d, t_select: %08x\\n\", __func__, idx, t_select);\n\n\tfor (i = 0; i < 17; i++)\n\t\tr[i] = 0;\n\n\tif (!pr->valid) {\n\t\trtl_table_write(q, idx);\n\t\trtl_table_release(q);\n\t\treturn 0;\n\t}\n\trtl839x_write_pie_fixed_fields(r, pr);\n\n\tpr_debug(\"%s: template %d\\n\", __func__, (t_select >> (pr->tid * 3)) & 0x7);\n\trtl839x_write_pie_templated(r, pr, fixed_templates[(t_select >> (pr->tid * 3)) & 0x7]);\n\n\trtl839x_write_pie_action(r, pr);\n\n//\trtl839x_pie_rule_dump_raw(r);\n\n\tfor (i = 0; i < 17; i++)\n\t\tsw_w32(r[i], rtl_table_data(q, i));\n\n\trtl_table_write(q, idx);\n\trtl_table_release(q);\n\n\treturn 0;\n}\n\nstatic bool rtl839x_pie_templ_has(int t, enum template_field_id field_type)\n{\n\tint i;\n\tenum template_field_id ft;\n\n\tfor (i = 0; i < N_FIXED_FIELDS; i++) {\n\t\tft = fixed_templates[t][i];\n\t\tif (field_type == ft)\n\t\t\treturn true;\n\t}\n\n\treturn false;\n}\n\nstatic int rtl839x_pie_verify_template(struct rtl838x_switch_priv *priv,\n\t\t\t\t       struct pie_rule *pr, int t, int block)\n{\n\tint i;\n\n\tif (!pr->is_ipv6 && pr->sip_m && !rtl839x_pie_templ_has(t, TEMPLATE_FIELD_SIP0))\n\t\treturn -1;\n\n\tif (!pr->is_ipv6 && pr->dip_m && !rtl839x_pie_templ_has(t, TEMPLATE_FIELD_DIP0))\n\t\treturn -1;\n\n\tif (pr->is_ipv6) {\n\t\tif ((pr->sip6_m.s6_addr32[0] || pr->sip6_m.s6_addr32[1]\n\t\t\t|| pr->sip6_m.s6_addr32[2] || pr->sip6_m.s6_addr32[3])\n\t\t\t&& !rtl839x_pie_templ_has(t, TEMPLATE_FIELD_SIP2))\n\t\t\treturn -1;\n\t\tif ((pr->dip6_m.s6_addr32[0] || pr->dip6_m.s6_addr32[1]\n\t\t\t|| pr->dip6_m.s6_addr32[2] || pr->dip6_m.s6_addr32[3])\n\t\t\t&& !rtl839x_pie_templ_has(t, TEMPLATE_FIELD_DIP2))\n\t\t\treturn -1;\n\t}\n\n\tif (ether_addr_to_u64(pr->smac) && !rtl839x_pie_templ_has(t, TEMPLATE_FIELD_SMAC0))\n\t\treturn -1;\n\n\tif (ether_addr_to_u64(pr->dmac) && !rtl839x_pie_templ_has(t, TEMPLATE_FIELD_DMAC0))\n\t\treturn -1;\n\n\t// TODO: Check more\n\n\ti = find_first_zero_bit(&priv->pie_use_bm[block * 4], PIE_BLOCK_SIZE);\n\n\tif (i >= PIE_BLOCK_SIZE)\n\t\treturn -1;\n\n\treturn i + PIE_BLOCK_SIZE * block;\n}\n\nstatic int rtl839x_pie_rule_add(struct rtl838x_switch_priv *priv, struct pie_rule *pr)\n{\n\tint idx, block, j, t;\n\tint min_block = 0;\n\tint max_block = priv->n_pie_blocks / 2;\n\n\tif (pr->is_egress) {\n\t\tmin_block = max_block;\n\t\tmax_block = priv->n_pie_blocks;\n\t}\n\n\tmutex_lock(&priv->pie_mutex);\n\n\tfor (block = min_block; block < max_block; block++) {\n\t\tfor (j = 0; j < 2; j++) {\n\t\t\tt = (sw_r32(RTL839X_ACL_BLK_TMPLTE_CTRL(block)) >> (j * 3)) & 0x7;\n\t\t\tidx = rtl839x_pie_verify_template(priv, pr, t, block);\n\t\t\tif (idx >= 0)\n\t\t\t\tbreak;\n\t\t}\n\t\tif (j < 2)\n\t\t\tbreak;\n\t}\n\n\tif (block >= priv->n_pie_blocks) {\n\t\tmutex_unlock(&priv->pie_mutex);\n\t\treturn -EOPNOTSUPP;\n\t}\n\n\tset_bit(idx, priv->pie_use_bm);\n\n\tpr->valid = true;\n\tpr->tid = j;  // Mapped to template number\n\tpr->tid_m = 0x3;\n\tpr->id = idx;\n\n\trtl839x_pie_lookup_enable(priv, idx);\n\trtl839x_pie_rule_write(priv, idx, pr);\n\n\tmutex_unlock(&priv->pie_mutex);\n\treturn 0;\n}\n\nstatic void rtl839x_pie_rule_rm(struct rtl838x_switch_priv *priv, struct pie_rule *pr)\n{\n\tint idx = pr->id;\n\n\trtl839x_pie_rule_del(priv, idx, idx);\n\tclear_bit(idx, priv->pie_use_bm);\n}\n\nstatic void rtl839x_pie_init(struct rtl838x_switch_priv *priv)\n{\n\tint i;\n\tu32 template_selectors;\n\n\tmutex_init(&priv->pie_mutex);\n\n\t// Power on all PIE blocks\n\tfor (i = 0; i < priv->n_pie_blocks; i++)\n\t\tsw_w32_mask(0, BIT(i), RTL839X_PS_ACL_PWR_CTRL);\n\n\t// Set ingress and egress ACL blocks to 50/50: first Egress block is 9\n\tsw_w32_mask(0x1f, 9, RTL839X_ACL_CTRL);  // Writes 9 to cutline field\n\n\t// Include IPG in metering\n\tsw_w32(1, RTL839X_METER_GLB_CTRL);\n\n\t// Delete all present rules\n\trtl839x_pie_rule_del(priv, 0, priv->n_pie_blocks * PIE_BLOCK_SIZE - 1);\n\n\t// Enable predefined templates 0, 1 for blocks 0-2\n\ttemplate_selectors = 0 | (1 << 3);\n\tfor (i = 0; i < 3; i++)\n\t\tsw_w32(template_selectors, RTL839X_ACL_BLK_TMPLTE_CTRL(i));\n\n\t// Enable predefined templates 2, 3 for blocks 3-5\n\ttemplate_selectors = 2 | (3 << 3);\n\tfor (i = 3; i < 6; i++)\n\t\tsw_w32(template_selectors, RTL839X_ACL_BLK_TMPLTE_CTRL(i));\n\n\t// Enable predefined templates 1, 4 for blocks 6-8\n\ttemplate_selectors = 2 | (3 << 3);\n\tfor (i = 6; i < 9; i++)\n\t\tsw_w32(template_selectors, RTL839X_ACL_BLK_TMPLTE_CTRL(i));\n\n\t// Enable predefined templates 0, 1 for blocks 9-11\n\ttemplate_selectors = 0 | (1 << 3);\n\tfor (i = 9; i < 12; i++)\n\t\tsw_w32(template_selectors, RTL839X_ACL_BLK_TMPLTE_CTRL(i));\n\n\t// Enable predefined templates 2, 3 for blocks 12-14\n\ttemplate_selectors = 2 | (3 << 3);\n\tfor (i = 12; i < 15; i++)\n\t\tsw_w32(template_selectors, RTL839X_ACL_BLK_TMPLTE_CTRL(i));\n\n\t// Enable predefined templates 1, 4 for blocks 15-17\n\ttemplate_selectors = 2 | (3 << 3);\n\tfor (i = 15; i < 18; i++)\n\t\tsw_w32(template_selectors, RTL839X_ACL_BLK_TMPLTE_CTRL(i));\n}\n\nstatic u32 rtl839x_packet_cntr_read(int counter)\n{\n\tu32 v;\n\n\t// Read LOG table (4) via register RTL8390_TBL_0\n\tstruct table_reg *r = rtl_table_get(RTL8390_TBL_0, 4);\n\n\tpr_debug(\"In %s, id %d\\n\", __func__, counter);\n\trtl_table_read(r, counter / 2);\n\n\t// The table has a size of 2 registers\n\tif (counter % 2)\n\t\tv = sw_r32(rtl_table_data(r, 0));\n\telse\n\t\tv = sw_r32(rtl_table_data(r, 1));\n\n\trtl_table_release(r);\n\n\treturn v;\n}\n\nstatic void rtl839x_packet_cntr_clear(int counter)\n{\n\t// Access LOG table (4) via register RTL8390_TBL_0\n\tstruct table_reg *r = rtl_table_get(RTL8390_TBL_0, 4);\n\n\tpr_debug(\"In %s, id %d\\n\", __func__, counter);\n\t// The table has a size of 2 registers\n\tif (counter % 2)\n\t\tsw_w32(0, rtl_table_data(r, 0));\n\telse\n\t\tsw_w32(0, rtl_table_data(r, 1));\n\n\trtl_table_write(r, counter / 2);\n\n\trtl_table_release(r);\n}\n\nstatic void rtl839x_route_read(int idx, struct rtl83xx_route *rt)\n{\n\tu64 v;\n\t// Read ROUTING table (2) via register RTL8390_TBL_1\n\tstruct table_reg *r = rtl_table_get(RTL8390_TBL_1, 2);\n\n\tpr_debug(\"In %s\\n\", __func__);\n\trtl_table_read(r, idx);\n\n\t// The table has a size of 2 registers\n\tv = sw_r32(rtl_table_data(r, 0));\n\tv <<= 32;\n\tv |= sw_r32(rtl_table_data(r, 1));\n\trt->switch_mac_id = (v >> 12) & 0xf;\n\trt->nh.gw = v >> 16;\n\n\trtl_table_release(r);\n}\n\nstatic void rtl839x_route_write(int idx, struct rtl83xx_route *rt)\n{\n\tu32 v;\n\n\t// Read ROUTING table (2) via register RTL8390_TBL_1\n\tstruct table_reg *r = rtl_table_get(RTL8390_TBL_1, 2);\n\n\tpr_debug(\"In %s\\n\", __func__);\n\tsw_w32(rt->nh.gw >> 16, rtl_table_data(r, 0));\n\tv = rt->nh.gw << 16;\n\tv |= rt->switch_mac_id << 12;\n\tsw_w32(v, rtl_table_data(r, 1));\n\trtl_table_write(r, idx);\n\n\trtl_table_release(r);\n}\n\n/*\n * Configure the switch's own MAC addresses used when routing packets\n */\nstatic void rtl839x_setup_port_macs(struct rtl838x_switch_priv *priv)\n{\n\tint i;\n\tstruct net_device *dev;\n\tu64 mac;\n\n\tpr_debug(\"%s: got port %08x\\n\", __func__, (u32)priv->ports[priv->cpu_port].dp);\n\tdev = priv->ports[priv->cpu_port].dp->slave;\n\tmac = ether_addr_to_u64(dev->dev_addr);\n\n\tfor (i = 0; i < 15; i++) {\n\t\tmac++;  // BUG: VRRP for testing\n\t\tsw_w32(mac >> 32, RTL839X_ROUTING_SA_CTRL + i * 8);\n\t\tsw_w32(mac, RTL839X_ROUTING_SA_CTRL + i * 8 + 4);\n\t}\n}\n\nint rtl839x_l3_setup(struct rtl838x_switch_priv *priv)\n{\n\trtl839x_setup_port_macs(priv);\n\n\treturn 0;\n}\n\nvoid rtl839x_vlan_port_pvidmode_set(int port, enum pbvlan_type type, enum pbvlan_mode mode)\n{\n\tif (type == PBVLAN_TYPE_INNER)\n\t\tsw_w32_mask(0x3, mode, RTL839X_VLAN_PORT_PB_VLAN + (port << 2));\n\telse\n\t\tsw_w32_mask(0x3 << 14, mode << 14, RTL839X_VLAN_PORT_PB_VLAN + (port << 2));\n}\n\nvoid rtl839x_vlan_port_pvid_set(int port, enum pbvlan_type type, int pvid)\n{\n\tif (type == PBVLAN_TYPE_INNER)\n\t\tsw_w32_mask(0xfff << 2, pvid << 2, RTL839X_VLAN_PORT_PB_VLAN + (port << 2));\n\telse\n\t\tsw_w32_mask(0xfff << 16, pvid << 16, RTL839X_VLAN_PORT_PB_VLAN + (port << 2));\n}\n\nstatic int rtl839x_set_ageing_time(unsigned long msec)\n{\n\tint t = sw_r32(RTL839X_L2_CTRL_1);\n\n\tt &= 0x1FFFFF;\n\tt = t * 3 / 5; /* Aging time in seconds. 0: L2 aging disabled */\n\tpr_debug(\"L2 AGING time: %d sec\\n\", t);\n\n\tt = (msec * 5 + 2000) / 3000;\n\tt = t > 0x1FFFFF ? 0x1FFFFF : t;\n\tsw_w32_mask(0x1FFFFF, t, RTL839X_L2_CTRL_1);\n\tpr_debug(\"Dynamic aging for ports: %x\\n\", sw_r32(RTL839X_L2_PORT_AGING_OUT));\n\n\treturn 0;\n}\n\nstatic void rtl839x_set_igr_filter(int port,  enum igr_filter state)\n{\n\tsw_w32_mask(0x3 << ((port & 0xf)<<1), state << ((port & 0xf)<<1),\n\t\t    RTL839X_VLAN_PORT_IGR_FLTR + (((port >> 4) << 2)));\n}\n\nstatic void rtl839x_set_egr_filter(int port,  enum egr_filter state)\n{\n\tsw_w32_mask(0x1 << (port % 0x20), state << (port % 0x20),\n\t\t\tRTL839X_VLAN_PORT_EGR_FLTR + (((port >> 5) << 2)));\n}\n\nvoid rtl839x_set_distribution_algorithm(int group, int algoidx, u32 algomsk)\n{\n\tsw_w32_mask(3 << ((group & 0xf) << 1), algoidx << ((group & 0xf) << 1),\n\t\t    RTL839X_TRK_HASH_IDX_CTRL + ((group >> 4) << 2));\n\tsw_w32(algomsk, RTL839X_TRK_HASH_CTRL + (algoidx << 2));\n}\n\nvoid rtl839x_set_receive_management_action(int port, rma_ctrl_t type, action_type_t action)\n{\n\tswitch(type) {\n\tcase BPDU:\n\t\tsw_w32_mask(3 << ((port & 0xf) << 1), (action & 0x3) << ((port & 0xf) << 1),\n\t\t\t    RTL839X_RMA_BPDU_CTRL + ((port >> 4) << 2));\n\tbreak;\n\tcase PTP:\n\t\tsw_w32_mask(3 << ((port & 0xf) << 1), (action & 0x3) << ((port & 0xf) << 1),\n\t\t\t    RTL839X_RMA_PTP_CTRL + ((port >> 4) << 2));\n\tbreak;\n\tcase LLTP:\n\t\tsw_w32_mask(3 << ((port & 0xf) << 1), (action & 0x3) << ((port & 0xf) << 1),\n\t\t\t    RTL839X_RMA_LLTP_CTRL + ((port >> 4) << 2));\n\tbreak;\n\tdefault:\n\tbreak;\n\t}\n}\n\nconst struct rtl838x_reg rtl839x_reg = {\n\t.mask_port_reg_be = rtl839x_mask_port_reg_be,\n\t.set_port_reg_be = rtl839x_set_port_reg_be,\n\t.get_port_reg_be = rtl839x_get_port_reg_be,\n\t.mask_port_reg_le = rtl839x_mask_port_reg_le,\n\t.set_port_reg_le = rtl839x_set_port_reg_le,\n\t.get_port_reg_le = rtl839x_get_port_reg_le,\n\t.stat_port_rst = RTL839X_STAT_PORT_RST,\n\t.stat_rst = RTL839X_STAT_RST,\n\t.stat_port_std_mib = RTL839X_STAT_PORT_STD_MIB,\n\t.traffic_enable = rtl839x_traffic_enable,\n\t.traffic_disable = rtl839x_traffic_disable,\n\t.traffic_get = rtl839x_traffic_get,\n\t.traffic_set = rtl839x_traffic_set,\n\t.port_iso_ctrl = rtl839x_port_iso_ctrl,\n\t.l2_ctrl_0 = RTL839X_L2_CTRL_0,\n\t.l2_ctrl_1 = RTL839X_L2_CTRL_1,\n\t.l2_port_aging_out = RTL839X_L2_PORT_AGING_OUT,\n\t.set_ageing_time = rtl839x_set_ageing_time,\n\t.smi_poll_ctrl = RTL839X_SMI_PORT_POLLING_CTRL,\n\t.l2_tbl_flush_ctrl = RTL839X_L2_TBL_FLUSH_CTRL,\n\t.exec_tbl0_cmd = rtl839x_exec_tbl0_cmd,\n\t.exec_tbl1_cmd = rtl839x_exec_tbl1_cmd,\n\t.tbl_access_data_0 = rtl839x_tbl_access_data_0,\n\t.isr_glb_src = RTL839X_ISR_GLB_SRC,\n\t.isr_port_link_sts_chg = RTL839X_ISR_PORT_LINK_STS_CHG,\n\t.imr_port_link_sts_chg = RTL839X_IMR_PORT_LINK_STS_CHG,\n\t.imr_glb = RTL839X_IMR_GLB,\n\t.vlan_tables_read = rtl839x_vlan_tables_read,\n\t.vlan_set_tagged = rtl839x_vlan_set_tagged,\n\t.vlan_set_untagged = rtl839x_vlan_set_untagged,\n\t.vlan_profile_dump = rtl839x_vlan_profile_dump,\n\t.vlan_profile_setup = rtl839x_vlan_profile_setup,\n\t.vlan_fwd_on_inner = rtl839x_vlan_fwd_on_inner,\n\t.vlan_port_pvidmode_set = rtl839x_vlan_port_pvidmode_set,\n\t.vlan_port_pvid_set = rtl839x_vlan_port_pvid_set,\n\t.set_vlan_igr_filter = rtl839x_set_igr_filter,\n\t.set_vlan_egr_filter = rtl839x_set_egr_filter,\n\t.enable_learning = rtl839x_enable_learning,\n\t.enable_flood = rtl839x_enable_flood,\n\t.enable_mcast_flood = rtl839x_enable_mcast_flood,\n\t.enable_bcast_flood = rtl839x_enable_bcast_flood,\n\t.stp_get = rtl839x_stp_get,\n\t.stp_set = rtl839x_stp_set,\n\t.mac_force_mode_ctrl = rtl839x_mac_force_mode_ctrl,\n\t.mac_port_ctrl = rtl839x_mac_port_ctrl,\n\t.l2_port_new_salrn = rtl839x_l2_port_new_salrn,\n\t.l2_port_new_sa_fwd = rtl839x_l2_port_new_sa_fwd,\n\t.mir_ctrl = RTL839X_MIR_CTRL,\n\t.mir_dpm = RTL839X_MIR_DPM_CTRL,\n\t.mir_spm = RTL839X_MIR_SPM_CTRL,\n\t.mac_link_sts = RTL839X_MAC_LINK_STS,\n\t.mac_link_dup_sts = RTL839X_MAC_LINK_DUP_STS,\n\t.mac_link_spd_sts = rtl839x_mac_link_spd_sts,\n\t.mac_rx_pause_sts = RTL839X_MAC_RX_PAUSE_STS,\n\t.mac_tx_pause_sts = RTL839X_MAC_TX_PAUSE_STS,\n\t.read_l2_entry_using_hash = rtl839x_read_l2_entry_using_hash,\n\t.write_l2_entry_using_hash = rtl839x_write_l2_entry_using_hash,\n\t.read_cam = rtl839x_read_cam,\n\t.write_cam = rtl839x_write_cam,\n\t.vlan_port_tag_sts_ctrl = RTL839X_VLAN_PORT_TAG_STS_CTRL,\n\t.trk_mbr_ctr = rtl839x_trk_mbr_ctr,\n\t.rma_bpdu_fld_pmask = RTL839X_RMA_BPDU_FLD_PMSK,\n\t.spcl_trap_eapol_ctrl = RTL839X_SPCL_TRAP_EAPOL_CTRL,\n\t.init_eee = rtl839x_init_eee,\n\t.port_eee_set = rtl839x_port_eee_set,\n\t.eee_port_ability = rtl839x_eee_port_ability,\n\t.l2_hash_seed = rtl839x_l2_hash_seed, \n\t.l2_hash_key = rtl839x_l2_hash_key,\n\t.read_mcast_pmask = rtl839x_read_mcast_pmask,\n\t.write_mcast_pmask = rtl839x_write_mcast_pmask,\n\t.pie_init = rtl839x_pie_init,\n\t.pie_rule_read = rtl839x_pie_rule_read,\n\t.pie_rule_write = rtl839x_pie_rule_write,\n\t.pie_rule_add = rtl839x_pie_rule_add,\n\t.pie_rule_rm = rtl839x_pie_rule_rm,\n\t.l2_learning_setup = rtl839x_l2_learning_setup,\n\t.packet_cntr_read = rtl839x_packet_cntr_read,\n\t.packet_cntr_clear = rtl839x_packet_cntr_clear,\n\t.route_read = rtl839x_route_read,\n\t.route_write = rtl839x_route_write,\n\t.l3_setup = rtl839x_l3_setup,\n\t.set_distribution_algorithm = rtl839x_set_distribution_algorithm,\n\t.set_receive_management_action = rtl839x_set_receive_management_action,\n};\n"
  },
  {
    "path": "target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/rtl83xx.h",
    "content": "/* SPDX-License-Identifier: GPL-2.0-only */\n\n#ifndef _NET_DSA_RTL83XX_H\n#define _NET_DSA_RTL83XX_H\n\n#include <net/dsa.h>\n#include \"rtl838x.h\"\n\n\n#define RTL8380_VERSION_A 'A'\n#define RTL8390_VERSION_A 'A'\n#define RTL8380_VERSION_B 'B'\n\nstruct fdb_update_work {\n\tstruct work_struct work;\n\tstruct net_device *ndev;\n\tu64 macs[];\n};\n\n#define MIB_DESC(_size, _offset, _name) {.size = _size, .offset = _offset, .name = _name}\nstruct rtl83xx_mib_desc {\n\tunsigned int size;\n\tunsigned int offset;\n\tconst char *name;\n};\n\n/* API for switch table access */\nstruct table_reg {\n\tu16 addr;\n\tu16 data;\n\tu8  max_data;\n\tu8 c_bit;\n\tu8 t_bit;\n\tu8 rmode;\n\tu8 tbl;\n\tstruct mutex lock;\n};\n\n#define TBL_DESC(_addr, _data, _max_data, _c_bit, _t_bit, _rmode) \\\n\t\t{  .addr = _addr, .data = _data, .max_data = _max_data, .c_bit = _c_bit, \\\n\t\t    .t_bit = _t_bit, .rmode = _rmode \\\n\t\t}\n\ntypedef enum {\n\tRTL8380_TBL_L2 = 0,\n\tRTL8380_TBL_0,\n\tRTL8380_TBL_1,\n\tRTL8390_TBL_L2,\n\tRTL8390_TBL_0,\n\tRTL8390_TBL_1,\n\tRTL8390_TBL_2,\n\tRTL9300_TBL_L2,\n\tRTL9300_TBL_0,\n\tRTL9300_TBL_1,\n\tRTL9300_TBL_2,\n\tRTL9300_TBL_HSB,\n\tRTL9300_TBL_HSA,\n\tRTL9310_TBL_0,\n\tRTL9310_TBL_1,\n\tRTL9310_TBL_2,\n\tRTL9310_TBL_3,\n\tRTL9310_TBL_4,\n\tRTL9310_TBL_5,\n\tRTL_TBL_END\n} rtl838x_tbl_reg_t;\n\nvoid rtl_table_init(void);\nstruct table_reg *rtl_table_get(rtl838x_tbl_reg_t r, int t);\nvoid rtl_table_release(struct table_reg *r);\nvoid rtl_table_read(struct table_reg *r, int idx);\nvoid rtl_table_write(struct table_reg *r, int idx);\ninline u16 rtl_table_data(struct table_reg *r, int i);\ninline u32 rtl_table_data_r(struct table_reg *r, int i);\ninline void rtl_table_data_w(struct table_reg *r, u32 v, int i);\n\nvoid __init rtl83xx_setup_qos(struct rtl838x_switch_priv *priv);\n\nint rtl83xx_packet_cntr_alloc(struct rtl838x_switch_priv *priv);\n\nint rtl83xx_port_is_under(const struct net_device * dev, struct rtl838x_switch_priv *priv);\n\nint read_phy(u32 port, u32 page, u32 reg, u32 *val);\nint write_phy(u32 port, u32 page, u32 reg, u32 val);\n\n/* Port register accessor functions for the RTL839x and RTL931X SoCs */\nvoid rtl839x_mask_port_reg_be(u64 clear, u64 set, int reg);\nu64 rtl839x_get_port_reg_be(int reg);\nvoid rtl839x_set_port_reg_be(u64 set, int reg);\nvoid rtl839x_mask_port_reg_le(u64 clear, u64 set, int reg);\nvoid rtl839x_set_port_reg_le(u64 set, int reg);\nu64 rtl839x_get_port_reg_le(int reg);\n\n/* Port register accessor functions for the RTL838x and RTL930X SoCs */\nvoid rtl838x_mask_port_reg(u64 clear, u64 set, int reg);\nvoid rtl838x_set_port_reg(u64 set, int reg);\nu64 rtl838x_get_port_reg(int reg);\n\n/* RTL838x-specific */\nu32 rtl838x_hash(struct rtl838x_switch_priv *priv, u64 seed);\nirqreturn_t rtl838x_switch_irq(int irq, void *dev_id);\nvoid rtl8380_get_version(struct rtl838x_switch_priv *priv);\nvoid rtl838x_vlan_profile_dump(int index);\nint rtl83xx_dsa_phy_read(struct dsa_switch *ds, int phy_addr, int phy_reg);\nvoid rtl8380_sds_rst(int mac);\nint rtl8380_sds_power(int mac, int val);\nvoid rtl838x_print_matrix(void);\n\n/* RTL839x-specific */\nu32 rtl839x_hash(struct rtl838x_switch_priv *priv, u64 seed);\nirqreturn_t rtl839x_switch_irq(int irq, void *dev_id);\nvoid rtl8390_get_version(struct rtl838x_switch_priv *priv);\nvoid rtl839x_vlan_profile_dump(int index);\nint rtl83xx_dsa_phy_write(struct dsa_switch *ds, int phy_addr, int phy_reg, u16 val);\nvoid rtl839x_exec_tbl2_cmd(u32 cmd);\nvoid rtl839x_print_matrix(void);\n\n/* RTL930x-specific */\nu32 rtl930x_hash(struct rtl838x_switch_priv *priv, u64 seed);\nirqreturn_t rtl930x_switch_irq(int irq, void *dev_id);\nirqreturn_t rtl839x_switch_irq(int irq, void *dev_id);\nvoid rtl930x_vlan_profile_dump(int index);\nint rtl9300_sds_power(int mac, int val);\nvoid rtl9300_sds_rst(int sds_num, u32 mode);\nint rtl9300_serdes_setup(int sds_num, phy_interface_t phy_mode);\nvoid rtl930x_print_matrix(void);\n\n/* RTL931x-specific */\nirqreturn_t rtl931x_switch_irq(int irq, void *dev_id);\nint rtl931x_sds_cmu_band_get(int sds, phy_interface_t mode);\nint rtl931x_sds_cmu_band_set(int sds, bool enable, u32 band, phy_interface_t mode);\nvoid rtl931x_sds_init(u32 sds, phy_interface_t mode);\n\nint rtl83xx_lag_add(struct dsa_switch *ds, int group, int port, struct netdev_lag_upper_info *info);\nint rtl83xx_lag_del(struct dsa_switch *ds, int group, int port);\n\n#endif /* _NET_DSA_RTL83XX_H */\n\n"
  },
  {
    "path": "target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/rtl930x.c",
    "content": "// SPDX-License-Identifier: GPL-2.0-only\n\n#include <asm/mach-rtl838x/mach-rtl83xx.h>\n#include <linux/inetdevice.h>\n\n#include \"rtl83xx.h\"\n\nextern struct mutex smi_lock;\nextern struct rtl83xx_soc_info soc_info;\n\n/* Definition of the RTL930X-specific template field IDs as used in the PIE */\nenum template_field_id {\n\tTEMPLATE_FIELD_SPM0 = 0,\t\t// Source portmask ports 0-15\n\tTEMPLATE_FIELD_SPM1 = 1,\t\t// Source portmask ports 16-31\n\tTEMPLATE_FIELD_DMAC0 = 2,\t\t// Destination MAC [15:0]\n\tTEMPLATE_FIELD_DMAC1 = 3,\t\t// Destination MAC [31:16]\n\tTEMPLATE_FIELD_DMAC2 = 4,\t\t// Destination MAC [47:32]\n\tTEMPLATE_FIELD_SMAC0 = 5,\t\t// Source MAC [15:0]\n\tTEMPLATE_FIELD_SMAC1 = 6,\t\t// Source MAC [31:16]\n\tTEMPLATE_FIELD_SMAC2 = 7,\t\t// Source MAC [47:32]\n\tTEMPLATE_FIELD_ETHERTYPE = 8,\t\t// Ethernet frame type field\n\tTEMPLATE_FIELD_OTAG = 9,\n\tTEMPLATE_FIELD_ITAG = 10,\n\tTEMPLATE_FIELD_SIP0 = 11,\n\tTEMPLATE_FIELD_SIP1 = 12,\n\tTEMPLATE_FIELD_DIP0 = 13,\n\tTEMPLATE_FIELD_DIP1 = 14,\n\tTEMPLATE_FIELD_IP_TOS_PROTO = 15,\n\tTEMPLATE_FIELD_L4_SPORT = 16,\n\tTEMPLATE_FIELD_L4_DPORT = 17,\n\tTEMPLATE_FIELD_L34_HEADER = 18,\n\tTEMPLATE_FIELD_TCP_INFO = 19,\n\tTEMPLATE_FIELD_FIELD_SELECTOR_VALID = 20,\n\tTEMPLATE_FIELD_FIELD_SELECTOR_0 = 21,\n\tTEMPLATE_FIELD_FIELD_SELECTOR_1 = 22,\n\tTEMPLATE_FIELD_FIELD_SELECTOR_2 = 23,\n\tTEMPLATE_FIELD_FIELD_SELECTOR_3 = 24,\n\tTEMPLATE_FIELD_FIELD_SELECTOR_4 = 25,\n\tTEMPLATE_FIELD_FIELD_SELECTOR_5 = 26,\n\tTEMPLATE_FIELD_SIP2 = 27,\n\tTEMPLATE_FIELD_SIP3 = 28,\n\tTEMPLATE_FIELD_SIP4 = 29,\n\tTEMPLATE_FIELD_SIP5 = 30,\n\tTEMPLATE_FIELD_SIP6 = 31,\n\tTEMPLATE_FIELD_SIP7 = 32,\n\tTEMPLATE_FIELD_DIP2 = 33,\n\tTEMPLATE_FIELD_DIP3 = 34,\n\tTEMPLATE_FIELD_DIP4 = 35,\n\tTEMPLATE_FIELD_DIP5 = 36,\n\tTEMPLATE_FIELD_DIP6 = 37,\n\tTEMPLATE_FIELD_DIP7 = 38,\n\tTEMPLATE_FIELD_PKT_INFO = 39,\n\tTEMPLATE_FIELD_FLOW_LABEL = 40,\n\tTEMPLATE_FIELD_DSAP_SSAP = 41,\n\tTEMPLATE_FIELD_SNAP_OUI = 42,\n\tTEMPLATE_FIELD_FWD_VID = 43,\n\tTEMPLATE_FIELD_RANGE_CHK = 44,\n\tTEMPLATE_FIELD_VLAN_GMSK = 45,\t\t// VLAN Group Mask/IP range check\n\tTEMPLATE_FIELD_DLP = 46,\n\tTEMPLATE_FIELD_META_DATA = 47,\n\tTEMPLATE_FIELD_SRC_FWD_VID = 48,\n\tTEMPLATE_FIELD_SLP = 49,\n};\n\n/* The meaning of TEMPLATE_FIELD_VLAN depends on phase and the configuration in\n * RTL930X_PIE_CTRL. We use always the same definition and map to the inner VLAN tag:\n */\n#define TEMPLATE_FIELD_VLAN TEMPLATE_FIELD_ITAG\n\n// Number of fixed templates predefined in the RTL9300 SoC\n#define N_FIXED_TEMPLATES 5\n// RTL9300 specific predefined templates\nstatic enum template_field_id fixed_templates[N_FIXED_TEMPLATES][N_FIXED_FIELDS] =\n{\n\t{\n\t  TEMPLATE_FIELD_DMAC0, TEMPLATE_FIELD_DMAC1, TEMPLATE_FIELD_DMAC2,\n\t  TEMPLATE_FIELD_SMAC0, TEMPLATE_FIELD_SMAC1, TEMPLATE_FIELD_SMAC2,\n\t  TEMPLATE_FIELD_VLAN, TEMPLATE_FIELD_IP_TOS_PROTO, TEMPLATE_FIELD_DSAP_SSAP,\n\t  TEMPLATE_FIELD_ETHERTYPE, TEMPLATE_FIELD_SPM0, TEMPLATE_FIELD_SPM1\n\t}, {\n\t  TEMPLATE_FIELD_SIP0, TEMPLATE_FIELD_SIP1, TEMPLATE_FIELD_DIP0,\n\t  TEMPLATE_FIELD_DIP1, TEMPLATE_FIELD_IP_TOS_PROTO, TEMPLATE_FIELD_TCP_INFO,\n\t  TEMPLATE_FIELD_L4_SPORT, TEMPLATE_FIELD_L4_DPORT, TEMPLATE_FIELD_VLAN,\n\t  TEMPLATE_FIELD_RANGE_CHK, TEMPLATE_FIELD_SPM0, TEMPLATE_FIELD_SPM1\n\t}, {\n\t  TEMPLATE_FIELD_DMAC0, TEMPLATE_FIELD_DMAC1, TEMPLATE_FIELD_DMAC2,\n\t  TEMPLATE_FIELD_VLAN, TEMPLATE_FIELD_ETHERTYPE, TEMPLATE_FIELD_IP_TOS_PROTO,\n\t  TEMPLATE_FIELD_SIP0, TEMPLATE_FIELD_SIP1, TEMPLATE_FIELD_DIP0,\n\t  TEMPLATE_FIELD_DIP1, TEMPLATE_FIELD_L4_SPORT, TEMPLATE_FIELD_L4_DPORT\n\t}, {\n\t  TEMPLATE_FIELD_DIP0, TEMPLATE_FIELD_DIP1, TEMPLATE_FIELD_DIP2,\n\t  TEMPLATE_FIELD_DIP3, TEMPLATE_FIELD_DIP4, TEMPLATE_FIELD_DIP5,\n\t  TEMPLATE_FIELD_DIP6, TEMPLATE_FIELD_DIP7, TEMPLATE_FIELD_IP_TOS_PROTO,\n\t  TEMPLATE_FIELD_TCP_INFO, TEMPLATE_FIELD_L4_SPORT, TEMPLATE_FIELD_L4_DPORT\n\t}, {\n\t  TEMPLATE_FIELD_SIP0, TEMPLATE_FIELD_SIP1, TEMPLATE_FIELD_SIP2,\n\t  TEMPLATE_FIELD_SIP3, TEMPLATE_FIELD_SIP4, TEMPLATE_FIELD_SIP5,\n\t  TEMPLATE_FIELD_SIP6, TEMPLATE_FIELD_SIP7, TEMPLATE_FIELD_VLAN,\n\t  TEMPLATE_FIELD_RANGE_CHK, TEMPLATE_FIELD_SPM1, TEMPLATE_FIELD_SPM1\n\t},\n};\n\nvoid rtl930x_print_matrix(void)\n{\n\tint i;\n\tstruct table_reg *r = rtl_table_get(RTL9300_TBL_0, 6);\n\n\tfor (i = 0; i < 29; i++) {\n\t\trtl_table_read(r, i);\n\t\tpr_debug(\"> %08x\\n\", sw_r32(rtl_table_data(r, 0)));\n\t}\n\trtl_table_release(r);\n}\n\ninline void rtl930x_exec_tbl0_cmd(u32 cmd)\n{\n\tsw_w32(cmd, RTL930X_TBL_ACCESS_CTRL_0);\n\tdo { } while (sw_r32(RTL930X_TBL_ACCESS_CTRL_0) & (1 << 17));\n}\n\ninline void rtl930x_exec_tbl1_cmd(u32 cmd)\n{\n\tsw_w32(cmd, RTL930X_TBL_ACCESS_CTRL_1);\n\tdo { } while (sw_r32(RTL930X_TBL_ACCESS_CTRL_1) & (1 << 17));\n}\n\ninline int rtl930x_tbl_access_data_0(int i)\n{\n\treturn RTL930X_TBL_ACCESS_DATA_0(i);\n}\n\nstatic inline int rtl930x_l2_port_new_salrn(int p)\n{\n\treturn RTL930X_L2_PORT_SALRN(p);\n}\n\nstatic inline int rtl930x_l2_port_new_sa_fwd(int p)\n{\n\t// TODO: The definition of the fields changed, because of the master-cpu in a stack\n\treturn RTL930X_L2_PORT_NEW_SA_FWD(p);\n}\n\ninline static int rtl930x_trk_mbr_ctr(int group)\n{\n\treturn RTL930X_TRK_MBR_CTRL + (group << 2);\n}\n\nstatic void rtl930x_vlan_tables_read(u32 vlan, struct rtl838x_vlan_info *info)\n{\n\tu32 v, w;\n\t// Read VLAN table (1) via register 0\n\tstruct table_reg *r = rtl_table_get(RTL9300_TBL_0, 1);\n\n\trtl_table_read(r, vlan);\n\tv = sw_r32(rtl_table_data(r, 0));\n\tw = sw_r32(rtl_table_data(r, 1));\n\tpr_debug(\"VLAN_READ %d: %08x %08x\\n\", vlan, v, w);\n\trtl_table_release(r);\n\n\tinfo->tagged_ports = v >> 3;\n\tinfo->profile_id = (w >> 24) & 7;\n\tinfo->hash_mc_fid = !!(w & BIT(27));\n\tinfo->hash_uc_fid = !!(w & BIT(28));\n\tinfo->fid = ((v & 0x7) << 3) | ((w >> 29) & 0x7);\n\n\t// Read UNTAG table via table register 2\n\tr = rtl_table_get(RTL9300_TBL_2, 0);\n\trtl_table_read(r, vlan);\n\tv = sw_r32(rtl_table_data(r, 0));\n\trtl_table_release(r);\n\n\tinfo->untagged_ports = v >> 3;\n}\n\nstatic void rtl930x_vlan_set_tagged(u32 vlan, struct rtl838x_vlan_info *info)\n{\n\tu32 v, w;\n\t// Access VLAN table (1) via register 0\n\tstruct table_reg *r = rtl_table_get(RTL9300_TBL_0, 1);\n\n\tv = info->tagged_ports << 3;\n\tv |= ((u32)info->fid) >> 3;\n\n\tw = ((u32)info->fid) << 29;\n\tw |= info->hash_mc_fid ? BIT(27) : 0;\n\tw |= info->hash_uc_fid ? BIT(28) : 0;\n\tw |= info->profile_id << 24;\n\n\tsw_w32(v, rtl_table_data(r, 0));\n\tsw_w32(w, rtl_table_data(r, 1));\n\n\trtl_table_write(r, vlan);\n\trtl_table_release(r);\n}\n\nvoid rtl930x_vlan_profile_dump(int profile)\n{\n\tu32 p[5];\n\n\tif (profile < 0 || profile > 7)\n\t\treturn;\n\n\tp[0] = sw_r32(RTL930X_VLAN_PROFILE_SET(profile));\n\tp[1] = sw_r32(RTL930X_VLAN_PROFILE_SET(profile) + 4);\n\tp[2] = sw_r32(RTL930X_VLAN_PROFILE_SET(profile) + 8) & 0x1FFFFFFF;\n\tp[3] = sw_r32(RTL930X_VLAN_PROFILE_SET(profile) + 12) & 0x1FFFFFFF;\n\tp[4] = sw_r32(RTL930X_VLAN_PROFILE_SET(profile) + 16) & 0x1FFFFFFF;\n\n\tpr_info(\"VLAN %d: L2 learn: %d; Unknown MC PMasks: L2 %0x, IPv4 %0x, IPv6: %0x\",\n\t\tprofile, p[0] & (3 << 21), p[2], p[3], p[4]);\n\tpr_info(\"  Routing enabled: IPv4 UC %c, IPv6 UC %c, IPv4 MC %c, IPv6 MC %c\\n\",\n\t\tp[0] & BIT(17) ? 'y' : 'n', p[0] & BIT(16) ? 'y' : 'n',\n\t\tp[0] & BIT(13) ? 'y' : 'n', p[0] & BIT(12) ? 'y' : 'n');\n\tpr_info(\"  Bridge enabled: IPv4 MC %c, IPv6 MC %c,\\n\",\n\t\tp[0] & BIT(15) ? 'y' : 'n', p[0] & BIT(14) ? 'y' : 'n');\n\tpr_info(\"VLAN profile %d: raw %08x %08x %08x %08x %08x\\n\",\n\t\tprofile, p[0], p[1], p[2], p[3], p[4]);\n}\n\nstatic void rtl930x_vlan_set_untagged(u32 vlan, u64 portmask)\n{\n\tstruct table_reg *r = rtl_table_get(RTL9300_TBL_2, 0);\n\n\tsw_w32(portmask << 3, rtl_table_data(r, 0));\n\trtl_table_write(r, vlan);\n\trtl_table_release(r);\n}\n\n/* Sets the L2 forwarding to be based on either the inner VLAN tag or the outer\n */\nstatic void rtl930x_vlan_fwd_on_inner(int port, bool is_set)\n{\n\t// Always set all tag modes to fwd based on either inner or outer tag\n\tif (is_set)\n\t\tsw_w32_mask(0, 0xf, RTL930X_VLAN_PORT_FWD + (port << 2));\n\telse\n\t\tsw_w32_mask(0xf, 0, RTL930X_VLAN_PORT_FWD + (port << 2));\n}\n\nstatic void rtl930x_vlan_profile_setup(int profile)\n{\n\tu32 p[5];\n\n\tpr_info(\"In %s\\n\", __func__);\n\tp[0] = sw_r32(RTL930X_VLAN_PROFILE_SET(profile));\n\tp[1] = sw_r32(RTL930X_VLAN_PROFILE_SET(profile) + 4);\n\n\t// Enable routing of Ipv4/6 Unicast and IPv4/6 Multicast traffic\n\tp[0] |= BIT(17) | BIT(16) | BIT(13) | BIT(12);\n\tp[2] = 0x1fffffff; // L2 unknown MC flooding portmask all ports, including the CPU-port\n\tp[3] = 0x1fffffff; // IPv4 unknown MC flooding portmask\n\tp[4] = 0x1fffffff; // IPv6 unknown MC flooding portmask\n\n\tsw_w32(p[0], RTL930X_VLAN_PROFILE_SET(profile));\n\tsw_w32(p[1], RTL930X_VLAN_PROFILE_SET(profile) + 4);\n\tsw_w32(p[2], RTL930X_VLAN_PROFILE_SET(profile) + 8);\n\tsw_w32(p[3], RTL930X_VLAN_PROFILE_SET(profile) + 12);\n\tsw_w32(p[4], RTL930X_VLAN_PROFILE_SET(profile) + 16);\n}\n\nstatic void rtl930x_l2_learning_setup(void)\n{\n\t// Portmask for flooding broadcast traffic\n\tsw_w32(0x1fffffff, RTL930X_L2_BC_FLD_PMSK);\n\n\t// Portmask for flooding unicast traffic with unknown destination\n\tsw_w32(0x1fffffff, RTL930X_L2_UNKN_UC_FLD_PMSK);\n\n\t// Limit learning to maximum: 32k entries, after that just flood (bits 0-1)\n\tsw_w32((0x7fff << 2) | 0, RTL930X_L2_LRN_CONSTRT_CTRL);\n}\n\nstatic void rtl930x_stp_get(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[])\n{\n\tint i;\n\tu32 cmd = 1 << 17 /* Execute cmd */\n\t\t| 0 << 16 /* Read */\n\t\t| 4 << 12 /* Table type 0b10 */\n\t\t| (msti & 0xfff);\n\tpriv->r->exec_tbl0_cmd(cmd);\n\n\tfor (i = 0; i < 2; i++)\n\t\tport_state[i] = sw_r32(RTL930X_TBL_ACCESS_DATA_0(i));\n\tpr_debug(\"MSTI: %d STATE: %08x, %08x\\n\", msti, port_state[0], port_state[1]);\n}\n\nstatic void rtl930x_stp_set(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[])\n{\n\tint i;\n\tu32 cmd = 1 << 17 /* Execute cmd */\n\t\t| 1 << 16 /* Write */\n\t\t| 4 << 12 /* Table type 4 */\n\t\t| (msti & 0xfff);\n\n\tfor (i = 0; i < 2; i++)\n\t\tsw_w32(port_state[i], RTL930X_TBL_ACCESS_DATA_0(i));\n\tpriv->r->exec_tbl0_cmd(cmd);\n}\n\nstatic inline int rtl930x_mac_force_mode_ctrl(int p)\n{\n\treturn RTL930X_MAC_FORCE_MODE_CTRL + (p << 2);\n}\n\nstatic inline int rtl930x_mac_port_ctrl(int p)\n{\n\treturn RTL930X_MAC_L2_PORT_CTRL(p);\n}\n\nstatic inline int rtl930x_mac_link_spd_sts(int p)\n{\n\treturn RTL930X_MAC_LINK_SPD_STS(p);\n}\n\nstatic u64 rtl930x_l2_hash_seed(u64 mac, u32 vid)\n{\n\tu64 v = vid;\n\n\tv <<= 48;\n\tv |= mac;\n\n\treturn v;\n}\n\n/*\n * Calculate both the block 0 and the block 1 hash by applyingthe same hash\n * algorithm as the one used currently by the ASIC to the seed, and return\n * both hashes in the lower and higher word of the return value since only 12 bit of\n * the hash are significant\n */\nstatic u32 rtl930x_l2_hash_key(struct rtl838x_switch_priv *priv, u64 seed)\n{\n\tu32 k0, k1, h1, h2, h;\n\n\tk0 = (u32) (((seed >> 55) & 0x1f) ^ ((seed >> 44) & 0x7ff)\n\t\t^ ((seed >> 33) & 0x7ff) ^ ((seed >> 22) & 0x7ff)\n\t\t^ ((seed >> 11) & 0x7ff) ^ (seed & 0x7ff));\n\n\th1 = (seed >> 11) & 0x7ff;\n\th1 = ((h1 & 0x1f) << 6) | ((h1 >> 5) & 0x3f);\n\n\th2 = (seed >> 33) & 0x7ff;\n\th2 = ((h2 & 0x3f) << 5)| ((h2 >> 6) & 0x3f);\n\n\tk1 = (u32) (((seed << 55) & 0x1f) ^ ((seed >> 44) & 0x7ff) ^ h2\n\t\t    ^ ((seed >> 22) & 0x7ff) ^ h1\n\t\t    ^ (seed & 0x7ff));\n\n\t// Algorithm choice for block 0\n\tif (sw_r32(RTL930X_L2_CTRL) & BIT(0))\n\t\th = k1;\n\telse\n\t\th = k0;\n\n\t/* Algorithm choice for block 1\n\t * Since k0 and k1 are < 2048, adding 2048 will offset the hash into the second\n\t * half of hash-space\n\t * 2048 is in fact the hash-table size 16384 divided by 4 hashes per bucket\n\t * divided by 2 to divide the hash space in 2\n\t */\n\tif (sw_r32(RTL930X_L2_CTRL) & BIT(1))\n\t\th |= (k1 + 2048) << 16;\n\telse\n\t\th |= (k0 + 2048) << 16;\n\n\treturn h;\n}\n\n/*\n * Fills an L2 entry structure from the SoC registers\n */\nstatic void rtl930x_fill_l2_entry(u32 r[], struct rtl838x_l2_entry *e)\n{\n\tpr_debug(\"In %s valid?\\n\", __func__);\n\te->valid = !!(r[2] & BIT(31));\n\tif (!e->valid)\n\t\treturn;\n\n\tpr_debug(\"In %s is valid\\n\", __func__);\n\te->is_ip_mc = false;\n\te->is_ipv6_mc = false;\n\n\t// TODO: Is there not a function to copy directly MAC memory?\n\te->mac[0] = (r[0] >> 24);\n\te->mac[1] = (r[0] >> 16);\n\te->mac[2] = (r[0] >> 8);\n\te->mac[3] = r[0];\n\te->mac[4] = (r[1] >> 24);\n\te->mac[5] = (r[1] >> 16);\n\n\te->next_hop = !!(r[2] & BIT(12));\n\te->rvid = r[1] & 0xfff;\n\n\t/* Is it a unicast entry? check multicast bit */\n\tif (!(e->mac[0] & 1)) {\n\t\te->type = L2_UNICAST;\n\t\te->is_static = !!(r[2] & BIT(14));\n\t\te->port = (r[2] >> 20) & 0x3ff;\n\t\t// Check for trunk port\n\t\tif (r[2] & BIT(30)) {\n\t\t\te->is_trunk = true;\n\t\t\te->stack_dev = (e->port >> 9) & 1;\n\t\t\te->trunk = e->port & 0x3f;\n\t\t} else {\n\t\t\te->is_trunk = false;\n\t\t\te->stack_dev = (e->port >> 6) & 0xf;\n\t\t\te->port = e->port & 0x3f;\n\t\t}\n\n\t\te->block_da = !!(r[2] & BIT(15));\n\t\te->block_sa = !!(r[2] & BIT(16));\n\t\te->suspended = !!(r[2] & BIT(13));\n\t\te->age = (r[2] >> 17) & 3;\n\t\te->valid = true;\n\t\t// the UC_VID field in hardware is used for the VID or for the route id\n\t\tif (e->next_hop) {\n\t\t\te->nh_route_id = r[2] & 0x7ff;\n\t\t\te->vid = 0;\n\t\t} else {\n\t\t\te->vid = r[2] & 0xfff;\n\t\t\te->nh_route_id = 0;\n\t\t}\n\t} else {\n\t\te->valid = true;\n\t\te->type = L2_MULTICAST;\n\t\te->mc_portmask_index = (r[2] >> 16) & 0x3ff;\n\t}\n}\n\n/*\n * Fills the 3 SoC table registers r[] with the information of in the rtl838x_l2_entry\n */\nstatic void rtl930x_fill_l2_row(u32 r[], struct rtl838x_l2_entry *e)\n{\n\tu32 port;\n\n\tif (!e->valid) {\n\t\tr[0] = r[1] = r[2] = 0;\n\t\treturn;\n\t}\n\n\tr[2] = BIT(31);\t// Set valid bit\n\n\tr[0] = ((u32)e->mac[0]) << 24 | ((u32)e->mac[1]) << 16 \n\t\t| ((u32)e->mac[2]) << 8 | ((u32)e->mac[3]);\n\tr[1] = ((u32)e->mac[4]) << 24 | ((u32)e->mac[5]) << 16;\n\n\tr[2] |= e->next_hop ? BIT(12) : 0;\n\n\tif (e->type == L2_UNICAST) {\n\t\tr[2] |= e->is_static ? BIT(14) : 0;\n\t\tr[1] |= e->rvid & 0xfff;\n\t\tr[2] |= (e->port & 0x3ff) << 20;\n\t\tif (e->is_trunk) {\n\t\t\tr[2] |= BIT(30);\n\t\t\tport = e->stack_dev << 9 | (e->port & 0x3f);\n\t\t} else {\n\t\t\tport = (e->stack_dev & 0xf) << 6;\n\t\t\tport |= e->port & 0x3f;\n\t\t}\n\t\tr[2] |= port << 20;\n\t\tr[2] |= e->block_da ? BIT(15) : 0;\n\t\tr[2] |= e->block_sa ? BIT(17) : 0;\n\t\tr[2] |= e->suspended ? BIT(13) : 0;\n\t\tr[2] |= (e->age & 0x3) << 17;\n\t\t// the UC_VID field in hardware is used for the VID or for the route id\n\t\tif (e->next_hop)\n\t\t\tr[2] |= e->nh_route_id & 0x7ff;\n\t\telse\n\t\t\tr[2] |= e->vid & 0xfff;\n\t} else { // L2_MULTICAST\n\t\tr[2] |= (e->mc_portmask_index & 0x3ff) << 16;\n\t\tr[2] |= e->mc_mac_index & 0x7ff;\n\t}\n}\n\n/*\n * Read an L2 UC or MC entry out of a hash bucket of the L2 forwarding table\n * hash is the id of the bucket and pos is the position of the entry in that bucket\n * The data read from the SoC is filled into rtl838x_l2_entry\n */\nstatic u64 rtl930x_read_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_l2_entry *e)\n{\n\tu32 r[3];\n\tstruct table_reg *q = rtl_table_get(RTL9300_TBL_L2, 0);\n\tu32 idx;\n\tint i;\n\tu64 mac;\n\tu64 seed;\n\n\tpr_debug(\"%s: hash %08x, pos: %d\\n\", __func__, hash, pos);\n\n\t/* On the RTL93xx, 2 different hash algorithms are used making it a total of\n\t * 8 buckets that need to be searched, 4 for each hash-half\n\t * Use second hash space when bucket is between 4 and 8 */\n\tif (pos >= 4) {\n\t\tpos -= 4;\n\t\thash >>= 16;\n\t} else {\n\t\thash &= 0xffff;\n\t}\n\n\tidx = (0 << 14) | (hash << 2) | pos; // Search SRAM, with hash and at pos in bucket\n\tpr_debug(\"%s: NOW hash %08x, pos: %d\\n\", __func__, hash, pos);\n\n\trtl_table_read(q, idx);\n\tfor (i = 0; i < 3; i++)\n\t\tr[i] = sw_r32(rtl_table_data(q, i));\n\n\trtl_table_release(q);\n\n\trtl930x_fill_l2_entry(r, e);\n\n\tpr_debug(\"%s: valid: %d, nh: %d\\n\", __func__, e->valid, e->next_hop);\n\tif (!e->valid)\n\t\treturn 0;\n\n\tmac = ((u64)e->mac[0]) << 40 | ((u64)e->mac[1]) << 32 | ((u64)e->mac[2]) << 24\n\t\t| ((u64)e->mac[3]) << 16 | ((u64)e->mac[4]) << 8 | ((u64)e->mac[5]);\n\n\tseed = rtl930x_l2_hash_seed(mac, e->rvid);\n\tpr_debug(\"%s: mac %016llx, seed %016llx\\n\", __func__, mac, seed);\n\t// return vid with concatenated mac as unique id\n\treturn seed;\n}\n\nstatic void rtl930x_write_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_l2_entry *e)\n{\n\tu32 r[3];\n\tstruct table_reg *q = rtl_table_get(RTL9300_TBL_L2, 0);\n\tu32 idx = (0 << 14) | (hash << 2) | pos; // Access SRAM, with hash and at pos in bucket\n\tint i;\n\n\tpr_debug(\"%s: hash %d, pos %d\\n\", __func__, hash, pos);\n\tpr_debug(\"%s: index %d -> mac %02x:%02x:%02x:%02x:%02x:%02x\\n\", __func__, idx,\n\t\te->mac[0], e->mac[1], e->mac[2], e->mac[3],e->mac[4],e->mac[5]);\n\n\trtl930x_fill_l2_row(r, e);\n\n\tfor (i= 0; i < 3; i++)\n\t\tsw_w32(r[i], rtl_table_data(q, i));\n\n\trtl_table_write(q, idx);\n\trtl_table_release(q);\n}\n\nstatic u64 rtl930x_read_cam(int idx, struct rtl838x_l2_entry *e)\n{\n\tu32 r[3];\n\tstruct table_reg *q = rtl_table_get(RTL9300_TBL_L2, 1);\n\tint i;\n\n\trtl_table_read(q, idx);\n\tfor (i= 0; i < 3; i++)\n\t\tr[i] = sw_r32(rtl_table_data(q, i));\n\n\trtl_table_release(q);\n\n\trtl930x_fill_l2_entry(r, e);\n\tif (!e->valid)\n\t\treturn 0;\n\n\t// return mac with concatenated vid as unique id\n\treturn ((u64)r[0] << 28) | ((r[1] & 0xffff0000) >> 4) | e->vid;\n}\n\nstatic void rtl930x_write_cam(int idx, struct rtl838x_l2_entry *e)\n{\n\tu32 r[3];\n\tstruct table_reg *q = rtl_table_get(RTL9300_TBL_L2, 1); // Access L2 Table 1\n\tint i;\n\n\trtl930x_fill_l2_row(r, e);\n\n\tfor (i= 0; i < 3; i++)\n\t\tsw_w32(r[i], rtl_table_data(q, i));\n\n\trtl_table_write(q, idx);\n\trtl_table_release(q);\n}\n\nstatic void dump_l2_entry(struct rtl838x_l2_entry *e)\n{\n\tpr_info(\"MAC: %02x:%02x:%02x:%02x:%02x:%02x vid: %d, rvid: %d, port: %d, valid: %d\\n\",\n\t\te->mac[0], e->mac[1], e->mac[2], e->mac[3], e->mac[4], e->mac[5],\n\t\te->vid, e->rvid, e->port, e->valid);\n\tpr_info(\"Type: %d, is_static: %d, is_ip_mc: %d, is_ipv6_mc: %d, block_da: %d\\n\",\n\t\te->type, e->is_static, e->is_ip_mc, e->is_ipv6_mc, e->block_da);\n\tpr_info(\"  block_sa: %d, suspended: %d, next_hop: %d, age: %d, is_trunk: %d, trunk: %d\\n\",\n\t\te->block_sa, e->suspended, e->next_hop, e->age, e->is_trunk, e->trunk);\n\tif (e->is_ip_mc || e->is_ipv6_mc)\n\t\tpr_info(\"  mc_portmask_index: %d, mc_gip: %d, mc_sip: %d\\n\",\n\t\t\te->mc_portmask_index, e->mc_gip, e->mc_sip);\n\tpr_info(\"  stac_dev: %d, nh_route_id: %d, port: %d, dev_id\\n\",\n\t\te->stack_dev, e->nh_route_id, e->port);\n}\n\nstatic u64 rtl930x_read_mcast_pmask(int idx)\n{\n\tu32 portmask;\n\t// Read MC_PORTMASK (2) via register RTL9300_TBL_L2\n\tstruct table_reg *q = rtl_table_get(RTL9300_TBL_L2, 2);\n\n\trtl_table_read(q, idx);\n\tportmask = sw_r32(rtl_table_data(q, 0));\n\tportmask >>= 3;\n\trtl_table_release(q);\n\n\tpr_debug(\"%s: Index idx %d has portmask %08x\\n\", __func__, idx, portmask);\n\treturn portmask;\n}\n\nstatic void rtl930x_write_mcast_pmask(int idx, u64 portmask)\n{\n\tu32 pm = portmask;\n\n\t// Access MC_PORTMASK (2) via register RTL9300_TBL_L2\n\tstruct table_reg *q = rtl_table_get(RTL9300_TBL_L2, 2);\n\n\tpr_debug(\"%s: Index idx %d has portmask %08x\\n\", __func__, idx, pm);\n\tpm <<= 3;\n\tsw_w32(pm, rtl_table_data(q, 0));\n\trtl_table_write(q, idx);\n\trtl_table_release(q);\n}\n\nu64 rtl930x_traffic_get(int source)\n{\n\tu32 v;\n\tstruct table_reg *r = rtl_table_get(RTL9300_TBL_0, 6);\n\n\trtl_table_read(r, source);\n\tv = sw_r32(rtl_table_data(r, 0));\n\trtl_table_release(r);\n\treturn v >> 3;\n}\n\n/*\n * Enable traffic between a source port and a destination port matrix\n */\nvoid rtl930x_traffic_set(int source, u64 dest_matrix)\n{\n\tstruct table_reg *r = rtl_table_get(RTL9300_TBL_0, 6);\n\n\tsw_w32((dest_matrix << 3), rtl_table_data(r, 0));\n\trtl_table_write(r, source);\n\trtl_table_release(r);\n}\n\nvoid rtl930x_traffic_enable(int source, int dest)\n{\n\tstruct table_reg *r = rtl_table_get(RTL9300_TBL_0, 6);\n\trtl_table_read(r, source);\n\tsw_w32_mask(0, BIT(dest + 3), rtl_table_data(r, 0));\n\trtl_table_write(r, source);\n\trtl_table_release(r);\n}\n\nvoid rtl930x_traffic_disable(int source, int dest)\n{\n\tstruct table_reg *r = rtl_table_get(RTL9300_TBL_0, 6);\n\trtl_table_read(r, source);\n\tsw_w32_mask(BIT(dest + 3), 0, rtl_table_data(r, 0));\n\trtl_table_write(r, source);\n\trtl_table_release(r);\n}\n\nvoid rtl9300_dump_debug(void)\n{\n\tint i;\n\tu16 r = RTL930X_STAT_PRVTE_DROP_COUNTER0;\n\n\tfor (i = 0; i < 10; i ++) {\n\t\tpr_info(\"# %d %08x %08x %08x %08x %08x %08x %08x %08x\\n\", i * 8,\n\t\t\tsw_r32(r), sw_r32(r + 4), sw_r32(r + 8), sw_r32(r + 12),\n\t\t\tsw_r32(r + 16), sw_r32(r + 20), sw_r32(r + 24), sw_r32(r + 28));\n\t\tr += 32;\n\t}\n\tpr_info(\"# %08x %08x %08x %08x %08x\\n\",\n\t\tsw_r32(r), sw_r32(r + 4), sw_r32(r + 8), sw_r32(r + 12), sw_r32(r + 16));\n\trtl930x_print_matrix();\n\tpr_info(\"RTL930X_L2_PORT_SABLK_CTRL: %08x, RTL930X_L2_PORT_DABLK_CTRL %08x\\n\",\n\t\tsw_r32(RTL930X_L2_PORT_SABLK_CTRL), sw_r32(RTL930X_L2_PORT_DABLK_CTRL)\n\n\t);\n}\n\nirqreturn_t rtl930x_switch_irq(int irq, void *dev_id)\n{\n\tstruct dsa_switch *ds = dev_id;\n\tu32 ports = sw_r32(RTL930X_ISR_PORT_LINK_STS_CHG);\n\tu32 link;\n\tint i;\n\n\t/* Clear status */\n\tsw_w32(ports, RTL930X_ISR_PORT_LINK_STS_CHG);\n\n\tfor (i = 0; i < 28; i++) {\n\t\tif (ports & BIT(i)) {\n\t\t\t/* Read the register twice because of issues with latency at least\n\t\t\t * with the external RTL8226 PHY on the XGS1210 */\n\t\t\tlink = sw_r32(RTL930X_MAC_LINK_STS);\n\t\t\tlink = sw_r32(RTL930X_MAC_LINK_STS);\n\t\t\tif (link & BIT(i))\n\t\t\t\tdsa_port_phylink_mac_change(ds, i, true);\n\t\t\telse\n\t\t\t\tdsa_port_phylink_mac_change(ds, i, false);\n\t\t}\n\t}\n\n\treturn IRQ_HANDLED;\n}\n\nint rtl930x_write_phy(u32 port, u32 page, u32 reg, u32 val)\n{\n\tu32 v;\n\tint err = 0;\n\n\tpr_debug(\"%s: port %d, page: %d, reg: %x, val: %x\\n\", __func__, port, page, reg, val);\n\n\tif (port > 63 || page > 4095 || reg > 31)\n\t\treturn -ENOTSUPP;\n\n\tval &= 0xffff;\n\tmutex_lock(&smi_lock);\n\n\tsw_w32(BIT(port), RTL930X_SMI_ACCESS_PHY_CTRL_0);\n\tsw_w32_mask(0xffff << 16, val << 16, RTL930X_SMI_ACCESS_PHY_CTRL_2);\n\tv = reg << 20 | page << 3 | 0x1f << 15 | BIT(2) | BIT(0);\n\tsw_w32(v, RTL930X_SMI_ACCESS_PHY_CTRL_1);\n\n\tdo {\n\t\tv = sw_r32(RTL930X_SMI_ACCESS_PHY_CTRL_1);\n\t} while (v & 0x1);\n\n\tif (v & 0x2)\n\t\terr = -EIO;\n\n\tmutex_unlock(&smi_lock);\n\n\treturn err;\n}\n\nint rtl930x_read_phy(u32 port, u32 page, u32 reg, u32 *val)\n{\n\tu32 v;\n\tint err = 0;\n\n\tif (port > 63 || page > 4095 || reg > 31)\n\t\treturn -ENOTSUPP;\n\n\tmutex_lock(&smi_lock);\n\n\tsw_w32_mask(0xffff << 16, port << 16, RTL930X_SMI_ACCESS_PHY_CTRL_2);\n\tv = reg << 20 | page << 3 | 0x1f << 15 | 1;\n\tsw_w32(v, RTL930X_SMI_ACCESS_PHY_CTRL_1);\n\n\tdo {\n\t\tv = sw_r32(RTL930X_SMI_ACCESS_PHY_CTRL_1);\n\t} while ( v & 0x1);\n\n\tif (v & BIT(25)) {\n\t\tpr_debug(\"Error reading phy %d, register %d\\n\", port, reg);\n\t\terr = -EIO;\n\t}\n\t*val = (sw_r32(RTL930X_SMI_ACCESS_PHY_CTRL_2) & 0xffff);\n\n\tpr_debug(\"%s: port %d, page: %d, reg: %x, val: %x\\n\", __func__, port, page, reg, *val);\n\n\tmutex_unlock(&smi_lock);\n\n\treturn err;\n}\n\n/*\n * Write to an mmd register of the PHY\n */\nint rtl930x_write_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 val)\n{\n\tint err = 0;\n\tu32 v;\n\n\tmutex_lock(&smi_lock);\n\n\t// Set PHY to access\n\tsw_w32(BIT(port), RTL930X_SMI_ACCESS_PHY_CTRL_0);\n\n\t// Set data to write\n\tsw_w32_mask(0xffff << 16, val << 16, RTL930X_SMI_ACCESS_PHY_CTRL_2);\n\n\t// Set MMD device number and register to write to\n\tsw_w32(devnum << 16 | (regnum & 0xffff), RTL930X_SMI_ACCESS_PHY_CTRL_3);\n\n\tv = BIT(2) | BIT(1) | BIT(0); // WRITE | MMD-access | EXEC\n\tsw_w32(v, RTL930X_SMI_ACCESS_PHY_CTRL_1);\n\n\tdo {\n\t\tv = sw_r32(RTL930X_SMI_ACCESS_PHY_CTRL_1);\n\t} while (v & BIT(0));\n\n\tpr_debug(\"%s: port %d, regnum: %x, val: %x (err %d)\\n\", __func__, port, regnum, val, err);\n\tmutex_unlock(&smi_lock);\n\treturn err;\n}\n\n/*\n * Read an mmd register of the PHY\n */\nint rtl930x_read_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 *val)\n{\n\tint err = 0;\n\tu32 v;\n\n\tmutex_lock(&smi_lock);\n\n\t// Set PHY to access\n\tsw_w32_mask(0xffff << 16, port << 16, RTL930X_SMI_ACCESS_PHY_CTRL_2);\n\n\t// Set MMD device number and register to write to\n\tsw_w32(devnum << 16 | (regnum & 0xffff), RTL930X_SMI_ACCESS_PHY_CTRL_3);\n\n\tv = BIT(1) | BIT(0); // MMD-access | EXEC\n\tsw_w32(v, RTL930X_SMI_ACCESS_PHY_CTRL_1);\n\n\tdo {\n\t\tv = sw_r32(RTL930X_SMI_ACCESS_PHY_CTRL_1);\n\t} while (v & BIT(0));\n\t// There is no error-checking via BIT 25 of v, as it does not seem to be set correctly\n\t*val = (sw_r32(RTL930X_SMI_ACCESS_PHY_CTRL_2) & 0xffff);\n\tpr_debug(\"%s: port %d, regnum: %x, val: %x (err %d)\\n\", __func__, port, regnum, *val, err);\n\n\tmutex_unlock(&smi_lock);\n\n\treturn err;\n}\n\n/*\n * Calculate both the block 0 and the block 1 hash, and return in\n * lower and higher word of the return value since only 12 bit of\n * the hash are significant\n */\nu32 rtl930x_hash(struct rtl838x_switch_priv *priv, u64 seed)\n{\n\tu32 k0, k1, h1, h2, h;\n\n\tk0 = (u32) (((seed >> 55) & 0x1f) ^ ((seed >> 44) & 0x7ff)\n\t\t^ ((seed >> 33) & 0x7ff) ^ ((seed >> 22) & 0x7ff)\n\t\t^ ((seed >> 11) & 0x7ff) ^ (seed & 0x7ff));\n\n\th1 = (seed >> 11) & 0x7ff;\n\th1 = ((h1 & 0x1f) << 6) | ((h1 >> 5) & 0x3f);\n\n\th2 = (seed >> 33) & 0x7ff;\n\th2 = ((h2 & 0x3f) << 5)| ((h2 >> 6) & 0x3f);\n\n\tk1 = (u32) (((seed << 55) & 0x1f) ^ ((seed >> 44) & 0x7ff) ^ h2\n\t\t    ^ ((seed >> 22) & 0x7ff) ^ h1\n\t\t    ^ (seed & 0x7ff));\n\n\t// Algorithm choice for block 0\n\tif (sw_r32(RTL930X_L2_CTRL) & BIT(0))\n\t\th = k1;\n\telse\n\t\th = k0;\n\n\t/* Algorithm choice for block 1\n\t * Since k0 and k1 are < 2048, adding 2048 will offset the hash into the second\n\t * half of hash-space\n\t * 2048 is in fact the hash-table size 16384 divided by 4 hashes per bucket\n\t * divided by 2 to divide the hash space in 2\n\t */\n\tif (sw_r32(RTL930X_L2_CTRL) & BIT(1))\n\t\th |= (k1 + 2048) << 16;\n\telse\n\t\th |= (k0 + 2048) << 16;\n\n\treturn h;\n}\n\n/*\n * Enables or disables the EEE/EEEP capability of a port\n */\nvoid rtl930x_port_eee_set(struct rtl838x_switch_priv *priv, int port, bool enable)\n{\n\tu32 v;\n\n\t// This works only for Ethernet ports, and on the RTL930X, ports from 26 are SFP\n\tif (port >= 26)\n\t\treturn;\n\n\tpr_debug(\"In %s: setting port %d to %d\\n\", __func__, port, enable);\n\tv = enable ? 0x3f : 0x0;\n\n\t// Set EEE/EEEP state for 100, 500, 1000MBit and 2.5, 5 and 10GBit\n\tsw_w32_mask(0, v << 10, rtl930x_mac_force_mode_ctrl(port));\n\n\t// Set TX/RX EEE state\n\tv = enable ? 0x3 : 0x0;\n\tsw_w32(v, RTL930X_EEE_CTRL(port));\n\n\tpriv->ports[port].eee_enabled = enable;\n}\n\n/*\n * Get EEE own capabilities and negotiation result\n */\nint rtl930x_eee_port_ability(struct rtl838x_switch_priv *priv, struct ethtool_eee *e, int port)\n{\n\tu32 link, a;\n\n\tif (port >= 26)\n\t\treturn -ENOTSUPP;\n\n\tpr_info(\"In %s, port %d\\n\", __func__, port);\n\tlink = sw_r32(RTL930X_MAC_LINK_STS);\n\tlink = sw_r32(RTL930X_MAC_LINK_STS);\n\tif (!(link & BIT(port)))\n\t\treturn 0;\n\n\tpr_info(\"Setting advertised\\n\");\n\tif (sw_r32(rtl930x_mac_force_mode_ctrl(port)) & BIT(10))\n\t\te->advertised |= ADVERTISED_100baseT_Full;\n\n\tif (sw_r32(rtl930x_mac_force_mode_ctrl(port)) & BIT(12))\n\t\te->advertised |= ADVERTISED_1000baseT_Full;\n\n\tif (priv->ports[port].is2G5 && sw_r32(rtl930x_mac_force_mode_ctrl(port)) & BIT(13)) {\n\t\tpr_info(\"ADVERTISING 2.5G EEE\\n\");\n\t\te->advertised |= ADVERTISED_2500baseX_Full;\n\t}\n\n\tif (priv->ports[port].is10G && sw_r32(rtl930x_mac_force_mode_ctrl(port)) & BIT(15))\n\t\te->advertised |= ADVERTISED_10000baseT_Full;\n\n\ta = sw_r32(RTL930X_MAC_EEE_ABLTY);\n\ta = sw_r32(RTL930X_MAC_EEE_ABLTY);\n\tpr_info(\"Link partner: %08x\\n\", a);\n\tif (a & BIT(port)) {\n\t\te->lp_advertised = ADVERTISED_100baseT_Full;\n\t\te->lp_advertised |= ADVERTISED_1000baseT_Full;\n\t\tif (priv->ports[port].is2G5)\n\t\t\te->lp_advertised |= ADVERTISED_2500baseX_Full;\n\t\tif (priv->ports[port].is10G)\n\t\t\te->lp_advertised |= ADVERTISED_10000baseT_Full;\n\t}\n\n\t// Read 2x to clear latched state\n\ta = sw_r32(RTL930X_EEEP_PORT_CTRL(port));\n\ta = sw_r32(RTL930X_EEEP_PORT_CTRL(port));\n\tpr_info(\"%s RTL930X_EEEP_PORT_CTRL: %08x\\n\", __func__, a);\n\n\treturn 0;\n}\n\nstatic void rtl930x_init_eee(struct rtl838x_switch_priv *priv, bool enable)\n{\n\tint i;\n\n\tpr_info(\"Setting up EEE, state: %d\\n\", enable);\n\n\t// Setup EEE on all ports\n\tfor (i = 0; i < priv->cpu_port; i++) {\n\t\tif (priv->ports[i].phy)\n\t\t\trtl930x_port_eee_set(priv, i, enable);\n\t}\n\n\tpriv->eee_enabled = enable;\n}\n#define HASH_PICK(val, lsb, len)   ((val & (((1 << len) - 1) << lsb)) >> lsb)\n\nstatic u32 rtl930x_l3_hash4(u32 ip, int algorithm, bool move_dip)\n{\n\tu32 rows[4];\n\tu32 hash;\n\tu32 s0, s1, pH;\n\n\tmemset(rows, 0, sizeof(rows));\n\n\trows[0] = HASH_PICK(ip, 27, 5);\n\trows[1] = HASH_PICK(ip, 18, 9);\n\trows[2] = HASH_PICK(ip, 9, 9);\n\n\tif (!move_dip)\n\t\trows[3] = HASH_PICK(ip, 0, 9);\n\n\tif (!algorithm) {\n\t\thash = rows[0] ^ rows[1] ^ rows[2] ^ rows[3];\n\t} else {\n\t\ts0 = rows[0] + rows[1] + rows[2];\n\t\ts1 = (s0 & 0x1ff) + ((s0 & (0x1ff << 9)) >> 9);\n\t\tpH = (s1 & 0x1ff) + ((s1 & (0x1ff << 9)) >> 9);\n\t\thash = pH ^ rows[3];\n\t}\n\treturn hash;\n}\n\nstatic u32 rtl930x_l3_hash6(struct in6_addr *ip6, int algorithm, bool move_dip)\n{\n\tu32 rows[16];\n\tu32 hash;\n\tu32 s0, s1, pH;\n\n\trows[0] = (HASH_PICK(ip6->s6_addr[0], 6, 2) << 0);\n\trows[1] = (HASH_PICK(ip6->s6_addr[0], 0, 6) << 3) | HASH_PICK(ip6->s6_addr[1], 5, 3);\n\trows[2] = (HASH_PICK(ip6->s6_addr[1], 0, 5) << 4) | HASH_PICK(ip6->s6_addr[2], 4, 4);\n\trows[3] = (HASH_PICK(ip6->s6_addr[2], 0, 4) << 5) | HASH_PICK(ip6->s6_addr[3], 3, 5);\n\trows[4] = (HASH_PICK(ip6->s6_addr[3], 0, 3) << 6) | HASH_PICK(ip6->s6_addr[4], 2, 6);\n\trows[5] = (HASH_PICK(ip6->s6_addr[4], 0, 2) << 7) | HASH_PICK(ip6->s6_addr[5], 1, 7);\n\trows[6] = (HASH_PICK(ip6->s6_addr[5], 0, 1) << 8) | HASH_PICK(ip6->s6_addr[6], 0, 8);\n\trows[7] = (HASH_PICK(ip6->s6_addr[7], 0, 8) << 1) | HASH_PICK(ip6->s6_addr[8], 7, 1);\n\trows[8] = (HASH_PICK(ip6->s6_addr[8], 0, 7) << 2) | HASH_PICK(ip6->s6_addr[9], 6, 2);\n\trows[9] = (HASH_PICK(ip6->s6_addr[9], 0, 6) << 3) | HASH_PICK(ip6->s6_addr[10], 5, 3);\n\trows[10] = (HASH_PICK(ip6->s6_addr[10], 0, 5) << 4) | HASH_PICK(ip6->s6_addr[11], 4, 4);\n\tif (!algorithm) {\n\t\trows[11] = (HASH_PICK(ip6->s6_addr[11], 0, 4) << 5)\n\t\t\t\t| (HASH_PICK(ip6->s6_addr[12], 3, 5) << 0);\n\t\trows[12] = (HASH_PICK(ip6->s6_addr[12], 0, 3) << 6)\n\t\t\t\t| (HASH_PICK(ip6->s6_addr[13], 2, 6) << 0);\n\t\trows[13] = (HASH_PICK(ip6->s6_addr[13], 0, 2) << 7)\n\t\t\t\t| (HASH_PICK(ip6->s6_addr[14], 1, 7) << 0);\n\t\tif (!move_dip) {\n\t\t\trows[14] = (HASH_PICK(ip6->s6_addr[14], 0, 1) << 8)\n\t\t\t\t\t| (HASH_PICK(ip6->s6_addr[15], 0, 8) << 0);\n\t\t}\n\t\thash = rows[0] ^ rows[1] ^ rows[2] ^ rows[3] ^ rows[4] ^ rows[5] ^ rows[6]\n\t\t\t^ rows[7] ^ rows[8] ^ rows[9] ^ rows[10] ^ rows[11] ^ rows[12]\n\t\t\t^ rows[13] ^ rows[14];\n\t} else {\n\t\trows[11] = (HASH_PICK(ip6->s6_addr[11], 0, 4) << 5);\n\t\trows[12] = (HASH_PICK(ip6->s6_addr[12], 3, 5) << 0);\n\t\trows[13] = (HASH_PICK(ip6->s6_addr[12], 0, 3) << 6)\n\t\t\t\t| HASH_PICK(ip6->s6_addr[13], 2, 6);\n\t\trows[14] = (HASH_PICK(ip6->s6_addr[13], 0, 2) << 7)\n\t\t\t\t| HASH_PICK(ip6->s6_addr[14], 1, 7);\n\t\tif (!move_dip) {\n\t\t\trows[15] = (HASH_PICK(ip6->s6_addr[14], 0, 1) << 8)\n\t\t\t\t\t| (HASH_PICK(ip6->s6_addr[15], 0, 8) << 0);\n\t\t}\n\t\ts0 = rows[12] + rows[13] + rows[14];\n\t\ts1 = (s0 & 0x1ff) + ((s0 & (0x1ff << 9)) >> 9);\n\t\tpH = (s1 & 0x1ff) + ((s1 & (0x1ff << 9)) >> 9);\n\t\thash = rows[0] ^ rows[1] ^ rows[2] ^ rows[3] ^ rows[4] ^ rows[5] ^ rows[6]\n\t\t\t^ rows[7] ^ rows[8] ^ rows[9] ^ rows[10] ^ rows[11] ^ pH ^ rows[15];\n\t}\n\treturn hash;\n}\n\n/*\n * Read a prefix route entry from the L3_PREFIX_ROUTE_IPUC table\n * We currently only support IPv4 and IPv6 unicast route\n */\nstatic void rtl930x_route_read(int idx, struct rtl83xx_route *rt)\n{\n\tu32 v, ip4_m;\n\tbool host_route, default_route;\n\tstruct in6_addr ip6_m;\n\n\t// Read L3_PREFIX_ROUTE_IPUC table (2) via register RTL9300_TBL_1\n\tstruct table_reg *r = rtl_table_get(RTL9300_TBL_1, 2);\n\n\trtl_table_read(r, idx);\n\t// The table has a size of 11 registers\n\trt->attr.valid = !!(sw_r32(rtl_table_data(r, 0)) & BIT(31));\n\tif (!rt->attr.valid)\n\t\tgoto out;\n\n\trt->attr.type = (sw_r32(rtl_table_data(r, 0)) >> 29) & 0x3;\n\n\tv = sw_r32(rtl_table_data(r, 10));\n\thost_route = !!(v & BIT(21));\n\tdefault_route = !!(v & BIT(20));\n\trt->prefix_len = -1;\n\tpr_info(\"%s: host route %d, default_route %d\\n\", __func__, host_route, default_route);\n\n\tswitch (rt->attr.type) {\n\tcase 0: // IPv4 Unicast route\n\t\trt->dst_ip = sw_r32(rtl_table_data(r, 4));\n\t\tip4_m = sw_r32(rtl_table_data(r, 9));\n\t\tpr_info(\"%s: Read ip4 mask: %08x\\n\", __func__, ip4_m);\n\t\trt->prefix_len = host_route ? 32 : -1;\n\t\trt->prefix_len = (rt->prefix_len < 0 && default_route) ? 0 : -1;\n\t\tif (rt->prefix_len < 0)\n\t\t\trt->prefix_len = inet_mask_len(ip4_m);\n\t\tbreak;\n\tcase 2: // IPv6 Unicast route\n\t\tipv6_addr_set(&rt->dst_ip6,\n\t\t\t      sw_r32(rtl_table_data(r, 1)), sw_r32(rtl_table_data(r, 2)),\n\t\t\t      sw_r32(rtl_table_data(r, 3)), sw_r32(rtl_table_data(r, 4)));\n\t\tipv6_addr_set(&ip6_m,\n\t\t\t      sw_r32(rtl_table_data(r, 6)), sw_r32(rtl_table_data(r, 7)),\n\t\t\t      sw_r32(rtl_table_data(r, 8)), sw_r32(rtl_table_data(r, 9)));\n\t\trt->prefix_len = host_route ? 128 : 0;\n\t\trt->prefix_len = (rt->prefix_len < 0 && default_route) ? 0 : -1;\n\t\tif (rt->prefix_len < 0)\n\t\t\trt->prefix_len = find_last_bit((unsigned long int *)&ip6_m.s6_addr32,\n\t\t\t\t\t\t\t 128);\n\t\tbreak;\n\tcase 1: // IPv4 Multicast route\n\tcase 3: // IPv6 Multicast route\n\t\tpr_warn(\"%s: route type not supported\\n\", __func__);\n\t\tgoto out;\n\t}\n\n\trt->attr.hit = !!(v & BIT(22));\n\trt->attr.action = (v >> 18) & 3;\n\trt->nh.id = (v >> 7) & 0x7ff;\n\trt->attr.ttl_dec = !!(v & BIT(6));\n\trt->attr.ttl_check = !!(v & BIT(5));\n\trt->attr.dst_null = !!(v & BIT(4));\n\trt->attr.qos_as = !!(v & BIT(3));\n\trt->attr.qos_prio =  v & 0x7;\n\tpr_info(\"%s: index %d is valid: %d\\n\", __func__, idx, rt->attr.valid);\n\tpr_info(\"%s: next_hop: %d, hit: %d, action :%d, ttl_dec %d, ttl_check %d, dst_null %d\\n\",\n\t\t__func__, rt->nh.id, rt->attr.hit, rt->attr.action,\n\t\trt->attr.ttl_dec, rt->attr.ttl_check, rt->attr.dst_null);\n\tpr_info(\"%s: GW: %pI4, prefix_len: %d\\n\", __func__, &rt->dst_ip, rt->prefix_len);\nout:\n\trtl_table_release(r);\n}\n\nstatic void rtl930x_net6_mask(int prefix_len, struct in6_addr *ip6_m)\n{\n\tint o, b;\n\t// Define network mask\n\to = prefix_len >> 3;\n\tb = prefix_len & 0x7;\n\tmemset(ip6_m->s6_addr, 0xff, o);\n\tip6_m->s6_addr[o] |= b ? 0xff00 >> b : 0x00;\n}\n\n/*\n * Read a host route entry from the table using its index\n * We currently only support IPv4 and IPv6 unicast route\n */\nstatic void rtl930x_host_route_read(int idx, struct rtl83xx_route *rt)\n{\n\tu32 v;\n\t// Read L3_HOST_ROUTE_IPUC table (1) via register RTL9300_TBL_1\n\tstruct table_reg *r = rtl_table_get(RTL9300_TBL_1, 1);\n\n\tidx = ((idx / 6) * 8) + (idx % 6);\n\n\tpr_debug(\"In %s, physical index %d\\n\", __func__, idx);\n\trtl_table_read(r, idx);\n\t// The table has a size of 5 (for UC, 11 for MC) registers\n\tv = sw_r32(rtl_table_data(r, 0));\n\trt->attr.valid = !!(v & BIT(31));\n\tif (!rt->attr.valid)\n\t\tgoto out;\n\trt->attr.type = (v >> 29) & 0x3;\n\tswitch (rt->attr.type) {\n\tcase 0: // IPv4 Unicast route\n\t\trt->dst_ip = sw_r32(rtl_table_data(r, 4));\n\t\tbreak;\n\tcase 2: // IPv6 Unicast route\n\t\tipv6_addr_set(&rt->dst_ip6,\n\t\t\t      sw_r32(rtl_table_data(r, 3)), sw_r32(rtl_table_data(r, 2)),\n\t\t\t      sw_r32(rtl_table_data(r, 1)), sw_r32(rtl_table_data(r, 0)));\n\t\tbreak;\n\tcase 1: // IPv4 Multicast route\n\tcase 3: // IPv6 Multicast route\n\t\tpr_warn(\"%s: route type not supported\\n\", __func__);\n\t\tgoto out;\n\t}\n\n\trt->attr.hit = !!(v & BIT(20));\n\trt->attr.dst_null = !!(v & BIT(19));\n\trt->attr.action = (v >> 17) & 3;\n\trt->nh.id = (v >> 6) & 0x7ff;\n\trt->attr.ttl_dec = !!(v & BIT(5));\n\trt->attr.ttl_check = !!(v & BIT(4));\n\trt->attr.qos_as = !!(v & BIT(3));\n\trt->attr.qos_prio =  v & 0x7;\n\tpr_debug(\"%s: index %d is valid: %d\\n\", __func__, idx, rt->attr.valid);\n\tpr_debug(\"%s: next_hop: %d, hit: %d, action :%d, ttl_dec %d, ttl_check %d, dst_null %d\\n\",\n\t\t__func__, rt->nh.id, rt->attr.hit, rt->attr.action, rt->attr.ttl_dec, rt->attr.ttl_check,\n\t\trt->attr.dst_null);\n\tpr_debug(\"%s: Destination: %pI4\\n\", __func__, &rt->dst_ip);\n\nout:\n\trtl_table_release(r);\n}\n\n/*\n * Write a host route entry from the table using its index\n * We currently only support IPv4 and IPv6 unicast route\n */\nstatic void rtl930x_host_route_write(int idx, struct rtl83xx_route *rt)\n{\n\tu32 v;\n\t// Access L3_HOST_ROUTE_IPUC table (1) via register RTL9300_TBL_1\n\tstruct table_reg *r = rtl_table_get(RTL9300_TBL_1, 1);\n\t// The table has a size of 5 (for UC, 11 for MC) registers\n\n\tidx = ((idx / 6) * 8) + (idx % 6);\n\n\tpr_debug(\"%s: index %d is valid: %d\\n\", __func__, idx, rt->attr.valid);\n\tpr_debug(\"%s: next_hop: %d, hit: %d, action :%d, ttl_dec %d, ttl_check %d, dst_null %d\\n\",\n\t\t__func__, rt->nh.id, rt->attr.hit, rt->attr.action, rt->attr.ttl_dec, rt->attr.ttl_check,\n\t\trt->attr.dst_null);\n\tpr_debug(\"%s: GW: %pI4, prefix_len: %d\\n\", __func__, &rt->dst_ip, rt->prefix_len);\n\n\tv = BIT(31); // Entry is valid\n\tv |= (rt->attr.type & 0x3) << 29;\n\tv |= rt->attr.hit ? BIT(20) : 0;\n\tv |= rt->attr.dst_null ? BIT(19) : 0;\n\tv |= (rt->attr.action & 0x3) << 17;\n\tv |= (rt->nh.id & 0x7ff) << 6;\n\tv |= rt->attr.ttl_dec ? BIT(5) : 0;\n\tv |= rt->attr.ttl_check ? BIT(4) : 0;\n\tv |= rt->attr.qos_as ? BIT(3) : 0;\n\tv |= rt->attr.qos_prio & 0x7;\n\n\tsw_w32(v, rtl_table_data(r, 0));\n\tswitch (rt->attr.type) {\n\tcase 0: // IPv4 Unicast route\n\t\tsw_w32(0, rtl_table_data(r, 1));\n\t\tsw_w32(0, rtl_table_data(r, 2));\n\t\tsw_w32(0, rtl_table_data(r, 3));\n\t\tsw_w32(rt->dst_ip, rtl_table_data(r, 4));\n\t\tbreak;\n\tcase 2: // IPv6 Unicast route\n\t\tsw_w32(rt->dst_ip6.s6_addr32[0], rtl_table_data(r, 1));\n\t\tsw_w32(rt->dst_ip6.s6_addr32[1], rtl_table_data(r, 2));\n\t\tsw_w32(rt->dst_ip6.s6_addr32[2], rtl_table_data(r, 3));\n\t\tsw_w32(rt->dst_ip6.s6_addr32[3], rtl_table_data(r, 4));\n\t\tbreak;\n\tcase 1: // IPv4 Multicast route\n\tcase 3: // IPv6 Multicast route\n\t\tpr_warn(\"%s: route type not supported\\n\", __func__);\n\t\tgoto out;\n\t}\n\n\trtl_table_write(r, idx);\n\nout:\n\trtl_table_release(r);\n}\n\n/*\n * Look up the index of a prefix route in the routing table CAM for unicast IPv4/6 routes\n * using hardware offload.\n */\nstatic int rtl930x_route_lookup_hw(struct rtl83xx_route *rt)\n{\n\tu32 ip4_m, v;\n\tstruct in6_addr ip6_m;\n\tint i;\n\n\tif (rt->attr.type == 1 || rt->attr.type == 3) // Hardware only supports UC routes\n\t\treturn -1;\n\n\tsw_w32_mask(0x3 << 19, rt->attr.type, RTL930X_L3_HW_LU_KEY_CTRL);\n\tif (rt->attr.type) { // IPv6\n\t\trtl930x_net6_mask(rt->prefix_len, &ip6_m);\n\t\tfor (i = 0; i < 4; i++)\n\t\t\tsw_w32(rt->dst_ip6.s6_addr32[0] & ip6_m.s6_addr32[0],\n\t\t\t       RTL930X_L3_HW_LU_KEY_IP_CTRL + (i << 2));\n\t} else { // IPv4\n\t\tip4_m = inet_make_mask(rt->prefix_len);\n\t\tsw_w32(0, RTL930X_L3_HW_LU_KEY_IP_CTRL);\n\t\tsw_w32(0, RTL930X_L3_HW_LU_KEY_IP_CTRL + 4);\n\t\tsw_w32(0, RTL930X_L3_HW_LU_KEY_IP_CTRL + 8);\n\t\tv = rt->dst_ip & ip4_m;\n\t\tpr_info(\"%s: searching for %pI4\\n\", __func__, &v);\n\t\tsw_w32(v, RTL930X_L3_HW_LU_KEY_IP_CTRL + 12);\n\t}\n\n\t// Execute CAM lookup in SoC\n\tsw_w32(BIT(15), RTL930X_L3_HW_LU_CTRL);\n\n\t// Wait until execute bit clears and result is ready\n\tdo {\n\t\tv = sw_r32(RTL930X_L3_HW_LU_CTRL);\n\t} while (v & BIT(15));\n\n\tpr_info(\"%s: found: %d, index: %d\\n\", __func__, !!(v & BIT(14)), v & 0x1ff);\n\n\t// Test if search successful (BIT 14 set)\n\tif (v & BIT(14))\n\t\treturn v & 0x1ff;\n\n\treturn -1;\n}\n\nstatic int rtl930x_find_l3_slot(struct rtl83xx_route *rt, bool must_exist)\n{\n\tint t, s, slot_width, algorithm, addr, idx;\n\tu32 hash;\n\tstruct rtl83xx_route route_entry;\n\n\t// IPv6 entries take up 3 slots\n\tslot_width = (rt->attr.type == 0) || (rt->attr.type == 2) ? 1 : 3;\n\n\tfor (t = 0; t < 2; t++) {\n\t\talgorithm = (sw_r32(RTL930X_L3_HOST_TBL_CTRL) >> (2 + t)) & 0x1;\n\t\thash = rtl930x_l3_hash4(rt->dst_ip, algorithm, false);\n\n\t\tpr_debug(\"%s: table %d, algorithm %d, hash %04x\\n\", __func__, t, algorithm, hash);\n\n\t\tfor (s = 0; s < 6; s += slot_width) {\n\t\t\taddr = (t << 12) | ((hash & 0x1ff) << 3) | s;\n\t\t\tpr_debug(\"%s physical address %d\\n\", __func__, addr);\n\t\t\tidx = ((addr / 8) * 6) + (addr % 8);\n\t\t\tpr_debug(\"%s logical address %d\\n\", __func__, idx);\n\n\t\t\trtl930x_host_route_read(idx, &route_entry);\n\t\t\tpr_debug(\"%s route valid %d, route dest: %pI4, hit %d\\n\", __func__,\n\t\t\t\trt->attr.valid, &rt->dst_ip, rt->attr.hit);\n\t\t\tif (!must_exist && rt->attr.valid)\n\t\t\t\treturn idx;\n\t\t\tif (must_exist && route_entry.dst_ip == rt->dst_ip)\n\t\t\t\treturn idx;\n\t\t}\n\t}\n\n\treturn -1;\n}\n\n/*\n * Write a prefix route into the routing table CAM at position idx\n * Currently only IPv4 and IPv6 unicast routes are supported\n */\nstatic void rtl930x_route_write(int idx, struct rtl83xx_route *rt)\n{\n\tu32 v, ip4_m;\n\tstruct in6_addr ip6_m;\n\t// Access L3_PREFIX_ROUTE_IPUC table (2) via register RTL9300_TBL_1\n\t// The table has a size of 11 registers (20 for MC)\n\tstruct table_reg *r = rtl_table_get(RTL9300_TBL_1, 2);\n\n\tpr_debug(\"%s: index %d is valid: %d\\n\", __func__, idx, rt->attr.valid);\n\tpr_debug(\"%s: nexthop: %d, hit: %d, action :%d, ttl_dec %d, ttl_check %d, dst_null %d\\n\",\n\t\t__func__, rt->nh.id, rt->attr.hit, rt->attr.action,\n\t\trt->attr.ttl_dec, rt->attr.ttl_check, rt->attr.dst_null);\n\tpr_debug(\"%s: GW: %pI4, prefix_len: %d\\n\", __func__, &rt->dst_ip, rt->prefix_len);\n\n\tv = rt->attr.valid ? BIT(31) : 0;\n\tv |= (rt->attr.type & 0x3) << 29;\n\tsw_w32(v, rtl_table_data(r, 0));\n\n\tv = rt->attr.hit ? BIT(22) : 0;\n\tv |= (rt->attr.action & 0x3) << 18;\n\tv |= (rt->nh.id & 0x7ff) << 7;\n\tv |= rt->attr.ttl_dec ? BIT(6) : 0;\n\tv |= rt->attr.ttl_check ? BIT(5) : 0;\n\tv |= rt->attr.dst_null ? BIT(6) : 0;\n\tv |= rt->attr.qos_as ? BIT(6) : 0;\n\tv |= rt->attr.qos_prio & 0x7;\n\tv |= rt->prefix_len == 0 ? BIT(20) : 0; // set default route bit\n\n\t// set bit mask for entry type always to 0x3\n\tsw_w32(0x3 << 29, rtl_table_data(r, 5));\n\n\tswitch (rt->attr.type) {\n\tcase 0: // IPv4 Unicast route\n\t\tsw_w32(0, rtl_table_data(r, 1));\n\t\tsw_w32(0, rtl_table_data(r, 2));\n\t\tsw_w32(0, rtl_table_data(r, 3));\n\t\tsw_w32(rt->dst_ip, rtl_table_data(r, 4));\n\n\t\tv |= rt->prefix_len == 32 ? BIT(21) : 0; // set host-route bit\n\t\tip4_m = inet_make_mask(rt->prefix_len);\n\t\tsw_w32(0, rtl_table_data(r, 6));\n\t\tsw_w32(0, rtl_table_data(r, 7));\n\t\tsw_w32(0, rtl_table_data(r, 8));\n\t\tsw_w32(ip4_m, rtl_table_data(r, 9));\n\t\tbreak;\n\tcase 2: // IPv6 Unicast route\n\t\tsw_w32(rt->dst_ip6.s6_addr32[0], rtl_table_data(r, 1));\n\t\tsw_w32(rt->dst_ip6.s6_addr32[1], rtl_table_data(r, 2));\n\t\tsw_w32(rt->dst_ip6.s6_addr32[2], rtl_table_data(r, 3));\n\t\tsw_w32(rt->dst_ip6.s6_addr32[3], rtl_table_data(r, 4));\n\n\t\tv |= rt->prefix_len == 128 ? BIT(21) : 0; // set host-route bit\n\n\t\trtl930x_net6_mask(rt->prefix_len, &ip6_m);\n\n\t\tsw_w32(ip6_m.s6_addr32[0], rtl_table_data(r, 6));\n\t\tsw_w32(ip6_m.s6_addr32[1], rtl_table_data(r, 7));\n\t\tsw_w32(ip6_m.s6_addr32[2], rtl_table_data(r, 8));\n\t\tsw_w32(ip6_m.s6_addr32[3], rtl_table_data(r, 9));\n\t\tbreak;\n\tcase 1: // IPv4 Multicast route\n\tcase 3: // IPv6 Multicast route\n\t\tpr_warn(\"%s: route type not supported\\n\", __func__);\n\t\trtl_table_release(r);\n\t\treturn;\n\t}\n\tsw_w32(v, rtl_table_data(r, 10));\n\n\tpr_debug(\"%s: %08x %08x %08x %08x %08x %08x %08x %08x %08x %08x %08x\\n\", __func__,\n\t\tsw_r32(rtl_table_data(r, 0)), sw_r32(rtl_table_data(r, 1)), sw_r32(rtl_table_data(r, 2)),\n\t\tsw_r32(rtl_table_data(r, 3)), sw_r32(rtl_table_data(r, 4)), sw_r32(rtl_table_data(r, 5)),\n\t\tsw_r32(rtl_table_data(r, 6)), sw_r32(rtl_table_data(r, 7)), sw_r32(rtl_table_data(r, 8)),\n\t\tsw_r32(rtl_table_data(r, 9)), sw_r32(rtl_table_data(r, 10)));\n\n\trtl_table_write(r, idx);\n\trtl_table_release(r);\n}\n\n\n/*\n * Get the destination MAC and L3 egress interface ID of a nexthop entry from\n * the SoC's L3_NEXTHOP table\n */\nstatic void rtl930x_get_l3_nexthop(int idx, u16 *dmac_id, u16 *interface)\n{\n\tu32 v;\n\t// Read L3_NEXTHOP table (3) via register RTL9300_TBL_1\n\tstruct table_reg *r = rtl_table_get(RTL9300_TBL_1, 3);\n\n\trtl_table_read(r, idx);\n\t// The table has a size of 1 register\n\tv = sw_r32(rtl_table_data(r, 0));\n\trtl_table_release(r);\n\n\t*dmac_id = (v >> 7) & 0x7fff;\n\t*interface = v & 0x7f;\n}\n\nstatic int rtl930x_l3_mtu_del(struct rtl838x_switch_priv *priv, int mtu)\n{\n\tint i;\n\n\tfor (i = 0; i < MAX_INTF_MTUS; i++) {\n\t\tif (mtu == priv->intf_mtus[i])\n\t\t\tbreak;\n\t}\n\tif (i >= MAX_INTF_MTUS || !priv->intf_mtu_count[i]) {\n\t\tpr_err(\"%s: No MTU slot found for MTU: %d\\n\", __func__, mtu);\n\t\treturn -EINVAL;\n\t}\n\n\tpriv->intf_mtu_count[i]--;\n}\n\nstatic int rtl930x_l3_mtu_add(struct rtl838x_switch_priv *priv, int mtu)\n{\n\tint i, free_mtu;\n\tint mtu_id;\n\n\t// Try to find an existing mtu-value or a free slot\n\tfree_mtu = MAX_INTF_MTUS;\n\tfor (i = 0; i < MAX_INTF_MTUS && priv->intf_mtus[i] != mtu; i++) {\n\t\tif ((!priv->intf_mtu_count[i]) && (free_mtu == MAX_INTF_MTUS))\n\t\t\tfree_mtu = i;\n\t}\n\ti = (i < MAX_INTF_MTUS) ? i : free_mtu;\n\tif (i < MAX_INTF_MTUS) {\n\t\tmtu_id = i;\n\t} else {\n\t\tpr_err(\"%s: No free MTU slot available!\\n\", __func__);\n\t\treturn -EINVAL;\n\t}\n\n\tpriv->intf_mtus[i] = mtu;\n\tpr_info(\"Writing MTU %d to slot %d\\n\", priv->intf_mtus[i], i);\n\t// Set MTU-value of the slot TODO: distinguish between IPv4/IPv6 routes / slots\n\tsw_w32_mask(0xffff << ((i % 2) * 16), priv->intf_mtus[i] << ((i % 2) * 16),\n\t\t    RTL930X_L3_IP_MTU_CTRL(i));\n\tsw_w32_mask(0xffff << ((i % 2) * 16), priv->intf_mtus[i] << ((i % 2) * 16),\n\t\t    RTL930X_L3_IP6_MTU_CTRL(i));\n\n\tpriv->intf_mtu_count[i]++;\n\n\treturn mtu_id;\n}\n\n/*\n * Creates an interface for a route by setting up the HW tables in the SoC\n */\nstatic int rtl930x_l3_intf_add(struct rtl838x_switch_priv *priv, struct rtl838x_l3_intf *intf)\n{\n\tint i, intf_id, mtu_id;\n\t// number of MTU-values < 16384\n\n\t// Use the same IPv6 mtu as the ip4 mtu for this route if unset\n\tintf->ip6_mtu = intf->ip6_mtu ? intf->ip6_mtu : intf->ip4_mtu;\n\n\tmtu_id = rtl930x_l3_mtu_add(priv, intf->ip4_mtu);\n\tpr_info(\"%s: added mtu %d with mtu-id %d\\n\", __func__, intf->ip4_mtu, mtu_id);\n\tif (mtu_id < 0)\n\t\treturn -ENOSPC;\n\tintf->ip4_mtu_id = mtu_id;\n\tintf->ip6_mtu_id = mtu_id;\n\n\tfor (i = 0; i < MAX_INTERFACES; i++) {\n\t\tif (!priv->interfaces[i])\n\t\t\tbreak;\n\t}\n\tif (i >= MAX_INTERFACES) {\n\t\tpr_err(\"%s: cannot find free interface entry\\n\", __func__);\n\t\treturn -EINVAL;\n\t}\n\tintf_id = i;\n\tpriv->interfaces[i] = kzalloc(sizeof(struct rtl838x_l3_intf), GFP_KERNEL);\n\tif (!priv->interfaces[i]) {\n\t\tpr_err(\"%s: no memory to allocate new interface\\n\", __func__);\n\t\treturn -ENOMEM;\n\t}\n}\n\n/*\n * Set the destination MAC and L3 egress interface ID for a nexthop entry in the SoC's\n * L3_NEXTHOP table. The nexthop entry is identified by idx.\n * dmac_id is the reference to the L2 entry in the L2 forwarding table, special values are\n * 0x7ffe: TRAP2CPU\n * 0x7ffd: TRAP2MASTERCPU\n * 0x7fff: DMAC_ID_DROP\n */\nstatic void rtl930x_set_l3_nexthop(int idx, u16 dmac_id, u16 interface)\n{\n\t// Access L3_NEXTHOP table (3) via register RTL9300_TBL_1\n\tstruct table_reg *r = rtl_table_get(RTL9300_TBL_1, 3);\n\n\tpr_info(\"%s: Writing to L3_NEXTHOP table, index %d, dmac_id %d, interface %d\\n\",\n\t\t__func__, idx, dmac_id, interface);\n\tsw_w32(((dmac_id & 0x7fff) << 7) | (interface & 0x7f), rtl_table_data(r, 0));\n\n\tpr_info(\"%s: %08x\\n\", __func__, sw_r32(rtl_table_data(r,0)));\n\trtl_table_write(r, idx);\n\trtl_table_release(r);\n}\n\nstatic void rtl930x_pie_lookup_enable(struct rtl838x_switch_priv *priv, int index)\n{\n\tint block = index / PIE_BLOCK_SIZE;\n\n\tsw_w32_mask(0, BIT(block), RTL930X_PIE_BLK_LOOKUP_CTRL);\n}\n\n/*\n * Reads the intermediate representation of the templated match-fields of the\n * PIE rule in the pie_rule structure and fills in the raw data fields in the\n * raw register space r[].\n * The register space configuration size is identical for the RTL8380/90 and RTL9300,\n * however the RTL9310 has 2 more registers / fields and the physical field-ids are different\n * on all SoCs\n * On the RTL9300 the mask fields are not word-aligend!\n */\nstatic void rtl930x_write_pie_templated(u32 r[], struct pie_rule *pr, enum template_field_id t[])\n{\n\tint i;\n\tenum template_field_id field_type;\n\tu16 data, data_m;\n\n\tfor (i = 0; i < N_FIXED_FIELDS; i++) {\n\t\tfield_type = t[i];\n\t\tdata = data_m = 0;\n\n\t\tswitch (field_type) {\n\t\tcase TEMPLATE_FIELD_SPM0:\n\t\t\tdata = pr->spm;\n\t\t\tdata_m = pr->spm_m;\n\t\t\tbreak;\n\t\tcase TEMPLATE_FIELD_SPM1:\n\t\t\tdata = pr->spm >> 16;\n\t\t\tdata_m = pr->spm_m >> 16;\n\t\t\tbreak;\n\t\tcase TEMPLATE_FIELD_OTAG:\n\t\t\tdata = pr->otag;\n\t\t\tdata_m = pr->otag_m;\n\t\t\tbreak;\n\t\tcase TEMPLATE_FIELD_SMAC0:\n\t\t\tdata = pr->smac[4];\n\t\t\tdata = (data << 8) | pr->smac[5];\n\t\t\tdata_m = pr->smac_m[4];\n\t\t\tdata_m = (data_m << 8) | pr->smac_m[5];\n\t\t\tbreak;\n\t\tcase TEMPLATE_FIELD_SMAC1:\n\t\t\tdata = pr->smac[2];\n\t\t\tdata = (data << 8) | pr->smac[3];\n\t\t\tdata_m = pr->smac_m[2];\n\t\t\tdata_m = (data_m << 8) | pr->smac_m[3];\n\t\t\tbreak;\n\t\tcase TEMPLATE_FIELD_SMAC2:\n\t\t\tdata = pr->smac[0];\n\t\t\tdata = (data << 8) | pr->smac[1];\n\t\t\tdata_m = pr->smac_m[0];\n\t\t\tdata_m = (data_m << 8) | pr->smac_m[1];\n\t\t\tbreak;\n\t\tcase TEMPLATE_FIELD_DMAC0:\n\t\t\tdata = pr->dmac[4];\n\t\t\tdata = (data << 8) | pr->dmac[5];\n\t\t\tdata_m = pr->dmac_m[4];\n\t\t\tdata_m = (data_m << 8) | pr->dmac_m[5];\n\t\t\tbreak;\n\t\tcase TEMPLATE_FIELD_DMAC1:\n\t\t\tdata = pr->dmac[2];\n\t\t\tdata = (data << 8) | pr->dmac[3];\n\t\t\tdata_m = pr->dmac_m[2];\n\t\t\tdata_m = (data_m << 8) | pr->dmac_m[3];\n\t\t\tbreak;\n\t\tcase TEMPLATE_FIELD_DMAC2:\n\t\t\tdata = pr->dmac[0];\n\t\t\tdata = (data << 8) | pr->dmac[1];\n\t\t\tdata_m = pr->dmac_m[0];\n\t\t\tdata_m = (data_m << 8) | pr->dmac_m[1];\n\t\t\tbreak;\n\t\tcase TEMPLATE_FIELD_ETHERTYPE:\n\t\t\tdata = pr->ethertype;\n\t\t\tdata_m = pr->ethertype_m;\n\t\t\tbreak;\n\t\tcase TEMPLATE_FIELD_ITAG:\n\t\t\tdata = pr->itag;\n\t\t\tdata_m = pr->itag_m;\n\t\t\tbreak;\n\t\tcase TEMPLATE_FIELD_SIP0:\n\t\t\tif (pr->is_ipv6) {\n\t\t\t\tdata = pr->sip6.s6_addr16[7];\n\t\t\t\tdata_m = pr->sip6_m.s6_addr16[7];\n\t\t\t} else {\n\t\t\t\tdata = pr->sip;\n\t\t\t\tdata_m = pr->sip_m;\n\t\t\t}\n\t\t\tbreak;\n\t\tcase TEMPLATE_FIELD_SIP1:\n\t\t\tif (pr->is_ipv6) {\n\t\t\t\tdata = pr->sip6.s6_addr16[6];\n\t\t\t\tdata_m = pr->sip6_m.s6_addr16[6];\n\t\t\t} else {\n\t\t\t\tdata = pr->sip >> 16;\n\t\t\t\tdata_m = pr->sip_m >> 16;\n\t\t\t}\n\t\t\tbreak;\n\n\t\tcase TEMPLATE_FIELD_SIP2:\n\t\tcase TEMPLATE_FIELD_SIP3:\n\t\tcase TEMPLATE_FIELD_SIP4:\n\t\tcase TEMPLATE_FIELD_SIP5:\n\t\tcase TEMPLATE_FIELD_SIP6:\n\t\tcase TEMPLATE_FIELD_SIP7:\n\t\t\tdata = pr->sip6.s6_addr16[5 - (field_type - TEMPLATE_FIELD_SIP2)];\n\t\t\tdata_m = pr->sip6_m.s6_addr16[5 - (field_type - TEMPLATE_FIELD_SIP2)];\n\t\t\tbreak;\n\n\t\tcase TEMPLATE_FIELD_DIP0:\n\t\t\tif (pr->is_ipv6) {\n\t\t\t\tdata = pr->dip6.s6_addr16[7];\n\t\t\t\tdata_m = pr->dip6_m.s6_addr16[7];\n\t\t\t} else {\n\t\t\t\tdata = pr->dip;\n\t\t\t\tdata_m = pr->dip_m;\n\t\t\t}\n\t\t\tbreak;\n\n\t\tcase TEMPLATE_FIELD_DIP1:\n\t\t\tif (pr->is_ipv6) {\n\t\t\t\tdata = pr->dip6.s6_addr16[6];\n\t\t\t\tdata_m = pr->dip6_m.s6_addr16[6];\n\t\t\t} else {\n\t\t\t\tdata = pr->dip >> 16;\n\t\t\t\tdata_m = pr->dip_m >> 16;\n\t\t\t}\n\t\t\tbreak;\n\n\t\tcase TEMPLATE_FIELD_DIP2:\n\t\tcase TEMPLATE_FIELD_DIP3:\n\t\tcase TEMPLATE_FIELD_DIP4:\n\t\tcase TEMPLATE_FIELD_DIP5:\n\t\tcase TEMPLATE_FIELD_DIP6:\n\t\tcase TEMPLATE_FIELD_DIP7:\n\t\t\tdata = pr->dip6.s6_addr16[5 - (field_type - TEMPLATE_FIELD_DIP2)];\n\t\t\tdata_m = pr->dip6_m.s6_addr16[5 - (field_type - TEMPLATE_FIELD_DIP2)];\n\t\t\tbreak;\n\n\t\tcase TEMPLATE_FIELD_IP_TOS_PROTO:\n\t\t\tdata = pr->tos_proto;\n\t\t\tdata_m = pr->tos_proto_m;\n\t\t\tbreak;\n\t\tcase TEMPLATE_FIELD_L4_SPORT:\n\t\t\tdata = pr->sport;\n\t\t\tdata_m = pr->sport_m;\n\t\t\tbreak;\n\t\tcase TEMPLATE_FIELD_L4_DPORT:\n\t\t\tdata = pr->dport;\n\t\t\tdata_m = pr->dport_m;\n\t\t\tbreak;\n\t\tcase TEMPLATE_FIELD_DSAP_SSAP:\n\t\t\tdata = pr->dsap_ssap;\n\t\t\tdata_m = pr->dsap_ssap_m;\n\t\t\tbreak;\n\t\tcase TEMPLATE_FIELD_TCP_INFO:\n\t\t\tdata = pr->tcp_info;\n\t\t\tdata_m = pr->tcp_info_m;\n\t\t\tbreak;\n\t\tcase TEMPLATE_FIELD_RANGE_CHK:\n\t\t\tpr_warn(\"Warning: TEMPLATE_FIELD_RANGE_CHK: not configured\\n\");\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tpr_info(\"%s: unknown field %d\\n\", __func__, field_type);\n\t\t}\n\n\t\t// On the RTL9300, the mask fields are not word aligned!\n\t\tif (!(i % 2)) {\n\t\t\tr[5 - i / 2] = data;\n\t\t\tr[12 - i / 2] |= ((u32)data_m << 8);\n\t\t} else {\n\t\t\tr[5 - i / 2] |= ((u32)data) << 16;\n\t\t\tr[12 - i / 2] |= ((u32)data_m) << 24;\n\t\t\tr[11 - i / 2] |= ((u32)data_m) >> 8;\n\t\t}\n\t}\n}\n\nstatic void rtl930x_read_pie_fixed_fields(u32 r[], struct pie_rule *pr)\n{\n\tpr->stacking_port = r[6] & BIT(31);\n\tpr->spn = (r[6] >> 24) & 0x7f;\n\tpr->mgnt_vlan = r[6] & BIT(23);\n\tif (pr->phase == PHASE_IACL)\n\t\tpr->dmac_hit_sw = r[6] & BIT(22);\n\telse\n\t\tpr->content_too_deep = r[6] & BIT(22);\n\tpr->not_first_frag = r[6]  & BIT(21);\n\tpr->frame_type_l4 = (r[6] >> 18) & 7;\n\tpr->frame_type = (r[6] >> 16) & 3;\n\tpr->otag_fmt = (r[6] >> 15) & 1;\n\tpr->itag_fmt = (r[6] >> 14) & 1;\n\tpr->otag_exist = (r[6] >> 13) & 1;\n\tpr->itag_exist = (r[6] >> 12) & 1;\n\tpr->frame_type_l2 = (r[6] >> 10) & 3;\n\tpr->igr_normal_port = (r[6] >> 9) & 1;\n\tpr->tid = (r[6] >> 8) & 1;\n\n\tpr->stacking_port_m = r[12] & BIT(7);\n\tpr->spn_m = r[12]  & 0x7f;\n\tpr->mgnt_vlan_m = r[13] & BIT(31);\n\tif (pr->phase == PHASE_IACL)\n\t\tpr->dmac_hit_sw_m = r[13] & BIT(30);\n\telse\n\t\tpr->content_too_deep_m = r[13] & BIT(30);\n\tpr->not_first_frag_m = r[13] & BIT(29);\n\tpr->frame_type_l4_m = (r[13] >> 26) & 7;\n\tpr->frame_type_m = (r[13] >> 24) & 3;\n\tpr->otag_fmt_m = r[13] & BIT(23);\n\tpr->itag_fmt_m = r[13] & BIT(22);\n\tpr->otag_exist_m = r[13] & BIT(21);\n\tpr->itag_exist_m = r[13] & BIT (20);\n\tpr->frame_type_l2_m = (r[13] >> 18) & 3;\n\tpr->igr_normal_port_m = r[13] & BIT(17);\n\tpr->tid_m = (r[13] >> 16) & 1;\n\n\tpr->valid = r[13] & BIT(15);\n\tpr->cond_not = r[13] & BIT(14);\n\tpr->cond_and1 = r[13] & BIT(13);\n\tpr->cond_and2 = r[13] & BIT(12);\n}\n\nstatic void rtl930x_write_pie_fixed_fields(u32 r[],  struct pie_rule *pr)\n{\n\tr[6] = pr->stacking_port ? BIT(31) : 0;\n\tr[6] |= ((u32) (pr->spn & 0x7f)) << 24;\n\tr[6] |= pr->mgnt_vlan ? BIT(23) : 0;\n\tif (pr->phase == PHASE_IACL)\n\t\tr[6] |= pr->dmac_hit_sw ? BIT(22) : 0;\n\telse\n\t\tr[6] |= pr->content_too_deep ? BIT(22) : 0;\n\tr[6] |= pr->not_first_frag ? BIT(21) : 0;\n\tr[6] |= ((u32) (pr->frame_type_l4 & 0x7)) << 18;\n\tr[6] |= ((u32) (pr->frame_type & 0x3)) << 16;\n\tr[6] |= pr->otag_fmt ? BIT(15) : 0;\n\tr[6] |= pr->itag_fmt ? BIT(14) : 0;\n\tr[6] |= pr->otag_exist ? BIT(13) : 0;\n\tr[6] |= pr->itag_exist ? BIT(12) : 0;\n\tr[6] |= ((u32) (pr->frame_type_l2 & 0x3)) << 10;\n\tr[6] |= pr->igr_normal_port ? BIT(9) : 0;\n\tr[6] |= ((u32) (pr->tid & 0x1)) << 8;\n\n\tr[12] |= pr->stacking_port_m ? BIT(7) : 0;\n\tr[12] |= (u32) (pr->spn_m & 0x7f);\n\tr[13] |= pr->mgnt_vlan_m ? BIT(31) : 0;\n\tif (pr->phase == PHASE_IACL)\n\t\tr[13] |= pr->dmac_hit_sw_m ? BIT(30) : 0;\n\telse\n\t\tr[13] |= pr->content_too_deep_m ? BIT(30) : 0;\n\tr[13] |= pr->not_first_frag_m ? BIT(29) : 0;\n\tr[13] |= ((u32) (pr->frame_type_l4_m & 0x7)) << 26;\n\tr[13] |= ((u32) (pr->frame_type_m & 0x3)) << 24;\n\tr[13] |= pr->otag_fmt_m ? BIT(23) : 0;\n\tr[13] |= pr->itag_fmt_m ? BIT(22) : 0;\n\tr[13] |= pr->otag_exist_m ? BIT(21) : 0;\n\tr[13] |= pr->itag_exist_m ? BIT(20) : 0;\n\tr[13] |= ((u32) (pr->frame_type_l2_m & 0x3)) << 18;\n\tr[13] |= pr->igr_normal_port_m ? BIT(17) : 0;\n\tr[13] |= ((u32) (pr->tid_m & 0x1)) << 16;\n\n\tr[13] |= pr->valid ? BIT(15) : 0;\n\tr[13] |= pr->cond_not ? BIT(14) : 0;\n\tr[13] |= pr->cond_and1 ? BIT(13) : 0;\n\tr[13] |= pr->cond_and2 ? BIT(12) : 0;\n}\n\nstatic void rtl930x_write_pie_action(u32 r[],  struct pie_rule *pr)\n{\n\t// Either drop or forward\n\tif (pr->drop) {\n\t\tr[14] |= BIT(24) | BIT(25) | BIT(26); // Do Green, Yellow and Red drops\n\t\t// Actually DROP, not PERMIT in Green / Yellow / Red\n\t\tr[14] |= BIT(23) | BIT(22) | BIT(20);\n\t} else {\n\t\tr[14] |= pr->fwd_sel ? BIT(27) : 0;\n\t\tr[14] |= pr->fwd_act << 18;\n\t\tr[14] |= BIT(14); // We overwrite any drop\n\t}\n\tif (pr->phase == PHASE_VACL)\n\t\tr[14] |= pr->fwd_sa_lrn ? BIT(15) : 0;\n\tr[13] |= pr->bypass_sel ? BIT(5) : 0;\n\tr[13] |= pr->nopri_sel ? BIT(4) : 0;\n\tr[13] |= pr->tagst_sel ? BIT(3) : 0;\n\tr[13] |= pr->ovid_sel ? BIT(1) : 0;\n\tr[14] |= pr->ivid_sel ? BIT(31) : 0;\n\tr[14] |= pr->meter_sel ? BIT(30) : 0;\n\tr[14] |= pr->mir_sel ? BIT(29) : 0;\n\tr[14] |= pr->log_sel ? BIT(28) : 0;\n\n\tr[14] |= ((u32)(pr->fwd_data & 0x3fff)) << 3;\n\tr[15] |= pr->log_octets ? BIT(31) : 0;\n\tr[15] |= (u32)(pr->meter_data) << 23;\n\n\tr[15] |= ((u32)(pr->ivid_act) << 21) & 0x3;\n\tr[15] |= ((u32)(pr->ivid_data) << 9) & 0xfff;\n\tr[16] |= ((u32)(pr->ovid_act) << 30) & 0x3;\n\tr[16] |= ((u32)(pr->ovid_data) & 0xfff) << 16;\n\tr[16] |= (pr->mir_data & 0x3) << 6;\n\tr[17] |= ((u32)(pr->tagst_data) & 0xf) << 28;\n\tr[17] |= ((u32)(pr->nopri_data) & 0x7) << 25;\n\tr[17] |= pr->bypass_ibc_sc ? BIT(16) : 0;\n}\n\nvoid rtl930x_pie_rule_dump_raw(u32 r[])\n{\n\tpr_info(\"Raw IACL table entry:\\n\");\n\tpr_info(\"r 0 - 7: %08x %08x %08x %08x %08x %08x %08x %08x\\n\",\n\t\tr[0], r[1], r[2], r[3], r[4], r[5], r[6], r[7]);\n\tpr_info(\"r 8 - 15: %08x %08x %08x %08x %08x %08x %08x %08x\\n\",\n\t\tr[8], r[9], r[10], r[11], r[12], r[13], r[14], r[15]);\n\tpr_info(\"r 16 - 18: %08x %08x %08x\\n\", r[16], r[17], r[18]);\n\tpr_info(\"Match  : %08x %08x %08x %08x %08x %08x\\n\", r[0], r[1], r[2], r[3], r[4], r[5]);\n\tpr_info(\"Fixed  : %06x\\n\", r[6] >> 8);\n\tpr_info(\"Match M: %08x %08x %08x %08x %08x %08x\\n\",\n\t\t(r[6] << 24) | (r[7] >> 8), (r[7] << 24) | (r[8] >> 8), (r[8] << 24) | (r[9] >> 8),\n\t\t(r[9] << 24) | (r[10] >> 8), (r[10] << 24) | (r[11] >> 8),\n\t\t(r[11] << 24) | (r[12] >> 8));\n\tpr_info(\"R[13]:   %08x\\n\", r[13]);\n\tpr_info(\"Fixed M: %06x\\n\", ((r[12] << 16) | (r[13] >> 16)) & 0xffffff);\n\tpr_info(\"Valid / not / and1 / and2 : %1x\\n\", (r[13] >> 12) & 0xf);\n\tpr_info(\"r 13-16: %08x %08x %08x %08x\\n\", r[13], r[14], r[15], r[16]);\n}\n\nstatic int rtl930x_pie_rule_write(struct rtl838x_switch_priv *priv, int idx, struct pie_rule *pr)\n{\n\t// Access IACL table (2) via register 0\n\tstruct table_reg *q = rtl_table_get(RTL9300_TBL_0, 2);\n\tu32 r[19];\n\tint i;\n\tint block = idx / PIE_BLOCK_SIZE;\n\tu32 t_select = sw_r32(RTL930X_PIE_BLK_TMPLTE_CTRL(block));\n\n\tpr_debug(\"%s: %d, t_select: %08x\\n\", __func__, idx, t_select);\n\n\tfor (i = 0; i < 19; i++)\n\t\tr[i] = 0;\n\n\tif (!pr->valid) {\n\t\trtl_table_write(q, idx);\n\t\trtl_table_release(q);\n\t\treturn 0;\n\t}\n\trtl930x_write_pie_fixed_fields(r, pr);\n\n\tpr_debug(\"%s: template %d\\n\", __func__, (t_select >> (pr->tid * 4)) & 0xf);\n\trtl930x_write_pie_templated(r, pr, fixed_templates[(t_select >> (pr->tid * 4)) & 0xf]);\n\n\trtl930x_write_pie_action(r, pr);\n\n//\trtl930x_pie_rule_dump_raw(r);\n\n\tfor (i = 0; i < 19; i++)\n\t\tsw_w32(r[i], rtl_table_data(q, i));\n\n\trtl_table_write(q, idx);\n\trtl_table_release(q);\n\n\treturn 0;\n}\n\nstatic bool rtl930x_pie_templ_has(int t, enum template_field_id field_type)\n{\n\tint i;\n\tenum template_field_id ft;\n\n\tfor (i = 0; i < N_FIXED_FIELDS; i++) {\n\t\tft = fixed_templates[t][i];\n\t\tif (field_type == ft)\n\t\t\treturn true;\n\t}\n\n\treturn false;\n}\n\n/*\n * Verify that the rule pr is compatible with a given template t in block block\n * Note that this function is SoC specific since the values of e.g. TEMPLATE_FIELD_SIP0\n * depend on the SoC\n */\nstatic int rtl930x_pie_verify_template(struct rtl838x_switch_priv *priv,\n\t\t\t\t       struct pie_rule *pr, int t, int block)\n{\n\tint i;\n\n\tif (!pr->is_ipv6 && pr->sip_m && !rtl930x_pie_templ_has(t, TEMPLATE_FIELD_SIP0))\n\t\treturn -1;\n\n\tif (!pr->is_ipv6 && pr->dip_m && !rtl930x_pie_templ_has(t, TEMPLATE_FIELD_DIP0))\n\t\treturn -1;\n\n\tif (pr->is_ipv6) {\n\t\tif ((pr->sip6_m.s6_addr32[0] || pr->sip6_m.s6_addr32[1]\n\t\t\t|| pr->sip6_m.s6_addr32[2] || pr->sip6_m.s6_addr32[3])\n\t\t\t&& !rtl930x_pie_templ_has(t, TEMPLATE_FIELD_SIP2))\n\t\t\treturn -1;\n\t\tif ((pr->dip6_m.s6_addr32[0] || pr->dip6_m.s6_addr32[1]\n\t\t\t|| pr->dip6_m.s6_addr32[2] || pr->dip6_m.s6_addr32[3])\n\t\t\t&& !rtl930x_pie_templ_has(t, TEMPLATE_FIELD_DIP2))\n\t\t\treturn -1;\n\t}\n\n\tif (ether_addr_to_u64(pr->smac) && !rtl930x_pie_templ_has(t, TEMPLATE_FIELD_SMAC0))\n\t\treturn -1;\n\n\tif (ether_addr_to_u64(pr->dmac) && !rtl930x_pie_templ_has(t, TEMPLATE_FIELD_DMAC0))\n\t\treturn -1;\n\n\t// TODO: Check more\n\n\ti = find_first_zero_bit(&priv->pie_use_bm[block * 4], PIE_BLOCK_SIZE);\n\n\tif (i >= PIE_BLOCK_SIZE)\n\t\treturn -1;\n\n\treturn i + PIE_BLOCK_SIZE * block;\n}\n\nstatic int rtl930x_pie_rule_add(struct rtl838x_switch_priv *priv, struct pie_rule *pr)\n{\n\tint idx, block, j, t;\n\tint min_block = 0;\n\tint max_block = priv->n_pie_blocks / 2;\n\n\tif (pr->is_egress) {\n\t\tmin_block = max_block;\n\t\tmax_block = priv->n_pie_blocks;\n\t}\n\tpr_debug(\"In %s\\n\", __func__);\n\n\tmutex_lock(&priv->pie_mutex);\n\n\tfor (block = min_block; block < max_block; block++) {\n\t\tfor (j = 0; j < 2; j++) {\n\t\t\tt = (sw_r32(RTL930X_PIE_BLK_TMPLTE_CTRL(block)) >> (j * 4)) & 0xf;\n\t\t\tpr_debug(\"Testing block %d, template %d, template id %d\\n\", block, j, t);\n\t\t\tpr_debug(\"%s: %08x\\n\",\n\t\t\t\t__func__, sw_r32(RTL930X_PIE_BLK_TMPLTE_CTRL(block)));\n\t\t\tidx = rtl930x_pie_verify_template(priv, pr, t, block);\n\t\t\tif (idx >= 0)\n\t\t\t\tbreak;\n\t\t}\n\t\tif (j < 2)\n\t\t\tbreak;\n\t}\n\n\tif (block >= priv->n_pie_blocks) {\n\t\tmutex_unlock(&priv->pie_mutex);\n\t\treturn -EOPNOTSUPP;\n\t}\n\n\tpr_debug(\"Using block: %d, index %d, template-id %d\\n\", block, idx, j);\n\tset_bit(idx, priv->pie_use_bm);\n\n\tpr->valid = true;\n\tpr->tid = j;  // Mapped to template number\n\tpr->tid_m = 0x1;\n\tpr->id = idx;\n\n\trtl930x_pie_lookup_enable(priv, idx);\n\trtl930x_pie_rule_write(priv, idx, pr);\n\n\tmutex_unlock(&priv->pie_mutex);\n\treturn 0;\n}\n\n/*\n * Delete a range of Packet Inspection Engine rules\n */\nstatic int rtl930x_pie_rule_del(struct rtl838x_switch_priv *priv, int index_from, int index_to)\n{\n\tu32 v = (index_from << 1)| (index_to << 12 ) | BIT(0);\n\n\tpr_debug(\"%s: from %d to %d\\n\", __func__, index_from, index_to);\n\tmutex_lock(&priv->reg_mutex);\n\n\t// Write from-to and execute bit into control register\n\tsw_w32(v, RTL930X_PIE_CLR_CTRL);\n\n\t// Wait until command has completed\n\tdo {\n\t} while (sw_r32(RTL930X_PIE_CLR_CTRL) & BIT(0));\n\n\tmutex_unlock(&priv->reg_mutex);\n\treturn 0;\n}\n\nstatic void rtl930x_pie_rule_rm(struct rtl838x_switch_priv *priv, struct pie_rule *pr)\n{\n\tint idx = pr->id;\n\n\trtl930x_pie_rule_del(priv, idx, idx);\n\tclear_bit(idx, priv->pie_use_bm);\n}\n\nstatic void rtl930x_pie_init(struct rtl838x_switch_priv *priv)\n{\n\tint i;\n\tu32 template_selectors;\n\n\tmutex_init(&priv->pie_mutex);\n\n\tpr_info(\"%s\\n\", __func__);\n\t// Enable ACL lookup on all ports, including CPU_PORT\n\tfor (i = 0; i <= priv->cpu_port; i++)\n\t\tsw_w32(1, RTL930X_ACL_PORT_LOOKUP_CTRL(i));\n\n\t// Include IPG in metering\n\tsw_w32_mask(0, 1, RTL930X_METER_GLB_CTRL);\n\n\t// Delete all present rules, block size is 128 on all SoC families\n\trtl930x_pie_rule_del(priv, 0, priv->n_pie_blocks * 128 - 1);\n\n\t// Assign blocks 0-7 to VACL phase (bit = 0), blocks 8-15 to IACL (bit = 1)\n\tsw_w32(0xff00, RTL930X_PIE_BLK_PHASE_CTRL);\n\t\n\t// Enable predefined templates 0, 1 for first quarter of all blocks\n\ttemplate_selectors = 0 | (1 << 4);\n\tfor (i = 0; i < priv->n_pie_blocks / 4; i++)\n\t\tsw_w32(template_selectors, RTL930X_PIE_BLK_TMPLTE_CTRL(i));\n\n\t// Enable predefined templates 2, 3 for second quarter of all blocks\n\ttemplate_selectors = 2 | (3 << 4);\n\tfor (i = priv->n_pie_blocks / 4; i < priv->n_pie_blocks / 2; i++)\n\t\tsw_w32(template_selectors, RTL930X_PIE_BLK_TMPLTE_CTRL(i));\n\n\t// Enable predefined templates 0, 1 for third half of all blocks\n\ttemplate_selectors = 0 | (1 << 4);\n\tfor (i = priv->n_pie_blocks / 2; i < priv->n_pie_blocks * 3 / 4; i++)\n\t\tsw_w32(template_selectors, RTL930X_PIE_BLK_TMPLTE_CTRL(i));\n\n\t// Enable predefined templates 2, 3 for fourth quater of all blocks\n\ttemplate_selectors = 2 | (3 << 4);\n\tfor (i = priv->n_pie_blocks * 3 / 4; i < priv->n_pie_blocks; i++)\n\t\tsw_w32(template_selectors, RTL930X_PIE_BLK_TMPLTE_CTRL(i));\n\n}\n\n/*\n * Sets up an egress interface for L3 actions\n * Actions for ip4/6_icmp_redirect, ip4/6_pbr_icmp_redirect are:\n * 0: FORWARD, 1: DROP, 2: TRAP2CPU, 3: COPY2CPU, 4: TRAP2MASTERCPU 5: COPY2MASTERCPU\n * 6: HARDDROP\n * idx is the index in the HW interface table: idx < 0x80\n */\nstatic void rtl930x_set_l3_egress_intf(int idx, struct rtl838x_l3_intf *intf)\n{\n\tu32 u, v;\n\t// Read L3_EGR_INTF table (4) via register RTL9300_TBL_1\n\tstruct table_reg *r = rtl_table_get(RTL9300_TBL_1, 4);\n\n\t// The table has 2 registers\n\tu = (intf->vid & 0xfff) << 9;\n\tu |= (intf->smac_idx & 0x3f) << 3;\n\tu |= (intf->ip4_mtu_id & 0x7);\n\n\tv = (intf->ip6_mtu_id & 0x7) << 28;\n\tv |= (intf->ttl_scope & 0xff) << 20;\n\tv |= (intf->hl_scope & 0xff) << 12;\n\tv |= (intf->ip4_icmp_redirect & 0x7) << 9;\n\tv |= (intf->ip6_icmp_redirect & 0x7)<< 6;\n\tv |= (intf->ip4_pbr_icmp_redirect & 0x7) << 3;\n\tv |= (intf->ip6_pbr_icmp_redirect & 0x7);\n\n\tsw_w32(u, rtl_table_data(r, 0));\n\tsw_w32(v, rtl_table_data(r, 1));\n\n\tpr_info(\"%s writing to index %d: %08x %08x\\n\", __func__, idx, u, v);\n\trtl_table_write(r, idx & 0x7f);\n\trtl_table_release(r);\n}\n\n/*\n * Reads a MAC entry for L3 termination as entry point for routing\n * from the hardware table\n * idx is the index into the L3_ROUTER_MAC table\n */\nstatic void rtl930x_get_l3_router_mac(u32 idx, struct rtl93xx_rt_mac *m)\n{\n\tu32 v, w;\n\t// Read L3_ROUTER_MAC table (0) via register RTL9300_TBL_1\n\tstruct table_reg *r = rtl_table_get(RTL9300_TBL_1, 0);\n\n\trtl_table_read(r, idx);\n\t// The table has a size of 7 registers, 64 entries\n\tv = sw_r32(rtl_table_data(r, 0));\n\tw = sw_r32(rtl_table_data(r, 3));\n\tm->valid = !!(v & BIT(20));\n\tif (!m->valid)\n\t\tgoto out;\n\n\tm->p_type = !!(v & BIT(19));\n\tm->p_id = (v >> 13) & 0x3f;  // trunk id of port\n\tm->vid = v & 0xfff;\n\tm->vid_mask = w & 0xfff;\n\tm->action = sw_r32(rtl_table_data(r, 6)) & 0x7;\n\tm->mac_mask = ((((u64)sw_r32(rtl_table_data(r, 5))) << 32) & 0xffffffffffffULL)\n\t\t\t| (sw_r32(rtl_table_data(r, 4)));\n\tm->mac = ((((u64)sw_r32(rtl_table_data(r, 1))) << 32) & 0xffffffffffffULL)\n\t\t\t| (sw_r32(rtl_table_data(r, 2)));\n\t// Bits L3_INTF and BMSK_L3_INTF are 0\n\nout:\n\trtl_table_release(r);\n}\n\n/*\n * Writes a MAC entry for L3 termination as entry point for routing\n * into the hardware table\n * idx is the index into the L3_ROUTER_MAC table\n */\nstatic void rtl930x_set_l3_router_mac(u32 idx, struct rtl93xx_rt_mac *m)\n{\n\tu32 v, w;\n\t// Read L3_ROUTER_MAC table (0) via register RTL9300_TBL_1\n\tstruct table_reg *r = rtl_table_get(RTL9300_TBL_1, 0);\n\n\t// The table has a size of 7 registers, 64 entries\n\tv = BIT(20); // mac entry valid, port type is 0: individual\n\tv |= (m->p_id & 0x3f) << 13;\n\tv |= (m->vid & 0xfff); // Set the interface_id to the vlan id\n\n\tw = m->vid_mask;\n\tw |= (m->p_id_mask & 0x3f) << 13;\n\n\tsw_w32(v, rtl_table_data(r, 0));\n\tsw_w32(w, rtl_table_data(r, 3));\n\n\t// Set MAC address, L3_INTF (bit 12 in register 1) needs to be 0\n\tsw_w32((u32)(m->mac), rtl_table_data(r, 2));\n\tsw_w32(m->mac >> 32, rtl_table_data(r, 1));\n\n\t// Set MAC address mask, BMSK_L3_INTF (bit 12 in register 5) needs to be 0\n\tsw_w32((u32)(m->mac_mask >> 32), rtl_table_data(r, 4));\n\tsw_w32((u32)m->mac_mask, rtl_table_data(r, 5));\n\n\tsw_w32(m->action & 0x7, rtl_table_data(r, 6));\n\n\tpr_debug(\"%s writing index %d: %08x %08x %08x %08x %08x %08x %08x\\n\", __func__, idx,\n\t\tsw_r32(rtl_table_data(r, 0)), sw_r32(rtl_table_data(r, 1)), sw_r32(rtl_table_data(r, 2)),\n\t\tsw_r32(rtl_table_data(r, 3)), sw_r32(rtl_table_data(r, 4)), sw_r32(rtl_table_data(r, 5)),\n\t\tsw_r32(rtl_table_data(r, 6))\n\t);\n\trtl_table_write(r, idx);\n\trtl_table_release(r);\n}\n\n/*\n * Get the Destination-MAC of an L3 egress interface or the Source MAC for routed packets\n * from the SoC's L3_EGR_INTF_MAC table\n * Indexes 0-2047 are DMACs, 2048+ are SMACs\n */\nstatic u64 rtl930x_get_l3_egress_mac(u32 idx)\n{\n\tu64 mac;\n\t// Read L3_EGR_INTF_MAC table (2) via register RTL9300_TBL_2\n\tstruct table_reg *r = rtl_table_get(RTL9300_TBL_2, 2);\n\n\trtl_table_read(r, idx);\n\t// The table has a size of 2 registers\n\tmac = sw_r32(rtl_table_data(r, 0));\n\tmac <<= 32;\n\tmac |= sw_r32(rtl_table_data(r, 1));\n\trtl_table_release(r);\n\n\treturn mac;\n}\n/*\n * Set the Destination-MAC of a route or the Source MAC of an L3 egress interface\n * in the SoC's L3_EGR_INTF_MAC table\n * Indexes 0-2047 are DMACs, 2048+ are SMACs\n */\nstatic void rtl930x_set_l3_egress_mac(u32 idx, u64 mac)\n{\n\t// Access L3_EGR_INTF_MAC table (2) via register RTL9300_TBL_2\n\tstruct table_reg *r = rtl_table_get(RTL9300_TBL_2, 2);\n\n\t// The table has a size of 2 registers\n\tsw_w32(mac >> 32, rtl_table_data(r, 0));\n\tsw_w32(mac, rtl_table_data(r, 1));\n\n\tpr_debug(\"%s: setting index %d to %016llx\\n\", __func__, idx, mac);\n\trtl_table_write(r, idx);\n\trtl_table_release(r);\n}\n\n/*\n * Configure L3 routing settings of the device:\n * - MTUs\n * - Egress interface\n * - The router's MAC address on which routed packets are expected\n * - MAC addresses used as source macs of routed packets\n */\nint rtl930x_l3_setup(struct rtl838x_switch_priv *priv)\n{\n\tint i;\n\n\t// Setup MTU with id 0 for default interface\n\tfor (i = 0; i < MAX_INTF_MTUS; i++)\n\t\tpriv->intf_mtu_count[i] = priv->intf_mtus[i] = 0;\n\n\tpriv->intf_mtu_count[0] = 0; // Needs to stay forever\n\tpriv->intf_mtus[0] = DEFAULT_MTU;\n\tsw_w32_mask(0xffff, DEFAULT_MTU, RTL930X_L3_IP_MTU_CTRL(0));\n\tsw_w32_mask(0xffff, DEFAULT_MTU, RTL930X_L3_IP6_MTU_CTRL(0));\n\tpriv->intf_mtus[1] = DEFAULT_MTU;\n\tsw_w32_mask(0xffff0000, DEFAULT_MTU << 16, RTL930X_L3_IP_MTU_CTRL(0));\n\tsw_w32_mask(0xffff0000, DEFAULT_MTU << 16, RTL930X_L3_IP6_MTU_CTRL(0));\n\n\tsw_w32_mask(0xffff, DEFAULT_MTU, RTL930X_L3_IP_MTU_CTRL(1));\n\tsw_w32_mask(0xffff, DEFAULT_MTU, RTL930X_L3_IP6_MTU_CTRL(1));\n\tsw_w32_mask(0xffff0000, DEFAULT_MTU << 16, RTL930X_L3_IP_MTU_CTRL(1));\n\tsw_w32_mask(0xffff0000, DEFAULT_MTU << 16, RTL930X_L3_IP6_MTU_CTRL(1));\n\n\t// Clear all source port MACs\n\tfor (i = 0; i < MAX_SMACS; i++)\n\t\trtl930x_set_l3_egress_mac(L3_EGRESS_DMACS + i, 0ULL);\n\n\t// Configure the default L3 hash algorithm\n\tsw_w32_mask(BIT(2), 0, RTL930X_L3_HOST_TBL_CTRL);  // Algorithm selection 0 = 0\n\tsw_w32_mask(0, BIT(3), RTL930X_L3_HOST_TBL_CTRL);  // Algorithm selection 1 = 1\n\n\tpr_info(\"L3_IPUC_ROUTE_CTRL %08x, IPMC_ROUTE %08x, IP6UC_ROUTE %08x, IP6MC_ROUTE %08x\\n\",\n\t\tsw_r32(RTL930X_L3_IPUC_ROUTE_CTRL), sw_r32(RTL930X_L3_IPMC_ROUTE_CTRL),\n\t\tsw_r32(RTL930X_L3_IP6UC_ROUTE_CTRL), sw_r32(RTL930X_L3_IP6MC_ROUTE_CTRL));\n\tsw_w32_mask(0, 1, RTL930X_L3_IPUC_ROUTE_CTRL);\n\tsw_w32_mask(0, 1, RTL930X_L3_IP6UC_ROUTE_CTRL);\n\tsw_w32_mask(0, 1, RTL930X_L3_IPMC_ROUTE_CTRL);\n\tsw_w32_mask(0, 1, RTL930X_L3_IP6MC_ROUTE_CTRL);\n\n\tsw_w32(0x00002001, RTL930X_L3_IPUC_ROUTE_CTRL);\n\tsw_w32(0x00014581, RTL930X_L3_IP6UC_ROUTE_CTRL);\n\tsw_w32(0x00000501, RTL930X_L3_IPMC_ROUTE_CTRL);\n\tsw_w32(0x00012881, RTL930X_L3_IP6MC_ROUTE_CTRL);\n\n\tpr_info(\"L3_IPUC_ROUTE_CTRL %08x, IPMC_ROUTE %08x, IP6UC_ROUTE %08x, IP6MC_ROUTE %08x\\n\",\n\t\tsw_r32(RTL930X_L3_IPUC_ROUTE_CTRL), sw_r32(RTL930X_L3_IPMC_ROUTE_CTRL),\n\t\tsw_r32(RTL930X_L3_IP6UC_ROUTE_CTRL), sw_r32(RTL930X_L3_IP6MC_ROUTE_CTRL));\n\n\t// Trap non-ip traffic to the CPU-port (e.g. ARP so we stay reachable)\n\tsw_w32_mask(0x3 << 8, 0x1 << 8, RTL930X_L3_IP_ROUTE_CTRL);\n\tpr_info(\"L3_IP_ROUTE_CTRL %08x\\n\", sw_r32(RTL930X_L3_IP_ROUTE_CTRL));\n\n\t// PORT_ISO_RESTRICT_ROUTE_CTRL ?\n\n\t// Do not use prefix route 0 because of HW limitations\n\tset_bit(0, priv->route_use_bm);\n\n\treturn 0;\n}\n\nstatic u32 rtl930x_packet_cntr_read(int counter)\n{\n\tu32 v;\n\n\t// Read LOG table (3) via register RTL9300_TBL_0\n\tstruct table_reg *r = rtl_table_get(RTL9300_TBL_0, 3);\n\n\tpr_debug(\"In %s, id %d\\n\", __func__, counter);\n\trtl_table_read(r, counter / 2);\n\n\tpr_debug(\"Registers: %08x %08x\\n\",\n\t\tsw_r32(rtl_table_data(r, 0)), sw_r32(rtl_table_data(r, 1)));\n\t// The table has a size of 2 registers\n\tif (counter % 2)\n\t\tv = sw_r32(rtl_table_data(r, 0));\n\telse\n\t\tv = sw_r32(rtl_table_data(r, 1));\n\n\trtl_table_release(r);\n\n\treturn v;\n}\n\nstatic void rtl930x_packet_cntr_clear(int counter)\n{\n\t// Access LOG table (3) via register RTL9300_TBL_0\n\tstruct table_reg *r = rtl_table_get(RTL9300_TBL_0, 3);\n\n\tpr_info(\"In %s, id %d\\n\", __func__, counter);\n\t// The table has a size of 2 registers\n\tif (counter % 2)\n\t\tsw_w32(0, rtl_table_data(r, 0));\n\telse\n\t\tsw_w32(0, rtl_table_data(r, 1));\n\n\trtl_table_write(r, counter / 2);\n\n\trtl_table_release(r);\n}\n\nvoid rtl930x_vlan_port_pvidmode_set(int port, enum pbvlan_type type, enum pbvlan_mode mode)\n{\n\tif (type == PBVLAN_TYPE_INNER)\n\t\tsw_w32_mask(0x3, mode, RTL930X_VLAN_PORT_PB_VLAN + (port << 2));\n\telse\n\t\tsw_w32_mask(0x3 << 14, mode << 14 ,RTL930X_VLAN_PORT_PB_VLAN + (port << 2));\n}\n\nvoid rtl930x_vlan_port_pvid_set(int port, enum pbvlan_type type, int pvid)\n{\n\tif (type == PBVLAN_TYPE_INNER)\n\t\tsw_w32_mask(0xfff << 2, pvid << 2, RTL930X_VLAN_PORT_PB_VLAN + (port << 2));\n\telse\n\t\tsw_w32_mask(0xfff << 16, pvid << 16, RTL930X_VLAN_PORT_PB_VLAN + (port << 2));\n}\n\nstatic int rtl930x_set_ageing_time(unsigned long msec)\n{\n\tint t = sw_r32(RTL930X_L2_AGE_CTRL);\n\n\tt &= 0x1FFFFF;\n\tt = (t * 7) / 10;\n\tpr_debug(\"L2 AGING time: %d sec\\n\", t);\n\n\tt = (msec / 100 + 6) / 7;\n\tt = t > 0x1FFFFF ? 0x1FFFFF : t;\n\tsw_w32_mask(0x1FFFFF, t, RTL930X_L2_AGE_CTRL);\n\tpr_debug(\"Dynamic aging for ports: %x\\n\", sw_r32(RTL930X_L2_PORT_AGE_CTRL));\n\n\treturn 0;\n}\n\nstatic void rtl930x_set_igr_filter(int port,  enum igr_filter state)\n{\n\tsw_w32_mask(0x3 << ((port & 0xf)<<1), state << ((port & 0xf)<<1),\n\t\t    RTL930X_VLAN_PORT_IGR_FLTR + (((port >> 4) << 2)));\n}\n\nstatic void rtl930x_set_egr_filter(int port,  enum egr_filter state)\n{\n\tsw_w32_mask(0x1 << (port % 0x1D), state << (port % 0x1D),\n\t\t    RTL930X_VLAN_PORT_EGR_FLTR + (((port / 29) << 2)));\n}\n\nvoid rtl930x_set_distribution_algorithm(int group, int algoidx, u32 algomsk)\n{\n\tu32 l3shift = 0;\n\tu32 newmask = 0;\n\n\t/* TODO: for now we set algoidx to 0 */\n\talgoidx = 0;\n\tif (algomsk & TRUNK_DISTRIBUTION_ALGO_SIP_BIT) {\n\t\tl3shift = 4;\n\t\tnewmask |= TRUNK_DISTRIBUTION_ALGO_L3_SIP_BIT;\n\t}\n\tif (algomsk & TRUNK_DISTRIBUTION_ALGO_DIP_BIT) {\n\t\tl3shift = 4;\n\t\tnewmask |= TRUNK_DISTRIBUTION_ALGO_L3_DIP_BIT;\n\t}\n\tif (algomsk & TRUNK_DISTRIBUTION_ALGO_SRC_L4PORT_BIT) {\n\t\tl3shift = 4;\n\t\tnewmask |= TRUNK_DISTRIBUTION_ALGO_L3_SRC_L4PORT_BIT;\n\t}\n\tif (algomsk & TRUNK_DISTRIBUTION_ALGO_SRC_L4PORT_BIT) {\n\t\tl3shift = 4;\n\t\tnewmask |= TRUNK_DISTRIBUTION_ALGO_L3_SRC_L4PORT_BIT;\n\t}\n\n\tif (l3shift == 4) {\n\t\tif (algomsk & TRUNK_DISTRIBUTION_ALGO_SMAC_BIT)\n\t\t\tnewmask |= TRUNK_DISTRIBUTION_ALGO_L3_SMAC_BIT;\n\n\t\tif (algomsk & TRUNK_DISTRIBUTION_ALGO_DMAC_BIT)\n\t\t\tnewmask |= TRUNK_DISTRIBUTION_ALGO_L3_DMAC_BIT;\n\t} else  {\n\t\tif (algomsk & TRUNK_DISTRIBUTION_ALGO_SMAC_BIT)\n\t\t\tnewmask |= TRUNK_DISTRIBUTION_ALGO_L2_SMAC_BIT;\n\t\tif (algomsk & TRUNK_DISTRIBUTION_ALGO_DMAC_BIT)\n\t\t\tnewmask |= TRUNK_DISTRIBUTION_ALGO_L2_DMAC_BIT;\n\t}\n\n\tsw_w32(newmask << l3shift, RTL930X_TRK_HASH_CTRL + (algoidx << 2));\n}\n\nstatic void rtl930x_led_init(struct rtl838x_switch_priv *priv)\n{\n\tint i, pos;\n\tu32 v, pm = 0, set;\n\tu32 setlen;\n\tconst __be32 *led_set;\n\tchar set_name[9];\n\tstruct device_node *node;\n\n\tpr_info(\"%s called\\n\", __func__);\n\tnode = of_find_compatible_node(NULL, NULL, \"realtek,rtl9300-leds\");\n\tif (!node) {\n\t\tpr_info(\"%s No compatible LED node found\\n\", __func__);\n\t\treturn;\n\t}\n\n\tfor (i= 0; i < priv->cpu_port; i++) {\n\t\tpos = (i << 1) % 32;\n\t\tsw_w32_mask(0x3 << pos, 0, RTL930X_LED_PORT_FIB_SET_SEL_CTRL(i));\n\t\tsw_w32_mask(0x3 << pos, 0, RTL930X_LED_PORT_COPR_SET_SEL_CTRL(i));\n\n\t\tif (!priv->ports[i].phy)\n\t\t\tcontinue;\n\n\t\tv = 0x1;\n\t\tif (priv->ports[i].is10G)\n\t\t\tv = 0x3;\n\t\tif (priv->ports[i].phy_is_integrated)\n\t\t\tv = 0x1;\n\t\tsw_w32_mask(0x3 << pos, v << pos, RTL930X_LED_PORT_NUM_CTRL(i));\n\n\t\tpm |= BIT(i);\n\n\t\tset = priv->ports[i].led_set;\n\t\tsw_w32_mask(0, set << pos, RTL930X_LED_PORT_COPR_SET_SEL_CTRL(i));\n\t\tsw_w32_mask(0, set << pos, RTL930X_LED_PORT_FIB_SET_SEL_CTRL(i));\n\t}\n\n\tfor (i = 0; i < 4; i++) {\n\t\tsprintf(set_name, \"led_set%d\", i);\n\t\tled_set = of_get_property(node, set_name, &setlen);\n\t\tif (!led_set || setlen != 16)\n\t\t\tbreak;\n\t\tv = be32_to_cpup(led_set) << 16 | be32_to_cpup(led_set + 1);\n\t\tsw_w32(v, RTL930X_LED_SET0_0_CTRL - 4 - i * 8);\n\t\tv = be32_to_cpup(led_set + 2) << 16 | be32_to_cpup(led_set + 3);\n\t\tsw_w32(v, RTL930X_LED_SET0_0_CTRL - i * 8);\n\t}\n\n\t// Set LED mode to serial (0x1)\n\tsw_w32_mask(0x3, 0x1, RTL930X_LED_GLB_CTRL);\n\n\t// Set port type masks\n\tsw_w32(pm, RTL930X_LED_PORT_COPR_MASK_CTRL);\n\tsw_w32(pm, RTL930X_LED_PORT_FIB_MASK_CTRL);\n\tsw_w32(pm, RTL930X_LED_PORT_COMBO_MASK_CTRL);\n\n\tfor (i = 0; i < 24; i++)\n\t\tpr_info(\"%s %08x: %08x\\n\",__func__, 0xbb00cc00 + i * 4, sw_r32(0xcc00 + i * 4));\n}\n\nconst struct rtl838x_reg rtl930x_reg = {\n\t.mask_port_reg_be = rtl838x_mask_port_reg,\n\t.set_port_reg_be = rtl838x_set_port_reg,\n\t.get_port_reg_be = rtl838x_get_port_reg,\n\t.mask_port_reg_le = rtl838x_mask_port_reg,\n\t.set_port_reg_le = rtl838x_set_port_reg,\n\t.get_port_reg_le = rtl838x_get_port_reg,\n\t.stat_port_rst = RTL930X_STAT_PORT_RST,\n\t.stat_rst = RTL930X_STAT_RST,\n\t.stat_port_std_mib = RTL930X_STAT_PORT_MIB_CNTR,\n\t.traffic_enable = rtl930x_traffic_enable,\n\t.traffic_disable = rtl930x_traffic_disable,\n\t.traffic_get = rtl930x_traffic_get,\n\t.traffic_set = rtl930x_traffic_set,\n\t.l2_ctrl_0 = RTL930X_L2_CTRL,\n\t.l2_ctrl_1 = RTL930X_L2_AGE_CTRL,\n\t.l2_port_aging_out = RTL930X_L2_PORT_AGE_CTRL,\n\t.set_ageing_time = rtl930x_set_ageing_time,\n\t.smi_poll_ctrl = RTL930X_SMI_POLL_CTRL, // TODO: Difference to RTL9300_SMI_PRVTE_POLLING_CTRL\n\t.l2_tbl_flush_ctrl = RTL930X_L2_TBL_FLUSH_CTRL,\n\t.exec_tbl0_cmd = rtl930x_exec_tbl0_cmd,\n\t.exec_tbl1_cmd = rtl930x_exec_tbl1_cmd,\n\t.tbl_access_data_0 = rtl930x_tbl_access_data_0,\n\t.isr_glb_src = RTL930X_ISR_GLB,\n\t.isr_port_link_sts_chg = RTL930X_ISR_PORT_LINK_STS_CHG,\n\t.imr_port_link_sts_chg = RTL930X_IMR_PORT_LINK_STS_CHG,\n\t.imr_glb = RTL930X_IMR_GLB,\n\t.vlan_tables_read = rtl930x_vlan_tables_read,\n\t.vlan_set_tagged = rtl930x_vlan_set_tagged,\n\t.vlan_set_untagged = rtl930x_vlan_set_untagged,\n\t.vlan_profile_dump = rtl930x_vlan_profile_dump,\n\t.vlan_profile_setup = rtl930x_vlan_profile_setup,\n\t.vlan_fwd_on_inner = rtl930x_vlan_fwd_on_inner,\n\t.set_vlan_igr_filter = rtl930x_set_igr_filter,\n\t.set_vlan_egr_filter = rtl930x_set_egr_filter,\n\t.stp_get = rtl930x_stp_get,\n\t.stp_set = rtl930x_stp_set,\n\t.mac_force_mode_ctrl = rtl930x_mac_force_mode_ctrl,\n\t.mac_port_ctrl = rtl930x_mac_port_ctrl,\n\t.l2_port_new_salrn = rtl930x_l2_port_new_salrn,\n\t.l2_port_new_sa_fwd = rtl930x_l2_port_new_sa_fwd,\n\t.mir_ctrl = RTL930X_MIR_CTRL,\n\t.mir_dpm = RTL930X_MIR_DPM_CTRL,\n\t.mir_spm = RTL930X_MIR_SPM_CTRL,\n\t.mac_link_sts = RTL930X_MAC_LINK_STS,\n\t.mac_link_dup_sts = RTL930X_MAC_LINK_DUP_STS,\n\t.mac_link_spd_sts = rtl930x_mac_link_spd_sts,\n\t.mac_rx_pause_sts = RTL930X_MAC_RX_PAUSE_STS,\n\t.mac_tx_pause_sts = RTL930X_MAC_TX_PAUSE_STS,\n\t.read_l2_entry_using_hash = rtl930x_read_l2_entry_using_hash,\n\t.write_l2_entry_using_hash = rtl930x_write_l2_entry_using_hash,\n\t.read_cam = rtl930x_read_cam,\n\t.write_cam = rtl930x_write_cam,\n\t.vlan_port_tag_sts_ctrl = RTL930X_VLAN_PORT_TAG_STS_CTRL,\n\t.vlan_port_pvidmode_set = rtl930x_vlan_port_pvidmode_set,\n\t.vlan_port_pvid_set = rtl930x_vlan_port_pvid_set,\n\t.trk_mbr_ctr = rtl930x_trk_mbr_ctr,\n\t.rma_bpdu_fld_pmask = RTL930X_RMA_BPDU_FLD_PMSK,\n\t.init_eee = rtl930x_init_eee,\n\t.port_eee_set = rtl930x_port_eee_set,\n\t.eee_port_ability = rtl930x_eee_port_ability,\n\t.l2_hash_seed = rtl930x_l2_hash_seed,\n\t.l2_hash_key = rtl930x_l2_hash_key,\n\t.read_mcast_pmask = rtl930x_read_mcast_pmask,\n\t.write_mcast_pmask = rtl930x_write_mcast_pmask,\n\t.pie_init = rtl930x_pie_init,\n\t.pie_rule_write = rtl930x_pie_rule_write,\n\t.pie_rule_add = rtl930x_pie_rule_add,\n\t.pie_rule_rm = rtl930x_pie_rule_rm,\n\t.l2_learning_setup = rtl930x_l2_learning_setup,\n\t.packet_cntr_read = rtl930x_packet_cntr_read,\n\t.packet_cntr_clear = rtl930x_packet_cntr_clear,\n\t.route_read = rtl930x_route_read,\n\t.route_write = rtl930x_route_write,\n\t.host_route_write = rtl930x_host_route_write,\n\t.l3_setup = rtl930x_l3_setup,\n\t.set_l3_nexthop = rtl930x_set_l3_nexthop,\n\t.get_l3_nexthop = rtl930x_get_l3_nexthop,\n\t.get_l3_egress_mac = rtl930x_get_l3_egress_mac,\n\t.set_l3_egress_mac = rtl930x_set_l3_egress_mac,\n\t.find_l3_slot = rtl930x_find_l3_slot,\n\t.route_lookup_hw = rtl930x_route_lookup_hw,\n\t.get_l3_router_mac = rtl930x_get_l3_router_mac,\n\t.set_l3_router_mac = rtl930x_set_l3_router_mac,\n\t.set_l3_egress_intf = rtl930x_set_l3_egress_intf,\n\t.set_distribution_algorithm = rtl930x_set_distribution_algorithm,\n\t.led_init = rtl930x_led_init,\n};\n"
  },
  {
    "path": "target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/rtl931x.c",
    "content": "// SPDX-License-Identifier: GPL-2.0-only\n\n#include <asm/mach-rtl838x/mach-rtl83xx.h>\n#include \"rtl83xx.h\"\n\nextern struct mutex smi_lock;\nextern struct rtl83xx_soc_info soc_info;\n\n/* Definition of the RTL931X-specific template field IDs as used in the PIE */\nenum template_field_id {\n\tTEMPLATE_FIELD_SPM0 = 1,\n\tTEMPLATE_FIELD_SPM1 = 2,\n\tTEMPLATE_FIELD_SPM2 = 3,\n\tTEMPLATE_FIELD_SPM3 = 4,\n\tTEMPLATE_FIELD_DMAC0 = 9,\n\tTEMPLATE_FIELD_DMAC1 = 10,\n\tTEMPLATE_FIELD_DMAC2 = 11,\n\tTEMPLATE_FIELD_SMAC0 = 12,\n\tTEMPLATE_FIELD_SMAC1 = 13,\n\tTEMPLATE_FIELD_SMAC2 = 14,\n\tTEMPLATE_FIELD_ETHERTYPE = 15,\n\tTEMPLATE_FIELD_OTAG = 16,\n\tTEMPLATE_FIELD_ITAG = 17,\n\tTEMPLATE_FIELD_SIP0 = 18,\n\tTEMPLATE_FIELD_SIP1 = 19,\n\tTEMPLATE_FIELD_DIP0 = 20,\n\tTEMPLATE_FIELD_DIP1 = 21,\n\tTEMPLATE_FIELD_IP_TOS_PROTO = 22,\n\tTEMPLATE_FIELD_L4_SPORT = 23,\n\tTEMPLATE_FIELD_L4_DPORT = 24,\n\tTEMPLATE_FIELD_L34_HEADER = 25,\n\tTEMPLATE_FIELD_TCP_INFO = 26,\n\tTEMPLATE_FIELD_SIP2 = 34,\n\tTEMPLATE_FIELD_SIP3 = 35,\n\tTEMPLATE_FIELD_SIP4 = 36,\n\tTEMPLATE_FIELD_SIP5 = 37,\n\tTEMPLATE_FIELD_SIP6 = 38,\n\tTEMPLATE_FIELD_SIP7 = 39,\n\tTEMPLATE_FIELD_DIP2 = 42,\n\tTEMPLATE_FIELD_DIP3 = 43,\n\tTEMPLATE_FIELD_DIP4 = 44,\n\tTEMPLATE_FIELD_DIP5 = 45,\n\tTEMPLATE_FIELD_DIP6 = 46,\n\tTEMPLATE_FIELD_DIP7 = 47,\n\tTEMPLATE_FIELD_FLOW_LABEL = 49,\n\tTEMPLATE_FIELD_DSAP_SSAP = 50,\n\tTEMPLATE_FIELD_FWD_VID = 52,\n\tTEMPLATE_FIELD_RANGE_CHK = 53,\n\tTEMPLATE_FIELD_SLP = 55,\n\tTEMPLATE_FIELD_DLP = 56,\n\tTEMPLATE_FIELD_META_DATA = 57,\n\tTEMPLATE_FIELD_FIRST_MPLS1 = 60,\n\tTEMPLATE_FIELD_FIRST_MPLS2 = 61,\n\tTEMPLATE_FIELD_DPM3 = 8,\n};\n\n/* The meaning of TEMPLATE_FIELD_VLAN depends on phase and the configuration in\n * RTL931X_PIE_CTRL. We use always the same definition and map to the inner VLAN tag:\n */\n#define TEMPLATE_FIELD_VLAN TEMPLATE_FIELD_ITAG\n\n// Number of fixed templates predefined in the RTL9300 SoC\n#define N_FIXED_TEMPLATES 5\n// RTL931x specific predefined templates\nstatic enum template_field_id fixed_templates[N_FIXED_TEMPLATES][N_FIXED_FIELDS_RTL931X] =\n{\n\t{\n\t\tTEMPLATE_FIELD_DMAC0, TEMPLATE_FIELD_DMAC1, TEMPLATE_FIELD_DMAC2,\n\t\tTEMPLATE_FIELD_SMAC0, TEMPLATE_FIELD_SMAC1, TEMPLATE_FIELD_SMAC2,\n\t\tTEMPLATE_FIELD_VLAN, TEMPLATE_FIELD_IP_TOS_PROTO, TEMPLATE_FIELD_DSAP_SSAP,\n\t\tTEMPLATE_FIELD_ETHERTYPE, TEMPLATE_FIELD_SPM0, TEMPLATE_FIELD_SPM1,\n\t\tTEMPLATE_FIELD_SPM2, TEMPLATE_FIELD_SPM3\n\t}, {\n\t\tTEMPLATE_FIELD_SIP0, TEMPLATE_FIELD_SIP1, TEMPLATE_FIELD_DIP0,\n\t\tTEMPLATE_FIELD_DIP1, TEMPLATE_FIELD_IP_TOS_PROTO, TEMPLATE_FIELD_TCP_INFO,\n\t\tTEMPLATE_FIELD_L4_SPORT, TEMPLATE_FIELD_L4_DPORT, TEMPLATE_FIELD_VLAN,\n\t\tTEMPLATE_FIELD_RANGE_CHK, TEMPLATE_FIELD_SPM0, TEMPLATE_FIELD_SPM1,\n\t\tTEMPLATE_FIELD_SPM2, TEMPLATE_FIELD_SPM3\n\t}, {\n\t\tTEMPLATE_FIELD_DMAC0, TEMPLATE_FIELD_DMAC1, TEMPLATE_FIELD_DMAC2,\n\t\tTEMPLATE_FIELD_VLAN, TEMPLATE_FIELD_ETHERTYPE, TEMPLATE_FIELD_IP_TOS_PROTO,\n\t\tTEMPLATE_FIELD_SIP0, TEMPLATE_FIELD_SIP1, TEMPLATE_FIELD_DIP0,\n\t\tTEMPLATE_FIELD_DIP1, TEMPLATE_FIELD_L4_SPORT, TEMPLATE_FIELD_L4_DPORT,\n\t\tTEMPLATE_FIELD_META_DATA, TEMPLATE_FIELD_SLP\n\t}, {\n\t\tTEMPLATE_FIELD_DIP0, TEMPLATE_FIELD_DIP1, TEMPLATE_FIELD_DIP2,\n\t\tTEMPLATE_FIELD_DIP3, TEMPLATE_FIELD_DIP4, TEMPLATE_FIELD_DIP5,\n\t\tTEMPLATE_FIELD_DIP6, TEMPLATE_FIELD_DIP7, TEMPLATE_FIELD_IP_TOS_PROTO,\n\t\tTEMPLATE_FIELD_TCP_INFO, TEMPLATE_FIELD_L4_SPORT, TEMPLATE_FIELD_L4_DPORT,\n\t\tTEMPLATE_FIELD_RANGE_CHK, TEMPLATE_FIELD_SLP\n\t}, {\n\t\tTEMPLATE_FIELD_SIP0, TEMPLATE_FIELD_SIP1, TEMPLATE_FIELD_SIP2,\n\t\tTEMPLATE_FIELD_SIP3, TEMPLATE_FIELD_SIP4, TEMPLATE_FIELD_SIP5,\n\t\tTEMPLATE_FIELD_SIP6, TEMPLATE_FIELD_SIP7, TEMPLATE_FIELD_META_DATA,\n\t\tTEMPLATE_FIELD_VLAN, TEMPLATE_FIELD_SPM0, TEMPLATE_FIELD_SPM1,\n\t\tTEMPLATE_FIELD_SPM2, TEMPLATE_FIELD_SPM3\n\t},\n};\n\ninline void rtl931x_exec_tbl0_cmd(u32 cmd)\n{\n\tsw_w32(cmd, RTL931X_TBL_ACCESS_CTRL_0);\n\tdo { } while (sw_r32(RTL931X_TBL_ACCESS_CTRL_0) & (1 << 20));\n}\n\ninline void rtl931x_exec_tbl1_cmd(u32 cmd)\n{\n\tsw_w32(cmd, RTL931X_TBL_ACCESS_CTRL_1);\n\tdo { } while (sw_r32(RTL931X_TBL_ACCESS_CTRL_1) & (1 << 17));\n}\n\ninline int rtl931x_tbl_access_data_0(int i)\n{\n\treturn RTL931X_TBL_ACCESS_DATA_0(i);\n}\n\nvoid rtl931x_vlan_profile_dump(int index)\n{\n\tu64 profile[4];\n\n\tif (index < 0 || index > 15)\n\t\treturn;\n\n\tprofile[0] = sw_r32(RTL931X_VLAN_PROFILE_SET(index));\n\tprofile[1] = (sw_r32(RTL931X_VLAN_PROFILE_SET(index) + 4) & 0x1FFFFFFFULL) << 32\n\t\t| (sw_r32(RTL931X_VLAN_PROFILE_SET(index) + 8) & 0xFFFFFFFF);\n\tprofile[2] = (sw_r32(RTL931X_VLAN_PROFILE_SET(index) + 16) & 0x1FFFFFFFULL) << 32\n\t\t| (sw_r32(RTL931X_VLAN_PROFILE_SET(index) + 12) & 0xFFFFFFFF);\n\tprofile[3] = (sw_r32(RTL931X_VLAN_PROFILE_SET(index) + 20) & 0x1FFFFFFFULL) << 32\n\t\t| (sw_r32(RTL931X_VLAN_PROFILE_SET(index) + 24) & 0xFFFFFFFF);\n\n\tpr_info(\"VLAN %d: L2 learning: %d, L2 Unknown MultiCast Field %llx, \\\n\t\tIPv4 Unknown MultiCast Field %llx, IPv6 Unknown MultiCast Field: %llx\",\n\t\tindex, (u32) (profile[0] & (3 << 14)), profile[1], profile[2], profile[3]);\n}\n\nstatic void rtl931x_stp_get(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[])\n{\n\tint i;\n\tu32 cmd = 1 << 20 /* Execute cmd */\n\t\t| 0 << 19 /* Read */\n\t\t| 5 << 15 /* Table type 0b101 */\n\t\t| (msti & 0x3fff);\n\tpriv->r->exec_tbl0_cmd(cmd);\n\n\tfor (i = 0; i < 4; i++)\n\t\tport_state[i] = sw_r32(priv->r->tbl_access_data_0(i));\n}\n\nstatic void rtl931x_stp_set(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[])\n{\n\tint i;\n\tu32 cmd = 1 << 20 /* Execute cmd */\n\t\t| 1 << 19 /* Write */\n\t\t| 5 << 15 /* Table type 0b101 */\n\t\t| (msti & 0x3fff);\n\tfor (i = 0; i < 4; i++)\n\t\tsw_w32(port_state[i], priv->r->tbl_access_data_0(i));\n\tpriv->r->exec_tbl0_cmd(cmd);\n}\n\ninline static int rtl931x_trk_mbr_ctr(int group)\n{\n\treturn RTL931X_TRK_MBR_CTRL + (group << 2);\n}\n\nstatic void rtl931x_vlan_tables_read(u32 vlan, struct rtl838x_vlan_info *info)\n{\n\tu32 v, w, x, y;\n\t// Read VLAN table (3) via register 0\n\tstruct table_reg *r = rtl_table_get(RTL9310_TBL_0, 3);\n\n\trtl_table_read(r, vlan);\n\tv = sw_r32(rtl_table_data(r, 0));\n\tw = sw_r32(rtl_table_data(r, 1));\n\tx = sw_r32(rtl_table_data(r, 2));\n\ty = sw_r32(rtl_table_data(r, 3));\n\trtl_table_release(r);\n\n\tpr_debug(\"VLAN_READ %d: %08x %08x %08x %08x\\n\", vlan, v, w, x, y);\n\tinfo->tagged_ports = ((u64) v) << 25 | (w >> 7);\n\tinfo->profile_id = (x >> 16) & 0xf;\n\tinfo->fid = w & 0x7f;\t\t\t\t// AKA MSTI depending on context\n\tinfo->hash_uc_fid = !!(x & BIT(31));\n\tinfo->hash_mc_fid = !!(x & BIT(30));\n\tinfo->if_id = (x >> 20) & 0x3ff;\n\tinfo->profile_id = (x >> 16) & 0xf;\n\tinfo->multicast_grp_mask = x & 0xffff;\n\tif (x & BIT(31))\n\t\tinfo->l2_tunnel_list_id = y >> 18;\n\telse\n\t\tinfo->l2_tunnel_list_id = -1;\n\tpr_debug(\"%s read tagged %016llx, profile-id %d, uc %d, mc %d, intf-id %d\\n\", __func__,\n\t\tinfo->tagged_ports, info->profile_id, info->hash_uc_fid, info->hash_mc_fid,\n\t\tinfo->if_id);\n\n\t// Read UNTAG table via table register 3\n\tr = rtl_table_get(RTL9310_TBL_3, 0);\n\trtl_table_read(r, vlan);\n\tv = ((u64)sw_r32(rtl_table_data(r, 0))) << 25;\n\tv |= sw_r32(rtl_table_data(r, 1)) >> 7;\n\trtl_table_release(r);\n\n\tinfo->untagged_ports = v;\n}\n\nstatic void rtl931x_vlan_set_tagged(u32 vlan, struct rtl838x_vlan_info *info)\n{\n\tu32 v, w, x, y;\n\t// Access VLAN table (1) via register 0\n\tstruct table_reg *r = rtl_table_get(RTL9310_TBL_0, 3);\n\n\tv = info->tagged_ports >> 25;\n\tw = (info->tagged_ports & 0x1fffff) << 7;\n\tw |= info->fid & 0x7f;\n\tx = info->hash_uc_fid ? BIT(31) : 0;\n\tx |= info->hash_mc_fid ? BIT(30) : 0;\n\tx |= info->if_id & 0x3ff << 20;\n\tx |= (info->profile_id & 0xf) << 16;\n\tx |= info->multicast_grp_mask & 0xffff;\n\tif (info->l2_tunnel_list_id >= 0) {\n\t\ty = info->l2_tunnel_list_id << 18;\n\t\ty |= BIT(31);\n\t} else {\n\t\ty = 0;\n\t}\n\n\tsw_w32(v, rtl_table_data(r, 0));\n\tsw_w32(w, rtl_table_data(r, 1));\n\tsw_w32(x, rtl_table_data(r, 2));\n\tsw_w32(y, rtl_table_data(r, 3));\n\n\trtl_table_write(r, vlan);\n\trtl_table_release(r);\n}\n\nstatic void rtl931x_vlan_set_untagged(u32 vlan, u64 portmask)\n{\n\tstruct table_reg *r = rtl_table_get(RTL9310_TBL_3, 0);\n\n\trtl839x_set_port_reg_be(portmask << 7, rtl_table_data(r, 0));\n\trtl_table_write(r, vlan);\n\trtl_table_release(r);\n}\n\nstatic inline int rtl931x_mac_force_mode_ctrl(int p)\n{\n\treturn RTL931X_MAC_FORCE_MODE_CTRL + (p << 2);\n}\n\nstatic inline int rtl931x_mac_link_spd_sts(int p)\n{\n\treturn RTL931X_MAC_LINK_SPD_STS + (((p >> 3) << 2));\n}\n\nstatic inline int rtl931x_mac_port_ctrl(int p)\n{\n\treturn RTL931X_MAC_L2_PORT_CTRL + (p << 7);\n}\n\nstatic inline int rtl931x_l2_port_new_salrn(int p)\n{\n\treturn RTL931X_L2_PORT_NEW_SALRN(p);\n}\n\nstatic inline int rtl931x_l2_port_new_sa_fwd(int p)\n{\n\treturn RTL931X_L2_PORT_NEW_SA_FWD(p);\n}\n\nirqreturn_t rtl931x_switch_irq(int irq, void *dev_id)\n{\n\tstruct dsa_switch *ds = dev_id;\n\tu32 status = sw_r32(RTL931X_ISR_GLB_SRC);\n\tu64 ports = rtl839x_get_port_reg_le(RTL931X_ISR_PORT_LINK_STS_CHG);\n\tu64 link;\n\tint i;\n\n\t/* Clear status */\n\trtl839x_set_port_reg_le(ports, RTL931X_ISR_PORT_LINK_STS_CHG);\n\tpr_debug(\"RTL931X Link change: status: %x, ports %016llx\\n\", status, ports);\n\n\tlink = rtl839x_get_port_reg_le(RTL931X_MAC_LINK_STS);\n\t// Must re-read this to get correct status\n\tlink = rtl839x_get_port_reg_le(RTL931X_MAC_LINK_STS);\n\tpr_debug(\"RTL931X Link change: status: %x, link status %016llx\\n\", status, link);\n\n\tfor (i = 0; i < 56; i++) {\n\t\tif (ports & BIT_ULL(i)) {\n\t\t\tif (link & BIT_ULL(i)) {\n\t\t\t\tpr_info(\"%s port %d up\\n\", __func__, i);\n\t\t\t\tdsa_port_phylink_mac_change(ds, i, true);\n\t\t\t} else {\n\t\t\t\tpr_info(\"%s port %d down\\n\", __func__, i);\n\t\t\t\tdsa_port_phylink_mac_change(ds, i, false);\n\t\t\t}\n\t\t}\n\t}\n\treturn IRQ_HANDLED;\n}\n\nint rtl931x_write_phy(u32 port, u32 page, u32 reg, u32 val)\n{\n\tu32 v;\n\tint err = 0;\n\n\tval &= 0xffff;\n\tif (port > 63 || page > 4095 || reg > 31)\n\t\treturn -ENOTSUPP;\n\n\tmutex_lock(&smi_lock);\n\tpr_debug(\"%s: writing to phy %d %d %d %d\\n\", __func__, port, page, reg, val);\n\t/* Clear both port registers */\n\tsw_w32(0, RTL931X_SMI_INDRT_ACCESS_CTRL_2);\n\tsw_w32(0, RTL931X_SMI_INDRT_ACCESS_CTRL_2 + 4);\n\tsw_w32_mask(0, BIT(port % 32), RTL931X_SMI_INDRT_ACCESS_CTRL_2 + (port / 32) * 4);\n\n\tsw_w32_mask(0xffff, val, RTL931X_SMI_INDRT_ACCESS_CTRL_3);\n\n\tv = reg << 6 | page << 11 ;\n\tsw_w32(v, RTL931X_SMI_INDRT_ACCESS_CTRL_0);\n\n\tsw_w32(0x1ff, RTL931X_SMI_INDRT_ACCESS_CTRL_1);\n\n\tv |= BIT(4) | 1; /* Write operation and execute */\n\tsw_w32(v, RTL931X_SMI_INDRT_ACCESS_CTRL_0);\n\n\tdo {\n\t} while (sw_r32(RTL931X_SMI_INDRT_ACCESS_CTRL_0) & 0x1);\n\n\tif (sw_r32(RTL931X_SMI_INDRT_ACCESS_CTRL_0) & 0x2)\n\t\terr = -EIO;\n\n\tmutex_unlock(&smi_lock);\n\treturn err;\n}\n\nint rtl931x_read_phy(u32 port, u32 page, u32 reg, u32 *val)\n{\n\tu32 v;\n\n\tif (port > 63 || page > 4095 || reg > 31)\n\t\treturn -ENOTSUPP;\n\n\tmutex_lock(&smi_lock);\n\n\tsw_w32(port << 5, RTL931X_SMI_INDRT_ACCESS_BC_PHYID_CTRL);\n\n\tv = reg << 6 | page << 11 | 1;\n\tsw_w32(v, RTL931X_SMI_INDRT_ACCESS_CTRL_0);\n\n\tdo {\n\t} while (sw_r32(RTL931X_SMI_INDRT_ACCESS_CTRL_0) & 0x1);\n\n\tv = sw_r32(RTL931X_SMI_INDRT_ACCESS_CTRL_0);\n\t*val = sw_r32(RTL931X_SMI_INDRT_ACCESS_CTRL_3);\n\t*val = (*val & 0xffff0000) >> 16;\n\n\tpr_debug(\"%s: port %d, page: %d, reg: %x, val: %x, v: %08x\\n\",\n\t\t__func__, port, page, reg, *val, v);\n\n\tmutex_unlock(&smi_lock);\n\treturn 0;\n}\n\n/*\n * Read an mmd register of the PHY\n */\nint rtl931x_read_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 *val)\n{\n\tint err = 0;\n\tu32 v;\n\t/* Select PHY register type\n\t * If select 1G/10G MMD register type, registers EXT_PAGE, MAIN_PAGE and REG settings are don’t care.\n\t * 0x0  Normal register (Clause 22)\n\t * 0x1: 1G MMD register (MMD via Clause 22 registers 13 and 14)\n\t * 0x2: 10G MMD register (MMD via Clause 45)\n\t */\n\tint type = (regnum & MII_ADDR_C45)?2:1;\n\n\tmutex_lock(&smi_lock);\n\n\t// Set PHY to access via port-number\n\tsw_w32(port << 5, RTL931X_SMI_INDRT_ACCESS_BC_PHYID_CTRL);\n\n\t// Set MMD device number and register to write to\n\tsw_w32(devnum << 16 | mdiobus_c45_regad(regnum), RTL931X_SMI_INDRT_ACCESS_MMD_CTRL);\n\n\tv = type << 2 | BIT(0); // MMD-access-type | EXEC\n\tsw_w32(v, RTL931X_SMI_INDRT_ACCESS_CTRL_0);\n\n\tdo {\n\t\tv = sw_r32(RTL931X_SMI_INDRT_ACCESS_CTRL_0);\n\t} while (v & BIT(0));\n\n\t// Check for error condition\n\tif (v & BIT(1))\n\t\terr = -EIO;\n\n\t*val = sw_r32(RTL931X_SMI_INDRT_ACCESS_CTRL_3) >> 16;\n\n\tpr_debug(\"%s: port %d, dev: %x, regnum: %x, val: %x (err %d)\\n\", __func__,\n\t\t port, devnum, mdiobus_c45_regad(regnum), *val, err);\n\n\tmutex_unlock(&smi_lock);\n\n\treturn err;\n}\n\n/*\n * Write to an mmd register of the PHY\n */\nint rtl931x_write_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 val)\n{\n\tint err = 0;\n\tu32 v;\n\tint type = (regnum & MII_ADDR_C45)?2:1;\n\tu64 pm;\n\n\tmutex_lock(&smi_lock);\n\n\t// Set PHY to access via port-mask\n\tpm = (u64)1 << port;\n\tsw_w32((u32)pm, RTL931X_SMI_INDRT_ACCESS_CTRL_2);\n\tsw_w32((u32)(pm >> 32), RTL931X_SMI_INDRT_ACCESS_CTRL_2 + 4);\n\n\t// Set data to write\n\tsw_w32_mask(0xffff, val, RTL931X_SMI_INDRT_ACCESS_CTRL_3);\n\n\t// Set MMD device number and register to write to\n\tsw_w32(devnum << 16 | mdiobus_c45_regad(regnum), RTL931X_SMI_INDRT_ACCESS_MMD_CTRL);\n\n\tv = BIT(4) | type << 2 | BIT(0); // WRITE | MMD-access-type | EXEC\n\tsw_w32(v, RTL931X_SMI_INDRT_ACCESS_CTRL_0);\n\n\tdo {\n\t\tv = sw_r32(RTL931X_SMI_INDRT_ACCESS_CTRL_0);\n\t} while (v & BIT(0));\n\n\tpr_debug(\"%s: port %d, dev: %x, regnum: %x, val: %x (err %d)\\n\", __func__,\n\t\t port, devnum, mdiobus_c45_regad(regnum), val, err);\n\tmutex_unlock(&smi_lock);\n\treturn err;\n}\n\nvoid rtl931x_print_matrix(void)\n{\n\tvolatile u64 *ptr = RTL838X_SW_BASE + RTL839X_PORT_ISO_CTRL(0);\n\tint i;\n\n\tfor (i = 0; i < 52; i += 4)\n\t\tpr_info(\"> %16llx %16llx %16llx %16llx\\n\",\n\t\t\tptr[i + 0], ptr[i + 1], ptr[i + 2], ptr[i + 3]);\n\tpr_info(\"CPU_PORT> %16llx\\n\", ptr[52]);\n}\n\nvoid rtl931x_set_receive_management_action(int port, rma_ctrl_t type, action_type_t action)\n{\n\tu32 value = 0;\n\n\t/* hack for value mapping */\n\tif (type == GRATARP && action == COPY2CPU)\n\t\taction = TRAP2MASTERCPU;\n\n\tswitch(action) {\n\tcase FORWARD:\n\t\tvalue = 0;\n\t\tbreak;\n\tcase DROP:\n\t\tvalue = 1;\n\t\tbreak;\n\tcase TRAP2CPU:\n\t\tvalue = 2;\n\t\tbreak;\n\tcase TRAP2MASTERCPU:\n\t\tvalue = 3;\n\t\tbreak;\n\tcase FLOODALL:\n\t\tvalue = 4;\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\n\tswitch(type) {\n\tcase BPDU:\n\t\tsw_w32_mask(7 << ((port % 10) * 3), value << ((port % 10) * 3), RTL931X_RMA_BPDU_CTRL + ((port / 10) << 2));\n\tbreak;\n\tcase PTP:\n\t\t//udp\n\t\tsw_w32_mask(3 << 2, value << 2, RTL931X_RMA_PTP_CTRL + (port << 2));\n\t\t//eth2\n\t\tsw_w32_mask(3, value, RTL931X_RMA_PTP_CTRL + (port << 2));\n\tbreak;\n\tcase PTP_UDP:\n\t\tsw_w32_mask(3 << 2, value << 2, RTL931X_RMA_PTP_CTRL + (port << 2));\n\tbreak;\n\tcase PTP_ETH2:\n\t\tsw_w32_mask(3, value, RTL931X_RMA_PTP_CTRL + (port << 2));\n\tbreak;\n\tcase LLTP:\n\t\tsw_w32_mask(7 << ((port % 10) * 3), value << ((port % 10) * 3), RTL931X_RMA_LLTP_CTRL + ((port / 10) << 2));\n\tbreak;\n\tcase EAPOL:\n\t\tsw_w32_mask(7 << ((port % 10) * 3), value << ((port % 10) * 3), RTL931X_RMA_EAPOL_CTRL + ((port / 10) << 2));\n\tbreak;\n\tcase GRATARP:\n\t\tsw_w32_mask(3 << ((port & 0xf) << 1), value << ((port & 0xf) << 1), RTL931X_TRAP_ARP_GRAT_PORT_ACT + ((port >> 4) << 2));\n\tbreak;\n\t}\n}\n\nu64 rtl931x_traffic_get(int source)\n{\n\tu32 v;\n\tstruct table_reg *r = rtl_table_get(RTL9310_TBL_0, 6);\n\n\trtl_table_read(r, source);\n\tv = sw_r32(rtl_table_data(r, 0));\n\trtl_table_release(r);\n\treturn v >> 3;\n}\n\n/*\n * Enable traffic between a source port and a destination port matrix\n */\nvoid rtl931x_traffic_set(int source, u64 dest_matrix)\n{\n\tstruct table_reg *r = rtl_table_get(RTL9310_TBL_0, 6);\n\n\tsw_w32((dest_matrix << 3), rtl_table_data(r, 0));\n\trtl_table_write(r, source);\n\trtl_table_release(r);\n}\n\nvoid rtl931x_traffic_enable(int source, int dest)\n{\n\tstruct table_reg *r = rtl_table_get(RTL9310_TBL_0, 6);\n\trtl_table_read(r, source);\n\tsw_w32_mask(0, BIT(dest + 3), rtl_table_data(r, 0));\n\trtl_table_write(r, source);\n\trtl_table_release(r);\n}\n\nvoid rtl931x_traffic_disable(int source, int dest)\n{\n\tstruct table_reg *r = rtl_table_get(RTL9310_TBL_0, 6);\n\trtl_table_read(r, source);\n\tsw_w32_mask(BIT(dest + 3), 0, rtl_table_data(r, 0));\n\trtl_table_write(r, source);\n\trtl_table_release(r);\n}\n\nstatic u64 rtl931x_l2_hash_seed(u64 mac, u32 vid)\n{\n\tu64 v = vid;\n\n\tv <<= 48;\n\tv |= mac;\n\n\treturn v;\n}\n\n/*\n * Calculate both the block 0 and the block 1 hash by applyingthe same hash\n * algorithm as the one used currently by the ASIC to the seed, and return\n * both hashes in the lower and higher word of the return value since only 12 bit of\n * the hash are significant.\n */\nstatic u32 rtl931x_l2_hash_key(struct rtl838x_switch_priv *priv, u64 seed)\n{\n\tu32 h, h0, h1, h2, h3, h4, k0, k1;\n\n\th0 = seed & 0xfff;\n\th1 = (seed >> 12) & 0xfff;\n\th2 = (seed >> 24) & 0xfff;\n\th3 = (seed >> 36) & 0xfff;\n\th4 = (seed >> 48) & 0xfff;\n\th4 = ((h4 & 0x7) << 9) | ((h4 >> 3) & 0x1ff);\n\tk0 = h0 ^ h1 ^ h2 ^ h3 ^ h4;\n\n\th0 = seed & 0xfff;\n\th0 = ((h0 & 0x1ff) << 3) | ((h0 >> 9) & 0x7);\n\th1 = (seed >> 12) & 0xfff;\n\th1 = ((h1 & 0x3f) << 6) | ((h1 >> 6) & 0x3f);\n\th2 = (seed >> 24) & 0xfff;\n\th3 = (seed >> 36) & 0xfff;\n\th3 = ((h3 & 0x3f) << 6) | ((h3 >> 6) & 0x3f);\n\th4 = (seed >> 48) & 0xfff;\n\tk1 = h0 ^ h1 ^ h2 ^ h3 ^ h4;\n\n\t// Algorithm choice for block 0\n\tif (sw_r32(RTL931X_L2_CTRL) & BIT(0))\n\t\th = k1;\n\telse\n\t\th = k0;\n\n\t/* Algorithm choice for block 1\n\t * Since k0 and k1 are < 4096, adding 4096 will offset the hash into the second\n\t * half of hash-space\n\t * 4096 is in fact the hash-table size 32768 divided by 4 hashes per bucket\n\t * divided by 2 to divide the hash space in 2\n\t */\n\tif (sw_r32(RTL931X_L2_CTRL) & BIT(1))\n\t\th |= (k1 + 4096) << 16;\n\telse\n\t\th |= (k0 + 4096) << 16;\n\n\treturn h;\n}\n\n/*\n * Fills an L2 entry structure from the SoC registers\n */\nstatic void rtl931x_fill_l2_entry(u32 r[], struct rtl838x_l2_entry *e)\n{\n\tpr_debug(\"In %s valid?\\n\", __func__);\n\te->valid = !!(r[0] & BIT(31));\n\tif (!e->valid)\n\t\treturn;\n\n\tpr_debug(\"%s: entry valid, raw: %08x %08x %08x %08x\\n\", __func__, r[0], r[1], r[2], r[3]);\n\te->is_ip_mc = false;\n\te->is_ipv6_mc = false;\n\n\te->mac[0] = r[0] >> 8;\n\te->mac[1] = r[0];\n\te->mac[2] = r[1] >> 24;\n\te->mac[3] = r[1] >> 16;\n\te->mac[4] = r[1] >> 8;\n\te->mac[5] = r[1];\n\n\te->is_open_flow = !!(r[0] & BIT(30));\n\te->is_pe_forward = !!(r[0] & BIT(29));\n\te->next_hop = !!(r[2] & BIT(30));\n\te->rvid = (r[0] >> 16) & 0xfff;\n\n\t/* Is it a unicast entry? check multicast bit */\n\tif (!(e->mac[0] & 1)) {\n\t\te->type = L2_UNICAST;\n\t\te->is_l2_tunnel = !!(r[2] & BIT(31));\n\t\te->is_static = !!(r[2] & BIT(13));\n\t\te->port = (r[2] >> 19) & 0x3ff;\n\t\t// Check for trunk port\n\t\tif (r[2] & BIT(29)) {\n\t\t\te->is_trunk = true;\n\t\t\te->stack_dev = (e->port >> 9) & 1;\n\t\t\te->trunk = e->port & 0x3f;\n\t\t} else {\n\t\t\te->is_trunk = false;\n\t\t\te->stack_dev = (e->port >> 6) & 0xf;\n\t\t\te->port = e->port & 0x3f;\n\t\t}\n\n\t\te->block_da = !!(r[2] & BIT(14));\n\t\te->block_sa = !!(r[2] & BIT(15));\n\t\te->suspended = !!(r[2] & BIT(12));\n\t\te->age = (r[2] >> 16) & 3;\n\n\t\t// the UC_VID field in hardware is used for the VID or for the route id\n\t\tif (e->next_hop) {\n\t\t\te->nh_route_id = r[2] & 0x7ff;\n\t\t\te->vid = 0;\n\t\t} else {\n\t\t\te->vid = r[2] & 0xfff;\n\t\t\te->nh_route_id = 0;\n\t\t}\n\t\tif (e->is_l2_tunnel)\n\t\t\te->l2_tunnel_id = ((r[2] & 0xff) << 4) | (r[3] >> 28);\n\t\t// TODO: Implement VLAN conversion\n\t} else {\n\t\te->type = L2_MULTICAST;\n\t\te->is_local_forward = !!(r[2] & BIT(31));\n\t\te->is_remote_forward = !!(r[2] & BIT(17));\n\t\te->mc_portmask_index = (r[2] >> 18) & 0xfff;\n\t\te->l2_tunnel_list_id = (r[2] >> 4) & 0x1fff;\n\t}\n}\n\n/*\n * Fills the 3 SoC table registers r[] with the information of in the rtl838x_l2_entry\n */\nstatic void rtl931x_fill_l2_row(u32 r[], struct rtl838x_l2_entry *e)\n{\n\tu32 port;\n\n\tif (!e->valid) {\n\t\tr[0] = r[1] = r[2] = 0;\n\t\treturn;\n\t}\n\n\tr[2] = BIT(31);\t// Set valid bit\n\n\tr[0] = ((u32)e->mac[0]) << 24 | ((u32)e->mac[1]) << 16\n\t\t| ((u32)e->mac[2]) << 8 | ((u32)e->mac[3]);\n\tr[1] = ((u32)e->mac[4]) << 24 | ((u32)e->mac[5]) << 16;\n\n\tr[2] |= e->next_hop ? BIT(12) : 0;\n\n\tif (e->type == L2_UNICAST) {\n\t\tr[2] |= e->is_static ? BIT(14) : 0;\n\t\tr[1] |= e->rvid & 0xfff;\n\t\tr[2] |= (e->port & 0x3ff) << 20;\n\t\tif (e->is_trunk) {\n\t\t\tr[2] |= BIT(30);\n\t\t\tport = e->stack_dev << 9 | (e->port & 0x3f);\n\t\t} else {\n\t\t\tport = (e->stack_dev & 0xf) << 6;\n\t\t\tport |= e->port & 0x3f;\n\t\t}\n\t\tr[2] |= port << 20;\n\t\tr[2] |= e->block_da ? BIT(15) : 0;\n\t\tr[2] |= e->block_sa ? BIT(17) : 0;\n\t\tr[2] |= e->suspended ? BIT(13) : 0;\n\t\tr[2] |= (e->age & 0x3) << 17;\n\t\t// the UC_VID field in hardware is used for the VID or for the route id\n\t\tif (e->next_hop)\n\t\t\tr[2] |= e->nh_route_id & 0x7ff;\n\t\telse\n\t\t\tr[2] |= e->vid & 0xfff;\n\t} else { // L2_MULTICAST\n\t\tr[2] |= (e->mc_portmask_index & 0x3ff) << 16;\n\t\tr[2] |= e->mc_mac_index & 0x7ff;\n\t}\n}\n\n/*\n * Read an L2 UC or MC entry out of a hash bucket of the L2 forwarding table\n * hash is the id of the bucket and pos is the position of the entry in that bucket\n * The data read from the SoC is filled into rtl838x_l2_entry\n */\nstatic u64 rtl931x_read_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_l2_entry *e)\n{\n\tu32 r[4];\n\tstruct table_reg *q = rtl_table_get(RTL9310_TBL_0, 0);\n\tu32 idx;\n\tint i;\n\tu64 mac;\n\tu64 seed;\n\n\tpr_debug(\"%s: hash %08x, pos: %d\\n\", __func__, hash, pos);\n\n\t/* On the RTL93xx, 2 different hash algorithms are used making it a total of\n\t * 8 buckets that need to be searched, 4 for each hash-half\n\t * Use second hash space when bucket is between 4 and 8 */\n\tif (pos >= 4) {\n\t\tpos -= 4;\n\t\thash >>= 16;\n\t} else {\n\t\thash &= 0xffff;\n\t}\n\n\tidx = (0 << 14) | (hash << 2) | pos; // Search SRAM, with hash and at pos in bucket\n\tpr_debug(\"%s: NOW hash %08x, pos: %d\\n\", __func__, hash, pos);\n\n\trtl_table_read(q, idx);\n\tfor (i = 0; i < 4; i++)\n\t\tr[i] = sw_r32(rtl_table_data(q, i));\n\n\trtl_table_release(q);\n\n\trtl931x_fill_l2_entry(r, e);\n\n\tpr_debug(\"%s: valid: %d, nh: %d\\n\", __func__, e->valid, e->next_hop);\n\tif (!e->valid)\n\t\treturn 0;\n\n\tmac = ((u64)e->mac[0]) << 40 | ((u64)e->mac[1]) << 32 | ((u64)e->mac[2]) << 24\n\t\t| ((u64)e->mac[3]) << 16 | ((u64)e->mac[4]) << 8 | ((u64)e->mac[5]);\n\n\tseed = rtl931x_l2_hash_seed(mac, e->rvid);\n\tpr_debug(\"%s: mac %016llx, seed %016llx\\n\", __func__, mac, seed);\n\t// return vid with concatenated mac as unique id\n\treturn seed;\n}\n\nstatic u64 rtl931x_read_cam(int idx, struct rtl838x_l2_entry *e)\n{\n\t\treturn 0;\n}\n\nstatic void rtl931x_write_cam(int idx, struct rtl838x_l2_entry *e)\n{\n}\n\nstatic void rtl931x_write_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_l2_entry *e)\n{\n\tu32 r[4];\n\tstruct table_reg *q = rtl_table_get(RTL9310_TBL_0, 0);\n\tu32 idx = (0 << 14) | (hash << 2) | pos; // Access SRAM, with hash and at pos in bucket\n\tint i;\n\n\tpr_info(\"%s: hash %d, pos %d\\n\", __func__, hash, pos);\n\tpr_info(\"%s: index %d -> mac %02x:%02x:%02x:%02x:%02x:%02x\\n\", __func__, idx,\n\t\te->mac[0], e->mac[1], e->mac[2], e->mac[3],e->mac[4],e->mac[5]);\n\n\trtl931x_fill_l2_row(r, e);\n\tpr_info(\"%s: %d: %08x %08x %08x\\n\", __func__, idx, r[0], r[1], r[2]);\n\n\tfor (i= 0; i < 4; i++)\n\t\tsw_w32(r[i], rtl_table_data(q, i));\n\n\trtl_table_write(q, idx);\n\trtl_table_release(q);\n\n}\n\nstatic void rtl931x_vlan_fwd_on_inner(int port, bool is_set)\n{\n\t// Always set all tag modes to fwd based on either inner or outer tag\n\tif (is_set)\n\t\tsw_w32_mask(0, 0xf, RTL931X_VLAN_PORT_FWD + (port << 2));\n\telse\n\t\tsw_w32_mask(0xf, 0, RTL931X_VLAN_PORT_FWD + (port << 2));\n}\n\nstatic void rtl931x_vlan_profile_setup(int profile)\n{\n\tu32 p[7];\n\tint i;\n\n\tpr_info(\"In %s\\n\", __func__);\n\n\tif (profile > 15)\n\t\treturn;\n\n\tp[0] = sw_r32(RTL931X_VLAN_PROFILE_SET(profile));\n\n\t// Enable routing of Ipv4/6 Unicast and IPv4/6 Multicast traffic\n\t//p[0] |= BIT(17) | BIT(16) | BIT(13) | BIT(12);\n\tp[0] |= 0x3 << 11; // COPY2CPU\n\n\tp[1] = 0x1FFFFFF; // L2 unknwon MC flooding portmask all ports, including the CPU-port\n\tp[2] = 0xFFFFFFFF;\n\tp[3] = 0x1FFFFFF; // IPv4 unknwon MC flooding portmask\n\tp[4] = 0xFFFFFFFF;\n\tp[5] = 0x1FFFFFF; // IPv6 unknwon MC flooding portmask\n\tp[6] = 0xFFFFFFFF;\n\n\tfor (i = 0; i < 7; i++)\n\t\tsw_w32(p[i], RTL931X_VLAN_PROFILE_SET(profile) + i * 4);\n\tpr_info(\"Leaving %s\\n\", __func__);\n}\n\nstatic void rtl931x_l2_learning_setup(void)\n{\n\t// Portmask for flooding broadcast traffic\n\trtl839x_set_port_reg_be(0x1FFFFFFFFFFFFFF, RTL931X_L2_BC_FLD_PMSK);\n\n\t// Portmask for flooding unicast traffic with unknown destination\n\trtl839x_set_port_reg_be(0x1FFFFFFFFFFFFFF, RTL931X_L2_UNKN_UC_FLD_PMSK);\n\n\t// Limit learning to maximum: 64k entries, after that just flood (bits 0-2)\n\tsw_w32((0xffff << 3) | FORWARD, RTL931X_L2_LRN_CONSTRT_CTRL);\n}\n\nstatic u64 rtl931x_read_mcast_pmask(int idx)\n{\n\tu64 portmask;\n\t// Read MC_PMSK (2) via register RTL9310_TBL_0\n\tstruct table_reg *q = rtl_table_get(RTL9310_TBL_0, 2);\n\n\trtl_table_read(q, idx);\n\tportmask = sw_r32(rtl_table_data(q, 0));\n\tportmask <<= 32;\n\tportmask |= sw_r32(rtl_table_data(q, 1));\n\tportmask >>= 7;\n\trtl_table_release(q);\n\n\tpr_debug(\"%s: Index idx %d has portmask %016llx\\n\", __func__, idx, portmask);\n\treturn portmask;\n}\n\nstatic void rtl931x_write_mcast_pmask(int idx, u64 portmask)\n{\n\tu64 pm = portmask;\n\n\t// Access MC_PMSK (2) via register RTL9310_TBL_0\n\tstruct table_reg *q = rtl_table_get(RTL9310_TBL_0, 2);\n\n\tpr_debug(\"%s: Index idx %d has portmask %016llx\\n\", __func__, idx, pm);\n\tpm <<= 7;\n\tsw_w32((u32)(pm >> 32), rtl_table_data(q, 0));\n\tsw_w32((u32)pm, rtl_table_data(q, 1));\n\trtl_table_write(q, idx);\n\trtl_table_release(q);\n}\n\n\nstatic int rtl931x_set_ageing_time(unsigned long msec)\n{\n\tint t = sw_r32(RTL931X_L2_AGE_CTRL);\n\n\tt &= 0x1FFFFF;\n\tt = (t * 8) / 10;\n\tpr_debug(\"L2 AGING time: %d sec\\n\", t);\n\n\tt = (msec / 100 + 7) / 8;\n\tt = t > 0x1FFFFF ? 0x1FFFFF : t;\n\tsw_w32_mask(0x1FFFFF, t, RTL931X_L2_AGE_CTRL);\n\tpr_debug(\"Dynamic aging for ports: %x\\n\", sw_r32(RTL931X_L2_PORT_AGE_CTRL));\n\treturn 0;\n}\nvoid rtl931x_sw_init(struct rtl838x_switch_priv *priv)\n{\n//\trtl931x_sds_init(priv);\n}\n\nstatic void rtl931x_pie_lookup_enable(struct rtl838x_switch_priv *priv, int index)\n{\n\tint block = index / PIE_BLOCK_SIZE;\n\n\tsw_w32_mask(0, BIT(block), RTL931X_PIE_BLK_LOOKUP_CTRL);\n}\n\n/*\n * Fills the data in the intermediate representation in the pie_rule structure\n * into a data field for a given template field field_type\n * TODO: This function looks very similar to the function of the rtl9300, but\n * since it uses the physical template_field_id, which are different for each\n * SoC and there are other field types, it is actually not. If we would also use\n * an intermediate representation for a field type, we would could have one\n * pie_data_fill function for all SoCs, provided we have also for each SoC a\n * function to map between physical and intermediate field type\n */\nint rtl931x_pie_data_fill(enum template_field_id field_type, struct pie_rule *pr, u16 *data, u16 *data_m)\n{\n\t*data = *data_m = 0;\n\n\tswitch (field_type) {\n\tcase TEMPLATE_FIELD_SPM0:\n\t\t*data = pr->spm;\n\t\t*data_m = pr->spm_m;\n\t\tbreak;\n\tcase TEMPLATE_FIELD_SPM1:\n\t\t*data = pr->spm >> 16;\n\t\t*data_m = pr->spm_m >> 16;\n\t\tbreak;\n\tcase TEMPLATE_FIELD_OTAG:\n\t\t*data = pr->otag;\n\t\t*data_m = pr->otag_m;\n\t\tbreak;\n\tcase TEMPLATE_FIELD_SMAC0:\n\t\t*data = pr->smac[4];\n\t\t*data = (*data << 8) | pr->smac[5];\n\t\t*data_m = pr->smac_m[4];\n\t\t*data_m = (*data_m << 8) | pr->smac_m[5];\n\t\tbreak;\n\tcase TEMPLATE_FIELD_SMAC1:\n\t\t*data = pr->smac[2];\n\t\t*data = (*data << 8) | pr->smac[3];\n\t\t*data_m = pr->smac_m[2];\n\t\t*data_m = (*data_m << 8) | pr->smac_m[3];\n\t\tbreak;\n\tcase TEMPLATE_FIELD_SMAC2:\n\t\t*data = pr->smac[0];\n\t\t*data = (*data << 8) | pr->smac[1];\n\t\t*data_m = pr->smac_m[0];\n\t\t*data_m = (*data_m << 8) | pr->smac_m[1];\n\t\tbreak;\n\tcase TEMPLATE_FIELD_DMAC0:\n\t\t*data = pr->dmac[4];\n\t\t*data = (*data << 8) | pr->dmac[5];\n\t\t*data_m = pr->dmac_m[4];\n\t\t*data_m = (*data_m << 8) | pr->dmac_m[5];\n\t\tbreak;\n\tcase TEMPLATE_FIELD_DMAC1:\n\t\t*data = pr->dmac[2];\n\t\t*data = (*data << 8) | pr->dmac[3];\n\t\t*data_m = pr->dmac_m[2];\n\t\t*data_m = (*data_m << 8) | pr->dmac_m[3];\n\t\tbreak;\n\tcase TEMPLATE_FIELD_DMAC2:\n\t\t*data = pr->dmac[0];\n\t\t*data = (*data << 8) | pr->dmac[1];\n\t\t*data_m = pr->dmac_m[0];\n\t\t*data_m = (*data_m << 8) | pr->dmac_m[1];\n\t\tbreak;\n\tcase TEMPLATE_FIELD_ETHERTYPE:\n\t\t*data = pr->ethertype;\n\t\t*data_m = pr->ethertype_m;\n\t\tbreak;\n\tcase TEMPLATE_FIELD_ITAG:\n\t\t*data = pr->itag;\n\t\t*data_m = pr->itag_m;\n\t\tbreak;\n\tcase TEMPLATE_FIELD_SIP0:\n\t\tif (pr->is_ipv6) {\n\t\t\t*data = pr->sip6.s6_addr16[7];\n\t\t\t*data_m = pr->sip6_m.s6_addr16[7];\n\t\t} else {\n\t\t\t*data = pr->sip;\n\t\t\t*data_m = pr->sip_m;\n\t\t}\n\t\tbreak;\n\tcase TEMPLATE_FIELD_SIP1:\n\t\tif (pr->is_ipv6) {\n\t\t\t*data = pr->sip6.s6_addr16[6];\n\t\t\t*data_m = pr->sip6_m.s6_addr16[6];\n\t\t} else {\n\t\t\t*data = pr->sip >> 16;\n\t\t\t*data_m = pr->sip_m >> 16;\n\t\t}\n\t\tbreak;\n\tcase TEMPLATE_FIELD_SIP2:\n\tcase TEMPLATE_FIELD_SIP3:\n\tcase TEMPLATE_FIELD_SIP4:\n\tcase TEMPLATE_FIELD_SIP5:\n\tcase TEMPLATE_FIELD_SIP6:\n\tcase TEMPLATE_FIELD_SIP7:\n\t\t*data = pr->sip6.s6_addr16[5 - (field_type - TEMPLATE_FIELD_SIP2)];\n\t\t*data_m = pr->sip6_m.s6_addr16[5 - (field_type - TEMPLATE_FIELD_SIP2)];\n\t\tbreak;\n\n\tcase TEMPLATE_FIELD_DIP0:\n\t\tif (pr->is_ipv6) {\n\t\t\t*data = pr->dip6.s6_addr16[7];\n\t\t\t*data_m = pr->dip6_m.s6_addr16[7];\n\t\t} else {\n\t\t\t*data = pr->dip;\n\t\t\t*data_m = pr->dip_m;\n\t\t}\n\t\tbreak;\n\t\tcase TEMPLATE_FIELD_DIP1:\n\t\tif (pr->is_ipv6) {\n\t\t\t*data = pr->dip6.s6_addr16[6];\n\t\t\t*data_m = pr->dip6_m.s6_addr16[6];\n\t\t} else {\n\t\t\t*data = pr->dip >> 16;\n\t\t\t*data_m = pr->dip_m >> 16;\n\t\t}\n\t\tbreak;\n\n\tcase TEMPLATE_FIELD_DIP2:\n\tcase TEMPLATE_FIELD_DIP3:\n\tcase TEMPLATE_FIELD_DIP4:\n\tcase TEMPLATE_FIELD_DIP5:\n\tcase TEMPLATE_FIELD_DIP6:\n\tcase TEMPLATE_FIELD_DIP7:\n\t\t*data = pr->dip6.s6_addr16[5 - (field_type - TEMPLATE_FIELD_DIP2)];\n\t\t*data_m = pr->dip6_m.s6_addr16[5 - (field_type - TEMPLATE_FIELD_DIP2)];\n\t\tbreak;\n\n\tcase TEMPLATE_FIELD_IP_TOS_PROTO:\n\t\t*data = pr->tos_proto;\n\t\t*data_m = pr->tos_proto_m;\n\t\tbreak;\n\tcase TEMPLATE_FIELD_L4_SPORT:\n\t\t*data = pr->sport;\n\t\t*data_m = pr->sport_m;\n\t\tbreak;\n\tcase TEMPLATE_FIELD_L4_DPORT:\n\t\t*data = pr->dport;\n\t\t*data_m = pr->dport_m;\n\t\tbreak;\n\tcase TEMPLATE_FIELD_DSAP_SSAP:\n\t\t*data = pr->dsap_ssap;\n\t\t*data_m = pr->dsap_ssap_m;\n\t\tbreak;\n\tcase TEMPLATE_FIELD_TCP_INFO:\n\t\t*data = pr->tcp_info;\n\t\t*data_m = pr->tcp_info_m;\n\t\tbreak;\n\tcase TEMPLATE_FIELD_RANGE_CHK:\n\t\tpr_info(\"TEMPLATE_FIELD_RANGE_CHK: not configured\\n\");\n\t\tbreak;\n\tdefault:\n\t\tpr_info(\"%s: unknown field %d\\n\", __func__, field_type);\n\t\treturn -1;\n\t}\n\n\treturn 0;\n}\n\n/*\n * Reads the intermediate representation of the templated match-fields of the\n * PIE rule in the pie_rule structure and fills in the raw data fields in the\n * raw register space r[].\n * The register space configuration size is identical for the RTL8380/90 and RTL9300,\n * however the RTL931X has 2 more registers / fields and the physical field-ids are different\n * on all SoCs\n * On the RTL9300 the mask fields are not word-aligend!\n */\nstatic void rtl931x_write_pie_templated(u32 r[], struct pie_rule *pr, enum template_field_id t[])\n{\n\tint i;\n\tu16 data, data_m;\n\n\tfor (i = 0; i < N_FIXED_FIELDS; i++) {\n\t\trtl931x_pie_data_fill(t[i], pr, &data, &data_m);\n\n\t\t// On the RTL9300, the mask fields are not word aligned!\n\t\tif (!(i % 2)) {\n\t\t\tr[5 - i / 2] = data;\n\t\t\tr[12 - i / 2] |= ((u32)data_m << 8);\n\t\t} else {\n\t\t\tr[5 - i / 2] |= ((u32)data) << 16;\n\t\t\tr[12 - i / 2] |= ((u32)data_m) << 24;\n\t\t\tr[11 - i / 2] |= ((u32)data_m) >> 8;\n\t\t}\n\t}\n}\n\nstatic void rtl931x_read_pie_fixed_fields(u32 r[], struct pie_rule *pr)\n{\n\tpr->mgnt_vlan = r[7] & BIT(31);\n\tif (pr->phase == PHASE_IACL)\n\t\tpr->dmac_hit_sw = r[7] & BIT(30);\n\telse  // TODO: EACL/VACL phase handling\n\t\tpr->content_too_deep = r[7] & BIT(30);\n\tpr->not_first_frag = r[7]  & BIT(29);\n\tpr->frame_type_l4 = (r[7] >> 26) & 7;\n\tpr->frame_type = (r[7] >> 24) & 3;\n\tpr->otag_fmt = (r[7] >> 23) & 1;\n\tpr->itag_fmt = (r[7] >> 22) & 1;\n\tpr->otag_exist = (r[7] >> 21) & 1;\n\tpr->itag_exist = (r[7] >> 20) & 1;\n\tpr->frame_type_l2 = (r[7] >> 18) & 3;\n\tpr->igr_normal_port = (r[7] >> 17) & 1;\n\tpr->tid = (r[7] >> 16) & 1;\n\n\tpr->mgnt_vlan_m = r[14] & BIT(15);\n\tif (pr->phase == PHASE_IACL)\n\t\tpr->dmac_hit_sw_m = r[14] & BIT(14);\n\telse\n\t\tpr->content_too_deep_m = r[14] & BIT(14);\n\tpr->not_first_frag_m = r[14] & BIT(13);\n\tpr->frame_type_l4_m = (r[14] >> 10) & 7;\n\tpr->frame_type_m = (r[14] >> 8) & 3;\n\tpr->otag_fmt_m = r[14] & BIT(7);\n\tpr->itag_fmt_m = r[14] & BIT(6);\n\tpr->otag_exist_m = r[14] & BIT(5);\n\tpr->itag_exist_m = r[14] & BIT (4);\n\tpr->frame_type_l2_m = (r[14] >> 2) & 3;\n\tpr->igr_normal_port_m = r[14] & BIT(1);\n\tpr->tid_m = r[14] & 1;\n\n\tpr->valid = r[15] & BIT(31);\n\tpr->cond_not = r[15] & BIT(30);\n\tpr->cond_and1 = r[15] & BIT(29);\n\tpr->cond_and2 = r[15] & BIT(28);\n}\n\nstatic void rtl931x_write_pie_fixed_fields(u32 r[],  struct pie_rule *pr)\n{\n\tr[7] |= pr->mgnt_vlan ? BIT(31) : 0;\n\tif (pr->phase == PHASE_IACL)\n\t\tr[7] |= pr->dmac_hit_sw ? BIT(30) : 0;\n\telse\n\t\tr[7] |= pr->content_too_deep ? BIT(30) : 0;\n\tr[7] |= pr->not_first_frag ? BIT(29) : 0;\n\tr[7] |= ((u32) (pr->frame_type_l4 & 0x7)) << 26;\n\tr[7] |= ((u32) (pr->frame_type & 0x3)) << 24;\n\tr[7] |= pr->otag_fmt ? BIT(23) : 0;\n\tr[7] |= pr->itag_fmt ? BIT(22) : 0;\n\tr[7] |= pr->otag_exist ? BIT(21) : 0;\n\tr[7] |= pr->itag_exist ? BIT(20) : 0;\n\tr[7] |= ((u32) (pr->frame_type_l2 & 0x3)) << 18;\n\tr[7] |= pr->igr_normal_port ? BIT(17) : 0;\n\tr[7] |= ((u32) (pr->tid & 0x1)) << 16;\n\n\tr[14] |= pr->mgnt_vlan_m ? BIT(15) : 0;\n\tif (pr->phase == PHASE_IACL)\n\t\tr[14] |= pr->dmac_hit_sw_m ? BIT(14) : 0;\n\telse\n\t\tr[14] |= pr->content_too_deep_m ? BIT(14) : 0;\n\tr[14] |= pr->not_first_frag_m ? BIT(13) : 0;\n\tr[14] |= ((u32) (pr->frame_type_l4_m & 0x7)) << 10;\n\tr[14] |= ((u32) (pr->frame_type_m & 0x3)) << 8;\n\tr[14] |= pr->otag_fmt_m ? BIT(7) : 0;\n\tr[14] |= pr->itag_fmt_m ? BIT(6) : 0;\n\tr[14] |= pr->otag_exist_m ? BIT(5) : 0;\n\tr[14] |= pr->itag_exist_m ? BIT(4) : 0;\n\tr[14] |= ((u32) (pr->frame_type_l2_m & 0x3)) << 2;\n\tr[14] |= pr->igr_normal_port_m ? BIT(1) : 0;\n\tr[14] |= (u32) (pr->tid_m & 0x1);\n\n\tr[15] |= pr->valid ? BIT(31) : 0;\n\tr[15] |= pr->cond_not ? BIT(30) : 0;\n\tr[15] |= pr->cond_and1 ? BIT(29) : 0;\n\tr[15] |= pr->cond_and2 ? BIT(28) : 0;\n}\n\nstatic void rtl931x_write_pie_action(u32 r[],  struct pie_rule *pr)\n{\n\t// Either drop or forward\n\tif (pr->drop) {\n\t\tr[15] |= BIT(11) | BIT(12) | BIT(13); // Do Green, Yellow and Red drops\n\t\t// Actually DROP, not PERMIT in Green / Yellow / Red\n\t\tr[16] |= BIT(27) | BIT(28) | BIT(29);\n\t} else {\n\t\tr[15] |= pr->fwd_sel ? BIT(14) : 0;\n\t\tr[16] |= pr->fwd_act << 24;\n\t\tr[16] |= BIT(21); // We overwrite any drop\n\t}\n\tif (pr->phase == PHASE_VACL)\n\t\tr[16] |= pr->fwd_sa_lrn ? BIT(22) : 0;\n\tr[15] |= pr->bypass_sel ? BIT(10) : 0;\n\tr[15] |= pr->nopri_sel ? BIT(21) : 0;\n\tr[15] |= pr->tagst_sel ? BIT(20) : 0;\n\tr[15] |= pr->ovid_sel ? BIT(18) : 0;\n\tr[15] |= pr->ivid_sel ? BIT(16) : 0;\n\tr[15] |= pr->meter_sel ? BIT(27) : 0;\n\tr[15] |= pr->mir_sel ? BIT(15) : 0;\n\tr[15] |= pr->log_sel ? BIT(26) : 0;\n\n\tr[16] |= ((u32)(pr->fwd_data & 0xfff)) << 9;\n//\tr[15] |= pr->log_octets ? BIT(31) : 0;\n\tr[15] |= (u32)(pr->meter_data) >> 2;\n\tr[16] |= (((u32)(pr->meter_data) >> 7) & 0x3) << 29;\n\n\tr[16] |= ((u32)(pr->ivid_act & 0x3)) << 21;\n\tr[15] |= ((u32)(pr->ivid_data & 0xfff)) << 9;\n\tr[16] |= ((u32)(pr->ovid_act & 0x3)) << 30;\n\tr[16] |= ((u32)(pr->ovid_data & 0xfff)) << 16;\n\tr[16] |= ((u32)(pr->mir_data & 0x3)) << 6;\n\tr[17] |= ((u32)(pr->tagst_data & 0xf)) << 28;\n\tr[17] |= ((u32)(pr->nopri_data & 0x7)) << 25;\n\tr[17] |= pr->bypass_ibc_sc ? BIT(16) : 0;\n}\n\nvoid rtl931x_pie_rule_dump_raw(u32 r[])\n{\n\tpr_info(\"Raw IACL table entry:\\n\");\n\tpr_info(\"r 0 - 7: %08x %08x %08x %08x %08x %08x %08x %08x\\n\",\n\t\tr[0], r[1], r[2], r[3], r[4], r[5], r[6], r[7]);\n\tpr_info(\"r 8 - 15: %08x %08x %08x %08x %08x %08x %08x %08x\\n\",\n\t\tr[8], r[9], r[10], r[11], r[12], r[13], r[14], r[15]);\n\tpr_info(\"r 16 - 18: %08x %08x %08x\\n\", r[16], r[17], r[18]);\n\tpr_info(\"Match  : %08x %08x %08x %08x %08x %08x\\n\", r[0], r[1], r[2], r[3], r[4], r[5]);\n\tpr_info(\"Fixed  : %06x\\n\", r[6] >> 8);\n\tpr_info(\"Match M: %08x %08x %08x %08x %08x %08x\\n\",\n\t\t(r[6] << 24) | (r[7] >> 8), (r[7] << 24) | (r[8] >> 8), (r[8] << 24) | (r[9] >> 8),\n\t\t(r[9] << 24) | (r[10] >> 8), (r[10] << 24) | (r[11] >> 8),\n\t\t(r[11] << 24) | (r[12] >> 8));\n\tpr_info(\"R[13]:   %08x\\n\", r[13]);\n\tpr_info(\"Fixed M: %06x\\n\", ((r[12] << 16) | (r[13] >> 16)) & 0xffffff);\n\tpr_info(\"Valid / not / and1 / and2 : %1x\\n\", (r[13] >> 12) & 0xf);\n\tpr_info(\"r 13-16: %08x %08x %08x %08x\\n\", r[13], r[14], r[15], r[16]);\n}\n\nstatic int rtl931x_pie_rule_write(struct rtl838x_switch_priv *priv, int idx, struct pie_rule *pr)\n{\n\t// Access IACL table (0) via register 1, the table size is 4096\n\tstruct table_reg *q = rtl_table_get(RTL9310_TBL_1, 0);\n\tu32 r[22];\n\tint i;\n\tint block = idx / PIE_BLOCK_SIZE;\n\tu32 t_select = sw_r32(RTL931X_PIE_BLK_TMPLTE_CTRL(block));\n\n\tpr_info(\"%s: %d, t_select: %08x\\n\", __func__, idx, t_select);\n\n\tfor (i = 0; i < 22; i++)\n\t\tr[i] = 0;\n\n\tif (!pr->valid) {\n\t\trtl_table_write(q, idx);\n\t\trtl_table_release(q);\n\t\treturn 0;\n\t}\n\trtl931x_write_pie_fixed_fields(r, pr);\n\n\tpr_info(\"%s: template %d\\n\", __func__, (t_select >> (pr->tid * 4)) & 0xf);\n\trtl931x_write_pie_templated(r, pr, fixed_templates[(t_select >> (pr->tid * 4)) & 0xf]);\n\n\trtl931x_write_pie_action(r, pr);\n\n\trtl931x_pie_rule_dump_raw(r);\n\n\tfor (i = 0; i < 22; i++)\n\t\tsw_w32(r[i], rtl_table_data(q, i));\n\n\trtl_table_write(q, idx);\n\trtl_table_release(q);\n\n\treturn 0;\n}\n\nstatic bool rtl931x_pie_templ_has(int t, enum template_field_id field_type)\n{\n\tint i;\n\tenum template_field_id ft;\n\n\tfor (i = 0; i < N_FIXED_FIELDS_RTL931X; i++) {\n\t\tft = fixed_templates[t][i];\n\t\tif (field_type == ft)\n\t\t\treturn true;\n\t}\n\n\treturn false;\n}\n\n/*\n * Verify that the rule pr is compatible with a given template t in block block\n * Note that this function is SoC specific since the values of e.g. TEMPLATE_FIELD_SIP0\n * depend on the SoC\n */\nstatic int rtl931x_pie_verify_template(struct rtl838x_switch_priv *priv,\n\t\t\t\t       struct pie_rule *pr, int t, int block)\n{\n\tint i;\n\n\tif (!pr->is_ipv6 && pr->sip_m && !rtl931x_pie_templ_has(t, TEMPLATE_FIELD_SIP0))\n\t\treturn -1;\n\n\tif (!pr->is_ipv6 && pr->dip_m && !rtl931x_pie_templ_has(t, TEMPLATE_FIELD_DIP0))\n\t\treturn -1;\n\n\tif (pr->is_ipv6) {\n\t\tif ((pr->sip6_m.s6_addr32[0] || pr->sip6_m.s6_addr32[1]\n\t\t\t|| pr->sip6_m.s6_addr32[2] || pr->sip6_m.s6_addr32[3])\n\t\t\t&& !rtl931x_pie_templ_has(t, TEMPLATE_FIELD_SIP2))\n\t\t\treturn -1;\n\t\tif ((pr->dip6_m.s6_addr32[0] || pr->dip6_m.s6_addr32[1]\n\t\t\t|| pr->dip6_m.s6_addr32[2] || pr->dip6_m.s6_addr32[3])\n\t\t\t&& !rtl931x_pie_templ_has(t, TEMPLATE_FIELD_DIP2))\n\t\t\treturn -1;\n\t}\n\n\tif (ether_addr_to_u64(pr->smac) && !rtl931x_pie_templ_has(t, TEMPLATE_FIELD_SMAC0))\n\t\treturn -1;\n\n\tif (ether_addr_to_u64(pr->dmac) && !rtl931x_pie_templ_has(t, TEMPLATE_FIELD_DMAC0))\n\t\treturn -1;\n\n\t// TODO: Check more\n\n\ti = find_first_zero_bit(&priv->pie_use_bm[block * 4], PIE_BLOCK_SIZE);\n\n\tif (i >= PIE_BLOCK_SIZE)\n\t\treturn -1;\n\n\treturn i + PIE_BLOCK_SIZE * block;\n}\n\nstatic int rtl931x_pie_rule_add(struct rtl838x_switch_priv *priv, struct pie_rule *pr)\n{\n\tint idx, block, j, t;\n\tint min_block = 0;\n\tint max_block = priv->n_pie_blocks / 2;\n\n\tif (pr->is_egress) {\n\t\tmin_block = max_block;\n\t\tmax_block = priv->n_pie_blocks;\n\t}\n\tpr_info(\"In %s\\n\", __func__);\n\n\tmutex_lock(&priv->pie_mutex);\n\n\tfor (block = min_block; block < max_block; block++) {\n\t\tfor (j = 0; j < 2; j++) {\n\t\t\tt = (sw_r32(RTL931X_PIE_BLK_TMPLTE_CTRL(block)) >> (j * 4)) & 0xf;\n\t\t\tpr_info(\"Testing block %d, template %d, template id %d\\n\", block, j, t);\n\t\t\tpr_info(\"%s: %08x\\n\",\n\t\t\t\t__func__, sw_r32(RTL931X_PIE_BLK_TMPLTE_CTRL(block)));\n\t\t\tidx = rtl931x_pie_verify_template(priv, pr, t, block);\n\t\t\tif (idx >= 0)\n\t\t\t\tbreak;\n\t\t}\n\t\tif (j < 2)\n\t\t\tbreak;\n\t}\n\n\tif (block >= priv->n_pie_blocks) {\n\t\tmutex_unlock(&priv->pie_mutex);\n\t\treturn -EOPNOTSUPP;\n\t}\n\n\tpr_info(\"Using block: %d, index %d, template-id %d\\n\", block, idx, j);\n\tset_bit(idx, priv->pie_use_bm);\n\n\tpr->valid = true;\n\tpr->tid = j;  // Mapped to template number\n\tpr->tid_m = 0x1;\n\tpr->id = idx;\n\n\trtl931x_pie_lookup_enable(priv, idx);\n\trtl931x_pie_rule_write(priv, idx, pr);\n\n\tmutex_unlock(&priv->pie_mutex);\n\treturn 0;\n}\n\n/*\n * Delete a range of Packet Inspection Engine rules\n */\nstatic int rtl931x_pie_rule_del(struct rtl838x_switch_priv *priv, int index_from, int index_to)\n{\n\tu32 v = (index_from << 1)| (index_to << 13 ) | BIT(0);\n\n\tpr_info(\"%s: from %d to %d\\n\", __func__, index_from, index_to);\n\tmutex_lock(&priv->reg_mutex);\n\n\t// Write from-to and execute bit into control register\n\tsw_w32(v, RTL931X_PIE_CLR_CTRL);\n\n\t// Wait until command has completed\n\tdo {\n\t} while (sw_r32(RTL931X_PIE_CLR_CTRL) & BIT(0));\n\n\tmutex_unlock(&priv->reg_mutex);\n\treturn 0;\n}\n\nstatic void rtl931x_pie_rule_rm(struct rtl838x_switch_priv *priv, struct pie_rule *pr)\n{\n\tint idx = pr->id;\n\n\trtl931x_pie_rule_del(priv, idx, idx);\n\tclear_bit(idx, priv->pie_use_bm);\n}\n\nstatic void rtl931x_pie_init(struct rtl838x_switch_priv *priv)\n{\n\tint i;\n\tu32 template_selectors;\n\n\tmutex_init(&priv->pie_mutex);\n\n\tpr_info(\"%s\\n\", __func__);\n\t// Enable ACL lookup on all ports, including CPU_PORT\n\tfor (i = 0; i <= priv->cpu_port; i++)\n\t\tsw_w32(1, RTL931X_ACL_PORT_LOOKUP_CTRL(i));\n\n\t// Include IPG in metering\n\tsw_w32_mask(0, 1, RTL931X_METER_GLB_CTRL);\n\n\t// Delete all present rules, block size is 128 on all SoC families\n\trtl931x_pie_rule_del(priv, 0, priv->n_pie_blocks * 128 - 1);\n\n\t// Assign first half blocks 0-7 to VACL phase, second half to IACL\n\t// 3 bits are used for each block, values for PIE blocks are\n\t// 6: Disabled, 0: VACL, 1: IACL, 2: EACL\n\t// And for OpenFlow Flow blocks: 3: Ingress Flow table 0,\n\t// 4: Ingress Flow Table 3, 5: Egress flow table 0\n\tfor (i = 0; i < priv->n_pie_blocks; i++) {\n\t\tint pos = (i % 10) * 3;\n\t\tu32 r = RTL931X_PIE_BLK_PHASE_CTRL + 4 * (i / 10);\n\n\t\tif (i < priv->n_pie_blocks / 2)\n\t\t\tsw_w32_mask(0x7 << pos, 0, r);\n\t\telse\n\t\t\tsw_w32_mask(0x7 << pos, 1 << pos, r);\n\t}\n\n\t// Enable predefined templates 0, 1 for first quarter of all blocks\n\ttemplate_selectors = 0 | (1 << 4);\n\tfor (i = 0; i < priv->n_pie_blocks / 4; i++)\n\t\tsw_w32(template_selectors, RTL931X_PIE_BLK_TMPLTE_CTRL(i));\n\n\t// Enable predefined templates 2, 3 for second quarter of all blocks\n\ttemplate_selectors = 2 | (3 << 4);\n\tfor (i = priv->n_pie_blocks / 4; i < priv->n_pie_blocks / 2; i++)\n\t\tsw_w32(template_selectors, RTL931X_PIE_BLK_TMPLTE_CTRL(i));\n\n\t// Enable predefined templates 0, 1 for third quater of all blocks\n\ttemplate_selectors = 0 | (1 << 4);\n\tfor (i = priv->n_pie_blocks / 2; i < priv->n_pie_blocks * 3 / 4; i++)\n\t\tsw_w32(template_selectors, RTL931X_PIE_BLK_TMPLTE_CTRL(i));\n\n\t// Enable predefined templates 2, 3 for fourth quater of all blocks\n\ttemplate_selectors = 2 | (3 << 4);\n\tfor (i = priv->n_pie_blocks * 3 / 4; i < priv->n_pie_blocks; i++)\n\t\tsw_w32(template_selectors, RTL931X_PIE_BLK_TMPLTE_CTRL(i));\n\n}\n\nint rtl931x_l3_setup(struct rtl838x_switch_priv *priv)\n{\n\treturn 0;\n}\n\nvoid rtl931x_vlan_port_pvidmode_set(int port, enum pbvlan_type type, enum pbvlan_mode mode)\n{\n\tif (type == PBVLAN_TYPE_INNER)\n\t\tsw_w32_mask(0x3 << 12, mode << 12, RTL931X_VLAN_PORT_IGR_CTRL + (port << 2));\n\telse\n\t\tsw_w32_mask(0x3 << 26, mode << 26, RTL931X_VLAN_PORT_IGR_CTRL + (port << 2));\n}\n\nvoid rtl931x_vlan_port_pvid_set(int port, enum pbvlan_type type, int pvid)\n{\n\tif (type == PBVLAN_TYPE_INNER)\n\t\tsw_w32_mask(0xfff, pvid, RTL931X_VLAN_PORT_IGR_CTRL + (port << 2));\n\telse\n\t\tsw_w32_mask(0xfff << 14, pvid << 14, RTL931X_VLAN_PORT_IGR_CTRL + (port << 2));\n}\n\nstatic void rtl931x_set_igr_filter(int port, enum igr_filter state)\n{\n\tsw_w32_mask(0x3 << ((port & 0xf)<<1), state << ((port & 0xf)<<1),\n\t\t    RTL931X_VLAN_PORT_IGR_FLTR + (((port >> 4) << 2)));\n}\n\nstatic void rtl931x_set_egr_filter(int port,  enum egr_filter state)\n{\n\tsw_w32_mask(0x1 << (port % 0x20), state << (port % 0x20),\n\t\t    RTL931X_VLAN_PORT_EGR_FLTR + (((port >> 5) << 2)));\n}\n\nvoid rtl931x_set_distribution_algorithm(int group, int algoidx, u32 algomsk)\n{\n\tu32 l3shift = 0;\n\tu32 newmask = 0;\n\n\t/* TODO: for now we set algoidx to 0 */\n\talgoidx=0;\n\n\tif (algomsk & TRUNK_DISTRIBUTION_ALGO_SIP_BIT) {\n\t\tl3shift = 4;\n\t\tnewmask |= TRUNK_DISTRIBUTION_ALGO_L3_SIP_BIT;\n\t}\n\tif (algomsk & TRUNK_DISTRIBUTION_ALGO_DIP_BIT) {\n\t\tl3shift = 4;\n\t\tnewmask |= TRUNK_DISTRIBUTION_ALGO_L3_DIP_BIT;\n\t}\n\tif (algomsk & TRUNK_DISTRIBUTION_ALGO_SRC_L4PORT_BIT) {\n\t\tl3shift = 4;\n\t\tnewmask |= TRUNK_DISTRIBUTION_ALGO_L3_SRC_L4PORT_BIT;\n\t}\n\tif (algomsk & TRUNK_DISTRIBUTION_ALGO_SRC_L4PORT_BIT) {\n\t\tl3shift = 4;\n\t\tnewmask |= TRUNK_DISTRIBUTION_ALGO_L3_SRC_L4PORT_BIT;\n\t}\n\n\tif (l3shift == 4) {\n\t\tif (algomsk & TRUNK_DISTRIBUTION_ALGO_SMAC_BIT)\n\t\t\tnewmask |= TRUNK_DISTRIBUTION_ALGO_L3_SMAC_BIT;\n\t\tif (algomsk & TRUNK_DISTRIBUTION_ALGO_DMAC_BIT)\n\t\t\tnewmask |= TRUNK_DISTRIBUTION_ALGO_L3_DMAC_BIT;\n\t} else {\n\t\tif (algomsk & TRUNK_DISTRIBUTION_ALGO_SMAC_BIT)\n\t\t\tnewmask |= TRUNK_DISTRIBUTION_ALGO_L2_SMAC_BIT;\n\t\tif (algomsk & TRUNK_DISTRIBUTION_ALGO_DMAC_BIT)\n\t\t\tnewmask |= TRUNK_DISTRIBUTION_ALGO_L2_DMAC_BIT;\n\t}\n\n\tsw_w32(newmask << l3shift, RTL931X_TRK_HASH_CTRL + (algoidx << 2));\n}\n\nstatic void rtl931x_led_init(struct rtl838x_switch_priv *priv)\n{\n\tint i, pos;\n\tu32 v, set;\n\tu64 pm_copper = 0, pm_fiber = 0;\n\tu32 setlen;\n\tconst __be32 *led_set;\n\tchar set_name[9];\n\tstruct device_node *node;\n\n\tpr_info(\"%s called\\n\", __func__);\n\tnode = of_find_compatible_node(NULL, NULL, \"realtek,rtl9300-leds\");\n\tif (!node) {\n\t\tpr_info(\"%s No compatible LED node found\\n\", __func__);\n\t\treturn;\n\t}\n\n\tfor (i= 0; i < priv->cpu_port; i++) {\n\t\tpos = (i << 1) % 32;\n\t\tsw_w32_mask(0x3 << pos, 0, RTL931X_LED_PORT_FIB_SET_SEL_CTRL(i));\n\t\tsw_w32_mask(0x3 << pos, 0, RTL931X_LED_PORT_COPR_SET_SEL_CTRL(i));\n\n\t\tif (!priv->ports[i].phy)\n\t\t\tcontinue;\n\n\t\tv = 0x1; // Found on the EdgeCore, but we do not have any HW description\n\t\tsw_w32_mask(0x3 << pos, v << pos, RTL931X_LED_PORT_NUM_CTRL(i));\n\n\t\tif (priv->ports[i].phy_is_integrated)\n\t\tpm_fiber |= BIT_ULL(i);\n\t\t\telse\n\t\tpm_copper |= BIT_ULL(i);\n\n\t\tset = priv->ports[i].led_set;\n\t\tsw_w32_mask(0, set << pos, RTL931X_LED_PORT_COPR_SET_SEL_CTRL(i));\n\t\tsw_w32_mask(0, set << pos, RTL931X_LED_PORT_FIB_SET_SEL_CTRL(i));\n\t}\n\n\tfor (i = 0; i < 4; i++) {\n\t\tsprintf(set_name, \"led_set%d\", i);\n\t\tpr_info(\">%s<\\n\", set_name);\n\t\tled_set = of_get_property(node, set_name, &setlen);\n\t\tif (!led_set || setlen != 16)\n\t\t\tbreak;\n\t\tv = be32_to_cpup(led_set) << 16 | be32_to_cpup(led_set + 1);\n\t\tsw_w32(v, RTL931X_LED_SET0_0_CTRL - 4 - i * 8);\n\t\tv = be32_to_cpup(led_set + 2) << 16 | be32_to_cpup(led_set + 3);\n\t\tsw_w32(v, RTL931X_LED_SET0_0_CTRL - i * 8);\n\t}\n\n\t// Set LED mode to serial (0x1)\n\tsw_w32_mask(0x3, 0x1, RTL931X_LED_GLB_CTRL);\n\n\trtl839x_set_port_reg_le(pm_copper, RTL931X_LED_PORT_COPR_MASK_CTRL);\n\trtl839x_set_port_reg_le(pm_fiber, RTL931X_LED_PORT_FIB_MASK_CTRL);\n\trtl839x_set_port_reg_le(pm_copper | pm_fiber, RTL931X_LED_PORT_COMBO_MASK_CTRL);\n\n\tfor (i = 0; i < 32; i++)\n\t\tpr_info(\"%s %08x: %08x\\n\",__func__, 0xbb000600 + i * 4, sw_r32(0x0600 + i * 4));\n\n}\n\nconst struct rtl838x_reg rtl931x_reg = {\n\t.mask_port_reg_be = rtl839x_mask_port_reg_be,\n\t.set_port_reg_be = rtl839x_set_port_reg_be,\n\t.get_port_reg_be = rtl839x_get_port_reg_be,\n\t.mask_port_reg_le = rtl839x_mask_port_reg_le,\n\t.set_port_reg_le = rtl839x_set_port_reg_le,\n\t.get_port_reg_le = rtl839x_get_port_reg_le,\n\t.stat_port_rst = RTL931X_STAT_PORT_RST,\n\t.stat_rst = RTL931X_STAT_RST,\n\t.stat_port_std_mib = 0,  // Not defined\n\t.traffic_enable = rtl931x_traffic_enable,\n\t.traffic_disable = rtl931x_traffic_disable,\n\t.traffic_get = rtl931x_traffic_get,\n\t.traffic_set = rtl931x_traffic_set,\n\t.l2_ctrl_0 = RTL931X_L2_CTRL,\n\t.l2_ctrl_1 = RTL931X_L2_AGE_CTRL,\n\t.l2_port_aging_out = RTL931X_L2_PORT_AGE_CTRL,\n\t.set_ageing_time = rtl931x_set_ageing_time,\n\t// .smi_poll_ctrl does not exist\n\t.l2_tbl_flush_ctrl = RTL931X_L2_TBL_FLUSH_CTRL,\n\t.exec_tbl0_cmd = rtl931x_exec_tbl0_cmd,\n\t.exec_tbl1_cmd = rtl931x_exec_tbl1_cmd,\n\t.tbl_access_data_0 = rtl931x_tbl_access_data_0,\n\t.isr_glb_src = RTL931X_ISR_GLB_SRC,\n\t.isr_port_link_sts_chg = RTL931X_ISR_PORT_LINK_STS_CHG,\n\t.imr_port_link_sts_chg = RTL931X_IMR_PORT_LINK_STS_CHG,\n\t// imr_glb does not exist on RTL931X\n\t.vlan_tables_read = rtl931x_vlan_tables_read,\n\t.vlan_set_tagged = rtl931x_vlan_set_tagged,\n\t.vlan_set_untagged = rtl931x_vlan_set_untagged,\n\t.vlan_profile_dump = rtl931x_vlan_profile_dump,\n\t.vlan_profile_setup = rtl931x_vlan_profile_setup,\n\t.vlan_fwd_on_inner = rtl931x_vlan_fwd_on_inner,\n\t.stp_get = rtl931x_stp_get,\n\t.stp_set = rtl931x_stp_set,\n\t.mac_force_mode_ctrl = rtl931x_mac_force_mode_ctrl,\n\t.mac_port_ctrl = rtl931x_mac_port_ctrl,\n\t.l2_port_new_salrn = rtl931x_l2_port_new_salrn,\n\t.l2_port_new_sa_fwd = rtl931x_l2_port_new_sa_fwd,\n\t.mir_ctrl = RTL931X_MIR_CTRL,\n\t.mir_dpm = RTL931X_MIR_DPM_CTRL,\n\t.mir_spm = RTL931X_MIR_SPM_CTRL,\n\t.mac_link_sts = RTL931X_MAC_LINK_STS,\n\t.mac_link_dup_sts = RTL931X_MAC_LINK_DUP_STS,\n\t.mac_link_spd_sts = rtl931x_mac_link_spd_sts,\n\t.mac_rx_pause_sts = RTL931X_MAC_RX_PAUSE_STS,\n\t.mac_tx_pause_sts = RTL931X_MAC_TX_PAUSE_STS,\n\t.read_l2_entry_using_hash = rtl931x_read_l2_entry_using_hash,\n\t.write_l2_entry_using_hash = rtl931x_write_l2_entry_using_hash,\n\t.read_cam = rtl931x_read_cam,\n\t.write_cam = rtl931x_write_cam,\n\t.vlan_port_tag_sts_ctrl = RTL931X_VLAN_PORT_TAG_CTRL,\n\t.vlan_port_pvidmode_set = rtl931x_vlan_port_pvidmode_set,\n\t.vlan_port_pvid_set = rtl931x_vlan_port_pvid_set,\n\t.trk_mbr_ctr = rtl931x_trk_mbr_ctr,\n\t.set_vlan_igr_filter = rtl931x_set_igr_filter,\n\t.set_vlan_egr_filter = rtl931x_set_egr_filter,\n\t.set_distribution_algorithm = rtl931x_set_distribution_algorithm,\n\t.l2_hash_key = rtl931x_l2_hash_key,\n\t.read_mcast_pmask = rtl931x_read_mcast_pmask,\n\t.write_mcast_pmask = rtl931x_write_mcast_pmask,\n\t.pie_init = rtl931x_pie_init,\n\t.pie_rule_write = rtl931x_pie_rule_write,\n\t.pie_rule_add = rtl931x_pie_rule_add,\n\t.pie_rule_rm = rtl931x_pie_rule_rm,\n\t.l2_learning_setup = rtl931x_l2_learning_setup,\n\t.l3_setup = rtl931x_l3_setup,\n\t.led_init = rtl931x_led_init,\n};\n\n"
  },
  {
    "path": "target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/tc.c",
    "content": "// SPDX-License-Identifier: GPL-2.0-only\n\n#include <net/dsa.h>\n#include <linux/delay.h>\n#include <linux/netdevice.h>\n#include <net/flow_offload.h>\n#include <linux/rhashtable.h>\n\n#include <asm/mach-rtl838x/mach-rtl83xx.h>\n#include \"rtl83xx.h\"\n#include \"rtl838x.h\"\n\n/*\n * Parse the flow rule for the matching conditions\n */\nstatic int rtl83xx_parse_flow_rule(struct rtl838x_switch_priv *priv,\n\t\t\t      struct flow_rule *rule, struct rtl83xx_flow *flow)\n{\n\tstruct flow_dissector *dissector = rule->match.dissector;\n\n\tpr_debug(\"In %s\\n\", __func__);\n\t/* KEY_CONTROL and KEY_BASIC are needed for forming a meaningful key */\n\tif ((dissector->used_keys & BIT(FLOW_DISSECTOR_KEY_CONTROL)) == 0 ||\n\t    (dissector->used_keys & BIT(FLOW_DISSECTOR_KEY_BASIC)) == 0) {\n\t\tpr_err(\"Cannot form TC key: used_keys = 0x%x\\n\", dissector->used_keys);\n\t\treturn -EOPNOTSUPP;\n\t}\n\n\tif (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) {\n\t\tstruct flow_match_basic match;\n\n\t\tpr_debug(\"%s: BASIC\\n\", __func__);\n\t\tflow_rule_match_basic(rule, &match);\n\t\tif (match.key->n_proto == htons(ETH_P_ARP))\n\t\t\tflow->rule.frame_type = 0;\n\t\tif (match.key->n_proto == htons(ETH_P_IP))\n\t\t\tflow->rule.frame_type = 2;\n\t\tif (match.key->n_proto == htons(ETH_P_IPV6))\n\t\t\tflow->rule.frame_type = 3;\n\t\tif ((match.key->n_proto == htons(ETH_P_ARP)) || flow->rule.frame_type)\n\t\t\tflow->rule.frame_type_m = 3;\n\t\tif (flow->rule.frame_type >= 2) {\n\t\t\tif (match.key->ip_proto == IPPROTO_UDP)\n\t\t\t\tflow->rule.frame_type_l4 = 0;\n\t\t\tif (match.key->ip_proto == IPPROTO_TCP)\n\t\t\t\tflow->rule.frame_type_l4 = 1;\n\t\t\tif (match.key->ip_proto == IPPROTO_ICMP\n\t\t\t\t|| match.key->ip_proto ==IPPROTO_ICMPV6)\n\t\t\t\tflow->rule.frame_type_l4 = 2;\n\t\t\tif (match.key->ip_proto == IPPROTO_TCP)\n\t\t\t\tflow->rule.frame_type_l4 = 3;\n\t\t\tif ((match.key->ip_proto == IPPROTO_UDP) || flow->rule.frame_type_l4)\n\t\t\t\tflow->rule.frame_type_l4_m = 7;\n\t\t}\n\t}\n\n\tif (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) {\n\t\tstruct flow_match_eth_addrs match;\n\n\t\tpr_debug(\"%s: ETH_ADDR\\n\", __func__);\n\t\tflow_rule_match_eth_addrs(rule, &match);\n\t\tether_addr_copy(flow->rule.dmac, match.key->dst);\n\t\tether_addr_copy(flow->rule.dmac_m, match.mask->dst);\n\t\tether_addr_copy(flow->rule.smac, match.key->src);\n\t\tether_addr_copy(flow->rule.smac_m, match.mask->src);\n\t}\n\n\tif (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN)) {\n\t\tstruct flow_match_vlan match;\n\n\t\tpr_debug(\"%s: VLAN\\n\", __func__);\n\t\tflow_rule_match_vlan(rule, &match);\n\t\tflow->rule.itag = match.key->vlan_id;\n\t\tflow->rule.itag_m = match.mask->vlan_id;\n\t\t// TODO: What about match.key->vlan_priority ?\n\t}\n\n\tif (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_IPV4_ADDRS)) {\n\t\tstruct flow_match_ipv4_addrs match;\n\n\t\tpr_debug(\"%s: IPV4\\n\", __func__);\n\t\tflow_rule_match_ipv4_addrs(rule, &match);\n\t\tflow->rule.is_ipv6 = false;\n\t\tflow->rule.dip = match.key->dst;\n\t\tflow->rule.dip_m = match.mask->dst;\n\t\tflow->rule.sip = match.key->src;\n\t\tflow->rule.sip_m = match.mask->src;\n\t} else if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_IPV6_ADDRS)) {\n\t\tstruct flow_match_ipv6_addrs match;\n\n\t\tpr_debug(\"%s: IPV6\\n\", __func__);\n\t\tflow->rule.is_ipv6 = true;\n\t\tflow_rule_match_ipv6_addrs(rule, &match);\n\t\tflow->rule.dip6 = match.key->dst;\n\t\tflow->rule.dip6_m = match.mask->dst;\n\t\tflow->rule.sip6 = match.key->src;\n\t\tflow->rule.sip6_m = match.mask->src;\n\t}\n\n\tif (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_PORTS)) {\n\t\tstruct flow_match_ports match;\n\n\t\tpr_debug(\"%s: PORTS\\n\", __func__);\n\t\tflow_rule_match_ports(rule, &match);\n\t\tflow->rule.dport = match.key->dst;\n\t\tflow->rule.dport_m = match.mask->dst;\n\t\tflow->rule.sport = match.key->src;\n\t\tflow->rule.sport_m = match.mask->src;\n\t}\n\n\t// TODO: ICMP\n\treturn 0;\n}\n\nstatic void rtl83xx_flow_bypass_all(struct rtl83xx_flow *flow)\n{\n\tflow->rule.bypass_sel = true;\n\tflow->rule.bypass_all = true;\n\tflow->rule.bypass_igr_stp = true;\n\tflow->rule.bypass_ibc_sc = true;\n}\n\nstatic int rtl83xx_parse_fwd(struct rtl838x_switch_priv *priv,\n\t\t\t     const struct flow_action_entry *act, struct rtl83xx_flow *flow)\n{\n\tstruct net_device *dev = act->dev;\n\tint port;\n\n\tport = rtl83xx_port_is_under(dev, priv);\n\tif (port < 0) {\n\t\tnetdev_info(dev, \"%s: not a DSA device.\\n\", __func__);\n\t\treturn -EINVAL;\n\t}\n\n\tflow->rule.fwd_sel = true;\n\tflow->rule.fwd_data = port;\n\tpr_debug(\"Using port index: %d\\n\", port);\n\trtl83xx_flow_bypass_all(flow);\n\n\treturn 0;\n}\n\nstatic int rtl83xx_add_flow(struct rtl838x_switch_priv *priv, struct flow_cls_offload *f,\n\t\t\t    struct rtl83xx_flow *flow)\n{\n\tstruct flow_rule *rule = flow_cls_offload_flow_rule(f);\n\tconst struct flow_action_entry *act;\n\tint i, err;\n\n\tpr_debug(\"%s\\n\", __func__);\n\n\trtl83xx_parse_flow_rule(priv, rule, flow);\n\t\n\tflow_action_for_each(i, act, &rule->action) {\n\t\tswitch (act->id) {\n\t\tcase FLOW_ACTION_DROP:\n\t\t\tpr_debug(\"%s: DROP\\n\", __func__);\n\t\t\tflow->rule.drop = true;\n\t\t\trtl83xx_flow_bypass_all(flow);\n\t\t\treturn 0;\n\n\t\tcase FLOW_ACTION_TRAP:\n\t\t\tpr_debug(\"%s: TRAP\\n\", __func__);\n\t\t\tflow->rule.fwd_data = priv->cpu_port;\n\t\t\tflow->rule.fwd_act = PIE_ACT_REDIRECT_TO_PORT;\n\t\t\trtl83xx_flow_bypass_all(flow);\n\t\t\tbreak;\n\n\t\tcase FLOW_ACTION_MANGLE:\n\t\t\tpr_err(\"%s: FLOW_ACTION_MANGLE not supported\\n\", __func__);\n\t\t\treturn -EOPNOTSUPP;\n\n\t\tcase FLOW_ACTION_ADD:\n\t\t\tpr_err(\"%s: FLOW_ACTION_ADD not supported\\n\", __func__);\n\t\t\treturn -EOPNOTSUPP;\n\n\t\tcase FLOW_ACTION_VLAN_PUSH:\n\t\t\tpr_debug(\"%s: VLAN_PUSH\\n\", __func__);\n//\t\t\tTODO: act->vlan.proto\n\t\t\tflow->rule.ivid_act = PIE_ACT_VID_ASSIGN;\n\t\t\tflow->rule.ivid_sel = true;\n\t\t\tflow->rule.ivid_data = htons(act->vlan.vid);\n\t\t\tflow->rule.ovid_act = PIE_ACT_VID_ASSIGN;\n\t\t\tflow->rule.ovid_sel = true;\n\t\t\tflow->rule.ovid_data = htons(act->vlan.vid);\n\t\t\tflow->rule.fwd_mod_to_cpu = true;\n\t\t\tbreak;\n\n\t\tcase FLOW_ACTION_VLAN_POP:\n\t\t\tpr_debug(\"%s: VLAN_POP\\n\", __func__);\n\t\t\tflow->rule.ivid_act = PIE_ACT_VID_ASSIGN;\n\t\t\tflow->rule.ivid_data = 0;\n\t\t\tflow->rule.ivid_sel = true;\n\t\t\tflow->rule.ovid_act = PIE_ACT_VID_ASSIGN;\n\t\t\tflow->rule.ovid_data = 0;\n\t\t\tflow->rule.ovid_sel = true;\n\t\t\tflow->rule.fwd_mod_to_cpu = true;\n\t\t\tbreak;\n\n\t\tcase FLOW_ACTION_CSUM:\n\t\t\tpr_err(\"%s: FLOW_ACTION_CSUM not supported\\n\", __func__);\n\t\t\treturn -EOPNOTSUPP;\n\n\t\tcase FLOW_ACTION_REDIRECT:\n\t\t\tpr_debug(\"%s: REDIRECT\\n\", __func__);\n\t\t\terr = rtl83xx_parse_fwd(priv, act, flow);\n\t\t\tif (err)\n\t\t\t\treturn err;\n\t\t\tflow->rule.fwd_act = PIE_ACT_REDIRECT_TO_PORT;\n\t\t\tbreak;\n\n\t\tcase FLOW_ACTION_MIRRED:\n\t\t\tpr_debug(\"%s: MIRRED\\n\", __func__);\n\t\t\terr = rtl83xx_parse_fwd(priv, act, flow);\n\t\t\tif (err)\n\t\t\t\treturn err;\n\t\t\tflow->rule.fwd_act = PIE_ACT_COPY_TO_PORT;\n\t\t\tbreak;\n\n\t\tdefault:\n\t\t\tpr_err(\"%s: Flow action not supported: %d\\n\", __func__, act->id);\n\t\t\treturn -EOPNOTSUPP;\n\t\t}\n\t}\n\n\treturn 0;\n}\n\nstatic const struct rhashtable_params tc_ht_params = {\n\t.head_offset = offsetof(struct rtl83xx_flow, node),\n\t.key_offset = offsetof(struct rtl83xx_flow, cookie),\n\t.key_len = sizeof(((struct rtl83xx_flow *)0)->cookie),\n\t.automatic_shrinking = true,\n};\n\nstatic int rtl83xx_configure_flower(struct rtl838x_switch_priv *priv,\n\t\t\t\t    struct flow_cls_offload *f)\n{\n\tstruct rtl83xx_flow *flow;\n\tint err = 0;\n\n\tpr_debug(\"In %s\\n\", __func__);\n\n\trcu_read_lock();\n\tpr_debug(\"Cookie %08lx\\n\", f->cookie);\n\tflow = rhashtable_lookup(&priv->tc_ht, &f->cookie, tc_ht_params);\n\tif (flow) {\n\t\tpr_info(\"%s: Got flow\\n\", __func__);\n\t\terr = -EEXIST;\n\t\tgoto rcu_unlock;\n\t}\n\nrcu_unlock:\n\trcu_read_unlock();\n\tif (flow)\n\t\tgoto out;\n\tpr_debug(\"%s: New flow\\n\", __func__);\n\n\tflow = kzalloc(sizeof(*flow), GFP_KERNEL);\n\tif (!flow) {\n\t\terr = -ENOMEM;\n\t\tgoto out;\n\t}\n\n\tflow->cookie = f->cookie;\n\tflow->priv = priv;\n\n\terr = rhashtable_insert_fast(&priv->tc_ht, &flow->node, tc_ht_params);\n\tif (err) {\n\t\tpr_err(\"Could not insert add new rule\\n\");\n\t\tgoto out_free;\n\t}\n\n\trtl83xx_add_flow(priv, f, flow); // TODO: check error\n\n\t// Add log action to flow\n\tflow->rule.packet_cntr = rtl83xx_packet_cntr_alloc(priv);\n\tif (flow->rule.packet_cntr >= 0) {\n\t\tpr_debug(\"Using packet counter %d\\n\", flow->rule.packet_cntr);\n\t\tflow->rule.log_sel = true;\n\t\tflow->rule.log_data = flow->rule.packet_cntr;\n\t}\n\n\terr = priv->r->pie_rule_add(priv, &flow->rule);\n\treturn err;\n\nout_free:\n\tkfree(flow);\nout:\n\tpr_err(\"%s: error %d\\n\", __func__, err);\n\treturn err;\n}\n\nstatic int rtl83xx_delete_flower(struct rtl838x_switch_priv *priv,\n\t\t\t\t struct flow_cls_offload * cls_flower)\n{\n\tstruct rtl83xx_flow *flow;\n\n\tpr_debug(\"In %s\\n\", __func__);\n\trcu_read_lock();\n\tflow = rhashtable_lookup_fast(&priv->tc_ht, &cls_flower->cookie, tc_ht_params);\n\tif (!flow) {\n\t\trcu_read_unlock();\n\t\treturn -EINVAL;\n\t}\n\n\tpriv->r->pie_rule_rm(priv, &flow->rule);\n\n\trhashtable_remove_fast(&priv->tc_ht, &flow->node, tc_ht_params);\n\n\tkfree_rcu(flow, rcu_head);\n\n\trcu_read_unlock();\n\treturn 0;\n}\n\nstatic int rtl83xx_stats_flower(struct rtl838x_switch_priv *priv,\n\t\t\t\tstruct flow_cls_offload * cls_flower)\n{\n\tstruct rtl83xx_flow *flow;\n\tunsigned long lastused = 0;\n\tint total_packets, new_packets;\n\n\tpr_debug(\"%s: \\n\", __func__);\n\tflow = rhashtable_lookup_fast(&priv->tc_ht, &cls_flower->cookie, tc_ht_params);\n\tif (!flow)\n\t\treturn -1;\n\n\tif (flow->rule.packet_cntr >= 0) {\n\t\ttotal_packets = priv->r->packet_cntr_read(flow->rule.packet_cntr);\n\t\tpr_debug(\"Total packets: %d\\n\", total_packets);\n\t\tnew_packets = total_packets - flow->rule.last_packet_cnt;\n\t\tflow->rule.last_packet_cnt = total_packets;\n\t}\n\n\t// TODO: We need a second PIE rule to count the bytes\n\tflow_stats_update(&cls_flower->stats, 100 * new_packets, new_packets, 0, lastused,\n\t\t\t  FLOW_ACTION_HW_STATS_IMMEDIATE);\n\treturn 0;\n}\n\nstatic int rtl83xx_setup_tc_cls_flower(struct rtl838x_switch_priv *priv,\n\t\t\t\t       struct flow_cls_offload *cls_flower)\n{\n\tpr_debug(\"%s: %d\\n\", __func__, cls_flower->command);\n\tswitch (cls_flower->command) {\n\tcase FLOW_CLS_REPLACE:\n\t\treturn rtl83xx_configure_flower(priv, cls_flower);\n\tcase FLOW_CLS_DESTROY:\n\t\treturn rtl83xx_delete_flower(priv, cls_flower);\n\tcase FLOW_CLS_STATS:\n\t\treturn rtl83xx_stats_flower(priv, cls_flower);\n\tdefault:\n\t\treturn -EOPNOTSUPP;\n\t}\n}\n\n\nstatic int rtl83xx_setup_tc_block_cb(enum tc_setup_type type, void *type_data,\n\t\t\t\t     void *cb_priv)\n{\n\tstruct rtl838x_switch_priv *priv = cb_priv;\n\n\tswitch (type) {\n\tcase TC_SETUP_CLSFLOWER:\n\t\tpr_debug(\"%s: TC_SETUP_CLSFLOWER\\n\", __func__);\n\t\treturn rtl83xx_setup_tc_cls_flower(priv, type_data);\n\tdefault:\n\t\treturn -EOPNOTSUPP;\n\t}\n}\n\nstatic LIST_HEAD(rtl83xx_block_cb_list);\n\nint rtl83xx_setup_tc(struct net_device *dev, enum tc_setup_type type, void *type_data)\n{\n\tstruct rtl838x_switch_priv *priv;\n\tstruct flow_block_offload *f = type_data;\n\tstatic bool first_time = true;\n\tint err;\n\n\tpr_debug(\"%s: %d\\n\", __func__, type);\n\n\tif(!netdev_uses_dsa(dev)) {\n\t\tpr_err(\"%s: no DSA\\n\", __func__);\n\t\treturn 0;\n\t}\n\tpriv = dev->dsa_ptr->ds->priv;\n\n\tswitch (type) {\n\tcase TC_SETUP_BLOCK:\n\t\tif (first_time) {\n\t\t\tfirst_time = false;\n\t\t\terr = rhashtable_init(&priv->tc_ht, &tc_ht_params);\n\t\t\tif (err)\n\t\t\t\tpr_err(\"%s: Could not initialize hash table\\n\", __func__);\n\t\t}\n\n\t\tf->unlocked_driver_cb = true;\n\t\treturn flow_block_cb_setup_simple(type_data,\n\t\t\t\t\t\t  &rtl83xx_block_cb_list,\n\t\t\t\t\t\t  rtl83xx_setup_tc_block_cb,\n\t\t\t\t\t\t  priv, priv, true);\n\tdefault:\n\t\treturn -EOPNOTSUPP;\n\t}\n\n\treturn 0;\n}\n"
  },
  {
    "path": "target/linux/realtek/files-5.10/drivers/net/ethernet/rtl838x_eth.c",
    "content": "// SPDX-License-Identifier: GPL-2.0-only\n/*\n * linux/drivers/net/ethernet/rtl838x_eth.c\n * Copyright (C) 2020 B. Koblitz\n */\n\n#include <linux/dma-mapping.h>\n#include <linux/etherdevice.h>\n#include <linux/interrupt.h>\n#include <linux/io.h>\n#include <linux/platform_device.h>\n#include <linux/sched.h>\n#include <linux/slab.h>\n#include <linux/of.h>\n#include <linux/of_net.h>\n#include <linux/of_mdio.h>\n#include <linux/module.h>\n#include <linux/phylink.h>\n#include <linux/pkt_sched.h>\n#include <net/dsa.h>\n#include <net/switchdev.h>\n#include <asm/cacheflush.h>\n\n#include <asm/mach-rtl838x/mach-rtl83xx.h>\n#include \"rtl838x_eth.h\"\n\nextern struct rtl83xx_soc_info soc_info;\n\n/*\n * Maximum number of RX rings is 8 on RTL83XX and 32 on the 93XX\n * The ring is assigned by switch based on packet/port priortity\n * Maximum number of TX rings is 2, Ring 2 being the high priority\n * ring on the RTL93xx SoCs. MAX_RXLEN gives the maximum length\n * for an RX ring, MAX_ENTRIES the maximum number of entries\n * available in total for all queues.\n */\n#define MAX_RXRINGS\t32\n#define MAX_RXLEN\t300\n#define MAX_ENTRIES\t(300 * 8)\n#define TXRINGS\t\t2\n#define TXRINGLEN\t160\n#define NOTIFY_EVENTS\t10\n#define NOTIFY_BLOCKS\t10\n#define TX_EN\t\t0x8\n#define RX_EN\t\t0x4\n#define TX_EN_93XX\t0x20\n#define RX_EN_93XX\t0x10\n#define TX_DO\t\t0x2\n#define WRAP\t\t0x2\n#define MAX_PORTS\t57\n#define MAX_SMI_BUSSES\t4\n\n#define RING_BUFFER\t1600\n\nstruct p_hdr {\n\tuint8_t\t\t*buf;\n\tuint16_t\treserved;\n\tuint16_t\tsize;\t\t/* buffer size */\n\tuint16_t\toffset;\n\tuint16_t\tlen;\t\t/* pkt len */\n\tuint16_t\tcpu_tag[10];\n} __packed __aligned(1);\n\nstruct n_event {\n\tuint32_t\ttype:2;\n\tuint32_t\tfidVid:12;\n\tuint64_t\tmac:48;\n\tuint32_t\tslp:6;\n\tuint32_t\tvalid:1;\n\tuint32_t\treserved:27;\n} __packed __aligned(1);\n\nstruct ring_b {\n\tuint32_t\trx_r[MAX_RXRINGS][MAX_RXLEN];\n\tuint32_t\ttx_r[TXRINGS][TXRINGLEN];\n\tstruct\tp_hdr\trx_header[MAX_RXRINGS][MAX_RXLEN];\n\tstruct\tp_hdr\ttx_header[TXRINGS][TXRINGLEN];\n\tuint32_t\tc_rx[MAX_RXRINGS];\n\tuint32_t\tc_tx[TXRINGS];\n\tuint8_t\t\ttx_space[TXRINGS * TXRINGLEN * RING_BUFFER];\n\tuint8_t\t\t*rx_space;\n};\n\nstruct notify_block {\n\tstruct n_event\tevents[NOTIFY_EVENTS];\n};\n\nstruct notify_b {\n\tstruct notify_block\tblocks[NOTIFY_BLOCKS];\n\tu32\t\t\treserved1[8];\n\tu32\t\t\tring[NOTIFY_BLOCKS];\n\tu32\t\t\treserved2[8];\n};\n\nstatic void rtl838x_create_tx_header(struct p_hdr *h, int dest_port, int prio)\n{\n\tprio &= 0x7;\n\n\tif (dest_port > 0) {\n\t\t// cpu_tag[0] is reserved on the RTL83XX SoCs\n\t\th->cpu_tag[1] = 0x0401;  // BIT 10: RTL8380_CPU_TAG, BIT0: L2LEARNING on\n\t\th->cpu_tag[2] = 0x0200;  // Set only AS_DPM, to enable DPM settings below\n\t\th->cpu_tag[3] = 0x0000;\n\t\th->cpu_tag[4] = BIT(dest_port) >> 16;\n\t\th->cpu_tag[5] = BIT(dest_port) & 0xffff;\n\t\t// Set internal priority and AS_PRIO\n\t\tif (prio >= 0)\n\t\t\th->cpu_tag[2] |= (prio | 0x8) << 12;\n\t}\n}\n\nstatic void rtl839x_create_tx_header(struct p_hdr *h, int dest_port, int prio)\n{\n\tprio &= 0x7;\n\n\tif (dest_port > 0) {\n\t\t// cpu_tag[0] is reserved on the RTL83XX SoCs\n\t\th->cpu_tag[1] = 0x0100; // RTL8390_CPU_TAG marker\n\t\th->cpu_tag[2] = h->cpu_tag[3] = h->cpu_tag[4] = h->cpu_tag[5] = 0;\n\t\t// h->cpu_tag[1] |= BIT(1) | BIT(0); // Bypass filter 1/2\n\t\tif (dest_port >= 32) {\n\t\t\tdest_port -= 32;\n\t\t\th->cpu_tag[2] = BIT(dest_port) >> 16;\n\t\t\th->cpu_tag[3] = BIT(dest_port) & 0xffff;\n\t\t} else {\n\t\t\th->cpu_tag[4] = BIT(dest_port) >> 16;\n\t\t\th->cpu_tag[5] = BIT(dest_port) & 0xffff;\n\t\t}\n\t\th->cpu_tag[2] |= BIT(5); // Enable destination port mask use\n\t\th->cpu_tag[2] |= BIT(8); // Enable L2 Learning\n\t\t// Set internal priority and AS_PRIO\n\t\tif (prio >= 0)\n\t\t\th->cpu_tag[1] |= prio | BIT(3);\n\t}\n}\n\nstatic void rtl930x_create_tx_header(struct p_hdr *h, int dest_port, int prio)\n{\n\th->cpu_tag[0] = 0x8000;  // CPU tag marker\n\th->cpu_tag[1] = h->cpu_tag[2] = 0;\n\tif (prio >= 0)\n\t\th->cpu_tag[2] = BIT(13) | prio << 8; // Enable and set Priority Queue\n\th->cpu_tag[3] = 0;\n\th->cpu_tag[4] = 0;\n\th->cpu_tag[5] = 0;\n\th->cpu_tag[6] = BIT(dest_port) >> 16;\n\th->cpu_tag[7] = BIT(dest_port) & 0xffff;\n}\n\nstatic void rtl931x_create_tx_header(struct p_hdr *h, int dest_port, int prio)\n{\n\th->cpu_tag[0] = 0x8000;  // CPU tag marker\n\th->cpu_tag[1] = h->cpu_tag[2] = 0;\n\tif (prio >= 0)\n\t\th->cpu_tag[2] = BIT(13) | prio << 8; // Enable and set Priority Queue\n\th->cpu_tag[3] = 0;\n\th->cpu_tag[4] = h->cpu_tag[5] = h->cpu_tag[6] = h->cpu_tag[7] = 0;\n\tif (dest_port >= 32) {\n\t\tdest_port -= 32;\n\t\th->cpu_tag[4] = BIT(dest_port) >> 16;\n\t\th->cpu_tag[5] = BIT(dest_port) & 0xffff;\n\t} else {\n\t\th->cpu_tag[6] = BIT(dest_port) >> 16;\n\t\th->cpu_tag[7] = BIT(dest_port) & 0xffff;\n\t}\n}\n\nstatic void rtl93xx_header_vlan_set(struct p_hdr *h, int vlan)\n{\n\th->cpu_tag[2] |= BIT(4); // Enable VLAN forwarding offload\n\th->cpu_tag[2] |= (vlan >> 8) & 0xf;\n\th->cpu_tag[3] |= (vlan & 0xff) << 8;\n}\n\nstruct rtl838x_rx_q {\n\tint id;\n\tstruct rtl838x_eth_priv *priv;\n\tstruct napi_struct napi;\n};\n\nstruct rtl838x_eth_priv {\n\tstruct net_device *netdev;\n\tstruct platform_device *pdev;\n\tvoid\t\t*membase;\n\tspinlock_t\tlock;\n\tstruct mii_bus\t*mii_bus;\n\tstruct rtl838x_rx_q rx_qs[MAX_RXRINGS];\n\tstruct phylink *phylink;\n\tstruct phylink_config phylink_config;\n\tu16 id;\n\tu16 family_id;\n\tconst struct rtl838x_eth_reg *r;\n\tu8 cpu_port;\n\tu32 lastEvent;\n\tu16 rxrings;\n\tu16 rxringlen;\n\tu8 smi_bus[MAX_PORTS];\n\tu8 smi_addr[MAX_PORTS];\n\tu32 sds_id[MAX_PORTS];\n\tbool smi_bus_isc45[MAX_SMI_BUSSES];\n\tbool phy_is_internal[MAX_PORTS];\n\tphy_interface_t interfaces[MAX_PORTS];\n};\n\nextern int rtl838x_phy_init(struct rtl838x_eth_priv *priv);\nextern int rtl838x_read_sds_phy(int phy_addr, int phy_reg);\nextern int rtl839x_read_sds_phy(int phy_addr, int phy_reg);\nextern int rtl839x_write_sds_phy(int phy_addr, int phy_reg, u16 v);\nextern int rtl930x_read_sds_phy(int phy_addr, int page, int phy_reg);\nextern int rtl930x_write_sds_phy(int phy_addr, int page, int phy_reg, u16 v);\nextern int rtl931x_read_sds_phy(int phy_addr, int page, int phy_reg);\nextern int rtl931x_write_sds_phy(int phy_addr, int page, int phy_reg, u16 v);\nextern int rtl930x_read_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 *val);\nextern int rtl930x_write_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 val);\nextern int rtl931x_read_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 *val);\nextern int rtl931x_write_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 val);\n\n/*\n * On the RTL93XX, the RTL93XX_DMA_IF_RX_RING_CNTR track the fill level of \n * the rings. Writing x into these registers substracts x from its content.\n * When the content reaches the ring size, the ASIC no longer adds\n * packets to this receive queue.\n */\nvoid rtl838x_update_cntr(int r, int released)\n{\n\t// This feature is not available on RTL838x SoCs\n}\n\nvoid rtl839x_update_cntr(int r, int released)\n{\n\t// This feature is not available on RTL839x SoCs\n}\n\nvoid rtl930x_update_cntr(int r, int released)\n{\n\tint pos = (r % 3) * 10;\n\tu32 reg = RTL930X_DMA_IF_RX_RING_CNTR + ((r / 3) << 2);\n\tu32 v = sw_r32(reg);\n\n\tv = (v >> pos) & 0x3ff;\n\tpr_debug(\"RX: Work done %d, old value: %d, pos %d, reg %04x\\n\", released, v, pos, reg);\n\tsw_w32_mask(0x3ff << pos, released << pos, reg);\n\tsw_w32(v, reg);\n}\n\nvoid rtl931x_update_cntr(int r, int released)\n{\n\tint pos = (r % 3) * 10;\n\tu32 reg = RTL931X_DMA_IF_RX_RING_CNTR + ((r / 3) << 2);\n\tu32 v = sw_r32(reg);\n\n\tv = (v >> pos) & 0x3ff;\n\tsw_w32_mask(0x3ff << pos, released << pos, reg);\n\tsw_w32(v, reg);\n}\n\nstruct dsa_tag {\n\tu8\treason;\n\tu8\tqueue;\n\tu16\tport;\n\tu8\tl2_offloaded;\n\tu8\tprio;\n\tbool\tcrc_error;\n};\n\nbool rtl838x_decode_tag(struct p_hdr *h, struct dsa_tag *t)\n{\n\tt->reason = h->cpu_tag[3] & 0xf;\n\tt->queue = (h->cpu_tag[0] & 0xe0) >> 5;\n\tt->port = h->cpu_tag[1] & 0x1f;\n\tt->crc_error = t->reason == 13;\n\n\tpr_debug(\"Reason: %d\\n\", t->reason);\n\tif (t->reason != 4) // NIC_RX_REASON_SPECIAL_TRAP\n\t\tt->l2_offloaded = 1;\n\telse\n\t\tt->l2_offloaded = 0;\n\n\treturn t->l2_offloaded;\n}\n\nbool rtl839x_decode_tag(struct p_hdr *h, struct dsa_tag *t)\n{\n\tt->reason = h->cpu_tag[5] & 0x1f;\n\tt->queue = (h->cpu_tag[3] & 0xe000) >> 13;\n\tt->port = h->cpu_tag[1] & 0x3f;\n\tt->crc_error = h->cpu_tag[3] & BIT(2);\n\n\tpr_debug(\"Reason: %d\\n\", t->reason);\n\tif ((t->reason >= 7 && t->reason <= 13) || // NIC_RX_REASON_RMA\n\t    (t->reason >= 23 && t->reason <= 25))  // NIC_RX_REASON_SPECIAL_TRAP\n\t\tt->l2_offloaded = 0;\n\telse\n\t\tt->l2_offloaded = 1;\n\n\treturn t->l2_offloaded;\n}\n\nbool rtl930x_decode_tag(struct p_hdr *h, struct dsa_tag *t)\n{\n\tt->reason = h->cpu_tag[7] & 0x3f;\n\tt->queue =  (h->cpu_tag[2] >> 11) & 0x1f;\n\tt->port = (h->cpu_tag[0] >> 8) & 0x1f;\n\tt->crc_error = h->cpu_tag[1] & BIT(6);\n\n\tpr_debug(\"Reason %d, port %d, queue %d\\n\", t->reason, t->port, t->queue);\n\tif (t->reason >= 19 && t->reason <= 27)\n\t\tt->l2_offloaded = 0;\n\telse\n\t\tt->l2_offloaded = 1;\n\n\treturn t->l2_offloaded;\n}\n\nbool rtl931x_decode_tag(struct p_hdr *h, struct dsa_tag *t)\n{\n\tt->reason = h->cpu_tag[7] & 0x3f;\n\tt->queue =  (h->cpu_tag[2] >> 11) & 0x1f;\n\tt->port = (h->cpu_tag[0] >> 8) & 0x3f;\n\tt->crc_error = h->cpu_tag[1] & BIT(6);\n\n\tif (t->reason != 63)\n\t\tpr_info(\"%s: Reason %d, port %d, queue %d\\n\", __func__, t->reason, t->port, t->queue);\n\tif (t->reason >= 19 && t->reason <= 27)\t// NIC_RX_REASON_RMA\n\t\tt->l2_offloaded = 0;\n\telse\n\t\tt->l2_offloaded = 1;\n\n\treturn t->l2_offloaded;\n}\n\n/*\n * Discard the RX ring-buffers, called as part of the net-ISR\n * when the buffer runs over\n */\nstatic void rtl838x_rb_cleanup(struct rtl838x_eth_priv *priv, int status)\n{\n\tint r;\n\tu32\t*last;\n\tstruct p_hdr *h;\n\tstruct ring_b *ring = priv->membase;\n\n\tfor (r = 0; r < priv->rxrings; r++) {\n\t\tpr_debug(\"In %s working on r: %d\\n\", __func__, r);\n\t\tlast = (u32 *)KSEG1ADDR(sw_r32(priv->r->dma_if_rx_cur + r * 4));\n\t\tdo {\n\t\t\tif ((ring->rx_r[r][ring->c_rx[r]] & 0x1))\n\t\t\t\tbreak;\n\t\t\tpr_debug(\"Got something: %d\\n\", ring->c_rx[r]);\n\t\t\th = &ring->rx_header[r][ring->c_rx[r]];\n\t\t\tmemset(h, 0, sizeof(struct p_hdr));\n\t\t\th->buf = (u8 *)KSEG1ADDR(ring->rx_space\n\t\t\t\t\t+ r * priv->rxringlen * RING_BUFFER\n\t\t\t\t\t+ ring->c_rx[r] * RING_BUFFER);\n\t\t\th->size = RING_BUFFER;\n\t\t\t/* make sure the header is visible to the ASIC */\n\t\t\tmb();\n\n\t\t\tring->rx_r[r][ring->c_rx[r]] = KSEG1ADDR(h) | 0x1\n\t\t\t\t| (ring->c_rx[r] == (priv->rxringlen - 1) ? WRAP : 0x1);\n\t\t\tring->c_rx[r] = (ring->c_rx[r] + 1) % priv->rxringlen;\n\t\t} while (&ring->rx_r[r][ring->c_rx[r]] != last);\n\t}\n}\n\nstruct fdb_update_work {\n\tstruct work_struct work;\n\tstruct net_device *ndev;\n\tu64 macs[NOTIFY_EVENTS + 1];\n};\n\nvoid rtl838x_fdb_sync(struct work_struct *work)\n{\n\tconst struct fdb_update_work *uw =\n\t\tcontainer_of(work, struct fdb_update_work, work);\n\tstruct switchdev_notifier_fdb_info info;\n\tu8 addr[ETH_ALEN];\n\tint i = 0;\n\tint action;\n\n\twhile (uw->macs[i]) {\n\t\taction = (uw->macs[i] & (1ULL << 63)) ? SWITCHDEV_FDB_ADD_TO_BRIDGE\n\t\t\t\t: SWITCHDEV_FDB_DEL_TO_BRIDGE;\n\t\tu64_to_ether_addr(uw->macs[i] & 0xffffffffffffULL, addr);\n\t\tinfo.addr = &addr[0];\n\t\tinfo.vid = 0;\n\t\tinfo.offloaded = 1;\n\t\tpr_debug(\"FDB entry %d: %llx, action %d\\n\", i, uw->macs[0], action);\n\t\tcall_switchdev_notifiers(action, uw->ndev, &info.info, NULL);\n\t\ti++;\n\t}\n\tkfree(work);\n}\n\nstatic void rtl839x_l2_notification_handler(struct rtl838x_eth_priv *priv)\n{\n\tstruct notify_b *nb = priv->membase + sizeof(struct ring_b);\n\tu32 e = priv->lastEvent;\n\tstruct n_event *event;\n\tint i;\n\tu64 mac;\n\tstruct fdb_update_work *w;\n\n\twhile (!(nb->ring[e] & 1)) {\n\t\tw = kzalloc(sizeof(*w), GFP_ATOMIC);\n\t\tif (!w) {\n\t\t\tpr_err(\"Out of memory: %s\", __func__);\n\t\t\treturn;\n\t\t}\n\t\tINIT_WORK(&w->work, rtl838x_fdb_sync);\n\n\t\tfor (i = 0; i < NOTIFY_EVENTS; i++) {\n\t\t\tevent = &nb->blocks[e].events[i];\n\t\t\tif (!event->valid)\n\t\t\t\tcontinue;\n\t\t\tmac = event->mac;\n\t\t\tif (event->type)\n\t\t\t\tmac |= 1ULL << 63;\n\t\t\tw->ndev = priv->netdev;\n\t\t\tw->macs[i] = mac;\n\t\t}\n\n\t\t/* Hand the ring entry back to the switch */\n\t\tnb->ring[e] = nb->ring[e] | 1;\n\t\te = (e + 1) % NOTIFY_BLOCKS;\n\n\t\tw->macs[i] = 0ULL;\n\t\tschedule_work(&w->work);\n\t}\n\tpriv->lastEvent = e;\n}\n\nstatic irqreturn_t rtl83xx_net_irq(int irq, void *dev_id)\n{\n\tstruct net_device *dev = dev_id;\n\tstruct rtl838x_eth_priv *priv = netdev_priv(dev);\n\tu32 status = sw_r32(priv->r->dma_if_intr_sts);\n\tint i;\n\n\tpr_debug(\"IRQ: %08x\\n\", status);\n\n\t/*  Ignore TX interrupt */\n\tif ((status & 0xf0000)) {\n\t\t/* Clear ISR */\n\t\tsw_w32(0x000f0000, priv->r->dma_if_intr_sts);\n\t}\n\n\t/* RX interrupt */\n\tif (status & 0x0ff00) {\n\t\t/* ACK and disable RX interrupt for this ring */\n\t\tsw_w32_mask(0xff00 & status, 0, priv->r->dma_if_intr_msk);\n\t\tsw_w32(0x0000ff00 & status, priv->r->dma_if_intr_sts);\n\t\tfor (i = 0; i < priv->rxrings; i++) {\n\t\t\tif (status & BIT(i + 8)) {\n\t\t\t\tpr_debug(\"Scheduling queue: %d\\n\", i);\n\t\t\t\tnapi_schedule(&priv->rx_qs[i].napi);\n\t\t\t}\n\t\t}\n\t}\n\n\t/* RX buffer overrun */\n\tif (status & 0x000ff) {\n\t\tpr_debug(\"RX buffer overrun: status %x, mask: %x\\n\",\n\t\t\t status, sw_r32(priv->r->dma_if_intr_msk));\n\t\tsw_w32(status, priv->r->dma_if_intr_sts);\n\t\trtl838x_rb_cleanup(priv, status & 0xff);\n\t}\n\n\tif (priv->family_id == RTL8390_FAMILY_ID && status & 0x00100000) {\n\t\tsw_w32(0x00100000, priv->r->dma_if_intr_sts);\n\t\trtl839x_l2_notification_handler(priv);\n\t}\n\n\tif (priv->family_id == RTL8390_FAMILY_ID && status & 0x00200000) {\n\t\tsw_w32(0x00200000, priv->r->dma_if_intr_sts);\n\t\trtl839x_l2_notification_handler(priv);\n\t}\n\n\tif (priv->family_id == RTL8390_FAMILY_ID && status & 0x00400000) {\n\t\tsw_w32(0x00400000, priv->r->dma_if_intr_sts);\n\t\trtl839x_l2_notification_handler(priv);\n\t}\n\n\treturn IRQ_HANDLED;\n}\n\nstatic irqreturn_t rtl93xx_net_irq(int irq, void *dev_id)\n{\n\tstruct net_device *dev = dev_id;\n\tstruct rtl838x_eth_priv *priv = netdev_priv(dev);\n\tu32 status_rx_r = sw_r32(priv->r->dma_if_intr_rx_runout_sts);\n\tu32 status_rx = sw_r32(priv->r->dma_if_intr_rx_done_sts);\n\tu32 status_tx = sw_r32(priv->r->dma_if_intr_tx_done_sts);\n\tint i;\n\n\tpr_debug(\"In %s, status_tx: %08x, status_rx: %08x, status_rx_r: %08x\\n\",\n\t\t__func__, status_tx, status_rx, status_rx_r);\n\n\t/*  Ignore TX interrupt */\n\tif (status_tx) {\n\t\t/* Clear ISR */\n\t\tpr_debug(\"TX done\\n\");\n\t\tsw_w32(status_tx, priv->r->dma_if_intr_tx_done_sts);\n\t}\n\n\t/* RX interrupt */\n\tif (status_rx) {\n\t\tpr_debug(\"RX IRQ\\n\");\n\t\t/* ACK and disable RX interrupt for given rings */\n\t\tsw_w32(status_rx, priv->r->dma_if_intr_rx_done_sts);\n\t\tsw_w32_mask(status_rx, 0, priv->r->dma_if_intr_rx_done_msk);\n\t\tfor (i = 0; i < priv->rxrings; i++) {\n\t\t\tif (status_rx & BIT(i)) {\n\t\t\t\tpr_debug(\"Scheduling queue: %d\\n\", i);\n\t\t\t\tnapi_schedule(&priv->rx_qs[i].napi);\n\t\t\t}\n\t\t}\n\t}\n\n\t/* RX buffer overrun */\n\tif (status_rx_r) {\n\t\tpr_debug(\"RX buffer overrun: status %x, mask: %x\\n\",\n\t\t\t status_rx_r, sw_r32(priv->r->dma_if_intr_rx_runout_msk));\n\t\tsw_w32(status_rx_r, priv->r->dma_if_intr_rx_runout_sts);\n\t\trtl838x_rb_cleanup(priv, status_rx_r);\n\t}\n\n\treturn IRQ_HANDLED;\n}\n\nstatic const struct rtl838x_eth_reg rtl838x_reg = {\n\t.net_irq = rtl83xx_net_irq,\n\t.mac_port_ctrl = rtl838x_mac_port_ctrl,\n\t.dma_if_intr_sts = RTL838X_DMA_IF_INTR_STS,\n\t.dma_if_intr_msk = RTL838X_DMA_IF_INTR_MSK,\n\t.dma_if_ctrl = RTL838X_DMA_IF_CTRL,\n\t.mac_force_mode_ctrl = RTL838X_MAC_FORCE_MODE_CTRL,\n\t.dma_rx_base = RTL838X_DMA_RX_BASE,\n\t.dma_tx_base = RTL838X_DMA_TX_BASE,\n\t.dma_if_rx_ring_size = rtl838x_dma_if_rx_ring_size,\n\t.dma_if_rx_ring_cntr = rtl838x_dma_if_rx_ring_cntr,\n\t.dma_if_rx_cur = RTL838X_DMA_IF_RX_CUR,\n\t.rst_glb_ctrl = RTL838X_RST_GLB_CTRL_0,\n\t.get_mac_link_sts = rtl838x_get_mac_link_sts,\n\t.get_mac_link_dup_sts = rtl838x_get_mac_link_dup_sts,\n\t.get_mac_link_spd_sts = rtl838x_get_mac_link_spd_sts,\n\t.get_mac_rx_pause_sts = rtl838x_get_mac_rx_pause_sts,\n\t.get_mac_tx_pause_sts = rtl838x_get_mac_tx_pause_sts,\n\t.mac = RTL838X_MAC,\n\t.l2_tbl_flush_ctrl = RTL838X_L2_TBL_FLUSH_CTRL,\n\t.update_cntr = rtl838x_update_cntr,\n\t.create_tx_header = rtl838x_create_tx_header,\n\t.decode_tag = rtl838x_decode_tag,\n};\n\nstatic const struct rtl838x_eth_reg rtl839x_reg = {\n\t.net_irq = rtl83xx_net_irq,\n\t.mac_port_ctrl = rtl839x_mac_port_ctrl,\n\t.dma_if_intr_sts = RTL839X_DMA_IF_INTR_STS,\n\t.dma_if_intr_msk = RTL839X_DMA_IF_INTR_MSK,\n\t.dma_if_ctrl = RTL839X_DMA_IF_CTRL,\n\t.mac_force_mode_ctrl = RTL839X_MAC_FORCE_MODE_CTRL,\n\t.dma_rx_base = RTL839X_DMA_RX_BASE,\n\t.dma_tx_base = RTL839X_DMA_TX_BASE,\n\t.dma_if_rx_ring_size = rtl839x_dma_if_rx_ring_size,\n\t.dma_if_rx_ring_cntr = rtl839x_dma_if_rx_ring_cntr,\n\t.dma_if_rx_cur = RTL839X_DMA_IF_RX_CUR,\n\t.rst_glb_ctrl = RTL839X_RST_GLB_CTRL,\n\t.get_mac_link_sts = rtl839x_get_mac_link_sts,\n\t.get_mac_link_dup_sts = rtl839x_get_mac_link_dup_sts,\n\t.get_mac_link_spd_sts = rtl839x_get_mac_link_spd_sts,\n\t.get_mac_rx_pause_sts = rtl839x_get_mac_rx_pause_sts,\n\t.get_mac_tx_pause_sts = rtl839x_get_mac_tx_pause_sts,\n\t.mac = RTL839X_MAC,\n\t.l2_tbl_flush_ctrl = RTL839X_L2_TBL_FLUSH_CTRL,\n\t.update_cntr = rtl839x_update_cntr,\n\t.create_tx_header = rtl839x_create_tx_header,\n\t.decode_tag = rtl839x_decode_tag,\n};\n\nstatic const struct rtl838x_eth_reg rtl930x_reg = {\n\t.net_irq = rtl93xx_net_irq,\n\t.mac_port_ctrl = rtl930x_mac_port_ctrl,\n\t.dma_if_intr_rx_runout_sts = RTL930X_DMA_IF_INTR_RX_RUNOUT_STS,\n\t.dma_if_intr_rx_done_sts = RTL930X_DMA_IF_INTR_RX_DONE_STS,\n\t.dma_if_intr_tx_done_sts = RTL930X_DMA_IF_INTR_TX_DONE_STS,\n\t.dma_if_intr_rx_runout_msk = RTL930X_DMA_IF_INTR_RX_RUNOUT_MSK,\n\t.dma_if_intr_rx_done_msk = RTL930X_DMA_IF_INTR_RX_DONE_MSK,\n\t.dma_if_intr_tx_done_msk = RTL930X_DMA_IF_INTR_TX_DONE_MSK,\n\t.l2_ntfy_if_intr_sts = RTL930X_L2_NTFY_IF_INTR_STS,\n\t.l2_ntfy_if_intr_msk = RTL930X_L2_NTFY_IF_INTR_MSK,\n\t.dma_if_ctrl = RTL930X_DMA_IF_CTRL,\n\t.mac_force_mode_ctrl = RTL930X_MAC_FORCE_MODE_CTRL,\n\t.dma_rx_base = RTL930X_DMA_RX_BASE,\n\t.dma_tx_base = RTL930X_DMA_TX_BASE,\n\t.dma_if_rx_ring_size = rtl930x_dma_if_rx_ring_size,\n\t.dma_if_rx_ring_cntr = rtl930x_dma_if_rx_ring_cntr,\n\t.dma_if_rx_cur = RTL930X_DMA_IF_RX_CUR,\n\t.rst_glb_ctrl = RTL930X_RST_GLB_CTRL_0,\n\t.get_mac_link_sts = rtl930x_get_mac_link_sts,\n\t.get_mac_link_dup_sts = rtl930x_get_mac_link_dup_sts,\n\t.get_mac_link_spd_sts = rtl930x_get_mac_link_spd_sts,\n\t.get_mac_rx_pause_sts = rtl930x_get_mac_rx_pause_sts,\n\t.get_mac_tx_pause_sts = rtl930x_get_mac_tx_pause_sts,\n\t.mac = RTL930X_MAC_L2_ADDR_CTRL,\n\t.l2_tbl_flush_ctrl = RTL930X_L2_TBL_FLUSH_CTRL,\n\t.update_cntr = rtl930x_update_cntr,\n\t.create_tx_header = rtl930x_create_tx_header,\n\t.decode_tag = rtl930x_decode_tag,\n};\n\nstatic const struct rtl838x_eth_reg rtl931x_reg = {\n\t.net_irq = rtl93xx_net_irq,\n\t.mac_port_ctrl = rtl931x_mac_port_ctrl,\n\t.dma_if_intr_rx_runout_sts = RTL931X_DMA_IF_INTR_RX_RUNOUT_STS,\n\t.dma_if_intr_rx_done_sts = RTL931X_DMA_IF_INTR_RX_DONE_STS,\n\t.dma_if_intr_tx_done_sts = RTL931X_DMA_IF_INTR_TX_DONE_STS,\n\t.dma_if_intr_rx_runout_msk = RTL931X_DMA_IF_INTR_RX_RUNOUT_MSK,\n\t.dma_if_intr_rx_done_msk = RTL931X_DMA_IF_INTR_RX_DONE_MSK,\n\t.dma_if_intr_tx_done_msk = RTL931X_DMA_IF_INTR_TX_DONE_MSK,\n\t.l2_ntfy_if_intr_sts = RTL931X_L2_NTFY_IF_INTR_STS,\n\t.l2_ntfy_if_intr_msk = RTL931X_L2_NTFY_IF_INTR_MSK,\n\t.dma_if_ctrl = RTL931X_DMA_IF_CTRL,\n\t.mac_force_mode_ctrl = RTL931X_MAC_FORCE_MODE_CTRL,\n\t.dma_rx_base = RTL931X_DMA_RX_BASE,\n\t.dma_tx_base = RTL931X_DMA_TX_BASE,\n\t.dma_if_rx_ring_size = rtl931x_dma_if_rx_ring_size,\n\t.dma_if_rx_ring_cntr = rtl931x_dma_if_rx_ring_cntr,\n\t.dma_if_rx_cur = RTL931X_DMA_IF_RX_CUR,\n\t.rst_glb_ctrl = RTL931X_RST_GLB_CTRL,\n\t.get_mac_link_sts = rtl931x_get_mac_link_sts,\n\t.get_mac_link_dup_sts = rtl931x_get_mac_link_dup_sts,\n\t.get_mac_link_spd_sts = rtl931x_get_mac_link_spd_sts,\n\t.get_mac_rx_pause_sts = rtl931x_get_mac_rx_pause_sts,\n\t.get_mac_tx_pause_sts = rtl931x_get_mac_tx_pause_sts,\n\t.mac = RTL931X_MAC_L2_ADDR_CTRL,\n\t.l2_tbl_flush_ctrl = RTL931X_L2_TBL_FLUSH_CTRL,\n\t.update_cntr = rtl931x_update_cntr,\n\t.create_tx_header = rtl931x_create_tx_header,\n\t.decode_tag = rtl931x_decode_tag,\n};\n\nstatic void rtl838x_hw_reset(struct rtl838x_eth_priv *priv)\n{\n\tu32 int_saved, nbuf;\n\tu32 reset_mask;\n\tint i, pos;\n\t\n\tpr_info(\"RESETTING %x, CPU_PORT %d\\n\", priv->family_id, priv->cpu_port);\n\tsw_w32_mask(0x3, 0, priv->r->mac_port_ctrl(priv->cpu_port));\n\tmdelay(100);\n\n\t/* Disable and clear interrupts */\n\tif (priv->family_id == RTL9300_FAMILY_ID || priv->family_id == RTL9310_FAMILY_ID) {\n\t\tsw_w32(0x00000000, priv->r->dma_if_intr_rx_runout_msk);\n\t\tsw_w32(0xffffffff, priv->r->dma_if_intr_rx_runout_sts);\n\t\tsw_w32(0x00000000, priv->r->dma_if_intr_rx_done_msk);\n\t\tsw_w32(0xffffffff, priv->r->dma_if_intr_rx_done_sts);\n\t\tsw_w32(0x00000000, priv->r->dma_if_intr_tx_done_msk);\n\t\tsw_w32(0x0000000f, priv->r->dma_if_intr_tx_done_sts);\n\t} else {\n\t\tsw_w32(0x00000000, priv->r->dma_if_intr_msk);\n\t\tsw_w32(0xffffffff, priv->r->dma_if_intr_sts);\n\t}\n\n\tif (priv->family_id == RTL8390_FAMILY_ID) {\n\t\t/* Preserve L2 notification and NBUF settings */\n\t\tint_saved = sw_r32(priv->r->dma_if_intr_msk);\n\t\tnbuf = sw_r32(RTL839X_DMA_IF_NBUF_BASE_DESC_ADDR_CTRL);\n\n\t\t/* Disable link change interrupt on RTL839x */\n\t\tsw_w32(0, RTL839X_IMR_PORT_LINK_STS_CHG);\n\t\tsw_w32(0, RTL839X_IMR_PORT_LINK_STS_CHG + 4);\n\n\t\tsw_w32(0x00000000, priv->r->dma_if_intr_msk);\n\t\tsw_w32(0xffffffff, priv->r->dma_if_intr_sts);\n\t}\n\n\t/* Reset NIC (SW_NIC_RST) and queues (SW_Q_RST) */\n\tif (priv->family_id == RTL9300_FAMILY_ID || priv->family_id == RTL9310_FAMILY_ID)\n\t\treset_mask = 0x6;\n\telse\n\t\treset_mask = 0xc;\n\n\tsw_w32(reset_mask, priv->r->rst_glb_ctrl);\n\n\tdo { /* Wait for reset of NIC and Queues done */\n\t\tudelay(20);\n\t} while (sw_r32(priv->r->rst_glb_ctrl) & reset_mask);\n\tmdelay(100);\n\n\t/* Setup Head of Line */\n\tif (priv->family_id == RTL8380_FAMILY_ID)\n\t\tsw_w32(0, RTL838X_DMA_IF_RX_RING_SIZE);  // Disabled on RTL8380\n\tif (priv->family_id == RTL8390_FAMILY_ID)\n\t\tsw_w32(0xffffffff, RTL839X_DMA_IF_RX_RING_CNTR);\n\tif (priv->family_id == RTL9300_FAMILY_ID || priv->family_id == RTL9310_FAMILY_ID) {\n\t\tfor (i = 0; i < priv->rxrings; i++) {\n\t\t\tpos = (i % 3) * 10;\n\t\t\tsw_w32_mask(0x3ff << pos, 0, priv->r->dma_if_rx_ring_size(i));\n\t\t\tsw_w32_mask(0x3ff << pos, priv->rxringlen,\n\t\t\t\t    priv->r->dma_if_rx_ring_cntr(i));\n\t\t}\n\t}\n\n\t/* Re-enable link change interrupt */\n\tif (priv->family_id == RTL8390_FAMILY_ID) {\n\t\tsw_w32(0xffffffff, RTL839X_ISR_PORT_LINK_STS_CHG);\n\t\tsw_w32(0xffffffff, RTL839X_ISR_PORT_LINK_STS_CHG + 4);\n\t\tsw_w32(0xffffffff, RTL839X_IMR_PORT_LINK_STS_CHG);\n\t\tsw_w32(0xffffffff, RTL839X_IMR_PORT_LINK_STS_CHG + 4);\n\n\t\t/* Restore notification settings: on RTL838x these bits are null */\n\t\tsw_w32_mask(7 << 20, int_saved & (7 << 20), priv->r->dma_if_intr_msk);\n\t\tsw_w32(nbuf, RTL839X_DMA_IF_NBUF_BASE_DESC_ADDR_CTRL);\n\t}\n}\n\nstatic void rtl838x_hw_ring_setup(struct rtl838x_eth_priv *priv)\n{\n\tint i;\n\tstruct ring_b *ring = priv->membase;\n\n\tfor (i = 0; i < priv->rxrings; i++)\n\t\tsw_w32(KSEG1ADDR(&ring->rx_r[i]), priv->r->dma_rx_base + i * 4);\n\n\tfor (i = 0; i < TXRINGS; i++)\n\t\tsw_w32(KSEG1ADDR(&ring->tx_r[i]), priv->r->dma_tx_base + i * 4);\n}\n\nstatic void rtl838x_hw_en_rxtx(struct rtl838x_eth_priv *priv)\n{\n\t/* Disable Head of Line features for all RX rings */\n\tsw_w32(0xffffffff, priv->r->dma_if_rx_ring_size(0));\n\n\t/* Truncate RX buffer to 0x640 (1600) bytes, pad TX */\n\tsw_w32(0x06400020, priv->r->dma_if_ctrl);\n\n\t/* Enable RX done, RX overflow and TX done interrupts */\n\tsw_w32(0xfffff, priv->r->dma_if_intr_msk);\n\n\t/* Enable DMA, engine expects empty FCS field */\n\tsw_w32_mask(0, RX_EN | TX_EN, priv->r->dma_if_ctrl);\n\n\t/* Restart TX/RX to CPU port */\n\tsw_w32_mask(0x0, 0x3, priv->r->mac_port_ctrl(priv->cpu_port));\n\t/* Set Speed, duplex, flow control\n\t * FORCE_EN | LINK_EN | NWAY_EN | DUP_SEL\n\t * | SPD_SEL = 0b10 | FORCE_FC_EN | PHY_MASTER_SLV_MANUAL_EN\n\t * | MEDIA_SEL\n\t */\n\tsw_w32(0x6192F, priv->r->mac_force_mode_ctrl + priv->cpu_port * 4);\n\n\t/* Enable CRC checks on CPU-port */\n\tsw_w32_mask(0, BIT(3), priv->r->mac_port_ctrl(priv->cpu_port));\n}\n\nstatic void rtl839x_hw_en_rxtx(struct rtl838x_eth_priv *priv)\n{\n\t/* Setup CPU-Port: RX Buffer */\n\tsw_w32(0x0000c808, priv->r->dma_if_ctrl);\n\n\t/* Enable Notify, RX done, RX overflow and TX done interrupts */\n\tsw_w32(0x007fffff, priv->r->dma_if_intr_msk); // Notify IRQ!\n\n\t/* Enable DMA */\n\tsw_w32_mask(0, RX_EN | TX_EN, priv->r->dma_if_ctrl);\n\n\t/* Restart TX/RX to CPU port, enable CRC checking */\n\tsw_w32_mask(0x0, 0x3 | BIT(3), priv->r->mac_port_ctrl(priv->cpu_port));\n\n\t/* CPU port joins Lookup Miss Flooding Portmask */\n\t// TODO: The code below should also work for the RTL838x\n\tsw_w32(0x28000, RTL839X_TBL_ACCESS_L2_CTRL);\n\tsw_w32_mask(0, 0x80000000, RTL839X_TBL_ACCESS_L2_DATA(0));\n\tsw_w32(0x38000, RTL839X_TBL_ACCESS_L2_CTRL);\n\n\t/* Force CPU port link up */\n\tsw_w32_mask(0, 3, priv->r->mac_force_mode_ctrl + priv->cpu_port * 4);\n}\n\nstatic void rtl93xx_hw_en_rxtx(struct rtl838x_eth_priv *priv)\n{\n\tint i, pos;\n\tu32 v;\n\n\t/* Setup CPU-Port: RX Buffer truncated at 1600 Bytes */\n\tsw_w32(0x06400040, priv->r->dma_if_ctrl);\n\n\tfor (i = 0; i < priv->rxrings; i++) {\n\t\tpos = (i % 3) * 10;\n\t\tsw_w32_mask(0x3ff << pos, priv->rxringlen << pos, priv->r->dma_if_rx_ring_size(i));\n\n\t\t// Some SoCs have issues with missing underflow protection\n\t\tv = (sw_r32(priv->r->dma_if_rx_ring_cntr(i)) >> pos) & 0x3ff;\n\t\tsw_w32_mask(0x3ff << pos, v, priv->r->dma_if_rx_ring_cntr(i));\n\t}\n\n\t/* Enable Notify, RX done, RX overflow and TX done interrupts */\n\tsw_w32(0xffffffff, priv->r->dma_if_intr_rx_runout_msk);\n\tsw_w32(0xffffffff, priv->r->dma_if_intr_rx_done_msk);\n\tsw_w32(0x0000000f, priv->r->dma_if_intr_tx_done_msk);\n\n\t/* Enable DMA */\n\tsw_w32_mask(0, RX_EN_93XX | TX_EN_93XX, priv->r->dma_if_ctrl);\n\n\t/* Restart TX/RX to CPU port, enable CRC checking */\n\tsw_w32_mask(0x0, 0x3 | BIT(4), priv->r->mac_port_ctrl(priv->cpu_port));\n\n\tif (priv->family_id == RTL9300_FAMILY_ID)\n\t\tsw_w32_mask(0, BIT(priv->cpu_port), RTL930X_L2_UNKN_UC_FLD_PMSK);\n\telse\n\t\tsw_w32_mask(0, BIT(priv->cpu_port), RTL931X_L2_UNKN_UC_FLD_PMSK);\n\n\tif (priv->family_id == RTL9300_FAMILY_ID)\n\t\tsw_w32(0x217, priv->r->mac_force_mode_ctrl + priv->cpu_port * 4);\n\telse\n\t\tsw_w32(0x2a1d, priv->r->mac_force_mode_ctrl + priv->cpu_port * 4);\n}\n\nstatic void rtl838x_setup_ring_buffer(struct rtl838x_eth_priv *priv, struct ring_b *ring)\n{\n\tint i, j;\n\n\tstruct p_hdr *h;\n\n\tfor (i = 0; i < priv->rxrings; i++) {\n\t\tfor (j = 0; j < priv->rxringlen; j++) {\n\t\t\th = &ring->rx_header[i][j];\n\t\t\tmemset(h, 0, sizeof(struct p_hdr));\n\t\t\th->buf = (u8 *)KSEG1ADDR(ring->rx_space\n\t\t\t\t\t+ i * priv->rxringlen * RING_BUFFER\n\t\t\t\t\t+ j * RING_BUFFER);\n\t\t\th->size = RING_BUFFER;\n\t\t\t/* All rings owned by switch, last one wraps */\n\t\t\tring->rx_r[i][j] = KSEG1ADDR(h) | 1 \n\t\t\t\t\t   | (j == (priv->rxringlen - 1) ? WRAP : 0);\n\t\t}\n\t\tring->c_rx[i] = 0;\n\t}\n\n\tfor (i = 0; i < TXRINGS; i++) {\n\t\tfor (j = 0; j < TXRINGLEN; j++) {\n\t\t\th = &ring->tx_header[i][j];\n\t\t\tmemset(h, 0, sizeof(struct p_hdr));\n\t\t\th->buf = (u8 *)KSEG1ADDR(ring->tx_space\n\t\t\t\t\t+ i * TXRINGLEN * RING_BUFFER\n\t\t\t\t\t+ j * RING_BUFFER);\n\t\t\th->size = RING_BUFFER;\n\t\t\tring->tx_r[i][j] = KSEG1ADDR(&ring->tx_header[i][j]);\n\t\t}\n\t\t/* Last header is wrapping around */\n\t\tring->tx_r[i][j-1] |= WRAP;\n\t\tring->c_tx[i] = 0;\n\t}\n}\n\nstatic void rtl839x_setup_notify_ring_buffer(struct rtl838x_eth_priv *priv)\n{\n\tint i;\n\tstruct notify_b *b = priv->membase + sizeof(struct ring_b);\n\n\tfor (i = 0; i < NOTIFY_BLOCKS; i++)\n\t\tb->ring[i] = KSEG1ADDR(&b->blocks[i]) | 1 | (i == (NOTIFY_BLOCKS - 1) ? WRAP : 0);\n\n\tsw_w32((u32) b->ring, RTL839X_DMA_IF_NBUF_BASE_DESC_ADDR_CTRL);\n\tsw_w32_mask(0x3ff << 2, 100 << 2, RTL839X_L2_NOTIFICATION_CTRL);\n\n\t/* Setup notification events */\n\tsw_w32_mask(0, 1 << 14, RTL839X_L2_CTRL_0); // RTL8390_L2_CTRL_0_FLUSH_NOTIFY_EN\n\tsw_w32_mask(0, 1 << 12, RTL839X_L2_NOTIFICATION_CTRL); // SUSPEND_NOTIFICATION_EN\n\n\t/* Enable Notification */\n\tsw_w32_mask(0, 1 << 0, RTL839X_L2_NOTIFICATION_CTRL);\n\tpriv->lastEvent = 0;\n}\n\nstatic int rtl838x_eth_open(struct net_device *ndev)\n{\n\tunsigned long flags;\n\tstruct rtl838x_eth_priv *priv = netdev_priv(ndev);\n\tstruct ring_b *ring = priv->membase;\n\tint i;\n\n\tpr_debug(\"%s called: RX rings %d(length %d), TX rings %d(length %d)\\n\",\n\t\t__func__, priv->rxrings, priv->rxringlen, TXRINGS, TXRINGLEN);\n\n\tspin_lock_irqsave(&priv->lock, flags);\n\trtl838x_hw_reset(priv);\n\trtl838x_setup_ring_buffer(priv, ring);\n\tif (priv->family_id == RTL8390_FAMILY_ID) {\n\t\trtl839x_setup_notify_ring_buffer(priv);\n\t\t/* Make sure the ring structure is visible to the ASIC */\n\t\tmb();\n\t\tflush_cache_all();\n\t}\n\n\trtl838x_hw_ring_setup(priv);\n\tphylink_start(priv->phylink);\n\n\tfor (i = 0; i < priv->rxrings; i++)\n\t\tnapi_enable(&priv->rx_qs[i].napi);\n\n\tswitch (priv->family_id) {\n\tcase RTL8380_FAMILY_ID:\n\t\trtl838x_hw_en_rxtx(priv);\n\t\t/* Trap IGMP/MLD traffic to CPU-Port */\n\t\tsw_w32(0x3, RTL838X_SPCL_TRAP_IGMP_CTRL);\n\t\t/* Flush learned FDB entries on link down of a port */\n\t\tsw_w32_mask(0, BIT(7), RTL838X_L2_CTRL_0);\n\t\tbreak;\n\n\tcase RTL8390_FAMILY_ID:\n\t\trtl839x_hw_en_rxtx(priv);\n\t\t// Trap MLD and IGMP messages to CPU_PORT\n\t\tsw_w32(0x3, RTL839X_SPCL_TRAP_IGMP_CTRL);\n\t\t/* Flush learned FDB entries on link down of a port */\n\t\tsw_w32_mask(0, BIT(7), RTL839X_L2_CTRL_0);\n\t\tbreak;\n\n\tcase RTL9300_FAMILY_ID:\n\t\trtl93xx_hw_en_rxtx(priv);\n\t\t/* Flush learned FDB entries on link down of a port */\n\t\tsw_w32_mask(0, BIT(7), RTL930X_L2_CTRL);\n\t\t// Trap MLD and IGMP messages to CPU_PORT\n\t\tsw_w32((0x2 << 3) | 0x2,  RTL930X_VLAN_APP_PKT_CTRL);\n\t\tbreak;\n\n\tcase RTL9310_FAMILY_ID:\n\t\trtl93xx_hw_en_rxtx(priv);\n\n\t\t// Trap MLD and IGMP messages to CPU_PORT\n\t\tsw_w32((0x2 << 3) | 0x2,  RTL931X_VLAN_APP_PKT_CTRL);\n\n\t\t// Disable External CPU access to switch, clear EXT_CPU_EN\n\t\tsw_w32_mask(BIT(2), 0, RTL931X_MAC_L2_GLOBAL_CTRL2);\n\n\t\t// Set PCIE_PWR_DOWN\n\t\tsw_w32_mask(0, BIT(1), RTL931X_PS_SOC_CTRL);\n\t\tbreak;\n\t}\n\n\tnetif_tx_start_all_queues(ndev);\n\n\tspin_unlock_irqrestore(&priv->lock, flags);\n\n\treturn 0;\n}\n\nstatic void rtl838x_hw_stop(struct rtl838x_eth_priv *priv)\n{\n\tu32 force_mac = priv->family_id == RTL8380_FAMILY_ID ? 0x6192C : 0x75;\n\tu32 clear_irq = priv->family_id == RTL8380_FAMILY_ID ? 0x000fffff : 0x007fffff;\n\tint i;\n\n\t// Disable RX/TX from/to CPU-port\n\tsw_w32_mask(0x3, 0, priv->r->mac_port_ctrl(priv->cpu_port));\n\n\t/* Disable traffic */\n\tif (priv->family_id == RTL9300_FAMILY_ID || priv->family_id == RTL9310_FAMILY_ID)\n\t\tsw_w32_mask(RX_EN_93XX | TX_EN_93XX, 0, priv->r->dma_if_ctrl);\n\telse\n\t\tsw_w32_mask(RX_EN | TX_EN, 0, priv->r->dma_if_ctrl);\n\tmdelay(200); // Test, whether this is needed\n\n\t/* Block all ports */\n\tif (priv->family_id == RTL8380_FAMILY_ID) {\n\t\tsw_w32(0x03000000, RTL838X_TBL_ACCESS_DATA_0(0));\n\t\tsw_w32(0x00000000, RTL838X_TBL_ACCESS_DATA_0(1));\n\t\tsw_w32(1 << 15 | 2 << 12, RTL838X_TBL_ACCESS_CTRL_0);\n\t}\n\n\t/* Flush L2 address cache */\n\tif (priv->family_id == RTL8380_FAMILY_ID) {\n\t\tfor (i = 0; i <= priv->cpu_port; i++) {\n\t\t\tsw_w32(1 << 26 | 1 << 23 | i << 5, priv->r->l2_tbl_flush_ctrl);\n\t\t\tdo { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & (1 << 26));\n\t\t}\n\t} else if (priv->family_id == RTL8390_FAMILY_ID) {\n\t\tfor (i = 0; i <= priv->cpu_port; i++) {\n\t\t\tsw_w32(1 << 28 | 1 << 25 | i << 5, priv->r->l2_tbl_flush_ctrl);\n\t\t\tdo { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & (1 << 28));\n\t\t}\n\t}\n\t// TODO: L2 flush register is 64 bit on RTL931X and 930X\n\n\t/* CPU-Port: Link down */\n\tif (priv->family_id == RTL8380_FAMILY_ID || priv->family_id == RTL8390_FAMILY_ID)\n\t\tsw_w32(force_mac, priv->r->mac_force_mode_ctrl + priv->cpu_port * 4);\n\telse if (priv->family_id == RTL9300_FAMILY_ID)\n\t\tsw_w32_mask(0x3, 0, priv->r->mac_force_mode_ctrl + priv->cpu_port *4);\n\telse if (priv->family_id == RTL9310_FAMILY_ID)\n\t\tsw_w32_mask(BIT(0) | BIT(9), 0, priv->r->mac_force_mode_ctrl + priv->cpu_port *4);\n\tmdelay(100);\n\n\t/* Disable all TX/RX interrupts */\n\tif (priv->family_id == RTL9300_FAMILY_ID || priv->family_id == RTL9310_FAMILY_ID) {\n\t\tsw_w32(0x00000000, priv->r->dma_if_intr_rx_runout_msk);\n\t\tsw_w32(0xffffffff, priv->r->dma_if_intr_rx_runout_sts);\n\t\tsw_w32(0x00000000, priv->r->dma_if_intr_rx_done_msk);\n\t\tsw_w32(0xffffffff, priv->r->dma_if_intr_rx_done_sts);\n\t\tsw_w32(0x00000000, priv->r->dma_if_intr_tx_done_msk);\n\t\tsw_w32(0x0000000f, priv->r->dma_if_intr_tx_done_sts);\n\t} else {\n\t\tsw_w32(0x00000000, priv->r->dma_if_intr_msk);\n\t\tsw_w32(clear_irq, priv->r->dma_if_intr_sts);\n\t}\n\n\t/* Disable TX/RX DMA */\n\tsw_w32(0x00000000, priv->r->dma_if_ctrl);\n\tmdelay(200);\n}\n\nstatic int rtl838x_eth_stop(struct net_device *ndev)\n{\n\tunsigned long flags;\n\tint i;\n\tstruct rtl838x_eth_priv *priv = netdev_priv(ndev);\n\n\tpr_info(\"in %s\\n\", __func__);\n\n\tphylink_stop(priv->phylink);\n\trtl838x_hw_stop(priv);\n\n\tfor (i = 0; i < priv->rxrings; i++)\n\t\tnapi_disable(&priv->rx_qs[i].napi);\n\n\tnetif_tx_stop_all_queues(ndev);\n\n\treturn 0;\n}\n\nstatic void rtl839x_eth_set_multicast_list(struct net_device *ndev)\n{\n\tif (!(ndev->flags & (IFF_PROMISC | IFF_ALLMULTI))) {\n\t\tsw_w32(0x0, RTL839X_RMA_CTRL_0);\n\t\tsw_w32(0x0, RTL839X_RMA_CTRL_1);\n\t\tsw_w32(0x0, RTL839X_RMA_CTRL_2);\n\t\tsw_w32(0x0, RTL839X_RMA_CTRL_3);\n\t}\n\tif (ndev->flags & IFF_ALLMULTI) {\n\t\tsw_w32(0x7fffffff, RTL839X_RMA_CTRL_0);\n\t\tsw_w32(0x7fffffff, RTL839X_RMA_CTRL_1);\n\t\tsw_w32(0x7fffffff, RTL839X_RMA_CTRL_2);\n\t}\n\tif (ndev->flags & IFF_PROMISC) {\n\t\tsw_w32(0x7fffffff, RTL839X_RMA_CTRL_0);\n\t\tsw_w32(0x7fffffff, RTL839X_RMA_CTRL_1);\n\t\tsw_w32(0x7fffffff, RTL839X_RMA_CTRL_2);\n\t\tsw_w32(0x3ff, RTL839X_RMA_CTRL_3);\n\t}\n}\n\nstatic void rtl838x_eth_set_multicast_list(struct net_device *ndev)\n{\n\tstruct rtl838x_eth_priv *priv = netdev_priv(ndev);\n\n\tif (priv->family_id == RTL8390_FAMILY_ID)\n\t\treturn rtl839x_eth_set_multicast_list(ndev);\n\n\tif (!(ndev->flags & (IFF_PROMISC | IFF_ALLMULTI))) {\n\t\tsw_w32(0x0, RTL838X_RMA_CTRL_0);\n\t\tsw_w32(0x0, RTL838X_RMA_CTRL_1);\n\t}\n\tif (ndev->flags & IFF_ALLMULTI)\n\t\tsw_w32(0x1fffff, RTL838X_RMA_CTRL_0);\n\tif (ndev->flags & IFF_PROMISC) {\n\t\tsw_w32(0x1fffff, RTL838X_RMA_CTRL_0);\n\t\tsw_w32(0x7fff, RTL838X_RMA_CTRL_1);\n\t}\n}\n\nstatic void rtl930x_eth_set_multicast_list(struct net_device *ndev)\n{\n\tif (!(ndev->flags & (IFF_PROMISC | IFF_ALLMULTI))) {\n\t\tsw_w32(0x0, RTL930X_RMA_CTRL_0);\n\t\tsw_w32(0x0, RTL930X_RMA_CTRL_1);\n\t\tsw_w32(0x0, RTL930X_RMA_CTRL_2);\n\t}\n\tif (ndev->flags & IFF_ALLMULTI) {\n\t\tsw_w32(0x7fffffff, RTL930X_RMA_CTRL_0);\n\t\tsw_w32(0x7fffffff, RTL930X_RMA_CTRL_1);\n\t\tsw_w32(0x7fffffff, RTL930X_RMA_CTRL_2);\n\t}\n\tif (ndev->flags & IFF_PROMISC) {\n\t\tsw_w32(0x7fffffff, RTL930X_RMA_CTRL_0);\n\t\tsw_w32(0x7fffffff, RTL930X_RMA_CTRL_1);\n\t\tsw_w32(0x7fffffff, RTL930X_RMA_CTRL_2);\n\t}\n}\n\nstatic void rtl931x_eth_set_multicast_list(struct net_device *ndev)\n{\n\tif (!(ndev->flags & (IFF_PROMISC | IFF_ALLMULTI))) {\n\t\tsw_w32(0x0, RTL931X_RMA_CTRL_0);\n\t\tsw_w32(0x0, RTL931X_RMA_CTRL_1);\n\t\tsw_w32(0x0, RTL931X_RMA_CTRL_2);\n\t}\n\tif (ndev->flags & IFF_ALLMULTI) {\n\t\tsw_w32(0x7fffffff, RTL931X_RMA_CTRL_0);\n\t\tsw_w32(0x7fffffff, RTL931X_RMA_CTRL_1);\n\t\tsw_w32(0x7fffffff, RTL931X_RMA_CTRL_2);\n\t}\n\tif (ndev->flags & IFF_PROMISC) {\n\t\tsw_w32(0x7fffffff, RTL931X_RMA_CTRL_0);\n\t\tsw_w32(0x7fffffff, RTL931X_RMA_CTRL_1);\n\t\tsw_w32(0x7fffffff, RTL931X_RMA_CTRL_2);\n\t}\n}\n\nstatic void rtl838x_eth_tx_timeout(struct net_device *ndev, unsigned int txqueue)\n{\n\tunsigned long flags;\n\tstruct rtl838x_eth_priv *priv = netdev_priv(ndev);\n\n\tpr_warn(\"%s\\n\", __func__);\n\tspin_lock_irqsave(&priv->lock, flags);\n\trtl838x_hw_stop(priv);\n\trtl838x_hw_ring_setup(priv);\n\trtl838x_hw_en_rxtx(priv);\n\tnetif_trans_update(ndev);\n\tnetif_start_queue(ndev);\n\tspin_unlock_irqrestore(&priv->lock, flags);\n}\n\nstatic int rtl838x_eth_tx(struct sk_buff *skb, struct net_device *dev)\n{\n\tint len, i;\n\tstruct rtl838x_eth_priv *priv = netdev_priv(dev);\n\tstruct ring_b *ring = priv->membase;\n\tuint32_t val;\n\tint ret;\n\tunsigned long flags;\n\tstruct p_hdr *h;\n\tint dest_port = -1;\n\tint q = skb_get_queue_mapping(skb) % TXRINGS;\n\n\tif (q) // Check for high prio queue\n\t\tpr_debug(\"SKB priority: %d\\n\", skb->priority);\n\n\tspin_lock_irqsave(&priv->lock, flags);\n\tlen = skb->len;\n\n\t/* Check for DSA tagging at the end of the buffer */\n\tif (netdev_uses_dsa(dev) && skb->data[len-4] == 0x80 && skb->data[len-3] > 0\n\t\t\t&& skb->data[len-3] < priv->cpu_port &&  skb->data[len-2] == 0x10\n\t\t\t&&  skb->data[len-1] == 0x00) {\n\t\t/* Reuse tag space for CRC if possible */\n\t\tdest_port = skb->data[len-3];\n\t\tskb->data[len-4] = skb->data[len-3] = skb->data[len-2] = skb->data[len-1] = 0x00;\n\t\tlen -= 4;\n\t}\n\n\tlen += 4; // Add space for CRC\n\n\tif (skb_padto(skb, len)) {\n\t\tret = NETDEV_TX_OK;\n\t\tgoto txdone;\n\t}\n\n\t/* We can send this packet if CPU owns the descriptor */\n\tif (!(ring->tx_r[q][ring->c_tx[q]] & 0x1)) {\n\n\t\t/* Set descriptor for tx */\n\t\th = &ring->tx_header[q][ring->c_tx[q]];\n\t\th->size = len;\n\t\th->len = len;\n\t\t// On RTL8380 SoCs, small packet lengths being sent need adjustments\n\t\tif (priv->family_id == RTL8380_FAMILY_ID) {\n\t\t\tif (len < ETH_ZLEN - 4)\n\t\t\t\th->len -= 4;\n\t\t}\n\n\t\tpriv->r->create_tx_header(h, dest_port, skb->priority >> 1);\n\n\t\t/* Copy packet data to tx buffer */\n\t\tmemcpy((void *)KSEG1ADDR(h->buf), skb->data, len);\n\t\t/* Make sure packet data is visible to ASIC */\n\t\twmb();\n\n\t\t/* Hand over to switch */\n\t\tring->tx_r[q][ring->c_tx[q]] |= 1;\n\n\t\t// Before starting TX, prevent a Lextra bus bug on RTL8380 SoCs\n\t\tif (priv->family_id == RTL8380_FAMILY_ID) {\n\t\t\tfor (i = 0; i < 10; i++) {\n\t\t\t\tval = sw_r32(priv->r->dma_if_ctrl);\n\t\t\t\tif ((val & 0xc) == 0xc)\n\t\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\n\t\t/* Tell switch to send data */\n\t\tif (priv->family_id == RTL9310_FAMILY_ID\n\t\t\t|| priv->family_id == RTL9300_FAMILY_ID) {\n\t\t\t// Ring ID q == 0: Low priority, Ring ID = 1: High prio queue\n\t\t\tif (!q)\n\t\t\t\tsw_w32_mask(0, BIT(2), priv->r->dma_if_ctrl);\n\t\t\telse\n\t\t\t\tsw_w32_mask(0, BIT(3), priv->r->dma_if_ctrl);\n\t\t} else {\n\t\t\tsw_w32_mask(0, TX_DO, priv->r->dma_if_ctrl);\n\t\t}\n\n\t\tdev->stats.tx_packets++;\n\t\tdev->stats.tx_bytes += len;\n\t\tdev_kfree_skb(skb);\n\t\tring->c_tx[q] = (ring->c_tx[q] + 1) % TXRINGLEN;\n\t\tret = NETDEV_TX_OK;\n\t} else {\n\t\tdev_warn(&priv->pdev->dev, \"Data is owned by switch\\n\");\n\t\tret = NETDEV_TX_BUSY;\n\t}\ntxdone:\n\tspin_unlock_irqrestore(&priv->lock, flags);\n\treturn ret;\n}\n\n/*\n * Return queue number for TX. On the RTL83XX, these queues have equal priority\n * so we do round-robin\n */\nu16 rtl83xx_pick_tx_queue(struct net_device *dev, struct sk_buff *skb,\n\t\t\t  struct net_device *sb_dev)\n{\n\tstatic u8 last = 0;\n\n\tlast++;\n\treturn last % TXRINGS;\n}\n\n/*\n * Return queue number for TX. On the RTL93XX, queue 1 is the high priority queue\n */\nu16 rtl93xx_pick_tx_queue(struct net_device *dev, struct sk_buff *skb,\n\t\t\t  struct net_device *sb_dev)\n{\n\tif (skb->priority >= TC_PRIO_CONTROL)\n\t\treturn 1;\n\treturn 0;\n}\n\nstatic int rtl838x_hw_receive(struct net_device *dev, int r, int budget)\n{\n\tstruct rtl838x_eth_priv *priv = netdev_priv(dev);\n\tstruct ring_b *ring = priv->membase;\n\tstruct sk_buff *skb;\n\tunsigned long flags;\n\tint i, len, work_done = 0;\n\tu8 *data, *skb_data;\n\tunsigned int val;\n\tu32\t*last;\n\tstruct p_hdr *h;\n\tbool dsa = netdev_uses_dsa(dev);\n\tstruct dsa_tag tag;\n\n\tpr_debug(\"---------------------------------------------------------- RX - %d\\n\", r);\n\tspin_lock_irqsave(&priv->lock, flags);\n\tlast = (u32 *)KSEG1ADDR(sw_r32(priv->r->dma_if_rx_cur + r * 4));\n\n\tdo {\n\t\tif ((ring->rx_r[r][ring->c_rx[r]] & 0x1)) {\n\t\t\tif (&ring->rx_r[r][ring->c_rx[r]] != last) {\n\t\t\t\tnetdev_warn(dev, \"Ring contention: r: %x, last %x, cur %x\\n\",\n\t\t\t\t    r, (uint32_t)last, (u32) &ring->rx_r[r][ring->c_rx[r]]);\n\t\t\t}\n\t\t\tbreak;\n\t\t}\n\n\t\th = &ring->rx_header[r][ring->c_rx[r]];\n\t\tdata = (u8 *)KSEG1ADDR(h->buf);\n\t\tlen = h->len;\n\t\tif (!len)\n\t\t\tbreak;\n\t\twork_done++;\n\n\t\tlen -= 4; /* strip the CRC */\n\t\t/* Add 4 bytes for cpu_tag */\n\t\tif (dsa)\n\t\t\tlen += 4;\n\n\t\tskb = netdev_alloc_skb(dev, len + 4);\n\t\tskb_reserve(skb, NET_IP_ALIGN);\n\n\t\tif (likely(skb)) {\n\t\t\t/* BUG: Prevent bug on RTL838x SoCs*/\n\t\t\tif (priv->family_id == RTL8380_FAMILY_ID) {\n\t\t\t\tsw_w32(0xffffffff, priv->r->dma_if_rx_ring_size(0));\n\t\t\t\tfor (i = 0; i < priv->rxrings; i++) {\n\t\t\t\t\t/* Update each ring cnt */\n\t\t\t\t\tval = sw_r32(priv->r->dma_if_rx_ring_cntr(i));\n\t\t\t\t\tsw_w32(val, priv->r->dma_if_rx_ring_cntr(i));\n\t\t\t\t}\n\t\t\t}\n\n\t\t\tskb_data = skb_put(skb, len);\n\t\t\t/* Make sure data is visible */\n\t\t\tmb();\n\t\t\tmemcpy(skb->data, (u8 *)KSEG1ADDR(data), len);\n\t\t\t/* Overwrite CRC with cpu_tag */\n\t\t\tif (dsa) {\n\t\t\t\tpriv->r->decode_tag(h, &tag);\n\t\t\t\tskb->data[len-4] = 0x80;\n\t\t\t\tskb->data[len-3] = tag.port;\n\t\t\t\tskb->data[len-2] = 0x10;\n\t\t\t\tskb->data[len-1] = 0x00;\n\t\t\t\tif (tag.l2_offloaded)\n\t\t\t\t\tskb->data[len-3] |= 0x40;\n\t\t\t}\n\n\t\t\tif (tag.queue >= 0)\n\t\t\t\tpr_debug(\"Queue: %d, len: %d, reason %d port %d\\n\",\n\t\t\t\t\t tag.queue, len, tag.reason, tag.port);\n\n\t\t\tskb->protocol = eth_type_trans(skb, dev);\n\t\t\tif (dev->features & NETIF_F_RXCSUM) {\n\t\t\t\tif (tag.crc_error)\n\t\t\t\t\tskb_checksum_none_assert(skb);\n\t\t\t\telse\n\t\t\t\t\tskb->ip_summed = CHECKSUM_UNNECESSARY;\n\t\t\t}\n\t\t\tdev->stats.rx_packets++;\n\t\t\tdev->stats.rx_bytes += len;\n\n\t\t\tnetif_receive_skb(skb);\n\t\t} else {\n\t\t\tif (net_ratelimit())\n\t\t\t\tdev_warn(&dev->dev, \"low on memory - packet dropped\\n\");\n\t\t\tdev->stats.rx_dropped++;\n\t\t}\n\n\t\t/* Reset header structure */\n\t\tmemset(h, 0, sizeof(struct p_hdr));\n\t\th->buf = data;\n\t\th->size = RING_BUFFER;\n\n\t\tring->rx_r[r][ring->c_rx[r]] = KSEG1ADDR(h) | 0x1 \n\t\t\t| (ring->c_rx[r] == (priv->rxringlen - 1) ? WRAP : 0x1);\n\t\tring->c_rx[r] = (ring->c_rx[r] + 1) % priv->rxringlen;\n\t\tlast = (u32 *)KSEG1ADDR(sw_r32(priv->r->dma_if_rx_cur + r * 4));\n\t} while (&ring->rx_r[r][ring->c_rx[r]] != last && work_done < budget);\n\n\t// Update counters\n\tpriv->r->update_cntr(r, 0);\n\n\tspin_unlock_irqrestore(&priv->lock, flags);\n\n\treturn work_done;\n}\n\nstatic int rtl838x_poll_rx(struct napi_struct *napi, int budget)\n{\n\tstruct rtl838x_rx_q *rx_q = container_of(napi, struct rtl838x_rx_q, napi);\n\tstruct rtl838x_eth_priv *priv = rx_q->priv;\n\tint work_done = 0;\n\tint r = rx_q->id;\n\tint work;\n\n\twhile (work_done < budget) {\n\t\twork = rtl838x_hw_receive(priv->netdev, r, budget - work_done);\n\t\tif (!work)\n\t\t\tbreak;\n\t\twork_done += work;\n\t}\n\n\tif (work_done < budget) {\n\t\tnapi_complete_done(napi, work_done);\n\n\t\t/* Enable RX interrupt */\n\t\tif (priv->family_id == RTL9300_FAMILY_ID || priv->family_id == RTL9310_FAMILY_ID)\n\t\t\tsw_w32(0xffffffff, priv->r->dma_if_intr_rx_done_msk);\n\t\telse\n\t\t\tsw_w32_mask(0, 0xf00ff | BIT(r + 8), priv->r->dma_if_intr_msk);\n\t}\n\treturn work_done;\n}\n\n\nstatic void rtl838x_validate(struct phylink_config *config,\n\t\t\t unsigned long *supported,\n\t\t\t struct phylink_link_state *state)\n{\n\t__ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };\n\n\tpr_debug(\"In %s\\n\", __func__);\n\n\tif (!phy_interface_mode_is_rgmii(state->interface) &&\n\t    state->interface != PHY_INTERFACE_MODE_1000BASEX &&\n\t    state->interface != PHY_INTERFACE_MODE_MII &&\n\t    state->interface != PHY_INTERFACE_MODE_REVMII &&\n\t    state->interface != PHY_INTERFACE_MODE_GMII &&\n\t    state->interface != PHY_INTERFACE_MODE_QSGMII &&\n\t    state->interface != PHY_INTERFACE_MODE_INTERNAL &&\n\t    state->interface != PHY_INTERFACE_MODE_SGMII) {\n\t\tbitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);\n\t\tpr_err(\"Unsupported interface: %d\\n\", state->interface);\n\t\treturn;\n\t}\n\n\t/* Allow all the expected bits */\n\tphylink_set(mask, Autoneg);\n\tphylink_set_port_modes(mask);\n\tphylink_set(mask, Pause);\n\tphylink_set(mask, Asym_Pause);\n\n\t/* With the exclusion of MII and Reverse MII, we support Gigabit,\n\t * including Half duplex\n\t */\n\tif (state->interface != PHY_INTERFACE_MODE_MII &&\n\t    state->interface != PHY_INTERFACE_MODE_REVMII) {\n\t\tphylink_set(mask, 1000baseT_Full);\n\t\tphylink_set(mask, 1000baseT_Half);\n\t}\n\n\tphylink_set(mask, 10baseT_Half);\n\tphylink_set(mask, 10baseT_Full);\n\tphylink_set(mask, 100baseT_Half);\n\tphylink_set(mask, 100baseT_Full);\n\n\tbitmap_and(supported, supported, mask,\n\t\t   __ETHTOOL_LINK_MODE_MASK_NBITS);\n\tbitmap_and(state->advertising, state->advertising, mask,\n\t\t   __ETHTOOL_LINK_MODE_MASK_NBITS);\n}\n\n\nstatic void rtl838x_mac_config(struct phylink_config *config,\n\t\t\t       unsigned int mode,\n\t\t\t       const struct phylink_link_state *state)\n{\n\t/* This is only being called for the master device,\n\t * i.e. the CPU-Port. We don't need to do anything.\n\t */\n\n\tpr_info(\"In %s, mode %x\\n\", __func__, mode);\n}\n\nstatic void rtl838x_mac_an_restart(struct phylink_config *config)\n{\n\tstruct net_device *dev = container_of(config->dev, struct net_device, dev);\n\tstruct rtl838x_eth_priv *priv = netdev_priv(dev);\n\n\t/* This works only on RTL838x chips */\n\tif (priv->family_id != RTL8380_FAMILY_ID)\n\t\treturn;\n\n\tpr_debug(\"In %s\\n\", __func__);\n\t/* Restart by disabling and re-enabling link */\n\tsw_w32(0x6192D, priv->r->mac_force_mode_ctrl + priv->cpu_port * 4);\n\tmdelay(20);\n\tsw_w32(0x6192F, priv->r->mac_force_mode_ctrl + priv->cpu_port * 4);\n}\n\nstatic void rtl838x_mac_pcs_get_state(struct phylink_config *config,\n\t\t\t\t  struct phylink_link_state *state)\n{\n\tu32 speed;\n\tstruct net_device *dev = container_of(config->dev, struct net_device, dev);\n\tstruct rtl838x_eth_priv *priv = netdev_priv(dev);\n\tint port = priv->cpu_port;\n\n\tpr_info(\"In %s\\n\", __func__);\n\n\tstate->link = priv->r->get_mac_link_sts(port) ? 1 : 0;\n\tstate->duplex = priv->r->get_mac_link_dup_sts(port) ? 1 : 0;\n\n\tpr_info(\"%s link status is %d\\n\", __func__, state->link);\n\tspeed = priv->r->get_mac_link_spd_sts(port);\n\tswitch (speed) {\n\tcase 0:\n\t\tstate->speed = SPEED_10;\n\t\tbreak;\n\tcase 1:\n\t\tstate->speed = SPEED_100;\n\t\tbreak;\n\tcase 2:\n\t\tstate->speed = SPEED_1000;\n\t\tbreak;\n\tcase 5:\n\t\tstate->speed = SPEED_2500;\n\t\tbreak;\n\tcase 6:\n\t\tstate->speed = SPEED_5000;\n\t\tbreak;\n\tcase 4:\n\t\tstate->speed = SPEED_10000;\n\t\tbreak;\n\tdefault:\n\t\tstate->speed = SPEED_UNKNOWN;\n\t\tbreak;\n\t}\n\n\tstate->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX);\n\tif (priv->r->get_mac_rx_pause_sts(port))\n\t\tstate->pause |= MLO_PAUSE_RX;\n\tif (priv->r->get_mac_tx_pause_sts(port))\n\t\tstate->pause |= MLO_PAUSE_TX;\n}\n\nstatic void rtl838x_mac_link_down(struct phylink_config *config,\n\t\t\t\t  unsigned int mode,\n\t\t\t\t  phy_interface_t interface)\n{\n\tstruct net_device *dev = container_of(config->dev, struct net_device, dev);\n\tstruct rtl838x_eth_priv *priv = netdev_priv(dev);\n\n\tpr_debug(\"In %s\\n\", __func__);\n\t/* Stop TX/RX to port */\n\tsw_w32_mask(0x03, 0, priv->r->mac_port_ctrl(priv->cpu_port));\n}\n\nstatic void rtl838x_mac_link_up(struct phylink_config *config,\n\t\t\t    struct phy_device *phy, unsigned int mode,\n\t\t\t    phy_interface_t interface, int speed, int duplex,\n\t\t\t    bool tx_pause, bool rx_pause)\n{\n\tstruct net_device *dev = container_of(config->dev, struct net_device, dev);\n\tstruct rtl838x_eth_priv *priv = netdev_priv(dev);\n\n\tpr_debug(\"In %s\\n\", __func__);\n\t/* Restart TX/RX to port */\n\tsw_w32_mask(0, 0x03, priv->r->mac_port_ctrl(priv->cpu_port));\n}\n\nstatic void rtl838x_set_mac_hw(struct net_device *dev, u8 *mac)\n{\n\tstruct rtl838x_eth_priv *priv = netdev_priv(dev);\n\tunsigned long flags;\n\n\tspin_lock_irqsave(&priv->lock, flags);\n\tpr_debug(\"In %s\\n\", __func__);\n\tsw_w32((mac[0] << 8) | mac[1], priv->r->mac);\n\tsw_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5], priv->r->mac + 4);\n\n\tif (priv->family_id == RTL8380_FAMILY_ID) {\n\t\t/* 2 more registers, ALE/MAC block */\n\t\tsw_w32((mac[0] << 8) | mac[1], RTL838X_MAC_ALE);\n\t\tsw_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],\n\t\t       (RTL838X_MAC_ALE + 4));\n\n\t\tsw_w32((mac[0] << 8) | mac[1], RTL838X_MAC2);\n\t\tsw_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],\n\t\t       RTL838X_MAC2 + 4);\n\t}\n\tspin_unlock_irqrestore(&priv->lock, flags);\n}\n\nstatic int rtl838x_set_mac_address(struct net_device *dev, void *p)\n{\n\tstruct rtl838x_eth_priv *priv = netdev_priv(dev);\n\tconst struct sockaddr *addr = p;\n\tu8 *mac = (u8 *) (addr->sa_data);\n\n\tif (!is_valid_ether_addr(addr->sa_data))\n\t\treturn -EADDRNOTAVAIL;\n\n\tmemcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);\n\trtl838x_set_mac_hw(dev, mac);\n\n\tpr_info(\"Using MAC %08x%08x\\n\", sw_r32(priv->r->mac), sw_r32(priv->r->mac + 4));\n\treturn 0;\n}\n\nstatic int rtl8390_init_mac(struct rtl838x_eth_priv *priv)\n{\n\t// We will need to set-up EEE and the egress-rate limitation\n\treturn 0;\n}\n\nstatic int rtl8380_init_mac(struct rtl838x_eth_priv *priv)\n{\n\tint i;\n\n\tif (priv->family_id == 0x8390)\n\t\treturn rtl8390_init_mac(priv);\n\n    // At present we do not know how to set up EEE on any other SoC than RTL8380\n\tif (priv->family_id != 0x8380)\n\t\treturn 0;\n\n\tpr_info(\"%s\\n\", __func__);\n\t/* fix timer for EEE */\n\tsw_w32(0x5001411, RTL838X_EEE_TX_TIMER_GIGA_CTRL);\n\tsw_w32(0x5001417, RTL838X_EEE_TX_TIMER_GELITE_CTRL);\n\n\t/* Init VLAN. TODO: Understand what is being done, here */\n\tif (priv->id == 0x8382) {\n\t\tfor (i = 0; i <= 28; i++)\n\t\t\tsw_w32(0, 0xd57c + i * 0x80);\n\t}\n\tif (priv->id == 0x8380) {\n\t\tfor (i = 8; i <= 28; i++)\n\t\t\tsw_w32(0, 0xd57c + i * 0x80);\n\t}\n\treturn 0;\n}\n\nstatic int rtl838x_get_link_ksettings(struct net_device *ndev,\n\t\t\t\t      struct ethtool_link_ksettings *cmd)\n{\n\tstruct rtl838x_eth_priv *priv = netdev_priv(ndev);\n\n\tpr_debug(\"%s called\\n\", __func__);\n\treturn phylink_ethtool_ksettings_get(priv->phylink, cmd);\n}\n\nstatic int rtl838x_set_link_ksettings(struct net_device *ndev,\n\t\t\t\t      const struct ethtool_link_ksettings *cmd)\n{\n\tstruct rtl838x_eth_priv *priv = netdev_priv(ndev);\n\n\tpr_debug(\"%s called\\n\", __func__);\n\treturn phylink_ethtool_ksettings_set(priv->phylink, cmd);\n}\n\nstatic int rtl838x_mdio_read_paged(struct mii_bus *bus, int mii_id, u16 page, int regnum)\n{\n\tu32 val;\n\tint err;\n\tstruct rtl838x_eth_priv *priv = bus->priv;\n\n\tif (mii_id >= 24 && mii_id <= 27 && priv->id == 0x8380)\n\t\treturn rtl838x_read_sds_phy(mii_id, regnum);\n\n\tif (regnum & (MII_ADDR_C45 | MII_ADDR_C22_MMD)) {\n\t\terr = rtl838x_read_mmd_phy(mii_id,\n\t\t\t\t\t   mdiobus_c45_devad(regnum),\n\t\t\t\t\t   regnum, &val);\n\t\tpr_debug(\"MMD: %d dev %x register %x read %x, err %d\\n\", mii_id,\n\t\t\t mdiobus_c45_devad(regnum), mdiobus_c45_regad(regnum),\n\t\t\t val, err);\n\t} else {\n\t\tpr_debug(\"PHY: %d register %x read %x, err %d\\n\", mii_id, regnum, val, err);\n\t\terr = rtl838x_read_phy(mii_id, page, regnum, &val);\n\t}\n\tif (err)\n\t\treturn err;\n\treturn val;\n}\n\nstatic int rtl838x_mdio_read(struct mii_bus *bus, int mii_id, int regnum)\n{\n\treturn rtl838x_mdio_read_paged(bus, mii_id, 0, regnum);\n}\n\nstatic int rtl839x_mdio_read_paged(struct mii_bus *bus, int mii_id, u16 page, int regnum)\n{\n\tu32 val;\n\tint err;\n\tstruct rtl838x_eth_priv *priv = bus->priv;\n\n\tif (mii_id >= 48 && mii_id <= 49 && priv->id == 0x8393)\n\t\treturn rtl839x_read_sds_phy(mii_id, regnum);\n\n\tif (regnum & (MII_ADDR_C45 | MII_ADDR_C22_MMD)) {\n\t\terr = rtl839x_read_mmd_phy(mii_id,\n\t\t\t\t\t   mdiobus_c45_devad(regnum),\n\t\t\t\t\t   regnum, &val);\n\t\tpr_debug(\"MMD: %d dev %x register %x read %x, err %d\\n\", mii_id,\n\t\t\t mdiobus_c45_devad(regnum), mdiobus_c45_regad(regnum),\n\t\t\t val, err);\n\t} else {\n\t\terr = rtl839x_read_phy(mii_id, page, regnum, &val);\n\t\tpr_debug(\"PHY: %d register %x read %x, err %d\\n\", mii_id, regnum, val, err);\n\t}\n\t\tif (err)\n\t\treturn err;\n\treturn val;\n}\n\nstatic int rtl839x_mdio_read(struct mii_bus *bus, int mii_id, int regnum)\n{\n\treturn rtl839x_mdio_read_paged(bus, mii_id, 0, regnum);\n}\n\nstatic int rtl930x_mdio_read_paged(struct mii_bus *bus, int mii_id, u16 page, int regnum)\n{\n\tu32 val;\n\tint err;\n\tstruct rtl838x_eth_priv *priv = bus->priv;\n\n\tif (priv->phy_is_internal[mii_id])\n\t\treturn rtl930x_read_sds_phy(priv->sds_id[mii_id], page, regnum);\n\n\tif (regnum & (MII_ADDR_C45 | MII_ADDR_C22_MMD)) {\n\t\terr = rtl930x_read_mmd_phy(mii_id,\n\t\t\t\t\t   mdiobus_c45_devad(regnum),\n\t\t\t\t\t   regnum, &val);\n\t\tpr_debug(\"MMD: %d dev %x register %x read %x, err %d\\n\", mii_id,\n\t\t\t mdiobus_c45_devad(regnum), mdiobus_c45_regad(regnum),\n\t\t\t val, err);\n\t} else {\n\t\terr = rtl930x_read_phy(mii_id, page, regnum, &val);\n\t\tpr_debug(\"PHY: %d register %x read %x, err %d\\n\", mii_id, regnum, val, err);\n\t}\n\tif (err)\n\t\treturn err;\n\treturn val;\n}\n\nstatic int rtl930x_mdio_read(struct mii_bus *bus, int mii_id, int regnum)\n{\n\treturn rtl930x_mdio_read_paged(bus, mii_id, 0, regnum);\n}\n\nstatic int rtl931x_mdio_read_paged(struct mii_bus *bus, int mii_id, u16 page, int regnum)\n{\n\tu32 val;\n\tint err, v;\n\tstruct rtl838x_eth_priv *priv = bus->priv;\n\n\tpr_debug(\"%s: In here, port %d\\n\", __func__, mii_id);\n\tif (priv->phy_is_internal[mii_id]) {\n\t\tv = rtl931x_read_sds_phy(priv->sds_id[mii_id], page, regnum);\n\t\tif (v < 0) {\n\t\t\terr = v;\n\t\t} else {\n\t\t\terr = 0;\n\t\t\tval = v;\n\t\t}\n\t} else {\n\t\tif (regnum & (MII_ADDR_C45 | MII_ADDR_C22_MMD)) {\n\t\t\terr = rtl931x_read_mmd_phy(mii_id,\n\t\t\t\t\t\t   mdiobus_c45_devad(regnum),\n\t\t\t\t\t\t   regnum, &val);\n\t\t\tpr_debug(\"MMD: %d dev %x register %x read %x, err %d\\n\", mii_id,\n\t\t\t\t mdiobus_c45_devad(regnum), mdiobus_c45_regad(regnum),\n\t\t\t\t val, err);\n\t\t} else {\n\t\t\terr = rtl931x_read_phy(mii_id, page, regnum, &val);\n\t\t\tpr_debug(\"PHY: %d register %x read %x, err %d\\n\", mii_id, regnum, val, err);\n\t\t}\n\t}\n\n\tif (err)\n\t\treturn err;\n\treturn val;\n}\n\nstatic int rtl931x_mdio_read(struct mii_bus *bus, int mii_id, int regnum)\n{\n\treturn rtl931x_mdio_read_paged(bus, mii_id, 0, regnum);\n}\n\nstatic int rtl838x_mdio_write_paged(struct mii_bus *bus, int mii_id, u16 page,\n\t\t\t\t    int regnum, u16 value)\n{\n\tu32 offset = 0;\n\tstruct rtl838x_eth_priv *priv = bus->priv;\n\tint err;\n\n\tif (mii_id >= 24 && mii_id <= 27 && priv->id == 0x8380) {\n\t\tif (mii_id == 26)\n\t\t\toffset = 0x100;\n\t\tsw_w32(value, RTL838X_SDS4_FIB_REG0 + offset + (regnum << 2));\n\t\treturn 0;\n\t}\n\n\tif (regnum & (MII_ADDR_C45 | MII_ADDR_C22_MMD)) {\n\t\terr = rtl838x_write_mmd_phy(mii_id, mdiobus_c45_devad(regnum),\n\t\t\t\t\t    regnum, value);\n\t\tpr_debug(\"MMD: %d dev %x register %x write %x, err %d\\n\", mii_id,\n\t\t\t mdiobus_c45_devad(regnum), mdiobus_c45_regad(regnum),\n\t\t\t value, err);\n\n\t\treturn err;\n\t}\n\terr = rtl838x_write_phy(mii_id, page, regnum, value);\n\tpr_debug(\"PHY: %d register %x write %x, err %d\\n\", mii_id, regnum, value, err);\n\treturn err;\n}\n\nstatic int rtl838x_mdio_write(struct mii_bus *bus, int mii_id,\n\t\t\t      int regnum, u16 value)\n{\n\treturn rtl838x_mdio_write_paged(bus, mii_id, 0, regnum, value);\n}\n\nstatic int rtl839x_mdio_write_paged(struct mii_bus *bus, int mii_id, u16 page,\n\t\t\t\t    int regnum, u16 value)\n{\n\tstruct rtl838x_eth_priv *priv = bus->priv;\n\tint err;\n\n\tif (mii_id >= 48 && mii_id <= 49 && priv->id == 0x8393)\n\t\treturn rtl839x_write_sds_phy(mii_id, regnum, value);\n\n\tif (regnum & (MII_ADDR_C45 | MII_ADDR_C22_MMD)) {\n\t\terr = rtl839x_write_mmd_phy(mii_id, mdiobus_c45_devad(regnum),\n\t\t\t\t\t    regnum, value);\n\t\tpr_debug(\"MMD: %d dev %x register %x write %x, err %d\\n\", mii_id,\n\t\t\t mdiobus_c45_devad(regnum), mdiobus_c45_regad(regnum),\n\t\t\t value, err);\n\n\t\treturn err;\n\t}\n\n\terr = rtl839x_write_phy(mii_id, page, regnum, value);\n\tpr_debug(\"PHY: %d register %x write %x, err %d\\n\", mii_id, regnum, value, err);\n\treturn err;\n}\n\nstatic int rtl839x_mdio_write(struct mii_bus *bus, int mii_id,\n\t\t\t      int regnum, u16 value)\n{\n\treturn rtl839x_mdio_write_paged(bus, mii_id, 0, regnum, value);\n}\n\nstatic int rtl930x_mdio_write_paged(struct mii_bus *bus, int mii_id, u16 page,\n\t\t\t\t    int regnum, u16 value)\n{\n\tstruct rtl838x_eth_priv *priv = bus->priv;\n\tint err;\n\n\tif (priv->phy_is_internal[mii_id])\n\t\treturn rtl930x_write_sds_phy(priv->sds_id[mii_id], page, regnum, value);\n\n\tif (regnum & (MII_ADDR_C45 | MII_ADDR_C22_MMD))\n\t\treturn rtl930x_write_mmd_phy(mii_id, mdiobus_c45_devad(regnum),\n\t\t\t\t\t     regnum, value);\n\n\terr = rtl930x_write_phy(mii_id, page, regnum, value);\n\tpr_debug(\"PHY: %d register %x write %x, err %d\\n\", mii_id, regnum, value, err);\n\treturn err;\n}\n\nstatic int rtl930x_mdio_write(struct mii_bus *bus, int mii_id,\n\t\t\t      int regnum, u16 value)\n{\n\treturn rtl930x_mdio_write_paged(bus, mii_id, 0, regnum, value);\n}\n\nstatic int rtl931x_mdio_write_paged(struct mii_bus *bus, int mii_id, u16 page,\n\t\t\t\t    int regnum, u16 value)\n{\n\tstruct rtl838x_eth_priv *priv = bus->priv;\n\tint err;\n\n\tif (priv->phy_is_internal[mii_id])\n\t\treturn rtl931x_write_sds_phy(priv->sds_id[mii_id], page, regnum, value);\n\n\tif (regnum & (MII_ADDR_C45 | MII_ADDR_C22_MMD)) {\n\t\terr = rtl931x_write_mmd_phy(mii_id, mdiobus_c45_devad(regnum),\n\t\t\t\t\t    regnum, value);\n\t\tpr_debug(\"MMD: %d dev %x register %x write %x, err %d\\n\", mii_id,\n\t\t\t mdiobus_c45_devad(regnum), mdiobus_c45_regad(regnum),\n\t\t\t value, err);\n\n\t\treturn err;\n\t}\n\n\terr = rtl931x_write_phy(mii_id, page, regnum, value);\n\tpr_debug(\"PHY: %d register %x write %x, err %d\\n\", mii_id, regnum, value, err);\n\treturn err;\n}\n\nstatic int rtl931x_mdio_write(struct mii_bus *bus, int mii_id,\n\t\t\t      int regnum, u16 value)\n{\n\treturn rtl931x_mdio_write_paged(bus, mii_id, 0, regnum, value);\n}\n\nstatic int rtl838x_mdio_reset(struct mii_bus *bus)\n{\n\tpr_debug(\"%s called\\n\", __func__);\n\t/* Disable MAC polling the PHY so that we can start configuration */\n\tsw_w32(0x00000000, RTL838X_SMI_POLL_CTRL);\n\n\t/* Enable PHY control via SoC */\n\tsw_w32_mask(0, 1 << 15, RTL838X_SMI_GLB_CTRL);\n\n\t// Probably should reset all PHYs here...\n\treturn 0;\n}\n\nstatic int rtl839x_mdio_reset(struct mii_bus *bus)\n{\n\treturn 0;\n\n\tpr_debug(\"%s called\\n\", __func__);\n\t/* BUG: The following does not work, but should! */\n\t/* Disable MAC polling the PHY so that we can start configuration */\n\tsw_w32(0x00000000, RTL839X_SMI_PORT_POLLING_CTRL);\n\tsw_w32(0x00000000, RTL839X_SMI_PORT_POLLING_CTRL + 4);\n\t/* Disable PHY polling via SoC */\n\tsw_w32_mask(1 << 7, 0, RTL839X_SMI_GLB_CTRL);\n\n\t// Probably should reset all PHYs here...\n\treturn 0;\n}\n\nu8 mac_type_bit[RTL930X_CPU_PORT] = {0, 0, 0, 0, 2, 2, 2, 2, 4, 4, 4, 4, 6, 6, 6, 6,\n\t\t\t\t     8, 8, 8, 8, 10, 10, 10, 10, 12, 15, 18, 21};\n\nstatic int rtl930x_mdio_reset(struct mii_bus *bus)\n{\n\tint i;\n\tint pos;\n\tstruct rtl838x_eth_priv *priv = bus->priv;\n\tu32 c45_mask = 0;\n\tu32 poll_sel[2];\n\tu32 poll_ctrl = 0;\n\tu32 private_poll_mask = 0;\n\tu32 v;\n\tbool uses_usxgmii = false; // For the Aquantia PHYs\n\tbool uses_hisgmii = false; // For the RTL8221/8226\n\n\t// Mapping of port to phy-addresses on an SMI bus\n\tpoll_sel[0] = poll_sel[1] = 0;\n\tfor (i = 0; i < RTL930X_CPU_PORT; i++) {\n\t\tif (priv->smi_bus[i] > 3)\n\t\t\tcontinue;\n\t\tpos = (i % 6) * 5;\n\t\tsw_w32_mask(0x1f << pos, priv->smi_addr[i] << pos,\n\t\t\t    RTL930X_SMI_PORT0_5_ADDR + (i / 6) * 4);\n\n\t\tpos = (i * 2) % 32;\n\t\tpoll_sel[i / 16] |= priv->smi_bus[i] << pos;\n\t\tpoll_ctrl |= BIT(20 + priv->smi_bus[i]);\n\t}\n\n\t// Configure which SMI bus is behind which port number\n\tsw_w32(poll_sel[0], RTL930X_SMI_PORT0_15_POLLING_SEL);\n\tsw_w32(poll_sel[1], RTL930X_SMI_PORT16_27_POLLING_SEL);\n\n\t// Disable POLL_SEL for any SMI bus with a normal PHY (not RTL8295R for SFP+)\n\tsw_w32_mask(poll_ctrl, 0, RTL930X_SMI_GLB_CTRL);\n\n\t// Configure which SMI busses are polled in c45 based on a c45 PHY being on that bus\n\tfor (i = 0; i < 4; i++)\n\t\tif (priv->smi_bus_isc45[i])\n\t\t\tc45_mask |= BIT(i + 16);\n\n\tpr_info(\"c45_mask: %08x\\n\", c45_mask);\n\tsw_w32_mask(0, c45_mask, RTL930X_SMI_GLB_CTRL);\n\n\t// Set the MAC type of each port according to the PHY-interface\n\t// Values are FE: 2, GE: 3, XGE/2.5G: 0(SERDES) or 1(otherwise), SXGE: 0\n\tv = 0;\n\tfor (i = 0; i < RTL930X_CPU_PORT; i++) {\n\t\tswitch (priv->interfaces[i]) {\n\t\tcase PHY_INTERFACE_MODE_10GBASER:\n\t\t\tbreak;\t\t\t// Serdes: Value = 0\n\n\t\tcase PHY_INTERFACE_MODE_HSGMII:\n\t\t\tprivate_poll_mask |= BIT(i);\n\t\t\t// fallthrough\n\t\tcase PHY_INTERFACE_MODE_USXGMII:\n\t\t\tv |= BIT(mac_type_bit[i]);\n\t\t\tuses_usxgmii = true;\n\t\t\tbreak;\n\n\t\tcase PHY_INTERFACE_MODE_QSGMII:\n\t\t\tprivate_poll_mask |= BIT(i);\n\t\t\tv |= 3 << mac_type_bit[i];\n\t\t\tbreak;\n\n\t\tdefault:\n\t\t\tbreak;\n\t\t}\n\t}\n\tsw_w32(v, RTL930X_SMI_MAC_TYPE_CTRL);\n\n\t// Set the private polling mask for all Realtek PHYs (i.e. not the 10GBit Aquantia ones)\n\tsw_w32(private_poll_mask, RTL930X_SMI_PRVTE_POLLING_CTRL);\n\n\t/* The following magic values are found in the port configuration, they seem to\n\t * define different ways of polling a PHY. The below is for the Aquantia PHYs of\n\t * the XGS1250 and the RTL8226 of the XGS1210 */\n\tif (uses_usxgmii) {\n\t\tsw_w32(0x01010000, RTL930X_SMI_10GPHY_POLLING_REG0_CFG);\n\t\tsw_w32(0x01E7C400, RTL930X_SMI_10GPHY_POLLING_REG9_CFG);\n\t\tsw_w32(0x01E7E820, RTL930X_SMI_10GPHY_POLLING_REG10_CFG);\n\t}\n\tif (uses_hisgmii) {\n\t\tsw_w32(0x011FA400, RTL930X_SMI_10GPHY_POLLING_REG0_CFG);\n\t\tsw_w32(0x013FA412, RTL930X_SMI_10GPHY_POLLING_REG9_CFG);\n\t\tsw_w32(0x017FA414, RTL930X_SMI_10GPHY_POLLING_REG10_CFG);\n\t}\n\n\tpr_debug(\"%s: RTL930X_SMI_GLB_CTRL %08x\\n\", __func__,\n\t\t sw_r32(RTL930X_SMI_GLB_CTRL));\n\tpr_debug(\"%s: RTL930X_SMI_PORT0_15_POLLING_SEL %08x\\n\", __func__,\n\t\t sw_r32(RTL930X_SMI_PORT0_15_POLLING_SEL));\n\tpr_debug(\"%s: RTL930X_SMI_PORT16_27_POLLING_SEL %08x\\n\", __func__,\n\t\t sw_r32(RTL930X_SMI_PORT16_27_POLLING_SEL));\n\tpr_debug(\"%s: RTL930X_SMI_MAC_TYPE_CTRL %08x\\n\", __func__,\n\t\t sw_r32(RTL930X_SMI_MAC_TYPE_CTRL));\n\tpr_debug(\"%s: RTL930X_SMI_10GPHY_POLLING_REG0_CFG %08x\\n\", __func__,\n\t\t sw_r32(RTL930X_SMI_10GPHY_POLLING_REG0_CFG));\n\tpr_debug(\"%s: RTL930X_SMI_10GPHY_POLLING_REG9_CFG %08x\\n\", __func__,\n\t\t sw_r32(RTL930X_SMI_10GPHY_POLLING_REG9_CFG));\n\tpr_debug(\"%s: RTL930X_SMI_10GPHY_POLLING_REG10_CFG %08x\\n\", __func__,\n\t\t sw_r32(RTL930X_SMI_10GPHY_POLLING_REG10_CFG));\n\tpr_debug(\"%s: RTL930X_SMI_PRVTE_POLLING_CTRL %08x\\n\", __func__,\n\t\t sw_r32(RTL930X_SMI_PRVTE_POLLING_CTRL));\n\treturn 0;\n}\n\nstatic int rtl931x_mdio_reset(struct mii_bus *bus)\n{\n\tint i;\n\tint pos;\n\tstruct rtl838x_eth_priv *priv = bus->priv;\n\tu32 c45_mask = 0;\n\tu32 poll_sel[4];\n\tu32 poll_ctrl = 0;\n\tbool mdc_on[4];\n\n\tpr_info(\"%s called\\n\", __func__);\n\t// Disable port polling for configuration purposes\n\tsw_w32(0, RTL931X_SMI_PORT_POLLING_CTRL);\n\tsw_w32(0, RTL931X_SMI_PORT_POLLING_CTRL + 4);\n\tmsleep(100);\n\n\tmdc_on[0] = mdc_on[1] = mdc_on[2] = mdc_on[3] = false;\n\t// Mapping of port to phy-addresses on an SMI bus\n\tpoll_sel[0] = poll_sel[1] = poll_sel[2] = poll_sel[3] = 0;\n\tfor (i = 0; i < 56; i++) {\n\t\tpos = (i % 6) * 5;\n\t\tsw_w32_mask(0x1f << pos, priv->smi_addr[i] << pos, RTL931X_SMI_PORT_ADDR + (i / 6) * 4);\n\t\tpos = (i * 2) % 32;\n\t\tpoll_sel[i / 16] |= priv->smi_bus[i] << pos;\n\t\tpoll_ctrl |= BIT(20 + priv->smi_bus[i]);\n\t\tmdc_on[priv->smi_bus[i]] = true;\n\t}\n\n\t// Configure which SMI bus is behind which port number\n\tfor (i = 0; i < 4; i++) {\n\t\tpr_info(\"poll sel %d, %08x\\n\", i, poll_sel[i]);\n\t\tsw_w32(poll_sel[i], RTL931X_SMI_PORT_POLLING_SEL + (i * 4));\n\t}\n\n\t// Configure which SMI busses\n\tpr_info(\"%s: WAS RTL931X_MAC_L2_GLOBAL_CTRL2 %08x\\n\", __func__, sw_r32(RTL931X_MAC_L2_GLOBAL_CTRL2));\n\tpr_info(\"c45_mask: %08x, RTL931X_SMI_GLB_CTRL0 was %X\", c45_mask, sw_r32(RTL931X_SMI_GLB_CTRL0));\n\tfor (i = 0; i < 4; i++) {\n\t\t// bus is polled in c45\n\t\tif (priv->smi_bus_isc45[i])\n\t\t\tc45_mask |= 0x2 << (i * 2);  // Std. C45, non-standard is 0x3\n\t\t// Enable bus access via MDC\n\t\tif (mdc_on[i])\n\t\t\tsw_w32_mask(0, BIT(9 + i), RTL931X_MAC_L2_GLOBAL_CTRL2);\n\t}\n\n\tpr_info(\"%s: RTL931X_MAC_L2_GLOBAL_CTRL2 %08x\\n\", __func__, sw_r32(RTL931X_MAC_L2_GLOBAL_CTRL2));\n\tpr_info(\"c45_mask: %08x, RTL931X_SMI_GLB_CTRL0 was %X\", c45_mask, sw_r32(RTL931X_SMI_GLB_CTRL0));\n\n\t/* We have a 10G PHY enable polling\n\tsw_w32(0x01010000, RTL931X_SMI_10GPHY_POLLING_SEL2);\n\tsw_w32(0x01E7C400, RTL931X_SMI_10GPHY_POLLING_SEL3);\n\tsw_w32(0x01E7E820, RTL931X_SMI_10GPHY_POLLING_SEL4);\n*/\n\tsw_w32_mask(0xff, c45_mask, RTL931X_SMI_GLB_CTRL1);\n\n\treturn 0;\n}\n\nstatic int rtl931x_chip_init(struct rtl838x_eth_priv *priv)\n{\n\tpr_info(\"In %s\\n\", __func__);\n\n\t// Initialize Encapsulation memory and wait until finished\n\tsw_w32(0x1, RTL931X_MEM_ENCAP_INIT);\n\tdo { } while (sw_r32(RTL931X_MEM_ENCAP_INIT) & 1);\n\tpr_info(\"%s: init ENCAP done\\n\", __func__);\n\n\t// Initialize Managemen Information Base memory and wait until finished\n\tsw_w32(0x1, RTL931X_MEM_MIB_INIT);\n\tdo { } while (sw_r32(RTL931X_MEM_MIB_INIT) & 1);\n\tpr_info(\"%s: init MIB done\\n\", __func__);\n\n\t// Initialize ACL (PIE) memory and wait until finished\n\tsw_w32(0x1, RTL931X_MEM_ACL_INIT);\n\tdo { } while (sw_r32(RTL931X_MEM_ACL_INIT) & 1);\n\tpr_info(\"%s: init ACL done\\n\", __func__);\n\n\t// Initialize ALE memory and wait until finished\n\tsw_w32(0xFFFFFFFF, RTL931X_MEM_ALE_INIT_0);\n\tdo { } while (sw_r32(RTL931X_MEM_ALE_INIT_0));\n\tsw_w32(0x7F, RTL931X_MEM_ALE_INIT_1);\n\tsw_w32(0x7ff, RTL931X_MEM_ALE_INIT_2);\n\tdo { } while (sw_r32(RTL931X_MEM_ALE_INIT_2) & 0x7ff);\n\tpr_info(\"%s: init ALE done\\n\", __func__);\n\n\t// Enable ESD auto recovery\n\tsw_w32(0x1, RTL931X_MDX_CTRL_RSVD);\n\n\t// Init SPI, is this for thermal control or what?\n\tsw_w32_mask(0x7 << 11, 0x2 << 11, RTL931X_SPI_CTRL0);\n\n\treturn 0;\n}\n\nstatic int rtl838x_mdio_init(struct rtl838x_eth_priv *priv)\n{\n\tstruct device_node *mii_np, *dn;\n\tu32 pn;\n\tint ret;\n\n\tpr_debug(\"%s called\\n\", __func__);\n\tmii_np = of_get_child_by_name(priv->pdev->dev.of_node, \"mdio-bus\");\n\n\tif (!mii_np) {\n\t\tdev_err(&priv->pdev->dev, \"no %s child node found\", \"mdio-bus\");\n\t\treturn -ENODEV;\n\t}\n\n\tif (!of_device_is_available(mii_np)) {\n\t\tret = -ENODEV;\n\t\tgoto err_put_node;\n\t}\n\n\tpriv->mii_bus = devm_mdiobus_alloc(&priv->pdev->dev);\n\tif (!priv->mii_bus) {\n\t\tret = -ENOMEM;\n\t\tgoto err_put_node;\n\t}\n\n\tswitch(priv->family_id) {\n\tcase RTL8380_FAMILY_ID:\n\t\tpriv->mii_bus->name = \"rtl838x-eth-mdio\";\n\t\tpriv->mii_bus->read = rtl838x_mdio_read;\n\t\tpriv->mii_bus->read_paged = rtl838x_mdio_read_paged;\n\t\tpriv->mii_bus->write = rtl838x_mdio_write;\n\t\tpriv->mii_bus->write_paged = rtl838x_mdio_write_paged;\n\t\tpriv->mii_bus->reset = rtl838x_mdio_reset;\n\t\tbreak;\n\tcase RTL8390_FAMILY_ID:\n\t\tpriv->mii_bus->name = \"rtl839x-eth-mdio\";\n\t\tpriv->mii_bus->read = rtl839x_mdio_read;\n\t\tpriv->mii_bus->read_paged = rtl839x_mdio_read_paged;\n\t\tpriv->mii_bus->write = rtl839x_mdio_write;\n\t\tpriv->mii_bus->write_paged = rtl839x_mdio_write_paged;\n\t\tpriv->mii_bus->reset = rtl839x_mdio_reset;\n\t\tbreak;\n\tcase RTL9300_FAMILY_ID:\n\t\tpriv->mii_bus->name = \"rtl930x-eth-mdio\";\n\t\tpriv->mii_bus->read = rtl930x_mdio_read;\n\t\tpriv->mii_bus->read_paged = rtl930x_mdio_read_paged;\n\t\tpriv->mii_bus->write = rtl930x_mdio_write;\n\t\tpriv->mii_bus->write_paged = rtl930x_mdio_write_paged;\n\t\tpriv->mii_bus->reset = rtl930x_mdio_reset;\n\t\tpriv->mii_bus->probe_capabilities = MDIOBUS_C22_C45;\n\t\tbreak;\n\tcase RTL9310_FAMILY_ID:\n\t\tpriv->mii_bus->name = \"rtl931x-eth-mdio\";\n\t\tpriv->mii_bus->read = rtl931x_mdio_read;\n\t\tpriv->mii_bus->read_paged = rtl931x_mdio_read_paged;\n\t\tpriv->mii_bus->write = rtl931x_mdio_write;\n\t\tpriv->mii_bus->write_paged = rtl931x_mdio_write_paged;\n\t\tpriv->mii_bus->reset = rtl931x_mdio_reset;\n\t\tpriv->mii_bus->probe_capabilities = MDIOBUS_C22_C45;\n\t\tbreak;\n\t}\n\tpriv->mii_bus->access_capabilities = MDIOBUS_ACCESS_C22_MMD;\n\tpriv->mii_bus->priv = priv;\n\tpriv->mii_bus->parent = &priv->pdev->dev;\n\n\tfor_each_node_by_name(dn, \"ethernet-phy\") {\n\t\tu32 smi_addr[2];\n\n\t\tif (of_property_read_u32(dn, \"reg\", &pn))\n\t\t\tcontinue;\n\n\t\tif (of_property_read_u32_array(dn, \"rtl9300,smi-address\", &smi_addr[0], 2)) {\n\t\t\tsmi_addr[0] = 0;\n\t\t\tsmi_addr[1] = pn;\n\t\t}\n\n\t\tif (of_property_read_u32(dn, \"sds\", &priv->sds_id[pn]))\n\t\t\tpriv->sds_id[pn] = -1;\n\t\telse {\n\t\t\tpr_info(\"set sds port %d to %d\\n\", pn, priv->sds_id[pn]);\n\t\t}\n\n\t\tif (pn < MAX_PORTS) {\n\t\t\tpriv->smi_bus[pn] = smi_addr[0];\n\t\t\tpriv->smi_addr[pn] = smi_addr[1];\n\t\t} else {\n\t\t\tpr_err(\"%s: illegal port number %d\\n\", __func__, pn);\n\t\t}\n\n\t\tif (of_device_is_compatible(dn, \"ethernet-phy-ieee802.3-c45\"))\n\t\t\tpriv->smi_bus_isc45[smi_addr[0]] = true;\n\n\t\tif (of_property_read_bool(dn, \"phy-is-integrated\")) {\n\t\t\tpriv->phy_is_internal[pn] = true;\n\t\t}\n\t}\n\n\tdn = of_find_compatible_node(NULL, NULL, \"realtek,rtl83xx-switch\");\n\tif (!dn) {\n\t\tdev_err(&priv->pdev->dev, \"No RTL switch node in DTS\\n\");\n\t\treturn -ENODEV;\n\t}\n\n\tfor_each_node_by_name(dn, \"port\") {\n\t\tif (of_property_read_u32(dn, \"reg\", &pn))\n\t\t\tcontinue;\n\t\tpr_debug(\"%s Looking at port %d\\n\", __func__, pn);\n\t\tif (pn > priv->cpu_port)\n\t\t\tcontinue;\n\t\tif (of_get_phy_mode(dn, &priv->interfaces[pn]))\n\t\t\tpriv->interfaces[pn] = PHY_INTERFACE_MODE_NA;\n\t\tpr_debug(\"%s phy mode of port %d is %s\\n\", __func__, pn, phy_modes(priv->interfaces[pn]));\n\t}\n\n\tsnprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, \"%pOFn\", mii_np);\n\tret = of_mdiobus_register(priv->mii_bus, mii_np);\n\nerr_put_node:\n\tof_node_put(mii_np);\n\treturn ret;\n}\n\nstatic int rtl838x_mdio_remove(struct rtl838x_eth_priv *priv)\n{\n\tpr_debug(\"%s called\\n\", __func__);\n\tif (!priv->mii_bus)\n\t\treturn 0;\n\n\tmdiobus_unregister(priv->mii_bus);\n\tmdiobus_free(priv->mii_bus);\n\n\treturn 0;\n}\n\nstatic netdev_features_t rtl838x_fix_features(struct net_device *dev,\n\t\t\t\t\t  netdev_features_t features)\n{\n\treturn features;\n}\n\nstatic int rtl83xx_set_features(struct net_device *dev, netdev_features_t features)\n{\n\tstruct rtl838x_eth_priv *priv = netdev_priv(dev);\n\n\tif ((features ^ dev->features) & NETIF_F_RXCSUM) {\n\t\tif (!(features & NETIF_F_RXCSUM))\n\t\t\tsw_w32_mask(BIT(3), 0, priv->r->mac_port_ctrl(priv->cpu_port));\n\t\telse\n\t\t\tsw_w32_mask(0, BIT(4), priv->r->mac_port_ctrl(priv->cpu_port));\n\t}\n\n\treturn 0;\n}\n\nstatic int rtl93xx_set_features(struct net_device *dev, netdev_features_t features)\n{\n\tstruct rtl838x_eth_priv *priv = netdev_priv(dev);\n\n\tif ((features ^ dev->features) & NETIF_F_RXCSUM) {\n\t\tif (!(features & NETIF_F_RXCSUM))\n\t\t\tsw_w32_mask(BIT(4), 0, priv->r->mac_port_ctrl(priv->cpu_port));\n\t\telse\n\t\t\tsw_w32_mask(0, BIT(4), priv->r->mac_port_ctrl(priv->cpu_port));\n\t}\n\n\treturn 0;\n}\n\nstatic const struct net_device_ops rtl838x_eth_netdev_ops = {\n\t.ndo_open = rtl838x_eth_open,\n\t.ndo_stop = rtl838x_eth_stop,\n\t.ndo_start_xmit = rtl838x_eth_tx,\n\t.ndo_select_queue = rtl83xx_pick_tx_queue,\n\t.ndo_set_mac_address = rtl838x_set_mac_address,\n\t.ndo_validate_addr = eth_validate_addr,\n\t.ndo_set_rx_mode = rtl838x_eth_set_multicast_list,\n\t.ndo_tx_timeout = rtl838x_eth_tx_timeout,\n\t.ndo_set_features = rtl83xx_set_features,\n\t.ndo_fix_features = rtl838x_fix_features,\n\t.ndo_setup_tc = rtl83xx_setup_tc,\n};\n\nstatic const struct net_device_ops rtl839x_eth_netdev_ops = {\n\t.ndo_open = rtl838x_eth_open,\n\t.ndo_stop = rtl838x_eth_stop,\n\t.ndo_start_xmit = rtl838x_eth_tx,\n\t.ndo_select_queue = rtl83xx_pick_tx_queue,\n\t.ndo_set_mac_address = rtl838x_set_mac_address,\n\t.ndo_validate_addr = eth_validate_addr,\n\t.ndo_set_rx_mode = rtl839x_eth_set_multicast_list,\n\t.ndo_tx_timeout = rtl838x_eth_tx_timeout,\n\t.ndo_set_features = rtl83xx_set_features,\n\t.ndo_fix_features = rtl838x_fix_features,\n\t.ndo_setup_tc = rtl83xx_setup_tc,\n};\n\nstatic const struct net_device_ops rtl930x_eth_netdev_ops = {\n\t.ndo_open = rtl838x_eth_open,\n\t.ndo_stop = rtl838x_eth_stop,\n\t.ndo_start_xmit = rtl838x_eth_tx,\n\t.ndo_select_queue = rtl93xx_pick_tx_queue,\n\t.ndo_set_mac_address = rtl838x_set_mac_address,\n\t.ndo_validate_addr = eth_validate_addr,\n\t.ndo_set_rx_mode = rtl930x_eth_set_multicast_list,\n\t.ndo_tx_timeout = rtl838x_eth_tx_timeout,\n\t.ndo_set_features = rtl93xx_set_features,\n\t.ndo_fix_features = rtl838x_fix_features,\n\t.ndo_setup_tc = rtl83xx_setup_tc,\n};\n\nstatic const struct net_device_ops rtl931x_eth_netdev_ops = {\n\t.ndo_open = rtl838x_eth_open,\n\t.ndo_stop = rtl838x_eth_stop,\n\t.ndo_start_xmit = rtl838x_eth_tx,\n\t.ndo_select_queue = rtl93xx_pick_tx_queue,\n\t.ndo_set_mac_address = rtl838x_set_mac_address,\n\t.ndo_validate_addr = eth_validate_addr,\n\t.ndo_set_rx_mode = rtl931x_eth_set_multicast_list,\n\t.ndo_tx_timeout = rtl838x_eth_tx_timeout,\n\t.ndo_set_features = rtl93xx_set_features,\n\t.ndo_fix_features = rtl838x_fix_features,\n};\n\nstatic const struct phylink_mac_ops rtl838x_phylink_ops = {\n\t.validate = rtl838x_validate,\n\t.mac_pcs_get_state = rtl838x_mac_pcs_get_state,\n\t.mac_an_restart = rtl838x_mac_an_restart,\n\t.mac_config = rtl838x_mac_config,\n\t.mac_link_down = rtl838x_mac_link_down,\n\t.mac_link_up = rtl838x_mac_link_up,\n};\n\nstatic const struct ethtool_ops rtl838x_ethtool_ops = {\n\t.get_link_ksettings     = rtl838x_get_link_ksettings,\n\t.set_link_ksettings     = rtl838x_set_link_ksettings,\n};\n\nstatic int __init rtl838x_eth_probe(struct platform_device *pdev)\n{\n\tstruct net_device *dev;\n\tstruct device_node *dn = pdev->dev.of_node;\n\tstruct rtl838x_eth_priv *priv;\n\tstruct resource *res, *mem;\n\tphy_interface_t phy_mode;\n\tstruct phylink *phylink;\n\tint err = 0, i, rxrings, rxringlen;\n\tstruct ring_b *ring;\n\n\tpr_info(\"Probing RTL838X eth device pdev: %x, dev: %x\\n\",\n\t\t(u32)pdev, (u32)(&(pdev->dev)));\n\n\tif (!dn) {\n\t\tdev_err(&pdev->dev, \"No DT found\\n\");\n\t\treturn -EINVAL;\n\t}\n\n\trxrings = (soc_info.family == RTL8380_FAMILY_ID \n\t\t\t|| soc_info.family == RTL8390_FAMILY_ID) ? 8 : 32;\n\trxrings = rxrings > MAX_RXRINGS ? MAX_RXRINGS : rxrings;\n\trxringlen = MAX_ENTRIES / rxrings;\n\trxringlen = rxringlen > MAX_RXLEN ? MAX_RXLEN : rxringlen;\n\n\tdev = alloc_etherdev_mqs(sizeof(struct rtl838x_eth_priv), TXRINGS, rxrings);\n\tif (!dev) {\n\t\terr = -ENOMEM;\n\t\tgoto err_free;\n\t}\n\tSET_NETDEV_DEV(dev, &pdev->dev);\n\tpriv = netdev_priv(dev);\n\n\t/* obtain buffer memory space */\n\tres = platform_get_resource(pdev, IORESOURCE_MEM, 0);\n\tif (res) {\n\t\tmem = devm_request_mem_region(&pdev->dev, res->start,\n\t\t\tresource_size(res), res->name);\n\t\tif (!mem) {\n\t\t\tdev_err(&pdev->dev, \"cannot request memory space\\n\");\n\t\t\terr = -ENXIO;\n\t\t\tgoto err_free;\n\t\t}\n\n\t\tdev->mem_start = mem->start;\n\t\tdev->mem_end   = mem->end;\n\t} else {\n\t\tdev_err(&pdev->dev, \"cannot request IO resource\\n\");\n\t\terr = -ENXIO;\n\t\tgoto err_free;\n\t}\n\n\t/* Allocate buffer memory */\n\tpriv->membase = dmam_alloc_coherent(&pdev->dev, rxrings * rxringlen * RING_BUFFER\n\t\t\t\t+ sizeof(struct ring_b) + sizeof(struct notify_b),\n\t\t\t\t(void *)&dev->mem_start, GFP_KERNEL);\n\tif (!priv->membase) {\n\t\tdev_err(&pdev->dev, \"cannot allocate DMA buffer\\n\");\n\t\terr = -ENOMEM;\n\t\tgoto err_free;\n\t}\n\n\t// Allocate ring-buffer space at the end of the allocated memory\n\tring = priv->membase;\n\tring->rx_space = priv->membase + sizeof(struct ring_b) + sizeof(struct notify_b);\n\n\tspin_lock_init(&priv->lock);\n\n\tdev->ethtool_ops = &rtl838x_ethtool_ops;\n\tdev->min_mtu = ETH_ZLEN;\n\tdev->max_mtu = 1536;\n\tdev->features = NETIF_F_RXCSUM | NETIF_F_HW_CSUM;\n\tdev->hw_features = NETIF_F_RXCSUM;\n\n\tpriv->id = soc_info.id;\n\tpriv->family_id = soc_info.family;\n\tif (priv->id) {\n\t\tpr_info(\"Found SoC ID: %4x: %s, family %x\\n\",\n\t\t\tpriv->id, soc_info.name, priv->family_id);\n\t} else {\n\t\tpr_err(\"Unknown chip id (%04x)\\n\", priv->id);\n\t\treturn -ENODEV;\n\t}\n\n\tswitch (priv->family_id) {\n\tcase RTL8380_FAMILY_ID:\n\t\tpriv->cpu_port = RTL838X_CPU_PORT;\n\t\tpriv->r = &rtl838x_reg;\n\t\tdev->netdev_ops = &rtl838x_eth_netdev_ops;\n\t\tbreak;\n\tcase RTL8390_FAMILY_ID:\n\t\tpriv->cpu_port = RTL839X_CPU_PORT;\n\t\tpriv->r = &rtl839x_reg;\n\t\tdev->netdev_ops = &rtl839x_eth_netdev_ops;\n\t\tbreak;\n\tcase RTL9300_FAMILY_ID:\n\t\tpriv->cpu_port = RTL930X_CPU_PORT;\n\t\tpriv->r = &rtl930x_reg;\n\t\tdev->netdev_ops = &rtl930x_eth_netdev_ops;\n\t\tbreak;\n\tcase RTL9310_FAMILY_ID:\n\t\tpriv->cpu_port = RTL931X_CPU_PORT;\n\t\tpriv->r = &rtl931x_reg;\n\t\tdev->netdev_ops = &rtl931x_eth_netdev_ops;\n\t\trtl931x_chip_init(priv);\n\t\tbreak;\n\tdefault:\n\t\tpr_err(\"Unknown SoC family\\n\");\n\t\treturn -ENODEV;\n\t}\n\tpriv->rxringlen = rxringlen;\n\tpriv->rxrings = rxrings;\n\n\t/* Obtain device IRQ number */\n\tdev->irq = platform_get_irq(pdev, 0);\n\tif (dev->irq < 0) {\n\t\tdev_err(&pdev->dev, \"cannot obtain network-device IRQ\\n\");\n\t\tgoto err_free;\n\t}\n\n\terr = devm_request_irq(&pdev->dev, dev->irq, priv->r->net_irq,\n\t\t\t       IRQF_SHARED, dev->name, dev);\n\tif (err) {\n\t\tdev_err(&pdev->dev, \"%s: could not acquire interrupt: %d\\n\",\n\t\t\t   __func__, err);\n\t\tgoto err_free;\n\t}\n\n\trtl8380_init_mac(priv);\n\n\t/* try to get mac address in the following order:\n\t * 1) from device tree data\n\t * 2) from internal registers set by bootloader\n\t */\n\tof_get_mac_address(pdev->dev.of_node, dev->dev_addr);\n\tif (is_valid_ether_addr(dev->dev_addr)) {\n\t\trtl838x_set_mac_hw(dev, (u8 *)dev->dev_addr);\n\t} else {\n\t\tdev->dev_addr[0] = (sw_r32(priv->r->mac) >> 8) & 0xff;\n\t\tdev->dev_addr[1] = sw_r32(priv->r->mac) & 0xff;\n\t\tdev->dev_addr[2] = (sw_r32(priv->r->mac + 4) >> 24) & 0xff;\n\t\tdev->dev_addr[3] = (sw_r32(priv->r->mac + 4) >> 16) & 0xff;\n\t\tdev->dev_addr[4] = (sw_r32(priv->r->mac + 4) >> 8) & 0xff;\n\t\tdev->dev_addr[5] = sw_r32(priv->r->mac + 4) & 0xff;\n\t}\n\t/* if the address is invalid, use a random value */\n\tif (!is_valid_ether_addr(dev->dev_addr)) {\n\t\tstruct sockaddr sa = { AF_UNSPEC };\n\n\t\tnetdev_warn(dev, \"Invalid MAC address, using random\\n\");\n\t\teth_hw_addr_random(dev);\n\t\tmemcpy(sa.sa_data, dev->dev_addr, ETH_ALEN);\n\t\tif (rtl838x_set_mac_address(dev, &sa))\n\t\t\tnetdev_warn(dev, \"Failed to set MAC address.\\n\");\n\t}\n\tpr_info(\"Using MAC %08x%08x\\n\", sw_r32(priv->r->mac),\n\t\t\t\t\tsw_r32(priv->r->mac + 4));\n\tstrcpy(dev->name, \"eth%d\");\n\tpriv->pdev = pdev;\n\tpriv->netdev = dev;\n\n\terr = rtl838x_mdio_init(priv);\n\tif (err)\n\t\tgoto err_free;\n\n\terr = register_netdev(dev);\n\tif (err)\n\t\tgoto err_free;\n\n\tfor (i = 0; i < priv->rxrings; i++) {\n\t\tpriv->rx_qs[i].id = i;\n\t\tpriv->rx_qs[i].priv = priv;\n\t\tnetif_napi_add(dev, &priv->rx_qs[i].napi, rtl838x_poll_rx, 64);\n\t}\n\n\tplatform_set_drvdata(pdev, dev);\n\n\tphy_mode = PHY_INTERFACE_MODE_NA;\n\terr = of_get_phy_mode(dn, &phy_mode);\n\tif (err < 0) {\n\t\tdev_err(&pdev->dev, \"incorrect phy-mode\\n\");\n\t\terr = -EINVAL;\n\t\tgoto err_free;\n\t}\n\tpriv->phylink_config.dev = &dev->dev;\n\tpriv->phylink_config.type = PHYLINK_NETDEV;\n\n\tphylink = phylink_create(&priv->phylink_config, pdev->dev.fwnode,\n\t\t\t\t phy_mode, &rtl838x_phylink_ops);\n\n\tif (IS_ERR(phylink)) {\n\t\terr = PTR_ERR(phylink);\n\t\tgoto err_free;\n\t}\n\tpriv->phylink = phylink;\n\n\treturn 0;\n\nerr_free:\n\tpr_err(\"Error setting up netdev, freeing it again.\\n\");\n\tfree_netdev(dev);\n\treturn err;\n}\n\nstatic int rtl838x_eth_remove(struct platform_device *pdev)\n{\n\tstruct net_device *dev = platform_get_drvdata(pdev);\n\tstruct rtl838x_eth_priv *priv = netdev_priv(dev);\n\tint i;\n\n\tif (dev) {\n\t\tpr_info(\"Removing platform driver for rtl838x-eth\\n\");\n\t\trtl838x_mdio_remove(priv);\n\t\trtl838x_hw_stop(priv);\n\n\t\tnetif_tx_stop_all_queues(dev);\n\n\t\tfor (i = 0; i < priv->rxrings; i++)\n\t\t\tnetif_napi_del(&priv->rx_qs[i].napi);\n\n\t\tunregister_netdev(dev);\n\t\tfree_netdev(dev);\n\t}\n\treturn 0;\n}\n\nstatic const struct of_device_id rtl838x_eth_of_ids[] = {\n\t{ .compatible = \"realtek,rtl838x-eth\"},\n\t{ /* sentinel */ }\n};\nMODULE_DEVICE_TABLE(of, rtl838x_eth_of_ids);\n\nstatic struct platform_driver rtl838x_eth_driver = {\n\t.probe = rtl838x_eth_probe,\n\t.remove = rtl838x_eth_remove,\n\t.driver = {\n\t\t.name = \"rtl838x-eth\",\n\t\t.pm = NULL,\n\t\t.of_match_table = rtl838x_eth_of_ids,\n\t},\n};\n\nmodule_platform_driver(rtl838x_eth_driver);\n\nMODULE_AUTHOR(\"B. Koblitz\");\nMODULE_DESCRIPTION(\"RTL838X SoC Ethernet Driver\");\nMODULE_LICENSE(\"GPL\");\n"
  },
  {
    "path": "target/linux/realtek/files-5.10/drivers/net/ethernet/rtl838x_eth.h",
    "content": "/* SPDX-License-Identifier: GPL-2.0-only */\n\n#ifndef _RTL838X_ETH_H\n#define _RTL838X_ETH_H\n\n/*\n * Register definition\n */\n\n/* Per port MAC control */\n#define RTL838X_MAC_PORT_CTRL\t\t\t(0xd560)\n#define RTL839X_MAC_PORT_CTRL\t\t\t(0x8004)\n#define RTL930X_MAC_L2_PORT_CTRL\t\t(0x3268)\n#define RTL930X_MAC_PORT_CTRL\t\t\t(0x3260)\n#define RTL931X_MAC_L2_PORT_CTRL\t\t(0x6000)\n#define RTL931X_MAC_PORT_CTRL\t\t\t(0x6004)\n\n/* DMA interrupt control and status registers */\n#define RTL838X_DMA_IF_CTRL\t\t\t(0x9f58)\n#define RTL838X_DMA_IF_INTR_STS\t\t\t(0x9f54)\n#define RTL838X_DMA_IF_INTR_MSK\t\t\t(0x9f50)\n\n#define RTL839X_DMA_IF_CTRL\t\t\t(0x786c)\n#define RTL839X_DMA_IF_INTR_STS\t\t\t(0x7868)\n#define RTL839X_DMA_IF_INTR_MSK\t\t\t(0x7864)\n\n#define RTL930X_DMA_IF_CTRL\t\t\t(0xe028)\n#define RTL930X_DMA_IF_INTR_RX_RUNOUT_STS\t(0xe01C)\n#define RTL930X_DMA_IF_INTR_RX_DONE_STS\t\t(0xe020)\n#define RTL930X_DMA_IF_INTR_TX_DONE_STS\t\t(0xe024)\n#define RTL930X_DMA_IF_INTR_RX_RUNOUT_MSK\t(0xe010)\n#define RTL930X_DMA_IF_INTR_RX_DONE_MSK\t\t(0xe014)\n#define RTL930X_DMA_IF_INTR_TX_DONE_MSK\t\t(0xe018)\n#define RTL930X_L2_NTFY_IF_INTR_MSK\t\t(0xe04C)\n#define RTL930X_L2_NTFY_IF_INTR_STS\t\t(0xe050)\n\n/* TODO: RTL931X_DMA_IF_CTRL has different bits meanings */\n#define RTL931X_DMA_IF_CTRL\t\t\t(0x0928)\n#define RTL931X_DMA_IF_INTR_RX_RUNOUT_STS\t(0x091c)\n#define RTL931X_DMA_IF_INTR_RX_DONE_STS\t\t(0x0920)\n#define RTL931X_DMA_IF_INTR_TX_DONE_STS\t\t(0x0924)\n#define RTL931X_DMA_IF_INTR_RX_RUNOUT_MSK\t(0x0910)\n#define RTL931X_DMA_IF_INTR_RX_DONE_MSK\t\t(0x0914)\n#define RTL931X_DMA_IF_INTR_TX_DONE_MSK\t\t(0x0918)\n#define RTL931X_L2_NTFY_IF_INTR_MSK\t\t(0x09E4)\n#define RTL931X_L2_NTFY_IF_INTR_STS\t\t(0x09E8)\n\n#define RTL838X_MAC_FORCE_MODE_CTRL\t\t(0xa104)\n#define RTL839X_MAC_FORCE_MODE_CTRL\t\t(0x02bc)\n#define RTL930X_MAC_FORCE_MODE_CTRL\t\t(0xCA1C)\n#define RTL931X_MAC_FORCE_MODE_CTRL\t\t(0x0ddc)\n\n/* MAC address settings */\n#define RTL838X_MAC\t\t\t\t(0xa9ec)\n#define RTL839X_MAC\t\t\t\t(0x02b4)\n#define RTL838X_MAC_ALE\t\t\t\t(0x6b04)\n#define RTL838X_MAC2\t\t\t\t(0xa320)\n#define RTL930X_MAC_L2_ADDR_CTRL\t\t(0xC714)\n#define RTL931X_MAC_L2_ADDR_CTRL\t\t(0x135c)\n\n/* Ringbuffer setup */\n#define RTL838X_DMA_RX_BASE\t\t\t(0x9f00)\n#define RTL839X_DMA_RX_BASE\t\t\t(0x780c)\n#define RTL930X_DMA_RX_BASE\t\t\t(0xdf00)\n#define RTL931X_DMA_RX_BASE\t\t\t(0x0800)\n\n#define RTL838X_DMA_TX_BASE\t\t\t(0x9f40)\n#define RTL839X_DMA_TX_BASE\t\t\t(0x784c)\n#define RTL930X_DMA_TX_BASE\t\t\t(0xe000)\n#define RTL931X_DMA_TX_BASE\t\t\t(0x0900)\n\n#define RTL838X_DMA_IF_RX_RING_SIZE\t\t(0xB7E4)\n#define RTL839X_DMA_IF_RX_RING_SIZE\t\t(0x6038)\n#define RTL930X_DMA_IF_RX_RING_SIZE\t\t(0x7C60)\n#define RTL931X_DMA_IF_RX_RING_SIZE\t\t(0x2080)\n\n#define RTL838X_DMA_IF_RX_RING_CNTR\t\t(0xB7E8)\n#define RTL839X_DMA_IF_RX_RING_CNTR\t\t(0x603c)\n#define RTL930X_DMA_IF_RX_RING_CNTR\t\t(0x7C8C)\n#define RTL931X_DMA_IF_RX_RING_CNTR\t\t(0x20AC)\n\n#define RTL838X_DMA_IF_RX_CUR\t\t\t(0x9F20)\n#define RTL839X_DMA_IF_RX_CUR\t\t\t(0x782c)\n#define RTL930X_DMA_IF_RX_CUR\t\t\t(0xdf80)\n#define RTL931X_DMA_IF_RX_CUR\t\t\t(0x0880)\n\n#define RTL838X_DMA_IF_TX_CUR_DESC_ADDR_CTRL\t(0x9F48)\n#define RTL930X_DMA_IF_TX_CUR_DESC_ADDR_CTRL\t(0xE008)\n\n#define RTL838X_DMY_REG31\t\t\t(0x3b28)\n#define RTL838X_SDS_MODE_SEL\t\t\t(0x0028)\n#define RTL838X_SDS_CFG_REG\t\t\t(0x0034)\n#define RTL838X_INT_MODE_CTRL\t\t\t(0x005c)\n#define RTL838X_CHIP_INFO\t\t\t(0x00d8)\n#define RTL838X_SDS4_REG28\t\t\t(0xef80)\n#define RTL838X_SDS4_DUMMY0\t\t\t(0xef8c)\n#define RTL838X_SDS5_EXT_REG6\t\t\t(0xf18c)\n\n/* L2 features */\n#define RTL839X_TBL_ACCESS_L2_CTRL\t\t(0x1180)\n#define RTL839X_TBL_ACCESS_L2_DATA(idx)\t\t(0x1184 + ((idx) << 2))\n#define RTL838X_TBL_ACCESS_CTRL_0\t\t(0x6914)\n#define RTL838X_TBL_ACCESS_DATA_0(idx)\t\t(0x6918 + ((idx) << 2))\n\n/* MAC-side link state handling */\n#define RTL838X_MAC_LINK_STS\t\t\t(0xa188)\n#define RTL839X_MAC_LINK_STS\t\t\t(0x0390)\n#define RTL930X_MAC_LINK_STS\t\t\t(0xCB10)\n#define RTL931X_MAC_LINK_STS\t\t\t(0x0ec0)\n\n#define RTL838X_MAC_LINK_SPD_STS\t\t(0xa190)\n#define RTL839X_MAC_LINK_SPD_STS\t\t(0x03a0)\n#define RTL930X_MAC_LINK_SPD_STS\t\t(0xCB18)\n#define RTL931X_MAC_LINK_SPD_STS\t\t(0x0ed0)\n\n#define RTL838X_MAC_LINK_DUP_STS\t\t(0xa19c)\n#define RTL839X_MAC_LINK_DUP_STS\t\t(0x03b0)\n#define RTL930X_MAC_LINK_DUP_STS\t\t(0xCB28)\n#define RTL931X_MAC_LINK_DUP_STS\t\t(0x0ef0)\n\n// TODO: RTL8390_MAC_LINK_MEDIA_STS_ADDR ???\n\n#define RTL838X_MAC_TX_PAUSE_STS\t\t(0xa1a0)\n#define RTL839X_MAC_TX_PAUSE_STS\t\t(0x03b8)\n#define RTL930X_MAC_TX_PAUSE_STS\t\t(0xCB2C)\n#define RTL931X_MAC_TX_PAUSE_STS\t\t(0x0ef8)\n\n#define RTL838X_MAC_RX_PAUSE_STS\t\t(0xa1a4)\n#define RTL839X_MAC_RX_PAUSE_STS\t\t(0xCB30)\n#define RTL930X_MAC_RX_PAUSE_STS\t\t(0xC2F8)\n#define RTL931X_MAC_RX_PAUSE_STS\t\t(0x0f00)\n\n#define RTL838X_EEE_TX_TIMER_GIGA_CTRL\t\t(0xaa04)\n#define RTL838X_EEE_TX_TIMER_GELITE_CTRL\t(0xaa08)\n\n#define RTL930X_L2_UNKN_UC_FLD_PMSK\t\t(0x9064)\n#define RTL931X_L2_UNKN_UC_FLD_PMSK\t\t(0xC8F4)\n\n#define RTL839X_MAC_GLB_CTRL\t\t\t(0x02a8)\n#define RTL839X_SCHED_LB_TICK_TKN_CTRL\t\t(0x60f8)\n\n#define RTL838X_L2_TBL_FLUSH_CTRL\t\t(0x3370)\n#define RTL839X_L2_TBL_FLUSH_CTRL\t\t(0x3ba0)\n#define RTL930X_L2_TBL_FLUSH_CTRL\t\t(0x9404)\n#define RTL931X_L2_TBL_FLUSH_CTRL\t\t(0xCD9C)\n\n#define RTL930X_L2_PORT_SABLK_CTRL\t\t(0x905c)\n#define RTL930X_L2_PORT_DABLK_CTRL\t\t(0x9060)\n\n/* MAC link state bits */\n#define FORCE_EN\t\t\t\t(1 << 0)\n#define FORCE_LINK_EN\t\t\t\t(1 << 1)\n#define NWAY_EN\t\t\t\t\t(1 << 2)\n#define DUPLX_MODE\t\t\t\t(1 << 3)\n#define TX_PAUSE_EN\t\t\t\t(1 << 6)\n#define RX_PAUSE_EN\t\t\t\t(1 << 7)\n\n/* L2 Notification DMA interface */\n#define RTL839X_DMA_IF_NBUF_BASE_DESC_ADDR_CTRL\t(0x785C)\n#define RTL839X_L2_NOTIFICATION_CTRL\t\t(0x7808)\n#define RTL931X_L2_NTFY_RING_BASE_ADDR\t\t(0x09DC)\n#define RTL931X_L2_NTFY_RING_CUR_ADDR\t\t(0x09E0)\n#define RTL839X_L2_NOTIFICATION_CTRL\t\t(0x7808)\n#define RTL931X_L2_NTFY_CTRL\t\t\t(0xCDC8)\n#define RTL838X_L2_CTRL_0\t\t\t(0x3200)\n#define RTL839X_L2_CTRL_0\t\t\t(0x3800)\n#define RTL930X_L2_CTRL\t\t\t\t(0x8FD8)\n#define RTL931X_L2_CTRL\t\t\t\t(0xC800)\n\n/* TRAPPING to CPU-PORT */\n#define RTL838X_SPCL_TRAP_IGMP_CTRL\t\t(0x6984)\n#define RTL838X_RMA_CTRL_0\t\t\t(0x4300)\n#define RTL838X_RMA_CTRL_1\t\t\t(0x4304)\n#define RTL839X_RMA_CTRL_0\t\t\t(0x1200)\n\n#define RTL839X_SPCL_TRAP_IGMP_CTRL\t\t(0x1058)\n#define RTL839X_RMA_CTRL_1\t\t\t(0x1204)\n#define RTL839X_RMA_CTRL_2\t\t\t(0x1208)\n#define RTL839X_RMA_CTRL_3\t\t\t(0x120C)\n\n#define RTL930X_VLAN_APP_PKT_CTRL\t\t(0xA23C)\n#define RTL930X_RMA_CTRL_0\t\t\t(0x9E60)\n#define RTL930X_RMA_CTRL_1\t\t\t(0x9E64)\n#define RTL930X_RMA_CTRL_2\t\t\t(0x9E68)\n\n#define RTL931X_VLAN_APP_PKT_CTRL\t\t(0x96b0)\n#define RTL931X_RMA_CTRL_0\t\t\t(0x8800)\n#define RTL931X_RMA_CTRL_1\t\t\t(0x8804)\n#define RTL931X_RMA_CTRL_2\t\t\t(0x8808)\n\n/* Advanced SMI control for clause 45 PHYs */\n#define RTL930X_SMI_MAC_TYPE_CTRL\t\t(0xCA04)\n#define RTL930X_SMI_PORT24_27_ADDR_CTRL\t\t(0xCB90)\n#define RTL930X_SMI_PORT0_15_POLLING_SEL\t(0xCA08)\n#define RTL930X_SMI_PORT16_27_POLLING_SEL\t(0xCA0C)\n\n#define RTL930X_SMI_10GPHY_POLLING_REG0_CFG\t(0xCBB4)\n#define RTL930X_SMI_10GPHY_POLLING_REG9_CFG\t(0xCBB8)\n#define RTL930X_SMI_10GPHY_POLLING_REG10_CFG\t(0xCBBC)\n#define RTL930X_SMI_PRVTE_POLLING_CTRL\t\t(0xCA10)\n\n/* Registers of the internal Serdes of the 8390 */\n#define RTL839X_SDS12_13_XSG0\t\t\t(0xB800)\n\n/* Chip configuration registers of the RTL9310 */\n#define RTL931X_MEM_ENCAP_INIT\t\t\t(0x4854)\n#define RTL931X_MEM_MIB_INIT\t\t\t(0x7E18)\n#define RTL931X_MEM_ACL_INIT\t\t\t(0x40BC)\n#define RTL931X_MEM_ALE_INIT_0\t\t\t(0x83F0)\n#define RTL931X_MEM_ALE_INIT_1\t\t\t(0x83F4)\n#define RTL931X_MEM_ALE_INIT_2\t\t\t(0x82E4)\n#define RTL931X_MDX_CTRL_RSVD\t\t\t(0x0fcc)\n#define RTL931X_PS_SOC_CTRL\t\t\t(0x13f8)\n#define RTL931X_SMI_10GPHY_POLLING_SEL2\t\t(0xCF8)\n#define RTL931X_SMI_10GPHY_POLLING_SEL3\t\t(0xCFC)\n#define RTL931X_SMI_10GPHY_POLLING_SEL4\t\t(0xD00)\n\n/* Registers of the internal Serdes of the 8380 */\n#define RTL838X_SDS4_FIB_REG0\t\t\t(0xF800)\n\ninline int rtl838x_mac_port_ctrl(int p)\n{\n\treturn RTL838X_MAC_PORT_CTRL + (p << 7);\n}\n\ninline int rtl839x_mac_port_ctrl(int p)\n{\n\treturn RTL839X_MAC_PORT_CTRL + (p << 7);\n}\n\n/* On the RTL931XX, the functionality of the MAC port control register is split up\n * into RTL931X_MAC_L2_PORT_CTRL and RTL931X_MAC_PORT_CTRL the functionality used\n * by the Ethernet driver is in the same bits now in RTL931X_MAC_L2_PORT_CTRL\n */\n\ninline int rtl930x_mac_port_ctrl(int p)\n{\n\treturn RTL930X_MAC_L2_PORT_CTRL + (p << 6);\n}\n\ninline int rtl931x_mac_port_ctrl(int p)\n{\n\treturn RTL931X_MAC_L2_PORT_CTRL + (p << 7);\n}\n\ninline int rtl838x_dma_if_rx_ring_size(int i)\n{\n\treturn RTL838X_DMA_IF_RX_RING_SIZE + ((i >> 3) << 2);\n}\n\ninline int rtl839x_dma_if_rx_ring_size(int i)\n{\n\treturn RTL839X_DMA_IF_RX_RING_SIZE + ((i >> 3) << 2);\n}\n\ninline int rtl930x_dma_if_rx_ring_size(int i)\n{\n\treturn RTL930X_DMA_IF_RX_RING_SIZE + ((i / 3) << 2);\n}\n\ninline int rtl931x_dma_if_rx_ring_size(int i)\n{\n\treturn RTL931X_DMA_IF_RX_RING_SIZE + ((i / 3) << 2);\n}\n\ninline int rtl838x_dma_if_rx_ring_cntr(int i)\n{\n\treturn RTL838X_DMA_IF_RX_RING_CNTR + ((i >> 3) << 2);\n}\n\ninline int rtl839x_dma_if_rx_ring_cntr(int i)\n{\n\treturn RTL839X_DMA_IF_RX_RING_CNTR + ((i >> 3) << 2);\n}\n\ninline int rtl930x_dma_if_rx_ring_cntr(int i)\n{\n\treturn RTL930X_DMA_IF_RX_RING_CNTR + ((i / 3) << 2);\n}\n\ninline int rtl931x_dma_if_rx_ring_cntr(int i)\n{\n\treturn RTL931X_DMA_IF_RX_RING_CNTR + ((i / 3) << 2);\n}\n\ninline u32 rtl838x_get_mac_link_sts(int port)\n{\n\treturn (sw_r32(RTL838X_MAC_LINK_STS) & BIT(port));\n}\n\ninline u32 rtl839x_get_mac_link_sts(int p)\n{\n\treturn (sw_r32(RTL839X_MAC_LINK_STS + ((p >> 5) << 2)) & BIT(p % 32));\n}\n\ninline u32 rtl930x_get_mac_link_sts(int port)\n{\n\tu32 link = sw_r32(RTL930X_MAC_LINK_STS);\n\n\tlink = sw_r32(RTL930X_MAC_LINK_STS);\n\tpr_info(\"%s link state is %08x\\n\", __func__, link);\n\treturn link & BIT(port);\n}\n\ninline u32 rtl931x_get_mac_link_sts(int p)\n{\n\treturn (sw_r32(RTL931X_MAC_LINK_STS + ((p >> 5) << 2)) & BIT(p % 32));\n}\n\ninline u32 rtl838x_get_mac_link_dup_sts(int port)\n{\n\treturn (sw_r32(RTL838X_MAC_LINK_DUP_STS) & BIT(port));\n}\n\ninline u32 rtl839x_get_mac_link_dup_sts(int p)\n{\n\treturn (sw_r32(RTL839X_MAC_LINK_DUP_STS + ((p >> 5) << 2)) & BIT(p % 32));\n}\n\ninline u32 rtl930x_get_mac_link_dup_sts(int port)\n{\n\treturn (sw_r32(RTL930X_MAC_LINK_DUP_STS) & BIT(port));\n}\n\ninline u32 rtl931x_get_mac_link_dup_sts(int p)\n{\n\treturn (sw_r32(RTL931X_MAC_LINK_DUP_STS + ((p >> 5) << 2)) & BIT(p % 32));\n}\n\ninline u32 rtl838x_get_mac_link_spd_sts(int port)\n{\n\tint r = RTL838X_MAC_LINK_SPD_STS + ((port >> 4) << 2);\n\tu32 speed = sw_r32(r);\n\n\tspeed >>= (port % 16) << 1;\n\treturn (speed & 0x3);\n}\n\ninline u32 rtl839x_get_mac_link_spd_sts(int port)\n{\n\tint r = RTL839X_MAC_LINK_SPD_STS + ((port >> 4) << 2);\n\tu32 speed = sw_r32(r);\n\n\tspeed >>= (port % 16) << 1;\n\treturn (speed & 0x3);\n}\n\n\ninline u32 rtl930x_get_mac_link_spd_sts(int port)\n{\n\tint r = RTL930X_MAC_LINK_SPD_STS + ((port / 10) << 2);\n\tu32 speed = sw_r32(r);\n\n\tspeed >>= (port % 10) * 3;\n\treturn (speed & 0x7);\n}\n\ninline u32 rtl931x_get_mac_link_spd_sts(int port)\n{\n\tint r = RTL931X_MAC_LINK_SPD_STS + ((port >> 3) << 2);\n\tu32 speed = sw_r32(r);\n\n\tspeed >>= (port % 8) << 2;\n\treturn (speed & 0xf);\n}\n\ninline u32 rtl838x_get_mac_rx_pause_sts(int port)\n{\n\treturn (sw_r32(RTL838X_MAC_RX_PAUSE_STS) & (1 << port));\n}\n\ninline u32 rtl839x_get_mac_rx_pause_sts(int p)\n{\n\treturn (sw_r32(RTL839X_MAC_RX_PAUSE_STS + ((p >> 5) << 2)) & BIT(p % 32));\n}\n\ninline u32 rtl930x_get_mac_rx_pause_sts(int port)\n{\n\treturn (sw_r32(RTL930X_MAC_RX_PAUSE_STS) & (1 << port));\n}\n\ninline u32 rtl931x_get_mac_rx_pause_sts(int p)\n{\n\treturn (sw_r32(RTL931X_MAC_RX_PAUSE_STS + ((p >> 5) << 2)) & BIT(p % 32));\n}\n\ninline u32 rtl838x_get_mac_tx_pause_sts(int port)\n{\n\treturn (sw_r32(RTL838X_MAC_TX_PAUSE_STS) & (1 << port));\n}\n\ninline u32 rtl839x_get_mac_tx_pause_sts(int p)\n{\n\treturn (sw_r32(RTL839X_MAC_TX_PAUSE_STS + ((p >> 5) << 2)) & BIT(p % 32));\n}\n\ninline u32 rtl930x_get_mac_tx_pause_sts(int port)\n{\n\treturn (sw_r32(RTL930X_MAC_TX_PAUSE_STS) & (1 << port));\n}\n\ninline u32 rtl931x_get_mac_tx_pause_sts(int p)\n{\n\treturn (sw_r32(RTL931X_MAC_TX_PAUSE_STS + ((p >> 5) << 2)) & BIT(p % 32));\n}\n\nstruct p_hdr;\nstruct dsa_tag;\n\nstruct rtl838x_eth_reg {\n\tirqreturn_t (*net_irq)(int irq, void *dev_id);\n\tint (*mac_port_ctrl)(int port);\n\tint dma_if_intr_sts;\n\tint dma_if_intr_msk;\n\tint dma_if_intr_rx_runout_sts;\n\tint dma_if_intr_rx_done_sts;\n\tint dma_if_intr_tx_done_sts;\n\tint dma_if_intr_rx_runout_msk;\n\tint dma_if_intr_rx_done_msk;\n\tint dma_if_intr_tx_done_msk;\n\tint l2_ntfy_if_intr_sts;\n\tint l2_ntfy_if_intr_msk;\n\tint dma_if_ctrl;\n\tint mac_force_mode_ctrl;\n\tint dma_rx_base;\n\tint dma_tx_base;\n\tint (*dma_if_rx_ring_size)(int ring);\n\tint (*dma_if_rx_ring_cntr)(int ring);\n\tint dma_if_rx_cur;\n\tint rst_glb_ctrl;\n\tu32 (*get_mac_link_sts)(int port);\n\tu32 (*get_mac_link_dup_sts)(int port);\n\tu32 (*get_mac_link_spd_sts)(int port);\n\tu32 (*get_mac_rx_pause_sts)(int port);\n\tu32 (*get_mac_tx_pause_sts)(int port);\n\tint mac;\n\tint l2_tbl_flush_ctrl;\n\tvoid (*update_cntr)(int r, int work_done);\n\tvoid (*create_tx_header)(struct p_hdr *h, int dest_port, int prio);\n\tbool (*decode_tag)(struct p_hdr *h, struct dsa_tag *tag);\n};\n\nint rtl838x_write_phy(u32 port, u32 page, u32 reg, u32 val);\nint rtl838x_read_phy(u32 port, u32 page, u32 reg, u32 *val);\nint rtl838x_write_mmd_phy(u32 port, u32 addr, u32 reg, u32 val);\nint rtl838x_read_mmd_phy(u32 port, u32 addr, u32 reg, u32 *val);\nint rtl839x_write_phy(u32 port, u32 page, u32 reg, u32 val);\nint rtl839x_read_phy(u32 port, u32 page, u32 reg, u32 *val);\nint rtl839x_read_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 *val);\nint rtl839x_write_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 val);\nint rtl930x_write_phy(u32 port, u32 page, u32 reg, u32 val);\nint rtl930x_read_phy(u32 port, u32 page, u32 reg, u32 *val);\nint rtl931x_write_phy(u32 port, u32 page, u32 reg, u32 val);\nint rtl931x_read_phy(u32 port, u32 page, u32 reg, u32 *val);\nint rtl83xx_setup_tc(struct net_device *dev, enum tc_setup_type type, void *type_data);\n\n#endif /* _RTL838X_ETH_H */\n"
  },
  {
    "path": "target/linux/realtek/files-5.10/drivers/net/phy/rtl83xx-phy.c",
    "content": "// SPDX-License-Identifier: GPL-2.0-only\n/* Realtek RTL838X Ethernet MDIO interface driver\n *\n * Copyright (C) 2020 B. Koblitz\n */\n\n#include <linux/module.h>\n#include <linux/delay.h>\n#include <linux/phy.h>\n#include <linux/netdevice.h>\n#include <linux/firmware.h>\n#include <linux/crc32.h>\n\n#include <asm/mach-rtl838x/mach-rtl83xx.h>\n#include \"rtl83xx-phy.h\"\n\nextern struct rtl83xx_soc_info soc_info;\nextern struct mutex smi_lock;\n\n#define PHY_CTRL_REG\t0\n#define PHY_POWER_BIT\t11\n\n#define PHY_PAGE_2\t2\n#define PHY_PAGE_4\t4\n\n/* all Clause-22 RealTek MDIO PHYs use register 0x1f for page select */\n#define RTL8XXX_PAGE_SELECT\t\t0x1f\n\n#define RTL8XXX_PAGE_MAIN\t\t0x0000\n#define RTL821X_PAGE_PORT\t\t0x0266\n#define RTL821X_PAGE_POWER\t\t0x0a40\n#define RTL821X_PAGE_GPHY\t\t0x0a42\n#define RTL821X_PAGE_MAC\t\t0x0a43\n#define RTL821X_PAGE_STATE\t\t0x0b80\n#define RTL821X_PAGE_PATCH\t\t0x0b82\n\n/*\n * Using the special page 0xfff with the MDIO controller found in\n * RealTek SoCs allows to access the PHY in RAW mode, ie. bypassing\n * the cache and paging engine of the MDIO controller.\n */\n#define RTL83XX_PAGE_RAW\t\t0x0fff\n\n/* internal RTL821X PHY uses register 0x1d to select media page */\n#define RTL821XINT_MEDIA_PAGE_SELECT\t0x1d\n/* external RTL821X PHY uses register 0x1e to select media page */\n#define RTL821XEXT_MEDIA_PAGE_SELECT\t0x1e\n\n#define RTL821X_MEDIA_PAGE_AUTO\t\t0\n#define RTL821X_MEDIA_PAGE_COPPER\t1\n#define RTL821X_MEDIA_PAGE_FIBRE\t3\n#define RTL821X_MEDIA_PAGE_INTERNAL\t8\n\n#define RTL9300_PHY_ID_MASK 0xf0ffffff\n\n/*\n * This lock protects the state of the SoC automatically polling the PHYs over the SMI\n * bus to detect e.g. link and media changes. For operations on the PHYs such as\n * patching or other configuration changes such as EEE, polling needs to be disabled\n * since otherwise these operations may fails or lead to unpredictable results.\n */\nDEFINE_MUTEX(poll_lock);\n\nstatic const struct firmware rtl838x_8380_fw;\nstatic const struct firmware rtl838x_8214fc_fw;\nstatic const struct firmware rtl838x_8218b_fw;\n\nstatic u64 disable_polling(int port)\n{\n\tu64 saved_state;\n\n\tmutex_lock(&poll_lock);\n\n\tswitch (soc_info.family) {\n\tcase RTL8380_FAMILY_ID:\n\t\tsaved_state = sw_r32(RTL838X_SMI_POLL_CTRL);\n\t\tsw_w32_mask(BIT(port), 0, RTL838X_SMI_POLL_CTRL);\n\t\tbreak;\n\tcase RTL8390_FAMILY_ID:\n\t\tsaved_state = sw_r32(RTL839X_SMI_PORT_POLLING_CTRL + 4);\n\t\tsaved_state <<= 32;\n\t\tsaved_state |= sw_r32(RTL839X_SMI_PORT_POLLING_CTRL);\n\t\tsw_w32_mask(BIT(port % 32), 0,\n\t\t\t    RTL839X_SMI_PORT_POLLING_CTRL + ((port >> 5) << 2));\n\t\tbreak;\n\tcase RTL9300_FAMILY_ID:\n\t\tsaved_state = sw_r32(RTL930X_SMI_POLL_CTRL);\n\t\tsw_w32_mask(BIT(port), 0, RTL930X_SMI_POLL_CTRL);\n\t\tbreak;\n\tcase RTL9310_FAMILY_ID:\n\t\tpr_warn(\"%s not implemented for RTL931X\\n\", __func__);\n\t\tbreak;\n\t}\n\n\tmutex_unlock(&poll_lock);\n\n\treturn saved_state;\n}\n\nstatic int resume_polling(u64 saved_state)\n{\n\tmutex_lock(&poll_lock);\n\n\tswitch (soc_info.family) {\n\tcase RTL8380_FAMILY_ID:\n\t\tsw_w32(saved_state, RTL838X_SMI_POLL_CTRL);\n\t\tbreak;\n\tcase RTL8390_FAMILY_ID:\n\t\tsw_w32(saved_state >> 32, RTL839X_SMI_PORT_POLLING_CTRL + 4);\n\t\tsw_w32(saved_state, RTL839X_SMI_PORT_POLLING_CTRL);\n\t\tbreak;\n\tcase RTL9300_FAMILY_ID:\n\t\tsw_w32(saved_state, RTL930X_SMI_POLL_CTRL);\n\t\tbreak;\n\tcase RTL9310_FAMILY_ID:\n\t\tpr_warn(\"%s not implemented for RTL931X\\n\", __func__);\n\t\tbreak;\n\t}\n\n\tmutex_unlock(&poll_lock);\n\n\treturn 0;\n}\n\nstatic void rtl8380_int_phy_on_off(struct phy_device *phydev, bool on)\n{\n\tphy_modify(phydev, 0, BIT(11), on?0:BIT(11));\n}\n\nstatic void rtl8380_rtl8214fc_on_off(struct phy_device *phydev, bool on)\n{\n\t/* fiber ports */\n\tphy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_FIBRE);\n\tphy_modify(phydev, 0x10, BIT(11), on?0:BIT(11));\n\n\t/* copper ports */\n\tphy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);\n\tphy_modify_paged(phydev, RTL821X_PAGE_POWER, 0x10, BIT(11), on?0:BIT(11));\n}\n\nstatic void rtl8380_phy_reset(struct phy_device *phydev)\n{\n\tphy_modify(phydev, 0, BIT(15), BIT(15));\n}\n\n// The access registers for SDS_MODE_SEL and the LSB for each SDS within\nu16 rtl9300_sds_regs[] = { 0x0194, 0x0194, 0x0194, 0x0194, 0x02a0, 0x02a0, 0x02a0, 0x02a0,\n\t\t\t   0x02A4, 0x02A4, 0x0198, 0x0198 };\nu8  rtl9300_sds_lsb[]  = { 0, 6, 12, 18, 0, 6, 12, 18, 0, 6, 0, 6};\n\n/*\n * Reset the SerDes by powering it off and set a new operations mode\n * of the SerDes. 0x1f is off. Other modes are\n * 0x02: SGMII\t\t0x04: 1000BX_FIBER\t0x05: FIBER100\n * 0x06: QSGMII\t\t0x09: RSGMII\t\t0x0d: USXGMII\n * 0x10: XSGMII\t\t0x12: HISGMII\t\t0x16: 2500Base_X\n * 0x17: RXAUI_LITE\t0x19: RXAUI_PLUS\t0x1a: 10G Base-R\n * 0x1b: 10GR1000BX_AUTO\t\t\t0x1f: OFF\n */\nvoid rtl9300_sds_rst(int sds_num, u32 mode)\n{\n\tpr_info(\"%s %d\\n\", __func__, mode);\n\tif (sds_num < 0 || sds_num > 11) {\n\t\tpr_err(\"Wrong SerDes number: %d\\n\", sds_num);\n\t\treturn;\n\t}\n\n\tsw_w32_mask(0x1f << rtl9300_sds_lsb[sds_num], 0x1f << rtl9300_sds_lsb[sds_num],\n\t\t    rtl9300_sds_regs[sds_num]);\n\tmdelay(10);\n\n\tsw_w32_mask(0x1f << rtl9300_sds_lsb[sds_num], mode << rtl9300_sds_lsb[sds_num],\n\t\t    rtl9300_sds_regs[sds_num]);\n\tmdelay(10);\n\n\tpr_debug(\"%s: 194:%08x 198:%08x 2a0:%08x 2a4:%08x\\n\", __func__,\n\t\tsw_r32(0x194), sw_r32(0x198), sw_r32(0x2a0), sw_r32(0x2a4));\n}\n\nvoid rtl9300_sds_set(int sds_num, u32 mode)\n{\n\tpr_info(\"%s %d\\n\", __func__, mode);\n\tif (sds_num < 0 || sds_num > 11) {\n\t\tpr_err(\"Wrong SerDes number: %d\\n\", sds_num);\n\t\treturn;\n\t}\n\n\tsw_w32_mask(0x1f << rtl9300_sds_lsb[sds_num], mode << rtl9300_sds_lsb[sds_num],\n\t\t    rtl9300_sds_regs[sds_num]);\n\tmdelay(10);\n\n\tpr_debug(\"%s: 194:%08x 198:%08x 2a0:%08x 2a4:%08x\\n\", __func__,\n\t\tsw_r32(0x194), sw_r32(0x198), sw_r32(0x2a0), sw_r32(0x2a4));\n}\n\nu32 rtl9300_sds_mode_get(int sds_num)\n{\n\tu32 v;\n\n\tif (sds_num < 0 || sds_num > 11) {\n\t\tpr_err(\"Wrong SerDes number: %d\\n\", sds_num);\n\t\treturn 0;\n\t}\n\n\tv = sw_r32(rtl9300_sds_regs[sds_num]);\n\tv >>= rtl9300_sds_lsb[sds_num];\n\n\treturn v & 0x1f;\n}\n\n/*\n * On the RTL839x family of SoCs with inbuilt SerDes, these SerDes are accessed through\n * a 2048 bit register that holds the contents of the PHY being simulated by the SoC.\n */\nint rtl839x_read_sds_phy(int phy_addr, int phy_reg)\n{\n\tint offset = 0;\n\tint reg;\n\tu32 val;\n\n\tif (phy_addr == 49)\n\t\toffset = 0x100;\n\n\t/*\n\t * For the RTL8393 internal SerDes, we simulate a PHY ID in registers 2/3\n\t * which would otherwise read as 0.\n\t */\n\tif (soc_info.id == 0x8393) {\n\t\tif (phy_reg == 2)\n\t\t\treturn 0x1c;\n\t\tif (phy_reg == 3)\n\t\t\treturn 0x8393;\n\t}\n\n\t/*\n\t * Register RTL839X_SDS12_13_XSG0 is 2048 bit broad, the MSB (bit 15) of the\n\t * 0th PHY register is bit 1023 (in byte 0x80). Because PHY-registers are 16\n\t * bit broad, we offset by reg << 1. In the SoC 2 registers are stored in\n\t * one 32 bit register.\n\t */\n\treg = (phy_reg << 1) & 0xfc;\n\tval = sw_r32(RTL839X_SDS12_13_XSG0 + offset + 0x80 + reg);\n\n\tif (phy_reg & 1)\n\t\tval = (val >> 16) & 0xffff;\n\telse\n\t\tval &= 0xffff;\n\treturn val;\n}\n\n/*\n * On the RTL930x family of SoCs, the internal SerDes are accessed through an IO\n * register which simulates commands to an internal MDIO bus.\n */\nint rtl930x_read_sds_phy(int phy_addr, int page, int phy_reg)\n{\n\tint i;\n\tu32 cmd = phy_addr << 2 | page << 7 | phy_reg << 13 | 1;\n\n\tsw_w32(cmd, RTL930X_SDS_INDACS_CMD);\n\n\tfor (i = 0; i < 100; i++) {\n\t\tif (!(sw_r32(RTL930X_SDS_INDACS_CMD) & 0x1))\n\t\t\tbreak;\n\t\tmdelay(1);\n\t}\n\n\tif (i >= 100)\n\t\treturn -EIO;\n\n\treturn sw_r32(RTL930X_SDS_INDACS_DATA) & 0xffff;\n}\n\nint rtl930x_write_sds_phy(int phy_addr, int page, int phy_reg, u16 v)\n{\n\tint i;\n\tu32 cmd;\n\n\tsw_w32(v, RTL930X_SDS_INDACS_DATA);\n\tcmd = phy_addr << 2 | page << 7 | phy_reg << 13 | 0x3;\n\n\tfor (i = 0; i < 100; i++) {\n\t\tif (!(sw_r32(RTL930X_SDS_INDACS_CMD) & 0x1))\n\t\t\tbreak;\n\t\tmdelay(1);\n\t}\n\n\n\tif (i >= 100) {\n\t\tpr_info(\"%s ERROR !!!!!!!!!!!!!!!!!!!!\\n\", __func__);\n\t\treturn -EIO;\n\t}\n\n\treturn 0;\n}\n\nint rtl931x_read_sds_phy(int phy_addr, int page, int phy_reg)\n{\n\tint i;\n\tu32 cmd = phy_addr << 2 | page << 7 | phy_reg << 13 | 1;\n\n\tpr_debug(\"%s: phy_addr(SDS-ID) %d, phy_reg: %d\\n\", __func__, phy_addr, phy_reg);\n\tsw_w32(cmd, RTL931X_SERDES_INDRT_ACCESS_CTRL);\n\n\tfor (i = 0; i < 100; i++) {\n\t\tif (!(sw_r32(RTL931X_SERDES_INDRT_ACCESS_CTRL) & 0x1))\n\t\t\tbreak;\n\t\tmdelay(1);\n\t}\n\n\tif (i >= 100)\n\t\treturn -EIO;\n\n\tpr_debug(\"%s: returning %04x\\n\", __func__, sw_r32(RTL931X_SERDES_INDRT_DATA_CTRL) & 0xffff);\n\treturn sw_r32(RTL931X_SERDES_INDRT_DATA_CTRL) & 0xffff;\n}\n\nint rtl931x_write_sds_phy(int phy_addr, int page, int phy_reg, u16 v)\n{\n\tint i;\n\tu32 cmd;\n\n\tcmd = phy_addr << 2 | page << 7 | phy_reg << 13;\n\tsw_w32(cmd, RTL931X_SERDES_INDRT_ACCESS_CTRL);\n\n\tsw_w32(v, RTL931X_SERDES_INDRT_DATA_CTRL);\n\t\t\n\tcmd =  sw_r32(RTL931X_SERDES_INDRT_ACCESS_CTRL) | 0x3;\n\tsw_w32(cmd, RTL931X_SERDES_INDRT_ACCESS_CTRL);\n\n\tfor (i = 0; i < 100; i++) {\n\t\tif (!(sw_r32(RTL931X_SERDES_INDRT_ACCESS_CTRL) & 0x1))\n\t\t\tbreak;\n\t\tmdelay(1);\n\t}\n\n\tif (i >= 100)\n\t\treturn -EIO;\n\n\treturn 0;\n}\n\n/*\n * On the RTL838x SoCs, the internal SerDes is accessed through direct access to\n * standard PHY registers, where a 32 bit register holds a 16 bit word as found\n * in a standard page 0 of a PHY\n */\nint rtl838x_read_sds_phy(int phy_addr, int phy_reg)\n{\n\tint offset = 0;\n\tu32 val;\n\n\tif (phy_addr == 26)\n\t\toffset = 0x100;\n\tval = sw_r32(RTL838X_SDS4_FIB_REG0 + offset + (phy_reg << 2)) & 0xffff;\n\n\treturn val;\n}\n\nint rtl839x_write_sds_phy(int phy_addr, int phy_reg, u16 v)\n{\n\tint offset = 0;\n\tint reg;\n\tu32 val;\n\n\tif (phy_addr == 49)\n\t\toffset = 0x100;\n\n\treg = (phy_reg << 1) & 0xfc;\n\tval = v;\n\tif (phy_reg & 1) {\n\t\tval = val << 16;\n\t\tsw_w32_mask(0xffff0000, val,\n\t\t\t    RTL839X_SDS12_13_XSG0 + offset + 0x80 + reg);\n\t} else {\n\t\tsw_w32_mask(0xffff, val,\n\t\t\t    RTL839X_SDS12_13_XSG0 + offset + 0x80 + reg);\n\t}\n\n\treturn 0;\n}\n\n/* Read the link and speed status of the 2 internal SGMII/1000Base-X\n * ports of the RTL838x SoCs\n */\nstatic int rtl8380_read_status(struct phy_device *phydev)\n{\n\tint err;\n\n\terr = genphy_read_status(phydev);\n\n\tif (phydev->link) {\n\t\tphydev->speed = SPEED_1000;\n\t\tphydev->duplex = DUPLEX_FULL;\n\t}\n\n\treturn err;\n}\n\n/* Read the link and speed status of the 2 internal SGMII/1000Base-X\n * ports of the RTL8393 SoC\n */\nstatic int rtl8393_read_status(struct phy_device *phydev)\n{\n\tint offset = 0;\n\tint err;\n\tint phy_addr = phydev->mdio.addr;\n\tu32 v;\n\n\terr = genphy_read_status(phydev);\n\tif (phy_addr == 49)\n\t\toffset = 0x100;\n\n\tif (phydev->link) {\n\t\tphydev->speed = SPEED_100;\n\t\t/* Read SPD_RD_00 (bit 13) and SPD_RD_01 (bit 6) out of the internal\n\t\t * PHY registers\n\t\t */\n\t\tv = sw_r32(RTL839X_SDS12_13_XSG0 + offset + 0x80);\n\t\tif (!(v & (1 << 13)) && (v & (1 << 6)))\n\t\t\tphydev->speed = SPEED_1000;\n\t\tphydev->duplex = DUPLEX_FULL;\n\t}\n\n\treturn err;\n}\n\nstatic int rtl8226_read_page(struct phy_device *phydev)\n{\n\treturn __phy_read(phydev, RTL8XXX_PAGE_SELECT);\n}\n\nstatic int rtl8226_write_page(struct phy_device *phydev, int page)\n{\n\treturn __phy_write(phydev, RTL8XXX_PAGE_SELECT, page);\n}\n\nstatic int rtl8226_read_status(struct phy_device *phydev)\n{\n\tint ret = 0, i;\n\tu32 val;\n\n// TODO: ret = genphy_read_status(phydev);\n// \tif (ret < 0) {\n// \t\tpr_info(\"%s: genphy_read_status failed\\n\", __func__);\n// \t\treturn ret;\n// \t}\n\n\t// Link status must be read twice\n\tfor (i = 0; i < 2; i++) {\n\t\tval = phy_read_mmd(phydev, MMD_VEND2, 0xA402);\n\t}\n\tphydev->link = val & BIT(2) ? 1 : 0;\n\tif (!phydev->link)\n\t\tgoto out;\n\n\t// Read duplex status\n\tval = phy_read_mmd(phydev, MMD_VEND2, 0xA434);\n\tif (val < 0)\n\t\tgoto out;\n\tphydev->duplex = !!(val & BIT(3));\n\n\t// Read speed\n\tval = phy_read_mmd(phydev, MMD_VEND2, 0xA434);\n\tswitch (val & 0x0630) {\n\tcase 0x0000:\n\t\tphydev->speed = SPEED_10;\n\t\tbreak;\n\tcase 0x0010:\n\t\tphydev->speed = SPEED_100;\n\t\tbreak;\n\tcase 0x0020:\n\t\tphydev->speed = SPEED_1000;\n\t\tbreak;\n\tcase 0x0200:\n\t\tphydev->speed = SPEED_10000;\n\t\tbreak;\n\tcase 0x0210:\n\t\tphydev->speed = SPEED_2500;\n\t\tbreak;\n\tcase 0x0220:\n\t\tphydev->speed = SPEED_5000;\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\nout:\n\treturn ret;\n}\n\nstatic int rtl8226_advertise_aneg(struct phy_device *phydev)\n{\n\tint ret = 0;\n\tu32 v;\n\n\tpr_info(\"In %s\\n\", __func__);\n\n\tv = phy_read_mmd(phydev, MMD_AN, 16);\n\tif (v < 0)\n\t\tgoto out;\n\n\tv |= BIT(5); // HD 10M\n\tv |= BIT(6); // FD 10M\n\tv |= BIT(7); // HD 100M\n\tv |= BIT(8); // FD 100M\n\n\tret = phy_write_mmd(phydev, MMD_AN, 16, v);\n\n\t// Allow 1GBit\n\tv = phy_read_mmd(phydev, MMD_VEND2, 0xA412);\n\tif (v < 0)\n\t\tgoto out;\n\tv |= BIT(9); // FD 1000M\n\n\tret = phy_write_mmd(phydev, MMD_VEND2, 0xA412, v);\n\tif (ret < 0)\n\t\tgoto out;\n\n\t// Allow 2.5G\n\tv = phy_read_mmd(phydev, MMD_AN, 32);\n\tif (v < 0)\n\t\tgoto out;\n\n\tv |= BIT(7);\n\tret = phy_write_mmd(phydev, MMD_AN, 32, v);\n\nout:\n\treturn ret;\n}\n\nstatic int rtl8226_config_aneg(struct phy_device *phydev)\n{\n\tint ret = 0;\n\tu32 v;\n\n\tpr_debug(\"In %s\\n\", __func__);\n\tif (phydev->autoneg == AUTONEG_ENABLE) {\n\t\tret = rtl8226_advertise_aneg(phydev);\n\t\tif (ret)\n\t\t\tgoto out;\n\t\t// AutoNegotiationEnable\n\t\tv = phy_read_mmd(phydev, MMD_AN, 0);\n\t\tif (v < 0)\n\t\t\tgoto out;\n\n\t\tv |= BIT(12); // Enable AN\n\t\tret = phy_write_mmd(phydev, MMD_AN, 0, v);\n\t\tif (ret < 0)\n\t\t\tgoto out;\n\n\t\t// RestartAutoNegotiation\n\t\tv = phy_read_mmd(phydev, MMD_VEND2, 0xA400);\n\t\tif (v < 0)\n\t\t\tgoto out;\n\t\tv |= BIT(9);\n\n\t\tret = phy_write_mmd(phydev, MMD_VEND2, 0xA400, v);\n\t}\n\n//\tTODO: ret = __genphy_config_aneg(phydev, ret);\n\nout:\n\treturn ret;\n}\n\nstatic int rtl8226_get_eee(struct phy_device *phydev,\n\t\t\t\t     struct ethtool_eee *e)\n{\n\tu32 val;\n\tint addr = phydev->mdio.addr;\n\n\tpr_debug(\"In %s, port %d, was enabled: %d\\n\", __func__, addr, e->eee_enabled);\n\n\tval = phy_read_mmd(phydev, MMD_AN, 60);\n\tif (e->eee_enabled) {\n\t\te->eee_enabled = !!(val & BIT(1));\n\t\tif (!e->eee_enabled) {\n\t\t\tval = phy_read_mmd(phydev, MMD_AN, 62);\n\t\t\te->eee_enabled = !!(val & BIT(0));\n\t\t}\n\t}\n\tpr_debug(\"%s: enabled: %d\\n\", __func__, e->eee_enabled);\n\n\treturn 0;\n}\n\nstatic int rtl8226_set_eee(struct phy_device *phydev, struct ethtool_eee *e)\n{\n\tint port = phydev->mdio.addr;\n\tu64 poll_state;\n\tbool an_enabled;\n\tu32 val;\n\n\tpr_info(\"In %s, port %d, enabled %d\\n\", __func__, port, e->eee_enabled);\n\n\tpoll_state = disable_polling(port);\n\n\t// Remember aneg state\n\tval = phy_read_mmd(phydev, MMD_AN, 0);\n\tan_enabled = !!(val & BIT(12));\n\n\t// Setup 100/1000MBit\n\tval = phy_read_mmd(phydev, MMD_AN, 60);\n\tif (e->eee_enabled)\n\t\tval |= 0x6;\n\telse\n\t\tval &= 0x6;\n\tphy_write_mmd(phydev, MMD_AN, 60, val);\n\n\t// Setup 2.5GBit\n\tval = phy_read_mmd(phydev, MMD_AN, 62);\n\tif (e->eee_enabled)\n\t\tval |= 0x1;\n\telse\n\t\tval &= 0x1;\n\tphy_write_mmd(phydev, MMD_AN, 62, val);\n\n\t// RestartAutoNegotiation\n\tval = phy_read_mmd(phydev, MMD_VEND2, 0xA400);\n\tval |= BIT(9);\n\tphy_write_mmd(phydev, MMD_VEND2, 0xA400, val);\n\n\tresume_polling(poll_state);\n\n\treturn 0;\n}\n\nstatic struct fw_header *rtl838x_request_fw(struct phy_device *phydev,\n\t\t\t\t\t    const struct firmware *fw,\n\t\t\t\t\t    const char *name)\n{\n\tstruct device *dev = &phydev->mdio.dev;\n\tint err;\n\tstruct fw_header *h;\n\tuint32_t checksum, my_checksum;\n\n\terr = request_firmware(&fw, name, dev);\n\tif (err < 0)\n\t\tgoto out;\n\n\tif (fw->size < sizeof(struct fw_header)) {\n\t\tpr_err(\"Firmware size too small.\\n\");\n\t\terr = -EINVAL;\n\t\tgoto out;\n\t}\n\n\th = (struct fw_header *) fw->data;\n\tpr_info(\"Firmware loaded. Size %d, magic: %08x\\n\", fw->size, h->magic);\n\n\tif (h->magic != 0x83808380) {\n\t\tpr_err(\"Wrong firmware file: MAGIC mismatch.\\n\");\n\t\tgoto out;\n\t}\n\n\tchecksum = h->checksum;\n\th->checksum = 0;\n\tmy_checksum = ~crc32(0xFFFFFFFFU, fw->data, fw->size);\n\tif (checksum != my_checksum) {\n\t\tpr_err(\"Firmware checksum mismatch.\\n\");\n\t\terr = -EINVAL;\n\t\tgoto out;\n\t}\n\th->checksum = checksum;\n\n\treturn h;\nout:\n\tdev_err(dev, \"Unable to load firmware %s (%d)\\n\", name, err);\n\treturn NULL;\n}\n\nstatic void rtl821x_phy_setup_package_broadcast(struct phy_device *phydev, bool enable)\n{\n\tint mac = phydev->mdio.addr;\n\n\t/* select main page 0 */\n\tphy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL8XXX_PAGE_MAIN);\n\t/* write to 0x8 to register 0x1d on main page 0 */\n\tphy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_INTERNAL);\n\t/* select page 0x266 */\n\tphy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL821X_PAGE_PORT);\n\t/* set phy id and target broadcast bitmap in register 0x16 on page 0x266 */\n\tphy_write_paged(phydev, RTL83XX_PAGE_RAW, 0x16, (enable?0xff00:0x00) | mac);\n\t/* return to main page 0 */\n\tphy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL8XXX_PAGE_MAIN);\n\t/* write to 0x0 to register 0x1d on main page 0 */\n\tphy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);\n\tmdelay(1);\n}\n\nstatic int rtl8390_configure_generic(struct phy_device *phydev)\n{\n\tint mac = phydev->mdio.addr;\n\tu32 val, phy_id;\n\n\tval = phy_read(phydev, 2);\n\tphy_id = val << 16;\n\tval = phy_read(phydev, 3);\n\tphy_id |= val;\n\tpr_debug(\"Phy on MAC %d: %x\\n\", mac, phy_id);\n\n\t/* Read internal PHY ID */\n\tphy_write_paged(phydev, 31, 27, 0x0002);\n\tval = phy_read_paged(phydev, 31, 28);\n\n\t/* Internal RTL8218B, version 2 */\n\tphydev_info(phydev, \"Detected unknown %x\\n\", val);\n\treturn 0;\n}\n\nstatic int rtl8380_configure_int_rtl8218b(struct phy_device *phydev)\n{\n\tu32 val, phy_id;\n\tint i, p, ipd_flag;\n\tint mac = phydev->mdio.addr;\n\tstruct fw_header *h;\n\tu32 *rtl838x_6275B_intPhy_perport;\n\tu32 *rtl8218b_6276B_hwEsd_perport;\n\n\tval = phy_read(phydev, 2);\n\tphy_id = val << 16;\n\tval = phy_read(phydev, 3);\n\tphy_id |= val;\n\tpr_debug(\"Phy on MAC %d: %x\\n\", mac, phy_id);\n\n\t/* Read internal PHY ID */\n\tphy_write_paged(phydev, 31, 27, 0x0002);\n\tval = phy_read_paged(phydev, 31, 28);\n\tif (val != 0x6275) {\n\t\tphydev_err(phydev, \"Expected internal RTL8218B, found PHY-ID %x\\n\", val);\n\t\treturn -1;\n\t}\n\n\t/* Internal RTL8218B, version 2 */\n\tphydev_info(phydev, \"Detected internal RTL8218B\\n\");\n\n\th = rtl838x_request_fw(phydev, &rtl838x_8380_fw, FIRMWARE_838X_8380_1);\n\tif (!h)\n\t\treturn -1;\n\n\tif (h->phy != 0x83800000) {\n\t\tphydev_err(phydev, \"Wrong firmware file: PHY mismatch.\\n\");\n\t\treturn -1;\n\t}\n\n\trtl838x_6275B_intPhy_perport = (void *)h + sizeof(struct fw_header)\n\t\t\t+ h->parts[8].start;\n\n\trtl8218b_6276B_hwEsd_perport = (void *)h + sizeof(struct fw_header)\n\t\t\t+ h->parts[9].start;\n\n\tif (sw_r32(RTL838X_DMY_REG31) == 0x1)\n\t\tipd_flag = 1;\n\n\tval = phy_read(phydev, 0);\n\tif (val & BIT(11))\n\t\trtl8380_int_phy_on_off(phydev, true);\n\telse\n\t\trtl8380_phy_reset(phydev);\n\tmsleep(100);\n\n\t/* Ready PHY for patch */\n\tfor (p = 0; p < 8; p++) {\n\t\tphy_package_port_write_paged(phydev, p, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL821X_PAGE_PATCH);\n\t\tphy_package_port_write_paged(phydev, p, RTL83XX_PAGE_RAW, 0x10, 0x0010);\n\t}\n\tmsleep(500);\n\tfor (p = 0; p < 8; p++) {\n\t\tfor (i = 0; i < 100 ; i++) {\n\t\t\tval = phy_package_port_read_paged(phydev, p, RTL821X_PAGE_STATE, 0x10);\n\t\t\tif (val & 0x40)\n\t\t\t\tbreak;\n\t\t}\n\t\tif (i >= 100) {\n\t\t\tphydev_err(phydev,\n\t\t\t\t   \"ERROR: Port %d not ready for patch.\\n\",\n\t\t\t\t   mac + p);\n\t\t\treturn -1;\n\t\t}\n\t}\n\tfor (p = 0; p < 8; p++) {\n\t\ti = 0;\n\t\twhile (rtl838x_6275B_intPhy_perport[i * 2]) {\n\t\t\tphy_package_port_write_paged(phydev, p, RTL83XX_PAGE_RAW,\n\t\t\t\trtl838x_6275B_intPhy_perport[i * 2],\n\t\t\t\trtl838x_6275B_intPhy_perport[i * 2 + 1]);\n\t\t\ti++;\n\t\t}\n\t\ti = 0;\n\t\twhile (rtl8218b_6276B_hwEsd_perport[i * 2]) {\n\t\t\tphy_package_port_write_paged(phydev, p, RTL83XX_PAGE_RAW,\n\t\t\t\trtl8218b_6276B_hwEsd_perport[i * 2],\n\t\t\t\trtl8218b_6276B_hwEsd_perport[i * 2 + 1]);\n\t\t\ti++;\n\t\t}\n\t}\n\treturn 0;\n}\n\nstatic int rtl8380_configure_ext_rtl8218b(struct phy_device *phydev)\n{\n\tu32 val, ipd, phy_id;\n\tint i, l;\n\tint mac = phydev->mdio.addr;\n\tstruct fw_header *h;\n\tu32 *rtl8380_rtl8218b_perchip;\n\tu32 *rtl8218B_6276B_rtl8380_perport;\n\tu32 *rtl8380_rtl8218b_perport;\n\n\tif (soc_info.family == RTL8380_FAMILY_ID && mac != 0 && mac != 16) {\n\t\tphydev_err(phydev, \"External RTL8218B must have PHY-IDs 0 or 16!\\n\");\n\t\treturn -1;\n\t}\n\tval = phy_read(phydev, 2);\n\tphy_id = val << 16;\n\tval = phy_read(phydev, 3);\n\tphy_id |= val;\n\tpr_info(\"Phy on MAC %d: %x\\n\", mac, phy_id);\n\n\t/* Read internal PHY ID */\n\tphy_write_paged(phydev, 31, 27, 0x0002);\n\tval = phy_read_paged(phydev, 31, 28);\n\tif (val != 0x6276) {\n\t\tphydev_err(phydev, \"Expected external RTL8218B, found PHY-ID %x\\n\", val);\n\t\treturn -1;\n\t}\n\tphydev_info(phydev, \"Detected external RTL8218B\\n\");\n\n\th = rtl838x_request_fw(phydev, &rtl838x_8218b_fw, FIRMWARE_838X_8218b_1);\n\tif (!h)\n\t\treturn -1;\n\n\tif (h->phy != 0x8218b000) {\n\t\tphydev_err(phydev, \"Wrong firmware file: PHY mismatch.\\n\");\n\t\treturn -1;\n\t}\n\n\trtl8380_rtl8218b_perchip = (void *)h + sizeof(struct fw_header)\n\t\t\t+ h->parts[0].start;\n\n\trtl8218B_6276B_rtl8380_perport = (void *)h + sizeof(struct fw_header)\n\t\t\t+ h->parts[1].start;\n\n\trtl8380_rtl8218b_perport = (void *)h + sizeof(struct fw_header)\n\t\t\t+ h->parts[2].start;\n\n\tval = phy_read(phydev, 0);\n\tif (val & (1 << 11))\n\t\trtl8380_int_phy_on_off(phydev, true);\n\telse\n\t\trtl8380_phy_reset(phydev);\n\n\tmsleep(100);\n\n\t/* Get Chip revision */\n\tphy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL8XXX_PAGE_MAIN);\n\tphy_write_paged(phydev, RTL83XX_PAGE_RAW, 0x1b, 0x4);\n\tval = phy_read_paged(phydev, RTL83XX_PAGE_RAW, 0x1c);\n\n\tphydev_info(phydev, \"Detected chip revision %04x\\n\", val);\n\n\ti = 0;\n\twhile (rtl8380_rtl8218b_perchip[i * 3]\n\t\t&& rtl8380_rtl8218b_perchip[i * 3 + 1]) {\n\t\t\tphy_package_port_write_paged(phydev, rtl8380_rtl8218b_perchip[i * 3],\n\t\t\t\t\t  RTL83XX_PAGE_RAW, rtl8380_rtl8218b_perchip[i * 3 + 1],\n\t\t\t\t\t  rtl8380_rtl8218b_perchip[i * 3 + 2]);\n\t\ti++;\n\t}\n\n\t/* Enable PHY */\n\tfor (i = 0; i < 8; i++) {\n\t\tphy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL8XXX_PAGE_MAIN);\n\t\tphy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, 0x00, 0x1140);\n\t}\n\tmdelay(100);\n\n\t/* Request patch */\n\tfor (i = 0; i < 8; i++) {\n\t\tphy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL821X_PAGE_PATCH);\n\t\tphy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, 0x10, 0x0010);\n\t}\n\n\tmdelay(300);\n\n\t/* Verify patch readiness */\n\tfor (i = 0; i < 8; i++) {\n\t\tfor (l = 0; l < 100; l++) {\n\t\t\tval = phy_package_port_read_paged(phydev, i, RTL821X_PAGE_STATE, 0x10);\n\t\t\tif (val & 0x40)\n\t\t\t\tbreak;\n\t\t}\n\t\tif (l >= 100) {\n\t\t\tphydev_err(phydev, \"Could not patch PHY\\n\");\n\t\t\treturn -1;\n\t\t}\n\t}\n\n\t/* Use Broadcast ID method for patching */\n\trtl821x_phy_setup_package_broadcast(phydev, true);\n\n\tphy_write_paged(phydev, RTL83XX_PAGE_RAW, 30, 8);\n\tphy_write_paged(phydev, 0x26e, 17, 0xb);\n\tphy_write_paged(phydev, 0x26e, 16, 0x2);\n\tmdelay(1);\n\tipd = phy_read_paged(phydev, 0x26e, 19);\n\tphy_write_paged(phydev, 0, 30, 0);\n\tipd = (ipd >> 4) & 0xf; /* unused ? */\n\n\ti = 0;\n\twhile (rtl8218B_6276B_rtl8380_perport[i * 2]) {\n\t\tphy_write_paged(phydev, RTL83XX_PAGE_RAW, rtl8218B_6276B_rtl8380_perport[i * 2],\n\t\t\t\t  rtl8218B_6276B_rtl8380_perport[i * 2 + 1]);\n\t\ti++;\n\t}\n\n\t/*Disable broadcast ID*/\n\trtl821x_phy_setup_package_broadcast(phydev, false);\n\n\treturn 0;\n}\n\nstatic int rtl8218b_ext_match_phy_device(struct phy_device *phydev)\n{\n\tint addr = phydev->mdio.addr;\n\n\t/* Both the RTL8214FC and the external RTL8218B have the same\n\t * PHY ID. On the RTL838x, the RTL8218B can only be attached_dev\n\t * at PHY IDs 0-7, while the RTL8214FC must be attached via\n\t * the pair of SGMII/1000Base-X with higher PHY-IDs\n\t */\n\tif (soc_info.family == RTL8380_FAMILY_ID)\n\t\treturn phydev->phy_id == PHY_ID_RTL8218B_E && addr < 8;\n\telse\n\t\treturn phydev->phy_id == PHY_ID_RTL8218B_E;\n}\n\nstatic void rtl8380_rtl8214fc_media_set(struct phy_device *phydev, bool set_fibre)\n{\n\tint mac = phydev->mdio.addr;\n\n\tstatic int reg[] = {16, 19, 20, 21};\n\tint val, media, power;\n\n\tpr_info(\"%s: port %d, set_fibre: %d\\n\", __func__, mac, set_fibre);\n\tphy_package_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_INTERNAL);\n\tval = phy_package_read_paged(phydev, RTL821X_PAGE_PORT, reg[mac % 4]);\n\n\tmedia = (val >> 10) & 0x3;\n\tpr_info(\"Current media %x\\n\", media);\n\tif (media & 0x2) {\n\t\tpr_info(\"Powering off COPPER\\n\");\n\t\tphy_package_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);\n\t\t/* Ensure power is off */\n\t\tpower = phy_package_read_paged(phydev, RTL821X_PAGE_POWER, 0x10);\n\t\tif (!(power & (1 << 11)))\n\t\t\tphy_package_write_paged(phydev, RTL821X_PAGE_POWER, 0x10, power | (1 << 11));\n\t} else {\n\t\tpr_info(\"Powering off FIBRE\");\n\t\tphy_package_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_FIBRE);\n\t\t/* Ensure power is off */\n\t\tpower = phy_package_read_paged(phydev, RTL821X_PAGE_POWER, 0x10);\n\t\tif (!(power & (1 << 11)))\n\t\t\tphy_package_write_paged(phydev, RTL821X_PAGE_POWER, 0x10, power | (1 << 11));\n\t}\n\n\tif (set_fibre) {\n\t\tval |= 1 << 10;\n\t\tval &= ~(1 << 11);\n\t} else {\n\t\tval |= 1 << 10;\n\t\tval |= 1 << 11;\n\t}\n\tphy_package_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_INTERNAL);\n\tphy_package_write_paged(phydev, RTL821X_PAGE_PORT, reg[mac % 4], val);\n\tphy_package_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);\n\n\tif (set_fibre) {\n\t\tpr_info(\"Powering on FIBRE\");\n\t\tphy_package_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_FIBRE);\n\t\t/* Ensure power is off */\n\t\tpower = phy_package_read_paged(phydev, RTL821X_PAGE_POWER, 0x10);\n\t\tif (power & (1 << 11))\n\t\t\tphy_package_write_paged(phydev, RTL821X_PAGE_POWER, 0x10, power & ~(1 << 11));\n\t} else {\n\t\tpr_info(\"Powering on COPPER\\n\");\n\t\tphy_package_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);\n\t\t/* Ensure power is off */\n\t\tpower = phy_package_read_paged(phydev, RTL821X_PAGE_POWER, 0x10);\n\t\tif (power & (1 << 11))\n\t\t\tphy_package_write_paged(phydev, RTL821X_PAGE_POWER, 0x10, power & ~(1 << 11));\n\t}\n\n\tphy_package_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);\n}\n\nstatic bool rtl8380_rtl8214fc_media_is_fibre(struct phy_device *phydev)\n{\n\tint mac = phydev->mdio.addr;\n\n\tstatic int reg[] = {16, 19, 20, 21};\n\tu32 val;\n\n\tphy_package_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_INTERNAL);\n\tval = phy_package_read_paged(phydev, RTL821X_PAGE_PORT, reg[mac % 4]);\n\tphy_package_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);\n\tif (val & (1 << 11))\n\t\treturn false;\n\treturn true;\n}\n\nstatic int rtl8214fc_set_port(struct phy_device *phydev, int port)\n{\n\tbool is_fibre = (port == PORT_FIBRE ? true : false);\n\tint addr = phydev->mdio.addr;\n\n\tpr_debug(\"%s port %d to %d\\n\", __func__, addr, port);\n\n\trtl8380_rtl8214fc_media_set(phydev, is_fibre);\n\treturn 0;\n}\n\nstatic int rtl8214fc_get_port(struct phy_device *phydev)\n{\n\tint addr = phydev->mdio.addr;\n\n\tpr_debug(\"%s: port %d\\n\", __func__, addr);\n\tif (rtl8380_rtl8214fc_media_is_fibre(phydev))\n\t\treturn PORT_FIBRE;\n\treturn PORT_MII;\n}\n\n/*\n * Enable EEE on the RTL8218B PHYs\n * The method used is not the preferred way (which would be based on the MAC-EEE state,\n * but the only way that works since the kernel first enables EEE in the MAC\n * and then sets up the PHY. The MAC-based approach would require the oppsite.\n */\nvoid rtl8218d_eee_set(struct phy_device *phydev, bool enable)\n{\n\tu32 val;\n\tbool an_enabled;\n\n\tpr_debug(\"In %s %d, enable %d\\n\", __func__, phydev->mdio.addr, enable);\n\t/* Set GPHY page to copper */\n\tphy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);\n\n\tval = phy_read(phydev, 0);\n\tan_enabled = val & BIT(12);\n\n\t/* Enable 100M (bit 1) / 1000M (bit 2) EEE */\n\tval = phy_read_mmd(phydev, 7, 60);\n\tval |= BIT(2) | BIT(1);\n\tphy_write_mmd(phydev, 7, 60, enable ? 0x6 : 0);\n\n\t/* 500M EEE ability */\n\tval = phy_read_paged(phydev, RTL821X_PAGE_GPHY, 20);\n\tif (enable)\n\t\tval |= BIT(7);\n\telse\n\t\tval &= ~BIT(7);\n\tphy_write_paged(phydev, RTL821X_PAGE_GPHY, 20, val);\n\n\t/* Restart AN if enabled */\n\tif (an_enabled) {\n\t\tval = phy_read(phydev, 0);\n\t\tval |= BIT(9);\n\t\tphy_write(phydev, 0, val);\n\t}\n\n\t/* GPHY page back to auto*/\n\tphy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);\n}\n\nstatic int rtl8218b_get_eee(struct phy_device *phydev,\n\t\t\t\t     struct ethtool_eee *e)\n{\n\tu32 val;\n\tint addr = phydev->mdio.addr;\n\n\tpr_debug(\"In %s, port %d, was enabled: %d\\n\", __func__, addr, e->eee_enabled);\n\n\t/* Set GPHY page to copper */\n\tphy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);\n\n\tval = phy_read_paged(phydev, 7, 60);\n\tif (e->eee_enabled) {\n\t\t// Verify vs MAC-based EEE\n\t\te->eee_enabled = !!(val & BIT(7));\n\t\tif (!e->eee_enabled) {\n\t\t\tval = phy_read_paged(phydev, RTL821X_PAGE_MAC, 25);\n\t\t\te->eee_enabled = !!(val & BIT(4));\n\t\t}\n\t}\n\tpr_debug(\"%s: enabled: %d\\n\", __func__, e->eee_enabled);\n\n\t/* GPHY page to auto */\n\tphy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);\n\n\treturn 0;\n}\n\nstatic int rtl8218d_get_eee(struct phy_device *phydev,\n\t\t\t\t     struct ethtool_eee *e)\n{\n\tu32 val;\n\tint addr = phydev->mdio.addr;\n\n\tpr_debug(\"In %s, port %d, was enabled: %d\\n\", __func__, addr, e->eee_enabled);\n\n\t/* Set GPHY page to copper */\n\tphy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);\n\n\tval = phy_read_paged(phydev, 7, 60);\n\tif (e->eee_enabled)\n\t\te->eee_enabled = !!(val & BIT(7));\n\tpr_debug(\"%s: enabled: %d\\n\", __func__, e->eee_enabled);\n\n\t/* GPHY page to auto */\n\tphy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);\n\n\treturn 0;\n}\n\nstatic int rtl8214fc_set_eee(struct phy_device *phydev,\n\t\t\t\t     struct ethtool_eee *e)\n{\n\tu32 poll_state;\n\tint port = phydev->mdio.addr;\n\tbool an_enabled;\n\tu32 val;\n\n\tpr_debug(\"In %s port %d, enabled %d\\n\", __func__, port, e->eee_enabled);\n\n\tif (rtl8380_rtl8214fc_media_is_fibre(phydev)) {\n\t\tnetdev_err(phydev->attached_dev, \"Port %d configured for FIBRE\", port);\n\t\treturn -ENOTSUPP;\n\t}\n\n\tpoll_state = disable_polling(port);\n\n\t/* Set GPHY page to copper */\n\tphy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);\n\n\t// Get auto-negotiation status\n\tval = phy_read(phydev, 0);\n\tan_enabled = val & BIT(12);\n\n\tpr_info(\"%s: aneg: %d\\n\", __func__, an_enabled);\n\tval = phy_read_paged(phydev, RTL821X_PAGE_MAC, 25);\n\tval &= ~BIT(5);  // Use MAC-based EEE\n\tphy_write_paged(phydev, RTL821X_PAGE_MAC, 25, val);\n\n\t/* Enable 100M (bit 1) / 1000M (bit 2) EEE */\n\tphy_write_paged(phydev, 7, 60, e->eee_enabled ? 0x6 : 0);\n\n\t/* 500M EEE ability */\n\tval = phy_read_paged(phydev, RTL821X_PAGE_GPHY, 20);\n\tif (e->eee_enabled)\n\t\tval |= BIT(7);\n\telse\n\t\tval &= ~BIT(7);\n\n\tphy_write_paged(phydev, RTL821X_PAGE_GPHY, 20, val);\n\n\t/* Restart AN if enabled */\n\tif (an_enabled) {\n\t\tpr_info(\"%s: doing aneg\\n\", __func__);\n\t\tval = phy_read(phydev, 0);\n\t\tval |= BIT(9);\n\t\tphy_write(phydev, 0, val);\n\t}\n\n\t/* GPHY page back to auto*/\n\tphy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);\n\n\tresume_polling(poll_state);\n\n\treturn 0;\n}\n\nstatic int rtl8214fc_get_eee(struct phy_device *phydev,\n\t\t\t\t      struct ethtool_eee *e)\n{\n\tint addr = phydev->mdio.addr;\n\n\tpr_debug(\"In %s port %d, enabled %d\\n\", __func__, addr, e->eee_enabled);\n\tif (rtl8380_rtl8214fc_media_is_fibre(phydev)) {\n\t\tnetdev_err(phydev->attached_dev, \"Port %d configured for FIBRE\", addr);\n\t\treturn -ENOTSUPP;\n\t}\n\n\treturn rtl8218b_get_eee(phydev, e);\n}\n\nstatic int rtl8218b_set_eee(struct phy_device *phydev, struct ethtool_eee *e)\n{\n\tint port = phydev->mdio.addr;\n\tu64 poll_state;\n\tu32 val;\n\tbool an_enabled;\n\n\tpr_info(\"In %s, port %d, enabled %d\\n\", __func__, port, e->eee_enabled);\n\n\tpoll_state = disable_polling(port);\n\n\t/* Set GPHY page to copper */\n\tphy_write(phydev, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);\n\tval = phy_read(phydev, 0);\n\tan_enabled = val & BIT(12);\n\n\tif (e->eee_enabled) {\n\t\t/* 100/1000M EEE Capability */\n\t\tphy_write(phydev, 13, 0x0007);\n\t\tphy_write(phydev, 14, 0x003C);\n\t\tphy_write(phydev, 13, 0x4007);\n\t\tphy_write(phydev, 14, 0x0006);\n\n\t\tval = phy_read_paged(phydev, RTL821X_PAGE_MAC, 25);\n\t\tval |= BIT(4);\n\t\tphy_write_paged(phydev, RTL821X_PAGE_MAC, 25, val);\n\t} else {\n\t\t/* 100/1000M EEE Capability */\n\t\tphy_write(phydev, 13, 0x0007);\n\t\tphy_write(phydev, 14, 0x003C);\n\t\tphy_write(phydev, 13, 0x0007);\n\t\tphy_write(phydev, 14, 0x0000);\n\n\t\tval = phy_read_paged(phydev, RTL821X_PAGE_MAC, 25);\n\t\tval &= ~BIT(4);\n\t\tphy_write_paged(phydev, RTL821X_PAGE_MAC, 25, val);\n\t}\n\n\t/* Restart AN if enabled */\n\tif (an_enabled) {\n\t\tval = phy_read(phydev, 0);\n\t\tval |= BIT(9);\n\t\tphy_write(phydev, 0, val);\n\t}\n\n\t/* GPHY page back to auto*/\n\tphy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);\n\n\tpr_info(\"%s done\\n\", __func__);\n\tresume_polling(poll_state);\n\n\treturn 0;\n}\n\nstatic int rtl8218d_set_eee(struct phy_device *phydev, struct ethtool_eee *e)\n{\n\tint addr = phydev->mdio.addr;\n\tu64 poll_state;\n\n\tpr_info(\"In %s, port %d, enabled %d\\n\", __func__, addr, e->eee_enabled);\n\n\tpoll_state = disable_polling(addr);\n\n\trtl8218d_eee_set(phydev, (bool) e->eee_enabled);\n\n\tresume_polling(poll_state);\n\n\treturn 0;\n}\n\nstatic int rtl8214c_match_phy_device(struct phy_device *phydev)\n{\n\treturn phydev->phy_id == PHY_ID_RTL8214C;\n}\n\nstatic int rtl8380_configure_rtl8214c(struct phy_device *phydev)\n{\n\tu32 phy_id, val;\n\tint mac = phydev->mdio.addr;\n\n\tval = phy_read(phydev, 2);\n\tphy_id = val << 16;\n\tval = phy_read(phydev, 3);\n\tphy_id |= val;\n\tpr_debug(\"Phy on MAC %d: %x\\n\", mac, phy_id);\n\n\tphydev_info(phydev, \"Detected external RTL8214C\\n\");\n\n\t/* GPHY auto conf */\n\tphy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);\n\treturn 0;\n}\n\nstatic int rtl8380_configure_rtl8214fc(struct phy_device *phydev)\n{\n\tu32 phy_id, val, page = 0;\n\tint i, l;\n\tint mac = phydev->mdio.addr;\n\tstruct fw_header *h;\n\tu32 *rtl8380_rtl8214fc_perchip;\n\tu32 *rtl8380_rtl8214fc_perport;\n\n\tval = phy_read(phydev, 2);\n\tphy_id = val << 16;\n\tval = phy_read(phydev, 3);\n\tphy_id |= val;\n\tpr_debug(\"Phy on MAC %d: %x\\n\", mac, phy_id);\n\n\t/* Read internal PHY id */\n\tphy_write_paged(phydev, 0, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);\n\tphy_write_paged(phydev, 0x1f, 0x1b, 0x0002);\n\tval = phy_read_paged(phydev, 0x1f, 0x1c);\n\tif (val != 0x6276) {\n\t\tphydev_err(phydev, \"Expected external RTL8214FC, found PHY-ID %x\\n\", val);\n\t\treturn -1;\n\t}\n\tphydev_info(phydev, \"Detected external RTL8214FC\\n\");\n\n\th = rtl838x_request_fw(phydev, &rtl838x_8214fc_fw, FIRMWARE_838X_8214FC_1);\n\tif (!h)\n\t\treturn -1;\n\n\tif (h->phy != 0x8214fc00) {\n\t\tphydev_err(phydev, \"Wrong firmware file: PHY mismatch.\\n\");\n\t\treturn -1;\n\t}\n\n\trtl8380_rtl8214fc_perchip = (void *)h + sizeof(struct fw_header)\n\t\t   + h->parts[0].start;\n\n\trtl8380_rtl8214fc_perport = (void *)h + sizeof(struct fw_header)\n\t\t   + h->parts[1].start;\n\n\t/* detect phy version */\n\tphy_write_paged(phydev, RTL83XX_PAGE_RAW, 27, 0x0004);\n\tval = phy_read_paged(phydev, RTL83XX_PAGE_RAW, 28);\n\n\tval = phy_read(phydev, 16);\n\tif (val & (1 << 11))\n\t\trtl8380_rtl8214fc_on_off(phydev, true);\n\telse\n\t\trtl8380_phy_reset(phydev);\n\n\tmsleep(100);\n\tphy_write_paged(phydev, 0, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);\n\n\ti = 0;\n\twhile (rtl8380_rtl8214fc_perchip[i * 3]\n\t       && rtl8380_rtl8214fc_perchip[i * 3 + 1]) {\n\t\tif (rtl8380_rtl8214fc_perchip[i * 3 + 1] == 0x1f)\n\t\t\tpage = rtl8380_rtl8214fc_perchip[i * 3 + 2];\n\t\tif (rtl8380_rtl8214fc_perchip[i * 3 + 1] == 0x13 && page == 0x260) {\n\t\t\tval = phy_read_paged(phydev, 0x260, 13);\n\t\t\tval = (val & 0x1f00) | (rtl8380_rtl8214fc_perchip[i * 3 + 2]\n\t\t\t\t& 0xe0ff);\n\t\t\tphy_write_paged(phydev, RTL83XX_PAGE_RAW,\n\t\t\t\t\trtl8380_rtl8214fc_perchip[i * 3 + 1], val);\n\t\t} else {\n\t\t\tphy_write_paged(phydev, RTL83XX_PAGE_RAW,\n\t\t\t\t\trtl8380_rtl8214fc_perchip[i * 3 + 1],\n\t\t\t\t\trtl8380_rtl8214fc_perchip[i * 3 + 2]);\n\t\t}\n\t\ti++;\n\t}\n\n\t/* Force copper medium */\n\tfor (i = 0; i < 4; i++) {\n\t\tphy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL8XXX_PAGE_MAIN);\n\t\tphy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);\n\t}\n\n\t/* Enable PHY */\n\tfor (i = 0; i < 4; i++) {\n\t\tphy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL8XXX_PAGE_MAIN);\n\t\tphy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, 0x00, 0x1140);\n\t}\n\tmdelay(100);\n\n\t/* Disable Autosensing */\n\tfor (i = 0; i < 4; i++) {\n\t\tfor (l = 0; l < 100; l++) {\n\t\t\tval = phy_package_port_read_paged(phydev, i, RTL821X_PAGE_GPHY, 0x10);\n\t\t\tif ((val & 0x7) >= 3)\n\t\t\t\tbreak;\n\t\t}\n\t\tif (l >= 100) {\n\t\t\tphydev_err(phydev, \"Could not disable autosensing\\n\");\n\t\t\treturn -1;\n\t\t}\n\t}\n\n\t/* Request patch */\n\tfor (i = 0; i < 4; i++) {\n\t\tphy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL821X_PAGE_PATCH);\n\t\tphy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, 0x10, 0x0010);\n\t}\n\tmdelay(300);\n\n\t/* Verify patch readiness */\n\tfor (i = 0; i < 4; i++) {\n\t\tfor (l = 0; l < 100; l++) {\n\t\t\tval = phy_package_port_read_paged(phydev, i, RTL821X_PAGE_STATE, 0x10);\n\t\t\tif (val & 0x40)\n\t\t\t\tbreak;\n\t\t}\n\t\tif (l >= 100) {\n\t\t\tphydev_err(phydev, \"Could not patch PHY\\n\");\n\t\t\treturn -1;\n\t\t}\n\t}\n\t/* Use Broadcast ID method for patching */\n\trtl821x_phy_setup_package_broadcast(phydev, true);\n\n\ti = 0;\n\twhile (rtl8380_rtl8214fc_perport[i * 2]) {\n\t\tphy_write_paged(phydev, RTL83XX_PAGE_RAW, rtl8380_rtl8214fc_perport[i * 2],\n\t\t\t\t  rtl8380_rtl8214fc_perport[i * 2 + 1]);\n\t\ti++;\n\t}\n\n\t/*Disable broadcast ID*/\n\trtl821x_phy_setup_package_broadcast(phydev, false);\n\n\t/* Auto medium selection */\n\tfor (i = 0; i < 4; i++) {\n\t\tphy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL8XXX_PAGE_MAIN);\n\t\tphy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);\n\t}\n\n\treturn 0;\n}\n\nstatic int rtl8214fc_match_phy_device(struct phy_device *phydev)\n{\n\tint addr = phydev->mdio.addr;\n\n\treturn phydev->phy_id == PHY_ID_RTL8214FC && addr >= 24;\n}\n\nstatic int rtl8380_configure_serdes(struct phy_device *phydev)\n{\n\tu32 v;\n\tu32 sds_conf_value;\n\tint i;\n\tstruct fw_header *h;\n\tu32 *rtl8380_sds_take_reset;\n\tu32 *rtl8380_sds_common;\n\tu32 *rtl8380_sds01_qsgmii_6275b;\n\tu32 *rtl8380_sds23_qsgmii_6275b;\n\tu32 *rtl8380_sds4_fiber_6275b;\n\tu32 *rtl8380_sds5_fiber_6275b;\n\tu32 *rtl8380_sds_reset;\n\tu32 *rtl8380_sds_release_reset;\n\n\tphydev_info(phydev, \"Detected internal RTL8380 SERDES\\n\");\n\n\th = rtl838x_request_fw(phydev, &rtl838x_8218b_fw, FIRMWARE_838X_8380_1);\n\tif (!h)\n\t\treturn -1;\n\n\tif (h->magic != 0x83808380) {\n\t\tphydev_err(phydev, \"Wrong firmware file: magic number mismatch.\\n\");\n\t\treturn -1;\n\t}\n\n\trtl8380_sds_take_reset = (void *)h + sizeof(struct fw_header)\n\t\t   + h->parts[0].start;\n\n\trtl8380_sds_common = (void *)h + sizeof(struct fw_header)\n\t\t   + h->parts[1].start;\n\n\trtl8380_sds01_qsgmii_6275b = (void *)h + sizeof(struct fw_header)\n\t\t   + h->parts[2].start;\n\n\trtl8380_sds23_qsgmii_6275b = (void *)h + sizeof(struct fw_header)\n\t\t   + h->parts[3].start;\n\n\trtl8380_sds4_fiber_6275b = (void *)h + sizeof(struct fw_header)\n\t\t   + h->parts[4].start;\n\n\trtl8380_sds5_fiber_6275b = (void *)h + sizeof(struct fw_header)\n\t\t   + h->parts[5].start;\n\n\trtl8380_sds_reset = (void *)h + sizeof(struct fw_header)\n\t\t   + h->parts[6].start;\n\n\trtl8380_sds_release_reset = (void *)h + sizeof(struct fw_header)\n\t\t   + h->parts[7].start;\n\n\t/* Back up serdes power off value */\n\tsds_conf_value = sw_r32(RTL838X_SDS_CFG_REG);\n\tpr_info(\"SDS power down value: %x\\n\", sds_conf_value);\n\n\t/* take serdes into reset */\n\ti = 0;\n\twhile (rtl8380_sds_take_reset[2 * i]) {\n\t\tsw_w32(rtl8380_sds_take_reset[2 * i + 1], rtl8380_sds_take_reset[2 * i]);\n\t\ti++;\n\t\tudelay(1000);\n\t}\n\n\t/* apply common serdes patch */\n\ti = 0;\n\twhile (rtl8380_sds_common[2 * i]) {\n\t\tsw_w32(rtl8380_sds_common[2 * i + 1], rtl8380_sds_common[2 * i]);\n\t\ti++;\n\t\tudelay(1000);\n\t}\n\n\t/* internal R/W enable */\n\tsw_w32(3, RTL838X_INT_RW_CTRL);\n\n\t/* SerDes ports 4 and 5 are FIBRE ports */\n\tsw_w32_mask(0x7 | 0x38, 1 | (1 << 3), RTL838X_INT_MODE_CTRL);\n\n\t/* SerDes module settings, SerDes 0-3 are QSGMII */\n\tv = 0x6 << 25 | 0x6 << 20 | 0x6 << 15 | 0x6 << 10;\n\t/* SerDes 4 and 5 are 1000BX FIBRE */\n\tv |= 0x4 << 5 | 0x4;\n\tsw_w32(v, RTL838X_SDS_MODE_SEL);\n\n\tpr_info(\"PLL control register: %x\\n\", sw_r32(RTL838X_PLL_CML_CTRL));\n\tsw_w32_mask(0xfffffff0, 0xaaaaaaaf & 0xf, RTL838X_PLL_CML_CTRL);\n\ti = 0;\n\twhile (rtl8380_sds01_qsgmii_6275b[2 * i]) {\n\t\tsw_w32(rtl8380_sds01_qsgmii_6275b[2 * i + 1],\n\t\t\trtl8380_sds01_qsgmii_6275b[2 * i]);\n\t\ti++;\n\t}\n\n\ti = 0;\n\twhile (rtl8380_sds23_qsgmii_6275b[2 * i]) {\n\t\tsw_w32(rtl8380_sds23_qsgmii_6275b[2 * i + 1], rtl8380_sds23_qsgmii_6275b[2 * i]);\n\t\ti++;\n\t}\n\n\ti = 0;\n\twhile (rtl8380_sds4_fiber_6275b[2 * i]) {\n\t\tsw_w32(rtl8380_sds4_fiber_6275b[2 * i + 1], rtl8380_sds4_fiber_6275b[2 * i]);\n\t\ti++;\n\t}\n\n\ti = 0;\n\twhile (rtl8380_sds5_fiber_6275b[2 * i]) {\n\t\tsw_w32(rtl8380_sds5_fiber_6275b[2 * i + 1], rtl8380_sds5_fiber_6275b[2 * i]);\n\t\ti++;\n\t}\n\n\ti = 0;\n\twhile (rtl8380_sds_reset[2 * i]) {\n\t\tsw_w32(rtl8380_sds_reset[2 * i + 1], rtl8380_sds_reset[2 * i]);\n\t\ti++;\n\t}\n\n\ti = 0;\n\twhile (rtl8380_sds_release_reset[2 * i]) {\n\t\tsw_w32(rtl8380_sds_release_reset[2 * i + 1], rtl8380_sds_release_reset[2 * i]);\n\t\ti++;\n\t}\n\n\tpr_info(\"SDS power down value now: %x\\n\", sw_r32(RTL838X_SDS_CFG_REG));\n\tsw_w32(sds_conf_value, RTL838X_SDS_CFG_REG);\n\n\tpr_info(\"Configuration of SERDES done\\n\");\n\treturn 0;\n}\n\nstatic int rtl8390_configure_serdes(struct phy_device *phydev)\n{\n\tphydev_info(phydev, \"Detected internal RTL8390 SERDES\\n\");\n\n\t/* In autoneg state, force link, set SR4_CFG_EN_LINK_FIB1G */\n\tsw_w32_mask(0, 1 << 18, RTL839X_SDS12_13_XSG0 + 0x0a);\n\n\t/* Disable EEE: Clear FRE16_EEE_RSG_FIB1G, FRE16_EEE_STD_FIB1G,\n\t * FRE16_C1_PWRSAV_EN_FIB1G, FRE16_C2_PWRSAV_EN_FIB1G\n\t * and FRE16_EEE_QUIET_FIB1G\n\t */\n\tsw_w32_mask(0x1f << 10, 0, RTL839X_SDS12_13_XSG0 + 0xe0);\n\n\treturn 0;\n}\n\nvoid rtl9300_sds_field_w(int sds, u32 page, u32 reg, int end_bit, int start_bit, u32 v)\n{\n\tint l = end_bit - start_bit + 1;\n\tu32 data = v;\n\n\tif (l < 32) {\n\t\tu32 mask = BIT(l) - 1;\n\n\t\tdata = rtl930x_read_sds_phy(sds, page, reg);\n\t\tdata &= ~(mask << start_bit);\n\t\tdata |= (v & mask) << start_bit;\n\t}\n\n\trtl930x_write_sds_phy(sds, page, reg, data);\n}\n\nu32 rtl9300_sds_field_r(int sds, u32 page, u32 reg, int end_bit, int start_bit)\n{\n\tint l = end_bit - start_bit + 1;\n\tu32 v = rtl930x_read_sds_phy(sds, page, reg);\n\n\tif (l >= 32)\n\t\treturn v;\n\n\treturn (v >> start_bit) & (BIT(l) - 1);\n}\n\n/* Read the link and speed status of the internal SerDes of the RTL9300\n */\nstatic int rtl9300_read_status(struct phy_device *phydev)\n{\n\tstruct device *dev = &phydev->mdio.dev;\n\tint phy_addr = phydev->mdio.addr;\n\tstruct device_node *dn;\n\tu32 sds_num = 0, status, latch_status, mode;\n\n\tif (dev->of_node) {\n\t\tdn = dev->of_node;\n\n\t\tif (of_property_read_u32(dn, \"sds\", &sds_num))\n\t\t\tsds_num = -1;\n\t\tpr_info(\"%s: Port %d, SerDes is %d\\n\", __func__, phy_addr, sds_num);\n\t} else {\n\t\tdev_err(dev, \"No DT node.\\n\");\n\t\treturn -EINVAL;\n\t}\n\n\tif (sds_num < 0)\n\t\treturn 0;\n\n\tmode = rtl9300_sds_mode_get(sds_num);\n\tpr_info(\"%s got SDS mode %02x\\n\", __func__, mode);\n\tif (mode == 0x1a) {\t\t// 10GR mode\n\t\tstatus = rtl9300_sds_field_r(sds_num, 0x5, 0, 12, 12);\n\t\tlatch_status = rtl9300_sds_field_r(sds_num, 0x4, 1, 2, 2);\n\t\tstatus |= rtl9300_sds_field_r(sds_num, 0x5, 0, 12, 12);\n\t\tlatch_status |= rtl9300_sds_field_r(sds_num, 0x4, 1, 2, 2);\n\t} else {\n\t\tstatus = rtl9300_sds_field_r(sds_num, 0x1, 29, 8, 0);\n\t\tlatch_status = rtl9300_sds_field_r(sds_num, 0x1, 30, 8, 0);\n\t\tstatus |= rtl9300_sds_field_r(sds_num, 0x1, 29, 8, 0);\n\t\tlatch_status |= rtl9300_sds_field_r(sds_num, 0x1, 30, 8, 0);\n\t}\n\n\tpr_info(\"%s link status: status: %d, latch %d\\n\", __func__, status, latch_status);\n\n\tif (latch_status) {\n\t\tphydev->link = true;\n\t\tif (mode == 0x1a)\n\t\t\tphydev->speed = SPEED_10000;\n\t\telse\n\t\t\tphydev->speed = SPEED_1000;\n\n\t\tphydev->duplex = DUPLEX_FULL;\n\t}\n\n\treturn 0;\n}\n\nvoid rtl930x_sds_rx_rst(int sds_num, phy_interface_t phy_if)\n{\n\tint page = 0x2e; // 10GR and USXGMII\n\n\tif (phy_if == PHY_INTERFACE_MODE_1000BASEX)\n\t\tpage = 0x24;\n\n\trtl9300_sds_field_w(sds_num, page, 0x15, 4, 4, 0x1);\n\tmdelay(5);\n\trtl9300_sds_field_w(sds_num, page, 0x15, 4, 4, 0x0);\n}\n\n/*\n * Force PHY modes on 10GBit Serdes\n */\nvoid rtl9300_force_sds_mode(int sds, phy_interface_t phy_if)\n{\n\tint sds_mode;\n\tbool lc_on;\n\tint i, lc_value;\n\tint lane_0 = (sds % 2) ? sds - 1 : sds;\n\tu32 v, cr_0, cr_1, cr_2;\n\tu32 m_bit, l_bit;\n\n\tpr_info(\"%s --------------------- serdes %d forcing to %x ...\\n\", __func__, sds, sds_mode);\n\tpr_info(\"%s: SDS: %d, mode %d\\n\", __func__, sds, phy_if);\n\tswitch (phy_if) {\n\tcase PHY_INTERFACE_MODE_SGMII:\n\t\tsds_mode = 0x2;\n\t\tlc_on = false;\n\t\tlc_value = 0x1;\n\t\tbreak;\n\n\tcase PHY_INTERFACE_MODE_HSGMII:\n\t\tsds_mode = 0x12;\n\t\tlc_value = 0x3;\n\t\t// Configure LC\n\t\tbreak;\n\n\tcase PHY_INTERFACE_MODE_1000BASEX:\n\t\tsds_mode = 0x04;\n\t\tlc_on = false;\n\t\tbreak;\n\n\tcase PHY_INTERFACE_MODE_2500BASEX:\n\t\tsds_mode = 0x16;\n\t\tlc_value = 0x3;\n\t\t// Configure LC\n\t\tbreak;\n\n\tcase PHY_INTERFACE_MODE_10GBASER:\n\t\tsds_mode = 0x1a;\n\t\tlc_on = true;\n\t\tlc_value = 0x5;\n\t\tbreak;\n\n\tcase PHY_INTERFACE_MODE_NA:\n\t\t// This will disable SerDes\n\t\tsds_mode = 0x1f;\n\t\tbreak;\n\n\tdefault:\n\t\tpr_err(\"%s: unknown serdes mode: %s\\n\",\n\t\t       __func__, phy_modes(phy_if));\n\t\treturn;\n\t}\n\n\tpr_info(\"%s: SDS mode %x\\n\", __func__, sds_mode);\n\t// Power down SerDes\n\trtl9300_sds_field_w(sds, 0x20, 0, 7, 6, 0x3);\n\tif (sds == 5) pr_info(\"%s after %x\\n\", __func__, rtl930x_read_sds_phy(sds, 0x20, 0));\n\n\tif (sds == 5) pr_info(\"%s a %x\\n\", __func__, rtl930x_read_sds_phy(sds, 0x1f, 9));\n\t// Force mode enable\n\trtl9300_sds_field_w(sds, 0x1f, 9, 6, 6, 0x1);\n\tif (sds == 5) pr_info(\"%s b %x\\n\", __func__, rtl930x_read_sds_phy(sds, 0x1f, 9));\n\n\t/* SerDes off */\n\trtl9300_sds_field_w(sds, 0x1f, 9, 11, 7, 0x1f);\n\n\tif (phy_if == PHY_INTERFACE_MODE_NA)\n\t\treturn;\n\n\tif (sds == 5) pr_info(\"%s c %x\\n\", __func__, rtl930x_read_sds_phy(sds, 0x20, 18));\n\t// Enable LC and ring\n\trtl9300_sds_field_w(lane_0, 0x20, 18, 3, 0, 0xf);\n\n\tif (sds == lane_0)\n\t\trtl9300_sds_field_w(lane_0, 0x20, 18, 5, 4, 0x1);\n\telse\n\t\trtl9300_sds_field_w(lane_0, 0x20, 18, 7, 6, 0x1);\n\n\trtl9300_sds_field_w(sds, 0x20, 0, 5, 4, 0x3);\n\n\tif (lc_on)\n\t\trtl9300_sds_field_w(lane_0, 0x20, 18, 11, 8, lc_value);\n\telse\n\t\trtl9300_sds_field_w(lane_0, 0x20, 18, 15, 12, lc_value);\n\n\t// Force analog LC & ring on\n\trtl9300_sds_field_w(lane_0, 0x21, 11, 3, 0, 0xf);\n\n\tv = lc_on ? 0x3 : 0x1;\n\n\tif (sds == lane_0)\n\t\trtl9300_sds_field_w(lane_0, 0x20, 18, 5, 4, v);\n\telse\n\t\trtl9300_sds_field_w(lane_0, 0x20, 18, 7, 6, v);\n\n\t// Force SerDes mode\n\trtl9300_sds_field_w(sds, 0x1f, 9, 6, 6, 1);\n\trtl9300_sds_field_w(sds, 0x1f, 9, 11, 7, sds_mode);\n\n\t// Toggle LC or Ring\n\tfor (i = 0; i < 20; i++) {\n\t\tmdelay(200);\n\n\t\trtl930x_write_sds_phy(lane_0, 0x1f, 2, 53);\n\n\t\tm_bit = (lane_0 == sds) ? (4) : (5);\n\t\tl_bit = (lane_0 == sds) ? (4) : (5);\n\n\t\tcr_0 = rtl9300_sds_field_r(lane_0, 0x1f, 20, m_bit, l_bit);\n\t\tmdelay(10);\n\t\tcr_1 = rtl9300_sds_field_r(lane_0, 0x1f, 20, m_bit, l_bit);\n\t\tmdelay(10);\n\t\tcr_2 = rtl9300_sds_field_r(lane_0, 0x1f, 20, m_bit, l_bit);\n\n\t\tif (cr_0 && cr_1 && cr_2) {\n\t\t\tu32 t;\n\t\t\tif (phy_if != PHY_INTERFACE_MODE_10GBASER)\n\t\t\t\tbreak;\n\n\t\t\tt = rtl9300_sds_field_r(sds, 0x6, 0x1, 2, 2);\n\t\t\trtl9300_sds_field_w(sds, 0x6, 0x1, 2, 2, 0x1);\n\n\t\t\t// Reset FSM\n\t\t\trtl9300_sds_field_w(sds, 0x6, 0x2, 12, 12, 0x1);\n\t\t\tmdelay(10);\n\t\t\trtl9300_sds_field_w(sds, 0x6, 0x2, 12, 12, 0x0);\n\t\t\tmdelay(10);\n\n\t\t\t// Need to read this twice\n\t\t\tv = rtl9300_sds_field_r(sds, 0x5, 0, 12, 12);\n\t\t\tv = rtl9300_sds_field_r(sds, 0x5, 0, 12, 12);\n\n\t\t\trtl9300_sds_field_w(sds, 0x6, 0x1, 2, 2, t);\n\n\t\t\t// Reset FSM again\n\t\t\trtl9300_sds_field_w(sds, 0x6, 0x2, 12, 12, 0x1);\n\t\t\tmdelay(10);\n\t\t\trtl9300_sds_field_w(sds, 0x6, 0x2, 12, 12, 0x0);\n\t\t\tmdelay(10);\n\n\t\t\tif (v == 1)\n\t\t\t\tbreak;\n\t\t}\n\n\t\tm_bit = (phy_if == PHY_INTERFACE_MODE_10GBASER) ? 3 : 1;\n\t\tl_bit = (phy_if == PHY_INTERFACE_MODE_10GBASER) ? 2 : 0;\n\n\t\trtl9300_sds_field_w(lane_0, 0x21, 11, m_bit, l_bit, 0x2);\n\t\tmdelay(10);\n\t\trtl9300_sds_field_w(lane_0, 0x21, 11, m_bit, l_bit, 0x3);\n\t}\n\n\trtl930x_sds_rx_rst(sds, phy_if);\n\n\t// Re-enable power\n\trtl9300_sds_field_w(sds, 0x20, 0, 7, 6, 0);\n\n\tpr_info(\"%s --------------------- serdes %d forced to %x DONE\\n\", __func__, sds, sds_mode);\n}\n\nvoid rtl9300_sds_tx_config(int sds, phy_interface_t phy_if)\n{\n\t// parameters: rtl9303_80G_txParam_s2\n\tint impedance = 0x8;\n\tint pre_amp = 0x2;\n\tint main_amp = 0x9;\n\tint post_amp = 0x2;\n\tint pre_en = 0x1;\n\tint post_en = 0x1;\n\tint page;\n\n\tswitch(phy_if) {\n\tcase PHY_INTERFACE_MODE_1000BASEX:\n\t\tpage = 0x25;\n\t\tbreak;\n\tcase PHY_INTERFACE_MODE_HSGMII:\n\tcase PHY_INTERFACE_MODE_2500BASEX:\n\t\tpage = 0x29;\n\t\tbreak;\n\tcase PHY_INTERFACE_MODE_10GBASER:\n\t\tpage = 0x2f;\n\t\tbreak;\n\tdefault:\n\t\tpr_err(\"%s: unsupported PHY mode\\n\", __func__);\n\t\treturn;\n\t}\n\n\trtl9300_sds_field_w(sds, page, 0x1, 15, 11, pre_amp);\n\trtl9300_sds_field_w(sds, page, 0x7, 0, 0, pre_en);\n\trtl9300_sds_field_w(sds, page, 0x7, 8, 4, main_amp);\n\trtl9300_sds_field_w(sds, page, 0x6, 4, 0, post_amp);\n\trtl9300_sds_field_w(sds, page, 0x7, 3, 3, post_en);\n\trtl9300_sds_field_w(sds, page, 0x18, 15, 12, impedance);\n}\n\n/*\n * Wait for clock ready, this assumes the SerDes is in XGMII mode\n * timeout is in ms\n */\nint rtl9300_sds_clock_wait(int timeout)\n{\n\tu32 v;\n\tunsigned long start = jiffies;\n\n\tdo {\n\t\trtl9300_sds_field_w(2, 0x1f, 0x2, 15, 0, 53);\n\t\tv = rtl9300_sds_field_r(2, 0x1f, 20, 5, 4);\n\t\tif (v == 3)\n\t\t\treturn 0;\n\t} while (jiffies < start + (HZ / 1000) * timeout);\n\n\treturn 1;\n}\n\nvoid rtl9300_serdes_mac_link_config(int sds, bool tx_normal, bool rx_normal)\n{\n\tu32 v10, v1;\n\n\tv10 = rtl930x_read_sds_phy(sds, 6, 2); // 10GBit, page 6, reg 2\n\tv1 = rtl930x_read_sds_phy(sds, 0, 0); // 1GBit, page 0, reg 0\n\tpr_info(\"%s: registers before %08x %08x\\n\", __func__, v10, v1);\n\n\tv10 &= ~(BIT(13) | BIT(14));\n\tv1 &= ~(BIT(8) | BIT(9));\n\n\tv10 |= rx_normal ? 0 : BIT(13);\n\tv1 |= rx_normal ? 0 : BIT(9);\n\n\tv10 |= tx_normal ? 0 : BIT(14);\n\tv1 |= tx_normal ? 0 : BIT(8);\n\n\trtl930x_write_sds_phy(sds, 6, 2, v10);\n\trtl930x_write_sds_phy(sds, 0, 0, v1);\n\n\tv10 = rtl930x_read_sds_phy(sds, 6, 2);\n\tv1 = rtl930x_read_sds_phy(sds, 0, 0);\n\tpr_info(\"%s: registers after %08x %08x\\n\", __func__, v10, v1);\n}\n\nvoid rtl9300_sds_rxcal_dcvs_manual(u32 sds_num, u32 dcvs_id, bool manual, u32 dvcs_list[])\n{\n\tif (manual) {\n\t\tswitch(dcvs_id) {\n\t\tcase 0:\n\t\t\trtl9300_sds_field_w(sds_num, 0x2e, 0x1e, 14, 14, 0x1);\n\t\t\trtl9300_sds_field_w(sds_num, 0x2f, 0x03, 5, 5, dvcs_list[0]);\n\t\t\trtl9300_sds_field_w(sds_num, 0x2f, 0x03, 4, 0, dvcs_list[1]);\n\t\t\tbreak;\n\t\tcase 1:\n\t\t\trtl9300_sds_field_w(sds_num, 0x2e, 0x1e, 13, 13, 0x1);\n\t\t\trtl9300_sds_field_w(sds_num, 0x2e, 0x1d, 15, 15, dvcs_list[0]);\n\t\t\trtl9300_sds_field_w(sds_num, 0x2e, 0x1d, 14, 11, dvcs_list[1]);\n\t\t\tbreak;\n\t\tcase 2:\n\t\t\trtl9300_sds_field_w(sds_num, 0x2e, 0x1e, 12, 12, 0x1);\n\t\t\trtl9300_sds_field_w(sds_num, 0x2e, 0x1d, 10, 10, dvcs_list[0]);\n\t\t\trtl9300_sds_field_w(sds_num, 0x2e, 0x1d, 9, 6, dvcs_list[1]);\n\t\t\tbreak;\n\t\tcase 3:\n\t\t\trtl9300_sds_field_w(sds_num, 0x2e, 0x1e, 11, 11, 0x1);\n\t\t\trtl9300_sds_field_w(sds_num, 0x2e, 0x1d, 5, 5, dvcs_list[0]);\n\t\t\trtl9300_sds_field_w(sds_num, 0x2e, 0x1d, 4, 1, dvcs_list[1]);\n\t\t\tbreak;\n\t\tcase 4:\n\t\t\trtl9300_sds_field_w(sds_num, 0x2e, 0x01, 15, 15, 0x1);\n\t\t\trtl9300_sds_field_w(sds_num, 0x2e, 0x11, 10, 10, dvcs_list[0]);\n\t\t\trtl9300_sds_field_w(sds_num, 0x2e, 0x11, 9, 6, dvcs_list[1]);\n\t\t\tbreak;\n\t\tcase 5:\n\t\t\trtl9300_sds_field_w(sds_num, 0x2e, 0x02, 11, 11, 0x1);\n\t\t\trtl9300_sds_field_w(sds_num, 0x2e, 0x11, 4, 4, dvcs_list[0]);\n\t\t\trtl9300_sds_field_w(sds_num, 0x2e, 0x11, 3, 0, dvcs_list[1]);\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tbreak;\n\t\t}\n\t} else {\n\t\tswitch(dcvs_id) {\n\t\tcase 0:\n\t\t\trtl9300_sds_field_w(sds_num, 0x2e, 0x1e, 14, 14, 0x0);\n\t\t\tbreak;\n\t\tcase 1:\n\t\t\trtl9300_sds_field_w(sds_num, 0x2e, 0x1e, 13, 13, 0x0);\n\t\t\tbreak;\n\t\tcase 2:\n\t\t\trtl9300_sds_field_w(sds_num, 0x2e, 0x1e, 12, 12, 0x0);\n\t\t\tbreak;\n\t\tcase 3:\n\t\t\trtl9300_sds_field_w(sds_num, 0x2e, 0x1e, 11, 11, 0x0);\n\t\t\tbreak;\n\t\tcase 4:\n\t\t\trtl9300_sds_field_w(sds_num, 0x2e, 0x01, 15, 15, 0x0);\n\t\t\tbreak;\n\t\tcase 5:\n\t\t\trtl9300_sds_field_w(sds_num, 0x2e, 0x02, 11, 11, 0x0);\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tbreak;\n\t\t}\n\t\tmdelay(1);\n\t}\n}\n\nvoid rtl9300_sds_rxcal_dcvs_get(u32 sds_num, u32 dcvs_id, u32 dcvs_list[])\n{\n\tu32 dcvs_sign_out = 0, dcvs_coef_bin = 0;\n\tbool dcvs_manual;\n\n\tif (!(sds_num % 2))\n\t\trtl930x_write_sds_phy(sds_num, 0x1f, 0x2, 0x2f);\n\telse\n\t\trtl930x_write_sds_phy(sds_num - 1, 0x1f, 0x2, 0x31);\n\n\t// ##Page0x2E, Reg0x15[9], REG0_RX_EN_TEST=[1]\n\trtl9300_sds_field_w(sds_num, 0x2e, 0x15, 9, 9, 0x1);\n\n\t// ##Page0x21, Reg0x06[11 6], REG0_RX_DEBUG_SEL=[1 0 x x x x]\n\trtl9300_sds_field_w(sds_num, 0x21, 0x06, 11, 6, 0x20);\n\n\tswitch(dcvs_id) {\n\tcase 0:\n\t\trtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0x22);\n\t\tmdelay(1);\n\n\t\t// ##DCVS0 Read Out\n\t\tdcvs_sign_out = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 4);\n\t\tdcvs_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 3, 0);\n\t\tdcvs_manual = !!rtl9300_sds_field_r(sds_num, 0x2e, 0x1e, 14, 14);\n\t\tbreak;\n\n\tcase 1:\n\t\trtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0x23);\n\t\tmdelay(1);\n\n\t\t// ##DCVS0 Read Out\n\t\tdcvs_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 4);\n\t\tdcvs_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 3, 0);\n\t\tdcvs_manual = !!rtl9300_sds_field_r(sds_num, 0x2e, 0x1e, 13, 13);\n\t\tbreak;\n\n\tcase 2:\n\t\trtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0x24);\n\t\tmdelay(1);\n\n\t\t// ##DCVS0 Read Out\n\t\tdcvs_sign_out = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 4);\n\t\tdcvs_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 3, 0);\n\t\tdcvs_manual = !!rtl9300_sds_field_r(sds_num, 0x2e, 0x1e, 12, 12);\n\t\tbreak;\n\tcase 3:\n\t\trtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0x25);\n\t\tmdelay(1);\n\n\t\t// ##DCVS0 Read Out\n\t\tdcvs_sign_out = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 4);\n\t\tdcvs_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 3, 0);\n\t\tdcvs_manual = rtl9300_sds_field_r(sds_num, 0x2e, 0x1e, 11, 11);\n\t\tbreak;\n\n\tcase 4:\n\t\trtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0x2c);\n\t\tmdelay(1);\n\n\t\t// ##DCVS0 Read Out\n\t\tdcvs_sign_out = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 4);\n\t\tdcvs_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 3, 0);\n\t\tdcvs_manual = !!rtl9300_sds_field_r(sds_num, 0x2e, 0x01, 15, 15);\n\t\tbreak;\n\n\tcase 5:\n\t\trtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0x2d);\n\t\tmdelay(1);\n\n\t\t// ##DCVS0 Read Out\n\t\tdcvs_sign_out = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 4);\n\t\tdcvs_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 3, 0);\n\t\tdcvs_manual = rtl9300_sds_field_r(sds_num, 0x2e, 0x02, 11, 11);\n\t\tbreak;\n\n\tdefault:\n\t\tbreak;\n\t}\n\n\tif (dcvs_sign_out)\n\t\tpr_info(\"%s DCVS %u Sign: -\", __func__, dcvs_id);\n\telse\n\t\tpr_info(\"%s DCVS %u Sign: +\", __func__, dcvs_id);\n\n\tpr_info(\"DCVS %u even coefficient = %u\", dcvs_id, dcvs_coef_bin);\n\tpr_info(\"DCVS %u manual = %u\", dcvs_id, dcvs_manual);\n\n\tdcvs_list[0] = dcvs_sign_out;\n\tdcvs_list[1] = dcvs_coef_bin;\n}\n\nvoid rtl9300_sds_rxcal_leq_manual(u32 sds_num, bool manual, u32 leq_gray)\n{\n\tif (manual) {\n\t\trtl9300_sds_field_w(sds_num, 0x2e, 0x18, 15, 15, 0x1);\n\t\trtl9300_sds_field_w(sds_num, 0x2e, 0x16, 14, 10, leq_gray);\n\t} else {\n\t\trtl9300_sds_field_w(sds_num, 0x2e, 0x18, 15, 15, 0x0);\n\t\tmdelay(100);\n\t}\n}\n\nvoid rtl9300_sds_rxcal_leq_offset_manual(u32 sds_num, bool manual, u32 offset)\n{\n\tif (manual) {\n\t\trtl9300_sds_field_w(sds_num, 0x2e, 0x17, 6, 2, offset);\n\t} else {\n\t\trtl9300_sds_field_w(sds_num, 0x2e, 0x17, 6, 2, offset);\n\t\tmdelay(1);\n\t}\n}\n\n#define GRAY_BITS 5\nu32 rtl9300_sds_rxcal_gray_to_binary(u32 gray_code)\n{\n\tint i, j, m;\n\tu32 g[GRAY_BITS];\n\tu32 c[GRAY_BITS];\n\tu32 leq_binary = 0;\n\n\tfor(i = 0; i < GRAY_BITS; i++)\n\t\tg[i] = (gray_code & BIT(i)) >> i;\n\n\tm = GRAY_BITS - 1;\n\n\tc[m] = g[m];\n\n\tfor(i = 0; i < m; i++) {\n\t\tc[i] = g[i];\n\t\tfor(j  = i + 1; j < GRAY_BITS; j++)\n\t\t\tc[i] = c[i] ^ g[j];\n\t}\n\n\tfor(i = 0; i < GRAY_BITS; i++)\n\t\tleq_binary += c[i] << i;\n\n\treturn leq_binary;\n}\n\nu32 rtl9300_sds_rxcal_leq_read(int sds_num)\n{\n\tu32 leq_gray, leq_bin;\n\tbool leq_manual;\n\n\tif (!(sds_num % 2))\n\t\trtl930x_write_sds_phy(sds_num, 0x1f, 0x2, 0x2f);\n\telse\n\t\trtl930x_write_sds_phy(sds_num - 1, 0x1f, 0x2, 0x31);\n\n\t// ##Page0x2E, Reg0x15[9], REG0_RX_EN_TEST=[1]\n\trtl9300_sds_field_w(sds_num, 0x2e, 0x15, 9, 9, 0x1);\n\n\t// ##Page0x21, Reg0x06[11 6], REG0_RX_DEBUG_SEL=[0 1 x x x x]\n\trtl9300_sds_field_w(sds_num, 0x21, 0x06, 11, 6, 0x10);\n\tmdelay(1);\n\n\t// ##LEQ Read Out\n\tleq_gray = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 7, 3);\n\tleq_manual = !!rtl9300_sds_field_r(sds_num, 0x2e, 0x18, 15, 15);\n\tleq_bin = rtl9300_sds_rxcal_gray_to_binary(leq_gray);\n\n\tpr_info(\"LEQ_gray: %u, LEQ_bin: %u\", leq_gray, leq_bin);\n\tpr_info(\"LEQ manual: %u\", leq_manual);\n\n\treturn leq_bin;\n}\n\nvoid rtl9300_sds_rxcal_vth_manual(u32 sds_num, bool manual, u32 vth_list[])\n{\n\tif (manual) {\n\t\trtl9300_sds_field_w(sds_num, 0x2e, 0x0f, 13, 13, 0x1);\n\t\trtl9300_sds_field_w(sds_num, 0x2e, 0x13, 5, 3, vth_list[0]);\n\t\trtl9300_sds_field_w(sds_num, 0x2e, 0x13, 2, 0, vth_list[1]);\n\t} else {\n\t\trtl9300_sds_field_w(sds_num, 0x2e, 0x0f, 13, 13, 0x0);\n\t\tmdelay(10);\n\t}\n}\n\nvoid rtl9300_sds_rxcal_vth_get(u32  sds_num, u32 vth_list[])\n{\n\tu32 vth_manual;\n\n\t//##Page0x1F, Reg0x02[15 0], REG_DBGO_SEL=[0x002F]; //Lane0\n\t//##Page0x1F, Reg0x02[15 0], REG_DBGO_SEL=[0x0031]; //Lane1\n\tif (!(sds_num % 2))\n\t\trtl930x_write_sds_phy(sds_num, 0x1f, 0x2, 0x2f);\n\telse\n\t\trtl930x_write_sds_phy(sds_num - 1, 0x1f, 0x2, 0x31);\n\n\t//##Page0x2E, Reg0x15[9], REG0_RX_EN_TEST=[1]\n\trtl9300_sds_field_w(sds_num, 0x2e, 0x15, 9, 9, 0x1);\n\t//##Page0x21, Reg0x06[11 6], REG0_RX_DEBUG_SEL=[1 0 x x x x]\n\trtl9300_sds_field_w(sds_num, 0x21, 0x06, 11, 6, 0x20);\n\t//##Page0x2F, Reg0x0C[5 0], REG0_COEF_SEL=[0 0 1 1 0 0]\n\trtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0xc);\n\n\tmdelay(1);\n\n\t//##VthP & VthN Read Out\n\tvth_list[0] = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 2, 0); // v_thp set bin\n\tvth_list[1] = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 5, 3); // v_thn set bin\n\n\tpr_info(\"vth_set_bin = %d\", vth_list[0]);\n\tpr_info(\"vth_set_bin = %d\", vth_list[1]);\n\n\tvth_manual = !!rtl9300_sds_field_r(sds_num, 0x2e, 0x0f, 13, 13);\n\tpr_info(\"Vth Maunal = %d\", vth_manual);\n}\n\nvoid rtl9300_sds_rxcal_tap_manual(u32 sds_num, int tap_id, bool manual, u32 tap_list[])\n{\n\tif (manual) {\n\t\tswitch(tap_id) {\n\t\tcase 0:\n\t\t\t//##REG0_LOAD_IN_INIT[0]=1; REG0_TAP0_INIT[5:0]=Tap0_Value\n\t\t\trtl9300_sds_field_w(sds_num, 0x2e, 0x0f, tap_id + 7, tap_id + 7, 0x1);\n\t\t\trtl9300_sds_field_w(sds_num, 0x2f, 0x03, 5, 5, tap_list[0]);\n\t\t\trtl9300_sds_field_w(sds_num, 0x2f, 0x03, 4, 0, tap_list[1]);\n\t\t\tbreak;\n\t\tcase 1:\n\t\t\trtl9300_sds_field_w(sds_num, 0x2e, 0x0f, tap_id + 7, tap_id + 7, 0x1);\n\t\t\trtl9300_sds_field_w(sds_num, 0x21, 0x07, 6, 6, tap_list[0]);\n\t\t\trtl9300_sds_field_w(sds_num, 0x2e, 0x09, 11, 6, tap_list[1]);\n\t\t\trtl9300_sds_field_w(sds_num, 0x21, 0x07, 5, 5, tap_list[2]);\n\t\t\trtl9300_sds_field_w(sds_num, 0x2f, 0x12, 5, 0, tap_list[3]);\n\t\t\tbreak;\n\t\tcase 2:\n\t\t\trtl9300_sds_field_w(sds_num, 0x2e, 0x0f, tap_id + 7, tap_id + 7, 0x1);\n\t\t\trtl9300_sds_field_w(sds_num, 0x2e, 0x09, 5, 5, tap_list[0]);\n\t\t\trtl9300_sds_field_w(sds_num, 0x2e, 0x09, 4, 0, tap_list[1]);\n\t\t\trtl9300_sds_field_w(sds_num, 0x2e, 0x0a, 11, 11, tap_list[2]);\n\t\t\trtl9300_sds_field_w(sds_num, 0x2e, 0x0a, 10, 6, tap_list[3]);\n\t\t\tbreak;\n\t\tcase 3:\n\t\t\trtl9300_sds_field_w(sds_num, 0x2e, 0x0f, tap_id + 7, tap_id + 7, 0x1);\n\t\t\trtl9300_sds_field_w(sds_num, 0x2e, 0x0a, 5, 5, tap_list[0]);\n\t\t\trtl9300_sds_field_w(sds_num, 0x2e, 0x0a, 4, 0, tap_list[1]);\n\t\t\trtl9300_sds_field_w(sds_num, 0x2e, 0x06, 5, 5, tap_list[2]);\n\t\t\trtl9300_sds_field_w(sds_num, 0x2e, 0x06, 4, 0, tap_list[3]);\n\t\t\tbreak;\n\t\tcase 4:\n\t\t\trtl9300_sds_field_w(sds_num, 0x2e, 0x0f, tap_id + 7, tap_id + 7, 0x1);\n\t\t\trtl9300_sds_field_w(sds_num, 0x2f, 0x01, 5, 5, tap_list[0]);\n\t\t\trtl9300_sds_field_w(sds_num, 0x2f, 0x01, 4, 0, tap_list[1]);\n\t\t\trtl9300_sds_field_w(sds_num, 0x2e, 0x06, 11, 11, tap_list[2]);\n\t\t\trtl9300_sds_field_w(sds_num, 0x2e, 0x06, 10, 6, tap_list[3]);\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tbreak;\n\t\t}\n\t} else {\n\t\trtl9300_sds_field_w(sds_num, 0x2e, 0x0f, tap_id + 7, tap_id + 7, 0x0);\n\t\tmdelay(10);\n\t}\n}\n\nvoid rtl9300_sds_rxcal_tap_get(u32 sds_num, u32 tap_id, u32 tap_list[])\n{\n\tu32 tap0_sign_out;\n\tu32 tap0_coef_bin;\n\tu32 tap_sign_out_even;\n\tu32 tap_coef_bin_even;\n\tu32 tap_sign_out_odd;\n\tu32 tap_coef_bin_odd;\n\tbool tap_manual;\n\n\tif (!(sds_num % 2))\n\t\trtl930x_write_sds_phy(sds_num, 0x1f, 0x2, 0x2f);\n\telse\n\t\trtl930x_write_sds_phy(sds_num - 1, 0x1f, 0x2, 0x31);\n\n\t//##Page0x2E, Reg0x15[9], REG0_RX_EN_TEST=[1]\n\trtl9300_sds_field_w(sds_num, 0x2e, 0x15, 9, 9, 0x1);\n\t//##Page0x21, Reg0x06[11 6], REG0_RX_DEBUG_SEL=[1 0 x x x x]\n\trtl9300_sds_field_w(sds_num, 0x21, 0x06, 11, 6, 0x20);\n\n\tif (!tap_id) {\n\t\t//##Page0x2F, Reg0x0C[5 0], REG0_COEF_SEL=[0 0 0 0 0 1]\n\t\trtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0);\n\t\t//##Tap1 Even Read Out\n\t\tmdelay(1);\n\t\ttap0_sign_out = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 5, 5);\n\t\ttap0_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 0);\n\n\t\tif (tap0_sign_out == 1)\n\t\t\tpr_info(\"Tap0 Sign : -\");\n\t\telse\n\t\t\tpr_info(\"Tap0 Sign : +\");\n\n\t\tpr_info(\"tap0_coef_bin = %d\", tap0_coef_bin);\n\n\t\ttap_list[0] = tap0_sign_out;\n\t\ttap_list[1] = tap0_coef_bin;\n\n\t\ttap_manual = !!rtl9300_sds_field_r(sds_num, 0x2e, 0x0f, 7, 7);\n\t\tpr_info(\"tap0 manual = %u\",tap_manual);\n\t} else {\n\t\t//##Page0x2F, Reg0x0C[5 0], REG0_COEF_SEL=[0 0 0 0 0 1]\n\t\trtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, tap_id);\n\t\tmdelay(1);\n\t\t//##Tap1 Even Read Out\n\t\ttap_sign_out_even = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 5, 5);\n\t\ttap_coef_bin_even = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 0);\n\n\t\t//##Page0x2F, Reg0x0C[5 0], REG0_COEF_SEL=[0 0 0 1 1 0]\n\t\trtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, (tap_id + 5));\n\t\t//##Tap1 Odd Read Out\n\t\ttap_sign_out_odd = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 5, 5);\n\t\ttap_coef_bin_odd = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 0);\n\n\t\tif (tap_sign_out_even == 1)\n\t\t\tpr_info(\"Tap %u even sign: -\", tap_id);\n\t\telse\n\t\t\tpr_info(\"Tap %u even sign: +\", tap_id);\n\n\t\tpr_info(\"Tap %u even coefficient = %u\", tap_id, tap_coef_bin_even);\n\n\t\tif (tap_sign_out_odd == 1)\n\t\t\tpr_info(\"Tap %u odd sign: -\", tap_id);\n\t\telse\n\t\t\tpr_info(\"Tap %u odd sign: +\", tap_id);\n\n\t\tpr_info(\"Tap %u odd coefficient = %u\", tap_id,tap_coef_bin_odd);\n\n\t\ttap_list[0] = tap_sign_out_even;\n\t\ttap_list[1] = tap_coef_bin_even;\n\t\ttap_list[2] = tap_sign_out_odd;\n\t\ttap_list[3] = tap_coef_bin_odd;\n\n\t\ttap_manual = rtl9300_sds_field_r(sds_num, 0x2e, 0x0f, tap_id + 7, tap_id + 7);\n\t\tpr_info(\"tap %u manual = %d\",tap_id, tap_manual);\n\t}\n}\n\nvoid rtl9300_do_rx_calibration_1(int sds, phy_interface_t phy_mode)\n{\n\t// From both rtl9300_rxCaliConf_serdes_myParam and rtl9300_rxCaliConf_phy_myParam\n\tint tap0_init_val       = 0x1f; // Initial Decision Fed Equalizer 0 tap\n\tint vth_min             = 0x0;\n\n\tpr_info(\"start_1.1.1 initial value for sds %d\\n\", sds);\n\trtl930x_write_sds_phy(sds, 6,  0, 0);\n\n\t// FGCAL\n\trtl9300_sds_field_w(sds, 0x2e, 0x01, 14, 14, 0x0);\n\trtl9300_sds_field_w(sds, 0x2e, 0x1c, 10, 5, 0x20);\n\trtl9300_sds_field_w(sds, 0x2f, 0x02, 0, 0, 0x1);\n\n\t// DCVS\n\trtl9300_sds_field_w(sds, 0x2e, 0x1e, 14, 11, 0x0);\n\trtl9300_sds_field_w(sds, 0x2e, 0x01, 15, 15, 0x0);\n\trtl9300_sds_field_w(sds, 0x2e, 0x02, 11, 11, 0x0);\n\trtl9300_sds_field_w(sds, 0x2e, 0x1c, 4, 0, 0x0);\n\trtl9300_sds_field_w(sds, 0x2e, 0x1d, 15, 11, 0x0);\n\trtl9300_sds_field_w(sds, 0x2e, 0x1d, 10, 6, 0x0);\n\trtl9300_sds_field_w(sds, 0x2e, 0x1d, 5, 1, 0x0);\n\trtl9300_sds_field_w(sds, 0x2e, 0x02, 10, 6, 0x0);\n\trtl9300_sds_field_w(sds, 0x2e, 0x11, 4, 0, 0x0);\n\trtl9300_sds_field_w(sds, 0x2f, 0x00, 3, 0, 0xf);\n\trtl9300_sds_field_w(sds, 0x2e, 0x04, 6, 6, 0x1);\n\trtl9300_sds_field_w(sds, 0x2e, 0x04, 7, 7, 0x1);\n\n\t// LEQ (Long Term Equivalent signal level)\n\trtl9300_sds_field_w(sds, 0x2e, 0x16, 14, 8, 0x0);\n\n\t// DFE (Decision Fed Equalizer)\n\trtl9300_sds_field_w(sds, 0x2f, 0x03, 5, 0, tap0_init_val);\n\trtl9300_sds_field_w(sds, 0x2e, 0x09, 11, 6, 0x0);\n\trtl9300_sds_field_w(sds, 0x2e, 0x09, 5, 0, 0x0);\n\trtl9300_sds_field_w(sds, 0x2e, 0x0a, 5, 0, 0x0);\n\trtl9300_sds_field_w(sds, 0x2f, 0x01, 5, 0, 0x0);\n\trtl9300_sds_field_w(sds, 0x2f, 0x12, 5, 0, 0x0);\n\trtl9300_sds_field_w(sds, 0x2e, 0x0a, 11, 6, 0x0);\n\trtl9300_sds_field_w(sds, 0x2e, 0x06, 5, 0, 0x0);\n\trtl9300_sds_field_w(sds, 0x2f, 0x01, 5, 0, 0x0);\n\n\t// Vth\n\trtl9300_sds_field_w(sds, 0x2e, 0x13, 5, 3, 0x7);\n\trtl9300_sds_field_w(sds, 0x2e, 0x13, 2, 0, 0x7);\n\trtl9300_sds_field_w(sds, 0x2f, 0x0b, 5, 3, vth_min);\n\n\tpr_info(\"end_1.1.1 --\\n\");\n\n\tpr_info(\"start_1.1.2 Load DFE init. value\\n\");\n\n\trtl9300_sds_field_w(sds, 0x2e, 0x0f, 13, 7, 0x7f);\n\n\tpr_info(\"end_1.1.2\\n\");\n\n\tpr_info(\"start_1.1.3 disable LEQ training,enable DFE clock\\n\");\n\n\trtl9300_sds_field_w(sds, 0x2e, 0x17, 7, 7, 0x0);\n\trtl9300_sds_field_w(sds, 0x2e, 0x17, 6, 2, 0x0);\n\trtl9300_sds_field_w(sds, 0x2e, 0x0c, 8, 8, 0x0);\n\trtl9300_sds_field_w(sds, 0x2e, 0x0b, 4, 4, 0x1);\n\trtl9300_sds_field_w(sds, 0x2e, 0x12, 14, 14, 0x0);\n\trtl9300_sds_field_w(sds, 0x2f, 0x02, 15, 15, 0x0);\n\n\tpr_info(\"end_1.1.3 --\\n\");\n\n\tpr_info(\"start_1.1.4 offset cali setting\\n\");\n\n\trtl9300_sds_field_w(sds, 0x2e, 0x0f, 15, 14, 0x3);\n\n\tpr_info(\"end_1.1.4\\n\");\n\n\tpr_info(\"start_1.1.5 LEQ and DFE setting\\n\");\n\n\t// TODO: make this work for DAC cables of different lengths\n\t// For a 10GBit serdes wit Fibre, SDS 8 or 9\n\tif (phy_mode == PHY_INTERFACE_MODE_10GBASER || PHY_INTERFACE_MODE_1000BASEX)\n\t\trtl9300_sds_field_w(sds, 0x2e, 0x16, 3, 2, 0x2);\n\telse\n\t\tpr_err(\"%s not PHY-based or SerDes, implement DAC!\\n\", __func__);\n\n\t// No serdes, check for Aquantia PHYs\n\trtl9300_sds_field_w(sds, 0x2e, 0x16, 3, 2, 0x2);\n\n\trtl9300_sds_field_w(sds, 0x2e, 0x0f, 6, 0, 0x5f);\n\trtl9300_sds_field_w(sds, 0x2f, 0x05, 7, 2, 0x1f);\n\trtl9300_sds_field_w(sds, 0x2e, 0x19, 9, 5, 0x1f);\n\trtl9300_sds_field_w(sds, 0x2f, 0x0b, 15, 9, 0x3c);\n\trtl9300_sds_field_w(sds, 0x2e, 0x0b, 1, 0, 0x3);\n\n\tpr_info(\"end_1.1.5\\n\");\n}\n\nvoid rtl9300_do_rx_calibration_2_1(u32 sds_num)\n{\n\tpr_info(\"start_1.2.1 ForegroundOffsetCal_Manual\\n\");\n\n\t// Gray config endis to 1\n\trtl9300_sds_field_w(sds_num, 0x2f, 0x02, 2, 2, 0x1);\n\n\t// ForegroundOffsetCal_Manual(auto mode)\n\trtl9300_sds_field_w(sds_num, 0x2e, 0x01, 14, 14, 0x0);\n\n\tpr_info(\"end_1.2.1\");\n}\n\nvoid rtl9300_do_rx_calibration_2_2(int sds_num)\n{\n\t//Force Rx-Run = 0\n\trtl9300_sds_field_w(sds_num, 0x2e, 0x15, 8, 8, 0x0);\n\n\trtl930x_sds_rx_rst(sds_num, PHY_INTERFACE_MODE_10GBASER);\n}\n\nvoid rtl9300_do_rx_calibration_2_3(int sds_num)\n{\n\tu32 fgcal_binary, fgcal_gray;\n\tu32 offset_range;\n\n\tpr_info(\"start_1.2.3 Foreground Calibration\\n\");\n\n\twhile(1) {\n\t\tif (!(sds_num % 2))\n\t\t\trtl930x_write_sds_phy(sds_num, 0x1f, 0x2, 0x2f);\n\t\telse\n\t\t\trtl930x_write_sds_phy(sds_num -1 , 0x1f, 0x2, 0x31);\n\n\t\t// ##Page0x2E, Reg0x15[9], REG0_RX_EN_TEST=[1]\n\t\trtl9300_sds_field_w(sds_num, 0x2e, 0x15, 9, 9, 0x1);\n\t\t// ##Page0x21, Reg0x06[11 6], REG0_RX_DEBUG_SEL=[1 0 x x x x]\n\t\trtl9300_sds_field_w(sds_num, 0x21, 0x06, 11, 6, 0x20);\n\t\t// ##Page0x2F, Reg0x0C[5 0], REG0_COEF_SEL=[0 0 1 1 1 1]\n\t\trtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0xf);\n\t\t// ##FGCAL read gray\n\t\tfgcal_gray = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 5, 0);\n\t\t// ##Page0x2F, Reg0x0C[5 0], REG0_COEF_SEL=[0 0 1 1 1 0]\n\t\trtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0xe);\n\t\t// ##FGCAL read binary\n\t\tfgcal_binary = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 5, 0);\n\n\t\tpr_info(\"%s: fgcal_gray: %d, fgcal_binary %d\\n\",\n\t\t\t__func__, fgcal_gray, fgcal_binary);\n\n\t\toffset_range = rtl9300_sds_field_r(sds_num, 0x2e, 0x15, 15, 14);\n\n\t\tif (fgcal_binary > 60 || fgcal_binary < 3) {\n\t\t\tif (offset_range == 3) {\n\t\t\t\tpr_info(\"%s: Foreground Calibration result marginal!\", __func__);\n\t\t\t\tbreak;\n\t\t\t} else {\n\t\t\t\toffset_range++;\n\t\t\t\trtl9300_sds_field_w(sds_num, 0x2e, 0x15, 15, 14, offset_range);\n\t\t\t\trtl9300_do_rx_calibration_2_2(sds_num);\n\t\t\t}\n\t\t} else {\n\t\t\tbreak;\n\t\t}\n\t}\n\tpr_info(\"%s: end_1.2.3\\n\", __func__);\n}\n\nvoid rtl9300_do_rx_calibration_2(int sds)\n{\n\trtl930x_sds_rx_rst(sds, PHY_INTERFACE_MODE_10GBASER);\n\trtl9300_do_rx_calibration_2_1(sds);\n\trtl9300_do_rx_calibration_2_2(sds);\n\trtl9300_do_rx_calibration_2_3(sds);\n}\n\nvoid rtl9300_sds_rxcal_3_1(int sds_num, phy_interface_t phy_mode)\n{\n\tpr_info(\"start_1.3.1\");\n\n\t// ##1.3.1\n\tif (phy_mode != PHY_INTERFACE_MODE_10GBASER && phy_mode != PHY_INTERFACE_MODE_1000BASEX)\n\t\trtl9300_sds_field_w(sds_num, 0x2e, 0xc, 8, 8, 0);\n\n\trtl9300_sds_field_w(sds_num, 0x2e, 0x17, 7, 7, 0x0);\n\trtl9300_sds_rxcal_leq_manual(sds_num, false, 0);\n\n\tpr_info(\"end_1.3.1\");\n}\n\nvoid rtl9300_sds_rxcal_3_2(int sds_num, phy_interface_t phy_mode)\n{\n\tu32 sum10 = 0, avg10, int10;\n\tint dac_long_cable_offset;\n\tbool eq_hold_enabled;\n\tint i;\n\n\tif (phy_mode == PHY_INTERFACE_MODE_10GBASER || phy_mode == PHY_INTERFACE_MODE_1000BASEX) {\n\t\t// rtl9300_rxCaliConf_serdes_myParam\n\t\tdac_long_cable_offset = 3;\n\t\teq_hold_enabled = true;\n\t} else {\n\t\t// rtl9300_rxCaliConf_phy_myParam\n\t\tdac_long_cable_offset = 0;\n\t\teq_hold_enabled = false;\n\t}\n\n\tif (phy_mode == PHY_INTERFACE_MODE_1000BASEX)\n\t\tpr_warn(\"%s: LEQ only valid for 10GR!\\n\", __func__);\n\n\tpr_info(\"start_1.3.2\");\n\n\tfor(i = 0; i < 10; i++) {\n\t\tsum10 += rtl9300_sds_rxcal_leq_read(sds_num);\n\t\tmdelay(10);\n\t}\n\n\tavg10 = (sum10 / 10) + (((sum10 % 10) >= 5) ? 1 : 0);\n\tint10 = sum10 / 10;\n\n\tpr_info(\"sum10:%u, avg10:%u, int10:%u\", sum10, avg10, int10);\n\n\tif (phy_mode == PHY_INTERFACE_MODE_10GBASER || phy_mode == PHY_INTERFACE_MODE_1000BASEX) {\n\t\tif (dac_long_cable_offset) {\n\t\t\trtl9300_sds_rxcal_leq_offset_manual(sds_num, 1, dac_long_cable_offset);\n\t\t\trtl9300_sds_field_w(sds_num, 0x2e, 0x17, 7, 7, eq_hold_enabled);\n\t\t\tif (phy_mode == PHY_INTERFACE_MODE_10GBASER)\n\t\t\t\trtl9300_sds_rxcal_leq_manual(sds_num, true, avg10);\n\t\t} else {\n\t\t\tif (sum10 >= 5) {\n\t\t\t\trtl9300_sds_rxcal_leq_offset_manual(sds_num, 1, 3);\n\t\t\t\trtl9300_sds_field_w(sds_num, 0x2e, 0x17, 7, 7, 0x1);\n\t\t\t\tif (phy_mode == PHY_INTERFACE_MODE_10GBASER)\n\t\t\t\t\trtl9300_sds_rxcal_leq_manual(sds_num, true, avg10);\n\t\t\t} else {\n\t\t\t\trtl9300_sds_rxcal_leq_offset_manual(sds_num, 1, 0);\n\t\t\t\trtl9300_sds_field_w(sds_num, 0x2e, 0x17, 7, 7, 0x1);\n\t\t\t\tif (phy_mode == PHY_INTERFACE_MODE_10GBASER)\n\t\t\t\t\trtl9300_sds_rxcal_leq_manual(sds_num, true, avg10);\n\t\t\t}\n\t\t}\n\t}\n\n\tpr_info(\"Sds:%u LEQ = %u\",sds_num, rtl9300_sds_rxcal_leq_read(sds_num));\n\n\tpr_info(\"end_1.3.2\");\n}\n\nvoid rtl9300_do_rx_calibration_3(int sds_num, phy_interface_t phy_mode)\n{\n\trtl9300_sds_rxcal_3_1(sds_num, phy_mode);\n\n\tif (phy_mode == PHY_INTERFACE_MODE_10GBASER || phy_mode == PHY_INTERFACE_MODE_1000BASEX)\n\t\trtl9300_sds_rxcal_3_2(sds_num, phy_mode);\n}\n\nvoid rtl9300_do_rx_calibration_4_1(int sds_num)\n{\n\tu32 vth_list[2] = {0, 0};\n\tu32 tap0_list[4] = {0, 0, 0, 0};\n\n\tpr_info(\"start_1.4.1\");\n\n\t// ##1.4.1\n\trtl9300_sds_rxcal_vth_manual(sds_num, false, vth_list);\n\trtl9300_sds_rxcal_tap_manual(sds_num, 0, false, tap0_list);\n\tmdelay(200);\n\n\tpr_info(\"end_1.4.1\");\n}\n\nvoid rtl9300_do_rx_calibration_4_2(u32 sds_num)\n{\n\tu32 vth_list[2];\n\tu32 tap_list[4];\n\n\tpr_info(\"start_1.4.2\");\n\n\trtl9300_sds_rxcal_vth_get(sds_num, vth_list);\n\trtl9300_sds_rxcal_vth_manual(sds_num, true, vth_list);\n\n\tmdelay(100);\n\n\trtl9300_sds_rxcal_tap_get(sds_num, 0, tap_list);\n\trtl9300_sds_rxcal_tap_manual(sds_num, 0, true, tap_list);\n\n\tpr_info(\"end_1.4.2\");\n}\n\nvoid rtl9300_do_rx_calibration_4(u32 sds_num)\n{\n\trtl9300_do_rx_calibration_4_1(sds_num);\n\trtl9300_do_rx_calibration_4_2(sds_num);\n}\n\nvoid rtl9300_do_rx_calibration_5_2(u32 sds_num)\n{\n\tu32 tap1_list[4] = {0};\n\tu32 tap2_list[4] = {0};\n\tu32 tap3_list[4] = {0};\n\tu32 tap4_list[4] = {0};\n\n\tpr_info(\"start_1.5.2\");\n\n\trtl9300_sds_rxcal_tap_manual(sds_num, 1, false, tap1_list);\n\trtl9300_sds_rxcal_tap_manual(sds_num, 2, false, tap2_list);\n\trtl9300_sds_rxcal_tap_manual(sds_num, 3, false, tap3_list);\n\trtl9300_sds_rxcal_tap_manual(sds_num, 4, false, tap4_list);\n\n\tmdelay(30);\n\n\tpr_info(\"end_1.5.2\");\n}\n\nvoid rtl9300_do_rx_calibration_5(u32 sds_num, phy_interface_t phy_mode)\n{\n\tif (phy_mode == PHY_INTERFACE_MODE_10GBASER) // dfeTap1_4Enable true\n\t\trtl9300_do_rx_calibration_5_2(sds_num);\n}\n\n\nvoid rtl9300_do_rx_calibration_dfe_disable(u32 sds_num)\n{\n\tu32 tap1_list[4] = {0};\n\tu32 tap2_list[4] = {0};\n\tu32 tap3_list[4] = {0};\n\tu32 tap4_list[4] = {0};\n\n\trtl9300_sds_rxcal_tap_manual(sds_num, 1, true, tap1_list);\n\trtl9300_sds_rxcal_tap_manual(sds_num, 2, true, tap2_list);\n\trtl9300_sds_rxcal_tap_manual(sds_num, 3, true, tap3_list);\n\trtl9300_sds_rxcal_tap_manual(sds_num, 4, true, tap4_list);\n\n\tmdelay(10);\n}\n\nvoid rtl9300_do_rx_calibration(int sds, phy_interface_t phy_mode)\n{\n\tu32 latch_sts;\n\n\trtl9300_do_rx_calibration_1(sds, phy_mode);\n\trtl9300_do_rx_calibration_2(sds);\n\trtl9300_do_rx_calibration_4(sds);\n\trtl9300_do_rx_calibration_5(sds, phy_mode);\n\tmdelay(20);\n\n\t// Do this only for 10GR mode, SDS active in mode 0x1a\n\tif (rtl9300_sds_field_r(sds, 0x1f, 9, 11, 7) == 0x1a) {\n\t\tpr_info(\"%s: SDS enabled\\n\", __func__);\n\t\tlatch_sts = rtl9300_sds_field_r(sds, 0x4, 1, 2, 2);\n\t\tmdelay(1);\n\t\tlatch_sts = rtl9300_sds_field_r(sds, 0x4, 1, 2, 2);\n\t\tif (latch_sts) {\n\t\t\trtl9300_do_rx_calibration_dfe_disable(sds);\n\t\t\trtl9300_do_rx_calibration_4(sds);\n\t\t\trtl9300_do_rx_calibration_5(sds, phy_mode);\n\t\t}\n\t}\n}\n\nint rtl9300_sds_sym_err_reset(int sds_num, phy_interface_t phy_mode)\n{\n\tswitch (phy_mode) {\n\tcase PHY_INTERFACE_MODE_XGMII:\n\t\tbreak;\n\n\tcase PHY_INTERFACE_MODE_10GBASER:\n\t\t// Read twice to clear\n\t\trtl930x_read_sds_phy(sds_num, 5, 1);\n\t\trtl930x_read_sds_phy(sds_num, 5, 1);\n\t\tbreak;\n\n\tcase PHY_INTERFACE_MODE_1000BASEX:\n\t\trtl9300_sds_field_w(sds_num, 0x1, 24, 2, 0, 0);\n\t\trtl9300_sds_field_w(sds_num, 0x1, 3, 15, 8, 0);\n\t\trtl9300_sds_field_w(sds_num, 0x1, 2, 15, 0, 0);\n\t\tbreak;\n\n\tdefault:\n\t\tpr_info(\"%s unsupported phy mode\\n\", __func__);\n\t\treturn -1;\n\t}\n\n\treturn 0;\n}\n\nu32 rtl9300_sds_sym_err_get(int sds_num, phy_interface_t phy_mode)\n{\n\tu32 v = 0;\n\n\tswitch (phy_mode) {\n\tcase PHY_INTERFACE_MODE_XGMII:\n\t\tbreak;\n\n\tcase PHY_INTERFACE_MODE_10GBASER:\n\t\tv = rtl930x_read_sds_phy(sds_num, 5, 1);\n\t\treturn v & 0xff;\n\n\tdefault:\n\t\tpr_info(\"%s unsupported PHY-mode\\n\", __func__);\n\t}\n\n\treturn v;\n}\n\nint rtl9300_sds_check_calibration(int sds_num, phy_interface_t phy_mode)\n{\n\tu32 errors1, errors2;\n\n\trtl9300_sds_sym_err_reset(sds_num, phy_mode);\n\trtl9300_sds_sym_err_reset(sds_num, phy_mode);\n\n\t// Count errors during 1ms\n\terrors1 = rtl9300_sds_sym_err_get(sds_num, phy_mode);\n\tmdelay(1);\n\terrors2 = rtl9300_sds_sym_err_get(sds_num, phy_mode);\n\n\tswitch (phy_mode) {\n\t\tcase PHY_INTERFACE_MODE_XGMII:\n\n\t\t\tif ((errors2 - errors1 > 100)\n\t\t\t    || (errors1 >= 0xffff00) || (errors2 >= 0xffff00)) {\n\t\t\t\tpr_info(\"%s XSGMII error rate too high\\n\", __func__);\n\t\t\t\treturn 1;\n\t\t\t}\n\t\t\tbreak;\n\t\tcase PHY_INTERFACE_MODE_10GBASER:\n\t\t\tif (errors2 > 0) {\n\t\t\t\tpr_info(\"%s 10GBASER error rate too high\\n\", __func__);\n\t\t\t\treturn 1;\n\t\t\t}\n\t\t\tbreak;\n\t\tdefault:\n\t\t\treturn 1;\n\t}\n\treturn 0;\n}\n\nvoid rtl9300_phy_enable_10g_1g(int sds_num)\n{\n\tu32 v;\n\n\t// Enable 1GBit PHY\n\tv = rtl930x_read_sds_phy(sds_num, PHY_PAGE_2, PHY_CTRL_REG);\n\tpr_info(\"%s 1gbit phy: %08x\\n\", __func__, v);\n\tv &= ~BIT(PHY_POWER_BIT);\n\trtl930x_write_sds_phy(sds_num, PHY_PAGE_2, PHY_CTRL_REG, v);\n\tpr_info(\"%s 1gbit phy enabled: %08x\\n\", __func__, v);\n\n\t// Enable 10GBit PHY\n\tv = rtl930x_read_sds_phy(sds_num, PHY_PAGE_4, PHY_CTRL_REG);\n\tpr_info(\"%s 10gbit phy: %08x\\n\", __func__, v);\n\tv &= ~BIT(PHY_POWER_BIT);\n\trtl930x_write_sds_phy(sds_num, PHY_PAGE_4, PHY_CTRL_REG, v);\n\tpr_info(\"%s 10gbit phy after: %08x\\n\", __func__, v);\n\n\t// dal_longan_construct_mac_default_10gmedia_fiber\n\tv = rtl930x_read_sds_phy(sds_num, 0x1f, 11);\n\tpr_info(\"%s set medium: %08x\\n\", __func__, v);\n\tv |= BIT(1);\n\trtl930x_write_sds_phy(sds_num, 0x1f, 11, v);\n\tpr_info(\"%s set medium after: %08x\\n\", __func__, v);\n}\n\n#define RTL930X_MAC_FORCE_MODE_CTRL\t\t(0xCA1C)\n// phy_mode = PHY_INTERFACE_MODE_10GBASER, sds_mode = 0x1a\nint rtl9300_serdes_setup(int sds_num, phy_interface_t phy_mode)\n{\n\tint sds_mode;\n\tint calib_tries = 0;\n\n\tswitch (phy_mode) {\n\tcase PHY_INTERFACE_MODE_HSGMII:\n\t\tsds_mode = 0x12;\n\t\tbreak;\n\tcase PHY_INTERFACE_MODE_1000BASEX:\n\t\tsds_mode = 0x04;\n\t\tbreak;\n\tcase PHY_INTERFACE_MODE_XGMII:\n\t\tsds_mode = 0x10;\n\t\tbreak;\n\tcase PHY_INTERFACE_MODE_10GBASER:\n\t\tsds_mode = 0x1a;\n\t\tbreak;\n\tcase PHY_INTERFACE_MODE_USXGMII:\n\t\tsds_mode = 0x0d;\n\t\tbreak;\n\tdefault:\n\t\tpr_err(\"%s: unknown serdes mode: %s\\n\", __func__, phy_modes(phy_mode));\n\t\treturn -EINVAL;\n\t}\n\n\t// Maybe use dal_longan_sds_init\n\n\t// dal_longan_construct_serdesConfig_init\t\t// Serdes Construct\n\trtl9300_phy_enable_10g_1g(sds_num);\n\n\t// Set Serdes Mode\n\trtl9300_sds_set(sds_num, 0x1a);\t // 0x1b: RTK_MII_10GR1000BX_AUTO\n\n\t// Do RX calibration\n\tdo {\n\t\trtl9300_do_rx_calibration(sds_num, phy_mode);\n\t\tcalib_tries++;\n\t\tmdelay(50);\n\t} while (rtl9300_sds_check_calibration(sds_num, phy_mode) && calib_tries < 3);\n\n\n\treturn 0;\n}\n\ntypedef struct {\n\tu8 page;\n\tu8 reg;\n\tu16 data;\n} sds_config;\n\nsds_config rtl9300_a_sds_10gr_lane0[] =\n{\n\t/*1G*/\n\t{0x00, 0x0E, 0x3053}, {0x01, 0x14, 0x0100}, {0x21, 0x03, 0x8206},\n\t{0x21, 0x05, 0x40B0}, {0x21, 0x06, 0x0010}, {0x21, 0x07, 0xF09F},\n\t{0x21, 0x0C, 0x0007}, {0x21, 0x0D, 0x6009}, {0x21, 0x0E, 0x0000},\n\t{0x21, 0x0F, 0x0008}, {0x24, 0x00, 0x0668}, {0x24, 0x02, 0xD020},\n\t{0x24, 0x06, 0xC000}, {0x24, 0x0B, 0x1892}, {0x24, 0x0F, 0xFFDF},\n\t{0x24, 0x12, 0x03C4}, {0x24, 0x13, 0x027F}, {0x24, 0x14, 0x1311},\n\t{0x24, 0x16, 0x00C9}, {0x24, 0x17, 0xA100}, {0x24, 0x1A, 0x0001},\n\t{0x24, 0x1C, 0x0400}, {0x25, 0x01, 0x0300}, {0x25, 0x02, 0x1017},\n\t{0x25, 0x03, 0xFFDF}, {0x25, 0x05, 0x7F7C}, {0x25, 0x07, 0x8100},\n\t{0x25, 0x08, 0x0001}, {0x25, 0x09, 0xFFD4}, {0x25, 0x0A, 0x7C2F},\n\t{0x25, 0x0E, 0x003F}, {0x25, 0x0F, 0x0121}, {0x25, 0x10, 0x0020},\n\t{0x25, 0x11, 0x8840}, {0x2B, 0x13, 0x0050}, {0x2B, 0x18, 0x8E88},\n\t{0x2B, 0x19, 0x4902}, {0x2B, 0x1D, 0x2501}, {0x2D, 0x13, 0x0050},\n\t{0x2D, 0x18, 0x8E88}, {0x2D, 0x19, 0x4902}, {0x2D, 0x1D, 0x2641},\n\t{0x2F, 0x13, 0x0050}, {0x2F, 0x18, 0x8E88}, {0x2F, 0x19, 0x4902},\n\t{0x2F, 0x1D, 0x66E1},\n\t/*3.125G*/\n\t{0x28, 0x00, 0x0668}, {0x28, 0x02, 0xD020}, {0x28, 0x06, 0xC000},\n\t{0x28, 0x0B, 0x1892}, {0x28, 0x0F, 0xFFDF}, {0x28, 0x12, 0x01C4},\n\t{0x28, 0x13, 0x027F}, {0x28, 0x14, 0x1311}, {0x28, 0x16, 0x00C9},\n\t{0x28, 0x17, 0xA100}, {0x28, 0x1A, 0x0001}, {0x28, 0x1C, 0x0400},\n\t{0x29, 0x01, 0x0300}, {0x29, 0x02, 0x1017}, {0x29, 0x03, 0xFFDF},\n\t{0x29, 0x05, 0x7F7C}, {0x29, 0x07, 0x8100}, {0x29, 0x08, 0x0001},\n\t{0x29, 0x09, 0xFFD4}, {0x29, 0x0A, 0x7C2F}, {0x29, 0x0E, 0x003F},\n\t{0x29, 0x0F, 0x0121}, {0x29, 0x10, 0x0020}, {0x29, 0x11, 0x8840},\n\t/*10G*/\n\t{0x06, 0x0D, 0x0F00}, {0x06, 0x00, 0x0000}, {0x06, 0x01, 0xC800},\n\t{0x21, 0x03, 0x8206}, {0x21, 0x05, 0x40B0}, {0x21, 0x06, 0x0010},\n\t{0x21, 0x07, 0xF09F}, {0x21, 0x0C, 0x0007}, {0x21, 0x0D, 0x6009},\n\t{0x21, 0x0E, 0x0000}, {0x21, 0x0F, 0x0008}, {0x2E, 0x00, 0xA668},\n\t{0x2E, 0x02, 0xD020}, {0x2E, 0x06, 0xC000}, {0x2E, 0x0B, 0x1892},\n\t{0x2E, 0x0F, 0xFFDF}, {0x2E, 0x11, 0x8280}, {0x2E, 0x12, 0x0044},\n\t{0x2E, 0x13, 0x027F}, {0x2E, 0x14, 0x1311}, {0x2E, 0x17, 0xA100},\n\t{0x2E, 0x1A, 0x0001}, {0x2E, 0x1C, 0x0400}, {0x2F, 0x01, 0x0300},\n\t{0x2F, 0x02, 0x1217}, {0x2F, 0x03, 0xFFDF}, {0x2F, 0x05, 0x7F7C},\n\t{0x2F, 0x07, 0x80C4}, {0x2F, 0x08, 0x0001}, {0x2F, 0x09, 0xFFD4},\n\t{0x2F, 0x0A, 0x7C2F}, {0x2F, 0x0E, 0x003F}, {0x2F, 0x0F, 0x0121},\n\t{0x2F, 0x10, 0x0020}, {0x2F, 0x11, 0x8840}, {0x2F, 0x14, 0xE008},\n\t{0x2B, 0x13, 0x0050}, {0x2B, 0x18, 0x8E88}, {0x2B, 0x19, 0x4902},\n\t{0x2B, 0x1D, 0x2501}, {0x2D, 0x13, 0x0050}, {0x2D, 0x17, 0x4109},\n\t{0x2D, 0x18, 0x8E88}, {0x2D, 0x19, 0x4902}, {0x2D, 0x1C, 0x1109},\n\t{0x2D, 0x1D, 0x2641}, {0x2F, 0x13, 0x0050}, {0x2F, 0x18, 0x8E88},\n\t{0x2F, 0x19, 0x4902}, {0x2F, 0x1D, 0x76E1},\n};\n\nsds_config rtl9300_a_sds_10gr_lane1[] =\n{\n\t/*1G*/\n\t{0x00, 0x0E, 0x3053}, {0x01, 0x14, 0x0100}, {0x21, 0x03, 0x8206},\n\t{0x21, 0x06, 0x0010}, {0x21, 0x07, 0xF09F}, {0x21, 0x0A, 0x0003},\n\t{0x21, 0x0B, 0x0005}, {0x21, 0x0C, 0x0007}, {0x21, 0x0D, 0x6009},\n\t{0x21, 0x0E, 0x0000}, {0x21, 0x0F, 0x0008}, {0x24, 0x00, 0x0668},\n\t{0x24, 0x02, 0xD020}, {0x24, 0x06, 0xC000}, {0x24, 0x0B, 0x1892},\n\t{0x24, 0x0F, 0xFFDF}, {0x24, 0x12, 0x03C4}, {0x24, 0x13, 0x027F},\n\t{0x24, 0x14, 0x1311}, {0x24, 0x16, 0x00C9}, {0x24, 0x17, 0xA100},\n\t{0x24, 0x1A, 0x0001}, {0x24, 0x1C, 0x0400}, {0x25, 0x00, 0x820F},\n\t{0x25, 0x01, 0x0300}, {0x25, 0x02, 0x1017}, {0x25, 0x03, 0xFFDF},\n\t{0x25, 0x05, 0x7F7C}, {0x25, 0x07, 0x8100}, {0x25, 0x08, 0x0001},\n\t{0x25, 0x09, 0xFFD4}, {0x25, 0x0A, 0x7C2F}, {0x25, 0x0E, 0x003F},\n\t{0x25, 0x0F, 0x0121}, {0x25, 0x10, 0x0020}, {0x25, 0x11, 0x8840},\n\t{0x2B, 0x13, 0x3D87}, {0x2B, 0x14, 0x3108}, {0x2D, 0x13, 0x3C87},\n\t{0x2D, 0x14, 0x1808},\n\t/*3.125G*/\n\t{0x28, 0x00, 0x0668}, {0x28, 0x02, 0xD020}, {0x28, 0x06, 0xC000},\n\t{0x28, 0x0B, 0x1892}, {0x28, 0x0F, 0xFFDF}, {0x28, 0x12, 0x01C4},\n\t{0x28, 0x13, 0x027F}, {0x28, 0x14, 0x1311}, {0x28, 0x16, 0x00C9},\n\t{0x28, 0x17, 0xA100}, {0x28, 0x1A, 0x0001}, {0x28, 0x1C, 0x0400},\n\t{0x29, 0x00, 0x820F}, {0x29, 0x01, 0x0300}, {0x29, 0x02, 0x1017},\n\t{0x29, 0x03, 0xFFDF}, {0x29, 0x05, 0x7F7C}, {0x29, 0x07, 0x8100},\n\t{0x29, 0x08, 0x0001}, {0x29, 0x0A, 0x7C2F}, {0x29, 0x0E, 0x003F},\n\t{0x29, 0x0F, 0x0121}, {0x29, 0x10, 0x0020}, {0x29, 0x11, 0x8840},\n\t/*10G*/\n\t{0x06, 0x0D, 0x0F00}, {0x06, 0x00, 0x0000}, {0x06, 0x01, 0xC800},\n\t{0x21, 0x03, 0x8206}, {0x21, 0x05, 0x40B0}, {0x21, 0x06, 0x0010},\n\t{0x21, 0x07, 0xF09F}, {0x21, 0x0A, 0x0003}, {0x21, 0x0B, 0x0005},\n\t{0x21, 0x0C, 0x0007}, {0x21, 0x0D, 0x6009}, {0x21, 0x0E, 0x0000},\n\t{0x21, 0x0F, 0x0008}, {0x2E, 0x00, 0xA668}, {0x2E, 0x02, 0xD020},\n\t{0x2E, 0x06, 0xC000}, {0x2E, 0x0B, 0x1892}, {0x2E, 0x0F, 0xFFDF},\n\t{0x2E, 0x11, 0x8280}, {0x2E, 0x12, 0x0044}, {0x2E, 0x13, 0x027F},\n\t{0x2E, 0x14, 0x1311}, {0x2E, 0x17, 0xA100}, {0x2E, 0x1A, 0x0001},\n\t{0x2E, 0x1C, 0x0400}, {0x2F, 0x00, 0x820F}, {0x2F, 0x01, 0x0300},\n\t{0x2F, 0x02, 0x1217}, {0x2F, 0x03, 0xFFDF}, {0x2F, 0x05, 0x7F7C},\n\t{0x2F, 0x07, 0x80C4}, {0x2F, 0x08, 0x0001}, {0x2F, 0x09, 0xFFD4},\n\t{0x2F, 0x0A, 0x7C2F}, {0x2F, 0x0E, 0x003F}, {0x2F, 0x0F, 0x0121},\n\t{0x2F, 0x10, 0x0020}, {0x2F, 0x11, 0x8840}, {0x2B, 0x13, 0x3D87},\n\t{0x2B, 0x14, 0x3108}, {0x2D, 0x13, 0x3C87}, {0x2D, 0x14, 0x1808},\n};\n\nint rtl9300_sds_cmu_band_get(int sds)\n{\n\tu32 page;\n\tu32 en;\n\tu32 cmu_band;\n\n//\tpage = rtl9300_sds_cmu_page_get(sds);\n\tpage = 0x25; // 10GR and 1000BX\n\tsds = (sds % 2) ? (sds - 1) : (sds);\n\n\trtl9300_sds_field_w(sds, page, 0x1c, 15, 15, 1);\n\trtl9300_sds_field_w(sds + 1, page, 0x1c, 15, 15, 1);\n\n\ten = rtl9300_sds_field_r(sds, page, 27, 1, 1);\n\tif(!en) { // Auto mode\n\t\trtl930x_write_sds_phy(sds, 0x1f, 0x02, 31);\n\n\t\tcmu_band = rtl9300_sds_field_r(sds, 0x1f, 0x15, 5, 1);\n\t} else {\n\t\tcmu_band = rtl9300_sds_field_r(sds, page, 30, 4, 0);\n\t}\n\n\treturn cmu_band;\n}\n\nint rtl9300_configure_serdes(struct phy_device *phydev)\n{\n\tstruct device *dev = &phydev->mdio.dev;\n\tint phy_addr = phydev->mdio.addr;\n\tstruct device_node *dn;\n\tu32 sds_num = 0;\n\tint sds_mode, calib_tries = 0, phy_mode = PHY_INTERFACE_MODE_10GBASER, i;\n\n\tif (dev->of_node) {\n\t\tdn = dev->of_node;\n\t\t\n\t\tif (of_property_read_u32(dn, \"sds\", &sds_num))\n\t\t\tsds_num = -1;\n\t\tpr_info(\"%s: Port %d, SerDes is %d\\n\", __func__, phy_addr, sds_num);\n\t} else {\n\t\tdev_err(dev, \"No DT node.\\n\");\n\t\treturn -EINVAL;\n\t}\n\n\tif (sds_num < 0)\n\t\treturn 0;\n\n\tif (phy_mode != PHY_INTERFACE_MODE_10GBASER) // TODO: for now we only patch 10GR SerDes\n\t\treturn 0;\n\n\tswitch (phy_mode) {\n\tcase PHY_INTERFACE_MODE_HSGMII:\n\t\tsds_mode = 0x12;\n\t\tbreak;\n\tcase PHY_INTERFACE_MODE_1000BASEX:\n\t\tsds_mode = 0x04;\n\t\tbreak;\n\tcase PHY_INTERFACE_MODE_XGMII:\n\t\tsds_mode = 0x10;\n\t\tbreak;\n\tcase PHY_INTERFACE_MODE_10GBASER:\n\t\tsds_mode = 0x1a;\n\t\tbreak;\n\tcase PHY_INTERFACE_MODE_USXGMII:\n\t\tsds_mode = 0x0d;\n\t\tbreak;\n\tdefault:\n\t\tpr_err(\"%s: unknown serdes mode: %s\\n\", __func__, phy_modes(phy_mode));\n\t\treturn -EINVAL;\n\t}\n\n\tpr_info(\"%s CMU BAND is %d\\n\", __func__, rtl9300_sds_cmu_band_get(sds_num));\n\n\t// Turn Off Serdes\n\trtl9300_sds_rst(sds_num, 0x1f);\n\n\tpr_info(\"%s PATCHING SerDes %d\\n\", __func__, sds_num);\n\tif (sds_num % 2) {\n\t\tfor (i = 0; i < sizeof(rtl9300_a_sds_10gr_lane1) / sizeof(sds_config); ++i) {\n\t\t\trtl930x_write_sds_phy(sds_num, rtl9300_a_sds_10gr_lane1[i].page,\n\t\t\t\t\t\trtl9300_a_sds_10gr_lane1[i].reg,\n\t\t\t\t\t\trtl9300_a_sds_10gr_lane1[i].data);\n\t\t}\n\t} else {\n\t\tfor (i = 0; i < sizeof(rtl9300_a_sds_10gr_lane0) / sizeof(sds_config); ++i) {\n\t\t\trtl930x_write_sds_phy(sds_num, rtl9300_a_sds_10gr_lane0[i].page,\n\t\t\t\t\t\trtl9300_a_sds_10gr_lane0[i].reg,\n\t\t\t\t\t\trtl9300_a_sds_10gr_lane0[i].data);\n\t\t}\n\t}\n\n\trtl9300_phy_enable_10g_1g(sds_num);\n\n\t// Disable MAC\n\tsw_w32_mask(0, 1, RTL930X_MAC_FORCE_MODE_CTRL);\n\tmdelay(20);\n\n\t// ----> dal_longan_sds_mode_set\n\tpr_info(\"%s: Configuring RTL9300 SERDES %d, mode %02x\\n\", __func__, sds_num, sds_mode);\n\n\t// Configure link to MAC\n\trtl9300_serdes_mac_link_config(sds_num, true, true);\t// MAC Construct\n\n\t// Disable MAC\n\tsw_w32_mask(0, 1, RTL930X_MAC_FORCE_MODE_CTRL);\n\tmdelay(20);\n\n\trtl9300_force_sds_mode(sds_num, PHY_INTERFACE_MODE_NA);\n\n\t// Re-Enable MAC\n\tsw_w32_mask(1, 0, RTL930X_MAC_FORCE_MODE_CTRL);\n\n\trtl9300_force_sds_mode(sds_num, phy_mode);\n\n\t// Do RX calibration\n\tdo {\n\t\trtl9300_do_rx_calibration(sds_num, phy_mode);\n\t\tcalib_tries++;\n\t\tmdelay(50);\n\t} while (rtl9300_sds_check_calibration(sds_num, phy_mode) && calib_tries < 3);\n\n\tif (calib_tries >= 3)\n\t\tpr_err(\"%s CALIBTRATION FAILED\\n\", __func__);\n\n\trtl9300_sds_tx_config(sds_num, phy_mode);\n\n\t// The clock needs only to be configured on the FPGA implementation\n\n\treturn 0;\n}\n\nvoid rtl9310_sds_field_w(int sds, u32 page, u32 reg, int end_bit, int start_bit, u32 v)\n{\n\tint l = end_bit - start_bit + 1;\n\tu32 data = v;\n\n\tif (l < 32) {\n\t\tu32 mask = BIT(l) - 1;\n\n\t\tdata = rtl930x_read_sds_phy(sds, page, reg);\n\t\tdata &= ~(mask << start_bit);\n\t\tdata |= (v & mask) << start_bit;\n\t}\n\n\trtl931x_write_sds_phy(sds, page, reg, data);\n}\n\n\nu32 rtl9310_sds_field_r(int sds, u32 page, u32 reg, int end_bit, int start_bit)\n{\n\tint l = end_bit - start_bit + 1;\n\tu32 v = rtl931x_read_sds_phy(sds, page, reg);\n\n\tif (l >= 32)\n\t\treturn v;\n\n\treturn (v >> start_bit) & (BIT(l) - 1);\n}\n\nstatic void rtl931x_sds_rst(u32 sds)\n{\n\tu32 o, v, o_mode;\n\tint shift = ((sds & 0x3) << 3);\n\n\t// TODO: We need to lock this!\n\t\n\to = sw_r32(RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR);\n\tv = o | BIT(sds);\n\tsw_w32(v, RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR);\n\n\to_mode = sw_r32(RTL931X_SERDES_MODE_CTRL + 4 * (sds >> 2));\n\tv = BIT(7) | 0x1F;\n\tsw_w32_mask(0xff << shift, v << shift, RTL931X_SERDES_MODE_CTRL + 4 * (sds >> 2));\n\tsw_w32(o_mode, RTL931X_SERDES_MODE_CTRL + 4 * (sds >> 2));\n\n\tsw_w32(o, RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR);\n}\n\nstatic void rtl931x_symerr_clear(u32 sds, phy_interface_t mode)\n{\n\tu32 i;\n\tu32 xsg_sdsid_0, xsg_sdsid_1;\n\n\tswitch (mode) {\n\tcase PHY_INTERFACE_MODE_NA:\n\t\tbreak;\n\tcase PHY_INTERFACE_MODE_XGMII:\n\t\tif (sds < 2)\n\t\t\txsg_sdsid_0 = sds;\n\t\telse\n\t\t\txsg_sdsid_0 = (sds - 1) * 2;\n\t\txsg_sdsid_1 = xsg_sdsid_0 + 1;\n\n\t\tfor (i = 0; i < 4; ++i) {\n\t\t\trtl9310_sds_field_w(xsg_sdsid_0, 0x1, 24, 2, 0, i);\n\t\t\trtl9310_sds_field_w(xsg_sdsid_0, 0x1, 3, 15, 8, 0x0);\n\t\t\trtl9310_sds_field_w(xsg_sdsid_0, 0x1, 2, 15, 0, 0x0);\n\t\t}\n\n\t\tfor (i = 0; i < 4; ++i) {\n\t\t\trtl9310_sds_field_w(xsg_sdsid_1, 0x1, 24, 2, 0, i);\n\t\t\trtl9310_sds_field_w(xsg_sdsid_1, 0x1, 3, 15, 8, 0x0);\n\t\t\trtl9310_sds_field_w(xsg_sdsid_1, 0x1, 2, 15, 0, 0x0);\n\t\t}\n\n\t\trtl9310_sds_field_w(xsg_sdsid_0, 0x1, 0, 15, 0, 0x0);\n\t\trtl9310_sds_field_w(xsg_sdsid_0, 0x1, 1, 15, 8, 0x0);\n\t\trtl9310_sds_field_w(xsg_sdsid_1, 0x1, 0, 15, 0, 0x0);\n\t\trtl9310_sds_field_w(xsg_sdsid_1, 0x1, 1, 15, 8, 0x0);\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\n\treturn;\n}\n\nstatic u32 rtl931x_get_analog_sds(u32 sds)\n{\n\tu32 sds_map[] = { 0, 1, 2, 3, 6, 7, 10, 11, 14, 15, 18, 19, 22, 23 };\n\n\tif (sds < 14)\n\t\treturn sds_map[sds];\n\treturn sds;\n}\n\nvoid rtl931x_sds_fiber_disable(u32 sds)\n{\n\tu32 v = 0x3F;\n\tu32 asds = rtl931x_get_analog_sds(sds);\n\n\trtl9310_sds_field_w(asds, 0x1F, 0x9, 11, 6, v);\n}\n\nstatic void rtl931x_sds_fiber_mode_set(u32 sds, phy_interface_t mode)\n{\n\tu32 val, asds = rtl931x_get_analog_sds(sds);\n\n\t/* clear symbol error count before changing mode */\n\trtl931x_symerr_clear(sds, mode);\n\n\tval = 0x9F;\n\tsw_w32(val, RTL931X_SERDES_MODE_CTRL + 4 * (sds >> 2));\n\n\tswitch (mode) {\n\tcase PHY_INTERFACE_MODE_SGMII:\n\t\tval = 0x5;\n\t\tbreak;\n\n\tcase PHY_INTERFACE_MODE_1000BASEX:\n\t\t/* serdes mode FIBER1G */\n\t\tval = 0x9;\n\t\tbreak;\n\n\tcase PHY_INTERFACE_MODE_10GBASER:\n\tcase PHY_INTERFACE_MODE_10GKR:\n\t\tval = 0x35;\n\t\tbreak;\n/*\tcase MII_10GR1000BX_AUTO:\n\t\tval = 0x39;\n\t\tbreak; */\n\n\n\tcase PHY_INTERFACE_MODE_USXGMII:\n\t\tval = 0x1B;\n\t\tbreak;\n\tdefault:\n\t\tval = 0x25;\n\t}\n\n\tpr_info(\"%s writing analog SerDes Mode value %02x\\n\", __func__, val);\n\trtl9310_sds_field_w(asds, 0x1F, 0x9, 11, 6, val);\n\n\treturn;\n}\n\nstatic int rtl931x_sds_cmu_page_get(phy_interface_t mode)\n{\n\tswitch (mode) {\n\tcase PHY_INTERFACE_MODE_SGMII:\n\tcase PHY_INTERFACE_MODE_1000BASEX:\t// MII_1000BX_FIBER / 100BX_FIBER / 1000BX100BX_AUTO\n\t\treturn 0x24;\n\tcase PHY_INTERFACE_MODE_HSGMII:\n\tcase PHY_INTERFACE_MODE_2500BASEX:\t// MII_2500Base_X:\n\t\treturn 0x28;\n//\tcase MII_HISGMII_5G:\n//\t\treturn 0x2a;\n\tcase PHY_INTERFACE_MODE_QSGMII:\n\t\treturn 0x2a;\t\t\t// Code also has 0x34\n\tcase PHY_INTERFACE_MODE_XAUI:\t\t// MII_RXAUI_LITE:\n\t\treturn 0x2c;\n\tcase PHY_INTERFACE_MODE_XGMII:\t\t// MII_XSGMII\n\tcase PHY_INTERFACE_MODE_10GKR:\n\tcase PHY_INTERFACE_MODE_10GBASER:\t// MII_10GR\n\t\treturn 0x2e;\n\tdefault:\n\t\treturn -1;\n\t}\n\treturn -1;\n}\n\nstatic void rtl931x_cmu_type_set(u32 asds, phy_interface_t mode, int chiptype)\n{\n\tint cmu_type = 0; // Clock Management Unit\n\tu32 cmu_page = 0;\n\tu32 frc_cmu_spd;\n\tu32 evenSds;\n\tu32 lane, frc_lc_mode_bitnum, frc_lc_mode_val_bitnum;\n\n\tswitch (mode) {\n\tcase PHY_INTERFACE_MODE_NA:\n\tcase PHY_INTERFACE_MODE_10GKR:\n\tcase PHY_INTERFACE_MODE_XGMII:\n\tcase PHY_INTERFACE_MODE_10GBASER:\n\tcase PHY_INTERFACE_MODE_USXGMII:\n\t\treturn;\n\n/*\tcase MII_10GR1000BX_AUTO:\n\t\tif (chiptype)\n\t\t\trtl9310_sds_field_w(asds, 0x24, 0xd, 14, 14, 0);\n\t\treturn; */\n\n\tcase PHY_INTERFACE_MODE_QSGMII:\n\t\tcmu_type = 1;\n\t\tfrc_cmu_spd = 0;\n\t\tbreak;\n\n\tcase PHY_INTERFACE_MODE_HSGMII:\n\t\tcmu_type = 1;\n\t\tfrc_cmu_spd = 1;\n\t\tbreak;\n\n\tcase PHY_INTERFACE_MODE_1000BASEX:\n\t\tcmu_type = 1;\n\t\tfrc_cmu_spd = 0;\n\t\tbreak;\n\n/*\tcase MII_1000BX100BX_AUTO:\n\t\tcmu_type = 1;\n\t\tfrc_cmu_spd = 0;\n\t\tbreak; */\n\n\tcase PHY_INTERFACE_MODE_SGMII:\n\t\tcmu_type = 1;\n\t\tfrc_cmu_spd = 0;\n\t\tbreak;\n\n\tcase PHY_INTERFACE_MODE_2500BASEX:\n\t\tcmu_type = 1;\n\t\tfrc_cmu_spd = 1;\n\t\tbreak;\n\n\tdefault:\n\t\tpr_info(\"SerDes %d mode is invalid\\n\", asds);\n\t\treturn;\n\t}\n\n\tif (cmu_type == 1)\n\t\tcmu_page = rtl931x_sds_cmu_page_get(mode);\n\n\tlane = asds % 2;\n\n\tif (!lane) {\n\t\tfrc_lc_mode_bitnum = 4;\n\t\tfrc_lc_mode_val_bitnum = 5;\n\t} else {\n\t\tfrc_lc_mode_bitnum = 6;\n\t\tfrc_lc_mode_val_bitnum = 7;\n\t}\n\n\tevenSds = asds - lane;\n\n\tpr_info(\"%s: cmu_type %0d cmu_page %x frc_cmu_spd %d lane %d asds %d\\n\",\n\t\t__func__, cmu_type, cmu_page, frc_cmu_spd, lane, asds);\n\n\tif (cmu_type == 1) {\n\t\tpr_info(\"%s A CMU page 0x28 0x7 %08x\\n\", __func__, rtl931x_read_sds_phy(asds, 0x28, 0x7));\n\t\trtl9310_sds_field_w(asds, cmu_page, 0x7, 15, 15, 0);\n\t\tpr_info(\"%s B CMU page 0x28 0x7 %08x\\n\", __func__, rtl931x_read_sds_phy(asds, 0x28, 0x7));\n\t\tif (chiptype) {\n\t\t\trtl9310_sds_field_w(asds, cmu_page, 0xd, 14, 14, 0);\n\t\t}\n\n\t\trtl9310_sds_field_w(evenSds, 0x20, 0x12, 3, 2, 0x3);\n\t\trtl9310_sds_field_w(evenSds, 0x20, 0x12, frc_lc_mode_bitnum, frc_lc_mode_bitnum, 1);\n\t\trtl9310_sds_field_w(evenSds, 0x20, 0x12, frc_lc_mode_val_bitnum, frc_lc_mode_val_bitnum, 0);\n\t\trtl9310_sds_field_w(evenSds, 0x20, 0x12, 12, 12, 1);\n\t\trtl9310_sds_field_w(evenSds, 0x20, 0x12, 15, 13, frc_cmu_spd);\n\t}\n\n\tpr_info(\"%s CMU page 0x28 0x7 %08x\\n\", __func__, rtl931x_read_sds_phy(asds, 0x28, 0x7));\n\treturn;\n}\n\nstatic void rtl931x_sds_rx_rst(u32 sds)\n{\n\tu32 asds = rtl931x_get_analog_sds(sds);\n\n\tif (sds < 2)\n\t\treturn;\n\n\trtl931x_write_sds_phy(asds, 0x2e, 0x12, 0x2740);\n\trtl931x_write_sds_phy(asds, 0x2f, 0x0, 0x0);\n\trtl931x_write_sds_phy(asds, 0x2f, 0x2, 0x2010);\n\trtl931x_write_sds_phy(asds, 0x20, 0x0, 0xc10);\n\n\trtl931x_write_sds_phy(asds, 0x2e, 0x12, 0x27c0);\n\trtl931x_write_sds_phy(asds, 0x2f, 0x0, 0xc000);\n\trtl931x_write_sds_phy(asds, 0x2f, 0x2, 0x6010);\n\trtl931x_write_sds_phy(asds, 0x20, 0x0, 0xc30);\n\n\tmdelay(50);\n}\n\nstatic void rtl931x_sds_disable(u32 sds)\n{\n\tu32 v = 0x1f;\n\n\tv |= BIT(7);\n\tsw_w32(v, RTL931X_SERDES_MODE_CTRL + (sds >> 2) * 4);\n}\n\nstatic void rtl931x_sds_mii_mode_set(u32 sds, phy_interface_t mode)\n{\n\tu32 val;\n\n\tswitch (mode) {\n\tcase PHY_INTERFACE_MODE_QSGMII:\n\t\tval = 0x6;\n\t\tbreak;\n\tcase PHY_INTERFACE_MODE_XGMII:\n\t\tval = 0x10; // serdes mode XSGMII\n\t\tbreak;\n\tcase PHY_INTERFACE_MODE_USXGMII:\n\tcase PHY_INTERFACE_MODE_2500BASEX:\n\t\tval = 0xD;\n\t\tbreak;\n\tcase PHY_INTERFACE_MODE_HSGMII:\n\t\tval = 0x12;\n\t\tbreak;\n\tcase PHY_INTERFACE_MODE_SGMII:\n\t\tval = 0x2;\n\t\tbreak;\n\tdefault:\n\t\treturn;\n\t}\n\n\tval |= (1 << 7);\n\n\tsw_w32(val, RTL931X_SERDES_MODE_CTRL + 4 * (sds >> 2));\n}\n\nstatic sds_config sds_config_10p3125g_type1[] = {\n\t{ 0x2E, 0x00, 0x0107 }, { 0x2E, 0x01, 0x01A3 }, { 0x2E, 0x02, 0x6A24 },\n\t{ 0x2E, 0x03, 0xD10D }, { 0x2E, 0x04, 0x8000 }, { 0x2E, 0x05, 0xA17E },\n\t{ 0x2E, 0x06, 0xE31D }, { 0x2E, 0x07, 0x800E }, { 0x2E, 0x08, 0x0294 },\n\t{ 0x2E, 0x09, 0x0CE4 }, { 0x2E, 0x0A, 0x7FC8 }, { 0x2E, 0x0B, 0xE0E7 },\n\t{ 0x2E, 0x0C, 0x0200 }, { 0x2E, 0x0D, 0xDF80 }, { 0x2E, 0x0E, 0x0000 },\n\t{ 0x2E, 0x0F, 0x1FC2 }, { 0x2E, 0x10, 0x0C3F }, { 0x2E, 0x11, 0x0000 },\n\t{ 0x2E, 0x12, 0x27C0 }, { 0x2E, 0x13, 0x7E1D }, { 0x2E, 0x14, 0x1300 },\n\t{ 0x2E, 0x15, 0x003F }, { 0x2E, 0x16, 0xBE7F }, { 0x2E, 0x17, 0x0090 },\n\t{ 0x2E, 0x18, 0x0000 }, { 0x2E, 0x19, 0x4000 }, { 0x2E, 0x1A, 0x0000 },\n\t{ 0x2E, 0x1B, 0x8000 }, { 0x2E, 0x1C, 0x011F }, { 0x2E, 0x1D, 0x0000 },\n\t{ 0x2E, 0x1E, 0xC8FF }, { 0x2E, 0x1F, 0x0000 }, { 0x2F, 0x00, 0xC000 },\n\t{ 0x2F, 0x01, 0xF000 }, { 0x2F, 0x02, 0x6010 }, { 0x2F, 0x12, 0x0EE7 },\n\t{ 0x2F, 0x13, 0x0000 }\n};\n\nstatic sds_config sds_config_10p3125g_cmu_type1[] = {\n\t{ 0x2F, 0x03, 0x4210 }, { 0x2F, 0x04, 0x0000 }, { 0x2F, 0x05, 0x0019 },\n\t{ 0x2F, 0x06, 0x18A6 }, { 0x2F, 0x07, 0x2990 }, { 0x2F, 0x08, 0xFFF4 },\n\t{ 0x2F, 0x09, 0x1F08 }, { 0x2F, 0x0A, 0x0000 }, { 0x2F, 0x0B, 0x8000 },\n\t{ 0x2F, 0x0C, 0x4224 }, { 0x2F, 0x0D, 0x0000 }, { 0x2F, 0x0E, 0x0000 },\n\t{ 0x2F, 0x0F, 0xA470 }, { 0x2F, 0x10, 0x8000 }, { 0x2F, 0x11, 0x037B }\n};\n\nvoid rtl931x_sds_init(u32 sds, phy_interface_t mode)\n{\n\n\tu32 board_sds_tx_type1[] = { 0x1C3, 0x1C3, 0x1C3, 0x1A3, 0x1A3,\n\t\t0x1A3, 0x143, 0x143, 0x143, 0x143, 0x163, 0x163\n\t};\n\n\tu32 board_sds_tx[] = { 0x1A00, 0x1A00, 0x200, 0x200, 0x200,\n\t\t0x200, 0x1A3, 0x1A3, 0x1A3, 0x1A3, 0x1E3, 0x1E3\n\t};\n\n\tu32 board_sds_tx2[] = { 0xDC0, 0x1C0, 0x200, 0x180, 0x160,\n\t\t0x123, 0x123, 0x163, 0x1A3, 0x1A0, 0x1C3, 0x9C3\n\t};\n\n\tu32 asds, dSds, ori, model_info, val;\n\tint chiptype = 0;\n\n\tasds = rtl931x_get_analog_sds(sds);\n\n\tif (sds > 13)\n\t\treturn;\n\n\tpr_info(\"%s: set sds %d to mode %d\\n\", __func__, sds, mode);\n\tval = rtl9310_sds_field_r(asds, 0x1F, 0x9, 11, 6);\n\n\tpr_info(\"%s: fibermode %08X stored mode 0x%x analog SDS %d\", __func__,\n\t\t\trtl931x_read_sds_phy(asds, 0x1f, 0x9), val, asds);\n\tpr_info(\"%s: SGMII mode %08X in 0x24 0x9 analog SDS %d\", __func__,\n\t\t\trtl931x_read_sds_phy(asds, 0x24, 0x9), asds);\n\tpr_info(\"%s: CMU mode %08X stored even SDS %d\", __func__,\n\t\t\trtl931x_read_sds_phy(asds & ~1, 0x20, 0x12), asds & ~1);\n\tpr_info(\"%s: serdes_mode_ctrl %08X\", __func__,  RTL931X_SERDES_MODE_CTRL + 4 * (sds >> 2));\n\tpr_info(\"%s CMU page 0x24 0x7 %08x\\n\", __func__, rtl931x_read_sds_phy(asds, 0x24, 0x7));\n\tpr_info(\"%s CMU page 0x26 0x7 %08x\\n\", __func__, rtl931x_read_sds_phy(asds, 0x26, 0x7));\n\tpr_info(\"%s CMU page 0x28 0x7 %08x\\n\", __func__, rtl931x_read_sds_phy(asds, 0x28, 0x7));\n\tpr_info(\"%s XSG page 0x0 0xe %08x\\n\", __func__, rtl931x_read_sds_phy(dSds, 0x0, 0xe));\n\tpr_info(\"%s XSG2 page 0x0 0xe %08x\\n\", __func__, rtl931x_read_sds_phy(dSds + 1, 0x0, 0xe));\n\n\tmodel_info = sw_r32(RTL93XX_MODEL_NAME_INFO);\n\tif ((model_info >> 4) & 0x1) {\n\t\tpr_info(\"detected chiptype 1\\n\");\n\t\tchiptype = 1;\n\t} else {\n\t\tpr_info(\"detected chiptype 0\\n\");\n\t}\n\n\tif (sds < 2)\n\t\tdSds = sds;\n\telse\n\t\tdSds = (sds - 1) * 2;\n\n\tpr_info(\"%s: 2.5gbit %08X dsds %d\", __func__,\n\t\trtl931x_read_sds_phy(dSds, 0x1, 0x14), dSds);\n\n\tpr_info(\"%s: RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR 0x%08X\\n\", __func__, sw_r32(RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR));\n\tori = sw_r32(RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR);\n\tval = ori | (1 << sds);\n\tsw_w32(val, RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR);\n\n\tswitch (mode) {\n\tcase PHY_INTERFACE_MODE_NA:\n\t\tbreak;\n\n\tcase PHY_INTERFACE_MODE_XGMII: // MII_XSGMII\n\n\t\tif (chiptype) {\n\t\t\tu32 xsg_sdsid_1;\n\t\t\txsg_sdsid_1 = dSds + 1;\n\t\t\t//fifo inv clk\n\t\t\trtl9310_sds_field_w(dSds, 0x1, 0x1, 7, 4, 0xf);\n\t\t\trtl9310_sds_field_w(dSds, 0x1, 0x1, 3, 0, 0xf);\n\n\t\t\trtl9310_sds_field_w(xsg_sdsid_1, 0x1, 0x1, 7, 4, 0xf);\n\t\t\trtl9310_sds_field_w(xsg_sdsid_1, 0x1, 0x1, 3, 0, 0xf);\n\n\t\t}\n\n\t\trtl9310_sds_field_w(dSds, 0x0, 0xE, 12, 12, 1);\n\t\trtl9310_sds_field_w(dSds + 1, 0x0, 0xE, 12, 12, 1);\n\t\tbreak;\n\n\tcase PHY_INTERFACE_MODE_USXGMII: // MII_USXGMII_10GSXGMII/10GDXGMII/10GQXGMII:\n\t\tu32 i, evenSds;\n\t\tu32 op_code = 0x6003;\n\n\t\tif (chiptype) {\n\t\t\trtl9310_sds_field_w(asds, 0x6, 0x2, 12, 12, 1);\n\n\t\t\tfor (i = 0; i < sizeof(sds_config_10p3125g_type1) / sizeof(sds_config); ++i) {\n\t\t\t\trtl931x_write_sds_phy(asds, sds_config_10p3125g_type1[i].page - 0x4, sds_config_10p3125g_type1[i].reg, sds_config_10p3125g_type1[i].data);\n\t\t\t}\n\n\t\t\tevenSds = asds - (asds % 2);\n\n\t\t\tfor (i = 0; i < sizeof(sds_config_10p3125g_cmu_type1) / sizeof(sds_config); ++i) {\n\t\t\t\trtl931x_write_sds_phy(evenSds,\n\t\t\t\t\t\t      sds_config_10p3125g_cmu_type1[i].page - 0x4, sds_config_10p3125g_cmu_type1[i].reg, sds_config_10p3125g_cmu_type1[i].data);\n\t\t\t}\n\n\t\t\trtl9310_sds_field_w(asds, 0x6, 0x2, 12, 12, 0);\n\t\t} else {\n\n\t\t\trtl9310_sds_field_w(asds, 0x2e, 0xd, 6, 0, 0x0);\n\t\t\trtl9310_sds_field_w(asds, 0x2e, 0xd, 7, 7, 0x1);\n\n\t\t\trtl9310_sds_field_w(asds, 0x2e, 0x1c, 5, 0, 0x1E);\n\t\t\trtl9310_sds_field_w(asds, 0x2e, 0x1d, 11, 0, 0x00);\n\t\t\trtl9310_sds_field_w(asds, 0x2e, 0x1f, 11, 0, 0x00);\n\t\t\trtl9310_sds_field_w(asds, 0x2f, 0x0, 11, 0, 0x00);\n\t\t\trtl9310_sds_field_w(asds, 0x2f, 0x1, 11, 0, 0x00);\n\n\t\t\trtl9310_sds_field_w(asds, 0x2e, 0xf, 12, 6, 0x7F);\n\t\t\trtl931x_write_sds_phy(asds, 0x2f, 0x12, 0xaaa);\n\n\t\t\trtl931x_sds_rx_rst(sds);\n\n\t\t\trtl931x_write_sds_phy(asds, 0x7, 0x10, op_code);\n\t\t\trtl931x_write_sds_phy(asds, 0x6, 0x1d, 0x0480);\n\t\t\trtl931x_write_sds_phy(asds, 0x6, 0xe, 0x0400);\n\t\t}\n\t\tbreak;\n\n\tcase PHY_INTERFACE_MODE_10GBASER: // MII_10GR / MII_10GR1000BX_AUTO:\n\t\t// configure 10GR fiber mode=1\n\t\trtl9310_sds_field_w(asds, 0x1f, 0xb, 1, 1, 1);\n\n\t\t// init fiber_1g\n\t\trtl9310_sds_field_w(dSds, 0x3, 0x13, 15, 14, 0);\n\n\t\trtl9310_sds_field_w(dSds, 0x2, 0x0, 12, 12, 1);\n\t\trtl9310_sds_field_w(dSds, 0x2, 0x0, 6, 6, 1);\n\t\trtl9310_sds_field_w(dSds, 0x2, 0x0, 13, 13, 0);\n\n\t\t// init auto\n\t\trtl9310_sds_field_w(asds, 0x1f, 13, 15, 0, 0x109e);\n\t\trtl9310_sds_field_w(asds, 0x1f, 0x6, 14, 10, 0x8);\n\t\trtl9310_sds_field_w(asds, 0x1f, 0x7, 10, 4, 0x7f);\n\t\tbreak;\n\n\tcase PHY_INTERFACE_MODE_HSGMII:\n\t\trtl9310_sds_field_w(dSds, 0x1, 0x14, 8, 8, 1);\n\t\tbreak;\n\n\tcase PHY_INTERFACE_MODE_1000BASEX: // MII_1000BX_FIBER\n\t\trtl9310_sds_field_w(dSds, 0x3, 0x13, 15, 14, 0);\n\n\t\trtl9310_sds_field_w(dSds, 0x2, 0x0, 12, 12, 1);\n\t\trtl9310_sds_field_w(dSds, 0x2, 0x0, 6, 6, 1);\n\t\trtl9310_sds_field_w(dSds, 0x2, 0x0, 13, 13, 0);\n\t\tbreak;\n\n\tcase PHY_INTERFACE_MODE_SGMII:\n\t\trtl9310_sds_field_w(asds, 0x24, 0x9, 15, 15, 0);\n\t\tbreak;\n\n\tcase PHY_INTERFACE_MODE_2500BASEX:\n\t\trtl9310_sds_field_w(dSds, 0x1, 0x14, 8, 8, 1);\n\t\tbreak;\n\n\tcase PHY_INTERFACE_MODE_QSGMII:\n\tdefault:\n\t\tpr_info(\"%s: PHY mode %s not supported by SerDes %d\\n\",\n\t\t\t__func__, phy_modes(mode), sds);\n\t\treturn;\n\t}\n\n\trtl931x_cmu_type_set(asds, mode, chiptype);\n\n\tif (sds >= 2 && sds <= 13) {\n\t\tif (chiptype)\n\t\t\trtl931x_write_sds_phy(asds, 0x2E, 0x1, board_sds_tx_type1[sds - 2]);\n\t\telse {\n\t\t\tval = 0xa0000;\n\t\t\tsw_w32(val, RTL931X_CHIP_INFO_ADDR);\n\t\t\tval = sw_r32(RTL931X_CHIP_INFO_ADDR);\n\t\t\tif (val & BIT(28)) // consider 9311 etc. RTL9313_CHIP_ID == HWP_CHIP_ID(unit))\n\t\t\t{\n\t\t\t\trtl931x_write_sds_phy(asds, 0x2E, 0x1, board_sds_tx2[sds - 2]);\n\t\t\t} else {\n\t\t\t\trtl931x_write_sds_phy(asds, 0x2E, 0x1, board_sds_tx[sds - 2]);\n\t\t\t}\n\t\t\tval = 0;\n\t\t\tsw_w32(val, RTL931X_CHIP_INFO_ADDR);\n\t\t}\n\t}\n\n\tval = ori & ~BIT(sds);\n\tsw_w32(val, RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR);\n\tpr_debug(\"%s: RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR 0x%08X\\n\", __func__, sw_r32(RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR));\n\n\tif (mode == PHY_INTERFACE_MODE_XGMII || mode == PHY_INTERFACE_MODE_QSGMII\n\t    || mode == PHY_INTERFACE_MODE_HSGMII || mode == PHY_INTERFACE_MODE_SGMII\n\t    || mode == PHY_INTERFACE_MODE_USXGMII) {\n\t\tif (mode == PHY_INTERFACE_MODE_XGMII)\n\t\t\trtl931x_sds_mii_mode_set(sds, mode);\n\t\telse\n\t\t\trtl931x_sds_fiber_mode_set(sds, mode);\n\t}\n}\n\nint rtl931x_sds_cmu_band_set(int sds, bool enable, u32 band, phy_interface_t mode)\n{\n\tu32 asds;\n\tint page = rtl931x_sds_cmu_page_get(mode);\n\n\tsds -= (sds % 2);\n\tsds = sds & ~1;\n\tasds = rtl931x_get_analog_sds(sds);\n\tpage += 1;\n\n\tif (enable) {\n\t\trtl9310_sds_field_w(asds, page, 0x7, 13, 13, 0);\n\t\trtl9310_sds_field_w(asds, page, 0x7, 11, 11, 0);\n\t} else {\n\t\trtl9310_sds_field_w(asds, page, 0x7, 13, 13, 0);\n\t\trtl9310_sds_field_w(asds, page, 0x7, 11, 11, 0);\n\t}\n\t\t\n\trtl9310_sds_field_w(asds, page, 0x7, 4, 0, band);\n\n\trtl931x_sds_rst(sds);\n\n\treturn 0;\n}\n\nint rtl931x_sds_cmu_band_get(int sds, phy_interface_t mode)\n{\n\tint page = rtl931x_sds_cmu_page_get(mode);\n\tu32 asds, band;\n\n\tsds -= (sds % 2);\n\tasds = rtl931x_get_analog_sds(sds);\n\tpage += 1;\n\trtl931x_write_sds_phy(asds, 0x1f, 0x02, 73);\n\n\trtl9310_sds_field_w(asds, page, 0x5, 15, 15, 1);\n\tband = rtl9310_sds_field_r(asds, 0x1f, 0x15, 8, 3);\n\tpr_info(\"%s band is: %d\\n\", __func__, band);\n\n\treturn band;\n}\n\n\nint rtl931x_link_sts_get(u32 sds)\n{\n\tu32 sts, sts1, latch_sts, latch_sts1;\n\tif (0){\n\t\tu32 xsg_sdsid_0, xsg_sdsid_1;\n\n\t\txsg_sdsid_0 = sds < 2 ? sds : (sds - 1) * 2;\n\t\txsg_sdsid_1 = xsg_sdsid_0 + 1;\n\n\t\tsts = rtl9310_sds_field_r(xsg_sdsid_0, 0x1, 29, 8, 0);\n\t\tsts1 = rtl9310_sds_field_r(xsg_sdsid_1, 0x1, 29, 8, 0);\n\t\tlatch_sts = rtl9310_sds_field_r(xsg_sdsid_0, 0x1, 30, 8, 0);\n\t\tlatch_sts1 = rtl9310_sds_field_r(xsg_sdsid_1, 0x1, 30, 8, 0);\n\t} else {\n\t\tu32  asds, dsds;\n\n\t\tasds = rtl931x_get_analog_sds(sds);\n\t\tsts = rtl9310_sds_field_r(asds, 0x5, 0, 12, 12);\n\t\tlatch_sts = rtl9310_sds_field_r(asds, 0x4, 1, 2, 2);\n\n\t\tdsds = sds < 2 ? sds : (sds - 1) * 2;\n\t\tlatch_sts1 = rtl9310_sds_field_r(dsds, 0x2, 1, 2, 2);\n\t\tsts1 = rtl9310_sds_field_r(dsds, 0x2, 1, 2, 2);\n\t}\n\n\tpr_info(\"%s: serdes %d sts %d, sts1 %d, latch_sts %d, latch_sts1 %d\\n\", __func__,\n\t\tsds, sts, sts1, latch_sts, latch_sts1);\n\treturn sts1;\n}\n\nstatic int rtl8214fc_phy_probe(struct phy_device *phydev)\n{\n\tstruct device *dev = &phydev->mdio.dev;\n\tint addr = phydev->mdio.addr;\n\tint ret = 0;\n\n\t/* 839x has internal SerDes */\n\tif (soc_info.id == 0x8393)\n\t\treturn -ENODEV;\n\n\t/* All base addresses of the PHYs start at multiples of 8 */\n\tdevm_phy_package_join(dev, phydev, addr & (~7),\n\t\t\t\tsizeof(struct rtl83xx_shared_private));\n\n\tif (!(addr % 8)) {\n\t\tstruct rtl83xx_shared_private *shared = phydev->shared->priv;\n\t\tshared->name = \"RTL8214FC\";\n\t\t/* Configuration must be done while patching still possible */\n\t\tret = rtl8380_configure_rtl8214fc(phydev);\n\t\tif (ret)\n\t\t\treturn ret;\n\t}\n\n\treturn 0;\n}\n\nstatic int rtl8214c_phy_probe(struct phy_device *phydev)\n{\n\tstruct device *dev = &phydev->mdio.dev;\n\tint addr = phydev->mdio.addr;\n\n\t/* All base addresses of the PHYs start at multiples of 8 */\n\tdevm_phy_package_join(dev, phydev, addr & (~7),\n\t\t\t\tsizeof(struct rtl83xx_shared_private));\n\n\tif (!(addr % 8)) {\n\t\tstruct rtl83xx_shared_private *shared = phydev->shared->priv;\n\t\tshared->name = \"RTL8214C\";\n\t\t/* Configuration must be done whil patching still possible */\n\t\treturn rtl8380_configure_rtl8214c(phydev);\n\t}\n\treturn 0;\n}\n\nstatic int rtl8218b_ext_phy_probe(struct phy_device *phydev)\n{\n\tstruct device *dev = &phydev->mdio.dev;\n\tint addr = phydev->mdio.addr;\n\n\t/* All base addresses of the PHYs start at multiples of 8 */\n\tdevm_phy_package_join(dev, phydev, addr & (~7),\n\t\t\t\tsizeof(struct rtl83xx_shared_private));\n\n\tif (!(addr % 8)) {\n\t\tstruct rtl83xx_shared_private *shared = phydev->shared->priv;\n\t\tshared->name = \"RTL8218B (external)\";\n\t\tif (soc_info.family == RTL8380_FAMILY_ID) {\n\t\t\t/* Configuration must be done while patching still possible */\n\t\t\treturn rtl8380_configure_ext_rtl8218b(phydev);\n\t\t}\n\t}\n\n\treturn 0;\n}\n\nstatic int rtl8218b_int_phy_probe(struct phy_device *phydev)\n{\n\tstruct device *dev = &phydev->mdio.dev;\n\tint addr = phydev->mdio.addr;\n\n\tif (soc_info.family != RTL8380_FAMILY_ID)\n\t\treturn -ENODEV;\n\tif (addr >= 24)\n\t\treturn -ENODEV;\n\n\tpr_debug(\"%s: id: %d\\n\", __func__, addr);\n\t/* All base addresses of the PHYs start at multiples of 8 */\n\tdevm_phy_package_join(dev, phydev, addr & (~7),\n\t\t\t      sizeof(struct rtl83xx_shared_private));\n\n\tif (!(addr % 8)) {\n\t\tstruct rtl83xx_shared_private *shared = phydev->shared->priv;\n\t\tshared->name = \"RTL8218B (internal)\";\n\t\t/* Configuration must be done while patching still possible */\n\t\treturn rtl8380_configure_int_rtl8218b(phydev);\n\t}\n\n\treturn 0;\n}\n\nstatic int rtl8218d_phy_probe(struct phy_device *phydev)\n{\n\tstruct device *dev = &phydev->mdio.dev;\n\tint addr = phydev->mdio.addr;\n\n\tpr_debug(\"%s: id: %d\\n\", __func__, addr);\n\t/* All base addresses of the PHYs start at multiples of 8 */\n\tdevm_phy_package_join(dev, phydev, addr & (~7),\n\t\t\t      sizeof(struct rtl83xx_shared_private));\n\n\t/* All base addresses of the PHYs start at multiples of 8 */\n\tif (!(addr % 8)) {\n\t\tstruct rtl83xx_shared_private *shared = phydev->shared->priv;\n\t\tshared->name = \"RTL8218D\";\n\t\t/* Configuration must be done while patching still possible */\n// TODO:\t\treturn configure_rtl8218d(phydev);\n\t}\n\treturn 0;\n}\n\nstatic int rtl838x_serdes_probe(struct phy_device *phydev)\n{\n\tint addr = phydev->mdio.addr;\n\n\tif (soc_info.family != RTL8380_FAMILY_ID)\n\t\treturn -ENODEV;\n\tif (addr < 24)\n\t\treturn -ENODEV;\n\n\t/* On the RTL8380M, PHYs 24-27 connect to the internal SerDes */\n\tif (soc_info.id == 0x8380) {\n\t\tif (addr == 24)\n\t\t\treturn rtl8380_configure_serdes(phydev);\n\t\treturn 0;\n\t}\n\treturn -ENODEV;\n}\n\nstatic int rtl8393_serdes_probe(struct phy_device *phydev)\n{\n\tint addr = phydev->mdio.addr;\n\n\tpr_info(\"%s: id: %d\\n\", __func__, addr);\n\tif (soc_info.family != RTL8390_FAMILY_ID)\n\t\treturn -ENODEV;\n\n\tif (addr < 24)\n\t\treturn -ENODEV;\n\n\treturn rtl8390_configure_serdes(phydev);\n}\n\nstatic int rtl8390_serdes_probe(struct phy_device *phydev)\n{\n\tint addr = phydev->mdio.addr;\n\n\tif (soc_info.family != RTL8390_FAMILY_ID)\n\t\treturn -ENODEV;\n\n\tif (addr < 24)\n\t\treturn -ENODEV;\n\n\treturn rtl8390_configure_generic(phydev);\n}\n\nstatic int rtl9300_serdes_probe(struct phy_device *phydev)\n{\n\tif (soc_info.family != RTL9300_FAMILY_ID)\n\t\treturn -ENODEV;\n\n\tphydev_info(phydev, \"Detected internal RTL9300 Serdes\\n\");\n\n\treturn rtl9300_configure_serdes(phydev);\n}\n\nstatic struct phy_driver rtl83xx_phy_driver[] = {\n\t{\n\t\tPHY_ID_MATCH_MODEL(PHY_ID_RTL8214C),\n\t\t.name\t\t= \"Realtek RTL8214C\",\n\t\t.features\t= PHY_GBIT_FEATURES,\n\t\t.flags\t\t= PHY_HAS_REALTEK_PAGES,\n\t\t.match_phy_device = rtl8214c_match_phy_device,\n\t\t.probe\t\t= rtl8214c_phy_probe,\n\t\t.suspend\t= genphy_suspend,\n\t\t.resume\t\t= genphy_resume,\n\t\t.set_loopback\t= genphy_loopback,\n\t},\n\t{\n\t\tPHY_ID_MATCH_MODEL(PHY_ID_RTL8214FC),\n\t\t.name\t\t= \"Realtek RTL8214FC\",\n\t\t.features\t= PHY_GBIT_FIBRE_FEATURES,\n\t\t.flags\t\t= PHY_HAS_REALTEK_PAGES,\n\t\t.match_phy_device = rtl8214fc_match_phy_device,\n\t\t.probe\t\t= rtl8214fc_phy_probe,\n\t\t.suspend\t= genphy_suspend,\n\t\t.resume\t\t= genphy_resume,\n\t\t.set_loopback\t= genphy_loopback,\n\t\t.set_port\t= rtl8214fc_set_port,\n\t\t.get_port\t= rtl8214fc_get_port,\n\t\t.set_eee\t= rtl8214fc_set_eee,\n\t\t.get_eee\t= rtl8214fc_get_eee,\n\t},\n\t{\n\t\tPHY_ID_MATCH_MODEL(PHY_ID_RTL8218B_E),\n\t\t.name\t\t= \"Realtek RTL8218B (external)\",\n\t\t.features\t= PHY_GBIT_FEATURES,\n\t\t.flags\t\t= PHY_HAS_REALTEK_PAGES,\n\t\t.match_phy_device = rtl8218b_ext_match_phy_device,\n\t\t.probe\t\t= rtl8218b_ext_phy_probe,\n\t\t.suspend\t= genphy_suspend,\n\t\t.resume\t\t= genphy_resume,\n\t\t.set_loopback\t= genphy_loopback,\n\t\t.set_eee\t= rtl8218b_set_eee,\n\t\t.get_eee\t= rtl8218b_get_eee,\n\t},\n\t{\n\t\tPHY_ID_MATCH_MODEL(PHY_ID_RTL8218D),\n\t\t.name\t\t= \"REALTEK RTL8218D\",\n\t\t.features\t= PHY_GBIT_FEATURES,\n\t\t.flags\t\t= PHY_HAS_REALTEK_PAGES,\n\t\t.probe\t\t= rtl8218d_phy_probe,\n\t\t.suspend\t= genphy_suspend,\n\t\t.resume\t\t= genphy_resume,\n\t\t.set_loopback\t= genphy_loopback,\n\t\t.set_eee\t= rtl8218d_set_eee,\n\t\t.get_eee\t= rtl8218d_get_eee,\n\t},\n\t{\n\t\tPHY_ID_MATCH_MODEL(PHY_ID_RTL8221B),\n\t\t.name           = \"REALTEK RTL8221B\",\n\t\t.features       = PHY_GBIT_FEATURES,\n\t\t.flags\t\t= PHY_HAS_REALTEK_PAGES,\n\t\t.suspend        = genphy_suspend,\n\t\t.resume         = genphy_resume,\n\t\t.set_loopback   = genphy_loopback,\n\t\t.read_page      = rtl8226_read_page,\n\t\t.write_page     = rtl8226_write_page,\n\t\t.read_status    = rtl8226_read_status,\n\t\t.config_aneg    = rtl8226_config_aneg,\n\t\t.set_eee        = rtl8226_set_eee,\n\t\t.get_eee        = rtl8226_get_eee,\n\t},\n\t{\n\t\tPHY_ID_MATCH_MODEL(PHY_ID_RTL8226),\n\t\t.name\t\t= \"REALTEK RTL8226\",\n\t\t.features\t= PHY_GBIT_FEATURES,\n\t\t.flags\t\t= PHY_HAS_REALTEK_PAGES,\n\t\t.suspend\t= genphy_suspend,\n\t\t.resume\t\t= genphy_resume,\n\t\t.set_loopback\t= genphy_loopback,\n\t\t.read_page\t= rtl8226_read_page,\n\t\t.write_page\t= rtl8226_write_page,\n\t\t.read_status\t= rtl8226_read_status,\n\t\t.config_aneg\t= rtl8226_config_aneg,\n\t\t.set_eee\t= rtl8226_set_eee,\n\t\t.get_eee\t= rtl8226_get_eee,\n\t},\n\t{\n\t\tPHY_ID_MATCH_MODEL(PHY_ID_RTL8218B_I),\n\t\t.name\t\t= \"Realtek RTL8218B (internal)\",\n\t\t.features\t= PHY_GBIT_FEATURES,\n\t\t.flags\t\t= PHY_HAS_REALTEK_PAGES,\n\t\t.probe\t\t= rtl8218b_int_phy_probe,\n\t\t.suspend\t= genphy_suspend,\n\t\t.resume\t\t= genphy_resume,\n\t\t.set_loopback\t= genphy_loopback,\n\t\t.set_eee\t= rtl8218b_set_eee,\n\t\t.get_eee\t= rtl8218b_get_eee,\n\t},\n\t{\n\t\tPHY_ID_MATCH_MODEL(PHY_ID_RTL8218B_I),\n\t\t.name\t\t= \"Realtek RTL8380 SERDES\",\n\t\t.features\t= PHY_GBIT_FIBRE_FEATURES,\n\t\t.flags\t\t= PHY_HAS_REALTEK_PAGES,\n\t\t.probe\t\t= rtl838x_serdes_probe,\n\t\t.suspend\t= genphy_suspend,\n\t\t.resume\t\t= genphy_resume,\n\t\t.set_loopback\t= genphy_loopback,\n\t\t.read_status\t= rtl8380_read_status,\n\t},\n\t{\n\t\tPHY_ID_MATCH_MODEL(PHY_ID_RTL8393_I),\n\t\t.name\t\t= \"Realtek RTL8393 SERDES\",\n\t\t.features\t= PHY_GBIT_FIBRE_FEATURES,\n\t\t.flags\t\t= PHY_HAS_REALTEK_PAGES,\n\t\t.probe\t\t= rtl8393_serdes_probe,\n\t\t.suspend\t= genphy_suspend,\n\t\t.resume\t\t= genphy_resume,\n\t\t.set_loopback\t= genphy_loopback,\n\t\t.read_status\t= rtl8393_read_status,\n\t},\n\t{\n\t\tPHY_ID_MATCH_MODEL(PHY_ID_RTL8390_GENERIC),\n\t\t.name\t\t= \"Realtek RTL8390 Generic\",\n\t\t.features\t= PHY_GBIT_FIBRE_FEATURES,\n\t\t.flags\t\t= PHY_HAS_REALTEK_PAGES,\n\t\t.probe\t\t= rtl8390_serdes_probe,\n\t\t.suspend\t= genphy_suspend,\n\t\t.resume\t\t= genphy_resume,\n\t\t.set_loopback\t= genphy_loopback,\n\t},\n\t{\n\t\tPHY_ID_MATCH_MODEL(PHY_ID_RTL9300_I),\n\t\t.name\t\t= \"REALTEK RTL9300 SERDES\",\n\t\t.features\t= PHY_GBIT_FIBRE_FEATURES,\n\t\t.flags\t\t= PHY_HAS_REALTEK_PAGES,\n\t\t.probe\t\t= rtl9300_serdes_probe,\n\t\t.suspend\t= genphy_suspend,\n\t\t.resume\t\t= genphy_resume,\n\t\t.set_loopback\t= genphy_loopback,\n\t\t.read_status\t= rtl9300_read_status,\n\t},\n};\n\nmodule_phy_driver(rtl83xx_phy_driver);\n\nstatic struct mdio_device_id __maybe_unused rtl83xx_tbl[] = {\n\t{ PHY_ID_MATCH_MODEL(PHY_ID_RTL8214FC) },\n\t{ }\n};\n\nMODULE_DEVICE_TABLE(mdio, rtl83xx_tbl);\n\nMODULE_AUTHOR(\"B. Koblitz\");\nMODULE_DESCRIPTION(\"RTL83xx PHY driver\");\nMODULE_LICENSE(\"GPL\");\n"
  },
  {
    "path": "target/linux/realtek/files-5.10/drivers/net/phy/rtl83xx-phy.h",
    "content": "// SPDX-License-Identifier: GPL-2.0-only\n\nstruct rtl83xx_shared_private {\n\tchar *name;\n};\n\nstruct __attribute__ ((__packed__)) part {\n\tuint16_t start;\n\tuint8_t wordsize;\n\tuint8_t words;\n};\n\nstruct __attribute__ ((__packed__)) fw_header {\n\tuint32_t magic;\n\tuint32_t phy;\n\tuint32_t checksum;\n\tuint32_t version;\n\tstruct part parts[10];\n};\n\n// TODO: fixed path?\n#define FIRMWARE_838X_8380_1\t\"rtl838x_phy/rtl838x_8380.fw\"\n#define FIRMWARE_838X_8214FC_1\t\"rtl838x_phy/rtl838x_8214fc.fw\"\n#define FIRMWARE_838X_8218b_1\t\"rtl838x_phy/rtl838x_8218b.fw\"\n\n/* External RTL8218B and RTL8214FC IDs are identical */\n#define PHY_ID_RTL8214C\t\t0x001cc942\n#define PHY_ID_RTL8214FC\t0x001cc981\n#define PHY_ID_RTL8218B_E\t0x001cc981\n#define PHY_ID_RTL8218D\t\t0x001cc983\n#define PHY_ID_RTL8218B_I\t0x001cca40\n#define PHY_ID_RTL8221B\t\t0x001cc849\n#define PHY_ID_RTL8226\t\t0x001cc838\n#define PHY_ID_RTL8390_GENERIC\t0x001ccab0\n#define PHY_ID_RTL8393_I\t0x001c8393\n#define PHY_ID_RTL9300_I\t0x70d03106\n\n// PHY MMD devices\n#define MMD_AN\t\t7\n#define MMD_VEND2\t31\n\n/* Registers of the internal Serdes of the 8380 */\n#define RTL838X_SDS_MODE_SEL\t\t\t(0x0028)\n#define RTL838X_SDS_CFG_REG\t\t\t(0x0034)\n#define RTL838X_INT_MODE_CTRL\t\t\t(0x005c)\n#define RTL838X_DMY_REG31\t\t\t(0x3b28)\n\n#define RTL8380_SDS4_FIB_REG0\t\t\t(0xF800)\n#define RTL838X_SDS4_REG28\t\t\t(0xef80)\n#define RTL838X_SDS4_DUMMY0\t\t\t(0xef8c)\n#define RTL838X_SDS5_EXT_REG6\t\t\t(0xf18c)\n#define RTL838X_SDS4_FIB_REG0\t\t\t(RTL838X_SDS4_REG28 + 0x880)\n#define RTL838X_SDS5_FIB_REG0\t\t\t(RTL838X_SDS4_REG28 + 0x980)\n\n/* Registers of the internal SerDes of the RTL8390 */\n#define RTL839X_SDS12_13_XSG0\t\t\t(0xB800)\n\n/* Registers of the internal Serdes of the 9300 */\n#define RTL930X_SDS_INDACS_CMD\t\t\t(0x03B0)\n#define RTL930X_SDS_INDACS_DATA\t\t\t(0x03B4)\n#define RTL930X_MAC_FORCE_MODE_CTRL\t\t(0xCA1C)\n\n/*Registers of the internal SerDes of the 9310 */\n#define RTL931X_SERDES_INDRT_ACCESS_CTRL\t(0x5638)\n#define RTL931X_SERDES_INDRT_DATA_CTRL\t\t(0x563C)\n#define RTL931X_SERDES_MODE_CTRL\t\t(0x13cc)\n#define RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR\t(0x13F4)\n#define RTL931X_MAC_SERDES_MODE_CTRL(sds)\t(0x136C + (((sds) << 2)))\n"
  },
  {
    "path": "target/linux/realtek/image/Makefile",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n\ninclude $(TOPDIR)/rules.mk\ninclude $(INCLUDE_DIR)/image.mk\n\nKERNEL_LOADADDR = 0x80000000\nKERNEL_ENTRY = 0x80000400\n\nDEVICE_VARS += ZYXEL_VERS\n\ndefine Build/zyxel-vers\n       ( echo VERS;\\\n       for hw in $(ZYXEL_VERS); do\\\n               echo -n \"V9.99($$hw.0) | \";\\\n               date -d @$(SOURCE_DATE_EPOCH) +%m/%d/%Y;\\\n       done ) >> $@\nendef\n\ndefine Device/Default\n  PROFILES = Default\n  KERNEL := kernel-bin | append-dtb | gzip | uImage gzip\n  KERNEL_INITRAMFS := kernel-bin | append-dtb | gzip | uImage gzip\n  DEVICE_DTS_DIR := ../dts-$(KERNEL_PATCHVER)\n  DEVICE_DTS = $$(SOC)_$(1)\n  IMAGES := sysupgrade.bin\n  IMAGE/sysupgrade.bin := append-kernel | pad-to 64k | append-rootfs | pad-rootfs | \\\n\tcheck-size | append-metadata\nendef\n\n# \"NGE\" refers to the uImage magic\ndefine Device/netgear_nge\n  KERNEL := kernel-bin | append-dtb | lzma | uImage lzma\n  KERNEL_INITRAMFS := kernel-bin | append-dtb | lzma | uImage lzma\n  SOC := rtl8380\n  IMAGE_SIZE := 14848k\n  UIMAGE_MAGIC := 0x4e474520\n  DEVICE_VENDOR := NETGEAR\nendef\n\ninclude $(SUBTARGET).mk\n\n$(eval $(call BuildImage))\n"
  },
  {
    "path": "target/linux/realtek/image/rtl838x.mk",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n\n\ndefine Device/allnet_all-sg8208m\n  SOC := rtl8382\n  IMAGE_SIZE := 7168k\n  DEVICE_VENDOR := ALLNET\n  DEVICE_MODEL := ALL-SG8208M\n  UIMAGE_MAGIC := 0x00000006\n  UIMAGE_NAME := 2.2.2.0\nendef\nTARGET_DEVICES += allnet_all-sg8208m\n\ndefine Device/d-link_dgs-1210\n  SOC := rtl8382\n  IMAGE_SIZE := 13824k\n  DEVICE_VENDOR := D-Link\nendef\n\ndefine Device/d-link_dgs-1210-10p\n  $(Device/d-link_dgs-1210)\n  DEVICE_MODEL := DGS-1210-10P\n  DEVICE_PACKAGES += lua-rs232\nendef\nTARGET_DEVICES += d-link_dgs-1210-10p\n\ndefine Device/d-link_dgs-1210-16\n  $(Device/d-link_dgs-1210)\n  DEVICE_MODEL := DGS-1210-16\nendef\nTARGET_DEVICES += d-link_dgs-1210-16\n\ndefine Device/d-link_dgs-1210-28\n  $(Device/d-link_dgs-1210)\n  DEVICE_MODEL := DGS-1210-28\nendef\nTARGET_DEVICES += d-link_dgs-1210-28\n\ndefine Device/inaba_aml2-17gp\n  SOC := rtl8382\n  IMAGE_SIZE := 13504k\n  DEVICE_VENDOR := INABA\n  DEVICE_MODEL := Abaniact AML2-17GP\n  UIMAGE_MAGIC := 0x83800000\nendef\nTARGET_DEVICES += inaba_aml2-17gp\n\ndefine Device/iodata_bsh-g24mb\n  SOC := rtl8382\n  IMAGE_SIZE := 13696k\n  DEVICE_VENDOR := I-O DATA\n  DEVICE_MODEL := BSH-G24MB\n  UIMAGE_MAGIC := 0x83800013\nendef\nTARGET_DEVICES += iodata_bsh-g24mb\n\ndefine Device/netgear_gs108t-v3\n  $(Device/netgear_nge)\n  DEVICE_MODEL := GS108T\n  DEVICE_VARIANT := v3\nendef\nTARGET_DEVICES += netgear_gs108t-v3\n\ndefine Device/netgear_gs110tpp-v1\n  $(Device/netgear_nge)\n  DEVICE_MODEL := GS110TPP\n  DEVICE_VARIANT := v1\nendef\nTARGET_DEVICES += netgear_gs110tpp-v1\n\ndefine Device/netgear_gs308t-v1\n  $(Device/netgear_nge)\n  DEVICE_MODEL := GS308T\n  DEVICE_VARIANT := v1\n  UIMAGE_MAGIC := 0x4e474335\nendef\nTARGET_DEVICES += netgear_gs308t-v1\n\ndefine Device/netgear_gs310tp-v1\n  $(Device/netgear_nge)\n  DEVICE_MODEL := GS310TP\n  DEVICE_VARIANT := v1\n  UIMAGE_MAGIC := 0x4e474335\n  DEVICE_PACKAGES += lua-rs232\nendef\nTARGET_DEVICES += netgear_gs310tp-v1\n\ndefine Device/panasonic_m8eg-pn28080k\n  SOC := rtl8380\n  IMAGE_SIZE := 16384k\n  DEVICE_VENDOR := Panasonic\n  DEVICE_MODEL := Switch-M8eG\n  DEVICE_VARIANT := PN28080K\n  DEVICE_PACKAGES := kmod-i2c-mux-pca954x\nendef\nTARGET_DEVICES += panasonic_m8eg-pn28080k\n\ndefine Device/zyxel_gs1900\n  SOC := rtl8380\n  IMAGE_SIZE := 6976k\n  DEVICE_VENDOR := ZyXEL\n  UIMAGE_MAGIC := 0x83800000\n  KERNEL_INITRAMFS := kernel-bin | append-dtb | gzip | zyxel-vers | \\\n\tuImage gzip\nendef\n\ndefine Device/zyxel_gs1900-10hp\n  $(Device/zyxel_gs1900)\n  DEVICE_MODEL := GS1900-10HP\n  ZYXEL_VERS := AAZI\nendef\nTARGET_DEVICES += zyxel_gs1900-10hp\n\ndefine Device/zyxel_gs1900-16\n  $(Device/zyxel_gs1900)\n  SOC := rtl8382\n  DEVICE_MODEL := GS1900-16\n  ZYXEL_VERS := AAHJ\nendef\nTARGET_DEVICES += zyxel_gs1900-16\n\ndefine Device/zyxel_gs1900-8\n  $(Device/zyxel_gs1900)\n  DEVICE_MODEL := GS1900-8\n  ZYXEL_VERS := AAHH\nendef\nTARGET_DEVICES += zyxel_gs1900-8\n\ndefine Device/zyxel_gs1900-8hp-v1\n  $(Device/zyxel_gs1900)\n  DEVICE_MODEL := GS1900-8HP\n  DEVICE_VARIANT := v1\n  ZYXEL_VERS := AAHI\n  DEVICE_PACKAGES += lua-rs232\nendef\nTARGET_DEVICES += zyxel_gs1900-8hp-v1\n\ndefine Device/zyxel_gs1900-8hp-v2\n  $(Device/zyxel_gs1900)\n  DEVICE_MODEL := GS1900-8HP\n  DEVICE_VARIANT := v2\n  ZYXEL_VERS := AAHI\n  DEVICE_PACKAGES += lua-rs232\nendef\nTARGET_DEVICES += zyxel_gs1900-8hp-v2\n\ndefine Device/zyxel_gs1900-24-v1\n  $(Device/zyxel_gs1900)\n  SOC := rtl8382\n  DEVICE_MODEL := GS1900-24\n  DEVICE_VARIANT := v1\n  ZYXEL_VERS := AAHL\nendef\nTARGET_DEVICES += zyxel_gs1900-24-v1\n\ndefine Device/zyxel_gs1900-24hp-v1\n  $(Device/zyxel_gs1900)\n  SOC := rtl8382\n  DEVICE_MODEL := GS1900-24HP\n  DEVICE_VARIANT := v1\n  ZYXEL_VERS := AAHM\nendef\nTARGET_DEVICES += zyxel_gs1900-24hp-v1\n\ndefine Device/zyxel_gs1900-24hp-v2\n  $(Device/zyxel_gs1900)\n  SOC := rtl8382\n  DEVICE_MODEL := GS1900-24HP\n  DEVICE_VARIANT := v2\n  ZYXEL_VERS := ABTP\nendef\nTARGET_DEVICES += zyxel_gs1900-24hp-v2\n"
  },
  {
    "path": "target/linux/realtek/image/rtl839x.mk",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n\ndefine Device/zyxel_gs1900-48\n  SOC := rtl8393\n  IMAGE_SIZE := 13952k\n  DEVICE_VENDOR := ZyXEL\n  UIMAGE_MAGIC := 0x83800000\n  ZYXEL_VERS := AAHO\n  DEVICE_MODEL := GS1900-48\n  KERNEL_INITRAMFS := kernel-bin | append-dtb | gzip | zyxel-vers $$$$(ZYXEL_VERS) | \\\n\tuImage gzip\nendef\nTARGET_DEVICES += zyxel_gs1900-48\n"
  },
  {
    "path": "target/linux/realtek/image/rtl930x.mk",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n\ndefine Device/zyxel_xgs1250-12\n  SOC := rtl9302\n  UIMAGE_MAGIC := 0x93001250\n  ZYXEL_VERS := ABWE\n  DEVICE_VENDOR := Zyxel\n  DEVICE_MODEL := XGS1250-12\n    IMAGE_SIZE := 13312k\n  KERNEL_INITRAMFS := kernel-bin | append-dtb | gzip | zyxel-vers $$$$(ZYXEL_VERS) | \\\n\tuImage gzip\nendef\n\nTARGET_DEVICES += zyxel_xgs1250-12\n"
  },
  {
    "path": "target/linux/realtek/image/rtl931x.mk",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n"
  },
  {
    "path": "target/linux/realtek/patches-5.10/001-5.13-dt-bindings-gpio-binding-for-realtek-otto-gpio.patch",
    "content": "From a362c0ce64866939c3daa17c76943cfed555b065 Mon Sep 17 00:00:00 2001\nFrom: Sander Vanheule <sander@svanheule.net>\nDate: Tue, 30 Mar 2021 19:48:42 +0200\nSubject: dt-bindings: gpio: Binding for Realtek Otto GPIO\n\nAdd a binding description for Realtek's GPIO controller found on several\nof their MIPS-based SoCs (codenamed Otto), such as the RTL838x and\nRTL839x series of switch SoCs.\n\nA fallback binding 'realtek,otto-gpio' is provided for cases where the\nactual port ordering is not known yet, and enabling the interrupt\ncontroller may result in uncaught interrupts.\n\nSigned-off-by: Sander Vanheule <sander@svanheule.net>\nReviewed-by: Linus Walleij <linus.walleij@linaro.org>\nReviewed-by: Rob Herring <robh@kernel.org>\nSigned-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>\n---\n .../bindings/gpio/realtek,otto-gpio.yaml           | 78 ++++++++++++++++++++++\n 1 file changed, 78 insertions(+)\n create mode 100644 Documentation/devicetree/bindings/gpio/realtek,otto-gpio.yaml\n\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/gpio/realtek,otto-gpio.yaml\n@@ -0,0 +1,78 @@\n+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause\n+%YAML 1.2\n+---\n+$id: http://devicetree.org/schemas/gpio/realtek,otto-gpio.yaml#\n+$schema: http://devicetree.org/meta-schemas/core.yaml#\n+\n+title: Realtek Otto GPIO controller\n+\n+maintainers:\n+  - Sander Vanheule <sander@svanheule.net>\n+  - Bert Vermeulen <bert@biot.com>\n+\n+description: |\n+  Realtek's GPIO controller on their MIPS switch SoCs (Otto platform) consists\n+  of two banks of 32 GPIOs. These GPIOs can generate edge-triggered interrupts.\n+  Each bank's interrupts are cascased into one interrupt line on the parent\n+  interrupt controller, if provided.\n+  This binding allows defining a single bank in the devicetree. The interrupt\n+  controller is not supported on the fallback compatible name, which only\n+  allows for GPIO port use.\n+\n+properties:\n+  $nodename:\n+    pattern: \"^gpio@[0-9a-f]+$\"\n+\n+  compatible:\n+    items:\n+      - enum:\n+          - realtek,rtl8380-gpio\n+          - realtek,rtl8390-gpio\n+      - const: realtek,otto-gpio\n+\n+  reg:\n+    maxItems: 1\n+\n+  \"#gpio-cells\":\n+    const: 2\n+\n+  gpio-controller: true\n+\n+  ngpios:\n+    minimum: 1\n+    maximum: 32\n+\n+  interrupt-controller: true\n+\n+  \"#interrupt-cells\":\n+    const: 2\n+\n+  interrupts:\n+    maxItems: 1\n+\n+required:\n+  - compatible\n+  - reg\n+  - \"#gpio-cells\"\n+  - gpio-controller\n+\n+additionalProperties: false\n+\n+dependencies:\n+  interrupt-controller: [ interrupts ]\n+\n+examples:\n+  - |\n+      gpio@3500 {\n+        compatible = \"realtek,rtl8380-gpio\", \"realtek,otto-gpio\";\n+        reg = <0x3500 0x1c>;\n+        gpio-controller;\n+        #gpio-cells = <2>;\n+        ngpios = <24>;\n+        interrupt-controller;\n+        #interrupt-cells = <2>;\n+        interrupt-parent = <&rtlintc>;\n+        interrupts = <23>;\n+      };\n+\n+...\n"
  },
  {
    "path": "target/linux/realtek/patches-5.10/002-5.13-gpio-add-realtek-otto-gpio-support.patch",
    "content": "From f0f7d662e8514169c90d3d84cd6df773b2983088 Mon Sep 17 00:00:00 2001\nFrom: Sander Vanheule <sander@svanheule.net>\nDate: Tue, 30 Mar 2021 19:48:43 +0200\nSubject: gpio: Add Realtek Otto GPIO support\n\nRealtek MIPS SoCs (platform name Otto) have GPIO controllers with up to\n64 GPIOs, divided over two banks. Each bank has a set of registers for\n32 GPIOs, with support for edge-triggered interrupts.\n\nEach GPIO bank consists of four 8-bit GPIO ports (ABCD and EFGH). Most\nregisters pack one bit per GPIO, except for the IMR register, which\npacks two bits per GPIO (AB-CD).\n\nAlthough the byte order is currently assumed to have port A..D at offset\n0x0..0x3, this has been observed to be reversed on other, Lexra-based,\nSoCs (e.g. RTL8196E/97D/97F).\n\nInterrupt support is disabled for the fallback devicetree-compatible\n'realtek,otto-gpio'. This allows for quick support of GPIO banks in\nwhich the byte order would be unknown. In this case, the port ordering\nin the IMR registers may not match the reversed order in the other\nregisters (DCBA, and BA-DC or DC-BA).\n\nSigned-off-by: Sander Vanheule <sander@svanheule.net>\nReviewed-by: Linus Walleij <linus.walleij@linaro.org>\nReviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>\nSigned-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>\n---\n drivers/gpio/Kconfig             |  13 ++\n drivers/gpio/Makefile            |   1 +\n drivers/gpio/gpio-realtek-otto.c | 325 +++++++++++++++++++++++++++++++++++++++\n 3 files changed, 339 insertions(+)\n create mode 100644 drivers/gpio/gpio-realtek-otto.c\n\n--- a/drivers/gpio/Kconfig\n+++ b/drivers/gpio/Kconfig\n@@ -489,6 +489,19 @@ config GPIO_RDA\n \thelp\n \t  Say Y here to support RDA Micro GPIO controller.\n \n+config GPIO_REALTEK_OTTO\n+\ttristate \"Realtek Otto GPIO support\"\n+\tdepends on MACH_REALTEK_RTL\n+\tdefault MACH_REALTEK_RTL\n+\tselect GPIO_GENERIC\n+\tselect GPIOLIB_IRQCHIP\n+\thelp\n+\t  The GPIO controller on the Otto MIPS platform supports up to two\n+\t  banks of 32 GPIOs, with edge triggered interrupts. The 32 GPIOs\n+\t  are grouped in four 8-bit wide ports.\n+\n+\t  When built as a module, the module will be called realtek_otto_gpio.\n+\n config GPIO_REG\n \tbool\n \thelp\n--- a/drivers/gpio/Makefile\n+++ b/drivers/gpio/Makefile\n@@ -125,6 +125,7 @@ obj-$(CONFIG_GPIO_RC5T583)\t\t+= gpio-rc5t\n obj-$(CONFIG_GPIO_RCAR)\t\t\t+= gpio-rcar.o\n obj-$(CONFIG_GPIO_RDA)\t\t\t+= gpio-rda.o\n obj-$(CONFIG_GPIO_RDC321X)\t\t+= gpio-rdc321x.o\n+obj-$(CONFIG_GPIO_REALTEK_OTTO)\t\t+= gpio-realtek-otto.o\n obj-$(CONFIG_GPIO_REG)\t\t\t+= gpio-reg.o\n obj-$(CONFIG_ARCH_SA1100)\t\t+= gpio-sa1100.o\n obj-$(CONFIG_GPIO_SAMA5D2_PIOBU)\t+= gpio-sama5d2-piobu.o\n--- /dev/null\n+++ b/drivers/gpio/gpio-realtek-otto.c\n@@ -0,0 +1,325 @@\n+// SPDX-License-Identifier: GPL-2.0-only\n+\n+#include <linux/gpio/driver.h>\n+#include <linux/irq.h>\n+#include <linux/minmax.h>\n+#include <linux/mod_devicetable.h>\n+#include <linux/module.h>\n+#include <linux/platform_device.h>\n+#include <linux/property.h>\n+\n+/*\n+ * Total register block size is 0x1C for one bank of four ports (A, B, C, D).\n+ * An optional second bank, with ports E, F, G, and H, may be present, starting\n+ * at register offset 0x1C.\n+ */\n+\n+/*\n+ * Pin select: (0) \"normal\", (1) \"dedicate peripheral\"\n+ * Not used on RTL8380/RTL8390, peripheral selection is managed by control bits\n+ * in the peripheral registers.\n+ */\n+#define REALTEK_GPIO_REG_CNR\t\t0x00\n+/* Clear bit (0) for input, set bit (1) for output */\n+#define REALTEK_GPIO_REG_DIR\t\t0x08\n+#define REALTEK_GPIO_REG_DATA\t\t0x0C\n+/* Read bit for IRQ status, write 1 to clear IRQ */\n+#define REALTEK_GPIO_REG_ISR\t\t0x10\n+/* Two bits per GPIO in IMR registers */\n+#define REALTEK_GPIO_REG_IMR\t\t0x14\n+#define REALTEK_GPIO_REG_IMR_AB\t\t0x14\n+#define REALTEK_GPIO_REG_IMR_CD\t\t0x18\n+#define REALTEK_GPIO_IMR_LINE_MASK\tGENMASK(1, 0)\n+#define REALTEK_GPIO_IRQ_EDGE_FALLING\t1\n+#define REALTEK_GPIO_IRQ_EDGE_RISING\t2\n+#define REALTEK_GPIO_IRQ_EDGE_BOTH\t3\n+\n+#define REALTEK_GPIO_MAX\t\t32\n+#define REALTEK_GPIO_PORTS_PER_BANK\t4\n+\n+/**\n+ * realtek_gpio_ctrl - Realtek Otto GPIO driver data\n+ *\n+ * @gc: Associated gpio_chip instance\n+ * @base: Base address of the register block for a GPIO bank\n+ * @lock: Lock for accessing the IRQ registers and values\n+ * @intr_mask: Mask for interrupts lines\n+ * @intr_type: Interrupt type selection\n+ *\n+ * Because the interrupt mask register (IMR) combines the function of IRQ type\n+ * selection and masking, two extra values are stored. @intr_mask is used to\n+ * mask/unmask the interrupts for a GPIO port, and @intr_type is used to store\n+ * the selected interrupt types. The logical AND of these values is written to\n+ * IMR on changes.\n+ */\n+struct realtek_gpio_ctrl {\n+\tstruct gpio_chip gc;\n+\tvoid __iomem *base;\n+\traw_spinlock_t lock;\n+\tu16 intr_mask[REALTEK_GPIO_PORTS_PER_BANK];\n+\tu16 intr_type[REALTEK_GPIO_PORTS_PER_BANK];\n+};\n+\n+/* Expand with more flags as devices with other quirks are added */\n+enum realtek_gpio_flags {\n+\t/*\n+\t * Allow disabling interrupts, for cases where the port order is\n+\t * unknown. This may result in a port mismatch between ISR and IMR.\n+\t * An interrupt would appear to come from a different line than the\n+\t * line the IRQ handler was assigned to, causing uncaught interrupts.\n+\t */\n+\tGPIO_INTERRUPTS_DISABLED = BIT(0),\n+};\n+\n+static struct realtek_gpio_ctrl *irq_data_to_ctrl(struct irq_data *data)\n+{\n+\tstruct gpio_chip *gc = irq_data_get_irq_chip_data(data);\n+\n+\treturn container_of(gc, struct realtek_gpio_ctrl, gc);\n+}\n+\n+/*\n+ * Normal port order register access\n+ *\n+ * Port information is stored with the first port at offset 0, followed by the\n+ * second, etc. Most registers store one bit per GPIO and use a u8 value per\n+ * port. The two interrupt mask registers store two bits per GPIO, so use u16\n+ * values.\n+ */\n+static void realtek_gpio_write_imr(struct realtek_gpio_ctrl *ctrl,\n+\tunsigned int port, u16 irq_type, u16 irq_mask)\n+{\n+\tiowrite16(irq_type & irq_mask, ctrl->base + REALTEK_GPIO_REG_IMR + 2 * port);\n+}\n+\n+static void realtek_gpio_clear_isr(struct realtek_gpio_ctrl *ctrl,\n+\tunsigned int port, u8 mask)\n+{\n+\tiowrite8(mask, ctrl->base + REALTEK_GPIO_REG_ISR + port);\n+}\n+\n+static u8 realtek_gpio_read_isr(struct realtek_gpio_ctrl *ctrl, unsigned int port)\n+{\n+\treturn ioread8(ctrl->base + REALTEK_GPIO_REG_ISR + port);\n+}\n+\n+/* Set the rising and falling edge mask bits for a GPIO port pin */\n+static u16 realtek_gpio_imr_bits(unsigned int pin, u16 value)\n+{\n+\treturn (value & REALTEK_GPIO_IMR_LINE_MASK) << 2 * pin;\n+}\n+\n+static void realtek_gpio_irq_ack(struct irq_data *data)\n+{\n+\tstruct realtek_gpio_ctrl *ctrl = irq_data_to_ctrl(data);\n+\tirq_hw_number_t line = irqd_to_hwirq(data);\n+\tunsigned int port = line / 8;\n+\tunsigned int port_pin = line % 8;\n+\n+\trealtek_gpio_clear_isr(ctrl, port, BIT(port_pin));\n+}\n+\n+static void realtek_gpio_irq_unmask(struct irq_data *data)\n+{\n+\tstruct realtek_gpio_ctrl *ctrl = irq_data_to_ctrl(data);\n+\tunsigned int line = irqd_to_hwirq(data);\n+\tunsigned int port = line / 8;\n+\tunsigned int port_pin = line % 8;\n+\tunsigned long flags;\n+\tu16 m;\n+\n+\traw_spin_lock_irqsave(&ctrl->lock, flags);\n+\tm = ctrl->intr_mask[port];\n+\tm |= realtek_gpio_imr_bits(port_pin, REALTEK_GPIO_IMR_LINE_MASK);\n+\tctrl->intr_mask[port] = m;\n+\trealtek_gpio_write_imr(ctrl, port, ctrl->intr_type[port], m);\n+\traw_spin_unlock_irqrestore(&ctrl->lock, flags);\n+}\n+\n+static void realtek_gpio_irq_mask(struct irq_data *data)\n+{\n+\tstruct realtek_gpio_ctrl *ctrl = irq_data_to_ctrl(data);\n+\tunsigned int line = irqd_to_hwirq(data);\n+\tunsigned int port = line / 8;\n+\tunsigned int port_pin = line % 8;\n+\tunsigned long flags;\n+\tu16 m;\n+\n+\traw_spin_lock_irqsave(&ctrl->lock, flags);\n+\tm = ctrl->intr_mask[port];\n+\tm &= ~realtek_gpio_imr_bits(port_pin, REALTEK_GPIO_IMR_LINE_MASK);\n+\tctrl->intr_mask[port] = m;\n+\trealtek_gpio_write_imr(ctrl, port, ctrl->intr_type[port], m);\n+\traw_spin_unlock_irqrestore(&ctrl->lock, flags);\n+}\n+\n+static int realtek_gpio_irq_set_type(struct irq_data *data, unsigned int flow_type)\n+{\n+\tstruct realtek_gpio_ctrl *ctrl = irq_data_to_ctrl(data);\n+\tunsigned int line = irqd_to_hwirq(data);\n+\tunsigned int port = line / 8;\n+\tunsigned int port_pin = line % 8;\n+\tunsigned long flags;\n+\tu16 type, t;\n+\n+\tswitch (flow_type & IRQ_TYPE_SENSE_MASK) {\n+\tcase IRQ_TYPE_EDGE_FALLING:\n+\t\ttype = REALTEK_GPIO_IRQ_EDGE_FALLING;\n+\t\tbreak;\n+\tcase IRQ_TYPE_EDGE_RISING:\n+\t\ttype = REALTEK_GPIO_IRQ_EDGE_RISING;\n+\t\tbreak;\n+\tcase IRQ_TYPE_EDGE_BOTH:\n+\t\ttype = REALTEK_GPIO_IRQ_EDGE_BOTH;\n+\t\tbreak;\n+\tdefault:\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tirq_set_handler_locked(data, handle_edge_irq);\n+\n+\traw_spin_lock_irqsave(&ctrl->lock, flags);\n+\tt = ctrl->intr_type[port];\n+\tt &= ~realtek_gpio_imr_bits(port_pin, REALTEK_GPIO_IMR_LINE_MASK);\n+\tt |= realtek_gpio_imr_bits(port_pin, type);\n+\tctrl->intr_type[port] = t;\n+\trealtek_gpio_write_imr(ctrl, port, t, ctrl->intr_mask[port]);\n+\traw_spin_unlock_irqrestore(&ctrl->lock, flags);\n+\n+\treturn 0;\n+}\n+\n+static void realtek_gpio_irq_handler(struct irq_desc *desc)\n+{\n+\tstruct gpio_chip *gc = irq_desc_get_handler_data(desc);\n+\tstruct realtek_gpio_ctrl *ctrl = gpiochip_get_data(gc);\n+\tstruct irq_chip *irq_chip = irq_desc_get_chip(desc);\n+\tunsigned int lines_done;\n+\tunsigned int port_pin_count;\n+\tunsigned int irq;\n+\tunsigned long status;\n+\tint offset;\n+\n+\tchained_irq_enter(irq_chip, desc);\n+\n+\tfor (lines_done = 0; lines_done < gc->ngpio; lines_done += 8) {\n+\t\tstatus = realtek_gpio_read_isr(ctrl, lines_done / 8);\n+\t\tport_pin_count = min(gc->ngpio - lines_done, 8U);\n+\t\tfor_each_set_bit(offset, &status, port_pin_count) {\n+\t\t\tirq = irq_find_mapping(gc->irq.domain, offset);\n+\t\t\tgeneric_handle_irq(irq);\n+\t\t}\n+\t}\n+\n+\tchained_irq_exit(irq_chip, desc);\n+}\n+\n+static int realtek_gpio_irq_init(struct gpio_chip *gc)\n+{\n+\tstruct realtek_gpio_ctrl *ctrl = gpiochip_get_data(gc);\n+\tunsigned int port;\n+\n+\tfor (port = 0; (port * 8) < gc->ngpio; port++) {\n+\t\trealtek_gpio_write_imr(ctrl, port, 0, 0);\n+\t\trealtek_gpio_clear_isr(ctrl, port, GENMASK(7, 0));\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static struct irq_chip realtek_gpio_irq_chip = {\n+\t.name = \"realtek-otto-gpio\",\n+\t.irq_ack = realtek_gpio_irq_ack,\n+\t.irq_mask = realtek_gpio_irq_mask,\n+\t.irq_unmask = realtek_gpio_irq_unmask,\n+\t.irq_set_type = realtek_gpio_irq_set_type,\n+};\n+\n+static const struct of_device_id realtek_gpio_of_match[] = {\n+\t{\n+\t\t.compatible = \"realtek,otto-gpio\",\n+\t\t.data = (void *)GPIO_INTERRUPTS_DISABLED,\n+\t},\n+\t{\n+\t\t.compatible = \"realtek,rtl8380-gpio\",\n+\t},\n+\t{\n+\t\t.compatible = \"realtek,rtl8390-gpio\",\n+\t},\n+\t{}\n+};\n+MODULE_DEVICE_TABLE(of, realtek_gpio_of_match);\n+\n+static int realtek_gpio_probe(struct platform_device *pdev)\n+{\n+\tstruct device *dev = &pdev->dev;\n+\tunsigned int dev_flags;\n+\tstruct gpio_irq_chip *girq;\n+\tstruct realtek_gpio_ctrl *ctrl;\n+\tu32 ngpios;\n+\tint err, irq;\n+\n+\tctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);\n+\tif (!ctrl)\n+\t\treturn -ENOMEM;\n+\n+\tdev_flags = (unsigned int) device_get_match_data(dev);\n+\n+\tngpios = REALTEK_GPIO_MAX;\n+\tdevice_property_read_u32(dev, \"ngpios\", &ngpios);\n+\n+\tif (ngpios > REALTEK_GPIO_MAX) {\n+\t\tdev_err(&pdev->dev, \"invalid ngpios (max. %d)\\n\",\n+\t\t\tREALTEK_GPIO_MAX);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tctrl->base = devm_platform_ioremap_resource(pdev, 0);\n+\tif (IS_ERR(ctrl->base))\n+\t\treturn PTR_ERR(ctrl->base);\n+\n+\traw_spin_lock_init(&ctrl->lock);\n+\n+\terr = bgpio_init(&ctrl->gc, dev, 4,\n+\t\tctrl->base + REALTEK_GPIO_REG_DATA, NULL, NULL,\n+\t\tctrl->base + REALTEK_GPIO_REG_DIR, NULL,\n+\t\tBGPIOF_BIG_ENDIAN_BYTE_ORDER);\n+\tif (err) {\n+\t\tdev_err(dev, \"unable to init generic GPIO\");\n+\t\treturn err;\n+\t}\n+\n+\tctrl->gc.ngpio = ngpios;\n+\tctrl->gc.owner = THIS_MODULE;\n+\n+\tirq = platform_get_irq_optional(pdev, 0);\n+\tif (!(dev_flags & GPIO_INTERRUPTS_DISABLED) && irq > 0) {\n+\t\tgirq = &ctrl->gc.irq;\n+\t\tgirq->chip = &realtek_gpio_irq_chip;\n+\t\tgirq->default_type = IRQ_TYPE_NONE;\n+\t\tgirq->handler = handle_bad_irq;\n+\t\tgirq->parent_handler = realtek_gpio_irq_handler;\n+\t\tgirq->num_parents = 1;\n+\t\tgirq->parents = devm_kcalloc(dev, girq->num_parents,\n+\t\t\t\t\tsizeof(*girq->parents),\tGFP_KERNEL);\n+\t\tif (!girq->parents)\n+\t\t\treturn -ENOMEM;\n+\t\tgirq->parents[0] = irq;\n+\t\tgirq->init_hw = realtek_gpio_irq_init;\n+\t}\n+\n+\treturn devm_gpiochip_add_data(dev, &ctrl->gc, ctrl);\n+}\n+\n+static struct platform_driver realtek_gpio_driver = {\n+\t.driver = {\n+\t\t.name = \"realtek-otto-gpio\",\n+\t\t.of_match_table\t= realtek_gpio_of_match,\n+\t},\n+\t.probe = realtek_gpio_probe,\n+};\n+module_platform_driver(realtek_gpio_driver);\n+\n+MODULE_DESCRIPTION(\"Realtek Otto GPIO support\");\n+MODULE_AUTHOR(\"Sander Vanheule <sander@svanheule.net>\");\n+MODULE_LICENSE(\"GPL v2\");\n"
  },
  {
    "path": "target/linux/realtek/patches-5.10/003-5.12-spi-realtek-rtl838x-rtl839x-spi-controller.patch",
    "content": "From 6acbd614c2c8d3b8de5fb7605d6e24b9b3a8a17b Mon Sep 17 00:00:00 2001\nFrom: Bert Vermeulen <bert@biot.com>\nDate: Wed, 20 Jan 2021 14:59:27 +0100\nSubject: spi: Realtek RTL838x/RTL839x SPI controller\n\nSigned-off-by: Bert Vermeulen <bert@biot.com>\nLink: https://lore.kernel.org/r/20210120135928.246054-2-bert@biot.com\nSigned-off-by: Mark Brown <broonie@kernel.org>\n---\n .../devicetree/bindings/spi/realtek,rtl-spi.yaml   | 41 ++++++++++++++++++++++\n 1 file changed, 41 insertions(+)\n create mode 100644 Documentation/devicetree/bindings/spi/realtek,rtl-spi.yaml\n\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/spi/realtek,rtl-spi.yaml\n@@ -0,0 +1,41 @@\n+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)\n+%YAML 1.2\n+---\n+$id: http://devicetree.org/schemas/spi/realtek,rtl-spi.yaml#\n+$schema: http://devicetree.org/meta-schemas/core.yaml#\n+\n+title: Realtek RTL838x/RTL839x SPI controller\n+\n+maintainers:\n+  - Bert Vermeulen <bert@biot.com>\n+  - Birger Koblitz <mail@birger-koblitz.de>\n+\n+allOf:\n+  - $ref: \"spi-controller.yaml#\"\n+\n+properties:\n+  compatible:\n+    oneOf:\n+      - const: realtek,rtl8380-spi\n+      - const: realtek,rtl8382-spi\n+      - const: realtek,rtl8391-spi\n+      - const: realtek,rtl8392-spi\n+      - const: realtek,rtl8393-spi\n+\n+  reg:\n+    maxItems: 1\n+\n+required:\n+  - compatible\n+  - reg\n+\n+unevaluatedProperties: false\n+\n+examples:\n+  - |\n+    spi: spi@1200 {\n+        compatible = \"realtek,rtl8382-spi\";\n+        reg = <0x1200 0x100>;\n+        #address-cells = <1>;\n+        #size-cells = <0>;\n+    };\n"
  },
  {
    "path": "target/linux/realtek/patches-5.10/004-5.12-spi-realtek-rtl-add-support-for-realtek-rtl838x-rtl839x-spi-controllers.patch",
    "content": "From a8af5cc2ff1e804694629a8ef320935629dd15ba Mon Sep 17 00:00:00 2001\nFrom: Bert Vermeulen <bert@biot.com>\nDate: Wed, 20 Jan 2021 14:59:28 +0100\nSubject: spi: realtek-rtl: Add support for Realtek RTL838x/RTL839x SPI\n controllers\n\nThis driver likely also supports earlier (RTL8196) and later (RTL93xx)\nSoCs.\n\nThe SPI hardware in these SoCs is specifically intended for connecting NOR\nbootflash chips, and only used for that in dozens of examined devices.\nHowever boiled down to basics, it's really just a half-duplex SPI\ncontroller.\n\nThe hardware appears to have a vestigial second chip-select control, but\nit hasn't been seen in the wild and is thus not supported.\n\nSigned-off-by: Bert Vermeulen <bert@biot.com>\nLink: https://lore.kernel.org/r/20210120135928.246054-3-bert@biot.com\nSigned-off-by: Mark Brown <broonie@kernel.org>\n---\n drivers/spi/Makefile          |   1 +\n drivers/spi/spi-realtek-rtl.c | 209 ++++++++++++++++++++++++++++++++++++++++++\n 2 files changed, 210 insertions(+)\n create mode 100644 drivers/spi/spi-realtek-rtl.c\n\n--- a/drivers/spi/Makefile\n+++ b/drivers/spi/Makefile\n@@ -94,6 +94,7 @@ obj-$(CONFIG_SPI_QCOM_QSPI)\t\t+= spi-qcom\n obj-$(CONFIG_SPI_QUP)\t\t\t+= spi-qup.o\n obj-$(CONFIG_SPI_ROCKCHIP)\t\t+= spi-rockchip.o\n obj-$(CONFIG_SPI_RB4XX)\t\t\t+= spi-rb4xx.o\n+obj-$(CONFIG_MACH_REALTEK_RTL)\t\t+= spi-realtek-rtl.o\n obj-$(CONFIG_SPI_RPCIF)\t\t\t+= spi-rpc-if.o\n obj-$(CONFIG_SPI_RSPI)\t\t\t+= spi-rspi.o\n obj-$(CONFIG_SPI_S3C24XX)\t\t+= spi-s3c24xx-hw.o\n--- /dev/null\n+++ b/drivers/spi/spi-realtek-rtl.c\n@@ -0,0 +1,209 @@\n+// SPDX-License-Identifier: GPL-2.0-only\n+\n+#include <linux/module.h>\n+#include <linux/platform_device.h>\n+#include <linux/mod_devicetable.h>\n+#include <linux/spi/spi.h>\n+\n+struct rtspi {\n+\tvoid __iomem *base;\n+};\n+\n+/* SPI Flash Configuration Register */\n+#define RTL_SPI_SFCR\t\t\t0x00\n+#define RTL_SPI_SFCR_RBO\t\tBIT(28)\n+#define RTL_SPI_SFCR_WBO\t\tBIT(27)\n+\n+/* SPI Flash Control and Status Register */\n+#define RTL_SPI_SFCSR\t\t\t0x08\n+#define RTL_SPI_SFCSR_CSB0\t\tBIT(31)\n+#define RTL_SPI_SFCSR_CSB1\t\tBIT(30)\n+#define RTL_SPI_SFCSR_RDY\t\tBIT(27)\n+#define RTL_SPI_SFCSR_CS\t\tBIT(24)\n+#define RTL_SPI_SFCSR_LEN_MASK\t\t~(0x03 << 28)\n+#define RTL_SPI_SFCSR_LEN1\t\t(0x00 << 28)\n+#define RTL_SPI_SFCSR_LEN4\t\t(0x03 << 28)\n+\n+/* SPI Flash Data Register */\n+#define RTL_SPI_SFDR\t\t\t0x0c\n+\n+#define REG(x)\t\t(rtspi->base + x)\n+\n+\n+static void rt_set_cs(struct spi_device *spi, bool active)\n+{\n+\tstruct rtspi *rtspi = spi_controller_get_devdata(spi->controller);\n+\tu32 value;\n+\n+\t/* CS0 bit is active low */\n+\tvalue = readl(REG(RTL_SPI_SFCSR));\n+\tif (active)\n+\t\tvalue |= RTL_SPI_SFCSR_CSB0;\n+\telse\n+\t\tvalue &= ~RTL_SPI_SFCSR_CSB0;\n+\twritel(value, REG(RTL_SPI_SFCSR));\n+}\n+\n+static void set_size(struct rtspi *rtspi, int size)\n+{\n+\tu32 value;\n+\n+\tvalue = readl(REG(RTL_SPI_SFCSR));\n+\tvalue &= RTL_SPI_SFCSR_LEN_MASK;\n+\tif (size == 4)\n+\t\tvalue |= RTL_SPI_SFCSR_LEN4;\n+\telse if (size == 1)\n+\t\tvalue |= RTL_SPI_SFCSR_LEN1;\n+\twritel(value, REG(RTL_SPI_SFCSR));\n+}\n+\n+static inline void wait_ready(struct rtspi *rtspi)\n+{\n+\twhile (!(readl(REG(RTL_SPI_SFCSR)) & RTL_SPI_SFCSR_RDY))\n+\t\tcpu_relax();\n+}\n+static void send4(struct rtspi *rtspi, const u32 *buf)\n+{\n+\twait_ready(rtspi);\n+\tset_size(rtspi, 4);\n+\twritel(*buf, REG(RTL_SPI_SFDR));\n+}\n+\n+static void send1(struct rtspi *rtspi, const u8 *buf)\n+{\n+\twait_ready(rtspi);\n+\tset_size(rtspi, 1);\n+\twritel(buf[0] << 24, REG(RTL_SPI_SFDR));\n+}\n+\n+static void rcv4(struct rtspi *rtspi, u32 *buf)\n+{\n+\twait_ready(rtspi);\n+\tset_size(rtspi, 4);\n+\t*buf = readl(REG(RTL_SPI_SFDR));\n+}\n+\n+static void rcv1(struct rtspi *rtspi, u8 *buf)\n+{\n+\twait_ready(rtspi);\n+\tset_size(rtspi, 1);\n+\t*buf = readl(REG(RTL_SPI_SFDR)) >> 24;\n+}\n+\n+static int transfer_one(struct spi_controller *ctrl, struct spi_device *spi,\n+\t\t\tstruct spi_transfer *xfer)\n+{\n+\tstruct rtspi *rtspi = spi_controller_get_devdata(ctrl);\n+\tvoid *rx_buf;\n+\tconst void *tx_buf;\n+\tint cnt;\n+\n+\ttx_buf = xfer->tx_buf;\n+\trx_buf = xfer->rx_buf;\n+\tcnt = xfer->len;\n+\tif (tx_buf) {\n+\t\twhile (cnt >= 4) {\n+\t\t\tsend4(rtspi, tx_buf);\n+\t\t\ttx_buf += 4;\n+\t\t\tcnt -= 4;\n+\t\t}\n+\t\twhile (cnt) {\n+\t\t\tsend1(rtspi, tx_buf);\n+\t\t\ttx_buf++;\n+\t\t\tcnt--;\n+\t\t}\n+\t} else if (rx_buf) {\n+\t\twhile (cnt >= 4) {\n+\t\t\trcv4(rtspi, rx_buf);\n+\t\t\trx_buf += 4;\n+\t\t\tcnt -= 4;\n+\t\t}\n+\t\twhile (cnt) {\n+\t\t\trcv1(rtspi, rx_buf);\n+\t\t\trx_buf++;\n+\t\t\tcnt--;\n+\t\t}\n+\t}\n+\n+\tspi_finalize_current_transfer(ctrl);\n+\n+\treturn 0;\n+}\n+\n+static void init_hw(struct rtspi *rtspi)\n+{\n+\tu32 value;\n+\n+\t/* Turn on big-endian byte ordering */\n+\tvalue = readl(REG(RTL_SPI_SFCR));\n+\tvalue |= RTL_SPI_SFCR_RBO | RTL_SPI_SFCR_WBO;\n+\twritel(value, REG(RTL_SPI_SFCR));\n+\n+\tvalue = readl(REG(RTL_SPI_SFCSR));\n+\t/* Permanently disable CS1, since it's never used */\n+\tvalue |= RTL_SPI_SFCSR_CSB1;\n+\t/* Select CS0 for use */\n+\tvalue &= RTL_SPI_SFCSR_CS;\n+\twritel(value, REG(RTL_SPI_SFCSR));\n+}\n+\n+static int realtek_rtl_spi_probe(struct platform_device *pdev)\n+{\n+\tstruct spi_controller *ctrl;\n+\tstruct rtspi *rtspi;\n+\tint err;\n+\n+\tctrl = devm_spi_alloc_master(&pdev->dev, sizeof(*rtspi));\n+\tif (!ctrl) {\n+\t\tdev_err(&pdev->dev, \"Error allocating SPI controller\\n\");\n+\t\treturn -ENOMEM;\n+\t}\n+\tplatform_set_drvdata(pdev, ctrl);\n+\trtspi = spi_controller_get_devdata(ctrl);\n+\n+\trtspi->base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);\n+\tif (IS_ERR(rtspi->base)) {\n+\t\tdev_err(&pdev->dev, \"Could not map SPI register address\");\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\tinit_hw(rtspi);\n+\n+\tctrl->dev.of_node = pdev->dev.of_node;\n+\tctrl->flags = SPI_CONTROLLER_HALF_DUPLEX;\n+\tctrl->set_cs = rt_set_cs;\n+\tctrl->transfer_one = transfer_one;\n+\n+\terr = devm_spi_register_controller(&pdev->dev, ctrl);\n+\tif (err) {\n+\t\tdev_err(&pdev->dev, \"Could not register SPI controller\\n\");\n+\t\treturn -ENODEV;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+\n+static const struct of_device_id realtek_rtl_spi_of_ids[] = {\n+\t{ .compatible = \"realtek,rtl8380-spi\" },\n+\t{ .compatible = \"realtek,rtl8382-spi\" },\n+\t{ .compatible = \"realtek,rtl8391-spi\" },\n+\t{ .compatible = \"realtek,rtl8392-spi\" },\n+\t{ .compatible = \"realtek,rtl8393-spi\" },\n+\t{ /* sentinel */ }\n+};\n+MODULE_DEVICE_TABLE(of, realtek_rtl_spi_of_ids);\n+\n+static struct platform_driver realtek_rtl_spi_driver = {\n+\t.probe = realtek_rtl_spi_probe,\n+\t.driver = {\n+\t\t.name = \"realtek-rtl-spi\",\n+\t\t.of_match_table = realtek_rtl_spi_of_ids,\n+\t},\n+};\n+\n+module_platform_driver(realtek_rtl_spi_driver);\n+\n+MODULE_LICENSE(\"GPL v2\");\n+MODULE_AUTHOR(\"Bert Vermeulen <bert@biot.com>\");\n+MODULE_DESCRIPTION(\"Realtek RTL SPI driver\");\n"
  },
  {
    "path": "target/linux/realtek/patches-5.10/005-5.12-dt-bindings-interrupt-controller-add-realtek-rtl838x-rtl839x-support.patch",
    "content": "From 4a2b92a5d3519fc2c1edda4d4aa0e05bff41e8de Mon Sep 17 00:00:00 2001\nFrom: Bert Vermeulen <bert@biot.com>\nDate: Fri, 22 Jan 2021 21:42:23 +0100\nSubject: dt-bindings: interrupt-controller: Add Realtek RTL838x/RTL839x\n support\n\nDocument the binding for the Realtek RTL838x/RTL839x interrupt controller.\n\nReviewed-by: Rob Herring <robh@kernel.org>\nSigned-off-by: Bert Vermeulen <bert@biot.com>\n[maz: Add a commit message, as the author couldn't be bothered...]\nSigned-off-by: Marc Zyngier <maz@kernel.org>\nLink: https://lore.kernel.org/r/20210122204224.509124-2-bert@biot.com\n---\n .../interrupt-controller/realtek,rtl-intc.yaml     | 57 ++++++++++++++++++++++\n 1 file changed, 57 insertions(+)\n create mode 100644 Documentation/devicetree/bindings/interrupt-controller/realtek,rtl-intc.yaml\n\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/interrupt-controller/realtek,rtl-intc.yaml\n@@ -0,0 +1,57 @@\n+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)\n+%YAML 1.2\n+---\n+$id: http://devicetree.org/schemas/interrupt-controller/realtek,rtl-intc.yaml#\n+$schema: http://devicetree.org/meta-schemas/core.yaml#\n+\n+title: Realtek RTL SoC interrupt controller devicetree bindings\n+\n+maintainers:\n+  - Birger Koblitz <mail@birger-koblitz.de>\n+  - Bert Vermeulen <bert@biot.com>\n+  - John Crispin <john@phrozen.org>\n+\n+properties:\n+  compatible:\n+    const: realtek,rtl-intc\n+\n+  \"#interrupt-cells\":\n+    const: 1\n+\n+  reg:\n+    maxItems: 1\n+\n+  interrupts:\n+    maxItems: 1\n+\n+  interrupt-controller: true\n+\n+  \"#address-cells\":\n+    const: 0\n+\n+  interrupt-map:\n+    description: Describes mapping from SoC interrupts to CPU interrupts\n+\n+required:\n+  - compatible\n+  - reg\n+  - \"#interrupt-cells\"\n+  - interrupt-controller\n+  - \"#address-cells\"\n+  - interrupt-map\n+\n+additionalProperties: false\n+\n+examples:\n+  - |\n+    intc: interrupt-controller@3000 {\n+      compatible = \"realtek,rtl-intc\";\n+      #interrupt-cells = <1>;\n+      interrupt-controller;\n+      reg = <0x3000 0x20>;\n+      #address-cells = <0>;\n+      interrupt-map =\n+              <31 &cpuintc 2>,\n+              <30 &cpuintc 1>,\n+              <29 &cpuintc 5>;\n+    };\n"
  },
  {
    "path": "target/linux/realtek/patches-5.10/006-5.12-irqchip-add-support-for-realtek-rtl838x-rtl839x-interrupt-controller.patch",
    "content": "From 9f3a0f34b84ad1b9a8f2bdae44b66f16685b2143 Mon Sep 17 00:00:00 2001\nFrom: Bert Vermeulen <bert@biot.com>\nDate: Fri, 22 Jan 2021 21:42:24 +0100\nSubject: irqchip: Add support for Realtek RTL838x/RTL839x interrupt controller\n\nThis is a standard IRQ driver with only status and mask registers.\n\nThe mapping from SoC interrupts (18-31) to MIPS core interrupts is\ndone via an interrupt-map in device tree.\n\nSigned-off-by: Bert Vermeulen <bert@biot.com>\nSigned-off-by: Birger Koblitz <mail@birger-koblitz.de>\nAcked-by: John Crispin <john@phrozen.org>\nSigned-off-by: Marc Zyngier <maz@kernel.org>\nLink: https://lore.kernel.org/r/20210122204224.509124-3-bert@biot.com\n---\n drivers/irqchip/Makefile          |   1 +\n drivers/irqchip/irq-realtek-rtl.c | 180 ++++++++++++++++++++++++++++++++++++++\n 2 files changed, 181 insertions(+)\n create mode 100644 drivers/irqchip/irq-realtek-rtl.c\n\n--- a/drivers/irqchip/Makefile\n+++ b/drivers/irqchip/Makefile\n@@ -114,3 +114,4 @@ obj-$(CONFIG_LOONGSON_PCH_PIC)\t\t+= irq-l\n obj-$(CONFIG_LOONGSON_PCH_MSI)\t\t+= irq-loongson-pch-msi.o\n obj-$(CONFIG_MST_IRQ)\t\t\t+= irq-mst-intc.o\n obj-$(CONFIG_SL28CPLD_INTC)\t\t+= irq-sl28cpld.o\n+obj-$(CONFIG_MACH_REALTEK_RTL)\t\t+= irq-realtek-rtl.o\n--- /dev/null\n+++ b/drivers/irqchip/irq-realtek-rtl.c\n@@ -0,0 +1,180 @@\n+// SPDX-License-Identifier: GPL-2.0-only\n+/*\n+ * Copyright (C) 2020 Birger Koblitz <mail@birger-koblitz.de>\n+ * Copyright (C) 2020 Bert Vermeulen <bert@biot.com>\n+ * Copyright (C) 2020 John Crispin <john@phrozen.org>\n+ */\n+\n+#include <linux/of_irq.h>\n+#include <linux/irqchip.h>\n+#include <linux/spinlock.h>\n+#include <linux/of_address.h>\n+#include <linux/irqchip/chained_irq.h>\n+\n+/* Global Interrupt Mask Register */\n+#define RTL_ICTL_GIMR\t\t0x00\n+/* Global Interrupt Status Register */\n+#define RTL_ICTL_GISR\t\t0x04\n+/* Interrupt Routing Registers */\n+#define RTL_ICTL_IRR0\t\t0x08\n+#define RTL_ICTL_IRR1\t\t0x0c\n+#define RTL_ICTL_IRR2\t\t0x10\n+#define RTL_ICTL_IRR3\t\t0x14\n+\n+#define REG(x)\t\t(realtek_ictl_base + x)\n+\n+static DEFINE_RAW_SPINLOCK(irq_lock);\n+static void __iomem *realtek_ictl_base;\n+\n+static void realtek_ictl_unmask_irq(struct irq_data *i)\n+{\n+\tunsigned long flags;\n+\tu32 value;\n+\n+\traw_spin_lock_irqsave(&irq_lock, flags);\n+\n+\tvalue = readl(REG(RTL_ICTL_GIMR));\n+\tvalue |= BIT(i->hwirq);\n+\twritel(value, REG(RTL_ICTL_GIMR));\n+\n+\traw_spin_unlock_irqrestore(&irq_lock, flags);\n+}\n+\n+static void realtek_ictl_mask_irq(struct irq_data *i)\n+{\n+\tunsigned long flags;\n+\tu32 value;\n+\n+\traw_spin_lock_irqsave(&irq_lock, flags);\n+\n+\tvalue = readl(REG(RTL_ICTL_GIMR));\n+\tvalue &= ~BIT(i->hwirq);\n+\twritel(value, REG(RTL_ICTL_GIMR));\n+\n+\traw_spin_unlock_irqrestore(&irq_lock, flags);\n+}\n+\n+static struct irq_chip realtek_ictl_irq = {\n+\t.name = \"realtek-rtl-intc\",\n+\t.irq_mask = realtek_ictl_mask_irq,\n+\t.irq_unmask = realtek_ictl_unmask_irq,\n+};\n+\n+static int intc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)\n+{\n+\tirq_set_chip_and_handler(hw, &realtek_ictl_irq, handle_level_irq);\n+\n+\treturn 0;\n+}\n+\n+static const struct irq_domain_ops irq_domain_ops = {\n+\t.map = intc_map,\n+\t.xlate = irq_domain_xlate_onecell,\n+};\n+\n+static void realtek_irq_dispatch(struct irq_desc *desc)\n+{\n+\tstruct irq_chip *chip = irq_desc_get_chip(desc);\n+\tstruct irq_domain *domain;\n+\tunsigned int pending;\n+\n+\tchained_irq_enter(chip, desc);\n+\tpending = readl(REG(RTL_ICTL_GIMR)) & readl(REG(RTL_ICTL_GISR));\n+\tif (unlikely(!pending)) {\n+\t\tspurious_interrupt();\n+\t\tgoto out;\n+\t}\n+\tdomain = irq_desc_get_handler_data(desc);\n+\tgeneric_handle_irq(irq_find_mapping(domain, __ffs(pending)));\n+\n+out:\n+\tchained_irq_exit(chip, desc);\n+}\n+\n+/*\n+ * SoC interrupts are cascaded to MIPS CPU interrupts according to the\n+ * interrupt-map in the device tree. Each SoC interrupt gets 4 bits for\n+ * the CPU interrupt in an Interrupt Routing Register. Max 32 SoC interrupts\n+ * thus go into 4 IRRs.\n+ */\n+static int __init map_interrupts(struct device_node *node, struct irq_domain *domain)\n+{\n+\tstruct device_node *cpu_ictl;\n+\tconst __be32 *imap;\n+\tu32 imaplen, soc_int, cpu_int, tmp, regs[4];\n+\tint ret, i, irr_regs[] = {\n+\t\tRTL_ICTL_IRR3,\n+\t\tRTL_ICTL_IRR2,\n+\t\tRTL_ICTL_IRR1,\n+\t\tRTL_ICTL_IRR0,\n+\t};\n+\tu8 mips_irqs_set;\n+\n+\tret = of_property_read_u32(node, \"#address-cells\", &tmp);\n+\tif (ret || tmp)\n+\t\treturn -EINVAL;\n+\n+\timap = of_get_property(node, \"interrupt-map\", &imaplen);\n+\tif (!imap || imaplen % 3)\n+\t\treturn -EINVAL;\n+\n+\tmips_irqs_set = 0;\n+\tmemset(regs, 0, sizeof(regs));\n+\tfor (i = 0; i < imaplen; i += 3 * sizeof(u32)) {\n+\t\tsoc_int = be32_to_cpup(imap);\n+\t\tif (soc_int > 31)\n+\t\t\treturn -EINVAL;\n+\n+\t\tcpu_ictl = of_find_node_by_phandle(be32_to_cpup(imap + 1));\n+\t\tif (!cpu_ictl)\n+\t\t\treturn -EINVAL;\n+\t\tret = of_property_read_u32(cpu_ictl, \"#interrupt-cells\", &tmp);\n+\t\tif (ret || tmp != 1)\n+\t\t\treturn -EINVAL;\n+\t\tof_node_put(cpu_ictl);\n+\n+\t\tcpu_int = be32_to_cpup(imap + 2);\n+\t\tif (cpu_int > 7)\n+\t\t\treturn -EINVAL;\n+\n+\t\tif (!(mips_irqs_set & BIT(cpu_int))) {\n+\t\t\tirq_set_chained_handler_and_data(cpu_int, realtek_irq_dispatch,\n+\t\t\t\t\t\t\t domain);\n+\t\t\tmips_irqs_set |= BIT(cpu_int);\n+\t\t}\n+\n+\t\tregs[(soc_int * 4) / 32] |= cpu_int << (soc_int * 4) % 32;\n+\t\timap += 3;\n+\t}\n+\n+\tfor (i = 0; i < 4; i++)\n+\t\twritel(regs[i], REG(irr_regs[i]));\n+\n+\treturn 0;\n+}\n+\n+static int __init realtek_rtl_of_init(struct device_node *node, struct device_node *parent)\n+{\n+\tstruct irq_domain *domain;\n+\tint ret;\n+\n+\trealtek_ictl_base = of_iomap(node, 0);\n+\tif (!realtek_ictl_base)\n+\t\treturn -ENXIO;\n+\n+\t/* Disable all cascaded interrupts */\n+\twritel(0, REG(RTL_ICTL_GIMR));\n+\n+\tdomain = irq_domain_add_simple(node, 32, 0,\n+\t\t\t\t       &irq_domain_ops, NULL);\n+\n+\tret = map_interrupts(node, domain);\n+\tif (ret) {\n+\t\tpr_err(\"invalid interrupt map\\n\");\n+\t\treturn ret;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+IRQCHIP_DECLARE(realtek_rtl_intc, \"realtek,rtl-intc\", realtek_rtl_of_init);\n"
  },
  {
    "path": "target/linux/realtek/patches-5.10/007-5.16-gpio-realtek-realtek-otto-fix-gpio-line-irq-offset.patch",
    "content": "gpio: realtek-otto: fix GPIO line IRQ offset\n\nThe irqchip uses one domain for all GPIO lines, so th line offset should be\ndetermined w.r.t. the first line of the first port, not the first line of the\ntriggered port.\n\nFixes: 0d82fb1127fb (\"gpio: Add Realtek Otto GPIO support\")\nSigned-off-by: Sander Vanheule <sander@svanheule.net>\nLink: https://lore.kernel.org/linux-gpio/20211028085243.34360-1-sander@svanheule.net/\n\n--- a/drivers/gpio/gpio-realtek-otto.c\n+++ b/drivers/gpio/gpio-realtek-otto.c\n@@ -206,7 +206,7 @@ static void realtek_gpio_irq_handler(str\n \t\tstatus = realtek_gpio_read_isr(ctrl, lines_done / 8);\n \t\tport_pin_count = min(gc->ngpio - lines_done, 8U);\n \t\tfor_each_set_bit(offset, &status, port_pin_count) {\n-\t\t\tirq = irq_find_mapping(gc->irq.domain, offset);\n+\t\t\tirq = irq_find_mapping(gc->irq.domain, offset + lines_done);\n \t\t\tgeneric_handle_irq(irq);\n \t\t}\n \t}\n"
  },
  {
    "path": "target/linux/realtek/patches-5.10/008-5.17-watchdog-add-realtek-otto-watchdog-timer.patch",
    "content": "From 293903b9dfe43520f01374dc1661be11d6838c49 Mon Sep 17 00:00:00 2001\nFrom: Sander Vanheule <sander@svanheule.net>\nDate: Thu, 18 Nov 2021 17:29:52 +0100\nSubject: watchdog: Add Realtek Otto watchdog timer\n\nRealtek MIPS SoCs (platform name Otto) have a watchdog timer with\npretimeout notifitication support. The WDT can (partially) hard reset,\nor soft reset the SoC.\n\nThis driver implements all features as described in the devicetree\nbinding, except the phase2 interrupt, and also functions as a restart\nhandler. The cpu reset mode is considered to be a \"warm\" restart, since\nthis mode does not reset all peripherals. Being an embedded system\nthough, the \"cpu\" and \"software\" modes will still cause the bootloader\nto run on restart.\n\nIt is not known how a forced system reset can be disabled on the\nsupported platforms. This means that the phase2 interrupt will only fire\nat the same time as reset, so implementing phase2 is of little use.\n\nSigned-off-by: Sander Vanheule <sander@svanheule.net>\nReviewed-by: Guenter Roeck <linux@roeck-us.net>\nLink: https://lore.kernel.org/r/6d060bccbdcc709cfa79203485db85aad3c3beb5.1637252610.git.sander@svanheule.net\nSigned-off-by: Guenter Roeck <linux@roeck-us.net>\n---\n MAINTAINERS                         |   7 +\n drivers/watchdog/Kconfig            |  13 ++\n drivers/watchdog/Makefile           |   1 +\n drivers/watchdog/realtek_otto_wdt.c | 384 ++++++++++++++++++++++++++++++++++++\n 4 files changed, 405 insertions(+)\n create mode 100644 drivers/watchdog/realtek_otto_wdt.c\n\n--- a/MAINTAINERS\n+++ b/MAINTAINERS\n@@ -14814,6 +14814,13 @@ S:\tMaintained\n F:\tinclude/sound/rt*.h\n F:\tsound/soc/codecs/rt*\n \n+REALTEK OTTO WATCHDOG\n+M:\tSander Vanheule <sander@svanheule.net>\n+L:\tlinux-watchdog@vger.kernel.org\n+S:\tMaintained\n+F:\tDocumentation/devicetree/bindings/watchdog/realtek,otto-wdt.yaml\n+F:\tdriver/watchdog/realtek_otto_wdt.c\n+\n REALTEK RTL83xx SMI DSA ROUTER CHIPS\n M:\tLinus Walleij <linus.walleij@linaro.org>\n S:\tMaintained\n--- a/drivers/watchdog/Kconfig\n+++ b/drivers/watchdog/Kconfig\n@@ -995,6 +995,19 @@ config RTD119X_WATCHDOG\n \t  Say Y here to include support for the watchdog timer in\n \t  Realtek RTD1295 SoCs.\n \n+config REALTEK_OTTO_WDT\n+\ttristate \"Realtek Otto MIPS watchdog support\"\n+\tdepends on MACH_REALTEK_RTL || COMPILE_TEST\n+\tdepends on COMMON_CLK\n+\tselect WATCHDOG_CORE\n+\tdefault MACH_REALTEK_RTL\n+\thelp\n+\t  Say Y here to include support for the watchdog timer on Realtek\n+\t  RTL838x, RTL839x, RTL930x SoCs. This watchdog has pretimeout\n+\t  notifications and system reset on timeout.\n+\n+\t  When built as a module this will be called realtek_otto_wdt.\n+\n config SPRD_WATCHDOG\n \ttristate \"Spreadtrum watchdog support\"\n \tdepends on ARCH_SPRD || COMPILE_TEST\n--- a/drivers/watchdog/Makefile\n+++ b/drivers/watchdog/Makefile\n@@ -174,6 +174,7 @@ obj-$(CONFIG_IMGPDC_WDT) += imgpdc_wdt.o\n obj-$(CONFIG_MT7621_WDT) += mt7621_wdt.o\n obj-$(CONFIG_PIC32_WDT) += pic32-wdt.o\n obj-$(CONFIG_PIC32_DMT) += pic32-dmt.o\n+obj-$(CONFIG_REALTEK_OTTO_WDT) += realtek_otto_wdt.o\n \n # PARISC Architecture\n \n--- /dev/null\n+++ b/drivers/watchdog/realtek_otto_wdt.c\n@@ -0,0 +1,384 @@\n+// SPDX-License-Identifier: GPL-2.0-only\n+\n+/*\n+ * Realtek Otto MIPS platform watchdog\n+ *\n+ * Watchdog timer that will reset the system after timeout, using the selected\n+ * reset mode.\n+ *\n+ * Counter scaling and timeouts:\n+ * - Base prescale of (2 << 25), providing tick duration T_0: 168ms @ 200MHz\n+ * - PRESCALE: logarithmic prescaler adding a factor of {1, 2, 4, 8}\n+ * - Phase 1: Times out after (PHASE1 + 1) × PRESCALE × T_0\n+ *   Generates an interrupt, WDT cannot be stopped after phase 1\n+ * - Phase 2: starts after phase 1, times out after (PHASE2 + 1) × PRESCALE × T_0\n+ *   Resets the system according to RST_MODE\n+ */\n+\n+#include <linux/bits.h>\n+#include <linux/bitfield.h>\n+#include <linux/clk.h>\n+#include <linux/delay.h>\n+#include <linux/interrupt.h>\n+#include <linux/io.h>\n+#include <linux/math.h>\n+#include <linux/minmax.h>\n+#include <linux/module.h>\n+#include <linux/mod_devicetable.h>\n+#include <linux/platform_device.h>\n+#include <linux/property.h>\n+#include <linux/reboot.h>\n+#include <linux/watchdog.h>\n+\n+#define OTTO_WDT_REG_CNTR\t\t0x0\n+#define OTTO_WDT_CNTR_PING\t\tBIT(31)\n+\n+#define OTTO_WDT_REG_INTR\t\t0x4\n+#define OTTO_WDT_INTR_PHASE_1\t\tBIT(31)\n+#define OTTO_WDT_INTR_PHASE_2\t\tBIT(30)\n+\n+#define OTTO_WDT_REG_CTRL\t\t0x8\n+#define OTTO_WDT_CTRL_ENABLE\t\tBIT(31)\n+#define OTTO_WDT_CTRL_PRESCALE\t\tGENMASK(30, 29)\n+#define OTTO_WDT_CTRL_PHASE1\t\tGENMASK(26, 22)\n+#define OTTO_WDT_CTRL_PHASE2\t\tGENMASK(19, 15)\n+#define OTTO_WDT_CTRL_RST_MODE\t\tGENMASK(1, 0)\n+#define OTTO_WDT_MODE_SOC\t\t0\n+#define OTTO_WDT_MODE_CPU\t\t1\n+#define OTTO_WDT_MODE_SOFTWARE\t\t2\n+#define OTTO_WDT_CTRL_DEFAULT\t\tOTTO_WDT_MODE_CPU\n+\n+#define OTTO_WDT_PRESCALE_MAX\t\t3\n+\n+/*\n+ * One higher than the max values contained in PHASE{1,2}, since a value of 0\n+ * corresponds to one tick.\n+ */\n+#define OTTO_WDT_PHASE_TICKS_MAX\t32\n+\n+/*\n+ * The maximum reset delay is actually 2×32 ticks, but that would require large\n+ * pretimeout values for timeouts longer than 32 ticks. Limit the maximum timeout\n+ * to 32 + 1 to ensure small pretimeout values can be configured as expected.\n+ */\n+#define OTTO_WDT_TIMEOUT_TICKS_MAX\t(OTTO_WDT_PHASE_TICKS_MAX + 1)\n+\n+struct otto_wdt_ctrl {\n+\tstruct watchdog_device wdev;\n+\tstruct device *dev;\n+\tvoid __iomem *base;\n+\tunsigned int clk_rate_khz;\n+\tint irq_phase1;\n+};\n+\n+static int otto_wdt_start(struct watchdog_device *wdev)\n+{\n+\tstruct otto_wdt_ctrl *ctrl = watchdog_get_drvdata(wdev);\n+\tu32 v;\n+\n+\tv = ioread32(ctrl->base + OTTO_WDT_REG_CTRL);\n+\tv |= OTTO_WDT_CTRL_ENABLE;\n+\tiowrite32(v, ctrl->base + OTTO_WDT_REG_CTRL);\n+\n+\treturn 0;\n+}\n+\n+static int otto_wdt_stop(struct watchdog_device *wdev)\n+{\n+\tstruct otto_wdt_ctrl *ctrl = watchdog_get_drvdata(wdev);\n+\tu32 v;\n+\n+\tv = ioread32(ctrl->base + OTTO_WDT_REG_CTRL);\n+\tv &= ~OTTO_WDT_CTRL_ENABLE;\n+\tiowrite32(v, ctrl->base + OTTO_WDT_REG_CTRL);\n+\n+\treturn 0;\n+}\n+\n+static int otto_wdt_ping(struct watchdog_device *wdev)\n+{\n+\tstruct otto_wdt_ctrl *ctrl = watchdog_get_drvdata(wdev);\n+\n+\tiowrite32(OTTO_WDT_CNTR_PING, ctrl->base + OTTO_WDT_REG_CNTR);\n+\n+\treturn 0;\n+}\n+\n+static int otto_wdt_tick_ms(struct otto_wdt_ctrl *ctrl, int prescale)\n+{\n+\treturn DIV_ROUND_CLOSEST(1 << (25 + prescale), ctrl->clk_rate_khz);\n+}\n+\n+/*\n+ * The timer asserts the PHASE1/PHASE2 IRQs when the number of ticks exceeds\n+ * the value stored in those fields. This means each phase will run for at least\n+ * one tick, so small values need to be clamped to correctly reflect the timeout.\n+ */\n+static inline unsigned int div_round_ticks(unsigned int val, unsigned int tick_duration,\n+\t\tunsigned int min_ticks)\n+{\n+\treturn max(min_ticks, DIV_ROUND_UP(val, tick_duration));\n+}\n+\n+static int otto_wdt_determine_timeouts(struct watchdog_device *wdev, unsigned int timeout,\n+\t\tunsigned int pretimeout)\n+{\n+\tstruct otto_wdt_ctrl *ctrl = watchdog_get_drvdata(wdev);\n+\tunsigned int pretimeout_ms = pretimeout * 1000;\n+\tunsigned int timeout_ms = timeout * 1000;\n+\tunsigned int prescale_next = 0;\n+\tunsigned int phase1_ticks;\n+\tunsigned int phase2_ticks;\n+\tunsigned int total_ticks;\n+\tunsigned int prescale;\n+\tunsigned int tick_ms;\n+\tu32 v;\n+\n+\tdo {\n+\t\tprescale = prescale_next;\n+\t\tif (prescale > OTTO_WDT_PRESCALE_MAX)\n+\t\t\treturn -EINVAL;\n+\n+\t\ttick_ms = otto_wdt_tick_ms(ctrl, prescale);\n+\t\ttotal_ticks = div_round_ticks(timeout_ms, tick_ms, 2);\n+\t\tphase1_ticks = div_round_ticks(timeout_ms - pretimeout_ms, tick_ms, 1);\n+\t\tphase2_ticks = total_ticks - phase1_ticks;\n+\n+\t\tprescale_next++;\n+\t} while (phase1_ticks > OTTO_WDT_PHASE_TICKS_MAX\n+\t\t|| phase2_ticks > OTTO_WDT_PHASE_TICKS_MAX);\n+\n+\tv = ioread32(ctrl->base + OTTO_WDT_REG_CTRL);\n+\n+\tv &= ~(OTTO_WDT_CTRL_PRESCALE | OTTO_WDT_CTRL_PHASE1 | OTTO_WDT_CTRL_PHASE2);\n+\tv |= FIELD_PREP(OTTO_WDT_CTRL_PHASE1, phase1_ticks - 1);\n+\tv |= FIELD_PREP(OTTO_WDT_CTRL_PHASE2, phase2_ticks - 1);\n+\tv |= FIELD_PREP(OTTO_WDT_CTRL_PRESCALE, prescale);\n+\n+\tiowrite32(v, ctrl->base + OTTO_WDT_REG_CTRL);\n+\n+\ttimeout_ms = total_ticks * tick_ms;\n+\tctrl->wdev.timeout = timeout_ms / 1000;\n+\n+\tpretimeout_ms = phase2_ticks * tick_ms;\n+\tctrl->wdev.pretimeout = pretimeout_ms / 1000;\n+\n+\treturn 0;\n+}\n+\n+static int otto_wdt_set_timeout(struct watchdog_device *wdev, unsigned int val)\n+{\n+\treturn otto_wdt_determine_timeouts(wdev, val, min(wdev->pretimeout, val - 1));\n+}\n+\n+static int otto_wdt_set_pretimeout(struct watchdog_device *wdev, unsigned int val)\n+{\n+\treturn otto_wdt_determine_timeouts(wdev, wdev->timeout, val);\n+}\n+\n+static int otto_wdt_restart(struct watchdog_device *wdev, unsigned long reboot_mode,\n+\t\tvoid *data)\n+{\n+\tstruct otto_wdt_ctrl *ctrl = watchdog_get_drvdata(wdev);\n+\tu32 reset_mode;\n+\tu32 v;\n+\n+\tdisable_irq(ctrl->irq_phase1);\n+\n+\tswitch (reboot_mode) {\n+\tcase REBOOT_SOFT:\n+\t\treset_mode = OTTO_WDT_MODE_SOFTWARE;\n+\t\tbreak;\n+\tcase REBOOT_WARM:\n+\t\treset_mode = OTTO_WDT_MODE_CPU;\n+\t\tbreak;\n+\tdefault:\n+\t\treset_mode = OTTO_WDT_MODE_SOC;\n+\t\tbreak;\n+\t}\n+\n+\t/* Configure for shortest timeout and wait for reset to occur */\n+\tv = FIELD_PREP(OTTO_WDT_CTRL_RST_MODE, reset_mode) | OTTO_WDT_CTRL_ENABLE;\n+\tiowrite32(v, ctrl->base + OTTO_WDT_REG_CTRL);\n+\n+\tmdelay(3 * otto_wdt_tick_ms(ctrl, 0));\n+\n+\treturn 0;\n+}\n+\n+static irqreturn_t otto_wdt_phase1_isr(int irq, void *dev_id)\n+{\n+\tstruct otto_wdt_ctrl *ctrl = dev_id;\n+\n+\tiowrite32(OTTO_WDT_INTR_PHASE_1, ctrl->base + OTTO_WDT_REG_INTR);\n+\tdev_crit(ctrl->dev, \"phase 1 timeout\\n\");\n+\twatchdog_notify_pretimeout(&ctrl->wdev);\n+\n+\treturn IRQ_HANDLED;\n+}\n+\n+static const struct watchdog_ops otto_wdt_ops = {\n+\t.owner = THIS_MODULE,\n+\t.start = otto_wdt_start,\n+\t.stop = otto_wdt_stop,\n+\t.ping = otto_wdt_ping,\n+\t.set_timeout = otto_wdt_set_timeout,\n+\t.set_pretimeout = otto_wdt_set_pretimeout,\n+\t.restart = otto_wdt_restart,\n+};\n+\n+static const struct watchdog_info otto_wdt_info = {\n+\t.identity = \"Realtek Otto watchdog timer\",\n+\t.options = WDIOF_KEEPALIVEPING |\n+\t\tWDIOF_MAGICCLOSE |\n+\t\tWDIOF_SETTIMEOUT |\n+\t\tWDIOF_PRETIMEOUT,\n+};\n+\n+static void otto_wdt_clock_action(void *data)\n+{\n+\tclk_disable_unprepare(data);\n+}\n+\n+static int otto_wdt_probe_clk(struct otto_wdt_ctrl *ctrl)\n+{\n+\tstruct clk *clk = devm_clk_get(ctrl->dev, NULL);\n+\tint ret;\n+\n+\tif (IS_ERR(clk))\n+\t\treturn dev_err_probe(ctrl->dev, PTR_ERR(clk), \"Failed to get clock\\n\");\n+\n+\tret = clk_prepare_enable(clk);\n+\tif (ret)\n+\t\treturn dev_err_probe(ctrl->dev, ret, \"Failed to enable clock\\n\");\n+\n+\tret = devm_add_action_or_reset(ctrl->dev, otto_wdt_clock_action, clk);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tctrl->clk_rate_khz = clk_get_rate(clk) / 1000;\n+\tif (ctrl->clk_rate_khz == 0)\n+\t\treturn dev_err_probe(ctrl->dev, -ENXIO, \"Failed to get clock rate\\n\");\n+\n+\treturn 0;\n+}\n+\n+static int otto_wdt_probe_reset_mode(struct otto_wdt_ctrl *ctrl)\n+{\n+\tstatic const char *mode_property = \"realtek,reset-mode\";\n+\tconst struct fwnode_handle *node = ctrl->dev->fwnode;\n+\tint mode_count;\n+\tu32 mode;\n+\tu32 v;\n+\n+\tif (!node)\n+\t\treturn -ENXIO;\n+\n+\tmode_count = fwnode_property_string_array_count(node, mode_property);\n+\tif (mode_count < 0)\n+\t\treturn mode_count;\n+\telse if (mode_count == 0)\n+\t\treturn 0;\n+\telse if (mode_count != 1)\n+\t\treturn -EINVAL;\n+\n+\tif (fwnode_property_match_string(node, mode_property, \"soc\") == 0)\n+\t\tmode = OTTO_WDT_MODE_SOC;\n+\telse if (fwnode_property_match_string(node, mode_property, \"cpu\") == 0)\n+\t\tmode = OTTO_WDT_MODE_CPU;\n+\telse if (fwnode_property_match_string(node, mode_property, \"software\") == 0)\n+\t\tmode = OTTO_WDT_MODE_SOFTWARE;\n+\telse\n+\t\treturn -EINVAL;\n+\n+\tv = ioread32(ctrl->base + OTTO_WDT_REG_CTRL);\n+\tv &= ~OTTO_WDT_CTRL_RST_MODE;\n+\tv |= FIELD_PREP(OTTO_WDT_CTRL_RST_MODE, mode);\n+\tiowrite32(v, ctrl->base + OTTO_WDT_REG_CTRL);\n+\n+\treturn 0;\n+}\n+\n+static int otto_wdt_probe(struct platform_device *pdev)\n+{\n+\tstruct device *dev = &pdev->dev;\n+\tstruct otto_wdt_ctrl *ctrl;\n+\tunsigned int max_tick_ms;\n+\tint ret;\n+\n+\tctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);\n+\tif (!ctrl)\n+\t\treturn -ENOMEM;\n+\n+\tctrl->dev = dev;\n+\tctrl->base = devm_platform_ioremap_resource(pdev, 0);\n+\tif (IS_ERR(ctrl->base))\n+\t\treturn PTR_ERR(ctrl->base);\n+\n+\t/* Clear any old interrupts and reset initial state */\n+\tiowrite32(OTTO_WDT_INTR_PHASE_1 | OTTO_WDT_INTR_PHASE_2,\n+\t\t\tctrl->base + OTTO_WDT_REG_INTR);\n+\tiowrite32(OTTO_WDT_CTRL_DEFAULT, ctrl->base + OTTO_WDT_REG_CTRL);\n+\n+\tret = otto_wdt_probe_clk(ctrl);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tctrl->irq_phase1 = platform_get_irq_byname(pdev, \"phase1\");\n+\tif (ctrl->irq_phase1 < 0)\n+\t\treturn ctrl->irq_phase1;\n+\n+\tret = devm_request_irq(dev, ctrl->irq_phase1, otto_wdt_phase1_isr, 0,\n+\t\t\t\"realtek-otto-wdt\", ctrl);\n+\tif (ret)\n+\t\treturn dev_err_probe(dev, ret, \"Failed to get IRQ for phase1\\n\");\n+\n+\tret = otto_wdt_probe_reset_mode(ctrl);\n+\tif (ret)\n+\t\treturn dev_err_probe(dev, ret, \"Invalid reset mode specified\\n\");\n+\n+\tctrl->wdev.parent = dev;\n+\tctrl->wdev.info = &otto_wdt_info;\n+\tctrl->wdev.ops = &otto_wdt_ops;\n+\n+\t/*\n+\t * Since pretimeout cannot be disabled, min. timeout is twice the\n+\t * subsystem resolution. Max. timeout is ca. 43s at a bus clock of 200MHz.\n+\t */\n+\tctrl->wdev.min_timeout = 2;\n+\tmax_tick_ms = otto_wdt_tick_ms(ctrl, OTTO_WDT_PRESCALE_MAX);\n+\tctrl->wdev.max_hw_heartbeat_ms = max_tick_ms * OTTO_WDT_TIMEOUT_TICKS_MAX;\n+\tctrl->wdev.timeout = min(30U, ctrl->wdev.max_hw_heartbeat_ms / 1000);\n+\n+\twatchdog_set_drvdata(&ctrl->wdev, ctrl);\n+\twatchdog_init_timeout(&ctrl->wdev, 0, dev);\n+\twatchdog_stop_on_reboot(&ctrl->wdev);\n+\twatchdog_set_restart_priority(&ctrl->wdev, 128);\n+\n+\tret = otto_wdt_determine_timeouts(&ctrl->wdev, ctrl->wdev.timeout, 1);\n+\tif (ret)\n+\t\treturn dev_err_probe(dev, ret, \"Failed to set timeout\\n\");\n+\n+\treturn devm_watchdog_register_device(dev, &ctrl->wdev);\n+}\n+\n+static const struct of_device_id otto_wdt_ids[] = {\n+\t{ .compatible = \"realtek,rtl8380-wdt\" },\n+\t{ .compatible = \"realtek,rtl8390-wdt\" },\n+\t{ .compatible = \"realtek,rtl9300-wdt\" },\n+\t{ }\n+};\n+MODULE_DEVICE_TABLE(of, otto_wdt_ids);\n+\n+static struct platform_driver otto_wdt_driver = {\n+\t.probe = otto_wdt_probe,\n+\t.driver = {\n+\t\t.name = \"realtek-otto-watchdog\",\n+\t\t.of_match_table\t= otto_wdt_ids,\n+\t},\n+};\n+module_platform_driver(otto_wdt_driver);\n+\n+MODULE_LICENSE(\"GPL v2\");\n+MODULE_AUTHOR(\"Sander Vanheule <sander@svanheule.net>\");\n+MODULE_DESCRIPTION(\"Realtek Otto watchdog timer driver\");\n"
  },
  {
    "path": "target/linux/realtek/patches-5.10/020-v5.17-net-mdio-add-helpers-to-extract-clause-45-regad-and-.patch",
    "content": "From c6af53f038aa32cec12e8a305ba07c7ef168f1b0 Mon Sep 17 00:00:00 2001\nFrom: \"Russell King (Oracle)\" <rmk+kernel@armlinux.org.uk>\nDate: Tue, 4 Jan 2022 12:07:00 +0000\nSubject: [PATCH 2/3] net: mdio: add helpers to extract clause 45 regad and\n devad fields\n\nAdd a couple of helpers and definitions to extract the clause 45 regad\nand devad fields from the regnum passed into MDIO drivers.\n\nTested-by: Daniel Golle <daniel@makrotopia.org>\nReviewed-by: Andrew Lunn <andrew@lunn.ch>\nSigned-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>\nSigned-off-by: Daniel Golle <daniel@makrotopia.org>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n---\n include/linux/mdio.h | 12 ++++++++++++\n 1 file changed, 12 insertions(+)\n\n--- a/include/linux/mdio.h\n+++ b/include/linux/mdio.h\n@@ -7,6 +7,7 @@\n #define __LINUX_MDIO_H__\n \n #include <uapi/linux/mdio.h>\n+#include <linux/bitfield.h>\n #include <linux/mod_devicetable.h>\n \n /* Or MII_ADDR_C45 into regnum for read/write on mii_bus to enable the 21 bit\n@@ -14,6 +15,7 @@\n  */\n #define MII_ADDR_C45\t\t(1<<30)\n #define MII_DEVADDR_C45_SHIFT\t16\n+#define MII_DEVADDR_C45_MASK\tGENMASK(20, 16)\n #define MII_REGADDR_C45_MASK\tGENMASK(15, 0)\n \n struct gpio_desc;\n@@ -342,6 +344,16 @@ static inline u32 mdiobus_c45_addr(int d\n \treturn MII_ADDR_C45 | devad << MII_DEVADDR_C45_SHIFT | regnum;\n }\n \n+static inline u16 mdiobus_c45_regad(u32 regnum)\n+{\n+\treturn FIELD_GET(MII_REGADDR_C45_MASK, regnum);\n+}\n+\n+static inline u16 mdiobus_c45_devad(u32 regnum)\n+{\n+\treturn FIELD_GET(MII_DEVADDR_C45_MASK, regnum);\n+}\n+\n static inline int __mdiobus_c45_read(struct mii_bus *bus, int prtad, int devad,\n \t\t\t\t     u16 regnum)\n {\n"
  },
  {
    "path": "target/linux/realtek/patches-5.10/300-mips-add-rtl838x-platform.patch",
    "content": "--- a/arch/mips/Kbuild.platforms\n+++ b/arch/mips/Kbuild.platforms\n@@ -23,6 +23,7 @@ platform-$(CONFIG_PIC32MZDA)\t\t+= pic32/\n platform-$(CONFIG_MACH_PISTACHIO)\t+= pistachio/\n platform-$(CONFIG_RALINK)\t\t+= ralink/\n platform-$(CONFIG_MIKROTIK_RB532)\t+= rb532/\n+platform-$(CONFIG_RTL83XX)\t\t+= rtl838x/\n platform-$(CONFIG_SGI_IP22)\t\t+= sgi-ip22/\n platform-$(CONFIG_SGI_IP27)\t\t+= sgi-ip27/\n platform-$(CONFIG_SGI_IP28)\t\t+= sgi-ip22/\n--- a/arch/mips/Kconfig\n+++ b/arch/mips/Kconfig\n@@ -1037,8 +1037,58 @@ config NLM_XLP_BOARD\n \t  This board is based on Netlogic XLP Processor.\n \t  Say Y here if you have a XLP based board.\n \n+config RTL83XX\n+\tbool \"Realtek based platforms\"\n+\tselect DMA_NONCOHERENT\n+\tselect IRQ_MIPS_CPU\n+\tselect SYS_HAS_CPU_MIPS32_R1\n+\tselect SYS_HAS_CPU_MIPS32_R2\n+\tselect SYS_SUPPORTS_BIG_ENDIAN\n+\tselect SYS_SUPPORTS_HIGHMEM\n+\tselect SYS_SUPPORTS_32BIT_KERNEL\n+\tselect SYS_SUPPORTS_MIPS16\n+\tselect SYS_HAS_EARLY_PRINTK\n+\tselect SYS_HAS_EARLY_PRINTK_8250\n+\tselect USE_GENERIC_EARLY_PRINTK_8250\n+\tselect BOOT_RAW\n+\tselect PINCTRL\n+\tselect ARCH_HAS_RESET_CONTROLLER\n+\tselect RESET_CONTROLLER\n+\tselect USE_OF\n+\n endchoice\n \n+config RTL838X\n+\tbool \"Realtek RTL838X based platforms\"\n+\tdepends on RTL83XX\n+\tselect CSRC_R4K\n+\tselect CEVT_R4K\n+\n+config RTL839X\n+\tbool \"Realtek RTL839X based platforms\"\n+\tdepends on RTL83XX\n+\tselect CSRC_R4K\n+\tselect CEVT_R4K\n+\tselect SYS_SUPPORTS_MULTITHREADING\n+\n+config RTL930X\n+\tbool \"Realtek RTL839X based platforms\"\n+\tdepends on RTL83XX\n+\tselect MIPS_CPU_SCACHE\n+\tselect CSRC_R4K\n+\tselect CEVT_RTL9300\n+\tselect SYS_SUPPORTS_MULTITHREADING\n+\n+config RTL931X\n+\tbool \"Realtek RTL931X based platforms\"\n+\tdepends on RTL930X\n+\tselect MIPS_GIC\n+\tselect COMMON_CLK\n+\tselect CLKSRC_MIPS_GIC\n+\tselect SYS_SUPPORTS_VPE_LOADER\n+\tselect SYS_SUPPORTS_SMP\n+\tselect SYS_SUPPORTS_MIPS_CPS\n+\n source \"arch/mips/alchemy/Kconfig\"\n source \"arch/mips/ath25/Kconfig\"\n source \"arch/mips/ath79/Kconfig\"\n@@ -1097,6 +1147,9 @@ config CEVT_GT641XX\n config CEVT_R4K\n \tbool\n \n+config CEVT_RTL9300\n+\tbool\n+\n config CEVT_SB1250\n \tbool\n \n"
  },
  {
    "path": "target/linux/realtek/patches-5.10/301-gpio-add-rtl8231-driver.patch",
    "content": "--- a/drivers/gpio/Kconfig\n+++ b/drivers/gpio/Kconfig\n@@ -508,6 +508,12 @@ config GPIO_REG\n \t  A 32-bit single register GPIO fixed in/out implementation.  This\n \t  can be used to represent any register as a set of GPIO signals.\n \n+config GPIO_RTL8231\n+\ttristate \"RTL8231 GPIO\"\n+\tdepends on RTL83XX\n+\thelp\n+\t  Say yes here to support Realtek RTL8231 GPIO expansion chips.\n+\n config GPIO_SAMA5D2_PIOBU\n \ttristate \"SAMA5D2 PIOBU GPIO support\"\n \tdepends on MFD_SYSCON\n--- a/drivers/gpio/Makefile\n+++ b/drivers/gpio/Makefile\n@@ -127,6 +127,7 @@ obj-$(CONFIG_GPIO_RDA)\t\t\t+= gpio-rda.o\n obj-$(CONFIG_GPIO_RDC321X)\t\t+= gpio-rdc321x.o\n obj-$(CONFIG_GPIO_REALTEK_OTTO)\t\t+= gpio-realtek-otto.o\n obj-$(CONFIG_GPIO_REG)\t\t\t+= gpio-reg.o\n+obj-$(CONFIG_GPIO_RTL8231)\t\t+= gpio-rtl8231.o\n obj-$(CONFIG_ARCH_SA1100)\t\t+= gpio-sa1100.o\n obj-$(CONFIG_GPIO_SAMA5D2_PIOBU)\t+= gpio-sama5d2-piobu.o\n obj-$(CONFIG_GPIO_SCH311X)\t\t+= gpio-sch311x.o\n"
  },
  {
    "path": "target/linux/realtek/patches-5.10/303-gpio-update-dependencies-for-gpio-realtek-otto.patch",
    "content": "--- a/drivers/gpio/Kconfig\n+++ b/drivers/gpio/Kconfig\n@@ -491,8 +491,8 @@ config GPIO_RDA\n \n config GPIO_REALTEK_OTTO\n \ttristate \"Realtek Otto GPIO support\"\n-\tdepends on MACH_REALTEK_RTL\n-\tdefault MACH_REALTEK_RTL\n+\tdepends on RTL83XX\n+\tdefault RTL838X\n \tselect GPIO_GENERIC\n \tselect GPIOLIB_IRQCHIP\n \thelp\n"
  },
  {
    "path": "target/linux/realtek/patches-5.10/304-spi-update-dependency-for-spi-realtek-rtl.patch",
    "content": "--- a/drivers/spi/Makefile\n+++ b/drivers/spi/Makefile\n@@ -94,7 +94,7 @@ obj-$(CONFIG_SPI_QCOM_QSPI)\t\t+= spi-qcom\n obj-$(CONFIG_SPI_QUP)\t\t\t+= spi-qup.o\n obj-$(CONFIG_SPI_ROCKCHIP)\t\t+= spi-rockchip.o\n obj-$(CONFIG_SPI_RB4XX)\t\t\t+= spi-rb4xx.o\n-obj-$(CONFIG_MACH_REALTEK_RTL)\t\t+= spi-realtek-rtl.o\n+obj-$(CONFIG_RTL83XX)\t\t\t+= spi-realtek-rtl.o\n obj-$(CONFIG_SPI_RPCIF)\t\t\t+= spi-rpc-if.o\n obj-$(CONFIG_SPI_RSPI)\t\t\t+= spi-rspi.o\n obj-$(CONFIG_SPI_S3C24XX)\t\t+= spi-s3c24xx-hw.o\n"
  },
  {
    "path": "target/linux/realtek/patches-5.10/305-irqchip-update-dependency-for-irq-realtek-rtl.patch",
    "content": "--- a/drivers/irqchip/Makefile\n+++ b/drivers/irqchip/Makefile\n@@ -114,4 +114,4 @@ obj-$(CONFIG_LOONGSON_PCH_PIC)\t\t+= irq-l\n obj-$(CONFIG_LOONGSON_PCH_MSI)\t\t+= irq-loongson-pch-msi.o\n obj-$(CONFIG_MST_IRQ)\t\t\t+= irq-mst-intc.o\n obj-$(CONFIG_SL28CPLD_INTC)\t\t+= irq-sl28cpld.o\n-obj-$(CONFIG_MACH_REALTEK_RTL)\t\t+= irq-realtek-rtl.o\n+obj-$(CONFIG_RTL83XX)\t\t\t+= irq-realtek-rtl.o\n"
  },
  {
    "path": "target/linux/realtek/patches-5.10/307-wdt-update-dependency-for-realtek-otto-wdt.patch",
    "content": "--- a/drivers/watchdog/Kconfig\n+++ b/drivers/watchdog/Kconfig\n@@ -997,10 +997,10 @@ config RTD119X_WATCHDOG\n \n config REALTEK_OTTO_WDT\n \ttristate \"Realtek Otto MIPS watchdog support\"\n-\tdepends on MACH_REALTEK_RTL || COMPILE_TEST\n+\tdepends on RTL83XX\n \tdepends on COMMON_CLK\n \tselect WATCHDOG_CORE\n-\tdefault MACH_REALTEK_RTL\n+\tdefault RTL83XX\n \thelp\n \t  Say Y here to include support for the watchdog timer on Realtek\n \t  RTL838x, RTL839x, RTL930x SoCs. This watchdog has pretimeout\n"
  },
  {
    "path": "target/linux/realtek/patches-5.10/308-otto-wdt-fix-missing-math-header.patch",
    "content": "--- a/drivers/watchdog/realtek_otto_wdt.c\n+++ b/drivers/watchdog/realtek_otto_wdt.c\n@@ -21,7 +21,7 @@\n #include <linux/delay.h>\n #include <linux/interrupt.h>\n #include <linux/io.h>\n-#include <linux/math.h>\n+#include <linux/kernel.h>\n #include <linux/minmax.h>\n #include <linux/module.h>\n #include <linux/mod_devicetable.h>\n"
  },
  {
    "path": "target/linux/realtek/patches-5.10/309-cevt-rtl9300-support.patch",
    "content": "--- a/arch/mips/kernel/Makefile\n+++ b/arch/mips/kernel/Makefile\n@@ -27,6 +27,7 @@ obj-$(CONFIG_CEVT_BCM1480)\t+= cevt-bcm14\n obj-$(CONFIG_CEVT_R4K)\t\t+= cevt-r4k.o\n obj-$(CONFIG_CEVT_DS1287)\t+= cevt-ds1287.o\n obj-$(CONFIG_CEVT_GT641XX)\t+= cevt-gt641xx.o\n+obj-$(CONFIG_CEVT_RTL9300)\t+= cevt-rtl9300.o\n obj-$(CONFIG_CEVT_SB1250)\t+= cevt-sb1250.o\n obj-$(CONFIG_CEVT_TXX9)\t\t+= cevt-txx9.o\n obj-$(CONFIG_CSRC_BCM1480)\t+= csrc-bcm1480.o\n--- a/arch/mips/include/asm/time.h\n+++ b/arch/mips/include/asm/time.h\n@@ -15,6 +15,8 @@\n #include <linux/clockchips.h>\n #include <linux/clocksource.h>\n \n+extern void rtl9300_clockevent_init(void);\n+\n extern spinlock_t rtc_lock;\n \n /*\n@@ -43,6 +45,11 @@ extern int r4k_clockevent_init(void);\n \n static inline int mips_clockevent_init(void)\n {\n+#ifdef CONFIG_CEVT_RTL9300\n+\trtl9300_clockevent_init();\n+\treturn 0;\n+#endif\n+\n #ifdef CONFIG_CEVT_R4K\n \treturn r4k_clockevent_init();\n #else\n--- a/arch/mips/kernel/smp-mt.c\n+++ b/arch/mips/kernel/smp-mt.c\n@@ -108,12 +108,18 @@ static void __init smvp_tc_init(unsigned\n static void vsmp_init_secondary(void)\n {\n \t/* This is Malta specific: IPI,performance and timer interrupts */\n+\n+\t/* RTL9300 Clear internal timer interrupt */\n+\twrite_c0_compare(0);\n+\n \tif (mips_gic_present())\n \t\tchange_c0_status(ST0_IM, STATUSF_IP2 | STATUSF_IP3 |\n \t\t\t\t\t STATUSF_IP4 | STATUSF_IP5 |\n \t\t\t\t\t STATUSF_IP6 | STATUSF_IP7);\n \telse\n \t\tchange_c0_status(ST0_IM, STATUSF_IP0 | STATUSF_IP1 |\n+\t\t\t\t\t STATUSF_IP2 | STATUSF_IP3 |\n+\t\t\t\t\t STATUSF_IP4 | STATUSF_IP5 |\n \t\t\t\t\t STATUSF_IP6 | STATUSF_IP7);\n }\n \n"
  },
  {
    "path": "target/linux/realtek/patches-5.10/310-add-i2c-rtl9300-support.patch",
    "content": "--- a/drivers/i2c/busses/Kconfig\n+++ b/drivers/i2c/busses/Kconfig\n@@ -954,6 +954,16 @@ config I2C_RK3X\n \t  This driver can also be built as a module. If so, the module will\n \t  be called i2c-rk3x.\n \n+config I2C_RTL9300\n+\ttristate \"Realtek RTL9300 I2C adapter\"\n+\tdepends on OF\n+\thelp\n+\t  Say Y here to include support for the I2C adapter in Realtek RTL9300\n+\t  and RTL9310 SoCs.\n+\n+\t  This driver can also be built as a module. If so, the module will\n+\t  be called i2c-rtl9300.\n+\n config HAVE_S3C2410_I2C\n \tbool\n \thelp\n--- a/drivers/i2c/busses/Makefile\n+++ b/drivers/i2c/busses/Makefile\n@@ -95,6 +95,7 @@ obj-$(CONFIG_I2C_QCOM_GENI)\t+= i2c-qcom-\n obj-$(CONFIG_I2C_QUP)\t\t+= i2c-qup.o\n obj-$(CONFIG_I2C_RIIC)\t\t+= i2c-riic.o\n obj-$(CONFIG_I2C_RK3X)\t\t+= i2c-rk3x.o\n+obj-$(CONFIG_I2C_RTL9300)\t+= i2c-rtl9300.o\n obj-$(CONFIG_I2C_S3C2410)\t+= i2c-s3c2410.o\n obj-$(CONFIG_I2C_SH7760)\t+= i2c-sh7760.o\n obj-$(CONFIG_I2C_SH_MOBILE)\t+= i2c-sh_mobile.o\n"
  },
  {
    "path": "target/linux/realtek/patches-5.10/311-add-i2c-mux-rtl9300-support.patch",
    "content": "--- a/drivers/i2c/muxes/Kconfig\n+++ b/drivers/i2c/muxes/Kconfig\n@@ -99,6 +99,15 @@ config I2C_MUX_REG\n \t  This driver can also be built as a module.  If so, the module\n \t  will be called i2c-mux-reg.\n \n+config I2C_MUX_RTL9300\n+\ttristate \"RTL9300 based I2C multiplexer\"\n+\thelp\n+\t  If you say yes to this option, support will be included for a\n+\t  RTL9300 based I2C multiplexer.\n+\n+\t  This driver can also be built as a module.  If so, the module\n+\t  will be called i2c-mux-reg.\n+\n config I2C_DEMUX_PINCTRL\n \ttristate \"pinctrl-based I2C demultiplexer\"\n \tdepends on PINCTRL && OF\n--- a/drivers/i2c/muxes/Makefile\n+++ b/drivers/i2c/muxes/Makefile\n@@ -14,5 +14,6 @@ obj-$(CONFIG_I2C_MUX_PCA9541)\t+= i2c-mux\n obj-$(CONFIG_I2C_MUX_PCA954x)\t+= i2c-mux-pca954x.o\n obj-$(CONFIG_I2C_MUX_PINCTRL)\t+= i2c-mux-pinctrl.o\n obj-$(CONFIG_I2C_MUX_REG)\t+= i2c-mux-reg.o\n+obj-$(CONFIG_I2C_MUX_RTL9300)\t+= i2c-mux-rtl9300.o\n \n ccflags-$(CONFIG_I2C_DEBUG_BUS) := -DDEBUG\n"
  },
  {
    "path": "target/linux/realtek/patches-5.10/312-rt9313-support.patch",
    "content": "--- a/arch/mips/Makefile\n+++ b/arch/mips/Makefile\n@@ -307,14 +307,24 @@ endif\n \n KBUILD_AFLAGS\t+= $(cflags-y)\n KBUILD_CFLAGS\t+= $(cflags-y)\n+ifdef CONFIG_931X\n+KBUILD_CPPFLAGS += -DVMLINUX_LOAD_ADDRESS=$(load-y)\n+bootvars-y\t= VMLINUX_LOAD_ADDRESS=$(load-y) \\\n+\t\t  VMLINUX_ENTRY_ADDRESS=$(entry-y) \\\n+\t\t  PLATFORM=\"$(platform-y)\" \\\n+\t\t  ITS_INPUTS=\"$(its-y)\"\n+else\n KBUILD_CPPFLAGS += -DVMLINUX_LOAD_ADDRESS=$(load-y) -DLINKER_LOAD_ADDRESS=$(load-ld)\n-KBUILD_CPPFLAGS += -DDATAOFFSET=$(if $(dataoffset-y),$(dataoffset-y),0)\n-\n bootvars-y\t= VMLINUX_LOAD_ADDRESS=$(load-y) \\\n \t\t  LINKER_LOAD_ADDRESS=$(load-ld) \\\n \t\t  VMLINUX_ENTRY_ADDRESS=$(entry-y) \\\n \t\t  PLATFORM=\"$(platform-y)\" \\\n \t\t  ITS_INPUTS=\"$(its-y)\"\n+endif\n+KBUILD_CPPFLAGS += -DDATAOFFSET=$(if $(dataoffset-y),$(dataoffset-y),0)\n+\n+\n+\n ifdef CONFIG_32BIT\n bootvars-y\t+= ADDR_BITS=32\n endif\n--- a/arch/mips/kernel/head.S\n+++ b/arch/mips/kernel/head.S\n@@ -60,12 +60,14 @@\n \t.endm\n \n #ifndef CONFIG_NO_EXCEPT_FILL\n+#ifndef CONFIG_RTL931X\n \t/*\n \t * Reserved space for exception handlers.\n \t * Necessary for machines which link their kernels at KSEG0.\n \t */\n \t.fill\t0x400\n #endif\n+#endif\n \n EXPORT(_stext)\n \n@@ -79,11 +81,13 @@ FEXPORT(__kernel_entry)\n \tj\tkernel_entry\n #endif /* CONFIG_BOOT_RAW */\n \n+#ifndef CONFIG_RTL931X\n #ifdef CONFIG_IMAGE_CMDLINE_HACK\n \t.ascii\t\"CMDLINE:\"\n EXPORT(__image_cmdline)\n \t.fill\t0x400\n #endif /* CONFIG_IMAGE_CMDLINE_HACK */\n+#endif\n \n \t__REF\n \n--- a/arch/mips/kernel/vmlinux.lds.S\n+++ b/arch/mips/kernel/vmlinux.lds.S\n@@ -55,7 +55,11 @@ SECTIONS\n \t/* . = 0xa800000000300000; */\n \t. = 0xffffffff80300000;\n #endif\n+#ifdef CONFIG_RTL931X\n+\t. = 0x80220000;\n+#else\n \t. = LINKER_LOAD_ADDRESS;\n+#endif\n \t/* read-only */\n \t_text = .;\t/* Text and read-only data */\n \t.text : {\n"
  },
  {
    "path": "target/linux/realtek/patches-5.10/315-irqchip-irq-realtek-rtl-add-VPE-support.patch",
    "content": "--- a/drivers/irqchip/irq-realtek-rtl.c\n+++ b/drivers/irqchip/irq-realtek-rtl.c\n@@ -21,21 +21,63 @@\n #define RTL_ICTL_IRR2\t\t0x10\n #define RTL_ICTL_IRR3\t\t0x14\n \n-#define REG(x)\t\t(realtek_ictl_base + x)\n+#define RTL_ICTL_NUM_INPUTS\t32\n+#define RTL_ICTL_NUM_OUTPUTS\t15\n \n static DEFINE_RAW_SPINLOCK(irq_lock);\n-static void __iomem *realtek_ictl_base;\n+\n+#define REG(offset, cpu)\t(realtek_ictl_base[cpu] + offset)\n+\n+static void __iomem *realtek_ictl_base[NR_CPUS];\n+static cpumask_t realtek_ictl_cpu_configurable;\n+\n+struct realtek_ictl_output {\n+\t/* IRQ controller data */\n+\tstruct fwnode_handle *fwnode;\n+\t/* Output specific data */\n+\tunsigned int output_index;\n+\tstruct irq_domain *domain;\n+\tu32 child_mask;\n+};\n+\n+/*\n+ * IRR0-IRR3 store 4 bits per interrupt, but Realtek uses inverted numbering,\n+ * placing IRQ 31 in the first four bits. A routing value of '0' means the\n+ * interrupt is left disconnected. Routing values {1..15} connect to output\n+ * lines {0..14}.\n+ */\n+#define IRR_OFFSET(idx)\t\t(4 * (3 - (idx * 4) / 32))\n+#define IRR_SHIFT(idx)\t\t((idx * 4) % 32)\n+\n+static inline u32 read_irr(void __iomem *irr0, int idx)\n+{\n+\treturn (readl(irr0 + IRR_OFFSET(idx)) >> IRR_SHIFT(idx)) & 0xf;\n+}\n+\n+static inline void write_irr(void __iomem *irr0, int idx, u32 value)\n+{\n+\tunsigned int offset = IRR_OFFSET(idx);\n+\tunsigned int shift = IRR_SHIFT(idx);\n+\tu32 irr;\n+\n+\tirr = readl(irr0 + offset) & ~(0xf << shift);\n+\tirr |= (value & 0xf) << shift;\n+\twritel(irr, irr0 + offset);\n+}\n \n static void realtek_ictl_unmask_irq(struct irq_data *i)\n {\n \tunsigned long flags;\n \tu32 value;\n+\tint cpu;\n \n \traw_spin_lock_irqsave(&irq_lock, flags);\n \n-\tvalue = readl(REG(RTL_ICTL_GIMR));\n-\tvalue |= BIT(i->hwirq);\n-\twritel(value, REG(RTL_ICTL_GIMR));\n+\tfor_each_cpu(cpu, &realtek_ictl_cpu_configurable) {\n+\t\tvalue = readl(REG(RTL_ICTL_GIMR, cpu));\n+\t\tvalue |= BIT(i->hwirq);\n+\t\twritel(value, REG(RTL_ICTL_GIMR, cpu));\n+\t}\n \n \traw_spin_unlock_irqrestore(&irq_lock, flags);\n }\n@@ -44,137 +86,247 @@ static void realtek_ictl_mask_irq(struct\n {\n \tunsigned long flags;\n \tu32 value;\n+\tint cpu;\n \n \traw_spin_lock_irqsave(&irq_lock, flags);\n \n-\tvalue = readl(REG(RTL_ICTL_GIMR));\n-\tvalue &= ~BIT(i->hwirq);\n-\twritel(value, REG(RTL_ICTL_GIMR));\n+\tfor_each_cpu(cpu, &realtek_ictl_cpu_configurable) {\n+\t\tvalue = readl(REG(RTL_ICTL_GIMR, cpu));\n+\t\tvalue &= ~BIT(i->hwirq);\n+\t\twritel(value, REG(RTL_ICTL_GIMR, cpu));\n+\t}\n \n \traw_spin_unlock_irqrestore(&irq_lock, flags);\n }\n \n+static int __maybe_unused realtek_ictl_irq_affinity(struct irq_data *i,\n+\tconst struct cpumask *dest, bool force)\n+{\n+\tstruct realtek_ictl_output *output = i->domain->host_data;\n+\tcpumask_t cpu_configure;\n+\tcpumask_t cpu_disable;\n+\tcpumask_t cpu_enable;\n+\tunsigned long flags;\n+\tint cpu;\n+\n+\traw_spin_lock_irqsave(&irq_lock, flags);\n+\n+\tcpumask_and(&cpu_configure, cpu_present_mask, &realtek_ictl_cpu_configurable);\n+\n+\tcpumask_and(&cpu_enable, &cpu_configure, dest);\n+\tcpumask_andnot(&cpu_disable, &cpu_configure, dest);\n+\n+\tfor_each_cpu(cpu, &cpu_disable)\n+\t\twrite_irr(REG(RTL_ICTL_IRR0, cpu), i->hwirq, 0);\n+\n+\tfor_each_cpu(cpu, &cpu_enable)\n+\t\twrite_irr(REG(RTL_ICTL_IRR0, cpu), i->hwirq, output->output_index + 1);\n+\n+\tirq_data_update_effective_affinity(i, &cpu_enable);\n+\n+\traw_spin_unlock_irqrestore(&irq_lock, flags);\n+\n+\treturn IRQ_SET_MASK_OK;\n+}\n+\n static struct irq_chip realtek_ictl_irq = {\n \t.name = \"realtek-rtl-intc\",\n \t.irq_mask = realtek_ictl_mask_irq,\n \t.irq_unmask = realtek_ictl_unmask_irq,\n+#ifdef CONFIG_SMP\n+\t.irq_set_affinity = realtek_ictl_irq_affinity,\n+#endif\n };\n \n static int intc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)\n {\n-\tirq_set_chip_and_handler(hw, &realtek_ictl_irq, handle_level_irq);\n+\tstruct realtek_ictl_output *output = d->host_data;\n+\tunsigned long flags;\n+\n+\tirq_set_chip_and_handler(irq, &realtek_ictl_irq, handle_level_irq);\n+\n+\traw_spin_lock_irqsave(&irq_lock, flags);\n+\n+\toutput->child_mask |= BIT(hw);\n+\twrite_irr(REG(RTL_ICTL_IRR0, 0), hw, output->output_index + 1);\n+\n+\traw_spin_unlock_irqrestore(&irq_lock, flags);\n \n \treturn 0;\n }\n \n+static int intc_select(struct irq_domain *d, struct irq_fwspec *fwspec,\n+\tenum irq_domain_bus_token bus_token)\n+{\n+\tstruct realtek_ictl_output *output = d->host_data;\n+\tbool routed_elsewhere;\n+\tunsigned long flags;\n+\tu32 routing_old;\n+\tint cpu;\n+\n+\tif (fwspec->fwnode != output->fwnode)\n+\t\treturn false;\n+\n+\t/* Original specifiers had only one parameter */\n+\tif (fwspec->param_count < 2)\n+\t\treturn true;\n+\n+\traw_spin_lock_irqsave(&irq_lock, flags);\n+\n+\t/*\n+\t * Inputs can only be routed to one output, so they shouldn't be\n+\t * allowed to end up in multiple domains.\n+\t */\n+\tfor_each_cpu(cpu, &realtek_ictl_cpu_configurable) {\n+\t\trouting_old = read_irr(REG(RTL_ICTL_IRR0, cpu), fwspec->param[0]);\n+\t\trouted_elsewhere = routing_old && fwspec->param[1] != routing_old - 1;\n+\t\tif (routed_elsewhere) {\n+\t\t\tpr_warn(\"soc int %d already routed to output %d\\n\",\n+\t\t\t\tfwspec->param[0], routing_old - 1);\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\n+\traw_spin_unlock_irqrestore(&irq_lock, flags);\n+\n+\treturn !routed_elsewhere && fwspec->param[1] == output->output_index;\n+}\n+\n static const struct irq_domain_ops irq_domain_ops = {\n \t.map = intc_map,\n+\t.select = intc_select,\n \t.xlate = irq_domain_xlate_onecell,\n };\n \n static void realtek_irq_dispatch(struct irq_desc *desc)\n {\n+\tstruct realtek_ictl_output *output = irq_desc_get_handler_data(desc);\n \tstruct irq_chip *chip = irq_desc_get_chip(desc);\n-\tstruct irq_domain *domain;\n-\tunsigned int pending;\n+\tint cpu = smp_processor_id();\n+\tunsigned long pending;\n+\tunsigned int soc_int;\n \n \tchained_irq_enter(chip, desc);\n-\tpending = readl(REG(RTL_ICTL_GIMR)) & readl(REG(RTL_ICTL_GISR));\n+\tpending = readl(REG(RTL_ICTL_GIMR, cpu)) & readl(REG(RTL_ICTL_GISR, cpu))\n+\t\t& output->child_mask;\n+\n \tif (unlikely(!pending)) {\n \t\tspurious_interrupt();\n \t\tgoto out;\n \t}\n-\tdomain = irq_desc_get_handler_data(desc);\n-\tgeneric_handle_irq(irq_find_mapping(domain, __ffs(pending)));\n+\n+\tfor_each_set_bit(soc_int, &pending, RTL_ICTL_NUM_INPUTS)\n+\t\tgeneric_handle_irq(irq_find_mapping(output->domain, soc_int));\n+//\t\tgeneric_handle_domain_irq(output->domain, soc_int);\n \n out:\n \tchained_irq_exit(chip, desc);\n }\n \n-/*\n- * SoC interrupts are cascaded to MIPS CPU interrupts according to the\n- * interrupt-map in the device tree. Each SoC interrupt gets 4 bits for\n- * the CPU interrupt in an Interrupt Routing Register. Max 32 SoC interrupts\n- * thus go into 4 IRRs.\n- */\n-static int __init map_interrupts(struct device_node *node, struct irq_domain *domain)\n+static int __init setup_parent_interrupts(struct device_node *node, int *parents,\n+\tunsigned int num_parents)\n {\n-\tstruct device_node *cpu_ictl;\n-\tconst __be32 *imap;\n-\tu32 imaplen, soc_int, cpu_int, tmp, regs[4];\n-\tint ret, i, irr_regs[] = {\n-\t\tRTL_ICTL_IRR3,\n-\t\tRTL_ICTL_IRR2,\n-\t\tRTL_ICTL_IRR1,\n-\t\tRTL_ICTL_IRR0,\n-\t};\n-\tu8 mips_irqs_set;\n+\tstruct realtek_ictl_output *outputs;\n+\tstruct realtek_ictl_output *output;\n+\tstruct irq_domain *domain;\n+\tunsigned int p;\n \n-\tret = of_property_read_u32(node, \"#address-cells\", &tmp);\n-\tif (ret || tmp)\n-\t\treturn -EINVAL;\n+\toutputs = kcalloc(num_parents, sizeof(*outputs), GFP_KERNEL);\n+\tif (!outputs)\n+\t\treturn -ENOMEM;\n \n-\timap = of_get_property(node, \"interrupt-map\", &imaplen);\n-\tif (!imap || imaplen % 3)\n-\t\treturn -EINVAL;\n+\tfor (p = 0; p < num_parents; p++) {\n+\t\toutput = outputs + p;\n \n-\tmips_irqs_set = 0;\n-\tmemset(regs, 0, sizeof(regs));\n-\tfor (i = 0; i < imaplen; i += 3 * sizeof(u32)) {\n-\t\tsoc_int = be32_to_cpup(imap);\n-\t\tif (soc_int > 31)\n-\t\t\treturn -EINVAL;\n-\n-\t\tcpu_ictl = of_find_node_by_phandle(be32_to_cpup(imap + 1));\n-\t\tif (!cpu_ictl)\n-\t\t\treturn -EINVAL;\n-\t\tret = of_property_read_u32(cpu_ictl, \"#interrupt-cells\", &tmp);\n-\t\tif (ret || tmp != 1)\n-\t\t\treturn -EINVAL;\n-\t\tof_node_put(cpu_ictl);\n-\n-\t\tcpu_int = be32_to_cpup(imap + 2);\n-\t\tif (cpu_int > 7)\n-\t\t\treturn -EINVAL;\n-\n-\t\tif (!(mips_irqs_set & BIT(cpu_int))) {\n-\t\t\tirq_set_chained_handler_and_data(cpu_int, realtek_irq_dispatch,\n-\t\t\t\t\t\t\t domain);\n-\t\t\tmips_irqs_set |= BIT(cpu_int);\n-\t\t}\n+\t\tdomain = irq_domain_add_linear(node, RTL_ICTL_NUM_INPUTS, &irq_domain_ops, output);\n+\t\tif (!domain)\n+\t\t\tgoto domain_err;\n \n-\t\tregs[(soc_int * 4) / 32] |= cpu_int << (soc_int * 4) % 32;\n-\t\timap += 3;\n-\t}\n+\t\toutput->fwnode = of_node_to_fwnode(node);\n+\t\toutput->output_index = p;\n+\t\toutput->domain = domain;\n \n-\tfor (i = 0; i < 4; i++)\n-\t\twritel(regs[i], REG(irr_regs[i]));\n+\t\tirq_set_chained_handler_and_data(parents[p], realtek_irq_dispatch, output);\n+\t}\n \n \treturn 0;\n+\n+domain_err:\n+\twhile (p--) {\n+\t\tirq_set_chained_handler_and_data(parents[p], NULL, NULL);\n+\t\tirq_domain_remove(outputs[p].domain);\n+\t}\n+\n+\tkfree(outputs);\n+\n+\treturn -ENOMEM;\n }\n \n static int __init realtek_rtl_of_init(struct device_node *node, struct device_node *parent)\n {\n-\tstruct irq_domain *domain;\n-\tint ret;\n+\tint parent_irqs[RTL_ICTL_NUM_OUTPUTS];\n+\tstruct of_phandle_args oirq;\n+\tunsigned int num_parents;\n+\tunsigned int soc_irq;\n+\tunsigned int p;\n+\tint cpu;\n+\n+\tcpumask_clear(&realtek_ictl_cpu_configurable);\n+\n+\tfor (cpu = 0; cpu < NR_CPUS; cpu++) {\n+\t\trealtek_ictl_base[cpu] = of_iomap(node, cpu);\n+\t\tif (realtek_ictl_base[cpu]) {\n+\t\t\tcpumask_set_cpu(cpu, &realtek_ictl_cpu_configurable);\n+\n+\t\t\t/* Disable all cascaded interrupts and clear routing */\n+\t\t\twritel(0, REG(RTL_ICTL_GIMR, cpu));\n+\t\t\tfor (soc_irq = 0; soc_irq < RTL_ICTL_NUM_INPUTS; soc_irq++)\n+\t\t\t\twrite_irr(REG(RTL_ICTL_IRR0, cpu), soc_irq, 0);\n+\t\t}\n+\t}\n \n-\trealtek_ictl_base = of_iomap(node, 0);\n-\tif (!realtek_ictl_base)\n+\tif (cpumask_empty(&realtek_ictl_cpu_configurable))\n \t\treturn -ENXIO;\n \n-\t/* Disable all cascaded interrupts */\n-\twritel(0, REG(RTL_ICTL_GIMR));\n+\tnum_parents = of_irq_count(node);\n+\tif (num_parents > RTL_ICTL_NUM_OUTPUTS) {\n+\t\tpr_err(\"too many parent interrupts\\n\");\n+\t\treturn -EINVAL;\n+\t}\n \n-\tdomain = irq_domain_add_simple(node, 32, 0,\n-\t\t\t\t       &irq_domain_ops, NULL);\n+\tfor (p = 0; p < num_parents; p++)\n+\t\tparent_irqs[p] = of_irq_get(node, p);\n \n-\tret = map_interrupts(node, domain);\n-\tif (ret) {\n-\t\tpr_err(\"invalid interrupt map\\n\");\n-\t\treturn ret;\n+\tif (WARN_ON(!num_parents)) {\n+\t\t/*\n+\t\t * If DT contains no parent interrupts, assume MIPS CPU IRQ 2\n+\t\t * (HW0) is connected to the first output. This is the case for\n+\t\t * all known hardware anyway. \"interrupt-map\" is deprecated, so\n+\t\t * don't bother trying to parse that.\n+\t\t * Since this is to account for old devicetrees with one-cell\n+\t\t * interrupt specifiers, only one output domain is needed.\n+\t\t */\n+\t\toirq.np = of_find_compatible_node(NULL, NULL, \"mti,cpu-interrupt-controller\");\n+\t\tif (oirq.np) {\n+\t\t\toirq.args_count = 1;\n+\t\t\toirq.args[0] = 2;\n+\n+\t\t\tparent_irqs[0] = irq_create_of_mapping(&oirq);\n+\t\t\tnum_parents = 1;\n+\t\t}\n+\n+\t\tof_node_put(oirq.np);\n \t}\n \n-\treturn 0;\n+\t/* Ensure we haven't collected any errors before proceeding */\n+\tfor (p = 0; p < num_parents; p++) {\n+\t\tif (parent_irqs[p] < 0)\n+\t\t\treturn parent_irqs[p];\n+\t\tif (!parent_irqs[p])\n+\t\t\treturn -ENODEV;\n+\t}\n+\n+\treturn setup_parent_interrupts(node, &parent_irqs[0], num_parents);\n }\n \n IRQCHIP_DECLARE(realtek_rtl_intc, \"realtek,rtl-intc\", realtek_rtl_of_init);\n"
  },
  {
    "path": "target/linux/realtek/patches-5.10/320-gpio-add-support-for-RTL930X-and-RTL931X.patch",
    "content": "--- a/drivers/gpio/gpio-realtek-otto.c\n+++ b/drivers/gpio/gpio-realtek-otto.c\n@@ -55,9 +55,12 @@\n struct realtek_gpio_ctrl {\n \tstruct gpio_chip gc;\n \tvoid __iomem *base;\n+\tvoid __iomem *cpumap_base;\n \traw_spinlock_t lock;\n \tu16 intr_mask[REALTEK_GPIO_PORTS_PER_BANK];\n \tu16 intr_type[REALTEK_GPIO_PORTS_PER_BANK];\n+\tunsigned int (*port_offset_u8)(unsigned int port);\n+\tunsigned int (*port_offset_u16)(unsigned int port);\n };\n \n /* Expand with more flags as devices with other quirks are added */\n@@ -69,6 +72,16 @@ enum realtek_gpio_flags {\n \t * line the IRQ handler was assigned to, causing uncaught interrupts.\n \t */\n \tGPIO_INTERRUPTS_DISABLED = BIT(0),\n+\t/*\n+\t * Port order is reversed, meaning DCBA register layout for 1-bit\n+\t * fields, and [BA, DC] for 2-bit fields.\n+\t */\n+\tGPIO_PORTS_REVERSED = BIT(1),\n+\t/*\n+\t * Interrupts can be enabled per cpu. This requires a secondary IO\n+\t * range, where the per-cpu enable masks are located.\n+\t */\n+\tGPIO_INTERRUPTS_PER_CPU = BIT(2),\n };\n \n static struct realtek_gpio_ctrl *irq_data_to_ctrl(struct irq_data *data)\n@@ -86,21 +99,50 @@ static struct realtek_gpio_ctrl *irq_dat\n  * port. The two interrupt mask registers store two bits per GPIO, so use u16\n  * values.\n  */\n+static unsigned int realtek_gpio_port_offset_u8(unsigned int port)\n+{\n+\treturn port;\n+}\n+\n+static unsigned int realtek_gpio_port_offset_u16(unsigned int port)\n+{\n+\treturn 2 * port;\n+}\n+\n+/*\n+ * Reversed port order register access\n+ *\n+ * For registers with one bit per GPIO, all ports are stored as u8-s in one\n+ * register in reversed order. The two interrupt mask registers store two bits\n+ * per GPIO, so use u16 values. The first register contains ports 1 and 0, the\n+ * second ports 3 and 2.\n+ */\n+static unsigned int realtek_gpio_port_offset_u8_rev(unsigned int port)\n+{\n+\treturn 3 - port;\n+}\n+\n+static unsigned int realtek_gpio_port_offset_u16_rev(unsigned int port)\n+{\n+\treturn 2 * (port ^ 1);\n+}\n+\n static void realtek_gpio_write_imr(struct realtek_gpio_ctrl *ctrl,\n \tunsigned int port, u16 irq_type, u16 irq_mask)\n {\n-\tiowrite16(irq_type & irq_mask, ctrl->base + REALTEK_GPIO_REG_IMR + 2 * port);\n+\tiowrite16(irq_type & irq_mask,\n+\t\tctrl->base + REALTEK_GPIO_REG_IMR + ctrl->port_offset_u16(port));\n }\n \n static void realtek_gpio_clear_isr(struct realtek_gpio_ctrl *ctrl,\n \tunsigned int port, u8 mask)\n {\n-\tiowrite8(mask, ctrl->base + REALTEK_GPIO_REG_ISR + port);\n+\tiowrite8(mask, ctrl->base + REALTEK_GPIO_REG_ISR + ctrl->port_offset_u8(port));\n }\n \n static u8 realtek_gpio_read_isr(struct realtek_gpio_ctrl *ctrl, unsigned int port)\n {\n-\treturn ioread8(ctrl->base + REALTEK_GPIO_REG_ISR + port);\n+\treturn ioread8(ctrl->base + REALTEK_GPIO_REG_ISR + ctrl->port_offset_u8(port));\n }\n \n /* Set the rising and falling edge mask bits for a GPIO port pin */\n@@ -222,6 +264,12 @@ static int realtek_gpio_irq_init(struct\n \tfor (port = 0; (port * 8) < gc->ngpio; port++) {\n \t\trealtek_gpio_write_imr(ctrl, port, 0, 0);\n \t\trealtek_gpio_clear_isr(ctrl, port, GENMASK(7, 0));\n+\n+\t\tif (ctrl->cpumap_base) {\n+\t\t\t/* Default CPU affinity to the first CPU */\n+\t\t\tiowrite8(GENMASK(7, 0),\n+\t\t\t\tctrl->cpumap_base + ctrl->port_offset_u8(port));\n+\t\t}\n \t}\n \n \treturn 0;\n@@ -246,6 +294,13 @@ static const struct of_device_id realtek\n \t{\n \t\t.compatible = \"realtek,rtl8390-gpio\",\n \t},\n+\t{\n+\t\t.compatible = \"realtek,rtl9300-gpio\",\n+\t\t.data = (void *)(GPIO_PORTS_REVERSED | GPIO_INTERRUPTS_PER_CPU)\n+\t},\n+\t{\n+\t\t.compatible = \"realtek,rtl9310-gpio\",\n+\t},\n \t{}\n };\n MODULE_DEVICE_TABLE(of, realtek_gpio_of_match);\n@@ -253,12 +308,14 @@ MODULE_DEVICE_TABLE(of, realtek_gpio_of_\n static int realtek_gpio_probe(struct platform_device *pdev)\n {\n \tstruct device *dev = &pdev->dev;\n+\tunsigned long bgpio_flags;\n \tunsigned int dev_flags;\n \tstruct gpio_irq_chip *girq;\n \tstruct realtek_gpio_ctrl *ctrl;\n \tu32 ngpios;\n \tint err, irq;\n \n+\tpr_info(\"%s probing RTL GPIO\\n\", __func__);\n \tctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);\n \tif (!ctrl)\n \t\treturn -ENOMEM;\n@@ -280,10 +337,21 @@ static int realtek_gpio_probe(struct pla\n \n \traw_spin_lock_init(&ctrl->lock);\n \n+\tif (dev_flags & GPIO_PORTS_REVERSED) {\n+\t\tbgpio_flags = 0;\n+\t\tctrl->port_offset_u8 = realtek_gpio_port_offset_u8_rev;\n+\t\tctrl->port_offset_u16 = realtek_gpio_port_offset_u16_rev;\n+\t}\n+\telse {\n+\t\tbgpio_flags = BGPIOF_BIG_ENDIAN_BYTE_ORDER;\n+\t\tctrl->port_offset_u8 = realtek_gpio_port_offset_u8;\n+\t\tctrl->port_offset_u16 = realtek_gpio_port_offset_u16;\n+\t}\n+\n \terr = bgpio_init(&ctrl->gc, dev, 4,\n \t\tctrl->base + REALTEK_GPIO_REG_DATA, NULL, NULL,\n \t\tctrl->base + REALTEK_GPIO_REG_DIR, NULL,\n-\t\tBGPIOF_BIG_ENDIAN_BYTE_ORDER);\n+\t\tbgpio_flags);\n \tif (err) {\n \t\tdev_err(dev, \"unable to init generic GPIO\");\n \t\treturn err;\n@@ -308,6 +376,13 @@ static int realtek_gpio_probe(struct pla\n \t\tgirq->init_hw = realtek_gpio_irq_init;\n \t}\n \n+\tif (dev_flags & GPIO_INTERRUPTS_PER_CPU) {\n+\t\tctrl->cpumap_base = devm_platform_ioremap_resource(pdev, 1);\n+\t\tif (IS_ERR(ctrl->cpumap_base))\n+\t\t\treturn dev_err_probe(dev, PTR_ERR(ctrl->cpumap_base),\n+\t\t\t\t\"IRQ CPU map registers not defined\");\n+\t}\n+\n \treturn devm_gpiochip_add_data(dev, &ctrl->gc, ctrl);\n }\n \n"
  },
  {
    "path": "target/linux/realtek/patches-5.10/700-net-dsa-add-support-for-rtl838x-switch.patch",
    "content": "--- a/drivers/net/dsa/Kconfig\n+++ b/drivers/net/dsa/Kconfig\n@@ -68,6 +68,8 @@ config NET_DSA_QCA8K\n \t  This enables support for the Qualcomm Atheros QCA8K Ethernet\n \t  switch chips.\n \n+source \"drivers/net/dsa/rtl83xx/Kconfig\"\n+\n config NET_DSA_REALTEK_SMI\n \ttristate \"Realtek SMI Ethernet switch family support\"\n \tdepends on NET_DSA\n--- a/drivers/net/dsa/Makefile\n+++ b/drivers/net/dsa/Makefile\n@@ -23,3 +23,4 @@ obj-y\t\t\t\t+= mv88e6xxx/\n obj-y\t\t\t\t+= ocelot/\n obj-y\t\t\t\t+= qca/\n obj-y\t\t\t\t+= sja1105/\n+obj-y\t\t\t\t+= rtl83xx/\n"
  },
  {
    "path": "target/linux/realtek/patches-5.10/701-net-dsa-add-rtl838x-support-for-tag-trailer.patch",
    "content": "--- a/net/dsa/tag_trailer.c\n+++ b/net/dsa/tag_trailer.c\n@@ -17,7 +17,12 @@ static struct sk_buff *trailer_xmit(stru\n \n \ttrailer = skb_put(skb, 4);\n \ttrailer[0] = 0x80;\n+\n+#ifdef CONFIG_NET_DSA_RTL83XX\n+\ttrailer[1] = dp->index;\n+#else\n \ttrailer[1] = 1 << dp->index;\n+#endif /* CONFIG_NET_DSA_RTL838X */\n \ttrailer[2] = 0x10;\n \ttrailer[3] = 0x00;\n \n@@ -34,12 +39,23 @@ static struct sk_buff *trailer_rcv(struc\n \t\treturn NULL;\n \n \ttrailer = skb_tail_pointer(skb) - 4;\n+\n+#ifdef CONFIG_NET_DSA_RTL83XX\n+\tif (trailer[0] != 0x80 || (trailer[1] & 0x80) != 0x00 ||\n+\t    (trailer[2] & 0xef) != 0x00 || trailer[3] != 0x00)\n+\t\treturn NULL;\n+\n+\tif (trailer[1] & 0x40)\n+\t\tskb->offload_fwd_mark = 1;\n+\n+\tsource_port = trailer[1] & 0x3f;\n+#else\n \tif (trailer[0] != 0x80 || (trailer[1] & 0xf8) != 0x00 ||\n \t    (trailer[2] & 0xef) != 0x00 || trailer[3] != 0x00)\n \t\treturn NULL;\n \n \tsource_port = trailer[1] & 7;\n-\n+#endif\n \tskb->dev = dsa_master_find_slave(dev, 0, source_port);\n \tif (!skb->dev)\n \t\treturn NULL;\n"
  },
  {
    "path": "target/linux/realtek/patches-5.10/702-net-dsa-increase-dsa-max-ports-for-rtl838x.patch",
    "content": "--- a/include/linux/platform_data/dsa.h\n+++ b/include/linux/platform_data/dsa.h\n@@ -6,7 +6,7 @@ struct device;\n struct net_device;\n \n #define DSA_MAX_SWITCHES\t4\n-#define DSA_MAX_PORTS\t\t12\n+#define DSA_MAX_PORTS\t\t54\n #define DSA_RTABLE_NONE\t\t-1\n \n struct dsa_chip_data {\n"
  },
  {
    "path": "target/linux/realtek/patches-5.10/702-net-ethernet-add-support-for-rtl838x-ethernet.patch",
    "content": "--- a/drivers/net/ethernet/Kconfig\n+++ b/drivers/net/ethernet/Kconfig\n@@ -163,6 +163,13 @@ source \"drivers/net/ethernet/rdc/Kconfig\n source \"drivers/net/ethernet/realtek/Kconfig\"\n source \"drivers/net/ethernet/renesas/Kconfig\"\n source \"drivers/net/ethernet/rocker/Kconfig\"\n+\n+config NET_RTL838X\n+\ttristate \"Realtek rtl838x Ethernet MAC support\"\n+\tdepends on RTL83XX\n+\thelp\n+\t  Say Y here if you want to use the Realtek rtl838x Gbps Ethernet MAC.\n+\n source \"drivers/net/ethernet/samsung/Kconfig\"\n source \"drivers/net/ethernet/seeq/Kconfig\"\n source \"drivers/net/ethernet/sfc/Kconfig\"\n--- a/drivers/net/ethernet/Makefile\n+++ b/drivers/net/ethernet/Makefile\n@@ -75,6 +75,7 @@ obj-$(CONFIG_NET_VENDOR_REALTEK) += real\n obj-$(CONFIG_NET_VENDOR_RENESAS) += renesas/\n obj-$(CONFIG_NET_VENDOR_RDC) += rdc/\n obj-$(CONFIG_NET_VENDOR_ROCKER) += rocker/\n+obj-$(CONFIG_NET_RTL838X) += rtl838x_eth.o\n obj-$(CONFIG_NET_VENDOR_SAMSUNG) += samsung/\n obj-$(CONFIG_NET_VENDOR_SEEQ) += seeq/\n obj-$(CONFIG_NET_VENDOR_SILAN) += silan/\n"
  },
  {
    "path": "target/linux/realtek/patches-5.10/703-include-linux-add-phy-ops-for-rtl838x.patch",
    "content": "--- a/include/linux/phy.h\n+++ b/include/linux/phy.h\n@@ -885,6 +885,10 @@ struct phy_driver {\n \tint (*get_sqi)(struct phy_device *dev);\n \t/** @get_sqi_max: Get the maximum signal quality indication */\n \tint (*get_sqi_max)(struct phy_device *dev);\n+\tint (*get_port)(struct phy_device *dev);\n+\tint (*set_port)(struct phy_device *dev, int port);\n+\tint (*get_eee)(struct phy_device *dev, struct ethtool_eee *e);\n+\tint (*set_eee)(struct phy_device *dev, struct ethtool_eee *e);\n };\n #define to_phy_driver(d) container_of(to_mdio_common_driver(d),\t\t\\\n \t\t\t\t      struct phy_driver, mdiodrv)\n"
  },
  {
    "path": "target/linux/realtek/patches-5.10/704-drivers-net-phy-eee-support-for-rtl838x.patch",
    "content": "--- a/drivers/net/phy/phylink.c\n+++ b/drivers/net/phy/phylink.c\n@@ -1449,6 +1449,11 @@ int phylink_ethtool_ksettings_set(struct\n \t\t *   the presence of a PHY, this should not be changed as that\n \t\t *   should be determined from the media side advertisement.\n \t\t */\n+\t\tif (pl->phydev->drv->get_port && pl->phydev->drv->set_port) {\n+\t\t\tif(pl->phydev->drv->get_port(pl->phydev) != kset->base.port) {\n+\t\t\t\tpl->phydev->drv->set_port(pl->phydev, kset->base.port);\n+\t\t\t}\n+\t\t}\n \t\treturn phy_ethtool_ksettings_set(pl->phydev, kset);\n \t}\n \n@@ -1750,8 +1755,11 @@ int phylink_ethtool_get_eee(struct phyli\n \n \tASSERT_RTNL();\n \n-\tif (pl->phydev)\n+\tif (pl->phydev) {\n+\t\tif (pl->phydev->drv->get_eee)\n+\t\t\treturn pl->phydev->drv->get_eee(pl->phydev, eee);\n \t\tret = phy_ethtool_get_eee(pl->phydev, eee);\n+\t}\n \n \treturn ret;\n }\n@@ -1768,8 +1776,11 @@ int phylink_ethtool_set_eee(struct phyli\n \n \tASSERT_RTNL();\n \n-\tif (pl->phydev)\n+\tif (pl->phydev) {\n+\t\tif (pl->phydev->drv->set_eee)\n+\t\t\treturn pl->phydev->drv->set_eee(pl->phydev, eee);\n \t\tret = phy_ethtool_set_eee(pl->phydev, eee);\n+\t}\n \n \treturn ret;\n }\n"
  },
  {
    "path": "target/linux/realtek/patches-5.10/704-include-linux-add-phy-hsgmii-mode.patch",
    "content": "--- a/include/linux/phy.h\n+++ b/include/linux/phy.h\n@@ -134,6 +134,7 @@ typedef enum {\n \tPHY_INTERFACE_MODE_XGMII,\n \tPHY_INTERFACE_MODE_XLGMII,\n \tPHY_INTERFACE_MODE_MOCA,\n+\tPHY_INTERFACE_MODE_HSGMII,\n \tPHY_INTERFACE_MODE_QSGMII,\n \tPHY_INTERFACE_MODE_TRGMII,\n \tPHY_INTERFACE_MODE_100BASEX,\n@@ -201,6 +202,8 @@ static inline const char *phy_modes(phy_\n \t\treturn \"xlgmii\";\n \tcase PHY_INTERFACE_MODE_MOCA:\n \t\treturn \"moca\";\n+\tcase PHY_INTERFACE_MODE_HSGMII:\n+\t\treturn \"hsgmii\";\n \tcase PHY_INTERFACE_MODE_QSGMII:\n \t\treturn \"qsgmii\";\n \tcase PHY_INTERFACE_MODE_TRGMII:\n"
  },
  {
    "path": "target/linux/realtek/patches-5.10/705-add-rtl-phy.patch",
    "content": "--- a/drivers/net/phy/Kconfig\n+++ b/drivers/net/phy/Kconfig\n@@ -330,6 +330,12 @@ config REALTEK_PHY\n \thelp\n \t  Supports the Realtek 821x PHY.\n \n+config REALTEK_SOC_PHY\n+\ttristate \"Realtek SoC PHYs\"\n+\tdepends on RTL83XX\n+\thelp\n+\t  Supports the PHYs found in combination with Realtek Switch SoCs\n+\n config RENESAS_PHY\n \ttristate \"Renesas PHYs\"\n \thelp\n--- a/drivers/net/phy/Makefile\n+++ b/drivers/net/phy/Makefile\n@@ -87,6 +87,7 @@ obj-$(CONFIG_NATIONAL_PHY)\t+= national.o\n obj-$(CONFIG_NXP_TJA11XX_PHY)\t+= nxp-tja11xx.o\n obj-$(CONFIG_QSEMI_PHY)\t\t+= qsemi.o\n obj-$(CONFIG_REALTEK_PHY)\t+= realtek.o\n+obj-$(CONFIG_REALTEK_SOC_PHY)   += rtl83xx-phy.o\n obj-$(CONFIG_RENESAS_PHY)\t+= uPD60620.o\n obj-$(CONFIG_ROCKCHIP_PHY)\t+= rockchip.o\n obj-$(CONFIG_SMSC_PHY)\t\t+= smsc.o\n"
  },
  {
    "path": "target/linux/realtek/patches-5.10/705-include-linux-phy-increase-phy-address-number-for-rtl839x.patch",
    "content": "--- a/include/linux/phy.h\n+++ b/include/linux/phy.h\n@@ -233,7 +233,7 @@ static inline const char *phy_modes(phy_\n #define PHY_INIT_TIMEOUT\t100000\n #define PHY_FORCE_TIMEOUT\t10\n \n-#define PHY_MAX_ADDR\t32\n+#define PHY_MAX_ADDR\t64\n \n /* Used when trying to connect to a specific phy (mii bus id:phy device id) */\n #define PHY_ID_FMT \"%s:%02x\"\n"
  },
  {
    "path": "target/linux/realtek/patches-5.10/708-brflood-api.patch",
    "content": "--- a/include/net/dsa.h\n+++ b/include/net/dsa.h\n@@ -552,8 +552,14 @@ struct dsa_switch_ops {\n \tvoid\t(*port_stp_state_set)(struct dsa_switch *ds, int port,\n \t\t\t\t      u8 state);\n \tvoid\t(*port_fast_age)(struct dsa_switch *ds, int port);\n-\tint\t(*port_egress_floods)(struct dsa_switch *ds, int port,\n-\t\t\t\t      bool unicast, bool multicast);\n+\tint\t(*port_pre_bridge_flags)(struct dsa_switch *ds, int port,\n+\t\t\t\t\t unsigned long flags,\n+\t\t\t\t\t struct netlink_ext_ack *extack);\n+\tint\t(*port_bridge_flags)(struct dsa_switch *ds, int port,\n+\t\t\t\t     unsigned long flags,\n+\t\t\t\t     struct netlink_ext_ack *extack);\n+\tint\t(*port_set_mrouter)(struct dsa_switch *ds, int port, bool mrouter,\n+\t\t\t\t    struct netlink_ext_ack *extack);\n \n \t/*\n \t * VLAN support\n--- a/net/dsa/dsa_priv.h\n+++ b/net/dsa/dsa_priv.h\n@@ -167,11 +167,11 @@ int dsa_port_mdb_add(const struct dsa_po\n int dsa_port_mdb_del(const struct dsa_port *dp,\n \t\t     const struct switchdev_obj_port_mdb *mdb);\n int dsa_port_pre_bridge_flags(const struct dsa_port *dp, unsigned long flags,\n-\t\t\t      struct switchdev_trans *trans);\n+\t\t\t      struct switchdev_trans *trans, struct netlink_ext_ack *extack);\n int dsa_port_bridge_flags(const struct dsa_port *dp, unsigned long flags,\n-\t\t\t  struct switchdev_trans *trans);\n+\t\t\t  struct switchdev_trans *trans, struct netlink_ext_ack *extack);\n int dsa_port_mrouter(struct dsa_port *dp, bool mrouter,\n-\t\t     struct switchdev_trans *trans);\n+\t\t     struct switchdev_trans *trans, struct netlink_ext_ack *extack);\n int dsa_port_vlan_add(struct dsa_port *dp,\n \t\t      const struct switchdev_obj_port_vlan *vlan,\n \t\t      struct switchdev_trans *trans);\n--- a/net/dsa/port.c\n+++ b/net/dsa/port.c\n@@ -145,7 +145,7 @@ int dsa_port_bridge_join(struct dsa_port\n \tint err;\n \n \t/* Set the flooding mode before joining the port in the switch */\n-\terr = dsa_port_bridge_flags(dp, BR_FLOOD | BR_MCAST_FLOOD, NULL);\n+\terr = dsa_port_bridge_flags(dp, BR_FLOOD | BR_MCAST_FLOOD, NULL, NULL);\n \tif (err)\n \t\treturn err;\n \n@@ -158,7 +158,7 @@ int dsa_port_bridge_join(struct dsa_port\n \n \t/* The bridging is rolled back on error */\n \tif (err) {\n-\t\tdsa_port_bridge_flags(dp, 0, NULL);\n+\t\tdsa_port_bridge_flags(dp, 0, NULL, NULL);\n \t\tdp->bridge_dev = NULL;\n \t}\n \n@@ -185,7 +185,7 @@ void dsa_port_bridge_leave(struct dsa_po\n \t\tpr_err(\"DSA: failed to notify DSA_NOTIFIER_BRIDGE_LEAVE\\n\");\n \n \t/* Port is leaving the bridge, disable flooding */\n-\tdsa_port_bridge_flags(dp, 0, NULL);\n+\tdsa_port_bridge_flags(dp, 0, NULL, NULL);\n \n \t/* Port left the bridge, put in BR_STATE_DISABLED by the bridge layer,\n \t * so allow it to be in BR_STATE_FORWARDING to be kept functional\n@@ -333,44 +333,44 @@ int dsa_port_ageing_time(struct dsa_port\n }\n \n int dsa_port_pre_bridge_flags(const struct dsa_port *dp, unsigned long flags,\n-\t\t\t      struct switchdev_trans *trans)\n+\t\t\t      struct switchdev_trans *trans, struct netlink_ext_ack *extack)\n {\n \tstruct dsa_switch *ds = dp->ds;\n \n-\tif (!ds->ops->port_egress_floods ||\n-\t    (flags & ~(BR_FLOOD | BR_MCAST_FLOOD)))\n+\tif (!ds->ops->port_pre_bridge_flags)\n \t\treturn -EINVAL;\n \n-\treturn 0;\n+\treturn ds->ops->port_pre_bridge_flags(ds, dp->index, flags, extack);\n }\n \n int dsa_port_bridge_flags(const struct dsa_port *dp, unsigned long flags,\n-\t\t\t  struct switchdev_trans *trans)\n+\t\t\t  struct switchdev_trans *trans, struct netlink_ext_ack *extack)\n {\n \tstruct dsa_switch *ds = dp->ds;\n-\tint port = dp->index;\n-\tint err = 0;\n \n \tif (switchdev_trans_ph_prepare(trans))\n \t\treturn 0;\n \n-\tif (ds->ops->port_egress_floods)\n-\t\terr = ds->ops->port_egress_floods(ds, port, flags & BR_FLOOD,\n-\t\t\t\t\t\t  flags & BR_MCAST_FLOOD);\n+\tif (!ds->ops->port_bridge_flags)\n+\t\treturn -EINVAL;\n+ \n+\treturn ds->ops->port_bridge_flags(ds, dp->index, flags, extack);\n \n-\treturn err;\n }\n \n int dsa_port_mrouter(struct dsa_port *dp, bool mrouter,\n-\t\t     struct switchdev_trans *trans)\n+\t\t     struct switchdev_trans *trans,\n+\t\t     struct netlink_ext_ack *extack)\n {\n \tstruct dsa_switch *ds = dp->ds;\n-\tint port = dp->index;\n \n \tif (switchdev_trans_ph_prepare(trans))\n-\t\treturn ds->ops->port_egress_floods ? 0 : -EOPNOTSUPP;\n+\t\treturn ds->ops->port_set_mrouter ? 0 : -EOPNOTSUPP;\n+\n+\tif (!ds->ops->port_set_mrouter)\n+ \t\treturn -EOPNOTSUPP;\n \n-\treturn ds->ops->port_egress_floods(ds, port, true, mrouter);\n+\treturn ds->ops->port_set_mrouter(ds, dp->index, mrouter, extack);\n }\n \n int dsa_port_mtu_change(struct dsa_port *dp, int new_mtu,\n--- a/net/dsa/slave.c\n+++ b/net/dsa/slave.c\n@@ -290,13 +290,13 @@ static int dsa_slave_port_attr_set(struc\n \t\tbreak;\n \tcase SWITCHDEV_ATTR_ID_PORT_PRE_BRIDGE_FLAGS:\n \t\tret = dsa_port_pre_bridge_flags(dp, attr->u.brport_flags,\n-\t\t\t\t\t\ttrans);\n+\t\t\t\t\t\ttrans, NULL);\n \t\tbreak;\n \tcase SWITCHDEV_ATTR_ID_PORT_BRIDGE_FLAGS:\n-\t\tret = dsa_port_bridge_flags(dp, attr->u.brport_flags, trans);\n+\t\tret = dsa_port_bridge_flags(dp, attr->u.brport_flags, trans, NULL);\n \t\tbreak;\n \tcase SWITCHDEV_ATTR_ID_BRIDGE_MROUTER:\n-\t\tret = dsa_port_mrouter(dp->cpu_dp, attr->u.mrouter, trans);\n+\t\tret = dsa_port_mrouter(dp->cpu_dp, attr->u.mrouter, trans, NULL);\n \t\tbreak;\n \tdefault:\n \t\tret = -EOPNOTSUPP;\n"
  },
  {
    "path": "target/linux/realtek/patches-5.10/709-lag-offloading.patch",
    "content": "--- a/drivers/net/bonding/bond_main.c\n+++ b/drivers/net/bonding/bond_main.c\n@@ -2046,6 +2046,8 @@ int bond_enslave(struct net_device *bond\n \t\tgoto err_unregister;\n \t}\n \n+\tbond_lower_state_changed(new_slave);\n+\n \tres = bond_sysfs_slave_add(new_slave);\n \tif (res) {\n \t\tslave_dbg(bond_dev, slave_dev, \"Error %d calling bond_sysfs_slave_add\\n\", res);\n--- a/include/net/dsa.h\n+++ b/include/net/dsa.h\n@@ -149,8 +149,41 @@ struct dsa_switch_tree {\n \n \t/* List of DSA links composing the routing table */\n \tstruct list_head rtable;\n+\n+\t/* Maps offloaded LAG netdevs to a zero-based linear ID for\n+\t * drivers that need it.\n+\t */\n+\tstruct net_device **lags;\n+\tunsigned int lags_len;\n };\n \n+#define dsa_lags_foreach_id(_id, _dst)\t\t\t\t\\\n+\tfor ((_id) = 0; (_id) < (_dst)->lags_len; (_id)++)\t\\\n+\t\tif ((_dst)->lags[(_id)])\n+\n+#define dsa_lag_foreach_port(_dp, _dst, _lag)\t\t\t\\\n+\tlist_for_each_entry((_dp), &(_dst)->ports, list)\t\\\n+\t\tif ((_dp)->lag_dev == (_lag))\n+\n+static inline struct net_device *dsa_lag_dev(struct dsa_switch_tree *dst,\n+\t\t\t\t\t     unsigned int id)\n+{\n+\treturn dst->lags[id];\n+}\n+\n+static inline int dsa_lag_id(struct dsa_switch_tree *dst,\n+\t\t\t     struct net_device *lag)\n+{\n+\tunsigned int id;\n+\n+\tdsa_lags_foreach_id(id, dst) {\n+\t\tif (dsa_lag_dev(dst, id) == lag)\n+\t\t\treturn id;\n+\t}\n+\n+\treturn -ENODEV;\n+}\n+\n /* TC matchall action types */\n enum dsa_port_mall_action_type {\n \tDSA_PORT_MALL_MIRROR,\n@@ -220,6 +253,8 @@ struct dsa_port {\n \tbool\t\t\tdevlink_port_setup;\n \tstruct phylink\t\t*pl;\n \tstruct phylink_config\tpl_config;\n+\tstruct net_device\t*lag_dev;\n+\tbool\t\t\tlag_tx_enabled;\n \n \tstruct list_head list;\n \n@@ -340,6 +375,14 @@ struct dsa_switch {\n \t */\n \tbool\t\t\tmtu_enforcement_ingress;\n \n+\t/* Drivers that benefit from having an ID associated with each\n+\t * offloaded LAG should set this to the maximum number of\n+\t * supported IDs. DSA will then maintain a mapping of _at\n+\t * least_ these many IDs, accessible to drivers via\n+\t * dsa_lag_id().\n+\t */\n+\tunsigned int\t\tnum_lag_ids;\n+\n \tsize_t num_ports;\n };\n \n@@ -432,6 +475,18 @@ static inline bool dsa_port_is_vlan_filt\n \t\treturn dp->vlan_filtering;\n }\n \n+static inline\n+struct net_device *dsa_port_to_bridge_port(const struct dsa_port *dp)\n+{\n+\tif (!dp->bridge_dev)\n+\t\treturn NULL;\n+\n+\tif (dp->lag_dev)\n+\t\treturn dp->lag_dev;\n+\n+\treturn dp->slave;\n+}\n+\n typedef int dsa_fdb_dump_cb_t(const unsigned char *addr, u16 vid,\n \t\t\t      bool is_static, void *data);\n struct dsa_switch_ops {\n@@ -629,6 +684,13 @@ struct dsa_switch_ops {\n \tvoid\t(*crosschip_bridge_leave)(struct dsa_switch *ds, int tree_index,\n \t\t\t\t\t  int sw_index, int port,\n \t\t\t\t\t  struct net_device *br);\n+\tint\t(*crosschip_lag_change)(struct dsa_switch *ds, int sw_index,\n+\t\t\t\t\tint port);\n+\tint\t(*crosschip_lag_join)(struct dsa_switch *ds, int sw_index,\n+\t\t\t\t      int port, struct net_device *lag,\n+\t\t\t\t      struct netdev_lag_upper_info *info);\n+\tint\t(*crosschip_lag_leave)(struct dsa_switch *ds, int sw_index,\n+\t\t\t\t       int port, struct net_device *lag);\n \n \t/*\n \t * PTP functionality\n@@ -660,6 +722,16 @@ struct dsa_switch_ops {\n \tint\t(*port_change_mtu)(struct dsa_switch *ds, int port,\n \t\t\t\t   int new_mtu);\n \tint\t(*port_max_mtu)(struct dsa_switch *ds, int port);\n+\n+\t/*\n+\t * LAG integration\n+\t */\n+\tint\t(*port_lag_change)(struct dsa_switch *ds, int port);\n+\tint\t(*port_lag_join)(struct dsa_switch *ds, int port,\n+\t\t\t\t struct net_device *lag,\n+\t\t\t\t struct netdev_lag_upper_info *info);\n+\tint\t(*port_lag_leave)(struct dsa_switch *ds, int port,\n+\t\t\t\t  struct net_device *lag);\n };\n \n #define DSA_DEVLINK_PARAM_DRIVER(_id, _name, _type, _cmodes)\t\t\\\n--- a/net/dsa/dsa.c\n+++ b/net/dsa/dsa.c\n@@ -220,11 +220,21 @@ static int dsa_switch_rcv(struct sk_buff\n \t}\n \n \tskb = nskb;\n-\tp = netdev_priv(skb->dev);\n \tskb_push(skb, ETH_HLEN);\n \tskb->pkt_type = PACKET_HOST;\n \tskb->protocol = eth_type_trans(skb, skb->dev);\n \n+\tif (unlikely(!dsa_slave_dev_check(skb->dev))) {\n+\t\t/* Packet is to be injected directly on an upper\n+\t\t * device, e.g. a team/bond, so skip all DSA-port\n+\t\t * specific actions.\n+\t\t */\n+\t\tnetif_rx(skb);\n+\t\treturn 0;\n+\t}\n+\n+\tp = netdev_priv(skb->dev);\n+\n \tif (unlikely(cpu_dp->ds->untag_bridge_pvid)) {\n \t\tnskb = dsa_untag_bridge_pvid(skb);\n \t\tif (!nskb) {\n--- a/net/dsa/dsa2.c\n+++ b/net/dsa/dsa2.c\n@@ -21,6 +21,65 @@\n static DEFINE_MUTEX(dsa2_mutex);\n LIST_HEAD(dsa_tree_list);\n \n+/**\n+ * dsa_lag_map() - Map LAG netdev to a linear LAG ID\n+ * @dst: Tree in which to record the mapping.\n+ * @lag: Netdev that is to be mapped to an ID.\n+ *\n+ * dsa_lag_id/dsa_lag_dev can then be used to translate between the\n+ * two spaces. The size of the mapping space is determined by the\n+ * driver by setting ds->num_lag_ids. It is perfectly legal to leave\n+ * it unset if it is not needed, in which case these functions become\n+ * no-ops.\n+ */\n+void dsa_lag_map(struct dsa_switch_tree *dst, struct net_device *lag)\n+{\n+\tunsigned int id;\n+\n+\tif (dsa_lag_id(dst, lag) >= 0)\n+\t\t/* Already mapped */\n+\t\treturn;\n+\n+\tfor (id = 0; id < dst->lags_len; id++) {\n+\t\tif (!dsa_lag_dev(dst, id)) {\n+\t\t\tdst->lags[id] = lag;\n+\t\t\treturn;\n+\t\t}\n+\t}\n+\n+\t/* No IDs left, which is OK. Some drivers do not need it. The\n+\t * ones that do, e.g. mv88e6xxx, will discover that dsa_lag_id\n+\t * returns an error for this device when joining the LAG. The\n+\t * driver can then return -EOPNOTSUPP back to DSA, which will\n+\t * fall back to a software LAG.\n+\t */\n+}\n+\n+/**\n+ * dsa_lag_unmap() - Remove a LAG ID mapping\n+ * @dst: Tree in which the mapping is recorded.\n+ * @lag: Netdev that was mapped.\n+ *\n+ * As there may be multiple users of the mapping, it is only removed\n+ * if there are no other references to it.\n+ */\n+void dsa_lag_unmap(struct dsa_switch_tree *dst, struct net_device *lag)\n+{\n+\tstruct dsa_port *dp;\n+\tunsigned int id;\n+\n+\tdsa_lag_foreach_port(dp, dst, lag)\n+\t\t/* There are remaining users of this mapping */\n+\t\treturn;\n+\n+\tdsa_lags_foreach_id(id, dst) {\n+\t\tif (dsa_lag_dev(dst, id) == lag) {\n+\t\t\tdst->lags[id] = NULL;\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+}\n+\n struct dsa_switch *dsa_switch_find(int tree_index, int sw_index)\n {\n \tstruct dsa_switch_tree *dst;\n@@ -597,6 +656,32 @@ static void dsa_tree_teardown_master(str\n \t\t\tdsa_master_teardown(dp->master);\n }\n \n+static int dsa_tree_setup_lags(struct dsa_switch_tree *dst)\n+{\n+\tunsigned int len = 0;\n+\tstruct dsa_port *dp;\n+\n+\tlist_for_each_entry(dp, &dst->ports, list) {\n+\t\tif (dp->ds->num_lag_ids > len)\n+\t\t\tlen = dp->ds->num_lag_ids;\n+\t}\n+\n+\tif (!len)\n+\t\treturn 0;\n+\n+\tdst->lags = kcalloc(len, sizeof(*dst->lags), GFP_KERNEL);\n+\tif (!dst->lags)\n+\t\treturn -ENOMEM;\n+\n+\tdst->lags_len = len;\n+\treturn 0;\n+}\n+\n+static void dsa_tree_teardown_lags(struct dsa_switch_tree *dst)\n+{\n+\tkfree(dst->lags);\n+}\n+\n static int dsa_tree_setup(struct dsa_switch_tree *dst)\n {\n \tbool complete;\n@@ -624,12 +709,18 @@ static int dsa_tree_setup(struct dsa_swi\n \tif (err)\n \t\tgoto teardown_switches;\n \n+\terr = dsa_tree_setup_lags(dst);\n+\tif (err)\n+\t\tgoto teardown_master;\n+\n \tdst->setup = true;\n \n \tpr_info(\"DSA: tree %d setup\\n\", dst->index);\n \n \treturn 0;\n \n+teardown_master:\n+\tdsa_tree_teardown_master(dst);\n teardown_switches:\n \tdsa_tree_teardown_switches(dst);\n teardown_default_cpu:\n@@ -645,6 +736,8 @@ static void dsa_tree_teardown(struct dsa\n \tif (!dst->setup)\n \t\treturn;\n \n+\tdsa_tree_teardown_lags(dst);\n+\n \tdsa_tree_teardown_master(dst);\n \n \tdsa_tree_teardown_switches(dst);\n--- a/net/dsa/dsa_priv.h\n+++ b/net/dsa/dsa_priv.h\n@@ -20,6 +20,9 @@ enum {\n \tDSA_NOTIFIER_BRIDGE_LEAVE,\n \tDSA_NOTIFIER_FDB_ADD,\n \tDSA_NOTIFIER_FDB_DEL,\n+\tDSA_NOTIFIER_LAG_CHANGE,\n+\tDSA_NOTIFIER_LAG_JOIN,\n+\tDSA_NOTIFIER_LAG_LEAVE,\n \tDSA_NOTIFIER_MDB_ADD,\n \tDSA_NOTIFIER_MDB_DEL,\n \tDSA_NOTIFIER_VLAN_ADD,\n@@ -57,6 +60,15 @@ struct dsa_notifier_mdb_info {\n \tint port;\n };\n \n+/* DSA_NOTIFIER_LAG_* */\n+struct dsa_notifier_lag_info {\n+\tstruct net_device *lag;\n+\tint sw_index;\n+\tint port;\n+\n+\tstruct netdev_lag_upper_info *info;\n+};\n+\n /* DSA_NOTIFIER_VLAN_* */\n struct dsa_notifier_vlan_info {\n \tconst struct switchdev_obj_port_vlan *vlan;\n@@ -149,6 +161,11 @@ void dsa_port_disable_rt(struct dsa_port\n void dsa_port_disable(struct dsa_port *dp);\n int dsa_port_bridge_join(struct dsa_port *dp, struct net_device *br);\n void dsa_port_bridge_leave(struct dsa_port *dp, struct net_device *br);\n+int dsa_port_lag_change(struct dsa_port *dp,\n+\t\t\tstruct netdev_lag_lower_state_info *linfo);\n+int dsa_port_lag_join(struct dsa_port *dp, struct net_device *lag_dev,\n+\t\t      struct netdev_lag_upper_info *uinfo);\n+void dsa_port_lag_leave(struct dsa_port *dp, struct net_device *lag_dev);\n int dsa_port_vlan_filtering(struct dsa_port *dp, bool vlan_filtering,\n \t\t\t    struct switchdev_trans *trans);\n bool dsa_port_skip_vlan_configuration(struct dsa_port *dp);\n@@ -181,6 +198,71 @@ int dsa_port_link_register_of(struct dsa\n void dsa_port_link_unregister_of(struct dsa_port *dp);\n extern const struct phylink_mac_ops dsa_port_phylink_mac_ops;\n \n+static inline bool dsa_port_offloads_netdev(struct dsa_port *dp,\n+\t\t\t\t\t    struct net_device *dev)\n+{\n+\t/* Switchdev offloading can be configured on: */\n+\n+\tif (dev == dp->slave)\n+\t\t/* DSA ports directly connected to a bridge, and event\n+\t\t * was emitted for the ports themselves.\n+\t\t */\n+\t\treturn true;\n+\n+\tif (dp->bridge_dev == dev)\n+\t\t/* DSA ports connected to a bridge, and event was emitted\n+\t\t * for the bridge.\n+\t\t */\n+\t\treturn true;\n+\n+\tif (dp->lag_dev == dev)\n+\t\t/* DSA ports connected to a bridge via a LAG */\n+\t\treturn true;\n+\n+\treturn false;\n+}\n+\n+static inline bool dsa_port_offloads_bridge_port(struct dsa_port *dp,\n+\t\t\t\t\t\t struct net_device *dev)\n+{\n+\treturn dsa_port_to_bridge_port(dp) == dev;\n+}\n+\n+static inline bool dsa_port_offloads_bridge(struct dsa_port *dp,\n+\t\t\t\t\t    struct net_device *bridge_dev)\n+{\n+\t/* DSA ports connected to a bridge, and event was emitted\n+\t * for the bridge.\n+\t */\n+\treturn dp->bridge_dev == bridge_dev;\n+}\n+\n+/* Returns true if any port of this tree offloads the given net_device */\n+static inline bool dsa_tree_offloads_bridge_port(struct dsa_switch_tree *dst,\n+\t\t\t\t\t\t struct net_device *dev)\n+{\n+\tstruct dsa_port *dp;\n+\n+\tlist_for_each_entry(dp, &dst->ports, list)\n+\t\tif (dsa_port_offloads_bridge_port(dp, dev))\n+\t\t\treturn true;\n+\n+\treturn false;\n+}\n+\n+/* Returns true if any port of this tree offloads the given net_device */\n+static inline bool dsa_tree_offloads_netdev(struct dsa_switch_tree *dst,\n+\t\t\t\t\t    struct net_device *dev)\n+{\n+\tstruct dsa_port *dp;\n+\n+\tlist_for_each_entry(dp, &dst->ports, list)\n+\t\tif (dsa_port_offloads_netdev(dp, dev))\n+\t\t\treturn true;\n+\n+\treturn false;\n+}\n+\n /* slave.c */\n extern const struct dsa_device_ops notag_netdev_ops;\n void dsa_slave_mii_bus_init(struct dsa_switch *ds);\n@@ -285,6 +367,9 @@ int dsa_switch_register_notifier(struct\n void dsa_switch_unregister_notifier(struct dsa_switch *ds);\n \n /* dsa2.c */\n+void dsa_lag_map(struct dsa_switch_tree *dst, struct net_device *lag);\n+void dsa_lag_unmap(struct dsa_switch_tree *dst, struct net_device *lag);\n+\n extern struct list_head dsa_tree_list;\n \n #endif\n--- a/net/dsa/port.c\n+++ b/net/dsa/port.c\n@@ -193,6 +193,99 @@ void dsa_port_bridge_leave(struct dsa_po\n \tdsa_port_set_state_now(dp, BR_STATE_FORWARDING);\n }\n \n+int dsa_port_lag_change(struct dsa_port *dp,\n+\t\t\tstruct netdev_lag_lower_state_info *linfo)\n+{\n+\tstruct dsa_notifier_lag_info info = {\n+\t\t.sw_index = dp->ds->index,\n+\t\t.port = dp->index,\n+\t};\n+\tbool tx_enabled;\n+\n+\tif (!dp->lag_dev)\n+\t\treturn 0;\n+\n+\t/* On statically configured aggregates (e.g. loadbalance\n+\t * without LACP) ports will always be tx_enabled, even if the\n+\t * link is down. Thus we require both link_up and tx_enabled\n+\t * in order to include it in the tx set.\n+\t */\n+\ttx_enabled = linfo->link_up && linfo->tx_enabled;\n+\n+\tif (tx_enabled == dp->lag_tx_enabled)\n+\t\treturn 0;\n+\n+\tdp->lag_tx_enabled = tx_enabled;\n+\n+\treturn dsa_port_notify(dp, DSA_NOTIFIER_LAG_CHANGE, &info);\n+}\n+\n+int dsa_port_lag_join(struct dsa_port *dp, struct net_device *lag,\n+\t\t      struct netdev_lag_upper_info *uinfo)\n+{\n+\tstruct dsa_notifier_lag_info info = {\n+\t\t.sw_index = dp->ds->index,\n+\t\t.port = dp->index,\n+\t\t.lag = lag,\n+\t\t.info = uinfo,\n+\t};\n+\tstruct net_device *bridge_dev;\n+\tint err;\n+\n+\tdsa_lag_map(dp->ds->dst, lag);\n+\tdp->lag_dev = lag;\n+\n+\terr = dsa_port_notify(dp, DSA_NOTIFIER_LAG_JOIN, &info);\n+\tif (err)\n+\t\tgoto err_lag_join;\n+\n+\tbridge_dev = netdev_master_upper_dev_get(lag);\n+\tif (!bridge_dev || !netif_is_bridge_master(bridge_dev))\n+\t\treturn 0;\n+\n+\terr = dsa_port_bridge_join(dp, bridge_dev);\n+\tif (err)\n+\t\tgoto err_bridge_join;\n+\n+\treturn 0;\n+\n+err_bridge_join:\n+\tdsa_port_notify(dp, DSA_NOTIFIER_LAG_LEAVE, &info);\n+err_lag_join:\n+\tdp->lag_dev = NULL;\n+\tdsa_lag_unmap(dp->ds->dst, lag);\n+\treturn err;\n+}\n+\n+void dsa_port_lag_leave(struct dsa_port *dp, struct net_device *lag)\n+{\n+\tstruct dsa_notifier_lag_info info = {\n+\t\t.sw_index = dp->ds->index,\n+\t\t.port = dp->index,\n+\t\t.lag = lag,\n+\t};\n+\tint err;\n+\n+\tif (!dp->lag_dev)\n+\t\treturn;\n+\n+\t/* Port might have been part of a LAG that in turn was\n+\t * attached to a bridge.\n+\t */\n+\tif (dp->bridge_dev)\n+\t\tdsa_port_bridge_leave(dp, dp->bridge_dev);\n+\n+\tdp->lag_tx_enabled = false;\n+\tdp->lag_dev = NULL;\n+\n+\terr = dsa_port_notify(dp, DSA_NOTIFIER_LAG_LEAVE, &info);\n+\tif (err)\n+\t\tpr_err(\"DSA: failed to notify DSA_NOTIFIER_LAG_LEAVE: %d\\n\",\n+\t\t       err);\n+\n+\tdsa_lag_unmap(dp->ds->dst, lag);\n+}\n+\n /* Must be called under rcu_read_lock() */\n static bool dsa_port_can_apply_vlan_filtering(struct dsa_port *dp,\n \t\t\t\t\t      bool vlan_filtering)\n--- a/net/dsa/slave.c\n+++ b/net/dsa/slave.c\n@@ -337,9 +337,6 @@ static int dsa_slave_vlan_add(struct net\n \tstruct switchdev_obj_port_vlan vlan;\n \tint vid, err;\n \n-\tif (obj->orig_dev != dev)\n-\t\treturn -EOPNOTSUPP;\n-\n \tif (dsa_port_skip_vlan_configuration(dp))\n \t\treturn 0;\n \n@@ -394,11 +391,13 @@ static int dsa_slave_port_obj_add(struct\n \n \tswitch (obj->id) {\n \tcase SWITCHDEV_OBJ_ID_PORT_MDB:\n-\t\tif (obj->orig_dev != dev)\n+\t\tif (!dsa_port_offloads_bridge_port(dp, obj->orig_dev))\n \t\t\treturn -EOPNOTSUPP;\n \t\terr = dsa_port_mdb_add(dp, SWITCHDEV_OBJ_PORT_MDB(obj), trans);\n \t\tbreak;\n \tcase SWITCHDEV_OBJ_ID_HOST_MDB:\n+\t\tif (!dsa_port_offloads_bridge(dp, obj->orig_dev))\n+\t\t\treturn -EOPNOTSUPP;\n \t\t/* DSA can directly translate this to a normal MDB add,\n \t\t * but on the CPU port.\n \t\t */\n@@ -406,6 +405,9 @@ static int dsa_slave_port_obj_add(struct\n \t\t\t\t       trans);\n \t\tbreak;\n \tcase SWITCHDEV_OBJ_ID_PORT_VLAN:\n+\t\tif (!dsa_port_offloads_bridge_port(dp, obj->orig_dev))\n+\t\t\treturn -EOPNOTSUPP;\n+\n \t\terr = dsa_slave_vlan_add(dev, obj, trans);\n \t\tbreak;\n \tdefault:\n@@ -424,9 +426,6 @@ static int dsa_slave_vlan_del(struct net\n \tstruct switchdev_obj_port_vlan *vlan;\n \tint vid, err;\n \n-\tif (obj->orig_dev != dev)\n-\t\treturn -EOPNOTSUPP;\n-\n \tif (dsa_port_skip_vlan_configuration(dp))\n \t\treturn 0;\n \n@@ -453,17 +452,22 @@ static int dsa_slave_port_obj_del(struct\n \n \tswitch (obj->id) {\n \tcase SWITCHDEV_OBJ_ID_PORT_MDB:\n-\t\tif (obj->orig_dev != dev)\n+\t\tif (!dsa_port_offloads_bridge_port(dp, obj->orig_dev))\n \t\t\treturn -EOPNOTSUPP;\n \t\terr = dsa_port_mdb_del(dp, SWITCHDEV_OBJ_PORT_MDB(obj));\n \t\tbreak;\n \tcase SWITCHDEV_OBJ_ID_HOST_MDB:\n+\t\tif (!dsa_port_offloads_bridge(dp, obj->orig_dev))\n+\t\t\treturn -EOPNOTSUPP;\n \t\t/* DSA can directly translate this to a normal MDB add,\n \t\t * but on the CPU port.\n \t\t */\n \t\terr = dsa_port_mdb_del(dp->cpu_dp, SWITCHDEV_OBJ_PORT_MDB(obj));\n \t\tbreak;\n \tcase SWITCHDEV_OBJ_ID_PORT_VLAN:\n+\t\tif (!dsa_port_offloads_bridge_port(dp, obj->orig_dev))\n+\t\t\treturn -EOPNOTSUPP;\n+\n \t\terr = dsa_slave_vlan_del(dev, obj);\n \t\tbreak;\n \tdefault:\n@@ -1993,6 +1997,46 @@ static int dsa_slave_changeupper(struct\n \t\t\tdsa_port_bridge_leave(dp, info->upper_dev);\n \t\t\terr = NOTIFY_OK;\n \t\t}\n+\t} else if (netif_is_lag_master(info->upper_dev)) {\n+\t\tif (info->linking) {\n+\t\t\terr = dsa_port_lag_join(dp, info->upper_dev,\n+\t\t\t\t\t\tinfo->upper_info);\n+\t\t\tif (err == -EOPNOTSUPP) {\n+\t\t\t\tNL_SET_ERR_MSG_MOD(info->info.extack,\n+\t\t\t\t\t\t   \"Offloading not supported\");\n+\t\t\t\terr = 0;\n+\t\t\t}\n+\t\t\terr = notifier_from_errno(err);\n+\t\t} else {\n+\t\t\tdsa_port_lag_leave(dp, info->upper_dev);\n+\t\t\terr = NOTIFY_OK;\n+\t\t}\n+\t}\n+\n+\treturn err;\n+}\n+\n+static int\n+dsa_slave_lag_changeupper(struct net_device *dev,\n+\t\t\t  struct netdev_notifier_changeupper_info *info)\n+{\n+\tstruct net_device *lower;\n+\tstruct list_head *iter;\n+\tint err = NOTIFY_DONE;\n+\tstruct dsa_port *dp;\n+\n+\tnetdev_for_each_lower_dev(dev, lower, iter) {\n+\t\tif (!dsa_slave_dev_check(lower))\n+\t\t\tcontinue;\n+\n+\t\tdp = dsa_slave_to_port(lower);\n+\t\tif (!dp->lag_dev)\n+\t\t\t/* Software LAG */\n+\t\t\tcontinue;\n+\n+\t\terr = dsa_slave_changeupper(lower, info);\n+\t\tif (notifier_to_errno(err))\n+\t\t\tbreak;\n \t}\n \n \treturn err;\n@@ -2078,10 +2122,26 @@ static int dsa_slave_netdevice_event(str\n \t\tbreak;\n \t}\n \tcase NETDEV_CHANGEUPPER:\n+\t\tif (dsa_slave_dev_check(dev))\n+\t\t\treturn dsa_slave_changeupper(dev, ptr);\n+\n+\t\tif (netif_is_lag_master(dev))\n+\t\t\treturn dsa_slave_lag_changeupper(dev, ptr);\n+\n+\t\tbreak;\n+\tcase NETDEV_CHANGELOWERSTATE: {\n+\t\tstruct netdev_notifier_changelowerstate_info *info = ptr;\n+\t\tstruct dsa_port *dp;\n+\t\tint err;\n+\n \t\tif (!dsa_slave_dev_check(dev))\n-\t\t\treturn NOTIFY_DONE;\n+\t\t\tbreak;\n \n-\t\treturn dsa_slave_changeupper(dev, ptr);\n+\t\tdp = dsa_slave_to_port(dev);\n+\n+\t\terr = dsa_port_lag_change(dp, info->lower_state_info);\n+\t\treturn notifier_from_errno(err);\n+\t}\n \t}\n \n \treturn NOTIFY_DONE;\n@@ -2229,6 +2289,15 @@ static int dsa_slave_switchdev_event(str\n \t\t\tif (!fdb_info->added_by_user &&\n \t\t\t    !dp->ds->assisted_learning_on_cpu_port)\n \t\t\t\treturn NOTIFY_DONE;\n+\n+\t\t\t/* When the bridge learns an address on an offloaded\n+\t\t\t * LAG we don't want to send traffic to the CPU, the\n+\t\t\t * other ports bridged with the LAG should be able to\n+\t\t\t * autonomously forward towards it.\n+\t\t\t */\n+\t\t\tif (dsa_tree_offloads_netdev(dp->ds->dst, dev))\n+\t\t\t\treturn NOTIFY_DONE;\n+\n \t\t}\n \n \t\tif (!dp->ds->ops->port_fdb_add || !dp->ds->ops->port_fdb_del)\n--- a/net/dsa/switch.c\n+++ b/net/dsa/switch.c\n@@ -193,6 +193,47 @@ static int dsa_switch_fdb_del(struct dsa\n \treturn ds->ops->port_fdb_del(ds, port, info->addr, info->vid);\n }\n \n+static int dsa_switch_lag_change(struct dsa_switch *ds,\n+\t\t\t\t struct dsa_notifier_lag_info *info)\n+{\n+\tif (ds->index == info->sw_index && ds->ops->port_lag_change)\n+\t\treturn ds->ops->port_lag_change(ds, info->port);\n+\n+\tif (ds->index != info->sw_index && ds->ops->crosschip_lag_change)\n+\t\treturn ds->ops->crosschip_lag_change(ds, info->sw_index,\n+\t\t\t\t\t\t     info->port);\n+\n+\treturn 0;\n+}\n+\n+static int dsa_switch_lag_join(struct dsa_switch *ds,\n+\t\t\t       struct dsa_notifier_lag_info *info)\n+{\n+\tif (ds->index == info->sw_index && ds->ops->port_lag_join)\n+\t\treturn ds->ops->port_lag_join(ds, info->port, info->lag,\n+\t\t\t\t\t      info->info);\n+\n+\tif (ds->index != info->sw_index && ds->ops->crosschip_lag_join)\n+\t\treturn ds->ops->crosschip_lag_join(ds, info->sw_index,\n+\t\t\t\t\t\t   info->port, info->lag,\n+\t\t\t\t\t\t   info->info);\n+\n+\treturn -EOPNOTSUPP;\n+}\n+\n+static int dsa_switch_lag_leave(struct dsa_switch *ds,\n+\t\t\t\tstruct dsa_notifier_lag_info *info)\n+{\n+\tif (ds->index == info->sw_index && ds->ops->port_lag_leave)\n+\t\treturn ds->ops->port_lag_leave(ds, info->port, info->lag);\n+\n+\tif (ds->index != info->sw_index && ds->ops->crosschip_lag_leave)\n+\t\treturn ds->ops->crosschip_lag_leave(ds, info->sw_index,\n+\t\t\t\t\t\t    info->port, info->lag);\n+\n+\treturn -EOPNOTSUPP;\n+}\n+\n static bool dsa_switch_mdb_match(struct dsa_switch *ds, int port,\n \t\t\t\t struct dsa_notifier_mdb_info *info)\n {\n@@ -340,6 +381,15 @@ static int dsa_switch_event(struct notif\n \tcase DSA_NOTIFIER_FDB_DEL:\n \t\terr = dsa_switch_fdb_del(ds, info);\n \t\tbreak;\n+\tcase DSA_NOTIFIER_LAG_CHANGE:\n+\t\terr = dsa_switch_lag_change(ds, info);\n+\t\tbreak;\n+\tcase DSA_NOTIFIER_LAG_JOIN:\n+\t\terr = dsa_switch_lag_join(ds, info);\n+\t\tbreak;\n+\tcase DSA_NOTIFIER_LAG_LEAVE:\n+\t\terr = dsa_switch_lag_leave(ds, info);\n+\t\tbreak;\n \tcase DSA_NOTIFIER_MDB_ADD:\n \t\terr = dsa_switch_mdb_add(ds, info);\n \t\tbreak;\n--- a/net/dsa/tag_dsa.c\n+++ b/net/dsa/tag_dsa.c\n@@ -82,7 +82,19 @@ static struct sk_buff *dsa_rcv(struct sk\n \tsource_device = dsa_header[0] & 0x1f;\n \tsource_port = (dsa_header[1] >> 3) & 0x1f;\n \n-\tskb->dev = dsa_master_find_slave(dev, source_device, source_port);\n+\tif (trunk) {\n+\t\tstruct dsa_port *cpu_dp = dev->dsa_ptr;\n+\n+\t\t/* The exact source port is not available in the tag,\n+\t\t * so we inject the frame directly on the upper\n+\t\t * team/bond.\n+\t\t */\n+\t\tskb->dev = dsa_lag_dev(cpu_dp->dst, source_port);\n+\t} else {\n+\t\tskb->dev = dsa_master_find_slave(dev, source_device,\n+\t\t\t\t\t\t source_port);\n+\t}\n+\n \tif (!skb->dev)\n \t\treturn NULL;\n \n"
  },
  {
    "path": "target/linux/realtek/patches-5.10/710-net-phy-sfp-re-probe-modules-on-DEV_UP-event.patch",
    "content": "From a381ac0aa281fdb0b41a39d8a2bc08fd88f6db92 Mon Sep 17 00:00:00 2001\nFrom: Antoine Tenart <antoine.tenart@bootlin.com>\nDate: Tue, 25 Feb 2020 16:32:37 +0100\nSubject: [PATCH 1/3] net: phy: sfp: re-probe modules on DEV_UP event\n\nSigned-off-by: Antoine Tenart <antoine.tenart@bootlin.com>\n---\n drivers/net/phy/sfp.c | 7 +++++++\n 1 file changed, 7 insertions(+)\n\n--- a/drivers/net/phy/sfp.c\n+++ b/drivers/net/phy/sfp.c\n@@ -1959,6 +1959,13 @@ static void sfp_sm_module(struct sfp *sf\n \t\treturn;\n \t}\n \n+\t/* Re-probe the SFP modules when an interface is brought up, as the MAC\n+\t * do not report its link status (This means Phylink wouldn't be\n+\t * triggered if the PHY had a link before a MAC is brought up).\n+\t */\n+\tif (event == SFP_E_DEV_UP && sfp->sm_mod_state == SFP_MOD_PRESENT)\n+\t\tsfp_sm_mod_next(sfp, SFP_MOD_PROBE, T_SERIAL);\n+\n \tswitch (sfp->sm_mod_state) {\n \tdefault:\n \t\tif (event == SFP_E_INSERT) {\n"
  },
  {
    "path": "target/linux/realtek/patches-5.10/711-net-phy-add-an-MDIO-SMBus-library.patch",
    "content": "From d585c55b9f70cf9e8c66820d7efe7130c683f19e Mon Sep 17 00:00:00 2001\nFrom: Antoine Tenart <antoine.tenart@bootlin.com>\nDate: Fri, 21 Feb 2020 11:51:27 +0100\nSubject: [PATCH 2/3] net: phy: add an MDIO SMBus library\n\nSigned-off-by: Antoine Tenart <antoine.tenart@bootlin.com>\n---\n drivers/net/mdio/Kconfig      | 11 +++++++\n drivers/net/mdio/Makefile     |  1 +\n drivers/net/mdio/mdio-smbus.c | 62 +++++++++++++++++++++++++++++++++++\n drivers/net/phy/Kconfig       |  1 +\n include/linux/mdio/mdio-i2c.h | 16 +++++++++\n 5 files changed, 91 insertions(+)\n create mode 100644 drivers/net/mdio/mdio-smbus.c\n\n--- a/drivers/net/mdio/Kconfig\n+++ b/drivers/net/mdio/Kconfig\n@@ -40,6 +40,17 @@ config MDIO_SUN4I\n \t  interface units of the Allwinner SoC that have an EMAC (A10,\n \t  A12, A10s, etc.)\n \n+config MDIO_SMBUS\n+\ttristate\n+\tdepends on I2C_SMBUS\n+\thelp\n+\t  Support SMBus based PHYs. This provides a MDIO bus bridged\n+\t  to SMBus to allow PHYs connected in SMBus mode to be accessed\n+\t  using the existing infrastructure.\n+\n+\t  This is library mode.\n+\n+\n config MDIO_XGENE\n \ttristate \"APM X-Gene SoC MDIO bus controller\"\n \tdepends on ARCH_XGENE || COMPILE_TEST\n--- a/drivers/net/mdio/Makefile\n+++ b/drivers/net/mdio/Makefile\n@@ -17,6 +17,7 @@ obj-$(CONFIG_MDIO_MOXART)\t\t+= mdio-moxar\n obj-$(CONFIG_MDIO_MSCC_MIIM)\t\t+= mdio-mscc-miim.o\n obj-$(CONFIG_MDIO_MVUSB)\t\t+= mdio-mvusb.o\n obj-$(CONFIG_MDIO_OCTEON)\t\t+= mdio-octeon.o\n+obj-$(CONFIG_MDIO_SMBUS)\t\t+= mdio-smbus.o\n obj-$(CONFIG_MDIO_SUN4I)\t\t+= mdio-sun4i.o\n obj-$(CONFIG_MDIO_THUNDER)\t\t+= mdio-thunder.o\n obj-$(CONFIG_MDIO_XGENE)\t\t+= mdio-xgene.o\n--- /dev/null\n+++ b/drivers/net/mdio/mdio-smbus.c\n@@ -0,0 +1,62 @@\n+// SPDX-License-Identifier: GPL-2.0-or-later\n+/*\n+ * MDIO SMBus bridge\n+ *\n+ * Copyright (C) 2020 Antoine Tenart\n+ *\n+ * Network PHYs can appear on SMBus when they are part of SFP modules.\n+ */\n+#include <linux/i2c.h>\n+#include <linux/phy.h>\n+#include <linux/mdio/mdio-i2c.h>\n+\n+static int smbus_mii_read(struct mii_bus *mii, int phy_id, int reg)\n+{\n+\tstruct i2c_adapter *i2c = mii->priv;\n+\tunion i2c_smbus_data data;\n+\tint ret;\n+\n+\tret = i2c_smbus_xfer(i2c, i2c_mii_phy_addr(phy_id), 0, I2C_SMBUS_READ,\n+\t\t\t     reg, I2C_SMBUS_BYTE_DATA, &data);\n+\tif (ret < 0)\n+\t\treturn 0xff;\n+\n+\treturn data.byte;\n+}\n+\n+static int smbus_mii_write(struct mii_bus *mii, int phy_id, int reg, u16 val)\n+{\n+\tstruct i2c_adapter *i2c = mii->priv;\n+\tunion i2c_smbus_data data;\n+\tint ret;\n+\n+\tdata.byte = val;\n+\n+\tret = i2c_smbus_xfer(i2c, i2c_mii_phy_addr(phy_id), 0, I2C_SMBUS_WRITE,\n+\t\t\t     reg, I2C_SMBUS_BYTE_DATA, &data);\n+\treturn ret < 0 ? ret : 0;\n+}\n+\n+struct mii_bus *mdio_smbus_alloc(struct device *parent, struct i2c_adapter *i2c)\n+{\n+\tstruct mii_bus *mii;\n+\n+\tif (!i2c_check_functionality(i2c, I2C_FUNC_SMBUS_BYTE_DATA))\n+\t\treturn ERR_PTR(-EINVAL);\n+\n+\tmii = mdiobus_alloc();\n+\tif (!mii)\n+\t\treturn ERR_PTR(-ENOMEM);\n+\n+\tsnprintf(mii->id, MII_BUS_ID_SIZE, \"smbus:%s\", dev_name(parent));\n+\tmii->parent = parent;\n+\tmii->read = smbus_mii_read;\n+\tmii->write = smbus_mii_write;\n+\tmii->priv = i2c;\n+\n+\treturn mii;\n+}\n+\n+MODULE_AUTHOR(\"Antoine Tenart\");\n+MODULE_DESCRIPTION(\"MDIO SMBus bridge library\");\n+MODULE_LICENSE(\"GPL\");\n--- a/drivers/net/phy/Kconfig\n+++ b/drivers/net/phy/Kconfig\n@@ -60,6 +60,7 @@ config SFP\n \tdepends on I2C && PHYLINK\n \tdepends on HWMON || HWMON=n\n \tselect MDIO_I2C\n+\tselect MDIO_SMBUS\n \n comment \"Switch configuration API + drivers\"\n \n--- a/include/linux/mdio/mdio-i2c.h\n+++ b/include/linux/mdio/mdio-i2c.h\n@@ -12,5 +12,21 @@ struct i2c_adapter;\n struct mii_bus;\n \n struct mii_bus *mdio_i2c_alloc(struct device *parent, struct i2c_adapter *i2c);\n+struct mii_bus *mdio_smbus_alloc(struct device *parent, struct i2c_adapter *i2c);\n+\n+/*\n+ * I2C bus addresses 0x50 and 0x51 are normally an EEPROM, which is\n+ * specified to be present in SFP modules.  These correspond with PHY\n+ * addresses 16 and 17.  Disallow access to these \"phy\" addresses.\n+ */\n+static bool i2c_mii_valid_phy_id(int phy_id)\n+{\n+\treturn phy_id != 0x10 && phy_id != 0x11;\n+}\n+\n+static unsigned int i2c_mii_phy_addr(int phy_id)\n+{\n+\treturn phy_id + 0x40;\n+}\n \n #endif\n--- a/drivers/net/mdio/mdio-i2c.c\n+++ b/drivers/net/mdio/mdio-i2c.c\n@@ -13,21 +13,6 @@\n #include <linux/mdio/mdio-i2c.h>\n #include <linux/phy.h>\n \n-/*\n- * I2C bus addresses 0x50 and 0x51 are normally an EEPROM, which is\n- * specified to be present in SFP modules.  These correspond with PHY\n- * addresses 16 and 17.  Disallow access to these \"phy\" addresses.\n- */\n-static bool i2c_mii_valid_phy_id(int phy_id)\n-{\n-\treturn phy_id != 0x10 && phy_id != 0x11;\n-}\n-\n-static unsigned int i2c_mii_phy_addr(int phy_id)\n-{\n-\treturn phy_id + 0x40;\n-}\n-\n static int i2c_mii_read(struct mii_bus *bus, int phy_id, int reg)\n {\n \tstruct i2c_adapter *i2c = bus->priv;\n"
  },
  {
    "path": "target/linux/realtek/patches-5.10/712-net-phy-sfp-add-support-for-SMBus.patch",
    "content": "From 3cb0bde365d913c484d20224367a54a0eac780a7 Mon Sep 17 00:00:00 2001\nFrom: Antoine Tenart <antoine.tenart@bootlin.com>\nDate: Fri, 21 Feb 2020 11:55:29 +0100\nSubject: [PATCH 3/3] net: phy: sfp: add support for SMBus\n\nSigned-off-by: Antoine Tenart <antoine.tenart@bootlin.com>\n---\n drivers/net/phy/sfp.c | 68 ++++++++++++++++++++++++++++++++++---------\n 1 file changed, 54 insertions(+), 14 deletions(-)\n\n--- a/drivers/net/phy/sfp.c\n+++ b/drivers/net/phy/sfp.c\n@@ -412,32 +412,72 @@ static int sfp_i2c_write(struct sfp *sfp\n \treturn ret == ARRAY_SIZE(msgs) ? len : 0;\n }\n \n+static int sfp_smbus_read(struct sfp *sfp, bool a2, u8 dev_addr, void *buf,\n+\t\t\t  size_t len)\n+{\n+\tu8 bus_addr = a2 ? 0x51 : 0x50, *val = buf;\n+\n+\tbus_addr -= 0x40;\n+\n+\twhile (len > 0) {\n+\t\t*val = sfp->i2c_mii->read(sfp->i2c_mii, bus_addr, dev_addr);\n+\n+\t\tval++;\n+\t\tdev_addr++;\n+\t\tlen--;\n+\t}\n+\n+\treturn val - (u8 *)buf;\n+}\n+\n+static int sfp_smbus_write(struct sfp *sfp, bool a2, u8 dev_addr, void *buf,\n+\t\t\t   size_t len)\n+{\n+\tu8 bus_addr = a2 ? 0x51 : 0x50;\n+\tu16 val;\n+\n+\tmemcpy(&val, buf, len);\n+\n+\treturn sfp->i2c_mii->write(sfp->i2c_mii, bus_addr, dev_addr, val);\n+}\n+\n static int sfp_i2c_configure(struct sfp *sfp, struct i2c_adapter *i2c)\n {\n-\tstruct mii_bus *i2c_mii;\n+\tstruct mii_bus *mii;\n \tint ret;\n \n-\tif (!i2c_check_functionality(i2c, I2C_FUNC_I2C))\n-\t\treturn -EINVAL;\n-\n \tsfp->i2c = i2c;\n-\tsfp->read = sfp_i2c_read;\n-\tsfp->write = sfp_i2c_write;\n \n-\ti2c_mii = mdio_i2c_alloc(sfp->dev, i2c);\n-\tif (IS_ERR(i2c_mii))\n-\t\treturn PTR_ERR(i2c_mii);\n+\tif (i2c_check_functionality(i2c, I2C_FUNC_I2C)) {\n+\t\tsfp->read = sfp_i2c_read;\n+\t\tsfp->write = sfp_i2c_write;\n+\n+\t\tmii = mdio_i2c_alloc(sfp->dev, i2c);\n+\t\tif (IS_ERR(mii))\n+\t\t\treturn PTR_ERR(mii);\n+\n+\t\tmii->name = \"SFP I2C Bus\";\n+\t} else if (i2c_check_functionality(i2c, I2C_FUNC_SMBUS_BYTE_DATA)) {\n+\t\tsfp->read = sfp_smbus_read;\n+\t\tsfp->write = sfp_smbus_write;\n+\n+\t\tmii = mdio_smbus_alloc(sfp->dev, i2c);\n+\t\tif (IS_ERR(mii))\n+\t\t\treturn PTR_ERR(mii);\n \n-\ti2c_mii->name = \"SFP I2C Bus\";\n-\ti2c_mii->phy_mask = ~0;\n+\t\tmii->name = \"SFP SMBus\";\n+\t} else {\n+\t\treturn -EINVAL;\n+\t}\n \n-\tret = mdiobus_register(i2c_mii);\n+\tmii->phy_mask = ~0;\n+\tret = mdiobus_register(mii);\n \tif (ret < 0) {\n-\t\tmdiobus_free(i2c_mii);\n+\t\tmdiobus_free(mii);\n \t\treturn ret;\n \t}\n \n-\tsfp->i2c_mii = i2c_mii;\n+\tsfp->i2c_mii = mii;\n \n \treturn 0;\n }\n"
  },
  {
    "path": "target/linux/realtek/patches-5.10/713-v5.12-net-dsa-configure-better-brport-flags-when-ports-lea.patch",
    "content": "From: Vladimir Oltean <vladimir.oltean@nxp.com>\nDate: Fri, 12 Feb 2021 17:15:54 +0200\nSubject: [PATCH] net: dsa: configure better brport flags when ports leave the\n bridge\n\nBugfixed version of upstream commit 5e38c15856e9 (\"net: dsa: configure\nbetter brport flags when ports leave the bridge\")\n\nFor a DSA switch port operating in standalone mode, address learning\ndoesn't make much sense since that is a bridge function. In fact,\naddress learning even breaks setups such as this one:\n\n   +---------------------------------------------+\n   |                                             |\n   | +-------------------+                       |\n   | |        br0        |    send      receive  |\n   | +--------+-+--------+ +--------+ +--------+ |\n   | |        | |        | |        | |        | |\n   | |  swp0  | |  swp1  | |  swp2  | |  swp3  | |\n   | |        | |        | |        | |        | |\n   +-+--------+-+--------+-+--------+-+--------+-+\n          |         ^           |          ^\n          |         |           |          |\n          |         +-----------+          |\n          |                                |\n          +--------------------------------+\n\nbecause if the switch has a single FDB (can offload a single bridge)\nthen source address learning on swp3 can \"steal\" the source MAC address\nof swp2 from br0's FDB, because learning frames coming from swp2 will be\ndone twice: first on the swp1 ingress port, second on the swp3 ingress\nport. So the hardware FDB will become out of sync with the software\nbridge, and when swp2 tries to send one more packet towards swp1, the\nASIC will attempt to short-circuit the forwarding path and send it\ndirectly to swp3 (since that's the last port it learned that address on),\nwhich it obviously can't, because swp3 operates in standalone mode.\n\nSo DSA drivers operating in standalone mode should still configure a\nlist of bridge port flags even when they are standalone. Currently DSA\nattempts to call dsa_port_bridge_flags with 0, which disables egress\nflooding of unknown unicast and multicast, something which doesn't make\nmuch sense. For the switches that implement .port_egress_floods - b53\nand mv88e6xxx, it probably doesn't matter too much either, since they\ncan possibly inject traffic from the CPU into a standalone port,\nregardless of MAC DA, even if egress flooding is turned off for that\nport, but certainly not all DSA switches can do that - sja1105, for\nexample, can't. So it makes sense to use a better common default there,\nsuch as \"flood everything\".\n\nIt should also be noted that what DSA calls \"dsa_port_bridge_flags()\"\nis a degenerate name for just calling .port_egress_floods(), since\nnothing else is implemented - not learning, in particular. But disabling\naddress learning, something that this driver is also coding up for, will\nbe supported by individual drivers once .port_egress_floods is replaced\nwith a more generic .port_bridge_flags.\n\nPrevious attempts to code up this logic have been in the common bridge\nlayer, but as pointed out by Ido Schimmel, there are corner cases that\nare missed when doing that:\nhttps://patchwork.kernel.org/project/netdevbpf/patch/20210209151936.97382-5-olteanv@gmail.com/\n\nSo, at least for now, let's leave DSA in charge of setting port flags\nbefore and after the bridge join and leave.\n\nSigned-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>\nReviewed-by: Florian Fainelli <f.fainelli@gmail.com>\nSigned-off-by: David S. Miller <davem@davemloft.net>\n[ backport and bugfix: break dsa_port_bridge_flags() out of loop ]\nSigned-off-by: Bjørn Mork <bjorn@mork.no>\n---\n net/dsa/port.c | 45 ++++++++++++++++++++++++++++++++++++++-------\n 1 file changed, 38 insertions(+), 7 deletions(-)\n\n--- a/net/dsa/port.c\n+++ b/net/dsa/port.c\n@@ -134,6 +134,27 @@ void dsa_port_disable(struct dsa_port *d\n \trtnl_unlock();\n }\n \n+static void dsa_port_change_brport_flags(struct dsa_port *dp,\n+\t\t\t\t\t bool bridge_offload)\n+{\n+\tunsigned long mask, flags;\n+\tint flag, err;\n+\n+\tmask = BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD | BR_BCAST_FLOOD;\n+\tif (bridge_offload)\n+\t\tflags = mask;\n+\telse\n+\t\tflags = mask & ~BR_LEARNING;\n+\n+\tfor_each_set_bit(flag, &mask, 32) {\n+\t\terr = dsa_port_pre_bridge_flags(dp, BIT(flag), NULL, NULL);\n+\t\tif (err)\n+\t\t\tflags &= ~BIT(flag);\n+\t}\n+\n+\tdsa_port_bridge_flags(dp, flags, NULL, NULL);\n+}\n+\n int dsa_port_bridge_join(struct dsa_port *dp, struct net_device *br)\n {\n \tstruct dsa_notifier_bridge_info info = {\n@@ -144,10 +165,10 @@ int dsa_port_bridge_join(struct dsa_port\n \t};\n \tint err;\n \n-\t/* Set the flooding mode before joining the port in the switch */\n-\terr = dsa_port_bridge_flags(dp, BR_FLOOD | BR_MCAST_FLOOD, NULL, NULL);\n-\tif (err)\n-\t\treturn err;\n+\t/* Notify the port driver to set its configurable flags in a way that\n+\t * matches the initial settings of a bridge port.\n+\t */\n+\tdsa_port_change_brport_flags(dp, true);\n \n \t/* Here the interface is already bridged. Reflect the current\n \t * configuration so that drivers can program their chips accordingly.\n@@ -158,7 +179,7 @@ int dsa_port_bridge_join(struct dsa_port\n \n \t/* The bridging is rolled back on error */\n \tif (err) {\n-\t\tdsa_port_bridge_flags(dp, 0, NULL, NULL);\n+\t\tdsa_port_change_brport_flags(dp, false);\n \t\tdp->bridge_dev = NULL;\n \t}\n \n@@ -184,8 +205,18 @@ void dsa_port_bridge_leave(struct dsa_po\n \tif (err)\n \t\tpr_err(\"DSA: failed to notify DSA_NOTIFIER_BRIDGE_LEAVE\\n\");\n \n-\t/* Port is leaving the bridge, disable flooding */\n-\tdsa_port_bridge_flags(dp, 0, NULL, NULL);\n+\t/* Configure the port for standalone mode (no address learning,\n+\t * flood everything).\n+\t * The bridge only emits SWITCHDEV_ATTR_ID_PORT_BRIDGE_FLAGS events\n+\t * when the user requests it through netlink or sysfs, but not\n+\t * automatically at port join or leave, so we need to handle resetting\n+\t * the brport flags ourselves. But we even prefer it that way, because\n+\t * otherwise, some setups might never get the notification they need,\n+\t * for example, when a port leaves a LAG that offloads the bridge,\n+\t * it becomes standalone, but as far as the bridge is concerned, no\n+\t * port ever left.\n+\t */\n+\tdsa_port_change_brport_flags(dp, false);\n \n \t/* Port left the bridge, put in BR_STATE_DISABLED by the bridge layer,\n \t * so allow it to be in BR_STATE_FORWARDING to be kept functional\n"
  },
  {
    "path": "target/linux/realtek/patches-5.10/800-net-mdio-support-hardware-assisted-indirect-access.patch",
    "content": "From 5d84f16b0036b33487b94abef15ad3c224c81ee9 Mon Sep 17 00:00:00 2001\nFrom: Daniel Golle <daniel@makrotopia.org>\nDate: Thu, 3 Feb 2022 16:38:50 +0000\nSubject: [PATCH] net: mdio: support hardware-assisted indirect access\n\nMDIO controllers found in Switch-SoCs can offload some MDIO operations\nto the hardware:\n * MMD register access via Clause-22\n   Instead of using multiple operations to access MMD registers via\n   MII register MII_MMD_CTRL and MII_MMD_DATA some controllers\n   allow transparent access to MMD PHY registers.\n\n * paged MII register access\n   Some PHYs (namely RealTek and Vitesse) use vendor-defined MII\n   register 0x1f for paged access. Some MDIO host controllers support\n   transparent paged access when used with such PHYs.\n\n * add convenience accessors to fully support paged access also on\n   multi-PHY packages (like the embedded PHYs in RTL83xx):\n   phy_package_read_paged and phy_package_write_paged\n   phy_package_port_read and phy_package_port_write\n   phy_package_port_read_paged and phy_package_port_write_paged\n\nSigned-off-by: Daniel Golle <daniel@makrotopia.org>\n---\n drivers/net/phy/mdio_bus.c | 335 ++++++++++++++++++++++++++++++++++++-\n drivers/net/phy/phy-core.c |  66 +++++++-\n include/linux/mdio.h       |  59 +++++++\n include/linux/phy.h        | 129 ++++++++++++++\n include/uapi/linux/mii.h   |   1 +\n 5 files changed, 580 insertions(+), 10 deletions(-)\n\n--- a/drivers/net/phy/mdio_bus.c\n+++ b/drivers/net/phy/mdio_bus.c\n@@ -734,6 +734,32 @@ out:\n }\n \n /**\n+ * __mdiobus_select_page - Unlocked version of the mdiobus_select_page function\n+ * @bus: the mii_bus struct\n+ * @addr: the phy address\n+ * @page: register page to select\n+ *\n+ * Selects a MDIO bus register page. Caller must hold the mdio bus lock.\n+ *\n+ * NOTE: MUST NOT be called from interrupt context.\n+ */\n+int __mdiobus_select_page(struct mii_bus *bus, int addr, u16 page)\n+{\n+\tlockdep_assert_held_once(&bus->mdio_lock);\n+\n+\tif (bus->selected_page[addr] == page)\n+\t\treturn 0;\n+\n+\tbus->selected_page[addr] = page;\n+\tif (bus->read_paged)\n+\t\treturn 0;\n+\n+\treturn bus->write(bus, addr, MII_MAINPAGE, page);\n+\n+}\n+EXPORT_SYMBOL(__mdiobus_select_page);\n+\n+/**\n  * __mdiobus_read - Unlocked version of the mdiobus_read function\n  * @bus: the mii_bus struct\n  * @addr: the phy address\n@@ -749,7 +775,10 @@ int __mdiobus_read(struct mii_bus *bus,\n \n \tWARN_ON_ONCE(!mutex_is_locked(&bus->mdio_lock));\n \n-\tretval = bus->read(bus, addr, regnum);\n+\tif (bus->read_paged)\n+\t\tretval = bus->read_paged(bus, addr, bus->selected_page[addr], regnum);\n+\telse\n+\t\tretval = bus->read(bus, addr, regnum);\n \n \ttrace_mdio_access(bus, 1, addr, regnum, retval, retval);\n \tmdiobus_stats_acct(&bus->stats[addr], true, retval);\n@@ -759,6 +788,40 @@ int __mdiobus_read(struct mii_bus *bus,\n EXPORT_SYMBOL(__mdiobus_read);\n \n /**\n+ * __mdiobus_read_paged - Unlocked version of the mdiobus_read_paged function\n+ * @bus: the mii_bus struct\n+ * @addr: the phy address\n+ * @page: the register page to access\n+ * @regnum: register number to read\n+ *\n+ * Read a MDIO bus register. Caller must hold the mdio bus lock.\n+ *\n+ * NOTE: MUST NOT be called from interrupt context.\n+ */\n+int __mdiobus_read_paged(struct mii_bus *bus, int addr, u16 page, u32 regnum)\n+{\n+\tint retval;\n+\tint oldpage;\n+\n+\tlockdep_assert_held_once(&bus->mdio_lock);\n+\n+\tif (bus->read_paged) {\n+\t\tretval = bus->read_paged(bus, addr, page, regnum);\n+\t} else {\n+\t\toldpage = bus->selected_page[addr];\n+\t\t__mdiobus_select_page(bus, addr, page);\n+\t\tretval = bus->read(bus, addr, regnum);\n+\t\t__mdiobus_select_page(bus, addr, oldpage);\n+\t}\n+\n+\ttrace_mdio_access(bus, 1, addr, regnum, retval, retval);\n+\tmdiobus_stats_acct(&bus->stats[addr], true, retval);\n+\n+\treturn retval;\n+}\n+EXPORT_SYMBOL(__mdiobus_read_paged);\n+\n+/**\n  * __mdiobus_write - Unlocked version of the mdiobus_write function\n  * @bus: the mii_bus struct\n  * @addr: the phy address\n@@ -775,7 +838,10 @@ int __mdiobus_write(struct mii_bus *bus,\n \n \tWARN_ON_ONCE(!mutex_is_locked(&bus->mdio_lock));\n \n-\terr = bus->write(bus, addr, regnum, val);\n+\tif (bus->write_paged)\n+\t\terr = bus->write_paged(bus, addr, bus->selected_page[addr], regnum, val);\n+\telse\n+\t\terr = bus->write(bus, addr, regnum, val);\n \n \ttrace_mdio_access(bus, 0, addr, regnum, val, err);\n \tmdiobus_stats_acct(&bus->stats[addr], false, err);\n@@ -785,6 +851,39 @@ int __mdiobus_write(struct mii_bus *bus,\n EXPORT_SYMBOL(__mdiobus_write);\n \n /**\n+ * __mdiobus_write_paged - Unlocked version of the mdiobus_write_paged function\n+ * @bus: the mii_bus struct\n+ * @addr: the phy address\n+ * @page: the register page to access\n+ * @regnum: register number to write\n+ * @val: value to write to @regnum\n+ *\n+ * Write a MDIO bus register. Caller must hold the mdio bus lock.\n+ *\n+ * NOTE: MUST NOT be called from interrupt context.\n+ */\n+int __mdiobus_write_paged(struct mii_bus *bus, int addr, u16 page, u32 regnum, u16 val)\n+{\n+\tint err, oldpage;\n+\n+\tlockdep_assert_held_once(&bus->mdio_lock);\n+\n+\tif (bus->write_paged) {\n+\t\terr = bus->write_paged(bus, addr, page, regnum, val);\n+\t} else {\n+\t\toldpage = bus->selected_page[addr];\n+\t\t__mdiobus_select_page(bus, addr, page);\n+\t\terr = bus->write(bus, addr, regnum, val);\n+\t\t__mdiobus_select_page(bus, addr, oldpage);\n+\t}\n+\ttrace_mdio_access(bus, 0, addr, regnum, val, err);\n+\tmdiobus_stats_acct(&bus->stats[addr], false, err);\n+\treturn err;\n+}\n+EXPORT_SYMBOL(__mdiobus_write_paged);\n+\n+\n+/**\n  * __mdiobus_modify_changed - Unlocked version of the mdiobus_modify function\n  * @bus: the mii_bus struct\n  * @addr: the phy address\n@@ -817,6 +916,43 @@ int __mdiobus_modify_changed(struct mii_\n EXPORT_SYMBOL_GPL(__mdiobus_modify_changed);\n \n /**\n+ * __mdiobus_modify_changed_paged - Unlocked version of the mdiobus_modify_paged function\n+ * @bus: the mii_bus struct\n+ * @addr: the phy address\n+ * @regnum: register number to modify\n+ * @mask: bit mask of bits to clear\n+ * @set: bit mask of bits to set\n+ *\n+ * Read, modify, and if any change, write the register value back to the\n+ * device. Any error returns a negative number.\n+ *\n+ * NOTE: MUST NOT be called from interrupt context.\n+ */\n+int __mdiobus_modify_changed_paged(struct mii_bus *bus, int addr, u32 regnum, u16 page,\n+\t\t\t\t   u16 mask, u16 set)\n+{\n+\tint new, ret, oldpage;\n+\n+\toldpage = bus->selected_page[addr];\n+\t__mdiobus_select_page(bus, addr, page);\n+\n+\tret = __mdiobus_read_paged(bus, addr, page, regnum);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\tnew = (ret & ~mask) | set;\n+\tif (new == ret)\n+\t\treturn 0;\n+\n+\tret = __mdiobus_write_paged(bus, addr, page, regnum, new);\n+\n+\t__mdiobus_select_page(bus, addr, oldpage);\n+\n+\treturn ret < 0 ? ret : 1;\n+}\n+EXPORT_SYMBOL_GPL(__mdiobus_modify_changed_paged);\n+\n+/**\n  * mdiobus_read_nested - Nested version of the mdiobus_read function\n  * @bus: the mii_bus struct\n  * @addr: the phy address\n@@ -842,6 +978,79 @@ int mdiobus_read_nested(struct mii_bus *\n EXPORT_SYMBOL(mdiobus_read_nested);\n \n /**\n+ * mdiobus_select_page_nested - Nested version of the mdiobus_select_page function\n+ * @bus: the mii_bus struct\n+ * @addr: the phy address\n+ * @page: register page to access\n+ *\n+ * In case of nested MDIO bus access avoid lockdep false positives by\n+ * using mutex_lock_nested().\n+ *\n+ * NOTE: MUST NOT be called from interrupt context,\n+ * because the bus read/write functions may wait for an interrupt\n+ * to conclude the operation.\n+ */\n+int mdiobus_select_page_nested(struct mii_bus *bus, int addr, u16 page)\n+{\n+\tint retval;\n+\n+\tmutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);\n+\tretval = __mdiobus_select_page(bus, addr, page);\n+\tmutex_unlock(&bus->mdio_lock);\n+\n+\treturn retval;\n+}\n+EXPORT_SYMBOL(mdiobus_select_page_nested);\n+\n+/**\n+ * mdiobus_read_paged_nested - Nested version of the mdiobus_read_paged function\n+ * @bus: the mii_bus struct\n+ * @addr: the phy address\n+ * @page: register page to access\n+ * @regnum: register number to read\n+ *\n+ * In case of nested MDIO bus access avoid lockdep false positives by\n+ * using mutex_lock_nested().\n+ *\n+ * NOTE: MUST NOT be called from interrupt context,\n+ * because the bus read/write functions may wait for an interrupt\n+ * to conclude the operation.\n+ */\n+int mdiobus_read_paged_nested(struct mii_bus *bus, int addr, u16 page, u32 regnum)\n+{\n+\tint retval;\n+\n+\tmutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);\n+\tretval = __mdiobus_read_paged(bus, addr, page, regnum);\n+\tmutex_unlock(&bus->mdio_lock);\n+\n+\treturn retval;\n+}\n+EXPORT_SYMBOL(mdiobus_read_paged_nested);\n+\n+/**\n+ * mdiobus_select_page - Convenience function for setting the MII register page\n+ * @bus: the mii_bus struct\n+ * @addr: the phy address\n+ * @page: the register page to set\n+ *\n+ * NOTE: MUST NOT be called from interrupt context,\n+ * because the bus read/write functions may wait for an interrupt\n+ * to conclude the operation.\n+ */\n+int mdiobus_select_page(struct mii_bus *bus, int addr, u16 page)\n+{\n+\tint retval;\n+\n+\tmutex_lock(&bus->mdio_lock);\n+\tretval = __mdiobus_select_page(bus, addr, page);\n+\tmutex_unlock(&bus->mdio_lock);\n+\n+\treturn retval;\n+}\n+EXPORT_SYMBOL(mdiobus_select_page);\n+\n+/**\n  * mdiobus_read - Convenience function for reading a given MII mgmt register\n  * @bus: the mii_bus struct\n  * @addr: the phy address\n@@ -864,6 +1073,29 @@ int mdiobus_read(struct mii_bus *bus, in\n EXPORT_SYMBOL(mdiobus_read);\n \n /**\n+ * mdiobus_read_paged - Convenience function for reading a given paged MII mgmt register\n+ * @bus: the mii_bus struct\n+ * @addr: the phy address\n+ * @page: register page to access\n+ * @regnum: register number to read\n+ *\n+ * NOTE: MUST NOT be called from interrupt context,\n+ * because the bus read/write functions may wait for an interrupt\n+ * to conclude the operation.\n+ */\n+int mdiobus_read_paged(struct mii_bus *bus, int addr, u16 page, u32 regnum)\n+{\n+\tint retval;\n+\n+\tmutex_lock(&bus->mdio_lock);\n+\tretval = __mdiobus_read_paged(bus, addr, page, regnum);\n+\tmutex_unlock(&bus->mdio_lock);\n+\n+\treturn retval;\n+}\n+EXPORT_SYMBOL(mdiobus_read_paged);\n+\n+/**\n  * mdiobus_write_nested - Nested version of the mdiobus_write function\n  * @bus: the mii_bus struct\n  * @addr: the phy address\n@@ -890,6 +1122,33 @@ int mdiobus_write_nested(struct mii_bus\n EXPORT_SYMBOL(mdiobus_write_nested);\n \n /**\n+ * mdiobus_write_paged_nested - Nested version of the mdiobus_write_aged function\n+ * @bus: the mii_bus struct\n+ * @addr: the phy address\n+ * @page: the register page to access\n+ * @regnum: register number to write\n+ * @val: value to write to @regnum\n+ *\n+ * In case of nested MDIO bus access avoid lockdep false positives by\n+ * using mutex_lock_nested().\n+ *\n+ * NOTE: MUST NOT be called from interrupt context,\n+ * because the bus read/write functions may wait for an interrupt\n+ * to conclude the operation.\n+ */\n+int mdiobus_write_paged_nested(struct mii_bus *bus, int addr, u16 page, u32 regnum, u16 val)\n+{\n+\tint err;\n+\n+\tmutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);\n+\terr = __mdiobus_write_paged(bus, addr, page, regnum, val);\n+\tmutex_unlock(&bus->mdio_lock);\n+\n+\treturn err;\n+}\n+EXPORT_SYMBOL(mdiobus_write_paged_nested);\n+\n+/**\n  * mdiobus_write - Convenience function for writing a given MII mgmt register\n  * @bus: the mii_bus struct\n  * @addr: the phy address\n@@ -913,6 +1172,30 @@ int mdiobus_write(struct mii_bus *bus, i\n EXPORT_SYMBOL(mdiobus_write);\n \n /**\n+ * mdiobus_write_paged - Convenience function for writing a given paged MII mgmt register\n+ * @bus: the mii_bus struct\n+ * @addr: the phy address\n+ * @page: the register page to access\n+ * @regnum: register number to write\n+ * @val: value to write to @regnum\n+ *\n+ * NOTE: MUST NOT be called from interrupt context,\n+ * because the bus read/write functions may wait for an interrupt\n+ * to conclude the operation.\n+ */\n+int mdiobus_write_paged(struct mii_bus *bus, int addr, u16 page, u32 regnum, u16 val)\n+{\n+\tint err;\n+\n+\tmutex_lock(&bus->mdio_lock);\n+\terr = __mdiobus_write_paged(bus, addr, page, regnum, val);\n+\tmutex_unlock(&bus->mdio_lock);\n+\n+\treturn err;\n+}\n+EXPORT_SYMBOL(mdiobus_write_paged);\n+\n+/**\n  * mdiobus_modify - Convenience function for modifying a given mdio device\n  *\tregister\n  * @bus: the mii_bus struct\n@@ -934,6 +1217,51 @@ int mdiobus_modify(struct mii_bus *bus,\n EXPORT_SYMBOL_GPL(mdiobus_modify);\n \n /**\n+ * mdiobus_modify_paged - Convenience function for modifying a given mdio device\n+ *\tregister\n+ * @bus: the mii_bus struct\n+ * @addr: the phy address\n+ * @page: the register page to access\n+ * @regnum: register number to write\n+ * @mask: bit mask of bits to clear\n+ * @set: bit mask of bits to set\n+ */\n+int mdiobus_modify_paged(struct mii_bus *bus, int addr, u16 page, u32 regnum, u16 mask, u16 set)\n+{\n+\tint err;\n+\n+\tmutex_lock(&bus->mdio_lock);\n+\terr = __mdiobus_modify_changed_paged(bus, addr, page, regnum, mask, set);\n+\tmutex_unlock(&bus->mdio_lock);\n+\n+\treturn err < 0 ? err : 0;\n+}\n+EXPORT_SYMBOL_GPL(mdiobus_modify_paged);\n+\n+/**\n+ * mdiobus_modify_changed_paged - Convenience function for modifying a given paged\n+ * mdio device register and returning if it changed\n+ * @bus: the mii_bus struct\n+ * @addr: the phy address\n+ * @page: the register page to access\n+ * @regnum: register number to write\n+ * @mask: bit mask of bits to clear\n+ * @set: bit mask of bits to set\n+ */\n+int mdiobus_modify_changed_paged(struct mii_bus *bus, int addr, u16 page, u32 regnum,\n+\t\t\t\t u16 mask, u16 set)\n+{\n+\tint err;\n+\n+\tmutex_lock(&bus->mdio_lock);\n+\terr = __mdiobus_modify_changed_paged(bus, addr, page, regnum, mask, set);\n+\tmutex_unlock(&bus->mdio_lock);\n+\n+\treturn err;\n+}\n+EXPORT_SYMBOL_GPL(mdiobus_modify_changed_paged);\n+\n+/**\n  * mdio_bus_match - determine if given MDIO driver supports the given\n  *\t\t    MDIO device\n  * @dev: target MDIO device\n--- a/drivers/net/phy/phy-core.c\n+++ b/drivers/net/phy/phy-core.c\n@@ -481,10 +481,16 @@ int __phy_read_mmd(struct phy_device *ph\n \t\tstruct mii_bus *bus = phydev->mdio.bus;\n \t\tint phy_addr = phydev->mdio.addr;\n \n-\t\tmmd_phy_indirect(bus, phy_addr, devad, regnum);\n-\n-\t\t/* Read the content of the MMD's selected register */\n-\t\tval = __mdiobus_read(bus, phy_addr, MII_MMD_DATA);\n+\t\tif (bus->access_capabilities & MDIOBUS_ACCESS_C22_MMD) {\n+\t\t\tval = __mdiobus_c22_mmd_read(phydev->mdio.bus,\n+\t\t\t\t\t\t     phydev->mdio.addr,\n+\t\t\t\t\t\t     devad, regnum);\n+\t\t} else {\n+\t\t\tmmd_phy_indirect(bus, phy_addr, devad, regnum);\n+\n+\t\t\t/* Read the content of the MMD's selected register */\n+\t\t\tval = __mdiobus_read(bus, phy_addr, MII_MMD_DATA);\n+\t\t}\n \t}\n \treturn val;\n }\n@@ -537,12 +543,18 @@ int __phy_write_mmd(struct phy_device *p\n \t\tstruct mii_bus *bus = phydev->mdio.bus;\n \t\tint phy_addr = phydev->mdio.addr;\n \n-\t\tmmd_phy_indirect(bus, phy_addr, devad, regnum);\n+\t\tif (bus->access_capabilities & MDIOBUS_ACCESS_C22_MMD) {\n+\t\t\tret = __mdiobus_c22_mmd_write(phydev->mdio.bus,\n+\t\t\t\t\t\t      phydev->mdio.addr,\n+\t\t\t\t\t\t      devad, regnum, val);\n+\t\t} else {\n+\t\t\tmmd_phy_indirect(bus, phy_addr, devad, regnum);\n \n-\t\t/* Write the data into MMD's selected register */\n-\t\t__mdiobus_write(bus, phy_addr, MII_MMD_DATA, val);\n+\t\t\t/* Write the data into MMD's selected register */\n+\t\t\t__mdiobus_write(bus, phy_addr, MII_MMD_DATA, val);\n \n-\t\tret = 0;\n+\t\t\tret = 0;\n+\t\t}\n \t}\n \treturn ret;\n }\n@@ -748,6 +760,13 @@ EXPORT_SYMBOL_GPL(phy_modify_mmd);\n \n static int __phy_read_page(struct phy_device *phydev)\n {\n+\tif (phydev->drv && phydev->drv->flags & PHY_HAS_REALTEK_PAGES) {\n+\t\tstruct mii_bus *bus = phydev->mdio.bus;\n+\t\tint phy_addr = phydev->mdio.addr;\n+\n+\t\treturn bus->selected_page[phy_addr];\n+\t}\n+\n \tif (WARN_ONCE(!phydev->drv->read_page, \"read_page callback not available, PHY driver not loaded?\\n\"))\n \t\treturn -EOPNOTSUPP;\n \n@@ -756,6 +775,13 @@ static int __phy_read_page(struct phy_de\n \n static int __phy_write_page(struct phy_device *phydev, int page)\n {\n+\tif (phydev->drv && phydev->drv->flags & PHY_HAS_REALTEK_PAGES) {\n+\t\tstruct mii_bus *bus = phydev->mdio.bus;\n+\t\tint phy_addr = phydev->mdio.addr;\n+\n+\t\treturn __mdiobus_select_page(bus, phy_addr, page);\n+\t}\n+\n \tif (WARN_ONCE(!phydev->drv->write_page, \"write_page callback not available, PHY driver not loaded?\\n\"))\n \t\treturn -EOPNOTSUPP;\n \n@@ -857,6 +883,18 @@ int phy_read_paged(struct phy_device *ph\n {\n \tint ret = 0, oldpage;\n \n+\tif (phydev->drv && phydev->drv->flags & PHY_HAS_REALTEK_PAGES) {\n+\t\tstruct mii_bus *bus = phydev->mdio.bus;\n+\t\tint phy_addr = phydev->mdio.addr;\n+\n+\t\tif (bus->read_paged) {\n+\t\t\tphy_lock_mdio_bus(phydev);\n+\t\t\tret = bus->read_paged(bus, phy_addr, page, regnum);\n+\t\t\tphy_unlock_mdio_bus(phydev);\n+\t\t\treturn ret;\n+\t\t}\n+\t}\n+\n \toldpage = phy_select_page(phydev, page);\n \tif (oldpage >= 0)\n \t\tret = __phy_read(phydev, regnum);\n@@ -878,6 +916,18 @@ int phy_write_paged(struct phy_device *p\n {\n \tint ret = 0, oldpage;\n \n+\tif (phydev->drv && phydev->drv->flags & PHY_HAS_REALTEK_PAGES) {\n+\t\tstruct mii_bus *bus = phydev->mdio.bus;\n+\t\tint phy_addr = phydev->mdio.addr;\n+\n+\t\tif (bus->write_paged) {\n+\t\t\tphy_lock_mdio_bus(phydev);\n+\t\t\tret = bus->write_paged(bus, phy_addr, page, regnum, val);\n+\t\t\tphy_unlock_mdio_bus(phydev);\n+\t\t\treturn ret;\n+\t\t}\n+\t}\n+\n \toldpage = phy_select_page(phydev, page);\n \tif (oldpage >= 0)\n \t\tret = __phy_write(phydev, regnum, val);\n--- a/include/linux/mdio.h\n+++ b/include/linux/mdio.h\n@@ -14,6 +14,7 @@\n  * IEEE 802.3ae clause 45 addressing mode used by 10GIGE phy chips.\n  */\n #define MII_ADDR_C45\t\t(1<<30)\n+#define MII_ADDR_C22_MMD\t(1<<29)\n #define MII_DEVADDR_C45_SHIFT\t16\n #define MII_DEVADDR_C45_MASK\tGENMASK(20, 16)\n #define MII_REGADDR_C45_MASK\tGENMASK(15, 0)\n@@ -327,11 +328,19 @@ static inline void mii_10gbt_stat_mod_li\n \t\t\t advertising, lpa & MDIO_AN_10GBT_STAT_LP10G);\n }\n \n+int __mdiobus_select_page(struct mii_bus *bus, int addr, u16 page);\n int __mdiobus_read(struct mii_bus *bus, int addr, u32 regnum);\n int __mdiobus_write(struct mii_bus *bus, int addr, u32 regnum, u16 val);\n int __mdiobus_modify_changed(struct mii_bus *bus, int addr, u32 regnum,\n \t\t\t     u16 mask, u16 set);\n \n+int __mdiobus_read_paged(struct mii_bus *bus, int addr, u16 page, u32 regnum);\n+int __mdiobus_write_paged(struct mii_bus *bus, int addr, u16 page, u32 regnum, u16 val);\n+int __mdiobus_modify_changed_paged(struct mii_bus *bus, int addr, u32 regnum, u16 page,\n+\t\t\t\t   u16 mask, u16 set);\n+\n+int mdiobus_select_page(struct mii_bus *bus, int addr, u16 page);\n+int mdiobus_select_page_nested(struct mii_bus *bus, int addr, u16 page);\n int mdiobus_read(struct mii_bus *bus, int addr, u32 regnum);\n int mdiobus_read_nested(struct mii_bus *bus, int addr, u32 regnum);\n int mdiobus_write(struct mii_bus *bus, int addr, u32 regnum, u16 val);\n@@ -339,11 +348,51 @@ int mdiobus_write_nested(struct mii_bus\n int mdiobus_modify(struct mii_bus *bus, int addr, u32 regnum, u16 mask,\n \t\t   u16 set);\n \n+int mdiobus_read_paged(struct mii_bus *bus, int addr, u16 page, u32 regnum);\n+int mdiobus_read_nested_paged(struct mii_bus *bus, int addr, u16 page, u32 regnum);\n+int mdiobus_write_paged(struct mii_bus *bus, int addr, u16 page, u32 regnum, u16 val);\n+int mdiobus_write_nested_paged(struct mii_bus *bus, int addr, u16 page, u32 regnum, u16 val);\n+int mdiobus_modify_paged(struct mii_bus *bus, int addr, u16 page, u32 regnum, u16 mask,\n+\t\t\t u16 set);\n+int mdiobus_modify_changed_paged(struct mii_bus *bus, int addr, u16 page, u32 regnum,\n+\t\t\t\t u16 mask, u16 set);\n+\n+static inline int mdiodev_read_paged(struct mdio_device *mdiodev, u16 page,\n+\t\t\t\t     u32 regnum)\n+{\n+\treturn mdiobus_read_paged(mdiodev->bus, mdiodev->addr, page, regnum);\n+}\n+\n+static inline int mdiodev_write_paged(struct mdio_device *mdiodev, u16 page,\n+\t\t\t\t      u32 regnum, u16 val)\n+{\n+\treturn mdiobus_write_paged(mdiodev->bus, mdiodev->addr, page, regnum, val);\n+}\n+\n+static inline int mdiodev_modify_paged(struct mdio_device *mdiodev, u16 page,\n+\t\t\t\t       u32 regnum, u16 mask, u16 set)\n+{\n+\treturn mdiobus_modify_paged(mdiodev->bus, mdiodev->addr, page, regnum,\n+\t\t\t\t    mask, set);\n+}\n+\n+static inline int mdiodev_modify_changed_paged(struct mdio_device *mdiodev, u16 page,\n+\t\t\t\t\t       u32 regnum, u16 mask, u16 set)\n+{\n+\treturn mdiobus_modify_changed_paged(mdiodev->bus, mdiodev->addr, page, regnum,\n+\t\t\t\t\t    mask, set);\n+}\n+\n static inline u32 mdiobus_c45_addr(int devad, u16 regnum)\n {\n \treturn MII_ADDR_C45 | devad << MII_DEVADDR_C45_SHIFT | regnum;\n }\n \n+static inline u32 mdiobus_c22_mmd_addr(int devad, u16 regnum)\n+{\n+\treturn MII_ADDR_C22_MMD | devad << MII_DEVADDR_C45_SHIFT | regnum;\n+}\n+\n static inline u16 mdiobus_c45_regad(u32 regnum)\n {\n \treturn FIELD_GET(MII_REGADDR_C45_MASK, regnum);\n@@ -367,6 +416,19 @@ static inline int __mdiobus_c45_write(st\n \t\t\t       val);\n }\n \n+static inline int __mdiobus_c22_mmd_read(struct mii_bus *bus, int prtad,\n+\t\t\t\t\t int devad, u16 regnum)\n+{\n+\treturn __mdiobus_read(bus, prtad, mdiobus_c22_mmd_addr(devad, regnum));\n+}\n+\n+static inline int __mdiobus_c22_mmd_write(struct mii_bus *bus, int prtad,\n+\t\t\t\t\t  int devad, u16 regnum, u16 val)\n+{\n+\treturn __mdiobus_write(bus, prtad, mdiobus_c22_mmd_addr(devad, regnum),\n+\t\t\t       val);\n+}\n+\n static inline int mdiobus_c45_read(struct mii_bus *bus, int prtad, int devad,\n \t\t\t\t   u16 regnum)\n {\n--- a/include/linux/phy.h\n+++ b/include/linux/phy.h\n@@ -80,6 +80,7 @@ extern const int phy_10gbit_features_arr\n #define PHY_IS_INTERNAL\t\t0x00000001\n #define PHY_RST_AFTER_CLK_EN\t0x00000002\n #define PHY_POLL_CABLE_TEST\t0x00000004\n+#define PHY_HAS_REALTEK_PAGES\t0x00000010\n #define MDIO_DEVICE_IS_PHY\t0x80000000\n \n /**\n@@ -374,6 +375,22 @@ struct mii_bus {\n \n \t/** @shared: shared state across different PHYs */\n \tstruct phy_package_shared *shared[PHY_MAX_ADDR];\n+\n+\t/** @access_capabilities: hardware-assisted access capabilties */\n+\tenum {\n+\t\tMDIOBUS_ACCESS_SOFTWARE_ONLY = 0,\n+\t\tMDIOBUS_ACCESS_C22_MMD = 0x1,\n+\t} access_capabilities;\n+\n+\t/** @read: Perform a read transfer on the bus, offloading page access */\n+\tint (*read_paged)(struct mii_bus *bus, int addr, u16 page, int regnum);\n+\t/** @write: Perform a write transfer on the bus, offloading page access */\n+\tint (*write_paged)(struct mii_bus *bus, int addr, u16 page, int regnum, u16 val);\n+\t/** currently selected page when page access is offloaded\n+\t * array should be PHY_MAX_ADDR+1size, but current design of the MDIO driver\n+\t * uses port addresses as phy addresses and they are up to 6 bit.\n+\t */\n+\tu16 selected_page[64];\n };\n #define to_mii_bus(d) container_of(d, struct mii_bus, dev)\n \n@@ -1651,6 +1668,66 @@ static inline int __phy_package_read(str\n \treturn __mdiobus_read(phydev->mdio.bus, shared->addr, regnum);\n }\n \n+static inline int phy_package_read_port(struct phy_device *phydev, u16 port, u32 regnum)\n+{\n+\tstruct phy_package_shared *shared = phydev->shared;\n+\n+\tif (!shared)\n+\t\treturn -EIO;\n+\n+\treturn mdiobus_read(phydev->mdio.bus, shared->addr + port, regnum);\n+}\n+\n+static inline int __phy_package_read_port(struct phy_device *phydev, u16 port, u32 regnum)\n+{\n+\tstruct phy_package_shared *shared = phydev->shared;\n+\n+\tif (!shared)\n+\t\treturn -EIO;\n+\n+\treturn __mdiobus_read(phydev->mdio.bus, shared->addr + port, regnum);\n+}\n+\n+static inline int phy_package_read_paged(struct phy_device *phydev, u16 page, u32 regnum)\n+{\n+\tstruct phy_package_shared *shared = phydev->shared;\n+\n+\tif (!shared)\n+\t\treturn -EIO;\n+\n+\treturn mdiobus_read_paged(phydev->mdio.bus, shared->addr, page, regnum);\n+}\n+\n+static inline int __phy_package_read_paged(struct phy_device *phydev, u16 page, u32 regnum)\n+{\n+\tstruct phy_package_shared *shared = phydev->shared;\n+\n+\tif (!shared)\n+\t\treturn -EIO;\n+\n+\treturn __mdiobus_read_paged(phydev->mdio.bus, shared->addr, page, regnum);\n+}\n+\n+static inline int phy_package_port_read_paged(struct phy_device *phydev, u16 port, u16 page, u32 regnum)\n+{\n+\tstruct phy_package_shared *shared = phydev->shared;\n+\n+\tif (!shared)\n+\t\treturn -EIO;\n+\n+\treturn mdiobus_read_paged(phydev->mdio.bus, shared->addr + port, page, regnum);\n+}\n+\n+static inline int __phy_package_port_read_paged(struct phy_device *phydev, u16 port, u16 page, u32 regnum)\n+{\n+\tstruct phy_package_shared *shared = phydev->shared;\n+\n+\tif (!shared)\n+\t\treturn -EIO;\n+\n+\treturn __mdiobus_read_paged(phydev->mdio.bus, shared->addr + port, page, regnum);\n+}\n+\n static inline int phy_package_write(struct phy_device *phydev,\n \t\t\t\t    u32 regnum, u16 val)\n {\n@@ -1673,6 +1750,72 @@ static inline int __phy_package_write(st\n \treturn __mdiobus_write(phydev->mdio.bus, shared->addr, regnum, val);\n }\n \n+static inline int phy_package_port_write(struct phy_device *phydev,\n+\t\t\t\t         u16 port, u32 regnum, u16 val)\n+{\n+\tstruct phy_package_shared *shared = phydev->shared;\n+\n+\tif (!shared)\n+\t\treturn -EIO;\n+\n+\treturn mdiobus_write(phydev->mdio.bus, shared->addr + port, regnum, val);\n+}\n+\n+static inline int __phy_package_port_write(struct phy_device *phydev,\n+\t\t\t\t      u16 port, u32 regnum, u16 val)\n+{\n+\tstruct phy_package_shared *shared = phydev->shared;\n+\n+\tif (!shared)\n+\t\treturn -EIO;\n+\n+\treturn __mdiobus_write(phydev->mdio.bus, shared->addr + port, regnum, val);\n+}\n+\n+static inline int phy_package_port_write_paged(struct phy_device *phydev,\n+\t\t\t\t\tu16 port, u16 page, u32 regnum, u16 val)\n+{\n+\tstruct phy_package_shared *shared = phydev->shared;\n+\n+\tif (!shared)\n+\t\treturn -EIO;\n+\n+\treturn mdiobus_write_paged(phydev->mdio.bus, shared->addr + port, page, regnum, val);\n+}\n+\n+static inline int __phy_package_port_write_paged(struct phy_device *phydev,\n+\t\t\t\t\tu16 port, u16 page, u32 regnum, u16 val)\n+{\n+\tstruct phy_package_shared *shared = phydev->shared;\n+\n+\tif (!shared)\n+\t\treturn -EIO;\n+\n+\treturn __mdiobus_write_paged(phydev->mdio.bus, shared->addr + port, page, regnum, val);\n+}\n+\n+static inline int phy_package_write_paged(struct phy_device *phydev,\n+\t\t\t\t\t  u16 page, u32 regnum, u16 val)\n+{\n+\tstruct phy_package_shared *shared = phydev->shared;\n+\n+\tif (!shared)\n+\t\treturn -EIO;\n+\n+\treturn mdiobus_write_paged(phydev->mdio.bus, shared->addr, page, regnum, val);\n+}\n+\n+static inline int __phy_package_write_paged(struct phy_device *phydev,\n+\t\t\t\t\t  u16 page, u32 regnum, u16 val)\n+{\n+\tstruct phy_package_shared *shared = phydev->shared;\n+\n+\tif (!shared)\n+\t\treturn -EIO;\n+\n+\treturn __mdiobus_write_paged(phydev->mdio.bus, shared->addr, page, regnum, val);\n+}\n+\n static inline bool __phy_package_set_once(struct phy_device *phydev,\n \t\t\t\t\t  unsigned int b)\n {\n--- a/include/uapi/linux/mii.h\n+++ b/include/uapi/linux/mii.h\n@@ -36,6 +36,7 @@\n #define MII_RESV2\t\t0x1a\t/* Reserved...                 */\n #define MII_TPISTATUS\t\t0x1b\t/* TPI status for 10mbps       */\n #define MII_NCONFIG\t\t0x1c\t/* Network interface config    */\n+#define MII_MAINPAGE\t\t0x1f\t/* Page register               */\n \n /* Basic mode control register. */\n #define BMCR_RESV\t\t0x003f\t/* Unused...                   */\n"
  },
  {
    "path": "target/linux/realtek/profiles/00-default.mk",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n\ndefine Profile/Default\n\tNAME:=Default Profile\n\tPRIORITY:=1\nendef\n\ndefine Profile/Default/Description\n\tDefault package set compatible with most boards.\nendef\n\n$(eval $(call Profile,Default))\n"
  },
  {
    "path": "target/linux/realtek/rtl838x/config-5.10",
    "content": "CONFIG_ARCH_32BIT_OFF_T=y\nCONFIG_ARCH_HIBERNATION_POSSIBLE=y\nCONFIG_ARCH_MMAP_RND_BITS_MAX=15\nCONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15\nCONFIG_ARCH_SUSPEND_POSSIBLE=y\nCONFIG_BLK_DEV_RAM=y\nCONFIG_BLK_DEV_RAM_COUNT=16\nCONFIG_BLK_DEV_RAM_SIZE=4096\nCONFIG_CEVT_R4K=y\nCONFIG_CEVT_RTL9300=y\nCONFIG_CLKDEV_LOOKUP=y\nCONFIG_CLKSRC_MMIO=y\nCONFIG_CLONE_BACKWARDS=y\nCONFIG_COMMON_CLK=y\nCONFIG_COMMON_CLK_BOSTON=y\nCONFIG_COMPAT_32BIT_TIME=y\nCONFIG_CONSOLE_LOGLEVEL_DEFAULT=15\nCONFIG_CPU_BIG_ENDIAN=y\nCONFIG_CPU_GENERIC_DUMP_TLB=y\nCONFIG_CPU_HAS_DIEI=y\nCONFIG_CPU_HAS_PREFETCH=y\nCONFIG_CPU_HAS_RIXI=y\nCONFIG_CPU_HAS_SYNC=y\nCONFIG_CPU_MIPS32=y\n# CONFIG_CPU_MIPS32_R1 is not set\nCONFIG_CPU_MIPS32_R2=y\nCONFIG_CPU_MIPSR2=y\nCONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y\nCONFIG_CPU_R4K_CACHE_TLB=y\nCONFIG_CPU_SUPPORTS_32BIT_KERNEL=y\nCONFIG_CPU_SUPPORTS_HIGHMEM=y\nCONFIG_CPU_SUPPORTS_MSA=y\nCONFIG_CRYPTO_LIB_POLY1305_RSIZE=2\nCONFIG_CRYPTO_RNG2=y\nCONFIG_CSRC_R4K=y\nCONFIG_DEBUG_INFO=y\nCONFIG_DEBUG_SECTION_MISMATCH=y\nCONFIG_DMA_NONCOHERENT=y\nCONFIG_DTC=y\nCONFIG_EARLY_PRINTK=y\nCONFIG_EARLY_PRINTK_8250=y\nCONFIG_EXTRA_FIRMWARE=\"rtl838x_phy/rtl838x_8214fc.fw rtl838x_phy/rtl838x_8218b.fw rtl838x_phy/rtl838x_8380.fw\"\nCONFIG_EXTRA_FIRMWARE_DIR=\"firmware\"\nCONFIG_FIXED_PHY=y\nCONFIG_FORCE_MAX_ZONEORDER=13\nCONFIG_FW_LOADER_PAGED_BUF=y\nCONFIG_GENERIC_ATOMIC64=y\nCONFIG_GENERIC_CLOCKEVENTS=y\nCONFIG_GENERIC_CMOS_UPDATE=y\nCONFIG_GENERIC_CPU_AUTOPROBE=y\nCONFIG_GENERIC_GETTIMEOFDAY=y\nCONFIG_GENERIC_IOMAP=y\nCONFIG_GENERIC_IRQ_CHIP=y\nCONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y\nCONFIG_GENERIC_IRQ_SHOW=y\nCONFIG_GENERIC_LIB_ASHLDI3=y\nCONFIG_GENERIC_LIB_ASHRDI3=y\nCONFIG_GENERIC_LIB_CMPDI2=y\nCONFIG_GENERIC_LIB_LSHRDI3=y\nCONFIG_GENERIC_LIB_UCMPDI2=y\nCONFIG_GENERIC_PCI_IOMAP=y\nCONFIG_GENERIC_PHY=y\nCONFIG_GENERIC_PINCONF=y\nCONFIG_GENERIC_PINCTRL_GROUPS=y\nCONFIG_GENERIC_PINMUX_FUNCTIONS=y\nCONFIG_GENERIC_SCHED_CLOCK=y\nCONFIG_GENERIC_SMP_IDLE_THREAD=y\nCONFIG_GENERIC_TIME_VSYSCALL=y\nCONFIG_GPIOLIB=y\nCONFIG_GPIOLIB_IRQCHIP=y\nCONFIG_GPIO_GENERIC=y\nCONFIG_GPIO_PCA953X=y\nCONFIG_GPIO_PCA953X_IRQ=y\nCONFIG_GPIO_REALTEK_OTTO=y\nCONFIG_GPIO_RTL8231=y\nCONFIG_GRO_CELLS=y\nCONFIG_HANDLE_DOMAIN_IRQ=y\nCONFIG_HARDWARE_WATCHPOINTS=y\nCONFIG_HAS_DMA=y\nCONFIG_HAS_IOMEM=y\nCONFIG_HAS_IOPORT_MAP=y\nCONFIG_HIGH_RES_TIMERS=y\nCONFIG_HWMON=y\nCONFIG_HZ_PERIODIC=y\nCONFIG_I2C=y\nCONFIG_I2C_ALGOBIT=y\nCONFIG_I2C_BOARDINFO=y\nCONFIG_I2C_CHARDEV=y\nCONFIG_I2C_GPIO=y\nCONFIG_I2C_MUX=y\n# CONFIG_I2C_RTL9300 is not set\n# CONFIG_I2C_MUX_RTL9300 is not set\nCONFIG_INITRAMFS_SOURCE=\"\"\nCONFIG_IRQCHIP=y\nCONFIG_IRQ_DOMAIN=y\nCONFIG_IRQ_FORCED_THREADING=y\nCONFIG_IRQ_MIPS_CPU=y\nCONFIG_IRQ_WORK=y\nCONFIG_JFFS2_ZLIB=y\nCONFIG_LEDS_GPIO=y\nCONFIG_LEGACY_PTYS=y\nCONFIG_LEGACY_PTY_COUNT=256\nCONFIG_LIBFDT=y\nCONFIG_LOCK_DEBUGGING_SUPPORT=y\nCONFIG_MARVELL_PHY=y\nCONFIG_MDIO_BUS=y\nCONFIG_MDIO_DEVICE=y\nCONFIG_MDIO_DEVRES=y\nCONFIG_MDIO_I2C=y\nCONFIG_MEMFD_CREATE=y\nCONFIG_MFD_SYSCON=y\nCONFIG_MIGRATION=y\nCONFIG_MIPS=y\nCONFIG_MIPS_ASID_BITS=8\nCONFIG_MIPS_ASID_SHIFT=0\nCONFIG_MIPS_CBPF_JIT=y\nCONFIG_MIPS_CLOCK_VSYSCALL=y\n# CONFIG_MIPS_CMDLINE_DTB_EXTEND is not set\n# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set\nCONFIG_MIPS_CMDLINE_FROM_DTB=y\n# CONFIG_MIPS_ELF_APPENDED_DTB is not set\nCONFIG_MIPS_L1_CACHE_SHIFT=5\nCONFIG_MIPS_LD_CAN_LINK_VDSO=y\n# CONFIG_MIPS_NO_APPENDED_DTB is not set\nCONFIG_MIPS_RAW_APPENDED_DTB=y\nCONFIG_MIPS_SPRAM=y\nCONFIG_MODULES_USE_ELF_REL=y\nCONFIG_MTD_CFI_ADV_OPTIONS=y\nCONFIG_MTD_CFI_GEOMETRY=y\nCONFIG_MTD_CMDLINE_PARTS=y\nCONFIG_MTD_JEDECPROBE=y\nCONFIG_MTD_SPI_NOR=y\nCONFIG_MTD_SPLIT_BRNIMAGE_FW=y\nCONFIG_MTD_SPLIT_EVA_FW=y\nCONFIG_MTD_SPLIT_FIRMWARE=y\nCONFIG_MTD_SPLIT_TPLINK_FW=y\nCONFIG_MTD_SPLIT_UIMAGE_FW=y\nCONFIG_NEED_DMA_MAP_STATE=y\nCONFIG_NEED_PER_CPU_KM=y\nCONFIG_NET_DEVLINK=y\nCONFIG_NET_DSA=y\nCONFIG_NET_DSA_RTL83XX=y\nCONFIG_NET_DSA_TAG_TRAILER=y\nCONFIG_NET_RTL838X=y\nCONFIG_NET_SWITCHDEV=y\nCONFIG_NO_GENERIC_PCI_IOPORT_MAP=y\nCONFIG_NVMEM=y\nCONFIG_OF=y\nCONFIG_OF_ADDRESS=y\nCONFIG_OF_EARLY_FLATTREE=y\nCONFIG_OF_FLATTREE=y\nCONFIG_OF_GPIO=y\nCONFIG_OF_IRQ=y\nCONFIG_OF_KOBJ=y\nCONFIG_OF_MDIO=y\nCONFIG_OF_NET=y\nCONFIG_PCI_DRIVERS_LEGACY=y\nCONFIG_PERF_USE_VMALLOC=y\nCONFIG_PGTABLE_LEVELS=2\nCONFIG_PHYLIB=y\nCONFIG_PHYLINK=y\nCONFIG_PINCTRL=y\nCONFIG_POWER_RESET=y\nCONFIG_POWER_RESET_GPIO_RESTART=y\nCONFIG_POWER_RESET_SYSCON=y\nCONFIG_RATIONAL=y\nCONFIG_REALTEK_OTTO_WDT=y\nCONFIG_REALTEK_PHY=y\nCONFIG_REALTEK_SOC_PHY=y\nCONFIG_REGMAP=y\nCONFIG_REGMAP_I2C=y\nCONFIG_REGMAP_MMIO=y\nCONFIG_RESET_CONTROLLER=y\nCONFIG_RTL83XX=y\nCONFIG_RTL838X=y\n# CONFIG_RTL839X is not set\n# CONFIG_RTL930X is not set\n# CONFIG_RTL931X is not set\nCONFIG_SERIAL_MCTRL_GPIO=y\nCONFIG_SERIAL_OF_PLATFORM=y\nCONFIG_SFP=y\nCONFIG_SPI=y\nCONFIG_SPI_MASTER=y\nCONFIG_SPI_MEM=y\nCONFIG_SRCU=y\nCONFIG_SWPHY=y\nCONFIG_SYSCTL_EXCEPTION_TRACE=y\nCONFIG_SYS_HAS_CPU_MIPS32_R1=y\nCONFIG_SYS_HAS_CPU_MIPS32_R2=y\nCONFIG_SYS_HAS_EARLY_PRINTK=y\nCONFIG_SYS_SUPPORTS_32BIT_KERNEL=y\nCONFIG_SYS_SUPPORTS_ARBIT_HZ=y\nCONFIG_SYS_SUPPORTS_BIG_ENDIAN=y\nCONFIG_SYS_SUPPORTS_MIPS16=y\nCONFIG_TARGET_ISA_REV=2\nCONFIG_TICK_CPU_ACCOUNTING=y\nCONFIG_TIMER_OF=y\nCONFIG_TIMER_PROBE=y\nCONFIG_TINY_SRCU=y\nCONFIG_USE_GENERIC_EARLY_PRINTK_8250=y\nCONFIG_USE_OF=y\nCONFIG_WATCHDOG_CORE=y\nCONFIG_ZLIB_DEFLATE=y\nCONFIG_ZLIB_INFLATE=y\n"
  },
  {
    "path": "target/linux/realtek/rtl838x/target.mk",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\nARCH:=mips\nSUBTARGET:=rtl838x\nCPU_TYPE:=4kec\nBOARD:=realtek\nBOARDNAME:=Realtek MIPS RTL838X\n\nKERNEL_PATCHVER:=5.10\n\ndefine Target/Description\n\tBuild firmware images for Realtek RTL838x based boards.\nendef\n\nFEATURES := $(filter-out mips16,$(FEATURES))\n\n"
  },
  {
    "path": "target/linux/realtek/rtl839x/config-5.10",
    "content": "CONFIG_ARCH_32BIT_OFF_T=y\nCONFIG_ARCH_HIBERNATION_POSSIBLE=y\nCONFIG_ARCH_MMAP_RND_BITS_MAX=15\nCONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15\nCONFIG_ARCH_SUSPEND_POSSIBLE=y\nCONFIG_BLK_DEV_RAM=y\nCONFIG_BLK_DEV_RAM_COUNT=16\nCONFIG_BLK_DEV_RAM_SIZE=4096\nCONFIG_CEVT_R4K=y\nCONFIG_CEVT_RTL9300=y\nCONFIG_CLKDEV_LOOKUP=y\nCONFIG_CLKSRC_MMIO=y\nCONFIG_CLONE_BACKWARDS=y\nCONFIG_COMMON_CLK=y\nCONFIG_COMMON_CLK_BOSTON=y\nCONFIG_COMPAT_32BIT_TIME=y\nCONFIG_CONSOLE_LOGLEVEL_DEFAULT=15\nCONFIG_CPU_BIG_ENDIAN=y\nCONFIG_CPU_GENERIC_DUMP_TLB=y\nCONFIG_CPU_HAS_DIEI=y\nCONFIG_CPU_HAS_PREFETCH=y\nCONFIG_CPU_HAS_RIXI=y\nCONFIG_CPU_HAS_SYNC=y\nCONFIG_CPU_MIPS32=y\n# CONFIG_CPU_MIPS32_R1 is not set\nCONFIG_CPU_MIPS32_R2=y\nCONFIG_CPU_MIPSR2=y\nCONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y\nCONFIG_CPU_R4K_CACHE_TLB=y\nCONFIG_CPU_SUPPORTS_32BIT_KERNEL=y\nCONFIG_CPU_SUPPORTS_HIGHMEM=y\nCONFIG_CPU_SUPPORTS_MSA=y\nCONFIG_CRYPTO_GF128MUL=y\nCONFIG_CRYPTO_LIB_POLY1305_RSIZE=2\nCONFIG_CRYPTO_NULL2=y\nCONFIG_CRYPTO_RNG2=y\nCONFIG_CSRC_R4K=y\nCONFIG_DEBUG_INFO=y\nCONFIG_DEBUG_SECTION_MISMATCH=y\nCONFIG_DMA_NONCOHERENT=y\nCONFIG_DTC=y\nCONFIG_EARLY_PRINTK=y\nCONFIG_EARLY_PRINTK_8250=y\nCONFIG_FIXED_PHY=y\nCONFIG_FORCE_MAX_ZONEORDER=13\nCONFIG_FW_LOADER_PAGED_BUF=y\nCONFIG_GENERIC_ATOMIC64=y\nCONFIG_GENERIC_CLOCKEVENTS=y\nCONFIG_GENERIC_CMOS_UPDATE=y\nCONFIG_GENERIC_CPU_AUTOPROBE=y\nCONFIG_GENERIC_GETTIMEOFDAY=y\nCONFIG_GENERIC_IOMAP=y\nCONFIG_GENERIC_IRQ_CHIP=y\nCONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y\nCONFIG_GENERIC_IRQ_SHOW=y\nCONFIG_GENERIC_LIB_ASHLDI3=y\nCONFIG_GENERIC_LIB_ASHRDI3=y\nCONFIG_GENERIC_LIB_CMPDI2=y\nCONFIG_GENERIC_LIB_LSHRDI3=y\nCONFIG_GENERIC_LIB_UCMPDI2=y\nCONFIG_GENERIC_PCI_IOMAP=y\nCONFIG_GENERIC_PHY=y\nCONFIG_GENERIC_PINCONF=y\nCONFIG_GENERIC_PINCTRL_GROUPS=y\nCONFIG_GENERIC_PINMUX_FUNCTIONS=y\nCONFIG_GENERIC_SCHED_CLOCK=y\nCONFIG_GENERIC_SMP_IDLE_THREAD=y\nCONFIG_GENERIC_TIME_VSYSCALL=y\nCONFIG_GPIOLIB=y\nCONFIG_GPIOLIB_IRQCHIP=y\nCONFIG_GPIO_GENERIC=y\nCONFIG_GPIO_REALTEK_OTTO=y\nCONFIG_GPIO_RTL8231=y\nCONFIG_GRO_CELLS=y\nCONFIG_HANDLE_DOMAIN_IRQ=y\nCONFIG_HARDWARE_WATCHPOINTS=y\nCONFIG_HAS_DMA=y\nCONFIG_HAS_IOMEM=y\nCONFIG_HAS_IOPORT_MAP=y\nCONFIG_HIGH_RES_TIMERS=y\nCONFIG_HWMON=y\nCONFIG_HZ_PERIODIC=y\nCONFIG_I2C=y\nCONFIG_I2C_ALGOBIT=y\nCONFIG_I2C_BOARDINFO=y\nCONFIG_I2C_GPIO=y\n# CONFIG_I2C_RTL9300 is not set\n# CONFIG_I2C_MUX_RTL9300 is not set\nCONFIG_INITRAMFS_SOURCE=\"\"\nCONFIG_IRQCHIP=y\nCONFIG_IRQ_DOMAIN=y\nCONFIG_IRQ_FORCED_THREADING=y\nCONFIG_IRQ_MIPS_CPU=y\nCONFIG_IRQ_WORK=y\nCONFIG_JFFS2_ZLIB=y\nCONFIG_LEDS_GPIO=y\nCONFIG_LEGACY_PTYS=y\nCONFIG_LEGACY_PTY_COUNT=256\nCONFIG_LIBFDT=y\nCONFIG_LLD_VERSION=0\nCONFIG_LOCK_DEBUGGING_SUPPORT=y\nCONFIG_MARVELL_PHY=y\nCONFIG_MDIO_BUS=y\nCONFIG_MDIO_DEVICE=y\nCONFIG_MDIO_DEVRES=y\nCONFIG_MDIO_I2C=y\nCONFIG_MEMFD_CREATE=y\nCONFIG_MFD_SYSCON=y\nCONFIG_MIGRATION=y\nCONFIG_MIPS=y\nCONFIG_MIPS_ASID_BITS=8\nCONFIG_MIPS_ASID_SHIFT=0\nCONFIG_MIPS_CBPF_JIT=y\nCONFIG_MIPS_CLOCK_VSYSCALL=y\n# CONFIG_MIPS_CMDLINE_DTB_EXTEND is not set\n# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set\nCONFIG_MIPS_CMDLINE_FROM_DTB=y\n# CONFIG_MIPS_ELF_APPENDED_DTB is not set\nCONFIG_MIPS_L1_CACHE_SHIFT=5\nCONFIG_MIPS_LD_CAN_LINK_VDSO=y\n# CONFIG_MIPS_NO_APPENDED_DTB is not set\nCONFIG_MIPS_MT_SMP=y\n# CONFIG_MIPS_MT_FPAFF is not set\nCONFIG_NR_CPUS=2\nCONFIG_MIPS_RAW_APPENDED_DTB=y\nCONFIG_MIPS_SPRAM=y\nCONFIG_MODULES_USE_ELF_REL=y\nCONFIG_MTD_CFI_ADV_OPTIONS=y\nCONFIG_MTD_CFI_GEOMETRY=y\nCONFIG_MTD_CMDLINE_PARTS=y\nCONFIG_MTD_JEDECPROBE=y\nCONFIG_MTD_SPI_NOR=y\nCONFIG_MTD_SPLIT_BRNIMAGE_FW=y\nCONFIG_MTD_SPLIT_EVA_FW=y\nCONFIG_MTD_SPLIT_FIRMWARE=y\nCONFIG_MTD_SPLIT_TPLINK_FW=y\nCONFIG_MTD_SPLIT_UIMAGE_FW=y\nCONFIG_NEED_DMA_MAP_STATE=y\nCONFIG_NEED_PER_CPU_KM=y\nCONFIG_NET_DEVLINK=y\nCONFIG_NET_DSA=y\nCONFIG_NET_DSA_RTL83XX=y\nCONFIG_NET_DSA_TAG_TRAILER=y\nCONFIG_NET_RTL838X=y\nCONFIG_NET_SWITCHDEV=y\nCONFIG_NO_GENERIC_PCI_IOPORT_MAP=y\nCONFIG_NVMEM=y\nCONFIG_OF=y\nCONFIG_OF_ADDRESS=y\nCONFIG_OF_EARLY_FLATTREE=y\nCONFIG_OF_FLATTREE=y\nCONFIG_OF_GPIO=y\nCONFIG_OF_IRQ=y\nCONFIG_OF_KOBJ=y\nCONFIG_OF_MDIO=y\nCONFIG_OF_NET=y\nCONFIG_PCI_DRIVERS_LEGACY=y\nCONFIG_PERF_USE_VMALLOC=y\nCONFIG_PGTABLE_LEVELS=2\nCONFIG_PHYLIB=y\nCONFIG_PHYLINK=y\nCONFIG_PINCTRL=y\nCONFIG_POWER_RESET=y\nCONFIG_POWER_RESET_GPIO_RESTART=y\nCONFIG_POWER_RESET_SYSCON=y\nCONFIG_RATIONAL=y\nCONFIG_REALTEK_OTTO_WDT=y\nCONFIG_REALTEK_PHY=y\nCONFIG_REALTEK_SOC_PHY=y\nCONFIG_REGMAP=y\nCONFIG_REGMAP_MMIO=y\nCONFIG_RESET_CONTROLLER=y\nCONFIG_RTL83XX=y\n# CONFIG_RTL838X is not set\nCONFIG_RTL839X=y\n# CONFIG_RTL930X is not set\n# CONFIG_RTL931X is not set\nCONFIG_SERIAL_MCTRL_GPIO=y\nCONFIG_SERIAL_OF_PLATFORM=y\nCONFIG_SFP=y\nCONFIG_SPI=y\nCONFIG_SPI_MASTER=y\nCONFIG_SPI_MEM=y\nCONFIG_SRCU=y\nCONFIG_SWPHY=y\nCONFIG_SYSCTL_EXCEPTION_TRACE=y\nCONFIG_SYS_HAS_CPU_MIPS32_R1=y\nCONFIG_SYS_HAS_CPU_MIPS32_R2=y\nCONFIG_SYS_HAS_EARLY_PRINTK=y\nCONFIG_SYS_SUPPORTS_32BIT_KERNEL=y\nCONFIG_SYS_SUPPORTS_ARBIT_HZ=y\nCONFIG_SYS_SUPPORTS_BIG_ENDIAN=y\nCONFIG_SYS_SUPPORTS_MIPS16=y\nCONFIG_TARGET_ISA_REV=2\nCONFIG_TICK_CPU_ACCOUNTING=y\nCONFIG_TIMER_OF=y\nCONFIG_TIMER_PROBE=y\nCONFIG_TINY_SRCU=y\nCONFIG_USE_GENERIC_EARLY_PRINTK_8250=y\nCONFIG_USE_OF=y\nCONFIG_WATCHDOG_CORE=y\nCONFIG_ZLIB_DEFLATE=y\nCONFIG_ZLIB_INFLATE=y\n"
  },
  {
    "path": "target/linux/realtek/rtl839x/target.mk",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\nARCH:=mips\nSUBTARGET:=rtl839x\nCPU_TYPE:=24kc\nBOARD:=realtek\nBOARDNAME:=Realtek MIPS RTL839X\n\nKERNEL_PATCHVER:=5.10\n\ndefine Target/Description\n\tBuild firmware images for Realtek RTL839x based boards.\nendef\n\n"
  },
  {
    "path": "target/linux/realtek/rtl930x/config-5.10",
    "content": "CONFIG_AQUANTIA_PHY=y\nCONFIG_ARCH_32BIT_OFF_T=y\nCONFIG_ARCH_HIBERNATION_POSSIBLE=y\nCONFIG_ARCH_MMAP_RND_BITS_MAX=15\nCONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15\nCONFIG_ARCH_SUSPEND_POSSIBLE=y\nCONFIG_BLK_DEV_RAM=y\nCONFIG_BLK_DEV_RAM_COUNT=16\nCONFIG_BLK_DEV_RAM_SIZE=4096\nCONFIG_CEVT_RTL9300=y\n# CONFIG_CEVT_R4K is not set\nCONFIG_CLKDEV_LOOKUP=y\nCONFIG_CLKSRC_MMIO=y\nCONFIG_CLONE_BACKWARDS=y\nCONFIG_COMMON_CLK=y\nCONFIG_COMMON_CLK_BOSTON=y\nCONFIG_COMPAT_32BIT_TIME=y\nCONFIG_CONSOLE_LOGLEVEL_DEFAULT=15\nCONFIG_CPU_BIG_ENDIAN=y\nCONFIG_CPU_GENERIC_DUMP_TLB=y\nCONFIG_CPU_HAS_DIEI=y\nCONFIG_CPU_HAS_PREFETCH=y\nCONFIG_CPU_HAS_RIXI=y\nCONFIG_CPU_HAS_SYNC=y\nCONFIG_CPU_MIPS32=y\n# CONFIG_CPU_MIPS32_R1 is not set\nCONFIG_CPU_MIPS32_R2=y\nCONFIG_CPU_MIPSR2=y\nCONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y\nCONFIG_CPU_R4K_CACHE_TLB=y\nCONFIG_CPU_SUPPORTS_32BIT_KERNEL=y\nCONFIG_CPU_SUPPORTS_HIGHMEM=y\nCONFIG_CPU_SUPPORTS_MSA=y\nCONFIG_CRYPTO_GF128MUL=y\nCONFIG_CRYPTO_LIB_POLY1305_RSIZE=2\nCONFIG_CRYPTO_NULL2=y\nCONFIG_CRYPTO_RNG2=y\nCONFIG_CSRC_R4K=y\nCONFIG_DEBUG_INFO=y\nCONFIG_DEBUG_SECTION_MISMATCH=y\nCONFIG_DMA_NONCOHERENT=y\nCONFIG_DTC=y\nCONFIG_EARLY_PRINTK=y\nCONFIG_EARLY_PRINTK_8250=y\nCONFIG_FIXED_PHY=y\nCONFIG_FORCE_MAX_ZONEORDER=13\nCONFIG_FW_LOADER_PAGED_BUF=y\nCONFIG_GENERIC_ATOMIC64=y\nCONFIG_GENERIC_CLOCKEVENTS=y\nCONFIG_GENERIC_CMOS_UPDATE=y\nCONFIG_GENERIC_CPU_AUTOPROBE=y\nCONFIG_GENERIC_GETTIMEOFDAY=y\nCONFIG_GENERIC_IOMAP=y\nCONFIG_GENERIC_IRQ_CHIP=y\nCONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y\nCONFIG_GENERIC_IRQ_SHOW=y\nCONFIG_GENERIC_LIB_ASHLDI3=y\nCONFIG_GENERIC_LIB_ASHRDI3=y\nCONFIG_GENERIC_LIB_CMPDI2=y\nCONFIG_GENERIC_LIB_LSHRDI3=y\nCONFIG_GENERIC_LIB_UCMPDI2=y\nCONFIG_GENERIC_PCI_IOMAP=y\nCONFIG_GENERIC_PHY=y\nCONFIG_GENERIC_PINCONF=y\nCONFIG_GENERIC_PINCTRL_GROUPS=y\nCONFIG_GENERIC_PINMUX_FUNCTIONS=y\nCONFIG_GENERIC_SCHED_CLOCK=y\nCONFIG_GENERIC_SMP_IDLE_THREAD=y\nCONFIG_GENERIC_TIME_VSYSCALL=y\nCONFIG_GPIOLIB=y\nCONFIG_GPIOLIB_IRQCHIP=y\nCONFIG_GPIO_GENERIC=y\nCONFIG_GPIO_PCA953X=y\nCONFIG_GPIO_REALTEK_OTTO=y\nCONFIG_GPIO_RTL8231=y\nCONFIG_GRO_CELLS=y\nCONFIG_HANDLE_DOMAIN_IRQ=y\nCONFIG_HARDWARE_WATCHPOINTS=y\nCONFIG_HAS_DMA=y\nCONFIG_HAS_IOMEM=y\nCONFIG_HAS_IOPORT_MAP=y\nCONFIG_HIGH_RES_TIMERS=y\nCONFIG_HWMON=y\nCONFIG_HZ_PERIODIC=y\nCONFIG_I2C=y\nCONFIG_I2C_ALGOBIT=y\nCONFIG_I2C_BOARDINFO=y\nCONFIG_I2C_CHARDEV=y\nCONFIG_I2C_GPIO=y\nCONFIG_I2C_MUX=y\nCONFIG_I2C_MUX_RTL9300=y\nCONFIG_I2C_RTL9300=y\nCONFIG_I2C_SMBUS=y\nCONFIG_INITRAMFS_SOURCE=\"\"\nCONFIG_IRQCHIP=y\nCONFIG_IRQ_DOMAIN=y\nCONFIG_IRQ_FORCED_THREADING=y\nCONFIG_IRQ_MIPS_CPU=y\nCONFIG_IRQ_WORK=y\nCONFIG_JFFS2_ZLIB=y\nCONFIG_LEDS_GPIO=y\nCONFIG_LEGACY_PTYS=y\nCONFIG_LEGACY_PTY_COUNT=256\nCONFIG_LIBFDT=y\nCONFIG_LLD_VERSION=0\nCONFIG_LOCK_DEBUGGING_SUPPORT=y\nCONFIG_MARVELL_PHY=y\nCONFIG_MDIO_BUS=y\nCONFIG_MDIO_DEVICE=y\nCONFIG_MDIO_DEVRES=y\nCONFIG_MDIO_I2C=y\nCONFIG_MDIO_SMBUS=y\nCONFIG_MEMFD_CREATE=y\nCONFIG_MFD_SYSCON=y\nCONFIG_MIGRATION=y\nCONFIG_MIPS=y\nCONFIG_MIPS_ASID_BITS=8\nCONFIG_MIPS_ASID_SHIFT=0\nCONFIG_MIPS_CBPF_JIT=y\nCONFIG_MIPS_CLOCK_VSYSCALL=y\n# CONFIG_MIPS_CMDLINE_DTB_EXTEND is not set\n# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set\nCONFIG_MIPS_CMDLINE_FROM_DTB=y\n# CONFIG_MIPS_ELF_APPENDED_DTB is not set\nCONFIG_MIPS_L1_CACHE_SHIFT=5\nCONFIG_MIPS_LD_CAN_LINK_VDSO=y\n# CONFIG_MIPS_NO_APPENDED_DTB is not set\n# CONFIG_MIPS_MT_SMP is not set\n# CONFIG_MIPS_MT_FPAFF is not set\nCONFIG_NR_CPUS=2\nCONFIG_MIPS_RAW_APPENDED_DTB=y\nCONFIG_MIPS_SPRAM=y\nCONFIG_MODULES_USE_ELF_REL=y\nCONFIG_MTD_CFI_ADV_OPTIONS=y\nCONFIG_MTD_CFI_GEOMETRY=y\nCONFIG_MTD_CMDLINE_PARTS=y\nCONFIG_MTD_JEDECPROBE=y\nCONFIG_MTD_SPI_NOR=y\nCONFIG_MTD_SPLIT_BRNIMAGE_FW=y\nCONFIG_MTD_SPLIT_EVA_FW=y\nCONFIG_MTD_SPLIT_FIRMWARE=y\nCONFIG_MTD_SPLIT_TPLINK_FW=y\nCONFIG_MTD_SPLIT_UIMAGE_FW=y\nCONFIG_NEED_DMA_MAP_STATE=y\nCONFIG_NEED_PER_CPU_KM=y\nCONFIG_NET_DEVLINK=y\nCONFIG_NET_DSA=y\nCONFIG_NET_DSA_RTL83XX=y\nCONFIG_NET_DSA_TAG_TRAILER=y\nCONFIG_NET_RTL838X=y\nCONFIG_NET_SWITCHDEV=y\nCONFIG_NO_GENERIC_PCI_IOPORT_MAP=y\nCONFIG_NVMEM=y\nCONFIG_OF=y\nCONFIG_OF_ADDRESS=y\nCONFIG_OF_EARLY_FLATTREE=y\nCONFIG_OF_FLATTREE=y\nCONFIG_OF_GPIO=y\nCONFIG_OF_IRQ=y\nCONFIG_OF_KOBJ=y\nCONFIG_OF_MDIO=y\nCONFIG_OF_NET=y\nCONFIG_PCI_DRIVERS_LEGACY=y\nCONFIG_PERF_USE_VMALLOC=y\nCONFIG_PGTABLE_LEVELS=2\nCONFIG_PHYLIB=y\nCONFIG_PHYLINK=y\nCONFIG_PINCTRL=y\nCONFIG_POWER_RESET=y\nCONFIG_POWER_RESET_GPIO_RESTART=y\nCONFIG_POWER_RESET_SYSCON=y\nCONFIG_RATIONAL=y\nCONFIG_REALTEK_OTTO_WDT=y\nCONFIG_REALTEK_PHY=y\nCONFIG_REALTEK_SOC_PHY=y\nCONFIG_REGMAP=y\nCONFIG_REGMAP_MMIO=y\nCONFIG_RESET_CONTROLLER=y\nCONFIG_RTL83XX=y\n# CONFIG_RTL838X is not set\n# CONFIG_RTL839X is not set\nCONFIG_RTL930X=y\n# CONFIG_RTL931X is not set\nCONFIG_SERIAL_MCTRL_GPIO=y\nCONFIG_SERIAL_OF_PLATFORM=y\nCONFIG_SFP=y\nCONFIG_SPI=y\nCONFIG_SPI_MASTER=y\nCONFIG_SPI_MEM=y\nCONFIG_SRCU=y\nCONFIG_SWPHY=y\nCONFIG_SYSCTL_EXCEPTION_TRACE=y\nCONFIG_SYS_HAS_CPU_MIPS32_R1=y\nCONFIG_SYS_HAS_CPU_MIPS32_R2=y\nCONFIG_SYS_HAS_EARLY_PRINTK=y\nCONFIG_SYS_SUPPORTS_32BIT_KERNEL=y\nCONFIG_SYS_SUPPORTS_ARBIT_HZ=y\nCONFIG_SYS_SUPPORTS_BIG_ENDIAN=y\nCONFIG_SYS_SUPPORTS_MIPS16=y\nCONFIG_TARGET_ISA_REV=2\nCONFIG_TICK_CPU_ACCOUNTING=y\nCONFIG_TIMER_OF=y\nCONFIG_TIMER_PROBE=y\nCONFIG_TINY_SRCU=y\nCONFIG_USE_GENERIC_EARLY_PRINTK_8250=y\nCONFIG_USE_OF=y\nCONFIG_WATCHDOG_CORE=y\nCONFIG_ZLIB_DEFLATE=y\nCONFIG_ZLIB_INFLATE=y\n"
  },
  {
    "path": "target/linux/realtek/rtl930x/target.mk",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\nARCH:=mips\nSUBTARGET:=rtl930x\nCPU_TYPE:=24kc\nBOARD:=realtek\nBOARDNAME:=Realtek MIPS RTL930X\n\nKERNEL_PATCHVER:=5.10\n\ndefine Target/Description\n\tBuild firmware images for Realtek RTL930x based boards.\nendef\n\n"
  },
  {
    "path": "target/linux/realtek/rtl931x/config-5.10",
    "content": "CONFIG_ARCH_32BIT_OFF_T=y\nCONFIG_ARCH_HIBERNATION_POSSIBLE=y\nCONFIG_ARCH_MMAP_RND_BITS_MAX=15\nCONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15\nCONFIG_ARCH_SUSPEND_POSSIBLE=y\nCONFIG_BLK_DEV_RAM=y\nCONFIG_BLK_DEV_RAM_COUNT=16\nCONFIG_BLK_DEV_RAM_SIZE=4096\nCONFIG_CEVT_R4K=y\nCONFIG_CLKDEV_LOOKUP=y\nCONFIG_CLKSRC_MMIO=y\nCONFIG_CLONE_BACKWARDS=y\nCONFIG_COMMON_CLK=y\nCONFIG_COMMON_CLK_BOSTON=y\nCONFIG_COMPAT_32BIT_TIME=y\nCONFIG_CONSOLE_LOGLEVEL_DEFAULT=15\nCONFIG_CPU_BIG_ENDIAN=y\nCONFIG_CPU_GENERIC_DUMP_TLB=y\nCONFIG_CPU_HAS_DIEI=y\nCONFIG_CPU_HAS_PREFETCH=y\nCONFIG_CPU_HAS_RIXI=y\nCONFIG_CPU_HAS_SYNC=y\nCONFIG_CPU_MIPS32=y\n# CONFIG_CPU_MIPS32_R1 is not set\nCONFIG_CPU_MIPS32_R2=y\nCONFIG_CPU_MIPSR2=y\nCONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y\nCONFIG_CPU_R4K_CACHE_TLB=y\nCONFIG_CPU_SUPPORTS_32BIT_KERNEL=y\nCONFIG_CPU_SUPPORTS_HIGHMEM=y\nCONFIG_CPU_SUPPORTS_MSA=y\nCONFIG_MIPS_MT=y\nCONFIG_MIPS_MT_FPAFF=y\nCONFIG_MIPS_MT_SMP=y\n# CONFIG_MIPS_NO_APPENDED_DTB is not set\nCONFIG_MIPS_NR_CPU_NR_MAP=4\nCONFIG_HIGHMEM=y\nCONFIG_CRYPTO_GF128MUL=y\nCONFIG_CRYPTO_LIB_POLY1305_RSIZE=2\nCONFIG_CRYPTO_NULL2=y\nCONFIG_CRYPTO_RNG2=y\nCONFIG_CSRC_R4K=y\nCONFIG_DEBUG_INFO=y\nCONFIG_DEBUG_SECTION_MISMATCH=y\nCONFIG_DMA_NONCOHERENT=y\nCONFIG_DTC=y\nCONFIG_EARLY_PRINTK=y\nCONFIG_FIXED_PHY=y\nCONFIG_FW_LOADER_PAGED_BUF=y\nCONFIG_GENERIC_ATOMIC64=y\nCONFIG_GENERIC_CLOCKEVENTS=y\nCONFIG_GENERIC_CMOS_UPDATE=y\nCONFIG_GENERIC_CPU_AUTOPROBE=y\nCONFIG_GENERIC_GETTIMEOFDAY=y\nCONFIG_GENERIC_IOMAP=y\nCONFIG_GENERIC_IRQ_CHIP=y\nCONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y\nCONFIG_GENERIC_IRQ_SHOW=y\nCONFIG_GENERIC_LIB_ASHLDI3=y\nCONFIG_GENERIC_LIB_ASHRDI3=y\nCONFIG_GENERIC_LIB_CMPDI2=y\nCONFIG_GENERIC_LIB_LSHRDI3=y\nCONFIG_GENERIC_LIB_UCMPDI2=y\nCONFIG_GENERIC_PCI_IOMAP=y\nCONFIG_GENERIC_PHY=y\nCONFIG_GENERIC_PINCONF=y\nCONFIG_GENERIC_PINCTRL_GROUPS=y\nCONFIG_GENERIC_PINMUX_FUNCTIONS=y\nCONFIG_GENERIC_SCHED_CLOCK=y\nCONFIG_GENERIC_SMP_IDLE_THREAD=y\nCONFIG_GENERIC_TIME_VSYSCALL=y\nCONFIG_GPIOLIB=y\nCONFIG_GPIOLIB_IRQCHIP=y\nCONFIG_GPIO_REALTEK_OTTO=y\nCONFIG_GPIO_GENERIC=y\nCONFIG_GPIO_RTL8231=y\nCONFIG_GRO_CELLS=y\nCONFIG_HANDLE_DOMAIN_IRQ=y\nCONFIG_HARDWARE_WATCHPOINTS=y\nCONFIG_HAS_DMA=y\nCONFIG_HAS_IOMEM=y\nCONFIG_HAS_IOPORT_MAP=y\nCONFIG_HIGH_RES_TIMERS=y\nCONFIG_HWMON=y\nCONFIG_HZ_PERIODIC=y\nCONFIG_I2C=y\nCONFIG_I2C_ALGOBIT=y\nCONFIG_I2C_BOARDINFO=y\nCONFIG_I2C_CHARDEV=y\nCONFIG_I2C_GPIO=y\nCONFIG_I2C_MUX=y\nCONFIG_I2C_MUX_RTL9300=y\nCONFIG_I2C_RTL9300=y\nCONFIG_I2C_SMBUS=y\nCONFIG_INITRAMFS_SOURCE=\"\"\nCONFIG_IRQCHIP=y\nCONFIG_IRQ_DOMAIN=y\nCONFIG_IRQ_FORCED_THREADING=y\nCONFIG_IRQ_MIPS_CPU=y\nCONFIG_IRQ_WORK=y\nCONFIG_JFFS2_ZLIB=y\nCONFIG_LEDS_GPIO=y\nCONFIG_LEGACY_PTYS=y\nCONFIG_LEGACY_PTY_COUNT=256\nCONFIG_LIBFDT=y\nCONFIG_LLD_VERSION=0\nCONFIG_LOCK_DEBUGGING_SUPPORT=y\nCONFIG_MARVELL_PHY=y\nCONFIG_MDIO_BUS=y\nCONFIG_MDIO_DEVICE=y\nCONFIG_MDIO_DEVRES=y\nCONFIG_MDIO_I2C=y\nCONFIG_MDIO_SMBUS=y\nCONFIG_MEMFD_CREATE=y\nCONFIG_MFD_SYSCON=y\nCONFIG_MIGRATION=y\nCONFIG_MIPS=y\nCONFIG_MIPS_ASID_BITS=8\nCONFIG_MIPS_ASID_SHIFT=0\nCONFIG_MIPS_CBPF_JIT=y\nCONFIG_MIPS_CLOCK_VSYSCALL=y\n# CONFIG_MIPS_CMDLINE_DTB_EXTEND is not set\n# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set\nCONFIG_MIPS_CMDLINE_FROM_DTB=y\n# CONFIG_MIPS_ELF_APPENDED_DTB is not set\nCONFIG_MIPS_L1_CACHE_SHIFT=5\nCONFIG_MIPS_LD_CAN_LINK_VDSO=y\n# CONFIG_MIPS_NO_APPENDED_DTB is not set\nCONFIG_MIPS_RAW_APPENDED_DTB=y\nCONFIG_MIPS_SPRAM=y\nCONFIG_MODULES_USE_ELF_REL=y\nCONFIG_MTD_CFI_ADV_OPTIONS=y\nCONFIG_MTD_CFI_GEOMETRY=y\nCONFIG_MTD_CMDLINE_PARTS=y\nCONFIG_MTD_JEDECPROBE=y\nCONFIG_MTD_SPI_NOR=y\nCONFIG_MTD_SPLIT_BRNIMAGE_FW=y\nCONFIG_MTD_SPLIT_EVA_FW=y\nCONFIG_MTD_SPLIT_FIRMWARE=y\nCONFIG_MTD_SPLIT_TPLINK_FW=y\nCONFIG_MTD_SPLIT_UIMAGE_FW=y\nCONFIG_NEED_DMA_MAP_STATE=y\nCONFIG_NEED_PER_CPU_KM=y\nCONFIG_NET_DEVLINK=y\nCONFIG_NET_DSA=y\nCONFIG_NET_DSA_RTL83XX=y\nCONFIG_NET_DSA_TAG_RTL83XX=y\nCONFIG_NET_DSA_TAG_TRAILER=y\nCONFIG_NET_RTL838X=y\nCONFIG_NET_SWITCHDEV=y\nCONFIG_NO_GENERIC_PCI_IOPORT_MAP=y\nCONFIG_NVMEM=y\nCONFIG_OF=y\nCONFIG_OF_ADDRESS=y\nCONFIG_OF_EARLY_FLATTREE=y\nCONFIG_OF_FLATTREE=y\nCONFIG_OF_GPIO=y\nCONFIG_OF_IRQ=y\nCONFIG_OF_KOBJ=y\nCONFIG_OF_MDIO=y\nCONFIG_OF_NET=y\nCONFIG_PCI_DRIVERS_LEGACY=y\nCONFIG_PERF_USE_VMALLOC=y\nCONFIG_PGTABLE_LEVELS=2\nCONFIG_PHYLIB=y\nCONFIG_PHYLINK=y\nCONFIG_PINCTRL=y\nCONFIG_POWER_RESET=y\nCONFIG_POWER_RESET_SYSCON=y\nCONFIG_RATIONAL=y\n# CONFIG_REALTEK_PHY is not set\nCONFIG_REALTEK_SOC_PHY=y\nCONFIG_REGMAP=y\nCONFIG_REGMAP_MMIO=y\nCONFIG_RESET_CONTROLLER=y\nCONFIG_RTL838X=y\n# CONFIG_RTL9300_TIMER is not set\nCONFIG_SENSORS_GPIO_FAN=y\nCONFIG_SENSORS_LM75=y\nCONFIG_SERIAL_MCTRL_GPIO=y\nCONFIG_SERIAL_OF_PLATFORM=y\nCONFIG_SFP=y\nCONFIG_SPI=y\nCONFIG_SPI_MASTER=y\nCONFIG_SPI_MEM=y\nCONFIG_SRCU=y\nCONFIG_SWPHY=y\nCONFIG_SYSCTL_EXCEPTION_TRACE=y\nCONFIG_SYS_HAS_CPU_MIPS32_R1=y\nCONFIG_SYS_HAS_CPU_MIPS32_R2=y\nCONFIG_SYS_HAS_EARLY_PRINTK=y\nCONFIG_SYS_SUPPORTS_32BIT_KERNEL=y\nCONFIG_SYS_SUPPORTS_ARBIT_HZ=y\nCONFIG_SYS_SUPPORTS_BIG_ENDIAN=y\nCONFIG_SYS_SUPPORTS_MIPS16=y\nCONFIG_TARGET_ISA_REV=2\nCONFIG_TICK_CPU_ACCOUNTING=y\nCONFIG_TIMER_OF=y\nCONFIG_TIMER_PROBE=y\nCONFIG_TINY_SRCU=y\n# CONFIG_USE_GENERIC_EARLY_PRINTK_8250 is not set\nCONFIG_USE_OF=y\nCONFIG_ZLIB_DEFLATE=y\nCONFIG_ZLIB_INFLATE=y\nCONFIG_FORCE_MAX_ZONEORDER=13\n# CONFIG_MIPS_VPE_LOADER is not set\nCONFIG_MIPS_CPU_SCACHE=y\nCONFIG_SPI_RTL838X=y\nCONFIG_MIPS_MT_SMP=y\nCONFIG_MIPS_CPC=y\nCONFIG_MIPS_CPS=y\nCONFIG_MIPS_PM=y\n# CONFIG_MIPS_CMP is not set\nCONFIG_MIPS_CPS_CPUIDLE=y\n# CONFIG_MIPS_CPS_NS16550_BOOL is not set\nCONFIG_SMP=y\nCONFIG_NR_CPUS=2\nCONFIG_RTL83XX=y\n# CONFIG_RTL838X is not set\n# CONFIG_RTL839X is not set\nCONFIG_RTL930X=y\nCONFIG_RTL931X=y\nCONFIG_REALTEK_OTTO_WDT=y\n"
  },
  {
    "path": "target/linux/realtek/rtl931x/target.mk",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\nARCH:=mips\nSUBTARGET:=rtl931x\nCPU_TYPE:=24kc\nBOARD:=realtek\nBOARDNAME:=Realtek MIPS RTL931X\n\nKERNEL_PATCHVER:=5.10\n\ndefine Target/Description\n\tBuild firmware images for Realtek RTL931x based boards.\nendef\n"
  },
  {
    "path": "target/linux/rockchip/Makefile",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n\ninclude $(TOPDIR)/rules.mk\n\nBOARD:=rockchip\nBOARDNAME:=Rockchip\nFEATURES:=ext4 audio usb usbgadget display gpio fpu pci pcie rootfs-part boot-part squashfs\nSUBTARGETS:=armv8\n\nKERNEL_PATCHVER=5.10\n\ndefine Target/Description\n\tBuild firmware image for Rockchip SoC devices.\nendef\n\ninclude $(INCLUDE_DIR)/target.mk\n\nDEFAULT_PACKAGES += uboot-envtools partx-utils e2fsprogs mkf2fs kmod-gpio-button-hotplug\n\nKERNELNAME:=Image dtbs\n\n$(eval $(call BuildTarget))\n"
  },
  {
    "path": "target/linux/rockchip/armv8/base-files/etc/board.d/01_leds",
    "content": "\n. /lib/functions/leds.sh\n. /lib/functions/uci-defaults.sh\n\nboard=$(board_name)\nboardname=\"${board##*,}\"\n\nboard_config_update\n\ncase $board in\nfriendlyarm,nanopi-r2s| \\\nxunlong,orangepi-r1-plus| \\\nxunlong,orangepi-r1-plus-lts)\n\tucidef_set_led_netdev \"wan\" \"WAN\" \"$boardname:green:wan\" \"eth0\"\n\tucidef_set_led_netdev \"lan\" \"LAN\" \"$boardname:green:lan\" \"eth1\"\n\t;;\nfriendlyarm,nanopi-r4s)\n\tucidef_set_led_netdev \"wan\" \"WAN\" \"green:wan\" \"eth0\"\n\tucidef_set_led_netdev \"lan\" \"LAN\" \"green:lan\" \"eth1\"\n\t;;\nesac\n\nboard_config_flush\n\nexit 0\n"
  },
  {
    "path": "target/linux/rockchip/armv8/base-files/etc/board.d/02_network",
    "content": "\n. /lib/functions/uci-defaults.sh\n. /lib/functions/system.sh\n\nrockchip_setup_interfaces()\n{\n\tlocal board=\"$1\"\n\n\tcase \"$board\" in\n\tfriendlyarm,nanopi-r2s|\\\n\tfriendlyarm,nanopi-r4s|\\\n\txunlong,orangepi-r1-plus|\\\n\txunlong,orangepi-r1-plus-lts)\n\t\tucidef_set_interfaces_lan_wan 'eth1' 'eth0'\n\t\t;;\n\t*)\n\t\tucidef_set_interface_lan 'eth0'\n\t\t;;\n\tesac\n}\n\nnanopi_r2s_generate_mac()\n{\n\tlocal sd_hash=$(sha256sum /sys/class/block/mmcblk0/device/cid)\n\tlocal mac_base=$(macaddr_canonicalize \"$(echo \"${sd_hash}\" | dd bs=1 count=12 2>/dev/null)\")\n\techo \"$(macaddr_unsetbit_mc \"$(macaddr_setbit_la \"${mac_base}\")\")\"\n}\n\nrockchip_setup_macs()\n{\n\tlocal board=\"$1\"\n\tlocal lan_mac=\"\"\n\tlocal wan_mac=\"\"\n\tlocal label_mac=\"\"\n\n\tcase \"$board\" in\n\txunlong,orangepi-r1-plus|\\\n\txunlong,orangepi-r1-plus-lts)\n\t\tlan_mac=$(cat /sys/class/net/eth1/address)\n                wan_mac=$(macaddr_add \"$lan_mac\" -1)\n\t\t;;\n\tfriendlyarm,nanopi-r2s)\n\t\twan_mac=$(nanopi_r2s_generate_mac)\n\t\tlan_mac=$(macaddr_add \"$wan_mac\" 1)\n\t\t;;\n\tfriendlyarm,nanopi-r4s)\n\t\twan_mac=$(get_mac_binary \"/sys/bus/i2c/devices/2-0051/eeprom\" 0xfa)\n\t\tlan_mac=$(macaddr_setbit_la \"$wan_mac\")\n\t\t;;\n\tesac\n\n\t[ -n \"$lan_mac\" ] && ucidef_set_interface_macaddr \"lan\" $lan_mac\n\t[ -n \"$wan_mac\" ] && ucidef_set_interface_macaddr \"wan\" $wan_mac\n\t[ -n \"$label_mac\" ] && ucidef_set_label_macaddr $label_mac\n}\n\nboard_config_update\nboard=$(board_name)\nrockchip_setup_interfaces $board\nrockchip_setup_macs $board\nboard_config_flush\n\nexit 0\n"
  },
  {
    "path": "target/linux/rockchip/armv8/base-files/etc/hotplug.d/net/40-net-smp-affinity",
    "content": "#!/bin/sh\n\n[ \"$ACTION\" = add ] || exit\n\nget_device_irq() {\n\tlocal device=\"$1\"\n\n\tlocal line=$(grep -m 1 \"${device}\\$\" /proc/interrupts)\n\techo ${line} | sed 's/:.*//'\n}\n\nset_interface_core() {\n\tlocal core_mask=\"$1\"\n\tlocal interface=\"$2\"\n\tlocal device=\"$3\"\n\n\t[ -z \"${device}\" ] && device=\"$interface\"\n\n\tlocal irq=$(get_device_irq \"$device\")\n\n\techo \"${core_mask}\" > /proc/irq/${irq}/smp_affinity\n}\n\ncase \"$(board_name)\" in\nfriendlyarm,nanopi-r2s|\\\nxunlong,orangepi-r1-plus|\\\nxunlong,orangepi-r1-plus-lts)\n\tset_interface_core 2 \"eth0\"\n\tset_interface_core 4 \"eth1\" \"xhci-hcd:usb3\"\n\t;;\nfriendlyarm,nanopi-r4s)\n\tset_interface_core 10 \"eth0\"\n\tset_interface_core 20 \"eth1\"\n\t;;\nesac\n\n"
  },
  {
    "path": "target/linux/rockchip/armv8/base-files/lib/preinit/79_move_config",
    "content": "move_config() {\n\tlocal partdev\n\n\t. /lib/upgrade/common.sh\n\n\tif export_bootdevice && export_partdevice partdev 1; then\n\t\tif mount -o rw,noatime \"/dev/$partdev\" /mnt; then\n\t\t\tif [ -f \"/mnt/$BACKUP_FILE\" ]; then\n\t\t\t\tmv -f \"/mnt/$BACKUP_FILE\" /\n\t\t\tfi\n\t\t\tumount /mnt\n\t\tfi\n\tfi\n}\n\nboot_hook_add preinit_mount_root move_config\n"
  },
  {
    "path": "target/linux/rockchip/armv8/base-files/lib/upgrade/platform.sh",
    "content": "platform_check_image() {\n\tlocal diskdev partdev diff\n\n\texport_bootdevice && export_partdevice diskdev 0 || {\n\t\techo \"Unable to determine upgrade device\"\n\t\treturn 1\n\t}\n\n\tget_partitions \"/dev/$diskdev\" bootdisk\n\n\t#extract the boot sector from the image\n\tget_image \"$@\" | dd of=/tmp/image.bs count=1 bs=512b 2>/dev/null\n\n\tget_partitions /tmp/image.bs image\n\n\t#compare tables\n\tdiff=\"$(grep -F -x -v -f /tmp/partmap.bootdisk /tmp/partmap.image)\"\n\n\trm -f /tmp/image.bs /tmp/partmap.bootdisk /tmp/partmap.image\n\n\tif [ -n \"$diff\" ]; then\n\t\techo \"Partition layout has changed. Full image will be written.\"\n\t\task_bool 0 \"Abort\" && exit 1\n\t\treturn 0\n\tfi\n}\n\nplatform_copy_config() {\n\tlocal partdev\n\n\tif export_partdevice partdev 1; then\n\t\tmount -o rw,noatime \"/dev/$partdev\" /mnt\n\t\tcp -af \"$UPGRADE_BACKUP\" \"/mnt/$BACKUP_FILE\"\n\t\tumount /mnt\n\tfi\n}\n\nplatform_do_upgrade() {\n\tlocal diskdev partdev diff\n\n\texport_bootdevice && export_partdevice diskdev 0 || {\n\t\techo \"Unable to determine upgrade device\"\n\t\treturn 1\n\t}\n\n\tsync\n\n\tif [ \"$UPGRADE_OPT_SAVE_PARTITIONS\" = \"1\" ]; then\n\t\tget_partitions \"/dev/$diskdev\" bootdisk\n\n\t\t#extract the boot sector from the image\n\t\tget_image \"$@\" | dd of=/tmp/image.bs count=1 bs=512b\n\n\t\tget_partitions /tmp/image.bs image\n\n\t\t#compare tables\n\t\tdiff=\"$(grep -F -x -v -f /tmp/partmap.bootdisk /tmp/partmap.image)\"\n\telse\n\t\tdiff=1\n\tfi\n\n\tif [ -n \"$diff\" ]; then\n\t\tget_image \"$@\" | dd of=\"/dev/$diskdev\" bs=4096 conv=fsync\n\n\t\t# Separate removal and addtion is necessary; otherwise, partition 1\n\t\t# will be missing if it overlaps with the old partition 2\n\t\tpartx -d - \"/dev/$diskdev\"\n\t\tpartx -a - \"/dev/$diskdev\"\n\n\t\treturn 0\n\tfi\n\n\t#iterate over each partition from the image and write it to the boot disk\n\twhile read part start size; do\n\t\tif export_partdevice partdev $part; then\n\t\t\techo \"Writing image to /dev/$partdev...\"\n\t\t\tget_image \"$@\" | dd of=\"/dev/$partdev\" ibs=\"512\" obs=1M skip=\"$start\" count=\"$size\" conv=fsync\n\t\telse\n\t\t\techo \"Unable to find partition $part device, skipped.\"\n\t\tfi\n\tdone < /tmp/partmap.image\n\n\t#copy partition uuid\n\techo \"Writing new UUID to /dev/$diskdev...\"\n\tget_image \"$@\" | dd of=\"/dev/$diskdev\" bs=1 skip=440 count=4 seek=440 conv=fsync\n}\n"
  },
  {
    "path": "target/linux/rockchip/armv8/config-5.10",
    "content": "CONFIG_64BIT=y\nCONFIG_ARCH_DMA_ADDR_T_64BIT=y\nCONFIG_ARCH_HIBERNATION_POSSIBLE=y\nCONFIG_ARCH_KEEP_MEMBLOCK=y\nCONFIG_ARCH_MMAP_RND_BITS=18\nCONFIG_ARCH_MMAP_RND_BITS_MAX=33\nCONFIG_ARCH_MMAP_RND_BITS_MIN=18\nCONFIG_ARCH_MMAP_RND_COMPAT_BITS=11\nCONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11\nCONFIG_ARCH_PROC_KCORE_TEXT=y\nCONFIG_ARCH_ROCKCHIP=y\nCONFIG_ARCH_SELECT_MEMORY_MODEL=y\nCONFIG_ARCH_SPARSEMEM_DEFAULT=y\nCONFIG_ARCH_SPARSEMEM_ENABLE=y\nCONFIG_ARCH_STACKWALK=y\nCONFIG_ARCH_SUSPEND_POSSIBLE=y\nCONFIG_ARC_EMAC_CORE=y\nCONFIG_ARM64=y\nCONFIG_ARM64_4K_PAGES=y\nCONFIG_ARM64_CNP=y\nCONFIG_ARM64_ERRATUM_819472=y\nCONFIG_ARM64_ERRATUM_824069=y\nCONFIG_ARM64_ERRATUM_826319=y\nCONFIG_ARM64_ERRATUM_827319=y\nCONFIG_ARM64_ERRATUM_832075=y\nCONFIG_ARM64_ERRATUM_843419=y\nCONFIG_ARM64_ERRATUM_845719=y\nCONFIG_ARM64_ERRATUM_858921=y\nCONFIG_ARM64_HW_AFDBM=y\nCONFIG_ARM64_MODULE_PLTS=y\nCONFIG_ARM64_PAGE_SHIFT=12\nCONFIG_ARM64_PAN=y\nCONFIG_ARM64_PA_BITS=48\nCONFIG_ARM64_PA_BITS_48=y\nCONFIG_ARM64_PTR_AUTH=y\nCONFIG_ARM64_RAS_EXTN=y\nCONFIG_ARM64_SVE=y\n# CONFIG_ARM64_SW_TTBR0_PAN is not set\nCONFIG_ARM64_TAGGED_ADDR_ABI=y\nCONFIG_ARM64_UAO=y\nCONFIG_ARM64_VA_BITS=48\n# CONFIG_ARM64_VA_BITS_39 is not set\nCONFIG_ARM64_VA_BITS_48=y\nCONFIG_ARM64_VHE=y\nCONFIG_ARM64_WORKAROUND_CLEAN_CACHE=y\n# CONFIG_ARMV8_DEPRECATED is not set\nCONFIG_ARM_AMBA=y\nCONFIG_ARM_ARCH_TIMER=y\nCONFIG_ARM_ARCH_TIMER_EVTSTREAM=y\nCONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y\nCONFIG_ARM_CPUIDLE=y\nCONFIG_ARM_GIC=y\nCONFIG_ARM_GIC_V2M=y\nCONFIG_ARM_GIC_V3=y\nCONFIG_ARM_GIC_V3_ITS=y\nCONFIG_ARM_GIC_V3_ITS_PCI=y\nCONFIG_ARM_MHU=y\nCONFIG_ARM_PSCI_CPUIDLE=y\nCONFIG_ARM_PSCI_CPUIDLE_DOMAIN=y\nCONFIG_ARM_PSCI_FW=y\nCONFIG_ARM_RK3328_DMC_DEVFREQ=y\n# CONFIG_ARM_RK3399_DMC_DEVFREQ is not set\n# CONFIG_ARM_SCMI_PROTOCOL is not set\nCONFIG_ARM_SCPI_CPUFREQ=y\nCONFIG_ARM_SCPI_POWER_DOMAIN=y\nCONFIG_ARM_SCPI_PROTOCOL=y\nCONFIG_ARM_SMMU=y\nCONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT=y\n# CONFIG_ARM_SMMU_LEGACY_DT_BINDINGS is not set\nCONFIG_ARM_SMMU_V3=y\n# CONFIG_ARM_SMMU_V3_SVA is not set\nCONFIG_AUDIT_ARCH_COMPAT_GENERIC=y\nCONFIG_BACKLIGHT_CLASS_DEVICE=y\nCONFIG_BACKLIGHT_GPIO=y\nCONFIG_BACKLIGHT_PWM=y\nCONFIG_BLK_DEV_BSG=y\nCONFIG_BLK_DEV_BSGLIB=y\n# CONFIG_BLK_DEV_INITRD is not set\nCONFIG_BLK_DEV_INTEGRITY=y\nCONFIG_BLK_DEV_INTEGRITY_T10=y\nCONFIG_BLK_DEV_LOOP=y\nCONFIG_BLK_DEV_NVME=y\nCONFIG_BLK_DEV_PCIESSD_MTIP32XX=y\nCONFIG_BLK_DEV_SD=y\nCONFIG_BLK_MQ_PCI=y\nCONFIG_BLK_PM=y\nCONFIG_BLK_SCSI_REQUEST=y\nCONFIG_BLOCK_COMPAT=y\nCONFIG_BRCMSTB_GISB_ARB=y\nCONFIG_BSD_PROCESS_ACCT=y\nCONFIG_BSD_PROCESS_ACCT_V3=y\n# CONFIG_CHARGER_BQ25980 is not set\nCONFIG_CHARGER_GPIO=y\nCONFIG_CLKDEV_LOOKUP=y\nCONFIG_CLKSRC_MMIO=y\nCONFIG_CLK_PX30=y\nCONFIG_CLK_RK3036=y\nCONFIG_CLK_RK312X=y\nCONFIG_CLK_RK3188=y\nCONFIG_CLK_RK322X=y\nCONFIG_CLK_RK3308=y\nCONFIG_CLK_RK3328=y\nCONFIG_CLK_RK3368=y\nCONFIG_CLK_RK3399=y\nCONFIG_CLK_RV110X=y\nCONFIG_CLONE_BACKWARDS=y\nCONFIG_CMA=y\nCONFIG_CMA_ALIGNMENT=8\nCONFIG_CMA_AREAS=7\n# CONFIG_CMA_DEBUG is not set\n# CONFIG_CMA_DEBUGFS is not set\nCONFIG_CMA_SIZE_MBYTES=5\n# CONFIG_CMA_SIZE_SEL_MAX is not set\nCONFIG_CMA_SIZE_SEL_MBYTES=y\n# CONFIG_CMA_SIZE_SEL_MIN is not set\n# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set\nCONFIG_COMMON_CLK=y\nCONFIG_COMMON_CLK_RK808=y\nCONFIG_COMMON_CLK_ROCKCHIP=y\nCONFIG_COMMON_CLK_SCPI=y\nCONFIG_COMPAT=y\nCONFIG_COMPAT_32BIT_TIME=y\nCONFIG_COMPAT_BINFMT_ELF=y\nCONFIG_COMPAT_NETLINK_MESSAGES=y\nCONFIG_COMPAT_OLD_SIGACTION=y\nCONFIG_CONFIGFS_FS=y\nCONFIG_CONSOLE_TRANSLATIONS=y\nCONFIG_CONTIG_ALLOC=y\nCONFIG_CPUFREQ_DT=y\nCONFIG_CPUFREQ_DT_PLATDEV=y\nCONFIG_CPU_FREQ=y\n# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set\nCONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y\nCONFIG_CPU_FREQ_GOV_ATTR_SET=y\n# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set\n# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set\nCONFIG_CPU_FREQ_GOV_PERFORMANCE=y\nCONFIG_CPU_FREQ_GOV_POWERSAVE=y\nCONFIG_CPU_FREQ_GOV_SCHEDUTIL=y\n# CONFIG_CPU_FREQ_GOV_USERSPACE is not set\nCONFIG_CPU_FREQ_STAT=y\nCONFIG_CPU_IDLE=y\nCONFIG_CPU_IDLE_GOV_MENU=y\nCONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y\nCONFIG_CPU_ISOLATION=y\nCONFIG_CPU_PM=y\nCONFIG_CPU_RMAP=y\nCONFIG_CPU_THERMAL=y\nCONFIG_CRASH_CORE=y\nCONFIG_CRASH_DUMP=y\nCONFIG_CRC16=y\n# CONFIG_CRC32_SARWATE is not set\nCONFIG_CRC32_SLICEBY8=y\nCONFIG_CRC_T10DIF=y\nCONFIG_CROSS_MEMORY_ATTACH=y\nCONFIG_CRYPTO_CRC32=y\nCONFIG_CRYPTO_CRC32C=y\nCONFIG_CRYPTO_CRCT10DIF=y\n# CONFIG_CRYPTO_DEV_ROCKCHIP is not set\nCONFIG_CRYPTO_RNG2=y\nCONFIG_DCACHE_WORD_ACCESS=y\nCONFIG_DEBUG_BUGVERBOSE=y\n# CONFIG_DEVFREQ_GOV_PASSIVE is not set\nCONFIG_DEVFREQ_GOV_PERFORMANCE=y\nCONFIG_DEVFREQ_GOV_POWERSAVE=y\nCONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y\nCONFIG_DEVFREQ_GOV_USERSPACE=y\n# CONFIG_DEVFREQ_THERMAL is not set\nCONFIG_DEVMEM=y\n# CONFIG_DEVPORT is not set\nCONFIG_DMADEVICES=y\nCONFIG_DMA_CMA=y\nCONFIG_DMA_DIRECT_REMAP=y\nCONFIG_DMA_ENGINE=y\nCONFIG_DMA_OF=y\nCONFIG_DMA_OPS=y\nCONFIG_DMA_REMAP=y\nCONFIG_DMA_SHARED_BUFFER=y\nCONFIG_DNOTIFY=y\n# CONFIG_DRM_ROCKCHIP is not set\nCONFIG_DTC=y\nCONFIG_DT_IDLE_STATES=y\nCONFIG_DUMMY_CONSOLE=y\nCONFIG_DWMAC_DWC_QOS_ETH=y\nCONFIG_DWMAC_GENERIC=y\nCONFIG_DWMAC_ROCKCHIP=y\nCONFIG_EDAC_SUPPORT=y\nCONFIG_EEPROM_AT24=y\nCONFIG_EMAC_ROCKCHIP=y\nCONFIG_ENABLE_MUST_CHECK=y\nCONFIG_ENERGY_MODEL=y\nCONFIG_EXT4_FS=y\nCONFIG_EXT4_FS_POSIX_ACL=y\nCONFIG_EXTCON=y\nCONFIG_F2FS_FS=y\nCONFIG_FANOTIFY=y\nCONFIG_FHANDLE=y\nCONFIG_FIXED_PHY=y\nCONFIG_FIX_EARLYCON_MEM=y\n# CONFIG_FLATMEM_MANUAL is not set\n# CONFIG_FORTIFY_SOURCE is not set\nCONFIG_FRAME_POINTER=y\nCONFIG_FRAME_WARN=2048\nCONFIG_FS_IOMAP=y\nCONFIG_FS_MBCACHE=y\nCONFIG_FS_POSIX_ACL=y\nCONFIG_FW_LOADER_PAGED_BUF=y\nCONFIG_GENERIC_ALLOCATOR=y\nCONFIG_GENERIC_ARCH_TOPOLOGY=y\nCONFIG_GENERIC_BUG=y\nCONFIG_GENERIC_BUG_RELATIVE_POINTERS=y\nCONFIG_GENERIC_CLOCKEVENTS=y\nCONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y\nCONFIG_GENERIC_CPU_AUTOPROBE=y\nCONFIG_GENERIC_CPU_VULNERABILITIES=y\nCONFIG_GENERIC_CSUM=y\nCONFIG_GENERIC_EARLY_IOREMAP=y\nCONFIG_GENERIC_GETTIMEOFDAY=y\nCONFIG_GENERIC_IDLE_POLL_SETUP=y\nCONFIG_GENERIC_IRQ_CHIP=y\nCONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y\nCONFIG_GENERIC_IRQ_MIGRATION=y\nCONFIG_GENERIC_IRQ_MULTI_HANDLER=y\nCONFIG_GENERIC_IRQ_SHOW=y\nCONFIG_GENERIC_IRQ_SHOW_LEVEL=y\nCONFIG_GENERIC_MSI_IRQ=y\nCONFIG_GENERIC_MSI_IRQ_DOMAIN=y\nCONFIG_GENERIC_PCI_IOMAP=y\nCONFIG_GENERIC_PHY=y\nCONFIG_GENERIC_PINCONF=y\nCONFIG_GENERIC_SCHED_CLOCK=y\nCONFIG_GENERIC_SMP_IDLE_THREAD=y\nCONFIG_GENERIC_STRNCPY_FROM_USER=y\nCONFIG_GENERIC_STRNLEN_USER=y\nCONFIG_GENERIC_TIME_VSYSCALL=y\nCONFIG_GPIOLIB=y\nCONFIG_GPIOLIB_IRQCHIP=y\nCONFIG_GPIO_DWAPB=y\nCONFIG_GPIO_GENERIC=y\nCONFIG_GPIO_GENERIC_PLATFORM=y\nCONFIG_HANDLE_DOMAIN_IRQ=y\n# CONFIG_HARDENED_USERCOPY is not set\nCONFIG_HARDIRQS_SW_RESEND=y\nCONFIG_HAS_DMA=y\nCONFIG_HAS_IOMEM=y\nCONFIG_HAS_IOPORT_MAP=y\nCONFIG_HID=y\nCONFIG_HID_GENERIC=y\n# CONFIG_HISI_HIKEY_USB is not set\nCONFIG_HOLES_IN_ZONE=y\nCONFIG_HOTPLUG_CPU=y\nCONFIG_HOTPLUG_PCI=y\n# CONFIG_HOTPLUG_PCI_CPCI is not set\n# CONFIG_HOTPLUG_PCI_PCIE is not set\n# CONFIG_HOTPLUG_PCI_SHPC is not set\nCONFIG_HUGETLBFS=y\nCONFIG_HUGETLB_PAGE=y\nCONFIG_HWMON=y\nCONFIG_HWSPINLOCK=y\nCONFIG_HW_CONSOLE=y\nCONFIG_HW_RANDOM=y\nCONFIG_HW_RANDOM_ROCKCHIP=y\nCONFIG_I2C=y\nCONFIG_I2C_BOARDINFO=y\nCONFIG_I2C_CHARDEV=y\nCONFIG_I2C_COMPAT=y\nCONFIG_I2C_HELPER_AUTO=y\nCONFIG_I2C_RK3X=y\nCONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000\nCONFIG_INDIRECT_PIO=y\nCONFIG_INPUT=y\nCONFIG_INPUT_EVDEV=y\nCONFIG_INPUT_FF_MEMLESS=y\nCONFIG_INPUT_KEYBOARD=y\nCONFIG_INPUT_LEDS=y\nCONFIG_INPUT_MATRIXKMAP=y\n# CONFIG_INPUT_MISC is not set\n# CONFIG_INPUT_RK805_PWRKEY is not set\nCONFIG_IOMMU_API=y\n# CONFIG_IOMMU_DEBUGFS is not set\n# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set\nCONFIG_IOMMU_DMA=y\nCONFIG_IOMMU_IOVA=y\nCONFIG_IOMMU_IO_PGTABLE=y\n# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set\nCONFIG_IOMMU_IO_PGTABLE_LPAE=y\n# CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST is not set\nCONFIG_IOMMU_SUPPORT=y\n# CONFIG_IO_STRICT_DEVMEM is not set\nCONFIG_IO_URING=y\nCONFIG_IRQCHIP=y\nCONFIG_IRQ_DOMAIN=y\nCONFIG_IRQ_DOMAIN_HIERARCHY=y\nCONFIG_IRQ_FORCED_THREADING=y\nCONFIG_IRQ_MSI_IOMMU=y\nCONFIG_IRQ_TIME_ACCOUNTING=y\nCONFIG_IRQ_WORK=y\nCONFIG_JBD2=y\nCONFIG_JFFS2_ZLIB=y\nCONFIG_JUMP_LABEL=y\nCONFIG_KALLSYMS=y\nCONFIG_KEXEC_CORE=y\nCONFIG_KEXEC_FILE=y\nCONFIG_KSM=y\n# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set\nCONFIG_LEDS_GPIO=y\n# CONFIG_LEDS_LP50XX is not set\nCONFIG_LEDS_PWM=y\nCONFIG_LEDS_SYSCON=y\nCONFIG_LEDS_TRIGGER_CPU=y\nCONFIG_LEDS_TRIGGER_PANIC=y\nCONFIG_LEGACY_PTYS=y\nCONFIG_LEGACY_PTY_COUNT=16\nCONFIG_LIBCRC32C=y\nCONFIG_LIBFDT=y\nCONFIG_LOCALVERSION_AUTO=y\nCONFIG_LOCK_DEBUGGING_SUPPORT=y\nCONFIG_LOCK_SPIN_ON_OWNER=y\nCONFIG_LOG_BUF_SHIFT=19\nCONFIG_MAGIC_SYSRQ=y\nCONFIG_MAGIC_SYSRQ_SERIAL=y\nCONFIG_MAILBOX=y\n# CONFIG_MAILBOX_TEST is not set\nCONFIG_MANDATORY_FILE_LOCKING=y\nCONFIG_MDIO_BUS=y\nCONFIG_MDIO_BUS_MUX=y\nCONFIG_MDIO_BUS_MUX_GPIO=y\nCONFIG_MDIO_BUS_MUX_MMIOREG=y\nCONFIG_MDIO_DEVICE=y\nCONFIG_MEMFD_CREATE=y\nCONFIG_MEMORY_ISOLATION=y\nCONFIG_MFD_CORE=y\n# CONFIG_MFD_KHADAS_MCU is not set\nCONFIG_MFD_RK808=y\n# CONFIG_MFD_ROHM_BD71828 is not set\nCONFIG_MFD_SYSCON=y\nCONFIG_MIGRATION=y\nCONFIG_MMC=y\nCONFIG_MMC_BLOCK=y\nCONFIG_MMC_BLOCK_MINORS=32\nCONFIG_MMC_CQHCI=y\nCONFIG_MMC_DW=y\n# CONFIG_MMC_DW_BLUEFIELD is not set\n# CONFIG_MMC_DW_EXYNOS is not set\n# CONFIG_MMC_DW_HI3798CV200 is not set\n# CONFIG_MMC_DW_K3 is not set\n# CONFIG_MMC_DW_PCI is not set\nCONFIG_MMC_DW_PLTFM=y\nCONFIG_MMC_DW_ROCKCHIP=y\nCONFIG_MMC_SDHCI=y\nCONFIG_MMC_SDHCI_OF_ARASAN=y\nCONFIG_MMC_SDHCI_OF_DWCMSHC=y\n# CONFIG_MMC_SDHCI_PCI is not set\nCONFIG_MMC_SDHCI_PLTFM=y\nCONFIG_MODULES_USE_ELF_RELA=y\nCONFIG_MOTORCOMM_PHY=y\nCONFIG_MQ_IOSCHED_DEADLINE=y\n# CONFIG_MTD_CFI is not set\nCONFIG_MTD_CMDLINE_PARTS=y\n# CONFIG_MTD_COMPLEX_MAPPINGS is not set\nCONFIG_MTD_SPI_NOR=y\nCONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y\nCONFIG_MTD_SPLIT_FIRMWARE=y\nCONFIG_MUTEX_SPIN_ON_OWNER=y\nCONFIG_NEED_DMA_MAP_STATE=y\nCONFIG_NEED_SG_DMA_LENGTH=y\nCONFIG_NET_FLOW_LIMIT=y\nCONFIG_NLS=y\nCONFIG_NLS_ISO8859_1=y\nCONFIG_NOP_USB_XCEIV=y\nCONFIG_NO_HZ_COMMON=y\nCONFIG_NO_HZ_IDLE=y\nCONFIG_NR_CPUS=256\nCONFIG_NVMEM=y\nCONFIG_NVMEM_SYSFS=y\nCONFIG_NVME_CORE=y\n# CONFIG_NVME_HWMON is not set\n# CONFIG_NVME_MULTIPATH is not set\n# CONFIG_NVME_TCP is not set\nCONFIG_OF=y\nCONFIG_OF_ADDRESS=y\nCONFIG_OF_DYNAMIC=y\nCONFIG_OF_EARLY_FLATTREE=y\nCONFIG_OF_FLATTREE=y\nCONFIG_OF_GPIO=y\nCONFIG_OF_IOMMU=y\nCONFIG_OF_IRQ=y\nCONFIG_OF_KOBJ=y\nCONFIG_OF_MDIO=y\nCONFIG_OF_NET=y\nCONFIG_OF_OVERLAY=y\nCONFIG_OF_RESOLVE=y\nCONFIG_OLD_SIGSUSPEND3=y\n# CONFIG_OVERLAY_FS_XINO_AUTO is not set\nCONFIG_PADATA=y\nCONFIG_PAGE_POOL=y\n# CONFIG_PANIC_ON_OOPS is not set\nCONFIG_PANIC_ON_OOPS_VALUE=0\nCONFIG_PANIC_TIMEOUT=0\n# CONFIG_PARTITION_ADVANCED is not set\nCONFIG_PARTITION_PERCPU=y\nCONFIG_PCI=y\nCONFIG_PCIEAER=y\nCONFIG_PCIEASPM=y\nCONFIG_PCIEASPM_DEFAULT=y\n# CONFIG_PCIEASPM_PERFORMANCE is not set\n# CONFIG_PCIEASPM_POWERSAVE is not set\n# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set\nCONFIG_PCIEPORTBUS=y\nCONFIG_PCIE_PME=y\nCONFIG_PCIE_ROCKCHIP=y\nCONFIG_PCIE_ROCKCHIP_HOST=y\nCONFIG_PCI_DOMAINS=y\nCONFIG_PCI_DOMAINS_GENERIC=y\nCONFIG_PCI_MSI=y\nCONFIG_PCI_MSI_IRQ_DOMAIN=y\nCONFIG_PCI_STUB=y\nCONFIG_PCS_XPCS=y\nCONFIG_PGTABLE_LEVELS=4\nCONFIG_PHYLIB=y\nCONFIG_PHYLINK=y\nCONFIG_PHYS_ADDR_T_64BIT=y\nCONFIG_PHY_ROCKCHIP_DP=y\n# CONFIG_PHY_ROCKCHIP_DPHY_RX0 is not set\nCONFIG_PHY_ROCKCHIP_EMMC=y\n# CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY is not set\n# CONFIG_PHY_ROCKCHIP_INNO_HDMI is not set\nCONFIG_PHY_ROCKCHIP_INNO_USB2=y\n# CONFIG_PHY_ROCKCHIP_INNO_USB3 is not set\nCONFIG_PHY_ROCKCHIP_PCIE=y\nCONFIG_PHY_ROCKCHIP_TYPEC=y\nCONFIG_PHY_ROCKCHIP_USB=y\nCONFIG_PINCTRL=y\n# CONFIG_PINCTRL_RK805 is not set\nCONFIG_PINCTRL_ROCKCHIP=y\n# CONFIG_PINCTRL_SINGLE is not set\nCONFIG_PL330_DMA=y\nCONFIG_PLATFORM_MHU=y\nCONFIG_PM=y\nCONFIG_PM_CLK=y\nCONFIG_PM_DEVFREQ=y\n# CONFIG_PM_DEVFREQ_EVENT is not set\nCONFIG_PM_GENERIC_DOMAINS=y\nCONFIG_PM_GENERIC_DOMAINS_OF=y\nCONFIG_PM_OPP=y\nCONFIG_POWER_RESET=y\nCONFIG_POWER_SUPPLY=y\nCONFIG_POWER_SUPPLY_HWMON=y\nCONFIG_PREEMPT=y\nCONFIG_PREEMPTION=y\nCONFIG_PREEMPT_COUNT=y\n# CONFIG_PREEMPT_NONE is not set\nCONFIG_PREEMPT_RCU=y\nCONFIG_PRINTK_TIME=y\n# CONFIG_PRINT_QUOTA_WARNING is not set\nCONFIG_PROC_PAGE_MONITOR=y\nCONFIG_PROC_VMCORE=y\nCONFIG_PWM=y\nCONFIG_PWM_ROCKCHIP=y\nCONFIG_PWM_SYSFS=y\n# CONFIG_QFMT_V1 is not set\n# CONFIG_QFMT_V2 is not set\nCONFIG_QUEUED_RWLOCKS=y\nCONFIG_QUEUED_SPINLOCKS=y\nCONFIG_QUOTA=y\nCONFIG_QUOTACTL=y\n# CONFIG_QUOTA_NETLINK_INTERFACE is not set\nCONFIG_RAID_ATTRS=y\nCONFIG_RANDOMIZE_BASE=y\nCONFIG_RANDOMIZE_MODULE_REGION_FULL=y\nCONFIG_RAS=y\nCONFIG_RATIONAL=y\n# CONFIG_RAVE_SP_CORE is not set\nCONFIG_RCU_TRACE=y\nCONFIG_REALTEK_PHY=y\nCONFIG_REGMAP=y\nCONFIG_REGMAP_I2C=y\nCONFIG_REGMAP_IRQ=y\nCONFIG_REGMAP_MMIO=y\nCONFIG_REGULATOR=y\nCONFIG_REGULATOR_FAN53555=y\nCONFIG_REGULATOR_FIXED_VOLTAGE=y\nCONFIG_REGULATOR_GPIO=y\nCONFIG_REGULATOR_PWM=y\nCONFIG_REGULATOR_RK808=y\n# CONFIG_REGULATOR_RT4801 is not set\n# CONFIG_REGULATOR_RTMV20 is not set\nCONFIG_RELOCATABLE=y\nCONFIG_RESET_CONTROLLER=y\nCONFIG_RFS_ACCEL=y\nCONFIG_ROCKCHIP_EFUSE=y\nCONFIG_ROCKCHIP_GRF=y\nCONFIG_ROCKCHIP_IODOMAIN=y\nCONFIG_ROCKCHIP_IOMMU=y\nCONFIG_ROCKCHIP_MBOX=y\n# CONFIG_ROCKCHIP_OTP is not set\nCONFIG_ROCKCHIP_PHY=y\nCONFIG_ROCKCHIP_PM_DOMAINS=y\n# CONFIG_ROCKCHIP_SARADC is not set\nCONFIG_ROCKCHIP_THERMAL=y\nCONFIG_ROCKCHIP_TIMER=y\nCONFIG_RODATA_FULL_DEFAULT_ENABLED=y\nCONFIG_RPS=y\nCONFIG_RSEQ=y\nCONFIG_RTC_CLASS=y\nCONFIG_RTC_DRV_RK808=y\n# CONFIG_RTC_DRV_RV3032 is not set\nCONFIG_RTC_I2C_AND_SPI=y\nCONFIG_RTC_NVMEM=y\n# CONFIG_RUNTIME_TESTING_MENU is not set\nCONFIG_RWSEM_SPIN_ON_OWNER=y\nCONFIG_SCHED_MC=y\nCONFIG_SCSI=y\n# CONFIG_SCSI_LOWLEVEL is not set\n# CONFIG_SCSI_PROC_FS is not set\nCONFIG_SCSI_SAS_ATTRS=y\nCONFIG_SCSI_SAS_HOST_SMP=y\nCONFIG_SCSI_SAS_LIBSAS=y\n# CONFIG_SECURITY_DMESG_RESTRICT is not set\nCONFIG_SENSORS_ARM_SCPI=y\n# CONFIG_SENSORS_MR75203 is not set\nCONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y\nCONFIG_SERIAL_8250_DW=y\nCONFIG_SERIAL_8250_DWLIB=y\nCONFIG_SERIAL_8250_EXAR=y\nCONFIG_SERIAL_8250_EXTENDED=y\nCONFIG_SERIAL_8250_FSL=y\nCONFIG_SERIAL_8250_NR_UARTS=4\nCONFIG_SERIAL_8250_PCI=y\nCONFIG_SERIAL_8250_RUNTIME_UARTS=4\nCONFIG_SERIAL_8250_SHARE_IRQ=y\nCONFIG_SERIAL_AMBA_PL011=y\nCONFIG_SERIAL_AMBA_PL011_CONSOLE=y\nCONFIG_SERIAL_DEV_BUS=y\nCONFIG_SERIAL_DEV_CTRL_TTYPORT=y\nCONFIG_SERIAL_MCTRL_GPIO=y\nCONFIG_SERIAL_OF_PLATFORM=y\nCONFIG_SERIO=y\nCONFIG_SERIO_AMBAKMI=y\nCONFIG_SERIO_LIBPS2=y\nCONFIG_SG_POOL=y\nCONFIG_SIMPLE_PM_BUS=y\nCONFIG_SLUB_DEBUG=y\nCONFIG_SMP=y\n# CONFIG_SND_SOC_ROCKCHIP is not set\nCONFIG_SPARSEMEM=y\nCONFIG_SPARSEMEM_EXTREME=y\nCONFIG_SPARSEMEM_MANUAL=y\nCONFIG_SPARSEMEM_VMEMMAP=y\nCONFIG_SPARSEMEM_VMEMMAP_ENABLE=y\nCONFIG_SPARSE_IRQ=y\nCONFIG_SPI=y\nCONFIG_SPI_BITBANG=y\nCONFIG_SPI_DYNAMIC=y\nCONFIG_SPI_MASTER=y\nCONFIG_SPI_MEM=y\nCONFIG_SPI_ROCKCHIP=y\nCONFIG_SPI_SPIDEV=y\n# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set\nCONFIG_SQUASHFS_DECOMP_SINGLE=y\n# CONFIG_SQUASHFS_EMBEDDED is not set\nCONFIG_SQUASHFS_FILE_CACHE=y\n# CONFIG_SQUASHFS_FILE_DIRECT is not set\nCONFIG_SRAM=y\nCONFIG_SRCU=y\nCONFIG_STACKPROTECTOR=y\nCONFIG_STACKPROTECTOR_STRONG=y\nCONFIG_STMMAC_ETH=y\nCONFIG_STMMAC_PLATFORM=y\n# CONFIG_STMMAC_SELFTESTS is not set\nCONFIG_STRICT_DEVMEM=y\n# CONFIG_STRIP_ASM_SYMS is not set\n# CONFIG_SWAP is not set\nCONFIG_SWIOTLB=y\nCONFIG_SWPHY=y\nCONFIG_SYNC_FILE=y\nCONFIG_SYSCTL_EXCEPTION_TRACE=y\nCONFIG_SYSFS_SYSCALL=y\nCONFIG_SYSVIPC_COMPAT=y\nCONFIG_SYS_SUPPORTS_HUGETLBFS=y\n# CONFIG_TEXTSEARCH is not set\nCONFIG_THERMAL=y\nCONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y\nCONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0\nCONFIG_THERMAL_EMULATION=y\nCONFIG_THERMAL_GOV_POWER_ALLOCATOR=y\nCONFIG_THERMAL_GOV_STEP_WISE=y\nCONFIG_THERMAL_HWMON=y\nCONFIG_THERMAL_OF=y\nCONFIG_THREAD_INFO_IN_TASK=y\nCONFIG_TICK_CPU_ACCOUNTING=y\nCONFIG_TIMER_OF=y\nCONFIG_TIMER_PROBE=y\nCONFIG_TRACE_CLOCK=y\nCONFIG_TRANSPARENT_HUGEPAGE=y\nCONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y\n# CONFIG_TRANSPARENT_HUGEPAGE_MADVISE is not set\nCONFIG_TREE_RCU=y\nCONFIG_TREE_SRCU=y\nCONFIG_TYPEC=y\n# CONFIG_TYPEC_DP_ALTMODE is not set\nCONFIG_TYPEC_FUSB302=y\n# CONFIG_TYPEC_HD3SS3220 is not set\n# CONFIG_TYPEC_MUX_PI3USB30532 is not set\n# CONFIG_TYPEC_STUSB160X is not set\n# CONFIG_TYPEC_TCPCI is not set\nCONFIG_TYPEC_TCPM=y\n# CONFIG_TYPEC_TPS6598X is not set\n# CONFIG_UACCE is not set\n# CONFIG_UCLAMP_TASK is not set\n# CONFIG_UEVENT_HELPER is not set\nCONFIG_UNINLINE_SPIN_UNLOCK=y\nCONFIG_UNMAP_KERNEL_AT_EL0=y\nCONFIG_USB=y\nCONFIG_USB_COMMON=y\nCONFIG_USB_DWC3=y\nCONFIG_USB_DWC3_HOST=y\nCONFIG_USB_DWC3_OF_SIMPLE=y\nCONFIG_USB_EHCI_HCD=y\nCONFIG_USB_EHCI_HCD_PLATFORM=y\n# CONFIG_USB_EHCI_ROOT_HUB_TT is not set\nCONFIG_USB_HID=y\nCONFIG_USB_OHCI_HCD=y\nCONFIG_USB_OHCI_HCD_PLATFORM=y\nCONFIG_USB_PHY=y\nCONFIG_USB_ROLE_SWITCH=y\nCONFIG_USB_STORAGE=y\nCONFIG_USB_SUPPORT=y\nCONFIG_USB_ULPI=y\nCONFIG_USB_ULPI_BUS=y\nCONFIG_USB_ULPI_VIEWPORT=y\nCONFIG_USB_XHCI_HCD=y\nCONFIG_USB_XHCI_PLATFORM=y\n# CONFIG_VIRTIO_MENU is not set\nCONFIG_VMAP_STACK=y\nCONFIG_VM_EVENT_COUNTERS=y\nCONFIG_VT=y\nCONFIG_VT_CONSOLE=y\nCONFIG_VT_HW_CONSOLE_BINDING=y\n# CONFIG_WATCHDOG is not set\nCONFIG_XARRAY_MULTI=y\nCONFIG_XPS=y\nCONFIG_XXHASH=y\nCONFIG_XZ_DEC_ARM=y\nCONFIG_XZ_DEC_ARMTHUMB=y\nCONFIG_XZ_DEC_BCJ=y\nCONFIG_ZLIB_DEFLATE=y\nCONFIG_ZLIB_INFLATE=y\nCONFIG_ZONE_DMA32=y\n"
  },
  {
    "path": "target/linux/rockchip/armv8/target.mk",
    "content": "ARCH:=aarch64\nSUBTARGET:=armv8\nBOARDNAME:=RK33xx boards (64 bit)\n\ndefine Target/Description\n\tBuild firmware image for Rockchip RK33xx devices.\n\tThis firmware features a 64 bit kernel.\nendef\n"
  },
  {
    "path": "target/linux/rockchip/files/Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb3.yaml",
    "content": "# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)\n%YAML 1.2\n---\n$id: \"http://devicetree.org/schemas/phy/phy-rockchip-inno-usb3.yaml#\"\n$schema: \"http://devicetree.org/meta-schemas/core.yaml#\"\n\ntitle: ROCKCHIP USB 3.0 PHY WITH INNO IP BLOCK\n\nmaintainers:\n\nproperties:\n  compatible:\n    enum:\n      - rockchip,rk3328-u3phy\n\n  reg:\n    - description: the base address of the USB 3.0 PHY\n\n  interrupts:\n    maxItems: 1\n\n  interrupt-names:\n    items:\n      - const: linestate\n        description: host/otg linestate interrupt\n\n  clocks:\n    maxItems: 2\n\n  clock-names:\n    items:\n      - const: u3phy-otg\n        description: USB 3.0 PHY UTMI\n      - const: u3phy-pipe\n        description: USB 3.0 PHY Pipe\n\n  resets:\n    maxItems: 6\n\n  reset-names:\n    items:\n      - const: u3phy-u2-por\n      description: USB 2.0 logic of USB 3.0 PHY\n      - const: u3phy-u3-por\n      description: USB 3.0 logic of USB 3.0 PHY\n      - const: u3phy-pipe-mac\n      description: USB 3.0 PHY pipe MAC\n      - const: u3phy-utmi-mac\n      description: USB 3.0 PHY utmi MAC\n      - const: u3phy-utmi-apb\n      description: USB 3.0 PHY utmi apb\n      - const: u3phy-pipe-apb\n      description: USB 3.0 PHY pipe apb\n\n  \"#phy-cells\":\n    const: 1\n\n  rockchip,u3phygrf:\n    $ref: /schemas/types.yaml#/definitions/phandle-array\n    type: array\n    - description: phandle to the syscon managing the\n                   \"USB 3.0 PHY general register files\".\n\n  vbus-drv-gpios:\n    $ref: /schemas/types.yaml#/definitions/phandle-array\n    type: array\n    - description: phandle for gpio vbus supply\n\nrequired:\n  - compatible\n  - reg\n  - interrupts\n  - interrupt-names\n  - clocks\n  - clock-names\n  - resets\n  - reset-names\n  - \"#phy-cells\"\n  - rockchip,u3phygrf\n\npatternProperties:\n  \"^u3phy_utmi@[0-9a-f]+$\":\n    type: object\n\n    properties:\n      - description: USB 2.0 utmi phy.\n\n      rockchip,odt-val-tuning:\n        type: boolean\n        - description: specify 45ohm ODT tuning value.\n\n      \"phy-cells\":\n        const: 0\n\n    required:\n      - reg\n      - \"#phy-cells\"\n\npatternProperties:\n  \"^u3phy_pipe@[0-9a-f]+$\":\n    type: object\n\n    properties:\n      - description: USB 3.0 pipe phy.\n\n      rockchip,refclk-25m-quirk :\n\n        - description: phy reference clock changed to 25m quirk.\n\n      \"phy-cells\":\n        const: 0\n\n    required:\n      - reg\n      - \"#phy-cells\"\n\nexamples:\n\nusb3phy_grf: syscon@ff460000 {\n\tcompatible = \"rockchip,usb3phy-grf\", \"syscon\";\n\treg = <0x0 0xff460000 0x0 0x1000>;\n};\n\n...\n\nu3phy: usb3-phy@ff470000 {\n\tcompatible = \"rockchip,rk3328-u3phy\";\n\treg = <0x0 0xff470000 0x0 0x0>;\n\trockchip,u3phygrf = <&usb3phy_grf>;\n\tinterrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;\n\tinterrupt-names = \"linestate\";\n\tclocks = <&cru PCLK_USB3PHY_OTG>, <&cru PCLK_USB3PHY_PIPE>;\n\tclock-names = \"u3phy-otg\", \"u3phy-pipe\";\n\tresets = <&cru SRST_USB3PHY_U2>,\n\t\t <&cru SRST_USB3PHY_U3>,\n\t\t <&cru SRST_USB3PHY_PIPE>,\n\t\t <&cru SRST_USB3OTG_UTMI>,\n\t\t <&cru SRST_USB3PHY_OTG_P>,\n\t\t <&cru SRST_USB3PHY_PIPE_P>;\n\treset-names = \"u3phy-u2-por\", \"u3phy-u3-por\",\n\t\t      \"u3phy-pipe-mac\", \"u3phy-utmi-mac\",\n\t\t      \"u3phy-utmi-apb\", \"u3phy-pipe-apb\";\n\tvbus-drv-gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;\n\t#address-cells = <2>;\n\t#size-cells = <2>;\n\tranges;\n\n\tu3phy_utmi: utmi@ff470000 {\n\t\treg = <0x0 0xff470000 0x0 0x8000>;\n\t\t#phy-cells = <0>;\n\t};\n\n\tu3phy_pipe: pipe@ff478000 {\n\t\treg = <0x0 0xff478000 0x0 0x8000>;\n\t\t#phy-cells = <0>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3328-dram-nanopi2-timing.dtsi",
    "content": "/*\n * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd\n *\n * This file is dual-licensed: you can use it either under the terms\n * of the GPL or the X11 license, at your option. Note that this dual\n * licensing only applies to this file, and not this project as a\n * whole.\n *\n *  a) This library is free software; you can redistribute it and/or\n *     modify it under the terms of the GNU General Public License as\n *     published by the Free Software Foundation; either version 2 of the\n *     License, or (at your option) any later version.\n *\n *     This library is distributed in the hope that it will be useful,\n *     but WITHOUT ANY WARRANTY; without even the implied warranty of\n *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n *     GNU General Public License for more details.\n *\n * Or, alternatively,\n *\n *  b) Permission is hereby granted, free of charge, to any person\n *     obtaining a copy of this software and associated documentation\n *     files (the \"Software\"), to deal in the Software without\n *     restriction, including without limitation the rights to use,\n *     copy, modify, merge, publish, distribute, sublicense, and/or\n *     sell copies of the Software, and to permit persons to whom the\n *     Software is furnished to do so, subject to the following\n *     conditions:\n *\n *     The above copyright notice and this permission notice shall be\n *     included in all copies or substantial portions of the Software.\n *\n *     THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n *     OTHER DEALINGS IN THE SOFTWARE.\n */\n#include <dt-bindings/clock/rockchip-ddr.h>\n#include <dt-bindings/memory/rk3328-dram.h>\n\n/ {\n\tddr_timing: ddr_timing {\n\t\tcompatible = \"rockchip,ddr-timing\";\n\t\tddr3_speed_bin = <DDR3_DEFAULT>;\n\t\tddr4_speed_bin = <DDR4_DEFAULT>;\n\t\tpd_idle = <0>;\n\t\tsr_idle = <0>;\n\t\tsr_mc_gate_idle = <0>;\n\t\tsrpd_lite_idle\t= <0>;\n\t\tstandby_idle = <0>;\n\n\t\tauto_pd_dis_freq = <1066>;\n\t\tauto_sr_dis_freq = <800>;\n\t\tddr3_dll_dis_freq = <300>;\n\t\tddr4_dll_dis_freq = <625>;\n\t\tphy_dll_dis_freq = <400>;\n\n\t\tddr3_odt_dis_freq = <100>;\n\t\tphy_ddr3_odt_dis_freq = <100>;\n\t\tddr3_drv = <DDR3_DS_40ohm>;\n\t\tddr3_odt = <DDR3_ODT_120ohm>;\n\t\tphy_ddr3_ca_drv = <PHY_DDR3_RON_RTT_34ohm>;\n\t\tphy_ddr3_ck_drv = <PHY_DDR3_RON_RTT_45ohm>;\n\t\tphy_ddr3_dq_drv = <PHY_DDR3_RON_RTT_34ohm>;\n\t\tphy_ddr3_odt = <PHY_DDR3_RON_RTT_225ohm>;\n\n\t\tlpddr3_odt_dis_freq = <666>;\n\t\tphy_lpddr3_odt_dis_freq = <666>;\n\t\tlpddr3_drv = <LP3_DS_40ohm>;\n\t\tlpddr3_odt = <LP3_ODT_240ohm>;\n\t\tphy_lpddr3_ca_drv = <PHY_DDR4_LPDDR3_RON_RTT_34ohm>;\n\t\tphy_lpddr3_ck_drv = <PHY_DDR4_LPDDR3_RON_RTT_43ohm>;\n\t\tphy_lpddr3_dq_drv = <PHY_DDR4_LPDDR3_RON_RTT_34ohm>;\n\t\tphy_lpddr3_odt = <PHY_DDR4_LPDDR3_RON_RTT_240ohm>;\n\n\t\tlpddr4_odt_dis_freq = <800>;\n\t\tphy_lpddr4_odt_dis_freq = <800>;\n\t\tlpddr4_drv = <LP4_PDDS_60ohm>;\n\t\tlpddr4_dq_odt = <LP4_DQ_ODT_40ohm>;\n\t\tlpddr4_ca_odt = <LP4_CA_ODT_40ohm>;\n\t\tphy_lpddr4_ca_drv = <PHY_DDR4_LPDDR3_RON_RTT_40ohm>;\n\t\tphy_lpddr4_ck_cs_drv = <PHY_DDR4_LPDDR3_RON_RTT_80ohm>;\n\t\tphy_lpddr4_dq_drv = <PHY_DDR4_LPDDR3_RON_RTT_80ohm>;\n\t\tphy_lpddr4_odt = <PHY_DDR4_LPDDR3_RON_RTT_60ohm>;\n\n\t\tddr4_odt_dis_freq = <666>;\n\t\tphy_ddr4_odt_dis_freq = <666>;\n\t\tddr4_drv = <DDR4_DS_34ohm>;\n\t\tddr4_odt = <DDR4_RTT_NOM_240ohm>;\n\t\tphy_ddr4_ca_drv = <PHY_DDR4_LPDDR3_RON_RTT_34ohm>;\n\t\tphy_ddr4_ck_drv = <PHY_DDR4_LPDDR3_RON_RTT_43ohm>;\n\t\tphy_ddr4_dq_drv = <PHY_DDR4_LPDDR3_RON_RTT_34ohm>;\n\t\tphy_ddr4_odt = <PHY_DDR4_LPDDR3_RON_RTT_240ohm>;\n\n\t\t/* CA de-skew, one step is 47.8ps, range 0-15 */\n\t\tddr3a1_ddr4a9_de-skew = <7>;\n\t\tddr3a0_ddr4a10_de-skew = <7>;\n\t\tddr3a3_ddr4a6_de-skew = <8>;\n\t\tddr3a2_ddr4a4_de-skew = <8>;\n\t\tddr3a5_ddr4a8_de-skew = <7>;\n\t\tddr3a4_ddr4a5_de-skew = <9>;\n\t\tddr3a7_ddr4a11_de-skew = <7>;\n\t\tddr3a6_ddr4a7_de-skew = <9>;\n\t\tddr3a9_ddr4a0_de-skew = <8>;\n\t\tddr3a8_ddr4a13_de-skew = <7>;\n\t\tddr3a11_ddr4a3_de-skew = <9>;\n\t\tddr3a10_ddr4cs0_de-skew = <7>;\n\t\tddr3a13_ddr4a2_de-skew = <8>;\n\t\tddr3a12_ddr4ba1_de-skew = <7>;\n\t\tddr3a15_ddr4odt0_de-skew = <7>;\n\t\tddr3a14_ddr4a1_de-skew = <8>;\n\t\tddr3ba1_ddr4a15_de-skew = <7>;\n\t\tddr3ba0_ddr4bg0_de-skew = <7>;\n\t\tddr3ras_ddr4cke_de-skew = <7>;\n\t\tddr3ba2_ddr4ba0_de-skew = <8>;\n\t\tddr3we_ddr4bg1_de-skew = <8>;\n\t\tddr3cas_ddr4a12_de-skew = <7>;\n\t\tddr3ckn_ddr4ckn_de-skew = <8>;\n\t\tddr3ckp_ddr4ckp_de-skew = <8>;\n\t\tddr3cke_ddr4a16_de-skew = <8>;\n\t\tddr3odt0_ddr4a14_de-skew = <7>;\n\t\tddr3cs0_ddr4act_de-skew = <8>;\n\t\tddr3reset_ddr4reset_de-skew = <7>;\n\t\tddr3cs1_ddr4cs1_de-skew = <7>;\n\t\tddr3odt1_ddr4odt1_de-skew = <7>;\n\n\t\t/* DATA de-skew\n\t\t * RX one step is 25.1ps, range 0-15\n\t\t * TX one step is 47.8ps, range 0-15\n\t\t */\n\t\tcs0_dm0_rx_de-skew = <7>;\n\t\tcs0_dm0_tx_de-skew = <8>;\n\t\tcs0_dq0_rx_de-skew = <7>;\n\t\tcs0_dq0_tx_de-skew = <8>;\n\t\tcs0_dq1_rx_de-skew = <7>;\n\t\tcs0_dq1_tx_de-skew = <8>;\n\t\tcs0_dq2_rx_de-skew = <7>;\n\t\tcs0_dq2_tx_de-skew = <8>;\n\t\tcs0_dq3_rx_de-skew = <7>;\n\t\tcs0_dq3_tx_de-skew = <8>;\n\t\tcs0_dq4_rx_de-skew = <7>;\n\t\tcs0_dq4_tx_de-skew = <8>;\n\t\tcs0_dq5_rx_de-skew = <7>;\n\t\tcs0_dq5_tx_de-skew = <8>;\n\t\tcs0_dq6_rx_de-skew = <7>;\n\t\tcs0_dq6_tx_de-skew = <8>;\n\t\tcs0_dq7_rx_de-skew = <7>;\n\t\tcs0_dq7_tx_de-skew = <8>;\n\t\tcs0_dqs0_rx_de-skew = <6>;\n\t\tcs0_dqs0p_tx_de-skew = <9>;\n\t\tcs0_dqs0n_tx_de-skew = <9>;\n\n\t\tcs0_dm1_rx_de-skew = <7>;\n\t\tcs0_dm1_tx_de-skew = <7>;\n\t\tcs0_dq8_rx_de-skew = <7>;\n\t\tcs0_dq8_tx_de-skew = <8>;\n\t\tcs0_dq9_rx_de-skew = <7>;\n\t\tcs0_dq9_tx_de-skew = <7>;\n\t\tcs0_dq10_rx_de-skew = <7>;\n\t\tcs0_dq10_tx_de-skew = <8>;\n\t\tcs0_dq11_rx_de-skew = <7>;\n\t\tcs0_dq11_tx_de-skew = <7>;\n\t\tcs0_dq12_rx_de-skew = <7>;\n\t\tcs0_dq12_tx_de-skew = <8>;\n\t\tcs0_dq13_rx_de-skew = <7>;\n\t\tcs0_dq13_tx_de-skew = <7>;\n\t\tcs0_dq14_rx_de-skew = <7>;\n\t\tcs0_dq14_tx_de-skew = <8>;\n\t\tcs0_dq15_rx_de-skew = <7>;\n\t\tcs0_dq15_tx_de-skew = <7>;\n\t\tcs0_dqs1_rx_de-skew = <7>;\n\t\tcs0_dqs1p_tx_de-skew = <9>;\n\t\tcs0_dqs1n_tx_de-skew = <9>;\n\n\t\tcs0_dm2_rx_de-skew = <7>;\n\t\tcs0_dm2_tx_de-skew = <8>;\n\t\tcs0_dq16_rx_de-skew = <7>;\n\t\tcs0_dq16_tx_de-skew = <8>;\n\t\tcs0_dq17_rx_de-skew = <7>;\n\t\tcs0_dq17_tx_de-skew = <8>;\n\t\tcs0_dq18_rx_de-skew = <7>;\n\t\tcs0_dq18_tx_de-skew = <8>;\n\t\tcs0_dq19_rx_de-skew = <7>;\n\t\tcs0_dq19_tx_de-skew = <8>;\n\t\tcs0_dq20_rx_de-skew = <7>;\n\t\tcs0_dq20_tx_de-skew = <8>;\n\t\tcs0_dq21_rx_de-skew = <7>;\n\t\tcs0_dq21_tx_de-skew = <8>;\n\t\tcs0_dq22_rx_de-skew = <7>;\n\t\tcs0_dq22_tx_de-skew = <8>;\n\t\tcs0_dq23_rx_de-skew = <7>;\n\t\tcs0_dq23_tx_de-skew = <8>;\n\t\tcs0_dqs2_rx_de-skew = <6>;\n\t\tcs0_dqs2p_tx_de-skew = <9>;\n\t\tcs0_dqs2n_tx_de-skew = <9>;\n\n\t\tcs0_dm3_rx_de-skew = <7>;\n\t\tcs0_dm3_tx_de-skew = <7>;\n\t\tcs0_dq24_rx_de-skew = <7>;\n\t\tcs0_dq24_tx_de-skew = <8>;\n\t\tcs0_dq25_rx_de-skew = <7>;\n\t\tcs0_dq25_tx_de-skew = <7>;\n\t\tcs0_dq26_rx_de-skew = <7>;\n\t\tcs0_dq26_tx_de-skew = <7>;\n\t\tcs0_dq27_rx_de-skew = <7>;\n\t\tcs0_dq27_tx_de-skew = <7>;\n\t\tcs0_dq28_rx_de-skew = <7>;\n\t\tcs0_dq28_tx_de-skew = <7>;\n\t\tcs0_dq29_rx_de-skew = <7>;\n\t\tcs0_dq29_tx_de-skew = <7>;\n\t\tcs0_dq30_rx_de-skew = <7>;\n\t\tcs0_dq30_tx_de-skew = <7>;\n\t\tcs0_dq31_rx_de-skew = <7>;\n\t\tcs0_dq31_tx_de-skew = <7>;\n\t\tcs0_dqs3_rx_de-skew = <7>;\n\t\tcs0_dqs3p_tx_de-skew = <9>;\n\t\tcs0_dqs3n_tx_de-skew = <9>;\n\n\t\tcs1_dm0_rx_de-skew = <7>;\n\t\tcs1_dm0_tx_de-skew = <8>;\n\t\tcs1_dq0_rx_de-skew = <7>;\n\t\tcs1_dq0_tx_de-skew = <8>;\n\t\tcs1_dq1_rx_de-skew = <7>;\n\t\tcs1_dq1_tx_de-skew = <8>;\n\t\tcs1_dq2_rx_de-skew = <7>;\n\t\tcs1_dq2_tx_de-skew = <8>;\n\t\tcs1_dq3_rx_de-skew = <7>;\n\t\tcs1_dq3_tx_de-skew = <8>;\n\t\tcs1_dq4_rx_de-skew = <7>;\n\t\tcs1_dq4_tx_de-skew = <8>;\n\t\tcs1_dq5_rx_de-skew = <7>;\n\t\tcs1_dq5_tx_de-skew = <8>;\n\t\tcs1_dq6_rx_de-skew = <7>;\n\t\tcs1_dq6_tx_de-skew = <8>;\n\t\tcs1_dq7_rx_de-skew = <7>;\n\t\tcs1_dq7_tx_de-skew = <8>;\n\t\tcs1_dqs0_rx_de-skew = <6>;\n\t\tcs1_dqs0p_tx_de-skew = <9>;\n\t\tcs1_dqs0n_tx_de-skew = <9>;\n\n\t\tcs1_dm1_rx_de-skew = <7>;\n\t\tcs1_dm1_tx_de-skew = <7>;\n\t\tcs1_dq8_rx_de-skew = <7>;\n\t\tcs1_dq8_tx_de-skew = <8>;\n\t\tcs1_dq9_rx_de-skew = <7>;\n\t\tcs1_dq9_tx_de-skew = <7>;\n\t\tcs1_dq10_rx_de-skew = <7>;\n\t\tcs1_dq10_tx_de-skew = <8>;\n\t\tcs1_dq11_rx_de-skew = <7>;\n\t\tcs1_dq11_tx_de-skew = <7>;\n\t\tcs1_dq12_rx_de-skew = <7>;\n\t\tcs1_dq12_tx_de-skew = <8>;\n\t\tcs1_dq13_rx_de-skew = <7>;\n\t\tcs1_dq13_tx_de-skew = <7>;\n\t\tcs1_dq14_rx_de-skew = <7>;\n\t\tcs1_dq14_tx_de-skew = <8>;\n\t\tcs1_dq15_rx_de-skew = <7>;\n\t\tcs1_dq15_tx_de-skew = <7>;\n\t\tcs1_dqs1_rx_de-skew = <7>;\n\t\tcs1_dqs1p_tx_de-skew = <9>;\n\t\tcs1_dqs1n_tx_de-skew = <9>;\n\n\t\tcs1_dm2_rx_de-skew = <7>;\n\t\tcs1_dm2_tx_de-skew = <8>;\n\t\tcs1_dq16_rx_de-skew = <7>;\n\t\tcs1_dq16_tx_de-skew = <8>;\n\t\tcs1_dq17_rx_de-skew = <7>;\n\t\tcs1_dq17_tx_de-skew = <8>;\n\t\tcs1_dq18_rx_de-skew = <7>;\n\t\tcs1_dq18_tx_de-skew = <8>;\n\t\tcs1_dq19_rx_de-skew = <7>;\n\t\tcs1_dq19_tx_de-skew = <8>;\n\t\tcs1_dq20_rx_de-skew = <7>;\n\t\tcs1_dq20_tx_de-skew = <8>;\n\t\tcs1_dq21_rx_de-skew = <7>;\n\t\tcs1_dq21_tx_de-skew = <8>;\n\t\tcs1_dq22_rx_de-skew = <7>;\n\t\tcs1_dq22_tx_de-skew = <8>;\n\t\tcs1_dq23_rx_de-skew = <7>;\n\t\tcs1_dq23_tx_de-skew = <8>;\n\t\tcs1_dqs2_rx_de-skew = <6>;\n\t\tcs1_dqs2p_tx_de-skew = <9>;\n\t\tcs1_dqs2n_tx_de-skew = <9>;\n\n\t\tcs1_dm3_rx_de-skew = <7>;\n\t\tcs1_dm3_tx_de-skew = <7>;\n\t\tcs1_dq24_rx_de-skew = <7>;\n\t\tcs1_dq24_tx_de-skew = <8>;\n\t\tcs1_dq25_rx_de-skew = <7>;\n\t\tcs1_dq25_tx_de-skew = <7>;\n\t\tcs1_dq26_rx_de-skew = <7>;\n\t\tcs1_dq26_tx_de-skew = <7>;\n\t\tcs1_dq27_rx_de-skew = <7>;\n\t\tcs1_dq27_tx_de-skew = <7>;\n\t\tcs1_dq28_rx_de-skew = <7>;\n\t\tcs1_dq28_tx_de-skew = <7>;\n\t\tcs1_dq29_rx_de-skew = <7>;\n\t\tcs1_dq29_tx_de-skew = <7>;\n\t\tcs1_dq30_rx_de-skew = <7>;\n\t\tcs1_dq30_tx_de-skew = <7>;\n\t\tcs1_dq31_rx_de-skew = <7>;\n\t\tcs1_dq31_tx_de-skew = <7>;\n\t\tcs1_dqs3_rx_de-skew = <7>;\n\t\tcs1_dqs3p_tx_de-skew = <9>;\n\t\tcs1_dqs3n_tx_de-skew = <9>;\n\t};\n};\n"
  },
  {
    "path": "target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3399-guangmiao-g4c.dts",
    "content": "// SPDX-License-Identifier: (GPL-2.0+ OR MIT)\n\n/dts-v1/;\n#include <dt-bindings/input/linux-event-codes.h>\n#include \"rk3399.dtsi\"\n#include \"rk3399-opp.dtsi\"\n\n/ {\n\tmodel = \"SHAREVDI GuangMiao G4C\";\n\tcompatible = \"sharevdi,guangmiao-g4c\", \"rockchip,rk3399\";\n\n\t/delete-node/ display-subsystem;\n\n\taliases {\n\t\tled-boot = &status_led;\n\t\tled-failsafe = &status_led;\n\t\tled-running = &status_led;\n\t\tled-upgrade = &status_led;\n\t};\n\n\tchosen {\n\t\tstdout-path = \"serial2:1500000n8\";\n\t};\n\n\tclkin_gmac: external-gmac-clock {\n\t\tcompatible = \"fixed-clock\";\n\t\tclock-frequency = <125000000>;\n\t\tclock-output-names = \"clkin_gmac\";\n\t\t#clock-cells = <0>;\n\t};\n\n\tvcc_sys: vcc-sys {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-always-on;\n\t\tregulator-boot-on;\n\t\tregulator-min-microvolt = <5000000>;\n\t\tregulator-max-microvolt = <5000000>;\n\t\tregulator-name = \"vcc_sys\";\n\t};\n\n\tvcc3v3_sys: vcc3v3-sys {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-always-on;\n\t\tregulator-boot-on;\n\t\tregulator-min-microvolt = <3300000>;\n\t\tregulator-max-microvolt = <3300000>;\n\t\tregulator-name = \"vcc3v3_sys\";\n\t\tvin-supply = <&vcc_sys>;\n\t};\n\n\tvcc_0v9: vcc-0v9 {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-always-on;\n\t\tregulator-boot-on;\n\t\tregulator-min-microvolt = <900000>;\n\t\tregulator-max-microvolt = <900000>;\n\t\tregulator-name = \"vcc_0v9\";\n\t\tvin-supply = <&vcc3v3_sys>;\n\t};\n\n\tvcc5v0_host0: vcc5v0-host0 {\n\t\tcompatible = \"regulator-fixed\";\n\t\tregulator-always-on;\n\t\tregulator-boot-on;\n\t\tregulator-name = \"vcc5v0_host0\";\n\t\tvin-supply = <&vcc_sys>;\n\t};\n\n\tvdd_log: vdd-log {\n\t\tcompatible = \"pwm-regulator\";\n\t\tpwms = <&pwm2 0 25000 1>;\n\t\tregulator-always-on;\n\t\tregulator-boot-on;\n\t\tregulator-min-microvolt = <800000>;\n\t\tregulator-max-microvolt = <1400000>;\n\t\tregulator-name = \"vdd_log\";\n\t\tvin-supply = <&vcc_sys>;\n\t};\n\n\tgpio-keys {\n\t\tcompatible = \"gpio-keys\";\n\t\tautorepeat;\n\t\tpinctrl-names = \"default\";\n\t\tpinctrl-0 = <&reset_button_pin>;\n\n\t\treset {\n\t\t\tdebounce-interval = <100>;\n\t\t\tgpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;\n\t\t\tlabel = \"reset\";\n\t\t\tlinux,code = <KEY_RESTART>;\n\t\t\twakeup-source;\n\t\t};\n\t};\n\n\tgpio-leds {\n\t\tcompatible = \"gpio-leds\";\n\t\tpinctrl-names = \"default\";\n\t\tpinctrl-0 = <&lan_led_pin>, <&status_led_pin>, <&wan_led_pin>;\n\n\t\tlan_led: led-lan {\n\t\t\tgpios = <&gpio0 RK_PA3 GPIO_ACTIVE_HIGH>;\n\t\t\tlabel = \"green:lan\";\n\t\t};\n\n\t\tstatus_led: led-status {\n\t\t\tgpios = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>;\n\t\t\tlabel = \"green:status\";\n\t\t};\n\n\t\twan_led: led-wan {\n\t\t\tgpios = <&gpio0 RK_PB2 GPIO_ACTIVE_HIGH>;\n\t\t\tlabel = \"green:wan\";\n\t\t};\n\t};\n};\n\n&cpu_b0 {\n\tcpu-supply = <&vdd_cpu_b>;\n};\n\n&cpu_b1 {\n\tcpu-supply = <&vdd_cpu_b>;\n};\n\n&cpu_l0 {\n\tcpu-supply = <&vdd_cpu_l>;\n};\n\n&cpu_l1 {\n\tcpu-supply = <&vdd_cpu_l>;\n};\n\n&cpu_l2 {\n\tcpu-supply = <&vdd_cpu_l>;\n};\n\n&cpu_l3 {\n\tcpu-supply = <&vdd_cpu_l>;\n};\n\n&emmc_phy {\n\tstatus = \"okay\";\n};\n\n&gmac {\n\tassigned-clock-parents = <&clkin_gmac>;\n\tassigned-clocks = <&cru SCLK_RMII_SRC>;\n\tclock_in_out = \"input\";\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&rgmii_pins>, <&phy_intb>, <&phy_pmeb>, <&phy_rstb>;\n\tphy-handle = <&rtl8211e>;\n\tphy-mode = \"rgmii\";\n\tphy-supply = <&vcc3v3_s3>;\n\ttx_delay = <0x28>;\n\trx_delay = <0x11>;\n\tstatus = \"okay\";\n\n\tmdio {\n\t\tcompatible = \"snps,dwmac-mdio\";\n\t\t#address-cells = <1>;\n\t\t#size-cells = <0>;\n\n\t\trtl8211e: ethernet-phy@1 {\n\t\t\treg = <1>;\n\t\t\tinterrupt-parent = <&gpio3>;\n\t\t\tinterrupts = <RK_PB2 IRQ_TYPE_LEVEL_LOW>;\n\t\t\treset-assert-us = <10000>;\n\t\t\treset-deassert-us = <30000>;\n\t\t\treset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;\n\t\t};\n\t};\n};\n\n&gpu {\n\tmali-supply = <&vdd_gpu>;\n\tstatus = \"okay\";\n};\n\n&i2c0 {\n\tclock-frequency = <400000>;\n\ti2c-scl-rising-time-ns = <160>;\n\ti2c-scl-falling-time-ns = <30>;\n\tstatus = \"okay\";\n\n\tvdd_cpu_b: regulator@40 {\n\t\tcompatible = \"silergy,syr827\";\n\t\treg = <0x40>;\n\t\tfcs,suspend-voltage-selector = <1>;\n\t\tpinctrl-names = \"default\";\n\t\tpinctrl-0 = <&cpu_b_sleep>;\n\t\tregulator-always-on;\n\t\tregulator-boot-on;\n\t\tregulator-min-microvolt = <712500>;\n\t\tregulator-max-microvolt = <1500000>;\n\t\tregulator-name = \"vdd_cpu_b\";\n\t\tregulator-ramp-delay = <1000>;\n\t\tvin-supply = <&vcc_sys>;\n\n\t\tregulator-state-mem {\n\t\t\tregulator-off-in-suspend;\n\t\t};\n\t};\n\n\tvdd_gpu: regulator@41 {\n\t\tcompatible = \"silergy,syr828\";\n\t\treg = <0x41>;\n\t\tfcs,suspend-voltage-selector = <1>;\n\t\tpinctrl-names = \"default\";\n\t\tpinctrl-0 = <&gpu_sleep>;\n\t\tregulator-always-on;\n\t\tregulator-boot-on;\n\t\tregulator-min-microvolt = <712500>;\n\t\tregulator-max-microvolt = <1500000>;\n\t\tregulator-name = \"vdd_gpu\";\n\t\tregulator-ramp-delay = <1000>;\n\t\tvin-supply = <&vcc_sys>;\n\n\t\tregulator-state-mem {\n\t\t\tregulator-off-in-suspend;\n\t\t};\n\t};\n\n\trk808: pmic@1b {\n\t\tcompatible = \"rockchip,rk808\";\n\t\treg = <0x1b>;\n\t\tclock-output-names = \"rtc_clko_soc\", \"rtc_clko_wifi\";\n\t\t#clock-cells = <1>;\n\t\tinterrupt-parent = <&gpio1>;\n\t\tinterrupts = <21 IRQ_TYPE_LEVEL_LOW>;\n\t\tpinctrl-names = \"default\";\n\t\tpinctrl-0 = <&pmic_int_l>;\n\t\trockchip,system-power-controller;\n\t\twakeup-source;\n\n\t\tvcc1-supply = <&vcc_sys>;\n\t\tvcc2-supply = <&vcc_sys>;\n\t\tvcc3-supply = <&vcc_sys>;\n\t\tvcc4-supply = <&vcc_sys>;\n\t\tvcc6-supply = <&vcc_sys>;\n\t\tvcc7-supply = <&vcc_sys>;\n\t\tvcc8-supply = <&vcc_3v0>;\n\t\tvcc9-supply = <&vcc_sys>;\n\t\tvcc10-supply = <&vcc_sys>;\n\t\tvcc11-supply = <&vcc_sys>;\n\t\tvcc12-supply = <&vcc_sys>;\n\t\tvddio-supply = <&vcc_3v0>;\n\n\t\tregulators {\n\t\t\tvdd_center: DCDC_REG1 {\n\t\t\t\tregulator-always-on;\n\t\t\t\tregulator-boot-on;\n\t\t\t\tregulator-min-microvolt = <750000>;\n\t\t\t\tregulator-max-microvolt = <1350000>;\n\t\t\t\tregulator-name = \"vdd_center\";\n\t\t\t\tregulator-ramp-delay = <6001>;\n\n\t\t\t\tregulator-state-mem {\n\t\t\t\t\tregulator-off-in-suspend;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tvdd_cpu_l: DCDC_REG2 {\n\t\t\t\tregulator-always-on;\n\t\t\t\tregulator-boot-on;\n\t\t\t\tregulator-min-microvolt = <750000>;\n\t\t\t\tregulator-max-microvolt = <1350000>;\n\t\t\t\tregulator-name = \"vdd_cpu_l\";\n\t\t\t\tregulator-ramp-delay = <6001>;\n\n\t\t\t\tregulator-state-mem {\n\t\t\t\t\tregulator-off-in-suspend;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tvcc_ddr: DCDC_REG3 {\n\t\t\t\tregulator-always-on;\n\t\t\t\tregulator-boot-on;\n\t\t\t\tregulator-name = \"vcc_ddr\";\n\n\t\t\t\tregulator-state-mem {\n\t\t\t\t\tregulator-on-in-suspend;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tvcc_1v8: DCDC_REG4 {\n\t\t\t\tregulator-always-on;\n\t\t\t\tregulator-boot-on;\n\t\t\t\tregulator-min-microvolt = <1800000>;\n\t\t\t\tregulator-max-microvolt = <1800000>;\n\t\t\t\tregulator-name = \"vcc_1v8\";\n\n\t\t\t\tregulator-state-mem {\n\t\t\t\t\tregulator-on-in-suspend;\n\t\t\t\t\tregulator-suspend-microvolt = <1800000>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tvcc_vldo1: LDO_REG1 {\n\t\t\t\tregulator-always-on;\n\t\t\t\tregulator-boot-on;\n\t\t\t\tregulator-min-microvolt = <1800000>;\n\t\t\t\tregulator-max-microvolt = <1800000>;\n\t\t\t\tregulator-name = \"vcc_vldo1\";\n\n\t\t\t\tregulator-state-mem {\n\t\t\t\t\tregulator-off-in-suspend;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tvcc_vldo2: LDO_REG2 {\n\t\t\t\tregulator-always-on;\n\t\t\t\tregulator-boot-on;\n\t\t\t\tregulator-min-microvolt = <1800000>;\n\t\t\t\tregulator-max-microvolt = <1800000>;\n\t\t\t\tregulator-name = \"vcc_vldo2\";\n\n\t\t\t\tregulator-state-mem {\n\t\t\t\t\tregulator-off-in-suspend;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tvcca_1v8: LDO_REG3 {\n\t\t\t\tregulator-always-on;\n\t\t\t\tregulator-boot-on;\n\t\t\t\tregulator-min-microvolt = <1800000>;\n\t\t\t\tregulator-max-microvolt = <1800000>;\n\t\t\t\tregulator-name = \"vcca_1v8\";\n\n\t\t\t\tregulator-state-mem {\n\t\t\t\t\tregulator-on-in-suspend;\n\t\t\t\t\tregulator-suspend-microvolt = <1800000>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tvcc_sdio: LDO_REG4 {\n\t\t\t\tregulator-always-on;\n\t\t\t\tregulator-boot-on;\n\t\t\t\tregulator-min-microvolt = <1800000>;\n\t\t\t\tregulator-max-microvolt = <3300000>;\n\t\t\t\tregulator-name = \"vcc_sdio\";\n\n\t\t\t\tregulator-state-mem {\n\t\t\t\t\tregulator-on-in-suspend;\n\t\t\t\t\tregulator-suspend-microvolt = <3300000>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tvcc3v0_sd: LDO_REG5 {\n\t\t\t\tregulator-always-on;\n\t\t\t\tregulator-boot-on;\n\t\t\t\tregulator-min-microvolt = <3000000>;\n\t\t\t\tregulator-max-microvolt = <3000000>;\n\t\t\t\tregulator-name = \"vcc3v0_sd\";\n\n\t\t\t\tregulator-state-mem {\n\t\t\t\t\tregulator-on-in-suspend;\n\t\t\t\t\tregulator-suspend-microvolt = <3000000>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tvcc_1v5: LDO_REG6 {\n\t\t\t\tregulator-always-on;\n\t\t\t\tregulator-boot-on;\n\t\t\t\tregulator-min-microvolt = <1500000>;\n\t\t\t\tregulator-max-microvolt = <1500000>;\n\t\t\t\tregulator-name = \"vcc_1v5\";\n\n\t\t\t\tregulator-state-mem {\n\t\t\t\t\tregulator-on-in-suspend;\n\t\t\t\t\tregulator-suspend-microvolt = <1500000>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tvcca1v8_codec: LDO_REG7 {\n\t\t\t\tregulator-always-on;\n\t\t\t\tregulator-boot-on;\n\t\t\t\tregulator-min-microvolt = <1800000>;\n\t\t\t\tregulator-max-microvolt = <1800000>;\n\t\t\t\tregulator-name = \"vcca1v8_codec\";\n\n\t\t\t\tregulator-state-mem {\n\t\t\t\t\tregulator-off-in-suspend;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tvcc_3v0: LDO_REG8 {\n\t\t\t\tregulator-always-on;\n\t\t\t\tregulator-boot-on;\n\t\t\t\tregulator-min-microvolt = <3000000>;\n\t\t\t\tregulator-max-microvolt = <3000000>;\n\t\t\t\tregulator-name = \"vcc_3v0\";\n\n\t\t\t\tregulator-state-mem {\n\t\t\t\t\tregulator-on-in-suspend;\n\t\t\t\t\tregulator-suspend-microvolt = <3000000>;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tvcc3v3_s3: SWITCH_REG1 {\n\t\t\t\tregulator-always-on;\n\t\t\t\tregulator-boot-on;\n\t\t\t\tregulator-name = \"vcc3v3_s3\";\n\n\t\t\t\tregulator-state-mem {\n\t\t\t\t\tregulator-off-in-suspend;\n\t\t\t\t};\n\t\t\t};\n\n\t\t\tvcc3v3_s0: SWITCH_REG2 {\n\t\t\t\tregulator-always-on;\n\t\t\t\tregulator-boot-on;\n\t\t\t\tregulator-name = \"vcc3v3_s0\";\n\n\t\t\t\tregulator-state-mem {\n\t\t\t\t\tregulator-off-in-suspend;\n\t\t\t\t};\n\t\t\t};\n\t\t};\n\t};\n};\n\n&i2c3 {\n\ti2c-scl-rising-time-ns = <450>;\n\ti2c-scl-falling-time-ns = <15>;\n\tstatus = \"okay\";\n};\n\n&io_domains {\n\tbt656-supply = <&vcc_1v8>;\n\taudio-supply = <&vcca1v8_codec>;\n\tsdmmc-supply = <&vcc_sdio>;\n\tgpio1830-supply = <&vcc_3v0>;\n\tstatus = \"okay\";\n};\n\n&pcie_phy {\n\tassigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>;\n\tassigned-clock-rates = <100000000>;\n\tassigned-clocks = <&cru SCLK_PCIEPHY_REF>;\n\tstatus = \"okay\";\n};\n\n&pcie0 {\n\tep-gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>;\n\tmax-link-speed = <1>;\n\tnum-lanes = <1>;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&pcie_clkreqnb_cpm>;\n\tvpcie0v9-supply = <&vcc_0v9>;\n\tvpcie1v8-supply = <&vcca_1v8>;\n\tvpcie3v3-supply = <&vcc3v3_sys>;\n\tstatus = \"okay\";\n\n\tpcie@0 {\n\t\treg = <0x00000000 0 0 0 0>;\n\t\t#address-cells = <3>;\n\t\t#size-cells = <2>;\n\n\t\tpcie-eth@0,0 {\n\t\t\tcompatible = \"realtek,r8168\";\n\t\t\treg = <0x000000 0 0 0 0>;\n\n\t\t\trealtek,led-data = <0x87>;\n\t\t};\n\t};\n};\n\n&pinctrl {\n\tgpio-leds {\n\t\tlan_led_pin: lan-led-pin {\n\t\t\trockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;\n\t\t};\n\n\t\tstatus_led_pin: status-led-pin {\n\t\t\trockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;\n\t\t};\n\n\t\twan_led_pin: wan-led-pin {\n\t\t\trockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;\n\t\t};\n\t};\n\n\tgmac {\n\t\tphy_intb: phy-intb {\n\t\t\trockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;\n\t\t};\n\n\t\tphy_pmeb: phy-pmeb {\n\t\t\trockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>;\n\t\t};\n\n\t\tphy_rstb: phy-rstb {\n\t\t\trockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;\n\t\t};\n\t};\n\n\tpmic {\n\t\tcpu_b_sleep: cpu-b-sleep {\n\t\t\trockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>;\n\t\t};\n\n\t\tgpu_sleep: gpu-sleep {\n\t\t\trockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;\n\t\t};\n\n\t\tpmic_int_l: pmic-int-l {\n\t\t\trockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;\n\t\t};\n\t};\n\n\trockchip-key {\n\t\treset_button_pin: reset-button-pin {\n\t\t\trockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;\n\t\t};\n\t};\n\n\tsdio {\n\t\tbt_reg_on_h: bt-reg-on-h {\n\t\t\t/* external pullup to VCC1V8_PMUPLL */\n\t\t\trockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;\n\t\t};\n\t};\n\n\tsdmmc {\n\t\tsdmmc0_det_l: sdmmc0-det-l {\n\t\t\trockchip,pins = <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>;\n\t\t};\n\t};\n};\n\n&pmu_io_domains {\n\tpmu1830-supply = <&vcc_3v0>;\n\tstatus = \"okay\";\n};\n\n&pwm0 {\n\tstatus = \"okay\";\n};\n\n&pwm1 {\n\tstatus = \"okay\";\n};\n\n&pwm2 {\n\tpinctrl-names = \"active\";\n\tpinctrl-0 = <&pwm2_pin_pull_down>;\n\tstatus = \"okay\";\n};\n\n&saradc {\n\tvref-supply = <&vcc_1v8>;\n\tstatus = \"okay\";\n};\n\n&sdhci {\n\tbus-width = <8>;\n\tmmc-hs200-1_8v;\n\tnon-removable;\n\tstatus = \"okay\";\n};\n\n&sdmmc {\n\tbus-width = <4>;\n\tcap-mmc-highspeed;\n\tcap-sd-highspeed;\n\tcd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;\n\tdisable-wp;\n\tpinctrl-names = \"default\";\n\tpinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc0_det_l>;\n\tvqmmc-supply = <&vcc_sdio>;\n\tstatus = \"okay\";\n};\n\n&tcphy0 {\n\tstatus = \"okay\";\n};\n\n&tcphy1 {\n\tstatus = \"okay\";\n};\n\n&tsadc {\n\trockchip,hw-tshut-mode = <1>;\n\trockchip,hw-tshut-polarity = <1>;\n\tstatus = \"okay\";\n};\n\n&u2phy0 {\n\tstatus = \"okay\";\n};\n\n&u2phy0_host {\n\tphy-supply = <&vcc5v0_host0>;\n\tstatus = \"okay\";\n};\n\n&u2phy0_otg {\n\tstatus = \"okay\";\n};\n\n&u2phy1 {\n\tstatus = \"okay\";\n};\n\n&u2phy1_host {\n\tphy-supply = <&vcc5v0_host0>;\n\tstatus = \"okay\";\n};\n\n&u2phy1_otg {\n\tstatus = \"okay\";\n};\n\n&uart2 {\n\tstatus = \"okay\";\n};\n\n&usbdrd3_0 {\n\tstatus = \"okay\";\n};\n\n&usbdrd3_1 {\n\tstatus = \"okay\";\n};\n\n&usbdrd_dwc3_0 {\n\tdr_mode = \"host\";\n\tstatus = \"okay\";\n};\n\n&usbdrd_dwc3_1 {\n\tdr_mode = \"host\";\n\tstatus = \"okay\";\n};\n\n&usb_host0_ehci {\n\tstatus = \"okay\";\n};\n\n&usb_host0_ohci {\n\tstatus = \"okay\";\n};\n\n&usb_host1_ehci {\n\tstatus = \"okay\";\n};\n\n&usb_host1_ohci {\n\tstatus = \"okay\";\n};\n\n&vopb {\n\tstatus = \"okay\";\n};\n\n&vopb_mmu {\n\tstatus = \"okay\";\n};\n\n&vopl {\n\tstatus = \"okay\";\n};\n\n&vopl_mmu {\n\tstatus = \"okay\";\n};\n"
  },
  {
    "path": "target/linux/rockchip/files/drivers/char/hw_random/rockchip-rng.c",
    "content": "// SPDX-License-Identifier: GPL-2.0\n/*\n * rockchip-rng.c Random Number Generator driver for the Rockchip\n *\n * Copyright (c) 2018, Fuzhou Rockchip Electronics Co., Ltd.\n * Author: Lin Jinhan <troy.lin@rock-chips.com>\n *\n */\n#include <linux/clk.h>\n#include <linux/hw_random.h>\n#include <linux/iopoll.h>\n#include <linux/module.h>\n#include <linux/mod_devicetable.h>\n#include <linux/of.h>\n#include <linux/platform_device.h>\n#include <linux/pm_runtime.h>\n\n#define _SBF(s, v)\t((v) << (s))\n#define HIWORD_UPDATE(val, mask, shift) \\\n\t\t\t((val) << (shift) | (mask) << ((shift) + 16))\n\n#define ROCKCHIP_AUTOSUSPEND_DELAY\t\t100\n#define ROCKCHIP_POLL_PERIOD_US\t\t\t100\n#define ROCKCHIP_POLL_TIMEOUT_US\t\t10000\n#define RK_MAX_RNG_BYTE\t\t\t\t(32)\n\n/* start of CRYPTO V1 register define */\n#define CRYPTO_V1_CTRL\t\t\t\t0x0008\n#define CRYPTO_V1_RNG_START\t\t\tBIT(8)\n#define CRYPTO_V1_RNG_FLUSH\t\t\tBIT(9)\n\n#define CRYPTO_V1_TRNG_CTRL\t\t\t0x0200\n#define CRYPTO_V1_OSC_ENABLE\t\t\tBIT(16)\n#define CRYPTO_V1_TRNG_SAMPLE_PERIOD(x)\t\t(x)\n\n#define CRYPTO_V1_TRNG_DOUT_0\t\t\t0x0204\n/* end of CRYPTO V1 register define */\n\n/* start of CRYPTO V2 register define */\n#define CRYPTO_V2_RNG_CTL\t\t\t0x0400\n#define CRYPTO_V2_RNG_64_BIT_LEN\t\t_SBF(4, 0x00)\n#define CRYPTO_V2_RNG_128_BIT_LEN\t\t_SBF(4, 0x01)\n#define CRYPTO_V2_RNG_192_BIT_LEN\t\t_SBF(4, 0x02)\n#define CRYPTO_V2_RNG_256_BIT_LEN\t\t_SBF(4, 0x03)\n#define CRYPTO_V2_RNG_FATESY_SOC_RING\t\t_SBF(2, 0x00)\n#define CRYPTO_V2_RNG_SLOWER_SOC_RING_0\t\t_SBF(2, 0x01)\n#define CRYPTO_V2_RNG_SLOWER_SOC_RING_1\t\t_SBF(2, 0x02)\n#define CRYPTO_V2_RNG_SLOWEST_SOC_RING\t\t_SBF(2, 0x03)\n#define CRYPTO_V2_RNG_ENABLE\t\t\tBIT(1)\n#define CRYPTO_V2_RNG_START\t\t\tBIT(0)\n#define CRYPTO_V2_RNG_SAMPLE_CNT\t\t0x0404\n#define CRYPTO_V2_RNG_DOUT_0\t\t\t0x0410\n/* end of CRYPTO V2 register define */\n\nstruct rk_rng_soc_data {\n\tconst char * const *clks;\n\tint clks_num;\n\tint (*rk_rng_read)(struct hwrng *rng, void *buf, size_t max, bool wait);\n};\n\nstruct rk_rng {\n\tstruct device\t\t*dev;\n\tstruct hwrng\t\trng;\n\tvoid __iomem\t\t*mem;\n\tstruct rk_rng_soc_data\t*soc_data;\n\tu32\t\t\tclk_num;\n\tstruct clk_bulk_data\t*clk_bulks;\n};\n\nstatic const char * const rk_rng_v1_clks[] = {\n\t\"hclk_crypto\",\n\t\"clk_crypto\",\n};\n\nstatic const char * const rk_rng_v2_clks[] = {\n\t\"hclk_crypto\",\n\t\"aclk_crypto\",\n\t\"clk_crypto\",\n\t\"clk_crypto_apk\",\n};\n\nstatic void rk_rng_writel(struct rk_rng *rng, u32 val, u32 offset)\n{\n\t__raw_writel(val, rng->mem + offset);\n}\n\nstatic u32 rk_rng_readl(struct rk_rng *rng, u32 offset)\n{\n\treturn __raw_readl(rng->mem + offset);\n}\n\nstatic int rk_rng_init(struct hwrng *rng)\n{\n\tint ret;\n\tstruct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);\n\n\tdev_dbg(rk_rng->dev, \"clk_bulk_prepare_enable.\\n\");\n\n\tret = clk_bulk_prepare_enable(rk_rng->clk_num, rk_rng->clk_bulks);\n\tif (ret < 0) {\n\t\tdev_err(rk_rng->dev, \"failed to enable clks %d\\n\", ret);\n\t\treturn ret;\n\t}\n\n\treturn 0;\n}\n\nstatic void rk_rng_cleanup(struct hwrng *rng)\n{\n\tstruct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);\n\n\tdev_dbg(rk_rng->dev, \"clk_bulk_disable_unprepare.\\n\");\n\tclk_bulk_disable_unprepare(rk_rng->clk_num, rk_rng->clk_bulks);\n}\n\nstatic void rk_rng_read_regs(struct rk_rng *rng, u32 offset, void *buf,\n\t\t\t     size_t size)\n{\n\tu32 i;\n\n\tfor (i = 0; i < size; i += 4)\n\t\t*(u32 *)(buf + i) = be32_to_cpu(rk_rng_readl(rng, offset + i));\n}\n\nstatic int rk_rng_v1_read(struct hwrng *rng, void *buf, size_t max, bool wait)\n{\n\tint ret = 0;\n\tu32 reg_ctrl = 0;\n\tstruct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);\n\n\tret = pm_runtime_get_sync(rk_rng->dev);\n\tif (ret < 0) {\n\t\tpm_runtime_put_noidle(rk_rng->dev);\n\t\treturn ret;\n\t}\n\n\t/* enable osc_ring to get entropy, sample period is set as 100 */\n\treg_ctrl = CRYPTO_V1_OSC_ENABLE | CRYPTO_V1_TRNG_SAMPLE_PERIOD(100);\n\trk_rng_writel(rk_rng, reg_ctrl, CRYPTO_V1_TRNG_CTRL);\n\n\treg_ctrl = HIWORD_UPDATE(CRYPTO_V1_RNG_START, CRYPTO_V1_RNG_START, 0);\n\n\trk_rng_writel(rk_rng, reg_ctrl, CRYPTO_V1_CTRL);\n\n\tret = readl_poll_timeout(rk_rng->mem + CRYPTO_V1_CTRL, reg_ctrl,\n\t\t\t\t !(reg_ctrl & CRYPTO_V1_RNG_START),\n\t\t\t\t ROCKCHIP_POLL_PERIOD_US,\n\t\t\t\t ROCKCHIP_POLL_TIMEOUT_US);\n\tif (ret < 0)\n\t\tgoto out;\n\n\tret = min_t(size_t, max, RK_MAX_RNG_BYTE);\n\n\trk_rng_read_regs(rk_rng, CRYPTO_V1_TRNG_DOUT_0, buf, ret);\n\nout:\n\t/* close TRNG */\n\trk_rng_writel(rk_rng, HIWORD_UPDATE(0, CRYPTO_V1_RNG_START, 0),\n\t\t      CRYPTO_V1_CTRL);\n\n\tpm_runtime_mark_last_busy(rk_rng->dev);\n\tpm_runtime_put_sync_autosuspend(rk_rng->dev);\n\n\treturn ret;\n}\n\nstatic int rk_rng_v2_read(struct hwrng *rng, void *buf, size_t max, bool wait)\n{\n\tint ret = 0;\n\tu32 reg_ctrl = 0;\n\tstruct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);\n\n\tret = pm_runtime_get_sync(rk_rng->dev);\n\tif (ret < 0) {\n\t\tpm_runtime_put_noidle(rk_rng->dev);\n\t\treturn ret;\n\t}\n\n\t/* enable osc_ring to get entropy, sample period is set as 100 */\n\trk_rng_writel(rk_rng, 100, CRYPTO_V2_RNG_SAMPLE_CNT);\n\n\treg_ctrl |= CRYPTO_V2_RNG_256_BIT_LEN;\n\treg_ctrl |= CRYPTO_V2_RNG_SLOWER_SOC_RING_0;\n\treg_ctrl |= CRYPTO_V2_RNG_ENABLE;\n\treg_ctrl |= CRYPTO_V2_RNG_START;\n\n\trk_rng_writel(rk_rng, HIWORD_UPDATE(reg_ctrl, 0xffff, 0),\n\t\t\tCRYPTO_V2_RNG_CTL);\n\n\tret = readl_poll_timeout(rk_rng->mem + CRYPTO_V2_RNG_CTL, reg_ctrl,\n\t\t\t\t !(reg_ctrl & CRYPTO_V2_RNG_START),\n\t\t\t\t ROCKCHIP_POLL_PERIOD_US,\n\t\t\t\t ROCKCHIP_POLL_TIMEOUT_US);\n\tif (ret < 0)\n\t\tgoto out;\n\n\tret = min_t(size_t, max, RK_MAX_RNG_BYTE);\n\n\trk_rng_read_regs(rk_rng, CRYPTO_V2_RNG_DOUT_0, buf, ret);\n\nout:\n\t/* close TRNG */\n\trk_rng_writel(rk_rng, HIWORD_UPDATE(0, 0xffff, 0), CRYPTO_V2_RNG_CTL);\n\n\tpm_runtime_mark_last_busy(rk_rng->dev);\n\tpm_runtime_put_sync_autosuspend(rk_rng->dev);\n\n\treturn ret;\n}\n\nstatic const struct rk_rng_soc_data rk_rng_v1_soc_data = {\n\t.clks_num = ARRAY_SIZE(rk_rng_v1_clks),\n\t.clks = rk_rng_v1_clks,\n\t.rk_rng_read = rk_rng_v1_read,\n};\n\nstatic const struct rk_rng_soc_data rk_rng_v2_soc_data = {\n\t.clks_num = ARRAY_SIZE(rk_rng_v2_clks),\n\t.clks = rk_rng_v2_clks,\n\t.rk_rng_read = rk_rng_v2_read,\n};\n\nstatic const struct of_device_id rk_rng_dt_match[] = {\n\t{\n\t\t.compatible = \"rockchip,cryptov1-rng\",\n\t\t.data = (void *)&rk_rng_v1_soc_data,\n\t},\n\t{\n\t\t.compatible = \"rockchip,cryptov2-rng\",\n\t\t.data = (void *)&rk_rng_v2_soc_data,\n\t},\n\t{ },\n};\n\nMODULE_DEVICE_TABLE(of, rk_rng_dt_match);\n\nstatic int rk_rng_probe(struct platform_device *pdev)\n{\n\tint i;\n\tint ret;\n\tstruct rk_rng *rk_rng;\n\tstruct device_node *np = pdev->dev.of_node;\n\tconst struct of_device_id *match;\n\n\tdev_dbg(&pdev->dev, \"probing...\\n\");\n\trk_rng = devm_kzalloc(&pdev->dev, sizeof(struct rk_rng), GFP_KERNEL);\n\tif (!rk_rng)\n\t\treturn -ENOMEM;\n\n\tmatch = of_match_node(rk_rng_dt_match, np);\n\trk_rng->soc_data = (struct rk_rng_soc_data *)match->data;\n\n\trk_rng->dev = &pdev->dev;\n\trk_rng->rng.name    = \"rockchip\";\n#ifndef CONFIG_PM\n\trk_rng->rng.init    = rk_rng_init;\n\trk_rng->rng.cleanup = rk_rng_cleanup,\n#endif\n\trk_rng->rng.read    = rk_rng->soc_data->rk_rng_read;\n\trk_rng->rng.quality = 1000;\n\n\trk_rng->clk_bulks =\n\t\tdevm_kzalloc(&pdev->dev, sizeof(*rk_rng->clk_bulks) *\n\t\t\t     rk_rng->soc_data->clks_num, GFP_KERNEL);\n\n\trk_rng->clk_num = rk_rng->soc_data->clks_num;\n\n\tfor (i = 0; i < rk_rng->soc_data->clks_num; i++)\n\t\trk_rng->clk_bulks[i].id = rk_rng->soc_data->clks[i];\n\n\trk_rng->mem = devm_of_iomap(&pdev->dev, pdev->dev.of_node, 0, NULL);\n\tif (IS_ERR(rk_rng->mem))\n\t\treturn PTR_ERR(rk_rng->mem);\n\n\tret = devm_clk_bulk_get(&pdev->dev, rk_rng->clk_num,\n\t\t\t\trk_rng->clk_bulks);\n\tif (ret) {\n\t\tdev_err(&pdev->dev, \"failed to get clks property\\n\");\n\t\treturn ret;\n\t}\n\n\tplatform_set_drvdata(pdev, rk_rng);\n\n\tpm_runtime_set_autosuspend_delay(&pdev->dev,\n\t\t\t\t\tROCKCHIP_AUTOSUSPEND_DELAY);\n\tpm_runtime_use_autosuspend(&pdev->dev);\n\tpm_runtime_enable(&pdev->dev);\n\n\tret = devm_hwrng_register(&pdev->dev, &rk_rng->rng);\n\tif (ret) {\n\t\tpm_runtime_dont_use_autosuspend(&pdev->dev);\n\t\tpm_runtime_disable(&pdev->dev);\n\t}\n\n\treturn ret;\n}\n\n#ifdef CONFIG_PM\nstatic int rk_rng_runtime_suspend(struct device *dev)\n{\n\tstruct rk_rng *rk_rng = dev_get_drvdata(dev);\n\n\trk_rng_cleanup(&rk_rng->rng);\n\n\treturn 0;\n}\n\nstatic int rk_rng_runtime_resume(struct device *dev)\n{\n\tstruct rk_rng *rk_rng = dev_get_drvdata(dev);\n\n\treturn rk_rng_init(&rk_rng->rng);\n}\n\nstatic const struct dev_pm_ops rk_rng_pm_ops = {\n\tSET_RUNTIME_PM_OPS(rk_rng_runtime_suspend,\n\t\t\t\trk_rng_runtime_resume, NULL)\n\tSET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,\n\t\t\t\tpm_runtime_force_resume)\n};\n\n#endif\n\nstatic struct platform_driver rk_rng_driver = {\n\t.driver\t= {\n\t\t.name\t= \"rockchip-rng\",\n#ifdef CONFIG_PM\n\t\t.pm\t= &rk_rng_pm_ops,\n#endif\n\t\t.of_match_table = rk_rng_dt_match,\n\t},\n\t.probe\t= rk_rng_probe,\n};\n\nmodule_platform_driver(rk_rng_driver);\n\nMODULE_DESCRIPTION(\"ROCKCHIP H/W Random Number Generator driver\");\nMODULE_AUTHOR(\"Lin Jinhan <troy.lin@rock-chips.com>\");\nMODULE_LICENSE(\"GPL v2\");\n\n"
  },
  {
    "path": "target/linux/rockchip/files/drivers/devfreq/rk3328_dmc.c",
    "content": "// SPDX-License-Identifier: GPL-2.0-only\n/*\n * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd.\n * Author: Lin Huang <hl@rock-chips.com>\n */\n\n#include <linux/arm-smccc.h>\n#include <linux/clk.h>\n#include <linux/delay.h>\n#include <linux/devfreq.h>\n#include <linux/devfreq-event.h>\n#include <linux/interrupt.h>\n#include <linux/iversion.h>\n#include <linux/mfd/syscon.h>\n#include <linux/module.h>\n#include <linux/of.h>\n#include <linux/platform_device.h>\n#include <linux/pm_opp.h>\n#include <linux/regmap.h>\n#include <linux/regulator/consumer.h>\n#include <linux/rwsem.h>\n#include <linux/suspend.h>\n#include <linux/version.h>\n\n#include <soc/rockchip/rockchip_sip.h>\n\n#define DTS_PAR_OFFSET\t\t(4096)\n\nstruct share_params {\n\tu32 hz;\n\tu32 lcdc_type;\n\tu32 vop;\n\tu32 vop_dclk_mode;\n\tu32 sr_idle_en;\n\tu32 addr_mcu_el3;\n\t/*\n\t * 1: need to wait flag1\n\t * 0: never wait flag1\n\t */\n\tu32 wait_flag1;\n\t/*\n\t * 1: need to wait flag1\n\t * 0: never wait flag1\n\t */\n\tu32 wait_flag0;\n\tu32 complt_hwirq;\n\t/* if need, add parameter after */\n};\n\nstatic struct share_params *ddr_psci_param;\n\n/* hope this define can adapt all future platform */\nstatic const char * const rk3328_dts_timing[] = {\n\t\"ddr3_speed_bin\",\n\t\"ddr4_speed_bin\",\n\t\"pd_idle\",\n\t\"sr_idle\",\n\t\"sr_mc_gate_idle\",\n\t\"srpd_lite_idle\",\n\t\"standby_idle\",\n\n\t\"auto_pd_dis_freq\",\n\t\"auto_sr_dis_freq\",\n\t\"ddr3_dll_dis_freq\",\n\t\"ddr4_dll_dis_freq\",\n\t\"phy_dll_dis_freq\",\n\n\t\"ddr3_odt_dis_freq\",\n\t\"phy_ddr3_odt_dis_freq\",\n\t\"ddr3_drv\",\n\t\"ddr3_odt\",\n\t\"phy_ddr3_ca_drv\",\n\t\"phy_ddr3_ck_drv\",\n\t\"phy_ddr3_dq_drv\",\n\t\"phy_ddr3_odt\",\n\n\t\"lpddr3_odt_dis_freq\",\n\t\"phy_lpddr3_odt_dis_freq\",\n\t\"lpddr3_drv\",\n\t\"lpddr3_odt\",\n\t\"phy_lpddr3_ca_drv\",\n\t\"phy_lpddr3_ck_drv\",\n\t\"phy_lpddr3_dq_drv\",\n\t\"phy_lpddr3_odt\",\n\n\t\"lpddr4_odt_dis_freq\",\n\t\"phy_lpddr4_odt_dis_freq\",\n\t\"lpddr4_drv\",\n\t\"lpddr4_dq_odt\",\n\t\"lpddr4_ca_odt\",\n\t\"phy_lpddr4_ca_drv\",\n\t\"phy_lpddr4_ck_cs_drv\",\n\t\"phy_lpddr4_dq_drv\",\n\t\"phy_lpddr4_odt\",\n\n\t\"ddr4_odt_dis_freq\",\n\t\"phy_ddr4_odt_dis_freq\",\n\t\"ddr4_drv\",\n\t\"ddr4_odt\",\n\t\"phy_ddr4_ca_drv\",\n\t\"phy_ddr4_ck_drv\",\n\t\"phy_ddr4_dq_drv\",\n\t\"phy_ddr4_odt\",\n};\n\nstatic const char * const rk3328_dts_ca_timing[] = {\n\t\"ddr3a1_ddr4a9_de-skew\",\n\t\"ddr3a0_ddr4a10_de-skew\",\n\t\"ddr3a3_ddr4a6_de-skew\",\n\t\"ddr3a2_ddr4a4_de-skew\",\n\t\"ddr3a5_ddr4a8_de-skew\",\n\t\"ddr3a4_ddr4a5_de-skew\",\n\t\"ddr3a7_ddr4a11_de-skew\",\n\t\"ddr3a6_ddr4a7_de-skew\",\n\t\"ddr3a9_ddr4a0_de-skew\",\n\t\"ddr3a8_ddr4a13_de-skew\",\n\t\"ddr3a11_ddr4a3_de-skew\",\n\t\"ddr3a10_ddr4cs0_de-skew\",\n\t\"ddr3a13_ddr4a2_de-skew\",\n\t\"ddr3a12_ddr4ba1_de-skew\",\n\t\"ddr3a15_ddr4odt0_de-skew\",\n\t\"ddr3a14_ddr4a1_de-skew\",\n\t\"ddr3ba1_ddr4a15_de-skew\",\n\t\"ddr3ba0_ddr4bg0_de-skew\",\n\t\"ddr3ras_ddr4cke_de-skew\",\n\t\"ddr3ba2_ddr4ba0_de-skew\",\n\t\"ddr3we_ddr4bg1_de-skew\",\n\t\"ddr3cas_ddr4a12_de-skew\",\n\t\"ddr3ckn_ddr4ckn_de-skew\",\n\t\"ddr3ckp_ddr4ckp_de-skew\",\n\t\"ddr3cke_ddr4a16_de-skew\",\n\t\"ddr3odt0_ddr4a14_de-skew\",\n\t\"ddr3cs0_ddr4act_de-skew\",\n\t\"ddr3reset_ddr4reset_de-skew\",\n\t\"ddr3cs1_ddr4cs1_de-skew\",\n\t\"ddr3odt1_ddr4odt1_de-skew\",\n};\n\nstatic const char * const rk3328_dts_cs0_timing[] = {\n\t\"cs0_dm0_rx_de-skew\",\n\t\"cs0_dm0_tx_de-skew\",\n\t\"cs0_dq0_rx_de-skew\",\n\t\"cs0_dq0_tx_de-skew\",\n\t\"cs0_dq1_rx_de-skew\",\n\t\"cs0_dq1_tx_de-skew\",\n\t\"cs0_dq2_rx_de-skew\",\n\t\"cs0_dq2_tx_de-skew\",\n\t\"cs0_dq3_rx_de-skew\",\n\t\"cs0_dq3_tx_de-skew\",\n\t\"cs0_dq4_rx_de-skew\",\n\t\"cs0_dq4_tx_de-skew\",\n\t\"cs0_dq5_rx_de-skew\",\n\t\"cs0_dq5_tx_de-skew\",\n\t\"cs0_dq6_rx_de-skew\",\n\t\"cs0_dq6_tx_de-skew\",\n\t\"cs0_dq7_rx_de-skew\",\n\t\"cs0_dq7_tx_de-skew\",\n\t\"cs0_dqs0_rx_de-skew\",\n\t\"cs0_dqs0p_tx_de-skew\",\n\t\"cs0_dqs0n_tx_de-skew\",\n\n\t\"cs0_dm1_rx_de-skew\",\n\t\"cs0_dm1_tx_de-skew\",\n\t\"cs0_dq8_rx_de-skew\",\n\t\"cs0_dq8_tx_de-skew\",\n\t\"cs0_dq9_rx_de-skew\",\n\t\"cs0_dq9_tx_de-skew\",\n\t\"cs0_dq10_rx_de-skew\",\n\t\"cs0_dq10_tx_de-skew\",\n\t\"cs0_dq11_rx_de-skew\",\n\t\"cs0_dq11_tx_de-skew\",\n\t\"cs0_dq12_rx_de-skew\",\n\t\"cs0_dq12_tx_de-skew\",\n\t\"cs0_dq13_rx_de-skew\",\n\t\"cs0_dq13_tx_de-skew\",\n\t\"cs0_dq14_rx_de-skew\",\n\t\"cs0_dq14_tx_de-skew\",\n\t\"cs0_dq15_rx_de-skew\",\n\t\"cs0_dq15_tx_de-skew\",\n\t\"cs0_dqs1_rx_de-skew\",\n\t\"cs0_dqs1p_tx_de-skew\",\n\t\"cs0_dqs1n_tx_de-skew\",\n\n\t\"cs0_dm2_rx_de-skew\",\n\t\"cs0_dm2_tx_de-skew\",\n\t\"cs0_dq16_rx_de-skew\",\n\t\"cs0_dq16_tx_de-skew\",\n\t\"cs0_dq17_rx_de-skew\",\n\t\"cs0_dq17_tx_de-skew\",\n\t\"cs0_dq18_rx_de-skew\",\n\t\"cs0_dq18_tx_de-skew\",\n\t\"cs0_dq19_rx_de-skew\",\n\t\"cs0_dq19_tx_de-skew\",\n\t\"cs0_dq20_rx_de-skew\",\n\t\"cs0_dq20_tx_de-skew\",\n\t\"cs0_dq21_rx_de-skew\",\n\t\"cs0_dq21_tx_de-skew\",\n\t\"cs0_dq22_rx_de-skew\",\n\t\"cs0_dq22_tx_de-skew\",\n\t\"cs0_dq23_rx_de-skew\",\n\t\"cs0_dq23_tx_de-skew\",\n\t\"cs0_dqs2_rx_de-skew\",\n\t\"cs0_dqs2p_tx_de-skew\",\n\t\"cs0_dqs2n_tx_de-skew\",\n\n\t\"cs0_dm3_rx_de-skew\",\n\t\"cs0_dm3_tx_de-skew\",\n\t\"cs0_dq24_rx_de-skew\",\n\t\"cs0_dq24_tx_de-skew\",\n\t\"cs0_dq25_rx_de-skew\",\n\t\"cs0_dq25_tx_de-skew\",\n\t\"cs0_dq26_rx_de-skew\",\n\t\"cs0_dq26_tx_de-skew\",\n\t\"cs0_dq27_rx_de-skew\",\n\t\"cs0_dq27_tx_de-skew\",\n\t\"cs0_dq28_rx_de-skew\",\n\t\"cs0_dq28_tx_de-skew\",\n\t\"cs0_dq29_rx_de-skew\",\n\t\"cs0_dq29_tx_de-skew\",\n\t\"cs0_dq30_rx_de-skew\",\n\t\"cs0_dq30_tx_de-skew\",\n\t\"cs0_dq31_rx_de-skew\",\n\t\"cs0_dq31_tx_de-skew\",\n\t\"cs0_dqs3_rx_de-skew\",\n\t\"cs0_dqs3p_tx_de-skew\",\n\t\"cs0_dqs3n_tx_de-skew\",\n};\n\nstatic const char * const rk3328_dts_cs1_timing[] = {\n\t\"cs1_dm0_rx_de-skew\",\n\t\"cs1_dm0_tx_de-skew\",\n\t\"cs1_dq0_rx_de-skew\",\n\t\"cs1_dq0_tx_de-skew\",\n\t\"cs1_dq1_rx_de-skew\",\n\t\"cs1_dq1_tx_de-skew\",\n\t\"cs1_dq2_rx_de-skew\",\n\t\"cs1_dq2_tx_de-skew\",\n\t\"cs1_dq3_rx_de-skew\",\n\t\"cs1_dq3_tx_de-skew\",\n\t\"cs1_dq4_rx_de-skew\",\n\t\"cs1_dq4_tx_de-skew\",\n\t\"cs1_dq5_rx_de-skew\",\n\t\"cs1_dq5_tx_de-skew\",\n\t\"cs1_dq6_rx_de-skew\",\n\t\"cs1_dq6_tx_de-skew\",\n\t\"cs1_dq7_rx_de-skew\",\n\t\"cs1_dq7_tx_de-skew\",\n\t\"cs1_dqs0_rx_de-skew\",\n\t\"cs1_dqs0p_tx_de-skew\",\n\t\"cs1_dqs0n_tx_de-skew\",\n\n\t\"cs1_dm1_rx_de-skew\",\n\t\"cs1_dm1_tx_de-skew\",\n\t\"cs1_dq8_rx_de-skew\",\n\t\"cs1_dq8_tx_de-skew\",\n\t\"cs1_dq9_rx_de-skew\",\n\t\"cs1_dq9_tx_de-skew\",\n\t\"cs1_dq10_rx_de-skew\",\n\t\"cs1_dq10_tx_de-skew\",\n\t\"cs1_dq11_rx_de-skew\",\n\t\"cs1_dq11_tx_de-skew\",\n\t\"cs1_dq12_rx_de-skew\",\n\t\"cs1_dq12_tx_de-skew\",\n\t\"cs1_dq13_rx_de-skew\",\n\t\"cs1_dq13_tx_de-skew\",\n\t\"cs1_dq14_rx_de-skew\",\n\t\"cs1_dq14_tx_de-skew\",\n\t\"cs1_dq15_rx_de-skew\",\n\t\"cs1_dq15_tx_de-skew\",\n\t\"cs1_dqs1_rx_de-skew\",\n\t\"cs1_dqs1p_tx_de-skew\",\n\t\"cs1_dqs1n_tx_de-skew\",\n\n\t\"cs1_dm2_rx_de-skew\",\n\t\"cs1_dm2_tx_de-skew\",\n\t\"cs1_dq16_rx_de-skew\",\n\t\"cs1_dq16_tx_de-skew\",\n\t\"cs1_dq17_rx_de-skew\",\n\t\"cs1_dq17_tx_de-skew\",\n\t\"cs1_dq18_rx_de-skew\",\n\t\"cs1_dq18_tx_de-skew\",\n\t\"cs1_dq19_rx_de-skew\",\n\t\"cs1_dq19_tx_de-skew\",\n\t\"cs1_dq20_rx_de-skew\",\n\t\"cs1_dq20_tx_de-skew\",\n\t\"cs1_dq21_rx_de-skew\",\n\t\"cs1_dq21_tx_de-skew\",\n\t\"cs1_dq22_rx_de-skew\",\n\t\"cs1_dq22_tx_de-skew\",\n\t\"cs1_dq23_rx_de-skew\",\n\t\"cs1_dq23_tx_de-skew\",\n\t\"cs1_dqs2_rx_de-skew\",\n\t\"cs1_dqs2p_tx_de-skew\",\n\t\"cs1_dqs2n_tx_de-skew\",\n\n\t\"cs1_dm3_rx_de-skew\",\n\t\"cs1_dm3_tx_de-skew\",\n\t\"cs1_dq24_rx_de-skew\",\n\t\"cs1_dq24_tx_de-skew\",\n\t\"cs1_dq25_rx_de-skew\",\n\t\"cs1_dq25_tx_de-skew\",\n\t\"cs1_dq26_rx_de-skew\",\n\t\"cs1_dq26_tx_de-skew\",\n\t\"cs1_dq27_rx_de-skew\",\n\t\"cs1_dq27_tx_de-skew\",\n\t\"cs1_dq28_rx_de-skew\",\n\t\"cs1_dq28_tx_de-skew\",\n\t\"cs1_dq29_rx_de-skew\",\n\t\"cs1_dq29_tx_de-skew\",\n\t\"cs1_dq30_rx_de-skew\",\n\t\"cs1_dq30_tx_de-skew\",\n\t\"cs1_dq31_rx_de-skew\",\n\t\"cs1_dq31_tx_de-skew\",\n\t\"cs1_dqs3_rx_de-skew\",\n\t\"cs1_dqs3p_tx_de-skew\",\n\t\"cs1_dqs3n_tx_de-skew\",\n};\n\nstruct rk3328_ddr_dts_config_timing {\n\tunsigned int ddr3_speed_bin;\n\tunsigned int ddr4_speed_bin;\n\tunsigned int pd_idle;\n\tunsigned int sr_idle;\n\tunsigned int sr_mc_gate_idle;\n\tunsigned int srpd_lite_idle;\n\tunsigned int standby_idle;\n\n\tunsigned int auto_pd_dis_freq;\n\tunsigned int auto_sr_dis_freq;\n\t/* for ddr3 only */\n\tunsigned int ddr3_dll_dis_freq;\n\t/* for ddr4 only */\n\tunsigned int ddr4_dll_dis_freq;\n\tunsigned int phy_dll_dis_freq;\n\n\tunsigned int ddr3_odt_dis_freq;\n\tunsigned int phy_ddr3_odt_dis_freq;\n\tunsigned int ddr3_drv;\n\tunsigned int ddr3_odt;\n\tunsigned int phy_ddr3_ca_drv;\n\tunsigned int phy_ddr3_ck_drv;\n\tunsigned int phy_ddr3_dq_drv;\n\tunsigned int phy_ddr3_odt;\n\n\tunsigned int lpddr3_odt_dis_freq;\n\tunsigned int phy_lpddr3_odt_dis_freq;\n\tunsigned int lpddr3_drv;\n\tunsigned int lpddr3_odt;\n\tunsigned int phy_lpddr3_ca_drv;\n\tunsigned int phy_lpddr3_ck_drv;\n\tunsigned int phy_lpddr3_dq_drv;\n\tunsigned int phy_lpddr3_odt;\n\n\tunsigned int lpddr4_odt_dis_freq;\n\tunsigned int phy_lpddr4_odt_dis_freq;\n\tunsigned int lpddr4_drv;\n\tunsigned int lpddr4_dq_odt;\n\tunsigned int lpddr4_ca_odt;\n\tunsigned int phy_lpddr4_ca_drv;\n\tunsigned int phy_lpddr4_ck_cs_drv;\n\tunsigned int phy_lpddr4_dq_drv;\n\tunsigned int phy_lpddr4_odt;\n\n\tunsigned int ddr4_odt_dis_freq;\n\tunsigned int phy_ddr4_odt_dis_freq;\n\tunsigned int ddr4_drv;\n\tunsigned int ddr4_odt;\n\tunsigned int phy_ddr4_ca_drv;\n\tunsigned int phy_ddr4_ck_drv;\n\tunsigned int phy_ddr4_dq_drv;\n\tunsigned int phy_ddr4_odt;\n\n\tunsigned int ca_skew[15];\n\tunsigned int cs0_skew[44];\n\tunsigned int cs1_skew[44];\n\n\tunsigned int available;\n};\n\nstruct rk3328_ddr_de_skew_setting {\n\tunsigned int ca_de_skew[30];\n\tunsigned int cs0_de_skew[84];\n\tunsigned int cs1_de_skew[84];\n};\n\nstruct rk3328_dmcfreq {\n\tstruct device *dev;\n\tstruct devfreq *devfreq;\n\tstruct devfreq_simple_ondemand_data ondemand_data;\n\tstruct clk *dmc_clk;\n\tstruct devfreq_event_dev *edev;\n\tstruct mutex lock;\n\tstruct regulator *vdd_center;\n\tunsigned long rate, target_rate;\n\tunsigned long volt, target_volt;\n\n\tint (*set_auto_self_refresh)(u32 en);\n};\n\nstatic void\nrk3328_de_skew_setting_2_register(struct rk3328_ddr_de_skew_setting *de_skew,\n\t\t\t\t  struct rk3328_ddr_dts_config_timing *tim)\n{\n\tu32 n;\n\tu32 offset;\n\tu32 shift;\n\n\tmemset_io(tim->ca_skew, 0, sizeof(tim->ca_skew));\n\tmemset_io(tim->cs0_skew, 0, sizeof(tim->cs0_skew));\n\tmemset_io(tim->cs1_skew, 0, sizeof(tim->cs1_skew));\n\n\t/* CA de-skew */\n\tfor (n = 0; n < ARRAY_SIZE(de_skew->ca_de_skew); n++) {\n\t\toffset = n / 2;\n\t\tshift = n % 2;\n\t\t/* 0 => 4; 1 => 0 */\n\t\tshift = (shift == 0) ? 4 : 0;\n\t\ttim->ca_skew[offset] &= ~(0xf << shift);\n\t\ttim->ca_skew[offset] |= (de_skew->ca_de_skew[n] << shift);\n\t}\n\n\t/* CS0 data de-skew */\n\tfor (n = 0; n < ARRAY_SIZE(de_skew->cs0_de_skew); n++) {\n\t\toffset = ((n / 21) * 11) + ((n % 21) / 2);\n\t\tshift = ((n % 21) % 2);\n\t\tif ((n % 21) == 20)\n\t\t\tshift = 0;\n\t\telse\n\t\t\t/* 0 => 4; 1 => 0 */\n\t\t\tshift = (shift == 0) ? 4 : 0;\n\t\ttim->cs0_skew[offset] &= ~(0xf << shift);\n\t\ttim->cs0_skew[offset] |= (de_skew->cs0_de_skew[n] << shift);\n\t}\n\n\t/* CS1 data de-skew */\n\tfor (n = 0; n < ARRAY_SIZE(de_skew->cs1_de_skew); n++) {\n\t\toffset = ((n / 21) * 11) + ((n % 21) / 2);\n\t\tshift = ((n % 21) % 2);\n\t\tif ((n % 21) == 20)\n\t\t\tshift = 0;\n\t\telse\n\t\t\t/* 0 => 4; 1 => 0 */\n\t\t\tshift = (shift == 0) ? 4 : 0;\n\t\ttim->cs1_skew[offset] &= ~(0xf << shift);\n\t\ttim->cs1_skew[offset] |= (de_skew->cs1_de_skew[n] << shift);\n\t}\n}\n\nstatic void of_get_rk3328_timings(struct device *dev,\n\t\t\t\t  struct device_node *np, uint32_t *timing)\n{\n\tstruct device_node *np_tim;\n\tu32 *p;\n\tstruct rk3328_ddr_dts_config_timing *dts_timing;\n\tstruct rk3328_ddr_de_skew_setting *de_skew;\n\tint ret = 0;\n\tu32 i;\n\n\tdts_timing =\n\t\t(struct rk3328_ddr_dts_config_timing *)(timing +\n\t\t\t\t\t\t\tDTS_PAR_OFFSET / 4);\n\n\tnp_tim = of_parse_phandle(np, \"ddr_timing\", 0);\n\tif (!np_tim) {\n\t\tret = -EINVAL;\n\t\tgoto end;\n\t}\n\tde_skew = kmalloc(sizeof(*de_skew), GFP_KERNEL);\n\tif (!de_skew) {\n\t\tret = -ENOMEM;\n\t\tgoto end;\n\t}\n\n\tp = (u32 *)dts_timing;\n\tfor (i = 0; i < ARRAY_SIZE(rk3328_dts_timing); i++) {\n\t\tret |= of_property_read_u32(np_tim, rk3328_dts_timing[i],\n\t\t\t\t\tp + i);\n\t}\n\tp = (u32 *)de_skew->ca_de_skew;\n\tfor (i = 0; i < ARRAY_SIZE(rk3328_dts_ca_timing); i++) {\n\t\tret |= of_property_read_u32(np_tim, rk3328_dts_ca_timing[i],\n\t\t\t\t\tp + i);\n\t}\n\tp = (u32 *)de_skew->cs0_de_skew;\n\tfor (i = 0; i < ARRAY_SIZE(rk3328_dts_cs0_timing); i++) {\n\t\tret |= of_property_read_u32(np_tim, rk3328_dts_cs0_timing[i],\n\t\t\t\t\tp + i);\n\t}\n\tp = (u32 *)de_skew->cs1_de_skew;\n\tfor (i = 0; i < ARRAY_SIZE(rk3328_dts_cs1_timing); i++) {\n\t\tret |= of_property_read_u32(np_tim, rk3328_dts_cs1_timing[i],\n\t\t\t\t\tp + i);\n\t}\n\tif (!ret)\n\t\trk3328_de_skew_setting_2_register(de_skew, dts_timing);\n\n\tkfree(de_skew);\nend:\n\tif (!ret) {\n\t\tdts_timing->available = 1;\n\t} else {\n\t\tdts_timing->available = 0;\n\t\tdev_err(dev, \"of_get_ddr_timings: fail\\n\");\n\t}\n\n\tof_node_put(np_tim);\n}\n\nstatic int rockchip_ddr_set_auto_self_refresh(uint32_t en)\n{\n\tstruct arm_smccc_res res;\n\n\tddr_psci_param->sr_idle_en = en;\n\n\tarm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ,\n\t\t      SHARE_PAGE_TYPE_DDR, 0, ROCKCHIP_SIP_CONFIG_DRAM_SET_AT_SR,\n\t\t      0, 0, 0, 0, &res);\n\n\treturn res.a0;\n}\n\nstatic int rk3328_dmc_init(struct platform_device *pdev,\n\t\t\t   struct rk3328_dmcfreq *dmcfreq)\n{\n\tstruct arm_smccc_res res;\n\tu32 size, page_num;\n\n\tarm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ,\n\t\t      0, 0, ROCKCHIP_SIP_CONFIG_DRAM_GET_VERSION,\n\t\t      0, 0, 0, 0, &res);\n\tif (res.a0 || (res.a1 < 0x101)) {\n\t\tdev_err(&pdev->dev,\n\t\t\t\"trusted firmware need to update or is invalid\\n\");\n\t\treturn -ENXIO;\n\t}\n\n\tdev_notice(&pdev->dev, \"current ATF version 0x%lx\\n\", res.a1);\n\n\t/*\n\t * first 4KB is used for interface parameters\n\t * after 4KB * N is dts parameters\n\t */\n\tsize = sizeof(struct rk3328_ddr_dts_config_timing);\n\tpage_num = DIV_ROUND_UP(size, 4096) + 1;\n\n\tarm_smccc_smc(ROCKCHIP_SIP_SHARE_MEM,\n\t\t      page_num, SHARE_PAGE_TYPE_DDR, 0,\n\t\t      0, 0, 0, 0, &res);\n\tif (res.a0 != 0) {\n\t\tdev_err(&pdev->dev, \"no ATF memory for init\\n\");\n\t\treturn -ENOMEM;\n\t}\n\n\tddr_psci_param = ioremap(res.a1, page_num << 12);\n\tof_get_rk3328_timings(&pdev->dev, pdev->dev.of_node,\n\t\t\t      (uint32_t *)ddr_psci_param);\n\n\tarm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ,\n\t\t      SHARE_PAGE_TYPE_DDR, 0, ROCKCHIP_SIP_CONFIG_DRAM_INIT,\n\t\t      0, 0, 0, 0, &res);\n\tif (res.a0) {\n\t\tdev_err(&pdev->dev, \"Rockchip dram init error %lx\\n\", res.a0);\n\t\treturn -ENOMEM;\n\t}\n\n\tdmcfreq->set_auto_self_refresh = rockchip_ddr_set_auto_self_refresh;\n\n\treturn 0;\n}\n\nstatic int rk3328_dmcfreq_target(struct device *dev, unsigned long *freq,\n\t\t\t\t u32 flags)\n{\n\tstruct rk3328_dmcfreq *dmcfreq = dev_get_drvdata(dev);\n\tstruct dev_pm_opp *opp;\n\tunsigned long old_clk_rate = dmcfreq->rate;\n\tunsigned long target_volt, target_rate;\n\tint err;\n\n\topp = devfreq_recommended_opp(dev, freq, flags);\n\tif (IS_ERR(opp))\n\t\treturn PTR_ERR(opp);\n\n\ttarget_rate = dev_pm_opp_get_freq(opp);\n\ttarget_volt = dev_pm_opp_get_voltage(opp);\n\tdev_pm_opp_put(opp);\n\n\tif (dmcfreq->rate == target_rate)\n\t\treturn 0;\n\n\tmutex_lock(&dmcfreq->lock);\n\n\t/*\n\t * If frequency scaling from low to high, adjust voltage first.\n\t * If frequency scaling from high to low, adjust frequency first.\n\t */\n\tif (old_clk_rate < target_rate) {\n\t\terr = regulator_set_voltage(dmcfreq->vdd_center, target_volt,\n\t\t\t\t\t    target_volt);\n\t\tif (err) {\n\t\t\tdev_err(dev, \"Cannot set voltage %lu uV\\n\",\n\t\t\t\ttarget_volt);\n\t\t\tgoto out;\n\t\t}\n\t}\n\n\terr = clk_set_rate(dmcfreq->dmc_clk, target_rate);\n\tif (err) {\n\t\tdev_err(dev, \"Cannot set frequency %lu (%d)\\n\", target_rate,\n\t\t\terr);\n\t\tregulator_set_voltage(dmcfreq->vdd_center, dmcfreq->volt,\n\t\t\t\t      dmcfreq->volt);\n\t\tgoto out;\n\t}\n\n\t/*\n\t * Check the dpll rate,\n\t * There only two result we will get,\n\t * 1. Ddr frequency scaling fail, we still get the old rate.\n\t * 2. Ddr frequency scaling sucessful, we get the rate we set.\n\t */\n\tdmcfreq->rate = clk_get_rate(dmcfreq->dmc_clk);\n\n\t/* If get the incorrect rate, set voltage to old value. */\n\tif (dmcfreq->rate != target_rate) {\n\t\tdev_err(dev, \"Got wrong frequency, Request %lu, Current %lu\\n\",\n\t\t\ttarget_rate, dmcfreq->rate);\n\t\tregulator_set_voltage(dmcfreq->vdd_center, dmcfreq->volt,\n\t\t\t\t      dmcfreq->volt);\n\t\tgoto out;\n\t} else if (old_clk_rate > target_rate)\n\t\terr = regulator_set_voltage(dmcfreq->vdd_center, target_volt,\n\t\t\t\t\t    target_volt);\n\tif (err)\n\t\tdev_err(dev, \"Cannot set voltage %lu uV\\n\", target_volt);\n\n\tdmcfreq->rate = target_rate;\n\tdmcfreq->volt = target_volt;\n\nout:\n\tmutex_unlock(&dmcfreq->lock);\n\treturn err;\n}\n\nstatic int rk3328_dmcfreq_get_dev_status(struct device *dev,\n\t\t\t\t\t struct devfreq_dev_status *stat)\n{\n\tstruct rk3328_dmcfreq *dmcfreq = dev_get_drvdata(dev);\n\tstruct devfreq_event_data edata;\n\tint ret = 0;\n\n\tret = devfreq_event_get_event(dmcfreq->edev, &edata);\n\tif (ret < 0)\n\t\treturn ret;\n\n\tstat->current_frequency = dmcfreq->rate;\n\tstat->busy_time = edata.load_count;\n\tstat->total_time = edata.total_count;\n\n\treturn ret;\n}\n\nstatic int rk3328_dmcfreq_get_cur_freq(struct device *dev, unsigned long *freq)\n{\n\tstruct rk3328_dmcfreq *dmcfreq = dev_get_drvdata(dev);\n\n\t*freq = dmcfreq->rate;\n\n\treturn 0;\n}\n\nstatic struct devfreq_dev_profile rk3328_devfreq_dmc_profile = {\n\t.polling_ms\t= 200,\n\t.target\t\t= rk3328_dmcfreq_target,\n\t.get_dev_status\t= rk3328_dmcfreq_get_dev_status,\n\t.get_cur_freq\t= rk3328_dmcfreq_get_cur_freq,\n};\n\nstatic __maybe_unused int rk3328_dmcfreq_suspend(struct device *dev)\n{\n\tstruct rk3328_dmcfreq *dmcfreq = dev_get_drvdata(dev);\n\tint ret = 0;\n\n\tret = devfreq_event_disable_edev(dmcfreq->edev);\n\tif (ret < 0) {\n\t\tdev_err(dev, \"failed to disable the devfreq-event devices\\n\");\n\t\treturn ret;\n\t}\n\n\tret = devfreq_suspend_device(dmcfreq->devfreq);\n\tif (ret < 0) {\n\t\tdev_err(dev, \"failed to suspend the devfreq devices\\n\");\n\t\treturn ret;\n\t}\n\n\treturn 0;\n}\n\nstatic __maybe_unused int rk3328_dmcfreq_resume(struct device *dev)\n{\n\tstruct rk3328_dmcfreq *dmcfreq = dev_get_drvdata(dev);\n\tint ret = 0;\n\n\tret = devfreq_event_enable_edev(dmcfreq->edev);\n\tif (ret < 0) {\n\t\tdev_err(dev, \"failed to enable the devfreq-event devices\\n\");\n\t\treturn ret;\n\t}\n\n\tret = devfreq_resume_device(dmcfreq->devfreq);\n\tif (ret < 0) {\n\t\tdev_err(dev, \"failed to resume the devfreq devices\\n\");\n\t\treturn ret;\n\t}\n\treturn ret;\n}\n\nstatic SIMPLE_DEV_PM_OPS(rk3328_dmcfreq_pm, rk3328_dmcfreq_suspend,\n\t\t\t rk3328_dmcfreq_resume);\n\nstatic int rk3328_dmcfreq_probe(struct platform_device *pdev)\n{\n\tstruct device *dev = &pdev->dev;\n\tstruct device_node *np = pdev->dev.of_node;\n\tstruct rk3328_dmcfreq *data;\n\tstruct dev_pm_opp *opp;\n\tint ret;\n\n\tdata = devm_kzalloc(dev, sizeof(struct rk3328_dmcfreq), GFP_KERNEL);\n\tif (!data)\n\t\treturn -ENOMEM;\n\n\tmutex_init(&data->lock);\n\n\tdata->vdd_center = devm_regulator_get(dev, \"center\");\n\tif (IS_ERR(data->vdd_center)) {\n\t\tif (PTR_ERR(data->vdd_center) == -EPROBE_DEFER)\n\t\t\treturn -EPROBE_DEFER;\n\n\t\tdev_err(dev, \"Cannot get the regulator \\\"center\\\"\\n\");\n\t\treturn PTR_ERR(data->vdd_center);\n\t}\n\n\tdata->dmc_clk = devm_clk_get(dev, \"dmc_clk\");\n\tif (IS_ERR(data->dmc_clk)) {\n\t\tif (PTR_ERR(data->dmc_clk) == -EPROBE_DEFER)\n\t\t\treturn -EPROBE_DEFER;\n\n\t\tdev_err(dev, \"Cannot get the clk dmc_clk\\n\");\n\t\treturn PTR_ERR(data->dmc_clk);\n\t}\n\n#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 9, 0)\n\tdata->edev = devfreq_event_get_edev_by_phandle(dev, 0);\n#else\n\tdata->edev = devfreq_event_get_edev_by_phandle(dev, \"devfreq-events\", 0);\n#endif\n\tif (IS_ERR(data->edev))\n\t\treturn -EPROBE_DEFER;\n\n\tret = devfreq_event_enable_edev(data->edev);\n\tif (ret < 0) {\n\t\tdev_err(dev, \"failed to enable devfreq-event devices\\n\");\n\t\treturn ret;\n\t}\n\n\tret = rk3328_dmc_init(pdev, data);\n\tif (ret)\n\t\treturn ret;\n\n\t/*\n\t * We add a devfreq driver to our parent since it has a device tree node\n\t * with operating points.\n\t */\n\tif (dev_pm_opp_of_add_table(dev)) {\n\t\tdev_err(dev, \"Invalid operating-points in device tree.\\n\");\n\t\treturn -EINVAL;\n\t}\n\n\tof_property_read_u32(np, \"upthreshold\",\n\t\t\t     &data->ondemand_data.upthreshold);\n\tof_property_read_u32(np, \"downdifferential\",\n\t\t\t     &data->ondemand_data.downdifferential);\n\n\tdata->rate = clk_get_rate(data->dmc_clk);\n\n\topp = devfreq_recommended_opp(dev, &data->rate, 0);\n\tif (IS_ERR(opp)) {\n\t\tret = PTR_ERR(opp);\n\t\tgoto err_free_opp;\n\t}\n\n\tdata->rate = dev_pm_opp_get_freq(opp);\n\tdata->volt = dev_pm_opp_get_voltage(opp);\n\tdev_pm_opp_put(opp);\n\n\trk3328_devfreq_dmc_profile.initial_freq = data->rate;\n\n\tdata->devfreq = devm_devfreq_add_device(dev,\n\t\t\t\t\t   &rk3328_devfreq_dmc_profile,\n\t\t\t\t\t   DEVFREQ_GOV_SIMPLE_ONDEMAND,\n\t\t\t\t\t   &data->ondemand_data);\n\tif (IS_ERR(data->devfreq)) {\n\t\tret = PTR_ERR(data->devfreq);\n\t\tgoto err_free_opp;\n\t}\n\n\tdevm_devfreq_register_opp_notifier(dev, data->devfreq);\n\n\tdata->dev = dev;\n\tplatform_set_drvdata(pdev, data);\n\n\treturn 0;\n\nerr_free_opp:\n\tdev_pm_opp_of_remove_table(&pdev->dev);\n\treturn ret;\n}\n\nstatic int rk3328_dmcfreq_remove(struct platform_device *pdev)\n{\n\tstruct rk3328_dmcfreq *dmcfreq = dev_get_drvdata(&pdev->dev);\n\n\t/*\n\t * Before remove the opp table we need to unregister the opp notifier.\n\t */\n\tdevm_devfreq_unregister_opp_notifier(dmcfreq->dev, dmcfreq->devfreq);\n\tdev_pm_opp_of_remove_table(dmcfreq->dev);\n\n\treturn 0;\n}\n\nstatic const struct of_device_id rk3328dmc_devfreq_of_match[] = {\n\t{ .compatible = \"rockchip,rk3328-dmc\" },\n\t{ },\n};\nMODULE_DEVICE_TABLE(of, rk3328dmc_devfreq_of_match);\n\nstatic struct platform_driver rk3328_dmcfreq_driver = {\n\t.probe\t= rk3328_dmcfreq_probe,\n\t.remove = rk3328_dmcfreq_remove,\n\t.driver = {\n\t\t.name\t= \"rk3328-dmc-freq\",\n\t\t.pm\t= &rk3328_dmcfreq_pm,\n\t\t.of_match_table = rk3328dmc_devfreq_of_match,\n\t},\n};\nmodule_platform_driver(rk3328_dmcfreq_driver);\n\nMODULE_LICENSE(\"GPL v2\");\nMODULE_AUTHOR(\"Lin Huang <hl@rock-chips.com>\");\nMODULE_DESCRIPTION(\"RK3328 dmcfreq driver with devfreq framework\");\n"
  },
  {
    "path": "target/linux/rockchip/files/drivers/phy/rockchip/phy-rockchip-inno-usb3.c",
    "content": "/*\n * Rockchip USB 3.0 PHY with Innosilicon IP block driver\n *\n * Copyright (C) 2016 Fuzhou Rockchip Electronics Co., Ltd\n *\n * This program is free software; you can redistribute it and/or modify\n * it under the terms of the GNU General Public License as published by\n * the Free Software Foundation; either version 2 of the License, or\n * (at your option) any later version.\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n * GNU General Public License for more details.\n */\n\n#include <linux/clk.h>\n#include <linux/delay.h>\n#include <linux/debugfs.h>\n#include <linux/gpio/consumer.h>\n#include <linux/interrupt.h>\n#include <linux/io.h>\n#include <linux/kernel.h>\n#include <linux/mfd/syscon.h>\n#include <linux/module.h>\n#include <linux/of.h>\n#include <linux/of_address.h>\n#include <linux/of_irq.h>\n#include <linux/of_platform.h>\n#include <linux/phy/phy.h>\n#include <linux/platform_device.h>\n#include <linux/regmap.h>\n#include <linux/reset.h>\n#include <linux/usb/phy.h>\n#include <linux/uaccess.h>\n\n#define U3PHY_PORT_NUM\t2\n#define U3PHY_MAX_CLKS\t4\n#define BIT_WRITEABLE_SHIFT\t16\n#define SCHEDULE_DELAY\t(60 * HZ)\n\n#define U3PHY_APB_RST\tBIT(0)\n#define U3PHY_POR_RST\tBIT(1)\n#define U3PHY_MAC_RST\tBIT(2)\n\nstruct rockchip_u3phy;\nstruct rockchip_u3phy_port;\n\nenum rockchip_u3phy_type {\n\tU3PHY_TYPE_PIPE,\n\tU3PHY_TYPE_UTMI,\n};\n\nenum rockchip_u3phy_pipe_pwr {\n\tPIPE_PWR_P0\t= 0,\n\tPIPE_PWR_P1\t= 1,\n\tPIPE_PWR_P2\t= 2,\n\tPIPE_PWR_P3\t= 3,\n\tPIPE_PWR_MAX\t= 4,\n};\n\nenum rockchip_u3phy_rest_req {\n\tU3_POR_RSTN\t= 0,\n\tU2_POR_RSTN\t= 1,\n\tPIPE_MAC_RSTN\t= 2,\n\tUTMI_MAC_RSTN\t= 3,\n\tPIPE_APB_RSTN\t= 4,\n\tUTMI_APB_RSTN\t= 5,\n\tU3PHY_RESET_MAX\t= 6,\n};\n\nenum rockchip_u3phy_utmi_state {\n\tPHY_UTMI_HS_ONLINE\t= 0,\n\tPHY_UTMI_DISCONNECT\t= 1,\n\tPHY_UTMI_CONNECT\t= 2,\n\tPHY_UTMI_FS_LS_ONLINE\t= 4,\n};\n\n/*\n * @rvalue: reset value\n * @dvalue: desired value\n */\nstruct u3phy_reg {\n\tunsigned int\toffset;\n\tunsigned int\tbitend;\n\tunsigned int\tbitstart;\n\tunsigned int\trvalue;\n\tunsigned int\tdvalue;\n};\n\nstruct rockchip_u3phy_grfcfg {\n\tstruct u3phy_reg\tum_suspend;\n\tstruct u3phy_reg\tls_det_en;\n\tstruct u3phy_reg\tls_det_st;\n\tstruct u3phy_reg\tum_ls;\n\tstruct u3phy_reg\tum_hstdct;\n\tstruct u3phy_reg\tu2_only_ctrl;\n\tstruct u3phy_reg\tu3_disable;\n\tstruct u3phy_reg\tpp_pwr_st;\n\tstruct u3phy_reg\tpp_pwr_en[PIPE_PWR_MAX];\n};\n\n/**\n * struct rockchip_u3phy_apbcfg: usb3-phy apb configuration.\n * @u2_pre_emp: usb2-phy pre-emphasis tuning.\n * @u2_pre_emp_sth: usb2-phy pre-emphasis strength tuning.\n * @u2_odt_tuning: usb2-phy odt 45ohm tuning.\n */\nstruct rockchip_u3phy_apbcfg {\n\tunsigned int\tu2_pre_emp;\n\tunsigned int\tu2_pre_emp_sth;\n\tunsigned int\tu2_odt_tuning;\n};\n\nstruct rockchip_u3phy_cfg {\n\tunsigned int reg;\n\tconst struct rockchip_u3phy_grfcfg grfcfg;\n\n\tint (*phy_pipe_power)(struct rockchip_u3phy *,\n\t\t\t      struct rockchip_u3phy_port *,\n\t\t\t      bool on);\n\tint (*phy_tuning)(struct rockchip_u3phy *,\n\t\t\t  struct rockchip_u3phy_port *,\n\t\t\t  struct device_node *);\n\tint (*phy_cp_test)(struct rockchip_u3phy *,\n\t\t\t   struct rockchip_u3phy_port *);\n};\n\nstruct rockchip_u3phy_port {\n\tstruct phy\t*phy;\n\tvoid __iomem\t*base;\n\tunsigned int\tindex;\n\tunsigned char\ttype;\n\tbool\t\tsuspended;\n\tbool\t\trefclk_25m_quirk;\n\tstruct mutex\tmutex; /* mutex for updating register */\n\tstruct delayed_work\tum_sm_work;\n};\n\nstruct rockchip_u3phy {\n\tstruct device *dev;\n\tstruct regmap *u3phy_grf;\n\tstruct regmap *grf;\n\tint um_ls_irq;\n\tstruct clk *clks[U3PHY_MAX_CLKS];\n\tstruct dentry *root;\n\tstruct regulator *vbus;\n\tstruct reset_control *rsts[U3PHY_RESET_MAX];\n\tstruct rockchip_u3phy_apbcfg apbcfg;\n\tconst struct rockchip_u3phy_cfg *cfgs;\n\tstruct rockchip_u3phy_port ports[U3PHY_PORT_NUM];\n\tstruct usb_phy usb_phy;\n\tbool vbus_enabled;\n};\n\nstatic inline int param_write(void __iomem *base,\n\t\t\t      const struct u3phy_reg *reg, bool desired)\n{\n\tunsigned int val, mask;\n\tunsigned int tmp = desired ? reg->dvalue : reg->rvalue;\n\tint ret = 0;\n\n\tmask = GENMASK(reg->bitend, reg->bitstart);\n\tval = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT);\n\tret = regmap_write(base, reg->offset, val);\n\n\treturn ret;\n}\n\nstatic inline bool param_exped(void __iomem *base,\n\t\t\t       const struct u3phy_reg *reg,\n\t\t\t       unsigned int value)\n{\n\tint ret;\n\tunsigned int tmp, orig;\n\tunsigned int mask = GENMASK(reg->bitend, reg->bitstart);\n\n\tret = regmap_read(base, reg->offset, &orig);\n\tif (ret)\n\t\treturn false;\n\n\ttmp = (orig & mask) >> reg->bitstart;\n\treturn tmp == value;\n}\n\nstatic int rockchip_set_vbus_power(struct rockchip_u3phy *u3phy, bool en)\n{\n\tint ret = 0;\n\n\tif (!u3phy->vbus)\n\t\treturn 0;\n\n\tif (en && !u3phy->vbus_enabled) {\n\t\tret = regulator_enable(u3phy->vbus);\n\t\tif (ret)\n\t\t\tdev_err(u3phy->dev,\n\t\t\t\t\"Failed to enable VBUS supply\\n\");\n\t} else if (!en && u3phy->vbus_enabled) {\n\t\tret = regulator_disable(u3phy->vbus);\n\t}\n\n\tif (ret == 0)\n\t\tu3phy->vbus_enabled = en;\n\n\treturn ret;\n}\n\nstatic int rockchip_u3phy_usb2_only_show(struct seq_file *s, void *unused)\n{\n\tstruct rockchip_u3phy\t*u3phy = s->private;\n\n\tif (param_exped(u3phy->u3phy_grf, &u3phy->cfgs->grfcfg.u2_only_ctrl, 1))\n\t\tdev_info(u3phy->dev, \"u2\\n\");\n\telse\n\t\tdev_info(u3phy->dev, \"u3\\n\");\n\n\treturn 0;\n}\n\nstatic int rockchip_u3phy_usb2_only_open(struct inode *inode,\n\t\t\t\t\t struct file *file)\n{\n\treturn single_open(file, rockchip_u3phy_usb2_only_show,\n\t\t\t   inode->i_private);\n}\n\nstatic ssize_t rockchip_u3phy_usb2_only_write(struct file *file,\n\t\t\t\t\t      const char __user *ubuf,\n\t\t\t\t\t      size_t count, loff_t *ppos)\n{\n\tstruct seq_file\t\t\t*s = file->private_data;\n\tstruct rockchip_u3phy\t\t*u3phy = s->private;\n\tstruct rockchip_u3phy_port\t*u3phy_port;\n\tchar\t\t\t\tbuf[32];\n\tu8\t\t\t\tindex;\n\n\tif (copy_from_user(&buf, ubuf, min_t(size_t, sizeof(buf) - 1, count)))\n\t\treturn -EFAULT;\n\n\tif (!strncmp(buf, \"u3\", 2) &&\n\t    param_exped(u3phy->u3phy_grf,\n\t\t\t&u3phy->cfgs->grfcfg.u2_only_ctrl, 1)) {\n\t\tdev_info(u3phy->dev, \"Set usb3.0 and usb2.0 mode successfully\\n\");\n\n\t\trockchip_set_vbus_power(u3phy, false);\n\n\t\tparam_write(u3phy->grf,\n\t\t\t    &u3phy->cfgs->grfcfg.u3_disable, false);\n\t\tparam_write(u3phy->u3phy_grf,\n\t\t\t    &u3phy->cfgs->grfcfg.u2_only_ctrl, false);\n\n\t\tfor (index = 0; index < U3PHY_PORT_NUM; index++) {\n\t\t\tu3phy_port = &u3phy->ports[index];\n\t\t\t/* enable u3 rx termimation */\n\t\t\tif (u3phy_port->type == U3PHY_TYPE_PIPE)\n\t\t\t\twritel(0x30, u3phy_port->base + 0xd8);\n\t\t}\n\n\t\tatomic_notifier_call_chain(&u3phy->usb_phy.notifier, 0, NULL);\n\n\t\trockchip_set_vbus_power(u3phy, true);\n\t} else if (!strncmp(buf, \"u2\", 2) &&\n\t\t   param_exped(u3phy->u3phy_grf,\n\t\t\t       &u3phy->cfgs->grfcfg.u2_only_ctrl, 0)) {\n\t\tdev_info(u3phy->dev, \"Set usb2.0 only mode successfully\\n\");\n\n\t\trockchip_set_vbus_power(u3phy, false);\n\n\t\tparam_write(u3phy->grf,\n\t\t\t    &u3phy->cfgs->grfcfg.u3_disable, true);\n\t\tparam_write(u3phy->u3phy_grf,\n\t\t\t    &u3phy->cfgs->grfcfg.u2_only_ctrl, true);\n\n\t\tfor (index = 0; index < U3PHY_PORT_NUM; index++) {\n\t\t\tu3phy_port = &u3phy->ports[index];\n\t\t\t/* disable u3 rx termimation */\n\t\t\tif (u3phy_port->type == U3PHY_TYPE_PIPE)\n\t\t\t\twritel(0x20, u3phy_port->base + 0xd8);\n\t\t}\n\n\t\tatomic_notifier_call_chain(&u3phy->usb_phy.notifier, 0, NULL);\n\n\t\trockchip_set_vbus_power(u3phy, true);\n\t} else {\n\t\tdev_info(u3phy->dev, \"Same or illegal mode\\n\");\n\t}\n\n\treturn count;\n}\n\nstatic const struct file_operations rockchip_u3phy_usb2_only_fops = {\n\t.open\t\t\t= rockchip_u3phy_usb2_only_open,\n\t.write\t\t\t= rockchip_u3phy_usb2_only_write,\n\t.read\t\t\t= seq_read,\n\t.llseek\t\t\t= seq_lseek,\n\t.release\t\t= single_release,\n};\n\nint rockchip_u3phy_debugfs_init(struct rockchip_u3phy *u3phy)\n{\n\tstruct dentry\t\t*root;\n\tstruct dentry\t\t*file;\n\tint\t\t\tret;\n\n\troot = debugfs_create_dir(dev_name(u3phy->dev), NULL);\n\tif (!root) {\n\t\tret = -ENOMEM;\n\t\tgoto err0;\n\t}\n\n\tu3phy->root = root;\n\n\tfile = debugfs_create_file(\"u3phy_mode\", 0644, root,\n\t\t\t\t   u3phy, &rockchip_u3phy_usb2_only_fops);\n\tif (!file) {\n\t\tret = -ENOMEM;\n\t\tgoto err1;\n\t}\n\treturn 0;\n\nerr1:\n\tdebugfs_remove_recursive(root);\nerr0:\n\treturn ret;\n}\n\nstatic const char *get_rest_name(enum rockchip_u3phy_rest_req rst)\n{\n\tswitch (rst) {\n\tcase U2_POR_RSTN:\n\t\treturn \"u3phy-u2-por\";\n\tcase U3_POR_RSTN:\n\t\treturn \"u3phy-u3-por\";\n\tcase PIPE_MAC_RSTN:\n\t\treturn \"u3phy-pipe-mac\";\n\tcase UTMI_MAC_RSTN:\n\t\treturn \"u3phy-utmi-mac\";\n\tcase UTMI_APB_RSTN:\n\t\treturn \"u3phy-utmi-apb\";\n\tcase PIPE_APB_RSTN:\n\t\treturn \"u3phy-pipe-apb\";\n\tdefault:\n\t\treturn \"invalid\";\n\t}\n}\n\nstatic void rockchip_u3phy_rest_deassert(struct rockchip_u3phy *u3phy,\n\t\t\t\t\t unsigned int flag)\n{\n\tint rst;\n\n\tif (flag & U3PHY_APB_RST) {\n\t\tdev_dbg(u3phy->dev, \"deassert APB bus interface reset\\n\");\n\t\tfor (rst = PIPE_APB_RSTN; rst <= UTMI_APB_RSTN; rst++) {\n\t\t\tif (u3phy->rsts[rst])\n\t\t\t\treset_control_deassert(u3phy->rsts[rst]);\n\t\t}\n\t}\n\n\tif (flag & U3PHY_POR_RST) {\n\t\tusleep_range(12, 15);\n\t\tdev_dbg(u3phy->dev, \"deassert u2 and u3 phy power on reset\\n\");\n\t\tfor (rst = U3_POR_RSTN; rst <= U2_POR_RSTN; rst++) {\n\t\t\tif (u3phy->rsts[rst])\n\t\t\t\treset_control_deassert(u3phy->rsts[rst]);\n\t\t}\n\t}\n\n\tif (flag & U3PHY_MAC_RST) {\n\t\tusleep_range(1200, 1500);\n\t\tdev_dbg(u3phy->dev, \"deassert pipe and utmi MAC reset\\n\");\n\t\tfor (rst = PIPE_MAC_RSTN; rst <= UTMI_MAC_RSTN; rst++)\n\t\t\tif (u3phy->rsts[rst])\n\t\t\t\treset_control_deassert(u3phy->rsts[rst]);\n\t}\n}\n\nstatic void rockchip_u3phy_rest_assert(struct rockchip_u3phy *u3phy)\n{\n\tint rst;\n\n\tdev_dbg(u3phy->dev, \"assert u3phy reset\\n\");\n\tfor (rst = 0; rst < U3PHY_RESET_MAX; rst++)\n\t\tif (u3phy->rsts[rst])\n\t\t\treset_control_assert(u3phy->rsts[rst]);\n}\n\nstatic int rockchip_u3phy_clk_enable(struct rockchip_u3phy *u3phy)\n{\n\tint ret, clk;\n\n\tfor (clk = 0; clk < U3PHY_MAX_CLKS && u3phy->clks[clk]; clk++) {\n\t\tret = clk_prepare_enable(u3phy->clks[clk]);\n\t\tif (ret)\n\t\t\tgoto err_disable_clks;\n\t}\n\treturn 0;\n\nerr_disable_clks:\n\twhile (--clk >= 0)\n\t\tclk_disable_unprepare(u3phy->clks[clk]);\n\treturn ret;\n}\n\nstatic void rockchip_u3phy_clk_disable(struct rockchip_u3phy *u3phy)\n{\n\tint clk;\n\n\tfor (clk = U3PHY_MAX_CLKS - 1; clk >= 0; clk--)\n\t\tif (u3phy->clks[clk])\n\t\t\tclk_disable_unprepare(u3phy->clks[clk]);\n}\n\nstatic int rockchip_u3phy_init(struct phy *phy)\n{\n\treturn 0;\n}\n\nstatic int rockchip_u3phy_exit(struct phy *phy)\n{\n\treturn 0;\n}\n\nstatic int rockchip_u3phy_power_on(struct phy *phy)\n{\n\tstruct rockchip_u3phy_port *u3phy_port = phy_get_drvdata(phy);\n\tstruct rockchip_u3phy *u3phy = dev_get_drvdata(phy->dev.parent);\n\tint ret;\n\n\tdev_info(&u3phy_port->phy->dev, \"u3phy %s power on\\n\",\n\t\t (u3phy_port->type == U3PHY_TYPE_UTMI) ? \"u2\" : \"u3\");\n\n\tif (!u3phy_port->suspended)\n\t\treturn 0;\n\n\tret = rockchip_u3phy_clk_enable(u3phy);\n\tif (ret)\n\t\treturn ret;\n\n\tif (u3phy_port->type == U3PHY_TYPE_UTMI) {\n\t\tparam_write(u3phy->u3phy_grf,\n\t\t\t    &u3phy->cfgs->grfcfg.um_suspend, false);\n\t} else {\n\t\t/* current in p2 ? */\n\t\tif (param_exped(u3phy->u3phy_grf,\n\t\t\t\t&u3phy->cfgs->grfcfg.pp_pwr_st, PIPE_PWR_P2))\n\t\t\tgoto done;\n\n\t\tif (u3phy->cfgs->phy_pipe_power) {\n\t\t\tdev_dbg(u3phy->dev, \"do pipe power up\\n\");\n\t\t\tu3phy->cfgs->phy_pipe_power(u3phy, u3phy_port, true);\n\t\t}\n\n\t\t/* exit to p0 */\n\t\tparam_write(u3phy->u3phy_grf,\n\t\t\t    &u3phy->cfgs->grfcfg.pp_pwr_en[PIPE_PWR_P0], true);\n\t\tusleep_range(90, 100);\n\n\t\t/* enter to p2 from p0 */\n\t\tparam_write(u3phy->u3phy_grf,\n\t\t\t    &u3phy->cfgs->grfcfg.pp_pwr_en[PIPE_PWR_P2],\n\t\t\t    false);\n\t\tudelay(3);\n\t}\n\ndone:\n\trockchip_set_vbus_power(u3phy, true);\n\tu3phy_port->suspended = false;\n\treturn 0;\n}\n\nstatic int rockchip_u3phy_power_off(struct phy *phy)\n{\n\tstruct rockchip_u3phy_port *u3phy_port = phy_get_drvdata(phy);\n\tstruct rockchip_u3phy *u3phy = dev_get_drvdata(phy->dev.parent);\n\n\tdev_info(&u3phy_port->phy->dev, \"u3phy %s power off\\n\",\n\t\t (u3phy_port->type == U3PHY_TYPE_UTMI) ? \"u2\" : \"u3\");\n\n\tif (u3phy_port->suspended)\n\t\treturn 0;\n\n\tif (u3phy_port->type == U3PHY_TYPE_UTMI) {\n\t\tparam_write(u3phy->u3phy_grf,\n\t\t\t    &u3phy->cfgs->grfcfg.um_suspend, true);\n\t} else {\n\t\t/* current in p3 ? */\n\t\tif (param_exped(u3phy->u3phy_grf,\n\t\t\t\t&u3phy->cfgs->grfcfg.pp_pwr_st, PIPE_PWR_P3))\n\t\t\tgoto done;\n\n\t\t/* exit to p0 */\n\t\tparam_write(u3phy->u3phy_grf,\n\t\t\t    &u3phy->cfgs->grfcfg.pp_pwr_en[PIPE_PWR_P0], true);\n\t\tudelay(2);\n\n\t\t/* enter to p3 from p0 */\n\t\tparam_write(u3phy->u3phy_grf,\n\t\t\t    &u3phy->cfgs->grfcfg.pp_pwr_en[PIPE_PWR_P3], true);\n\t\tudelay(6);\n\n\t\tif (u3phy->cfgs->phy_pipe_power) {\n\t\t\tdev_dbg(u3phy->dev, \"do pipe power down\\n\");\n\t\t\tu3phy->cfgs->phy_pipe_power(u3phy, u3phy_port, false);\n\t\t}\n\t}\n\ndone:\n\trockchip_u3phy_clk_disable(u3phy);\n\tu3phy_port->suspended = true;\n\treturn 0;\n}\n\nstatic __maybe_unused int rockchip_u3phy_cp_test(struct phy *phy)\n{\n\tstruct rockchip_u3phy_port *u3phy_port = phy_get_drvdata(phy);\n\tstruct rockchip_u3phy *u3phy = dev_get_drvdata(phy->dev.parent);\n\tint ret;\n\n\tif (u3phy->cfgs->phy_cp_test) {\n\t\t/*\n\t\t * When do USB3 compliance test, we may connect the oscilloscope\n\t\t * front panel Aux Out to the DUT SSRX+, the Aux Out of the\n\t\t * oscilloscope outputs a negative pulse whose width is between\n\t\t * 300- 400 ns which may trigger some DUTs to change the CP test\n\t\t * pattern.\n\t\t *\n\t\t * The Inno USB3 PHY disable the function to detect the negative\n\t\t * pulse in SSRX+ by default, so we need to enable the function\n\t\t * to toggle the CP test pattern before do USB3 compliance test.\n\t\t */\n\t\tdev_dbg(u3phy->dev, \"prepare for u3phy compliance test\\n\");\n\t\tret = u3phy->cfgs->phy_cp_test(u3phy, u3phy_port);\n\t\tif (ret)\n\t\t\treturn ret;\n\t}\n\n\treturn 0;\n}\n\nstatic __maybe_unused\nstruct phy *rockchip_u3phy_xlate(struct device *dev,\n\t\t\t\t struct of_phandle_args *args)\n{\n\tstruct rockchip_u3phy *u3phy = dev_get_drvdata(dev);\n\tstruct rockchip_u3phy_port *u3phy_port = NULL;\n\tstruct device_node *phy_np = args->np;\n\tint index;\n\n\tif (args->args_count != 1) {\n\t\tdev_err(dev, \"invalid number of cells in 'phy' property\\n\");\n\t\treturn ERR_PTR(-EINVAL);\n\t}\n\n\tfor (index = 0; index < U3PHY_PORT_NUM; index++) {\n\t\tif (phy_np == u3phy->ports[index].phy->dev.of_node) {\n\t\t\tu3phy_port = &u3phy->ports[index];\n\t\t\tbreak;\n\t\t}\n\t}\n\n\tif (!u3phy_port) {\n\t\tdev_err(dev, \"failed to find appropriate phy\\n\");\n\t\treturn ERR_PTR(-EINVAL);\n\t}\n\n\treturn u3phy_port->phy;\n}\n\nstatic struct phy_ops rockchip_u3phy_ops = {\n\t.init\t\t= rockchip_u3phy_init,\n\t.exit\t\t= rockchip_u3phy_exit,\n\t.power_on\t= rockchip_u3phy_power_on,\n\t.power_off\t= rockchip_u3phy_power_off,\n\t.owner\t\t= THIS_MODULE,\n};\n\n/*\n * The function manage host-phy port state and suspend/resume phy port\n * to save power automatically.\n *\n * we rely on utmi_linestate and utmi_hostdisconnect to identify whether\n * devices is disconnect or not. Besides, we do not need care it is FS/LS\n * disconnected or HS disconnected, actually, we just only need get the\n * device is disconnected at last through rearm the delayed work,\n * to suspend the phy port in _PHY_STATE_DISCONNECT_ case.\n */\nstatic void rockchip_u3phy_um_sm_work(struct work_struct *work)\n{\n\tstruct rockchip_u3phy_port *u3phy_port =\n\t\tcontainer_of(work, struct rockchip_u3phy_port, um_sm_work.work);\n\tstruct rockchip_u3phy *u3phy =\n\t\tdev_get_drvdata(u3phy_port->phy->dev.parent);\n\tunsigned int sh = u3phy->cfgs->grfcfg.um_hstdct.bitend -\n\t\t\tu3phy->cfgs->grfcfg.um_hstdct.bitstart + 1;\n\tunsigned int ul, uhd, state;\n\tunsigned int ul_mask, uhd_mask;\n\tint ret;\n\n\tmutex_lock(&u3phy_port->mutex);\n\n\tret = regmap_read(u3phy->u3phy_grf,\n\t\t\t  u3phy->cfgs->grfcfg.um_ls.offset, &ul);\n\tif (ret < 0)\n\t\tgoto next_schedule;\n\n\tret = regmap_read(u3phy->u3phy_grf,\n\t\t\t  u3phy->cfgs->grfcfg.um_hstdct.offset, &uhd);\n\tif (ret < 0)\n\t\tgoto next_schedule;\n\n\tuhd_mask = GENMASK(u3phy->cfgs->grfcfg.um_hstdct.bitend,\n\t\t\t   u3phy->cfgs->grfcfg.um_hstdct.bitstart);\n\tul_mask = GENMASK(u3phy->cfgs->grfcfg.um_ls.bitend,\n\t\t\t  u3phy->cfgs->grfcfg.um_ls.bitstart);\n\n\t/* stitch on um_ls and um_hstdct as phy state */\n\tstate = ((uhd & uhd_mask) >> u3phy->cfgs->grfcfg.um_hstdct.bitstart) |\n\t\t(((ul & ul_mask) >> u3phy->cfgs->grfcfg.um_ls.bitstart) << sh);\n\n\tswitch (state) {\n\tcase PHY_UTMI_HS_ONLINE:\n\t\tdev_dbg(&u3phy_port->phy->dev, \"HS online\\n\");\n\t\tbreak;\n\tcase PHY_UTMI_FS_LS_ONLINE:\n\t\t/*\n\t\t * For FS/LS device, the online state share with connect state\n\t\t * from um_ls and um_hstdct register, so we distinguish\n\t\t * them via suspended flag.\n\t\t *\n\t\t * Plus, there are two cases, one is D- Line pull-up, and D+\n\t\t * line pull-down, the state is 4; another is D+ line pull-up,\n\t\t * and D- line pull-down, the state is 2.\n\t\t */\n\t\tif (!u3phy_port->suspended) {\n\t\t\t/* D- line pull-up, D+ line pull-down */\n\t\t\tdev_dbg(&u3phy_port->phy->dev, \"FS/LS online\\n\");\n\t\t\tbreak;\n\t\t}\n\t\t/* fall through */\n\tcase PHY_UTMI_CONNECT:\n\t\tif (u3phy_port->suspended) {\n\t\t\tdev_dbg(&u3phy_port->phy->dev, \"Connected\\n\");\n\t\t\trockchip_u3phy_power_on(u3phy_port->phy);\n\t\t\tu3phy_port->suspended = false;\n\t\t} else {\n\t\t\t/* D+ line pull-up, D- line pull-down */\n\t\t\tdev_dbg(&u3phy_port->phy->dev, \"FS/LS online\\n\");\n\t\t}\n\t\tbreak;\n\tcase PHY_UTMI_DISCONNECT:\n\t\tif (!u3phy_port->suspended) {\n\t\t\tdev_dbg(&u3phy_port->phy->dev, \"Disconnected\\n\");\n\t\t\trockchip_u3phy_power_off(u3phy_port->phy);\n\t\t\tu3phy_port->suspended = true;\n\t\t}\n\n\t\t/*\n\t\t * activate the linestate detection to get the next device\n\t\t * plug-in irq.\n\t\t */\n\t\tparam_write(u3phy->u3phy_grf,\n\t\t\t    &u3phy->cfgs->grfcfg.ls_det_st, true);\n\t\tparam_write(u3phy->u3phy_grf,\n\t\t\t    &u3phy->cfgs->grfcfg.ls_det_en, true);\n\n\t\t/*\n\t\t * we don't need to rearm the delayed work when the phy port\n\t\t * is suspended.\n\t\t */\n\t\tmutex_unlock(&u3phy_port->mutex);\n\t\treturn;\n\tdefault:\n\t\tdev_dbg(&u3phy_port->phy->dev, \"unknown phy state\\n\");\n\t\tbreak;\n\t}\n\nnext_schedule:\n\tmutex_unlock(&u3phy_port->mutex);\n\tschedule_delayed_work(&u3phy_port->um_sm_work, SCHEDULE_DELAY);\n}\n\nstatic irqreturn_t rockchip_u3phy_um_ls_irq(int irq, void *data)\n{\n\tstruct rockchip_u3phy_port *u3phy_port = data;\n\tstruct rockchip_u3phy *u3phy =\n\t\tdev_get_drvdata(u3phy_port->phy->dev.parent);\n\n\tif (!param_exped(u3phy->u3phy_grf,\n\t\t\t &u3phy->cfgs->grfcfg.ls_det_st,\n\t\t\t u3phy->cfgs->grfcfg.ls_det_st.dvalue))\n\t\treturn IRQ_NONE;\n\n\tdev_dbg(u3phy->dev, \"utmi linestate interrupt\\n\");\n\tmutex_lock(&u3phy_port->mutex);\n\n\t/* disable linestate detect irq and clear its status */\n\tparam_write(u3phy->u3phy_grf, &u3phy->cfgs->grfcfg.ls_det_en, false);\n\tparam_write(u3phy->u3phy_grf, &u3phy->cfgs->grfcfg.ls_det_st, true);\n\n\tmutex_unlock(&u3phy_port->mutex);\n\n\t/*\n\t * In this case for host phy, a new device is plugged in, meanwhile,\n\t * if the phy port is suspended, we need rearm the work to resume it\n\t * and mange its states; otherwise, we just return irq handled.\n\t */\n\tif (u3phy_port->suspended) {\n\t\tdev_dbg(u3phy->dev, \"schedule utmi sm work\\n\");\n\t\trockchip_u3phy_um_sm_work(&u3phy_port->um_sm_work.work);\n\t}\n\n\treturn IRQ_HANDLED;\n}\n\nstatic int rockchip_u3phy_parse_dt(struct rockchip_u3phy *u3phy,\n\t\t\t\t   struct platform_device *pdev)\n\n{\n\tstruct device *dev = &pdev->dev;\n\tstruct device_node *np = dev->of_node;\n\tint ret, i, clk;\n\n\tu3phy->um_ls_irq = platform_get_irq_byname(pdev, \"linestate\");\n\tif (u3phy->um_ls_irq < 0) {\n\t\tdev_err(dev, \"get utmi linestate irq failed\\n\");\n\t\treturn -ENXIO;\n\t}\n\n\t/* Get Vbus regulators */\n\tu3phy->vbus = devm_regulator_get_optional(dev, \"vbus\");\n\tif (IS_ERR(u3phy->vbus)) {\n\t\tret = PTR_ERR(u3phy->vbus);\n\t\tif (ret == -EPROBE_DEFER)\n\t\t\treturn ret;\n\n\t\tdev_warn(dev, \"Failed to get VBUS supply regulator\\n\");\n\t\tu3phy->vbus = NULL;\n\t}\n\n\tfor (clk = 0; clk < U3PHY_MAX_CLKS; clk++) {\n\t\tu3phy->clks[clk] = of_clk_get(np, clk);\n\t\tif (IS_ERR(u3phy->clks[clk])) {\n\t\t\tret = PTR_ERR(u3phy->clks[clk]);\n\t\t\tif (ret == -EPROBE_DEFER)\n\t\t\t\tgoto err_put_clks;\n\t\t\tu3phy->clks[clk] = NULL;\n\t\t\tbreak;\n\t\t}\n\t}\n\n\tfor (i = 0; i < U3PHY_RESET_MAX; i++) {\n\t\tu3phy->rsts[i] = devm_reset_control_get(dev, get_rest_name(i));\n\t\tif (IS_ERR(u3phy->rsts[i])) {\n\t\t\tdev_info(dev, \"no %s reset control specified\\n\",\n\t\t\t\t get_rest_name(i));\n\t\t\tu3phy->rsts[i] = NULL;\n\t\t}\n\t}\n\n\treturn 0;\n\nerr_put_clks:\n\twhile (--clk >= 0)\n\t\tclk_put(u3phy->clks[clk]);\n\treturn ret;\n}\n\nstatic int rockchip_u3phy_port_init(struct rockchip_u3phy *u3phy,\n\t\t\t\t    struct rockchip_u3phy_port *u3phy_port,\n\t\t\t\t    struct device_node *child_np)\n{\n\tstruct resource res;\n\tstruct phy *phy;\n\tint ret;\n\n\tdev_dbg(u3phy->dev, \"u3phy port initialize\\n\");\n\n\tmutex_init(&u3phy_port->mutex);\n\tu3phy_port->suspended = true; /* initial status */\n\n\tphy = devm_phy_create(u3phy->dev, child_np, &rockchip_u3phy_ops);\n\tif (IS_ERR(phy)) {\n\t\tdev_err(u3phy->dev, \"failed to create phy\\n\");\n\t\treturn PTR_ERR(phy);\n\t}\n\n\tu3phy_port->phy = phy;\n\n\tret = of_address_to_resource(child_np, 0, &res);\n\tif (ret) {\n\t\tdev_err(u3phy->dev, \"failed to get address resource(np-%s)\\n\",\n\t\t\tchild_np->name);\n\t\treturn ret;\n\t}\n\n\tu3phy_port->base = devm_ioremap_resource(&u3phy_port->phy->dev, &res);\n\tif (IS_ERR(u3phy_port->base)) {\n\t\tdev_err(u3phy->dev, \"failed to remap phy regs\\n\");\n\t\treturn PTR_ERR(u3phy_port->base);\n\t}\n\n\tif (!of_node_cmp(child_np->name, \"pipe\")) {\n\t\tu3phy_port->type = U3PHY_TYPE_PIPE;\n\t\tu3phy_port->refclk_25m_quirk =\n\t\t\tof_property_read_bool(child_np,\n\t\t\t\t\t      \"rockchip,refclk-25m-quirk\");\n\t} else {\n\t\tu3phy_port->type = U3PHY_TYPE_UTMI;\n\t\tINIT_DELAYED_WORK(&u3phy_port->um_sm_work,\n\t\t\t\t  rockchip_u3phy_um_sm_work);\n\n\t\tret = devm_request_threaded_irq(u3phy->dev, u3phy->um_ls_irq,\n\t\t\t\t\t\tNULL, rockchip_u3phy_um_ls_irq,\n\t\t\t\t\t\tIRQF_ONESHOT, \"rockchip_u3phy\",\n\t\t\t\t\t\tu3phy_port);\n\t\tif (ret) {\n\t\t\tdev_err(u3phy->dev, \"failed to request utmi linestate irq handle\\n\");\n\t\t\treturn ret;\n\t\t}\n\t}\n\n\tif (u3phy->cfgs->phy_tuning) {\n\t\tdev_dbg(u3phy->dev, \"do u3phy tuning\\n\");\n\t\tret = u3phy->cfgs->phy_tuning(u3phy, u3phy_port, child_np);\n\t\tif (ret)\n\t\t\treturn ret;\n\t}\n\n\tphy_set_drvdata(u3phy_port->phy, u3phy_port);\n\treturn 0;\n}\n\nstatic int rockchip_u3phy_on_init(struct usb_phy *usb_phy)\n{\n\tstruct rockchip_u3phy *u3phy =\n\t\tcontainer_of(usb_phy, struct rockchip_u3phy, usb_phy);\n\n\trockchip_u3phy_rest_deassert(u3phy, U3PHY_POR_RST | U3PHY_MAC_RST);\n\treturn 0;\n}\n\nstatic void rockchip_u3phy_on_shutdown(struct usb_phy *usb_phy)\n{\n\tstruct rockchip_u3phy *u3phy =\n\t\tcontainer_of(usb_phy, struct rockchip_u3phy, usb_phy);\n\tint rst;\n\n\tfor (rst = 0; rst < U3PHY_RESET_MAX; rst++)\n\t\tif (u3phy->rsts[rst] && rst != UTMI_APB_RSTN &&\n\t\t    rst != PIPE_APB_RSTN)\n\t\t\treset_control_assert(u3phy->rsts[rst]);\n\tudelay(1);\n}\n\nstatic int rockchip_u3phy_on_disconnect(struct usb_phy *usb_phy,\n\t\t\t\t\tenum usb_device_speed speed)\n{\n\tstruct rockchip_u3phy *u3phy =\n\t\tcontainer_of(usb_phy, struct rockchip_u3phy, usb_phy);\n\n\tdev_info(u3phy->dev, \"%s device has disconnected\\n\",\n\t\t (speed == USB_SPEED_SUPER) ? \"U3\" : \"UW/U2/U1.1/U1\");\n\n\tif (speed == USB_SPEED_SUPER)\n\t\tatomic_notifier_call_chain(&usb_phy->notifier, 0, NULL);\n\n\treturn 0;\n}\n\nstatic int rockchip_u3phy_probe(struct platform_device *pdev)\n{\n\tstruct device *dev = &pdev->dev;\n\tstruct device_node *np = dev->of_node;\n\tstruct device_node *child_np;\n\tstruct phy_provider *provider;\n\tstruct rockchip_u3phy *u3phy;\n\tconst struct rockchip_u3phy_cfg *phy_cfgs;\n\tconst struct of_device_id *match;\n\tunsigned int reg[2];\n\tint index, ret;\n\n\tmatch = of_match_device(dev->driver->of_match_table, dev);\n\tif (!match || !match->data) {\n\t\tdev_err(dev, \"phy-cfgs are not assigned!\\n\");\n\t\treturn -EINVAL;\n\t}\n\n\tu3phy = devm_kzalloc(dev, sizeof(*u3phy), GFP_KERNEL);\n\tif (!u3phy)\n\t\treturn -ENOMEM;\n\n\tu3phy->u3phy_grf =\n\t\tsyscon_regmap_lookup_by_phandle(np, \"rockchip,u3phygrf\");\n\tif (IS_ERR(u3phy->u3phy_grf))\n\t\treturn PTR_ERR(u3phy->u3phy_grf);\n\n\tu3phy->grf =\n\t\tsyscon_regmap_lookup_by_phandle(np, \"rockchip,grf\");\n\tif (IS_ERR(u3phy->grf)) {\n\t\tdev_err(dev, \"Missing rockchip,grf property\\n\");\n\t\treturn PTR_ERR(u3phy->grf);\n\t}\n\n\tif (of_property_read_u32_array(np, \"reg\", reg, 2)) {\n\t\tdev_err(dev, \"the reg property is not assigned in %s node\\n\",\n\t\t\tnp->name);\n\t\treturn -EINVAL;\n\t}\n\n\tu3phy->dev = dev;\n\tu3phy->vbus_enabled = false;\n\tphy_cfgs = match->data;\n\tplatform_set_drvdata(pdev, u3phy);\n\n\t/* find out a proper config which can be matched with dt. */\n\tindex = 0;\n\twhile (phy_cfgs[index].reg) {\n\t\tif (phy_cfgs[index].reg == reg[1]) {\n\t\t\tu3phy->cfgs = &phy_cfgs[index];\n\t\t\tbreak;\n\t\t}\n\n\t\t++index;\n\t}\n\n\tif (!u3phy->cfgs) {\n\t\tdev_err(dev, \"no phy-cfgs can be matched with %s node\\n\",\n\t\t\tnp->name);\n\t\treturn -EINVAL;\n\t}\n\n\tret = rockchip_u3phy_parse_dt(u3phy, pdev);\n\tif (ret) {\n\t\tdev_err(dev, \"parse dt failed, ret(%d)\\n\", ret);\n\t\treturn ret;\n\t}\n\n\tret = rockchip_u3phy_clk_enable(u3phy);\n\tif (ret) {\n\t\tdev_err(dev, \"clk enable failed, ret(%d)\\n\", ret);\n\t\treturn ret;\n\t}\n\n\trockchip_u3phy_rest_assert(u3phy);\n\trockchip_u3phy_rest_deassert(u3phy, U3PHY_APB_RST | U3PHY_POR_RST);\n\n\tindex = 0;\n\tfor_each_available_child_of_node(np, child_np) {\n\t\tstruct rockchip_u3phy_port *u3phy_port = &u3phy->ports[index];\n\n\t\tu3phy_port->index = index;\n\t\tret = rockchip_u3phy_port_init(u3phy, u3phy_port, child_np);\n\t\tif (ret) {\n\t\t\tdev_err(dev, \"u3phy port init failed,ret(%d)\\n\", ret);\n\t\t\tgoto put_child;\n\t\t}\n\n\t\t/* to prevent out of boundary */\n\t\tif (++index >= U3PHY_PORT_NUM)\n\t\t\tbreak;\n\t}\n\n\tprovider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);\n\tif (IS_ERR_OR_NULL(provider))\n\t\tgoto put_child;\n\n\trockchip_u3phy_rest_deassert(u3phy, U3PHY_MAC_RST);\n\trockchip_u3phy_clk_disable(u3phy);\n\n\tu3phy->usb_phy.dev = dev;\n\tu3phy->usb_phy.init = rockchip_u3phy_on_init;\n\tu3phy->usb_phy.shutdown = rockchip_u3phy_on_shutdown;\n\tu3phy->usb_phy.notify_disconnect = rockchip_u3phy_on_disconnect;\n\tusb_add_phy(&u3phy->usb_phy, USB_PHY_TYPE_USB3);\n\tATOMIC_INIT_NOTIFIER_HEAD(&u3phy->usb_phy.notifier);\n\n\trockchip_u3phy_debugfs_init(u3phy);\n\n\tdev_info(dev, \"Rockchip u3phy initialized successfully\\n\");\n\treturn 0;\n\nput_child:\n\tof_node_put(child_np);\n\treturn ret;\n}\n\nstatic int rk3328_u3phy_pipe_power(struct rockchip_u3phy *u3phy,\n\t\t\t\t   struct rockchip_u3phy_port *u3phy_port,\n\t\t\t\t   bool on)\n{\n\tunsigned int reg;\n\n\tif (on) {\n\t\treg = readl(u3phy_port->base + 0x1a8);\n\t\treg &= ~BIT(4); /* ldo power up */\n\t\twritel(reg, u3phy_port->base + 0x1a8);\n\n\t\treg = readl(u3phy_port->base + 0x044);\n\t\treg &= ~BIT(4); /* bg power on */\n\t\twritel(reg, u3phy_port->base + 0x044);\n\n\t\treg = readl(u3phy_port->base + 0x150);\n\t\treg |= BIT(6); /* tx bias enable */\n\t\twritel(reg, u3phy_port->base + 0x150);\n\n\t\treg = readl(u3phy_port->base + 0x080);\n\t\treg &= ~BIT(2); /* tx cm power up */\n\t\twritel(reg, u3phy_port->base + 0x080);\n\n\t\treg = readl(u3phy_port->base + 0x0c0);\n\t\t/* tx obs enable and rx cm enable */\n\t\treg |= (BIT(3) | BIT(4));\n\t\twritel(reg, u3phy_port->base + 0x0c0);\n\n\t\tudelay(1);\n\t} else {\n\t\treg = readl(u3phy_port->base + 0x1a8);\n\t\treg |= BIT(4); /* ldo power down */\n\t\twritel(reg, u3phy_port->base + 0x1a8);\n\n\t\treg = readl(u3phy_port->base + 0x044);\n\t\treg |= BIT(4); /* bg power down */\n\t\twritel(reg, u3phy_port->base + 0x044);\n\n\t\treg = readl(u3phy_port->base + 0x150);\n\t\treg &= ~BIT(6); /* tx bias disable */\n\t\twritel(reg, u3phy_port->base + 0x150);\n\n\t\treg = readl(u3phy_port->base + 0x080);\n\t\treg |= BIT(2); /* tx cm power down */\n\t\twritel(reg, u3phy_port->base + 0x080);\n\n\t\treg = readl(u3phy_port->base + 0x0c0);\n\t\t/* tx obs disable and rx cm disable */\n\t\treg &= ~(BIT(3) | BIT(4));\n\t\twritel(reg, u3phy_port->base + 0x0c0);\n\t}\n\n\treturn 0;\n}\n\nstatic int rk3328_u3phy_tuning(struct rockchip_u3phy *u3phy,\n\t\t\t       struct rockchip_u3phy_port *u3phy_port,\n\t\t\t       struct device_node *child_np)\n{\n\tif (u3phy_port->type == U3PHY_TYPE_UTMI) {\n\t\t/*\n\t\t * For rk3328 SoC, pre-emphasis and pre-emphasis strength must\n\t\t * be written as one fixed value as below.\n\t\t *\n\t\t * Dissimilarly, the odt 45ohm value should be flexibly tuninged\n\t\t * for the different boards to adjust HS eye height, so its\n\t\t * value can be assigned in DT in code design.\n\t\t */\n\n\t\t/* {bits[2:0]=111}: always enable pre-emphasis */\n\t\tu3phy->apbcfg.u2_pre_emp = 0x0f;\n\n\t\t/* {bits[5:3]=000}: pre-emphasis strength as the weakest */\n\t\tu3phy->apbcfg.u2_pre_emp_sth = 0x41;\n\n\t\t/* {bits[4:0]=10101}: odt 45ohm tuning */\n\t\tu3phy->apbcfg.u2_odt_tuning = 0xb5;\n\t\t/* optional override of the odt 45ohm tuning */\n\t\tof_property_read_u32(child_np, \"rockchip,odt-val-tuning\",\n\t\t\t\t     &u3phy->apbcfg.u2_odt_tuning);\n\n\t\twritel(u3phy->apbcfg.u2_pre_emp, u3phy_port->base + 0x030);\n\t\twritel(u3phy->apbcfg.u2_pre_emp_sth, u3phy_port->base + 0x040);\n\t\twritel(u3phy->apbcfg.u2_odt_tuning, u3phy_port->base + 0x11c);\n\t} else if (u3phy_port->type == U3PHY_TYPE_PIPE) {\n\t\tif (u3phy_port->refclk_25m_quirk) {\n\t\t\tdev_dbg(u3phy->dev, \"switch to 25m refclk\\n\");\n\t\t\t/* ref clk switch to 25M */\n\t\t\twritel(0x64, u3phy_port->base + 0x11c);\n\t\t\twritel(0x64, u3phy_port->base + 0x028);\n\t\t\twritel(0x01, u3phy_port->base + 0x020);\n\t\t\twritel(0x21, u3phy_port->base + 0x030);\n\t\t\twritel(0x06, u3phy_port->base + 0x108);\n\t\t\twritel(0x00, u3phy_port->base + 0x118);\n\t\t} else {\n\t\t\t/* configure for 24M ref clk */\n\t\t\twritel(0x80, u3phy_port->base + 0x10c);\n\t\t\twritel(0x01, u3phy_port->base + 0x118);\n\t\t\twritel(0x38, u3phy_port->base + 0x11c);\n\t\t\twritel(0x83, u3phy_port->base + 0x020);\n\t\t\twritel(0x02, u3phy_port->base + 0x108);\n\t\t}\n\n\t\t/* Enable SSC */\n\t\tudelay(3);\n\t\twritel(0x08, u3phy_port->base + 0x000);\n\t\twritel(0x0c, u3phy_port->base + 0x120);\n\n\t\t/* Tuning Rx for compliance RJTL test */\n\t\twritel(0x70, u3phy_port->base + 0x150);\n\t\twritel(0x12, u3phy_port->base + 0x0c8);\n\t\twritel(0x05, u3phy_port->base + 0x148);\n\t\twritel(0x08, u3phy_port->base + 0x068);\n\t\twritel(0xf0, u3phy_port->base + 0x1c4);\n\t\twritel(0xff, u3phy_port->base + 0x070);\n\t\twritel(0x0f, u3phy_port->base + 0x06c);\n\t\twritel(0xe0, u3phy_port->base + 0x060);\n\n\t\t/*\n\t\t * Tuning Tx to increase the bias current\n\t\t * used in TX driver and RX EQ, it can\n\t\t * also increase the voltage of LFPS.\n\t\t */\n\t\twritel(0x08, u3phy_port->base + 0x180);\n\t} else {\n\t\tdev_err(u3phy->dev, \"invalid u3phy port type\\n\");\n\t\treturn -EINVAL;\n\t}\n\n\treturn 0;\n}\n\nstatic int rk322xh_u3phy_cp_test_enable(struct rockchip_u3phy *u3phy,\n\t\t\t\t\tstruct rockchip_u3phy_port *u3phy_port)\n{\n\tif (u3phy_port->type == U3PHY_TYPE_PIPE) {\n\t\twritel(0x0c, u3phy_port->base + 0x408);\n\t} else {\n\t\tdev_err(u3phy->dev, \"The u3phy type is not pipe\\n\");\n\t\treturn -EINVAL;\n\t}\n\n\treturn 0;\n}\n\nstatic const struct rockchip_u3phy_cfg rk3328_u3phy_cfgs[] = {\n\t{\n\t\t.reg\t\t= 0xff470000,\n\t\t.grfcfg\t\t= {\n\t\t\t.um_suspend\t= { 0x0004, 15, 0, 0x1452, 0x15d1 },\n\t\t\t.u2_only_ctrl\t= { 0x0020, 15, 15, 0, 1 },\n\t\t\t.um_ls\t\t= { 0x0030, 5, 4, 0, 1 },\n\t\t\t.um_hstdct\t= { 0x0030, 7, 7, 0, 1 },\n\t\t\t.ls_det_en\t= { 0x0040, 0, 0, 0, 1 },\n\t\t\t.ls_det_st\t= { 0x0044, 0, 0, 0, 1 },\n\t\t\t.pp_pwr_st\t= { 0x0034, 14, 13, 0, 0},\n\t\t\t.pp_pwr_en\t= { {0x0020, 14, 0, 0x0014, 0x0005},\n\t\t\t\t\t    {0x0020, 14, 0, 0x0014, 0x000d},\n\t\t\t\t\t    {0x0020, 14, 0, 0x0014, 0x0015},\n\t\t\t\t\t    {0x0020, 14, 0, 0x0014, 0x001d} },\n\t\t\t.u3_disable\t= { 0x04c4, 15, 0, 0x1100, 0x101},\n\t\t},\n\t\t.phy_pipe_power\t= rk3328_u3phy_pipe_power,\n\t\t.phy_tuning\t= rk3328_u3phy_tuning,\n\t\t.phy_cp_test\t= rk322xh_u3phy_cp_test_enable,\n\t},\n\t{ /* sentinel */ }\n};\n\nstatic const struct of_device_id rockchip_u3phy_dt_match[] = {\n\t{ .compatible = \"rockchip,rk3328-u3phy\", .data = &rk3328_u3phy_cfgs },\n\t{}\n};\nMODULE_DEVICE_TABLE(of, rockchip_u3phy_dt_match);\n\nstatic struct platform_driver rockchip_u3phy_driver = {\n\t.probe\t\t= rockchip_u3phy_probe,\n\t.driver\t\t= {\n\t\t.name\t= \"rockchip-u3phy\",\n\t\t.of_match_table = rockchip_u3phy_dt_match,\n\t},\n};\nmodule_platform_driver(rockchip_u3phy_driver);\n\nMODULE_AUTHOR(\"Frank Wang <frank.wang@rock-chips.com>\");\nMODULE_AUTHOR(\"William Wu <william.wu@rock-chips.com>\");\nMODULE_DESCRIPTION(\"Rockchip USB 3.0 PHY driver\");\nMODULE_LICENSE(\"GPL v2\");\n"
  },
  {
    "path": "target/linux/rockchip/files/include/dt-bindings/clock/rockchip-ddr.h",
    "content": "/*\n *\n * Copyright (C) 2017 ROCKCHIP, Inc.\n *\n * This software is licensed under the terms of the GNU General Public\n * License version 2, as published by the Free Software Foundation, and\n * may be copied, distributed, and modified under those terms.\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n * GNU General Public License for more details.\n *\n */\n\n#ifndef _DT_BINDINGS_CLOCK_ROCKCHIP_DDR_H\n#define _DT_BINDINGS_CLOCK_ROCKCHIP_DDR_H\n\n#define DDR2_DEFAULT\t(0)\n\n#define DDR3_800D\t(0)\t/* 5-5-5 */\n#define DDR3_800E\t(1)\t/* 6-6-6 */\n#define DDR3_1066E\t(2)\t/* 6-6-6 */\n#define DDR3_1066F\t(3)\t/* 7-7-7 */\n#define DDR3_1066G\t(4)\t/* 8-8-8 */\n#define DDR3_1333F\t(5)\t/* 7-7-7 */\n#define DDR3_1333G\t(6)\t/* 8-8-8 */\n#define DDR3_1333H\t(7)\t/* 9-9-9 */\n#define DDR3_1333J\t(8)\t/* 10-10-10 */\n#define DDR3_1600G\t(9)\t/* 8-8-8 */\n#define DDR3_1600H\t(10)\t/* 9-9-9 */\n#define DDR3_1600J\t(11)\t/* 10-10-10 */\n#define DDR3_1600K\t(12)\t/* 11-11-11 */\n#define DDR3_1866J\t(13)\t/* 10-10-10 */\n#define DDR3_1866K\t(14)\t/* 11-11-11 */\n#define DDR3_1866L\t(15)\t/* 12-12-12 */\n#define DDR3_1866M\t(16)\t/* 13-13-13 */\n#define DDR3_2133K\t(17)\t/* 11-11-11 */\n#define DDR3_2133L\t(18)\t/* 12-12-12 */\n#define DDR3_2133M\t(19)\t/* 13-13-13 */\n#define DDR3_2133N\t(20)\t/* 14-14-14 */\n#define DDR3_DEFAULT\t(21)\n#define DDR_DDR2\t(22)\n#define DDR_LPDDR\t(23)\n#define DDR_LPDDR2\t(24)\n\n#define DDR4_1600J\t(0)\t/* 10-10-10 */\n#define DDR4_1600K\t(1)\t/* 11-11-11 */\n#define DDR4_1600L\t(2)\t/* 12-12-12 */\n#define DDR4_1866L\t(3)\t/* 12-12-12 */\n#define DDR4_1866M\t(4)\t/* 13-13-13 */\n#define DDR4_1866N\t(5)\t/* 14-14-14 */\n#define DDR4_2133N\t(6)\t/* 14-14-14 */\n#define DDR4_2133P\t(7)\t/* 15-15-15 */\n#define DDR4_2133R\t(8)\t/* 16-16-16 */\n#define DDR4_2400P\t(9)\t/* 15-15-15 */\n#define DDR4_2400R\t(10)\t/* 16-16-16 */\n#define DDR4_2400U\t(11)\t/* 18-18-18 */\n#define DDR4_DEFAULT\t(12)\n\n#define PAUSE_CPU_STACK_SIZE\t16\n\n#endif\n"
  },
  {
    "path": "target/linux/rockchip/files/include/dt-bindings/memory/rk3328-dram.h",
    "content": "/*\n * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd\n *\n * This file is dual-licensed: you can use it either under the terms\n * of the GPL or the X11 license, at your option. Note that this dual\n * licensing only applies to this file, and not this project as a\n * whole.\n *\n *  a) This library is free software; you can redistribute it and/or\n *     modify it under the terms of the GNU General Public License as\n *     published by the Free Software Foundation; either version 2 of the\n *     License, or (at your option) any later version.\n *\n *     This library is distributed in the hope that it will be useful,\n *     but WITHOUT ANY WARRANTY; without even the implied warranty of\n *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n *     GNU General Public License for more details.\n *\n * Or, alternatively,\n *\n *  b) Permission is hereby granted, free of charge, to any person\n *     obtaining a copy of this software and associated documentation\n *     files (the \"Software\"), to deal in the Software without\n *     restriction, including without limitation the rights to use,\n *     copy, modify, merge, publish, distribute, sublicense, and/or\n *     sell copies of the Software, and to permit persons to whom the\n *     Software is furnished to do so, subject to the following\n *     conditions:\n *\n *     The above copyright notice and this permission notice shall be\n *     included in all copies or substantial portions of the Software.\n *\n *     THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n *     OTHER DEALINGS IN THE SOFTWARE.\n */\n#ifndef _DT_BINDINGS_DRAM_ROCKCHIP_RK3328_H\n#define _DT_BINDINGS_DRAM_ROCKCHIP_RK3328_H\n\n#define DDR3_DS_34ohm\t\t\t(34)\n#define DDR3_DS_40ohm\t\t\t(40)\n\n#define DDR3_ODT_DIS\t\t\t(0)\n#define DDR3_ODT_40ohm\t\t\t(40)\n#define DDR3_ODT_60ohm\t\t\t(60)\n#define DDR3_ODT_120ohm\t\t\t(120)\n\n#define LP2_DS_34ohm\t\t\t(34)\n#define LP2_DS_40ohm\t\t\t(40)\n#define LP2_DS_48ohm\t\t\t(48)\n#define LP2_DS_60ohm\t\t\t(60)\n#define LP2_DS_68_6ohm\t\t\t(68)\t/* optional */\n#define LP2_DS_80ohm\t\t\t(80)\n#define LP2_DS_120ohm\t\t\t(120)\t/* optional */\n\n#define LP3_DS_34ohm\t\t\t(34)\n#define LP3_DS_40ohm\t\t\t(40)\n#define LP3_DS_48ohm\t\t\t(48)\n#define LP3_DS_60ohm\t\t\t(60)\n#define LP3_DS_80ohm\t\t\t(80)\n#define LP3_DS_34D_40U\t\t\t(3440)\n#define LP3_DS_40D_48U\t\t\t(4048)\n#define LP3_DS_34D_48U\t\t\t(3448)\n\n#define LP3_ODT_DIS\t\t\t(0)\n#define LP3_ODT_60ohm\t\t\t(60)\n#define LP3_ODT_120ohm\t\t\t(120)\n#define LP3_ODT_240ohm\t\t\t(240)\n\n#define LP4_PDDS_40ohm\t\t\t(40)\n#define LP4_PDDS_48ohm\t\t\t(48)\n#define LP4_PDDS_60ohm\t\t\t(60)\n#define LP4_PDDS_80ohm\t\t\t(80)\n#define LP4_PDDS_120ohm\t\t\t(120)\n#define LP4_PDDS_240ohm\t\t\t(240)\n\n#define LP4_DQ_ODT_40ohm\t\t(40)\n#define LP4_DQ_ODT_48ohm\t\t(48)\n#define LP4_DQ_ODT_60ohm\t\t(60)\n#define LP4_DQ_ODT_80ohm\t\t(80)\n#define LP4_DQ_ODT_120ohm\t\t(120)\n#define LP4_DQ_ODT_240ohm\t\t(240)\n#define LP4_DQ_ODT_DIS\t\t\t(0)\n\n#define LP4_CA_ODT_40ohm\t\t(40)\n#define LP4_CA_ODT_48ohm\t\t(48)\n#define LP4_CA_ODT_60ohm\t\t(60)\n#define LP4_CA_ODT_80ohm\t\t(80)\n#define LP4_CA_ODT_120ohm\t\t(120)\n#define LP4_CA_ODT_240ohm\t\t(240)\n#define LP4_CA_ODT_DIS\t\t\t(0)\n\n#define DDR4_DS_34ohm\t\t\t(34)\n#define DDR4_DS_48ohm\t\t\t(48)\n#define DDR4_RTT_NOM_DIS\t\t(0)\n#define DDR4_RTT_NOM_60ohm\t\t(60)\n#define DDR4_RTT_NOM_120ohm\t\t(120)\n#define DDR4_RTT_NOM_40ohm\t\t(40)\n#define DDR4_RTT_NOM_240ohm\t\t(240)\n#define DDR4_RTT_NOM_48ohm\t\t(48)\n#define DDR4_RTT_NOM_80ohm\t\t(80)\n#define DDR4_RTT_NOM_34ohm\t\t(34)\n\n#define PHY_DDR3_RON_RTT_DISABLE\t(0)\n#define PHY_DDR3_RON_RTT_451ohm\t\t(1)\n#define PHY_DDR3_RON_RTT_225ohm\t\t(2)\n#define PHY_DDR3_RON_RTT_150ohm\t\t(3)\n#define PHY_DDR3_RON_RTT_112ohm\t\t(4)\n#define PHY_DDR3_RON_RTT_90ohm\t\t(5)\n#define PHY_DDR3_RON_RTT_75ohm\t\t(6)\n#define PHY_DDR3_RON_RTT_64ohm\t\t(7)\n#define PHY_DDR3_RON_RTT_56ohm\t\t(16)\n#define PHY_DDR3_RON_RTT_50ohm\t\t(17)\n#define PHY_DDR3_RON_RTT_45ohm\t\t(18)\n#define PHY_DDR3_RON_RTT_41ohm\t\t(19)\n#define PHY_DDR3_RON_RTT_37ohm\t\t(20)\n#define PHY_DDR3_RON_RTT_34ohm\t\t(21)\n#define PHY_DDR3_RON_RTT_33ohm\t\t(22)\n#define PHY_DDR3_RON_RTT_30ohm\t\t(23)\n#define PHY_DDR3_RON_RTT_28ohm\t\t(24)\n#define PHY_DDR3_RON_RTT_26ohm\t\t(25)\n#define PHY_DDR3_RON_RTT_25ohm\t\t(26)\n#define PHY_DDR3_RON_RTT_23ohm\t\t(27)\n#define PHY_DDR3_RON_RTT_22ohm\t\t(28)\n#define PHY_DDR3_RON_RTT_21ohm\t\t(29)\n#define PHY_DDR3_RON_RTT_20ohm\t\t(30)\n#define PHY_DDR3_RON_RTT_19ohm\t\t(31)\n\n#define PHY_DDR4_LPDDR3_RON_RTT_DISABLE (0)\n#define PHY_DDR4_LPDDR3_RON_RTT_480ohm\t(1)\n#define PHY_DDR4_LPDDR3_RON_RTT_240ohm\t(2)\n#define PHY_DDR4_LPDDR3_RON_RTT_160ohm\t(3)\n#define PHY_DDR4_LPDDR3_RON_RTT_120ohm\t(4)\n#define PHY_DDR4_LPDDR3_RON_RTT_96ohm\t(5)\n#define PHY_DDR4_LPDDR3_RON_RTT_80ohm\t(6)\n#define PHY_DDR4_LPDDR3_RON_RTT_68ohm\t(7)\n#define PHY_DDR4_LPDDR3_RON_RTT_60ohm\t(16)\n#define PHY_DDR4_LPDDR3_RON_RTT_53ohm\t(17)\n#define PHY_DDR4_LPDDR3_RON_RTT_48ohm\t(18)\n#define PHY_DDR4_LPDDR3_RON_RTT_43ohm\t(19)\n#define PHY_DDR4_LPDDR3_RON_RTT_40ohm\t(20)\n#define PHY_DDR4_LPDDR3_RON_RTT_37ohm\t(21)\n#define PHY_DDR4_LPDDR3_RON_RTT_34ohm\t(22)\n#define PHY_DDR4_LPDDR3_RON_RTT_32ohm\t(23)\n#define PHY_DDR4_LPDDR3_RON_RTT_30ohm\t(24)\n#define PHY_DDR4_LPDDR3_RON_RTT_28ohm\t(25)\n#define PHY_DDR4_LPDDR3_RON_RTT_26ohm\t(26)\n#define PHY_DDR4_LPDDR3_RON_RTT_25ohm\t(27)\n#define PHY_DDR4_LPDDR3_RON_RTT_24ohm\t(28)\n#define PHY_DDR4_LPDDR3_RON_RTT_22ohm\t(29)\n#define PHY_DDR4_LPDDR3_RON_RTT_21ohm\t(30)\n#define PHY_DDR4_LPDDR3_RON_RTT_20ohm\t(31)\n\n#endif /*_DT_BINDINGS_DRAM_ROCKCHIP_RK3328_H*/\n"
  },
  {
    "path": "target/linux/rockchip/image/Makefile",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n\ninclude $(TOPDIR)/rules.mk\ninclude $(INCLUDE_DIR)/image.mk\n\nDEVICE_VARS += UBOOT_DEVICE_NAME\n\ndefine Build/Compile\n\t$(CP) $(LINUX_DIR)/COPYING $(KDIR)/COPYING.linux\nendef\n\n### Image scripts ###\ndefine Build/boot-common\n\t# This creates a new folder copies the dtb (as rockchip.dtb) \n\t# and the kernel image (as kernel.img)\n\trm -fR $@.boot\n\tmkdir -p $@.boot\n\n\t$(CP) $(DTS_DIR)/$(DEVICE_DTS).dtb $@.boot/rockchip.dtb\n\t$(CP) $(IMAGE_KERNEL) $@.boot/kernel.img\nendef\n\ndefine Build/boot-script\n\t# Make an U-boot image and copy it to the boot partition\n\tmkimage -A arm -O linux -T script -C none -a 0 -e 0 -d $(if $(1),$(1),mmc).bootscript $@.boot/boot.scr\nendef\n\ndefine Build/pine64-img\n\t# Creates the final SD/eMMC images, \n\t# combining boot partition, root partition as well as the u-boot bootloader\n\n\t# Generate a new partition table in $@ with 32 MiB of \n\t# alignment padding for the idbloader and u-boot to fit:\n\t# http://opensource.rock-chips.com/wiki_Boot_option#Boot_flow\n\t#\n\t# U-Boot SPL expects the U-Boot ITB to be located at sector 0x4000 (8 MiB) on the MMC storage\n\tPADDING=1 $(SCRIPT_DIR)/gen_image_generic.sh \\\n\t\t$@ \\\n\t\t$(CONFIG_TARGET_KERNEL_PARTSIZE) $@.boot \\\n\t\t$(CONFIG_TARGET_ROOTFS_PARTSIZE) $(IMAGE_ROOTFS) \\\n\t\t32768\n\n\t# Copy the idbloader and the u-boot image to the image at sector 0x40 and 0x4000\n\tdd if=\"$(STAGING_DIR_IMAGE)\"/$(UBOOT_DEVICE_NAME)-idbloader.img of=\"$@\" seek=64 conv=notrunc\n\tdd if=\"$(STAGING_DIR_IMAGE)\"/$(UBOOT_DEVICE_NAME)-u-boot.itb of=\"$@\" seek=16384 conv=notrunc\nendef\n\ndefine Build/pine64-bin\n       # Typical Rockchip boot flow with Rockchip miniloader\n       # Rockchp idbLoader which is combinded by Rockchip ddr init bin\n       # and miniloader bin from Rockchip rkbin project\n\n       # Generate a new partition table in $@ with 32 MiB of alignment\n       # padding for the idbloader, uboot and trust image to fit:\n       # http://opensource.rock-chips.com/wiki_Boot_option#Boot_flow\n       $(SCRIPT_DIR)/gen_image_generic.sh \\\n               $@ \\\n               $(CONFIG_TARGET_KERNEL_PARTSIZE) $@.boot \\\n               $(CONFIG_TARGET_ROOTFS_PARTSIZE) $(IMAGE_ROOTFS) \\\n               32768\n\n       # Copy the idbloader, uboot and trust image to the image at sector 0x40, 0x4000 and 0x6000\n       dd if=\"$(STAGING_DIR_IMAGE)\"/$(UBOOT_DEVICE_NAME)-idbloader.bin of=\"$@\" seek=64 conv=notrunc\n       dd if=\"$(STAGING_DIR_IMAGE)\"/$(UBOOT_DEVICE_NAME)-uboot.img of=\"$@\" seek=16384 conv=notrunc\n       dd if=\"$(STAGING_DIR_IMAGE)\"/$(UBOOT_DEVICE_NAME)-trust.bin of=\"$@\" seek=24576 conv=notrunc\nendef\n\n### Devices ###\ndefine Device/Default\n  PROFILES := Default\n  KERNEL := kernel-bin\n  IMAGES := sysupgrade.img.gz\n  DEVICE_DTS = rockchip/$$(SOC)-$(lastword $(subst _, ,$(1)))\nendef\n\ninclude $(SUBTARGET).mk\n\n$(eval $(call BuildImage))\n"
  },
  {
    "path": "target/linux/rockchip/image/armv8.mk",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2020 Tobias Maedel\n\ndefine Device/xunlong_orangepi-r1-plus\n  DEVICE_VENDOR := Xunlong\n  DEVICE_MODEL := OrangePi R1 Plus\n  SOC := rk3328\n  UBOOT_DEVICE_NAME := orangepi-r1-plus-rk3328\n  IMAGE/sysupgrade.img.gz := boot-common | boot-script nanopi-r2s | pine64-bin | gzip | append-metadata\n  DEVICE_PACKAGES := kmod-usb-net-rtl8152\nendef\nTARGET_DEVICES += xunlong_orangepi-r1-plus\n\ndefine Device/xunlong_orangepi-r1-plus-lts\n  DEVICE_VENDOR := Xunlong\n  DEVICE_MODEL := OrangePi R1 Plus LTS\n  SOC := rk3328\n  UBOOT_DEVICE_NAME := orangepi-r1-plus-lts-rk3328\n  IMAGE/sysupgrade.img.gz := boot-common | boot-script nanopi-r2s | pine64-bin | gzip | append-metadata\n  DEVICE_PACKAGES := kmod-usb-net-rtl8152\nendef\nTARGET_DEVICES += xunlong_orangepi-r1-plus-lts\n\ndefine Device/friendlyarm_nanopi-r2s\n  DEVICE_VENDOR := FriendlyARM\n  DEVICE_MODEL := NanoPi R2S\n  SOC := rk3328\n  UBOOT_DEVICE_NAME := nanopi-r2s-rk3328\n  IMAGE/sysupgrade.img.gz := boot-common | boot-script nanopi-r2s | pine64-bin | gzip | append-metadata\n  DEVICE_PACKAGES := kmod-usb-net-rtl8152\nendef\nTARGET_DEVICES += friendlyarm_nanopi-r2s\n\ndefine Device/friendlyarm_nanopi-r4s\n  DEVICE_VENDOR := FriendlyARM\n  DEVICE_MODEL := NanoPi R4S\n  DEVICE_VARIANT := 4GB LPDDR4\n  SOC := rk3399\n  UBOOT_DEVICE_NAME := nanopi-r4s-rk3399\n  IMAGE/sysupgrade.img.gz := boot-common | boot-script nanopi-r4s | pine64-img | gzip | append-metadata\n  DEVICE_PACKAGES := kmod-r8169\nendef\nTARGET_DEVICES += friendlyarm_nanopi-r4s\n\ndefine Device/pine64_rockpro64\n  DEVICE_VENDOR := Pine64\n  DEVICE_MODEL := RockPro64\n  SOC := rk3399\n  UBOOT_DEVICE_NAME := rockpro64-rk3399\n  IMAGE/sysupgrade.img.gz := boot-common | boot-script | pine64-img | gzip | append-metadata\nendef\nTARGET_DEVICES += pine64_rockpro64\n\ndefine Device/radxa_rock-pi-4a\n  DEVICE_VENDOR := Radxa\n  DEVICE_MODEL := ROCK Pi 4A\n  SOC := rk3399\n  SUPPORTED_DEVICES := radxa,rockpi4a radxa,rockpi4\n  UBOOT_DEVICE_NAME := rock-pi-4-rk3399\n  IMAGE/sysupgrade.img.gz := boot-common | boot-script | pine64-img | gzip | append-metadata\nendef\nTARGET_DEVICES += radxa_rock-pi-4a\n"
  },
  {
    "path": "target/linux/rockchip/image/mmc.bootscript",
    "content": "part uuid mmc ${devnum}:2 uuid\n\nsetenv bootargs \"console=ttyS2,1500000 console=tty1 earlycon=uart8250,mmio32,0xff1a0000 root=PARTUUID=${uuid} rw rootwait\"\n\nload mmc ${devnum}:1 ${fdt_addr_r} rockchip.dtb\nload mmc ${devnum}:1 ${kernel_addr_r} kernel.img\n\nbooti ${kernel_addr_r} - ${fdt_addr_r}\n"
  },
  {
    "path": "target/linux/rockchip/image/nanopi-r2s.bootscript",
    "content": "part uuid mmc ${devnum}:2 uuid\n\nsetenv bootargs \"console=ttyS2,1500000 earlycon=uart8250,mmio32,0xff130000 root=PARTUUID=${uuid} rw rootwait\"\n\nload mmc ${devnum}:1 ${fdt_addr_r} rockchip.dtb\nload mmc ${devnum}:1 ${kernel_addr_r} kernel.img\n\nbooti ${kernel_addr_r} - ${fdt_addr_r}\n"
  },
  {
    "path": "target/linux/rockchip/image/nanopi-r4s.bootscript",
    "content": "part uuid mmc ${devnum}:2 uuid\n\nsetenv bootargs \"console=ttyS2,1500000 earlycon=uart8250,mmio32,0xff1a0000 root=PARTUUID=${uuid} rw rootwait\"\n\nload mmc ${devnum}:1 ${fdt_addr_r} rockchip.dtb\nload mmc ${devnum}:1 ${kernel_addr_r} kernel.img\n\nbooti ${kernel_addr_r} - ${fdt_addr_r}\n"
  },
  {
    "path": "target/linux/rockchip/patches-5.10/004-v5.13-rockchip-rk3399-Add-support-for-FriendlyARM-NanoPi-R.patch",
    "content": "From db792e9adbf85ffc9d6b0b060ac3c8e3148c8992 Mon Sep 17 00:00:00 2001\nFrom: Tianling Shen <cnsztl@gmail.com>\nDate: Fri, 19 Mar 2021 13:16:27 +0800\nSubject: [PATCH] rockchip: rk3399: Add support for FriendlyARM NanoPi R4S\n\nThis adds support for the NanoPi R4S from FriendlyArm.\n\nRockchip RK3399 SoC\n1GB DDR3 or 4GB LPDDR4 RAM\nGigabit Ethernet (WAN)\nGigabit Ethernet (PCIe) (LAN)\nUSB 3.0 Port x 2\nMicroSD slot\nReset button\nWAN - LAN - SYS LED\n\nCo-developed-by: Jensen Huang <jensenhuang@friendlyarm.com>\nSigned-off-by: Jensen Huang <jensenhuang@friendlyarm.com>\n[minor adjustments]\nCo-developed-by: Marty Jones <mj8263788@gmail.com>\nSigned-off-by: Marty Jones <mj8263788@gmail.com>\n[further adjustments, fixed format issues]\nSigned-off-by: Tianling Shen <cnsztl@gmail.com>\nLink: https://lore.kernel.org/r/20210319051627.814-2-cnsztl@gmail.com\nSigned-off-by: Heiko Stuebner <heiko@sntech.de>\n---\n arch/arm64/boot/dts/rockchip/Makefile         |   1 +\n .../boot/dts/rockchip/rk3399-nanopi-r4s.dts   | 133 +++++++++++++++++++++\n 2 files changed, 134 insertions(+)\n create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts\n\n--- a/arch/arm64/boot/dts/rockchip/Makefile\n+++ b/arch/arm64/boot/dts/rockchip/Makefile\n@@ -30,6 +30,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-le\n dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopc-t4.dtb\n dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-m4.dtb\n dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-neo4.dtb\n+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-r4s.dtb\n dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-orangepi.dtb\n dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-pinebook-pro.dtb\n dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-puma-haikou.dtb\n--- /dev/null\n+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts\n@@ -0,0 +1,133 @@\n+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)\n+/*\n+ * FriendlyElec NanoPC-T4 board device tree source\n+ *\n+ * Copyright (c) 2020 FriendlyElec Computer Tech. Co., Ltd.\n+ * (http://www.friendlyarm.com)\n+ *\n+ * Copyright (c) 2018 Collabora Ltd.\n+ *\n+ * Copyright (c) 2020 Jensen Huang <jensenhuang@friendlyarm.com>\n+ * Copyright (c) 2020 Marty Jones <mj8263788@gmail.com>\n+ * Copyright (c) 2021 Tianling Shen <cnsztl@gmail.com>\n+ */\n+\n+/dts-v1/;\n+#include \"rk3399-nanopi4.dtsi\"\n+\n+/ {\n+\tmodel = \"FriendlyElec NanoPi R4S\";\n+\tcompatible = \"friendlyarm,nanopi-r4s\", \"rockchip,rk3399\";\n+\n+\t/delete-node/ display-subsystem;\n+\n+\tgpio-leds {\n+\t\tpinctrl-0 = <&lan_led_pin>, <&sys_led_pin>, <&wan_led_pin>;\n+\n+\t\t/delete-node/ led-0;\n+\n+\t\tlan_led: led-lan {\n+\t\t\tgpios = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>;\n+\t\t\tlabel = \"green:lan\";\n+\t\t};\n+\n+\t\tsys_led: led-sys {\n+\t\t\tgpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>;\n+\t\t\tlabel = \"red:sys\";\n+\t\t\tdefault-state = \"on\";\n+\t\t};\n+\n+\t\twan_led: led-wan {\n+\t\t\tgpios = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>;\n+\t\t\tlabel = \"green:wan\";\n+\t\t};\n+\t};\n+\n+\tgpio-keys {\n+\t\tpinctrl-0 = <&reset_button_pin>;\n+\n+\t\t/delete-node/ power;\n+\n+\t\treset {\n+\t\t\tdebounce-interval = <50>;\n+\t\t\tgpios = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>;\n+\t\t\tlabel = \"reset\";\n+\t\t\tlinux,code = <KEY_RESTART>;\n+\t\t};\n+\t};\n+\n+\tvdd_5v: vdd-5v {\n+\t\tcompatible = \"regulator-fixed\";\n+\t\tregulator-name = \"vdd_5v\";\n+\t\tregulator-always-on;\n+\t\tregulator-boot-on;\n+\t};\n+};\n+\n+&emmc_phy {\n+\tstatus = \"disabled\";\n+};\n+\n+&i2c4 {\n+\tstatus = \"disabled\";\n+};\n+\n+&pcie0 {\n+\tmax-link-speed = <1>;\n+\tnum-lanes = <1>;\n+\tvpcie3v3-supply = <&vcc3v3_sys>;\n+};\n+\n+&pinctrl {\n+\tgpio-leds {\n+\t\t/delete-node/ status-led-pin;\n+\n+\t\tlan_led_pin: lan-led-pin {\n+\t\t\trockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;\n+\t\t};\n+\n+\t\tsys_led_pin: sys-led-pin {\n+\t\t\trockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;\n+\t\t};\n+\n+\t\twan_led_pin: wan-led-pin {\n+\t\t\trockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;\n+\t\t};\n+\t};\n+\n+\trockchip-key {\n+\t\t/delete-node/ power-key;\n+\n+\t\treset_button_pin: reset-button-pin {\n+\t\t\trockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>;\n+\t\t};\n+\t};\n+};\n+\n+&sdhci {\n+\tstatus = \"disabled\";\n+};\n+\n+&sdio0 {\n+\tstatus = \"disabled\";\n+};\n+\n+&u2phy0_host {\n+\tphy-supply = <&vdd_5v>;\n+};\n+\n+&u2phy1_host {\n+\tstatus = \"disabled\";\n+};\n+\n+&uart0 {\n+\tstatus = \"disabled\";\n+};\n+\n+&usbdrd_dwc3_0 {\n+\tdr_mode = \"host\";\n+};\n+\n+&vcc3v3_sys {\n+\tvin-supply = <&vcc5v0_sys>;\n+};\n"
  },
  {
    "path": "target/linux/rockchip/patches-5.10/005-arm64-dts-rockchip-add-EEPROM-node-for-NanoPi-R4S.patch",
    "content": "From af20b3384e8723077cc6484160b0cf4e9be321de Mon Sep 17 00:00:00 2001\nFrom: Tianling Shen <cnsztl@gmail.com>\nDate: Mon, 7 Jun 2021 15:45:37 +0800\nSubject: [PATCH] arm64: dts: rockchip: add EEPROM node for NanoPi R4S\n\nNanoPi R4S has a EEPROM attached to the 2nd I2C bus (U92), which\nstores the MAC address.\n\nSigned-off-by: Tianling Shen <cnsztl@gmail.com>\n---\n arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts | 9 +++++++++\n 1 file changed, 9 insertions(+)\n\n--- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts\n+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts\n@@ -68,6 +68,15 @@\n \tstatus = \"disabled\";\n };\n \n+&i2c2 {\n+\teeprom@51 {\n+\t\tcompatible = \"microchip,24c02\", \"atmel,24c02\";\n+\t\treg = <0x51>;\n+\t\tpagesize = <16>;\n+\t\tread-only; /* This holds our MAC */\n+\t};\n+};\n+\n &i2c4 {\n \tstatus = \"disabled\";\n };\n"
  },
  {
    "path": "target/linux/rockchip/patches-5.10/100-rockchip-use-system-LED-for-OpenWrt.patch",
    "content": "From 6731d2c9039fbe1ecf21915eab3acee0a999508a Mon Sep 17 00:00:00 2001\nFrom: David Bauer <mail@david-bauer.net>\nDate: Fri, 10 Jul 2020 21:38:20 +0200\nSubject: [PATCH] rockchip: use system LED for OpenWrt\n\nUse the SYS LED on the casing for showing system status.\n\nThis patch is kept separate from the NanoPi R2S support patch, as i plan\non submitting the device support upstream.\n\nSigned-off-by: David Bauer <mail@david-bauer.net>\n---\n arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts | 9 ++++++++-\n 1 file changed, 8 insertions(+), 1 deletion(-)\n\n--- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts\n+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts\n@@ -13,6 +13,13 @@\n \tmodel = \"FriendlyElec NanoPi R2S\";\n \tcompatible = \"friendlyarm,nanopi-r2s\", \"rockchip,rk3328\";\n \n+\taliases {\n+\t\tled-boot = &sys_led;\n+\t\tled-failsafe = &sys_led;\n+\t\tled-running = &sys_led;\n+\t\tled-upgrade = &sys_led;\n+\t};\n+\n \tchosen {\n \t\tstdout-path = \"serial2:1500000n8\";\n \t};\n"
  },
  {
    "path": "target/linux/rockchip/patches-5.10/101-dts-rockchip-add-usb3-controller-node-for-RK3328-SoCs.patch",
    "content": "From: William Wu <william.wu@rock-chips.com>\n\nRK3328 has one USB 3.0 OTG controller which uses DWC_USB3\ncore's general architecture. It can act as static xHCI host\ncontroller, static device controller, USB 3.0/2.0 OTG basing\non ID of USB3.0 PHY.\n\nSigned-off-by: William Wu <william.wu@rock-chips.com>\nSigned-off-by: Leonidas P. Papadakos <papadakospan@gmail.com>\n\n---\n\nNOTE: This binding still has issues. From the original thread:\n\nthe rk3328 usb3-phy has an issue with detecting any plugin events\nafter a previous device got removed - see the inno-usb3-phy driver\nin the vendor kernel.\n\nThe current state is good-enough for enabling the USB3 attached LAN\nport of the NanoPi R2S. However, it might explode depending on your\nuse-case. You've been warned.\n\n---\n arch/arm64/boot/dts/rockchip/rk3328.dtsi | 27 ++++++++++++++++++++++++\n 1 file changed, 27 insertions(+)\n\n--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi\n+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi\n@@ -985,22 +985,30 @@\n \t};\n \n \tusbdrd3: usb@ff600000 {\n-\t\tcompatible = \"rockchip,rk3328-dwc3\", \"snps,dwc3\";\n-\t\treg = <0x0 0xff600000 0x0 0x100000>;\n-\t\tinterrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;\n+\t\tcompatible = \"rockchip,rk3328-dwc3\", \"rockchip,rk3399-dwc3\";\n \t\tclocks = <&cru SCLK_USB3OTG_REF>, <&cru SCLK_USB3OTG_SUSPEND>,\n \t\t\t <&cru ACLK_USB3OTG>;\n \t\tclock-names = \"ref_clk\", \"suspend_clk\",\n \t\t\t      \"bus_clk\";\n-\t\tdr_mode = \"otg\";\n-\t\tphy_type = \"utmi_wide\";\n-\t\tsnps,dis-del-phy-power-chg-quirk;\n-\t\tsnps,dis_enblslpm_quirk;\n-\t\tsnps,dis-tx-ipgap-linecheck-quirk;\n-\t\tsnps,dis-u2-freeclk-exists-quirk;\n-\t\tsnps,dis_u2_susphy_quirk;\n-\t\tsnps,dis_u3_susphy_quirk;\n+\t\t#address-cells = <2>;\n+\t\t#size-cells = <2>;\n+\t\tranges;\n \t\tstatus = \"disabled\";\n+\n+\t\tusbdrd_dwc3: dwc3@ff600000 {\n+\t\t\tcompatible = \"snps,dwc3\";\n+\t\t\treg = <0x0 0xff600000 0x0 0x100000>;\n+\t\t\tinterrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tdr_mode = \"otg\";\n+\t\t\tphy_type = \"utmi_wide\";\n+\t\t\tsnps,dis_enblslpm_quirk;\n+\t\t\tsnps,dis-u2-freeclk-exists-quirk;\n+\t\t\tsnps,dis_u2_susphy_quirk;\n+\t\t\tsnps,dis_u3_susphy_quirk;\n+\t\t\tsnps,dis-del-phy-power-chg-quirk;\n+\t\t\tsnps,dis-tx-ipgap-linecheck-quirk;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n \t};\n \n \tgic: interrupt-controller@ff811000 {\n"
  },
  {
    "path": "target/linux/rockchip/patches-5.10/102-rockchip-enable-LAN-port-on-NanoPi-R2S.patch",
    "content": "From 0fc3b9b7619c4878f73a6a7989863f0d1a3fd392 Mon Sep 17 00:00:00 2001\nFrom: David Bauer <mail@david-bauer.net>\nDate: Fri, 10 Jul 2020 21:12:16 +0200\nSubject: [PATCH] rockchip: enabled LAN port on NanoPi R2S\n\nEnable the USB3 port on the FriendlyARM NanoPi R2S.\nThis is required for the USB3 attached LAN port to work.\n\nSigned-off-by: David Bauer <mail@david-bauer.net>\n---\n .../boot/dts/rockchip/rk3328-nanopi-r2s.dts   | 27 +++++++++++++++++++\n 1 file changed, 27 insertions(+)\n\n--- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts\n+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts\n@@ -44,6 +44,18 @@\n \t\t};\n \t};\n \n+\tvcc_rtl8153: vcc-rtl8153-regulator {\n+\t\tcompatible = \"regulator-fixed\";\n+\t\tgpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>;\n+\t\tpinctrl-names = \"default\";\n+\t\tpinctrl-0 = <&rtl8153_en_drv>;\n+\t\tregulator-always-on;\n+\t\tregulator-name = \"vcc_rtl8153\";\n+\t\tregulator-min-microvolt = <5000000>;\n+\t\tregulator-max-microvolt = <5000000>;\n+\t\tenable-active-high;\n+\t};\n+\n \tleds {\n \t\tcompatible = \"gpio-leds\";\n \t\tpinctrl-0 = <&lan_led_pin>,  <&sys_led_pin>, <&wan_led_pin>;\n@@ -271,6 +283,12 @@\n \t\t\t};\n \t\t};\n \t};\n+\n+\tusb {\n+\t\trtl8153_en_drv: rtl8153-en-drv {\n+\t\t\trockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;\n+\t\t};\n+\t};\n };\n \n &io_domains {\n@@ -377,3 +395,12 @@\n &usb_host0_ohci {\n \tstatus = \"okay\";\n };\n+\n+&usbdrd3 {\n+\tstatus = \"okay\";\n+};\n+\n+&usbdrd_dwc3 {\n+\tdr_mode = \"host\";\n+\tstatus = \"okay\";\n+};\n"
  },
  {
    "path": "target/linux/rockchip/patches-5.10/103-arm64-rockchip-add-OF-node-for-USB-eth-on-NanoPi-R2S.patch",
    "content": "From 2795c8b31a686bdb8338f9404d18ef7a154f0d75 Mon Sep 17 00:00:00 2001\nFrom: David Bauer <mail@david-bauer.net>\nDate: Sun, 26 Jul 2020 13:32:59 +0200\nSubject: [PATCH] arm64: rockchip: add OF node for USB eth on NanoPi R2S\n\nThis adds the OF node for the USB3 ethernet adapter on the FriendlyARM\nNanoPi R2S. Add the correct value for the RTL8153 LED configuration\nregister to match the blink behavior of the other port on the device.\n\nSigned-off-by: David Bauer <mail@david-bauer.net>\n---\n arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts | 7 +++++++\n 1 file changed, 7 insertions(+)\n\n--- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts\n+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts\n@@ -403,4 +403,11 @@\n &usbdrd_dwc3 {\n \tdr_mode = \"host\";\n \tstatus = \"okay\";\n+\n+\tusb-eth@2 {\n+\t\tcompatible = \"realtek,rtl8153\";\n+\t\treg = <2>;\n+\n+\t\trealtek,led-data = <0x87>;\n+\t};\n };\n"
  },
  {
    "path": "target/linux/rockchip/patches-5.10/104-rockchip-use-USB-host-by-default-on-rk3399-rock-pi-4.patch",
    "content": "From e12f67fe83446432ef16704c22ec23bd1dbcd094 Mon Sep 17 00:00:00 2001\nFrom: Vicente Bergas <vicencb@gmail.com>\nDate: Tue, 1 Dec 2020 16:41:32 +0100\nSubject: arm64: dts: rockchip: use USB host by default on rk3399-rock-pi-4\n\nBased on the board schematics at\nhttps://dl.radxa.com/rockpi4/docs/hw/rockpi4/rockpi_4c_v12_sch_20200620.pdf\non page 19 there is an USB Type-A receptacle being used as an USB-OTG port.\n\nBut the Type-A connector is not valid for OTG operation, for this reason\nthere is a switch to select host or device role.\nThis is non-compliant and error prone because switching is manual.\nSo, use host mode as it corresponds for a Type-A receptacle.\n\nSigned-off-by: Vicente Bergas <vicencb@gmail.com>\nLink: https://lore.kernel.org/r/20201201154132.1286-4-vicencb@gmail.com\nSigned-off-by: Heiko Stuebner <heiko@sntech.de>\n---\n arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dts | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi\n+++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi\n@@ -680,7 +680,7 @@\n \n &usbdrd_dwc3_0 {\n \tstatus = \"okay\";\n-\tdr_mode = \"otg\";\n+\tdr_mode = \"host\";\n };\n \n &usbdrd3_1 {\n"
  },
  {
    "path": "target/linux/rockchip/patches-5.10/105-nanopi-r4s-sd-signalling.patch",
    "content": "From: David Bauer <mail@david-bauer.net>\nSubject: arm64: dts: rockchip: disable UHS modes for NanoPi R4S\n\nThe NanoPi R4S leaves the SD card in 1.8V signalling when rebooting\nwhile U-Boot requires the card to be in 3.3V mode.\n\nRemove UHS support from the SD controller so the card remains in 3.3V\nmode. This reduces transfer speeds but ensures a reboot whether from\nuserspace or following a kernel panic is always working.\n\nSigned-off-by: David Bauer <mail@david-bauer.net>\n\n--- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts\n+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts\n@@ -121,6 +121,11 @@\n \tstatus = \"disabled\";\n };\n \n+&sdmmc {\n+\t/delete-property/ sd-uhs-sdr104;\n+\tcap-sd-highspeed;\n+};\n+\n &u2phy0_host {\n \tphy-supply = <&vdd_5v>;\n };\n"
  },
  {
    "path": "target/linux/rockchip/patches-5.10/202-rockchip-rk3328-Add-support-for-OrangePi-R1-Plus.patch",
    "content": "--- a/arch/arm64/boot/dts/rockchip/Makefile\n+++ b/arch/arm64/boot/dts/rockchip/Makefile\n@@ -7,6 +7,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-od\n dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-a1.dtb\n dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb\n dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb\n+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus.dtb\n dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb\n dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-cc.dtb\n dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-evb-act8846.dtb\n--- /dev/null\n+++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts\n@@ -0,0 +1,46 @@\n+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)\n+#include \"rk3328-nanopi-r2s.dts\"\n+\n+/ {\n+\tmodel = \"Xunlong Orange Pi R1 Plus\";\n+\tcompatible = \"xunlong,orangepi-r1-plus\", \"rockchip,rk3328\";\n+};\n+\n+&lan_led {\n+\tlabel = \"orangepi-r1-plus:green:lan\";\n+};\n+\n+&spi0 {\n+\tmax-freq = <48000000>;\n+\tstatus = \"okay\";\n+\n+\tflash@0 {\n+\t\tcompatible = \"jedec,spi-nor\";\n+\t\treg = <0>;\n+\t\tspi-max-frequency = <10000000>;\n+\t};\n+};\n+\n+&sys_led {\n+\tgpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;\n+\tlabel = \"orangepi-r1-plus:red:sys\";\n+};\n+\n+&sys_led_pin {\n+\trockchip,pins = <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;\n+};\n+\n+&uart1 {\n+\tstatus = \"okay\";\n+};\n+\n+&wan_led {\n+\tlabel = \"orangepi-r1-plus:green:wan\";\n+};\n+\n+&sdmmc {\n+\t/delete-property/ sd-uhs-sdr12;\n+\t/delete-property/ sd-uhs-sdr25;\n+\t/delete-property/ sd-uhs-sdr50;\n+\t/delete-property/ sd-uhs-sdr104;\n+};\n"
  },
  {
    "path": "target/linux/rockchip/patches-5.10/206-Add-support-for-OrangePi-R1-Plus-LTS.patch",
    "content": "From 9f0bfe430a5a67b34bc2274a898b4375a321810b Mon Sep 17 00:00:00 2001\nFrom: baiywt <baiywt_gj@163.com>\nDate: Mon, 15 Nov 2021 16:51:43 +0800\nSubject: [PATCH] Add support for OrangePi R1 Plus LTS\n\n---\n arch/arm64/boot/dts/rockchip/Makefile         |  1 +\n .../rockchip/rk3328-orangepi-r1-plus-lts.dts  | 44 +++++++++++++++++++\n 2 files changed, 45 insertions(+)\n create mode 100644 arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts\n\ndiff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile\nindex 23373c752..552d97555 100644\n--- a/arch/arm64/boot/dts/rockchip/Makefile\n+++ b/arch/arm64/boot/dts/rockchip/Makefile\n@@ -3,6 +3,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-evb.dtb\n dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb\n dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb\n dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus.dtb\n+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus-lts.dtb\n dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb\n dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-cc.dtb\n dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-evb-act8846.dtb\ndiff --git a/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts\nnew file mode 100644\nindex 000000000..c65f7c417\n--- /dev/null\n+++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts\n@@ -0,0 +1,70 @@\n+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)\n+#include \"rk3328-orangepi-r1-plus.dts\"\n+\n+/ {\n+\tmodel = \"Xunlong Orange Pi R1 Plus LTS\";\n+\tcompatible = \"xunlong,orangepi-r1-plus-lts\", \"rockchip,rk3328\";\n+};\n+\n+/delete-node/ &rtl8211e;\n+&gmac2io {\n+        phy-handle = <&ethphy3>;\n+        snps,reset-delays-us = <0 15000 50000>;\n+        tx_delay = <0x19>;\n+        rx_delay = <0x05>;\n+        status = \"okay\";\n+\n+        mdio {\n+                compatible = \"snps,dwmac-mdio\";\n+                #address-cells = <1>;\n+                #size-cells = <0>;\n+\n+                ethphy3: ethernet-phy@0 {\n+                        reg = <0x0>;\n+                        keep-clkout-on;\n+                       reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;\n+                };\n+        };\n+};\n+\n+&sdmmc {\n+      bus-width = <4>;\n+      cap-sd-highspeed;\n+      disable-wp;\n+      pinctrl-0 = <&sdmmc0_clk>, <&sdmmc0_cmd>, <&sdmmc0_dectn>, <&sdmmc0_bus4>;\n+      pinctrl-names = \"default\";\n+      sd-uhs-sdr12;\n+      sd-uhs-sdr25;\n+      sd-uhs-sdr50;\n+      sd-uhs-sdr104;\n+      vmmc-supply = <&vcc_sd>;\n+      vqmmc-supply = <&vcc_io_sdio>;\n+      status = \"okay\";\n+};\n+\n+&dmc_opp_table {\n+        opp-1056000000 {\n+                status = \"disabled\";\n+        };\n+        opp-924000000 {\n+                status = \"disabled\";\n+        };\n+        opp-840000000 {\n+                status = \"disabled\";\n+        };\n+        opp-798000000 {\n+                status = \"disabled\";\n+        };\n+};\n+\n+&sys_led {\n+       label = \"orangepi-r1-plus-lts:red:sys\";\n+};\n+\n+&wan_led {\n+       label = \"orangepi-r1-plus-lts:green:wan\";\n+};\n+\n+&lan_led {\n+       label = \"orangepi-r1-plus-lts:green:lan\";\n+};\n-- \n2.25.1\n\n"
  },
  {
    "path": "target/linux/rockchip/patches-5.10/600-Add-yt8531c-support.patch",
    "content": "From 3b60e97e8cf8a1ae78ec68a2fed37cd763675e56 Mon Sep 17 00:00:00 2001\nFrom: baiywt <baiywt_gj@163.com>\nDate: Fri, 18 Feb 2022 16:38:43 +0800\nSubject: [PATCH] Add yt8531c support\n\n---\n drivers/net/phy/Kconfig       |    5 +\n drivers/net/phy/Makefile      |    1 +\n drivers/net/phy/motorcomm.c   | 1540 +++++++++++++++++++++++++++++++++\n drivers/net/phy/yt8614-phy.h  |  491 +++++++++++\n include/linux/motorcomm_phy.h |  119 +++\n 5 files changed, 2156 insertions(+)\n create mode 100644 drivers/net/phy/motorcomm.c\n create mode 100644 drivers/net/phy/yt8614-phy.h\n create mode 100644 include/linux/motorcomm_phy.h\n\ndiff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig\nindex ce030fcb1..ff4861847 100644\n--- a/drivers/net/phy/Kconfig\n+++ b/drivers/net/phy/Kconfig\n@@ -297,6 +297,11 @@ config MICROSEMI_PHY\n \thelp\n \t  Currently supports VSC8514, VSC8530, VSC8531, VSC8540 and VSC8541 PHYs\n \n+config MOTORCOMM_PHY\n+        tristate \"Motorcomm PHYs\"\n+        help\n+          Supports the YT8010, YT8510, YT8511, YT8512 PHYs.\n+\n config NATIONAL_PHY\n \ttristate \"National Semiconductor PHYs\"\n \thelp\ndiff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile\nindex 7c227bd26..83b447f11 100644\n--- a/drivers/net/phy/Makefile\n+++ b/drivers/net/phy/Makefile\n@@ -82,6 +82,7 @@ obj-$(CONFIG_MICREL_PHY)\t+= micrel.o\n obj-$(CONFIG_MICROCHIP_PHY)\t+= microchip.o\n obj-$(CONFIG_MICROCHIP_T1_PHY)\t+= microchip_t1.o\n obj-$(CONFIG_MICROSEMI_PHY)\t+= mscc/\n+obj-$(CONFIG_MOTORCOMM_PHY)     += motorcomm.o\n obj-$(CONFIG_NATIONAL_PHY)\t+= national.o\n obj-$(CONFIG_NXP_TJA11XX_PHY)\t+= nxp-tja11xx.o\n obj-$(CONFIG_QSEMI_PHY)\t\t+= qsemi.o\ndiff --git a/drivers/net/phy/motorcomm.c b/drivers/net/phy/motorcomm.c\nnew file mode 100644\nindex 000000000..74eef3dfa\n--- /dev/null\n+++ b/drivers/net/phy/motorcomm.c\n@@ -0,0 +1,1540 @@\n+/*\n+ * drivers/net/phy/motorcomm.c\n+ *\n+ * Driver for Motorcomm PHYs\n+ *\n+ * Author: Leilei Zhao <leilei.zhao@motorcomm.com>\n+ *\n+ * Copyright (c) 2019 Motorcomm, Inc.\n+ *\n+ * This program is free software; you can redistribute  it and/or modify it\n+ * under  the terms of  the GNU General  Public License as published by the\n+ * Free Software Foundation;  either version 2 of the  License, or (at your\n+ * option) any later version.\n+ *\n+ * Support : Motorcomm Phys:\n+ *\t\tGiga phys: yt8511, yt8521\n+ *\t\t100/10 Phys : yt8512, yt8512b, yt8510\n+ *\t\tAutomotive 100Mb Phys : yt8010\n+ *\t\tAutomotive 100/10 hyper range Phys: yt8510\n+ */\n+\n+#include <linux/kernel.h>\n+#include <linux/module.h>\n+#include <linux/phy.h>\n+#include <linux/motorcomm_phy.h>\n+#include <linux/of.h>\n+#include <linux/clk.h>\n+#include <linux/delay.h>\n+#ifndef LINUX_VERSION_CODE\n+#include <linux/version.h>\n+#else\n+#define KERNEL_VERSION(a,b,c) (((a) << 16) + ((b) << 8) + (c))\n+#endif\n+/*for wol, 20210604*/\n+#include <linux/netdevice.h>\n+\n+#include \"yt8614-phy.h\"\n+\n+/**** configuration section begin ***********/\n+\n+/* if system depends on ethernet packet to restore from sleep, please define this macro to 1\n+ * otherwise, define it to 0.\n+ */\n+#define SYS_WAKEUP_BASED_ON_ETH_PKT \t1\n+\n+/* to enable system WOL of phy, please define this macro to 1\n+ * otherwise, define it to 0.\n+ */\n+#define YTPHY_ENABLE_WOL \t\t0\n+\n+/* some GMAC need clock input from PHY, for eg., 125M, please enable this macro\n+ * by degault, it is set to 0\n+ * NOTE: this macro will need macro SYS_WAKEUP_BASED_ON_ETH_PKT to set to 1\n+ */\n+#define GMAC_CLOCK_INPUT_NEEDED 1\n+\n+\n+#define YT8521_PHY_MODE_FIBER\t1 //fiber mode only\n+#define YT8521_PHY_MODE_UTP\t\t2 //utp mode only\n+#define YT8521_PHY_MODE_POLL\t3 //fiber and utp, poll mode\n+\n+/* please make choice according to system design\n+ * for Fiber only system, please define YT8521_PHY_MODE_CURR 1\n+ * for UTP only system, please define YT8521_PHY_MODE_CURR 2\n+ * for combo system, please define YT8521_PHY_MODE_CURR 3 \n+ */\n+#define YT8521_PHY_MODE_CURR\t3\n+\n+/**** configuration section end ***********/\n+\n+\n+/* no need to change below */\n+\n+#if (YTPHY_ENABLE_WOL)\n+#undef SYS_WAKEUP_BASED_ON_ETH_PKT\n+#define SYS_WAKEUP_BASED_ON_ETH_PKT \t1\n+#endif\n+\n+/* workaround for 8521 fiber 100m mode */\n+static int link_mode_8521 = 0; //0: no link; 1: utp; 32: fiber. traced that 1000m fiber uses 32.\n+static int link_mode_8614[4] = {0}; //0: no link; 1: utp; 32: fiber. traced that 1000m fiber uses 32.\n+\n+/* for multiple port phy, base phy address */\n+static unsigned int yt_mport_base_phy_addr = 0xff; //0xff: invalid; for 8618\n+static unsigned int yt_mport_base_phy_addr_8614 = 0xff; //0xff: invalid;\n+\n+int phy_yt8531_led_fixup(struct mii_bus *bus, int addr);\n+int yt8511_config_out_125m(struct mii_bus *bus, int phy_id);\n+\n+#if ( LINUX_VERSION_CODE > KERNEL_VERSION(5,0,0) )\n+int genphy_config_init(struct phy_device *phydev)\n+{\n+\tint ret;\n+\n+\tprintk (KERN_INFO \"yzhang..read phyaddr=%d, phyid=%08x\\n\",phydev->mdio.addr, phydev->phy_id);\n+\n+\tif(phydev->phy_id == 0x4f51e91b)\n+\t{\n+\t\tprintk (KERN_INFO \"yzhang..get YT8511, abt to set 125m clk out, phyaddr=%d, phyid=%08x\\n\",phydev->mdio.addr, phydev->phy_id);\n+\t\tret = yt8511_config_out_125m(phydev->mdio.bus, phydev->mdio.addr);\n+\t\tprintk (KERN_INFO \"yzhang..8511 set 125m clk out, reg=%#04x\\n\",phydev->mdio.bus->read(phydev->mdio.bus,phydev->mdio.addr,0x1f)/*double check as delay*/);\n+\t\tif (ret<0)\n+\t\t\tprintk (KERN_INFO \"yzhang..failed to set 125m clk out, ret=%d\\n\",ret);\n+\n+\t\tphy_yt8531_led_fixup(phydev->mdio.bus, phydev->mdio.addr);\n+\t}\n+\treturn  genphy_read_abilities(phydev);\n+}\n+#endif\n+\n+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) )\n+static int ytphy_config_init(struct phy_device *phydev)\n+{\n+\treturn 0;\n+}\n+#endif\n+\n+static int ytphy_read_ext(struct phy_device *phydev, u32 regnum)\n+{\n+\tint ret;\n+\tint val;\n+\n+\tret = phy_write(phydev, REG_DEBUG_ADDR_OFFSET, regnum);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\tval = phy_read(phydev, REG_DEBUG_DATA);\n+\n+\treturn val;\n+}\n+\n+static int ytphy_write_ext(struct phy_device *phydev, u32 regnum, u16 val)\n+{\n+\tint ret;\n+\n+\tret = phy_write(phydev, REG_DEBUG_ADDR_OFFSET, regnum);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\tret = phy_write(phydev, REG_DEBUG_DATA, val);\n+\n+\treturn ret;\n+}\n+\n+static int yt8010_config_aneg(struct phy_device *phydev)\n+{\n+\tphydev->speed = SPEED_100;\n+\treturn 0;\n+}\n+\n+static int yt8512_clk_init(struct phy_device *phydev)\n+{\n+\tint ret;\n+\tint val;\n+\n+\tval = ytphy_read_ext(phydev, YT8512_EXTREG_AFE_PLL);\n+\tif (val < 0)\n+\t\treturn val;\n+\n+\tval |= YT8512_CONFIG_PLL_REFCLK_SEL_EN;\n+\n+\tret = ytphy_write_ext(phydev, YT8512_EXTREG_AFE_PLL, val);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\tval = ytphy_read_ext(phydev, YT8512_EXTREG_EXTEND_COMBO);\n+\tif (val < 0)\n+\t\treturn val;\n+\n+\tval |= YT8512_CONTROL1_RMII_EN;\n+\n+\tret = ytphy_write_ext(phydev, YT8512_EXTREG_EXTEND_COMBO, val);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\tval = phy_read(phydev, MII_BMCR);\n+\tif (val < 0)\n+\t\treturn val;\n+\n+\tval |= YT_SOFTWARE_RESET;\n+\tret = phy_write(phydev, MII_BMCR, val);\n+\n+\treturn ret;\n+}\n+\n+static int yt8512_led_init(struct phy_device *phydev)\n+{\n+\tint ret;\n+\tint val;\n+\tint mask;\n+\n+\tval = ytphy_read_ext(phydev, YT8512_EXTREG_LED0);\n+\tif (val < 0)\n+\t\treturn val;\n+\n+\tval |= YT8512_LED0_ACT_BLK_IND;\n+\n+\tmask = YT8512_LED0_DIS_LED_AN_TRY | YT8512_LED0_BT_BLK_EN |\n+\t\tYT8512_LED0_HT_BLK_EN | YT8512_LED0_COL_BLK_EN |\n+\t\tYT8512_LED0_BT_ON_EN;\n+\tval &= ~mask;\n+\n+\tret = ytphy_write_ext(phydev, YT8512_EXTREG_LED0, val);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\tval = ytphy_read_ext(phydev, YT8512_EXTREG_LED1);\n+\tif (val < 0)\n+\t\treturn val;\n+\n+\tval |= YT8512_LED1_BT_ON_EN;\n+\n+\tmask = YT8512_LED1_TXACT_BLK_EN | YT8512_LED1_RXACT_BLK_EN;\n+\tval &= ~mask;\n+\n+\tret = ytphy_write_ext(phydev, YT8512_LED1_BT_ON_EN, val);\n+\n+\treturn ret;\n+}\n+\n+static int yt8512_config_init(struct phy_device *phydev)\n+{\n+\tint ret;\n+\tint val;\n+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) )\n+\tret = ytphy_config_init(phydev);\n+#else\n+\tret = genphy_config_init(phydev);\n+#endif\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\tret = yt8512_clk_init(phydev);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\tret = yt8512_led_init(phydev);\n+\n+\t/* disable auto sleep */\n+\tval = ytphy_read_ext(phydev, YT8512_EXTREG_SLEEP_CONTROL1);\n+\tif (val < 0)\n+\t\treturn val;\n+\n+\tval &= (~BIT(YT8512_EN_SLEEP_SW_BIT));\n+\n+\tret = ytphy_write_ext(phydev, YT8512_EXTREG_SLEEP_CONTROL1, val);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\treturn ret;\n+}\n+\n+static int yt8512_read_status(struct phy_device *phydev)\n+{\n+\tint ret;\n+\tint val;\n+\tint speed, speed_mode, duplex;\n+\n+\tret = genphy_update_link(phydev);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tval = phy_read(phydev, REG_PHY_SPEC_STATUS);\n+\tif (val < 0)\n+\t\treturn val;\n+\n+\tduplex = (val & YT8512_DUPLEX) >> YT8512_DUPLEX_BIT;\n+\tspeed_mode = (val & YT8512_SPEED_MODE) >> YT8512_SPEED_MODE_BIT;\n+\tswitch (speed_mode) {\n+\tcase 0:\n+\t\tspeed = SPEED_10;\n+\t\tbreak;\n+\tcase 1:\n+\t\tspeed = SPEED_100;\n+\t\tbreak;\n+\tcase 2:\n+\tcase 3:\n+\tdefault:\n+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) )\n+\t\tspeed = -1;\n+#else\n+\t\tspeed = SPEED_UNKNOWN;\n+#endif\n+\t\tbreak;\n+\t}\n+\n+\tphydev->speed = speed;\n+\tphydev->duplex = duplex;\n+\n+\treturn 0;\n+}\n+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) )\n+#else\n+#if 0\n+int yt8521_soft_reset(struct phy_device *phydev)\n+{\n+\tint ret;\n+\n+\tytphy_write_ext(phydev, 0xa000, 0);\n+\tret = genphy_soft_reset(phydev);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\tytphy_write_ext(phydev, 0xa000, 2);\n+\tret = genphy_soft_reset(phydev);\n+\tif (ret < 0) {\n+\t\tytphy_write_ext(phydev, 0xa000, 0);\n+\t\treturn ret;\n+\t}\n+\n+\treturn 0;\n+}\n+#else\n+/* qingsong feedback 2 genphy_soft_reset will cause problem.\n+ * and this is the reduction version\n+ */\n+int yt8521_soft_reset(struct phy_device *phydev)\n+{\n+\tint ret, val;\n+\n+\tval = ytphy_read_ext(phydev, 0xa001);\n+\tytphy_write_ext(phydev, 0xa001, (val & ~0x8000));\n+\n+\tret = genphy_soft_reset(phydev);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\treturn 0;\n+}\n+#endif\n+\n+#endif\n+\n+#if GMAC_CLOCK_INPUT_NEEDED\n+static int ytphy_mii_rd_ext(struct mii_bus *bus, int phy_id, u32 regnum)\n+{\n+\tint ret;\n+\tint val;\n+\n+\tret = bus->write(bus, phy_id, REG_DEBUG_ADDR_OFFSET, regnum);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\tval = bus->read(bus, phy_id, REG_DEBUG_DATA);\n+\n+\treturn val;\n+}\n+\n+static int ytphy_mii_wr_ext(struct mii_bus *bus, int phy_id, u32 regnum, u16 val)\n+{\n+\tint ret;\n+\n+\tret = bus->write(bus, phy_id, REG_DEBUG_ADDR_OFFSET, regnum);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\tret = bus->write(bus, phy_id, REG_DEBUG_DATA, val);\n+\n+\treturn ret;\n+}\n+\n+int yt8511_config_dis_txdelay(struct mii_bus *bus, int phy_id)\n+{\n+    int ret;\n+    int val;\n+\n+    /* disable auto sleep */\n+    val = ytphy_mii_rd_ext(bus, phy_id, 0x27);\n+    if (val < 0)\n+            return val;\n+\n+    val &= (~BIT(15));\n+\n+    ret = ytphy_mii_wr_ext(bus, phy_id, 0x27, val);\n+    if (ret < 0)\n+            return ret;\n+\n+    /* enable RXC clock when no wire plug */\n+    val = ytphy_mii_rd_ext(bus, phy_id, 0xc);\n+    if (val < 0)\n+            return val;\n+\n+    /* ext reg 0xc b[7:4]\n+\tTx Delay time = 150ps * N - 250ps\n+    */\n+    val &= ~(0xf << 4);\n+    ret = ytphy_mii_wr_ext(bus, phy_id, 0xc, val);\n+    printk(\"yt8511_config_dis_txdelay..phy txdelay, val=%#08x\\n\",val);\n+\n+    return ret;\n+}\n+\n+int phy_yt8531_led_fixup(struct mii_bus *bus, int addr)\n+{\n+\tprintk(\"%s in\\n\", __func__);\n+\n+\tytphy_mii_wr_ext(bus, addr, 0xa00d, 0x670);\n+\tytphy_mii_wr_ext(bus, addr, 0xa00e, 0x2070);\n+\tytphy_mii_wr_ext(bus, addr, 0xa00f, 0x7e);\n+\n+\treturn 0;\n+}\n+\n+int yt8511_config_out_125m(struct mii_bus *bus, int addr)\n+{\n+\tint ret;\n+\tint val;\n+\n+\tmdelay(50);\n+\tret = ytphy_mii_wr_ext(bus, addr, 0xa012, 0xd0);\n+\n+\tmdelay(100);\n+\tval = ytphy_mii_rd_ext(bus, addr, 0xa012);\n+\t\n+\tif(val != 0xd0)\n+\t{\n+\t\tprintk(\"yt8511_config_out_125m error\\n\");\n+\t\treturn -1;\n+\t}\n+\n+\t/* disable auto sleep */\n+\tval = ytphy_mii_rd_ext(bus, addr, 0x27);\n+\tif (val < 0)\n+\t        return val;\n+\n+\tval &= (~BIT(15));\n+\n+\tret = ytphy_mii_wr_ext(bus, addr, 0x27, val);\n+\tif (ret < 0)\n+\t        return ret;\n+\n+\t/* enable RXC clock when no wire plug */\n+\tval = ytphy_mii_rd_ext(bus, addr, 0xc);\n+\tif (val < 0)\n+\t        return val;\n+\n+\t/* ext reg 0xc.b[2:1]\n+\t00-----25M from pll;\n+\t01---- 25M from xtl;(default)\n+\t10-----62.5M from pll;\n+\t11----125M from pll(here set to this value)\n+\t*/\n+\tval |= (3 << 1);\n+\tret = ytphy_mii_wr_ext(bus, addr, 0xc, val);\n+\tprintk(\"yt8511_config_out_125m, phy clk out, val=%#08x\\n\",val);\n+\n+#if 0\n+\t/* for customer, please enable it based on demand.\n+\t * configure to master\n+\t */\t\n+\tval = bus->read(bus, phy_id, 0x9/*master/slave config reg*/);\n+\tval |= (0x3<<11); //to be manual config and force to be master\n+\tret = bus->write(bus, phy_id, 0x9, val); //take effect until phy soft reset\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\tprintk(\"yt8511_config_out_125m, phy to be master, val=%#08x\\n\",val);\n+#endif\n+\n+    return ret;\n+}\n+\n+EXPORT_SYMBOL(yt8511_config_out_125m);\n+\n+static int yt8511_config_init(struct phy_device *phydev)\n+{\n+\tint ret;\n+\n+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) )\n+\tret = ytphy_config_init(phydev);\n+#else\n+\tret = genphy_config_init(phydev);\n+#endif\n+\n+\treturn ret;\n+}\n+#endif /*GMAC_CLOCK_INPUT_NEEDED*/\n+\n+#if (YTPHY_ENABLE_WOL)\n+static int ytphy_switch_reg_space(struct phy_device *phydev, int space)\n+{\n+\tint ret;\n+\n+\tif (space == YTPHY_REG_SPACE_UTP){\n+\t\tret = ytphy_write_ext(phydev, 0xa000, 0);\n+\t}else{\n+\t\tret = ytphy_write_ext(phydev, 0xa000, 2);\n+\t}\n+\t\n+\treturn ret;\n+}\n+\n+static int ytphy_wol_en_cfg(struct phy_device *phydev, ytphy_wol_cfg_t wol_cfg)\n+{\n+\tint ret=0;\n+\tint val=0;\n+\n+\tval = ytphy_read_ext(phydev, YTPHY_WOL_CFG_REG);\n+\tif (val < 0)\n+\t\treturn val;\n+\n+\tif(wol_cfg.enable) {\n+\t\tval |= YTPHY_WOL_CFG_EN;\n+\n+\t\tif(wol_cfg.type == YTPHY_WOL_TYPE_LEVEL) {\n+\t\t\tval &= ~YTPHY_WOL_CFG_TYPE;\n+\t\t\tval &= ~YTPHY_WOL_CFG_INTR_SEL;\n+\t\t} else if(wol_cfg.type == YTPHY_WOL_TYPE_PULSE) {\n+\t\t\tval |= YTPHY_WOL_CFG_TYPE;\n+\t\t\tval |= YTPHY_WOL_CFG_INTR_SEL;\n+\n+\t\t\tif(wol_cfg.width == YTPHY_WOL_WIDTH_84MS) {\n+\t\t\t\tval &= ~YTPHY_WOL_CFG_WIDTH1;\n+\t\t\t\tval &= ~YTPHY_WOL_CFG_WIDTH2;\n+\t\t\t} else if(wol_cfg.width == YTPHY_WOL_WIDTH_168MS) {\n+\t\t\t\tval |= YTPHY_WOL_CFG_WIDTH1;\n+\t\t\t\tval &= ~YTPHY_WOL_CFG_WIDTH2;\n+\t\t\t} else if(wol_cfg.width == YTPHY_WOL_WIDTH_336MS) {\n+\t\t\t\tval &= ~YTPHY_WOL_CFG_WIDTH1;\n+\t\t\t\tval |= YTPHY_WOL_CFG_WIDTH2;\n+\t\t\t} else if(wol_cfg.width == YTPHY_WOL_WIDTH_672MS) {\n+\t\t\t\tval |= YTPHY_WOL_CFG_WIDTH1;\n+\t\t\t\tval |= YTPHY_WOL_CFG_WIDTH2;\n+\t\t\t}\n+\t\t}\n+\t} else {\n+\t\tval &= ~YTPHY_WOL_CFG_EN;\n+\t\tval &= ~YTPHY_WOL_CFG_INTR_SEL;\n+\t}\n+\n+\tret = ytphy_write_ext(phydev, YTPHY_WOL_CFG_REG, val);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\treturn 0;\n+}\n+\n+static void ytphy_get_wol(struct phy_device *phydev, struct ethtool_wolinfo *wol)\n+{\n+\tint val = 0;\n+\n+\twol->supported = WAKE_MAGIC;\n+\twol->wolopts = 0;\n+\n+\tval = ytphy_read_ext(phydev, YTPHY_WOL_CFG_REG);\n+\tif (val < 0)\n+\t\treturn;\n+\n+\tif (val & YTPHY_WOL_CFG_EN)\n+\t\twol->wolopts |= WAKE_MAGIC;\n+\n+\treturn;\n+}\n+\n+static int ytphy_set_wol(struct phy_device *phydev, struct ethtool_wolinfo *wol)\n+{\n+\tint ret, pre_page, val;\n+\tytphy_wol_cfg_t wol_cfg;\n+\tstruct net_device *p_attached_dev = phydev->attached_dev;\n+\n+\tmemset(&wol_cfg,0,sizeof(ytphy_wol_cfg_t));\n+\tpre_page = ytphy_read_ext(phydev, 0xa000);\n+\tif (pre_page < 0)\n+\t\treturn pre_page;\n+\n+\t/* Switch to phy UTP page */\n+\tret = ytphy_switch_reg_space(phydev, YTPHY_REG_SPACE_UTP);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\tif (wol->wolopts & WAKE_MAGIC) {\n+\t\t\n+\t\t/* Enable the WOL interrupt */\n+\t\tval = phy_read(phydev, YTPHY_UTP_INTR_REG);\n+\t\tval |= YTPHY_WOL_INTR;\n+\t\tret = phy_write(phydev, YTPHY_UTP_INTR_REG, val);\n+\t\tif (ret < 0)\n+\t\t\treturn ret;\n+\n+\t\t/* Set the WOL config */\n+\t\twol_cfg.enable = 1; //enable\n+\t\twol_cfg.type= YTPHY_WOL_TYPE_PULSE;\n+\t\twol_cfg.width= YTPHY_WOL_WIDTH_672MS;\n+\t\tret = ytphy_wol_en_cfg(phydev, wol_cfg);\n+\t\tif (ret < 0)\n+\t\t\treturn ret;\n+\n+\t\t/* Store the device address for the magic packet */\n+\t\tret = ytphy_write_ext(phydev, YTPHY_MAGIC_PACKET_MAC_ADDR2,\n+\t\t\t\t((p_attached_dev->dev_addr[0] << 8) |\n+\t\t\t\t p_attached_dev->dev_addr[1]));\n+\t\tif (ret < 0)\n+\t\t\treturn ret;\n+\t\tret = ytphy_write_ext(phydev, YTPHY_MAGIC_PACKET_MAC_ADDR1,\n+\t\t\t\t((p_attached_dev->dev_addr[2] << 8) |\n+\t\t\t\t p_attached_dev->dev_addr[3]));\n+\t\tif (ret < 0)\n+\t\t\treturn ret;\n+\t\tret = ytphy_write_ext(phydev, YTPHY_MAGIC_PACKET_MAC_ADDR0,\n+\t\t\t\t((p_attached_dev->dev_addr[4] << 8) |\n+\t\t\t\t p_attached_dev->dev_addr[5]));\n+\t\tif (ret < 0)\n+\t\t\treturn ret;\n+\t} else {\n+\t\twol_cfg.enable = 0; //disable\n+\t\twol_cfg.type= YTPHY_WOL_TYPE_MAX;\n+\t\twol_cfg.width= YTPHY_WOL_WIDTH_MAX;\n+\t\tret = ytphy_wol_en_cfg(phydev, wol_cfg);\n+\t\tif (ret < 0)\n+\t\t\treturn ret;\n+\t}\n+\n+\t/* Recover to previous register space page */\n+\tret = ytphy_switch_reg_space(phydev, pre_page);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\treturn 0;\n+}\n+\n+#endif /*(YTPHY_ENABLE_WOL)*/\n+\n+static int yt8521_config_init(struct phy_device *phydev)\n+{\n+\tint ret;\n+\tint val;\n+\n+\tphydev->irq = PHY_POLL;\n+\n+\tytphy_write_ext(phydev, 0xa000, 0);\n+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) )\n+\tret = ytphy_config_init(phydev);\n+#else\n+\tret = genphy_config_init(phydev);\n+#endif\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\t/* disable auto sleep */\n+\tval = ytphy_read_ext(phydev, YT8521_EXTREG_SLEEP_CONTROL1);\n+\tif (val < 0)\n+\t\treturn val;\n+\n+\tval &= (~BIT(YT8521_EN_SLEEP_SW_BIT));\n+\n+\tret = ytphy_write_ext(phydev, YT8521_EXTREG_SLEEP_CONTROL1, val);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\t/* enable RXC clock when no wire plug */\n+\tret = ytphy_write_ext(phydev, 0xa000, 0);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\tval = ytphy_read_ext(phydev, 0xc);\n+\tif (val < 0)\n+\t\treturn val;\n+\tval &= ~(1 << 12);\n+\tret = ytphy_write_ext(phydev, 0xc, val);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\tprintk (KERN_INFO \"yt8521_config_init, 8521 init call out.\\n\");\n+\treturn ret;\n+}\n+\n+/*\n+ * for fiber mode, there is no 10M speed mode and \n+ * this function is for this purpose.\n+ */\n+static int yt8521_adjust_status(struct phy_device *phydev, int val, int is_utp)\n+{\n+\tint speed_mode, duplex;\n+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) )\n+\tint speed = -1;\n+#else\n+\tint speed = SPEED_UNKNOWN;\n+#endif\n+\n+\tduplex = (val & YT8512_DUPLEX) >> YT8521_DUPLEX_BIT;\n+\tspeed_mode = (val & YT8521_SPEED_MODE) >> YT8521_SPEED_MODE_BIT;\n+\tswitch (speed_mode) {\n+\tcase 0:\n+\t\tif (is_utp)\n+\t\t\tspeed = SPEED_10;\n+\t\tbreak;\n+\tcase 1:\n+\t\tspeed = SPEED_100;\n+\t\tbreak;\n+\tcase 2:\n+\t\tspeed = SPEED_1000;\n+\t\tbreak;\n+\tcase 3:\n+\t\tbreak;\n+\tdefault:\n+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) )\n+\t\tspeed = -1;\n+#else\n+\t\tspeed = SPEED_UNKNOWN;\n+#endif\n+\t\tbreak;\n+\t}\n+\n+\tphydev->speed = speed;\n+\tphydev->duplex = duplex;\n+\t//printk (KERN_INFO \"yt8521_adjust_status call out,regval=0x%04x,mode=%s,speed=%dm...\\n\", val,is_utp?\"utp\":\"fiber\", phydev->speed);\n+\n+\treturn 0;\n+}\n+\n+/*\n+ * for fiber mode, when speed is 100M, there is no definition for autonegotiation, and\n+ * this function handles this case and return 1 per linux kernel's polling.\n+ */\n+int yt8521_aneg_done (struct phy_device *phydev)\n+{\n+\n+\t//printk(\"yt8521_aneg_done callin,speed=%dm,linkmoded=%d\\n\", phydev->speed,link_mode_8521);\n+\n+\tif((32 == link_mode_8521) && (SPEED_100 == phydev->speed))\n+\t{\n+\t\treturn 1/*link_mode_8521*/;\n+\t}\n+\n+#if ( LINUX_VERSION_CODE > KERNEL_VERSION(3,11,0) )\n+\treturn genphy_aneg_done(phydev);\n+#else\n+\treturn 1;\n+#endif\n+}\n+\n+static int yt8521_read_status(struct phy_device *phydev)\n+{\n+\tint ret;\n+\tvolatile int val, yt8521_fiber_latch_val, yt8521_fiber_curr_val;\n+\tvolatile int link;\n+\tint link_utp = 0, link_fiber = 0;\n+\n+#if (YT8521_PHY_MODE_CURR != YT8521_PHY_MODE_FIBER)\n+\t/* reading UTP */\n+\tret = ytphy_write_ext(phydev, 0xa000, 0);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\tval = phy_read(phydev, REG_PHY_SPEC_STATUS);\n+\tif (val < 0)\n+\t\treturn val;\n+\n+\tlink = val & (BIT(YT8521_LINK_STATUS_BIT));\n+\tif (link) {\n+\t\tlink_utp = 1;\n+\t\tlink_mode_8521 = 1;\n+\t\tyt8521_adjust_status(phydev, val, 1);\n+\t} else {\n+\t\tlink_utp = 0;\n+\t}\n+#endif //(YT8521_PHY_MODE_CURR != YT8521_PHY_MODE_FIBER)\n+\n+#if (YT8521_PHY_MODE_CURR != YT8521_PHY_MODE_UTP)\n+\t/* reading Fiber */\n+\tret = ytphy_write_ext(phydev, 0xa000, 2);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\tval = phy_read(phydev, REG_PHY_SPEC_STATUS);\n+\tif (val < 0)\n+\t\treturn val;\n+\t\n+\t//note: below debug information is used to check multiple PHy ports.\n+\t//printk (KERN_INFO \"yt8521_read_status, fiber status=%04x,macbase=0x%08lx\\n\", val,(unsigned long)phydev->attached_dev);\n+\n+\t/* for fiber, from 1000m to 100m, there is not link down from 0x11, and check reg 1 to identify such case\n+\t * this is important for Linux kernel for that, missing linkdown event will cause problem.\n+\t */\t\n+\tyt8521_fiber_latch_val = phy_read(phydev, MII_BMSR);\n+\tyt8521_fiber_curr_val = phy_read(phydev, MII_BMSR);\n+\tlink = val & (BIT(YT8521_LINK_STATUS_BIT));\n+\tif((link) && (yt8521_fiber_latch_val != yt8521_fiber_curr_val))\n+\t{\n+\t\tlink = 0;\n+\t\tprintk (KERN_INFO \"yt8521_read_status, fiber link down detect,latch=%04x,curr=%04x\\n\", yt8521_fiber_latch_val,yt8521_fiber_curr_val);\n+\t}\n+\t\n+\tif (link) {\n+\t\tlink_fiber = 1;\n+\t\tyt8521_adjust_status(phydev, val, 0);\n+\t\tlink_mode_8521 = 32; //fiber mode\n+\n+\n+\t} else {\n+\t\tlink_fiber = 0;\n+\t}\n+#endif //(YT8521_PHY_MODE_CURR != YT8521_PHY_MODE_UTP)\n+\n+\tif (link_utp || link_fiber) {\n+\t\tphydev->link = 1;\n+\t} else {\n+\t\tphydev->link = 0;\n+\t\tlink_mode_8521 = 0;\n+\t}\n+\n+#if (YT8521_PHY_MODE_CURR != YT8521_PHY_MODE_FIBER)\n+\tif (link_utp) {\n+\t\tytphy_write_ext(phydev, 0xa000, 0);\n+\t}\n+#endif\n+\n+\t//printk (KERN_INFO \"yzhang..8521 read status call out,link=%d,linkmode=%d\\n\", phydev->link, link_mode_8521 );\n+\treturn 0;\n+}\n+\n+int yt8521_suspend(struct phy_device *phydev)\n+{\n+#if !(SYS_WAKEUP_BASED_ON_ETH_PKT)\t\t\t\t\n+\tint value;\n+\n+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) )\n+\tmutex_lock(&phydev->lock);\n+#else\n+\t/* no need lock in 4.19 */\n+#endif\n+\n+\tytphy_write_ext(phydev, 0xa000, 0);\n+\tvalue = phy_read(phydev, MII_BMCR);\n+\tphy_write(phydev, MII_BMCR, value | BMCR_PDOWN);\n+\n+\tytphy_write_ext(phydev, 0xa000, 2);\n+\tvalue = phy_read(phydev, MII_BMCR);\n+\tphy_write(phydev, MII_BMCR, value | BMCR_PDOWN);\n+\n+\tytphy_write_ext(phydev, 0xa000, 0);\n+\n+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) )\n+\tmutex_unlock(&phydev->lock);\n+#else\n+\t/* no need lock/unlock in 4.19 */\n+#endif\n+#endif /*!(SYS_WAKEUP_BASED_ON_ETH_PKT)*/\t\t\t\t\n+\n+\treturn 0;\n+}\n+\n+int yt8521_resume(struct phy_device *phydev)\n+{\n+#if !(SYS_WAKEUP_BASED_ON_ETH_PKT)\t\t\t\t\n+\tint value;\n+\tint ret;\n+\t\n+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) )\n+\tmutex_lock(&phydev->lock);\n+#else\n+\t/* no need lock/unlock in 4.19 */\n+#endif\n+\n+\tytphy_write_ext(phydev, 0xa000, 0);\n+\tvalue = phy_read(phydev, MII_BMCR);\n+\tphy_write(phydev, MII_BMCR, value & ~BMCR_PDOWN);\n+\n+\t/* disable auto sleep */\n+\tvalue = ytphy_read_ext(phydev, YT8521_EXTREG_SLEEP_CONTROL1);\n+\tif (value < 0)\n+\t\treturn value;\n+\n+\tvalue &= (~BIT(YT8521_EN_SLEEP_SW_BIT));\n+\tret = ytphy_write_ext(phydev, YT8521_EXTREG_SLEEP_CONTROL1, value);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\t/* enable RXC clock when no wire plug */\n+\tvalue = ytphy_read_ext(phydev, 0xc);\n+\tif (value < 0)\n+\t\treturn value;\n+\tvalue &= ~(1 << 12);\n+\tret = ytphy_write_ext(phydev, 0xc, value);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\tytphy_write_ext(phydev, 0xa000, 2);\n+\tvalue = phy_read(phydev, MII_BMCR);\n+\tphy_write(phydev, MII_BMCR, value & ~BMCR_PDOWN);\n+\n+#if (YT8521_PHY_MODE_CURR != YT8521_PHY_MODE_FIBER)\n+\tytphy_write_ext(phydev, 0xa000, 0);\n+#endif\n+\n+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) )\n+\tmutex_unlock(&phydev->lock);\n+#else\n+\t/* no need lock/unlock in 4.19 */\n+#endif\n+#endif /*!(SYS_WAKEUP_BASED_ON_ETH_PKT)*/\t\t\t\t\n+\n+\treturn 0;\n+}\n+\n+\n+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) )\n+#else\n+int yt8618_soft_reset(struct phy_device *phydev)\n+{\n+\tint ret;\n+\n+\tytphy_write_ext(phydev, 0xa000, 0);\n+\tret = genphy_soft_reset(phydev);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\treturn 0;\n+}\n+\n+int yt8614_soft_reset(struct phy_device *phydev)\n+{\n+\tint ret;\n+\n+\t/* utp */\n+\tytphy_write_ext(phydev, 0xa000, 0);\n+\tret = genphy_soft_reset(phydev);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\t/* qsgmii */\n+\tytphy_write_ext(phydev, 0xa000, 2);\n+\tret = genphy_soft_reset(phydev);\n+\tif (ret < 0) {\n+\t\tytphy_write_ext(phydev, 0xa000, 0); //back to utp mode\n+\t\treturn ret;\n+\t}\n+\n+\t/* sgmii */\n+\tytphy_write_ext(phydev, 0xa000, 3);\n+\tret = genphy_soft_reset(phydev);\n+\tif (ret < 0) {\n+\t\tytphy_write_ext(phydev, 0xa000, 0); //back to utp mode\n+\t\treturn ret;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+#endif\n+\n+static int yt8618_config_init(struct phy_device *phydev)\n+{\n+\tint ret;\n+\tint val;\n+\n+\tphydev->irq = PHY_POLL;\n+\n+\tif(0xff == yt_mport_base_phy_addr)\n+\t\t/* by default, we think the first phy should be the base phy addr. for mul */\n+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) )\n+\t{\n+\t\tyt_mport_base_phy_addr = phydev->addr;\n+\t}else if (yt_mport_base_phy_addr > phydev->addr) { \n+\t\tprintk (KERN_INFO \"yzhang..8618 init, phy address mismatch, base=%d, cur=%d\\n\", yt_mport_base_phy_addr, phydev->addr);\n+\t}\n+#else\n+\t{\n+\t\tyt_mport_base_phy_addr = phydev->mdio.addr;\n+\t}else if (yt_mport_base_phy_addr > phydev->mdio.addr) { \n+\t\tprintk (KERN_INFO \"yzhang..8618 init, phy address mismatch, base=%d, cur=%d\\n\", yt_mport_base_phy_addr, phydev->mdio.addr);\n+\t}\n+#endif\t\n+\n+\tytphy_write_ext(phydev, 0xa000, 0);\n+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) )\n+\tret = ytphy_config_init(phydev);\n+#else\n+\tret = genphy_config_init(phydev);\n+#endif\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\t/* for utp to optimize signal */\n+\tret = ytphy_write_ext(phydev, 0x41, 0x33);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\tret = ytphy_write_ext(phydev, 0x42, 0x66);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\tret = ytphy_write_ext(phydev, 0x43, 0xaa);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\tret = ytphy_write_ext(phydev, 0x44, 0xd0d);\n+\tif (ret < 0)\n+\t\treturn ret;\n+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) )\n+\tif((phydev->addr > yt_mport_base_phy_addr) && ((2 == phydev->addr - yt_mport_base_phy_addr) || (5 == phydev->addr - yt_mport_base_phy_addr)))\n+#else\n+\tif((phydev->mdio.addr > yt_mport_base_phy_addr) && ((2 == phydev->mdio.addr - yt_mport_base_phy_addr) || (5 == phydev->mdio.addr - yt_mport_base_phy_addr)))\n+#endif\n+\t{\n+\t\tret = ytphy_write_ext(phydev, 0x44, 0x2929);\n+\t\tif (ret < 0)\n+\t\t\treturn ret;\n+\t}\n+\n+\tval = phy_read(phydev, MII_BMCR);\n+\tphy_write(phydev, MII_BMCR, val | BMCR_RESET);\n+\n+\tprintk (KERN_INFO \"yt8618_config_init call out.\\n\");\n+\treturn ret;\n+}\n+\n+static int yt8614_config_init(struct phy_device *phydev)\n+{\n+\tint ret = 0;\n+\n+\tphydev->irq = PHY_POLL;\n+\n+\tif(0xff == yt_mport_base_phy_addr_8614)\n+\t\t/* by default, we think the first phy should be the base phy addr. for mul */\n+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) )\n+\t{\n+\t\tyt_mport_base_phy_addr_8614 = (unsigned int)phydev->addr;\n+\t}else if (yt_mport_base_phy_addr_8614 > (unsigned int)phydev->addr) { \n+\t\tprintk (KERN_INFO \"yzhang..8618 init, phy address mismatch, base=%u, cur=%d\\n\", yt_mport_base_phy_addr_8614, phydev->addr);\n+\t}\n+#else\n+\t{\n+\t\tyt_mport_base_phy_addr_8614 = (unsigned int)phydev->mdio.addr;\n+\t}else if (yt_mport_base_phy_addr_8614 > (unsigned int)phydev->mdio.addr) { \n+\t\tprintk (KERN_INFO \"yzhang..8618 init, phy address mismatch, base=%u, cur=%d\\n\", yt_mport_base_phy_addr_8614, phydev->mdio.addr);\n+\t}\n+#endif\t\n+\treturn ret;\n+}\n+\n+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) )\n+#define yt8614_get_port_from_phydev(phydev) ((0xff == yt_mport_base_phy_addr_8614) && (yt_mport_base_phy_addr_8614 <= (phydev)->addr) ? 0 : (unsigned int)((phydev)->addr) - yt_mport_base_phy_addr_8614)\n+#else\n+#define yt8614_get_port_from_phydev(phydev) ((0xff == yt_mport_base_phy_addr_8614) && (yt_mport_base_phy_addr_8614 <= (phydev)->mdio.addr) ? 0 : (unsigned int)((phydev)->mdio.addr) - yt_mport_base_phy_addr_8614)\n+#endif\n+\n+int yt8618_aneg_done (struct phy_device *phydev)\n+{\n+\n+\treturn genphy_aneg_done(phydev);\n+}\n+\n+int yt8614_aneg_done (struct phy_device *phydev)\n+{\n+\tint port = yt8614_get_port_from_phydev(phydev);\n+\t\n+\t/*it should be used for 8614 fiber*/\n+\tif((32 == link_mode_8614[port]) && (SPEED_100 == phydev->speed))\n+\t{\n+\t\treturn 1;\n+\t}\n+\n+\treturn genphy_aneg_done(phydev);\n+}\n+\n+static int yt8614_read_status(struct phy_device *phydev)\n+{\n+        //int i;\n+\tint ret;\n+\tvolatile int val, yt8614_fiber_latch_val, yt8614_fiber_curr_val;\n+\tvolatile int link;\n+\tint link_utp = 0, link_fiber = 0;\n+\tint port = yt8614_get_port_from_phydev(phydev);\n+\n+#if (YT8614_PHY_MODE_CURR != YT8521_PHY_MODE_FIBER)\n+\t/* switch to utp and reading regs  */\n+\tret = ytphy_write_ext(phydev, 0xa000, 0);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\tval = phy_read(phydev, REG_PHY_SPEC_STATUS);\n+\tif (val < 0)\n+\t\treturn val;\n+\n+\tlink = val & (BIT(YT8521_LINK_STATUS_BIT));\n+\tif (link) {\n+\t\tlink_utp = 1;\n+\t\t// here is same as 8521 and re-use the function;\n+\t\tyt8521_adjust_status(phydev, val, 1);  \n+\t} else {\n+\t\tlink_utp = 0;\n+\t}\n+#endif //(YT8614_PHY_MODE_CURR != YT8521_PHY_MODE_FIBER)\n+\n+#if (YT8614_PHY_MODE_CURR != YT8521_PHY_MODE_UTP)\n+\t/* reading Fiber/sgmii */\n+\tret = ytphy_write_ext(phydev, 0xa000, 3);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\tval = phy_read(phydev, REG_PHY_SPEC_STATUS);\n+\tif (val < 0)\n+\t\treturn val;\n+\t\n+\t//printk (KERN_INFO \"yzhang..8614 read fiber status=%04x,macbase=0x%08lx\\n\", val,(unsigned long)phydev->attached_dev);\n+\n+\t/* for fiber, from 1000m to 100m, there is not link down from 0x11, and check reg 1 to identify such case */\t\n+\tyt8614_fiber_latch_val = phy_read(phydev, MII_BMSR);\n+\tyt8614_fiber_curr_val = phy_read(phydev, MII_BMSR);\n+\tlink = val & (BIT(YT8521_LINK_STATUS_BIT));\n+\tif((link) && (yt8614_fiber_latch_val != yt8614_fiber_curr_val))\n+\t{\n+\t\tlink = 0;\n+\t\tprintk (KERN_INFO \"yt8614_read_status, fiber link down detect,latch=%04x,curr=%04x\\n\", yt8614_fiber_latch_val,yt8614_fiber_curr_val);\n+\t}\n+\t\n+\tif (link) {\n+\t\tlink_fiber = 1;\n+\t\tyt8521_adjust_status(phydev, val, 0);\n+\t\tlink_mode_8614[port] = 32; //fiber mode\n+\n+\n+\t} else {\n+\t\tlink_fiber = 0;\n+\t}\n+#endif //(YT8521_PHY_MODE_CURR != YT8521_PHY_MODE_UTP)\n+\n+\tif (link_utp || link_fiber) {\n+\t\tphydev->link = 1;\n+\t} else {\n+\t\tphydev->link = 0;\n+\t\tlink_mode_8614[port] = 0;\n+\t}\n+\n+#if (YT8614_PHY_MODE_CURR != YT8521_PHY_MODE_FIBER)\n+\tif (link_utp) {\n+\t\tytphy_write_ext(phydev, 0xa000, 0);\n+\t}\n+#endif\n+\t//printk (KERN_INFO \"yt8614_read_status call out,link=%d,linkmode=%d\\n\", phydev->link, link_mode_8614[port] );\n+\n+\treturn 0;\n+}\n+\n+static int yt8618_read_status(struct phy_device *phydev)\n+{\n+\tint ret;\n+\tvolatile int val; //maybe for 8614 yt8521_fiber_latch_val, yt8521_fiber_curr_val;\n+\tvolatile int link;\n+\tint link_utp = 0, link_fiber = 0;\n+\n+\t/* switch to utp and reading regs  */\n+\tret = ytphy_write_ext(phydev, 0xa000, 0);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\tval = phy_read(phydev, REG_PHY_SPEC_STATUS);\n+\tif (val < 0)\n+\t\treturn val;\n+\n+\tlink = val & (BIT(YT8521_LINK_STATUS_BIT));\n+\tif (link) {\n+\t\tlink_utp = 1;\n+\t\tyt8521_adjust_status(phydev, val, 1);\n+\t} else {\n+\t\tlink_utp = 0;\n+\t}\n+\n+\tif (link_utp || link_fiber) {\n+\t\tphydev->link = 1;\n+\t} else {\n+\t\tphydev->link = 0;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+int yt8618_suspend(struct phy_device *phydev)\n+{\n+#if !(SYS_WAKEUP_BASED_ON_ETH_PKT)\t\t\t\t\n+\tint value;\n+\n+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) )\n+\tmutex_lock(&phydev->lock);\n+#else\n+\t/* no need lock in 4.19 */\n+#endif\n+\n+\tytphy_write_ext(phydev, 0xa000, 0);\n+\tvalue = phy_read(phydev, MII_BMCR);\n+\tphy_write(phydev, MII_BMCR, value | BMCR_PDOWN);\n+\n+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) )\n+\tmutex_unlock(&phydev->lock);\n+#else\n+\t/* no need lock/unlock in 4.19 */\n+#endif\n+#endif /*!(SYS_WAKEUP_BASED_ON_ETH_PKT)*/\t\t\t\t\n+\n+\treturn 0;\n+}\n+\n+int yt8618_resume(struct phy_device *phydev)\n+{\n+#if !(SYS_WAKEUP_BASED_ON_ETH_PKT)\t\t\t\t\n+\tint value;\n+\n+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) )\n+\tmutex_lock(&phydev->lock);\n+#else\n+\t/* no need lock/unlock in 4.19 */\n+#endif\n+\n+\tytphy_write_ext(phydev, 0xa000, 0);\n+\tvalue = phy_read(phydev, MII_BMCR);\n+\tphy_write(phydev, MII_BMCR, value & ~BMCR_PDOWN);\n+\n+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) )\n+\tmutex_unlock(&phydev->lock);\n+#else\n+\t/* no need lock/unlock in 4.19 */\n+#endif\n+#endif /*!(SYS_WAKEUP_BASED_ON_ETH_PKT)*/\t\t\t\t\n+\n+\treturn 0;\n+}\n+\n+int yt8614_suspend(struct phy_device *phydev)\n+{\n+#if !(SYS_WAKEUP_BASED_ON_ETH_PKT)\t\t\t\t\n+\tint value;\n+\n+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) )\n+\tmutex_lock(&phydev->lock);\n+#else\n+\t/* no need lock in 4.19 */\n+#endif\n+\n+\tytphy_write_ext(phydev, 0xa000, 0);\n+\tvalue = phy_read(phydev, MII_BMCR);\n+\tphy_write(phydev, MII_BMCR, value | BMCR_PDOWN);\n+\n+\tytphy_write_ext(phydev, 0xa000, 3);\n+\tvalue = phy_read(phydev, MII_BMCR);\n+\tphy_write(phydev, MII_BMCR, value | BMCR_PDOWN);\n+\n+\tytphy_write_ext(phydev, 0xa000, 0);\n+\n+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) )\n+\tmutex_unlock(&phydev->lock);\n+#else\n+\t/* no need lock/unlock in 4.19 */\n+#endif\n+#endif /*!(SYS_WAKEUP_BASED_ON_ETH_PKT)*/\t\t\t\t\n+\n+\treturn 0;\n+}\n+\n+int yt8614_resume(struct phy_device *phydev)\n+{\n+#if !(SYS_WAKEUP_BASED_ON_ETH_PKT)\t\t\t\t\n+\tint value;\n+\n+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) )\n+\tmutex_lock(&phydev->lock);\n+#else\n+\t/* no need lock/unlock in 4.19 */\n+#endif\n+\n+\tytphy_write_ext(phydev, 0xa000, 0);\n+\tvalue = phy_read(phydev, MII_BMCR);\n+\tphy_write(phydev, MII_BMCR, value & ~BMCR_PDOWN);\n+\n+\tytphy_write_ext(phydev, 0xa000, 3);\n+\tvalue = phy_read(phydev, MII_BMCR);\n+\tphy_write(phydev, MII_BMCR, value & ~BMCR_PDOWN);\n+\n+\tytphy_write_ext(phydev, 0xa000, 0);\n+\n+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) )\n+\tmutex_unlock(&phydev->lock);\n+#else\n+\t/* no need lock/unlock in 4.19 */\n+#endif\n+#endif /*!(SYS_WAKEUP_BASED_ON_ETH_PKT)*/\t\t\t\t\n+\n+\treturn 0;\n+}\n+\n+\n+static struct phy_driver ytphy_drvs[] = {\n+\t{\n+\t\t.phy_id         = PHY_ID_YT8010,\n+\t\t.name           = \"YT8010 Automotive Ethernet\",\n+\t\t.phy_id_mask    = MOTORCOMM_PHY_ID_MASK,\n+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(5,4,0) )\n+\t\t.features       = PHY_BASIC_FEATURES,\n+\t\t.flags          = PHY_HAS_INTERRUPT,\n+#endif\t\t\n+\t\t.config_aneg    = yt8010_config_aneg,\n+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) )\n+\t\t.config_init\t= ytphy_config_init,\n+#else\n+\t\t.config_init\t= genphy_config_init,\n+#endif\n+\t\t.read_status    = genphy_read_status,\n+\t}, {\n+\t\t.phy_id\t\t= PHY_ID_YT8510,\n+\t\t.name\t\t= \"YT8510 100/10Mb Ethernet\",\n+\t\t.phy_id_mask\t= MOTORCOMM_PHY_ID_MASK,\n+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(5,4,0) )\n+\t\t.features\t= PHY_BASIC_FEATURES,\n+\t\t.flags\t\t\t= PHY_HAS_INTERRUPT,\n+#endif\t\t\n+\t\t.config_aneg\t= genphy_config_aneg,\n+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) )\n+\t\t.config_init\t= ytphy_config_init,\n+#else\n+\t\t.config_init\t= genphy_config_init,\n+#endif\n+\t\t.read_status\t= genphy_read_status,\n+\t}, {\n+\t\t.phy_id\t\t= PHY_ID_YT8511,\n+\t\t.name\t\t= \"YT8511 Gigabit Ethernet\",\n+\t\t.phy_id_mask\t= MOTORCOMM_PHY_ID_MASK,\n+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(5,4,0) )\n+\t\t.features\t= PHY_GBIT_FEATURES,\n+\t\t.flags\t\t\t= PHY_HAS_INTERRUPT,\n+#endif\t\t\n+\t\t.config_aneg\t= genphy_config_aneg,\n+#if GMAC_CLOCK_INPUT_NEEDED\n+\t\t.config_init\t= yt8511_config_init,\n+#else\n+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) )\n+\t\t.config_init\t= ytphy_config_init,\n+#else\n+\t\t.config_init\t= genphy_config_init,\n+#endif\n+#endif\n+\t\t.read_status\t= genphy_read_status,\n+\t\t.suspend\t= genphy_suspend,\n+\t\t.resume\t\t= genphy_resume,\n+\t}, {\n+\t\t.phy_id\t\t= PHY_ID_YT8512,\n+\t\t.name\t\t= \"YT8512 Ethernet\",\n+\t\t.phy_id_mask\t= MOTORCOMM_PHY_ID_MASK,\n+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(5,4,0) )\n+\t\t.features\t= PHY_BASIC_FEATURES,\n+\t\t.flags\t\t\t= PHY_HAS_INTERRUPT,\n+#endif\t\t\n+\t\t.config_aneg\t= genphy_config_aneg,\n+\t\t.config_init\t= yt8512_config_init,\n+\t\t.read_status\t= yt8512_read_status,\n+\t\t.suspend\t= genphy_suspend,\n+\t\t.resume\t\t= genphy_resume,\n+\t}, {\n+\t\t.phy_id\t\t= PHY_ID_YT8512B,\n+\t\t.name\t\t= \"YT8512B Ethernet\",\n+\t\t.phy_id_mask\t= MOTORCOMM_PHY_ID_MASK,\n+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(5,4,0) )\n+\t\t.features\t= PHY_BASIC_FEATURES,\n+\t\t.flags\t\t\t= PHY_HAS_INTERRUPT,\n+#endif\t\t\n+\t\t.config_aneg\t= genphy_config_aneg,\n+\t\t.config_init\t= yt8512_config_init,\n+\t\t.read_status\t= yt8512_read_status,\n+\t\t.suspend\t= genphy_suspend,\n+\t\t.resume\t\t= genphy_resume,\n+\t}, {\n+        .phy_id         = PHY_ID_YT8521,\n+        .name           = \"YT8521 Ethernet\",\n+        .phy_id_mask    = MOTORCOMM_PHY_ID_MASK,\n+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(5,4,0) )\n+        .features       = PHY_BASIC_FEATURES | PHY_GBIT_FEATURES,\n+#endif\n+        .flags          = PHY_POLL,\n+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) )\n+#else\n+\t\t.soft_reset\t= yt8521_soft_reset,\n+#endif\n+        .config_aneg    = genphy_config_aneg,\n+#if ( LINUX_VERSION_CODE > KERNEL_VERSION(3,11,0) )\n+        .aneg_done\t= yt8521_aneg_done,\n+#endif\n+        .config_init    = yt8521_config_init,\n+        .read_status    = yt8521_read_status,\n+        .suspend        = yt8521_suspend,\n+        .resume         = yt8521_resume,\n+#if (YTPHY_ENABLE_WOL)\n+\t\t.get_wol\t\t= &ytphy_get_wol,\n+\t\t.set_wol\t\t= &ytphy_set_wol,\n+#endif                \n+        },{\n+\t\t/* same as 8521 */\n+        .phy_id         = PHY_ID_YT8531S,\n+        .name           = \"YT8531S Ethernet\",\n+        .phy_id_mask    = MOTORCOMM_PHY_ID_MASK,\n+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(5,4,0) )\n+        .features       = PHY_BASIC_FEATURES | PHY_GBIT_FEATURES,\n+#endif\n+        .flags          = PHY_POLL,\n+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) )\n+#else\n+\t\t.soft_reset\t= yt8521_soft_reset,\n+#endif\n+        .config_aneg    = genphy_config_aneg,\n+#if ( LINUX_VERSION_CODE > KERNEL_VERSION(3,11,0) )\n+        .aneg_done\t= yt8521_aneg_done,\n+#endif\n+        .config_init    = yt8521_config_init,\n+        .read_status    = yt8521_read_status,\n+        .suspend        = yt8521_suspend,\n+        .resume         = yt8521_resume,\n+#if (YTPHY_ENABLE_WOL)\n+\t\t.get_wol\t\t= &ytphy_get_wol,\n+\t\t.set_wol\t\t= &ytphy_set_wol,\n+#endif                \n+        }, {\n+        /* same as 8511 */\n+\t\t.phy_id\t\t= PHY_ID_YT8531,\n+\t\t.name\t\t= \"YT8531 Gigabit Ethernet\",\n+\t\t.phy_id_mask\t= MOTORCOMM_PHY_ID_MASK,\n+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(5,4,0) )\n+\t\t.features\t= PHY_BASIC_FEATURES | PHY_GBIT_FEATURES,\n+\t\t.flags\t\t\t= PHY_HAS_INTERRUPT,\n+#endif\t\t\n+\t\t.config_aneg\t= genphy_config_aneg,\n+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) )\n+\t\t.config_init\t= ytphy_config_init,\n+#else\n+\t\t.config_init\t= genphy_config_init,\n+#endif\n+\t\t.read_status\t= genphy_read_status,\n+\t\t.suspend\t= genphy_suspend,\n+\t\t.resume\t\t= genphy_resume,\n+#if (YTPHY_ENABLE_WOL)\n+\t\t.get_wol\t\t= &ytphy_get_wol,\n+\t\t.set_wol\t\t= &ytphy_set_wol,\n+#endif                \n+\t}, {\n+        .phy_id         = PHY_ID_YT8618,\n+        .name           = \"YT8618 Ethernet\",\n+        .phy_id_mask    = MOTORCOMM_MPHY_ID_MASK,\n+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(5,4,0) )\n+        .features       = PHY_BASIC_FEATURES | PHY_GBIT_FEATURES,\n+#endif\n+        .flags          = PHY_POLL,\n+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) )\n+#else\n+\t\t.soft_reset\t= yt8618_soft_reset,\n+#endif\n+        .config_aneg    = genphy_config_aneg,\n+#if ( LINUX_VERSION_CODE > KERNEL_VERSION(3,11,0) )\n+        .aneg_done\t\t= yt8618_aneg_done,\n+#endif\n+        .config_init    = yt8618_config_init,\n+        .read_status    = yt8618_read_status,\n+        .suspend        = yt8618_suspend,\n+        .resume         = yt8618_resume,\n+    }, {\n+\t\t.phy_id \t\t= PHY_ID_YT8614,\n+\t\t.name\t\t\t= \"YT8614 Ethernet\",\n+\t\t.phy_id_mask\t= MOTORCOMM_MPHY_ID_MASK_8614,\n+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(5,4,0) )\n+\t\t.features\t\t= PHY_BASIC_FEATURES | PHY_GBIT_FEATURES,\n+#endif\n+\t\t.flags\t\t\t= PHY_POLL,\n+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) )\n+#else\n+\t\t.soft_reset = yt8614_soft_reset,\n+#endif\n+\t\t.config_aneg\t= genphy_config_aneg,\n+#if ( LINUX_VERSION_CODE > KERNEL_VERSION(3,11,0) )\n+\t\t.aneg_done\t\t= yt8614_aneg_done,\n+#endif\n+\t\t.config_init\t= yt8614_config_init,\n+\t\t.read_status\t= yt8614_read_status,\n+\t\t.suspend\t\t= yt8614_suspend,\n+\t\t.resume \t\t= yt8614_resume,\n+\t\t}, \n+};\n+\n+#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) )\n+static int ytphy_drivers_register(struct phy_driver* phy_drvs, int size)\n+{\n+\tint i, j;\n+\tint ret;\n+\n+\tfor (i = 0; i < size; i++) {\n+\t\tret = phy_driver_register(&phy_drvs[i]);\n+\t\tif (ret)\n+\t\t\tgoto err;\n+\t}\n+\n+\treturn 0;\n+\n+err:\n+\tfor (j = 0; j < i; j++)\n+\t\tphy_driver_unregister(&phy_drvs[j]);\n+\n+\treturn ret;\n+}\n+\n+static void ytphy_drivers_unregister(struct phy_driver* phy_drvs, int size)\n+{\n+\tint i;\n+\n+\tfor (i = 0; i < size; i++) {\n+\t\tphy_driver_unregister(&phy_drvs[i]);\n+\t}\n+}\n+\n+static int __init ytphy_init(void)\n+{\n+\tprintk(\"motorcomm phy register\\n\");\n+\treturn ytphy_drivers_register(ytphy_drvs, ARRAY_SIZE(ytphy_drvs));\n+}\n+\n+static void __exit ytphy_exit(void)\n+{\n+\tprintk(\"motorcomm phy unregister\\n\");\n+\tytphy_drivers_unregister(ytphy_drvs, ARRAY_SIZE(ytphy_drvs));\n+}\n+\n+module_init(ytphy_init);\n+module_exit(ytphy_exit);\n+#else\n+/* for linux 4.x */\n+module_phy_driver(ytphy_drvs);\n+#endif\n+\n+MODULE_DESCRIPTION(\"Motorcomm PHY driver\");\n+MODULE_AUTHOR(\"Leilei Zhao\");\n+MODULE_LICENSE(\"GPL\");\n+\n+static struct mdio_device_id __maybe_unused motorcomm_tbl[] = {\n+\t{ PHY_ID_YT8010, MOTORCOMM_PHY_ID_MASK },\n+\t{ PHY_ID_YT8510, MOTORCOMM_PHY_ID_MASK },\n+\t{ PHY_ID_YT8511, MOTORCOMM_PHY_ID_MASK },\n+\t{ PHY_ID_YT8512, MOTORCOMM_PHY_ID_MASK },\n+\t{ PHY_ID_YT8512B, MOTORCOMM_PHY_ID_MASK },\n+\t{ PHY_ID_YT8521, MOTORCOMM_PHY_ID_MASK },\n+\t{ PHY_ID_YT8531S, MOTORCOMM_PHY_ID_8531_MASK },\n+\t{ PHY_ID_YT8531, MOTORCOMM_PHY_ID_8531_MASK },\n+\t{ PHY_ID_YT8618, MOTORCOMM_MPHY_ID_MASK },\n+\t{ PHY_ID_YT8614, MOTORCOMM_MPHY_ID_MASK_8614 },\n+\t{ }\n+};\n+\n+MODULE_DEVICE_TABLE(mdio, motorcomm_tbl);\n+\n+\ndiff --git a/drivers/net/phy/yt8614-phy.h b/drivers/net/phy/yt8614-phy.h\nnew file mode 100644\nindex 000000000..56a398338\n--- /dev/null\n+++ b/drivers/net/phy/yt8614-phy.h\n@@ -0,0 +1,491 @@\n+#ifndef _PHY_H_\n+#define _PHY_H_\n+\n+\n+/* configuration for driver */\n+\n+#define YT8614_MAX_LPORT_ID\t\t3\n+\n+#define YT8614_PHY_MODE_FIBER\t1 //fiber mode only\n+#define YT8614_PHY_MODE_UTP\t\t2 //utp mode only\n+#define YT8614_PHY_MODE_POLL\t3 //fiber and utp, poll mode\n+\n+/* please make choice according to system design\n+ * for Fiber only system, please define YT8614_PHY_MODE_CURR 1\n+ * for UTP only system, please define YT8614_PHY_MODE_CURR 2\n+ * for combo system, please define YT8614_PHY_MODE_CURR 3 \n+ */\n+#define YT8614_PHY_MODE_CURR\t3\n+\n+\n+\n+/* pls dont modify below lines */\n+\n+#define PHY_ID_YT8614  0x4F51E899 //serdes\n+#define MOTORCOMM_MPHY_ID_MASK_8614 0xffffffff\n+\n+#ifndef BOOL\n+#define BOOL unsigned int\n+#endif\n+\n+#ifndef FALSE\n+#define FALSE 0\n+#endif\n+\n+#ifndef TRUE\n+#define TRUE 1\n+#endif\n+\n+#ifndef SPEED_1000M\n+#define SPEED_1000M     2\n+#endif\n+#ifndef SPEED_100M\n+#define SPEED_100M     \t1\n+#endif\n+#ifndef SPEED_10M\n+#define SPEED_10M     \t0\n+#endif\n+\n+#ifndef SPEED_UNKNOWN\n+#define SPEED_UNKNOWN   0xffff\n+#endif\n+\n+#ifndef DUPLEX_FULL\n+#define DUPLEX_FULL\t\t1\t\n+#endif\n+#ifndef DUPLEX_HALF\n+#define DUPLEX_HALF\t\t0\t\n+#endif\n+\n+#ifndef BIT\n+#define BIT(n) (0x1<<(n))\n+#endif\n+#ifndef s32\n+typedef int  s32;\n+typedef unsigned int  u32;\n+typedef unsigned short  u16;\n+typedef unsigned char  u8;\n+#endif\n+\n+#ifndef REG_PHY_SPEC_STATUS\n+#define REG_PHY_SPEC_STATUS\t\t0x11\n+#define REG_DEBUG_ADDR_OFFSET\t\t0x1e\n+#define REG_DEBUG_DATA\t\t\t0x1f\n+#endif\n+\n+/**********YT8614************************************************/\n+\n+#define YT8614_SMI_SEL_PHY        0x0\n+#define YT8614_SMI_SEL_SDS_QSGMII 0x02\n+#define YT8614_SMI_SEL_SDS_SGMII  0x03\n+\n+/* yt8614 register type */\n+#define YT8614_TYPE_COMMON         0x01\n+#define YT8614_TYPE_UTP_MII        0x02\n+#define YT8614_TYPE_UTP_EXT        0x03\n+#define YT8614_TYPE_LDS_MII        0x04\n+#define YT8614_TYPE_UTP_MMD        0x05\n+#define YT8614_TYPE_SDS_QSGMII_MII 0x06\n+#define YT8614_TYPE_SDS_SGMII_MII  0x07\n+#define YT8614_TYPE_SDS_QSGMII_EXT 0x08\n+#define YT8614_TYPE_SDS_SGMII_EXT  0x09\n+\n+/* YT8614 extended common register */\n+#define YT8614_REG_COM_SMI_MUX        0xA000\n+#define YT8614_REG_COM_SLED_CFG0      0xA001\n+#define YT8614_REG_COM_PHY_ID         0xA002\n+#define YT8614_REG_COM_CHIP_VER       0xA003\n+#define YT8614_REG_COM_SLED_CFG       0xA004\n+#define YT8614_REG_COM_MODE_CHG_RESET 0xA005\n+#define YT8614_REG_COM_SYNCE0_CFG     0xA006\n+#define YT8614_REG_COM_CHIP_MODE      0xA007\n+\n+#define YT8614_REG_COM_HIDE_SPEED     0xA009\n+\n+#define YT8614_REG_COM_SYNCE1_CFG     0xA00E\n+\n+#define YT8614_REG_COM_HIDE_FIBER_MODE 0xA019\n+\n+\n+#define YT8614_REG_COM_HIDE_SEL1      0xA054\n+#define YT8614_REG_COM_HIDE_LED_CFG2  0xB8\n+#define YT8614_REG_COM_HIDE_LED_CFG3  0xB9\n+#define YT8614_REG_COM_HIDE_LED_CFG5  0xBB\n+\n+#define YT8614_REG_COM_HIDE_LED_CFG4  0xBA //not used currently\n+\n+#if 0\n+#define YT8614_REG_COM_HIDE_LED12_CFG 0xA060 //not used currently\n+#define YT8614_REG_COM_HIDE_LED13_CFG 0xA061\n+#define YT8614_REG_COM_HIDE_LED14_CFG 0xA062\n+#define YT8614_REG_COM_HIDE_LED15_CFG 0xA063\n+#define YT8614_REG_COM_HIDE_LED16_CFG 0xA064\n+#define YT8614_REG_COM_HIDE_LED17_CFG 0xA065\n+#define YT8614_REG_COM_HIDE_LED18_CFG 0xA066\n+#define YT8614_REG_COM_HIDE_LED19_CFG 0xA067\n+#define YT8614_REG_COM_HIDE_LED20_CFG 0xA068\n+#define YT8614_REG_COM_HIDE_LED21_CFG 0xA069\n+#define YT8614_REG_COM_HIDE_LED22_CFG 0xA06A\n+#define YT8614_REG_COM_HIDE_LED23_CFG 0xA06B\n+#define YT8614_REG_COM_HIDE_LED24_CFG 0xA06C\n+#define YT8614_REG_COM_HIDE_LED25_CFG 0xA06D\n+#define YT8614_REG_COM_HIDE_LED26_CFG 0xA06E\n+#define YT8614_REG_COM_HIDE_LED27_CFG 0xA06F\n+#endif\n+\n+#define YT8614_REG_COM_HIDE_LED28_CFG 0xA070\n+#define YT8614_REG_COM_HIDE_LED29_CFG 0xA071\n+#define YT8614_REG_COM_HIDE_LED30_CFG 0xA072\n+#define YT8614_REG_COM_HIDE_LED31_CFG 0xA073\n+#define YT8614_REG_COM_HIDE_LED32_CFG 0xA074\n+#define YT8614_REG_COM_HIDE_LED33_CFG 0xA075\n+#define YT8614_REG_COM_HIDE_LED34_CFG 0xA076\n+#define YT8614_REG_COM_HIDE_LED35_CFG 0xA077\n+\n+#define YT8614_REG_COM_PKG_CFG0       0xA0A0\n+#define YT8614_REG_COM_PKG_CFG1       0xA0A1\n+#define YT8614_REG_COM_PKG_CFG2       0xA0A2\n+#define YT8614_REG_COM_PKG_RX_VALID0  0xA0A3\n+#define YT8614_REG_COM_PKG_RX_VALID1  0xA0A4\n+#define YT8614_REG_COM_PKG_RX_OS0     0xA0A5\n+#define YT8614_REG_COM_PKG_RX_OS1     0xA0A6\n+#define YT8614_REG_COM_PKG_RX_US0     0xA0A7\n+#define YT8614_REG_COM_PKG_RX_US1     0xA0A8\n+#define YT8614_REG_COM_PKG_RX_ERR     0xA0A9\n+#define YT8614_REG_COM_PKG_RX_OS_BAD  0xA0AA\n+#define YT8614_REG_COM_PKG_RX_FRAG    0xA0AB\n+#define YT8614_REG_COM_PKG_RX_NOSFD   0xA0AC\n+#define YT8614_REG_COM_PKG_TX_VALID0  0xA0AD\n+#define YT8614_REG_COM_PKG_TX_VALID1  0xA0AE\n+#define YT8614_REG_COM_PKG_TX_OS0     0xA0AF\n+\n+#define YT8614_REG_COM_PKG_TX_OS1     0xA0B0\n+#define YT8614_REG_COM_PKG_TX_US0     0xA0B1\n+#define YT8614_REG_COM_PKG_TX_US1     0xA0B2\n+#define YT8614_REG_COM_PKG_TX_ERR     0xA0B3\n+#define YT8614_REG_COM_PKG_TX_OS_BAD  0xA0B4\n+#define YT8614_REG_COM_PKG_TX_FRAG    0xA0B5\n+#define YT8614_REG_COM_PKG_TX_NOSFD   0xA0B6\n+#define YT8614_REG_COM_PKG_CFG3       0xA0B7\n+#define YT8614_REG_COM_PKG_AZ_CFG     0xA0B8\n+#define YT8614_REG_COM_PKG_DA_SA_CFG3 0xA0B9\n+\n+#define YT8614_REG_COM_MANU_HW_RESET  0xA0C0\n+\n+/* YT8614 UTP MII register: same as generic phy register definitions */\n+#define REG_MII_BMCR          0x00    /* Basic mode control register */\n+#define REG_MII_BMSR          0x01    /* Basic mode status register  */\n+#define REG_MII_PHYSID1       0x02    /* PHYS ID 1                   */\n+#define REG_MII_PHYSID2       0x03    /* PHYS ID 2                   */\n+#define REG_MII_ADVERTISE     0x04    /* Advertisement control reg   */\n+#define REG_MII_LPA           0x05    /* Link partner ability reg    */\n+#define REG_MII_EXPANSION     0x06    /* Expansion register          */\n+#define REG_MII_NEXT_PAGE     0x07    /* Next page register          */\n+#define REG_MII_LPR_NEXT_PAGE 0x08    /* LPR next page register      */\n+#define REG_MII_CTRL1000      0x09    /* 1000BASE-T control          */\n+#define REG_MII_STAT1000      0x0A    /* 1000BASE-T status           */\n+\n+#define REG_MII_MMD_CTRL      0x0D    /* MMD access control register */\n+#define REG_MII_MMD_DATA      0x0E    /* MMD access data register    */\n+\n+#define REG_MII_ESTATUS       0x0F    /* Extended Status             */\n+#define REG_MII_SPEC_CTRL     0x10    /* PHY specific func control   */\n+#define REG_MII_SPEC_STATUS   0x11    /* PHY specific status         */\n+#define REG_MII_INT_MASK      0x12    /* Interrupt mask register     */\n+#define REG_MII_INT_STATUS    0x13    /* Interrupt status register   */\n+#define REG_MII_DOWNG_CTRL    0x14    /* Speed auto downgrade control*/\n+#define REG_MII_RERRCOUNTER   0x15    /* Receive error counter       */\n+\n+#define REG_MII_EXT_ADDR      0x1E    /* Extended reg's address      */\n+#define REG_MII_EXT_DATA      0x1F    /* Extended reg's date         */\n+\n+#ifndef MII_BMSR\n+#define MII_BMSR\t\t\t\t\t\tREG_MII_BMSR\n+#endif\n+\n+#ifndef YT8614_SPEED_MODE_BIT\n+#define YT8614_SPEED_MODE\t\t0xc000\n+#define YT8614_DUPLEX\t\t\t0x2000\n+#define YT8614_SPEED_MODE_BIT\t\t14\n+#define YT8614_DUPLEX_BIT\t\t13\n+#define YT8614_LINK_STATUS_BIT\t\t10\n+\n+#endif\n+\n+#define YT8614_REG_COM_HIDE_SPEED_CMB_PRI\t\t0x2000\n+\n+/* YT8614 UTP MMD register  */\n+#define YT8614_REG_UTP_MMD_CTRL1           0x00    /* PCS control 1 register     */\n+#define YT8614_REG_UTP_MMD_STATUS1         0x01    /* PCS status 1 register      */\n+#define YT8614_REG_UTP_MMD_EEE_CTRL        0x14    /* EEE control and capability */\n+#define YT8614_REG_UTP_MMD_EEE_WK_ERR_CNT  0x16    /* EEE wake error counter     */\n+#define YT8614_REG_UTP_MMD_EEE_LOCAL_ABI   0x3C    /* local device EEE ability   */\n+#define YT8614_REG_UTP_MMD_EEE_LP_ABI      0x3D    /* link partner EEE ability   */\n+#define YT8614_REG_UTP_MMD_EEE_AUTONEG_RES 0x8000  /* autoneg result of EEE      */\n+\n+/* YT8614 UTP EXT register  */\n+#define YT8614_REG_UTP_EXT_LPBK        0x0A\n+#define YT8614_REG_UTP_EXT_SLEEP_CTRL1 0x27\n+#define YT8614_REG_UTP_EXT_DEBUG_MON1  0x5A\n+#define YT8614_REG_UTP_EXT_DEBUG_MON2  0x5B\n+#define YT8614_REG_UTP_EXT_DEBUG_MON3  0x5C\n+#define YT8614_REG_UTP_EXT_DEBUG_MON4  0x5D\n+\n+/* YT8614 SDS(1.25G/5G) MII register: same as YT8521S */\n+#define REG_SDS_BMCR          0x00    /* Basic mode control register */\n+#define REG_SDS_BMSR          0x01    /* Basic mode status register  */\n+#define REG_SDS_PHYSID1       0x02    /* PHYS ID 1                   */\n+#define REG_SDS_PHYSID2       0x03    /* PHYS ID 2                   */\n+#define REG_SDS_ADVERTISE     0x04    /* Advertisement control reg   */\n+#define REG_SDS_LPA           0x05    /* Link partner ability reg    */\n+#define REG_SDS_EXPANSION     0x06    /* Expansion register          */\n+#define REG_SDS_NEXT_PAGE     0x07    /* Next page register          */\n+#define REG_SDS_LPR_NEXT_PAGE 0x08    /* LPR next page register      */\n+\n+#define REG_SDS_ESTATUS       0x0F    /* Extended Status             */\n+#define REG_SDS_SPEC_STATUS   0x11    /* SDS specific status         */\n+\n+#define REG_SDS_100FX_CFG     0x14    /* 100fx cfg                   */\n+#define REG_SDS_RERRCOUNTER   0x15    /* Receive error counter       */\n+#define REG_SDS_LINT_FAIL_CNT 0x16    /* Lint fail counter mon       */\n+\n+/* YT8614 SDS(5G) EXT register */\n+#define YT8614_REG_QSGMII_EXT_ANA_DIG_CFG 0x02    /* sds analog digital interface cfg */\n+#define YT8614_REG_QSGMII_EXT_PRBS_CFG1   0x05    /* sds prbs cfg1 */\n+#define YT8614_REG_QSGMII_EXT_PRBS_CFG2_1 0x06    /* sds prbs cfg2 */\n+#define YT8614_REG_QSGMII_EXT_PRBS_CFG2_2 0x07    /* sds prbs cfg2 */\n+#define YT8614_REG_QSGMII_EXT_PRBS_MON1   0x08    /* sds prbs mon1 */\n+#define YT8614_REG_QSGMII_EXT_PRBS_MON2   0x09    /* sds prbs mon2 */\n+#define YT8614_REG_QSGMII_EXT_PRBS_MON3   0x0A    /* sds prbs mon3 */\n+#define YT8614_REG_QSGMII_EXT_PRBS_MON4   0x0B    /* sds prbs mon4 */\n+#define YT8614_REG_QSGMII_EXT_PRBS_MON5   0x0C    /* sds prbs mon5 */\n+#define YT8614_REG_QSGMII_EXT_ANA_CFG2    0xA1    /* Analog cfg2   */\n+\n+/* YT8614 SDS(1.25G) EXT register */\n+#define YT8614_REG_SGMII_EXT_PRBS_CFG1    0x05    /* sds prbs cfg1 */\n+#define YT8614_REG_SGMII_EXT_PRBS_CFG2    0x06    /* sds prbs cfg2 */\n+#define YT8614_REG_SGMII_EXT_PRBS_MON1    0x08    /* sds prbs mon1 */\n+#define YT8614_REG_SGMII_EXT_PRBS_MON2    0x09    /* sds prbs mon2 */\n+#define YT8614_REG_SGMII_EXT_PRBS_MON3    0x0A    /* sds prbs mon3 */\n+#define YT8614_REG_SGMII_EXT_PRBS_MON4    0x0B    /* sds prbs mon4 */\n+#define YT8614_REG_SGMII_EXT_PRBS_MON5    0x0C    /* sds prbs mon5 */\n+#define YT8614_REG_SGMII_EXT_ANA_CFG2     0xA1    /* Analog cfg2   */\n+#define YT8614_REG_SGMII_EXT_HIDE_AUTO_SEN 0xA5   /* Fiber auto sensing */\n+\n+////////////////////////////////////////////////////////////////////\n+#define YT8614_MMD_DEV_ADDR1     0x1\n+#define YT8614_MMD_DEV_ADDR3     0x3\n+#define YT8614_MMD_DEV_ADDR7     0x7\n+#define YT8614_MMD_DEV_ADDR_NONE 0xFF\n+\n+/**********YT8521S************************************************/\n+/* Basic mode control register(0x00) */\n+#define BMCR_RESV         0x003f  /* Unused...                   */\n+#define BMCR_SPEED1000    0x0040  /* MSB of Speed (1000)         */\n+#define BMCR_CTST         0x0080  /* Collision test              */\n+#define BMCR_FULLDPLX     0x0100  /* Full duplex                 */\n+#define BMCR_ANRESTART    0x0200  /* Auto negotiation restart    */\n+#define BMCR_ISOLATE      0x0400  /* Disconnect DP83840 from MII */\n+#define BMCR_PDOWN        0x0800  /* Powerdown the DP83840       */\n+#define BMCR_ANENABLE     0x1000  /* Enable auto negotiation     */\n+#define BMCR_SPEED100     0x2000  /* Select 100Mbps              */\n+#define BMCR_LOOPBACK     0x4000  /* TXD loopback bits           */\n+#define BMCR_RESET        0x8000  /* Reset the DP83840           */\n+\n+/* Basic mode status register(0x01) */\n+#define BMSR_ERCAP        0x0001  /* Ext-reg capability          */\n+#define BMSR_JCD          0x0002  /* Jabber detected             */\n+#define BMSR_LSTATUS      0x0004  /* Link status                 */\n+#define BMSR_ANEGCAPABLE  0x0008  /* Able to do auto-negotiation */\n+#define BMSR_RFAULT       0x0010  /* Remote fault detected       */\n+#define BMSR_ANEGCOMPLETE 0x0020  /* Auto-negotiation complete   */\n+#define BMSR_RESV         0x00c0  /* Unused...                   */\n+#define BMSR_ESTATEN      0x0100  /* Extended Status in R15      */\n+#define BMSR_100HALF2     0x0200  /* Can do 100BASE-T2 HDX       */\n+#define BMSR_100FULL2     0x0400  /* Can do 100BASE-T2 FDX       */\n+#define BMSR_10HALF       0x0800  /* Can do 10mbps, half-duplex  */\n+#define BMSR_10FULL       0x1000  /* Can do 10mbps, full-duplex  */\n+#define BMSR_100HALF      0x2000  /* Can do 100mbps, half-duplex */\n+#define BMSR_100FULL      0x4000  /* Can do 100mbps, full-duplex */\n+#define BMSR_100BASE4     0x8000  /* Can do 100mbps, 4k packets  */\n+\n+/* Advertisement control register(0x04) */\n+#define ADVERTISE_SLCT          0x001f  /* Selector bits               */\n+#define ADVERTISE_CSMA          0x0001  /* Only selector supported     */\n+#define ADVERTISE_10HALF        0x0020  /* Try for 10mbps half-duplex  */\n+#define ADVERTISE_1000XFULL     0x0020  /* Try for 1000BASE-X full-duplex */\n+#define ADVERTISE_10FULL        0x0040  /* Try for 10mbps full-duplex  */\n+#define ADVERTISE_1000XHALF     0x0040  /* Try for 1000BASE-X half-duplex */\n+#define ADVERTISE_100HALF       0x0080  /* Try for 100mbps half-duplex */\n+#define ADVERTISE_1000XPAUSE    0x0080  /* Try for 1000BASE-X pause    */\n+#define ADVERTISE_100FULL       0x0100  /* Try for 100mbps full-duplex */\n+#define ADVERTISE_1000XPSE_ASYM 0x0100  /* Try for 1000BASE-X asym pause */\n+#define ADVERTISE_100BASE4      0x0200  /* Try for 100mbps 4k packets  */\n+#define ADVERTISE_PAUSE_CAP     0x0400  /* Try for pause               */\n+#define ADVERTISE_PAUSE_ASYM    0x0800  /* Try for asymetric pause     */\n+#define ADVERTISE_RESV          0x1000  /* Unused...                   */\n+#define ADVERTISE_RFAULT        0x2000  /* Say we can detect faults    */\n+#define ADVERTISE_LPACK         0x4000  /* Ack link partners response  */\n+#define ADVERTISE_NPAGE         0x8000  /* Next page bit               */\n+\n+#define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | ADVERTISE_CSMA)\n+#define ADVERTISE_ALL  (ADVERTISE_10HALF  | ADVERTISE_10FULL | \\\n+                        ADVERTISE_100HALF | ADVERTISE_100FULL)\n+\n+/* Link partner ability register(0x05) */\n+#define LPA_SLCT              0x001f  /* Same as advertise selector    */\n+#define LPA_10HALF            0x0020  /* Can do 10mbps half-duplex     */\n+#define LPA_1000XFULL         0x0020  /* Can do 1000BASE-X full-duplex */\n+#define LPA_10FULL            0x0040  /* Can do 10mbps full-duplex     */\n+#define LPA_1000XHALF         0x0040  /* Can do 1000BASE-X half-duplex */\n+#define LPA_100HALF           0x0080  /* Can do 100mbps half-duplex    */\n+#define LPA_1000XPAUSE        0x0080  /* Can do 1000BASE-X pause       */\n+#define LPA_100FULL           0x0100  /* Can do 100mbps full-duplex    */\n+#define LPA_1000XPAUSE_ASYM   0x0100  /* Can do 1000BASE-X pause asym  */\n+#define LPA_100BASE4          0x0200  /* Can do 100mbps 4k packets     */\n+#define LPA_PAUSE_CAP         0x0400  /* Can pause                     */\n+#define LPA_PAUSE_ASYM        0x0800  /* Can pause asymetrically       */\n+#define LPA_RESV              0x1000  /* Unused...                     */\n+#define LPA_RFAULT            0x2000  /* Link partner faulted          */\n+#define LPA_LPACK             0x4000  /* Link partner acked us         */\n+#define LPA_NPAGE             0x8000  /* Next page bit                 */\n+\n+/* 1000BASE-T Control register(0x09) */\n+#define ADVERTISE_1000FULL    0x0200  /* Advertise 1000BASE-T full duplex */\n+#define ADVERTISE_1000HALF    0x0100  /* Advertise 1000BASE-T half duplex */\n+#define CTL1000_AS_MASTER     0x0800\n+#define CTL1000_ENABLE_MASTER 0x1000\n+\n+/* 1000BASE-T Status register(0x0A) */\n+#define LPA_1000LOCALRXOK     0x2000  /* Link partner local receiver status  */\n+#define LPA_1000REMRXOK       0x1000  /* Link partner remote receiver status */\n+#define LPA_1000FULL          0x0800  /* Link partner 1000BASE-T full duplex */\n+#define LPA_1000HALF          0x0400  /* Link partner 1000BASE-T half duplex */\n+\n+/**********YT8614************************************************/\n+/* Basic mode control register(0x00) */\n+#define FIBER_BMCR_RESV        0x001f  /* b[4:0] Unused...                      */\n+#define FIBER_BMCR_EN_UNIDIR   0x0020  /* b[5]   Valid when bit 0.12 is zero and bit 0.8 is one */\n+#define FIBER_BMCR_SPEED1000   0x0040  /* b[6]   MSB of Speed (1000)            */\n+#define FIBER_BMCR_CTST        0x0080  /* b[7]   Collision test                 */\n+#define FIBER_BMCR_DUPLEX_MODE 0x0100  /* b[8]   Duplex mode                    */\n+#define FIBER_BMCR_ANRESTART   0x0200  /* b[9]   Auto negotiation restart       */\n+#define FIBER_BMCR_ISOLATE     0x0400  /* b[10]  Isolate phy from RGMII/SGMII/FIBER */\n+#define FIBER_BMCR_PDOWN       0x0800  /* b[11]  1: Power down                  */\n+#define FIBER_BMCR_ANENABLE    0x1000  /* b[12]  Enable auto negotiation        */\n+#define FIBER_BMCR_SPEED100    0x2000  /* b[13]  LSB of Speed (100)             */\n+#define FIBER_BMCR_LOOPBACK    0x4000  /* b[14]  Internal loopback control      */\n+#define FIBER_BMCR_RESET       0x8000  /* b[15]  PHY Software Reset(self-clear) */\n+\n+/* Sds specific status register(0x11) */\n+#define FIBER_SSR_ERCAP          0x0001  /* b[0]     realtime syncstatus */\n+#define FIBER_SSR_XMIT           0x000E  /* b[3:1]   realtime transmit statemachine.\n+                                                     001: Xmit Idle;\n+                                                     010: Xmit Config; \n+                                                     100: Xmit Data. */\n+#define FIBER_SSR_SER_MODE_CFG   0x0030  /* b[5:4]   realtime serdes working mode.\n+                                                     00: SG_MAC;\n+                                                     01: SG_PHY;\n+                                                     10: FIB_1000;\n+                                                     11: FIB_100. */\n+#define FIBER_SSR_EN_FLOWCTRL_TX 0x0040  /* b[6]     realtime en_flowctrl_tx */\n+#define FIBER_SSR_EN_FLOWCTRL_RX 0x0080  /* b[7]     realtime en_flowctrl_rx */\n+#define FIBER_SSR_DUPLEX_ERROR   0x0100  /* b[8]     realtime deplex error */\n+#define FIBER_SSR_RX_LPI_ACTIVE  0x0200  /* b[9]     rx lpi is active */\n+#define FIBER_SSR_LSTATUS        0x0400  /* b[10]    Link status real-time */\n+#define FIBER_SSR_PAUSE          0x1800  /* b[12:11] Pause to mac */\n+#define FIBER_SSR_DUPLEX         0x2000  /* b[13]    This status bit is valid only when bit10 is 1.\n+                                                     1: full duplex \n+                                                     0: half duplex */\n+#define FIBER_SSR_SPEED_MODE     0xC000  /* b[15:14] These status bits are valid only when bit10 is 1.\n+                                                     10---1000M \n+                                                     01---100M */\n+\n+/* SLED cfg0 (ext 0xA001) */\n+#define FIBER_SLED_CFG0_EN_CTRL  0x00FF  /* b[7:0]   Control to enable the eight ports' SLED */\n+#define FIBER_SLED_CFG0_BIT_MASK 0x0700  /* b[10:8]  1: enable the pin output */\n+#define FIBER_SLED_CFG0_ACT_LOW  0x0800  /* b[11]    control SLED's polarity. 1: active low; 0: active high */\n+#define FIBER_SLED_CFG0_MANU_ST  0x7000  /* b[14:12] SLEDs' manul status, corresponding to each port's 3 SLEDs */\n+#define FIBER_SLED_CFG0_MANU_EN  0x8000  /* b[15]    to control serial LEDs status manually */\n+\n+/**********YT8614************************************************/\n+/* Fiber auto sensing(sgmii ext 0xA5) */\n+#define FIBER_AUTO_SEN_ENABLE    0x8000  /* b[15]  Enable fiber auto sensing */\n+\n+/* Fiber force speed(common ext 0xA009) */\n+#define FIBER_FORCE_1000M        0x0001  /* b[0]  1:1000BX 0:100FX */\n+\n+#ifndef NULL\n+#define NULL 0\n+#endif\n+\n+/* errno */\n+enum ytphy_8614_errno_e\n+{\n+\tSYS_E_NONE,\n+\tSYS_E_PARAM,\n+\tSYS_E_MAX\n+};\n+\n+/* errno */\n+enum ytphy_8614_combo_speed_e\n+{\n+\tYT8614_COMBO_FIBER_1000M,\n+\tYT8614_COMBO_FIBER_100M,\n+\tYT8614_COMBO_UTP_ONLY,\n+\tYT8614_COMBO_SPEED_MAX\n+};\n+\n+/* definition for porting */\n+/* phy registers access */\n+typedef struct\n+{\n+    u16 reg;     /* the offset of the phy internal address */\n+    u16 val;     /* the value of the register */\n+    u8  regType; /* register type */\n+} phy_data_s;\n+\n+/* for porting use.\n+ * pls over-write member function read/write for mdio access\n+ */\n+typedef struct phy_info_str\n+{\n+#if 0\n+    struct phy_device *phydev;\n+\tint mdio_base;\n+#endif\n+\tunsigned int lport;\n+\tunsigned int bus_id;\n+\tunsigned int phy_addr;\n+\n+    s32 (*read)(struct phy_info_str *info, phy_data_s *param);\n+    s32 (*write)(struct phy_info_str *info, phy_data_s *param);\n+}phy_info_s;\n+\n+/* get phy access method */\n+s32 yt8614_read_reg(struct phy_info_str *info, phy_data_s *param);\n+s32 yt8614_write_reg(struct phy_info_str *info, phy_data_s *param);\n+s32 yt8614_phy_soft_reset(u32 lport);\n+s32 yt8614_phy_init(u32 lport);\n+s32 yt8614_fiber_enable(u32 lport, BOOL enable);\n+s32 yt8614_utp_enable(u32 lport, BOOL enable);\n+s32 yt8614_fiber_unidirection_set(u32 lport, int speed, BOOL enable);\n+s32 yt8614_fiber_autosensing_set(u32 lport, BOOL enable);\n+s32 yt8614_fiber_speed_set(u32 lport, int fiber_speed);\n+s32 yt8614_qsgmii_autoneg_set(u32 lport, BOOL enable);\n+s32 yt8614_sgmii_autoneg_set(u32 lport, BOOL enable);\n+s32 yt8614_qsgmii_sgmii_link_status_get(u32 lport, BOOL *enable, BOOL if_qsgmii);\n+int yt8614_combo_media_priority_set (u32 lport, int fiber);\n+int yt8614_combo_media_priority_get (u32 lport, int *fiber);\n+s32 yt8614_utp_autoneg_set(u32 lport, BOOL enable);\n+s32 yt8614_utp_autoneg_get(u32 lport, BOOL *enable);\n+s32 yt8614_utp_autoneg_ability_set(u32 lport, unsigned int cap_mask);\n+s32 yt8614_utp_autoneg_ability_get(u32 lport, unsigned int *cap_mask);\n+s32 yt8614_utp_force_duplex_set(u32 lport, BOOL full);\n+s32 yt8614_utp_force_duplex_get(u32 lport, BOOL *full);\n+s32 yt8614_utp_force_speed_set(u32 lport, unsigned int speed);\n+s32 yt8614_utp_force_speed_get(u32 lport, unsigned int *speed);\n+int yt8614_autoneg_done_get (u32 lport, int speed, int *aneg);\n+int yt8614_media_status_get(u32 lport, int* speed, int* duplex, int* ret_link, int *media);\n+\n+#endif\ndiff --git a/include/linux/motorcomm_phy.h b/include/linux/motorcomm_phy.h\nnew file mode 100644\nindex 000000000..9e01fc205\n--- /dev/null\n+++ b/include/linux/motorcomm_phy.h\n@@ -0,0 +1,119 @@\n+/*\n+ * include/linux/motorcomm_phy.h\n+ *\n+ * Motorcomm PHY IDs\n+ *\n+ * This program is free software; you can redistribute  it and/or modify it\n+ * under  the terms of  the GNU General  Public License as published by the\n+ * Free Software Foundation;  either version 2 of the  License, or (at your\n+ * option) any later version.\n+ *\n+ */\n+\n+#ifndef _MOTORCOMM_PHY_H\n+#define _MOTORCOMM_PHY_H\n+\n+#define MOTORCOMM_PHY_ID_MASK\t0x00000fff\n+#define MOTORCOMM_PHY_ID_8531_MASK\t0xffffffff\n+#define MOTORCOMM_MPHY_ID_MASK\t0x0000ffff\n+\n+#define PHY_ID_YT8010\t\t0x00000309\n+#define PHY_ID_YT8510\t\t0x00000109\n+#define PHY_ID_YT8511\t\t0x0000010a\n+#define PHY_ID_YT8512\t\t0x00000118\n+#define PHY_ID_YT8512B\t\t0x00000128\n+#define PHY_ID_YT8521\t\t0x0000011a\n+#define PHY_ID_YT8531S\t\t0x4f51e91a\n+#define PHY_ID_YT8531\t\t0x4f51e91b\n+//#define PHY_ID_YT8614\t\t0x0000e899\n+#define PHY_ID_YT8618\t\t0x0000e889\n+\n+#define REG_PHY_SPEC_STATUS\t\t0x11\n+#define REG_DEBUG_ADDR_OFFSET\t\t0x1e\n+#define REG_DEBUG_DATA\t\t\t0x1f\n+\n+#define YT8512_EXTREG_AFE_PLL\t\t0x50\n+#define YT8512_EXTREG_EXTEND_COMBO\t0x4000\n+#define YT8512_EXTREG_LED0\t\t0x40c0\n+#define YT8512_EXTREG_LED1\t\t0x40c3\n+\n+#define YT8512_EXTREG_SLEEP_CONTROL1\t0x2027\n+\n+#define YT_SOFTWARE_RESET\t\t0x8000\n+\n+#define YT8512_CONFIG_PLL_REFCLK_SEL_EN\t0x0040\n+#define YT8512_CONTROL1_RMII_EN\t\t0x0001\n+#define YT8512_LED0_ACT_BLK_IND\t\t0x1000\n+#define YT8512_LED0_DIS_LED_AN_TRY\t0x0001\n+#define YT8512_LED0_BT_BLK_EN\t\t0x0002\n+#define YT8512_LED0_HT_BLK_EN\t\t0x0004\n+#define YT8512_LED0_COL_BLK_EN\t\t0x0008\n+#define YT8512_LED0_BT_ON_EN\t\t0x0010\n+#define YT8512_LED1_BT_ON_EN\t\t0x0010\n+#define YT8512_LED1_TXACT_BLK_EN\t0x0100\n+#define YT8512_LED1_RXACT_BLK_EN\t0x0200\n+#define YT8512_SPEED_MODE\t\t0xc000\n+#define YT8512_DUPLEX\t\t\t0x2000\n+\n+#define YT8512_SPEED_MODE_BIT\t\t14\n+#define YT8512_DUPLEX_BIT\t\t13\n+#define YT8512_EN_SLEEP_SW_BIT\t\t15\n+\n+#define YT8521_EXTREG_SLEEP_CONTROL1\t0x27\n+#define YT8521_EN_SLEEP_SW_BIT\t\t15\n+\n+#define YT8521_SPEED_MODE\t\t0xc000\n+#define YT8521_DUPLEX\t\t\t0x2000\n+#define YT8521_SPEED_MODE_BIT\t\t14\n+#define YT8521_DUPLEX_BIT\t\t13\n+#define YT8521_LINK_STATUS_BIT\t\t10\n+\n+/* based on yt8521 wol config register */\n+#define YTPHY_UTP_INTR_REG             0x12\n+/* WOL Event Interrupt Enable */\n+#define YTPHY_WOL_INTR            BIT(6)\n+\n+/* Magic Packet MAC address registers */\n+#define YTPHY_MAGIC_PACKET_MAC_ADDR2                 0xa007\n+#define YTPHY_MAGIC_PACKET_MAC_ADDR1                 0xa008\n+#define YTPHY_MAGIC_PACKET_MAC_ADDR0                 0xa009\n+\n+#define YTPHY_WOL_CFG_REG\t\t0xa00a\n+#define YTPHY_WOL_CFG_TYPE\t\tBIT(0)\t/* WOL TYPE */\n+#define YTPHY_WOL_CFG_EN\t\tBIT(3)\t/* WOL Enable */\n+#define YTPHY_WOL_CFG_INTR_SEL\tBIT(6)\t/* WOL Event Interrupt Enable */\n+#define YTPHY_WOL_CFG_WIDTH1\tBIT(1)\t/* WOL Pulse Width */\n+#define YTPHY_WOL_CFG_WIDTH2\tBIT(2)\n+\n+#define YTPHY_REG_SPACE_UTP             0\n+#define YTPHY_REG_SPACE_FIBER           2\n+\n+enum ytphy_wol_type_e\n+{\n+    YTPHY_WOL_TYPE_LEVEL,\n+    YTPHY_WOL_TYPE_PULSE,\n+    YTPHY_WOL_TYPE_MAX\n+};\n+typedef enum ytphy_wol_type_e ytphy_wol_type_t;\n+\n+enum ytphy_wol_width_e\n+{\n+    YTPHY_WOL_WIDTH_84MS,\n+    YTPHY_WOL_WIDTH_168MS,\n+    YTPHY_WOL_WIDTH_336MS,\n+    YTPHY_WOL_WIDTH_672MS,\n+    YTPHY_WOL_WIDTH_MAX\n+};\n+typedef enum ytphy_wol_width_e ytphy_wol_width_t;\n+\n+struct ytphy_wol_cfg_s\n+{\n+    int enable;\n+    int type;\n+    int width;\n+};\n+typedef struct ytphy_wol_cfg_s ytphy_wol_cfg_t;\n+\n+#endif /* _MOTORCOMM_PHY_H */\n+\n+\n-- \n2.25.1\n\n"
  },
  {
    "path": "target/linux/rockchip/patches-5.10/801-char-add-support-for-rockchip-hardware-random-number.patch",
    "content": "From e5b5361651940ff5c0c1784dfd0130abec7ab535 Mon Sep 17 00:00:00 2001\nFrom: wevsty <ty@wevs.org>\nDate: Mon, 24 Aug 2020 02:27:11 +0800\nSubject: [PATCH] char: add support for rockchip hardware random number\n generator\n\nThis patch provides hardware random number generator support for all rockchip SOC.\n\nrockchip-rng.c from  https://github.com/rockchip-linux/kernel/blob/develop-4.4/drivers/char/hw_random/rockchip-rng.c\n\nSigned-off-by: wevsty <ty@wevs.org>\n---\n\n--- a/drivers/char/hw_random/Kconfig\n+++ b/drivers/char/hw_random/Kconfig\n@@ -398,6 +398,19 @@ config HW_RANDOM_STM32\n \n \t  If unsure, say N.\n \n+config HW_RANDOM_ROCKCHIP\n+\ttristate \"Rockchip Random Number Generator support\"\n+\tdepends on ARCH_ROCKCHIP\n+\tdefault HW_RANDOM\n+\thelp\n+\t  This driver provides kernel-side support for the Random Number\n+\t  Generator hardware found on Rockchip cpus.\n+\n+\t  To compile this driver as a module, choose M here: the\n+\t  module will be called rockchip-rng.\n+\n+\t  If unsure, say Y.\n+\n config HW_RANDOM_PIC32\n \ttristate \"Microchip PIC32 Random Number Generator support\"\n \tdepends on HW_RANDOM && MACH_PIC32\n--- a/drivers/char/hw_random/Makefile\n+++ b/drivers/char/hw_random/Makefile\n@@ -36,6 +36,7 @@ obj-$(CONFIG_HW_RANDOM_IPROC_RNG200) +=\n obj-$(CONFIG_HW_RANDOM_ST) += st-rng.o\n obj-$(CONFIG_HW_RANDOM_XGENE) += xgene-rng.o\n obj-$(CONFIG_HW_RANDOM_STM32) += stm32-rng.o\n+obj-$(CONFIG_HW_RANDOM_ROCKCHIP) += rockchip-rng.o\n obj-$(CONFIG_HW_RANDOM_PIC32) += pic32-rng.o\n obj-$(CONFIG_HW_RANDOM_MESON) += meson-rng.o\n obj-$(CONFIG_HW_RANDOM_CAVIUM) += cavium-rng.o cavium-rng-vf.o\n"
  },
  {
    "path": "target/linux/rockchip/patches-5.10/802-arm64-dts-rockchip-add-hardware-random-number-genera.patch",
    "content": "From e5b5361651940ff5c0c1784dfd0130abec7ab535 Mon Sep 17 00:00:00 2001\nFrom: wevsty <ty@wevs.org>\nDate: Mon, 24 Aug 2020 02:27:11 +0800\nSubject: [PATCH] arm64: dts: rockchip: add hardware random number generator\n for RK3328 and RK3399\n\nAdding Hardware Random Number Generator Resources to the RK3328 and RK3399.\n\nSigned-off-by: wevsty <ty@wevs.org>\n---\n\n--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi\n+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi\n@@ -297,6 +297,17 @@\n \t\tstatus = \"disabled\";\n \t};\n \n+\trng: rng@ff060000 {\n+\t\tcompatible = \"rockchip,cryptov1-rng\";\n+\t\treg = <0x0 0xff060000 0x0 0x4000>;\n+\n+\t\tclocks = <&cru SCLK_CRYPTO>, <&cru HCLK_CRYPTO_SLV>;\n+\t\tclock-names = \"clk_crypto\", \"hclk_crypto\";\n+\t\tassigned-clocks = <&cru SCLK_CRYPTO>, <&cru HCLK_CRYPTO_SLV>;\n+\t\tassigned-clock-rates = <150000000>, <100000000>;\n+\t\tstatus = \"disabled\";\n+\t};\n+\n \tgrf: syscon@ff100000 {\n \t\tcompatible = \"rockchip,rk3328-grf\", \"syscon\", \"simple-mfd\";\n \t\treg = <0x0 0xff100000 0x0 0x1000>;\n--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi\n+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi\n@@ -1905,6 +1905,16 @@\n \t\t};\n \t};\n \n+\trng: rng@ff8b8000 {\n+\t\tcompatible = \"rockchip,cryptov1-rng\";\n+\t\treg = <0x0 0xff8b8000 0x0 0x1000>;\n+\t\tclocks = <&cru SCLK_CRYPTO1>, <&cru HCLK_S_CRYPTO1>;\n+\t\tclock-names = \"clk_crypto\", \"hclk_crypto\";\n+\t\tassigned-clocks = <&cru SCLK_CRYPTO1>, <&cru HCLK_S_CRYPTO1>;\n+\t\tassigned-clock-rates = <150000000>, <100000000>;\n+\t\tstatus = \"okay\";\n+\t};\n+\n \tgpu: gpu@ff9a0000 {\n \t\tcompatible = \"rockchip,rk3399-mali\", \"arm,mali-t860\";\n \t\treg = <0x0 0xff9a0000 0x0 0x10000>;\n"
  },
  {
    "path": "target/linux/rockchip/patches-5.10/803-PM-devfreq-rockchip-add-devfreq-driver-for-rk3328-dmc.patch",
    "content": "From fcd9629c05f373771e85920e1c1d0ab252617878 Mon Sep 17 00:00:00 2001\nFrom: hmz007 <hmz007@gmail.com>\nDate: Tue, 19 Nov 2019 13:53:25 +0800\nSubject: [PATCH] PM / devfreq: rockchip: add devfreq driver for rk3328 dmc\n\nSigned-off-by: hmz007 <hmz007@gmail.com>\n---\n drivers/devfreq/Kconfig      |  18 +-\n drivers/devfreq/Makefile     |   1 +\n drivers/devfreq/rk3328_dmc.c | 846 +++++++++++++++++++++++++++++++++++\n 3 files changed, 862 insertions(+), 3 deletions(-)\n create mode 100644 drivers/devfreq/rk3328_dmc.c\n\n--- a/drivers/devfreq/Kconfig\n+++ b/drivers/devfreq/Kconfig\n@@ -131,6 +131,18 @@ config ARM_TEGRA20_DEVFREQ\n \t  It reads Memory Controller counters and adjusts the operating\n \t  frequencies and voltages with OPP support.\n \n+config ARM_RK3328_DMC_DEVFREQ\n+\ttristate \"ARM RK3328 DMC DEVFREQ Driver\"\n+\tdepends on ARCH_ROCKCHIP\n+\tselect DEVFREQ_EVENT_ROCKCHIP_DFI\n+\tselect DEVFREQ_GOV_SIMPLE_ONDEMAND\n+\tselect PM_DEVFREQ_EVENT\n+\tselect PM_OPP\n+\thelp\n+\t  This adds the DEVFREQ driver for the RK3328 DMC(Dynamic Memory Controller).\n+\t  It sets the frequency for the memory controller and reads the usage counts\n+\t  from hardware.\n+\n config ARM_RK3399_DMC_DEVFREQ\n \ttristate \"ARM RK3399 DMC DEVFREQ Driver\"\n \tdepends on (ARCH_ROCKCHIP && HAVE_ARM_SMCCC) || \\\n--- a/drivers/devfreq/Makefile\n+++ b/drivers/devfreq/Makefile\n@@ -12,6 +12,7 @@ obj-$(CONFIG_ARM_EXYNOS_BUS_DEVFREQ)\t+=\n obj-$(CONFIG_ARM_IMX_BUS_DEVFREQ)\t+= imx-bus.o\n obj-$(CONFIG_ARM_IMX8M_DDRC_DEVFREQ)\t+= imx8m-ddrc.o\n obj-$(CONFIG_ARM_RK3399_DMC_DEVFREQ)\t+= rk3399_dmc.o\n+obj-$(CONFIG_ARM_RK3328_DMC_DEVFREQ)\t+= rk3328_dmc.o\n obj-$(CONFIG_ARM_TEGRA_DEVFREQ)\t\t+= tegra30-devfreq.o\n obj-$(CONFIG_ARM_TEGRA20_DEVFREQ)\t+= tegra20-devfreq.o\n \n"
  },
  {
    "path": "target/linux/rockchip/patches-5.10/804-clk-rockchip-support-setting-ddr-clock-via-SIP-Version-2-.patch",
    "content": "From ce6d3614888e6358466f0e84e248177a6bca5258 Mon Sep 17 00:00:00 2001\nFrom: Tang Yun ping <typ@rock-chips.com>\nDate: Thu, 4 May 2017 20:49:58 +0800\nSubject: [PATCH] clk: rockchip: support setting ddr clock via SIP Version 2\n APIs\n\ncommit 764e893ee82321938fc6f4349e9e7caf06a04410 rockchip.\n\nSigned-off-by: Tang Yun ping <typ@rock-chips.com>\nSigned-off-by: hmz007 <hmz007@gmail.com>\n---\n drivers/clk/rockchip/clk-ddr.c      | 130 ++++++++++++++++++++++++++++\n drivers/clk/rockchip/clk-rk3328.c   |   7 +-\n drivers/clk/rockchip/clk.h          |   3 +-\n include/soc/rockchip/rockchip_sip.h |  11 +++\n 4 files changed, 147 insertions(+), 4 deletions(-)\n\n--- a/drivers/clk/rockchip/clk-ddr.c\n+++ b/drivers/clk/rockchip/clk-ddr.c\n@@ -87,6 +87,133 @@ static const struct clk_ops rockchip_ddr\n \t.get_parent = rockchip_ddrclk_get_parent,\n };\n \n+/* See v4.4/include/dt-bindings/display/rk_fb.h */\n+#define SCREEN_NULL\t\t\t0\n+#define SCREEN_HDMI\t\t\t6\n+\n+static inline int rk_drm_get_lcdc_type(void)\n+{\n+\treturn SCREEN_NULL;\n+}\n+\n+struct share_params {\n+\tu32 hz;\n+\tu32 lcdc_type;\n+\tu32 vop;\n+\tu32 vop_dclk_mode;\n+\tu32 sr_idle_en;\n+\tu32 addr_mcu_el3;\n+\t/*\n+\t * 1: need to wait flag1\n+\t * 0: never wait flag1\n+\t */\n+\tu32 wait_flag1;\n+\t/*\n+\t * 1: need to wait flag1\n+\t * 0: never wait flag1\n+\t */\n+\tu32 wait_flag0;\n+\tu32 complt_hwirq;\n+\t /* if need, add parameter after */\n+};\n+\n+struct rockchip_ddrclk_data {\n+\tu32 inited_flag;\n+\tvoid __iomem *share_memory;\n+};\n+\n+static struct rockchip_ddrclk_data ddr_data;\n+\n+static void rockchip_ddrclk_data_init(void)\n+{\n+\tstruct arm_smccc_res res;\n+\n+\tarm_smccc_smc(ROCKCHIP_SIP_SHARE_MEM,\n+\t\t      1, SHARE_PAGE_TYPE_DDR, 0,\n+\t\t      0, 0, 0, 0, &res);\n+\n+\tif (!res.a0) {\n+\t\tddr_data.share_memory = (void __iomem *)ioremap(res.a1, 1<<12);\n+\t\tddr_data.inited_flag = 1;\n+\t}\n+}\n+\n+static int rockchip_ddrclk_sip_set_rate_v2(struct clk_hw *hw,\n+\t\t\t\t\t   unsigned long drate,\n+\t\t\t\t\t   unsigned long prate)\n+{\n+\tstruct share_params *p;\n+\tstruct arm_smccc_res res;\n+\n+\tif (!ddr_data.inited_flag)\n+\t\trockchip_ddrclk_data_init();\n+\n+\tp = (struct share_params *)ddr_data.share_memory;\n+\n+\tp->hz = drate;\n+\tp->lcdc_type = rk_drm_get_lcdc_type();\n+\tp->wait_flag1 = 1;\n+\tp->wait_flag0 = 1;\n+\n+\tarm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ,\n+\t\t      SHARE_PAGE_TYPE_DDR, 0,\n+\t\t      ROCKCHIP_SIP_CONFIG_DRAM_SET_RATE,\n+\t\t      0, 0, 0, 0, &res);\n+\n+\tif ((int)res.a1 == -6) {\n+\t\tpr_err(\"%s: timeout, drate = %lumhz\\n\", __func__, drate/1000000);\n+\t\t/* TODO: rockchip_dmcfreq_wait_complete(); */\n+\t}\n+\n+\treturn res.a0;\n+}\n+\n+static unsigned long rockchip_ddrclk_sip_recalc_rate_v2\n+\t\t\t(struct clk_hw *hw, unsigned long parent_rate)\n+{\n+\tstruct arm_smccc_res res;\n+\n+\tarm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ,\n+\t\t      SHARE_PAGE_TYPE_DDR, 0,\n+\t\t      ROCKCHIP_SIP_CONFIG_DRAM_GET_RATE,\n+\t\t      0, 0, 0, 0, &res);\n+\tif (!res.a0)\n+\t\treturn res.a1;\n+\telse\n+\t\treturn 0;\n+}\n+\n+static long rockchip_ddrclk_sip_round_rate_v2(struct clk_hw *hw,\n+\t\t\t\t\t      unsigned long rate,\n+\t\t\t\t\t      unsigned long *prate)\n+{\n+\tstruct share_params *p;\n+\tstruct arm_smccc_res res;\n+\n+\tif (!ddr_data.inited_flag)\n+\t\trockchip_ddrclk_data_init();\n+\n+\tp = (struct share_params *)ddr_data.share_memory;\n+\n+\tp->hz = rate;\n+\n+\tarm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ,\n+\t\t      SHARE_PAGE_TYPE_DDR, 0,\n+\t\t      ROCKCHIP_SIP_CONFIG_DRAM_ROUND_RATE,\n+\t\t      0, 0, 0, 0, &res);\n+\tif (!res.a0)\n+\t\treturn res.a1;\n+\telse\n+\t\treturn 0;\n+}\n+\n+static const struct clk_ops rockchip_ddrclk_sip_ops_v2 = {\n+\t.recalc_rate = rockchip_ddrclk_sip_recalc_rate_v2,\n+\t.set_rate = rockchip_ddrclk_sip_set_rate_v2,\n+\t.round_rate = rockchip_ddrclk_sip_round_rate_v2,\n+\t.get_parent = rockchip_ddrclk_get_parent,\n+};\n+\n struct clk *rockchip_clk_register_ddrclk(const char *name, int flags,\n \t\t\t\t\t const char *const *parent_names,\n \t\t\t\t\t u8 num_parents, int mux_offset,\n@@ -114,6 +241,9 @@ struct clk *rockchip_clk_register_ddrclk\n \tcase ROCKCHIP_DDRCLK_SIP:\n \t\tinit.ops = &rockchip_ddrclk_sip_ops;\n \t\tbreak;\n+\tcase ROCKCHIP_DDRCLK_SIP_V2:\n+\t\tinit.ops = &rockchip_ddrclk_sip_ops_v2;\n+\t\tbreak;\n \tdefault:\n \t\tpr_err(\"%s: unsupported ddrclk type %d\\n\", __func__, ddr_flag);\n \t\tkfree(ddrclk);\n--- a/drivers/clk/rockchip/clk-rk3328.c\n+++ b/drivers/clk/rockchip/clk-rk3328.c\n@@ -314,9 +314,10 @@ static struct rockchip_clk_branch rk3328\n \t\t\tRK3328_CLKGATE_CON(14), 1, GFLAGS),\n \n \t/* PD_DDR */\n-\tCOMPOSITE(0, \"clk_ddr\", mux_ddrphy_p, CLK_IGNORE_UNUSED,\n-\t\t\tRK3328_CLKSEL_CON(3), 8, 2, MFLAGS, 0, 3, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,\n-\t\t\tRK3328_CLKGATE_CON(0), 4, GFLAGS),\n+\tCOMPOSITE_DDRCLK(SCLK_DDRCLK, \"sclk_ddrc\", mux_ddrphy_p, 0,\n+\t\t\tRK3328_CLKSEL_CON(3), 8, 2, 0, 3,\n+\t\t\tROCKCHIP_DDRCLK_SIP_V2),\n+\n \tGATE(0, \"clk_ddrmsch\", \"clk_ddr\", CLK_IGNORE_UNUSED,\n \t\t\tRK3328_CLKGATE_CON(18), 6, GFLAGS),\n \tGATE(0, \"clk_ddrupctl\", \"clk_ddr\", CLK_IGNORE_UNUSED,\n--- a/drivers/clk/rockchip/clk.h\n+++ b/drivers/clk/rockchip/clk.h\n@@ -362,7 +362,8 @@ struct clk *rockchip_clk_register_mmc(co\n  * DDRCLK flags, including method of setting the rate\n  * ROCKCHIP_DDRCLK_SIP: use SIP call to bl31 to change ddrclk rate.\n  */\n-#define ROCKCHIP_DDRCLK_SIP\t\tBIT(0)\n+#define ROCKCHIP_DDRCLK_SIP\t\t0x01\n+#define ROCKCHIP_DDRCLK_SIP_V2\t\t0x03\n \n struct clk *rockchip_clk_register_ddrclk(const char *name, int flags,\n \t\t\t\t\t const char *const *parent_names,\n--- a/include/soc/rockchip/rockchip_sip.h\n+++ b/include/soc/rockchip/rockchip_sip.h\n@@ -16,5 +16,16 @@\n #define ROCKCHIP_SIP_CONFIG_DRAM_CLR_IRQ\t0x06\n #define ROCKCHIP_SIP_CONFIG_DRAM_SET_PARAM\t0x07\n #define ROCKCHIP_SIP_CONFIG_DRAM_SET_ODT_PD\t0x08\n+#define ROCKCHIP_SIP_CONFIG_DRAM_GET_VERSION\t0x08\n+\n+#define ROCKCHIP_SIP_SHARE_MEM\t\t\t0x82000009\n+\n+/* Share mem page types */\n+typedef enum {\n+    SHARE_PAGE_TYPE_INVALID = 0,\n+    SHARE_PAGE_TYPE_UARTDBG,\n+    SHARE_PAGE_TYPE_DDR,\n+    SHARE_PAGE_TYPE_MAX,\n+} share_page_type_t;\n \n #endif\n"
  },
  {
    "path": "target/linux/rockchip/patches-5.10/805-PM-devfreq-rockchip-dfi-add-more-soc-support.patch",
    "content": "From 4db93c6dad0c71750b86163df2fdb21c35f00d9a Mon Sep 17 00:00:00 2001\nFrom: hmz007 <hmz007@gmail.com>\nDate: Tue, 19 Nov 2019 12:49:48 +0800\nSubject: [PATCH] PM / devfreq: rockchip-dfi: add more soc support\n\nSigned-off-by: hmz007 <hmz007@gmail.com>\n---\n drivers/devfreq/event/rockchip-dfi.c | 554 ++++++++++++++++++++++++---\n 1 file changed, 505 insertions(+), 49 deletions(-)\n\n--- a/drivers/devfreq/event/rockchip-dfi.c\n+++ b/drivers/devfreq/event/rockchip-dfi.c\n@@ -18,25 +18,66 @@\n #include <linux/list.h>\n #include <linux/of.h>\n \n-#include <soc/rockchip/rk3399_grf.h>\n-\n-#define RK3399_DMC_NUM_CH\t2\n+#define PX30_PMUGRF_OS_REG2\t\t0x208\n \n+#define RK3128_GRF_SOC_CON0\t\t0x140\n+#define RK3128_GRF_OS_REG1\t\t0x1cc\n+#define RK3128_GRF_DFI_WRNUM\t\t0x220\n+#define RK3128_GRF_DFI_RDNUM\t\t0x224\n+#define RK3128_GRF_DFI_TIMERVAL\t\t0x22c\n+#define RK3128_DDR_MONITOR_EN\t\t((1 << (16 + 6)) + (1 << 6))\n+#define RK3128_DDR_MONITOR_DISB\t\t((1 << (16 + 6)) + (0 << 6))\n+\n+#define RK3288_PMU_SYS_REG2\t\t0x9c\n+#define RK3288_GRF_SOC_CON4\t\t0x254\n+#define RK3288_GRF_SOC_STATUS(n)\t(0x280 + (n) * 4)\n+#define RK3288_DFI_EN\t\t\t(0x30003 << 14)\n+#define RK3288_DFI_DIS\t\t\t(0x30000 << 14)\n+#define RK3288_LPDDR_SEL\t\t(0x10001 << 13)\n+#define RK3288_DDR3_SEL\t\t\t(0x10000 << 13)\n+\n+#define RK3328_GRF_OS_REG2\t\t0x5d0\n+\n+#define RK3368_GRF_DDRC0_CON0\t\t0x600\n+#define RK3368_GRF_SOC_STATUS5\t\t0x494\n+#define RK3368_GRF_SOC_STATUS6\t\t0x498\n+#define RK3368_GRF_SOC_STATUS8\t\t0x4a0\n+#define RK3368_GRF_SOC_STATUS9\t\t0x4a4\n+#define RK3368_GRF_SOC_STATUS10\t\t0x4a8\n+#define RK3368_DFI_EN\t\t\t(0x30003 << 5)\n+#define RK3368_DFI_DIS\t\t\t(0x30000 << 5)\n+\n+#define MAX_DMC_NUM_CH\t\t\t2\n+#define READ_DRAMTYPE_INFO(n)\t\t(((n) >> 13) & 0x7)\n+#define READ_CH_INFO(n)\t\t\t(((n) >> 28) & 0x3)\n /* DDRMON_CTRL */\n-#define DDRMON_CTRL\t0x04\n-#define CLR_DDRMON_CTRL\t(0x1f0000 << 0)\n-#define LPDDR4_EN\t(0x10001 << 4)\n-#define HARDWARE_EN\t(0x10001 << 3)\n-#define LPDDR3_EN\t(0x10001 << 2)\n-#define SOFTWARE_EN\t(0x10001 << 1)\n-#define SOFTWARE_DIS\t(0x10000 << 1)\n-#define TIME_CNT_EN\t(0x10001 << 0)\n+#define DDRMON_CTRL\t\t\t0x04\n+#define CLR_DDRMON_CTRL\t\t\t(0x3f0000 << 0)\n+#define DDR4_EN\t\t\t\t(0x10001 << 5)\n+#define LPDDR4_EN\t\t\t(0x10001 << 4)\n+#define HARDWARE_EN\t\t\t(0x10001 << 3)\n+#define LPDDR2_3_EN\t\t\t(0x10001 << 2)\n+#define SOFTWARE_EN\t\t\t(0x10001 << 1)\n+#define SOFTWARE_DIS\t\t\t(0x10000 << 1)\n+#define TIME_CNT_EN\t\t\t(0x10001 << 0)\n \n #define DDRMON_CH0_COUNT_NUM\t\t0x28\n #define DDRMON_CH0_DFI_ACCESS_NUM\t0x2c\n #define DDRMON_CH1_COUNT_NUM\t\t0x3c\n #define DDRMON_CH1_DFI_ACCESS_NUM\t0x40\n \n+/* pmu grf */\n+#define PMUGRF_OS_REG2\t\t\t0x308\n+\n+enum {\n+\tDDR4 = 0,\n+\tDDR3 = 3,\n+\tLPDDR2 = 5,\n+\tLPDDR3 = 6,\n+\tLPDDR4 = 7,\n+\tUNUSED = 0xFF\n+};\n+\n struct dmc_usage {\n \tu32 access;\n \tu32 total;\n@@ -50,33 +91,261 @@ struct dmc_usage {\n struct rockchip_dfi {\n \tstruct devfreq_event_dev *edev;\n \tstruct devfreq_event_desc *desc;\n-\tstruct dmc_usage ch_usage[RK3399_DMC_NUM_CH];\n+\tstruct dmc_usage ch_usage[MAX_DMC_NUM_CH];\n \tstruct device *dev;\n \tvoid __iomem *regs;\n \tstruct regmap *regmap_pmu;\n+\tstruct regmap *regmap_grf;\n+\tstruct regmap *regmap_pmugrf;\n \tstruct clk *clk;\n+\tu32 dram_type;\n+\t/*\n+\t * available mask, 1: available, 0: not available\n+\t * each bit represent a channel\n+\t */\n+\tu32 ch_msk;\n+};\n+\n+static void rk3128_dfi_start_hardware_counter(struct devfreq_event_dev *edev)\n+{\n+\tstruct rockchip_dfi *info = devfreq_event_get_drvdata(edev);\n+\n+\tregmap_write(info->regmap_grf,\n+\t\t     RK3128_GRF_SOC_CON0,\n+\t\t     RK3128_DDR_MONITOR_EN);\n+}\n+\n+static void rk3128_dfi_stop_hardware_counter(struct devfreq_event_dev *edev)\n+{\n+\tstruct rockchip_dfi *info = devfreq_event_get_drvdata(edev);\n+\n+\tregmap_write(info->regmap_grf,\n+\t\t     RK3128_GRF_SOC_CON0,\n+\t\t     RK3128_DDR_MONITOR_DISB);\n+}\n+\n+static int rk3128_dfi_disable(struct devfreq_event_dev *edev)\n+{\n+\trk3128_dfi_stop_hardware_counter(edev);\n+\n+\treturn 0;\n+}\n+\n+static int rk3128_dfi_enable(struct devfreq_event_dev *edev)\n+{\n+\trk3128_dfi_start_hardware_counter(edev);\n+\n+\treturn 0;\n+}\n+\n+static int rk3128_dfi_set_event(struct devfreq_event_dev *edev)\n+{\n+\treturn 0;\n+}\n+\n+static int rk3128_dfi_get_event(struct devfreq_event_dev *edev,\n+\t\t\t\tstruct devfreq_event_data *edata)\n+{\n+\tstruct rockchip_dfi *info = devfreq_event_get_drvdata(edev);\n+\tunsigned long flags;\n+\tu32 dfi_wr, dfi_rd, dfi_timer;\n+\n+\tlocal_irq_save(flags);\n+\n+\trk3128_dfi_stop_hardware_counter(edev);\n+\n+\tregmap_read(info->regmap_grf, RK3128_GRF_DFI_WRNUM, &dfi_wr);\n+\tregmap_read(info->regmap_grf, RK3128_GRF_DFI_RDNUM, &dfi_rd);\n+\tregmap_read(info->regmap_grf, RK3128_GRF_DFI_TIMERVAL, &dfi_timer);\n+\n+\tedata->load_count = (dfi_wr + dfi_rd) * 4;\n+\tedata->total_count = dfi_timer;\n+\n+\trk3128_dfi_start_hardware_counter(edev);\n+\n+\tlocal_irq_restore(flags);\n+\n+\treturn 0;\n+}\n+\n+static const struct devfreq_event_ops rk3128_dfi_ops = {\n+\t.disable = rk3128_dfi_disable,\n+\t.enable = rk3128_dfi_enable,\n+\t.get_event = rk3128_dfi_get_event,\n+\t.set_event = rk3128_dfi_set_event,\n+};\n+\n+static void rk3288_dfi_start_hardware_counter(struct devfreq_event_dev *edev)\n+{\n+\tstruct rockchip_dfi *info = devfreq_event_get_drvdata(edev);\n+\n+\tregmap_write(info->regmap_grf, RK3288_GRF_SOC_CON4, RK3288_DFI_EN);\n+}\n+\n+static void rk3288_dfi_stop_hardware_counter(struct devfreq_event_dev *edev)\n+{\n+\tstruct rockchip_dfi *info = devfreq_event_get_drvdata(edev);\n+\n+\tregmap_write(info->regmap_grf, RK3288_GRF_SOC_CON4, RK3288_DFI_DIS);\n+}\n+\n+static int rk3288_dfi_disable(struct devfreq_event_dev *edev)\n+{\n+\trk3288_dfi_stop_hardware_counter(edev);\n+\n+\treturn 0;\n+}\n+\n+static int rk3288_dfi_enable(struct devfreq_event_dev *edev)\n+{\n+\trk3288_dfi_start_hardware_counter(edev);\n+\n+\treturn 0;\n+}\n+\n+static int rk3288_dfi_set_event(struct devfreq_event_dev *edev)\n+{\n+\treturn 0;\n+}\n+\n+static int rk3288_dfi_get_busier_ch(struct devfreq_event_dev *edev)\n+{\n+\tstruct rockchip_dfi *info = devfreq_event_get_drvdata(edev);\n+\tu32 tmp, max = 0;\n+\tu32 i, busier_ch = 0;\n+\tu32 rd_count, wr_count, total_count;\n+\n+\trk3288_dfi_stop_hardware_counter(edev);\n+\n+\t/* Find out which channel is busier */\n+\tfor (i = 0; i < MAX_DMC_NUM_CH; i++) {\n+\t\tif (!(info->ch_msk & BIT(i)))\n+\t\t\tcontinue;\n+\t\tregmap_read(info->regmap_grf,\n+\t\t\t    RK3288_GRF_SOC_STATUS(11 + i * 4), &wr_count);\n+\t\tregmap_read(info->regmap_grf,\n+\t\t\t    RK3288_GRF_SOC_STATUS(12 + i * 4), &rd_count);\n+\t\tregmap_read(info->regmap_grf,\n+\t\t\t    RK3288_GRF_SOC_STATUS(14 + i * 4), &total_count);\n+\t\tinfo->ch_usage[i].access = (wr_count + rd_count) * 4;\n+\t\tinfo->ch_usage[i].total = total_count;\n+\t\ttmp = info->ch_usage[i].access;\n+\t\tif (tmp > max) {\n+\t\t\tbusier_ch = i;\n+\t\t\tmax = tmp;\n+\t\t}\n+\t}\n+\trk3288_dfi_start_hardware_counter(edev);\n+\n+\treturn busier_ch;\n+}\n+\n+static int rk3288_dfi_get_event(struct devfreq_event_dev *edev,\n+\t\t\t\tstruct devfreq_event_data *edata)\n+{\n+\tstruct rockchip_dfi *info = devfreq_event_get_drvdata(edev);\n+\tint busier_ch;\n+\tunsigned long flags;\n+\n+\tlocal_irq_save(flags);\n+\tbusier_ch = rk3288_dfi_get_busier_ch(edev);\n+\tlocal_irq_restore(flags);\n+\n+\tedata->load_count = info->ch_usage[busier_ch].access;\n+\tedata->total_count = info->ch_usage[busier_ch].total;\n+\n+\treturn 0;\n+}\n+\n+static const struct devfreq_event_ops rk3288_dfi_ops = {\n+\t.disable = rk3288_dfi_disable,\n+\t.enable = rk3288_dfi_enable,\n+\t.get_event = rk3288_dfi_get_event,\n+\t.set_event = rk3288_dfi_set_event,\n+};\n+\n+static void rk3368_dfi_start_hardware_counter(struct devfreq_event_dev *edev)\n+{\n+\tstruct rockchip_dfi *info = devfreq_event_get_drvdata(edev);\n+\n+\tregmap_write(info->regmap_grf, RK3368_GRF_DDRC0_CON0, RK3368_DFI_EN);\n+}\n+\n+static void rk3368_dfi_stop_hardware_counter(struct devfreq_event_dev *edev)\n+{\n+\tstruct rockchip_dfi *info = devfreq_event_get_drvdata(edev);\n+\n+\tregmap_write(info->regmap_grf, RK3368_GRF_DDRC0_CON0, RK3368_DFI_DIS);\n+}\n+\n+static int rk3368_dfi_disable(struct devfreq_event_dev *edev)\n+{\n+\trk3368_dfi_stop_hardware_counter(edev);\n+\n+\treturn 0;\n+}\n+\n+static int rk3368_dfi_enable(struct devfreq_event_dev *edev)\n+{\n+\trk3368_dfi_start_hardware_counter(edev);\n+\n+\treturn 0;\n+}\n+\n+static int rk3368_dfi_set_event(struct devfreq_event_dev *edev)\n+{\n+\treturn 0;\n+}\n+\n+static int rk3368_dfi_get_event(struct devfreq_event_dev *edev,\n+\t\t\t\tstruct devfreq_event_data *edata)\n+{\n+\tstruct rockchip_dfi *info = devfreq_event_get_drvdata(edev);\n+\tunsigned long flags;\n+\tu32 dfi0_wr, dfi0_rd, dfi1_wr, dfi1_rd, dfi_timer;\n+\n+\tlocal_irq_save(flags);\n+\n+\trk3368_dfi_stop_hardware_counter(edev);\n+\n+\tregmap_read(info->regmap_grf, RK3368_GRF_SOC_STATUS5, &dfi0_wr);\n+\tregmap_read(info->regmap_grf, RK3368_GRF_SOC_STATUS6, &dfi0_rd);\n+\tregmap_read(info->regmap_grf, RK3368_GRF_SOC_STATUS9, &dfi1_wr);\n+\tregmap_read(info->regmap_grf, RK3368_GRF_SOC_STATUS10, &dfi1_rd);\n+\tregmap_read(info->regmap_grf, RK3368_GRF_SOC_STATUS8, &dfi_timer);\n+\n+\tedata->load_count = (dfi0_wr + dfi0_rd + dfi1_wr + dfi1_rd) * 2;\n+\tedata->total_count = dfi_timer;\n+\n+\trk3368_dfi_start_hardware_counter(edev);\n+\n+\tlocal_irq_restore(flags);\n+\n+\treturn 0;\n+}\n+\n+static const struct devfreq_event_ops rk3368_dfi_ops = {\n+\t.disable = rk3368_dfi_disable,\n+\t.enable = rk3368_dfi_enable,\n+\t.get_event = rk3368_dfi_get_event,\n+\t.set_event = rk3368_dfi_set_event,\n };\n \n static void rockchip_dfi_start_hardware_counter(struct devfreq_event_dev *edev)\n {\n \tstruct rockchip_dfi *info = devfreq_event_get_drvdata(edev);\n \tvoid __iomem *dfi_regs = info->regs;\n-\tu32 val;\n-\tu32 ddr_type;\n-\n-\t/* get ddr type */\n-\tregmap_read(info->regmap_pmu, RK3399_PMUGRF_OS_REG2, &val);\n-\tddr_type = (val >> RK3399_PMUGRF_DDRTYPE_SHIFT) &\n-\t\t    RK3399_PMUGRF_DDRTYPE_MASK;\n \n \t/* clear DDRMON_CTRL setting */\n \twritel_relaxed(CLR_DDRMON_CTRL, dfi_regs + DDRMON_CTRL);\n \n \t/* set ddr type to dfi */\n-\tif (ddr_type == RK3399_PMUGRF_DDRTYPE_LPDDR3)\n-\t\twritel_relaxed(LPDDR3_EN, dfi_regs + DDRMON_CTRL);\n-\telse if (ddr_type == RK3399_PMUGRF_DDRTYPE_LPDDR4)\n+\tif (info->dram_type == LPDDR3 || info->dram_type == LPDDR2)\n+\t\twritel_relaxed(LPDDR2_3_EN, dfi_regs + DDRMON_CTRL);\n+\telse if (info->dram_type == LPDDR4)\n \t\twritel_relaxed(LPDDR4_EN, dfi_regs + DDRMON_CTRL);\n+\telse if (info->dram_type == DDR4)\n+\t\twritel_relaxed(DDR4_EN, dfi_regs + DDRMON_CTRL);\n \n \t/* enable count, use software mode */\n \twritel_relaxed(SOFTWARE_EN, dfi_regs + DDRMON_CTRL);\n@@ -100,12 +369,22 @@ static int rockchip_dfi_get_busier_ch(st\n \trockchip_dfi_stop_hardware_counter(edev);\n \n \t/* Find out which channel is busier */\n-\tfor (i = 0; i < RK3399_DMC_NUM_CH; i++) {\n-\t\tinfo->ch_usage[i].access = readl_relaxed(dfi_regs +\n-\t\t\t\tDDRMON_CH0_DFI_ACCESS_NUM + i * 20) * 4;\n+\tfor (i = 0; i < MAX_DMC_NUM_CH; i++) {\n+\t\tif (!(info->ch_msk & BIT(i)))\n+\t\t\tcontinue;\n+\n \t\tinfo->ch_usage[i].total = readl_relaxed(dfi_regs +\n \t\t\t\tDDRMON_CH0_COUNT_NUM + i * 20);\n-\t\ttmp = info->ch_usage[i].access;\n+\n+\t\t/* LPDDR4 BL = 16,other DDR type BL = 8 */\n+\t\ttmp = readl_relaxed(dfi_regs +\n+\t\t\t\tDDRMON_CH0_DFI_ACCESS_NUM + i * 20);\n+\t\tif (info->dram_type == LPDDR4)\n+\t\t\ttmp *= 8;\n+\t\telse\n+\t\t\ttmp *= 4;\n+\t\tinfo->ch_usage[i].access = tmp;\n+\n \t\tif (tmp > max) {\n \t\t\tbusier_ch = i;\n \t\t\tmax = tmp;\n@@ -121,7 +400,8 @@ static int rockchip_dfi_disable(struct d\n \tstruct rockchip_dfi *info = devfreq_event_get_drvdata(edev);\n \n \trockchip_dfi_stop_hardware_counter(edev);\n-\tclk_disable_unprepare(info->clk);\n+\tif (info->clk)\n+\t\tclk_disable_unprepare(info->clk);\n \n \treturn 0;\n }\n@@ -131,10 +411,13 @@ static int rockchip_dfi_enable(struct de\n \tstruct rockchip_dfi *info = devfreq_event_get_drvdata(edev);\n \tint ret;\n \n-\tret = clk_prepare_enable(info->clk);\n-\tif (ret) {\n-\t\tdev_err(&edev->dev, \"failed to enable dfi clk: %d\\n\", ret);\n-\t\treturn ret;\n+\tif (info->clk) {\n+\t\tret = clk_prepare_enable(info->clk);\n+\t\tif (ret) {\n+\t\t\tdev_err(&edev->dev, \"failed to enable dfi clk: %d\\n\",\n+\t\t\t\tret);\n+\t\t\treturn ret;\n+\t\t}\n \t}\n \n \trockchip_dfi_start_hardware_counter(edev);\n@@ -151,8 +434,11 @@ static int rockchip_dfi_get_event(struct\n {\n \tstruct rockchip_dfi *info = devfreq_event_get_drvdata(edev);\n \tint busier_ch;\n+\tunsigned long flags;\n \n+\tlocal_irq_save(flags);\n \tbusier_ch = rockchip_dfi_get_busier_ch(edev);\n+\tlocal_irq_restore(flags);\n \n \tedata->load_count = info->ch_usage[busier_ch].access;\n \tedata->total_count = info->ch_usage[busier_ch].total;\n@@ -167,22 +453,116 @@ static const struct devfreq_event_ops ro\n \t.set_event = rockchip_dfi_set_event,\n };\n \n-static const struct of_device_id rockchip_dfi_id_match[] = {\n-\t{ .compatible = \"rockchip,rk3399-dfi\" },\n-\t{ },\n-};\n-MODULE_DEVICE_TABLE(of, rockchip_dfi_id_match);\n+static __init int px30_dfi_init(struct platform_device *pdev,\n+\t\t\t\t  struct rockchip_dfi *data,\n+\t\t\t\t  struct devfreq_event_desc *desc)\n+{\n+\tstruct device_node *np = pdev->dev.of_node, *node;\n+\tstruct resource *res;\n+\tu32 val;\n \n-static int rockchip_dfi_probe(struct platform_device *pdev)\n+\tres = platform_get_resource(pdev, IORESOURCE_MEM, 0);\n+\tdata->regs = devm_ioremap_resource(&pdev->dev, res);\n+\tif (IS_ERR(data->regs))\n+\t\treturn PTR_ERR(data->regs);\n+\n+\tnode = of_parse_phandle(np, \"rockchip,pmugrf\", 0);\n+\tif (node) {\n+\t\tdata->regmap_pmugrf = syscon_node_to_regmap(node);\n+\t\tif (IS_ERR(data->regmap_pmugrf))\n+\t\t\treturn PTR_ERR(data->regmap_pmugrf);\n+\t}\n+\n+\tregmap_read(data->regmap_pmugrf, PX30_PMUGRF_OS_REG2, &val);\n+\tdata->dram_type = READ_DRAMTYPE_INFO(val);\n+\tdata->ch_msk = 1;\n+\tdata->clk = NULL;\n+\n+\tdesc->ops = &rockchip_dfi_ops;\n+\n+\treturn 0;\n+}\n+\n+static __init int rk3128_dfi_init(struct platform_device *pdev,\n+\t\t\t\t  struct rockchip_dfi *data,\n+\t\t\t\t  struct devfreq_event_desc *desc)\n {\n-\tstruct device *dev = &pdev->dev;\n-\tstruct rockchip_dfi *data;\n-\tstruct devfreq_event_desc *desc;\n \tstruct device_node *np = pdev->dev.of_node, *node;\n \n-\tdata = devm_kzalloc(dev, sizeof(struct rockchip_dfi), GFP_KERNEL);\n-\tif (!data)\n-\t\treturn -ENOMEM;\n+\tnode = of_parse_phandle(np, \"rockchip,grf\", 0);\n+\tif (node) {\n+\t\tdata->regmap_grf = syscon_node_to_regmap(node);\n+\t\tif (IS_ERR(data->regmap_grf))\n+\t\t\treturn PTR_ERR(data->regmap_grf);\n+\t}\n+\n+\tdesc->ops = &rk3128_dfi_ops;\n+\n+\treturn 0;\n+}\n+\n+static __init int rk3288_dfi_init(struct platform_device *pdev,\n+\t\t\t\t  struct rockchip_dfi *data,\n+\t\t\t\t  struct devfreq_event_desc *desc)\n+{\n+\tstruct device_node *np = pdev->dev.of_node, *node;\n+\tu32 val;\n+\n+\tnode = of_parse_phandle(np, \"rockchip,pmu\", 0);\n+\tif (node) {\n+\t\tdata->regmap_pmu = syscon_node_to_regmap(node);\n+\t\tif (IS_ERR(data->regmap_pmu))\n+\t\t\treturn PTR_ERR(data->regmap_pmu);\n+\t}\n+\n+\tnode = of_parse_phandle(np, \"rockchip,grf\", 0);\n+\tif (node) {\n+\t\tdata->regmap_grf = syscon_node_to_regmap(node);\n+\t\tif (IS_ERR(data->regmap_grf))\n+\t\t\treturn PTR_ERR(data->regmap_grf);\n+\t}\n+\n+\tregmap_read(data->regmap_pmu, RK3288_PMU_SYS_REG2, &val);\n+\tdata->dram_type = READ_DRAMTYPE_INFO(val);\n+\tdata->ch_msk = READ_CH_INFO(val);\n+\n+\tif (data->dram_type == DDR3)\n+\t\tregmap_write(data->regmap_grf, RK3288_GRF_SOC_CON4,\n+\t\t\t     RK3288_DDR3_SEL);\n+\telse\n+\t\tregmap_write(data->regmap_grf, RK3288_GRF_SOC_CON4,\n+\t\t\t     RK3288_LPDDR_SEL);\n+\n+\tdesc->ops = &rk3288_dfi_ops;\n+\n+\treturn 0;\n+}\n+\n+static __init int rk3368_dfi_init(struct platform_device *pdev,\n+\t\t\t\t  struct rockchip_dfi *data,\n+\t\t\t\t  struct devfreq_event_desc *desc)\n+{\n+\tstruct device *dev = &pdev->dev;\n+\n+\tif (!dev->parent || !dev->parent->of_node)\n+\t\treturn -EINVAL;\n+\n+\tdata->regmap_grf = syscon_node_to_regmap(dev->parent->of_node);\n+\tif (IS_ERR(data->regmap_grf))\n+\t\treturn PTR_ERR(data->regmap_grf);\n+\n+\tdesc->ops = &rk3368_dfi_ops;\n+\n+\treturn 0;\n+}\n+\n+static __init int rockchip_dfi_init(struct platform_device *pdev,\n+\t\t\t\t    struct rockchip_dfi *data,\n+\t\t\t\t    struct devfreq_event_desc *desc)\n+{\n+\tstruct device *dev = &pdev->dev;\n+\tstruct device_node *np = pdev->dev.of_node, *node;\n+\tu32 val;\n \n \tdata->regs = devm_platform_ioremap_resource(pdev, 0);\n \tif (IS_ERR(data->regs))\n@@ -202,21 +582,97 @@ static int rockchip_dfi_probe(struct pla\n \t\tif (IS_ERR(data->regmap_pmu))\n \t\t\treturn PTR_ERR(data->regmap_pmu);\n \t}\n-\tdata->dev = dev;\n+\n+\tregmap_read(data->regmap_pmu, PMUGRF_OS_REG2, &val);\n+\tdata->dram_type = READ_DRAMTYPE_INFO(val);\n+\tdata->ch_msk = READ_CH_INFO(val);\n+\n+\tdesc->ops = &rockchip_dfi_ops;\n+\n+\treturn 0;\n+}\n+\n+static __init int rk3328_dfi_init(struct platform_device *pdev,\n+\t\t\t\t  struct rockchip_dfi *data,\n+\t\t\t\t  struct devfreq_event_desc *desc)\n+{\n+\tstruct device_node *np = pdev->dev.of_node, *node;\n+\tstruct resource *res;\n+\tu32 val;\n+\n+\tres = platform_get_resource(pdev, IORESOURCE_MEM, 0);\n+\tdata->regs = devm_ioremap_resource(&pdev->dev, res);\n+\tif (IS_ERR(data->regs))\n+\t\treturn PTR_ERR(data->regs);\n+\n+\tnode = of_parse_phandle(np, \"rockchip,grf\", 0);\n+\tif (node) {\n+\t\tdata->regmap_grf = syscon_node_to_regmap(node);\n+\t\tif (IS_ERR(data->regmap_grf))\n+\t\t\treturn PTR_ERR(data->regmap_grf);\n+\t}\n+\n+\tregmap_read(data->regmap_grf, RK3328_GRF_OS_REG2, &val);\n+\tdata->dram_type = READ_DRAMTYPE_INFO(val);\n+\tdata->ch_msk = 1;\n+\tdata->clk = NULL;\n+\n+\tdesc->ops = &rockchip_dfi_ops;\n+\n+\treturn 0;\n+}\n+\n+static const struct of_device_id rockchip_dfi_id_match[] = {\n+\t{ .compatible = \"rockchip,px30-dfi\", .data = px30_dfi_init },\n+\t{ .compatible = \"rockchip,rk1808-dfi\", .data = px30_dfi_init },\n+\t{ .compatible = \"rockchip,rk3128-dfi\", .data = rk3128_dfi_init },\n+\t{ .compatible = \"rockchip,rk3288-dfi\", .data = rk3288_dfi_init },\n+\t{ .compatible = \"rockchip,rk3328-dfi\", .data = rk3328_dfi_init },\n+\t{ .compatible = \"rockchip,rk3368-dfi\", .data = rk3368_dfi_init },\n+\t{ .compatible = \"rockchip,rk3399-dfi\", .data = rockchip_dfi_init },\n+\t{ },\n+};\n+MODULE_DEVICE_TABLE(of, rockchip_dfi_id_match);\n+\n+static int rockchip_dfi_probe(struct platform_device *pdev)\n+{\n+\tstruct device *dev = &pdev->dev;\n+\tstruct rockchip_dfi *data;\n+\tstruct devfreq_event_desc *desc;\n+\tstruct device_node *np = pdev->dev.of_node;\n+\tconst struct of_device_id *match;\n+\tint (*init)(struct platform_device *pdev, struct rockchip_dfi *data,\n+\t\t    struct devfreq_event_desc *desc);\n+\n+\tdata = devm_kzalloc(dev, sizeof(struct rockchip_dfi), GFP_KERNEL);\n+\tif (!data)\n+\t\treturn -ENOMEM;\n \n \tdesc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL);\n \tif (!desc)\n \t\treturn -ENOMEM;\n \n-\tdesc->ops = &rockchip_dfi_ops;\n+\tmatch = of_match_node(rockchip_dfi_id_match, pdev->dev.of_node);\n+\tif (match) {\n+\t\tinit = match->data;\n+\t\tif (init) {\n+\t\t\tif (init(pdev, data, desc))\n+\t\t\t\treturn -EINVAL;\n+\t\t} else {\n+\t\t\treturn 0;\n+\t\t}\n+\t} else {\n+\t\treturn 0;\n+\t}\n+\n \tdesc->driver_data = data;\n \tdesc->name = np->name;\n \tdata->desc = desc;\n+\tdata->dev = dev;\n \n-\tdata->edev = devm_devfreq_event_add_edev(&pdev->dev, desc);\n+\tdata->edev = devm_devfreq_event_add_edev(dev, desc);\n \tif (IS_ERR(data->edev)) {\n-\t\tdev_err(&pdev->dev,\n-\t\t\t\"failed to add devfreq-event device\\n\");\n+\t\tdev_err(dev, \"failed to add devfreq-event device\\n\");\n \t\treturn PTR_ERR(data->edev);\n \t}\n \n"
  },
  {
    "path": "target/linux/rockchip/patches-5.10/806-arm64-dts-rockchip-rk3328-add-dfi-node.patch",
    "content": "From f9ae6e992d3d9e80357fee7d65ba0fe2dd37ae1f Mon Sep 17 00:00:00 2001\nFrom: hmz007 <hmz007@gmail.com>\nDate: Tue, 19 Nov 2019 14:21:51 +0800\nSubject: [PATCH] arm64: dts: rockchip: rk3328: add dfi node\n\nSigned-off-by: hmz007 <hmz007@gmail.com>\n[adjusted commit title]\nSigned-off-by: Tianling Shen <cnsztl@immortalwrt.org>\n---\n arch/arm64/boot/dts/rockchip/rk3328.dtsi   |   7 +++++++\n\n--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi\n+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi\n@@ -1022,6 +1022,13 @@\n \t\t};\n \t};\n \n+\tdfi: dfi@ff790000 {\n+\t\treg = <0x00 0xff790000 0x00 0x400>;\n+\t\tcompatible = \"rockchip,rk3328-dfi\";\n+\t\trockchip,grf = <&grf>;\n+\t\tstatus = \"disabled\";\n+\t};\n+\n \tgic: interrupt-controller@ff811000 {\n \t\tcompatible = \"arm,gic-400\";\n \t\t#interrupt-cells = <3>;\n"
  },
  {
    "path": "target/linux/rockchip/patches-5.10/807-arm64-dts-nanopi-r2s-add-rk3328-dmc-relate-node.patch",
    "content": "From f9ae6e992d3d9e80357fee7d65ba0fe2dd37ae1f Mon Sep 17 00:00:00 2001\nFrom: hmz007 <hmz007@gmail.com>\nDate: Tue, 19 Nov 2019 14:21:51 +0800\nSubject: [PATCH] arm64: dts: nanopi-r2: add rk3328-dmc relate node\n\nSigned-off-by: hmz007 <hmz007@gmail.com>\n---\n .../rockchip/rk3328-dram-default-timing.dtsi  | 311 ++++++++++++++++++\n .../dts/rockchip/rk3328-nanopi-r2-common.dtsi |  85 ++++-\n include/dt-bindings/clock/rockchip-ddr.h      |  63 ++++\n include/dt-bindings/memory/rk3328-dram.h      | 159 +++++++++\n 4 files changed, 617 insertions(+), 1 deletion(-)\n create mode 100644 arch/arm64/boot/dts/rockchip/rk3328-dram-default-timing.dtsi\n create mode 100644 include/dt-bindings/clock/rockchip-ddr.h\n create mode 100644 include/dt-bindings/memory/rk3328-dram.h\n\n--- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts\n+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts\n@@ -7,6 +7,7 @@\n \n #include <dt-bindings/input/input.h>\n #include <dt-bindings/gpio/gpio.h>\n+#include \"rk3328-dram-nanopi2-timing.dtsi\"\n #include \"rk3328.dtsi\"\n \n / {\n@@ -115,6 +116,72 @@\n \t\tregulator-min-microvolt = <5000000>;\n \t\tregulator-max-microvolt = <5000000>;\n \t};\n+\n+\tdmc: dmc {\n+\t\tcompatible = \"rockchip,rk3328-dmc\";\n+\t\tdevfreq-events = <&dfi>;\n+\t\tcenter-supply = <&vdd_log>;\n+\t\tclocks = <&cru SCLK_DDRCLK>;\n+\t\tclock-names = \"dmc_clk\";\n+\t\toperating-points-v2 = <&dmc_opp_table>;\n+\t\tddr_timing = <&ddr_timing>;\n+\t\tupthreshold = <40>;\n+\t\tdowndifferential = <20>;\n+\t\tauto-min-freq = <786000>;\n+\t\tauto-freq-en = <0>;\n+\t\t#cooling-cells = <2>;\n+\t\tstatus = \"okay\";\n+\n+\t\tddr_power_model: ddr_power_model {\n+\t\t\tcompatible = \"ddr_power_model\";\n+\t\t\tdynamic-power-coefficient = <120>;\n+\t\t\tstatic-power-coefficient = <200>;\n+\t\t\tts = <32000 4700 (-80) 2>;\n+\t\t\tthermal-zone = \"soc-thermal\";\n+\t\t};\n+\t};\n+\n+\tdmc_opp_table: dmc-opp-table {\n+\t\tcompatible = \"operating-points-v2\";\n+\n+\t\trockchip,leakage-voltage-sel = <\n+\t\t\t1   10    0\n+\t\t\t11  254   1\n+\t\t>;\n+\t\tnvmem-cells = <&logic_leakage>;\n+\t\tnvmem-cell-names = \"ddr_leakage\";\n+\n+\t\topp-786000000 {\n+\t\t\topp-hz = /bits/ 64 <786000000>;\n+\t\t\topp-microvolt = <1075000>;\n+\t\t\topp-microvolt-L0 = <1075000>;\n+\t\t\topp-microvolt-L1 = <1050000>;\n+\t\t};\n+\t\topp-798000000 {\n+\t\t\topp-hz = /bits/ 64 <798000000>;\n+\t\t\topp-microvolt = <1075000>;\n+\t\t\topp-microvolt-L0 = <1075000>;\n+\t\t\topp-microvolt-L1 = <1050000>;\n+\t\t};\n+\t\topp-840000000 {\n+\t\t\topp-hz = /bits/ 64 <840000000>;\n+\t\t\topp-microvolt = <1075000>;\n+\t\t\topp-microvolt-L0 = <1075000>;\n+\t\t\topp-microvolt-L1 = <1050000>;\n+\t\t};\n+\t\topp-924000000 {\n+\t\t\topp-hz = /bits/ 64 <924000000>;\n+\t\t\topp-microvolt = <1100000>;\n+\t\t\topp-microvolt-L0 = <1100000>;\n+\t\t\topp-microvolt-L1 = <1075000>;\n+\t\t};\n+\t\topp-1056000000 {\n+\t\t\topp-hz = /bits/ 64 <1056000000>;\n+\t\t\topp-microvolt = <1175000>;\n+\t\t\topp-microvolt-L0 = <1175000>;\n+\t\t\topp-microvolt-L1 = <1150000>;\n+\t\t};\n+\t};\n };\n \n &cpu0 {\n@@ -137,6 +204,10 @@\n \tstatus = \"disabled\";\n };\n \n+&dfi {\n+\tstatus = \"okay\";\n+};\n+\n &gmac2io {\n \tassigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>;\n \tassigned-clock-parents = <&gmac_clk>, <&gmac_clk>;\n@@ -202,6 +273,7 @@\n \t\t\t\tregulator-name = \"vdd_log\";\n \t\t\t\tregulator-always-on;\n \t\t\t\tregulator-boot-on;\n+\t\t\t\tregulator-init-microvolt = <1075000>;\n \t\t\t\tregulator-min-microvolt = <712500>;\n \t\t\t\tregulator-max-microvolt = <1450000>;\n \t\t\t\tregulator-ramp-delay = <12500>;\n@@ -216,6 +288,7 @@\n \t\t\t\tregulator-name = \"vdd_arm\";\n \t\t\t\tregulator-always-on;\n \t\t\t\tregulator-boot-on;\n+\t\t\t\tregulator-init-microvolt = <1225000>;\n \t\t\t\tregulator-min-microvolt = <712500>;\n \t\t\t\tregulator-max-microvolt = <1450000>;\n \t\t\t\tregulator-ramp-delay = <12500>;\n"
  },
  {
    "path": "target/linux/rockchip/patches-5.10/808-phy-rockchip-add-driver-for-Rockchip-USB-3.0-PHY.patch",
    "content": "From faa767a9d0ced5642da0ae50b53d87de258f9525 Mon Sep 17 00:00:00 2001\nFrom: hmz007 <hmz007@gmail.com>\nDate: Tue, 19 Nov 2019 17:24:30 +0800\nSubject: [PATCH] phy: rockchip: add driver for Rockchip USB 3.0 PHY\n\nSigned-off-by: hmz007 <hmz007@gmail.com>\n---\n drivers/phy/rockchip/Kconfig                  |    8 +\n drivers/phy/rockchip/Makefile                 |    1 +\n drivers/phy/rockchip/phy-rockchip-inno-usb3.c | 1175 +++++++++++++++++\n 3 files changed, 1184 insertions(+)\n create mode 100644 drivers/phy/rockchip/phy-rockchip-inno-usb3.c\n\n--- a/drivers/phy/rockchip/Kconfig\n+++ b/drivers/phy/rockchip/Kconfig\n@@ -56,6 +56,15 @@ config PHY_ROCKCHIP_INNO_DSIDPHY\n \t  Enable this to support the Rockchip MIPI/LVDS/TTL PHY with\n \t  Innosilicon IP block.\n \n+config PHY_ROCKCHIP_INNO_USB3\n+\ttristate \"Rockchip INNO USB 3.0 PHY Driver\"\n+\tdepends on (ARCH_ROCKCHIP || COMPILE_TEST) && OF\n+\tdepends on USB_SUPPORT\n+\tselect GENERIC_PHY\n+\tselect USB_PHY\n+\thelp\n+\t  Support for Rockchip USB 3.0 PHY with Innosilicon IP block.\n+\n config PHY_ROCKCHIP_PCIE\n \ttristate \"Rockchip PCIe PHY Driver\"\n \tdepends on (ARCH_ROCKCHIP && OF) || COMPILE_TEST\n--- a/drivers/phy/rockchip/Makefile\n+++ b/drivers/phy/rockchip/Makefile\n@@ -5,6 +5,7 @@ obj-$(CONFIG_PHY_ROCKCHIP_EMMC)\t\t+= phy-\n obj-$(CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY)\t+= phy-rockchip-inno-dsidphy.o\n obj-$(CONFIG_PHY_ROCKCHIP_INNO_HDMI)\t+= phy-rockchip-inno-hdmi.o\n obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2)\t+= phy-rockchip-inno-usb2.o\n+obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB3)\t+= phy-rockchip-inno-usb3.o\n obj-$(CONFIG_PHY_ROCKCHIP_PCIE)\t\t+= phy-rockchip-pcie.o\n obj-$(CONFIG_PHY_ROCKCHIP_TYPEC)\t+= phy-rockchip-typec.o\n obj-$(CONFIG_PHY_ROCKCHIP_USB)\t\t+= phy-rockchip-usb.o\n--- a/Documentation/devicetree/bindings/soc/rockchip/grf.txt\n+++ b/Documentation/devicetree/bindings/soc/rockchip/grf.txt\n@@ -45,6 +45,8 @@ Required Properties:\n    - \"rockchip,rk3328-usb2phy-grf\", \"syscon\": for rk3328\n - compatible: USBGRF should be one of the following:\n    - \"rockchip,rv1108-usbgrf\", \"syscon\": for rv1108\n+- compatible: USB3PHYGRF should be one of the following:\n+   - \"rockchip,u3phy-grf\", \"syscon\"\n - reg: physical base address of the controller and length of memory mapped\n   region.\n \n"
  },
  {
    "path": "target/linux/sunxi/Makefile",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2013-2016 OpenWrt.org\n\ninclude $(TOPDIR)/rules.mk\n\nARCH:=arm\nBOARD:=sunxi\nBOARDNAME:=Allwinner A1x/A20/A3x/H3/H5/R40\nFEATURES:=fpu usb ext4 display rootfs-part rtc squashfs\nSUBTARGETS:=cortexa8 cortexa7 cortexa53\n\nKERNEL_PATCHVER:=5.10\nKERNEL_TESTING_PATCHVER:=5.15\n\nKERNELNAME:=zImage dtbs\n\n# A10: Cortex-A8\n# A13: Cortex-A8\n# A20: dual Cortex-A7\n# A31: quad Cortex-A7\n# A80: octa Cortex-A15/A7\n# H3: quad Cortex-A7\n# R40: quad Cortex-A7\n\ninclude $(INCLUDE_DIR)/target.mk\n\nDEFAULT_PACKAGES += uboot-envtools\nDEFAULT_PACKAGES += partx-utils mkf2fs e2fsprogs\n\n$(eval $(call BuildTarget))\n"
  },
  {
    "path": "target/linux/sunxi/base-files/etc/board.d/01_leds",
    "content": "\n. /lib/functions/uci-defaults.sh\n\nboard=$(board_name)\nboardname=\"${board##*,}\"\n\nboard_config_update\n\ncase $board in\nfriendlyarm,nanopi-r1|\\\nfriendlyarm,nanopi-r1s-h5)\n\tucidef_set_led_netdev \"wan\" \"WAN\" \"nanopi:green:wan\" \"eth0\"\n\tucidef_set_led_netdev \"lan\" \"LAN\" \"nanopi:green:lan\" \"eth1\"\n\t;;\nesac\n\nboard_config_flush\n\nexit 0\n"
  },
  {
    "path": "target/linux/sunxi/base-files/etc/board.d/02_network",
    "content": "#\n# Copyright (C) 2013-2015 OpenWrt.org\n#\n\n. /lib/functions/uci-defaults.sh\n. /lib/functions/system.sh\n\nsunxi_setup_interfaces()\n{\n\tlocal board=\"$1\"\n\n\tcase \"$board\" in\n\tfriendlyarm,nanopi-r1|\\\n\tfriendlyarm,nanopi-r1s-h5)\n\t\tucidef_set_interfaces_lan_wan \"eth1\" \"eth0\"\n\t\t;;\n\tlamobo,lamobo-r1)\n\t\tucidef_set_interfaces_lan_wan \"lan1 lan2 lan3 lan4\" wan\n\t\t;;\n\tolimex,a20-olinuxino-micro)\n\t\tucidef_set_interface_lan \"wlan0\"\n\t\t;;\n\txunlong,orangepi-r1)\n\t\tucidef_set_interfaces_lan_wan \"eth0\" \"eth1\"\n\t\t;;\n\t*)\n\t\tucidef_set_interface_lan \"eth0\"\n\t\t;;\n\tesac\n}\n\nsunxi_setup_macs()\n{\n\tlocal board=\"$1\"\n\tlocal lan_mac=\"\"\n\tlocal wan_mac=\"\"\n\tlocal label_mac=\"\"\n\n\tcase \"$board\" in\n\tfriendlyarm,nanopi-r1s-h5)\n\t\tlan_mac=$(get_mac_binary \"/sys/bus/i2c/devices/0-0051/eeprom\" 0xfa)\n\t\t;;\n\tesac\n\n\t[ -n \"$lan_mac\" ] && ucidef_set_interface_macaddr \"lan\" $lan_mac\n\t[ -n \"$wan_mac\" ] && ucidef_set_interface_macaddr \"wan\" $wan_mac\n\t[ -n \"$label_mac\" ] && ucidef_set_label_macaddr $label_mac\n}\n\nboard_config_update\nboard=$(board_name)\nsunxi_setup_interfaces $board\nsunxi_setup_macs $board\nboard_config_flush\n\nexit 0\n"
  },
  {
    "path": "target/linux/sunxi/base-files/etc/board.d/05_compat-version",
    "content": "\n. /lib/functions.sh\n. /lib/functions/uci-defaults.sh\n\nboard_config_update\n\ncase \"$(board_name)\" in\n\tlamobo,lamobo-r1)\n\t\tucidef_set_compat_version \"1.1\"\n\t\t;;\nesac\n\nboard_config_flush\n\nexit 0\n"
  },
  {
    "path": "target/linux/sunxi/base-files/etc/inittab",
    "content": "::sysinit:/etc/init.d/rcS S boot\n::shutdown:/etc/init.d/rcS K shutdown\ntts/0::askfirst:/usr/libexec/login.sh\nttyS0::askfirst:/usr/libexec/login.sh\ntty1::askfirst:/usr/libexec/login.sh\n"
  },
  {
    "path": "target/linux/sunxi/base-files/lib/firmware/brcm/brcmfmac4329-sdio.txt",
    "content": "#AP6210_NVRAM_V1.2_03192013\nmanfid=0x2d0\nprodid=0x492\nvendid=0x14e4\ndevid=0x4343\nboardtype=0x0598\n\n# Board Revision is P307, same nvram file can be used for P304, P305, P306 and P307 as the tssi pa params used are same\n#Please force the automatic RX PER data to the respective board directory if not using P307 board, for e.g. for P305 boards force the data into the following directory /projects/BCM43362/a1_labdata/boardtests/results/sdg_rev0305\nboardrev=0x1307\nboardnum=777\nxtalfreq=26000\nboardflags=0x80201\nboardflags2=0x80\nsromrev=3\nwl0id=0x431b\nmacaddr=00:90:4c:07:71:12\naa2g=1\nag0=2\nmaxp2ga0=74\ncck2gpo=0x2222\nofdm2gpo=0x44444444\nmcs2gpo0=0x6666\nmcs2gpo1=0x6666\npa0maxpwr=56\n\n#P207 PA params\n#pa0b0=5447\n#pa0b1=-658\n#pa0b2=-175<div></div>\n\n#Same PA params for P304,P305, P306, P307\n\npa0b0=5447\npa0b1=-607\npa0b2=-160\npa0itssit=62\npa1itssit=62\n\n\ncckPwrOffset=5\nccode=0\nrssismf2g=0xa\nrssismc2g=0x3\nrssisav2g=0x7\ntriso2g=0\nnoise_cal_enable_2g=0\nnoise_cal_po_2g=0\nswctrlmap_2g=0x04040404,0x02020202,0x02020202,0x010101,0x1ff\ntemp_add=29767\ntemp_mult=425\n\nbtc_flags=0x6\nbtc_params0=5000\nbtc_params1=1000\nbtc_params6=63\n\n"
  },
  {
    "path": "target/linux/sunxi/base-files/lib/firmware/brcm/brcmfmac43362-sdio.txt",
    "content": "#AP6181_NVRAM_V1.1_01152013\n#adjuest PA parameter for g/n mode\nmanfid=0x2d0\nprodid=0x492\nvendid=0x14e4\ndevid=0x4343\nboardtype=0x0598\n\n# Board Revision is P307, same nvram file can be used for P304, P305, P306 and P307 as the tssi pa params used are same\n#Please force the automatic RX PER data to the respective board directory if not using P307 board, for e.g. for P305 boards force the data into the following directory /projects/BCM43362/a1_labdata/boardtests/results/sdg_rev0305\nboardrev=0x1307\nboardnum=777\nxtalfreq=26000\nboardflags=0xa00\nsromrev=3\nwl0id=0x431b\nmacaddr=00:90:4c:07:71:12\naa2g=1\nag0=2\nmaxp2ga0=74\ncck2gpo=0x2222\nofdm2gpo=0x66666666\nmcs2gpo0=0x7777\nmcs2gpo1=0x7777\npa0maxpwr=56\n\n#P207 PA params\n#pa0b0=5447\n#pa0b1=-658\n#pa0b2=-175<div></div>\n\n#Same PA params for P304,P305, P306, P307\n\npa0b0=5447\npa0b1=-607\npa0b2=-160\npa0itssit=62\npa1itssit=62\n\n\ncckPwrOffset=5\nccode=0\nrssismf2g=0xa\nrssismc2g=0x3\nrssisav2g=0x7\ntriso2g=0\nnoise_cal_enable_2g=0\nnoise_cal_po_2g=0\nswctrlmap_2g=0x04040404,0x02020202,0x02020202,0x010101,0x1ff\ntemp_add=29767\ntemp_mult=425\n"
  },
  {
    "path": "target/linux/sunxi/base-files/lib/firmware/brcm/brcmfmac43430-sdio.txt",
    "content": "#AP6212_NVRAM_V1.0_20140603\n# 2.4 GHz, 20 MHz BW mode\n\n# The following parameter values are just placeholders, need to be updated.\nmanfid=0x2d0\nprodid=0x0726\nvendid=0x14e4\ndevid=0x43e2\nboardtype=0x0726\nboardrev=0x1101\nboardnum=22\nmacaddr=00:90:4c:c5:12:38\nsromrev=11\nboardflags=0x00404201\nxtalfreq=26000\nnocrc=1\nag0=255\naa2g=1\nccode=ALL\n\npa0itssit=0x20\nextpagain2g=0\n\n#PA parameters for 2.4GHz, measured at CHIP OUTPUT\npa2ga0=-168,7161,-820\nAvVmid_c0=0x0,0xc8\ncckpwroffset0=5\n\n# PPR params\nmaxp2ga0=90\ntxpwrbckof=6\ncckbw202gpo=0x5555\nlegofdmbw202gpo=0x77777777\nmcsbw202gpo=0xaaaaaaaa\n\n# OFDM IIR :\nofdmdigfilttype=7\n# PAPD mode:\npapdmode=2\n\nil0macaddr=00:90:4c:c5:12:38\nwl0id=0x431b\n\n#OOB parameters\nhostwake=0x40\nhostrdy=0x41\nusbrdy=0x03\nusbrdydelay=100\ndeadman_to=0xffffffff\n# muxenab: 0x1 for UART enable, 0x10 for Host awake\nmuxenab=0x10\n# CLDO PWM voltage settings - 0x4 - 1.1 volt\n#cldo_pwm=0x4\n"
  },
  {
    "path": "target/linux/sunxi/base-files/lib/preinit/79_move_config",
    "content": "# Copyright (C) 2012-2015 OpenWrt.org\n\nmove_config() {\n\tlocal partdev\n\n\t. /lib/upgrade/common.sh\n\n\tif export_bootdevice && export_partdevice partdev 1; then\n\t\tif mount -t vfat -o rw,noatime \"/dev/$partdev\" /mnt; then\n\t\t\tif [ -f \"/mnt/$BACKUP_FILE\" ]; then\n\t\t\t\tmv -f \"/mnt/$BACKUP_FILE\" /\n\t\t\tfi\n\t\t\tumount /mnt\n\t\tfi\n\tfi\n}\n\nboot_hook_add preinit_mount_root move_config\n\n"
  },
  {
    "path": "target/linux/sunxi/base-files/lib/upgrade/platform.sh",
    "content": "platform_check_image() {\n\tlocal diskdev partdev diff\n\n\texport_bootdevice && export_partdevice diskdev 0 || {\n\t\techo \"Unable to determine upgrade device\"\n\t\treturn 1\n\t}\n\n\tget_partitions \"/dev/$diskdev\" bootdisk\n\n\t#extract the boot sector from the image\n\tget_image \"$@\" | dd of=/tmp/image.bs count=1 bs=512b 2>/dev/null\n\n\tget_partitions /tmp/image.bs image\n\n\t#compare tables\n\tdiff=\"$(grep -F -x -v -f /tmp/partmap.bootdisk /tmp/partmap.image)\"\n\n\trm -f /tmp/image.bs /tmp/partmap.bootdisk /tmp/partmap.image\n\n\tif [ -n \"$diff\" ]; then\n\t\techo \"Partition layout has changed. Full image will be written.\"\n\t\task_bool 0 \"Abort\" && exit 1\n\t\treturn 0\n\tfi\n}\n\nplatform_copy_config() {\n\tlocal partdev\n\n\tif export_partdevice partdev 1; then\n\t\tmount -t vfat -o rw,noatime \"/dev/$partdev\" /mnt\n\t\tcp -af \"$UPGRADE_BACKUP\" \"/mnt/$BACKUP_FILE\"\n\t\tumount /mnt\n\tfi\n}\n\nplatform_do_upgrade() {\n\tlocal diskdev partdev diff\n\n\texport_bootdevice && export_partdevice diskdev 0 || {\n\t\techo \"Unable to determine upgrade device\"\n\t\treturn 1\n\t}\n\n\tsync\n\n\tif [ \"$UPGRADE_OPT_SAVE_PARTITIONS\" = \"1\" ]; then\n\t\tget_partitions \"/dev/$diskdev\" bootdisk\n\n\t\t#extract the boot sector from the image\n\t\tget_image \"$@\" | dd of=/tmp/image.bs count=1 bs=512b\n\n\t\tget_partitions /tmp/image.bs image\n\n\t\t#compare tables\n\t\tdiff=\"$(grep -F -x -v -f /tmp/partmap.bootdisk /tmp/partmap.image)\"\n\telse\n\t\tdiff=1\n\tfi\n\n\tif [ -n \"$diff\" ]; then\n\t\tget_image \"$@\" | dd of=\"/dev/$diskdev\" bs=4096 conv=fsync\n\n\t\t# Separate removal and addtion is necessary; otherwise, partition 1\n\t\t# will be missing if it overlaps with the old partition 2\n\t\tpartx -d - \"/dev/$diskdev\"\n\t\tpartx -a - \"/dev/$diskdev\"\n\n\t\treturn 0\n\tfi\n\n\t#write uboot image\n\tget_image \"$@\" | dd of=\"$diskdev\" bs=1024 skip=8 seek=8 count=1016 conv=fsync\n\t#iterate over each partition from the image and write it to the boot disk\n\twhile read part start size; do\n\t\tif export_partdevice partdev $part; then\n\t\t\techo \"Writing image to /dev/$partdev...\"\n\t\t\tget_image \"$@\" | dd of=\"/dev/$partdev\" ibs=\"512\" obs=1M skip=\"$start\" count=\"$size\" conv=fsync\n\t\telse\n\t\t\techo \"Unable to find partition $part device, skipped.\"\n\t\tfi\n\tdone < /tmp/partmap.image\n\n\t#copy partition uuid\n\techo \"Writing new UUID to /dev/$diskdev...\"\n\tget_image \"$@\" | dd of=\"/dev/$diskdev\" bs=1 skip=440 count=4 seek=440 conv=fsync\n}\n"
  },
  {
    "path": "target/linux/sunxi/config-5.10",
    "content": "# CONFIG_AHCI_SUNXI is not set\nCONFIG_ALIGNMENT_TRAP=y\nCONFIG_ARCH_32BIT_OFF_T=y\nCONFIG_ARCH_DMA_ADDR_T_64BIT=y\nCONFIG_ARCH_HIBERNATION_POSSIBLE=y\nCONFIG_ARCH_KEEP_MEMBLOCK=y\nCONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y\nCONFIG_ARCH_MULTIPLATFORM=y\nCONFIG_ARCH_MULTI_V6_V7=y\nCONFIG_ARCH_MULTI_V7=y\nCONFIG_ARCH_NR_GPIO=416\nCONFIG_ARCH_OPTIONAL_KERNEL_RWX=y\nCONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y\nCONFIG_ARCH_SELECT_MEMORY_MODEL=y\nCONFIG_ARCH_SPARSEMEM_ENABLE=y\nCONFIG_ARCH_SUNXI=y\nCONFIG_ARCH_SUNXI_MC_SMP=y\nCONFIG_ARCH_SUSPEND_POSSIBLE=y\nCONFIG_ARM=y\n# CONFIG_ARM_ALLWINNER_SUN50I_CPUFREQ_NVMEM is not set\nCONFIG_ARM_APPENDED_DTB=y\nCONFIG_ARM_ARCH_TIMER=y\nCONFIG_ARM_ARCH_TIMER_EVTSTREAM=y\nCONFIG_ARM_ATAG_DTB_COMPAT=y\nCONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y\nCONFIG_ARM_CCI=y\nCONFIG_ARM_CCI400_COMMON=y\nCONFIG_ARM_CCI400_PORT_CTRL=y\nCONFIG_ARM_CPU_SUSPEND=y\nCONFIG_ARM_CRYPTO=y\nCONFIG_ARM_ERRATA_643719=y\nCONFIG_ARM_GIC=y\nCONFIG_ARM_HAS_SG_CHAIN=y\nCONFIG_ARM_HEAVY_MB=y\nCONFIG_ARM_L1_CACHE_SHIFT=6\nCONFIG_ARM_L1_CACHE_SHIFT_6=y\nCONFIG_ARM_LPAE=y\nCONFIG_ARM_PATCH_IDIV=y\nCONFIG_ARM_PATCH_PHYS_VIRT=y\nCONFIG_ARM_PSCI=y\nCONFIG_ARM_PSCI_FW=y\nCONFIG_ARM_THUMB=y\nCONFIG_ARM_UNWIND=y\nCONFIG_ARM_VIRT_EXT=y\nCONFIG_ATA=y\nCONFIG_ATAGS=y\nCONFIG_AUTO_ZRELADDR=y\nCONFIG_AXP20X_POWER=y\nCONFIG_BACKLIGHT_CLASS_DEVICE=y\nCONFIG_BACKLIGHT_PWM=y\nCONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y\nCONFIG_BLK_DEV_LOOP=y\nCONFIG_BLK_DEV_SD=y\nCONFIG_BLK_PM=y\nCONFIG_BLK_SCSI_REQUEST=y\nCONFIG_BOUNCE=y\nCONFIG_CACHE_L2X0=y\nCONFIG_CAN=y\nCONFIG_CLKDEV_LOOKUP=y\nCONFIG_CLKSRC_MMIO=y\nCONFIG_CLK_SUNXI=y\nCONFIG_CLK_SUNXI_CLOCKS=y\nCONFIG_CLK_SUNXI_PRCM_SUN6I=y\nCONFIG_CLK_SUNXI_PRCM_SUN8I=y\nCONFIG_CLK_SUNXI_PRCM_SUN9I=y\nCONFIG_CLONE_BACKWARDS=y\nCONFIG_COMMON_CLK=y\nCONFIG_COMPAT_32BIT_TIME=y\nCONFIG_CONFIGFS_FS=y\nCONFIG_CONNECTOR=y\nCONFIG_CONSOLE_TRANSLATIONS=y\nCONFIG_COREDUMP=y\nCONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y\nCONFIG_CPUFREQ_DT=y\nCONFIG_CPUFREQ_DT_PLATDEV=y\nCONFIG_CPU_32v6K=y\nCONFIG_CPU_32v7=y\nCONFIG_CPU_ABRT_EV7=y\nCONFIG_CPU_CACHE_V7=y\nCONFIG_CPU_CACHE_VIPT=y\nCONFIG_CPU_COPY_V6=y\nCONFIG_CPU_CP15=y\nCONFIG_CPU_CP15_MMU=y\nCONFIG_CPU_FREQ=y\nCONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y\nCONFIG_CPU_FREQ_GOV_ATTR_SET=y\nCONFIG_CPU_FREQ_GOV_COMMON=y\nCONFIG_CPU_FREQ_GOV_CONSERVATIVE=y\nCONFIG_CPU_FREQ_GOV_ONDEMAND=y\nCONFIG_CPU_FREQ_GOV_PERFORMANCE=y\nCONFIG_CPU_FREQ_GOV_POWERSAVE=y\nCONFIG_CPU_FREQ_GOV_USERSPACE=y\nCONFIG_CPU_FREQ_STAT=y\nCONFIG_CPU_HAS_ASID=y\nCONFIG_CPU_PABRT_V7=y\nCONFIG_CPU_PM=y\nCONFIG_CPU_RMAP=y\nCONFIG_CPU_SPECTRE=y\nCONFIG_CPU_THERMAL=y\nCONFIG_CPU_THUMB_CAPABLE=y\nCONFIG_CPU_TLB_V7=y\nCONFIG_CPU_V7=y\nCONFIG_CRC16=y\nCONFIG_CRC_T10DIF=y\nCONFIG_CRYPTO_CRC32=y\nCONFIG_CRYPTO_CRC32C=y\nCONFIG_CRYPTO_CRCT10DIF=y\nCONFIG_CRYPTO_CRCT10DIF_ARM_CE=y\nCONFIG_CRYPTO_DES=y\nCONFIG_CRYPTO_DEV_ALLWINNER=y\nCONFIG_CRYPTO_DEV_SUN4I_SS=y\nCONFIG_CRYPTO_DEV_SUN4I_SS_PRNG=y\n# CONFIG_CRYPTO_DEV_SUN8I_CE is not set\n# CONFIG_CRYPTO_DEV_SUN8I_SS is not set\nCONFIG_CRYPTO_HW=y\nCONFIG_CRYPTO_LIB_DES=y\nCONFIG_CRYPTO_MD5=y\nCONFIG_CRYPTO_RNG=y\nCONFIG_CRYPTO_RNG2=y\nCONFIG_CRYPTO_SHA1=y\nCONFIG_DCACHE_WORD_ACCESS=y\nCONFIG_DEBUG_BUGVERBOSE=y\nCONFIG_DEBUG_LL_INCLUDE=\"mach/debug-macro.S\"\nCONFIG_DEBUG_MEMORY_INIT=y\nCONFIG_DMADEVICES=y\nCONFIG_DMA_ENGINE=y\nCONFIG_DMA_OF=y\nCONFIG_DMA_OPS=y\nCONFIG_DMA_REMAP=y\nCONFIG_DMA_SUN4I=y\nCONFIG_DMA_SUN6I=y\nCONFIG_DMA_VIRTUAL_CHANNELS=y\nCONFIG_DNOTIFY=y\nCONFIG_DTC=y\nCONFIG_DUMMY_CONSOLE=y\nCONFIG_DVB_CORE=y\nCONFIG_DWMAC_GENERIC=y\n# CONFIG_DWMAC_SUN8I is not set\nCONFIG_DWMAC_SUNXI=y\nCONFIG_DYNAMIC_DEBUG=y\nCONFIG_EDAC_ATOMIC_SCRUB=y\nCONFIG_EDAC_SUPPORT=y\nCONFIG_ELF_CORE=y\nCONFIG_ENABLE_MUST_CHECK=y\nCONFIG_EXT4_FS=y\nCONFIG_EXTCON=y\nCONFIG_F2FS_FS=y\nCONFIG_FAT_FS=y\nCONFIG_FB=y\nCONFIG_FB_CFB_COPYAREA=y\nCONFIG_FB_CFB_FILLRECT=y\nCONFIG_FB_CFB_IMAGEBLIT=y\nCONFIG_FB_CMDLINE=y\nCONFIG_FB_FOREIGN_ENDIAN=y\nCONFIG_FB_LITTLE_ENDIAN=y\nCONFIG_FB_MODE_HELPERS=y\nCONFIG_FB_SIMPLE=y\nCONFIG_FB_TILEBLITTING=y\nCONFIG_FIXED_PHY=y\nCONFIG_FIX_EARLYCON_MEM=y\nCONFIG_FONT_8x16=y\nCONFIG_FONT_8x8=y\nCONFIG_FONT_SUPPORT=y\nCONFIG_FRAMEBUFFER_CONSOLE=y\nCONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y\nCONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y\nCONFIG_FRAME_WARN=2048\nCONFIG_FREEZER=y\nCONFIG_FS_IOMAP=y\nCONFIG_FS_MBCACHE=y\nCONFIG_FS_POSIX_ACL=y\nCONFIG_FW_CACHE=y\nCONFIG_FW_LOADER_PAGED_BUF=y\nCONFIG_GENERIC_ALLOCATOR=y\nCONFIG_GENERIC_ARCH_TOPOLOGY=y\nCONFIG_GENERIC_BUG=y\nCONFIG_GENERIC_CLOCKEVENTS=y\nCONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y\nCONFIG_GENERIC_CPU_AUTOPROBE=y\nCONFIG_GENERIC_EARLY_IOREMAP=y\nCONFIG_GENERIC_GETTIMEOFDAY=y\nCONFIG_GENERIC_IDLE_POLL_SETUP=y\nCONFIG_GENERIC_IRQ_CHIP=y\nCONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y\nCONFIG_GENERIC_IRQ_MIGRATION=y\nCONFIG_GENERIC_IRQ_MULTI_HANDLER=y\nCONFIG_GENERIC_IRQ_SHOW=y\nCONFIG_GENERIC_IRQ_SHOW_LEVEL=y\nCONFIG_GENERIC_PCI_IOMAP=y\nCONFIG_GENERIC_PHY=y\nCONFIG_GENERIC_PINCONF=y\nCONFIG_GENERIC_PINCTRL_GROUPS=y\nCONFIG_GENERIC_PINMUX_FUNCTIONS=y\nCONFIG_GENERIC_SCHED_CLOCK=y\nCONFIG_GENERIC_SMP_IDLE_THREAD=y\nCONFIG_GENERIC_STRNCPY_FROM_USER=y\nCONFIG_GENERIC_STRNLEN_USER=y\nCONFIG_GENERIC_TIME_VSYSCALL=y\nCONFIG_GENERIC_VDSO_32=y\nCONFIG_GLOB=y\nCONFIG_GPIOLIB=y\nCONFIG_HANDLE_DOMAIN_IRQ=y\nCONFIG_HARDEN_BRANCH_PREDICTOR=y\nCONFIG_HARDIRQS_SW_RESEND=y\nCONFIG_HAS_DMA=y\nCONFIG_HAS_IOMEM=y\nCONFIG_HAS_IOPORT_MAP=y\nCONFIG_HAVE_SMP=y\nCONFIG_HIGHMEM=y\nCONFIG_HIGHPTE=y\nCONFIG_HOTPLUG_CPU=y\nCONFIG_HWMON=y\nCONFIG_HW_CONSOLE=y\nCONFIG_HW_RANDOM=y\nCONFIG_HW_RANDOM_TIMERIOMEM=y\nCONFIG_HZ_FIXED=0\nCONFIG_I2C=y\nCONFIG_I2C_BOARDINFO=y\nCONFIG_I2C_CHARDEV=y\nCONFIG_I2C_COMPAT=y\nCONFIG_I2C_HELPER_AUTO=y\nCONFIG_I2C_MV64XXX=y\nCONFIG_I2C_SUN6I_P2WI=y\nCONFIG_IIO=y\nCONFIG_INITRAMFS_SOURCE=\"\"\nCONFIG_INPUT=y\nCONFIG_INPUT_AXP20X_PEK=y\nCONFIG_INPUT_KEYBOARD=y\nCONFIG_INPUT_MOUSEDEV=y\nCONFIG_INPUT_MOUSEDEV_PSAUX=y\nCONFIG_INPUT_MOUSEDEV_SCREEN_X=1024\nCONFIG_INPUT_MOUSEDEV_SCREEN_Y=768\nCONFIG_INPUT_TOUCHSCREEN=y\nCONFIG_IRQCHIP=y\nCONFIG_IRQ_DOMAIN=y\nCONFIG_IRQ_DOMAIN_HIERARCHY=y\nCONFIG_IRQ_FORCED_THREADING=y\nCONFIG_IRQ_WORK=y\nCONFIG_JBD2=y\nCONFIG_KALLSYMS=y\nCONFIG_KEYBOARD_SUN4I_LRADC=y\nCONFIG_KSM=y\nCONFIG_LCD_CLASS_DEVICE=y\nCONFIG_LCD_PLATFORM=y\nCONFIG_LEDS_GPIO=y\nCONFIG_LIBFDT=y\nCONFIG_LOCK_DEBUGGING_SUPPORT=y\nCONFIG_LOCK_SPIN_ON_OWNER=y\nCONFIG_LOGO=y\nCONFIG_LOGO_LINUX_CLUT224=y\nCONFIG_LOGO_LINUX_MONO=y\nCONFIG_LOGO_LINUX_VGA16=y\nCONFIG_MACH_SUN4I=y\nCONFIG_MACH_SUN5I=y\nCONFIG_MACH_SUN6I=y\nCONFIG_MACH_SUN7I=y\nCONFIG_MACH_SUN8I=y\nCONFIG_MACH_SUN9I=y\nCONFIG_MAGIC_SYSRQ=y\nCONFIG_MDIO_BUS=y\nCONFIG_MDIO_DEVICE=y\nCONFIG_MDIO_DEVRES=y\nCONFIG_MDIO_SUN4I=y\nCONFIG_MEDIA_ANALOG_TV_SUPPORT=y\nCONFIG_MEDIA_ATTACH=y\nCONFIG_MEDIA_CAMERA_SUPPORT=y\nCONFIG_MEDIA_DIGITAL_TV_SUPPORT=y\nCONFIG_MEDIA_PLATFORM_SUPPORT=y\nCONFIG_MEDIA_RADIO_SUPPORT=y\nCONFIG_MEDIA_SDR_SUPPORT=y\nCONFIG_MEDIA_SUPPORT=y\nCONFIG_MEDIA_TEST_SUPPORT=y\nCONFIG_MEDIA_TUNER=y\nCONFIG_MEMFD_CREATE=y\nCONFIG_MFD_AXP20X=y\nCONFIG_MFD_AXP20X_I2C=y\nCONFIG_MFD_AXP20X_RSB=y\nCONFIG_MFD_CORE=y\nCONFIG_MFD_SUN6I_PRCM=y\nCONFIG_MFD_SYSCON=y\nCONFIG_MIGHT_HAVE_CACHE_L2X0=y\nCONFIG_MIGRATION=y\nCONFIG_MMC=y\nCONFIG_MMC_BLOCK=y\nCONFIG_MMC_SUNXI=y\nCONFIG_MODULES_USE_ELF_REL=y\nCONFIG_MTD_JEDECPROBE=y\nCONFIG_MTD_SPI_NOR=y\nCONFIG_MTD_SPLIT_FIT_FW=y\nCONFIG_MUTEX_SPIN_ON_OWNER=y\nCONFIG_NEED_DMA_MAP_STATE=y\nCONFIG_NEON=y\nCONFIG_NET_FLOW_LIMIT=y\nCONFIG_NET_PTP_CLASSIFY=y\nCONFIG_NET_VENDOR_ALLWINNER=y\nCONFIG_NLS=y\nCONFIG_NLS_CODEPAGE_437=y\nCONFIG_NLS_ISO8859_1=y\nCONFIG_NO_HZ=y\nCONFIG_NO_HZ_COMMON=y\nCONFIG_NO_HZ_IDLE=y\nCONFIG_NR_CPUS=8\nCONFIG_NVMEM=y\nCONFIG_NVMEM_SUNXI_SID=y\nCONFIG_OF=y\nCONFIG_OF_ADDRESS=y\nCONFIG_OF_EARLY_FLATTREE=y\nCONFIG_OF_FLATTREE=y\nCONFIG_OF_GPIO=y\nCONFIG_OF_IRQ=y\nCONFIG_OF_KOBJ=y\nCONFIG_OF_MDIO=y\nCONFIG_OF_NET=y\nCONFIG_OLD_SIGACTION=y\nCONFIG_OLD_SIGSUSPEND3=y\nCONFIG_OUTER_CACHE=y\nCONFIG_OUTER_CACHE_SYNC=y\nCONFIG_PADATA=y\nCONFIG_PAGE_OFFSET=0xC0000000\nCONFIG_PAGE_POOL=y\nCONFIG_PCS_XPCS=y\nCONFIG_PERF_USE_VMALLOC=y\nCONFIG_PGTABLE_LEVELS=3\nCONFIG_PHYLIB=y\nCONFIG_PHYLINK=y\nCONFIG_PHYS_ADDR_T_64BIT=y\nCONFIG_PHY_SUN4I_USB=y\n# CONFIG_PHY_SUN50I_USB3 is not set\n# CONFIG_PHY_SUN6I_MIPI_DPHY is not set\nCONFIG_PHY_SUN9I_USB=y\nCONFIG_PINCTRL=y\nCONFIG_PINCTRL_AXP209=y\nCONFIG_PINCTRL_SUN4I_A10=y\n# CONFIG_PINCTRL_SUN50I_A100 is not set\n# CONFIG_PINCTRL_SUN50I_A100_R is not set\n# CONFIG_PINCTRL_SUN50I_A64 is not set\n# CONFIG_PINCTRL_SUN50I_A64_R is not set\n# CONFIG_PINCTRL_SUN50I_H5 is not set\n# CONFIG_PINCTRL_SUN50I_H6 is not set\n# CONFIG_PINCTRL_SUN50I_H6_R is not set\nCONFIG_PINCTRL_SUN5I=y\nCONFIG_PINCTRL_SUN6I_A31=y\nCONFIG_PINCTRL_SUN6I_A31_R=y\nCONFIG_PINCTRL_SUN8I_A23=y\nCONFIG_PINCTRL_SUN8I_A23_R=y\nCONFIG_PINCTRL_SUN8I_A33=y\nCONFIG_PINCTRL_SUN8I_A83T=y\nCONFIG_PINCTRL_SUN8I_A83T_R=y\nCONFIG_PINCTRL_SUN8I_H3=y\nCONFIG_PINCTRL_SUN8I_H3_R=y\nCONFIG_PINCTRL_SUN8I_V3S=y\nCONFIG_PINCTRL_SUN9I_A80=y\nCONFIG_PINCTRL_SUN9I_A80_R=y\nCONFIG_PINCTRL_SUNXI=y\nCONFIG_PM=y\nCONFIG_PM_CLK=y\nCONFIG_PM_OPP=y\nCONFIG_PM_SLEEP=y\nCONFIG_PM_SLEEP_SMP=y\nCONFIG_POWER_RESET=y\nCONFIG_POWER_SUPPLY=y\nCONFIG_PPS=y\nCONFIG_PRINTK_TIME=y\nCONFIG_PROC_EVENTS=y\nCONFIG_PROC_PAGE_MONITOR=y\nCONFIG_PTP_1588_CLOCK=y\nCONFIG_PWM=y\nCONFIG_PWM_SUN4I=y\nCONFIG_PWM_SYSFS=y\nCONFIG_RATIONAL=y\nCONFIG_REALTEK_PHY=y\nCONFIG_REGMAP=y\nCONFIG_REGMAP_I2C=y\nCONFIG_REGMAP_IRQ=y\nCONFIG_REGMAP_MMIO=y\nCONFIG_REGMAP_SPI=y\nCONFIG_REGULATOR=y\nCONFIG_REGULATOR_AXP20X=y\nCONFIG_REGULATOR_FIXED_VOLTAGE=y\nCONFIG_REGULATOR_GPIO=y\nCONFIG_REGULATOR_SY8106A=y\nCONFIG_RELAY=y\nCONFIG_RESET_CONTROLLER=y\nCONFIG_RESET_SIMPLE=y\nCONFIG_RESET_SUNXI=y\nCONFIG_RFS_ACCEL=y\nCONFIG_RPS=y\nCONFIG_RWSEM_SPIN_ON_OWNER=y\nCONFIG_SATA_HOST=y\nCONFIG_SATA_PMP=y\nCONFIG_SCSI=y\nCONFIG_SDIO_UART=y\nCONFIG_SECURITYFS=y\nCONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y\nCONFIG_SERIAL_8250_DW=y\nCONFIG_SERIAL_8250_DWLIB=y\nCONFIG_SERIAL_8250_FSL=y\nCONFIG_SERIAL_8250_NR_UARTS=8\nCONFIG_SERIAL_8250_RUNTIME_UARTS=8\nCONFIG_SERIAL_MCTRL_GPIO=y\nCONFIG_SERIAL_OF_PLATFORM=y\nCONFIG_SERIO=y\nCONFIG_SERIO_SERPORT=y\nCONFIG_SG_POOL=y\nCONFIG_SMP=y\nCONFIG_SMP_ON_UP=y\nCONFIG_SND=y\nCONFIG_SND_COMPRESS_OFFLOAD=y\nCONFIG_SND_JACK=y\nCONFIG_SND_JACK_INPUT_DEV=y\nCONFIG_SND_PCM=y\nCONFIG_SND_SIMPLE_CARD=y\nCONFIG_SND_SIMPLE_CARD_UTILS=y\nCONFIG_SND_SOC=y\nCONFIG_SND_SOC_I2C_AND_SPI=y\n# CONFIG_SND_SUN4I_I2S is not set\n# CONFIG_SND_SUN4I_SPDIF is not set\n# CONFIG_SND_SUN8I_CODEC is not set\n# CONFIG_SND_SUN8I_CODEC_ANALOG is not set\nCONFIG_SOUND=y\nCONFIG_SOUND_OSS_CORE=y\nCONFIG_SPARSE_IRQ=y\nCONFIG_SPI=y\nCONFIG_SPI_MASTER=y\nCONFIG_SPI_MEM=y\nCONFIG_SPI_SUN4I=y\nCONFIG_SPI_SUN6I=y\nCONFIG_SRCU=y\nCONFIG_STMMAC_ETH=y\nCONFIG_STMMAC_PLATFORM=y\n# CONFIG_STMMAC_SELFTESTS is not set\nCONFIG_SUN4I_A10_CCU=y\n# CONFIG_SUN4I_EMAC is not set\nCONFIG_SUN4I_TIMER=y\nCONFIG_SUN5I_CCU=y\nCONFIG_SUN5I_HSTIMER=y\nCONFIG_SUN6I_A31_CCU=y\nCONFIG_SUN8I_A23_CCU=y\nCONFIG_SUN8I_A33_CCU=y\nCONFIG_SUN8I_A83T_CCU=y\nCONFIG_SUN8I_DE2_CCU=y\nCONFIG_SUN8I_H3_CCU=y\nCONFIG_SUN8I_R40_CCU=y\nCONFIG_SUN8I_R_CCU=y\nCONFIG_SUN8I_THERMAL=y\nCONFIG_SUN8I_V3S_CCU=y\nCONFIG_SUN9I_A80_CCU=y\nCONFIG_SUNXI_CCU=y\nCONFIG_SUNXI_RSB=y\nCONFIG_SUNXI_SRAM=y\nCONFIG_SUNXI_WATCHDOG=y\nCONFIG_SUSPEND=y\nCONFIG_SUSPEND_FREEZER=y\nCONFIG_SWIOTLB=y\nCONFIG_SWPHY=y\nCONFIG_SWP_EMULATE=y\nCONFIG_SYSFS_SYSCALL=y\nCONFIG_SYS_SUPPORTS_APM_EMULATION=y\nCONFIG_SYS_SUPPORTS_HUGETLBFS=y\nCONFIG_THERMAL=y\nCONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y\nCONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0\nCONFIG_THERMAL_GOV_STEP_WISE=y\nCONFIG_THERMAL_HWMON=y\nCONFIG_THERMAL_OF=y\nCONFIG_TICK_CPU_ACCOUNTING=y\nCONFIG_TIMER_OF=y\nCONFIG_TIMER_PROBE=y\nCONFIG_TMPFS_POSIX_ACL=y\nCONFIG_TOUCHSCREEN_PROPERTIES=y\nCONFIG_TOUCHSCREEN_SUN4I=y\nCONFIG_TREE_RCU=y\nCONFIG_TREE_SRCU=y\nCONFIG_UNCOMPRESS_INCLUDE=\"debug/uncompress.h\"\nCONFIG_UNWINDER_ARM=y\nCONFIG_USB=y\nCONFIG_USB_ANNOUNCE_NEW_DEVICES=y\n# CONFIG_USB_AUDIO is not set\nCONFIG_USB_COMMON=y\nCONFIG_USB_DWC2=y\nCONFIG_USB_DWC2_HOST=y\nCONFIG_USB_EHCI_HCD=y\nCONFIG_USB_EHCI_HCD_PLATFORM=y\nCONFIG_USB_GADGET=y\nCONFIG_USB_NET_DRIVERS=y\nCONFIG_USB_OHCI_HCD=y\nCONFIG_USB_OHCI_HCD_PLATFORM=y\nCONFIG_USB_ROLE_SWITCH=y\nCONFIG_USB_STORAGE=y\nCONFIG_USB_SUPPORT=y\nCONFIG_USERIO=y\nCONFIG_USE_OF=y\nCONFIG_VFAT_FS=y\nCONFIG_VFP=y\nCONFIG_VFPv3=y\nCONFIG_VHOST=y\nCONFIG_VHOST_IOTLB=y\nCONFIG_VHOST_NET=y\n# CONFIG_VIDEO_SUN4I_CSI is not set\n# CONFIG_VIDEO_SUN6I_CSI is not set\nCONFIG_VM_EVENT_COUNTERS=y\nCONFIG_VT=y\nCONFIG_VT_CONSOLE=y\nCONFIG_VT_CONSOLE_SLEEP=y\nCONFIG_VT_HW_CONSOLE_BINDING=y\nCONFIG_WATCHDOG_CORE=y\nCONFIG_XPS=y\nCONFIG_XXHASH=y\nCONFIG_XZ_DEC_ARM=y\nCONFIG_XZ_DEC_BCJ=y\nCONFIG_ZBOOT_ROM_BSS=0\nCONFIG_ZBOOT_ROM_TEXT=0\n"
  },
  {
    "path": "target/linux/sunxi/config-5.15",
    "content": "# CONFIG_AHCI_SUNXI is not set\nCONFIG_ALIGNMENT_TRAP=y\nCONFIG_ARCH_32BIT_OFF_T=y\nCONFIG_ARCH_DMA_ADDR_T_64BIT=y\nCONFIG_ARCH_HIBERNATION_POSSIBLE=y\nCONFIG_ARCH_KEEP_MEMBLOCK=y\nCONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y\nCONFIG_ARCH_MULTIPLATFORM=y\nCONFIG_ARCH_MULTI_V6_V7=y\nCONFIG_ARCH_MULTI_V7=y\nCONFIG_ARCH_NR_GPIO=416\nCONFIG_ARCH_OPTIONAL_KERNEL_RWX=y\nCONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y\nCONFIG_ARCH_SELECT_MEMORY_MODEL=y\nCONFIG_ARCH_SPARSEMEM_ENABLE=y\nCONFIG_ARCH_SUNXI=y\nCONFIG_ARCH_SUNXI_MC_SMP=y\nCONFIG_ARCH_SUSPEND_POSSIBLE=y\nCONFIG_ARM=y\n# CONFIG_ARM_ALLWINNER_SUN50I_CPUFREQ_NVMEM is not set\nCONFIG_ARM_APPENDED_DTB=y\nCONFIG_ARM_ARCH_TIMER=y\nCONFIG_ARM_ARCH_TIMER_EVTSTREAM=y\nCONFIG_ARM_ATAG_DTB_COMPAT=y\nCONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y\nCONFIG_ARM_CCI=y\nCONFIG_ARM_CCI400_COMMON=y\nCONFIG_ARM_CCI400_PORT_CTRL=y\nCONFIG_ARM_CPU_SUSPEND=y\nCONFIG_ARM_CRYPTO=y\nCONFIG_ARM_ERRATA_643719=y\nCONFIG_ARM_GIC=y\nCONFIG_ARM_HAS_SG_CHAIN=y\nCONFIG_ARM_HEAVY_MB=y\nCONFIG_ARM_L1_CACHE_SHIFT=6\nCONFIG_ARM_L1_CACHE_SHIFT_6=y\nCONFIG_ARM_LPAE=y\nCONFIG_ARM_PATCH_IDIV=y\nCONFIG_ARM_PATCH_PHYS_VIRT=y\nCONFIG_ARM_PSCI=y\nCONFIG_ARM_PSCI_FW=y\nCONFIG_ARM_THUMB=y\nCONFIG_ARM_UNWIND=y\nCONFIG_ARM_VIRT_EXT=y\nCONFIG_ATA=y\nCONFIG_ATAGS=y\nCONFIG_AUTO_ZRELADDR=y\nCONFIG_AXP20X_POWER=y\nCONFIG_BACKLIGHT_CLASS_DEVICE=y\nCONFIG_BACKLIGHT_PWM=y\nCONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y\nCONFIG_BLK_DEV_LOOP=y\nCONFIG_BLK_DEV_SD=y\nCONFIG_BLK_PM=y\nCONFIG_BOUNCE=y\nCONFIG_CACHE_L2X0=y\nCONFIG_CAN=y\nCONFIG_CLKSRC_MMIO=y\nCONFIG_CLK_SUNXI=y\nCONFIG_CLK_SUNXI_CLOCKS=y\nCONFIG_CLK_SUNXI_PRCM_SUN6I=y\nCONFIG_CLK_SUNXI_PRCM_SUN8I=y\nCONFIG_CLK_SUNXI_PRCM_SUN9I=y\nCONFIG_CLONE_BACKWARDS=y\nCONFIG_COMMON_CLK=y\nCONFIG_COMPAT_32BIT_TIME=y\nCONFIG_CONFIGFS_FS=y\nCONFIG_CONNECTOR=y\nCONFIG_CONSOLE_TRANSLATIONS=y\nCONFIG_COREDUMP=y\nCONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y\nCONFIG_CPUFREQ_DT=y\nCONFIG_CPUFREQ_DT_PLATDEV=y\nCONFIG_CPU_32v6K=y\nCONFIG_CPU_32v7=y\nCONFIG_CPU_ABRT_EV7=y\nCONFIG_CPU_CACHE_V7=y\nCONFIG_CPU_CACHE_VIPT=y\nCONFIG_CPU_COPY_V6=y\nCONFIG_CPU_CP15=y\nCONFIG_CPU_CP15_MMU=y\nCONFIG_CPU_FREQ=y\nCONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y\nCONFIG_CPU_FREQ_GOV_ATTR_SET=y\nCONFIG_CPU_FREQ_GOV_COMMON=y\nCONFIG_CPU_FREQ_GOV_CONSERVATIVE=y\nCONFIG_CPU_FREQ_GOV_ONDEMAND=y\nCONFIG_CPU_FREQ_GOV_PERFORMANCE=y\nCONFIG_CPU_FREQ_GOV_POWERSAVE=y\nCONFIG_CPU_FREQ_GOV_USERSPACE=y\nCONFIG_CPU_FREQ_STAT=y\nCONFIG_CPU_HAS_ASID=y\nCONFIG_CPU_PABRT_V7=y\nCONFIG_CPU_PM=y\nCONFIG_CPU_RMAP=y\nCONFIG_CPU_SPECTRE=y\nCONFIG_CPU_THERMAL=y\nCONFIG_CPU_THUMB_CAPABLE=y\nCONFIG_CPU_TLB_V7=y\nCONFIG_CPU_V7=y\nCONFIG_CRC16=y\nCONFIG_CRC_T10DIF=y\nCONFIG_CRYPTO_CRC32=y\nCONFIG_CRYPTO_CRC32C=y\nCONFIG_CRYPTO_CRCT10DIF=y\nCONFIG_CRYPTO_CRCT10DIF_ARM_CE=y\nCONFIG_CRYPTO_DES=y\nCONFIG_CRYPTO_DEV_ALLWINNER=y\nCONFIG_CRYPTO_DEV_SUN4I_SS=y\n# CONFIG_CRYPTO_DEV_SUN4I_SS_DEBUG is not set\nCONFIG_CRYPTO_DEV_SUN4I_SS_PRNG=y\n# CONFIG_CRYPTO_DEV_SUN8I_CE is not set\n# CONFIG_CRYPTO_DEV_SUN8I_SS is not set\nCONFIG_CRYPTO_HW=y\nCONFIG_CRYPTO_LIB_DES=y\nCONFIG_CRYPTO_MD5=y\nCONFIG_CRYPTO_RNG=y\nCONFIG_CRYPTO_RNG2=y\nCONFIG_CRYPTO_SHA1=y\nCONFIG_DCACHE_WORD_ACCESS=y\nCONFIG_DEBUG_BUGVERBOSE=y\nCONFIG_DEBUG_LL_INCLUDE=\"mach/debug-macro.S\"\nCONFIG_DEBUG_MEMORY_INIT=y\nCONFIG_DMADEVICES=y\nCONFIG_DMA_ENGINE=y\nCONFIG_DMA_OF=y\nCONFIG_DMA_OPS=y\nCONFIG_DMA_REMAP=y\nCONFIG_DMA_SUN4I=y\nCONFIG_DMA_SUN6I=y\nCONFIG_DMA_VIRTUAL_CHANNELS=y\nCONFIG_DNOTIFY=y\nCONFIG_DTC=y\nCONFIG_DUMMY_CONSOLE=y\nCONFIG_DVB_CORE=y\nCONFIG_DWMAC_GENERIC=y\n# CONFIG_DWMAC_SUN8I is not set\nCONFIG_DWMAC_SUNXI=y\nCONFIG_DYNAMIC_DEBUG=y\nCONFIG_EDAC_ATOMIC_SCRUB=y\nCONFIG_EDAC_SUPPORT=y\nCONFIG_ELF_CORE=y\nCONFIG_EXT4_FS=y\nCONFIG_EXTCON=y\nCONFIG_F2FS_FS=y\nCONFIG_FAT_FS=y\nCONFIG_FB=y\nCONFIG_FB_CFB_COPYAREA=y\nCONFIG_FB_CFB_FILLRECT=y\nCONFIG_FB_CFB_IMAGEBLIT=y\nCONFIG_FB_CMDLINE=y\nCONFIG_FB_FOREIGN_ENDIAN=y\nCONFIG_FB_LITTLE_ENDIAN=y\nCONFIG_FB_MODE_HELPERS=y\nCONFIG_FB_SIMPLE=y\nCONFIG_FB_TILEBLITTING=y\nCONFIG_FIXED_PHY=y\nCONFIG_FIX_EARLYCON_MEM=y\nCONFIG_FONT_8x16=y\nCONFIG_FONT_8x8=y\nCONFIG_FONT_SUPPORT=y\nCONFIG_FRAMEBUFFER_CONSOLE=y\nCONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y\nCONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y\nCONFIG_FRAME_WARN=2048\nCONFIG_FREEZER=y\nCONFIG_FS_IOMAP=y\nCONFIG_FS_MBCACHE=y\nCONFIG_FS_POSIX_ACL=y\nCONFIG_FWNODE_MDIO=y\nCONFIG_FW_CACHE=y\nCONFIG_FW_LOADER_PAGED_BUF=y\nCONFIG_GENERIC_ALLOCATOR=y\nCONFIG_GENERIC_ARCH_TOPOLOGY=y\nCONFIG_GENERIC_BUG=y\nCONFIG_GENERIC_CLOCKEVENTS=y\nCONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y\nCONFIG_GENERIC_CPU_AUTOPROBE=y\nCONFIG_GENERIC_CPU_VULNERABILITIES=y\nCONFIG_GENERIC_EARLY_IOREMAP=y\nCONFIG_GENERIC_GETTIMEOFDAY=y\nCONFIG_GENERIC_IDLE_POLL_SETUP=y\nCONFIG_GENERIC_IRQ_CHIP=y\nCONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y\nCONFIG_GENERIC_IRQ_MIGRATION=y\nCONFIG_GENERIC_IRQ_MULTI_HANDLER=y\nCONFIG_GENERIC_IRQ_SHOW=y\nCONFIG_GENERIC_IRQ_SHOW_LEVEL=y\nCONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y\nCONFIG_GENERIC_PCI_IOMAP=y\nCONFIG_GENERIC_PHY=y\nCONFIG_GENERIC_PINCONF=y\nCONFIG_GENERIC_PINCTRL_GROUPS=y\nCONFIG_GENERIC_PINMUX_FUNCTIONS=y\nCONFIG_GENERIC_SCHED_CLOCK=y\nCONFIG_GENERIC_SMP_IDLE_THREAD=y\nCONFIG_GENERIC_STRNCPY_FROM_USER=y\nCONFIG_GENERIC_STRNLEN_USER=y\nCONFIG_GENERIC_TIME_VSYSCALL=y\nCONFIG_GENERIC_VDSO_32=y\nCONFIG_GLOB=y\nCONFIG_GPIOLIB=y\nCONFIG_GPIO_CDEV=y\nCONFIG_HANDLE_DOMAIN_IRQ=y\nCONFIG_HARDEN_BRANCH_PREDICTOR=y\nCONFIG_HARDIRQS_SW_RESEND=y\nCONFIG_HAS_DMA=y\nCONFIG_HAS_IOMEM=y\nCONFIG_HAS_IOPORT_MAP=y\nCONFIG_HAVE_SMP=y\nCONFIG_HIGHMEM=y\nCONFIG_HIGHPTE=y\nCONFIG_HOTPLUG_CPU=y\nCONFIG_HWMON=y\nCONFIG_HW_CONSOLE=y\nCONFIG_HW_RANDOM=y\nCONFIG_HW_RANDOM_TIMERIOMEM=y\nCONFIG_HZ_FIXED=0\nCONFIG_I2C=y\nCONFIG_I2C_BOARDINFO=y\nCONFIG_I2C_CHARDEV=y\nCONFIG_I2C_COMPAT=y\nCONFIG_I2C_HELPER_AUTO=y\nCONFIG_I2C_MV64XXX=y\nCONFIG_I2C_SUN6I_P2WI=y\nCONFIG_IIO=y\nCONFIG_INITRAMFS_SOURCE=\"\"\nCONFIG_INPUT=y\nCONFIG_INPUT_AXP20X_PEK=y\nCONFIG_INPUT_KEYBOARD=y\nCONFIG_INPUT_MOUSEDEV=y\nCONFIG_INPUT_MOUSEDEV_PSAUX=y\nCONFIG_INPUT_MOUSEDEV_SCREEN_X=1024\nCONFIG_INPUT_MOUSEDEV_SCREEN_Y=768\nCONFIG_INPUT_TOUCHSCREEN=y\nCONFIG_IRQCHIP=y\nCONFIG_IRQ_DOMAIN=y\nCONFIG_IRQ_DOMAIN_HIERARCHY=y\nCONFIG_IRQ_FASTEOI_HIERARCHY_HANDLERS=y\nCONFIG_IRQ_FORCED_THREADING=y\nCONFIG_IRQ_WORK=y\nCONFIG_JBD2=y\nCONFIG_KALLSYMS=y\nCONFIG_KEYBOARD_SUN4I_LRADC=y\nCONFIG_KMAP_LOCAL=y\nCONFIG_KMAP_LOCAL_NON_LINEAR_PTE_ARRAY=y\nCONFIG_KSM=y\nCONFIG_LCD_CLASS_DEVICE=y\nCONFIG_LCD_PLATFORM=y\nCONFIG_LEDS_GPIO=y\nCONFIG_LIBFDT=y\nCONFIG_LOCK_DEBUGGING_SUPPORT=y\nCONFIG_LOCK_SPIN_ON_OWNER=y\nCONFIG_LOGO=y\nCONFIG_LOGO_LINUX_CLUT224=y\nCONFIG_LOGO_LINUX_MONO=y\nCONFIG_LOGO_LINUX_VGA16=y\nCONFIG_MACH_SUN4I=y\nCONFIG_MACH_SUN5I=y\nCONFIG_MACH_SUN6I=y\nCONFIG_MACH_SUN7I=y\nCONFIG_MACH_SUN8I=y\nCONFIG_MACH_SUN9I=y\nCONFIG_MAGIC_SYSRQ=y\nCONFIG_MDIO_BUS=y\nCONFIG_MDIO_DEVICE=y\nCONFIG_MDIO_DEVRES=y\nCONFIG_MDIO_SUN4I=y\nCONFIG_MEDIA_ANALOG_TV_SUPPORT=y\nCONFIG_MEDIA_ATTACH=y\nCONFIG_MEDIA_CAMERA_SUPPORT=y\nCONFIG_MEDIA_DIGITAL_TV_SUPPORT=y\nCONFIG_MEDIA_PLATFORM_SUPPORT=y\nCONFIG_MEDIA_RADIO_SUPPORT=y\nCONFIG_MEDIA_SDR_SUPPORT=y\nCONFIG_MEDIA_SUPPORT=y\nCONFIG_MEDIA_TEST_SUPPORT=y\nCONFIG_MEDIA_TUNER=y\nCONFIG_MEMFD_CREATE=y\nCONFIG_MFD_AXP20X=y\nCONFIG_MFD_AXP20X_I2C=y\nCONFIG_MFD_AXP20X_RSB=y\nCONFIG_MFD_CORE=y\nCONFIG_MFD_SUN6I_PRCM=y\nCONFIG_MFD_SYSCON=y\nCONFIG_MIGHT_HAVE_CACHE_L2X0=y\nCONFIG_MIGRATION=y\nCONFIG_MMC=y\nCONFIG_MMC_BLOCK=y\nCONFIG_MMC_SUNXI=y\nCONFIG_MODULES_USE_ELF_REL=y\nCONFIG_MTD_JEDECPROBE=y\nCONFIG_MTD_SPI_NOR=y\nCONFIG_MTD_SPLIT_FIT_FW=y\nCONFIG_MUTEX_SPIN_ON_OWNER=y\nCONFIG_NEED_DMA_MAP_STATE=y\nCONFIG_NEON=y\nCONFIG_NET_FLOW_LIMIT=y\nCONFIG_NET_PTP_CLASSIFY=y\nCONFIG_NET_SELFTESTS=y\nCONFIG_NET_VENDOR_ALLWINNER=y\nCONFIG_NLS=y\nCONFIG_NLS_CODEPAGE_437=y\nCONFIG_NLS_ISO8859_1=y\nCONFIG_NO_HZ=y\nCONFIG_NO_HZ_COMMON=y\nCONFIG_NO_HZ_IDLE=y\nCONFIG_NR_CPUS=8\nCONFIG_NVMEM=y\nCONFIG_NVMEM_SUNXI_SID=y\nCONFIG_OF=y\nCONFIG_OF_ADDRESS=y\nCONFIG_OF_EARLY_FLATTREE=y\nCONFIG_OF_FLATTREE=y\nCONFIG_OF_GPIO=y\nCONFIG_OF_IRQ=y\nCONFIG_OF_KOBJ=y\nCONFIG_OF_MDIO=y\nCONFIG_OLD_SIGACTION=y\nCONFIG_OLD_SIGSUSPEND3=y\nCONFIG_OUTER_CACHE=y\nCONFIG_OUTER_CACHE_SYNC=y\nCONFIG_PADATA=y\nCONFIG_PAGE_OFFSET=0xC0000000\nCONFIG_PAGE_POOL=y\nCONFIG_PCS_XPCS=y\nCONFIG_PERF_USE_VMALLOC=y\nCONFIG_PGTABLE_LEVELS=3\nCONFIG_PHYLIB=y\nCONFIG_PHYLINK=y\nCONFIG_PHYS_ADDR_T_64BIT=y\nCONFIG_PHY_SUN4I_USB=y\n# CONFIG_PHY_SUN50I_USB3 is not set\n# CONFIG_PHY_SUN6I_MIPI_DPHY is not set\nCONFIG_PHY_SUN9I_USB=y\nCONFIG_PINCTRL=y\nCONFIG_PINCTRL_AXP209=y\nCONFIG_PINCTRL_SUN4I_A10=y\n# CONFIG_PINCTRL_SUN50I_A100 is not set\n# CONFIG_PINCTRL_SUN50I_A100_R is not set\n# CONFIG_PINCTRL_SUN50I_A64 is not set\n# CONFIG_PINCTRL_SUN50I_A64_R is not set\n# CONFIG_PINCTRL_SUN50I_H5 is not set\n# CONFIG_PINCTRL_SUN50I_H6 is not set\n# CONFIG_PINCTRL_SUN50I_H616 is not set\n# CONFIG_PINCTRL_SUN50I_H616_R is not set\n# CONFIG_PINCTRL_SUN50I_H6_R is not set\nCONFIG_PINCTRL_SUN5I=y\nCONFIG_PINCTRL_SUN6I_A31=y\nCONFIG_PINCTRL_SUN6I_A31_R=y\nCONFIG_PINCTRL_SUN8I_A23=y\nCONFIG_PINCTRL_SUN8I_A23_R=y\nCONFIG_PINCTRL_SUN8I_A33=y\nCONFIG_PINCTRL_SUN8I_A83T=y\nCONFIG_PINCTRL_SUN8I_A83T_R=y\nCONFIG_PINCTRL_SUN8I_H3=y\nCONFIG_PINCTRL_SUN8I_H3_R=y\nCONFIG_PINCTRL_SUN8I_V3S=y\nCONFIG_PINCTRL_SUN9I_A80=y\nCONFIG_PINCTRL_SUN9I_A80_R=y\nCONFIG_PINCTRL_SUNXI=y\nCONFIG_PM=y\nCONFIG_PM_CLK=y\nCONFIG_PM_OPP=y\nCONFIG_PM_SLEEP=y\nCONFIG_PM_SLEEP_SMP=y\nCONFIG_POWER_RESET=y\nCONFIG_POWER_SUPPLY=y\nCONFIG_PPS=y\nCONFIG_PRINTK_TIME=y\nCONFIG_PROC_EVENTS=y\nCONFIG_PROC_PAGE_MONITOR=y\nCONFIG_PTP_1588_CLOCK=y\nCONFIG_PTP_1588_CLOCK_OPTIONAL=y\nCONFIG_PWM=y\nCONFIG_PWM_SUN4I=y\nCONFIG_PWM_SYSFS=y\nCONFIG_RATIONAL=y\nCONFIG_REALTEK_PHY=y\nCONFIG_REGMAP=y\nCONFIG_REGMAP_I2C=y\nCONFIG_REGMAP_IRQ=y\nCONFIG_REGMAP_MMIO=y\nCONFIG_REGMAP_SPI=y\nCONFIG_REGULATOR=y\nCONFIG_REGULATOR_AXP20X=y\nCONFIG_REGULATOR_FIXED_VOLTAGE=y\nCONFIG_REGULATOR_GPIO=y\nCONFIG_REGULATOR_SY8106A=y\nCONFIG_RELAY=y\nCONFIG_RESET_CONTROLLER=y\nCONFIG_RESET_SIMPLE=y\nCONFIG_RESET_SUNXI=y\nCONFIG_RFS_ACCEL=y\nCONFIG_RPS=y\nCONFIG_RWSEM_SPIN_ON_OWNER=y\nCONFIG_SATA_HOST=y\nCONFIG_SATA_PMP=y\nCONFIG_SCSI=y\nCONFIG_SCSI_COMMON=y\nCONFIG_SDIO_UART=y\nCONFIG_SECURITYFS=y\nCONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y\nCONFIG_SERIAL_8250_DW=y\nCONFIG_SERIAL_8250_DWLIB=y\nCONFIG_SERIAL_8250_FSL=y\nCONFIG_SERIAL_8250_NR_UARTS=8\nCONFIG_SERIAL_8250_RUNTIME_UARTS=8\nCONFIG_SERIAL_MCTRL_GPIO=y\nCONFIG_SERIAL_OF_PLATFORM=y\nCONFIG_SERIO=y\nCONFIG_SERIO_SERPORT=y\nCONFIG_SG_POOL=y\nCONFIG_SMP=y\nCONFIG_SMP_ON_UP=y\nCONFIG_SND=y\nCONFIG_SND_COMPRESS_OFFLOAD=y\nCONFIG_SND_JACK=y\nCONFIG_SND_JACK_INPUT_DEV=y\nCONFIG_SND_PCM=y\nCONFIG_SND_SIMPLE_CARD=y\nCONFIG_SND_SIMPLE_CARD_UTILS=y\nCONFIG_SND_SOC=y\nCONFIG_SND_SOC_I2C_AND_SPI=y\n# CONFIG_SND_SUN4I_I2S is not set\n# CONFIG_SND_SUN4I_SPDIF is not set\n# CONFIG_SND_SUN8I_CODEC is not set\n# CONFIG_SND_SUN8I_CODEC_ANALOG is not set\nCONFIG_SOCK_RX_QUEUE_MAPPING=y\nCONFIG_SOUND=y\nCONFIG_SOUND_OSS_CORE=y\nCONFIG_SPARSE_IRQ=y\nCONFIG_SPI=y\nCONFIG_SPI_MASTER=y\nCONFIG_SPI_MEM=y\nCONFIG_SPI_SUN4I=y\nCONFIG_SPI_SUN6I=y\nCONFIG_SRCU=y\nCONFIG_STMMAC_ETH=y\nCONFIG_STMMAC_PLATFORM=y\nCONFIG_SUN4I_A10_CCU=y\n# CONFIG_SUN4I_EMAC is not set\nCONFIG_SUN4I_TIMER=y\nCONFIG_SUN5I_CCU=y\nCONFIG_SUN5I_HSTIMER=y\nCONFIG_SUN6I_A31_CCU=y\nCONFIG_SUN8I_A23_CCU=y\nCONFIG_SUN8I_A33_CCU=y\nCONFIG_SUN8I_A83T_CCU=y\nCONFIG_SUN8I_DE2_CCU=y\nCONFIG_SUN8I_H3_CCU=y\nCONFIG_SUN8I_R40_CCU=y\nCONFIG_SUN8I_R_CCU=y\nCONFIG_SUN8I_THERMAL=y\nCONFIG_SUN8I_V3S_CCU=y\nCONFIG_SUN9I_A80_CCU=y\nCONFIG_SUNXI_CCU=y\nCONFIG_SUNXI_MBUS=y\nCONFIG_SUNXI_RSB=y\nCONFIG_SUNXI_SRAM=y\nCONFIG_SUNXI_WATCHDOG=y\nCONFIG_SUSPEND=y\nCONFIG_SUSPEND_FREEZER=y\nCONFIG_SWIOTLB=y\nCONFIG_SWPHY=y\nCONFIG_SWP_EMULATE=y\nCONFIG_SYSFS_SYSCALL=y\nCONFIG_SYS_SUPPORTS_APM_EMULATION=y\nCONFIG_THERMAL=y\nCONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y\nCONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0\nCONFIG_THERMAL_GOV_STEP_WISE=y\nCONFIG_THERMAL_HWMON=y\nCONFIG_THERMAL_OF=y\nCONFIG_TICK_CPU_ACCOUNTING=y\nCONFIG_TIMER_OF=y\nCONFIG_TIMER_PROBE=y\nCONFIG_TMPFS_POSIX_ACL=y\nCONFIG_TOUCHSCREEN_SUN4I=y\nCONFIG_TREE_RCU=y\nCONFIG_TREE_SRCU=y\nCONFIG_UNCOMPRESS_INCLUDE=\"debug/uncompress.h\"\nCONFIG_UNWINDER_ARM=y\nCONFIG_USB=y\nCONFIG_USB_ANNOUNCE_NEW_DEVICES=y\nCONFIG_USB_COMMON=y\nCONFIG_USB_DWC2=y\nCONFIG_USB_DWC2_HOST=y\nCONFIG_USB_EHCI_HCD=y\nCONFIG_USB_EHCI_HCD_PLATFORM=y\nCONFIG_USB_GADGET=y\nCONFIG_USB_NET_DRIVERS=y\nCONFIG_USB_OHCI_HCD=y\nCONFIG_USB_OHCI_HCD_PLATFORM=y\nCONFIG_USB_ROLE_SWITCH=y\nCONFIG_USB_STORAGE=y\nCONFIG_USB_SUPPORT=y\nCONFIG_USERIO=y\nCONFIG_USE_OF=y\nCONFIG_VFAT_FS=y\nCONFIG_VFP=y\nCONFIG_VFPv3=y\nCONFIG_VHOST=y\nCONFIG_VHOST_IOTLB=y\nCONFIG_VHOST_NET=y\n# CONFIG_VIDEO_SUN4I_CSI is not set\n# CONFIG_VIDEO_SUN6I_CSI is not set\nCONFIG_VM_EVENT_COUNTERS=y\nCONFIG_VT=y\nCONFIG_VT_CONSOLE=y\nCONFIG_VT_CONSOLE_SLEEP=y\nCONFIG_VT_HW_CONSOLE_BINDING=y\nCONFIG_WATCHDOG_CORE=y\nCONFIG_XPS=y\nCONFIG_XXHASH=y\nCONFIG_XZ_DEC_ARM=y\nCONFIG_XZ_DEC_BCJ=y\nCONFIG_ZBOOT_ROM_BSS=0\nCONFIG_ZBOOT_ROM_TEXT=0\n"
  },
  {
    "path": "target/linux/sunxi/cortexa53/config-5.10",
    "content": "CONFIG_64BIT=y\nCONFIG_ARCH_MMAP_RND_BITS=18\nCONFIG_ARCH_MMAP_RND_BITS_MAX=24\nCONFIG_ARCH_MMAP_RND_BITS_MIN=18\nCONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11\nCONFIG_ARCH_PROC_KCORE_TEXT=y\nCONFIG_ARCH_SPARSEMEM_DEFAULT=y\nCONFIG_ARCH_STACKWALK=y\nCONFIG_ARM64=y\nCONFIG_ARM64_4K_PAGES=y\nCONFIG_ARM64_PAGE_SHIFT=12\nCONFIG_ARM64_PA_BITS=48\nCONFIG_ARM64_PA_BITS_48=y\n# CONFIG_ARM64_PTR_AUTH is not set\n# CONFIG_ARM64_SVE is not set\nCONFIG_ARM64_TAGGED_ADDR_ABI=y\nCONFIG_ARM64_VA_BITS=39\nCONFIG_ARM64_VA_BITS_39=y\nCONFIG_ARM64_WORKAROUND_REPEAT_TLBI=y\nCONFIG_ARM64_WORKAROUND_SPECULATIVE_AT=y\nCONFIG_ARM_AMBA=y\nCONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y\nCONFIG_ARM_GIC_V3=y\nCONFIG_ARM_GIC_V3_ITS=y\nCONFIG_AUDIT_ARCH_COMPAT_GENERIC=y\nCONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y\nCONFIG_DMA_DIRECT_REMAP=y\nCONFIG_DWMAC_SUN8I=y\nCONFIG_EEPROM_AT24=y\n# CONFIG_FLATMEM_MANUAL is not set\nCONFIG_FRAME_POINTER=y\nCONFIG_GENERIC_BUG_RELATIVE_POINTERS=y\nCONFIG_GENERIC_CPU_VULNERABILITIES=y\nCONFIG_GENERIC_CSUM=y\nCONFIG_GENERIC_MSI_IRQ=y\nCONFIG_GENERIC_MSI_IRQ_DOMAIN=y\nCONFIG_HOLES_IN_ZONE=y\nCONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000\nCONFIG_MDIO_BUS_MUX=y\nCONFIG_MICREL_PHY=y\nCONFIG_MODULES_USE_ELF_RELA=y\nCONFIG_MUSB_PIO_ONLY=y\nCONFIG_NEED_SG_DMA_LENGTH=y\nCONFIG_NOP_USB_XCEIV=y\nCONFIG_NO_IOPORT_MAP=y\nCONFIG_PARTITION_PERCPU=y\nCONFIG_PHY_SUN50I_USB3=y\nCONFIG_PINCTRL_SUN50I_A100=y\nCONFIG_PINCTRL_SUN50I_A100_R=y\nCONFIG_PINCTRL_SUN50I_A64=y\nCONFIG_PINCTRL_SUN50I_A64_R=y\nCONFIG_PINCTRL_SUN50I_H5=y\nCONFIG_PINCTRL_SUN50I_H6=y\nCONFIG_PINCTRL_SUN50I_H6_R=y\nCONFIG_QUEUED_RWLOCKS=y\nCONFIG_QUEUED_SPINLOCKS=y\nCONFIG_RODATA_FULL_DEFAULT_ENABLED=y\nCONFIG_RTC_DRV_SUN6I=y\n# CONFIG_SND_SUN50I_CODEC_ANALOG is not set\nCONFIG_SOUND_OSS_CORE_PRECLAIM=y\nCONFIG_SPARSEMEM=y\nCONFIG_SPARSEMEM_EXTREME=y\nCONFIG_SPARSEMEM_MANUAL=y\nCONFIG_SPARSEMEM_VMEMMAP=y\nCONFIG_SPARSEMEM_VMEMMAP_ENABLE=y\nCONFIG_SUN50I_A100_CCU=y\nCONFIG_SUN50I_A100_R_CCU=y\nCONFIG_SUN50I_A64_CCU=y\nCONFIG_SUN50I_DE2_BUS=y\nCONFIG_SUN50I_ERRATUM_UNKNOWN1=y\nCONFIG_SUN50I_H6_CCU=y\nCONFIG_SUN50I_H6_R_CCU=y\nCONFIG_SYSCTL_EXCEPTION_TRACE=y\nCONFIG_THREAD_INFO_IN_TASK=y\nCONFIG_UNMAP_KERNEL_AT_EL0=y\nCONFIG_USB_MUSB_DUAL_ROLE=y\n# CONFIG_USB_MUSB_GADGET is not set\nCONFIG_USB_MUSB_HDRC=y\n# CONFIG_USB_MUSB_HOST is not set\nCONFIG_USB_MUSB_SUNXI=y\nCONFIG_USB_PHY=y\nCONFIG_VMAP_STACK=y\nCONFIG_ZONE_DMA32=y\n"
  },
  {
    "path": "target/linux/sunxi/cortexa53/config-5.15",
    "content": "CONFIG_64BIT=y\nCONFIG_ARCH_MMAP_RND_BITS=18\nCONFIG_ARCH_MMAP_RND_BITS_MAX=24\nCONFIG_ARCH_MMAP_RND_BITS_MIN=18\nCONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11\nCONFIG_ARCH_PROC_KCORE_TEXT=y\nCONFIG_ARCH_SPARSEMEM_DEFAULT=y\nCONFIG_ARCH_STACKWALK=y\nCONFIG_ARM64=y\nCONFIG_ARM64_4K_PAGES=y\nCONFIG_ARM64_PAGE_SHIFT=12\nCONFIG_ARM64_PA_BITS=48\nCONFIG_ARM64_PA_BITS_48=y\nCONFIG_ARM64_TAGGED_ADDR_ABI=y\nCONFIG_ARM64_VA_BITS=39\nCONFIG_ARM64_VA_BITS_39=y\nCONFIG_ARM64_WORKAROUND_REPEAT_TLBI=y\nCONFIG_ARM64_WORKAROUND_SPECULATIVE_AT=y\nCONFIG_ARM_AMBA=y\nCONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y\nCONFIG_ARM_GIC_V3=y\nCONFIG_ARM_GIC_V3_ITS=y\nCONFIG_AUDIT_ARCH_COMPAT_GENERIC=y\nCONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y\nCONFIG_DMA_DIRECT_REMAP=y\nCONFIG_DWMAC_SUN8I=y\nCONFIG_EEPROM_AT24=y\n# CONFIG_FLATMEM_MANUAL is not set\nCONFIG_FRAME_POINTER=y\nCONFIG_GENERIC_BUG_RELATIVE_POINTERS=y\nCONFIG_GENERIC_CPU_VULNERABILITIES=y\nCONFIG_GENERIC_CSUM=y\nCONFIG_GENERIC_MSI_IRQ=y\nCONFIG_GENERIC_MSI_IRQ_DOMAIN=y\nCONFIG_HOLES_IN_ZONE=y\nCONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000\nCONFIG_MDIO_BUS_MUX=y\nCONFIG_MICREL_PHY=y\nCONFIG_MODULES_USE_ELF_RELA=y\nCONFIG_MUSB_PIO_ONLY=y\nCONFIG_NEED_SG_DMA_LENGTH=y\nCONFIG_NOP_USB_XCEIV=y\nCONFIG_NO_IOPORT_MAP=y\nCONFIG_PARTITION_PERCPU=y\nCONFIG_PHY_SUN50I_USB3=y\nCONFIG_PINCTRL_SUN50I_A100=y\nCONFIG_PINCTRL_SUN50I_A100_R=y\nCONFIG_PINCTRL_SUN50I_A64=y\nCONFIG_PINCTRL_SUN50I_A64_R=y\nCONFIG_PINCTRL_SUN50I_H5=y\nCONFIG_PINCTRL_SUN50I_H6=y\nCONFIG_PINCTRL_SUN50I_H6_R=y\nCONFIG_QUEUED_RWLOCKS=y\nCONFIG_QUEUED_SPINLOCKS=y\nCONFIG_RODATA_FULL_DEFAULT_ENABLED=y\nCONFIG_RTC_DRV_SUN6I=y\n# CONFIG_SND_SUN50I_CODEC_ANALOG is not set\nCONFIG_SOUND_OSS_CORE_PRECLAIM=y\nCONFIG_SPARSEMEM=y\nCONFIG_SPARSEMEM_EXTREME=y\nCONFIG_SPARSEMEM_MANUAL=y\nCONFIG_SPARSEMEM_VMEMMAP=y\nCONFIG_SPARSEMEM_VMEMMAP_ENABLE=y\nCONFIG_SUN50I_A100_CCU=y\nCONFIG_SUN50I_A100_R_CCU=y\nCONFIG_SUN50I_A64_CCU=y\nCONFIG_SUN50I_DE2_BUS=y\nCONFIG_SUN50I_ERRATUM_UNKNOWN1=y\nCONFIG_SUN50I_H6_CCU=y\nCONFIG_SUN50I_H6_R_CCU=y\nCONFIG_SYSCTL_EXCEPTION_TRACE=y\nCONFIG_THREAD_INFO_IN_TASK=y\nCONFIG_UNMAP_KERNEL_AT_EL0=y\nCONFIG_USB_MUSB_DUAL_ROLE=y\nCONFIG_USB_MUSB_HDRC=y\nCONFIG_USB_MUSB_SUNXI=y\nCONFIG_USB_PHY=y\nCONFIG_VMAP_STACK=y\nCONFIG_ZONE_DMA32=y\n"
  },
  {
    "path": "target/linux/sunxi/cortexa53/target.mk",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2017 Hauke Mehrtens\n\ninclude $(TOPDIR)/rules.mk\n\nARCH:=aarch64\nBOARDNAME:=Allwinner A64/H5\nCPU_TYPE:=cortex-a53\nKERNELNAME:=Image dtbs\n"
  },
  {
    "path": "target/linux/sunxi/cortexa7/config-5.10",
    "content": "CONFIG_B53=y\nCONFIG_B53_MDIO_DRIVER=y\nCONFIG_DWMAC_SUN8I=y\nCONFIG_GRO_CELLS=y\n# CONFIG_MACH_SUN4I is not set\n# CONFIG_MACH_SUN5I is not set\nCONFIG_MDIO_BUS_MUX=y\nCONFIG_MICREL_PHY=y\nCONFIG_MUSB_PIO_ONLY=y\nCONFIG_NET_DEVLINK=y\nCONFIG_NET_DSA=y\nCONFIG_NET_DSA_TAG_BRCM=y\nCONFIG_NET_DSA_TAG_BRCM_COMMON=y\nCONFIG_NET_DSA_TAG_BRCM_LEGACY=y\nCONFIG_NET_DSA_TAG_BRCM_PREPEND=y\nCONFIG_NET_SWITCHDEV=y\nCONFIG_NOP_USB_XCEIV=y\nCONFIG_RTC_DRV_SUN6I=y\nCONFIG_USB_MUSB_DUAL_ROLE=y\n# CONFIG_USB_MUSB_GADGET is not set\nCONFIG_USB_MUSB_HDRC=y\n# CONFIG_USB_MUSB_HOST is not set\nCONFIG_USB_MUSB_SUNXI=y\nCONFIG_USB_PHY=y\n"
  },
  {
    "path": "target/linux/sunxi/cortexa7/config-5.15",
    "content": "CONFIG_B53=y\nCONFIG_B53_MDIO_DRIVER=y\nCONFIG_DWMAC_SUN8I=y\nCONFIG_GRO_CELLS=y\n# CONFIG_MACH_SUN4I is not set\n# CONFIG_MACH_SUN5I is not set\nCONFIG_MDIO_BUS_MUX=y\nCONFIG_MICREL_PHY=y\nCONFIG_MUSB_PIO_ONLY=y\nCONFIG_NET_DEVLINK=y\nCONFIG_NET_DSA=y\nCONFIG_NET_DSA_TAG_BRCM=y\nCONFIG_NET_DSA_TAG_BRCM_COMMON=y\nCONFIG_NET_DSA_TAG_BRCM_LEGACY=y\nCONFIG_NET_DSA_TAG_BRCM_PREPEND=y\nCONFIG_NET_SWITCHDEV=y\nCONFIG_NOP_USB_XCEIV=y\nCONFIG_RTC_DRV_SUN6I=y\nCONFIG_USB_MUSB_DUAL_ROLE=y\nCONFIG_USB_MUSB_HDRC=y\nCONFIG_USB_MUSB_SUNXI=y\nCONFIG_USB_PHY=y\n"
  },
  {
    "path": "target/linux/sunxi/cortexa7/target.mk",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2017 Hauke Mehrtens\n\ninclude $(TOPDIR)/rules.mk\n\nBOARDNAME:=Allwinner A20/A3x/H3/R40\nCPU_TYPE:=cortex-a7\nCPU_SUBTYPE:=neon-vfpv4\n"
  },
  {
    "path": "target/linux/sunxi/cortexa8/config-5.10",
    "content": "# CONFIG_ARM_LPAE is not set\n# CONFIG_MACH_SUN6I is not set\n# CONFIG_MACH_SUN7I is not set\n# CONFIG_MACH_SUN8I is not set\n# CONFIG_MACH_SUN9I is not set\nCONFIG_PGTABLE_LEVELS=2\n# CONFIG_PHY_SUN9I_USB is not set\n# CONFIG_SPI_SUN6I is not set\n# CONFIG_SUN8I_A83T_CCU is not set\n# CONFIG_SUN8I_THERMAL is not set\n"
  },
  {
    "path": "target/linux/sunxi/cortexa8/config-5.15",
    "content": "# CONFIG_ARM_LPAE is not set\n# CONFIG_MACH_SUN6I is not set\n# CONFIG_MACH_SUN7I is not set\n# CONFIG_MACH_SUN8I is not set\n# CONFIG_MACH_SUN9I is not set\nCONFIG_PGTABLE_LEVELS=2\n# CONFIG_PHY_SUN9I_USB is not set\n# CONFIG_SPI_SUN6I is not set\n# CONFIG_SUN8I_A83T_CCU is not set\n# CONFIG_SUN8I_THERMAL is not set\n"
  },
  {
    "path": "target/linux/sunxi/cortexa8/target.mk",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2017 Hauke Mehrtens\n\ninclude $(TOPDIR)/rules.mk\n\nBOARDNAME:=Allwinner A1x\nCPU_TYPE:=cortex-a8\nCPU_SUBTYPE:=vfpv3\n"
  },
  {
    "path": "target/linux/sunxi/image/Config.in",
    "content": "config SUNXI_SD_BOOT_PARTSIZE\n\tint \"Boot (SD Card) filesystem partition size (in MB)\"\n\tdepends on TARGET_sunxi\n\tdefault 20\n\n"
  },
  {
    "path": "target/linux/sunxi/image/Makefile",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2013-2016 OpenWrt.org\n# Copyright (C) 2016 Yousong Zhou\n\ninclude $(TOPDIR)/rules.mk\ninclude $(INCLUDE_DIR)/image.mk\n\nFAT32_BLOCK_SIZE=1024\nFAT32_BLOCKS=$(shell echo $$(($(CONFIG_SUNXI_SD_BOOT_PARTSIZE)*1024*1024/$(FAT32_BLOCK_SIZE))))\n\nDEVICE_VARS := SUNXI_DTS SUNXI_DTS_DIR\nKERNEL_LOADADDR:=0x40008000\n\ndefine Build/sunxi-sdcard\n\trm -f $@.boot\n\tmkfs.fat $@.boot -C $(FAT32_BLOCKS)\n\n\tmcopy -i $@.boot $(STAGING_DIR_IMAGE)/$(DEVICE_NAME)-boot.scr ::boot.scr\n\tmcopy -i $@.boot $(DTS_DIR)/$(SUNXI_DTS).dtb ::dtb\n\tmcopy -i $@.boot $(IMAGE_KERNEL) ::uImage\n\t./gen_sunxi_sdcard_img.sh $@ \\\n\t\t$@.boot \\\n\t\t$(IMAGE_ROOTFS) \\\n\t\t$(CONFIG_SUNXI_SD_BOOT_PARTSIZE) \\\n\t\t$(CONFIG_TARGET_ROOTFS_PARTSIZE) \\\n\t\t$(STAGING_DIR_IMAGE)/$(DEVICE_NAME)-u-boot-with-spl.bin\n\trm -f $@.boot\nendef\n\n# why \\x00\\x00\\x00\\x00 for zImage-initramfs\ndefine Device/Default\n  PROFILES := Default\n  KERNEL_NAME := zImage\n  KERNEL := kernel-bin | uImage none\n  IMAGES := sdcard.img.gz\n  IMAGE/sdcard.img.gz := sunxi-sdcard | append-metadata | gzip\n  SUNXI_DTS_DIR :=\n  SUNXI_DTS = $$(SUNXI_DTS_DIR)$$(SOC)-$(lastword $(subst _, ,$(1)))\nendef\n\ninclude $(SUBTARGET).mk\n\n$(eval $(call BuildImage))\n"
  },
  {
    "path": "target/linux/sunxi/image/cortexa53.mk",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2013-2016 OpenWrt.org\n# Copyright (C) 2016 Yousong Zhou\n\ndefine Device/sun50i\n  SUNXI_DTS_DIR := allwinner/\n  KERNEL_NAME := Image\n  KERNEL := kernel-bin\nendef\n\ndefine Device/sun50i-a64\n  SOC := sun50i-a64\n  $(Device/sun50i)\nendef\n\ndefine Device/sun50i-h5\n  SOC := sun50i-h5\n  $(Device/sun50i)\nendef\n\ndefine Device/sun50i-h6\n  SOC := sun50i-h6\n  $(Device/sun50i)\nendef\n\ndefine Device/friendlyarm_nanopi-neo-plus2\n  DEVICE_VENDOR := FriendlyARM\n  DEVICE_MODEL := NanoPi NEO Plus2\n  SUPPORTED_DEVICES:=nanopi-neo-plus2\n  $(Device/sun50i-h5)\nendef\nTARGET_DEVICES += friendlyarm_nanopi-neo-plus2\n\ndefine Device/friendlyarm_nanopi-neo2\n  DEVICE_VENDOR := FriendlyARM\n  DEVICE_MODEL := NanoPi NEO2\n  SUPPORTED_DEVICES:=nanopi-neo2\n  $(Device/sun50i-h5)\nendef\nTARGET_DEVICES += friendlyarm_nanopi-neo2\n\ndefine Device/friendlyarm_nanopi-r1s-h5\n  DEVICE_VENDOR := FriendlyARM\n  DEVICE_MODEL := Nanopi R1S H5\n  DEVICE_PACKAGES := kmod-gpio-button-hotplug kmod-usb-net-rtl8152\n  SUPPORTED_DEVICES:=nanopi-r1s-h5\n  $(Device/sun50i-h5)\nendef\nTARGET_DEVICES += friendlyarm_nanopi-r1s-h5\n\ndefine Device/libretech_all-h3-cc-h5\n  DEVICE_VENDOR := Libre Computer\n  DEVICE_MODEL := ALL-H3-CC\n  DEVICE_VARIANT := H5\n  $(Device/sun50i-h5)\n  SUNXI_DTS := $$(SUNXI_DTS_DIR)$$(SOC)-libretech-all-h3-cc\nendef\nTARGET_DEVICES += libretech_all-h3-cc-h5\n\ndefine Device/olimex_a64-olinuxino\n  DEVICE_VENDOR := Olimex\n  DEVICE_MODEL := A64-Olinuxino\n  DEVICE_PACKAGES := kmod-rtl8723bs rtl8723bu-firmware\n  $(Device/sun50i-a64)\n  SUNXI_DTS := $$(SUNXI_DTS_DIR)$$(SOC)-olinuxino\nendef\nTARGET_DEVICES += olimex_a64-olinuxino\n\ndefine Device/olimex_a64-olinuxino-emmc\n  DEVICE_VENDOR := Olimex\n  DEVICE_MODEL := A64-Olinuxino\n  DEVICE_VARIANT := eMMC\n  DEVICE_PACKAGES := kmod-rtl8723bs rtl8723bu-firmware\n  $(Device/sun50i-a64)\n  SUNXI_DTS := $$(SUNXI_DTS_DIR)$$(SOC)-olinuxino-emmc\nendef\nTARGET_DEVICES += olimex_a64-olinuxino-emmc\n\ndefine Device/pine64_pine64-plus\n  DEVICE_VENDOR := Pine64\n  DEVICE_MODEL := Pine64+\n  DEVICE_PACKAGES := kmod-rtl8723bs rtl8723bu-firmware\n  $(Device/sun50i-a64)\nendef\nTARGET_DEVICES += pine64_pine64-plus\n\ndefine Device/pine64_sopine-baseboard\n  DEVICE_VENDOR := Pine64\n  DEVICE_MODEL := SoPine\n  DEVICE_PACKAGES := kmod-rtl8723bs rtl8723bu-firmware\n  $(Device/sun50i-a64)\nendef\nTARGET_DEVICES += pine64_sopine-baseboard\n\ndefine Device/xunlong_orangepi-one-plus\n  $(Device/sun50i-h6)\n  DEVICE_VENDOR := Xunlong\n  DEVICE_MODEL := Orange Pi One Plus\n  SUNXI_DTS_DIR := allwinner/\nendef\nTARGET_DEVICES += xunlong_orangepi-one-plus\n\ndefine Device/xunlong_orangepi-pc2\n  DEVICE_VENDOR := Xunlong\n  DEVICE_MODEL := Orange Pi PC 2\n  $(Device/sun50i-h5)\nendef\nTARGET_DEVICES += xunlong_orangepi-pc2\n\ndefine Device/xunlong_orangepi-zero-plus\n  DEVICE_VENDOR := Xunlong\n  DEVICE_MODEL := Orange Pi Zero Plus\n  $(Device/sun50i-h5)\nendef\nTARGET_DEVICES += xunlong_orangepi-zero-plus\n"
  },
  {
    "path": "target/linux/sunxi/image/cortexa7.mk",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2013-2019 OpenWrt.org\n# Copyright (C) 2016 Yousong Zhou\n\ndefine Device/cubietech_cubieboard2\n  DEVICE_VENDOR := Cubietech\n  DEVICE_MODEL := Cubieboard2\n  DEVICE_PACKAGES:=kmod-ata-sunxi kmod-sun4i-emac kmod-rtc-sunxi\n  SOC := sun7i-a20\nendef\nTARGET_DEVICES += cubietech_cubieboard2\n\ndefine Device/cubietech_cubietruck\n  DEVICE_VENDOR := Cubietech\n  DEVICE_MODEL := Cubietruck\n  DEVICE_PACKAGES:=kmod-ata-sunxi kmod-rtc-sunxi kmod-brcmfmac\n  SOC := sun7i-a20\nendef\nTARGET_DEVICES += cubietech_cubietruck\n\ndefine Device/friendlyarm_nanopi-m1-plus\n  DEVICE_VENDOR := FriendlyARM\n  DEVICE_MODEL := NanoPi M1 Plus\n  DEVICE_PACKAGES:=kmod-leds-gpio kmod-brcmfmac \\\n\tcypress-firmware-43430-sdio wpad-basic-wolfssl\n  SOC := sun8i-h3\nendef\nTARGET_DEVICES += friendlyarm_nanopi-m1-plus\n\ndefine Device/friendlyarm_nanopi-neo\n  DEVICE_VENDOR := FriendlyARM\n  DEVICE_MODEL := NanoPi NEO\n  SOC := sun8i-h3\nendef\nTARGET_DEVICES += friendlyarm_nanopi-neo\n\ndefine Device/friendlyarm_nanopi-neo-air\n  DEVICE_VENDOR := FriendlyARM\n  DEVICE_MODEL := NanoPi NEO Air\n  DEVICE_PACKAGES := kmod-leds-gpio kmod-brcmfmac \\\n\tbrcmfmac-firmware-43430a0-sdio wpad-basic-wolfssl\n  SOC := sun8i-h3\nendef\nTARGET_DEVICES += friendlyarm_nanopi-neo-air\n\ndefine Device/friendlyarm_nanopi-r1\n  DEVICE_VENDOR := FriendlyARM\n  DEVICE_MODEL := NanoPi R1\n  DEVICE_PACKAGES := kmod-usb-net-rtl8152 kmod-leds-gpio \\\n\tkmod-brcmfmac cypress-firmware-43430-sdio wpad-basic-wolfssl\n  SOC := sun8i-h3\nendef\nTARGET_DEVICES += friendlyarm_nanopi-r1\n\ndefine Device/friendlyarm_zeropi\n  DEVICE_VENDOR := FriendlyARM\n  DEVICE_MODEL := ZeroPi\n  DEVICE_PACKAGES := kmod-rtc-sunxi\n  SOC := sun8i-h3\nendef\nTARGET_DEVICES += friendlyarm_zeropi\n\ndefine Device/lamobo_lamobo-r1\n  DEVICE_VENDOR := Lamobo\n  DEVICE_MODEL := Lamobo R1\n  DEVICE_ALT0_VENDOR := Bananapi\n  DEVICE_ALT0_MODEL := BPi-R1\n  DEVICE_PACKAGES := kmod-ata-sunxi kmod-rtl8192cu wpad-basic-wolfssl\n  DEVICE_COMPAT_VERSION := 1.1\n  DEVICE_COMPAT_MESSAGE := Config cannot be migrated from swconfig to DSA\n  SOC := sun7i-a20\nendef\nTARGET_DEVICES += lamobo_lamobo-r1\n\ndefine Device/lemaker_bananapi\n  DEVICE_VENDOR := LeMaker\n  DEVICE_MODEL := Banana Pi\n  DEVICE_PACKAGES:=kmod-rtc-sunxi kmod-ata-sunxi\n  SOC := sun7i-a20\nendef\nTARGET_DEVICES += lemaker_bananapi\n\ndefine Device/sinovoip_bananapi-m2-berry\n  DEVICE_VENDOR := Sinovoip\n  DEVICE_MODEL := Banana Pi M2 Berry\n  DEVICE_PACKAGES:=kmod-ata-sunxi kmod-brcmfmac \\\n\tcypress-firmware-43430-sdio wpad-basic-wolfssl\n  SUPPORTED_DEVICES:=lemaker,bananapi-m2-berry\n  SOC := sun8i-v40\nendef\nTARGET_DEVICES += sinovoip_bananapi-m2-berry\n\ndefine Device/sinovoip_bananapi-m2-ultra\n  DEVICE_VENDOR := Sinovoip\n  DEVICE_MODEL := Banana Pi M2 Ultra\n  DEVICE_PACKAGES:=kmod-ata-sunxi kmod-brcmfmac \\\n\tbrcmfmac-firmware-43430a0-sdio wpad-basic-wolfssl\n  SUPPORTED_DEVICES:=lemaker,bananapi-m2-ultra\n  SOC := sun8i-r40\nendef\nTARGET_DEVICES += sinovoip_bananapi-m2-ultra\n\ndefine Device/lemaker_bananapro\n  DEVICE_VENDOR := LeMaker\n  DEVICE_MODEL := Banana Pro\n  DEVICE_PACKAGES:=kmod-rtc-sunxi kmod-ata-sunxi kmod-brcmfmac\n  SOC := sun7i-a20\nendef\nTARGET_DEVICES += lemaker_bananapro\n\ndefine Device/linksprite_pcduino3\n  DEVICE_VENDOR := LinkSprite\n  DEVICE_MODEL := pcDuino3\n  DEVICE_PACKAGES:=kmod-sun4i-emac kmod-rtc-sunxi kmod-ata-sunxi kmod-rtl8xxxu \\\n\trtl8188eu-firmware\n  SOC := sun7i-a20\nendef\nTARGET_DEVICES += linksprite_pcduino3\n\ndefine Device/linksprite_pcduino3-nano\n  DEVICE_VENDOR := LinkSprite\n  DEVICE_MODEL := pcDuino3 Nano\n  DEVICE_PACKAGES:=kmod-rtc-sunxi kmod-ata-sunxi\n  SOC := sun7i-a20\nendef\nTARGET_DEVICES += linksprite_pcduino3-nano\n\ndefine Device/mele_m9\n  DEVICE_VENDOR := Mele\n  DEVICE_MODEL := M9\n  DEVICE_PACKAGES:=kmod-sun4i-emac kmod-rtl8192cu\n  SOC := sun6i-a31\nendef\nTARGET_DEVICES += mele_m9\n\ndefine Device/olimex_a20-olinuxino-lime\n  DEVICE_VENDOR := Olimex\n  DEVICE_MODEL := A20-OLinuXino-LIME\n  DEVICE_PACKAGES:=kmod-ata-sunxi kmod-rtc-sunxi\n  SOC := sun7i\nendef\nTARGET_DEVICES += olimex_a20-olinuxino-lime\n\ndefine Device/olimex_a20-olinuxino-lime2\n  DEVICE_VENDOR := Olimex\n  DEVICE_MODEL := A20-OLinuXino-LIME2\n  DEVICE_PACKAGES:=kmod-ata-sunxi kmod-rtc-sunxi kmod-usb-hid\n  SOC := sun7i\nendef\nTARGET_DEVICES += olimex_a20-olinuxino-lime2\n\ndefine Device/olimex_a20-olinuxino-lime2-emmc\n  DEVICE_VENDOR := Olimex\n  DEVICE_MODEL := A20-OLinuXino-LIME2\n  DEVICE_VARIANT := eMMC\n  DEVICE_PACKAGES:=kmod-ata-sunxi kmod-rtc-sunxi kmod-usb-hid\n  SOC := sun7i\nendef\nTARGET_DEVICES += olimex_a20-olinuxino-lime2-emmc\n\ndefine Device/olimex_a20-olinuxino-micro\n  DEVICE_VENDOR := Olimex\n  DEVICE_MODEL := A20-OLinuXino-MICRO\n  DEVICE_PACKAGES:=kmod-ata-sunxi kmod-sun4i-emac kmod-rtc-sunxi\n  SOC := sun7i\nendef\nTARGET_DEVICES += olimex_a20-olinuxino-micro\n\ndefine Device/sinovoip_bananapi-m2-plus\n  DEVICE_VENDOR := Sinovoip\n  DEVICE_MODEL := Banana Pi M2+\n  DEVICE_PACKAGES:=kmod-leds-gpio kmod-brcmfmac \\\n\tbrcmfmac-firmware-43430a0-sdio wpad-basic-wolfssl\n  SOC := sun8i-h3\nendef\nTARGET_DEVICES += sinovoip_bananapi-m2-plus\n\ndefine Device/xunlong_orangepi-one\n  DEVICE_VENDOR := Xunlong\n  DEVICE_MODEL := Orange Pi One\n  DEVICE_PACKAGES:=kmod-rtc-sunxi\n  SOC := sun8i-h3\nendef\nTARGET_DEVICES += xunlong_orangepi-one\n\ndefine Device/xunlong_orangepi-pc\n  DEVICE_VENDOR := Xunlong\n  DEVICE_MODEL := Orange Pi PC\n  DEVICE_PACKAGES:=kmod-gpio-button-hotplug\n  SOC := sun8i-h3\nendef\nTARGET_DEVICES += xunlong_orangepi-pc\n\ndefine Device/xunlong_orangepi-pc-plus\n  DEVICE_VENDOR := Xunlong\n  DEVICE_MODEL := Orange Pi PC Plus\n  DEVICE_PACKAGES:=kmod-gpio-button-hotplug\n  SOC := sun8i-h3\nendef\nTARGET_DEVICES += xunlong_orangepi-pc-plus\n\ndefine Device/xunlong_orangepi-plus\n  DEVICE_VENDOR := Xunlong\n  DEVICE_MODEL := Orange Pi Plus\n  DEVICE_PACKAGES:=kmod-rtc-sunxi\n  SOC := sun8i-h3\nendef\nTARGET_DEVICES += xunlong_orangepi-plus\n\ndefine Device/xunlong_orangepi-r1\n  DEVICE_VENDOR := Xunlong\n  DEVICE_MODEL := Orange Pi R1\n  DEVICE_PACKAGES:=kmod-usb-net-rtl8152\n  SOC := sun8i-h2-plus\nendef\nTARGET_DEVICES += xunlong_orangepi-r1\n\ndefine Device/xunlong_orangepi-zero\n  DEVICE_VENDOR := Xunlong\n  DEVICE_MODEL := Orange Pi Zero\n  DEVICE_PACKAGES:=kmod-rtc-sunxi\n  SOC := sun8i-h2-plus\nendef\nTARGET_DEVICES += xunlong_orangepi-zero\n\ndefine Device/xunlong_orangepi-2\n  DEVICE_VENDOR := Xunlong\n  DEVICE_MODEL := Orange Pi 2\n  DEVICE_PACKAGES:=kmod-rtc-sunxi\n  SOC := sun8i-h3\nendef\nTARGET_DEVICES += xunlong_orangepi-2\n"
  },
  {
    "path": "target/linux/sunxi/image/cortexa8.mk",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2013-2016 OpenWrt.org\n# Copyright (C) 2016 Yousong Zhou\n\ndefine Device/cubietech_a10-cubieboard\n  DEVICE_VENDOR := Cubietech\n  DEVICE_MODEL := Cubieboard\n  DEVICE_PACKAGES:=kmod-ata-sunxi kmod-sun4i-emac kmod-rtc-sunxi\n  SOC := sun4i\nendef\nTARGET_DEVICES += cubietech_a10-cubieboard\n\ndefine Device/linksprite_a10-pcduino\n  DEVICE_VENDOR := LinkSprite\n  DEVICE_MODEL := pcDuino\n  DEVICE_PACKAGES:=kmod-sun4i-emac kmod-rtc-sunxi kmod-rtl8192cu\n  SOC := sun4i\nendef\nTARGET_DEVICES += linksprite_a10-pcduino\n\ndefine Device/marsboard_a10-marsboard\n  DEVICE_VENDOR := HAOYU Electronics\n  DEVICE_MODEL := MarsBoard A10\n  DEVICE_PACKAGES:=kmod-ata-core kmod-ata-sunxi kmod-sun4i-emac kmod-rtc-sunxi \\\n\tsound-soc-sunxi\n  SOC := sun4i\nendef\nTARGET_DEVICES += marsboard_a10-marsboard\n\ndefine Device/olimex_a10-olinuxino-lime\n  DEVICE_VENDOR := Olimex\n  DEVICE_MODEL := A10-OLinuXino-LIME\n  DEVICE_PACKAGES:=kmod-ata-sunxi kmod-sun4i-emac kmod-rtc-sunxi\n  SOC := sun4i\nendef\nTARGET_DEVICES += olimex_a10-olinuxino-lime\n\ndefine Device/olimex_a13-olimex-som\n  DEVICE_VENDOR := Olimex\n  DEVICE_MODEL := A13-SOM\n  DEVICE_PACKAGES:=kmod-rtl8192cu\n  SUPPORTED_DEVICES:=olimex,a13-olinuxino\n  SOC := sun5i-a13\n  SUNXI_DTS := sun5i-a13-olinuxino\nendef\nTARGET_DEVICES += olimex_a13-olimex-som\n\ndefine Device/olimex_a13-olinuxino\n  DEVICE_VENDOR := Olimex\n  DEVICE_MODEL := A13-OLinuXino\n  DEVICE_PACKAGES:=kmod-rtl8192cu\n  SOC := sun5i\nendef\nTARGET_DEVICES += olimex_a13-olinuxino\n"
  },
  {
    "path": "target/linux/sunxi/image/gen_sunxi_sdcard_img.sh",
    "content": "#!/bin/sh\n# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2013 OpenWrt.org\n\nset -ex\n[ $# -eq 6 ] || {\n    echo \"SYNTAX: $0 <file> <bootfs image> <rootfs image> <bootfs size> <rootfs size> <u-boot image>\"\n    exit 1\n}\n\nOUTPUT=\"$1\"\nBOOTFS=\"$2\"\nROOTFS=\"$3\"\nBOOTFSSIZE=\"$4\"\nROOTFSSIZE=\"$5\"\nUBOOT=\"$6\"\n\nhead=4\nsect=63\n\nset $(ptgen -o $OUTPUT -h $head -s $sect -l 1024 -t c -p ${BOOTFSSIZE}M -t 83 -p ${ROOTFSSIZE}M)\n\nBOOTOFFSET=\"$(($1 / 512))\"\nBOOTSIZE=\"$(($2 / 512))\"\nROOTFSOFFSET=\"$(($3 / 512))\"\nROOTFSSIZE=\"$(($4 / 512))\"\n\ndd bs=1024 if=\"$UBOOT\" of=\"$OUTPUT\" seek=8 conv=notrunc\ndd bs=512 if=\"$BOOTFS\" of=\"$OUTPUT\" seek=\"$BOOTOFFSET\" conv=notrunc\ndd bs=512 if=\"$ROOTFS\" of=\"$OUTPUT\" seek=\"$ROOTFSOFFSET\" conv=notrunc\n"
  },
  {
    "path": "target/linux/sunxi/modules.mk",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2013-2016 OpenWrt.org\n\ndefine KernelPackage/rtc-sunxi\n    SUBMENU:=$(OTHER_MENU)\n    TITLE:=Sunxi SoC built-in RTC support\n    DEPENDS:=@TARGET_sunxi\n    $(call AddDepends/rtc)\n    KCONFIG:= \\\n\tCONFIG_RTC_DRV_SUNXI \\\n\tCONFIG_RTC_CLASS=y\n    FILES:=$(LINUX_DIR)/drivers/rtc/rtc-sunxi.ko\n    AUTOLOAD:=$(call AutoLoad,50,rtc-sunxi)\nendef\n\ndefine KernelPackage/rtc-sunxi/description\n Support for the AllWinner sunXi SoC's onboard RTC\nendef\n\n$(eval $(call KernelPackage,rtc-sunxi))\n\ndefine KernelPackage/sunxi-ir\n    SUBMENU:=$(OTHER_MENU)\n    TITLE:=Sunxi SoC built-in IR support (A20)\n    DEPENDS:=@TARGET_sunxi +kmod-input-core\n    $(call AddDepends/rtc)\n    KCONFIG:= \\\n\tCONFIG_MEDIA_SUPPORT=y \\\n\tCONFIG_MEDIA_RC_SUPPORT=y \\\n\tCONFIG_RC_DEVICES=y \\\n\tCONFIG_IR_SUNXI\n    FILES:=$(LINUX_DIR)/drivers/media/rc/sunxi-cir.ko\n    AUTOLOAD:=$(call AutoLoad,50,sunxi-cir)\nendef\n\ndefine KernelPackage/sunxi-ir/description\n Support for the AllWinner sunXi SoC's onboard IR (A20)\nendef\n\n$(eval $(call KernelPackage,sunxi-ir))\n\ndefine KernelPackage/ata-sunxi\n    TITLE:=AllWinner sunXi AHCI SATA support\n    SUBMENU:=$(BLOCK_MENU)\n    DEPENDS:=@TARGET_sunxi +kmod-ata-ahci-platform +kmod-scsi-core\n    KCONFIG:=CONFIG_AHCI_SUNXI\n    FILES:=$(LINUX_DIR)/drivers/ata/ahci_sunxi.ko\n    AUTOLOAD:=$(call AutoLoad,41,ahci_sunxi,1)\nendef\n\ndefine KernelPackage/ata-sunxi/description\n SATA support for the AllWinner sunXi SoC's onboard AHCI SATA\nendef\n\n$(eval $(call KernelPackage,ata-sunxi))\n\ndefine KernelPackage/sun4i-emac\n  SUBMENU:=$(NETWORK_DEVICES_MENU)\n  TITLE:=AllWinner EMAC Ethernet support\n  DEPENDS:=@TARGET_sunxi +kmod-of-mdio +kmod-libphy\n  KCONFIG:=CONFIG_SUN4I_EMAC\n  FILES:=$(LINUX_DIR)/drivers/net/ethernet/allwinner/sun4i-emac.ko\n  AUTOLOAD:=$(call AutoProbe,sun4i-emac)\nendef\n\n$(eval $(call KernelPackage,sun4i-emac))\n\ndefine KernelPackage/sound-soc-sunxi\n  TITLE:=AllWinner built-in SoC sound support\n  KCONFIG:=CONFIG_SND_SUN4I_CODEC\n  FILES:=$(LINUX_DIR)/sound/soc/sunxi/sun4i-codec.ko\n  AUTOLOAD:=$(call AutoLoad,65,sun4i-codec)\n  DEPENDS:=@TARGET_sunxi +kmod-sound-soc-core\n  $(call AddDepends/sound)\nendef\n\ndefine KernelPackage/sound-soc-sunxi/description\n  Kernel support for AllWinner built-in SoC audio\nendef\n\n$(eval $(call KernelPackage,sound-soc-sunxi))\n\ndefine KernelPackage/sound-soc-sunxi-spdif\n  TITLE:=Allwinner A10 SPDIF Support\n  KCONFIG:=CONFIG_SND_SUN4I_SPDIF\n  FILES:=$(LINUX_DIR)/sound/soc/sunxi/sun4i-spdif.ko\n  AUTOLOAD:=$(call AutoLoad,65,sun4i-spdif)\n  DEPENDS:=@TARGET_sunxi +kmod-sound-soc-spdif\n  $(call AddDepends/sound)\nendef\n\ndefine KernelPackage/sound-soc-sunxi-spdif/description\n  Kernel support for Allwinner A10 SPDIF Support\nendef\n\n$(eval $(call KernelPackage,sound-soc-sunxi-spdif))\n"
  },
  {
    "path": "target/linux/sunxi/patches-5.10/062-add-sun8i-h3-zeropi-support.patch",
    "content": "--- a/arch/arm/boot/dts/Makefile\n+++ b/arch/arm/boot/dts/Makefile\n@@ -1203,6 +1203,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \\\n \tsun8i-h3-orangepi-zero-plus2.dtb \\\n \tsun8i-h3-rervision-dvk.dtb \\\n \tsun8i-h3-emlid-neutis-n5h3-devboard.dtb \\\n+\tsun8i-h3-zeropi.dtb \\\n \tsun8i-r16-bananapi-m2m.dtb \\\n \tsun8i-r16-nintendo-nes-classic.dtb \\\n \tsun8i-r16-nintendo-super-nes-classic.dtb \\\n--- /dev/null\n+++ b/arch/arm/boot/dts/sun8i-h3-zeropi.dts\n@@ -0,0 +1,66 @@\n+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)\n+\n+#include \"sun8i-h3-nanopi.dtsi\"\n+\n+/ {\n+\tmodel = \"FriendlyElec ZeroPi\";\n+\tcompatible = \"friendlyarm,zeropi\", \"allwinner,sun8i-h3\";\n+\n+\taliases {\n+\t\tethernet0 = &emac;\n+\t};\n+\n+\treg_gmac_3v3: gmac-3v3 {\n+\t\tcompatible = \"regulator-fixed\";\n+\t\tpinctrl-names = \"default\";\n+\t\tpinctrl-0 = <&gmac_power_pin_nanopi>;\n+\t\tregulator-name = \"gmac-3v3\";\n+\t\tregulator-min-microvolt = <3300000>;\n+\t\tregulator-max-microvolt = <3300000>;\n+\t\tstartup-delay-us = <100000>;\n+\t\tenable-active-high;\n+\t\tgpio = <&pio 3 6 GPIO_ACTIVE_HIGH>;\n+\t};\n+};\n+\n+&ehci0 {\n+\tstatus = \"okay\";\n+};\n+\n+&ohci0 {\n+\tstatus = \"okay\";\n+};\n+\n+&pio {\n+\tgmac_power_pin_nanopi: gmac_power_pin@0 {\n+\t\tpins = \"PD6\";\n+\t\tfunction = \"gpio_out\";\n+\t};\n+};\n+\n+&external_mdio {\n+\text_rgmii_phy: ethernet-phy@1 {\n+\t\tcompatible = \"ethernet-phy-ieee802.3-c22\";\n+\t\treg = <7>;\n+\t};\n+};\n+\n+&emac {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&emac_rgmii_pins>;\n+\tphy-supply = <&reg_gmac_3v3>;\n+\tphy-handle = <&ext_rgmii_phy>;\n+\tphy-mode = \"rgmii\";\n+\n+\tallwinner,leds-active-low;\n+\tstatus = \"okay\";\n+};\n+\n+&usb_otg {\n+\tstatus = \"okay\";\n+\tdr_mode = \"peripheral\";\n+};\n+\n+&usbphy {\n+\tusb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */\n+};\n"
  },
  {
    "path": "target/linux/sunxi/patches-5.10/100-sunxi-h3-add-support-for-nanopi-r1.patch",
    "content": "From 5aee0b1272cd5b42933ef629d66b677669e2e8d2 Mon Sep 17 00:00:00 2001\nFrom: Jayantajit Gogoi <jayanta.gogoi525@gmail.com>\nDate: Mon, 12 Oct 2020 05:24:51 +0000\nSubject: [PATCH] sunxi: add support for friendlyarm nanopi r1\n\nSigned-off-by: Jayantajit Gogoi <jayanta.gogoi525@gmail.com>\n---\n .../devicetree/bindings/arm/sunxi.yaml        |   5 +\n arch/arm/boot/dts/Makefile                    |   1 +\n arch/arm/boot/dts/sun8i-h3-nanopi-r1.dts      | 146 ++++++++++++++++++\n 3 files changed, 152 insertions(+)\n create mode 100644 arch/arm/boot/dts/sun8i-h3-nanopi-r1.dts\n\n--- a/Documentation/devicetree/bindings/arm/sunxi.yaml\n+++ b/Documentation/devicetree/bindings/arm/sunxi.yaml\n@@ -251,6 +251,11 @@ properties:\n           - const: friendlyarm,nanopi-neo-plus2\n           - const: allwinner,sun50i-h5\n \n+      - description: FriendlyARM NanoPi R1\n+        items:\n+          - const: friendlyarm,nanopi-r1\n+          - const: allwinner,sun8i-h3\n+\n       - description: Gemei G9 Tablet\n         items:\n           - const: gemei,g9\n--- a/arch/arm/boot/dts/Makefile\n+++ b/arch/arm/boot/dts/Makefile\n@@ -1193,6 +1193,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \\\n \tsun8i-h3-nanopi-m1-plus.dtb \\\n \tsun8i-h3-nanopi-neo.dtb \\\n \tsun8i-h3-nanopi-neo-air.dtb \\\n+\tsun8i-h3-nanopi-r1.dtb \\\n \tsun8i-h3-orangepi-2.dtb \\\n \tsun8i-h3-orangepi-lite.dtb \\\n \tsun8i-h3-orangepi-one.dtb \\\n--- /dev/null\n+++ b/arch/arm/boot/dts/sun8i-h3-nanopi-r1.dts\n@@ -0,0 +1,146 @@\n+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)\n+/*\n+ * Copyright (C) 2019 Igor Pecovnik <igor@armbian.com>\n+ * Copyright (C) 2020 Jayantajit Gogoi <jayanta.gogoi525@gmail.com>\n+ */\n+\n+/* NanoPi R1 is based on the NanoPi-H3 design from FriendlyARM */\n+#include \"sun8i-h3-nanopi.dtsi\"\n+\n+/ {\n+\tmodel = \"FriendlyARM NanoPi R1\";\n+\tcompatible = \"friendlyarm,nanopi-r1\", \"allwinner,sun8i-h3\";\n+\n+\treg_gmac_3v3: gmac-3v3 {\n+\t\tcompatible = \"regulator-fixed\";\n+\t\tregulator-name = \"gmac-3v3\";\n+\t\tregulator-min-microvolt = <3300000>;\n+\t\tregulator-max-microvolt = <3300000>;\n+\t\tstartup-delay-us = <100000>;\n+\t\tenable-active-high;\n+\t\tgpio = <&pio 3 6 GPIO_ACTIVE_HIGH>;\n+\t};\n+\n+\tvdd_cpux: gpio-regulator {\n+\t\tcompatible = \"regulator-gpio\";\n+\t\tpinctrl-names = \"default\";\n+\t\tregulator-name = \"vdd-cpux\";\n+\t\tregulator-type = \"voltage\";\n+\t\tregulator-boot-on;\n+\t\tregulator-always-on;\n+\t\tregulator-min-microvolt = <1100000>;\n+\t\tregulator-max-microvolt = <1300000>;\n+\t\tregulator-ramp-delay = <50>;\n+\t\tgpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>;\n+\t\tgpios-states = <0x1>;\n+\t\tstates = <1100000 0x0\n+\t\t\t  1300000 0x1>;\n+\t};\n+\n+\twifi_pwrseq: wifi_pwrseq {\n+\t\tcompatible = \"mmc-pwrseq-simple\";\n+\t\tpinctrl-names = \"default\";\n+\t\treset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>;\n+\t};\n+\n+\tleds {\n+\t\t/delete-node/ pwr;\n+\t\tstatus {\n+\t\t\tlabel = \"nanopi:red:status\";\n+\t\t\tgpios = <&pio 0 10 GPIO_ACTIVE_HIGH>;\n+\t\t\tlinux,default-trigger = \"heartbeat\";\n+\t\t};\n+\n+\t\twan {\n+\t\t\tlabel = \"nanopi:green:wan\";\n+\t\t\tgpios = <&pio 6 11 GPIO_ACTIVE_HIGH>;\n+\t\t};\n+\n+\t\tlan {\n+\t\t\tlabel = \"nanopi:green:lan\";\n+\t\t\tgpios = <&pio 0 9 GPIO_ACTIVE_HIGH>;\n+\t\t};\n+\t};\n+\n+\tr_gpio_keys {\n+\t\tpinctrl-names = \"default\";\n+\t\tpinctrl-0 = <&sw_r_npi>;\n+\n+\t\t/delete-node/ k1;\n+\t\treset {\n+\t\t\tlabel = \"reset\";\n+\t\t\tlinux,code = <KEY_RESTART>;\n+\t\t\tgpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\t};\n+};\n+\n+&cpu0 {\n+\tcpu-supply = <&vdd_cpux>;\n+};\n+\n+&ehci1 {\n+\tstatus = \"okay\";\n+};\n+\n+&ehci2 {\n+\tstatus = \"okay\";\n+};\n+\n+&emac {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&emac_rgmii_pins>;\n+\tphy-supply = <&reg_gmac_3v3>;\n+\tphy-handle = <&ext_rgmii_phy>;\n+\tphy-mode = \"rgmii\";\n+\tstatus = \"okay\";\n+};\n+\n+&external_mdio {\n+\text_rgmii_phy: ethernet-phy@1 {\n+\t\tcompatible = \"ethernet-phy-ieee802.3-c22\";\n+\t\treg = <7>;\n+\t};\n+};\n+\n+&mmc1 {\n+\tvmmc-supply = <&reg_vcc3v3>;\n+\tvqmmc-supply = <&reg_vcc3v3>;\n+\tmmc-pwrseq = <&wifi_pwrseq>;\n+\tbus-width = <4>;\n+\tnon-removable;\n+\tstatus = \"okay\";\n+\n+\tsdio_wifi: sdio_wifi@1 {\n+\t\treg = <1>;\n+\t\tcompatible = \"brcm,bcm4329-fmac\";\n+\t\tinterrupt-parent = <&pio>;\n+\t\tinterrupts = <6 10 IRQ_TYPE_LEVEL_LOW>;\n+\t\tinterrupt-names = \"host-wake\";\n+\t};\n+};\n+\n+&mmc2 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&mmc2_8bit_pins>;\n+\tvmmc-supply = <&reg_vcc3v3>;\n+\tvqmmc-supply = <&reg_vcc3v3>;\n+\tbus-width = <8>;\n+\tnon-removable;\n+\tstatus = \"okay\";\n+};\n+\n+&ohci1 {\n+\tstatus = \"okay\";\n+};\n+\n+&ohci2 {\n+\tstatus = \"okay\";\n+};\n+\n+&r_pio {\n+\tsw_r_npi: key_pins {\n+\t\tpins = \"PL3\";\n+\t\tfunction = \"gpio_in\";\n+\t};\n+};\n"
  },
  {
    "path": "target/linux/sunxi/patches-5.10/101-sunxi-h5-add-support-for-nanopi-r1s-h5.patch",
    "content": "From 9962cb9be2db877c232aaf00db40125c0d7bf4bc Mon Sep 17 00:00:00 2001\nFrom: Chukun Pan <amadeus@jmu.edu.cn>\nDate: Mon, 17 May 2021 00:35:22 +0800\nSubject: [PATCH] arm64: dts: allwinner: h5: Add NanoPi R1S H5 support\n\nThe NanoPi R1S H5 is a open source board made by FriendlyElec.\nIt has the following features:\n\n- Allwinner H5, Quad-core Cortex-A53\n- 512MB DDR3 RAM\n- 10/100/1000M Ethernet x 2\n- RTL8189ETV WiFi 802.11b/g/n\n- USB 2.0 host port (A)\n- MicroSD Slot\n- Serial Debug Port\n- 5V 2A DC power-supply\n\nSigned-off-by: Chukun Pan <amadeus@jmu.edu.cn>\nSigned-off-by: Maxime Ripard <maxime@cerno.tech>\nLink: https://lore.kernel.org/r/20210516163523.9484-2-amadeus@jmu.edu.cn\n---\n arch/arm64/boot/dts/allwinner/Makefile        |   1 +\n .../dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts | 195 ++++++++++++++++++\n 2 files changed, 196 insertions(+)\n create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts\n\n--- a/arch/arm64/boot/dts/allwinner/Makefile\n+++ b/arch/arm64/boot/dts/allwinner/Makefile\n@@ -24,6 +24,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-li\n dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-libretech-all-h5-cc.dtb\n dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-neo2.dtb\n dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-neo-plus2.dtb\n+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-r1s-h5.dtb\n dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-pc2.dtb\n dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-prime.dtb\n dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-zero-plus.dtb\n--- /dev/null\n+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts\n@@ -0,0 +1,191 @@\n+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)\n+/*\n+ * Copyright (C) 2021 Chukun Pan <amadeus@jmu.edu.cn>\n+ *\n+ * Based on sun50i-h5-nanopi-neo-plus2.dts, which is:\n+ *   Copyright (C) 2017 Antony Antony <antony@phenome.org>\n+ *   Copyright (C) 2016 ARM Ltd.\n+ */\n+\n+/dts-v1/;\n+#include \"sun50i-h5.dtsi\"\n+#include \"sun50i-h5-cpu-opp.dtsi\"\n+\n+#include <dt-bindings/gpio/gpio.h>\n+#include <dt-bindings/input/input.h>\n+\n+/ {\n+\tmodel = \"FriendlyARM NanoPi R1S H5\";\n+\tcompatible = \"friendlyarm,nanopi-r1s-h5\", \"allwinner,sun50i-h5\";\n+\n+\taliases {\n+\t\tethernet0 = &emac;\n+\t\tethernet1 = &rtl8189etv;\n+\t\tserial0 = &uart0;\n+\t};\n+\n+\tchosen {\n+\t\tstdout-path = \"serial0:115200n8\";\n+\t};\n+\n+\tleds {\n+\t\tcompatible = \"gpio-leds\";\n+\n+\t\tsys {\n+\t\t\tlabel = \"nanopi:red:sys\";\n+\t\t\tgpios = <&pio 0 10 GPIO_ACTIVE_HIGH>;\n+\t\t\tlinux,default-trigger = \"heartbeat\";\n+\t\t};\n+\n+\t\tlan {\n+\t\t\tlabel = \"nanopi:green:lan\";\n+\t\t\tgpios = <&pio 0 9 GPIO_ACTIVE_HIGH>;\n+\t\t};\n+\n+\t\twan {\n+\t\t\tlabel = \"nanopi:green:wan\";\n+\t\t\tgpios = <&pio 6 11 GPIO_ACTIVE_HIGH>;\n+\t\t};\n+\t};\n+\n+\tr-gpio-keys {\n+\t\tcompatible = \"gpio-keys\";\n+\n+\t\treset {\n+\t\t\tlabel = \"reset\";\n+\t\t\tlinux,code = <KEY_RESTART>;\n+\t\t\tgpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\t};\n+\n+\treg_gmac_3v3: gmac-3v3 {\n+\t\tcompatible = \"regulator-fixed\";\n+\t\tregulator-name = \"gmac-3v3\";\n+\t\tregulator-min-microvolt = <3300000>;\n+\t\tregulator-max-microvolt = <3300000>;\n+\t\tstartup-delay-us = <100000>;\n+\t\tenable-active-high;\n+\t\tgpio = <&pio 3 6 GPIO_ACTIVE_HIGH>;\n+\t};\n+\n+\treg_vcc3v3: vcc3v3 {\n+\t\tcompatible = \"regulator-fixed\";\n+\t\tregulator-name = \"vcc3v3\";\n+\t\tregulator-min-microvolt = <3300000>;\n+\t\tregulator-max-microvolt = <3300000>;\n+\t};\n+\n+\treg_usb0_vbus: usb0-vbus {\n+\t\tcompatible = \"regulator-fixed\";\n+\t\tregulator-name = \"usb0-vbus\";\n+\t\tregulator-min-microvolt = <5000000>;\n+\t\tregulator-max-microvolt = <5000000>;\n+\t\tenable-active-high;\n+\t\tgpio = <&r_pio 0 2 GPIO_ACTIVE_HIGH>; /* PL2 */\n+\t\tstatus = \"okay\";\n+\t};\n+\n+\tvdd_cpux: gpio-regulator {\n+\t\tcompatible = \"regulator-gpio\";\n+\t\tregulator-name = \"vdd-cpux\";\n+\t\tregulator-type = \"voltage\";\n+\t\tregulator-boot-on;\n+\t\tregulator-always-on;\n+\t\tregulator-min-microvolt = <1100000>;\n+\t\tregulator-max-microvolt = <1300000>;\n+\t\tregulator-ramp-delay = <50>; /* 4ms */\n+\t\tgpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>;\n+\t\tgpios-states = <0x1>;\n+\t\tstates = <1100000 0x0>, <1300000 0x1>;\n+\t};\n+\n+\twifi_pwrseq: wifi_pwrseq {\n+\t\tcompatible = \"mmc-pwrseq-simple\";\n+\t\treset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */\n+\t\tpost-power-on-delay-ms = <200>;\n+\t};\n+};\n+\n+&cpu0 {\n+\tcpu-supply = <&vdd_cpux>;\n+};\n+\n+&ehci1 {\n+\tstatus = \"okay\";\n+};\n+\n+&ehci2 {\n+\tstatus = \"okay\";\n+};\n+\n+&emac {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&emac_rgmii_pins>;\n+\tphy-supply = <&reg_gmac_3v3>;\n+\tphy-handle = <&ext_rgmii_phy>;\n+\tphy-mode = \"rgmii-id\";\n+\tstatus = \"okay\";\n+};\n+\n+&external_mdio {\n+\text_rgmii_phy: ethernet-phy@7 {\n+\t\tcompatible = \"ethernet-phy-ieee802.3-c22\";\n+\t\treg = <7>;\n+\t};\n+};\n+\n+&i2c0 {\n+\tstatus = \"okay\";\n+\n+\teeprom@51 {\n+\t\tcompatible = \"microchip,24c02\";\n+\t\treg = <0x51>;\n+\t\tpagesize = <16>;\n+\t};\n+};\n+\n+&mmc0 {\n+\tvmmc-supply = <&reg_vcc3v3>;\n+\tbus-width = <4>;\n+\tcd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */\n+\tstatus = \"okay\";\n+};\n+\n+&mmc1 {\n+\tvmmc-supply = <&reg_vcc3v3>;\n+\tvqmmc-supply = <&reg_vcc3v3>;\n+\tmmc-pwrseq = <&wifi_pwrseq>;\n+\tbus-width = <4>;\n+\tnon-removable;\n+\tstatus = \"okay\";\n+\n+\trtl8189etv: sdio_wifi@1 {\n+\t\treg = <1>;\n+\t};\n+};\n+\n+&ohci1 {\n+\tstatus = \"okay\";\n+};\n+\n+&ohci2 {\n+\tstatus = \"okay\";\n+};\n+\n+&uart0 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&uart0_pa_pins>;\n+\tstatus = \"okay\";\n+};\n+\n+&usb_otg {\n+\tdr_mode = \"peripheral\";\n+\tstatus = \"okay\";\n+};\n+\n+&usbphy {\n+\t/* USB Type-A port's VBUS is always on */\n+\tusb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */\n+\tusb0_vbus-supply = <&reg_usb0_vbus>;\n+\tstatus = \"okay\";\n+};\n"
  },
  {
    "path": "target/linux/sunxi/patches-5.10/102-sunxi-add-OF-node-for-USB-eth-on-NanoPi-R1S-H5.patch",
    "content": "From a896bc1d79e3c00f0aacfe225499d811775616f3 Mon Sep 17 00:00:00 2001\nFrom: Chukun Pan <amadeus@jmu.edu.cn>\nDate: Sun, 10 Oct 2021 21:50:17 +0800\nSubject: [PATCH] arm64: allwinner: add OF node for USB eth on NanoPi R1S H5\n\nThis adds the OF node for the USB3 ethernet adapter on the FriendlyARM\nNanoPi R1S H5. Add the correct value for the RTL8153 LED configuration\nregister to match the blink behavior of the other port on the device.\n\nSigned-off-by: Chukun Pan <amadeus@jmu.edu.cn>\n---\n arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts | 7 +++++++\n 1 file changed, 7 insertions(+)\n\n--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts\n+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts\n@@ -112,6 +112,13 @@\n \n &ehci1 {\n \tstatus = \"okay\";\n+\n+\tusb-eth@1 {\n+\t\tcompatible = \"realtek,rtl8153\";\n+\t\treg = <1>;\n+\n+\t\trealtek,led-data = <0x78>;\n+\t};\n };\n \n &ehci2 {\n"
  },
  {
    "path": "target/linux/sunxi/patches-5.10/301-orangepi_pc2_usb_otg_to_host_key_power.patch",
    "content": "--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts\n+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts\n@@ -59,7 +59,7 @@\n \n \t\tsw4 {\n \t\t\tlabel = \"sw4\";\n-\t\t\tlinux,code = <BTN_0>;\n+\t\t\tlinux,code = <KEY_POWER>;\n \t\t\tgpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;\n \t\t\twakeup-source;\n \t\t};\n@@ -220,7 +220,7 @@\n };\n \n &usb_otg {\n-\tdr_mode = \"otg\";\n+\tdr_mode = \"host\";\n \tstatus = \"okay\";\n };\n \n"
  },
  {
    "path": "target/linux/sunxi/patches-5.10/400-arm64-allwinner-a64-sopine-Add-Sopine-flash-partitio.patch",
    "content": "From 7d87d3dafc4b1ea5659eb71ee6c5fd5308490d1f Mon Sep 17 00:00:00 2001\nFrom: Oskari Lemmela <oskari@lemmela.net>\nDate: Mon, 31 Dec 2018 07:44:49 +0200\nSubject: [PATCH] arm64: allwinner: a64-sopine: Add Sopine flash partitions.\n\nFirst 896kB to u-boot. Enough space for SPL, u-boot and ATF.\nNext 128kB to u-boot environment and rest to firmware.\n\nFirmware partition is compatible FIT image dynamic splitting.\n\nSigned-off-by: Oskari Lemmela <oskari@lemmela.net>\n---\n .../boot/dts/allwinner/sun50i-a64-sopine.dtsi | 22 +++++++++++++++++++\n 1 file changed, 22 insertions(+)\n\n--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi\n+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi\n@@ -58,6 +58,28 @@\n \t\tcompatible = \"jedec,spi-nor\";\n \t\treg = <0>;\n \t\tspi-max-frequency = <40000000>;\n+\n+\t\tpartitions {\n+\t\t\tcompatible = \"fixed-partitions\";\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <1>;\n+\n+\t\t\tpartition@0 {\n+\t\t\t\tlabel = \"u-boot\";\n+\t\t\t\treg = <0x000000 0x0E0000>;\n+\t\t\t};\n+\n+\t\t\tpartition@e0000 {\n+\t\t\t\tlabel = \"u-boot-env\";\n+\t\t\t\treg = <0x0E0000 0x020000>;\n+\t\t\t};\n+\n+\t\t\tpartition@100000 {\n+\t\t\t\tcompatible = \"denx,fit\";\n+\t\t\t\tlabel = \"firmware\";\n+\t\t\t\treg = <0x100000 0xF00000>;\n+\t\t\t};\n+\t\t};\n \t};\n };\n \n"
  },
  {
    "path": "target/linux/sunxi/patches-5.10/430-arm64-dts-allwinner-a64-olinuxino-add-status-LED-ali.patch",
    "content": "From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Petr=20=C5=A0tetiar?= <ynezz@true.cz>\nDate: Thu, 26 Mar 2020 10:09:19 +0100\nSubject: [PATCH] arm64: dts: allwinner: a64: olinuxino: add status LED aliases\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nSigned-off-by: Petr Štetiar <ynezz@true.cz>\n\n--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts\n+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts\n@@ -15,6 +15,10 @@\n \taliases {\n \t\tethernet0 = &emac;\n \t\tserial0 = &uart0;\n+\t\tled-boot = &led_user;\n+\t\tled-failsafe = &led_user;\n+\t\tled-running = &led_user;\n+\t\tled-upgrade = &led_user;\n \t};\n \n \tchosen {\n@@ -35,7 +39,7 @@\n \tleds {\n \t\tcompatible = \"gpio-leds\";\n \n-\t\tled-0 {\n+\t\tled_user: led-0 {\n \t\t\tlabel = \"a64-olinuxino:red:user\";\n \t\t\tgpios = <&pio 4 17 GPIO_ACTIVE_HIGH>; /* PE17 */\n \t\t};\n"
  },
  {
    "path": "target/linux/sunxi/patches-5.10/431-arm64-dts-allwinner-nanopi-r1s-h5-add-status-LED.patch",
    "content": "From 1845163a052efac124f00656eb72f38947630a42 Mon Sep 17 00:00:00 2001\nFrom: Chukun Pan <amadeus@jmu.edu.cn>\nDate: Sun, 10 Oct 2021 21:50:18 +0800\nSubject: [PATCH] arm64: dts: allwinner: NanoPi R1S H5: add status LED aliases\n\nUse the SYS LED on the casing for showing system status.\n\nSigned-off-by: Chukun Pan <amadeus@jmu.edu.cn>\n---\n arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts | 7 ++++++-\n 1 file changed, 6 insertions(+), 1 deletion(-)\n\n--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts\n+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts\n@@ -22,6 +22,11 @@\n \t\tethernet0 = &emac;\n \t\tethernet1 = &rtl8189etv;\n \t\tserial0 = &uart0;\n+\n+\t\tled-boot = &led_sys;\n+\t\tled-failsafe = &led_sys;\n+\t\tled-running = &led_sys;\n+\t\tled-upgrade = &led_sys;\n \t};\n \n \tchosen {\n@@ -31,7 +36,7 @@\n \tleds {\n \t\tcompatible = \"gpio-leds\";\n \n-\t\tsys {\n+\t\tled_sys: sys {\n \t\t\tlabel = \"nanopi:red:sys\";\n \t\t\tgpios = <&pio 0 10 GPIO_ACTIVE_HIGH>;\n \t\t\tlinux,default-trigger = \"heartbeat\";\n"
  },
  {
    "path": "target/linux/sunxi/patches-5.10/442-arm64-dts-orangepi-one-plus-enable-PWM.patch",
    "content": "--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-one-plus.dts\n+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-one-plus.dts\n@@ -41,3 +41,7 @@\n \t\treg = <1>;\n \t};\n };\n+\n+&pwm {\n+\tstatus = \"okay\";\n+};\n"
  },
  {
    "path": "target/linux/sunxi/patches-5.10/450-arm64-dts-enable-wifi-on-pine64-boards.patch",
    "content": "--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts\n+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts\n@@ -42,6 +42,11 @@\n \t\tregulator-min-microvolt = <1800000>;\n \t\tregulator-max-microvolt = <1800000>;\n \t};\n+\n+\twifi_pwrseq: wifi_pwrseq {\n+\t\tcompatible = \"mmc-pwrseq-simple\";\n+\t\treset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */\n+\t};\n };\n \n &ac_power_supply {\n@@ -102,6 +107,21 @@\n \t\treg = <1>;\n \t};\n };\n+\n+&mmc1 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&mmc1_pins>;\n+\tvmmc-supply = <&reg_dldo4>;\n+\tvqmmc-supply = <&reg_eldo1>;\n+\tmmc-pwrseq = <&wifi_pwrseq>;\n+\tbus-width = <4>;\n+\tnon-removable;\n+\tstatus = \"okay\";\n+\n+\trtl8723cs: wifi@1 {\n+\t\treg = <1>;\n+\t};\n+};\n \n &mmc2 {\n \tpinctrl-names = \"default\";\n--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts\n+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts\n@@ -35,6 +35,11 @@\n \t\t\t};\n \t\t};\n \t};\n+\n+\twifi_pwrseq: wifi_pwrseq {\n+\t\tcompatible = \"mmc-pwrseq-simple\";\n+\t\treset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */\n+\t};\n };\n \n &codec {\n@@ -124,6 +129,21 @@\n \tstatus = \"okay\";\n };\n \n+&mmc1 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&mmc1_pins>;\n+\tvmmc-supply = <&reg_dldo4>;\n+\tvqmmc-supply = <&reg_eldo1>;\n+\tmmc-pwrseq = <&wifi_pwrseq>;\n+\tbus-width = <4>;\n+\tnon-removable;\n+\tstatus = \"okay\";\n+\n+\trtl8723cs: wifi@1 {\n+\t\treg = <1>;\n+\t};\n+};\n+\n &ohci0 {\n \tstatus = \"okay\";\n };\n"
  },
  {
    "path": "target/linux/sunxi/patches-5.15/102-sunxi-add-OF-node-for-USB-eth-on-NanoPi-R1S-H5.patch",
    "content": "From a896bc1d79e3c00f0aacfe225499d811775616f3 Mon Sep 17 00:00:00 2001\nFrom: Chukun Pan <amadeus@jmu.edu.cn>\nDate: Sun, 10 Oct 2021 21:50:17 +0800\nSubject: [PATCH] arm64: allwinner: add OF node for USB eth on NanoPi R1S H5\n\nThis adds the OF node for the USB3 ethernet adapter on the FriendlyARM\nNanoPi R1S H5. Add the correct value for the RTL8153 LED configuration\nregister to match the blink behavior of the other port on the device.\n\nSigned-off-by: Chukun Pan <amadeus@jmu.edu.cn>\n---\n arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts | 7 +++++++\n 1 file changed, 7 insertions(+)\n\n--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts\n+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts\n@@ -116,6 +116,13 @@\n \n &ehci1 {\n \tstatus = \"okay\";\n+\n+\tusb-eth@1 {\n+\t\tcompatible = \"realtek,rtl8153\";\n+\t\treg = <1>;\n+\n+\t\trealtek,led-data = <0x78>;\n+\t};\n };\n \n &ehci2 {\n"
  },
  {
    "path": "target/linux/sunxi/patches-5.15/301-orangepi_pc2_usb_otg_to_host_key_power.patch",
    "content": "--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts\n+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts\n@@ -59,7 +59,7 @@\n \n \t\tsw4 {\n \t\t\tlabel = \"sw4\";\n-\t\t\tlinux,code = <BTN_0>;\n+\t\t\tlinux,code = <KEY_POWER>;\n \t\t\tgpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;\n \t\t\twakeup-source;\n \t\t};\n@@ -220,7 +220,7 @@\n };\n \n &usb_otg {\n-\tdr_mode = \"otg\";\n+\tdr_mode = \"host\";\n \tstatus = \"okay\";\n };\n \n"
  },
  {
    "path": "target/linux/sunxi/patches-5.15/400-arm64-allwinner-a64-sopine-Add-Sopine-flash-partitio.patch",
    "content": "From 7d87d3dafc4b1ea5659eb71ee6c5fd5308490d1f Mon Sep 17 00:00:00 2001\nFrom: Oskari Lemmela <oskari@lemmela.net>\nDate: Mon, 31 Dec 2018 07:44:49 +0200\nSubject: [PATCH] arm64: allwinner: a64-sopine: Add Sopine flash partitions.\n\nFirst 896kB to u-boot. Enough space for SPL, u-boot and ATF.\nNext 128kB to u-boot environment and rest to firmware.\n\nFirmware partition is compatible FIT image dynamic splitting.\n\nSigned-off-by: Oskari Lemmela <oskari@lemmela.net>\n---\n .../boot/dts/allwinner/sun50i-a64-sopine.dtsi | 22 +++++++++++++++++++\n 1 file changed, 22 insertions(+)\n\n--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi\n+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi\n@@ -58,6 +58,28 @@\n \t\tcompatible = \"jedec,spi-nor\";\n \t\treg = <0>;\n \t\tspi-max-frequency = <40000000>;\n+\n+\t\tpartitions {\n+\t\t\tcompatible = \"fixed-partitions\";\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <1>;\n+\n+\t\t\tpartition@0 {\n+\t\t\t\tlabel = \"u-boot\";\n+\t\t\t\treg = <0x000000 0x0E0000>;\n+\t\t\t};\n+\n+\t\t\tpartition@e0000 {\n+\t\t\t\tlabel = \"u-boot-env\";\n+\t\t\t\treg = <0x0E0000 0x020000>;\n+\t\t\t};\n+\n+\t\t\tpartition@100000 {\n+\t\t\t\tcompatible = \"denx,fit\";\n+\t\t\t\tlabel = \"firmware\";\n+\t\t\t\treg = <0x100000 0xF00000>;\n+\t\t\t};\n+\t\t};\n \t};\n };\n \n"
  },
  {
    "path": "target/linux/sunxi/patches-5.15/430-arm64-dts-allwinner-a64-olinuxino-add-status-LED-ali.patch",
    "content": "From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Petr=20=C5=A0tetiar?= <ynezz@true.cz>\nDate: Thu, 26 Mar 2020 10:09:19 +0100\nSubject: [PATCH] arm64: dts: allwinner: a64: olinuxino: add status LED aliases\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nSigned-off-by: Petr Štetiar <ynezz@true.cz>\n\n--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts\n+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts\n@@ -15,6 +15,10 @@\n \taliases {\n \t\tethernet0 = &emac;\n \t\tserial0 = &uart0;\n+\t\tled-boot = &led_user;\n+\t\tled-failsafe = &led_user;\n+\t\tled-running = &led_user;\n+\t\tled-upgrade = &led_user;\n \t};\n \n \tchosen {\n@@ -35,7 +39,7 @@\n \tleds {\n \t\tcompatible = \"gpio-leds\";\n \n-\t\tled-0 {\n+\t\tled_user: led-0 {\n \t\t\tlabel = \"a64-olinuxino:red:user\";\n \t\t\tgpios = <&pio 4 17 GPIO_ACTIVE_HIGH>; /* PE17 */\n \t\t};\n"
  },
  {
    "path": "target/linux/sunxi/patches-5.15/431-arm64-dts-allwinner-nanopi-r1s-h5-add-status-LED.patch",
    "content": "From 1845163a052efac124f00656eb72f38947630a42 Mon Sep 17 00:00:00 2001\nFrom: Chukun Pan <amadeus@jmu.edu.cn>\nDate: Sun, 10 Oct 2021 21:50:18 +0800\nSubject: [PATCH] arm64: dts: allwinner: NanoPi R1S H5: add status LED aliases\n\nUse the SYS LED on the casing for showing system status.\n\nSigned-off-by: Chukun Pan <amadeus@jmu.edu.cn>\n---\n arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts | 7 ++++++-\n 1 file changed, 6 insertions(+), 1 deletion(-)\n\n--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts\n+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts\n@@ -23,6 +23,11 @@\n \t\tethernet0 = &emac;\n \t\tethernet1 = &rtl8189etv;\n \t\tserial0 = &uart0;\n+\n+\t\tled-boot = &led_sys;\n+\t\tled-failsafe = &led_sys;\n+\t\tled-running = &led_sys;\n+\t\tled-upgrade = &led_sys;\n \t};\n \n \tchosen {\n@@ -38,7 +43,7 @@\n \t\t\tgpios = <&pio 0 9 GPIO_ACTIVE_HIGH>;\n \t\t};\n \n-\t\tled-1 {\n+\t\tled_sys: led-1 {\n \t\t\tfunction = LED_FUNCTION_STATUS;\n \t\t\tcolor = <LED_COLOR_ID_RED>;\n \t\t\tgpios = <&pio 0 10 GPIO_ACTIVE_HIGH>;\n"
  },
  {
    "path": "target/linux/sunxi/patches-5.15/442-arm64-dts-orangepi-one-plus-enable-PWM.patch",
    "content": "--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-one-plus.dts\n+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-one-plus.dts\n@@ -41,3 +41,7 @@\n \t\treg = <1>;\n \t};\n };\n+\n+&pwm {\n+\tstatus = \"okay\";\n+};\n"
  },
  {
    "path": "target/linux/sunxi/patches-5.15/450-arm64-dts-enable-wifi-on-pine64-boards.patch",
    "content": "--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts\n+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts\n@@ -42,6 +42,11 @@\n \t\tregulator-min-microvolt = <1800000>;\n \t\tregulator-max-microvolt = <1800000>;\n \t};\n+\n+\twifi_pwrseq: wifi_pwrseq {\n+\t\tcompatible = \"mmc-pwrseq-simple\";\n+\t\treset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */\n+\t};\n };\n \n &ac_power_supply {\n@@ -102,6 +107,21 @@\n \t\treg = <1>;\n \t};\n };\n+\n+&mmc1 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&mmc1_pins>;\n+\tvmmc-supply = <&reg_dldo4>;\n+\tvqmmc-supply = <&reg_eldo1>;\n+\tmmc-pwrseq = <&wifi_pwrseq>;\n+\tbus-width = <4>;\n+\tnon-removable;\n+\tstatus = \"okay\";\n+\n+\trtl8723cs: wifi@1 {\n+\t\treg = <1>;\n+\t};\n+};\n \n &mmc2 {\n \tpinctrl-names = \"default\";\n--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts\n+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts\n@@ -35,6 +35,11 @@\n \t\t\t};\n \t\t};\n \t};\n+\n+\twifi_pwrseq: wifi_pwrseq {\n+\t\tcompatible = \"mmc-pwrseq-simple\";\n+\t\treset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */\n+\t};\n };\n \n &codec {\n@@ -124,6 +129,21 @@\n \tstatus = \"okay\";\n };\n \n+&mmc1 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&mmc1_pins>;\n+\tvmmc-supply = <&reg_dldo4>;\n+\tvqmmc-supply = <&reg_eldo1>;\n+\tmmc-pwrseq = <&wifi_pwrseq>;\n+\tbus-width = <4>;\n+\tnon-removable;\n+\tstatus = \"okay\";\n+\n+\trtl8723cs: wifi@1 {\n+\t\treg = <1>;\n+\t};\n+};\n+\n &ohci0 {\n \tstatus = \"okay\";\n };\n"
  },
  {
    "path": "target/linux/sunxi/profiles/00-default.mk",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2017 Yousong Zhou\n\ndefine Profile/Default\n  NAME:=Default Profile (all drivers)\n  PACKAGES:= \\\n\tkmod-ata-sunxi \\\n\tkmod-brcmfmac \\\n\tkmod-rtc-sunxi \\\n\tkmod-rtl8192cu \\\n\tkmod-rtl8xxxu \\\n\tkmod-sun4i-emac \\\n\trtl8188eu-firmware \\\n\tswconfig \\\n\twpad-basic-wolfssl\n  PRIORITY := 1\nendef\n\ndefine Profile/Default/Description\n  Default profile with package set compatible with most boards.\nendef\n$(eval $(call Profile,Default))\n"
  },
  {
    "path": "target/linux/tegra/Makefile",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2017-2019 Tomasz Maciej Nowak <tmn505@gmail.com>\n\ninclude $(TOPDIR)/rules.mk\n\nARCH := arm\nBOARD := tegra\nBOARDNAME := NVIDIA Tegra\nFEATURES := audio boot-part display ext4 fpu gpio pci pcie rootfs-part rtc squashfs usb\nCPU_TYPE := cortex-a9\nCPU_SUBTYPE := vfpv3-d16\n\nKERNEL_PATCHVER := 5.10\n\ninclude $(INCLUDE_DIR)/target.mk\n\nKERNELNAME := zImage dtbs\n\nDEFAULT_PACKAGES += e2fsprogs mkf2fs partx-utils\n\ndefine Target/Description\n\tBuild firmware image for NVIDIA Tegra SoC devices.\nendef\n\n$(eval $(call BuildTarget))\n"
  },
  {
    "path": "target/linux/tegra/base-files/etc/inittab",
    "content": "::sysinit:/etc/init.d/rcS S boot\n::shutdown:/etc/init.d/rcS K shutdown\n::askconsole:/usr/libexec/login.sh\ntty1::askfirst:/usr/libexec/login.sh\n"
  },
  {
    "path": "target/linux/tegra/base-files/lib/preinit/79_move_config",
    "content": "move_config() {\n\tlocal partdev\n\n\t. /lib/upgrade/common.sh\n\n\tif export_bootdevice && export_partdevice partdev 1; then\n\t\tmkdir -p /boot\n\t\tif mount -o ro,noatime \"/dev/$partdev\" /boot; then\n\t\t\tif [ -f \"/boot/$BACKUP_FILE\" ]; then\n\t\t\t\tmount /boot -o remount,rw,noatime\n\t\t\t\tmv -f \"/boot/$BACKUP_FILE\" /\n\t\t\tfi\n\t\t\tumount /boot\n\t\t\trm -fR /boot\n\t\tfi\n\tfi\n}\n\nboot_hook_add preinit_mount_root move_config\n"
  },
  {
    "path": "target/linux/tegra/base-files/lib/upgrade/platform.sh",
    "content": "REQUIRE_IMAGE_METADATA=1\n\nplatform_check_image() {\n\tlocal diskdev partdev diff\n\n\texport_bootdevice && export_partdevice diskdev 0 || {\n\t\tv \"Unable to determine upgrade device\"\n\t\treturn 1\n\t}\n\n\tget_partitions \"/dev/$diskdev\" bootdisk\n\n\tv \"Extract boot sector from the image\"\n\tget_image_dd \"$1\" of=/tmp/image.bs count=1 bs=512b\n\n\tget_partitions /tmp/image.bs image\n\n\t#compare tables\n\tdiff=\"$(grep -F -x -v -f /tmp/partmap.bootdisk /tmp/partmap.image)\"\n\n\trm -f /tmp/image.bs /tmp/partmap.bootdisk /tmp/partmap.image\n\n\tif [ -n \"$diff\" ]; then\n\t\tv \"Partition layout has changed. Full image will be written.\"\n\t\task_bool 0 \"Abort\" && exit 1\n\t\treturn 0\n\tfi\n}\n\nplatform_copy_config() {\n\tlocal partdev\n\n\tif export_partdevice partdev 1; then\n\t\tmount -o rw,noatime \"/dev/$partdev\" /mnt\n\t\tcp -af \"$UPGRADE_BACKUP\" \"/mnt/$BACKUP_FILE\"\n\t\tumount /mnt\n\tfi\n}\n\nplatform_do_upgrade() {\n\tlocal diskdev partdev diff\n\n\texport_bootdevice && export_partdevice diskdev 0 || {\n\t\tv \"Unable to determine upgrade device\"\n\t\treturn 1\n\t}\n\n\tsync\n\n\tif [ \"$UPGRADE_OPT_SAVE_PARTITIONS\" = \"1\" ]; then\n\t\tget_partitions \"/dev/$diskdev\" bootdisk\n\n\t\tv \"Extract boot sector from the image\"\n\t\tget_image_dd \"$1\" of=/tmp/image.bs count=1 bs=512b\n\n\t\tget_partitions /tmp/image.bs image\n\n\t\t#compare tables\n\t\tdiff=\"$(grep -F -x -v -f /tmp/partmap.bootdisk /tmp/partmap.image)\"\n\telse\n\t\tdiff=1\n\tfi\n\n\tif [ -n \"$diff\" ]; then\n\t\tget_image_dd \"$1\" of=\"/dev/$diskdev\" bs=4096 conv=fsync\n\n\t\t# Separate removal and addtion is necessary; otherwise, partition 1\n\t\t# will be missing if it overlaps with the old partition 2\n\t\tpartx -d - \"/dev/$diskdev\"\n\t\tpartx -a - \"/dev/$diskdev\"\n\n\t\treturn 0\n\tfi\n\n\tv \"Writing bootloader to /dev/$diskdev\"\n\tget_image_dd \"$1\" of=\"$diskdev\" bs=512 skip=1 seek=1 count=4097 conv=fsync,notrunc\n\t#iterate over each partition from the image and write it to the boot disk\n\twhile read part start size; do\n\t\tif export_partdevice partdev $part; then\n\t\t\tv \"Writing image to /dev/$partdev...\"\n\t\t\tget_image_dd \"$1\" of=\"/dev/$partdev\" ibs=\"512\" obs=1M skip=\"$start\" count=\"$size\" conv=fsync\n\t\telse\n\t\t\tv \"Unable to find partition $part device, skipped.\"\n\t\tfi\n\tdone < /tmp/partmap.image\n\n\tv \"Writing new UUID to /dev/$diskdev...\"\n\tget_image_dd \"$1\" of=\"/dev/$diskdev\" bs=1 skip=440 count=4 seek=440 conv=fsync\n}\n"
  },
  {
    "path": "target/linux/tegra/config-5.10",
    "content": "CONFIG_AC97_BUS=y\n# CONFIG_AHCI_TEGRA is not set\nCONFIG_ALIGNMENT_TRAP=y\nCONFIG_ARCH_32BIT_OFF_T=y\nCONFIG_ARCH_HIBERNATION_POSSIBLE=y\nCONFIG_ARCH_KEEP_MEMBLOCK=y\nCONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y\nCONFIG_ARCH_MULTIPLATFORM=y\nCONFIG_ARCH_MULTI_V6_V7=y\nCONFIG_ARCH_MULTI_V7=y\nCONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED=y\nCONFIG_ARCH_NR_GPIO=1024\nCONFIG_ARCH_OPTIONAL_KERNEL_RWX=y\nCONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y\nCONFIG_ARCH_SELECT_MEMORY_MODEL=y\nCONFIG_ARCH_SPARSEMEM_ENABLE=y\nCONFIG_ARCH_SUSPEND_POSSIBLE=y\nCONFIG_ARCH_TEGRA=y\n# CONFIG_ARCH_TEGRA_114_SOC is not set\n# CONFIG_ARCH_TEGRA_124_SOC is not set\nCONFIG_ARCH_TEGRA_2x_SOC=y\n# CONFIG_ARCH_TEGRA_3x_SOC is not set\nCONFIG_ARM=y\nCONFIG_ARM_AMBA=y\nCONFIG_ARM_CPU_SUSPEND=y\nCONFIG_ARM_CRYPTO=y\nCONFIG_ARM_ERRATA_720789=y\nCONFIG_ARM_ERRATA_754327=y\nCONFIG_ARM_ERRATA_764369=y\nCONFIG_ARM_GIC=y\nCONFIG_ARM_HAS_SG_CHAIN=y\nCONFIG_ARM_HEAVY_MB=y\nCONFIG_ARM_L1_CACHE_SHIFT=6\nCONFIG_ARM_L1_CACHE_SHIFT_6=y\nCONFIG_ARM_PATCH_IDIV=y\nCONFIG_ARM_PATCH_PHYS_VIRT=y\n# CONFIG_ARM_PL172_MPMC is not set\n# CONFIG_ARM_SMMU is not set\nCONFIG_ARM_TEGRA_CPUIDLE=y\nCONFIG_ARM_THUMB=y\nCONFIG_ARM_THUMBEE=y\nCONFIG_ARM_UNWIND=y\nCONFIG_ARM_VIRT_EXT=y\nCONFIG_ASN1=y\nCONFIG_ATA=y\nCONFIG_ATAGS=y\nCONFIG_AUTO_ZRELADDR=y\nCONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y\nCONFIG_BLK_DEV_BSG=y\nCONFIG_BLK_DEV_LOOP=y\nCONFIG_BLK_MQ_PCI=y\nCONFIG_BLK_PM=y\nCONFIG_BLK_SCSI_REQUEST=y\nCONFIG_BOUNCE=y\nCONFIG_CACHE_L2X0=y\nCONFIG_CLKDEV_LOOKUP=y\nCONFIG_CLKSRC_MMIO=y\nCONFIG_CLONE_BACKWARDS=y\nCONFIG_CLZ_TAB=y\nCONFIG_CMA=y\nCONFIG_CMA_ALIGNMENT=8\nCONFIG_CMA_AREAS=7\n# CONFIG_CMA_DEBUG is not set\n# CONFIG_CMA_DEBUGFS is not set\nCONFIG_CMA_SIZE_MBYTES=16\n# CONFIG_CMA_SIZE_SEL_MAX is not set\nCONFIG_CMA_SIZE_SEL_MBYTES=y\n# CONFIG_CMA_SIZE_SEL_MIN is not set\n# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set\nCONFIG_COMMON_CLK=y\nCONFIG_COMPAT_32BIT_TIME=y\nCONFIG_CONTIG_ALLOC=y\n# CONFIG_CPUFREQ_DT is not set\nCONFIG_CPU_32v6K=y\nCONFIG_CPU_32v7=y\nCONFIG_CPU_ABRT_EV7=y\nCONFIG_CPU_CACHE_V7=y\nCONFIG_CPU_CACHE_VIPT=y\nCONFIG_CPU_COPY_V6=y\nCONFIG_CPU_CP15=y\nCONFIG_CPU_CP15_MMU=y\nCONFIG_CPU_FREQ=y\nCONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y\n# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set\nCONFIG_CPU_FREQ_GOV_ATTR_SET=y\nCONFIG_CPU_FREQ_GOV_COMMON=y\nCONFIG_CPU_FREQ_GOV_CONSERVATIVE=y\nCONFIG_CPU_FREQ_GOV_ONDEMAND=y\nCONFIG_CPU_FREQ_GOV_PERFORMANCE=y\nCONFIG_CPU_FREQ_GOV_POWERSAVE=y\nCONFIG_CPU_FREQ_GOV_SCHEDUTIL=y\nCONFIG_CPU_FREQ_GOV_USERSPACE=y\n# CONFIG_CPU_FREQ_STAT is not set\nCONFIG_CPU_HAS_ASID=y\nCONFIG_CPU_IDLE=y\nCONFIG_CPU_IDLE_GOV_LADDER=y\nCONFIG_CPU_PABRT_V7=y\nCONFIG_CPU_PM=y\nCONFIG_CPU_RMAP=y\nCONFIG_CPU_SPECTRE=y\nCONFIG_CPU_THUMB_CAPABLE=y\nCONFIG_CPU_TLB_V7=y\nCONFIG_CPU_V7=y\nCONFIG_CRC16=y\n# CONFIG_CRC32_SARWATE is not set\nCONFIG_CRC32_SLICEBY8=y\nCONFIG_CROSS_MEMORY_ATTACH=y\nCONFIG_CRYPTO_ACOMP2=y\nCONFIG_CRYPTO_AES_ARM=y\nCONFIG_CRYPTO_AKCIPHER=y\nCONFIG_CRYPTO_AKCIPHER2=y\nCONFIG_CRYPTO_CRC32=y\nCONFIG_CRYPTO_CRC32C=y\nCONFIG_CRYPTO_CRYPTD=y\nCONFIG_CRYPTO_DEFLATE=y\nCONFIG_CRYPTO_DRBG=y\nCONFIG_CRYPTO_DRBG_HMAC=y\nCONFIG_CRYPTO_DRBG_MENU=y\nCONFIG_CRYPTO_ECHAINIV=y\nCONFIG_CRYPTO_HMAC=y\nCONFIG_CRYPTO_JITTERENTROPY=y\nCONFIG_CRYPTO_LIB_SHA256=y\nCONFIG_CRYPTO_LZ4=y\nCONFIG_CRYPTO_LZ4HC=y\nCONFIG_CRYPTO_LZO=y\nCONFIG_CRYPTO_NULL=y\nCONFIG_CRYPTO_RNG=y\nCONFIG_CRYPTO_RNG2=y\nCONFIG_CRYPTO_RNG_DEFAULT=y\nCONFIG_CRYPTO_RSA=y\nCONFIG_CRYPTO_SEQIV=y\nCONFIG_CRYPTO_SHA1=y\nCONFIG_CRYPTO_SHA1_ARM=y\nCONFIG_CRYPTO_SHA256=y\nCONFIG_CRYPTO_SHA256_ARM=y\nCONFIG_CRYPTO_SHA512_ARM=y\nCONFIG_CRYPTO_TWOFISH=y\nCONFIG_CRYPTO_TWOFISH_COMMON=y\nCONFIG_DCACHE_WORD_ACCESS=y\nCONFIG_DEBUG_ALIGN_RODATA=y\nCONFIG_DEBUG_LL_INCLUDE=\"mach/debug-macro.S\"\n# CONFIG_DEVPORT is not set\nCONFIG_DMADEVICES=y\nCONFIG_DMA_CMA=y\nCONFIG_DMA_ENGINE=y\nCONFIG_DMA_OF=y\nCONFIG_DMA_OPS=y\nCONFIG_DMA_REMAP=y\nCONFIG_DMA_SHARED_BUFFER=y\nCONFIG_DNOTIFY=y\nCONFIG_DRM=y\nCONFIG_DRM_BRIDGE=y\nCONFIG_DRM_FBDEV_EMULATION=y\nCONFIG_DRM_FBDEV_OVERALLOC=100\nCONFIG_DRM_KMS_FB_HELPER=y\nCONFIG_DRM_KMS_HELPER=y\nCONFIG_DRM_MIPI_DSI=y\nCONFIG_DRM_PANEL=y\nCONFIG_DRM_PANEL_BRIDGE=y\nCONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y\nCONFIG_DRM_TEGRA=y\n# CONFIG_DRM_TEGRA_DEBUG is not set\n# CONFIG_DRM_TEGRA_STAGING is not set\nCONFIG_DTC=y\nCONFIG_EDAC_ATOMIC_SCRUB=y\nCONFIG_EDAC_SUPPORT=y\nCONFIG_ENABLE_MUST_CHECK=y\nCONFIG_EXT4_FS=y\nCONFIG_EXTCON=y\nCONFIG_F2FS_FS=y\nCONFIG_FB=y\nCONFIG_FB_CFB_COPYAREA=y\nCONFIG_FB_CFB_FILLRECT=y\nCONFIG_FB_CFB_IMAGEBLIT=y\nCONFIG_FB_CMDLINE=y\nCONFIG_FB_DEFERRED_IO=y\nCONFIG_FB_SYS_COPYAREA=y\nCONFIG_FB_SYS_FILLRECT=y\nCONFIG_FB_SYS_FOPS=y\nCONFIG_FB_SYS_IMAGEBLIT=y\nCONFIG_FIX_EARLYCON_MEM=y\nCONFIG_FREEZER=y\nCONFIG_FS_IOMAP=y\nCONFIG_FS_MBCACHE=y\n# CONFIG_FW_CACHE is not set\nCONFIG_FW_LOADER_PAGED_BUF=y\nCONFIG_GENERIC_ALLOCATOR=y\nCONFIG_GENERIC_ARCH_TOPOLOGY=y\nCONFIG_GENERIC_BUG=y\nCONFIG_GENERIC_CLOCKEVENTS=y\nCONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y\nCONFIG_GENERIC_CPU_AUTOPROBE=y\nCONFIG_GENERIC_EARLY_IOREMAP=y\nCONFIG_GENERIC_GETTIMEOFDAY=y\nCONFIG_GENERIC_IDLE_POLL_SETUP=y\nCONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y\nCONFIG_GENERIC_IRQ_MIGRATION=y\nCONFIG_GENERIC_IRQ_MULTI_HANDLER=y\nCONFIG_GENERIC_IRQ_SHOW=y\nCONFIG_GENERIC_IRQ_SHOW_LEVEL=y\nCONFIG_GENERIC_MSI_IRQ=y\nCONFIG_GENERIC_MSI_IRQ_DOMAIN=y\nCONFIG_GENERIC_PCI_IOMAP=y\nCONFIG_GENERIC_PHY=y\nCONFIG_GENERIC_PINCONF=y\nCONFIG_GENERIC_PINCTRL_GROUPS=y\nCONFIG_GENERIC_PINMUX_FUNCTIONS=y\nCONFIG_GENERIC_SCHED_CLOCK=y\nCONFIG_GENERIC_SMP_IDLE_THREAD=y\nCONFIG_GENERIC_STRNCPY_FROM_USER=y\nCONFIG_GENERIC_STRNLEN_USER=y\nCONFIG_GENERIC_TIME_VSYSCALL=y\nCONFIG_GENERIC_VDSO_32=y\nCONFIG_GLOB=y\nCONFIG_GPIOLIB=y\nCONFIG_GPIO_TEGRA=y\nCONFIG_HANDLE_DOMAIN_IRQ=y\nCONFIG_HARDEN_BRANCH_PREDICTOR=y\nCONFIG_HARDIRQS_SW_RESEND=y\nCONFIG_HAS_DMA=y\nCONFIG_HAS_IOMEM=y\nCONFIG_HAS_IOPORT_MAP=y\nCONFIG_HAVE_SMP=y\nCONFIG_HDMI=y\nCONFIG_HID=y\nCONFIG_HIDRAW=y\nCONFIG_HID_GENERIC=y\nCONFIG_HIGHMEM=y\nCONFIG_HIGHPTE=y\nCONFIG_HOTPLUG_CPU=y\nCONFIG_HWMON=y\nCONFIG_HZ_FIXED=0\nCONFIG_HZ_PERIODIC=y\nCONFIG_I2C=y\nCONFIG_I2C_ALGOBIT=y\nCONFIG_I2C_BOARDINFO=y\nCONFIG_I2C_COMPAT=y\nCONFIG_I2C_TEGRA=y\nCONFIG_INITRAMFS_SOURCE=\"\"\nCONFIG_INPUT=y\nCONFIG_INPUT_KEYBOARD=y\nCONFIG_IOMMU_API=y\n# CONFIG_IOMMU_DEBUGFS is not set\n# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set\nCONFIG_IOMMU_IOVA=y\n# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set\n# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set\nCONFIG_IOMMU_SUPPORT=y\nCONFIG_IRQCHIP=y\nCONFIG_IRQ_DOMAIN=y\nCONFIG_IRQ_DOMAIN_HIERARCHY=y\nCONFIG_IRQ_FORCED_THREADING=y\nCONFIG_IRQ_WORK=y\nCONFIG_JBD2=y\nCONFIG_KCMP=y\nCONFIG_KEYBOARD_ATKBD=y\nCONFIG_LIBFDT=y\nCONFIG_LOCK_DEBUGGING_SUPPORT=y\nCONFIG_LOCK_SPIN_ON_OWNER=y\nCONFIG_LZ4HC_COMPRESS=y\nCONFIG_LZ4_COMPRESS=y\nCONFIG_LZ4_DECOMPRESS=y\nCONFIG_LZO_COMPRESS=y\nCONFIG_LZO_DECOMPRESS=y\nCONFIG_MEMFD_CREATE=y\nCONFIG_MEMORY=y\nCONFIG_MEMORY_ISOLATION=y\n# CONFIG_MFD_NVEC is not set\nCONFIG_MIGHT_HAVE_CACHE_L2X0=y\nCONFIG_MIGRATION=y\nCONFIG_MMC=y\nCONFIG_MMC_BLOCK=y\nCONFIG_MMC_CQHCI=y\nCONFIG_MMC_SDHCI=y\nCONFIG_MMC_SDHCI_IO_ACCESSORS=y\n# CONFIG_MMC_SDHCI_PCI is not set\nCONFIG_MMC_SDHCI_PLTFM=y\nCONFIG_MMC_SDHCI_TEGRA=y\nCONFIG_MODULES_USE_ELF_REL=y\nCONFIG_MPILIB=y\nCONFIG_MTD_SPI_NOR=y\nCONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y\nCONFIG_MUTEX_SPIN_ON_OWNER=y\nCONFIG_NEED_DMA_MAP_STATE=y\n# CONFIG_NEON is not set\nCONFIG_NET_FLOW_LIMIT=y\nCONFIG_NLS=y\nCONFIG_NR_CPUS=4\nCONFIG_NVMEM=y\nCONFIG_OF=y\nCONFIG_OF_ADDRESS=y\nCONFIG_OF_EARLY_FLATTREE=y\nCONFIG_OF_FLATTREE=y\nCONFIG_OF_GPIO=y\nCONFIG_OF_IOMMU=y\nCONFIG_OF_IRQ=y\nCONFIG_OF_KOBJ=y\nCONFIG_OF_NET=y\nCONFIG_OLD_SIGACTION=y\nCONFIG_OLD_SIGSUSPEND3=y\nCONFIG_OUTER_CACHE=y\nCONFIG_OUTER_CACHE_SYNC=y\nCONFIG_PADATA=y\nCONFIG_PAGE_OFFSET=0xC0000000\nCONFIG_PCI=y\nCONFIG_PCIEAER=y\nCONFIG_PCIEASPM=y\nCONFIG_PCIEASPM_DEFAULT=y\n# CONFIG_PCIEASPM_PERFORMANCE is not set\n# CONFIG_PCIEASPM_POWERSAVE is not set\n# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set\nCONFIG_PCIEPORTBUS=y\nCONFIG_PCIE_PME=y\nCONFIG_PCI_DOMAINS=y\nCONFIG_PCI_DOMAINS_GENERIC=y\nCONFIG_PCI_MSI=y\nCONFIG_PCI_MSI_ARCH_FALLBACKS=y\nCONFIG_PCI_MSI_IRQ_DOMAIN=y\nCONFIG_PCI_TEGRA=y\nCONFIG_PERF_USE_VMALLOC=y\nCONFIG_PGTABLE_LEVELS=2\nCONFIG_PHY_TEGRA_XUSB=y\nCONFIG_PINCTRL=y\nCONFIG_PINCTRL_TEGRA=y\nCONFIG_PINCTRL_TEGRA20=y\nCONFIG_PINCTRL_TEGRA_XUSB=y\nCONFIG_PL310_ERRATA_727915=y\nCONFIG_PL310_ERRATA_769419=y\nCONFIG_PL353_SMC=y\nCONFIG_PM=y\nCONFIG_PM_CLK=y\nCONFIG_PM_OPP=y\nCONFIG_PM_SLEEP=y\nCONFIG_PM_SLEEP_SMP=y\nCONFIG_POWER_RESET=y\nCONFIG_POWER_RESET_GPIO=y\nCONFIG_POWER_SUPPLY=y\nCONFIG_PROC_PAGE_MONITOR=y\nCONFIG_PWM=y\nCONFIG_PWM_SYSFS=y\nCONFIG_PWM_TEGRA=y\nCONFIG_RAS=y\nCONFIG_RATIONAL=y\nCONFIG_REGMAP=y\nCONFIG_REGMAP_I2C=y\nCONFIG_REGMAP_MMIO=y\nCONFIG_REGMAP_SPI=y\nCONFIG_REGULATOR=y\nCONFIG_REGULATOR_FIXED_VOLTAGE=y\nCONFIG_REGULATOR_GPIO=y\nCONFIG_RESET_CONTROLLER=y\nCONFIG_RFS_ACCEL=y\nCONFIG_RPS=y\nCONFIG_RTC_CLASS=y\nCONFIG_RTC_DRV_TEGRA=y\nCONFIG_RTC_I2C_AND_SPI=y\nCONFIG_RTC_MC146818_LIB=y\nCONFIG_RTC_NVMEM=y\nCONFIG_RWSEM_SPIN_ON_OWNER=y\nCONFIG_SCSI=y\n# CONFIG_SCSI_LOWLEVEL is not set\n# CONFIG_SCSI_PROC_FS is not set\nCONFIG_SERIAL_8250_FSL=y\nCONFIG_SERIAL_8250_TEGRA=y\nCONFIG_SERIAL_MCTRL_GPIO=y\nCONFIG_SERIAL_OF_PLATFORM=y\nCONFIG_SERIAL_TEGRA=y\nCONFIG_SERIO=y\nCONFIG_SERIO_LIBPS2=y\nCONFIG_SGL_ALLOC=y\nCONFIG_SG_POOL=y\nCONFIG_SMP=y\nCONFIG_SMP_ON_UP=y\nCONFIG_SND=y\n# CONFIG_SND_COMPRESS_OFFLOAD is not set\nCONFIG_SND_DMAENGINE_PCM=y\n# CONFIG_SND_DRIVERS is not set\n# CONFIG_SND_HDA_TEGRA is not set\nCONFIG_SND_JACK=y\nCONFIG_SND_JACK_INPUT_DEV=y\n# CONFIG_SND_PCI is not set\nCONFIG_SND_PCM=y\n# CONFIG_SND_PROC_FS is not set\nCONFIG_SND_SIMPLE_CARD=y\nCONFIG_SND_SIMPLE_CARD_UTILS=y\nCONFIG_SND_SOC=y\nCONFIG_SND_SOC_AC97_BUS=y\nCONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y\nCONFIG_SND_SOC_I2C_AND_SPI=y\nCONFIG_SND_SOC_TEGRA=y\n# CONFIG_SND_SOC_TEGRA186_DSPK is not set\nCONFIG_SND_SOC_TEGRA20_AC97=y\nCONFIG_SND_SOC_TEGRA20_DAS=y\nCONFIG_SND_SOC_TEGRA20_I2S=y\nCONFIG_SND_SOC_TEGRA20_SPDIF=y\n# CONFIG_SND_SOC_TEGRA210_ADMAIF is not set\n# CONFIG_SND_SOC_TEGRA210_AHUB is not set\n# CONFIG_SND_SOC_TEGRA210_DMIC is not set\n# CONFIG_SND_SOC_TEGRA210_I2S is not set\n# CONFIG_SND_SOC_TEGRA30_AHUB is not set\n# CONFIG_SND_SOC_TEGRA30_I2S is not set\n# CONFIG_SND_SOC_TEGRA_ALC5632 is not set\n# CONFIG_SND_SOC_TEGRA_MAX98090 is not set\n# CONFIG_SND_SOC_TEGRA_RT5640 is not set\n# CONFIG_SND_SOC_TEGRA_RT5677 is not set\n# CONFIG_SND_SOC_TEGRA_SGTL5000 is not set\nCONFIG_SND_SOC_TEGRA_TRIMSLICE=y\n# CONFIG_SND_SOC_TEGRA_WM8753 is not set\n# CONFIG_SND_SOC_TEGRA_WM8903 is not set\n# CONFIG_SND_SOC_TEGRA_WM9712 is not set\nCONFIG_SND_SOC_TLV320AIC23=y\nCONFIG_SND_SOC_TLV320AIC23_I2C=y\n# CONFIG_SND_USB is not set\nCONFIG_SOC_BUS=y\nCONFIG_SOC_TEGRA20_VOLTAGE_COUPLER=y\nCONFIG_SOC_TEGRA_FLOWCTRL=y\nCONFIG_SOC_TEGRA_FUSE=y\nCONFIG_SOC_TEGRA_PMC=y\nCONFIG_SOUND=y\nCONFIG_SOUND_OSS_CORE=y\nCONFIG_SOUND_OSS_CORE_PRECLAIM=y\nCONFIG_SPARSE_IRQ=y\nCONFIG_SPI=y\nCONFIG_SPI_MASTER=y\nCONFIG_SPI_MEM=y\n# CONFIG_SPI_TEGRA114 is not set\nCONFIG_SPI_TEGRA20_SFLASH=y\nCONFIG_SPI_TEGRA20_SLINK=y\nCONFIG_SRCU=y\nCONFIG_SUSPEND=y\nCONFIG_SUSPEND_FREEZER=y\nCONFIG_SWP_EMULATE=y\nCONFIG_SYNC_FILE=y\nCONFIG_SYS_SUPPORTS_APM_EMULATION=y\nCONFIG_TEGRA20_APB_DMA=y\nCONFIG_TEGRA20_EMC=y\nCONFIG_TEGRA_AHB=y\nCONFIG_TEGRA_GMI=y\nCONFIG_TEGRA_HOST1X=y\nCONFIG_TEGRA_HOST1X_FIREWALL=y\nCONFIG_TEGRA_IOMMU_GART=y\n# CONFIG_TEGRA_IOMMU_SMMU is not set\n# CONFIG_TEGRA_IVC is not set\nCONFIG_TEGRA_MC=y\n# CONFIG_TEGRA_SOCTHERM is not set\nCONFIG_TEGRA_TIMER=y\nCONFIG_TEGRA_WATCHDOG=y\nCONFIG_TICK_CPU_ACCOUNTING=y\nCONFIG_TIMER_OF=y\nCONFIG_TIMER_PROBE=y\nCONFIG_TREE_RCU=y\nCONFIG_TREE_SRCU=y\n# CONFIG_UACCE is not set\n# CONFIG_UCLAMP_TASK is not set\nCONFIG_UNCOMPRESS_INCLUDE=\"debug/uncompress.h\"\nCONFIG_UNWINDER_ARM=y\nCONFIG_USB=y\nCONFIG_USB_COMMON=y\nCONFIG_USB_CONN_GPIO=y\nCONFIG_USB_EHCI_HCD=y\n# CONFIG_USB_EHCI_HCD_PLATFORM is not set\nCONFIG_USB_EHCI_TEGRA=y\nCONFIG_USB_HID=y\nCONFIG_USB_HIDDEV=y\nCONFIG_USB_PHY=y\nCONFIG_USB_ROLE_SWITCH=y\nCONFIG_USB_SUPPORT=y\nCONFIG_USB_TEGRA_PHY=y\nCONFIG_USB_ULPI=y\nCONFIG_USB_ULPI_VIEWPORT=y\nCONFIG_USE_OF=y\nCONFIG_VFP=y\nCONFIG_VFPv3=y\nCONFIG_WATCHDOG_CORE=y\n# CONFIG_USB_XHCI_TEGRA is not set\nCONFIG_XPS=y\nCONFIG_XZ_DEC_ARM=y\nCONFIG_XZ_DEC_ARMTHUMB=y\nCONFIG_XZ_DEC_BCJ=y\nCONFIG_ZBOOT_ROM_BSS=0\nCONFIG_ZBOOT_ROM_TEXT=0\nCONFIG_ZLIB_DEFLATE=y\nCONFIG_ZLIB_INFLATE=y\n"
  },
  {
    "path": "target/linux/tegra/image/Makefile",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2017-2019 Tomasz Maciej Nowak <tmn505@gmail.com>\n\ninclude $(TOPDIR)/rules.mk\ninclude $(INCLUDE_DIR)/image.mk\n\ndefine Build/tegra-sdcard\n\trm -fR $@.boot\n\tmkdir -p $@.boot\n\t$(CP) $(KDIR)/$(KERNEL_NAME) $@.boot\n\t$(if $(DEVICE_DTS),\\\n\t\t$(foreach dtb,$(DEVICE_DTS),$(CP) $(DTS_DIR)/$(dtb).dtb $@.boot), \\\n\t\t$(CP) $(DTS_DIR)/*.dtb $@.boot)\n\tmkimage -A arm -O linux -T script -C none -a 0 -e 0 \\\n\t\t-n '$(DEVICE_TITLE) OpenWrt bootscript' \\\n\t\t-d $(BOOT_SCRIPT) \\\n\t\t$@.boot/boot.scr\n\n\tSIGNATURE=\"$(IMG_PART_SIGNATURE)\" \\\n\t$(SCRIPT_DIR)/gen_image_generic.sh \\\n\t\t$@ \\\n\t\t$(CONFIG_TARGET_KERNEL_PARTSIZE) $@.boot \\\n\t\t$(CONFIG_TARGET_ROOTFS_PARTSIZE) $(IMAGE_ROOTFS) \\\n\t\t2048\n\n\t$(if $(UBOOT),dd if=$(STAGING_DIR_IMAGE)/$(UBOOT).img of=$@ bs=512 skip=1 seek=1 conv=notrunc)\nendef\n\nDEVICE_VARS += BOOT_SCRIPT UBOOT\n\ndefine Device/Default\n  BOOT_SCRIPT := generic-bootscript\n  IMAGES := sdcard.img.gz\n  IMAGE/sdcard.img.gz := tegra-sdcard | gzip | append-metadata\n  KERNEL_NAME := zImage\n  KERNEL := kernel-bin\n  PROFILES := Default\nendef\n\ndefine Device/compulab_trimslice\n  DEVICE_VENDOR := CompuLab\n  DEVICE_MODEL := TrimSlice\n  DEVICE_DTS := tegra20-trimslice\n  DEVICE_PACKAGES := kmod-r8169 kmod-rt2800-usb kmod-rtc-em3027 \\\n\tkmod-usb-storage wpad-basic-wolfssl\n  UBOOT := trimslice-mmc\nendef\nTARGET_DEVICES += compulab_trimslice\n\n$(eval $(call BuildImage))\n"
  },
  {
    "path": "target/linux/tegra/image/generic-bootscript",
    "content": "part uuid ${devtype} ${devnum}:2 ptuuid\n\nsetenv bootargs \"root=PARTUUID=${ptuuid} rw rootwait console=ttyS0,115200 console=tty0\"\n\nload ${devtype} ${devnum}:${bootpart} ${kernel_addr_r} zImage\nload ${devtype} ${devnum}:${bootpart} ${fdt_addr_r} ${soc}-${board}.dtb\n\nbootz ${kernel_addr_r} - ${fdt_addr_r}\n"
  },
  {
    "path": "target/linux/tegra/patches-5.10/100-serial8250-on-tegra-hsuart-recover-from-spurious-interrupts-due-to-tegra2-silicon-bug.patch",
    "content": "From patchwork Fri Jul 13 11:32:42 2018\nContent-Type: text/plain; charset=\"utf-8\"\nMIME-Version: 1.0\nContent-Transfer-Encoding: 7bit\nSubject: serial8250 on tegra hsuart: recover from spurious interrupts due to\n tegra2 silicon bug\nX-Patchwork-Submitter: \"David R. Piegdon\" <lkml@p23q.org>\nX-Patchwork-Id: 943440\nMessage-Id: <4676ea34-69ce-5422-1ded-94218b89f7d9@p23q.org>\nTo: linux-tegra@vger.kernel.org\nDate: Fri, 13 Jul 2018 11:32:42 +0000\nFrom: \"David R. Piegdon\" <lkml@p23q.org>\nList-Id: <linux-tegra.vger.kernel.org>\n\nHi,\na while back I sent a few mails regarding spurious interrupts in the\nUARTA (hsuart) block of the Tegra2 SoC, when using the 8250 driver for\nit instead of the hsuart driver. After going down a pretty deep\ndebugging/testing hole, I think I found a patch that fixes the issue. So\nfar testing in a reboot-cycle suggests that the error frequency dropped\nfrom >3% of all reboots to at least <0.05% of all reboots. Tests\ncontinue to run over the weekend.\n\nThe patch below already is a second iteration; the first did not reset\nthe MCR or contain the lines below '// clear interrupts'. This resulted\nin no more spurious interrupts, but in a few % of spurious interrupts\nthat were recovered the UART block did not receive any characters any\nmore. So further resetting was required to fully reacquire operational\nstate of the UART block.\n\nI'd love any comments/suggestions on this!\n\nCheers,\n\nDavid\n\n--- a/drivers/tty/serial/8250/8250_core.c\n+++ b/drivers/tty/serial/8250/8250_core.c\n@@ -133,6 +133,38 @@ static irqreturn_t serial8250_interrupt(\n \n \t\tif (l == i->head && pass_counter++ > PASS_LIMIT)\n \t\t\tbreak;\n+\n+#ifdef CONFIG_ARCH_TEGRA_2x_SOC\n+\t\tif (!handled && (port->type == PORT_TEGRA)) {\n+\t\t\t/*\n+\t\t\t * Fix Tegra 2 CPU silicon bug where sometimes\n+\t\t\t * \"TX holding register empty\" interrupts result in a\n+\t\t\t * bad (metastable?) state in Tegras HSUART IP core.\n+\t\t\t * Only way to recover seems to be to reset all\n+\t\t\t * interrupts as well as the TX queue and the MCR.\n+\t\t\t * But we don't want to loose any outgoing characters,\n+\t\t\t * so only do it if the RX and TX queues are empty.\n+\t\t\t */\n+\t\t\tunsigned char lsr = port->serial_in(port, UART_LSR);\n+\t\t\tconst unsigned char fifo_empty_mask =\n+\t\t\t\t\t\t(UART_LSR_TEMT | UART_LSR_THRE);\n+\t\t\tif (((lsr & (UART_LSR_DR | fifo_empty_mask)) ==\n+\t\t\t\t\t\t\tfifo_empty_mask)) {\n+\t\t\t\tport->serial_out(port, UART_IER, 0);\n+\t\t\t\tport->serial_out(port, UART_MCR, 0);\n+\t\t\t\tserial8250_clear_and_reinit_fifos(up);\n+\t\t\t\tport->serial_out(port, UART_MCR, up->mcr);\n+\t\t\t\tport->serial_out(port, UART_IER, up->ier);\n+\t\t\t\t// clear interrupts\n+\t\t\t\tserial_port_in(port, UART_LSR);\n+\t\t\t\tserial_port_in(port, UART_RX);\n+\t\t\t\tserial_port_in(port, UART_IIR);\n+\t\t\t\tserial_port_in(port, UART_MSR);\n+\t\t\t\tup->lsr_saved_flags = 0;\n+\t\t\t\tup->msr_saved_flags = 0;\n+\t\t\t}\n+\t\t}\n+#endif\n \t} while (l != end);\n \n \tspin_unlock(&i->lock);\n"
  },
  {
    "path": "target/linux/tegra/patches-5.10/101-ARM-dtc-tegra-enable-front-panel-leds-in-TrimSlice.patch",
    "content": "--- a/arch/arm/boot/dts/tegra20-trimslice.dts\n+++ b/arch/arm/boot/dts/tegra20-trimslice.dts\n@@ -201,16 +201,17 @@\n \t\t\tconf_ata {\n \t\t\t\tnvidia,pins = \"ata\", \"atc\", \"atd\", \"ate\",\n \t\t\t\t\t\"crtp\", \"dap2\", \"dap3\", \"dap4\", \"dta\",\n-\t\t\t\t\t\"dtb\", \"dtc\", \"dtd\", \"dte\", \"gmb\",\n-\t\t\t\t\t\"gme\", \"i2cp\", \"pta\", \"slxc\", \"slxd\",\n-\t\t\t\t\t\"spdi\", \"spdo\", \"uda\";\n+\t\t\t\t\t\"dtb\", \"dtc\", \"dtd\", \"gmb\", \"gme\",\n+\t\t\t\t\t\"i2cp\", \"pta\", \"slxc\", \"slxd\", \"spdi\",\n+\t\t\t\t\t\"spdo\", \"uda\";\n \t\t\t\tnvidia,pull = <TEGRA_PIN_PULL_NONE>;\n \t\t\t\tnvidia,tristate = <TEGRA_PIN_ENABLE>;\n \t\t\t};\n \t\t\tconf_atb {\n \t\t\t\tnvidia,pins = \"atb\", \"cdev1\", \"cdev2\", \"dap1\",\n-\t\t\t\t\t\"gma\", \"gmc\", \"gmd\", \"gpu\", \"gpu7\",\n-\t\t\t\t\t\"gpv\", \"sdio1\", \"slxa\", \"slxk\", \"uac\";\n+\t\t\t\t\t\"dte\", \"gma\", \"gmc\", \"gmd\", \"gpu\",\n+\t\t\t\t\t\"gpu7\", \"gpv\", \"sdio1\", \"slxa\", \"slxk\",\n+\t\t\t\t\t\"uac\";\n \t\t\t\tnvidia,pull = <TEGRA_PIN_PULL_NONE>;\n \t\t\t\tnvidia,tristate = <TEGRA_PIN_DISABLE>;\n \t\t\t};\n@@ -396,6 +397,20 @@\n \t\t};\n \t};\n \n+\tgpio-leds {\n+\t\tcompatible = \"gpio-leds\";\n+\n+\t\tds2 {\n+\t\t\tlabel = \"trimslice:green:right\";\n+\t\t\tgpios = <&gpio TEGRA_GPIO(D, 2) GPIO_ACTIVE_LOW>;\n+\t\t};\n+\n+\t\tds3 {\n+\t\t\tlabel = \"trimslice:green:left\";\n+\t\t\tgpios = <&gpio TEGRA_GPIO(BB, 5) GPIO_ACTIVE_LOW>;\n+\t\t};\n+\t};\n+\n \tpoweroff {\n \t\tcompatible = \"gpio-poweroff\";\n \t\tgpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW>;\n"
  },
  {
    "path": "target/linux/uml/Makefile",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2006-2021 OpenWrt.org\n\ninclude $(TOPDIR)/rules.mk\n\n# UML only makes sense on linux\nifeq ($(HOST_OS),Linux)\n  ifeq ($(HOST_ARCH),x86_64)\n\nARCH:=x86_64\nBOARD:=uml\nBOARDNAME:=User Mode Linux\nFEATURES:=audio ext4 rootfs-part squashfs\n\nKERNEL_PATCHVER:=5.10\n\ninclude $(INCLUDE_DIR)/target.mk\n\nDEFAULT_PACKAGES += wpad-basic-wolfssl kmod-mac80211-hwsim mkf2fs e2fsprogs\n\n  endif\nendif\n\n$(eval $(call BuildTarget))\n"
  },
  {
    "path": "target/linux/uml/README.md",
    "content": "# OpenWrt inside a user mode linux\n\n> Why would we even want this many ask?\n\nThere are potentially a lot of reasons, one obvious one to me, it allows folks\nto 'kick the tires' without actually flashing up any hardware.  It's also a\ngreat environment for porting over packages, you can get a package fully\nfunctional in the uclibc root environment inside a uml without actually\ndisturbing your 'real router', and then rebuild for a specific target once it's\nfully tested.\n\nThis is a first stab at a build that 'just works' and there will be more\ncleanup to come.  The simple directions are:-\n\n* Configure for uml target\n* Configure with an ext4 or squashfs root file system\n* Build it all\n\nIn your bin directory you will find a Kernel and an root file system when it's\nfinished. Just run it like this:-\n\n```shell\n./openwrt-uml-vmlinux ubd0=openwrt-uml-squashfs.img\n```\n\nThe uml will start and eventually the serial console of the uml will be at your\nconsole prompt. If you would like it in xterms, substitute `con=xterm` and\n`con0=xterm`. **No networking is configured** but it's a starting point. The\nresulting file system has just enough free space to start kicking the tires and\nplaying in the world of 'embedded routers' along with all the resource\nrestrictions that come with that world.  \n\nTo configure networking and more refer to the *user mode linux* documentation\nonline. A quick start goes along this line. Install the `uml-utilities`\npackages so you have the `uml_switch` in and running, then add a command param\nto your uml start like this:\n\n```shell\neth0=daemon,00:01:01:01:01:01,unix,/<your uml switch control socket here>\n```\n\nWith that in, and uml networking actually functional (can be a challenge at\ntimes), you should be able to `ifconfig` the interface and talk to the host\nside or if you bridged the uml switch to your host network, you should be able\nto run `udhcp` and be away with networking off to the world. Again, if you are\nunfamiliar with uml and uml networking, please read the docs and how-to stuff\navailable on the net. It does take some fiddling to get it started and working\nright the first time, but after that, it opens up a whole new world of virtual\nmachines.\n\nhttp://user-mode-linux.sourceforge.net/\n"
  },
  {
    "path": "target/linux/uml/base-files/etc/inittab",
    "content": "# Copyright (c) 2013 The Linux Foundation. All rights reserved.\n::sysinit:/etc/init.d/rcS S boot\n::shutdown:/etc/init.d/rcS K shutdown\ntty0::askfirst:/usr/libexec/login.sh\n"
  },
  {
    "path": "target/linux/uml/config-5.10",
    "content": "CONFIG_3_LEVEL_PGTABLES=y\nCONFIG_64BIT=y\nCONFIG_ARCH_DMA_ADDR_T_64BIT=y\nCONFIG_ARCH_NO_PREEMPT=y\nCONFIG_BLK_DEV_COW_COMMON=y\nCONFIG_BLK_DEV_LOOP=y\nCONFIG_BLK_DEV_UBD=y\nCONFIG_BLK_DEV_UBD_SYNC=y\nCONFIG_BLK_MQ_VIRTIO=y\nCONFIG_BLK_SCSI_REQUEST=y\nCONFIG_CDROM=y\n# CONFIG_COMMON_CLK is not set\n# CONFIG_COMPAT_32BIT_TIME is not set\nCONFIG_CON_CHAN=\"xterm\"\nCONFIG_CON_ZERO_CHAN=\"fd:0,fd:1\"\nCONFIG_CPU_SUP_AMD=y\nCONFIG_CPU_SUP_CENTAUR=y\nCONFIG_CPU_SUP_HYGON=y\nCONFIG_CPU_SUP_INTEL=y\nCONFIG_CPU_SUP_ZHAOXIN=y\nCONFIG_CRC16=y\nCONFIG_CRYPTO_CRC32=y\nCONFIG_CRYPTO_CRC32C=y\nCONFIG_CRYPTO_LIB_POLY1305_RSIZE=11\nCONFIG_CRYPTO_RNG2=y\nCONFIG_CRYPTO_SHA1=y\n# CONFIG_CRYPTO_TWOFISH_X86_64 is not set\nCONFIG_DEBUG_MEMORY_INIT=y\nCONFIG_DECOMPRESS_BZIP2=y\nCONFIG_DECOMPRESS_GZIP=y\nCONFIG_DNOTIFY=y\n# CONFIG_EARLY_PRINTK is not set\nCONFIG_EXT4_FS=y\nCONFIG_F2FS_FS=y\nCONFIG_FAILOVER=y\nCONFIG_FS_IOMAP=y\nCONFIG_FS_MBCACHE=y\nCONFIG_FW_LOADER_PAGED_BUF=y\nCONFIG_GENERIC_CLOCKEVENTS=y\n# CONFIG_GENERIC_CPU is not set\nCONFIG_GENERIC_CPU_DEVICES=y\nCONFIG_GENERIC_FIND_FIRST_BIT=y\nCONFIG_GENERIC_IRQ_SHOW=y\nCONFIG_HOSTFS=y\nCONFIG_HVC_DRIVER=y\nCONFIG_HW_RANDOM=y\nCONFIG_HZ_PERIODIC=y\nCONFIG_IA32_FEAT_CTL=y\nCONFIG_INITRAMFS_SOURCE=\"\"\nCONFIG_INIT_ENV_ARG_LIMIT=128\nCONFIG_IRQ_WORK=y\nCONFIG_ISO9660_FS=y\nCONFIG_JBD2=y\n# CONFIG_JFFS2_FS is not set\nCONFIG_KALLSYMS=y\nCONFIG_KERNEL_STACK_ORDER=2\nCONFIG_LOCK_DEBUGGING_SUPPORT=y\n# CONFIG_MATOM is not set\nCONFIG_MAY_HAVE_RUNTIME_DEPS=y\nCONFIG_MCONSOLE=y\n# CONFIG_MCORE2 is not set\nCONFIG_MEMFD_CREATE=y\nCONFIG_MIGRATION=y\nCONFIG_MK8=y\n# CONFIG_MMAPPER is not set\nCONFIG_MODULES_USE_ELF_RELA=y\n# CONFIG_MPSC is not set\nCONFIG_NAMESPACES=y\nCONFIG_NEED_PER_CPU_KM=y\nCONFIG_NET_FAILOVER=y\n# CONFIG_NET_NS is not set\nCONFIG_NLS=y\nCONFIG_NO_DMA=y\nCONFIG_NO_IOMEM=y\nCONFIG_NR_CPUS=1\nCONFIG_NULL_CHAN=y\n# CONFIG_OF is not set\nCONFIG_PGTABLE_LEVELS=3\nCONFIG_PHYS_ADDR_T_64BIT=y\nCONFIG_PORT_CHAN=y\nCONFIG_POSIX_MQUEUE=y\nCONFIG_POSIX_MQUEUE_SYSCTL=y\n# CONFIG_PROCESSOR_SELECT is not set\nCONFIG_PROC_PAGE_MONITOR=y\nCONFIG_PTY_CHAN=y\nCONFIG_RD_BZIP2=y\nCONFIG_RD_GZIP=y\nCONFIG_RELAY=y\nCONFIG_SOFT_WATCHDOG=m\nCONFIG_SRCU=y\nCONFIG_SSL=y\nCONFIG_SSL_CHAN=\"pty\"\nCONFIG_STACKTRACE=y\nCONFIG_STDERR_CONSOLE=y\nCONFIG_TICK_CPU_ACCOUNTING=y\nCONFIG_TINY_SRCU=y\nCONFIG_TTY_CHAN=y\nCONFIG_UML=y\nCONFIG_UML_NET=y\nCONFIG_UML_NET_DAEMON=y\nCONFIG_UML_NET_DETERMINISTIC_MAC=y\nCONFIG_UML_NET_ETHERTAP=y\nCONFIG_UML_NET_MCAST=y\n# CONFIG_UML_NET_PCAP is not set\nCONFIG_UML_NET_SLIP=y\nCONFIG_UML_NET_SLIRP=y\nCONFIG_UML_NET_TUNTAP=y\n# CONFIG_UML_NET_VDE is not set\nCONFIG_UML_NET_VECTOR=y\nCONFIG_UML_RANDOM=y\n# CONFIG_UML_SOUND is not set\nCONFIG_UML_TIME_TRAVEL_SUPPORT=y\nCONFIG_UML_WATCHDOG=y\nCONFIG_UML_X86=y\n# CONFIG_USER_NS is not set\nCONFIG_VIRTIO=y\nCONFIG_VIRTIO_BLK=y\nCONFIG_VIRTIO_CONSOLE=y\nCONFIG_VIRTIO_NET=y\nCONFIG_VIRTIO_UML=y\nCONFIG_VM_EVENT_COUNTERS=y\nCONFIG_WATCHDOG_CORE=y\nCONFIG_X86_64=y\nCONFIG_X86_CMOV=y\nCONFIG_X86_CMPXCHG64=y\nCONFIG_X86_INTEL_USERCOPY=y\nCONFIG_X86_INTERNODE_CACHE_SHIFT=6\nCONFIG_X86_L1_CACHE_SHIFT=6\nCONFIG_X86_MINIMUM_CPU_FAMILY=64\nCONFIG_X86_TSC=y\nCONFIG_X86_USE_PPRO_CHECKSUM=y\nCONFIG_XTERM_CHAN=y\nCONFIG_ZLIB_INFLATE=y\n"
  },
  {
    "path": "target/linux/uml/files/arch/um/include/uapi/asm/Kbuild",
    "content": ""
  },
  {
    "path": "target/linux/uml/image/Makefile",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2006-2010 OpenWrt.org\n\ninclude $(TOPDIR)/rules.mk\ninclude $(INCLUDE_DIR)/image.mk\n\ndefine Image/Prepare\n\tcp $(LINUX_DIR)/linux $(KDIR)/vmlinux.elf\nendef\n\ndefine Image/Build/squashfs\n\tdd if=/dev/zero of=$(KDIR)/root.squashfs bs=1024k count=0 seek=$(CONFIG_TARGET_ROOTFS_PARTSIZE)\nendef\n\ndefine Image/Build\n\t$(call Image/Build/$(1))\n\tcp $(KDIR)/root.$(1) $(BIN_DIR)/$(IMG_PREFIX)-$(1).img\n\tcp $(KDIR)/vmlinux.elf $(BIN_DIR)/$(IMG_PREFIX)-vmlinux\nendef\n\n$(eval $(call BuildImage))\n\n# UML requires linking against several glibc static libraries: libutil, librt\n# and libpthread, check that here. We do not check against libpthread\n# specifically because getting something to build that references a libpthread\n# symbol is pretty involved and Linux distributions package these 3 libraries\n# in the same package.\n\n$(eval $(call TestHostCommand,glibc-static, \\\n\tPlease install a static glibc package. (Missing libutil.a, librt.a or libpthread.a), \\\n\techo 'int main(int argc, char **argv) { login(0); timer_gettime(0, 0); return 0; }' | \\\n\t\tgcc -include utmp.h -x c -o $(TMP_DIR)/a.out - -static -lutil -lrt))\n"
  },
  {
    "path": "target/linux/uml/patches-5.10/101-mconsole-exec.patch",
    "content": "#\n# Minimalist mconsole exec patch \n#\n# 3.10 version (with bit more synchronous behavior) by fingon at iki dot fi\n# Adaptation to kernel 3.3.8 made by David Fernández (david at dit.upm.es) for \n# Starting point: mconsole-exec-2.6.30.patch for kernel 2.6.30\n# Author of original patch: Paolo Giarrusso, aka Blaisorblade \n#                           (http://www.user-mode-linux.org/~blaisorblade)\n#\n# Known misfeatures:\n#\n# - If output is too long, blocks (and breaks horribly) \n# (this misfeature from 3.10 patches, when minimalizing the patch;\n#  workaround: redirect to a shared filesystem if long output is expected)\n#\n# - Nothing useful is done with stdin\n#\n--- a/arch/um/drivers/mconsole.h\n+++ b/arch/um/drivers/mconsole.h\n@@ -85,6 +85,7 @@ extern void mconsole_cad(struct mc_reque\n extern void mconsole_stop(struct mc_request *req);\n extern void mconsole_go(struct mc_request *req);\n extern void mconsole_log(struct mc_request *req);\n+extern void mconsole_exec(struct mc_request *req);\n extern void mconsole_proc(struct mc_request *req);\n extern void mconsole_stack(struct mc_request *req);\n \n--- a/arch/um/drivers/mconsole_kern.c\n+++ b/arch/um/drivers/mconsole_kern.c\n@@ -4,6 +4,7 @@\n  * Copyright (C) 2001 - 2008 Jeff Dike (jdike@{addtoit,linux.intel}.com)\n  */\n \n+#include <linux/kmod.h>\n #include <linux/console.h>\n #include <linux/ctype.h>\n #include <linux/string.h>\n@@ -26,6 +27,7 @@\n #include <linux/mount.h>\n #include <linux/file.h>\n #include <linux/uaccess.h>\n+#include <linux/completion.h>\n #include <asm/switch_to.h>\n \n #include <init.h>\n@@ -123,6 +125,59 @@ void mconsole_log(struct mc_request *req\n \tmconsole_reply(req, \"\", 0, 0);\n }\n \n+void mconsole_exec(struct mc_request *req)\n+{\n+  struct subprocess_info *sub_info;\n+  int res, len;\n+  struct file *out;\n+  char buf[MCONSOLE_MAX_DATA];\n+\n+  char *envp[] = {\n+    \"HOME=/\", \"TERM=linux\",\n+    \"PATH=/sbin:/bin:/usr/sbin:/usr/bin:/usr/local/sbin:/usr/local/bin\",\n+    NULL\n+  };\n+  char *argv[] = {\n+    \"/bin/sh\", \"-c\",\n+    req->request.data + strlen(\"exec \"),\n+    NULL\n+  };\n+\n+  sub_info = call_usermodehelper_setup(\"/bin/sh\", argv, envp, GFP_ATOMIC, NULL, NULL, NULL);\n+  if (sub_info == NULL) {\n+    mconsole_reply(req, \"call_usermodehelper_setup failed\", 1, 0);\n+    return;\n+  }\n+  res = call_usermodehelper_stdoutpipe(sub_info, &out);\n+  if (res < 0) {\n+    kfree(sub_info);\n+    mconsole_reply(req, \"call_usermodehelper_stdoutpipe failed\", 1, 0);\n+    return;\n+  }\n+\n+  res = call_usermodehelper_exec(sub_info, UMH_WAIT_PROC);\n+  if (res < 0) {\n+    kfree(sub_info);\n+    mconsole_reply(req, \"call_usermodehelper_exec failed\", 1, 0);\n+    return;\n+  }\n+\n+  for (;;) {\n+    len = out->f_op->read(out, buf, sizeof(buf), &out->f_pos);\n+    if (len < 0) {\n+      mconsole_reply(req, \"reading output failed\", 1, 0);\n+      break;\n+    }\n+    if (len == 0)\n+      break;\n+    mconsole_reply_len(req, buf, len, 0, 1);\n+  }\n+  fput(out);\n+\n+  mconsole_reply_len(req, NULL, 0, 0, 0);\n+}\n+\n+\n void mconsole_proc(struct mc_request *req)\n {\n \tstruct vfsmount *mnt = proc_mnt;\n@@ -189,6 +244,7 @@ void mconsole_proc(struct mc_request *re\n     stop - pause the UML; it will do nothing until it receives a 'go' \\n\\\n     go - continue the UML after a 'stop' \\n\\\n     log <string> - make UML enter <string> into the kernel log\\n\\\n+    exec <string> - pass <string> to /bin/sh -c synchronously\\n\\\n     proc <file> - returns the contents of the UML's /proc/<file>\\n\\\n     stack <pid> - returns the stack of the specified pid\\n\\\n \"\n--- a/arch/um/drivers/mconsole_user.c\n+++ b/arch/um/drivers/mconsole_user.c\n@@ -30,6 +30,7 @@ static struct mconsole_command commands[\n \t{ \"stop\", mconsole_stop, MCONSOLE_PROC },\n \t{ \"go\", mconsole_go, MCONSOLE_INTR },\n \t{ \"log\", mconsole_log, MCONSOLE_INTR },\n+\t{ \"exec\", mconsole_exec, MCONSOLE_PROC },\n \t{ \"proc\", mconsole_proc, MCONSOLE_PROC },\n \t{ \"stack\", mconsole_stack, MCONSOLE_INTR },\n };\n--- a/arch/um/os-Linux/file.c\n+++ b/arch/um/os-Linux/file.c\n@@ -560,6 +560,8 @@ int os_create_unix_socket(const char *fi\n \n \taddr.sun_family = AF_UNIX;\n \n+\tif (len > sizeof(addr.sun_path))\n+\t\tlen = sizeof(addr.sun_path);\n \tsnprintf(addr.sun_path, len, \"%s\", file);\n \n \terr = bind(sock, (struct sockaddr *) &addr, sizeof(addr));\n--- a/include/linux/kmod.h\n+++ b/include/linux/kmod.h\n@@ -32,4 +32,6 @@ static inline int request_module_nowait(\n #define try_then_request_module(x, mod...) (x)\n #endif\n \n+int call_usermodehelper_stdoutpipe(struct subprocess_info *sub_info, struct file **filp);\n+\n #endif /* __LINUX_KMOD_H__ */\n--- a/include/linux/umh.h\n+++ b/include/linux/umh.h\n@@ -22,6 +22,7 @@ struct subprocess_info {\n \tconst char *path;\n \tchar **argv;\n \tchar **envp;\n+\tstruct file *stdout;\n \tint wait;\n \tint retval;\n \tint (*init)(struct subprocess_info *info, struct cred *new);\n--- a/kernel/umh.c\n+++ b/kernel/umh.c\n@@ -27,6 +27,7 @@\n #include <linux/ptrace.h>\n #include <linux/async.h>\n #include <linux/uaccess.h>\n+#include <linux/pipe_fs_i.h>\n \n #include <trace/events/module.h>\n \n@@ -72,6 +73,28 @@ static int call_usermodehelper_exec_asyn\n \tflush_signal_handlers(current, 1);\n \tspin_unlock_irq(&current->sighand->siglock);\n \n+\t/* Install output when needed */\n+\tif (sub_info->stdout) {\n+\t\tstruct files_struct *f = current->files;\n+\t\tstruct fdtable *fdt;\n+\n+\t\tsys_close(1);\n+\t\tsys_close(2);\n+\t\tget_file(sub_info->stdout);\n+\t\tfd_install(1, sub_info->stdout);\n+\t\tfd_install(2, sub_info->stdout);\n+\t\tspin_lock(&f->file_lock);\n+\t\tfdt = files_fdtable(f);\n+\t\t__set_bit(1, fdt->open_fds);\n+\t\t__clear_bit(1, fdt->close_on_exec);\n+\t\t__set_bit(2, fdt->open_fds);\n+\t\t__clear_bit(2, fdt->close_on_exec);\n+\t\tspin_unlock(&f->file_lock);\n+\n+\t\t/* disallow core files */\n+\t\tcurrent->signal->rlim[RLIMIT_CORE] = (struct rlimit){0, 0};\n+\t}\n+\n \t/*\n \t * Initial kernel threads share ther FS with init, in order to\n \t * get the init root directory. But we've now created a new\n@@ -330,6 +353,20 @@ static void helper_unlock(void)\n \t\twake_up(&running_helpers_waitq);\n }\n \n+int call_usermodehelper_stdoutpipe(struct subprocess_info *sub_info,\n+\t\t\t\t\tstruct file **filp)\n+{\n+\tstruct file *f[2];\n+\n+\tif (create_pipe_files(f, 0) < 0)\n+\t\t return PTR_ERR(f);\n+\n+\tsub_info->stdout = f[1];\n+\t*filp = f[0];\n+\treturn 0;\n+}\n+EXPORT_SYMBOL(call_usermodehelper_stdoutpipe);\n+\n /**\n  * call_usermodehelper_setup - prepare to call a usermode helper\n  * @path: path to usermode executable\n"
  },
  {
    "path": "target/linux/uml/patches-5.10/102-pseudo-random-mac.patch",
    "content": "===============================================================================\n\nThis patch makes MAC addresses of network interfaces predictable. In\nparticular, it adds a small routine that computes MAC addresses of based on\na SHA1 hash of the virtual machine name and interface ID.\n\nTECHNICAL INFORMATION:\n\nApplies to vanilla kernel 3.9.4.\n\n===============================================================================\n--- a/arch/um/drivers/Kconfig\n+++ b/arch/um/drivers/Kconfig\n@@ -146,6 +146,20 @@ config UML_NET\n \t  enable at least one of the following transport options to actually\n \t  make use of UML networking.\n \n+config UML_NET_DETERMINISTIC_MAC\n+\tbool \"Use deterministic MAC addresses for network interfaces\"\n+\tdefault y\n+\tdepends on UML_NET\n+\tselect CRYPTO_SHA1\n+\thelp\n+        Virtual network devices inside a User-Mode Linux instance must be\n+        assigned a MAC (Ethernet) address. If none is specified on the UML\n+        command line, one must be automatically computed. If this option is\n+        enabled, a randomly generated address is used. Otherwise, if this\n+        option is disabled, the address is generated from a SHA1 hash of\n+        the umid of the UML instance and the interface name. The latter choice\n+        is useful to make MAC addresses predictable.\n+\n config UML_NET_ETHERTAP\n \tbool \"Ethertap transport (obsolete)\"\n \tdepends on UML_NET\n--- a/arch/um/drivers/net_kern.c\n+++ b/arch/um/drivers/net_kern.c\n@@ -25,6 +25,14 @@\n #include <net_kern.h>\n #include <net_user.h>\n \n+#include <crypto/sha.h>\n+#include <crypto/hash.h>\n+#include <linux/string.h>\n+#include <linux/crypto.h>\n+#include <linux/err.h>\n+#include <linux/scatterlist.h>\n+#include \"os.h\"\n+\n #define DRIVER_NAME \"uml-netdev\"\n \n static DEFINE_SPINLOCK(opened_lock);\n@@ -274,9 +282,51 @@ static const struct ethtool_ops uml_net_\n \t.get_ts_info\t= ethtool_op_get_ts_info,\n };\n \n+#ifdef CONFIG_UML_NET_DETERMINISTIC_MAC\n+\n+/* Compute a SHA1 hash of the UML instance's id and\n+ *  * an interface name. */\n+static int compute_hash(const char *umid, const char *ifname, char *hash)\n+{\n+\tstruct ahash_request *desc;\n+\tstruct crypto_ahash *tfm;\n+\tstruct scatterlist sg;\n+\tchar vmif[1024];\n+\tint ret;\n+\n+\tstrcpy (vmif, umid);\n+\tstrcat (vmif, ifname);\n+\n+\ttfm = crypto_alloc_ahash(\"sha1\", 0, CRYPTO_ALG_ASYNC);\n+\tif (IS_ERR(tfm))\n+\t\treturn -ENOMEM;\n+\n+\tdesc = ahash_request_alloc(tfm, GFP_KERNEL);\n+\tif (!desc) {\n+\t\tret = -ENOMEM;\n+\t\tgoto out;\n+\t}\n+\n+\tcrypto_ahash_clear_flags(tfm, ~0);\n+\n+\tsg_init_table(&sg, 1);\n+\tsg_set_buf(&sg, vmif, strlen(vmif));\n+\n+\tahash_request_set_crypt(desc, &sg, hash, strlen(vmif));\n+\n+\tret = crypto_ahash_digest(desc);\n+out:\n+\tcrypto_free_ahash(tfm);\n+\n+\treturn ret;\n+}\n+\n+#endif\n+\n void uml_net_setup_etheraddr(struct net_device *dev, char *str)\n {\n \tunsigned char *addr = dev->dev_addr;\n+\tu8 hash[SHA1_DIGEST_SIZE];\n \tchar *end;\n \tint i;\n \n@@ -319,9 +369,26 @@ void uml_net_setup_etheraddr(struct net_\n \treturn;\n \n random:\n+#ifndef CONFIG_UML_NET_DETERMINISTIC_MAC\n \tprintk(KERN_INFO\n \t       \"Choosing a random ethernet address for device %s\\n\", dev->name);\n \teth_hw_addr_random(dev);\n+#else\n+\tprintk(KERN_INFO\n+\t       \"Computing a digest to use as ethernet address for device %s\\n\", dev->name);\n+\tif (compute_hash(get_umid(), dev->name, hash) < 0) {\n+\t\tprintk(KERN_WARNING\n+\t\t       \"Could not compute digest to use as ethernet address for device %s. \"\n+\t\t       \"Using random address instead.\\n\", dev->name);\n+\t\trandom_ether_addr(addr);\n+\t}\n+\telse {\n+\t\tfor (i=0; i < 6; i++)\n+\t\t\taddr[i] = (hash[i] + hash[i+6]) % 0x100;\n+\t}\n+\taddr [0] &= 0xfe; /* clear multicast bit */\n+\taddr [0] |= 0x02; /* set local assignment bit (IEEE802) */\n+#endif\n }\n \n static DEFINE_SPINLOCK(devices_lock);\n--- a/kernel/umh.c\n+++ b/kernel/umh.c\n@@ -354,12 +354,12 @@ static void helper_unlock(void)\n }\n \n int call_usermodehelper_stdoutpipe(struct subprocess_info *sub_info,\n-\t\t\t\t\tstruct file **filp)\n+\t\t\t\t   struct file **filp)\n {\n \tstruct file *f[2];\n \n \tif (create_pipe_files(f, 0) < 0)\n-\t\t return PTR_ERR(f);\n+\t\treturn PTR_ERR(f);\n \n \tsub_info->stdout = f[1];\n \t*filp = f[0];\n"
  },
  {
    "path": "target/linux/x86/64/base-files/lib/preinit/45_mount_xenfs",
    "content": "# Copyright (C) 2010 OpenWrt.org\n\ndo_mount_xenfs() {\n\tgrep -q xenfs /proc/filesystems && \\\n\t\tmount -o noatime -t xenfs none /proc/xen\n}\n\nboot_hook_add preinit_mount_root do_mount_xenfs\n"
  },
  {
    "path": "target/linux/x86/64/config-5.10",
    "content": "CONFIG_64BIT=y\nCONFIG_ACPI=y\nCONFIG_ACPI_AC=y\nCONFIG_ACPI_BATTERY=y\n# CONFIG_ACPI_BGRT is not set\nCONFIG_ACPI_BUTTON=y\n# CONFIG_ACPI_CMPC is not set\nCONFIG_ACPI_CONTAINER=y\nCONFIG_ACPI_CPPC_LIB=y\nCONFIG_ACPI_CPU_FREQ_PSS=y\n# CONFIG_ACPI_DEBUG is not set\n# CONFIG_ACPI_DEBUGGER is not set\n# CONFIG_ACPI_DOCK is not set\n# CONFIG_ACPI_DPTF is not set\n# CONFIG_ACPI_EC_DEBUGFS is not set\nCONFIG_ACPI_FAN=y\nCONFIG_ACPI_HOTPLUG_CPU=y\nCONFIG_ACPI_HOTPLUG_IOAPIC=y\n# CONFIG_ACPI_I2C_OPREGION is not set\nCONFIG_ACPI_LEGACY_TABLES_LOOKUP=y\nCONFIG_ACPI_LPIT=y\n# CONFIG_ACPI_PCI_SLOT is not set\nCONFIG_ACPI_PROCESSOR=y\n# CONFIG_ACPI_PROCESSOR_AGGREGATOR is not set\nCONFIG_ACPI_PROCESSOR_CSTATE=y\nCONFIG_ACPI_PROCESSOR_IDLE=y\nCONFIG_ACPI_REV_OVERRIDE_POSSIBLE=y\n# CONFIG_ACPI_SBS is not set\nCONFIG_ACPI_SPCR_TABLE=y\nCONFIG_ACPI_SYSTEM_POWER_STATES_SUPPORT=y\n# CONFIG_ACPI_TAD is not set\nCONFIG_ACPI_THERMAL=y\nCONFIG_ACPI_VIDEO=y\n# CONFIG_ACPI_WMI is not set\n# CONFIG_ACRN_GUEST is not set\nCONFIG_AGP=y\n# CONFIG_AGP_AMD64 is not set\nCONFIG_AGP_INTEL=y\n# CONFIG_AGP_SIS is not set\n# CONFIG_AGP_VIA is not set\nCONFIG_ARCH_CPUIDLE_HALTPOLL=y\nCONFIG_ARCH_DMA_ADDR_T_64BIT=y\nCONFIG_ARCH_MIGHT_HAVE_ACPI_PDC=y\nCONFIG_ARCH_MMAP_RND_BITS=28\nCONFIG_ARCH_MMAP_RND_BITS_MAX=32\nCONFIG_ARCH_MMAP_RND_BITS_MIN=28\nCONFIG_ARCH_SPARSEMEM_DEFAULT=y\nCONFIG_ARCH_WANTS_THP_SWAP=y\nCONFIG_AUDIT_ARCH=y\nCONFIG_BACKLIGHT_CLASS_DEVICE=y\nCONFIG_BALLOON_COMPACTION=y\nCONFIG_BLK_DEV_INTEGRITY=y\nCONFIG_BLK_DEV_INTEGRITY_T10=y\nCONFIG_BLK_DEV_NVME=y\nCONFIG_BLK_DEV_SR=y\nCONFIG_BLK_MQ_VIRTIO=y\nCONFIG_BLK_PM=y\n# CONFIG_BOOTPARAM_HOTPLUG_CPU0 is not set\nCONFIG_BTT=y\nCONFIG_CDROM=y\nCONFIG_CONNECTOR=y\nCONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y\nCONFIG_CPU_FREQ_GOV_SCHEDUTIL=y\n# CONFIG_CPU_IDLE_GOV_HALTPOLL is not set\nCONFIG_CPU_RMAP=y\nCONFIG_CRC_T10DIF=y\nCONFIG_CRYPTO_AES_NI_INTEL=y\n# CONFIG_CRYPTO_BLOWFISH_X86_64 is not set\n# CONFIG_CRYPTO_CAMELLIA_AESNI_AVX2_X86_64 is not set\n# CONFIG_CRYPTO_CAMELLIA_AESNI_AVX_X86_64 is not set\n# CONFIG_CRYPTO_CAMELLIA_X86_64 is not set\n# CONFIG_CRYPTO_CAST5_AVX_X86_64 is not set\n# CONFIG_CRYPTO_CAST6_AVX_X86_64 is not set\nCONFIG_CRYPTO_CRCT10DIF=y\n# CONFIG_CRYPTO_CRCT10DIF_PCLMUL is not set\nCONFIG_CRYPTO_CRYPTD=y\n# CONFIG_CRYPTO_DES3_EDE_X86_64 is not set\nCONFIG_CRYPTO_ECB=y\nCONFIG_CRYPTO_GLUE_HELPER_X86=y\nCONFIG_CRYPTO_LIB_POLY1305_RSIZE=11\nCONFIG_CRYPTO_LRW=y\n# CONFIG_CRYPTO_NHPOLY1305_AVX2 is not set\n# CONFIG_CRYPTO_NHPOLY1305_SSE2 is not set\n# CONFIG_CRYPTO_SERPENT_AVX2_X86_64 is not set\n# CONFIG_CRYPTO_SERPENT_AVX_X86_64 is not set\n# CONFIG_CRYPTO_SERPENT_SSE2_X86_64 is not set\n# CONFIG_CRYPTO_SHA1_SSSE3 is not set\n# CONFIG_CRYPTO_SHA256_SSSE3 is not set\n# CONFIG_CRYPTO_SHA512_SSSE3 is not set\nCONFIG_CRYPTO_SIMD=y\n# CONFIG_CRYPTO_TWOFISH_AVX_X86_64 is not set\n# CONFIG_CRYPTO_TWOFISH_X86_64 is not set\n# CONFIG_CRYPTO_TWOFISH_X86_64_3WAY is not set\nCONFIG_CRYPTO_XTS=y\n# CONFIG_DEBUG_HOTPLUG_CPU0 is not set\nCONFIG_DMA_ACPI=y\nCONFIG_DMA_OPS=y\nCONFIG_DMA_SHARED_BUFFER=y\nCONFIG_DRM=y\nCONFIG_DRM_BOCHS=y\nCONFIG_DRM_BRIDGE=y\nCONFIG_DRM_FBDEV_EMULATION=y\nCONFIG_DRM_FBDEV_OVERALLOC=100\nCONFIG_DRM_GEM_SHMEM_HELPER=y\nCONFIG_DRM_I915=y\nCONFIG_DRM_I915_CAPTURE_ERROR=y\nCONFIG_DRM_I915_COMPRESS_ERROR=y\n# CONFIG_DRM_I915_DEBUG is not set\n# CONFIG_DRM_I915_DEBUG_GUC is not set\n# CONFIG_DRM_I915_DEBUG_MMIO is not set\n# CONFIG_DRM_I915_DEBUG_RUNTIME_PM is not set\n# CONFIG_DRM_I915_DEBUG_VBLANK_EVADE is not set\nCONFIG_DRM_I915_FENCE_TIMEOUT=10000\nCONFIG_DRM_I915_FORCE_PROBE=\"\"\nCONFIG_DRM_I915_GVT=y\nCONFIG_DRM_I915_HEARTBEAT_INTERVAL=2500\n# CONFIG_DRM_I915_LOW_LEVEL_TRACEPOINTS is not set\nCONFIG_DRM_I915_MAX_REQUEST_BUSYWAIT=8000\nCONFIG_DRM_I915_PREEMPT_TIMEOUT=640\n# CONFIG_DRM_I915_SELFTEST is not set\nCONFIG_DRM_I915_STOP_TIMEOUT=100\n# CONFIG_DRM_I915_SW_FENCE_CHECK_DAG is not set\n# CONFIG_DRM_I915_SW_FENCE_DEBUG_OBJECTS is not set\nCONFIG_DRM_I915_TIMESLICE_DURATION=1\nCONFIG_DRM_I915_USERFAULT_AUTOSUSPEND=250\nCONFIG_DRM_I915_USERPTR=y\n# CONFIG_DRM_I915_WERROR is not set\nCONFIG_DRM_KMS_FB_HELPER=y\nCONFIG_DRM_KMS_HELPER=y\nCONFIG_DRM_MIPI_DSI=y\nCONFIG_DRM_PANEL=y\nCONFIG_DRM_PANEL_BRIDGE=y\nCONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y\nCONFIG_DRM_TTM=y\nCONFIG_DRM_TTM_DMA_PAGE_POOL=y\nCONFIG_DRM_TTM_HELPER=y\nCONFIG_DRM_VIRTIO_GPU=y\nCONFIG_DRM_VRAM_HELPER=y\nCONFIG_EFI=y\nCONFIG_EFIVAR_FS=m\n# CONFIG_EFI_BOOTLOADER_CONTROL is not set\n# CONFIG_EFI_CAPSULE_LOADER is not set\n# CONFIG_EFI_CUSTOM_SSDT_OVERLAYS is not set\n# CONFIG_EFI_DISABLE_PCI_DMA is not set\nCONFIG_EFI_EARLYCON=y\nCONFIG_EFI_ESRT=y\n# CONFIG_EFI_FAKE_MEMMAP is not set\nCONFIG_EFI_GENERIC_STUB_INITRD_CMDLINE_LOADER=y\n# CONFIG_EFI_MIXED is not set\n# CONFIG_EFI_PGT_DUMP is not set\n# CONFIG_EFI_RCI2_TABLE is not set\nCONFIG_EFI_RUNTIME_MAP=y\nCONFIG_EFI_RUNTIME_WRAPPERS=y\nCONFIG_EFI_STUB=y\n# CONFIG_EFI_TEST is not set\n# CONFIG_EFI_VARS is not set\nCONFIG_FAILOVER=y\nCONFIG_FB=y\nCONFIG_FB_CFB_COPYAREA=y\nCONFIG_FB_CFB_FILLRECT=y\nCONFIG_FB_CFB_IMAGEBLIT=y\nCONFIG_FB_CMDLINE=y\nCONFIG_FB_DEFERRED_IO=y\nCONFIG_FB_EFI=y\nCONFIG_FB_HYPERV=y\nCONFIG_FB_MODE_HELPERS=y\nCONFIG_FB_SIMPLE=y\nCONFIG_FB_SYS_COPYAREA=y\nCONFIG_FB_SYS_FILLRECT=y\nCONFIG_FB_SYS_FOPS=y\nCONFIG_FB_SYS_IMAGEBLIT=y\nCONFIG_FB_TILEBLITTING=y\n# CONFIG_FB_VESA is not set\nCONFIG_FONT_8x16=y\nCONFIG_FONT_8x8=y\nCONFIG_FONT_SUPPORT=y\nCONFIG_FRAMEBUFFER_CONSOLE=y\nCONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y\n# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set\nCONFIG_FREEZER=y\nCONFIG_FUSION_SAS=y\nCONFIG_FW_CACHE=y\nCONFIG_GART_IOMMU=y\nCONFIG_GENERIC_BUG_RELATIVE_POINTERS=y\nCONFIG_GENERIC_CPU=y\nCONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y\nCONFIG_GENERIC_IRQ_MIGRATION=y\nCONFIG_GENERIC_PENDING_IRQ=y\nCONFIG_GPIOLIB=y\nCONFIG_GPIO_ACPI=y\nCONFIG_GPIO_ICH=y\nCONFIG_GPIO_SCH=y\nCONFIG_HALTPOLL_CPUIDLE=y\nCONFIG_HARDLOCKUP_CHECK_TIMESTAMP=y\nCONFIG_HDMI=y\nCONFIG_HIBERNATE_CALLBACKS=y\nCONFIG_HID_BATTERY_STRENGTH=y\nCONFIG_HID_GENERIC=y\nCONFIG_HID_HYPERV_MOUSE=y\nCONFIG_HOTPLUG_CPU=y\nCONFIG_HOTPLUG_PCI=y\nCONFIG_HOTPLUG_PCI_ACPI=y\n# CONFIG_HOTPLUG_PCI_ACPI_IBM is not set\n# CONFIG_HOTPLUG_PCI_CPCI is not set\n# CONFIG_HOTPLUG_PCI_PCIE is not set\n# CONFIG_HOTPLUG_PCI_SHPC is not set\nCONFIG_HOTPLUG_SMT=y\nCONFIG_HPET=y\nCONFIG_HPET_MMAP=y\n# CONFIG_HP_ACCEL is not set\nCONFIG_HVC_DRIVER=y\nCONFIG_HVC_IRQ=y\nCONFIG_HVC_XEN=y\nCONFIG_HVC_XEN_FRONTEND=y\nCONFIG_HWMON=y\nCONFIG_HWMON_VID=y\nCONFIG_HW_RANDOM_AMD=y\nCONFIG_HW_RANDOM_INTEL=y\nCONFIG_HW_RANDOM_VIRTIO=y\nCONFIG_HYPERV=y\nCONFIG_HYPERVISOR_GUEST=y\nCONFIG_HYPERV_BALLOON=y\nCONFIG_HYPERV_KEYBOARD=y\nCONFIG_HYPERV_NET=y\nCONFIG_HYPERV_STORAGE=y\n# CONFIG_HYPERV_TESTING is not set\nCONFIG_HYPERV_TIMER=y\nCONFIG_HYPERV_UTILS=y\n# CONFIG_HYPERV_VSOCKETS is not set\nCONFIG_I2C=y\nCONFIG_I2C_ALGOBIT=y\n# CONFIG_I2C_AMD_MP2 is not set\nCONFIG_I2C_BOARDINFO=y\n# CONFIG_I2C_MULTI_INSTANTIATE is not set\n# CONFIG_IA32_EMULATION is not set\nCONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000\n# CONFIG_IMA_SECURE_AND_OR_TRUSTED_BOOT is not set\nCONFIG_INPUT_XEN_KBDDEV_FRONTEND=y\nCONFIG_INTEL_GTT=y\nCONFIG_INTEL_IDLE=y\n# CONFIG_INTEL_IDXD is not set\n# CONFIG_INTEL_IPS is not set\n# CONFIG_INTEL_MEI_HDCP is not set\n# CONFIG_INTEL_MENLOW is not set\nCONFIG_INTEL_PCH_THERMAL=y\n# CONFIG_INTEL_SCU_PLATFORM is not set\nCONFIG_INTEL_SOC_DTS_IOSF_CORE=y\nCONFIG_INTEL_SOC_DTS_THERMAL=y\n# CONFIG_INTEL_SPEED_SELECT_INTERFACE is not set\n# CONFIG_INTEL_TURBO_MAX_3 is not set\n# CONFIG_INTEL_UNCORE_FREQ_CONTROL is not set\nCONFIG_INTERVAL_TREE=y\n# CONFIG_IOMMU_DEBUG is not set\nCONFIG_IOMMU_HELPER=y\nCONFIG_IOSF_MBI=y\n# CONFIG_IOSF_MBI_DEBUG is not set\n# CONFIG_ISCSI_IBFT is not set\nCONFIG_ISO9660_FS=y\nCONFIG_KALLSYMS_ABSOLUTE_PERCPU=y\nCONFIG_KCMP=y\nCONFIG_KVM_GUEST=y\nCONFIG_LEDS_GPIO=y\n# CONFIG_LEGACY_VSYSCALL_EMULATE is not set\nCONFIG_LEGACY_VSYSCALL_NONE=y\n# CONFIG_LEGACY_VSYSCALL_XONLY is not set\nCONFIG_LIBNVDIMM=y\nCONFIG_LOCK_SPIN_ON_OWNER=y\nCONFIG_LPC_ICH=y\nCONFIG_LPC_SCH=y\nCONFIG_MAILBOX=y\n# CONFIG_MAXSMP is not set\nCONFIG_MEMORY_BALLOON=y\nCONFIG_MEMREGION=y\nCONFIG_MFD_CORE=y\n# CONFIG_MFD_INTEL_LPSS_ACPI is not set\n# CONFIG_MFD_INTEL_PMC_BXT is not set\nCONFIG_MMC=y\nCONFIG_MMC_BLOCK=y\nCONFIG_MMC_CQHCI=y\nCONFIG_MMC_RICOH_MMC=y\nCONFIG_MMC_SDHCI=y\nCONFIG_MMC_SDHCI_ACPI=y\nCONFIG_MMC_SDHCI_IO_ACCESSORS=y\nCONFIG_MMC_SDHCI_PCI=y\n# CONFIG_MMC_SDHCI_PLTFM is not set\n# CONFIG_MMC_WBSD is not set\nCONFIG_MMU_NOTIFIER=y\nCONFIG_MODULES_USE_ELF_RELA=y\n# CONFIG_MPSC is not set\nCONFIG_MUTEX_SPIN_ON_OWNER=y\nCONFIG_ND_BLK=y\nCONFIG_ND_BTT=y\nCONFIG_ND_CLAIM=y\nCONFIG_NEED_DMA_MAP_STATE=y\nCONFIG_NET_FAILOVER=y\nCONFIG_NET_FLOW_LIMIT=y\n# CONFIG_NITRO_ENCLAVES is not set\nCONFIG_NR_CPUS=512\nCONFIG_NR_CPUS_DEFAULT=512\nCONFIG_NR_CPUS_RANGE_BEGIN=2\nCONFIG_NR_CPUS_RANGE_END=512\nCONFIG_NVME_CORE=y\n# CONFIG_NVME_HWMON is not set\nCONFIG_NVME_MULTIPATH=y\n# CONFIG_NVME_TCP is not set\nCONFIG_OUTPUT_FORMAT=\"elf64-x86-64\"\nCONFIG_PADATA=y\nCONFIG_PAGE_POOL=y\nCONFIG_PAGE_REPORTING=y\nCONFIG_PAGE_TABLE_ISOLATION=y\nCONFIG_PARAVIRT=y\nCONFIG_PARAVIRT_CLOCK=y\n# CONFIG_PARAVIRT_DEBUG is not set\nCONFIG_PARAVIRT_SPINLOCKS=y\nCONFIG_PARAVIRT_XXL=y\nCONFIG_PATA_AMD=y\nCONFIG_PATA_ATIIXP=y\nCONFIG_PATA_MPIIX=y\nCONFIG_PATA_OLDPIIX=y\nCONFIG_PATA_PLATFORM=y\nCONFIG_PATA_TIMINGS=y\nCONFIG_PATA_VIA=y\nCONFIG_PCC=y\n# CONFIG_PCENGINES_APU2 is not set\nCONFIG_PCIEAER=y\nCONFIG_PCIEPORTBUS=y\nCONFIG_PCIE_PME=y\nCONFIG_PCI_HYPERV=y\nCONFIG_PCI_HYPERV_INTERFACE=y\n# CONFIG_PCI_MMCONFIG is not set\nCONFIG_PCI_XEN=y\nCONFIG_PGTABLE_LEVELS=4\nCONFIG_PHYSICAL_ALIGN=0x1000000\nCONFIG_PHYS_ADDR_T_64BIT=y\nCONFIG_PINCTRL=y\n# CONFIG_PINCTRL_BAYTRAIL is not set\n# CONFIG_PINCTRL_BROXTON is not set\n# CONFIG_PINCTRL_CANNONLAKE is not set\n# CONFIG_PINCTRL_CHERRYVIEW is not set\n# CONFIG_PINCTRL_DENVERTON is not set\n# CONFIG_PINCTRL_EMMITSBURG is not set\n# CONFIG_PINCTRL_GEMINILAKE is not set\n# CONFIG_PINCTRL_JASPERLAKE is not set\n# CONFIG_PINCTRL_LEWISBURG is not set\n# CONFIG_PINCTRL_LYNXPOINT is not set\n# CONFIG_PINCTRL_SUNRISEPOINT is not set\n# CONFIG_PINCTRL_TIGERLAKE is not set\nCONFIG_PM=y\n# CONFIG_PMIC_OPREGION is not set\nCONFIG_PM_CLK=y\nCONFIG_PM_SLEEP=y\nCONFIG_PM_SLEEP_SMP=y\nCONFIG_PNP=y\nCONFIG_PNPACPI=y\nCONFIG_PNP_DEBUG_MESSAGES=y\nCONFIG_PROC_EVENTS=y\nCONFIG_PVH=y\nCONFIG_QUEUED_RWLOCKS=y\nCONFIG_QUEUED_SPINLOCKS=y\nCONFIG_RAS=y\nCONFIG_RELAY=y\nCONFIG_RELOCATABLE=y\nCONFIG_RESET_ATTACK_MITIGATION=y\nCONFIG_RFS_ACCEL=y\nCONFIG_RPS=y\nCONFIG_RTC_I2C_AND_SPI=y\nCONFIG_RWSEM_SPIN_ON_OWNER=y\n# CONFIG_SAMSUNG_Q10 is not set\nCONFIG_SATA_AHCI=y\nCONFIG_SCHED_MC=y\nCONFIG_SCHED_MC_PRIO=y\nCONFIG_SCHED_SMT=y\nCONFIG_SCSI_VIRTIO=y\n# CONFIG_SENSORS_AMD_ENERGY is not set\nCONFIG_SENSORS_CORETEMP=y\nCONFIG_SENSORS_FAM15H_POWER=y\nCONFIG_SENSORS_I5500=y\nCONFIG_SENSORS_K10TEMP=y\nCONFIG_SENSORS_K8TEMP=y\nCONFIG_SENSORS_VIA_CPUTEMP=y\nCONFIG_SERIAL_8250_PNP=y\nCONFIG_SERIAL_MCTRL_GPIO=y\nCONFIG_SMP=y\nCONFIG_SPARSEMEM=y\nCONFIG_SPARSEMEM_EXTREME=y\nCONFIG_SPARSEMEM_MANUAL=y\n# CONFIG_SPARSEMEM_VMEMMAP is not set\nCONFIG_SPARSEMEM_VMEMMAP_ENABLE=y\nCONFIG_STACK_VALIDATION=y\n# CONFIG_SURFACE_3_POWER_OPREGION is not set\n# CONFIG_SURFACE_PRO3_BUTTON is not set\nCONFIG_SWIOTLB=y\nCONFIG_SWIOTLB_XEN=y\nCONFIG_SYNC_FILE=y\n# CONFIG_SYSTEM76_ACPI is not set\nCONFIG_SYS_HYPERVISOR=y\nCONFIG_THERMAL_GOV_USER_SPACE=y\nCONFIG_THERMAL_HWMON=y\nCONFIG_THERMAL_WRITABLE_TRIPS=y\n# CONFIG_TOSHIBA_BT_RFKILL is not set\nCONFIG_TREE_RCU=y\nCONFIG_TREE_SRCU=y\n# CONFIG_UCLAMP_TASK is not set\nCONFIG_UCS2_STRING=y\n# CONFIG_UNWINDER_ORC is not set\nCONFIG_USB_STORAGE=y\nCONFIG_VIRTIO=y\nCONFIG_VIRTIO_BALLOON=y\nCONFIG_VIRTIO_BLK=y\nCONFIG_VIRTIO_CONSOLE=y\nCONFIG_VIRTIO_DMA_SHARED_BUFFER=y\nCONFIG_VIRTIO_MMIO=y\nCONFIG_VIRTIO_MMIO_CMDLINE_DEVICES=y\nCONFIG_VIRTIO_NET=y\nCONFIG_VIRTIO_PCI=y\nCONFIG_VIRTIO_PCI_LEGACY=y\n# CONFIG_VIRTIO_PMEM is not set\n# CONFIG_VIRTIO_VSOCKETS is not set\nCONFIG_VIRTIO_VSOCKETS_COMMON=y\nCONFIG_VIRT_DRIVERS=y\nCONFIG_VMAP_PFN=y\nCONFIG_VMAP_STACK=y\n# CONFIG_VMD is not set\nCONFIG_VMWARE_BALLOON=y\nCONFIG_VMWARE_PVSCSI=y\nCONFIG_VMWARE_VMCI=y\nCONFIG_VMWARE_VMCI_VSOCKETS=y\nCONFIG_VMXNET3=y\nCONFIG_VSOCKETS=y\nCONFIG_VSOCKETS_LOOPBACK=y\nCONFIG_VT_CONSOLE_SLEEP=y\nCONFIG_WATCHDOG_CORE=y\n# CONFIG_X86_5LEVEL is not set\nCONFIG_X86_64=y\nCONFIG_X86_64_SMP=y\nCONFIG_X86_ACPI_CPUFREQ=y\n# CONFIG_X86_ACPI_CPUFREQ_CPB is not set\nCONFIG_X86_AMD_FREQ_SENSITIVITY=y\n# CONFIG_X86_AMD_PLATFORM_DEVICE is not set\nCONFIG_X86_CPUID=y\nCONFIG_X86_DIRECT_GBPAGES=y\nCONFIG_X86_HV_CALLBACK_VECTOR=y\nCONFIG_X86_INTEL_LPSS=y\n# CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS is not set\nCONFIG_X86_INTEL_PSTATE=y\nCONFIG_X86_MINIMUM_CPU_FAMILY=64\n# CONFIG_X86_PCC_CPUFREQ is not set\nCONFIG_X86_PKG_TEMP_THERMAL=y\n# CONFIG_X86_PMEM_LEGACY is not set\nCONFIG_X86_PM_TIMER=y\n# CONFIG_X86_POWERNOW_K8 is not set\n# CONFIG_X86_VSYSCALL_EMULATION is not set\nCONFIG_X86_X2APIC=y\n# CONFIG_X86_X32 is not set\nCONFIG_XEN=y\nCONFIG_XENFS=y\nCONFIG_XEN_512GB=y\nCONFIG_XEN_ACPI=y\nCONFIG_XEN_ACPI_PROCESSOR=y\nCONFIG_XEN_AUTO_XLATE=y\n# CONFIG_XEN_BACKEND is not set\nCONFIG_XEN_BALLOON=y\nCONFIG_XEN_BLKDEV_FRONTEND=y\nCONFIG_XEN_COMPAT_XENFS=y\nCONFIG_XEN_DEBUG_FS=y\nCONFIG_XEN_DEV_EVTCHN=y\nCONFIG_XEN_DOM0=y\nCONFIG_XEN_EFI=y\nCONFIG_XEN_FBDEV_FRONTEND=y\nCONFIG_XEN_GNTDEV=y\nCONFIG_XEN_GRANT_DEV_ALLOC=y\nCONFIG_XEN_HAVE_PVMMU=y\nCONFIG_XEN_HAVE_VPMU=y\n# CONFIG_XEN_MCE_LOG is not set\nCONFIG_XEN_NETDEV_FRONTEND=y\nCONFIG_XEN_PCIDEV_FRONTEND=y\nCONFIG_XEN_PRIVCMD=y\nCONFIG_XEN_PV=y\nCONFIG_XEN_PVH=y\nCONFIG_XEN_PVHVM=y\nCONFIG_XEN_PVHVM_SMP=y\nCONFIG_XEN_PV_SMP=y\nCONFIG_XEN_SAVE_RESTORE=y\nCONFIG_XEN_SCSI_FRONTEND=y\nCONFIG_XEN_SYMS=y\nCONFIG_XEN_SYS_HYPERVISOR=y\nCONFIG_XEN_WDT=y\nCONFIG_XEN_XENBUS_FRONTEND=y\nCONFIG_XPS=y\nCONFIG_ZLIB_DEFLATE=y\nCONFIG_ZONE_DMA32=y\n"
  },
  {
    "path": "target/linux/x86/64/config-5.15",
    "content": "CONFIG_64BIT=y\nCONFIG_ACPI=y\nCONFIG_ACPI_AC=y\nCONFIG_ACPI_BATTERY=y\n# CONFIG_ACPI_BGRT is not set\nCONFIG_ACPI_BUTTON=y\n# CONFIG_ACPI_CMPC is not set\nCONFIG_ACPI_CONTAINER=y\nCONFIG_ACPI_CPPC_LIB=y\nCONFIG_ACPI_CPU_FREQ_PSS=y\n# CONFIG_ACPI_DEBUG is not set\n# CONFIG_ACPI_DEBUGGER is not set\n# CONFIG_ACPI_DOCK is not set\n# CONFIG_ACPI_DPTF is not set\n# CONFIG_ACPI_EC_DEBUGFS is not set\nCONFIG_ACPI_FAN=y\n# CONFIG_ACPI_FPDT is not set\nCONFIG_ACPI_HOTPLUG_CPU=y\nCONFIG_ACPI_HOTPLUG_IOAPIC=y\n# CONFIG_ACPI_I2C_OPREGION is not set\nCONFIG_ACPI_LEGACY_TABLES_LOOKUP=y\nCONFIG_ACPI_LPIT=y\n# CONFIG_ACPI_PCI_SLOT is not set\nCONFIG_ACPI_PRMT=y\nCONFIG_ACPI_PROCESSOR=y\n# CONFIG_ACPI_PROCESSOR_AGGREGATOR is not set\nCONFIG_ACPI_PROCESSOR_CSTATE=y\nCONFIG_ACPI_PROCESSOR_IDLE=y\nCONFIG_ACPI_REV_OVERRIDE_POSSIBLE=y\n# CONFIG_ACPI_SBS is not set\nCONFIG_ACPI_SPCR_TABLE=y\nCONFIG_ACPI_SYSTEM_POWER_STATES_SUPPORT=y\n# CONFIG_ACPI_TAD is not set\nCONFIG_ACPI_THERMAL=y\nCONFIG_ACPI_VIDEO=y\n# CONFIG_ACPI_WMI is not set\n# CONFIG_ACRN_GUEST is not set\n# CONFIG_ADV_SWBUTTON is not set\nCONFIG_AGP=y\n# CONFIG_AGP_AMD64 is not set\nCONFIG_AGP_INTEL=y\n# CONFIG_AGP_SIS is not set\n# CONFIG_AGP_VIA is not set\n# CONFIG_AMD_PMC is not set\n# CONFIG_AMD_PTDMA is not set\n# CONFIG_AMD_SFH_HID is not set\nCONFIG_ARCH_CPUIDLE_HALTPOLL=y\nCONFIG_ARCH_DMA_ADDR_T_64BIT=y\nCONFIG_ARCH_MIGHT_HAVE_ACPI_PDC=y\nCONFIG_ARCH_MMAP_RND_BITS=28\nCONFIG_ARCH_MMAP_RND_BITS_MAX=32\nCONFIG_ARCH_MMAP_RND_BITS_MIN=28\nCONFIG_ARCH_NR_GPIO=1024\nCONFIG_ARCH_SPARSEMEM_DEFAULT=y\nCONFIG_ARCH_WANTS_THP_SWAP=y\nCONFIG_AUDIT_ARCH=y\nCONFIG_BACKLIGHT_CLASS_DEVICE=y\nCONFIG_BALLOON_COMPACTION=y\nCONFIG_BLK_DEV_BSGLIB=y\nCONFIG_BLK_DEV_BSG_COMMON=y\nCONFIG_BLK_DEV_INTEGRITY=y\nCONFIG_BLK_DEV_INTEGRITY_T10=y\nCONFIG_BLK_DEV_NVME=y\nCONFIG_BLK_DEV_SR=y\nCONFIG_BLK_MQ_VIRTIO=y\nCONFIG_BLK_PM=y\n# CONFIG_BOOTPARAM_HOTPLUG_CPU0 is not set\nCONFIG_BTT=y\nCONFIG_CDROM=y\nCONFIG_CONNECTOR=y\nCONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y\nCONFIG_CPU_FREQ_GOV_SCHEDUTIL=y\n# CONFIG_CPU_IDLE_GOV_HALTPOLL is not set\nCONFIG_CPU_RMAP=y\nCONFIG_CRC_T10DIF=y\nCONFIG_CRYPTO_AES_NI_INTEL=y\n# CONFIG_CRYPTO_BLOWFISH_X86_64 is not set\n# CONFIG_CRYPTO_CAMELLIA_AESNI_AVX2_X86_64 is not set\n# CONFIG_CRYPTO_CAMELLIA_AESNI_AVX_X86_64 is not set\n# CONFIG_CRYPTO_CAMELLIA_X86_64 is not set\n# CONFIG_CRYPTO_CAST5_AVX_X86_64 is not set\n# CONFIG_CRYPTO_CAST6_AVX_X86_64 is not set\nCONFIG_CRYPTO_CRCT10DIF=y\n# CONFIG_CRYPTO_CRCT10DIF_PCLMUL is not set\nCONFIG_CRYPTO_CRYPTD=y\n# CONFIG_CRYPTO_DES3_EDE_X86_64 is not set\nCONFIG_CRYPTO_ECB=y\nCONFIG_CRYPTO_LIB_POLY1305_RSIZE=11\nCONFIG_CRYPTO_LRW=y\n# CONFIG_CRYPTO_NHPOLY1305_AVX2 is not set\n# CONFIG_CRYPTO_NHPOLY1305_SSE2 is not set\n# CONFIG_CRYPTO_SERPENT_AVX2_X86_64 is not set\n# CONFIG_CRYPTO_SERPENT_AVX_X86_64 is not set\n# CONFIG_CRYPTO_SERPENT_SSE2_X86_64 is not set\n# CONFIG_CRYPTO_SHA1_SSSE3 is not set\n# CONFIG_CRYPTO_SHA256_SSSE3 is not set\n# CONFIG_CRYPTO_SHA512_SSSE3 is not set\nCONFIG_CRYPTO_SIMD=y\n# CONFIG_CRYPTO_SM4_AESNI_AVX2_X86_64 is not set\n# CONFIG_CRYPTO_SM4_AESNI_AVX_X86_64 is not set\n# CONFIG_CRYPTO_TWOFISH_AVX_X86_64 is not set\n# CONFIG_CRYPTO_TWOFISH_X86_64 is not set\n# CONFIG_CRYPTO_TWOFISH_X86_64_3WAY is not set\nCONFIG_CRYPTO_XTS=y\n# CONFIG_DEBUG_HOTPLUG_CPU0 is not set\nCONFIG_DMA_ACPI=y\nCONFIG_DMA_OPS=y\nCONFIG_DMA_SHARED_BUFFER=y\nCONFIG_DRM=y\nCONFIG_DRM_BOCHS=y\nCONFIG_DRM_BRIDGE=y\nCONFIG_DRM_FBDEV_EMULATION=y\nCONFIG_DRM_FBDEV_OVERALLOC=100\nCONFIG_DRM_GEM_SHMEM_HELPER=y\n# CONFIG_DRM_HYPERV is not set\nCONFIG_DRM_I915=y\nCONFIG_DRM_I915_CAPTURE_ERROR=y\nCONFIG_DRM_I915_COMPRESS_ERROR=y\n# CONFIG_DRM_I915_DEBUG is not set\n# CONFIG_DRM_I915_DEBUG_GUC is not set\n# CONFIG_DRM_I915_DEBUG_MMIO is not set\n# CONFIG_DRM_I915_DEBUG_RUNTIME_PM is not set\n# CONFIG_DRM_I915_DEBUG_VBLANK_EVADE is not set\nCONFIG_DRM_I915_FENCE_TIMEOUT=10000\nCONFIG_DRM_I915_FORCE_PROBE=\"\"\nCONFIG_DRM_I915_GVT=y\nCONFIG_DRM_I915_HEARTBEAT_INTERVAL=2500\n# CONFIG_DRM_I915_LOW_LEVEL_TRACEPOINTS is not set\nCONFIG_DRM_I915_MAX_REQUEST_BUSYWAIT=8000\nCONFIG_DRM_I915_PREEMPT_TIMEOUT=640\nCONFIG_DRM_I915_REQUEST_TIMEOUT=20000\n# CONFIG_DRM_I915_SELFTEST is not set\nCONFIG_DRM_I915_STOP_TIMEOUT=100\n# CONFIG_DRM_I915_SW_FENCE_CHECK_DAG is not set\n# CONFIG_DRM_I915_SW_FENCE_DEBUG_OBJECTS is not set\nCONFIG_DRM_I915_TIMESLICE_DURATION=1\nCONFIG_DRM_I915_USERFAULT_AUTOSUSPEND=250\nCONFIG_DRM_I915_USERPTR=y\n# CONFIG_DRM_I915_WERROR is not set\nCONFIG_DRM_KMS_HELPER=y\nCONFIG_DRM_MIPI_DSI=y\nCONFIG_DRM_PANEL=y\nCONFIG_DRM_PANEL_BRIDGE=y\nCONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y\nCONFIG_DRM_TTM=y\nCONFIG_DRM_TTM_HELPER=y\nCONFIG_DRM_VIRTIO_GPU=y\nCONFIG_DRM_VRAM_HELPER=y\n# CONFIG_DRM_XEN_FRONTEND is not set\nCONFIG_EFI=y\nCONFIG_EFIVAR_FS=m\n# CONFIG_EFI_BOOTLOADER_CONTROL is not set\n# CONFIG_EFI_CAPSULE_LOADER is not set\n# CONFIG_EFI_CUSTOM_SSDT_OVERLAYS is not set\n# CONFIG_EFI_DISABLE_PCI_DMA is not set\nCONFIG_EFI_EARLYCON=y\nCONFIG_EFI_ESRT=y\n# CONFIG_EFI_FAKE_MEMMAP is not set\nCONFIG_EFI_GENERIC_STUB_INITRD_CMDLINE_LOADER=y\n# CONFIG_EFI_MIXED is not set\n# CONFIG_EFI_PGT_DUMP is not set\n# CONFIG_EFI_RCI2_TABLE is not set\nCONFIG_EFI_RUNTIME_MAP=y\nCONFIG_EFI_RUNTIME_WRAPPERS=y\nCONFIG_EFI_STUB=y\n# CONFIG_EFI_TEST is not set\n# CONFIG_EFI_VARS is not set\nCONFIG_FAILOVER=y\nCONFIG_FB=y\nCONFIG_FB_CFB_COPYAREA=y\nCONFIG_FB_CFB_FILLRECT=y\nCONFIG_FB_CFB_IMAGEBLIT=y\nCONFIG_FB_CMDLINE=y\nCONFIG_FB_DEFERRED_IO=y\nCONFIG_FB_EFI=y\nCONFIG_FB_HYPERV=y\nCONFIG_FB_MODE_HELPERS=y\nCONFIG_FB_SIMPLE=y\nCONFIG_FB_SYS_COPYAREA=y\nCONFIG_FB_SYS_FILLRECT=y\nCONFIG_FB_SYS_FOPS=y\nCONFIG_FB_SYS_IMAGEBLIT=y\nCONFIG_FB_TILEBLITTING=y\n# CONFIG_FB_VESA is not set\nCONFIG_FONT_8x16=y\nCONFIG_FONT_8x8=y\nCONFIG_FONT_SUPPORT=y\nCONFIG_FRAMEBUFFER_CONSOLE=y\nCONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y\n# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set\nCONFIG_FREEZER=y\nCONFIG_FUSION_SAS=y\nCONFIG_FW_CACHE=y\nCONFIG_GART_IOMMU=y\nCONFIG_GENERIC_BUG_RELATIVE_POINTERS=y\nCONFIG_GENERIC_CPU=y\nCONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y\nCONFIG_GENERIC_IRQ_MIGRATION=y\nCONFIG_GENERIC_PENDING_IRQ=y\nCONFIG_GPIOLIB=y\nCONFIG_GPIOLIB_IRQCHIP=y\nCONFIG_GPIO_ACPI=y\nCONFIG_GPIO_CDEV=y\nCONFIG_GPIO_ICH=y\nCONFIG_GPIO_SCH=y\nCONFIG_HALTPOLL_CPUIDLE=y\nCONFIG_HARDLOCKUP_CHECK_TIMESTAMP=y\nCONFIG_HDMI=y\nCONFIG_HIBERNATE_CALLBACKS=y\nCONFIG_HID_BATTERY_STRENGTH=y\nCONFIG_HID_GENERIC=y\nCONFIG_HID_HYPERV_MOUSE=y\nCONFIG_HOTPLUG_CPU=y\nCONFIG_HOTPLUG_PCI=y\nCONFIG_HOTPLUG_PCI_ACPI=y\n# CONFIG_HOTPLUG_PCI_ACPI_IBM is not set\n# CONFIG_HOTPLUG_PCI_CPCI is not set\n# CONFIG_HOTPLUG_PCI_PCIE is not set\n# CONFIG_HOTPLUG_PCI_SHPC is not set\nCONFIG_HOTPLUG_SMT=y\nCONFIG_HPET=y\nCONFIG_HPET_MMAP=y\n# CONFIG_HP_ACCEL is not set\nCONFIG_HVC_DRIVER=y\nCONFIG_HVC_IRQ=y\nCONFIG_HVC_XEN=y\nCONFIG_HVC_XEN_FRONTEND=y\nCONFIG_HWMON=y\nCONFIG_HWMON_VID=y\nCONFIG_HW_RANDOM_AMD=y\nCONFIG_HW_RANDOM_INTEL=y\nCONFIG_HW_RANDOM_VIRTIO=y\nCONFIG_HYPERV=y\nCONFIG_HYPERVISOR_GUEST=y\nCONFIG_HYPERV_BALLOON=y\nCONFIG_HYPERV_KEYBOARD=y\nCONFIG_HYPERV_NET=y\nCONFIG_HYPERV_STORAGE=y\n# CONFIG_HYPERV_TESTING is not set\nCONFIG_HYPERV_TIMER=y\nCONFIG_HYPERV_UTILS=y\n# CONFIG_HYPERV_VSOCKETS is not set\nCONFIG_I2C=y\nCONFIG_I2C_ALGOBIT=y\n# CONFIG_I2C_AMD_MP2 is not set\nCONFIG_I2C_BOARDINFO=y\n# CONFIG_I2C_HID_ACPI is not set\n# CONFIG_I2C_MULTI_INSTANTIATE is not set\n# CONFIG_I8K is not set\n# CONFIG_IA32_EMULATION is not set\nCONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000\n# CONFIG_IMA_SECURE_AND_OR_TRUSTED_BOOT is not set\nCONFIG_INPUT_XEN_KBDDEV_FRONTEND=y\nCONFIG_INTEL_GTT=y\nCONFIG_INTEL_IDLE=y\n# CONFIG_INTEL_IDXD_COMPAT is not set\n# CONFIG_INTEL_IPS is not set\n# CONFIG_INTEL_MEI_HDCP is not set\n# CONFIG_INTEL_MENLOW is not set\nCONFIG_INTEL_PCH_THERMAL=y\n# CONFIG_INTEL_SAR_INT1092 is not set\n# CONFIG_INTEL_SCU_PLATFORM is not set\nCONFIG_INTEL_SOC_DTS_IOSF_CORE=y\nCONFIG_INTEL_SOC_DTS_THERMAL=y\n# CONFIG_INTEL_SPEED_SELECT_INTERFACE is not set\n# CONFIG_INTEL_TURBO_MAX_3 is not set\n# CONFIG_INTEL_UNCORE_FREQ_CONTROL is not set\nCONFIG_INTERVAL_TREE=y\n# CONFIG_IOMMU_DEBUG is not set\nCONFIG_IOMMU_HELPER=y\nCONFIG_IOSF_MBI=y\n# CONFIG_IOSF_MBI_DEBUG is not set\n# CONFIG_ISCSI_IBFT is not set\nCONFIG_ISO9660_FS=y\nCONFIG_KALLSYMS_ABSOLUTE_PERCPU=y\nCONFIG_KCMP=y\nCONFIG_KVM_GUEST=y\nCONFIG_LEDS_GPIO=y\n# CONFIG_LEGACY_VSYSCALL_EMULATE is not set\nCONFIG_LEGACY_VSYSCALL_NONE=y\n# CONFIG_LEGACY_VSYSCALL_XONLY is not set\nCONFIG_LIBNVDIMM=y\nCONFIG_LOCK_SPIN_ON_OWNER=y\nCONFIG_LPC_ICH=y\nCONFIG_LPC_SCH=y\nCONFIG_MAILBOX=y\n# CONFIG_MAXSMP is not set\nCONFIG_MEMORY_BALLOON=y\nCONFIG_MEMREGION=y\n# CONFIG_MERAKI_MX100 is not set\nCONFIG_MFD_CORE=y\n# CONFIG_MFD_INTEL_LPSS_ACPI is not set\n# CONFIG_MFD_INTEL_PMC_BXT is not set\nCONFIG_MMC=y\nCONFIG_MMC_BLOCK=y\nCONFIG_MMC_CQHCI=y\nCONFIG_MMC_RICOH_MMC=y\nCONFIG_MMC_SDHCI=y\nCONFIG_MMC_SDHCI_ACPI=y\nCONFIG_MMC_SDHCI_IO_ACCESSORS=y\nCONFIG_MMC_SDHCI_PCI=y\n# CONFIG_MMC_SDHCI_PLTFM is not set\n# CONFIG_MMC_WBSD is not set\nCONFIG_MMU_NOTIFIER=y\nCONFIG_MODULES_USE_ELF_RELA=y\n# CONFIG_MPSC is not set\nCONFIG_MUTEX_SPIN_ON_OWNER=y\nCONFIG_ND_BLK=y\nCONFIG_ND_BTT=y\nCONFIG_ND_CLAIM=y\nCONFIG_NEED_DMA_MAP_STATE=y\nCONFIG_NET_FAILOVER=y\nCONFIG_NET_FLOW_LIMIT=y\n# CONFIG_NITRO_ENCLAVES is not set\nCONFIG_NR_CPUS=512\nCONFIG_NR_CPUS_DEFAULT=64\nCONFIG_NR_CPUS_RANGE_BEGIN=2\nCONFIG_NR_CPUS_RANGE_END=512\nCONFIG_NVME_CORE=y\n# CONFIG_NVME_HWMON is not set\nCONFIG_NVME_MULTIPATH=y\nCONFIG_OUTPUT_FORMAT=\"elf64-x86-64\"\nCONFIG_PADATA=y\nCONFIG_PAGE_POOL=y\nCONFIG_PAGE_REPORTING=y\nCONFIG_PAGE_TABLE_ISOLATION=y\nCONFIG_PARAVIRT=y\nCONFIG_PARAVIRT_CLOCK=y\n# CONFIG_PARAVIRT_DEBUG is not set\nCONFIG_PARAVIRT_SPINLOCKS=y\nCONFIG_PARAVIRT_XXL=y\nCONFIG_PATA_AMD=y\nCONFIG_PATA_ATIIXP=y\nCONFIG_PATA_MPIIX=y\nCONFIG_PATA_OLDPIIX=y\nCONFIG_PATA_PLATFORM=y\nCONFIG_PATA_TIMINGS=y\nCONFIG_PATA_VIA=y\nCONFIG_PCC=y\n# CONFIG_PCENGINES_APU2 is not set\nCONFIG_PCIEAER=y\nCONFIG_PCIEPORTBUS=y\nCONFIG_PCIE_PME=y\nCONFIG_PCI_HYPERV=y\nCONFIG_PCI_HYPERV_INTERFACE=y\n# CONFIG_PCI_MMCONFIG is not set\nCONFIG_PCI_XEN=y\nCONFIG_PGTABLE_LEVELS=4\nCONFIG_PHYSICAL_ALIGN=0x1000000\nCONFIG_PHYS_ADDR_T_64BIT=y\nCONFIG_PINCTRL=y\n# CONFIG_PINCTRL_ALDERLAKE is not set\n# CONFIG_PINCTRL_BAYTRAIL is not set\n# CONFIG_PINCTRL_BROXTON is not set\n# CONFIG_PINCTRL_CANNONLAKE is not set\n# CONFIG_PINCTRL_CHERRYVIEW is not set\n# CONFIG_PINCTRL_DENVERTON is not set\n# CONFIG_PINCTRL_ELKHARTLAKE is not set\n# CONFIG_PINCTRL_EMMITSBURG is not set\n# CONFIG_PINCTRL_GEMINILAKE is not set\n# CONFIG_PINCTRL_JASPERLAKE is not set\n# CONFIG_PINCTRL_LAKEFIELD is not set\n# CONFIG_PINCTRL_LEWISBURG is not set\n# CONFIG_PINCTRL_LYNXPOINT is not set\n# CONFIG_PINCTRL_SUNRISEPOINT is not set\n# CONFIG_PINCTRL_TIGERLAKE is not set\nCONFIG_PM=y\n# CONFIG_PMIC_OPREGION is not set\nCONFIG_PM_CLK=y\nCONFIG_PM_SLEEP=y\nCONFIG_PM_SLEEP_SMP=y\nCONFIG_PNP=y\nCONFIG_PNPACPI=y\nCONFIG_PNP_DEBUG_MESSAGES=y\nCONFIG_PROC_EVENTS=y\nCONFIG_PVH=y\nCONFIG_QUEUED_RWLOCKS=y\nCONFIG_QUEUED_SPINLOCKS=y\nCONFIG_RAS=y\nCONFIG_RELAY=y\nCONFIG_RELOCATABLE=y\nCONFIG_RESET_ATTACK_MITIGATION=y\nCONFIG_RFS_ACCEL=y\nCONFIG_RPS=y\nCONFIG_RTC_I2C_AND_SPI=y\nCONFIG_RWSEM_SPIN_ON_OWNER=y\n# CONFIG_SAMSUNG_Q10 is not set\nCONFIG_SATA_AHCI=y\n# CONFIG_SCHED_CORE is not set\nCONFIG_SCHED_MC=y\nCONFIG_SCHED_MC_PRIO=y\nCONFIG_SCHED_SMT=y\nCONFIG_SCSI_SAS_ATTRS=y\nCONFIG_SCSI_VIRTIO=y\nCONFIG_SENSORS_CORETEMP=y\nCONFIG_SENSORS_FAM15H_POWER=y\nCONFIG_SENSORS_I5500=y\nCONFIG_SENSORS_K10TEMP=y\nCONFIG_SENSORS_K8TEMP=y\nCONFIG_SENSORS_VIA_CPUTEMP=y\nCONFIG_SERIAL_8250_PNP=y\nCONFIG_SERIAL_MCTRL_GPIO=y\nCONFIG_SMP=y\nCONFIG_SOCK_RX_QUEUE_MAPPING=y\nCONFIG_SPARSEMEM=y\nCONFIG_SPARSEMEM_EXTREME=y\nCONFIG_SPARSEMEM_MANUAL=y\n# CONFIG_SPARSEMEM_VMEMMAP is not set\nCONFIG_SPARSEMEM_VMEMMAP_ENABLE=y\nCONFIG_STACK_VALIDATION=y\n# CONFIG_SURFACE_PLATFORMS is not set\nCONFIG_SWIOTLB=y\nCONFIG_SWIOTLB_XEN=y\nCONFIG_SYNC_FILE=y\n# CONFIG_SYSTEM76_ACPI is not set\nCONFIG_SYS_HYPERVISOR=y\nCONFIG_THERMAL_GOV_USER_SPACE=y\nCONFIG_THERMAL_HWMON=y\nCONFIG_THERMAL_WRITABLE_TRIPS=y\n# CONFIG_TOSHIBA_BT_RFKILL is not set\nCONFIG_TREE_RCU=y\nCONFIG_TREE_SRCU=y\n# CONFIG_UCLAMP_TASK is not set\nCONFIG_UCS2_STRING=y\n# CONFIG_UNWINDER_ORC is not set\nCONFIG_USB_STORAGE=y\nCONFIG_VIRTIO=y\nCONFIG_VIRTIO_BALLOON=y\nCONFIG_VIRTIO_BLK=y\nCONFIG_VIRTIO_CONSOLE=y\nCONFIG_VIRTIO_DMA_SHARED_BUFFER=y\nCONFIG_VIRTIO_MMIO=y\nCONFIG_VIRTIO_MMIO_CMDLINE_DEVICES=y\nCONFIG_VIRTIO_NET=y\nCONFIG_VIRTIO_PCI=y\nCONFIG_VIRTIO_PCI_LEGACY=y\nCONFIG_VIRTIO_PCI_LIB=y\n# CONFIG_VIRTIO_PMEM is not set\n# CONFIG_VIRTIO_VSOCKETS is not set\nCONFIG_VIRTIO_VSOCKETS_COMMON=y\nCONFIG_VIRT_DRIVERS=y\nCONFIG_VMAP_PFN=y\nCONFIG_VMAP_STACK=y\n# CONFIG_VMD is not set\nCONFIG_VMWARE_BALLOON=y\nCONFIG_VMWARE_PVSCSI=y\nCONFIG_VMWARE_VMCI=y\nCONFIG_VMWARE_VMCI_VSOCKETS=y\nCONFIG_VMXNET3=y\nCONFIG_VSOCKETS=y\nCONFIG_VSOCKETS_LOOPBACK=y\nCONFIG_VT_CONSOLE_SLEEP=y\nCONFIG_WATCHDOG_CORE=y\n# CONFIG_WIRELESS_HOTKEY is not set\n# CONFIG_X86_5LEVEL is not set\nCONFIG_X86_64=y\nCONFIG_X86_64_SMP=y\nCONFIG_X86_ACPI_CPUFREQ=y\n# CONFIG_X86_ACPI_CPUFREQ_CPB is not set\nCONFIG_X86_AMD_FREQ_SENSITIVITY=y\n# CONFIG_X86_AMD_PLATFORM_DEVICE is not set\nCONFIG_X86_CPUID=y\nCONFIG_X86_DIRECT_GBPAGES=y\nCONFIG_X86_HV_CALLBACK_VECTOR=y\nCONFIG_X86_INTEL_LPSS=y\n# CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS is not set\nCONFIG_X86_INTEL_PSTATE=y\nCONFIG_X86_MINIMUM_CPU_FAMILY=64\n# CONFIG_X86_PCC_CPUFREQ is not set\nCONFIG_X86_PKG_TEMP_THERMAL=y\n# CONFIG_X86_PMEM_LEGACY is not set\nCONFIG_X86_PM_TIMER=y\n# CONFIG_X86_POWERNOW_K8 is not set\n# CONFIG_X86_VSYSCALL_EMULATION is not set\nCONFIG_X86_X2APIC=y\n# CONFIG_X86_X32 is not set\nCONFIG_XEN=y\nCONFIG_XENFS=y\nCONFIG_XEN_512GB=y\nCONFIG_XEN_ACPI=y\nCONFIG_XEN_ACPI_PROCESSOR=y\nCONFIG_XEN_AUTO_XLATE=y\n# CONFIG_XEN_BACKEND is not set\nCONFIG_XEN_BALLOON=y\nCONFIG_XEN_BLKDEV_FRONTEND=y\nCONFIG_XEN_COMPAT_XENFS=y\nCONFIG_XEN_DEBUG_FS=y\nCONFIG_XEN_DEV_EVTCHN=y\nCONFIG_XEN_DOM0=y\nCONFIG_XEN_EFI=y\nCONFIG_XEN_FBDEV_FRONTEND=y\nCONFIG_XEN_GNTDEV=y\nCONFIG_XEN_GRANT_DEV_ALLOC=y\nCONFIG_XEN_HAVE_PVMMU=y\nCONFIG_XEN_HAVE_VPMU=y\n# CONFIG_XEN_MCE_LOG is not set\nCONFIG_XEN_NETDEV_FRONTEND=y\nCONFIG_XEN_PCIDEV_FRONTEND=y\nCONFIG_XEN_PRIVCMD=y\nCONFIG_XEN_PV=y\nCONFIG_XEN_PVH=y\nCONFIG_XEN_PVHVM=y\nCONFIG_XEN_PVHVM_GUEST=y\nCONFIG_XEN_PVHVM_SMP=y\nCONFIG_XEN_PV_DOM0=y\nCONFIG_XEN_PV_SMP=y\nCONFIG_XEN_SAVE_RESTORE=y\nCONFIG_XEN_SCSI_FRONTEND=y\nCONFIG_XEN_SYMS=y\nCONFIG_XEN_SYS_HYPERVISOR=y\nCONFIG_XEN_WDT=y\nCONFIG_XEN_XENBUS_FRONTEND=y\nCONFIG_XPS=y\nCONFIG_ZLIB_DEFLATE=y\nCONFIG_ZONE_DMA32=y\n"
  },
  {
    "path": "target/linux/x86/64/target.mk",
    "content": "ARCH:=x86_64\nBOARDNAME:=x86_64\n\ndefine Target/Description\n        Build images for 64 bit systems including virtualized guests.\nendef\n"
  },
  {
    "path": "target/linux/x86/Makefile",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2006-2011 OpenWrt.org\n\ninclude $(TOPDIR)/rules.mk\n\nARCH:=i386\nBOARD:=x86\nBOARDNAME:=x86\nFEATURES:=squashfs ext4 vdi vmdk vhdx pcmcia targz fpu boot-part rootfs-part\nSUBTARGETS:=generic legacy geode 64\n\nKERNEL_PATCHVER:=5.10\nKERNEL_TESTING_PATCHVER:=5.15\n\nKERNELNAME:=bzImage\n\ninclude $(INCLUDE_DIR)/target.mk\n\nDEFAULT_PACKAGES += partx-utils mkf2fs e2fsprogs kmod-button-hotplug\n\n$(eval $(call BuildTarget))\n\n$(eval $(call $(if $(CONFIG_ISO_IMAGES),SetupHostCommand,Ignore),mkisofs, \\\n\tPlease install mkisofs. , \\\n\tmkisofs -v 2>&1 , \\\n\tgenisoimage -v 2>&1 | grep genisoimage, \\\n\txorrisofs -v 2>&1 | grep xorriso \\\n))\n"
  },
  {
    "path": "target/linux/x86/base-files/etc/board.d/01_leds",
    "content": "#\n# Copyright © 2017 OpenWrt.org\n#\n\n. /lib/functions/uci-defaults.sh\n\nboard_config_update\n\ncase \"$(board_name)\" in\ncisco-mx100-hw)\n\tucidef_set_led_usbport \"usb\" \"USB\" \"mx100:green:usb\" \"1-1-port2\"\n\tucidef_set_led_default \"diag\" \"DIAG\" \"mx100:green:tricolor\" \"1\"\n\t;;\npc-engines-apu1|pc-engines-apu2|pc-engines-apu3)\n\tucidef_set_led_netdev \"wan\" \"WAN\" \"apu:green:3\" \"eth0\"\n\tucidef_set_led_netdev \"lan\" \"LAN\" \"apu:green:2\" \"br-lan\"\n\tucidef_set_led_default \"diag\" \"DIAG\" \"apu:green:1\" \"1\"\n\t;;\ntraverse-technologies-geos)\n\tucidef_set_led_netdev \"lan\" \"LAN\" \"geos:1\" \"br-lan\" \"tx rx\"\n\tucidef_set_led_netdev \"wlan\" \"WiFi\" \"geos:2\" \"phy0tpt\"\n\tucidef_set_led_default \"diag\" \"DIAG\" \"geos:3\" \"1\"\n\t;;\nesac\nboard_config_flush\n\nexit 0\n"
  },
  {
    "path": "target/linux/x86/base-files/etc/board.d/02_network",
    "content": "#\n# Copyright © 2017 OpenWrt.org\n#\n\n. /lib/functions/system.sh\n. /lib/functions/uci-defaults.sh\n\nboard_config_update\n\ncase \"$(board_name)\" in\ncisco-mx100-hw)\n\tucidef_set_interfaces_lan_wan \"eth0 eth1 eth2 eth3 eth4 eth5 eth7 eth8 eth9 eth10 eth11\" \"eth6\"\n\t;;\npc-engines-apu1|pc-engines-apu2|pc-engines-apu3)\n\tucidef_set_interfaces_lan_wan \"eth1 eth2\" \"eth0\"\n\t;;\nroqos-roqos-core-rc10)\n\tucidef_set_interfaces_lan_wan \"eth1\" \"eth0\"\n\t;;\nsophos-sg-105r1|sophos-xg-105r1| \\\nsophos-sg-105wr1|sophos-xg-105wr1| \\\nsophos-sg-105r2|sophos-xg-105r2| \\\nsophos-sg-105wr2|sophos-xg-105wr2| \\\nsophos-sg-115r1|sophos-xg-115r1| \\\nsophos-sg-115wr1|sophos-xg-115wr1| \\\nsophos-sg-115r2|sophos-xg-115r2| \\\nsophos-sg-115wr2|sophos-xg-115wr2| \\\nsophos-xg-85*|sophos-xg-86*)\n\tucidef_set_interfaces_lan_wan \"eth0 eth2 eth3\" \"eth1\"\n\t;;\nsophos-sg-125r1|sophos-xg-125r1| \\\nsophos-sg-125wr1|sophos-xg-125wr1| \\\nsophos-sg-125r2|sophos-xg-125r2| \\\nsophos-sg-125wr2|sophos-xg-125wr2| \\\nsophos-sg-135r1|sophos-xg-135r1| \\\nsophos-sg-135wr1|sophos-xg-135wr1| \\\nsophos-sg-135r2|sophos-xg-135r2| \\\nsophos-sg-135wr2|sophos-xg-135wr2)\n\tucidef_set_interfaces_lan_wan \"eth0 eth2 eth3 eth4 eth5 eth6 eth7\" \"eth1\"\n\t;;\ntraverse-technologies-geos)\n\tucidef_set_interface_lan \"eth0 eth1\"\n\tucidef_add_atm_bridge \"0\" \"35\" \"llc\" \"bridged\"\n\tucidef_set_interface_wan \"nas0\" \"dhcp\"\n\tmacaddr=\"$(cat /sys/class/net/eth0/address)\" 2>/dev/null\n\t[ -n \"$macaddr\" ] && ucidef_set_interface_macaddr \"wan\" \"$macaddr\"\n\t;;\nesac\nboard_config_flush\n\nexit 0\n"
  },
  {
    "path": "target/linux/x86/base-files/etc/diag.sh",
    "content": "#!/bin/sh\n#\n# Copyright © 2017 OpenWrt.org\n#\n\n. /lib/functions.sh\n. /lib/functions/leds.sh\n. /usr/share/libubox/jshn.sh\n\npreinit_match_diag_led() {\n\tlocal CFG keys key cfg name sysfs default\n\n\tCFG=/etc/board.json\n\tif [ ! -s $CFG ]; then\n\t\tCFG=/tmp/board.json\n\t\t[ -s /tmp/sysinfo/model ] || return\n\t\t/bin/board_detect $CFG || return\n\tfi\n\n\tjson_init\n\tjson_load \"$(cat $CFG)\"\n\tjson_get_keys keys led\n\tjson_is_a led object || return\n\n\tjson_select led\n\tfor key in $keys; do\n\t\tjson_select \"$key\"\n\t\tjson_get_vars name sysfs default\n\n\t\tif [ \"$name\" = \"DIAG\" -a \"$default\" = \"1\" ]; then\n\t\t\tstatus_led=\"$sysfs\"\n\t\t\treturn\n\t\tfi\n\t\tjson_select ..\n\tdone\n}\n\nmatch_diag_led() {\n\tlocal name\n\tlocal default\n\tlocal sysfs\n\tconfig_get name \"$1\" name\n\tconfig_get default \"$1\" default\n\tconfig_get sysfs \"$1\" sysfs\n\n\tif [ \"$name\" = \"DIAG\" -a \"$default\" = \"1\" ]; then\n\t\tstatus_led=\"$sysfs\"\n\tfi\n}\n\nget_status_led() {\n\tif [ -s /etc/config/system ]; then\n\t\tconfig_load system\n\t\tconfig_foreach match_diag_led led\n\telse\n\t\tpreinit_match_diag_led\n\tfi\n}\n\nset_state() {\n\tget_status_led\n\n\tcase \"$1\" in\n\tpreinit)\n\t\tstatus_led_blink_preinit\n\t\t;;\n\n\tfailsafe)\n\t\tstatus_led_blink_failsafe\n\t\t;;\n\n\tpreinit_regular)\n\t\tstatus_led_blink_preinit_regular\n\t\t;;\n\n\tupgrade)\n\t\tstatus_led_blink_preinit_regular\n\t\t;;\n\n\tdone)\n\t\tstatus_led_on\n\t\t;;\n\tesac\n}\n"
  },
  {
    "path": "target/linux/x86/base-files/etc/inittab",
    "content": "::sysinit:/etc/init.d/rcS S boot\n::shutdown:/etc/init.d/rcS K shutdown\nttyS0::askfirst:/usr/libexec/login.sh\nhvc0::askfirst:/usr/libexec/login.sh\ntty1::askfirst:/usr/libexec/login.sh\n"
  },
  {
    "path": "target/linux/x86/base-files/lib/preinit/01_sysinfo",
    "content": "sanitize_name_x86() {\n\tsed -e '\n\t\ty/ABCDEFGHIJKLMNOPQRSTUVWXYZ/abcdefghijklmnopqrstuvwxyz/;\n\t\ts/[^a-z0-9_-]\\+/-/g;\n\t\ts/^-//;\n\t\ts/-$//;\n\t' \"$@\"\n}\n\ndo_sysinfo_x86() {\n\tlocal vendor product file\n\n\tfor file in sys_vendor board_vendor; do\n\t\tvendor=\"$(cat /sys/devices/virtual/dmi/id/$file 2>/dev/null)\"\n\t\tcase \"$vendor\" in\n\t\tempty | \\\n\t\tSystem\\ manufacturer | \\\n\t\tTo\\ [bB]e\\ [fF]illed\\ [bB]y\\ O\\.E\\.M\\.)\n\t\t\tcontinue\n\t\t\t;;\n\t\tesac\n\t\t[ -n \"$vendor\" ] && break\n\tdone\n\n\tfor file in product_name board_name; do\n\t\tproduct=\"$(cat /sys/devices/virtual/dmi/id/$file 2>/dev/null)\"\n\t\tcase \"$vendor:$product\" in\n\t\t?*:empty | \\\n\t\t?*:System\\ Product\\ Name | \\\n\t\t?*:To\\ [bB]e\\ [fF]illed\\ [bB]y\\ O\\.E\\.M\\.)\n\t\t\tcontinue\n\t\t\t;;\n\t\t\"PC Engines:APU\")\n\t\t\tproduct=\"apu1\"\n\t\t\tbreak\n\t\t\t;;\n\t\t\"Sophos:SG\"|\"Sophos:XG\")\n\t\t\tlocal product_version\n\t\t\tproduct_version=\"$(cat /sys/devices/virtual/dmi/id/product_version 2>/dev/null)\"\n\t\t\tcase \"$product_version\" in\n\t\t\t105*|115*|125*|135*|85*|86*)\n\t\t\t\tproduct=\"${product}-${product_version}\"\n\t\t\t\tbreak\n\t\t\t\t;;\n\t\t\tesac\n\t\t\t;;\n\t\t\"Supermicro:Super Server\")\n\t\t\tcontinue\n\t\t\t;;\n\t\t?*:?*)\n\t\t\tbreak\n\t\t\t;;\n\t\tesac\n\tdone\n\n\t[ -n \"$vendor\" -a -n \"$product\" ] || return\n\n\tmkdir -p /tmp/sysinfo\n\n\techo \"$vendor $product\" > /tmp/sysinfo/model\n\n\tsanitize_name_x86 /tmp/sysinfo/model > /tmp/sysinfo/board_name\n}\n\nboot_hook_add preinit_main do_sysinfo_x86\n"
  },
  {
    "path": "target/linux/x86/base-files/lib/preinit/02_load_x86_ucode",
    "content": "# Copyright (C) 2018 OpenWrt.org\n\ndo_load_x86_ucode() {\n\tif [ -e \"/sys/devices/system/cpu/microcode/reload\" ]; then\n\t\techo 1 > /sys/devices/system/cpu/microcode/reload\n\tfi\n}\n\nboot_hook_add preinit_main do_load_x86_ucode\n"
  },
  {
    "path": "target/linux/x86/base-files/lib/preinit/15_essential_fs_x86",
    "content": "# Copyright (C) 2006-2010 OpenWrt.org\n# Copyright (C) 2010 Vertical Communications\n\ndo_mount_procfs() {\n\tmount -o noatime -t proc none /proc\n}\n\n"
  },
  {
    "path": "target/linux/x86/base-files/lib/preinit/20_check_iso",
    "content": "check_for_iso() {\n\tgrep -qE '/dev/root.*iso9660' /proc/mounts && ramoverlay\n}\n\nboot_hook_add preinit_mount_root check_for_iso\n"
  },
  {
    "path": "target/linux/x86/base-files/lib/preinit/79_move_config",
    "content": "# Copyright (C) 2012-2015 OpenWrt.org\n\nmove_config() {\n\tlocal partdev parttype=ext4\n\n\t. /lib/upgrade/common.sh\n\n\tif export_bootdevice && export_partdevice partdev 1; then\n\t\tmkdir -p /boot\n\t\tpart_magic_fat \"/dev/$partdev\" && parttype=vfat\n\t\tmount -t $parttype -o rw,noatime \"/dev/$partdev\" /boot\n\t\tif [ -f \"/boot/$BACKUP_FILE\" ]; then\n\t\t\tmv -f \"/boot/$BACKUP_FILE\" /\n\t\tfi\n\t\tmount --bind /boot/boot /boot\n\tfi\n}\n\nboot_hook_add preinit_mount_root move_config\n"
  },
  {
    "path": "target/linux/x86/base-files/lib/preinit/81_upgrade_bootloader",
    "content": "upgrade_bootloader() {\n\tlocal diskdev\n\n\t. /lib/upgrade/common.sh\n\n\tif [ ! -f /boot/grub/upgraded ] && export_bootdevice && export_partdevice diskdev 0; then\n\t\tpart_magic_efi \"/dev/$diskdev\" && return 0\n\t\techo \"(hd0) /dev/$diskdev\" > /tmp/device.map\n\t\t/usr/sbin/grub-bios-setup \\\n\t\t\t-m \"/tmp/device.map\" \\\n\t\t\t-d \"/boot/grub\" \\\n\t\t\t-r \"hd0,msdos1\" \\\n\t\t\t\"/dev/$diskdev\" \\\n\t\t&& touch /boot/grub/upgraded\n\tfi\n}\n\n[ \"$INITRAMFS\" = \"1\" ] || boot_hook_add preinit_main upgrade_bootloader\n"
  },
  {
    "path": "target/linux/x86/base-files/lib/upgrade/platform.sh",
    "content": "RAMFS_COPY_BIN='grub-bios-setup'\n\nplatform_check_image() {\n\tlocal diskdev partdev diff\n\t[ \"$#\" -gt 1 ] && return 1\n\n\tcase \"$(get_magic_word \"$1\")\" in\n\t\teb48|eb63) ;;\n\t\t*)\n\t\t\tv \"Invalid image type\"\n\t\t\treturn 1\n\t\t;;\n\tesac\n\n\texport_bootdevice && export_partdevice diskdev 0 || {\n\t\tv \"Unable to determine upgrade device\"\n\t\treturn 1\n\t}\n\n\tget_partitions \"/dev/$diskdev\" bootdisk\n\n\tv \"Extract boot sector from the image\"\n\tget_image_dd \"$1\" of=/tmp/image.bs count=63 bs=512b\n\n\tget_partitions /tmp/image.bs image\n\n\t#compare tables\n\tdiff=\"$(grep -F -x -v -f /tmp/partmap.bootdisk /tmp/partmap.image)\"\n\n\trm -f /tmp/image.bs /tmp/partmap.bootdisk /tmp/partmap.image\n\n\tif [ -n \"$diff\" ]; then\n\t\tv \"Partition layout has changed. Full image will be written.\"\n\t\task_bool 0 \"Abort\" && exit 1\n\t\treturn 0\n\tfi\n}\n\nplatform_copy_config() {\n\tlocal partdev parttype=ext4\n\n\tif export_partdevice partdev 1; then\n\t\tpart_magic_fat \"/dev/$partdev\" && parttype=vfat\n\t\tmount -t $parttype -o rw,noatime \"/dev/$partdev\" /mnt\n\t\tcp -af \"$UPGRADE_BACKUP\" \"/mnt/$BACKUP_FILE\"\n\t\tumount /mnt\n\tfi\n}\n\nplatform_do_bootloader_upgrade() {\n\tlocal bootpart parttable=msdos\n\tlocal diskdev=\"$1\"\n\n\tif export_partdevice bootpart 1; then\n\t\tmkdir -p /tmp/boot\n\t\tmount -o rw,noatime \"/dev/$bootpart\" /tmp/boot\n\t\techo \"(hd0) /dev/$diskdev\" > /tmp/device.map\n\t\tpart_magic_efi \"/dev/$diskdev\" && parttable=gpt\n\n\t\tv \"Upgrading bootloader on /dev/$diskdev...\"\n\t\tgrub-bios-setup \\\n\t\t\t-m \"/tmp/device.map\" \\\n\t\t\t-d \"/tmp/boot/boot/grub\" \\\n\t\t\t-r \"hd0,${parttable}1\" \\\n\t\t\t\"/dev/$diskdev\" \\\n\t\t&& touch /tmp/boot/boot/grub/upgraded\n\n\t\tumount /tmp/boot\n\tfi\n}\n\nplatform_do_upgrade() {\n\tlocal diskdev partdev diff\n\n\texport_bootdevice && export_partdevice diskdev 0 || {\n\t\tv \"Unable to determine upgrade device\"\n\t\treturn 1\n\t}\n\n\tsync\n\n\tif [ \"$UPGRADE_OPT_SAVE_PARTITIONS\" = \"1\" ]; then\n\t\tget_partitions \"/dev/$diskdev\" bootdisk\n\n\t\tv \"Extract boot sector from the image\"\n\t\tget_image_dd \"$1\" of=/tmp/image.bs count=63 bs=512b\n\n\t\tget_partitions /tmp/image.bs image\n\n\t\t#compare tables\n\t\tdiff=\"$(grep -F -x -v -f /tmp/partmap.bootdisk /tmp/partmap.image)\"\n\telse\n\t\tdiff=1\n\tfi\n\n\tif [ -n \"$diff\" ]; then\n\t\tget_image_dd \"$1\" of=\"/dev/$diskdev\" bs=4096 conv=fsync\n\n\t\t# Separate removal and addtion is necessary; otherwise, partition 1\n\t\t# will be missing if it overlaps with the old partition 2\n\t\tpartx -d - \"/dev/$diskdev\"\n\t\tpartx -a - \"/dev/$diskdev\"\n\n\t\treturn 0\n\tfi\n\n\t#iterate over each partition from the image and write it to the boot disk\n\twhile read part start size; do\n\t\tif export_partdevice partdev $part; then\n\t\t\tv \"Writing image to /dev/$partdev...\"\n\t\t\tget_image_dd \"$1\" of=\"/dev/$partdev\" ibs=512 obs=1M skip=\"$start\" count=\"$size\" conv=fsync\n\t\telse\n\t\t\tv \"Unable to find partition $part device, skipped.\"\n\t\tfi\n\tdone < /tmp/partmap.image\n\n\tv \"Writing new UUID to /dev/$diskdev...\"\n\tget_image_dd \"$1\" of=\"/dev/$diskdev\" bs=1 skip=440 count=4 seek=440 conv=fsync\n\n\tplatform_do_bootloader_upgrade \"$diskdev\"\n\tlocal parttype=ext4\n\tpart_magic_efi \"/dev/$diskdev\" || return 0\n\n\tif export_partdevice partdev 1; then\n\t\tpart_magic_fat \"/dev/$partdev\" && parttype=vfat\n\t\tmount -t $parttype -o rw,noatime \"/dev/$partdev\" /mnt\n\t\tset -- $(dd if=\"/dev/$diskdev\" bs=1 skip=1168 count=16 2>/dev/null | hexdump -v -e '8/1 \"%02x \"\" \"2/1 \"%02x\"\"-\"6/1 \"%02x\"')\n\t\tsed -i \"s/\\(PARTUUID=\\)[a-f0-9-]\\+/\\1$4$3$2$1-$6$5-$8$7-$9/ig\" /mnt/boot/grub/grub.cfg\n\t\tumount /mnt\n\tfi\n}\n"
  },
  {
    "path": "target/linux/x86/config-5.10",
    "content": "# CONFIG_60XX_WDT is not set\n# CONFIG_64BIT is not set\n# CONFIG_ACPI is not set\n# CONFIG_ACQUIRE_WDT is not set\n# CONFIG_ADVANTECH_WDT is not set\n# CONFIG_ALIM1535_WDT is not set\n# CONFIG_ALIX is not set\nCONFIG_AMD_NB=y\nCONFIG_ARCH_32BIT_OFF_T=y\nCONFIG_ARCH_CLOCKSOURCE_INIT=y\nCONFIG_ARCH_HIBERNATION_POSSIBLE=y\nCONFIG_ARCH_MAY_HAVE_PC_FDC=y\nCONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y\nCONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y\nCONFIG_ARCH_RANDOM=y\nCONFIG_ARCH_SELECT_MEMORY_MODEL=y\nCONFIG_ARCH_SPARSEMEM_ENABLE=y\nCONFIG_ARCH_SPLIT_ARG64=y\nCONFIG_ARCH_STACKWALK=y\nCONFIG_ARCH_SUSPEND_POSSIBLE=y\nCONFIG_ARCH_USES_PG_UNCACHED=y\nCONFIG_ARCH_WANTS_DYNAMIC_TASK_STRUCT=y\nCONFIG_ATA=y\nCONFIG_ATA_GENERIC=y\nCONFIG_ATA_PIIX=y\nCONFIG_BLK_DEV_LOOP=y\nCONFIG_BLK_DEV_SD=y\nCONFIG_BLK_MQ_PCI=y\nCONFIG_BLK_SCSI_REQUEST=y\nCONFIG_BOUNCE=y\nCONFIG_CLKBLD_I8253=y\nCONFIG_CLKDEV_LOOKUP=y\nCONFIG_CLKEVT_I8253=y\nCONFIG_CLKSRC_I8253=y\nCONFIG_CLOCKSOURCE_VALIDATE_LAST_CYCLE=y\nCONFIG_CLOCKSOURCE_WATCHDOG=y\nCONFIG_CLONE_BACKWARDS=y\nCONFIG_COMMON_CLK=y\nCONFIG_COMPAT_32=y\nCONFIG_COMPAT_32BIT_TIME=y\n# CONFIG_COMPAT_VDSO is not set\nCONFIG_CONSOLE_TRANSLATIONS=y\n# CONFIG_CPU5_WDT is not set\nCONFIG_CPU_FREQ=y\nCONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y\n# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set\nCONFIG_CPU_FREQ_GOV_ATTR_SET=y\nCONFIG_CPU_FREQ_GOV_COMMON=y\n# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set\nCONFIG_CPU_FREQ_GOV_ONDEMAND=y\nCONFIG_CPU_FREQ_GOV_PERFORMANCE=y\n# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set\n# CONFIG_CPU_FREQ_GOV_USERSPACE is not set\nCONFIG_CPU_FREQ_STAT=y\nCONFIG_CPU_IDLE=y\nCONFIG_CPU_IDLE_GOV_LADDER=y\nCONFIG_CPU_SUP_AMD=y\nCONFIG_CPU_SUP_CENTAUR=y\nCONFIG_CPU_SUP_CYRIX_32=y\nCONFIG_CPU_SUP_HYGON=y\nCONFIG_CPU_SUP_INTEL=y\nCONFIG_CPU_SUP_TRANSMETA_32=y\nCONFIG_CPU_SUP_UMC_32=y\nCONFIG_CPU_SUP_ZHAOXIN=y\nCONFIG_CRASH_CORE=y\nCONFIG_CRC16=y\nCONFIG_CRYPTO_CRC32=y\nCONFIG_CRYPTO_CRC32C=y\n# CONFIG_CRYPTO_CRC32_PCLMUL is not set\nCONFIG_CRYPTO_LIB_POLY1305_RSIZE=1\nCONFIG_CRYPTO_RNG2=y\n# CONFIG_CRYPTO_SERPENT_SSE2_586 is not set\n# CONFIG_CX_ECAT is not set\nCONFIG_DCACHE_WORD_ACCESS=y\n# CONFIG_DCDBAS is not set\n# CONFIG_DEBUG_BOOT_PARAMS is not set\n# CONFIG_DEBUG_ENTRY is not set\nCONFIG_DEBUG_MEMORY_INIT=y\nCONFIG_DEBUG_MISC=y\n# CONFIG_DEBUG_NMI_SELFTEST is not set\n# CONFIG_DEBUG_TLBFLUSH is not set\nCONFIG_DECOMPRESS_BZIP2=y\nCONFIG_DECOMPRESS_GZIP=y\n# CONFIG_DELL_RBU is not set\nCONFIG_DMADEVICES=y\nCONFIG_DMI=y\nCONFIG_DMIID=y\nCONFIG_DMI_SCAN_MACHINE_NON_EFI_FALLBACK=y\nCONFIG_DMI_SYSFS=y\nCONFIG_DNOTIFY=y\nCONFIG_DUMMY_CONSOLE=y\nCONFIG_EARLY_PRINTK=y\n# CONFIG_EARLY_PRINTK_DBGP is not set\nCONFIG_EDAC_ATOMIC_SCRUB=y\nCONFIG_EDAC_SUPPORT=y\n# CONFIG_EDD is not set\n# CONFIG_EISA is not set\n# CONFIG_EUROTECH_WDT is not set\nCONFIG_EXT4_FS=y\nCONFIG_F2FS_FS=y\n# CONFIG_F71808E_WDT is not set\nCONFIG_FIRMWARE_MEMMAP=y\nCONFIG_FIX_EARLYCON_MEM=y\nCONFIG_FRAME_POINTER=y\nCONFIG_FS_IOMAP=y\nCONFIG_FS_MBCACHE=y\nCONFIG_FUSION=y\n# CONFIG_FUSION_CTL is not set\n# CONFIG_FUSION_LOGGING is not set\nCONFIG_FUSION_MAX_SGE=128\nCONFIG_FUSION_SPI=y\nCONFIG_FW_LOADER_PAGED_BUF=y\nCONFIG_GENERIC_ALLOCATOR=y\nCONFIG_GENERIC_BUG=y\nCONFIG_GENERIC_CLOCKEVENTS=y\nCONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y\nCONFIG_GENERIC_CLOCKEVENTS_MIN_ADJUST=y\nCONFIG_GENERIC_CMOS_UPDATE=y\nCONFIG_GENERIC_CPU_AUTOPROBE=y\nCONFIG_GENERIC_CPU_VULNERABILITIES=y\nCONFIG_GENERIC_EARLY_IOREMAP=y\nCONFIG_GENERIC_ENTRY=y\nCONFIG_GENERIC_FIND_FIRST_BIT=y\nCONFIG_GENERIC_GETTIMEOFDAY=y\nCONFIG_GENERIC_IOMAP=y\nCONFIG_GENERIC_IRQ_MATRIX_ALLOCATOR=y\nCONFIG_GENERIC_IRQ_RESERVATION_MODE=y\nCONFIG_GENERIC_IRQ_SHOW=y\nCONFIG_GENERIC_ISA_DMA=y\nCONFIG_GENERIC_MSI_IRQ=y\nCONFIG_GENERIC_MSI_IRQ_DOMAIN=y\nCONFIG_GENERIC_PCI_IOMAP=y\nCONFIG_GENERIC_SMP_IDLE_THREAD=y\nCONFIG_GENERIC_STRNCPY_FROM_USER=y\nCONFIG_GENERIC_STRNLEN_USER=y\nCONFIG_GENERIC_TIME_VSYSCALL=y\nCONFIG_GENERIC_VDSO_32=y\n# CONFIG_GEOS is not set\nCONFIG_GLOB=y\n# CONFIG_HANGCHECK_TIMER is not set\nCONFIG_HARDIRQS_SW_RESEND=y\nCONFIG_HAS_DMA=y\nCONFIG_HAS_IOMEM=y\nCONFIG_HAS_IOPORT_MAP=y\nCONFIG_HID=y\nCONFIG_HIGHMEM=y\nCONFIG_HIGHMEM4G=y\n# CONFIG_HIGHMEM64G is not set\nCONFIG_HIGHPTE=y\nCONFIG_HPET_EMULATE_RTC=y\nCONFIG_HPET_TIMER=y\n# CONFIG_HP_WATCHDOG is not set\nCONFIG_HW_CONSOLE=y\nCONFIG_HW_RANDOM=y\nCONFIG_HW_RANDOM_GEODE=y\nCONFIG_HW_RANDOM_VIA=y\n# CONFIG_HYPERVISOR_GUEST is not set\nCONFIG_HZ_PERIODIC=y\nCONFIG_I8253_LOCK=y\n# CONFIG_I8K is not set\nCONFIG_IA32_FEAT_CTL=y\n# CONFIG_IB700_WDT is not set\n# CONFIG_IBMASR is not set\n# CONFIG_IBM_RTL is not set\n# CONFIG_IE6XX_WDT is not set\nCONFIG_ILLEGAL_POINTER_VALUE=0\nCONFIG_INITRAMFS_SOURCE=\"\"\nCONFIG_INPUT=y\nCONFIG_INPUT_KEYBOARD=y\nCONFIG_INSTRUCTION_DECODER=y\n# CONFIG_INTEL_INT0002_VGPIO is not set\n# CONFIG_INTEL_PCH_THERMAL is not set\n# CONFIG_INTEL_POWERCLAMP is not set\n# CONFIG_INTEL_SCU_PCI is not set\n# CONFIG_IOSF_MBI is not set\nCONFIG_IO_DELAY_0X80=y\n# CONFIG_IO_DELAY_0XED is not set\n# CONFIG_IO_DELAY_NONE is not set\n# CONFIG_IO_DELAY_UDELAY is not set\nCONFIG_IO_URING=y\nCONFIG_IRQ_DOMAIN=y\nCONFIG_IRQ_DOMAIN_HIERARCHY=y\nCONFIG_IRQ_FORCED_THREADING=y\nCONFIG_IRQ_WORK=y\n# CONFIG_ISA is not set\nCONFIG_ISA_DMA_API=y\n# CONFIG_IT8712F_WDT is not set\n# CONFIG_IT87_WDT is not set\n# CONFIG_ITCO_WDT is not set\nCONFIG_JBD2=y\nCONFIG_KALLSYMS=y\nCONFIG_KEXEC=y\nCONFIG_KEXEC_CORE=y\nCONFIG_KEYBOARD_ATKBD=y\n# CONFIG_LEDS_CLEVO_MAIL is not set\nCONFIG_LOCK_DEBUGGING_SUPPORT=y\n# CONFIG_M486 is not set\n# CONFIG_M486SX is not set\n# CONFIG_M586 is not set\n# CONFIG_M586MMX is not set\n# CONFIG_M586TSC is not set\nCONFIG_M686=y\n# CONFIG_MACHZ_WDT is not set\n# CONFIG_MATOM is not set\n# CONFIG_MCORE2 is not set\n# CONFIG_MCRUSOE is not set\n# CONFIG_MCYRIXIII is not set\n# CONFIG_MEFFICEON is not set\n# CONFIG_MELAN is not set\nCONFIG_MEMFD_CREATE=y\n# CONFIG_MFD_INTEL_LPSS_PCI is not set\n# CONFIG_MGEODEGX1 is not set\n# CONFIG_MGEODE_LX is not set\nCONFIG_MICROCODE=y\nCONFIG_MICROCODE_AMD=y\nCONFIG_MICROCODE_INTEL=y\nCONFIG_MICROCODE_OLD_INTERFACE=y\nCONFIG_MIGRATION=y\n# CONFIG_MK6 is not set\n# CONFIG_MK7 is not set\n# CONFIG_MK8 is not set\n# CONFIG_MODIFY_LDT_SYSCALL is not set\nCONFIG_MODULES_TREE_LOOKUP=y\nCONFIG_MODULES_USE_ELF_REL=y\n# CONFIG_MPENTIUM4 is not set\n# CONFIG_MPENTIUMII is not set\n# CONFIG_MPENTIUMIII is not set\n# CONFIG_MPENTIUMM is not set\n# CONFIG_MTD is not set\nCONFIG_MTRR=y\n# CONFIG_MTRR_SANITIZER is not set\n# CONFIG_MVIAC3_2 is not set\n# CONFIG_MVIAC7 is not set\n# CONFIG_MWINCHIP3D is not set\n# CONFIG_MWINCHIPC6 is not set\nCONFIG_NAMESPACES=y\nCONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK=y\nCONFIG_NEED_PER_CPU_KM=y\nCONFIG_NEED_PER_CPU_PAGE_FIRST_CHUNK=y\nCONFIG_NEED_SG_DMA_LENGTH=y\n# CONFIG_NET5501 is not set\n# CONFIG_NET_NS is not set\nCONFIG_NLS=y\n# CONFIG_NOHIGHMEM is not set\nCONFIG_NR_CPUS=1\nCONFIG_NR_CPUS_DEFAULT=1\nCONFIG_NR_CPUS_RANGE_BEGIN=1\nCONFIG_NR_CPUS_RANGE_END=1\n# CONFIG_NSC_GPIO is not set\nCONFIG_NVRAM=y\n# CONFIG_OF is not set\nCONFIG_OLD_SIGACTION=y\nCONFIG_OLD_SIGSUSPEND3=y\n# CONFIG_OLPC is not set\nCONFIG_OPROFILE_NMI_TIMER=y\nCONFIG_OUTPUT_FORMAT=\"elf32-i386\"\nCONFIG_PAGE_OFFSET=0xC0000000\nCONFIG_PC104=y\n# CONFIG_PC8736x_GPIO is not set\n# CONFIG_PC87413_WDT is not set\nCONFIG_PCI=y\nCONFIG_PCI_ATS=y\nCONFIG_PCI_BIOS=y\nCONFIG_PCI_DIRECT=y\nCONFIG_PCI_DOMAINS=y\nCONFIG_PCI_GOANY=y\n# CONFIG_PCI_GOBIOS is not set\n# CONFIG_PCI_GODIRECT is not set\n# CONFIG_PCI_GOMMCONFIG is not set\nCONFIG_PCI_IOV=y\nCONFIG_PCI_LABEL=y\nCONFIG_PCI_LOCKLESS_CONFIG=y\nCONFIG_PCI_MSI=y\nCONFIG_PCI_MSI_IRQ_DOMAIN=y\nCONFIG_PCSPKR_PLATFORM=y\nCONFIG_PERF_EVENTS=y\nCONFIG_PERF_EVENTS_INTEL_CSTATE=y\nCONFIG_PERF_EVENTS_INTEL_RAPL=y\nCONFIG_PERF_EVENTS_INTEL_UNCORE=y\nCONFIG_PGTABLE_LEVELS=2\nCONFIG_PHYSICAL_ALIGN=0x100000\nCONFIG_PHYSICAL_START=0x1000000\n# CONFIG_PHY_INTEL_LGM_EMMC is not set\nCONFIG_PMC_ATOM=y\nCONFIG_POSIX_CPU_TIMERS_TASK_WORK=y\nCONFIG_POWER_SUPPLY=y\n# CONFIG_PROCESSOR_SELECT is not set\nCONFIG_PROC_PAGE_MONITOR=y\nCONFIG_PROC_PID_ARCH_STATUS=y\n# CONFIG_PROVIDE_OHCI1394_DMA_INIT is not set\n# CONFIG_PUNIT_ATOM_DEBUG is not set\nCONFIG_RATIONAL=y\nCONFIG_RD_BZIP2=y\nCONFIG_RD_GZIP=y\nCONFIG_RETPOLINE=y\nCONFIG_RTC_CLASS=y\nCONFIG_RTC_MC146818_LIB=y\nCONFIG_SATA_HOST=y\n# CONFIG_SBC7240_WDT is not set\n# CONFIG_SBC8360_WDT is not set\n# CONFIG_SBC_EPX_C3_WATCHDOG is not set\n# CONFIG_SC1200_WDT is not set\nCONFIG_SCSI=y\nCONFIG_SCSI_SPI_ATTRS=y\nCONFIG_SCx200=y\nCONFIG_SCx200HR_TIMER=y\n# CONFIG_SCx200_GPIO is not set\n# CONFIG_SCx200_WDT is not set\nCONFIG_SERIAL_8250_PCI=y\n# CONFIG_SERIAL_LANTIQ is not set\nCONFIG_SERIO=y\nCONFIG_SERIO_I8042=y\nCONFIG_SERIO_LIBPS2=y\nCONFIG_SERIO_SERPORT=y\nCONFIG_SG_POOL=y\n# CONFIG_SMSC37B787_WDT is not set\n# CONFIG_SMSC_SCH311X_WDT is not set\nCONFIG_SPARSEMEM_STATIC=y\nCONFIG_SPARSE_IRQ=y\nCONFIG_SRCU=y\n# CONFIG_STATIC_CALL_SELFTEST is not set\nCONFIG_SYSCTL_EXCEPTION_TRACE=y\n# CONFIG_TELCLOCK is not set\n# CONFIG_TEST_FPU is not set\nCONFIG_THERMAL=y\nCONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y\nCONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0\nCONFIG_THERMAL_GOV_STEP_WISE=y\nCONFIG_THREAD_INFO_IN_TASK=y\nCONFIG_TICK_CPU_ACCOUNTING=y\nCONFIG_TINY_SRCU=y\n# CONFIG_TOSHIBA is not set\n# CONFIG_TQMX86_WDT is not set\nCONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y\nCONFIG_UNWINDER_FRAME_POINTER=y\n# CONFIG_UNWINDER_GUESS is not set\nCONFIG_UP_LATE_INIT=y\nCONFIG_USB=y\nCONFIG_USB_COMMON=y\nCONFIG_USB_EHCI_HCD=y\n# CONFIG_USB_EHCI_HCD_PLATFORM is not set\nCONFIG_USB_EHCI_PCI=y\nCONFIG_USB_HID=y\nCONFIG_USB_HIDDEV=y\nCONFIG_USB_OHCI_HCD=y\nCONFIG_USB_OHCI_HCD_PCI=y\n# CONFIG_USB_OHCI_HCD_PLATFORM is not set\nCONFIG_USB_PCI=y\nCONFIG_USB_SUPPORT=y\nCONFIG_USB_UHCI_HCD=y\nCONFIG_USB_XHCI_HCD=y\nCONFIG_USB_XHCI_PCI=y\n# CONFIG_USB_XHCI_PLATFORM is not set\n# CONFIG_USER_NS is not set\nCONFIG_USER_STACKTRACE_SUPPORT=y\nCONFIG_VGA_CONSOLE=y\n# CONFIG_VIA_WDT is not set\n# CONFIG_VMWARE_VMCI is not set\nCONFIG_VM_EVENT_COUNTERS=y\nCONFIG_VT=y\nCONFIG_VT_CONSOLE=y\nCONFIG_VT_HW_CONSOLE_BINDING=y\n# CONFIG_WAFER_WDT is not set\nCONFIG_X86=y\nCONFIG_X86_32=y\n# CONFIG_X86_32_IRIS is not set\nCONFIG_X86_32_LAZY_GS=y\n# CONFIG_X86_ANCIENT_MCE is not set\n# CONFIG_X86_CHECK_BIOS_CORRUPTION is not set\nCONFIG_X86_CMOV=y\nCONFIG_X86_CMPXCHG64=y\n# CONFIG_X86_CPA_STATISTICS is not set\n# CONFIG_X86_CPUFREQ_NFORCE2 is not set\n# CONFIG_X86_CPUID is not set\n# CONFIG_X86_CPU_RESCTRL is not set\nCONFIG_X86_DEBUGCTLMSR=y\n# CONFIG_X86_DEBUG_FPU is not set\n# CONFIG_X86_DECODER_SELFTEST is not set\n# CONFIG_X86_EXTENDED_PLATFORM is not set\nCONFIG_X86_FEATURE_NAMES=y\nCONFIG_X86_GENERIC=y\n# CONFIG_X86_GX_SUSPMOD is not set\n# CONFIG_X86_INTEL_PSTATE is not set\n# CONFIG_X86_INTEL_TSX_MODE_AUTO is not set\nCONFIG_X86_INTEL_TSX_MODE_OFF=y\n# CONFIG_X86_INTEL_TSX_MODE_ON is not set\nCONFIG_X86_INTEL_USERCOPY=y\nCONFIG_X86_INTERNODE_CACHE_SHIFT=6\nCONFIG_X86_IOPL_IOPERM=y\nCONFIG_X86_IO_APIC=y\nCONFIG_X86_L1_CACHE_SHIFT=6\n# CONFIG_X86_LEGACY_VM86 is not set\nCONFIG_X86_LOCAL_APIC=y\n# CONFIG_X86_LONGRUN is not set\nCONFIG_X86_MCE=y\n# CONFIG_X86_MCELOG_LEGACY is not set\nCONFIG_X86_MCE_AMD=y\n# CONFIG_X86_MCE_INJECT is not set\nCONFIG_X86_MCE_INTEL=y\nCONFIG_X86_MCE_THRESHOLD=y\nCONFIG_X86_MINIMUM_CPU_FAMILY=6\nCONFIG_X86_MPPARSE=y\nCONFIG_X86_MSR=y\n# CONFIG_X86_P4_CLOCKMOD is not set\nCONFIG_X86_PAT=y\nCONFIG_X86_PLATFORM_DEVICES=y\n# CONFIG_X86_POWERNOW_K6 is not set\n# CONFIG_X86_POWERNOW_K7 is not set\n# CONFIG_X86_REBOOTFIXUPS is not set\nCONFIG_X86_REROUTE_FOR_BROKEN_BOOT_IRQS=y\nCONFIG_X86_RESERVE_LOW=64\nCONFIG_X86_SMAP=y\n# CONFIG_X86_SPEEDSTEP_CENTRINO is not set\n# CONFIG_X86_SPEEDSTEP_ICH is not set\n# CONFIG_X86_SPEEDSTEP_SMI is not set\nCONFIG_X86_SUPPORTS_MEMORY_FAILURE=y\nCONFIG_X86_THERMAL_VECTOR=y\nCONFIG_X86_TSC=y\nCONFIG_X86_UMIP=y\nCONFIG_X86_UP_APIC=y\nCONFIG_X86_UP_IOAPIC=y\nCONFIG_X86_USE_PPRO_CHECKSUM=y\nCONFIG_X86_VERBOSE_BOOTUP=y\nCONFIG_X86_VMX_FEATURE_NAMES=y\nCONFIG_XZ_DEC_BCJ=y\nCONFIG_XZ_DEC_X86=y\nCONFIG_ZLIB_INFLATE=y\n"
  },
  {
    "path": "target/linux/x86/config-5.15",
    "content": "# CONFIG_60XX_WDT is not set\n# CONFIG_64BIT is not set\n# CONFIG_ACPI is not set\n# CONFIG_ACQUIRE_WDT is not set\n# CONFIG_ADVANTECH_WDT is not set\n# CONFIG_ALIM1535_WDT is not set\n# CONFIG_ALIX is not set\nCONFIG_AMD_NB=y\nCONFIG_ARCH_32BIT_OFF_T=y\nCONFIG_ARCH_CLOCKSOURCE_INIT=y\nCONFIG_ARCH_HIBERNATION_POSSIBLE=y\nCONFIG_ARCH_MAY_HAVE_PC_FDC=y\nCONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y\nCONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y\nCONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y\nCONFIG_ARCH_NR_GPIO=512\nCONFIG_ARCH_RANDOM=y\nCONFIG_ARCH_SELECT_MEMORY_MODEL=y\nCONFIG_ARCH_SPARSEMEM_ENABLE=y\nCONFIG_ARCH_SPLIT_ARG64=y\nCONFIG_ARCH_STACKWALK=y\nCONFIG_ARCH_SUSPEND_POSSIBLE=y\nCONFIG_ARCH_USES_PG_UNCACHED=y\nCONFIG_ARCH_WANTS_DYNAMIC_TASK_STRUCT=y\nCONFIG_ARCH_WANTS_NO_INSTR=y\nCONFIG_ATA=y\nCONFIG_ATA_GENERIC=y\nCONFIG_ATA_PIIX=y\nCONFIG_BLK_DEV_LOOP=y\nCONFIG_BLK_DEV_SD=y\nCONFIG_BLK_MQ_PCI=y\nCONFIG_BOUNCE=y\nCONFIG_CLKBLD_I8253=y\nCONFIG_CLKEVT_I8253=y\nCONFIG_CLKSRC_I8253=y\nCONFIG_CLOCKSOURCE_VALIDATE_LAST_CYCLE=y\nCONFIG_CLOCKSOURCE_WATCHDOG=y\nCONFIG_CLONE_BACKWARDS=y\nCONFIG_COMMON_CLK=y\nCONFIG_COMPAT_32=y\nCONFIG_COMPAT_32BIT_TIME=y\n# CONFIG_COMPAT_VDSO is not set\nCONFIG_CONSOLE_TRANSLATIONS=y\n# CONFIG_CPU5_WDT is not set\nCONFIG_CPU_FREQ=y\nCONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y\n# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set\nCONFIG_CPU_FREQ_GOV_ATTR_SET=y\nCONFIG_CPU_FREQ_GOV_COMMON=y\n# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set\nCONFIG_CPU_FREQ_GOV_ONDEMAND=y\nCONFIG_CPU_FREQ_GOV_PERFORMANCE=y\n# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set\n# CONFIG_CPU_FREQ_GOV_USERSPACE is not set\nCONFIG_CPU_FREQ_STAT=y\nCONFIG_CPU_IDLE=y\nCONFIG_CPU_IDLE_GOV_LADDER=y\nCONFIG_CPU_SUP_AMD=y\nCONFIG_CPU_SUP_CENTAUR=y\nCONFIG_CPU_SUP_CYRIX_32=y\nCONFIG_CPU_SUP_HYGON=y\nCONFIG_CPU_SUP_INTEL=y\nCONFIG_CPU_SUP_TRANSMETA_32=y\nCONFIG_CPU_SUP_UMC_32=y\nCONFIG_CPU_SUP_ZHAOXIN=y\nCONFIG_CRASH_CORE=y\nCONFIG_CRC16=y\nCONFIG_CRYPTO_CRC32=y\nCONFIG_CRYPTO_CRC32C=y\n# CONFIG_CRYPTO_CRC32_PCLMUL is not set\nCONFIG_CRYPTO_LIB_POLY1305_RSIZE=1\nCONFIG_CRYPTO_RNG2=y\n# CONFIG_CRYPTO_SERPENT_SSE2_586 is not set\n# CONFIG_CX_ECAT is not set\nCONFIG_DCACHE_WORD_ACCESS=y\n# CONFIG_DEBUG_BOOT_PARAMS is not set\n# CONFIG_DEBUG_ENTRY is not set\n# CONFIG_DEBUG_KMAP_LOCAL_FORCE_MAP is not set\nCONFIG_DEBUG_MEMORY_INIT=y\nCONFIG_DEBUG_MISC=y\n# CONFIG_DEBUG_NMI_SELFTEST is not set\n# CONFIG_DEBUG_TLBFLUSH is not set\nCONFIG_DECOMPRESS_BZIP2=y\nCONFIG_DECOMPRESS_GZIP=y\nCONFIG_DMADEVICES=y\nCONFIG_DMI=y\nCONFIG_DMIID=y\nCONFIG_DMI_SCAN_MACHINE_NON_EFI_FALLBACK=y\nCONFIG_DMI_SYSFS=y\nCONFIG_DNOTIFY=y\nCONFIG_DUMMY_CONSOLE=y\nCONFIG_EARLY_PRINTK=y\n# CONFIG_EARLY_PRINTK_DBGP is not set\nCONFIG_EDAC_ATOMIC_SCRUB=y\nCONFIG_EDAC_SUPPORT=y\n# CONFIG_EDD is not set\n# CONFIG_EISA is not set\n# CONFIG_EUROTECH_WDT is not set\nCONFIG_EXT4_FS=y\nCONFIG_F2FS_FS=y\n# CONFIG_F71808E_WDT is not set\nCONFIG_FIRMWARE_MEMMAP=y\nCONFIG_FIX_EARLYCON_MEM=y\nCONFIG_FRAME_POINTER=y\nCONFIG_FS_IOMAP=y\nCONFIG_FS_MBCACHE=y\nCONFIG_FUSION=y\n# CONFIG_FUSION_CTL is not set\n# CONFIG_FUSION_LOGGING is not set\nCONFIG_FUSION_MAX_SGE=128\nCONFIG_FUSION_SPI=y\nCONFIG_FW_LOADER_PAGED_BUF=y\nCONFIG_GENERIC_ALLOCATOR=y\nCONFIG_GENERIC_BUG=y\nCONFIG_GENERIC_CLOCKEVENTS=y\nCONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y\nCONFIG_GENERIC_CLOCKEVENTS_MIN_ADJUST=y\nCONFIG_GENERIC_CMOS_UPDATE=y\nCONFIG_GENERIC_CPU_AUTOPROBE=y\nCONFIG_GENERIC_CPU_VULNERABILITIES=y\nCONFIG_GENERIC_EARLY_IOREMAP=y\nCONFIG_GENERIC_ENTRY=y\nCONFIG_GENERIC_FIND_FIRST_BIT=y\nCONFIG_GENERIC_GETTIMEOFDAY=y\nCONFIG_GENERIC_IOMAP=y\nCONFIG_GENERIC_IRQ_MATRIX_ALLOCATOR=y\nCONFIG_GENERIC_IRQ_RESERVATION_MODE=y\nCONFIG_GENERIC_IRQ_SHOW=y\nCONFIG_GENERIC_ISA_DMA=y\nCONFIG_GENERIC_MSI_IRQ=y\nCONFIG_GENERIC_MSI_IRQ_DOMAIN=y\nCONFIG_GENERIC_PCI_IOMAP=y\nCONFIG_GENERIC_SMP_IDLE_THREAD=y\nCONFIG_GENERIC_STRNCPY_FROM_USER=y\nCONFIG_GENERIC_STRNLEN_USER=y\nCONFIG_GENERIC_TIME_VSYSCALL=y\nCONFIG_GENERIC_VDSO_32=y\n# CONFIG_GEOS is not set\nCONFIG_GLOB=y\n# CONFIG_HANGCHECK_TIMER is not set\nCONFIG_HARDIRQS_SW_RESEND=y\nCONFIG_HAS_DMA=y\nCONFIG_HAS_IOMEM=y\nCONFIG_HAS_IOPORT_MAP=y\nCONFIG_HID=y\nCONFIG_HIGHMEM=y\nCONFIG_HIGHMEM4G=y\n# CONFIG_HIGHMEM64G is not set\nCONFIG_HIGHPTE=y\nCONFIG_HPET_EMULATE_RTC=y\nCONFIG_HPET_TIMER=y\n# CONFIG_HP_WATCHDOG is not set\nCONFIG_HW_CONSOLE=y\nCONFIG_HW_RANDOM=y\nCONFIG_HW_RANDOM_GEODE=y\nCONFIG_HW_RANDOM_VIA=y\n# CONFIG_HYPERVISOR_GUEST is not set\nCONFIG_HZ_PERIODIC=y\nCONFIG_I8253_LOCK=y\nCONFIG_IA32_FEAT_CTL=y\n# CONFIG_IB700_WDT is not set\n# CONFIG_IBMASR is not set\n# CONFIG_IBM_RTL is not set\n# CONFIG_IE6XX_WDT is not set\nCONFIG_ILLEGAL_POINTER_VALUE=0\nCONFIG_INITRAMFS_SOURCE=\"\"\nCONFIG_INPUT=y\nCONFIG_INPUT_KEYBOARD=y\nCONFIG_INSTRUCTION_DECODER=y\n# CONFIG_INTEL_LDMA is not set\n# CONFIG_INTEL_PCH_THERMAL is not set\n# CONFIG_INTEL_POWERCLAMP is not set\n# CONFIG_INTEL_SCU_PCI is not set\n# CONFIG_INTEL_TCC_COOLING is not set\n# CONFIG_IOSF_MBI is not set\nCONFIG_IO_DELAY_0X80=y\n# CONFIG_IO_DELAY_0XED is not set\n# CONFIG_IO_DELAY_NONE is not set\n# CONFIG_IO_DELAY_UDELAY is not set\nCONFIG_IO_URING=y\nCONFIG_IRQ_DOMAIN=y\nCONFIG_IRQ_DOMAIN_HIERARCHY=y\nCONFIG_IRQ_FORCED_THREADING=y\nCONFIG_IRQ_WORK=y\n# CONFIG_ISA is not set\nCONFIG_ISA_DMA_API=y\n# CONFIG_IT8712F_WDT is not set\n# CONFIG_IT87_WDT is not set\n# CONFIG_ITCO_WDT is not set\nCONFIG_JBD2=y\nCONFIG_KALLSYMS=y\nCONFIG_KEXEC=y\nCONFIG_KEXEC_CORE=y\nCONFIG_KEYBOARD_ATKBD=y\nCONFIG_KMAP_LOCAL=y\n# CONFIG_LEDS_CLEVO_MAIL is not set\nCONFIG_LOCK_DEBUGGING_SUPPORT=y\n# CONFIG_M486 is not set\n# CONFIG_M486SX is not set\n# CONFIG_M586 is not set\n# CONFIG_M586MMX is not set\n# CONFIG_M586TSC is not set\nCONFIG_M686=y\n# CONFIG_MACHZ_WDT is not set\n# CONFIG_MATOM is not set\n# CONFIG_MCORE2 is not set\n# CONFIG_MCRUSOE is not set\n# CONFIG_MCYRIXIII is not set\n# CONFIG_MEFFICEON is not set\n# CONFIG_MELAN is not set\nCONFIG_MEMFD_CREATE=y\n# CONFIG_MFD_INTEL_LPSS_PCI is not set\n# CONFIG_MGEODEGX1 is not set\n# CONFIG_MGEODE_LX is not set\nCONFIG_MICROCODE=y\nCONFIG_MICROCODE_AMD=y\nCONFIG_MICROCODE_INTEL=y\nCONFIG_MICROCODE_OLD_INTERFACE=y\nCONFIG_MIGRATION=y\n# CONFIG_MK6 is not set\n# CONFIG_MK7 is not set\n# CONFIG_MK8 is not set\n# CONFIG_MODIFY_LDT_SYSCALL is not set\nCONFIG_MODULES_TREE_LOOKUP=y\nCONFIG_MODULES_USE_ELF_REL=y\n# CONFIG_MPENTIUM4 is not set\n# CONFIG_MPENTIUMII is not set\n# CONFIG_MPENTIUMIII is not set\n# CONFIG_MPENTIUMM is not set\n# CONFIG_MTD is not set\nCONFIG_MTRR=y\n# CONFIG_MTRR_SANITIZER is not set\n# CONFIG_MVIAC3_2 is not set\n# CONFIG_MVIAC7 is not set\n# CONFIG_MWINCHIP3D is not set\n# CONFIG_MWINCHIPC6 is not set\nCONFIG_NAMESPACES=y\nCONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK=y\nCONFIG_NEED_PER_CPU_KM=y\nCONFIG_NEED_PER_CPU_PAGE_FIRST_CHUNK=y\nCONFIG_NEED_SG_DMA_LENGTH=y\n# CONFIG_NET5501 is not set\n# CONFIG_NET_NS is not set\nCONFIG_NLS=y\n# CONFIG_NOHIGHMEM is not set\nCONFIG_NR_CPUS=1\nCONFIG_NR_CPUS_DEFAULT=1\nCONFIG_NR_CPUS_RANGE_BEGIN=1\nCONFIG_NR_CPUS_RANGE_END=1\n# CONFIG_NSC_GPIO is not set\nCONFIG_NVRAM=y\n# CONFIG_OF is not set\nCONFIG_OLD_SIGACTION=y\nCONFIG_OLD_SIGSUSPEND3=y\n# CONFIG_OLPC is not set\nCONFIG_OUTPUT_FORMAT=\"elf32-i386\"\nCONFIG_PAGE_OFFSET=0xC0000000\nCONFIG_PC104=y\n# CONFIG_PC8736x_GPIO is not set\n# CONFIG_PC87413_WDT is not set\nCONFIG_PCI=y\nCONFIG_PCI_ATS=y\nCONFIG_PCI_BIOS=y\nCONFIG_PCI_DIRECT=y\nCONFIG_PCI_DOMAINS=y\nCONFIG_PCI_GOANY=y\n# CONFIG_PCI_GOBIOS is not set\n# CONFIG_PCI_GODIRECT is not set\n# CONFIG_PCI_GOMMCONFIG is not set\nCONFIG_PCI_IOV=y\nCONFIG_PCI_LABEL=y\nCONFIG_PCI_LOCKLESS_CONFIG=y\nCONFIG_PCI_MSI=y\nCONFIG_PCI_MSI_IRQ_DOMAIN=y\nCONFIG_PCSPKR_PLATFORM=y\nCONFIG_PERF_EVENTS=y\n# CONFIG_PERF_EVENTS_AMD_UNCORE is not set\nCONFIG_PERF_EVENTS_INTEL_CSTATE=y\nCONFIG_PERF_EVENTS_INTEL_RAPL=y\nCONFIG_PERF_EVENTS_INTEL_UNCORE=y\nCONFIG_PGTABLE_LEVELS=2\nCONFIG_PHYSICAL_ALIGN=0x100000\nCONFIG_PHYSICAL_START=0x1000000\n# CONFIG_PHY_INTEL_LGM_EMMC is not set\nCONFIG_PMC_ATOM=y\nCONFIG_POSIX_CPU_TIMERS_TASK_WORK=y\nCONFIG_POWER_SUPPLY=y\n# CONFIG_PROCESSOR_SELECT is not set\nCONFIG_PROC_PAGE_MONITOR=y\nCONFIG_PROC_PID_ARCH_STATUS=y\n# CONFIG_PROVIDE_OHCI1394_DMA_INIT is not set\nCONFIG_PTP_1588_CLOCK_OPTIONAL=y\n# CONFIG_PUNIT_ATOM_DEBUG is not set\nCONFIG_RATIONAL=y\nCONFIG_RD_BZIP2=y\nCONFIG_RD_GZIP=y\nCONFIG_RETPOLINE=y\nCONFIG_RTC_CLASS=y\nCONFIG_RTC_MC146818_LIB=y\nCONFIG_SATA_HOST=y\n# CONFIG_SBC7240_WDT is not set\n# CONFIG_SBC8360_WDT is not set\n# CONFIG_SBC_EPX_C3_WATCHDOG is not set\n# CONFIG_SC1200_WDT is not set\nCONFIG_SCSI=y\nCONFIG_SCSI_COMMON=y\nCONFIG_SCSI_SPI_ATTRS=y\nCONFIG_SCx200=y\nCONFIG_SCx200HR_TIMER=y\n# CONFIG_SCx200_GPIO is not set\n# CONFIG_SCx200_WDT is not set\nCONFIG_SERIAL_8250_PCI=y\n# CONFIG_SERIAL_LANTIQ is not set\nCONFIG_SERIO=y\nCONFIG_SERIO_I8042=y\nCONFIG_SERIO_LIBPS2=y\nCONFIG_SERIO_SERPORT=y\nCONFIG_SG_POOL=y\n# CONFIG_SMSC37B787_WDT is not set\n# CONFIG_SMSC_SCH311X_WDT is not set\nCONFIG_SPARSEMEM_STATIC=y\nCONFIG_SPARSE_IRQ=y\nCONFIG_SRCU=y\n# CONFIG_STATIC_CALL_SELFTEST is not set\nCONFIG_SYSCTL_EXCEPTION_TRACE=y\nCONFIG_SYSFB=y\n# CONFIG_SYSFB_SIMPLEFB is not set\n# CONFIG_TELCLOCK is not set\n# CONFIG_TEST_FPU is not set\nCONFIG_THERMAL=y\nCONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y\nCONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0\nCONFIG_THERMAL_GOV_STEP_WISE=y\nCONFIG_THREAD_INFO_IN_TASK=y\nCONFIG_TICK_CPU_ACCOUNTING=y\nCONFIG_TINY_SRCU=y\n# CONFIG_TOSHIBA is not set\n# CONFIG_TQMX86_WDT is not set\nCONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y\nCONFIG_UNWINDER_FRAME_POINTER=y\n# CONFIG_UNWINDER_GUESS is not set\nCONFIG_UP_LATE_INIT=y\nCONFIG_USB=y\nCONFIG_USB_COMMON=y\nCONFIG_USB_EHCI_HCD=y\n# CONFIG_USB_EHCI_HCD_PLATFORM is not set\nCONFIG_USB_EHCI_PCI=y\nCONFIG_USB_HID=y\nCONFIG_USB_HIDDEV=y\nCONFIG_USB_OHCI_HCD=y\nCONFIG_USB_OHCI_HCD_PCI=y\n# CONFIG_USB_OHCI_HCD_PLATFORM is not set\nCONFIG_USB_PCI=y\nCONFIG_USB_SUPPORT=y\nCONFIG_USB_UHCI_HCD=y\nCONFIG_USB_XHCI_HCD=y\nCONFIG_USB_XHCI_PCI=y\n# CONFIG_USB_XHCI_PLATFORM is not set\n# CONFIG_USER_NS is not set\nCONFIG_USER_STACKTRACE_SUPPORT=y\nCONFIG_VGA_CONSOLE=y\n# CONFIG_VIA_WDT is not set\n# CONFIG_VMWARE_VMCI is not set\nCONFIG_VM_EVENT_COUNTERS=y\nCONFIG_VT=y\nCONFIG_VT_CONSOLE=y\nCONFIG_VT_HW_CONSOLE_BINDING=y\n# CONFIG_WAFER_WDT is not set\nCONFIG_X86=y\nCONFIG_X86_32=y\n# CONFIG_X86_32_IRIS is not set\n# CONFIG_X86_ANCIENT_MCE is not set\n# CONFIG_X86_CHECK_BIOS_CORRUPTION is not set\nCONFIG_X86_CMOV=y\nCONFIG_X86_CMPXCHG64=y\n# CONFIG_X86_CPA_STATISTICS is not set\n# CONFIG_X86_CPUFREQ_NFORCE2 is not set\n# CONFIG_X86_CPUID is not set\n# CONFIG_X86_CPU_RESCTRL is not set\nCONFIG_X86_DEBUGCTLMSR=y\n# CONFIG_X86_DEBUG_FPU is not set\n# CONFIG_X86_DECODER_SELFTEST is not set\n# CONFIG_X86_EXTENDED_PLATFORM is not set\nCONFIG_X86_FEATURE_NAMES=y\nCONFIG_X86_GENERIC=y\n# CONFIG_X86_GX_SUSPMOD is not set\n# CONFIG_X86_INTEL_PSTATE is not set\n# CONFIG_X86_INTEL_TSX_MODE_AUTO is not set\nCONFIG_X86_INTEL_TSX_MODE_OFF=y\n# CONFIG_X86_INTEL_TSX_MODE_ON is not set\nCONFIG_X86_INTEL_USERCOPY=y\nCONFIG_X86_INTERNODE_CACHE_SHIFT=6\nCONFIG_X86_IOPL_IOPERM=y\nCONFIG_X86_IO_APIC=y\nCONFIG_X86_L1_CACHE_SHIFT=6\n# CONFIG_X86_LEGACY_VM86 is not set\nCONFIG_X86_LOCAL_APIC=y\n# CONFIG_X86_LONGRUN is not set\nCONFIG_X86_MCE=y\n# CONFIG_X86_MCELOG_LEGACY is not set\nCONFIG_X86_MCE_AMD=y\n# CONFIG_X86_MCE_INJECT is not set\nCONFIG_X86_MCE_INTEL=y\nCONFIG_X86_MCE_THRESHOLD=y\nCONFIG_X86_MINIMUM_CPU_FAMILY=6\nCONFIG_X86_MPPARSE=y\nCONFIG_X86_MSR=y\n# CONFIG_X86_P4_CLOCKMOD is not set\nCONFIG_X86_PAT=y\nCONFIG_X86_PLATFORM_DEVICES=y\n# CONFIG_X86_PLATFORM_DRIVERS_DELL is not set\n# CONFIG_X86_POWERNOW_K6 is not set\n# CONFIG_X86_POWERNOW_K7 is not set\n# CONFIG_X86_REBOOTFIXUPS is not set\nCONFIG_X86_REROUTE_FOR_BROKEN_BOOT_IRQS=y\nCONFIG_X86_SMAP=y\n# CONFIG_X86_SPEEDSTEP_CENTRINO is not set\n# CONFIG_X86_SPEEDSTEP_ICH is not set\n# CONFIG_X86_SPEEDSTEP_SMI is not set\nCONFIG_X86_SUPPORTS_MEMORY_FAILURE=y\nCONFIG_X86_THERMAL_VECTOR=y\nCONFIG_X86_TSC=y\nCONFIG_X86_UMIP=y\nCONFIG_X86_UP_APIC=y\nCONFIG_X86_UP_IOAPIC=y\nCONFIG_X86_USE_PPRO_CHECKSUM=y\nCONFIG_X86_VERBOSE_BOOTUP=y\nCONFIG_X86_VMX_FEATURE_NAMES=y\nCONFIG_XZ_DEC_BCJ=y\nCONFIG_XZ_DEC_X86=y\nCONFIG_ZLIB_INFLATE=y\n"
  },
  {
    "path": "target/linux/x86/generic/base-files/lib/preinit/45_mount_xenfs",
    "content": "# Copyright (C) 2010 OpenWrt.org\n\ndo_mount_xenfs() {\n\tgrep -q xenfs /proc/filesystems && \\\n\t\tmount -o noatime -t xenfs none /proc/xen\n}\n\nboot_hook_add preinit_mount_root do_mount_xenfs\n"
  },
  {
    "path": "target/linux/x86/generic/config-5.10",
    "content": "# CONFIG_3C515 is not set\nCONFIG_ACPI=y\nCONFIG_ACPI_AC=y\nCONFIG_ACPI_BATTERY=y\n# CONFIG_ACPI_BGRT is not set\nCONFIG_ACPI_BUTTON=y\n# CONFIG_ACPI_CMPC is not set\nCONFIG_ACPI_CONTAINER=y\nCONFIG_ACPI_CPU_FREQ_PSS=y\n# CONFIG_ACPI_DEBUG is not set\n# CONFIG_ACPI_DEBUGGER is not set\n# CONFIG_ACPI_DOCK is not set\n# CONFIG_ACPI_DPTF is not set\n# CONFIG_ACPI_EC_DEBUGFS is not set\n# CONFIG_ACPI_FAN is not set\nCONFIG_ACPI_HOTPLUG_CPU=y\nCONFIG_ACPI_HOTPLUG_IOAPIC=y\n# CONFIG_ACPI_I2C_OPREGION is not set\nCONFIG_ACPI_LEGACY_TABLES_LOOKUP=y\n# CONFIG_ACPI_PCI_SLOT is not set\nCONFIG_ACPI_PROCESSOR=y\n# CONFIG_ACPI_PROCESSOR_AGGREGATOR is not set\nCONFIG_ACPI_PROCESSOR_CSTATE=y\nCONFIG_ACPI_PROCESSOR_IDLE=y\nCONFIG_ACPI_REV_OVERRIDE_POSSIBLE=y\n# CONFIG_ACPI_SBS is not set\nCONFIG_ACPI_SPCR_TABLE=y\nCONFIG_ACPI_SYSTEM_POWER_STATES_SUPPORT=y\nCONFIG_ACPI_TAD=y\nCONFIG_ACPI_THERMAL=y\nCONFIG_ACPI_VIDEO=y\n# CONFIG_ACPI_WMI is not set\nCONFIG_AGP=y\n# CONFIG_AGP_ALI is not set\n# CONFIG_AGP_AMD is not set\n# CONFIG_AGP_AMD64 is not set\n# CONFIG_AGP_ATI is not set\n# CONFIG_AGP_EFFICEON is not set\nCONFIG_AGP_INTEL=y\n# CONFIG_AGP_NVIDIA is not set\n# CONFIG_AGP_SIS is not set\n# CONFIG_AGP_SWORKS is not set\n# CONFIG_AGP_VIA is not set\n# CONFIG_APM is not set\nCONFIG_ARCH_CPUIDLE_HALTPOLL=y\nCONFIG_ARCH_DMA_ADDR_T_64BIT=y\nCONFIG_ARCH_MIGHT_HAVE_ACPI_PDC=y\nCONFIG_BACKLIGHT_CLASS_DEVICE=y\nCONFIG_BALLOON_COMPACTION=y\nCONFIG_BLK_DEV_SR=y\nCONFIG_BLK_MQ_VIRTIO=y\nCONFIG_BLK_PM=y\n# CONFIG_BOOTPARAM_HOTPLUG_CPU0 is not set\nCONFIG_BTT=y\nCONFIG_CDROM=y\nCONFIG_CONNECTOR=y\nCONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y\nCONFIG_CPU_FREQ_GOV_SCHEDUTIL=y\n# CONFIG_CPU_IDLE_GOV_HALTPOLL is not set\nCONFIG_CPU_IDLE_GOV_MENU=y\nCONFIG_CPU_RMAP=y\n# CONFIG_DEBUG_HOTPLUG_CPU0 is not set\nCONFIG_DMA_ACPI=y\nCONFIG_DMA_OPS=y\nCONFIG_DMA_SHARED_BUFFER=y\nCONFIG_DRM=y\nCONFIG_DRM_BOCHS=y\nCONFIG_DRM_BRIDGE=y\nCONFIG_DRM_FBDEV_EMULATION=y\nCONFIG_DRM_FBDEV_OVERALLOC=100\nCONFIG_DRM_GEM_SHMEM_HELPER=y\nCONFIG_DRM_I915=y\nCONFIG_DRM_I915_CAPTURE_ERROR=y\nCONFIG_DRM_I915_COMPRESS_ERROR=y\n# CONFIG_DRM_I915_DEBUG is not set\n# CONFIG_DRM_I915_DEBUG_GUC is not set\n# CONFIG_DRM_I915_DEBUG_MMIO is not set\n# CONFIG_DRM_I915_DEBUG_RUNTIME_PM is not set\n# CONFIG_DRM_I915_DEBUG_VBLANK_EVADE is not set\nCONFIG_DRM_I915_FENCE_TIMEOUT=10000\nCONFIG_DRM_I915_FORCE_PROBE=\"\"\nCONFIG_DRM_I915_HEARTBEAT_INTERVAL=2500\n# CONFIG_DRM_I915_LOW_LEVEL_TRACEPOINTS is not set\nCONFIG_DRM_I915_MAX_REQUEST_BUSYWAIT=8000\nCONFIG_DRM_I915_PREEMPT_TIMEOUT=640\n# CONFIG_DRM_I915_SELFTEST is not set\nCONFIG_DRM_I915_STOP_TIMEOUT=100\n# CONFIG_DRM_I915_SW_FENCE_CHECK_DAG is not set\n# CONFIG_DRM_I915_SW_FENCE_DEBUG_OBJECTS is not set\nCONFIG_DRM_I915_TIMESLICE_DURATION=1\nCONFIG_DRM_I915_USERFAULT_AUTOSUSPEND=250\nCONFIG_DRM_I915_USERPTR=y\n# CONFIG_DRM_I915_WERROR is not set\nCONFIG_DRM_KMS_FB_HELPER=y\nCONFIG_DRM_KMS_HELPER=y\nCONFIG_DRM_MIPI_DSI=y\nCONFIG_DRM_PANEL=y\nCONFIG_DRM_PANEL_BRIDGE=y\nCONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y\nCONFIG_DRM_TTM=y\nCONFIG_DRM_TTM_DMA_PAGE_POOL=y\nCONFIG_DRM_TTM_HELPER=y\nCONFIG_DRM_VIRTIO_GPU=y\nCONFIG_DRM_VRAM_HELPER=y\nCONFIG_EFI=y\nCONFIG_EFIVAR_FS=m\n# CONFIG_EFI_BOOTLOADER_CONTROL is not set\n# CONFIG_EFI_CAPSULE_LOADER is not set\n# CONFIG_EFI_CAPSULE_QUIRK_QUARK_CSH is not set\n# CONFIG_EFI_CUSTOM_SSDT_OVERLAYS is not set\n# CONFIG_EFI_DISABLE_PCI_DMA is not set\nCONFIG_EFI_EARLYCON=y\nCONFIG_EFI_ESRT=y\n# CONFIG_EFI_FAKE_MEMMAP is not set\nCONFIG_EFI_GENERIC_STUB_INITRD_CMDLINE_LOADER=y\n# CONFIG_EFI_PGT_DUMP is not set\n# CONFIG_EFI_RCI2_TABLE is not set\nCONFIG_EFI_RUNTIME_MAP=y\nCONFIG_EFI_RUNTIME_WRAPPERS=y\nCONFIG_EFI_STUB=y\n# CONFIG_EFI_TEST is not set\n# CONFIG_EFI_VARS is not set\n# CONFIG_EL3 is not set\nCONFIG_FAILOVER=y\nCONFIG_FB=y\nCONFIG_FB_CFB_COPYAREA=y\nCONFIG_FB_CFB_FILLRECT=y\nCONFIG_FB_CFB_IMAGEBLIT=y\nCONFIG_FB_CMDLINE=y\nCONFIG_FB_DEFERRED_IO=y\nCONFIG_FB_EFI=y\nCONFIG_FB_HYPERV=y\n# CONFIG_FB_I810 is not set\nCONFIG_FB_SIMPLE=y\nCONFIG_FB_SYS_COPYAREA=y\nCONFIG_FB_SYS_FILLRECT=y\nCONFIG_FB_SYS_FOPS=y\nCONFIG_FB_SYS_IMAGEBLIT=y\n# CONFIG_FB_VESA is not set\nCONFIG_FONT_8x16=y\nCONFIG_FONT_8x8=y\nCONFIG_FONT_SUPPORT=y\nCONFIG_FRAMEBUFFER_CONSOLE=y\nCONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y\n# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set\nCONFIG_FREEZER=y\nCONFIG_FW_CACHE=y\nCONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y\nCONFIG_GENERIC_IRQ_MIGRATION=y\nCONFIG_GENERIC_PENDING_IRQ=y\nCONFIG_GENERIC_PINCONF=y\nCONFIG_GPIOLIB=y\nCONFIG_GPIOLIB_IRQCHIP=y\nCONFIG_GPIO_ACPI=y\nCONFIG_GUP_GET_PTE_LOW_HIGH=y\nCONFIG_HALTPOLL_CPUIDLE=y\nCONFIG_HDMI=y\nCONFIG_HIBERNATE_CALLBACKS=y\nCONFIG_HID_BATTERY_STRENGTH=y\nCONFIG_HID_GENERIC=y\nCONFIG_HID_HYPERV_MOUSE=y\n# CONFIG_HIGHMEM4G is not set\nCONFIG_HIGHMEM64G=y\nCONFIG_HOTPLUG_CPU=y\nCONFIG_HOTPLUG_PCI=y\nCONFIG_HOTPLUG_PCI_ACPI=y\n# CONFIG_HOTPLUG_PCI_ACPI_IBM is not set\n# CONFIG_HOTPLUG_PCI_COMPAQ is not set\n# CONFIG_HOTPLUG_PCI_CPCI is not set\n# CONFIG_HOTPLUG_PCI_IBM is not set\nCONFIG_HOTPLUG_PCI_PCIE=y\n# CONFIG_HOTPLUG_PCI_SHPC is not set\nCONFIG_HOTPLUG_SMT=y\nCONFIG_HPET=y\nCONFIG_HPET_MMAP=y\n# CONFIG_HP_ACCEL is not set\nCONFIG_HVC_DRIVER=y\nCONFIG_HVC_IRQ=y\nCONFIG_HVC_XEN=y\nCONFIG_HVC_XEN_FRONTEND=y\nCONFIG_HWMON=y\nCONFIG_HWMON_VID=y\nCONFIG_HW_RANDOM_VIRTIO=y\nCONFIG_HYPERV=y\nCONFIG_HYPERVISOR_GUEST=y\nCONFIG_HYPERV_BALLOON=y\nCONFIG_HYPERV_KEYBOARD=y\nCONFIG_HYPERV_NET=y\nCONFIG_HYPERV_STORAGE=y\n# CONFIG_HYPERV_TESTING is not set\nCONFIG_HYPERV_TIMER=y\nCONFIG_HYPERV_UTILS=y\nCONFIG_I2C=y\nCONFIG_I2C_ALGOBIT=y\n# CONFIG_I2C_AMD_MP2 is not set\nCONFIG_I2C_BOARDINFO=y\n# CONFIG_I2C_MULTI_INSTANTIATE is not set\n# CONFIG_IMA_SECURE_AND_OR_TRUSTED_BOOT is not set\nCONFIG_INPUT_MOUSE=y\nCONFIG_INPUT_MOUSEDEV=y\nCONFIG_INPUT_MOUSEDEV_PSAUX=y\nCONFIG_INPUT_MOUSEDEV_SCREEN_X=1024\nCONFIG_INPUT_MOUSEDEV_SCREEN_Y=768\nCONFIG_INPUT_XEN_KBDDEV_FRONTEND=y\nCONFIG_INTEL_GTT=y\nCONFIG_INTEL_IDLE=y\n# CONFIG_INTEL_IPS is not set\n# CONFIG_INTEL_MEI_HDCP is not set\n# CONFIG_INTEL_MENLOW is not set\nCONFIG_INTEL_PCH_THERMAL=y\n# CONFIG_INTEL_SCU_PLATFORM is not set\nCONFIG_INTEL_SOC_DTS_IOSF_CORE=y\nCONFIG_INTEL_SOC_DTS_THERMAL=y\nCONFIG_INTERVAL_TREE=y\nCONFIG_IOSF_MBI=y\n# CONFIG_IOSF_MBI_DEBUG is not set\nCONFIG_IRQ_BYPASS_MANAGER=y\nCONFIG_ISA=y\nCONFIG_ISAPNP=y\nCONFIG_ISA_BUS_API=y\n# CONFIG_ISCSI_IBFT is not set\nCONFIG_ISO9660_FS=y\n# CONFIG_JOLIET is not set\nCONFIG_KCMP=y\nCONFIG_KVM=y\nCONFIG_KVM_AMD=y\nCONFIG_KVM_ASYNC_PF=y\nCONFIG_KVM_GENERIC_DIRTYLOG_READ_PROTECT=y\nCONFIG_KVM_GUEST=y\nCONFIG_KVM_INTEL=y\nCONFIG_KVM_MMIO=y\nCONFIG_KVM_VFIO=y\nCONFIG_KVM_XFER_TO_GUEST_WORK=y\n# CONFIG_LANCE is not set\nCONFIG_LIBNVDIMM=y\nCONFIG_LOCK_SPIN_ON_OWNER=y\n# CONFIG_M686 is not set\n# CONFIG_MDA_CONSOLE is not set\nCONFIG_MEMORY_BALLOON=y\nCONFIG_MEMREGION=y\nCONFIG_MFD_CORE=y\nCONFIG_MFD_INTEL_LPSS=y\nCONFIG_MFD_INTEL_LPSS_ACPI=y\n# CONFIG_MFD_INTEL_PMC_BXT is not set\n# CONFIG_MIXCOMWD is not set\nCONFIG_MMC=y\nCONFIG_MMC_BLOCK=y\nCONFIG_MMC_CQHCI=y\nCONFIG_MMC_RICOH_MMC=y\nCONFIG_MMC_SDHCI=y\nCONFIG_MMC_SDHCI_IO_ACCESSORS=y\nCONFIG_MMC_SDHCI_PCI=y\n# CONFIG_MMC_SDHCI_PLTFM is not set\n# CONFIG_MMC_WBSD is not set\nCONFIG_MMU_NOTIFIER=y\n# CONFIG_MOUSE_BCM5974 is not set\n# CONFIG_MOUSE_CYAPA is not set\nCONFIG_MOUSE_PS2=y\nCONFIG_MOUSE_PS2_ALPS=y\n# CONFIG_MOUSE_PS2_BYD is not set\n# CONFIG_MOUSE_PS2_CYPRESS is not set\n# CONFIG_MOUSE_PS2_ELANTECH is not set\nCONFIG_MOUSE_PS2_LIFEBOOK=y\nCONFIG_MOUSE_PS2_LOGIPS2PP=y\nCONFIG_MOUSE_PS2_SMBUS=y\nCONFIG_MOUSE_PS2_SYNAPTICS=y\nCONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y\n# CONFIG_MOUSE_PS2_TOUCHKIT is not set\nCONFIG_MOUSE_PS2_TRACKPOINT=y\n# CONFIG_MOUSE_PS2_VMMOUSE is not set\n# CONFIG_MOUSE_SERIAL is not set\n# CONFIG_MOUSE_VSXXXAA is not set\nCONFIG_MPENTIUM4=y\nCONFIG_MUTEX_SPIN_ON_OWNER=y\nCONFIG_ND_BLK=y\nCONFIG_ND_BTT=y\nCONFIG_ND_CLAIM=y\nCONFIG_NEED_DMA_MAP_STATE=y\nCONFIG_NET_FAILOVER=y\nCONFIG_NET_FLOW_LIMIT=y\nCONFIG_NO_HZ=y\nCONFIG_NR_CPUS=4\nCONFIG_NR_CPUS_DEFAULT=8\nCONFIG_NR_CPUS_RANGE_BEGIN=2\nCONFIG_NR_CPUS_RANGE_END=8\nCONFIG_PADATA=y\nCONFIG_PAGE_POOL=y\nCONFIG_PAGE_REPORTING=y\nCONFIG_PAGE_TABLE_ISOLATION=y\nCONFIG_PARAVIRT=y\nCONFIG_PARAVIRT_CLOCK=y\n# CONFIG_PARAVIRT_DEBUG is not set\nCONFIG_PARAVIRT_SPINLOCKS=y\nCONFIG_PATA_AMD=y\nCONFIG_PATA_ATIIXP=y\nCONFIG_PATA_MPIIX=y\nCONFIG_PATA_OLDPIIX=y\nCONFIG_PATA_PLATFORM=y\nCONFIG_PATA_SC1200=y\nCONFIG_PATA_TIMINGS=y\nCONFIG_PATA_VIA=y\n# CONFIG_PCENGINES_APU2 is not set\nCONFIG_PCIEAER=y\nCONFIG_PCIEPORTBUS=y\nCONFIG_PCIE_PME=y\nCONFIG_PCI_MMCONFIG=y\nCONFIG_PCI_XEN=y\n# CONFIG_PCWATCHDOG is not set\nCONFIG_PGTABLE_LEVELS=3\nCONFIG_PHYS_ADDR_T_64BIT=y\nCONFIG_PINCTRL=y\nCONFIG_PINCTRL_BAYTRAIL=y\nCONFIG_PINCTRL_BROXTON=y\nCONFIG_PINCTRL_CANNONLAKE=y\nCONFIG_PINCTRL_CHERRYVIEW=y\nCONFIG_PINCTRL_DENVERTON=y\n# CONFIG_PINCTRL_EMMITSBURG is not set\nCONFIG_PINCTRL_GEMINILAKE=y\nCONFIG_PINCTRL_INTEL=y\n# CONFIG_PINCTRL_JASPERLAKE is not set\n# CONFIG_PINCTRL_LEWISBURG is not set\n# CONFIG_PINCTRL_LYNXPOINT is not set\nCONFIG_PINCTRL_SUNRISEPOINT=y\n# CONFIG_PINCTRL_TIGERLAKE is not set\nCONFIG_PM=y\n# CONFIG_PMIC_OPREGION is not set\nCONFIG_PM_CLK=y\nCONFIG_PM_SLEEP=y\nCONFIG_PM_SLEEP_SMP=y\nCONFIG_PNP=y\nCONFIG_PNPACPI=y\n# CONFIG_PNPBIOS is not set\nCONFIG_PNP_DEBUG_MESSAGES=y\nCONFIG_PREEMPT_NOTIFIERS=y\nCONFIG_PROC_EVENTS=y\nCONFIG_PVH=y\nCONFIG_QUEUED_RWLOCKS=y\nCONFIG_QUEUED_SPINLOCKS=y\nCONFIG_RAS=y\nCONFIG_RELAY=y\nCONFIG_RELOCATABLE=y\nCONFIG_RESET_ATTACK_MITIGATION=y\nCONFIG_RFS_ACCEL=y\nCONFIG_RPS=y\nCONFIG_RTC_I2C_AND_SPI=y\nCONFIG_RWSEM_SPIN_ON_OWNER=y\n# CONFIG_SAMSUNG_Q10 is not set\nCONFIG_SATA_AHCI=y\nCONFIG_SATA_VIA=y\nCONFIG_SCHED_INFO=y\nCONFIG_SCHED_SMT=y\n# CONFIG_SCSI_FDOMAIN_ISA is not set\nCONFIG_SCSI_VIRTIO=y\n# CONFIG_SENSORS_AMD_ENERGY is not set\nCONFIG_SENSORS_CORETEMP=y\nCONFIG_SENSORS_FAM15H_POWER=y\nCONFIG_SENSORS_I5500=y\nCONFIG_SENSORS_K10TEMP=y\nCONFIG_SENSORS_K8TEMP=y\nCONFIG_SENSORS_VIA_CPUTEMP=y\nCONFIG_SERIAL_8250_PNP=y\nCONFIG_SERIAL_MCTRL_GPIO=y\nCONFIG_SMP=y\n# CONFIG_SURFACE_3_POWER_OPREGION is not set\n# CONFIG_SURFACE_PRO3_BUTTON is not set\nCONFIG_SWIOTLB=y\nCONFIG_SWIOTLB_XEN=y\nCONFIG_SYNC_FILE=y\n# CONFIG_SYSTEM76_ACPI is not set\nCONFIG_SYS_HYPERVISOR=y\nCONFIG_TASKSTATS=y\nCONFIG_TASK_DELAY_ACCT=y\nCONFIG_THERMAL_GOV_USER_SPACE=y\nCONFIG_THERMAL_HWMON=y\nCONFIG_THERMAL_WRITABLE_TRIPS=y\n# CONFIG_TOSHIBA_BT_RFKILL is not set\nCONFIG_TREE_RCU=y\nCONFIG_TREE_SRCU=y\n# CONFIG_UCLAMP_TASK is not set\nCONFIG_UCS2_STRING=y\nCONFIG_USB_STORAGE=y\nCONFIG_USER_RETURN_NOTIFIER=y\nCONFIG_VHOST=y\nCONFIG_VHOST_IOTLB=y\nCONFIG_VHOST_NET=y\nCONFIG_VIRTIO=y\nCONFIG_VIRTIO_BALLOON=y\nCONFIG_VIRTIO_BLK=y\nCONFIG_VIRTIO_CONSOLE=y\nCONFIG_VIRTIO_DMA_SHARED_BUFFER=y\nCONFIG_VIRTIO_INPUT=y\nCONFIG_VIRTIO_MMIO=y\nCONFIG_VIRTIO_NET=y\nCONFIG_VIRTIO_PCI=y\nCONFIG_VIRTIO_PCI_LEGACY=y\n# CONFIG_VIRTIO_PMEM is not set\nCONFIG_VIRTUALIZATION=y\nCONFIG_VMAP_PFN=y\nCONFIG_VT_CONSOLE_SLEEP=y\nCONFIG_WATCHDOG_CORE=y\n# CONFIG_WDT is not set\nCONFIG_X86_32_SMP=y\nCONFIG_X86_ACPI_CPUFREQ=y\n# CONFIG_X86_ACPI_CPUFREQ_CPB is not set\nCONFIG_X86_AMD_FREQ_SENSITIVITY=y\n# CONFIG_X86_AMD_PLATFORM_DEVICE is not set\n# CONFIG_X86_BIGSMP is not set\nCONFIG_X86_CPUID=y\n# CONFIG_X86_E_POWERSAVER is not set\nCONFIG_X86_HV_CALLBACK_VECTOR=y\nCONFIG_X86_INTEL_LPSS=y\nCONFIG_X86_INTEL_PSTATE=y\nCONFIG_X86_INTERNODE_CACHE_SHIFT=7\nCONFIG_X86_L1_CACHE_SHIFT=7\n# CONFIG_X86_LONGHAUL is not set\nCONFIG_X86_NEED_RELOCS=y\nCONFIG_X86_PAE=y\n# CONFIG_X86_PCC_CPUFREQ is not set\nCONFIG_X86_PKG_TEMP_THERMAL=y\n# CONFIG_X86_PMEM_LEGACY is not set\nCONFIG_X86_PM_TIMER=y\n# CONFIG_X86_POWERNOW_K8 is not set\nCONFIG_XEN=y\nCONFIG_XENFS=y\nCONFIG_XEN_ACPI=y\nCONFIG_XEN_AUTO_XLATE=y\n# CONFIG_XEN_BACKEND is not set\nCONFIG_XEN_BALLOON=y\nCONFIG_XEN_BLKDEV_FRONTEND=y\nCONFIG_XEN_COMPAT_XENFS=y\nCONFIG_XEN_DEBUG_FS=y\nCONFIG_XEN_DEV_EVTCHN=y\nCONFIG_XEN_FBDEV_FRONTEND=y\nCONFIG_XEN_GNTDEV=y\nCONFIG_XEN_GRANT_DEV_ALLOC=y\nCONFIG_XEN_NETDEV_FRONTEND=y\nCONFIG_XEN_PCIDEV_FRONTEND=y\nCONFIG_XEN_PRIVCMD=y\nCONFIG_XEN_PVH=y\nCONFIG_XEN_PVHVM=y\nCONFIG_XEN_PVHVM_SMP=y\nCONFIG_XEN_SAVE_RESTORE=y\nCONFIG_XEN_SCSI_FRONTEND=y\nCONFIG_XEN_SYS_HYPERVISOR=y\nCONFIG_XEN_WDT=y\nCONFIG_XEN_XENBUS_FRONTEND=y\nCONFIG_XPS=y\nCONFIG_ZLIB_DEFLATE=y\n"
  },
  {
    "path": "target/linux/x86/generic/config-5.15",
    "content": "# CONFIG_3C515 is not set\nCONFIG_ACPI=y\nCONFIG_ACPI_AC=y\nCONFIG_ACPI_BATTERY=y\n# CONFIG_ACPI_BGRT is not set\nCONFIG_ACPI_BUTTON=y\n# CONFIG_ACPI_CMPC is not set\nCONFIG_ACPI_CONTAINER=y\nCONFIG_ACPI_CPU_FREQ_PSS=y\n# CONFIG_ACPI_DEBUG is not set\n# CONFIG_ACPI_DEBUGGER is not set\n# CONFIG_ACPI_DOCK is not set\n# CONFIG_ACPI_DPTF is not set\n# CONFIG_ACPI_EC_DEBUGFS is not set\n# CONFIG_ACPI_FAN is not set\nCONFIG_ACPI_HOTPLUG_CPU=y\nCONFIG_ACPI_HOTPLUG_IOAPIC=y\n# CONFIG_ACPI_I2C_OPREGION is not set\nCONFIG_ACPI_LEGACY_TABLES_LOOKUP=y\n# CONFIG_ACPI_PCI_SLOT is not set\nCONFIG_ACPI_PROCESSOR=y\n# CONFIG_ACPI_PROCESSOR_AGGREGATOR is not set\nCONFIG_ACPI_PROCESSOR_CSTATE=y\nCONFIG_ACPI_PROCESSOR_IDLE=y\nCONFIG_ACPI_REV_OVERRIDE_POSSIBLE=y\n# CONFIG_ACPI_SBS is not set\nCONFIG_ACPI_SPCR_TABLE=y\nCONFIG_ACPI_SYSTEM_POWER_STATES_SUPPORT=y\nCONFIG_ACPI_TAD=y\nCONFIG_ACPI_THERMAL=y\nCONFIG_ACPI_VIDEO=y\n# CONFIG_ACPI_WMI is not set\n# CONFIG_ADV_SWBUTTON is not set\nCONFIG_AGP=y\n# CONFIG_AGP_ALI is not set\n# CONFIG_AGP_AMD is not set\n# CONFIG_AGP_AMD64 is not set\n# CONFIG_AGP_ATI is not set\n# CONFIG_AGP_EFFICEON is not set\nCONFIG_AGP_INTEL=y\n# CONFIG_AGP_NVIDIA is not set\n# CONFIG_AGP_SIS is not set\n# CONFIG_AGP_SWORKS is not set\n# CONFIG_AGP_VIA is not set\n# CONFIG_AMD_PMC is not set\n# CONFIG_APM is not set\nCONFIG_ARCH_CPUIDLE_HALTPOLL=y\nCONFIG_ARCH_DMA_ADDR_T_64BIT=y\nCONFIG_ARCH_MIGHT_HAVE_ACPI_PDC=y\nCONFIG_BACKLIGHT_CLASS_DEVICE=y\nCONFIG_BALLOON_COMPACTION=y\nCONFIG_BLK_DEV_SR=y\nCONFIG_BLK_MQ_VIRTIO=y\nCONFIG_BLK_PM=y\n# CONFIG_BOOTPARAM_HOTPLUG_CPU0 is not set\nCONFIG_BTT=y\nCONFIG_CDROM=y\nCONFIG_CONNECTOR=y\nCONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y\nCONFIG_CPU_FREQ_GOV_SCHEDUTIL=y\n# CONFIG_CPU_IDLE_GOV_HALTPOLL is not set\nCONFIG_CPU_IDLE_GOV_MENU=y\nCONFIG_CPU_RMAP=y\n# CONFIG_CS89x0_ISA is not set\n# CONFIG_DEBUG_HOTPLUG_CPU0 is not set\nCONFIG_DMA_ACPI=y\nCONFIG_DMA_SHARED_BUFFER=y\nCONFIG_DRM=y\nCONFIG_DRM_BOCHS=y\nCONFIG_DRM_BRIDGE=y\nCONFIG_DRM_FBDEV_EMULATION=y\nCONFIG_DRM_FBDEV_OVERALLOC=100\nCONFIG_DRM_GEM_SHMEM_HELPER=y\n# CONFIG_DRM_HYPERV is not set\nCONFIG_DRM_I915=y\nCONFIG_DRM_I915_CAPTURE_ERROR=y\nCONFIG_DRM_I915_COMPRESS_ERROR=y\n# CONFIG_DRM_I915_DEBUG is not set\n# CONFIG_DRM_I915_DEBUG_GUC is not set\n# CONFIG_DRM_I915_DEBUG_MMIO is not set\n# CONFIG_DRM_I915_DEBUG_RUNTIME_PM is not set\n# CONFIG_DRM_I915_DEBUG_VBLANK_EVADE is not set\nCONFIG_DRM_I915_FENCE_TIMEOUT=10000\nCONFIG_DRM_I915_FORCE_PROBE=\"\"\nCONFIG_DRM_I915_HEARTBEAT_INTERVAL=2500\n# CONFIG_DRM_I915_LOW_LEVEL_TRACEPOINTS is not set\nCONFIG_DRM_I915_MAX_REQUEST_BUSYWAIT=8000\nCONFIG_DRM_I915_PREEMPT_TIMEOUT=640\nCONFIG_DRM_I915_REQUEST_TIMEOUT=20000\n# CONFIG_DRM_I915_SELFTEST is not set\nCONFIG_DRM_I915_STOP_TIMEOUT=100\n# CONFIG_DRM_I915_SW_FENCE_CHECK_DAG is not set\n# CONFIG_DRM_I915_SW_FENCE_DEBUG_OBJECTS is not set\nCONFIG_DRM_I915_TIMESLICE_DURATION=1\nCONFIG_DRM_I915_USERFAULT_AUTOSUSPEND=250\nCONFIG_DRM_I915_USERPTR=y\n# CONFIG_DRM_I915_WERROR is not set\nCONFIG_DRM_KMS_HELPER=y\nCONFIG_DRM_MIPI_DSI=y\nCONFIG_DRM_PANEL=y\nCONFIG_DRM_PANEL_BRIDGE=y\nCONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y\nCONFIG_DRM_TTM=y\nCONFIG_DRM_TTM_HELPER=y\nCONFIG_DRM_VIRTIO_GPU=y\nCONFIG_DRM_VRAM_HELPER=y\n# CONFIG_DRM_XEN_FRONTEND is not set\nCONFIG_EFI=y\nCONFIG_EFIVAR_FS=m\n# CONFIG_EFI_BOOTLOADER_CONTROL is not set\n# CONFIG_EFI_CAPSULE_LOADER is not set\n# CONFIG_EFI_CAPSULE_QUIRK_QUARK_CSH is not set\n# CONFIG_EFI_CUSTOM_SSDT_OVERLAYS is not set\n# CONFIG_EFI_DISABLE_PCI_DMA is not set\nCONFIG_EFI_EARLYCON=y\nCONFIG_EFI_ESRT=y\n# CONFIG_EFI_FAKE_MEMMAP is not set\nCONFIG_EFI_GENERIC_STUB_INITRD_CMDLINE_LOADER=y\n# CONFIG_EFI_PGT_DUMP is not set\n# CONFIG_EFI_RCI2_TABLE is not set\nCONFIG_EFI_RUNTIME_MAP=y\nCONFIG_EFI_RUNTIME_WRAPPERS=y\nCONFIG_EFI_STUB=y\n# CONFIG_EFI_TEST is not set\n# CONFIG_EFI_VARS is not set\n# CONFIG_EL3 is not set\nCONFIG_FAILOVER=y\nCONFIG_FB=y\nCONFIG_FB_CFB_COPYAREA=y\nCONFIG_FB_CFB_FILLRECT=y\nCONFIG_FB_CFB_IMAGEBLIT=y\nCONFIG_FB_CMDLINE=y\nCONFIG_FB_DEFERRED_IO=y\nCONFIG_FB_EFI=y\nCONFIG_FB_HYPERV=y\n# CONFIG_FB_I810 is not set\nCONFIG_FB_SIMPLE=y\nCONFIG_FB_SYS_COPYAREA=y\nCONFIG_FB_SYS_FILLRECT=y\nCONFIG_FB_SYS_FOPS=y\nCONFIG_FB_SYS_IMAGEBLIT=y\n# CONFIG_FB_VESA is not set\nCONFIG_FONT_8x16=y\nCONFIG_FONT_8x8=y\nCONFIG_FONT_SUPPORT=y\nCONFIG_FRAMEBUFFER_CONSOLE=y\nCONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y\n# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set\nCONFIG_FREEZER=y\nCONFIG_FW_CACHE=y\nCONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y\nCONFIG_GENERIC_IRQ_MIGRATION=y\nCONFIG_GENERIC_PENDING_IRQ=y\nCONFIG_GENERIC_PINCONF=y\nCONFIG_GPIOLIB=y\nCONFIG_GPIOLIB_IRQCHIP=y\nCONFIG_GPIO_ACPI=y\nCONFIG_GPIO_CDEV=y\nCONFIG_GUP_GET_PTE_LOW_HIGH=y\nCONFIG_HALTPOLL_CPUIDLE=y\nCONFIG_HDMI=y\nCONFIG_HIBERNATE_CALLBACKS=y\nCONFIG_HID_BATTERY_STRENGTH=y\nCONFIG_HID_GENERIC=y\nCONFIG_HID_HYPERV_MOUSE=y\n# CONFIG_HIGHMEM4G is not set\nCONFIG_HIGHMEM64G=y\nCONFIG_HOTPLUG_CPU=y\nCONFIG_HOTPLUG_PCI=y\nCONFIG_HOTPLUG_PCI_ACPI=y\n# CONFIG_HOTPLUG_PCI_ACPI_IBM is not set\n# CONFIG_HOTPLUG_PCI_COMPAQ is not set\n# CONFIG_HOTPLUG_PCI_CPCI is not set\n# CONFIG_HOTPLUG_PCI_IBM is not set\nCONFIG_HOTPLUG_PCI_PCIE=y\n# CONFIG_HOTPLUG_PCI_SHPC is not set\nCONFIG_HOTPLUG_SMT=y\nCONFIG_HPET=y\nCONFIG_HPET_MMAP=y\n# CONFIG_HP_ACCEL is not set\nCONFIG_HVC_DRIVER=y\nCONFIG_HVC_IRQ=y\nCONFIG_HVC_XEN=y\nCONFIG_HVC_XEN_FRONTEND=y\nCONFIG_HWMON=y\nCONFIG_HWMON_VID=y\nCONFIG_HW_RANDOM_VIRTIO=y\nCONFIG_HYPERV=y\nCONFIG_HYPERVISOR_GUEST=y\nCONFIG_HYPERV_BALLOON=y\nCONFIG_HYPERV_KEYBOARD=y\nCONFIG_HYPERV_NET=y\nCONFIG_HYPERV_STORAGE=y\n# CONFIG_HYPERV_TESTING is not set\nCONFIG_HYPERV_TIMER=y\nCONFIG_HYPERV_UTILS=y\nCONFIG_I2C=y\nCONFIG_I2C_ALGOBIT=y\n# CONFIG_I2C_AMD_MP2 is not set\nCONFIG_I2C_BOARDINFO=y\n# CONFIG_I2C_HID_ACPI is not set\n# CONFIG_I2C_MULTI_INSTANTIATE is not set\n# CONFIG_I8K is not set\n# CONFIG_IMA_SECURE_AND_OR_TRUSTED_BOOT is not set\nCONFIG_INPUT_MOUSE=y\nCONFIG_INPUT_MOUSEDEV=y\nCONFIG_INPUT_MOUSEDEV_PSAUX=y\nCONFIG_INPUT_MOUSEDEV_SCREEN_X=1024\nCONFIG_INPUT_MOUSEDEV_SCREEN_Y=768\nCONFIG_INPUT_XEN_KBDDEV_FRONTEND=y\nCONFIG_INTEL_GTT=y\nCONFIG_INTEL_IDLE=y\n# CONFIG_INTEL_IPS is not set\n# CONFIG_INTEL_MEI_HDCP is not set\n# CONFIG_INTEL_MENLOW is not set\nCONFIG_INTEL_PCH_THERMAL=y\n# CONFIG_INTEL_SAR_INT1092 is not set\n# CONFIG_INTEL_SCU_PLATFORM is not set\nCONFIG_INTEL_SOC_DTS_IOSF_CORE=y\nCONFIG_INTEL_SOC_DTS_THERMAL=y\nCONFIG_INTERVAL_TREE=y\nCONFIG_IOSF_MBI=y\n# CONFIG_IOSF_MBI_DEBUG is not set\nCONFIG_IRQ_BYPASS_MANAGER=y\nCONFIG_ISA=y\nCONFIG_ISAPNP=y\nCONFIG_ISA_BUS_API=y\n# CONFIG_ISCSI_IBFT is not set\nCONFIG_ISO9660_FS=y\n# CONFIG_JOLIET is not set\nCONFIG_KCMP=y\nCONFIG_KVM=y\nCONFIG_KVM_AMD=y\nCONFIG_KVM_ASYNC_PF=y\nCONFIG_KVM_GENERIC_DIRTYLOG_READ_PROTECT=y\nCONFIG_KVM_GUEST=y\nCONFIG_KVM_INTEL=y\nCONFIG_KVM_MMIO=y\nCONFIG_KVM_VFIO=y\n# CONFIG_KVM_XEN is not set\nCONFIG_KVM_XFER_TO_GUEST_WORK=y\n# CONFIG_LANCE is not set\nCONFIG_LIBNVDIMM=y\nCONFIG_LOCK_SPIN_ON_OWNER=y\n# CONFIG_M686 is not set\n# CONFIG_MDA_CONSOLE is not set\nCONFIG_MEMORY_BALLOON=y\nCONFIG_MEMREGION=y\nCONFIG_MFD_CORE=y\nCONFIG_MFD_INTEL_LPSS=y\nCONFIG_MFD_INTEL_LPSS_ACPI=y\n# CONFIG_MFD_INTEL_PMC_BXT is not set\n# CONFIG_MIXCOMWD is not set\nCONFIG_MMC=y\nCONFIG_MMC_BLOCK=y\nCONFIG_MMC_CQHCI=y\nCONFIG_MMC_RICOH_MMC=y\nCONFIG_MMC_SDHCI=y\nCONFIG_MMC_SDHCI_IO_ACCESSORS=y\nCONFIG_MMC_SDHCI_PCI=y\n# CONFIG_MMC_SDHCI_PLTFM is not set\n# CONFIG_MMC_WBSD is not set\nCONFIG_MMU_NOTIFIER=y\n# CONFIG_MOUSE_BCM5974 is not set\n# CONFIG_MOUSE_CYAPA is not set\nCONFIG_MOUSE_PS2=y\nCONFIG_MOUSE_PS2_ALPS=y\n# CONFIG_MOUSE_PS2_BYD is not set\n# CONFIG_MOUSE_PS2_CYPRESS is not set\n# CONFIG_MOUSE_PS2_ELANTECH is not set\nCONFIG_MOUSE_PS2_LIFEBOOK=y\nCONFIG_MOUSE_PS2_LOGIPS2PP=y\nCONFIG_MOUSE_PS2_SMBUS=y\nCONFIG_MOUSE_PS2_SYNAPTICS=y\nCONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y\n# CONFIG_MOUSE_PS2_TOUCHKIT is not set\nCONFIG_MOUSE_PS2_TRACKPOINT=y\n# CONFIG_MOUSE_PS2_VMMOUSE is not set\n# CONFIG_MOUSE_SERIAL is not set\n# CONFIG_MOUSE_VSXXXAA is not set\nCONFIG_MPENTIUM4=y\nCONFIG_MUTEX_SPIN_ON_OWNER=y\nCONFIG_ND_BLK=y\nCONFIG_ND_BTT=y\nCONFIG_ND_CLAIM=y\nCONFIG_NEED_DMA_MAP_STATE=y\nCONFIG_NET_FAILOVER=y\nCONFIG_NET_FLOW_LIMIT=y\nCONFIG_NO_HZ=y\nCONFIG_NR_CPUS=4\nCONFIG_NR_CPUS_DEFAULT=8\nCONFIG_NR_CPUS_RANGE_BEGIN=2\nCONFIG_NR_CPUS_RANGE_END=8\nCONFIG_PADATA=y\nCONFIG_PAGE_POOL=y\nCONFIG_PAGE_REPORTING=y\nCONFIG_PAGE_TABLE_ISOLATION=y\nCONFIG_PARAVIRT=y\nCONFIG_PARAVIRT_CLOCK=y\n# CONFIG_PARAVIRT_DEBUG is not set\nCONFIG_PARAVIRT_SPINLOCKS=y\nCONFIG_PATA_AMD=y\nCONFIG_PATA_ATIIXP=y\nCONFIG_PATA_MPIIX=y\nCONFIG_PATA_OLDPIIX=y\nCONFIG_PATA_PLATFORM=y\nCONFIG_PATA_SC1200=y\nCONFIG_PATA_TIMINGS=y\nCONFIG_PATA_VIA=y\n# CONFIG_PCENGINES_APU2 is not set\nCONFIG_PCIEAER=y\nCONFIG_PCIEPORTBUS=y\nCONFIG_PCIE_PME=y\nCONFIG_PCI_MMCONFIG=y\nCONFIG_PCI_XEN=y\n# CONFIG_PCWATCHDOG is not set\nCONFIG_PGTABLE_LEVELS=3\nCONFIG_PHYS_ADDR_T_64BIT=y\nCONFIG_PINCTRL=y\n# CONFIG_PINCTRL_ALDERLAKE is not set\nCONFIG_PINCTRL_BAYTRAIL=y\nCONFIG_PINCTRL_BROXTON=y\nCONFIG_PINCTRL_CANNONLAKE=y\nCONFIG_PINCTRL_CHERRYVIEW=y\nCONFIG_PINCTRL_DENVERTON=y\n# CONFIG_PINCTRL_ELKHARTLAKE is not set\n# CONFIG_PINCTRL_EMMITSBURG is not set\nCONFIG_PINCTRL_GEMINILAKE=y\nCONFIG_PINCTRL_INTEL=y\n# CONFIG_PINCTRL_JASPERLAKE is not set\n# CONFIG_PINCTRL_LAKEFIELD is not set\n# CONFIG_PINCTRL_LEWISBURG is not set\n# CONFIG_PINCTRL_LYNXPOINT is not set\nCONFIG_PINCTRL_SUNRISEPOINT=y\n# CONFIG_PINCTRL_TIGERLAKE is not set\nCONFIG_PM=y\n# CONFIG_PMIC_OPREGION is not set\nCONFIG_PM_CLK=y\nCONFIG_PM_SLEEP=y\nCONFIG_PM_SLEEP_SMP=y\nCONFIG_PNP=y\nCONFIG_PNPACPI=y\n# CONFIG_PNPBIOS is not set\nCONFIG_PNP_DEBUG_MESSAGES=y\nCONFIG_PREEMPT_NOTIFIERS=y\nCONFIG_PROC_EVENTS=y\nCONFIG_PVH=y\nCONFIG_QUEUED_RWLOCKS=y\nCONFIG_QUEUED_SPINLOCKS=y\nCONFIG_RAS=y\nCONFIG_RELAY=y\nCONFIG_RELOCATABLE=y\nCONFIG_RESET_ATTACK_MITIGATION=y\nCONFIG_RFS_ACCEL=y\nCONFIG_RPS=y\nCONFIG_RTC_I2C_AND_SPI=y\nCONFIG_RWSEM_SPIN_ON_OWNER=y\n# CONFIG_SAMSUNG_Q10 is not set\nCONFIG_SATA_AHCI=y\nCONFIG_SATA_VIA=y\n# CONFIG_SCHED_CORE is not set\nCONFIG_SCHED_INFO=y\nCONFIG_SCHED_SMT=y\n# CONFIG_SCSI_FDOMAIN_ISA is not set\nCONFIG_SCSI_VIRTIO=y\nCONFIG_SENSORS_CORETEMP=y\nCONFIG_SENSORS_FAM15H_POWER=y\nCONFIG_SENSORS_I5500=y\nCONFIG_SENSORS_K10TEMP=y\nCONFIG_SENSORS_K8TEMP=y\nCONFIG_SENSORS_VIA_CPUTEMP=y\nCONFIG_SERIAL_8250_PNP=y\nCONFIG_SERIAL_MCTRL_GPIO=y\nCONFIG_SMP=y\nCONFIG_SOCK_RX_QUEUE_MAPPING=y\n# CONFIG_SURFACE_PLATFORMS is not set\nCONFIG_SWIOTLB=y\nCONFIG_SYNC_FILE=y\n# CONFIG_SYSTEM76_ACPI is not set\nCONFIG_SYS_HYPERVISOR=y\nCONFIG_TASKSTATS=y\nCONFIG_TASK_DELAY_ACCT=y\nCONFIG_THERMAL_GOV_USER_SPACE=y\nCONFIG_THERMAL_HWMON=y\nCONFIG_THERMAL_WRITABLE_TRIPS=y\n# CONFIG_TOSHIBA_BT_RFKILL is not set\nCONFIG_TREE_RCU=y\nCONFIG_TREE_SRCU=y\n# CONFIG_UCLAMP_TASK is not set\nCONFIG_UCS2_STRING=y\nCONFIG_USB_STORAGE=y\nCONFIG_USER_RETURN_NOTIFIER=y\nCONFIG_VHOST=y\nCONFIG_VHOST_IOTLB=y\nCONFIG_VHOST_NET=y\nCONFIG_VIRTIO=y\nCONFIG_VIRTIO_BALLOON=y\nCONFIG_VIRTIO_BLK=y\nCONFIG_VIRTIO_CONSOLE=y\nCONFIG_VIRTIO_DMA_SHARED_BUFFER=y\nCONFIG_VIRTIO_INPUT=y\nCONFIG_VIRTIO_MMIO=y\nCONFIG_VIRTIO_NET=y\nCONFIG_VIRTIO_PCI=y\nCONFIG_VIRTIO_PCI_LEGACY=y\nCONFIG_VIRTIO_PCI_LIB=y\n# CONFIG_VIRTIO_PMEM is not set\nCONFIG_VIRTUALIZATION=y\nCONFIG_VMAP_PFN=y\nCONFIG_VT_CONSOLE_SLEEP=y\nCONFIG_WATCHDOG_CORE=y\n# CONFIG_WDT is not set\n# CONFIG_WIRELESS_HOTKEY is not set\nCONFIG_X86_32_SMP=y\nCONFIG_X86_ACPI_CPUFREQ=y\n# CONFIG_X86_ACPI_CPUFREQ_CPB is not set\nCONFIG_X86_AMD_FREQ_SENSITIVITY=y\n# CONFIG_X86_AMD_PLATFORM_DEVICE is not set\n# CONFIG_X86_BIGSMP is not set\nCONFIG_X86_CPUID=y\n# CONFIG_X86_E_POWERSAVER is not set\nCONFIG_X86_HV_CALLBACK_VECTOR=y\nCONFIG_X86_INTEL_LPSS=y\nCONFIG_X86_INTEL_PSTATE=y\nCONFIG_X86_INTERNODE_CACHE_SHIFT=7\nCONFIG_X86_L1_CACHE_SHIFT=7\n# CONFIG_X86_LONGHAUL is not set\nCONFIG_X86_NEED_RELOCS=y\nCONFIG_X86_PAE=y\n# CONFIG_X86_PCC_CPUFREQ is not set\nCONFIG_X86_PKG_TEMP_THERMAL=y\n# CONFIG_X86_PMEM_LEGACY is not set\nCONFIG_X86_PM_TIMER=y\n# CONFIG_X86_POWERNOW_K8 is not set\nCONFIG_XEN=y\nCONFIG_XENFS=y\nCONFIG_XEN_ACPI=y\nCONFIG_XEN_AUTO_XLATE=y\n# CONFIG_XEN_BACKEND is not set\nCONFIG_XEN_BALLOON=y\nCONFIG_XEN_BLKDEV_FRONTEND=y\nCONFIG_XEN_COMPAT_XENFS=y\nCONFIG_XEN_DEBUG_FS=y\nCONFIG_XEN_DEV_EVTCHN=y\nCONFIG_XEN_FBDEV_FRONTEND=y\nCONFIG_XEN_GNTDEV=y\nCONFIG_XEN_GRANT_DEV_ALLOC=y\nCONFIG_XEN_NETDEV_FRONTEND=y\nCONFIG_XEN_PRIVCMD=y\nCONFIG_XEN_PVH=y\nCONFIG_XEN_PVHVM=y\nCONFIG_XEN_PVHVM_GUEST=y\nCONFIG_XEN_PVHVM_SMP=y\nCONFIG_XEN_SAVE_RESTORE=y\nCONFIG_XEN_SCSI_FRONTEND=y\nCONFIG_XEN_SYS_HYPERVISOR=y\nCONFIG_XEN_WDT=y\nCONFIG_XEN_XENBUS_FRONTEND=y\nCONFIG_XPS=y\nCONFIG_ZLIB_DEFLATE=y\n"
  },
  {
    "path": "target/linux/x86/generic/target.mk",
    "content": "BOARDNAME:=Generic\nCPU_TYPE :=pentium4\nFEATURES += audio pci pcie usb\n\ndefine Target/Description\n\tBuild firmware images for modern x86 based boards with CPUs\n\tsupporting at least the Intel Pentium 4 instruction set with\n\tMMX, SSE and SSE2.\nendef\n\n"
  },
  {
    "path": "target/linux/x86/geode/config-5.10",
    "content": "# CONFIG_3C515 is not set\nCONFIG_8139CP=y\nCONFIG_8139TOO=y\nCONFIG_8139TOO_8129=y\nCONFIG_8139TOO_PIO=y\n# CONFIG_8139TOO_TUNE_TWISTER is not set\n# CONFIG_8139_OLD_RX_RESET is not set\nCONFIG_ACPI=y\nCONFIG_ACPI_AC=y\n# CONFIG_ACPI_BATTERY is not set\n# CONFIG_ACPI_CMPC is not set\n# CONFIG_ACPI_CONTAINER is not set\nCONFIG_ACPI_CPU_FREQ_PSS=y\n# CONFIG_ACPI_DEBUG is not set\n# CONFIG_ACPI_DEBUGGER is not set\n# CONFIG_ACPI_DOCK is not set\n# CONFIG_ACPI_DPTF is not set\n# CONFIG_ACPI_EC_DEBUGFS is not set\nCONFIG_ACPI_FAN=y\nCONFIG_ACPI_HOTPLUG_IOAPIC=y\nCONFIG_ACPI_I2C_OPREGION=y\nCONFIG_ACPI_LEGACY_TABLES_LOOKUP=y\n# CONFIG_ACPI_PCI_SLOT is not set\nCONFIG_ACPI_PROCESSOR=y\n# CONFIG_ACPI_PROCESSOR_AGGREGATOR is not set\nCONFIG_ACPI_PROCESSOR_CSTATE=y\nCONFIG_ACPI_PROCESSOR_IDLE=y\nCONFIG_ACPI_REV_OVERRIDE_POSSIBLE=y\n# CONFIG_ACPI_SBS is not set\nCONFIG_ACPI_SPCR_TABLE=y\nCONFIG_ACPI_SYSTEM_POWER_STATES_SUPPORT=y\nCONFIG_ACPI_THERMAL=y\n# CONFIG_ACPI_TINY_POWER_BUTTON is not set\n# CONFIG_ACPI_WMI is not set\nCONFIG_ALIX=y\nCONFIG_ARCH_MIGHT_HAVE_ACPI_PDC=y\n# CONFIG_ATA_PIIX is not set\nCONFIG_CS5535_CLOCK_EVENT_SRC=y\nCONFIG_CS5535_MFGPT=y\nCONFIG_CS5535_MFGPT_DEFAULT_IRQ=7\nCONFIG_DMA_ACPI=y\n# CONFIG_EL3 is not set\nCONFIG_GEODE_WDT=y\nCONFIG_GEOS=y\nCONFIG_GPIOLIB=y\nCONFIG_GPIO_ACPI=y\nCONFIG_GPIO_CS5535=y\n# CONFIG_HPET is not set\n# CONFIG_HP_ACCEL is not set\nCONFIG_HWMON=y\nCONFIG_I2C=y\nCONFIG_I2C_ALGOBIT=y\nCONFIG_I2C_ALGOPCA=y\nCONFIG_I2C_ALGOPCF=y\n# CONFIG_I2C_AMD_MP2 is not set\nCONFIG_I2C_BOARDINFO=y\n# CONFIG_I2C_MULTI_INSTANTIATE is not set\n# CONFIG_INTEL_IPS is not set\n# CONFIG_INTEL_MENLOW is not set\n# CONFIG_INTEL_SCU_PLATFORM is not set\n# CONFIG_INTEL_SOC_DTS_THERMAL is not set\nCONFIG_IOSF_MBI=y\n# CONFIG_IOSF_MBI_DEBUG is not set\nCONFIG_ISA=y\n# CONFIG_ISAPNP is not set\nCONFIG_ISA_BUS_API=y\n# CONFIG_ISCSI_IBFT is not set\n# CONFIG_LANCE is not set\nCONFIG_LEDS_GPIO=y\n# CONFIG_M686 is not set\n# CONFIG_MDA_CONSOLE is not set\nCONFIG_MFD_CORE=y\nCONFIG_MFD_CS5535=y\n# CONFIG_MFD_INTEL_LPSS_ACPI is not set\n# CONFIG_MFD_INTEL_PMC_BXT is not set\nCONFIG_MGEODEGX1=y\n# CONFIG_MIXCOMWD is not set\nCONFIG_NATSEMI=y\nCONFIG_NET5501=y\nCONFIG_NSC_GPIO=y\nCONFIG_PATA_CS5520=y\nCONFIG_PATA_CS5530=y\nCONFIG_PATA_CS5535=y\nCONFIG_PATA_CS5536=y\nCONFIG_PATA_SC1200=y\nCONFIG_PC8736x_GPIO=y\n# CONFIG_PCENGINES_APU2 is not set\nCONFIG_PCI_MMCONFIG=y\n# CONFIG_PCWATCHDOG is not set\nCONFIG_PINCTRL=y\n# CONFIG_PINCTRL_BAYTRAIL is not set\n# CONFIG_PINCTRL_BROXTON is not set\n# CONFIG_PINCTRL_CANNONLAKE is not set\n# CONFIG_PINCTRL_CHERRYVIEW is not set\n# CONFIG_PINCTRL_DENVERTON is not set\n# CONFIG_PINCTRL_EMMITSBURG is not set\n# CONFIG_PINCTRL_GEMINILAKE is not set\n# CONFIG_PINCTRL_JASPERLAKE is not set\n# CONFIG_PINCTRL_LEWISBURG is not set\n# CONFIG_PINCTRL_LYNXPOINT is not set\n# CONFIG_PINCTRL_SUNRISEPOINT is not set\n# CONFIG_PINCTRL_TIGERLAKE is not set\n# CONFIG_PMIC_OPREGION is not set\nCONFIG_PNP=y\nCONFIG_PNPACPI=y\n# CONFIG_PNPBIOS is not set\nCONFIG_PNP_DEBUG_MESSAGES=y\nCONFIG_RTC_I2C_AND_SPI=y\n# CONFIG_SAMSUNG_Q10 is not set\nCONFIG_SC1200_WDT=y\n# CONFIG_SCSI_FDOMAIN_ISA is not set\nCONFIG_SCx200_ACB=y\nCONFIG_SCx200_WDT=y\n# CONFIG_SENSORS_AMD_ENERGY is not set\nCONFIG_SENSORS_LM90=y\nCONFIG_SERIAL_8250_PNP=y\nCONFIG_SERIAL_MCTRL_GPIO=y\n# CONFIG_SURFACE_3_POWER_OPREGION is not set\n# CONFIG_SURFACE_PRO3_BUTTON is not set\n# CONFIG_SYSTEM76_ACPI is not set\n# CONFIG_TOSHIBA_BT_RFKILL is not set\n# CONFIG_USB_UHCI_HCD is not set\nCONFIG_VIA_RHINE=y\nCONFIG_VIA_RHINE_MMIO=y\n# CONFIG_WDT is not set\n# CONFIG_X86_ACPI_CPUFREQ is not set\nCONFIG_X86_ALIGNMENT_16=y\n# CONFIG_X86_AMD_PLATFORM_DEVICE is not set\nCONFIG_X86_CPUID=y\n# CONFIG_X86_E_POWERSAVER is not set\nCONFIG_X86_INTEL_LPSS=y\n# CONFIG_X86_LONGHAUL is not set\n# CONFIG_X86_MCE is not set\nCONFIG_X86_MINIMUM_CPU_FAMILY=5\n# CONFIG_X86_PCC_CPUFREQ is not set\nCONFIG_X86_PM_TIMER=y\nCONFIG_X86_REBOOTFIXUPS=y\n"
  },
  {
    "path": "target/linux/x86/geode/config-5.15",
    "content": "# CONFIG_3C515 is not set\nCONFIG_8139CP=y\nCONFIG_8139TOO=y\nCONFIG_8139TOO_8129=y\nCONFIG_8139TOO_PIO=y\n# CONFIG_8139TOO_TUNE_TWISTER is not set\n# CONFIG_8139_OLD_RX_RESET is not set\nCONFIG_ACPI=y\nCONFIG_ACPI_AC=y\n# CONFIG_ACPI_BATTERY is not set\n# CONFIG_ACPI_CMPC is not set\n# CONFIG_ACPI_CONTAINER is not set\nCONFIG_ACPI_CPU_FREQ_PSS=y\n# CONFIG_ACPI_DEBUG is not set\n# CONFIG_ACPI_DEBUGGER is not set\n# CONFIG_ACPI_DOCK is not set\n# CONFIG_ACPI_DPTF is not set\n# CONFIG_ACPI_EC_DEBUGFS is not set\nCONFIG_ACPI_FAN=y\nCONFIG_ACPI_HOTPLUG_IOAPIC=y\nCONFIG_ACPI_I2C_OPREGION=y\nCONFIG_ACPI_LEGACY_TABLES_LOOKUP=y\n# CONFIG_ACPI_PCI_SLOT is not set\nCONFIG_ACPI_PROCESSOR=y\n# CONFIG_ACPI_PROCESSOR_AGGREGATOR is not set\nCONFIG_ACPI_PROCESSOR_CSTATE=y\nCONFIG_ACPI_PROCESSOR_IDLE=y\nCONFIG_ACPI_REV_OVERRIDE_POSSIBLE=y\n# CONFIG_ACPI_SBS is not set\nCONFIG_ACPI_SPCR_TABLE=y\nCONFIG_ACPI_SYSTEM_POWER_STATES_SUPPORT=y\nCONFIG_ACPI_THERMAL=y\n# CONFIG_ACPI_TINY_POWER_BUTTON is not set\n# CONFIG_ACPI_WMI is not set\n# CONFIG_ADV_SWBUTTON is not set\nCONFIG_ALIX=y\n# CONFIG_AMD_PMC is not set\nCONFIG_ARCH_MIGHT_HAVE_ACPI_PDC=y\n# CONFIG_ATA_PIIX is not set\nCONFIG_CS5535_CLOCK_EVENT_SRC=y\nCONFIG_CS5535_MFGPT=y\nCONFIG_CS5535_MFGPT_DEFAULT_IRQ=7\n# CONFIG_CS89x0_ISA is not set\nCONFIG_DMA_ACPI=y\n# CONFIG_EL3 is not set\nCONFIG_GEODE_WDT=y\nCONFIG_GEOS=y\nCONFIG_GPIOLIB=y\nCONFIG_GPIO_ACPI=y\nCONFIG_GPIO_CDEV=y\nCONFIG_GPIO_CS5535=y\n# CONFIG_HPET is not set\n# CONFIG_HP_ACCEL is not set\nCONFIG_HWMON=y\nCONFIG_I2C=y\nCONFIG_I2C_ALGOBIT=y\nCONFIG_I2C_ALGOPCA=y\nCONFIG_I2C_ALGOPCF=y\n# CONFIG_I2C_AMD_MP2 is not set\nCONFIG_I2C_BOARDINFO=y\n# CONFIG_I2C_HID_ACPI is not set\n# CONFIG_I2C_MULTI_INSTANTIATE is not set\n# CONFIG_I8K is not set\n# CONFIG_INTEL_IPS is not set\n# CONFIG_INTEL_MENLOW is not set\n# CONFIG_INTEL_SAR_INT1092 is not set\n# CONFIG_INTEL_SCU_PLATFORM is not set\n# CONFIG_INTEL_SOC_DTS_THERMAL is not set\nCONFIG_IOSF_MBI=y\n# CONFIG_IOSF_MBI_DEBUG is not set\nCONFIG_ISA=y\n# CONFIG_ISAPNP is not set\nCONFIG_ISA_BUS_API=y\n# CONFIG_ISCSI_IBFT is not set\n# CONFIG_LANCE is not set\nCONFIG_LEDS_GPIO=y\n# CONFIG_M686 is not set\n# CONFIG_MDA_CONSOLE is not set\nCONFIG_MFD_CORE=y\nCONFIG_MFD_CS5535=y\n# CONFIG_MFD_INTEL_LPSS_ACPI is not set\n# CONFIG_MFD_INTEL_PMC_BXT is not set\nCONFIG_MGEODEGX1=y\n# CONFIG_MIXCOMWD is not set\nCONFIG_NATSEMI=y\nCONFIG_NET5501=y\nCONFIG_NSC_GPIO=y\nCONFIG_PATA_CS5520=y\nCONFIG_PATA_CS5530=y\nCONFIG_PATA_CS5535=y\nCONFIG_PATA_CS5536=y\nCONFIG_PATA_SC1200=y\nCONFIG_PC8736x_GPIO=y\n# CONFIG_PCENGINES_APU2 is not set\nCONFIG_PCI_MMCONFIG=y\n# CONFIG_PCWATCHDOG is not set\nCONFIG_PINCTRL=y\n# CONFIG_PINCTRL_ALDERLAKE is not set\n# CONFIG_PINCTRL_BAYTRAIL is not set\n# CONFIG_PINCTRL_BROXTON is not set\n# CONFIG_PINCTRL_CANNONLAKE is not set\n# CONFIG_PINCTRL_CHERRYVIEW is not set\n# CONFIG_PINCTRL_DENVERTON is not set\n# CONFIG_PINCTRL_ELKHARTLAKE is not set\n# CONFIG_PINCTRL_EMMITSBURG is not set\n# CONFIG_PINCTRL_GEMINILAKE is not set\n# CONFIG_PINCTRL_JASPERLAKE is not set\n# CONFIG_PINCTRL_LAKEFIELD is not set\n# CONFIG_PINCTRL_LEWISBURG is not set\n# CONFIG_PINCTRL_LYNXPOINT is not set\n# CONFIG_PINCTRL_SUNRISEPOINT is not set\n# CONFIG_PINCTRL_TIGERLAKE is not set\n# CONFIG_PMIC_OPREGION is not set\nCONFIG_PNP=y\nCONFIG_PNPACPI=y\n# CONFIG_PNPBIOS is not set\nCONFIG_PNP_DEBUG_MESSAGES=y\nCONFIG_RTC_I2C_AND_SPI=y\n# CONFIG_SAMSUNG_Q10 is not set\nCONFIG_SC1200_WDT=y\n# CONFIG_SCSI_FDOMAIN_ISA is not set\nCONFIG_SCx200_ACB=y\nCONFIG_SCx200_WDT=y\nCONFIG_SENSORS_LM90=y\nCONFIG_SERIAL_8250_PNP=y\nCONFIG_SERIAL_MCTRL_GPIO=y\n# CONFIG_SURFACE_PLATFORMS is not set\n# CONFIG_SYSTEM76_ACPI is not set\n# CONFIG_TOSHIBA_BT_RFKILL is not set\n# CONFIG_USB_UHCI_HCD is not set\nCONFIG_VIA_RHINE=y\nCONFIG_VIA_RHINE_MMIO=y\n# CONFIG_WDT is not set\n# CONFIG_WIRELESS_HOTKEY is not set\n# CONFIG_X86_ACPI_CPUFREQ is not set\nCONFIG_X86_ALIGNMENT_16=y\n# CONFIG_X86_AMD_PLATFORM_DEVICE is not set\nCONFIG_X86_CPUID=y\n# CONFIG_X86_E_POWERSAVER is not set\nCONFIG_X86_INTEL_LPSS=y\n# CONFIG_X86_LONGHAUL is not set\n# CONFIG_X86_MCE is not set\nCONFIG_X86_MINIMUM_CPU_FAMILY=5\n# CONFIG_X86_PCC_CPUFREQ is not set\nCONFIG_X86_PM_TIMER=y\nCONFIG_X86_REBOOTFIXUPS=y\n"
  },
  {
    "path": "target/linux/x86/geode/target.mk",
    "content": "BOARDNAME:=AMD Geode based systems\nFEATURES += pci usb gpio\n\ndefine Target/Description\n\tBuild firmware images for AMD Geode GX/LX based systems (net5501, alix, geos)\nendef\n"
  },
  {
    "path": "target/linux/x86/image/64.mk",
    "content": "define Device/generic\n  DEVICE_VENDOR := Generic\n  DEVICE_MODEL := x86/64\n  DEVICE_PACKAGES += \\\n\tkmod-amazon-ena kmod-amd-xgbe kmod-bnx2 kmod-e1000e kmod-e1000 \\\n\tkmod-forcedeth kmod-fs-vfat kmod-igb kmod-ixgbe kmod-r8169 \\\n\tkmod-tg3\n  GRUB2_VARIANT := generic\nendef\nTARGET_DEVICES += generic\n"
  },
  {
    "path": "target/linux/x86/image/Makefile",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2006-2020 OpenWrt.org\n\ninclude $(TOPDIR)/rules.mk\ninclude $(INCLUDE_DIR)/image.mk\n\nGRUB2_VARIANT =\nGRUB_TERMINALS =\nGRUB_SERIAL_CONFIG =\nGRUB_TERMINAL_CONFIG =\nGRUB_CONSOLE_CMDLINE =\n\nifneq ($(CONFIG_GRUB_CONSOLE),)\n  GRUB_CONSOLE_CMDLINE += console=tty0\n  GRUB_TERMINALS += console\nendif\n\nGRUB_SERIAL:=$(call qstrip,$(CONFIG_GRUB_SERIAL))\n\nifneq ($(GRUB_SERIAL),)\n  GRUB_CONSOLE_CMDLINE += console=$(GRUB_SERIAL),$(CONFIG_GRUB_BAUDRATE)n8$(if $(CONFIG_GRUB_FLOWCONTROL),r,)\n  GRUB_SERIAL_CONFIG := serial --unit=0 --speed=$(CONFIG_GRUB_BAUDRATE) --word=8 --parity=no --stop=1 --rtscts=$(if $(CONFIG_GRUB_FLOWCONTROL),on,off)\n  GRUB_TERMINALS += serial\nendif\n\nifneq ($(GRUB_TERMINALS),)\n  GRUB_TERMINAL_CONFIG := terminal_input $(GRUB_TERMINALS); terminal_output $(GRUB_TERMINALS)\nendif\n\nROOTPART:=$(call qstrip,$(CONFIG_TARGET_ROOTFS_PARTNAME))\nROOTPART:=$(if $(ROOTPART),$(ROOTPART),PARTUUID=$(IMG_PART_SIGNATURE)-02)\nGPT_ROOTPART:=$(call qstrip,$(CONFIG_TARGET_ROOTFS_PARTNAME))\nGPT_ROOTPART:=$(if $(GPT_ROOTPART),$(GPT_ROOTPART),PARTUUID=$(shell echo $(IMG_PART_DISKGUID) | sed 's/00$$/02/'))\n\nGRUB_TIMEOUT:=$(call qstrip,$(CONFIG_GRUB_TIMEOUT))\nGRUB_TITLE:=$(call qstrip,$(CONFIG_GRUB_TITLE))\n\nBOOTOPTS:=$(call qstrip,$(CONFIG_GRUB_BOOTOPTS))\n\ndefine Build/combined\n\t$(CP) $(KDIR)/$(KERNEL_NAME) $@.boot/boot/vmlinuz\n\t-$(CP) $(STAGING_DIR_ROOT)/boot/. $@.boot/boot/\n\t$(CP) $(STAGING_DIR_IMAGE)/grub2/boot.img $@.boot/boot/grub/\n\t$(CP) $(STAGING_DIR_IMAGE)/grub2/$(if $(filter $(1),efi),gpt,$(GRUB2_VARIANT))-core.img \\\n\t\t$@.boot/boot/grub/core.img\n\t$(if $(filter $(1),efi),\n\t\t$(INSTALL_DIR) $@.boot/efi/boot\n\t\t$(CP) $(STAGING_DIR_IMAGE)/grub2/boot$(if $(CONFIG_x86_64),x64,ia32).efi $@.boot/efi/boot/\n\t)\n\tPADDING=\"1\" SIGNATURE=\"$(IMG_PART_SIGNATURE)\" \\\n\t\t$(if $(filter $(1),efi),GUID=\"$(IMG_PART_DISKGUID)\") $(SCRIPT_DIR)/gen_image_generic.sh \\\n\t\t$@ \\\n\t\t$(CONFIG_TARGET_KERNEL_PARTSIZE) $@.boot \\\n\t\t$(CONFIG_TARGET_ROOTFS_PARTSIZE) $(IMAGE_ROOTFS) \\\n\t\t256\nendef\n\ndefine Build/grub-config\n\trm -fR $@.boot\n\t$(INSTALL_DIR) $@.boot/boot/grub\n\tsed \\\n\t\t-e 's#@SERIAL_CONFIG@#$(strip $(GRUB_SERIAL_CONFIG))#g' \\\n\t\t-e 's#@TERMINAL_CONFIG@#$(strip $(GRUB_TERMINAL_CONFIG))#g' \\\n\t\t-e 's#@ROOTPART@#root=$(ROOTPART) rootwait#g' \\\n\t\t-e 's#@GPT_ROOTPART@#root=$(GPT_ROOTPART) rootwait#g' \\\n\t\t-e 's#@CMDLINE@#$(BOOTOPTS) $(GRUB_CONSOLE_CMDLINE)#g' \\\n\t\t-e 's#@TIMEOUT@#$(GRUB_TIMEOUT)#g' \\\n\t\t-e 's#@TITLE@#$(GRUB_TITLE)#g' \\\n\t\t./grub-$(1).cfg > $@.boot/boot/grub/grub.cfg\nendef\n\ndefine Build/grub-install\n\trm -fR $@.grub2\n\t$(INSTALL_DIR) $@.grub2\n\t$(CP) $(STAGING_DIR_IMAGE)/grub2/boot.img $@.grub2/\n\t$(CP) $(STAGING_DIR_IMAGE)/grub2/$(if $(filter $(1),efi),gpt,$(GRUB2_VARIANT))-core.img $@.grub2/core.img\n\techo '(hd0) $@' > $@.grub2/device.map\n\t$(STAGING_DIR_HOST)/bin/grub-bios-setup \\\n\t\t-m \"$@.grub2/device.map\" \\\n\t\t-d \"$@.grub2\" \\\n\t\t-r \"hd0,$(if $(filter $(1),efi),gpt1,msdos1)\" \\\n\t\t$@\nendef\n\ndefine Build/iso\n\t$(CP) $(KDIR)/$(KERNEL_NAME) $@.boot/boot/vmlinuz\n\tcat \\\n\t\t$(STAGING_DIR_IMAGE)/grub2/cdboot.img \\\n\t\t$(STAGING_DIR_IMAGE)/grub2/eltorito.img \\\n\t\t> $@.boot/boot/grub/eltorito.img\n\t-$(CP) $(STAGING_DIR_ROOT)/boot/. $@.boot/boot/\n\t$(if $(filter $(1),efi),\n\t\tmkfs.fat -C $@.boot/boot/grub/isoboot.img -S 512 1440\n\t\tmmd -i $@.boot/boot/grub/isoboot.img ::/efi ::/efi/boot\n\t\tmcopy -i $@.boot/boot/grub/isoboot.img \\\n\t\t\t$(STAGING_DIR_IMAGE)/grub2/iso-boot$(if $(CONFIG_x86_64),x64,ia32).efi \\\n\t\t\t::/efi/boot/boot$(if $(CONFIG_x86_64),x64,ia32).efi\n\t)\n\tmkisofs -R -b boot/grub/eltorito.img -no-emul-boot -boot-info-table \\\n\t\t$(if $(filter $(1),efi),-boot-load-size 4 -c boot.cat -eltorito-alt-boot -b boot/grub/isoboot.img -no-emul-boot) \\\n\t\t-o $@ $@.boot $(TARGET_DIR)\nendef\n\nDEVICE_VARS += GRUB2_VARIANT\ndefine Device/Default\n  ARTIFACT/image.iso := grub-config iso | iso\n  IMAGE/combined.img := grub-config pc | combined | grub-install | append-metadata\n  IMAGE/combined.img.gz := grub-config pc | combined | grub-install | gzip | append-metadata\n  IMAGE/combined.vdi := grub-config pc | combined | grub-install | qemu-image vdi\n  IMAGE/combined.vmdk := grub-config pc | combined | grub-install | qemu-image vmdk\n  IMAGE/combined.vhdx := grub-config pc | combined | grub-install | qemu-image vhdx -o subformat=dynamic\n  IMAGE/rootfs.img := append-rootfs | pad-to $(ROOTFS_PARTSIZE)\n  IMAGE/rootfs.img.gz := append-rootfs | pad-to $(ROOTFS_PARTSIZE) | gzip\n  ARTIFACT/image-efi.iso := grub-config iso | iso efi\n  IMAGE/combined-efi.img := grub-config efi | combined efi | grub-install efi | append-metadata\n  IMAGE/combined-efi.img.gz := grub-config efi | combined efi | grub-install efi | gzip | append-metadata\n  IMAGE/combined-efi.vdi := grub-config efi | combined efi | grub-install efi | qemu-image vdi\n  IMAGE/combined-efi.vmdk := grub-config efi | combined efi | grub-install efi | qemu-image vmdk\n  IMAGE/combined-efi.vhdx := grub-config efi | combined efi | grub-install efi | qemu-image vhdx -o subformat=dynamic\n  ifeq ($(CONFIG_TARGET_IMAGES_GZIP),y)\n    IMAGES-y := rootfs.img.gz\n    IMAGES-$$(CONFIG_GRUB_IMAGES) += combined.img.gz\n    IMAGES-$$(CONFIG_GRUB_EFI_IMAGES) += combined-efi.img.gz\n  else\n    IMAGES-y := rootfs.img\n    IMAGES-$$(CONFIG_GRUB_IMAGES) += combined.img\n    IMAGES-$$(CONFIG_GRUB_EFI_IMAGES) += combined-efi.img\n  endif\n  KERNEL := kernel-bin\n  KERNEL_INSTALL := 1\n  KERNEL_NAME := bzImage\n  ifeq ($(CONFIG_ISO_IMAGES),y)\n    ARTIFACTS-$$(CONFIG_GRUB_IMAGES) += image.iso\n    ARTIFACTS-$$(CONFIG_GRUB_EFI_IMAGES) += image-efi.iso\n  endif\n  ifeq ($(CONFIG_VDI_IMAGES),y)\n    IMAGES-$$(CONFIG_GRUB_IMAGES) += combined.vdi\n    IMAGES-$$(CONFIG_GRUB_EFI_IMAGES) += combined-efi.vdi\n  endif\n  ifeq ($(CONFIG_VMDK_IMAGES),y)\n    IMAGES-$$(CONFIG_GRUB_IMAGES) += combined.vmdk\n    IMAGES-$$(CONFIG_GRUB_EFI_IMAGES) += combined-efi.vmdk\n  endif\n  ifeq ($(CONFIG_VHDX_IMAGES),y)\n    IMAGES-$$(CONFIG_GRUB_IMAGES) += combined.vhdx\n    IMAGES-$$(CONFIG_GRUB_EFI_IMAGES) += combined-efi.vhdx\n  endif\n  IMAGES := $$(IMAGES-y)\n  ARTIFACTS := $$(ARTIFACTS-y)\n  SUPPORTED_DEVICES :=\nendef\n\ninclude $(SUBTARGET).mk\n\n$(eval $(call BuildImage))\n\n"
  },
  {
    "path": "target/linux/x86/image/generic.mk",
    "content": "define Device/generic\n  DEVICE_VENDOR := Generic\n  DEVICE_MODEL := x86\n  DEVICE_PACKAGES += kmod-3c59x kmod-8139too kmod-e100 kmod-e1000 kmod-natsemi \\\n\tkmod-ne2k-pci kmod-pcnet32 kmod-r8169 kmod-sis900 kmod-tg3 \\\n\tkmod-via-rhine kmod-via-velocity kmod-forcedeth kmod-fs-vfat\n  GRUB2_VARIANT := generic\nendef\nTARGET_DEVICES += generic\n"
  },
  {
    "path": "target/linux/x86/image/geode.mk",
    "content": "define Device/generic\n  DEVICE_VENDOR := Generic\n  DEVICE_MODEL := x86/Geode\n  DEVICE_PACKAGES += kmod-crypto-cbc kmod-crypto-ecb kmod-crypto-hw-geode \\\n\tkmod-ledtrig-gpio\n  GRUB2_VARIANT := legacy\nendef\nTARGET_DEVICES += generic\n\ndefine Device/geos\n  $(call Device/generic)\n  DEVICE_VENDOR := Traverse Technologies\n  DEVICE_MODEL := Geos\n  DEVICE_PACKAGES += br2684ctl flashrom kmod-hwmon-lm90 kmod-mppe kmod-pppoa \\\n\tkmod-usb-ohci-pci linux-atm ppp-mod-pppoa pppdump pppstats soloscli tc\nendef\nTARGET_DEVICES += geos\n"
  },
  {
    "path": "target/linux/x86/image/grub-efi.cfg",
    "content": "@SERIAL_CONFIG@\n@TERMINAL_CONFIG@\n\nset default=\"0\"\nset timeout=\"@TIMEOUT@\"\nsearch -l kernel -s root\n\nmenuentry \"@TITLE@\" {\n\tlinux /boot/vmlinuz @GPT_ROOTPART@ @CMDLINE@ noinitrd\n}\nmenuentry \"@TITLE@ (failsafe)\" {\n\tlinux /boot/vmlinuz failsafe=true @GPT_ROOTPART@ @CMDLINE@ noinitrd\n}\n"
  },
  {
    "path": "target/linux/x86/image/grub-iso.cfg",
    "content": "@SERIAL_CONFIG@\n@TERMINAL_CONFIG@\n\nset default=\"0\"\nset timeout=\"@TIMEOUT@\"\n\nif [ \"${grub_platform}\" = \"efi\" ]; then\n    set root='(cd0)'\nelse\n    set root='(cd)'\nfi\n\nmenuentry \"@TITLE@\" {\n\tlinux /boot/vmlinuz root=/dev/sr0 rootfstype=iso9660 rootwait @CMDLINE@ noinitrd\n}\n"
  },
  {
    "path": "target/linux/x86/image/grub-pc.cfg",
    "content": "@SERIAL_CONFIG@\n@TERMINAL_CONFIG@\n\nset default=\"0\"\nset timeout=\"@TIMEOUT@\"\nset root='(hd0,msdos1)'\n\nmenuentry \"@TITLE@\" {\n\tlinux /boot/vmlinuz @ROOTPART@ @CMDLINE@ noinitrd\n}\nmenuentry \"@TITLE@ (failsafe)\" {\n\tlinux /boot/vmlinuz failsafe=true @ROOTPART@ @CMDLINE@ noinitrd\n}\n"
  },
  {
    "path": "target/linux/x86/image/legacy.mk",
    "content": "define Device/generic\n  DEVICE_VENDOR := Generic\n  DEVICE_MODEL := x86/legacy\n  DEVICE_PACKAGES += kmod-3c59x kmod-8139too kmod-e100 kmod-e1000 \\\n\tkmod-natsemi kmod-ne2k-pci kmod-pcnet32 kmod-r8169 kmod-sis900 \\\n\tkmod-tg3 kmod-via-rhine kmod-via-velocity kmod-forcedeth\n  GRUB2_VARIANT := legacy\nendef\nTARGET_DEVICES += generic\n"
  },
  {
    "path": "target/linux/x86/legacy/config-5.10",
    "content": "# CONFIG_3C515 is not set\nCONFIG_ACPI=y\nCONFIG_ACPI_AC=y\nCONFIG_ACPI_BATTERY=y\nCONFIG_ACPI_BUTTON=y\n# CONFIG_ACPI_CMPC is not set\n# CONFIG_ACPI_CONTAINER is not set\nCONFIG_ACPI_CPU_FREQ_PSS=y\n# CONFIG_ACPI_DEBUG is not set\n# CONFIG_ACPI_DEBUGGER is not set\n# CONFIG_ACPI_DOCK is not set\n# CONFIG_ACPI_DPTF is not set\n# CONFIG_ACPI_EC_DEBUGFS is not set\n# CONFIG_ACPI_FAN is not set\nCONFIG_ACPI_HOTPLUG_IOAPIC=y\n# CONFIG_ACPI_I2C_OPREGION is not set\nCONFIG_ACPI_LEGACY_TABLES_LOOKUP=y\n# CONFIG_ACPI_PCI_SLOT is not set\nCONFIG_ACPI_PROCESSOR=y\n# CONFIG_ACPI_PROCESSOR_AGGREGATOR is not set\nCONFIG_ACPI_PROCESSOR_CSTATE=y\nCONFIG_ACPI_PROCESSOR_IDLE=y\nCONFIG_ACPI_REV_OVERRIDE_POSSIBLE=y\n# CONFIG_ACPI_SBS is not set\nCONFIG_ACPI_SPCR_TABLE=y\nCONFIG_ACPI_SYSTEM_POWER_STATES_SUPPORT=y\nCONFIG_ACPI_THERMAL=y\nCONFIG_ACPI_VIDEO=y\n# CONFIG_ACPI_WMI is not set\nCONFIG_AGP=y\n# CONFIG_AGP_ALI is not set\n# CONFIG_AGP_AMD is not set\n# CONFIG_AGP_AMD64 is not set\n# CONFIG_AGP_ATI is not set\n# CONFIG_AGP_EFFICEON is not set\nCONFIG_AGP_INTEL=y\n# CONFIG_AGP_NVIDIA is not set\n# CONFIG_AGP_SIS is not set\n# CONFIG_AGP_SWORKS is not set\n# CONFIG_AGP_VIA is not set\nCONFIG_ARCH_MIGHT_HAVE_ACPI_PDC=y\nCONFIG_BACKLIGHT_CLASS_DEVICE=y\nCONFIG_BLK_DEV_SR=y\nCONFIG_CDROM=y\nCONFIG_CPU_IDLE_GOV_MENU=y\nCONFIG_DMA_ACPI=y\nCONFIG_DMA_SHARED_BUFFER=y\nCONFIG_DRM=y\nCONFIG_DRM_AMDGPU=y\n# CONFIG_DRM_AMD_DC is not set\nCONFIG_DRM_BOCHS=y\nCONFIG_DRM_BRIDGE=y\nCONFIG_DRM_FBDEV_EMULATION=y\nCONFIG_DRM_FBDEV_OVERALLOC=100\nCONFIG_DRM_I915=y\nCONFIG_DRM_I915_CAPTURE_ERROR=y\nCONFIG_DRM_I915_COMPRESS_ERROR=y\n# CONFIG_DRM_I915_DEBUG is not set\n# CONFIG_DRM_I915_DEBUG_GUC is not set\n# CONFIG_DRM_I915_DEBUG_MMIO is not set\n# CONFIG_DRM_I915_DEBUG_RUNTIME_PM is not set\n# CONFIG_DRM_I915_DEBUG_VBLANK_EVADE is not set\nCONFIG_DRM_I915_FENCE_TIMEOUT=10000\nCONFIG_DRM_I915_FORCE_PROBE=\"\"\nCONFIG_DRM_I915_HEARTBEAT_INTERVAL=2500\n# CONFIG_DRM_I915_LOW_LEVEL_TRACEPOINTS is not set\nCONFIG_DRM_I915_MAX_REQUEST_BUSYWAIT=8000\nCONFIG_DRM_I915_PREEMPT_TIMEOUT=640\n# CONFIG_DRM_I915_SELFTEST is not set\nCONFIG_DRM_I915_STOP_TIMEOUT=100\n# CONFIG_DRM_I915_SW_FENCE_CHECK_DAG is not set\n# CONFIG_DRM_I915_SW_FENCE_DEBUG_OBJECTS is not set\nCONFIG_DRM_I915_TIMESLICE_DURATION=1\nCONFIG_DRM_I915_USERFAULT_AUTOSUSPEND=250\nCONFIG_DRM_I915_USERPTR=y\n# CONFIG_DRM_I915_WERROR is not set\nCONFIG_DRM_KMS_FB_HELPER=y\nCONFIG_DRM_KMS_HELPER=y\nCONFIG_DRM_MIPI_DSI=y\nCONFIG_DRM_PANEL=y\nCONFIG_DRM_PANEL_BRIDGE=y\nCONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y\nCONFIG_DRM_RADEON=y\nCONFIG_DRM_SCHED=y\nCONFIG_DRM_TTM=y\nCONFIG_DRM_TTM_HELPER=y\nCONFIG_DRM_VRAM_HELPER=y\n# CONFIG_EL3 is not set\nCONFIG_FB=y\nCONFIG_FB_CFB_COPYAREA=y\nCONFIG_FB_CFB_FILLRECT=y\nCONFIG_FB_CFB_IMAGEBLIT=y\nCONFIG_FB_CMDLINE=y\nCONFIG_FB_DEFERRED_IO=y\n# CONFIG_FB_I810 is not set\nCONFIG_FB_SYS_COPYAREA=y\nCONFIG_FB_SYS_FILLRECT=y\nCONFIG_FB_SYS_FOPS=y\nCONFIG_FB_SYS_IMAGEBLIT=y\n# CONFIG_FB_VESA is not set\nCONFIG_FONT_8x16=y\nCONFIG_FONT_8x8=y\nCONFIG_FONT_SUPPORT=y\nCONFIG_FRAMEBUFFER_CONSOLE=y\nCONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y\n# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set\nCONFIG_HDMI=y\nCONFIG_HID_BATTERY_STRENGTH=y\n# CONFIG_HIGHMEM4G is not set\nCONFIG_HPET=y\nCONFIG_HPET_MMAP=y\n# CONFIG_HP_ACCEL is not set\nCONFIG_HWMON=y\nCONFIG_I2C=y\nCONFIG_I2C_ALGOBIT=y\n# CONFIG_I2C_AMD_MP2 is not set\nCONFIG_I2C_BOARDINFO=y\n# CONFIG_I2C_MULTI_INSTANTIATE is not set\nCONFIG_INPUT_MOUSE=y\nCONFIG_INPUT_MOUSEDEV=y\nCONFIG_INPUT_MOUSEDEV_PSAUX=y\nCONFIG_INPUT_MOUSEDEV_SCREEN_X=1024\nCONFIG_INPUT_MOUSEDEV_SCREEN_Y=768\nCONFIG_INTEL_GTT=y\nCONFIG_INTEL_IDLE=y\n# CONFIG_INTEL_IPS is not set\n# CONFIG_INTEL_MEI_HDCP is not set\n# CONFIG_INTEL_MENLOW is not set\n# CONFIG_INTEL_SCU_PLATFORM is not set\n# CONFIG_INTEL_SOC_DTS_THERMAL is not set\nCONFIG_INTERVAL_TREE=y\nCONFIG_IOSF_MBI=y\n# CONFIG_IOSF_MBI_DEBUG is not set\nCONFIG_ISA=y\nCONFIG_ISAPNP=y\nCONFIG_ISA_BUS_API=y\n# CONFIG_ISCSI_IBFT is not set\nCONFIG_ISO9660_FS=y\n# CONFIG_JOLIET is not set\nCONFIG_KCMP=y\n# CONFIG_LANCE is not set\nCONFIG_M586MMX=y\n# CONFIG_M686 is not set\n# CONFIG_MDA_CONSOLE is not set\nCONFIG_MFD_CORE=y\nCONFIG_MFD_INTEL_LPSS=y\nCONFIG_MFD_INTEL_LPSS_ACPI=y\n# CONFIG_MFD_INTEL_PMC_BXT is not set\n# CONFIG_MIXCOMWD is not set\nCONFIG_MMU_NOTIFIER=y\n# CONFIG_MOUSE_BCM5974 is not set\n# CONFIG_MOUSE_CYAPA is not set\nCONFIG_MOUSE_PS2=y\nCONFIG_MOUSE_PS2_ALPS=y\n# CONFIG_MOUSE_PS2_BYD is not set\n# CONFIG_MOUSE_PS2_CYPRESS is not set\n# CONFIG_MOUSE_PS2_ELANTECH is not set\nCONFIG_MOUSE_PS2_LIFEBOOK=y\nCONFIG_MOUSE_PS2_LOGIPS2PP=y\nCONFIG_MOUSE_PS2_SMBUS=y\nCONFIG_MOUSE_PS2_SYNAPTICS=y\nCONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y\n# CONFIG_MOUSE_PS2_TOUCHKIT is not set\nCONFIG_MOUSE_PS2_TRACKPOINT=y\n# CONFIG_MOUSE_SERIAL is not set\n# CONFIG_MOUSE_VSXXXAA is not set\nCONFIG_NOHIGHMEM=y\nCONFIG_NO_HZ=y\nCONFIG_PATA_AMD=y\nCONFIG_PATA_ATIIXP=y\nCONFIG_PATA_LEGACY=y\nCONFIG_PATA_MPIIX=y\nCONFIG_PATA_OLDPIIX=y\nCONFIG_PATA_PLATFORM=y\nCONFIG_PATA_SC1200=y\nCONFIG_PATA_SIS=y\nCONFIG_PATA_TIMINGS=y\nCONFIG_PATA_VIA=y\nCONFIG_PCIEAER=y\nCONFIG_PCIEPORTBUS=y\nCONFIG_PCI_MMCONFIG=y\n# CONFIG_PCWATCHDOG is not set\n# CONFIG_PMIC_OPREGION is not set\nCONFIG_PNP=y\nCONFIG_PNPACPI=y\n# CONFIG_PNPBIOS is not set\nCONFIG_PNP_DEBUG_MESSAGES=y\nCONFIG_RAS=y\nCONFIG_RELAY=y\nCONFIG_RTC_I2C_AND_SPI=y\n# CONFIG_SAMSUNG_Q10 is not set\nCONFIG_SATA_AHCI=y\n# CONFIG_SCSI_FDOMAIN_ISA is not set\n# CONFIG_SENSORS_AMD_ENERGY is not set\nCONFIG_SERIAL_8250_PNP=y\n# CONFIG_SURFACE_3_POWER_OPREGION is not set\n# CONFIG_SURFACE_PRO3_BUTTON is not set\nCONFIG_SYNC_FILE=y\n# CONFIG_SYSTEM76_ACPI is not set\n# CONFIG_TOSHIBA_BT_RFKILL is not set\nCONFIG_USB_STORAGE=y\nCONFIG_VMAP_PFN=y\n# CONFIG_WDT is not set\nCONFIG_X86_ACPI_CPUFREQ=y\n# CONFIG_X86_ACPI_CPUFREQ_CPB is not set\nCONFIG_X86_ALIGNMENT_16=y\n# CONFIG_X86_AMD_FREQ_SENSITIVITY is not set\n# CONFIG_X86_AMD_PLATFORM_DEVICE is not set\n# CONFIG_X86_E_POWERSAVER is not set\nCONFIG_X86_F00F_BUG=y\n# CONFIG_X86_INTEL_LPSS is not set\n# CONFIG_X86_LONGHAUL is not set\nCONFIG_X86_MINIMUM_CPU_FAMILY=5\n# CONFIG_X86_PAE is not set\n# CONFIG_X86_PCC_CPUFREQ is not set\nCONFIG_X86_PM_TIMER=y\n# CONFIG_X86_POWERNOW_K8 is not set\nCONFIG_ZLIB_DEFLATE=y\n"
  },
  {
    "path": "target/linux/x86/legacy/config-5.15",
    "content": "# CONFIG_3C515 is not set\nCONFIG_ACPI=y\nCONFIG_ACPI_AC=y\nCONFIG_ACPI_BATTERY=y\nCONFIG_ACPI_BUTTON=y\n# CONFIG_ACPI_CMPC is not set\n# CONFIG_ACPI_CONTAINER is not set\nCONFIG_ACPI_CPU_FREQ_PSS=y\n# CONFIG_ACPI_DEBUG is not set\n# CONFIG_ACPI_DEBUGGER is not set\n# CONFIG_ACPI_DOCK is not set\n# CONFIG_ACPI_DPTF is not set\n# CONFIG_ACPI_EC_DEBUGFS is not set\n# CONFIG_ACPI_FAN is not set\nCONFIG_ACPI_HOTPLUG_IOAPIC=y\n# CONFIG_ACPI_I2C_OPREGION is not set\nCONFIG_ACPI_LEGACY_TABLES_LOOKUP=y\n# CONFIG_ACPI_PCI_SLOT is not set\nCONFIG_ACPI_PROCESSOR=y\n# CONFIG_ACPI_PROCESSOR_AGGREGATOR is not set\nCONFIG_ACPI_PROCESSOR_CSTATE=y\nCONFIG_ACPI_PROCESSOR_IDLE=y\nCONFIG_ACPI_REV_OVERRIDE_POSSIBLE=y\n# CONFIG_ACPI_SBS is not set\nCONFIG_ACPI_SPCR_TABLE=y\nCONFIG_ACPI_SYSTEM_POWER_STATES_SUPPORT=y\nCONFIG_ACPI_THERMAL=y\nCONFIG_ACPI_VIDEO=y\n# CONFIG_ACPI_WMI is not set\n# CONFIG_ADV_SWBUTTON is not set\nCONFIG_AGP=y\n# CONFIG_AGP_ALI is not set\n# CONFIG_AGP_AMD is not set\n# CONFIG_AGP_AMD64 is not set\n# CONFIG_AGP_ATI is not set\n# CONFIG_AGP_EFFICEON is not set\nCONFIG_AGP_INTEL=y\n# CONFIG_AGP_NVIDIA is not set\n# CONFIG_AGP_SIS is not set\n# CONFIG_AGP_SWORKS is not set\n# CONFIG_AGP_VIA is not set\n# CONFIG_AMD_PMC is not set\nCONFIG_ARCH_MIGHT_HAVE_ACPI_PDC=y\nCONFIG_BACKLIGHT_CLASS_DEVICE=y\nCONFIG_BLK_DEV_SR=y\nCONFIG_CDROM=y\nCONFIG_CPU_IDLE_GOV_MENU=y\n# CONFIG_CS89x0_ISA is not set\nCONFIG_DMA_ACPI=y\nCONFIG_DMA_SHARED_BUFFER=y\nCONFIG_DRM=y\nCONFIG_DRM_AMDGPU=y\n# CONFIG_DRM_AMD_DC is not set\nCONFIG_DRM_BOCHS=y\nCONFIG_DRM_BRIDGE=y\nCONFIG_DRM_FBDEV_EMULATION=y\nCONFIG_DRM_FBDEV_OVERALLOC=100\nCONFIG_DRM_I915=y\nCONFIG_DRM_I915_CAPTURE_ERROR=y\nCONFIG_DRM_I915_COMPRESS_ERROR=y\n# CONFIG_DRM_I915_DEBUG is not set\n# CONFIG_DRM_I915_DEBUG_GUC is not set\n# CONFIG_DRM_I915_DEBUG_MMIO is not set\n# CONFIG_DRM_I915_DEBUG_RUNTIME_PM is not set\n# CONFIG_DRM_I915_DEBUG_VBLANK_EVADE is not set\nCONFIG_DRM_I915_FENCE_TIMEOUT=10000\nCONFIG_DRM_I915_FORCE_PROBE=\"\"\nCONFIG_DRM_I915_HEARTBEAT_INTERVAL=2500\n# CONFIG_DRM_I915_LOW_LEVEL_TRACEPOINTS is not set\nCONFIG_DRM_I915_MAX_REQUEST_BUSYWAIT=8000\nCONFIG_DRM_I915_PREEMPT_TIMEOUT=640\nCONFIG_DRM_I915_REQUEST_TIMEOUT=20000\n# CONFIG_DRM_I915_SELFTEST is not set\nCONFIG_DRM_I915_STOP_TIMEOUT=100\n# CONFIG_DRM_I915_SW_FENCE_CHECK_DAG is not set\n# CONFIG_DRM_I915_SW_FENCE_DEBUG_OBJECTS is not set\nCONFIG_DRM_I915_TIMESLICE_DURATION=1\nCONFIG_DRM_I915_USERFAULT_AUTOSUSPEND=250\nCONFIG_DRM_I915_USERPTR=y\n# CONFIG_DRM_I915_WERROR is not set\nCONFIG_DRM_KMS_HELPER=y\nCONFIG_DRM_MIPI_DSI=y\nCONFIG_DRM_PANEL=y\nCONFIG_DRM_PANEL_BRIDGE=y\nCONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y\nCONFIG_DRM_RADEON=y\nCONFIG_DRM_SCHED=y\nCONFIG_DRM_TTM=y\nCONFIG_DRM_TTM_HELPER=y\nCONFIG_DRM_VRAM_HELPER=y\n# CONFIG_EL3 is not set\nCONFIG_FB=y\nCONFIG_FB_CFB_COPYAREA=y\nCONFIG_FB_CFB_FILLRECT=y\nCONFIG_FB_CFB_IMAGEBLIT=y\nCONFIG_FB_CMDLINE=y\nCONFIG_FB_DEFERRED_IO=y\n# CONFIG_FB_I810 is not set\nCONFIG_FB_SYS_COPYAREA=y\nCONFIG_FB_SYS_FILLRECT=y\nCONFIG_FB_SYS_FOPS=y\nCONFIG_FB_SYS_IMAGEBLIT=y\n# CONFIG_FB_VESA is not set\nCONFIG_FONT_8x16=y\nCONFIG_FONT_8x8=y\nCONFIG_FONT_SUPPORT=y\nCONFIG_FRAMEBUFFER_CONSOLE=y\nCONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y\n# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set\nCONFIG_HDMI=y\nCONFIG_HID_BATTERY_STRENGTH=y\n# CONFIG_HIGHMEM4G is not set\nCONFIG_HPET=y\nCONFIG_HPET_MMAP=y\n# CONFIG_HP_ACCEL is not set\nCONFIG_HWMON=y\nCONFIG_I2C=y\nCONFIG_I2C_ALGOBIT=y\n# CONFIG_I2C_AMD_MP2 is not set\nCONFIG_I2C_BOARDINFO=y\n# CONFIG_I2C_HID_ACPI is not set\n# CONFIG_I2C_MULTI_INSTANTIATE is not set\n# CONFIG_I8K is not set\nCONFIG_INPUT_MOUSE=y\nCONFIG_INPUT_MOUSEDEV=y\nCONFIG_INPUT_MOUSEDEV_PSAUX=y\nCONFIG_INPUT_MOUSEDEV_SCREEN_X=1024\nCONFIG_INPUT_MOUSEDEV_SCREEN_Y=768\nCONFIG_INTEL_GTT=y\nCONFIG_INTEL_IDLE=y\n# CONFIG_INTEL_IPS is not set\n# CONFIG_INTEL_MEI_HDCP is not set\n# CONFIG_INTEL_MENLOW is not set\n# CONFIG_INTEL_SAR_INT1092 is not set\n# CONFIG_INTEL_SCU_PLATFORM is not set\n# CONFIG_INTEL_SOC_DTS_THERMAL is not set\nCONFIG_INTERVAL_TREE=y\nCONFIG_IOSF_MBI=y\n# CONFIG_IOSF_MBI_DEBUG is not set\nCONFIG_ISA=y\nCONFIG_ISAPNP=y\nCONFIG_ISA_BUS_API=y\n# CONFIG_ISCSI_IBFT is not set\nCONFIG_ISO9660_FS=y\n# CONFIG_JOLIET is not set\nCONFIG_KCMP=y\n# CONFIG_LANCE is not set\nCONFIG_M586MMX=y\n# CONFIG_M686 is not set\n# CONFIG_MDA_CONSOLE is not set\nCONFIG_MFD_CORE=y\nCONFIG_MFD_INTEL_LPSS=y\nCONFIG_MFD_INTEL_LPSS_ACPI=y\n# CONFIG_MFD_INTEL_PMC_BXT is not set\n# CONFIG_MIXCOMWD is not set\nCONFIG_MMU_NOTIFIER=y\n# CONFIG_MOUSE_BCM5974 is not set\n# CONFIG_MOUSE_CYAPA is not set\nCONFIG_MOUSE_PS2=y\nCONFIG_MOUSE_PS2_ALPS=y\n# CONFIG_MOUSE_PS2_BYD is not set\n# CONFIG_MOUSE_PS2_CYPRESS is not set\n# CONFIG_MOUSE_PS2_ELANTECH is not set\nCONFIG_MOUSE_PS2_LIFEBOOK=y\nCONFIG_MOUSE_PS2_LOGIPS2PP=y\nCONFIG_MOUSE_PS2_SMBUS=y\nCONFIG_MOUSE_PS2_SYNAPTICS=y\nCONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y\n# CONFIG_MOUSE_PS2_TOUCHKIT is not set\nCONFIG_MOUSE_PS2_TRACKPOINT=y\n# CONFIG_MOUSE_SERIAL is not set\n# CONFIG_MOUSE_VSXXXAA is not set\nCONFIG_NOHIGHMEM=y\nCONFIG_NO_HZ=y\nCONFIG_PATA_AMD=y\nCONFIG_PATA_ATIIXP=y\nCONFIG_PATA_LEGACY=y\nCONFIG_PATA_MPIIX=y\nCONFIG_PATA_OLDPIIX=y\nCONFIG_PATA_PLATFORM=y\nCONFIG_PATA_SC1200=y\nCONFIG_PATA_SIS=y\nCONFIG_PATA_TIMINGS=y\nCONFIG_PATA_VIA=y\nCONFIG_PCIEAER=y\nCONFIG_PCIEPORTBUS=y\nCONFIG_PCI_MMCONFIG=y\n# CONFIG_PCWATCHDOG is not set\n# CONFIG_PMIC_OPREGION is not set\nCONFIG_PNP=y\nCONFIG_PNPACPI=y\n# CONFIG_PNPBIOS is not set\nCONFIG_PNP_DEBUG_MESSAGES=y\nCONFIG_RAS=y\nCONFIG_RELAY=y\nCONFIG_RTC_I2C_AND_SPI=y\n# CONFIG_SAMSUNG_Q10 is not set\nCONFIG_SATA_AHCI=y\n# CONFIG_SCSI_FDOMAIN_ISA is not set\nCONFIG_SERIAL_8250_PNP=y\n# CONFIG_SURFACE_PLATFORMS is not set\nCONFIG_SYNC_FILE=y\n# CONFIG_SYSTEM76_ACPI is not set\n# CONFIG_TOSHIBA_BT_RFKILL is not set\nCONFIG_USB_STORAGE=y\nCONFIG_VMAP_PFN=y\n# CONFIG_WDT is not set\n# CONFIG_WIRELESS_HOTKEY is not set\nCONFIG_X86_ACPI_CPUFREQ=y\n# CONFIG_X86_ACPI_CPUFREQ_CPB is not set\nCONFIG_X86_ALIGNMENT_16=y\n# CONFIG_X86_AMD_FREQ_SENSITIVITY is not set\n# CONFIG_X86_AMD_PLATFORM_DEVICE is not set\n# CONFIG_X86_E_POWERSAVER is not set\nCONFIG_X86_F00F_BUG=y\n# CONFIG_X86_INTEL_LPSS is not set\n# CONFIG_X86_LONGHAUL is not set\nCONFIG_X86_MINIMUM_CPU_FAMILY=5\n# CONFIG_X86_PAE is not set\n# CONFIG_X86_PCC_CPUFREQ is not set\nCONFIG_X86_PM_TIMER=y\n# CONFIG_X86_POWERNOW_K8 is not set\nCONFIG_ZLIB_DEFLATE=y\n"
  },
  {
    "path": "target/linux/x86/legacy/target.mk",
    "content": "BOARDNAME:=Legacy\n\ndefine Target/Description\n\tBuild firmware images for legacy x86 based boards\n\t(e.g : Soekris, ...)\nendef\n\n"
  },
  {
    "path": "target/linux/x86/modules.mk",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2017 Cezary Jackiewicz <cezary@eko.one.pll>\n\ndefine KernelPackage/amazon-ena\n  SUBMENU:=$(NETWORK_DEVICES_MENU)\n  TITLE:=Elastic Network Adapter (for Amazon AWS T3)\n  DEPENDS:=@TARGET_x86_64\n  KCONFIG:=CONFIG_ENA_ETHERNET\n  FILES:=$(LINUX_DIR)/drivers/net/ethernet/amazon/ena/ena.ko\n  AUTOLOAD:=$(call AutoLoad,12,ena)\nendef\n\ndefine KernelPackage/amazon-ena/description\n  This driver supports Elastic Network Adapter (ENA)\n  used by Amazon AWS T3 instances.\nendef\n\n$(eval $(call KernelPackage,amazon-ena))\n\n\ndefine KernelPackage/amd-xgbe\n  SUBMENU:=$(NETWORK_DEVICES_MENU)\n  TITLE:=AMD Ethernet on SoC support\n  DEPENDS:=@PCI_SUPPORT @TARGET_x86_64 +kmod-lib-crc32c +kmod-ptp +kmod-libphy +(LINUX_5_10||LINUX_5_15):kmod-mdio-devres\n  KCONFIG:=CONFIG_AMD_XGBE\n  FILES:=$(LINUX_DIR)/drivers/net/ethernet/amd/xgbe/amd-xgbe.ko\n  AUTOLOAD:=$(call AutoLoad,35,amd-xgbe)\nendef\n\ndefine KernelPackage/amd-xgbe/description\n Kernel modules for AMD 10GbE Ethernet device on an AMD SoC.\nendef\n\n$(eval $(call KernelPackage,amd-xgbe))\n\n\ndefine KernelPackage/f71808e-wdt\n  SUBMENU:=$(OTHER_MENU)\n  TITLE:=Fintek F718xx/F818xx Watchdog Timer\n  DEPENDS:=@TARGET_x86\n  KCONFIG:=CONFIG_F71808E_WDT\n  FILES:=$(LINUX_DIR)/drivers/watchdog/f71808e_wdt.ko\n  AUTOLOAD:=$(call AutoProbe,f71808e-wdt,1)\nendef\n\ndefine KernelPackage/f71808e-wdt/description\n  Kernel module for the watchdog timer found on many Fintek Super-IO chips.\nendef\n\n$(eval $(call KernelPackage,f71808e-wdt))\n\n\ndefine KernelPackage/sound-cs5535audio\n  TITLE:=CS5535/CS5536 Audio Controller\n  DEPENDS:=@TARGET_x86_geode +kmod-ac97\n  KCONFIG:=CONFIG_SND_CS5535AUDIO\n  FILES:=$(LINUX_DIR)/sound/pci/cs5535audio/snd-cs5535audio.ko\n  AUTOLOAD:=$(call AutoLoad,36,snd-cs5535audio)\n  $(call AddDepends/sound)\nendef\n\ndefine KernelPackage/sound-cs5535audio/description\n Support for the integrated AC97 sound device on motherboards\n with AMD CS5535/CS5536 chipsets.\nendef\n\n$(eval $(call KernelPackage,sound-cs5535audio))\n\ndefine KernelPackage/sp5100-tco\n  SUBMENU:=$(OTHER_MENU)\n  TITLE:=SP5100 Watchdog Support\n  DEPENDS:=@TARGET_x86\n  KCONFIG:=CONFIG_SP5100_TCO\n  FILES:=$(LINUX_DIR)/drivers/watchdog/sp5100_tco.ko\n  AUTOLOAD:=$(call AutoLoad,50,sp5100_tco,1)\nendef\n\ndefine KernelPackage/sp5100-tco/description\n Kernel module for the SP5100_TCO hardware watchdog.\nendef\n\n$(eval $(call KernelPackage,sp5100-tco))\n\n\ndefine KernelPackage/ib700-wdt\n  SUBMENU:=$(OTHER_MENU)\n  TITLE:=IB700 SBC Watchdog Timer\n  DEPENDS:=@TARGET_x86\n  KCONFIG:=CONFIG_IB700_WDT\n  FILES:=$(LINUX_DIR)/drivers/watchdog/ib700wdt.ko\n  AUTOLOAD:=$(call AutoLoad,50,ib700wdt,1)\nendef\n\ndefine KernelPackage/ib700-wdt/description\n  Kernel module for the hardware watchdog on the IB700 Single\n  Board Computer produced by TMC Technology (www.tmc-uk.com).\n  Also used by QEMU/libvirt.\nendef\n\n$(eval $(call KernelPackage,ib700-wdt))\n\ndefine KernelPackage/it87-wdt\n  SUBMENU:=$(OTHER_MENU)\n  TITLE:=ITE IT87 Watchdog Timer\n  DEPENDS:=@TARGET_x86\n  KCONFIG:=CONFIG_IT87_WDT\n  FILES:=$(LINUX_DIR)/drivers/watchdog/it87_wdt.ko\n  AUTOLOAD:=$(call AutoLoad,50,it87-wdt,1)\n  MODPARAMS.it87-wdt:= \\\n\tnogameport=1 \\\n\tnocir=1\nendef\n\ndefine KernelPackage/it87-wdt/description\n  Kernel module for ITE IT87 Watchdog Timer\nendef\n\n$(eval $(call KernelPackage,it87-wdt))\n\n\ndefine KernelPackage/itco-wdt\n  SUBMENU:=$(OTHER_MENU)\n  TITLE:=Intel iTCO Watchdog Timer\n  DEPENDS:=@TARGET_x86\n  KCONFIG:=CONFIG_ITCO_WDT \\\n           CONFIG_ITCO_VENDOR_SUPPORT=y\n  FILES:=$(LINUX_DIR)/drivers/watchdog/iTCO_wdt.ko \\\n         $(LINUX_DIR)/drivers/watchdog/iTCO_vendor_support.ko\n  AUTOLOAD:=$(call AutoLoad,50,iTCO_vendor_support iTCO_wdt,1)\nendef\n\ndefine KernelPackage/itco-wdt/description\n  Kernel module for Intel iTCO Watchdog Timer\nendef\n\n$(eval $(call KernelPackage,itco-wdt))\n\n\ndefine KernelPackage/pcengines-apuv2\n  SUBMENU:=$(OTHER_MENU)\n  TITLE:=PC Engines APUv2/3 front button and LEDs driver\n  DEPENDS:=@TARGET_x86 +kmod-gpio-amd-fch +kmod-leds-gpio\n  KCONFIG:=CONFIG_PCENGINES_APU2\n  FILES:=$(LINUX_DIR)/drivers/platform/x86/pcengines-apuv2.ko\n  AUTOLOAD:=$(call AutoLoad,60,pcengines-apuv2)\nendef\n\ndefine KernelPackage/pcengines-apuv2/description\n  This driver provides support for the front button and LEDs on\n  PC Engines APUv2/APUv3 board.\nendef\n\n$(eval $(call KernelPackage,pcengines-apuv2))\n\n\ndefine KernelPackage/meraki-mx100\n  SUBMENU:=$(OTHER_MENU)\n  TITLE:=Cisco Meraki MX100 Platform Driver\n  DEPENDS:=@TARGET_x86 +kmod-tg3 +kmod-gpio-button-hotplug +kmod-leds-gpio \\\n    +kmod-usb-ledtrig-usbport +PACKAGE_kmod-meraki-mx100:nu801 +kmod-itco-wdt \\\n    +kmod-leds-uleds\n  KCONFIG:=CONFIG_MERAKI_MX100\n  FILES:=$(LINUX_DIR)/drivers/platform/x86/meraki-mx100.ko\n  AUTOLOAD:=$(call AutoLoad,60,meraki-mx100,1)\nendef\n\ndefine KernelPackage/meraki-mx100/description\n  This driver provides support for the front button and LEDs on\n  the Cisco Meraki MX100 (Tinkerbell) 1U appliance. Note this also\n  selects the gpio-cdev nu801 userspace driver to support the Status\n  LED, as well as other required platform drivers.\nendef\n\n$(eval $(call KernelPackage,meraki-mx100))\n\ndefine KernelPackage/w83627hf-wdt\n  SUBMENU:=$(OTHER_MENU)\n  TITLE:=Winbond 83627HF Watchdog Timer\n  DEPENDS:=@TARGET_x86\n  KCONFIG:=CONFIG_W83627HF_WDT\n  FILES:=$(LINUX_DIR)/drivers/watchdog/w83627hf_wdt.ko\n  AUTOLOAD:=$(call AutoLoad,50,w83627hf-wdt,1)\nendef\n\ndefine KernelPackage/w83627hf-wdt/description\n  Kernel module for Winbond 83627HF Watchdog Timer\nendef\n\n$(eval $(call KernelPackage,w83627hf-wdt))\n"
  },
  {
    "path": "target/linux/x86/patches-5.10/100-fix_cs5535_clockevt.patch",
    "content": "--- a/drivers/clocksource/timer-cs5535.c\n+++ b/drivers/clocksource/timer-cs5535.c\n@@ -127,7 +127,9 @@ static irqreturn_t mfgpt_tick(int irq, v\n \t\tcs5535_mfgpt_write(cs5535_event_clock, MFGPT_REG_SETUP,\n \t\t\t\tMFGPT_SETUP_CNTEN | MFGPT_SETUP_CMP2);\n \n-\tcs5535_clockevent.event_handler(&cs5535_clockevent);\n+\tif (cs5535_clockevent.event_handler)\n+\t\tcs5535_clockevent.event_handler(&cs5535_clockevent);\n+\n \treturn IRQ_HANDLED;\n }\n \n"
  },
  {
    "path": "target/linux/x86/patches-5.10/101-v5.15-mfd-lpc_ich-Enable-GPIO-driver-for-DH89xxCC.patch",
    "content": "From ef0eea5b151aefe1efea78e2fa7c507ff3c56bf0 Mon Sep 17 00:00:00 2001\nFrom: Chris Blake <chrisrblake93@gmail.com>\nDate: Mon, 7 Jun 2021 18:35:35 -0500\nSubject: mfd: lpc_ich: Enable GPIO driver for DH89xxCC\n\nBased on the Intel Datasheet for the DH89xxCC PCH, the GPIO driver\nis the same as ICH_v5_GPIO, minus the fact the DH89xxCC also has\nblink support. However, blink support isn't supported by the GPIO\ndriver so we should use ICH_v5_GPIO. Tested and working on a Meraki\nMX100-HW.\n\nSigned-off-by: Chris Blake <chrisrblake93@gmail.com>\nCo-developed-by: Christian Lamparter <chunkeey@gmail.com>\nSigned-off-by: Lee Jones <lee.jones@linaro.org>\n---\n drivers/mfd/lpc_ich.c | 1 +\n 1 file changed, 1 insertion(+)\n\n--- a/drivers/mfd/lpc_ich.c\n+++ b/drivers/mfd/lpc_ich.c\n@@ -489,6 +489,7 @@ static struct lpc_ich_info lpc_chipset_i\n \t[LPC_DH89XXCC] = {\n \t\t.name = \"DH89xxCC\",\n \t\t.iTCO_version = 2,\n+\t\t.gpio_version = ICH_V5_GPIO,\n \t},\n \t[LPC_PPT] = {\n \t\t.name = \"Panther Point\",\n"
  },
  {
    "path": "target/linux/x86/patches-5.10/102-v5.15-platform-x86-add-meraki-mx100-platform-driver.patch",
    "content": "From 636a1e697555e73c28cdd6952a409edbfdd16475 Mon Sep 17 00:00:00 2001\nFrom: Chris Blake <chrisrblake93@gmail.com>\nDate: Mon, 9 Aug 2021 19:40:21 -0500\nSubject: platform/x86: add meraki-mx100 platform driver\n\nThis adds platform support for the Cisco Meraki MX100 (Tinkerbell)\nnetwork appliance. This sets up the network LEDs and Reset\nbutton.\n\nDepends-on: ef0eea5b151ae (\"mfd: lpc_ich: Enable GPIO driver for DH89xxCC\")\nCo-developed-by: Christian Lamparter <chunkeey@gmail.com>\nSigned-off-by: Christian Lamparter <chunkeey@gmail.com>\nSigned-off-by: Chris Blake <chrisrblake93@gmail.com>\nReviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>\nLink: https://lore.kernel.org/r/20210810004021.2538308-1-chrisrblake93@gmail.com\nReviewed-by: Hans de Goede <hdegoede@redhat.com>\nSigned-off-by: Hans de Goede <hdegoede@redhat.com>\n---\n drivers/platform/x86/Kconfig        |  13 ++\n drivers/platform/x86/Makefile       |   3 +\n drivers/platform/x86/meraki-mx100.c | 230 ++++++++++++++++++++++++++++++++++++\n 3 files changed, 246 insertions(+)\n create mode 100644 drivers/platform/x86/meraki-mx100.c\n\n--- a/drivers/platform/x86/Kconfig\n+++ b/drivers/platform/x86/Kconfig\n@@ -267,6 +267,19 @@ config ASUS_NB_WMI\n \t  If you have an ACPI-WMI compatible Asus Notebook, say Y or M\n \t  here.\n \n+config MERAKI_MX100\n+\ttristate \"Cisco Meraki MX100 Platform Driver\"\n+\tdepends on GPIOLIB\n+\tdepends on GPIO_ICH\n+\tdepends on LEDS_CLASS\n+\tselect LEDS_GPIO\n+\thelp\n+\t  This driver provides support for the front button and LEDs on\n+\t  the Cisco Meraki MX100 (Tinkerbell) 1U appliance.\n+\n+\t  To compile this driver as a module, choose M here: the module\n+\t  will be called meraki-mx100.\n+\n config EEEPC_LAPTOP\n \ttristate \"Eee PC Hotkey Driver\"\n \tdepends on ACPI\n--- a/drivers/platform/x86/Makefile\n+++ b/drivers/platform/x86/Makefile\n@@ -33,6 +33,9 @@ obj-$(CONFIG_ASUS_NB_WMI)\t+= asus-nb-wmi\n obj-$(CONFIG_EEEPC_LAPTOP)\t+= eeepc-laptop.o\n obj-$(CONFIG_EEEPC_WMI)\t\t+= eeepc-wmi.o\n \n+# Cisco/Meraki\n+obj-$(CONFIG_MERAKI_MX100)\t+= meraki-mx100.o\n+\n # Dell\n obj-$(CONFIG_DCDBAS)\t\t\t+= dcdbas.o\n obj-$(CONFIG_DELL_SMBIOS)\t\t+= dell-smbios.o\n--- /dev/null\n+++ b/drivers/platform/x86/meraki-mx100.c\n@@ -0,0 +1,230 @@\n+// SPDX-License-Identifier: GPL-2.0+\n+\n+/*\n+ * Cisco Meraki MX100 (Tinkerbell) board platform driver\n+ *\n+ * Based off of arch/x86/platform/meraki/tink.c from the\n+ * Meraki GPL release meraki-firmware-sources-r23-20150601\n+ *\n+ * Format inspired by platform/x86/pcengines-apuv2.c\n+ *\n+ * Copyright (C) 2021 Chris Blake <chrisrblake93@gmail.com>\n+ */\n+\n+#define pr_fmt(fmt)\tKBUILD_MODNAME \": \" fmt\n+\n+#include <linux/dmi.h>\n+#include <linux/err.h>\n+#include <linux/gpio_keys.h>\n+#include <linux/gpio/machine.h>\n+#include <linux/input.h>\n+#include <linux/io.h>\n+#include <linux/kernel.h>\n+#include <linux/leds.h>\n+#include <linux/module.h>\n+#include <linux/platform_device.h>\n+\n+#define TINK_GPIO_DRIVER_NAME \"gpio_ich\"\n+\n+/* LEDs */\n+static const struct gpio_led tink_leds[] = {\n+\t{\n+\t\t.name = \"mx100:green:internet\",\n+\t\t.default_trigger = \"default-on\",\n+\t},\n+\t{\n+\t\t.name = \"mx100:green:lan2\",\n+\t},\n+\t{\n+\t\t.name = \"mx100:green:lan3\",\n+\t},\n+\t{\n+\t\t.name = \"mx100:green:lan4\",\n+\t},\n+\t{\n+\t\t.name = \"mx100:green:lan5\",\n+\t},\n+\t{\n+\t\t.name = \"mx100:green:lan6\",\n+\t},\n+\t{\n+\t\t.name = \"mx100:green:lan7\",\n+\t},\n+\t{\n+\t\t.name = \"mx100:green:lan8\",\n+\t},\n+\t{\n+\t\t.name = \"mx100:green:lan9\",\n+\t},\n+\t{\n+\t\t.name = \"mx100:green:lan10\",\n+\t},\n+\t{\n+\t\t.name = \"mx100:green:lan11\",\n+\t},\n+\t{\n+\t\t.name = \"mx100:green:ha\",\n+\t},\n+\t{\n+\t\t.name = \"mx100:orange:ha\",\n+\t},\n+\t{\n+\t\t.name = \"mx100:green:usb\",\n+\t},\n+\t{\n+\t\t.name = \"mx100:orange:usb\",\n+\t},\n+};\n+\n+static const struct gpio_led_platform_data tink_leds_pdata = {\n+\t.num_leds\t= ARRAY_SIZE(tink_leds),\n+\t.leds\t\t= tink_leds,\n+};\n+\n+static struct gpiod_lookup_table tink_leds_table = {\n+\t.dev_id = \"leds-gpio\",\n+\t.table = {\n+\t\tGPIO_LOOKUP_IDX(TINK_GPIO_DRIVER_NAME, 11,\n+\t\t\t\tNULL, 0, GPIO_ACTIVE_LOW),\n+\t\tGPIO_LOOKUP_IDX(TINK_GPIO_DRIVER_NAME, 18,\n+\t\t\t\tNULL, 1, GPIO_ACTIVE_HIGH),\n+\t\tGPIO_LOOKUP_IDX(TINK_GPIO_DRIVER_NAME, 20,\n+\t\t\t\tNULL, 2, GPIO_ACTIVE_HIGH),\n+\t\tGPIO_LOOKUP_IDX(TINK_GPIO_DRIVER_NAME, 22,\n+\t\t\t\tNULL, 3, GPIO_ACTIVE_HIGH),\n+\t\tGPIO_LOOKUP_IDX(TINK_GPIO_DRIVER_NAME, 23,\n+\t\t\t\tNULL, 4, GPIO_ACTIVE_HIGH),\n+\t\tGPIO_LOOKUP_IDX(TINK_GPIO_DRIVER_NAME, 32,\n+\t\t\t\tNULL, 5, GPIO_ACTIVE_HIGH),\n+\t\tGPIO_LOOKUP_IDX(TINK_GPIO_DRIVER_NAME, 34,\n+\t\t\t\tNULL, 6, GPIO_ACTIVE_HIGH),\n+\t\tGPIO_LOOKUP_IDX(TINK_GPIO_DRIVER_NAME, 35,\n+\t\t\t\tNULL, 7, GPIO_ACTIVE_HIGH),\n+\t\tGPIO_LOOKUP_IDX(TINK_GPIO_DRIVER_NAME, 36,\n+\t\t\t\tNULL, 8, GPIO_ACTIVE_HIGH),\n+\t\tGPIO_LOOKUP_IDX(TINK_GPIO_DRIVER_NAME, 37,\n+\t\t\t\tNULL, 9, GPIO_ACTIVE_HIGH),\n+\t\tGPIO_LOOKUP_IDX(TINK_GPIO_DRIVER_NAME, 48,\n+\t\t\t\tNULL, 10, GPIO_ACTIVE_HIGH),\n+\t\tGPIO_LOOKUP_IDX(TINK_GPIO_DRIVER_NAME, 16,\n+\t\t\t\tNULL, 11, GPIO_ACTIVE_LOW),\n+\t\tGPIO_LOOKUP_IDX(TINK_GPIO_DRIVER_NAME, 7,\n+\t\t\t\tNULL, 12, GPIO_ACTIVE_LOW),\n+\t\tGPIO_LOOKUP_IDX(TINK_GPIO_DRIVER_NAME, 21,\n+\t\t\t\tNULL, 13, GPIO_ACTIVE_LOW),\n+\t\tGPIO_LOOKUP_IDX(TINK_GPIO_DRIVER_NAME, 19,\n+\t\t\t\tNULL, 14, GPIO_ACTIVE_LOW),\n+\t\t{} /* Terminating entry */\n+\t}\n+};\n+\n+/* Reset Button */\n+static struct gpio_keys_button tink_buttons[] = {\n+\t{\n+\t\t.desc\t\t\t= \"Reset\",\n+\t\t.type\t\t\t= EV_KEY,\n+\t\t.code\t\t\t= KEY_RESTART,\n+\t\t.active_low             = 1,\n+\t\t.debounce_interval      = 100,\n+\t},\n+};\n+\n+static const struct gpio_keys_platform_data tink_buttons_pdata = {\n+\t.buttons\t= tink_buttons,\n+\t.nbuttons\t= ARRAY_SIZE(tink_buttons),\n+\t.poll_interval  = 20,\n+\t.rep\t\t= 0,\n+\t.name\t\t= \"mx100-keys\",\n+};\n+\n+static struct gpiod_lookup_table tink_keys_table = {\n+\t.dev_id = \"gpio-keys-polled\",\n+\t.table = {\n+\t\tGPIO_LOOKUP_IDX(TINK_GPIO_DRIVER_NAME, 60,\n+\t\t\t\tNULL, 0, GPIO_ACTIVE_LOW),\n+\t\t{} /* Terminating entry */\n+\t}\n+};\n+\n+/* Board setup */\n+static const struct dmi_system_id tink_systems[] __initconst = {\n+\t{\n+\t\t.matches = {\n+\t\t\tDMI_EXACT_MATCH(DMI_SYS_VENDOR, \"Cisco\"),\n+\t\t\tDMI_EXACT_MATCH(DMI_PRODUCT_NAME, \"MX100-HW\"),\n+\t\t},\n+\t},\n+\t{} /* Terminating entry */\n+};\n+MODULE_DEVICE_TABLE(dmi, tink_systems);\n+\n+static struct platform_device *tink_leds_pdev;\n+static struct platform_device *tink_keys_pdev;\n+\n+static struct platform_device * __init tink_create_dev(\n+\tconst char *name, const void *pdata, size_t sz)\n+{\n+\tstruct platform_device *pdev;\n+\n+\tpdev = platform_device_register_data(NULL,\n+\t\tname, PLATFORM_DEVID_NONE, pdata, sz);\n+\tif (IS_ERR(pdev))\n+\t\tpr_err(\"failed registering %s: %ld\\n\", name, PTR_ERR(pdev));\n+\n+\treturn pdev;\n+}\n+\n+static int __init tink_board_init(void)\n+{\n+\tint ret;\n+\n+\tif (!dmi_first_match(tink_systems))\n+\t\treturn -ENODEV;\n+\n+\t/*\n+\t * We need to make sure that GPIO60 isn't set to native mode as is default since it's our\n+\t * Reset Button. To do this, write to GPIO_USE_SEL2 to have GPIO60 set to GPIO mode.\n+\t * This is documented on page 1609 of the PCH datasheet, order number 327879-005US\n+\t */\n+\toutl(inl(0x530) | BIT(28), 0x530);\n+\n+\tgpiod_add_lookup_table(&tink_leds_table);\n+\tgpiod_add_lookup_table(&tink_keys_table);\n+\n+\ttink_leds_pdev = tink_create_dev(\"leds-gpio\",\n+\t\t&tink_leds_pdata, sizeof(tink_leds_pdata));\n+\tif (IS_ERR(tink_leds_pdev)) {\n+\t\tret = PTR_ERR(tink_leds_pdev);\n+\t\tgoto err;\n+\t}\n+\n+\ttink_keys_pdev = tink_create_dev(\"gpio-keys-polled\",\n+\t\t&tink_buttons_pdata, sizeof(tink_buttons_pdata));\n+\tif (IS_ERR(tink_keys_pdev)) {\n+\t\tret = PTR_ERR(tink_keys_pdev);\n+\t\tplatform_device_unregister(tink_leds_pdev);\n+\t\tgoto err;\n+\t}\n+\n+\treturn 0;\n+\n+err:\n+\tgpiod_remove_lookup_table(&tink_keys_table);\n+\tgpiod_remove_lookup_table(&tink_leds_table);\n+\treturn ret;\n+}\n+module_init(tink_board_init);\n+\n+static void __exit tink_board_exit(void)\n+{\n+\tplatform_device_unregister(tink_keys_pdev);\n+\tplatform_device_unregister(tink_leds_pdev);\n+\tgpiod_remove_lookup_table(&tink_keys_table);\n+\tgpiod_remove_lookup_table(&tink_leds_table);\n+}\n+module_exit(tink_board_exit);\n+\n+MODULE_AUTHOR(\"Chris Blake <chrisrblake93@gmail.com>\");\n+MODULE_DESCRIPTION(\"Cisco Meraki MX100 Platform Driver\");\n+MODULE_LICENSE(\"GPL\");\n+MODULE_ALIAS(\"platform:meraki-mx100\");\n"
  },
  {
    "path": "target/linux/x86/patches-5.10/300-pcengines_apu1_led.patch",
    "content": "From: Andreas Eberlein <foodeas@aeberlein.de>\nSubject: x86: add LED support for PC Engines APU1 with mainline bios\n\nThis adds support for the LEDs on PC Engines APU1 with the mainline bios.\n\nSigned-off-by: Andreas Eberlein <foodeas@aeberlein.de>\n---\n--- a/drivers/leds/leds-apu.c\n+++ b/drivers/leds/leds-apu.c\n@@ -83,6 +83,7 @@ static const struct apu_led_profile apu1\n };\n \n static const struct dmi_system_id apu_led_dmi_table[] __initconst = {\n+\t/* PC Engines APU with \"Legacy\" bios < 4.0.8 */\n \t{\n \t\t.ident = \"apu\",\n \t\t.matches = {\n@@ -90,6 +91,14 @@ static const struct dmi_system_id apu_le\n \t\t\tDMI_MATCH(DMI_PRODUCT_NAME, \"APU\")\n \t\t}\n \t},\n+\t/* PC Engines APU with \"Mainline\" bios >= 4.0.8 */\n+\t{\n+\t\t.ident = \"apu\",\n+\t\t.matches = {\n+\t\t\tDMI_MATCH(DMI_SYS_VENDOR, \"PC Engines\"),\n+\t\t\tDMI_MATCH(DMI_PRODUCT_NAME, \"apu1\")\n+\t\t}\n+\t},\n \t{}\n };\n MODULE_DEVICE_TABLE(dmi, apu_led_dmi_table);\n@@ -173,7 +182,7 @@ static int __init apu_led_init(void)\n \tint err;\n \n \tif (!(dmi_match(DMI_SYS_VENDOR, \"PC Engines\") &&\n-\t      dmi_match(DMI_PRODUCT_NAME, \"APU\"))) {\n+\t      (dmi_match(DMI_PRODUCT_NAME, \"APU\") || dmi_match(DMI_PRODUCT_NAME, \"apu1\")))) {\n \t\tpr_err(\"No PC Engines APUv1 board detected. For APUv2,3 support, enable CONFIG_PCENGINES_APU2\\n\");\n \t\treturn -ENODEV;\n \t}\n"
  },
  {
    "path": "target/linux/x86/patches-5.15/100-fix_cs5535_clockevt.patch",
    "content": "--- a/drivers/clocksource/timer-cs5535.c\n+++ b/drivers/clocksource/timer-cs5535.c\n@@ -127,7 +127,9 @@ static irqreturn_t mfgpt_tick(int irq, v\n \t\tcs5535_mfgpt_write(cs5535_event_clock, MFGPT_REG_SETUP,\n \t\t\t\tMFGPT_SETUP_CNTEN | MFGPT_SETUP_CMP2);\n \n-\tcs5535_clockevent.event_handler(&cs5535_clockevent);\n+\tif (cs5535_clockevent.event_handler)\n+\t\tcs5535_clockevent.event_handler(&cs5535_clockevent);\n+\n \treturn IRQ_HANDLED;\n }\n \n"
  },
  {
    "path": "target/linux/zynq/Makefile",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2015 OpenWrt.org\n\ninclude $(TOPDIR)/rules.mk\n\nARCH:=arm\nBOARD:=zynq\nBOARDNAME:=Xilinx Zynq 7000 SoCs\nFEATURES:=fpu gpio rtc usb usbgadget boot-part rootfs-part squashfs\nCPU_TYPE:=cortex-a9\nCPU_SUBTYPE:=neon\n\n# future support SUBTARGETS: for both zynq and zynqmp\n\ndefine Target/Description\n\tBuild firmware image for Zynq 7000 SoC devices.\nendef\n\nKERNEL_PATCHVER:=5.10\n\ninclude $(INCLUDE_DIR)/target.mk\n\nKERNELNAME:=Image dtbs\n\nDEFAULT_PACKAGES += uboot-envtools mkf2fs e2fsprogs \\\n\tkmod-usb-storage kmod-fs-msdos\n\n$(eval $(call BuildTarget))\n"
  },
  {
    "path": "target/linux/zynq/base-files/etc/board.d/02_network",
    "content": "# Copyright (C) 2015 OpenWrt.org\n\n. /lib/functions/uci-defaults.sh\n\nboard_config_update\n\ncase \"$(board_name)\" in\navnet,zynq-zed | \\\ndigilent,zynq-zybo | \\\ndigilent,zynq-zybo-z7 | \\\nxlnx,zynq-zc702)\n\tucidef_set_interface_lan 'eth0'\n\t;;\n*)\n\techo \"Unsupported hardware. Network interfaces not intialized\"\n\t;;\nesac\n\nboard_config_flush\n\nexit 0\n"
  },
  {
    "path": "target/linux/zynq/base-files/etc/inittab",
    "content": "::sysinit:/etc/init.d/rcS S boot\n::shutdown:/etc/init.d/rcS K shutdown\n::askconsole:/usr/libexec/login.sh\n"
  },
  {
    "path": "target/linux/zynq/config-5.10",
    "content": "CONFIG_ALIGNMENT_TRAP=y\n# CONFIG_ALTERA_FREEZE_BRIDGE is not set\n# CONFIG_ALTERA_PR_IP_CORE is not set\nCONFIG_ARCH_32BIT_OFF_T=y\nCONFIG_ARCH_HIBERNATION_POSSIBLE=y\nCONFIG_ARCH_KEEP_MEMBLOCK=y\nCONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y\nCONFIG_ARCH_MULTIPLATFORM=y\nCONFIG_ARCH_MULTI_V6_V7=y\nCONFIG_ARCH_MULTI_V7=y\nCONFIG_ARCH_NR_GPIO=1024\nCONFIG_ARCH_OPTIONAL_KERNEL_RWX=y\nCONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y\nCONFIG_ARCH_SELECT_MEMORY_MODEL=y\nCONFIG_ARCH_SPARSEMEM_ENABLE=y\nCONFIG_ARCH_SUSPEND_POSSIBLE=y\nCONFIG_ARCH_VEXPRESS=y\nCONFIG_ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA=y\n# CONFIG_ARCH_VEXPRESS_SPC is not set\nCONFIG_ARCH_ZYNQ=y\nCONFIG_ARM=y\nCONFIG_ARM_AMBA=y\nCONFIG_ARM_CPU_SUSPEND=y\nCONFIG_ARM_ERRATA_643719=y\nCONFIG_ARM_ERRATA_720789=y\nCONFIG_ARM_ERRATA_754322=y\nCONFIG_ARM_ERRATA_754327=y\nCONFIG_ARM_ERRATA_764369=y\nCONFIG_ARM_ERRATA_775420=y\nCONFIG_ARM_GIC=y\nCONFIG_ARM_GLOBAL_TIMER=y\nCONFIG_ARM_HAS_SG_CHAIN=y\nCONFIG_ARM_HEAVY_MB=y\nCONFIG_ARM_L1_CACHE_SHIFT=6\nCONFIG_ARM_L1_CACHE_SHIFT_6=y\nCONFIG_ARM_PATCH_IDIV=y\nCONFIG_ARM_PATCH_PHYS_VIRT=y\n# CONFIG_ARM_PL172_MPMC is not set\n# CONFIG_ARM_SMMU is not set\nCONFIG_ARM_THUMB=y\nCONFIG_ARM_TIMER_SP804=y\nCONFIG_ARM_UNWIND=y\nCONFIG_ARM_VIRT_EXT=y\nCONFIG_ARM_ZYNQ_CPUIDLE=y\nCONFIG_ATAGS=y\nCONFIG_AUTO_ZRELADDR=y\n# CONFIG_AXI_DMAC is not set\nCONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y\nCONFIG_BLK_DEV_LOOP=y\nCONFIG_BLK_DEV_RAM=y\nCONFIG_BLK_DEV_RAM_COUNT=16\nCONFIG_BLK_DEV_RAM_SIZE=16384\nCONFIG_BLK_MQ_PCI=y\nCONFIG_BLK_PM=y\nCONFIG_BOUNCE=y\nCONFIG_CACHE_L2X0=y\nCONFIG_CADENCE_TTC_TIMER=y\nCONFIG_CADENCE_WATCHDOG=y\nCONFIG_CLKDEV_LOOKUP=y\nCONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK=y\nCONFIG_CLKSRC_MMIO=y\nCONFIG_CLKSRC_VERSATILE=y\nCONFIG_CLK_SP810=y\nCONFIG_CLK_VEXPRESS_OSC=y\nCONFIG_CLONE_BACKWARDS=y\nCONFIG_CMA=y\nCONFIG_CMA_ALIGNMENT=8\nCONFIG_CMA_AREAS=7\n# CONFIG_CMA_DEBUG is not set\n# CONFIG_CMA_DEBUGFS is not set\nCONFIG_CMA_SIZE_MBYTES=16\n# CONFIG_CMA_SIZE_SEL_MAX is not set\nCONFIG_CMA_SIZE_SEL_MBYTES=y\n# CONFIG_CMA_SIZE_SEL_MIN is not set\n# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set\nCONFIG_COMMON_CLK=y\n# CONFIG_COMMON_CLK_AXI_CLKGEN is not set\nCONFIG_COMMON_CLK_SI570=y\nCONFIG_COMPAT_32BIT_TIME=y\nCONFIG_CONNECTOR=y\nCONFIG_CONSOLE_TRANSLATIONS=y\nCONFIG_CONTIG_ALLOC=y\nCONFIG_COREDUMP=y\n# CONFIG_CPUFREQ_DT is not set\nCONFIG_CPU_32v6K=y\nCONFIG_CPU_32v7=y\nCONFIG_CPU_ABRT_EV7=y\nCONFIG_CPU_CACHE_V7=y\nCONFIG_CPU_CACHE_VIPT=y\nCONFIG_CPU_COPY_V6=y\nCONFIG_CPU_CP15=y\nCONFIG_CPU_CP15_MMU=y\nCONFIG_CPU_FREQ=y\n# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set\nCONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y\nCONFIG_CPU_FREQ_GOV_ATTR_SET=y\nCONFIG_CPU_FREQ_GOV_COMMON=y\nCONFIG_CPU_FREQ_GOV_CONSERVATIVE=y\nCONFIG_CPU_FREQ_GOV_ONDEMAND=y\nCONFIG_CPU_FREQ_GOV_PERFORMANCE=y\nCONFIG_CPU_FREQ_GOV_POWERSAVE=y\nCONFIG_CPU_FREQ_GOV_USERSPACE=y\nCONFIG_CPU_FREQ_STAT=y\nCONFIG_CPU_HAS_ASID=y\nCONFIG_CPU_IDLE=y\nCONFIG_CPU_IDLE_GOV_LADDER=y\nCONFIG_CPU_IDLE_GOV_MENU=y\nCONFIG_CPU_PABRT_V7=y\nCONFIG_CPU_PM=y\nCONFIG_CPU_RMAP=y\nCONFIG_CPU_SPECTRE=y\nCONFIG_CPU_THERMAL=y\nCONFIG_CPU_THUMB_CAPABLE=y\nCONFIG_CPU_TLB_V7=y\nCONFIG_CPU_V7=y\nCONFIG_CRC16=y\n# CONFIG_CRC32_SARWATE is not set\nCONFIG_CRC32_SLICEBY8=y\nCONFIG_CROSS_MEMORY_ATTACH=y\nCONFIG_CRYPTO_CRC32=y\nCONFIG_CRYPTO_CRC32C=y\nCONFIG_CRYPTO_HW=y\nCONFIG_CRYPTO_RNG2=y\nCONFIG_DCACHE_WORD_ACCESS=y\nCONFIG_DEBUG_LL_INCLUDE=\"mach/debug-macro.S\"\nCONFIG_DMADEVICES=y\nCONFIG_DMA_CMA=y\nCONFIG_DMA_ENGINE=y\nCONFIG_DMA_OF=y\nCONFIG_DMA_OPS=y\nCONFIG_DMA_REMAP=y\nCONFIG_DMA_SHARED_BUFFER=y\nCONFIG_DRM=y\nCONFIG_DRM_BRIDGE=y\nCONFIG_DRM_FBDEV_EMULATION=y\nCONFIG_DRM_FBDEV_OVERALLOC=100\nCONFIG_DRM_KMS_FB_HELPER=y\nCONFIG_DRM_KMS_HELPER=y\nCONFIG_DRM_PANEL=y\nCONFIG_DRM_PANEL_BRIDGE=y\nCONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y\nCONFIG_DTC=y\nCONFIG_DUMMY_CONSOLE=y\nCONFIG_E1000E=y\nCONFIG_EDAC=y\nCONFIG_EDAC_ATOMIC_SCRUB=y\n# CONFIG_EDAC_DEBUG is not set\nCONFIG_EDAC_LEGACY_SYSFS=y\nCONFIG_EDAC_SUPPORT=y\n# CONFIG_EDAC_SYNOPSYS is not set\nCONFIG_EEPROM_AT24=y\nCONFIG_EEPROM_AT25=y\nCONFIG_ELF_CORE=y\nCONFIG_ENABLE_MUST_CHECK=y\nCONFIG_EXT4_FS=y\nCONFIG_EXTCON=y\nCONFIG_F2FS_FS=y\nCONFIG_FB=y\nCONFIG_FB_CFB_COPYAREA=y\nCONFIG_FB_CFB_FILLRECT=y\nCONFIG_FB_CFB_IMAGEBLIT=y\nCONFIG_FB_CMDLINE=y\nCONFIG_FB_DEFERRED_IO=y\nCONFIG_FB_SYS_COPYAREA=y\nCONFIG_FB_SYS_FILLRECT=y\nCONFIG_FB_SYS_FOPS=y\nCONFIG_FB_SYS_IMAGEBLIT=y\n# CONFIG_FB_XILINX is not set\nCONFIG_FHANDLE=y\nCONFIG_FIXED_PHY=y\nCONFIG_FIX_EARLYCON_MEM=y\nCONFIG_FPGA=y\nCONFIG_FPGA_BRIDGE=y\n# CONFIG_FPGA_DFL is not set\n# CONFIG_FPGA_MGR_ALTERA_CVP is not set\n# CONFIG_FPGA_MGR_ALTERA_PS_SPI is not set\n# CONFIG_FPGA_MGR_ICE40_SPI is not set\n# CONFIG_FPGA_MGR_MACHXO2_SPI is not set\n# CONFIG_FPGA_MGR_XILINX_SPI is not set\nCONFIG_FPGA_MGR_ZYNQ_FPGA=y\nCONFIG_FPGA_REGION=y\nCONFIG_FREEZER=y\nCONFIG_FS_IOMAP=y\nCONFIG_FS_MBCACHE=y\nCONFIG_FW_CACHE=y\nCONFIG_FW_LOADER_PAGED_BUF=y\nCONFIG_GENERIC_ALLOCATOR=y\nCONFIG_GENERIC_ARCH_TOPOLOGY=y\nCONFIG_GENERIC_BUG=y\nCONFIG_GENERIC_CLOCKEVENTS=y\nCONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y\nCONFIG_GENERIC_CPU_AUTOPROBE=y\nCONFIG_GENERIC_EARLY_IOREMAP=y\nCONFIG_GENERIC_GETTIMEOFDAY=y\nCONFIG_GENERIC_IDLE_POLL_SETUP=y\nCONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y\nCONFIG_GENERIC_IRQ_MIGRATION=y\nCONFIG_GENERIC_IRQ_MULTI_HANDLER=y\nCONFIG_GENERIC_IRQ_SHOW=y\nCONFIG_GENERIC_IRQ_SHOW_LEVEL=y\nCONFIG_GENERIC_MSI_IRQ=y\nCONFIG_GENERIC_MSI_IRQ_DOMAIN=y\nCONFIG_GENERIC_PCI_IOMAP=y\nCONFIG_GENERIC_PINCONF=y\nCONFIG_GENERIC_SCHED_CLOCK=y\nCONFIG_GENERIC_SMP_IDLE_THREAD=y\nCONFIG_GENERIC_STRNCPY_FROM_USER=y\nCONFIG_GENERIC_STRNLEN_USER=y\nCONFIG_GENERIC_TIME_VSYSCALL=y\nCONFIG_GENERIC_VDSO_32=y\nCONFIG_GLOB=y\nCONFIG_GPIOLIB=y\nCONFIG_GPIOLIB_IRQCHIP=y\nCONFIG_GPIO_GENERIC=y\nCONFIG_GPIO_GENERIC_PLATFORM=y\nCONFIG_GPIO_ZYNQ=y\nCONFIG_HANDLE_DOMAIN_IRQ=y\nCONFIG_HARDEN_BRANCH_PREDICTOR=y\nCONFIG_HARDIRQS_SW_RESEND=y\nCONFIG_HAS_DMA=y\nCONFIG_HAS_IOMEM=y\nCONFIG_HAVE_SMP=y\nCONFIG_HDMI=y\nCONFIG_HID=y\nCONFIG_HID_GENERIC=y\nCONFIG_HID_MICROSOFT=y\nCONFIG_HIGHMEM=y\nCONFIG_HIGHPTE=y\nCONFIG_HOTPLUG_CPU=y\nCONFIG_HWMON=y\nCONFIG_HW_CONSOLE=y\nCONFIG_HZ_FIXED=0\nCONFIG_I2C=y\nCONFIG_I2C_ALGOBIT=y\nCONFIG_I2C_BOARDINFO=y\nCONFIG_I2C_CADENCE=y\nCONFIG_I2C_CHARDEV=y\nCONFIG_I2C_COMPAT=y\nCONFIG_I2C_HELPER_AUTO=y\nCONFIG_I2C_MUX=y\nCONFIG_I2C_MUX_PCA954x=y\nCONFIG_ICST=y\nCONFIG_IIO=y\nCONFIG_IIO_BUFFER=y\nCONFIG_IIO_KFIFO_BUF=y\nCONFIG_IIO_TRIGGER=y\nCONFIG_IIO_TRIGGERED_BUFFER=y\nCONFIG_IKCONFIG=y\nCONFIG_IKCONFIG_PROC=y\nCONFIG_INITRAMFS_SOURCE=\"\"\nCONFIG_INPUT=y\nCONFIG_INPUT_EVDEV=y\nCONFIG_INPUT_FF_MEMLESS=y\nCONFIG_INPUT_KEYBOARD=y\n# CONFIG_INPUT_MISC is not set\nCONFIG_INPUT_MOUSE=y\nCONFIG_INPUT_MOUSEDEV=y\nCONFIG_INPUT_MOUSEDEV_PSAUX=y\nCONFIG_INPUT_MOUSEDEV_SCREEN_X=1024\nCONFIG_INPUT_MOUSEDEV_SCREEN_Y=768\nCONFIG_INPUT_POLLDEV=y\nCONFIG_INPUT_SPARSEKMAP=y\n# CONFIG_IOMMU_DEBUGFS is not set\n# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set\n# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set\nCONFIG_IOMMU_SUPPORT=y\nCONFIG_IP_PNP=y\nCONFIG_IP_PNP_BOOTP=y\nCONFIG_IP_PNP_DHCP=y\nCONFIG_IP_PNP_RARP=y\nCONFIG_IRQCHIP=y\nCONFIG_IRQ_DOMAIN=y\nCONFIG_IRQ_DOMAIN_HIERARCHY=y\nCONFIG_IRQ_FORCED_THREADING=y\nCONFIG_IRQ_WORK=y\n# CONFIG_ISDN is not set\nCONFIG_JBD2=y\n# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set\nCONFIG_JFFS2_ZLIB=y\nCONFIG_KCMP=y\nCONFIG_KERNEL_GZIP=y\n# CONFIG_KERNEL_XZ is not set\nCONFIG_KEYBOARD_ATKBD=y\nCONFIG_KEYBOARD_GPIO=y\nCONFIG_KEYBOARD_GPIO_POLLED=y\nCONFIG_LEDS_GPIO=y\nCONFIG_LEDS_TRIGGER_BACKLIGHT=y\nCONFIG_LEDS_TRIGGER_CAMERA=y\nCONFIG_LEDS_TRIGGER_CPU=y\nCONFIG_LEDS_TRIGGER_GPIO=y\nCONFIG_LEDS_TRIGGER_ONESHOT=y\nCONFIG_LEDS_TRIGGER_TRANSIENT=y\nCONFIG_LIBFDT=y\nCONFIG_LOCK_DEBUGGING_SUPPORT=y\nCONFIG_LOCK_SPIN_ON_OWNER=y\nCONFIG_MACB=y\n# CONFIG_MACB_PCI is not set\nCONFIG_MACB_USE_HWSTAMP=y\nCONFIG_MARVELL_PHY=y\nCONFIG_MDIO_BITBANG=y\nCONFIG_MDIO_BUS=y\nCONFIG_MDIO_DEVICE=y\nCONFIG_MDIO_DEVRES=y\n# CONFIG_MDIO_GPIO is not set\nCONFIG_MEMFD_CREATE=y\nCONFIG_MEMORY=y\nCONFIG_MEMORY_ISOLATION=y\nCONFIG_MFD_CORE=y\nCONFIG_MFD_SYSCON=y\nCONFIG_MFD_VEXPRESS_SYSREG=y\nCONFIG_MIGHT_HAVE_CACHE_L2X0=y\nCONFIG_MIGRATION=y\nCONFIG_MMC=y\nCONFIG_MMC_BLOCK=y\nCONFIG_MMC_CQHCI=y\nCONFIG_MMC_SDHCI=y\nCONFIG_MMC_SDHCI_OF_ARASAN=y\n# CONFIG_MMC_SDHCI_PCI is not set\nCONFIG_MMC_SDHCI_PLTFM=y\nCONFIG_MODULES_USE_ELF_REL=y\nCONFIG_MODULE_FORCE_UNLOAD=y\n# CONFIG_MODULE_STRIPPED is not set\n# CONFIG_MOUSE_BCM5974 is not set\n# CONFIG_MOUSE_CYAPA is not set\nCONFIG_MOUSE_PS2=y\nCONFIG_MOUSE_PS2_ALPS=y\nCONFIG_MOUSE_PS2_BYD=y\nCONFIG_MOUSE_PS2_CYPRESS=y\n# CONFIG_MOUSE_PS2_ELANTECH is not set\nCONFIG_MOUSE_PS2_FOCALTECH=y\nCONFIG_MOUSE_PS2_LOGIPS2PP=y\nCONFIG_MOUSE_PS2_SMBUS=y\nCONFIG_MOUSE_PS2_SYNAPTICS=y\nCONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y\n# CONFIG_MOUSE_PS2_TOUCHKIT is not set\nCONFIG_MOUSE_PS2_TRACKPOINT=y\n# CONFIG_MOUSE_SERIAL is not set\n# CONFIG_MOUSE_VSXXXAA is not set\n# CONFIG_MTD_CFI_INTELEXT is not set\nCONFIG_MTD_CMDLINE_PARTS=y\n# CONFIG_MTD_COMPLEX_MAPPINGS is not set\nCONFIG_MTD_PHYSMAP=y\nCONFIG_MTD_SPI_NOR=y\nCONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y\nCONFIG_MTD_SPLIT_FIRMWARE=y\n# CONFIG_MTD_SPLIT_SQUASHFS_ROOT is not set\nCONFIG_MUTEX_SPIN_ON_OWNER=y\nCONFIG_NEED_DMA_MAP_STATE=y\nCONFIG_NEON=y\nCONFIG_NET_FLOW_LIMIT=y\nCONFIG_NET_PTP_CLASSIFY=y\n# CONFIG_NET_VENDOR_CIRRUS is not set\n# CONFIG_NET_VENDOR_FARADAY is not set\n# CONFIG_NET_VENDOR_MARVELL is not set\n# CONFIG_NET_VENDOR_MICREL is not set\n# CONFIG_NET_VENDOR_MICROCHIP is not set\n# CONFIG_NET_VENDOR_NATSEMI is not set\n# CONFIG_NET_VENDOR_SEEQ is not set\n# CONFIG_NET_VENDOR_SMSC is not set\n# CONFIG_NET_VENDOR_STMICRO is not set\n# CONFIG_NET_VENDOR_VIA is not set\nCONFIG_NLS=y\nCONFIG_NLS_ASCII=y\nCONFIG_NLS_CODEPAGE_437=y\nCONFIG_NLS_ISO8859_1=y\nCONFIG_NOP_USB_XCEIV=y\nCONFIG_NO_HZ=y\nCONFIG_NO_HZ_COMMON=y\nCONFIG_NO_HZ_IDLE=y\nCONFIG_NO_IOPORT_MAP=y\nCONFIG_NR_CPUS=4\nCONFIG_NVMEM=y\nCONFIG_NVMEM_SYSFS=y\nCONFIG_OF=y\nCONFIG_OF_ADDRESS=y\nCONFIG_OF_EARLY_FLATTREE=y\nCONFIG_OF_FLATTREE=y\n# CONFIG_OF_FPGA_REGION is not set\nCONFIG_OF_GPIO=y\nCONFIG_OF_IRQ=y\nCONFIG_OF_KOBJ=y\nCONFIG_OF_MDIO=y\nCONFIG_OF_NET=y\nCONFIG_OLD_SIGACTION=y\nCONFIG_OLD_SIGSUSPEND3=y\nCONFIG_OUTER_CACHE=y\nCONFIG_OUTER_CACHE_SYNC=y\nCONFIG_PADATA=y\nCONFIG_PAGE_OFFSET=0xC0000000\n# CONFIG_PARTITION_ADVANCED is not set\nCONFIG_PCI=y\nCONFIG_PCIE_XILINX=y\nCONFIG_PCI_DOMAINS=y\nCONFIG_PCI_DOMAINS_GENERIC=y\nCONFIG_PCI_MSI=y\nCONFIG_PCI_MSI_ARCH_FALLBACKS=y\nCONFIG_PCI_MSI_IRQ_DOMAIN=y\nCONFIG_PERF_USE_VMALLOC=y\nCONFIG_PGTABLE_LEVELS=2\nCONFIG_PHYLIB=y\nCONFIG_PHYLINK=y\nCONFIG_PINCTRL=y\n# CONFIG_PINCTRL_SINGLE is not set\nCONFIG_PINCTRL_ZYNQ=y\nCONFIG_PL310_ERRATA_588369=y\nCONFIG_PL310_ERRATA_727915=y\nCONFIG_PL310_ERRATA_753970=y\nCONFIG_PL310_ERRATA_769419=y\nCONFIG_PL330_DMA=y\n# CONFIG_PL353_SMC is not set\nCONFIG_PLAT_VERSATILE=y\nCONFIG_PM=y\nCONFIG_PMBUS=y\nCONFIG_PM_CLK=y\nCONFIG_PM_SLEEP=y\nCONFIG_PM_SLEEP_SMP=y\nCONFIG_POWER_RESET=y\nCONFIG_POWER_RESET_VEXPRESS=y\nCONFIG_POWER_SUPPLY=y\nCONFIG_PPS=y\nCONFIG_PROC_EVENTS=y\nCONFIG_PTP_1588_CLOCK=y\nCONFIG_R8169=y\nCONFIG_RAS=y\nCONFIG_RATIONAL=y\nCONFIG_REALTEK_PHY=y\nCONFIG_REGMAP=y\nCONFIG_REGMAP_I2C=y\nCONFIG_REGMAP_MMIO=y\nCONFIG_REGULATOR=y\nCONFIG_REGULATOR_FIXED_VOLTAGE=y\n# CONFIG_REGULATOR_VEXPRESS is not set\nCONFIG_RESET_CONTROLLER=y\nCONFIG_RESET_ZYNQ=y\nCONFIG_RFS_ACCEL=y\nCONFIG_RPS=y\nCONFIG_RTC_CLASS=y\nCONFIG_RTC_DRV_PCF8563=y\nCONFIG_RTC_I2C_AND_SPI=y\nCONFIG_RTC_MC146818_LIB=y\nCONFIG_RWSEM_SPIN_ON_OWNER=y\nCONFIG_SCHED_MC=y\nCONFIG_SCHED_SMT=y\nCONFIG_SENSORS_PMBUS=y\nCONFIG_SENSORS_UCD9000=y\nCONFIG_SENSORS_UCD9200=y\n# CONFIG_SERIAL_8250 is not set\nCONFIG_SERIAL_XILINX_PS_UART=y\nCONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y\nCONFIG_SERIO=y\nCONFIG_SERIO_LIBPS2=y\nCONFIG_SERIO_SERPORT=y\nCONFIG_SMP=y\nCONFIG_SMP_ON_UP=y\nCONFIG_SOC_BUS=y\nCONFIG_SPARSE_IRQ=y\nCONFIG_SPI=y\nCONFIG_SPI_BITBANG=y\nCONFIG_SPI_CADENCE=y\nCONFIG_SPI_MASTER=y\nCONFIG_SPI_MEM=y\nCONFIG_SPI_XILINX=y\nCONFIG_SPI_ZYNQ_QSPI=y\nCONFIG_SRAM=y\nCONFIG_SRAM_EXEC=y\nCONFIG_SRCU=y\n# CONFIG_STRIP_ASM_SYMS is not set\nCONFIG_SUSPEND=y\nCONFIG_SUSPEND_FREEZER=y\nCONFIG_SWPHY=y\nCONFIG_SWP_EMULATE=y\nCONFIG_SYNC_FILE=y\nCONFIG_SYSFS_SYSCALL=y\nCONFIG_SYS_SUPPORTS_APM_EMULATION=y\n# CONFIG_TEXTSEARCH is not set\nCONFIG_THERMAL=y\nCONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y\nCONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0\nCONFIG_THERMAL_GOV_STEP_WISE=y\nCONFIG_THERMAL_HWMON=y\nCONFIG_THERMAL_OF=y\nCONFIG_TICK_CPU_ACCOUNTING=y\nCONFIG_TIMER_OF=y\nCONFIG_TIMER_PROBE=y\nCONFIG_TREE_RCU=y\nCONFIG_TREE_SRCU=y\nCONFIG_UIO=y\n# CONFIG_UIO_AEC is not set\n# CONFIG_UIO_CIF is not set\n# CONFIG_UIO_DMEM_GENIRQ is not set\n# CONFIG_UIO_MF624 is not set\n# CONFIG_UIO_NETX is not set\n# CONFIG_UIO_PCI_GENERIC is not set\nCONFIG_UIO_PDRV_GENIRQ=y\n# CONFIG_UIO_PRUSS is not set\n# CONFIG_UIO_SERCOS3 is not set\nCONFIG_UNCOMPRESS_INCLUDE=\"debug/uncompress.h\"\nCONFIG_UNWINDER_ARM=y\nCONFIG_USB=y\nCONFIG_USB_CHIPIDEA=y\nCONFIG_USB_CHIPIDEA_HOST=y\nCONFIG_USB_CHIPIDEA_UDC=y\nCONFIG_USB_COMMON=y\nCONFIG_USB_EHCI_HCD=y\n# CONFIG_USB_EHCI_HCD_PLATFORM is not set\n# CONFIG_USB_EHCI_TT_NEWSCHED is not set\nCONFIG_USB_GADGET=y\nCONFIG_USB_GADGET_XILINX=y\nCONFIG_USB_HID=y\nCONFIG_USB_NET_DRIVERS=y\nCONFIG_USB_OTG=y\nCONFIG_USB_OTG_FSM=y\nCONFIG_USB_PHY=y\nCONFIG_USB_ROLE_SWITCH=y\nCONFIG_USB_SUPPORT=y\nCONFIG_USB_ULPI=y\nCONFIG_USB_ULPI_BUS=y\nCONFIG_USB_ULPI_VIEWPORT=y\nCONFIG_USE_OF=y\nCONFIG_VEXPRESS_CONFIG=y\nCONFIG_VFP=y\nCONFIG_VFPv3=y\nCONFIG_VGA_ARB=y\nCONFIG_VGA_ARB_MAX_GPUS=16\nCONFIG_VITESSE_PHY=y\nCONFIG_VM_EVENT_COUNTERS=y\nCONFIG_VT=y\nCONFIG_VT_CONSOLE=y\nCONFIG_VT_CONSOLE_SLEEP=y\n# CONFIG_VT_HW_CONSOLE_BINDING is not set\nCONFIG_WATCHDOG_CORE=y\n# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set\nCONFIG_XILINX_EMACLITE=y\n# CONFIG_XILINX_PR_DECOUPLER is not set\nCONFIG_XILINX_WATCHDOG=y\nCONFIG_XILINX_XADC=y\nCONFIG_XPS=y\nCONFIG_XZ_DEC_ARM=y\nCONFIG_XZ_DEC_ARMTHUMB=y\nCONFIG_XZ_DEC_BCJ=y\nCONFIG_XZ_DEC_IA64=y\nCONFIG_XZ_DEC_POWERPC=y\nCONFIG_XZ_DEC_SPARC=y\nCONFIG_XZ_DEC_X86=y\nCONFIG_ZBOOT_ROM_BSS=0x0\nCONFIG_ZBOOT_ROM_TEXT=0x0\nCONFIG_ZLIB_DEFLATE=y\nCONFIG_ZLIB_INFLATE=y\n"
  },
  {
    "path": "target/linux/zynq/image/Makefile",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\n#\n# Copyright (C) 2015 OpenWrt.org\n\ninclude $(TOPDIR)/rules.mk\ninclude $(INCLUDE_DIR)/image.mk\n\nFAT32_BLOCK_SIZE=1024\nFAT32_BLOCKS=$(shell echo $$(($(CONFIG_TARGET_KERNEL_PARTSIZE)*1024*1024/$(FAT32_BLOCK_SIZE))))\n\ndefine Build/zynq-sdcard\n\trm -f $@.boot\n\tmkfs.fat $@.boot -C $(FAT32_BLOCKS)\n\tmcopy -i $@.boot $(STAGING_DIR_IMAGE)/$(DEVICE_NAME)-boot.bin ::boot.bin\n\tmcopy -i $@.boot $(STAGING_DIR_IMAGE)/$(DEVICE_NAME)-u-boot.img ::u-boot.img\n\tmcopy -i $@.boot $(STAGING_DIR_IMAGE)/$(DEVICE_NAME)-uEnv.txt ::uEnv.txt\n\tmcopy -i $@.boot $(IMAGE_KERNEL) ::fit.itb\n\t./gen_zynq_sdcard_img.sh $@ \\\n\t\t$@.boot \\\n\t\t$(IMAGE_ROOTFS) \\\n\t\t$(CONFIG_TARGET_KERNEL_PARTSIZE) \\\n\t\t$(CONFIG_TARGET_ROOTFS_PARTSIZE)\n\trm -f $@.boot\nendef\n\n#################################################\n# Default and templates\n#################################################\n\ndefine Device/Default\n\tPROFILES := Default\n\tDEVICE_DTS := $(lastword $(subst _, ,$(1)))\n\tKERNEL_DEPENDS = $$(wildcard $(DTS_DIR)/$$(DEVICE_DTS).dts)\n\tKERNEL_LOADADDR := 0x8000\n\tIMAGES := sdcard.img.gz\n\tIMAGE/sdcard.img.gz := zynq-sdcard | gzip\nendef\n\ndefine Device/FitImageGzip\n\tKERNEL_SUFFIX := -fit-uImage.itb\n\tKERNEL = kernel-bin | gzip | fit gzip $$(DTS_DIR)/$$(DEVICE_DTS).dtb\n\tKERNEL_NAME := Image\nendef\n\n#################################################\n# Devices\n#################################################\n\ndefine Device/avnet_zynq-zed\n\t$(call Device/FitImageGzip)\n\tDEVICE_VENDOR := Avnet\n\tDEVICE_MODEL := ZedBoard\nendef\nTARGET_DEVICES += avnet_zynq-zed\n\ndefine Device/digilent_zynq-zybo\n\t$(call Device/FitImageGzip)\n\tDEVICE_VENDOR := Digilent\n\tDEVICE_MODEL := Zybo\nendef\nTARGET_DEVICES += digilent_zynq-zybo\n\ndefine Device/digilent_zynq-zybo-z7\n\t$(call Device/FitImageGzip)\n\tDEVICE_VENDOR := Digilent\n\tDEVICE_MODEL := Zybo Z7\nendef\nTARGET_DEVICES += digilent_zynq-zybo-z7\n\ndefine Device/xlnx_zynq-zc702\n\t$(call Device/FitImageGzip)\n\tDEVICE_VENDOR := Xilinx\n\tDEVICE_MODEL := ZC702\n\tDEVICE_PACKAGES:=kmod-can kmod-can-xilinx-can\nendef\nTARGET_DEVICES += xlnx_zynq-zc702\n\n$(eval $(call BuildImage))\n"
  },
  {
    "path": "target/linux/zynq/image/gen_zynq_sdcard_img.sh",
    "content": "#!/bin/sh\n\nset -ex\n[ $# -eq 5 ] || {\n    echo \"SYNTAX: $0 <file> <bootfs image> <rootfs image> <bootfs size> <rootfs size>\"\n    exit 1\n}\n\nOUTPUT=\"$1\"\nBOOTFS=\"$2\"\nROOTFS=\"$3\"\nBOOTFSSIZE=\"$4\"\nROOTFSSIZE=\"$5\"\n\nhead=4\nsect=63\n\nset $(ptgen -o $OUTPUT -h $head -s $sect -l 1024 -t c -p ${BOOTFSSIZE}M -t 83 -p ${ROOTFSSIZE}M)\n\nBOOTOFFSET=\"$(($1 / 512))\"\nBOOTSIZE=\"$(($2 / 512))\"\nROOTFSOFFSET=\"$(($3 / 512))\"\nROOTFSSIZE=\"$(($4 / 512))\"\n\ndd bs=512 if=\"$BOOTFS\" of=\"$OUTPUT\" seek=\"$BOOTOFFSET\" conv=notrunc\ndd bs=512 if=\"$ROOTFS\" of=\"$OUTPUT\" seek=\"$ROOTFSOFFSET\" conv=notrunc\n"
  },
  {
    "path": "target/llvm-bpf/Makefile",
    "content": "#\n# Copyright (C) 2021 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\noverride MAKEFLAGS=\n\nLLVM_VERSION := $(shell cat $(STAGING_DIR_HOST)/llvm-bpf/.llvm-version)\n\nLLVM_BPF_PREFIX := llvm-bpf-$(LLVM_VERSION).$(HOST_OS)-$(HOST_ARCH)\nLLVM_TAR := $(BIN_DIR)/$(LLVM_BPF_PREFIX).tar.xz\n\n$(LLVM_TAR): $(STAGING_DIR_HOST)/llvm-bpf/.llvm-version\n\ttar -C $(STAGING_DIR_HOST) \\\n\t\t-I '$(STAGING_DIR_HOST)/bin/xz -7e -T$(if $(filter 1,$(NPROC)),2,0)' \\\n\t\t$(if $(SOURCE_DATE_EPOCH),--mtime=\"@$(SOURCE_DATE_EPOCH)\") \\\n\t\t-cf $@.tmp llvm-bpf $(LLVM_BPF_PREFIX)\n\tmv $@.tmp $@\n\ndownload:\nprepare:\ncompile: $(LLVM_TAR)\ninstall: compile\n\nclean:\n\trm -f $(LLVM_TAR)\n"
  },
  {
    "path": "target/sdk/Config.in",
    "content": "config SDK\n\tbool \"Build the OpenWrt SDK\"\n\tdepends on !EXTERNAL_TOOLCHAIN\n\tdefault BUILDBOT\n\thelp\n\t  This is essentially a stripped-down version of the buildroot\n\t  with a precompiled toolchain. It can be used to develop and\n\t  test packages for OpenWrt before including them in the buildroot\n\nconfig SDK_LLVM_BPF\n\tbool \"Build the LLVM-BPF toolchain tarball\"\n\tdepends on BPF_TOOLCHAIN_BUILD_LLVM\n\tdefault BUILDBOT\n\thelp\n\t  This is a tarball of the precompiled LLVM toolchain suitable\n\t  for unpacking into the buildroot/SDK. It is used to build packages\n\t  that ship with eBPF kernel modules\n"
  },
  {
    "path": "target/sdk/Makefile",
    "content": "# \n# Copyright (C) 2006-2014 OpenWrt.org\n# Copyright (C) 2016 LEDE Project\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\ninclude $(INCLUDE_DIR)/kernel.mk\ninclude $(INCLUDE_DIR)/version.mk\ninclude $(INCLUDE_DIR)/download.mk\n\noverride MAKEFLAGS=\n\nSDK_NAME:=$(VERSION_DIST_SANITIZED)-sdk-$(if $(CONFIG_VERSION_FILENAMES),$(VERSION_NUMBER)-)$(BOARD)$(if $(SUBTARGET),-$(SUBTARGET))$(if $(GCCV),_gcc-$(GCCV))$(DIR_SUFFIX).$(HOST_OS)-$(HOST_ARCH)\nSDK_BUILD_DIR:=$(BUILD_DIR)/$(SDK_NAME)\n\nSTAGING_SUBDIR_HOST := staging_dir/host\nSTAGING_SUBDIR_TARGET := staging_dir/$(TARGET_DIR_NAME)\nSTAGING_SUBDIR_TOOLCHAIN := staging_dir/toolchain-$(ARCH)$(ARCH_SUFFIX)_gcc-$(GCCV)_$(LIBC)$(if $(CONFIG_arm),_eabi)\n\nBUNDLER_PATH := $(subst $(space),:,$(filter-out $(TOPDIR)/%,$(subst :,$(space),$(PATH))))\nBUNDLER_COMMAND := PATH=$(BUNDLER_PATH) $(XARGS) $(SCRIPT_DIR)/bundle-libraries.sh $(SDK_BUILD_DIR)/$(STAGING_SUBDIR_HOST)\n\nEXCLUDE_DIRS:= \\\n\t*/stamp \\\n\t*/stampfiles \\\n\t*/man \\\n\t*/info \\\n\t*/root-* \\\n\tinitial \\\n\t*.install.clean \\\n\t*.install.flags \\\n\t*.install \\\n\t*/doc \\\n\t*/share/locale\n\nSDK_DIRS = \\\n\t\t$(STAGING_SUBDIR_HOST) \\\n\t\t$(STAGING_SUBDIR_TOOLCHAIN)\n\nGIT_URL:=$(shell git config --get remote.origin.url 2>/dev/null)\nGIT_URL:=$(if $(CONFIG_BUILDBOT),$(filter git://% http://% https://%,$(GIT_URL)),$(GIT_URL))\nGIT_COMMIT:=$(shell git rev-parse HEAD 2>/dev/null)\nGIT_BRANCH:=$(filter-out master HEAD,$(shell git rev-parse --abbrev-ref HEAD 2>/dev/null))\nGIT_TAGNAME:=$(shell git show-ref --tags --dereference 2>/dev/null | sed -ne '/^$(GIT_COMMIT) / { s|^.*/||; s|\\^.*||; p }')\n\nBASE_FEED:=$(if $(GIT_URL),src-git base $(GIT_URL)$(if $(GIT_BRANCH),;$(GIT_BRANCH),$(if $(GIT_TAGNAME),;$(GIT_TAGNAME))))\nBASE_FEED:=$(if $(BASE_FEED),$(BASE_FEED),$(shell cd $(TOPDIR); LC_ALL=C git svn info 2>/dev/null | sed -ne 's/^URL: /src-gitsvn base /p'))\nBASE_FEED:=$(if $(BASE_FEED),$(BASE_FEED),$(shell cd $(TOPDIR); LC_ALL=C svn info 2>/dev/null | sed -ne 's/^URL: /src-svn base /p'))\nBASE_FEED:=$(if $(BASE_FEED),$(BASE_FEED),src-git base $(PROJECT_GIT)/openwrt/openwrt.git$(if $(GIT_BRANCH),;$(GIT_BRANCH),$(if $(GIT_TAGNAME),;$(GIT_TAGNAME))))\n\nKDIR_BASE = $(patsubst $(TOPDIR)/%,%,$(LINUX_DIR))\nKDIR_ARCHES = $(LINUX_KARCH)\n\n# arch/arm64/ includes reference files in arch/arm/, so we'll need both\nifeq ($(LINUX_KARCH),arm64)\n  KDIR_ARCHES += arm\nendif\n\nKERNEL_FILES_ARCH = \\\n\tMakefile* \\\n\tmodule.lds \\\n\tKbuild.platforms \\\n\t*/Platform \\\n\tinclude \\\n\t*/include \\\n\tscripts \\\n\tkernel/asm-offsets.s \\\n\tkernel/module.lds\n\nKERNEL_FILES_BASE := \\\n\t.config \\\n\tMakefile \\\n\tscripts \\\n\ttools/objtool \\\n\tinclude \\\n\tModule.symvers \\\n\tmodules.builtin \\\n\t$(foreach arch,$(KDIR_ARCHES),$(addprefix arch/$(arch)/,$(KERNEL_FILES_ARCH)))\n\nKERNEL_FILES := $(patsubst $(TOPDIR)/%,%,$(wildcard $(addprefix $(LINUX_DIR)/,$(KERNEL_FILES_BASE))))\n\nall: compile\n\n$(BIN_DIR)/$(SDK_NAME).tar.xz: clean\n\tmkdir -p \\\n\t\t$(SDK_BUILD_DIR)/dl \\\n\t\t$(SDK_BUILD_DIR)/package \\\n\t\t$(SDK_BUILD_DIR)/$(STAGING_SUBDIR_TARGET)/include \\\n\t\t$(SDK_BUILD_DIR)/$(STAGING_SUBDIR_TARGET)/usr/include\n\n\t$(CP) -L $(INCLUDE_DIR) $(SCRIPT_DIR) $(SDK_BUILD_DIR)/\n\t$(TAR) -cf - -C $(TOPDIR) \\\n\t\t`cd $(TOPDIR); find $(KDIR_BASE)/ -name \\*.ko` \\\n\t\t`cd $(TOPDIR); find $(KDIR_BASE)/firmware/ -newer $(KDIR_BASE)/firmware/Makefile \\\n\t\t\t-type f -name '*.bin' -or -name '*.cis' -or -name '*.csp' -or -name '*.dsp' -or -name '*.fw'` \\\n\t\t$(foreach exclude,$(EXCLUDE_DIRS),--exclude=\"$(exclude)\") \\\n\t\t$(SDK_DIRS) $(KERNEL_FILES) | \\\n\t\t$(TAR) -xf - -C $(SDK_BUILD_DIR)\n\n\t# Copy usbip sources, this is required for the usbip userspace packages to be buildable by the SDK.\n\t$(TAR) -cf - -C $(TOPDIR) $(KDIR_BASE)/tools/usb/usbip/ | \\\n\t\t$(TAR) -xf - -C $(SDK_BUILD_DIR)\n\n\t(cd $(SDK_BUILD_DIR); find $(STAGING_SUBDIR_HOST)/bin $(STAGING_SUBDIR_HOST)/usr/bin \\\n\t\t$(STAGING_SUBDIR_TOOLCHAIN)/bin $(STAGING_SUBDIR_TOOLCHAIN)/*/bin $(STAGING_SUBDIR_TOOLCHAIN)/libexec \\\n\t\t$(KDIR_BASE) \\\n\t\t-type f | $(BUNDLER_COMMAND))\n\n\t@-( \\\n\t\tfind \\\n\t\t\t$(SDK_BUILD_DIR)/$(STAGING_SUBDIR_HOST)/bin \\\n\t\t\t$(SDK_BUILD_DIR)/$(STAGING_SUBDIR_HOST)/usr/bin \\\n\t\t\t$(SDK_BUILD_DIR)/$(STAGING_SUBDIR_TOOLCHAIN)/bin \\\n\t\t\t$(SDK_BUILD_DIR)/$(STAGING_SUBDIR_TOOLCHAIN)/*/bin \\\n\t\t\t$(SDK_BUILD_DIR)/$(STAGING_SUBDIR_TOOLCHAIN)/libexec \\\n\t\t\t-type f; \\\n\t\tfind \\\n\t\t\t$(SDK_BUILD_DIR)/$(STAGING_SUBDIR_HOST)/lib \\\n\t\t\t$(SDK_BUILD_DIR)/$(STAGING_SUBDIR_HOST)/usr/lib \\\n\t\t\t-type f -name \\*.so\\*; \\\n\t) | xargs strip 2>/dev/null >/dev/null\n\n\tmkdir -p $(SDK_BUILD_DIR)/target/linux\n\t$(CP) $(GENERIC_PLATFORM_DIR) $(PLATFORM_DIR) $(SDK_BUILD_DIR)/target/linux/\n\trm -rf \\\n\t\t$(SDK_BUILD_DIR)/target/linux/*/files* \\\n\t\t$(SDK_BUILD_DIR)/target/linux/*/patches*\n\t./convert-config.pl $(TOPDIR)/.config > $(SDK_BUILD_DIR)/Config-build.in\n\t$(CP) -L \\\n\t\t$(TOPDIR)/LICENSES \\\n\t\t$(TOPDIR)/COPYING \\\n\t\t$(TOPDIR)/rules.mk \\\n\t\t./files/Config.in \\\n\t\t./files/Makefile \\\n\t\t./files/include/prepare.mk \\\n\t\t./files/README.SDK \\\n\t\t$(SDK_BUILD_DIR)/\n\tmkdir -p $(SDK_BUILD_DIR)/package/kernel\n\t$(CP) \\\n\t\t$(TOPDIR)/package/Makefile \\\n\t\t$(TOPDIR)/package/libs/toolchain \\\n\t\t$(SDK_BUILD_DIR)/package/\n\t$(CP) \\\n\t\t$(TOPDIR)/package/kernel/linux \\\n\t\t$(SDK_BUILD_DIR)/package/kernel/\n\n\t-rm -rf $(SDK_BUILD_DIR)/$(STAGING_SUBDIR_HOST)/.prereq-build\n\n\t-rm -f $(SDK_BUILD_DIR)/feeds.conf.default\n\t$(if $(BASE_FEED),echo \"$(BASE_FEED)\" > $(SDK_BUILD_DIR)/feeds.conf.default)\n\tif [ -f $(TOPDIR)/feeds.conf ]; then \\\n\t\tcat $(TOPDIR)/feeds.conf >> $(SDK_BUILD_DIR)/feeds.conf.default; \\\n\telse \\\n\t\tcat $(TOPDIR)/feeds.conf.default >> $(SDK_BUILD_DIR)/feeds.conf.default; \\\n\tfi\n\t$(SED) 's,^# REVISION:=.*,REVISION:=$(REVISION),g' $(SDK_BUILD_DIR)/include/version.mk\n\t$(SED) 's,^# SOURCE_DATE_EPOCH:=.*,SOURCE_DATE_EPOCH:=$(SOURCE_DATE_EPOCH),g' $(SDK_BUILD_DIR)/include/version.mk\n\t$(SED) '/LINUX_VERMAGIC:=/ { s,unknown,$(LINUX_VERMAGIC),g }' $(SDK_BUILD_DIR)/include/kernel.mk\n\tfind $(SDK_BUILD_DIR) -name .git | $(XARGS) rm -rf\n\tfind $(SDK_BUILD_DIR) -name .svn | $(XARGS) rm -rf\n\tfind $(SDK_BUILD_DIR) -name CVS | $(XARGS) rm -rf\n\t-make -C $(SDK_BUILD_DIR)/scripts/config clean\n\t(cd $(BUILD_DIR); \\\n\t\ttar -I '$(STAGING_DIR_HOST)/bin/xz -7e -T$(if $(filter 1,$(NPROC)),2,0)' -cf $@ $(SDK_NAME) \\\n\t\t--mtime=\"$(shell date --date=@$(SOURCE_DATE_EPOCH))\"; \\\n\t)\n\ndownload:\nprepare:\ncompile: $(BIN_DIR)/$(SDK_NAME).tar.xz\ninstall: compile\n\nclean:\n\trm -rf $(SDK_BUILD_DIR) $(BIN_DIR)/$(SDK_NAME).tar.xz\n"
  },
  {
    "path": "target/sdk/convert-config.pl",
    "content": "#!/usr/bin/env perl\nuse strict;\n\nwhile (<>) {\n\tmy $match;\n\tmy $var;\n\tmy $val;\n\tmy $type;\n\tchomp;\n\tnext if /^CONFIG_SIGNED_PACKAGES/;\n\n\tif (/^CONFIG_((BINARY)|(DOWNLOAD))_FOLDER=(.*)$/) {\n\t\t# We don't want to preserve the build setting of\n\t\t# BINARY_FOLDER and DOWNLOAD_FOLDER.\n\t\t$var = \"$1_FOLDER\";\n\t\t$val = '\"\"';\n\t\t$type = \"string\";\n\t} elsif (/^CONFIG_([^=]+)=(.*)$/) {\n\t\t$var = $1;\n\t\t$val = $2;\n\n\t\tnext if $var eq 'ALL';\n\n\t\tif ($val eq 'y') {\n\t\t\t$type = \"bool\";\n\t\t} elsif ($val eq 'm') {\n\t\t\t$type = \"tristate\";\n\t\t} elsif ($val =~ /^\".*\"$/) {\n\t\t\t$type = \"string\";\n\t\t} elsif ($val =~ /^\\d+$/) {\n\t\t\t$type = \"int\";\n\t\t} else {\n\t\t\twarn \"WARNING: no type found for symbol CONFIG_$var=$val\\n\";\n\t\t\tnext;\n\t\t}\n\t} elsif (/^# CONFIG_BUSYBOX_(.*) is not set/) {\n\t\t$var = \"BUSYBOX_$1\";\n\t\t$val = 'n';\n\t\t$type = \"bool\";\n\t} else {\n\t\t# We don't want to preserve a record of deselecting\n\t\t# packages because we may want build them in the SDK.\n\t\t# non-package configs however may be important to preserve\n\t\t# the same compilation settings for packages that get\n\t\t# recompiled in the SDK.\n\t\t# Also we want avoid preserving image generation settings\n\t\t# because we set those while in ImageBuilder\n\t\tnext if /^(# )?CONFIG_PACKAGE/;\n\t\tnext if /^(# )?CONFIG_TARGET/;\n\t\tif (/^# CONFIG_(.*) is not set/) {\n\t\t\t$var = $1;\n\t\t\t$val = 'n';\n\t\t\t$type = \"bool\";\n                }\n\t}\n\n\tif (($var ne '') && ($type ne '') && ($val ne '')) {\n\t\tprint <<EOF;\nconfig $var\n\t$type\n\tdefault $val\n\nEOF\n\t}\n}\n"
  },
  {
    "path": "target/sdk/files/Config.in",
    "content": "mainmenu \"OpenWrt Configuration\"\n\nmenu \"Global build settings\"\n\n\tconfig ALL_NONSHARED\n\t\tbool \"Select all target specific packages by default\"\n\t\tdefault ALL\n\n\tconfig ALL_KMODS\n\t\tbool \"Select all kernel module packages by default\"\n\t\tdefault ALL\n\n\tconfig ALL\n\t\tbool \"Select all userspace packages by default\"\n\t\tdefault y\n\n\tconfig SIGNED_PACKAGES\n\t\tbool \"Cryptographically sign package lists\"\n\t\tdefault y\n\n\tcomment \"Package build options\"\n\n\tconfig DEBUG\n\t\tbool\n\t\tprompt \"Compile packages with debugging info\"\n\t\tdefault n\n\t\thelp\n\t\t  Adds -g3 to the CFLAGS.\n\n\tcomment \"Stripping options\"\n\n\tchoice\n\t\tprompt \"Binary stripping method\"\n\t\tdefault USE_STRIP   if EXTERNAL_TOOLCHAIN\n\t\tdefault USE_STRIP   if USE_GLIBC\n\t\tdefault USE_SSTRIP\n\t\thelp\n\t\t  Select the binary stripping method you wish to use.\n\n\t\tconfig NO_STRIP\n\t\t\tbool \"none\"\n\t\t\thelp\n\t\t\t  This will install unstripped binaries (useful for native\n\t\t\t  compiling/debugging).\n\n\t\tconfig USE_STRIP\n\t\t\tbool \"strip\"\n\t\t\thelp\n\t\t\t  This will install binaries stripped using strip from binutils.\n\n\t\tconfig USE_SSTRIP\n\t\t\tbool \"sstrip\"\n\t\t\tdepends on !USE_GLIBC\n\t\t\thelp\n\t\t\t  This will install binaries stripped using sstrip.\n\tendchoice\n\n\tconfig STRIP_ARGS\n\t\tstring\n\t\tprompt \"Strip arguments\"\n\t\tdepends on USE_STRIP\n\t\tdefault \"--strip-unneeded --remove-section=.comment --remove-section=.note\" if DEBUG\n\t\tdefault \"--strip-all\"\n\t\thelp\n\t\t  Specifies arguments passed to the strip command when stripping binaries.\n\nendmenu\n\nmenu \"Advanced configuration options (for developers)\"\n\n\tconfig BROKEN\n\t\tbool \"Show broken packages\"\n\t\tdefault n\n\n\tconfig DOWNLOAD_FOLDER\n\t\tstring \"Download folder\"\n\t\tdefault \"\"\n\t\thelp\n\t\t  Store downloaded source bundles in this directory.\n\t\t  If not set then defaults to './dl', which is removed by operations such as\n\t\t  'git clean -xdf' or 'make distclean'.\n\t\t  This option is useful if you have a low bandwidth Internet connection, and by\n\t\t  setting a path outside the OpenWrt tree downloads will be saved.\n\n\tconfig LOCALMIRROR\n\t\tstring \"Local mirror for source packages\"\n\t\tdefault \"\"\n\n\tconfig AUTOREBUILD\n\t\tbool \"Automatic rebuild of packages\"\n\t\tdefault y\n\t\thelp\n\t\t  Automatically rebuild packages when their files change.\n\n\tconfig AUTOREMOVE\n\t\tbool \"Automatic removal of build directories\"\n\t\tdefault y\n\t\thelp\n\t\t  Automatically delete build directories after make target completed.\n\t\t  This allows you to symlink build_dir into a scratch location, e.g. a ramdisk,\n\t\t  which does not have enough space to keep a complete build_dir.\n\n\tconfig CCACHE\n\t\tbool \"Use ccache\"\n\t\tdefault n\n\t\thelp\n\t\t  Compiler cache; see https://ccache.samba.org/\n\n\tconfig BUILD_LOG\n\t\tbool \"Enable log files during build process\"\n\t\tdefault n\n\t\thelp\n\t\t  If enabled, log files will be written to the ./log directory.\n\n\tconfig SRC_TREE_OVERRIDE\n\t\tbool \"Enable package source tree override\"\n\t\tdefault n\n\t\thelp\n\t\t  If enabled, you can force a package to use a git tree as source\n\t\t  code instead of the normal tarball. Create a symlink 'git-src'\n\t\t  in the package directory, pointing to the .git tree that you want\n\t\t  to pull the source code from.\n\nendmenu\n\nconfig IN_SDK\n\tdefault y\n\tbool\n\nconfig MODULES\n\tbool\n\tdefault y\n\tmodules\n\nsource \"Config-build.in\"\nsource \"tmp/.config-package.in\"\n"
  },
  {
    "path": "target/sdk/files/Makefile",
    "content": "# Makefile for OpenWrt\n#\n# Copyright (C) 2007-2015 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\nTOPDIR:=${CURDIR}\nLC_ALL:=C\nLANG:=C\nSDK:=1\nexport TOPDIR LC_ALL LANG SDK\n\nworld:\n\nDISTRO_PKG_CONFIG:=$(shell $(TOPDIR)/scripts/command_all.sh pkg-config | grep -E '\\/usr' | head -n 1)\nexport PATH:=$(TOPDIR)/staging_dir/host/bin:$(PATH)\n\nifneq ($(OPENWRT_BUILD),1)\n  override OPENWRT_BUILD=1\n  export OPENWRT_BUILD\n\n  empty:=\n  space:= $(empty) $(empty)\n  _SINGLE=export MAKEFLAGS=$(space);\n\n  include $(TOPDIR)/include/debug.mk\n  include $(TOPDIR)/include/depends.mk\n  include $(TOPDIR)/include/toplevel.mk\nelse\n  include rules.mk\n  include $(INCLUDE_DIR)/depends.mk\n  include $(INCLUDE_DIR)/subdir.mk\n  include package/Makefile\n\n$(package/stamp-compile): $(BUILD_DIR)/.prepared\n$(BUILD_DIR)/.prepared: Makefile\n\t@mkdir -p $$(dirname $@)\n\t@touch $@\n\nclean: FORCE\n\tgit clean -f -d $(STAGING_DIR); true\n\tgit clean -f -d $(BUILD_DIR); true\n\tgit clean -f -d $(BIN_DIR); true\n\ndirclean: clean\n\tgit reset --hard HEAD\n\tgit clean -f -d\n\trm -rf feeds/\n\n# check prerequisites before starting to build\nprereq: $(package/stamp-prereq) ;\n\nworld: prepare $(package/stamp-compile) FORCE\n\t@$(MAKE) package/index\n\n.PHONY: clean dirclean prereq prepare world\n\nendif\n"
  },
  {
    "path": "target/sdk/files/README.SDK",
    "content": "This is the OpenWrt SDK. It contains a stripped-down version of\nthe buildroot. You can use it to test/develop packages without\nhaving to compile your own toolchain or any of the libraries\nincluded with OpenWrt.\n\nTo use it, just put your buildroot-compatible package directory\n(including its dependencies) in the subdir 'package/' and run\n'make' from this directory.\n\nTo make dependency handling easier, you can use ./scripts/feeds\nto install any core package that you need\n"
  },
  {
    "path": "target/sdk/files/include/prepare.mk",
    "content": "#\n# Copyright (C) 2015 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\nprepare: .git/config\n\n.git/config:\n\t@( \\\n\t\tprintf \"Initializing SDK ... \"; \\\n\t\tgit init -q .; \\\n\t\tfind . -mindepth 1 -maxdepth 1 -not -name feeds | xargs git add; \\\n\t\tgit commit -q -m \"Initial state\"; \\\n\t\techo \"ok.\"; \\\n\t)\n"
  },
  {
    "path": "target/toolchain/Config.in",
    "content": "config MAKE_TOOLCHAIN\n\tbool \"Package the OpenWrt-based Toolchain\"\n\tdepends on !EXTERNAL_TOOLCHAIN\n\tdefault BUILDBOT\n\thelp\n\t  Package the created toolchain as a tarball under the bin/ directory as\n\t  OpenWrt-Toolchain-$(BOARD)-for-$(ARCH)$(ARCH_SUFFIX)-gcc-$(GCCV)$(DIR_SUFFIX).\n\t  For example, a toolchain for the MIPS architecture might be named\n\t  OpenWrt-Toolchain-malta-for-mipsel_mips32-gcc-4.8-linaro_uClibc-0.9.33.2.tar.bz2.\n"
  },
  {
    "path": "target/toolchain/Makefile",
    "content": "#\n# Copyright (C) 2008-2009 Industrie Dial Face S.p.A.\n#               Luigi 'Comio' Mantellini <luigi.mantellini@idf-hit.com>\n# Copyright (C) 2006-2008 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\ninclude $(INCLUDE_DIR)/kernel.mk\ninclude $(INCLUDE_DIR)/version.mk\n\noverride MAKEFLAGS=\n\nTOOLCHAIN_NAME:=$(VERSION_DIST_SANITIZED)-toolchain-$(if $(CONFIG_VERSION_FILENAMES),$(VERSION_NUMBER)-)$(BOARD)$(if $(SUBTARGET),-$(SUBTARGET))_gcc-$(GCCV)$(DIR_SUFFIX).$(HOST_OS)-$(HOST_ARCH)\nTOOLCHAIN_BUILD_DIR:=$(BUILD_DIR)/$(TOOLCHAIN_NAME)\nEXCLUDE_DIRS:= \\\n\t*/initial \\\n\t*/stamp \\\n\t*/stampfiles \\\n\t*/man \\\n\t*/info\n\nall: compile\n\nTOOLCHAIN_PREFIX:=$(TOOLCHAIN_BUILD_DIR)/toolchain-$(ARCH)$(ARCH_SUFFIX)_gcc-$(GCCV)$(DIR_SUFFIX)\n\n$(BIN_DIR)/$(TOOLCHAIN_NAME).tar.xz: clean\n\tmkdir -p $(TOOLCHAIN_BUILD_DIR)\n\t$(TAR) -cf - -C $(TOPDIR)/staging_dir/  \\\n\t       $(foreach exclude,$(EXCLUDE_DIRS),--exclude=\"$(exclude)\") \\\n\t       toolchain-$(ARCH)$(ARCH_SUFFIX)_gcc-$(GCCV)$(DIR_SUFFIX) | \\\n\t       $(TAR) -xf - -C $(TOOLCHAIN_BUILD_DIR)\n\n\t$(CP) \\\n\t\t$(TOPDIR)/LICENSES \\\n\t\t$(TOPDIR)/COPYING \\\n\t\t./files/README.TOOLCHAIN \\\n\t\t$(TOOLCHAIN_BUILD_DIR)/\n\n\t$(CP) ./files/wrapper.sh $(TOOLCHAIN_PREFIX)/bin/$(REAL_GNU_TARGET_NAME)-wrapper.sh\n\tchmod +x $(TOOLCHAIN_PREFIX)/bin/$(REAL_GNU_TARGET_NAME)-wrapper.sh\n\t(cd $(TOOLCHAIN_PREFIX)/bin; \\\n\t\tfor app in cc gcc g++ c++ cpp ld as ; do \\\n\t\t\t[ -f $(REAL_GNU_TARGET_NAME)-$${app} ] && mv $(REAL_GNU_TARGET_NAME)-$${app} $(REAL_GNU_TARGET_NAME)-$${app}.bin ; \\\n\t\t\tln -sf $(REAL_GNU_TARGET_NAME)-wrapper.sh $(REAL_GNU_TARGET_NAME)-$${app} ; \\\n\t\tdone; \\\n\t)\n\n\t@-( \\\n\t\tfind \\\n\t\t\t$(TOOLCHAIN_BUILD_DIR)/*/bin \\\n\t\t\t$(TOOLCHAIN_BUILD_DIR)/*/*/bin \\\n\t\t\t$(TOOLCHAIN_BUILD_DIR)/*/libexec \\\n\t\t\t-type f; \\\n\t) | xargs strip 2>/dev/null >/dev/null\n\n\techo REVISION:=\"$(REVISION)\" > $(TOOLCHAIN_BUILD_DIR)/version.mk\n\tfind $(TOOLCHAIN_BUILD_DIR) -name .git | $(XARGS) rm -rf\n\tfind $(TOOLCHAIN_BUILD_DIR) -name .svn | $(XARGS) rm -rf\n\tfind $(TOOLCHAIN_BUILD_DIR) -name CVS | $(XARGS) rm -rf\n\tmkdir -p $(BIN_DIR)\n\t(cd $(BUILD_DIR); \\\n\t\ttar -I '$(STAGING_DIR_HOST)/bin/xz -7e -T$(if $(filter 1,$(NPROC)),2,0)' -cf $@ $(TOOLCHAIN_NAME) \\\n\t\t--mtime=\"$(shell date --date=@$(SOURCE_DATE_EPOCH))\"; \\\n\t)\n\ndownload:\nprepare:\ncompile: $(BIN_DIR)/$(TOOLCHAIN_NAME).tar.xz\ninstall: compile\n\nclean:\n\trm -rf $(TOOLCHAIN_BUILD_DIR) $(BIN_DIR)/$(TOOLCHAIN_NAME).tar.xz\n"
  },
  {
    "path": "target/toolchain/files/README.TOOLCHAIN",
    "content": "This is the OpenWrt SDK. It contains just the toolchain created\nby buildroot.\n"
  },
  {
    "path": "target/toolchain/files/wrapper.sh",
    "content": "#!/bin/sh\n\n# 2009 (C) Copyright Industrie Dial Face S.p.A.\n#          Luigi 'Comio' Mantellini <luigi.mantellini@idf-hit.com>\n#\n# Based on original idea from WindRiver\n#\n# Toolchain wrapper script.\n#\n# This script allows us to use a small number of GCC / binutils cross-tools\n# (one toolchain per instruction set architecture) to implement a larger\n# number of processor- or board-specific tools.  The wrapper script is\n# configured at install time with information covering basic CFLAGS,\n# LD options and the toolchain triplet name.\n#\n\nPROGNAME=$0\nREALNAME=$(readlink -f \"$0\")\n\nREALNAME_BASE=$(basename \"$REALNAME\")\nREALNAME_DIR=$(dirname \"$REALNAME\")\n\nTARGET_FUNDAMENTAL_ASFLAGS=''\nTARGET_FUNDAMENTAL_CFLAGS=''\nTARGET_ROOTFS_CFLAGS=''\nTARGET_FUNDAMENTAL_LDFLAGS=''\nTARGET_TOOLCHAIN_TRIPLET=${REALNAME_BASE%-*}\n\n# Parse our tool name, splitting it at '-' characters.\nBINARY=${PROGNAME##*-}\n\n# Parse our tool name, splitting it at '-' characters.\nIFS=- read -r _ _ _ TOOLCHAIN_PLATFORM PROGNAME << EOF\n$REALNAME_BASE\nEOF\n\n#\n# We add the directory this was executed from to the PATH\n# The toolchains (links) should be in this directory or in the users\n# PATH.\n#\nTOOLCHAIN_BIN_DIR=\"$REALNAME_DIR/\"\n\n# Set the PATH so that our run-time location is first\n# (get_feature is run from the path, so this has to be set)\nexport PATH=\"$TOOLCHAIN_BIN_DIR\":$PATH\nexport GCC_HONOUR_COPTS\n\nTOOLCHAIN_SYSROOT=\"$TOOLCHAIN_BIN_DIR/../..\"\nif [ ! -d \"$TOOLCHAIN_SYSROOT\" ]; then\n\techo \"Error: Unable to determine sysroot (looking for $TOOLCHAIN_SYSROOT)!\" >&2\n\texit 1\nfi\n\n# -Wl,--dynamic-linker=$TOOLCHAIN_SYSROOT/lib/ld-uClibc.so.0 \n# --dynamic-linker=$TOOLCHAIN_SYSROOT/lib/ld-uClibc.so.0 \n\ncase $TOOLCHAIN_PLATFORM in\n\tgnu|glibc|uclibc|musl)\n\t\tGCC_SYSROOT_FLAGS=\"--sysroot=$TOOLCHAIN_SYSROOT -Wl,-rpath=$TOOLCHAIN_SYSROOT/lib:$TOOLCHAIN_SYSROOT/usr/lib\"\n\t\tLD_SYSROOT_FLAGS=\"-rpath=$TOOLCHAIN_SYSROOT/lib:$TOOLCHAIN_SYSROOT/usr/lib\"\n\t\t;;\n\t*)\n\t\tGCC_SYSROOT_FLAGS=\"\"\n\t\tLD_SYSROOT_FLAGS=\"\"\n\t\t;;\nesac\n\n#\n# Run the cross-tool.\n#\ncase $BINARY in\n\tcc|gcc|g++|c++|cpp)\n\t\texec \"$TARGET_TOOLCHAIN_TRIPLET-$BINARY.bin\" $GCC_SYSROOT_FLAGS $TARGET_FUNDAMENTAL_CFLAGS $TARGET_ROOTFS_CFLAGS \"$@\"\n\t\t;;\n\tld)\n\t\texec \"$TARGET_TOOLCHAIN_TRIPLET-$BINARY.bin\" $LD_SYSROOT_FLAGS $TARGET_FUNDAMENTAL_LDFLAGS \"$@\"\n\t\t;;\n\tas)\n\t\texec \"$TARGET_TOOLCHAIN_TRIPLET-$BINARY.bin\" $TARGET_FUNDAMENTAL_ASFLAGS \"$@\"\n\t\t;;\n\t*)\n\t\texec \"$TARGET_TOOLCHAIN_TRIPLET-$BINARY.bin\" \"$@\"\n\t\t;;\nesac\n\nexit 0\n"
  },
  {
    "path": "toolchain/Config.in",
    "content": "# Copyright (C) 2006-2013 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\nmenuconfig TARGET_OPTIONS\n\tbool \"Target Options\"  if DEVEL\n\n\tconfig TARGET_OPTIMIZATION\n\t\tstring \"Target Optimizations\" if TARGET_OPTIONS\n\t\tdefault DEFAULT_TARGET_OPTIMIZATION\n\t\thelp\n\t\t  Optimizations to use when building for the target host.\n\n\tconfig SOFT_FLOAT\n\t\tbool \"Use software floating point by default\" if TARGET_OPTIONS\n\t\tdefault y if !HAS_FPU\n\t\tdepends on arm || armeb || powerpc || mipsel || mips || mips64el || mips64\n\t\thelp\n\t\t  If your target CPU does not have a Floating Point Unit (FPU) or a\n\t\t  kernel FPU emulator, but you still wish to support floating point\n\t\t  functions, then everything will need to be compiled with soft floating\n\t\t  point support (-msoft-float).\n\n\t\t  Most people will answer N.\n\n\tconfig USE_MIPS16\n\t\tbool \"Build packages with MIPS16 instructions\" if TARGET_OPTIONS\n\t\tdepends on HAS_MIPS16\n\t\tdefault y\n\t\thelp\n\t\t  If your target CPU does support the MIPS16 instruction set\n\t\t  and you want to use it for packages, enable this option.\n\t\t  MIPS16 produces smaller binaries thus reducing pressure on\n\t\t  caches and TLB.\n\n\t\t  Most people will answer N.\n\n\n\tchoice BPF_TOOLCHAIN\n\t\tprompt \"BPF toolchain\" if DEVEL\n\t\tdefault BPF_TOOLCHAIN_BUILD_LLVM if BUILDBOT\n\t\tdefault BPF_TOOLCHAIN_PREBUILT if HAS_PREBUILT_LLVM_TOOLCHAIN\n\t\tdefault BPF_TOOLCHAIN_NONE\n\n\t\tconfig BPF_TOOLCHAIN_NONE\n\t\t\tbool \"None\"\n\n\t\tconfig BPF_TOOLCHAIN_PREBUILT\n\t\t\tbool \"Use prebuilt LLVM toolchain\"\n\t\t\tdepends on HAS_PREBUILT_LLVM_TOOLCHAIN\n\t\t\tselect USE_LLVM_PREBUILT\n\n\t\tconfig BPF_TOOLCHAIN_HOST\n\t\t\tselect USE_LLVM_HOST\n\t\t\tbool \"Use host LLVM toolchain\"\n\n\t\tconfig BPF_TOOLCHAIN_BUILD_LLVM\n\t\t\tselect USE_LLVM_BUILD\n\t\t\tbool \"Build LLVM toolchain for eBPF\"\n\t\t\thelp\n\t\t\t  If enabled, a LLVM toolchain for building eBPF binaries will be built.\n\t\t\t  If this is not enabled, eBPF packages can only be built if the host\n\t\t\t  has a suitable toolchain\n\tendchoice\n\n\tconfig BPF_TOOLCHAIN_HOST_PATH\n\t\tstring\n\t\tdepends on BPF_TOOLCHAIN_HOST\n\t\tprompt \"Host LLVM toolchain path (prefix)\" if DEVEL\n\t\tdefault \"/usr/local/opt/llvm\" if HOST_OS_MACOS\n\t\tdefault \"\"\n\nmenuconfig EXTERNAL_TOOLCHAIN\n\tbool\n\tprompt \"Use external toolchain\"  if DEVEL\n\thelp\n\t  If enabled, the buildroot will compile using an existing toolchain instead of\n\t  compiling one.\n\n\tconfig NATIVE_TOOLCHAIN\n\t\tbool\n\t\tprompt \"Use host's toolchain\"  if DEVEL\n\t\tdepends on EXTERNAL_TOOLCHAIN\n\t\tselect NO_STRIP\n\t\thelp\n\t\t  If enabled, the buildroot will compile using the native toolchain for your\n\t\t  host instead of compiling one.\n\n\tconfig TARGET_NAME\n\t\tstring\n\t\tprompt \"Target name\"  if DEVEL\n\t\tdepends on EXTERNAL_TOOLCHAIN && !NATIVE_TOOLCHAIN\n\t\tdefault \"aarch64-unknown-linux-gnu\"  if aarch64\n\t\tdefault \"aarch64_be-unknown-linux-gnu\"  if aarch64_be\n\t\tdefault \"arm-unknown-linux-gnu\"      if arm\n\t\tdefault \"armeb-unknown-linux-gnu\"    if armeb\n\t\tdefault \"i486-unknown-linux-gnu\"     if i386\n\t\tdefault \"mips-unknown-linux-gnu\"     if mips\n\t\tdefault \"mipsel-unknown-linux-gnu\"   if mipsel\n\t\tdefault \"powerpc-unknown-linux-gnu\"  if powerpc\n\t\tdefault \"x86_64-unknown-linux-gnu\"   if x86_64\n\n\tconfig TOOLCHAIN_PREFIX\n\t\tstring\n\t\tprompt \"Toolchain prefix\"  if DEVEL\n\t\tdepends on EXTERNAL_TOOLCHAIN && !NATIVE_TOOLCHAIN\n\t\tdefault \"aarch64-unknown-linux-gnu\"  if aarch64\n\t\tdefault \"aarch64_be-unknown-linux-gnu\"  if aarch64_be\n\t\tdefault \"arm-unknown-linux-gnu-\"      if arm\n\t\tdefault \"armeb-unknown-linux-gnu-\"    if armeb\n\t\tdefault \"i486-unknown-linux-gnu-\"     if i386\n\t\tdefault \"mips-unknown-linux-gnu-\"     if mips\n\t\tdefault \"mipsel-unknown-linux-gnu-\"   if mipsel\n\t\tdefault \"powerpc-unknown-linux-gnu-\"  if powerpc\n\t\tdefault \"x86_64-unknown-linux-gnu-\"   if x86_64\n\n\tconfig TOOLCHAIN_ROOT\n\t\tstring\n\t\tprompt \"Toolchain root\"  if DEVEL\n\t\tdepends on EXTERNAL_TOOLCHAIN && !NATIVE_TOOLCHAIN\n\t\tdefault \"/opt/cross/aarch64-unknown-linux-gnu\"  if aarch64\n\t\tdefault \"/opt/cross/aarch64_be-unknown-linux-gnu\"  if aarch64_be\n\t\tdefault \"/opt/cross/arm-unknown-linux-gnu\"      if arm\n\t\tdefault \"/opt/cross/armeb-unknown-linux-gnu\"    if armeb\n\t\tdefault \"/opt/cross/i486-unknown-linux-gnu\"     if i386\n\t\tdefault \"/opt/cross/mips-unknown-linux-gnu\"     if mips\n\t\tdefault \"/opt/cross/mipsel-unknown-linux-gnu\"   if mipsel\n\t\tdefault \"/opt/cross/powerpc-unknown-linux-gnu\"  if powerpc\n\t\tdefault \"/opt/cross/x86_64-unknown-linux-gnu\"   if x86_64\n\n\tchoice TOOLCHAIN_LIBC_TYPE\n\t\tprompt \"Toolchain libc\"  if DEVEL\n\t\tdepends on EXTERNAL_TOOLCHAIN && !NATIVE_TOOLCHAIN\n\t\tdefault EXTERNAL_TOOLCHAIN_LIBC_USE_MUSL\n\t\thelp\n\t\t  Specify the libc type used by the external toolchain. The given value\n\t\t  is passed as -m flag to all gcc and g++ invocations. This is mainly\n\t\t  intended for multilib toolchains which support glibc and uclibc at\n\t\t  the same time. If no value is specified, no -m flag is passed.\n\n\t\tconfig EXTERNAL_TOOLCHAIN_LIBC_USE_GLIBC\n\t\t\tbool \"glibc\"\n\t\t\tselect USE_GLIBC\n\n\t\tconfig EXTERNAL_TOOLCHAIN_LIBC_USE_MUSL\n\t\t\tbool \"musl\"\n\t\t\tselect USE_MUSL\n\n\tendchoice\n\n\tconfig TOOLCHAIN_LIBC\n\t\tstring\n\t\tdepends on EXTERNAL_TOOLCHAIN && !NATIVE_TOOLCHAIN\n\t\tdefault \"glibc\" if EXTERNAL_TOOLCHAIN_LIBC_USE_GLIBC\n\t\tdefault \"musl\" if EXTERNAL_TOOLCHAIN_LIBC_USE_MUSL\n\n\tconfig TOOLCHAIN_BIN_PATH\n\t\tstring\n\t\tprompt \"Toolchain program path\"  if DEVEL\n\t\tdepends on EXTERNAL_TOOLCHAIN && !NATIVE_TOOLCHAIN\n\t\tdefault \"./usr/bin ./bin\"\n\t\thelp\n\t\t  Specify additional directories searched for toolchain binaries\n\t\t  (override PATH). Use ./DIR for directories relative to the root above.\n\n\tconfig TOOLCHAIN_INC_PATH\n\t\tstring\n\t\tprompt \"Toolchain include path\"  if DEVEL\n\t\tdepends on EXTERNAL_TOOLCHAIN && !NATIVE_TOOLCHAIN\n\t\tdefault \"./usr/include ./include\"\n\t\thelp\n\t\t  Specify additional directories searched for header files (override\n\t\t  CPPFLAGS). Use ./DIR for directories relative to the root above.\n\n\tconfig TOOLCHAIN_LIB_PATH\n\t\tstring\n\t\tprompt \"Toolchain library path\"  if DEVEL\n\t\tdepends on EXTERNAL_TOOLCHAIN && !NATIVE_TOOLCHAIN\n\t\tdefault \"./usr/lib ./lib\"\n\t\thelp\n\t\t  Specify additional directories searched for libraries (override LDFLAGS).\n\t\t  Use ./DIR for directories relative to the root above.\n\nconfig NEED_TOOLCHAIN\n\tbool\n\tdepends on DEVEL\n\tdefault y if !EXTERNAL_TOOLCHAIN\n\nmenuconfig TOOLCHAINOPTS\n\tbool \"Toolchain Options\"  if DEVEL\n\tdepends on NEED_TOOLCHAIN\n\nmenuconfig EXTRA_TARGET_ARCH\n\tbool\n\tprompt \"Enable an extra toolchain target architecture\" if TOOLCHAINOPTS\n\tdepends on !sparc\n\tdefault n\n\thelp\n\t  Some builds may require a 'biarch' toolchain. This option\n\t  allows you to specify an additional target arch.\n\n\t  Most people will answer N here.\n\n\tconfig EXTRA_TARGET_ARCH_NAME\n\t\tstring\n\t\tprompt \"Extra architecture name\" if EXTRA_TARGET_ARCH\n\t\thelp\n\t\t  Specify the cpu name (eg powerpc64 or x86_64) of the\n\t\t  additional target architecture.\n\n\tconfig EXTRA_TARGET_ARCH_OPTS\n\t\tstring\n\t\tprompt \"Extra architecture compiler options\" if EXTRA_TARGET_ARCH\n\t\thelp\n\t\t  If you're specifying an addition target architecture,\n\t\t  you'll probably need to also provide options to make\n\t\t  the compiler use this alternate arch.\n\n\t\t  For example, if you're building a compiler that can build\n\t\t  both powerpc and powerpc64 binaries, you'll need to\n\t\t  specify -m64 here.\n\n\n\tchoice\n\t\tprompt \"MIPS64 user-land ABI\" if TOOLCHAINOPTS && (mips64 || mips64el)\n\t\tdefault MIPS64_ABI_N64\n\t\thelp\n\t\t   MIPS64 supports 3 different user-land ABIs: o32 (legacy),\n\t\t   n32 and n64.\n\n\t\tconfig MIPS64_ABI_N64\n\t\t\tbool \"n64\"\n\n\t\tconfig MIPS64_ABI_N32\n\t\t\tdepends on !LIBC_USE_MUSL\n\t\t\tbool \"n32\"\n\n\t\tconfig MIPS64_ABI_O32\n\t\t\tbool \"o32\"\n\n\tendchoice\n\ncomment \"Binary tools\"\n\tdepends on TOOLCHAINOPTS\n\nsource \"toolchain/binutils/Config.in\"\n\ncomment \"Compiler\"\n\tdepends on TOOLCHAINOPTS\n\nsource \"toolchain/gcc/Config.in\"\n\nconfig NASM\n\tbool\n\tdepends on ( i386 || x86_64 )\n\tprompt \"Build nasm\" if TOOLCHAINOPTS\n\tdefault y\n\thelp\n\t  Enable if you want to build nasm\n\ncomment \"C Library\"\n\tdepends on TOOLCHAINOPTS\n\nchoice\n\tprompt \"C Library implementation\" if TOOLCHAINOPTS\n\tdefault LIBC_USE_GLIBC if arc\n\tdefault LIBC_USE_MUSL\n\thelp\n\t  Select the C library implementation.\n\n\tconfig LIBC_USE_GLIBC\n\t\tbool \"Use glibc\"\n\t\tselect USE_GLIBC\n\n\tconfig LIBC_USE_MUSL\n\t\tselect USE_MUSL\n\t\tbool \"Use musl\"\n\t\tdepends on !arc\n\nendchoice\n\nsource \"toolchain/musl/Config.in\"\n\ncomment \"Debuggers\"\n\tdepends on TOOLCHAINOPTS\n\nconfig GDB\n\tbool\n\tprompt \"Build gdb\" if TOOLCHAINOPTS\n\tdefault y if !EXTERNAL_TOOLCHAIN\n\thelp\n\t  Enable if you want to build the gdb.\n\nconfig GDB_PYTHON\n\tbool\n\tdepends on GDB\n\tprompt \"Build gdb with python binding\"\n\t\n\thelp\n\t  Enable the python bindings for GDB to allow using python in the gdb shell.\n\nconfig HAS_BPF_TOOLCHAIN\n\tbool\n\nconfig HAS_PREBUILT_LLVM_TOOLCHAIN\n\tdef_bool $(shell, [ -f llvm-bpf/.llvm-version ] && echo y || echo n)\n\nconfig USE_LLVM_HOST\n\tselect HAS_BPF_TOOLCHAIN\n\tbool\n\nconfig USE_LLVM_PREBUILT\n\tselect HAS_BPF_TOOLCHAIN\n\tdefault y if !DEVEL && !BUILDBOT && HAS_PREBUILT_LLVM_TOOLCHAIN\n\tbool\n\nconfig USE_LLVM_BUILD\n\tdefault y if !DEVEL && BUILDBOT\n\tselect HAS_BPF_TOOLCHAIN\n\tbool\n\nconfig USE_GLIBC\n\tdefault y if !TOOLCHAINOPTS && !EXTERNAL_TOOLCHAIN && !NATIVE_TOOLCHAIN && (arc)\n\tbool\n\nconfig USE_MUSL\n\tdefault y if !TOOLCHAINOPTS && !EXTERNAL_TOOLCHAIN && !NATIVE_TOOLCHAIN && !(arc)\n\tbool\n\nconfig SSP_SUPPORT\n\tdefault y if !PKG_CC_STACKPROTECTOR_NONE\n\tbool\n\nconfig USE_EXTERNAL_LIBC\n\tbool\n\tdefault y if EXTERNAL_TOOLCHAIN || NATIVE_TOOLCHAIN\n\nsource \"toolchain/binutils/Config.version\"\nsource \"toolchain/gcc/Config.version\"\n\nconfig LIBC\n\tstring\n\tdefault \"glibc\"   if USE_GLIBC\n\tdefault \"musl\"\t  if USE_MUSL\n\nconfig TARGET_SUFFIX\n\tstring\n\tdefault \"gnueabi\"         if USE_GLIBC && (arm || armeb)\n\tdefault \"gnu\"             if USE_GLIBC && !(arm || armeb)\n\tdefault \"muslgnueabi\"     if USE_MUSL && (arm || armeb)\n\tdefault \"musl\"            if USE_MUSL && !(arm || armeb)\n\nconfig MIPS64_ABI\n\tdepends on mips64 || mips64el\n\tstring\n\tdefault \"64\" if MIPS64_ABI_N64\n\tdefault \"n32\" if MIPS64_ABI_N32\n\tdefault \"32\" if MIPS64_ABI_O32\n\tdefault \"64\"\n"
  },
  {
    "path": "toolchain/Makefile",
    "content": "# \n# Copyright (C) 2007-2009 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n# Main makefile for the toolchain\n#\n# Steps:\n# 1) toolchain/binutils/compile\n#    build & install binutils\n# 2) toolchain/gcc/minimal/compile\n#    build & install a minimal gcc, needed for steps 3 & 4\n# 3) toolchain/kernel-headers/compile\n#    install kernel headers, needed for step 4\n# 4) toolchain/libc/headers/compile\n#    build & install libc headers & support files, needed for step 5\n# 5) toolchain/gcc/initial/compile\n#    build & install an initial gcc, needed for step 6\n# 6) toolchain/libc/compile\n#    build & install the final libc\n# 7) toolchain/gcc/final/compile\n#    build & install the final gcc\n# 8) toolchain/libc/utils/compile\n#    build & install libc utilities\n#\n# For musl, steps 2 and 4 are skipped, and step 3 is done after 5\n\ncurdir:=toolchain\n\n# subdirectories to descend into\n$(curdir)/builddirs := $(if $(CONFIG_GDB),gdb) $(if $(CONFIG_EXTERNAL_TOOLCHAIN),wrapper,kernel-headers binutils gcc/initial gcc/final $(LIBC) fortify-headers) $(if $(CONFIG_NASM),nasm)\n\n# builddir dependencies\nifeq ($(CONFIG_EXTERNAL_TOOLCHAIN),)\n  ifdef CONFIG_USE_MUSL\n    $(curdir)/kernel-headers/compile:=$(curdir)/gcc/initial/compile\n    $(curdir)/$(LIBC)/compile:=$(curdir)/kernel-headers/compile\n  else\n    $(curdir)/builddirs += $(LIBC)/headers gcc/minimal\n    $(curdir)/gcc/minimal/compile:=$(curdir)/binutils/compile\n    $(curdir)/kernel-headers/compile:=$(curdir)/gcc/minimal/compile\n    $(curdir)/$(LIBC)/headers/compile:=$(curdir)/kernel-headers/compile\n    $(curdir)/gcc/initial/compile:=$(curdir)/$(LIBC)/headers/compile\n  endif\n\n  $(curdir)/gcc/initial/compile+=$(curdir)/binutils/compile\n  $(curdir)/$(LIBC)/compile:=$(curdir)/gcc/initial/compile\n  $(curdir)/gcc/final/compile:=$(curdir)/$(LIBC)/compile $(curdir)/kernel-headers/compile\n  $(curdir)/$(LIBC)/utils/compile:=$(curdir)/gcc/final/compile\nendif\n\nifndef DUMP_TARGET_DB\nifneq ($(ARCH),)\n  $(TOOLCHAIN_DIR)/info.mk: .config\n\t@for dir in $(TOOLCHAIN_DIR); do ( \\\n\t\t$(if $(QUIET),,set -x;) \\\n\t\tmkdir -p \"$$dir\"; \\\n\t\tcd \"$$dir\"; \\\n\t\tln -nsf lib lib64; \\\n\t\tln -nsf lib lib32; \\\n\t\tmkdir -p stamp lib usr/include usr/lib ; \\\n\t); done\n\t@grep GCC_VERSION $@ >/dev/null 2>&1 || $(INSTALL_DATA) $(TOPDIR)/toolchain/info.mk $@\n\t@touch $@\nendif\nendif\n\nifdef CONFIG_BUILDBOT\nifneq ($(wildcard $(TOPDIR)/.git),)\n  $(TOOLCHAIN_DIR)/stamp/.ver_check: $(TMP_DIR)/.build\n\tcd \"$(TOPDIR)\"; git log --format=%h -1 toolchain > $(TMP_DIR)/.ver_check\n\tcmp -s $(TMP_DIR)/.ver_check $@ || { \\\n\t\trm -rf $(BUILD_DIR) $(STAGING_DIR) $(TOOLCHAIN_DIR) $(BUILD_DIR_TOOLCHAIN); \\\n\t\tmkdir -p $(TOOLCHAIN_DIR)/stamp; \\\n\t\tmv $(TMP_DIR)/.ver_check $@; \\\n\t}\n\n$(TOOLCHAIN_DIR)/info.mk $(STAGING_DIR)/.prepared: $(TOOLCHAIN_DIR)/stamp/.ver_check\nendif\nendif\n\n# prerequisites for the individual targets\n$(curdir)/ := .config prereq\n$(curdir)//compile = $(STAGING_DIR)/.prepared $(TOOLCHAIN_DIR)/info.mk $(tools/stamp-compile)\n\nifndef DUMP_TARGET_DB\n$(TOOLCHAIN_DIR)/stamp/.gcc-initial_installed:\nendif\n\n$(curdir)/install: $(curdir)/compile\n\n$(eval $(call stampfile,$(curdir),toolchain,compile,$(TOOLCHAIN_DIR)/stamp/.gcc-initial_installed,,$(TOOLCHAIN_DIR)))\n$(eval $(call stampfile,$(curdir),toolchain,check,$(TMP_DIR)/.build))\n$(eval $(call subdir,$(curdir)))\n\n"
  },
  {
    "path": "toolchain/binutils/Config.in",
    "content": "# Choose binutils version.\n\nchoice\n\tprompt \"Binutils Version\" if TOOLCHAINOPTS\n\tdefault BINUTILS_USE_VERSION_2_37\n\thelp\n\t  Select the version of binutils you wish to use.\n\n\tconfig BINUTILS_USE_VERSION_2_37\n\t\tbool \"Binutils 2.37\"\n\t\tselect BINUTILS_VERSION_2_37\n\n\tconfig BINUTILS_USE_VERSION_2_38\n\t\tbool \"Binutils 2.38\"\n\t\tselect BINUTILS_VERSION_2_38\nendchoice\n\nconfig EXTRA_BINUTILS_CONFIG_OPTIONS\n\tstring\n\tprompt \"Additional binutils configure options\" if TOOLCHAINOPTS\n\tdefault \"\"\n\thelp\n\t    Any additional binutils options you may want to include....\n"
  },
  {
    "path": "toolchain/binutils/Config.version",
    "content": "\nconfig BINUTILS_VERSION_2_37\n\tdefault y if !TOOLCHAINOPTS\n\tbool\n\nconfig BINUTILS_VERSION_2_38\n\tbool\n\nconfig BINUTILS_VERSION\n\tstring\n\tdefault \"2.37\"\t\t\tif BINUTILS_VERSION_2_37\n\tdefault \"2.38\"\t\t\tif BINUTILS_VERSION_2_38\n"
  },
  {
    "path": "toolchain/binutils/Makefile",
    "content": "#\n# Copyright (C) 2006-2013 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=binutils\nPKG_VERSION:=$(call qstrip,$(CONFIG_BINUTILS_VERSION))\nBIN_VERSION:=$(PKG_VERSION)\n\nPKG_SOURCE_URL:=@GNU/binutils/\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz\n\nTAR_OPTIONS += --exclude='*.rej'\n\nifeq ($(PKG_VERSION),2.32)\n  PKG_HASH:=0ab6c55dd86a92ed561972ba15b9b70a8b9f75557f896446c82e8b36e473ee04\nendif\n\nifeq ($(PKG_VERSION),2.34)\n  PKG_HASH:=f00b0e8803dc9bab1e2165bd568528135be734df3fabf8d0161828cd56028952\nendif\n\nifeq ($(PKG_VERSION),2.35.2)\n  PKG_HASH:=dcd5b0416e7b0a9b24bed76cd8c6c132526805761863150a26d016415b8bdc7b\nendif\n\nifeq ($(PKG_VERSION),2.36.1)\n  PKG_HASH:=e81d9edf373f193af428a0f256674aea62a9d74dfe93f65192d4eae030b0f3b0\nendif\n\nifeq ($(PKG_VERSION),2.37)\n  PKG_HASH:=820d9724f020a3e69cb337893a0b63c2db161dadcb0e06fc11dc29eb1e84a32c\nendif\n\nifeq ($(PKG_VERSION),2.38)\n  PKG_HASH:=e316477a914f567eccc34d5d29785b8b0f5a10208d36bbacedcc39048ecfe024\nendif\n\nHOST_BUILD_PARALLEL:=1\n\nPATCH_DIR:=./patches/$(PKG_VERSION)\n\ninclude $(INCLUDE_DIR)/toolchain-build.mk\n\nHOST_CONFIGURE_ARGS = \\\n\t--prefix=$(TOOLCHAIN_DIR) \\\n\t--build=$(GNU_HOST_NAME) \\\n\t--host=$(GNU_HOST_NAME) \\\n\t--target=$(REAL_GNU_TARGET_NAME) \\\n\t--with-sysroot=$(TOOLCHAIN_DIR) \\\n\t--enable-deterministic-archives \\\n\t--enable-plugins \\\n\t--disable-multilib \\\n\t--disable-werror \\\n\t--disable-nls \\\n\t--disable-sim \\\n\t--disable-gdb \\\n\t$(GRAPHITE_CONFIGURE) \\\n\t$(SOFT_FLOAT_CONFIG_OPTION) \\\n\t$(call qstrip,$(CONFIG_EXTRA_BINUTILS_CONFIG_OPTIONS))\n\nifneq ($(CONFIG_SSP_SUPPORT),)\n  HOST_CONFIGURE_ARGS+= \\\n\t\t--enable-libssp\nelse\n  HOST_CONFIGURE_ARGS+= \\\n\t\t--disable-libssp\nendif\n\nifneq ($(CONFIG_EXTRA_TARGET_ARCH),)\n  HOST_CONFIGURE_ARGS+= \\\n\t\t--enable-targets=$(call qstrip,$(CONFIG_EXTRA_TARGET_ARCH_NAME))-linux-$(TARGET_SUFFIX)\nendif\n\nHOST_CONFIGURE_VARS += \\\n\tacx_cv_cc_gcc_supports_ada=false\n\ndefine Host/Prepare\n\t$(call Host/Prepare/Default)\n\tln -snf $(notdir $(HOST_BUILD_DIR)) $(BUILD_DIR_TOOLCHAIN)/$(PKG_NAME)\n\t$(CP) $(SCRIPT_DIR)/config.{guess,sub} $(HOST_BUILD_DIR)/\n\t$(SED) 's, \" Linaro.*,,' $(HOST_BUILD_DIR)/bfd/version.h\nendef\n\ndefine Host/Compile\n\t+$(MAKE) $(HOST_JOBS) -C $(HOST_BUILD_DIR) all\nendef\n\ndefine Host/Install\n\tmkdir -p $(TOOLCHAIN_DIR)/initial\n\t$(MAKE) -C $(HOST_BUILD_DIR) \\\n\t\tprefix=$(TOOLCHAIN_DIR)/initial \\\n\t\tinstall\n\t$(MAKE) -C $(HOST_BUILD_DIR) \\\n\t\tprefix=$(TOOLCHAIN_DIR) \\\n\t\tinstall\n\t$(call FixupLibdir,$(TOOLCHAIN_DIR)/initial)\n\t$(RM) $(TOOLCHAIN_DIR)/initial/lib/libiberty.a\n\t$(CP) $(TOOLCHAIN_DIR)/bin/$(REAL_GNU_TARGET_NAME)-readelf $(HOST_BUILD_PREFIX)/bin/readelf\n\t# ARC gcc requires extlib.\n\t# If extlib is not available in \"initial\" folder\n\t# initial gcc will fail to build libc.\n\tif [ -d $(TOOLCHAIN_DIR)/extlib ]; then \\\n\t\t$(CP) -r $(TOOLCHAIN_DIR)/extlib $(TOOLCHAIN_DIR)/initial/; \\\n\tfi\nendef\n\ndefine Host/Clean\n\trm -rf \\\n\t\t$(HOST_BUILD_DIR) \\\n\t\t$(BUILD_DIR_TOOLCHAIN)/$(PKG_NAME)\nendef\n\n$(eval $(call HostBuild))\n"
  },
  {
    "path": "toolchain/binutils/patches/2.37/300-001_ld_makefile_patch.patch",
    "content": "--- a/ld/Makefile.am\n+++ b/ld/Makefile.am\n@@ -50,7 +50,7 @@ AM_CFLAGS = $(WARN_CFLAGS) $(ELF_CLFAGS)\n # We put the scripts in the directory $(scriptdir)/ldscripts.\n # We can't put the scripts in $(datadir) because the SEARCH_DIR\n # directives need to be different for native and cross linkers.\n-scriptdir = $(tooldir)/lib\n+scriptdir = $(libdir)\n \n EMUL = @EMUL@\n EMULATION_OFILES = @EMULATION_OFILES@\n--- a/ld/Makefile.in\n+++ b/ld/Makefile.in\n@@ -561,7 +561,7 @@ AM_CFLAGS = $(WARN_CFLAGS) $(ELF_CLFAGS)\n # We put the scripts in the directory $(scriptdir)/ldscripts.\n # We can't put the scripts in $(datadir) because the SEARCH_DIR\n # directives need to be different for native and cross linkers.\n-scriptdir = $(tooldir)/lib\n+scriptdir = $(libdir)\n BASEDIR = $(srcdir)/..\n BFDDIR = $(BASEDIR)/bfd\n INCDIR = $(BASEDIR)/include\n"
  },
  {
    "path": "toolchain/binutils/patches/2.37/400-mips_no_dynamic_linking_sym.patch",
    "content": "--- a/bfd/elfxx-mips.c\n+++ b/bfd/elfxx-mips.c\n@@ -8057,6 +8057,7 @@ _bfd_mips_elf_create_dynamic_sections (b\n \n       name = SGI_COMPAT (abfd) ? \"_DYNAMIC_LINK\" : \"_DYNAMIC_LINKING\";\n       bh = NULL;\n+      if (0) {\n       if (!(_bfd_generic_link_add_one_symbol\n \t    (info, abfd, name, BSF_GLOBAL, bfd_abs_section_ptr, 0,\n \t     NULL, false, get_elf_backend_data (abfd)->collect, &bh)))\n@@ -8069,6 +8070,7 @@ _bfd_mips_elf_create_dynamic_sections (b\n \n       if (! bfd_elf_link_record_dynamic_symbol (info, h))\n \treturn false;\n+      }\n \n       if (! mips_elf_hash_table (info)->use_rld_obj_head)\n \t{\n"
  },
  {
    "path": "toolchain/binutils/patches/2.37/500-Change-default-emulation-for-mips64-linux.patch",
    "content": "--- a/bfd/config.bfd\n+++ b/bfd/config.bfd\n@@ -891,12 +891,12 @@ case \"${targ}\" in\n     targ_selvecs=\"mips_elf32_le_vec mips_elf64_be_vec mips_elf64_le_vec mips_ecoff_be_vec mips_ecoff_le_vec\"\n     ;;\n   mips64*el-*-linux*)\n-    targ_defvec=mips_elf32_ntrad_le_vec\n-    targ_selvecs=\"mips_elf32_ntrad_be_vec mips_elf32_trad_le_vec mips_elf32_trad_be_vec mips_elf64_trad_le_vec mips_elf64_trad_be_vec\"\n+    targ_defvec=mips_elf64_trad_le_vec\n+    targ_selvecs=\"mips_elf32_ntrad_le_vec mips_elf32_ntrad_be_vec mips_elf32_trad_le_vec mips_elf32_trad_be_vec mips_elf64_trad_be_vec\"\n     ;;\n   mips64*-*-linux*)\n-    targ_defvec=mips_elf32_ntrad_be_vec\n-    targ_selvecs=\"mips_elf32_ntrad_le_vec mips_elf32_trad_be_vec mips_elf32_trad_le_vec mips_elf64_trad_be_vec mips_elf64_trad_le_vec\"\n+    targ_defvec=mips_elf64_trad_be_vec\n+    targ_selvecs=\"mips_elf32_ntrad_be_vec mips_elf32_ntrad_le_vec mips_elf32_trad_be_vec mips_elf32_trad_le_vec mips_elf64_trad_le_vec\"\n     ;;\n   mips*el-*-linux*)\n     targ_defvec=mips_elf32_trad_le_vec\n--- a/ld/configure.tgt\n+++ b/ld/configure.tgt\n@@ -530,12 +530,12 @@ mips*-*-vxworks*)\ttarg_emul=elf32ebmipvx\n \t\t\t;;\n mips*-*-windiss)\ttarg_emul=elf32mipswindiss\n \t\t\t;;\n-mips64*el-*-linux-*)\ttarg_emul=elf32ltsmipn32\n-\t\t\ttarg_extra_emuls=\"elf32btsmipn32 elf32ltsmip elf32btsmip elf64ltsmip elf64btsmip\"\n+mips64*el-*-linux-*)\ttarg_emul=elf64ltsmip\n+\t\t\ttarg_extra_emuls=\"elf32btsmipn32 elf32ltsmipn32 elf32ltsmip elf32btsmip elf64btsmip\"\n \t\t\ttarg_extra_libpath=$targ_extra_emuls\n \t\t\t;;\n-mips64*-*-linux-*)\ttarg_emul=elf32btsmipn32\n-\t\t\ttarg_extra_emuls=\"elf32ltsmipn32 elf32btsmip elf32ltsmip elf64btsmip elf64ltsmip\"\n+mips64*-*-linux-*)\ttarg_emul=elf64btsmip\n+\t\t\ttarg_extra_emuls=\"elf32btsmipn32 elf32ltsmipn32 elf32btsmip elf32ltsmip elf64ltsmip\"\n \t\t\ttarg_extra_libpath=$targ_extra_emuls\n \t\t\t;;\n mips*el-*-linux-*)\ttarg_emul=elf32ltsmip\n"
  },
  {
    "path": "toolchain/binutils/patches/2.37/600-Close_the_file_descriptor.patch",
    "content": "From: H.J. Lu <hjl.tools@gmail.com>\nDate: Mon, 26 Jul 2021 12:59:55 +0000 (-0700)\nSubject: bfd: Close the file descriptor if there is no archive fd\nX-Git-Url: https://sourceware.org/git/?p=binutils-gdb.git;a=commitdiff_plain;h=1c611b40e6bfc8029bff7696814330b5bc0ee5c0\n\nbfd: Close the file descriptor if there is no archive fd\n\nClose the file descriptor if there is no archive plugin file descriptor\nto avoid running out of file descriptors on thin archives with many\narchive members.\n\nbfd/\n\n\tPR ld/28138\n\t* plugin.c (bfd_plugin_close_file_descriptor): Close the file\n\tdescriptor there is no archive plugin file descriptor.\n\nld/\n\n\tPR ld/28138\n\t* testsuite/ld-plugin/lto.exp: Run tmpdir/pr28138 only for\n\tnative build.\n\n\tPR ld/28138\n\t* testsuite/ld-plugin/lto.exp: Run ld/28138 tests.\n\t* testsuite/ld-plugin/pr28138.c: New file.\n\t* testsuite/ld-plugin/pr28138-1.c: Likewise.\n\t* testsuite/ld-plugin/pr28138-2.c: Likewise.\n\t* testsuite/ld-plugin/pr28138-3.c: Likewise.\n\t* testsuite/ld-plugin/pr28138-4.c: Likewise.\n\t* testsuite/ld-plugin/pr28138-5.c: Likewise.\n\t* testsuite/ld-plugin/pr28138-6.c: Likewise.\n\t* testsuite/ld-plugin/pr28138-7.c: Likewise.\n\n(cherry picked from commit 5a98fb7513b559e20dfebdbaa2a471afda3b4742)\n(cherry picked from commit 7dc37e1e1209c80e0bab784df6b6bac335e836f2)\n---\n\n--- a/bfd/plugin.c\n+++ b/bfd/plugin.c\n@@ -291,6 +291,14 @@ bfd_plugin_close_file_descriptor (bfd *a\n \t     && !bfd_is_thin_archive (abfd->my_archive))\n \tabfd = abfd->my_archive;\n \n+      /* Close the file descriptor if there is no archive plugin file\n+\t descriptor.  */\n+      if (abfd->archive_plugin_fd == -1)\n+\t{\n+\t  close (fd);\n+\t  return;\n+\t}\n+\n       abfd->archive_plugin_fd_open_count--;\n       /* Dup the archive plugin file descriptor for later use, which\n \t will be closed by _bfd_archive_close_and_cleanup.  */\n--- a/ld/testsuite/ld-plugin/lto.exp\n+++ b/ld/testsuite/ld-plugin/lto.exp\n@@ -687,6 +687,40 @@ if { [is_elf_format] && [check_lto_share\n     }\n }\n \n+run_cc_link_tests [list \\\n+    [list \\\n+\t\"Build pr28138.a\" \\\n+\t\"-T\" \"\" \\\n+\t{pr28138-1.c pr28138-2.c pr28138-3.c pr28138-4.c pr28138-5.c \\\n+\t pr28138-6.c pr28138-7.c} {} \"pr28138.a\" \\\n+    ] \\\n+    [list \\\n+\t\"Build pr28138.o\" \\\n+\t\"\" \"\" \\\n+\t{pr28138.c} {} \\\n+    ] \\\n+]\n+\n+set exec_output [run_host_cmd \"sh\" \\\n+\t\t\t      \"-c \\\"ulimit -n 20; \\\n+\t\t\t      $CC -Btmpdir/ld -o tmpdir/pr28138 \\\n+\t\t\t      tmpdir/pr28138.o tmpdir/pr28138.a\\\"\"]\n+set exec_output [prune_warnings $exec_output]\n+if [string match \"\" $exec_output] then {\n+    if { [isnative] } {\n+\tset exec_output [run_host_cmd \"tmpdir/pr28138\" \"\"]\n+\tif [string match \"PASS\" $exec_output] then {\n+\t    pass \"PR ld/28138\"\n+\t} else {\n+\t    fail \"PR ld/28138\"\n+\t}\n+    } else {\n+\tpass \"PR ld/28138\"\n+    }\n+} else {\n+    fail \"PR ld/28138\"\n+}\n+\n set testname \"Build liblto-11.a\"\n remote_file host delete \"tmpdir/liblto-11.a\"\n set catch_output [run_host_cmd \"$ar\" \"rc $plug_opt tmpdir/liblto-11.a tmpdir/lto-11a.o tmpdir/lto-11b.o tmpdir/lto-11c.o\"]\n--- /dev/null\n+++ b/ld/testsuite/ld-plugin/pr28138-1.c\n@@ -0,0 +1,6 @@\n+extern int a0(void);\n+int\n+a1(void)\n+{\n+  return 1 + a0();\n+}\n--- /dev/null\n+++ b/ld/testsuite/ld-plugin/pr28138-2.c\n@@ -0,0 +1,6 @@\n+extern int a1(void);\n+int\n+a2(void)\n+{\n+  return 1 + a1();\n+}\n--- /dev/null\n+++ b/ld/testsuite/ld-plugin/pr28138-3.c\n@@ -0,0 +1,6 @@\n+extern int a2(void);\n+int\n+a3(void)\n+{\n+  return 1 + a2();\n+}\n--- /dev/null\n+++ b/ld/testsuite/ld-plugin/pr28138-4.c\n@@ -0,0 +1,6 @@\n+extern int a3(void);\n+int\n+a4(void)\n+{\n+  return 1 + a3();\n+}\n--- /dev/null\n+++ b/ld/testsuite/ld-plugin/pr28138-5.c\n@@ -0,0 +1,6 @@\n+extern int a4(void);\n+int\n+a5(void)\n+{\n+  return 1 + a4();\n+}\n--- /dev/null\n+++ b/ld/testsuite/ld-plugin/pr28138-6.c\n@@ -0,0 +1,6 @@\n+extern int a5(void);\n+int\n+a6(void)\n+{\n+  return 1 + a5();\n+}\n--- /dev/null\n+++ b/ld/testsuite/ld-plugin/pr28138-7.c\n@@ -0,0 +1,6 @@\n+extern int a6(void);\n+int\n+a7(void)\n+{\n+  return 1 + a6();\n+}\n--- /dev/null\n+++ b/ld/testsuite/ld-plugin/pr28138.c\n@@ -0,0 +1,20 @@\n+#include <stdio.h>\n+\n+extern int a7(void);\n+\n+int\n+a0(void)\n+{\n+  return 0;\n+}\n+\n+int\n+main()\n+{\n+  if (a7() == 7)\n+    {\n+      printf (\"PASS\\n\");\n+      return 0;\n+    }\n+  return 1;\n+}\n"
  },
  {
    "path": "toolchain/binutils/patches/2.38/300-001_ld_makefile_patch.patch",
    "content": "--- a/ld/Makefile.am\n+++ b/ld/Makefile.am\n@@ -50,7 +50,7 @@ AM_CFLAGS = $(WARN_CFLAGS) $(ELF_CLFAGS)\n # We put the scripts in the directory $(scriptdir)/ldscripts.\n # We can't put the scripts in $(datadir) because the SEARCH_DIR\n # directives need to be different for native and cross linkers.\n-scriptdir = $(tooldir)/lib\n+scriptdir = $(libdir)\n \n EMUL = @EMUL@\n EMULATION_OFILES = @EMULATION_OFILES@\n--- a/ld/Makefile.in\n+++ b/ld/Makefile.in\n@@ -563,7 +563,7 @@ AM_CFLAGS = $(WARN_CFLAGS) $(ELF_CLFAGS)\n # We put the scripts in the directory $(scriptdir)/ldscripts.\n # We can't put the scripts in $(datadir) because the SEARCH_DIR\n # directives need to be different for native and cross linkers.\n-scriptdir = $(tooldir)/lib\n+scriptdir = $(libdir)\n BASEDIR = $(srcdir)/..\n BFDDIR = $(BASEDIR)/bfd\n INCDIR = $(BASEDIR)/include\n"
  },
  {
    "path": "toolchain/binutils/patches/2.38/400-mips_no_dynamic_linking_sym.patch",
    "content": "--- a/bfd/elfxx-mips.c\n+++ b/bfd/elfxx-mips.c\n@@ -8057,6 +8057,7 @@ _bfd_mips_elf_create_dynamic_sections (b\n \n       name = SGI_COMPAT (abfd) ? \"_DYNAMIC_LINK\" : \"_DYNAMIC_LINKING\";\n       bh = NULL;\n+      if (0) {\n       if (!(_bfd_generic_link_add_one_symbol\n \t    (info, abfd, name, BSF_GLOBAL, bfd_abs_section_ptr, 0,\n \t     NULL, false, get_elf_backend_data (abfd)->collect, &bh)))\n@@ -8069,6 +8070,7 @@ _bfd_mips_elf_create_dynamic_sections (b\n \n       if (! bfd_elf_link_record_dynamic_symbol (info, h))\n \treturn false;\n+      }\n \n       if (! mips_elf_hash_table (info)->use_rld_obj_head)\n \t{\n"
  },
  {
    "path": "toolchain/binutils/patches/2.38/500-Change-default-emulation-for-mips64-linux.patch",
    "content": "--- a/bfd/config.bfd\n+++ b/bfd/config.bfd\n@@ -928,12 +928,12 @@ case \"${targ}\" in\n     targ_selvecs=\"mips_elf32_le_vec mips_elf64_be_vec mips_elf64_le_vec mips_ecoff_be_vec mips_ecoff_le_vec\"\n     ;;\n   mips64*el-*-linux*)\n-    targ_defvec=mips_elf32_ntrad_le_vec\n-    targ_selvecs=\"mips_elf32_ntrad_be_vec mips_elf32_trad_le_vec mips_elf32_trad_be_vec mips_elf64_trad_le_vec mips_elf64_trad_be_vec\"\n+    targ_defvec=mips_elf64_trad_le_vec\n+    targ_selvecs=\"mips_elf32_ntrad_le_vec mips_elf32_ntrad_be_vec mips_elf32_trad_le_vec mips_elf32_trad_be_vec mips_elf64_trad_be_vec\"\n     ;;\n   mips64*-*-linux*)\n-    targ_defvec=mips_elf32_ntrad_be_vec\n-    targ_selvecs=\"mips_elf32_ntrad_le_vec mips_elf32_trad_be_vec mips_elf32_trad_le_vec mips_elf64_trad_be_vec mips_elf64_trad_le_vec\"\n+    targ_defvec=mips_elf64_trad_be_vec\n+    targ_selvecs=\"mips_elf32_ntrad_be_vec mips_elf32_ntrad_le_vec mips_elf32_trad_be_vec mips_elf32_trad_le_vec mips_elf64_trad_le_vec\"\n     ;;\n   mips*el-*-linux*)\n     targ_defvec=mips_elf32_trad_le_vec\n--- a/ld/configure.tgt\n+++ b/ld/configure.tgt\n@@ -543,12 +543,12 @@ mips*-*-vxworks*)\ttarg_emul=elf32ebmipvx\n \t\t\t;;\n mips*-*-windiss)\ttarg_emul=elf32mipswindiss\n \t\t\t;;\n-mips64*el-*-linux-*)\ttarg_emul=elf32ltsmipn32\n-\t\t\ttarg_extra_emuls=\"elf32btsmipn32 elf32ltsmip elf32btsmip elf64ltsmip elf64btsmip\"\n+mips64*el-*-linux-*)\ttarg_emul=elf64ltsmip\n+\t\t\ttarg_extra_emuls=\"elf32btsmipn32 elf32ltsmipn32 elf32ltsmip elf32btsmip elf64btsmip\"\n \t\t\ttarg_extra_libpath=$targ_extra_emuls\n \t\t\t;;\n-mips64*-*-linux-*)\ttarg_emul=elf32btsmipn32\n-\t\t\ttarg_extra_emuls=\"elf32ltsmipn32 elf32btsmip elf32ltsmip elf64btsmip elf64ltsmip\"\n+mips64*-*-linux-*)\ttarg_emul=elf64btsmip\n+\t\t\ttarg_extra_emuls=\"elf32btsmipn32 elf32ltsmipn32 elf32btsmip elf32ltsmip elf64ltsmip\"\n \t\t\ttarg_extra_libpath=$targ_extra_emuls\n \t\t\t;;\n mips*el-*-linux-*)\ttarg_emul=elf32ltsmip\n"
  },
  {
    "path": "toolchain/build_version",
    "content": "1\n"
  },
  {
    "path": "toolchain/fortify-headers/Makefile",
    "content": "#\n# Copyright (C) 2015 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\ninclude $(TOPDIR)/rules.mk\ninclude $(INCLUDE_DIR)/target.mk\n\nPKG_NAME:=fortify-headers\nPKG_VERSION:=1.1\nPKG_RELEASE=1\n\nPKG_SOURCE_URL:=http://dl.2f30.org/releases\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz\nPKG_HASH:=6ba5d860a2d2ba4c3346924b93930c34856eafe148bdbdf271ecab8065201fb6\n\ninclude $(INCLUDE_DIR)/toolchain-build.mk\n\ndefine Host/Compile\n\ttrue\nendef\n\ndefine Host/Install\n\t$(MAKE) -C $(HOST_BUILD_DIR) PREFIX=\"\" DESTDIR=\"$(TOOLCHAIN_DIR)\" install\nendef\n\n$(eval $(call HostBuild))\n"
  },
  {
    "path": "toolchain/gcc/Config.in",
    "content": "# Choose gcc version.\n\nchoice\n\tprompt \"GCC compiler Version\" if TOOLCHAINOPTS\n\tdefault GCC_USE_VERSION_11\n\thelp\n\t  Select the version of gcc you wish to use.\n\n\tconfig GCC_USE_VERSION_8\n\t\tbool \"gcc 8.x\"\n\n\tconfig GCC_USE_VERSION_10\n\t\tbool \"gcc 10.x\"\n\n\tconfig GCC_USE_VERSION_11\n\t\tbool \"gcc 11.x\"\nendchoice\n\nconfig GCC_USE_GRAPHITE\n\tbool\n\tprompt \"Compile in support for the new Graphite framework in GCC 4.4+\" if TOOLCHAINOPTS\n\nconfig EXTRA_GCC_CONFIG_OPTIONS\n\tstring\n\tprompt \"Additional gcc configure options\" if TOOLCHAINOPTS\n\tdefault \"\"\n\thelp\n\t    Any additional gcc options you may want to include....\n\nconfig GCC_DEFAULT_PIE\n\tbool\n\tprompt \"Build executable with PIE enabled by default\" if TOOLCHAINOPTS\n\tdefault n\n\thelp\n\t    Use gcc configure option --enable-default-pie to turn on -fPIE and -pie by default.\n\nconfig GCC_DEFAULT_SSP\n\tbool\n\tprompt \"Build executable with Stack-Smashing Protection enabled by default\" if TOOLCHAINOPTS\n\tdefault n\n\thelp\n\t    Use gcc configure option --enable-default-ssp to turn on -fstack-protector-strong by default.\n\nconfig SJLJ_EXCEPTIONS\n\tbool\n\tprompt \"Use setjump()/longjump() exceptions\" if TOOLCHAINOPTS\n\tdefault n\n\thelp\n\t    Use old setjump()/longjump() exceptions instead of the newer\n\t    frame unwinding exceptions handling routines.  Warning: increases\n\t    code size and runtime memory usage.\n\nconfig INSTALL_GFORTRAN\n\tbool\n\tprompt \"Build/install fortran compiler?\" if TOOLCHAINOPTS\n\tdefault n\n\thelp\n\t    Build/install GNU fortran compiler ?\n\nconfig INSTALL_GCCGO\n\tbool\n\tprompt \"Build/install Go compiler?\" if TOOLCHAINOPTS\n\tdepends on USE_GLIBC || BROKEN\n\tdefault n\n\thelp\n\t    Build/install GNU gccgo compiler ?\n"
  },
  {
    "path": "toolchain/gcc/Config.version",
    "content": "config GCC_VERSION_8\n\tdefault y if GCC_USE_VERSION_8\n\tbool\n\nconfig GCC_VERSION_10\n\tdefault y if GCC_USE_VERSION_10\n\tbool\n\nconfig GCC_VERSION\n\tstring\n\tdefault \"8.4.0\"\t\tif GCC_VERSION_8\n\tdefault \"10.3.0\"\tif GCC_VERSION_10\n\tdefault \"11.2.0\"\n"
  },
  {
    "path": "toolchain/gcc/common.mk",
    "content": "#\n# Copyright (C) 2002-2003 Erik Andersen <andersen@uclibc.org>\n# Copyright (C) 2004 Manuel Novoa III <mjn3@uclibc.org>\n# Copyright (C) 2005-2006 Felix Fietkau <nbd@nbd.name>\n# Copyright (C) 2006-2014 OpenWrt.org\n#\n# This program is free software; you can redistribute it and/or modify\n# it under the terms of the GNU General Public License as published by\n# the Free Software Foundation; either version 2 of the License, or\n# (at your option) any later version.\n#\n# This program is distributed in the hope that it will be useful,\n# but WITHOUT ANY WARRANTY; without even the implied warranty of\n# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU\n# General Public License for more details.\n#\n# You should have received a copy of the GNU General Public License\n# along with this program; if not, write to the Free Software\n# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=gcc\nGCC_VERSION:=$(call qstrip,$(CONFIG_GCC_VERSION))\nPKG_VERSION:=$(firstword $(subst +, ,$(GCC_VERSION)))\nGCC_DIR:=$(PKG_NAME)-$(PKG_VERSION)\n\nPKG_SOURCE_URL:=@GNU/gcc/gcc-$(PKG_VERSION)\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz\n\nifeq ($(PKG_VERSION),8.4.0)\n  PKG_HASH:=e30a6e52d10e1f27ed55104ad233c30bd1e99cfb5ff98ab022dc941edd1b2dd4\nendif\n\nifeq ($(PKG_VERSION),10.3.0)\n  PKG_HASH:=64f404c1a650f27fc33da242e1f2df54952e3963a49e06e73f6940f3223ac344\nendif\n\nifeq ($(PKG_VERSION),11.2.0)\n  PKG_HASH:=d08edc536b54c372a1010ff6619dd274c0f1603aa49212ba20f7aa2cda36fa8b\nendif\n\nPATCH_DIR=../patches/$(GCC_VERSION)\n\nBUGURL=http://bugs.openwrt.org/\nPKGVERSION=OpenWrt GCC $(PKG_VERSION) $(REVISION)\n\nHOST_BUILD_PARALLEL:=1\n\ninclude $(INCLUDE_DIR)/toolchain-build.mk\n\nHOST_SOURCE_DIR:=$(HOST_BUILD_DIR)\nifeq ($(GCC_VARIANT),minimal)\n  GCC_BUILD_DIR:=$(HOST_BUILD_DIR)-$(GCC_VARIANT)\nelse\n  HOST_BUILD_DIR:=$(HOST_BUILD_DIR)-$(GCC_VARIANT)\n  GCC_BUILD_DIR:=$(HOST_BUILD_DIR)\nendif\n\nHOST_STAMP_PREPARED:=$(HOST_BUILD_DIR)/.prepared\nHOST_STAMP_BUILT:=$(GCC_BUILD_DIR)/.built\nHOST_STAMP_CONFIGURED:=$(GCC_BUILD_DIR)/.configured\nHOST_STAMP_INSTALLED:=$(HOST_BUILD_PREFIX)/stamp/.gcc_$(GCC_VARIANT)_installed\n\nSEP:=,\nTARGET_LANGUAGES:=\"c,c++$(if $(CONFIG_INSTALL_GFORTRAN),$(SEP)fortran)$(if $(CONFIG_INSTALL_GCCGO),$(SEP)go)\"\n\nTAR_OPTIONS += \\\n\t--exclude-from='$(CURDIR)/../exclude-testsuite' --exclude=gcc/ada/*.ad* \\\n\t--exclude=libjava\n\nexport libgcc_cv_fixed_point=no\nifdef CONFIG_INSTALL_GCCGO\n  export libgo_cv_c_split_stack_supported=no\nendif\n\nifdef CONFIG_GCC_USE_GRAPHITE\n  GRAPHITE_CONFIGURE:= --with-isl=$(TOPDIR)/staging_dir/host\nelse\n  GRAPHITE_CONFIGURE:= --without-isl --without-cloog\nendif\n\nGCC_CONFIGURE:= \\\n\tSHELL=\"$(BASH)\" \\\n\t$(if $(shell gcc --version 2>&1 | grep -E \"Apple.(LLVM|clang)\"), \\\n\t\tCFLAGS=\"-O2 -fbracket-depth=512 -pipe\" \\\n\t\tCXXFLAGS=\"-O2 -fbracket-depth=512 -pipe\" \\\n\t) \\\n\t$(HOST_SOURCE_DIR)/configure \\\n\t\t--with-bugurl=$(BUGURL) \\\n\t\t--with-pkgversion=\"$(PKGVERSION)\" \\\n\t\t--prefix=$(TOOLCHAIN_DIR) \\\n\t\t--build=$(GNU_HOST_NAME) \\\n\t\t--host=$(GNU_HOST_NAME) \\\n\t\t--target=$(REAL_GNU_TARGET_NAME) \\\n\t\t--with-gnu-ld \\\n\t\t--enable-target-optspace \\\n\t\t--disable-libgomp \\\n\t\t--disable-libmudflap \\\n\t\t--disable-multilib \\\n\t\t--disable-libmpx \\\n\t\t--disable-nls \\\n\t\t--disable-libssp \\\n\t\t$(GRAPHITE_CONFIGURE) \\\n\t\t--with-host-libstdcxx=-lstdc++ \\\n\t\t$(SOFT_FLOAT_CONFIG_OPTION) \\\n\t\t$(call qstrip,$(CONFIG_EXTRA_GCC_CONFIG_OPTIONS)) \\\n\t\t$(if $(CONFIG_mips64)$(CONFIG_mips64el),--with-arch=mips64 \\\n\t\t\t--with-abi=$(call qstrip,$(CONFIG_MIPS64_ABI))) \\\n\t\t$(if $(CONFIG_arc),--with-cpu=$(CONFIG_CPU_TYPE)) \\\n\t\t$(if $(CONFIG_powerpc64), $(if $(CONFIG_USE_MUSL),--with-abi=elfv2)) \\\n\t\t--with-gmp=$(TOPDIR)/staging_dir/host \\\n\t\t--with-mpfr=$(TOPDIR)/staging_dir/host \\\n\t\t--with-mpc=$(TOPDIR)/staging_dir/host \\\n\t\t--disable-decimal-float \\\n\t\t--with-diagnostics-color=auto-if-env \\\n\t\t--enable-__cxa_atexit \\\n\t\t--disable-libstdcxx-dual-abi \\\n\t\t--with-default-libstdcxx-abi=new\nifneq ($(CONFIG_mips)$(CONFIG_mipsel),)\n  GCC_CONFIGURE += --with-mips-plt\nendif\n\nifneq ($(CONFIG_GCC_DEFAULT_PIE),)\n  GCC_CONFIGURE+= \\\n\t\t--enable-default-pie\nendif\n\nifneq ($(CONFIG_GCC_DEFAULT_SSP),)\n  GCC_CONFIGURE+= \\\n\t\t--enable-default-ssp\nendif\n\nifneq ($(CONFIG_EXTRA_TARGET_ARCH),)\n  GCC_CONFIGURE+= \\\n\t\t--enable-biarch \\\n\t\t--enable-targets=$(call qstrip,$(CONFIG_EXTRA_TARGET_ARCH_NAME))-linux-$(TARGET_SUFFIX)\nendif\n\nifdef CONFIG_sparc\n  GCC_CONFIGURE+= \\\n\t\t--enable-targets=all \\\n\t\t--with-long-double-128\nendif\n\nifneq ($(GCC_ARCH),)\n  GCC_CONFIGURE+= --with-arch=$(GCC_ARCH)\nendif\n\nifeq ($(CONFIG_arm),y)\n  GCC_CONFIGURE+= \\\n\t--with-cpu=$(word 1, $(subst +,\" ,$(CONFIG_CPU_TYPE)))\n\n  ifneq ($(CONFIG_SOFT_FLOAT),y)\n    GCC_CONFIGURE+= \\\n\t\t--with-fpu=$(word 2, $(subst +, \",$(CONFIG_CPU_TYPE))) \\\n\t\t--with-float=hard\n  endif\n\n  # Do not let TARGET_CFLAGS get poisoned by extra CPU optimization flags\n  # that do not belong here. The cpu,fpu type should be specified via\n  # --with-cpu and --with-fpu for ARM and not CFLAGS.\n  TARGET_CFLAGS:=$(filter-out -m%,$(call qstrip,$(TARGET_CFLAGS)))\nendif\n\nifeq ($(CONFIG_TARGET_x86)$(CONFIG_USE_GLIBC)$(CONFIG_INSTALL_GCCGO),yyy)\n  TARGET_CFLAGS+=-fno-split-stack\nendif\n\nGCC_MAKE:= \\\n\texport SHELL=\"$(BASH)\"; \\\n\t$(MAKE) \\\n\t\tCFLAGS=\"$(HOST_CFLAGS)\" \\\n\t\tCFLAGS_FOR_TARGET=\"$(TARGET_CFLAGS)\" \\\n\t\tCXXFLAGS_FOR_TARGET=\"$(TARGET_CFLAGS)\" \\\n\t\tGOCFLAGS_FOR_TARGET=\"$(TARGET_CFLAGS)\"\n\ndefine Host/SetToolchainInfo\n\t$(SED) 's,TARGET_CROSS=.*,TARGET_CROSS=$(REAL_GNU_TARGET_NAME)-,' $(TOOLCHAIN_DIR)/info.mk\n\t$(SED) 's,GCC_VERSION=.*,GCC_VERSION=$(GCC_VERSION),' $(TOOLCHAIN_DIR)/info.mk\nendef\n\nifneq ($(GCC_PREPARE),)\n  define Host/Prepare\n\t$(call Host/SetToolchainInfo)\n\t$(call Host/Prepare/Default)\n\tln -snf $(GCC_DIR) $(BUILD_DIR_TOOLCHAIN)/$(PKG_NAME)\n\t$(CP) $(SCRIPT_DIR)/config.{guess,sub} $(HOST_SOURCE_DIR)/\n\t$(SED) 's,^MULTILIB_OSDIRNAMES,# MULTILIB_OSDIRNAMES,' $(HOST_SOURCE_DIR)/gcc/config/*/t-*\n\t$(SED) 'd' $(HOST_SOURCE_DIR)/gcc/DEV-PHASE\n\t$(SED) 's, DATESTAMP,,' $(HOST_SOURCE_DIR)/gcc/version.c\n\t#(cd $(HOST_SOURCE_DIR)/libstdc++-v3; autoconf;);\n\t$(SED) 's,gcc_no_link=yes,gcc_no_link=no,' $(HOST_SOURCE_DIR)/libstdc++-v3/configure\n\tmkdir -p $(GCC_BUILD_DIR)\n  endef\nelse\n  define Host/Prepare\n\tmkdir -p $(GCC_BUILD_DIR)\n  endef\nendif\n\ndefine Host/Configure\n\t(cd $(GCC_BUILD_DIR) && rm -f config.cache; \\\n\t\t$(GCC_CONFIGURE) \\\n\t);\nendef\n\ndefine Host/Clean\n\trm -rf $(if $(GCC_PREPARE),$(HOST_SOURCE_DIR)) \\\n\t\t$(HOST_BUILD_PREFIX)/stamp/.gcc_* \\\n\t\t$(HOST_BUILD_PREFIX)/stamp/.binutils_* \\\n\t\t$(GCC_BUILD_DIR) \\\n\t\t$(BUILD_DIR_TOOLCHAIN)/$(PKG_NAME) \\\n\t\t$(TOOLCHAIN_DIR)/$(REAL_GNU_TARGET_NAME) \\\n\t\t$(TOOLCHAIN_DIR)/bin/$(REAL_GNU_TARGET_NAME)-gc* \\\n\t\t$(TOOLCHAIN_DIR)/bin/$(REAL_GNU_TARGET_NAME)-c*\nendef\n"
  },
  {
    "path": "toolchain/gcc/exclude-testsuite",
    "content": "gcc-*/gcc/testsuite/ada\ngcc-*/gcc/testsuite/brig.dg\ngcc-*/gcc/testsuite/c-c++-common\ngcc-*/gcc/testsuite/ChangeLog*\ngcc-*/gcc/testsuite/config\ngcc-*/gcc/testsuite/g*\ngcc-*/gcc/testsuite/jit.dg\ngcc-*/gcc/testsuite/lib\ngcc-*/gcc/testsuite/o*\n"
  },
  {
    "path": "toolchain/gcc/files/alternate-arch-cc.in",
    "content": "#!/bin/sh\n\nexec @CC_BASE@ @EXTRA_ARCH_OPTS@ \"$@\"\n"
  },
  {
    "path": "toolchain/gcc/final/Makefile",
    "content": "GCC_VARIANT:=final\n\ninclude ../common.mk\n\nGCC_CONFIGURE += \\\n\t--with-headers=$(TOOLCHAIN_DIR)/include \\\n\t--enable-languages=$(TARGET_LANGUAGES) \\\n\t--enable-shared \\\n\t--enable-threads \\\n\t--with-slibdir=$(TOOLCHAIN_DIR)/lib \\\n\t--enable-lto \\\n\t--with-libelf=$(TOPDIR)/staging_dir/host\n\nifndef CONFIG_USE_GLIBC\n  GCC_CONFIGURE += --disable-libsanitizer\nendif\n\nifdef CONFIG_USE_MUSL\n  GCC_MAKE += gcc_cv_libc_provides_ssp=yes\nendif\n\nifneq ($(CONFIG_SJLJ_EXCEPTIONS),)\n  GCC_CONFIGURE += \\\n\t--enable-sjlj-exceptions\nendif\n\ndefine CleanupToolchain\n\t$(INSTALL_DIR) $(TOOLCHAIN_DIR)/$(REAL_GNU_TARGET_NAME)\n\t# Important!  Required for limits.h to be fixed.\n\trm -rf $(TOOLCHAIN_DIR)/$(REAL_GNU_TARGET_NAME)/sys-include\n\tln -sf ../include $(TOOLCHAIN_DIR)/$(REAL_GNU_TARGET_NAME)/sys-include\n\trm -rf $(TOOLCHAIN_DIR)/$(REAL_GNU_TARGET_NAME)/lib\n\tln -sf ../lib $(TOOLCHAIN_DIR)/$(REAL_GNU_TARGET_NAME)/lib\n\t$(if $(CONFIG_ARCH_64BIT),ln -sf ../lib64 $(TOOLCHAIN_DIR)/$(REAL_GNU_TARGET_NAME)/lib64)\nendef\n\ndefine Host/Configure\n\t$(CleanupToolchain)\n\tmkdir -p $(GCC_BUILD_DIR)\n\t(cd $(GCC_BUILD_DIR) && rm -f config.cache; \\\n\t\t$(GCC_CONFIGURE) \\\n\t);\nendef\n\nifeq ($(CONFIG_USE_GLIBC)$(CONFIG_INSTALL_GCCGO),yy)\ndefine FixGogccCrt\n\t# link crtX.o for gotools\n\tmkdir -p $(GCC_BUILD_DIR)/gotools\n\t$(foreach crt, i 1 n, ln -sf ../../glibc-dev/lib/crt$(crt).o $(GCC_BUILD_DIR)/gotools/ ; )\nendef\nendif\n\ndefine Host/Compile\n\t$(FixGogccCrt)\n\t+$(GCC_MAKE) $(HOST_JOBS) -C $(GCC_BUILD_DIR) all\nendef\n\ndefine SetupExtraArch\n\tfor app in $(TOOLCHAIN_DIR)/bin/$(OPTIMIZE_FOR_CPU)*-{gcc,gcc-*,g++}; do \\\n\t\t[ -e $$$$app ] || continue; \\\n\t\told_base=$$$$(basename $$$$app); \\\n\t\tnew_base=$(call qstrip,$(CONFIG_EXTRA_TARGET_ARCH_NAME))-$$$${old_base##$(OPTIMIZE_FOR_CPU)-}; \\\n\t\tsed -e \"s/@CC_BASE@/$$$$old_base/\" \\\n\t\t\t-e 's/@EXTRA_ARCH_OPTS@/$(call qstrip,$(CONFIG_EXTRA_TARGET_ARCH_OPTS))/' \\\n\t\t\t ../files/alternate-arch-cc.in > \\\n\t\t\t $(TOOLCHAIN_DIR)/bin/$$$$new_base; \\\n\t\tchmod a+x $(TOOLCHAIN_DIR)/bin/$$$$new_base; \\\n\tdone\nendef\n\ndefine Host/Install\n\t$(CleanupToolchain)\n\t+$(GCC_MAKE) $(HOST_JOBS) -C $(GCC_BUILD_DIR) install\n\t# Set up the symlinks to enable lying about target name.\n\tset -e; \\\n\t(cd $(TOOLCHAIN_DIR); \\\n\t\tln -sf $(REAL_GNU_TARGET_NAME) $(GNU_TARGET_NAME); \\\n\t\tcd bin; \\\n\t\tfor app in $(REAL_GNU_TARGET_NAME)-* ; do \\\n\t\t\tln -sf $$$${app} \\\n\t\t   \t$(GNU_TARGET_NAME)$$$${app##$(REAL_GNU_TARGET_NAME)}; \\\n\t\tdone; \\\n\t);\n\t$(if $(CONFIG_EXTRA_TARGET_ARCH),$(call SetupExtraArch))\n\t$(RM) $(TOOLCHAIN_DIR)/lib/libiberty.a\n\t$(SCRIPT_DIR)/patch-specs.sh \"$(TOOLCHAIN_DIR)\"\nendef\n\n$(eval $(call HostBuild))\n\n"
  },
  {
    "path": "toolchain/gcc/initial/Makefile",
    "content": "GCC_VARIANT:=initial\nGCC_PREPARE=$(CONFIG_USE_MUSL)\n\ninclude ../common.mk\n\nGCC_CONFIGURE += \\\n\t--with-newlib \\\n\t--with-sysroot=$(TOOLCHAIN_DIR) \\\n\t--enable-languages=c \\\n\t--disable-shared \\\n\t--disable-threads \\\n\ndefine Host/Compile\n\t+$(GCC_MAKE) $(HOST_JOBS) -C $(GCC_BUILD_DIR) \\\n\t\tall-build-libiberty \\\n\t\tall-gcc \\\n\t\tall-target-libgcc\nendef\n\ndefine Host/Install\n\t+$(GCC_MAKE) $(HOST_JOBS) -C $(GCC_BUILD_DIR) \\\n\t\tprefix=\"$(TOOLCHAIN_DIR)/initial\" \\\n\t\tinstall-gcc \\\n\t\tinstall-target-libgcc\n\n\t# XXX: glibc insists on linking against libgcc_eh\n\t( cd $(TOOLCHAIN_DIR)/initial/lib/gcc/$(REAL_GNU_TARGET_NAME)/$(PKG_VERSION) ; \\\n\t\t[ -e libgcc_eh.a ] || ln -sf libgcc.a libgcc_eh.a ; \\\n\t\tcp libgcc.a libgcc_initial.a; \\\n\t)\n\n\t$(call FixupLibdir,$(TOOLCHAIN_DIR)/initial)\n\t$$(call file_copy,$(TOOLCHAIN_DIR)/initial/.,$(TOOLCHAIN_DIR)/)\nendef\n\n$(eval $(call HostBuild))\n"
  },
  {
    "path": "toolchain/gcc/minimal/Makefile",
    "content": "GCC_VARIANT:=minimal\nGCC_PREPARE=$(if $(CONFIG_USE_MUSL),,1)\n\ninclude ../common.mk\n\nGCC_CONFIGURE += \\\n\t--with-newlib \\\n\t--without-headers \\\n\t--enable-languages=c \\\n\t--disable-libsanitizer \\\n\t--disable-libssp \\\n\t--disable-shared \\\n\t--disable-threads\n\ndefine Host/Compile\n\t+$(GCC_MAKE) $(HOST_JOBS) -C $(GCC_BUILD_DIR) all-gcc all-target-libgcc\nendef\n\ndefine Host/Install\n\t$(GCC_MAKE) -C $(GCC_BUILD_DIR) install-gcc install-target-libgcc\nendef\n\ndefine Host/Clean\n\trm -rf \\\n\t\t$(HOST_BUILD_DIR) \\\n\t\t$(GCC_BUILD_DIR)\nendef\n\n$(eval $(call HostBuild))\n"
  },
  {
    "path": "toolchain/gcc/patches/10.3.0/002-case_insensitive.patch",
    "content": "commit 81cc26c706b2bc8c8c1eb1a322e5c5157900836e\nAuthor: Felix Fietkau <nbd@openwrt.org>\nDate:   Sun Oct 19 21:45:51 2014 +0000\n\n    gcc: do not assume that the Mac OS X filesystem is case insensitive\n    \n    Signed-off-by: Felix Fietkau <nbd@openwrt.org>\n    \n    SVN-Revision: 42973\n\n--- a/include/filenames.h\n+++ b/include/filenames.h\n@@ -44,11 +44,6 @@ extern \"C\" {\n #  define IS_DIR_SEPARATOR(c) IS_DOS_DIR_SEPARATOR (c)\n #  define IS_ABSOLUTE_PATH(f) IS_DOS_ABSOLUTE_PATH (f)\n #else /* not DOSish */\n-#  if defined(__APPLE__)\n-#    ifndef HAVE_CASE_INSENSITIVE_FILE_SYSTEM\n-#      define HAVE_CASE_INSENSITIVE_FILE_SYSTEM 1\n-#    endif\n-#  endif /* __APPLE__ */\n #  define HAS_DRIVE_SPEC(f) (0)\n #  define IS_DIR_SEPARATOR(c) IS_UNIX_DIR_SEPARATOR (c)\n #  define IS_ABSOLUTE_PATH(f) IS_UNIX_ABSOLUTE_PATH (f)\n"
  },
  {
    "path": "toolchain/gcc/patches/10.3.0/010-documentation.patch",
    "content": "commit 098bd91f5eae625c7d2ee621e10930fc4434e5e2\nAuthor: Luka Perkov <luka@openwrt.org>\nDate:   Tue Feb 26 16:16:33 2013 +0000\n\n    gcc: don't build documentation\n    \n    This closes #13039.\n    \n    Signed-off-by: Luka Perkov <luka@openwrt.org>\n    \n    SVN-Revision: 35807\n\n--- a/gcc/Makefile.in\n+++ b/gcc/Makefile.in\n@@ -3285,18 +3285,10 @@ doc/gcc.info: $(TEXI_GCC_FILES)\n doc/gccint.info: $(TEXI_GCCINT_FILES)\n doc/cppinternals.info: $(TEXI_CPPINT_FILES)\n \n-doc/%.info: %.texi\n-\tif [ x$(BUILD_INFO) = xinfo ]; then \\\n-\t\t$(MAKEINFO) $(MAKEINFOFLAGS) -I . -I $(gcc_docdir) \\\n-\t\t\t-I $(gcc_docdir)/include -o $@ $<; \\\n-\tfi\n+doc/%.info:\n \n # Duplicate entry to handle renaming of gccinstall.info\n-doc/gccinstall.info: $(TEXI_GCCINSTALL_FILES)\n-\tif [ x$(BUILD_INFO) = xinfo ]; then \\\n-\t\t$(MAKEINFO) $(MAKEINFOFLAGS) -I $(gcc_docdir) \\\n-\t\t\t-I $(gcc_docdir)/include -o $@ $<; \\\n-\tfi\n+doc/gccinstall.info:\n \n doc/cpp.dvi: $(TEXI_CPP_FILES)\n doc/gcc.dvi: $(TEXI_GCC_FILES)\n"
  },
  {
    "path": "toolchain/gcc/patches/10.3.0/110-Fix-MIPS-PR-84790.patch",
    "content": "Fix https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84790.\nMIPS16 functions have a static assembler prologue which clobbers\nregisters v0 and v1. Add these register clobbers to function call\ninstructions.\n\n--- a/gcc/config/mips/mips.c\n+++ b/gcc/config/mips/mips.c\n@@ -3132,6 +3132,12 @@ mips_emit_call_insn (rtx pattern, rtx or\n       emit_insn (gen_update_got_version ());\n     }\n \n+  if (TARGET_MIPS16 && TARGET_USE_GOT)\n+    {\n+      clobber_reg (&CALL_INSN_FUNCTION_USAGE (insn), MIPS16_PIC_TEMP);\n+      clobber_reg (&CALL_INSN_FUNCTION_USAGE (insn), MIPS_PROLOGUE_TEMP (word_mode));\n+    }\n+\n   if (TARGET_MIPS16\n       && TARGET_EXPLICIT_RELOCS\n       && TARGET_CALL_CLOBBERED_GP)\n"
  },
  {
    "path": "toolchain/gcc/patches/10.3.0/230-musl_libssp.patch",
    "content": "--- a/gcc/gcc.c\n+++ b/gcc/gcc.c\n@@ -875,7 +875,9 @@ proper position among the other output f\n #endif\n \n #ifndef LINK_SSP_SPEC\n-#ifdef TARGET_LIBC_PROVIDES_SSP\n+#if DEFAULT_LIBC == LIBC_MUSL\n+#define LINK_SSP_SPEC \"-lssp_nonshared\"\n+#elif defined(TARGET_LIBC_PROVIDES_SSP)\n #define LINK_SSP_SPEC \"%{fstack-protector|fstack-protector-all\" \\\n \t\t       \"|fstack-protector-strong|fstack-protector-explicit:}\"\n #else\n"
  },
  {
    "path": "toolchain/gcc/patches/10.3.0/300-mips_Os_cpu_rtx_cost_model.patch",
    "content": "commit ecf7671b769fe96f7b5134be442089f8bdba55d2\nAuthor: Felix Fietkau <nbd@nbd.name>\nDate:   Thu Aug 4 20:29:45 2016 +0200\n\ngcc: add a patch to generate better code with Os on mips\n\nAlso happens to reduce compressed code size a bit\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n\n--- a/gcc/config/mips/mips.c\n+++ b/gcc/config/mips/mips.c\n@@ -20041,7 +20041,7 @@ mips_option_override (void)\n     flag_pcc_struct_return = 0;\n \n   /* Decide which rtx_costs structure to use.  */\n-  if (optimize_size)\n+  if (0 && optimize_size)\n     mips_cost = &mips_rtx_cost_optimize_size;\n   else\n     mips_cost = &mips_rtx_cost_data[mips_tune];\n"
  },
  {
    "path": "toolchain/gcc/patches/10.3.0/810-arm-softfloat-libgcc.patch",
    "content": "commit 8570c4be394cff7282f332f97da2ff569a927ddb\nAuthor: Imre Kaloz <kaloz@openwrt.org>\nDate:   Wed Feb 2 20:06:12 2011 +0000\n\n    fixup arm soft-float symbols\n    \n    SVN-Revision: 25325\n\n--- a/libgcc/config/arm/t-linux\n+++ b/libgcc/config/arm/t-linux\n@@ -1,6 +1,10 @@\n LIB1ASMSRC = arm/lib1funcs.S\n LIB1ASMFUNCS = _udivsi3 _divsi3 _umodsi3 _modsi3 _dvmd_lnx _clzsi2 _clzdi2 \\\n-\t_ctzsi2 _arm_addsubdf3 _arm_addsubsf3\n+\t_ctzsi2 _arm_addsubdf3 _arm_addsubsf3 \\\n+\t_arm_negdf2 _arm_muldivdf3 _arm_cmpdf2 _arm_unorddf2 \\\n+\t_arm_fixdfsi _arm_fixunsdfsi _arm_truncdfsf2 \\\n+\t_arm_negsf2 _arm_muldivsf3 _arm_cmpsf2 _arm_unordsf2 \\\n+\t_arm_fixsfsi _arm_fixunssfsi\n \n # Just for these, we omit the frame pointer since it makes such a big\n # difference.\n--- a/gcc/config/arm/linux-elf.h\n+++ b/gcc/config/arm/linux-elf.h\n@@ -58,8 +58,6 @@\n    %{shared:-lc} \\\n    %{!shared:%{profile:-lc_p}%{!profile:-lc}}\"\n \n-#define LIBGCC_SPEC \"%{mfloat-abi=soft*:-lfloat} -lgcc\"\n-\n #define GLIBC_DYNAMIC_LINKER \"/lib/ld-linux.so.2\"\n \n #define LINUX_TARGET_LINK_SPEC  \"%{h*} \\\n"
  },
  {
    "path": "toolchain/gcc/patches/10.3.0/820-libgcc_pic.patch",
    "content": "commit c96312958c0621e72c9b32da5bc224ffe2161384\nAuthor: Felix Fietkau <nbd@openwrt.org>\nDate:   Mon Oct 19 23:26:09 2009 +0000\n\n    gcc: create a proper libgcc_pic.a static library for relinking (4.3.3+ for now, backport will follow)\n    \n    SVN-Revision: 18086\n\n--- a/libgcc/Makefile.in\n+++ b/libgcc/Makefile.in\n@@ -929,11 +929,12 @@ $(libgcov-driver-objects): %$(objext): $\n \n # Static libraries.\n libgcc.a: $(libgcc-objects)\n+libgcc_pic.a: $(libgcc-s-objects)\n libgcov.a: $(libgcov-objects)\n libunwind.a: $(libunwind-objects)\n libgcc_eh.a: $(libgcc-eh-objects)\n \n-libgcc.a libgcov.a libunwind.a libgcc_eh.a:\n+libgcc.a libgcov.a libunwind.a libgcc_eh.a libgcc_pic.a:\n \t-rm -f $@\n \n \tobjects=\"$(objects)\";\t\t\t\t\t\\\n@@ -957,7 +958,7 @@ all: libunwind.a\n endif\n \n ifeq ($(enable_shared),yes)\n-all: libgcc_eh.a libgcc_s$(SHLIB_EXT)\n+all: libgcc_eh.a libgcc_pic.a libgcc_s$(SHLIB_EXT)\n ifneq ($(LIBUNWIND),)\n all: libunwind$(SHLIB_EXT)\n libgcc_s$(SHLIB_EXT): libunwind$(SHLIB_EXT)\n@@ -1163,6 +1164,10 @@ install-shared:\n \tchmod 644 $(DESTDIR)$(inst_libdir)/libgcc_eh.a\n \t$(RANLIB) $(DESTDIR)$(inst_libdir)/libgcc_eh.a\n \n+\t$(INSTALL_DATA) libgcc_pic.a $(mapfile) $(DESTDIR)$(inst_libdir)/\n+\tchmod 644 $(DESTDIR)$(inst_libdir)/libgcc_pic.a\n+\t$(RANLIB) $(DESTDIR)$(inst_libdir)/libgcc_pic.a\n+\n \t$(subst @multilib_dir@,$(MULTIDIR),$(subst \\\n \t\t@shlib_base_name@,libgcc_s,$(subst \\\n \t\t@shlib_slibdir_qual@,$(MULTIOSSUBDIR),$(SHLIB_INSTALL))))\n"
  },
  {
    "path": "toolchain/gcc/patches/10.3.0/840-armv4_pass_fix-v4bx_to_ld.patch",
    "content": "commit 7edc8ca5456d9743dd0075eb3cc5b04f4f24c8cc\nAuthor: Imre Kaloz <kaloz@openwrt.org>\nDate:   Wed Feb 2 19:34:36 2011 +0000\n\n    add armv4 fixup patches\n    \n    SVN-Revision: 25322\n\n\n--- a/gcc/config/arm/linux-eabi.h\n+++ b/gcc/config/arm/linux-eabi.h\n@@ -91,10 +91,15 @@\n #define MUSL_DYNAMIC_LINKER \\\n   \"/lib/ld-musl-arm\" MUSL_DYNAMIC_LINKER_E \"%{mfloat-abi=hard:hf}%{mfdpic:-fdpic}.so.1\"\n \n+/* For armv4 we pass --fix-v4bx to linker to support EABI */\n+#undef TARGET_FIX_V4BX_SPEC\n+#define TARGET_FIX_V4BX_SPEC \" %{mcpu=arm8|mcpu=arm810|mcpu=strongarm*\"\\\n+  \"|march=armv4|mcpu=fa526|mcpu=fa626:--fix-v4bx}\"\n+\n /* At this point, bpabi.h will have clobbered LINK_SPEC.  We want to\n    use the GNU/Linux version, not the generic BPABI version.  */\n #undef  LINK_SPEC\n-#define LINK_SPEC EABI_LINK_SPEC\t\t\t\t\t\\\n+#define LINK_SPEC EABI_LINK_SPEC TARGET_FIX_V4BX_SPEC\t\t\t\\\n   LINUX_OR_ANDROID_LD (LINUX_TARGET_LINK_SPEC,\t\t\t\t\\\n \t\t       LINUX_TARGET_LINK_SPEC \" \" ANDROID_LINK_SPEC)\n \n"
  },
  {
    "path": "toolchain/gcc/patches/10.3.0/850-use_shared_libgcc.patch",
    "content": "commit dcfc40358b5a3cae7320c17f8d1cebd5ad5540cd\nAuthor: Felix Fietkau <nbd@openwrt.org>\nDate:   Sun Feb 12 20:25:47 2012 +0000\n\n    gcc 4.6: port over the missing patch 850-use_shared_libgcc.patch to prevent libgcc crap from leaking into every single binary\n    \n    SVN-Revision: 30486\n--- a/gcc/config/arm/linux-eabi.h\n+++ b/gcc/config/arm/linux-eabi.h\n@@ -132,10 +132,6 @@\n   \"%{Ofast|ffast-math|funsafe-math-optimizations:crtfastmath.o%s} \"\t\\\n   LINUX_OR_ANDROID_LD (GNU_USER_TARGET_ENDFILE_SPEC, ANDROID_ENDFILE_SPEC)\n \n-/* Use the default LIBGCC_SPEC, not the version in linux-elf.h, as we\n-   do not use -lfloat.  */\n-#undef LIBGCC_SPEC\n-\n /* Clear the instruction cache from `beg' to `end'.  This is\n    implemented in lib1funcs.S, so ensure an error if this definition\n    is used.  */\n--- a/gcc/config/linux.h\n+++ b/gcc/config/linux.h\n@@ -66,6 +66,10 @@ see the files COPYING3 and COPYING.RUNTI\n \t  builtin_version (\"CRuntime_Musl\");\t\t\t\\\n     } while (0)\n \n+#ifndef LIBGCC_SPEC\n+#define LIBGCC_SPEC \"%{static|static-libgcc:-lgcc}%{!static:%{!static-libgcc:-lgcc_s}}\"\n+#endif\n+\n /* Determine which dynamic linker to use depending on whether GLIBC or\n    uClibc or Bionic or musl is the default C library and whether\n    -muclibc or -mglibc or -mbionic or -mmusl has been passed to change\n--- a/libgcc/mkmap-symver.awk\n+++ b/libgcc/mkmap-symver.awk\n@@ -136,5 +136,5 @@ function output(lib) {\n   else if (inherit[lib])\n     printf(\"} %s;\\n\", inherit[lib]);\n   else\n-    printf (\"\\n  local:\\n\\t*;\\n};\\n\");\n+    printf (\"\\n\\t*;\\n};\\n\");\n }\n--- a/gcc/config/rs6000/linux.h\n+++ b/gcc/config/rs6000/linux.h\n@@ -62,6 +62,9 @@\n #undef\tCPP_OS_DEFAULT_SPEC\n #define CPP_OS_DEFAULT_SPEC \"%(cpp_os_linux)\"\n \n+#undef LIBGCC_SPEC\n+#define LIBGCC_SPEC \"%{!static:%{!static-libgcc:-lgcc_s}} -lgcc\"\n+\n #undef  LINK_SHLIB_SPEC\n #define LINK_SHLIB_SPEC \"%{shared:-shared} %{!shared: %{static:-static}} \\\n   %{static-pie:-static -pie --no-dynamic-linker -z text}\"\n"
  },
  {
    "path": "toolchain/gcc/patches/10.3.0/851-libgcc_no_compat.patch",
    "content": "commit 64661de100da1ec1061ef3e5e400285dce115e6b\nAuthor: Felix Fietkau <nbd@openwrt.org>\nDate:   Sun May 10 13:16:35 2015 +0000\n\n    gcc: add some size optimization patches\n    \n    Signed-off-by: Felix Fietkau <nbd@openwrt.org>\n    \n    SVN-Revision: 45664\n\n--- a/libgcc/config/t-libunwind\n+++ b/libgcc/config/t-libunwind\n@@ -2,8 +2,7 @@\n \n HOST_LIBGCC2_CFLAGS += -DUSE_GAS_SYMVER\n \n-LIB2ADDEH = $(srcdir)/unwind-sjlj.c $(srcdir)/unwind-c.c \\\n-  $(srcdir)/unwind-compat.c $(srcdir)/unwind-dw2-fde-compat.c\n+LIB2ADDEH = $(srcdir)/unwind-sjlj.c $(srcdir)/unwind-c.c\n LIB2ADDEHSTATIC = $(srcdir)/unwind-sjlj.c $(srcdir)/unwind-c.c\n \n # Override the default value from t-slibgcc-elf-ver and mention -lunwind\n"
  },
  {
    "path": "toolchain/gcc/patches/10.3.0/870-ppc_no_crtsavres.patch",
    "content": "--- a/gcc/config/rs6000/rs6000-logue.c\n+++ b/gcc/config/rs6000/rs6000-logue.c\n@@ -348,7 +348,7 @@ rs6000_savres_strategy (rs6000_stack_t *\n   /* Define cutoff for using out-of-line functions to save registers.  */\n   if (DEFAULT_ABI == ABI_V4 || TARGET_ELF)\n     {\n-      if (!optimize_size)\n+      if (1)\n \t{\n \t  strategy |= SAVE_INLINE_FPRS | REST_INLINE_FPRS;\n \t  strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;\n"
  },
  {
    "path": "toolchain/gcc/patches/10.3.0/881-no_tm_section.patch",
    "content": "--- a/libgcc/crtstuff.c\n+++ b/libgcc/crtstuff.c\n@@ -152,7 +152,7 @@ call_ ## FUNC (void)\t\t\t\t\t\\\n #endif\n \n #if !defined(USE_TM_CLONE_REGISTRY) && defined(OBJECT_FORMAT_ELF)\n-# define USE_TM_CLONE_REGISTRY 1\n+# define USE_TM_CLONE_REGISTRY 0\n #elif !defined(USE_TM_CLONE_REGISTRY)\n # define USE_TM_CLONE_REGISTRY 0\n #endif\n"
  },
  {
    "path": "toolchain/gcc/patches/10.3.0/900-bad-mips16-crt.patch",
    "content": "--- a/libgcc/config/mips/t-mips16\n+++ b/libgcc/config/mips/t-mips16\n@@ -43,3 +43,6 @@ SYNC_CFLAGS = -mno-mips16\n \n # Version these symbols if building libgcc.so.\n SHLIB_MAPFILES += $(srcdir)/config/mips/libgcc-mips16.ver\n+\n+CRTSTUFF_T_CFLAGS += -mno-mips16\n+CRTSTUFF_T_CFLAGS_S += -mno-mips16\n"
  },
  {
    "path": "toolchain/gcc/patches/10.3.0/910-mbsd_multi.patch",
    "content": "commit 99368862e44740ff4fd33760893f04e14f9dbdf1\nAuthor: Felix Fietkau <nbd@openwrt.org>\nDate:   Tue Jul 31 00:52:27 2007 +0000\n\n    Port the mbsd_multi patch from freewrt, which adds -fhonour-copts. This will emit warnings in packages that don't use our target cflags properly\n    \n    SVN-Revision: 8256\n\n\tThis patch brings over a feature from MirBSD:\n\t* -fhonour-copts\n\t  If this option is not given, it's warned (depending\n\t  on environment variables). This is to catch errors\n\t  of misbuilt packages which override CFLAGS themselves.\n\n\tThis patch was authored by Thorsten Glaser <tg at mirbsd.de>\n\twith copyright assignment to the FSF in effect.\n\n--- a/gcc/c-family/c-opts.c\n+++ b/gcc/c-family/c-opts.c\n@@ -107,6 +107,9 @@ static dump_flags_t original_dump_flags;\n /* Whether any standard preincluded header has been preincluded.  */\n static bool done_preinclude;\n \n+/* Check if a port honours COPTS.  */\n+static int honour_copts = 0;\n+\n static void handle_OPT_d (const char *);\n static void set_std_cxx98 (int);\n static void set_std_cxx11 (int);\n@@ -455,6 +458,12 @@ c_common_handle_option (size_t scode, co\n       flag_no_builtin = !value;\n       break;\n \n+    case OPT_fhonour_copts:\n+      if (c_language == clk_c) {\n+        honour_copts++;\n+      }\n+      break;\n+\n     case OPT_fconstant_string_class_:\n       constant_string_class_name = arg;\n       break;\n@@ -1168,6 +1177,47 @@ c_common_init (void)\n       return false;\n     }\n \n+  if (c_language == clk_c) {\n+    char *ev = getenv (\"GCC_HONOUR_COPTS\");\n+    int evv;\n+    if (ev == NULL)\n+      evv = -1;\n+    else if ((*ev == '0') || (*ev == '\\0'))\n+      evv = 0;\n+    else if (*ev == '1')\n+      evv = 1;\n+    else if (*ev == '2')\n+      evv = 2;\n+    else if (*ev == 's')\n+      evv = -1;\n+    else {\n+      warning (0, \"unknown GCC_HONOUR_COPTS value, assuming 1\");\n+      evv = 1; /* maybe depend this on something like MIRBSD_NATIVE?  */\n+    }\n+    if (evv == 1) {\n+      if (honour_copts == 0) {\n+        error (\"someone does not honour COPTS at all in lenient mode\");\n+        return false;\n+      } else if (honour_copts != 1) {\n+        warning (0, \"someone does not honour COPTS correctly, passed %d times\",\n+         honour_copts);\n+      }\n+    } else if (evv == 2) {\n+      if (honour_copts == 0) {\n+        error (\"someone does not honour COPTS at all in strict mode\");\n+        return false;\n+      } else if (honour_copts != 1) {\n+        error (\"someone does not honour COPTS correctly, passed %d times\",\n+         honour_copts);\n+        return false;\n+      }\n+    } else if (evv == 0) {\n+      if (honour_copts != 1)\n+        inform (UNKNOWN_LOCATION, \"someone does not honour COPTS correctly, passed %d times\",\n+         honour_copts);\n+    }\n+  }\n+\n   return true;\n }\n \n--- a/gcc/c-family/c.opt\n+++ b/gcc/c-family/c.opt\n@@ -1590,6 +1590,9 @@ C++ ObjC++ Optimization Alias(fexception\n fhonor-std\n C++ ObjC++ WarnRemoved\n \n+fhonour-copts\n+C ObjC C++ ObjC++ RejectNegative\n+\n fhosted\n C ObjC\n Assume normal C execution environment.\n--- a/gcc/common.opt\n+++ b/gcc/common.opt\n@@ -1660,6 +1660,9 @@ fguess-branch-probability\n Common Report Var(flag_guess_branch_prob) Optimization\n Enable guessing of branch probabilities.\n \n+fhonour-copts\n+Common RejectNegative\n+\n ; Nonzero means ignore `#ident' directives.  0 means handle them.\n ; Generate position-independent code for executables if possible\n ; On SVR4 targets, it also controls whether or not to emit a\n--- a/gcc/doc/invoke.texi\n+++ b/gcc/doc/invoke.texi\n@@ -8171,6 +8171,17 @@ This option is only supported for C and\n @option{-Wall} and by @option{-Wpedantic}, which can be disabled with\n @option{-Wno-pointer-sign}.\n \n+@item -fhonour-copts\n+@opindex fhonour-copts\n+If @env{GCC_HONOUR_COPTS} is set to 1, abort if this option is not\n+given at least once, and warn if it is given more than once.\n+If @env{GCC_HONOUR_COPTS} is set to 2, abort if this option is not\n+given exactly once.\n+If @env{GCC_HONOUR_COPTS} is set to 0 or unset, warn if this option\n+is not given exactly once.\n+The warning is quelled if @env{GCC_HONOUR_COPTS} is set to @samp{s}.\n+This flag and environment variable only affect the C language.\n+\n @item -Wstack-protector\n @opindex Wstack-protector\n @opindex Wno-stack-protector\n--- a/gcc/opts.c\n+++ b/gcc/opts.c\n@@ -2318,6 +2318,9 @@ common_handle_option (struct gcc_options\n       /* Currently handled in a prescan.  */\n       break;\n \n+    case OPT_fhonour_copts:\n+      break;\n+\n     case OPT_Werror:\n       dc->warning_as_error_requested = value;\n       break;\n"
  },
  {
    "path": "toolchain/gcc/patches/10.3.0/920-specs_nonfatal_getenv.patch",
    "content": "Author: Jo-Philipp Wich <jow@openwrt.org>\nDate:   Sat Apr 21 03:02:39 2012 +0000\n\n    gcc: add patch to make the getenv() spec function nonfatal if requested environment variable is unset\n    \n    SVN-Revision: 31390\n\n--- a/gcc/gcc.c\n+++ b/gcc/gcc.c\n@@ -9396,8 +9396,10 @@ getenv_spec_function (int argc, const ch\n     }\n \n   if (!value)\n-    fatal_error (input_location,\n-\t\t \"environment variable %qs not defined\", varname);\n+    {\n+      warning (input_location, \"environment variable %qs not defined\", varname);\n+      value = \"\";\n+    }\n \n   /* We have to escape every character of the environment variable so\n      they are not interpreted as active spec characters.  A\n"
  },
  {
    "path": "toolchain/gcc/patches/10.3.0/930-fix-mips-noexecstack.patch",
    "content": "From da45b3fde60095756f5f6030f6012c23a3d34429 Mon Sep 17 00:00:00 2001\nFrom: Andrew McDonnell <bugs@andrewmcdonnell.net>\nDate: Fri, 3 Oct 2014 19:09:00 +0930\nSubject: Add .note.GNU-stack section\n\nSee http://lists.busybox.net/pipermail/uclibc/2014-October/048671.html\nBelow copied from https://gcc.gnu.org/ml/gcc-patches/2014-09/msg02430.html\n\nRe: [Patch, MIPS] Add .note.GNU-stack section\n\n    From: Steve Ellcey <sellcey at mips dot com>\n\nOn Wed, 2014-09-10 at 10:15 -0700, Eric Christopher wrote:\n>\n>\n> On Wed, Sep 10, 2014 at 9:27 AM, <pinskia@gmail.com> wrote:\n\n>         This works except you did not update the assembly files in\n>         libgcc or glibc. We (Cavium) have the same patch in our tree\n>         for a few released versions.\n\n> Mind just checking yours in then Andrew?\n\n> Thanks!\n> -eric\n\nI talked to Andrew about what files he changed in GCC and created and\ntested this new patch.  Andrew also mentioned changing some assembly\nfiles in glibc but I don't see any use of '.section .note.GNU-stack' in\nany assembly files in glibc (for any platform) so I wasn't planning on\ncreating a glibc to add them to mips glibc assembly language files.\n\nOK to check in this patch?\n\nSteve Ellcey\nsellcey@mips.com\n\n\n\n2014-09-26  Steve Ellcey  <sellcey@mips.com>\n---\n gcc/config/mips/mips.c          | 3 +++\n libgcc/config/mips/crti.S       | 4 ++++\n libgcc/config/mips/crtn.S       | 3 +++\n libgcc/config/mips/mips16.S     | 4 ++++\n libgcc/config/mips/vr4120-div.S | 4 ++++\n 5 files changed, 18 insertions(+)\n\n--- a/gcc/config/mips/mips.c\n+++ b/gcc/config/mips/mips.c\n@@ -22881,6 +22881,9 @@ mips_asm_file_end (void)\n #define TARGET_ASM_FILE_END mips_asm_file_end\n \n \n+#undef TARGET_ASM_FILE_END\n+#define TARGET_ASM_FILE_END file_end_indicate_exec_stack\n+\n struct gcc_target targetm = TARGET_INITIALIZER;\n \f\n #include \"gt-mips.h\"\n--- a/libgcc/config/mips/crti.S\n+++ b/libgcc/config/mips/crti.S\n@@ -24,6 +24,10 @@ see the files COPYING3 and COPYING.RUNTI\n /* An executable stack is *not* required for these functions.  */\n #include \"gnustack.h\"\n \n+\n+/* An executable stack is *not* required for these functions.  */\n+\t.section .note.GNU-stack,\"\",%progbits\n+\n /* 4 slots for argument spill area.  1 for cpreturn, 1 for stack.\n    Return spill offset of 40 and 20.  Aligned to 16 bytes for n32.  */\n \n--- a/libgcc/config/mips/crtn.S\n+++ b/libgcc/config/mips/crtn.S\n@@ -24,6 +24,9 @@ see the files COPYING3 and COPYING.RUNTI\n /* An executable stack is *not* required for these functions.  */\n #include \"gnustack.h\"\n \n+/* An executable stack is *not* required for these functions.  */\n+\t.section .note.GNU-stack,\"\",%progbits\n+\n /* 4 slots for argument spill area.  1 for cpreturn, 1 for stack.\n    Return spill offset of 40 and 20.  Aligned to 16 bytes for n32.  */\n \n--- a/libgcc/config/mips/mips16.S\n+++ b/libgcc/config/mips/mips16.S\n@@ -51,6 +51,10 @@ see the files COPYING3 and COPYING.RUNTI\n    values using the soft-float calling convention, but do the actual\n    operation using the hard floating point instructions.  */\n \n+/* An executable stack is *not* required for these functions.  */\n+\t.section .note.GNU-stack,\"\",%progbits\n+\t.previous\n+\n #if defined _MIPS_SIM && (_MIPS_SIM == _ABIO32 || _MIPS_SIM == _ABIO64)\n \n /* This file contains 32-bit assembly code.  */\n--- a/libgcc/config/mips/vr4120-div.S\n+++ b/libgcc/config/mips/vr4120-div.S\n@@ -29,6 +29,10 @@ see the files COPYING3 and COPYING.RUNTI\n    -mfix-vr4120.  div and ddiv do not give the correct result when one\n    of the operands is negative.  */\n \n+/* An executable stack is *not* required for these functions.  */\n+\t.section .note.GNU-stack,\"\",%progbits\n+\t.previous\n+\n \t.set\tnomips16\n \n #define DIV\t\t\t\t\t\t\t\t\\\n"
  },
  {
    "path": "toolchain/gcc/patches/10.3.0/931-libffi-fix-MIPS-softfloat-build-issue.patch",
    "content": "From c0c62fa4256f805389f16ebfc4a60cf789129b50 Mon Sep 17 00:00:00 2001\nFrom: BangLang Huang <banglang.huang@foxmail.com>\nDate: Wed, 9 Nov 2016 10:36:49 +0800\nSubject: [PATCH] libffi: fix MIPS softfloat build issue\n\nBackported from github.com/libffi/libffi#272\n\nSigned-off-by: BangLang Huang <banglang.huang@foxmail.com>\nSigned-off-by: Yousong Zhou <yszhou4tech@gmail.com>\n---\n libffi/src/mips/n32.S | 17 +++++++++++++++++\n libffi/src/mips/o32.S | 17 +++++++++++++++++\n 2 files changed, 34 insertions(+)\n\n--- a/libffi/src/mips/n32.S\n+++ b/libffi/src/mips/n32.S\n@@ -107,6 +107,16 @@ loadregs:\n \n \tREG_L\tt6, 3*FFI_SIZEOF_ARG($fp)  # load the flags word into t6.\n \n+#ifdef __mips_soft_float\n+\tREG_L\ta0, 0*FFI_SIZEOF_ARG(t9)\n+\tREG_L\ta1, 1*FFI_SIZEOF_ARG(t9)\n+\tREG_L\ta2, 2*FFI_SIZEOF_ARG(t9)\n+\tREG_L\ta3, 3*FFI_SIZEOF_ARG(t9)\n+\tREG_L\ta4, 4*FFI_SIZEOF_ARG(t9)\n+\tREG_L\ta5, 5*FFI_SIZEOF_ARG(t9)\n+\tREG_L\ta6, 6*FFI_SIZEOF_ARG(t9)\n+\tREG_L\ta7, 7*FFI_SIZEOF_ARG(t9)\n+#else\n \tand\tt4, t6, ((1<<FFI_FLAG_BITS)-1)\n \tREG_L\ta0, 0*FFI_SIZEOF_ARG(t9)\n \tbeqz\tt4, arg1_next\n@@ -193,6 +203,7 @@ arg7_next:\n arg8_doublep:\t\n  \tl.d\t$f19, 7*FFI_SIZEOF_ARG(t9)\t\n arg8_next:\t\n+#endif\n \n callit:\t\t\n \t# Load the function pointer\n@@ -214,6 +225,7 @@ retint:\n \tb\tepilogue\n \n retfloat:\n+#ifndef __mips_soft_float\n \tbne     t6, FFI_TYPE_FLOAT, retdouble\n \tjal\tt9\n \tREG_L\tt4, 4*FFI_SIZEOF_ARG($fp)\n@@ -272,6 +284,7 @@ retstruct_f_d:\n \ts.s\t$f0, 0(t4)\n \ts.d\t$f2, 8(t4)\n \tb\tepilogue\n+#endif\n \n retstruct_d_soft:\n \tbne\tt6, FFI_TYPE_STRUCT_D_SOFT, retstruct_f_soft\n@@ -429,6 +442,7 @@ ffi_closure_N32:\n \tREG_S\ta6, A6_OFF2($sp)\n \tREG_S\ta7, A7_OFF2($sp)\n \n+#ifndef __mips_soft_float\n \t# Store all possible float/double registers.\n \ts.d\t$f12, F12_OFF2($sp)\n \ts.d\t$f13, F13_OFF2($sp)\n@@ -438,6 +452,7 @@ ffi_closure_N32:\n \ts.d\t$f17, F17_OFF2($sp)\n \ts.d\t$f18, F18_OFF2($sp)\n \ts.d\t$f19, F19_OFF2($sp)\n+#endif\n \n \t# Call ffi_closure_mips_inner_N32 to do the real work.\n \tLA\tt9, ffi_closure_mips_inner_N32\n@@ -458,6 +473,7 @@ cls_retint:\n \tb\tcls_epilogue\n \n cls_retfloat:\n+#ifndef __mips_soft_float\n \tbne     v0, FFI_TYPE_FLOAT, cls_retdouble\n \tl.s\t$f0, V0_OFF2($sp)\n \tb\tcls_epilogue\n@@ -500,6 +516,7 @@ cls_retstruct_f_d:\n \tl.s\t$f0, V0_OFF2($sp)\n \tl.d\t$f2, V1_OFF2($sp)\n \tb\tcls_epilogue\n+#endif\n \t\n cls_retstruct_small2:\t\n \tREG_L\tv0, V0_OFF2($sp)\n--- a/libffi/src/mips/o32.S\n+++ b/libffi/src/mips/o32.S\n@@ -82,13 +82,16 @@ sixteen:\n \t\t\n \tADDU\t$sp, 4 * FFI_SIZEOF_ARG\t\t# adjust $sp to new args\n \n+#ifndef __mips_soft_float\n \tbnez\tt0, pass_d\t\t\t# make it quick for int\n+#endif\n \tREG_L\ta0, 0*FFI_SIZEOF_ARG($sp)\t# just go ahead and load the\n \tREG_L\ta1, 1*FFI_SIZEOF_ARG($sp)\t# four regs.\n \tREG_L\ta2, 2*FFI_SIZEOF_ARG($sp)\n \tREG_L\ta3, 3*FFI_SIZEOF_ARG($sp)\n \tb\tcall_it\n \n+#ifndef __mips_soft_float\n pass_d:\n \tbne\tt0, FFI_ARGS_D, pass_f\n \tl.d\t$f12, 0*FFI_SIZEOF_ARG($sp)\t# load $fp regs from args\n@@ -130,6 +133,7 @@ pass_f_d:\n  #\tbne\tt0, FFI_ARGS_F_D, call_it\n \tl.s\t$f12, 0*FFI_SIZEOF_ARG($sp)\t# load $fp regs from args\n \tl.d\t$f14, 2*FFI_SIZEOF_ARG($sp)\t# passing double and float\n+#endif\n \n call_it:\t\n \t# Load the function pointer\n@@ -158,14 +162,23 @@ retfloat:\n \tbne     t2, FFI_TYPE_FLOAT, retdouble\n \tjalr\tt9\n \tREG_L\tt0, SIZEOF_FRAME + 4*FFI_SIZEOF_ARG($fp)\n+#ifndef __mips_soft_float\n \ts.s\t$f0, 0(t0)\n+#else\n+\tREG_S v0, 0(t0)\n+#endif\n \tb\tepilogue\n \n retdouble:\t\n \tbne\tt2, FFI_TYPE_DOUBLE, noretval\n \tjalr\tt9\n \tREG_L\tt0, SIZEOF_FRAME + 4*FFI_SIZEOF_ARG($fp)\n+#ifndef __mips_soft_float\n \ts.d\t$f0, 0(t0)\n+#else\n+\tREG_S v1, 4(t0)\n+\tREG_S v0, 0(t0)\n+#endif\n \tb\tepilogue\n \t\n noretval:\t\n@@ -261,9 +274,11 @@ $LCFI7:\n \tli\t$13, 1\t\t# FFI_O32\n \tbne\t$16, $13, 1f\t# Skip fp save if FFI_O32_SOFT_FLOAT\n \t\n+#ifndef __mips_soft_float\n \t# Store all possible float/double registers.\n \ts.d\t$f12, FA_0_0_OFF2($fp)\n \ts.d\t$f14, FA_1_0_OFF2($fp)\n+#endif\n 1:\t\n \t# Call ffi_closure_mips_inner_O32 to do the work.\n \tla\tt9, ffi_closure_mips_inner_O32\n@@ -281,6 +296,7 @@ $LCFI7:\n \tli\t$13, 1\t\t# FFI_O32\n \tbne\t$16, $13, 1f\t# Skip fp restore if FFI_O32_SOFT_FLOAT\n \n+#ifndef __mips_soft_float\n \tli\t$9, FFI_TYPE_FLOAT\n \tl.s\t$f0, V0_OFF2($fp)\n \tbeq\t$8, $9, closure_done\n@@ -288,6 +304,7 @@ $LCFI7:\n \tli\t$9, FFI_TYPE_DOUBLE\n \tl.d\t$f0, V0_OFF2($fp)\n \tbeq\t$8, $9, closure_done\n+#endif\n 1:\t\n \tREG_L\t$3, V1_OFF2($fp)\n \tREG_L\t$2, V0_OFF2($fp)\n"
  },
  {
    "path": "toolchain/gcc/patches/10.3.0/960-gotools-fix-compilation-when-making-cross-compiler.patch",
    "content": "From dda6b050cd74a352670787a294596a9c56c21327 Mon Sep 17 00:00:00 2001\nFrom: Yousong Zhou <yszhou4tech@gmail.com>\nDate: Fri, 4 May 2018 18:20:53 +0800\nSubject: [PATCH] gotools: fix compilation when making cross compiler\n\nlibgo is \"the runtime support library for the Go programming language.\nThis library is intended for use with the Go frontend.\"\n\ngccgo will link target files with libgo.so which depends on libgcc_s.so.1, but\nthe linker will complain that it cannot find it.  That's because shared libgcc\nis not present in the install directory yet.  libgo.so was made without problem\nbecause gcc will emit -lgcc_s when compiled with -shared option.  When gotools\nwere being made, it was supplied with -static-libgcc thus no link option was\nprovided.  Check LIBGO in gcc/go/gcc-spec.c for how gccgo make a builtin spec\nfor linking with libgo.so\n\n- GccgoCrossCompilation, https://github.com/golang/go/wiki/GccgoCrossCompilation\n- Cross-building instructions, http://www.eglibc.org/archives/patches/msg00078.html\n\nWhen 3-pass GCC compilation is used, shared libgcc runtime libraries will be\navailable after gcc pass2 completed and will meet the gotools link requirement\nat gcc pass3\n---\n gotools/Makefile.am | 4 +++-\n gotools/Makefile.in | 4 +++-\n 2 files changed, 6 insertions(+), 2 deletions(-)\n\n--- a/gotools/Makefile.am\n+++ b/gotools/Makefile.am\n@@ -26,6 +26,7 @@ PWD_COMMAND = $${PWDCMD-pwd}\n STAMP = echo timestamp >\n \n libgodir = ../$(target_noncanonical)/libgo\n+libgccdir = ../$(target_noncanonical)/libgcc\n LIBGODEP = $(libgodir)/libgo.la\n \n LIBGOTOOL = $(libgodir)/libgotool.a\n@@ -41,7 +42,8 @@ GOCFLAGS = $(CFLAGS_FOR_TARGET)\n GOCOMPILE = $(GOCOMPILER) $(GOCFLAGS)\n \n AM_GOCFLAGS = -I $(libgodir)\n-AM_LDFLAGS = -L $(libgodir) -L $(libgodir)/.libs\n+AM_LDFLAGS = -L $(libgodir) -L $(libgodir)/.libs \\\n+\t-L $(libgccdir) -L $(libgccdir)/.libs -lgcc_s\n GOLINK = $(GOCOMPILER) $(GOCFLAGS) $(AM_GOCFLAGS) $(LDFLAGS) $(AM_LDFLAGS) -o $@\n \n libgosrcdir = $(srcdir)/../libgo/go\n--- a/gotools/Makefile.in\n+++ b/gotools/Makefile.in\n@@ -337,6 +337,7 @@ mkinstalldirs = $(SHELL) $(toplevel_srcd\n PWD_COMMAND = $${PWDCMD-pwd}\n STAMP = echo timestamp >\n libgodir = ../$(target_noncanonical)/libgo\n+libgccdir = ../$(target_noncanonical)/libgcc\n LIBGODEP = $(libgodir)/libgo.la\n LIBGOTOOL = $(libgodir)/libgotool.a\n @NATIVE_FALSE@GOCOMPILER = $(GOC)\n@@ -346,7 +347,8 @@ LIBGOTOOL = $(libgodir)/libgotool.a\n GOCFLAGS = $(CFLAGS_FOR_TARGET)\n GOCOMPILE = $(GOCOMPILER) $(GOCFLAGS)\n AM_GOCFLAGS = -I $(libgodir)\n-AM_LDFLAGS = -L $(libgodir) -L $(libgodir)/.libs\n+AM_LDFLAGS = -L $(libgodir) -L $(libgodir)/.libs \\\n+\t-L $(libgccdir) -L $(libgccdir)/.libs -lgcc_s\n GOLINK = $(GOCOMPILER) $(GOCFLAGS) $(AM_GOCFLAGS) $(LDFLAGS) $(AM_LDFLAGS) -o $@\n libgosrcdir = $(srcdir)/../libgo/go\n cmdsrcdir = $(libgosrcdir)/cmd\n"
  },
  {
    "path": "toolchain/gcc/patches/11.2.0/001-v11.3.0-ranger-Fix-up-fold_using_range-range_of_address-PR10.patch",
    "content": "From a6219e8e0719b14f474b0dcaa7bde2f4e57474f9 Mon Sep 17 00:00:00 2001\nFrom: Jakub Jelinek <jakub@redhat.com>\nDate: Wed, 17 Nov 2021 13:45:53 +0100\nSubject: [PATCH] ranger: Fix up fold_using_range::range_of_address [PR103255]\n\nIf on &base->member the offset isn't constant or isn't zero and\n-fdelete-null-pointer-checks and not -fwrapv-pointer and base has a range\nthat doesn't include NULL, we return the range of the base.\nUsually it isn't a big deal, because for most pointers we just use\nvarying, range_zero and range_nonzero ranges and nothing beyond that,\nbut if a pointer is initialized from a constant, we actually track the\nexact range and in that case this causes miscompilation.\nAs discussed on IRC, I think doing something like:\n              offset_int off2;\n              if (off_cst && off.is_constant (&off2))\n                {\n                  tree cst = wide_int_to_tree (sizetype, off2 / BITS_PER_UNIT);\n                  // adjust range r with POINTER_PLUS_EXPR cst\n                  if (!range_includes_zero_p (&r))\n                    return true;\n                }\n              // Fallback\n              r = range_nonzero (TREE_TYPE (gimple_assign_rhs1 (stmt)));\n              return true;\ncould work, given that most of the pointer ranges are just the simple ones\nperhaps it is too much for little benefit.\n\n2021-11-17  Jakub Jelinek  <jakub@redhat.com>\n\n\tPR tree-optimization/103255\n\t* gimple-range.cc (fold_using_range::range_of_address): Return\n\trange_nonzero rather than unadjusted base's range.  Formatting fixes.\n\n\t* gcc.c-torture/execute/pr103255.c: New test.\n\n(cherry picked from commit c39cb6bf835ca12e590eaa6f90222e51be207c50)\n---\n gcc/gimple-range.cc                           | 16 +++++---\n .../gcc.c-torture/execute/pr103255.c          | 41 +++++++++++++++++++\n 2 files changed, 52 insertions(+), 5 deletions(-)\n create mode 100644 gcc/testsuite/gcc.c-torture/execute/pr103255.c\n\n--- a/gcc/gimple-range.cc\n+++ b/gcc/gimple-range.cc\n@@ -491,14 +491,20 @@ gimple_ranger::range_of_address (irange\n \t}\n       /* If &X->a is equal to X, the range of X is the result.  */\n       if (off_cst && known_eq (off, 0))\n-\t  return true;\n+\treturn true;\n       else if (flag_delete_null_pointer_checks\n \t       && !TYPE_OVERFLOW_WRAPS (TREE_TYPE (expr)))\n \t{\n-\t /* For -fdelete-null-pointer-checks -fno-wrapv-pointer we don't\n-\t allow going from non-NULL pointer to NULL.  */\n-\t   if(!range_includes_zero_p (&r))\n-\t    return true;\n+\t  /* For -fdelete-null-pointer-checks -fno-wrapv-pointer we don't\n+\t     allow going from non-NULL pointer to NULL.  */\n+\t  if (!range_includes_zero_p (&r))\n+\t    {\n+\t      /* We could here instead adjust r by off >> LOG2_BITS_PER_UNIT\n+\t\t using POINTER_PLUS_EXPR if off_cst and just fall back to\n+\t\t this.  */\n+\t      r = range_nonzero (TREE_TYPE (gimple_assign_rhs1 (stmt)));\n+\t      return true;\n+\t    }\n \t}\n       /* If MEM_REF has a \"positive\" offset, consider it non-NULL\n \t always, for -fdelete-null-pointer-checks also \"negative\"\n--- /dev/null\n+++ b/gcc/testsuite/gcc.c-torture/execute/pr103255.c\n@@ -0,0 +1,41 @@\n+/* PR tree-optimization/103255 */\n+\n+struct H\n+{\n+  unsigned a;\n+  unsigned b;\n+  unsigned c;\n+};\n+\n+#if __SIZEOF_POINTER__ >= 4\n+#define ADDR 0x400000\n+#else\n+#define ADDR 0x4000\n+#endif\n+#define OFF 0x20\n+\n+int\n+main ()\n+{\n+  struct H *h = 0;\n+  unsigned long o;\n+  volatile int t = 1;\n+\n+  for (o = OFF; o <= OFF; o += 0x1000)\n+    {\n+      struct H *u;\n+      u = (struct H *) (ADDR + o);\n+      if (t)\n+\t{\n+\t  h = u;\n+\t  break;\n+\t}\n+    }\n+\n+  if (h == 0)\n+    return 0;\n+  unsigned *tt = &h->b;\n+  if ((__SIZE_TYPE__) tt != (ADDR + OFF + __builtin_offsetof (struct H, b)))\n+    __builtin_abort ();\n+  return 0;\n+}\n"
  },
  {
    "path": "toolchain/gcc/patches/11.2.0/002-case_insensitive.patch",
    "content": "commit 81cc26c706b2bc8c8c1eb1a322e5c5157900836e\nAuthor: Felix Fietkau <nbd@openwrt.org>\nDate:   Sun Oct 19 21:45:51 2014 +0000\n\n    gcc: do not assume that the Mac OS X filesystem is case insensitive\n    \n    Signed-off-by: Felix Fietkau <nbd@openwrt.org>\n    \n    SVN-Revision: 42973\n\n--- a/include/filenames.h\n+++ b/include/filenames.h\n@@ -44,11 +44,6 @@ extern \"C\" {\n #  define IS_DIR_SEPARATOR(c) IS_DOS_DIR_SEPARATOR (c)\n #  define IS_ABSOLUTE_PATH(f) IS_DOS_ABSOLUTE_PATH (f)\n #else /* not DOSish */\n-#  if defined(__APPLE__)\n-#    ifndef HAVE_CASE_INSENSITIVE_FILE_SYSTEM\n-#      define HAVE_CASE_INSENSITIVE_FILE_SYSTEM 1\n-#    endif\n-#  endif /* __APPLE__ */\n #  define HAS_DRIVE_SPEC(f) (0)\n #  define IS_DIR_SEPARATOR(c) IS_UNIX_DIR_SEPARATOR (c)\n #  define IS_ABSOLUTE_PATH(f) IS_UNIX_ABSOLUTE_PATH (f)\n"
  },
  {
    "path": "toolchain/gcc/patches/11.2.0/010-documentation.patch",
    "content": "commit 098bd91f5eae625c7d2ee621e10930fc4434e5e2\nAuthor: Luka Perkov <luka@openwrt.org>\nDate:   Tue Feb 26 16:16:33 2013 +0000\n\n    gcc: don't build documentation\n    \n    This closes #13039.\n    \n    Signed-off-by: Luka Perkov <luka@openwrt.org>\n    \n    SVN-Revision: 35807\n\n--- a/gcc/Makefile.in\n+++ b/gcc/Makefile.in\n@@ -3355,18 +3355,10 @@ doc/gcc.info: $(TEXI_GCC_FILES)\n doc/gccint.info: $(TEXI_GCCINT_FILES)\n doc/cppinternals.info: $(TEXI_CPPINT_FILES)\n \n-doc/%.info: %.texi\n-\tif [ x$(BUILD_INFO) = xinfo ]; then \\\n-\t\t$(MAKEINFO) $(MAKEINFOFLAGS) -I . -I $(gcc_docdir) \\\n-\t\t\t-I $(gcc_docdir)/include -o $@ $<; \\\n-\tfi\n+doc/%.info:\n \n # Duplicate entry to handle renaming of gccinstall.info\n-doc/gccinstall.info: $(TEXI_GCCINSTALL_FILES)\n-\tif [ x$(BUILD_INFO) = xinfo ]; then \\\n-\t\t$(MAKEINFO) $(MAKEINFOFLAGS) -I $(gcc_docdir) \\\n-\t\t\t-I $(gcc_docdir)/include -o $@ $<; \\\n-\tfi\n+doc/gccinstall.info:\n \n doc/cpp.dvi: $(TEXI_CPP_FILES)\n doc/gcc.dvi: $(TEXI_GCC_FILES)\n"
  },
  {
    "path": "toolchain/gcc/patches/11.2.0/011-v12-configure-define-TARGET_LIBC_GNUSTACK-on-musl.patch",
    "content": "From ea650cae26da4a8fc04f0c4666f4dd776d0b5fc0 Mon Sep 17 00:00:00 2001\nFrom: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com>\nDate: Sun, 14 Nov 2021 21:54:25 -0800\nSubject: [PATCH] configure: define TARGET_LIBC_GNUSTACK on musl\n\nmusl only uses PT_GNU_STACK to set default thread stack size and has no\nexecutable stack support[0], so there is no reason not to emit the\n.note.GNU-stack section on musl builds.\n\n[0]: https://lore.kernel.org/all/20190423192534.GN23599@brightrain.aerifal.cx/T/#u\n\ngcc/ChangeLog:\n\n\t* configure: Regenerate.\n\t* configure.ac: define TARGET_LIBC_GNUSTACK on musl\n\nSigned-off-by: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com>\n---\n gcc/configure    | 3 +++\n gcc/configure.ac | 3 +++\n 2 files changed, 6 insertions(+)\n\n--- a/gcc/configure\n+++ b/gcc/configure\n@@ -30954,6 +30954,9 @@ fi\n # Check if the target LIBC handles PT_GNU_STACK.\n gcc_cv_libc_gnustack=unknown\n case \"$target\" in\n+  mips*-*-linux-musl*)\n+    gcc_cv_libc_gnustack=yes\n+    ;;\n   mips*-*-linux*)\n \n if test $glibc_version_major -gt 2 \\\n--- a/gcc/configure.ac\n+++ b/gcc/configure.ac\n@@ -6788,6 +6788,9 @@ fi\n # Check if the target LIBC handles PT_GNU_STACK.\n gcc_cv_libc_gnustack=unknown\n case \"$target\" in\n+  mips*-*-linux-musl*)\n+    gcc_cv_libc_gnustack=yes\n+    ;;\n   mips*-*-linux*)\n     GCC_GLIBC_VERSION_GTE_IFELSE([2], [31], [gcc_cv_libc_gnustack=yes], )\n     ;;\n"
  },
  {
    "path": "toolchain/gcc/patches/11.2.0/110-Fix-MIPS-PR-84790.patch",
    "content": "Fix https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84790.\nMIPS16 functions have a static assembler prologue which clobbers\nregisters v0 and v1. Add these register clobbers to function call\ninstructions.\n\n--- a/gcc/config/mips/mips.c\n+++ b/gcc/config/mips/mips.c\n@@ -3132,6 +3132,12 @@ mips_emit_call_insn (rtx pattern, rtx or\n       emit_insn (gen_update_got_version ());\n     }\n \n+  if (TARGET_MIPS16 && TARGET_USE_GOT)\n+    {\n+      clobber_reg (&CALL_INSN_FUNCTION_USAGE (insn), MIPS16_PIC_TEMP);\n+      clobber_reg (&CALL_INSN_FUNCTION_USAGE (insn), MIPS_PROLOGUE_TEMP (word_mode));\n+    }\n+\n   if (TARGET_MIPS16\n       && TARGET_EXPLICIT_RELOCS\n       && TARGET_CALL_CLOBBERED_GP)\n"
  },
  {
    "path": "toolchain/gcc/patches/11.2.0/230-musl_libssp.patch",
    "content": "--- a/gcc/gcc.c\n+++ b/gcc/gcc.c\n@@ -978,7 +978,9 @@ proper position among the other output f\n #endif\n \n #ifndef LINK_SSP_SPEC\n-#ifdef TARGET_LIBC_PROVIDES_SSP\n+#if DEFAULT_LIBC == LIBC_MUSL\n+#define LINK_SSP_SPEC \"-lssp_nonshared\"\n+#elif defined(TARGET_LIBC_PROVIDES_SSP)\n #define LINK_SSP_SPEC \"%{fstack-protector|fstack-protector-all\" \\\n \t\t       \"|fstack-protector-strong|fstack-protector-explicit:}\"\n #else\n"
  },
  {
    "path": "toolchain/gcc/patches/11.2.0/300-mips_Os_cpu_rtx_cost_model.patch",
    "content": "commit ecf7671b769fe96f7b5134be442089f8bdba55d2\nAuthor: Felix Fietkau <nbd@nbd.name>\nDate:   Thu Aug 4 20:29:45 2016 +0200\n\ngcc: add a patch to generate better code with Os on mips\n\nAlso happens to reduce compressed code size a bit\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n\n--- a/gcc/config/mips/mips.c\n+++ b/gcc/config/mips/mips.c\n@@ -20041,7 +20041,7 @@ mips_option_override (void)\n     flag_pcc_struct_return = 0;\n \n   /* Decide which rtx_costs structure to use.  */\n-  if (optimize_size)\n+  if (0 && optimize_size)\n     mips_cost = &mips_rtx_cost_optimize_size;\n   else\n     mips_cost = &mips_rtx_cost_data[mips_tune];\n"
  },
  {
    "path": "toolchain/gcc/patches/11.2.0/810-arm-softfloat-libgcc.patch",
    "content": "commit 8570c4be394cff7282f332f97da2ff569a927ddb\nAuthor: Imre Kaloz <kaloz@openwrt.org>\nDate:   Wed Feb 2 20:06:12 2011 +0000\n\n    fixup arm soft-float symbols\n    \n    SVN-Revision: 25325\n\n--- a/libgcc/config/arm/t-linux\n+++ b/libgcc/config/arm/t-linux\n@@ -1,6 +1,10 @@\n LIB1ASMSRC = arm/lib1funcs.S\n LIB1ASMFUNCS = _udivsi3 _divsi3 _umodsi3 _modsi3 _dvmd_lnx _clzsi2 _clzdi2 \\\n-\t_ctzsi2 _arm_addsubdf3 _arm_addsubsf3\n+\t_ctzsi2 _arm_addsubdf3 _arm_addsubsf3 \\\n+\t_arm_negdf2 _arm_muldivdf3 _arm_cmpdf2 _arm_unorddf2 \\\n+\t_arm_fixdfsi _arm_fixunsdfsi _arm_truncdfsf2 \\\n+\t_arm_negsf2 _arm_muldivsf3 _arm_cmpsf2 _arm_unordsf2 \\\n+\t_arm_fixsfsi _arm_fixunssfsi\n \n # Just for these, we omit the frame pointer since it makes such a big\n # difference.\n--- a/gcc/config/arm/linux-elf.h\n+++ b/gcc/config/arm/linux-elf.h\n@@ -58,8 +58,6 @@\n    %{shared:-lc} \\\n    %{!shared:%{profile:-lc_p}%{!profile:-lc}}\"\n \n-#define LIBGCC_SPEC \"%{mfloat-abi=soft*:-lfloat} -lgcc\"\n-\n #define GLIBC_DYNAMIC_LINKER \"/lib/ld-linux.so.2\"\n \n #define LINUX_TARGET_LINK_SPEC  \"%{h*} \\\n"
  },
  {
    "path": "toolchain/gcc/patches/11.2.0/820-libgcc_pic.patch",
    "content": "commit c96312958c0621e72c9b32da5bc224ffe2161384\nAuthor: Felix Fietkau <nbd@openwrt.org>\nDate:   Mon Oct 19 23:26:09 2009 +0000\n\n    gcc: create a proper libgcc_pic.a static library for relinking (4.3.3+ for now, backport will follow)\n    \n    SVN-Revision: 18086\n\n--- a/libgcc/Makefile.in\n+++ b/libgcc/Makefile.in\n@@ -930,11 +930,12 @@ $(libgcov-driver-objects): %$(objext): $\n \n # Static libraries.\n libgcc.a: $(libgcc-objects)\n+libgcc_pic.a: $(libgcc-s-objects)\n libgcov.a: $(libgcov-objects)\n libunwind.a: $(libunwind-objects)\n libgcc_eh.a: $(libgcc-eh-objects)\n \n-libgcc.a libgcov.a libunwind.a libgcc_eh.a:\n+libgcc.a libgcov.a libunwind.a libgcc_eh.a libgcc_pic.a:\n \t-rm -f $@\n \n \tobjects=\"$(objects)\";\t\t\t\t\t\\\n@@ -958,7 +959,7 @@ all: libunwind.a\n endif\n \n ifeq ($(enable_shared),yes)\n-all: libgcc_eh.a libgcc_s$(SHLIB_EXT)\n+all: libgcc_eh.a libgcc_pic.a libgcc_s$(SHLIB_EXT)\n ifneq ($(LIBUNWIND),)\n all: libunwind$(SHLIB_EXT)\n libgcc_s$(SHLIB_EXT): libunwind$(SHLIB_EXT)\n@@ -1164,6 +1165,10 @@ install-shared:\n \tchmod 644 $(DESTDIR)$(inst_libdir)/libgcc_eh.a\n \t$(RANLIB) $(DESTDIR)$(inst_libdir)/libgcc_eh.a\n \n+\t$(INSTALL_DATA) libgcc_pic.a $(mapfile) $(DESTDIR)$(inst_libdir)/\n+\tchmod 644 $(DESTDIR)$(inst_libdir)/libgcc_pic.a\n+\t$(RANLIB) $(DESTDIR)$(inst_libdir)/libgcc_pic.a\n+\n \t$(subst @multilib_dir@,$(MULTIDIR),$(subst \\\n \t\t@shlib_base_name@,libgcc_s,$(subst \\\n \t\t@shlib_slibdir_qual@,$(MULTIOSSUBDIR),$(SHLIB_INSTALL))))\n"
  },
  {
    "path": "toolchain/gcc/patches/11.2.0/840-armv4_pass_fix-v4bx_to_ld.patch",
    "content": "commit 7edc8ca5456d9743dd0075eb3cc5b04f4f24c8cc\nAuthor: Imre Kaloz <kaloz@openwrt.org>\nDate:   Wed Feb 2 19:34:36 2011 +0000\n\n    add armv4 fixup patches\n    \n    SVN-Revision: 25322\n\n\n--- a/gcc/config/arm/linux-eabi.h\n+++ b/gcc/config/arm/linux-eabi.h\n@@ -91,10 +91,15 @@\n #define MUSL_DYNAMIC_LINKER \\\n   \"/lib/ld-musl-arm\" MUSL_DYNAMIC_LINKER_E \"%{mfloat-abi=hard:hf}%{mfdpic:-fdpic}.so.1\"\n \n+/* For armv4 we pass --fix-v4bx to linker to support EABI */\n+#undef TARGET_FIX_V4BX_SPEC\n+#define TARGET_FIX_V4BX_SPEC \" %{mcpu=arm8|mcpu=arm810|mcpu=strongarm*\"\\\n+  \"|march=armv4|mcpu=fa526|mcpu=fa626:--fix-v4bx}\"\n+\n /* At this point, bpabi.h will have clobbered LINK_SPEC.  We want to\n    use the GNU/Linux version, not the generic BPABI version.  */\n #undef  LINK_SPEC\n-#define LINK_SPEC EABI_LINK_SPEC\t\t\t\t\t\\\n+#define LINK_SPEC EABI_LINK_SPEC TARGET_FIX_V4BX_SPEC\t\t\t\\\n   LINUX_OR_ANDROID_LD (LINUX_TARGET_LINK_SPEC,\t\t\t\t\\\n \t\t       LINUX_TARGET_LINK_SPEC \" \" ANDROID_LINK_SPEC)\n \n"
  },
  {
    "path": "toolchain/gcc/patches/11.2.0/850-use_shared_libgcc.patch",
    "content": "commit dcfc40358b5a3cae7320c17f8d1cebd5ad5540cd\nAuthor: Felix Fietkau <nbd@openwrt.org>\nDate:   Sun Feb 12 20:25:47 2012 +0000\n\n    gcc 4.6: port over the missing patch 850-use_shared_libgcc.patch to prevent libgcc crap from leaking into every single binary\n    \n    SVN-Revision: 30486\n--- a/gcc/config/arm/linux-eabi.h\n+++ b/gcc/config/arm/linux-eabi.h\n@@ -132,10 +132,6 @@\n   \"%{Ofast|ffast-math|funsafe-math-optimizations:crtfastmath.o%s} \"\t\\\n   LINUX_OR_ANDROID_LD (GNU_USER_TARGET_ENDFILE_SPEC, ANDROID_ENDFILE_SPEC)\n \n-/* Use the default LIBGCC_SPEC, not the version in linux-elf.h, as we\n-   do not use -lfloat.  */\n-#undef LIBGCC_SPEC\n-\n /* Clear the instruction cache from `beg' to `end'.  This is\n    implemented in lib1funcs.S, so ensure an error if this definition\n    is used.  */\n--- a/gcc/config/linux.h\n+++ b/gcc/config/linux.h\n@@ -66,6 +66,10 @@ see the files COPYING3 and COPYING.RUNTI\n \t  builtin_version (\"CRuntime_Musl\");\t\t\t\\\n     } while (0)\n \n+#ifndef LIBGCC_SPEC\n+#define LIBGCC_SPEC \"%{static|static-libgcc:-lgcc}%{!static:%{!static-libgcc:-lgcc_s}}\"\n+#endif\n+\n /* Determine which dynamic linker to use depending on whether GLIBC or\n    uClibc or Bionic or musl is the default C library and whether\n    -muclibc or -mglibc or -mbionic or -mmusl has been passed to change\n--- a/libgcc/mkmap-symver.awk\n+++ b/libgcc/mkmap-symver.awk\n@@ -136,5 +136,5 @@ function output(lib) {\n   else if (inherit[lib])\n     printf(\"} %s;\\n\", inherit[lib]);\n   else\n-    printf (\"\\n  local:\\n\\t*;\\n};\\n\");\n+    printf (\"\\n\\t*;\\n};\\n\");\n }\n--- a/gcc/config/rs6000/linux.h\n+++ b/gcc/config/rs6000/linux.h\n@@ -62,6 +62,9 @@\n #undef\tCPP_OS_DEFAULT_SPEC\n #define CPP_OS_DEFAULT_SPEC \"%(cpp_os_linux)\"\n \n+#undef LIBGCC_SPEC\n+#define LIBGCC_SPEC \"%{!static:%{!static-libgcc:-lgcc_s}} -lgcc\"\n+\n #undef  LINK_SHLIB_SPEC\n #define LINK_SHLIB_SPEC \"%{shared:-shared} %{!shared: %{static:-static}} \\\n   %{static-pie:-static -pie --no-dynamic-linker -z text}\"\n"
  },
  {
    "path": "toolchain/gcc/patches/11.2.0/851-libgcc_no_compat.patch",
    "content": "commit 64661de100da1ec1061ef3e5e400285dce115e6b\nAuthor: Felix Fietkau <nbd@openwrt.org>\nDate:   Sun May 10 13:16:35 2015 +0000\n\n    gcc: add some size optimization patches\n    \n    Signed-off-by: Felix Fietkau <nbd@openwrt.org>\n    \n    SVN-Revision: 45664\n\n--- a/libgcc/config/t-libunwind\n+++ b/libgcc/config/t-libunwind\n@@ -2,8 +2,7 @@\n \n HOST_LIBGCC2_CFLAGS += -DUSE_GAS_SYMVER\n \n-LIB2ADDEH = $(srcdir)/unwind-sjlj.c $(srcdir)/unwind-c.c \\\n-  $(srcdir)/unwind-compat.c $(srcdir)/unwind-dw2-fde-compat.c\n+LIB2ADDEH = $(srcdir)/unwind-sjlj.c $(srcdir)/unwind-c.c\n LIB2ADDEHSTATIC = $(srcdir)/unwind-sjlj.c $(srcdir)/unwind-c.c\n \n # Override the default value from t-slibgcc-elf-ver and mention -lunwind\n"
  },
  {
    "path": "toolchain/gcc/patches/11.2.0/870-ppc_no_crtsavres.patch",
    "content": "--- a/gcc/config/rs6000/rs6000-logue.c\n+++ b/gcc/config/rs6000/rs6000-logue.c\n@@ -348,7 +348,7 @@ rs6000_savres_strategy (rs6000_stack_t *\n   /* Define cutoff for using out-of-line functions to save registers.  */\n   if (DEFAULT_ABI == ABI_V4 || TARGET_ELF)\n     {\n-      if (!optimize_size)\n+      if (1)\n \t{\n \t  strategy |= SAVE_INLINE_FPRS | REST_INLINE_FPRS;\n \t  strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;\n"
  },
  {
    "path": "toolchain/gcc/patches/11.2.0/881-no_tm_section.patch",
    "content": "--- a/libgcc/crtstuff.c\n+++ b/libgcc/crtstuff.c\n@@ -152,7 +152,7 @@ call_ ## FUNC (void)\t\t\t\t\t\\\n #endif\n \n #if !defined(USE_TM_CLONE_REGISTRY) && defined(OBJECT_FORMAT_ELF)\n-# define USE_TM_CLONE_REGISTRY 1\n+# define USE_TM_CLONE_REGISTRY 0\n #elif !defined(USE_TM_CLONE_REGISTRY)\n # define USE_TM_CLONE_REGISTRY 0\n #endif\n"
  },
  {
    "path": "toolchain/gcc/patches/11.2.0/900-bad-mips16-crt.patch",
    "content": "--- a/libgcc/config/mips/t-mips16\n+++ b/libgcc/config/mips/t-mips16\n@@ -43,3 +43,6 @@ SYNC_CFLAGS = -mno-mips16\n \n # Version these symbols if building libgcc.so.\n SHLIB_MAPFILES += $(srcdir)/config/mips/libgcc-mips16.ver\n+\n+CRTSTUFF_T_CFLAGS += -mno-mips16\n+CRTSTUFF_T_CFLAGS_S += -mno-mips16\n"
  },
  {
    "path": "toolchain/gcc/patches/11.2.0/910-mbsd_multi.patch",
    "content": "commit 99368862e44740ff4fd33760893f04e14f9dbdf1\nAuthor: Felix Fietkau <nbd@openwrt.org>\nDate:   Tue Jul 31 00:52:27 2007 +0000\n\n    Port the mbsd_multi patch from freewrt, which adds -fhonour-copts. This will emit warnings in packages that don't use our target cflags properly\n    \n    SVN-Revision: 8256\n\n\tThis patch brings over a feature from MirBSD:\n\t* -fhonour-copts\n\t  If this option is not given, it's warned (depending\n\t  on environment variables). This is to catch errors\n\t  of misbuilt packages which override CFLAGS themselves.\n\n\tThis patch was authored by Thorsten Glaser <tg at mirbsd.de>\n\twith copyright assignment to the FSF in effect.\n\n--- a/gcc/c-family/c-opts.c\n+++ b/gcc/c-family/c-opts.c\n@@ -107,6 +107,9 @@ static dump_flags_t original_dump_flags;\n /* Whether any standard preincluded header has been preincluded.  */\n static bool done_preinclude;\n \n+/* Check if a port honours COPTS.  */\n+static int honour_copts = 0;\n+\n static void handle_OPT_d (const char *);\n static void set_std_cxx98 (int);\n static void set_std_cxx11 (int);\n@@ -469,6 +472,12 @@ c_common_handle_option (size_t scode, co\n       flag_no_builtin = !value;\n       break;\n \n+    case OPT_fhonour_copts:\n+      if (c_language == clk_c) {\n+        honour_copts++;\n+      }\n+      break;\n+\n     case OPT_fconstant_string_class_:\n       constant_string_class_name = arg;\n       break;\n@@ -1196,6 +1205,47 @@ c_common_init (void)\n       return false;\n     }\n \n+  if (c_language == clk_c) {\n+    char *ev = getenv (\"GCC_HONOUR_COPTS\");\n+    int evv;\n+    if (ev == NULL)\n+      evv = -1;\n+    else if ((*ev == '0') || (*ev == '\\0'))\n+      evv = 0;\n+    else if (*ev == '1')\n+      evv = 1;\n+    else if (*ev == '2')\n+      evv = 2;\n+    else if (*ev == 's')\n+      evv = -1;\n+    else {\n+      warning (0, \"unknown GCC_HONOUR_COPTS value, assuming 1\");\n+      evv = 1; /* maybe depend this on something like MIRBSD_NATIVE?  */\n+    }\n+    if (evv == 1) {\n+      if (honour_copts == 0) {\n+        error (\"someone does not honour COPTS at all in lenient mode\");\n+        return false;\n+      } else if (honour_copts != 1) {\n+        warning (0, \"someone does not honour COPTS correctly, passed %d times\",\n+         honour_copts);\n+      }\n+    } else if (evv == 2) {\n+      if (honour_copts == 0) {\n+        error (\"someone does not honour COPTS at all in strict mode\");\n+        return false;\n+      } else if (honour_copts != 1) {\n+        error (\"someone does not honour COPTS correctly, passed %d times\",\n+         honour_copts);\n+        return false;\n+      }\n+    } else if (evv == 0) {\n+      if (honour_copts != 1)\n+        inform (UNKNOWN_LOCATION, \"someone does not honour COPTS correctly, passed %d times\",\n+         honour_copts);\n+    }\n+  }\n+\n   return true;\n }\n \n--- a/gcc/c-family/c.opt\n+++ b/gcc/c-family/c.opt\n@@ -1663,6 +1663,9 @@ C++ ObjC++ Optimization Alias(fexception\n fhonor-std\n C++ ObjC++ WarnRemoved\n \n+fhonour-copts\n+C ObjC C++ ObjC++ RejectNegative\n+\n fhosted\n C ObjC\n Assume normal C execution environment.\n--- a/gcc/common.opt\n+++ b/gcc/common.opt\n@@ -1698,6 +1698,9 @@ fguess-branch-probability\n Common Var(flag_guess_branch_prob) Optimization\n Enable guessing of branch probabilities.\n \n+fhonour-copts\n+Common RejectNegative\n+\n ; Nonzero means ignore `#ident' directives.  0 means handle them.\n ; Generate position-independent code for executables if possible\n ; On SVR4 targets, it also controls whether or not to emit a\n--- a/gcc/doc/invoke.texi\n+++ b/gcc/doc/invoke.texi\n@@ -9055,6 +9055,17 @@ This option is only supported for C and\n @option{-Wall} and by @option{-Wpedantic}, which can be disabled with\n @option{-Wno-pointer-sign}.\n \n+@item -fhonour-copts\n+@opindex fhonour-copts\n+If @env{GCC_HONOUR_COPTS} is set to 1, abort if this option is not\n+given at least once, and warn if it is given more than once.\n+If @env{GCC_HONOUR_COPTS} is set to 2, abort if this option is not\n+given exactly once.\n+If @env{GCC_HONOUR_COPTS} is set to 0 or unset, warn if this option\n+is not given exactly once.\n+The warning is quelled if @env{GCC_HONOUR_COPTS} is set to @samp{s}.\n+This flag and environment variable only affect the C language.\n+\n @item -Wstack-protector\n @opindex Wstack-protector\n @opindex Wno-stack-protector\n--- a/gcc/opts.c\n+++ b/gcc/opts.c\n@@ -2448,6 +2448,9 @@ common_handle_option (struct gcc_options\n       /* Currently handled in a prescan.  */\n       break;\n \n+    case OPT_fhonour_copts:\n+      break;\n+\n     case OPT_Werror:\n       dc->warning_as_error_requested = value;\n       break;\n"
  },
  {
    "path": "toolchain/gcc/patches/11.2.0/920-specs_nonfatal_getenv.patch",
    "content": "Author: Jo-Philipp Wich <jow@openwrt.org>\nDate:   Sat Apr 21 03:02:39 2012 +0000\n\n    gcc: add patch to make the getenv() spec function nonfatal if requested environment variable is unset\n    \n    SVN-Revision: 31390\n\n--- a/gcc/gcc.c\n+++ b/gcc/gcc.c\n@@ -10100,8 +10100,10 @@ getenv_spec_function (int argc, const ch\n     }\n \n   if (!value)\n-    fatal_error (input_location,\n-\t\t \"environment variable %qs not defined\", varname);\n+    {\n+      warning (input_location, \"environment variable %qs not defined\", varname);\n+      value = \"\";\n+    }\n \n   /* We have to escape every character of the environment variable so\n      they are not interpreted as active spec characters.  A\n"
  },
  {
    "path": "toolchain/gcc/patches/11.2.0/931-libffi-fix-MIPS-softfloat-build-issue.patch",
    "content": "From c0c62fa4256f805389f16ebfc4a60cf789129b50 Mon Sep 17 00:00:00 2001\nFrom: BangLang Huang <banglang.huang@foxmail.com>\nDate: Wed, 9 Nov 2016 10:36:49 +0800\nSubject: [PATCH] libffi: fix MIPS softfloat build issue\n\nBackported from github.com/libffi/libffi#272\n\nSigned-off-by: BangLang Huang <banglang.huang@foxmail.com>\nSigned-off-by: Yousong Zhou <yszhou4tech@gmail.com>\n---\n libffi/src/mips/n32.S | 17 +++++++++++++++++\n libffi/src/mips/o32.S | 17 +++++++++++++++++\n 2 files changed, 34 insertions(+)\n\n--- a/libffi/src/mips/n32.S\n+++ b/libffi/src/mips/n32.S\n@@ -107,6 +107,16 @@ loadregs:\n \n \tREG_L\tt6, 3*FFI_SIZEOF_ARG($fp)  # load the flags word into t6.\n \n+#ifdef __mips_soft_float\n+\tREG_L\ta0, 0*FFI_SIZEOF_ARG(t9)\n+\tREG_L\ta1, 1*FFI_SIZEOF_ARG(t9)\n+\tREG_L\ta2, 2*FFI_SIZEOF_ARG(t9)\n+\tREG_L\ta3, 3*FFI_SIZEOF_ARG(t9)\n+\tREG_L\ta4, 4*FFI_SIZEOF_ARG(t9)\n+\tREG_L\ta5, 5*FFI_SIZEOF_ARG(t9)\n+\tREG_L\ta6, 6*FFI_SIZEOF_ARG(t9)\n+\tREG_L\ta7, 7*FFI_SIZEOF_ARG(t9)\n+#else\n \tand\tt4, t6, ((1<<FFI_FLAG_BITS)-1)\n \tREG_L\ta0, 0*FFI_SIZEOF_ARG(t9)\n \tbeqz\tt4, arg1_next\n@@ -193,6 +203,7 @@ arg7_next:\n arg8_doublep:\t\n  \tl.d\t$f19, 7*FFI_SIZEOF_ARG(t9)\t\n arg8_next:\t\n+#endif\n \n callit:\t\t\n \t# Load the function pointer\n@@ -214,6 +225,7 @@ retint:\n \tb\tepilogue\n \n retfloat:\n+#ifndef __mips_soft_float\n \tbne     t6, FFI_TYPE_FLOAT, retdouble\n \tjal\tt9\n \tREG_L\tt4, 4*FFI_SIZEOF_ARG($fp)\n@@ -272,6 +284,7 @@ retstruct_f_d:\n \ts.s\t$f0, 0(t4)\n \ts.d\t$f2, 8(t4)\n \tb\tepilogue\n+#endif\n \n retstruct_d_soft:\n \tbne\tt6, FFI_TYPE_STRUCT_D_SOFT, retstruct_f_soft\n@@ -429,6 +442,7 @@ ffi_closure_N32:\n \tREG_S\ta6, A6_OFF2($sp)\n \tREG_S\ta7, A7_OFF2($sp)\n \n+#ifndef __mips_soft_float\n \t# Store all possible float/double registers.\n \ts.d\t$f12, F12_OFF2($sp)\n \ts.d\t$f13, F13_OFF2($sp)\n@@ -438,6 +452,7 @@ ffi_closure_N32:\n \ts.d\t$f17, F17_OFF2($sp)\n \ts.d\t$f18, F18_OFF2($sp)\n \ts.d\t$f19, F19_OFF2($sp)\n+#endif\n \n \t# Call ffi_closure_mips_inner_N32 to do the real work.\n \tLA\tt9, ffi_closure_mips_inner_N32\n@@ -458,6 +473,7 @@ cls_retint:\n \tb\tcls_epilogue\n \n cls_retfloat:\n+#ifndef __mips_soft_float\n \tbne     v0, FFI_TYPE_FLOAT, cls_retdouble\n \tl.s\t$f0, V0_OFF2($sp)\n \tb\tcls_epilogue\n@@ -500,6 +516,7 @@ cls_retstruct_f_d:\n \tl.s\t$f0, V0_OFF2($sp)\n \tl.d\t$f2, V1_OFF2($sp)\n \tb\tcls_epilogue\n+#endif\n \t\n cls_retstruct_small2:\t\n \tREG_L\tv0, V0_OFF2($sp)\n--- a/libffi/src/mips/o32.S\n+++ b/libffi/src/mips/o32.S\n@@ -82,13 +82,16 @@ sixteen:\n \t\t\n \tADDU\t$sp, 4 * FFI_SIZEOF_ARG\t\t# adjust $sp to new args\n \n+#ifndef __mips_soft_float\n \tbnez\tt0, pass_d\t\t\t# make it quick for int\n+#endif\n \tREG_L\ta0, 0*FFI_SIZEOF_ARG($sp)\t# just go ahead and load the\n \tREG_L\ta1, 1*FFI_SIZEOF_ARG($sp)\t# four regs.\n \tREG_L\ta2, 2*FFI_SIZEOF_ARG($sp)\n \tREG_L\ta3, 3*FFI_SIZEOF_ARG($sp)\n \tb\tcall_it\n \n+#ifndef __mips_soft_float\n pass_d:\n \tbne\tt0, FFI_ARGS_D, pass_f\n \tl.d\t$f12, 0*FFI_SIZEOF_ARG($sp)\t# load $fp regs from args\n@@ -130,6 +133,7 @@ pass_f_d:\n  #\tbne\tt0, FFI_ARGS_F_D, call_it\n \tl.s\t$f12, 0*FFI_SIZEOF_ARG($sp)\t# load $fp regs from args\n \tl.d\t$f14, 2*FFI_SIZEOF_ARG($sp)\t# passing double and float\n+#endif\n \n call_it:\t\n \t# Load the function pointer\n@@ -158,14 +162,23 @@ retfloat:\n \tbne     t2, FFI_TYPE_FLOAT, retdouble\n \tjalr\tt9\n \tREG_L\tt0, SIZEOF_FRAME + 4*FFI_SIZEOF_ARG($fp)\n+#ifndef __mips_soft_float\n \ts.s\t$f0, 0(t0)\n+#else\n+\tREG_S v0, 0(t0)\n+#endif\n \tb\tepilogue\n \n retdouble:\t\n \tbne\tt2, FFI_TYPE_DOUBLE, noretval\n \tjalr\tt9\n \tREG_L\tt0, SIZEOF_FRAME + 4*FFI_SIZEOF_ARG($fp)\n+#ifndef __mips_soft_float\n \ts.d\t$f0, 0(t0)\n+#else\n+\tREG_S v1, 4(t0)\n+\tREG_S v0, 0(t0)\n+#endif\n \tb\tepilogue\n \t\n noretval:\t\n@@ -261,9 +274,11 @@ $LCFI7:\n \tli\t$13, 1\t\t# FFI_O32\n \tbne\t$16, $13, 1f\t# Skip fp save if FFI_O32_SOFT_FLOAT\n \t\n+#ifndef __mips_soft_float\n \t# Store all possible float/double registers.\n \ts.d\t$f12, FA_0_0_OFF2($fp)\n \ts.d\t$f14, FA_1_0_OFF2($fp)\n+#endif\n 1:\t\n \t# Call ffi_closure_mips_inner_O32 to do the work.\n \tla\tt9, ffi_closure_mips_inner_O32\n@@ -281,6 +296,7 @@ $LCFI7:\n \tli\t$13, 1\t\t# FFI_O32\n \tbne\t$16, $13, 1f\t# Skip fp restore if FFI_O32_SOFT_FLOAT\n \n+#ifndef __mips_soft_float\n \tli\t$9, FFI_TYPE_FLOAT\n \tl.s\t$f0, V0_OFF2($fp)\n \tbeq\t$8, $9, closure_done\n@@ -288,6 +304,7 @@ $LCFI7:\n \tli\t$9, FFI_TYPE_DOUBLE\n \tl.d\t$f0, V0_OFF2($fp)\n \tbeq\t$8, $9, closure_done\n+#endif\n 1:\t\n \tREG_L\t$3, V1_OFF2($fp)\n \tREG_L\t$2, V0_OFF2($fp)\n"
  },
  {
    "path": "toolchain/gcc/patches/11.2.0/960-gotools-fix-compilation-when-making-cross-compiler.patch",
    "content": "From dda6b050cd74a352670787a294596a9c56c21327 Mon Sep 17 00:00:00 2001\nFrom: Yousong Zhou <yszhou4tech@gmail.com>\nDate: Fri, 4 May 2018 18:20:53 +0800\nSubject: [PATCH] gotools: fix compilation when making cross compiler\n\nlibgo is \"the runtime support library for the Go programming language.\nThis library is intended for use with the Go frontend.\"\n\ngccgo will link target files with libgo.so which depends on libgcc_s.so.1, but\nthe linker will complain that it cannot find it.  That's because shared libgcc\nis not present in the install directory yet.  libgo.so was made without problem\nbecause gcc will emit -lgcc_s when compiled with -shared option.  When gotools\nwere being made, it was supplied with -static-libgcc thus no link option was\nprovided.  Check LIBGO in gcc/go/gcc-spec.c for how gccgo make a builtin spec\nfor linking with libgo.so\n\n- GccgoCrossCompilation, https://github.com/golang/go/wiki/GccgoCrossCompilation\n- Cross-building instructions, http://www.eglibc.org/archives/patches/msg00078.html\n\nWhen 3-pass GCC compilation is used, shared libgcc runtime libraries will be\navailable after gcc pass2 completed and will meet the gotools link requirement\nat gcc pass3\n---\n gotools/Makefile.am | 4 +++-\n gotools/Makefile.in | 4 +++-\n 2 files changed, 6 insertions(+), 2 deletions(-)\n\n--- a/gotools/Makefile.am\n+++ b/gotools/Makefile.am\n@@ -26,6 +26,7 @@ PWD_COMMAND = $${PWDCMD-pwd}\n STAMP = echo timestamp >\n \n libgodir = ../$(target_noncanonical)/libgo\n+libgccdir = ../$(target_noncanonical)/libgcc\n LIBGODEP = $(libgodir)/libgo.la\n \n LIBGOTOOL = $(libgodir)/libgotool.a\n@@ -41,7 +42,8 @@ GOCFLAGS = $(CFLAGS_FOR_TARGET)\n GOCOMPILE = $(GOCOMPILER) $(GOCFLAGS)\n \n AM_GOCFLAGS = -I $(libgodir)\n-AM_LDFLAGS = -L $(libgodir) -L $(libgodir)/.libs\n+AM_LDFLAGS = -L $(libgodir) -L $(libgodir)/.libs \\\n+\t-L $(libgccdir) -L $(libgccdir)/.libs -lgcc_s\n GOLINK = $(GOCOMPILER) $(GOCFLAGS) $(AM_GOCFLAGS) $(LDFLAGS) $(AM_LDFLAGS) -o $@\n \n libgosrcdir = $(srcdir)/../libgo/go\n--- a/gotools/Makefile.in\n+++ b/gotools/Makefile.in\n@@ -337,6 +337,7 @@ mkinstalldirs = $(SHELL) $(toplevel_srcd\n PWD_COMMAND = $${PWDCMD-pwd}\n STAMP = echo timestamp >\n libgodir = ../$(target_noncanonical)/libgo\n+libgccdir = ../$(target_noncanonical)/libgcc\n LIBGODEP = $(libgodir)/libgo.la\n LIBGOTOOL = $(libgodir)/libgotool.a\n @NATIVE_FALSE@GOCOMPILER = $(GOC)\n@@ -346,7 +347,8 @@ LIBGOTOOL = $(libgodir)/libgotool.a\n GOCFLAGS = $(CFLAGS_FOR_TARGET)\n GOCOMPILE = $(GOCOMPILER) $(GOCFLAGS)\n AM_GOCFLAGS = -I $(libgodir)\n-AM_LDFLAGS = -L $(libgodir) -L $(libgodir)/.libs\n+AM_LDFLAGS = -L $(libgodir) -L $(libgodir)/.libs \\\n+\t-L $(libgccdir) -L $(libgccdir)/.libs -lgcc_s\n GOLINK = $(GOCOMPILER) $(GOCFLAGS) $(AM_GOCFLAGS) $(LDFLAGS) $(AM_LDFLAGS) -o $@\n libgosrcdir = $(srcdir)/../libgo/go\n cmdsrcdir = $(libgosrcdir)/cmd\n"
  },
  {
    "path": "toolchain/gcc/patches/11.2.0/970-macos_arm64-building-fix.patch",
    "content": "commit 9c6e71079b46ad5433165feaa2001450f2017b56\nAuthor: Przemysław Buczkowski <prem@prem.moe>\nDate:   Mon Aug 16 13:16:21 2021 +0100\n\n    GCC: Patch for Apple Silicon compatibility\n    \n    This patch fixes a linker error occuring when compiling\n    the cross-compiler on macOS and ARM64 architecture.\n    \n    Adapted from:\n    https://github.com/richfelker/musl-cross-make/issues/116#issuecomment-823612404\n    \n    Change-Id: Ia3ee98a163bbb62689f42e2da83a5ef36beb0913\n    Reviewed-on: https://review.haiku-os.org/c/buildtools/+/4329\n    Reviewed-by: John Scipione <jscipione@gmail.com>\n    Reviewed-by: Adrien Destugues <pulkomandy@gmail.com>\n\n--- a/gcc/config/aarch64/aarch64.h\n+++ b/gcc/config/aarch64/aarch64.h\n@@ -1236,7 +1236,7 @@ extern const char *aarch64_rewrite_mcpu\n #define MCPU_TO_MARCH_SPEC_FUNCTIONS \\\n   { \"rewrite_mcpu\", aarch64_rewrite_mcpu },\n \n-#if defined(__aarch64__)\n+#if defined(__aarch64__) && ! defined(__APPLE__)\n extern const char *host_detect_local_cpu (int argc, const char **argv);\n #define HAVE_LOCAL_CPU_DETECT\n # define EXTRA_SPEC_FUNCTIONS\t\t\t\t\t\t\\\n--- a/gcc/config/host-darwin.c\n+++ b/gcc/config/host-darwin.c\n@@ -22,6 +22,8 @@\n #include \"coretypes.h\"\n #include \"diagnostic-core.h\"\n #include \"config/host-darwin.h\"\n+#include \"hosthooks.h\"\n+#include \"hosthooks-def.h\"\n \n /* Yes, this is really supposed to work.  */\n /* This allows for a pagesize of 16384, which we have on Darwin20, but should\n@@ -79,3 +81,5 @@ darwin_gt_pch_use_address (void *addr, s\n \n   return ret;\n }\n+\n+const struct host_hooks host_hooks = HOST_HOOKS_INITIALIZER;\n"
  },
  {
    "path": "toolchain/gcc/patches/8.4.0/002-case_insensitive.patch",
    "content": "commit 81cc26c706b2bc8c8c1eb1a322e5c5157900836e\nAuthor: Felix Fietkau <nbd@openwrt.org>\nDate:   Sun Oct 19 21:45:51 2014 +0000\n\n    gcc: do not assume that the Mac OS X filesystem is case insensitive\n    \n    Signed-off-by: Felix Fietkau <nbd@openwrt.org>\n    \n    SVN-Revision: 42973\n\n--- a/include/filenames.h\n+++ b/include/filenames.h\n@@ -43,11 +43,6 @@ extern \"C\" {\n #  define IS_DIR_SEPARATOR(c) IS_DOS_DIR_SEPARATOR (c)\n #  define IS_ABSOLUTE_PATH(f) IS_DOS_ABSOLUTE_PATH (f)\n #else /* not DOSish */\n-#  if defined(__APPLE__)\n-#    ifndef HAVE_CASE_INSENSITIVE_FILE_SYSTEM\n-#      define HAVE_CASE_INSENSITIVE_FILE_SYSTEM 1\n-#    endif\n-#  endif /* __APPLE__ */\n #  define HAS_DRIVE_SPEC(f) (0)\n #  define IS_DIR_SEPARATOR(c) IS_UNIX_DIR_SEPARATOR (c)\n #  define IS_ABSOLUTE_PATH(f) IS_UNIX_ABSOLUTE_PATH (f)\n"
  },
  {
    "path": "toolchain/gcc/patches/8.4.0/010-documentation.patch",
    "content": "commit 098bd91f5eae625c7d2ee621e10930fc4434e5e2\nAuthor: Luka Perkov <luka@openwrt.org>\nDate:   Tue Feb 26 16:16:33 2013 +0000\n\n    gcc: don't build documentation\n    \n    This closes #13039.\n    \n    Signed-off-by: Luka Perkov <luka@openwrt.org>\n    \n    SVN-Revision: 35807\n\n--- a/gcc/Makefile.in\n+++ b/gcc/Makefile.in\n@@ -3204,18 +3204,10 @@ doc/gcc.info: $(TEXI_GCC_FILES)\n doc/gccint.info: $(TEXI_GCCINT_FILES)\n doc/cppinternals.info: $(TEXI_CPPINT_FILES)\n \n-doc/%.info: %.texi\n-\tif [ x$(BUILD_INFO) = xinfo ]; then \\\n-\t\t$(MAKEINFO) $(MAKEINFOFLAGS) -I . -I $(gcc_docdir) \\\n-\t\t\t-I $(gcc_docdir)/include -o $@ $<; \\\n-\tfi\n+doc/%.info:\n \n # Duplicate entry to handle renaming of gccinstall.info\n-doc/gccinstall.info: $(TEXI_GCCINSTALL_FILES)\n-\tif [ x$(BUILD_INFO) = xinfo ]; then \\\n-\t\t$(MAKEINFO) $(MAKEINFOFLAGS) -I $(gcc_docdir) \\\n-\t\t\t-I $(gcc_docdir)/include -o $@ $<; \\\n-\tfi\n+doc/gccinstall.info:\n \n doc/cpp.dvi: $(TEXI_CPP_FILES)\n doc/gcc.dvi: $(TEXI_GCC_FILES)\n"
  },
  {
    "path": "toolchain/gcc/patches/8.4.0/110-Fix-MIPS-PR-84790.patch",
    "content": "Fix https://gcc.gnu.org/bugzilla/show_bug.cgi?id=84790.\nMIPS16 functions have a static assembler prologue which clobbers\nregisters v0 and v1. Add these register clobbers to function call\ninstructions.\n\n--- a/gcc/config/mips/mips.c\n+++ b/gcc/config/mips/mips.c\n@@ -3102,6 +3102,12 @@ mips_emit_call_insn (rtx pattern, rtx or\n       emit_insn (gen_update_got_version ());\n     }\n \n+  if (TARGET_MIPS16 && TARGET_USE_GOT)\n+    {\n+      clobber_reg (&CALL_INSN_FUNCTION_USAGE (insn), MIPS16_PIC_TEMP);\n+      clobber_reg (&CALL_INSN_FUNCTION_USAGE (insn), MIPS_PROLOGUE_TEMP (word_mode));\n+    }\n+\n   if (TARGET_MIPS16\n       && TARGET_EXPLICIT_RELOCS\n       && TARGET_CALL_CLOBBERED_GP)\n"
  },
  {
    "path": "toolchain/gcc/patches/8.4.0/230-musl_libssp.patch",
    "content": "--- a/gcc/gcc.c\n+++ b/gcc/gcc.c\n@@ -868,7 +868,9 @@ proper position among the other output f\n #endif\n \n #ifndef LINK_SSP_SPEC\n-#ifdef TARGET_LIBC_PROVIDES_SSP\n+#if DEFAULT_LIBC == LIBC_MUSL\n+#define LINK_SSP_SPEC \"-lssp_nonshared\"\n+#elif defined(TARGET_LIBC_PROVIDES_SSP)\n #define LINK_SSP_SPEC \"%{fstack-protector|fstack-protector-all\" \\\n \t\t       \"|fstack-protector-strong|fstack-protector-explicit:}\"\n #else\n"
  },
  {
    "path": "toolchain/gcc/patches/8.4.0/300-mips_Os_cpu_rtx_cost_model.patch",
    "content": "commit ecf7671b769fe96f7b5134be442089f8bdba55d2\nAuthor: Felix Fietkau <nbd@nbd.name>\nDate:   Thu Aug 4 20:29:45 2016 +0200\n\ngcc: add a patch to generate better code with Os on mips\n\nAlso happens to reduce compressed code size a bit\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n\n--- a/gcc/config/mips/mips.c\n+++ b/gcc/config/mips/mips.c\n@@ -19847,7 +19847,7 @@ mips_option_override (void)\n     flag_pcc_struct_return = 0;\n \n   /* Decide which rtx_costs structure to use.  */\n-  if (optimize_size)\n+  if (0 && optimize_size)\n     mips_cost = &mips_rtx_cost_optimize_size;\n   else\n     mips_cost = &mips_rtx_cost_data[mips_tune];\n"
  },
  {
    "path": "toolchain/gcc/patches/8.4.0/800-arm_v5te_no_ldrd_strd.patch",
    "content": "--- a/gcc/config/arm/arm.h\n+++ b/gcc/config/arm/arm.h\n@@ -155,7 +155,7 @@ extern tree arm_fp16_type_node;\n /* Thumb-1 only.  */\n #define TARGET_THUMB1_ONLY\t\t(TARGET_THUMB1 && !arm_arch_notm)\n \n-#define TARGET_LDRD\t\t\t(arm_arch5e && ARM_DOUBLEWORD_ALIGN \\\n+#define TARGET_LDRD\t\t\t(arm_arch6 && ARM_DOUBLEWORD_ALIGN \\\n                                          && !TARGET_THUMB1)\n \n #define TARGET_CRC32\t\t\t(arm_arch_crc)\n"
  },
  {
    "path": "toolchain/gcc/patches/8.4.0/810-arm-softfloat-libgcc.patch",
    "content": "commit 8570c4be394cff7282f332f97da2ff569a927ddb\nAuthor: Imre Kaloz <kaloz@openwrt.org>\nDate:   Wed Feb 2 20:06:12 2011 +0000\n\n    fixup arm soft-float symbols\n    \n    SVN-Revision: 25325\n\n--- a/libgcc/config/arm/t-linux\n+++ b/libgcc/config/arm/t-linux\n@@ -1,6 +1,10 @@\n LIB1ASMSRC = arm/lib1funcs.S\n LIB1ASMFUNCS = _udivsi3 _divsi3 _umodsi3 _modsi3 _dvmd_lnx _clzsi2 _clzdi2 \\\n-\t_ctzsi2 _arm_addsubdf3 _arm_addsubsf3\n+\t_ctzsi2 _arm_addsubdf3 _arm_addsubsf3 \\\n+\t_arm_negdf2 _arm_muldivdf3 _arm_cmpdf2 _arm_unorddf2 \\\n+\t_arm_fixdfsi _arm_fixunsdfsi _arm_truncdfsf2 \\\n+\t_arm_negsf2 _arm_muldivsf3 _arm_cmpsf2 _arm_unordsf2 \\\n+\t_arm_fixsfsi _arm_fixunssfsi\n \n # Just for these, we omit the frame pointer since it makes such a big\n # difference.\n--- a/gcc/config/arm/linux-elf.h\n+++ b/gcc/config/arm/linux-elf.h\n@@ -58,8 +58,6 @@\n    %{shared:-lc} \\\n    %{!shared:%{profile:-lc_p}%{!profile:-lc}}\"\n \n-#define LIBGCC_SPEC \"%{mfloat-abi=soft*:-lfloat} -lgcc\"\n-\n #define GLIBC_DYNAMIC_LINKER \"/lib/ld-linux.so.2\"\n \n #define LINUX_TARGET_LINK_SPEC  \"%{h*} \\\n"
  },
  {
    "path": "toolchain/gcc/patches/8.4.0/820-libgcc_pic.patch",
    "content": "commit c96312958c0621e72c9b32da5bc224ffe2161384\nAuthor: Felix Fietkau <nbd@openwrt.org>\nDate:   Mon Oct 19 23:26:09 2009 +0000\n\n    gcc: create a proper libgcc_pic.a static library for relinking (4.3.3+ for now, backport will follow)\n    \n    SVN-Revision: 18086\n\n--- a/libgcc/Makefile.in\n+++ b/libgcc/Makefile.in\n@@ -923,11 +923,12 @@ $(libgcov-driver-objects): %$(objext): $\n \n # Static libraries.\n libgcc.a: $(libgcc-objects)\n+libgcc_pic.a: $(libgcc-s-objects)\n libgcov.a: $(libgcov-objects)\n libunwind.a: $(libunwind-objects)\n libgcc_eh.a: $(libgcc-eh-objects)\n \n-libgcc.a libgcov.a libunwind.a libgcc_eh.a:\n+libgcc.a libgcov.a libunwind.a libgcc_eh.a libgcc_pic.a:\n \t-rm -f $@\n \n \tobjects=\"$(objects)\";\t\t\t\t\t\\\n@@ -948,7 +949,7 @@ all: libunwind.a\n endif\n \n ifeq ($(enable_shared),yes)\n-all: libgcc_eh.a libgcc_s$(SHLIB_EXT)\n+all: libgcc_eh.a libgcc_pic.a libgcc_s$(SHLIB_EXT)\n ifneq ($(LIBUNWIND),)\n all: libunwind$(SHLIB_EXT)\n libgcc_s$(SHLIB_EXT): libunwind$(SHLIB_EXT)\n@@ -1154,6 +1155,10 @@ install-shared:\n \tchmod 644 $(DESTDIR)$(inst_libdir)/libgcc_eh.a\n \t$(RANLIB) $(DESTDIR)$(inst_libdir)/libgcc_eh.a\n \n+\t$(INSTALL_DATA) libgcc_pic.a $(mapfile) $(DESTDIR)$(inst_libdir)/\n+\tchmod 644 $(DESTDIR)$(inst_libdir)/libgcc_pic.a\n+\t$(RANLIB) $(DESTDIR)$(inst_libdir)/libgcc_pic.a\n+\n \t$(subst @multilib_dir@,$(MULTIDIR),$(subst \\\n \t\t@shlib_base_name@,libgcc_s,$(subst \\\n \t\t@shlib_slibdir_qual@,$(MULTIOSSUBDIR),$(SHLIB_INSTALL))))\n"
  },
  {
    "path": "toolchain/gcc/patches/8.4.0/840-armv4_pass_fix-v4bx_to_ld.patch",
    "content": "commit 7edc8ca5456d9743dd0075eb3cc5b04f4f24c8cc\nAuthor: Imre Kaloz <kaloz@openwrt.org>\nDate:   Wed Feb 2 19:34:36 2011 +0000\n\n    add armv4 fixup patches\n    \n    SVN-Revision: 25322\n\n\n--- a/gcc/config/arm/linux-eabi.h\n+++ b/gcc/config/arm/linux-eabi.h\n@@ -88,10 +88,15 @@\n #define MUSL_DYNAMIC_LINKER \\\n   \"/lib/ld-musl-arm\" MUSL_DYNAMIC_LINKER_E \"%{mfloat-abi=hard:hf}.so.1\"\n \n+/* For armv4 we pass --fix-v4bx to linker to support EABI */\n+#undef TARGET_FIX_V4BX_SPEC\n+#define TARGET_FIX_V4BX_SPEC \" %{mcpu=arm8|mcpu=arm810|mcpu=strongarm*\"\\\n+  \"|march=armv4|mcpu=fa526|mcpu=fa626:--fix-v4bx}\"\n+\n /* At this point, bpabi.h will have clobbered LINK_SPEC.  We want to\n    use the GNU/Linux version, not the generic BPABI version.  */\n #undef  LINK_SPEC\n-#define LINK_SPEC EABI_LINK_SPEC\t\t\t\t\t\\\n+#define LINK_SPEC EABI_LINK_SPEC TARGET_FIX_V4BX_SPEC\t\t\t\\\n   LINUX_OR_ANDROID_LD (LINUX_TARGET_LINK_SPEC,\t\t\t\t\\\n \t\t       LINUX_TARGET_LINK_SPEC \" \" ANDROID_LINK_SPEC)\n \n"
  },
  {
    "path": "toolchain/gcc/patches/8.4.0/850-use_shared_libgcc.patch",
    "content": "commit dcfc40358b5a3cae7320c17f8d1cebd5ad5540cd\nAuthor: Felix Fietkau <nbd@openwrt.org>\nDate:   Sun Feb 12 20:25:47 2012 +0000\n\n    gcc 4.6: port over the missing patch 850-use_shared_libgcc.patch to prevent libgcc crap from leaking into every single binary\n    \n    SVN-Revision: 30486\n--- a/gcc/config/arm/linux-eabi.h\n+++ b/gcc/config/arm/linux-eabi.h\n@@ -126,10 +126,6 @@\n   \"%{Ofast|ffast-math|funsafe-math-optimizations:crtfastmath.o%s} \"\t\\\n   LINUX_OR_ANDROID_LD (GNU_USER_TARGET_ENDFILE_SPEC, ANDROID_ENDFILE_SPEC)\n \n-/* Use the default LIBGCC_SPEC, not the version in linux-elf.h, as we\n-   do not use -lfloat.  */\n-#undef LIBGCC_SPEC\n-\n /* Clear the instruction cache from `beg' to `end'.  This is\n    implemented in lib1funcs.S, so ensure an error if this definition\n    is used.  */\n--- a/gcc/config/linux.h\n+++ b/gcc/config/linux.h\n@@ -53,6 +53,10 @@ see the files COPYING3 and COPYING.RUNTI\n \tbuiltin_assert (\"system=posix\");\t\t\t\\\n     } while (0)\n \n+#ifndef LIBGCC_SPEC\n+#define LIBGCC_SPEC \"%{static|static-libgcc:-lgcc}%{!static:%{!static-libgcc:-lgcc_s}}\"\n+#endif\n+\n /* Determine which dynamic linker to use depending on whether GLIBC or\n    uClibc or Bionic or musl is the default C library and whether\n    -muclibc or -mglibc or -mbionic or -mmusl has been passed to change\n--- a/libgcc/mkmap-symver.awk\n+++ b/libgcc/mkmap-symver.awk\n@@ -136,5 +136,5 @@ function output(lib) {\n   else if (inherit[lib])\n     printf(\"} %s;\\n\", inherit[lib]);\n   else\n-    printf (\"\\n  local:\\n\\t*;\\n};\\n\");\n+    printf (\"\\n\\t*;\\n};\\n\");\n }\n--- a/gcc/config/rs6000/linux.h\n+++ b/gcc/config/rs6000/linux.h\n@@ -60,6 +60,9 @@\n #undef\tCPP_OS_DEFAULT_SPEC\n #define CPP_OS_DEFAULT_SPEC \"%(cpp_os_linux)\"\n \n+#undef LIBGCC_SPEC\n+#define LIBGCC_SPEC \"%{!static:%{!static-libgcc:-lgcc_s}} -lgcc\"\n+\n #undef  LINK_SHLIB_SPEC\n #define LINK_SHLIB_SPEC \"%{shared:-shared} %{!shared: %{static:-static}} \\\n   %{static-pie:-static -pie --no-dynamic-linker -z text}\"\n"
  },
  {
    "path": "toolchain/gcc/patches/8.4.0/851-libgcc_no_compat.patch",
    "content": "commit 64661de100da1ec1061ef3e5e400285dce115e6b\nAuthor: Felix Fietkau <nbd@openwrt.org>\nDate:   Sun May 10 13:16:35 2015 +0000\n\n    gcc: add some size optimization patches\n    \n    Signed-off-by: Felix Fietkau <nbd@openwrt.org>\n    \n    SVN-Revision: 45664\n\n--- a/libgcc/config/t-libunwind\n+++ b/libgcc/config/t-libunwind\n@@ -2,8 +2,7 @@\n \n HOST_LIBGCC2_CFLAGS += -DUSE_GAS_SYMVER\n \n-LIB2ADDEH = $(srcdir)/unwind-sjlj.c $(srcdir)/unwind-c.c \\\n-  $(srcdir)/unwind-compat.c $(srcdir)/unwind-dw2-fde-compat.c\n+LIB2ADDEH = $(srcdir)/unwind-sjlj.c $(srcdir)/unwind-c.c\n LIB2ADDEHSTATIC = $(srcdir)/unwind-sjlj.c $(srcdir)/unwind-c.c\n \n # Override the default value from t-slibgcc-elf-ver and mention -lunwind\n"
  },
  {
    "path": "toolchain/gcc/patches/8.4.0/870-ppc_no_crtsavres.patch",
    "content": "--- a/gcc/config/rs6000/rs6000.c\n+++ b/gcc/config/rs6000/rs6000.c\n@@ -24780,7 +24780,7 @@ rs6000_savres_strategy (rs6000_stack_t *\n   /* Define cutoff for using out-of-line functions to save registers.  */\n   if (DEFAULT_ABI == ABI_V4 || TARGET_ELF)\n     {\n-      if (!optimize_size)\n+      if (1)\n \t{\n \t  strategy |= SAVE_INLINE_FPRS | REST_INLINE_FPRS;\n \t  strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;\n"
  },
  {
    "path": "toolchain/gcc/patches/8.4.0/881-no_tm_section.patch",
    "content": "--- a/libgcc/crtstuff.c\n+++ b/libgcc/crtstuff.c\n@@ -152,7 +152,7 @@ call_ ## FUNC (void)\t\t\t\t\t\\\n #endif\n \n #if !defined(USE_TM_CLONE_REGISTRY) && defined(OBJECT_FORMAT_ELF)\n-# define USE_TM_CLONE_REGISTRY 1\n+# define USE_TM_CLONE_REGISTRY 0\n #endif\n \n /* We do not want to add the weak attribute to the declarations of these\n"
  },
  {
    "path": "toolchain/gcc/patches/8.4.0/900-bad-mips16-crt.patch",
    "content": "--- a/libgcc/config/mips/t-mips16\n+++ b/libgcc/config/mips/t-mips16\n@@ -43,3 +43,6 @@ SYNC_CFLAGS = -mno-mips16\n \n # Version these symbols if building libgcc.so.\n SHLIB_MAPFILES += $(srcdir)/config/mips/libgcc-mips16.ver\n+\n+CRTSTUFF_T_CFLAGS += -mno-mips16\n+CRTSTUFF_T_CFLAGS_S += -mno-mips16\n"
  },
  {
    "path": "toolchain/gcc/patches/8.4.0/910-mbsd_multi.patch",
    "content": "commit 99368862e44740ff4fd33760893f04e14f9dbdf1\nAuthor: Felix Fietkau <nbd@openwrt.org>\nDate:   Tue Jul 31 00:52:27 2007 +0000\n\n    Port the mbsd_multi patch from freewrt, which adds -fhonour-copts. This will emit warnings in packages that don't use our target cflags properly\n    \n    SVN-Revision: 8256\n\n\tThis patch brings over a feature from MirBSD:\n\t* -fhonour-copts\n\t  If this option is not given, it's warned (depending\n\t  on environment variables). This is to catch errors\n\t  of misbuilt packages which override CFLAGS themselves.\n\n\tThis patch was authored by Thorsten Glaser <tg at mirbsd.de>\n\twith copyright assignment to the FSF in effect.\n\n--- a/gcc/c-family/c-opts.c\n+++ b/gcc/c-family/c-opts.c\n@@ -107,6 +107,9 @@ static dump_flags_t original_dump_flags;\n /* Whether any standard preincluded header has been preincluded.  */\n static bool done_preinclude;\n \n+/* Check if a port honours COPTS.  */\n+static int honour_copts = 0;\n+\n static void handle_OPT_d (const char *);\n static void set_std_cxx98 (int);\n static void set_std_cxx11 (int);\n@@ -459,6 +462,12 @@ c_common_handle_option (size_t scode, co\n       flag_no_builtin = !value;\n       break;\n \n+    case OPT_fhonour_copts:\n+      if (c_language == clk_c) {\n+        honour_copts++;\n+      }\n+      break;\n+\n     case OPT_fconstant_string_class_:\n       constant_string_class_name = arg;\n       break;\n@@ -1125,6 +1134,47 @@ c_common_init (void)\n       return false;\n     }\n \n+  if (c_language == clk_c) {\n+    char *ev = getenv (\"GCC_HONOUR_COPTS\");\n+    int evv;\n+    if (ev == NULL)\n+      evv = -1;\n+    else if ((*ev == '0') || (*ev == '\\0'))\n+      evv = 0;\n+    else if (*ev == '1')\n+      evv = 1;\n+    else if (*ev == '2')\n+      evv = 2;\n+    else if (*ev == 's')\n+      evv = -1;\n+    else {\n+      warning (0, \"unknown GCC_HONOUR_COPTS value, assuming 1\");\n+      evv = 1; /* maybe depend this on something like MIRBSD_NATIVE?  */\n+    }\n+    if (evv == 1) {\n+      if (honour_copts == 0) {\n+        error (\"someone does not honour COPTS at all in lenient mode\");\n+        return false;\n+      } else if (honour_copts != 1) {\n+        warning (0, \"someone does not honour COPTS correctly, passed %d times\",\n+         honour_copts);\n+      }\n+    } else if (evv == 2) {\n+      if (honour_copts == 0) {\n+        error (\"someone does not honour COPTS at all in strict mode\");\n+        return false;\n+      } else if (honour_copts != 1) {\n+        error (\"someone does not honour COPTS correctly, passed %d times\",\n+         honour_copts);\n+        return false;\n+      }\n+    } else if (evv == 0) {\n+      if (honour_copts != 1)\n+        inform (UNKNOWN_LOCATION, \"someone does not honour COPTS correctly, passed %d times\",\n+         honour_copts);\n+    }\n+  }\n+\n   return true;\n }\n \n--- a/gcc/c-family/c.opt\n+++ b/gcc/c-family/c.opt\n@@ -1469,6 +1469,9 @@ C++ ObjC++ Optimization Alias(fexception\n fhonor-std\n C++ ObjC++ Ignore Warn(switch %qs is no longer supported)\n \n+fhonour-copts\n+C ObjC C++ ObjC++ RejectNegative\n+\n fhosted\n C ObjC\n Assume normal C execution environment.\n--- a/gcc/common.opt\n+++ b/gcc/common.opt\n@@ -1551,6 +1551,9 @@ fguess-branch-probability\n Common Report Var(flag_guess_branch_prob) Optimization\n Enable guessing of branch probabilities.\n \n+fhonour-copts\n+Common RejectNegative\n+\n ; Nonzero means ignore `#ident' directives.  0 means handle them.\n ; Generate position-independent code for executables if possible\n ; On SVR4 targets, it also controls whether or not to emit a\n--- a/gcc/opts.c\n+++ b/gcc/opts.c\n@@ -2073,6 +2073,9 @@ common_handle_option (struct gcc_options\n \t\t\t       opts, opts_set, loc, dc);\n       break;\n \n+    case OPT_fhonour_copts:\n+      break;\n+\n     case OPT_Wlarger_than_:\n       opts->x_larger_than_size = value;\n       opts->x_warn_larger_than = value != -1;\n--- a/gcc/doc/invoke.texi\n+++ b/gcc/doc/invoke.texi\n@@ -7013,6 +7013,17 @@ This option is only supported for C and\n @option{-Wall} and by @option{-Wpedantic}, which can be disabled with\n @option{-Wno-pointer-sign}.\n \n+@item -fhonour-copts\n+@opindex fhonour-copts\n+If @env{GCC_HONOUR_COPTS} is set to 1, abort if this option is not\n+given at least once, and warn if it is given more than once.\n+If @env{GCC_HONOUR_COPTS} is set to 2, abort if this option is not\n+given exactly once.\n+If @env{GCC_HONOUR_COPTS} is set to 0 or unset, warn if this option\n+is not given exactly once.\n+The warning is quelled if @env{GCC_HONOUR_COPTS} is set to @samp{s}.\n+This flag and environment variable only affect the C language.\n+\n @item -Wstack-protector\n @opindex Wstack-protector\n @opindex Wno-stack-protector\n"
  },
  {
    "path": "toolchain/gcc/patches/8.4.0/920-specs_nonfatal_getenv.patch",
    "content": "Author: Jo-Philipp Wich <jow@openwrt.org>\nDate:   Sat Apr 21 03:02:39 2012 +0000\n\n    gcc: add patch to make the getenv() spec function nonfatal if requested environment variable is unset\n    \n    SVN-Revision: 31390\n\n--- a/gcc/gcc.c\n+++ b/gcc/gcc.c\n@@ -9347,8 +9347,10 @@ getenv_spec_function (int argc, const ch\n     value = varname;\n \n   if (!value)\n-    fatal_error (input_location,\n-\t\t \"environment variable %qs not defined\", varname);\n+    {\n+      warning (input_location, \"environment variable %qs not defined\", varname);\n+      value = \"\";\n+    }\n \n   /* We have to escape every character of the environment variable so\n      they are not interpreted as active spec characters.  A\n"
  },
  {
    "path": "toolchain/gcc/patches/8.4.0/930-fix-mips-noexecstack.patch",
    "content": "From da45b3fde60095756f5f6030f6012c23a3d34429 Mon Sep 17 00:00:00 2001\nFrom: Andrew McDonnell <bugs@andrewmcdonnell.net>\nDate: Fri, 3 Oct 2014 19:09:00 +0930\nSubject: Add .note.GNU-stack section\n\nSee http://lists.busybox.net/pipermail/uclibc/2014-October/048671.html\nBelow copied from https://gcc.gnu.org/ml/gcc-patches/2014-09/msg02430.html\n\nRe: [Patch, MIPS] Add .note.GNU-stack section\n\n    From: Steve Ellcey <sellcey at mips dot com>\n\nOn Wed, 2014-09-10 at 10:15 -0700, Eric Christopher wrote:\n>\n>\n> On Wed, Sep 10, 2014 at 9:27 AM, <pinskia@gmail.com> wrote:\n\n>         This works except you did not update the assembly files in\n>         libgcc or glibc. We (Cavium) have the same patch in our tree\n>         for a few released versions.\n\n> Mind just checking yours in then Andrew?\n\n> Thanks!\n> -eric\n\nI talked to Andrew about what files he changed in GCC and created and\ntested this new patch.  Andrew also mentioned changing some assembly\nfiles in glibc but I don't see any use of '.section .note.GNU-stack' in\nany assembly files in glibc (for any platform) so I wasn't planning on\ncreating a glibc to add them to mips glibc assembly language files.\n\nOK to check in this patch?\n\nSteve Ellcey\nsellcey@mips.com\n\n\n\n2014-09-26  Steve Ellcey  <sellcey@mips.com>\n---\n gcc/config/mips/mips.c          | 3 +++\n libgcc/config/mips/crti.S       | 4 ++++\n libgcc/config/mips/crtn.S       | 3 +++\n libgcc/config/mips/mips16.S     | 4 ++++\n libgcc/config/mips/vr4120-div.S | 4 ++++\n 5 files changed, 18 insertions(+)\n\n--- a/gcc/config/mips/mips.c\n+++ b/gcc/config/mips/mips.c\n@@ -22640,6 +22640,9 @@ mips_starting_frame_offset (void)\n #undef TARGET_STARTING_FRAME_OFFSET\n #define TARGET_STARTING_FRAME_OFFSET mips_starting_frame_offset\n \n+#undef TARGET_ASM_FILE_END\n+#define TARGET_ASM_FILE_END file_end_indicate_exec_stack\n+\n struct gcc_target targetm = TARGET_INITIALIZER;\n \f\n #include \"gt-mips.h\"\n--- a/libgcc/config/mips/crti.S\n+++ b/libgcc/config/mips/crti.S\n@@ -21,6 +21,10 @@ a copy of the GCC Runtime Library Except\n see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see\n <http://www.gnu.org/licenses/>.  */\n \n+\n+/* An executable stack is *not* required for these functions.  */\n+\t.section .note.GNU-stack,\"\",%progbits\n+\n /* 4 slots for argument spill area.  1 for cpreturn, 1 for stack.\n    Return spill offset of 40 and 20.  Aligned to 16 bytes for n32.  */\n \n--- a/libgcc/config/mips/crtn.S\n+++ b/libgcc/config/mips/crtn.S\n@@ -21,6 +21,9 @@ a copy of the GCC Runtime Library Except\n see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see\n <http://www.gnu.org/licenses/>.  */\n \n+/* An executable stack is *not* required for these functions.  */\n+\t.section .note.GNU-stack,\"\",%progbits\n+\n /* 4 slots for argument spill area.  1 for cpreturn, 1 for stack.\n    Return spill offset of 40 and 20.  Aligned to 16 bytes for n32.  */\n \n--- a/libgcc/config/mips/mips16.S\n+++ b/libgcc/config/mips/mips16.S\n@@ -48,6 +48,10 @@ see the files COPYING3 and COPYING.RUNTI\n    values using the soft-float calling convention, but do the actual\n    operation using the hard floating point instructions.  */\n \n+/* An executable stack is *not* required for these functions.  */\n+\t.section .note.GNU-stack,\"\",%progbits\n+\t.previous\n+\n #if defined _MIPS_SIM && (_MIPS_SIM == _ABIO32 || _MIPS_SIM == _ABIO64)\n \n /* This file contains 32-bit assembly code.  */\n--- a/libgcc/config/mips/vr4120-div.S\n+++ b/libgcc/config/mips/vr4120-div.S\n@@ -26,6 +26,10 @@ see the files COPYING3 and COPYING.RUNTI\n    -mfix-vr4120.  div and ddiv do not give the correct result when one\n    of the operands is negative.  */\n \n+/* An executable stack is *not* required for these functions.  */\n+\t.section .note.GNU-stack,\"\",%progbits\n+\t.previous\n+\n \t.set\tnomips16\n \n #define DIV\t\t\t\t\t\t\t\t\\\n"
  },
  {
    "path": "toolchain/gcc/patches/8.4.0/931-libffi-fix-MIPS-softfloat-build-issue.patch",
    "content": "From c0c62fa4256f805389f16ebfc4a60cf789129b50 Mon Sep 17 00:00:00 2001\nFrom: BangLang Huang <banglang.huang@foxmail.com>\nDate: Wed, 9 Nov 2016 10:36:49 +0800\nSubject: [PATCH] libffi: fix MIPS softfloat build issue\n\nBackported from github.com/libffi/libffi#272\n\nSigned-off-by: BangLang Huang <banglang.huang@foxmail.com>\nSigned-off-by: Yousong Zhou <yszhou4tech@gmail.com>\n---\n libffi/src/mips/n32.S | 17 +++++++++++++++++\n libffi/src/mips/o32.S | 17 +++++++++++++++++\n 2 files changed, 34 insertions(+)\n\n--- a/libffi/src/mips/n32.S\n+++ b/libffi/src/mips/n32.S\n@@ -107,6 +107,16 @@ loadregs:\n \n \tREG_L\tt6, 3*FFI_SIZEOF_ARG($fp)  # load the flags word into t6.\n \n+#ifdef __mips_soft_float\n+\tREG_L\ta0, 0*FFI_SIZEOF_ARG(t9)\n+\tREG_L\ta1, 1*FFI_SIZEOF_ARG(t9)\n+\tREG_L\ta2, 2*FFI_SIZEOF_ARG(t9)\n+\tREG_L\ta3, 3*FFI_SIZEOF_ARG(t9)\n+\tREG_L\ta4, 4*FFI_SIZEOF_ARG(t9)\n+\tREG_L\ta5, 5*FFI_SIZEOF_ARG(t9)\n+\tREG_L\ta6, 6*FFI_SIZEOF_ARG(t9)\n+\tREG_L\ta7, 7*FFI_SIZEOF_ARG(t9)\n+#else\n \tand\tt4, t6, ((1<<FFI_FLAG_BITS)-1)\n \tREG_L\ta0, 0*FFI_SIZEOF_ARG(t9)\n \tbeqz\tt4, arg1_next\n@@ -193,6 +203,7 @@ arg7_next:\n arg8_doublep:\t\n  \tl.d\t$f19, 7*FFI_SIZEOF_ARG(t9)\t\n arg8_next:\t\n+#endif\n \n callit:\t\t\n \t# Load the function pointer\n@@ -214,6 +225,7 @@ retint:\n \tb\tepilogue\n \n retfloat:\n+#ifndef __mips_soft_float\n \tbne     t6, FFI_TYPE_FLOAT, retdouble\n \tjal\tt9\n \tREG_L\tt4, 4*FFI_SIZEOF_ARG($fp)\n@@ -272,6 +284,7 @@ retstruct_f_d:\n \ts.s\t$f0, 0(t4)\n \ts.d\t$f2, 8(t4)\n \tb\tepilogue\n+#endif\n \n retstruct_d_soft:\n \tbne\tt6, FFI_TYPE_STRUCT_D_SOFT, retstruct_f_soft\n@@ -429,6 +442,7 @@ ffi_closure_N32:\n \tREG_S\ta6, A6_OFF2($sp)\n \tREG_S\ta7, A7_OFF2($sp)\n \n+#ifndef __mips_soft_float\n \t# Store all possible float/double registers.\n \ts.d\t$f12, F12_OFF2($sp)\n \ts.d\t$f13, F13_OFF2($sp)\n@@ -438,6 +452,7 @@ ffi_closure_N32:\n \ts.d\t$f17, F17_OFF2($sp)\n \ts.d\t$f18, F18_OFF2($sp)\n \ts.d\t$f19, F19_OFF2($sp)\n+#endif\n \n \t# Call ffi_closure_mips_inner_N32 to do the real work.\n \tLA\tt9, ffi_closure_mips_inner_N32\n@@ -458,6 +473,7 @@ cls_retint:\n \tb\tcls_epilogue\n \n cls_retfloat:\n+#ifndef __mips_soft_float\n \tbne     v0, FFI_TYPE_FLOAT, cls_retdouble\n \tl.s\t$f0, V0_OFF2($sp)\n \tb\tcls_epilogue\n@@ -500,6 +516,7 @@ cls_retstruct_f_d:\n \tl.s\t$f0, V0_OFF2($sp)\n \tl.d\t$f2, V1_OFF2($sp)\n \tb\tcls_epilogue\n+#endif\n \t\n cls_retstruct_small2:\t\n \tREG_L\tv0, V0_OFF2($sp)\n--- a/libffi/src/mips/o32.S\n+++ b/libffi/src/mips/o32.S\n@@ -82,13 +82,16 @@ sixteen:\n \t\t\n \tADDU\t$sp, 4 * FFI_SIZEOF_ARG\t\t# adjust $sp to new args\n \n+#ifndef __mips_soft_float\n \tbnez\tt0, pass_d\t\t\t# make it quick for int\n+#endif\n \tREG_L\ta0, 0*FFI_SIZEOF_ARG($sp)\t# just go ahead and load the\n \tREG_L\ta1, 1*FFI_SIZEOF_ARG($sp)\t# four regs.\n \tREG_L\ta2, 2*FFI_SIZEOF_ARG($sp)\n \tREG_L\ta3, 3*FFI_SIZEOF_ARG($sp)\n \tb\tcall_it\n \n+#ifndef __mips_soft_float\n pass_d:\n \tbne\tt0, FFI_ARGS_D, pass_f\n \tl.d\t$f12, 0*FFI_SIZEOF_ARG($sp)\t# load $fp regs from args\n@@ -130,6 +133,7 @@ pass_f_d:\n  #\tbne\tt0, FFI_ARGS_F_D, call_it\n \tl.s\t$f12, 0*FFI_SIZEOF_ARG($sp)\t# load $fp regs from args\n \tl.d\t$f14, 2*FFI_SIZEOF_ARG($sp)\t# passing double and float\n+#endif\n \n call_it:\t\n \t# Load the function pointer\n@@ -158,14 +162,23 @@ retfloat:\n \tbne     t2, FFI_TYPE_FLOAT, retdouble\n \tjalr\tt9\n \tREG_L\tt0, SIZEOF_FRAME + 4*FFI_SIZEOF_ARG($fp)\n+#ifndef __mips_soft_float\n \ts.s\t$f0, 0(t0)\n+#else\n+\tREG_S v0, 0(t0)\n+#endif\n \tb\tepilogue\n \n retdouble:\t\n \tbne\tt2, FFI_TYPE_DOUBLE, noretval\n \tjalr\tt9\n \tREG_L\tt0, SIZEOF_FRAME + 4*FFI_SIZEOF_ARG($fp)\n+#ifndef __mips_soft_float\n \ts.d\t$f0, 0(t0)\n+#else\n+\tREG_S v1, 4(t0)\n+\tREG_S v0, 0(t0)\n+#endif\n \tb\tepilogue\n \t\n noretval:\t\n@@ -261,9 +274,11 @@ $LCFI7:\n \tli\t$13, 1\t\t# FFI_O32\n \tbne\t$16, $13, 1f\t# Skip fp save if FFI_O32_SOFT_FLOAT\n \t\n+#ifndef __mips_soft_float\n \t# Store all possible float/double registers.\n \ts.d\t$f12, FA_0_0_OFF2($fp)\n \ts.d\t$f14, FA_1_0_OFF2($fp)\n+#endif\n 1:\t\n \t# Call ffi_closure_mips_inner_O32 to do the work.\n \tla\tt9, ffi_closure_mips_inner_O32\n@@ -281,6 +296,7 @@ $LCFI7:\n \tli\t$13, 1\t\t# FFI_O32\n \tbne\t$16, $13, 1f\t# Skip fp restore if FFI_O32_SOFT_FLOAT\n \n+#ifndef __mips_soft_float\n \tli\t$9, FFI_TYPE_FLOAT\n \tl.s\t$f0, V0_OFF2($fp)\n \tbeq\t$8, $9, closure_done\n@@ -288,6 +304,7 @@ $LCFI7:\n \tli\t$9, FFI_TYPE_DOUBLE\n \tl.d\t$f0, V0_OFF2($fp)\n \tbeq\t$8, $9, closure_done\n+#endif\n 1:\t\n \tREG_L\t$3, V1_OFF2($fp)\n \tREG_L\t$2, V0_OFF2($fp)\n"
  },
  {
    "path": "toolchain/gcc/patches/8.4.0/960-gotools-fix-compilation-when-making-cross-compiler.patch",
    "content": "From dda6b050cd74a352670787a294596a9c56c21327 Mon Sep 17 00:00:00 2001\nFrom: Yousong Zhou <yszhou4tech@gmail.com>\nDate: Fri, 4 May 2018 18:20:53 +0800\nSubject: [PATCH] gotools: fix compilation when making cross compiler\n\nlibgo is \"the runtime support library for the Go programming language.\nThis library is intended for use with the Go frontend.\"\n\ngccgo will link target files with libgo.so which depends on libgcc_s.so.1, but\nthe linker will complain that it cannot find it.  That's because shared libgcc\nis not present in the install directory yet.  libgo.so was made without problem\nbecause gcc will emit -lgcc_s when compiled with -shared option.  When gotools\nwere being made, it was supplied with -static-libgcc thus no link option was\nprovided.  Check LIBGO in gcc/go/gcc-spec.c for how gccgo make a builtin spec\nfor linking with libgo.so\n\n- GccgoCrossCompilation, https://github.com/golang/go/wiki/GccgoCrossCompilation\n- Cross-building instructions, http://www.eglibc.org/archives/patches/msg00078.html\n\nWhen 3-pass GCC compilation is used, shared libgcc runtime libraries will be\navailable after gcc pass2 completed and will meet the gotools link requirement\nat gcc pass3\n---\n gotools/Makefile.am | 4 +++-\n gotools/Makefile.in | 4 +++-\n 2 files changed, 6 insertions(+), 2 deletions(-)\n\n--- a/gotools/Makefile.am\n+++ b/gotools/Makefile.am\n@@ -26,6 +26,7 @@ PWD_COMMAND = $${PWDCMD-pwd}\n STAMP = echo timestamp >\n \n libgodir = ../$(target_noncanonical)/libgo\n+libgccdir = ../$(target_noncanonical)/libgcc\n LIBGODEP = $(libgodir)/libgo.la\n \n LIBGOTOOL = $(libgodir)/libgotool.a\n@@ -41,7 +42,8 @@ GOCFLAGS = $(CFLAGS_FOR_TARGET)\n GOCOMPILE = $(GOCOMPILER) $(GOCFLAGS)\n \n AM_GOCFLAGS = -I $(libgodir)\n-AM_LDFLAGS = -L $(libgodir) -L $(libgodir)/.libs\n+AM_LDFLAGS = -L $(libgodir) -L $(libgodir)/.libs \\\n+\t-L $(libgccdir) -L $(libgccdir)/.libs -lgcc_s\n GOLINK = $(GOCOMPILER) $(GOCFLAGS) $(AM_GOCFLAGS) $(LDFLAGS) $(AM_LDFLAGS) -o $@\n \n libgosrcdir = $(srcdir)/../libgo/go\n--- a/gotools/Makefile.in\n+++ b/gotools/Makefile.in\n@@ -263,6 +263,7 @@ mkinstalldirs = $(SHELL) $(toplevel_srcd\n PWD_COMMAND = $${PWDCMD-pwd}\n STAMP = echo timestamp >\n libgodir = ../$(target_noncanonical)/libgo\n+libgccdir = ../$(target_noncanonical)/libgcc\n LIBGODEP = $(libgodir)/libgo.la\n LIBGOTOOL = $(libgodir)/libgotool.a\n @NATIVE_FALSE@GOCOMPILER = $(GOC)\n@@ -271,7 +272,8 @@ LIBGOTOOL = $(libgodir)/libgotool.a\n @NATIVE_TRUE@GOCOMPILER = $(GOC_FOR_TARGET) $(XGCC_FLAGS_FOR_TARGET)\n GOCOMPILE = $(GOCOMPILER) $(GOCFLAGS)\n AM_GOCFLAGS = -I $(libgodir)\n-AM_LDFLAGS = -L $(libgodir) -L $(libgodir)/.libs\n+AM_LDFLAGS = -L $(libgodir) -L $(libgodir)/.libs \\\n+\t-L $(libgccdir) -L $(libgccdir)/.libs -lgcc_s\n GOLINK = $(GOCOMPILER) $(GOCFLAGS) $(AM_GOCFLAGS) $(LDFLAGS) $(AM_LDFLAGS) -o $@\n libgosrcdir = $(srcdir)/../libgo/go\n cmdsrcdir = $(libgosrcdir)/cmd\n"
  },
  {
    "path": "toolchain/gdb/Makefile",
    "content": "#\n# Copyright (C) 2006-2020 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=gdb\nPKG_VERSION:=11.2\nPKG_RELEASE:=1\n\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz\nPKG_SOURCE_URL:=@GNU/gdb\nPKG_HASH:=1497c36a71881b8671a9a84a0ee40faab788ca30d7ba19d8463c3cc787152e32\nGDB_DIR:=$(PKG_NAME)-$(PKG_VERSION)\n\nHOST_BUILD_DIR:=$(BUILD_DIR_TOOLCHAIN)/$(GDB_DIR)\n\nHOST_BUILD_PARALLEL:=1\n\ninclude $(INCLUDE_DIR)/toolchain-build.mk\n\nHOST_CONFIGURE_VARS += \\\n\tacx_cv_cc_gcc_supports_ada=false \\\n\tgdb_cv_func_sigsetjmp=yes\n\nHOST_CONFIGURE_ARGS = \\\n\t--prefix=$(TOOLCHAIN_DIR) \\\n\t--build=$(GNU_HOST_NAME) \\\n\t--host=$(GNU_HOST_NAME) \\\n\t--target=$(REAL_GNU_TARGET_NAME) \\\n\t--with-gmp=$(TOPDIR)/staging_dir/host \\\n\t--with-mpfr=$(TOPDIR)/staging_dir/host \\\n\t--with-mpc=$(TOPDIR)/staging_dir/host \\\n\t--disable-werror \\\n\t--without-uiout \\\n\t--enable-tui --disable-gdbtk --without-x \\\n\t--without-included-gettext \\\n\t--enable-threads \\\n\t--with-expat \\\n\t--disable-unit-tests \\\n\t--disable-ubsan \\\n\t--disable-binutils \\\n\t--disable-ld \\\n\t--disable-gas \\\n\t--disable-sim\n\nifneq ($(CONFIG_GDB_PYTHON),)\n  HOST_CONFIGURE_ARGS+= --with-python\nelse\n  HOST_CONFIGURE_ARGS+= --without-python\nendif\n\ndefine Host/Install\n\tmkdir -p $(TOOLCHAIN_DIR)/bin\n\t$(INSTALL_BIN) $(HOST_BUILD_DIR)/gdb/gdb $(TOOLCHAIN_DIR)/bin/$(TARGET_CROSS)gdb\n\tln -fs $(TARGET_CROSS)gdb $(TOOLCHAIN_DIR)/bin/$(GNU_TARGET_NAME)-gdb\n\tstrip $(TOOLCHAIN_DIR)/bin/$(TARGET_CROSS)gdb\n\tmkdir -p $(TOOLCHAIN_DIR)/share/gdb\n\t-cp -R $(HOST_BUILD_DIR)/gdb/data-directory/python $(TOOLCHAIN_DIR)/share/gdb/\n\tcp -R $(HOST_BUILD_DIR)/gdb/data-directory/syscalls $(TOOLCHAIN_DIR)/share/gdb/\n\tcp -R $(HOST_BUILD_DIR)/gdb/data-directory/system-gdbinit $(TOOLCHAIN_DIR)/share/gdb/\nendef\n\ndefine Host/Clean\n\trm -rf \\\n\t\t$(HOST_BUILD_DIR) \\\n\t\t$(TOOLCHAIN_DIR)/bin/$(TARGET_CROSS)gdb \\\n\t\t$(TOOLCHAIN_DIR)/bin/$(GNU_TARGET_NAME)-gdb\nendef\n\n$(eval $(call HostBuild))\n"
  },
  {
    "path": "toolchain/gdb/patches/120-fix-compile-flag-mismatch.patch",
    "content": "--- a/gdbserver/configure\n+++ b/gdbserver/configure\n@@ -2661,7 +2661,7 @@ $as_echo \"$as_me: error: \\`$ac_var' was\n       ac_cache_corrupted=: ;;\n     ,);;\n     *)\n-      if test \"x$ac_old_val\" != \"x$ac_new_val\"; then\n+      if test \"`echo x$ac_old_val`\" != \"`echo x$ac_new_val`\"; then\n \t# differences in whitespace do not lead to failure.\n \tac_old_val_w=`echo x $ac_old_val`\n \tac_new_val_w=`echo x $ac_new_val`\n"
  },
  {
    "path": "toolchain/glibc/Makefile",
    "content": "PATH_PREFIX := .\nVARIANT:=final\nHOST_BUILD_PARALLEL:=1\n\ninclude ./common.mk\n\ndefine Host/Compile\n\t+$(MAKE) -C $(CUR_BUILD_DIR) \\\n\t\tPARALLELMFLAGS=\"$(HOST_JOBS)\" \\\n\t\tBUILD_CFLAGS=\"$(HOST_CFLAGS)\" \\\n\t\tdefault-rpath=\"/lib:/usr/lib\" \\\n\t\tall\nendef\n\ndefine Host/Install\n\t$(call Host/SetToolchainInfo)\n\t$(MAKE) -C $(CUR_BUILD_DIR) \\\n\t\tBUILD_CFLAGS=\"$(HOST_CFLAGS)\" \\\n\t\tinstall_root=\"$(TOOLCHAIN_DIR)\" \\\n\t\tinstall\n\t( cd $(TOOLCHAIN_DIR) ; \\\n\t\tfor d in lib usr/lib ; do \\\n\t\t  for f in libc.so libpthread.so libgcc_s.so ; do \\\n\t\t    if [ -f $$$$d/$$$$f -a ! -L $$$$d/$$$$f ] ; then \\\n\t\t      $(SED) 's,/usr/lib/,,g;s,/lib/,,g' $$$$d/$$$$f ; \\\n\t\t    fi \\\n\t\t  done \\\n\t\tdone \\\n\t)\nendef\n\n$(eval $(call HostBuild))\n"
  },
  {
    "path": "toolchain/glibc/common.mk",
    "content": "#\n# Copyright (C) 2006-2020 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=glibc\nPKG_VERSION:=2.34\nPKG_RELEASE:=1\n\nPKG_SOURCE_PROTO:=git\nPKG_SOURCE_SUBDIR:=$(PKG_NAME)-$(PKG_VERSION)\nPKG_SOURCE_VERSION:=b87b697f15d6bf7e576a2eeadc1f740172f9d013\nPKG_MIRROR_HASH:=c65c9600292bfb73118793ff268aac7561e6c3c90f6c152a8b334fd6eddc0838\nPKG_SOURCE_URL:=https://sourceware.org/git/glibc.git\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION)-$(PKG_SOURCE_VERSION).tar.xz\n\nHOST_BUILD_DIR:=$(BUILD_DIR_TOOLCHAIN)/$(PKG_SOURCE_SUBDIR)\nCUR_BUILD_DIR:=$(HOST_BUILD_DIR)-$(VARIANT)\nPATCH_DIR:=$(PATH_PREFIX)/patches\n\ninclude $(INCLUDE_DIR)/toolchain-build.mk\n\nHOST_STAMP_PREPARED:=$(HOST_BUILD_DIR)/.prepared\nHOST_STAMP_CONFIGURED:=$(CUR_BUILD_DIR)/.configured\nHOST_STAMP_BUILT:=$(CUR_BUILD_DIR)/.built\nHOST_STAMP_INSTALLED:=$(TOOLCHAIN_DIR)/stamp/.glibc_$(VARIANT)_installed\n\nifeq ($(ARCH),mips64)\n  ifdef CONFIG_MIPS64_ABI_N64\n    TARGET_CFLAGS += -mabi=64\n  endif\n  ifdef CONFIG_MIPS64_ABI_N32\n    TARGET_CFLAGS += -mabi=n32\n  endif\n  ifdef CONFIG_MIPS64_ABI_O32\n    TARGET_CFLAGS += -mabi=32\n  endif\nendif\n\n# -Os miscompiles w. 2.24 gcc5/gcc6\n# only -O2 tested by upstream changeset\n# \"Optimize i386 syscall inlining for GCC 5\"\nGLIBC_CONFIGURE:= \\\n\tunset LD_LIBRARY_PATH; \\\n\tBUILD_CC=\"$(HOSTCC)\" \\\n\t$(TARGET_CONFIGURE_OPTS) \\\n\tCFLAGS=\"-O2 $(filter-out -Os,$(call qstrip,$(TARGET_CFLAGS)))\" \\\n\tlibc_cv_slibdir=\"/lib\" \\\n\tuse_ldconfig=no \\\n\t$(HOST_BUILD_DIR)/$(GLIBC_PATH)configure \\\n\t\t--prefix= \\\n\t\t--build=$(GNU_HOST_NAME) \\\n\t\t--host=$(REAL_GNU_TARGET_NAME) \\\n\t\t--with-headers=$(TOOLCHAIN_DIR)/include \\\n\t\t--disable-profile \\\n\t\t--disable-werror \\\n\t\t--without-gd \\\n\t\t--without-cvs \\\n\t\t--enable-add-ons \\\n\t\t--$(if $(CONFIG_SOFT_FLOAT),without,with)-fp \\\n\t\t  $(if $(CONFIG_PKG_CC_STACKPROTECTOR_REGULAR),--enable-stack-protector=yes) \\\n\t\t  $(if $(CONFIG_PKG_CC_STACKPROTECTOR_STRONG),--enable-stack-protector=strong) \\\n\t\t  $(if $(CONFIG_PKG_RELRO_FULL),--enable-bind-now) \\\n\t\t--enable-kernel=5.4.0\n\nexport libc_cv_ssp=no\nexport libc_cv_ssp_strong=no\nexport ac_cv_header_cpuid_h=yes\nexport HOST_CFLAGS := $(HOST_CFLAGS) -idirafter $(CURDIR)/$(PATH_PREFIX)/include\n\ndefine Host/SetToolchainInfo\n\t$(SED) 's,^\\(LIBC_TYPE\\)=.*,\\1=$(PKG_NAME),' $(TOOLCHAIN_DIR)/info.mk\n\t$(SED) 's,^\\(LIBC_URL\\)=.*,\\1=http://www.gnu.org/software/libc/,' $(TOOLCHAIN_DIR)/info.mk\n\t$(SED) 's,^\\(LIBC_VERSION\\)=.*,\\1=$(PKG_VERSION),' $(TOOLCHAIN_DIR)/info.mk\n\t$(SED) 's,^\\(LIBC_SO_VERSION\\)=.*,\\1=$(PKG_VERSION),' $(TOOLCHAIN_DIR)/info.mk\nendef\n\ndefine Host/Configure\n\t[ -f $(HOST_BUILD_DIR)/.autoconf ] || { \\\n\t\tcd $(HOST_BUILD_DIR)/; \\\n\t\tautoconf --force && \\\n\t\ttouch $(HOST_BUILD_DIR)/.autoconf; \\\n\t}\n\tmkdir -p $(CUR_BUILD_DIR)\n\t( cd $(CUR_BUILD_DIR); rm -f config.cache; \\\n\t\t$(GLIBC_CONFIGURE) \\\n\t);\nendef\n\ndefine Host/Prepare\n\t$(call Host/Prepare/Default)\n\tln -snf $(PKG_SOURCE_SUBDIR) $(BUILD_DIR_TOOLCHAIN)/$(PKG_NAME)\nendef\n\ndefine Host/Clean\n\trm -rf $(CUR_BUILD_DIR)* \\\n\t\t$(BUILD_DIR_TOOLCHAIN)/$(LIBC)-dev \\\n\t\t$(BUILD_DIR_TOOLCHAIN)/$(PKG_NAME)\nendef\n"
  },
  {
    "path": "toolchain/glibc/headers/Makefile",
    "content": "PATH_PREFIX:=..\nVARIANT:=headers\n\ninclude ../common.mk\n\ndefine Host/Compile\n\nendef\n\ndefine Host/Install\n\t$(call Host/SetToolchainInfo)\n\tmkdir -p $(BUILD_DIR_TOOLCHAIN)/$(LIBC)-dev/{include,lib}\n\t$(MAKE) -C $(CUR_BUILD_DIR) \\\n\t\tBUILD_CFLAGS=\"$(HOST_CFLAGS)\" \\\n\t\tinstall_root=\"$(BUILD_DIR_TOOLCHAIN)/$(LIBC)-dev\" \\\n\t\tinstall-bootstrap-headers=yes \\\n\t\tinstall-headers\n\t$(CP) $(BUILD_DIR_TOOLCHAIN)/linux-dev/* $(BUILD_DIR_TOOLCHAIN)/$(LIBC)-dev/\n\t$(MAKE) -C $(CUR_BUILD_DIR) \\\n\t\tcsu/subdir_lib\n\t( cd $(CUR_BUILD_DIR); \\\n\t\t$(CP) csu/crt1.o csu/crti.o csu/crtn.o $(BUILD_DIR_TOOLCHAIN)/$(LIBC)-dev/lib/ \\\n\t)\n\t$(TARGET_CC) -nostdlib -nostartfiles -shared -x c /dev/null \\\n\t\t-o $(BUILD_DIR_TOOLCHAIN)/$(LIBC)-dev/lib/libc.so\nendef\n\n$(eval $(call HostBuild))\n"
  },
  {
    "path": "toolchain/glibc/include/libintl.h",
    "content": "#ifndef __FAKE_LIBINTL_H\n#define __FAKE_LIBINTL_H\n\n#define _(X) (X)\n\n#endif\n"
  },
  {
    "path": "toolchain/glibc/patches/050-Revert-Disallow-use-of-DES-encryption-functions-in-n.patch",
    "content": "From 08f5e0df46ce1ad617bcde1fd5542545397630b9 Mon Sep 17 00:00:00 2001\nFrom: Hans Dedecker <dedeckeh@gmail.com>\nDate: Sat, 24 Oct 2020 21:13:30 +0200\nSubject: Revert \"Disallow use of DES encryption functions in new programs.\"\n\nThis reverts commit b10a0accee709a5efff2fadf0b0bbb79ff0ad759.\n\nppp still uses the encrypt functions from the libc while musl libc also\nprovides them.\n---\n conform/data/stdlib.h-data |   3 +\n conform/data/unistd.h-data |   6 ++\n crypt/cert.c               |  26 -----\n crypt/crypt-entry.c        |  15 ++-\n crypt/crypt.h              |  16 +++\n crypt/crypt_util.c         |   9 --\n manual/conf.texi           |   2 -\n manual/crypt.texi          | 204 +++++++++++++++++++++++++++++++++++++\n manual/string.texi         |  82 +++++++--------\n posix/unistd.h             |  17 +++-\n stdlib/stdlib.h            |   6 ++\n sunrpc/des_crypt.c         |   7 +-\n sunrpc/des_soft.c          |   2 +-\n 13 files changed, 305 insertions(+), 90 deletions(-)\n\n--- a/conform/data/stdlib.h-data\n+++ b/conform/data/stdlib.h-data\n@@ -149,6 +149,9 @@ function {unsigned short int*} seed48 (u\n #if !defined ISO && !defined ISO99 && !defined ISO11 && !defined POSIX && !defined XPG4 && !defined XPG42 && !defined UNIX98\n function int setenv (const char*, const char*, int)\n #endif\n+#if !defined ISO && !defined ISO99 && !defined ISO11 && !defined POSIX && !defined POSIX2008\n+function void setkey (const char*)\n+#endif\n #if !defined ISO && !defined ISO99 && !defined ISO11 && !defined XPG4 && !defined POSIX && !defined POSIX2008\n function {char*} setstate (char*)\n #endif\n--- a/conform/data/unistd.h-data\n+++ b/conform/data/unistd.h-data\n@@ -437,6 +437,9 @@ function int chroot (const char*)\n function int chown (const char*, uid_t, gid_t)\n function int close (int)\n function size_t confstr (int, char*, size_t)\n+#if !defined POSIX && !defined POSIX2008\n+function {char*} crypt (const char*, const char*)\n+#endif\n #if defined XPG4 || defined XPG42 || defined UNIX98\n function {char*} ctermid (char*)\n function {char*} cuserid (char*)\n@@ -446,6 +449,9 @@ allow cuserid\n #endif\n function int dup (int)\n function int dup2 (int, int)\n+#if !defined POSIX && !defined POSIX2008\n+function void encrypt (char[64], int)\n+#endif\n function int execl (const char*, const char*, ...)\n function int execle (const char*, const char*, ...)\n function int execlp (const char*, const char*, ...)\n--- a/crypt/cert.c\n+++ b/crypt/cert.c\n@@ -10,22 +10,6 @@\n #include <stdlib.h>\n #include \"crypt.h\"\n \n-/* This file tests the deprecated setkey/encrypt interface.  */\n-#include <shlib-compat.h>\n-#if TEST_COMPAT (libcrypt, GLIBC_2_0, GLIBC_2_28)\n-\n-#define libcrypt_version_reference(symbol, version) \\\n-  _libcrypt_version_reference (symbol, VERSION_libcrypt_##version)\n-#define _libcrypt_version_reference(symbol, version) \\\n-  __libcrypt_version_reference (symbol, version)\n-#define __libcrypt_version_reference(symbol, version) \\\n-  __asm__ (\".symver \" #symbol \", \" #symbol \"@\" #version)\n-\n-extern void setkey (const char *);\n-extern void encrypt (const char *, int);\n-libcrypt_version_reference (setkey, GLIBC_2_0);\n-libcrypt_version_reference (encrypt, GLIBC_2_0);\n-\n int totfails = 0;\n \n int main (int argc, char *argv[]);\n@@ -120,13 +104,3 @@ put8 (char *cp)\n \t  printf(\"%02x\", t);\n \t}\n }\n-\n-#else /* encrypt and setkey are not available.  */\n-\n-int\n-main (void)\n-{\n-  return 77; /* UNSUPPORTED */\n-}\n-\n-#endif\n--- a/crypt/crypt-entry.c\n+++ b/crypt/crypt-entry.c\n@@ -35,7 +35,6 @@\n #endif\n \n #include \"crypt-private.h\"\n-#include <shlib-compat.h>\n \n /* Prototypes for local functions.  */\n #ifndef __GNU_LIBRARY__\n@@ -177,7 +176,17 @@ crypt (const char *key, const char *salt\n   return __crypt_r (key, salt, &_ufc_foobar);\n }\n \n-#if SHLIB_COMPAT (libcrypt, GLIBC_2_0, GLIBC_2_28)\n+\n+/*\n+ * To make fcrypt users happy.\n+ * They don't need to call init_des.\n+ */\n+#ifdef _LIBC\n weak_alias (crypt, fcrypt)\n-compat_symbol (libcrypt, fcrypt, fcrypt, GLIBC_2_0);\n+#else\n+char *\n+__fcrypt (const char *key, const char *salt)\n+{\n+  return crypt (key, salt);\n+}\n #endif\n--- a/crypt/crypt.h\n+++ b/crypt/crypt.h\n@@ -36,6 +36,14 @@ __BEGIN_DECLS\n extern char *crypt (const char *__phrase, const char *__salt)\n      __THROW __nonnull ((1, 2));\n \n+/* Setup DES tables according KEY.  */\n+extern void setkey (const char *__key) __THROW __nonnull ((1));\n+\n+/* Encrypt data in BLOCK in place if EDFLAG is zero; otherwise decrypt\n+   block in place.  */\n+extern void encrypt (char *__glibc_block, int __edflag)\n+     __THROW __nonnull ((1));\n+\n #ifdef __USE_GNU\n \n /* This structure provides scratch and output buffers for 'crypt_r'.\n@@ -63,6 +71,14 @@ struct crypt_data\n extern char *crypt_r (const char *__phrase, const char *__salt,\n \t\t      struct crypt_data * __restrict __data)\n      __THROW __nonnull ((1, 2, 3));\n+\n+extern void setkey_r (const char *__key,\n+\t\t      struct crypt_data * __restrict __data)\n+     __THROW __nonnull ((1, 2));\n+\n+extern void encrypt_r (char *__glibc_block, int __edflag,\n+\t\t       struct crypt_data * __restrict __data)\n+     __THROW __nonnull ((1, 3));\n #endif\n \n __END_DECLS\n--- a/crypt/crypt_util.c\n+++ b/crypt/crypt_util.c\n@@ -34,7 +34,6 @@\n #endif\n \n #include \"crypt-private.h\"\n-#include <shlib-compat.h>\n \n /* Prototypes for local functions.  */\n #ifndef __GNU_LIBRARY__\n@@ -151,7 +150,6 @@ static const int sbox[8][4][16]= {\n \t}\n };\n \n-#if SHLIB_COMPAT (libcrypt, GLIBC_2_0, GLIBC_2_28)\n /*\n  * This is the initial\n  * permutation matrix\n@@ -162,7 +160,6 @@ static const int initial_perm[64] = {\n   57, 49, 41, 33, 25, 17,  9,  1, 59, 51, 43, 35, 27, 19, 11, 3,\n   61, 53, 45, 37, 29, 21, 13,  5, 63, 55, 47, 39, 31, 23, 15, 7\n };\n-#endif\n \n /*\n  * This is the final\n@@ -788,7 +785,6 @@ _ufc_output_conversion_r (ufc_long v1, u\n   __data->crypt_3_buf[13] = 0;\n }\n \n-#if SHLIB_COMPAT (libcrypt, GLIBC_2_0, GLIBC_2_28)\n \n /*\n  * UNIX encrypt function. Takes a bitvector\n@@ -889,14 +885,12 @@ __encrypt_r (char *__block, int __edflag\n   }\n }\n weak_alias (__encrypt_r, encrypt_r)\n-compat_symbol (libcrypt, encrypt_r, encrypt_r, GLIBC_2_0);\n \n void\n encrypt (char *__block, int __edflag)\n {\n   __encrypt_r(__block, __edflag, &_ufc_foobar);\n }\n-compat_symbol (libcrypt, encrypt, encrypt, GLIBC_2_0);\n \n \n /*\n@@ -921,15 +915,12 @@ __setkey_r (const char *__key, struct cr\n   _ufc_mk_keytab_r((char *) ktab, __data);\n }\n weak_alias (__setkey_r, setkey_r)\n-compat_symbol (libcrypt, setkey_r, setkey_r, GLIBC_2_0);\n \n void\n setkey (const char *__key)\n {\n   __setkey_r(__key, &_ufc_foobar);\n }\n-compat_symbol (libcrypt, setkey, setkey, GLIBC_2_0);\n-#endif /* SHLIB_COMPAT (libcrypt, GLIBC_2_0, GLIBC_2_28) */\n \n void\n __b64_from_24bit (char **cp, int *buflen,\n--- a/manual/conf.texi\n+++ b/manual/conf.texi\n@@ -780,8 +780,6 @@ Inquire about the parameter correspondin\n @item _SC_XOPEN_CRYPT\n @standards{X/Open, unistd.h}\n Inquire about the parameter corresponding to @code{_XOPEN_CRYPT}.\n-@Theglibc no longer implements the @code{_XOPEN_CRYPT} extensions,\n-so @samp{sysconf (_SC_XOPEN_CRYPT)} always returns @code{-1}.\n \n @item _SC_XOPEN_ENH_I18N\n @standards{X/Open, unistd.h}\n--- a/manual/crypt.texi\n+++ b/manual/crypt.texi\n@@ -16,8 +16,19 @@ subject to them, even if you do not use\n yourself.  The restrictions vary from place to place and are changed\n often, so we cannot give any more specific advice than this warning.\n \n+@vindex AUTH_DES\n+@cindex FIPS 140-2\n+It also provides support for Secure RPC, and some library functions that\n+can be used to perform normal DES encryption.  The @code{AUTH_DES}\n+authentication flavor in Secure RPC, as provided by @theglibc{},\n+uses DES and does not comply with FIPS 140-2 nor does any other use of DES\n+within @theglibc{}.  It is recommended that Secure RPC should not be used\n+for systems that need to comply with FIPS 140-2 since all flavors of\n+encrypted authentication use normal DES.\n+\n @menu\n * Passphrase Storage::          One-way hashing for passphrases.\n+* crypt::                       A one-way function for passwords.\n * Unpredictable Bytes::         Randomness for cryptographic purposes.\n @end menu\n \n@@ -190,6 +201,199 @@ unpredictable as possible; @pxref{Unpred\n @include genpass.c.texi\n @end smallexample\n \n+@node DES Encryption\n+@section DES Encryption\n+\n+@cindex FIPS 46-3\n+The Data Encryption Standard is described in the US Government Federal\n+Information Processing Standards (FIPS) 46-3 published by the National\n+Institute of Standards and Technology.  The DES has been very thoroughly\n+analyzed since it was developed in the late 1970s, and no new\n+significant flaws have been found.\n+\n+However, the DES uses only a 56-bit key (plus 8 parity bits), and a\n+machine has been built in 1998 which can search through all possible\n+keys in about 6 days, which cost about US$200000; faster searches would\n+be possible with more money.  This makes simple DES insecure for most\n+purposes, and NIST no longer permits new US government systems\n+to use simple DES.\n+\n+For serious encryption functionality, it is recommended that one of the\n+many free encryption libraries be used instead of these routines.\n+\n+The DES is a reversible operation which takes a 64-bit block and a\n+64-bit key, and produces another 64-bit block.  Usually the bits are\n+numbered so that the most-significant bit, the first bit, of each block\n+is numbered 1.\n+\n+Under that numbering, every 8th bit of the key (the 8th, 16th, and so\n+on) is not used by the encryption algorithm itself.  But the key must\n+have odd parity; that is, out of bits 1 through 8, and 9 through 16, and\n+so on, there must be an odd number of `1' bits, and this completely\n+specifies the unused bits.\n+\n+@deftypefun void setkey (const char *@var{key})\n+@standards{BSD, crypt.h}\n+@standards{SVID, crypt.h}\n+@safety{@prelim{}@mtunsafe{@mtasurace{:crypt}}@asunsafe{@asucorrupt{} @asulock{}}@acunsafe{@aculock{}}}\n+@c The static buffer stores the key, making it fundamentally\n+@c thread-unsafe.  The locking issues are only in the initialization\n+@c path; cancelling the initialization will leave the lock held, it\n+@c would otherwise repeat the initialization on the next call.\n+\n+The @code{setkey} function sets an internal data structure to be an\n+expanded form of @var{key}.  @var{key} is specified as an array of 64\n+bits each stored in a @code{char}, the first bit is @code{key[0]} and\n+the 64th bit is @code{key[63]}.  The @var{key} should have the correct\n+parity.\n+@end deftypefun\n+\n+@deftypefun void encrypt (char *@var{block}, int @var{edflag})\n+@standards{BSD, crypt.h}\n+@standards{SVID, crypt.h}\n+@safety{@prelim{}@mtunsafe{@mtasurace{:crypt}}@asunsafe{@asucorrupt{} @asulock{}}@acunsafe{@aculock{}}}\n+@c Same issues as setkey.\n+\n+The @code{encrypt} function encrypts @var{block} if\n+@var{edflag} is 0, otherwise it decrypts @var{block}, using a key\n+previously set by @code{setkey}.  The result is\n+placed in @var{block}.\n+\n+Like @code{setkey}, @var{block} is specified as an array of 64 bits each\n+stored in a @code{char}, but there are no parity bits in @var{block}.\n+@end deftypefun\n+\n+@deftypefun void setkey_r (const char *@var{key}, {struct crypt_data *} @var{data})\n+@deftypefunx void encrypt_r (char *@var{block}, int @var{edflag}, {struct crypt_data *} @var{data})\n+@standards{GNU, crypt.h}\n+@c setkey_r: @safety{@prelim{}@mtsafe{}@asunsafe{@asucorrupt{} @asulock{}}@acunsafe{@aculock{}}}\n+@safety{@prelim{}@mtsafe{}@asunsafe{@asucorrupt{} @asulock{}}@acunsafe{@aculock{}}}\n+\n+These are reentrant versions of @code{setkey} and @code{encrypt}.  The\n+only difference is the extra parameter, which stores the expanded\n+version of @var{key}.  Before calling @code{setkey_r} the first time,\n+@code{data->initialized} must be cleared to zero.\n+@end deftypefun\n+\n+The @code{setkey_r} and @code{encrypt_r} functions are GNU extensions.\n+@code{setkey}, @code{encrypt}, @code{setkey_r}, and @code{encrypt_r} are\n+defined in @file{crypt.h}.\n+\n+@deftypefun int ecb_crypt (char *@var{key}, char *@var{blocks}, unsigned int @var{len}, unsigned int @var{mode})\n+@standards{SUNRPC, rpc/des_crypt.h}\n+@safety{@prelim{}@mtsafe{}@assafe{}@acsafe{}}\n+\n+The function @code{ecb_crypt} encrypts or decrypts one or more blocks\n+using DES.  Each block is encrypted independently.\n+\n+The @var{blocks} and the @var{key} are stored packed in 8-bit bytes, so\n+that the first bit of the key is the most-significant bit of\n+@code{key[0]} and the 63rd bit of the key is stored as the\n+least-significant bit of @code{key[7]}.  The @var{key} should have the\n+correct parity.\n+\n+@var{len} is the number of bytes in @var{blocks}.  It should be a\n+multiple of 8 (so that there are a whole number of blocks to encrypt).\n+@var{len} is limited to a maximum of @code{DES_MAXDATA} bytes.\n+\n+The result of the encryption replaces the input in @var{blocks}.\n+\n+The @var{mode} parameter is the bitwise OR of two of the following:\n+\n+@vtable @code\n+@item DES_ENCRYPT\n+@standards{SUNRPC, rpc/des_crypt.h}\n+This constant, used in the @var{mode} parameter, specifies that\n+@var{blocks} is to be encrypted.\n+\n+@item DES_DECRYPT\n+@standards{SUNRPC, rpc/des_crypt.h}\n+This constant, used in the @var{mode} parameter, specifies that\n+@var{blocks} is to be decrypted.\n+\n+@item DES_HW\n+@standards{SUNRPC, rpc/des_crypt.h}\n+This constant, used in the @var{mode} parameter, asks to use a hardware\n+device.  If no hardware device is available, encryption happens anyway,\n+but in software.\n+\n+@item DES_SW\n+@standards{SUNRPC, rpc/des_crypt.h}\n+This constant, used in the @var{mode} parameter, specifies that no\n+hardware device is to be used.\n+@end vtable\n+\n+The result of the function will be one of these values:\n+\n+@vtable @code\n+@item DESERR_NONE\n+@standards{SUNRPC, rpc/des_crypt.h}\n+The encryption succeeded.\n+\n+@item DESERR_NOHWDEVICE\n+@standards{SUNRPC, rpc/des_crypt.h}\n+The encryption succeeded, but there was no hardware device available.\n+\n+@item DESERR_HWERROR\n+@standards{SUNRPC, rpc/des_crypt.h}\n+The encryption failed because of a hardware problem.\n+\n+@item DESERR_BADPARAM\n+@standards{SUNRPC, rpc/des_crypt.h}\n+The encryption failed because of a bad parameter, for instance @var{len}\n+is not a multiple of 8 or @var{len} is larger than @code{DES_MAXDATA}.\n+@end vtable\n+@end deftypefun\n+\n+@deftypefun int DES_FAILED (int @var{err})\n+@standards{SUNRPC, rpc/des_crypt.h}\n+@safety{@prelim{}@mtsafe{}@assafe{}@acsafe{}}\n+This macro returns 1 if @var{err} is a `success' result code from\n+@code{ecb_crypt} or @code{cbc_crypt}, and 0 otherwise.\n+@end deftypefun\n+\n+@deftypefun int cbc_crypt (char *@var{key}, char *@var{blocks}, unsigned int @var{len}, unsigned int @var{mode}, char *@var{ivec})\n+@standards{SUNRPC, rpc/des_crypt.h}\n+@safety{@prelim{}@mtsafe{}@assafe{}@acsafe{}}\n+\n+The function @code{cbc_crypt} encrypts or decrypts one or more blocks\n+using DES in Cipher Block Chaining mode.\n+\n+For encryption in CBC mode, each block is exclusive-ored with @var{ivec}\n+before being encrypted, then @var{ivec} is replaced with the result of\n+the encryption, then the next block is processed.  Decryption is the\n+reverse of this process.\n+\n+This has the advantage that blocks which are the same before being\n+encrypted are very unlikely to be the same after being encrypted, making\n+it much harder to detect patterns in the data.\n+\n+Usually, @var{ivec} is set to 8 random bytes before encryption starts.\n+Then the 8 random bytes are transmitted along with the encrypted data\n+(without themselves being encrypted), and passed back in as @var{ivec}\n+for decryption.  Another possibility is to set @var{ivec} to 8 zeroes\n+initially, and have the first block encrypted consist of 8 random\n+bytes.\n+\n+Otherwise, all the parameters are similar to those for @code{ecb_crypt}.\n+@end deftypefun\n+\n+@deftypefun void des_setparity (char *@var{key})\n+@standards{SUNRPC, rpc/des_crypt.h}\n+@safety{@prelim{}@mtsafe{}@assafe{}@acsafe{}}\n+\n+The function @code{des_setparity} changes the 64-bit @var{key}, stored\n+packed in 8-bit bytes, to have odd parity by altering the low bits of\n+each byte.\n+@end deftypefun\n+\n+The @code{ecb_crypt}, @code{cbc_crypt}, and @code{des_setparity}\n+functions and their accompanying macros are all defined in the header\n+@file{rpc/des_crypt.h}.\n+\n+@node Unpredictable Bytes\n+@section Generating Unpredictable Bytes\n+\n The next program demonstrates how to verify a passphrase.  It checks a\n hash hardcoded into the program, because looking up real users' hashed\n passphrases may require special privileges (@pxref{User Database}).\n--- a/manual/string.texi\n+++ b/manual/string.texi\n@@ -36,8 +36,8 @@ too.\n \t\t\t\t for delimiters.\n * Erasing Sensitive Data::      Clearing memory which contains sensitive\n                                  data, after it's no longer needed.\n-* Shuffling Bytes::             Or how to flash-cook a string.\n-* Obfuscating Data::            Reversibly obscuring data from casual view.\n+* strfry::                      Function for flash-cooking a string.\n+* Trivial Encryption::          Obscuring data.\n * Encode Binary Data::          Encoding and Decoding of Binary Data.\n * Argz and Envz Vectors::       Null-separated string vectors.\n @end menu\n@@ -2423,73 +2423,73 @@ functionality under a different name, su\n systems it may be in @file{strings.h} instead.\n @end deftypefun\n \n-\n-@node Shuffling Bytes\n-@section Shuffling Bytes\n+@node strfry\n+@section strfry\n \n The function below addresses the perennial programming quandary: ``How do\n I take good data in string form and painlessly turn it into garbage?''\n-This is not a difficult thing to code for oneself, but the authors of\n-@theglibc{} wish to make it as convenient as possible.\n+This is actually a fairly simple task for C programmers who do not use\n+@theglibc{} string functions, but for programs based on @theglibc{},\n+the @code{strfry} function is the preferred method for\n+destroying string data.\n \n-To @emph{erase} data, use @code{explicit_bzero} (@pxref{Erasing\n-Sensitive Data}); to obfuscate it reversibly, use @code{memfrob}\n-(@pxref{Obfuscating Data}).\n+The prototype for this function is in @file{string.h}.\n \n @deftypefun {char *} strfry (char *@var{string})\n @standards{GNU, string.h}\n @safety{@prelim{}@mtsafe{}@assafe{}@acsafe{}}\n @c Calls initstate_r, time, getpid, strlen, and random_r.\n \n-@code{strfry} performs an in-place shuffle on @var{string}.  Each\n-character is swapped to a position selected at random, within the\n-portion of the string starting with the character's original position.\n-(This is the Fisher-Yates algorithm for unbiased shuffling.)\n-\n-Calling @code{strfry} will not disturb any of the random number\n-generators that have global state (@pxref{Pseudo-Random Numbers}).\n+@code{strfry} creates a pseudorandom anagram of a string, replacing the\n+input with the anagram in place.  For each position in the string,\n+@code{strfry} swaps it with a position in the string selected at random\n+(from a uniform distribution).  The two positions may be the same.\n \n The return value of @code{strfry} is always @var{string}.\n \n @strong{Portability Note:}  This function is unique to @theglibc{}.\n-It is declared in @file{string.h}.\n+\n @end deftypefun\n \n \n-@node Obfuscating Data\n-@section Obfuscating Data\n+@node Trivial Encryption\n+@section Trivial Encryption\n+@cindex encryption\n+\n+\n+The @code{memfrob} function converts an array of data to something\n+unrecognizable and back again.  It is not encryption in its usual sense\n+since it is easy for someone to convert the encrypted data back to clear\n+text.  The transformation is analogous to Usenet's ``Rot13'' encryption\n+method for obscuring offensive jokes from sensitive eyes and such.\n+Unlike Rot13, @code{memfrob} works on arbitrary binary data, not just\n+text.\n @cindex Rot13\n \n-The @code{memfrob} function reversibly obfuscates an array of binary\n-data.  This is not true encryption; the obfuscated data still bears a\n-clear relationship to the original, and no secret key is required to\n-undo the obfuscation.  It is analogous to the ``Rot13'' cipher used on\n-Usenet for obscuring offensive jokes, spoilers for works of fiction,\n-and so on, but it can be applied to arbitrary binary data.\n-\n-Programs that need true encryption---a transformation that completely\n-obscures the original and cannot be reversed without knowledge of a\n-secret key---should use a dedicated cryptography library, such as\n-@uref{https://www.gnu.org/software/libgcrypt/,,libgcrypt}.\n-\n-Programs that need to @emph{destroy} data should use\n-@code{explicit_bzero} (@pxref{Erasing Sensitive Data}), or possibly\n-@code{strfry} (@pxref{Shuffling Bytes}).\n+For true encryption, @xref{Cryptographic Functions}.\n+\n+This function is declared in @file{string.h}.\n+@pindex string.h\n \n @deftypefun {void *} memfrob (void *@var{mem}, size_t @var{length})\n @standards{GNU, string.h}\n @safety{@prelim{}@mtsafe{}@assafe{}@acsafe{}}\n \n-The function @code{memfrob} obfuscates @var{length} bytes of data\n-beginning at @var{mem}, in place.  Each byte is bitwise xor-ed with\n-the binary pattern 00101010 (hexadecimal 0x2A).  The return value is\n-always @var{mem}.\n-\n-@code{memfrob} a second time on the same data returns it to\n-its original state.\n+@code{memfrob} transforms (frobnicates) each byte of the data structure\n+at @var{mem}, which is @var{length} bytes long, by bitwise exclusive\n+oring it with binary 00101010.  It does the transformation in place and\n+its return value is always @var{mem}.\n+\n+Note that @code{memfrob} a second time on the same data structure\n+returns it to its original state.\n+\n+This is a good function for hiding information from someone who doesn't\n+want to see it or doesn't want to see it very much.  To really prevent\n+people from retrieving the information, use stronger encryption such as\n+that described in @xref{Cryptographic Functions}.\n \n @strong{Portability Note:}  This function is unique to @theglibc{}.\n-It is declared in @file{string.h}.\n+\n @end deftypefun\n \n @node Encode Binary Data\n--- a/posix/unistd.h\n+++ b/posix/unistd.h\n@@ -107,6 +107,9 @@ __BEGIN_DECLS\n /* The X/Open Unix extensions are available.  */\n #define _XOPEN_UNIX\t1\n \n+/* Encryption is present.  */\n+#define\t_XOPEN_CRYPT\t1\n+\n /* The enhanced internationalization capabilities according to XPG4.2\n    are present.  */\n #define\t_XOPEN_ENH_I18N\t1\n@@ -1150,17 +1153,25 @@ ssize_t copy_file_range (int __infd, __o\n extern int fdatasync (int __fildes);\n #endif /* Use POSIX199309 */\n \n-#ifdef __USE_MISC\n+/* XPG4.2 specifies that prototypes for the encryption functions must\n+   be defined here.  */\n+#ifdef\t__USE_XOPEN\n /* One-way hash PHRASE, returning a string suitable for storage in the\n    user database.  SALT selects the one-way function to use, and\n    ensures that no two users' hashes are the same, even if they use\n    the same passphrase.  The return value points to static storage\n    which will be overwritten by the next call to crypt.  */\n+\n+/* Encrypt at most 8 characters from KEY using salt to perturb DES.  */\n extern char *crypt (const char *__key, const char *__salt)\n      __THROW __nonnull ((1, 2));\n-#endif\n \n-#ifdef\t__USE_XOPEN\n+/* Encrypt data in BLOCK in place if EDFLAG is zero; otherwise decrypt\n+   block in place.  */\n+extern void encrypt (char *__glibc_block, int __edflag)\n+     __THROW __nonnull ((1));\n+\n+\n /* Swab pairs bytes in the first N bytes of the area pointed to by\n    FROM and copy the result to TO.  The value of TO must not be in the\n    range [FROM - N + 1, FROM - 1].  If N is odd the first byte in FROM\n--- a/stdlib/stdlib.h\n+++ b/stdlib/stdlib.h\n@@ -969,6 +969,12 @@ extern int getsubopt (char **__restrict\n #endif\n \n \n+#ifdef __USE_XOPEN\n+/* Setup DES tables according KEY.  */\n+extern void setkey (const char *__key) __THROW __nonnull ((1));\n+#endif\n+\n+\n /* X/Open pseudo terminal handling.  */\n \n #ifdef __USE_XOPEN2KXSI\n--- a/sunrpc/des_crypt.c\n+++ b/sunrpc/des_crypt.c\n@@ -86,9 +86,6 @@ common_crypt (char *key, char *buf, regi\n   return desdev == DES_SW ? DESERR_NONE : DESERR_NOHWDEVICE;\n }\n \n-/* Note: these cannot be excluded from the build yet, because they are\n-   still used internally.  */\n-\n /*\n  * CBC mode encryption\n  */\n@@ -105,7 +102,7 @@ cbc_crypt (char *key, char *buf, unsigne\n   COPY8 (dp.des_ivec, ivec);\n   return err;\n }\n-hidden_nolink (cbc_crypt, libc, GLIBC_2_1)\n+libc_hidden_nolink_sunrpc (cbc_crypt, GLIBC_2_1)\n \n /*\n  * ECB mode encryption\n@@ -118,4 +115,4 @@ ecb_crypt (char *key, char *buf, unsigne\n   dp.des_mode = ECB;\n   return common_crypt (key, buf, len, mode, &dp);\n }\n-hidden_nolink (ecb_crypt, libc, GLIBC_2_1)\n+libc_hidden_nolink_sunrpc (ecb_crypt, GLIBC_2_1)\n--- a/sunrpc/des_soft.c\n+++ b/sunrpc/des_soft.c\n@@ -71,4 +71,4 @@ des_setparity (char *p)\n       p++;\n     }\n }\n-hidden_nolink (des_setparity, libc, GLIBC_2_1)\n+libc_hidden_nolink_sunrpc (des_setparity, GLIBC_2_1)\n"
  },
  {
    "path": "toolchain/glibc/patches/100-fix_cross_rpcgen.patch",
    "content": "--- a/sunrpc/rpc/types.h\n+++ b/sunrpc/rpc/types.h\n@@ -75,18 +75,23 @@ typedef unsigned long rpcport_t;\n #endif\n \n #ifndef __u_char_defined\n-typedef __u_char u_char;\n-typedef __u_short u_short;\n-typedef __u_int u_int;\n-typedef __u_long u_long;\n-typedef __quad_t quad_t;\n-typedef __u_quad_t u_quad_t;\n-typedef __fsid_t fsid_t;\n+typedef unsigned char u_char;\n+typedef unsigned short u_short;\n+typedef unsigned int u_int;\n+typedef unsigned long u_long;\n+#if __WORDSIZE == 64\n+typedef long int quad_t;\n+typedef unsigned long int u_quad_t;\n+#elif defined __GLIBC_HAVE_LONG_LONG\n+typedef long long int quad_t;\n+typedef unsigned long long int u_quad_t;\n+#endif\n+typedef u_quad_t fsid_t;\n # define __u_char_defined\n #endif\n-#ifndef __daddr_t_defined\n-typedef __daddr_t daddr_t;\n-typedef __caddr_t caddr_t;\n+#if !defined(__daddr_t_defined) && defined(linux)\n+typedef long int daddr_t;\n+typedef char *caddr_t;\n # define __daddr_t_defined\n #endif\n \n"
  },
  {
    "path": "toolchain/glibc/patches/200-add-dl-search-paths.patch",
    "content": "add /usr/lib to default search path for the dynamic linker\n\n--- a/Makeconfig\n+++ b/Makeconfig\n@@ -610,6 +610,9 @@ else\n default-rpath = $(libdir)\n endif\n \n+# Add /usr/lib to default search path for the dynamic linker\n+user-defined-trusted-dirs := /usr/lib\n+\n ifndef link-extra-libs\n link-extra-libs = $(LDLIBS-$(@F))\n link-extra-libs-static = $(link-extra-libs)\n"
  },
  {
    "path": "toolchain/info.mk",
    "content": "TARGET_CROSS=\nGCC_VERSION=unknown\nLIBC_TYPE=unknown\nLIBC_URL=unknown\nLIBC_VERSION=unknown\nLIBC_SO_VERSION=unknown\n"
  },
  {
    "path": "toolchain/kernel-headers/Makefile",
    "content": "# \n# Copyright (C) 2006-2009 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\ninclude $(TOPDIR)/rules.mk\n\nKERNEL_BUILD_DIR := $(BUILD_DIR_TOOLCHAIN)\nBUILD_DIR := $(KERNEL_BUILD_DIR)\n\noverride QUILT:=\noverride HOST_QUILT:=\n\ninclude $(INCLUDE_DIR)/kernel.mk\n\nPKG_NAME:=linux\nPKG_VERSION:=$(LINUX_VERSION)\nPKG_SOURCE:=$(LINUX_SOURCE)\nifneq ($(call qstrip,$(CONFIG_KERNEL_GIT_CLONE_URI)),)\n  PKG_SOURCE_PROTO:=git\n  PKG_SOURCE_URL:=$(call qstrip,$(CONFIG_KERNEL_GIT_CLONE_URI))\n  PKG_SOURCE_VERSION:=$(call qstrip,$(CONFIG_KERNEL_GIT_REF))\n  PKG_MIRROR_HASH:=$(call qstrip,$(CONFIG_KERNEL_GIT_MIRROR_HASH))\nifdef CHECK\n  include $(INCLUDE_DIR)/kernel-version.mk\n  PKG_VERSION:=$(LINUX_VERSION)\nelse\n  PKG_SOURCE:=$(LINUX_SOURCE)\nendif\nelse\n  PKG_SOURCE:=$(LINUX_SOURCE)\n  PKG_SOURCE_URL:=$(LINUX_SITE)\nendif\nHOST_BUILD_DIR:=$(KERNEL_BUILD_DIR)/linux-$(LINUX_VERSION)\nPKG_HASH:=$(LINUX_KERNEL_HASH)\nLINUX_DIR := $(HOST_BUILD_DIR)\nFILES_DIR := \nPATCH_DIR := ./patches$(if $(wildcard ./patches-$(LINUX_VERSION)),-$(LINUX_VERSION))\n\ninclude $(INCLUDE_DIR)/toolchain-build.mk\ninclude $(INCLUDE_DIR)/kernel-defaults.mk\n\nifeq ($(strip $(BOARD)),uml)\n  LINUX_KARCH:=$(subst x86_64,x86,$(subst i386,x86,$(ARCH)))\nendif\n\nHOST_EXTRACFLAGS=\n\nLINUX_HAS_HEADERS_INSTALL:=y\n\nHOST_KMAKE := $(MAKE) -C $(HOST_BUILD_DIR) \\\n\t$(KERNEL_MAKE_FLAGS) \\\n\tCC=\"$(KERNEL_CC)\" \\\n\tHOSTCFLAGS=\"$(HOST_CFLAGS)\"\n\ndefine Host/Configure/all\n\tmkdir -p $(BUILD_DIR_TOOLCHAIN)/linux-dev\n\t$(HOST_KMAKE) \\\n\t\tINSTALL_HDR_PATH=\"$(BUILD_DIR_TOOLCHAIN)/linux-dev/\" \\\n\t\theaders_install\nendef\n\n# XXX: the following is needed to build lzma-loader\nifneq ($(CONFIG_mips)$(CONFIG_mipsel),)\n  define Host/Configure/lzma\n\t$(CP) \\\n\t\t$(HOST_BUILD_DIR)/arch/mips/include/asm/asm.h \\\n\t\t$(HOST_BUILD_DIR)/arch/mips/include/asm/regdef.h \\\n\t\t$(HOST_BUILD_DIR)/arch/mips/include/asm/asm-eva.h \\\n\t\t$(BUILD_DIR_TOOLCHAIN)/linux-dev/include/asm/\n  endef\nendif\n\ndefine Host/Configure/post/mips\n\t$(call Host/Configure/lzma)\nendef\n\ndefine Host/Configure/post/mipsel\n\t$(call Host/Configure/lzma)\nendef\n\ndefine Host/Prepare\n\trm -rf $(BUILD_DIR_TOOLCHAIN)/linux-*\n\t$(call Kernel/Prepare/Default)\n\trm -f $(BUILD_DIR_TOOLCHAIN)/linux\n\tln -s linux-$(LINUX_VERSION) $(BUILD_DIR_TOOLCHAIN)/linux\n\t$(SED) 's/@expr length/@-expr length/' $(HOST_BUILD_DIR)/Makefile\nendef\n\ndefine Host/Configure\n\tenv\n\tyes '' | $(HOST_KMAKE) oldconfig\n\t$(call Host/Configure/all)\n\t$(call Host/Configure/post/$(ARCH))\nendef\n\ndefine Host/Compile\nendef\n\ndefine Host/Install\n\t$(CP) $(BUILD_DIR_TOOLCHAIN)/linux-dev/* $(TOOLCHAIN_DIR)/\nendef\n\ndefine Host/Clean\n\trm -rf \\\n\t\t$(HOST_BUILD_DIR) \\\n\t\t$(BUILD_DIR_TOOLCHAIN)/linux \\\n\t\t$(BUILD_DIR_TOOLCHAIN)/linux-dev\nendef\n\n$(eval $(call HostBuild))\n"
  },
  {
    "path": "toolchain/musl/Config.in",
    "content": "# Password crypt stubbing\n\nconfig MUSL_DISABLE_CRYPT_SIZE_HACK\n\tbool\n\tprompt \"Include crypt() support for SHA256, SHA512 and Blowfish ciphers\" if TOOLCHAINOPTS\n\tdepends on USE_MUSL && !EXTERNAL_TOOLCHAIN\n\tdefault y\n\thelp\n\t  Enable this option to re-include crypt() support for the SHA256, SHA512 and\n\t  Blowfish ciphers. Without this option, attempting to hash a string with a salt\n\t  requesting one of these ciphers will cause the crypt() function to call stub\n\t  implementations which will always fail with errno ENOSYS. Including the ciphers\n\t  will increase the library size by about 14KB after LZMA compression.\n"
  },
  {
    "path": "toolchain/musl/Makefile",
    "content": "PATH_PREFIX=.\n\ninclude ./common.mk\n\nHOST_STAMP_BUILT:=$(HOST_BUILD_DIR)/.built\nHOST_STAMP_INSTALLED:=$(TOOLCHAIN_DIR)/stamp/.musl_installed\n\nHOST_BUILD_PARALLEL:=1\n\nMUSL_MAKEOPTS = -C $(HOST_BUILD_DIR) \\\n\tDESTDIR=\"$(TOOLCHAIN_DIR)/\" \\\n\tLIBCC=\"$(subst libgcc.a,libgcc_initial.a,$(shell $(TARGET_CC) -print-libgcc-file-name))\"\n\ndefine Host/SetToolchainInfo\n\t$(SED) 's,^\\(LIBC_TYPE\\)=.*,\\1=$(PKG_NAME),' $(TOOLCHAIN_DIR)/info.mk\n\t$(SED) 's,^\\(LIBC_URL\\)=.*,\\1=http://www.musl-libc.org/,' $(TOOLCHAIN_DIR)/info.mk\n\t$(SED) 's,^\\(LIBC_VERSION\\)=.*,\\1=$(PKG_VERSION),' $(TOOLCHAIN_DIR)/info.mk\n\t$(SED) 's,^\\(LIBC_SO_VERSION\\)=.*,\\1=$(LIBC_SO_VERSION),' $(TOOLCHAIN_DIR)/info.mk\nendef\n\ndefine Host/Compile\n\t+$(MAKE) $(HOST_JOBS) $(MUSL_MAKEOPTS) all\nendef\n\ndefine Host/Install\n\t$(call Host/SetToolchainInfo)\n\t+$(MAKE) $(HOST_JOBS) $(MUSL_MAKEOPTS) DESTDIR=\"$(TOOLCHAIN_DIR)/\" install\n\t$(CP) ./include $(TOOLCHAIN_DIR)/\nendef\n\n$(eval $(call HostBuild))\n"
  },
  {
    "path": "toolchain/musl/common.mk",
    "content": "#\n# Copyright (C) 2012-2013 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\ninclude $(TOPDIR)/rules.mk\ninclude $(INCLUDE_DIR)/target.mk\n\nPKG_NAME:=musl\nPKG_VERSION:=1.2.3\nPKG_RELEASE:=1\n\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz\nPKG_SOURCE_URL:=https://musl.libc.org/releases/\nPKG_HASH:=7d5b0b6062521e4627e099e4c9dc8248d32a30285e959b7eecaa780cf8cfd4a4\n\nLIBC_SO_VERSION:=$(PKG_VERSION)\nPATCH_DIR:=$(PATH_PREFIX)/patches\n\nBUILD_DIR_HOST:=$(BUILD_DIR_TOOLCHAIN)\nHOST_BUILD_PREFIX:=$(TOOLCHAIN_DIR)\nHOST_BUILD_DIR:=$(BUILD_DIR_TOOLCHAIN)/$(PKG_NAME)-$(PKG_VERSION)\n\ninclude $(INCLUDE_DIR)/host-build.mk\ninclude $(INCLUDE_DIR)/hardening.mk\n\nTARGET_CFLAGS:= $(filter-out -O%,$(TARGET_CFLAGS))\nTARGET_CFLAGS+= $(if $(CONFIG_MUSL_DISABLE_CRYPT_SIZE_HACK),,-DCRYPT_SIZE_HACK)\n\nMUSL_CONFIGURE:= \\\n\t$(TARGET_CONFIGURE_OPTS) \\\n\tCFLAGS=\"$(TARGET_CFLAGS)\" \\\n\tCROSS_COMPILE=\"$(TARGET_CROSS)\" \\\n\t$(HOST_BUILD_DIR)/configure \\\n\t\t--prefix=/ \\\n\t\t--host=$(GNU_HOST_NAME) \\\n\t\t--target=$(REAL_GNU_TARGET_NAME) \\\n\t\t--disable-gcc-wrapper \\\n\t\t--enable-debug \\\n\t\t--enable-optimize\n\ndefine Host/Configure\n\tln -snf $(PKG_NAME)-$(PKG_VERSION) $(BUILD_DIR_TOOLCHAIN)/$(PKG_NAME)\n\t( cd $(HOST_BUILD_DIR); rm -f config.cache; \\\n\t\t$(MUSL_CONFIGURE) \\\n\t);\nendef\n\ndefine Host/Clean\n\trm -rf \\\n\t\t$(HOST_BUILD_DIR) \\\n\t\t$(BUILD_DIR_TOOLCHAIN)/$(PKG_NAME) \\\n\t\t$(BUILD_DIR_TOOLCHAIN)/$(LIBC)-dev\nendef\n"
  },
  {
    "path": "toolchain/musl/include/sys/queue.h",
    "content": "/*\n * Copyright (c) 1991, 1993\n *\tThe Regents of the University of California.  All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n *    notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n *    notice, this list of conditions and the following disclaimer in the\n *    documentation and/or other materials provided with the distribution.\n * 3. Neither the name of the University nor the names of its contributors\n *    may be used to endorse or promote products derived from this software\n *    without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n *\n *\t@(#)queue.h\t8.5 (Berkeley) 8/20/94\n */\n\n#ifndef\t_SYS_QUEUE_H_\n#define\t_SYS_QUEUE_H_\n\n/*\n * This file defines five types of data structures: singly-linked lists,\n * lists, simple queues, tail queues, and circular queues.\n *\n * A singly-linked list is headed by a single forward pointer. The\n * elements are singly linked for minimum space and pointer manipulation\n * overhead at the expense of O(n) removal for arbitrary elements. New\n * elements can be added to the list after an existing element or at the\n * head of the list.  Elements being removed from the head of the list\n * should use the explicit macro for this purpose for optimum\n * efficiency. A singly-linked list may only be traversed in the forward\n * direction.  Singly-linked lists are ideal for applications with large\n * datasets and few or no removals or for implementing a LIFO queue.\n *\n * A list is headed by a single forward pointer (or an array of forward\n * pointers for a hash table header). The elements are doubly linked\n * so that an arbitrary element can be removed without a need to\n * traverse the list. New elements can be added to the list before\n * or after an existing element or at the head of the list. A list\n * may only be traversed in the forward direction.\n *\n * A simple queue is headed by a pair of pointers, one the head of the\n * list and the other to the tail of the list. The elements are singly\n * linked to save space, so elements can only be removed from the\n * head of the list. New elements can be added to the list after\n * an existing element, at the head of the list, or at the end of the\n * list. A simple queue may only be traversed in the forward direction.\n *\n * A tail queue is headed by a pair of pointers, one to the head of the\n * list and the other to the tail of the list. The elements are doubly\n * linked so that an arbitrary element can be removed without a need to\n * traverse the list. New elements can be added to the list before or\n * after an existing element, at the head of the list, or at the end of\n * the list. A tail queue may be traversed in either direction.\n *\n * A circle queue is headed by a pair of pointers, one to the head of the\n * list and the other to the tail of the list. The elements are doubly\n * linked so that an arbitrary element can be removed without a need to\n * traverse the list. New elements can be added to the list before or after\n * an existing element, at the head of the list, or at the end of the list.\n * A circle queue may be traversed in either direction, but has a more\n * complex end of list detection.\n *\n * For details on the use of these macros, see the queue(3) manual page.\n */\n\n/*\n * List definitions.\n */\n#define\tLIST_HEAD(name, type)\t\t\t\t\t\t\\\nstruct name {\t\t\t\t\t\t\t\t\\\n\tstruct type *lh_first;\t/* first element */\t\t\t\\\n}\n\n#define\tLIST_HEAD_INITIALIZER(head)\t\t\t\t\t\\\n\t{ NULL }\n\n#define\tLIST_ENTRY(type)\t\t\t\t\t\t\\\nstruct {\t\t\t\t\t\t\t\t\\\n\tstruct type *le_next;\t/* next element */\t\t\t\\\n\tstruct type **le_prev;\t/* address of previous next element */\t\\\n}\n\n/*\n * List functions.\n */\n#define\tLIST_INIT(head) do {\t\t\t\t\t\t\\\n\t(head)->lh_first = NULL;\t\t\t\t\t\\\n} while (/*CONSTCOND*/0)\n\n#define\tLIST_INSERT_AFTER(listelm, elm, field) do {\t\t\t\\\n\tif (((elm)->field.le_next = (listelm)->field.le_next) != NULL)\t\\\n\t\t(listelm)->field.le_next->field.le_prev =\t\t\\\n\t\t    &(elm)->field.le_next;\t\t\t\t\\\n\t(listelm)->field.le_next = (elm);\t\t\t\t\\\n\t(elm)->field.le_prev = &(listelm)->field.le_next;\t\t\\\n} while (/*CONSTCOND*/0)\n\n#define\tLIST_INSERT_BEFORE(listelm, elm, field) do {\t\t\t\\\n\t(elm)->field.le_prev = (listelm)->field.le_prev;\t\t\\\n\t(elm)->field.le_next = (listelm);\t\t\t\t\\\n\t*(listelm)->field.le_prev = (elm);\t\t\t\t\\\n\t(listelm)->field.le_prev = &(elm)->field.le_next;\t\t\\\n} while (/*CONSTCOND*/0)\n\n#define\tLIST_INSERT_HEAD(head, elm, field) do {\t\t\t\t\\\n\tif (((elm)->field.le_next = (head)->lh_first) != NULL)\t\t\\\n\t\t(head)->lh_first->field.le_prev = &(elm)->field.le_next;\\\n\t(head)->lh_first = (elm);\t\t\t\t\t\\\n\t(elm)->field.le_prev = &(head)->lh_first;\t\t\t\\\n} while (/*CONSTCOND*/0)\n\n#define\tLIST_REMOVE(elm, field) do {\t\t\t\t\t\\\n\tif ((elm)->field.le_next != NULL)\t\t\t\t\\\n\t\t(elm)->field.le_next->field.le_prev = \t\t\t\\\n\t\t    (elm)->field.le_prev;\t\t\t\t\\\n\t*(elm)->field.le_prev = (elm)->field.le_next;\t\t\t\\\n} while (/*CONSTCOND*/0)\n\n#define\tLIST_FOREACH(var, head, field)\t\t\t\t\t\\\n\tfor ((var) = ((head)->lh_first);\t\t\t\t\\\n\t\t(var);\t\t\t\t\t\t\t\\\n\t\t(var) = ((var)->field.le_next))\n\n/*\n * List access methods.\n */\n#define\tLIST_EMPTY(head)\t\t((head)->lh_first == NULL)\n#define\tLIST_FIRST(head)\t\t((head)->lh_first)\n#define\tLIST_NEXT(elm, field)\t\t((elm)->field.le_next)\n\n\n/*\n * Singly-linked List definitions.\n */\n#define\tSLIST_HEAD(name, type)\t\t\t\t\t\t\\\nstruct name {\t\t\t\t\t\t\t\t\\\n\tstruct type *slh_first;\t/* first element */\t\t\t\\\n}\n\n#define\tSLIST_HEAD_INITIALIZER(head)\t\t\t\t\t\\\n\t{ NULL }\n\n#define\tSLIST_ENTRY(type)\t\t\t\t\t\t\\\nstruct {\t\t\t\t\t\t\t\t\\\n\tstruct type *sle_next;\t/* next element */\t\t\t\\\n}\n\n/*\n * Singly-linked List functions.\n */\n#define\tSLIST_INIT(head) do {\t\t\t\t\t\t\\\n\t(head)->slh_first = NULL;\t\t\t\t\t\\\n} while (/*CONSTCOND*/0)\n\n#define\tSLIST_INSERT_AFTER(slistelm, elm, field) do {\t\t\t\\\n\t(elm)->field.sle_next = (slistelm)->field.sle_next;\t\t\\\n\t(slistelm)->field.sle_next = (elm);\t\t\t\t\\\n} while (/*CONSTCOND*/0)\n\n#define\tSLIST_INSERT_HEAD(head, elm, field) do {\t\t\t\\\n\t(elm)->field.sle_next = (head)->slh_first;\t\t\t\\\n\t(head)->slh_first = (elm);\t\t\t\t\t\\\n} while (/*CONSTCOND*/0)\n\n#define\tSLIST_REMOVE_HEAD(head, field) do {\t\t\t\t\\\n\t(head)->slh_first = (head)->slh_first->field.sle_next;\t\t\\\n} while (/*CONSTCOND*/0)\n\n#define\tSLIST_REMOVE(head, elm, type, field) do {\t\t\t\\\n\tif ((head)->slh_first == (elm)) {\t\t\t\t\\\n\t\tSLIST_REMOVE_HEAD((head), field);\t\t\t\\\n\t}\t\t\t\t\t\t\t\t\\\n\telse {\t\t\t\t\t\t\t\t\\\n\t\tstruct type *curelm = (head)->slh_first;\t\t\\\n\t\twhile(curelm->field.sle_next != (elm))\t\t\t\\\n\t\t\tcurelm = curelm->field.sle_next;\t\t\\\n\t\tcurelm->field.sle_next =\t\t\t\t\\\n\t\t    curelm->field.sle_next->field.sle_next;\t\t\\\n\t}\t\t\t\t\t\t\t\t\\\n} while (/*CONSTCOND*/0)\n\n#define\tSLIST_FOREACH(var, head, field)\t\t\t\t\t\\\n\tfor((var) = (head)->slh_first; (var); (var) = (var)->field.sle_next)\n\n/*\n * Singly-linked List access methods.\n */\n#define\tSLIST_EMPTY(head)\t((head)->slh_first == NULL)\n#define\tSLIST_FIRST(head)\t((head)->slh_first)\n#define\tSLIST_NEXT(elm, field)\t((elm)->field.sle_next)\n\n\n/*\n * Singly-linked Tail queue declarations.\n */\n#define\tSTAILQ_HEAD(name, type)\t\t\t\t\t\\\nstruct name {\t\t\t\t\t\t\t\t\\\n\tstruct type *stqh_first;\t/* first element */\t\t\t\\\n\tstruct type **stqh_last;\t/* addr of last next element */\t\t\\\n}\n\n#define\tSTAILQ_HEAD_INITIALIZER(head)\t\t\t\t\t\\\n\t{ NULL, &(head).stqh_first }\n\n#define\tSTAILQ_ENTRY(type)\t\t\t\t\t\t\\\nstruct {\t\t\t\t\t\t\t\t\\\n\tstruct type *stqe_next;\t/* next element */\t\t\t\\\n}\n\n/*\n * Singly-linked Tail queue functions.\n */\n#define\tSTAILQ_INIT(head) do {\t\t\t\t\t\t\\\n\t(head)->stqh_first = NULL;\t\t\t\t\t\\\n\t(head)->stqh_last = &(head)->stqh_first;\t\t\t\t\\\n} while (/*CONSTCOND*/0)\n\n#define\tSTAILQ_INSERT_HEAD(head, elm, field) do {\t\t\t\\\n\tif (((elm)->field.stqe_next = (head)->stqh_first) == NULL)\t\\\n\t\t(head)->stqh_last = &(elm)->field.stqe_next;\t\t\\\n\t(head)->stqh_first = (elm);\t\t\t\t\t\\\n} while (/*CONSTCOND*/0)\n\n#define\tSTAILQ_INSERT_TAIL(head, elm, field) do {\t\t\t\\\n\t(elm)->field.stqe_next = NULL;\t\t\t\t\t\\\n\t*(head)->stqh_last = (elm);\t\t\t\t\t\\\n\t(head)->stqh_last = &(elm)->field.stqe_next;\t\t\t\\\n} while (/*CONSTCOND*/0)\n\n#define\tSTAILQ_INSERT_AFTER(head, listelm, elm, field) do {\t\t\\\n\tif (((elm)->field.stqe_next = (listelm)->field.stqe_next) == NULL)\\\n\t\t(head)->stqh_last = &(elm)->field.stqe_next;\t\t\\\n\t(listelm)->field.stqe_next = (elm);\t\t\t\t\\\n} while (/*CONSTCOND*/0)\n\n#define\tSTAILQ_REMOVE_HEAD(head, field) do {\t\t\t\t\\\n\tif (((head)->stqh_first = (head)->stqh_first->field.stqe_next) == NULL) \\\n\t\t(head)->stqh_last = &(head)->stqh_first;\t\t\t\\\n} while (/*CONSTCOND*/0)\n\n#define\tSTAILQ_REMOVE(head, elm, type, field) do {\t\t\t\\\n\tif ((head)->stqh_first == (elm)) {\t\t\t\t\\\n\t\tSTAILQ_REMOVE_HEAD((head), field);\t\t\t\\\n\t} else {\t\t\t\t\t\t\t\\\n\t\tstruct type *curelm = (head)->stqh_first;\t\t\\\n\t\twhile (curelm->field.stqe_next != (elm))\t\t\t\\\n\t\t\tcurelm = curelm->field.stqe_next;\t\t\\\n\t\tif ((curelm->field.stqe_next =\t\t\t\t\\\n\t\t\tcurelm->field.stqe_next->field.stqe_next) == NULL) \\\n\t\t\t    (head)->stqh_last = &(curelm)->field.stqe_next; \\\n\t}\t\t\t\t\t\t\t\t\\\n} while (/*CONSTCOND*/0)\n\n#define\tSTAILQ_FOREACH(var, head, field)\t\t\t\t\\\n\tfor ((var) = ((head)->stqh_first);\t\t\t\t\\\n\t\t(var);\t\t\t\t\t\t\t\\\n\t\t(var) = ((var)->field.stqe_next))\n\n#define\tSTAILQ_CONCAT(head1, head2) do {\t\t\t\t\\\n\tif (!STAILQ_EMPTY((head2))) {\t\t\t\t\t\\\n\t\t*(head1)->stqh_last = (head2)->stqh_first;\t\t\\\n\t\t(head1)->stqh_last = (head2)->stqh_last;\t\t\\\n\t\tSTAILQ_INIT((head2));\t\t\t\t\t\\\n\t}\t\t\t\t\t\t\t\t\\\n} while (/*CONSTCOND*/0)\n\n/*\n * Singly-linked Tail queue access methods.\n */\n#define\tSTAILQ_EMPTY(head)\t((head)->stqh_first == NULL)\n#define\tSTAILQ_FIRST(head)\t((head)->stqh_first)\n#define\tSTAILQ_NEXT(elm, field)\t((elm)->field.stqe_next)\n\n\n/*\n * Simple queue definitions.\n */\n#define\tSIMPLEQ_HEAD(name, type)\t\t\t\t\t\\\nstruct name {\t\t\t\t\t\t\t\t\\\n\tstruct type *sqh_first;\t/* first element */\t\t\t\\\n\tstruct type **sqh_last;\t/* addr of last next element */\t\t\\\n}\n\n#define\tSIMPLEQ_HEAD_INITIALIZER(head)\t\t\t\t\t\\\n\t{ NULL, &(head).sqh_first }\n\n#define\tSIMPLEQ_ENTRY(type)\t\t\t\t\t\t\\\nstruct {\t\t\t\t\t\t\t\t\\\n\tstruct type *sqe_next;\t/* next element */\t\t\t\\\n}\n\n/*\n * Simple queue functions.\n */\n#define\tSIMPLEQ_INIT(head) do {\t\t\t\t\t\t\\\n\t(head)->sqh_first = NULL;\t\t\t\t\t\\\n\t(head)->sqh_last = &(head)->sqh_first;\t\t\t\t\\\n} while (/*CONSTCOND*/0)\n\n#define\tSIMPLEQ_INSERT_HEAD(head, elm, field) do {\t\t\t\\\n\tif (((elm)->field.sqe_next = (head)->sqh_first) == NULL)\t\\\n\t\t(head)->sqh_last = &(elm)->field.sqe_next;\t\t\\\n\t(head)->sqh_first = (elm);\t\t\t\t\t\\\n} while (/*CONSTCOND*/0)\n\n#define\tSIMPLEQ_INSERT_TAIL(head, elm, field) do {\t\t\t\\\n\t(elm)->field.sqe_next = NULL;\t\t\t\t\t\\\n\t*(head)->sqh_last = (elm);\t\t\t\t\t\\\n\t(head)->sqh_last = &(elm)->field.sqe_next;\t\t\t\\\n} while (/*CONSTCOND*/0)\n\n#define\tSIMPLEQ_INSERT_AFTER(head, listelm, elm, field) do {\t\t\\\n\tif (((elm)->field.sqe_next = (listelm)->field.sqe_next) == NULL)\\\n\t\t(head)->sqh_last = &(elm)->field.sqe_next;\t\t\\\n\t(listelm)->field.sqe_next = (elm);\t\t\t\t\\\n} while (/*CONSTCOND*/0)\n\n#define\tSIMPLEQ_REMOVE_HEAD(head, field) do {\t\t\t\t\\\n\tif (((head)->sqh_first = (head)->sqh_first->field.sqe_next) == NULL) \\\n\t\t(head)->sqh_last = &(head)->sqh_first;\t\t\t\\\n} while (/*CONSTCOND*/0)\n\n#define\tSIMPLEQ_REMOVE(head, elm, type, field) do {\t\t\t\\\n\tif ((head)->sqh_first == (elm)) {\t\t\t\t\\\n\t\tSIMPLEQ_REMOVE_HEAD((head), field);\t\t\t\\\n\t} else {\t\t\t\t\t\t\t\\\n\t\tstruct type *curelm = (head)->sqh_first;\t\t\\\n\t\twhile (curelm->field.sqe_next != (elm))\t\t\t\\\n\t\t\tcurelm = curelm->field.sqe_next;\t\t\\\n\t\tif ((curelm->field.sqe_next =\t\t\t\t\\\n\t\t\tcurelm->field.sqe_next->field.sqe_next) == NULL) \\\n\t\t\t    (head)->sqh_last = &(curelm)->field.sqe_next; \\\n\t}\t\t\t\t\t\t\t\t\\\n} while (/*CONSTCOND*/0)\n\n#define\tSIMPLEQ_FOREACH(var, head, field)\t\t\t\t\\\n\tfor ((var) = ((head)->sqh_first);\t\t\t\t\\\n\t\t(var);\t\t\t\t\t\t\t\\\n\t\t(var) = ((var)->field.sqe_next))\n\n/*\n * Simple queue access methods.\n */\n#define\tSIMPLEQ_EMPTY(head)\t\t((head)->sqh_first == NULL)\n#define\tSIMPLEQ_FIRST(head)\t\t((head)->sqh_first)\n#define\tSIMPLEQ_NEXT(elm, field)\t((elm)->field.sqe_next)\n\n\n/*\n * Tail queue definitions.\n */\n#define\t_TAILQ_HEAD(name, type, qual)\t\t\t\t\t\\\nstruct name {\t\t\t\t\t\t\t\t\\\n\tqual type *tqh_first;\t\t/* first element */\t\t\\\n\tqual type *qual *tqh_last;\t/* addr of last next element */\t\\\n}\n#define TAILQ_HEAD(name, type)\t_TAILQ_HEAD(name, struct type,)\n\n#define\tTAILQ_HEAD_INITIALIZER(head)\t\t\t\t\t\\\n\t{ NULL, &(head).tqh_first }\n\n#define\t_TAILQ_ENTRY(type, qual)\t\t\t\t\t\\\nstruct {\t\t\t\t\t\t\t\t\\\n\tqual type *tqe_next;\t\t/* next element */\t\t\\\n\tqual type *qual *tqe_prev;\t/* address of previous next element */\\\n}\n#define TAILQ_ENTRY(type)\t_TAILQ_ENTRY(struct type,)\n\n/*\n * Tail queue functions.\n */\n#define\tTAILQ_INIT(head) do {\t\t\t\t\t\t\\\n\t(head)->tqh_first = NULL;\t\t\t\t\t\\\n\t(head)->tqh_last = &(head)->tqh_first;\t\t\t\t\\\n} while (/*CONSTCOND*/0)\n\n#define\tTAILQ_INSERT_HEAD(head, elm, field) do {\t\t\t\\\n\tif (((elm)->field.tqe_next = (head)->tqh_first) != NULL)\t\\\n\t\t(head)->tqh_first->field.tqe_prev =\t\t\t\\\n\t\t    &(elm)->field.tqe_next;\t\t\t\t\\\n\telse\t\t\t\t\t\t\t\t\\\n\t\t(head)->tqh_last = &(elm)->field.tqe_next;\t\t\\\n\t(head)->tqh_first = (elm);\t\t\t\t\t\\\n\t(elm)->field.tqe_prev = &(head)->tqh_first;\t\t\t\\\n} while (/*CONSTCOND*/0)\n\n#define\tTAILQ_INSERT_TAIL(head, elm, field) do {\t\t\t\\\n\t(elm)->field.tqe_next = NULL;\t\t\t\t\t\\\n\t(elm)->field.tqe_prev = (head)->tqh_last;\t\t\t\\\n\t*(head)->tqh_last = (elm);\t\t\t\t\t\\\n\t(head)->tqh_last = &(elm)->field.tqe_next;\t\t\t\\\n} while (/*CONSTCOND*/0)\n\n#define\tTAILQ_INSERT_AFTER(head, listelm, elm, field) do {\t\t\\\n\tif (((elm)->field.tqe_next = (listelm)->field.tqe_next) != NULL)\\\n\t\t(elm)->field.tqe_next->field.tqe_prev = \t\t\\\n\t\t    &(elm)->field.tqe_next;\t\t\t\t\\\n\telse\t\t\t\t\t\t\t\t\\\n\t\t(head)->tqh_last = &(elm)->field.tqe_next;\t\t\\\n\t(listelm)->field.tqe_next = (elm);\t\t\t\t\\\n\t(elm)->field.tqe_prev = &(listelm)->field.tqe_next;\t\t\\\n} while (/*CONSTCOND*/0)\n\n#define\tTAILQ_INSERT_BEFORE(listelm, elm, field) do {\t\t\t\\\n\t(elm)->field.tqe_prev = (listelm)->field.tqe_prev;\t\t\\\n\t(elm)->field.tqe_next = (listelm);\t\t\t\t\\\n\t*(listelm)->field.tqe_prev = (elm);\t\t\t\t\\\n\t(listelm)->field.tqe_prev = &(elm)->field.tqe_next;\t\t\\\n} while (/*CONSTCOND*/0)\n\n#define\tTAILQ_REMOVE(head, elm, field) do {\t\t\t\t\\\n\tif (((elm)->field.tqe_next) != NULL)\t\t\t\t\\\n\t\t(elm)->field.tqe_next->field.tqe_prev = \t\t\\\n\t\t    (elm)->field.tqe_prev;\t\t\t\t\\\n\telse\t\t\t\t\t\t\t\t\\\n\t\t(head)->tqh_last = (elm)->field.tqe_prev;\t\t\\\n\t*(elm)->field.tqe_prev = (elm)->field.tqe_next;\t\t\t\\\n} while (/*CONSTCOND*/0)\n\n#define\tTAILQ_FOREACH(var, head, field)\t\t\t\t\t\\\n\tfor ((var) = ((head)->tqh_first);\t\t\t\t\\\n\t\t(var);\t\t\t\t\t\t\t\\\n\t\t(var) = ((var)->field.tqe_next))\n\n#define\tTAILQ_FOREACH_REVERSE(var, head, headname, field)\t\t\\\n\tfor ((var) = (*(((struct headname *)((head)->tqh_last))->tqh_last));\t\\\n\t\t(var);\t\t\t\t\t\t\t\\\n\t\t(var) = (*(((struct headname *)((var)->field.tqe_prev))->tqh_last)))\n\n#define\tTAILQ_CONCAT(head1, head2, field) do {\t\t\t\t\\\n\tif (!TAILQ_EMPTY(head2)) {\t\t\t\t\t\\\n\t\t*(head1)->tqh_last = (head2)->tqh_first;\t\t\\\n\t\t(head2)->tqh_first->field.tqe_prev = (head1)->tqh_last;\t\\\n\t\t(head1)->tqh_last = (head2)->tqh_last;\t\t\t\\\n\t\tTAILQ_INIT((head2));\t\t\t\t\t\\\n\t}\t\t\t\t\t\t\t\t\\\n} while (/*CONSTCOND*/0)\n\n/*\n * Tail queue access methods.\n */\n#define\tTAILQ_EMPTY(head)\t\t((head)->tqh_first == NULL)\n#define\tTAILQ_FIRST(head)\t\t((head)->tqh_first)\n#define\tTAILQ_NEXT(elm, field)\t\t((elm)->field.tqe_next)\n\n#define\tTAILQ_LAST(head, headname) \\\n\t(*(((struct headname *)((head)->tqh_last))->tqh_last))\n#define\tTAILQ_PREV(elm, headname, field) \\\n\t(*(((struct headname *)((elm)->field.tqe_prev))->tqh_last))\n\n\n/*\n * Circular queue definitions.\n */\n#define\tCIRCLEQ_HEAD(name, type)\t\t\t\t\t\\\nstruct name {\t\t\t\t\t\t\t\t\\\n\tstruct type *cqh_first;\t\t/* first element */\t\t\\\n\tstruct type *cqh_last;\t\t/* last element */\t\t\\\n}\n\n#define\tCIRCLEQ_HEAD_INITIALIZER(head)\t\t\t\t\t\\\n\t{ (void *)&head, (void *)&head }\n\n#define\tCIRCLEQ_ENTRY(type)\t\t\t\t\t\t\\\nstruct {\t\t\t\t\t\t\t\t\\\n\tstruct type *cqe_next;\t\t/* next element */\t\t\\\n\tstruct type *cqe_prev;\t\t/* previous element */\t\t\\\n}\n\n/*\n * Circular queue functions.\n */\n#define\tCIRCLEQ_INIT(head) do {\t\t\t\t\t\t\\\n\t(head)->cqh_first = (void *)(head);\t\t\t\t\\\n\t(head)->cqh_last = (void *)(head);\t\t\t\t\\\n} while (/*CONSTCOND*/0)\n\n#define\tCIRCLEQ_INSERT_AFTER(head, listelm, elm, field) do {\t\t\\\n\t(elm)->field.cqe_next = (listelm)->field.cqe_next;\t\t\\\n\t(elm)->field.cqe_prev = (listelm);\t\t\t\t\\\n\tif ((listelm)->field.cqe_next == (void *)(head))\t\t\\\n\t\t(head)->cqh_last = (elm);\t\t\t\t\\\n\telse\t\t\t\t\t\t\t\t\\\n\t\t(listelm)->field.cqe_next->field.cqe_prev = (elm);\t\\\n\t(listelm)->field.cqe_next = (elm);\t\t\t\t\\\n} while (/*CONSTCOND*/0)\n\n#define\tCIRCLEQ_INSERT_BEFORE(head, listelm, elm, field) do {\t\t\\\n\t(elm)->field.cqe_next = (listelm);\t\t\t\t\\\n\t(elm)->field.cqe_prev = (listelm)->field.cqe_prev;\t\t\\\n\tif ((listelm)->field.cqe_prev == (void *)(head))\t\t\\\n\t\t(head)->cqh_first = (elm);\t\t\t\t\\\n\telse\t\t\t\t\t\t\t\t\\\n\t\t(listelm)->field.cqe_prev->field.cqe_next = (elm);\t\\\n\t(listelm)->field.cqe_prev = (elm);\t\t\t\t\\\n} while (/*CONSTCOND*/0)\n\n#define\tCIRCLEQ_INSERT_HEAD(head, elm, field) do {\t\t\t\\\n\t(elm)->field.cqe_next = (head)->cqh_first;\t\t\t\\\n\t(elm)->field.cqe_prev = (void *)(head);\t\t\t\t\\\n\tif ((head)->cqh_last == (void *)(head))\t\t\t\t\\\n\t\t(head)->cqh_last = (elm);\t\t\t\t\\\n\telse\t\t\t\t\t\t\t\t\\\n\t\t(head)->cqh_first->field.cqe_prev = (elm);\t\t\\\n\t(head)->cqh_first = (elm);\t\t\t\t\t\\\n} while (/*CONSTCOND*/0)\n\n#define\tCIRCLEQ_INSERT_TAIL(head, elm, field) do {\t\t\t\\\n\t(elm)->field.cqe_next = (void *)(head);\t\t\t\t\\\n\t(elm)->field.cqe_prev = (head)->cqh_last;\t\t\t\\\n\tif ((head)->cqh_first == (void *)(head))\t\t\t\\\n\t\t(head)->cqh_first = (elm);\t\t\t\t\\\n\telse\t\t\t\t\t\t\t\t\\\n\t\t(head)->cqh_last->field.cqe_next = (elm);\t\t\\\n\t(head)->cqh_last = (elm);\t\t\t\t\t\\\n} while (/*CONSTCOND*/0)\n\n#define\tCIRCLEQ_REMOVE(head, elm, field) do {\t\t\t\t\\\n\tif ((elm)->field.cqe_next == (void *)(head))\t\t\t\\\n\t\t(head)->cqh_last = (elm)->field.cqe_prev;\t\t\\\n\telse\t\t\t\t\t\t\t\t\\\n\t\t(elm)->field.cqe_next->field.cqe_prev =\t\t\t\\\n\t\t    (elm)->field.cqe_prev;\t\t\t\t\\\n\tif ((elm)->field.cqe_prev == (void *)(head))\t\t\t\\\n\t\t(head)->cqh_first = (elm)->field.cqe_next;\t\t\\\n\telse\t\t\t\t\t\t\t\t\\\n\t\t(elm)->field.cqe_prev->field.cqe_next =\t\t\t\\\n\t\t    (elm)->field.cqe_next;\t\t\t\t\\\n} while (/*CONSTCOND*/0)\n\n#define\tCIRCLEQ_FOREACH(var, head, field)\t\t\t\t\\\n\tfor ((var) = ((head)->cqh_first);\t\t\t\t\\\n\t\t(var) != (const void *)(head);\t\t\t\t\\\n\t\t(var) = ((var)->field.cqe_next))\n\n#define\tCIRCLEQ_FOREACH_REVERSE(var, head, field)\t\t\t\\\n\tfor ((var) = ((head)->cqh_last);\t\t\t\t\\\n\t\t(var) != (const void *)(head);\t\t\t\t\\\n\t\t(var) = ((var)->field.cqe_prev))\n\n/*\n * Circular queue access methods.\n */\n#define\tCIRCLEQ_EMPTY(head)\t\t((head)->cqh_first == (void *)(head))\n#define\tCIRCLEQ_FIRST(head)\t\t((head)->cqh_first)\n#define\tCIRCLEQ_LAST(head)\t\t((head)->cqh_last)\n#define\tCIRCLEQ_NEXT(elm, field)\t((elm)->field.cqe_next)\n#define\tCIRCLEQ_PREV(elm, field)\t((elm)->field.cqe_prev)\n\n#define CIRCLEQ_LOOP_NEXT(head, elm, field)\t\t\t\t\\\n\t(((elm)->field.cqe_next == (void *)(head))\t\t\t\\\n\t    ? ((head)->cqh_first)\t\t\t\t\t\\\n\t    : (elm->field.cqe_next))\n#define CIRCLEQ_LOOP_PREV(head, elm, field)\t\t\t\t\\\n\t(((elm)->field.cqe_prev == (void *)(head))\t\t\t\\\n\t    ? ((head)->cqh_last)\t\t\t\t\t\\\n\t    : (elm->field.cqe_prev))\n\n#endif\t/* sys/queue.h */\n"
  },
  {
    "path": "toolchain/musl/patches/110-read_timezone_from_fs.patch",
    "content": "--- a/src/time/__tz.c\n+++ b/src/time/__tz.c\n@@ -32,6 +32,9 @@ static int r0[5], r1[5];\n static const unsigned char *zi, *trans, *index, *types, *abbrevs, *abbrevs_end;\n static size_t map_size;\n \n+static const char *tzfile;\n+static size_t tzfile_size;\n+\n static char old_tz_buf[32];\n static char *old_tz = old_tz_buf;\n static size_t old_tz_size = sizeof old_tz_buf;\n@@ -133,6 +136,15 @@ static void do_tzset()\n \t\t\"/usr/share/zoneinfo/\\0/share/zoneinfo/\\0/etc/zoneinfo/\\0\";\n \n \ts = getenv(\"TZ\");\n+\n+\t/* if TZ is empty try to read it from /etc/TZ */\n+\tif (!s || !*s) {\n+\t\tif (tzfile)\n+\t\t\t__munmap((void*)tzfile, tzfile_size);\n+\n+\t\ts = tzfile = (void *)__map_file(\"/etc/TZ\", &tzfile_size);\n+\t}\n+\n \tif (!s) s = \"/etc/localtime\";\n \tif (!*s) s = __utc;\n \n"
  },
  {
    "path": "toolchain/musl/patches/200-add_libssp_nonshared.patch",
    "content": "From 7ec87fbbc3cac99b4173d082dd6195f47c9a32e7 Mon Sep 17 00:00:00 2001\nFrom: Steven Barth <steven@midlink.org>\nDate: Mon, 22 Jun 2015 11:01:56 +0200\nSubject: [PATCH] Add libssp_nonshared.a so GCC's is not needed\n\nSigned-off-by: Steven Barth <steven@midlink.org>\n\n--- a/Makefile\n+++ b/Makefile\n@@ -67,7 +67,7 @@ CRT_LIBS = $(addprefix lib/,$(notdir $(C\n STATIC_LIBS = lib/libc.a\n SHARED_LIBS = lib/libc.so\n TOOL_LIBS = lib/musl-gcc.specs\n-ALL_LIBS = $(CRT_LIBS) $(STATIC_LIBS) $(SHARED_LIBS) $(EMPTY_LIBS) $(TOOL_LIBS)\n+ALL_LIBS = $(CRT_LIBS) $(STATIC_LIBS) $(SHARED_LIBS) $(EMPTY_LIBS) $(TOOL_LIBS) lib/libssp_nonshared.a\n ALL_TOOLS = obj/musl-gcc\n \n WRAPCC_GCC = gcc\n@@ -88,7 +88,7 @@ else\n \n all: $(ALL_LIBS) $(ALL_TOOLS)\n \n-OBJ_DIRS = $(sort $(patsubst %/,%,$(dir $(ALL_LIBS) $(ALL_TOOLS) $(ALL_OBJS) $(GENH) $(GENH_INT))) obj/include)\n+OBJ_DIRS = $(sort $(patsubst %/,%,$(dir $(ALL_LIBS) $(ALL_TOOLS) $(ALL_OBJS) $(GENH) $(GENH_INT))) obj/include obj/libssp_nonshared)\n \n $(ALL_LIBS) $(ALL_TOOLS) $(ALL_OBJS) $(ALL_OBJS:%.o=%.lo) $(GENH) $(GENH_INT): | $(OBJ_DIRS)\n \n@@ -115,6 +115,8 @@ obj/crt/rcrt1.o: $(srcdir)/ldso/dlstart.\n \n obj/crt/Scrt1.o obj/crt/rcrt1.o: CFLAGS_ALL += -fPIC\n \n+obj/libssp_nonshared/__stack_chk_fail_local.o: CFLAGS_ALL += $(CFLAGS_NOSSP)\n+\n OPTIMIZE_SRCS = $(wildcard $(OPTIMIZE_GLOBS:%=$(srcdir)/src/%))\n $(OPTIMIZE_SRCS:$(srcdir)/%.c=obj/%.o) $(OPTIMIZE_SRCS:$(srcdir)/%.c=obj/%.lo): CFLAGS += -O3\n \n@@ -167,6 +169,11 @@ lib/libc.a: $(AOBJS)\n \t$(AR) rc $@ $(AOBJS)\n \t$(RANLIB) $@\n \n+lib/libssp_nonshared.a: obj/libssp_nonshared/__stack_chk_fail_local.o\n+\trm -f $@\n+\t$(AR) rc $@ $<\n+\t$(RANLIB) $@\n+\n $(EMPTY_LIBS):\n \trm -f $@\n \t$(AR) rc $@\n--- /dev/null\n+++ b/libssp_nonshared/__stack_chk_fail_local.c\n@@ -0,0 +1,2 @@\n+#include \"atomic.h\"\n+void __attribute__((visibility (\"hidden\"))) __stack_chk_fail_local(void) { a_crash(); }\n"
  },
  {
    "path": "toolchain/musl/patches/300-relative.patch",
    "content": "--- a/Makefile\n+++ b/Makefile\n@@ -217,7 +217,7 @@ $(DESTDIR)$(includedir)/%: $(srcdir)/inc\n \t$(INSTALL) -D -m 644 $< $@\n \n $(DESTDIR)$(LDSO_PATHNAME): $(DESTDIR)$(libdir)/libc.so\n-\t$(INSTALL) -D -l $(libdir)/libc.so $@ || true\n+\t$(INSTALL) -D -l libc.so $@ || true\n \n install-libs: $(ALL_LIBS:lib/%=$(DESTDIR)$(libdir)/%) $(if $(SHARED_LIBS),$(DESTDIR)$(LDSO_PATHNAME),)\n \n"
  },
  {
    "path": "toolchain/musl/patches/600-nftw-support-common-gnu-extension.patch",
    "content": "From 6f1143425a3afc4eb5086e9c90e7efb3affd7cb7 Mon Sep 17 00:00:00 2001\nFrom: Tony Ambardar <Tony.Ambardar@gmail.com>\nDate: Sat, 11 Jul 2020 06:35:46 -0700\nSubject: [PATCH 2/2] nftw: support common gnu extension\n\nSigned-off-by: Tony Ambardar <Tony.Ambardar@gmail.com>\n---\n include/ftw.h   |  8 ++++++++\n src/misc/nftw.c | 35 ++++++++++++++++++++++++++++++-----\n 2 files changed, 38 insertions(+), 5 deletions(-)\n\n--- a/include/ftw.h\n+++ b/include/ftw.h\n@@ -21,6 +21,14 @@ extern \"C\" {\n #define FTW_CHDIR 4\n #define FTW_DEPTH 8\n \n+#ifdef _GNU_SOURCE\n+#define FTW_ACTIONRETVAL 16\n+#define FTW_CONTINUE 0\n+#define FTW_STOP 1\n+#define FTW_SKIP_SUBTREE 2\n+#define FTW_SKIP_SIBLINGS 3\n+#endif\n+\n struct FTW {\n \tint base;\n \tint level;\n--- a/src/misc/nftw.c\n+++ b/src/misc/nftw.c\n@@ -1,3 +1,4 @@\n+#define _GNU_SOURCE\n #include <ftw.h>\n #include <dirent.h>\n #include <fcntl.h>\n@@ -72,8 +73,20 @@ static int do_nftw(char *path, int (*fn)\n \t\tif (!fd_limit) close(dfd);\n \t}\n \n-\tif (!(flags & FTW_DEPTH) && (r=fn(path, &st, type, &lev)))\n-\t\treturn r;\n+\tif (!(flags & FTW_DEPTH) && (r=fn(path, &st, type, &lev))) {\n+\t\tif (flags & FTW_ACTIONRETVAL)\n+\t\t\tswitch (r) {\n+\t\t\tcase FTW_SKIP_SUBTREE:\n+\t\t\t\th = NULL;\n+\t\t\tcase FTW_CONTINUE:\n+\t\t\t\tbreak;\n+\t\t\tcase FTW_SKIP_SIBLINGS:\n+\t\t\tcase FTW_STOP:\n+\t\t\t\treturn r;\n+\t\t\t}\n+\t\telse\n+\t\t\treturn r;\n+\t}\n \n \tfor (; h; h = h->chain)\n \t\tif (h->dev == st.st_dev && h->ino == st.st_ino)\n@@ -101,7 +114,10 @@ static int do_nftw(char *path, int (*fn)\n \t\t\t\tstrcpy(path+j+1, de->d_name);\n \t\t\t\tif ((r=do_nftw(path, fn, fd_limit-1, flags, &new))) {\n \t\t\t\t\tclosedir(d);\n-\t\t\t\t\treturn r;\n+\t\t\t\t\tif ((flags & FTW_ACTIONRETVAL) && r == FTW_SKIP_SIBLINGS)\n+\t\t\t\t\t\tbreak;\n+\t\t\t\t\telse\n+\t\t\t\t\t\treturn r;\n \t\t\t\t}\n \t\t\t}\n \t\t\tclosedir(d);\n@@ -112,8 +128,16 @@ static int do_nftw(char *path, int (*fn)\n \t}\n \n \tpath[l] = 0;\n-\tif ((flags & FTW_DEPTH) && (r=fn(path, &st, type, &lev)))\n-\t\treturn r;\n+\tif ((flags & FTW_DEPTH) && (r=fn(path, &st, type, &lev))) {\n+\t\tif (flags & FTW_ACTIONRETVAL)\n+\t\t\tswitch (r) {\n+\t\t\t\tcase FTW_SKIP_SIBLINGS:\n+\t\t\t\tcase FTW_STOP:\n+\t\t\t\t\treturn r;\n+\t\t\t}\n+\t\telse\n+\t\t\treturn r;\n+\t}\n \n \treturn 0;\n }\n@@ -139,4 +163,5 @@ int nftw(const char *path, int (*fn)(con\n \treturn r;\n }\n \n+#undef nftw64\n weak_alias(nftw, nftw64);\n"
  },
  {
    "path": "toolchain/musl/patches/900-iconv_size_hack.patch",
    "content": "--- a/src/locale/iconv.c\n+++ b/src/locale/iconv.c\n@@ -48,6 +48,7 @@ static const unsigned char charmaps[] =\n \"utf16\\0\\0\\312\"\n \"ucs4\\0utf32\\0\\0\\313\"\n \"ucs2\\0\\0\\314\"\n+#ifdef FULL_ICONV\n \"eucjp\\0\\0\\320\"\n \"shiftjis\\0sjis\\0\\0\\321\"\n \"iso2022jp\\0\\0\\322\"\n@@ -56,6 +57,7 @@ static const unsigned char charmaps[] =\n \"gb2312\\0\\0\\332\"\n \"big5\\0bigfive\\0cp950\\0big5hkscs\\0\\0\\340\"\n \"euckr\\0ksc5601\\0ksx1001\\0cp949\\0\\0\\350\"\n+#endif\n #include \"codepages.h\"\n ;\n \n@@ -66,6 +68,7 @@ static const unsigned short legacy_chars\n #include \"legacychars.h\"\n };\n \n+#ifdef FULL_ICONV\n static const unsigned short jis0208[84][94] = {\n #include \"jis0208.h\"\n };\n@@ -85,6 +88,7 @@ static const unsigned short hkscs[] = {\n static const unsigned short ksc[93][94] = {\n #include \"ksc.h\"\n };\n+#endif\n \n static const unsigned short rev_jis[] = {\n #include \"revjis.h\"\n@@ -205,6 +209,7 @@ static unsigned legacy_map(const unsigne\n \treturn x < 256 ? x : legacy_chars[x-256];\n }\n \n+#ifdef FULL_ICONV\n static unsigned uni_to_jis(unsigned c)\n {\n \tunsigned nel = sizeof rev_jis / sizeof *rev_jis;\n@@ -223,6 +228,7 @@ static unsigned uni_to_jis(unsigned c)\n \t\t}\n \t}\n }\n+#endif\n \n size_t iconv(iconv_t cd, char **restrict in, size_t *restrict inb, char **restrict out, size_t *restrict outb)\n {\n@@ -319,6 +325,7 @@ size_t iconv(iconv_t cd, char **restrict\n \t\t\t}\n \t\t\ttype = scd->state;\n \t\t\tcontinue;\n+#ifdef FULL_ICONV\n \t\tcase SHIFT_JIS:\n \t\t\tif (c < 128) break;\n \t\t\tif (c-0xa1 <= 0xdf-0xa1) {\n@@ -518,6 +525,7 @@ size_t iconv(iconv_t cd, char **restrict\n \t\t\tc = ksc[c][d];\n \t\t\tif (!c) goto ilseq;\n \t\t\tbreak;\n+#endif\n \t\tdefault:\n \t\t\tif (!c) break;\n \t\t\tc = legacy_map(map, c);\n@@ -559,6 +567,7 @@ size_t iconv(iconv_t cd, char **restrict\n \t\t\t\t}\n \t\t\t}\n \t\t\tgoto subst;\n+#ifdef FULL_ICONV\n \t\tcase SHIFT_JIS:\n \t\t\tif (c < 128) goto revout;\n \t\t\tif (c == 0xa5) {\n@@ -632,6 +641,7 @@ size_t iconv(iconv_t cd, char **restrict\n \t\t\t*(*out)++ = 'B';\n \t\t\t*outb -= 8;\n \t\t\tbreak;\n+#endif\n \t\tcase UCS2:\n \t\t\ttotype = UCS2BE;\n \t\tcase UCS2BE:\n--- a/src/locale/codepages.h\n+++ b/src/locale/codepages.h\n@@ -129,6 +129,7 @@\n \"\\340\\204\\43\\316\\100\\344\\34\\144\\316\\71\\350\\244\\243\\316\\72\\354\\264\\343\\316\\73\"\n \"\\21\\361\\44\\317\\74\\364\\30\\145\\17\\124\\146\\345\\243\\317\\76\\374\\134\\304\\327\\77\"\n \n+#ifdef FULL_ICONV\n \"cp1250\\0\"\n \"windows1250\\0\"\n \"\\0\\40\"\n@@ -239,6 +240,7 @@\n \"\\20\\105\\163\\330\\64\\324\\324\\145\\315\\65\\330\\144\\243\\315\\66\\334\\334\\145\\330\\67\"\n \"\\340\\204\\43\\316\\100\\344\\224\\143\\316\\71\\350\\244\\243\\316\\72\\205\\265\\343\\316\\73\"\n \"\\21\\305\\203\\330\\74\\364\\330\\145\\317\\75\\370\\344\\243\\317\\76\\374\\340\\65\\362\\77\"\n+#endif\n \n \"koi8r\\0\"\n \"\\0\\40\"\n"
  },
  {
    "path": "toolchain/musl/patches/901-crypt_size_hack.patch",
    "content": "--- a/src/crypt/crypt_sha512.c\n+++ b/src/crypt/crypt_sha512.c\n@@ -13,6 +13,17 @@\n #include <string.h>\n #include <stdint.h>\n \n+#ifdef CRYPT_SIZE_HACK\n+#include <errno.h>\n+\n+char *__crypt_sha512(const char *key, const char *setting, char *output)\n+{\n+\terrno = ENOSYS;\n+\treturn NULL;\n+}\n+\n+#else\n+\n /* public domain sha512 implementation based on fips180-3 */\n /* >=2^64 bits messages are not supported (about 2000 peta bytes) */\n \n@@ -369,3 +380,4 @@ char *__crypt_sha512(const char *key, co\n \t\treturn \"*\";\n \treturn p;\n }\n+#endif\n--- a/src/crypt/crypt_blowfish.c\n+++ b/src/crypt/crypt_blowfish.c\n@@ -50,6 +50,17 @@\n #include <string.h>\n #include <stdint.h>\n \n+#ifdef CRYPT_SIZE_HACK\n+#include <errno.h>\n+\n+char *__crypt_blowfish(const char *key, const char *setting, char *output)\n+{\n+\terrno = ENOSYS;\n+\treturn NULL;\n+}\n+\n+#else\n+\n typedef uint32_t BF_word;\n typedef int32_t BF_word_signed;\n \n@@ -804,3 +815,4 @@ char *__crypt_blowfish(const char *key,\n \n \treturn \"*\";\n }\n+#endif\n--- a/src/crypt/crypt_sha256.c\n+++ b/src/crypt/crypt_sha256.c\n@@ -13,6 +13,17 @@\n #include <string.h>\n #include <stdint.h>\n \n+#ifdef CRYPT_SIZE_HACK\n+#include <errno.h>\n+\n+char *__crypt_sha256(const char *key, const char *setting, char *output)\n+{\n+\terrno = ENOSYS;\n+\treturn NULL;\n+}\n+\n+#else\n+\n /* public domain sha256 implementation based on fips180-3 */\n \n struct sha256 {\n@@ -320,3 +331,4 @@ char *__crypt_sha256(const char *key, co\n \t\treturn \"*\";\n \treturn p;\n }\n+#endif\n"
  },
  {
    "path": "toolchain/nasm/Makefile",
    "content": "#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=nasm\nPKG_VERSION:=2.15.05\n\nPKG_SOURCE_URL:=https://www.nasm.us/pub/nasm/releasebuilds/$(PKG_VERSION)/\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz\n\nPKG_HASH:=3caf6729c1073bf96629b57cee31eeb54f4f8129b01902c73428836550b30a3f\n\nHOST_BUILD_PARALLEL:=1\n\ninclude $(INCLUDE_DIR)/toolchain-build.mk\n\nHOST_CONFIGURE_ARGS+= \\\n\t\t--target=$(REAL_GNU_TARGET_NAME) \\\n\t\t--with-sysroot=$(TOOLCHAIN_DIR) \\\n\t\t--disable-lto \\\n\t\t--disable-werror \\\n\t\t--disable-gdb \\\n\t\t$(SOFT_FLOAT_CONFIG_OPTION) \\\n\ndefine Host/Prepare\n\t$(call Host/Prepare/Default)\n\tln -snf $(notdir $(HOST_BUILD_DIR)) $(BUILD_DIR_TOOLCHAIN)/$(PKG_NAME)\n\t$(CP) $(SCRIPT_DIR)/config.{guess,sub} $(HOST_BUILD_DIR)/\nendef\n\ndefine Host/Configure\n\t(cd $(HOST_BUILD_DIR); \\\n\t\t./autogen.sh \\\n\t);\n\t$(call Host/Configure/Default)\nendef\n\ndefine Host/Install\n\t$(MAKE) -C $(HOST_BUILD_DIR) \\\n\t\t$(HOST_MAKE_FLAGS) \\\n\t\tprefix=$(TOOLCHAIN_DIR) \\\n\t\tinstall\nendef\n\ndefine Host/Clean\n\trm -rf \\\n\t\t$(HOST_BUILD_DIR) \\\n\t\t$(BUILD_DIR_TOOLCHAIN)/$(PKG_NAME)\nendef\n\n$(eval $(call HostBuild))\n"
  },
  {
    "path": "toolchain/wrapper/Makefile",
    "content": "#\n# Copyright (C) 2012 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=wrapper\nPKG_VERSION:=1\n\ninclude $(INCLUDE_DIR)/toolchain-build.mk\n\n\n# 1: args\ndefine toolchain_util\n$(strip $(SCRIPT_DIR)/ext-toolchain.sh --toolchain $(CONFIG_TOOLCHAIN_ROOT) \\\n\t--cflags $(CONFIG_TARGET_OPTIMIZATION) \\\n\t--cflags \"$(if $(call qstrip,$(CONFIG_TOOLCHAIN_LIBC)),-m$(call qstrip,$(CONFIG_TOOLCHAIN_LIBC))) $(if $(CONFIG_SOFT_FLOAT),-msoft-float)\" \\\n\t--cflags \"$(patsubst ./%,-I$(TOOLCHAIN_ROOT_DIR)/%,$(call qstrip,$(CONFIG_TOOLCHAIN_INC_PATH)))\" \\\n\t--cflags \"$(patsubst ./%,-L$(TOOLCHAIN_ROOT_DIR)/%,$(call qstrip,$(CONFIG_TOOLCHAIN_LIB_PATH)))\" \\\n\t$(1))\nendef\n\n# 1: config symbol\n# 2: feature\ndefine toolchain_test\n$$(if $$($(1)), \\\n\t@echo -n \"Testing external toolchain for $(2) support ... \"; \\\n\tif $(call toolchain_util,--test \"$(2)\"); then \\\n\t\techo \"ok\"; exit 0; \\\n\telse \\\n\t\techo \"failed\"; \\\n\t\techo \"ERROR: $(1) is enabled but the external toolchain does not support it\"; \\\n\t\texit 1; \\\n\tfi)\nendef\n\n\ndefine Host/Prepare\n\t$(call toolchain_test,CONFIG_SOFT_FLOAT,softfloat)\n\t$(call toolchain_test,CONFIG_IPV6,ipv6)\n\t$(call toolchain_test,CONFIG_NLS,wchar)\n\t$(call toolchain_test,CONFIG_PACKAGE_libpthread,threads)\nendef\n\ndefine Host/Configure\nendef\n\ndefine Host/Compile\nendef\n\ndefine Host/Install\n\t$(call toolchain_util,--wrap \"$(TOOLCHAIN_DIR)/bin\")\nendef\n\ndefine Host/Clean\n\trm -rf $(TOOLCHAIN_DIR)/bin\nendef\n\n$(eval $(call HostBuild))\n"
  },
  {
    "path": "tools/Makefile",
    "content": "#\n# Copyright (C) 2006-2011 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n# Main makefile for the host tools\n#\ncurdir:=tools\n\n# subdirectories to descend into\ntools-y :=\n\nifeq ($(CONFIG_EXTERNAL_TOOLCHAIN),)\n  BUILD_TOOLCHAIN := y\n  ifdef CONFIG_GCC_USE_GRAPHITE\n    BUILD_ISL = y\n  endif\nendif\nifneq ($(CONFIG_SDK)$(CONFIG_PACKAGE_kmod-b43)$(CONFIG_PACKAGE_b43legacy-firmware)$(CONFIG_BRCMSMAC_USE_FW_FROM_WL),)\n  BUILD_B43_TOOLS = y\nendif\n\ntools-y += autoconf autoconf-archive automake bc bison cmake cpio dosfstools\ntools-y += e2fsprogs fakeroot findutils firmware-utils flex gengetopt\ntools-y += libressl libtool lzma m4 make-ext4fs meson missing-macros mkimage\ntools-y += mklibs mtd-utils mtools ninja padjffs2 patch-image\ntools-y += patchelf pkgconf quilt squashfskit4 sstrip xxd zip zlib zstd\ntools-$(BUILD_B43_TOOLS) += b43-tools\ntools-$(BUILD_ISL) += isl\ntools-$(BUILD_TOOLCHAIN) += expat gmp mpc mpfr\ntools-$(CONFIG_TARGET_apm821xx)$(CONFIG_TARGET_gemini) += genext2fs\ntools-$(CONFIG_TARGET_ath79) += lzma-old squashfs\ntools-$(CONFIG_TARGET_mxs) += elftosb sdimage\ntools-$(CONFIG_TARGET_tegra) += cbootimage cbootimage-configs\ntools-$(CONFIG_USES_MINOR) += kernel2minor\ntools-$(CONFIG_USE_SPARSE) += sparse\ntools-$(CONFIG_USE_LLVM_BUILD) += llvm-bpf\n\n# builddir dependencies\n$(curdir)/autoconf/compile := $(curdir)/m4/compile\n$(curdir)/automake/compile := $(curdir)/m4/compile $(curdir)/autoconf/compile $(curdir)/pkgconf/compile $(curdir)/xz/compile\n$(curdir)/b43-tools/compile := $(curdir)/bison/compile\n$(curdir)/bc/compile := $(curdir)/bison/compile $(curdir)/libtool/compile\n$(curdir)/bison/compile := $(curdir)/flex/compile\n$(curdir)/cbootimage/compile += $(curdir)/automake/compile\n$(curdir)/cmake/compile += $(curdir)/libressl/compile $(curdir)/ninja/compile\n$(curdir)/dosfstools/compile := $(curdir)/autoconf/compile $(curdir)/automake/compile\n$(curdir)/expat/compile := $(curdir)/cmake/compile\n$(curdir)/e2fsprogs/compile := $(curdir)/libtool/compile\n$(curdir)/fakeroot/compile := $(curdir)/libtool/compile\n$(curdir)/findutils/compile := $(curdir)/bison/compile\n$(curdir)/firmware-utils/compile += $(curdir)/libressl/compile $(curdir)/zlib/compile\n$(curdir)/flex/compile := $(curdir)/libtool/compile\n$(curdir)/gengetopt/compile := $(curdir)/libtool/compile\n$(curdir)/gmp/compile := $(curdir)/libtool/compile\n$(curdir)/isl/compile := $(curdir)/gmp/compile\n$(curdir)/libressl/compile := $(curdir)/pkgconf/compile\n$(curdir)/libtool/compile := $(curdir)/m4/compile $(curdir)/autoconf/compile $(curdir)/automake/compile $(curdir)/missing-macros/compile\n$(curdir)/lzma-old/compile := $(curdir)/zlib/compile\n$(curdir)/llvm-bpf/compile := $(curdir)/cmake/compile\n$(curdir)/make-ext4fs/compile := $(curdir)/zlib/compile\n$(curdir)/meson/compile := $(curdir)/ninja/compile\n$(curdir)/missing-macros/compile := $(curdir)/autoconf/compile\n$(curdir)/mkimage/compile += $(curdir)/bison/compile $(curdir)/libressl/compile\n$(curdir)/mklibs/compile := $(curdir)/libtool/compile\n$(curdir)/mpc/compile := $(curdir)/mpfr/compile $(curdir)/gmp/compile\n$(curdir)/mpfr/compile := $(curdir)/gmp/compile\n$(curdir)/mtd-utils/compile := $(curdir)/libtool/compile $(curdir)/e2fsprogs/compile $(curdir)/zlib/compile\n$(curdir)/padjffs2/compile := $(curdir)/findutils/compile\n$(curdir)/patchelf/compile := $(curdir)/libtool/compile\n$(curdir)/pkgconf/compile := $(curdir)/meson/compile\n$(curdir)/quilt/compile := $(curdir)/autoconf/compile $(curdir)/findutils/compile\n$(curdir)/sdcc/compile := $(curdir)/bison/compile\n$(curdir)/squashfs/compile := $(curdir)/lzma-old/compile\n$(curdir)/squashfskit4/compile := $(curdir)/xz/compile $(curdir)/zlib/compile\n$(curdir)/zlib/compile := $(curdir)/cmake/compile\n$(curdir)/zstd/compile := $(curdir)/meson/compile\n\nifneq ($(HOST_OS),Linux)\n  $(curdir)/squashfskit4/compile += $(curdir)/coreutils/compile\n  tools-y += coreutils\nendif\nifeq ($(HOST_OS),Darwin)\n  tools-y += bash\nendif\n\nifneq ($(CONFIG_CCACHE)$(CONFIG_SDK),)\n$(foreach tool, $(filter-out xz zstd pkgconf patch ninja meson libressl cmake,$(tools-y)), $(eval $(curdir)/$(tool)/compile += $(curdir)/ccache/compile))\ntools-y += ccache\n$(curdir)/ccache/compile := $(curdir)/cmake/compile $(curdir)/zstd/compile\nendif\n\n# in case there is no patch tool on the host we need to make patch tool a\n# dependency for tools which have patches directory\n$(foreach tool, $(tools-y), $(if $(wildcard $(curdir)/$(tool)/patches),$(eval $(curdir)/$(tool)/compile += $(curdir)/patch/compile)))\n\n$(foreach tool, $(filter-out xz,$(tools-y)), $(eval $(curdir)/$(tool)/compile += $(curdir)/xz/compile))\n\n# make any tool depend on tar, xz and patch to ensure that archives can be unpacked and patched properly\ntools-core := tar xz patch\n\n$(foreach tool, $(tools-y), $(eval $(curdir)/$(tool)/compile += $(patsubst %,$(curdir)/%/compile,$(tools-core))))\ntools-y += $(tools-core)\n\n# make core tools depend on sed and flock\n$(foreach tool, $(filter-out xz,$(tools-core)), $(eval $(curdir)/$(tool)/compile += $(curdir)/sed/compile))\n$(curdir)/xz/compile += $(curdir)/flock/compile\n\n$(curdir)/sed/compile := $(curdir)/flock/compile $(curdir)/xz/compile\ntools-y += flock sed\n\n$(curdir)/autoremove := 1\n$(curdir)/builddirs := $(tools-y) $(tools-dep) $(tools-)\n$(curdir)/builddirs-default := $(tools-y)\n\nifdef CHECK_ALL\n$(curdir)/builddirs-check:=$($(curdir)/builddirs)\n$(curdir)/builddirs-download:=$($(curdir)/builddirs)\nendif\n\nifndef DUMP_TARGET_DB\ndefine PrepareStaging\n\t@for dir in $(1); do ( \\\n\t\t$(if $(QUIET),,set -x;) \\\n\t\tmkdir -p \"$$dir\"; \\\n\t\tcd \"$$dir\"; \\\n\t\tmkdir -p bin lib stamp usr/include usr/lib; \\\n\t); done\nendef\n\n$(BIN_DIR):\n\tmkdir -p $@\n\n# preparatory work\n$(STAGING_DIR)/.prepared: $(TMP_DIR)/.build\n\t$(call PrepareStaging,$(STAGING_DIR))\n\tmkdir -p $(BUILD_DIR)/stamp\n\ttouch $@\n\n$(STAGING_DIR_HOST)/.prepared: $(TMP_DIR)/.build\n\t$(call PrepareStaging,$(STAGING_DIR_HOST))\n\tmkdir -p $(BUILD_DIR_HOST)/stamp $(STAGING_DIR_HOST)/include/sys\n\t$(INSTALL_DATA) $(TOPDIR)/tools/include/*.h $(STAGING_DIR_HOST)/include/\n\t$(INSTALL_DATA) $(TOPDIR)/tools/include/sys/*.h $(STAGING_DIR_HOST)/include/sys/\nifneq ($(HOST_OS),Linux)\n\tmkdir -p $(STAGING_DIR_HOST)/include/asm\n\t$(INSTALL_DATA) $(TOPDIR)/tools/include/asm/*.h $(STAGING_DIR_HOST)/include/asm/\nendif\n\tln -snf lib $(STAGING_DIR_HOST)/lib64\n\ttouch $@\n\nendif\n\n$(curdir)//prepare = $(STAGING_DIR)/.prepared $(STAGING_DIR_HOST)/.prepared $(BIN_DIR)\n$(curdir)//compile = $(STAGING_DIR)/.prepared $(STAGING_DIR_HOST)/.prepared $(BIN_DIR)\n\n# prerequisites for the individual targets\n$(curdir)/ := .config prereq\n\n$(curdir)/install: $(curdir)/compile\n\ntools_enabled = $(foreach tool,$(sort $(tools-y) $(tools-)),$(if $(filter $(tool),$(tools-y)),y,n))\n$(eval $(call stampfile,$(curdir),tools,compile,,_$(subst $(space),,$(tools_enabled)),$(STAGING_DIR_HOST)))\n$(eval $(call stampfile,$(curdir),tools,check,$(TMP_DIR)/.build,,$(STAGING_DIR_HOST)))\n$(eval $(call subdir,$(curdir)))\n"
  },
  {
    "path": "tools/autoconf/Makefile",
    "content": "# \n# Copyright (C) 2006-2015 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=autoconf\nPKG_VERSION:=2.69\n\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz\nPKG_SOURCE_URL:=@GNU/autoconf\nPKG_HASH:=64ebcec9f8ac5b2487125a86a7760d2591ac9e1d3dbd59489633f9de62a57684\n\ninclude $(INCLUDE_DIR)/host-build.mk\n\nHOST_CONFIGURE_ARGS += \\\n\t--datarootdir=$(STAGING_DIR_HOST)/share\n\nHOST_CONFIGURE_VARS += \\\n\tPERL=\"/usr/bin/env perl\"\n\ndefine Host/Compile\n\texport SHELL=\"$(BASH)\"; $(MAKE) -C $(HOST_BUILD_DIR)\nendef\n\ndefine Host/Install\n\texport SHELL=\"$(BASH)\"; $(MAKE) -C $(HOST_BUILD_DIR) install\nendef\n\ndefine Host/Clean\n\t-export SHELL=\"$(BASH)\"; $(MAKE) -C $(HOST_BUILD_DIR) uninstall\n\t$(call Host/Clean/Default)\nendef\n\n$(eval $(call HostBuild))\n"
  },
  {
    "path": "tools/autoconf/patches/000-relocatable.patch",
    "content": "--- a/bin/autoheader.in\n+++ b/bin/autoheader.in\n@@ -28,7 +28,8 @@ eval 'case $# in 0) exec @PERL@ -S \"$0\";\n \n BEGIN\n {\n-  my $pkgdatadir = $ENV{'autom4te_perllibdir'} || '@pkgdatadir@';\n+  my $pkgdatadir = $ENV{'autom4te_perllibdir'} ||\n+\t($ENV{'STAGING_DIR'} ? $ENV{'STAGING_DIR'} . '/../host/share/autoconf' : '@pkgdatadir@');\n   unshift @INC, \"$pkgdatadir\";\n \n   # Override SHELL.  On DJGPP SHELL may not be set to a shell\n@@ -50,7 +51,7 @@ use strict;\n use vars qw ($config_h %verbatim %symbol);\n \n # Lib files.\n-my $autom4te = $ENV{'AUTOM4TE'} || '@bindir@/@autom4te-name@';\n+my $autom4te = $ENV{'AUTOM4TE'} || ($ENV{'STAGING_DIR'} ? $ENV{'STAGING_DIR'} . '/../host/bin/@autom4te-name@' : '@bindir@/@autom4te-name@');\n local $config_h;\n my $config_h_in;\n my @prepend_include;\n--- a/bin/autom4te.in\n+++ b/bin/autom4te.in\n@@ -1,10 +1,12 @@\n-#! @PERL@ -w\n+#! @PERL@\n # -*- perl -*-\n # @configure_input@\n \n eval 'case $# in 0) exec @PERL@ -S \"$0\";; *) exec @PERL@ -S \"$0\" \"$@\";; esac'\n     if 0;\n \n+$^W = 1;\n+\n # autom4te - Wrapper around M4 libraries.\n # Copyright (C) 2001-2003, 2005-2012 Free Software Foundation, Inc.\n \n@@ -24,7 +26,8 @@ eval 'case $# in 0) exec @PERL@ -S \"$0\";\n \n BEGIN\n {\n-  my $pkgdatadir = $ENV{'autom4te_perllibdir'} || '@pkgdatadir@';\n+  my $pkgdatadir = $ENV{'autom4te_perllibdir'} ||\n+\t($ENV{'STAGING_DIR'} ? $ENV{'STAGING_DIR'} . '/../host/share/autoconf' : '@pkgdatadir@');\n   unshift @INC, $pkgdatadir;\n \n   # Override SHELL.  On DJGPP SHELL may not be set to a shell\n@@ -44,7 +47,8 @@ use File::Basename;\n use strict;\n \n # Data directory.\n-my $pkgdatadir = $ENV{'AC_MACRODIR'} || '@pkgdatadir@';\n+my $pkgdatadir = $ENV{'AC_MACRODIR'} ||\n+\t($ENV{'STAGING_DIR'} ? $ENV{'STAGING_DIR'} . '/../host/share/autoconf' : '@pkgdatadir@');\n \n # $LANGUAGE{LANGUAGE} -- Automatic options for LANGUAGE.\n my %language;\n@@ -87,7 +91,7 @@ my @include;\n my $freeze = 0;\n \n # $M4.\n-my $m4 = $ENV{\"M4\"} || '@M4@';\n+my $m4 = $ENV{\"M4\"} || ($ENV{'STAGING_DIR'} ? $ENV{'STAGING_DIR'} . '/../host/bin/m4' : '@M4@');\n # Some non-GNU m4's don't reject the --help option, so give them /dev/null.\n fatal \"need GNU m4 1.4 or later: $m4\"\n   if system \"$m4 --help </dev/null 2>&1 | grep reload-state >/dev/null\";\n@@ -269,6 +273,12 @@ sub load_configuration ($)\n \n       my @words = shellwords ($_);\n       my $type = shift @words;\n+\n+      if ($ENV{'STAGING_DIR'})\n+      {\n+        @words = map { s!^@pkgdatadir@!$ENV{'STAGING_DIR'}/../host/share/autoconf!; $_ } @words;\n+      }\n+\n       if ($type eq 'begin-language:')\n \t{\n \t  fatal \"$file:$.: end-language missing for: $lang\"\n--- a/bin/autoreconf.in\n+++ b/bin/autoreconf.in\n@@ -1,10 +1,12 @@\n-#! @PERL@ -w\n+#! @PERL@\n # -*- perl -*-\n # @configure_input@\n \n eval 'case $# in 0) exec @PERL@ -S \"$0\";; *) exec @PERL@ -S \"$0\" \"$@\";; esac'\n     if 0;\n \n+$^W = 1;\n+\n # autoreconf - install the GNU Build System in a directory tree\n # Copyright (C) 1994, 1999-2012 Free Software Foundation, Inc.\n \n@@ -26,7 +28,8 @@ eval 'case $# in 0) exec @PERL@ -S \"$0\";\n \n BEGIN\n {\n-  my $pkgdatadir = $ENV{'autom4te_perllibdir'} || '@pkgdatadir@';\n+  my $pkgdatadir = $ENV{'autom4te_perllibdir'} ||\n+\t($ENV{'STAGING_DIR'} ? $ENV{'STAGING_DIR'} . '/../host/share/autoconf' : '@pkgdatadir@');\n   unshift @INC, $pkgdatadir;\n \n   # Override SHELL.  On DJGPP SHELL may not be set to a shell\n@@ -106,9 +109,9 @@ Written by David J. MacKenzie and Akim D\n \";\n \n # Lib files.\n-my $autoconf   = $ENV{'AUTOCONF'}   || '@bindir@/@autoconf-name@';\n-my $autoheader = $ENV{'AUTOHEADER'} || '@bindir@/@autoheader-name@';\n-my $autom4te   = $ENV{'AUTOM4TE'}   || '@bindir@/@autom4te-name@';\n+my $autoconf   = $ENV{'AUTOCONF'}   || ($ENV{'STAGING_DIR'} ? $ENV{'STAGING_DIR'} . '/../host/bin/@autoconf-name@' : '@bindir@/@autoconf-name@');\n+my $autoheader = $ENV{'AUTOHEADER'} || ($ENV{'STAGING_DIR'} ? $ENV{'STAGING_DIR'} . '/../host/bin/@autoheader-name@' : '@bindir@/@autoheader-name@');\n+my $autom4te   = $ENV{'AUTOM4TE'}   || ($ENV{'STAGING_DIR'} ? $ENV{'STAGING_DIR'} . '/../host/bin/@autom4te-name@' : '@bindir@/@autom4te-name@');\n my $automake   = $ENV{'AUTOMAKE'}   || 'automake';\n my $aclocal    = $ENV{'ACLOCAL'}    || 'aclocal';\n my $libtoolize = $ENV{'LIBTOOLIZE'} || 'libtoolize';\n--- a/bin/autoscan.in\n+++ b/bin/autoscan.in\n@@ -1,4 +1,4 @@\n-#! @PERL@ -w\n+#! @PERL@\n # -*- perl -*-\n # @configure_input@\n \n@@ -23,9 +23,12 @@\n eval 'case $# in 0) exec @PERL@ -S \"$0\";; *) exec @PERL@ -S \"$0\" \"$@\";; esac'\n     if 0;\n \n+$^W = 1;\n+\n BEGIN\n {\n-  my $pkgdatadir = $ENV{'autom4te_perllibdir'} || '@pkgdatadir@';\n+  my $pkgdatadir = $ENV{'autom4te_perllibdir'} ||\n+\t($ENV{'STAGING_DIR'} ? $ENV{'STAGING_DIR'} . '/../host/share/autoconf' : '@pkgdatadir@');\n   unshift @INC, $pkgdatadir;\n \n   # Override SHELL.  On DJGPP SHELL may not be set to a shell\n@@ -91,10 +94,10 @@ my $configure_scan = 'configure.scan';\n my $log;\n \n # Autoconf and lib files.\n-my $autom4te = $ENV{'AUTOM4TE'} || '@bindir@/@autom4te-name@';\n+my $autom4te = $ENV{'AUTOM4TE'} || ($ENV{'STAGING_DIR'} ? $ENV{'STAGING_DIR'} . '/../host/bin/@autom4te-name@' : '@bindir@/@autom4te-name@');\n my $autoconf = \"$autom4te --language=autoconf\";\n my @prepend_include;\n-my @include = ('@pkgdatadir@');\n+my @include = ($ENV{'STAGING_DIR'} ? $ENV{'STAGING_DIR'} . '/../host/share/autoconf' : '@pkgdatadir@');\n \n # $help\n # -----\n--- a/bin/autoupdate.in\n+++ b/bin/autoupdate.in\n@@ -1,4 +1,4 @@\n-#! @PERL@ -w\n+#! @PERL@\n # -*- perl -*-\n # @configure_input@\n \n@@ -24,9 +24,12 @@\n eval 'case $# in 0) exec @PERL@ -S \"$0\";; *) exec @PERL@ -S \"$0\" \"$@\";; esac'\n     if 0;\n \n+$^W = 1;\n+\n BEGIN\n {\n-  my $pkgdatadir = $ENV{'autom4te_perllibdir'} || '@pkgdatadir@';\n+  my $pkgdatadir = $ENV{'autom4te_perllibdir'} ||\n+\t($ENV{'STAGING_DIR'} ? $ENV{'STAGING_DIR'} . '/../host/share/autoconf' : '@pkgdatadir@');\n   unshift @INC, $pkgdatadir;\n \n   # Override SHELL.  On DJGPP SHELL may not be set to a shell\n@@ -50,10 +53,10 @@ my $autom4te = $ENV{'AUTOM4TE'} || '@bin\n my $autoconf = \"$autom4te --language=autoconf\";\n # We need to find m4sugar.\n my @prepend_include;\n-my @include = ('@pkgdatadir@');\n+my @include = ($ENV{'STAGING_DIR'} ? $ENV{'STAGING_DIR'} . '/../host/share/autoconf' : '@pkgdatadir@');\n my $force = 0;\n # m4.\n-my $m4 = $ENV{\"M4\"} || '@M4@';\n+my $m4 = $ENV{\"M4\"} || ($ENV{'STAGING_DIR'} ? $ENV{'STAGING_DIR'} . '/../host/bin/m4' : '@M4@');\n \n \n # $HELP\n--- a/bin/ifnames.in\n+++ b/bin/ifnames.in\n@@ -1,10 +1,12 @@\n-#! @PERL@ -w\n+#! @PERL@\n # -*- perl -*-\n # @configure_input@\n \n eval 'case $# in 0) exec @PERL@ -S \"$0\";; *) exec @PERL@ -S \"$0\" \"$@\";; esac'\n     if 0;\n \n+$^W = 1;\n+\n # ifnames - print the identifiers used in C preprocessor conditionals\n \n # Copyright (C) 1994-1995, 1999-2003, 2005-2012 Free Software\n@@ -31,7 +33,8 @@ eval 'case $# in 0) exec @PERL@ -S \"$0\";\n \n BEGIN\n {\n-  my $pkgdatadir = $ENV{'autom4te_perllibdir'} || '@pkgdatadir@';\n+  my $pkgdatadir = $ENV{'autom4te_perllibdir'} ||\n+\t($ENV{'STAGING_DIR'} ? $ENV{'STAGING_DIR'} . '/../host/share/autoconf' : '@pkgdatadir@');\n   unshift @INC, $pkgdatadir;\n \n   # Override SHELL.  On DJGPP SHELL may not be set to a shell\n--- a/bin/autoconf.as\n+++ b/bin/autoconf.as\n@@ -84,7 +84,11 @@ exit_missing_arg='\n # restore font-lock: '\n \n # Variables.\n-: ${AUTOM4TE='@bindir@/@autom4te-name@'}\n+if test -n \"$STAGING_DIR\"; then\n+\t: ${AUTOM4TE=\"$STAGING_DIR/../host/bin/@autom4te-name@\"}\n+else\n+\t: ${AUTOM4TE='@bindir@/@autom4te-name@'}\n+fi\n autom4te_options=\n outfile=\n verbose=false\n"
  },
  {
    "path": "tools/autoconf/patches/001-no_emacs_lib.patch",
    "content": "--- a/lib/Makefile.am\n+++ b/lib/Makefile.am\n@@ -15,7 +15,7 @@\n # You should have received a copy of the GNU General Public License\n # along with this program.  If not, see <http://www.gnu.org/licenses/>.\n \n-SUBDIRS = Autom4te m4sugar autoconf autotest autoscan emacs\n+SUBDIRS = Autom4te m4sugar autoconf autotest autoscan\n nodist_pkgdata_DATA = autom4te.cfg\n EXTRA_DIST = autom4te.in freeze.mk\n \n--- a/lib/Makefile.in\n+++ b/lib/Makefile.in\n@@ -225,7 +225,7 @@ target_alias = @target_alias@\n top_build_prefix = @top_build_prefix@\n top_builddir = @top_builddir@\n top_srcdir = @top_srcdir@\n-SUBDIRS = Autom4te m4sugar autoconf autotest autoscan emacs\n+SUBDIRS = Autom4te m4sugar autoconf autotest autoscan\n nodist_pkgdata_DATA = autom4te.cfg\n EXTRA_DIST = autom4te.in freeze.mk\n edit = sed \\\n"
  },
  {
    "path": "tools/autoconf/patches/002-musl_host_fixup.patch",
    "content": "--- a/build-aux/config.sub\n+++ b/build-aux/config.sub\n@@ -122,9 +122,9 @@ esac\n # Here we must recognize all the valid KERNEL-OS combinations.\n maybe_os=`echo $1 | sed 's/^\\(.*\\)-\\([^-]*-[^-]*\\)$/\\2/'`\n case $maybe_os in\n-  nto-qnx* | linux-gnu* | linux-android* | linux-dietlibc | linux-newlib* | \\\n-  linux-uclibc* | uclinux-uclibc* | uclinux-gnu* | kfreebsd*-gnu* | \\\n-  knetbsd*-gnu* | netbsd*-gnu* | \\\n+  nto-qnx* | linux-gnu* | linux-android* | linux-dietlibc | linux-musl* | \\\n+  linux-newlib* | linux-uclibc* | uclinux-uclibc* | uclinux-gnu* | \\\n+  kfreebsd*-gnu* | knetbsd*-gnu* | netbsd*-gnu* | \\\n   kopensolaris*-gnu* | \\\n   storm-chaos* | os2-emx* | rtmk-nova*)\n     os=-$maybe_os\n@@ -1360,7 +1360,7 @@ case $os in\n \t      | -chorusos* | -chorusrdb* | -cegcc* \\\n \t      | -cygwin* | -msys* | -pe* | -psos* | -moss* | -proelf* | -rtems* \\\n \t      | -mingw32* | -linux-gnu* | -linux-android* \\\n-\t      | -linux-newlib* | -linux-uclibc* \\\n+\t      | -linux-musl* | -linux-newlib* | -linux-uclibc* \\\n \t      | -uxpv* | -beos* | -mpeix* | -udk* \\\n \t      | -interix* | -uwin* | -mks* | -rhapsody* | -darwin* | -opened* \\\n \t      | -openstep* | -oskit* | -conix* | -pw32* | -nonstopux* \\\n"
  },
  {
    "path": "tools/autoconf-archive/Makefile",
    "content": "include $(TOPDIR)/rules.mk\n\nPKG_NAME:=autoconf-archive\nPKG_VERSION:=2021.02.19\n\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz\nPKG_SOURCE_URL:=@GNU/autoconf-archive\nPKG_HASH:=e8a6eb9d28ddcba8ffef3fa211653239e9bf239aba6a01a6b7cfc7ceaec69cbd\n\ninclude $(INCLUDE_DIR)/host-build.mk\n\nHOST_CONFIGURE_ARGS += \\\n\t--datarootdir=$(STAGING_DIR_HOST)/share\n\ndefine Host/Compile\n\texport SHELL=\"$(BASH)\"; $(MAKE) -C $(HOST_BUILD_DIR)\nendef\n\ndefine Host/Install\n\texport SHELL=\"$(BASH)\"; $(MAKE) -C $(HOST_BUILD_DIR) install\nendef\n\ndefine Host/Clean\n\t-export SHELL=\"$(BASH)\"; $(MAKE) -C $(HOST_BUILD_DIR) uninstall\n\t$(call Host/Clean/Default)\nendef\n\n$(eval $(call HostBuild))\n"
  },
  {
    "path": "tools/automake/Makefile",
    "content": "#\n# Copyright (C) 2006-2015 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=automake\nPKG_CPE_ID:=cpe:/a:gnu:automake\nPKG_VERSION:=1.15.1\n\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz\nPKG_SOURCE_URL:=@GNU/automake\nPKG_HASH:=af6ba39142220687c500f79b4aa2f181d9b24e4f8d8ec497cea4ba26c64bedaf\n\ninclude $(INCLUDE_DIR)/host-build.mk\n\nHOST_CONFIGURE_ARGS += \\\n\t--datarootdir=$(STAGING_DIR_HOST)/share \\\n\t--disable-silent-rules\n\nHOST_CONFIGURE_VARS += \\\n\tPERL=\"/usr/bin/env perl\" \\\n\tam_cv_prog_PERL_ithreads=no\n\ndefine Host/Configure\n\t(cd $(HOST_BUILD_DIR); $(AM_TOOL_PATHS) STAGING_DIR=\"\" ./bootstrap)\n\t$(call Host/Configure/Default)\nendef\n\ndefine Host/Install\n\t# remove old automake resources to avoid version conflicts\n\trm -rf $(STAGING_DIR_HOST)/share/aclocal-[0-9]*\n\trm -rf $(STAGING_DIR_HOST)/share/automake-[0-9]*\n\t$(MAKE) -C $(HOST_BUILD_DIR) install\n\tmv $(STAGING_DIR_HOST)/bin/aclocal $(STAGING_DIR_HOST)/bin/aclocal.real\n\t$(INSTALL_BIN) ./files/aclocal $(STAGING_DIR_HOST)/bin\n\tln -sf aclocal $(STAGING_DIR_HOST)/bin/aclocal-1.9\n\tln -sf aclocal $(STAGING_DIR_HOST)/bin/aclocal-1.10\n\tln -sf aclocal $(STAGING_DIR_HOST)/bin/aclocal-1.11\n\tln -sf aclocal $(STAGING_DIR_HOST)/bin/aclocal-1.11.6\n\tln -sf aclocal $(STAGING_DIR_HOST)/bin/aclocal-1.15\nendef\n\ndefine Host/Clean\n\t-$(MAKE) -C $(HOST_BUILD_DIR) uninstall\n\t$(call Host/Clean/Default)\nendef\n\n$(eval $(call HostBuild))\n"
  },
  {
    "path": "tools/automake/files/aclocal",
    "content": "#!/usr/bin/env sh\naclocal.real $ACLOCAL_INCLUDE $@\n"
  },
  {
    "path": "tools/automake/patches/000-relocatable.patch",
    "content": "--- a/lib/Automake/Config.in\n+++ b/lib/Automake/Config.in\n@@ -32,7 +32,7 @@ our $PACKAGE = '@PACKAGE@';\n our $PACKAGE_BUGREPORT = '@PACKAGE_BUGREPORT@';\n our $VERSION = '@VERSION@';\n our $RELEASE_YEAR = '@RELEASE_YEAR@';\n-our $libdir = '@datadir@/@PACKAGE@-@APIVERSION@';\n+our $libdir = $ENV{'STAGING_DIR'} ? $ENV{'STAGING_DIR'} . '/../host/share/@PACKAGE@-@APIVERSION@' : '@datadir@/@PACKAGE@-@APIVERSION@';\n \n our $perl_threads = 0;\n # We need at least this version for CLONE support.\n--- a/bin/aclocal.in\n+++ b/bin/aclocal.in\n@@ -1,10 +1,12 @@\n-#!@PERL@ -w\n+#!@PERL@\n # -*- perl -*-\n # @configure_input@\n \n eval 'case $# in 0) exec @PERL@ -S \"$0\";; *) exec @PERL@ -S \"$0\" \"$@\";; esac'\n     if 0;\n \n+$^W = 1;\n+\n # aclocal - create aclocal.m4 by scanning configure.ac\n \n # Copyright (C) 1996-2017 Free Software Foundation, Inc.\n@@ -27,7 +29,7 @@ eval 'case $# in 0) exec @PERL@ -S \"$0\";\n \n BEGIN\n {\n-  @Aclocal::perl_libdirs = ('@datadir@/@PACKAGE@-@APIVERSION@')\n+  @Aclocal::perl_libdirs = ($ENV{'STAGING_DIR'} ? $ENV{'STAGING_DIR'} . '/../host/share/@PACKAGE@-@APIVERSION@' : '@datadir@/@PACKAGE@-@APIVERSION@')\n     unless @Aclocal::perl_libdirs;\n   unshift @INC, @Aclocal::perl_libdirs;\n }\n@@ -69,8 +71,8 @@ $perl_threads = 0;\n # ACLOCAL_PATH environment variable, and reset with the '--system-acdir'\n # option.\n my @user_includes = ();\n-my @automake_includes = (\"@datadir@/aclocal-$APIVERSION\");\n-my @system_includes = ('@datadir@/aclocal');\n+my @automake_includes = ($ENV{'STAGING_DIR'} ? $ENV{'STAGING_DIR'} . \"/../host/share/aclocal-$APIVERSION\" : \"@datadir@/aclocal-$APIVERSION\");\n+my @system_includes = ($ENV{'STAGING_DIR'} ? $ENV{'STAGING_DIR'} . '/../host/share/aclocal' : '@datadir@/aclocal');\n \n # Whether we should copy M4 file in $user_includes[0].\n my $install = 0;\n--- a/bin/automake.in\n+++ b/bin/automake.in\n@@ -1,10 +1,12 @@\n-#!@PERL@ -w\n+#!@PERL@\n # -*- perl -*-\n # @configure_input@\n \n eval 'case $# in 0) exec @PERL@ -S \"$0\";; *) exec @PERL@ -S \"$0\" \"$@\";; esac'\n     if 0;\n \n+$^W = 1;\n+\n # automake - create Makefile.in from Makefile.am\n # Copyright (C) 1994-2017 Free Software Foundation, Inc.\n \n@@ -31,7 +33,7 @@ use strict;\n \n BEGIN\n {\n-  @Automake::perl_libdirs = ('@datadir@/@PACKAGE@-@APIVERSION@')\n+  @Automake::perl_libdirs = ($ENV{'STAGING_DIR'} ? $ENV{'STAGING_DIR'} . '/../host/share/@PACKAGE@-@APIVERSION@' : '@datadir@/@PACKAGE@-@APIVERSION@')\n     unless @Automake::perl_libdirs;\n   unshift @INC, @Automake::perl_libdirs;\n \n--- a/t/wrap/aclocal.in\n+++ b/t/wrap/aclocal.in\n@@ -1,6 +1,8 @@\n-#!@PERL@ -w\n+#!@PERL@\n # @configure_input@\n \n+$^W = 1;\n+\n # Copyright (C) 2012-2017 Free Software Foundation, Inc.\n \n # This program is free software; you can redistribute it and/or modify\n--- a/t/wrap/automake.in\n+++ b/t/wrap/automake.in\n@@ -1,6 +1,8 @@\n-#!@PERL@ -w\n+#!@PERL@\n # @configure_input@\n \n+$^W = 1;\n+\n # Copyright (C) 2012-2017 Free Software Foundation, Inc.\n \n # This program is free software; you can redistribute it and/or modify\n"
  },
  {
    "path": "tools/automake/patches/100-aclocal-skip-not-existing-directories.patch",
    "content": "--- a/bin/aclocal.in\n+++ b/bin/aclocal.in\n@@ -356,6 +356,12 @@ sub scan_m4_dirs ($$@)\n \n   foreach my $m4dir (@dirlist)\n     {\n+      if (! -d $m4dir)\n+        {\n+          msg ('override', \"warning: skipping not existing directory `$m4dir'\");\n+          next;\n+        }\n+\n       if (! opendir (DIR, $m4dir))\n \t{\n \t  # TODO: maybe avoid complaining only if errno == ENONENT?\n"
  },
  {
    "path": "tools/b43-tools/Makefile",
    "content": "#\n# Copyright (C) 2012 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=b43-tools\nPKG_DATE:=2017-09-13\n\nPKG_SOURCE_URL:=https://github.com/mbuesch/b43-tools.git\nPKG_SOURCE_PROTO:=git\nPKG_SOURCE_SUBDIR:=$(PKG_NAME)\nPKG_SOURCE_VERSION:=27892ef741e7f1d08cb939744f8b8f5dac7b04ae\nPKG_MIRROR_HASH:=f914c36ac566e9e3b5a3a04de16ddb014fcad6a1cf25cdd8e4825c708d28d3f4\nHOST_BUILD_DIR=$(BUILD_DIR_HOST)/$(PKG_NAME)\n\ninclude $(INCLUDE_DIR)/host-build.mk\n\n\ndefine Host/Compile\n\t+$(MAKE) $(HOST_JOBS) -C $(HOST_BUILD_DIR)/fwcutter \\\n\t\tCFLAGS=\"$(HOST_CFLAGS) -include endian.h\" \\\n\t\t$(HOST_MAKE_FLAGS) \\\n\t\t$(1) QUIET_SPARSE=:\n\t+$(MAKE) $(HOST_JOBS) -C $(HOST_BUILD_DIR)/assembler \\\n\t\tCFLAGS=\"$(HOST_CFLAGS) -include endian.h\" \\\n\t\t$(HOST_MAKE_FLAGS) \\\n\t\tLDFLAGS= \\\n\t\t$(1) QUIET_SPARSE=:\nendef\n\ndefine Host/Install\n\t$(INSTALL_DIR) $(STAGING_DIR_HOST)/bin\n\t$(INSTALL_BIN) $(HOST_BUILD_DIR)/fwcutter/b43-fwcutter $(STAGING_DIR_HOST)/bin/\n\t$(INSTALL_BIN) $(HOST_BUILD_DIR)/assembler/b43-asm $(STAGING_DIR_HOST)/bin/\n\t$(INSTALL_BIN) $(HOST_BUILD_DIR)/assembler/b43-asm.bin $(STAGING_DIR_HOST)/bin/\n\t$(INSTALL_BIN) ./files/b43-fwsquash.py $(STAGING_DIR_HOST)/bin/\nendef\n\ndefine Host/Clean\n\trm -f $(STAGING_DIR_HOST)/bin/b43-fwcutter\n\trm -f $(STAGING_DIR_HOST)/bin/b43-asm\n\trm -f $(STAGING_DIR_HOST)/bin/b43-asm.bin\n\trm -f $(STAGING_DIR_HOST)/bin/b43-fwsquash.py\nendef\n\n$(eval $(call HostBuild))\n"
  },
  {
    "path": "tools/b43-tools/files/b43-fwsquash.py",
    "content": "#!/usr/bin/env python3\n#\n# b43 firmware file squasher\n# Removes unnecessary firmware files\n#\n# Copyright (c) 2009 Michael Buesch <mb@bu3sch.de>\n#\n# Licensed under the GNU/GPL version 2 or (at your option) any later version.\n#\n\nimport sys\nimport os\n\ndef usage():\n\tprint(\"Usage: %s PHYTYPES COREREVS /path/to/extracted/firmware\" % sys.argv[0])\n\tprint(\"\")\n\tprint(\"PHYTYPES is a comma separated list of:\")\n\tprint(\"A         => A-PHY\")\n\tprint(\"AG        => Dual A-PHY G-PHY\")\n\tprint(\"G         => G-PHY\")\n\tprint(\"LP        => LP-PHY\")\n\tprint(\"N         => N-PHY\")\n\tprint(\"HT        => HT-PHY\")\n\tprint(\"LCN       => LCN-PHY\")\n\tprint(\"LCN40     => LCN40-PHY\")\n\tprint(\"AC        => AC-PHY\")\n\tprint(\"\")\n\tprint(\"COREREVS is a comma separated list of core revision numbers.\")\n\nif len(sys.argv) != 4:\n\tusage()\n\tsys.exit(1)\n\nphytypes = sys.argv[1]\ncorerevs = sys.argv[2]\nfwpath = sys.argv[3]\n\nphytypes = phytypes.split(',')\ntry:\n\tcorerevs = [int(r) for r in corerevs.split(',')]\nexcept ValueError:\n\tprint(\"ERROR: \\\"%s\\\" is not a valid COREREVS string\\n\" % corerevs)\n\tusage()\n\tsys.exit(1)\n\n\nfwfiles = os.listdir(fwpath)\nfwfiles = [str for str in fwfiles if str.endswith(\".fw\")]\nif not fwfiles:\n\tprint(\"ERROR: No firmware files found in %s\" % fwpath)\n\tsys.exit(1)\n\nrequired_fwfiles = []\n\ndef revs_match(revs_a, revs_b):\n\tfor rev in revs_a:\n\t\tif rev in revs_b:\n\t\t\treturn True\n\treturn False\n\ndef phytypes_match(types_a, types_b):\n\tfor type in types_a:\n\t\ttype = type.strip().upper()\n\t\tif type in types_b:\n\t\t\treturn True\n\treturn False\n\nrevmapping = {\n\t\"ucode2.fw\"\t\t: ( (2,3,),\t\t(\"G\",), ),\n\t\"ucode4.fw\"\t\t: ( (4,),\t\t(\"G\",), ),\n\t\"ucode5.fw\"\t\t: ( (5,6,7,8,9,10,),\t(\"G\",\"A\",\"AG\",), ),\n\t\"ucode11.fw\"\t\t: ( (11,12,),\t\t(\"N\",), ),\n\t\"ucode13.fw\"\t\t: ( (13,),\t\t(\"LP\",\"G\",), ),\n\t\"ucode14.fw\"\t\t: ( (14,),\t\t(\"LP\",), ),\n\t\"ucode15.fw\"\t\t: ( (15,),\t\t(\"LP\",), ),\n\t\"ucode16_mimo.fw\"\t: ( (16,17,18,19,23,),\t(\"N\",), ),\n#\t\"ucode16_lp.fw\"\t\t: ( (16,17,18,19,),\t(\"LP\",), ),\n\t\"ucode24_lcn.fw\"\t: ( (24,),\t\t(\"LCN\",), ),\n\t\"ucode25_mimo.fw\"\t: ( (25,28,),\t\t(\"N\",), ),\n\t\"ucode25_lcn.fw\"\t: ( (25,28,),\t\t(\"LCN\",), ),\n\t\"ucode26_mimo.fw\"\t: ( (26,),\t\t(\"HT\",), ),\n\t\"ucode29_mimo.fw\"\t: ( (29,),\t\t(\"HT\",), ),\n\t\"ucode30_mimo.fw\"\t: ( (30,),\t\t(\"N\",), ),\n\t\"ucode33_lcn40.fw\"\t: ( (33,),\t\t(\"LCN40\",), ),\n\t\"ucode40.fw\"\t\t: ( (40,),\t\t(\"AC\",), ),\n\t\"ucode42.fw\"\t\t: ( (42,),\t\t(\"AC\",), ),\n\t\"pcm4.fw\"\t\t: ( (1,2,3,4,),\t\t(\"G\",), ),\n\t\"pcm5.fw\"\t\t: ( (5,6,7,8,9,10,),\t(\"G\",\"A\",\"AG\",), ),\n}\n\ninitvalmapping = {\n\t\"a0g1initvals5.fw\"\t: ( (5,6,7,8,9,10,),\t(\"AG\",), ),\n\t\"a0g0initvals5.fw\"\t: ( (5,6,7,8,9,10,),\t(\"A\", \"AG\",), ),\n\t\"b0g0initvals2.fw\"\t: ( (2,4,),\t\t(\"G\",), ),\n\t\"b0g0initvals5.fw\"\t: ( (5,6,7,8,9,10,),\t(\"G\",), ),\n\t\"b0g0initvals13.fw\"\t: ( (13,),\t\t(\"G\",), ),\n\t\"n0initvals11.fw\"\t: ( (11,12,),\t\t(\"N\",), ),\n\t\"n0initvals16.fw\"\t: ( (16,17,18,23,),\t(\"N\",), ),\n\t\"n0initvals24.fw\"\t: ( (24,),\t\t(\"N\",), ),\n\t\"n0initvals25.fw\"\t: ( (25,28,),\t\t(\"N\",), ),\n\t\"n16initvals30.fw\"\t: ( (30,),\t\t(\"N\",), ),\n\t\"lp0initvals13.fw\"\t: ( (13,),\t\t(\"LP\",), ),\n\t\"lp0initvals14.fw\"\t: ( (14,),\t\t(\"LP\",), ),\n\t\"lp0initvals15.fw\"\t: ( (15,),\t\t(\"LP\",), ),\n#\t\"lp0initvals16.fw\"\t: ( (16,17,18,),\t(\"LP\",), ),\n\t\"lcn0initvals24.fw\"\t: ( (24,),\t\t(\"LCN\",), ),\n\t\"ht0initvals26.fw\"\t: ( (26,),\t\t(\"HT\",), ),\n\t\"ht0initvals29.fw\"\t: ( (29,),\t\t(\"HT\",), ),\n\t\"lcn400initvals33.fw\"\t: ( (33,),\t\t(\"LCN40\",), ),\n\t\"ac0initvals40.fw\"\t: ( (40,),\t\t(\"AC\",), ),\n\t\"ac1initvals42.fw\"\t: ( (42,),\t\t(\"AC\",), ),\n\t\"a0g1bsinitvals5.fw\"\t: ( (5,6,7,8,9,10,),\t(\"AG\",), ),\n\t\"a0g0bsinitvals5.fw\"\t: ( (5,6,7,8,9,10,),\t(\"A\", \"AG\"), ),\n\t\"b0g0bsinitvals5.fw\"\t: ( (5,6,7,8,9,10,),\t(\"G\",), ),\n\t\"n0bsinitvals11.fw\"\t: ( (11,12,),\t\t(\"N\",), ),\n\t\"n0bsinitvals16.fw\"\t: ( (16,17,18,23,),\t(\"N\",), ),\n\t\"n0bsinitvals24.fw\"\t: ( (24,),\t\t(\"N\",), ),\n\t\"n0bsinitvals25.fw\"\t: ( (25,28,),\t\t(\"N\",), ),\n\t\"n16bsinitvals30.fw\"\t: ( (30,),\t\t(\"N\",), ),\n\t\"lp0bsinitvals13.fw\"\t: ( (13,),\t\t(\"LP\",), ),\n\t\"lp0bsinitvals14.fw\"\t: ( (14,),\t\t(\"LP\",), ),\n\t\"lp0bsinitvals15.fw\"\t: ( (15,),\t\t(\"LP\",), ),\n#\t\"lp0bsinitvals16.fw\"\t: ( (16,17,18,),\t(\"LP\",), ),\n\t\"lcn0bsinitvals24.fw\"\t: ( (24,),\t\t(\"LCN\",), ),\n\t\"ht0bsinitvals26.fw\"\t: ( (26,),\t\t(\"HT\",), ),\n\t\"ht0bsinitvals29.fw\"\t: ( (29,),\t\t(\"HT\",), ),\n\t\"lcn400bsinitvals33.fw\"\t: ( (33,),\t\t(\"LCN40\",), ),\n\t\"ac0bsinitvals40.fw\"\t: ( (40,),\t\t(\"AC\",), ),\n\t\"ac1bsinitvals42.fw\"\t: ( (42,),\t\t(\"AC\",), ),\n}\n\nfor f in fwfiles:\n\tif f in revmapping:\n\t\tif revs_match(corerevs, revmapping[f][0]) and\\\n\t\t   phytypes_match(phytypes, revmapping[f][1]):\n\t\t\trequired_fwfiles += [f]\n\t\tcontinue\n\tif f in initvalmapping:\n\t\tif revs_match(corerevs, initvalmapping[f][0]) and\\\n\t\t   phytypes_match(phytypes, initvalmapping[f][1]):\n\t\t\trequired_fwfiles += [f]\n\t\tcontinue\n\tprint(\"WARNING: Firmware file %s not found in the mapping lists\" % f)\n\nfor f in fwfiles:\n\tif f not in required_fwfiles:\n\t\tprint(\"Deleting %s\" % f)\n\t\tos.unlink(fwpath + '/' + f)\n\n"
  },
  {
    "path": "tools/b43-tools/patches/001-fw-dirname.patch",
    "content": "--- a/fwcutter/fwcutter.c\n+++ b/fwcutter/fwcutter.c\n@@ -50,13 +50,8 @@\n #include \"fwcutter.h\"\n #include \"fwcutter_list.h\"\n \n-#if defined(__DragonFly__) || defined(__FreeBSD__)\n-#define V3_FW_DIRNAME\t\"v3\"\n-#define V4_FW_DIRNAME\t\"v4\"\n-#else\n #define V3_FW_DIRNAME\t\"b43legacy\"\n #define V4_FW_DIRNAME\t\"b43\"\n-#endif\n \n static struct cmdline_args cmdargs;\n \n"
  },
  {
    "path": "tools/b43-tools/patches/002-no_libfl.patch",
    "content": "--- a/assembler/main.c\n+++ b/assembler/main.c\n@@ -1268,6 +1268,11 @@ static void initialize(void)\n #endif /* YYDEBUG */\n }\n \n+int yywrap(void)\n+{\n+\treturn 1;\n+}\n+\n int main(int argc, char **argv)\n {\n \tint err, res = 1;\n"
  },
  {
    "path": "tools/bash/Makefile",
    "content": "#\n# Copyright (C) 2015 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=bash\nPKG_CPE_ID:=cpe:/a:gnu:bash\nPKG_VERSION:=5.1.16\n\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz\nPKG_SOURCE_URL:=@GNU/bash\nPKG_HASH:=5bac17218d3911834520dad13cd1f85ab944e1c09ae1aba55906be1f8192f558\n\nHOST_BUILD_PARALLEL := 1\n\ninclude $(INCLUDE_DIR)/host-build.mk\n\n$(eval $(call HostBuild))\n"
  },
  {
    "path": "tools/bc/Makefile",
    "content": "# \n# Copyright (C) 2013-2022 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=bc\nPKG_VERSION:=1.06.95\n\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.bz2\nPKG_SOURCE_URL:=https://alpha.gnu.org/gnu/bc \\\n\thttps://gnualpha.uib.no/bc/ \\\n\thttps://mirrors.fe.up.pt/pub/gnu-alpha/bc/ \\\n\thttps://www.nic.funet.fi/pub/gnu/alpha/gnu/bc/\nPKG_HASH:=7ee4abbcfac03d8a6e1a8a3440558a3d239d6b858585063e745c760957725ecc\n\nPKG_FIXUP := autoreconf\n\ninclude $(INCLUDE_DIR)/host-build.mk\n\n$(eval $(call HostBuild))\n"
  },
  {
    "path": "tools/bc/patches/001-no_doc.patch",
    "content": "diff -urN bc-1.06.95/Makefile.am bc-1.06.95.new/Makefile.am\n--- bc-1.06.95/Makefile.am\t2005-05-27 01:05:41.000000000 +0100\n+++ bc-1.06.95.new/Makefile.am\t2013-07-09 09:33:31.521490710 +0100\n@@ -1,6 +1,6 @@\n ## Process this file with automake to produce Makefile.in\n \n-SUBDIRS = lib bc dc doc\n+SUBDIRS = lib bc dc\n \n MAINTAINERCLEANFILES =  aclocal.m4 config.h.in configure Makefile.in \\\n \t\t\tstamp-h $(distdir).tar.gz h/number.h depcomp missing\ndiff -urN bc-1.06.95/Makefile.in bc-1.06.95.new/Makefile.in\n--- bc-1.06.95/Makefile.in\t2006-09-05 03:39:30.000000000 +0100\n+++ bc-1.06.95.new/Makefile.in\t2013-07-09 09:33:28.565490767 +0100\n@@ -149,7 +149,7 @@\n sharedstatedir = @sharedstatedir@\n sysconfdir = @sysconfdir@\n target_alias = @target_alias@\n-SUBDIRS = lib bc dc doc\n+SUBDIRS = lib bc dc\n MAINTAINERCLEANFILES = aclocal.m4 config.h.in configure Makefile.in \\\n \t\t\tstamp-h $(distdir).tar.gz h/number.h depcomp missing\n \n"
  },
  {
    "path": "tools/bison/Makefile",
    "content": "#\n# Copyright (C) 2008-2015 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=bison\nPKG_VERSION:=3.8.2\n\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz\nPKG_SOURCE_URL:=@GNU/$(PKG_NAME)\nPKG_HASH:=9bba0214ccf7f1079c5d59210045227bcf619519840ebfa80cd3849cff5a5bf2\n\nHOST_BUILD_PARALLEL:=1\n\ninclude $(INCLUDE_DIR)/host-build.mk\n\nHOST_CONFIGURE_ARGS += --enable-threads=posix --disable-nls\n\ndefine Host/Clean\n\t-$(MAKE) -C $(HOST_BUILD_DIR) uninstall\n\t$(call Host/Clean/Default)\nendef\n\ndefine Host/Install\n\t$(call Host/Install/Default)\n\t$(INSTALL_BIN) ./scripts/yacc $(STAGING_DIR_HOST)/bin/yacc\nendef\n\n$(eval $(call HostBuild))\n"
  },
  {
    "path": "tools/bison/scripts/yacc",
    "content": "#!/bin/sh\nexec bison -y \"$@\"\n"
  },
  {
    "path": "tools/cbootimage/Makefile",
    "content": "#\n# Copyright (c) 2017-2019 Tomasz Maciej Nowak <tmn505@gmail.com>\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME := cbootimage\nPKG_VERSION := 1.8\n\nPKG_SOURCE_PROTO := git\nPKG_SOURCE_URL := https://github.com/NVIDIA/cbootimage.git\nPKG_SOURCE_VERSION := 7c9db585d06cce9efffa2a82245f233233680060\nPKG_MIRROR_HASH := 84d9abaaa3eddde05f506dc16effe1c9e18eb94727ed59c5e0a879baeb04e0b2\n\nHOST_BUILD_PARALLEL := 1\n\ninclude $(INCLUDE_DIR)/host-build.mk\n\ndefine Host/Configure\n\t(cd $(HOST_BUILD_DIR); autoreconf --install --symlink)\n\t$(call Host/Configure/Default)\nendef\n\ndefine Host/Clean\n\trm -f $(STAGING_DIR_HOST)/bin/$(PKG_NAME) \\\n\t\t$(STAGING_DIR_HOST)/share/man/man1/$(PKG_NAME).1\nendef\n\n$(eval $(call HostBuild))\n"
  },
  {
    "path": "tools/cbootimage-configs/Makefile",
    "content": "#\n# Copyright (c) 2017-2019 Tomasz Maciej Nowak <tmn505@gmail.com>\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME := cbootimage-configs\n\nPKG_SOURCE_DATE := 2017-04-13\nPKG_SOURCE_PROTO := git\nPKG_SOURCE_URL := https://github.com/NVIDIA/cbootimage-configs.git\nPKG_SOURCE_VERSION := 7c3b458b93ed6947cd083623f543e93f9103cc0f\nPKG_MIRROR_HASH := 1d24421af8cf74ec2d625e237aa8121b1273774c4380ad333e2954e052a5a4fe\n\ninclude $(INCLUDE_DIR)/host-build.mk\n\ndefine Host/Compile\nendef\n\ndefine Host/Install\n\t$(INSTALL_DIR) $(STAGING_DIR_HOST)/share/$(PKG_NAME)\n\t$(CP) $(HOST_BUILD_DIR)/* \\\n\t\t$(STAGING_DIR_HOST)/share/$(PKG_NAME)\nendef\n\ndefine Host/Clean\n\trm -fR $(STAGING_DIR_HOST)/share/$(PKG_NAME)\nendef\n\n$(eval $(call HostBuild))\n"
  },
  {
    "path": "tools/ccache/Makefile",
    "content": "#\n# Copyright (C) 2006-2015 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\ninclude $(TOPDIR)/rules.mk\ninclude $(INCLUDE_DIR)/target.mk\n\nPKG_NAME:=ccache\nPKG_VERSION:=4.6\n\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz\nPKG_SOURCE_URL:=https://github.com/ccache/ccache/releases/download/v$(PKG_VERSION)\nPKG_HASH:=3d2bb860f4359169e640f60cf7cc11da5fab5fb9aed55230d78141e49c3945e9\n\ninclude $(INCLUDE_DIR)/host-build.mk\ninclude $(INCLUDE_DIR)/cmake.mk\n\nCMAKE_HOST_OPTIONS += \\\n\t-DCMAKE_C_COMPILER_LAUNCHER=\"\" \\\n\t-DCMAKE_CXX_COMPILER_LAUNCHER=\"\" \\\n\t-DCMAKE_SKIP_RPATH=FALSE \\\n\t-DCMAKE_INSTALL_RPATH=\"${STAGING_DIR_HOST}/lib\" \\\n\t-DREDIS_STORAGE_BACKEND=OFF\n\nifneq (docs-$(CONFIG_BUILD_DOCUMENTATION),docs-y)\nCMAKE_HOST_OPTIONS += -DENABLE_DOCUMENTATION=OFF\nendif\n\ndefine Host/Install/ccache\n\t$(INSTALL_DIR) $(STAGING_DIR_HOST)/bin/\n\t$(CP) ./files/* $(STAGING_DIR_HOST)/bin/\nendef\n\ndefine Host/Install\n\t$(call Host/Install/Default)\n\t$(call Host/Install/ccache)\nendef\n\n$(eval $(call HostBuild))\n"
  },
  {
    "path": "tools/ccache/files/ccache_cc",
    "content": "#!/bin/sh\nexec ccache \"${TARGET_CC_NOCACHE}\" \"$@\"\n"
  },
  {
    "path": "tools/ccache/files/ccache_cxx",
    "content": "#!/bin/sh\nexec ccache \"${TARGET_CXX_NOCACHE}\" \"$@\"\n"
  },
  {
    "path": "tools/ccache/patches/100-honour-copts.patch",
    "content": "--- a/src/ccache.cpp\n+++ b/src/ccache.cpp\n@@ -1633,6 +1633,7 @@ calculate_result_and_manifest_key(Contex\n                              \"CPLUS_INCLUDE_PATH\",\n                              \"OBJC_INCLUDE_PATH\",\n                              \"OBJCPLUS_INCLUDE_PATH\", // clang\n+                             \"GCC_HONOUR_COPTS\",\n                              nullptr};\n     for (const char** p = envvars; *p; ++p) {\n       const char* v = getenv(*p);\n"
  },
  {
    "path": "tools/cmake/Makefile",
    "content": "#\n# Copyright (C) 2006-2016 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=cmake\nPKG_VERSION:=3.22.3\nPKG_RELEASE:=1\nPKG_CPE_ID:=cpe:/a:kitware:cmake\n\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz\nPKG_SOURCE_URL:=https://github.com/Kitware/CMake/releases/download/v$(PKG_VERSION)/ \\\n\t\thttps://cmake.org/files/v3.22/\nPKG_HASH:=9f8469166f94553b6978a16ee29227ec49a2eb5ceb608275dec40d8ae0d1b5a0\n\nHOST_BUILD_PARALLEL:=1\nHOST_CONFIGURE_PARALLEL:=1\n\ninclude $(INCLUDE_DIR)/host-build.mk\n\nHOST_CONFIGURE_VARS += \\\n\tCC=\"$(HOSTCC_NOCACHE)\" \\\n\tCXX=\"$(HOSTCXX_NOCACHE)\" \\\n\tMAKEFLAGS=\"$(HOST_JOBS)\" \\\n\tCXXFLAGS=\"$(HOST_CFLAGS)\" \\\n\tMAKE=\"$(STAGING_DIR_HOST)/bin/ninja\"\n\nHOST_CONFIGURE_ARGS := \\\n\t$(if $(MAKE_JOBSERVER),--parallel=\"$(MAKE_JOBSERVER)\") \\\n\t--prefix=\"$(STAGING_DIR_HOST)\" \\\n\t--generator=Ninja\n\ndefine Host/Compile/Default\n\t+$(NINJA) -C $(HOST_BUILD_DIR) $(1)\nendef\n\ndefine Host/Install/Default\n\t+$(NINJA) -C $(HOST_BUILD_DIR) install\nendef\n\ndefine Host/Uninstall/Default\n\t+$(NINJA) -C $(HOST_BUILD_DIR) uninstall\nendef\n\nifneq ($(findstring c,$(OPENWRT_VERBOSE)),)\n  HOST_MAKE_FLAGS += VERBOSE=1\nendif\n\n$(eval $(call HostBuild))\n"
  },
  {
    "path": "tools/cmake/patches/100-no-testing.patch",
    "content": "--- a/Modules/CTest.cmake\n+++ b/Modules/CTest.cmake\n@@ -47,7 +47,7 @@ the :variable:`CTEST_USE_LAUNCHERS` vari\n in the ``CTestConfig.cmake`` file.\n #]=======================================================================]\n \n-option(BUILD_TESTING \"Build the testing tree.\" ON)\n+option(BUILD_TESTING \"Build the testing tree.\" OFF)\n \n # function to turn generator name into a version string\n # like vs9 or vs10\n--- a/Modules/Dart.cmake\n+++ b/Modules/Dart.cmake\n@@ -33,7 +33,7 @@ whether testing support should be enable\n #\n #\n \n-option(BUILD_TESTING \"Build the testing tree.\" ON)\n+option(BUILD_TESTING \"Build the testing tree.\" OFF)\n \n if(BUILD_TESTING)\n   find_package(Dart QUIET)\n--- a/Tests/Contracts/VTK/Dashboard.cmake.in\n+++ b/Tests/Contracts/VTK/Dashboard.cmake.in\n@@ -25,7 +25,7 @@ ctest_empty_binary_directory(${CTEST_BIN\n \n file(WRITE \"${CTEST_BINARY_DIRECTORY}/CMakeCache.txt\" \"\n   VTK_BUILD_EXAMPLES:BOOL=ON\n-  VTK_BUILD_TESTING:STRING=WANT\n+  VTK_BUILD_TESTING:STRING=OFF\n   VTK_WRAP_PYTHON:BOOL=ON\n   ExternalData_OBJECT_STORES:FILEPATH=@base_dir@/ExternalData\n \")\n"
  },
  {
    "path": "tools/cmake/patches/120-curl-fix-libressl-linking.patch",
    "content": "From: Jo-Philipp Wich <jo@mein.io>\nDate: Wed, 11 Jan 2017 03:36:04 +0100\nSubject: [PATCH] cmcurl: link librt\n\nWhen cmake is linked against LibreSSL, there might be an indirect\ndependency on librt on certain systems if LibreSSL's libcrypto uses\nclock_gettime() from librt:\n\n    [ 28%] Linking C executable LIBCURL\n    .../lib/libcrypto.a(getentropy_linux.o): In function `getentropy_fallback':\n    getentropy_linux.c:(.text+0x16d): undefined reference to `clock_gettime'\n    getentropy_linux.c:(.text+0x412): undefined reference to `clock_gettime'\n    collect2: error: ld returned 1 exit status\n    make[5]: *** [Utilities/cmcurl/LIBCURL] Error 1\n\nModify the cmcurl CMakeLists.txt to check for clock_gettime() in librt\nand unconditionally link the rt library when the symbol is found.\n\nSigned-off-by: Jo-Philipp Wich <jo@mein.io>\n---\n--- a/Utilities/cmcurl/CMakeLists.txt\n+++ b/Utilities/cmcurl/CMakeLists.txt\n@@ -565,6 +565,14 @@ if(CMAKE_USE_OPENSSL)\n   endif()\n   set(SSL_ENABLED ON)\n   set(USE_OPENSSL ON)\n+  check_library_exists(\"rt\" clock_gettime \"\" HAVE_LIBRT)\n+  if(HAVE_LIBRT)\n+    list(APPEND OPENSSL_LIBRARIES rt)\n+  endif()\n+  check_library_exists(\"pthread\" pthread_once \"\" HAVE_PTHREAD)\n+  if(HAVE_PTHREAD)\n+    list(APPEND OPENSSL_LIBRARIES pthread)\n+  endif()\n   list(APPEND CURL_LIBS ${OPENSSL_LIBRARIES})\n   include_directories(${OPENSSL_INCLUDE_DIR})\n \n"
  },
  {
    "path": "tools/cmake/patches/130-bootstrap_parallel_make_flag.patch",
    "content": "--- a/bootstrap\n+++ b/bootstrap\n@@ -1423,7 +1423,10 @@ int main(){ printf(\"1%c\", (char)0x0a); r\n ' > \"test.c\"\n cmake_original_make_flags=\"${cmake_make_flags}\"\n if test \"x${cmake_parallel_make}\" != \"x\"; then\n-  cmake_make_flags=\"${cmake_make_flags} -j ${cmake_parallel_make}\"\n+  case \"$cmake_parallel_make\" in\n+    [0-9]*) cmake_parallel_make=\"-j ${cmake_parallel_make}\";;\n+  esac\n+  cmake_make_flags=\"${cmake_make_flags} ${cmake_parallel_make}\"\n fi\n for a in ${cmake_make_processors}; do\n   if test -z \"${cmake_make_processor}\" && cmake_try_make \"${a}\" \"${cmake_make_flags}\" >> ../cmake_bootstrap.log 2>&1; then\n"
  },
  {
    "path": "tools/coreutils/Makefile",
    "content": "#\n# Copyright (C) 2015 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=coreutils\nPKG_CPE_ID:=cpe:/a:gnu:coreutils\nPKG_VERSION:=8.32\n\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz\nPKG_SOURCE_URL:=@GNU/coreutils\nPKG_HASH:=4458d8de7849df44ccab15e16b1548b285224dbba5f08fac070c1c0e0bcc4cfa\n\nHOST_BUILD_PARALLEL := 1\n\nBUILD_PROGRAMS = date readlink touch ln chown\n\ninclude $(INCLUDE_DIR)/host-build.mk\n\nBUILD_BINS = $(patsubst %,src/%,$(BUILD_PROGRAMS))\n\nHOST_CONFIGURE_ARGS += \\\n\t --enable-install-program=$(subst $(space),$(comma),$(strip $(BUILD_PROGRAMS)))\n\nHOST_MAKE_FLAGS += \\\n\tPROGRAMS=\"$(BUILD_BINS)\" \\\n\tLIBRARIES= MANS= SUBDIRS=.\n\ndefine Host/Install\n\t$(INSTALL_DIR) $(1)/bin\n\t$(CP) $(patsubst %,$(HOST_BUILD_DIR)/%,$(BUILD_BINS)) $(1)/bin/\nendef\n\n$(eval $(call HostBuild))\n"
  },
  {
    "path": "tools/cpio/Makefile",
    "content": "# SPDX-License-Identifier: GPL-2.0-only\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=cpio\nPKG_CPE_ID:=cpe:/a:gnu:cpio\nPKG_VERSION:=2.13\n\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.bz2\nPKG_SOURCE_URL:=@GNU/cpio\nPKG_HASH:=eab5bdc5ae1df285c59f2a4f140a98fc33678a0bf61bdba67d9436ae26b46f6d\n\ninclude $(INCLUDE_DIR)/host-build.mk\n\n$(eval $(call HostBuild))\n"
  },
  {
    "path": "tools/cpio/patches/001-duplicate-program-name.patch",
    "content": "author\tSergey Poznyakoff <gray@gnu.org>\n\nhttps://git.savannah.gnu.org/cgit/cpio.git/commit/?id=641d3f489cf6238bb916368d4ba0d9325a235afb\n\n* src/global.c: Remove superfluous declaration of program_name\n\n--- a/src/global.c\n+++ b/src/global.c\n@@ -184,9 +184,6 @@ unsigned int warn_option = 0;\n /* Extract to standard output? */\n bool to_stdout_option = false;\n \n-/* The name this program was run with.  */\n-char *program_name;\n-\n /* A pointer to either lstat or stat, depending on whether\n    dereferencing of symlinks is done for input files.  */\n int (*xstat) ();\n"
  },
  {
    "path": "tools/cpio/patches/010-clang.patch",
    "content": "--- a/gnu/xalloc-oversized.h\n+++ b/gnu/xalloc-oversized.h\n@@ -52,7 +52,7 @@ typedef size_t __xalloc_count_type;\n #elif ((5 <= __GNUC__ \\\n         || (__has_builtin (__builtin_mul_overflow) \\\n             && __has_builtin (__builtin_constant_p))) \\\n-       && !__STRICT_ANSI__)\n+       && !__STRICT_ANSI__) && !defined(__clang__)\n # define xalloc_oversized(n, s) \\\n    (__builtin_constant_p (n) && __builtin_constant_p (s) \\\n     ? __xalloc_oversized (n, s) \\\n"
  },
  {
    "path": "tools/dosfstools/Makefile",
    "content": "#\n# Copyright (C) 2012-2015 OpenWrt.org\n# Copyright (C) 2016 LEDE-Project.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=dosfstools\nPKG_CPE_ID:=cpe:/a:dosfstools_project:dosfstools\nPKG_VERSION:=4.2\n\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz\nPKG_SOURCE_URL:=https://github.com/dosfstools/dosfstools/releases/download/v$(PKG_VERSION)/ \\\n\t\thttp://fossies.org/linux/misc\nPKG_HASH:=ba7c716ff9b8208a3bba5094a77584a7dc814141de09ab4ce1ae9b84bbcd7844\n\nHOST_FIXUP:=autoreconf\n\ninclude $(INCLUDE_DIR)/host-build.mk\n\nifeq ($(HOST_OS),Darwin)\nHOST_CFLAGS += -UHAVE_ENDIAN_H\nendif\n\n$(eval $(call HostBuild))\n"
  },
  {
    "path": "tools/dosfstools/patches/source-date-epoch.patch",
    "content": "From 8da7bc93315cb0c32ad868f17808468b81fa76ec Mon Sep 17 00:00:00 2001\nFrom: =?UTF-8?q?Bj=C3=B8rn=20Forsman?= <bjorn.forsman@gmail.com>\nDate: Wed, 5 Dec 2018 19:52:51 +0100\nSubject: [PATCH] Honor the SOURCE_DATE_EPOCH variable\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nImplement the SOURCE_DATE_EPOCH specification[1] for reproducible\nbuilds. If SOURCE_DATE_EPOCH is set, use it as timestamp instead of the\ncurrent time.\n\n[1] https://reproducible-builds.org/specs/source-date-epoch/\n\nSigned-off-by: Bjørn Forsman <bjorn.forsman@gmail.com>\n---\n src/boot.c     | 23 +++++++++++++++++++++--\n src/common.c   | 18 ++++++++++++++++--\n src/mkfs.fat.c | 19 ++++++++++++++++---\n 3 files changed, 53 insertions(+), 7 deletions(-)\n\ndiff --git a/src/boot.c b/src/boot.c\nindex 4de450d..8f78e1c 100644\n--- a/src/boot.c\n+++ b/src/boot.c\n@@ -33,6 +33,8 @@\n #include <stdlib.h>\n #include <sys/types.h>\n #include <time.h>\n+#include <errno.h>\n+#include <ctype.h>\n \n #include \"common.h\"\n #include \"fsck.fat.h\"\n@@ -672,6 +674,7 @@ void write_volume_label(DOS_FS * fs, char *label)\n {\n     time_t now;\n     struct tm *mtime;\n+    char *source_date_epoch = NULL;\n     off_t offset;\n     int created;\n     DIR_ENT de;\n@@ -687,8 +690,24 @@ void write_volume_label(DOS_FS * fs, char *label)\n     if (de.name[0] == 0xe5)\n \tde.name[0] = 0x05;\n \n-    now = time(NULL);\n-    mtime = (now != (time_t)-1) ? localtime(&now) : NULL;\n+    source_date_epoch = getenv(\"SOURCE_DATE_EPOCH\");\n+    if (source_date_epoch) {\n+        char *tmp = NULL;\n+        long long conversion = 0;\n+        errno = 0;\n+        conversion = strtoll(source_date_epoch, &tmp, 10);\n+        now = conversion;\n+        if (!isdigit((unsigned char)*source_date_epoch) || *tmp != '\\0'\n+                || errno != 0 || (long long)now != conversion) {\n+            die(\"SOURCE_DATE_EPOCH is too big or contains non-digits: \\\"%s\\\"\",\n+                source_date_epoch);\n+        }\n+        mtime = gmtime(&now);\n+    } else {\n+        now = time(NULL);\n+        mtime = (now != (time_t)-1) ? localtime(&now) : NULL;\n+    }\n+\n     if (mtime && mtime->tm_year >= 80 && mtime->tm_year <= 207) {\n \tde.time = htole16((unsigned short)((mtime->tm_sec >> 1) +\n \t\t\t\t\t   (mtime->tm_min << 5) +\ndiff --git a/src/common.c b/src/common.c\nindex 6a2e396..4f1afcb 100644\n--- a/src/common.c\n+++ b/src/common.c\n@@ -30,6 +30,7 @@\n #include <string.h>\n #include <stdarg.h>\n #include <errno.h>\n+#include <ctype.h>\n #include <wctype.h>\n #include <termios.h>\n #include <sys/time.h>\n@@ -298,8 +299,21 @@ void check_atari(void)\n uint32_t generate_volume_id(void)\n {\n     struct timeval now;\n-\n-    if (gettimeofday(&now, NULL) != 0 || now.tv_sec == (time_t)-1 || now.tv_sec < 0) {\n+    char *source_date_epoch = NULL;\n+\n+    source_date_epoch = getenv(\"SOURCE_DATE_EPOCH\");\n+    if (source_date_epoch) {\n+        char *tmp = NULL;\n+        long long conversion = 0;\n+        errno = 0;\n+        conversion = strtoll(source_date_epoch, &tmp, 10);\n+        if (!isdigit((unsigned char)*source_date_epoch) || *tmp != '\\0'\n+                || errno != 0) {\n+            die(\"SOURCE_DATE_EPOCH is too big or contains non-digits: \\\"%s\\\"\",\n+                source_date_epoch);\n+        }\n+        return (uint32_t)conversion;\n+    } else if (gettimeofday(&now, NULL) != 0 || now.tv_sec == (time_t)-1 || now.tv_sec < 0) {\n         srand(getpid());\n         /* rand() returns int from [0,RAND_MAX], therefore only 31 bits */\n         return (((uint32_t)(rand() & 0xFFFF)) << 16) | ((uint32_t)(rand() & 0xFFFF));\ndiff --git a/src/mkfs.fat.c b/src/mkfs.fat.c\nindex 37fc8ff..1948635 100644\n--- a/src/mkfs.fat.c\n+++ b/src/mkfs.fat.c\n@@ -1074,7 +1074,7 @@ static void setup_tables(void)\n         }\n \n         /* If is not available then generate random 32 bit disk signature */\n-        if (invariant)\n+        if (invariant || getenv(\"SOURCE_DATE_EPOCH\"))\n             disk_sig = volume_id;\n         else if (!disk_sig)\n             disk_sig = generate_volume_id();\n@@ -1287,7 +1287,7 @@ static void setup_tables(void)\n \t    de->name[0] = 0x05;\n \tde->attr = ATTR_VOLUME;\n \tif (create_time != (time_t)-1) {\n-\t    if (!invariant)\n+\t    if (!invariant && !getenv(\"SOURCE_DATE_EPOCH\"))\n \t\tctime = localtime(&create_time);\n \t    else\n \t\tctime = gmtime(&create_time);\n@@ -1477,6 +1477,7 @@ int main(int argc, char **argv)\n     int blocks_specified = 0;\n     struct timeval create_timeval;\n     long long conversion;\n+    char *source_date_epoch = NULL;\n \n     enum {OPT_HELP=1000, OPT_INVARIANT, OPT_MBR, OPT_VARIANT, OPT_CODEPAGE, OPT_OFFSET};\n     const struct option long_options[] = {\n@@ -1497,8 +1498,20 @@ int main(int argc, char **argv)\n \t    program_name = p + 1;\n     }\n \n-    if (gettimeofday(&create_timeval, NULL) == 0 && create_timeval.tv_sec != (time_t)-1)\n+    source_date_epoch = getenv(\"SOURCE_DATE_EPOCH\");\n+    if (source_date_epoch) {\n+        errno = 0;\n+        conversion = strtoll(source_date_epoch, &tmp, 10);\n+        create_time = conversion;\n+        if (!isdigit((unsigned char)*source_date_epoch) || *tmp != '\\0'\n+                || errno != 0 || (long long)create_time != conversion) {\n+            die(\"SOURCE_DATE_EPOCH is too big or contains non-digits: \\\"%s\\\"\",\n+                source_date_epoch);\n+        }\n+    } else if (gettimeofday(&create_timeval, NULL) == 0 && create_timeval.tv_sec != (time_t)-1) {\n         create_time = create_timeval.tv_sec;\n+    }\n+\n     volume_id = generate_volume_id();\n     check_atari();\n "
  },
  {
    "path": "tools/e2fsprogs/Makefile",
    "content": "#\n# Copyright (C) 2010-2015 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=e2fsprogs\nPKG_CPE_ID:=cpe:/a:e2fsprogs_project:e2fsprogs\nPKG_VERSION:=1.46.4\nPKG_HASH:=b11042533c1b1dcf17512f0da48e05b0c573dada1dd8b762864d10f4dc399713\nPKG_RELEASE:=1\n\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz\nPKG_SOURCE_URL:=@KERNEL/linux/kernel/people/tytso/e2fsprogs/v$(PKG_VERSION)/\n\nHOST_BUILD_PARALLEL:=1\n\ninclude $(INCLUDE_DIR)/host-build.mk\n\nifneq ($(shell $(HOSTCC) --version | grep clang),)\n  HOST_CFLAGS += -D__GNUC_PREREQ\\(...\\)=0 -Dloff_t=off_t\nendif\nHOST_CFLAGS += $(HOST_FPIC)\n\nHOST_CONFIGURE_ARGS += \\\n\t--disable-elf-shlibs \\\n\t--enable-libuuid \\\n\t--disable-tls \\\n\t--disable-nls \\\n\t--enable-threads=pth\n\ndefine Host/Prepare\n\t$(call Host/Prepare/Default)\n\trm -rf $(HOST_BUILD_DIR)/doc\nendef\n\ndefine Host/Install\n\t$(Host/Install/Default)\n\t$(MAKE) -C $(HOST_BUILD_DIR)/lib/uuid install\n\tmkdir -p $(STAGING_DIR_HOST)/include/e2fsprogs\n\t$(CP) $(STAGING_DIR_HOST)/include/uuid $(STAGING_DIR_HOST)/include/e2fsprogs/\n\trm -rf $(STAGING_DIR_HOST)/include/uuid\n\t$(INSTALL_DATA) $(HOST_BUILD_DIR)/lib/uuid/libuuid.a $(STAGING_DIR_HOST)/lib/\nendef\n\ndefine Host/Clean\n\trm -f $(STAGING_DIR_HOST)/bin/e2fsck\n\trm -f $(STAGING_DIR_HOST)/bin/tune2fs\nendef\n\n$(eval $(call HostBuild))\n"
  },
  {
    "path": "tools/e2fsprogs/patches/001-exit_0_on_corrected_errors.patch",
    "content": "--- a/e2fsck/e2fsck.h\n+++ b/e2fsck/e2fsck.h\n@@ -74,7 +74,7 @@\n  * Exit codes used by fsck-type programs\n  */\n #define FSCK_OK          0\t/* No errors */\n-#define FSCK_NONDESTRUCT 1\t/* File system errors corrected */\n+#define FSCK_NONDESTRUCT 0\t/* File system errors corrected */\n #define FSCK_REBOOT      2\t/* System should be rebooted */\n #define FSCK_UNCORRECTED 4\t/* File system errors left uncorrected */\n #define FSCK_ERROR       8\t/* Operational error */\n"
  },
  {
    "path": "tools/e2fsprogs/patches/002-dont-build-e4defrag.patch",
    "content": "--- a/misc/Makefile.in\n+++ b/misc/Makefile.in\n@@ -12,7 +12,7 @@ MKDIR_P = @MKDIR_P@\n \n @MCONFIG@\n \n-@DEFRAG_CMT@@LINUX_CMT@E4DEFRAG_PROG= e4defrag\n+@DEFRAG_CMT@@LINUX_CMT@E4DEFRAG_PROG=\n @DEFRAG_CMT@@LINUX_CMT@E4DEFRAG_MAN= e4defrag.8\n \n @LINUX_CMT@E4CRYPT_PROG = e4crypt\n"
  },
  {
    "path": "tools/e2fsprogs/patches/003-no-crond.patch",
    "content": "--- a/configure\n+++ b/configure\n@@ -12538,7 +12538,7 @@ $as_echo_n \"checking for system crontab\n \n \t\t{ $as_echo \"$as_me:${as_lineno-$LINENO}: result: ${crond_dir}\" >&5\n $as_echo \"${crond_dir}\" >&6; }\n-\t\thave_crond=\"yes\"\n+\t\thave_crond=\"no\"; with_crond_dir=\"\"\n \n else\n \n"
  },
  {
    "path": "tools/elftosb/Makefile",
    "content": "#\n# Copyright (C) 2013 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=elftosb\nPKG_VERSION:=10.12.01\n\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz\nPKG_SOURCE_URL:=http://repository.timesys.com/buildsources/e/elftosb/elftosb-10.12.01/\nPKG_HASH:=77bb6981620f7575b87d136d94c7daa88dd09195959cc75fc18b138369ecd42b\n\ninclude $(INCLUDE_DIR)/host-build.mk\n\ndefine Host/Compile\n\t$(MAKE) -C $(HOST_BUILD_DIR) LDFLAGS=\"$(HOST_LDFLAGS)\"\nendef\n\ndefine Host/Install\n\t$(INSTALL_BIN) $(HOST_BUILD_DIR)/bld/linux/elftosb $(STAGING_DIR_HOST)/bin/elftosb\nendef\n\n$(eval $(call HostBuild))\n"
  },
  {
    "path": "tools/elftosb/patches/001-libm.patch",
    "content": "--- elftosb-10.12.01/makefile.rules\t2012-03-15 11:01:44.979020178 -0400\n+++ elftosb-10.12.01/makefile.rules\t2012-03-15 11:01:16.332761989 -0400\n@@ -101,7 +101,7 @@\n \tkeygen.o\n \n \n-LIBS =     -lstdc++\n+LIBS =     -lstdc++ -lm\n \n \n ifeq (\"${UNAMES}\", \"Linux\")\n"
  },
  {
    "path": "tools/elftosb/patches/002-fix-header-path.patch",
    "content": "This package had an absolute path for sys/types.h, which doesn't\nmake much sense. It breaks on newer Ubuntu systems, and probably many\nothers once multiarch becomes more common.\n\nThis patch makes the types a relative path, and allows the system\nto use whatever include paths it feels are correct.\n\ndiff -Naurp elftosb-10.12.01-orig/common/stdafx.h elftosb-10.12.01/common/stdafx.h\n--- elftosb-10.12.01-orig/common/stdafx.h\t2012-07-12 13:30:10.990249396 -0400\n+++ elftosb-10.12.01/common/stdafx.h\t2012-07-12 13:30:06.858249391 -0400\n@@ -27,7 +27,7 @@\n // For Linux systems only, types.h only defines the signed\n // integer types.  This is not professional code.\n // Update: They are defined in the header files in the more recent version of redhat enterprise gcc.\n-#include \"/usr/include/sys/types.h\"\n+#include <sys/types.h>\n #include <stdint.h>\n //typedef unsigned long uint32_t;\n //typedef unsigned short uint16_t;\n"
  },
  {
    "path": "tools/elftosb/patches/003-use-ldflags.patch",
    "content": "--- a/makefile.rules\n+++ b/makefile.rules\n@@ -131,19 +131,20 @@ exec_always:\n \t@echo \"LIBS = ${LIBS}\"\n \t@echo \"EXEC_FILE = ${EXEC_FILE}\"\n \t@echo \"BUILD_DIR = ${BUILD_DIR}\"\n+\t@echo \"LDFLAGS = ${LDFLAGS}\"\n \n clean:\n \trm -f ${OBJ_FILES_ELFTOSB2} ${OBJ_FILES_SBTOOL} ${OBJ_FILES_KEYGEN} \\\n \t\t${EXEC_FILE_ELFTOSB2} ${EXEC_FILE_SBTOOL} ${EXEC_FILE_KEYGEN}\n \n elftosb: ${OBJ_FILES_ELFTOSB2}\n-\tgcc ${OBJ_FILES_ELFTOSB2} ${LIBS} -o ${EXEC_FILE_ELFTOSB2}\n+\tgcc ${OBJ_FILES_ELFTOSB2} ${LIBS} ${LDFLAGS} -o ${EXEC_FILE_ELFTOSB2}\n \n sbtool: ${OBJ_FILES_SBTOOL}\n-\tgcc ${OBJ_FILES_SBTOOL} ${LIBS} -o ${EXEC_FILE_SBTOOL}\n+\tgcc ${OBJ_FILES_SBTOOL} ${LIBS} ${LDFLAGS} -o ${EXEC_FILE_SBTOOL}\n \n keygen: ${OBJ_FILES_KEYGEN}\n-\tgcc ${OBJ_FILES_KEYGEN} ${LIBS} -o ${EXEC_FILE_KEYGEN}\n+\tgcc ${OBJ_FILES_KEYGEN} ${LIBS} ${LDFLAGS} -o ${EXEC_FILE_KEYGEN}\n \n \n #ifeq (\"${UNAMES}\", \"Linux\")\n"
  },
  {
    "path": "tools/expat/Makefile",
    "content": "#\n# Copyright (C) 2006-2014 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=expat\nPKG_CPE_ID:=cpe:/a:libexpat:expat\nPKG_VERSION:=2.4.7\n\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.bz2\nPKG_HASH:=e149bdd8b90254c62b3d195da53a09bd531a4d63a963b0d8a5268d48dd2f6a65\nPKG_SOURCE_URL:=https://github.com/libexpat/libexpat/releases/download/R_$(subst .,_,$(PKG_VERSION))\n\ninclude $(INCLUDE_DIR)/host-build.mk\ninclude $(INCLUDE_DIR)/cmake.mk\n\nCMAKE_HOST_OPTIONS += \\\n\t-DDOCBOOK_TO_MAN=OFF \\\n\t-DEXPAT_BUILD_TOOLS=OFF \\\n\t-DEXPAT_BUILD_EXAMPLES=OFF \\\n\t-DEXPAT_BUILD_TESTS=OFF \\\n\t-DEXPAT_BUILD_DOCS=OFF \\\n\t-DEXPAT_WITH_LIBBSD=OFF \\\n\t-DEXPAT_ENABLE_INSTALL=ON \\\n\t-DEXPAT_DTD=ON \\\n\t-DEXPAT_NS=OFF \\\n\t-DEXPAT_DEV_URANDOM=OFF\n\n$(eval $(call HostBuild))\n"
  },
  {
    "path": "tools/fakeroot/Makefile",
    "content": "#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=fakeroot\nPKG_VERSION:=1.28\nPKG_RELEASE:=1\n\nPKG_SOURCE:=$(PKG_NAME)_$(PKG_VERSION).orig.tar.gz\nPKG_SOURCE_URL:=@DEBIAN/pool/main/f/fakeroot\nPKG_HASH:=56d405e36ff685f83879be08fdd654255ab9aa38632b4605a98e896ad63990c2\nPKG_LICENSE:=GPL-3.0-or-later\nPKG_LICENSE_FILES:=COPYING\nPKG_FIXUP:=autoreconf\n\ninclude $(INCLUDE_DIR)/host-build.mk\n\nHOST_CONFIGURE_VARS += \\\n\tac_cv_header_sys_capability_h=no \\\n\tac_cv_func_capset=no \\\n\tCPP=\"$(HOSTCC) -E\"\n\nHOST_CONFIGURE_ARGS += \\\n\t--with-ipc=tcp\n\n$(eval $(call HostBuild))\n"
  },
  {
    "path": "tools/fakeroot/patches/000-relocatable.patch",
    "content": "--- a/scripts/fakeroot.in\n+++ b/scripts/fakeroot.in\n@@ -30,13 +30,20 @@ fatal ()\n }\n \n # strip /bin/fakeroot to find install prefix\n-FAKEROOT_PREFIX=@prefix@\n-FAKEROOT_BINDIR=@bindir@\n+if [ -n \"$STAGING_DIR_HOST\" ]; then\n+    USEABSLIBPATH=1\n+    FAKEROOT_LIB=${STAGING_DIR_HOST}/lib/lib@fakeroot_transformed@@DLSUFFIX@\n+    FAKED=${STAGING_DIR_HOST}/bin/faked\n+    PATHS=\n+else\n+    FAKEROOT_PREFIX=@prefix@\n+    FAKEROOT_BINDIR=@bindir@\n \n-USEABSLIBPATH=@LDPRELOADABS@\n-FAKEROOT_LIB=lib@fakeroot_transformed@@DLSUFFIX@\n-PATHS=@libdir@:${FAKEROOT_PREFIX}/lib64/libfakeroot:${FAKEROOT_PREFIX}/lib32/libfakeroot\n-FAKED=${FAKEROOT_BINDIR}/@faked_transformed@\n+    USEABSLIBPATH=@LDPRELOADABS@\n+    FAKEROOT_LIB=lib@fakeroot_transformed@@DLSUFFIX@\n+    PATHS=@libdir@:${FAKEROOT_PREFIX}/lib64/libfakeroot:${FAKEROOT_PREFIX}/lib32/libfakeroot\n+    FAKED=${FAKEROOT_BINDIR}/@faked_transformed@\n+fi\n \n FAKED_MODE=\"unknown-is-root\"\n export FAKED_MODE\n"
  },
  {
    "path": "tools/fakeroot/patches/200-disable-doc.patch",
    "content": "--- a/Makefile.am\n+++ b/Makefile.am\n@@ -1,6 +1,6 @@\n AUTOMAKE_OPTIONS=foreign\n ACLOCAL_AMFLAGS = -I build-aux\n-SUBDIRS=doc scripts test\n+SUBDIRS=scripts test\n \n noinst_LTLIBRARIES = libcommunicate.la libmacosx.la\n libcommunicate_la_SOURCES = communicate.c\n"
  },
  {
    "path": "tools/fakeroot/patches/400-alpine-libc.musl-fix.patch",
    "content": "Alpine linux libc.musl build error fix\n\nPrevent build error on Alpine Linux host:\nlibfakeroot.c error: conflicting types for 'id_t'\nError relocating openwrt/staging_dir/host/lib/libfakeroot.so: SEND_GET_XATTR: symbol not found\n\n--- a/libfakeroot.c\n+++ b/libfakeroot.c\n@@ -86,12 +86,14 @@\n #define SEND_STAT64(a,b,c) send_stat64(a,b,c)\n #define SEND_GET_STAT(a,b) send_get_stat(a,b)\n #define SEND_GET_STAT64(a,b) send_get_stat64(a,b)\n+#define SEND_GET_XATTR(a,b,c) send_get_xattr(a,b,c)\n #define SEND_GET_XATTR64(a,b,c) send_get_xattr64(a,b,c)\n #else\n #define SEND_STAT(a,b,c) send_stat(a,b)\n #define SEND_STAT64(a,b,c) send_stat64(a,b)\n #define SEND_GET_STAT(a,b) send_get_stat(a)\n #define SEND_GET_STAT64(a,b) send_get_stat64(a)\n+#define SEND_GET_XATTR(a,b,c) send_get_xattr(a,b)\n #define SEND_GET_XATTR64(a,b,c) send_get_xattr64(a,b)\n #endif\n \n@@ -140,8 +142,9 @@\n \n /* 10.10 uses id_t in getpriority/setpriority calls, so pretend\n    id_t is used everywhere, just happens to be int on some OSes */\n-#ifndef _ID_T\n+#if !defined(_ID_T) && !defined(__DEFINED_id_t)\n #define _ID_T\n+#define __DEFINED_id_t\n typedef int id_t;\n #endif\n #endif\n"
  },
  {
    "path": "tools/fakeroot/patches/600-macOS.patch",
    "content": "--- a/communicate.c\n+++ b/communicate.c\n@@ -441,6 +441,10 @@ void semaphore_down(){\n \n #else /* FAKEROOT_FAKENET */\n \n+#ifndef SOL_TCP\n+# define SOL_TCP 6 /* this should probably be done with getprotoent */\n+#endif\n+\n static struct sockaddr *get_addr(void)\n {\n   static struct sockaddr_in addr = { 0, 0, { 0 } };\n--- a/libfakeroot_inode64.c\n+++ b/libfakeroot_inode64.c\n@@ -25,7 +25,7 @@\n #include \"config.h\"\n #include \"communicate.h\"\n \n-#if MAC_OS_X_VERSION_MIN_REQUIRED >= MAC_OS_X_VERSION_10_5\n+#if MAC_OS_X_VERSION_MIN_REQUIRED >= MAC_OS_X_VERSION_10_5 && !__DARWIN_ONLY_64_BIT_INO_T\n \n #include <stdio.h>\n #include <spawn.h>\n--- a/wrapfunc.inp\n+++ b/wrapfunc.inp\n@@ -48,9 +48,11 @@ getattrlist$UNIX2003;int;(const char *pa\n #endif\n #endif\n #if MAC_OS_X_VERSION_MIN_REQUIRED >= MAC_OS_X_VERSION_10_5\n+#if !__DARWIN_ONLY_64_BIT_INO_T\n lstat$INODE64;int;(const char *file_name, struct stat *buf);(file_name, buf)\n stat$INODE64;int;(const char *file_name, struct stat *buf);(file_name, buf)\n fstat$INODE64;int;(int fd, struct stat *buf);(fd, buf)\n+#endif\n posix_spawn;int;(pid_t * __restrict pid, const char * __restrict path, const posix_spawn_file_actions_t *file_actions, const posix_spawnattr_t * __restrict attrp, char *const argv[ __restrict], char *const envp[ __restrict]);(pid, path, file_actions, attrp, argv, envp)\n posix_spawnp;int;(pid_t * __restrict pid, const char * __restrict path, const posix_spawn_file_actions_t *file_actions, const posix_spawnattr_t * __restrict attrp, char *const argv[ __restrict], char *const envp[ __restrict]);(pid, path, file_actions, attrp, argv, envp)\n #endif\n@@ -232,7 +234,7 @@ facl;int;(int fd, int cmd, int cnt, void\n #ifdef HAVE_FTS_READ\n fts_read;FTSENT *;(FTS *ftsp);(ftsp)\n #ifdef __APPLE__\n-#if MAC_OS_X_VERSION_MIN_REQUIRED >= MAC_OS_X_VERSION_10_5\n+#if MAC_OS_X_VERSION_MIN_REQUIRED >= MAC_OS_X_VERSION_10_5 && !__DARWIN_ONLY_64_BIT_INO_T\n fts_read$INODE64;FTSENT *;(FTS *ftsp);(ftsp)\n #endif\n #endif /* ifdef __APPLE__ */\n@@ -240,7 +242,7 @@ fts_read$INODE64;FTSENT *;(FTS *ftsp);(f\n #ifdef HAVE_FTS_CHILDREN\n fts_children;FTSENT *;(FTS *ftsp, int options);(ftsp, options)\n #ifdef __APPLE__\n-#if MAC_OS_X_VERSION_MIN_REQUIRED >= MAC_OS_X_VERSION_10_5\n+#if MAC_OS_X_VERSION_MIN_REQUIRED >= MAC_OS_X_VERSION_10_5 && !__DARWIN_ONLY_64_BIT_INO_T\n fts_children$INODE64;FTSENT *;(FTS *ftsp, int options);(ftsp, options)\n #endif\n #endif /* ifdef __APPLE__ */\n"
  },
  {
    "path": "tools/findutils/Makefile",
    "content": "# \n# Copyright (C) 2006-2016 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=findutils\nPKG_CPE_ID:=cpe:/a:gnu:findutils\nPKG_VERSION:=4.9.0\n\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz\nPKG_SOURCE_URL:=@GNU/$(PKG_NAME)\nPKG_HASH:=a2bfb8c09d436770edc59f50fa483e785b161a3b7b9d547573cb08065fd462fe\n\nHOST_BUILD_PARALLEL:=1\n\ninclude $(INCLUDE_DIR)/host-build.mk\n\nifeq ($(HOST_OS),Darwin)\n\tHOST_CFLAGS +=-D__nonnull\\\\(params\\\\)=\nendif\n\nHOST_CONFIGURE_ARGS += \\\n\t--enable-threads=pth \\\n\t--disable-rpath \\\n\t--disable-nls \\\n\t--without-selinux\n\n$(eval $(call HostBuild))\n"
  },
  {
    "path": "tools/findutils/patches/010-endpwent.patch",
    "content": "--- a/find/parser.c\n+++ b/find/parser.c\n@@ -67,12 +67,12 @@\n #include \"findutils-version.h\"\n #include \"system.h\"\n \n-\n-#ifndef HAVE_ENDGRENT\n-# define endgrent ()\n+#if ! HAVE_ENDGRENT\n+# define endgrent() ((void) 0)\n #endif\n-#ifndef HAVE_ENDPWENT\n-# define endpwent ()\n+\n+#if ! HAVE_ENDPWENT\n+# define endpwent() ((void) 0)\n #endif\n \n static bool parse_accesscheck   (const struct parser_table*, char *argv[], int *arg_ptr);\n"
  },
  {
    "path": "tools/firmware-utils/Makefile",
    "content": "#\n# Copyright (C) 2006-2020 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=firmware-utils\nPKG_RELEASE:=1\n\nPKG_SOURCE_PROTO:=git\nPKG_SOURCE_URL=$(PROJECT_GIT)/project/firmware-utils.git\nPKG_SOURCE_DATE:=2022-04-25\nPKG_SOURCE_VERSION:=ddc3e00e314d3fbc3f9faab2d07395722ce9b01a\nPKG_MIRROR_HASH:=246fc1d72d3a8cdb4072d81e033c92abaf614acd6f35a10fffd029d5c7f9303b\n\ninclude $(INCLUDE_DIR)/host-build.mk\ninclude $(INCLUDE_DIR)/cmake.mk\n\n$(eval $(call HostBuild))\n"
  },
  {
    "path": "tools/flex/Makefile",
    "content": "#\n# Copyright (C) 2008-2016 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=flex\nPKG_CPE_ID:=cpe:/a:flex_project:flex\nPKG_VERSION:=2.6.4\n\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz\nPKG_SOURCE_URL:=https://github.com/westes/flex/releases/download/v$(PKG_VERSION)/\nPKG_HASH:=e87aae032bf07c26f85ac0ed3250998c37621d95f8bd748b31f15b33c45ee995\n\nHOST_FIXUP:=autoreconf\nHOST_BUILD_PARALLEL:=1\n\ninclude $(INCLUDE_DIR)/host-build.mk\n\nHOST_CONFIGURE_ARGS += --disable-shared\n\ndefine Host/Install\n\t$(call Host/Install/Default)\n\t$(LN) flex $(STAGING_DIR_HOST)/bin/lex\nendef\n\ndefine Host/Clean\n\t-$(MAKE) -C $(HOST_BUILD_DIR) uninstall\n\t$(call Host/Clean/Default)\nendef\n\n$(eval $(call HostBuild))\n"
  },
  {
    "path": "tools/flex/patches/100-disable-tests-docs.patch",
    "content": "--- a/Makefile.am\n+++ b/Makefile.am\n@@ -43,10 +43,7 @@ EXTRA_DIST = \\\n \n SUBDIRS = \\\n \tsrc \\\n-\tdoc \\\n-\texamples \\\n \tpo \\\n-\ttests \\\n \ttools\n \n # Create the ChangeLog, but only if we're inside a git working directory\n"
  },
  {
    "path": "tools/flex/patches/200-build-AC_USE_SYSTEM_EXTENSIONS-in-configure.ac.patch",
    "content": "From 24fd0551333e7eded87b64dd36062da3df2f6380 Mon Sep 17 00:00:00 2001\nFrom: Explorer09 <explorer09@gmail.com>\nDate: Mon, 4 Sep 2017 10:47:33 +0800\nSubject: [PATCH] build: AC_USE_SYSTEM_EXTENSIONS in configure.ac.\n\nThis would, e.g. define _GNU_SOURCE in config.h, enabling the\nreallocarray() prototype in glibc 2.26+ on Linux systems with that\nversion of glibc.\n\nFixes #241.\n---\n configure.ac | 2 ++\n 1 file changed, 2 insertions(+)\n\n--- a/configure.ac\n+++ b/configure.ac\n@@ -25,8 +25,10 @@\n # autoconf requirements and initialization\n \n AC_INIT([the fast lexical analyser generator],[2.6.4],[flex-help@lists.sourceforge.net],[flex])\n+AC_PREREQ([2.60])\n AC_CONFIG_SRCDIR([src/scan.l])\n AC_CONFIG_AUX_DIR([build-aux])\n+AC_USE_SYSTEM_EXTENSIONS\n LT_INIT\n AM_INIT_AUTOMAKE([1.11.3 -Wno-portability foreign check-news std-options dist-lzip parallel-tests subdir-objects])\n AC_CONFIG_HEADER([src/config.h])\n"
  },
  {
    "path": "tools/flock/Makefile",
    "content": "#\n# Copyright (C) 2006-2012 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME := flock\nPKG_VERSION := 2.18\nPKG_RELEASE := 1\n\ninclude $(INCLUDE_DIR)/host-build.mk\n\nHOSTCC := $(HOSTCC_NOCACHE)\nHOSTCXX := $(HOSTCXX_NOCACHE)\n\ndefine Host/Compile\n\tmkdir -p $(HOST_BUILD_DIR)\n\t$(HOSTCC) $(HOST_CFLAGS) -o $(HOST_BUILD_DIR)/flock src/flock.c\nendef\n\ndefine Host/Install\n\t$(INSTALL_BIN) $(HOST_BUILD_DIR)/flock $(STAGING_DIR_HOST)/bin/\nendef\n\n$(eval $(call HostBuild))\n"
  },
  {
    "path": "tools/flock/src/flock.c",
    "content": "/* ----------------------------------------------------------------------- *\n *\n *   Copyright 2003-2005 H. Peter Anvin - All Rights Reserved\n *\n *   Permission is hereby granted, free of charge, to any person\n *   obtaining a copy of this software and associated documentation\n *   files (the \"Software\"), to deal in the Software without\n *   restriction, including without limitation the rights to use,\n *   copy, modify, merge, publish, distribute, sublicense, and/or\n *   sell copies of the Software, and to permit persons to whom\n *   the Software is furnished to do so, subject to the following\n *   conditions:\n *\n *   The above copyright notice and this permission notice shall\n *   be included in all copies or substantial portions of the Software.\n *\n *   THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n *   EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n *   OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n *   NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n *   HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n *   WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n *   FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n *   OTHER DEALINGS IN THE SOFTWARE.\n *\n * ----------------------------------------------------------------------- */\n\n#include <errno.h>\n#include <stdio.h>\n#include <stdlib.h>\n#include <unistd.h>\n#include <getopt.h>\n#include <signal.h>\n#include <ctype.h>\n#include <string.h>\n#include <paths.h>\n#include <sysexits.h>\n#include <sys/types.h>\n#include <sys/file.h>\n#include <sys/time.h>\n#include <sys/wait.h>\n#include <fcntl.h>\n\n#define PACKAGE_STRING \"util-linux-ng 2.18\"\n#define _(x) (x)\n\nstatic const struct option long_options[] = {\n  { \"shared\",       0, NULL, 's' },\n  { \"exclusive\",    0, NULL, 'x' },\n  { \"unlock\",       0, NULL, 'u' },\n  { \"nonblocking\",  0, NULL, 'n' },\n  { \"nb\",           0, NULL, 'n' },\n  { \"timeout\",      1, NULL, 'w' },\n  { \"wait\",         1, NULL, 'w' },\n  { \"close\",        0, NULL, 'o' },\n  { \"help\",         0, NULL, 'h' },\n  { \"version\",      0, NULL, 'V' },\n  { 0, 0, 0, 0 }\n};\n\nconst char *program;\n\nstatic void usage(int ex)\n{\n  fputs(\"flock (\" PACKAGE_STRING \")\\n\", stderr);\n  fprintf(stderr,\n\t_(\"Usage: %1$s [-sxun][-w #] fd#\\n\"\n\t  \"       %1$s [-sxon][-w #] file [-c] command...\\n\"\n\t  \"       %1$s [-sxon][-w #] directory [-c] command...\\n\"\n\t  \"  -s  --shared     Get a shared lock\\n\"\n\t  \"  -x  --exclusive  Get an exclusive lock\\n\"\n\t  \"  -u  --unlock     Remove a lock\\n\"\n\t  \"  -n  --nonblock   Fail rather than wait\\n\"\n\t  \"  -w  --timeout    Wait for a limited amount of time\\n\"\n\t  \"  -o  --close      Close file descriptor before running command\\n\"\n\t  \"  -c  --command    Run a single command string through the shell\\n\"\n\t  \"  -h  --help       Display this text\\n\"\n\t  \"  -V  --version    Display version\\n\"),\n\t  program);\n  exit(ex);\n}\n\n\nstatic sig_atomic_t timeout_expired = 0;\n\nstatic void timeout_handler(int sig)\n{\n  (void)sig;\n\n  timeout_expired = 1;\n}\n\n\nstatic char * strtotimeval(const char *str, struct timeval *tv)\n{\n  char *s;\n  long fs;\t\t\t/* Fractional seconds */\n  int i;\n\n  tv->tv_sec = strtol(str, &s, 10);\n  fs = 0;\n\n  if ( *s == '.' ) {\n    s++;\n\n    for ( i = 0 ; i < 6 ; i++ ) {\n      if ( !isdigit(*s) )\n\tbreak;\n\n      fs *= 10;\n      fs += *s++ - '0';\n    }\n\n    for ( ; i < 6; i++ )\n      fs *= 10;\n\n    while ( isdigit(*s) )\n      s++;\n  }\n\n  tv->tv_usec = fs;\n  return s;\n}\n\nint main(int argc, char *argv[])\n{\n  struct itimerval timeout, old_timer;\n  int have_timeout = 0;\n  int type = LOCK_EX;\n  int block = 0;\n  int fd = -1;\n  int opt, ix;\n  int do_close = 0;\n  int err;\n  int status;\n  int open_flags = 0;\n  char *eon;\n  char **cmd_argv = NULL, *sh_c_argv[4];\n  const char *filename = NULL;\n  struct sigaction sa, old_sa;\n\n  program = argv[0];\n\n  if ( argc < 2 )\n    usage(EX_USAGE);\n\n  memset(&timeout, 0, sizeof timeout);\n\n  optopt = 0;\n  while ( (opt = getopt_long(argc, argv, \"+sexnouw:hV?\", long_options, &ix)) != EOF ) {\n    switch(opt) {\n    case 's':\n      type = LOCK_SH;\n      break;\n    case 'e':\n    case 'x':\n      type = LOCK_EX;\n      break;\n    case 'u':\n      type = LOCK_UN;\n      break;\n    case 'o':\n      do_close = 1;\n      break;\n    case 'n':\n      block = LOCK_NB;\n      break;\n    case 'w':\n      have_timeout = 1;\n      eon = strtotimeval(optarg, &timeout.it_value);\n      if ( *eon )\n\tusage(EX_USAGE);\n      break;\n    case 'V':\n      printf(\"flock (%s)\\n\", PACKAGE_STRING);\n      exit(0);\n    default:\n      /* optopt will be set if this was an unrecognized option, i.e. *not* 'h' or '?' */\n      usage(optopt ? EX_USAGE : 0);\n      break;\n    }\n  }\n\n  if ( argc > optind+1 ) {\n    /* Run command */\n\n    if ( !strcmp(argv[optind+1], \"-c\") ||\n\t !strcmp(argv[optind+1], \"--command\") ) {\n\n      if ( argc != optind+3 ) {\n\tfprintf(stderr, _(\"%s: %s requires exactly one command argument\\n\"),\n\t\tprogram, argv[optind+1]);\n\texit(EX_USAGE);\n      }\n\n      cmd_argv = sh_c_argv;\n\n      cmd_argv[0] = getenv(\"SHELL\");\n      if ( !cmd_argv[0] || !*cmd_argv[0] )\n\tcmd_argv[0] = _PATH_BSHELL;\n\n      cmd_argv[1] = \"-c\";\n      cmd_argv[2] = argv[optind+2];\n      cmd_argv[3] = 0;\n    } else {\n      cmd_argv = &argv[optind+1];\n    }\n\n    filename = argv[optind];\n    fd = open(filename, O_RDONLY|O_NOCTTY|O_CREAT, 0666);\n    /* Linux doesn't like O_CREAT on a directory, even though it should be a\n       no-op */\n    if (fd < 0 && errno == EISDIR)\n        fd = open(filename, O_RDONLY|O_NOCTTY);\n\n    if ( fd < 0 ) {\n      err = errno;\n      fprintf(stderr, _(\"%s: cannot open lock file %s: %s\\n\"),\n\t      program, argv[optind], strerror(err));\n      exit((err == ENOMEM||err == EMFILE||err == ENFILE) ? EX_OSERR :\n\t   (err == EROFS||err == ENOSPC) ? EX_CANTCREAT :\n\t   EX_NOINPUT);\n    }\n\n  } else if (optind < argc) {\n    /* Use provided file descriptor */\n\n    fd = (int)strtol(argv[optind], &eon, 10);\n    if ( *eon || !argv[optind] ) {\n      fprintf(stderr, _(\"%s: bad number: %s\\n\"), program, argv[optind]);\n      exit(EX_USAGE);\n    }\n\n  } else {\n    /* Bad options */\n\n    fprintf(stderr, _(\"%s: requires file descriptor, file or directory\\n\"),\n\t\tprogram);\n    exit(EX_USAGE);\n  }\n\n\n  if ( have_timeout ) {\n    if ( timeout.it_value.tv_sec == 0 &&\n\t timeout.it_value.tv_usec == 0 ) {\n      /* -w 0 is equivalent to -n; this has to be special-cased\n\t because setting an itimer to zero means disabled! */\n\n      have_timeout = 0;\n      block = LOCK_NB;\n    } else {\n      memset(&sa, 0, sizeof sa);\n\n      sa.sa_handler = timeout_handler;\n      sa.sa_flags   = SA_RESETHAND;\n      sigaction(SIGALRM, &sa, &old_sa);\n\n      setitimer(ITIMER_REAL, &timeout, &old_timer);\n    }\n  }\n\n  while ( flock(fd, type|block) ) {\n    switch( (err = errno) ) {\n    case EWOULDBLOCK:\t\t/* -n option set and failed to lock */\n      exit(1);\n    case EINTR:\t\t\t/* Signal received */\n      if ( timeout_expired )\n\texit(1);\t\t/* -w option set and failed to lock */\n      continue;\t\t\t/* otherwise try again */\n    case EBADF:\t\t\t/* since Linux 3.4 (commit 55725513) */\n      /* Probably NFSv4 where flock() is emulated by fcntl().\n       * Let's try to reopen in read-write mode.\n       */\n      if (!(open_flags & O_RDWR) &&\n          type != LOCK_SH &&\n          filename &&\n          access(filename, R_OK | W_OK) == 0) {\n\n              close(fd);\n              open_flags = O_RDWR;\n              fd = open(filename, open_flags);\n              break;\n      }\n      /* go through */\n    default:\t\t\t/* Other errors */\n      if ( filename )\n\tfprintf(stderr, \"%s: %s: %s\\n\", program, filename, strerror(err));\n      else\n\tfprintf(stderr, \"%s: %d: %s\\n\", program, fd, strerror(err));\n      exit((err == ENOLCK||err == ENOMEM) ? EX_OSERR : EX_DATAERR);\n    }\n  }\n\n  if ( have_timeout ) {\n    setitimer(ITIMER_REAL, &old_timer, NULL); /* Cancel itimer */\n    sigaction(SIGALRM, &old_sa, NULL); /* Cancel signal handler */\n  }\n\n  status = 0;\n\n  if ( cmd_argv ) {\n    pid_t w, f;\n\n    /* Clear any inherited settings */\n    signal(SIGCHLD, SIG_DFL);\n    f = fork();\n\n    if ( f < 0 ) {\n      err = errno;\n      fprintf(stderr, _(\"%s: fork failed: %s\\n\"), program, strerror(err));\n      exit(EX_OSERR);\n    } else if ( f == 0 ) {\n      if ( do_close )\n\tclose(fd);\n      err = errno;\n      execvp(cmd_argv[0], cmd_argv);\n      /* execvp() failed */\n      fprintf(stderr, \"%s: %s: %s\\n\", program, cmd_argv[0], strerror(err));\n      _exit((err == ENOMEM) ? EX_OSERR: EX_UNAVAILABLE);\n    } else {\n      do {\n\tw = waitpid(f, &status, 0);\n\tif (w == -1 && errno != EINTR)\n\t  break;\n      } while ( w != f );\n\n      if (w == -1) {\n\terr = errno;\n\tstatus = EXIT_FAILURE;\n\tfprintf(stderr, \"%s: waitpid failed: %s\\n\", program, strerror(err));\n      } else if ( WIFEXITED(status) )\n\tstatus = WEXITSTATUS(status);\n      else if ( WIFSIGNALED(status) )\n\tstatus = WTERMSIG(status) + 128;\n      else\n\tstatus = EX_OSERR;\t/* WTF? */\n    }\n  }\n\n  return status;\n}\n\n"
  },
  {
    "path": "tools/genext2fs/Makefile",
    "content": "# \n# Copyright (C) 2006 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=genext2fs\nPKG_VERSION:=1.4.1\n\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz\nPKG_SOURCE_URL:=@SF/genext2fs\nPKG_HASH:=404dbbfa7a86a6c3de8225c8da254d026b17fd288e05cec4df2cc7e1f4feecfc\n\ninclude $(INCLUDE_DIR)/host-build.mk\n\nHOST_CONFIGURE_ARGS = \\\n\t--target=$(GNU_HOST_NAME) \\\n\t--host=$(GNU_HOST_NAME) \\\n\t--build=$(GNU_HOST_NAME) \\\n\t--program-prefix=\"\" \\\n\t--program-suffix=\"\" \\\n\t--prefix=/usr \\\n\t--exec-prefix=/usr \\\n\t--bindir=/usr/bin \\\n\t--sbindir=/usr/sbin \\\n\t--libexecdir=/usr/lib \\\n\t--sysconfdir=/etc \\\n\t--datadir=/usr/share \\\n\t--localstatedir=/var \\\n\t--mandir=/usr/man \\\n\t--infodir=/usr/info \\\n\ndefine Host/Compile\n\t$(MAKE) -C $(HOST_BUILD_DIR) \\\n\t\tCFLAGS=\"$(HOST_CFLAGS)\" \\\n\t\tLDFLAGS=\"$(HOST_LDFLAGS)\" \\\n\t\tall\nendef\n\ndefine Host/Install\n\tinstall -m0755 $(HOST_BUILD_DIR)/genext2fs $(STAGING_DIR_HOST)/bin/\nendef\n\ndefine Host/Clean\n\trm -f $(STAGING_DIR_HOST)/bin/genext2fs\nendef\n\n$(eval $(call HostBuild))\n"
  },
  {
    "path": "tools/genext2fs/patches/100-c99_scanf.patch",
    "content": "commit 3b8ca0ce9a0b58287a780747c90c449bdebfe464\nAuthor: Xavier Bestel <bestouff@users.sourceforge.net>\nDate:   Mon Jan 14 08:52:44 2008 +0000\n\n    removed use of %as is scanf (GNU conflicts with C99) by Giacomo Catenazzi <cate@debian.org>\n\ndiff --git a/genext2fs.c b/genext2fs.c\nindex 070b270..f0d797d 100644\n--- a/genext2fs.c\n+++ b/genext2fs.c\n@@ -286,7 +286,9 @@ typedef unsigned int uint32;\n // older solaris. Note that this is still not very portable, in that\n // the return value cannot be trusted.\n \n-#if SCANF_CAN_MALLOC\n+#if 0 // SCANF_CAN_MALLOC\n+// C99 define \"a\" for floating point, so you can have runtime surprise\n+// according the library versions\n # define SCANF_PREFIX \"a\"\n # define SCANF_STRING(s) (&s)\n #else\n"
  },
  {
    "path": "tools/genext2fs/patches/200-autoconf.patch",
    "content": "Index: genext2fs/m4/ac_func_scanf_can_malloc.m4\n===================================================================\n--- genext2fs.orig/m4/ac_func_scanf_can_malloc.m4\t2011-09-03 21:28:49.000000000 +0200\n+++ genext2fs/m4/ac_func_scanf_can_malloc.m4\t2011-09-03 21:29:41.000000000 +0200\n@@ -9,7 +9,7 @@\n # --------------------------------------\n AC_DEFUN([AC_FUNC_SCANF_CAN_MALLOC],\n   [ AC_CHECK_HEADERS([stdlib.h])\n-    AC_CACHE_CHECK([whether scanf can malloc], [ac_scanf_can_malloc],\n+    AC_CACHE_CHECK([whether scanf can malloc], [ac_cv_func_scanf_can_malloc],\n     [ AC_RUN_IFELSE(\n       [ AC_LANG_PROGRAM(\n         [\n"
  },
  {
    "path": "tools/genext2fs/patches/300-blocksize-creator.patch",
    "content": "Index: genext2fs/genext2fs.c\n===================================================================\n--- genext2fs.orig/genext2fs.c\t2011-09-03 14:21:17.000000000 +0200\n+++ genext2fs/genext2fs.c\t2011-09-03 14:21:17.000000000 +0200\n@@ -151,13 +151,24 @@\n \n // block size\n \n-#define BLOCKSIZE         1024\n+static int blocksize = 1024;\n+\n+#define BLOCKSIZE         blocksize\n #define BLOCKS_PER_GROUP  8192\n #define INODES_PER_GROUP  8192\n /* Percentage of blocks that are reserved.*/\n #define RESERVED_BLOCKS       5/100\n #define MAX_RESERVED_BLOCKS  25/100\n \n+/* The default value for s_creator_os. */\n+#if defined(__GNU__)\n+# define CREATOR_OS  1 /* Hurd */\n+#elif defined(__FreeBSD__)\n+# define CREATOR_OS  3 /* FreeBSD */\n+#else\n+# define CREATOR_OS  0 /* Linux */\n+#endif\n+\n \n // inode block size (why is it != BLOCKSIZE ?!?)\n /* The field i_blocks in the ext2 inode stores the number of data blocks\n@@ -239,10 +250,10 @@\n \t  (fs)->sb.s_blocks_per_group - 1) / (fs)->sb.s_blocks_per_group)\n \n // Get group block bitmap (bbm) given the group number\n-#define GRP_GET_GROUP_BBM(fs,grp) ( get_blk((fs),(fs)->gd[(grp)].bg_block_bitmap) )\n+#define GRP_GET_GROUP_BBM(fs,grp) ( get_blk((fs), get_gd((fs),(grp))->bg_block_bitmap) )\n \n // Get group inode bitmap (ibm) given the group number\n-#define GRP_GET_GROUP_IBM(fs,grp) ( get_blk((fs),(fs)->gd[(grp)].bg_inode_bitmap) )\n+#define GRP_GET_GROUP_IBM(fs,grp) ( get_blk((fs), get_gd((fs),(grp))->bg_inode_bitmap) )\n \t\t\n // Given an inode number find the group it belongs to\n #define GRP_GROUP_OF_INODE(fs,nod) ( ((nod)-1) / (fs)->sb.s_inodes_per_group)\n@@ -532,7 +543,7 @@\n \tchar d_name[0];\n } directory;\n \n-typedef uint8 block[BLOCKSIZE];\n+typedef uint8 *block;\n \n /* blockwalker fields:\n    The blockwalker is used to access all the blocks of a file (including\n@@ -571,16 +582,12 @@\n \n \n /* Filesystem structure that support groups */\n-#if BLOCKSIZE == 1024\n typedef struct\n {\n-\tblock zero;            // The famous block 0\n-\tsuperblock sb;         // The superblock\n-\tgroupdescriptor gd[0]; // The group descriptors\n+\tuint8 zero[1024];      // Room for bootloader stuff\n+\tsuperblock sb;         // The superblock, always at 1024\n+\t// group descriptors come next, see get_gd() below\n } filesystem;\n-#else\n-#error UNHANDLED BLOCKSIZE\n-#endif\n \n // now the endianness swap\n \n@@ -820,6 +827,14 @@\n \treturn (uint8*)fs + blk*BLOCKSIZE;\n }\n \n+// the group descriptors are aligned on the block size\n+static inline groupdescriptor *\n+get_gd(filesystem *fs, int no)\n+{\n+\tint gdblk = (sizeof (filesystem) + BLOCKSIZE - 1) / BLOCKSIZE;\n+\treturn ((groupdescriptor *) get_blk(fs, gdblk)) + no;\n+}\n+\n // return a given inode from a filesystem\n static inline inode *\n get_nod(filesystem *fs, uint32 nod)\n@@ -829,7 +844,7 @@\n \n \toffset = GRP_IBM_OFFSET(fs,nod);\n \tgrp = GRP_GROUP_OF_INODE(fs,nod);\n-\titab = (inode *)get_blk(fs, fs->gd[grp].bg_inode_table);\n+\titab = (inode *)get_blk(fs, get_gd(fs,grp)->bg_inode_table);\n \treturn itab+offset-1;\n }\n \n@@ -875,18 +890,18 @@\n \n \tgrp = GRP_GROUP_OF_INODE(fs,nod);\n \tnbgroups = GRP_NBGROUPS(fs);\n-\tif(!(bk = allocate(get_blk(fs,fs->gd[grp].bg_block_bitmap), 0))) {\n+\tif(!(bk = allocate(GRP_GET_GROUP_BBM(fs, grp), 0))) {\n \t\tfor(grp=0;grp<nbgroups && !bk;grp++)\n-\t\t\tbk=allocate(get_blk(fs,fs->gd[grp].bg_block_bitmap),0);\n+\t\t\tbk = allocate(GRP_GET_GROUP_BBM(fs, grp), 0);\n \t\tgrp--;\n \t}\n \tif (!bk)\n \t\terror_msg_and_die(\"couldn't allocate a block (no free space)\");\n-\tif(!(fs->gd[grp].bg_free_blocks_count--))\n+\tif(!(get_gd(fs, grp)->bg_free_blocks_count--))\n \t\terror_msg_and_die(\"group descr %d. free blocks count == 0 (corrupted fs?)\",grp);\n \tif(!(fs->sb.s_free_blocks_count--))\n \t\terror_msg_and_die(\"superblock free blocks count == 0 (corrupted fs?)\");\n-\treturn fs->sb.s_blocks_per_group*grp + bk;\n+\treturn fs->sb.s_first_data_block + fs->sb.s_blocks_per_group*grp + (bk-1);\n }\n \n // free a block\n@@ -897,8 +912,8 @@\n \n \tgrp = bk / fs->sb.s_blocks_per_group;\n \tbk %= fs->sb.s_blocks_per_group;\n-\tdeallocate(get_blk(fs,fs->gd[grp].bg_block_bitmap), bk);\n-\tfs->gd[grp].bg_free_blocks_count++;\n+\tdeallocate(GRP_GET_GROUP_BBM(fs, grp), bk);\n+\tget_gd(fs, grp)->bg_free_blocks_count++;\n \tfs->sb.s_free_blocks_count++;\n }\n \n@@ -918,16 +933,16 @@\n \t/* We do it for all inodes.                                           */\n \tavefreei  =  fs->sb.s_free_inodes_count / nbgroups;\n \tfor(grp=0; grp<nbgroups; grp++) {\n-\t\tif (fs->gd[grp].bg_free_inodes_count < avefreei ||\n-\t\t    fs->gd[grp].bg_free_inodes_count == 0)\n+\t\tif (get_gd(fs, grp)->bg_free_inodes_count < avefreei ||\n+\t\t    get_gd(fs, grp)->bg_free_inodes_count == 0)\n \t\t\tcontinue;\n \t\tif (!best_group || \n-\t\t\tfs->gd[grp].bg_free_blocks_count > fs->gd[best_group].bg_free_blocks_count)\n+\t\t\tget_gd(fs, grp)->bg_free_blocks_count > get_gd(fs, best_group)->bg_free_blocks_count)\n \t\t\tbest_group = grp;\n \t}\n-\tif (!(nod = allocate(get_blk(fs,fs->gd[best_group].bg_inode_bitmap),0)))\n+\tif (!(nod = allocate(GRP_GET_GROUP_IBM(fs, best_group), 0)))\n \t\terror_msg_and_die(\"couldn't allocate an inode (no free inode)\");\n-\tif(!(fs->gd[best_group].bg_free_inodes_count--))\n+\tif(!(get_gd(fs, best_group)->bg_free_inodes_count--))\n \t\terror_msg_and_die(\"group descr. free blocks count == 0 (corrupted fs?)\");\n \tif(!(fs->sb.s_free_inodes_count--))\n \t\terror_msg_and_die(\"superblock free blocks count == 0 (corrupted fs?)\");\n@@ -1390,7 +1405,7 @@\n \t\t\tcase FM_IFDIR:\n \t\t\t\tadd2dir(fs, nod, nod, \".\");\n \t\t\t\tadd2dir(fs, nod, parent_nod, \"..\");\n-\t\t\t\tfs->gd[GRP_GROUP_OF_INODE(fs,nod)].bg_used_dirs_count++;\n+\t\t\t\tget_gd(fs, GRP_GROUP_OF_INODE(fs,nod))->bg_used_dirs_count++;\n \t\t\t\tbreak;\n \t\t}\n \t}\n@@ -1860,7 +1875,7 @@\n \t\tswap_nod(nod);\n \t}\n \tfor(i=0;i<GRP_NBGROUPS(fs);i++)\n-\t\tswap_gd(&(fs->gd[i]));\n+\t\tswap_gd(get_gd(fs, i));\n \tswap_sb(&fs->sb);\n }\n \n@@ -1870,7 +1885,7 @@\n \tuint32 i;\n \tswap_sb(&fs->sb);\n \tfor(i=0;i<GRP_NBGROUPS(fs);i++)\n-\t\tswap_gd(&(fs->gd[i]));\n+\t\tswap_gd(get_gd(fs, i));\n \tfor(i = 1; i < fs->sb.s_inodes_count; i++)\n \t{\n \t\tinode *nod = get_nod(fs, i);\n@@ -1895,7 +1910,8 @@\n \n // initialize an empty filesystem\n static filesystem *\n-init_fs(int nbblocks, int nbinodes, int nbresrvd, int holes, uint32 fs_timestamp)\n+init_fs(int nbblocks, int nbinodes, int nbresrvd, int holes,\n+\t\tuint32 fs_timestamp, uint32 creator_os)\n {\n \tuint32 i;\n \tfilesystem *fs;\n@@ -1921,10 +1937,14 @@\n \t */\n \tmin_nbgroups = (nbinodes + INODES_PER_GROUP - 1) / INODES_PER_GROUP;\n \n+\t/* On filesystems with 1k block size, the bootloader area uses a full\n+\t * block. For 2048 and up, the superblock can be fitted into block 0.\n+\t */\n+\tfirst_block = (BLOCKSIZE == 1024);\n+\n \t/* nbblocks is the total number of blocks in the filesystem.\n \t * a block group can have no more than 8192 blocks.\n \t */\n-\tfirst_block = (BLOCKSIZE == 1024);\n \tnbgroups = (nbblocks - first_block + BLOCKS_PER_GROUP - 1) / BLOCKS_PER_GROUP;\n \tif(nbgroups < min_nbgroups) nbgroups = min_nbgroups;\n \tnbblocks_per_group = rndup((nbblocks - first_block + nbgroups - 1)/nbgroups, 8);\n@@ -1936,10 +1956,10 @@\n \tgdsz = rndup(nbgroups*sizeof(groupdescriptor),BLOCKSIZE)/BLOCKSIZE;\n \titblsz = nbinodes_per_group * sizeof(inode)/BLOCKSIZE;\n \toverhead_per_group = 3 /*sb,bbm,ibm*/ + gdsz + itblsz;\n-\tif((uint32)nbblocks - 1 < overhead_per_group * nbgroups)\n-\t\terror_msg_and_die(\"too much overhead, try fewer inodes or more blocks. Note: options have changed, see --help or the man page.\");\n-\tfree_blocks = nbblocks - overhead_per_group*nbgroups - 1 /*boot block*/;\n+\tfree_blocks = nbblocks - overhead_per_group*nbgroups - first_block;\n \tfree_blocks_per_group = nbblocks_per_group - overhead_per_group;\n+\tif(free_blocks < 0)\n+\t\terror_msg_and_die(\"too much overhead, try fewer inodes or more blocks. Note: options have changed, see --help or the man page.\");\n \n \tif(!(fs = (filesystem*)calloc(nbblocks, BLOCKSIZE)))\n \t\terror_msg_and_die(\"not enough memory for filesystem\");\n@@ -1959,28 +1979,31 @@\n \tfs->sb.s_wtime = fs_timestamp;\n \tfs->sb.s_magic = EXT2_MAGIC_NUMBER;\n \tfs->sb.s_lastcheck = fs_timestamp;\n+\tfs->sb.s_creator_os = creator_os;\n \n \t// set up groupdescriptors\n-\tfor(i=0, bbmpos=gdsz+2, ibmpos=bbmpos+1, itblpos=ibmpos+1;\n+\tfor(i=0, bbmpos=first_block+1+gdsz, ibmpos=bbmpos+1, itblpos=ibmpos+1;\n \t\ti<nbgroups;\n \t\ti++, bbmpos+=nbblocks_per_group, ibmpos+=nbblocks_per_group, itblpos+=nbblocks_per_group)\n \t{\n+\t\tgroupdescriptor *gd = get_gd(fs, i);\n+\n \t\tif(free_blocks > free_blocks_per_group) {\n-\t\t\tfs->gd[i].bg_free_blocks_count = free_blocks_per_group;\n+\t\t\tgd->bg_free_blocks_count = free_blocks_per_group;\n \t\t\tfree_blocks -= free_blocks_per_group;\n \t\t} else {\n-\t\t\tfs->gd[i].bg_free_blocks_count = free_blocks;\n+\t\t\tgd->bg_free_blocks_count = free_blocks;\n \t\t\tfree_blocks = 0; // this is the last block group\n \t\t}\n \t\tif(i)\n-\t\t\tfs->gd[i].bg_free_inodes_count = nbinodes_per_group;\n+\t\t\tgd->bg_free_inodes_count = nbinodes_per_group;\n \t\telse\n-\t\t\tfs->gd[i].bg_free_inodes_count = nbinodes_per_group -\n+\t\t\tgd->bg_free_inodes_count = nbinodes_per_group -\n \t\t\t\t\t\t\tEXT2_FIRST_INO + 2;\n-\t\tfs->gd[i].bg_used_dirs_count = 0;\n-\t\tfs->gd[i].bg_block_bitmap = bbmpos;\n-\t\tfs->gd[i].bg_inode_bitmap = ibmpos;\n-\t\tfs->gd[i].bg_inode_table = itblpos;\n+\t\tgd->bg_used_dirs_count = 0;\n+\t\tgd->bg_block_bitmap = bbmpos;\n+\t\tgd->bg_inode_bitmap = ibmpos;\n+\t\tgd->bg_inode_table = itblpos;\n \t}\n \n \t/* Mark non-filesystem blocks and inodes as allocated */\n@@ -1988,9 +2011,9 @@\n \tfor(i = 0; i<nbgroups;i++) {\n \n \t\t/* Block bitmap */\n-\t\tbbm = get_blk(fs,fs->gd[i].bg_block_bitmap);\t\n+\t\tbbm = GRP_GET_GROUP_BBM(fs, i);\n \t\t//non-filesystem blocks\n-\t\tfor(j = fs->gd[i].bg_free_blocks_count\n+\t\tfor(j = get_gd(fs, i)->bg_free_blocks_count\n \t\t        + overhead_per_group + 1; j <= BLOCKSIZE * 8; j++)\n \t\t\tallocate(bbm, j); \n \t\t//system blocks\n@@ -1998,7 +2021,7 @@\n \t\t\tallocate(bbm, j); \n \t\t\n \t\t/* Inode bitmap */\n-\t\tibm = get_blk(fs,fs->gd[i].bg_inode_bitmap);\t\n+\t\tibm = GRP_GET_GROUP_IBM(fs, i);\n \t\t//non-filesystem inodes\n \t\tfor(j = fs->sb.s_inodes_per_group+1; j <= BLOCKSIZE * 8; j++)\n \t\t\tallocate(ibm, j);\n@@ -2012,9 +2035,9 @@\n \t// make root inode and directory\n \t/* We have groups now. Add the root filesystem in group 0 */\n \t/* Also increment the directory count for group 0 */\n-\tfs->gd[0].bg_free_inodes_count--;\n-\tfs->gd[0].bg_used_dirs_count = 1;\n-\titab0 = (inode *)get_blk(fs,fs->gd[0].bg_inode_table);\n+\tget_gd(fs, 0)->bg_free_inodes_count--;\n+\tget_gd(fs, 0)->bg_used_dirs_count = 1;\n+\titab0 = (inode *)get_blk(fs, get_gd(fs,0)->bg_inode_table);\n \titab0[EXT2_ROOT_INO-1].i_mode = FM_IFDIR | FM_IRWXU | FM_IRGRP | FM_IROTH | FM_IXGRP | FM_IXOTH; \n \titab0[EXT2_ROOT_INO-1].i_ctime = fs_timestamp;\n \titab0[EXT2_ROOT_INO-1].i_mtime = fs_timestamp;\n@@ -2338,8 +2361,9 @@\n \tfor (i = 0; i < GRP_NBGROUPS(fs); i++) {\n \t\tprintf(\"Group No: %d\\n\", i+1);\n \t\tprintf(\"block bitmap: block %d,inode bitmap: block %d, inode table: block %d\\n\",\n-\t\t     fs->gd[i].bg_block_bitmap, fs->gd[i].bg_inode_bitmap,\n-\t\t     fs->gd[i].bg_inode_table);\n+\t\t     get_gd(fs, i)->bg_block_bitmap,\n+\t\t     get_gd(fs, i)->bg_inode_bitmap,\n+\t\t     get_gd(fs, i)->bg_inode_table);\n \t\tprintf(\"block bitmap allocation:\\n\");\n \t\tprint_bm(GRP_GET_GROUP_BBM(fs, i),fs->sb.s_blocks_per_group);\n \t\tprintf(\"inode bitmap allocation:\\n\");\n@@ -2421,10 +2445,12 @@\n \t\"  -x, --starting-image <image>\\n\"\n \t\"  -d, --root <directory>\\n\"\n \t\"  -D, --devtable <file>\\n\"\n+\t\"  -B, --block-size <bytes>\\n\"\n \t\"  -b, --size-in-blocks <blocks>\\n\"\n \t\"  -i, --bytes-per-inode <bytes per inode>\\n\"\n \t\"  -N, --number-of-inodes <number of inodes>\\n\"\n \t\"  -m, --reserved-percentage <percentage of blocks to reserve>\\n\"\n+\t\"  -o, --creator-os <os>      'linux', 'hurd', 'freebsd' or a numerical value.\\n\"\n \t\"  -g, --block-map <path>     Generate a block map file for this path.\\n\"\n \t\"  -e, --fill-value <value>   Fill unallocated blocks with value.\\n\"\n \t\"  -z, --allow-holes          Allow files with holes.\\n\"\n@@ -2446,6 +2472,29 @@\n extern char* optarg;\n extern int optind, opterr, optopt;\n \n+// parse the value for -o <os>\n+int\n+lookup_creator_os(const char *name)\n+{\n+\tstatic const char *const creators[] =\n+\t\t{\"linux\", \"hurd\", \"2\", \"freebsd\", NULL};\n+\tchar *endptr;\n+\tint i;\n+\n+\t// numerical value ?\n+\ti = strtol(name, &endptr, 0);\n+\tif(name[0] && *endptr == '\\0')\n+\t\treturn i;\n+\n+\t// symbolic name ?\n+\tfor(i=0; creators[i]; i++)\n+\t       if(strcasecmp(creators[i], name) == 0)\n+\t\t       return i;\n+\n+\t// whatever ?\n+\treturn -1;\n+}\n+\n int\n main(int argc, char **argv)\n {\n@@ -2455,6 +2504,7 @@\n \tfloat bytes_per_inode = -1;\n \tfloat reserved_frac = -1;\n \tint fs_timestamp = -1;\n+\tint creator_os = CREATOR_OS;\n \tchar * fsout = \"-\";\n \tchar * fsin = 0;\n \tchar * dopt[MAX_DOPT];\n@@ -2478,10 +2528,12 @@\n \t  { \"starting-image\",\trequired_argument,\tNULL, 'x' },\n \t  { \"root\",\t\trequired_argument,\tNULL, 'd' },\n \t  { \"devtable\",\t\trequired_argument,\tNULL, 'D' },\n+\t  { \"block-size\",\trequired_argument,\tNULL, 'B' },\n \t  { \"size-in-blocks\",\trequired_argument,\tNULL, 'b' },\n \t  { \"bytes-per-inode\",\trequired_argument,\tNULL, 'i' },\n \t  { \"number-of-inodes\",\trequired_argument,\tNULL, 'N' },\n \t  { \"reserved-percentage\", required_argument,\tNULL, 'm' },\n+\t  { \"creator-os\",\trequired_argument,\tNULL, 'o' },\n \t  { \"block-map\",\trequired_argument,\tNULL, 'g' },\n \t  { \"fill-value\",\trequired_argument,\tNULL, 'e' },\n \t  { \"allow-holes\",\tno_argument, \t\tNULL, 'z' },\n@@ -2497,11 +2549,11 @@\n \n \tapp_name = argv[0];\n \n-\twhile((c = getopt_long(argc, argv, \"x:d:D:b:i:N:m:g:e:zfqUPhVv\", longopts, NULL)) != EOF) {\n+\twhile((c = getopt_long(argc, argv, \"x:d:D:B:b:i:N:m:o:g:e:zfqUPhVv\", longopts, NULL)) != EOF) {\n #else\n \tapp_name = argv[0];\n \n-\twhile((c = getopt(argc, argv,      \"x:d:D:b:i:N:m:g:e:zfqUPhVv\")) != EOF) {\n+\twhile((c = getopt(argc, argv,      \"x:d:D:B:b:i:N:m:o:g:e:zfqUPhVv\")) != EOF) {\n #endif /* HAVE_GETOPT_LONG */\n \t\tswitch(c)\n \t\t{\n@@ -2512,6 +2564,9 @@\n \t\t\tcase 'D':\n \t\t\t\tdopt[didx++] = optarg;\n \t\t\t\tbreak;\n+\t\t\tcase 'B':\n+\t\t\t\tblocksize = SI_atof(optarg);\n+\t\t\t\tbreak;\n \t\t\tcase 'b':\n \t\t\t\tnbblocks = SI_atof(optarg);\n \t\t\t\tbreak;\n@@ -2524,6 +2579,9 @@\n \t\t\tcase 'm':\n \t\t\t\treserved_frac = SI_atof(optarg) / 100;\n \t\t\t\tbreak;\n+\t\t\tcase 'o':\n+\t\t\t\tcreator_os = lookup_creator_os(optarg);\n+\t\t\t\tbreak;\n \t\t\tcase 'g':\n \t\t\t\tgopt[gidx++] = optarg;\n \t\t\t\tbreak;\n@@ -2567,6 +2625,11 @@\n \t\terror_msg_and_die(\"Not enough arguments. Try --help or else see the man page.\");\n \tfsout = argv[optind];\n \n+\tif(blocksize != 1024 && blocksize != 2048 && blocksize != 4096)\n+\t\terror_msg_and_die(\"Valid block sizes: 1024, 2048 or 4096.\");\n+\tif(creator_os < 0)\n+\t\terror_msg_and_die(\"Creator OS unknown.\");\n+\n \thdlinks.hdl = (struct hdlink_s *)malloc(hdlink_cnt * sizeof(struct hdlink_s));\n \tif (!hdlinks.hdl)\n \t\terror_msg_and_die(\"Not enough memory\");\n@@ -2611,7 +2674,8 @@\n \t\t}\n \t\tif(fs_timestamp == -1)\n \t\t\tfs_timestamp = time(NULL);\n-\t\tfs = init_fs(nbblocks, nbinodes, nbresrvd, holes, fs_timestamp);\n+\t\tfs = init_fs(nbblocks, nbinodes, nbresrvd, holes,\n+\t\t\t\tfs_timestamp, creator_os);\n \t}\n \t\n \tpopulate_fs(fs, dopt, didx, squash_uids, squash_perms, fs_timestamp, NULL);\nIndex: genext2fs/test-gen.lib\n===================================================================\n--- genext2fs.orig/test-gen.lib\t2011-09-03 13:40:35.000000000 +0200\n+++ genext2fs/test-gen.lib\t2011-09-03 14:21:17.000000000 +0200\n@@ -8,7 +8,7 @@\n # Creates an image with a file of given size\n # Usage: dgen file-size number-of-blocks \n dgen () {\n-\tsize=$1; blocks=$2\n+\tsize=$1; blocks=$2; blocksz=$3;\n \trm -rf test\n \tmkdir -p test\n \tcd test\n@@ -20,7 +20,7 @@\n         chmod 777 file.$1\n \tTZ=UTC-11 touch -t 200502070321.43 file.$1 .\n \tcd ..\n-\t./genext2fs -N 17 -b $blocks -d test -f -q ext2.img \n+\t./genext2fs -B $blocksz -N 17 -b $blocks -d test -f -o Linux -q ext2.img\n }\n \n # fgen - Exercises the -f spec-file option of genext2fs\n@@ -31,7 +31,7 @@\n \tmkdir -p test\n \tcp $fname test\n \tTZ=UTC-11 touch -t 200502070321.43 test/$fname\n-\t./genext2fs -N 92 -b $blocks -D test/$fname -f ext2.img\n+\t./genext2fs -N 92 -b $blocks -D test/$fname -f -o Linux ext2.img\n }\n \n # gen_cleanup - Remove the files generated by the above functions\nIndex: genext2fs/test-mount.sh\n===================================================================\n--- genext2fs.orig/test-mount.sh\t2011-09-03 13:40:35.000000000 +0200\n+++ genext2fs/test-mount.sh\t2011-09-03 14:21:17.000000000 +0200\n@@ -33,9 +33,9 @@\n # and returns the command line with which to invoke dtest()\n # Usage: dtest-mount file-size number-of-blocks \n dtest_mount () {\n-\tsize=$1; blocks=$2\n-\techo Testing with file of size $size\n-\tdgen $size $blocks\n+\tsize=$1; blocks=$2; blocksz=$3;\n+\techo Testing $blocks blocks of $blocksz bytes with file of size $size\n+\tdgen $size $blocks $blocksz\n \t/sbin/e2fsck -fn ext2.img || fail\n \tmkdir -p mnt\n \tmount -t ext2 -o ro,loop ext2.img mnt || fail\n@@ -44,7 +44,7 @@\n \t                                awk '{print $5}'`\" ] ; then\n \t\tfail\n \tfi\n-\tpass dtest $size $blocks\n+\tpass dtest $size $blocks $blocksz\n }\n \n # ftest-mount - Exercise the -f spec-file option of genext2fs\n@@ -75,13 +75,21 @@\n \tpass ftest $fname $blocks\n }\n \n-dtest_mount 0 4096 \n-dtest_mount 0 8193\n-dtest_mount 0 8194\n-dtest_mount 1 4096 \n-dtest_mount 12288 4096 \n-dtest_mount 274432 4096 \n-dtest_mount 8388608 9000 \n-dtest_mount 16777216 20000\n+dtest_mount 0 4096 1024\n+dtest_mount 0 2048 2048\n+dtest_mount 0 1024 4096\n+dtest_mount 0 8193 1024\n+dtest_mount 0 8194 1024\n+dtest_mount 0 8193 4096\n+dtest_mount 0 8194 2048\n+dtest_mount 1 4096 1024\n+dtest_mount 1 1024 4096\n+dtest_mount 12288 4096 1024\n+dtest_mount 274432 4096 1024\n+dtest_mount 8388608 9000 1024\n+dtest_mount 8388608 4500 2048\n+dtest_mount 8388608 2250 4096\n+dtest_mount 16777216 20000 1024\n+dtest_mount 16777216 10000 2048\n \n ftest_mount device_table.txt 4096 \nIndex: genext2fs/test.sh\n===================================================================\n--- genext2fs.orig/test.sh\t2011-09-03 13:40:35.000000000 +0200\n+++ genext2fs/test.sh\t2011-09-03 14:21:17.000000000 +0200\n@@ -30,9 +30,9 @@\n # Creates an image with a file of given size and verifies it\n # Usage: dtest file-size number-of-blocks correct-checksum\n dtest () {\n-\tsize=$1; blocks=$2; checksum=$3\n+\tsize=$1; blocks=$2; blocksz=$3; checksum=$4\n \techo Testing with file of size $size\n-\tdgen $size $blocks\n+\tdgen $size $blocks $blocksz\n \tmd5cmp $checksum\n \tgen_cleanup\n }\n@@ -53,12 +53,20 @@\n # replace the following lines with the output of\n # sudo sh test-mount.sh|grep test\n \n-dtest 0 4096 3bc6424b8fcd51a0de34ee59d91d5f16\n-dtest 0 8193 f174804f6b433b552706cbbfc60c416d\n-dtest 0 8194 4855a55d0cbdc44584634df49ebd5711\n-dtest 1 4096 09c569b6bfb45222c729c42d04d5451f\n-dtest 12288 4096 61febcbfbf32024ef99103fcdc282c39\n-dtest 274432 4096 0c517803552c55c1806e4220b0a0164f\n-dtest 8388608 9000 e0e5ea15bced10ab486d8135584b5d8e\n-dtest 16777216 20000 fdf636eb905ab4dc1bf76dce5ac5d209\n+dtest 0 4096 1024 3bc6424b8fcd51a0de34ee59d91d5f16\n+dtest 0 2048 2048 230afa16496df019878cc2370c661cdc\n+dtest 0 1024 4096 ebff5eeb38b70f3f1cd081e60eb44561\n+dtest 0 8193 1024 f174804f6b433b552706cbbfc60c416d\n+dtest 0 8194 1024 4855a55d0cbdc44584634df49ebd5711\n+dtest 0 8193 4096 c493679698418ec7e6552005e2d2a6d8\n+dtest 0 8194 2048 ec13f328fa7543563f35f494bddc059c\n+dtest 1 4096 1024 09c569b6bfb45222c729c42d04d5451f\n+dtest 1 1024 4096 d318a326fdc907810ae9e6b0a20e9b06\n+dtest 12288 4096 1024 61febcbfbf32024ef99103fcdc282c39\n+dtest 274432 4096 1024 0c517803552c55c1806e4220b0a0164f\n+dtest 8388608 9000 1024 e0e5ea15bced10ab486d8135584b5d8e\n+dtest 8388608 4500 2048 39f4d537a72f5053fd6891721c59680d\n+dtest 8388608 2250 4096 1d697fa4bc2cfffe02ac91edfadc40bf\n+dtest 16777216 20000 1024 fdf636eb905ab4dc1bf76dce5ac5d209\n+dtest 16777216 10000 2048 f9824a81ea5e74fdf469c097927c292b\n ftest device_table.txt 4096 a0af06d944b11d2902dfd705484c64cc\n"
  },
  {
    "path": "tools/genext2fs/patches/400-byteswap_fix.patch",
    "content": "Index: genext2fs/genext2fs.c\n===================================================================\n--- genext2fs.orig/genext2fs.c\t2011-11-29 17:36:06.000000000 +0100\n+++ genext2fs/genext2fs.c\t2011-11-29 17:37:37.000000000 +0100\n@@ -1779,7 +1779,8 @@\n \tassert(nod->i_block[EXT2_DIND_BLOCK] != 0);\n \tfor(i = 0; i < BLOCKSIZE/4; i++)\n \t\tif(nblk > EXT2_IND_BLOCK + BLOCKSIZE/4 + (BLOCKSIZE/4)*i )\n-\t\t\tswap_block(get_blk(fs, ((uint32*)get_blk(fs, nod->i_block[EXT2_DIND_BLOCK]))[i]));\n+\t\t\tif (((uint32*)get_blk(fs, nod->i_block[EXT2_DIND_BLOCK]))[i])\n+\t\t\t\tswap_block(get_blk(fs, ((uint32*)get_blk(fs, nod->i_block[EXT2_DIND_BLOCK]))[i]));\n \tswap_block(get_blk(fs, nod->i_block[EXT2_DIND_BLOCK]));\n \tif(nblk <= EXT2_IND_BLOCK + BLOCKSIZE/4 + BLOCKSIZE/4 * BLOCKSIZE/4)\n \t\treturn;\n@@ -1792,7 +1793,8 @@\n \t\t\t\t     (BLOCKSIZE/4)*(BLOCKSIZE/4) + \n \t\t\t\t     i*(BLOCKSIZE/4)*(BLOCKSIZE/4) + \n \t\t\t\t     j*(BLOCKSIZE/4)) ) \n-\t\t\t  swap_block(get_blk(fs,b2[j]));\n+\t\t\t  if (b2[j])\n+\t\t\t  \tswap_block(get_blk(fs,b2[j]));\n \t\t\telse {\n \t\t\t  done = 1;\n \t\t\t  break;\n@@ -1825,7 +1827,8 @@\n \tswap_block(get_blk(fs, nod->i_block[EXT2_DIND_BLOCK]));\n \tfor(i = 0; i < BLOCKSIZE/4; i++)\n \t\tif(nblk > EXT2_IND_BLOCK + BLOCKSIZE/4 + (BLOCKSIZE/4)*i )\n-\t\t\tswap_block(get_blk(fs, ((uint32*)get_blk(fs, nod->i_block[EXT2_DIND_BLOCK]))[i]));\n+\t\t\tif (((uint32*)get_blk(fs, nod->i_block[EXT2_DIND_BLOCK]))[i])\n+\t\t\t\tswap_block(get_blk(fs, ((uint32*)get_blk(fs, nod->i_block[EXT2_DIND_BLOCK]))[i]));\n \tif(nblk <= EXT2_IND_BLOCK + BLOCKSIZE/4 + BLOCKSIZE/4 * BLOCKSIZE/4)\n \t\treturn;\n \t/* Adding support for triple indirection */\n@@ -1839,7 +1842,8 @@\n \t\t\t\t     (BLOCKSIZE/4)*(BLOCKSIZE/4) + \n \t\t\t\t     i*(BLOCKSIZE/4)*(BLOCKSIZE/4) + \n \t\t\t\t     j*(BLOCKSIZE/4)) ) \n-\t\t\t  swap_block(get_blk(fs,b2[j]));\n+\t\t\t  if (b2[j])\n+\t\t\t\tswap_block(get_blk(fs,b2[j]));\n \t\t\telse {\n \t\t\t  done = 1;\n \t\t\t  break;\n"
  },
  {
    "path": "tools/gengetopt/Makefile",
    "content": "#\n# Copyright (C) 2014 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=gengetopt\nPKG_VERSION:=2.23\n\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz\nPKG_SOURCE_URL:=@GNU/$(PKG_NAME)\nPKG_HASH:=b941aec9011864978dd7fdeb052b1943535824169d2aa2b0e7eae9ab807584ac\n\nHOST_FIXUP:=autoreconf\n\nHOST_BUILD_PARALLEL:=1\n\ninclude $(INCLUDE_DIR)/host-build.mk\n\ndefine Host/Install\n\t$(INSTALL_BIN) $(HOST_BUILD_DIR)/src/gengetopt $(STAGING_DIR_HOST)/bin/\nendef\n\ndefine Host/Clean\n\trm -f $(STAGING_DIR_HOST)/bin/gengetopt\nendef\n\n$(eval $(call HostBuild))\n"
  },
  {
    "path": "tools/gengetopt/patches/100-no-tests-docs.patch",
    "content": "--- a/Makefile.am\n+++ b/Makefile.am\n@@ -18,7 +18,7 @@\n ACLOCAL_AMFLAGS = -I m4 -I gl/m4\n \n EXTRA_DIST = configure TODO LICENSE gl/m4/gnulib-cache.m4\n-SUBDIRS = gl src doc tests\n+SUBDIRS = gl src\n \n gengetoptdoc_DATA = ChangeLog COPYING NEWS THANKS INSTALL README LICENSE\n \n--- a/Makefile.in\n+++ b/Makefile.in\n@@ -593,7 +593,7 @@ top_builddir = @top_builddir@\n top_srcdir = @top_srcdir@\n ACLOCAL_AMFLAGS = -I m4 -I gl/m4\n EXTRA_DIST = configure TODO LICENSE gl/m4/gnulib-cache.m4\n-SUBDIRS = gl src doc tests\n+SUBDIRS = gl src\n gengetoptdoc_DATA = ChangeLog COPYING NEWS THANKS INSTALL README LICENSE\n TARBALL = $(top_builddir)/gengetopt-$(PACKAGE_VERSION).tar.xz\n all: config.h\n--- a/src/Makefile.am\n+++ b/src/Makefile.am\n@@ -16,7 +16,7 @@\n # with gengetopt; see the file COPYING. If not, write to the Free Software \n # Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. \n \n-SUBDIRS = skels tests\n+SUBDIRS = skels\n \n bin_PROGRAMS = gengetopt\n \n"
  },
  {
    "path": "tools/gmp/Makefile",
    "content": "#\n# Copyright (C) 2009-2016 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=gmp\nPKG_VERSION:=6.2.1\n\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz\nPKG_SOURCE_URL:=@GNU/gmp/\nPKG_HASH:=fd4829912cddd12f84181c3451cc752be224643e87fac497b69edddadc49b4f2\n\nHOST_FIXUP:=autoreconf\n\nHOST_BUILD_PARALLEL:=1\n\ninclude $(INCLUDE_DIR)/host-build.mk\n\nunexport CFLAGS\n\nHOST_CONFIGURE_ARGS += \\\n\t--enable-static \\\n\t--disable-shared \\\n\t--disable-assembly \\\n\t--enable-cxx\n\nifeq ($(GNU_HOST_NAME),x86_64-linux-gnux32)\nHOST_CONFIGURE_ARGS += ABI=x32\nendif\n\n$(eval $(call HostBuild))\n"
  },
  {
    "path": "tools/include/asm/types.h",
    "content": "/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */\n/*\n * asm-generic/int-ll64.h\n *\n * Integer declarations for architectures which use \"long long\"\n * for 64-bit types.\n */\n\n#ifndef _ASM_GENERIC_INT_LL64_H\n#define _ASM_GENERIC_INT_LL64_H\n\ntypedef __signed__ char __s8;\n\ntypedef __signed__ short __s16;\n\ntypedef __signed__ int __s32;\n\n#ifdef __GNUC__\n__extension__ typedef __signed__ long long __s64;\n#else\ntypedef __signed__ long long __s64;\n#endif\n\n#endif /* _ASM_GENERIC_INT_LL64_H */\n"
  },
  {
    "path": "tools/include/byteswap.h",
    "content": "#if defined(__linux__) || defined(__CYGWIN__) \n#include_next <byteswap.h>\n#else\n#include <endian.h>\n#endif\n"
  },
  {
    "path": "tools/include/elf.h",
    "content": "/* This file defines standard ELF types, structures, and macros.\n   Copyright (C) 1995-2012 Free Software Foundation, Inc.\n   This file is part of the GNU C Library.\n\n   The GNU C Library is free software; you can redistribute it and/or\n   modify it under the terms of the GNU Lesser General Public\n   License as published by the Free Software Foundation; either\n   version 2.1 of the License, or (at your option) any later version.\n\n   The GNU C Library is distributed in the hope that it will be useful,\n   but WITHOUT ANY WARRANTY; without even the implied warranty of\n   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\n   Lesser General Public License for more details.\n\n   You should have received a copy of the GNU Lesser General Public\n   License along with the GNU C Library; if not, see\n   <http://www.gnu.org/licenses/>.  */\n\n#ifndef _ELF_H\n#define\t_ELF_H 1\n\n/* Standard ELF types.  */\n\n#include <stdint.h>\n\n/* Type for a 16-bit quantity.  */\ntypedef uint16_t Elf32_Half;\ntypedef uint16_t Elf64_Half;\n\n/* Types for signed and unsigned 32-bit quantities.  */\ntypedef uint32_t Elf32_Word;\ntypedef\tint32_t  Elf32_Sword;\ntypedef uint32_t Elf64_Word;\ntypedef\tint32_t  Elf64_Sword;\n\n/* Types for signed and unsigned 64-bit quantities.  */\ntypedef uint64_t Elf32_Xword;\ntypedef\tint64_t  Elf32_Sxword;\ntypedef uint64_t Elf64_Xword;\ntypedef\tint64_t  Elf64_Sxword;\n\n/* Type of addresses.  */\ntypedef uint32_t Elf32_Addr;\ntypedef uint64_t Elf64_Addr;\n\n/* Type of file offsets.  */\ntypedef uint32_t Elf32_Off;\ntypedef uint64_t Elf64_Off;\n\n/* Type for section indices, which are 16-bit quantities.  */\ntypedef uint16_t Elf32_Section;\ntypedef uint16_t Elf64_Section;\n\n/* Type for version symbol information.  */\ntypedef Elf32_Half Elf32_Versym;\ntypedef Elf64_Half Elf64_Versym;\n\n\n/* The ELF file header.  This appears at the start of every ELF file.  */\n\n#define EI_NIDENT (16)\n\ntypedef struct\n{\n  unsigned char\te_ident[EI_NIDENT];\t/* Magic number and other info */\n  Elf32_Half\te_type;\t\t\t/* Object file type */\n  Elf32_Half\te_machine;\t\t/* Architecture */\n  Elf32_Word\te_version;\t\t/* Object file version */\n  Elf32_Addr\te_entry;\t\t/* Entry point virtual address */\n  Elf32_Off\te_phoff;\t\t/* Program header table file offset */\n  Elf32_Off\te_shoff;\t\t/* Section header table file offset */\n  Elf32_Word\te_flags;\t\t/* Processor-specific flags */\n  Elf32_Half\te_ehsize;\t\t/* ELF header size in bytes */\n  Elf32_Half\te_phentsize;\t\t/* Program header table entry size */\n  Elf32_Half\te_phnum;\t\t/* Program header table entry count */\n  Elf32_Half\te_shentsize;\t\t/* Section header table entry size */\n  Elf32_Half\te_shnum;\t\t/* Section header table entry count */\n  Elf32_Half\te_shstrndx;\t\t/* Section header string table index */\n} Elf32_Ehdr;\n\ntypedef struct\n{\n  unsigned char\te_ident[EI_NIDENT];\t/* Magic number and other info */\n  Elf64_Half\te_type;\t\t\t/* Object file type */\n  Elf64_Half\te_machine;\t\t/* Architecture */\n  Elf64_Word\te_version;\t\t/* Object file version */\n  Elf64_Addr\te_entry;\t\t/* Entry point virtual address */\n  Elf64_Off\te_phoff;\t\t/* Program header table file offset */\n  Elf64_Off\te_shoff;\t\t/* Section header table file offset */\n  Elf64_Word\te_flags;\t\t/* Processor-specific flags */\n  Elf64_Half\te_ehsize;\t\t/* ELF header size in bytes */\n  Elf64_Half\te_phentsize;\t\t/* Program header table entry size */\n  Elf64_Half\te_phnum;\t\t/* Program header table entry count */\n  Elf64_Half\te_shentsize;\t\t/* Section header table entry size */\n  Elf64_Half\te_shnum;\t\t/* Section header table entry count */\n  Elf64_Half\te_shstrndx;\t\t/* Section header string table index */\n} Elf64_Ehdr;\n\n/* Fields in the e_ident array.  The EI_* macros are indices into the\n   array.  The macros under each EI_* macro are the values the byte\n   may have.  */\n\n#define EI_MAG0\t\t0\t\t/* File identification byte 0 index */\n#define ELFMAG0\t\t0x7f\t\t/* Magic number byte 0 */\n\n#define EI_MAG1\t\t1\t\t/* File identification byte 1 index */\n#define ELFMAG1\t\t'E'\t\t/* Magic number byte 1 */\n\n#define EI_MAG2\t\t2\t\t/* File identification byte 2 index */\n#define ELFMAG2\t\t'L'\t\t/* Magic number byte 2 */\n\n#define EI_MAG3\t\t3\t\t/* File identification byte 3 index */\n#define ELFMAG3\t\t'F'\t\t/* Magic number byte 3 */\n\n/* Conglomeration of the identification bytes, for easy testing as a word.  */\n#define\tELFMAG\t\t\"\\177ELF\"\n#define\tSELFMAG\t\t4\n\n#define EI_CLASS\t4\t\t/* File class byte index */\n#define ELFCLASSNONE\t0\t\t/* Invalid class */\n#define ELFCLASS32\t1\t\t/* 32-bit objects */\n#define ELFCLASS64\t2\t\t/* 64-bit objects */\n#define ELFCLASSNUM\t3\n\n#define EI_DATA\t\t5\t\t/* Data encoding byte index */\n#define ELFDATANONE\t0\t\t/* Invalid data encoding */\n#define ELFDATA2LSB\t1\t\t/* 2's complement, little endian */\n#define ELFDATA2MSB\t2\t\t/* 2's complement, big endian */\n#define ELFDATANUM\t3\n\n#define EI_VERSION\t6\t\t/* File version byte index */\n\t\t\t\t\t/* Value must be EV_CURRENT */\n\n#define EI_OSABI\t7\t\t/* OS ABI identification */\n#define ELFOSABI_NONE\t\t0\t/* UNIX System V ABI */\n#define ELFOSABI_SYSV\t\t0\t/* Alias.  */\n#define ELFOSABI_HPUX\t\t1\t/* HP-UX */\n#define ELFOSABI_NETBSD\t\t2\t/* NetBSD.  */\n#define ELFOSABI_GNU\t\t3\t/* Object uses GNU ELF extensions.  */\n#define ELFOSABI_LINUX\t\tELFOSABI_GNU /* Compatibility alias.  */\n#define ELFOSABI_SOLARIS\t6\t/* Sun Solaris.  */\n#define ELFOSABI_AIX\t\t7\t/* IBM AIX.  */\n#define ELFOSABI_IRIX\t\t8\t/* SGI Irix.  */\n#define ELFOSABI_FREEBSD\t9\t/* FreeBSD.  */\n#define ELFOSABI_TRU64\t\t10\t/* Compaq TRU64 UNIX.  */\n#define ELFOSABI_MODESTO\t11\t/* Novell Modesto.  */\n#define ELFOSABI_OPENBSD\t12\t/* OpenBSD.  */\n#define ELFOSABI_ARM_AEABI\t64\t/* ARM EABI */\n#define ELFOSABI_ARM\t\t97\t/* ARM */\n#define ELFOSABI_STANDALONE\t255\t/* Standalone (embedded) application */\n\n#define EI_ABIVERSION\t8\t\t/* ABI version */\n\n#define EI_PAD\t\t9\t\t/* Byte index of padding bytes */\n\n/* Legal values for e_type (object file type).  */\n\n#define ET_NONE\t\t0\t\t/* No file type */\n#define ET_REL\t\t1\t\t/* Relocatable file */\n#define ET_EXEC\t\t2\t\t/* Executable file */\n#define ET_DYN\t\t3\t\t/* Shared object file */\n#define ET_CORE\t\t4\t\t/* Core file */\n#define\tET_NUM\t\t5\t\t/* Number of defined types */\n#define ET_LOOS\t\t0xfe00\t\t/* OS-specific range start */\n#define ET_HIOS\t\t0xfeff\t\t/* OS-specific range end */\n#define ET_LOPROC\t0xff00\t\t/* Processor-specific range start */\n#define ET_HIPROC\t0xffff\t\t/* Processor-specific range end */\n\n/* Legal values for e_machine (architecture).  */\n\n#define EM_NONE\t\t 0\t\t/* No machine */\n#define EM_M32\t\t 1\t\t/* AT&T WE 32100 */\n#define EM_SPARC\t 2\t\t/* SUN SPARC */\n#define EM_386\t\t 3\t\t/* Intel 80386 */\n#define EM_68K\t\t 4\t\t/* Motorola m68k family */\n#define EM_88K\t\t 5\t\t/* Motorola m88k family */\n#define EM_860\t\t 7\t\t/* Intel 80860 */\n#define EM_MIPS\t\t 8\t\t/* MIPS R3000 big-endian */\n#define EM_S370\t\t 9\t\t/* IBM System/370 */\n#define EM_MIPS_RS3_LE\t10\t\t/* MIPS R3000 little-endian */\n\n#define EM_PARISC\t15\t\t/* HPPA */\n#define EM_VPP500\t17\t\t/* Fujitsu VPP500 */\n#define EM_SPARC32PLUS\t18\t\t/* Sun's \"v8plus\" */\n#define EM_960\t\t19\t\t/* Intel 80960 */\n#define EM_PPC\t\t20\t\t/* PowerPC */\n#define EM_PPC64\t21\t\t/* PowerPC 64-bit */\n#define EM_S390\t\t22\t\t/* IBM S390 */\n\n#define EM_V800\t\t36\t\t/* NEC V800 series */\n#define EM_FR20\t\t37\t\t/* Fujitsu FR20 */\n#define EM_RH32\t\t38\t\t/* TRW RH-32 */\n#define EM_RCE\t\t39\t\t/* Motorola RCE */\n#define EM_ARM\t\t40\t\t/* ARM */\n#define EM_FAKE_ALPHA\t41\t\t/* Digital Alpha */\n#define EM_SH\t\t42\t\t/* Hitachi SH */\n#define EM_SPARCV9\t43\t\t/* SPARC v9 64-bit */\n#define EM_TRICORE\t44\t\t/* Siemens Tricore */\n#define EM_ARC\t\t45\t\t/* Argonaut RISC Core */\n#define EM_H8_300\t46\t\t/* Hitachi H8/300 */\n#define EM_H8_300H\t47\t\t/* Hitachi H8/300H */\n#define EM_H8S\t\t48\t\t/* Hitachi H8S */\n#define EM_H8_500\t49\t\t/* Hitachi H8/500 */\n#define EM_IA_64\t50\t\t/* Intel Merced */\n#define EM_MIPS_X\t51\t\t/* Stanford MIPS-X */\n#define EM_COLDFIRE\t52\t\t/* Motorola Coldfire */\n#define EM_68HC12\t53\t\t/* Motorola M68HC12 */\n#define EM_MMA\t\t54\t\t/* Fujitsu MMA Multimedia Accelerator*/\n#define EM_PCP\t\t55\t\t/* Siemens PCP */\n#define EM_NCPU\t\t56\t\t/* Sony nCPU embeeded RISC */\n#define EM_NDR1\t\t57\t\t/* Denso NDR1 microprocessor */\n#define EM_STARCORE\t58\t\t/* Motorola Start*Core processor */\n#define EM_ME16\t\t59\t\t/* Toyota ME16 processor */\n#define EM_ST100\t60\t\t/* STMicroelectronic ST100 processor */\n#define EM_TINYJ\t61\t\t/* Advanced Logic Corp. Tinyj emb.fam*/\n#define EM_X86_64\t62\t\t/* AMD x86-64 architecture */\n#define EM_PDSP\t\t63\t\t/* Sony DSP Processor */\n\n#define EM_FX66\t\t66\t\t/* Siemens FX66 microcontroller */\n#define EM_ST9PLUS\t67\t\t/* STMicroelectronics ST9+ 8/16 mc */\n#define EM_ST7\t\t68\t\t/* STmicroelectronics ST7 8 bit mc */\n#define EM_68HC16\t69\t\t/* Motorola MC68HC16 microcontroller */\n#define EM_68HC11\t70\t\t/* Motorola MC68HC11 microcontroller */\n#define EM_68HC08\t71\t\t/* Motorola MC68HC08 microcontroller */\n#define EM_68HC05\t72\t\t/* Motorola MC68HC05 microcontroller */\n#define EM_SVX\t\t73\t\t/* Silicon Graphics SVx */\n#define EM_ST19\t\t74\t\t/* STMicroelectronics ST19 8 bit mc */\n#define EM_VAX\t\t75\t\t/* Digital VAX */\n#define EM_CRIS\t\t76\t\t/* Axis Communications 32-bit embedded processor */\n#define EM_JAVELIN\t77\t\t/* Infineon Technologies 32-bit embedded processor */\n#define EM_FIREPATH\t78\t\t/* Element 14 64-bit DSP Processor */\n#define EM_ZSP\t\t79\t\t/* LSI Logic 16-bit DSP Processor */\n#define EM_MMIX\t\t80\t\t/* Donald Knuth's educational 64-bit processor */\n#define EM_HUANY\t81\t\t/* Harvard University machine-independent object files */\n#define EM_PRISM\t82\t\t/* SiTera Prism */\n#define EM_AVR\t\t83\t\t/* Atmel AVR 8-bit microcontroller */\n#define EM_FR30\t\t84\t\t/* Fujitsu FR30 */\n#define EM_D10V\t\t85\t\t/* Mitsubishi D10V */\n#define EM_D30V\t\t86\t\t/* Mitsubishi D30V */\n#define EM_V850\t\t87\t\t/* NEC v850 */\n#define EM_M32R\t\t88\t\t/* Mitsubishi M32R */\n#define EM_MN10300\t89\t\t/* Matsushita MN10300 */\n#define EM_MN10200\t90\t\t/* Matsushita MN10200 */\n#define EM_PJ\t\t91\t\t/* picoJava */\n#define EM_OPENRISC\t92\t\t/* OpenRISC 32-bit embedded processor */\n#define EM_ARC_A5\t93\t\t/* ARC Cores Tangent-A5 */\n#define EM_XTENSA\t94\t\t/* Tensilica Xtensa Architecture */\n#define EM_TILEPRO\t188\t\t/* Tilera TILEPro */\n#define EM_TILEGX\t191\t\t/* Tilera TILE-Gx */\n#define EM_NUM\t\t192\n\n/* If it is necessary to assign new unofficial EM_* values, please\n   pick large random numbers (0x8523, 0xa7f2, etc.) to minimize the\n   chances of collision with official or non-GNU unofficial values.  */\n\n#define EM_ALPHA\t0x9026\n\n/* Legal values for e_version (version).  */\n\n#define EV_NONE\t\t0\t\t/* Invalid ELF version */\n#define EV_CURRENT\t1\t\t/* Current version */\n#define EV_NUM\t\t2\n\n/* Section header.  */\n\ntypedef struct\n{\n  Elf32_Word\tsh_name;\t\t/* Section name (string tbl index) */\n  Elf32_Word\tsh_type;\t\t/* Section type */\n  Elf32_Word\tsh_flags;\t\t/* Section flags */\n  Elf32_Addr\tsh_addr;\t\t/* Section virtual addr at execution */\n  Elf32_Off\tsh_offset;\t\t/* Section file offset */\n  Elf32_Word\tsh_size;\t\t/* Section size in bytes */\n  Elf32_Word\tsh_link;\t\t/* Link to another section */\n  Elf32_Word\tsh_info;\t\t/* Additional section information */\n  Elf32_Word\tsh_addralign;\t\t/* Section alignment */\n  Elf32_Word\tsh_entsize;\t\t/* Entry size if section holds table */\n} Elf32_Shdr;\n\ntypedef struct\n{\n  Elf64_Word\tsh_name;\t\t/* Section name (string tbl index) */\n  Elf64_Word\tsh_type;\t\t/* Section type */\n  Elf64_Xword\tsh_flags;\t\t/* Section flags */\n  Elf64_Addr\tsh_addr;\t\t/* Section virtual addr at execution */\n  Elf64_Off\tsh_offset;\t\t/* Section file offset */\n  Elf64_Xword\tsh_size;\t\t/* Section size in bytes */\n  Elf64_Word\tsh_link;\t\t/* Link to another section */\n  Elf64_Word\tsh_info;\t\t/* Additional section information */\n  Elf64_Xword\tsh_addralign;\t\t/* Section alignment */\n  Elf64_Xword\tsh_entsize;\t\t/* Entry size if section holds table */\n} Elf64_Shdr;\n\n/* Special section indices.  */\n\n#define SHN_UNDEF\t0\t\t/* Undefined section */\n#define SHN_LORESERVE\t0xff00\t\t/* Start of reserved indices */\n#define SHN_LOPROC\t0xff00\t\t/* Start of processor-specific */\n#define SHN_BEFORE\t0xff00\t\t/* Order section before all others\n\t\t\t\t\t   (Solaris).  */\n#define SHN_AFTER\t0xff01\t\t/* Order section after all others\n\t\t\t\t\t   (Solaris).  */\n#define SHN_HIPROC\t0xff1f\t\t/* End of processor-specific */\n#define SHN_LOOS\t0xff20\t\t/* Start of OS-specific */\n#define SHN_HIOS\t0xff3f\t\t/* End of OS-specific */\n#define SHN_ABS\t\t0xfff1\t\t/* Associated symbol is absolute */\n#define SHN_COMMON\t0xfff2\t\t/* Associated symbol is common */\n#define SHN_XINDEX\t0xffff\t\t/* Index is in extra table.  */\n#define SHN_HIRESERVE\t0xffff\t\t/* End of reserved indices */\n\n/* Legal values for sh_type (section type).  */\n\n#define SHT_NULL\t  0\t\t/* Section header table entry unused */\n#define SHT_PROGBITS\t  1\t\t/* Program data */\n#define SHT_SYMTAB\t  2\t\t/* Symbol table */\n#define SHT_STRTAB\t  3\t\t/* String table */\n#define SHT_RELA\t  4\t\t/* Relocation entries with addends */\n#define SHT_HASH\t  5\t\t/* Symbol hash table */\n#define SHT_DYNAMIC\t  6\t\t/* Dynamic linking information */\n#define SHT_NOTE\t  7\t\t/* Notes */\n#define SHT_NOBITS\t  8\t\t/* Program space with no data (bss) */\n#define SHT_REL\t\t  9\t\t/* Relocation entries, no addends */\n#define SHT_SHLIB\t  10\t\t/* Reserved */\n#define SHT_DYNSYM\t  11\t\t/* Dynamic linker symbol table */\n#define SHT_INIT_ARRAY\t  14\t\t/* Array of constructors */\n#define SHT_FINI_ARRAY\t  15\t\t/* Array of destructors */\n#define SHT_PREINIT_ARRAY 16\t\t/* Array of pre-constructors */\n#define SHT_GROUP\t  17\t\t/* Section group */\n#define SHT_SYMTAB_SHNDX  18\t\t/* Extended section indeces */\n#define\tSHT_NUM\t\t  19\t\t/* Number of defined types.  */\n#define SHT_LOOS\t  0x60000000\t/* Start OS-specific.  */\n#define SHT_GNU_ATTRIBUTES 0x6ffffff5\t/* Object attributes.  */\n#define SHT_GNU_HASH\t  0x6ffffff6\t/* GNU-style hash table.  */\n#define SHT_GNU_LIBLIST\t  0x6ffffff7\t/* Prelink library list */\n#define SHT_CHECKSUM\t  0x6ffffff8\t/* Checksum for DSO content.  */\n#define SHT_LOSUNW\t  0x6ffffffa\t/* Sun-specific low bound.  */\n#define SHT_SUNW_move\t  0x6ffffffa\n#define SHT_SUNW_COMDAT   0x6ffffffb\n#define SHT_SUNW_syminfo  0x6ffffffc\n#define SHT_GNU_verdef\t  0x6ffffffd\t/* Version definition section.  */\n#define SHT_GNU_verneed\t  0x6ffffffe\t/* Version needs section.  */\n#define SHT_GNU_versym\t  0x6fffffff\t/* Version symbol table.  */\n#define SHT_HISUNW\t  0x6fffffff\t/* Sun-specific high bound.  */\n#define SHT_HIOS\t  0x6fffffff\t/* End OS-specific type */\n#define SHT_LOPROC\t  0x70000000\t/* Start of processor-specific */\n#define SHT_HIPROC\t  0x7fffffff\t/* End of processor-specific */\n#define SHT_LOUSER\t  0x80000000\t/* Start of application-specific */\n#define SHT_HIUSER\t  0x8fffffff\t/* End of application-specific */\n\n/* Legal values for sh_flags (section flags).  */\n\n#define SHF_WRITE\t     (1 << 0)\t/* Writable */\n#define SHF_ALLOC\t     (1 << 1)\t/* Occupies memory during execution */\n#define SHF_EXECINSTR\t     (1 << 2)\t/* Executable */\n#define SHF_MERGE\t     (1 << 4)\t/* Might be merged */\n#define SHF_STRINGS\t     (1 << 5)\t/* Contains nul-terminated strings */\n#define SHF_INFO_LINK\t     (1 << 6)\t/* `sh_info' contains SHT index */\n#define SHF_LINK_ORDER\t     (1 << 7)\t/* Preserve order after combining */\n#define SHF_OS_NONCONFORMING (1 << 8)\t/* Non-standard OS specific handling\n\t\t\t\t\t   required */\n#define SHF_GROUP\t     (1 << 9)\t/* Section is member of a group.  */\n#define SHF_TLS\t\t     (1 << 10)\t/* Section hold thread-local data.  */\n#define SHF_MASKOS\t     0x0ff00000\t/* OS-specific.  */\n#define SHF_MASKPROC\t     0xf0000000\t/* Processor-specific */\n#define SHF_ORDERED\t     (1 << 30)\t/* Special ordering requirement\n\t\t\t\t\t   (Solaris).  */\n#define SHF_EXCLUDE\t     (1 << 31)\t/* Section is excluded unless\n\t\t\t\t\t   referenced or allocated (Solaris).*/\n\n/* Section group handling.  */\n#define GRP_COMDAT\t0x1\t\t/* Mark group as COMDAT.  */\n\n/* Symbol table entry.  */\n\ntypedef struct\n{\n  Elf32_Word\tst_name;\t\t/* Symbol name (string tbl index) */\n  Elf32_Addr\tst_value;\t\t/* Symbol value */\n  Elf32_Word\tst_size;\t\t/* Symbol size */\n  unsigned char\tst_info;\t\t/* Symbol type and binding */\n  unsigned char\tst_other;\t\t/* Symbol visibility */\n  Elf32_Section\tst_shndx;\t\t/* Section index */\n} Elf32_Sym;\n\ntypedef struct\n{\n  Elf64_Word\tst_name;\t\t/* Symbol name (string tbl index) */\n  unsigned char\tst_info;\t\t/* Symbol type and binding */\n  unsigned char st_other;\t\t/* Symbol visibility */\n  Elf64_Section\tst_shndx;\t\t/* Section index */\n  Elf64_Addr\tst_value;\t\t/* Symbol value */\n  Elf64_Xword\tst_size;\t\t/* Symbol size */\n} Elf64_Sym;\n\n/* The syminfo section if available contains additional information about\n   every dynamic symbol.  */\n\ntypedef struct\n{\n  Elf32_Half si_boundto;\t\t/* Direct bindings, symbol bound to */\n  Elf32_Half si_flags;\t\t\t/* Per symbol flags */\n} Elf32_Syminfo;\n\ntypedef struct\n{\n  Elf64_Half si_boundto;\t\t/* Direct bindings, symbol bound to */\n  Elf64_Half si_flags;\t\t\t/* Per symbol flags */\n} Elf64_Syminfo;\n\n/* Possible values for si_boundto.  */\n#define SYMINFO_BT_SELF\t\t0xffff\t/* Symbol bound to self */\n#define SYMINFO_BT_PARENT\t0xfffe\t/* Symbol bound to parent */\n#define SYMINFO_BT_LOWRESERVE\t0xff00\t/* Beginning of reserved entries */\n\n/* Possible bitmasks for si_flags.  */\n#define SYMINFO_FLG_DIRECT\t0x0001\t/* Direct bound symbol */\n#define SYMINFO_FLG_PASSTHRU\t0x0002\t/* Pass-thru symbol for translator */\n#define SYMINFO_FLG_COPY\t0x0004\t/* Symbol is a copy-reloc */\n#define SYMINFO_FLG_LAZYLOAD\t0x0008\t/* Symbol bound to object to be lazy\n\t\t\t\t\t   loaded */\n/* Syminfo version values.  */\n#define SYMINFO_NONE\t\t0\n#define SYMINFO_CURRENT\t\t1\n#define SYMINFO_NUM\t\t2\n\n\n/* How to extract and insert information held in the st_info field.  */\n\n#define ELF32_ST_BIND(val)\t\t(((unsigned char) (val)) >> 4)\n#define ELF32_ST_TYPE(val)\t\t((val) & 0xf)\n#define ELF32_ST_INFO(bind, type)\t(((bind) << 4) + ((type) & 0xf))\n\n/* Both Elf32_Sym and Elf64_Sym use the same one-byte st_info field.  */\n#define ELF64_ST_BIND(val)\t\tELF32_ST_BIND (val)\n#define ELF64_ST_TYPE(val)\t\tELF32_ST_TYPE (val)\n#define ELF64_ST_INFO(bind, type)\tELF32_ST_INFO ((bind), (type))\n\n/* Legal values for ST_BIND subfield of st_info (symbol binding).  */\n\n#define STB_LOCAL\t0\t\t/* Local symbol */\n#define STB_GLOBAL\t1\t\t/* Global symbol */\n#define STB_WEAK\t2\t\t/* Weak symbol */\n#define\tSTB_NUM\t\t3\t\t/* Number of defined types.  */\n#define STB_LOOS\t10\t\t/* Start of OS-specific */\n#define STB_GNU_UNIQUE\t10\t\t/* Unique symbol.  */\n#define STB_HIOS\t12\t\t/* End of OS-specific */\n#define STB_LOPROC\t13\t\t/* Start of processor-specific */\n#define STB_HIPROC\t15\t\t/* End of processor-specific */\n\n/* Legal values for ST_TYPE subfield of st_info (symbol type).  */\n\n#define STT_NOTYPE\t0\t\t/* Symbol type is unspecified */\n#define STT_OBJECT\t1\t\t/* Symbol is a data object */\n#define STT_FUNC\t2\t\t/* Symbol is a code object */\n#define STT_SECTION\t3\t\t/* Symbol associated with a section */\n#define STT_FILE\t4\t\t/* Symbol's name is file name */\n#define STT_COMMON\t5\t\t/* Symbol is a common data object */\n#define STT_TLS\t\t6\t\t/* Symbol is thread-local data object*/\n#define\tSTT_NUM\t\t7\t\t/* Number of defined types.  */\n#define STT_LOOS\t10\t\t/* Start of OS-specific */\n#define STT_GNU_IFUNC\t10\t\t/* Symbol is indirect code object */\n#define STT_HIOS\t12\t\t/* End of OS-specific */\n#define STT_LOPROC\t13\t\t/* Start of processor-specific */\n#define STT_HIPROC\t15\t\t/* End of processor-specific */\n\n\n/* Symbol table indices are found in the hash buckets and chain table\n   of a symbol hash table section.  This special index value indicates\n   the end of a chain, meaning no further symbols are found in that bucket.  */\n\n#define STN_UNDEF\t0\t\t/* End of a chain.  */\n\n\n/* How to extract and insert information held in the st_other field.  */\n\n#define ELF32_ST_VISIBILITY(o)\t((o) & 0x03)\n\n/* For ELF64 the definitions are the same.  */\n#define ELF64_ST_VISIBILITY(o)\tELF32_ST_VISIBILITY (o)\n\n/* Symbol visibility specification encoded in the st_other field.  */\n#define STV_DEFAULT\t0\t\t/* Default symbol visibility rules */\n#define STV_INTERNAL\t1\t\t/* Processor specific hidden class */\n#define STV_HIDDEN\t2\t\t/* Sym unavailable in other modules */\n#define STV_PROTECTED\t3\t\t/* Not preemptible, not exported */\n\n\n/* Relocation table entry without addend (in section of type SHT_REL).  */\n\ntypedef struct\n{\n  Elf32_Addr\tr_offset;\t\t/* Address */\n  Elf32_Word\tr_info;\t\t\t/* Relocation type and symbol index */\n} Elf32_Rel;\n\n/* I have seen two different definitions of the Elf64_Rel and\n   Elf64_Rela structures, so we'll leave them out until Novell (or\n   whoever) gets their act together.  */\n/* The following, at least, is used on Sparc v9, MIPS, and Alpha.  */\n\ntypedef struct\n{\n  Elf64_Addr\tr_offset;\t\t/* Address */\n  Elf64_Xword\tr_info;\t\t\t/* Relocation type and symbol index */\n} Elf64_Rel;\n\n/* Relocation table entry with addend (in section of type SHT_RELA).  */\n\ntypedef struct\n{\n  Elf32_Addr\tr_offset;\t\t/* Address */\n  Elf32_Word\tr_info;\t\t\t/* Relocation type and symbol index */\n  Elf32_Sword\tr_addend;\t\t/* Addend */\n} Elf32_Rela;\n\ntypedef struct\n{\n  Elf64_Addr\tr_offset;\t\t/* Address */\n  Elf64_Xword\tr_info;\t\t\t/* Relocation type and symbol index */\n  Elf64_Sxword\tr_addend;\t\t/* Addend */\n} Elf64_Rela;\n\n/* How to extract and insert information held in the r_info field.  */\n\n#define ELF32_R_SYM(val)\t\t((val) >> 8)\n#define ELF32_R_TYPE(val)\t\t((val) & 0xff)\n#define ELF32_R_INFO(sym, type)\t\t(((sym) << 8) + ((type) & 0xff))\n\n#define ELF64_R_SYM(i)\t\t\t((i) >> 32)\n#define ELF64_R_TYPE(i)\t\t\t((i) & 0xffffffff)\n#define ELF64_R_INFO(sym,type)\t\t((((Elf64_Xword) (sym)) << 32) + (type))\n\n/* Program segment header.  */\n\ntypedef struct\n{\n  Elf32_Word\tp_type;\t\t\t/* Segment type */\n  Elf32_Off\tp_offset;\t\t/* Segment file offset */\n  Elf32_Addr\tp_vaddr;\t\t/* Segment virtual address */\n  Elf32_Addr\tp_paddr;\t\t/* Segment physical address */\n  Elf32_Word\tp_filesz;\t\t/* Segment size in file */\n  Elf32_Word\tp_memsz;\t\t/* Segment size in memory */\n  Elf32_Word\tp_flags;\t\t/* Segment flags */\n  Elf32_Word\tp_align;\t\t/* Segment alignment */\n} Elf32_Phdr;\n\ntypedef struct\n{\n  Elf64_Word\tp_type;\t\t\t/* Segment type */\n  Elf64_Word\tp_flags;\t\t/* Segment flags */\n  Elf64_Off\tp_offset;\t\t/* Segment file offset */\n  Elf64_Addr\tp_vaddr;\t\t/* Segment virtual address */\n  Elf64_Addr\tp_paddr;\t\t/* Segment physical address */\n  Elf64_Xword\tp_filesz;\t\t/* Segment size in file */\n  Elf64_Xword\tp_memsz;\t\t/* Segment size in memory */\n  Elf64_Xword\tp_align;\t\t/* Segment alignment */\n} Elf64_Phdr;\n\n/* Special value for e_phnum.  This indicates that the real number of\n   program headers is too large to fit into e_phnum.  Instead the real\n   value is in the field sh_info of section 0.  */\n\n#define PN_XNUM\t\t0xffff\n\n/* Legal values for p_type (segment type).  */\n\n#define\tPT_NULL\t\t0\t\t/* Program header table entry unused */\n#define PT_LOAD\t\t1\t\t/* Loadable program segment */\n#define PT_DYNAMIC\t2\t\t/* Dynamic linking information */\n#define PT_INTERP\t3\t\t/* Program interpreter */\n#define PT_NOTE\t\t4\t\t/* Auxiliary information */\n#define PT_SHLIB\t5\t\t/* Reserved */\n#define PT_PHDR\t\t6\t\t/* Entry for header table itself */\n#define PT_TLS\t\t7\t\t/* Thread-local storage segment */\n#define\tPT_NUM\t\t8\t\t/* Number of defined types */\n#define PT_LOOS\t\t0x60000000\t/* Start of OS-specific */\n#define PT_GNU_EH_FRAME\t0x6474e550\t/* GCC .eh_frame_hdr segment */\n#define PT_GNU_STACK\t0x6474e551\t/* Indicates stack executability */\n#define PT_GNU_RELRO\t0x6474e552\t/* Read-only after relocation */\n#define PT_LOSUNW\t0x6ffffffa\n#define PT_SUNWBSS\t0x6ffffffa\t/* Sun Specific segment */\n#define PT_SUNWSTACK\t0x6ffffffb\t/* Stack segment */\n#define PT_HISUNW\t0x6fffffff\n#define PT_HIOS\t\t0x6fffffff\t/* End of OS-specific */\n#define PT_LOPROC\t0x70000000\t/* Start of processor-specific */\n#define PT_HIPROC\t0x7fffffff\t/* End of processor-specific */\n\n/* Legal values for p_flags (segment flags).  */\n\n#define PF_X\t\t(1 << 0)\t/* Segment is executable */\n#define PF_W\t\t(1 << 1)\t/* Segment is writable */\n#define PF_R\t\t(1 << 2)\t/* Segment is readable */\n#define PF_MASKOS\t0x0ff00000\t/* OS-specific */\n#define PF_MASKPROC\t0xf0000000\t/* Processor-specific */\n\n/* Legal values for note segment descriptor types for core files. */\n\n#define NT_PRSTATUS\t1\t\t/* Contains copy of prstatus struct */\n#define NT_FPREGSET\t2\t\t/* Contains copy of fpregset struct */\n#define NT_PRPSINFO\t3\t\t/* Contains copy of prpsinfo struct */\n#define NT_PRXREG\t4\t\t/* Contains copy of prxregset struct */\n#define NT_TASKSTRUCT\t4\t\t/* Contains copy of task structure */\n#define NT_PLATFORM\t5\t\t/* String from sysinfo(SI_PLATFORM) */\n#define NT_AUXV\t\t6\t\t/* Contains copy of auxv array */\n#define NT_GWINDOWS\t7\t\t/* Contains copy of gwindows struct */\n#define NT_ASRS\t\t8\t\t/* Contains copy of asrset struct */\n#define NT_PSTATUS\t10\t\t/* Contains copy of pstatus struct */\n#define NT_PSINFO\t13\t\t/* Contains copy of psinfo struct */\n#define NT_PRCRED\t14\t\t/* Contains copy of prcred struct */\n#define NT_UTSNAME\t15\t\t/* Contains copy of utsname struct */\n#define NT_LWPSTATUS\t16\t\t/* Contains copy of lwpstatus struct */\n#define NT_LWPSINFO\t17\t\t/* Contains copy of lwpinfo struct */\n#define NT_PRFPXREG\t20\t\t/* Contains copy of fprxregset struct */\n#define NT_PRXFPREG\t0x46e62b7f\t/* Contains copy of user_fxsr_struct */\n#define NT_PPC_VMX\t0x100\t\t/* PowerPC Altivec/VMX registers */\n#define NT_PPC_SPE\t0x101\t\t/* PowerPC SPE/EVR registers */\n#define NT_PPC_VSX\t0x102\t\t/* PowerPC VSX registers */\n#define NT_386_TLS\t0x200\t\t/* i386 TLS slots (struct user_desc) */\n#define NT_386_IOPERM\t0x201\t\t/* x86 io permission bitmap (1=deny) */\n#define NT_X86_XSTATE\t0x202\t\t/* x86 extended state using xsave */\n\n/* Legal values for the note segment descriptor types for object files.  */\n\n#define NT_VERSION\t1\t\t/* Contains a version string.  */\n\n\n/* Dynamic section entry.  */\n\ntypedef struct\n{\n  Elf32_Sword\td_tag;\t\t\t/* Dynamic entry type */\n  union\n    {\n      Elf32_Word d_val;\t\t\t/* Integer value */\n      Elf32_Addr d_ptr;\t\t\t/* Address value */\n    } d_un;\n} Elf32_Dyn;\n\ntypedef struct\n{\n  Elf64_Sxword\td_tag;\t\t\t/* Dynamic entry type */\n  union\n    {\n      Elf64_Xword d_val;\t\t/* Integer value */\n      Elf64_Addr d_ptr;\t\t\t/* Address value */\n    } d_un;\n} Elf64_Dyn;\n\n/* Legal values for d_tag (dynamic entry type).  */\n\n#define DT_NULL\t\t0\t\t/* Marks end of dynamic section */\n#define DT_NEEDED\t1\t\t/* Name of needed library */\n#define DT_PLTRELSZ\t2\t\t/* Size in bytes of PLT relocs */\n#define DT_PLTGOT\t3\t\t/* Processor defined value */\n#define DT_HASH\t\t4\t\t/* Address of symbol hash table */\n#define DT_STRTAB\t5\t\t/* Address of string table */\n#define DT_SYMTAB\t6\t\t/* Address of symbol table */\n#define DT_RELA\t\t7\t\t/* Address of Rela relocs */\n#define DT_RELASZ\t8\t\t/* Total size of Rela relocs */\n#define DT_RELAENT\t9\t\t/* Size of one Rela reloc */\n#define DT_STRSZ\t10\t\t/* Size of string table */\n#define DT_SYMENT\t11\t\t/* Size of one symbol table entry */\n#define DT_INIT\t\t12\t\t/* Address of init function */\n#define DT_FINI\t\t13\t\t/* Address of termination function */\n#define DT_SONAME\t14\t\t/* Name of shared object */\n#define DT_RPATH\t15\t\t/* Library search path (deprecated) */\n#define DT_SYMBOLIC\t16\t\t/* Start symbol search here */\n#define DT_REL\t\t17\t\t/* Address of Rel relocs */\n#define DT_RELSZ\t18\t\t/* Total size of Rel relocs */\n#define DT_RELENT\t19\t\t/* Size of one Rel reloc */\n#define DT_PLTREL\t20\t\t/* Type of reloc in PLT */\n#define DT_DEBUG\t21\t\t/* For debugging; unspecified */\n#define DT_TEXTREL\t22\t\t/* Reloc might modify .text */\n#define DT_JMPREL\t23\t\t/* Address of PLT relocs */\n#define\tDT_BIND_NOW\t24\t\t/* Process relocations of object */\n#define\tDT_INIT_ARRAY\t25\t\t/* Array with addresses of init fct */\n#define\tDT_FINI_ARRAY\t26\t\t/* Array with addresses of fini fct */\n#define\tDT_INIT_ARRAYSZ\t27\t\t/* Size in bytes of DT_INIT_ARRAY */\n#define\tDT_FINI_ARRAYSZ\t28\t\t/* Size in bytes of DT_FINI_ARRAY */\n#define DT_RUNPATH\t29\t\t/* Library search path */\n#define DT_FLAGS\t30\t\t/* Flags for the object being loaded */\n#define DT_ENCODING\t32\t\t/* Start of encoded range */\n#define DT_PREINIT_ARRAY 32\t\t/* Array with addresses of preinit fct*/\n#define DT_PREINIT_ARRAYSZ 33\t\t/* size in bytes of DT_PREINIT_ARRAY */\n#define\tDT_NUM\t\t34\t\t/* Number used */\n#define DT_LOOS\t\t0x6000000d\t/* Start of OS-specific */\n#define DT_HIOS\t\t0x6ffff000\t/* End of OS-specific */\n#define DT_LOPROC\t0x70000000\t/* Start of processor-specific */\n#define DT_HIPROC\t0x7fffffff\t/* End of processor-specific */\n#define\tDT_PROCNUM\tDT_MIPS_NUM\t/* Most used by any processor */\n\n/* DT_* entries which fall between DT_VALRNGHI & DT_VALRNGLO use the\n   Dyn.d_un.d_val field of the Elf*_Dyn structure.  This follows Sun's\n   approach.  */\n#define DT_VALRNGLO\t0x6ffffd00\n#define DT_GNU_PRELINKED 0x6ffffdf5\t/* Prelinking timestamp */\n#define DT_GNU_CONFLICTSZ 0x6ffffdf6\t/* Size of conflict section */\n#define DT_GNU_LIBLISTSZ 0x6ffffdf7\t/* Size of library list */\n#define DT_CHECKSUM\t0x6ffffdf8\n#define DT_PLTPADSZ\t0x6ffffdf9\n#define DT_MOVEENT\t0x6ffffdfa\n#define DT_MOVESZ\t0x6ffffdfb\n#define DT_FEATURE_1\t0x6ffffdfc\t/* Feature selection (DTF_*).  */\n#define DT_POSFLAG_1\t0x6ffffdfd\t/* Flags for DT_* entries, effecting\n\t\t\t\t\t   the following DT_* entry.  */\n#define DT_SYMINSZ\t0x6ffffdfe\t/* Size of syminfo table (in bytes) */\n#define DT_SYMINENT\t0x6ffffdff\t/* Entry size of syminfo */\n#define DT_VALRNGHI\t0x6ffffdff\n#define DT_VALTAGIDX(tag)\t(DT_VALRNGHI - (tag))\t/* Reverse order! */\n#define DT_VALNUM 12\n\n/* DT_* entries which fall between DT_ADDRRNGHI & DT_ADDRRNGLO use the\n   Dyn.d_un.d_ptr field of the Elf*_Dyn structure.\n\n   If any adjustment is made to the ELF object after it has been\n   built these entries will need to be adjusted.  */\n#define DT_ADDRRNGLO\t0x6ffffe00\n#define DT_GNU_HASH\t0x6ffffef5\t/* GNU-style hash table.  */\n#define DT_TLSDESC_PLT\t0x6ffffef6\n#define DT_TLSDESC_GOT\t0x6ffffef7\n#define DT_GNU_CONFLICT\t0x6ffffef8\t/* Start of conflict section */\n#define DT_GNU_LIBLIST\t0x6ffffef9\t/* Library list */\n#define DT_CONFIG\t0x6ffffefa\t/* Configuration information.  */\n#define DT_DEPAUDIT\t0x6ffffefb\t/* Dependency auditing.  */\n#define DT_AUDIT\t0x6ffffefc\t/* Object auditing.  */\n#define\tDT_PLTPAD\t0x6ffffefd\t/* PLT padding.  */\n#define\tDT_MOVETAB\t0x6ffffefe\t/* Move table.  */\n#define DT_SYMINFO\t0x6ffffeff\t/* Syminfo table.  */\n#define DT_ADDRRNGHI\t0x6ffffeff\n#define DT_ADDRTAGIDX(tag)\t(DT_ADDRRNGHI - (tag))\t/* Reverse order! */\n#define DT_ADDRNUM 11\n\n/* The versioning entry types.  The next are defined as part of the\n   GNU extension.  */\n#define DT_VERSYM\t0x6ffffff0\n\n#define DT_RELACOUNT\t0x6ffffff9\n#define DT_RELCOUNT\t0x6ffffffa\n\n/* These were chosen by Sun.  */\n#define DT_FLAGS_1\t0x6ffffffb\t/* State flags, see DF_1_* below.  */\n#define\tDT_VERDEF\t0x6ffffffc\t/* Address of version definition\n\t\t\t\t\t   table */\n#define\tDT_VERDEFNUM\t0x6ffffffd\t/* Number of version definitions */\n#define\tDT_VERNEED\t0x6ffffffe\t/* Address of table with needed\n\t\t\t\t\t   versions */\n#define\tDT_VERNEEDNUM\t0x6fffffff\t/* Number of needed versions */\n#define DT_VERSIONTAGIDX(tag)\t(DT_VERNEEDNUM - (tag))\t/* Reverse order! */\n#define DT_VERSIONTAGNUM 16\n\n/* Sun added these machine-independent extensions in the \"processor-specific\"\n   range.  Be compatible.  */\n#define DT_AUXILIARY    0x7ffffffd      /* Shared object to load before self */\n#define DT_FILTER       0x7fffffff      /* Shared object to get values from */\n#define DT_EXTRATAGIDX(tag)\t((Elf32_Word)-((Elf32_Sword) (tag) <<1>>1)-1)\n#define DT_EXTRANUM\t3\n\n/* Values of `d_un.d_val' in the DT_FLAGS entry.  */\n#define DF_ORIGIN\t0x00000001\t/* Object may use DF_ORIGIN */\n#define DF_SYMBOLIC\t0x00000002\t/* Symbol resolutions starts here */\n#define DF_TEXTREL\t0x00000004\t/* Object contains text relocations */\n#define DF_BIND_NOW\t0x00000008\t/* No lazy binding for this object */\n#define DF_STATIC_TLS\t0x00000010\t/* Module uses the static TLS model */\n\n/* State flags selectable in the `d_un.d_val' element of the DT_FLAGS_1\n   entry in the dynamic section.  */\n#define DF_1_NOW\t0x00000001\t/* Set RTLD_NOW for this object.  */\n#define DF_1_GLOBAL\t0x00000002\t/* Set RTLD_GLOBAL for this object.  */\n#define DF_1_GROUP\t0x00000004\t/* Set RTLD_GROUP for this object.  */\n#define DF_1_NODELETE\t0x00000008\t/* Set RTLD_NODELETE for this object.*/\n#define DF_1_LOADFLTR\t0x00000010\t/* Trigger filtee loading at runtime.*/\n#define DF_1_INITFIRST\t0x00000020\t/* Set RTLD_INITFIRST for this object*/\n#define DF_1_NOOPEN\t0x00000040\t/* Set RTLD_NOOPEN for this object.  */\n#define DF_1_ORIGIN\t0x00000080\t/* $ORIGIN must be handled.  */\n#define DF_1_DIRECT\t0x00000100\t/* Direct binding enabled.  */\n#define DF_1_TRANS\t0x00000200\n#define DF_1_INTERPOSE\t0x00000400\t/* Object is used to interpose.  */\n#define DF_1_NODEFLIB\t0x00000800\t/* Ignore default lib search path.  */\n#define DF_1_NODUMP\t0x00001000\t/* Object can't be dldump'ed.  */\n#define DF_1_CONFALT\t0x00002000\t/* Configuration alternative created.*/\n#define DF_1_ENDFILTEE\t0x00004000\t/* Filtee terminates filters search. */\n#define\tDF_1_DISPRELDNE\t0x00008000\t/* Disp reloc applied at build time. */\n#define\tDF_1_DISPRELPND\t0x00010000\t/* Disp reloc applied at run-time.  */\n\n/* Flags for the feature selection in DT_FEATURE_1.  */\n#define DTF_1_PARINIT\t0x00000001\n#define DTF_1_CONFEXP\t0x00000002\n\n/* Flags in the DT_POSFLAG_1 entry effecting only the next DT_* entry.  */\n#define DF_P1_LAZYLOAD\t0x00000001\t/* Lazyload following object.  */\n#define DF_P1_GROUPPERM\t0x00000002\t/* Symbols from next object are not\n\t\t\t\t\t   generally available.  */\n\n/* Version definition sections.  */\n\ntypedef struct\n{\n  Elf32_Half\tvd_version;\t\t/* Version revision */\n  Elf32_Half\tvd_flags;\t\t/* Version information */\n  Elf32_Half\tvd_ndx;\t\t\t/* Version Index */\n  Elf32_Half\tvd_cnt;\t\t\t/* Number of associated aux entries */\n  Elf32_Word\tvd_hash;\t\t/* Version name hash value */\n  Elf32_Word\tvd_aux;\t\t\t/* Offset in bytes to verdaux array */\n  Elf32_Word\tvd_next;\t\t/* Offset in bytes to next verdef\n\t\t\t\t\t   entry */\n} Elf32_Verdef;\n\ntypedef struct\n{\n  Elf64_Half\tvd_version;\t\t/* Version revision */\n  Elf64_Half\tvd_flags;\t\t/* Version information */\n  Elf64_Half\tvd_ndx;\t\t\t/* Version Index */\n  Elf64_Half\tvd_cnt;\t\t\t/* Number of associated aux entries */\n  Elf64_Word\tvd_hash;\t\t/* Version name hash value */\n  Elf64_Word\tvd_aux;\t\t\t/* Offset in bytes to verdaux array */\n  Elf64_Word\tvd_next;\t\t/* Offset in bytes to next verdef\n\t\t\t\t\t   entry */\n} Elf64_Verdef;\n\n\n/* Legal values for vd_version (version revision).  */\n#define VER_DEF_NONE\t0\t\t/* No version */\n#define VER_DEF_CURRENT\t1\t\t/* Current version */\n#define VER_DEF_NUM\t2\t\t/* Given version number */\n\n/* Legal values for vd_flags (version information flags).  */\n#define VER_FLG_BASE\t0x1\t\t/* Version definition of file itself */\n#define VER_FLG_WEAK\t0x2\t\t/* Weak version identifier */\n\n/* Versym symbol index values.  */\n#define\tVER_NDX_LOCAL\t\t0\t/* Symbol is local.  */\n#define\tVER_NDX_GLOBAL\t\t1\t/* Symbol is global.  */\n#define\tVER_NDX_LORESERVE\t0xff00\t/* Beginning of reserved entries.  */\n#define\tVER_NDX_ELIMINATE\t0xff01\t/* Symbol is to be eliminated.  */\n\n/* Auxialiary version information.  */\n\ntypedef struct\n{\n  Elf32_Word\tvda_name;\t\t/* Version or dependency names */\n  Elf32_Word\tvda_next;\t\t/* Offset in bytes to next verdaux\n\t\t\t\t\t   entry */\n} Elf32_Verdaux;\n\ntypedef struct\n{\n  Elf64_Word\tvda_name;\t\t/* Version or dependency names */\n  Elf64_Word\tvda_next;\t\t/* Offset in bytes to next verdaux\n\t\t\t\t\t   entry */\n} Elf64_Verdaux;\n\n\n/* Version dependency section.  */\n\ntypedef struct\n{\n  Elf32_Half\tvn_version;\t\t/* Version of structure */\n  Elf32_Half\tvn_cnt;\t\t\t/* Number of associated aux entries */\n  Elf32_Word\tvn_file;\t\t/* Offset of filename for this\n\t\t\t\t\t   dependency */\n  Elf32_Word\tvn_aux;\t\t\t/* Offset in bytes to vernaux array */\n  Elf32_Word\tvn_next;\t\t/* Offset in bytes to next verneed\n\t\t\t\t\t   entry */\n} Elf32_Verneed;\n\ntypedef struct\n{\n  Elf64_Half\tvn_version;\t\t/* Version of structure */\n  Elf64_Half\tvn_cnt;\t\t\t/* Number of associated aux entries */\n  Elf64_Word\tvn_file;\t\t/* Offset of filename for this\n\t\t\t\t\t   dependency */\n  Elf64_Word\tvn_aux;\t\t\t/* Offset in bytes to vernaux array */\n  Elf64_Word\tvn_next;\t\t/* Offset in bytes to next verneed\n\t\t\t\t\t   entry */\n} Elf64_Verneed;\n\n\n/* Legal values for vn_version (version revision).  */\n#define VER_NEED_NONE\t 0\t\t/* No version */\n#define VER_NEED_CURRENT 1\t\t/* Current version */\n#define VER_NEED_NUM\t 2\t\t/* Given version number */\n\n/* Auxiliary needed version information.  */\n\ntypedef struct\n{\n  Elf32_Word\tvna_hash;\t\t/* Hash value of dependency name */\n  Elf32_Half\tvna_flags;\t\t/* Dependency specific information */\n  Elf32_Half\tvna_other;\t\t/* Unused */\n  Elf32_Word\tvna_name;\t\t/* Dependency name string offset */\n  Elf32_Word\tvna_next;\t\t/* Offset in bytes to next vernaux\n\t\t\t\t\t   entry */\n} Elf32_Vernaux;\n\ntypedef struct\n{\n  Elf64_Word\tvna_hash;\t\t/* Hash value of dependency name */\n  Elf64_Half\tvna_flags;\t\t/* Dependency specific information */\n  Elf64_Half\tvna_other;\t\t/* Unused */\n  Elf64_Word\tvna_name;\t\t/* Dependency name string offset */\n  Elf64_Word\tvna_next;\t\t/* Offset in bytes to next vernaux\n\t\t\t\t\t   entry */\n} Elf64_Vernaux;\n\n\n/* Legal values for vna_flags.  */\n#define VER_FLG_WEAK\t0x2\t\t/* Weak version identifier */\n\n\n/* Auxiliary vector.  */\n\n/* This vector is normally only used by the program interpreter.  The\n   usual definition in an ABI supplement uses the name auxv_t.  The\n   vector is not usually defined in a standard <elf.h> file, but it\n   can't hurt.  We rename it to avoid conflicts.  The sizes of these\n   types are an arrangement between the exec server and the program\n   interpreter, so we don't fully specify them here.  */\n\ntypedef struct\n{\n  uint32_t a_type;\t\t/* Entry type */\n  union\n    {\n      uint32_t a_val;\t\t/* Integer value */\n      /* We use to have pointer elements added here.  We cannot do that,\n\t though, since it does not work when using 32-bit definitions\n\t on 64-bit platforms and vice versa.  */\n    } a_un;\n} Elf32_auxv_t;\n\ntypedef struct\n{\n  uint64_t a_type;\t\t/* Entry type */\n  union\n    {\n      uint64_t a_val;\t\t/* Integer value */\n      /* We use to have pointer elements added here.  We cannot do that,\n\t though, since it does not work when using 32-bit definitions\n\t on 64-bit platforms and vice versa.  */\n    } a_un;\n} Elf64_auxv_t;\n\n/* Legal values for a_type (entry type).  */\n\n#define AT_NULL\t\t0\t\t/* End of vector */\n#define AT_IGNORE\t1\t\t/* Entry should be ignored */\n#define AT_EXECFD\t2\t\t/* File descriptor of program */\n#define AT_PHDR\t\t3\t\t/* Program headers for program */\n#define AT_PHENT\t4\t\t/* Size of program header entry */\n#define AT_PHNUM\t5\t\t/* Number of program headers */\n#define AT_PAGESZ\t6\t\t/* System page size */\n#define AT_BASE\t\t7\t\t/* Base address of interpreter */\n#define AT_FLAGS\t8\t\t/* Flags */\n#define AT_ENTRY\t9\t\t/* Entry point of program */\n#define AT_NOTELF\t10\t\t/* Program is not ELF */\n#define AT_UID\t\t11\t\t/* Real uid */\n#define AT_EUID\t\t12\t\t/* Effective uid */\n#define AT_GID\t\t13\t\t/* Real gid */\n#define AT_EGID\t\t14\t\t/* Effective gid */\n#define AT_CLKTCK\t17\t\t/* Frequency of times() */\n\n/* Some more special a_type values describing the hardware.  */\n#define AT_PLATFORM\t15\t\t/* String identifying platform.  */\n#define AT_HWCAP\t16\t\t/* Machine dependent hints about\n\t\t\t\t\t   processor capabilities.  */\n\n/* This entry gives some information about the FPU initialization\n   performed by the kernel.  */\n#define AT_FPUCW\t18\t\t/* Used FPU control word.  */\n\n/* Cache block sizes.  */\n#define AT_DCACHEBSIZE\t19\t\t/* Data cache block size.  */\n#define AT_ICACHEBSIZE\t20\t\t/* Instruction cache block size.  */\n#define AT_UCACHEBSIZE\t21\t\t/* Unified cache block size.  */\n\n/* A special ignored value for PPC, used by the kernel to control the\n   interpretation of the AUXV. Must be > 16.  */\n#define AT_IGNOREPPC\t22\t\t/* Entry should be ignored.  */\n\n#define\tAT_SECURE\t23\t\t/* Boolean, was exec setuid-like?  */\n\n#define AT_BASE_PLATFORM 24\t\t/* String identifying real platforms.*/\n\n#define AT_RANDOM\t25\t\t/* Address of 16 random bytes.  */\n\n#define AT_EXECFN\t31\t\t/* Filename of executable.  */\n\n/* Pointer to the global system page used for system calls and other\n   nice things.  */\n#define AT_SYSINFO\t32\n#define AT_SYSINFO_EHDR\t33\n\n/* Shapes of the caches.  Bits 0-3 contains associativity; bits 4-7 contains\n   log2 of line size; mask those to get cache size.  */\n#define AT_L1I_CACHESHAPE\t34\n#define AT_L1D_CACHESHAPE\t35\n#define AT_L2_CACHESHAPE\t36\n#define AT_L3_CACHESHAPE\t37\n\n/* Note section contents.  Each entry in the note section begins with\n   a header of a fixed form.  */\n\ntypedef struct\n{\n  Elf32_Word n_namesz;\t\t\t/* Length of the note's name.  */\n  Elf32_Word n_descsz;\t\t\t/* Length of the note's descriptor.  */\n  Elf32_Word n_type;\t\t\t/* Type of the note.  */\n} Elf32_Nhdr;\n\ntypedef struct\n{\n  Elf64_Word n_namesz;\t\t\t/* Length of the note's name.  */\n  Elf64_Word n_descsz;\t\t\t/* Length of the note's descriptor.  */\n  Elf64_Word n_type;\t\t\t/* Type of the note.  */\n} Elf64_Nhdr;\n\n/* Known names of notes.  */\n\n/* Solaris entries in the note section have this name.  */\n#define ELF_NOTE_SOLARIS\t\"SUNW Solaris\"\n\n/* Note entries for GNU systems have this name.  */\n#define ELF_NOTE_GNU\t\t\"GNU\"\n\n\n/* Defined types of notes for Solaris.  */\n\n/* Value of descriptor (one word) is desired pagesize for the binary.  */\n#define ELF_NOTE_PAGESIZE_HINT\t1\n\n\n/* Defined note types for GNU systems.  */\n\n/* ABI information.  The descriptor consists of words:\n   word 0: OS descriptor\n   word 1: major version of the ABI\n   word 2: minor version of the ABI\n   word 3: subminor version of the ABI\n*/\n#define NT_GNU_ABI_TAG\t1\n#define ELF_NOTE_ABI\tNT_GNU_ABI_TAG /* Old name.  */\n\n/* Known OSes.  These values can appear in word 0 of an\n   NT_GNU_ABI_TAG note section entry.  */\n#define ELF_NOTE_OS_LINUX\t0\n#define ELF_NOTE_OS_GNU\t\t1\n#define ELF_NOTE_OS_SOLARIS2\t2\n#define ELF_NOTE_OS_FREEBSD\t3\n\n/* Synthetic hwcap information.  The descriptor begins with two words:\n   word 0: number of entries\n   word 1: bitmask of enabled entries\n   Then follow variable-length entries, one byte followed by a\n   '\\0'-terminated hwcap name string.  The byte gives the bit\n   number to test if enabled, (1U << bit) & bitmask.  */\n#define NT_GNU_HWCAP\t2\n\n/* Build ID bits as generated by ld --build-id.\n   The descriptor consists of any nonzero number of bytes.  */\n#define NT_GNU_BUILD_ID\t3\n\n/* Version note generated by GNU gold containing a version string.  */\n#define NT_GNU_GOLD_VERSION\t4\n\n\n/* Move records.  */\ntypedef struct\n{\n  Elf32_Xword m_value;\t\t/* Symbol value.  */\n  Elf32_Word m_info;\t\t/* Size and index.  */\n  Elf32_Word m_poffset;\t\t/* Symbol offset.  */\n  Elf32_Half m_repeat;\t\t/* Repeat count.  */\n  Elf32_Half m_stride;\t\t/* Stride info.  */\n} Elf32_Move;\n\ntypedef struct\n{\n  Elf64_Xword m_value;\t\t/* Symbol value.  */\n  Elf64_Xword m_info;\t\t/* Size and index.  */\n  Elf64_Xword m_poffset;\t/* Symbol offset.  */\n  Elf64_Half m_repeat;\t\t/* Repeat count.  */\n  Elf64_Half m_stride;\t\t/* Stride info.  */\n} Elf64_Move;\n\n/* Macro to construct move records.  */\n#define ELF32_M_SYM(info)\t((info) >> 8)\n#define ELF32_M_SIZE(info)\t((unsigned char) (info))\n#define ELF32_M_INFO(sym, size)\t(((sym) << 8) + (unsigned char) (size))\n\n#define ELF64_M_SYM(info)\tELF32_M_SYM (info)\n#define ELF64_M_SIZE(info)\tELF32_M_SIZE (info)\n#define ELF64_M_INFO(sym, size)\tELF32_M_INFO (sym, size)\n\n\n/* Motorola 68k specific definitions.  */\n\n/* Values for Elf32_Ehdr.e_flags.  */\n#define EF_CPU32\t0x00810000\n\n/* m68k relocs.  */\n\n#define R_68K_NONE\t0\t\t/* No reloc */\n#define R_68K_32\t1\t\t/* Direct 32 bit  */\n#define R_68K_16\t2\t\t/* Direct 16 bit  */\n#define R_68K_8\t\t3\t\t/* Direct 8 bit  */\n#define R_68K_PC32\t4\t\t/* PC relative 32 bit */\n#define R_68K_PC16\t5\t\t/* PC relative 16 bit */\n#define R_68K_PC8\t6\t\t/* PC relative 8 bit */\n#define R_68K_GOT32\t7\t\t/* 32 bit PC relative GOT entry */\n#define R_68K_GOT16\t8\t\t/* 16 bit PC relative GOT entry */\n#define R_68K_GOT8\t9\t\t/* 8 bit PC relative GOT entry */\n#define R_68K_GOT32O\t10\t\t/* 32 bit GOT offset */\n#define R_68K_GOT16O\t11\t\t/* 16 bit GOT offset */\n#define R_68K_GOT8O\t12\t\t/* 8 bit GOT offset */\n#define R_68K_PLT32\t13\t\t/* 32 bit PC relative PLT address */\n#define R_68K_PLT16\t14\t\t/* 16 bit PC relative PLT address */\n#define R_68K_PLT8\t15\t\t/* 8 bit PC relative PLT address */\n#define R_68K_PLT32O\t16\t\t/* 32 bit PLT offset */\n#define R_68K_PLT16O\t17\t\t/* 16 bit PLT offset */\n#define R_68K_PLT8O\t18\t\t/* 8 bit PLT offset */\n#define R_68K_COPY\t19\t\t/* Copy symbol at runtime */\n#define R_68K_GLOB_DAT\t20\t\t/* Create GOT entry */\n#define R_68K_JMP_SLOT\t21\t\t/* Create PLT entry */\n#define R_68K_RELATIVE\t22\t\t/* Adjust by program base */\n#define R_68K_TLS_GD32      25          /* 32 bit GOT offset for GD */\n#define R_68K_TLS_GD16      26          /* 16 bit GOT offset for GD */\n#define R_68K_TLS_GD8       27          /* 8 bit GOT offset for GD */\n#define R_68K_TLS_LDM32     28          /* 32 bit GOT offset for LDM */\n#define R_68K_TLS_LDM16     29          /* 16 bit GOT offset for LDM */\n#define R_68K_TLS_LDM8      30          /* 8 bit GOT offset for LDM */\n#define R_68K_TLS_LDO32     31          /* 32 bit module-relative offset */\n#define R_68K_TLS_LDO16     32          /* 16 bit module-relative offset */\n#define R_68K_TLS_LDO8      33          /* 8 bit module-relative offset */\n#define R_68K_TLS_IE32      34          /* 32 bit GOT offset for IE */\n#define R_68K_TLS_IE16      35          /* 16 bit GOT offset for IE */\n#define R_68K_TLS_IE8       36          /* 8 bit GOT offset for IE */\n#define R_68K_TLS_LE32      37          /* 32 bit offset relative to\n\t\t\t\t\t   static TLS block */\n#define R_68K_TLS_LE16      38          /* 16 bit offset relative to\n\t\t\t\t\t   static TLS block */\n#define R_68K_TLS_LE8       39          /* 8 bit offset relative to\n\t\t\t\t\t   static TLS block */\n#define R_68K_TLS_DTPMOD32  40          /* 32 bit module number */\n#define R_68K_TLS_DTPREL32  41          /* 32 bit module-relative offset */\n#define R_68K_TLS_TPREL32   42          /* 32 bit TP-relative offset */\n/* Keep this the last entry.  */\n#define R_68K_NUM\t43\n\n/* Intel 80386 specific definitions.  */\n\n/* i386 relocs.  */\n\n#define R_386_NONE\t   0\t\t/* No reloc */\n#define R_386_32\t   1\t\t/* Direct 32 bit  */\n#define R_386_PC32\t   2\t\t/* PC relative 32 bit */\n#define R_386_GOT32\t   3\t\t/* 32 bit GOT entry */\n#define R_386_PLT32\t   4\t\t/* 32 bit PLT address */\n#define R_386_COPY\t   5\t\t/* Copy symbol at runtime */\n#define R_386_GLOB_DAT\t   6\t\t/* Create GOT entry */\n#define R_386_JMP_SLOT\t   7\t\t/* Create PLT entry */\n#define R_386_RELATIVE\t   8\t\t/* Adjust by program base */\n#define R_386_GOTOFF\t   9\t\t/* 32 bit offset to GOT */\n#define R_386_GOTPC\t   10\t\t/* 32 bit PC relative offset to GOT */\n#define R_386_32PLT\t   11\n#define R_386_TLS_TPOFF\t   14\t\t/* Offset in static TLS block */\n#define R_386_TLS_IE\t   15\t\t/* Address of GOT entry for static TLS\n\t\t\t\t\t   block offset */\n#define R_386_TLS_GOTIE\t   16\t\t/* GOT entry for static TLS block\n\t\t\t\t\t   offset */\n#define R_386_TLS_LE\t   17\t\t/* Offset relative to static TLS\n\t\t\t\t\t   block */\n#define R_386_TLS_GD\t   18\t\t/* Direct 32 bit for GNU version of\n\t\t\t\t\t   general dynamic thread local data */\n#define R_386_TLS_LDM\t   19\t\t/* Direct 32 bit for GNU version of\n\t\t\t\t\t   local dynamic thread local data\n\t\t\t\t\t   in LE code */\n#define R_386_16\t   20\n#define R_386_PC16\t   21\n#define R_386_8\t\t   22\n#define R_386_PC8\t   23\n#define R_386_TLS_GD_32\t   24\t\t/* Direct 32 bit for general dynamic\n\t\t\t\t\t   thread local data */\n#define R_386_TLS_GD_PUSH  25\t\t/* Tag for pushl in GD TLS code */\n#define R_386_TLS_GD_CALL  26\t\t/* Relocation for call to\n\t\t\t\t\t   __tls_get_addr() */\n#define R_386_TLS_GD_POP   27\t\t/* Tag for popl in GD TLS code */\n#define R_386_TLS_LDM_32   28\t\t/* Direct 32 bit for local dynamic\n\t\t\t\t\t   thread local data in LE code */\n#define R_386_TLS_LDM_PUSH 29\t\t/* Tag for pushl in LDM TLS code */\n#define R_386_TLS_LDM_CALL 30\t\t/* Relocation for call to\n\t\t\t\t\t   __tls_get_addr() in LDM code */\n#define R_386_TLS_LDM_POP  31\t\t/* Tag for popl in LDM TLS code */\n#define R_386_TLS_LDO_32   32\t\t/* Offset relative to TLS block */\n#define R_386_TLS_IE_32\t   33\t\t/* GOT entry for negated static TLS\n\t\t\t\t\t   block offset */\n#define R_386_TLS_LE_32\t   34\t\t/* Negated offset relative to static\n\t\t\t\t\t   TLS block */\n#define R_386_TLS_DTPMOD32 35\t\t/* ID of module containing symbol */\n#define R_386_TLS_DTPOFF32 36\t\t/* Offset in TLS block */\n#define R_386_TLS_TPOFF32  37\t\t/* Negated offset in static TLS block */\n/* 38? */\n#define R_386_TLS_GOTDESC  39\t\t/* GOT offset for TLS descriptor.  */\n#define R_386_TLS_DESC_CALL 40\t\t/* Marker of call through TLS\n\t\t\t\t\t   descriptor for\n\t\t\t\t\t   relaxation.  */\n#define R_386_TLS_DESC     41\t\t/* TLS descriptor containing\n\t\t\t\t\t   pointer to code and to\n\t\t\t\t\t   argument, returning the TLS\n\t\t\t\t\t   offset for the symbol.  */\n#define R_386_IRELATIVE\t   42\t\t/* Adjust indirectly by program base */\n/* Keep this the last entry.  */\n#define R_386_NUM\t   43\n\n/* SUN SPARC specific definitions.  */\n\n/* Legal values for ST_TYPE subfield of st_info (symbol type).  */\n\n#define STT_SPARC_REGISTER\t13\t/* Global register reserved to app. */\n\n/* Values for Elf64_Ehdr.e_flags.  */\n\n#define EF_SPARCV9_MM\t\t3\n#define EF_SPARCV9_TSO\t\t0\n#define EF_SPARCV9_PSO\t\t1\n#define EF_SPARCV9_RMO\t\t2\n#define EF_SPARC_LEDATA\t\t0x800000 /* little endian data */\n#define EF_SPARC_EXT_MASK\t0xFFFF00\n#define EF_SPARC_32PLUS\t\t0x000100 /* generic V8+ features */\n#define EF_SPARC_SUN_US1\t0x000200 /* Sun UltraSPARC1 extensions */\n#define EF_SPARC_HAL_R1\t\t0x000400 /* HAL R1 extensions */\n#define EF_SPARC_SUN_US3\t0x000800 /* Sun UltraSPARCIII extensions */\n\n/* SPARC relocs.  */\n\n#define R_SPARC_NONE\t\t0\t/* No reloc */\n#define R_SPARC_8\t\t1\t/* Direct 8 bit */\n#define R_SPARC_16\t\t2\t/* Direct 16 bit */\n#define R_SPARC_32\t\t3\t/* Direct 32 bit */\n#define R_SPARC_DISP8\t\t4\t/* PC relative 8 bit */\n#define R_SPARC_DISP16\t\t5\t/* PC relative 16 bit */\n#define R_SPARC_DISP32\t\t6\t/* PC relative 32 bit */\n#define R_SPARC_WDISP30\t\t7\t/* PC relative 30 bit shifted */\n#define R_SPARC_WDISP22\t\t8\t/* PC relative 22 bit shifted */\n#define R_SPARC_HI22\t\t9\t/* High 22 bit */\n#define R_SPARC_22\t\t10\t/* Direct 22 bit */\n#define R_SPARC_13\t\t11\t/* Direct 13 bit */\n#define R_SPARC_LO10\t\t12\t/* Truncated 10 bit */\n#define R_SPARC_GOT10\t\t13\t/* Truncated 10 bit GOT entry */\n#define R_SPARC_GOT13\t\t14\t/* 13 bit GOT entry */\n#define R_SPARC_GOT22\t\t15\t/* 22 bit GOT entry shifted */\n#define R_SPARC_PC10\t\t16\t/* PC relative 10 bit truncated */\n#define R_SPARC_PC22\t\t17\t/* PC relative 22 bit shifted */\n#define R_SPARC_WPLT30\t\t18\t/* 30 bit PC relative PLT address */\n#define R_SPARC_COPY\t\t19\t/* Copy symbol at runtime */\n#define R_SPARC_GLOB_DAT\t20\t/* Create GOT entry */\n#define R_SPARC_JMP_SLOT\t21\t/* Create PLT entry */\n#define R_SPARC_RELATIVE\t22\t/* Adjust by program base */\n#define R_SPARC_UA32\t\t23\t/* Direct 32 bit unaligned */\n\n/* Additional Sparc64 relocs.  */\n\n#define R_SPARC_PLT32\t\t24\t/* Direct 32 bit ref to PLT entry */\n#define R_SPARC_HIPLT22\t\t25\t/* High 22 bit PLT entry */\n#define R_SPARC_LOPLT10\t\t26\t/* Truncated 10 bit PLT entry */\n#define R_SPARC_PCPLT32\t\t27\t/* PC rel 32 bit ref to PLT entry */\n#define R_SPARC_PCPLT22\t\t28\t/* PC rel high 22 bit PLT entry */\n#define R_SPARC_PCPLT10\t\t29\t/* PC rel trunc 10 bit PLT entry */\n#define R_SPARC_10\t\t30\t/* Direct 10 bit */\n#define R_SPARC_11\t\t31\t/* Direct 11 bit */\n#define R_SPARC_64\t\t32\t/* Direct 64 bit */\n#define R_SPARC_OLO10\t\t33\t/* 10bit with secondary 13bit addend */\n#define R_SPARC_HH22\t\t34\t/* Top 22 bits of direct 64 bit */\n#define R_SPARC_HM10\t\t35\t/* High middle 10 bits of ... */\n#define R_SPARC_LM22\t\t36\t/* Low middle 22 bits of ... */\n#define R_SPARC_PC_HH22\t\t37\t/* Top 22 bits of pc rel 64 bit */\n#define R_SPARC_PC_HM10\t\t38\t/* High middle 10 bit of ... */\n#define R_SPARC_PC_LM22\t\t39\t/* Low miggle 22 bits of ... */\n#define R_SPARC_WDISP16\t\t40\t/* PC relative 16 bit shifted */\n#define R_SPARC_WDISP19\t\t41\t/* PC relative 19 bit shifted */\n#define R_SPARC_GLOB_JMP\t42\t/* was part of v9 ABI but was removed */\n#define R_SPARC_7\t\t43\t/* Direct 7 bit */\n#define R_SPARC_5\t\t44\t/* Direct 5 bit */\n#define R_SPARC_6\t\t45\t/* Direct 6 bit */\n#define R_SPARC_DISP64\t\t46\t/* PC relative 64 bit */\n#define R_SPARC_PLT64\t\t47\t/* Direct 64 bit ref to PLT entry */\n#define R_SPARC_HIX22\t\t48\t/* High 22 bit complemented */\n#define R_SPARC_LOX10\t\t49\t/* Truncated 11 bit complemented */\n#define R_SPARC_H44\t\t50\t/* Direct high 12 of 44 bit */\n#define R_SPARC_M44\t\t51\t/* Direct mid 22 of 44 bit */\n#define R_SPARC_L44\t\t52\t/* Direct low 10 of 44 bit */\n#define R_SPARC_REGISTER\t53\t/* Global register usage */\n#define R_SPARC_UA64\t\t54\t/* Direct 64 bit unaligned */\n#define R_SPARC_UA16\t\t55\t/* Direct 16 bit unaligned */\n#define R_SPARC_TLS_GD_HI22\t56\n#define R_SPARC_TLS_GD_LO10\t57\n#define R_SPARC_TLS_GD_ADD\t58\n#define R_SPARC_TLS_GD_CALL\t59\n#define R_SPARC_TLS_LDM_HI22\t60\n#define R_SPARC_TLS_LDM_LO10\t61\n#define R_SPARC_TLS_LDM_ADD\t62\n#define R_SPARC_TLS_LDM_CALL\t63\n#define R_SPARC_TLS_LDO_HIX22\t64\n#define R_SPARC_TLS_LDO_LOX10\t65\n#define R_SPARC_TLS_LDO_ADD\t66\n#define R_SPARC_TLS_IE_HI22\t67\n#define R_SPARC_TLS_IE_LO10\t68\n#define R_SPARC_TLS_IE_LD\t69\n#define R_SPARC_TLS_IE_LDX\t70\n#define R_SPARC_TLS_IE_ADD\t71\n#define R_SPARC_TLS_LE_HIX22\t72\n#define R_SPARC_TLS_LE_LOX10\t73\n#define R_SPARC_TLS_DTPMOD32\t74\n#define R_SPARC_TLS_DTPMOD64\t75\n#define R_SPARC_TLS_DTPOFF32\t76\n#define R_SPARC_TLS_DTPOFF64\t77\n#define R_SPARC_TLS_TPOFF32\t78\n#define R_SPARC_TLS_TPOFF64\t79\n#define R_SPARC_GOTDATA_HIX22\t80\n#define R_SPARC_GOTDATA_LOX10\t81\n#define R_SPARC_GOTDATA_OP_HIX22\t82\n#define R_SPARC_GOTDATA_OP_LOX10\t83\n#define R_SPARC_GOTDATA_OP\t84\n#define R_SPARC_H34\t\t85\n#define R_SPARC_SIZE32\t\t86\n#define R_SPARC_SIZE64\t\t87\n#define R_SPARC_WDISP10\t\t88\n#define R_SPARC_JMP_IREL\t248\n#define R_SPARC_IRELATIVE\t249\n#define R_SPARC_GNU_VTINHERIT\t250\n#define R_SPARC_GNU_VTENTRY\t251\n#define R_SPARC_REV32\t\t252\n/* Keep this the last entry.  */\n#define R_SPARC_NUM\t\t253\n\n/* For Sparc64, legal values for d_tag of Elf64_Dyn.  */\n\n#define DT_SPARC_REGISTER 0x70000001\n#define DT_SPARC_NUM\t2\n\n/* MIPS R3000 specific definitions.  */\n\n/* Legal values for e_flags field of Elf32_Ehdr.  */\n\n#define EF_MIPS_NOREORDER   1\t\t/* A .noreorder directive was used */\n#define EF_MIPS_PIC\t    2\t\t/* Contains PIC code */\n#define EF_MIPS_CPIC\t    4\t\t/* Uses PIC calling sequence */\n#define EF_MIPS_XGOT\t    8\n#define EF_MIPS_64BIT_WHIRL 16\n#define EF_MIPS_ABI2\t    32\n#define EF_MIPS_ABI_ON32    64\n#define EF_MIPS_ARCH\t    0xf0000000\t/* MIPS architecture level */\n\n/* Legal values for MIPS architecture level.  */\n\n#define EF_MIPS_ARCH_1\t    0x00000000\t/* -mips1 code.  */\n#define EF_MIPS_ARCH_2\t    0x10000000\t/* -mips2 code.  */\n#define EF_MIPS_ARCH_3\t    0x20000000\t/* -mips3 code.  */\n#define EF_MIPS_ARCH_4\t    0x30000000\t/* -mips4 code.  */\n#define EF_MIPS_ARCH_5\t    0x40000000\t/* -mips5 code.  */\n#define EF_MIPS_ARCH_32\t    0x60000000\t/* MIPS32 code.  */\n#define EF_MIPS_ARCH_64\t    0x70000000\t/* MIPS64 code.  */\n\n/* The following are non-official names and should not be used.  */\n\n#define E_MIPS_ARCH_1\t  0x00000000\t/* -mips1 code.  */\n#define E_MIPS_ARCH_2\t  0x10000000\t/* -mips2 code.  */\n#define E_MIPS_ARCH_3\t  0x20000000\t/* -mips3 code.  */\n#define E_MIPS_ARCH_4\t  0x30000000\t/* -mips4 code.  */\n#define E_MIPS_ARCH_5\t  0x40000000\t/* -mips5 code.  */\n#define E_MIPS_ARCH_32\t  0x60000000\t/* MIPS32 code.  */\n#define E_MIPS_ARCH_64\t  0x70000000\t/* MIPS64 code.  */\n\n/* Special section indices.  */\n\n#define SHN_MIPS_ACOMMON    0xff00\t/* Allocated common symbols */\n#define SHN_MIPS_TEXT\t    0xff01\t/* Allocated test symbols.  */\n#define SHN_MIPS_DATA\t    0xff02\t/* Allocated data symbols.  */\n#define SHN_MIPS_SCOMMON    0xff03\t/* Small common symbols */\n#define SHN_MIPS_SUNDEFINED 0xff04\t/* Small undefined symbols */\n\n/* Legal values for sh_type field of Elf32_Shdr.  */\n\n#define SHT_MIPS_LIBLIST       0x70000000 /* Shared objects used in link */\n#define SHT_MIPS_MSYM\t       0x70000001\n#define SHT_MIPS_CONFLICT      0x70000002 /* Conflicting symbols */\n#define SHT_MIPS_GPTAB\t       0x70000003 /* Global data area sizes */\n#define SHT_MIPS_UCODE\t       0x70000004 /* Reserved for SGI/MIPS compilers */\n#define SHT_MIPS_DEBUG\t       0x70000005 /* MIPS ECOFF debugging information*/\n#define SHT_MIPS_REGINFO       0x70000006 /* Register usage information */\n#define SHT_MIPS_PACKAGE       0x70000007\n#define SHT_MIPS_PACKSYM       0x70000008\n#define SHT_MIPS_RELD\t       0x70000009\n#define SHT_MIPS_IFACE         0x7000000b\n#define SHT_MIPS_CONTENT       0x7000000c\n#define SHT_MIPS_OPTIONS       0x7000000d /* Miscellaneous options.  */\n#define SHT_MIPS_SHDR\t       0x70000010\n#define SHT_MIPS_FDESC\t       0x70000011\n#define SHT_MIPS_EXTSYM\t       0x70000012\n#define SHT_MIPS_DENSE\t       0x70000013\n#define SHT_MIPS_PDESC\t       0x70000014\n#define SHT_MIPS_LOCSYM\t       0x70000015\n#define SHT_MIPS_AUXSYM\t       0x70000016\n#define SHT_MIPS_OPTSYM\t       0x70000017\n#define SHT_MIPS_LOCSTR\t       0x70000018\n#define SHT_MIPS_LINE\t       0x70000019\n#define SHT_MIPS_RFDESC\t       0x7000001a\n#define SHT_MIPS_DELTASYM      0x7000001b\n#define SHT_MIPS_DELTAINST     0x7000001c\n#define SHT_MIPS_DELTACLASS    0x7000001d\n#define SHT_MIPS_DWARF         0x7000001e /* DWARF debugging information.  */\n#define SHT_MIPS_DELTADECL     0x7000001f\n#define SHT_MIPS_SYMBOL_LIB    0x70000020\n#define SHT_MIPS_EVENTS\t       0x70000021 /* Event section.  */\n#define SHT_MIPS_TRANSLATE     0x70000022\n#define SHT_MIPS_PIXIE\t       0x70000023\n#define SHT_MIPS_XLATE\t       0x70000024\n#define SHT_MIPS_XLATE_DEBUG   0x70000025\n#define SHT_MIPS_WHIRL\t       0x70000026\n#define SHT_MIPS_EH_REGION     0x70000027\n#define SHT_MIPS_XLATE_OLD     0x70000028\n#define SHT_MIPS_PDR_EXCEPTION 0x70000029\n\n/* Legal values for sh_flags field of Elf32_Shdr.  */\n\n#define SHF_MIPS_GPREL\t 0x10000000\t/* Must be part of global data area */\n#define SHF_MIPS_MERGE\t 0x20000000\n#define SHF_MIPS_ADDR\t 0x40000000\n#define SHF_MIPS_STRINGS 0x80000000\n#define SHF_MIPS_NOSTRIP 0x08000000\n#define SHF_MIPS_LOCAL\t 0x04000000\n#define SHF_MIPS_NAMES\t 0x02000000\n#define SHF_MIPS_NODUPE\t 0x01000000\n\n\n/* Symbol tables.  */\n\n/* MIPS specific values for `st_other'.  */\n#define STO_MIPS_DEFAULT\t\t0x0\n#define STO_MIPS_INTERNAL\t\t0x1\n#define STO_MIPS_HIDDEN\t\t\t0x2\n#define STO_MIPS_PROTECTED\t\t0x3\n#define STO_MIPS_PLT\t\t\t0x8\n#define STO_MIPS_SC_ALIGN_UNUSED\t0xff\n\n/* MIPS specific values for `st_info'.  */\n#define STB_MIPS_SPLIT_COMMON\t\t13\n\n/* Entries found in sections of type SHT_MIPS_GPTAB.  */\n\ntypedef union\n{\n  struct\n    {\n      Elf32_Word gt_current_g_value;\t/* -G value used for compilation */\n      Elf32_Word gt_unused;\t\t/* Not used */\n    } gt_header;\t\t\t/* First entry in section */\n  struct\n    {\n      Elf32_Word gt_g_value;\t\t/* If this value were used for -G */\n      Elf32_Word gt_bytes;\t\t/* This many bytes would be used */\n    } gt_entry;\t\t\t\t/* Subsequent entries in section */\n} Elf32_gptab;\n\n/* Entry found in sections of type SHT_MIPS_REGINFO.  */\n\ntypedef struct\n{\n  Elf32_Word\tri_gprmask;\t\t/* General registers used */\n  Elf32_Word\tri_cprmask[4];\t\t/* Coprocessor registers used */\n  Elf32_Sword\tri_gp_value;\t\t/* $gp register value */\n} Elf32_RegInfo;\n\n/* Entries found in sections of type SHT_MIPS_OPTIONS.  */\n\ntypedef struct\n{\n  unsigned char kind;\t\t/* Determines interpretation of the\n\t\t\t\t   variable part of descriptor.  */\n  unsigned char size;\t\t/* Size of descriptor, including header.  */\n  Elf32_Section section;\t/* Section header index of section affected,\n\t\t\t\t   0 for global options.  */\n  Elf32_Word info;\t\t/* Kind-specific information.  */\n} Elf_Options;\n\n/* Values for `kind' field in Elf_Options.  */\n\n#define ODK_NULL\t0\t/* Undefined.  */\n#define ODK_REGINFO\t1\t/* Register usage information.  */\n#define ODK_EXCEPTIONS\t2\t/* Exception processing options.  */\n#define ODK_PAD\t\t3\t/* Section padding options.  */\n#define ODK_HWPATCH\t4\t/* Hardware workarounds performed */\n#define ODK_FILL\t5\t/* record the fill value used by the linker. */\n#define ODK_TAGS\t6\t/* reserve space for desktop tools to write. */\n#define ODK_HWAND\t7\t/* HW workarounds.  'AND' bits when merging. */\n#define ODK_HWOR\t8\t/* HW workarounds.  'OR' bits when merging.  */\n\n/* Values for `info' in Elf_Options for ODK_EXCEPTIONS entries.  */\n\n#define OEX_FPU_MIN\t0x1f\t/* FPE's which MUST be enabled.  */\n#define OEX_FPU_MAX\t0x1f00\t/* FPE's which MAY be enabled.  */\n#define OEX_PAGE0\t0x10000\t/* page zero must be mapped.  */\n#define OEX_SMM\t\t0x20000\t/* Force sequential memory mode?  */\n#define OEX_FPDBUG\t0x40000\t/* Force floating point debug mode?  */\n#define OEX_PRECISEFP\tOEX_FPDBUG\n#define OEX_DISMISS\t0x80000\t/* Dismiss invalid address faults?  */\n\n#define OEX_FPU_INVAL\t0x10\n#define OEX_FPU_DIV0\t0x08\n#define OEX_FPU_OFLO\t0x04\n#define OEX_FPU_UFLO\t0x02\n#define OEX_FPU_INEX\t0x01\n\n/* Masks for `info' in Elf_Options for an ODK_HWPATCH entry.  */\n\n#define OHW_R4KEOP\t0x1\t/* R4000 end-of-page patch.  */\n#define OHW_R8KPFETCH\t0x2\t/* may need R8000 prefetch patch.  */\n#define OHW_R5KEOP\t0x4\t/* R5000 end-of-page patch.  */\n#define OHW_R5KCVTL\t0x8\t/* R5000 cvt.[ds].l bug.  clean=1.  */\n\n#define OPAD_PREFIX\t0x1\n#define OPAD_POSTFIX\t0x2\n#define OPAD_SYMBOL\t0x4\n\n/* Entry found in `.options' section.  */\n\ntypedef struct\n{\n  Elf32_Word hwp_flags1;\t/* Extra flags.  */\n  Elf32_Word hwp_flags2;\t/* Extra flags.  */\n} Elf_Options_Hw;\n\n/* Masks for `info' in ElfOptions for ODK_HWAND and ODK_HWOR entries.  */\n\n#define OHWA0_R4KEOP_CHECKED\t0x00000001\n#define OHWA1_R4KEOP_CLEAN\t0x00000002\n\n/* MIPS relocs.  */\n\n#define R_MIPS_NONE\t\t0\t/* No reloc */\n#define R_MIPS_16\t\t1\t/* Direct 16 bit */\n#define R_MIPS_32\t\t2\t/* Direct 32 bit */\n#define R_MIPS_REL32\t\t3\t/* PC relative 32 bit */\n#define R_MIPS_26\t\t4\t/* Direct 26 bit shifted */\n#define R_MIPS_HI16\t\t5\t/* High 16 bit */\n#define R_MIPS_LO16\t\t6\t/* Low 16 bit */\n#define R_MIPS_GPREL16\t\t7\t/* GP relative 16 bit */\n#define R_MIPS_LITERAL\t\t8\t/* 16 bit literal entry */\n#define R_MIPS_GOT16\t\t9\t/* 16 bit GOT entry */\n#define R_MIPS_PC16\t\t10\t/* PC relative 16 bit */\n#define R_MIPS_CALL16\t\t11\t/* 16 bit GOT entry for function */\n#define R_MIPS_GPREL32\t\t12\t/* GP relative 32 bit */\n\n#define R_MIPS_SHIFT5\t\t16\n#define R_MIPS_SHIFT6\t\t17\n#define R_MIPS_64\t\t18\n#define R_MIPS_GOT_DISP\t\t19\n#define R_MIPS_GOT_PAGE\t\t20\n#define R_MIPS_GOT_OFST\t\t21\n#define R_MIPS_GOT_HI16\t\t22\n#define R_MIPS_GOT_LO16\t\t23\n#define R_MIPS_SUB\t\t24\n#define R_MIPS_INSERT_A\t\t25\n#define R_MIPS_INSERT_B\t\t26\n#define R_MIPS_DELETE\t\t27\n#define R_MIPS_HIGHER\t\t28\n#define R_MIPS_HIGHEST\t\t29\n#define R_MIPS_CALL_HI16\t30\n#define R_MIPS_CALL_LO16\t31\n#define R_MIPS_SCN_DISP\t\t32\n#define R_MIPS_REL16\t\t33\n#define R_MIPS_ADD_IMMEDIATE\t34\n#define R_MIPS_PJUMP\t\t35\n#define R_MIPS_RELGOT\t\t36\n#define R_MIPS_JALR\t\t37\n#define R_MIPS_TLS_DTPMOD32\t38\t/* Module number 32 bit */\n#define R_MIPS_TLS_DTPREL32\t39\t/* Module-relative offset 32 bit */\n#define R_MIPS_TLS_DTPMOD64\t40\t/* Module number 64 bit */\n#define R_MIPS_TLS_DTPREL64\t41\t/* Module-relative offset 64 bit */\n#define R_MIPS_TLS_GD\t\t42\t/* 16 bit GOT offset for GD */\n#define R_MIPS_TLS_LDM\t\t43\t/* 16 bit GOT offset for LDM */\n#define R_MIPS_TLS_DTPREL_HI16\t44\t/* Module-relative offset, high 16 bits */\n#define R_MIPS_TLS_DTPREL_LO16\t45\t/* Module-relative offset, low 16 bits */\n#define R_MIPS_TLS_GOTTPREL\t46\t/* 16 bit GOT offset for IE */\n#define R_MIPS_TLS_TPREL32\t47\t/* TP-relative offset, 32 bit */\n#define R_MIPS_TLS_TPREL64\t48\t/* TP-relative offset, 64 bit */\n#define R_MIPS_TLS_TPREL_HI16\t49\t/* TP-relative offset, high 16 bits */\n#define R_MIPS_TLS_TPREL_LO16\t50\t/* TP-relative offset, low 16 bits */\n#define R_MIPS_GLOB_DAT\t\t51\n#define R_MIPS_COPY\t\t126\n#define R_MIPS_JUMP_SLOT        127\n/* Keep this the last entry.  */\n#define R_MIPS_NUM\t\t128\n\n/* Legal values for p_type field of Elf32_Phdr.  */\n\n#define PT_MIPS_REGINFO\t0x70000000\t/* Register usage information */\n#define PT_MIPS_RTPROC  0x70000001\t/* Runtime procedure table. */\n#define PT_MIPS_OPTIONS 0x70000002\n\n/* Special program header types.  */\n\n#define PF_MIPS_LOCAL\t0x10000000\n\n/* Legal values for d_tag field of Elf32_Dyn.  */\n\n#define DT_MIPS_RLD_VERSION  0x70000001\t/* Runtime linker interface version */\n#define DT_MIPS_TIME_STAMP   0x70000002\t/* Timestamp */\n#define DT_MIPS_ICHECKSUM    0x70000003\t/* Checksum */\n#define DT_MIPS_IVERSION     0x70000004\t/* Version string (string tbl index) */\n#define DT_MIPS_FLAGS\t     0x70000005\t/* Flags */\n#define DT_MIPS_BASE_ADDRESS 0x70000006\t/* Base address */\n#define DT_MIPS_MSYM\t     0x70000007\n#define DT_MIPS_CONFLICT     0x70000008\t/* Address of CONFLICT section */\n#define DT_MIPS_LIBLIST\t     0x70000009\t/* Address of LIBLIST section */\n#define DT_MIPS_LOCAL_GOTNO  0x7000000a\t/* Number of local GOT entries */\n#define DT_MIPS_CONFLICTNO   0x7000000b\t/* Number of CONFLICT entries */\n#define DT_MIPS_LIBLISTNO    0x70000010\t/* Number of LIBLIST entries */\n#define DT_MIPS_SYMTABNO     0x70000011\t/* Number of DYNSYM entries */\n#define DT_MIPS_UNREFEXTNO   0x70000012\t/* First external DYNSYM */\n#define DT_MIPS_GOTSYM\t     0x70000013\t/* First GOT entry in DYNSYM */\n#define DT_MIPS_HIPAGENO     0x70000014\t/* Number of GOT page table entries */\n#define DT_MIPS_RLD_MAP\t     0x70000016\t/* Address of run time loader map.  */\n#define DT_MIPS_DELTA_CLASS  0x70000017\t/* Delta C++ class definition.  */\n#define DT_MIPS_DELTA_CLASS_NO    0x70000018 /* Number of entries in\n\t\t\t\t\t\tDT_MIPS_DELTA_CLASS.  */\n#define DT_MIPS_DELTA_INSTANCE    0x70000019 /* Delta C++ class instances.  */\n#define DT_MIPS_DELTA_INSTANCE_NO 0x7000001a /* Number of entries in\n\t\t\t\t\t\tDT_MIPS_DELTA_INSTANCE.  */\n#define DT_MIPS_DELTA_RELOC  0x7000001b /* Delta relocations.  */\n#define DT_MIPS_DELTA_RELOC_NO 0x7000001c /* Number of entries in\n\t\t\t\t\t     DT_MIPS_DELTA_RELOC.  */\n#define DT_MIPS_DELTA_SYM    0x7000001d /* Delta symbols that Delta\n\t\t\t\t\t   relocations refer to.  */\n#define DT_MIPS_DELTA_SYM_NO 0x7000001e /* Number of entries in\n\t\t\t\t\t   DT_MIPS_DELTA_SYM.  */\n#define DT_MIPS_DELTA_CLASSSYM 0x70000020 /* Delta symbols that hold the\n\t\t\t\t\t     class declaration.  */\n#define DT_MIPS_DELTA_CLASSSYM_NO 0x70000021 /* Number of entries in\n\t\t\t\t\t\tDT_MIPS_DELTA_CLASSSYM.  */\n#define DT_MIPS_CXX_FLAGS    0x70000022 /* Flags indicating for C++ flavor.  */\n#define DT_MIPS_PIXIE_INIT   0x70000023\n#define DT_MIPS_SYMBOL_LIB   0x70000024\n#define DT_MIPS_LOCALPAGE_GOTIDX 0x70000025\n#define DT_MIPS_LOCAL_GOTIDX 0x70000026\n#define DT_MIPS_HIDDEN_GOTIDX 0x70000027\n#define DT_MIPS_PROTECTED_GOTIDX 0x70000028\n#define DT_MIPS_OPTIONS\t     0x70000029 /* Address of .options.  */\n#define DT_MIPS_INTERFACE    0x7000002a /* Address of .interface.  */\n#define DT_MIPS_DYNSTR_ALIGN 0x7000002b\n#define DT_MIPS_INTERFACE_SIZE 0x7000002c /* Size of the .interface section. */\n#define DT_MIPS_RLD_TEXT_RESOLVE_ADDR 0x7000002d /* Address of rld_text_rsolve\n\t\t\t\t\t\t    function stored in GOT.  */\n#define DT_MIPS_PERF_SUFFIX  0x7000002e /* Default suffix of dso to be added\n\t\t\t\t\t   by rld on dlopen() calls.  */\n#define DT_MIPS_COMPACT_SIZE 0x7000002f /* (O32)Size of compact rel section. */\n#define DT_MIPS_GP_VALUE     0x70000030 /* GP value for aux GOTs.  */\n#define DT_MIPS_AUX_DYNAMIC  0x70000031 /* Address of aux .dynamic.  */\n/* The address of .got.plt in an executable using the new non-PIC ABI.  */\n#define DT_MIPS_PLTGOT\t     0x70000032\n/* The base of the PLT in an executable using the new non-PIC ABI if that\n   PLT is writable.  For a non-writable PLT, this is omitted or has a zero\n   value.  */\n#define DT_MIPS_RWPLT        0x70000034\n#define DT_MIPS_NUM\t     0x35\n\n/* Legal values for DT_MIPS_FLAGS Elf32_Dyn entry.  */\n\n#define RHF_NONE\t\t   0\t\t/* No flags */\n#define RHF_QUICKSTART\t\t   (1 << 0)\t/* Use quickstart */\n#define RHF_NOTPOT\t\t   (1 << 1)\t/* Hash size not power of 2 */\n#define RHF_NO_LIBRARY_REPLACEMENT (1 << 2)\t/* Ignore LD_LIBRARY_PATH */\n#define RHF_NO_MOVE\t\t   (1 << 3)\n#define RHF_SGI_ONLY\t\t   (1 << 4)\n#define RHF_GUARANTEE_INIT\t   (1 << 5)\n#define RHF_DELTA_C_PLUS_PLUS\t   (1 << 6)\n#define RHF_GUARANTEE_START_INIT   (1 << 7)\n#define RHF_PIXIE\t\t   (1 << 8)\n#define RHF_DEFAULT_DELAY_LOAD\t   (1 << 9)\n#define RHF_REQUICKSTART\t   (1 << 10)\n#define RHF_REQUICKSTARTED\t   (1 << 11)\n#define RHF_CORD\t\t   (1 << 12)\n#define RHF_NO_UNRES_UNDEF\t   (1 << 13)\n#define RHF_RLD_ORDER_SAFE\t   (1 << 14)\n\n/* Entries found in sections of type SHT_MIPS_LIBLIST.  */\n\ntypedef struct\n{\n  Elf32_Word l_name;\t\t/* Name (string table index) */\n  Elf32_Word l_time_stamp;\t/* Timestamp */\n  Elf32_Word l_checksum;\t/* Checksum */\n  Elf32_Word l_version;\t\t/* Interface version */\n  Elf32_Word l_flags;\t\t/* Flags */\n} Elf32_Lib;\n\ntypedef struct\n{\n  Elf64_Word l_name;\t\t/* Name (string table index) */\n  Elf64_Word l_time_stamp;\t/* Timestamp */\n  Elf64_Word l_checksum;\t/* Checksum */\n  Elf64_Word l_version;\t\t/* Interface version */\n  Elf64_Word l_flags;\t\t/* Flags */\n} Elf64_Lib;\n\n\n/* Legal values for l_flags.  */\n\n#define LL_NONE\t\t  0\n#define LL_EXACT_MATCH\t  (1 << 0)\t/* Require exact match */\n#define LL_IGNORE_INT_VER (1 << 1)\t/* Ignore interface version */\n#define LL_REQUIRE_MINOR  (1 << 2)\n#define LL_EXPORTS\t  (1 << 3)\n#define LL_DELAY_LOAD\t  (1 << 4)\n#define LL_DELTA\t  (1 << 5)\n\n/* Entries found in sections of type SHT_MIPS_CONFLICT.  */\n\ntypedef Elf32_Addr Elf32_Conflict;\n\n\n/* HPPA specific definitions.  */\n\n/* Legal values for e_flags field of Elf32_Ehdr.  */\n\n#define EF_PARISC_TRAPNIL\t0x00010000 /* Trap nil pointer dereference.  */\n#define EF_PARISC_EXT\t\t0x00020000 /* Program uses arch. extensions. */\n#define EF_PARISC_LSB\t\t0x00040000 /* Program expects little endian. */\n#define EF_PARISC_WIDE\t\t0x00080000 /* Program expects wide mode.  */\n#define EF_PARISC_NO_KABP\t0x00100000 /* No kernel assisted branch\n\t\t\t\t\t      prediction.  */\n#define EF_PARISC_LAZYSWAP\t0x00400000 /* Allow lazy swapping.  */\n#define EF_PARISC_ARCH\t\t0x0000ffff /* Architecture version.  */\n\n/* Defined values for `e_flags & EF_PARISC_ARCH' are:  */\n\n#define EFA_PARISC_1_0\t\t    0x020b /* PA-RISC 1.0 big-endian.  */\n#define EFA_PARISC_1_1\t\t    0x0210 /* PA-RISC 1.1 big-endian.  */\n#define EFA_PARISC_2_0\t\t    0x0214 /* PA-RISC 2.0 big-endian.  */\n\n/* Additional section indeces.  */\n\n#define SHN_PARISC_ANSI_COMMON\t0xff00\t   /* Section for tenatively declared\n\t\t\t\t\t      symbols in ANSI C.  */\n#define SHN_PARISC_HUGE_COMMON\t0xff01\t   /* Common blocks in huge model.  */\n\n/* Legal values for sh_type field of Elf32_Shdr.  */\n\n#define SHT_PARISC_EXT\t\t0x70000000 /* Contains product specific ext. */\n#define SHT_PARISC_UNWIND\t0x70000001 /* Unwind information.  */\n#define SHT_PARISC_DOC\t\t0x70000002 /* Debug info for optimized code. */\n\n/* Legal values for sh_flags field of Elf32_Shdr.  */\n\n#define SHF_PARISC_SHORT\t0x20000000 /* Section with short addressing. */\n#define SHF_PARISC_HUGE\t\t0x40000000 /* Section far from gp.  */\n#define SHF_PARISC_SBP\t\t0x80000000 /* Static branch prediction code. */\n\n/* Legal values for ST_TYPE subfield of st_info (symbol type).  */\n\n#define STT_PARISC_MILLICODE\t13\t/* Millicode function entry point.  */\n\n#define STT_HP_OPAQUE\t\t(STT_LOOS + 0x1)\n#define STT_HP_STUB\t\t(STT_LOOS + 0x2)\n\n/* HPPA relocs.  */\n\n#define R_PARISC_NONE\t\t0\t/* No reloc.  */\n#define R_PARISC_DIR32\t\t1\t/* Direct 32-bit reference.  */\n#define R_PARISC_DIR21L\t\t2\t/* Left 21 bits of eff. address.  */\n#define R_PARISC_DIR17R\t\t3\t/* Right 17 bits of eff. address.  */\n#define R_PARISC_DIR17F\t\t4\t/* 17 bits of eff. address.  */\n#define R_PARISC_DIR14R\t\t6\t/* Right 14 bits of eff. address.  */\n#define R_PARISC_PCREL32\t9\t/* 32-bit rel. address.  */\n#define R_PARISC_PCREL21L\t10\t/* Left 21 bits of rel. address.  */\n#define R_PARISC_PCREL17R\t11\t/* Right 17 bits of rel. address.  */\n#define R_PARISC_PCREL17F\t12\t/* 17 bits of rel. address.  */\n#define R_PARISC_PCREL14R\t14\t/* Right 14 bits of rel. address.  */\n#define R_PARISC_DPREL21L\t18\t/* Left 21 bits of rel. address.  */\n#define R_PARISC_DPREL14R\t22\t/* Right 14 bits of rel. address.  */\n#define R_PARISC_GPREL21L\t26\t/* GP-relative, left 21 bits.  */\n#define R_PARISC_GPREL14R\t30\t/* GP-relative, right 14 bits.  */\n#define R_PARISC_LTOFF21L\t34\t/* LT-relative, left 21 bits.  */\n#define R_PARISC_LTOFF14R\t38\t/* LT-relative, right 14 bits.  */\n#define R_PARISC_SECREL32\t41\t/* 32 bits section rel. address.  */\n#define R_PARISC_SEGBASE\t48\t/* No relocation, set segment base.  */\n#define R_PARISC_SEGREL32\t49\t/* 32 bits segment rel. address.  */\n#define R_PARISC_PLTOFF21L\t50\t/* PLT rel. address, left 21 bits.  */\n#define R_PARISC_PLTOFF14R\t54\t/* PLT rel. address, right 14 bits.  */\n#define R_PARISC_LTOFF_FPTR32\t57\t/* 32 bits LT-rel. function pointer. */\n#define R_PARISC_LTOFF_FPTR21L\t58\t/* LT-rel. fct ptr, left 21 bits. */\n#define R_PARISC_LTOFF_FPTR14R\t62\t/* LT-rel. fct ptr, right 14 bits. */\n#define R_PARISC_FPTR64\t\t64\t/* 64 bits function address.  */\n#define R_PARISC_PLABEL32\t65\t/* 32 bits function address.  */\n#define R_PARISC_PLABEL21L\t66\t/* Left 21 bits of fdesc address.  */\n#define R_PARISC_PLABEL14R\t70\t/* Right 14 bits of fdesc address.  */\n#define R_PARISC_PCREL64\t72\t/* 64 bits PC-rel. address.  */\n#define R_PARISC_PCREL22F\t74\t/* 22 bits PC-rel. address.  */\n#define R_PARISC_PCREL14WR\t75\t/* PC-rel. address, right 14 bits.  */\n#define R_PARISC_PCREL14DR\t76\t/* PC rel. address, right 14 bits.  */\n#define R_PARISC_PCREL16F\t77\t/* 16 bits PC-rel. address.  */\n#define R_PARISC_PCREL16WF\t78\t/* 16 bits PC-rel. address.  */\n#define R_PARISC_PCREL16DF\t79\t/* 16 bits PC-rel. address.  */\n#define R_PARISC_DIR64\t\t80\t/* 64 bits of eff. address.  */\n#define R_PARISC_DIR14WR\t83\t/* 14 bits of eff. address.  */\n#define R_PARISC_DIR14DR\t84\t/* 14 bits of eff. address.  */\n#define R_PARISC_DIR16F\t\t85\t/* 16 bits of eff. address.  */\n#define R_PARISC_DIR16WF\t86\t/* 16 bits of eff. address.  */\n#define R_PARISC_DIR16DF\t87\t/* 16 bits of eff. address.  */\n#define R_PARISC_GPREL64\t88\t/* 64 bits of GP-rel. address.  */\n#define R_PARISC_GPREL14WR\t91\t/* GP-rel. address, right 14 bits.  */\n#define R_PARISC_GPREL14DR\t92\t/* GP-rel. address, right 14 bits.  */\n#define R_PARISC_GPREL16F\t93\t/* 16 bits GP-rel. address.  */\n#define R_PARISC_GPREL16WF\t94\t/* 16 bits GP-rel. address.  */\n#define R_PARISC_GPREL16DF\t95\t/* 16 bits GP-rel. address.  */\n#define R_PARISC_LTOFF64\t96\t/* 64 bits LT-rel. address.  */\n#define R_PARISC_LTOFF14WR\t99\t/* LT-rel. address, right 14 bits.  */\n#define R_PARISC_LTOFF14DR\t100\t/* LT-rel. address, right 14 bits.  */\n#define R_PARISC_LTOFF16F\t101\t/* 16 bits LT-rel. address.  */\n#define R_PARISC_LTOFF16WF\t102\t/* 16 bits LT-rel. address.  */\n#define R_PARISC_LTOFF16DF\t103\t/* 16 bits LT-rel. address.  */\n#define R_PARISC_SECREL64\t104\t/* 64 bits section rel. address.  */\n#define R_PARISC_SEGREL64\t112\t/* 64 bits segment rel. address.  */\n#define R_PARISC_PLTOFF14WR\t115\t/* PLT-rel. address, right 14 bits.  */\n#define R_PARISC_PLTOFF14DR\t116\t/* PLT-rel. address, right 14 bits.  */\n#define R_PARISC_PLTOFF16F\t117\t/* 16 bits LT-rel. address.  */\n#define R_PARISC_PLTOFF16WF\t118\t/* 16 bits PLT-rel. address.  */\n#define R_PARISC_PLTOFF16DF\t119\t/* 16 bits PLT-rel. address.  */\n#define R_PARISC_LTOFF_FPTR64\t120\t/* 64 bits LT-rel. function ptr.  */\n#define R_PARISC_LTOFF_FPTR14WR\t123\t/* LT-rel. fct. ptr., right 14 bits. */\n#define R_PARISC_LTOFF_FPTR14DR\t124\t/* LT-rel. fct. ptr., right 14 bits. */\n#define R_PARISC_LTOFF_FPTR16F\t125\t/* 16 bits LT-rel. function ptr.  */\n#define R_PARISC_LTOFF_FPTR16WF\t126\t/* 16 bits LT-rel. function ptr.  */\n#define R_PARISC_LTOFF_FPTR16DF\t127\t/* 16 bits LT-rel. function ptr.  */\n#define R_PARISC_LORESERVE\t128\n#define R_PARISC_COPY\t\t128\t/* Copy relocation.  */\n#define R_PARISC_IPLT\t\t129\t/* Dynamic reloc, imported PLT */\n#define R_PARISC_EPLT\t\t130\t/* Dynamic reloc, exported PLT */\n#define R_PARISC_TPREL32\t153\t/* 32 bits TP-rel. address.  */\n#define R_PARISC_TPREL21L\t154\t/* TP-rel. address, left 21 bits.  */\n#define R_PARISC_TPREL14R\t158\t/* TP-rel. address, right 14 bits.  */\n#define R_PARISC_LTOFF_TP21L\t162\t/* LT-TP-rel. address, left 21 bits. */\n#define R_PARISC_LTOFF_TP14R\t166\t/* LT-TP-rel. address, right 14 bits.*/\n#define R_PARISC_LTOFF_TP14F\t167\t/* 14 bits LT-TP-rel. address.  */\n#define R_PARISC_TPREL64\t216\t/* 64 bits TP-rel. address.  */\n#define R_PARISC_TPREL14WR\t219\t/* TP-rel. address, right 14 bits.  */\n#define R_PARISC_TPREL14DR\t220\t/* TP-rel. address, right 14 bits.  */\n#define R_PARISC_TPREL16F\t221\t/* 16 bits TP-rel. address.  */\n#define R_PARISC_TPREL16WF\t222\t/* 16 bits TP-rel. address.  */\n#define R_PARISC_TPREL16DF\t223\t/* 16 bits TP-rel. address.  */\n#define R_PARISC_LTOFF_TP64\t224\t/* 64 bits LT-TP-rel. address.  */\n#define R_PARISC_LTOFF_TP14WR\t227\t/* LT-TP-rel. address, right 14 bits.*/\n#define R_PARISC_LTOFF_TP14DR\t228\t/* LT-TP-rel. address, right 14 bits.*/\n#define R_PARISC_LTOFF_TP16F\t229\t/* 16 bits LT-TP-rel. address.  */\n#define R_PARISC_LTOFF_TP16WF\t230\t/* 16 bits LT-TP-rel. address.  */\n#define R_PARISC_LTOFF_TP16DF\t231\t/* 16 bits LT-TP-rel. address.  */\n#define R_PARISC_GNU_VTENTRY\t232\n#define R_PARISC_GNU_VTINHERIT\t233\n#define R_PARISC_TLS_GD21L\t234\t/* GD 21-bit left.  */\n#define R_PARISC_TLS_GD14R\t235\t/* GD 14-bit right.  */\n#define R_PARISC_TLS_GDCALL\t236\t/* GD call to __t_g_a.  */\n#define R_PARISC_TLS_LDM21L\t237\t/* LD module 21-bit left.  */\n#define R_PARISC_TLS_LDM14R\t238\t/* LD module 14-bit right.  */\n#define R_PARISC_TLS_LDMCALL\t239\t/* LD module call to __t_g_a.  */\n#define R_PARISC_TLS_LDO21L\t240\t/* LD offset 21-bit left.  */\n#define R_PARISC_TLS_LDO14R\t241\t/* LD offset 14-bit right.  */\n#define R_PARISC_TLS_DTPMOD32\t242\t/* DTP module 32-bit.  */\n#define R_PARISC_TLS_DTPMOD64\t243\t/* DTP module 64-bit.  */\n#define R_PARISC_TLS_DTPOFF32\t244\t/* DTP offset 32-bit.  */\n#define R_PARISC_TLS_DTPOFF64\t245\t/* DTP offset 32-bit.  */\n#define R_PARISC_TLS_LE21L\tR_PARISC_TPREL21L\n#define R_PARISC_TLS_LE14R\tR_PARISC_TPREL14R\n#define R_PARISC_TLS_IE21L\tR_PARISC_LTOFF_TP21L\n#define R_PARISC_TLS_IE14R\tR_PARISC_LTOFF_TP14R\n#define R_PARISC_TLS_TPREL32\tR_PARISC_TPREL32\n#define R_PARISC_TLS_TPREL64\tR_PARISC_TPREL64\n#define R_PARISC_HIRESERVE\t255\n\n/* Legal values for p_type field of Elf32_Phdr/Elf64_Phdr.  */\n\n#define PT_HP_TLS\t\t(PT_LOOS + 0x0)\n#define PT_HP_CORE_NONE\t\t(PT_LOOS + 0x1)\n#define PT_HP_CORE_VERSION\t(PT_LOOS + 0x2)\n#define PT_HP_CORE_KERNEL\t(PT_LOOS + 0x3)\n#define PT_HP_CORE_COMM\t\t(PT_LOOS + 0x4)\n#define PT_HP_CORE_PROC\t\t(PT_LOOS + 0x5)\n#define PT_HP_CORE_LOADABLE\t(PT_LOOS + 0x6)\n#define PT_HP_CORE_STACK\t(PT_LOOS + 0x7)\n#define PT_HP_CORE_SHM\t\t(PT_LOOS + 0x8)\n#define PT_HP_CORE_MMF\t\t(PT_LOOS + 0x9)\n#define PT_HP_PARALLEL\t\t(PT_LOOS + 0x10)\n#define PT_HP_FASTBIND\t\t(PT_LOOS + 0x11)\n#define PT_HP_OPT_ANNOT\t\t(PT_LOOS + 0x12)\n#define PT_HP_HSL_ANNOT\t\t(PT_LOOS + 0x13)\n#define PT_HP_STACK\t\t(PT_LOOS + 0x14)\n\n#define PT_PARISC_ARCHEXT\t0x70000000\n#define PT_PARISC_UNWIND\t0x70000001\n\n/* Legal values for p_flags field of Elf32_Phdr/Elf64_Phdr.  */\n\n#define PF_PARISC_SBP\t\t0x08000000\n\n#define PF_HP_PAGE_SIZE\t\t0x00100000\n#define PF_HP_FAR_SHARED\t0x00200000\n#define PF_HP_NEAR_SHARED\t0x00400000\n#define PF_HP_CODE\t\t0x01000000\n#define PF_HP_MODIFY\t\t0x02000000\n#define PF_HP_LAZYSWAP\t\t0x04000000\n#define PF_HP_SBP\t\t0x08000000\n\n\n/* Alpha specific definitions.  */\n\n/* Legal values for e_flags field of Elf64_Ehdr.  */\n\n#define EF_ALPHA_32BIT\t\t1\t/* All addresses must be < 2GB.  */\n#define EF_ALPHA_CANRELAX\t2\t/* Relocations for relaxing exist.  */\n\n/* Legal values for sh_type field of Elf64_Shdr.  */\n\n/* These two are primerily concerned with ECOFF debugging info.  */\n#define SHT_ALPHA_DEBUG\t\t0x70000001\n#define SHT_ALPHA_REGINFO\t0x70000002\n\n/* Legal values for sh_flags field of Elf64_Shdr.  */\n\n#define SHF_ALPHA_GPREL\t\t0x10000000\n\n/* Legal values for st_other field of Elf64_Sym.  */\n#define STO_ALPHA_NOPV\t\t0x80\t/* No PV required.  */\n#define STO_ALPHA_STD_GPLOAD\t0x88\t/* PV only used for initial ldgp.  */\n\n/* Alpha relocs.  */\n\n#define R_ALPHA_NONE\t\t0\t/* No reloc */\n#define R_ALPHA_REFLONG\t\t1\t/* Direct 32 bit */\n#define R_ALPHA_REFQUAD\t\t2\t/* Direct 64 bit */\n#define R_ALPHA_GPREL32\t\t3\t/* GP relative 32 bit */\n#define R_ALPHA_LITERAL\t\t4\t/* GP relative 16 bit w/optimization */\n#define R_ALPHA_LITUSE\t\t5\t/* Optimization hint for LITERAL */\n#define R_ALPHA_GPDISP\t\t6\t/* Add displacement to GP */\n#define R_ALPHA_BRADDR\t\t7\t/* PC+4 relative 23 bit shifted */\n#define R_ALPHA_HINT\t\t8\t/* PC+4 relative 16 bit shifted */\n#define R_ALPHA_SREL16\t\t9\t/* PC relative 16 bit */\n#define R_ALPHA_SREL32\t\t10\t/* PC relative 32 bit */\n#define R_ALPHA_SREL64\t\t11\t/* PC relative 64 bit */\n#define R_ALPHA_GPRELHIGH\t17\t/* GP relative 32 bit, high 16 bits */\n#define R_ALPHA_GPRELLOW\t18\t/* GP relative 32 bit, low 16 bits */\n#define R_ALPHA_GPREL16\t\t19\t/* GP relative 16 bit */\n#define R_ALPHA_COPY\t\t24\t/* Copy symbol at runtime */\n#define R_ALPHA_GLOB_DAT\t25\t/* Create GOT entry */\n#define R_ALPHA_JMP_SLOT\t26\t/* Create PLT entry */\n#define R_ALPHA_RELATIVE\t27\t/* Adjust by program base */\n#define R_ALPHA_TLS_GD_HI\t28\n#define R_ALPHA_TLSGD\t\t29\n#define R_ALPHA_TLS_LDM\t\t30\n#define R_ALPHA_DTPMOD64\t31\n#define R_ALPHA_GOTDTPREL\t32\n#define R_ALPHA_DTPREL64\t33\n#define R_ALPHA_DTPRELHI\t34\n#define R_ALPHA_DTPRELLO\t35\n#define R_ALPHA_DTPREL16\t36\n#define R_ALPHA_GOTTPREL\t37\n#define R_ALPHA_TPREL64\t\t38\n#define R_ALPHA_TPRELHI\t\t39\n#define R_ALPHA_TPRELLO\t\t40\n#define R_ALPHA_TPREL16\t\t41\n/* Keep this the last entry.  */\n#define R_ALPHA_NUM\t\t46\n\n/* Magic values of the LITUSE relocation addend.  */\n#define LITUSE_ALPHA_ADDR\t0\n#define LITUSE_ALPHA_BASE\t1\n#define LITUSE_ALPHA_BYTOFF\t2\n#define LITUSE_ALPHA_JSR\t3\n#define LITUSE_ALPHA_TLS_GD\t4\n#define LITUSE_ALPHA_TLS_LDM\t5\n\n/* Legal values for d_tag of Elf64_Dyn.  */\n#define DT_ALPHA_PLTRO\t\t(DT_LOPROC + 0)\n#define DT_ALPHA_NUM\t\t1\n\n/* PowerPC specific declarations */\n\n/* Values for Elf32/64_Ehdr.e_flags.  */\n#define EF_PPC_EMB\t\t0x80000000\t/* PowerPC embedded flag */\n\n/* Cygnus local bits below */\n#define EF_PPC_RELOCATABLE\t0x00010000\t/* PowerPC -mrelocatable flag*/\n#define EF_PPC_RELOCATABLE_LIB\t0x00008000\t/* PowerPC -mrelocatable-lib\n\t\t\t\t\t\t   flag */\n\n/* PowerPC relocations defined by the ABIs */\n#define R_PPC_NONE\t\t0\n#define R_PPC_ADDR32\t\t1\t/* 32bit absolute address */\n#define R_PPC_ADDR24\t\t2\t/* 26bit address, 2 bits ignored.  */\n#define R_PPC_ADDR16\t\t3\t/* 16bit absolute address */\n#define R_PPC_ADDR16_LO\t\t4\t/* lower 16bit of absolute address */\n#define R_PPC_ADDR16_HI\t\t5\t/* high 16bit of absolute address */\n#define R_PPC_ADDR16_HA\t\t6\t/* adjusted high 16bit */\n#define R_PPC_ADDR14\t\t7\t/* 16bit address, 2 bits ignored */\n#define R_PPC_ADDR14_BRTAKEN\t8\n#define R_PPC_ADDR14_BRNTAKEN\t9\n#define R_PPC_REL24\t\t10\t/* PC relative 26 bit */\n#define R_PPC_REL14\t\t11\t/* PC relative 16 bit */\n#define R_PPC_REL14_BRTAKEN\t12\n#define R_PPC_REL14_BRNTAKEN\t13\n#define R_PPC_GOT16\t\t14\n#define R_PPC_GOT16_LO\t\t15\n#define R_PPC_GOT16_HI\t\t16\n#define R_PPC_GOT16_HA\t\t17\n#define R_PPC_PLTREL24\t\t18\n#define R_PPC_COPY\t\t19\n#define R_PPC_GLOB_DAT\t\t20\n#define R_PPC_JMP_SLOT\t\t21\n#define R_PPC_RELATIVE\t\t22\n#define R_PPC_LOCAL24PC\t\t23\n#define R_PPC_UADDR32\t\t24\n#define R_PPC_UADDR16\t\t25\n#define R_PPC_REL32\t\t26\n#define R_PPC_PLT32\t\t27\n#define R_PPC_PLTREL32\t\t28\n#define R_PPC_PLT16_LO\t\t29\n#define R_PPC_PLT16_HI\t\t30\n#define R_PPC_PLT16_HA\t\t31\n#define R_PPC_SDAREL16\t\t32\n#define R_PPC_SECTOFF\t\t33\n#define R_PPC_SECTOFF_LO\t34\n#define R_PPC_SECTOFF_HI\t35\n#define R_PPC_SECTOFF_HA\t36\n\n/* PowerPC relocations defined for the TLS access ABI.  */\n#define R_PPC_TLS\t\t67 /* none\t(sym+add)@tls */\n#define R_PPC_DTPMOD32\t\t68 /* word32\t(sym+add)@dtpmod */\n#define R_PPC_TPREL16\t\t69 /* half16*\t(sym+add)@tprel */\n#define R_PPC_TPREL16_LO\t70 /* half16\t(sym+add)@tprel@l */\n#define R_PPC_TPREL16_HI\t71 /* half16\t(sym+add)@tprel@h */\n#define R_PPC_TPREL16_HA\t72 /* half16\t(sym+add)@tprel@ha */\n#define R_PPC_TPREL32\t\t73 /* word32\t(sym+add)@tprel */\n#define R_PPC_DTPREL16\t\t74 /* half16*\t(sym+add)@dtprel */\n#define R_PPC_DTPREL16_LO\t75 /* half16\t(sym+add)@dtprel@l */\n#define R_PPC_DTPREL16_HI\t76 /* half16\t(sym+add)@dtprel@h */\n#define R_PPC_DTPREL16_HA\t77 /* half16\t(sym+add)@dtprel@ha */\n#define R_PPC_DTPREL32\t\t78 /* word32\t(sym+add)@dtprel */\n#define R_PPC_GOT_TLSGD16\t79 /* half16*\t(sym+add)@got@tlsgd */\n#define R_PPC_GOT_TLSGD16_LO\t80 /* half16\t(sym+add)@got@tlsgd@l */\n#define R_PPC_GOT_TLSGD16_HI\t81 /* half16\t(sym+add)@got@tlsgd@h */\n#define R_PPC_GOT_TLSGD16_HA\t82 /* half16\t(sym+add)@got@tlsgd@ha */\n#define R_PPC_GOT_TLSLD16\t83 /* half16*\t(sym+add)@got@tlsld */\n#define R_PPC_GOT_TLSLD16_LO\t84 /* half16\t(sym+add)@got@tlsld@l */\n#define R_PPC_GOT_TLSLD16_HI\t85 /* half16\t(sym+add)@got@tlsld@h */\n#define R_PPC_GOT_TLSLD16_HA\t86 /* half16\t(sym+add)@got@tlsld@ha */\n#define R_PPC_GOT_TPREL16\t87 /* half16*\t(sym+add)@got@tprel */\n#define R_PPC_GOT_TPREL16_LO\t88 /* half16\t(sym+add)@got@tprel@l */\n#define R_PPC_GOT_TPREL16_HI\t89 /* half16\t(sym+add)@got@tprel@h */\n#define R_PPC_GOT_TPREL16_HA\t90 /* half16\t(sym+add)@got@tprel@ha */\n#define R_PPC_GOT_DTPREL16\t91 /* half16*\t(sym+add)@got@dtprel */\n#define R_PPC_GOT_DTPREL16_LO\t92 /* half16*\t(sym+add)@got@dtprel@l */\n#define R_PPC_GOT_DTPREL16_HI\t93 /* half16*\t(sym+add)@got@dtprel@h */\n#define R_PPC_GOT_DTPREL16_HA\t94 /* half16*\t(sym+add)@got@dtprel@ha */\n\n/* The remaining relocs are from the Embedded ELF ABI, and are not\n   in the SVR4 ELF ABI.  */\n#define R_PPC_EMB_NADDR32\t101\n#define R_PPC_EMB_NADDR16\t102\n#define R_PPC_EMB_NADDR16_LO\t103\n#define R_PPC_EMB_NADDR16_HI\t104\n#define R_PPC_EMB_NADDR16_HA\t105\n#define R_PPC_EMB_SDAI16\t106\n#define R_PPC_EMB_SDA2I16\t107\n#define R_PPC_EMB_SDA2REL\t108\n#define R_PPC_EMB_SDA21\t\t109\t/* 16 bit offset in SDA */\n#define R_PPC_EMB_MRKREF\t110\n#define R_PPC_EMB_RELSEC16\t111\n#define R_PPC_EMB_RELST_LO\t112\n#define R_PPC_EMB_RELST_HI\t113\n#define R_PPC_EMB_RELST_HA\t114\n#define R_PPC_EMB_BIT_FLD\t115\n#define R_PPC_EMB_RELSDA\t116\t/* 16 bit relative offset in SDA */\n\n/* Diab tool relocations.  */\n#define R_PPC_DIAB_SDA21_LO\t180\t/* like EMB_SDA21, but lower 16 bit */\n#define R_PPC_DIAB_SDA21_HI\t181\t/* like EMB_SDA21, but high 16 bit */\n#define R_PPC_DIAB_SDA21_HA\t182\t/* like EMB_SDA21, adjusted high 16 */\n#define R_PPC_DIAB_RELSDA_LO\t183\t/* like EMB_RELSDA, but lower 16 bit */\n#define R_PPC_DIAB_RELSDA_HI\t184\t/* like EMB_RELSDA, but high 16 bit */\n#define R_PPC_DIAB_RELSDA_HA\t185\t/* like EMB_RELSDA, adjusted high 16 */\n\n/* GNU extension to support local ifunc.  */\n#define R_PPC_IRELATIVE\t\t248\n\n/* GNU relocs used in PIC code sequences.  */\n#define R_PPC_REL16\t\t249\t/* half16   (sym+add-.) */\n#define R_PPC_REL16_LO\t\t250\t/* half16   (sym+add-.)@l */\n#define R_PPC_REL16_HI\t\t251\t/* half16   (sym+add-.)@h */\n#define R_PPC_REL16_HA\t\t252\t/* half16   (sym+add-.)@ha */\n\n/* This is a phony reloc to handle any old fashioned TOC16 references\n   that may still be in object files.  */\n#define R_PPC_TOC16\t\t255\n\n/* PowerPC specific values for the Dyn d_tag field.  */\n#define DT_PPC_GOT\t\t(DT_LOPROC + 0)\n#define DT_PPC_NUM\t\t1\n\n/* PowerPC64 relocations defined by the ABIs */\n#define R_PPC64_NONE\t\tR_PPC_NONE\n#define R_PPC64_ADDR32\t\tR_PPC_ADDR32 /* 32bit absolute address */\n#define R_PPC64_ADDR24\t\tR_PPC_ADDR24 /* 26bit address, word aligned */\n#define R_PPC64_ADDR16\t\tR_PPC_ADDR16 /* 16bit absolute address */\n#define R_PPC64_ADDR16_LO\tR_PPC_ADDR16_LO\t/* lower 16bits of address */\n#define R_PPC64_ADDR16_HI\tR_PPC_ADDR16_HI\t/* high 16bits of address. */\n#define R_PPC64_ADDR16_HA\tR_PPC_ADDR16_HA /* adjusted high 16bits.  */\n#define R_PPC64_ADDR14\t\tR_PPC_ADDR14 /* 16bit address, word aligned */\n#define R_PPC64_ADDR14_BRTAKEN\tR_PPC_ADDR14_BRTAKEN\n#define R_PPC64_ADDR14_BRNTAKEN\tR_PPC_ADDR14_BRNTAKEN\n#define R_PPC64_REL24\t\tR_PPC_REL24 /* PC-rel. 26 bit, word aligned */\n#define R_PPC64_REL14\t\tR_PPC_REL14 /* PC relative 16 bit */\n#define R_PPC64_REL14_BRTAKEN\tR_PPC_REL14_BRTAKEN\n#define R_PPC64_REL14_BRNTAKEN\tR_PPC_REL14_BRNTAKEN\n#define R_PPC64_GOT16\t\tR_PPC_GOT16\n#define R_PPC64_GOT16_LO\tR_PPC_GOT16_LO\n#define R_PPC64_GOT16_HI\tR_PPC_GOT16_HI\n#define R_PPC64_GOT16_HA\tR_PPC_GOT16_HA\n\n#define R_PPC64_COPY\t\tR_PPC_COPY\n#define R_PPC64_GLOB_DAT\tR_PPC_GLOB_DAT\n#define R_PPC64_JMP_SLOT\tR_PPC_JMP_SLOT\n#define R_PPC64_RELATIVE\tR_PPC_RELATIVE\n\n#define R_PPC64_UADDR32\t\tR_PPC_UADDR32\n#define R_PPC64_UADDR16\t\tR_PPC_UADDR16\n#define R_PPC64_REL32\t\tR_PPC_REL32\n#define R_PPC64_PLT32\t\tR_PPC_PLT32\n#define R_PPC64_PLTREL32\tR_PPC_PLTREL32\n#define R_PPC64_PLT16_LO\tR_PPC_PLT16_LO\n#define R_PPC64_PLT16_HI\tR_PPC_PLT16_HI\n#define R_PPC64_PLT16_HA\tR_PPC_PLT16_HA\n\n#define R_PPC64_SECTOFF\t\tR_PPC_SECTOFF\n#define R_PPC64_SECTOFF_LO\tR_PPC_SECTOFF_LO\n#define R_PPC64_SECTOFF_HI\tR_PPC_SECTOFF_HI\n#define R_PPC64_SECTOFF_HA\tR_PPC_SECTOFF_HA\n#define R_PPC64_ADDR30\t\t37 /* word30 (S + A - P) >> 2 */\n#define R_PPC64_ADDR64\t\t38 /* doubleword64 S + A */\n#define R_PPC64_ADDR16_HIGHER\t39 /* half16 #higher(S + A) */\n#define R_PPC64_ADDR16_HIGHERA\t40 /* half16 #highera(S + A) */\n#define R_PPC64_ADDR16_HIGHEST\t41 /* half16 #highest(S + A) */\n#define R_PPC64_ADDR16_HIGHESTA\t42 /* half16 #highesta(S + A) */\n#define R_PPC64_UADDR64\t\t43 /* doubleword64 S + A */\n#define R_PPC64_REL64\t\t44 /* doubleword64 S + A - P */\n#define R_PPC64_PLT64\t\t45 /* doubleword64 L + A */\n#define R_PPC64_PLTREL64\t46 /* doubleword64 L + A - P */\n#define R_PPC64_TOC16\t\t47 /* half16* S + A - .TOC */\n#define R_PPC64_TOC16_LO\t48 /* half16 #lo(S + A - .TOC.) */\n#define R_PPC64_TOC16_HI\t49 /* half16 #hi(S + A - .TOC.) */\n#define R_PPC64_TOC16_HA\t50 /* half16 #ha(S + A - .TOC.) */\n#define R_PPC64_TOC\t\t51 /* doubleword64 .TOC */\n#define R_PPC64_PLTGOT16\t52 /* half16* M + A */\n#define R_PPC64_PLTGOT16_LO\t53 /* half16 #lo(M + A) */\n#define R_PPC64_PLTGOT16_HI\t54 /* half16 #hi(M + A) */\n#define R_PPC64_PLTGOT16_HA\t55 /* half16 #ha(M + A) */\n\n#define R_PPC64_ADDR16_DS\t56 /* half16ds* (S + A) >> 2 */\n#define R_PPC64_ADDR16_LO_DS\t57 /* half16ds  #lo(S + A) >> 2 */\n#define R_PPC64_GOT16_DS\t58 /* half16ds* (G + A) >> 2 */\n#define R_PPC64_GOT16_LO_DS\t59 /* half16ds  #lo(G + A) >> 2 */\n#define R_PPC64_PLT16_LO_DS\t60 /* half16ds  #lo(L + A) >> 2 */\n#define R_PPC64_SECTOFF_DS\t61 /* half16ds* (R + A) >> 2 */\n#define R_PPC64_SECTOFF_LO_DS\t62 /* half16ds  #lo(R + A) >> 2 */\n#define R_PPC64_TOC16_DS\t63 /* half16ds* (S + A - .TOC.) >> 2 */\n#define R_PPC64_TOC16_LO_DS\t64 /* half16ds  #lo(S + A - .TOC.) >> 2 */\n#define R_PPC64_PLTGOT16_DS\t65 /* half16ds* (M + A) >> 2 */\n#define R_PPC64_PLTGOT16_LO_DS\t66 /* half16ds  #lo(M + A) >> 2 */\n\n/* PowerPC64 relocations defined for the TLS access ABI.  */\n#define R_PPC64_TLS\t\t67 /* none\t(sym+add)@tls */\n#define R_PPC64_DTPMOD64\t68 /* doubleword64 (sym+add)@dtpmod */\n#define R_PPC64_TPREL16\t\t69 /* half16*\t(sym+add)@tprel */\n#define R_PPC64_TPREL16_LO\t70 /* half16\t(sym+add)@tprel@l */\n#define R_PPC64_TPREL16_HI\t71 /* half16\t(sym+add)@tprel@h */\n#define R_PPC64_TPREL16_HA\t72 /* half16\t(sym+add)@tprel@ha */\n#define R_PPC64_TPREL64\t\t73 /* doubleword64 (sym+add)@tprel */\n#define R_PPC64_DTPREL16\t74 /* half16*\t(sym+add)@dtprel */\n#define R_PPC64_DTPREL16_LO\t75 /* half16\t(sym+add)@dtprel@l */\n#define R_PPC64_DTPREL16_HI\t76 /* half16\t(sym+add)@dtprel@h */\n#define R_PPC64_DTPREL16_HA\t77 /* half16\t(sym+add)@dtprel@ha */\n#define R_PPC64_DTPREL64\t78 /* doubleword64 (sym+add)@dtprel */\n#define R_PPC64_GOT_TLSGD16\t79 /* half16*\t(sym+add)@got@tlsgd */\n#define R_PPC64_GOT_TLSGD16_LO\t80 /* half16\t(sym+add)@got@tlsgd@l */\n#define R_PPC64_GOT_TLSGD16_HI\t81 /* half16\t(sym+add)@got@tlsgd@h */\n#define R_PPC64_GOT_TLSGD16_HA\t82 /* half16\t(sym+add)@got@tlsgd@ha */\n#define R_PPC64_GOT_TLSLD16\t83 /* half16*\t(sym+add)@got@tlsld */\n#define R_PPC64_GOT_TLSLD16_LO\t84 /* half16\t(sym+add)@got@tlsld@l */\n#define R_PPC64_GOT_TLSLD16_HI\t85 /* half16\t(sym+add)@got@tlsld@h */\n#define R_PPC64_GOT_TLSLD16_HA\t86 /* half16\t(sym+add)@got@tlsld@ha */\n#define R_PPC64_GOT_TPREL16_DS\t87 /* half16ds*\t(sym+add)@got@tprel */\n#define R_PPC64_GOT_TPREL16_LO_DS 88 /* half16ds (sym+add)@got@tprel@l */\n#define R_PPC64_GOT_TPREL16_HI\t89 /* half16\t(sym+add)@got@tprel@h */\n#define R_PPC64_GOT_TPREL16_HA\t90 /* half16\t(sym+add)@got@tprel@ha */\n#define R_PPC64_GOT_DTPREL16_DS\t91 /* half16ds*\t(sym+add)@got@dtprel */\n#define R_PPC64_GOT_DTPREL16_LO_DS 92 /* half16ds (sym+add)@got@dtprel@l */\n#define R_PPC64_GOT_DTPREL16_HI\t93 /* half16\t(sym+add)@got@dtprel@h */\n#define R_PPC64_GOT_DTPREL16_HA\t94 /* half16\t(sym+add)@got@dtprel@ha */\n#define R_PPC64_TPREL16_DS\t95 /* half16ds*\t(sym+add)@tprel */\n#define R_PPC64_TPREL16_LO_DS\t96 /* half16ds\t(sym+add)@tprel@l */\n#define R_PPC64_TPREL16_HIGHER\t97 /* half16\t(sym+add)@tprel@higher */\n#define R_PPC64_TPREL16_HIGHERA\t98 /* half16\t(sym+add)@tprel@highera */\n#define R_PPC64_TPREL16_HIGHEST\t99 /* half16\t(sym+add)@tprel@highest */\n#define R_PPC64_TPREL16_HIGHESTA 100 /* half16\t(sym+add)@tprel@highesta */\n#define R_PPC64_DTPREL16_DS\t101 /* half16ds* (sym+add)@dtprel */\n#define R_PPC64_DTPREL16_LO_DS\t102 /* half16ds\t(sym+add)@dtprel@l */\n#define R_PPC64_DTPREL16_HIGHER\t103 /* half16\t(sym+add)@dtprel@higher */\n#define R_PPC64_DTPREL16_HIGHERA 104 /* half16\t(sym+add)@dtprel@highera */\n#define R_PPC64_DTPREL16_HIGHEST 105 /* half16\t(sym+add)@dtprel@highest */\n#define R_PPC64_DTPREL16_HIGHESTA 106 /* half16\t(sym+add)@dtprel@highesta */\n\n/* GNU extension to support local ifunc.  */\n#define R_PPC64_JMP_IREL\t247\n#define R_PPC64_IRELATIVE\t248\n#define R_PPC64_REL16\t\t249\t/* half16   (sym+add-.) */\n#define R_PPC64_REL16_LO\t250\t/* half16   (sym+add-.)@l */\n#define R_PPC64_REL16_HI\t251\t/* half16   (sym+add-.)@h */\n#define R_PPC64_REL16_HA\t252\t/* half16   (sym+add-.)@ha */\n\n/* PowerPC64 specific values for the Dyn d_tag field.  */\n#define DT_PPC64_GLINK  (DT_LOPROC + 0)\n#define DT_PPC64_OPD\t(DT_LOPROC + 1)\n#define DT_PPC64_OPDSZ\t(DT_LOPROC + 2)\n#define DT_PPC64_NUM    3\n\n\n/* ARM specific declarations */\n\n/* Processor specific flags for the ELF header e_flags field.  */\n#define EF_ARM_RELEXEC\t\t0x01\n#define EF_ARM_HASENTRY\t\t0x02\n#define EF_ARM_INTERWORK\t0x04\n#define EF_ARM_APCS_26\t\t0x08\n#define EF_ARM_APCS_FLOAT\t0x10\n#define EF_ARM_PIC\t\t0x20\n#define EF_ARM_ALIGN8\t\t0x40 /* 8-bit structure alignment is in use */\n#define EF_ARM_NEW_ABI\t\t0x80\n#define EF_ARM_OLD_ABI\t\t0x100\n#define EF_ARM_SOFT_FLOAT\t0x200\n#define EF_ARM_VFP_FLOAT\t0x400\n#define EF_ARM_MAVERICK_FLOAT\t0x800\n\n\n/* Other constants defined in the ARM ELF spec. version B-01.  */\n/* NB. These conflict with values defined above.  */\n#define EF_ARM_SYMSARESORTED\t0x04\n#define EF_ARM_DYNSYMSUSESEGIDX\t0x08\n#define EF_ARM_MAPSYMSFIRST\t0x10\n#define EF_ARM_EABIMASK\t\t0XFF000000\n\n/* Constants defined in AAELF.  */\n#define EF_ARM_BE8\t    0x00800000\n#define EF_ARM_LE8\t    0x00400000\n\n#define EF_ARM_EABI_VERSION(flags)\t((flags) & EF_ARM_EABIMASK)\n#define EF_ARM_EABI_UNKNOWN\t0x00000000\n#define EF_ARM_EABI_VER1\t0x01000000\n#define EF_ARM_EABI_VER2\t0x02000000\n#define EF_ARM_EABI_VER3\t0x03000000\n#define EF_ARM_EABI_VER4\t0x04000000\n#define EF_ARM_EABI_VER5\t0x05000000\n\n/* Additional symbol types for Thumb.  */\n#define STT_ARM_TFUNC\t\tSTT_LOPROC /* A Thumb function.  */\n#define STT_ARM_16BIT\t\tSTT_HIPROC /* A Thumb label.  */\n\n/* ARM-specific values for sh_flags */\n#define SHF_ARM_ENTRYSECT\t0x10000000 /* Section contains an entry point */\n#define SHF_ARM_COMDEF\t\t0x80000000 /* Section may be multiply defined\n\t\t\t\t\t      in the input to a link step.  */\n\n/* ARM-specific program header flags */\n#define PF_ARM_SB\t\t0x10000000 /* Segment contains the location\n\t\t\t\t\t      addressed by the static base. */\n#define PF_ARM_PI\t\t0x20000000 /* Position-independent segment.  */\n#define PF_ARM_ABS\t\t0x40000000 /* Absolute segment.  */\n\n/* Processor specific values for the Phdr p_type field.  */\n#define PT_ARM_EXIDX\t\t(PT_LOPROC + 1)\t/* ARM unwind segment.  */\n\n/* Processor specific values for the Shdr sh_type field.  */\n#define SHT_ARM_EXIDX\t\t(SHT_LOPROC + 1) /* ARM unwind section.  */\n#define SHT_ARM_PREEMPTMAP\t(SHT_LOPROC + 2) /* Preemption details.  */\n#define SHT_ARM_ATTRIBUTES\t(SHT_LOPROC + 3) /* ARM attributes section.  */\n\n\n/* ARM relocs.  */\n\n#define R_ARM_NONE\t\t0\t/* No reloc */\n#define R_ARM_PC24\t\t1\t/* PC relative 26 bit branch */\n#define R_ARM_ABS32\t\t2\t/* Direct 32 bit  */\n#define R_ARM_REL32\t\t3\t/* PC relative 32 bit */\n#define R_ARM_PC13\t\t4\n#define R_ARM_ABS16\t\t5\t/* Direct 16 bit */\n#define R_ARM_ABS12\t\t6\t/* Direct 12 bit */\n#define R_ARM_THM_ABS5\t\t7\n#define R_ARM_ABS8\t\t8\t/* Direct 8 bit */\n#define R_ARM_SBREL32\t\t9\n#define R_ARM_THM_PC22\t\t10\n#define R_ARM_THM_PC8\t\t11\n#define R_ARM_AMP_VCALL9\t12\n#define R_ARM_SWI24\t\t13\t/* Obsolete static relocation.  */\n#define R_ARM_TLS_DESC\t\t13      /* Dynamic relocation.  */\n#define R_ARM_THM_SWI8\t\t14\n#define R_ARM_XPC25\t\t15\n#define R_ARM_THM_XPC22\t\t16\n#define R_ARM_TLS_DTPMOD32\t17\t/* ID of module containing symbol */\n#define R_ARM_TLS_DTPOFF32\t18\t/* Offset in TLS block */\n#define R_ARM_TLS_TPOFF32\t19\t/* Offset in static TLS block */\n#define R_ARM_COPY\t\t20\t/* Copy symbol at runtime */\n#define R_ARM_GLOB_DAT\t\t21\t/* Create GOT entry */\n#define R_ARM_JUMP_SLOT\t\t22\t/* Create PLT entry */\n#define R_ARM_RELATIVE\t\t23\t/* Adjust by program base */\n#define R_ARM_GOTOFF\t\t24\t/* 32 bit offset to GOT */\n#define R_ARM_GOTPC\t\t25\t/* 32 bit PC relative offset to GOT */\n#define R_ARM_GOT32\t\t26\t/* 32 bit GOT entry */\n#define R_ARM_PLT32\t\t27\t/* 32 bit PLT address */\n#define R_ARM_ALU_PCREL_7_0\t32\n#define R_ARM_ALU_PCREL_15_8\t33\n#define R_ARM_ALU_PCREL_23_15\t34\n#define R_ARM_LDR_SBREL_11_0\t35\n#define R_ARM_ALU_SBREL_19_12\t36\n#define R_ARM_ALU_SBREL_27_20\t37\n#define R_ARM_TLS_GOTDESC\t90\n#define R_ARM_TLS_CALL\t\t91\n#define R_ARM_TLS_DESCSEQ\t92\n#define R_ARM_THM_TLS_CALL\t93\n#define R_ARM_GNU_VTENTRY\t100\n#define R_ARM_GNU_VTINHERIT\t101\n#define R_ARM_THM_PC11\t\t102\t/* thumb unconditional branch */\n#define R_ARM_THM_PC9\t\t103\t/* thumb conditional branch */\n#define R_ARM_TLS_GD32\t\t104\t/* PC-rel 32 bit for global dynamic\n\t\t\t\t\t   thread local data */\n#define R_ARM_TLS_LDM32\t\t105\t/* PC-rel 32 bit for local dynamic\n\t\t\t\t\t   thread local data */\n#define R_ARM_TLS_LDO32\t\t106\t/* 32 bit offset relative to TLS\n\t\t\t\t\t   block */\n#define R_ARM_TLS_IE32\t\t107\t/* PC-rel 32 bit for GOT entry of\n\t\t\t\t\t   static TLS block offset */\n#define R_ARM_TLS_LE32\t\t108\t/* 32 bit offset relative to static\n\t\t\t\t\t   TLS block */\n#define\tR_ARM_THM_TLS_DESCSEQ\t129\n#define R_ARM_IRELATIVE\t\t160\n#define R_ARM_RXPC25\t\t249\n#define R_ARM_RSBREL32\t\t250\n#define R_ARM_THM_RPC22\t\t251\n#define R_ARM_RREL32\t\t252\n#define R_ARM_RABS22\t\t253\n#define R_ARM_RPC24\t\t254\n#define R_ARM_RBASE\t\t255\n/* Keep this the last entry.  */\n#define R_ARM_NUM\t\t256\n\n/* IA-64 specific declarations.  */\n\n/* Processor specific flags for the Ehdr e_flags field.  */\n#define EF_IA_64_MASKOS\t\t0x0000000f\t/* os-specific flags */\n#define EF_IA_64_ABI64\t\t0x00000010\t/* 64-bit ABI */\n#define EF_IA_64_ARCH\t\t0xff000000\t/* arch. version mask */\n\n/* Processor specific values for the Phdr p_type field.  */\n#define PT_IA_64_ARCHEXT\t(PT_LOPROC + 0)\t/* arch extension bits */\n#define PT_IA_64_UNWIND\t\t(PT_LOPROC + 1)\t/* ia64 unwind bits */\n#define PT_IA_64_HP_OPT_ANOT\t(PT_LOOS + 0x12)\n#define PT_IA_64_HP_HSL_ANOT\t(PT_LOOS + 0x13)\n#define PT_IA_64_HP_STACK\t(PT_LOOS + 0x14)\n\n/* Processor specific flags for the Phdr p_flags field.  */\n#define PF_IA_64_NORECOV\t0x80000000\t/* spec insns w/o recovery */\n\n/* Processor specific values for the Shdr sh_type field.  */\n#define SHT_IA_64_EXT\t\t(SHT_LOPROC + 0) /* extension bits */\n#define SHT_IA_64_UNWIND\t(SHT_LOPROC + 1) /* unwind bits */\n\n/* Processor specific flags for the Shdr sh_flags field.  */\n#define SHF_IA_64_SHORT\t\t0x10000000\t/* section near gp */\n#define SHF_IA_64_NORECOV\t0x20000000\t/* spec insns w/o recovery */\n\n/* Processor specific values for the Dyn d_tag field.  */\n#define DT_IA_64_PLT_RESERVE\t(DT_LOPROC + 0)\n#define DT_IA_64_NUM\t\t1\n\n/* IA-64 relocations.  */\n#define R_IA64_NONE\t\t0x00\t/* none */\n#define R_IA64_IMM14\t\t0x21\t/* symbol + addend, add imm14 */\n#define R_IA64_IMM22\t\t0x22\t/* symbol + addend, add imm22 */\n#define R_IA64_IMM64\t\t0x23\t/* symbol + addend, mov imm64 */\n#define R_IA64_DIR32MSB\t\t0x24\t/* symbol + addend, data4 MSB */\n#define R_IA64_DIR32LSB\t\t0x25\t/* symbol + addend, data4 LSB */\n#define R_IA64_DIR64MSB\t\t0x26\t/* symbol + addend, data8 MSB */\n#define R_IA64_DIR64LSB\t\t0x27\t/* symbol + addend, data8 LSB */\n#define R_IA64_GPREL22\t\t0x2a\t/* @gprel(sym + add), add imm22 */\n#define R_IA64_GPREL64I\t\t0x2b\t/* @gprel(sym + add), mov imm64 */\n#define R_IA64_GPREL32MSB\t0x2c\t/* @gprel(sym + add), data4 MSB */\n#define R_IA64_GPREL32LSB\t0x2d\t/* @gprel(sym + add), data4 LSB */\n#define R_IA64_GPREL64MSB\t0x2e\t/* @gprel(sym + add), data8 MSB */\n#define R_IA64_GPREL64LSB\t0x2f\t/* @gprel(sym + add), data8 LSB */\n#define R_IA64_LTOFF22\t\t0x32\t/* @ltoff(sym + add), add imm22 */\n#define R_IA64_LTOFF64I\t\t0x33\t/* @ltoff(sym + add), mov imm64 */\n#define R_IA64_PLTOFF22\t\t0x3a\t/* @pltoff(sym + add), add imm22 */\n#define R_IA64_PLTOFF64I\t0x3b\t/* @pltoff(sym + add), mov imm64 */\n#define R_IA64_PLTOFF64MSB\t0x3e\t/* @pltoff(sym + add), data8 MSB */\n#define R_IA64_PLTOFF64LSB\t0x3f\t/* @pltoff(sym + add), data8 LSB */\n#define R_IA64_FPTR64I\t\t0x43\t/* @fptr(sym + add), mov imm64 */\n#define R_IA64_FPTR32MSB\t0x44\t/* @fptr(sym + add), data4 MSB */\n#define R_IA64_FPTR32LSB\t0x45\t/* @fptr(sym + add), data4 LSB */\n#define R_IA64_FPTR64MSB\t0x46\t/* @fptr(sym + add), data8 MSB */\n#define R_IA64_FPTR64LSB\t0x47\t/* @fptr(sym + add), data8 LSB */\n#define R_IA64_PCREL60B\t\t0x48\t/* @pcrel(sym + add), brl */\n#define R_IA64_PCREL21B\t\t0x49\t/* @pcrel(sym + add), ptb, call */\n#define R_IA64_PCREL21M\t\t0x4a\t/* @pcrel(sym + add), chk.s */\n#define R_IA64_PCREL21F\t\t0x4b\t/* @pcrel(sym + add), fchkf */\n#define R_IA64_PCREL32MSB\t0x4c\t/* @pcrel(sym + add), data4 MSB */\n#define R_IA64_PCREL32LSB\t0x4d\t/* @pcrel(sym + add), data4 LSB */\n#define R_IA64_PCREL64MSB\t0x4e\t/* @pcrel(sym + add), data8 MSB */\n#define R_IA64_PCREL64LSB\t0x4f\t/* @pcrel(sym + add), data8 LSB */\n#define R_IA64_LTOFF_FPTR22\t0x52\t/* @ltoff(@fptr(s+a)), imm22 */\n#define R_IA64_LTOFF_FPTR64I\t0x53\t/* @ltoff(@fptr(s+a)), imm64 */\n#define R_IA64_LTOFF_FPTR32MSB\t0x54\t/* @ltoff(@fptr(s+a)), data4 MSB */\n#define R_IA64_LTOFF_FPTR32LSB\t0x55\t/* @ltoff(@fptr(s+a)), data4 LSB */\n#define R_IA64_LTOFF_FPTR64MSB\t0x56\t/* @ltoff(@fptr(s+a)), data8 MSB */\n#define R_IA64_LTOFF_FPTR64LSB\t0x57\t/* @ltoff(@fptr(s+a)), data8 LSB */\n#define R_IA64_SEGREL32MSB\t0x5c\t/* @segrel(sym + add), data4 MSB */\n#define R_IA64_SEGREL32LSB\t0x5d\t/* @segrel(sym + add), data4 LSB */\n#define R_IA64_SEGREL64MSB\t0x5e\t/* @segrel(sym + add), data8 MSB */\n#define R_IA64_SEGREL64LSB\t0x5f\t/* @segrel(sym + add), data8 LSB */\n#define R_IA64_SECREL32MSB\t0x64\t/* @secrel(sym + add), data4 MSB */\n#define R_IA64_SECREL32LSB\t0x65\t/* @secrel(sym + add), data4 LSB */\n#define R_IA64_SECREL64MSB\t0x66\t/* @secrel(sym + add), data8 MSB */\n#define R_IA64_SECREL64LSB\t0x67\t/* @secrel(sym + add), data8 LSB */\n#define R_IA64_REL32MSB\t\t0x6c\t/* data 4 + REL */\n#define R_IA64_REL32LSB\t\t0x6d\t/* data 4 + REL */\n#define R_IA64_REL64MSB\t\t0x6e\t/* data 8 + REL */\n#define R_IA64_REL64LSB\t\t0x6f\t/* data 8 + REL */\n#define R_IA64_LTV32MSB\t\t0x74\t/* symbol + addend, data4 MSB */\n#define R_IA64_LTV32LSB\t\t0x75\t/* symbol + addend, data4 LSB */\n#define R_IA64_LTV64MSB\t\t0x76\t/* symbol + addend, data8 MSB */\n#define R_IA64_LTV64LSB\t\t0x77\t/* symbol + addend, data8 LSB */\n#define R_IA64_PCREL21BI\t0x79\t/* @pcrel(sym + add), 21bit inst */\n#define R_IA64_PCREL22\t\t0x7a\t/* @pcrel(sym + add), 22bit inst */\n#define R_IA64_PCREL64I\t\t0x7b\t/* @pcrel(sym + add), 64bit inst */\n#define R_IA64_IPLTMSB\t\t0x80\t/* dynamic reloc, imported PLT, MSB */\n#define R_IA64_IPLTLSB\t\t0x81\t/* dynamic reloc, imported PLT, LSB */\n#define R_IA64_COPY\t\t0x84\t/* copy relocation */\n#define R_IA64_SUB\t\t0x85\t/* Addend and symbol difference */\n#define R_IA64_LTOFF22X\t\t0x86\t/* LTOFF22, relaxable.  */\n#define R_IA64_LDXMOV\t\t0x87\t/* Use of LTOFF22X.  */\n#define R_IA64_TPREL14\t\t0x91\t/* @tprel(sym + add), imm14 */\n#define R_IA64_TPREL22\t\t0x92\t/* @tprel(sym + add), imm22 */\n#define R_IA64_TPREL64I\t\t0x93\t/* @tprel(sym + add), imm64 */\n#define R_IA64_TPREL64MSB\t0x96\t/* @tprel(sym + add), data8 MSB */\n#define R_IA64_TPREL64LSB\t0x97\t/* @tprel(sym + add), data8 LSB */\n#define R_IA64_LTOFF_TPREL22\t0x9a\t/* @ltoff(@tprel(s+a)), imm2 */\n#define R_IA64_DTPMOD64MSB\t0xa6\t/* @dtpmod(sym + add), data8 MSB */\n#define R_IA64_DTPMOD64LSB\t0xa7\t/* @dtpmod(sym + add), data8 LSB */\n#define R_IA64_LTOFF_DTPMOD22\t0xaa\t/* @ltoff(@dtpmod(sym + add)), imm22 */\n#define R_IA64_DTPREL14\t\t0xb1\t/* @dtprel(sym + add), imm14 */\n#define R_IA64_DTPREL22\t\t0xb2\t/* @dtprel(sym + add), imm22 */\n#define R_IA64_DTPREL64I\t0xb3\t/* @dtprel(sym + add), imm64 */\n#define R_IA64_DTPREL32MSB\t0xb4\t/* @dtprel(sym + add), data4 MSB */\n#define R_IA64_DTPREL32LSB\t0xb5\t/* @dtprel(sym + add), data4 LSB */\n#define R_IA64_DTPREL64MSB\t0xb6\t/* @dtprel(sym + add), data8 MSB */\n#define R_IA64_DTPREL64LSB\t0xb7\t/* @dtprel(sym + add), data8 LSB */\n#define R_IA64_LTOFF_DTPREL22\t0xba\t/* @ltoff(@dtprel(s+a)), imm22 */\n\n/* SH specific declarations */\n\n/* Processor specific flags for the ELF header e_flags field.  */\n#define EF_SH_MACH_MASK\t\t0x1f\n#define EF_SH_UNKNOWN\t\t0x0\n#define EF_SH1\t\t\t0x1\n#define EF_SH2\t\t\t0x2\n#define EF_SH3\t\t\t0x3\n#define EF_SH_DSP\t\t0x4\n#define EF_SH3_DSP\t\t0x5\n#define EF_SH4AL_DSP\t\t0x6\n#define EF_SH3E\t\t\t0x8\n#define EF_SH4\t\t\t0x9\n#define EF_SH2E\t\t\t0xb\n#define EF_SH4A\t\t\t0xc\n#define EF_SH2A\t\t\t0xd\n#define EF_SH4_NOFPU\t\t0x10\n#define EF_SH4A_NOFPU\t\t0x11\n#define EF_SH4_NOMMU_NOFPU\t0x12\n#define EF_SH2A_NOFPU\t\t0x13\n#define EF_SH3_NOMMU\t\t0x14\n#define EF_SH2A_SH4_NOFPU\t0x15\n#define EF_SH2A_SH3_NOFPU\t0x16\n#define EF_SH2A_SH4\t\t0x17\n#define EF_SH2A_SH3E\t\t0x18\n\n/* SH relocs.  */\n#define\tR_SH_NONE\t\t0\n#define\tR_SH_DIR32\t\t1\n#define\tR_SH_REL32\t\t2\n#define\tR_SH_DIR8WPN\t\t3\n#define\tR_SH_IND12W\t\t4\n#define\tR_SH_DIR8WPL\t\t5\n#define\tR_SH_DIR8WPZ\t\t6\n#define\tR_SH_DIR8BP\t\t7\n#define\tR_SH_DIR8W\t\t8\n#define\tR_SH_DIR8L\t\t9\n#define\tR_SH_SWITCH16\t\t25\n#define\tR_SH_SWITCH32\t\t26\n#define\tR_SH_USES\t\t27\n#define\tR_SH_COUNT\t\t28\n#define\tR_SH_ALIGN\t\t29\n#define\tR_SH_CODE\t\t30\n#define\tR_SH_DATA\t\t31\n#define\tR_SH_LABEL\t\t32\n#define\tR_SH_SWITCH8\t\t33\n#define\tR_SH_GNU_VTINHERIT\t34\n#define\tR_SH_GNU_VTENTRY\t35\n#define\tR_SH_TLS_GD_32\t\t144\n#define\tR_SH_TLS_LD_32\t\t145\n#define\tR_SH_TLS_LDO_32\t\t146\n#define\tR_SH_TLS_IE_32\t\t147\n#define\tR_SH_TLS_LE_32\t\t148\n#define\tR_SH_TLS_DTPMOD32\t149\n#define\tR_SH_TLS_DTPOFF32\t150\n#define\tR_SH_TLS_TPOFF32\t151\n#define\tR_SH_GOT32\t\t160\n#define\tR_SH_PLT32\t\t161\n#define\tR_SH_COPY\t\t162\n#define\tR_SH_GLOB_DAT\t\t163\n#define\tR_SH_JMP_SLOT\t\t164\n#define\tR_SH_RELATIVE\t\t165\n#define\tR_SH_GOTOFF\t\t166\n#define\tR_SH_GOTPC\t\t167\n/* Keep this the last entry.  */\n#define\tR_SH_NUM\t\t256\n\n/* S/390 specific definitions.  */\n\n/* Valid values for the e_flags field.  */\n\n#define EF_S390_HIGH_GPRS    0x00000001  /* High GPRs kernel facility needed.  */\n\n/* Additional s390 relocs */\n\n#define R_390_NONE\t\t0\t/* No reloc.  */\n#define R_390_8\t\t\t1\t/* Direct 8 bit.  */\n#define R_390_12\t\t2\t/* Direct 12 bit.  */\n#define R_390_16\t\t3\t/* Direct 16 bit.  */\n#define R_390_32\t\t4\t/* Direct 32 bit.  */\n#define R_390_PC32\t\t5\t/* PC relative 32 bit.\t*/\n#define R_390_GOT12\t\t6\t/* 12 bit GOT offset.  */\n#define R_390_GOT32\t\t7\t/* 32 bit GOT offset.  */\n#define R_390_PLT32\t\t8\t/* 32 bit PC relative PLT address.  */\n#define R_390_COPY\t\t9\t/* Copy symbol at runtime.  */\n#define R_390_GLOB_DAT\t\t10\t/* Create GOT entry.  */\n#define R_390_JMP_SLOT\t\t11\t/* Create PLT entry.  */\n#define R_390_RELATIVE\t\t12\t/* Adjust by program base.  */\n#define R_390_GOTOFF32\t\t13\t/* 32 bit offset to GOT.\t */\n#define R_390_GOTPC\t\t14\t/* 32 bit PC relative offset to GOT.  */\n#define R_390_GOT16\t\t15\t/* 16 bit GOT offset.  */\n#define R_390_PC16\t\t16\t/* PC relative 16 bit.\t*/\n#define R_390_PC16DBL\t\t17\t/* PC relative 16 bit shifted by 1.  */\n#define R_390_PLT16DBL\t\t18\t/* 16 bit PC rel. PLT shifted by 1.  */\n#define R_390_PC32DBL\t\t19\t/* PC relative 32 bit shifted by 1.  */\n#define R_390_PLT32DBL\t\t20\t/* 32 bit PC rel. PLT shifted by 1.  */\n#define R_390_GOTPCDBL\t\t21\t/* 32 bit PC rel. GOT shifted by 1.  */\n#define R_390_64\t\t22\t/* Direct 64 bit.  */\n#define R_390_PC64\t\t23\t/* PC relative 64 bit.\t*/\n#define R_390_GOT64\t\t24\t/* 64 bit GOT offset.  */\n#define R_390_PLT64\t\t25\t/* 64 bit PC relative PLT address.  */\n#define R_390_GOTENT\t\t26\t/* 32 bit PC rel. to GOT entry >> 1. */\n#define R_390_GOTOFF16\t\t27\t/* 16 bit offset to GOT. */\n#define R_390_GOTOFF64\t\t28\t/* 64 bit offset to GOT. */\n#define R_390_GOTPLT12\t\t29\t/* 12 bit offset to jump slot.\t*/\n#define R_390_GOTPLT16\t\t30\t/* 16 bit offset to jump slot.\t*/\n#define R_390_GOTPLT32\t\t31\t/* 32 bit offset to jump slot.\t*/\n#define R_390_GOTPLT64\t\t32\t/* 64 bit offset to jump slot.\t*/\n#define R_390_GOTPLTENT\t\t33\t/* 32 bit rel. offset to jump slot.  */\n#define R_390_PLTOFF16\t\t34\t/* 16 bit offset from GOT to PLT. */\n#define R_390_PLTOFF32\t\t35\t/* 32 bit offset from GOT to PLT. */\n#define R_390_PLTOFF64\t\t36\t/* 16 bit offset from GOT to PLT. */\n#define R_390_TLS_LOAD\t\t37\t/* Tag for load insn in TLS code.  */\n#define R_390_TLS_GDCALL\t38\t/* Tag for function call in general\n\t\t\t\t\t   dynamic TLS code. */\n#define R_390_TLS_LDCALL\t39\t/* Tag for function call in local\n\t\t\t\t\t   dynamic TLS code. */\n#define R_390_TLS_GD32\t\t40\t/* Direct 32 bit for general dynamic\n\t\t\t\t\t   thread local data.  */\n#define R_390_TLS_GD64\t\t41\t/* Direct 64 bit for general dynamic\n\t\t\t\t\t  thread local data.  */\n#define R_390_TLS_GOTIE12\t42\t/* 12 bit GOT offset for static TLS\n\t\t\t\t\t   block offset.  */\n#define R_390_TLS_GOTIE32\t43\t/* 32 bit GOT offset for static TLS\n\t\t\t\t\t   block offset.  */\n#define R_390_TLS_GOTIE64\t44\t/* 64 bit GOT offset for static TLS\n\t\t\t\t\t   block offset. */\n#define R_390_TLS_LDM32\t\t45\t/* Direct 32 bit for local dynamic\n\t\t\t\t\t   thread local data in LE code.  */\n#define R_390_TLS_LDM64\t\t46\t/* Direct 64 bit for local dynamic\n\t\t\t\t\t   thread local data in LE code.  */\n#define R_390_TLS_IE32\t\t47\t/* 32 bit address of GOT entry for\n\t\t\t\t\t   negated static TLS block offset.  */\n#define R_390_TLS_IE64\t\t48\t/* 64 bit address of GOT entry for\n\t\t\t\t\t   negated static TLS block offset.  */\n#define R_390_TLS_IEENT\t\t49\t/* 32 bit rel. offset to GOT entry for\n\t\t\t\t\t   negated static TLS block offset.  */\n#define R_390_TLS_LE32\t\t50\t/* 32 bit negated offset relative to\n\t\t\t\t\t   static TLS block.  */\n#define R_390_TLS_LE64\t\t51\t/* 64 bit negated offset relative to\n\t\t\t\t\t   static TLS block.  */\n#define R_390_TLS_LDO32\t\t52\t/* 32 bit offset relative to TLS\n\t\t\t\t\t   block.  */\n#define R_390_TLS_LDO64\t\t53\t/* 64 bit offset relative to TLS\n\t\t\t\t\t   block.  */\n#define R_390_TLS_DTPMOD\t54\t/* ID of module containing symbol.  */\n#define R_390_TLS_DTPOFF\t55\t/* Offset in TLS block.\t */\n#define R_390_TLS_TPOFF\t\t56\t/* Negated offset in static TLS\n\t\t\t\t\t   block.  */\n#define R_390_20\t\t57\t/* Direct 20 bit.  */\n#define R_390_GOT20\t\t58\t/* 20 bit GOT offset.  */\n#define R_390_GOTPLT20\t\t59\t/* 20 bit offset to jump slot.  */\n#define R_390_TLS_GOTIE20\t60\t/* 20 bit GOT offset for static TLS\n\t\t\t\t\t   block offset.  */\n#define R_390_IRELATIVE         61      /* STT_GNU_IFUNC relocation.  */\n/* Keep this the last entry.  */\n#define R_390_NUM\t\t62\n\n\n/* CRIS relocations.  */\n#define R_CRIS_NONE\t\t0\n#define R_CRIS_8\t\t1\n#define R_CRIS_16\t\t2\n#define R_CRIS_32\t\t3\n#define R_CRIS_8_PCREL\t\t4\n#define R_CRIS_16_PCREL\t\t5\n#define R_CRIS_32_PCREL\t\t6\n#define R_CRIS_GNU_VTINHERIT\t7\n#define R_CRIS_GNU_VTENTRY\t8\n#define R_CRIS_COPY\t\t9\n#define R_CRIS_GLOB_DAT\t\t10\n#define R_CRIS_JUMP_SLOT\t11\n#define R_CRIS_RELATIVE\t\t12\n#define R_CRIS_16_GOT\t\t13\n#define R_CRIS_32_GOT\t\t14\n#define R_CRIS_16_GOTPLT\t15\n#define R_CRIS_32_GOTPLT\t16\n#define R_CRIS_32_GOTREL\t17\n#define R_CRIS_32_PLT_GOTREL\t18\n#define R_CRIS_32_PLT_PCREL\t19\n\n#define R_CRIS_NUM\t\t20\n\n\n/* AMD x86-64 relocations.  */\n#define R_X86_64_NONE\t\t0\t/* No reloc */\n#define R_X86_64_64\t\t1\t/* Direct 64 bit  */\n#define R_X86_64_PC32\t\t2\t/* PC relative 32 bit signed */\n#define R_X86_64_GOT32\t\t3\t/* 32 bit GOT entry */\n#define R_X86_64_PLT32\t\t4\t/* 32 bit PLT address */\n#define R_X86_64_COPY\t\t5\t/* Copy symbol at runtime */\n#define R_X86_64_GLOB_DAT\t6\t/* Create GOT entry */\n#define R_X86_64_JUMP_SLOT\t7\t/* Create PLT entry */\n#define R_X86_64_RELATIVE\t8\t/* Adjust by program base */\n#define R_X86_64_GOTPCREL\t9\t/* 32 bit signed PC relative\n\t\t\t\t\t   offset to GOT */\n#define R_X86_64_32\t\t10\t/* Direct 32 bit zero extended */\n#define R_X86_64_32S\t\t11\t/* Direct 32 bit sign extended */\n#define R_X86_64_16\t\t12\t/* Direct 16 bit zero extended */\n#define R_X86_64_PC16\t\t13\t/* 16 bit sign extended pc relative */\n#define R_X86_64_8\t\t14\t/* Direct 8 bit sign extended  */\n#define R_X86_64_PC8\t\t15\t/* 8 bit sign extended pc relative */\n#define R_X86_64_DTPMOD64\t16\t/* ID of module containing symbol */\n#define R_X86_64_DTPOFF64\t17\t/* Offset in module's TLS block */\n#define R_X86_64_TPOFF64\t18\t/* Offset in initial TLS block */\n#define R_X86_64_TLSGD\t\t19\t/* 32 bit signed PC relative offset\n\t\t\t\t\t   to two GOT entries for GD symbol */\n#define R_X86_64_TLSLD\t\t20\t/* 32 bit signed PC relative offset\n\t\t\t\t\t   to two GOT entries for LD symbol */\n#define R_X86_64_DTPOFF32\t21\t/* Offset in TLS block */\n#define R_X86_64_GOTTPOFF\t22\t/* 32 bit signed PC relative offset\n\t\t\t\t\t   to GOT entry for IE symbol */\n#define R_X86_64_TPOFF32\t23\t/* Offset in initial TLS block */\n#define R_X86_64_PC64\t\t24\t/* PC relative 64 bit */\n#define R_X86_64_GOTOFF64\t25\t/* 64 bit offset to GOT */\n#define R_X86_64_GOTPC32\t26\t/* 32 bit signed pc relative\n\t\t\t\t\t   offset to GOT */\n#define R_X86_64_GOT64\t\t27\t/* 64-bit GOT entry offset */\n#define R_X86_64_GOTPCREL64\t28\t/* 64-bit PC relative offset\n\t\t\t\t\t   to GOT entry */\n#define R_X86_64_GOTPC64\t29\t/* 64-bit PC relative offset to GOT */\n#define R_X86_64_GOTPLT64\t30 \t/* like GOT64, says PLT entry needed */\n#define R_X86_64_PLTOFF64\t31\t/* 64-bit GOT relative offset\n\t\t\t\t\t   to PLT entry */\n#define R_X86_64_SIZE32\t\t32\t/* Size of symbol plus 32-bit addend */\n#define R_X86_64_SIZE64\t\t33\t/* Size of symbol plus 64-bit addend */\n#define R_X86_64_GOTPC32_TLSDESC 34\t/* GOT offset for TLS descriptor.  */\n#define R_X86_64_TLSDESC_CALL   35\t/* Marker for call through TLS\n\t\t\t\t\t   descriptor.  */\n#define R_X86_64_TLSDESC        36\t/* TLS descriptor.  */\n#define R_X86_64_IRELATIVE\t37\t/* Adjust indirectly by program base */\n#define R_X86_64_RELATIVE64\t38\t/* 64-bit adjust by program base */\n\n#define R_X86_64_NUM\t\t39\n\n\n/* AM33 relocations.  */\n#define R_MN10300_NONE\t\t0\t/* No reloc.  */\n#define R_MN10300_32\t\t1\t/* Direct 32 bit.  */\n#define R_MN10300_16\t\t2\t/* Direct 16 bit.  */\n#define R_MN10300_8\t\t3\t/* Direct 8 bit.  */\n#define R_MN10300_PCREL32\t4\t/* PC-relative 32-bit.  */\n#define R_MN10300_PCREL16\t5\t/* PC-relative 16-bit signed.  */\n#define R_MN10300_PCREL8\t6\t/* PC-relative 8-bit signed.  */\n#define R_MN10300_GNU_VTINHERIT\t7\t/* Ancient C++ vtable garbage... */\n#define R_MN10300_GNU_VTENTRY\t8\t/* ... collection annotation.  */\n#define R_MN10300_24\t\t9\t/* Direct 24 bit.  */\n#define R_MN10300_GOTPC32\t10\t/* 32-bit PCrel offset to GOT.  */\n#define R_MN10300_GOTPC16\t11\t/* 16-bit PCrel offset to GOT.  */\n#define R_MN10300_GOTOFF32\t12\t/* 32-bit offset from GOT.  */\n#define R_MN10300_GOTOFF24\t13\t/* 24-bit offset from GOT.  */\n#define R_MN10300_GOTOFF16\t14\t/* 16-bit offset from GOT.  */\n#define R_MN10300_PLT32\t\t15\t/* 32-bit PCrel to PLT entry.  */\n#define R_MN10300_PLT16\t\t16\t/* 16-bit PCrel to PLT entry.  */\n#define R_MN10300_GOT32\t\t17\t/* 32-bit offset to GOT entry.  */\n#define R_MN10300_GOT24\t\t18\t/* 24-bit offset to GOT entry.  */\n#define R_MN10300_GOT16\t\t19\t/* 16-bit offset to GOT entry.  */\n#define R_MN10300_COPY\t\t20\t/* Copy symbol at runtime.  */\n#define R_MN10300_GLOB_DAT\t21\t/* Create GOT entry.  */\n#define R_MN10300_JMP_SLOT\t22\t/* Create PLT entry.  */\n#define R_MN10300_RELATIVE\t23\t/* Adjust by program base.  */\n\n#define R_MN10300_NUM\t\t24\n\n\n/* M32R relocs.  */\n#define R_M32R_NONE\t\t0\t/* No reloc. */\n#define R_M32R_16\t\t1\t/* Direct 16 bit. */\n#define R_M32R_32\t\t2\t/* Direct 32 bit. */\n#define R_M32R_24\t\t3\t/* Direct 24 bit. */\n#define R_M32R_10_PCREL\t\t4\t/* PC relative 10 bit shifted. */\n#define R_M32R_18_PCREL\t\t5\t/* PC relative 18 bit shifted. */\n#define R_M32R_26_PCREL\t\t6\t/* PC relative 26 bit shifted. */\n#define R_M32R_HI16_ULO\t\t7\t/* High 16 bit with unsigned low. */\n#define R_M32R_HI16_SLO\t\t8\t/* High 16 bit with signed low. */\n#define R_M32R_LO16\t\t9\t/* Low 16 bit. */\n#define R_M32R_SDA16\t\t10\t/* 16 bit offset in SDA. */\n#define R_M32R_GNU_VTINHERIT\t11\n#define R_M32R_GNU_VTENTRY\t12\n/* M32R relocs use SHT_RELA.  */\n#define R_M32R_16_RELA\t\t33\t/* Direct 16 bit. */\n#define R_M32R_32_RELA\t\t34\t/* Direct 32 bit. */\n#define R_M32R_24_RELA\t\t35\t/* Direct 24 bit. */\n#define R_M32R_10_PCREL_RELA\t36\t/* PC relative 10 bit shifted. */\n#define R_M32R_18_PCREL_RELA\t37\t/* PC relative 18 bit shifted. */\n#define R_M32R_26_PCREL_RELA\t38\t/* PC relative 26 bit shifted. */\n#define R_M32R_HI16_ULO_RELA\t39\t/* High 16 bit with unsigned low */\n#define R_M32R_HI16_SLO_RELA\t40\t/* High 16 bit with signed low */\n#define R_M32R_LO16_RELA\t41\t/* Low 16 bit */\n#define R_M32R_SDA16_RELA\t42\t/* 16 bit offset in SDA */\n#define R_M32R_RELA_GNU_VTINHERIT\t43\n#define R_M32R_RELA_GNU_VTENTRY\t44\n#define R_M32R_REL32\t\t45\t/* PC relative 32 bit.  */\n\n#define R_M32R_GOT24\t\t48\t/* 24 bit GOT entry */\n#define R_M32R_26_PLTREL\t49\t/* 26 bit PC relative to PLT shifted */\n#define R_M32R_COPY\t\t50\t/* Copy symbol at runtime */\n#define R_M32R_GLOB_DAT\t\t51\t/* Create GOT entry */\n#define R_M32R_JMP_SLOT\t\t52\t/* Create PLT entry */\n#define R_M32R_RELATIVE\t\t53\t/* Adjust by program base */\n#define R_M32R_GOTOFF\t\t54\t/* 24 bit offset to GOT */\n#define R_M32R_GOTPC24\t\t55\t/* 24 bit PC relative offset to GOT */\n#define R_M32R_GOT16_HI_ULO\t56\t/* High 16 bit GOT entry with unsigned\n\t\t\t\t\t   low */\n#define R_M32R_GOT16_HI_SLO\t57\t/* High 16 bit GOT entry with signed\n\t\t\t\t\t   low */\n#define R_M32R_GOT16_LO\t\t58\t/* Low 16 bit GOT entry */\n#define R_M32R_GOTPC_HI_ULO\t59\t/* High 16 bit PC relative offset to\n\t\t\t\t\t   GOT with unsigned low */\n#define R_M32R_GOTPC_HI_SLO\t60\t/* High 16 bit PC relative offset to\n\t\t\t\t\t   GOT with signed low */\n#define R_M32R_GOTPC_LO\t\t61\t/* Low 16 bit PC relative offset to\n\t\t\t\t\t   GOT */\n#define R_M32R_GOTOFF_HI_ULO\t62\t/* High 16 bit offset to GOT\n\t\t\t\t\t   with unsigned low */\n#define R_M32R_GOTOFF_HI_SLO\t63\t/* High 16 bit offset to GOT\n\t\t\t\t\t   with signed low */\n#define R_M32R_GOTOFF_LO\t64\t/* Low 16 bit offset to GOT */\n#define R_M32R_NUM\t\t256\t/* Keep this the last entry. */\n\n\n/* TILEPro relocations.  */\n#define R_TILEPRO_NONE\t\t0\t/* No reloc */\n#define R_TILEPRO_32\t\t1\t/* Direct 32 bit */\n#define R_TILEPRO_16\t\t2\t/* Direct 16 bit */\n#define R_TILEPRO_8\t\t3\t/* Direct 8 bit */\n#define R_TILEPRO_32_PCREL\t4\t/* PC relative 32 bit */\n#define R_TILEPRO_16_PCREL\t5\t/* PC relative 16 bit */\n#define R_TILEPRO_8_PCREL\t6\t/* PC relative 8 bit */\n#define R_TILEPRO_LO16\t\t7\t/* Low 16 bit */\n#define R_TILEPRO_HI16\t\t8\t/* High 16 bit */\n#define R_TILEPRO_HA16\t\t9\t/* High 16 bit, adjusted */\n#define R_TILEPRO_COPY\t\t10\t/* Copy relocation */\n#define R_TILEPRO_GLOB_DAT\t11\t/* Create GOT entry */\n#define R_TILEPRO_JMP_SLOT\t12\t/* Create PLT entry */\n#define R_TILEPRO_RELATIVE\t13\t/* Adjust by program base */\n#define R_TILEPRO_BROFF_X1\t14\t/* X1 pipe branch offset */\n#define R_TILEPRO_JOFFLONG_X1\t15\t/* X1 pipe jump offset */\n#define R_TILEPRO_JOFFLONG_X1_PLT 16\t/* X1 pipe jump offset to PLT */\n#define R_TILEPRO_IMM8_X0\t17\t/* X0 pipe 8-bit */\n#define R_TILEPRO_IMM8_Y0\t18\t/* Y0 pipe 8-bit */\n#define R_TILEPRO_IMM8_X1\t19\t/* X1 pipe 8-bit */\n#define R_TILEPRO_IMM8_Y1\t20\t/* Y1 pipe 8-bit */\n#define R_TILEPRO_MT_IMM15_X1\t21\t/* X1 pipe mtspr */\n#define R_TILEPRO_MF_IMM15_X1\t22\t/* X1 pipe mfspr */\n#define R_TILEPRO_IMM16_X0\t23\t/* X0 pipe 16-bit */\n#define R_TILEPRO_IMM16_X1\t24\t/* X1 pipe 16-bit */\n#define R_TILEPRO_IMM16_X0_LO\t25\t/* X0 pipe low 16-bit */\n#define R_TILEPRO_IMM16_X1_LO\t26\t/* X1 pipe low 16-bit */\n#define R_TILEPRO_IMM16_X0_HI\t27\t/* X0 pipe high 16-bit */\n#define R_TILEPRO_IMM16_X1_HI\t28\t/* X1 pipe high 16-bit */\n#define R_TILEPRO_IMM16_X0_HA\t29\t/* X0 pipe high 16-bit, adjusted */\n#define R_TILEPRO_IMM16_X1_HA\t30\t/* X1 pipe high 16-bit, adjusted */\n#define R_TILEPRO_IMM16_X0_PCREL 31\t/* X0 pipe PC relative 16 bit */\n#define R_TILEPRO_IMM16_X1_PCREL 32\t/* X1 pipe PC relative 16 bit */\n#define R_TILEPRO_IMM16_X0_LO_PCREL 33\t/* X0 pipe PC relative low 16 bit */\n#define R_TILEPRO_IMM16_X1_LO_PCREL 34\t/* X1 pipe PC relative low 16 bit */\n#define R_TILEPRO_IMM16_X0_HI_PCREL 35\t/* X0 pipe PC relative high 16 bit */\n#define R_TILEPRO_IMM16_X1_HI_PCREL 36\t/* X1 pipe PC relative high 16 bit */\n#define R_TILEPRO_IMM16_X0_HA_PCREL 37\t/* X0 pipe PC relative ha() 16 bit */\n#define R_TILEPRO_IMM16_X1_HA_PCREL 38\t/* X1 pipe PC relative ha() 16 bit */\n#define R_TILEPRO_IMM16_X0_GOT\t39\t/* X0 pipe 16-bit GOT offset */\n#define R_TILEPRO_IMM16_X1_GOT\t40\t/* X1 pipe 16-bit GOT offset */\n#define R_TILEPRO_IMM16_X0_GOT_LO 41\t/* X0 pipe low 16-bit GOT offset */\n#define R_TILEPRO_IMM16_X1_GOT_LO 42\t/* X1 pipe low 16-bit GOT offset */\n#define R_TILEPRO_IMM16_X0_GOT_HI 43\t/* X0 pipe high 16-bit GOT offset */\n#define R_TILEPRO_IMM16_X1_GOT_HI 44\t/* X1 pipe high 16-bit GOT offset */\n#define R_TILEPRO_IMM16_X0_GOT_HA 45\t/* X0 pipe ha() 16-bit GOT offset */\n#define R_TILEPRO_IMM16_X1_GOT_HA 46\t/* X1 pipe ha() 16-bit GOT offset */\n#define R_TILEPRO_MMSTART_X0\t47\t/* X0 pipe mm \"start\" */\n#define R_TILEPRO_MMEND_X0\t48\t/* X0 pipe mm \"end\" */\n#define R_TILEPRO_MMSTART_X1\t49\t/* X1 pipe mm \"start\" */\n#define R_TILEPRO_MMEND_X1\t50\t/* X1 pipe mm \"end\" */\n#define R_TILEPRO_SHAMT_X0\t51\t/* X0 pipe shift amount */\n#define R_TILEPRO_SHAMT_X1\t52\t/* X1 pipe shift amount */\n#define R_TILEPRO_SHAMT_Y0\t53\t/* Y0 pipe shift amount */\n#define R_TILEPRO_SHAMT_Y1\t54\t/* Y1 pipe shift amount */\n#define R_TILEPRO_DEST_IMM8_X1\t55\t/* X1 pipe destination 8-bit */\n/* Relocs 56-59 are currently not defined.  */\n#define R_TILEPRO_TLS_GD_CALL\t60\t/* \"jal\" for TLS GD */\n#define R_TILEPRO_IMM8_X0_TLS_GD_ADD 61\t/* X0 pipe \"addi\" for TLS GD */\n#define R_TILEPRO_IMM8_X1_TLS_GD_ADD 62\t/* X1 pipe \"addi\" for TLS GD */\n#define R_TILEPRO_IMM8_Y0_TLS_GD_ADD 63\t/* Y0 pipe \"addi\" for TLS GD */\n#define R_TILEPRO_IMM8_Y1_TLS_GD_ADD 64\t/* Y1 pipe \"addi\" for TLS GD */\n#define R_TILEPRO_TLS_IE_LOAD\t65\t/* \"lw_tls\" for TLS IE */\n#define R_TILEPRO_IMM16_X0_TLS_GD 66\t/* X0 pipe 16-bit TLS GD offset */\n#define R_TILEPRO_IMM16_X1_TLS_GD 67\t/* X1 pipe 16-bit TLS GD offset */\n#define R_TILEPRO_IMM16_X0_TLS_GD_LO 68\t/* X0 pipe low 16-bit TLS GD offset */\n#define R_TILEPRO_IMM16_X1_TLS_GD_LO 69\t/* X1 pipe low 16-bit TLS GD offset */\n#define R_TILEPRO_IMM16_X0_TLS_GD_HI 70\t/* X0 pipe high 16-bit TLS GD offset */\n#define R_TILEPRO_IMM16_X1_TLS_GD_HI 71\t/* X1 pipe high 16-bit TLS GD offset */\n#define R_TILEPRO_IMM16_X0_TLS_GD_HA 72\t/* X0 pipe ha() 16-bit TLS GD offset */\n#define R_TILEPRO_IMM16_X1_TLS_GD_HA 73\t/* X1 pipe ha() 16-bit TLS GD offset */\n#define R_TILEPRO_IMM16_X0_TLS_IE 74\t/* X0 pipe 16-bit TLS IE offset */\n#define R_TILEPRO_IMM16_X1_TLS_IE 75\t/* X1 pipe 16-bit TLS IE offset */\n#define R_TILEPRO_IMM16_X0_TLS_IE_LO 76\t/* X0 pipe low 16-bit TLS IE offset */\n#define R_TILEPRO_IMM16_X1_TLS_IE_LO 77\t/* X1 pipe low 16-bit TLS IE offset */\n#define R_TILEPRO_IMM16_X0_TLS_IE_HI 78\t/* X0 pipe high 16-bit TLS IE offset */\n#define R_TILEPRO_IMM16_X1_TLS_IE_HI 79\t/* X1 pipe high 16-bit TLS IE offset */\n#define R_TILEPRO_IMM16_X0_TLS_IE_HA 80\t/* X0 pipe ha() 16-bit TLS IE offset */\n#define R_TILEPRO_IMM16_X1_TLS_IE_HA 81\t/* X1 pipe ha() 16-bit TLS IE offset */\n#define R_TILEPRO_TLS_DTPMOD32\t82\t/* ID of module containing symbol */\n#define R_TILEPRO_TLS_DTPOFF32\t83\t/* Offset in TLS block */\n#define R_TILEPRO_TLS_TPOFF32\t84\t/* Offset in static TLS block */\n#define R_TILEPRO_IMM16_X0_TLS_LE 85\t/* X0 pipe 16-bit TLS LE offset */\n#define R_TILEPRO_IMM16_X1_TLS_LE 86\t/* X1 pipe 16-bit TLS LE offset */\n#define R_TILEPRO_IMM16_X0_TLS_LE_LO 87\t/* X0 pipe low 16-bit TLS LE offset */\n#define R_TILEPRO_IMM16_X1_TLS_LE_LO 88\t/* X1 pipe low 16-bit TLS LE offset */\n#define R_TILEPRO_IMM16_X0_TLS_LE_HI 89\t/* X0 pipe high 16-bit TLS LE offset */\n#define R_TILEPRO_IMM16_X1_TLS_LE_HI 90\t/* X1 pipe high 16-bit TLS LE offset */\n#define R_TILEPRO_IMM16_X0_TLS_LE_HA 91\t/* X0 pipe ha() 16-bit TLS LE offset */\n#define R_TILEPRO_IMM16_X1_TLS_LE_HA 92\t/* X1 pipe ha() 16-bit TLS LE offset */\n\n#define R_TILEPRO_GNU_VTINHERIT\t128\t/* GNU C++ vtable hierarchy */\n#define R_TILEPRO_GNU_VTENTRY\t129\t/* GNU C++ vtable member usage */\n\n#define R_TILEPRO_NUM\t\t130\n\n\n/* TILE-Gx relocations.  */\n#define R_TILEGX_NONE\t\t0\t/* No reloc */\n#define R_TILEGX_64\t\t1\t/* Direct 64 bit */\n#define R_TILEGX_32\t\t2\t/* Direct 32 bit */\n#define R_TILEGX_16\t\t3\t/* Direct 16 bit */\n#define R_TILEGX_8\t\t4\t/* Direct 8 bit */\n#define R_TILEGX_64_PCREL\t5\t/* PC relative 64 bit */\n#define R_TILEGX_32_PCREL\t6\t/* PC relative 32 bit */\n#define R_TILEGX_16_PCREL\t7\t/* PC relative 16 bit */\n#define R_TILEGX_8_PCREL\t8\t/* PC relative 8 bit */\n#define R_TILEGX_HW0\t\t9\t/* hword 0 16-bit */\n#define R_TILEGX_HW1\t\t10\t/* hword 1 16-bit */\n#define R_TILEGX_HW2\t\t11\t/* hword 2 16-bit */\n#define R_TILEGX_HW3\t\t12\t/* hword 3 16-bit */\n#define R_TILEGX_HW0_LAST\t13\t/* last hword 0 16-bit */\n#define R_TILEGX_HW1_LAST\t14\t/* last hword 1 16-bit */\n#define R_TILEGX_HW2_LAST\t15\t/* last hword 2 16-bit */\n#define R_TILEGX_COPY\t\t16\t/* Copy relocation */\n#define R_TILEGX_GLOB_DAT\t17\t/* Create GOT entry */\n#define R_TILEGX_JMP_SLOT\t18\t/* Create PLT entry */\n#define R_TILEGX_RELATIVE\t19\t/* Adjust by program base */\n#define R_TILEGX_BROFF_X1\t20\t/* X1 pipe branch offset */\n#define R_TILEGX_JUMPOFF_X1\t21\t/* X1 pipe jump offset */\n#define R_TILEGX_JUMPOFF_X1_PLT\t22\t/* X1 pipe jump offset to PLT */\n#define R_TILEGX_IMM8_X0\t23\t/* X0 pipe 8-bit */\n#define R_TILEGX_IMM8_Y0\t24\t/* Y0 pipe 8-bit */\n#define R_TILEGX_IMM8_X1\t25\t/* X1 pipe 8-bit */\n#define R_TILEGX_IMM8_Y1\t26\t/* Y1 pipe 8-bit */\n#define R_TILEGX_DEST_IMM8_X1\t27\t/* X1 pipe destination 8-bit */\n#define R_TILEGX_MT_IMM14_X1\t28\t/* X1 pipe mtspr */\n#define R_TILEGX_MF_IMM14_X1\t29\t/* X1 pipe mfspr */\n#define R_TILEGX_MMSTART_X0\t30\t/* X0 pipe mm \"start\" */\n#define R_TILEGX_MMEND_X0\t31\t/* X0 pipe mm \"end\" */\n#define R_TILEGX_SHAMT_X0\t32\t/* X0 pipe shift amount */\n#define R_TILEGX_SHAMT_X1\t33\t/* X1 pipe shift amount */\n#define R_TILEGX_SHAMT_Y0\t34\t/* Y0 pipe shift amount */\n#define R_TILEGX_SHAMT_Y1\t35\t/* Y1 pipe shift amount */\n#define R_TILEGX_IMM16_X0_HW0\t36\t/* X0 pipe hword 0 */\n#define R_TILEGX_IMM16_X1_HW0\t37\t/* X1 pipe hword 0 */\n#define R_TILEGX_IMM16_X0_HW1\t38\t/* X0 pipe hword 1 */\n#define R_TILEGX_IMM16_X1_HW1\t39\t/* X1 pipe hword 1 */\n#define R_TILEGX_IMM16_X0_HW2\t40\t/* X0 pipe hword 2 */\n#define R_TILEGX_IMM16_X1_HW2\t41\t/* X1 pipe hword 2 */\n#define R_TILEGX_IMM16_X0_HW3\t42\t/* X0 pipe hword 3 */\n#define R_TILEGX_IMM16_X1_HW3\t43\t/* X1 pipe hword 3 */\n#define R_TILEGX_IMM16_X0_HW0_LAST 44\t/* X0 pipe last hword 0 */\n#define R_TILEGX_IMM16_X1_HW0_LAST 45\t/* X1 pipe last hword 0 */\n#define R_TILEGX_IMM16_X0_HW1_LAST 46\t/* X0 pipe last hword 1 */\n#define R_TILEGX_IMM16_X1_HW1_LAST 47\t/* X1 pipe last hword 1 */\n#define R_TILEGX_IMM16_X0_HW2_LAST 48\t/* X0 pipe last hword 2 */\n#define R_TILEGX_IMM16_X1_HW2_LAST 49\t/* X1 pipe last hword 2 */\n#define R_TILEGX_IMM16_X0_HW0_PCREL 50\t/* X0 pipe PC relative hword 0 */\n#define R_TILEGX_IMM16_X1_HW0_PCREL 51\t/* X1 pipe PC relative hword 0 */\n#define R_TILEGX_IMM16_X0_HW1_PCREL 52\t/* X0 pipe PC relative hword 1 */\n#define R_TILEGX_IMM16_X1_HW1_PCREL 53\t/* X1 pipe PC relative hword 1 */\n#define R_TILEGX_IMM16_X0_HW2_PCREL 54\t/* X0 pipe PC relative hword 2 */\n#define R_TILEGX_IMM16_X1_HW2_PCREL 55\t/* X1 pipe PC relative hword 2 */\n#define R_TILEGX_IMM16_X0_HW3_PCREL 56\t/* X0 pipe PC relative hword 3 */\n#define R_TILEGX_IMM16_X1_HW3_PCREL 57\t/* X1 pipe PC relative hword 3 */\n#define R_TILEGX_IMM16_X0_HW0_LAST_PCREL 58 /* X0 pipe PC-rel last hword 0 */\n#define R_TILEGX_IMM16_X1_HW0_LAST_PCREL 59 /* X1 pipe PC-rel last hword 0 */\n#define R_TILEGX_IMM16_X0_HW1_LAST_PCREL 60 /* X0 pipe PC-rel last hword 1 */\n#define R_TILEGX_IMM16_X1_HW1_LAST_PCREL 61 /* X1 pipe PC-rel last hword 1 */\n#define R_TILEGX_IMM16_X0_HW2_LAST_PCREL 62 /* X0 pipe PC-rel last hword 2 */\n#define R_TILEGX_IMM16_X1_HW2_LAST_PCREL 63 /* X1 pipe PC-rel last hword 2 */\n#define R_TILEGX_IMM16_X0_HW0_GOT 64\t/* X0 pipe hword 0 GOT offset */\n#define R_TILEGX_IMM16_X1_HW0_GOT 65\t/* X1 pipe hword 0 GOT offset */\n/* Relocs 66-71 are currently not defined.  */\n#define R_TILEGX_IMM16_X0_HW0_LAST_GOT 72 /* X0 pipe last hword 0 GOT offset */\n#define R_TILEGX_IMM16_X1_HW0_LAST_GOT 73 /* X1 pipe last hword 0 GOT offset */\n#define R_TILEGX_IMM16_X0_HW1_LAST_GOT 74 /* X0 pipe last hword 1 GOT offset */\n#define R_TILEGX_IMM16_X1_HW1_LAST_GOT 75 /* X1 pipe last hword 1 GOT offset */\n/* Relocs 76-77 are currently not defined.  */\n#define R_TILEGX_IMM16_X0_HW0_TLS_GD 78\t/* X0 pipe hword 0 TLS GD offset */\n#define R_TILEGX_IMM16_X1_HW0_TLS_GD 79\t/* X1 pipe hword 0 TLS GD offset */\n#define R_TILEGX_IMM16_X0_HW0_TLS_LE 80\t/* X0 pipe hword 0 TLS LE offset */\n#define R_TILEGX_IMM16_X1_HW0_TLS_LE 81\t/* X1 pipe hword 0 TLS LE offset */\n#define R_TILEGX_IMM16_X0_HW0_LAST_TLS_LE 82 /* X0 pipe last hword 0 LE off */\n#define R_TILEGX_IMM16_X1_HW0_LAST_TLS_LE 83 /* X1 pipe last hword 0 LE off */\n#define R_TILEGX_IMM16_X0_HW1_LAST_TLS_LE 84 /* X0 pipe last hword 1 LE off */\n#define R_TILEGX_IMM16_X1_HW1_LAST_TLS_LE 85 /* X1 pipe last hword 1 LE off */\n#define R_TILEGX_IMM16_X0_HW0_LAST_TLS_GD 86 /* X0 pipe last hword 0 GD off */\n#define R_TILEGX_IMM16_X1_HW0_LAST_TLS_GD 87 /* X1 pipe last hword 0 GD off */\n#define R_TILEGX_IMM16_X0_HW1_LAST_TLS_GD 88 /* X0 pipe last hword 1 GD off */\n#define R_TILEGX_IMM16_X1_HW1_LAST_TLS_GD 89 /* X1 pipe last hword 1 GD off */\n/* Relocs 90-91 are currently not defined.  */\n#define R_TILEGX_IMM16_X0_HW0_TLS_IE 92\t/* X0 pipe hword 0 TLS IE offset */\n#define R_TILEGX_IMM16_X1_HW0_TLS_IE 93\t/* X1 pipe hword 0 TLS IE offset */\n/* Relocs 94-99 are currently not defined.  */\n#define R_TILEGX_IMM16_X0_HW0_LAST_TLS_IE 100 /* X0 pipe last hword 0 IE off */\n#define R_TILEGX_IMM16_X1_HW0_LAST_TLS_IE 101 /* X1 pipe last hword 0 IE off */\n#define R_TILEGX_IMM16_X0_HW1_LAST_TLS_IE 102 /* X0 pipe last hword 1 IE off */\n#define R_TILEGX_IMM16_X1_HW1_LAST_TLS_IE 103 /* X1 pipe last hword 1 IE off */\n/* Relocs 104-105 are currently not defined.  */\n#define R_TILEGX_TLS_DTPMOD64\t106\t/* 64-bit ID of symbol's module */\n#define R_TILEGX_TLS_DTPOFF64\t107\t/* 64-bit offset in TLS block */\n#define R_TILEGX_TLS_TPOFF64\t108\t/* 64-bit offset in static TLS block */\n#define R_TILEGX_TLS_DTPMOD32\t109\t/* 32-bit ID of symbol's module */\n#define R_TILEGX_TLS_DTPOFF32\t110\t/* 32-bit offset in TLS block */\n#define R_TILEGX_TLS_TPOFF32\t111\t/* 32-bit offset in static TLS block */\n#define R_TILEGX_TLS_GD_CALL\t112\t/* \"jal\" for TLS GD */\n#define R_TILEGX_IMM8_X0_TLS_GD_ADD 113\t/* X0 pipe \"addi\" for TLS GD */\n#define R_TILEGX_IMM8_X1_TLS_GD_ADD 114\t/* X1 pipe \"addi\" for TLS GD */\n#define R_TILEGX_IMM8_Y0_TLS_GD_ADD 115\t/* Y0 pipe \"addi\" for TLS GD */\n#define R_TILEGX_IMM8_Y1_TLS_GD_ADD 116\t/* Y1 pipe \"addi\" for TLS GD */\n#define R_TILEGX_TLS_IE_LOAD\t117\t/* \"ld_tls\" for TLS IE */\n#define R_TILEGX_IMM8_X0_TLS_ADD 118\t/* X0 pipe \"addi\" for TLS GD/IE */\n#define R_TILEGX_IMM8_X1_TLS_ADD 119\t/* X1 pipe \"addi\" for TLS GD/IE */\n#define R_TILEGX_IMM8_Y0_TLS_ADD 120\t/* Y0 pipe \"addi\" for TLS GD/IE */\n#define R_TILEGX_IMM8_Y1_TLS_ADD 121\t/* Y1 pipe \"addi\" for TLS GD/IE */\n\n#define R_TILEGX_GNU_VTINHERIT\t128\t/* GNU C++ vtable hierarchy */\n#define R_TILEGX_GNU_VTENTRY\t129\t/* GNU C++ vtable member usage */\n\n#define R_TILEGX_NUM\t\t130\n\n#endif\t/* elf.h */\n"
  },
  {
    "path": "tools/include/endian.h",
    "content": "#ifndef __endian_compat_h\n#define __endian_compat_h\n\n#if defined(__linux__) || defined(__CYGWIN__)\n#include <byteswap.h>\n#include_next <endian.h>\n#elif defined(__APPLE__)\n#include <netinet/in.h>\n#include <libkern/OSByteOrder.h>\n#define bswap_16(x) OSSwapInt16(x)\n#define bswap_32(x) OSSwapInt32(x)\n#define bswap_64(x) OSSwapInt64(x)\n#elif defined(__FreeBSD__)\n#include <sys/endian.h>\n#define bswap_16(x) bswap16(x)\n#define bswap_32(x) bswap32(x)\n#define bswap_64(x) bswap64(x)\n#elif defined(__OpenBSD__)\n#include <sys/types.h>\n#define bswap_16(x) __swap16(x)\n#define bswap_32(x) __swap32(x)\n#define bswap_64(x) __swap64(x)\n#else\n#include <machine/endian.h>\n#define bswap_16(x) swap16(x)\n#define bswap_32(x) swap32(x)\n#define bswap_64(x) swap64(x)\n#endif\n\n#ifndef __BYTE_ORDER\n#define __BYTE_ORDER BYTE_ORDER\n#endif\n#ifndef __BIG_ENDIAN\n#define __BIG_ENDIAN BIG_ENDIAN\n#endif\n#ifndef __LITTLE_ENDIAN\n#define __LITTLE_ENDIAN LITTLE_ENDIAN\n#endif\n\n#endif\n"
  },
  {
    "path": "tools/include/sys/sysmacros.h",
    "content": "/* Definitions of macros to access `dev_t' values.\n   Copyright (C) 1996, 1997, 1999, 2003, 2004 Free Software Foundation, Inc.\n   This file is part of the GNU C Library.\n\n   The GNU C Library is free software; you can redistribute it and/or\n   modify it under the terms of the GNU Lesser General Public\n   License as published by the Free Software Foundation; either\n   version 2.1 of the License, or (at your option) any later version.\n\n   The GNU C Library is distributed in the hope that it will be useful,\n   but WITHOUT ANY WARRANTY; without even the implied warranty of\n   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\n   Lesser General Public License for more details.\n\n   You should have received a copy of the GNU Lesser General Public\n   License along with the GNU C Library; if not, write to the Free\n   Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA\n   02111-1307 USA.  */\n\n#ifndef __SYS_SYSMACROS_H\n#define __SYS_SYSMACROS_H\t1\n\nstatic inline unsigned int\n__gnu_dev_major(unsigned long long int __dev)\n{\n  return ((__dev >> 8) & 0xfff) | ((unsigned int) (__dev >> 32) & ~0xfff);\n}\n\nstatic inline unsigned int\n__gnu_dev_minor(unsigned long long int __dev)\n{\n  return (__dev & 0xff) | ((unsigned int) (__dev >> 12) & ~0xff);\n}\n\nstatic inline unsigned long long int\n__gnu_dev_makedev(unsigned int __major, unsigned int __minor)\n{\n  return ((__minor & 0xff) | ((__major & 0xfff) << 8)\n\t  | (((unsigned long long int) (__minor & ~0xff)) << 12)\n\t  | (((unsigned long long int) (__major & ~0xfff)) << 32));\n}\n\n/* Access the functions with their traditional names.  */\n#ifndef major\n# define major(dev) __gnu_dev_major (dev)\n#endif\n\n#ifndef minor\n# define minor(dev) __gnu_dev_minor (dev)\n#endif\n\n#ifndef makedev\n# define makedev(maj, min) __gnu_dev_makedev (maj, min)\n#endif\n\n#endif /* sys/sysmacros.h */\n"
  },
  {
    "path": "tools/isl/Makefile",
    "content": "#\n# Copyright (C) 2009-2013 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=isl\nPKG_VERSION:=0.24\n\nPKG_SOURCE_URL:=https://libisl.sourceforge.io/\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz\nPKG_HASH:=043105cc544f416b48736fff8caf077fb0663a717d06b1113f16e391ac99ebad\n\nHOST_BUILD_PARALLEL:=1\n\ninclude $(INCLUDE_DIR)/host-build.mk\n\nunexport CFLAGS\n\nHOST_CONFIGURE_ARGS += \\\n\t--enable-static \\\n\t--disable-shared \\\n\t--with-gmp-prefix=$(STAGING_DIR_HOST)\n\n$(eval $(call HostBuild))\n"
  },
  {
    "path": "tools/kernel2minor/Makefile",
    "content": "#\n# Copyright (C) 2016 adron@yapic.net\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=kernel2minor\nPKG_VERSION:=0.25\nPKG_RELEASE:=1\n\nPKG_SOURCE_URL:=https://github.com/adron-s/kernel2minor.git\nPKG_MIRROR_HASH:=6083c46c2fe0da37bacd04d5d5439c0e2a9d00e58ff47a63acfd5057d2aa2145\nPKG_SOURCE_PROTO:=git\nPKG_SOURCE_VERSION:=1e5a52c7941945f6d64807ebca4a5923ba5466bd\nPKG_HASH:=33ca413403a3341af0c9a8e6d9bb58f4ad080a5339e8a8729b83637d35bfaf1b\n\ninclude $(INCLUDE_DIR)/host-build.mk\n\ndefine Host/Install\n\t$(INSTALL_BIN) $(HOST_BUILD_DIR)/kernel2minor $(STAGING_DIR_HOST)/bin/\nendef\n\ndefine Host/Clean\n\trm -f $(STAGING_DIR_HOST)/bin/kernel2minor\nendef\n\n$(eval $(call HostBuild))\n"
  },
  {
    "path": "tools/libressl/Makefile",
    "content": "#\n# Copyright (C) 2016-2017 LEDE project\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=libressl\nPKG_VERSION:=3.4.2\nPKG_HASH:=cb82ca7d547336917352fbd23db2fc483c6c44d35157b32780214ec74197b3ce\nPKG_RELEASE:=1\n\nPKG_CPE_ID:=cpe:/a:openbsd:libressl\n\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz\nPKG_SOURCE_URL:=http://mirror.ox.ac.uk/pub/OpenBSD/LibreSSL \\\n\thttp://ftp.jaist.ac.jp/pub/OpenBSD/LibreSSL \\\n\thttps://ftp.openbsd.org/pub/OpenBSD/LibreSSL\n\nHOST_BUILD_PARALLEL:=1\n\ninclude $(INCLUDE_DIR)/host-build.mk\n\nHOSTCC := $(HOSTCC_NOCACHE)\nHOST_CONFIGURE_ARGS += --enable-static --disable-shared --disable-tests\nHOST_CFLAGS += $(HOST_FPIC)\n\nifeq ($(GNU_HOST_NAME),x86_64-linux-gnux32)\nHOST_CONFIGURE_ARGS += --disable-asm\nendif\n\n$(eval $(call HostBuild))\n"
  },
  {
    "path": "tools/libtool/Makefile",
    "content": "# \n# Copyright (C) 2008-2015 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=libtool\nPKG_CPE_ID:=cpe:/a:gnu:libtool\nPKG_VERSION:=2.4.2\n\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz\nPKG_SOURCE_URL:=@GNU/$(PKG_NAME)\nPKG_HASH:=1d7b6862c1ed162e327f083a6f78f40eae29218f0db8c38393d61dab764c4407\n\nHOST_BUILD_PARALLEL:=1\n\ninclude $(INCLUDE_DIR)/host-build.mk\n\nHOST_CONFIGURE_VARS += \\\n\tlt_cv_sys_dlsearch_path=\"\"\n\ndefine Host/Prepare\n\t$(call Host/Prepare/Default)\n\t(cd $(STAGING_DIR_HOST)/share/aclocal/ && rm -f libtool.m4 ltdl.m4 lt~obsolete.m4 ltoptions.m4 ltsugar.m4 ltversion.m4)\n\t(cd $(HOST_BUILD_DIR); $(AM_TOOL_PATHS) ./bootstrap)\nendef\n\ndefine Host/Install\n\t$(MAKE) -C $(HOST_BUILD_DIR) install\n\t$(SED) 's,\\(hardcode_into_libs\\)=yes,\\1=no,g' $(STAGING_DIR_HOST)/bin/libtool\n\t$(CP) $(STAGING_DIR_HOST)/bin/libtool $(STAGING_DIR_HOST)/bin/libtool-ucxx\n\t$(SED) 's,-lstdc++,-luClibc++,g' $(STAGING_DIR_HOST)/bin/libtool-ucxx\nendef\n\ndefine Host/Clean\n\t-$(MAKE) -C $(HOST_BUILD_DIR) uninstall\n\t$(call Host/Clean/Default)\nendef\n\n$(eval $(call HostBuild))\n"
  },
  {
    "path": "tools/libtool/files/libtool-v1.5.patch",
    "content": "--- a/ltmain.sh\n+++ b/ltmain.sh\n@@ -35,7 +35,7 @@ progpath=\"$0\"\n \n # The name of this program:\n progname=`echo \"$progpath\" | $SED $basename`\n-modename=\"$progname\"\n+modename=\"OpenWrt-$progname-patched-1.5\"\n \n # Global variables:\n EXIT_SUCCESS=0\n@@ -297,8 +297,8 @@ func_infer_tag ()\n \t# line option must be used.\n \tif test -z \"$tagname\"; then\n \t  $echo \"$modename: unable to infer tagged configuration\"\n-\t  $echo \"$modename: specify a tag with \\`--tag'\" 1>&2\n-\t  exit $EXIT_FAILURE\n+\t  $echo \"$modename: defaulting to \\`CC'\"\n+\t  $echo \"$modename: if this is not correct, specify a tag with \\`--tag'\"\n #        else\n #          $echo \"$modename: using $tagname tagged configuration\"\n \tfi\n@@ -2462,8 +2462,14 @@ EOF\n \t    absdir=\"$abs_ladir\"\n \t    libdir=\"$abs_ladir\"\n \t  else\n-\t    dir=\"$libdir\"\n-\t    absdir=\"$libdir\"\n+\t    # Adding 'libdir' from the .la file to our library search paths\n+\t    # breaks crosscompilation horribly.  We cheat here and don't add\n+\t    # it, instead adding the path where we found the .la.  -CL\n+\t    dir=\"$lt_sysroot$abs_ladir\"\n+\t    absdir=\"$abs_ladir\"\n+\t    libdir=\"$abs_ladir\"\n+\t    #dir=\"$libdir\"\n+\t    #absdir=\"$libdir\"\n \t  fi\n \t  test \"X$hardcode_automatic\" = Xyes && avoidtemprpath=yes\n \telse\n@@ -2602,7 +2608,7 @@ EOF\n \t   { test \"$use_static_libs\" = no || test -z \"$old_library\"; }; then\n \t  if test \"$installed\" = no; then\n \t    notinst_deplibs=\"$notinst_deplibs $lib\"\n-\t    need_relink=yes\n+\t    need_relink=no\n \t  fi\n \t  # This is a shared library\n \n@@ -2804,7 +2810,6 @@ EOF\n \t    if test \"$hardcode_direct\" = yes; then\n \t      add=\"$libdir/$linklib\"\n \t    elif test \"$hardcode_minus_L\" = yes; then\n-\t      add_dir=\"-L$libdir\"\n \t      add=\"-l$name\"\n \t    elif test \"$hardcode_shlibpath_var\" = yes; then\n \t      case :$finalize_shlibpath: in\n@@ -2820,8 +2825,6 @@ EOF\n \t        add=\"$libdir/$linklib\"\n \t      fi\n \t    else\n-\t      # We cannot seem to hardcode it, guess we'll fake it.\n-\t      add_dir=\"-L$libdir\"\n \t      # Try looking first in the location we're being installed to.\n \t      if test -n \"$inst_prefix_dir\"; then\n \t\tcase $libdir in\n@@ -5687,6 +5690,10 @@ fi\\\n \t    # Replace all uninstalled libtool libraries with the installed ones\n \t    newdependency_libs=\n \t    for deplib in $dependency_libs; do\n+\t      # Replacing uninstalled with installed can easily break crosscompilation,\n+\t      # since the installed path is generally the wrong architecture.  -CL\n+\t      newdependency_libs=\"$newdependency_libs $deplib\"\n+\t      continue\n \t      case $deplib in\n \t      *.la)\n \t\tname=`$echo \"X$deplib\" | $Xsed -e 's%^.*/%%'`\n@@ -5999,8 +6006,12 @@ relink_command=\\\"$relink_command\\\"\"\n \tdir=\"$dir$objdir\"\n \n \tif test -n \"$relink_command\"; then\n+\t  # Strip any trailing slash from the destination.\n+\t  s_libdir=`$echo \"X$libdir\" | $Xsed -e 's%/$%%'`\n+\t  s_destdir=`$echo \"X$destdir\" | $Xsed -e 's%/$%%'`\n+\n \t  # Determine the prefix the user has applied to our future dir.\n-\t  inst_prefix_dir=`$echo \"$destdir\" | $SED \"s%$libdir\\$%%\"`\n+\t  inst_prefix_dir=`$echo \"$s_destdir\" | $SED \"s%$s_libdir\\$%%\"`\n \n \t  # Don't allow the user to place us outside of our expected\n \t  # location b/c this prevents finding dependent libraries that\n@@ -6008,10 +6019,13 @@ relink_command=\\\"$relink_command\\\"\"\n \t  # At present, this check doesn't affect windows .dll's that\n \t  # are installed into $libdir/../bin (currently, that works fine)\n \t  # but it's something to keep an eye on.\n-\t  if test \"$inst_prefix_dir\" = \"$destdir\"; then\n-\t    $echo \"$modename: error: cannot install \\`$file' to a directory not ending in $libdir\" 1>&2\n-\t    exit $EXIT_FAILURE\n-\t  fi\n+\t  #\n+\t  # This breaks install into our staging area.  -PB\n+\t  #\n+\t  # if test \"$inst_prefix_dir\" = \"$destdir\"; then\n+\t  #   $echo \"$modename: error: cannot install \\`$file' to a directory not ending in $libdir\" 1>&2\n+\t  #   exit $EXIT_FAILURE\n+\t  # fi\n \n \t  if test -n \"$inst_prefix_dir\"; then\n \t    # Stick the inst_prefix_dir data into the link command.\n@@ -6020,6 +6034,9 @@ relink_command=\\\"$relink_command\\\"\"\n \t    relink_command=`$echo \"$relink_command\" | $SP2NL | $SED \"s%@inst_prefix_dir@%%\" | $NL2SP`\n \t  fi\n \n+\t  relink_command=`$ECHO \"$relink_command\" | $SED \"s%-L[[:space:]]*/lib[^[:space:]]*%%\"`\n+\t  relink_command=`$ECHO \"$relink_command\" | $SED \"s%-L[[:space:]]*/usr/lib[^[:space:]]*%%\"`\n+\n \t  $echo \"$modename: warning: relinking \\`$file'\" 1>&2\n \t  $show \"$relink_command\"\n \t  if $run eval \"$relink_command\"; then :\n"
  },
  {
    "path": "tools/libtool/files/libtool-v2.2.patch",
    "content": "--- a/ltmain.sh\n+++ b/ltmain.sh\n@@ -243,7 +243,7 @@ opt_warning=:\n # name if it has been set yet.\n func_echo ()\n {\n-    $ECHO \"$progname${mode+: }$mode: $*\"\n+    $ECHO \"OpenWrt-$progname-patched-2.2${mode+: }$mode: $*\"\n }\n \n # func_verbose arg...\n@@ -262,14 +262,14 @@ func_verbose ()\n # Echo program name prefixed message to standard error.\n func_error ()\n {\n-    $ECHO \"$progname${mode+: }$mode: \"${1+\"$@\"} 1>&2\n+    $ECHO \"OpenWrt-$progname-patched-2.2${mode+: }$mode: \"${1+\"$@\"} 1>&2\n }\n \n # func_warning arg...\n # Echo program name prefixed warning message to standard error.\n func_warning ()\n {\n-    $opt_warning && $ECHO \"$progname${mode+: }$mode: warning: \"${1+\"$@\"} 1>&2\n+    $opt_warning && $ECHO \"OpenWrt-$progname-patched-2.2${mode+: }$mode: warning: \"${1+\"$@\"} 1>&2\n \n     # bash bug again:\n     :\n@@ -1048,8 +1048,8 @@ func_infer_tag ()\n \t# was found and let the user know that the \"--tag\" command\n \t# line option must be used.\n \tif test -z \"$tagname\"; then\n-\t  func_echo \"unable to infer tagged configuration\"\n-\t  func_fatal_error \"specify a tag with \\`--tag'\"\n+\t  func_echo \"defaulting to \\`CC'\"\n+\t  func_echo \"if this is not correct, specify a tag with \\`--tag'\"\n #\telse\n #\t  func_verbose \"using $tagname tagged configuration\"\n \tfi\n@@ -2009,8 +2009,15 @@ func_mode_install ()\n \tdir=\"$dir$objdir\"\n \n \tif test -n \"$relink_command\"; then\n+\t  # Strip any trailing slash from the destination.\n+\t  func_stripname '' '/' \"$libdir\"\n+\t  s_libdir=$func_stripname_result\n+\n+\t  func_stripname '' '/' \"$destdir\"\n+\t  s_destdir=$func_stripname_result\n+\n \t  # Determine the prefix the user has applied to our future dir.\n-\t  inst_prefix_dir=`$ECHO \"X$destdir\" | $Xsed -e \"s%$libdir\\$%%\"`\n+\t  inst_prefix_dir=`$ECHO \"X$s_destdir\" | $Xsed -e \"s%$s_libdir\\$%%\"`\n \n \t  # Don't allow the user to place us outside of our expected\n \t  # location b/c this prevents finding dependent libraries that\n@@ -2018,8 +2025,11 @@ func_mode_install ()\n \t  # At present, this check doesn't affect windows .dll's that\n \t  # are installed into $libdir/../bin (currently, that works fine)\n \t  # but it's something to keep an eye on.\n-\t  test \"$inst_prefix_dir\" = \"$destdir\" && \\\n-\t    func_fatal_error \"error: cannot install \\`$file' to a directory not ending in $libdir\"\n+\t  #\n+\t  # This breaks install into our staging area.  -PB\n+\t  #\n+\t  # test \"$inst_prefix_dir\" = \"$destdir\" && \\\n+\t  #   func_fatal_error \"error: cannot install \\`$file' to a directory not ending in $libdir\"\n \n \t  if test -n \"$inst_prefix_dir\"; then\n \t    # Stick the inst_prefix_dir data into the link command.\n@@ -2028,6 +2038,9 @@ func_mode_install ()\n \t    relink_command=`$ECHO \"X$relink_command\" | $Xsed -e \"s%@inst_prefix_dir@%%\"`\n \t  fi\n \n+\t  relink_command=`$ECHO \"$relink_command\" | $SED \"s%-L[[:space:]]*/lib[^[:space:]]*%%\"`\n+\t  relink_command=`$ECHO \"$relink_command\" | $SED \"s%-L[[:space:]]*/usr/lib[^[:space:]]*%%\"`\n+\n \t  func_warning \"relinking \\`$file'\"\n \t  func_show_eval \"$relink_command\" \\\n \t    'func_fatal_error \"error: relink \\`$file'\\'' with the above command before installing it\"'\n@@ -5412,8 +5425,12 @@ func_mode_link ()\n \t    absdir=\"$abs_ladir\"\n \t    libdir=\"$abs_ladir\"\n \t  else\n-\t    dir=\"$libdir\"\n-\t    absdir=\"$libdir\"\n+\t    # Adding 'libdir' from the .la file to our library search paths\n+\t    # breaks crosscompilation horribly.  We cheat here and don't add\n+\t    # it, instead adding the path where we found the .la.  -CL\n+\t    dir=\"$abs_ladir\"\n+\t    absdir=\"$abs_ladir\"\n+\t    libdir=\"$abs_ladir\"\n \t  fi\n \t  test \"X$hardcode_automatic\" = Xyes && avoidtemprpath=yes\n \telse\n@@ -5564,7 +5581,7 @@ func_mode_link ()\n \t  *)\n \t    if test \"$installed\" = no; then\n \t      notinst_deplibs=\"$notinst_deplibs $lib\"\n-\t      need_relink=yes\n+\t      need_relink=no\n \t    fi\n \t    ;;\n \t  esac\n@@ -5768,7 +5785,6 @@ func_mode_link ()\n \t       test \"$hardcode_direct_absolute\" = no; then\n \t      add=\"$libdir/$linklib\"\n \t    elif test \"$hardcode_minus_L\" = yes; then\n-\t      add_dir=\"-L$libdir\"\n \t      add=\"-l$name\"\n \t    elif test \"$hardcode_shlibpath_var\" = yes; then\n \t      case :$finalize_shlibpath: in\n@@ -8052,6 +8068,10 @@ EOF\n \t    # Replace all uninstalled libtool libraries with the installed ones\n \t    newdependency_libs=\n \t    for deplib in $dependency_libs; do\n+\t      # Replacing uninstalled with installed can easily break crosscompilation,\n+\t      # since the installed path is generally the wrong architecture.  -CL\n+\t      newdependency_libs=\"$newdependency_libs $deplib\"\n+\t      continue\n \t      case $deplib in\n \t      *.la)\n \t\tfunc_basename \"$deplib\"\n"
  },
  {
    "path": "tools/libtool/files/libtool-v2.4.patch",
    "content": "--- a/ltmain.sh\n+++ b/ltmain.sh\n@@ -443,7 +443,7 @@ opt_warning=:\n # name if it has been set yet.\n func_echo ()\n {\n-    $ECHO \"$progname: ${opt_mode+$opt_mode: }$*\"\n+    $ECHO \"OpenWrt-$progname-patched-2.4: ${opt_mode+$opt_mode: }$*\"\n }\n \n # func_verbose arg...\n@@ -469,14 +469,14 @@ func_echo_all ()\n # Echo program name prefixed message to standard error.\n func_error ()\n {\n-    $ECHO \"$progname: ${opt_mode+$opt_mode: }\"${1+\"$@\"} 1>&2\n+    $ECHO \"OpenWrt-$progname-patched-2.4: ${opt_mode+$opt_mode: }\"${1+\"$@\"} 1>&2\n }\n \n # func_warning arg...\n # Echo program name prefixed warning message to standard error.\n func_warning ()\n {\n-    $opt_warning && $ECHO \"$progname: ${opt_mode+$opt_mode: }warning: \"${1+\"$@\"} 1>&2\n+    $opt_warning && $ECHO \"OpenWrt-$progname-patched-2.4: ${opt_mode+$opt_mode: }warning: \"${1+\"$@\"} 1>&2\n \n     # bash bug again:\n     :\n@@ -1416,8 +1416,8 @@ func_infer_tag ()\n \t# was found and let the user know that the \"--tag\" command\n \t# line option must be used.\n \tif test -z \"$tagname\"; then\n-\t  func_echo \"unable to infer tagged configuration\"\n-\t  func_fatal_error \"specify a tag with \\`--tag'\"\n+\t  func_echo \"defaulting to \\`CC'\"\n+\t  func_echo \"if this is not correct, specify a tag with \\`--tag'\"\n #\telse\n #\t  func_verbose \"using $tagname tagged configuration\"\n \tfi\n@@ -2953,8 +2953,15 @@ func_mode_install ()\n \tfunc_append dir \"$objdir\"\n \n \tif test -n \"$relink_command\"; then\n+\t  # Strip any trailing slash from the destination.\n+\t  func_stripname '' '/' \"$libdir\"\n+\t  s_libdir=$func_stripname_result\n+\n+\t  func_stripname '' '/' \"$destdir\"\n+\t  s_destdir=$func_stripname_result\n+\n \t  # Determine the prefix the user has applied to our future dir.\n-\t  inst_prefix_dir=`$ECHO \"$destdir\" | $SED -e \"s%$libdir\\$%%\"`\n+\t  inst_prefix_dir=`$ECHO \"$s_destdir\" | $SED -e \"s%$s_libdir\\$%%\"`\n \n \t  # Don't allow the user to place us outside of our expected\n \t  # location b/c this prevents finding dependent libraries that\n@@ -2962,8 +2969,11 @@ func_mode_install ()\n \t  # At present, this check doesn't affect windows .dll's that\n \t  # are installed into $libdir/../bin (currently, that works fine)\n \t  # but it's something to keep an eye on.\n-\t  test \"$inst_prefix_dir\" = \"$destdir\" && \\\n-\t    func_fatal_error \"error: cannot install \\`$file' to a directory not ending in $libdir\"\n+\t  #\n+\t  # This breaks install into our staging area.  -PB\n+\t  #\n+\t  # test \"$inst_prefix_dir\" = \"$destdir\" && \\\n+\t  #   func_fatal_error \"error: cannot install \\`$file' to a directory not ending in $libdir\"\n \n \t  if test -n \"$inst_prefix_dir\"; then\n \t    # Stick the inst_prefix_dir data into the link command.\n@@ -2972,6 +2982,9 @@ func_mode_install ()\n \t    relink_command=`$ECHO \"$relink_command\" | $SED \"s%@inst_prefix_dir@%%\"`\n \t  fi\n \n+\t  relink_command=`$ECHO \"$relink_command\" | $SED \"s%-L[[:space:]]*/lib[^[:space:]]*%%\"`\n+\t  relink_command=`$ECHO \"$relink_command\" | $SED \"s%-L[[:space:]]*/usr/lib[^[:space:]]*%%\"`\n+\n \t  func_warning \"relinking \\`$file'\"\n \t  func_show_eval \"$relink_command\" \\\n \t    'func_fatal_error \"error: relink \\`$file'\\'' with the above command before installing it\"'\n@@ -6504,8 +6517,12 @@ func_mode_link ()\n \t    absdir=\"$abs_ladir\"\n \t    libdir=\"$abs_ladir\"\n \t  else\n-\t    dir=\"$lt_sysroot$libdir\"\n-\t    absdir=\"$lt_sysroot$libdir\"\n+\t    # Adding 'libdir' from the .la file to our library search paths\n+\t    # breaks crosscompilation horribly.  We cheat here and don't add\n+\t    # it, instead adding the path where we found the .la.  -CL\n+\t    dir=\"$lt_sysroot$abs_ladir\"\n+\t    absdir=\"$abs_ladir\"\n+\t    libdir=\"$abs_ladir\"\n \t  fi\n \t  test \"X$hardcode_automatic\" = Xyes && avoidtemprpath=yes\n \telse\n@@ -6683,7 +6700,7 @@ func_mode_link ()\n \t  *)\n \t    if test \"$installed\" = no; then\n \t      func_append notinst_deplibs \" $lib\"\n-\t      need_relink=yes\n+\t      need_relink=no\n \t    fi\n \t    ;;\n \t  esac\n@@ -6887,7 +6904,6 @@ func_mode_link ()\n \t       test \"$hardcode_direct_absolute\" = no; then\n \t      add=\"$libdir/$linklib\"\n \t    elif test \"$hardcode_minus_L\" = yes; then\n-\t      add_dir=\"-L$libdir\"\n \t      add=\"-l$name\"\n \t    elif test \"$hardcode_shlibpath_var\" = yes; then\n \t      case :$finalize_shlibpath: in\n@@ -6903,8 +6919,6 @@ func_mode_link ()\n \t\tadd=\"$libdir/$linklib\"\n \t      fi\n \t    else\n-\t      # We cannot seem to hardcode it, guess we'll fake it.\n-\t      add_dir=\"-L$libdir\"\n \t      # Try looking first in the location we're being installed to.\n \t      if test -n \"$inst_prefix_dir\"; then\n \t\tcase $libdir in\n@@ -7059,7 +7073,17 @@ func_mode_link ()\n \t\t  fi\n \t\t  ;;\n \t\t*)\n-\t\t  path=\"-L$absdir/$objdir\"\n+\t\t  # OE sets installed=no in staging. We need to look in $objdir and $absdir,\n+\t\t  # preferring $objdir. RP 31/04/2008\n+\t\t  if test -f \"$absdir/$objdir/$depdepl\" ; then\n+\t\t    depdepl=\"$absdir/$objdir/$depdepl\"\n+\t\t    path=\"-L$absdir/$objdir\"\n+\t\t  elif test -f \"$absdir/$depdepl\" ; then\n+\t\t    depdepl=\"$absdir/$depdepl\"\n+\t\t    path=\"-L$absdir\"\n+\t\t  else\n+\t\t    path=\"-L$absdir/$objdir\"\n+\t\t  fi\n \t\t  ;;\n \t\tesac\n \t\telse\n@@ -8050,7 +8074,7 @@ EOF\n \t    elif test -n \"$runpath_var\"; then\n \t      case \"$perm_rpath \" in\n \t      *\" $libdir \"*) ;;\n-\t      *) func_apped perm_rpath \" $libdir\" ;;\n+\t      *) func_append perm_rpath \" $libdir\" ;;\n \t      esac\n \t    fi\n \t  done\n@@ -9257,6 +9281,10 @@ EOF\n \t    # Replace all uninstalled libtool libraries with the installed ones\n \t    newdependency_libs=\n \t    for deplib in $dependency_libs; do\n+\t      # Replacing uninstalled with installed can easily break crosscompilation,\n+\t      # since the installed path is generally the wrong architecture.  -CL\n+\t      newdependency_libs=\"$newdependency_libs $deplib\"\n+\t      continue\n \t      case $deplib in\n \t      *.la)\n \t\tfunc_basename \"$deplib\"\n"
  },
  {
    "path": "tools/libtool/patches/000-relocatable.patch",
    "content": "--- a/libltdl/config/general.m4sh\n+++ b/libltdl/config/general.m4sh\n@@ -45,15 +45,22 @@ progpath=\"$0\"\n M4SH_VERBATIM([[\n : ${CP=\"cp -f\"}\n test \"${ECHO+set}\" = set || ECHO=${as_echo-'printf %s\\n'}\n-: ${EGREP=\"@EGREP@\"}\n-: ${FGREP=\"@FGREP@\"}\n-: ${GREP=\"@GREP@\"}\n : ${LN_S=\"@LN_S@\"}\n : ${MAKE=\"make\"}\n : ${MKDIR=\"mkdir\"}\n : ${MV=\"mv -f\"}\n : ${RM=\"rm -f\"}\n-: ${SED=\"@SED@\"}\n+if test -n \"$STAGING_DIR\"; then\n+\t: ${EGREP=\"$STAGING_DIR/../host/bin/grep -E\"}\n+\t: ${FGREP=\"$STAGING_DIR/../host/bin/grep -F\"}\n+\t: ${GREP=\"$STAGING_DIR/../host/bin/grep\"}\n+\t: ${SED=\"$STAGING_DIR/../host/bin/sed\"}\n+else\n+\t: ${EGREP=\"@EGREP@\"}\n+\t: ${FGREP=\"@FGREP@\"}\n+\t: ${GREP=\"@GREP@\"}\n+\t: ${SED=\"@SED@\"}\n+fi\n : ${SHELL=\"${CONFIG_SHELL-/bin/sh}\"}\n : ${Xsed=\"$SED -e 1s/^X//\"}\n \n--- a/libtoolize.in\n+++ b/libtoolize.in\n@@ -334,15 +334,22 @@ as_unset=as_fn_unset\n \n : ${CP=\"cp -f\"}\n test \"${ECHO+set}\" = set || ECHO=${as_echo-'printf %s\\n'}\n-: ${EGREP=\"@EGREP@\"}\n-: ${FGREP=\"@FGREP@\"}\n-: ${GREP=\"@GREP@\"}\n : ${LN_S=\"@LN_S@\"}\n : ${MAKE=\"make\"}\n : ${MKDIR=\"mkdir\"}\n : ${MV=\"mv -f\"}\n : ${RM=\"rm -f\"}\n-: ${SED=\"@SED@\"}\n+if test -n \"$STAGING_DIR\"; then\n+\t: ${EGREP=\"$STAGING_DIR/../host/bin/grep -E\"}\n+\t: ${FGREP=\"$STAGING_DIR/../host/bin/grep -F\"}\n+\t: ${GREP=\"$STAGING_DIR/../host/bin/grep\"}\n+\t: ${SED=\"$STAGING_DIR/../host/bin/sed\"}\n+else\n+\t: ${EGREP=\"@EGREP@\"}\n+\t: ${FGREP=\"@FGREP@\"}\n+\t: ${GREP=\"@GREP@\"}\n+\t: ${SED=\"@SED@\"}\n+fi\n : ${SHELL=\"${CONFIG_SHELL-/bin/sh}\"}\n : ${Xsed=\"$SED -e 1s/^X//\"}\n \n@@ -2487,10 +2494,17 @@ func_check_macros ()\n \n   # Locations for important files:\n   prefix=@prefix@\n-  datadir=@datadir@\n-  pkgdatadir=@pkgdatadir@\n-  pkgltdldir=@pkgdatadir@\n-  aclocaldir=@aclocaldir@\n+  if test -n \"$STAGING_DIR\"; then\n+    datadir=\"$STAGING_DIR/../host/share\"\n+    pkgdatadir=\"$STAGING_DIR/../host/share/libtool\"\n+    pkgltdldir=\"$STAGING_DIR/../host/share/libtool\"\n+    aclocaldir=\"$STAGING_DIR/../host/share/aclocal\"\n+  else\n+    datadir=@datadir@\n+    pkgdatadir=@pkgdatadir@\n+    pkgltdldir=@pkgdatadir@\n+    aclocaldir=@aclocaldir@\n+  fi\n   auxdir=\n   macrodir=\n   configure_ac=configure.in\n--- a/libtoolize.m4sh\n+++ b/libtoolize.m4sh\n@@ -1453,10 +1453,17 @@ func_check_macros ()\n \n   # Locations for important files:\n   prefix=@prefix@\n-  datadir=@datadir@\n-  pkgdatadir=@pkgdatadir@\n-  pkgltdldir=@pkgdatadir@\n-  aclocaldir=@aclocaldir@\n+  if test -n \"$STAGING_DIR\"; then\n+    datadir=\"$STAGING_DIR/../host/share\"\n+    pkgdatadir=\"$STAGING_DIR/../host/share/libtool\"\n+    pkgltdldir=\"$STAGING_DIR/../host/share/libtool\"\n+    aclocaldir=\"$STAGING_DIR/../host/share/aclocal\"\n+  else\n+    datadir=@datadir@\n+    pkgdatadir=@pkgdatadir@\n+    pkgltdldir=@pkgdatadir@\n+    aclocaldir=@aclocaldir@\n+  fi\n   auxdir=\n   macrodir=\n   configure_ac=configure.in\n--- a/libltdl/m4/libtool.m4\n+++ b/libltdl/m4/libtool.m4\n@@ -907,9 +907,8 @@ dnl AC_DEFUN([AC_LIBTOOL_RC], [])\n # ----------------\n m4_defun([_LT_TAG_COMPILER],\n [AC_REQUIRE([AC_PROG_CC])dnl\n-\n _LT_DECL([LTCC], [CC], [1], [A C compiler])dnl\n-_LT_DECL([LTCFLAGS], [CFLAGS], [1], [LTCC compiler flags])dnl\n+_LT_DECL([LTCFLAGS], [CFLAGS], [\"-O2 -I\\${STAGING_DIR:-$STAGING_DIR}/../host/include\"], [LTCC compiler flags])dnl\n _LT_TAGDECL([CC], [compiler], [1], [A language specific compiler])dnl\n _LT_TAGDECL([with_gcc], [GCC], [0], [Is the compiler the GNU compiler?])dnl\n \n@@ -7660,9 +7659,9 @@ m4_defun([_LT_DECL_EGREP],\n [AC_REQUIRE([AC_PROG_EGREP])dnl\n AC_REQUIRE([AC_PROG_FGREP])dnl\n test -z \"$GREP\" && GREP=grep\n-_LT_DECL([], [GREP], [1], [A grep program that handles long lines])\n-_LT_DECL([], [EGREP], [1], [An ERE matcher])\n-_LT_DECL([], [FGREP], [1], [A literal string matcher])\n+_LT_DECL([], [GREP], [\"\\${STAGING_DIR:-$STAGING_DIR}/../host/bin/grep\"], [A grep program that handles long lines])\n+_LT_DECL([], [EGREP], [\"\\${STAGING_DIR:-$STAGING_DIR}/../host/bin/grep -E\"], [An ERE matcher])\n+_LT_DECL([], [FGREP], [\"\\${STAGING_DIR:-$STAGING_DIR}/../host/bin/grep -F\"], [A literal string matcher])\n dnl Non-bleeding-edge autoconf doesn't subst GREP, so do it here too\n AC_SUBST([GREP])\n ])\n@@ -7695,9 +7694,8 @@ AC_SUBST([DLLTOOL])\n # as few characters as possible.  Prefer GNU sed if found.\n m4_defun([_LT_DECL_SED],\n [AC_PROG_SED\n-test -z \"$SED\" && SED=sed\n Xsed=\"$SED -e 1s/^X//\"\n-_LT_DECL([], [SED], [1], [A sed program that does not truncate output])\n+_LT_DECL([], [SED], [\"\\${STAGING_DIR:-$STAGING_DIR}/../host/bin/sed\"], [A sed program that does not truncate output])\n _LT_DECL([], [Xsed], [\"\\$SED -e 1s/^X//\"],\n     [Sed that helps us avoid accidentally triggering echo(1) options like -n])\n ])# _LT_DECL_SED\n"
  },
  {
    "path": "tools/libtool/patches/100-libdir-fixes.patch",
    "content": "--- a/libltdl/config/ltmain.m4sh\n+++ b/libltdl/config/ltmain.m4sh\n@@ -5731,8 +5731,14 @@ func_mode_link ()\n \t    absdir=\"$abs_ladir\"\n \t    libdir=\"$abs_ladir\"\n \t  else\n-\t    dir=\"$lt_sysroot$libdir\"\n-\t    absdir=\"$lt_sysroot$libdir\"\n+\t    # Adding 'libdir' from the .la file to our library search paths\n+\t    # breaks crosscompilation horribly.  We cheat here and don't add\n+\t    # it, instead adding the path where we found the .la.  -CL\n+\t    dir=\"$lt_sysroot$abs_ladir\"\n+\t    absdir=\"$abs_ladir\"\n+\t    libdir=\"$abs_ladir\"\n+\t    #dir=\"$libdir\"\n+\t    #absdir=\"$lt_sysroot$libdir\"\n \t  fi\n \t  test \"X$hardcode_automatic\" = Xyes && avoidtemprpath=yes\n \telse\n@@ -6130,8 +6136,6 @@ func_mode_link ()\n \t\tadd=\"$libdir/$linklib\"\n \t      fi\n \t    else\n-\t      # We cannot seem to hardcode it, guess we'll fake it.\n-\t      add_dir=\"-L$libdir\"\n \t      # Try looking first in the location we're being installed to.\n \t      if test -n \"$inst_prefix_dir\"; then\n \t\tcase $libdir in\n@@ -6286,7 +6290,17 @@ func_mode_link ()\n \t\t  fi\n \t\t  ;;\n \t\t*)\n-\t\t  path=\"-L$absdir/$objdir\"\n+                  # OE sets installed=no in staging. We need to look in $objdir and $absdir, \n+                  # preferring $objdir. RP 31/04/2008\n+                  if test -f \"$absdir/$objdir/$depdepl\" ; then\n+\t\t    depdepl=\"$absdir/$objdir/$depdepl\"\n+\t\t    path=\"-L$absdir/$objdir\"\n+                  elif test -f \"$absdir/$depdepl\" ; then\n+\t\t    depdepl=\"$absdir/$depdepl\"\n+\t\t    path=\"-L$absdir\"\n+                  else\n+\t\t    path=\"-L$absdir/$objdir\"\n+                  fi\n \t\t  ;;\n \t\tesac\n \t\telse\n--- a/libltdl/config/ltmain.sh\n+++ b/libltdl/config/ltmain.sh\n@@ -6518,8 +6518,14 @@ func_mode_link ()\n \t    absdir=\"$abs_ladir\"\n \t    libdir=\"$abs_ladir\"\n \t  else\n-\t    dir=\"$lt_sysroot$libdir\"\n-\t    absdir=\"$lt_sysroot$libdir\"\n+\t    # Adding 'libdir' from the .la file to our library search paths\n+\t    # breaks crosscompilation horribly.  We cheat here and don't add\n+\t    # it, instead adding the path where we found the .la.  -CL\n+\t    dir=\"$lt_sysroot$abs_ladir\"\n+\t    absdir=\"$abs_ladir\"\n+\t    libdir=\"$abs_ladir\"\n+\t    #dir=\"$libdir\"\n+\t    #absdir=\"$lt_sysroot$libdir\"\n \t  fi\n \t  test \"X$hardcode_automatic\" = Xyes && avoidtemprpath=yes\n \telse\n@@ -6917,8 +6923,6 @@ func_mode_link ()\n \t\tadd=\"$libdir/$linklib\"\n \t      fi\n \t    else\n-\t      # We cannot seem to hardcode it, guess we'll fake it.\n-\t      add_dir=\"-L$libdir\"\n \t      # Try looking first in the location we're being installed to.\n \t      if test -n \"$inst_prefix_dir\"; then\n \t\tcase $libdir in\n@@ -7073,7 +7077,17 @@ func_mode_link ()\n \t\t  fi\n \t\t  ;;\n \t\t*)\n-\t\t  path=\"-L$absdir/$objdir\"\n+                  # OE sets installed=no in staging. We need to look in $objdir and $absdir, \n+                  # preferring $objdir. RP 31/04/2008\n+                  if test -f \"$absdir/$objdir/$depdepl\" ; then\n+\t\t    depdepl=\"$absdir/$objdir/$depdepl\"\n+\t\t    path=\"-L$absdir/$objdir\"\n+                  elif test -f \"$absdir/$depdepl\" ; then\n+\t\t    depdepl=\"$absdir/$depdepl\"\n+\t\t    path=\"-L$absdir\"\n+                  else\n+\t\t    path=\"-L$absdir/$objdir\"\n+                  fi\n \t\t  ;;\n \t\tesac\n \t\telse\n"
  },
  {
    "path": "tools/libtool/patches/110-dont-use-target-dir-for-relinking.patch",
    "content": "--- a/libltdl/config/ltmain.m4sh\n+++ b/libltdl/config/ltmain.m4sh\n@@ -6120,7 +6120,6 @@ func_mode_link ()\n \t       test \"$hardcode_direct_absolute\" = no; then\n \t      add=\"$libdir/$linklib\"\n \t    elif test \"$hardcode_minus_L\" = yes; then\n-\t      add_dir=\"-L$libdir\"\n \t      add=\"-l$name\"\n \t    elif test \"$hardcode_shlibpath_var\" = yes; then\n \t      case :$finalize_shlibpath: in\n--- a/libltdl/config/ltmain.sh\n+++ b/libltdl/config/ltmain.sh\n@@ -6907,7 +6907,6 @@ func_mode_link ()\n \t       test \"$hardcode_direct_absolute\" = no; then\n \t      add=\"$libdir/$linklib\"\n \t    elif test \"$hardcode_minus_L\" = yes; then\n-\t      add_dir=\"-L$libdir\"\n \t      add=\"-l$name\"\n \t    elif test \"$hardcode_shlibpath_var\" = yes; then\n \t      case :$finalize_shlibpath: in\n"
  },
  {
    "path": "tools/libtool/patches/120-strip-unsafe-dirs-for-relinking.patch",
    "content": "--- a/libltdl/config/ltmain.m4sh\n+++ b/libltdl/config/ltmain.m4sh\n@@ -2183,6 +2183,9 @@ func_mode_install ()\n \t    relink_command=`$ECHO \"$relink_command\" | $SED \"s%@inst_prefix_dir@%%\"`\n \t  fi\n \n+\t  relink_command=`$ECHO \"$relink_command\" | $SED \"s%-L[[:space:]]*/lib[^[:space:]]*%%\"`\n+\t  relink_command=`$ECHO \"$relink_command\" | $SED \"s%-L[[:space:]]*/usr/lib[^[:space:]]*%%\"`\n+\n \t  func_warning \"relinking \\`$file'\"\n \t  func_show_eval \"$relink_command\" \\\n \t    'func_fatal_error \"error: relink \\`$file'\\'' with the above command before installing it\"'\n--- a/libltdl/config/ltmain.sh\n+++ b/libltdl/config/ltmain.sh\n@@ -2973,6 +2973,9 @@ func_mode_install ()\n \t    relink_command=`$ECHO \"$relink_command\" | $SED \"s%@inst_prefix_dir@%%\"`\n \t  fi\n \n+\t  relink_command=`$ECHO \"$relink_command\" | $SED \"s%-L[[:space:]]*/lib[^[:space:]]*%%\"`\n+\t  relink_command=`$ECHO \"$relink_command\" | $SED \"s%-L[[:space:]]*/usr/lib[^[:space:]]*%%\"`\n+\n \t  func_warning \"relinking \\`$file'\"\n \t  func_show_eval \"$relink_command\" \\\n \t    'func_fatal_error \"error: relink \\`$file'\\'' with the above command before installing it\"'\n"
  },
  {
    "path": "tools/libtool/patches/150-trailingslash.patch",
    "content": "A command like /bin/sh ../../i586-poky-linux-libtool   --mode=install /usr/bin/install -c   gck-roots-store-standalone.la '/media/data1/builds/poky1/tmp/work/core2-poky-linux/gnome-keyring-2.26.1-r1/image/usr/lib/gnome-keyring/standalone/' fails (e.g. gnome-keyring or pulseaudio)\n\nThis is because libdir has a trailing slash which breaks the comparision.\n\nRP 2/1/10\n\nMerged a patch received from Gary Thomas <gary@mlbassoc.com>\n\nDate: 2010/07/12\nNitin A Kamble <nitin.a.kamble@intel.com>\n\n--- a/libltdl/config/ltmain.m4sh\n+++ b/libltdl/config/ltmain.m4sh\n@@ -2167,8 +2167,15 @@ func_mode_install ()\n \tfunc_append dir \"$objdir\"\n \n \tif test -n \"$relink_command\"; then\n+      # Strip any trailing slash from the destination.\n+      func_stripname '' '/' \"$libdir\"\n+      destlibdir=$func_stripname_result\n+\n+      func_stripname '' '/' \"$destdir\"\n+      s_destdir=$func_stripname_result\n+\n \t  # Determine the prefix the user has applied to our future dir.\n-\t  inst_prefix_dir=`$ECHO \"$destdir\" | $SED -e \"s%$libdir\\$%%\"`\n+\t  inst_prefix_dir=`$ECHO \"X$s_destdir\" | $Xsed -e \"s%$destlibdir\\$%%\"`\n \n \t  # Don't allow the user to place us outside of our expected\n \t  # location b/c this prevents finding dependent libraries that\n--- a/libltdl/config/ltmain.sh\n+++ b/libltdl/config/ltmain.sh\n@@ -2954,8 +2954,15 @@ func_mode_install ()\n \tfunc_append dir \"$objdir\"\n \n \tif test -n \"$relink_command\"; then\n+      # Strip any trailing slash from the destination.\n+      func_stripname '' '/' \"$libdir\"\n+      destlibdir=$func_stripname_result\n+\n+      func_stripname '' '/' \"$destdir\"\n+      s_destdir=$func_stripname_result\n+\n \t  # Determine the prefix the user has applied to our future dir.\n-\t  inst_prefix_dir=`$ECHO \"$destdir\" | $SED -e \"s%$libdir\\$%%\"`\n+\t  inst_prefix_dir=`$ECHO \"X$s_destdir\" | $Xsed -e \"s%$destlibdir\\$%%\"`\n \n \t  # Don't allow the user to place us outside of our expected\n \t  # location b/c this prevents finding dependent libraries that\n"
  },
  {
    "path": "tools/libtool/patches/160-passthrough-ssp.patch",
    "content": "diff -ur libtool-2.4.orig/libltdl/config/ltmain.m4sh libtool-2.4/libltdl/config/ltmain.m4sh\n--- libtool-2.4.orig/libltdl/config/ltmain.m4sh\t2015-06-18 10:46:15.499996979 +0200\n+++ libtool-2.4/libltdl/config/ltmain.m4sh\t2015-06-18 10:48:24.686882213 +0200\n@@ -5076,7 +5076,7 @@\n       # -O*, -flto*, -fwhopr*, -fuse-linker-plugin GCC link-time optimization\n       -64|-mips[0-9]|-r[0-9][0-9]*|-xarch=*|-xtarget=*|+DA*|+DD*|-q*|-m*| \\\n       -t[45]*|-txscale*|-p|-pg|--coverage|-fprofile-*|-F*|@*|-tp=*|--sysroot=*| \\\n-      -O*|-flto*|-fwhopr*|-fuse-linker-plugin)\n+      -O*|-flto*|-fwhopr*|-fuse-linker-plugin|-fstack-protector*)\n         func_quote_for_eval \"$arg\"\n \targ=\"$func_quote_for_eval_result\"\n         func_append compile_command \" $arg\"\n"
  },
  {
    "path": "tools/libtool/patches/200-openwrt-branding.patch",
    "content": "--- a/libltdl/config/general.m4sh\n+++ b/libltdl/config/general.m4sh\n@@ -359,7 +359,7 @@ opt_warning=:\n # name if it has been set yet.\n func_echo ()\n {\n-    $ECHO \"$progname: ${opt_mode+$opt_mode: }$*\"\n+    $ECHO \"OpenWrt-$progname: ${opt_mode+$opt_mode: }$*\"\n }\n \n # func_verbose arg...\n@@ -385,14 +385,14 @@ func_echo_all ()\n # Echo program name prefixed message to standard error.\n func_error ()\n {\n-    $ECHO \"$progname: ${opt_mode+$opt_mode: }\"${1+\"$@\"} 1>&2\n+    $ECHO \"OpenWrt-$progname: ${opt_mode+$opt_mode: }\"${1+\"$@\"} 1>&2\n }\n \n # func_warning arg...\n # Echo program name prefixed warning message to standard error.\n func_warning ()\n {\n-    $opt_warning && $ECHO \"$progname: ${opt_mode+$opt_mode: }warning: \"${1+\"$@\"} 1>&2\n+    $opt_warning && $ECHO \"OpenWrt-$progname: ${opt_mode+$opt_mode: }warning: \"${1+\"$@\"} 1>&2\n \n     # bash bug again:\n     :\n--- a/libltdl/config/ltmain.sh\n+++ b/libltdl/config/ltmain.sh\n@@ -439,7 +439,7 @@ opt_warning=:\n # name if it has been set yet.\n func_echo ()\n {\n-    $ECHO \"$progname: ${opt_mode+$opt_mode: }$*\"\n+    $ECHO \"OpenWrt-$progname: ${opt_mode+$opt_mode: }$*\"\n }\n \n # func_verbose arg...\n@@ -465,14 +465,14 @@ func_echo_all ()\n # Echo program name prefixed message to standard error.\n func_error ()\n {\n-    $ECHO \"$progname: ${opt_mode+$opt_mode: }\"${1+\"$@\"} 1>&2\n+    $ECHO \"OpenWrt-$progname: ${opt_mode+$opt_mode: }\"${1+\"$@\"} 1>&2\n }\n \n # func_warning arg...\n # Echo program name prefixed warning message to standard error.\n func_warning ()\n {\n-    $opt_warning && $ECHO \"$progname: ${opt_mode+$opt_mode: }warning: \"${1+\"$@\"} 1>&2\n+    $opt_warning && $ECHO \"OpenWrt-$progname: ${opt_mode+$opt_mode: }warning: \"${1+\"$@\"} 1>&2\n \n     # bash bug again:\n     :\n--- a/libtoolize.in\n+++ b/libtoolize.in\n@@ -648,7 +648,7 @@ opt_warning=:\n # name if it has been set yet.\n func_echo ()\n {\n-    $ECHO \"$progname: ${opt_mode+$opt_mode: }$*\"\n+    $ECHO \"OpenWrt-$progname: ${opt_mode+$opt_mode: }$*\"\n }\n \n # func_verbose arg...\n@@ -674,14 +674,14 @@ func_echo_all ()\n # Echo program name prefixed message to standard error.\n func_error ()\n {\n-    $ECHO \"$progname: ${opt_mode+$opt_mode: }\"${1+\"$@\"} 1>&2\n+    $ECHO \"OpenWrt-$progname: ${opt_mode+$opt_mode: }\"${1+\"$@\"} 1>&2\n }\n \n # func_warning arg...\n # Echo program name prefixed warning message to standard error.\n func_warning ()\n {\n-    $opt_warning && $ECHO \"$progname: ${opt_mode+$opt_mode: }warning: \"${1+\"$@\"} 1>&2\n+    $opt_warning && $ECHO \"OpenWrt-$progname: ${opt_mode+$opt_mode: }warning: \"${1+\"$@\"} 1>&2\n \n     # bash bug again:\n     :\n--- a/tests/defs.in\n+++ b/tests/defs.in\n@@ -596,7 +596,7 @@ opt_warning=:\n # name if it has been set yet.\n func_echo ()\n {\n-    $ECHO \"$progname: ${opt_mode+$opt_mode: }$*\"\n+    $ECHO \"OpenWrt-$progname: ${opt_mode+$opt_mode: }$*\"\n }\n \n # func_verbose arg...\n@@ -622,14 +622,14 @@ func_echo_all ()\n # Echo program name prefixed message to standard error.\n func_error ()\n {\n-    $ECHO \"$progname: ${opt_mode+$opt_mode: }\"${1+\"$@\"} 1>&2\n+    $ECHO \"OpenWrt-$progname: ${opt_mode+$opt_mode: }\"${1+\"$@\"} 1>&2\n }\n \n # func_warning arg...\n # Echo program name prefixed warning message to standard error.\n func_warning ()\n {\n-    $opt_warning && $ECHO \"$progname: ${opt_mode+$opt_mode: }warning: \"${1+\"$@\"} 1>&2\n+    $opt_warning && $ECHO \"OpenWrt-$progname: ${opt_mode+$opt_mode: }warning: \"${1+\"$@\"} 1>&2\n \n     # bash bug again:\n     :\n"
  },
  {
    "path": "tools/llvm-bpf/Makefile",
    "content": "#\n# Copyright (C) 2006-2016 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=llvm-project\nPKG_VERSION:=13.0.0\nPKG_RELEASE:=1\n\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).src.tar.xz\nPKG_SOURCE_URL:=https://github.com/llvm/llvm-project/releases/download/llvmorg-$(PKG_VERSION)\nPKG_HASH:=6075ad30f1ac0e15f07c1bf062c1e1268c241d674f11bd32cdf0e040c71f2bf3\n\nHOST_BUILD_DIR:=$(BUILD_DIR_HOST)/$(PKG_NAME)-$(PKG_VERSION).src\n\nHOST_BUILD_PARALLEL:=1\n\nCMAKE_BINARY_SUBDIR := build\nCMAKE_SOURCE_SUBDIR := llvm\n\ninclude $(INCLUDE_DIR)/host-build.mk\ninclude $(INCLUDE_DIR)/cmake.mk\n\nLLVM_BPF_PREFIX = llvm-bpf-$(PKG_VERSION).$(HOST_OS)-$(HOST_ARCH)\n\nCMAKE_HOST_INSTALL_PREFIX = $(STAGING_DIR_HOST)/$(LLVM_BPF_PREFIX)\n\nCMAKE_HOST_OPTIONS += \\\n\t-DLLVM_ENABLE_BINDINGS=OFF \\\n\t-DLLVM_INCLUDE_DOCS=OFF \\\n\t-DLLVM_INCLUDE_EXAMPLES=OFF \\\n\t-DLLVM_INCLUDE_TESTS=OFF \\\n\t-DLLVM_ENABLE_PROJECTS=\"clang;lld\" \\\n\t-DLLVM_TARGETS_TO_BUILD=BPF \\\n\t-DCLANG_BUILD_EXAMPLES=OFF \\\n\t-DLLVM_INSTALL_TOOLCHAIN_ONLY=ON \\\n\t-DLLVM_LINK_LLVM_DYLIB=ON \\\n\t-DLLVM_TOOLCHAIN_TOOLS=\"llvm-objcopy;llvm-objdump;llvm-readelf;llvm-strip;llvm-ar;llvm-as;llvm-dis;llvm-link;llvm-nm;llvm-ranlib;llc;opt\" \\\n\t-DCMAKE_SKIP_RPATH=OFF\n\ndefine Host/Install\n\trm -rf $(STAGING_DIR_HOST)/llvm-bpf*\n\t$(Host/Install/Default)\n\tln -s $(LLVM_BPF_PREFIX) $(STAGING_DIR_HOST)/llvm-bpf\n\tSTRIP_KMOD= PATCHELF= STRIP=strip $(SCRIPT_DIR)/rstrip.sh $(STAGING_DIR_HOST)/llvm-bpf\n\techo \"$(PKG_VERSION)\" > $(CMAKE_HOST_INSTALL_PREFIX)/.llvm-version\nendef\n\ndefine Host/Uninstall\n\trm -rf $(STAGING_DIR_HOST)/llvm-bpf*\nendef\n\n$(eval $(call HostBuild))\n"
  },
  {
    "path": "tools/lzma/Makefile",
    "content": "# \n# Copyright (C) 2006 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=lzma\nPKG_VERSION:=4.65\n\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.bz2\nPKG_SOURCE_URL:=@OPENWRT\nPKG_HASH:=dcbdb5f4843eff638e4a5e8be0e2486a3c5483df73c70823618db8e66f609ec2\n\nHOST_BUILD_DIR:=$(BUILD_DIR_HOST)/$(PKG_NAME)-$(PKG_VERSION)\n\ninclude $(INCLUDE_DIR)/host-build.mk\n\nUTIL_DIR=$(HOST_BUILD_DIR)/C/LzmaUtil\nALONE_DIR=$(HOST_BUILD_DIR)/CPP/7zip/Compress/LZMA_Alone\n\ndefine Host/Compile\n\t$(MAKE) -C $(UTIL_DIR) -f makefile.gcc\n\t$(MAKE) -C $(ALONE_DIR) -f makefile.gcc\nendef\n\ndefine Host/Install\n\t$(INSTALL_DIR) $(STAGING_DIR_HOST)/bin\n\t$(INSTALL_BIN) $(HOST_BUILD_DIR)/CPP/7zip/Compress/LZMA_Alone/lzma_alone $(STAGING_DIR_HOST)/bin/lzma\nendef\n\ndefine Host/Clean\nendef\n\n$(eval $(call HostBuild))\n"
  },
  {
    "path": "tools/lzma/patches/001-large_files.patch",
    "content": "Index: lzma-4.65/CPP/7zip/Compress/LZMA_Alone/makefile.gcc\n===================================================================\n--- lzma-4.65.orig/CPP/7zip/Compress/LZMA_Alone/makefile.gcc\t2009-05-15 23:33:51.000000000 +0200\n+++ lzma-4.65/CPP/7zip/Compress/LZMA_Alone/makefile.gcc\t2009-06-01 22:00:54.000000000 +0200\n@@ -3,7 +3,7 @@\n CXX_C = gcc -O2 -Wall\n LIB = -lm\n RM = rm -f\n-CFLAGS = -c\n+CFLAGS = -c -D_FILE_OFFSET_BITS=64\n \n ifdef SystemDrive\n IS_MINGW = 1\n"
  },
  {
    "path": "tools/lzma/patches/002-lzmp.patch",
    "content": "Index: lzma-4.65/CPP/7zip/Compress/LZMA_Alone/lzmp.cpp\n===================================================================\n--- /dev/null\t1970-01-01 00:00:00.000000000 +0000\n+++ lzma-4.65/CPP/7zip/Compress/LZMA_Alone/lzmp.cpp\t2009-06-01 22:01:10.000000000 +0200\n@@ -0,0 +1,895 @@\n+/*\n+ * LZMA command line tool similar to gzip to encode and decode LZMA files.\n+ *\n+ * Copyright (C) 2005 Ville Koskinen\n+ *\n+ * This program is free software; you can redistribute it and/or\n+ * modify it under the terms of the GNU General Public License\n+ * as published by the Free Software Foundation; either version 2\n+ * of the License, or (at your option) any later version.\n+ *\n+ * This program is distributed in the hope that it will be useful,\n+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\n+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n+ * GNU General Public License for more details.\n+ *\n+ * You should have received a copy of the GNU General Public License\n+ * along with this program; if not, write to the Free Software\n+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301,\n+ * USA.\n+ */\n+\n+#include \"../../../Common/MyInitGuid.h\"\n+\n+#include <iostream>\n+using std::cout;\n+using std::cerr;\n+using std::endl;\n+\n+#include <cstdio>\n+#include <cstdlib>\n+#include <cstring>\n+\n+#include <string>\n+using std::string;\n+#include <vector>\n+using std::vector;\n+typedef vector<string> stringVector;\n+\n+#include <unistd.h>\n+#include <getopt.h>\n+#include <signal.h>\n+\n+#include <sys/types.h>\n+#include <sys/stat.h>\n+#include <utime.h>\n+#include <sys/time.h> // futimes()\n+\n+// For Solaris\n+#ifndef HAVE_FUTIMES\n+//#define futimes(fd, tv) futimesat(fd, NULL, tv)\n+#endif\n+\n+#if defined(_WIN32) || defined(OS2) || defined(MSDOS)\n+#include <fcntl.h>\n+#include <io.h>\n+#define MY_SET_BINARY_MODE(file) setmode(fileno(file),O_BINARY)\n+#else\n+#define MY_SET_BINARY_MODE(file)\n+#endif\n+\n+#include \"../../../7zip/Common/FileStreams.h\"\n+\n+#include \"../../../Common/Types.h\"\n+\n+#include \"../../../7zip/Compress/LzmaDecoder.h\"\n+#include \"../../../7zip/Compress/LzmaEncoder.h\"\n+\n+#include \"Exception.h\"\n+\n+#include \"lzma_version.h\"\n+\n+namespace lzma {\n+\n+const char *PROGRAM_VERSION = PACKAGE_VERSION;\n+const char *PROGRAM_COPYRIGHT = \"Copyright (C) 2006 Ville Koskinen\";\n+\n+/* LZMA_Alone switches:\n+    -a{N}:  set compression mode - [0, 2], default: 2 (max)\n+    -d{N}:  set dictionary - [0,28], default: 23 (8MB)\n+    -fb{N}: set number of fast bytes - [5, 255], default: 128\n+    -lc{N}: set number of literal context bits - [0, 8], default: 3\n+    -lp{N}: set number of literal pos bits - [0, 4], default: 0\n+    -pb{N}: set number of pos bits - [0, 4], default: 2\n+    -mf{MF_ID}: set Match Finder: [bt2, bt3, bt4, bt4b, pat2r, pat2,\n+                pat2h, pat3h, pat4h, hc3, hc4], default: bt4\n+*/\n+\n+struct lzma_option {\n+\tshort compression_mode;\t\t\t// -a\n+\tshort dictionary;\t\t\t// -d\n+\tshort fast_bytes;\t\t\t// -fb\n+\twchar_t *match_finder;\t\t\t// -mf\n+\tshort literal_context_bits;\t\t// -lc\n+\tshort literal_pos_bits;\t\t\t// -lp\n+\tshort pos_bits;\t\t\t\t// -pb\n+};\n+\n+/* The following is a mapping from gzip/bzip2 style -1 .. -9 compression modes\n+ * to the corresponding LZMA compression modes. Thanks, Larhzu, for coining\n+ * these. */\n+const lzma_option option_mapping[] = {\n+\t{ 0,  0,  0,    NULL, 0, 0, 0},\t\t// -0 (needed for indexing)\n+\t{ 0, 16, 64,  L\"hc4\", 3, 0, 2},\t\t// -1\n+\t{ 0, 20, 64,  L\"hc4\", 3, 0, 2},\t\t// -2\n+\t{ 1, 19, 64,  L\"bt4\", 3, 0, 2},\t\t// -3\n+\t{ 2, 20, 64,  L\"bt4\", 3, 0, 2},\t\t// -4\n+\t{ 2, 21, 128, L\"bt4\", 3, 0, 2},\t\t// -5\n+\t{ 2, 22, 128, L\"bt4\", 3, 0, 2},\t\t// -6\n+\t{ 2, 23, 128, L\"bt4\", 3, 0, 2},\t\t// -7\n+\t{ 2, 24, 255, L\"bt4\", 3, 0, 2},\t\t// -8\n+\t{ 2, 25, 255, L\"bt4\", 3, 0, 2},\t\t// -9\n+};\n+\n+struct extension_pair {\n+\tchar *from;\n+\tchar *to;\n+};\n+\n+const extension_pair known_extensions[] = {\n+\t{ \".lzma\", \"\" },\n+\t{ \".tlz\", \".tar\" },\n+\t{ NULL, NULL }\n+};\n+\n+/* Sorry, I just happen to like enumerations. */\n+enum PROGRAM_MODE {\n+\tPM_COMPRESS = 0,\n+\tPM_DECOMPRESS,\n+\tPM_TEST,\n+\tPM_HELP,\n+\tPM_LICENSE,\n+\tPM_VERSION\n+};\n+\n+enum {\n+\tSTATUS_OK = 0,\n+\tSTATUS_ERROR = 1,\n+\tSTATUS_WARNING = 2\n+};\n+\n+/* getopt options. */\n+/* struct option { name, has_arg, flag, val } */\n+const struct option long_options[] = {\n+\t{ \"stdout\", 0, 0, 'c' },\n+\t{ \"decompress\", 0, 0, 'd' },\n+\t{ \"compress\", 0, 0, 'z' },\n+\t{ \"keep\", 0, 0, 'k' },\n+\t{ \"force\", 0, 0, 'f' },\n+\t{ \"test\", 0, 0, 't' },\n+\t{ \"suffix\", 1, 0, 'S' },\n+\t{ \"quiet\", 0, 0, 'q' },\n+\t{ \"verbose\", 0, 0, 'v' },\n+\t{ \"help\", 0, 0, 'h' },\n+\t{ \"license\", 0, 0, 'L' },\n+\t{ \"version\", 0, 0, 'V' },\n+\t{ \"fast\", 0, 0, '1' },\n+\t{ \"best\", 0, 0, '9' },\n+\t{ 0, 0, 0, 0 }\n+};\n+\n+/* getopt option string (for the above options). */\n+const char option_string[] = \"cdzkftS:qvhLV123456789A:D:F:\";\n+\n+/* Defaults. */\n+PROGRAM_MODE program_mode = PM_COMPRESS;\n+int\tverbosity\t\t\t= 0;\n+bool\tstdinput\t\t\t= false;\n+bool\tstdoutput\t\t\t= false;\n+bool\tkeep\t\t\t\t= false;\n+bool\tforce\t\t\t\t= false;\n+int\tcompression_mode\t\t= 7;\n+//char\t*suffix\t\t\t\t= strdup(\".lzma\");\n+char\t*suffix\t\t\t\t= strdup(known_extensions[0].from);\n+lzma_option\tadvanced_options \t= { -1, -1, -1, NULL, -1, -1, -1 };\n+\n+void print_help(const char *const argv0)\n+{\n+\t// Help goes to stdout while other messages go to stderr.\n+\tcout << \"\\nlzma \" << PROGRAM_VERSION\n+\t\t<< \" \" << PROGRAM_COPYRIGHT << \"\\n\"\n+\t\t\"Based on LZMA SDK \" << LZMA_SDK_VERSION_STRING << \" \"\n+\t\t<< LZMA_SDK_COPYRIGHT_STRING\n+\t\t<< \"\\n\\nUsage: \" << argv0\n+\t\t<< \" [flags and input files in any order]\\n\"\n+\"  -c --stdout       output to standard output\\n\"\n+\"  -d --decompress   force decompression\\n\"\n+\"  -z --compress     force compression\\n\"\n+\"  -k --keep         keep (don't delete) input files\\n\"\n+\"  -f --force        force overwrite of output file and compress links\\n\"\n+\"  -t --test         test compressed file integrity\\n\"\n+\"  -S .suf  --suffix .suf   use suffix .suf on compressed files\\n\"\n+\"  -q --quiet        suppress error messages\\n\"\n+\"  -v --verbose      be verbose\\n\"\n+\"  -h --help         print this message\\n\"\n+\"  -L --license      display the license information\\n\"\n+\"  -V --version      display version numbers of LZMA SDK and lzma\\n\"\n+\"  -1 .. -2          fast compression\\n\"\n+\"  -3 .. -9          good to excellent compression. -7 is the default.\\n\"\n+\"     --fast         alias for -1\\n\"\n+\"     --best         alias for -9 (usually *not* what you want)\\n\\n\"\n+\"  Memory usage depends a lot on the chosen compression mode -1 .. -9.\\n\"\n+\"  See the man page lzma(1) for details.\\n\\n\";\n+}\n+\n+void print_license(void)\n+{\n+\tcout << \"\\n  LZMA command line tool \" << PROGRAM_VERSION << \" - \"\n+\t\t<< PROGRAM_COPYRIGHT\n+\t\t<< \"\\n  LZMA SDK \" << LZMA_SDK_VERSION_STRING << \" - \"\n+\t\t<< LZMA_SDK_COPYRIGHT_STRING\n+\t\t<< \"\\n  This program is a part of the LZMA utils package.\\n\"\n+\t\t\"  http://tukaani.org/lzma/\\n\\n\"\n+\"  This program is free software; you can redistribute it and/or\\n\"\n+\"  modify it under the terms of the GNU General Public License\\n\"\n+\"  as published by the Free Software Foundation; either version 2\\n\"\n+\"  of the License, or (at your option) any later version.\\n\"\n+\"\\n\"\n+\"  This program is distributed in the hope that it will be useful,\\n\"\n+\"  but WITHOUT ANY WARRANTY; without even the implied warranty of\\n\"\n+\"  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\\n\"\n+\"  GNU General Public License for more details.\\n\"\n+\"\\n\";\n+}\n+\n+void print_version(void)\n+{\n+\tcout << \"LZMA command line tool \" << PROGRAM_VERSION << \"\\n\"\n+\t\t<< \"LZMA SDK \" << LZMA_SDK_VERSION_STRING << \"\\n\";\n+}\n+\n+short str2int (const char *str, const int &min, const int &max)\n+{\n+\tint value = -1;\n+\tchar *endptr = NULL;\n+\tif (str == NULL || str[0] == '\\0')\n+\t\tthrow ArgumentException(\"Invalid integer option\");\n+\tvalue = strtol (str, &endptr, 10);\n+\tif (*endptr != '\\0' || value < min || value > max)\n+\t\tthrow ArgumentException(\"Invalid integer option\");\n+\treturn value;\n+}\n+\n+void parse_options(int argc, char **argv, stringVector &filenames)\n+{\n+\t/* Snatched from getopt(3). */\n+\tint c;\n+\n+\t/* Check how we were called */\n+\t{\n+\t\tchar *p = strrchr (argv[0], '/'); // Remove path prefix, if any\n+\t\tif (p++ == NULL)\n+\t\t\tp = argv[0];\n+\t\tif (strstr (p, \"un\") != NULL) {\n+\t\t\tprogram_mode = PM_DECOMPRESS;\n+\t\t} else if (strstr (p, \"cat\") != NULL) {\n+\t\t\tprogram_mode = PM_DECOMPRESS;\n+\t\t\tstdoutput = true;\n+\t\t}\n+\t}\n+\n+\twhile (-1 != (c = getopt_long(argc, argv, option_string,\n+\t\t\tlong_options, NULL))) {\n+\t\tswitch (c) {\n+\t\t\t// stdout\n+\t\t\tcase 'c':\n+\t\t\t\tstdoutput = true;\n+\t\t\t\tbreak;\n+\n+\t\t\t// decompress\n+\t\t\tcase 'd':\n+\t\t\t\tprogram_mode = PM_DECOMPRESS;\n+\t\t\t\tbreak;\n+\n+\t\t\t// compress\n+\t\t\tcase 'z':\n+\t\t\t\tprogram_mode = PM_COMPRESS;\n+\t\t\t\tbreak;\n+\n+\t\t\t// keep\n+\t\t\tcase 'k':\n+\t\t\t\tkeep = true;\n+\t\t\t\tbreak;\n+\n+\t\t\t// force\n+\t\t\tcase 'f':\n+\t\t\t\tforce = true;\n+\t\t\t\tbreak;\n+\n+\t\t\t// test\n+\t\t\tcase 't':\n+\t\t\t\tprogram_mode = PM_TEST;\n+\t\t\t\tbreak;\n+\n+\t\t\t// suffix\n+\t\t\tcase 'S':\n+\t\t\t\tif (optarg) {\n+\t\t\t\t\tfree(suffix);\n+\t\t\t\t\tsuffix = strdup(optarg);\n+\t\t\t\t}\n+\t\t\t\tbreak;\n+\n+\t\t\t// quiet\n+\t\t\tcase 'q':\n+\t\t\t\tverbosity = 0;\n+\t\t\t\tbreak;\n+\n+\t\t\t// verbose\n+\t\t\tcase 'v':\n+\t\t\t\tverbosity++;\n+\t\t\t\tbreak;\n+\n+\t\t\t// help\n+\t\t\tcase 'h':\n+\t\t\t\tprogram_mode = PM_HELP;\n+\t\t\t\tbreak;\n+\n+\t\t\t// license\n+\t\t\tcase 'L':\n+\t\t\t\tprogram_mode = PM_LICENSE;\n+\t\t\t\tbreak;\n+\n+\t\t\t// version\n+\t\t\tcase 'V':\n+\t\t\t\tprogram_mode = PM_VERSION;\n+\t\t\t\tbreak;\n+\n+\t\t\tcase '1': case '2': case '3': case '4': case '5':\n+\t\t\tcase '6': case '7': case '8': case '9':\n+\t\t\t\tcompression_mode = c - '0';\n+\t\t\t\tbreak;\n+\n+\t\t\t// Advanced options //\n+\t\t\t// Compression mode\n+\t\t\tcase 'A':\n+\t\t\t\tadvanced_options.compression_mode =\n+\t\t\t\t\t\tstr2int (optarg, 0, 2);\n+\t\t\t\tbreak;\n+\n+\t\t\t// Dictionary size\n+\t\t\tcase 'D':\n+\t\t\t\tadvanced_options.dictionary =\n+\t\t\t\t\t\tstr2int (optarg, 0, 28);\n+\t\t\t\tbreak;\n+\n+\t\t\t// Fast bytes\n+\t\t\tcase 'F':\n+\t\t\t\tadvanced_options.fast_bytes =\n+\t\t\t\t\t\tstr2int (optarg, 0, 273);\n+\t\t\t\tbreak;\n+\n+\t\t\tdefault:\n+\t\t\t\tthrow ArgumentException(\"\");\n+\t\t\t\tbreak;\n+\t\t} // switch(c)\n+\t} // while(1)\n+\n+\tfor (int i = optind; i < argc; i++) {\n+\t\tif (strcmp(\"-\", argv[i]) == 0)\n+\t\t\tcontinue;\n+\t\tfilenames.push_back(argv[i]);\n+\t}\n+} // parse_options\n+\n+void set_encoder_properties(NCompress::NLzma::CEncoder *encoder,\n+\t\tlzma_option &opt)\n+{\n+\t/* Almost verbatim from LzmaAlone.cpp. */\n+\t    PROPID propIDs[] =\n+\t{\n+\t\tNCoderPropID::kDictionarySize,\n+\t\tNCoderPropID::kPosStateBits,\n+\t\tNCoderPropID::kLitContextBits,\n+\t\tNCoderPropID::kLitPosBits,\n+\t\tNCoderPropID::kAlgorithm,\n+\t\tNCoderPropID::kNumFastBytes,\n+\t\tNCoderPropID::kMatchFinder,\n+\t\tNCoderPropID::kEndMarker\n+\t};\n+\tconst int kNumProps = sizeof(propIDs) / sizeof(propIDs[0]);\n+#define VALUE(x) (advanced_options.x >= 0 ? advanced_options.x : opt.x)\n+\tPROPVARIANT properties[kNumProps];\n+\tfor (int p = 0; p < 6; p++)\n+\t\tproperties[p].vt = VT_UI4;\n+\tproperties[0].ulVal = UInt32(1 << VALUE (dictionary));\n+\tproperties[1].ulVal = UInt32(VALUE (pos_bits));\n+\tproperties[2].ulVal = UInt32(VALUE (literal_context_bits));\n+\tproperties[3].ulVal = UInt32(VALUE (literal_pos_bits));\n+\tproperties[4].ulVal = UInt32(VALUE (compression_mode));\n+\tproperties[5].ulVal = UInt32(VALUE (fast_bytes));\n+#undef VALUE\n+\n+\tproperties[6].vt = VT_BSTR;\n+\tproperties[6].bstrVal = (BSTR)opt.match_finder;\n+\n+\tproperties[7].vt = VT_BOOL;\n+\tproperties[7].boolVal = stdinput ? VARIANT_TRUE : VARIANT_FALSE;\n+\n+\tif (encoder->SetCoderProperties(propIDs, properties, kNumProps) != S_OK)\n+\t\tthrow Exception(\"SetCoderProperties() error\");\n+}\n+\n+void encode(NCompress::NLzma::CEncoder *encoderSpec,\n+\t\tCMyComPtr<ISequentialInStream> inStream,\n+\t\tCMyComPtr<ISequentialOutStream> outStream,\n+\t\tlzma_option encoder_options,\n+\t\tUInt64 fileSize)\n+{\n+\tset_encoder_properties(encoderSpec, encoder_options);\n+\n+\tencoderSpec->WriteCoderProperties(outStream);\n+\n+\tfor (int i = 0; i < 8; i++)\n+\t{\n+\t\tByte b = Byte(fileSize >> (8 * i));\n+\t\tif (outStream->Write(&b, sizeof(b), 0) != S_OK)\n+\t\t\tthrow Exception(\"Write error while encoding\");\n+\t}\n+\n+\tHRESULT result = encoderSpec->Code(inStream, outStream, 0, 0, 0);\n+\n+\tif (result == E_OUTOFMEMORY)\n+\t\tthrow Exception(\"Cannot allocate memory\");\n+\telse if (result != S_OK) {\n+\t\tchar buffer[33];\n+\t\tsnprintf(buffer, 33, \"%d\", (unsigned int)result);\n+\t\tthrow Exception(string(\"Encoder error: \") + buffer);\n+\t}\n+}\n+\n+void decode(NCompress::NLzma::CDecoder *decoderSpec,\n+\t\tCMyComPtr<ISequentialInStream> inStream,\n+\t\tCMyComPtr<ISequentialOutStream> outStream)\n+{\n+\tconst UInt32 kPropertiesSize = 5;\n+\tByte properties[kPropertiesSize];\n+\tUInt32 processedSize;\n+\tUInt64 fileSize = 0;\n+\n+\tif (inStream->Read(properties, kPropertiesSize, &processedSize) != S_OK)\n+\t\tthrow Exception(\"Read error\");\n+\tif (processedSize != kPropertiesSize)\n+\t\tthrow Exception(\"Read error\");\n+\tif (decoderSpec->SetDecoderProperties2(properties, kPropertiesSize) != S_OK)\n+\t\tthrow Exception(\"SetDecoderProperties() error\");\n+\n+\tfor (int i = 0; i < 8; i++)\n+\t{\n+\t\tByte b;\n+\n+\t\tif (inStream->Read(&b, sizeof(b), &processedSize) != S_OK)\n+\t\t\tthrow Exception(\"Read error\");\n+\t\tif (processedSize != 1)\n+\t\t\tthrow Exception(\"Read error\");\n+\n+\t\tfileSize |= ((UInt64)b) << (8 * i);\n+\t}\n+\n+\tif (decoderSpec->Code(inStream, outStream, 0, &fileSize, 0) != S_OK)\n+\t\tthrow Exception(\"Decoder error\");\n+}\n+\n+int open_instream(const string infile,\n+\t\tCMyComPtr<ISequentialInStream> &inStream,\n+\t\tUInt64 &fileSize)\n+{\n+\tCInFileStream *inStreamSpec = new CInFileStream;\n+\tinStream = inStreamSpec;\n+\tif (!inStreamSpec->Open(infile.c_str()))\n+\t\tthrow Exception(\"Cannot open input file \" + infile);\n+\n+\tinStreamSpec->File.GetLength(fileSize);\n+\n+\treturn inStreamSpec->File.GetHandle();\n+}\n+\n+int open_outstream(const string outfile,\n+\t\tCMyComPtr<ISequentialOutStream> &outStream)\n+{\n+\tCOutFileStream *outStreamSpec = new COutFileStream;\n+\toutStream = outStreamSpec;\n+\n+\tbool open_by_force = (program_mode == PM_TEST) | force;\n+\n+\tif (!outStreamSpec->Create(outfile.c_str(), open_by_force))\n+\t\tthrow Exception(\"Cannot open output file \" + outfile);\n+\n+\treturn outStreamSpec->File.GetHandle();\n+}\n+\n+double get_ratio(int inhandle, int outhandle)\n+{\n+\tstruct stat in_stats, out_stats;\n+\tfstat(inhandle, &in_stats);\n+\tfstat(outhandle, &out_stats);\n+\n+\treturn (double)out_stats.st_size / (double)in_stats.st_size;\n+}\n+\n+mode_t get_file_mode(string filename)\n+{\n+\tstruct stat in_stat;\n+\tlstat(filename.c_str(), &in_stat);\n+\n+\treturn in_stat.st_mode;\n+}\n+\n+bool string_ends_with(string str, string ending)\n+{\n+\treturn equal(ending.rbegin(), ending.rend(), str.rbegin());\n+}\n+\n+bool extension_is_known(string filename)\n+{\n+\tbool known_format = false;\n+\textension_pair extension; int i = 1;\n+\n+\textension = known_extensions[0];\n+\twhile (extension.from != NULL) {\n+\t\tif (string_ends_with(filename, extension.from)) {\n+\t\t\tknown_format = true;\n+\t\t\tbreak;\n+\t\t}\n+\t\textension = known_extensions[i];\n+\t\ti++;\n+\t}\n+\n+\tif (!known_format) {\n+\t\tif (!string_ends_with(filename, suffix)) {\n+\t\t\treturn false;\n+\t\t}\n+\t}\n+\n+\treturn true;\n+}\n+\n+string replace_extension(string filename)\n+{\n+\tint suffix_starts_at = filename.length() - strlen (suffix);\n+\tstring from_suffix = filename.substr(suffix_starts_at, strlen (suffix));\n+\tstring ret = filename.substr(0, suffix_starts_at);\n+\textension_pair extension; int i = 1;\n+\n+\tbool found_replacement = false;\n+\textension = known_extensions[0];\n+\twhile (extension.from != NULL) {\n+\t\tif (from_suffix.compare(extension.from) == 0) {\n+\t\t\tret += extension.to;\n+\t\t\tfound_replacement = true;\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\textension = known_extensions[i];\n+\t\ti++;\n+\t}\n+\n+\treturn ret;\n+}\n+\n+string pretty_print_status(string filename, string output_filename,\n+\t\tstring ratio)\n+{\n+\tstring ret = \"\";\n+\n+\tret += filename;\n+\tret += \":\\t \";\n+\n+\tif (program_mode == PM_TEST) {\n+\t\tret += \"decoded succesfully\";\n+\n+\t\treturn ret;\n+\t}\n+\n+\tif (!stdinput && !stdoutput) {\n+\t\tret += ratio;\n+\t\tret += \" -- \";\n+\t}\n+\n+\tif (program_mode == PM_COMPRESS) {\n+\t\tif (keep) {\n+\t\t\tret += \"encoded succesfully\";\n+\n+\t\t\treturn ret;\n+\t\t}\n+\n+\t\tret += \"replaced with \";\n+\t\tret += output_filename;\n+\n+\t\treturn ret;\n+\t}\n+\n+\tif (program_mode == PM_DECOMPRESS) {\n+\t\tif (keep) {\n+\t\t\tret += \"decoded succesfully\";\n+\n+\t\t\treturn ret;\n+\t\t}\n+\n+\t\tret += \"replaced with \";\n+\t\tret += output_filename;\n+\n+\t\treturn ret;\n+\t}\n+\n+\treturn ret;\n+}\n+\n+static string archive_name; // I know, it is crude, but I haven't found any other\n+    // way then making a global variable to transfer filename to handler\n+\n+void signal_handler (int signum)\n+{\n+    unlink (archive_name.c_str()); // deleting\n+    signal (signum, SIG_DFL); // we return the default function to used signal\n+    kill (getpid(), signum); // and then send this signal to the process again\n+}\n+\n+} // namespace lzma\n+\n+\n+int main(int argc, char **argv)\n+{\n+\tusing namespace lzma;\n+\tusing std::cerr;\n+\n+\tstringVector filenames;\n+\n+\tsignal (SIGTERM,signal_handler);\n+\tsignal (SIGHUP,signal_handler);\n+\tsignal (SIGINT,signal_handler);\n+\n+\ttry {\n+\t\tparse_options(argc, argv, filenames);\n+\t}\n+\tcatch (...) {\n+\t\treturn STATUS_ERROR;\n+\t}\n+\n+\tif (program_mode == PM_HELP) {\n+\t\tprint_help(argv[0]);\n+\t\treturn STATUS_OK;\n+\t}\n+\telse if (program_mode == PM_LICENSE) {\n+\t\tprint_license();\n+\t\treturn STATUS_OK;\n+\t}\n+\telse if (program_mode == PM_VERSION) {\n+\t\tprint_version();\n+\t\treturn STATUS_OK;\n+\t}\n+\n+\tif (filenames.empty()) {\n+\t\tstdinput = true;\n+\t\tstdoutput = true;\n+\n+\t\t/* FIXME: get rid of this */\n+\t\tfilenames.push_back(\"-\");\n+\t}\n+\n+\t/* Protection: always create new files with 0600 in order to prevent\n+\t * outsiders from reading incomplete data. */\n+\tumask(0077);\n+\n+\tbool warning = false;\n+\n+\tfor (int i = 0; i < filenames.size(); i++) {\n+\t\tCMyComPtr<ISequentialInStream> inStream;\n+\t\tCMyComPtr<ISequentialOutStream> outStream;\n+\t\tUInt64 fileSize = 0;\n+\t\tint inhandle = 0, outhandle = 0;\n+\t\tstring output_filename;\n+\n+\t\tif (stdinput) {\n+\t\t\tinStream = new CStdInFileStream;\n+\t\t\tMY_SET_BINARY_MODE(stdin);\n+\t\t\tfileSize = (UInt64)(Int64)-1;\n+\n+\t\t\tinhandle = STDIN_FILENO;\n+\n+\t\t\toutStream = new CStdOutFileStream;\n+\t\t\tMY_SET_BINARY_MODE(stdout);\n+\n+\t\t\touthandle = STDOUT_FILENO;\n+\t\t}\n+\t\telse {\n+\t\t\tmode_t infile_mode = get_file_mode(filenames[i]);\n+\t\t\tif (!S_ISREG(infile_mode)) {\n+\t\t\t\tif (S_ISDIR(infile_mode)) {\n+\t\t\t\t\twarning = true;\n+\t\t\t\t\tcerr << argv[0] << \": \" << filenames[i] << \": \"\n+\t\t\t\t\t\t<< \"cowardly refusing to work on directory\"\n+\t\t\t\t\t\t<< endl;\n+\n+\t\t\t\t\tcontinue;\n+\t\t\t\t}\n+\t\t\t\telse if (S_ISLNK(infile_mode)) {\n+\t\t\t\t\tif (!stdoutput && !force) {\n+\t\t\t\t\t\twarning = true;\n+\n+\t\t\t\t\tcerr << argv[0] << \": \" << filenames[i] << \": \"\n+\t\t\t\t\t\t\t<< \"cowardly refusing to work on symbolic link \"\n+\t\t\t\t\t\t\t<< \"(use --force to force encoding or decoding)\"\n+\t\t\t\t\t\t\t<< endl;\n+\n+\t\t\t\t\t\tcontinue;\n+\t\t\t\t\t}\n+\t\t\t\t}\n+\t\t\t\telse {\n+\t\t\t\t\twarning = true;\n+\n+\t\t\t\t\tcerr << argv[0] << \": \" << filenames[i] << \": \"\n+\t\t\t\t\t\t<< \"doesn't exist or is not a regular file\"\n+\t\t\t\t\t\t<< endl;\n+\n+\t\t\t\t\tcontinue;\n+\t\t\t\t}\n+\t\t\t}\n+\n+\t\t\t// Test if the file already ends with *suffix.\n+\t\t\tif (program_mode == PM_COMPRESS && !force\n+\t\t\t\t\t&& string_ends_with(filenames[i],\n+\t\t\t\t\t\tsuffix)) {\n+\t\t\t\twarning = true;\n+\n+\t\t\t\tcerr << filenames[i] << \" already has \"\n+\t\t\t\t\t<< suffix << \" suffix -- unchanged\\n\";\n+\n+\t\t\t\tcontinue;\n+\t\t\t}\n+\n+\t\t\t// Test if the file extension is known.\n+\t\t\tif (program_mode == PM_DECOMPRESS\n+\t\t\t\t\t&& !extension_is_known(filenames[i])) {\n+\t\t\t\twarning = true;\n+\n+\t\t\t\tcerr << filenames[i] << \": \"\n+\t\t\t\t\t<< \" unknown suffix -- unchanged\"\n+\t\t\t\t\t<< endl;\n+\n+\t\t\t\tcontinue;\n+\t\t\t}\n+\n+\t\t\ttry {\n+\t\t\t\tinhandle = open_instream(filenames[i], inStream, fileSize);\n+\t\t\t}\n+\t\t\tcatch (Exception e) {\n+\t\t\t\tcerr << argv[0] << \": \" << e.what() << endl;\n+\t\t\t\treturn STATUS_ERROR;\n+\t\t\t}\n+\n+\t\t\tif (stdoutput) {\n+\t\t\t\toutStream = new CStdOutFileStream;\n+\t\t\t\tMY_SET_BINARY_MODE(stdout);\n+\n+\t\t\t\touthandle = STDOUT_FILENO;\n+\t\t\t}\n+\t\t\telse {\n+\t\t\t\t/* Testing mode is nothing else but decoding\n+\t\t\t\t * and throwing away the result. */\n+\t\t\t\tif (program_mode == PM_TEST)\n+\t\t\t\t\toutput_filename = \"/dev/null\";\n+\t\t\t\telse if (program_mode == PM_DECOMPRESS)\n+\t\t\t\t\toutput_filename = replace_extension(filenames[i]);\n+\t\t\t\telse\n+\t\t\t\t\toutput_filename = filenames[i]\n+\t\t\t\t\t\t\t+ suffix;\n+\t\t\t\tarchive_name = output_filename;\n+\n+\t\t\t\ttry {\n+\t\t\t\t\touthandle = open_outstream(output_filename, outStream);\n+\t\t\t\t}\n+\t\t\t\tcatch (Exception e) {\n+\t\t\t\t\tcerr << argv[0] << \": \" << e.what() << endl;\n+\t\t\t\t\treturn STATUS_ERROR;\n+\t\t\t\t}\n+\t\t\t}\n+\n+\t\t}\n+\n+\t\t// Unless --force is specified, do not read/write compressed\n+\t\t// data from/to a terminal.\n+\t\tif (!force) {\n+\t\t\tif (program_mode == PM_COMPRESS && isatty(outhandle)) {\n+\t\t\t\tcerr << argv[0] << \": compressed data not \"\n+\t\t\t\t\t\"written to a terminal. Use \"\n+\t\t\t\t\t\"-f to force compression.\\n\"\n+\t\t\t\t\t<< argv[0] << \": For help, type: \"\n+\t\t\t\t\t<< argv[0] << \" -h\\n\";\n+\t\t\t\treturn STATUS_ERROR;\n+\t\t\t} else if (program_mode == PM_DECOMPRESS\n+\t\t\t\t\t&& isatty(inhandle)) {\n+\t\t\t\tcerr << argv[0] << \": compressed data not \"\n+\t\t\t\t\t\"read from a terminal. Use \"\n+\t\t\t\t\t\"-f to force decompression.\\n\"\n+\t\t\t\t\t<< argv[0] << \": For help, type: \"\n+\t\t\t\t\t<< argv[0] << \" -h\\n\";\n+\t\t\t\treturn STATUS_ERROR;\n+\t\t\t}\n+\t\t}\n+\n+\t\tif (program_mode == PM_COMPRESS) {\n+\t\t\t    NCompress::NLzma::CEncoder *encoderSpec =\n+\t\t\t\t      new NCompress::NLzma::CEncoder;\n+\n+\t\t\tlzma_option options = option_mapping[compression_mode];\n+\n+\t\t\ttry {\n+\t\t\t\tencode(encoderSpec, inStream, outStream, options, fileSize);\n+\t\t\t}\n+\t\t\tcatch (Exception e) {\n+\t\t\t\tcerr << argv[0] << \": \" << e.what() << endl;\n+\t\t\t\tunlink(output_filename.c_str());\n+\t\t\t\tdelete(encoderSpec);\n+\n+\t\t\t\treturn STATUS_ERROR;\n+\t\t\t}\n+\n+\t\t\tdelete(encoderSpec);\n+\t\t}\n+\t\telse {\t\t\t// PM_DECOMPRESS | PM_TEST\n+\t\t    NCompress::NLzma::CDecoder *decoderSpec =\n+\t\t        new NCompress::NLzma::CDecoder;\n+\n+\t\t\ttry {\n+\t\t\t\tdecode(decoderSpec, inStream, outStream);\n+\t\t\t}\n+\t\t\tcatch (Exception e) {\n+\t\t\t\tcerr << argv[0] << \": \" << e.what() << endl;\n+\t\t\t\tunlink(output_filename.c_str());\n+\t\t\t\tdelete(decoderSpec);\n+\n+\t\t\t\treturn STATUS_ERROR;\n+\t\t\t}\n+\n+\t\t\tdelete(decoderSpec);\n+\t\t}\n+\n+\t\t/* Set permissions and owners. */\n+\t\tif ( (program_mode == PM_COMPRESS || program_mode == PM_DECOMPRESS )\n+\t\t\t\t&& (!stdinput && !stdoutput) ) {\n+\n+\t\t\tint ret = 0;\n+\t\t\tstruct stat file_stats;\n+\t\t\tret = fstat(inhandle, &file_stats);\n+\n+\t\t\tret = fchmod(outhandle, file_stats.st_mode);\n+\t\t\tret = fchown(outhandle, file_stats.st_uid, file_stats.st_gid);\n+\t\t\t// We need to call fchmod() again, since otherwise the SUID bits\n+\t\t\t// are lost.\n+\t\t\tret = fchmod(outhandle, file_stats.st_mode);\n+\n+\t\t\tstruct timeval file_times[2];\n+\t\t\t// Access time\n+\t\t\tfile_times[0].tv_sec = file_stats.st_atime;\n+\t\t\tfile_times[0].tv_usec = 0;\n+\t\t\t// Modification time\n+\t\t\tfile_times[1].tv_sec = file_stats.st_mtime;\n+\t\t\tfile_times[1].tv_usec = 0;\n+\n+\t\t\tret = futimes(outhandle, file_times);\n+\n+\t\t\tif (!keep)\n+\t\t\t\tunlink(filenames[i].c_str());\n+\t\t}\n+\n+\t\tif (verbosity > 0) {\n+\t\t\tif (stdoutput) {\n+\t\t\t\tcerr << filenames[i] << \":\\t \";\n+\t\t\t\tcerr << \"decoded succesfully\"\n+\t\t\t\t\t<< endl;\n+\t\t\t}\n+\n+\t\t\telse {\n+\t\t\t\tchar buf[10] = { 0 };\n+\n+\t\t\t\tif (program_mode == PM_DECOMPRESS)\n+\t\t\t\t\tsnprintf(buf, 10, \"%.2f%%\",\n+\t\t\t\t\t\t\t(1 - get_ratio(outhandle, inhandle)) * 100);\n+\t\t\t\tif (program_mode == PM_COMPRESS)\n+\t\t\t\t\tsnprintf(buf, 10, \"%.2f%%\",\n+\t\t\t\t\t\t\t(1 - get_ratio(inhandle, outhandle)) * 100);\n+\n+\t\t\t\tstring ratio = buf;\n+\t\t\t\tcerr << pretty_print_status(filenames[i], output_filename,\n+\t\t\t\t\t\tratio)\n+\t\t\t\t\t<< endl;\n+\t\t\t}\n+\t\t}\n+\t}\n+\n+\tif (warning)\n+\t\treturn STATUS_WARNING;\n+\n+\treturn STATUS_OK;\n+}\n+\nIndex: lzma-4.65/CPP/7zip/Compress/LZMA_Alone/Exception.h\n===================================================================\n--- /dev/null\t1970-01-01 00:00:00.000000000 +0000\n+++ lzma-4.65/CPP/7zip/Compress/LZMA_Alone/Exception.h\t2009-06-01 22:01:10.000000000 +0200\n@@ -0,0 +1,45 @@\n+/* A couple of exceptions for lzmp.\n+ *\n+ * Copyright (C) 2005 Ville Koskinen\n+ *\n+ * This program is free software; you can redistribute it and/or\n+ * modify it under the terms of the GNU General Public License\n+ * as published by the Free Software Foundation; either version 2\n+ * of the License, or (at your option) any later version.\n+ *\n+ * This program is distributed in the hope that it will be useful,\n+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\n+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n+ * GNU General Public License for more details.\n+ */\n+\n+#ifndef _EXCEPTION_H_\n+#define _EXCEPTION_H_\n+\n+#include <string>\n+using std::string;\n+\n+class Exception\n+{\n+private:\n+\tstring message;\n+public:\n+\tException(char *what): message(what) { }\n+\tException(string what): message(what) { }\n+\n+\t~Exception() { }\n+\n+\tstring what(void) { return message; }\n+};\n+\n+class ArgumentException: public Exception\n+{\n+public:\n+\tArgumentException(char *what): Exception(what) { }\n+\tArgumentException(string what): Exception(what) { }\n+\n+\t~ArgumentException() { }\n+};\n+\n+#endif\n+\nIndex: lzma-4.65/CPP/7zip/Compress/LZMA_Alone/makefile.gcc\n===================================================================\n--- lzma-4.65.orig/CPP/7zip/Compress/LZMA_Alone/makefile.gcc\t2009-06-01 22:00:54.000000000 +0200\n+++ lzma-4.65/CPP/7zip/Compress/LZMA_Alone/makefile.gcc\t2009-06-01 22:06:13.000000000 +0200\n@@ -1,9 +1,10 @@\n-PROG = lzma\n+PROG = lzma_alone\n+PROG2 = lzma\n CXX = g++ -O2 -Wall\n CXX_C = gcc -O2 -Wall\n LIB = -lm\n RM = rm -f\n-CFLAGS = -c -D_FILE_OFFSET_BITS=64\n+CFLAGS = -c -I ../../../ -D_FILE_OFFSET_BITS=64 -DPACKAGE_VERSION=\"\\\"4.32.0beta3\\\"\"\n \n ifdef SystemDrive\n IS_MINGW = 1\n@@ -45,12 +46,35 @@\n   Lzma86Dec.o \\\n   Lzma86Enc.o \\\n \n+OBJS2 = \\\n+\tC_FileIO.o \\\n+\tCRC.o \\\n+\tAlloc.o \\\n+\tFileStreams.o \\\n+\tStreamUtils.o \\\n+\tInBuffer.o \\\n+\tOutBuffer.o \\\n+\tLzmaDecoder.o \\\n+\tStringConvert.o \\\n+\tStringToInt.o \\\n+\tLzmaEncoder.o \\\n+\tLzmaDec.o \\\n+\tLzmaEnc.o \\\n+\tLzFind.o \\\n+\t7zCrc.o \\\n+\tlzmp.o\n \n-all: $(PROG)\n+all: $(PROG) $(PROG2)\n \n $(PROG): $(OBJS)\n \t$(CXX) -o $(PROG) $(LDFLAGS) $(OBJS) $(LIB) $(LIB2)\n \n+$(PROG2): $(OBJS2)\n+\t$(CXX) -o $(PROG2) $(LDFLAGS) $(OBJS2) $(LIB)\n+\n+lzmp.o: lzmp.cpp\n+\t$(CXX) $(CFLAGS) lzmp.cpp\n+\n LzmaAlone.o: LzmaAlone.cpp\n \t$(CXX) $(CFLAGS) LzmaAlone.cpp\n \n@@ -131,5 +153,5 @@\n \t$(CXX_C) $(CFLAGS) ../../../../C/LzmaUtil/Lzma86Enc.c\n \n clean:\n-\t-$(RM) $(PROG) $(OBJS)\n+\t-$(RM) $(PROG) $(PROG2) $(OBJS)\n \nIndex: lzma-4.65/CPP/7zip/Compress/LZMA_Alone/lzma_version.h\n===================================================================\n--- /dev/null\t1970-01-01 00:00:00.000000000 +0000\n+++ lzma-4.65/CPP/7zip/Compress/LZMA_Alone/lzma_version.h\t2009-06-01 22:01:10.000000000 +0200\n@@ -0,0 +1,31 @@\n+#ifndef LZMA_VERSION_H\n+#define LZMA_VERSION_H\n+\n+/*\n+    Version and copyright information used by LZMA utils.\n+*/\n+\n+static const char *LZMA_SDK_VERSION_STRING = \"4.43\";\n+\n+static const char *LZMA_SDK_COPYRIGHT_STRING =\n+\t\t\"Copyright (C) 1999-2006 Igor Pavlov\";\n+\n+static const char *LZMA_SDK_COPYRIGHT_INFO =\n+\t\t\"  See http://7-zip.org/sdk.html or the documentation of LZMA SDK for\\n\"\n+\t\t\"  the license. For reference, the version 4.43 is free software\\n\"\n+\t\t\"  licensed under the GNU LGPL.\";\n+\n+\n+static const char *LZMA_UTILS_VERSION_STRING = PACKAGE_VERSION;\n+\n+static const char *LZMA_UTILS_COPYRIGHT_STRING =\n+\t\t\"Copyright (C) 2006 Lasse Collin\";\n+\n+static const char *LZMA_UTILS_COPYRIGHT_INFO =\n+\t\t\"This program comes with ABSOLUTELY NO WARRANTY.\\n\"\n+\t\t\"You may redistribute copies of this program\\n\"\n+\t\t\"under the terms of the GNU General Public License.\\n\"\n+\t\t\"For more information about these matters, see the file \"\n+\t\t\"named COPYING.\\n\";\n+\n+#endif /* ifndef LZMA_VERSION_H */\nIndex: lzma-4.65/CPP/Common/C_FileIO.h\n===================================================================\n--- lzma-4.65.orig/CPP/Common/C_FileIO.h\t2009-05-15 23:33:51.000000000 +0200\n+++ lzma-4.65/CPP/Common/C_FileIO.h\t2009-06-01 22:06:56.000000000 +0200\n@@ -24,6 +24,7 @@\n   bool Close();\n   bool GetLength(UInt64 &length) const;\n   off_t Seek(off_t distanceToMove, int moveMethod) const;\n+  int GetHandle() const { return _handle; }\n };\n \n class CInFile: public CFileBase\n"
  },
  {
    "path": "tools/lzma/patches/003-compile_fixes.patch",
    "content": "diff -urN lzma-4.65/CPP/7zip/Common/FileStreams.h lzma-4.65.new/CPP/7zip/Common/FileStreams.h\n--- lzma-4.65/CPP/7zip/Common/FileStreams.h\t2009-05-15 23:33:51.000000000 +0200\n+++ lzma-4.65.new/CPP/7zip/Common/FileStreams.h\t2009-06-01 22:30:01.000000000 +0200\n@@ -72,6 +72,7 @@\n   public IOutStream,\n   public CMyUnknownImp\n {\n+public:\n   #ifdef USE_WIN_FILE\n   NWindows::NFile::NIO::COutFile File;\n   #else\ndiff -urN lzma-4.65/CPP/Common/MyWindows.h lzma-4.65.new/CPP/Common/MyWindows.h\n--- lzma-4.65/CPP/Common/MyWindows.h\t2009-05-15 23:33:51.000000000 +0200\n+++ lzma-4.65.new/CPP/Common/MyWindows.h\t2009-06-01 22:29:26.000000000 +0200\n@@ -101,8 +101,11 @@\n \n #ifdef __cplusplus\n \n+#ifndef INITGUID\n+#define INITGUID\n DEFINE_GUID(IID_IUnknown,\n 0x00000000, 0x0000, 0x0000, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x46);\n+#endif\n struct IUnknown\n {\n   STDMETHOD(QueryInterface) (REFIID iid, void **outObject) PURE;\n"
  },
  {
    "path": "tools/lzma/patches/100-static_library.patch",
    "content": "--- a/C/LzmaUtil/makefile.gcc\n+++ b/C/LzmaUtil/makefile.gcc\n@@ -1,44 +1,53 @@\n PROG = lzma\n-CXX = g++\n-LIB =\n+CC = gcc\n+LIB = liblzma.a\n RM = rm -f\n CFLAGS = -c -O2 -Wall\n+AR = ar\n+RANLIB = ranlib\n \n OBJS = \\\n-  LzmaUtil.o \\\n   Alloc.o \\\n   LzFind.o \\\n   LzmaDec.o \\\n   LzmaEnc.o \\\n+  LzmaLib.o \\\n   7zFile.o \\\n   7zStream.o \\\n \n-\n all: $(PROG)\n \n-$(PROG): $(OBJS)\n-\t$(CXX) -o $(PROG) $(LDFLAGS) $(OBJS) $(LIB) $(LIB2)\n+$(PROG): LzmaUtil.o $(LIB)\n+\t$(CC) -o $(PROG) $(LDFLAGS) $< $(LIB)\n \n LzmaUtil.o: LzmaUtil.c\n-\t$(CXX) $(CFLAGS) LzmaUtil.c\n+\t$(CC) $(CFLAGS) LzmaUtil.c\n+\n+$(LIB): $(OBJS)\n+\trm -f $@\n+\t$(AR) rcu $@ $(OBJS)\n+\t$(RANLIB) $@\n \n Alloc.o: ../Alloc.c\n-\t$(CXX) $(CFLAGS) ../Alloc.c\n+\t$(CC) $(CFLAGS) ../Alloc.c\n \n LzFind.o: ../LzFind.c\n-\t$(CXX) $(CFLAGS) ../LzFind.c\n+\t$(CC) $(CFLAGS) ../LzFind.c\n \n LzmaDec.o: ../LzmaDec.c\n-\t$(CXX) $(CFLAGS) ../LzmaDec.c\n+\t$(CC) $(CFLAGS) ../LzmaDec.c\n \n LzmaEnc.o: ../LzmaEnc.c\n-\t$(CXX) $(CFLAGS) ../LzmaEnc.c\n+\t$(CC) $(CFLAGS) ../LzmaEnc.c\n+\n+LzmaLib.o: ../LzmaLib.c\n+\t$(CC) $(CFLAGS) ../LzmaLib.c\n \n 7zFile.o: ../7zFile.c\n-\t$(CXX) $(CFLAGS) ../7zFile.c\n+\t$(CC) $(CFLAGS) ../7zFile.c\n \n 7zStream.o: ../7zStream.c\n-\t$(CXX) $(CFLAGS) ../7zStream.c\n+\t$(CC) $(CFLAGS) ../7zStream.c\n \n clean:\n-\t-$(RM) $(PROG) $(OBJS)\n+\t-$(RM) $(PROG) *.o *.a\n"
  },
  {
    "path": "tools/lzma/patches/101-move-copyright-to-usage-info.patch",
    "content": "--- a/CPP/7zip/Compress/LZMA_Alone/LzmaAlone.cpp\n+++ b/CPP/7zip/Compress/LZMA_Alone/LzmaAlone.cpp\n@@ -101,6 +101,8 @@ static const int kNumSwitches = sizeof(k\n \n static void PrintHelp()\n {\n+  fprintf(stderr, \"\\nLZMA \" MY_VERSION_COPYRIGHT_DATE \"\\n\");\n+\n   fprintf(stderr, \"\\nUsage:  LZMA <e|d> inputFile outputFile [<switches>...]\\n\"\n              \"  e: encode file\\n\"\n              \"  d: decode file\\n\"\n@@ -168,8 +170,6 @@ int main2(int n, const char *args[])\n   g_IsNT = IsItWindowsNT();\n   #endif\n \n-  fprintf(stderr, \"\\nLZMA \" MY_VERSION_COPYRIGHT_DATE \"\\n\");\n-\n   if (n == 1)\n   {\n     PrintHelp();\n"
  },
  {
    "path": "tools/lzma-old/Makefile",
    "content": "# \n# Copyright (C) 2006 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=lzma-old\nPKG_VERSION:=4.32\n\nPKG_SOURCE:=lzma-$(PKG_VERSION).tar.bz2\nPKG_SOURCE_URL:=@OPENWRT\nPKG_HASH:=49053e4bb5e0646a841d250d9cb81f7714f5fff04a133216c4748163567acc3d\n\nHOST_BUILD_DIR:=$(BUILD_DIR_HOST)/lzma-$(PKG_VERSION)\n\ninclude $(INCLUDE_DIR)/host-build.mk\n\nLIB_DIR=$(HOST_BUILD_DIR)/C/7zip/Compress/LZMA_Lib\nALONE_DIR=$(HOST_BUILD_DIR)/C/7zip/Compress/LZMA_Alone\n\ndefine Host/Compile\n\t+$(HOST_MAKE_VARS) \\\n\t$(MAKE) -C $(LIB_DIR)\n\t+$(HOST_MAKE_VARS) \\\n\t$(MAKE) -f makefile.gcc -C $(ALONE_DIR)\nendef\n\ndefine Host/Install\n\t$(INSTALL_DATA) $(LIB_DIR)/liblzma.a $(STAGING_DIR_HOST)/lib/liblzma-old.a\nendef\n\ndefine Host/Clean\n\trm -f $(STAGING_DIR_HOST)/lib/liblzma-old.a\nendef\n\n$(eval $(call HostBuild))\n"
  },
  {
    "path": "tools/lzma-old/patches/100-lzma_zlib.patch",
    "content": "--- a/C/7zip/Compress/LZMA/LZMADecoder.cpp\n+++ b/C/7zip/Compress/LZMA/LZMADecoder.cpp\n@@ -274,12 +274,17 @@ STDMETHODIMP CDecoder::SetDecoderPropert\n   Byte remainder = (Byte)(properties[0] / 9);\n   int lp = remainder % 5;\n   int pb = remainder / 5;\n-  if (pb > NLength::kNumPosStatesBitsMax)\n-    return E_INVALIDARG;\n-  _posStateMask = (1 << pb) - 1;\n   UInt32 dictionarySize = 0;\n   for (int i = 0; i < 4; i++)\n     dictionarySize += ((UInt32)(properties[1 + i])) << (i * 8);\n+  return SetDecoderPropertiesRaw(lc, lp, pb, dictionarySize);\n+}\n+\n+STDMETHODIMP CDecoder::SetDecoderPropertiesRaw(int lc, int lp, int pb, UInt32 dictionarySize)\n+{\n+  if (pb > NLength::kNumPosStatesBitsMax)\n+    return E_INVALIDARG;\n+  _posStateMask = (1 << pb) - 1;\n   if (!_outWindowStream.Create(dictionarySize))\n     return E_OUTOFMEMORY;\n   if (!_literalDecoder.Create(lp, lc))\n--- a/C/7zip/Compress/LZMA/LZMADecoder.h\n+++ b/C/7zip/Compress/LZMA/LZMADecoder.h\n@@ -228,6 +228,7 @@ public:\n       ICompressProgressInfo *progress);\n \n   STDMETHOD(SetDecoderProperties2)(const Byte *data, UInt32 size);\n+  STDMETHOD(SetDecoderPropertiesRaw)(int lc, int lp, int pb, UInt32 dictionarySize);\n \n   STDMETHOD(GetInStreamProcessedSize)(UInt64 *value);\n \n--- /dev/null\n+++ b/C/7zip/Compress/LZMA_Lib/makefile\n@@ -0,0 +1,92 @@\n+PROG = liblzma.a\n+CXX = g++ -O3 -Wall\n+AR = ar\n+RM = rm -f\n+CFLAGS = -c  -I ../../../\n+\n+OBJS = \\\n+  ZLib.o \\\n+  LZMADecoder.o \\\n+  LZMAEncoder.o \\\n+  LZInWindow.o \\\n+  LZOutWindow.o \\\n+  RangeCoderBit.o \\\n+  InBuffer.o \\\n+  OutBuffer.o \\\n+  FileStreams.o \\\n+  Alloc.o \\\n+  C_FileIO.o \\\n+  CommandLineParser.o \\\n+  CRC.o \\\n+  StreamUtils.o \\\n+  String.o \\\n+  StringConvert.o \\\n+  StringToInt.o \\\n+  Vector.o \\\n+\n+\n+all: $(PROG)\n+\n+$(PROG): $(OBJS)\n+\t$(AR) r $(PROG) $(OBJS)\n+\n+ZLib.o: ZLib.cpp\n+\t$(CXX) $(CFLAGS) ZLib.cpp\n+\n+LZMADecoder.o: ../LZMA/LZMADecoder.cpp\n+\t$(CXX) $(CFLAGS) ../LZMA/LZMADecoder.cpp\n+\n+LZMAEncoder.o: ../LZMA/LZMAEncoder.cpp\n+\t$(CXX) $(CFLAGS) ../LZMA/LZMAEncoder.cpp\n+\n+LZInWindow.o: ../LZ/LZInWindow.cpp\n+\t$(CXX) $(CFLAGS) ../LZ/LZInWindow.cpp\n+\n+LZOutWindow.o: ../LZ/LZOutWindow.cpp\n+\t$(CXX) $(CFLAGS) ../LZ/LZOutWindow.cpp\n+\n+RangeCoderBit.o: ../RangeCoder/RangeCoderBit.cpp\n+\t$(CXX) $(CFLAGS) ../RangeCoder/RangeCoderBit.cpp\n+\n+InBuffer.o: ../../Common/InBuffer.cpp\n+\t$(CXX) $(CFLAGS) ../../Common/InBuffer.cpp\n+\n+OutBuffer.o: ../../Common/OutBuffer.cpp\n+\t$(CXX) $(CFLAGS) ../../Common/OutBuffer.cpp\n+\n+StreamUtils.o: ../../Common/StreamUtils.cpp\n+\t$(CXX) $(CFLAGS) ../../Common/StreamUtils.cpp\n+\n+FileStreams.o: ../../Common/FileStreams.cpp\n+\t$(CXX) $(CFLAGS) ../../Common/FileStreams.cpp\n+\n+Alloc.o: ../../../Common/Alloc.cpp\n+\t$(CXX) $(CFLAGS) ../../../Common/Alloc.cpp\n+\n+C_FileIO.o: ../../../Common/C_FileIO.cpp\n+\t$(CXX) $(CFLAGS) ../../../Common/C_FileIO.cpp\n+\n+CommandLineParser.o: ../../../Common/CommandLineParser.cpp\n+\t$(CXX) $(CFLAGS) ../../../Common/CommandLineParser.cpp\n+\n+CRC.o: ../../../Common/CRC.cpp\n+\t$(CXX) $(CFLAGS) ../../../Common/CRC.cpp\n+\n+MyWindows.o: ../../../Common/MyWindows.cpp\n+\t$(CXX) $(CFLAGS) ../../../Common/MyWindows.cpp\n+\n+String.o: ../../../Common/String.cpp\n+\t$(CXX) $(CFLAGS) ../../../Common/String.cpp\n+\n+StringConvert.o: ../../../Common/StringConvert.cpp\n+\t$(CXX) $(CFLAGS) ../../../Common/StringConvert.cpp\n+\n+StringToInt.o: ../../../Common/StringToInt.cpp\n+\t$(CXX) $(CFLAGS) ../../../Common/StringToInt.cpp\n+\n+Vector.o: ../../../Common/Vector.cpp\n+\t$(CXX) $(CFLAGS) ../../../Common/Vector.cpp\n+\n+clean:\n+\t-$(RM) $(PROG) $(OBJS)\n+\n--- /dev/null\n+++ b/C/7zip/Compress/LZMA_Lib/ZLib.cpp\n@@ -0,0 +1,273 @@\n+/*\n+ * lzma zlib simplified wrapper\n+ *\n+ * Copyright (c) 2005-2006 Oleg I. Vdovikin <oleg@cs.msu.su>\n+ *\n+ * This library is free software; you can redistribute \n+ * it and/or modify it under the terms of the GNU Lesser \n+ * General Public License as published by the Free Software \n+ * Foundation; either version 2.1 of the License, or \n+ * (at your option) any later version.\n+ *\n+ * This library is distributed in the hope that it will be \n+ * useful, but WITHOUT ANY WARRANTY; without even the implied \n+ * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR \n+ * PURPOSE. See the GNU Lesser General Public License \n+ * for more details.\n+ *\n+ * You should have received a copy of the GNU Lesser General \n+ * Public License along with this library; if not, write to \n+ * the Free Software Foundation, Inc., 59 Temple Place, \n+ * Suite 330, Boston, MA 02111-1307 USA \n+ */\n+\n+/*\n+ * default values for encoder/decoder used by wrapper\n+ */\n+\n+#include <zlib.h>\n+\n+#define ZLIB_LC 3\n+#define ZLIB_LP 0\n+#define ZLIB_PB 2\n+\n+#ifdef WIN32\n+#include <initguid.h>\n+#else\n+#define INITGUID\n+#endif\n+\n+#include \"../../../Common/MyWindows.h\"\n+#include \"../LZMA/LZMADecoder.h\"\n+#include \"../LZMA/LZMAEncoder.h\"\n+\n+#define STG_E_SEEKERROR                  ((HRESULT)0x80030019L)\n+#define STG_E_MEDIUMFULL                 ((HRESULT)0x80030070L)\n+\n+class CInMemoryStream: \n+  public IInStream,\n+  public IStreamGetSize,\n+  public CMyUnknownImp\n+{\n+public:\n+  CInMemoryStream(const Bytef *data, UInt64 size) : \n+\t  m_data(data), m_size(size), m_offset(0) {}\n+\n+  virtual ~CInMemoryStream() {}\n+\n+  MY_UNKNOWN_IMP2(IInStream, IStreamGetSize)\n+\n+  STDMETHOD(Read)(void *data, UInt32 size, UInt32 *processedSize)\n+  {\n+\t  if (size > m_size - m_offset) \n+\t\t  size = m_size - m_offset;\n+\n+\t  if (size) {\n+\t\t  memcpy(data, m_data + m_offset, size);\n+\t  }\n+\n+\t  m_offset += size;\n+\n+\t  if (processedSize) \n+\t\t  *processedSize = size;\n+\n+\t  return S_OK;\n+  }\n+\n+  STDMETHOD(ReadPart)(void *data, UInt32 size, UInt32 *processedSize)\n+  {\n+\treturn Read(data, size, processedSize);\n+  }\n+\n+  STDMETHOD(Seek)(Int64 offset, UInt32 seekOrigin, UInt64 *newPosition)\n+  {\n+\t  UInt64 _offset;\n+\n+\t  if (seekOrigin == STREAM_SEEK_SET) _offset = offset;\n+\t  else if (seekOrigin == STREAM_SEEK_CUR) _offset = m_offset + offset; \n+\t  else if (seekOrigin == STREAM_SEEK_END) _offset = m_size;\n+\t  else return STG_E_INVALIDFUNCTION;\n+\n+\t  if (_offset < 0 || _offset > m_size)\n+\t\t  return STG_E_SEEKERROR;\n+\n+\t  m_offset = _offset;\n+\n+\t  if (newPosition)\n+\t\t  *newPosition = m_offset;\n+\n+\t  return S_OK;\n+  }\n+\n+  STDMETHOD(GetSize)(UInt64 *size)\n+  {\n+\t  *size = m_size;\n+\t  return S_OK;\n+  }\n+protected:\n+\tconst Bytef *m_data;\n+\tUInt64 m_size;\n+\tUInt64 m_offset;\n+};\n+\n+class COutMemoryStream: \n+  public IOutStream,\n+  public CMyUnknownImp\n+{\n+public:\n+  COutMemoryStream(Bytef *data, UInt64 maxsize) : \n+\t  m_data(data), m_size(0), m_maxsize(maxsize), m_offset(0) {}\n+  virtual ~COutMemoryStream() {}\n+  \n+  MY_UNKNOWN_IMP1(IOutStream)\n+\n+  STDMETHOD(Write)(const void *data, UInt32 size, UInt32 *processedSize)\n+  {\n+\t  if (size > m_maxsize - m_offset) \n+\t\t  size = m_maxsize - m_offset;\n+\n+\t  if (size) {\n+\t\t  memcpy(m_data + m_offset, data, size);\n+\t  }\n+\n+\t  m_offset += size;\n+\n+\t  if (m_offset > m_size)\n+\t\tm_size = m_offset;\n+\n+\t  if (processedSize) \n+\t\t  *processedSize = size;\n+\n+\t  return S_OK;\n+  }\n+  \n+  STDMETHOD(WritePart)(const void *data, UInt32 size, UInt32 *processedSize)\n+  {\n+\t  return Write(data, size, processedSize);\n+  }\n+\n+  STDMETHOD(Seek)(Int64 offset, UInt32 seekOrigin, UInt64 *newPosition)\n+  {\n+\t  UInt64 _offset;\n+\n+\t  if (seekOrigin == STREAM_SEEK_SET) _offset = offset;\n+\t  else if (seekOrigin == STREAM_SEEK_CUR) _offset = m_offset + offset; \n+\t  else if (seekOrigin == STREAM_SEEK_END) _offset = m_size;\n+\t  else return STG_E_INVALIDFUNCTION;\n+\n+\t  if (_offset < 0 || _offset > m_maxsize)\n+\t\t  return STG_E_SEEKERROR;\n+\n+\t  m_offset = _offset;\n+\n+\t  if (newPosition)\n+\t\t  *newPosition = m_offset;\n+\n+\t  return S_OK;\n+  }\n+  \n+  STDMETHOD(SetSize)(Int64 newSize)\n+  {\n+\t  if ((UInt64)newSize > m_maxsize) \n+\t\t  return STG_E_MEDIUMFULL;\n+\n+\t  return S_OK;\n+  }\n+protected:\n+\tBytef *m_data;\n+\tUInt64 m_size;\n+\tUInt64 m_maxsize;\n+\tUInt64 m_offset;\n+};\n+\n+ZEXTERN int ZEXPORT compress2 (Bytef *dest,   uLongf *destLen,\n+                                  const Bytef *source, uLong sourceLen,\n+                                  int level)\n+{\n+\tCInMemoryStream *inStreamSpec = new CInMemoryStream(source, sourceLen);\n+\tCMyComPtr<ISequentialInStream> inStream = inStreamSpec;\n+\t\n+\tCOutMemoryStream *outStreamSpec = new COutMemoryStream(dest, *destLen);\n+\tCMyComPtr<ISequentialOutStream> outStream = outStreamSpec;\n+\t\n+\tNCompress::NLZMA::CEncoder *encoderSpec = \n+\t\tnew NCompress::NLZMA::CEncoder;\n+\tCMyComPtr<ICompressCoder> encoder = encoderSpec;\n+\t\n+\tPROPID propIDs[] = \n+\t{\n+\t\tNCoderPropID::kDictionarySize,\n+\t\tNCoderPropID::kPosStateBits,\n+\t\tNCoderPropID::kLitContextBits,\n+\t\tNCoderPropID::kLitPosBits,\n+\t\tNCoderPropID::kAlgorithm,\n+\t\tNCoderPropID::kNumFastBytes,\n+\t\tNCoderPropID::kMatchFinder,\n+\t\tNCoderPropID::kEndMarker\n+\t};\n+\tconst int kNumProps = sizeof(propIDs) / sizeof(propIDs[0]);\n+\t\n+\tPROPVARIANT properties[kNumProps];\n+\tfor (int p = 0; p < 6; p++)\n+\t\tproperties[p].vt = VT_UI4;\n+\tproperties[0].ulVal = UInt32(1 << (level + 14));\n+\tproperties[1].ulVal = UInt32(ZLIB_PB);\n+\tproperties[2].ulVal = UInt32(ZLIB_LC); // for normal files\n+\tproperties[3].ulVal = UInt32(ZLIB_LP); // for normal files\n+\tproperties[4].ulVal = UInt32(2);\n+\tproperties[5].ulVal = UInt32(128);\n+\t\n+\tproperties[6].vt = VT_BSTR;\n+\tproperties[6].bstrVal = (BSTR)(const wchar_t *)L\"BT4\";\n+\t\n+\tproperties[7].vt = VT_BOOL;\n+\tproperties[7].boolVal = VARIANT_TRUE;\n+\t\n+\tif (encoderSpec->SetCoderProperties(propIDs, properties, kNumProps) != S_OK)\n+\t\treturn Z_MEM_ERROR; // should not happen\n+\t\n+\tHRESULT result = encoder->Code(inStream, outStream, 0, 0, 0);\n+\tif (result == E_OUTOFMEMORY)\n+\t{\n+\t\treturn Z_MEM_ERROR;\n+\t}   \n+\telse if (result != S_OK)\n+\t{\n+\t\treturn Z_BUF_ERROR;\t// should not happen\n+\t}   \n+\t\n+\tUInt64 fileSize;\n+\toutStreamSpec->Seek(0, STREAM_SEEK_END, &fileSize);\n+\t*destLen = fileSize;\n+\t\n+\treturn Z_OK;\n+}\n+\n+ZEXTERN int ZEXPORT uncompress (Bytef *dest,   uLongf *destLen,\n+                                   const Bytef *source, uLong sourceLen)\n+{\n+\tCInMemoryStream *inStreamSpec = new CInMemoryStream(source, sourceLen);\n+\tCMyComPtr<ISequentialInStream> inStream = inStreamSpec;\n+\t\n+\tCOutMemoryStream *outStreamSpec = new COutMemoryStream(dest, *destLen);\n+\tCMyComPtr<ISequentialOutStream> outStream = outStreamSpec;\n+\t\n+\tNCompress::NLZMA::CDecoder *decoderSpec = \n+\t\tnew NCompress::NLZMA::CDecoder;\n+\tCMyComPtr<ICompressCoder> decoder = decoderSpec;\n+\t\n+\tif (decoderSpec->SetDecoderPropertiesRaw(ZLIB_LC, \n+\t\tZLIB_LP, ZLIB_PB, (1 << 23)) != S_OK) return Z_DATA_ERROR;\n+\t\n+\tUInt64 fileSize = *destLen;\n+\t\n+\tif (decoder->Code(inStream, outStream, 0, &fileSize, 0) != S_OK)\n+\t{\n+\t\treturn Z_DATA_ERROR;\n+\t}\n+\t\n+\toutStreamSpec->Seek(0, STREAM_SEEK_END, &fileSize);\n+\t*destLen = fileSize;\n+\t\n+\treturn Z_OK;\n+}\n"
  },
  {
    "path": "tools/lzma-old/patches/110-ranlib.patch",
    "content": "--- a/C/7zip/Compress/LZMA_Lib/makefile\n+++ b/C/7zip/Compress/LZMA_Lib/makefile\n@@ -29,6 +29,7 @@ all: $(PROG)\n \n $(PROG): $(OBJS)\n \t$(AR) r $(PROG) $(OBJS)\n+\tranlib $(PROG)\n \n ZLib.o: ZLib.cpp\n \t$(CXX) $(CFLAGS) ZLib.cpp\n"
  },
  {
    "path": "tools/lzma-old/patches/120-add-cflags.patch",
    "content": "--- a/C/7zip/Compress/LZMA_Lib/makefile\n+++ b/C/7zip/Compress/LZMA_Lib/makefile\n@@ -2,7 +2,7 @@ PROG = liblzma.a\n CXX = g++ -O3 -Wall\n AR = ar\n RM = rm -f\n-CFLAGS = -c  -I ../../../\n+CFLAGS += -c  -I ../../../\n \n OBJS = \\\n   ZLib.o \\\n"
  },
  {
    "path": "tools/m4/Makefile",
    "content": "# \n# Copyright (C) 2008-2013 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=m4\nPKG_CPE_ID:=cpe:/a:gnu:m4\nPKG_VERSION:=1.4.19\n\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz\nPKG_SOURCE_URL:=@GNU/$(PKG_NAME)\nPKG_HASH:=63aede5c6d33b6d9b13511cd0be2cac046f2e70fd0a07aa9573a04a82783af96\nPKG_CAT:=xzcat\n\nHOST_BUILD_PARALLEL:=1\n\ninclude $(INCLUDE_DIR)/host-build.mk\n\nHOST_CONFIGURE_VARS += gl_cv_func_strstr_linear=no\n\ndefine Host/Clean\n\t-$(MAKE) -C $(HOST_BUILD_DIR) uninstall\n\t$(call Host/Clean/Default)\nendef\n\n$(eval $(call HostBuild))\n"
  },
  {
    "path": "tools/make-ext4fs/Makefile",
    "content": "#\n# Copyright (C) 2015 OpenWrt.org\n# Copyright (C) 2016 LEDE project\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=make-ext4fs\n\nPKG_SOURCE_URL=$(PROJECT_GIT)/project/make_ext4fs.git\nPKG_SOURCE_PROTO:=git\nPKG_SOURCE_DATE:=2020-01-05\nPKG_SOURCE_VERSION:=5c201be7d72aff735da27e17c29852e0cefe3e52\nPKG_MIRROR_HASH:=a9b74b7b95acc84a5a5c33d6acf493faad8f161caca3180734d9bd383c9d823f\n\ninclude $(INCLUDE_DIR)/host-build.mk\n\ndefine Host/Install\n\t$(INSTALL_BIN) $(HOST_BUILD_DIR)/make_ext4fs $(STAGING_DIR_HOST)/bin/\nendef\n\ndefine Host/Clean\n\trm -f $(STAGING_DIR_HOST)/bin/make_ext4fs\nendef\n\n$(eval $(call HostBuild))\n"
  },
  {
    "path": "tools/meson/Makefile",
    "content": "include $(TOPDIR)/rules.mk\n\nPKG_NAME:=meson\nPKG_VERSION:=0.61.4\n\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz\nPKG_SOURCE_URL:=https://github.com/mesonbuild/meson/releases/download/$(PKG_VERSION)\nPKG_HASH:=4e3733ddc66bac38e38c63b739c9b8b8fc5a866de5333396b0c85c2b144ddee9\n\nPKG_MAINTAINER:=Andre Heider <a.heider@gmail.com>\nPKG_LICENSE:=Apache-2.0\nPKG_LICENSE_FILES:=COPYING\n\ninclude $(INCLUDE_DIR)/host-build.mk\n\ndefine Host/Configure\nendef\n\ndefine Host/Compile\nendef\n\ndefine Host/Install\n\t$(INSTALL_DIR) $(STAGING_DIR_HOST)/bin\n\t$(HOST_BUILD_DIR)/packaging/create_zipapp.py $(HOST_BUILD_DIR) --outfile $(STAGING_DIR_HOST)/bin/meson.py\n\t$(INSTALL_DIR) $(STAGING_DIR_HOST)/lib/meson\n\t$(INSTALL_CONF) files/openwrt-cross.txt.in $(STAGING_DIR_HOST)/lib/meson/\n\t$(INSTALL_CONF) files/openwrt-native.txt.in $(STAGING_DIR_HOST)/lib/meson/\nendef\n\ndefine Host/Clean\n\t$(call Host/Clean/Default)\n\trm -rf $(STAGING_DIR_HOST)/lib/meson\nendef\n\n$(eval $(call HostBuild))\n"
  },
  {
    "path": "tools/meson/files/openwrt-cross.txt.in",
    "content": "[binaries]\nc = [@CC@]\ncpp = [@CXX@]\nar = '@AR@'\nstrip = '@STRIP@'\nnm = '@NM@'\npkgconfig = '@PKGCONFIG@'\ncmake = '@CMAKE@'\npython = '@PYTHON@'\n\n[built-in options]\nc_args = [@CFLAGS@]\nc_link_args = [@LDFLAGS@]\ncpp_args = [@CXXFLAGS@]\ncpp_link_args = [@LDFLAGS@]\nprefix = '/usr'\n\n[host_machine]\nsystem = 'linux'\ncpu_family = '@ARCH@'\ncpu = '@CPU@'\nendian = '@ENDIAN@'\n\n[properties]\nneeds_exe_wrapper = true\n"
  },
  {
    "path": "tools/meson/files/openwrt-native.txt.in",
    "content": "[binaries]\nc = [@CC@]\ncpp = [@CXX@]\npkgconfig = '@PKGCONFIG@'\ncmake = '@CMAKE@'\npython = '@PYTHON@'\n\n[built-in options]\nc_args = [@CFLAGS@]\nc_link_args = [@LDFLAGS@]\ncpp_args = [@CXXFLAGS@]\ncpp_link_args = [@LDFLAGS@]\nprefix = '@PREFIX@'\nsbindir = 'bin'\nlibdir = 'lib'\n"
  },
  {
    "path": "tools/missing-macros/Makefile",
    "content": "#\n# Copyright (C) 2010-2015 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=missing-macros\nPKG_RELEASE:=11\n\ninclude $(INCLUDE_DIR)/host-build.mk\n\ndefine Host/Configure\nendef\n\ndefine Host/Compile\nendef\n\ndefine Host/Install\n\t$(INSTALL_DIR) $(STAGING_DIR_HOST)/share/aclocal\n\t$(INSTALL_DATA) ./src/m4/*.m4 $(STAGING_DIR_HOST)/share/aclocal/\n\t$(INSTALL_DIR) $(STAGING_DIR_HOST)/bin\n\t$(INSTALL_BIN) ./src/bin/* $(STAGING_DIR_HOST)/bin/\nendef\n\n$(eval $(call HostBuild))\n"
  },
  {
    "path": "tools/missing-macros/src/README",
    "content": "The m4/ directory below contains various m4 macros used\nby different packages in the OpenWrt feed.\n\n\nFrom GNU gettext:\nLibrary linking and rpath helper macros.\n\n  lib-ld.m4\n  lib-link.m4\n  lib-prefix.m4\n\nInteger data type test macros.\n\n  intmax.m4\n  wint_t.m4\n  inttypes-pri.m4\n  uintmax_t.m4\n  stdint_h.m4\n  intdiv0.m4\n  inttypes_h.m4\n\nProgram test macro.\n\n  progtest.m4\n\nGNU libc version test macros.\n\n  glibc2.m4\n  glibc21.m4\n\n\nFrom UCL and LZO:\nCompiler ACC conformance testing macros.\n\n  mfx_acc.m4\n  mfx_cppflags.m4\n  mfx_limits.m4\n\n\nFrom OSSP-JS:\nTest macros for va_copy() implementations.\n\n  va_copy.m4\n\n\nFrom libmikmod:\nFeature test macros for the Enlightment Sound Daemon.\n\n  esd.m4\n\n\nFrom libdnet:\nFeature test macros for socket api implementations.\n\n  dnet.m4\n\n\nFrom FLAC:\nXMMS feature detection macros.\n\n  xmms.m4\n\n\nFrom ao:\nDirectory expansion macro for Automake.\n\n  as-ac-expand.m4\n\n\nFrom tinyproxy:\nAutostars m4 macro for detection of compiler flags.\n\n  as-compiler-flags.m4\n\n\nFrom morituri:\nAutostars m4 macro for versioning.\n\n  as-version.m4\n\n\nFrom liboil:\nCheck if unaligned memory access works correctly.\n\n  as-unaligned-access.m4\n\n\nFrom OpenWrt:\nAlways disable GTK docs.\n\n  fake-gtk-doc-check.m4\n\nProvide intltool.m4 stubs to allow for autoreconf.\n\n  fake-intltool.m4\n\nFrom XDM:\nXAW macros.\n\n  xaw.m4\n"
  },
  {
    "path": "tools/missing-macros/src/bin/help2man",
    "content": "#!/usr/bin/env perl\n\nuse strict;\nuse Getopt::Long;\n\nmy $output;\nmy $version;\n\nGetopt::Long::Configure('pass_through');\nGetopt::Long::GetOptions(\n\t'output=s' => \\$output,\n\t'version'  => \\$version\n);\n\nif ($version)\n{\n\tprintf \"OpenWrt help2man 1.40.10\\n\";\n\texit 0;\n}\nelsif ($output)\n{\n\topen O, \"> $output\" || die \"Unable to open $output: $!\\n\";\n\tprint O \"Dummy man page.\\n\";\n\tclose O;\n}\nelse\n{\n\tprint O \"Dummy man page.\\n\";\n}\n"
  },
  {
    "path": "tools/missing-macros/src/bin/makeinfo",
    "content": "#!/usr/bin/env perl\n\nuse strict;\nuse Getopt::Long;\n\nmy $output;\nmy $version;\nmy $docbook;\nmy $html;\nmy $xml;\nmy $plaintext;\nmy $no_split;\nmy $no_headers;\n\nGetopt::Long::Configure('pass_through');\nGetopt::Long::GetOptions(\n\t'output=s'   => \\$output,\n\t'version'    => \\$version,\n\t'no-split'   => \\$no_split,\n\t'no-headers' => \\$no_headers,\n\t'docbook'    => \\$docbook,\n\t'html'       => \\$html,\n\t'xml'        => \\$xml,\n\t'plaintext'  => \\$plaintext\n);\n\nif ($version)\n{\n\tprint \"makeinfo (OpenWrt stub) 4.13\\n\";\n\texit 0;\n}\n\n\nsub output_filename\n{\n\tmy $path = shift || return;\n\tmy $name = $path;\n\tmy $setfile;\n\n\tif (open F, \"< $path\")\n\t{\n\t\twhile (defined(my $line = readline F))\n\t\t{\n\t\t\tif ($line =~ /\\@setfilename\\s+(\\S+)/)\n\t\t\t{\n\t\t\t\t$setfile = $1;\n\t\t\t\t$setfile =~ s!^.+/!!;\n\t\t\t\tlast;\n\t\t\t}\n\t\t}\n\n\t\tclose F;\n\t}\n\n\t$name =~ s!^.+/!!;\n\t$name =~ s!\\.[^.]+$!!;\n\n\tif ($html)\n\t{\n\t\t$setfile =~ s!\\.[^.]+$!! if $setfile;\n\n\t\tif ($no_split)\n\t\t{\n\t\t\treturn $setfile ? \"$setfile.html\" : \"$name.html\" unless $output;\n\t\t\treturn $output;\n\t\t}\n\n\t\treturn $setfile ? \"$setfile/index.html\" : \"$name/index.html\" unless $output;\n\t\treturn \"$output/index.html\";\n\t}\n\telsif ($xml || $docbook)\n\t{\n\t\t$setfile =~ s!\\.[^.]+$!! if $setfile;\n\n\t\treturn $setfile ? \"$setfile.xml\" : \"$name.info\" unless $output;\n\t\treturn $output;\n\t}\n\telsif ($plaintext)\n\t{\n\t\treturn ($output || \"-\");\t\n\t}\n\n\treturn ($output || $setfile || \"$name.info\");\n}\n\nforeach my $arg (@ARGV)\n{\n\tnext unless -f $arg;\n\n\tmy $out = output_filename($arg);\n\tif ($out =~ m!^(.+/)[^/]+$!)\n\t{\n\t\tsystem(\"mkdir\", \"-p\", $1);\n\t}\n\n\tmy $fd = \\*STDOUT;\n\tif ($out ne \"-\" && !$no_headers)\n\t{\n\t\topen $fd, \"> $out\" || die \"Can't open $out: $!\\n\";\n\t}\n\n\tif ($html || $xml || $docbook)\n\t{\n\t\tprint $fd \"<!-- Dummy output for $arg -->\\n\";\n\t}\n\telse\n\t{\n\t\tprint $fd \"Dummy output for $arg\\n\";\t\n\t}\n\n\tclose $fd;\n}\n"
  },
  {
    "path": "tools/missing-macros/src/m4/as-ac-expand.m4",
    "content": "dnl as-ac-expand.m4 0.2.0\ndnl autostars m4 macro for expanding directories using configure's prefix\ndnl thomas@apestaart.org\n\ndnl AS_AC_EXPAND(VAR, CONFIGURE_VAR)\ndnl example\ndnl AS_AC_EXPAND(SYSCONFDIR, $sysconfdir)\ndnl will set SYSCONFDIR to /usr/local/etc if prefix=/usr/local\n\nAC_DEFUN([AS_AC_EXPAND],\n[\n  EXP_VAR=[$1]\n  FROM_VAR=[$2]\n\n  dnl first expand prefix and exec_prefix if necessary\n  prefix_save=$prefix\n  exec_prefix_save=$exec_prefix\n\n  dnl if no prefix given, then use /usr/local, the default prefix\n  if test \"x$prefix\" = \"xNONE\"; then\n    prefix=\"$ac_default_prefix\"\n  fi\n  dnl if no exec_prefix given, then use prefix\n  if test \"x$exec_prefix\" = \"xNONE\"; then\n    exec_prefix=$prefix\n  fi\n\n  full_var=\"$FROM_VAR\"\n  dnl loop until it doesn't change anymore\n  while true; do\n    new_full_var=\"`eval echo $full_var`\"\n    if test \"x$new_full_var\" = \"x$full_var\"; then break; fi\n    full_var=$new_full_var\n  done\n\n  dnl clean up\n  full_var=$new_full_var\n  AC_SUBST([$1], \"$full_var\")\n\n  dnl restore prefix and exec_prefix\n  prefix=$prefix_save\n  exec_prefix=$exec_prefix_save\n])\n"
  },
  {
    "path": "tools/missing-macros/src/m4/as-compiler-flag.m4",
    "content": "dnl as-compiler-flag.m4 0.1.0\n\ndnl autostars m4 macro for detection of compiler flags\n\ndnl David Schleef <ds@schleef.org>\n\ndnl $Id: as-compiler-flag.m4,v 1.1 2005/12/15 23:35:19 ds Exp $\n\ndnl AS_COMPILER_FLAG(CFLAGS, ACTION-IF-ACCEPTED, [ACTION-IF-NOT-ACCEPTED])\ndnl Tries to compile with the given CFLAGS.\ndnl Runs ACTION-IF-ACCEPTED if the compiler can compile with the flags,\ndnl and ACTION-IF-NOT-ACCEPTED otherwise.\n\nAC_DEFUN([AS_COMPILER_FLAG],\n[\n  AC_MSG_CHECKING([to see if compiler understands $1])\n\n  save_CFLAGS=\"$CFLAGS\"\n  CFLAGS=\"$CFLAGS $1\"\n\n  AC_TRY_COMPILE([ ], [], [flag_ok=yes], [flag_ok=no])\n  CFLAGS=\"$save_CFLAGS\"\n\n  if test \"X$flag_ok\" = Xyes ; then\n    m4_ifvaln([$2],[$2])\n    true\n  else\n    m4_ifvaln([$3],[$3])\n    true\n  fi\n  AC_MSG_RESULT([$flag_ok])\n])\n\ndnl AS_COMPILER_FLAGS(VAR, FLAGS)\ndnl Tries to compile with the given CFLAGS.\n\nAC_DEFUN([AS_COMPILER_FLAGS],\n[\n  list=$2\n  flags_supported=\"\"\n  flags_unsupported=\"\"\n  AC_MSG_CHECKING([for supported compiler flags])\n  for each in $list\n  do\n    save_CFLAGS=\"$CFLAGS\"\n    CFLAGS=\"$CFLAGS $each\"\n    AC_TRY_COMPILE([ ], [], [flag_ok=yes], [flag_ok=no])\n    CFLAGS=\"$save_CFLAGS\"\n\n    if test \"X$flag_ok\" = Xyes ; then\n      flags_supported=\"$flags_supported $each\"\n    else\n      flags_unsupported=\"$flags_unsupported $each\"\n    fi\n  done\n  AC_MSG_RESULT([$flags_supported])\n  if test \"X$flags_unsupported\" != X ; then\n    AC_MSG_WARN([unsupported compiler flags: $flags_unsupported])\n  fi\n  $1=\"$$1 $flags_supported\"\n])\n\n"
  },
  {
    "path": "tools/missing-macros/src/m4/as-unaligned-access.m4",
    "content": "dnl AS_UNALIGNED_ACCESS\n\ndnl check if unaligned memory access works correctly\nAC_DEFUN([AS_UNALIGNED_ACCESS], [\n  AC_MSG_CHECKING([if unaligned memory access works correctly])\n  if test x\"$as_cv_unaligned_access\" = x ; then\n    case $host in\n      alpha*|arm*|hp*|mips*|sh*|sparc*|ia64*)\n        _AS_ECHO_N([(blacklisted) ])\n        as_cv_unaligned_access=no\n\t;;\n      i?86*|x86_64|amd64|powerpc*|m68k*|cris*)\n        _AS_ECHO_N([(whitelisted) ])\n        as_cv_unaligned_access=yes\n\t;;\n    esac\n  else\n    _AS_ECHO_N([(cached) ])\n  fi\n  if test x\"$as_cv_unaligned_access\" = x ; then\n    AC_TRY_RUN([\nint main(int argc, char **argv)\n{\n  char array[] = \"ABCDEFGH\";\n  unsigned int iarray[2];\n  memcpy(iarray,array,8);\n#define GET(x) (*(unsigned int *)((char *)iarray + (x)))\n  if(GET(0) != 0x41424344 && GET(0) != 0x44434241) return 1;\n  if(GET(1) != 0x42434445 && GET(1) != 0x45444342) return 1;\n  if(GET(2) != 0x43444546 && GET(2) != 0x46454443) return 1;\n  if(GET(3) != 0x44454647 && GET(3) != 0x47464544) return 1;\n  return 0;\n}\n    ], as_cv_unaligned_access=\"yes\", as_cv_unaligned_access=\"no\")\n  fi\n  AC_MSG_RESULT($as_cv_unaligned_access)\n  if test \"$as_cv_unaligned_access\" = \"yes\"; then\n    AC_DEFINE_UNQUOTED(HAVE_UNALIGNED_ACCESS, 1,\n      [defined if unaligned memory access works correctly])\n  fi\n])\n"
  },
  {
    "path": "tools/missing-macros/src/m4/as-version.m4",
    "content": "dnl as-version.m4 0.2.0\n\ndnl autostars m4 macro for versioning\n\ndnl Thomas Vander Stichele <thomas at apestaart dot org>\n\ndnl $Id: as-version.m4,v 1.4 2004/06/01 09:40:05 thomasvs Exp $\n\ndnl AS_VERSION\n\ndnl example\ndnl AS_VERSION\n\ndnl this macro\ndnl - AC_SUBST's PACKAGE_VERSION_MAJOR, _MINOR, _MICRO\ndnl - AC_SUBST's PACKAGE_VERSION_RELEASE,\ndnl    which can be used for rpm release fields\ndnl - doesn't call AM_INIT_AUTOMAKE anymore because it prevents\ndnl   maintainer mode from running correctly\ndnl\ndnl don't forget to put #undef PACKAGE_VERSION_RELEASE in acconfig.h\ndnl if you use acconfig.h\n\nAC_DEFUN([AS_VERSION],\n[\n  PACKAGE_VERSION_MAJOR=$(echo AC_PACKAGE_VERSION | cut -d'.' -f1)\n  PACKAGE_VERSION_MINOR=$(echo AC_PACKAGE_VERSION | cut -d'.' -f2)\n  PACKAGE_VERSION_MICRO=$(echo AC_PACKAGE_VERSION | cut -d'.' -f3)\n\n  AC_SUBST(PACKAGE_VERSION_MAJOR)\n  AC_SUBST(PACKAGE_VERSION_MINOR)\n  AC_SUBST(PACKAGE_VERSION_MICRO)\n])\n\ndnl AS_NANO(ACTION-IF-NO-NANO, [ACTION-IF-NANO])\n\ndnl requires AC_INIT to be called before\ndnl For projects using a fourth or nano number in your versioning to indicate\ndnl development or prerelease snapshots, this macro allows the build to be\ndnl set up differently accordingly.\n\ndnl this macro:\ndnl - parses AC_PACKAGE_VERSION, set by AC_INIT, and extracts the nano number\ndnl - sets the variable PACKAGE_VERSION_NANO\ndnl - sets the variable PACKAGE_VERSION_RELEASE, which can be used\ndnl   for rpm release fields\ndnl - executes ACTION-IF-NO-NANO or ACTION-IF-NANO\n    \ndnl example:\ndnl AS_NANO(RELEASE=\"yes\", RELEASE=\"no\")\n\nAC_DEFUN([AS_NANO],\n[\n  AC_MSG_CHECKING(nano version)\n\n  NANO=$(echo AC_PACKAGE_VERSION | cut -d'.' -f4)\n\n  if test x\"$NANO\" = x || test \"x$NANO\" = \"x0\" ; then\n    AC_MSG_RESULT([0 (release)])\n    NANO=0\n    PACKAGE_VERSION_RELEASE=1\n    ifelse([$1], , :, [$1])\n  else\n    AC_MSG_RESULT($NANO)\n    PACKAGE_VERSION_RELEASE=0.`date +%Y%m%d.%H%M%S`\n    ifelse([$2], , :, [$2])\n  fi\n  PACKAGE_VERSION_NANO=$NANO\n  AC_SUBST(PACKAGE_VERSION_NANO)\n  AC_SUBST(PACKAGE_VERSION_RELEASE)\n])\n"
  },
  {
    "path": "tools/missing-macros/src/m4/dnet.m4",
    "content": "# dnet.m4 serial 1 (libdnet-1.11)\n\ndnl\ndnl Check for 4.4 BSD sa_len member in sockaddr struct\ndnl\ndnl usage:\tAC_DNET_SOCKADDR_SA_LEN\ndnl results:\tHAVE_SOCKADDR_SA_LEN (defined)\ndnl\nAC_DEFUN([AC_DNET_SOCKADDR_SA_LEN],\n    [AC_MSG_CHECKING(for sa_len in sockaddr struct)\n    AC_CACHE_VAL(ac_cv_dnet_sockaddr_has_sa_len,\n        AC_TRY_COMPILE([\n# ifndef _SOCKADDR_LEN\n#\tdefine _SOCKADDR_LEN 1 \n# endif\n#       include <sys/types.h>\n#       include <sys/socket.h>],\n        [u_int i = sizeof(((struct sockaddr *)0)->sa_len)],\n        ac_cv_dnet_sockaddr_has_sa_len=yes,\n        ac_cv_dnet_sockaddr_has_sa_len=no))\n    AC_MSG_RESULT($ac_cv_dnet_sockaddr_has_sa_len)\n    if test $ac_cv_dnet_sockaddr_has_sa_len = yes ; then\n            AC_DEFINE(HAVE_SOCKADDR_SA_LEN, 1,\n                      [Define if sockaddr struct has sa_len.])\n    fi])\n\ndnl\ndnl Check for sockaddr_in6 struct in <netinet/in.h>\ndnl\ndnl usage:\tAC_DNET_SOCKADDR_IN6\ndnl results:\tHAVE_SOCKADDR_IN6\ndnl\nAC_DEFUN([AC_DNET_SOCKADDR_IN6],\n    [AC_MSG_CHECKING(for sockaddr_in6 struct in <netinet/in.h>)\n    AC_CACHE_VAL(ac_cv_dnet_netinet_in_h_has_sockaddr_in6,\n        AC_TRY_COMPILE([\n#       include <sys/types.h>\n#\tinclude <sys/socket.h>\n#       include <netinet/in.h>],\n        [struct sockaddr_in6 sin6; sin6.sin6_family = AF_INET6;],\n\tac_cv_dnet_netinet_in_h_has_sockaddr_in6=yes,\n\tac_cv_dnet_netinet_in_h_has_sockaddr_in6=no))\n    AC_MSG_RESULT($ac_cv_dnet_netinet_in_h_has_sockaddr_in6)\n    if test $ac_cv_dnet_netinet_in_h_has_sockaddr_in6 = yes ; then\n        AC_DEFINE(HAVE_SOCKADDR_IN6, 1,\n\t          [Define if <netinet/in.h> has sockaddr_in6 struct.])\n    fi])\n\ndnl\ndnl Check for arp_dev member in arpreq struct\ndnl\ndnl usage:\tAC_DNET_ARPREQ_ARP_DEV\ndnl results:\tHAVE_ARPREQ_ARP_DEV (defined)\ndnl\nAC_DEFUN([AC_DNET_ARPREQ_ARP_DEV],\n    [AC_MSG_CHECKING(for arp_dev in arpreq struct)\n    AC_CACHE_VAL(ac_cv_dnet_arpreq_has_arp_dev,\n\tAC_TRY_COMPILE([\n#       include <sys/types.h>\n#\tinclude <sys/socket.h>\n#\tinclude <net/if_arp.h>],\n\t[void *p = ((struct arpreq *)0)->arp_dev],\n\tac_cv_dnet_arpreq_has_arp_dev=yes,\n\tac_cv_dnet_arpreq_has_arp_dev=no))\n    AC_MSG_RESULT($ac_cv_dnet_arpreq_has_arp_dev)\n    if test $ac_cv_dnet_arpreq_has_arp_dev = yes ; then\n\tAC_DEFINE(HAVE_ARPREQ_ARP_DEV, 1,\n\t\t[Define if arpreq struct has arp_dev.])\n    fi])\n\ndnl\ndnl Check for rt_msghdr struct in <net/route.h>\ndnl\ndnl usage:\tAC_DNET_ROUTE_RT_MSGHDR\ndnl results:\tHAVE_ROUTE_RT_MSGHDR\ndnl\nAC_DEFUN([AC_DNET_ROUTE_RT_MSGHDR],\n    [AC_MSG_CHECKING(for rt_msghdr struct in <net/route.h>)\n    AC_CACHE_VAL(ac_cv_dnet_route_h_has_rt_msghdr,\n        AC_TRY_COMPILE([\n#       include <sys/types.h>\n#       include <sys/socket.h>\n#       include <net/if.h>\n#       include <net/route.h>],\n        [struct rt_msghdr rtm; rtm.rtm_msglen = 0;],\n\tac_cv_dnet_route_h_has_rt_msghdr=yes,\n\tac_cv_dnet_route_h_has_rt_msghdr=no))\n    AC_MSG_RESULT($ac_cv_dnet_route_h_has_rt_msghdr)\n    if test $ac_cv_dnet_route_h_has_rt_msghdr = yes ; then\n        AC_DEFINE(HAVE_ROUTE_RT_MSGHDR, 1,\n\t          [Define if <net/route.h> has rt_msghdr struct.])\n    fi])\n\ndnl\ndnl Check for the Berkeley Packet Filter\ndnl\ndnl usage:\tAC_DNET_BSD_BPF\ndnl results:\tHAVE_BSD_BPF\ndnl\nAC_DEFUN([AC_DNET_BSD_BPF],\n    [AC_MSG_CHECKING(for Berkeley Packet Filter)\n    AC_CACHE_VAL(ac_cv_dnet_bsd_bpf,\n\tif test -c /dev/bpf0 ; then\n\t    ac_cv_dnet_bsd_bpf=yes\n\telse\n\t    ac_cv_dnet_bsd_bpf=no\n\tfi)\n    AC_MSG_RESULT($ac_cv_dnet_bsd_bpf)\n    if test $ac_cv_dnet_bsd_bpf = yes ; then\n\tAC_DEFINE(HAVE_BSD_BPF, 1,\n\t\t  [Define if you have the Berkeley Packet Filter.])\n    fi])\n\ndnl\ndnl Check for the Linux /proc filesystem\ndnl\ndnl usage:\tAC_DNET_LINUX_PROCFS\ndnl results:\tHAVE_LINUX_PROCFS\ndnl\nAC_DEFUN([AC_DNET_LINUX_PROCFS],\n    [AC_MSG_CHECKING(for Linux proc filesystem)\n    AC_CACHE_VAL(ac_cv_dnet_linux_procfs,\n\tif test \"x`cat /proc/sys/kernel/ostype 2>&-`\" = \"xLinux\" ; then\n\t    ac_cv_dnet_linux_procfs=yes\n        else\n\t    ac_cv_dnet_linux_procfs=no\n\tfi)\n    AC_MSG_RESULT($ac_cv_dnet_linux_procfs)\n    if test $ac_cv_dnet_linux_procfs = yes ; then\n\tAC_DEFINE(HAVE_LINUX_PROCFS, 1,\n\t\t  [Define if you have the Linux /proc filesystem.])\n    fi])\n\ndnl\ndnl Check for Linux PF_PACKET sockets\ndnl\ndnl usage:\tAC_DNET_LINUX_PF_PACKET\ndnl results:\tHAVE_LINUX_PF_PACKET\ndnl\nAC_DEFUN([AC_DNET_LINUX_PF_PACKET],\n    [AC_MSG_CHECKING(for Linux PF_PACKET sockets)\n    AC_CACHE_VAL(ac_cv_dnet_linux_pf_packet,\n\tif test -f /usr/include/netpacket/packet.h ; then\n\t    ac_cv_dnet_linux_pf_packet=yes\n\telse\n\t    ac_cv_dnet_linux_pf_packet=no\n\tfi)\n    AC_MSG_RESULT($ac_cv_dnet_linux_pf_packet)\n    if test $ac_cv_dnet_linux_pf_packet = yes ; then\n\tAC_DEFINE(HAVE_LINUX_PF_PACKET, 1,\n\t\t  [Define if you have Linux PF_PACKET sockets.])\n    fi])\n\ndnl\ndnl Check for SNMP MIB2 STREAMS (Solaris only?)\ndnl\ndnl usage:      AC_DNET_STREAMS_MIB2\ndnl results:    HAVE_STREAMS_MIB2\ndnl\nAC_DEFUN([AC_DNET_STREAMS_MIB2],\n    [AC_MSG_CHECKING(for SNMP MIB2 STREAMS)\n    AC_CACHE_VAL(ac_cv_dnet_streams_mib2,\n        if test -f /usr/include/inet/mib2.h -a -c /dev/ip ; then\n            ac_cv_dnet_streams_mib2=yes\n        else\n            ac_cv_dnet_streams_mib2=no\n        fi)\n    AC_MSG_RESULT($ac_cv_dnet_streams_mib2)\n    if test $ac_cv_dnet_streams_mib2 = yes ; then\n        AC_DEFINE(HAVE_STREAMS_MIB2, 1,\n                  [Define if you have SNMP MIB2 STREAMS.])\n    fi])\n\ndnl\ndnl Check for route(7) STREAMS (UnixWare only?)\ndnl\ndnl usage:      AC_DNET_STREAMS_ROUTE\ndnl results:    HAVE_STREAMS_ROUTE\ndnl\nAC_DEFUN([AC_DNET_STREAMS_ROUTE],\n    [AC_MSG_CHECKING(for route(7) STREAMS)\n    AC_CACHE_VAL(ac_cv_dnet_streams_route,\n        if grep RTSTR_SEND /usr/include/net/route.h >/dev/null 2>&1 ; then\n            ac_cv_dnet_streams_route=yes\n        else\n            ac_cv_dnet_streams_route=no\n        fi)\n    AC_MSG_RESULT($ac_cv_dnet_streams_route)\n    if test $ac_cv_dnet_streams_route = yes ; then\n        AC_DEFINE(HAVE_STREAMS_ROUTE, 1,\n                  [Define if you have route(7) STREAMS.])\n    fi])\n\ndnl\ndnl Check for arp(7) ioctls\ndnl\ndnl usage:      AC_DNET_IOCTL_ARP\ndnl results:    HAVE_IOCTL_ARP\ndnl\nAC_DEFUN([AC_DNET_IOCTL_ARP],\n    [AC_MSG_CHECKING(for arp(7) ioctls)\n    AC_CACHE_VAL(ac_cv_dnet_ioctl_arp,\n\tAC_EGREP_CPP(werd, [\n#\tinclude <sys/types.h>\n#\tdefine BSD_COMP\n#\tinclude <sys/ioctl.h>\n#\tifdef SIOCGARP\n\twerd\n#\tendif],\n\tac_cv_dnet_ioctl_arp=yes,\n\tac_cv_dnet_ioctl_arp=no))\n    case \"$host_os\" in\n    irix*)\n        ac_cv_dnet_ioctl_arp=no ;;\n    esac\n    AC_MSG_RESULT($ac_cv_dnet_ioctl_arp)\n    if test $ac_cv_dnet_ioctl_arp = yes ; then\n        AC_DEFINE(HAVE_IOCTL_ARP, 1,\n                  [Define if you have arp(7) ioctls.])\n    fi])\n\ndnl\ndnl Check for raw IP sockets ip_{len,off} host byte ordering\ndnl\ndnl usage:      AC_DNET_RAWIP_HOST_OFFLEN\ndnl results:    HAVE_RAWIP_HOST_OFFLEN\ndnl\nAC_DEFUN([AC_DNET_RAWIP_HOST_OFFLEN],\n    [AC_MSG_CHECKING([for raw IP sockets ip_{len,off} host byte ordering])\n    AC_CACHE_VAL(ac_cv_dnet_rawip_host_offlen, [\n\tcase \"$host_os\" in\n\t*openbsd*)\n\t    ac_cv_dnet_rawip_host_offlen=no ;;\n\t*bsd*|*osf*|*unixware*)\n\t    ac_cv_dnet_rawip_host_offlen=yes ;;\n\t*)\n\t    ac_cv_dnet_rawip_host_offlen=no ;;\n\tesac])\n    AC_MSG_RESULT($ac_cv_dnet_rawip_host_offlen)\n    if test $ac_cv_dnet_rawip_host_offlen = yes ; then\n        AC_DEFINE(HAVE_RAWIP_HOST_OFFLEN, 1,\n                  [Define if raw IP sockets require host byte ordering for ip_off, ip_len.])\n    fi])\n\ndnl\ndnl Check for cooked raw IP sockets\ndnl\ndnl usage:      AC_DNET_RAWIP_COOKED\ndnl results:    HAVE_RAWIP_COOKED\ndnl\nAC_DEFUN([AC_DNET_RAWIP_COOKED],\n    [AC_MSG_CHECKING(for cooked raw IP sockets)\n    AC_CACHE_VAL(ac_cv_dnet_rawip_cooked, [\n\tcase \"$host_os\" in\n\tsolaris*|irix*)\n\t    ac_cv_dnet_rawip_cooked=yes ;;\n\t*)\n\t    ac_cv_dnet_rawip_cooked=no ;;\n\tesac])\n    AC_MSG_RESULT($ac_cv_dnet_rawip_cooked)\n    if test $ac_cv_dnet_rawip_cooked = yes ; then\n        AC_DEFINE(HAVE_RAWIP_COOKED, 1,\n                  [Define if you have cooked raw IP sockets.])\n    fi])\n\ndnl\ndnl AC_LBL_LIBRARY_NET\ndnl\ndnl This test is for network applications that need socket() and\ndnl gethostbyname() -ish functions.  Under Solaris, those applications\ndnl need to link with \"-lsocket -lnsl\".  Under IRIX, they need to link\ndnl with \"-lnsl\" but should *not* link with \"-lsocket\" because\ndnl libsocket.a breaks a number of things (for instance:\ndnl gethostbyname() under IRIX 5.2, and snoop sockets under most\ndnl versions of IRIX).\ndnl\ndnl Unfortunately, many application developers are not aware of this,\ndnl and mistakenly write tests that cause -lsocket to be used under\ndnl IRIX.  It is also easy to write tests that cause -lnsl to be used\ndnl under operating systems where neither are necessary (or useful),\ndnl such as SunOS 4.1.4, which uses -lnsl for TLI.\ndnl\ndnl This test exists so that every application developer does not test\ndnl this in a different, and subtly broken fashion.\n\ndnl It has been argued that this test should be broken up into two\ndnl seperate tests, one for the resolver libraries, and one for the\ndnl libraries necessary for using Sockets API. Unfortunately, the two\ndnl are carefully intertwined and allowing the autoconf user to use\ndnl them independantly potentially results in unfortunate ordering\ndnl dependancies -- as such, such component macros would have to\ndnl carefully use indirection and be aware if the other components were\ndnl executed. Since other autoconf macros do not go to this trouble,\ndnl and almost no applications use sockets without the resolver, this\ndnl complexity has not been implemented.\ndnl\ndnl The check for libresolv is in case you are attempting to link\ndnl statically and happen to have a libresolv.a lying around (and no\ndnl libnsl.a).\ndnl\nAC_DEFUN([AC_LBL_LIBRARY_NET], [\n    # Most operating systems have gethostbyname() in the default searched\n    # libraries (i.e. libc):\n    AC_CHECK_FUNC(gethostbyname, ,\n        # Some OSes (eg. Solaris) place it in libnsl:\n        AC_CHECK_LIB(nsl, gethostbyname, , \n            # Some strange OSes (SINIX) have it in libsocket:\n            AC_CHECK_LIB(socket, gethostbyname, ,\n                # Unfortunately libsocket sometimes depends on libnsl.\n                # AC_CHECK_LIB's API is essentially broken so the\n                # following ugliness is necessary:\n                AC_CHECK_LIB(socket, gethostbyname,\n                    LIBS=\"-lsocket -lnsl $LIBS\",\n                    AC_CHECK_LIB(resolv, gethostbyname),\n                    -lnsl))))\n    AC_CHECK_FUNC(socket, , AC_CHECK_LIB(socket, socket, ,\n        AC_CHECK_LIB(socket, socket, LIBS=\"-lsocket -lnsl $LIBS\", ,\n            -lnsl)))\n    # DLPI needs putmsg under HPUX so test for -lstr while we're at it\n    AC_CHECK_LIB(str, putmsg)\n    ])\n\n"
  },
  {
    "path": "tools/missing-macros/src/m4/fake-gtk-doc-check.m4",
    "content": "dnl fake-gtk-doc-check.m4 serial 1 (OpenWrt)\ndnl Provide a fake GTK_DOC_CHECK macros which\ndnl always defines false.\n\nAC_DEFUN([GTK_DOC_CHECK],\n[\n\tAM_CONDITIONAL([ENABLE_GTK_DOC], [false])\n\tAM_CONDITIONAL([GTK_DOC_BUILD_HTML], [false])\n\tAM_CONDITIONAL([GTK_DOC_BUILD_PDF], [false])\n\tAM_CONDITIONAL([GTK_DOC_USE_LIBTOOL], [false])\n\tAM_CONDITIONAL([GTK_DOC_USE_REBASE], [false])\n\tAC_PATH_PROGS([GTKDOC_REBASE],[true],[true])\n])\n"
  },
  {
    "path": "tools/missing-macros/src/m4/fake-intltool.m4",
    "content": "# stripped intltool.m4 to make automake happy\n# serial 1\nAC_DEFUN([IT_PROG_INTLTOOL],\n[\n\tAC_SUBST(ALL_LINGUAS)\n\t\n\tDATADIRNAME=share\n\tAC_SUBST(DATADIRNAME)\n])\n\n# deprecated macros\nAU_ALIAS([AC_PROG_INTLTOOL], [IT_PROG_INTLTOOL])\n\n# A hint is needed for aclocal from Automake <= 1.9.4:\n# AC_DEFUN([AC_PROG_INTLTOOL], ...)\n\n"
  },
  {
    "path": "tools/missing-macros/src/m4/glibc2.m4",
    "content": "# glibc2.m4 serial 2\ndnl Copyright (C) 2000-2002, 2004, 2008-2010 Free Software Foundation, Inc.\ndnl This file is free software; the Free Software Foundation\ndnl gives unlimited permission to copy and/or distribute it,\ndnl with or without modifications, as long as this notice is preserved.\n\n# Test for the GNU C Library, version 2.0 or newer.\n# From Bruno Haible.\n\nAC_DEFUN([gt_GLIBC2],\n  [\n    AC_CACHE_CHECK([whether we are using the GNU C Library 2 or newer],\n      [ac_cv_gnu_library_2],\n      [AC_EGREP_CPP([Lucky GNU user],\n        [\n#include <features.h>\n#ifdef __GNU_LIBRARY__\n #if (__GLIBC__ >= 2)\n  Lucky GNU user\n #endif\n#endif\n        ],\n        [ac_cv_gnu_library_2=yes],\n        [ac_cv_gnu_library_2=no])\n      ]\n    )\n    AC_SUBST([GLIBC2])\n    GLIBC2=\"$ac_cv_gnu_library_2\"\n  ]\n)\n"
  },
  {
    "path": "tools/missing-macros/src/m4/glibc21.m4",
    "content": "# glibc21.m4 serial 4\ndnl Copyright (C) 2000-2002, 2004, 2008-2010 Free Software Foundation, Inc.\ndnl This file is free software; the Free Software Foundation\ndnl gives unlimited permission to copy and/or distribute it,\ndnl with or without modifications, as long as this notice is preserved.\n\n# Test for the GNU C Library, version 2.1 or newer.\n# From Bruno Haible.\n\nAC_DEFUN([gl_GLIBC21],\n  [\n    AC_CACHE_CHECK([whether we are using the GNU C Library 2.1 or newer],\n      [ac_cv_gnu_library_2_1],\n      [AC_EGREP_CPP([Lucky GNU user],\n        [\n#include <features.h>\n#ifdef __GNU_LIBRARY__\n #if (__GLIBC__ == 2 && __GLIBC_MINOR__ >= 1) || (__GLIBC__ > 2)\n  Lucky GNU user\n #endif\n#endif\n        ],\n        [ac_cv_gnu_library_2_1=yes],\n        [ac_cv_gnu_library_2_1=no])\n      ]\n    )\n    AC_SUBST([GLIBC21])\n    GLIBC21=\"$ac_cv_gnu_library_2_1\"\n  ]\n)\n"
  },
  {
    "path": "tools/missing-macros/src/m4/intdiv0.m4",
    "content": "# intdiv0.m4 serial 3 (gettext-0.18)\ndnl Copyright (C) 2002, 2007-2010 Free Software Foundation, Inc.\ndnl This file is free software; the Free Software Foundation\ndnl gives unlimited permission to copy and/or distribute it,\ndnl with or without modifications, as long as this notice is preserved.\n\ndnl From Bruno Haible.\n\nAC_DEFUN([gt_INTDIV0],\n[\n  AC_REQUIRE([AC_PROG_CC])dnl\n  AC_REQUIRE([AC_CANONICAL_HOST])dnl\n\n  AC_CACHE_CHECK([whether integer division by zero raises SIGFPE],\n    gt_cv_int_divbyzero_sigfpe,\n    [\n      gt_cv_int_divbyzero_sigfpe=\nchangequote(,)dnl\n      case \"$host_os\" in\n        macos* | darwin[6-9]* | darwin[1-9][0-9]*)\n          # On MacOS X 10.2 or newer, just assume the same as when cross-\n          # compiling. If we were to perform the real test, 1 Crash Report\n          # dialog window would pop up.\n          case \"$host_cpu\" in\n            i[34567]86 | x86_64)\n              gt_cv_int_divbyzero_sigfpe=\"guessing yes\" ;;\n          esac\n          ;;\n      esac\nchangequote([,])dnl\n      if test -z \"$gt_cv_int_divbyzero_sigfpe\"; then\n        AC_TRY_RUN([\n#include <stdlib.h>\n#include <signal.h>\n\nstatic void\nsigfpe_handler (int sig)\n{\n  /* Exit with code 0 if SIGFPE, with code 1 if any other signal.  */\n  exit (sig != SIGFPE);\n}\n\nint x = 1;\nint y = 0;\nint z;\nint nan;\n\nint main ()\n{\n  signal (SIGFPE, sigfpe_handler);\n/* IRIX and AIX (when \"xlc -qcheck\" is used) yield signal SIGTRAP.  */\n#if (defined (__sgi) || defined (_AIX)) && defined (SIGTRAP)\n  signal (SIGTRAP, sigfpe_handler);\n#endif\n/* Linux/SPARC yields signal SIGILL.  */\n#if defined (__sparc__) && defined (__linux__)\n  signal (SIGILL, sigfpe_handler);\n#endif\n\n  z = x / y;\n  nan = y / y;\n  exit (1);\n}\n], [gt_cv_int_divbyzero_sigfpe=yes], [gt_cv_int_divbyzero_sigfpe=no],\n          [\n            # Guess based on the CPU.\nchangequote(,)dnl\n            case \"$host_cpu\" in\n              alpha* | i[34567]86 | x86_64 | m68k | s390*)\n                gt_cv_int_divbyzero_sigfpe=\"guessing yes\";;\n              *)\n                gt_cv_int_divbyzero_sigfpe=\"guessing no\";;\n            esac\nchangequote([,])dnl\n          ])\n      fi\n    ])\n  case \"$gt_cv_int_divbyzero_sigfpe\" in\n    *yes) value=1;;\n    *) value=0;;\n  esac\n  AC_DEFINE_UNQUOTED([INTDIV0_RAISES_SIGFPE], [$value],\n    [Define if integer division by zero raises signal SIGFPE.])\n])\n"
  },
  {
    "path": "tools/missing-macros/src/m4/intmax.m4",
    "content": "# intmax.m4 serial 5 (gettext-0.18)\ndnl Copyright (C) 2002-2005, 2008-2010 Free Software Foundation, Inc.\ndnl This file is free software; the Free Software Foundation\ndnl gives unlimited permission to copy and/or distribute it,\ndnl with or without modifications, as long as this notice is preserved.\n\ndnl From Bruno Haible.\ndnl Test whether the system has the 'intmax_t' type, but don't attempt to\ndnl find a replacement if it is lacking.\n\nAC_DEFUN([gt_TYPE_INTMAX_T],\n[\n  AC_REQUIRE([gl_AC_HEADER_INTTYPES_H])\n  AC_REQUIRE([gl_AC_HEADER_STDINT_H])\n  AC_CACHE_CHECK([for intmax_t], [gt_cv_c_intmax_t],\n    [AC_TRY_COMPILE([\n#include <stddef.h>\n#include <stdlib.h>\n#if HAVE_STDINT_H_WITH_UINTMAX\n#include <stdint.h>\n#endif\n#if HAVE_INTTYPES_H_WITH_UINTMAX\n#include <inttypes.h>\n#endif\n],     [intmax_t x = -1;\n        return !x;],\n       [gt_cv_c_intmax_t=yes],\n       [gt_cv_c_intmax_t=no])])\n  if test $gt_cv_c_intmax_t = yes; then\n    AC_DEFINE([HAVE_INTMAX_T], [1],\n      [Define if you have the 'intmax_t' type in <stdint.h> or <inttypes.h>.])\n  fi\n])\n"
  },
  {
    "path": "tools/missing-macros/src/m4/inttypes-pri.m4",
    "content": "# inttypes-pri.m4 serial 6 (gettext-0.18)\ndnl Copyright (C) 1997-2002, 2006, 2008-2010 Free Software Foundation, Inc.\ndnl This file is free software; the Free Software Foundation\ndnl gives unlimited permission to copy and/or distribute it,\ndnl with or without modifications, as long as this notice is preserved.\n\ndnl From Bruno Haible.\n\nAC_PREREQ([2.52])\n\n# Define PRI_MACROS_BROKEN if <inttypes.h> exists and defines the PRI*\n# macros to non-string values.  This is the case on AIX 4.3.3.\n\nAC_DEFUN([gt_INTTYPES_PRI],\n[\n  AC_CHECK_HEADERS([inttypes.h])\n  if test $ac_cv_header_inttypes_h = yes; then\n    AC_CACHE_CHECK([whether the inttypes.h PRIxNN macros are broken],\n      [gt_cv_inttypes_pri_broken],\n      [\n        AC_TRY_COMPILE([#include <inttypes.h>\n#ifdef PRId32\nchar *p = PRId32;\n#endif\n], [], [gt_cv_inttypes_pri_broken=no], [gt_cv_inttypes_pri_broken=yes])\n      ])\n  fi\n  if test \"$gt_cv_inttypes_pri_broken\" = yes; then\n    AC_DEFINE_UNQUOTED([PRI_MACROS_BROKEN], [1],\n      [Define if <inttypes.h> exists and defines unusable PRI* macros.])\n    PRI_MACROS_BROKEN=1\n  else\n    PRI_MACROS_BROKEN=0\n  fi\n  AC_SUBST([PRI_MACROS_BROKEN])\n])\n"
  },
  {
    "path": "tools/missing-macros/src/m4/inttypes_h.m4",
    "content": "# inttypes_h.m4 serial 9\ndnl Copyright (C) 1997-2004, 2006, 2008-2010 Free Software Foundation, Inc.\ndnl This file is free software; the Free Software Foundation\ndnl gives unlimited permission to copy and/or distribute it,\ndnl with or without modifications, as long as this notice is preserved.\n\ndnl From Paul Eggert.\n\n# Define HAVE_INTTYPES_H_WITH_UINTMAX if <inttypes.h> exists,\n# doesn't clash with <sys/types.h>, and declares uintmax_t.\n\nAC_DEFUN([gl_AC_HEADER_INTTYPES_H],\n[\n  AC_CACHE_CHECK([for inttypes.h], [gl_cv_header_inttypes_h],\n  [AC_TRY_COMPILE(\n    [#include <sys/types.h>\n#include <inttypes.h>],\n    [uintmax_t i = (uintmax_t) -1; return !i;],\n    [gl_cv_header_inttypes_h=yes],\n    [gl_cv_header_inttypes_h=no])])\n  if test $gl_cv_header_inttypes_h = yes; then\n    AC_DEFINE_UNQUOTED([HAVE_INTTYPES_H_WITH_UINTMAX], [1],\n      [Define if <inttypes.h> exists, doesn't clash with <sys/types.h>,\n       and declares uintmax_t. ])\n  fi\n])\n"
  },
  {
    "path": "tools/missing-macros/src/m4/lib-ld.m4",
    "content": "# lib-ld.m4 serial 4 (gettext-0.18)\ndnl Copyright (C) 1996-2003, 2009-2010 Free Software Foundation, Inc.\ndnl This file is free software; the Free Software Foundation\ndnl gives unlimited permission to copy and/or distribute it,\ndnl with or without modifications, as long as this notice is preserved.\n\ndnl Subroutines of libtool.m4,\ndnl with replacements s/AC_/AC_LIB/ and s/lt_cv/acl_cv/ to avoid collision\ndnl with libtool.m4.\n\ndnl From libtool-1.4. Sets the variable with_gnu_ld to yes or no.\nAC_DEFUN([AC_LIB_PROG_LD_GNU],\n[AC_CACHE_CHECK([if the linker ($LD) is GNU ld], [acl_cv_prog_gnu_ld],\n[# I'd rather use --version here, but apparently some GNU ld's only accept -v.\ncase `$LD -v 2>&1 </dev/null` in\n*GNU* | *'with BFD'*)\n  acl_cv_prog_gnu_ld=yes ;;\n*)\n  acl_cv_prog_gnu_ld=no ;;\nesac])\nwith_gnu_ld=$acl_cv_prog_gnu_ld\n])\n\ndnl From libtool-1.4. Sets the variable LD.\nAC_DEFUN([AC_LIB_PROG_LD],\n[AC_ARG_WITH([gnu-ld],\n[  --with-gnu-ld           assume the C compiler uses GNU ld [default=no]],\ntest \"$withval\" = no || with_gnu_ld=yes, with_gnu_ld=no)\nAC_REQUIRE([AC_PROG_CC])dnl\nAC_REQUIRE([AC_CANONICAL_HOST])dnl\n# Prepare PATH_SEPARATOR.\n# The user is always right.\nif test \"${PATH_SEPARATOR+set}\" != set; then\n  echo \"#! /bin/sh\" >conf$$.sh\n  echo  \"exit 0\"   >>conf$$.sh\n  chmod +x conf$$.sh\n  if (PATH=\"/nonexistent;.\"; conf$$.sh) >/dev/null 2>&1; then\n    PATH_SEPARATOR=';'\n  else\n    PATH_SEPARATOR=:\n  fi\n  rm -f conf$$.sh\nfi\nac_prog=ld\nif test \"$GCC\" = yes; then\n  # Check if gcc -print-prog-name=ld gives a path.\n  AC_MSG_CHECKING([for ld used by GCC])\n  case $host in\n  *-*-mingw*)\n    # gcc leaves a trailing carriage return which upsets mingw\n    ac_prog=`($CC -print-prog-name=ld) 2>&5 | tr -d '\\015'` ;;\n  *)\n    ac_prog=`($CC -print-prog-name=ld) 2>&5` ;;\n  esac\n  case $ac_prog in\n    # Accept absolute paths.\n    [[\\\\/]* | [A-Za-z]:[\\\\/]*)]\n      [re_direlt='/[^/][^/]*/\\.\\./']\n      # Canonicalize the path of ld\n      ac_prog=`echo $ac_prog| sed 's%\\\\\\\\%/%g'`\n      while echo $ac_prog | grep \"$re_direlt\" > /dev/null 2>&1; do\n        ac_prog=`echo $ac_prog| sed \"s%$re_direlt%/%\"`\n      done\n      test -z \"$LD\" && LD=\"$ac_prog\"\n      ;;\n  \"\")\n    # If it fails, then pretend we aren't using GCC.\n    ac_prog=ld\n    ;;\n  *)\n    # If it is relative, then search for the first ld in PATH.\n    with_gnu_ld=unknown\n    ;;\n  esac\nelif test \"$with_gnu_ld\" = yes; then\n  AC_MSG_CHECKING([for GNU ld])\nelse\n  AC_MSG_CHECKING([for non-GNU ld])\nfi\nAC_CACHE_VAL([acl_cv_path_LD],\n[if test -z \"$LD\"; then\n  IFS=\"${IFS= \t}\"; ac_save_ifs=\"$IFS\"; IFS=\"${IFS}${PATH_SEPARATOR-:}\"\n  for ac_dir in $PATH; do\n    test -z \"$ac_dir\" && ac_dir=.\n    if test -f \"$ac_dir/$ac_prog\" || test -f \"$ac_dir/$ac_prog$ac_exeext\"; then\n      acl_cv_path_LD=\"$ac_dir/$ac_prog\"\n      # Check to see if the program is GNU ld.  I'd rather use --version,\n      # but apparently some GNU ld's only accept -v.\n      # Break only if it was the GNU/non-GNU ld that we prefer.\n      case `\"$acl_cv_path_LD\" -v 2>&1 < /dev/null` in\n      *GNU* | *'with BFD'*)\n        test \"$with_gnu_ld\" != no && break ;;\n      *)\n        test \"$with_gnu_ld\" != yes && break ;;\n      esac\n    fi\n  done\n  IFS=\"$ac_save_ifs\"\nelse\n  acl_cv_path_LD=\"$LD\" # Let the user override the test with a path.\nfi])\nLD=\"$acl_cv_path_LD\"\nif test -n \"$LD\"; then\n  AC_MSG_RESULT([$LD])\nelse\n  AC_MSG_RESULT([no])\nfi\ntest -z \"$LD\" && AC_MSG_ERROR([no acceptable ld found in \\$PATH])\nAC_LIB_PROG_LD_GNU\n])\n"
  },
  {
    "path": "tools/missing-macros/src/m4/lib-link.m4",
    "content": "# lib-link.m4 serial 21 (gettext-0.18)\ndnl Copyright (C) 2001-2010 Free Software Foundation, Inc.\ndnl This file is free software; the Free Software Foundation\ndnl gives unlimited permission to copy and/or distribute it,\ndnl with or without modifications, as long as this notice is preserved.\n\ndnl From Bruno Haible.\n\nAC_PREREQ([2.54])\n\ndnl AC_LIB_LINKFLAGS(name [, dependencies]) searches for libname and\ndnl the libraries corresponding to explicit and implicit dependencies.\ndnl Sets and AC_SUBSTs the LIB${NAME} and LTLIB${NAME} variables and\ndnl augments the CPPFLAGS variable.\ndnl Sets and AC_SUBSTs the LIB${NAME}_PREFIX variable to nonempty if libname\ndnl was found in ${LIB${NAME}_PREFIX}/$acl_libdirstem.\nAC_DEFUN([AC_LIB_LINKFLAGS],\n[\n  AC_REQUIRE([AC_LIB_PREPARE_PREFIX])\n  AC_REQUIRE([AC_LIB_RPATH])\n  pushdef([Name],[translit([$1],[./-], [___])])\n  pushdef([NAME],[translit([$1],[abcdefghijklmnopqrstuvwxyz./-],\n                                [ABCDEFGHIJKLMNOPQRSTUVWXYZ___])])\n  AC_CACHE_CHECK([how to link with lib[]$1], [ac_cv_lib[]Name[]_libs], [\n    AC_LIB_LINKFLAGS_BODY([$1], [$2])\n    ac_cv_lib[]Name[]_libs=\"$LIB[]NAME\"\n    ac_cv_lib[]Name[]_ltlibs=\"$LTLIB[]NAME\"\n    ac_cv_lib[]Name[]_cppflags=\"$INC[]NAME\"\n    ac_cv_lib[]Name[]_prefix=\"$LIB[]NAME[]_PREFIX\"\n  ])\n  LIB[]NAME=\"$ac_cv_lib[]Name[]_libs\"\n  LTLIB[]NAME=\"$ac_cv_lib[]Name[]_ltlibs\"\n  INC[]NAME=\"$ac_cv_lib[]Name[]_cppflags\"\n  LIB[]NAME[]_PREFIX=\"$ac_cv_lib[]Name[]_prefix\"\n  AC_LIB_APPENDTOVAR([CPPFLAGS], [$INC]NAME)\n  AC_SUBST([LIB]NAME)\n  AC_SUBST([LTLIB]NAME)\n  AC_SUBST([LIB]NAME[_PREFIX])\n  dnl Also set HAVE_LIB[]NAME so that AC_LIB_HAVE_LINKFLAGS can reuse the\n  dnl results of this search when this library appears as a dependency.\n  HAVE_LIB[]NAME=yes\n  popdef([NAME])\n  popdef([Name])\n])\n\ndnl AC_LIB_HAVE_LINKFLAGS(name, dependencies, includes, testcode, [missing-message])\ndnl searches for libname and the libraries corresponding to explicit and\ndnl implicit dependencies, together with the specified include files and\ndnl the ability to compile and link the specified testcode. The missing-message\ndnl defaults to 'no' and may contain additional hints for the user.\ndnl If found, it sets and AC_SUBSTs HAVE_LIB${NAME}=yes and the LIB${NAME}\ndnl and LTLIB${NAME} variables and augments the CPPFLAGS variable, and\ndnl #defines HAVE_LIB${NAME} to 1. Otherwise, it sets and AC_SUBSTs\ndnl HAVE_LIB${NAME}=no and LIB${NAME} and LTLIB${NAME} to empty.\ndnl Sets and AC_SUBSTs the LIB${NAME}_PREFIX variable to nonempty if libname\ndnl was found in ${LIB${NAME}_PREFIX}/$acl_libdirstem.\nAC_DEFUN([AC_LIB_HAVE_LINKFLAGS],\n[\n  AC_REQUIRE([AC_LIB_PREPARE_PREFIX])\n  AC_REQUIRE([AC_LIB_RPATH])\n  pushdef([Name],[translit([$1],[./-], [___])])\n  pushdef([NAME],[translit([$1],[abcdefghijklmnopqrstuvwxyz./-],\n                                [ABCDEFGHIJKLMNOPQRSTUVWXYZ___])])\n\n  dnl Search for lib[]Name and define LIB[]NAME, LTLIB[]NAME and INC[]NAME\n  dnl accordingly.\n  AC_LIB_LINKFLAGS_BODY([$1], [$2])\n\n  dnl Add $INC[]NAME to CPPFLAGS before performing the following checks,\n  dnl because if the user has installed lib[]Name and not disabled its use\n  dnl via --without-lib[]Name-prefix, he wants to use it.\n  ac_save_CPPFLAGS=\"$CPPFLAGS\"\n  AC_LIB_APPENDTOVAR([CPPFLAGS], [$INC]NAME)\n\n  AC_CACHE_CHECK([for lib[]$1], [ac_cv_lib[]Name], [\n    ac_save_LIBS=\"$LIBS\"\n    dnl If $LIB[]NAME contains some -l options, add it to the end of LIBS,\n    dnl because these -l options might require -L options that are present in\n    dnl LIBS. -l options benefit only from the -L options listed before it.\n    dnl Otherwise, add it to the front of LIBS, because it may be a static\n    dnl library that depends on another static library that is present in LIBS.\n    dnl Static libraries benefit only from the static libraries listed after\n    dnl it.\n    case \" $LIB[]NAME\" in\n      *\" -l\"*) LIBS=\"$LIBS $LIB[]NAME\" ;;\n      *)       LIBS=\"$LIB[]NAME $LIBS\" ;;\n    esac\n    AC_TRY_LINK([$3], [$4],\n      [ac_cv_lib[]Name=yes],\n      [ac_cv_lib[]Name='m4_if([$5], [], [no], [[$5]])'])\n    LIBS=\"$ac_save_LIBS\"\n  ])\n  if test \"$ac_cv_lib[]Name\" = yes; then\n    HAVE_LIB[]NAME=yes\n    AC_DEFINE([HAVE_LIB]NAME, 1, [Define if you have the lib][$1 library.])\n    AC_MSG_CHECKING([how to link with lib[]$1])\n    AC_MSG_RESULT([$LIB[]NAME])\n  else\n    HAVE_LIB[]NAME=no\n    dnl If $LIB[]NAME didn't lead to a usable library, we don't need\n    dnl $INC[]NAME either.\n    CPPFLAGS=\"$ac_save_CPPFLAGS\"\n    LIB[]NAME=\n    LTLIB[]NAME=\n    LIB[]NAME[]_PREFIX=\n  fi\n  AC_SUBST([HAVE_LIB]NAME)\n  AC_SUBST([LIB]NAME)\n  AC_SUBST([LTLIB]NAME)\n  AC_SUBST([LIB]NAME[_PREFIX])\n  popdef([NAME])\n  popdef([Name])\n])\n\ndnl Determine the platform dependent parameters needed to use rpath:\ndnl   acl_libext,\ndnl   acl_shlibext,\ndnl   acl_hardcode_libdir_flag_spec,\ndnl   acl_hardcode_libdir_separator,\ndnl   acl_hardcode_direct,\ndnl   acl_hardcode_minus_L.\nAC_DEFUN([AC_LIB_RPATH],\n[\n  dnl Tell automake >= 1.10 to complain if config.rpath is missing.\n  m4_ifdef([AC_REQUIRE_AUX_FILE], [AC_REQUIRE_AUX_FILE([config.rpath])])\n  AC_REQUIRE([AC_PROG_CC])                dnl we use $CC, $GCC, $LDFLAGS\n  AC_REQUIRE([AC_LIB_PROG_LD])            dnl we use $LD, $with_gnu_ld\n  AC_REQUIRE([AC_CANONICAL_HOST])         dnl we use $host\n  AC_REQUIRE([AC_CONFIG_AUX_DIR_DEFAULT]) dnl we use $ac_aux_dir\n  AC_CACHE_CHECK([for shared library run path origin], [acl_cv_rpath], [\n    CC=\"$CC\" GCC=\"$GCC\" LDFLAGS=\"$LDFLAGS\" LD=\"$LD\" with_gnu_ld=\"$with_gnu_ld\" \\\n    ${CONFIG_SHELL-/bin/sh} \"$ac_aux_dir/config.rpath\" \"$host\" > conftest.sh\n    . ./conftest.sh\n    rm -f ./conftest.sh\n    acl_cv_rpath=done\n  ])\n  wl=\"$acl_cv_wl\"\n  acl_libext=\"$acl_cv_libext\"\n  acl_shlibext=\"$acl_cv_shlibext\"\n  acl_libname_spec=\"$acl_cv_libname_spec\"\n  acl_library_names_spec=\"$acl_cv_library_names_spec\"\n  acl_hardcode_libdir_flag_spec=\"$acl_cv_hardcode_libdir_flag_spec\"\n  acl_hardcode_libdir_separator=\"$acl_cv_hardcode_libdir_separator\"\n  acl_hardcode_direct=\"$acl_cv_hardcode_direct\"\n  acl_hardcode_minus_L=\"$acl_cv_hardcode_minus_L\"\n  dnl Determine whether the user wants rpath handling at all.\n  AC_ARG_ENABLE([rpath],\n    [  --disable-rpath         do not hardcode runtime library paths],\n    :, enable_rpath=yes)\n])\n\ndnl AC_LIB_FROMPACKAGE(name, package)\ndnl declares that libname comes from the given package. The configure file\ndnl will then not have a --with-libname-prefix option but a\ndnl --with-package-prefix option. Several libraries can come from the same\ndnl package. This declaration must occur before an AC_LIB_LINKFLAGS or similar\ndnl macro call that searches for libname.\nAC_DEFUN([AC_LIB_FROMPACKAGE],\n[\n  pushdef([NAME],[translit([$1],[abcdefghijklmnopqrstuvwxyz./-],\n                                [ABCDEFGHIJKLMNOPQRSTUVWXYZ___])])\n  define([acl_frompackage_]NAME, [$2])\n  popdef([NAME])\n  pushdef([PACK],[$2])\n  pushdef([PACKUP],[translit(PACK,[abcdefghijklmnopqrstuvwxyz./-],\n                                  [ABCDEFGHIJKLMNOPQRSTUVWXYZ___])])\n  define([acl_libsinpackage_]PACKUP,\n    m4_ifdef([acl_libsinpackage_]PACKUP, [acl_libsinpackage_]PACKUP[[, ]],)[lib$1])\n  popdef([PACKUP])\n  popdef([PACK])\n])\n\ndnl AC_LIB_LINKFLAGS_BODY(name [, dependencies]) searches for libname and\ndnl the libraries corresponding to explicit and implicit dependencies.\ndnl Sets the LIB${NAME}, LTLIB${NAME} and INC${NAME} variables.\ndnl Also, sets the LIB${NAME}_PREFIX variable to nonempty if libname was found\ndnl in ${LIB${NAME}_PREFIX}/$acl_libdirstem.\nAC_DEFUN([AC_LIB_LINKFLAGS_BODY],\n[\n  AC_REQUIRE([AC_LIB_PREPARE_MULTILIB])\n  pushdef([NAME],[translit([$1],[abcdefghijklmnopqrstuvwxyz./-],\n                                [ABCDEFGHIJKLMNOPQRSTUVWXYZ___])])\n  pushdef([PACK],[m4_ifdef([acl_frompackage_]NAME, [acl_frompackage_]NAME, lib[$1])])\n  pushdef([PACKUP],[translit(PACK,[abcdefghijklmnopqrstuvwxyz./-],\n                                  [ABCDEFGHIJKLMNOPQRSTUVWXYZ___])])\n  pushdef([PACKLIBS],[m4_ifdef([acl_frompackage_]NAME, [acl_libsinpackage_]PACKUP, lib[$1])])\n  dnl Autoconf >= 2.61 supports dots in --with options.\n  pushdef([P_A_C_K],[m4_if(m4_version_compare(m4_defn([m4_PACKAGE_VERSION]),[2.61]),[-1],[translit(PACK,[.],[_])],PACK)])\n  dnl By default, look in $includedir and $libdir.\n  use_additional=yes\n  AC_LIB_WITH_FINAL_PREFIX([\n    eval additional_includedir=\\\"$includedir\\\"\n    eval additional_libdir=\\\"$libdir\\\"\n  ])\n  AC_ARG_WITH(P_A_C_K[-prefix],\n[[  --with-]]P_A_C_K[[-prefix[=DIR]  search for ]PACKLIBS[ in DIR/include and DIR/lib\n  --without-]]P_A_C_K[[-prefix     don't search for ]PACKLIBS[ in includedir and libdir]],\n[\n    if test \"X$withval\" = \"Xno\"; then\n      use_additional=no\n    else\n      if test \"X$withval\" = \"X\"; then\n        AC_LIB_WITH_FINAL_PREFIX([\n          eval additional_includedir=\\\"$includedir\\\"\n          eval additional_libdir=\\\"$libdir\\\"\n        ])\n      else\n        additional_includedir=\"$withval/include\"\n        additional_libdir=\"$withval/$acl_libdirstem\"\n        if test \"$acl_libdirstem2\" != \"$acl_libdirstem\" \\\n           && ! test -d \"$withval/$acl_libdirstem\"; then\n          additional_libdir=\"$withval/$acl_libdirstem2\"\n        fi\n      fi\n    fi\n])\n  dnl Search the library and its dependencies in $additional_libdir and\n  dnl $LDFLAGS. Using breadth-first-seach.\n  LIB[]NAME=\n  LTLIB[]NAME=\n  INC[]NAME=\n  LIB[]NAME[]_PREFIX=\n  dnl HAVE_LIB${NAME} is an indicator that LIB${NAME}, LTLIB${NAME} have been\n  dnl computed. So it has to be reset here.\n  HAVE_LIB[]NAME=\n  rpathdirs=\n  ltrpathdirs=\n  names_already_handled=\n  names_next_round='$1 $2'\n  while test -n \"$names_next_round\"; do\n    names_this_round=\"$names_next_round\"\n    names_next_round=\n    for name in $names_this_round; do\n      already_handled=\n      for n in $names_already_handled; do\n        if test \"$n\" = \"$name\"; then\n          already_handled=yes\n          break\n        fi\n      done\n      if test -z \"$already_handled\"; then\n        names_already_handled=\"$names_already_handled $name\"\n        dnl See if it was already located by an earlier AC_LIB_LINKFLAGS\n        dnl or AC_LIB_HAVE_LINKFLAGS call.\n        uppername=`echo \"$name\" | sed -e 'y|abcdefghijklmnopqrstuvwxyz./-|ABCDEFGHIJKLMNOPQRSTUVWXYZ___|'`\n        eval value=\\\"\\$HAVE_LIB$uppername\\\"\n        if test -n \"$value\"; then\n          if test \"$value\" = yes; then\n            eval value=\\\"\\$LIB$uppername\\\"\n            test -z \"$value\" || LIB[]NAME=\"${LIB[]NAME}${LIB[]NAME:+ }$value\"\n            eval value=\\\"\\$LTLIB$uppername\\\"\n            test -z \"$value\" || LTLIB[]NAME=\"${LTLIB[]NAME}${LTLIB[]NAME:+ }$value\"\n          else\n            dnl An earlier call to AC_LIB_HAVE_LINKFLAGS has determined\n            dnl that this library doesn't exist. So just drop it.\n            :\n          fi\n        else\n          dnl Search the library lib$name in $additional_libdir and $LDFLAGS\n          dnl and the already constructed $LIBNAME/$LTLIBNAME.\n          found_dir=\n          found_la=\n          found_so=\n          found_a=\n          eval libname=\\\"$acl_libname_spec\\\"    # typically: libname=lib$name\n          if test -n \"$acl_shlibext\"; then\n            shrext=\".$acl_shlibext\"             # typically: shrext=.so\n          else\n            shrext=\n          fi\n          if test $use_additional = yes; then\n            dir=\"$additional_libdir\"\n            dnl The same code as in the loop below:\n            dnl First look for a shared library.\n            if test -n \"$acl_shlibext\"; then\n              if test -f \"$dir/$libname$shrext\"; then\n                found_dir=\"$dir\"\n                found_so=\"$dir/$libname$shrext\"\n              else\n                if test \"$acl_library_names_spec\" = '$libname$shrext$versuffix'; then\n                  ver=`(cd \"$dir\" && \\\n                        for f in \"$libname$shrext\".*; do echo \"$f\"; done \\\n                        | sed -e \"s,^$libname$shrext\\\\\\\\.,,\" \\\n                        | sort -t '.' -n -r -k1,1 -k2,2 -k3,3 -k4,4 -k5,5 \\\n                        | sed 1q ) 2>/dev/null`\n                  if test -n \"$ver\" && test -f \"$dir/$libname$shrext.$ver\"; then\n                    found_dir=\"$dir\"\n                    found_so=\"$dir/$libname$shrext.$ver\"\n                  fi\n                else\n                  eval library_names=\\\"$acl_library_names_spec\\\"\n                  for f in $library_names; do\n                    if test -f \"$dir/$f\"; then\n                      found_dir=\"$dir\"\n                      found_so=\"$dir/$f\"\n                      break\n                    fi\n                  done\n                fi\n              fi\n            fi\n            dnl Then look for a static library.\n            if test \"X$found_dir\" = \"X\"; then\n              if test -f \"$dir/$libname.$acl_libext\"; then\n                found_dir=\"$dir\"\n                found_a=\"$dir/$libname.$acl_libext\"\n              fi\n            fi\n            if test \"X$found_dir\" != \"X\"; then\n              if test -f \"$dir/$libname.la\"; then\n                found_la=\"$dir/$libname.la\"\n              fi\n            fi\n          fi\n          if test \"X$found_dir\" = \"X\"; then\n            for x in $LDFLAGS $LTLIB[]NAME; do\n              AC_LIB_WITH_FINAL_PREFIX([eval x=\\\"$x\\\"])\n              case \"$x\" in\n                -L*)\n                  dir=`echo \"X$x\" | sed -e 's/^X-L//'`\n                  dnl First look for a shared library.\n                  if test -n \"$acl_shlibext\"; then\n                    if test -f \"$dir/$libname$shrext\"; then\n                      found_dir=\"$dir\"\n                      found_so=\"$dir/$libname$shrext\"\n                    else\n                      if test \"$acl_library_names_spec\" = '$libname$shrext$versuffix'; then\n                        ver=`(cd \"$dir\" && \\\n                              for f in \"$libname$shrext\".*; do echo \"$f\"; done \\\n                              | sed -e \"s,^$libname$shrext\\\\\\\\.,,\" \\\n                              | sort -t '.' -n -r -k1,1 -k2,2 -k3,3 -k4,4 -k5,5 \\\n                              | sed 1q ) 2>/dev/null`\n                        if test -n \"$ver\" && test -f \"$dir/$libname$shrext.$ver\"; then\n                          found_dir=\"$dir\"\n                          found_so=\"$dir/$libname$shrext.$ver\"\n                        fi\n                      else\n                        eval library_names=\\\"$acl_library_names_spec\\\"\n                        for f in $library_names; do\n                          if test -f \"$dir/$f\"; then\n                            found_dir=\"$dir\"\n                            found_so=\"$dir/$f\"\n                            break\n                          fi\n                        done\n                      fi\n                    fi\n                  fi\n                  dnl Then look for a static library.\n                  if test \"X$found_dir\" = \"X\"; then\n                    if test -f \"$dir/$libname.$acl_libext\"; then\n                      found_dir=\"$dir\"\n                      found_a=\"$dir/$libname.$acl_libext\"\n                    fi\n                  fi\n                  if test \"X$found_dir\" != \"X\"; then\n                    if test -f \"$dir/$libname.la\"; then\n                      found_la=\"$dir/$libname.la\"\n                    fi\n                  fi\n                  ;;\n              esac\n              if test \"X$found_dir\" != \"X\"; then\n                break\n              fi\n            done\n          fi\n          if test \"X$found_dir\" != \"X\"; then\n            dnl Found the library.\n            LTLIB[]NAME=\"${LTLIB[]NAME}${LTLIB[]NAME:+ }-L$found_dir -l$name\"\n            if test \"X$found_so\" != \"X\"; then\n              dnl Linking with a shared library. We attempt to hardcode its\n              dnl directory into the executable's runpath, unless it's the\n              dnl standard /usr/lib.\n              if test \"$enable_rpath\" = no \\\n                 || test \"X$found_dir\" = \"X/usr/$acl_libdirstem\" \\\n                 || test \"X$found_dir\" = \"X/usr/$acl_libdirstem2\"; then\n                dnl No hardcoding is needed.\n                LIB[]NAME=\"${LIB[]NAME}${LIB[]NAME:+ }$found_so\"\n              else\n                dnl Use an explicit option to hardcode DIR into the resulting\n                dnl binary.\n                dnl Potentially add DIR to ltrpathdirs.\n                dnl The ltrpathdirs will be appended to $LTLIBNAME at the end.\n                haveit=\n                for x in $ltrpathdirs; do\n                  if test \"X$x\" = \"X$found_dir\"; then\n                    haveit=yes\n                    break\n                  fi\n                done\n                if test -z \"$haveit\"; then\n                  ltrpathdirs=\"$ltrpathdirs $found_dir\"\n                fi\n                dnl The hardcoding into $LIBNAME is system dependent.\n                if test \"$acl_hardcode_direct\" = yes; then\n                  dnl Using DIR/libNAME.so during linking hardcodes DIR into the\n                  dnl resulting binary.\n                  LIB[]NAME=\"${LIB[]NAME}${LIB[]NAME:+ }$found_so\"\n                else\n                  if test -n \"$acl_hardcode_libdir_flag_spec\" && test \"$acl_hardcode_minus_L\" = no; then\n                    dnl Use an explicit option to hardcode DIR into the resulting\n                    dnl binary.\n                    LIB[]NAME=\"${LIB[]NAME}${LIB[]NAME:+ }$found_so\"\n                    dnl Potentially add DIR to rpathdirs.\n                    dnl The rpathdirs will be appended to $LIBNAME at the end.\n                    haveit=\n                    for x in $rpathdirs; do\n                      if test \"X$x\" = \"X$found_dir\"; then\n                        haveit=yes\n                        break\n                      fi\n                    done\n                    if test -z \"$haveit\"; then\n                      rpathdirs=\"$rpathdirs $found_dir\"\n                    fi\n                  else\n                    dnl Rely on \"-L$found_dir\".\n                    dnl But don't add it if it's already contained in the LDFLAGS\n                    dnl or the already constructed $LIBNAME\n                    haveit=\n                    for x in $LDFLAGS $LIB[]NAME; do\n                      AC_LIB_WITH_FINAL_PREFIX([eval x=\\\"$x\\\"])\n                      if test \"X$x\" = \"X-L$found_dir\"; then\n                        haveit=yes\n                        break\n                      fi\n                    done\n                    if test -z \"$haveit\"; then\n                      LIB[]NAME=\"${LIB[]NAME}${LIB[]NAME:+ }-L$found_dir\"\n                    fi\n                    if test \"$acl_hardcode_minus_L\" != no; then\n                      dnl FIXME: Not sure whether we should use\n                      dnl \"-L$found_dir -l$name\" or \"-L$found_dir $found_so\"\n                      dnl here.\n                      LIB[]NAME=\"${LIB[]NAME}${LIB[]NAME:+ }$found_so\"\n                    else\n                      dnl We cannot use $acl_hardcode_runpath_var and LD_RUN_PATH\n                      dnl here, because this doesn't fit in flags passed to the\n                      dnl compiler. So give up. No hardcoding. This affects only\n                      dnl very old systems.\n                      dnl FIXME: Not sure whether we should use\n                      dnl \"-L$found_dir -l$name\" or \"-L$found_dir $found_so\"\n                      dnl here.\n                      LIB[]NAME=\"${LIB[]NAME}${LIB[]NAME:+ }-l$name\"\n                    fi\n                  fi\n                fi\n              fi\n            else\n              if test \"X$found_a\" != \"X\"; then\n                dnl Linking with a static library.\n                LIB[]NAME=\"${LIB[]NAME}${LIB[]NAME:+ }$found_a\"\n              else\n                dnl We shouldn't come here, but anyway it's good to have a\n                dnl fallback.\n                LIB[]NAME=\"${LIB[]NAME}${LIB[]NAME:+ }-L$found_dir -l$name\"\n              fi\n            fi\n            dnl Assume the include files are nearby.\n            additional_includedir=\n            case \"$found_dir\" in\n              */$acl_libdirstem | */$acl_libdirstem/)\n                basedir=`echo \"X$found_dir\" | sed -e 's,^X,,' -e \"s,/$acl_libdirstem/\"'*$,,'`\n                if test \"$name\" = '$1'; then\n                  LIB[]NAME[]_PREFIX=\"$basedir\"\n                fi\n                additional_includedir=\"$basedir/include\"\n                ;;\n              */$acl_libdirstem2 | */$acl_libdirstem2/)\n                basedir=`echo \"X$found_dir\" | sed -e 's,^X,,' -e \"s,/$acl_libdirstem2/\"'*$,,'`\n                if test \"$name\" = '$1'; then\n                  LIB[]NAME[]_PREFIX=\"$basedir\"\n                fi\n                additional_includedir=\"$basedir/include\"\n                ;;\n            esac\n            if test \"X$additional_includedir\" != \"X\"; then\n              dnl Potentially add $additional_includedir to $INCNAME.\n              dnl But don't add it\n              dnl   1. if it's the standard /usr/include,\n              dnl   2. if it's /usr/local/include and we are using GCC on Linux,\n              dnl   3. if it's already present in $CPPFLAGS or the already\n              dnl      constructed $INCNAME,\n              dnl   4. if it doesn't exist as a directory.\n              if test \"X$additional_includedir\" != \"X/usr/include\"; then\n                haveit=\n                if test \"X$additional_includedir\" = \"X/usr/local/include\"; then\n                  if test -n \"$GCC\"; then\n                    case $host_os in\n                      linux* | gnu* | k*bsd*-gnu) haveit=yes;;\n                    esac\n                  fi\n                fi\n                if test -z \"$haveit\"; then\n                  for x in $CPPFLAGS $INC[]NAME; do\n                    AC_LIB_WITH_FINAL_PREFIX([eval x=\\\"$x\\\"])\n                    if test \"X$x\" = \"X-I$additional_includedir\"; then\n                      haveit=yes\n                      break\n                    fi\n                  done\n                  if test -z \"$haveit\"; then\n                    if test -d \"$additional_includedir\"; then\n                      dnl Really add $additional_includedir to $INCNAME.\n                      INC[]NAME=\"${INC[]NAME}${INC[]NAME:+ }-I$additional_includedir\"\n                    fi\n                  fi\n                fi\n              fi\n            fi\n            dnl Look for dependencies.\n            if test -n \"$found_la\"; then\n              dnl Read the .la file. It defines the variables\n              dnl dlname, library_names, old_library, dependency_libs, current,\n              dnl age, revision, installed, dlopen, dlpreopen, libdir.\n              save_libdir=\"$libdir\"\n              case \"$found_la\" in\n                */* | *\\\\*) . \"$found_la\" ;;\n                *) . \"./$found_la\" ;;\n              esac\n              libdir=\"$save_libdir\"\n              dnl We use only dependency_libs.\n              for dep in $dependency_libs; do\n                case \"$dep\" in\n                  -L*)\n                    additional_libdir=`echo \"X$dep\" | sed -e 's/^X-L//'`\n                    dnl Potentially add $additional_libdir to $LIBNAME and $LTLIBNAME.\n                    dnl But don't add it\n                    dnl   1. if it's the standard /usr/lib,\n                    dnl   2. if it's /usr/local/lib and we are using GCC on Linux,\n                    dnl   3. if it's already present in $LDFLAGS or the already\n                    dnl      constructed $LIBNAME,\n                    dnl   4. if it doesn't exist as a directory.\n                    if test \"X$additional_libdir\" != \"X/usr/$acl_libdirstem\" \\\n                       && test \"X$additional_libdir\" != \"X/usr/$acl_libdirstem2\"; then\n                      haveit=\n                      if test \"X$additional_libdir\" = \"X/usr/local/$acl_libdirstem\" \\\n                         || test \"X$additional_libdir\" = \"X/usr/local/$acl_libdirstem2\"; then\n                        if test -n \"$GCC\"; then\n                          case $host_os in\n                            linux* | gnu* | k*bsd*-gnu) haveit=yes;;\n                          esac\n                        fi\n                      fi\n                      if test -z \"$haveit\"; then\n                        haveit=\n                        for x in $LDFLAGS $LIB[]NAME; do\n                          AC_LIB_WITH_FINAL_PREFIX([eval x=\\\"$x\\\"])\n                          if test \"X$x\" = \"X-L$additional_libdir\"; then\n                            haveit=yes\n                            break\n                          fi\n                        done\n                        if test -z \"$haveit\"; then\n                          if test -d \"$additional_libdir\"; then\n                            dnl Really add $additional_libdir to $LIBNAME.\n                            LIB[]NAME=\"${LIB[]NAME}${LIB[]NAME:+ }-L$additional_libdir\"\n                          fi\n                        fi\n                        haveit=\n                        for x in $LDFLAGS $LTLIB[]NAME; do\n                          AC_LIB_WITH_FINAL_PREFIX([eval x=\\\"$x\\\"])\n                          if test \"X$x\" = \"X-L$additional_libdir\"; then\n                            haveit=yes\n                            break\n                          fi\n                        done\n                        if test -z \"$haveit\"; then\n                          if test -d \"$additional_libdir\"; then\n                            dnl Really add $additional_libdir to $LTLIBNAME.\n                            LTLIB[]NAME=\"${LTLIB[]NAME}${LTLIB[]NAME:+ }-L$additional_libdir\"\n                          fi\n                        fi\n                      fi\n                    fi\n                    ;;\n                  -R*)\n                    dir=`echo \"X$dep\" | sed -e 's/^X-R//'`\n                    if test \"$enable_rpath\" != no; then\n                      dnl Potentially add DIR to rpathdirs.\n                      dnl The rpathdirs will be appended to $LIBNAME at the end.\n                      haveit=\n                      for x in $rpathdirs; do\n                        if test \"X$x\" = \"X$dir\"; then\n                          haveit=yes\n                          break\n                        fi\n                      done\n                      if test -z \"$haveit\"; then\n                        rpathdirs=\"$rpathdirs $dir\"\n                      fi\n                      dnl Potentially add DIR to ltrpathdirs.\n                      dnl The ltrpathdirs will be appended to $LTLIBNAME at the end.\n                      haveit=\n                      for x in $ltrpathdirs; do\n                        if test \"X$x\" = \"X$dir\"; then\n                          haveit=yes\n                          break\n                        fi\n                      done\n                      if test -z \"$haveit\"; then\n                        ltrpathdirs=\"$ltrpathdirs $dir\"\n                      fi\n                    fi\n                    ;;\n                  -l*)\n                    dnl Handle this in the next round.\n                    names_next_round=\"$names_next_round \"`echo \"X$dep\" | sed -e 's/^X-l//'`\n                    ;;\n                  *.la)\n                    dnl Handle this in the next round. Throw away the .la's\n                    dnl directory; it is already contained in a preceding -L\n                    dnl option.\n                    names_next_round=\"$names_next_round \"`echo \"X$dep\" | sed -e 's,^X.*/,,' -e 's,^lib,,' -e 's,\\.la$,,'`\n                    ;;\n                  *)\n                    dnl Most likely an immediate library name.\n                    LIB[]NAME=\"${LIB[]NAME}${LIB[]NAME:+ }$dep\"\n                    LTLIB[]NAME=\"${LTLIB[]NAME}${LTLIB[]NAME:+ }$dep\"\n                    ;;\n                esac\n              done\n            fi\n          else\n            dnl Didn't find the library; assume it is in the system directories\n            dnl known to the linker and runtime loader. (All the system\n            dnl directories known to the linker should also be known to the\n            dnl runtime loader, otherwise the system is severely misconfigured.)\n            LIB[]NAME=\"${LIB[]NAME}${LIB[]NAME:+ }-l$name\"\n            LTLIB[]NAME=\"${LTLIB[]NAME}${LTLIB[]NAME:+ }-l$name\"\n          fi\n        fi\n      fi\n    done\n  done\n  if test \"X$rpathdirs\" != \"X\"; then\n    if test -n \"$acl_hardcode_libdir_separator\"; then\n      dnl Weird platform: only the last -rpath option counts, the user must\n      dnl pass all path elements in one option. We can arrange that for a\n      dnl single library, but not when more than one $LIBNAMEs are used.\n      alldirs=\n      for found_dir in $rpathdirs; do\n        alldirs=\"${alldirs}${alldirs:+$acl_hardcode_libdir_separator}$found_dir\"\n      done\n      dnl Note: acl_hardcode_libdir_flag_spec uses $libdir and $wl.\n      acl_save_libdir=\"$libdir\"\n      libdir=\"$alldirs\"\n      eval flag=\\\"$acl_hardcode_libdir_flag_spec\\\"\n      libdir=\"$acl_save_libdir\"\n      LIB[]NAME=\"${LIB[]NAME}${LIB[]NAME:+ }$flag\"\n    else\n      dnl The -rpath options are cumulative.\n      for found_dir in $rpathdirs; do\n        acl_save_libdir=\"$libdir\"\n        libdir=\"$found_dir\"\n        eval flag=\\\"$acl_hardcode_libdir_flag_spec\\\"\n        libdir=\"$acl_save_libdir\"\n        LIB[]NAME=\"${LIB[]NAME}${LIB[]NAME:+ }$flag\"\n      done\n    fi\n  fi\n  if test \"X$ltrpathdirs\" != \"X\"; then\n    dnl When using libtool, the option that works for both libraries and\n    dnl executables is -R. The -R options are cumulative.\n    for found_dir in $ltrpathdirs; do\n      LTLIB[]NAME=\"${LTLIB[]NAME}${LTLIB[]NAME:+ }-R$found_dir\"\n    done\n  fi\n  popdef([P_A_C_K])\n  popdef([PACKLIBS])\n  popdef([PACKUP])\n  popdef([PACK])\n  popdef([NAME])\n])\n\ndnl AC_LIB_APPENDTOVAR(VAR, CONTENTS) appends the elements of CONTENTS to VAR,\ndnl unless already present in VAR.\ndnl Works only for CPPFLAGS, not for LIB* variables because that sometimes\ndnl contains two or three consecutive elements that belong together.\nAC_DEFUN([AC_LIB_APPENDTOVAR],\n[\n  for element in [$2]; do\n    haveit=\n    for x in $[$1]; do\n      AC_LIB_WITH_FINAL_PREFIX([eval x=\\\"$x\\\"])\n      if test \"X$x\" = \"X$element\"; then\n        haveit=yes\n        break\n      fi\n    done\n    if test -z \"$haveit\"; then\n      [$1]=\"${[$1]}${[$1]:+ }$element\"\n    fi\n  done\n])\n\ndnl For those cases where a variable contains several -L and -l options\ndnl referring to unknown libraries and directories, this macro determines the\ndnl necessary additional linker options for the runtime path.\ndnl AC_LIB_LINKFLAGS_FROM_LIBS([LDADDVAR], [LIBSVALUE], [USE-LIBTOOL])\ndnl sets LDADDVAR to linker options needed together with LIBSVALUE.\ndnl If USE-LIBTOOL evaluates to non-empty, linking with libtool is assumed,\ndnl otherwise linking without libtool is assumed.\nAC_DEFUN([AC_LIB_LINKFLAGS_FROM_LIBS],\n[\n  AC_REQUIRE([AC_LIB_RPATH])\n  AC_REQUIRE([AC_LIB_PREPARE_MULTILIB])\n  $1=\n  if test \"$enable_rpath\" != no; then\n    if test -n \"$acl_hardcode_libdir_flag_spec\" && test \"$acl_hardcode_minus_L\" = no; then\n      dnl Use an explicit option to hardcode directories into the resulting\n      dnl binary.\n      rpathdirs=\n      next=\n      for opt in $2; do\n        if test -n \"$next\"; then\n          dir=\"$next\"\n          dnl No need to hardcode the standard /usr/lib.\n          if test \"X$dir\" != \"X/usr/$acl_libdirstem\" \\\n             && test \"X$dir\" != \"X/usr/$acl_libdirstem2\"; then\n            rpathdirs=\"$rpathdirs $dir\"\n          fi\n          next=\n        else\n          case $opt in\n            -L) next=yes ;;\n            -L*) dir=`echo \"X$opt\" | sed -e 's,^X-L,,'`\n                 dnl No need to hardcode the standard /usr/lib.\n                 if test \"X$dir\" != \"X/usr/$acl_libdirstem\" \\\n                    && test \"X$dir\" != \"X/usr/$acl_libdirstem2\"; then\n                   rpathdirs=\"$rpathdirs $dir\"\n                 fi\n                 next= ;;\n            *) next= ;;\n          esac\n        fi\n      done\n      if test \"X$rpathdirs\" != \"X\"; then\n        if test -n \"\"$3\"\"; then\n          dnl libtool is used for linking. Use -R options.\n          for dir in $rpathdirs; do\n            $1=\"${$1}${$1:+ }-R$dir\"\n          done\n        else\n          dnl The linker is used for linking directly.\n          if test -n \"$acl_hardcode_libdir_separator\"; then\n            dnl Weird platform: only the last -rpath option counts, the user\n            dnl must pass all path elements in one option.\n            alldirs=\n            for dir in $rpathdirs; do\n              alldirs=\"${alldirs}${alldirs:+$acl_hardcode_libdir_separator}$dir\"\n            done\n            acl_save_libdir=\"$libdir\"\n            libdir=\"$alldirs\"\n            eval flag=\\\"$acl_hardcode_libdir_flag_spec\\\"\n            libdir=\"$acl_save_libdir\"\n            $1=\"$flag\"\n          else\n            dnl The -rpath options are cumulative.\n            for dir in $rpathdirs; do\n              acl_save_libdir=\"$libdir\"\n              libdir=\"$dir\"\n              eval flag=\\\"$acl_hardcode_libdir_flag_spec\\\"\n              libdir=\"$acl_save_libdir\"\n              $1=\"${$1}${$1:+ }$flag\"\n            done\n          fi\n        fi\n      fi\n    fi\n  fi\n  AC_SUBST([$1])\n])\n"
  },
  {
    "path": "tools/missing-macros/src/m4/lib-prefix.m4",
    "content": "# lib-prefix.m4 serial 7 (gettext-0.18)\ndnl Copyright (C) 2001-2005, 2008-2010 Free Software Foundation, Inc.\ndnl This file is free software; the Free Software Foundation\ndnl gives unlimited permission to copy and/or distribute it,\ndnl with or without modifications, as long as this notice is preserved.\n\ndnl From Bruno Haible.\n\ndnl AC_LIB_ARG_WITH is synonymous to AC_ARG_WITH in autoconf-2.13, and\ndnl similar to AC_ARG_WITH in autoconf 2.52...2.57 except that is doesn't\ndnl require excessive bracketing.\nifdef([AC_HELP_STRING],\n[AC_DEFUN([AC_LIB_ARG_WITH], [AC_ARG_WITH([$1],[[$2]],[$3],[$4])])],\n[AC_DEFUN([AC_][LIB_ARG_WITH], [AC_ARG_WITH([$1],[$2],[$3],[$4])])])\n\ndnl AC_LIB_PREFIX adds to the CPPFLAGS and LDFLAGS the flags that are needed\ndnl to access previously installed libraries. The basic assumption is that\ndnl a user will want packages to use other packages he previously installed\ndnl with the same --prefix option.\ndnl This macro is not needed if only AC_LIB_LINKFLAGS is used to locate\ndnl libraries, but is otherwise very convenient.\nAC_DEFUN([AC_LIB_PREFIX],\n[\n  AC_BEFORE([$0], [AC_LIB_LINKFLAGS])\n  AC_REQUIRE([AC_PROG_CC])\n  AC_REQUIRE([AC_CANONICAL_HOST])\n  AC_REQUIRE([AC_LIB_PREPARE_MULTILIB])\n  AC_REQUIRE([AC_LIB_PREPARE_PREFIX])\n  dnl By default, look in $includedir and $libdir.\n  use_additional=yes\n  AC_LIB_WITH_FINAL_PREFIX([\n    eval additional_includedir=\\\"$includedir\\\"\n    eval additional_libdir=\\\"$libdir\\\"\n  ])\n  AC_LIB_ARG_WITH([lib-prefix],\n[  --with-lib-prefix[=DIR] search for libraries in DIR/include and DIR/lib\n  --without-lib-prefix    don't search for libraries in includedir and libdir],\n[\n    if test \"X$withval\" = \"Xno\"; then\n      use_additional=no\n    else\n      if test \"X$withval\" = \"X\"; then\n        AC_LIB_WITH_FINAL_PREFIX([\n          eval additional_includedir=\\\"$includedir\\\"\n          eval additional_libdir=\\\"$libdir\\\"\n        ])\n      else\n        additional_includedir=\"$withval/include\"\n        additional_libdir=\"$withval/$acl_libdirstem\"\n      fi\n    fi\n])\n  if test $use_additional = yes; then\n    dnl Potentially add $additional_includedir to $CPPFLAGS.\n    dnl But don't add it\n    dnl   1. if it's the standard /usr/include,\n    dnl   2. if it's already present in $CPPFLAGS,\n    dnl   3. if it's /usr/local/include and we are using GCC on Linux,\n    dnl   4. if it doesn't exist as a directory.\n    if test \"X$additional_includedir\" != \"X/usr/include\"; then\n      haveit=\n      for x in $CPPFLAGS; do\n        AC_LIB_WITH_FINAL_PREFIX([eval x=\\\"$x\\\"])\n        if test \"X$x\" = \"X-I$additional_includedir\"; then\n          haveit=yes\n          break\n        fi\n      done\n      if test -z \"$haveit\"; then\n        if test \"X$additional_includedir\" = \"X/usr/local/include\"; then\n          if test -n \"$GCC\"; then\n            case $host_os in\n              linux* | gnu* | k*bsd*-gnu) haveit=yes;;\n            esac\n          fi\n        fi\n        if test -z \"$haveit\"; then\n          if test -d \"$additional_includedir\"; then\n            dnl Really add $additional_includedir to $CPPFLAGS.\n            CPPFLAGS=\"${CPPFLAGS}${CPPFLAGS:+ }-I$additional_includedir\"\n          fi\n        fi\n      fi\n    fi\n    dnl Potentially add $additional_libdir to $LDFLAGS.\n    dnl But don't add it\n    dnl   1. if it's the standard /usr/lib,\n    dnl   2. if it's already present in $LDFLAGS,\n    dnl   3. if it's /usr/local/lib and we are using GCC on Linux,\n    dnl   4. if it doesn't exist as a directory.\n    if test \"X$additional_libdir\" != \"X/usr/$acl_libdirstem\"; then\n      haveit=\n      for x in $LDFLAGS; do\n        AC_LIB_WITH_FINAL_PREFIX([eval x=\\\"$x\\\"])\n        if test \"X$x\" = \"X-L$additional_libdir\"; then\n          haveit=yes\n          break\n        fi\n      done\n      if test -z \"$haveit\"; then\n        if test \"X$additional_libdir\" = \"X/usr/local/$acl_libdirstem\"; then\n          if test -n \"$GCC\"; then\n            case $host_os in\n              linux*) haveit=yes;;\n            esac\n          fi\n        fi\n        if test -z \"$haveit\"; then\n          if test -d \"$additional_libdir\"; then\n            dnl Really add $additional_libdir to $LDFLAGS.\n            LDFLAGS=\"${LDFLAGS}${LDFLAGS:+ }-L$additional_libdir\"\n          fi\n        fi\n      fi\n    fi\n  fi\n])\n\ndnl AC_LIB_PREPARE_PREFIX creates variables acl_final_prefix,\ndnl acl_final_exec_prefix, containing the values to which $prefix and\ndnl $exec_prefix will expand at the end of the configure script.\nAC_DEFUN([AC_LIB_PREPARE_PREFIX],\n[\n  dnl Unfortunately, prefix and exec_prefix get only finally determined\n  dnl at the end of configure.\n  if test \"X$prefix\" = \"XNONE\"; then\n    acl_final_prefix=\"$ac_default_prefix\"\n  else\n    acl_final_prefix=\"$prefix\"\n  fi\n  if test \"X$exec_prefix\" = \"XNONE\"; then\n    acl_final_exec_prefix='${prefix}'\n  else\n    acl_final_exec_prefix=\"$exec_prefix\"\n  fi\n  acl_save_prefix=\"$prefix\"\n  prefix=\"$acl_final_prefix\"\n  eval acl_final_exec_prefix=\\\"$acl_final_exec_prefix\\\"\n  prefix=\"$acl_save_prefix\"\n])\n\ndnl AC_LIB_WITH_FINAL_PREFIX([statement]) evaluates statement, with the\ndnl variables prefix and exec_prefix bound to the values they will have\ndnl at the end of the configure script.\nAC_DEFUN([AC_LIB_WITH_FINAL_PREFIX],\n[\n  acl_save_prefix=\"$prefix\"\n  prefix=\"$acl_final_prefix\"\n  acl_save_exec_prefix=\"$exec_prefix\"\n  exec_prefix=\"$acl_final_exec_prefix\"\n  $1\n  exec_prefix=\"$acl_save_exec_prefix\"\n  prefix=\"$acl_save_prefix\"\n])\n\ndnl AC_LIB_PREPARE_MULTILIB creates\ndnl - a variable acl_libdirstem, containing the basename of the libdir, either\ndnl   \"lib\" or \"lib64\" or \"lib/64\",\ndnl - a variable acl_libdirstem2, as a secondary possible value for\ndnl   acl_libdirstem, either the same as acl_libdirstem or \"lib/sparcv9\" or\ndnl   \"lib/amd64\".\nAC_DEFUN([AC_LIB_PREPARE_MULTILIB],\n[\n  dnl There is no formal standard regarding lib and lib64.\n  dnl On glibc systems, the current practice is that on a system supporting\n  dnl 32-bit and 64-bit instruction sets or ABIs, 64-bit libraries go under\n  dnl $prefix/lib64 and 32-bit libraries go under $prefix/lib. We determine\n  dnl the compiler's default mode by looking at the compiler's library search\n  dnl path. If at least one of its elements ends in /lib64 or points to a\n  dnl directory whose absolute pathname ends in /lib64, we assume a 64-bit ABI.\n  dnl Otherwise we use the default, namely \"lib\".\n  dnl On Solaris systems, the current practice is that on a system supporting\n  dnl 32-bit and 64-bit instruction sets or ABIs, 64-bit libraries go under\n  dnl $prefix/lib/64 (which is a symlink to either $prefix/lib/sparcv9 or\n  dnl $prefix/lib/amd64) and 32-bit libraries go under $prefix/lib.\n  AC_REQUIRE([AC_CANONICAL_HOST])\n  acl_libdirstem=lib\n  acl_libdirstem2=\n  case \"$host_os\" in\n    solaris*)\n      dnl See Solaris 10 Software Developer Collection > Solaris 64-bit Developer's Guide > The Development Environment\n      dnl <http://docs.sun.com/app/docs/doc/816-5138/dev-env?l=en&a=view>.\n      dnl \"Portable Makefiles should refer to any library directories using the 64 symbolic link.\"\n      dnl But we want to recognize the sparcv9 or amd64 subdirectory also if the\n      dnl symlink is missing, so we set acl_libdirstem2 too.\n      AC_CACHE_CHECK([for 64-bit host], [gl_cv_solaris_64bit],\n        [AC_EGREP_CPP([sixtyfour bits], [\n#ifdef _LP64\nsixtyfour bits\n#endif\n           ], [gl_cv_solaris_64bit=yes], [gl_cv_solaris_64bit=no])\n        ])\n      if test $gl_cv_solaris_64bit = yes; then\n        acl_libdirstem=lib/64\n        case \"$host_cpu\" in\n          sparc*)        acl_libdirstem2=lib/sparcv9 ;;\n          i*86 | x86_64) acl_libdirstem2=lib/amd64 ;;\n        esac\n      fi\n      ;;\n    *)\n      searchpath=`(LC_ALL=C $CC -print-search-dirs) 2>/dev/null | sed -n -e 's,^libraries: ,,p' | sed -e 's,^=,,'`\n      if test -n \"$searchpath\"; then\n        acl_save_IFS=\"${IFS= \t}\"; IFS=\":\"\n        for searchdir in $searchpath; do\n          if test -d \"$searchdir\"; then\n            case \"$searchdir\" in\n              */lib64/ | */lib64 ) acl_libdirstem=lib64 ;;\n              */../ | */.. )\n                # Better ignore directories of this form. They are misleading.\n                ;;\n              *) searchdir=`cd \"$searchdir\" && pwd`\n                 case \"$searchdir\" in\n                   */lib64 ) acl_libdirstem=lib64 ;;\n                 esac ;;\n            esac\n          fi\n        done\n        IFS=\"$acl_save_IFS\"\n      fi\n      ;;\n  esac\n  test -n \"$acl_libdirstem2\" || acl_libdirstem2=\"$acl_libdirstem\"\n])\n"
  },
  {
    "path": "tools/missing-macros/src/m4/mfx_acc.m4",
    "content": "# acc.m4 serial 1 (ucl-1.03)\n# /***********************************************************************\n# // standard ACC macros\n# ************************************************************************/\n\nAC_DEFUN([mfx_ACC_CHECK_ENDIAN], [\nAC_C_BIGENDIAN([AC_DEFINE(ACC_ABI_BIG_ENDIAN,1,[Define to 1 if your machine is big endian.])],[AC_DEFINE(ACC_ABI_LITTLE_ENDIAN,1,[Define to 1 if your machine is little endian.])])\n])#\n\nAC_DEFUN([mfx_ACC_CHECK_HEADERS], [\nAC_HEADER_TIME\nAC_CHECK_HEADERS([assert.h ctype.h dirent.h errno.h fcntl.h float.h limits.h malloc.h memory.h setjmp.h signal.h stdarg.h stddef.h stdint.h stdio.h stdlib.h string.h strings.h time.h unistd.h utime.h sys/mman.h sys/resource.h sys/stat.h sys/time.h sys/types.h sys/wait.h])\n])#\n\nAC_DEFUN([mfx_ACC_CHECK_FUNCS], [\nAC_CHECK_FUNCS(access alloca atexit atoi atol chmod chown clock_getcpuclockid clock_getres clock_gettime ctime difftime fstat getenv getpagesize getrusage gettimeofday gmtime isatty localtime longjmp lstat memcmp memcpy memmove memset mkdir mktime mmap mprotect munmap qsort raise rmdir setjmp signal snprintf strcasecmp strchr strdup strerror strftime stricmp strncasecmp strnicmp strrchr strstr time umask utime vsnprintf)\n])#\n\n\nAC_DEFUN([mfx_ACC_CHECK_SIZEOF], [\nAC_CHECK_SIZEOF(short)\nAC_CHECK_SIZEOF(int)\nAC_CHECK_SIZEOF(long)\n\nAC_CHECK_SIZEOF(long long)\nAC_CHECK_SIZEOF(__int16)\nAC_CHECK_SIZEOF(__int32)\nAC_CHECK_SIZEOF(__int64)\n\nAC_CHECK_SIZEOF(void *)\nAC_CHECK_SIZEOF(char *)\nAC_CHECK_SIZEOF(size_t)\nAC_CHECK_SIZEOF(ptrdiff_t)\n])#\n\n\n# /***********************************************************************\n# // Check for ACC_conformance\n# ************************************************************************/\n\nAC_DEFUN([mfx_ACC_ACCCHK], [\nmfx_tmp=$1\nmfx_save_CPPFLAGS=$CPPFLAGS\ndnl in Makefile.in $(INCLUDES) will be before $(CPPFLAGS), so we mimic this here\ntest \"X$mfx_tmp\" = \"X\" || CPPFLAGS=\"$mfx_tmp $CPPFLAGS\"\n\nAC_MSG_CHECKING([whether your compiler passes the ACC conformance test])\n\nAC_LANG_CONFTEST([AC_LANG_PROGRAM(\n[[#define ACC_CONFIG_NO_HEADER 1\n#include \"acc/acc.h\"\n#include \"acc/acc_incd.h\"\n#undef ACCCHK_ASSERT\n#define ACCCHK_ASSERT(expr)     ACC_COMPILE_TIME_ASSERT_HEADER(expr)\n#include \"acc/acc_chk.ch\"\n#undef ACCCHK_ASSERT\nstatic void test_acc_compile_time_assert(void) {\n#define ACCCHK_ASSERT(expr)     ACC_COMPILE_TIME_ASSERT(expr)\n#include \"acc/acc_chk.ch\"\n#undef ACCCHK_ASSERT\n}\n#undef NDEBUG\n#include <assert.h>\nstatic int test_acc_run_time_assert(int r) {\n#define ACCCHK_ASSERT(expr)     assert(expr);\n#include \"acc/acc_chk.ch\"\n#undef ACCCHK_ASSERT\nreturn r;\n}\n]], [[\ntest_acc_compile_time_assert();\nif (test_acc_run_time_assert(1) != 1) return 1;\n]]\n)])\n\nmfx_tmp=FAILED\n_AC_COMPILE_IFELSE([], [mfx_tmp=yes])\nrm -f conftest.$ac_ext conftest.$ac_objext\n\nCPPFLAGS=$mfx_save_CPPFLAGS\n\nAC_MSG_RESULT([$mfx_tmp])\ncase x$mfx_tmp in\n  xpassed | xyes) ;;\n  *)\n    AC_MSG_NOTICE([])\n    AC_MSG_NOTICE([Your compiler failed the ACC conformance test - for details see ])\n    AC_MSG_NOTICE([`config.log'. Please check that log file and consider sending])\n    AC_MSG_NOTICE([a patch or bug-report to <${PACKAGE_BUGREPORT}>.])\n    AC_MSG_NOTICE([Thanks for your support.])\n    AC_MSG_NOTICE([])\n    AC_MSG_ERROR([ACC conformance test failed. Stop.])\ndnl    AS_EXIT\n    ;;\nesac\n])# mfx_ACC_ACCCHK\n\n\n# /***********************************************************************\n# // Check for ACC_conformance\n# ************************************************************************/\n\nAC_DEFUN([mfx_MINIACC_ACCCHK], [\nmfx_tmp=$1\nmfx_save_CPPFLAGS=$CPPFLAGS\ndnl in Makefile.in $(INCLUDES) will be before $(CPPFLAGS), so we mimic this here\ntest \"X$mfx_tmp\" = \"X\" || CPPFLAGS=\"$mfx_tmp $CPPFLAGS\"\n\nAC_MSG_CHECKING([whether your compiler passes the ACC conformance test])\n\nAC_LANG_CONFTEST([AC_LANG_PROGRAM(\n[[#define ACC_CONFIG_NO_HEADER 1\n#define ACC_WANT_ACC_INCD_H 1\n#include $2\n\n#define ACC_WANT_ACC_CHK_CH 1\n#undef ACCCHK_ASSERT\n#define ACCCHK_ASSERT(expr)     ACC_COMPILE_TIME_ASSERT_HEADER(expr)\n#include $2\n\n#define ACC_WANT_ACC_CHK_CH 1\n#undef ACCCHK_ASSERT\n#define ACCCHK_ASSERT(expr)     ACC_COMPILE_TIME_ASSERT(expr)\nstatic void test_acc_compile_time_assert(void) {\n#include $2\n}\n\n#undef NDEBUG\n#include <assert.h>\n#define ACC_WANT_ACC_CHK_CH 1\n#undef ACCCHK_ASSERT\n#define ACCCHK_ASSERT(expr)  assert(expr);\nstatic int test_acc_run_time_assert(int r) {\n#include $2\nreturn r;\n}\n]], [[\ntest_acc_compile_time_assert();\nif (test_acc_run_time_assert(1) != 1) return 1;\n]]\n)])\n\nmfx_tmp=FAILED\n_AC_COMPILE_IFELSE([], [mfx_tmp=yes])\nrm -f conftest.$ac_ext conftest.$ac_objext\n\nCPPFLAGS=$mfx_save_CPPFLAGS\n\nAC_MSG_RESULT([$mfx_tmp])\ncase x$mfx_tmp in\n  xpassed | xyes) ;;\n  *)\n    AC_MSG_NOTICE([])\n    AC_MSG_NOTICE([Your compiler failed the ACC conformance test - for details see ])\n    AC_MSG_NOTICE([`config.log'. Please check that log file and consider sending])\n    AC_MSG_NOTICE([a patch or bug-report to <${PACKAGE_BUGREPORT}>.])\n    AC_MSG_NOTICE([Thanks for your support.])\n    AC_MSG_NOTICE([])\n    AC_MSG_ERROR([ACC conformance test failed. Stop.])\ndnl    AS_EXIT\n    ;;\nesac\n])# mfx_MINIACC_ACCCHK\n"
  },
  {
    "path": "tools/missing-macros/src/m4/mfx_cppflags.m4",
    "content": "# serial 1\n\nAC_DEFUN([mfx_PROG_CPPFLAGS], [\nAC_MSG_CHECKING([whether the C preprocessor needs special flags])\n\nAC_LANG_CONFTEST([AC_LANG_PROGRAM(\n[[#include <limits.h>\n#if (32767 >= 4294967295ul) || (65535u >= 4294967295ul)\n#  include \"your C preprocessor is broken 1\"\n#elif (0xffffu == 0xfffffffful)\n#  include \"your C preprocessor is broken 2\"\n#elif (32767 >= ULONG_MAX) || (65535u >= ULONG_MAX)\n#  include \"your C preprocessor is broken 3\"\n#endif\n]], [[ ]]\n)])\n\nmfx_save_CPPFLAGS=$CPPFLAGS\nmfx_tmp=ERROR\nfor mfx_arg in \"\" -no-cpp-precomp\ndo\n  CPPFLAGS=\"$mfx_arg $mfx_save_CPPFLAGS\"\n  _AC_COMPILE_IFELSE([],\n[mfx_tmp=$mfx_arg\nbreak])\ndone\nCPPFLAGS=$mfx_save_CPPFLAGS\nrm -f conftest.$ac_ext conftest.$ac_objext\ncase x$mfx_tmp in\n  x)\n    AC_MSG_RESULT([none needed]) ;;\n  xERROR)\n    AC_MSG_RESULT([ERROR])\n    AC_MSG_ERROR([your C preprocessor is broken - for details see config.log])\n    ;;\n  *)\n    AC_MSG_RESULT([$mfx_tmp])\n    CPPFLAGS=\"$mfx_tmp $CPPFLAGS\"\n    ;;\nesac\n])# mfx_PROG_CPPFLAGS\n"
  },
  {
    "path": "tools/missing-macros/src/m4/mfx_limits.m4",
    "content": "# serial 3\n\nAC_DEFUN([mfx_CHECK_HEADER_SANE_LIMITS_H], [\nAC_CACHE_CHECK([whether limits.h is sane],\nmfx_cv_header_sane_limits_h,\n[AC_COMPILE_IFELSE([AC_LANG_PROGRAM([[#include <limits.h>\n#if (32767 >= 4294967295ul) || (65535u >= 4294967295ul)\n#  if defined(__APPLE__) && defined(__GNUC__)\n#    error \"your preprocessor is broken - use compiler option -no-cpp-precomp\"\n#  else\n#    include \"your preprocessor is broken\"\n#  endif\n#endif\n#define MFX_0xffff          0xffff\n#define MFX_0xffffffffL     4294967295ul\n#if !defined(CHAR_BIT) || (CHAR_BIT != 8)\n#  include \"error CHAR_BIT\"\n#endif\n#if !defined(UCHAR_MAX)\n#  include \"error UCHAR_MAX 1\"\n#endif\n#if !defined(USHRT_MAX)\n#  include \"error USHRT_MAX 1\"\n#endif\n#if !defined(UINT_MAX)\n#  include \"error UINT_MAX 1\"\n#endif\n#if !defined(ULONG_MAX)\n#  include \"error ULONG_MAX 1\"\n#endif\n#if !defined(SHRT_MAX)\n#  include \"error SHRT_MAX 1\"\n#endif\n#if !defined(INT_MAX)\n#  include \"error INT_MAX 1\"\n#endif\n#if !defined(LONG_MAX)\n#  include \"error LONG_MAX 1\"\n#endif\n#if (UCHAR_MAX < 1)\n#  include \"error UCHAR_MAX 2\"\n#endif\n#if (USHRT_MAX < 1)\n#  include \"error USHRT_MAX 2\"\n#endif\n#if (UINT_MAX < 1)\n#  include \"error UINT_MAX 2\"\n#endif\n#if (ULONG_MAX < 1)\n#  include \"error ULONG_MAX 2\"\n#endif\n#if (UCHAR_MAX < 0xff)\n#  include \"error UCHAR_MAX 3\"\n#endif\n#if (USHRT_MAX < MFX_0xffff)\n#  include \"error USHRT_MAX 3\"\n#endif\n#if (UINT_MAX < MFX_0xffff)\n#  include \"error UINT_MAX 3\"\n#endif\n#if (ULONG_MAX < MFX_0xffffffffL)\n#  include \"error ULONG_MAX 3\"\n#endif\n#if (USHRT_MAX > UINT_MAX)\n#  include \"error USHRT_MAX vs UINT_MAX\"\n#endif\n#if (UINT_MAX > ULONG_MAX)\n#  include \"error UINT_MAX vs ULONG_MAX\"\n#endif\n]], [[\n#if (USHRT_MAX == MFX_0xffff)\n{ typedef char a_short2a[1 - 2 * !(sizeof(short) == 2)]; }\n#elif (USHRT_MAX >= MFX_0xffff)\n{ typedef char a_short2b[1 - 2 * !(sizeof(short) > 2)]; }\n#endif\n#if (UINT_MAX == MFX_0xffff)\n{ typedef char a_int2a[1 - 2 * !(sizeof(int) == 2)]; }\n#elif (UINT_MAX >= MFX_0xffff)\n{ typedef char a_int2b[1 - 2 * !(sizeof(int) > 2)]; }\n#endif\n#if (ULONG_MAX == MFX_0xffff)\n{ typedef char a_long2a[1 - 2 * !(sizeof(long) == 2)]; }\n#elif (ULONG_MAX >= MFX_0xffff)\n{ typedef char a_long2b[1 - 2 * !(sizeof(long) > 2)]; }\n#endif\n#if !defined(_CRAY1) /* CRAY PVP systems */\n#if (USHRT_MAX == MFX_0xffffffffL)\n{ typedef char a_short4a[1 - 2 * !(sizeof(short) == 4)]; }\n#elif (USHRT_MAX >= MFX_0xffffffffL)\n{ typedef char a_short4b[1 - 2 * !(sizeof(short) > 4)]; }\n#endif\n#endif /* _CRAY1 */\n#if (UINT_MAX == MFX_0xffffffffL)\n{ typedef char a_int4a[1 - 2 * !(sizeof(int) == 4)]; }\n#elif (UINT_MAX >= MFX_0xffffffffL)\n{ typedef char a_int4b[1 - 2 * !(sizeof(int) > 4)]; }\n#endif\n#if (ULONG_MAX == MFX_0xffffffffL)\n{ typedef char a_long4a[1 - 2 * !(sizeof(long) == 4)]; }\n#elif (ULONG_MAX >= MFX_0xffffffffL)\n{ typedef char a_long4b[1 - 2 * !(sizeof(long) > 4)]; }\n#endif\n]])],\n[mfx_cv_header_sane_limits_h=yes],\n[mfx_cv_header_sane_limits_h=no])])\n])\n\n# /***********************************************************************\n# // standard\n# ************************************************************************/\n\nAC_DEFUN([mfx_LZO_CHECK_ENDIAN], [\nAC_C_BIGENDIAN([AC_DEFINE(LZO_ABI_BIG_ENDIAN,1,[Define to 1 if your machine is big endian.])],[AC_DEFINE(LZO_ABI_LITTLE_ENDIAN,1,[Define to 1 if your machine is little endian.])])\n])#\n\n\n# /***********************************************************************\n# //\n# ************************************************************************/\n\ndnl more types which are not yet covered by ACC\n\nAC_DEFUN([mfx_CHECK_SIZEOF], [\nAC_CHECK_SIZEOF(__int32)\nAC_CHECK_SIZEOF(intmax_t)\nAC_CHECK_SIZEOF(uintmax_t)\nAC_CHECK_SIZEOF(intptr_t)\nAC_CHECK_SIZEOF(uintptr_t)\n\nAC_CHECK_SIZEOF(float)\nAC_CHECK_SIZEOF(double)\nAC_CHECK_SIZEOF(long double)\n\nAC_CHECK_SIZEOF(dev_t)\nAC_CHECK_SIZEOF(fpos_t)\nAC_CHECK_SIZEOF(mode_t)\nAC_CHECK_SIZEOF(off_t)\nAC_CHECK_SIZEOF(ssize_t)\nAC_CHECK_SIZEOF(time_t)\n])#\n\n\n\nAC_DEFUN([mfx_CHECK_LIB_WINMM], [\nif test \"X$GCC\" = Xyes; then\ncase $host_os in\ncygwin* | mingw* | pw32*)\n     test \"X$LIBS\" != \"X\" && LIBS=\"$LIBS \"\n     LIBS=\"${LIBS}-lwinmm\" ;;\nesac\nfi\n])#\n"
  },
  {
    "path": "tools/missing-macros/src/m4/progtest.m4",
    "content": "# progtest.m4 serial 6 (gettext-0.18)\ndnl Copyright (C) 1996-2003, 2005, 2008-2010 Free Software Foundation, Inc.\ndnl This file is free software; the Free Software Foundation\ndnl gives unlimited permission to copy and/or distribute it,\ndnl with or without modifications, as long as this notice is preserved.\ndnl\ndnl This file can can be used in projects which are not available under\ndnl the GNU General Public License or the GNU Library General Public\ndnl License but which still want to provide support for the GNU gettext\ndnl functionality.\ndnl Please note that the actual code of the GNU gettext library is covered\ndnl by the GNU Library General Public License, and the rest of the GNU\ndnl gettext package package is covered by the GNU General Public License.\ndnl They are *not* in the public domain.\n\ndnl Authors:\ndnl   Ulrich Drepper <drepper@cygnus.com>, 1996.\n\nAC_PREREQ([2.50])\n\n# Search path for a program which passes the given test.\n\ndnl AM_PATH_PROG_WITH_TEST(VARIABLE, PROG-TO-CHECK-FOR,\ndnl   TEST-PERFORMED-ON-FOUND_PROGRAM [, VALUE-IF-NOT-FOUND [, PATH]])\nAC_DEFUN([AM_PATH_PROG_WITH_TEST],\n[\n# Prepare PATH_SEPARATOR.\n# The user is always right.\nif test \"${PATH_SEPARATOR+set}\" != set; then\n  echo \"#! /bin/sh\" >conf$$.sh\n  echo  \"exit 0\"   >>conf$$.sh\n  chmod +x conf$$.sh\n  if (PATH=\"/nonexistent;.\"; conf$$.sh) >/dev/null 2>&1; then\n    PATH_SEPARATOR=';'\n  else\n    PATH_SEPARATOR=:\n  fi\n  rm -f conf$$.sh\nfi\n\n# Find out how to test for executable files. Don't use a zero-byte file,\n# as systems may use methods other than mode bits to determine executability.\ncat >conf$$.file <<_ASEOF\n#! /bin/sh\nexit 0\n_ASEOF\nchmod +x conf$$.file\nif test -x conf$$.file >/dev/null 2>&1; then\n  ac_executable_p=\"test -x\"\nelse\n  ac_executable_p=\"test -f\"\nfi\nrm -f conf$$.file\n\n# Extract the first word of \"$2\", so it can be a program name with args.\nset dummy $2; ac_word=[$]2\nAC_MSG_CHECKING([for $ac_word])\nAC_CACHE_VAL([ac_cv_path_$1],\n[case \"[$]$1\" in\n  [[\\\\/]]* | ?:[[\\\\/]]*)\n    ac_cv_path_$1=\"[$]$1\" # Let the user override the test with a path.\n    ;;\n  *)\n    ac_save_IFS=\"$IFS\"; IFS=$PATH_SEPARATOR\n    for ac_dir in ifelse([$5], , $PATH, [$5]); do\n      IFS=\"$ac_save_IFS\"\n      test -z \"$ac_dir\" && ac_dir=.\n      for ac_exec_ext in '' $ac_executable_extensions; do\n        if $ac_executable_p \"$ac_dir/$ac_word$ac_exec_ext\"; then\n          echo \"$as_me: trying $ac_dir/$ac_word...\" >&AS_MESSAGE_LOG_FD\n          if [$3]; then\n            ac_cv_path_$1=\"$ac_dir/$ac_word$ac_exec_ext\"\n            break 2\n          fi\n        fi\n      done\n    done\n    IFS=\"$ac_save_IFS\"\ndnl If no 4th arg is given, leave the cache variable unset,\ndnl so AC_PATH_PROGS will keep looking.\nifelse([$4], , , [  test -z \"[$]ac_cv_path_$1\" && ac_cv_path_$1=\"$4\"\n])dnl\n    ;;\nesac])dnl\n$1=\"$ac_cv_path_$1\"\nif test ifelse([$4], , [-n \"[$]$1\"], [\"[$]$1\" != \"$4\"]); then\n  AC_MSG_RESULT([$][$1])\nelse\n  AC_MSG_RESULT([no])\nfi\nAC_SUBST([$1])dnl\n])\n"
  },
  {
    "path": "tools/missing-macros/src/m4/stdint_h.m4",
    "content": "# stdint_h.m4 serial 8\ndnl Copyright (C) 1997-2004, 2006, 2008-2010 Free Software Foundation, Inc.\ndnl This file is free software; the Free Software Foundation\ndnl gives unlimited permission to copy and/or distribute it,\ndnl with or without modifications, as long as this notice is preserved.\n\ndnl From Paul Eggert.\n\n# Define HAVE_STDINT_H_WITH_UINTMAX if <stdint.h> exists,\n# doesn't clash with <sys/types.h>, and declares uintmax_t.\n\nAC_DEFUN([gl_AC_HEADER_STDINT_H],\n[\n  AC_CACHE_CHECK([for stdint.h], [gl_cv_header_stdint_h],\n  [AC_TRY_COMPILE(\n    [#include <sys/types.h>\n#include <stdint.h>],\n    [uintmax_t i = (uintmax_t) -1; return !i;],\n    [gl_cv_header_stdint_h=yes],\n    [gl_cv_header_stdint_h=no])])\n  if test $gl_cv_header_stdint_h = yes; then\n    AC_DEFINE_UNQUOTED([HAVE_STDINT_H_WITH_UINTMAX], [1],\n      [Define if <stdint.h> exists, doesn't clash with <sys/types.h>,\n       and declares uintmax_t. ])\n  fi\n])\n"
  },
  {
    "path": "tools/missing-macros/src/m4/uintmax_t.m4",
    "content": "# uintmax_t.m4 serial 12\ndnl Copyright (C) 1997-2004, 2007-2010 Free Software Foundation, Inc.\ndnl This file is free software; the Free Software Foundation\ndnl gives unlimited permission to copy and/or distribute it,\ndnl with or without modifications, as long as this notice is preserved.\n\ndnl From Paul Eggert.\n\nAC_PREREQ([2.13])\n\n# Define uintmax_t to 'unsigned long' or 'unsigned long long'\n# if it is not already defined in <stdint.h> or <inttypes.h>.\n\nAC_DEFUN([gl_AC_TYPE_UINTMAX_T],\n[\n  AC_REQUIRE([gl_AC_HEADER_INTTYPES_H])\n  AC_REQUIRE([gl_AC_HEADER_STDINT_H])\n  if test $gl_cv_header_inttypes_h = no && test $gl_cv_header_stdint_h = no; then\n    AC_REQUIRE([AC_TYPE_UNSIGNED_LONG_LONG_INT])\n    test $ac_cv_type_unsigned_long_long_int = yes \\\n      && ac_type='unsigned long long' \\\n      || ac_type='unsigned long'\n    AC_DEFINE_UNQUOTED([uintmax_t], [$ac_type],\n      [Define to unsigned long or unsigned long long\n       if <stdint.h> and <inttypes.h> don't define.])\n  else\n    AC_DEFINE([HAVE_UINTMAX_T], [1],\n      [Define if you have the 'uintmax_t' type in <stdint.h> or <inttypes.h>.])\n  fi\n])\n"
  },
  {
    "path": "tools/missing-macros/src/m4/va_copy.m4",
    "content": "# va_copy.m4 serial 1 (js-1.6.20070208)\n\ndnl ##\ndnl ##  Check for C99 va_copy() implementation\ndnl ##  (and provide fallback implementation if neccessary)\ndnl ##\ndnl ##  configure.in:\ndnl ##    AC_CHECK_VA_COPY\ndnl ##  foo.c:\ndnl ##    #include \"config.h\"\ndnl ##    [...]\ndnl ##    va_copy(d,s)\ndnl ##\ndnl ##  This check is rather complex: first because we really have to\ndnl ##  try various possible implementations in sequence and second, we\ndnl ##  cannot define a macro in config.h with parameters directly.\ndnl ##\n\ndnl #   test program for va_copy() implementation\nchangequote(<<,>>)\nm4_define(__va_copy_test, <<[\n#include <stdlib.h>\n#include <stdarg.h>\n#include <string.h>\n#define DO_VA_COPY(d, s) $1\nvoid test(char *str, ...)\n{\n    va_list ap, ap2;\n    int i;\n    va_start(ap, str);\n    DO_VA_COPY(ap2, ap);\n    for (i = 1; i <= 9; i++) {\n        int k = (int)va_arg(ap, int);\n        if (k != i)\n            abort();\n    }\n    DO_VA_COPY(ap, ap2);\n    for (i = 1; i <= 9; i++) {\n        int k = (int)va_arg(ap, int);\n        if (k != i)\n            abort();\n    }\n    va_end(ap);\n}\nint main(int argc, char *argv[])\n{\n    test(\"test\", 1, 2, 3, 4, 5, 6, 7, 8, 9);\n    exit(0);\n}\n]>>)\nchangequote([,])\n\ndnl #   test driver for va_copy() implementation\nm4_define(__va_copy_check, [\n    AH_VERBATIM($1,\n[/* Predefined possible va_copy() implementation (id: $1) */\n#define __VA_COPY_USE_$1(d, s) $2])\n    if test \".$ac_cv_va_copy\" = .; then\n        AC_TRY_RUN(__va_copy_test($2), [ac_cv_va_copy=\"$1\"])\n    fi\n])\n\ndnl #   Autoconf check for va_copy() implementation checking\nAC_DEFUN([AC_CHECK_VA_COPY],[\n  dnl #   provide Autoconf display check message\n  AC_MSG_CHECKING(for va_copy() function)\n  dnl #   check for various implementations in priorized sequence   \n  AC_CACHE_VAL(ac_cv_va_copy, [\n    ac_cv_va_copy=\"\"\n    dnl #   1. check for standardized C99 macro\n    __va_copy_check(C99, [va_copy((d), (s))])\n    dnl #   2. check for alternative/deprecated GCC macro\n    __va_copy_check(GCM, [VA_COPY((d), (s))])\n    dnl #   3. check for internal GCC macro (high-level define)\n    __va_copy_check(GCH, [__va_copy((d), (s))])\n    dnl #   4. check for internal GCC macro (built-in function)\n    __va_copy_check(GCB, [__builtin_va_copy((d), (s))])\n    dnl #   5. check for assignment approach (assuming va_list is a struct)\n    __va_copy_check(ASS, [do { (d) = (s); } while (0)])\n    dnl #   6. check for assignment approach (assuming va_list is a pointer)\n    __va_copy_check(ASP, [do { *(d) = *(s); } while (0)])\n    dnl #   7. check for memory copying approach (assuming va_list is a struct)\n    __va_copy_check(CPS, [memcpy((void *)&(d), (void *)&(s)), sizeof((s))])\n    dnl #   8. check for memory copying approach (assuming va_list is a pointer)\n    __va_copy_check(CPP, [memcpy((void *)(d), (void *)(s)), sizeof(*(s))])\n    if test \".$ac_cv_va_copy\" = .; then\n        AC_ERROR([no working implementation found])\n    fi\n  ])\n  dnl #   optionally activate the fallback implementation\n  if test \".$ac_cv_va_copy\" = \".C99\"; then\n      AC_DEFINE(HAVE_VA_COPY, 1, [Define if va_copy() macro exists (and no fallback implementation is required)])\n  fi\n  dnl #   declare which fallback implementation to actually use\n  AC_DEFINE_UNQUOTED([__VA_COPY_USE], [__VA_COPY_USE_$ac_cv_va_copy],\n      [Define to id of used va_copy() implementation])\n  dnl #   provide activation hook for fallback implementation\n  AH_VERBATIM([__VA_COPY_ACTIVATION],\n[/* Optional va_copy() implementation activation */\n#ifndef HAVE_VA_COPY\n#define va_copy(d, s) __VA_COPY_USE(d, s)\n#endif\n])\n  dnl #   provide Autoconf display result message\n  if test \".$ac_cv_va_copy\" = \".C99\"; then\n      AC_MSG_RESULT([yes])\n  else\n      AC_MSG_RESULT([no (using fallback implementation)])\n  fi\n])\n\n"
  },
  {
    "path": "tools/missing-macros/src/m4/wint_t.m4",
    "content": "# wint_t.m4 serial 4 (gettext-0.18)\ndnl Copyright (C) 2003, 2007-2010 Free Software Foundation, Inc.\ndnl This file is free software; the Free Software Foundation\ndnl gives unlimited permission to copy and/or distribute it,\ndnl with or without modifications, as long as this notice is preserved.\n\ndnl From Bruno Haible.\ndnl Test whether <wchar.h> has the 'wint_t' type.\ndnl Prerequisite: AC_PROG_CC\n\nAC_DEFUN([gt_TYPE_WINT_T],\n[\n  AC_CACHE_CHECK([for wint_t], [gt_cv_c_wint_t],\n    [AC_TRY_COMPILE([\n/* Tru64 with Desktop Toolkit C has a bug: <stdio.h> must be included before\n   <wchar.h>.\n   BSD/OS 4.0.1 has a bug: <stddef.h>, <stdio.h> and <time.h> must be included\n   before <wchar.h>.  */\n#include <stddef.h>\n#include <stdio.h>\n#include <time.h>\n#include <wchar.h>\n       wint_t foo = (wchar_t)'\\0';], ,\n       [gt_cv_c_wint_t=yes], [gt_cv_c_wint_t=no])])\n  if test $gt_cv_c_wint_t = yes; then\n    AC_DEFINE([HAVE_WINT_T], [1], [Define if you have the 'wint_t' type.])\n  fi\n])\n"
  },
  {
    "path": "tools/mkimage/Makefile",
    "content": "#\n# Copyright (C) 2006-2014 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=mkimage\nPKG_VERSION:=2022.01\n\nPKG_SOURCE:=u-boot-$(PKG_VERSION).tar.bz2\nPKG_SOURCE_URL:= \\\n\thttps://mirror.cyberbits.eu/u-boot \\\n\thttps://ftp.denx.de/pub/u-boot \\\n\tftp://ftp.denx.de/pub/u-boot\nPKG_HASH:=81b4543227db228c03f8a1bf5ddbc813b0bb8f6555ce46064ef721a6fc680413\n\nHOST_BUILD_DIR:=$(BUILD_DIR_HOST)/u-boot-$(PKG_VERSION)\n\ninclude $(INCLUDE_DIR)/host-build.mk\n\ndefine Host/Compile\n\t$(MAKE) -C $(HOST_BUILD_DIR) \\\n\t\tHOSTCFLAGS=\"$(HOST_CFLAGS)\" \\\n\t\tHOSTLDFLAGS=\"$(HOST_LDFLAGS)\" \\\n\t\tPKG_CONFIG_EXTRAARGS=\"--static\" \\\n\t\tV=$(if $(findstring c,$(OPENWRT_VERBOSE)),1) \\\n\t\ttools-only_config \\\n\t\ttools-only\nendef\n\ndefine Host/Install\n\t$(CP) $(HOST_BUILD_DIR)/tools/mkimage $(STAGING_DIR_HOST)/bin/\n\t$(CP) $(HOST_BUILD_DIR)/tools/mkenvimage $(STAGING_DIR_HOST)/bin/\nendef\n\ndefine Host/Clean\n\trm -f $(STAGING_DIR_HOST)/bin/mkimage\n\trm -f $(STAGING_DIR_HOST)/bin/mkenvimage\nendef\n\n$(eval $(call HostBuild))\n"
  },
  {
    "path": "tools/mkimage/patches/030-allow-to-use-different-magic.patch",
    "content": "This patch makes it possible to set a custom image magic.\n\n--- a/tools/mkimage.c\n+++ b/tools/mkimage.c\n@@ -24,6 +24,7 @@ static struct image_tool_params params =\n \t.arch = IH_ARCH_PPC,\n \t.type = IH_TYPE_KERNEL,\n \t.comp = IH_COMP_GZIP,\n+\t.magic = IH_MAGIC,\n \t.dtc = MKIMAGE_DEFAULT_DTC_OPTIONS,\n \t.imagename = \"\",\n \t.imagename2 = \"\",\n@@ -85,11 +86,12 @@ static void usage(const char *msg)\n \t\t\t \"          -l ==> list image header information\\n\",\n \t\tparams.cmdname);\n \tfprintf(stderr,\n-\t\t\"       %s [-x] -A arch -O os -T type -C comp -a addr -e ep -n name -d data_file[:data_file...] image\\n\"\n+\t\t\"       %s [-x] -A arch -O os -T type -C comp -M magic -a addr -e ep -n name -d data_file[:data_file...] image\\n\"\n \t\t\"          -A ==> set architecture to 'arch'\\n\"\n \t\t\"          -O ==> set operating system to 'os'\\n\"\n \t\t\"          -T ==> set image type to 'type'\\n\"\n \t\t\"          -C ==> set compression type 'comp'\\n\"\n+\t\t\"          -M ==> set image magic to 'magic'\\n\"\n \t\t\"          -a ==> set load address to 'addr' (hex)\\n\"\n \t\t\"          -e ==> set entry point to 'ep' (hex)\\n\"\n \t\t\"          -n ==> set image name to 'name'\\n\"\n@@ -155,7 +157,7 @@ static void process_args(int argc, char\n \tint opt;\n \n \twhile ((opt = getopt(argc, argv,\n-\t\t   \"a:A:b:B:c:C:d:D:e:Ef:FG:k:i:K:ln:N:p:O:rR:qstT:vVx\")) != -1) {\n+\t\t   \"a:A:b:B:c:C:d:D:e:Ef:FG:k:i:K:lM:n:N:p:O:rR:qstT:vVx\")) != -1) {\n \t\tswitch (opt) {\n \t\tcase 'a':\n \t\t\tparams.addr = strtoull(optarg, &ptr, 16);\n@@ -245,6 +247,14 @@ static void process_args(int argc, char\n \t\tcase 'l':\n \t\t\tparams.lflag = 1;\n \t\t\tbreak;\n+\t\tcase 'M':\n+\t\t\tparams.magic = strtoull(optarg, &ptr, 16);\n+\t\t\tif (*ptr) {\n+\t\t\t\tfprintf(stderr,\t\"%s: invalid magic %s\\n\",\n+\t\t\t\t\tparams.cmdname, optarg);\n+\t\t\t\texit(EXIT_FAILURE);\n+\t\t\t}\n+\t\t\tbreak;\n \t\tcase 'n':\n \t\t\tparams.imagename = optarg;\n \t\t\tbreak;\n--- a/tools/default_image.c\n+++ b/tools/default_image.c\n@@ -120,7 +120,7 @@ static void image_set_header(void *ptr,\n \t}\n \n \t/* Build new header */\n-\timage_set_magic(hdr, IH_MAGIC);\n+\timage_set_magic(hdr, params->magic);\n \timage_set_time(hdr, time);\n \timage_set_size(hdr, imagesize);\n \timage_set_load(hdr, addr);\n--- a/tools/imagetool.h\n+++ b/tools/imagetool.h\n@@ -56,6 +56,7 @@ struct image_tool_params {\n \tint arch;\n \tint type;\n \tint comp;\n+\tunsigned int magic;\n \tchar *dtc;\n \tunsigned int addr;\n \tunsigned int ep;\n"
  },
  {
    "path": "tools/mkimage/patches/050-Add-compatibility-with-non-Linux-hosts.patch",
    "content": "From 590b23a46b7ae0f5ec5e8f57a85c0e7578c71141 Mon Sep 17 00:00:00 2001\nFrom: Hauke Mehrtens <hauke@hauke-m.de>\nDate: Sun, 26 Apr 2020 17:15:17 +0200\nSubject: [PATCH 1/2] Add compatibility with non Linux hosts\n\nThis adds some changes to the u-boot tools to make it possible to build\nthem on non Linux hosts like MacOS or FreeBSD.\n\nasm/byteorder.h, asm/posix_types.h, asm/types.h and linux/kernel.h are\nnot available on such systems. Remove the include and add the necessary\nparts for these header files manually or remove the usage too.\n\n__u64 is not available on FreeBSD, remove its usage.\n\nSigned-off-by: Hauke Mehrtens <hauke@hauke-m.de>\n---\n include/image.h             | 2 ++\n include/linux/posix_types.h | 2 ++\n include/linux/types.h       | 4 +++-\n 3 files changed, 7 insertions(+), 1 deletion(-)\n\n--- a/include/image.h\n+++ b/include/image.h\n@@ -16,7 +16,9 @@\n #define __IMAGE_H__\n \n #include \"compiler.h\"\n+#ifdef linux\n #include <asm/byteorder.h>\n+#endif\n #include <stdbool.h>\n \n /* Define this to avoid #ifdefs later on */\n--- a/include/linux/posix_types.h\n+++ b/include/linux/posix_types.h\n@@ -43,6 +43,8 @@ typedef void (*__kernel_sighandler_t)(in\n /* Type of a SYSV IPC key.  */\n typedef int __kernel_key_t;\n \n+#ifdef linux\n #include <asm/posix_types.h>\n+#endif\n \n #endif /* _LINUX_POSIX_TYPES_H */\n--- a/include/linux/types.h\n+++ b/include/linux/types.h\n@@ -2,7 +2,9 @@\n #define _LINUX_TYPES_H\n \n #include <linux/posix_types.h>\n+#ifdef linux\n #include <asm/types.h>\n+#endif\n #include <stdbool.h>\n \n #ifndef __KERNEL_STRICT_NAMES\n@@ -142,7 +144,7 @@ typedef __u16 __bitwise __le16;\n typedef __u16 __bitwise __be16;\n typedef __u32 __bitwise __le32;\n typedef __u32 __bitwise __be32;\n-#if defined(__GNUC__)\n+#if defined(__GNUC__) && defined(linux)\n typedef __u64 __bitwise __le64;\n typedef __u64 __bitwise __be64;\n #endif\n"
  },
  {
    "path": "tools/mkimage/patches/090-macos-arm64-builing-fix.patch",
    "content": "This patch fixes compilation issues on MacOS arm64.\nBased on discussion \nhttps://github.com/u-boot/u-boot/commit/3b142045e8a7f0ab17b6099e9226296af45967d0\n\n--- a/tools/imagetool.h\n+++ b/tools/imagetool.h\n@@ -272,11 +272,14 @@ int rockchip_copy_image(int fd, struct i\n  *  b) we need a API call to get the respective section symbols */\n #if defined(__MACH__)\n #include <mach-o/getsect.h>\n+#include <mach-o/dyld.h>\n \n #define INIT_SECTION(name)  do {\t\t\t\t\t\\\n \t\tunsigned long name ## _len;\t\t\t\t\\\n \t\tchar *__cat(pstart_, name) = getsectdata(\"__DATA\",\t\\\n \t\t\t#name, &__cat(name, _len));\t\t\t\\\n+\t\t\t__cat(pstart_, name) +=\t\t\t\t\\\n+\t\t\t\t_dyld_get_image_vmaddr_slide(0);\t\\\n \t\tchar *__cat(pstop_, name) = __cat(pstart_, name) +\t\\\n \t\t\t__cat(name, _len);\t\t\t\t\\\n \t\t__cat(__start_, name) = (void *)__cat(pstart_, name);\t\\\n"
  },
  {
    "path": "tools/mkimage/patches/095-tools-disable-TOOLS_FIT_FULL_CHECK.patch",
    "content": "From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001\nFrom: Huangbin Zhan <zhanhb88@gmail.com>\nDate: Fri, 18 Feb 2022 14:19:23 +0800\nSubject: [PATCH] tools: disable TOOLS_FIT_FULL_CHECK\n\n\tU-Boot disallows unit addresses by default. Disable TOOLS_FIT_FULL_CHECK\n\tto allow at symbol in node names.\n\nhttps://github.com/openwrt/openwrt/commits/master/scripts/mkits.sh\nhttps://github.com/u-boot/u-boot/commit/3f04db891a353f4b127ed57279279f851c6b4917\n---\n tools/Kconfig | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/tools/Kconfig\n+++ b/tools/Kconfig\n@@ -31,7 +31,7 @@ config TOOLS_FIT\n \t  Enable FIT support in the tools builds.\n \n config TOOLS_FIT_FULL_CHECK\n-\tdef_bool y\n+\tbool \"Do a full check of the FIT\"\n \thelp\n \t  Do a full check of the FIT before using it in the tools builds\n \n"
  },
  {
    "path": "tools/mklibs/Makefile",
    "content": "#\n# Copyright (C) 2009-2013 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=mklibs\nPKG_VERSION:=0.1.45\n\nPKG_SOURCE:=$(PKG_NAME)_$(PKG_VERSION).tar.xz\nPKG_SOURCE_URL:=@DEBIAN/pool/main/m/mklibs/\nPKG_HASH:=dd92a904b3942566f713fe536cd77dd1a5cfc62243c0e0bc6bb5d866e37422f3\n\nHOST_FIXUP:=autoreconf\n\ninclude $(INCLUDE_DIR)/host-build.mk\n\nHOST_CFLAGS += -I$(CURDIR)/include\nHOST_CPPFLAGS += -std=gnu++98\n\ndefine Host/Install\n       $(INSTALL_BIN) \\\n               $(HOST_BUILD_DIR)/src/mklibs \\\n               $(HOST_BUILD_DIR)/src/mklibs-copy \\\n               $(HOST_BUILD_DIR)/src/mklibs-readelf/mklibs-readelf \\\n               $(STAGING_DIR_HOST)/bin/\nendef\n\ndefine Host/Clean\n       rm -f $(STAGING_DIR_HOST)/bin/mklibs*\nendef\n\n$(eval $(call HostBuild))\n"
  },
  {
    "path": "tools/mklibs/include/elf.h",
    "content": "/* This file defines standard ELF types, structures, and macros.\n   Copyright (C) 1995-2003, 2004 Free Software Foundation, Inc.\n   This file is part of the GNU C Library.\n\n   The GNU C Library is free software; you can redistribute it and/or\n   modify it under the terms of the GNU Lesser General Public\n   License as published by the Free Software Foundation; either\n   version 2.1 of the License, or (at your option) any later version.\n\n   The GNU C Library is distributed in the hope that it will be useful,\n   but WITHOUT ANY WARRANTY; without even the implied warranty of\n   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\n   Lesser General Public License for more details.\n\n   You should have received a copy of the GNU Lesser General Public\n   License along with the GNU C Library; if not, write to the Free\n   Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA\n   02111-1307 USA.  */\n\n#ifndef _ELF_H\n#define\t_ELF_H 1\n\n__BEGIN_DECLS\n\n/* Standard ELF types.  */\n\n#include <stdint.h>\n\n/* Type for a 16-bit quantity.  */\ntypedef uint16_t Elf32_Half;\ntypedef uint16_t Elf64_Half;\n\n/* Types for signed and unsigned 32-bit quantities.  */\ntypedef uint32_t Elf32_Word;\ntypedef\tint32_t  Elf32_Sword;\ntypedef uint32_t Elf64_Word;\ntypedef\tint32_t  Elf64_Sword;\n\n/* Types for signed and unsigned 64-bit quantities.  */\ntypedef uint64_t Elf32_Xword;\ntypedef\tint64_t  Elf32_Sxword;\ntypedef uint64_t Elf64_Xword;\ntypedef\tint64_t  Elf64_Sxword;\n\n/* Type of addresses.  */\ntypedef uint32_t Elf32_Addr;\ntypedef uint64_t Elf64_Addr;\n\n/* Type of file offsets.  */\ntypedef uint32_t Elf32_Off;\ntypedef uint64_t Elf64_Off;\n\n/* Type for section indices, which are 16-bit quantities.  */\ntypedef uint16_t Elf32_Section;\ntypedef uint16_t Elf64_Section;\n\n/* Type for version symbol information.  */\ntypedef Elf32_Half Elf32_Versym;\ntypedef Elf64_Half Elf64_Versym;\n\n\n/* The ELF file header.  This appears at the start of every ELF file.  */\n\n#define EI_NIDENT (16)\n\ntypedef struct\n{\n  unsigned char\te_ident[EI_NIDENT];\t/* Magic number and other info */\n  Elf32_Half\te_type;\t\t\t/* Object file type */\n  Elf32_Half\te_machine;\t\t/* Architecture */\n  Elf32_Word\te_version;\t\t/* Object file version */\n  Elf32_Addr\te_entry;\t\t/* Entry point virtual address */\n  Elf32_Off\te_phoff;\t\t/* Program header table file offset */\n  Elf32_Off\te_shoff;\t\t/* Section header table file offset */\n  Elf32_Word\te_flags;\t\t/* Processor-specific flags */\n  Elf32_Half\te_ehsize;\t\t/* ELF header size in bytes */\n  Elf32_Half\te_phentsize;\t\t/* Program header table entry size */\n  Elf32_Half\te_phnum;\t\t/* Program header table entry count */\n  Elf32_Half\te_shentsize;\t\t/* Section header table entry size */\n  Elf32_Half\te_shnum;\t\t/* Section header table entry count */\n  Elf32_Half\te_shstrndx;\t\t/* Section header string table index */\n} Elf32_Ehdr;\n\ntypedef struct\n{\n  unsigned char\te_ident[EI_NIDENT];\t/* Magic number and other info */\n  Elf64_Half\te_type;\t\t\t/* Object file type */\n  Elf64_Half\te_machine;\t\t/* Architecture */\n  Elf64_Word\te_version;\t\t/* Object file version */\n  Elf64_Addr\te_entry;\t\t/* Entry point virtual address */\n  Elf64_Off\te_phoff;\t\t/* Program header table file offset */\n  Elf64_Off\te_shoff;\t\t/* Section header table file offset */\n  Elf64_Word\te_flags;\t\t/* Processor-specific flags */\n  Elf64_Half\te_ehsize;\t\t/* ELF header size in bytes */\n  Elf64_Half\te_phentsize;\t\t/* Program header table entry size */\n  Elf64_Half\te_phnum;\t\t/* Program header table entry count */\n  Elf64_Half\te_shentsize;\t\t/* Section header table entry size */\n  Elf64_Half\te_shnum;\t\t/* Section header table entry count */\n  Elf64_Half\te_shstrndx;\t\t/* Section header string table index */\n} Elf64_Ehdr;\n\n/* Fields in the e_ident array.  The EI_* macros are indices into the\n   array.  The macros under each EI_* macro are the values the byte\n   may have.  */\n\n#define EI_MAG0\t\t0\t\t/* File identification byte 0 index */\n#define ELFMAG0\t\t0x7f\t\t/* Magic number byte 0 */\n\n#define EI_MAG1\t\t1\t\t/* File identification byte 1 index */\n#define ELFMAG1\t\t'E'\t\t/* Magic number byte 1 */\n\n#define EI_MAG2\t\t2\t\t/* File identification byte 2 index */\n#define ELFMAG2\t\t'L'\t\t/* Magic number byte 2 */\n\n#define EI_MAG3\t\t3\t\t/* File identification byte 3 index */\n#define ELFMAG3\t\t'F'\t\t/* Magic number byte 3 */\n\n/* Conglomeration of the identification bytes, for easy testing as a word.  */\n#define\tELFMAG\t\t\"\\177ELF\"\n#define\tSELFMAG\t\t4\n\n#define EI_CLASS\t4\t\t/* File class byte index */\n#define ELFCLASSNONE\t0\t\t/* Invalid class */\n#define ELFCLASS32\t1\t\t/* 32-bit objects */\n#define ELFCLASS64\t2\t\t/* 64-bit objects */\n#define ELFCLASSNUM\t3\n\n#define EI_DATA\t\t5\t\t/* Data encoding byte index */\n#define ELFDATANONE\t0\t\t/* Invalid data encoding */\n#define ELFDATA2LSB\t1\t\t/* 2's complement, little endian */\n#define ELFDATA2MSB\t2\t\t/* 2's complement, big endian */\n#define ELFDATANUM\t3\n\n#define EI_VERSION\t6\t\t/* File version byte index */\n\t\t\t\t\t/* Value must be EV_CURRENT */\n\n#define EI_OSABI\t7\t\t/* OS ABI identification */\n#define ELFOSABI_NONE\t\t0\t/* UNIX System V ABI */\n#define ELFOSABI_SYSV\t\t0\t/* Alias.  */\n#define ELFOSABI_HPUX\t\t1\t/* HP-UX */\n#define ELFOSABI_NETBSD\t\t2\t/* NetBSD.  */\n#define ELFOSABI_LINUX\t\t3\t/* Linux.  */\n#define ELFOSABI_SOLARIS\t6\t/* Sun Solaris.  */\n#define ELFOSABI_AIX\t\t7\t/* IBM AIX.  */\n#define ELFOSABI_IRIX\t\t8\t/* SGI Irix.  */\n#define ELFOSABI_FREEBSD\t9\t/* FreeBSD.  */\n#define ELFOSABI_TRU64\t\t10\t/* Compaq TRU64 UNIX.  */\n#define ELFOSABI_MODESTO\t11\t/* Novell Modesto.  */\n#define ELFOSABI_OPENBSD\t12\t/* OpenBSD.  */\n#define ELFOSABI_ARM\t\t97\t/* ARM */\n#define ELFOSABI_STANDALONE\t255\t/* Standalone (embedded) application */\n\n#define EI_ABIVERSION\t8\t\t/* ABI version */\n\n#define EI_PAD\t\t9\t\t/* Byte index of padding bytes */\n\n/* Legal values for e_type (object file type).  */\n\n#define ET_NONE\t\t0\t\t/* No file type */\n#define ET_REL\t\t1\t\t/* Relocatable file */\n#define ET_EXEC\t\t2\t\t/* Executable file */\n#define ET_DYN\t\t3\t\t/* Shared object file */\n#define ET_CORE\t\t4\t\t/* Core file */\n#define\tET_NUM\t\t5\t\t/* Number of defined types */\n#define ET_LOOS\t\t0xfe00\t\t/* OS-specific range start */\n#define ET_HIOS\t\t0xfeff\t\t/* OS-specific range end */\n#define ET_LOPROC\t0xff00\t\t/* Processor-specific range start */\n#define ET_HIPROC\t0xffff\t\t/* Processor-specific range end */\n\n/* Legal values for e_machine (architecture).  */\n\n#define EM_NONE\t\t 0\t\t/* No machine */\n#define EM_M32\t\t 1\t\t/* AT&T WE 32100 */\n#define EM_SPARC\t 2\t\t/* SUN SPARC */\n#define EM_386\t\t 3\t\t/* Intel 80386 */\n#define EM_68K\t\t 4\t\t/* Motorola m68k family */\n#define EM_88K\t\t 5\t\t/* Motorola m88k family */\n#define EM_860\t\t 7\t\t/* Intel 80860 */\n#define EM_MIPS\t\t 8\t\t/* MIPS R3000 big-endian */\n#define EM_S370\t\t 9\t\t/* IBM System/370 */\n#define EM_MIPS_RS3_LE\t10\t\t/* MIPS R3000 little-endian */\n\n#define EM_PARISC\t15\t\t/* HPPA */\n#define EM_VPP500\t17\t\t/* Fujitsu VPP500 */\n#define EM_SPARC32PLUS\t18\t\t/* Sun's \"v8plus\" */\n#define EM_960\t\t19\t\t/* Intel 80960 */\n#define EM_PPC\t\t20\t\t/* PowerPC */\n#define EM_PPC64\t21\t\t/* PowerPC 64-bit */\n#define EM_S390\t\t22\t\t/* IBM S390 */\n\n#define EM_V800\t\t36\t\t/* NEC V800 series */\n#define EM_FR20\t\t37\t\t/* Fujitsu FR20 */\n#define EM_RH32\t\t38\t\t/* TRW RH-32 */\n#define EM_RCE\t\t39\t\t/* Motorola RCE */\n#define EM_ARM\t\t40\t\t/* ARM */\n#define EM_FAKE_ALPHA\t41\t\t/* Digital Alpha */\n#define EM_SH\t\t42\t\t/* Hitachi SH */\n#define EM_SPARCV9\t43\t\t/* SPARC v9 64-bit */\n#define EM_TRICORE\t44\t\t/* Siemens Tricore */\n#define EM_ARC\t\t45\t\t/* Argonaut RISC Core */\n#define EM_H8_300\t46\t\t/* Hitachi H8/300 */\n#define EM_H8_300H\t47\t\t/* Hitachi H8/300H */\n#define EM_H8S\t\t48\t\t/* Hitachi H8S */\n#define EM_H8_500\t49\t\t/* Hitachi H8/500 */\n#define EM_IA_64\t50\t\t/* Intel Merced */\n#define EM_MIPS_X\t51\t\t/* Stanford MIPS-X */\n#define EM_COLDFIRE\t52\t\t/* Motorola Coldfire */\n#define EM_68HC12\t53\t\t/* Motorola M68HC12 */\n#define EM_MMA\t\t54\t\t/* Fujitsu MMA Multimedia Accelerator*/\n#define EM_PCP\t\t55\t\t/* Siemens PCP */\n#define EM_NCPU\t\t56\t\t/* Sony nCPU embeeded RISC */\n#define EM_NDR1\t\t57\t\t/* Denso NDR1 microprocessor */\n#define EM_STARCORE\t58\t\t/* Motorola Start*Core processor */\n#define EM_ME16\t\t59\t\t/* Toyota ME16 processor */\n#define EM_ST100\t60\t\t/* STMicroelectronic ST100 processor */\n#define EM_TINYJ\t61\t\t/* Advanced Logic Corp. Tinyj emb.fam*/\n#define EM_X86_64\t62\t\t/* AMD x86-64 architecture */\n#define EM_PDSP\t\t63\t\t/* Sony DSP Processor */\n\n#define EM_FX66\t\t66\t\t/* Siemens FX66 microcontroller */\n#define EM_ST9PLUS\t67\t\t/* STMicroelectronics ST9+ 8/16 mc */\n#define EM_ST7\t\t68\t\t/* STmicroelectronics ST7 8 bit mc */\n#define EM_68HC16\t69\t\t/* Motorola MC68HC16 microcontroller */\n#define EM_68HC11\t70\t\t/* Motorola MC68HC11 microcontroller */\n#define EM_68HC08\t71\t\t/* Motorola MC68HC08 microcontroller */\n#define EM_68HC05\t72\t\t/* Motorola MC68HC05 microcontroller */\n#define EM_SVX\t\t73\t\t/* Silicon Graphics SVx */\n#define EM_ST19\t\t74\t\t/* STMicroelectronics ST19 8 bit mc */\n#define EM_VAX\t\t75\t\t/* Digital VAX */\n#define EM_CRIS\t\t76\t\t/* Axis Communications 32-bit embedded processor */\n#define EM_JAVELIN\t77\t\t/* Infineon Technologies 32-bit embedded processor */\n#define EM_FIREPATH\t78\t\t/* Element 14 64-bit DSP Processor */\n#define EM_ZSP\t\t79\t\t/* LSI Logic 16-bit DSP Processor */\n#define EM_MMIX\t\t80\t\t/* Donald Knuth's educational 64-bit processor */\n#define EM_HUANY\t81\t\t/* Harvard University machine-independent object files */\n#define EM_PRISM\t82\t\t/* SiTera Prism */\n#define EM_AVR\t\t83\t\t/* Atmel AVR 8-bit microcontroller */\n#define EM_FR30\t\t84\t\t/* Fujitsu FR30 */\n#define EM_D10V\t\t85\t\t/* Mitsubishi D10V */\n#define EM_D30V\t\t86\t\t/* Mitsubishi D30V */\n#define EM_V850\t\t87\t\t/* NEC v850 */\n#define EM_M32R\t\t88\t\t/* Mitsubishi M32R */\n#define EM_MN10300\t89\t\t/* Matsushita MN10300 */\n#define EM_MN10200\t90\t\t/* Matsushita MN10200 */\n#define EM_PJ\t\t91\t\t/* picoJava */\n#define EM_OPENRISC\t92\t\t/* OpenRISC 32-bit embedded processor */\n#define EM_ARC_A5\t93\t\t/* ARC Cores Tangent-A5 */\n#define EM_XTENSA\t94\t\t/* Tensilica Xtensa Architecture */\n#define EM_NUM\t\t95\n\n/* If it is necessary to assign new unofficial EM_* values, please\n   pick large random numbers (0x8523, 0xa7f2, etc.) to minimize the\n   chances of collision with official or non-GNU unofficial values.  */\n\n#define EM_ALPHA\t0x9026\n\n/* Legal values for e_version (version).  */\n\n#define EV_NONE\t\t0\t\t/* Invalid ELF version */\n#define EV_CURRENT\t1\t\t/* Current version */\n#define EV_NUM\t\t2\n\n/* Section header.  */\n\ntypedef struct\n{\n  Elf32_Word\tsh_name;\t\t/* Section name (string tbl index) */\n  Elf32_Word\tsh_type;\t\t/* Section type */\n  Elf32_Word\tsh_flags;\t\t/* Section flags */\n  Elf32_Addr\tsh_addr;\t\t/* Section virtual addr at execution */\n  Elf32_Off\tsh_offset;\t\t/* Section file offset */\n  Elf32_Word\tsh_size;\t\t/* Section size in bytes */\n  Elf32_Word\tsh_link;\t\t/* Link to another section */\n  Elf32_Word\tsh_info;\t\t/* Additional section information */\n  Elf32_Word\tsh_addralign;\t\t/* Section alignment */\n  Elf32_Word\tsh_entsize;\t\t/* Entry size if section holds table */\n} Elf32_Shdr;\n\ntypedef struct\n{\n  Elf64_Word\tsh_name;\t\t/* Section name (string tbl index) */\n  Elf64_Word\tsh_type;\t\t/* Section type */\n  Elf64_Xword\tsh_flags;\t\t/* Section flags */\n  Elf64_Addr\tsh_addr;\t\t/* Section virtual addr at execution */\n  Elf64_Off\tsh_offset;\t\t/* Section file offset */\n  Elf64_Xword\tsh_size;\t\t/* Section size in bytes */\n  Elf64_Word\tsh_link;\t\t/* Link to another section */\n  Elf64_Word\tsh_info;\t\t/* Additional section information */\n  Elf64_Xword\tsh_addralign;\t\t/* Section alignment */\n  Elf64_Xword\tsh_entsize;\t\t/* Entry size if section holds table */\n} Elf64_Shdr;\n\n/* Special section indices.  */\n\n#define SHN_UNDEF\t0\t\t/* Undefined section */\n#define SHN_LORESERVE\t0xff00\t\t/* Start of reserved indices */\n#define SHN_LOPROC\t0xff00\t\t/* Start of processor-specific */\n#define SHN_BEFORE\t0xff00\t\t/* Order section before all others\n\t\t\t\t\t   (Solaris).  */\n#define SHN_AFTER\t0xff01\t\t/* Order section after all others\n\t\t\t\t\t   (Solaris).  */\n#define SHN_HIPROC\t0xff1f\t\t/* End of processor-specific */\n#define SHN_LOOS\t0xff20\t\t/* Start of OS-specific */\n#define SHN_HIOS\t0xff3f\t\t/* End of OS-specific */\n#define SHN_ABS\t\t0xfff1\t\t/* Associated symbol is absolute */\n#define SHN_COMMON\t0xfff2\t\t/* Associated symbol is common */\n#define SHN_XINDEX\t0xffff\t\t/* Index is in extra table.  */\n#define SHN_HIRESERVE\t0xffff\t\t/* End of reserved indices */\n\n/* Legal values for sh_type (section type).  */\n\n#define SHT_NULL\t  0\t\t/* Section header table entry unused */\n#define SHT_PROGBITS\t  1\t\t/* Program data */\n#define SHT_SYMTAB\t  2\t\t/* Symbol table */\n#define SHT_STRTAB\t  3\t\t/* String table */\n#define SHT_RELA\t  4\t\t/* Relocation entries with addends */\n#define SHT_HASH\t  5\t\t/* Symbol hash table */\n#define SHT_DYNAMIC\t  6\t\t/* Dynamic linking information */\n#define SHT_NOTE\t  7\t\t/* Notes */\n#define SHT_NOBITS\t  8\t\t/* Program space with no data (bss) */\n#define SHT_REL\t\t  9\t\t/* Relocation entries, no addends */\n#define SHT_SHLIB\t  10\t\t/* Reserved */\n#define SHT_DYNSYM\t  11\t\t/* Dynamic linker symbol table */\n#define SHT_INIT_ARRAY\t  14\t\t/* Array of constructors */\n#define SHT_FINI_ARRAY\t  15\t\t/* Array of destructors */\n#define SHT_PREINIT_ARRAY 16\t\t/* Array of pre-constructors */\n#define SHT_GROUP\t  17\t\t/* Section group */\n#define SHT_SYMTAB_SHNDX  18\t\t/* Extended section indeces */\n#define\tSHT_NUM\t\t  19\t\t/* Number of defined types.  */\n#define SHT_LOOS\t  0x60000000\t/* Start OS-specific */\n#define SHT_GNU_LIBLIST\t  0x6ffffff7\t/* Prelink library list */\n#define SHT_CHECKSUM\t  0x6ffffff8\t/* Checksum for DSO content.  */\n#define SHT_LOSUNW\t  0x6ffffffa\t/* Sun-specific low bound.  */\n#define SHT_SUNW_move\t  0x6ffffffa\n#define SHT_SUNW_COMDAT   0x6ffffffb\n#define SHT_SUNW_syminfo  0x6ffffffc\n#define SHT_GNU_verdef\t  0x6ffffffd\t/* Version definition section.  */\n#define SHT_GNU_verneed\t  0x6ffffffe\t/* Version needs section.  */\n#define SHT_GNU_versym\t  0x6fffffff\t/* Version symbol table.  */\n#define SHT_HISUNW\t  0x6fffffff\t/* Sun-specific high bound.  */\n#define SHT_HIOS\t  0x6fffffff\t/* End OS-specific type */\n#define SHT_LOPROC\t  0x70000000\t/* Start of processor-specific */\n#define SHT_HIPROC\t  0x7fffffff\t/* End of processor-specific */\n#define SHT_LOUSER\t  0x80000000\t/* Start of application-specific */\n#define SHT_HIUSER\t  0x8fffffff\t/* End of application-specific */\n\n/* Legal values for sh_flags (section flags).  */\n\n#define SHF_WRITE\t     (1 << 0)\t/* Writable */\n#define SHF_ALLOC\t     (1 << 1)\t/* Occupies memory during execution */\n#define SHF_EXECINSTR\t     (1 << 2)\t/* Executable */\n#define SHF_MERGE\t     (1 << 4)\t/* Might be merged */\n#define SHF_STRINGS\t     (1 << 5)\t/* Contains nul-terminated strings */\n#define SHF_INFO_LINK\t     (1 << 6)\t/* `sh_info' contains SHT index */\n#define SHF_LINK_ORDER\t     (1 << 7)\t/* Preserve order after combining */\n#define SHF_OS_NONCONFORMING (1 << 8)\t/* Non-standard OS specific handling\n\t\t\t\t\t   required */\n#define SHF_GROUP\t     (1 << 9)\t/* Section is member of a group.  */\n#define SHF_TLS\t\t     (1 << 10)\t/* Section hold thread-local data.  */\n#define SHF_MASKOS\t     0x0ff00000\t/* OS-specific.  */\n#define SHF_MASKPROC\t     0xf0000000\t/* Processor-specific */\n#define SHF_ORDERED\t     (1 << 30)\t/* Special ordering requirement\n\t\t\t\t\t   (Solaris).  */\n#define SHF_EXCLUDE\t     (1 << 31)\t/* Section is excluded unless\n\t\t\t\t\t   referenced or allocated (Solaris).*/\n\n/* Section group handling.  */\n#define GRP_COMDAT\t0x1\t\t/* Mark group as COMDAT.  */\n\n/* Symbol table entry.  */\n\ntypedef struct\n{\n  Elf32_Word\tst_name;\t\t/* Symbol name (string tbl index) */\n  Elf32_Addr\tst_value;\t\t/* Symbol value */\n  Elf32_Word\tst_size;\t\t/* Symbol size */\n  unsigned char\tst_info;\t\t/* Symbol type and binding */\n  unsigned char\tst_other;\t\t/* Symbol visibility */\n  Elf32_Section\tst_shndx;\t\t/* Section index */\n} Elf32_Sym;\n\ntypedef struct\n{\n  Elf64_Word\tst_name;\t\t/* Symbol name (string tbl index) */\n  unsigned char\tst_info;\t\t/* Symbol type and binding */\n  unsigned char st_other;\t\t/* Symbol visibility */\n  Elf64_Section\tst_shndx;\t\t/* Section index */\n  Elf64_Addr\tst_value;\t\t/* Symbol value */\n  Elf64_Xword\tst_size;\t\t/* Symbol size */\n} Elf64_Sym;\n\n/* The syminfo section if available contains additional information about\n   every dynamic symbol.  */\n\ntypedef struct\n{\n  Elf32_Half si_boundto;\t\t/* Direct bindings, symbol bound to */\n  Elf32_Half si_flags;\t\t\t/* Per symbol flags */\n} Elf32_Syminfo;\n\ntypedef struct\n{\n  Elf64_Half si_boundto;\t\t/* Direct bindings, symbol bound to */\n  Elf64_Half si_flags;\t\t\t/* Per symbol flags */\n} Elf64_Syminfo;\n\n/* Possible values for si_boundto.  */\n#define SYMINFO_BT_SELF\t\t0xffff\t/* Symbol bound to self */\n#define SYMINFO_BT_PARENT\t0xfffe\t/* Symbol bound to parent */\n#define SYMINFO_BT_LOWRESERVE\t0xff00\t/* Beginning of reserved entries */\n\n/* Possible bitmasks for si_flags.  */\n#define SYMINFO_FLG_DIRECT\t0x0001\t/* Direct bound symbol */\n#define SYMINFO_FLG_PASSTHRU\t0x0002\t/* Pass-thru symbol for translator */\n#define SYMINFO_FLG_COPY\t0x0004\t/* Symbol is a copy-reloc */\n#define SYMINFO_FLG_LAZYLOAD\t0x0008\t/* Symbol bound to object to be lazy\n\t\t\t\t\t   loaded */\n/* Syminfo version values.  */\n#define SYMINFO_NONE\t\t0\n#define SYMINFO_CURRENT\t\t1\n#define SYMINFO_NUM\t\t2\n\n\n/* How to extract and insert information held in the st_info field.  */\n\n#define ELF32_ST_BIND(val)\t\t(((unsigned char) (val)) >> 4)\n#define ELF32_ST_TYPE(val)\t\t((val) & 0xf)\n#define ELF32_ST_INFO(bind, type)\t(((bind) << 4) + ((type) & 0xf))\n\n/* Both Elf32_Sym and Elf64_Sym use the same one-byte st_info field.  */\n#define ELF64_ST_BIND(val)\t\tELF32_ST_BIND (val)\n#define ELF64_ST_TYPE(val)\t\tELF32_ST_TYPE (val)\n#define ELF64_ST_INFO(bind, type)\tELF32_ST_INFO ((bind), (type))\n\n/* Legal values for ST_BIND subfield of st_info (symbol binding).  */\n\n#define STB_LOCAL\t0\t\t/* Local symbol */\n#define STB_GLOBAL\t1\t\t/* Global symbol */\n#define STB_WEAK\t2\t\t/* Weak symbol */\n#define\tSTB_NUM\t\t3\t\t/* Number of defined types.  */\n#define STB_LOOS\t10\t\t/* Start of OS-specific */\n#define STB_HIOS\t12\t\t/* End of OS-specific */\n#define STB_LOPROC\t13\t\t/* Start of processor-specific */\n#define STB_HIPROC\t15\t\t/* End of processor-specific */\n\n/* Legal values for ST_TYPE subfield of st_info (symbol type).  */\n\n#define STT_NOTYPE\t0\t\t/* Symbol type is unspecified */\n#define STT_OBJECT\t1\t\t/* Symbol is a data object */\n#define STT_FUNC\t2\t\t/* Symbol is a code object */\n#define STT_SECTION\t3\t\t/* Symbol associated with a section */\n#define STT_FILE\t4\t\t/* Symbol's name is file name */\n#define STT_COMMON\t5\t\t/* Symbol is a common data object */\n#define STT_TLS\t\t6\t\t/* Symbol is thread-local data object*/\n#define\tSTT_NUM\t\t7\t\t/* Number of defined types.  */\n#define STT_LOOS\t10\t\t/* Start of OS-specific */\n#define STT_HIOS\t12\t\t/* End of OS-specific */\n#define STT_LOPROC\t13\t\t/* Start of processor-specific */\n#define STT_HIPROC\t15\t\t/* End of processor-specific */\n\n\n/* Symbol table indices are found in the hash buckets and chain table\n   of a symbol hash table section.  This special index value indicates\n   the end of a chain, meaning no further symbols are found in that bucket.  */\n\n#define STN_UNDEF\t0\t\t/* End of a chain.  */\n\n\n/* How to extract and insert information held in the st_other field.  */\n\n#define ELF32_ST_VISIBILITY(o)\t((o) & 0x03)\n\n/* For ELF64 the definitions are the same.  */\n#define ELF64_ST_VISIBILITY(o)\tELF32_ST_VISIBILITY (o)\n\n/* Symbol visibility specification encoded in the st_other field.  */\n#define STV_DEFAULT\t0\t\t/* Default symbol visibility rules */\n#define STV_INTERNAL\t1\t\t/* Processor specific hidden class */\n#define STV_HIDDEN\t2\t\t/* Sym unavailable in other modules */\n#define STV_PROTECTED\t3\t\t/* Not preemptible, not exported */\n\n\n/* Relocation table entry without addend (in section of type SHT_REL).  */\n\ntypedef struct\n{\n  Elf32_Addr\tr_offset;\t\t/* Address */\n  Elf32_Word\tr_info;\t\t\t/* Relocation type and symbol index */\n} Elf32_Rel;\n\n/* I have seen two different definitions of the Elf64_Rel and\n   Elf64_Rela structures, so we'll leave them out until Novell (or\n   whoever) gets their act together.  */\n/* The following, at least, is used on Sparc v9, MIPS, and Alpha.  */\n\ntypedef struct\n{\n  Elf64_Addr\tr_offset;\t\t/* Address */\n  Elf64_Xword\tr_info;\t\t\t/* Relocation type and symbol index */\n} Elf64_Rel;\n\n/* Relocation table entry with addend (in section of type SHT_RELA).  */\n\ntypedef struct\n{\n  Elf32_Addr\tr_offset;\t\t/* Address */\n  Elf32_Word\tr_info;\t\t\t/* Relocation type and symbol index */\n  Elf32_Sword\tr_addend;\t\t/* Addend */\n} Elf32_Rela;\n\ntypedef struct\n{\n  Elf64_Addr\tr_offset;\t\t/* Address */\n  Elf64_Xword\tr_info;\t\t\t/* Relocation type and symbol index */\n  Elf64_Sxword\tr_addend;\t\t/* Addend */\n} Elf64_Rela;\n\n/* How to extract and insert information held in the r_info field.  */\n\n#define ELF32_R_SYM(val)\t\t((val) >> 8)\n#define ELF32_R_TYPE(val)\t\t((val) & 0xff)\n#define ELF32_R_INFO(sym, type)\t\t(((sym) << 8) + ((type) & 0xff))\n\n#define ELF64_R_SYM(i)\t\t\t((i) >> 32)\n#define ELF64_R_TYPE(i)\t\t\t((i) & 0xffffffff)\n#define ELF64_R_INFO(sym,type)\t\t((((Elf64_Xword) (sym)) << 32) + (type))\n\n/* Program segment header.  */\n\ntypedef struct\n{\n  Elf32_Word\tp_type;\t\t\t/* Segment type */\n  Elf32_Off\tp_offset;\t\t/* Segment file offset */\n  Elf32_Addr\tp_vaddr;\t\t/* Segment virtual address */\n  Elf32_Addr\tp_paddr;\t\t/* Segment physical address */\n  Elf32_Word\tp_filesz;\t\t/* Segment size in file */\n  Elf32_Word\tp_memsz;\t\t/* Segment size in memory */\n  Elf32_Word\tp_flags;\t\t/* Segment flags */\n  Elf32_Word\tp_align;\t\t/* Segment alignment */\n} Elf32_Phdr;\n\ntypedef struct\n{\n  Elf64_Word\tp_type;\t\t\t/* Segment type */\n  Elf64_Word\tp_flags;\t\t/* Segment flags */\n  Elf64_Off\tp_offset;\t\t/* Segment file offset */\n  Elf64_Addr\tp_vaddr;\t\t/* Segment virtual address */\n  Elf64_Addr\tp_paddr;\t\t/* Segment physical address */\n  Elf64_Xword\tp_filesz;\t\t/* Segment size in file */\n  Elf64_Xword\tp_memsz;\t\t/* Segment size in memory */\n  Elf64_Xword\tp_align;\t\t/* Segment alignment */\n} Elf64_Phdr;\n\n/* Legal values for p_type (segment type).  */\n\n#define\tPT_NULL\t\t0\t\t/* Program header table entry unused */\n#define PT_LOAD\t\t1\t\t/* Loadable program segment */\n#define PT_DYNAMIC\t2\t\t/* Dynamic linking information */\n#define PT_INTERP\t3\t\t/* Program interpreter */\n#define PT_NOTE\t\t4\t\t/* Auxiliary information */\n#define PT_SHLIB\t5\t\t/* Reserved */\n#define PT_PHDR\t\t6\t\t/* Entry for header table itself */\n#define PT_TLS\t\t7\t\t/* Thread-local storage segment */\n#define\tPT_NUM\t\t8\t\t/* Number of defined types */\n#define PT_LOOS\t\t0x60000000\t/* Start of OS-specific */\n#define PT_GNU_EH_FRAME\t0x6474e550\t/* GCC .eh_frame_hdr segment */\n#define PT_GNU_STACK\t0x6474e551\t/* Indicates stack executability */\n#define PT_GNU_RELRO\t0x6474e552\t/* Read-only after relocation */\n#define PT_LOSUNW\t0x6ffffffa\n#define PT_SUNWBSS\t0x6ffffffa\t/* Sun Specific segment */\n#define PT_SUNWSTACK\t0x6ffffffb\t/* Stack segment */\n#define PT_HISUNW\t0x6fffffff\n#define PT_HIOS\t\t0x6fffffff\t/* End of OS-specific */\n#define PT_LOPROC\t0x70000000\t/* Start of processor-specific */\n#define PT_HIPROC\t0x7fffffff\t/* End of processor-specific */\n\n/* Legal values for p_flags (segment flags).  */\n\n#define PF_X\t\t(1 << 0)\t/* Segment is executable */\n#define PF_W\t\t(1 << 1)\t/* Segment is writable */\n#define PF_R\t\t(1 << 2)\t/* Segment is readable */\n#define PF_MASKOS\t0x0ff00000\t/* OS-specific */\n#define PF_MASKPROC\t0xf0000000\t/* Processor-specific */\n\n/* Legal values for note segment descriptor types for core files. */\n\n#define NT_PRSTATUS\t1\t\t/* Contains copy of prstatus struct */\n#define NT_FPREGSET\t2\t\t/* Contains copy of fpregset struct */\n#define NT_PRPSINFO\t3\t\t/* Contains copy of prpsinfo struct */\n#define NT_PRXREG\t4\t\t/* Contains copy of prxregset struct */\n#define NT_TASKSTRUCT\t4\t\t/* Contains copy of task structure */\n#define NT_PLATFORM\t5\t\t/* String from sysinfo(SI_PLATFORM) */\n#define NT_AUXV\t\t6\t\t/* Contains copy of auxv array */\n#define NT_GWINDOWS\t7\t\t/* Contains copy of gwindows struct */\n#define NT_ASRS\t\t8\t\t/* Contains copy of asrset struct */\n#define NT_PSTATUS\t10\t\t/* Contains copy of pstatus struct */\n#define NT_PSINFO\t13\t\t/* Contains copy of psinfo struct */\n#define NT_PRCRED\t14\t\t/* Contains copy of prcred struct */\n#define NT_UTSNAME\t15\t\t/* Contains copy of utsname struct */\n#define NT_LWPSTATUS\t16\t\t/* Contains copy of lwpstatus struct */\n#define NT_LWPSINFO\t17\t\t/* Contains copy of lwpinfo struct */\n#define NT_PRFPXREG\t20\t\t/* Contains copy of fprxregset struct*/\n\n/* Legal values for the note segment descriptor types for object files.  */\n\n#define NT_VERSION\t1\t\t/* Contains a version string.  */\n\n\n/* Dynamic section entry.  */\n\ntypedef struct\n{\n  Elf32_Sword\td_tag;\t\t\t/* Dynamic entry type */\n  union\n    {\n      Elf32_Word d_val;\t\t\t/* Integer value */\n      Elf32_Addr d_ptr;\t\t\t/* Address value */\n    } d_un;\n} Elf32_Dyn;\n\ntypedef struct\n{\n  Elf64_Sxword\td_tag;\t\t\t/* Dynamic entry type */\n  union\n    {\n      Elf64_Xword d_val;\t\t/* Integer value */\n      Elf64_Addr d_ptr;\t\t\t/* Address value */\n    } d_un;\n} Elf64_Dyn;\n\n/* Legal values for d_tag (dynamic entry type).  */\n\n#define DT_NULL\t\t0\t\t/* Marks end of dynamic section */\n#define DT_NEEDED\t1\t\t/* Name of needed library */\n#define DT_PLTRELSZ\t2\t\t/* Size in bytes of PLT relocs */\n#define DT_PLTGOT\t3\t\t/* Processor defined value */\n#define DT_HASH\t\t4\t\t/* Address of symbol hash table */\n#define DT_STRTAB\t5\t\t/* Address of string table */\n#define DT_SYMTAB\t6\t\t/* Address of symbol table */\n#define DT_RELA\t\t7\t\t/* Address of Rela relocs */\n#define DT_RELASZ\t8\t\t/* Total size of Rela relocs */\n#define DT_RELAENT\t9\t\t/* Size of one Rela reloc */\n#define DT_STRSZ\t10\t\t/* Size of string table */\n#define DT_SYMENT\t11\t\t/* Size of one symbol table entry */\n#define DT_INIT\t\t12\t\t/* Address of init function */\n#define DT_FINI\t\t13\t\t/* Address of termination function */\n#define DT_SONAME\t14\t\t/* Name of shared object */\n#define DT_RPATH\t15\t\t/* Library search path (deprecated) */\n#define DT_SYMBOLIC\t16\t\t/* Start symbol search here */\n#define DT_REL\t\t17\t\t/* Address of Rel relocs */\n#define DT_RELSZ\t18\t\t/* Total size of Rel relocs */\n#define DT_RELENT\t19\t\t/* Size of one Rel reloc */\n#define DT_PLTREL\t20\t\t/* Type of reloc in PLT */\n#define DT_DEBUG\t21\t\t/* For debugging; unspecified */\n#define DT_TEXTREL\t22\t\t/* Reloc might modify .text */\n#define DT_JMPREL\t23\t\t/* Address of PLT relocs */\n#define\tDT_BIND_NOW\t24\t\t/* Process relocations of object */\n#define\tDT_INIT_ARRAY\t25\t\t/* Array with addresses of init fct */\n#define\tDT_FINI_ARRAY\t26\t\t/* Array with addresses of fini fct */\n#define\tDT_INIT_ARRAYSZ\t27\t\t/* Size in bytes of DT_INIT_ARRAY */\n#define\tDT_FINI_ARRAYSZ\t28\t\t/* Size in bytes of DT_FINI_ARRAY */\n#define DT_RUNPATH\t29\t\t/* Library search path */\n#define DT_FLAGS\t30\t\t/* Flags for the object being loaded */\n#define DT_ENCODING\t32\t\t/* Start of encoded range */\n#define DT_PREINIT_ARRAY 32\t\t/* Array with addresses of preinit fct*/\n#define DT_PREINIT_ARRAYSZ 33\t\t/* size in bytes of DT_PREINIT_ARRAY */\n#define\tDT_NUM\t\t34\t\t/* Number used */\n#define DT_LOOS\t\t0x6000000d\t/* Start of OS-specific */\n#define DT_HIOS\t\t0x6ffff000\t/* End of OS-specific */\n#define DT_LOPROC\t0x70000000\t/* Start of processor-specific */\n#define DT_HIPROC\t0x7fffffff\t/* End of processor-specific */\n#define\tDT_PROCNUM\tDT_MIPS_NUM\t/* Most used by any processor */\n\n/* DT_* entries which fall between DT_VALRNGHI & DT_VALRNGLO use the\n   Dyn.d_un.d_val field of the Elf*_Dyn structure.  This follows Sun's\n   approach.  */\n#define DT_VALRNGLO\t0x6ffffd00\n#define DT_GNU_PRELINKED 0x6ffffdf5\t/* Prelinking timestamp */\n#define DT_GNU_CONFLICTSZ 0x6ffffdf6\t/* Size of conflict section */\n#define DT_GNU_LIBLISTSZ 0x6ffffdf7\t/* Size of library list */\n#define DT_CHECKSUM\t0x6ffffdf8\n#define DT_PLTPADSZ\t0x6ffffdf9\n#define DT_MOVEENT\t0x6ffffdfa\n#define DT_MOVESZ\t0x6ffffdfb\n#define DT_FEATURE_1\t0x6ffffdfc\t/* Feature selection (DTF_*).  */\n#define DT_POSFLAG_1\t0x6ffffdfd\t/* Flags for DT_* entries, effecting\n\t\t\t\t\t   the following DT_* entry.  */\n#define DT_SYMINSZ\t0x6ffffdfe\t/* Size of syminfo table (in bytes) */\n#define DT_SYMINENT\t0x6ffffdff\t/* Entry size of syminfo */\n#define DT_VALRNGHI\t0x6ffffdff\n#define DT_VALTAGIDX(tag)\t(DT_VALRNGHI - (tag))\t/* Reverse order! */\n#define DT_VALNUM 12\n\n/* DT_* entries which fall between DT_ADDRRNGHI & DT_ADDRRNGLO use the\n   Dyn.d_un.d_ptr field of the Elf*_Dyn structure.\n\n   If any adjustment is made to the ELF object after it has been\n   built these entries will need to be adjusted.  */\n#define DT_ADDRRNGLO\t0x6ffffe00\n#define DT_GNU_CONFLICT\t0x6ffffef8\t/* Start of conflict section */\n#define DT_GNU_LIBLIST\t0x6ffffef9\t/* Library list */\n#define DT_CONFIG\t0x6ffffefa\t/* Configuration information.  */\n#define DT_DEPAUDIT\t0x6ffffefb\t/* Dependency auditing.  */\n#define DT_AUDIT\t0x6ffffefc\t/* Object auditing.  */\n#define\tDT_PLTPAD\t0x6ffffefd\t/* PLT padding.  */\n#define\tDT_MOVETAB\t0x6ffffefe\t/* Move table.  */\n#define DT_SYMINFO\t0x6ffffeff\t/* Syminfo table.  */\n#define DT_ADDRRNGHI\t0x6ffffeff\n#define DT_ADDRTAGIDX(tag)\t(DT_ADDRRNGHI - (tag))\t/* Reverse order! */\n#define DT_ADDRNUM 10\n\n/* The versioning entry types.  The next are defined as part of the\n   GNU extension.  */\n#define DT_VERSYM\t0x6ffffff0\n\n#define DT_RELACOUNT\t0x6ffffff9\n#define DT_RELCOUNT\t0x6ffffffa\n\n/* These were chosen by Sun.  */\n#define DT_FLAGS_1\t0x6ffffffb\t/* State flags, see DF_1_* below.  */\n#define\tDT_VERDEF\t0x6ffffffc\t/* Address of version definition\n\t\t\t\t\t   table */\n#define\tDT_VERDEFNUM\t0x6ffffffd\t/* Number of version definitions */\n#define\tDT_VERNEED\t0x6ffffffe\t/* Address of table with needed\n\t\t\t\t\t   versions */\n#define\tDT_VERNEEDNUM\t0x6fffffff\t/* Number of needed versions */\n#define DT_VERSIONTAGIDX(tag)\t(DT_VERNEEDNUM - (tag))\t/* Reverse order! */\n#define DT_VERSIONTAGNUM 16\n\n/* Sun added these machine-independent extensions in the \"processor-specific\"\n   range.  Be compatible.  */\n#define DT_AUXILIARY    0x7ffffffd      /* Shared object to load before self */\n#define DT_FILTER       0x7fffffff      /* Shared object to get values from */\n#define DT_EXTRATAGIDX(tag)\t((Elf32_Word)-((Elf32_Sword) (tag) <<1>>1)-1)\n#define DT_EXTRANUM\t3\n\n/* Values of `d_un.d_val' in the DT_FLAGS entry.  */\n#define DF_ORIGIN\t0x00000001\t/* Object may use DF_ORIGIN */\n#define DF_SYMBOLIC\t0x00000002\t/* Symbol resolutions starts here */\n#define DF_TEXTREL\t0x00000004\t/* Object contains text relocations */\n#define DF_BIND_NOW\t0x00000008\t/* No lazy binding for this object */\n#define DF_STATIC_TLS\t0x00000010\t/* Module uses the static TLS model */\n\n/* State flags selectable in the `d_un.d_val' element of the DT_FLAGS_1\n   entry in the dynamic section.  */\n#define DF_1_NOW\t0x00000001\t/* Set RTLD_NOW for this object.  */\n#define DF_1_GLOBAL\t0x00000002\t/* Set RTLD_GLOBAL for this object.  */\n#define DF_1_GROUP\t0x00000004\t/* Set RTLD_GROUP for this object.  */\n#define DF_1_NODELETE\t0x00000008\t/* Set RTLD_NODELETE for this object.*/\n#define DF_1_LOADFLTR\t0x00000010\t/* Trigger filtee loading at runtime.*/\n#define DF_1_INITFIRST\t0x00000020\t/* Set RTLD_INITFIRST for this object*/\n#define DF_1_NOOPEN\t0x00000040\t/* Set RTLD_NOOPEN for this object.  */\n#define DF_1_ORIGIN\t0x00000080\t/* $ORIGIN must be handled.  */\n#define DF_1_DIRECT\t0x00000100\t/* Direct binding enabled.  */\n#define DF_1_TRANS\t0x00000200\n#define DF_1_INTERPOSE\t0x00000400\t/* Object is used to interpose.  */\n#define DF_1_NODEFLIB\t0x00000800\t/* Ignore default lib search path.  */\n#define DF_1_NODUMP\t0x00001000\t/* Object can't be dldump'ed.  */\n#define DF_1_CONFALT\t0x00002000\t/* Configuration alternative created.*/\n#define DF_1_ENDFILTEE\t0x00004000\t/* Filtee terminates filters search. */\n#define\tDF_1_DISPRELDNE\t0x00008000\t/* Disp reloc applied at build time. */\n#define\tDF_1_DISPRELPND\t0x00010000\t/* Disp reloc applied at run-time.  */\n\n/* Flags for the feature selection in DT_FEATURE_1.  */\n#define DTF_1_PARINIT\t0x00000001\n#define DTF_1_CONFEXP\t0x00000002\n\n/* Flags in the DT_POSFLAG_1 entry effecting only the next DT_* entry.  */\n#define DF_P1_LAZYLOAD\t0x00000001\t/* Lazyload following object.  */\n#define DF_P1_GROUPPERM\t0x00000002\t/* Symbols from next object are not\n\t\t\t\t\t   generally available.  */\n\n/* Version definition sections.  */\n\ntypedef struct\n{\n  Elf32_Half\tvd_version;\t\t/* Version revision */\n  Elf32_Half\tvd_flags;\t\t/* Version information */\n  Elf32_Half\tvd_ndx;\t\t\t/* Version Index */\n  Elf32_Half\tvd_cnt;\t\t\t/* Number of associated aux entries */\n  Elf32_Word\tvd_hash;\t\t/* Version name hash value */\n  Elf32_Word\tvd_aux;\t\t\t/* Offset in bytes to verdaux array */\n  Elf32_Word\tvd_next;\t\t/* Offset in bytes to next verdef\n\t\t\t\t\t   entry */\n} Elf32_Verdef;\n\ntypedef struct\n{\n  Elf64_Half\tvd_version;\t\t/* Version revision */\n  Elf64_Half\tvd_flags;\t\t/* Version information */\n  Elf64_Half\tvd_ndx;\t\t\t/* Version Index */\n  Elf64_Half\tvd_cnt;\t\t\t/* Number of associated aux entries */\n  Elf64_Word\tvd_hash;\t\t/* Version name hash value */\n  Elf64_Word\tvd_aux;\t\t\t/* Offset in bytes to verdaux array */\n  Elf64_Word\tvd_next;\t\t/* Offset in bytes to next verdef\n\t\t\t\t\t   entry */\n} Elf64_Verdef;\n\n\n/* Legal values for vd_version (version revision).  */\n#define VER_DEF_NONE\t0\t\t/* No version */\n#define VER_DEF_CURRENT\t1\t\t/* Current version */\n#define VER_DEF_NUM\t2\t\t/* Given version number */\n\n/* Legal values for vd_flags (version information flags).  */\n#define VER_FLG_BASE\t0x1\t\t/* Version definition of file itself */\n#define VER_FLG_WEAK\t0x2\t\t/* Weak version identifier */\n\n/* Versym symbol index values.  */\n#define\tVER_NDX_LOCAL\t\t0\t/* Symbol is local.  */\n#define\tVER_NDX_GLOBAL\t\t1\t/* Symbol is global.  */\n#define\tVER_NDX_LORESERVE\t0xff00\t/* Beginning of reserved entries.  */\n#define\tVER_NDX_ELIMINATE\t0xff01\t/* Symbol is to be eliminated.  */\n\n/* Auxialiary version information.  */\n\ntypedef struct\n{\n  Elf32_Word\tvda_name;\t\t/* Version or dependency names */\n  Elf32_Word\tvda_next;\t\t/* Offset in bytes to next verdaux\n\t\t\t\t\t   entry */\n} Elf32_Verdaux;\n\ntypedef struct\n{\n  Elf64_Word\tvda_name;\t\t/* Version or dependency names */\n  Elf64_Word\tvda_next;\t\t/* Offset in bytes to next verdaux\n\t\t\t\t\t   entry */\n} Elf64_Verdaux;\n\n\n/* Version dependency section.  */\n\ntypedef struct\n{\n  Elf32_Half\tvn_version;\t\t/* Version of structure */\n  Elf32_Half\tvn_cnt;\t\t\t/* Number of associated aux entries */\n  Elf32_Word\tvn_file;\t\t/* Offset of filename for this\n\t\t\t\t\t   dependency */\n  Elf32_Word\tvn_aux;\t\t\t/* Offset in bytes to vernaux array */\n  Elf32_Word\tvn_next;\t\t/* Offset in bytes to next verneed\n\t\t\t\t\t   entry */\n} Elf32_Verneed;\n\ntypedef struct\n{\n  Elf64_Half\tvn_version;\t\t/* Version of structure */\n  Elf64_Half\tvn_cnt;\t\t\t/* Number of associated aux entries */\n  Elf64_Word\tvn_file;\t\t/* Offset of filename for this\n\t\t\t\t\t   dependency */\n  Elf64_Word\tvn_aux;\t\t\t/* Offset in bytes to vernaux array */\n  Elf64_Word\tvn_next;\t\t/* Offset in bytes to next verneed\n\t\t\t\t\t   entry */\n} Elf64_Verneed;\n\n\n/* Legal values for vn_version (version revision).  */\n#define VER_NEED_NONE\t 0\t\t/* No version */\n#define VER_NEED_CURRENT 1\t\t/* Current version */\n#define VER_NEED_NUM\t 2\t\t/* Given version number */\n\n/* Auxiliary needed version information.  */\n\ntypedef struct\n{\n  Elf32_Word\tvna_hash;\t\t/* Hash value of dependency name */\n  Elf32_Half\tvna_flags;\t\t/* Dependency specific information */\n  Elf32_Half\tvna_other;\t\t/* Unused */\n  Elf32_Word\tvna_name;\t\t/* Dependency name string offset */\n  Elf32_Word\tvna_next;\t\t/* Offset in bytes to next vernaux\n\t\t\t\t\t   entry */\n} Elf32_Vernaux;\n\ntypedef struct\n{\n  Elf64_Word\tvna_hash;\t\t/* Hash value of dependency name */\n  Elf64_Half\tvna_flags;\t\t/* Dependency specific information */\n  Elf64_Half\tvna_other;\t\t/* Unused */\n  Elf64_Word\tvna_name;\t\t/* Dependency name string offset */\n  Elf64_Word\tvna_next;\t\t/* Offset in bytes to next vernaux\n\t\t\t\t\t   entry */\n} Elf64_Vernaux;\n\n\n/* Legal values for vna_flags.  */\n#define VER_FLG_WEAK\t0x2\t\t/* Weak version identifier */\n\n\n/* Auxiliary vector.  */\n\n/* This vector is normally only used by the program interpreter.  The\n   usual definition in an ABI supplement uses the name auxv_t.  The\n   vector is not usually defined in a standard <elf.h> file, but it\n   can't hurt.  We rename it to avoid conflicts.  The sizes of these\n   types are an arrangement between the exec server and the program\n   interpreter, so we don't fully specify them here.  */\n\ntypedef struct\n{\n  int a_type;\t\t\t/* Entry type */\n  union\n    {\n      long int a_val;\t\t/* Integer value */\n      void *a_ptr;\t\t/* Pointer value */\n      void (*a_fcn) (void);\t/* Function pointer value */\n    } a_un;\n} Elf32_auxv_t;\n\ntypedef struct\n{\n  long int a_type;\t\t/* Entry type */\n  union\n    {\n      long int a_val;\t\t/* Integer value */\n      void *a_ptr;\t\t/* Pointer value */\n      void (*a_fcn) (void);\t/* Function pointer value */\n    } a_un;\n} Elf64_auxv_t;\n\n/* Legal values for a_type (entry type).  */\n\n#define AT_NULL\t\t0\t\t/* End of vector */\n#define AT_IGNORE\t1\t\t/* Entry should be ignored */\n#define AT_EXECFD\t2\t\t/* File descriptor of program */\n#define AT_PHDR\t\t3\t\t/* Program headers for program */\n#define AT_PHENT\t4\t\t/* Size of program header entry */\n#define AT_PHNUM\t5\t\t/* Number of program headers */\n#define AT_PAGESZ\t6\t\t/* System page size */\n#define AT_BASE\t\t7\t\t/* Base address of interpreter */\n#define AT_FLAGS\t8\t\t/* Flags */\n#define AT_ENTRY\t9\t\t/* Entry point of program */\n#define AT_NOTELF\t10\t\t/* Program is not ELF */\n#define AT_UID\t\t11\t\t/* Real uid */\n#define AT_EUID\t\t12\t\t/* Effective uid */\n#define AT_GID\t\t13\t\t/* Real gid */\n#define AT_EGID\t\t14\t\t/* Effective gid */\n#define AT_CLKTCK\t17\t\t/* Frequency of times() */\n\n/* Some more special a_type values describing the hardware.  */\n#define AT_PLATFORM\t15\t\t/* String identifying platform.  */\n#define AT_HWCAP\t16\t\t/* Machine dependent hints about\n\t\t\t\t\t   processor capabilities.  */\n\n/* This entry gives some information about the FPU initialization\n   performed by the kernel.  */\n#define AT_FPUCW\t18\t\t/* Used FPU control word.  */\n\n/* Cache block sizes.  */\n#define AT_DCACHEBSIZE\t19\t\t/* Data cache block size.  */\n#define AT_ICACHEBSIZE\t20\t\t/* Instruction cache block size.  */\n#define AT_UCACHEBSIZE\t21\t\t/* Unified cache block size.  */\n\n/* A special ignored value for PPC, used by the kernel to control the\n   interpretation of the AUXV. Must be > 16.  */\n#define AT_IGNOREPPC\t22\t\t/* Entry should be ignored.  */\n\n#define\tAT_SECURE\t23\t\t/* Boolean, was exec setuid-like?  */\n\n/* Pointer to the global system page used for system calls and other\n   nice things.  */\n#define AT_SYSINFO\t32\n#define AT_SYSINFO_EHDR\t33\n\n/* Shapes of the caches.  Bits 0-3 contains associativity; bits 4-7 contains\n   log2 of line size; mask those to get cache size.  */\n#define AT_L1I_CACHESHAPE\t34\n#define AT_L1D_CACHESHAPE\t35\n#define AT_L2_CACHESHAPE\t36\n#define AT_L3_CACHESHAPE\t37\n\n/* Note section contents.  Each entry in the note section begins with\n   a header of a fixed form.  */\n\ntypedef struct\n{\n  Elf32_Word n_namesz;\t\t\t/* Length of the note's name.  */\n  Elf32_Word n_descsz;\t\t\t/* Length of the note's descriptor.  */\n  Elf32_Word n_type;\t\t\t/* Type of the note.  */\n} Elf32_Nhdr;\n\ntypedef struct\n{\n  Elf64_Word n_namesz;\t\t\t/* Length of the note's name.  */\n  Elf64_Word n_descsz;\t\t\t/* Length of the note's descriptor.  */\n  Elf64_Word n_type;\t\t\t/* Type of the note.  */\n} Elf64_Nhdr;\n\n/* Known names of notes.  */\n\n/* Solaris entries in the note section have this name.  */\n#define ELF_NOTE_SOLARIS\t\"SUNW Solaris\"\n\n/* Note entries for GNU systems have this name.  */\n#define ELF_NOTE_GNU\t\t\"GNU\"\n\n\n/* Defined types of notes for Solaris.  */\n\n/* Value of descriptor (one word) is desired pagesize for the binary.  */\n#define ELF_NOTE_PAGESIZE_HINT\t1\n\n\n/* Defined note types for GNU systems.  */\n\n/* ABI information.  The descriptor consists of words:\n   word 0: OS descriptor\n   word 1: major version of the ABI\n   word 2: minor version of the ABI\n   word 3: subminor version of the ABI\n*/\n#define ELF_NOTE_ABI\t\t1\n\n/* Known OSes.  These value can appear in word 0 of an ELF_NOTE_ABI\n   note section entry.  */\n#define ELF_NOTE_OS_LINUX\t0\n#define ELF_NOTE_OS_GNU\t\t1\n#define ELF_NOTE_OS_SOLARIS2\t2\n#define ELF_NOTE_OS_FREEBSD\t3\n\n\n/* Move records.  */\ntypedef struct\n{\n  Elf32_Xword m_value;\t\t/* Symbol value.  */\n  Elf32_Word m_info;\t\t/* Size and index.  */\n  Elf32_Word m_poffset;\t\t/* Symbol offset.  */\n  Elf32_Half m_repeat;\t\t/* Repeat count.  */\n  Elf32_Half m_stride;\t\t/* Stride info.  */\n} Elf32_Move;\n\ntypedef struct\n{\n  Elf64_Xword m_value;\t\t/* Symbol value.  */\n  Elf64_Xword m_info;\t\t/* Size and index.  */\n  Elf64_Xword m_poffset;\t/* Symbol offset.  */\n  Elf64_Half m_repeat;\t\t/* Repeat count.  */\n  Elf64_Half m_stride;\t\t/* Stride info.  */\n} Elf64_Move;\n\n/* Macro to construct move records.  */\n#define ELF32_M_SYM(info)\t((info) >> 8)\n#define ELF32_M_SIZE(info)\t((unsigned char) (info))\n#define ELF32_M_INFO(sym, size)\t(((sym) << 8) + (unsigned char) (size))\n\n#define ELF64_M_SYM(info)\tELF32_M_SYM (info)\n#define ELF64_M_SIZE(info)\tELF32_M_SIZE (info)\n#define ELF64_M_INFO(sym, size)\tELF32_M_INFO (sym, size)\n\n\n/* Motorola 68k specific definitions.  */\n\n/* Values for Elf32_Ehdr.e_flags.  */\n#define EF_CPU32\t0x00810000\n\n/* m68k relocs.  */\n\n#define R_68K_NONE\t0\t\t/* No reloc */\n#define R_68K_32\t1\t\t/* Direct 32 bit  */\n#define R_68K_16\t2\t\t/* Direct 16 bit  */\n#define R_68K_8\t\t3\t\t/* Direct 8 bit  */\n#define R_68K_PC32\t4\t\t/* PC relative 32 bit */\n#define R_68K_PC16\t5\t\t/* PC relative 16 bit */\n#define R_68K_PC8\t6\t\t/* PC relative 8 bit */\n#define R_68K_GOT32\t7\t\t/* 32 bit PC relative GOT entry */\n#define R_68K_GOT16\t8\t\t/* 16 bit PC relative GOT entry */\n#define R_68K_GOT8\t9\t\t/* 8 bit PC relative GOT entry */\n#define R_68K_GOT32O\t10\t\t/* 32 bit GOT offset */\n#define R_68K_GOT16O\t11\t\t/* 16 bit GOT offset */\n#define R_68K_GOT8O\t12\t\t/* 8 bit GOT offset */\n#define R_68K_PLT32\t13\t\t/* 32 bit PC relative PLT address */\n#define R_68K_PLT16\t14\t\t/* 16 bit PC relative PLT address */\n#define R_68K_PLT8\t15\t\t/* 8 bit PC relative PLT address */\n#define R_68K_PLT32O\t16\t\t/* 32 bit PLT offset */\n#define R_68K_PLT16O\t17\t\t/* 16 bit PLT offset */\n#define R_68K_PLT8O\t18\t\t/* 8 bit PLT offset */\n#define R_68K_COPY\t19\t\t/* Copy symbol at runtime */\n#define R_68K_GLOB_DAT\t20\t\t/* Create GOT entry */\n#define R_68K_JMP_SLOT\t21\t\t/* Create PLT entry */\n#define R_68K_RELATIVE\t22\t\t/* Adjust by program base */\n/* Keep this the last entry.  */\n#define R_68K_NUM\t23\n\n/* Intel 80386 specific definitions.  */\n\n/* i386 relocs.  */\n\n#define R_386_NONE\t   0\t\t/* No reloc */\n#define R_386_32\t   1\t\t/* Direct 32 bit  */\n#define R_386_PC32\t   2\t\t/* PC relative 32 bit */\n#define R_386_GOT32\t   3\t\t/* 32 bit GOT entry */\n#define R_386_PLT32\t   4\t\t/* 32 bit PLT address */\n#define R_386_COPY\t   5\t\t/* Copy symbol at runtime */\n#define R_386_GLOB_DAT\t   6\t\t/* Create GOT entry */\n#define R_386_JMP_SLOT\t   7\t\t/* Create PLT entry */\n#define R_386_RELATIVE\t   8\t\t/* Adjust by program base */\n#define R_386_GOTOFF\t   9\t\t/* 32 bit offset to GOT */\n#define R_386_GOTPC\t   10\t\t/* 32 bit PC relative offset to GOT */\n#define R_386_32PLT\t   11\n#define R_386_TLS_TPOFF\t   14\t\t/* Offset in static TLS block */\n#define R_386_TLS_IE\t   15\t\t/* Address of GOT entry for static TLS\n\t\t\t\t\t   block offset */\n#define R_386_TLS_GOTIE\t   16\t\t/* GOT entry for static TLS block\n\t\t\t\t\t   offset */\n#define R_386_TLS_LE\t   17\t\t/* Offset relative to static TLS\n\t\t\t\t\t   block */\n#define R_386_TLS_GD\t   18\t\t/* Direct 32 bit for GNU version of\n\t\t\t\t\t   general dynamic thread local data */\n#define R_386_TLS_LDM\t   19\t\t/* Direct 32 bit for GNU version of\n\t\t\t\t\t   local dynamic thread local data\n\t\t\t\t\t   in LE code */\n#define R_386_16\t   20\n#define R_386_PC16\t   21\n#define R_386_8\t\t   22\n#define R_386_PC8\t   23\n#define R_386_TLS_GD_32\t   24\t\t/* Direct 32 bit for general dynamic\n\t\t\t\t\t   thread local data */\n#define R_386_TLS_GD_PUSH  25\t\t/* Tag for pushl in GD TLS code */\n#define R_386_TLS_GD_CALL  26\t\t/* Relocation for call to\n\t\t\t\t\t   __tls_get_addr() */\n#define R_386_TLS_GD_POP   27\t\t/* Tag for popl in GD TLS code */\n#define R_386_TLS_LDM_32   28\t\t/* Direct 32 bit for local dynamic\n\t\t\t\t\t   thread local data in LE code */\n#define R_386_TLS_LDM_PUSH 29\t\t/* Tag for pushl in LDM TLS code */\n#define R_386_TLS_LDM_CALL 30\t\t/* Relocation for call to\n\t\t\t\t\t   __tls_get_addr() in LDM code */\n#define R_386_TLS_LDM_POP  31\t\t/* Tag for popl in LDM TLS code */\n#define R_386_TLS_LDO_32   32\t\t/* Offset relative to TLS block */\n#define R_386_TLS_IE_32\t   33\t\t/* GOT entry for negated static TLS\n\t\t\t\t\t   block offset */\n#define R_386_TLS_LE_32\t   34\t\t/* Negated offset relative to static\n\t\t\t\t\t   TLS block */\n#define R_386_TLS_DTPMOD32 35\t\t/* ID of module containing symbol */\n#define R_386_TLS_DTPOFF32 36\t\t/* Offset in TLS block */\n#define R_386_TLS_TPOFF32  37\t\t/* Negated offset in static TLS block */\n/* Keep this the last entry.  */\n#define R_386_NUM\t   38\n\n/* SUN SPARC specific definitions.  */\n\n/* Legal values for ST_TYPE subfield of st_info (symbol type).  */\n\n#define STT_SPARC_REGISTER\t13\t/* Global register reserved to app. */\n\n/* Values for Elf64_Ehdr.e_flags.  */\n\n#define EF_SPARCV9_MM\t\t3\n#define EF_SPARCV9_TSO\t\t0\n#define EF_SPARCV9_PSO\t\t1\n#define EF_SPARCV9_RMO\t\t2\n#define EF_SPARC_LEDATA\t\t0x800000 /* little endian data */\n#define EF_SPARC_EXT_MASK\t0xFFFF00\n#define EF_SPARC_32PLUS\t\t0x000100 /* generic V8+ features */\n#define EF_SPARC_SUN_US1\t0x000200 /* Sun UltraSPARC1 extensions */\n#define EF_SPARC_HAL_R1\t\t0x000400 /* HAL R1 extensions */\n#define EF_SPARC_SUN_US3\t0x000800 /* Sun UltraSPARCIII extensions */\n\n/* SPARC relocs.  */\n\n#define R_SPARC_NONE\t\t0\t/* No reloc */\n#define R_SPARC_8\t\t1\t/* Direct 8 bit */\n#define R_SPARC_16\t\t2\t/* Direct 16 bit */\n#define R_SPARC_32\t\t3\t/* Direct 32 bit */\n#define R_SPARC_DISP8\t\t4\t/* PC relative 8 bit */\n#define R_SPARC_DISP16\t\t5\t/* PC relative 16 bit */\n#define R_SPARC_DISP32\t\t6\t/* PC relative 32 bit */\n#define R_SPARC_WDISP30\t\t7\t/* PC relative 30 bit shifted */\n#define R_SPARC_WDISP22\t\t8\t/* PC relative 22 bit shifted */\n#define R_SPARC_HI22\t\t9\t/* High 22 bit */\n#define R_SPARC_22\t\t10\t/* Direct 22 bit */\n#define R_SPARC_13\t\t11\t/* Direct 13 bit */\n#define R_SPARC_LO10\t\t12\t/* Truncated 10 bit */\n#define R_SPARC_GOT10\t\t13\t/* Truncated 10 bit GOT entry */\n#define R_SPARC_GOT13\t\t14\t/* 13 bit GOT entry */\n#define R_SPARC_GOT22\t\t15\t/* 22 bit GOT entry shifted */\n#define R_SPARC_PC10\t\t16\t/* PC relative 10 bit truncated */\n#define R_SPARC_PC22\t\t17\t/* PC relative 22 bit shifted */\n#define R_SPARC_WPLT30\t\t18\t/* 30 bit PC relative PLT address */\n#define R_SPARC_COPY\t\t19\t/* Copy symbol at runtime */\n#define R_SPARC_GLOB_DAT\t20\t/* Create GOT entry */\n#define R_SPARC_JMP_SLOT\t21\t/* Create PLT entry */\n#define R_SPARC_RELATIVE\t22\t/* Adjust by program base */\n#define R_SPARC_UA32\t\t23\t/* Direct 32 bit unaligned */\n\n/* Additional Sparc64 relocs.  */\n\n#define R_SPARC_PLT32\t\t24\t/* Direct 32 bit ref to PLT entry */\n#define R_SPARC_HIPLT22\t\t25\t/* High 22 bit PLT entry */\n#define R_SPARC_LOPLT10\t\t26\t/* Truncated 10 bit PLT entry */\n#define R_SPARC_PCPLT32\t\t27\t/* PC rel 32 bit ref to PLT entry */\n#define R_SPARC_PCPLT22\t\t28\t/* PC rel high 22 bit PLT entry */\n#define R_SPARC_PCPLT10\t\t29\t/* PC rel trunc 10 bit PLT entry */\n#define R_SPARC_10\t\t30\t/* Direct 10 bit */\n#define R_SPARC_11\t\t31\t/* Direct 11 bit */\n#define R_SPARC_64\t\t32\t/* Direct 64 bit */\n#define R_SPARC_OLO10\t\t33\t/* 10bit with secondary 13bit addend */\n#define R_SPARC_HH22\t\t34\t/* Top 22 bits of direct 64 bit */\n#define R_SPARC_HM10\t\t35\t/* High middle 10 bits of ... */\n#define R_SPARC_LM22\t\t36\t/* Low middle 22 bits of ... */\n#define R_SPARC_PC_HH22\t\t37\t/* Top 22 bits of pc rel 64 bit */\n#define R_SPARC_PC_HM10\t\t38\t/* High middle 10 bit of ... */\n#define R_SPARC_PC_LM22\t\t39\t/* Low miggle 22 bits of ... */\n#define R_SPARC_WDISP16\t\t40\t/* PC relative 16 bit shifted */\n#define R_SPARC_WDISP19\t\t41\t/* PC relative 19 bit shifted */\n#define R_SPARC_7\t\t43\t/* Direct 7 bit */\n#define R_SPARC_5\t\t44\t/* Direct 5 bit */\n#define R_SPARC_6\t\t45\t/* Direct 6 bit */\n#define R_SPARC_DISP64\t\t46\t/* PC relative 64 bit */\n#define R_SPARC_PLT64\t\t47\t/* Direct 64 bit ref to PLT entry */\n#define R_SPARC_HIX22\t\t48\t/* High 22 bit complemented */\n#define R_SPARC_LOX10\t\t49\t/* Truncated 11 bit complemented */\n#define R_SPARC_H44\t\t50\t/* Direct high 12 of 44 bit */\n#define R_SPARC_M44\t\t51\t/* Direct mid 22 of 44 bit */\n#define R_SPARC_L44\t\t52\t/* Direct low 10 of 44 bit */\n#define R_SPARC_REGISTER\t53\t/* Global register usage */\n#define R_SPARC_UA64\t\t54\t/* Direct 64 bit unaligned */\n#define R_SPARC_UA16\t\t55\t/* Direct 16 bit unaligned */\n#define R_SPARC_TLS_GD_HI22\t56\n#define R_SPARC_TLS_GD_LO10\t57\n#define R_SPARC_TLS_GD_ADD\t58\n#define R_SPARC_TLS_GD_CALL\t59\n#define R_SPARC_TLS_LDM_HI22\t60\n#define R_SPARC_TLS_LDM_LO10\t61\n#define R_SPARC_TLS_LDM_ADD\t62\n#define R_SPARC_TLS_LDM_CALL\t63\n#define R_SPARC_TLS_LDO_HIX22\t64\n#define R_SPARC_TLS_LDO_LOX10\t65\n#define R_SPARC_TLS_LDO_ADD\t66\n#define R_SPARC_TLS_IE_HI22\t67\n#define R_SPARC_TLS_IE_LO10\t68\n#define R_SPARC_TLS_IE_LD\t69\n#define R_SPARC_TLS_IE_LDX\t70\n#define R_SPARC_TLS_IE_ADD\t71\n#define R_SPARC_TLS_LE_HIX22\t72\n#define R_SPARC_TLS_LE_LOX10\t73\n#define R_SPARC_TLS_DTPMOD32\t74\n#define R_SPARC_TLS_DTPMOD64\t75\n#define R_SPARC_TLS_DTPOFF32\t76\n#define R_SPARC_TLS_DTPOFF64\t77\n#define R_SPARC_TLS_TPOFF32\t78\n#define R_SPARC_TLS_TPOFF64\t79\n/* Keep this the last entry.  */\n#define R_SPARC_NUM\t\t80\n\n/* For Sparc64, legal values for d_tag of Elf64_Dyn.  */\n\n#define DT_SPARC_REGISTER 0x70000001\n#define DT_SPARC_NUM\t2\n\n/* Bits present in AT_HWCAP, primarily for Sparc32.  */\n\n#define HWCAP_SPARC_FLUSH\t1\t/* The cpu supports flush insn.  */\n#define HWCAP_SPARC_STBAR\t2\n#define HWCAP_SPARC_SWAP\t4\n#define HWCAP_SPARC_MULDIV\t8\n#define HWCAP_SPARC_V9\t\t16\t/* The cpu is v9, so v8plus is ok.  */\n#define HWCAP_SPARC_ULTRA3\t32\n\n/* MIPS R3000 specific definitions.  */\n\n/* Legal values for e_flags field of Elf32_Ehdr.  */\n\n#define EF_MIPS_NOREORDER   1\t\t/* A .noreorder directive was used */\n#define EF_MIPS_PIC\t    2\t\t/* Contains PIC code */\n#define EF_MIPS_CPIC\t    4\t\t/* Uses PIC calling sequence */\n#define EF_MIPS_XGOT\t    8\n#define EF_MIPS_64BIT_WHIRL 16\n#define EF_MIPS_ABI2\t    32\n#define EF_MIPS_ABI_ON32    64\n#define EF_MIPS_ARCH\t    0xf0000000\t/* MIPS architecture level */\n\n/* Legal values for MIPS architecture level.  */\n\n#define EF_MIPS_ARCH_1\t    0x00000000\t/* -mips1 code.  */\n#define EF_MIPS_ARCH_2\t    0x10000000\t/* -mips2 code.  */\n#define EF_MIPS_ARCH_3\t    0x20000000\t/* -mips3 code.  */\n#define EF_MIPS_ARCH_4\t    0x30000000\t/* -mips4 code.  */\n#define EF_MIPS_ARCH_5\t    0x40000000\t/* -mips5 code.  */\n#define EF_MIPS_ARCH_32\t    0x60000000\t/* MIPS32 code.  */\n#define EF_MIPS_ARCH_64\t    0x70000000\t/* MIPS64 code.  */\n\n/* The following are non-official names and should not be used.  */\n\n#define E_MIPS_ARCH_1\t  0x00000000\t/* -mips1 code.  */\n#define E_MIPS_ARCH_2\t  0x10000000\t/* -mips2 code.  */\n#define E_MIPS_ARCH_3\t  0x20000000\t/* -mips3 code.  */\n#define E_MIPS_ARCH_4\t  0x30000000\t/* -mips4 code.  */\n#define E_MIPS_ARCH_5\t  0x40000000\t/* -mips5 code.  */\n#define E_MIPS_ARCH_32\t  0x60000000\t/* MIPS32 code.  */\n#define E_MIPS_ARCH_64\t  0x70000000\t/* MIPS64 code.  */\n\n/* Special section indices.  */\n\n#define SHN_MIPS_ACOMMON    0xff00\t/* Allocated common symbols */\n#define SHN_MIPS_TEXT\t    0xff01\t/* Allocated test symbols.  */\n#define SHN_MIPS_DATA\t    0xff02\t/* Allocated data symbols.  */\n#define SHN_MIPS_SCOMMON    0xff03\t/* Small common symbols */\n#define SHN_MIPS_SUNDEFINED 0xff04\t/* Small undefined symbols */\n\n/* Legal values for sh_type field of Elf32_Shdr.  */\n\n#define SHT_MIPS_LIBLIST       0x70000000 /* Shared objects used in link */\n#define SHT_MIPS_MSYM\t       0x70000001\n#define SHT_MIPS_CONFLICT      0x70000002 /* Conflicting symbols */\n#define SHT_MIPS_GPTAB\t       0x70000003 /* Global data area sizes */\n#define SHT_MIPS_UCODE\t       0x70000004 /* Reserved for SGI/MIPS compilers */\n#define SHT_MIPS_DEBUG\t       0x70000005 /* MIPS ECOFF debugging information*/\n#define SHT_MIPS_REGINFO       0x70000006 /* Register usage information */\n#define SHT_MIPS_PACKAGE       0x70000007\n#define SHT_MIPS_PACKSYM       0x70000008\n#define SHT_MIPS_RELD\t       0x70000009\n#define SHT_MIPS_IFACE         0x7000000b\n#define SHT_MIPS_CONTENT       0x7000000c\n#define SHT_MIPS_OPTIONS       0x7000000d /* Miscellaneous options.  */\n#define SHT_MIPS_SHDR\t       0x70000010\n#define SHT_MIPS_FDESC\t       0x70000011\n#define SHT_MIPS_EXTSYM\t       0x70000012\n#define SHT_MIPS_DENSE\t       0x70000013\n#define SHT_MIPS_PDESC\t       0x70000014\n#define SHT_MIPS_LOCSYM\t       0x70000015\n#define SHT_MIPS_AUXSYM\t       0x70000016\n#define SHT_MIPS_OPTSYM\t       0x70000017\n#define SHT_MIPS_LOCSTR\t       0x70000018\n#define SHT_MIPS_LINE\t       0x70000019\n#define SHT_MIPS_RFDESC\t       0x7000001a\n#define SHT_MIPS_DELTASYM      0x7000001b\n#define SHT_MIPS_DELTAINST     0x7000001c\n#define SHT_MIPS_DELTACLASS    0x7000001d\n#define SHT_MIPS_DWARF         0x7000001e /* DWARF debugging information.  */\n#define SHT_MIPS_DELTADECL     0x7000001f\n#define SHT_MIPS_SYMBOL_LIB    0x70000020\n#define SHT_MIPS_EVENTS\t       0x70000021 /* Event section.  */\n#define SHT_MIPS_TRANSLATE     0x70000022\n#define SHT_MIPS_PIXIE\t       0x70000023\n#define SHT_MIPS_XLATE\t       0x70000024\n#define SHT_MIPS_XLATE_DEBUG   0x70000025\n#define SHT_MIPS_WHIRL\t       0x70000026\n#define SHT_MIPS_EH_REGION     0x70000027\n#define SHT_MIPS_XLATE_OLD     0x70000028\n#define SHT_MIPS_PDR_EXCEPTION 0x70000029\n\n/* Legal values for sh_flags field of Elf32_Shdr.  */\n\n#define SHF_MIPS_GPREL\t 0x10000000\t/* Must be part of global data area */\n#define SHF_MIPS_MERGE\t 0x20000000\n#define SHF_MIPS_ADDR\t 0x40000000\n#define SHF_MIPS_STRINGS 0x80000000\n#define SHF_MIPS_NOSTRIP 0x08000000\n#define SHF_MIPS_LOCAL\t 0x04000000\n#define SHF_MIPS_NAMES\t 0x02000000\n#define SHF_MIPS_NODUPE\t 0x01000000\n\n\n/* Symbol tables.  */\n\n/* MIPS specific values for `st_other'.  */\n#define STO_MIPS_DEFAULT\t\t0x0\n#define STO_MIPS_INTERNAL\t\t0x1\n#define STO_MIPS_HIDDEN\t\t\t0x2\n#define STO_MIPS_PROTECTED\t\t0x3\n#define STO_MIPS_SC_ALIGN_UNUSED\t0xff\n\n/* MIPS specific values for `st_info'.  */\n#define STB_MIPS_SPLIT_COMMON\t\t13\n\n/* Entries found in sections of type SHT_MIPS_GPTAB.  */\n\ntypedef union\n{\n  struct\n    {\n      Elf32_Word gt_current_g_value;\t/* -G value used for compilation */\n      Elf32_Word gt_unused;\t\t/* Not used */\n    } gt_header;\t\t\t/* First entry in section */\n  struct\n    {\n      Elf32_Word gt_g_value;\t\t/* If this value were used for -G */\n      Elf32_Word gt_bytes;\t\t/* This many bytes would be used */\n    } gt_entry;\t\t\t\t/* Subsequent entries in section */\n} Elf32_gptab;\n\n/* Entry found in sections of type SHT_MIPS_REGINFO.  */\n\ntypedef struct\n{\n  Elf32_Word\tri_gprmask;\t\t/* General registers used */\n  Elf32_Word\tri_cprmask[4];\t\t/* Coprocessor registers used */\n  Elf32_Sword\tri_gp_value;\t\t/* $gp register value */\n} Elf32_RegInfo;\n\n/* Entries found in sections of type SHT_MIPS_OPTIONS.  */\n\ntypedef struct\n{\n  unsigned char kind;\t\t/* Determines interpretation of the\n\t\t\t\t   variable part of descriptor.  */\n  unsigned char size;\t\t/* Size of descriptor, including header.  */\n  Elf32_Section section;\t/* Section header index of section affected,\n\t\t\t\t   0 for global options.  */\n  Elf32_Word info;\t\t/* Kind-specific information.  */\n} Elf_Options;\n\n/* Values for `kind' field in Elf_Options.  */\n\n#define ODK_NULL\t0\t/* Undefined.  */\n#define ODK_REGINFO\t1\t/* Register usage information.  */\n#define ODK_EXCEPTIONS\t2\t/* Exception processing options.  */\n#define ODK_PAD\t\t3\t/* Section padding options.  */\n#define ODK_HWPATCH\t4\t/* Hardware workarounds performed */\n#define ODK_FILL\t5\t/* record the fill value used by the linker. */\n#define ODK_TAGS\t6\t/* reserve space for desktop tools to write. */\n#define ODK_HWAND\t7\t/* HW workarounds.  'AND' bits when merging. */\n#define ODK_HWOR\t8\t/* HW workarounds.  'OR' bits when merging.  */\n\n/* Values for `info' in Elf_Options for ODK_EXCEPTIONS entries.  */\n\n#define OEX_FPU_MIN\t0x1f\t/* FPE's which MUST be enabled.  */\n#define OEX_FPU_MAX\t0x1f00\t/* FPE's which MAY be enabled.  */\n#define OEX_PAGE0\t0x10000\t/* page zero must be mapped.  */\n#define OEX_SMM\t\t0x20000\t/* Force sequential memory mode?  */\n#define OEX_FPDBUG\t0x40000\t/* Force floating point debug mode?  */\n#define OEX_PRECISEFP\tOEX_FPDBUG\n#define OEX_DISMISS\t0x80000\t/* Dismiss invalid address faults?  */\n\n#define OEX_FPU_INVAL\t0x10\n#define OEX_FPU_DIV0\t0x08\n#define OEX_FPU_OFLO\t0x04\n#define OEX_FPU_UFLO\t0x02\n#define OEX_FPU_INEX\t0x01\n\n/* Masks for `info' in Elf_Options for an ODK_HWPATCH entry.  */\n\n#define OHW_R4KEOP\t0x1\t/* R4000 end-of-page patch.  */\n#define OHW_R8KPFETCH\t0x2\t/* may need R8000 prefetch patch.  */\n#define OHW_R5KEOP\t0x4\t/* R5000 end-of-page patch.  */\n#define OHW_R5KCVTL\t0x8\t/* R5000 cvt.[ds].l bug.  clean=1.  */\n\n#define OPAD_PREFIX\t0x1\n#define OPAD_POSTFIX\t0x2\n#define OPAD_SYMBOL\t0x4\n\n/* Entry found in `.options' section.  */\n\ntypedef struct\n{\n  Elf32_Word hwp_flags1;\t/* Extra flags.  */\n  Elf32_Word hwp_flags2;\t/* Extra flags.  */\n} Elf_Options_Hw;\n\n/* Masks for `info' in ElfOptions for ODK_HWAND and ODK_HWOR entries.  */\n\n#define OHWA0_R4KEOP_CHECKED\t0x00000001\n#define OHWA1_R4KEOP_CLEAN\t0x00000002\n\n/* MIPS relocs.  */\n\n#define R_MIPS_NONE\t\t0\t/* No reloc */\n#define R_MIPS_16\t\t1\t/* Direct 16 bit */\n#define R_MIPS_32\t\t2\t/* Direct 32 bit */\n#define R_MIPS_REL32\t\t3\t/* PC relative 32 bit */\n#define R_MIPS_26\t\t4\t/* Direct 26 bit shifted */\n#define R_MIPS_HI16\t\t5\t/* High 16 bit */\n#define R_MIPS_LO16\t\t6\t/* Low 16 bit */\n#define R_MIPS_GPREL16\t\t7\t/* GP relative 16 bit */\n#define R_MIPS_LITERAL\t\t8\t/* 16 bit literal entry */\n#define R_MIPS_GOT16\t\t9\t/* 16 bit GOT entry */\n#define R_MIPS_PC16\t\t10\t/* PC relative 16 bit */\n#define R_MIPS_CALL16\t\t11\t/* 16 bit GOT entry for function */\n#define R_MIPS_GPREL32\t\t12\t/* GP relative 32 bit */\n\n#define R_MIPS_SHIFT5\t\t16\n#define R_MIPS_SHIFT6\t\t17\n#define R_MIPS_64\t\t18\n#define R_MIPS_GOT_DISP\t\t19\n#define R_MIPS_GOT_PAGE\t\t20\n#define R_MIPS_GOT_OFST\t\t21\n#define R_MIPS_GOT_HI16\t\t22\n#define R_MIPS_GOT_LO16\t\t23\n#define R_MIPS_SUB\t\t24\n#define R_MIPS_INSERT_A\t\t25\n#define R_MIPS_INSERT_B\t\t26\n#define R_MIPS_DELETE\t\t27\n#define R_MIPS_HIGHER\t\t28\n#define R_MIPS_HIGHEST\t\t29\n#define R_MIPS_CALL_HI16\t30\n#define R_MIPS_CALL_LO16\t31\n#define R_MIPS_SCN_DISP\t\t32\n#define R_MIPS_REL16\t\t33\n#define R_MIPS_ADD_IMMEDIATE\t34\n#define R_MIPS_PJUMP\t\t35\n#define R_MIPS_RELGOT\t\t36\n#define R_MIPS_JALR\t\t37\n/* Keep this the last entry.  */\n#define R_MIPS_NUM\t\t38\n\n/* Legal values for p_type field of Elf32_Phdr.  */\n\n#define PT_MIPS_REGINFO\t0x70000000\t/* Register usage information */\n#define PT_MIPS_RTPROC  0x70000001\t/* Runtime procedure table. */\n#define PT_MIPS_OPTIONS 0x70000002\n\n/* Special program header types.  */\n\n#define PF_MIPS_LOCAL\t0x10000000\n\n/* Legal values for d_tag field of Elf32_Dyn.  */\n\n#define DT_MIPS_RLD_VERSION  0x70000001\t/* Runtime linker interface version */\n#define DT_MIPS_TIME_STAMP   0x70000002\t/* Timestamp */\n#define DT_MIPS_ICHECKSUM    0x70000003\t/* Checksum */\n#define DT_MIPS_IVERSION     0x70000004\t/* Version string (string tbl index) */\n#define DT_MIPS_FLAGS\t     0x70000005\t/* Flags */\n#define DT_MIPS_BASE_ADDRESS 0x70000006\t/* Base address */\n#define DT_MIPS_MSYM\t     0x70000007\n#define DT_MIPS_CONFLICT     0x70000008\t/* Address of CONFLICT section */\n#define DT_MIPS_LIBLIST\t     0x70000009\t/* Address of LIBLIST section */\n#define DT_MIPS_LOCAL_GOTNO  0x7000000a\t/* Number of local GOT entries */\n#define DT_MIPS_CONFLICTNO   0x7000000b\t/* Number of CONFLICT entries */\n#define DT_MIPS_LIBLISTNO    0x70000010\t/* Number of LIBLIST entries */\n#define DT_MIPS_SYMTABNO     0x70000011\t/* Number of DYNSYM entries */\n#define DT_MIPS_UNREFEXTNO   0x70000012\t/* First external DYNSYM */\n#define DT_MIPS_GOTSYM\t     0x70000013\t/* First GOT entry in DYNSYM */\n#define DT_MIPS_HIPAGENO     0x70000014\t/* Number of GOT page table entries */\n#define DT_MIPS_RLD_MAP\t     0x70000016\t/* Address of run time loader map.  */\n#define DT_MIPS_DELTA_CLASS  0x70000017\t/* Delta C++ class definition.  */\n#define DT_MIPS_DELTA_CLASS_NO    0x70000018 /* Number of entries in\n\t\t\t\t\t\tDT_MIPS_DELTA_CLASS.  */\n#define DT_MIPS_DELTA_INSTANCE    0x70000019 /* Delta C++ class instances.  */\n#define DT_MIPS_DELTA_INSTANCE_NO 0x7000001a /* Number of entries in\n\t\t\t\t\t\tDT_MIPS_DELTA_INSTANCE.  */\n#define DT_MIPS_DELTA_RELOC  0x7000001b /* Delta relocations.  */\n#define DT_MIPS_DELTA_RELOC_NO 0x7000001c /* Number of entries in\n\t\t\t\t\t     DT_MIPS_DELTA_RELOC.  */\n#define DT_MIPS_DELTA_SYM    0x7000001d /* Delta symbols that Delta\n\t\t\t\t\t   relocations refer to.  */\n#define DT_MIPS_DELTA_SYM_NO 0x7000001e /* Number of entries in\n\t\t\t\t\t   DT_MIPS_DELTA_SYM.  */\n#define DT_MIPS_DELTA_CLASSSYM 0x70000020 /* Delta symbols that hold the\n\t\t\t\t\t     class declaration.  */\n#define DT_MIPS_DELTA_CLASSSYM_NO 0x70000021 /* Number of entries in\n\t\t\t\t\t\tDT_MIPS_DELTA_CLASSSYM.  */\n#define DT_MIPS_CXX_FLAGS    0x70000022 /* Flags indicating for C++ flavor.  */\n#define DT_MIPS_PIXIE_INIT   0x70000023\n#define DT_MIPS_SYMBOL_LIB   0x70000024\n#define DT_MIPS_LOCALPAGE_GOTIDX 0x70000025\n#define DT_MIPS_LOCAL_GOTIDX 0x70000026\n#define DT_MIPS_HIDDEN_GOTIDX 0x70000027\n#define DT_MIPS_PROTECTED_GOTIDX 0x70000028\n#define DT_MIPS_OPTIONS\t     0x70000029 /* Address of .options.  */\n#define DT_MIPS_INTERFACE    0x7000002a /* Address of .interface.  */\n#define DT_MIPS_DYNSTR_ALIGN 0x7000002b\n#define DT_MIPS_INTERFACE_SIZE 0x7000002c /* Size of the .interface section. */\n#define DT_MIPS_RLD_TEXT_RESOLVE_ADDR 0x7000002d /* Address of rld_text_rsolve\n\t\t\t\t\t\t    function stored in GOT.  */\n#define DT_MIPS_PERF_SUFFIX  0x7000002e /* Default suffix of dso to be added\n\t\t\t\t\t   by rld on dlopen() calls.  */\n#define DT_MIPS_COMPACT_SIZE 0x7000002f /* (O32)Size of compact rel section. */\n#define DT_MIPS_GP_VALUE     0x70000030 /* GP value for aux GOTs.  */\n#define DT_MIPS_AUX_DYNAMIC  0x70000031 /* Address of aux .dynamic.  */\n#define DT_MIPS_NUM\t     0x32\n\n/* Legal values for DT_MIPS_FLAGS Elf32_Dyn entry.  */\n\n#define RHF_NONE\t\t   0\t\t/* No flags */\n#define RHF_QUICKSTART\t\t   (1 << 0)\t/* Use quickstart */\n#define RHF_NOTPOT\t\t   (1 << 1)\t/* Hash size not power of 2 */\n#define RHF_NO_LIBRARY_REPLACEMENT (1 << 2)\t/* Ignore LD_LIBRARY_PATH */\n#define RHF_NO_MOVE\t\t   (1 << 3)\n#define RHF_SGI_ONLY\t\t   (1 << 4)\n#define RHF_GUARANTEE_INIT\t   (1 << 5)\n#define RHF_DELTA_C_PLUS_PLUS\t   (1 << 6)\n#define RHF_GUARANTEE_START_INIT   (1 << 7)\n#define RHF_PIXIE\t\t   (1 << 8)\n#define RHF_DEFAULT_DELAY_LOAD\t   (1 << 9)\n#define RHF_REQUICKSTART\t   (1 << 10)\n#define RHF_REQUICKSTARTED\t   (1 << 11)\n#define RHF_CORD\t\t   (1 << 12)\n#define RHF_NO_UNRES_UNDEF\t   (1 << 13)\n#define RHF_RLD_ORDER_SAFE\t   (1 << 14)\n\n/* Entries found in sections of type SHT_MIPS_LIBLIST.  */\n\ntypedef struct\n{\n  Elf32_Word l_name;\t\t/* Name (string table index) */\n  Elf32_Word l_time_stamp;\t/* Timestamp */\n  Elf32_Word l_checksum;\t/* Checksum */\n  Elf32_Word l_version;\t\t/* Interface version */\n  Elf32_Word l_flags;\t\t/* Flags */\n} Elf32_Lib;\n\ntypedef struct\n{\n  Elf64_Word l_name;\t\t/* Name (string table index) */\n  Elf64_Word l_time_stamp;\t/* Timestamp */\n  Elf64_Word l_checksum;\t/* Checksum */\n  Elf64_Word l_version;\t\t/* Interface version */\n  Elf64_Word l_flags;\t\t/* Flags */\n} Elf64_Lib;\n\n\n/* Legal values for l_flags.  */\n\n#define LL_NONE\t\t  0\n#define LL_EXACT_MATCH\t  (1 << 0)\t/* Require exact match */\n#define LL_IGNORE_INT_VER (1 << 1)\t/* Ignore interface version */\n#define LL_REQUIRE_MINOR  (1 << 2)\n#define LL_EXPORTS\t  (1 << 3)\n#define LL_DELAY_LOAD\t  (1 << 4)\n#define LL_DELTA\t  (1 << 5)\n\n/* Entries found in sections of type SHT_MIPS_CONFLICT.  */\n\ntypedef Elf32_Addr Elf32_Conflict;\n\n\n/* HPPA specific definitions.  */\n\n/* Legal values for e_flags field of Elf32_Ehdr.  */\n\n#define EF_PARISC_TRAPNIL\t0x00010000 /* Trap nil pointer dereference.  */\n#define EF_PARISC_EXT\t\t0x00020000 /* Program uses arch. extensions. */\n#define EF_PARISC_LSB\t\t0x00040000 /* Program expects little endian. */\n#define EF_PARISC_WIDE\t\t0x00080000 /* Program expects wide mode.  */\n#define EF_PARISC_NO_KABP\t0x00100000 /* No kernel assisted branch\n\t\t\t\t\t      prediction.  */\n#define EF_PARISC_LAZYSWAP\t0x00400000 /* Allow lazy swapping.  */\n#define EF_PARISC_ARCH\t\t0x0000ffff /* Architecture version.  */\n\n/* Defined values for `e_flags & EF_PARISC_ARCH' are:  */\n\n#define EFA_PARISC_1_0\t\t    0x020b /* PA-RISC 1.0 big-endian.  */\n#define EFA_PARISC_1_1\t\t    0x0210 /* PA-RISC 1.1 big-endian.  */\n#define EFA_PARISC_2_0\t\t    0x0214 /* PA-RISC 2.0 big-endian.  */\n\n/* Additional section indeces.  */\n\n#define SHN_PARISC_ANSI_COMMON\t0xff00\t   /* Section for tenatively declared\n\t\t\t\t\t      symbols in ANSI C.  */\n#define SHN_PARISC_HUGE_COMMON\t0xff01\t   /* Common blocks in huge model.  */\n\n/* Legal values for sh_type field of Elf32_Shdr.  */\n\n#define SHT_PARISC_EXT\t\t0x70000000 /* Contains product specific ext. */\n#define SHT_PARISC_UNWIND\t0x70000001 /* Unwind information.  */\n#define SHT_PARISC_DOC\t\t0x70000002 /* Debug info for optimized code. */\n\n/* Legal values for sh_flags field of Elf32_Shdr.  */\n\n#define SHF_PARISC_SHORT\t0x20000000 /* Section with short addressing. */\n#define SHF_PARISC_HUGE\t\t0x40000000 /* Section far from gp.  */\n#define SHF_PARISC_SBP\t\t0x80000000 /* Static branch prediction code. */\n\n/* Legal values for ST_TYPE subfield of st_info (symbol type).  */\n\n#define STT_PARISC_MILLICODE\t13\t/* Millicode function entry point.  */\n\n#define STT_HP_OPAQUE\t\t(STT_LOOS + 0x1)\n#define STT_HP_STUB\t\t(STT_LOOS + 0x2)\n\n/* HPPA relocs.  */\n\n#define R_PARISC_NONE\t\t0\t/* No reloc.  */\n#define R_PARISC_DIR32\t\t1\t/* Direct 32-bit reference.  */\n#define R_PARISC_DIR21L\t\t2\t/* Left 21 bits of eff. address.  */\n#define R_PARISC_DIR17R\t\t3\t/* Right 17 bits of eff. address.  */\n#define R_PARISC_DIR17F\t\t4\t/* 17 bits of eff. address.  */\n#define R_PARISC_DIR14R\t\t6\t/* Right 14 bits of eff. address.  */\n#define R_PARISC_PCREL32\t9\t/* 32-bit rel. address.  */\n#define R_PARISC_PCREL21L\t10\t/* Left 21 bits of rel. address.  */\n#define R_PARISC_PCREL17R\t11\t/* Right 17 bits of rel. address.  */\n#define R_PARISC_PCREL17F\t12\t/* 17 bits of rel. address.  */\n#define R_PARISC_PCREL14R\t14\t/* Right 14 bits of rel. address.  */\n#define R_PARISC_DPREL21L\t18\t/* Left 21 bits of rel. address.  */\n#define R_PARISC_DPREL14R\t22\t/* Right 14 bits of rel. address.  */\n#define R_PARISC_GPREL21L\t26\t/* GP-relative, left 21 bits.  */\n#define R_PARISC_GPREL14R\t30\t/* GP-relative, right 14 bits.  */\n#define R_PARISC_LTOFF21L\t34\t/* LT-relative, left 21 bits.  */\n#define R_PARISC_LTOFF14R\t38\t/* LT-relative, right 14 bits.  */\n#define R_PARISC_SECREL32\t41\t/* 32 bits section rel. address.  */\n#define R_PARISC_SEGBASE\t48\t/* No relocation, set segment base.  */\n#define R_PARISC_SEGREL32\t49\t/* 32 bits segment rel. address.  */\n#define R_PARISC_PLTOFF21L\t50\t/* PLT rel. address, left 21 bits.  */\n#define R_PARISC_PLTOFF14R\t54\t/* PLT rel. address, right 14 bits.  */\n#define R_PARISC_LTOFF_FPTR32\t57\t/* 32 bits LT-rel. function pointer. */\n#define R_PARISC_LTOFF_FPTR21L\t58\t/* LT-rel. fct ptr, left 21 bits. */\n#define R_PARISC_LTOFF_FPTR14R\t62\t/* LT-rel. fct ptr, right 14 bits. */\n#define R_PARISC_FPTR64\t\t64\t/* 64 bits function address.  */\n#define R_PARISC_PLABEL32\t65\t/* 32 bits function address.  */\n#define R_PARISC_PLABEL21L\t66\t/* Left 21 bits of fct ptr.  */\n#define R_PARISC_PLABEL14R\t70\t/* Left 21 bits of fct ptr.  */\n#define R_PARISC_PCREL64\t72\t/* 64 bits PC-rel. address.  */\n#define R_PARISC_PCREL22F\t74\t/* 22 bits PC-rel. address.  */\n#define R_PARISC_PCREL14WR\t75\t/* PC-rel. address, right 14 bits.  */\n#define R_PARISC_PCREL14DR\t76\t/* PC rel. address, right 14 bits.  */\n#define R_PARISC_PCREL16F\t77\t/* 16 bits PC-rel. address.  */\n#define R_PARISC_PCREL16WF\t78\t/* 16 bits PC-rel. address.  */\n#define R_PARISC_PCREL16DF\t79\t/* 16 bits PC-rel. address.  */\n#define R_PARISC_DIR64\t\t80\t/* 64 bits of eff. address.  */\n#define R_PARISC_DIR14WR\t83\t/* 14 bits of eff. address.  */\n#define R_PARISC_DIR14DR\t84\t/* 14 bits of eff. address.  */\n#define R_PARISC_DIR16F\t\t85\t/* 16 bits of eff. address.  */\n#define R_PARISC_DIR16WF\t86\t/* 16 bits of eff. address.  */\n#define R_PARISC_DIR16DF\t87\t/* 16 bits of eff. address.  */\n#define R_PARISC_GPREL64\t88\t/* 64 bits of GP-rel. address.  */\n#define R_PARISC_GPREL14WR\t91\t/* GP-rel. address, right 14 bits.  */\n#define R_PARISC_GPREL14DR\t92\t/* GP-rel. address, right 14 bits.  */\n#define R_PARISC_GPREL16F\t93\t/* 16 bits GP-rel. address.  */\n#define R_PARISC_GPREL16WF\t94\t/* 16 bits GP-rel. address.  */\n#define R_PARISC_GPREL16DF\t95\t/* 16 bits GP-rel. address.  */\n#define R_PARISC_LTOFF64\t96\t/* 64 bits LT-rel. address.  */\n#define R_PARISC_LTOFF14WR\t99\t/* LT-rel. address, right 14 bits.  */\n#define R_PARISC_LTOFF14DR\t100\t/* LT-rel. address, right 14 bits.  */\n#define R_PARISC_LTOFF16F\t101\t/* 16 bits LT-rel. address.  */\n#define R_PARISC_LTOFF16WF\t102\t/* 16 bits LT-rel. address.  */\n#define R_PARISC_LTOFF16DF\t103\t/* 16 bits LT-rel. address.  */\n#define R_PARISC_SECREL64\t104\t/* 64 bits section rel. address.  */\n#define R_PARISC_SEGREL64\t112\t/* 64 bits segment rel. address.  */\n#define R_PARISC_PLTOFF14WR\t115\t/* PLT-rel. address, right 14 bits.  */\n#define R_PARISC_PLTOFF14DR\t116\t/* PLT-rel. address, right 14 bits.  */\n#define R_PARISC_PLTOFF16F\t117\t/* 16 bits LT-rel. address.  */\n#define R_PARISC_PLTOFF16WF\t118\t/* 16 bits PLT-rel. address.  */\n#define R_PARISC_PLTOFF16DF\t119\t/* 16 bits PLT-rel. address.  */\n#define R_PARISC_LTOFF_FPTR64\t120\t/* 64 bits LT-rel. function ptr.  */\n#define R_PARISC_LTOFF_FPTR14WR\t123\t/* LT-rel. fct. ptr., right 14 bits. */\n#define R_PARISC_LTOFF_FPTR14DR\t124\t/* LT-rel. fct. ptr., right 14 bits. */\n#define R_PARISC_LTOFF_FPTR16F\t125\t/* 16 bits LT-rel. function ptr.  */\n#define R_PARISC_LTOFF_FPTR16WF\t126\t/* 16 bits LT-rel. function ptr.  */\n#define R_PARISC_LTOFF_FPTR16DF\t127\t/* 16 bits LT-rel. function ptr.  */\n#define R_PARISC_LORESERVE\t128\n#define R_PARISC_COPY\t\t128\t/* Copy relocation.  */\n#define R_PARISC_IPLT\t\t129\t/* Dynamic reloc, imported PLT */\n#define R_PARISC_EPLT\t\t130\t/* Dynamic reloc, exported PLT */\n#define R_PARISC_TPREL32\t153\t/* 32 bits TP-rel. address.  */\n#define R_PARISC_TPREL21L\t154\t/* TP-rel. address, left 21 bits.  */\n#define R_PARISC_TPREL14R\t158\t/* TP-rel. address, right 14 bits.  */\n#define R_PARISC_LTOFF_TP21L\t162\t/* LT-TP-rel. address, left 21 bits. */\n#define R_PARISC_LTOFF_TP14R\t166\t/* LT-TP-rel. address, right 14 bits.*/\n#define R_PARISC_LTOFF_TP14F\t167\t/* 14 bits LT-TP-rel. address.  */\n#define R_PARISC_TPREL64\t216\t/* 64 bits TP-rel. address.  */\n#define R_PARISC_TPREL14WR\t219\t/* TP-rel. address, right 14 bits.  */\n#define R_PARISC_TPREL14DR\t220\t/* TP-rel. address, right 14 bits.  */\n#define R_PARISC_TPREL16F\t221\t/* 16 bits TP-rel. address.  */\n#define R_PARISC_TPREL16WF\t222\t/* 16 bits TP-rel. address.  */\n#define R_PARISC_TPREL16DF\t223\t/* 16 bits TP-rel. address.  */\n#define R_PARISC_LTOFF_TP64\t224\t/* 64 bits LT-TP-rel. address.  */\n#define R_PARISC_LTOFF_TP14WR\t227\t/* LT-TP-rel. address, right 14 bits.*/\n#define R_PARISC_LTOFF_TP14DR\t228\t/* LT-TP-rel. address, right 14 bits.*/\n#define R_PARISC_LTOFF_TP16F\t229\t/* 16 bits LT-TP-rel. address.  */\n#define R_PARISC_LTOFF_TP16WF\t230\t/* 16 bits LT-TP-rel. address.  */\n#define R_PARISC_LTOFF_TP16DF\t231\t/* 16 bits LT-TP-rel. address.  */\n#define R_PARISC_HIRESERVE\t255\n\n/* Legal values for p_type field of Elf32_Phdr/Elf64_Phdr.  */\n\n#define PT_HP_TLS\t\t(PT_LOOS + 0x0)\n#define PT_HP_CORE_NONE\t\t(PT_LOOS + 0x1)\n#define PT_HP_CORE_VERSION\t(PT_LOOS + 0x2)\n#define PT_HP_CORE_KERNEL\t(PT_LOOS + 0x3)\n#define PT_HP_CORE_COMM\t\t(PT_LOOS + 0x4)\n#define PT_HP_CORE_PROC\t\t(PT_LOOS + 0x5)\n#define PT_HP_CORE_LOADABLE\t(PT_LOOS + 0x6)\n#define PT_HP_CORE_STACK\t(PT_LOOS + 0x7)\n#define PT_HP_CORE_SHM\t\t(PT_LOOS + 0x8)\n#define PT_HP_CORE_MMF\t\t(PT_LOOS + 0x9)\n#define PT_HP_PARALLEL\t\t(PT_LOOS + 0x10)\n#define PT_HP_FASTBIND\t\t(PT_LOOS + 0x11)\n#define PT_HP_OPT_ANNOT\t\t(PT_LOOS + 0x12)\n#define PT_HP_HSL_ANNOT\t\t(PT_LOOS + 0x13)\n#define PT_HP_STACK\t\t(PT_LOOS + 0x14)\n\n#define PT_PARISC_ARCHEXT\t0x70000000\n#define PT_PARISC_UNWIND\t0x70000001\n\n/* Legal values for p_flags field of Elf32_Phdr/Elf64_Phdr.  */\n\n#define PF_PARISC_SBP\t\t0x08000000\n\n#define PF_HP_PAGE_SIZE\t\t0x00100000\n#define PF_HP_FAR_SHARED\t0x00200000\n#define PF_HP_NEAR_SHARED\t0x00400000\n#define PF_HP_CODE\t\t0x01000000\n#define PF_HP_MODIFY\t\t0x02000000\n#define PF_HP_LAZYSWAP\t\t0x04000000\n#define PF_HP_SBP\t\t0x08000000\n\n\n/* Alpha specific definitions.  */\n\n/* Legal values for e_flags field of Elf64_Ehdr.  */\n\n#define EF_ALPHA_32BIT\t\t1\t/* All addresses must be < 2GB.  */\n#define EF_ALPHA_CANRELAX\t2\t/* Relocations for relaxing exist.  */\n\n/* Legal values for sh_type field of Elf64_Shdr.  */\n\n/* These two are primerily concerned with ECOFF debugging info.  */\n#define SHT_ALPHA_DEBUG\t\t0x70000001\n#define SHT_ALPHA_REGINFO\t0x70000002\n\n/* Legal values for sh_flags field of Elf64_Shdr.  */\n\n#define SHF_ALPHA_GPREL\t\t0x10000000\n\n/* Legal values for st_other field of Elf64_Sym.  */\n#define STO_ALPHA_NOPV\t\t0x80\t/* No PV required.  */\n#define STO_ALPHA_STD_GPLOAD\t0x88\t/* PV only used for initial ldgp.  */\n\n/* Alpha relocs.  */\n\n#define R_ALPHA_NONE\t\t0\t/* No reloc */\n#define R_ALPHA_REFLONG\t\t1\t/* Direct 32 bit */\n#define R_ALPHA_REFQUAD\t\t2\t/* Direct 64 bit */\n#define R_ALPHA_GPREL32\t\t3\t/* GP relative 32 bit */\n#define R_ALPHA_LITERAL\t\t4\t/* GP relative 16 bit w/optimization */\n#define R_ALPHA_LITUSE\t\t5\t/* Optimization hint for LITERAL */\n#define R_ALPHA_GPDISP\t\t6\t/* Add displacement to GP */\n#define R_ALPHA_BRADDR\t\t7\t/* PC+4 relative 23 bit shifted */\n#define R_ALPHA_HINT\t\t8\t/* PC+4 relative 16 bit shifted */\n#define R_ALPHA_SREL16\t\t9\t/* PC relative 16 bit */\n#define R_ALPHA_SREL32\t\t10\t/* PC relative 32 bit */\n#define R_ALPHA_SREL64\t\t11\t/* PC relative 64 bit */\n#define R_ALPHA_GPRELHIGH\t17\t/* GP relative 32 bit, high 16 bits */\n#define R_ALPHA_GPRELLOW\t18\t/* GP relative 32 bit, low 16 bits */\n#define R_ALPHA_GPREL16\t\t19\t/* GP relative 16 bit */\n#define R_ALPHA_COPY\t\t24\t/* Copy symbol at runtime */\n#define R_ALPHA_GLOB_DAT\t25\t/* Create GOT entry */\n#define R_ALPHA_JMP_SLOT\t26\t/* Create PLT entry */\n#define R_ALPHA_RELATIVE\t27\t/* Adjust by program base */\n#define R_ALPHA_TLS_GD_HI\t28\n#define R_ALPHA_TLSGD\t\t29\n#define R_ALPHA_TLS_LDM\t\t30\n#define R_ALPHA_DTPMOD64\t31\n#define R_ALPHA_GOTDTPREL\t32\n#define R_ALPHA_DTPREL64\t33\n#define R_ALPHA_DTPRELHI\t34\n#define R_ALPHA_DTPRELLO\t35\n#define R_ALPHA_DTPREL16\t36\n#define R_ALPHA_GOTTPREL\t37\n#define R_ALPHA_TPREL64\t\t38\n#define R_ALPHA_TPRELHI\t\t39\n#define R_ALPHA_TPRELLO\t\t40\n#define R_ALPHA_TPREL16\t\t41\n/* Keep this the last entry.  */\n#define R_ALPHA_NUM\t\t46\n\n/* Magic values of the LITUSE relocation addend.  */\n#define LITUSE_ALPHA_ADDR\t0\n#define LITUSE_ALPHA_BASE\t1\n#define LITUSE_ALPHA_BYTOFF\t2\n#define LITUSE_ALPHA_JSR\t3\n#define LITUSE_ALPHA_TLS_GD\t4\n#define LITUSE_ALPHA_TLS_LDM\t5\n\n\n/* PowerPC specific declarations */\n\n/* Values for Elf32/64_Ehdr.e_flags.  */\n#define EF_PPC_EMB\t\t0x80000000\t/* PowerPC embedded flag */\n\n/* Cygnus local bits below */\n#define EF_PPC_RELOCATABLE\t0x00010000\t/* PowerPC -mrelocatable flag*/\n#define EF_PPC_RELOCATABLE_LIB\t0x00008000\t/* PowerPC -mrelocatable-lib\n\t\t\t\t\t\t   flag */\n\n/* PowerPC relocations defined by the ABIs */\n#define R_PPC_NONE\t\t0\n#define R_PPC_ADDR32\t\t1\t/* 32bit absolute address */\n#define R_PPC_ADDR24\t\t2\t/* 26bit address, 2 bits ignored.  */\n#define R_PPC_ADDR16\t\t3\t/* 16bit absolute address */\n#define R_PPC_ADDR16_LO\t\t4\t/* lower 16bit of absolute address */\n#define R_PPC_ADDR16_HI\t\t5\t/* high 16bit of absolute address */\n#define R_PPC_ADDR16_HA\t\t6\t/* adjusted high 16bit */\n#define R_PPC_ADDR14\t\t7\t/* 16bit address, 2 bits ignored */\n#define R_PPC_ADDR14_BRTAKEN\t8\n#define R_PPC_ADDR14_BRNTAKEN\t9\n#define R_PPC_REL24\t\t10\t/* PC relative 26 bit */\n#define R_PPC_REL14\t\t11\t/* PC relative 16 bit */\n#define R_PPC_REL14_BRTAKEN\t12\n#define R_PPC_REL14_BRNTAKEN\t13\n#define R_PPC_GOT16\t\t14\n#define R_PPC_GOT16_LO\t\t15\n#define R_PPC_GOT16_HI\t\t16\n#define R_PPC_GOT16_HA\t\t17\n#define R_PPC_PLTREL24\t\t18\n#define R_PPC_COPY\t\t19\n#define R_PPC_GLOB_DAT\t\t20\n#define R_PPC_JMP_SLOT\t\t21\n#define R_PPC_RELATIVE\t\t22\n#define R_PPC_LOCAL24PC\t\t23\n#define R_PPC_UADDR32\t\t24\n#define R_PPC_UADDR16\t\t25\n#define R_PPC_REL32\t\t26\n#define R_PPC_PLT32\t\t27\n#define R_PPC_PLTREL32\t\t28\n#define R_PPC_PLT16_LO\t\t29\n#define R_PPC_PLT16_HI\t\t30\n#define R_PPC_PLT16_HA\t\t31\n#define R_PPC_SDAREL16\t\t32\n#define R_PPC_SECTOFF\t\t33\n#define R_PPC_SECTOFF_LO\t34\n#define R_PPC_SECTOFF_HI\t35\n#define R_PPC_SECTOFF_HA\t36\n\n/* PowerPC relocations defined for the TLS access ABI.  */\n#define R_PPC_TLS\t\t67 /* none\t(sym+add)@tls */\n#define R_PPC_DTPMOD32\t\t68 /* word32\t(sym+add)@dtpmod */\n#define R_PPC_TPREL16\t\t69 /* half16*\t(sym+add)@tprel */\n#define R_PPC_TPREL16_LO\t70 /* half16\t(sym+add)@tprel@l */\n#define R_PPC_TPREL16_HI\t71 /* half16\t(sym+add)@tprel@h */\n#define R_PPC_TPREL16_HA\t72 /* half16\t(sym+add)@tprel@ha */\n#define R_PPC_TPREL32\t\t73 /* word32\t(sym+add)@tprel */\n#define R_PPC_DTPREL16\t\t74 /* half16*\t(sym+add)@dtprel */\n#define R_PPC_DTPREL16_LO\t75 /* half16\t(sym+add)@dtprel@l */\n#define R_PPC_DTPREL16_HI\t76 /* half16\t(sym+add)@dtprel@h */\n#define R_PPC_DTPREL16_HA\t77 /* half16\t(sym+add)@dtprel@ha */\n#define R_PPC_DTPREL32\t\t78 /* word32\t(sym+add)@dtprel */\n#define R_PPC_GOT_TLSGD16\t79 /* half16*\t(sym+add)@got@tlsgd */\n#define R_PPC_GOT_TLSGD16_LO\t80 /* half16\t(sym+add)@got@tlsgd@l */\n#define R_PPC_GOT_TLSGD16_HI\t81 /* half16\t(sym+add)@got@tlsgd@h */\n#define R_PPC_GOT_TLSGD16_HA\t82 /* half16\t(sym+add)@got@tlsgd@ha */\n#define R_PPC_GOT_TLSLD16\t83 /* half16*\t(sym+add)@got@tlsld */\n#define R_PPC_GOT_TLSLD16_LO\t84 /* half16\t(sym+add)@got@tlsld@l */\n#define R_PPC_GOT_TLSLD16_HI\t85 /* half16\t(sym+add)@got@tlsld@h */\n#define R_PPC_GOT_TLSLD16_HA\t86 /* half16\t(sym+add)@got@tlsld@ha */\n#define R_PPC_GOT_TPREL16\t87 /* half16*\t(sym+add)@got@tprel */\n#define R_PPC_GOT_TPREL16_LO\t88 /* half16\t(sym+add)@got@tprel@l */\n#define R_PPC_GOT_TPREL16_HI\t89 /* half16\t(sym+add)@got@tprel@h */\n#define R_PPC_GOT_TPREL16_HA\t90 /* half16\t(sym+add)@got@tprel@ha */\n#define R_PPC_GOT_DTPREL16\t91 /* half16*\t(sym+add)@got@dtprel */\n#define R_PPC_GOT_DTPREL16_LO\t92 /* half16*\t(sym+add)@got@dtprel@l */\n#define R_PPC_GOT_DTPREL16_HI\t93 /* half16*\t(sym+add)@got@dtprel@h */\n#define R_PPC_GOT_DTPREL16_HA\t94 /* half16*\t(sym+add)@got@dtprel@ha */\n\n/* Keep this the last entry.  */\n#define R_PPC_NUM\t\t95\n\n/* The remaining relocs are from the Embedded ELF ABI, and are not\n   in the SVR4 ELF ABI.  */\n#define R_PPC_EMB_NADDR32\t101\n#define R_PPC_EMB_NADDR16\t102\n#define R_PPC_EMB_NADDR16_LO\t103\n#define R_PPC_EMB_NADDR16_HI\t104\n#define R_PPC_EMB_NADDR16_HA\t105\n#define R_PPC_EMB_SDAI16\t106\n#define R_PPC_EMB_SDA2I16\t107\n#define R_PPC_EMB_SDA2REL\t108\n#define R_PPC_EMB_SDA21\t\t109\t/* 16 bit offset in SDA */\n#define R_PPC_EMB_MRKREF\t110\n#define R_PPC_EMB_RELSEC16\t111\n#define R_PPC_EMB_RELST_LO\t112\n#define R_PPC_EMB_RELST_HI\t113\n#define R_PPC_EMB_RELST_HA\t114\n#define R_PPC_EMB_BIT_FLD\t115\n#define R_PPC_EMB_RELSDA\t116\t/* 16 bit relative offset in SDA */\n\n/* Diab tool relocations.  */\n#define R_PPC_DIAB_SDA21_LO\t180\t/* like EMB_SDA21, but lower 16 bit */\n#define R_PPC_DIAB_SDA21_HI\t181\t/* like EMB_SDA21, but high 16 bit */\n#define R_PPC_DIAB_SDA21_HA\t182\t/* like EMB_SDA21, adjusted high 16 */\n#define R_PPC_DIAB_RELSDA_LO\t183\t/* like EMB_RELSDA, but lower 16 bit */\n#define R_PPC_DIAB_RELSDA_HI\t184\t/* like EMB_RELSDA, but high 16 bit */\n#define R_PPC_DIAB_RELSDA_HA\t185\t/* like EMB_RELSDA, adjusted high 16 */\n\n/* This is a phony reloc to handle any old fashioned TOC16 references\n   that may still be in object files.  */\n#define R_PPC_TOC16\t\t255\n\n\n/* PowerPC64 relocations defined by the ABIs */\n#define R_PPC64_NONE\t\tR_PPC_NONE\n#define R_PPC64_ADDR32\t\tR_PPC_ADDR32 /* 32bit absolute address */\n#define R_PPC64_ADDR24\t\tR_PPC_ADDR24 /* 26bit address, word aligned */\n#define R_PPC64_ADDR16\t\tR_PPC_ADDR16 /* 16bit absolute address */\n#define R_PPC64_ADDR16_LO\tR_PPC_ADDR16_LO\t/* lower 16bits of address */\n#define R_PPC64_ADDR16_HI\tR_PPC_ADDR16_HI\t/* high 16bits of address. */\n#define R_PPC64_ADDR16_HA\tR_PPC_ADDR16_HA /* adjusted high 16bits.  */\n#define R_PPC64_ADDR14\t\tR_PPC_ADDR14 /* 16bit address, word aligned */\n#define R_PPC64_ADDR14_BRTAKEN\tR_PPC_ADDR14_BRTAKEN\n#define R_PPC64_ADDR14_BRNTAKEN\tR_PPC_ADDR14_BRNTAKEN\n#define R_PPC64_REL24\t\tR_PPC_REL24 /* PC-rel. 26 bit, word aligned */\n#define R_PPC64_REL14\t\tR_PPC_REL14 /* PC relative 16 bit */\n#define R_PPC64_REL14_BRTAKEN\tR_PPC_REL14_BRTAKEN\n#define R_PPC64_REL14_BRNTAKEN\tR_PPC_REL14_BRNTAKEN\n#define R_PPC64_GOT16\t\tR_PPC_GOT16\n#define R_PPC64_GOT16_LO\tR_PPC_GOT16_LO\n#define R_PPC64_GOT16_HI\tR_PPC_GOT16_HI\n#define R_PPC64_GOT16_HA\tR_PPC_GOT16_HA\n\n#define R_PPC64_COPY\t\tR_PPC_COPY\n#define R_PPC64_GLOB_DAT\tR_PPC_GLOB_DAT\n#define R_PPC64_JMP_SLOT\tR_PPC_JMP_SLOT\n#define R_PPC64_RELATIVE\tR_PPC_RELATIVE\n\n#define R_PPC64_UADDR32\t\tR_PPC_UADDR32\n#define R_PPC64_UADDR16\t\tR_PPC_UADDR16\n#define R_PPC64_REL32\t\tR_PPC_REL32\n#define R_PPC64_PLT32\t\tR_PPC_PLT32\n#define R_PPC64_PLTREL32\tR_PPC_PLTREL32\n#define R_PPC64_PLT16_LO\tR_PPC_PLT16_LO\n#define R_PPC64_PLT16_HI\tR_PPC_PLT16_HI\n#define R_PPC64_PLT16_HA\tR_PPC_PLT16_HA\n\n#define R_PPC64_SECTOFF\t\tR_PPC_SECTOFF\n#define R_PPC64_SECTOFF_LO\tR_PPC_SECTOFF_LO\n#define R_PPC64_SECTOFF_HI\tR_PPC_SECTOFF_HI\n#define R_PPC64_SECTOFF_HA\tR_PPC_SECTOFF_HA\n#define R_PPC64_ADDR30\t\t37 /* word30 (S + A - P) >> 2 */\n#define R_PPC64_ADDR64\t\t38 /* doubleword64 S + A */\n#define R_PPC64_ADDR16_HIGHER\t39 /* half16 #higher(S + A) */\n#define R_PPC64_ADDR16_HIGHERA\t40 /* half16 #highera(S + A) */\n#define R_PPC64_ADDR16_HIGHEST\t41 /* half16 #highest(S + A) */\n#define R_PPC64_ADDR16_HIGHESTA\t42 /* half16 #highesta(S + A) */\n#define R_PPC64_UADDR64\t\t43 /* doubleword64 S + A */\n#define R_PPC64_REL64\t\t44 /* doubleword64 S + A - P */\n#define R_PPC64_PLT64\t\t45 /* doubleword64 L + A */\n#define R_PPC64_PLTREL64\t46 /* doubleword64 L + A - P */\n#define R_PPC64_TOC16\t\t47 /* half16* S + A - .TOC */\n#define R_PPC64_TOC16_LO\t48 /* half16 #lo(S + A - .TOC.) */\n#define R_PPC64_TOC16_HI\t49 /* half16 #hi(S + A - .TOC.) */\n#define R_PPC64_TOC16_HA\t50 /* half16 #ha(S + A - .TOC.) */\n#define R_PPC64_TOC\t\t51 /* doubleword64 .TOC */\n#define R_PPC64_PLTGOT16\t52 /* half16* M + A */\n#define R_PPC64_PLTGOT16_LO\t53 /* half16 #lo(M + A) */\n#define R_PPC64_PLTGOT16_HI\t54 /* half16 #hi(M + A) */\n#define R_PPC64_PLTGOT16_HA\t55 /* half16 #ha(M + A) */\n\n#define R_PPC64_ADDR16_DS\t56 /* half16ds* (S + A) >> 2 */\n#define R_PPC64_ADDR16_LO_DS\t57 /* half16ds  #lo(S + A) >> 2 */\n#define R_PPC64_GOT16_DS\t58 /* half16ds* (G + A) >> 2 */\n#define R_PPC64_GOT16_LO_DS\t59 /* half16ds  #lo(G + A) >> 2 */\n#define R_PPC64_PLT16_LO_DS\t60 /* half16ds  #lo(L + A) >> 2 */\n#define R_PPC64_SECTOFF_DS\t61 /* half16ds* (R + A) >> 2 */\n#define R_PPC64_SECTOFF_LO_DS\t62 /* half16ds  #lo(R + A) >> 2 */\n#define R_PPC64_TOC16_DS\t63 /* half16ds* (S + A - .TOC.) >> 2 */\n#define R_PPC64_TOC16_LO_DS\t64 /* half16ds  #lo(S + A - .TOC.) >> 2 */\n#define R_PPC64_PLTGOT16_DS\t65 /* half16ds* (M + A) >> 2 */\n#define R_PPC64_PLTGOT16_LO_DS\t66 /* half16ds  #lo(M + A) >> 2 */\n\n/* PowerPC64 relocations defined for the TLS access ABI.  */\n#define R_PPC64_TLS\t\t67 /* none\t(sym+add)@tls */\n#define R_PPC64_DTPMOD64\t68 /* doubleword64 (sym+add)@dtpmod */\n#define R_PPC64_TPREL16\t\t69 /* half16*\t(sym+add)@tprel */\n#define R_PPC64_TPREL16_LO\t70 /* half16\t(sym+add)@tprel@l */\n#define R_PPC64_TPREL16_HI\t71 /* half16\t(sym+add)@tprel@h */\n#define R_PPC64_TPREL16_HA\t72 /* half16\t(sym+add)@tprel@ha */\n#define R_PPC64_TPREL64\t\t73 /* doubleword64 (sym+add)@tprel */\n#define R_PPC64_DTPREL16\t74 /* half16*\t(sym+add)@dtprel */\n#define R_PPC64_DTPREL16_LO\t75 /* half16\t(sym+add)@dtprel@l */\n#define R_PPC64_DTPREL16_HI\t76 /* half16\t(sym+add)@dtprel@h */\n#define R_PPC64_DTPREL16_HA\t77 /* half16\t(sym+add)@dtprel@ha */\n#define R_PPC64_DTPREL64\t78 /* doubleword64 (sym+add)@dtprel */\n#define R_PPC64_GOT_TLSGD16\t79 /* half16*\t(sym+add)@got@tlsgd */\n#define R_PPC64_GOT_TLSGD16_LO\t80 /* half16\t(sym+add)@got@tlsgd@l */\n#define R_PPC64_GOT_TLSGD16_HI\t81 /* half16\t(sym+add)@got@tlsgd@h */\n#define R_PPC64_GOT_TLSGD16_HA\t82 /* half16\t(sym+add)@got@tlsgd@ha */\n#define R_PPC64_GOT_TLSLD16\t83 /* half16*\t(sym+add)@got@tlsld */\n#define R_PPC64_GOT_TLSLD16_LO\t84 /* half16\t(sym+add)@got@tlsld@l */\n#define R_PPC64_GOT_TLSLD16_HI\t85 /* half16\t(sym+add)@got@tlsld@h */\n#define R_PPC64_GOT_TLSLD16_HA\t86 /* half16\t(sym+add)@got@tlsld@ha */\n#define R_PPC64_GOT_TPREL16_DS\t87 /* half16ds*\t(sym+add)@got@tprel */\n#define R_PPC64_GOT_TPREL16_LO_DS 88 /* half16ds (sym+add)@got@tprel@l */\n#define R_PPC64_GOT_TPREL16_HI\t89 /* half16\t(sym+add)@got@tprel@h */\n#define R_PPC64_GOT_TPREL16_HA\t90 /* half16\t(sym+add)@got@tprel@ha */\n#define R_PPC64_GOT_DTPREL16_DS\t91 /* half16ds*\t(sym+add)@got@dtprel */\n#define R_PPC64_GOT_DTPREL16_LO_DS 92 /* half16ds (sym+add)@got@dtprel@l */\n#define R_PPC64_GOT_DTPREL16_HI\t93 /* half16\t(sym+add)@got@dtprel@h */\n#define R_PPC64_GOT_DTPREL16_HA\t94 /* half16\t(sym+add)@got@dtprel@ha */\n#define R_PPC64_TPREL16_DS\t95 /* half16ds*\t(sym+add)@tprel */\n#define R_PPC64_TPREL16_LO_DS\t96 /* half16ds\t(sym+add)@tprel@l */\n#define R_PPC64_TPREL16_HIGHER\t97 /* half16\t(sym+add)@tprel@higher */\n#define R_PPC64_TPREL16_HIGHERA\t98 /* half16\t(sym+add)@tprel@highera */\n#define R_PPC64_TPREL16_HIGHEST\t99 /* half16\t(sym+add)@tprel@highest */\n#define R_PPC64_TPREL16_HIGHESTA 100 /* half16\t(sym+add)@tprel@highesta */\n#define R_PPC64_DTPREL16_DS\t101 /* half16ds* (sym+add)@dtprel */\n#define R_PPC64_DTPREL16_LO_DS\t102 /* half16ds\t(sym+add)@dtprel@l */\n#define R_PPC64_DTPREL16_HIGHER\t103 /* half16\t(sym+add)@dtprel@higher */\n#define R_PPC64_DTPREL16_HIGHERA 104 /* half16\t(sym+add)@dtprel@highera */\n#define R_PPC64_DTPREL16_HIGHEST 105 /* half16\t(sym+add)@dtprel@highest */\n#define R_PPC64_DTPREL16_HIGHESTA 106 /* half16\t(sym+add)@dtprel@highesta */\n\n/* Keep this the last entry.  */\n#define R_PPC64_NUM\t\t107\n\n/* PowerPC64 specific values for the Dyn d_tag field.  */\n#define DT_PPC64_GLINK  (DT_LOPROC + 0)\n#define DT_PPC64_OPD\t(DT_LOPROC + 1)\n#define DT_PPC64_OPDSZ\t(DT_LOPROC + 2)\n#define DT_PPC64_NUM    3\n\n\n/* ARM specific declarations */\n\n/* Processor specific flags for the ELF header e_flags field.  */\n#define EF_ARM_RELEXEC     0x01\n#define EF_ARM_HASENTRY    0x02\n#define EF_ARM_INTERWORK   0x04\n#define EF_ARM_APCS_26     0x08\n#define EF_ARM_APCS_FLOAT  0x10\n#define EF_ARM_PIC         0x20\n#define EF_ARM_ALIGN8      0x40\t\t/* 8-bit structure alignment is in use */\n#define EF_ARM_NEW_ABI     0x80\n#define EF_ARM_OLD_ABI     0x100\n\n/* Other constants defined in the ARM ELF spec. version B-01.  */\n/* NB. These conflict with values defined above.  */\n#define EF_ARM_SYMSARESORTED\t0x04\n#define EF_ARM_DYNSYMSUSESEGIDX 0x08\n#define EF_ARM_MAPSYMSFIRST\t0x10\n#define EF_ARM_EABIMASK\t\t0XFF000000\n\n#define EF_ARM_EABI_VERSION(flags) ((flags) & EF_ARM_EABIMASK)\n#define EF_ARM_EABI_UNKNOWN  0x00000000\n#define EF_ARM_EABI_VER1     0x01000000\n#define EF_ARM_EABI_VER2     0x02000000\n\n/* Additional symbol types for Thumb */\n#define STT_ARM_TFUNC      0xd\n\n/* ARM-specific values for sh_flags */\n#define SHF_ARM_ENTRYSECT  0x10000000   /* Section contains an entry point */\n#define SHF_ARM_COMDEF     0x80000000   /* Section may be multiply defined\n\t\t\t\t\t   in the input to a link step */\n\n/* ARM-specific program header flags */\n#define PF_ARM_SB          0x10000000   /* Segment contains the location\n\t\t\t\t\t   addressed by the static base */\n\n/* ARM relocs.  */\n#define R_ARM_NONE\t\t0\t/* No reloc */\n#define R_ARM_PC24\t\t1\t/* PC relative 26 bit branch */\n#define R_ARM_ABS32\t\t2\t/* Direct 32 bit  */\n#define R_ARM_REL32\t\t3\t/* PC relative 32 bit */\n#define R_ARM_PC13\t\t4\n#define R_ARM_ABS16\t\t5\t/* Direct 16 bit */\n#define R_ARM_ABS12\t\t6\t/* Direct 12 bit */\n#define R_ARM_THM_ABS5\t\t7\n#define R_ARM_ABS8\t\t8\t/* Direct 8 bit */\n#define R_ARM_SBREL32\t\t9\n#define R_ARM_THM_PC22\t\t10\n#define R_ARM_THM_PC8\t\t11\n#define R_ARM_AMP_VCALL9\t12\n#define R_ARM_SWI24\t\t13\n#define R_ARM_THM_SWI8\t\t14\n#define R_ARM_XPC25\t\t15\n#define R_ARM_THM_XPC22\t\t16\n#define R_ARM_COPY\t\t20\t/* Copy symbol at runtime */\n#define R_ARM_GLOB_DAT\t\t21\t/* Create GOT entry */\n#define R_ARM_JUMP_SLOT\t\t22\t/* Create PLT entry */\n#define R_ARM_RELATIVE\t\t23\t/* Adjust by program base */\n#define R_ARM_GOTOFF\t\t24\t/* 32 bit offset to GOT */\n#define R_ARM_GOTPC\t\t25\t/* 32 bit PC relative offset to GOT */\n#define R_ARM_GOT32\t\t26\t/* 32 bit GOT entry */\n#define R_ARM_PLT32\t\t27\t/* 32 bit PLT address */\n#define R_ARM_ALU_PCREL_7_0\t32\n#define R_ARM_ALU_PCREL_15_8\t33\n#define R_ARM_ALU_PCREL_23_15\t34\n#define R_ARM_LDR_SBREL_11_0\t35\n#define R_ARM_ALU_SBREL_19_12\t36\n#define R_ARM_ALU_SBREL_27_20\t37\n#define R_ARM_GNU_VTENTRY\t100\n#define R_ARM_GNU_VTINHERIT\t101\n#define R_ARM_THM_PC11\t\t102\t/* thumb unconditional branch */\n#define R_ARM_THM_PC9\t\t103\t/* thumb conditional branch */\n#define R_ARM_RXPC25\t\t249\n#define R_ARM_RSBREL32\t\t250\n#define R_ARM_THM_RPC22\t\t251\n#define R_ARM_RREL32\t\t252\n#define R_ARM_RABS22\t\t253\n#define R_ARM_RPC24\t\t254\n#define R_ARM_RBASE\t\t255\n/* Keep this the last entry.  */\n#define R_ARM_NUM\t\t256\n\n/* IA-64 specific declarations.  */\n\n/* Processor specific flags for the Ehdr e_flags field.  */\n#define EF_IA_64_MASKOS\t\t0x0000000f\t/* os-specific flags */\n#define EF_IA_64_ABI64\t\t0x00000010\t/* 64-bit ABI */\n#define EF_IA_64_ARCH\t\t0xff000000\t/* arch. version mask */\n\n/* Processor specific values for the Phdr p_type field.  */\n#define PT_IA_64_ARCHEXT\t(PT_LOPROC + 0)\t/* arch extension bits */\n#define PT_IA_64_UNWIND\t\t(PT_LOPROC + 1)\t/* ia64 unwind bits */\n#define PT_IA_64_HP_OPT_ANOT\t(PT_LOOS + 0x12)\n#define PT_IA_64_HP_HSL_ANOT\t(PT_LOOS + 0x13)\n#define PT_IA_64_HP_STACK\t(PT_LOOS + 0x14)\n\n/* Processor specific flags for the Phdr p_flags field.  */\n#define PF_IA_64_NORECOV\t0x80000000\t/* spec insns w/o recovery */\n\n/* Processor specific values for the Shdr sh_type field.  */\n#define SHT_IA_64_EXT\t\t(SHT_LOPROC + 0) /* extension bits */\n#define SHT_IA_64_UNWIND\t(SHT_LOPROC + 1) /* unwind bits */\n\n/* Processor specific flags for the Shdr sh_flags field.  */\n#define SHF_IA_64_SHORT\t\t0x10000000\t/* section near gp */\n#define SHF_IA_64_NORECOV\t0x20000000\t/* spec insns w/o recovery */\n\n/* Processor specific values for the Dyn d_tag field.  */\n#define DT_IA_64_PLT_RESERVE\t(DT_LOPROC + 0)\n#define DT_IA_64_NUM\t\t1\n\n/* IA-64 relocations.  */\n#define R_IA64_NONE\t\t0x00\t/* none */\n#define R_IA64_IMM14\t\t0x21\t/* symbol + addend, add imm14 */\n#define R_IA64_IMM22\t\t0x22\t/* symbol + addend, add imm22 */\n#define R_IA64_IMM64\t\t0x23\t/* symbol + addend, mov imm64 */\n#define R_IA64_DIR32MSB\t\t0x24\t/* symbol + addend, data4 MSB */\n#define R_IA64_DIR32LSB\t\t0x25\t/* symbol + addend, data4 LSB */\n#define R_IA64_DIR64MSB\t\t0x26\t/* symbol + addend, data8 MSB */\n#define R_IA64_DIR64LSB\t\t0x27\t/* symbol + addend, data8 LSB */\n#define R_IA64_GPREL22\t\t0x2a\t/* @gprel(sym + add), add imm22 */\n#define R_IA64_GPREL64I\t\t0x2b\t/* @gprel(sym + add), mov imm64 */\n#define R_IA64_GPREL32MSB\t0x2c\t/* @gprel(sym + add), data4 MSB */\n#define R_IA64_GPREL32LSB\t0x2d\t/* @gprel(sym + add), data4 LSB */\n#define R_IA64_GPREL64MSB\t0x2e\t/* @gprel(sym + add), data8 MSB */\n#define R_IA64_GPREL64LSB\t0x2f\t/* @gprel(sym + add), data8 LSB */\n#define R_IA64_LTOFF22\t\t0x32\t/* @ltoff(sym + add), add imm22 */\n#define R_IA64_LTOFF64I\t\t0x33\t/* @ltoff(sym + add), mov imm64 */\n#define R_IA64_PLTOFF22\t\t0x3a\t/* @pltoff(sym + add), add imm22 */\n#define R_IA64_PLTOFF64I\t0x3b\t/* @pltoff(sym + add), mov imm64 */\n#define R_IA64_PLTOFF64MSB\t0x3e\t/* @pltoff(sym + add), data8 MSB */\n#define R_IA64_PLTOFF64LSB\t0x3f\t/* @pltoff(sym + add), data8 LSB */\n#define R_IA64_FPTR64I\t\t0x43\t/* @fptr(sym + add), mov imm64 */\n#define R_IA64_FPTR32MSB\t0x44\t/* @fptr(sym + add), data4 MSB */\n#define R_IA64_FPTR32LSB\t0x45\t/* @fptr(sym + add), data4 LSB */\n#define R_IA64_FPTR64MSB\t0x46\t/* @fptr(sym + add), data8 MSB */\n#define R_IA64_FPTR64LSB\t0x47\t/* @fptr(sym + add), data8 LSB */\n#define R_IA64_PCREL60B\t\t0x48\t/* @pcrel(sym + add), brl */\n#define R_IA64_PCREL21B\t\t0x49\t/* @pcrel(sym + add), ptb, call */\n#define R_IA64_PCREL21M\t\t0x4a\t/* @pcrel(sym + add), chk.s */\n#define R_IA64_PCREL21F\t\t0x4b\t/* @pcrel(sym + add), fchkf */\n#define R_IA64_PCREL32MSB\t0x4c\t/* @pcrel(sym + add), data4 MSB */\n#define R_IA64_PCREL32LSB\t0x4d\t/* @pcrel(sym + add), data4 LSB */\n#define R_IA64_PCREL64MSB\t0x4e\t/* @pcrel(sym + add), data8 MSB */\n#define R_IA64_PCREL64LSB\t0x4f\t/* @pcrel(sym + add), data8 LSB */\n#define R_IA64_LTOFF_FPTR22\t0x52\t/* @ltoff(@fptr(s+a)), imm22 */\n#define R_IA64_LTOFF_FPTR64I\t0x53\t/* @ltoff(@fptr(s+a)), imm64 */\n#define R_IA64_LTOFF_FPTR32MSB\t0x54\t/* @ltoff(@fptr(s+a)), data4 MSB */\n#define R_IA64_LTOFF_FPTR32LSB\t0x55\t/* @ltoff(@fptr(s+a)), data4 LSB */\n#define R_IA64_LTOFF_FPTR64MSB\t0x56\t/* @ltoff(@fptr(s+a)), data8 MSB */\n#define R_IA64_LTOFF_FPTR64LSB\t0x57\t/* @ltoff(@fptr(s+a)), data8 LSB */\n#define R_IA64_SEGREL32MSB\t0x5c\t/* @segrel(sym + add), data4 MSB */\n#define R_IA64_SEGREL32LSB\t0x5d\t/* @segrel(sym + add), data4 LSB */\n#define R_IA64_SEGREL64MSB\t0x5e\t/* @segrel(sym + add), data8 MSB */\n#define R_IA64_SEGREL64LSB\t0x5f\t/* @segrel(sym + add), data8 LSB */\n#define R_IA64_SECREL32MSB\t0x64\t/* @secrel(sym + add), data4 MSB */\n#define R_IA64_SECREL32LSB\t0x65\t/* @secrel(sym + add), data4 LSB */\n#define R_IA64_SECREL64MSB\t0x66\t/* @secrel(sym + add), data8 MSB */\n#define R_IA64_SECREL64LSB\t0x67\t/* @secrel(sym + add), data8 LSB */\n#define R_IA64_REL32MSB\t\t0x6c\t/* data 4 + REL */\n#define R_IA64_REL32LSB\t\t0x6d\t/* data 4 + REL */\n#define R_IA64_REL64MSB\t\t0x6e\t/* data 8 + REL */\n#define R_IA64_REL64LSB\t\t0x6f\t/* data 8 + REL */\n#define R_IA64_LTV32MSB\t\t0x74\t/* symbol + addend, data4 MSB */\n#define R_IA64_LTV32LSB\t\t0x75\t/* symbol + addend, data4 LSB */\n#define R_IA64_LTV64MSB\t\t0x76\t/* symbol + addend, data8 MSB */\n#define R_IA64_LTV64LSB\t\t0x77\t/* symbol + addend, data8 LSB */\n#define R_IA64_PCREL21BI\t0x79\t/* @pcrel(sym + add), 21bit inst */\n#define R_IA64_PCREL22\t\t0x7a\t/* @pcrel(sym + add), 22bit inst */\n#define R_IA64_PCREL64I\t\t0x7b\t/* @pcrel(sym + add), 64bit inst */\n#define R_IA64_IPLTMSB\t\t0x80\t/* dynamic reloc, imported PLT, MSB */\n#define R_IA64_IPLTLSB\t\t0x81\t/* dynamic reloc, imported PLT, LSB */\n#define R_IA64_COPY\t\t0x84\t/* copy relocation */\n#define R_IA64_SUB\t\t0x85\t/* Addend and symbol difference */\n#define R_IA64_LTOFF22X\t\t0x86\t/* LTOFF22, relaxable.  */\n#define R_IA64_LDXMOV\t\t0x87\t/* Use of LTOFF22X.  */\n#define R_IA64_TPREL14\t\t0x91\t/* @tprel(sym + add), imm14 */\n#define R_IA64_TPREL22\t\t0x92\t/* @tprel(sym + add), imm22 */\n#define R_IA64_TPREL64I\t\t0x93\t/* @tprel(sym + add), imm64 */\n#define R_IA64_TPREL64MSB\t0x96\t/* @tprel(sym + add), data8 MSB */\n#define R_IA64_TPREL64LSB\t0x97\t/* @tprel(sym + add), data8 LSB */\n#define R_IA64_LTOFF_TPREL22\t0x9a\t/* @ltoff(@tprel(s+a)), imm2 */\n#define R_IA64_DTPMOD64MSB\t0xa6\t/* @dtpmod(sym + add), data8 MSB */\n#define R_IA64_DTPMOD64LSB\t0xa7\t/* @dtpmod(sym + add), data8 LSB */\n#define R_IA64_LTOFF_DTPMOD22\t0xaa\t/* @ltoff(@dtpmod(sym + add)), imm22 */\n#define R_IA64_DTPREL14\t\t0xb1\t/* @dtprel(sym + add), imm14 */\n#define R_IA64_DTPREL22\t\t0xb2\t/* @dtprel(sym + add), imm22 */\n#define R_IA64_DTPREL64I\t0xb3\t/* @dtprel(sym + add), imm64 */\n#define R_IA64_DTPREL32MSB\t0xb4\t/* @dtprel(sym + add), data4 MSB */\n#define R_IA64_DTPREL32LSB\t0xb5\t/* @dtprel(sym + add), data4 LSB */\n#define R_IA64_DTPREL64MSB\t0xb6\t/* @dtprel(sym + add), data8 MSB */\n#define R_IA64_DTPREL64LSB\t0xb7\t/* @dtprel(sym + add), data8 LSB */\n#define R_IA64_LTOFF_DTPREL22\t0xba\t/* @ltoff(@dtprel(s+a)), imm22 */\n\n/* SH specific declarations */\n\n/* SH relocs.  */\n#define\tR_SH_NONE\t\t0\n#define\tR_SH_DIR32\t\t1\n#define\tR_SH_REL32\t\t2\n#define\tR_SH_DIR8WPN\t\t3\n#define\tR_SH_IND12W\t\t4\n#define\tR_SH_DIR8WPL\t\t5\n#define\tR_SH_DIR8WPZ\t\t6\n#define\tR_SH_DIR8BP\t\t7\n#define\tR_SH_DIR8W\t\t8\n#define\tR_SH_DIR8L\t\t9\n#define\tR_SH_SWITCH16\t\t25\n#define\tR_SH_SWITCH32\t\t26\n#define\tR_SH_USES\t\t27\n#define\tR_SH_COUNT\t\t28\n#define\tR_SH_ALIGN\t\t29\n#define\tR_SH_CODE\t\t30\n#define\tR_SH_DATA\t\t31\n#define\tR_SH_LABEL\t\t32\n#define\tR_SH_SWITCH8\t\t33\n#define\tR_SH_GNU_VTINHERIT\t34\n#define\tR_SH_GNU_VTENTRY\t35\n#define\tR_SH_TLS_GD_32\t\t144\n#define\tR_SH_TLS_LD_32\t\t145\n#define\tR_SH_TLS_LDO_32\t\t146\n#define\tR_SH_TLS_IE_32\t\t147\n#define\tR_SH_TLS_LE_32\t\t148\n#define\tR_SH_TLS_DTPMOD32\t149\n#define\tR_SH_TLS_DTPOFF32\t150\n#define\tR_SH_TLS_TPOFF32\t151\n#define\tR_SH_GOT32\t\t160\n#define\tR_SH_PLT32\t\t161\n#define\tR_SH_COPY\t\t162\n#define\tR_SH_GLOB_DAT\t\t163\n#define\tR_SH_JMP_SLOT\t\t164\n#define\tR_SH_RELATIVE\t\t165\n#define\tR_SH_GOTOFF\t\t166\n#define\tR_SH_GOTPC\t\t167\n/* Keep this the last entry.  */\n#define\tR_SH_NUM\t\t256\n\n/* Additional s390 relocs */\n\n#define R_390_NONE\t\t0\t/* No reloc.  */\n#define R_390_8\t\t\t1\t/* Direct 8 bit.  */\n#define R_390_12\t\t2\t/* Direct 12 bit.  */\n#define R_390_16\t\t3\t/* Direct 16 bit.  */\n#define R_390_32\t\t4\t/* Direct 32 bit.  */\n#define R_390_PC32\t\t5\t/* PC relative 32 bit.\t*/\n#define R_390_GOT12\t\t6\t/* 12 bit GOT offset.  */\n#define R_390_GOT32\t\t7\t/* 32 bit GOT offset.  */\n#define R_390_PLT32\t\t8\t/* 32 bit PC relative PLT address.  */\n#define R_390_COPY\t\t9\t/* Copy symbol at runtime.  */\n#define R_390_GLOB_DAT\t\t10\t/* Create GOT entry.  */\n#define R_390_JMP_SLOT\t\t11\t/* Create PLT entry.  */\n#define R_390_RELATIVE\t\t12\t/* Adjust by program base.  */\n#define R_390_GOTOFF32\t\t13\t/* 32 bit offset to GOT.\t */\n#define R_390_GOTPC\t\t14\t/* 32 bit PC relative offset to GOT.  */\n#define R_390_GOT16\t\t15\t/* 16 bit GOT offset.  */\n#define R_390_PC16\t\t16\t/* PC relative 16 bit.\t*/\n#define R_390_PC16DBL\t\t17\t/* PC relative 16 bit shifted by 1.  */\n#define R_390_PLT16DBL\t\t18\t/* 16 bit PC rel. PLT shifted by 1.  */\n#define R_390_PC32DBL\t\t19\t/* PC relative 32 bit shifted by 1.  */\n#define R_390_PLT32DBL\t\t20\t/* 32 bit PC rel. PLT shifted by 1.  */\n#define R_390_GOTPCDBL\t\t21\t/* 32 bit PC rel. GOT shifted by 1.  */\n#define R_390_64\t\t22\t/* Direct 64 bit.  */\n#define R_390_PC64\t\t23\t/* PC relative 64 bit.\t*/\n#define R_390_GOT64\t\t24\t/* 64 bit GOT offset.  */\n#define R_390_PLT64\t\t25\t/* 64 bit PC relative PLT address.  */\n#define R_390_GOTENT\t\t26\t/* 32 bit PC rel. to GOT entry >> 1. */\n#define R_390_GOTOFF16\t\t27\t/* 16 bit offset to GOT. */\n#define R_390_GOTOFF64\t\t28\t/* 64 bit offset to GOT. */\n#define R_390_GOTPLT12\t\t29\t/* 12 bit offset to jump slot.\t*/\n#define R_390_GOTPLT16\t\t30\t/* 16 bit offset to jump slot.\t*/\n#define R_390_GOTPLT32\t\t31\t/* 32 bit offset to jump slot.\t*/\n#define R_390_GOTPLT64\t\t32\t/* 64 bit offset to jump slot.\t*/\n#define R_390_GOTPLTENT\t\t33\t/* 32 bit rel. offset to jump slot.  */\n#define R_390_PLTOFF16\t\t34\t/* 16 bit offset from GOT to PLT. */\n#define R_390_PLTOFF32\t\t35\t/* 32 bit offset from GOT to PLT. */\n#define R_390_PLTOFF64\t\t36\t/* 16 bit offset from GOT to PLT. */\n#define R_390_TLS_LOAD\t\t37\t/* Tag for load insn in TLS code.  */\n#define R_390_TLS_GDCALL\t38\t/* Tag for function call in general\n\t\t\t\t\t   dynamic TLS code. */\n#define R_390_TLS_LDCALL\t39\t/* Tag for function call in local\n\t\t\t\t\t   dynamic TLS code. */\n#define R_390_TLS_GD32\t\t40\t/* Direct 32 bit for general dynamic\n\t\t\t\t\t   thread local data.  */\n#define R_390_TLS_GD64\t\t41\t/* Direct 64 bit for general dynamic\n\t\t\t\t\t  thread local data.  */\n#define R_390_TLS_GOTIE12\t42\t/* 12 bit GOT offset for static TLS\n\t\t\t\t\t   block offset.  */\n#define R_390_TLS_GOTIE32\t43\t/* 32 bit GOT offset for static TLS\n\t\t\t\t\t   block offset.  */\n#define R_390_TLS_GOTIE64\t44\t/* 64 bit GOT offset for static TLS\n\t\t\t\t\t   block offset. */\n#define R_390_TLS_LDM32\t\t45\t/* Direct 32 bit for local dynamic\n\t\t\t\t\t   thread local data in LE code.  */\n#define R_390_TLS_LDM64\t\t46\t/* Direct 64 bit for local dynamic\n\t\t\t\t\t   thread local data in LE code.  */\n#define R_390_TLS_IE32\t\t47\t/* 32 bit address of GOT entry for\n\t\t\t\t\t   negated static TLS block offset.  */\n#define R_390_TLS_IE64\t\t48\t/* 64 bit address of GOT entry for\n\t\t\t\t\t   negated static TLS block offset.  */\n#define R_390_TLS_IEENT\t\t49\t/* 32 bit rel. offset to GOT entry for\n\t\t\t\t\t   negated static TLS block offset.  */\n#define R_390_TLS_LE32\t\t50\t/* 32 bit negated offset relative to\n\t\t\t\t\t   static TLS block.  */\n#define R_390_TLS_LE64\t\t51\t/* 64 bit negated offset relative to\n\t\t\t\t\t   static TLS block.  */\n#define R_390_TLS_LDO32\t\t52\t/* 32 bit offset relative to TLS\n\t\t\t\t\t   block.  */\n#define R_390_TLS_LDO64\t\t53\t/* 64 bit offset relative to TLS\n\t\t\t\t\t   block.  */\n#define R_390_TLS_DTPMOD\t54\t/* ID of module containing symbol.  */\n#define R_390_TLS_DTPOFF\t55\t/* Offset in TLS block.\t */\n#define R_390_TLS_TPOFF\t\t56\t/* Negated offset in static TLS\n\t\t\t\t\t   block.  */\n#define R_390_20\t\t57\t/* Direct 20 bit.  */\n#define R_390_GOT20\t\t58\t/* 20 bit GOT offset.  */\n#define R_390_GOTPLT20\t\t59\t/* 20 bit offset to jump slot.  */\n#define R_390_TLS_GOTIE20\t60\t/* 20 bit GOT offset for static TLS\n\t\t\t\t\t   block offset.  */\n/* Keep this the last entry.  */\n#define R_390_NUM\t\t61\n\n\n/* CRIS relocations.  */\n#define R_CRIS_NONE\t\t0\n#define R_CRIS_8\t\t1\n#define R_CRIS_16\t\t2\n#define R_CRIS_32\t\t3\n#define R_CRIS_8_PCREL\t\t4\n#define R_CRIS_16_PCREL\t\t5\n#define R_CRIS_32_PCREL\t\t6\n#define R_CRIS_GNU_VTINHERIT\t7\n#define R_CRIS_GNU_VTENTRY\t8\n#define R_CRIS_COPY\t\t9\n#define R_CRIS_GLOB_DAT\t\t10\n#define R_CRIS_JUMP_SLOT\t11\n#define R_CRIS_RELATIVE\t\t12\n#define R_CRIS_16_GOT\t\t13\n#define R_CRIS_32_GOT\t\t14\n#define R_CRIS_16_GOTPLT\t15\n#define R_CRIS_32_GOTPLT\t16\n#define R_CRIS_32_GOTREL\t17\n#define R_CRIS_32_PLT_GOTREL\t18\n#define R_CRIS_32_PLT_PCREL\t19\n\n#define R_CRIS_NUM\t\t20\n\n\n/* AMD x86-64 relocations.  */\n#define R_X86_64_NONE\t\t0\t/* No reloc */\n#define R_X86_64_64\t\t1\t/* Direct 64 bit  */\n#define R_X86_64_PC32\t\t2\t/* PC relative 32 bit signed */\n#define R_X86_64_GOT32\t\t3\t/* 32 bit GOT entry */\n#define R_X86_64_PLT32\t\t4\t/* 32 bit PLT address */\n#define R_X86_64_COPY\t\t5\t/* Copy symbol at runtime */\n#define R_X86_64_GLOB_DAT\t6\t/* Create GOT entry */\n#define R_X86_64_JUMP_SLOT\t7\t/* Create PLT entry */\n#define R_X86_64_RELATIVE\t8\t/* Adjust by program base */\n#define R_X86_64_GOTPCREL\t9\t/* 32 bit signed PC relative\n\t\t\t\t\t   offset to GOT */\n#define R_X86_64_32\t\t10\t/* Direct 32 bit zero extended */\n#define R_X86_64_32S\t\t11\t/* Direct 32 bit sign extended */\n#define R_X86_64_16\t\t12\t/* Direct 16 bit zero extended */\n#define R_X86_64_PC16\t\t13\t/* 16 bit sign extended pc relative */\n#define R_X86_64_8\t\t14\t/* Direct 8 bit sign extended  */\n#define R_X86_64_PC8\t\t15\t/* 8 bit sign extended pc relative */\n#define R_X86_64_DTPMOD64\t16\t/* ID of module containing symbol */\n#define R_X86_64_DTPOFF64\t17\t/* Offset in module's TLS block */\n#define R_X86_64_TPOFF64\t18\t/* Offset in initial TLS block */\n#define R_X86_64_TLSGD\t\t19\t/* 32 bit signed PC relative offset\n\t\t\t\t\t   to two GOT entries for GD symbol */\n#define R_X86_64_TLSLD\t\t20\t/* 32 bit signed PC relative offset\n\t\t\t\t\t   to two GOT entries for LD symbol */\n#define R_X86_64_DTPOFF32\t21\t/* Offset in TLS block */\n#define R_X86_64_GOTTPOFF\t22\t/* 32 bit signed PC relative offset\n\t\t\t\t\t   to GOT entry for IE symbol */\n#define R_X86_64_TPOFF32\t23\t/* Offset in initial TLS block */\n\n#define R_X86_64_NUM\t\t24\n\n\n/* AM33 relocations.  */\n#define R_MN10300_NONE\t\t0\t/* No reloc.  */\n#define R_MN10300_32\t\t1\t/* Direct 32 bit.  */\n#define R_MN10300_16\t\t2\t/* Direct 16 bit.  */\n#define R_MN10300_8\t\t3\t/* Direct 8 bit.  */\n#define R_MN10300_PCREL32\t4\t/* PC-relative 32-bit.  */\n#define R_MN10300_PCREL16\t5\t/* PC-relative 16-bit signed.  */\n#define R_MN10300_PCREL8\t6\t/* PC-relative 8-bit signed.  */\n#define R_MN10300_GNU_VTINHERIT\t7\t/* Ancient C++ vtable garbage... */\n#define R_MN10300_GNU_VTENTRY\t8\t/* ... collection annotation.  */\n#define R_MN10300_24\t\t9\t/* Direct 24 bit.  */\n#define R_MN10300_GOTPC32\t10\t/* 32-bit PCrel offset to GOT.  */\n#define R_MN10300_GOTPC16\t11\t/* 16-bit PCrel offset to GOT.  */\n#define R_MN10300_GOTOFF32\t12\t/* 32-bit offset from GOT.  */\n#define R_MN10300_GOTOFF24\t13\t/* 24-bit offset from GOT.  */\n#define R_MN10300_GOTOFF16\t14\t/* 16-bit offset from GOT.  */\n#define R_MN10300_PLT32\t\t15\t/* 32-bit PCrel to PLT entry.  */\n#define R_MN10300_PLT16\t\t16\t/* 16-bit PCrel to PLT entry.  */\n#define R_MN10300_GOT32\t\t17\t/* 32-bit offset to GOT entry.  */\n#define R_MN10300_GOT24\t\t18\t/* 24-bit offset to GOT entry.  */\n#define R_MN10300_GOT16\t\t19\t/* 16-bit offset to GOT entry.  */\n#define R_MN10300_COPY\t\t20\t/* Copy symbol at runtime.  */\n#define R_MN10300_GLOB_DAT\t21\t/* Create GOT entry.  */\n#define R_MN10300_JMP_SLOT\t22\t/* Create PLT entry.  */\n#define R_MN10300_RELATIVE\t23\t/* Adjust by program base.  */\n\n#define R_MN10300_NUM\t\t24\n\n\n/* M32R relocs.  */\n#define R_M32R_NONE\t\t0\t/* No reloc. */\n#define R_M32R_16\t\t1\t/* Direct 16 bit. */\n#define R_M32R_32\t\t2\t/* Direct 32 bit. */\n#define R_M32R_24\t\t3\t/* Direct 24 bit. */\n#define R_M32R_10_PCREL\t\t4\t/* PC relative 10 bit shifted. */\n#define R_M32R_18_PCREL\t\t5\t/* PC relative 18 bit shifted. */\n#define R_M32R_26_PCREL\t\t6\t/* PC relative 26 bit shifted. */\n#define R_M32R_HI16_ULO\t\t7\t/* High 16 bit with unsigned low. */\n#define R_M32R_HI16_SLO\t\t8\t/* High 16 bit with signed low. */\n#define R_M32R_LO16\t\t9\t/* Low 16 bit. */\n#define R_M32R_SDA16\t\t10\t/* 16 bit offset in SDA. */\n#define R_M32R_GNU_VTINHERIT\t11\n#define R_M32R_GNU_VTENTRY\t12\n/* M32R relocs use SHT_RELA.  */\n#define R_M32R_16_RELA\t\t33\t/* Direct 16 bit. */\n#define R_M32R_32_RELA\t\t34\t/* Direct 32 bit. */\n#define R_M32R_24_RELA\t\t35\t/* Direct 24 bit. */\n#define R_M32R_10_PCREL_RELA\t36\t/* PC relative 10 bit shifted. */\n#define R_M32R_18_PCREL_RELA\t37\t/* PC relative 18 bit shifted. */\n#define R_M32R_26_PCREL_RELA\t38\t/* PC relative 26 bit shifted. */\n#define R_M32R_HI16_ULO_RELA\t39\t/* High 16 bit with unsigned low */\n#define R_M32R_HI16_SLO_RELA\t40\t/* High 16 bit with signed low */\n#define R_M32R_LO16_RELA\t41\t/* Low 16 bit */\n#define R_M32R_SDA16_RELA\t42\t/* 16 bit offset in SDA */\n#define R_M32R_RELA_GNU_VTINHERIT\t43\n#define R_M32R_RELA_GNU_VTENTRY\t44\n#define R_M32R_REL32\t\t45\t/* PC relative 32 bit */\n\n#define R_M32R_GOT24\t\t48\t/* 24 bit GOT entry */\n#define R_M32R_26_PLTREL\t49\t/* 26 bit PC relative to PLT shifted */\n#define R_M32R_COPY\t\t50\t/* Copy symbol at runtime */\n#define R_M32R_GLOB_DAT\t\t51\t/* Create GOT entry */\n#define R_M32R_JMP_SLOT\t\t52\t/* Create PLT entry */\n#define R_M32R_RELATIVE\t\t53\t/* Adjust by program base */\n#define R_M32R_GOTOFF\t\t54\t/* 24 bit offset to GOT */\n#define R_M32R_GOTPC24\t\t55\t/* 24 bit PC relative offset to GOT */\n#define R_M32R_GOT16_HI_ULO\t56\t/* High 16 bit GOT entry with unsigned\n\t\t\t\t\t   low */\n#define R_M32R_GOT16_HI_SLO\t57\t/* High 16 bit GOT entry with signed\n\t\t\t\t\t   low */\n#define R_M32R_GOT16_LO\t\t58\t/* Low 16 bit GOT entry */\n#define R_M32R_GOTPC_HI_ULO\t59\t/* High 16 bit PC relative offset to\n\t\t\t\t\t   GOT with unsigned low */\n#define R_M32R_GOTPC_HI_SLO\t60\t/* High 16 bit PC relative offset to\n\t\t\t\t\t   GOT with signed low */\n#define R_M32R_GOTPC_LO\t\t61\t/* Low 16 bit PC relative offset to\n\t\t\t\t\t   GOT */\n#define R_M32R_GOTOFF_HI_ULO\t62\t/* High 16 bit offset to GOT\n\t\t\t\t\t   with unsigned low */\n#define R_M32R_GOTOFF_HI_SLO\t63\t/* High 16 bit offset to GOT\n\t\t\t\t\t   with signed low */\n#define R_M32R_GOTOFF_LO\t64\t/* Low 16 bit offset to GOT */\n#define R_M32R_NUM\t\t256\t/* Keep this the last entry. */\n\n\n__END_DECLS\n\n#endif\t/* elf.h */\n"
  },
  {
    "path": "tools/mklibs/patches/001-compile.patch",
    "content": "--- a/configure.ac\n+++ b/configure.ac\n@@ -1,4 +1,4 @@\n-AC_INIT([mklibs],m4_esyscmd(dpkg-parsechangelog | perl -ne 'print $1 if m/^Version: (.*)$/;'))\n+AC_INIT([mklibs],m4_esyscmd([head -n1 debian/changelog | awk -F'[\\\\\\\\(\\\\\\\\)]' '{ print $2 }' | xargs -I{} echo -n {}]))\n AM_INIT_AUTOMAKE([foreign no-define])\n AC_CONFIG_HEADERS([config.h])\n AM_MAINTAINER_MODE\n"
  },
  {
    "path": "tools/mklibs/patches/002-disable_symbol_checks.patch",
    "content": "--- a/src/mklibs\n+++ b/src/mklibs\n@@ -533,7 +533,7 @@ while 1:\n         # No progress in last pass. Verify all remaining symbols are weak.\n         for name in unresolved:\n             if not needed_symbols[name].weak:\n-                raise Exception(\"Unresolvable symbol %s\" % name)\n+                print(\"WARNING: Unresolvable symbol %s\" % name)\n         break\n \n     previous_pass_unresolved = unresolved\n@@ -568,7 +568,7 @@ while 1:\n     for name in needed_symbols:\n         if not name in symbol_provider:\n             if not needed_symbols[name].weak:\n-                raise Exception(\"No library provides non-weak %s\" % name)\n+                print(\"WARNING: Unresolvable symbol %s\" % name)\n         else:\n             lib = symbol_provider[name]\n             library_symbols_used[lib].add(library_symbols[lib][name])\n"
  },
  {
    "path": "tools/mklibs/patches/003-no_copy.patch",
    "content": "--- a/src/mklibs\n+++ b/src/mklibs\n@@ -472,7 +472,7 @@ while 1:\n     passnr = passnr + 1\n     # Gather all already reduced libraries and treat them as objects as well\n     small_libs = []\n-    for lib in regexpfilter(os.listdir(dest_path), \"(.*-so-stripped)$\"):\n+    for lib in regexpfilter(os.listdir(dest_path), \"(.*-so)$\"):\n         obj = dest_path + \"/\" + lib\n         small_libs.append(obj)\n         inode = os.stat(obj)[ST_INO]\n@@ -588,12 +588,7 @@ while 1:\n         if not so_file:\n             sys.exit(\"File not found:\" + library)\n         pic_file = find_pic(library)\n-        if not pic_file:\n-            # No pic file, so we have to use the .so file, no reduction\n-            debug(DEBUG_VERBOSE, \"No pic file found for\", so_file, \"; copying\")\n-            command(target + \"objcopy\", \"--strip-unneeded -R .note -R .comment\",\n-                    so_file, dest_path + \"/\" + so_file_name + \"-so-stripped\")\n-        else:\n+        if pic_file:\n             # we have a pic file, recompile\n             debug(DEBUG_SPAM, \"extracting from:\", pic_file, \"so_file:\", so_file)\n             soname = extract_soname(so_file)\n@@ -636,22 +631,14 @@ while 1:\n             cmd.append(library_depends_gcc_libnames(so_file))\n             command(target + \"gcc\", *cmd)\n \n-            # strip result\n-            command(target + \"objcopy\", \"--strip-unneeded -R .note -R .comment\",\n-                      dest_path + \"/\" + so_file_name + \"-so\",\n-                      dest_path + \"/\" + so_file_name + \"-so-stripped\")\n             ## DEBUG\n             debug(DEBUG_VERBOSE, so_file, \"\\t\", str(os.stat(so_file)[ST_SIZE]))\n             debug(DEBUG_VERBOSE, dest_path + \"/\" + so_file_name + \"-so\", \"\\t\",\n                   str(os.stat(dest_path + \"/\" + so_file_name + \"-so\")[ST_SIZE]))\n-            debug(DEBUG_VERBOSE, dest_path + \"/\" + so_file_name + \"-so-stripped\",\n-                  \"\\t\", str(os.stat(dest_path + \"/\" + so_file_name + \"-so-stripped\")[ST_SIZE]))\n \n # Finalising libs and cleaning up\n-for lib in regexpfilter(os.listdir(dest_path), \"(.*)-so-stripped$\"):\n-    os.rename(dest_path + \"/\" + lib + \"-so-stripped\", dest_path + \"/\" + lib)\n-for lib in regexpfilter(os.listdir(dest_path), \"(.*-so)$\"):\n-    os.remove(dest_path + \"/\" + lib)\n+for lib in regexpfilter(os.listdir(dest_path), \"(.*)-so$\"):\n+    os.rename(dest_path + \"/\" + lib + \"-so\", dest_path + \"/\" + lib)\n \n # Canonicalize library names.\n for lib in sorted(regexpfilter(os.listdir(dest_path), \"(.*so[.\\d]*)$\")):\n"
  },
  {
    "path": "tools/mklibs/patches/004-libpthread_link.patch",
    "content": "--- a/src/mklibs\n+++ b/src/mklibs\n@@ -106,14 +106,14 @@ def library_depends(obj):\n \n # Return a list of libraries the passed objects depend on. The\n # libraries are in \"-lfoo\" format suitable for passing to gcc.\n-def library_depends_gcc_libnames(obj):\n+def library_depends_gcc_libnames(obj, soname):\n     if not os.access(obj, os.F_OK):\n         raise Exception(\"Cannot find lib: \" + obj)\n     libs = library_depends(obj)\n     ret = []\n     for i in libs:\n         match = re.match(\"^(((?P<ld>ld\\S*)|(lib(?P<lib>\\S+))))\\.so.*$\", i)\n-        if match:\n+        if match and not soname in (\"libpthread.so.0\"):\n             if match.group('ld'):\n                 ret.append(find_lib(match.group(0)))\n             elif match.group('lib'):\n@@ -628,7 +628,7 @@ while 1:\n             cmd.extend(extra_flags)\n             cmd.append(\"-lgcc\")\n             cmd.extend([\"-L%s\" % a for a in [dest_path] + [sysroot + b for b in lib_path if sysroot == \"\" or b not in (\"/\" + libdir + \"/\", \"/usr/\" + libdir + \"/\")]])\n-            cmd.append(library_depends_gcc_libnames(so_file))\n+            cmd.append(library_depends_gcc_libnames(so_file, soname))\n             command(target + \"gcc\", *cmd)\n \n             ## DEBUG\n"
  },
  {
    "path": "tools/mklibs/patches/005-duplicate_syms.patch",
    "content": "--- a/src/mklibs\n+++ b/src/mklibs\n@@ -540,7 +540,6 @@ while 1:\n \n     library_symbols = {}\n     library_symbols_used = {}\n-    symbol_provider = {}\n \n     # WORKAROUND: Always add libgcc on old-abi arm\n     header = elf_header(find_lib(libraries.copy().pop()))\n@@ -558,20 +557,13 @@ while 1:\n         library_symbols_used[library] = set()\n         for symbol in symbols:\n             for name in symbol.base_names():\n-                if name in symbol_provider:\n-                    debug(DEBUG_SPAM, \"duplicate symbol %s in %s and %s\" % (symbol, symbol_provider[name], library))\n-                else:\n-                    library_symbols[library][name] = symbol\n-                    symbol_provider[name] = library\n+                library_symbols[library][name] = symbol\n \n     # which symbols are actually used from each lib\n     for name in needed_symbols:\n-        if not name in symbol_provider:\n-            if not needed_symbols[name].weak:\n-                print(\"WARNING: Unresolvable symbol %s\" % name)\n-        else:\n-            lib = symbol_provider[name]\n-            library_symbols_used[lib].add(library_symbols[lib][name])\n+        for lib in libraries:\n+            if name in library_symbols[lib]:\n+                library_symbols_used[lib].add(library_symbols[lib][name])\n \n     # reduce libraries\n     for library in sorted(libraries):\n"
  },
  {
    "path": "tools/mklibs/patches/007-gc_sections.patch",
    "content": "--- a/src/mklibs\n+++ b/src/mklibs\n@@ -611,7 +611,7 @@ while 1:\n             # compile in only used symbols\n             cmd = []\n             cmd.extend(gcc_options)\n-            cmd.append(\"-nostdlib -nostartfiles -shared -Wl,-soname=\" + soname)\n+            cmd.append(\"-nostdlib -nostartfiles -shared -Wl,--gc-sections -Wl,-soname=\" + soname)\n             cmd.extend([\"-u%s\" % a.linker_name() for a in symbols])\n             cmd.extend([\"-o\", dest_path + \"/\" + so_file_name + \"-so\"])\n             cmd.extend(extra_pre_obj)\n"
  },
  {
    "path": "tools/mklibs/patches/008-uclibc_libgcc_link.patch",
    "content": "--- a/src/mklibs\n+++ b/src/mklibs\n@@ -113,11 +113,8 @@ def library_depends_gcc_libnames(obj, so\n     ret = []\n     for i in libs:\n         match = re.match(\"^(((?P<ld>ld\\S*)|(lib(?P<lib>\\S+))))\\.so.*$\", i)\n-        if match and not soname in (\"libpthread.so.0\"):\n-            if match.group('ld'):\n-                ret.append(find_lib(match.group(0)))\n-            elif match.group('lib'):\n-                ret.append('-l%s' % match.group('lib'))\n+        if match:\n+            ret.append(find_lib(match.group(0)))\n     return ' '.join(ret)\n \n class Symbol(object):\n@@ -593,6 +590,7 @@ while 1:\n             extra_flags = []\n             extra_pre_obj = []\n             extra_post_obj = []\n+            libgcc_link = find_lib(\"libgcc_s.so.1\")\n \n             symbols.update(library_symbols_used[library])\n \n@@ -618,9 +616,10 @@ while 1:\n             cmd.append(pic_file)\n             cmd.extend(extra_post_obj)\n             cmd.extend(extra_flags)\n-            cmd.append(\"-lgcc\")\n             cmd.extend([\"-L%s\" % a for a in [dest_path] + [sysroot + b for b in lib_path if sysroot == \"\" or b not in (\"/\" + libdir + \"/\", \"/usr/\" + libdir + \"/\")]])\n-            cmd.append(library_depends_gcc_libnames(so_file, soname))\n+            if soname != \"libgcc_s.so.1\":\n+                cmd.append(library_depends_gcc_libnames(so_file, soname))\n+                cmd.append(libgcc_link)\n             command(target + \"gcc\", *cmd)\n \n             ## DEBUG\n"
  },
  {
    "path": "tools/mklibs/patches/010-remove_STT_GNU_IFUNC.patch",
    "content": "--- a/src/mklibs-readelf/main.cpp\n+++ b/src/mklibs-readelf/main.cpp\n@@ -84,7 +84,7 @@ static void process_symbols_provided (co\n       continue;\n     if (shndx == SHN_UNDEF || shndx == SHN_ABS)\n       continue;\n-    if (type != STT_NOTYPE && type != STT_OBJECT && type != STT_FUNC && type != STT_GNU_IFUNC && type != STT_COMMON && type != STT_TLS)\n+    if (type != STT_NOTYPE && type != STT_OBJECT && type != STT_FUNC && type != STT_COMMON && type != STT_TLS)\n       continue;\n     if (!name.size())\n       continue;\n@@ -115,7 +115,7 @@ static void process_symbols_undefined (c\n       continue;\n     if (shndx != SHN_UNDEF)\n       continue;\n-    if (type != STT_NOTYPE && type != STT_OBJECT && type != STT_FUNC && type != STT_GNU_IFUNC && type != STT_COMMON && type != STT_TLS)\n+    if (type != STT_NOTYPE && type != STT_OBJECT && type != STT_FUNC && type != STT_COMMON && type != STT_TLS)\n       continue;\n     if (!name.size())\n       continue;\n"
  },
  {
    "path": "tools/mklibs/patches/011-remove_multiarch.patch",
    "content": "--- a/src/mklibs\n+++ b/src/mklibs\n@@ -269,6 +269,7 @@ def extract_soname(so_file):\n     return \"\"\n \n def multiarch(paths):\n+    return paths\n     devnull = open('/dev/null', 'w')\n     dpkg_architecture = subprocess.Popen(\n         ['dpkg-architecture', '-qDEB_HOST_MULTIARCH'],\n"
  },
  {
    "path": "tools/mklibs/patches/100-apply-2to3.patch",
    "content": "--- a/src/mklibs\n+++ b/src/mklibs\n@@ -57,17 +57,17 @@ debuglevel = DEBUG_NORMAL\n \n def debug(level, *msg):\n     if debuglevel >= level:\n-        print(string.join(msg))\n+        print(' '.join(msg))\n \n # return a list of lines of output of the command\n def command(command, *args):\n-    debug(DEBUG_SPAM, \"calling\", command, string.join(args))\n+    debug(DEBUG_SPAM, \"calling\", command, ' '.join(args))\n     pipe = os.popen(command + ' ' + ' '.join(args), 'r')\n     output = pipe.read().strip()\n     status = pipe.close() \n     if status is not None and os.WEXITSTATUS(status) != 0:\n         print(\"Command failed with status\", os.WEXITSTATUS(status),  \":\", \\\n-               command, string.join(args))\n+               command, ' '.join(args))\n         print(\"With output:\", output)\n         sys.exit(1)\n     return [i for i in output.split('\\n') if i]\n@@ -296,7 +296,7 @@ def usage(was_err):\n     print(\"Make a set of minimal libraries for FILE(s, file=outfd) in DEST.\", file=outfd)\n     print(\"\" , file=outfd)\n     print(\"  -d, --dest-dir DIRECTORY     create libraries in DIRECTORY\", file=outfd)\n-    print(\"  -D, --no-default-lib         omit default libpath (\", ':'.join(default_lib_path, file=outfd), \", file=outfd)\", file=outfd)\n+    print(\"  -D, --no-default-lib         omit default libpath (\", ':'.join(default_lib_path), \")\", file=outfd)\n     print(\"  -L DIRECTORY[:DIRECTORY]...  add DIRECTORY(s, file=outfd) to the library search path\", file=outfd)\n     print(\"  -l LIBRARY                   add LIBRARY always\", file=outfd)\n     print(\"      --ldlib LDLIB            use LDLIB for the dynamic linker\", file=outfd)\n@@ -372,7 +372,7 @@ for opt, arg in optlist:\n         if debuglevel < DEBUG_SPAM:\n             debuglevel = debuglevel + 1\n     elif opt == \"-L\":\n-        lib_path.extend(string.split(arg, \":\"))\n+        lib_path.extend(arg.split(\":\"))\n     elif opt in (\"-d\", \"--dest-dir\"):\n         dest_path = arg\n     elif opt in (\"-D\", \"--no-default-lib\"):\n@@ -391,7 +391,7 @@ for opt, arg in optlist:\n     elif opt in (\"-l\",):\n         force_libs.append(arg)\n     elif opt == \"--gcc-options\":\n-        gcc_options.extend(string.split(arg, \" \"))\n+        gcc_options.extend(arg.split(\" \"))\n     elif opt == \"--libdir\":\n         libdir = arg\n     elif opt in (\"--help\", \"-h\"):\n@@ -419,17 +419,17 @@ if ldlib == \"LDLIB\":\n objects = {}  # map from inode to filename\n for prog in proglist:\n     inode = os.stat(prog)[ST_INO]\n-    if objects.has_key(inode):\n+    if inode in objects:\n         debug(DEBUG_SPAM, prog, \"is a hardlink to\", objects[inode])\n     elif so_pattern.match(prog):\n         debug(DEBUG_SPAM, prog, \"is a library\")\n-    elif script_pattern.match(open(prog).read(256)):\n+    elif script_pattern.match(open(prog, 'r', encoding='iso-8859-1').read(256)):\n         debug(DEBUG_SPAM, prog, \"is a script\")\n     else:\n         objects[inode] = prog\n \n if not ldlib:\n-    for obj in objects.values():\n+    for obj in list(objects.values()):\n         output = command(\"mklibs-readelf\", \"--print-interp\", obj)\n         if output:\n             ldlib = output.pop()\n@@ -462,9 +462,9 @@ previous_pass_unresolved = set()\n while 1:\n     debug(DEBUG_NORMAL, \"I: library reduction pass\", str(passnr))\n     if debuglevel >= DEBUG_VERBOSE:\n-        print(\"Objects:\",)\n-        for obj in sorted([x[string.rfind(x, '/') + 1:] for x in objects.values()]):\n-            print(obj,)\n+        print(\"Objects:\", end=' ')\n+        for obj in sorted([x[x.rfind('/') + 1:] for x in list(objects.values())]):\n+            print(obj, end=' ')\n         print()\n \n     passnr = passnr + 1\n@@ -474,7 +474,7 @@ while 1:\n         obj = dest_path + \"/\" + lib\n         small_libs.append(obj)\n         inode = os.stat(obj)[ST_INO]\n-        if objects.has_key(inode):\n+        if inode in objects:\n             debug(DEBUG_SPAM, obj, \"is hardlink to\", objects[inode])\n         else:\n             objects[inode] = obj\n@@ -504,7 +504,7 @@ while 1:\n     present_symbols = {}\n     checked_libs = small_libs\n     checked_libs.extend(available_libs)\n-    checked_libs.append(ldlib)\n+    checked_libs.append(sysroot + \"/\" + ldlib)\n     for lib in checked_libs:\n         for symbol in provided_symbols(lib):\n             debug(DEBUG_SPAM, \"present_symbols adding %s\" % symbol)\n--- a/src/mklibs-copy\n+++ b/src/mklibs-copy\n@@ -159,7 +159,7 @@ if include_default_lib_path:\n objects = {}  # map from inode to filename\n for prog in proglist:\n     inode = os.stat(prog)[ST_INO]\n-    if objects.has_key(inode):\n+    if inode in objects:\n         logger.debug(\"%s is a hardlink to %s\", prog, objects[inode])\n     elif so_pattern.match(prog):\n         logger.debug(\"%s is a library\", prog)\n@@ -169,7 +169,7 @@ for prog in proglist:\n         logger.debug(\"%s is no ELF\", prog)\n \n if not ldlib:\n-    for obj in objects.values():\n+    for obj in list(objects.values()):\n         output = command(\"mklibs-readelf\", \"-i\", obj)\n         for x in output:\n                 ldlib = x\n@@ -182,7 +182,7 @@ if not ldlib:\n logger.info('Using %s as dynamic linker', ldlib)\n \n # Check for rpaths\n-for obj in objects.values():\n+for obj in list(objects.values()):\n     rpath_val = rpath(obj)\n     if rpath_val:\n         if root:\n@@ -208,18 +208,18 @@ while 1:\n         obj = dest_path + \"/\" + lib\n         small_libs.append(obj)\n         inode = os.stat(obj)[ST_INO]\n-        if objects.has_key(inode):\n+        if inode in objects:\n             logger.debug(\"%s is hardlink to %s\", obj, objects[inode])\n         else:\n             objects[inode] = obj\n \n-    for obj in objects.values():\n+    for obj in list(objects.values()):\n         small_libs.append(obj)\n \n-    logger.verbose('Objects: %r', ' '.join([i[i.rfind('/') + 1:] for i in objects.itervalues()]))\n+    logger.verbose('Objects: %r', ' '.join([i[i.rfind('/') + 1:] for i in objects.values()]))\n \n     libraries = set()\n-    for obj in objects.values():\n+    for obj in list(objects.values()):\n         libraries.update(library_depends(obj))\n \n     if libraries == previous_pass_libraries:\n"
  },
  {
    "path": "tools/mpc/Makefile",
    "content": "#\n# Copyright (C) 2009-2015 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=mpc\nPKG_VERSION:=1.2.1\n\nPKG_SOURCE_URL:=@GNU/mpc/\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz\nPKG_HASH:=17503d2c395dfcf106b622dc142683c1199431d095367c6aacba6eec30340459\n\nHOST_BUILD_PARALLEL:=1\n\ninclude $(INCLUDE_DIR)/host-build.mk\n\nunexport CFLAGS\n\nHOST_CONFIGURE_ARGS += \\\n\t--enable-static \\\n\t--disable-shared \\\n\t--with-mpfr=$(TOPDIR)/staging_dir/host \\\n\t--with-gmp=$(TOPDIR)/staging_dir/host\n\n$(eval $(call HostBuild))\n"
  },
  {
    "path": "tools/mpfr/Makefile",
    "content": "#\n# Copyright (C) 2009-2016 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=mpfr\nPKG_VERSION:=4.1.0\nPKG_CPE_ID:=cpe:/a:mpfr:gnu_mpfr\n\nPKG_SOURCE_URL:=@GNU/mpfr http://www.mpfr.org/mpfr-$(PKG_VERSION)\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz\nPKG_HASH:=0c98a3f1732ff6ca4ea690552079da9c597872d30e96ec28414ee23c95558a7f\n\nHOST_BUILD_PARALLEL:=1\nHOST_FIXUP:=autoreconf\n\ninclude $(INCLUDE_DIR)/host-build.mk\n\nHOST_CONFIGURE_ARGS += \\\n\t--enable-static \\\n\t--disable-shared \\\n\t--enable-thread-safe \\\n\t--with-gmp=$(STAGING_DIR_HOST)\n\n$(eval $(call HostBuild))\n"
  },
  {
    "path": "tools/mpfr/patches/001-only_src.patch",
    "content": "--- a/Makefile.am\n+++ b/Makefile.am\n@@ -24,7 +24,7 @@ AUTOMAKE_OPTIONS = gnu\n # old Automake version.\n ACLOCAL_AMFLAGS = -I m4\n \n-SUBDIRS = doc src tests tune tools/bench\n+SUBDIRS = src\n \n pkgconfigdir = $(libdir)/pkgconfig\n pkgconfig_DATA = mpfr.pc\n--- a/Makefile.in\n+++ b/Makefile.in\n@@ -384,7 +384,7 @@ AUTOMAKE_OPTIONS = gnu\n # libtoolize and in case some developer needs to switch back to an\n # old Automake version.\n ACLOCAL_AMFLAGS = -I m4\n-SUBDIRS = doc src tests tune tools/bench\n+SUBDIRS = src\n pkgconfigdir = $(libdir)/pkgconfig\n pkgconfig_DATA = mpfr.pc\n nobase_dist_doc_DATA = AUTHORS BUGS COPYING COPYING.LESSER NEWS TODO \\\n"
  },
  {
    "path": "tools/mpfr/patches/100-freebsd-compat.patch",
    "content": "--- a/src/vasprintf.c\n+++ b/src/vasprintf.c\n@@ -72,6 +72,7 @@ https://www.gnu.org/licenses/ or write t\n #endif /* HAVE_VA_COPY */\n \n #ifdef HAVE_WCHAR_H\n+#include <stddef.h>\n #include <wchar.h>\n #endif\n \n"
  },
  {
    "path": "tools/mtd-utils/Makefile",
    "content": "#\n# Copyright (C) 2006-2015 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=mtd-utils\nPKG_VERSION:=2.1.2\nPKG_RELEASE:=1\n\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.bz2\nPKG_SOURCE_URL:=ftp://ftp.infradead.org/pub/mtd-utils/\nPKG_HASH:=8ad4c5f34716d40646aa28724a2f5616d325a6f119254f914e26976f1f76e9d6\n\nPKG_FIXUP:=autoreconf\n\ninclude $(INCLUDE_DIR)/host-build.mk\n\nifneq ($(HOST_OS),Linux)\n  HOST_CFLAGS += \\\n\t-I$(CURDIR)/include \\\n\t-Dloff_t=off_t \\\n\t-D__BYTE_ORDER=BYTE_ORDER \\\n\t-include endian.h \\\n\t-DNO_NATIVE_SUPPORT \\\n\t-include fls.h\nendif\n\nHOST_CONFIGURE_VARS+= \\\n\tUUID_CFLAGS=\"-I$(STAGING_DIR_HOST)/include/e2fsprogs/uuid\"\n\nHOST_CONFIGURE_ARGS+= \\\n\t--disable-tests \\\n\t--without-crypto \\\n\t--without-xattr \\\n\t--without-zstd \\\n\t--without-lzo\n\nHOST_MAKE_FLAGS += \\\n\tPROGRAMS=\"mkfs.jffs2 ubinize mkfs.ubifs\"\n\ndefine Host/Install\n\t$(CP) \\\n\t\t$(HOST_BUILD_DIR)/mkfs.jffs2 \\\n\t\t$(HOST_BUILD_DIR)/mkfs.ubifs \\\n\t\t$(HOST_BUILD_DIR)/ubinize \\\n\t\t$(STAGING_DIR_HOST)/bin/\nendef\n\ndefine Host/Clean\n\trm -f $(STAGING_DIR_HOST)/bin/{mkfs.jffs2,mkfs.ubifs,ubinize}\nendef\n\n$(eval $(call HostBuild))\n"
  },
  {
    "path": "tools/mtd-utils/include/fls.h",
    "content": "#include <string.h>\n#define fls local_fls\n"
  },
  {
    "path": "tools/mtd-utils/include/linux/types.h",
    "content": "#ifndef _LINUX_TYPES_H\n#define _LINUX_TYPES_H\n\n#include <mtd/ubi-media.h>\n\ntypedef uint16_t __u16;\ntypedef uint32_t __u32;\ntypedef uint64_t __u64;\n\ntypedef __u16 __le16;\ntypedef __u32 __le32;\ntypedef __u64 __le64;\ntypedef __u64 off64_t;\n\ntypedef __u16  __sum16;\ntypedef __u32  __wsum;\n\n#endif /* _LINUX_TYPES_H */\n"
  },
  {
    "path": "tools/mtd-utils/patches/100-sscanf_fix.patch",
    "content": "--- a/jffsX-utils/mkfs.jffs2.c\n+++ b/jffsX-utils/mkfs.jffs2.c\n@@ -428,7 +428,7 @@ static int interpret_table_entry(struct\n \n \tif (sscanf (line, \"%\" SCANF_PREFIX \"s %c %lo %lu %lu %lu %lu %lu %lu %lu\",\n \t\t\t\tSCANF_STRING(name), &type, &mode, &uid, &gid, &major, &minor,\n-\t\t\t\t&start, &increment, &count) < 0)\n+\t\t\t\t&start, &increment, &count) < 10)\n \t{\n \t\treturn 1;\n \t}\n"
  },
  {
    "path": "tools/mtd-utils/patches/110-portability.patch",
    "content": "--- a/jffsX-utils/compr_lzo.c\n+++ b/jffsX-utils/compr_lzo.c\n@@ -26,7 +26,6 @@\n #include <string.h>\n \n #ifndef WITHOUT_LZO\n-#include <asm/types.h>\n #include <linux/jffs2.h>\n #include <lzo/lzo1x.h>\n #include \"compr.h\"\n--- a/jffsX-utils/compr_zlib.c\n+++ b/jffsX-utils/compr_zlib.c\n@@ -39,7 +39,6 @@\n #include <zlib.h>\n #undef crc32\n #include <stdio.h>\n-#include <asm/types.h>\n #include <linux/jffs2.h>\n #include \"common.h\"\n #include \"compr.h\"\n--- a/jffsX-utils/rbtree.h\n+++ b/jffsX-utils/rbtree.h\n@@ -94,8 +94,7 @@ static inline struct page * rb_insert_pa\n #ifndef\t_LINUX_RBTREE_H\n #define\t_LINUX_RBTREE_H\n \n-#include <linux/kernel.h>\n-#include <linux/stddef.h>\n+#include <stddef.h>\n \n struct rb_node\n {\n--- a/include/mtd/ubi-media.h\n+++ b/include/mtd/ubi-media.h\n@@ -30,7 +30,15 @@\n #ifndef __UBI_MEDIA_H__\n #define __UBI_MEDIA_H__\n \n+#ifdef __linux__\n #include <asm/byteorder.h>\n+#else\n+#include <stdint.h>\n+typedef uint8_t __u8;\n+typedef uint16_t __be16;\n+typedef uint32_t __be32;\n+typedef uint64_t __be64;\n+#endif\n \n /* The version of UBI images supported by this implementation */\n #define UBI_VERSION 1\n--- a/ubifs-utils/mkfs.ubifs/mkfs.ubifs.h\n+++ b/ubifs-utils/mkfs.ubifs/mkfs.ubifs.h\n@@ -32,7 +32,17 @@\n #include <endian.h>\n #include <byteswap.h>\n #include <linux/types.h>\n+#ifdef __linux__\n #include <linux/fs.h>\n+# if defined(__x86_64__) && defined(__ILP32__)\n+#  define llseek lseek64\n+# endif\n+#else\n+# ifndef O_LARGEFILE\n+#  define O_LARGEFILE 0\n+# endif\n+# define llseek lseek\n+#endif\n \n #include <getopt.h>\n #include <sys/types.h>\n--- a/ubifs-utils/mkfs.ubifs/mkfs.ubifs.c\n+++ b/ubifs-utils/mkfs.ubifs/mkfs.ubifs.c\n@@ -1549,6 +1549,7 @@ static int add_inode(struct stat *st, in\n \n \tif (c->default_compr != UBIFS_COMPR_NONE)\n \t\tuse_flags |= UBIFS_COMPR_FL;\n+#ifndef NO_NATIVE_SUPPORT\n \tif (flags & FS_COMPR_FL)\n \t\tuse_flags |= UBIFS_COMPR_FL;\n \tif (flags & FS_SYNC_FL)\n@@ -1561,6 +1562,7 @@ static int add_inode(struct stat *st, in\n \t\tuse_flags |= UBIFS_DIRSYNC_FL;\n \tif (fctx)\n \t\tuse_flags |= UBIFS_CRYPT_FL;\n+#endif\n \tmemset(ino, 0, UBIFS_INO_NODE_SZ);\n \n \tino_key_init(&key, inum);\n@@ -1646,7 +1648,9 @@ static int add_dir_inode(const char *pat\n \t\tfd = dirfd(dir);\n \t\tif (fd == -1)\n \t\t\treturn sys_err_msg(\"dirfd failed\");\n+#ifndef NO_NATIVE_SUPPORT\n \t\tif (ioctl(fd, FS_IOC_GETFLAGS, &flags) == -1)\n+#endif\n \t\t\tflags = 0;\n \t}\n \n@@ -1857,6 +1861,7 @@ static int add_file(const char *path_nam\n \t\tdn->ch.node_type = UBIFS_DATA_NODE;\n \t\tkey_write(&key, &dn->key);\n \t\tout_len = NODE_BUFFER_SIZE - UBIFS_DATA_NODE_SZ;\n+#ifndef NO_NATIVE_SUPPORT\n \t\tif (c->default_compr == UBIFS_COMPR_NONE &&\n \t\t    !c->encrypted && (flags & FS_COMPR_FL))\n #ifdef WITHOUT_LZO\n@@ -1865,6 +1870,7 @@ static int add_file(const char *path_nam\n \t\t\tuse_compr = UBIFS_COMPR_LZO;\n #endif\n \t\telse\n+#endif\n \t\t\tuse_compr = c->default_compr;\n \t\tcompr_type = compress_data(buf, bytes_read, &dn->data,\n \t\t\t\t\t   &out_len, use_compr);\n@@ -1924,7 +1930,9 @@ static int add_non_dir(const char *path_\n \t\tif (fd == -1)\n \t\t\treturn sys_err_msg(\"failed to open file '%s'\",\n \t\t\t\t\t   path_name);\n+#ifndef NO_NATIVE_SUPPORT\n \t\tif (ioctl(fd, FS_IOC_GETFLAGS, &flags) == -1)\n+#endif\n \t\t\tflags = 0;\n \t\tif (close(fd) == -1)\n \t\t\treturn sys_err_msg(\"failed to close file '%s'\",\n--- a/ubifs-utils/mkfs.ubifs/devtable.c\n+++ b/ubifs-utils/mkfs.ubifs/devtable.c\n@@ -135,6 +135,7 @@ static int interpret_table_entry(const c\n \tunsigned int mode = 0755, uid = 0, gid = 0, major = 0, minor = 0;\n \tunsigned int start = 0, increment = 0, count = 0;\n \n+\tbuf[1023] = 0;\n \tif (sscanf(line, \"%1023s %c %o %u %u %u %u %u %u %u\",\n \t\t   buf, &type, &mode, &uid, &gid, &major, &minor,\n \t\t   &start, &increment, &count) < 0)\n@@ -145,10 +146,10 @@ static int interpret_table_entry(const c\n \t\tbuf, type, mode, uid, gid, major, minor, start,\n \t\tincrement, count);\n \n-\tlen = strnlen(buf, 1024);\n+\tlen = strlen(buf);\n \tif (len == 0)\n \t\treturn err_msg(\"empty path\");\n-\tif (len == 1024)\n+\tif (len == 1023)\n \t\treturn err_msg(\"too long path\");\n \n \tif (buf[0] != '/')\n--- a/include/common.h\n+++ b/include/common.h\n@@ -26,7 +26,6 @@\n #include <string.h>\n #include <fcntl.h>\n #include <errno.h>\n-#include <features.h>\n #include <inttypes.h>\n #include <unistd.h>\n #include <sys/sysmacros.h>\n--- a/include/mtd/ubifs-media.h\n+++ b/include/mtd/ubifs-media.h\n@@ -33,7 +33,15 @@\n #ifndef __UBIFS_MEDIA_H__\n #define __UBIFS_MEDIA_H__\n \n+#ifdef __linux__\n #include <asm/byteorder.h>\n+#else\n+#include <stdint.h>\n+typedef uint8_t __u8;\n+typedef uint16_t __be16;\n+typedef uint32_t __be32;\n+typedef uint64_t __be64;\n+#endif\n \n /* UBIFS node magic number (must not have the padding byte first or last) */\n #define UBIFS_NODE_MAGIC  0x06101831\n"
  },
  {
    "path": "tools/mtd-utils/patches/130-lzma_jffs2.patch",
    "content": "--- a/jffsX-utils/Makemodule.am\n+++ b/jffsX-utils/Makemodule.am\n@@ -4,11 +4,19 @@ mkfs_jffs2_SOURCES = \\\n \tjffsX-utils/compr_zlib.c \\\n \tjffsX-utils/compr.h \\\n \tjffsX-utils/rbtree.c \\\n-\tjffsX-utils/compr_lzo.c \\\n+\tjffsX-utils/compr_lzma.c \\\n+\tjffsX-utils/lzma/LzFind.c \\\n+\tjffsX-utils/lzma/LzmaEnc.c \\\n+\tjffsX-utils/lzma/LzmaDec.c \\\n \tjffsX-utils/compr.c \\\n \tjffsX-utils/compr_rtime.c\n+\n+if !WITHOUT_LZO\n+mkfs_jffs2_SOURCES += jffsX-utils/compr_lzo.c\n+endif\n+\n mkfs_jffs2_LDADD = libmtd.a $(ZLIB_LIBS) $(LZO_LIBS)\n-mkfs_jffs2_CPPFLAGS = $(AM_CPPFLAGS) $(ZLIB_CFLAGS) $(LZO_CFLAGS)\n+mkfs_jffs2_CPPFLAGS = $(AM_CPPFLAGS) $(ZLIB_CFLAGS) $(LZO_CFLAGS) -I./include/linux/lzma\n \n jffs2reader_SOURCES = jffsX-utils/jffs2reader.c\n jffs2reader_LDADD = libmtd.a $(ZLIB_LIBS) $(LZO_LIBS)\n--- a/jffsX-utils/compr.c\n+++ b/jffsX-utils/compr.c\n@@ -520,6 +520,9 @@ int jffs2_compressors_init(void)\n #ifdef CONFIG_JFFS2_LZO\n \tjffs2_lzo_init();\n #endif\n+#ifdef CONFIG_JFFS2_LZMA\n+\tjffs2_lzma_init();\n+#endif\n \treturn 0;\n }\n \n@@ -534,5 +537,8 @@ int jffs2_compressors_exit(void)\n #ifdef CONFIG_JFFS2_LZO\n \tjffs2_lzo_exit();\n #endif\n+#ifdef CONFIG_JFFS2_LZMA\n+\tjffs2_lzma_exit();\n+#endif\n \treturn 0;\n }\n--- a/jffsX-utils/compr.h\n+++ b/jffsX-utils/compr.h\n@@ -18,13 +18,14 @@\n \n #define CONFIG_JFFS2_ZLIB\n #define CONFIG_JFFS2_RTIME\n-#define CONFIG_JFFS2_LZO\n+#define CONFIG_JFFS2_LZMA\n \n #define JFFS2_RUBINMIPS_PRIORITY 10\n #define JFFS2_DYNRUBIN_PRIORITY  20\n #define JFFS2_RTIME_PRIORITY     50\n-#define JFFS2_ZLIB_PRIORITY      60\n-#define JFFS2_LZO_PRIORITY       80\n+#define JFFS2_LZMA_PRIORITY      70\n+#define JFFS2_ZLIB_PRIORITY      80\n+#define JFFS2_LZO_PRIORITY       90\n \n #define JFFS2_COMPR_MODE_NONE       0\n #define JFFS2_COMPR_MODE_PRIORITY   1\n@@ -115,5 +116,10 @@ void jffs2_rtime_exit(void);\n int jffs2_lzo_init(void);\n void jffs2_lzo_exit(void);\n #endif\n+#ifdef CONFIG_JFFS2_LZMA\n+int jffs2_lzma_init(void);\n+void jffs2_lzma_exit(void);\n+#endif\n+\n \n #endif /* __JFFS2_COMPR_H__ */\n--- /dev/null\n+++ b/jffsX-utils/compr_lzma.c\n@@ -0,0 +1,128 @@\n+/*\n+ * JFFS2 -- Journalling Flash File System, Version 2.\n+ *\n+ * For licensing information, see the file 'LICENCE' in this directory.\n+ *\n+ * JFFS2 wrapper to the LZMA C SDK\n+ *\n+ */\n+\n+#include <linux/lzma.h>\n+#include \"compr.h\"\n+\n+#ifdef __KERNEL__\n+\tstatic DEFINE_MUTEX(deflate_mutex);\n+#endif\n+\n+CLzmaEncHandle *p;\n+Byte propsEncoded[LZMA_PROPS_SIZE];\n+SizeT propsSize = sizeof(propsEncoded);\n+\n+STATIC void lzma_free_workspace(void)\n+{\n+\tLzmaEnc_Destroy(p, &lzma_alloc, &lzma_alloc);\n+}\n+\n+STATIC int INIT lzma_alloc_workspace(CLzmaEncProps *props)\n+{\n+\tif ((p = (CLzmaEncHandle *)LzmaEnc_Create(&lzma_alloc)) == NULL)\n+\t{\n+\t\tPRINT_ERROR(\"Failed to allocate lzma deflate workspace\\n\");\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\tif (LzmaEnc_SetProps(p, props) != SZ_OK)\n+\t{\n+\t\tlzma_free_workspace();\n+\t\treturn -1;\n+\t}\n+\t\n+\tif (LzmaEnc_WriteProperties(p, propsEncoded, &propsSize) != SZ_OK)\n+\t{\n+\t\tlzma_free_workspace();\n+\t\treturn -1;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+STATIC int jffs2_lzma_compress(unsigned char *data_in, unsigned char *cpage_out,\n+\t\t\t      uint32_t *sourcelen, uint32_t *dstlen)\n+{\n+\tSizeT compress_size = (SizeT)(*dstlen);\n+\tint ret;\n+\n+\t#ifdef __KERNEL__\n+\t\tmutex_lock(&deflate_mutex);\n+\t#endif\n+\n+\tret = LzmaEnc_MemEncode(p, cpage_out, &compress_size, data_in, *sourcelen,\n+\t\t0, NULL, &lzma_alloc, &lzma_alloc);\n+\n+\t#ifdef __KERNEL__\n+\t\tmutex_unlock(&deflate_mutex);\n+\t#endif\n+\n+\tif (ret != SZ_OK)\n+\t\treturn -1;\n+\n+\t*dstlen = (uint32_t)compress_size;\n+\n+\treturn 0;\n+}\n+\n+STATIC int jffs2_lzma_decompress(unsigned char *data_in, unsigned char *cpage_out,\n+\t\t\t\t uint32_t srclen, uint32_t destlen)\n+{\n+\tint ret;\n+\tSizeT dl = (SizeT)destlen;\n+\tSizeT sl = (SizeT)srclen;\n+\tELzmaStatus status;\n+\t\n+\tret = LzmaDecode(cpage_out, &dl, data_in, &sl, propsEncoded,\n+\t\tpropsSize, LZMA_FINISH_ANY, &status, &lzma_alloc);\n+\n+\tif (ret != SZ_OK || status == LZMA_STATUS_NOT_FINISHED || dl != (SizeT)destlen)\n+\t\treturn -1;\n+\n+\treturn 0;\n+}\n+\n+static struct jffs2_compressor jffs2_lzma_comp = {\n+\t.priority = JFFS2_LZMA_PRIORITY,\n+\t.name = \"lzma\",\n+\t.compr = JFFS2_COMPR_LZMA,\n+\t.compress = &jffs2_lzma_compress,\n+\t.decompress = &jffs2_lzma_decompress,\n+\t.disabled = 0,\n+};\n+\n+int INIT jffs2_lzma_init(void)\n+{\n+\tint ret;\n+\tCLzmaEncProps props;\n+\tLzmaEncProps_Init(&props);\n+\n+\tprops.dictSize = LZMA_BEST_DICT(0x2000);\n+\tprops.level = LZMA_BEST_LEVEL;\n+\tprops.lc = LZMA_BEST_LC;\n+\tprops.lp = LZMA_BEST_LP;\n+\tprops.pb = LZMA_BEST_PB;\n+\tprops.fb = LZMA_BEST_FB;\n+\n+\tret = lzma_alloc_workspace(&props);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\tret = jffs2_register_compressor(&jffs2_lzma_comp);\n+\tif (ret)\n+\t\tlzma_free_workspace();\n+\t\n+\treturn ret;\n+}\n+\n+void jffs2_lzma_exit(void)\n+{\n+\tjffs2_unregister_compressor(&jffs2_lzma_comp);\n+\tlzma_free_workspace();\n+}\n--- a/include/linux/jffs2.h\n+++ b/include/linux/jffs2.h\n@@ -47,6 +47,7 @@\n #define JFFS2_COMPR_DYNRUBIN\t0x05\n #define JFFS2_COMPR_ZLIB\t0x06\n #define JFFS2_COMPR_LZO\t\t0x07\n+#define JFFS2_COMPR_LZMA\t0x08\n /* Compatibility flags. */\n #define JFFS2_COMPAT_MASK 0xc000      /* What do to if an unknown nodetype is found */\n #define JFFS2_NODE_ACCURATE 0x2000\n--- /dev/null\n+++ b/include/linux/lzma.h\n@@ -0,0 +1,61 @@\n+#ifndef __LZMA_H__\n+#define __LZMA_H__\n+\n+#ifdef __KERNEL__\n+\t#include <linux/kernel.h>\n+\t#include <linux/sched.h>\n+\t#include <linux/slab.h>\n+\t#include <linux/vmalloc.h>\n+\t#include <linux/init.h>\n+\t#define LZMA_MALLOC vmalloc\n+\t#define LZMA_FREE vfree\n+\t#define PRINT_ERROR(msg) printk(KERN_WARNING #msg)\n+\t#define INIT __init\n+\t#define STATIC static\n+#else\n+\t#include <stdint.h>\n+\t#include <stdlib.h>\n+\t#include <stdio.h>\n+\t#include <unistd.h>\n+\t#include <string.h>\n+\t#include <errno.h>\n+\t#include <linux/jffs2.h>\n+\t#ifndef PAGE_SIZE\n+\t\textern int page_size;\n+\t\t#define PAGE_SIZE page_size\n+\t#endif\n+\t#define LZMA_MALLOC malloc\n+\t#define LZMA_FREE free\n+\t#define PRINT_ERROR(msg) fprintf(stderr, msg)\n+\t#define INIT\n+\t#define STATIC static\n+#endif\n+\n+#include \"lzma/LzmaDec.h\"\n+#include \"lzma/LzmaEnc.h\"\n+\n+#define LZMA_BEST_LEVEL (9)\n+#define LZMA_BEST_LC    (0)\n+#define LZMA_BEST_LP    (0)\n+#define LZMA_BEST_PB    (0)\n+#define LZMA_BEST_FB  (273)\n+\n+#define LZMA_BEST_DICT(n) (((int)((n) / 2)) * 2)\n+\n+static void *p_lzma_malloc(void *p, size_t size)\n+{\n+\tif (size == 0)\n+\t\treturn NULL;\n+\n+\treturn LZMA_MALLOC(size);\n+}\n+\n+static void p_lzma_free(void *p, void *address)\n+{\n+\tif (address != NULL)\n+\t\tLZMA_FREE(address);\n+}\n+\n+static ISzAlloc lzma_alloc = {p_lzma_malloc, p_lzma_free};\n+\n+#endif\n--- /dev/null\n+++ b/include/linux/lzma/LzFind.h\n@@ -0,0 +1,116 @@\n+/* LzFind.h  -- Match finder for LZ algorithms\n+2008-04-04\n+Copyright (c) 1999-2008 Igor Pavlov\n+You can use any of the following license options:\n+  1) GNU Lesser General Public License (GNU LGPL)\n+  2) Common Public License (CPL)\n+  3) Common Development and Distribution License (CDDL) Version 1.0 \n+  4) Igor Pavlov, as the author of this code, expressly permits you to \n+     statically or dynamically link your code (or bind by name) to this file, \n+     while you keep this file unmodified.\n+*/\n+\n+#ifndef __LZFIND_H\n+#define __LZFIND_H\n+\n+#include \"Types.h\"\n+\n+typedef UInt32 CLzRef;\n+\n+typedef struct _CMatchFinder\n+{\n+  Byte *buffer;\n+  UInt32 pos;\n+  UInt32 posLimit;\n+  UInt32 streamPos;\n+  UInt32 lenLimit;\n+\n+  UInt32 cyclicBufferPos;\n+  UInt32 cyclicBufferSize; /* it must be = (historySize + 1) */\n+\n+  UInt32 matchMaxLen;\n+  CLzRef *hash;\n+  CLzRef *son;\n+  UInt32 hashMask;\n+  UInt32 cutValue;\n+\n+  Byte *bufferBase;\n+  ISeqInStream *stream;\n+  int streamEndWasReached;\n+\n+  UInt32 blockSize;\n+  UInt32 keepSizeBefore;\n+  UInt32 keepSizeAfter;\n+\n+  UInt32 numHashBytes;\n+  int directInput;\n+  int btMode;\n+  /* int skipModeBits; */\n+  int bigHash;\n+  UInt32 historySize;\n+  UInt32 fixedHashSize;\n+  UInt32 hashSizeSum;\n+  UInt32 numSons;\n+  SRes result;\n+  UInt32 crc[256];\n+} CMatchFinder;\n+\n+#define Inline_MatchFinder_GetPointerToCurrentPos(p) ((p)->buffer)\n+#define Inline_MatchFinder_GetIndexByte(p, index) ((p)->buffer[(Int32)(index)])\n+\n+#define Inline_MatchFinder_GetNumAvailableBytes(p) ((p)->streamPos - (p)->pos)\n+\n+int MatchFinder_NeedMove(CMatchFinder *p);\n+Byte *MatchFinder_GetPointerToCurrentPos(CMatchFinder *p);\n+void MatchFinder_MoveBlock(CMatchFinder *p);\n+void MatchFinder_ReadIfRequired(CMatchFinder *p);\n+\n+void MatchFinder_Construct(CMatchFinder *p);\n+\n+/* Conditions:\n+     historySize <= 3 GB\n+     keepAddBufferBefore + matchMaxLen + keepAddBufferAfter < 511MB\n+*/\n+int MatchFinder_Create(CMatchFinder *p, UInt32 historySize, \n+    UInt32 keepAddBufferBefore, UInt32 matchMaxLen, UInt32 keepAddBufferAfter,\n+    ISzAlloc *alloc);\n+void MatchFinder_Free(CMatchFinder *p, ISzAlloc *alloc);\n+void MatchFinder_Normalize3(UInt32 subValue, CLzRef *items, UInt32 numItems);\n+void MatchFinder_ReduceOffsets(CMatchFinder *p, UInt32 subValue);\n+\n+UInt32 * GetMatchesSpec1(UInt32 lenLimit, UInt32 curMatch, UInt32 pos, const Byte *buffer, CLzRef *son, \n+    UInt32 _cyclicBufferPos, UInt32 _cyclicBufferSize, UInt32 _cutValue, \n+    UInt32 *distances, UInt32 maxLen);\n+\n+/* \n+Conditions:\n+  Mf_GetNumAvailableBytes_Func must be called before each Mf_GetMatchLen_Func.\n+  Mf_GetPointerToCurrentPos_Func's result must be used only before any other function\n+*/\n+\n+typedef void (*Mf_Init_Func)(void *object);\n+typedef Byte (*Mf_GetIndexByte_Func)(void *object, Int32 index);\n+typedef UInt32 (*Mf_GetNumAvailableBytes_Func)(void *object);\n+typedef const Byte * (*Mf_GetPointerToCurrentPos_Func)(void *object);\n+typedef UInt32 (*Mf_GetMatches_Func)(void *object, UInt32 *distances);\n+typedef void (*Mf_Skip_Func)(void *object, UInt32);\n+\n+typedef struct _IMatchFinder\n+{\n+  Mf_Init_Func Init;\n+  Mf_GetIndexByte_Func GetIndexByte;\n+  Mf_GetNumAvailableBytes_Func GetNumAvailableBytes;\n+  Mf_GetPointerToCurrentPos_Func GetPointerToCurrentPos;\n+  Mf_GetMatches_Func GetMatches;\n+  Mf_Skip_Func Skip;\n+} IMatchFinder;\n+\n+void MatchFinder_CreateVTable(CMatchFinder *p, IMatchFinder *vTable);\n+\n+void MatchFinder_Init(CMatchFinder *p);\n+UInt32 Bt3Zip_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances);\n+UInt32 Hc3Zip_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances);\n+void Bt3Zip_MatchFinder_Skip(CMatchFinder *p, UInt32 num);\n+void Hc3Zip_MatchFinder_Skip(CMatchFinder *p, UInt32 num);\n+\n+#endif\n--- /dev/null\n+++ b/include/linux/lzma/LzHash.h\n@@ -0,0 +1,56 @@\n+/* LzHash.h  -- HASH functions for LZ algorithms\n+2008-03-26\n+Copyright (c) 1999-2008 Igor Pavlov\n+Read LzFind.h for license options */\n+\n+#ifndef __LZHASH_H\n+#define __LZHASH_H\n+\n+#define kHash2Size (1 << 10)\n+#define kHash3Size (1 << 16)\n+#define kHash4Size (1 << 20)\n+\n+#define kFix3HashSize (kHash2Size)\n+#define kFix4HashSize (kHash2Size + kHash3Size)\n+#define kFix5HashSize (kHash2Size + kHash3Size + kHash4Size)\n+\n+#define HASH2_CALC hashValue = cur[0] | ((UInt32)cur[1] << 8);\n+\n+#define HASH3_CALC { \\\n+  UInt32 temp = p->crc[cur[0]] ^ cur[1]; \\\n+  hash2Value = temp & (kHash2Size - 1); \\\n+  hashValue = (temp ^ ((UInt32)cur[2] << 8)) & p->hashMask; }\n+\n+#define HASH4_CALC { \\\n+  UInt32 temp = p->crc[cur[0]] ^ cur[1]; \\\n+  hash2Value = temp & (kHash2Size - 1); \\\n+  hash3Value = (temp ^ ((UInt32)cur[2] << 8)) & (kHash3Size - 1); \\\n+  hashValue = (temp ^ ((UInt32)cur[2] << 8) ^ (p->crc[cur[3]] << 5)) & p->hashMask; }\n+\n+#define HASH5_CALC { \\\n+  UInt32 temp = p->crc[cur[0]] ^ cur[1]; \\\n+  hash2Value = temp & (kHash2Size - 1); \\\n+  hash3Value = (temp ^ ((UInt32)cur[2] << 8)) & (kHash3Size - 1); \\\n+  hash4Value = (temp ^ ((UInt32)cur[2] << 8) ^ (p->crc[cur[3]] << 5)); \\\n+  hashValue = (hash4Value ^ (p->crc[cur[4]] << 3)) & p->hashMask; \\\n+  hash4Value &= (kHash4Size - 1); }\n+\n+/* #define HASH_ZIP_CALC hashValue = ((cur[0] | ((UInt32)cur[1] << 8)) ^ p->crc[cur[2]]) & 0xFFFF; */\n+#define HASH_ZIP_CALC hashValue = ((cur[2] | ((UInt32)cur[0] << 8)) ^ p->crc[cur[1]]) & 0xFFFF;\n+\n+\n+#define MT_HASH2_CALC \\\n+  hash2Value = (p->crc[cur[0]] ^ cur[1]) & (kHash2Size - 1);\n+\n+#define MT_HASH3_CALC { \\\n+  UInt32 temp = p->crc[cur[0]] ^ cur[1]; \\\n+  hash2Value = temp & (kHash2Size - 1); \\\n+  hash3Value = (temp ^ ((UInt32)cur[2] << 8)) & (kHash3Size - 1); }\n+\n+#define MT_HASH4_CALC { \\\n+  UInt32 temp = p->crc[cur[0]] ^ cur[1]; \\\n+  hash2Value = temp & (kHash2Size - 1); \\\n+  hash3Value = (temp ^ ((UInt32)cur[2] << 8)) & (kHash3Size - 1); \\\n+  hash4Value = (temp ^ ((UInt32)cur[2] << 8) ^ (p->crc[cur[3]] << 5)) & (kHash4Size - 1); }\n+\n+#endif\n--- /dev/null\n+++ b/include/linux/lzma/LzmaDec.h\n@@ -0,0 +1,232 @@\n+/* LzmaDec.h -- LZMA Decoder\n+2008-04-29\n+Copyright (c) 1999-2008 Igor Pavlov\n+You can use any of the following license options:\n+  1) GNU Lesser General Public License (GNU LGPL)\n+  2) Common Public License (CPL)\n+  3) Common Development and Distribution License (CDDL) Version 1.0 \n+  4) Igor Pavlov, as the author of this code, expressly permits you to \n+     statically or dynamically link your code (or bind by name) to this file, \n+     while you keep this file unmodified.\n+*/\n+\n+#ifndef __LZMADEC_H\n+#define __LZMADEC_H\n+\n+#include \"Types.h\"\n+\n+/* #define _LZMA_PROB32 */\n+/* _LZMA_PROB32 can increase the speed on some CPUs, \n+   but memory usage for CLzmaDec::probs will be doubled in that case */\n+\n+#ifdef _LZMA_PROB32\n+#define CLzmaProb UInt32\n+#else\n+#define CLzmaProb UInt16\n+#endif\n+\n+\n+/* ---------- LZMA Properties ---------- */  \n+\n+#define LZMA_PROPS_SIZE 5\n+\n+typedef struct _CLzmaProps\n+{\n+  unsigned lc, lp, pb;\n+  UInt32 dicSize;\n+} CLzmaProps;\n+\n+/* LzmaProps_Decode - decodes properties\n+Returns:\n+  SZ_OK\n+  SZ_ERROR_UNSUPPORTED - Unsupported properties\n+*/\n+\n+SRes LzmaProps_Decode(CLzmaProps *p, const Byte *data, unsigned size);\n+\n+\n+/* ---------- LZMA Decoder state ---------- */  \n+\n+/* LZMA_REQUIRED_INPUT_MAX = number of required input bytes for worst case.\n+   Num bits = log2((2^11 / 31) ^ 22) + 26 < 134 + 26 = 160; */\n+\n+#define LZMA_REQUIRED_INPUT_MAX 20\n+\n+typedef struct\n+{\n+  CLzmaProps prop;\n+  CLzmaProb *probs;\n+  Byte *dic;\n+  const Byte *buf;\n+  UInt32 range, code;\n+  SizeT dicPos;\n+  SizeT dicBufSize;\n+  UInt32 processedPos;\n+  UInt32 checkDicSize;\n+  unsigned state;\n+  UInt32 reps[4];\n+  unsigned remainLen;\n+  int needFlush;\n+  int needInitState;\n+  UInt32 numProbs;\n+  unsigned tempBufSize;\n+  Byte tempBuf[LZMA_REQUIRED_INPUT_MAX];\n+} CLzmaDec;\n+\n+#define LzmaDec_Construct(p) { (p)->dic = 0; (p)->probs = 0; }\n+\n+void LzmaDec_Init(CLzmaDec *p);\n+\n+/* There are two types of LZMA streams:\n+     0) Stream with end mark. That end mark adds about 6 bytes to compressed size.\n+     1) Stream without end mark. You must know exact uncompressed size to decompress such stream. */\n+\n+typedef enum \n+{\n+  LZMA_FINISH_ANY,   /* finish at any point */      \n+  LZMA_FINISH_END    /* block must be finished at the end */\n+} ELzmaFinishMode;\n+\n+/* ELzmaFinishMode has meaning only if the decoding reaches output limit !!!\n+\n+   You must use LZMA_FINISH_END, when you know that current output buffer \n+   covers last bytes of block. In other cases you must use LZMA_FINISH_ANY.\n+\n+   If LZMA decoder sees end marker before reaching output limit, it returns SZ_OK,\n+   and output value of destLen will be less than output buffer size limit.\n+   You can check status result also.\n+\n+   You can use multiple checks to test data integrity after full decompression:\n+     1) Check Result and \"status\" variable.\n+     2) Check that output(destLen) = uncompressedSize, if you know real uncompressedSize.\n+     3) Check that output(srcLen) = compressedSize, if you know real compressedSize. \n+        You must use correct finish mode in that case. */ \n+\n+typedef enum \n+{\n+  LZMA_STATUS_NOT_SPECIFIED,               /* use main error code instead */\n+  LZMA_STATUS_FINISHED_WITH_MARK,          /* stream was finished with end mark. */\n+  LZMA_STATUS_NOT_FINISHED,                /* stream was not finished */\n+  LZMA_STATUS_NEEDS_MORE_INPUT,            /* you must provide more input bytes */   \n+  LZMA_STATUS_MAYBE_FINISHED_WITHOUT_MARK  /* there is probability that stream was finished without end mark */\n+} ELzmaStatus;\n+\n+/* ELzmaStatus is used only as output value for function call */\n+\n+\n+/* ---------- Interfaces ---------- */  \n+\n+/* There are 3 levels of interfaces:\n+     1) Dictionary Interface\n+     2) Buffer Interface\n+     3) One Call Interface\n+   You can select any of these interfaces, but don't mix functions from different \n+   groups for same object. */\n+\n+\n+/* There are two variants to allocate state for Dictionary Interface:\n+     1) LzmaDec_Allocate / LzmaDec_Free\n+     2) LzmaDec_AllocateProbs / LzmaDec_FreeProbs\n+   You can use variant 2, if you set dictionary buffer manually. \n+   For Buffer Interface you must always use variant 1. \n+\n+LzmaDec_Allocate* can return:\n+  SZ_OK\n+  SZ_ERROR_MEM         - Memory allocation error\n+  SZ_ERROR_UNSUPPORTED - Unsupported properties\n+*/\n+   \n+SRes LzmaDec_AllocateProbs(CLzmaDec *p, const Byte *props, unsigned propsSize, ISzAlloc *alloc);\n+void LzmaDec_FreeProbs(CLzmaDec *p, ISzAlloc *alloc);\n+\n+SRes LzmaDec_Allocate(CLzmaDec *state, const Byte *prop, unsigned propsSize, ISzAlloc *alloc);\n+void LzmaDec_Free(CLzmaDec *state, ISzAlloc *alloc);\n+\n+/* ---------- Dictionary Interface ---------- */  \n+\n+/* You can use it, if you want to eliminate the overhead for data copying from \n+   dictionary to some other external buffer.\n+   You must work with CLzmaDec variables directly in this interface.\n+\n+   STEPS:\n+     LzmaDec_Constr()\n+     LzmaDec_Allocate()\n+     for (each new stream)\n+     {\n+       LzmaDec_Init()\n+       while (it needs more decompression)\n+       {\n+         LzmaDec_DecodeToDic()\n+         use data from CLzmaDec::dic and update CLzmaDec::dicPos\n+       }\n+     }\n+     LzmaDec_Free()\n+*/\n+\n+/* LzmaDec_DecodeToDic\n+   \n+   The decoding to internal dictionary buffer (CLzmaDec::dic).\n+   You must manually update CLzmaDec::dicPos, if it reaches CLzmaDec::dicBufSize !!! \n+\n+finishMode:\n+  It has meaning only if the decoding reaches output limit (dicLimit).\n+  LZMA_FINISH_ANY - Decode just dicLimit bytes.\n+  LZMA_FINISH_END - Stream must be finished after dicLimit.\n+\n+Returns:\n+  SZ_OK\n+    status:\n+      LZMA_STATUS_FINISHED_WITH_MARK\n+      LZMA_STATUS_NOT_FINISHED \n+      LZMA_STATUS_NEEDS_MORE_INPUT\n+      LZMA_STATUS_MAYBE_FINISHED_WITHOUT_MARK\n+  SZ_ERROR_DATA - Data error\n+*/\n+\n+SRes LzmaDec_DecodeToDic(CLzmaDec *p, SizeT dicLimit, \n+    const Byte *src, SizeT *srcLen, ELzmaFinishMode finishMode, ELzmaStatus *status);\n+\n+\n+/* ---------- Buffer Interface ---------- */  \n+\n+/* It's zlib-like interface.\n+   See LzmaDec_DecodeToDic description for information about STEPS and return results,\n+   but you must use LzmaDec_DecodeToBuf instead of LzmaDec_DecodeToDic and you don't need\n+   to work with CLzmaDec variables manually.\n+\n+finishMode: \n+  It has meaning only if the decoding reaches output limit (*destLen).\n+  LZMA_FINISH_ANY - Decode just destLen bytes.\n+  LZMA_FINISH_END - Stream must be finished after (*destLen).\n+*/\n+\n+SRes LzmaDec_DecodeToBuf(CLzmaDec *p, Byte *dest, SizeT *destLen, \n+    const Byte *src, SizeT *srcLen, ELzmaFinishMode finishMode, ELzmaStatus *status);\n+\n+\n+/* ---------- One Call Interface ---------- */  \n+\n+/* LzmaDecode\n+\n+finishMode:\n+  It has meaning only if the decoding reaches output limit (*destLen).\n+  LZMA_FINISH_ANY - Decode just destLen bytes.\n+  LZMA_FINISH_END - Stream must be finished after (*destLen).\n+\n+Returns:\n+  SZ_OK\n+    status:\n+      LZMA_STATUS_FINISHED_WITH_MARK\n+      LZMA_STATUS_NOT_FINISHED \n+      LZMA_STATUS_MAYBE_FINISHED_WITHOUT_MARK\n+  SZ_ERROR_DATA - Data error\n+  SZ_ERROR_MEM  - Memory allocation error\n+  SZ_ERROR_UNSUPPORTED - Unsupported properties\n+  SZ_ERROR_INPUT_EOF - It needs more bytes in input buffer (src).\n+*/\n+\n+SRes LzmaDecode(Byte *dest, SizeT *destLen, const Byte *src, SizeT *srcLen,\n+    const Byte *propData, unsigned propSize, ELzmaFinishMode finishMode, \n+    ELzmaStatus *status, ISzAlloc *alloc);\n+\n+#endif\n--- /dev/null\n+++ b/include/linux/lzma/LzmaEnc.h\n@@ -0,0 +1,74 @@\n+/*  LzmaEnc.h -- LZMA Encoder\n+2008-04-27\n+Copyright (c) 1999-2008 Igor Pavlov\n+Read LzFind.h for license options */\n+\n+#ifndef __LZMAENC_H\n+#define __LZMAENC_H\n+\n+#include \"Types.h\"\n+\n+#define LZMA_PROPS_SIZE 5\n+\n+typedef struct _CLzmaEncProps\n+{\n+  int level;       /*  0 <= level <= 9 */ \n+  UInt32 dictSize; /* (1 << 12) <= dictSize <= (1 << 27) for 32-bit version\n+                      (1 << 12) <= dictSize <= (1 << 30) for 64-bit version \n+                       default = (1 << 24) */\n+  int lc;          /* 0 <= lc <= 8, default = 3 */ \n+  int lp;          /* 0 <= lp <= 4, default = 0 */ \n+  int pb;          /* 0 <= pb <= 4, default = 2 */ \n+  int algo;        /* 0 - fast, 1 - normal, default = 1 */\n+  int fb;          /* 5 <= fb <= 273, default = 32 */\n+  int btMode;      /* 0 - hashChain Mode, 1 - binTree mode - normal, default = 1 */\n+  int numHashBytes; /* 2, 3 or 4, default = 4 */\n+  UInt32 mc;        /* 1 <= mc <= (1 << 30), default = 32 */\n+  unsigned writeEndMark;  /* 0 - do not write EOPM, 1 - write EOPM, default = 0 */\n+  int numThreads;  /* 1 or 2, default = 2 */\n+} CLzmaEncProps;\n+\n+void LzmaEncProps_Init(CLzmaEncProps *p);\n+void LzmaEncProps_Normalize(CLzmaEncProps *p);\n+UInt32 LzmaEncProps_GetDictSize(const CLzmaEncProps *props2);\n+\n+\n+/* ---------- CLzmaEncHandle Interface ---------- */\n+\n+/* LzmaEnc_* functions can return the following exit codes:\n+Returns:\n+  SZ_OK           - OK\n+  SZ_ERROR_MEM    - Memory allocation error \n+  SZ_ERROR_PARAM  - Incorrect paramater in props\n+  SZ_ERROR_WRITE  - Write callback error.\n+  SZ_ERROR_PROGRESS - some break from progress callback\n+  SZ_ERROR_THREAD - errors in multithreading functions (only for Mt version)\n+*/\n+\n+typedef void * CLzmaEncHandle;\n+\n+CLzmaEncHandle LzmaEnc_Create(ISzAlloc *alloc);\n+void LzmaEnc_Destroy(CLzmaEncHandle p, ISzAlloc *alloc, ISzAlloc *allocBig);\n+SRes LzmaEnc_SetProps(CLzmaEncHandle p, const CLzmaEncProps *props);\n+SRes LzmaEnc_WriteProperties(CLzmaEncHandle p, Byte *properties, SizeT *size);\n+SRes LzmaEnc_Encode(CLzmaEncHandle p, ISeqOutStream *outStream, ISeqInStream *inStream, \n+    ICompressProgress *progress, ISzAlloc *alloc, ISzAlloc *allocBig);\n+SRes LzmaEnc_MemEncode(CLzmaEncHandle p, Byte *dest, SizeT *destLen, const Byte *src, SizeT srcLen,\n+    int writeEndMark, ICompressProgress *progress, ISzAlloc *alloc, ISzAlloc *allocBig);\n+\n+/* ---------- One Call Interface ---------- */\n+\n+/* LzmaEncode\n+Return code:\n+  SZ_OK               - OK\n+  SZ_ERROR_MEM        - Memory allocation error \n+  SZ_ERROR_PARAM      - Incorrect paramater\n+  SZ_ERROR_OUTPUT_EOF - output buffer overflow\n+  SZ_ERROR_THREAD     - errors in multithreading functions (only for Mt version)\n+*/\n+\n+SRes LzmaEncode(Byte *dest, SizeT *destLen, const Byte *src, SizeT srcLen,\n+    const CLzmaEncProps *props, Byte *propsEncoded, SizeT *propsSize, int writeEndMark, \n+    ICompressProgress *progress, ISzAlloc *alloc, ISzAlloc *allocBig);\n+\n+#endif\n--- /dev/null\n+++ b/include/linux/lzma/Types.h\n@@ -0,0 +1,130 @@\n+/* Types.h -- Basic types\n+2008-04-11\n+Igor Pavlov\n+Public domain */\n+\n+#ifndef __7Z_TYPES_H\n+#define __7Z_TYPES_H\n+\n+#define SZ_OK 0\n+\n+#define SZ_ERROR_DATA 1\n+#define SZ_ERROR_MEM 2\n+#define SZ_ERROR_CRC 3\n+#define SZ_ERROR_UNSUPPORTED 4\n+#define SZ_ERROR_PARAM 5\n+#define SZ_ERROR_INPUT_EOF 6\n+#define SZ_ERROR_OUTPUT_EOF 7\n+#define SZ_ERROR_READ 8\n+#define SZ_ERROR_WRITE 9\n+#define SZ_ERROR_PROGRESS 10\n+#define SZ_ERROR_FAIL 11\n+#define SZ_ERROR_THREAD 12\n+\n+#define SZ_ERROR_ARCHIVE 16\n+#define SZ_ERROR_NO_ARCHIVE 17\n+\n+typedef int SRes;\n+\n+#ifndef RINOK\n+#define RINOK(x) { int __result__ = (x); if (__result__ != 0) return __result__; }\n+#endif\n+\n+typedef unsigned char Byte;\n+typedef short Int16;\n+typedef unsigned short UInt16;\n+\n+#ifdef _LZMA_UINT32_IS_ULONG\n+typedef long Int32;\n+typedef unsigned long UInt32;\n+#else\n+typedef int Int32;\n+typedef unsigned int UInt32;\n+#endif\n+\n+/* #define _SZ_NO_INT_64 */\n+/* define it if your compiler doesn't support 64-bit integers */\n+\n+#ifdef _SZ_NO_INT_64\n+\n+typedef long Int64;\n+typedef unsigned long UInt64;\n+\n+#else\n+\n+#if defined(_MSC_VER) || defined(__BORLANDC__)\n+typedef __int64 Int64;\n+typedef unsigned __int64 UInt64;\n+#else\n+typedef long long int Int64;\n+typedef unsigned long long int UInt64;\n+#endif\n+\n+#endif\n+\n+#ifdef _LZMA_NO_SYSTEM_SIZE_T\n+typedef UInt32 SizeT;\n+#else\n+#include <stddef.h>\n+typedef size_t SizeT;\n+#endif\n+\n+typedef int Bool;\n+#define True 1\n+#define False 0\n+\n+\n+#ifdef _MSC_VER\n+\n+#if _MSC_VER >= 1300\n+#define MY_NO_INLINE __declspec(noinline)\n+#else\n+#define MY_NO_INLINE\n+#endif\n+\n+#define MY_CDECL __cdecl\n+#define MY_STD_CALL __stdcall \n+#define MY_FAST_CALL MY_NO_INLINE __fastcall \n+\n+#else\n+\n+#define MY_CDECL\n+#define MY_STD_CALL\n+#define MY_FAST_CALL\n+\n+#endif\n+\n+\n+/* The following interfaces use first parameter as pointer to structure */\n+\n+typedef struct\n+{\n+  SRes (*Read)(void *p, void *buf, size_t *size);\n+    /* if (input(*size) != 0 && output(*size) == 0) means end_of_stream.\n+       (output(*size) < input(*size)) is allowed */\n+} ISeqInStream;\n+\n+typedef struct\n+{\n+  size_t (*Write)(void *p, const void *buf, size_t size);\n+    /* Returns: result - the number of actually written bytes.\n+      (result < size) means error */\n+} ISeqOutStream;\n+\n+typedef struct\n+{\n+  SRes (*Progress)(void *p, UInt64 inSize, UInt64 outSize);\n+    /* Returns: result. (result != SZ_OK) means break.\n+       Value (UInt64)(Int64)-1 for size means unknown value. */\n+} ICompressProgress;\n+\n+typedef struct\n+{\n+  void *(*Alloc)(void *p, size_t size);\n+  void (*Free)(void *p, void *address); /* address can be 0 */\n+} ISzAlloc;\n+\n+#define IAlloc_Alloc(p, size) (p)->Alloc((p), size)\n+#define IAlloc_Free(p, a) (p)->Free((p), a)\n+\n+#endif\n--- /dev/null\n+++ b/jffsX-utils/lzma/LzFind.c\n@@ -0,0 +1,753 @@\n+/* LzFind.c  -- Match finder for LZ algorithms\n+2008-04-04\n+Copyright (c) 1999-2008 Igor Pavlov\n+Read LzFind.h for license options */\n+\n+#include <string.h>\n+\n+#include \"LzFind.h\"\n+#include \"LzHash.h\"\n+\n+#define kEmptyHashValue 0\n+#define kMaxValForNormalize ((UInt32)0xFFFFFFFF)\n+#define kNormalizeStepMin (1 << 10) /* it must be power of 2 */\n+#define kNormalizeMask (~(kNormalizeStepMin - 1))\n+#define kMaxHistorySize ((UInt32)3 << 30)\n+\n+#define kStartMaxLen 3\n+\n+static void LzInWindow_Free(CMatchFinder *p, ISzAlloc *alloc)\n+{\n+  if (!p->directInput)\n+  {\n+    alloc->Free(alloc, p->bufferBase);\n+    p->bufferBase = 0;\n+  }\n+}\n+\n+/* keepSizeBefore + keepSizeAfter + keepSizeReserv must be < 4G) */\n+\n+static int LzInWindow_Create(CMatchFinder *p, UInt32 keepSizeReserv, ISzAlloc *alloc)\n+{\n+  UInt32 blockSize = p->keepSizeBefore + p->keepSizeAfter + keepSizeReserv;\n+  if (p->directInput)\n+  {\n+    p->blockSize = blockSize;\n+    return 1;\n+  }\n+  if (p->bufferBase == 0 || p->blockSize != blockSize)\n+  {\n+    LzInWindow_Free(p, alloc);\n+    p->blockSize = blockSize;\n+    p->bufferBase = (Byte *)alloc->Alloc(alloc, (size_t)blockSize);\n+  }\n+  return (p->bufferBase != 0);\n+}\n+\n+Byte *MatchFinder_GetPointerToCurrentPos(CMatchFinder *p) { return p->buffer; }\n+static Byte MatchFinder_GetIndexByte(CMatchFinder *p, Int32 index) { return p->buffer[index]; }\n+\n+static UInt32 MatchFinder_GetNumAvailableBytes(CMatchFinder *p) { return p->streamPos - p->pos; }\n+\n+void MatchFinder_ReduceOffsets(CMatchFinder *p, UInt32 subValue)\n+{\n+  p->posLimit -= subValue;\n+  p->pos -= subValue;\n+  p->streamPos -= subValue;\n+}\n+\n+static void MatchFinder_ReadBlock(CMatchFinder *p)\n+{\n+  if (p->streamEndWasReached || p->result != SZ_OK)\n+    return;\n+  for (;;)\n+  {\n+    Byte *dest = p->buffer + (p->streamPos - p->pos);\n+    size_t size = (p->bufferBase + p->blockSize - dest);\n+    if (size == 0)\n+      return;\n+    p->result = p->stream->Read(p->stream, dest, &size);\n+    if (p->result != SZ_OK)\n+      return;\n+    if (size == 0)\n+    {\n+      p->streamEndWasReached = 1;\n+      return;\n+    }\n+    p->streamPos += (UInt32)size;\n+    if (p->streamPos - p->pos > p->keepSizeAfter)\n+      return;\n+  }\n+}\n+\n+void MatchFinder_MoveBlock(CMatchFinder *p)\n+{\n+  memmove(p->bufferBase, \n+    p->buffer - p->keepSizeBefore, \n+    (size_t)(p->streamPos - p->pos + p->keepSizeBefore));\n+  p->buffer = p->bufferBase + p->keepSizeBefore;\n+}\n+\n+int MatchFinder_NeedMove(CMatchFinder *p)\n+{\n+  /* if (p->streamEndWasReached) return 0; */\n+  return ((size_t)(p->bufferBase + p->blockSize - p->buffer) <= p->keepSizeAfter);\n+}\n+\n+void MatchFinder_ReadIfRequired(CMatchFinder *p)\n+{\n+  if (p->streamEndWasReached) \n+    return;\n+  if (p->keepSizeAfter >= p->streamPos - p->pos)\n+    MatchFinder_ReadBlock(p);\n+}\n+\n+static void MatchFinder_CheckAndMoveAndRead(CMatchFinder *p)\n+{\n+  if (MatchFinder_NeedMove(p))\n+    MatchFinder_MoveBlock(p);\n+  MatchFinder_ReadBlock(p);\n+}\n+\n+static void MatchFinder_SetDefaultSettings(CMatchFinder *p)\n+{\n+  p->cutValue = 32;\n+  p->btMode = 1;\n+  p->numHashBytes = 4;\n+  /* p->skipModeBits = 0; */\n+  p->directInput = 0;\n+  p->bigHash = 0;\n+}\n+\n+#define kCrcPoly 0xEDB88320\n+\n+void MatchFinder_Construct(CMatchFinder *p)\n+{\n+  UInt32 i;\n+  p->bufferBase = 0;\n+  p->directInput = 0;\n+  p->hash = 0;\n+  MatchFinder_SetDefaultSettings(p);\n+\n+  for (i = 0; i < 256; i++)\n+  {\n+    UInt32 r = i;\n+    int j;\n+    for (j = 0; j < 8; j++)\n+      r = (r >> 1) ^ (kCrcPoly & ~((r & 1) - 1));\n+    p->crc[i] = r;\n+  }\n+}\n+\n+static void MatchFinder_FreeThisClassMemory(CMatchFinder *p, ISzAlloc *alloc)\n+{\n+  alloc->Free(alloc, p->hash);\n+  p->hash = 0;\n+}\n+\n+void MatchFinder_Free(CMatchFinder *p, ISzAlloc *alloc)\n+{\n+  MatchFinder_FreeThisClassMemory(p, alloc);\n+  LzInWindow_Free(p, alloc);\n+}\n+\n+static CLzRef* AllocRefs(UInt32 num, ISzAlloc *alloc)\n+{\n+  size_t sizeInBytes = (size_t)num * sizeof(CLzRef);\n+  if (sizeInBytes / sizeof(CLzRef) != num)\n+    return 0;\n+  return (CLzRef *)alloc->Alloc(alloc, sizeInBytes);\n+}\n+\n+int MatchFinder_Create(CMatchFinder *p, UInt32 historySize, \n+    UInt32 keepAddBufferBefore, UInt32 matchMaxLen, UInt32 keepAddBufferAfter,\n+    ISzAlloc *alloc)\n+{\n+  UInt32 sizeReserv;\n+  if (historySize > kMaxHistorySize)\n+  {\n+    MatchFinder_Free(p, alloc);\n+    return 0;\n+  }\n+  sizeReserv = historySize >> 1;\n+  if (historySize > ((UInt32)2 << 30))\n+    sizeReserv = historySize >> 2;\n+  sizeReserv += (keepAddBufferBefore + matchMaxLen + keepAddBufferAfter) / 2 + (1 << 19);\n+\n+  p->keepSizeBefore = historySize + keepAddBufferBefore + 1; \n+  p->keepSizeAfter = matchMaxLen + keepAddBufferAfter;\n+  /* we need one additional byte, since we use MoveBlock after pos++ and before dictionary using */\n+  if (LzInWindow_Create(p, sizeReserv, alloc))\n+  {\n+    UInt32 newCyclicBufferSize = (historySize /* >> p->skipModeBits */) + 1;\n+    UInt32 hs;\n+    p->matchMaxLen = matchMaxLen;\n+    {\n+      p->fixedHashSize = 0;\n+      if (p->numHashBytes == 2)\n+        hs = (1 << 16) - 1;\n+      else\n+      {\n+        hs = historySize - 1;\n+        hs |= (hs >> 1);\n+        hs |= (hs >> 2);\n+        hs |= (hs >> 4);\n+        hs |= (hs >> 8);\n+        hs >>= 1;\n+        /* hs >>= p->skipModeBits; */\n+        hs |= 0xFFFF; /* don't change it! It's required for Deflate */\n+        if (hs > (1 << 24))\n+        {\n+          if (p->numHashBytes == 3)\n+            hs = (1 << 24) - 1;\n+          else\n+            hs >>= 1;\n+        }\n+      }\n+      p->hashMask = hs;\n+      hs++;\n+      if (p->numHashBytes > 2) p->fixedHashSize += kHash2Size;\n+      if (p->numHashBytes > 3) p->fixedHashSize += kHash3Size;\n+      if (p->numHashBytes > 4) p->fixedHashSize += kHash4Size;\n+      hs += p->fixedHashSize;\n+    }\n+\n+    {\n+      UInt32 prevSize = p->hashSizeSum + p->numSons;\n+      UInt32 newSize;\n+      p->historySize = historySize;\n+      p->hashSizeSum = hs;\n+      p->cyclicBufferSize = newCyclicBufferSize;\n+      p->numSons = (p->btMode ? newCyclicBufferSize * 2 : newCyclicBufferSize);\n+      newSize = p->hashSizeSum + p->numSons;\n+      if (p->hash != 0 && prevSize == newSize)\n+        return 1;\n+      MatchFinder_FreeThisClassMemory(p, alloc);\n+      p->hash = AllocRefs(newSize, alloc);\n+      if (p->hash != 0)\n+      {\n+        p->son = p->hash + p->hashSizeSum;\n+        return 1;\n+      }\n+    }\n+  }\n+  MatchFinder_Free(p, alloc);\n+  return 0;\n+}\n+\n+static void MatchFinder_SetLimits(CMatchFinder *p)\n+{\n+  UInt32 limit = kMaxValForNormalize - p->pos;\n+  UInt32 limit2 = p->cyclicBufferSize - p->cyclicBufferPos;\n+  if (limit2 < limit) \n+    limit = limit2;\n+  limit2 = p->streamPos - p->pos;\n+  if (limit2 <= p->keepSizeAfter)\n+  {\n+    if (limit2 > 0)\n+      limit2 = 1;\n+  }\n+  else\n+    limit2 -= p->keepSizeAfter;\n+  if (limit2 < limit) \n+    limit = limit2;\n+  {\n+    UInt32 lenLimit = p->streamPos - p->pos;\n+    if (lenLimit > p->matchMaxLen)\n+      lenLimit = p->matchMaxLen;\n+    p->lenLimit = lenLimit;\n+  }\n+  p->posLimit = p->pos + limit;\n+}\n+\n+void MatchFinder_Init(CMatchFinder *p)\n+{\n+  UInt32 i;\n+  for(i = 0; i < p->hashSizeSum; i++)\n+    p->hash[i] = kEmptyHashValue;\n+  p->cyclicBufferPos = 0;\n+  p->buffer = p->bufferBase;\n+  p->pos = p->streamPos = p->cyclicBufferSize;\n+  p->result = SZ_OK;\n+  p->streamEndWasReached = 0;\n+  MatchFinder_ReadBlock(p);\n+  MatchFinder_SetLimits(p);\n+}\n+\n+static UInt32 MatchFinder_GetSubValue(CMatchFinder *p) \n+{ \n+  return (p->pos - p->historySize - 1) & kNormalizeMask; \n+}\n+\n+void MatchFinder_Normalize3(UInt32 subValue, CLzRef *items, UInt32 numItems)\n+{\n+  UInt32 i;\n+  for (i = 0; i < numItems; i++)\n+  {\n+    UInt32 value = items[i];\n+    if (value <= subValue)\n+      value = kEmptyHashValue;\n+    else\n+      value -= subValue;\n+    items[i] = value;\n+  }\n+}\n+\n+static void MatchFinder_Normalize(CMatchFinder *p)\n+{\n+  UInt32 subValue = MatchFinder_GetSubValue(p);\n+  MatchFinder_Normalize3(subValue, p->hash, p->hashSizeSum + p->numSons);\n+  MatchFinder_ReduceOffsets(p, subValue);\n+}\n+\n+static void MatchFinder_CheckLimits(CMatchFinder *p)\n+{\n+  if (p->pos == kMaxValForNormalize)\n+    MatchFinder_Normalize(p);\n+  if (!p->streamEndWasReached && p->keepSizeAfter == p->streamPos - p->pos)\n+    MatchFinder_CheckAndMoveAndRead(p);\n+  if (p->cyclicBufferPos == p->cyclicBufferSize)\n+    p->cyclicBufferPos = 0;\n+  MatchFinder_SetLimits(p);\n+}\n+\n+static UInt32 * Hc_GetMatchesSpec(UInt32 lenLimit, UInt32 curMatch, UInt32 pos, const Byte *cur, CLzRef *son, \n+    UInt32 _cyclicBufferPos, UInt32 _cyclicBufferSize, UInt32 cutValue, \n+    UInt32 *distances, UInt32 maxLen)\n+{\n+  son[_cyclicBufferPos] = curMatch;\n+  for (;;)\n+  {\n+    UInt32 delta = pos - curMatch;\n+    if (cutValue-- == 0 || delta >= _cyclicBufferSize)\n+      return distances;\n+    {\n+      const Byte *pb = cur - delta;\n+      curMatch = son[_cyclicBufferPos - delta + ((delta > _cyclicBufferPos) ? _cyclicBufferSize : 0)];\n+      if (pb[maxLen] == cur[maxLen] && *pb == *cur)\n+      {\n+        UInt32 len = 0;\n+        while(++len != lenLimit)\n+          if (pb[len] != cur[len])\n+            break;\n+        if (maxLen < len)\n+        {\n+          *distances++ = maxLen = len;\n+          *distances++ = delta - 1;\n+          if (len == lenLimit)\n+            return distances;\n+        }\n+      }\n+    }\n+  }\n+}\n+\n+UInt32 * GetMatchesSpec1(UInt32 lenLimit, UInt32 curMatch, UInt32 pos, const Byte *cur, CLzRef *son, \n+    UInt32 _cyclicBufferPos, UInt32 _cyclicBufferSize, UInt32 cutValue, \n+    UInt32 *distances, UInt32 maxLen)\n+{\n+  CLzRef *ptr0 = son + (_cyclicBufferPos << 1) + 1;\n+  CLzRef *ptr1 = son + (_cyclicBufferPos << 1);\n+  UInt32 len0 = 0, len1 = 0;\n+  for (;;)\n+  {\n+    UInt32 delta = pos - curMatch;\n+    if (cutValue-- == 0 || delta >= _cyclicBufferSize)\n+    {\n+      *ptr0 = *ptr1 = kEmptyHashValue;\n+      return distances;\n+    }\n+    {\n+      CLzRef *pair = son + ((_cyclicBufferPos - delta + ((delta > _cyclicBufferPos) ? _cyclicBufferSize : 0)) << 1);\n+      const Byte *pb = cur - delta;\n+      UInt32 len = (len0 < len1 ? len0 : len1);\n+      if (pb[len] == cur[len])\n+      {\n+        if (++len != lenLimit && pb[len] == cur[len])\n+          while(++len != lenLimit)\n+            if (pb[len] != cur[len])\n+              break;\n+        if (maxLen < len)\n+        {\n+          *distances++ = maxLen = len;\n+          *distances++ = delta - 1;\n+          if (len == lenLimit)\n+          {\n+            *ptr1 = pair[0];\n+            *ptr0 = pair[1];\n+            return distances;\n+          }\n+        }\n+      }\n+      if (pb[len] < cur[len])\n+      {\n+        *ptr1 = curMatch;\n+        ptr1 = pair + 1;\n+        curMatch = *ptr1;\n+        len1 = len;\n+      }\n+      else\n+      {\n+        *ptr0 = curMatch;\n+        ptr0 = pair;\n+        curMatch = *ptr0;\n+        len0 = len;\n+      }\n+    }\n+  }\n+}\n+\n+static void SkipMatchesSpec(UInt32 lenLimit, UInt32 curMatch, UInt32 pos, const Byte *cur, CLzRef *son, \n+    UInt32 _cyclicBufferPos, UInt32 _cyclicBufferSize, UInt32 cutValue)\n+{\n+  CLzRef *ptr0 = son + (_cyclicBufferPos << 1) + 1;\n+  CLzRef *ptr1 = son + (_cyclicBufferPos << 1);\n+  UInt32 len0 = 0, len1 = 0;\n+  for (;;)\n+  {\n+    UInt32 delta = pos - curMatch;\n+    if (cutValue-- == 0 || delta >= _cyclicBufferSize)\n+    {\n+      *ptr0 = *ptr1 = kEmptyHashValue;\n+      return;\n+    }\n+    {\n+      CLzRef *pair = son + ((_cyclicBufferPos - delta + ((delta > _cyclicBufferPos) ? _cyclicBufferSize : 0)) << 1);\n+      const Byte *pb = cur - delta;\n+      UInt32 len = (len0 < len1 ? len0 : len1);\n+      if (pb[len] == cur[len])\n+      {\n+        while(++len != lenLimit)\n+          if (pb[len] != cur[len])\n+            break;\n+        {\n+          if (len == lenLimit)\n+          {\n+            *ptr1 = pair[0];\n+            *ptr0 = pair[1];\n+            return;\n+          }\n+        }\n+      }\n+      if (pb[len] < cur[len])\n+      {\n+        *ptr1 = curMatch;\n+        ptr1 = pair + 1;\n+        curMatch = *ptr1;\n+        len1 = len;\n+      }\n+      else\n+      {\n+        *ptr0 = curMatch;\n+        ptr0 = pair;\n+        curMatch = *ptr0;\n+        len0 = len;\n+      }\n+    }\n+  }\n+}\n+\n+#define MOVE_POS \\\n+  ++p->cyclicBufferPos; \\\n+  p->buffer++; \\\n+  if (++p->pos == p->posLimit) MatchFinder_CheckLimits(p);\n+\n+#define MOVE_POS_RET MOVE_POS return offset;\n+\n+static void MatchFinder_MovePos(CMatchFinder *p) { MOVE_POS; }\n+\n+#define GET_MATCHES_HEADER2(minLen, ret_op) \\\n+  UInt32 lenLimit; UInt32 hashValue; const Byte *cur; UInt32 curMatch; \\\n+  lenLimit = p->lenLimit; { if (lenLimit < minLen) { MatchFinder_MovePos(p); ret_op; }} \\\n+  cur = p->buffer;\n+\n+#define GET_MATCHES_HEADER(minLen) GET_MATCHES_HEADER2(minLen, return 0)\n+#define SKIP_HEADER(minLen)        GET_MATCHES_HEADER2(minLen, continue)\n+\n+#define MF_PARAMS(p) p->pos, p->buffer, p->son, p->cyclicBufferPos, p->cyclicBufferSize, p->cutValue\n+\n+#define GET_MATCHES_FOOTER(offset, maxLen) \\\n+  offset = (UInt32)(GetMatchesSpec1(lenLimit, curMatch, MF_PARAMS(p), \\\n+  distances + offset, maxLen) - distances); MOVE_POS_RET;\n+\n+#define SKIP_FOOTER \\\n+  SkipMatchesSpec(lenLimit, curMatch, MF_PARAMS(p)); MOVE_POS;\n+\n+static UInt32 Bt2_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances)\n+{\n+  UInt32 offset;\n+  GET_MATCHES_HEADER(2)\n+  HASH2_CALC;\n+  curMatch = p->hash[hashValue];\n+  p->hash[hashValue] = p->pos;\n+  offset = 0;\n+  GET_MATCHES_FOOTER(offset, 1)\n+}\n+\n+UInt32 Bt3Zip_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances)\n+{\n+  UInt32 offset;\n+  GET_MATCHES_HEADER(3)\n+  HASH_ZIP_CALC;\n+  curMatch = p->hash[hashValue];\n+  p->hash[hashValue] = p->pos;\n+  offset = 0;\n+  GET_MATCHES_FOOTER(offset, 2)\n+}\n+\n+static UInt32 Bt3_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances)\n+{\n+  UInt32 hash2Value, delta2, maxLen, offset;\n+  GET_MATCHES_HEADER(3)\n+\n+  HASH3_CALC;\n+\n+  delta2 = p->pos - p->hash[hash2Value];\n+  curMatch = p->hash[kFix3HashSize + hashValue];\n+  \n+  p->hash[hash2Value] = \n+  p->hash[kFix3HashSize + hashValue] = p->pos;\n+\n+\n+  maxLen = 2;\n+  offset = 0;\n+  if (delta2 < p->cyclicBufferSize && *(cur - delta2) == *cur)\n+  {\n+    for (; maxLen != lenLimit; maxLen++)\n+      if (cur[(ptrdiff_t)maxLen - delta2] != cur[maxLen])\n+        break;\n+    distances[0] = maxLen;\n+    distances[1] = delta2 - 1;\n+    offset = 2;\n+    if (maxLen == lenLimit)\n+    {\n+      SkipMatchesSpec(lenLimit, curMatch, MF_PARAMS(p));\n+      MOVE_POS_RET; \n+    }\n+  }\n+  GET_MATCHES_FOOTER(offset, maxLen)\n+}\n+\n+static UInt32 Bt4_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances)\n+{\n+  UInt32 hash2Value, hash3Value, delta2, delta3, maxLen, offset;\n+  GET_MATCHES_HEADER(4)\n+\n+  HASH4_CALC;\n+\n+  delta2 = p->pos - p->hash[                hash2Value];\n+  delta3 = p->pos - p->hash[kFix3HashSize + hash3Value];\n+  curMatch = p->hash[kFix4HashSize + hashValue];\n+  \n+  p->hash[                hash2Value] =\n+  p->hash[kFix3HashSize + hash3Value] =\n+  p->hash[kFix4HashSize + hashValue] = p->pos;\n+\n+  maxLen = 1;\n+  offset = 0;\n+  if (delta2 < p->cyclicBufferSize && *(cur - delta2) == *cur)\n+  {\n+    distances[0] = maxLen = 2;\n+    distances[1] = delta2 - 1;\n+    offset = 2;\n+  }\n+  if (delta2 != delta3 && delta3 < p->cyclicBufferSize && *(cur - delta3) == *cur)\n+  {\n+    maxLen = 3;\n+    distances[offset + 1] = delta3 - 1;\n+    offset += 2;\n+    delta2 = delta3;\n+  }\n+  if (offset != 0)\n+  {\n+    for (; maxLen != lenLimit; maxLen++)\n+      if (cur[(ptrdiff_t)maxLen - delta2] != cur[maxLen])\n+        break;\n+    distances[offset - 2] = maxLen;\n+    if (maxLen == lenLimit)\n+    {\n+      SkipMatchesSpec(lenLimit, curMatch, MF_PARAMS(p));\n+      MOVE_POS_RET; \n+    }\n+  }\n+  if (maxLen < 3)\n+    maxLen = 3;\n+  GET_MATCHES_FOOTER(offset, maxLen)\n+}\n+\n+static UInt32 Hc4_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances)\n+{\n+  UInt32 hash2Value, hash3Value, delta2, delta3, maxLen, offset;\n+  GET_MATCHES_HEADER(4)\n+\n+  HASH4_CALC;\n+\n+  delta2 = p->pos - p->hash[                hash2Value];\n+  delta3 = p->pos - p->hash[kFix3HashSize + hash3Value];\n+  curMatch = p->hash[kFix4HashSize + hashValue];\n+\n+  p->hash[                hash2Value] =\n+  p->hash[kFix3HashSize + hash3Value] =\n+  p->hash[kFix4HashSize + hashValue] = p->pos;\n+\n+  maxLen = 1;\n+  offset = 0;\n+  if (delta2 < p->cyclicBufferSize && *(cur - delta2) == *cur)\n+  {\n+    distances[0] = maxLen = 2;\n+    distances[1] = delta2 - 1;\n+    offset = 2;\n+  }\n+  if (delta2 != delta3 && delta3 < p->cyclicBufferSize && *(cur - delta3) == *cur)\n+  {\n+    maxLen = 3;\n+    distances[offset + 1] = delta3 - 1;\n+    offset += 2;\n+    delta2 = delta3;\n+  }\n+  if (offset != 0)\n+  {\n+    for (; maxLen != lenLimit; maxLen++)\n+      if (cur[(ptrdiff_t)maxLen - delta2] != cur[maxLen])\n+        break;\n+    distances[offset - 2] = maxLen;\n+    if (maxLen == lenLimit)\n+    {\n+      p->son[p->cyclicBufferPos] = curMatch;\n+      MOVE_POS_RET; \n+    }\n+  }\n+  if (maxLen < 3)\n+    maxLen = 3;\n+  offset = (UInt32)(Hc_GetMatchesSpec(lenLimit, curMatch, MF_PARAMS(p),\n+    distances + offset, maxLen) - (distances));\n+  MOVE_POS_RET\n+}\n+\n+UInt32 Hc3Zip_MatchFinder_GetMatches(CMatchFinder *p, UInt32 *distances)\n+{\n+  UInt32 offset;\n+  GET_MATCHES_HEADER(3)\n+  HASH_ZIP_CALC;\n+  curMatch = p->hash[hashValue];\n+  p->hash[hashValue] = p->pos;\n+  offset = (UInt32)(Hc_GetMatchesSpec(lenLimit, curMatch, MF_PARAMS(p),\n+    distances, 2) - (distances));\n+  MOVE_POS_RET\n+}\n+\n+static void Bt2_MatchFinder_Skip(CMatchFinder *p, UInt32 num)\n+{\n+  do\n+  {\n+    SKIP_HEADER(2) \n+    HASH2_CALC;\n+    curMatch = p->hash[hashValue];\n+    p->hash[hashValue] = p->pos;\n+    SKIP_FOOTER\n+  }\n+  while (--num != 0);\n+}\n+\n+void Bt3Zip_MatchFinder_Skip(CMatchFinder *p, UInt32 num)\n+{\n+  do\n+  {\n+    SKIP_HEADER(3)\n+    HASH_ZIP_CALC;\n+    curMatch = p->hash[hashValue];\n+    p->hash[hashValue] = p->pos;\n+    SKIP_FOOTER\n+  }\n+  while (--num != 0);\n+}\n+\n+static void Bt3_MatchFinder_Skip(CMatchFinder *p, UInt32 num)\n+{\n+  do\n+  {\n+    UInt32 hash2Value;\n+    SKIP_HEADER(3)\n+    HASH3_CALC;\n+    curMatch = p->hash[kFix3HashSize + hashValue];\n+    p->hash[hash2Value] =\n+    p->hash[kFix3HashSize + hashValue] = p->pos;\n+    SKIP_FOOTER\n+  }\n+  while (--num != 0);\n+}\n+\n+static void Bt4_MatchFinder_Skip(CMatchFinder *p, UInt32 num)\n+{\n+  do\n+  {\n+    UInt32 hash2Value, hash3Value;\n+    SKIP_HEADER(4) \n+    HASH4_CALC;\n+    curMatch = p->hash[kFix4HashSize + hashValue];\n+    p->hash[                hash2Value] =\n+    p->hash[kFix3HashSize + hash3Value] = p->pos;\n+    p->hash[kFix4HashSize + hashValue] = p->pos;\n+    SKIP_FOOTER\n+  }\n+  while (--num != 0);\n+}\n+\n+static void Hc4_MatchFinder_Skip(CMatchFinder *p, UInt32 num)\n+{\n+  do\n+  {\n+    UInt32 hash2Value, hash3Value;\n+    SKIP_HEADER(4)\n+    HASH4_CALC;\n+    curMatch = p->hash[kFix4HashSize + hashValue];\n+    p->hash[                hash2Value] =\n+    p->hash[kFix3HashSize + hash3Value] =\n+    p->hash[kFix4HashSize + hashValue] = p->pos;\n+    p->son[p->cyclicBufferPos] = curMatch;\n+    MOVE_POS\n+  }\n+  while (--num != 0);\n+}\n+\n+void Hc3Zip_MatchFinder_Skip(CMatchFinder *p, UInt32 num)\n+{\n+  do\n+  {\n+    SKIP_HEADER(3)\n+    HASH_ZIP_CALC;\n+    curMatch = p->hash[hashValue];\n+    p->hash[hashValue] = p->pos;\n+    p->son[p->cyclicBufferPos] = curMatch;\n+    MOVE_POS\n+  }\n+  while (--num != 0);\n+}\n+\n+void MatchFinder_CreateVTable(CMatchFinder *p, IMatchFinder *vTable)\n+{\n+  vTable->Init = (Mf_Init_Func)MatchFinder_Init;\n+  vTable->GetIndexByte = (Mf_GetIndexByte_Func)MatchFinder_GetIndexByte;\n+  vTable->GetNumAvailableBytes = (Mf_GetNumAvailableBytes_Func)MatchFinder_GetNumAvailableBytes;\n+  vTable->GetPointerToCurrentPos = (Mf_GetPointerToCurrentPos_Func)MatchFinder_GetPointerToCurrentPos;\n+  if (!p->btMode)\n+  {\n+    vTable->GetMatches = (Mf_GetMatches_Func)Hc4_MatchFinder_GetMatches;\n+    vTable->Skip = (Mf_Skip_Func)Hc4_MatchFinder_Skip;\n+  }\n+  else if (p->numHashBytes == 2)\n+  {\n+    vTable->GetMatches = (Mf_GetMatches_Func)Bt2_MatchFinder_GetMatches;\n+    vTable->Skip = (Mf_Skip_Func)Bt2_MatchFinder_Skip;\n+  }\n+  else if (p->numHashBytes == 3)\n+  {\n+    vTable->GetMatches = (Mf_GetMatches_Func)Bt3_MatchFinder_GetMatches;\n+    vTable->Skip = (Mf_Skip_Func)Bt3_MatchFinder_Skip;\n+  }\n+  else\n+  {\n+    vTable->GetMatches = (Mf_GetMatches_Func)Bt4_MatchFinder_GetMatches;\n+    vTable->Skip = (Mf_Skip_Func)Bt4_MatchFinder_Skip;\n+  }\n+}\n--- /dev/null\n+++ b/jffsX-utils/lzma/LzmaDec.c\n@@ -0,0 +1,1014 @@\n+/* LzmaDec.c -- LZMA Decoder\n+2008-04-29\n+Copyright (c) 1999-2008 Igor Pavlov\n+Read LzmaDec.h for license options */\n+\n+#include \"LzmaDec.h\"\n+\n+#include <string.h>\n+\n+#define kNumTopBits 24\n+#define kTopValue ((UInt32)1 << kNumTopBits)\n+\n+#define kNumBitModelTotalBits 11\n+#define kBitModelTotal (1 << kNumBitModelTotalBits)\n+#define kNumMoveBits 5\n+\n+#define RC_INIT_SIZE 5\n+\n+#define NORMALIZE if (range < kTopValue) { range <<= 8; code = (code << 8) | (*buf++); }\n+\n+#define IF_BIT_0(p) ttt = *(p); NORMALIZE; bound = (range >> kNumBitModelTotalBits) * ttt; if (code < bound)\n+#define UPDATE_0(p) range = bound; *(p) = (CLzmaProb)(ttt + ((kBitModelTotal - ttt) >> kNumMoveBits));\n+#define UPDATE_1(p) range -= bound; code -= bound; *(p) = (CLzmaProb)(ttt - (ttt >> kNumMoveBits));\n+#define GET_BIT2(p, i, A0, A1) IF_BIT_0(p) \\\n+  { UPDATE_0(p); i = (i + i); A0; } else \\\n+  { UPDATE_1(p); i = (i + i) + 1; A1; } \n+#define GET_BIT(p, i) GET_BIT2(p, i, ; , ;)               \n+\n+#define TREE_GET_BIT(probs, i) { GET_BIT((probs + i), i); }\n+#define TREE_DECODE(probs, limit, i) \\\n+  { i = 1; do { TREE_GET_BIT(probs, i); } while (i < limit); i -= limit; }\n+\n+/* #define _LZMA_SIZE_OPT */\n+\n+#ifdef _LZMA_SIZE_OPT\n+#define TREE_6_DECODE(probs, i) TREE_DECODE(probs, (1 << 6), i)\n+#else\n+#define TREE_6_DECODE(probs, i) \\\n+  { i = 1; \\\n+  TREE_GET_BIT(probs, i); \\\n+  TREE_GET_BIT(probs, i); \\\n+  TREE_GET_BIT(probs, i); \\\n+  TREE_GET_BIT(probs, i); \\\n+  TREE_GET_BIT(probs, i); \\\n+  TREE_GET_BIT(probs, i); \\\n+  i -= 0x40; }\n+#endif\n+\n+#define NORMALIZE_CHECK if (range < kTopValue) { if (buf >= bufLimit) return DUMMY_ERROR; range <<= 8; code = (code << 8) | (*buf++); }\n+\n+#define IF_BIT_0_CHECK(p) ttt = *(p); NORMALIZE_CHECK; bound = (range >> kNumBitModelTotalBits) * ttt; if (code < bound)\n+#define UPDATE_0_CHECK range = bound;\n+#define UPDATE_1_CHECK range -= bound; code -= bound;\n+#define GET_BIT2_CHECK(p, i, A0, A1) IF_BIT_0_CHECK(p) \\\n+  { UPDATE_0_CHECK; i = (i + i); A0; } else \\\n+  { UPDATE_1_CHECK; i = (i + i) + 1; A1; } \n+#define GET_BIT_CHECK(p, i) GET_BIT2_CHECK(p, i, ; , ;)               \n+#define TREE_DECODE_CHECK(probs, limit, i) \\\n+  { i = 1; do { GET_BIT_CHECK(probs + i, i) } while(i < limit); i -= limit; }\n+\n+\n+#define kNumPosBitsMax 4\n+#define kNumPosStatesMax (1 << kNumPosBitsMax)\n+\n+#define kLenNumLowBits 3\n+#define kLenNumLowSymbols (1 << kLenNumLowBits)\n+#define kLenNumMidBits 3\n+#define kLenNumMidSymbols (1 << kLenNumMidBits)\n+#define kLenNumHighBits 8\n+#define kLenNumHighSymbols (1 << kLenNumHighBits)\n+\n+#define LenChoice 0\n+#define LenChoice2 (LenChoice + 1)\n+#define LenLow (LenChoice2 + 1)\n+#define LenMid (LenLow + (kNumPosStatesMax << kLenNumLowBits))\n+#define LenHigh (LenMid + (kNumPosStatesMax << kLenNumMidBits))\n+#define kNumLenProbs (LenHigh + kLenNumHighSymbols) \n+\n+\n+#define kNumStates 12\n+#define kNumLitStates 7\n+\n+#define kStartPosModelIndex 4\n+#define kEndPosModelIndex 14\n+#define kNumFullDistances (1 << (kEndPosModelIndex >> 1))\n+\n+#define kNumPosSlotBits 6\n+#define kNumLenToPosStates 4\n+\n+#define kNumAlignBits 4\n+#define kAlignTableSize (1 << kNumAlignBits)\n+\n+#define kMatchMinLen 2\n+#define kMatchSpecLenStart (kMatchMinLen + kLenNumLowSymbols + kLenNumMidSymbols + kLenNumHighSymbols)\n+\n+#define IsMatch 0\n+#define IsRep (IsMatch + (kNumStates << kNumPosBitsMax))\n+#define IsRepG0 (IsRep + kNumStates)\n+#define IsRepG1 (IsRepG0 + kNumStates)\n+#define IsRepG2 (IsRepG1 + kNumStates)\n+#define IsRep0Long (IsRepG2 + kNumStates)\n+#define PosSlot (IsRep0Long + (kNumStates << kNumPosBitsMax))\n+#define SpecPos (PosSlot + (kNumLenToPosStates << kNumPosSlotBits))\n+#define Align (SpecPos + kNumFullDistances - kEndPosModelIndex)\n+#define LenCoder (Align + kAlignTableSize)\n+#define RepLenCoder (LenCoder + kNumLenProbs)\n+#define Literal (RepLenCoder + kNumLenProbs)\n+\n+#define LZMA_BASE_SIZE 1846\n+#define LZMA_LIT_SIZE 768\n+\n+#define LzmaProps_GetNumProbs(p) ((UInt32)LZMA_BASE_SIZE + (LZMA_LIT_SIZE << ((p)->lc + (p)->lp)))\n+\n+#if Literal != LZMA_BASE_SIZE\n+StopCompilingDueBUG\n+#endif\n+\n+/*\n+#define LZMA_STREAM_WAS_FINISHED_ID (-1)\n+#define LZMA_SPEC_LEN_OFFSET (-3)\n+*/\n+\n+Byte kLiteralNextStates[kNumStates * 2] = \n+{\n+  0, 0, 0, 0, 1, 2, 3,  4,  5,  6,  4,  5, \n+  7, 7, 7, 7, 7, 7, 7, 10, 10, 10, 10, 10\n+};\n+\n+#define LZMA_DIC_MIN (1 << 12)\n+\n+/* First LZMA-symbol is always decoded. \n+And it decodes new LZMA-symbols while (buf < bufLimit), but \"buf\" is without last normalization \n+Out:\n+  Result:\n+    0 - OK\n+    1 - Error\n+  p->remainLen:\n+    < kMatchSpecLenStart : normal remain\n+    = kMatchSpecLenStart : finished\n+    = kMatchSpecLenStart + 1 : Flush marker\n+    = kMatchSpecLenStart + 2 : State Init Marker\n+*/\n+\n+static int MY_FAST_CALL LzmaDec_DecodeReal(CLzmaDec *p, SizeT limit, const Byte *bufLimit)\n+{\n+  CLzmaProb *probs = p->probs;\n+\n+  unsigned state = p->state;\n+  UInt32 rep0 = p->reps[0], rep1 = p->reps[1], rep2 = p->reps[2], rep3 = p->reps[3];\n+  unsigned pbMask = ((unsigned)1 << (p->prop.pb)) - 1;\n+  unsigned lpMask = ((unsigned)1 << (p->prop.lp)) - 1;\n+  unsigned lc = p->prop.lc;\n+\n+  Byte *dic = p->dic;\n+  SizeT dicBufSize = p->dicBufSize;\n+  SizeT dicPos = p->dicPos;\n+  \n+  UInt32 processedPos = p->processedPos;\n+  UInt32 checkDicSize = p->checkDicSize;\n+  unsigned len = 0;\n+\n+  const Byte *buf = p->buf;\n+  UInt32 range = p->range;\n+  UInt32 code = p->code;\n+\n+  do\n+  {\n+    CLzmaProb *prob;\n+    UInt32 bound;\n+    unsigned ttt;\n+    unsigned posState = processedPos & pbMask;\n+\n+    prob = probs + IsMatch + (state << kNumPosBitsMax) + posState;\n+    IF_BIT_0(prob)\n+    {\n+      unsigned symbol;\n+      UPDATE_0(prob);\n+      prob = probs + Literal;\n+      if (checkDicSize != 0 || processedPos != 0)\n+        prob += (LZMA_LIT_SIZE * (((processedPos & lpMask) << lc) + \n+        (dic[(dicPos == 0 ? dicBufSize : dicPos) - 1] >> (8 - lc))));\n+\n+      if (state < kNumLitStates)\n+      {\n+        symbol = 1;\n+        do { GET_BIT(prob + symbol, symbol) } while (symbol < 0x100);\n+      }\n+      else\n+      {\n+        unsigned matchByte = p->dic[(dicPos - rep0) + ((dicPos < rep0) ? dicBufSize : 0)];\n+        unsigned offs = 0x100;\n+        symbol = 1;\n+        do\n+        {\n+          unsigned bit;\n+          CLzmaProb *probLit;\n+          matchByte <<= 1;\n+          bit = (matchByte & offs);\n+          probLit = prob + offs + bit + symbol;\n+          GET_BIT2(probLit, symbol, offs &= ~bit, offs &= bit)\n+        }\n+        while (symbol < 0x100);\n+      }\n+      dic[dicPos++] = (Byte)symbol;\n+      processedPos++;\n+\n+      state = kLiteralNextStates[state];\n+      /* if (state < 4) state = 0; else if (state < 10) state -= 3; else state -= 6; */\n+      continue;\n+    }\n+    else             \n+    {\n+      UPDATE_1(prob);\n+      prob = probs + IsRep + state;\n+      IF_BIT_0(prob)\n+      {\n+        UPDATE_0(prob);\n+        state += kNumStates;\n+        prob = probs + LenCoder;\n+      }\n+      else\n+      {\n+        UPDATE_1(prob);\n+        if (checkDicSize == 0 && processedPos == 0)\n+          return SZ_ERROR_DATA;\n+        prob = probs + IsRepG0 + state;\n+        IF_BIT_0(prob)\n+        {\n+          UPDATE_0(prob);\n+          prob = probs + IsRep0Long + (state << kNumPosBitsMax) + posState;\n+          IF_BIT_0(prob)\n+          {\n+            UPDATE_0(prob);\n+            dic[dicPos] = dic[(dicPos - rep0) + ((dicPos < rep0) ? dicBufSize : 0)];\n+            dicPos++;\n+            processedPos++;\n+            state = state < kNumLitStates ? 9 : 11;\n+            continue;\n+          }\n+          UPDATE_1(prob);\n+        }\n+        else\n+        {\n+          UInt32 distance;\n+          UPDATE_1(prob);\n+          prob = probs + IsRepG1 + state;\n+          IF_BIT_0(prob)\n+          {\n+            UPDATE_0(prob);\n+            distance = rep1;\n+          }\n+          else \n+          {\n+            UPDATE_1(prob);\n+            prob = probs + IsRepG2 + state;\n+            IF_BIT_0(prob)\n+            {\n+              UPDATE_0(prob);\n+              distance = rep2;\n+            }\n+            else\n+            {\n+              UPDATE_1(prob);\n+              distance = rep3;\n+              rep3 = rep2;\n+            }\n+            rep2 = rep1;\n+          }\n+          rep1 = rep0;\n+          rep0 = distance;\n+        }\n+        state = state < kNumLitStates ? 8 : 11;\n+        prob = probs + RepLenCoder;\n+      }\n+      {\n+        unsigned limit, offset;\n+        CLzmaProb *probLen = prob + LenChoice;\n+        IF_BIT_0(probLen)\n+        {\n+          UPDATE_0(probLen);\n+          probLen = prob + LenLow + (posState << kLenNumLowBits);\n+          offset = 0;\n+          limit = (1 << kLenNumLowBits);\n+        }\n+        else\n+        {\n+          UPDATE_1(probLen);\n+          probLen = prob + LenChoice2;\n+          IF_BIT_0(probLen)\n+          {\n+            UPDATE_0(probLen);\n+            probLen = prob + LenMid + (posState << kLenNumMidBits);\n+            offset = kLenNumLowSymbols;\n+            limit = (1 << kLenNumMidBits);\n+          }\n+          else\n+          {\n+            UPDATE_1(probLen);\n+            probLen = prob + LenHigh;\n+            offset = kLenNumLowSymbols + kLenNumMidSymbols;\n+            limit = (1 << kLenNumHighBits);\n+          }\n+        }\n+        TREE_DECODE(probLen, limit, len);\n+        len += offset;\n+      }\n+\n+      if (state >= kNumStates)\n+      {\n+        UInt32 distance;\n+        prob = probs + PosSlot +\n+            ((len < kNumLenToPosStates ? len : kNumLenToPosStates - 1) << kNumPosSlotBits);\n+        TREE_6_DECODE(prob, distance);\n+        if (distance >= kStartPosModelIndex)\n+        {\n+          unsigned posSlot = (unsigned)distance; \n+          int numDirectBits = (int)(((distance >> 1) - 1));\n+          distance = (2 | (distance & 1));\n+          if (posSlot < kEndPosModelIndex)\n+          {\n+            distance <<= numDirectBits;\n+            prob = probs + SpecPos + distance - posSlot - 1;\n+            {\n+              UInt32 mask = 1;\n+              unsigned i = 1;\n+              do\n+              {\n+                GET_BIT2(prob + i, i, ; , distance |= mask);\n+                mask <<= 1;\n+              }\n+              while(--numDirectBits != 0);\n+            }\n+          }\n+          else\n+          {\n+            numDirectBits -= kNumAlignBits;\n+            do\n+            {\n+              NORMALIZE\n+              range >>= 1;\n+              \n+              {\n+                UInt32 t;\n+                code -= range;\n+                t = (0 - ((UInt32)code >> 31)); /* (UInt32)((Int32)code >> 31) */\n+                distance = (distance << 1) + (t + 1);\n+                code += range & t;\n+              }\n+              /*\n+              distance <<= 1;\n+              if (code >= range)\n+              {\n+                code -= range;\n+                distance |= 1;\n+              }\n+              */\n+            }\n+            while (--numDirectBits != 0);\n+            prob = probs + Align;\n+            distance <<= kNumAlignBits;\n+            {\n+              unsigned i = 1;\n+              GET_BIT2(prob + i, i, ; , distance |= 1);\n+              GET_BIT2(prob + i, i, ; , distance |= 2);\n+              GET_BIT2(prob + i, i, ; , distance |= 4);\n+              GET_BIT2(prob + i, i, ; , distance |= 8);\n+            }\n+            if (distance == (UInt32)0xFFFFFFFF)\n+            {\n+              len += kMatchSpecLenStart;\n+              state -= kNumStates;\n+              break;\n+            }\n+          }\n+        }\n+        rep3 = rep2;\n+        rep2 = rep1;\n+        rep1 = rep0;\n+        rep0 = distance + 1; \n+        if (checkDicSize == 0)\n+        {\n+          if (distance >= processedPos)\n+            return SZ_ERROR_DATA;\n+        }\n+        else if (distance >= checkDicSize)\n+          return SZ_ERROR_DATA;\n+        state = (state < kNumStates + kNumLitStates) ? kNumLitStates : kNumLitStates + 3;\n+        /* state = kLiteralNextStates[state]; */\n+      }\n+\n+      len += kMatchMinLen;\n+\n+      {\n+        SizeT rem = limit - dicPos;\n+        unsigned curLen = ((rem < len) ? (unsigned)rem : len);\n+        SizeT pos = (dicPos - rep0) + ((dicPos < rep0) ? dicBufSize : 0);\n+\n+        processedPos += curLen;\n+\n+        len -= curLen;\n+        if (pos + curLen <= dicBufSize)\n+        {\n+          Byte *dest = dic + dicPos;\n+          ptrdiff_t src = (ptrdiff_t)pos - (ptrdiff_t)dicPos;\n+          const Byte *lim = dest + curLen;\n+          dicPos += curLen;\n+          do \n+            *(dest) = (Byte)*(dest + src); \n+          while (++dest != lim);\n+        }\n+        else\n+        {\n+          do\n+          {\n+            dic[dicPos++] = dic[pos];\n+            if (++pos == dicBufSize)\n+              pos = 0;\n+          }\n+          while (--curLen != 0);\n+        }\n+      }\n+    }\n+  }\n+  while (dicPos < limit && buf < bufLimit);\n+  NORMALIZE;\n+  p->buf = buf;\n+  p->range = range;\n+  p->code = code;\n+  p->remainLen = len;\n+  p->dicPos = dicPos;\n+  p->processedPos = processedPos;\n+  p->reps[0] = rep0;\n+  p->reps[1] = rep1;\n+  p->reps[2] = rep2;\n+  p->reps[3] = rep3;\n+  p->state = state;\n+\n+  return SZ_OK;\n+}\n+\n+static void MY_FAST_CALL LzmaDec_WriteRem(CLzmaDec *p, SizeT limit)\n+{\n+  if (p->remainLen != 0 && p->remainLen < kMatchSpecLenStart)\n+  {\n+    Byte *dic = p->dic;\n+    SizeT dicPos = p->dicPos;\n+    SizeT dicBufSize = p->dicBufSize;\n+    unsigned len = p->remainLen;\n+    UInt32 rep0 = p->reps[0];\n+    if (limit - dicPos < len)\n+      len = (unsigned)(limit - dicPos);\n+\n+    if (p->checkDicSize == 0 && p->prop.dicSize - p->processedPos <= len)\n+      p->checkDicSize = p->prop.dicSize;\n+\n+    p->processedPos += len;\n+    p->remainLen -= len;\n+    while (len-- != 0)\n+    {\n+      dic[dicPos] = dic[(dicPos - rep0) + ((dicPos < rep0) ? dicBufSize : 0)];\n+      dicPos++;\n+    }\n+    p->dicPos = dicPos;\n+  }\n+}\n+\n+/* LzmaDec_DecodeReal2 decodes LZMA-symbols and sets p->needFlush and p->needInit, if required. */\n+\n+static int MY_FAST_CALL LzmaDec_DecodeReal2(CLzmaDec *p, SizeT limit, const Byte *bufLimit)\n+{\n+  do\n+  {\n+    SizeT limit2 = limit;\n+    if (p->checkDicSize == 0)\n+    {\n+      UInt32 rem = p->prop.dicSize - p->processedPos;\n+      if (limit - p->dicPos > rem)\n+        limit2 = p->dicPos + rem;\n+    }\n+    RINOK(LzmaDec_DecodeReal(p, limit2, bufLimit));\n+    if (p->processedPos >= p->prop.dicSize)\n+      p->checkDicSize = p->prop.dicSize;\n+    LzmaDec_WriteRem(p, limit);\n+  }\n+  while (p->dicPos < limit && p->buf < bufLimit && p->remainLen < kMatchSpecLenStart);\n+\n+  if (p->remainLen > kMatchSpecLenStart)\n+  {\n+    p->remainLen = kMatchSpecLenStart;\n+  }\n+  return 0;\n+}\n+\n+typedef enum \n+{\n+  DUMMY_ERROR, /* unexpected end of input stream */\n+  DUMMY_LIT,\n+  DUMMY_MATCH,\n+  DUMMY_REP\n+} ELzmaDummy;\n+\n+static ELzmaDummy LzmaDec_TryDummy(const CLzmaDec *p, const Byte *buf, SizeT inSize)\n+{\n+  UInt32 range = p->range;\n+  UInt32 code = p->code;\n+  const Byte *bufLimit = buf + inSize;\n+  CLzmaProb *probs = p->probs;\n+  unsigned state = p->state;\n+  ELzmaDummy res;\n+\n+  {\n+    CLzmaProb *prob;\n+    UInt32 bound;\n+    unsigned ttt;\n+    unsigned posState = (p->processedPos) & ((1 << p->prop.pb) - 1);\n+\n+    prob = probs + IsMatch + (state << kNumPosBitsMax) + posState;\n+    IF_BIT_0_CHECK(prob)\n+    {\n+      UPDATE_0_CHECK\n+\n+      /* if (bufLimit - buf >= 7) return DUMMY_LIT; */\n+\n+      prob = probs + Literal;\n+      if (p->checkDicSize != 0 || p->processedPos != 0)\n+        prob += (LZMA_LIT_SIZE * \n+          ((((p->processedPos) & ((1 << (p->prop.lp)) - 1)) << p->prop.lc) + \n+          (p->dic[(p->dicPos == 0 ? p->dicBufSize : p->dicPos) - 1] >> (8 - p->prop.lc))));\n+\n+      if (state < kNumLitStates)\n+      {\n+        unsigned symbol = 1;\n+        do { GET_BIT_CHECK(prob + symbol, symbol) } while (symbol < 0x100);\n+      }\n+      else\n+      {\n+        unsigned matchByte = p->dic[p->dicPos - p->reps[0] + \n+            ((p->dicPos < p->reps[0]) ? p->dicBufSize : 0)];\n+        unsigned offs = 0x100;\n+        unsigned symbol = 1;\n+        do\n+        {\n+          unsigned bit;\n+          CLzmaProb *probLit;\n+          matchByte <<= 1;\n+          bit = (matchByte & offs);\n+          probLit = prob + offs + bit + symbol;\n+          GET_BIT2_CHECK(probLit, symbol, offs &= ~bit, offs &= bit)\n+        }\n+        while (symbol < 0x100);\n+      }\n+      res = DUMMY_LIT;\n+    }\n+    else             \n+    {\n+      unsigned len;\n+      UPDATE_1_CHECK;\n+\n+      prob = probs + IsRep + state;\n+      IF_BIT_0_CHECK(prob)\n+      {\n+        UPDATE_0_CHECK;\n+        state = 0;\n+        prob = probs + LenCoder;\n+        res = DUMMY_MATCH;\n+      }\n+      else\n+      {\n+        UPDATE_1_CHECK;\n+        res = DUMMY_REP;\n+        prob = probs + IsRepG0 + state;\n+        IF_BIT_0_CHECK(prob)\n+        {\n+          UPDATE_0_CHECK;\n+          prob = probs + IsRep0Long + (state << kNumPosBitsMax) + posState;\n+          IF_BIT_0_CHECK(prob)\n+          {\n+            UPDATE_0_CHECK;\n+            NORMALIZE_CHECK;\n+            return DUMMY_REP;\n+          }\n+          else\n+          {\n+            UPDATE_1_CHECK;\n+          }\n+        }\n+        else\n+        {\n+          UPDATE_1_CHECK;\n+          prob = probs + IsRepG1 + state;\n+          IF_BIT_0_CHECK(prob)\n+          {\n+            UPDATE_0_CHECK;\n+          }\n+          else \n+          {\n+            UPDATE_1_CHECK;\n+            prob = probs + IsRepG2 + state;\n+            IF_BIT_0_CHECK(prob)\n+            {\n+              UPDATE_0_CHECK;\n+            }\n+            else\n+            {\n+              UPDATE_1_CHECK;\n+            }\n+          }\n+        }\n+        state = kNumStates;\n+        prob = probs + RepLenCoder;\n+      }\n+      {\n+        unsigned limit, offset;\n+        CLzmaProb *probLen = prob + LenChoice;\n+        IF_BIT_0_CHECK(probLen)\n+        {\n+          UPDATE_0_CHECK;\n+          probLen = prob + LenLow + (posState << kLenNumLowBits);\n+          offset = 0;\n+          limit = 1 << kLenNumLowBits;\n+        }\n+        else\n+        {\n+          UPDATE_1_CHECK;\n+          probLen = prob + LenChoice2;\n+          IF_BIT_0_CHECK(probLen)\n+          {\n+            UPDATE_0_CHECK;\n+            probLen = prob + LenMid + (posState << kLenNumMidBits);\n+            offset = kLenNumLowSymbols;\n+            limit = 1 << kLenNumMidBits;\n+          }\n+          else\n+          {\n+            UPDATE_1_CHECK;\n+            probLen = prob + LenHigh;\n+            offset = kLenNumLowSymbols + kLenNumMidSymbols;\n+            limit = 1 << kLenNumHighBits;\n+          }\n+        }\n+        TREE_DECODE_CHECK(probLen, limit, len);\n+        len += offset;\n+      }\n+\n+      if (state < 4)\n+      {\n+        unsigned posSlot;\n+        prob = probs + PosSlot +\n+            ((len < kNumLenToPosStates ? len : kNumLenToPosStates - 1) << \n+            kNumPosSlotBits);\n+        TREE_DECODE_CHECK(prob, 1 << kNumPosSlotBits, posSlot);\n+        if (posSlot >= kStartPosModelIndex)\n+        {\n+          int numDirectBits = ((posSlot >> 1) - 1);\n+\n+          /* if (bufLimit - buf >= 8) return DUMMY_MATCH; */\n+\n+          if (posSlot < kEndPosModelIndex)\n+          {\n+            prob = probs + SpecPos + ((2 | (posSlot & 1)) << numDirectBits) - posSlot - 1;\n+          }\n+          else\n+          {\n+            numDirectBits -= kNumAlignBits;\n+            do\n+            {\n+              NORMALIZE_CHECK\n+              range >>= 1;\n+              code -= range & (((code - range) >> 31) - 1);\n+              /* if (code >= range) code -= range; */\n+            }\n+            while (--numDirectBits != 0);\n+            prob = probs + Align;\n+            numDirectBits = kNumAlignBits;\n+          }\n+          {\n+            unsigned i = 1;\n+            do\n+            {\n+              GET_BIT_CHECK(prob + i, i);\n+            }\n+            while(--numDirectBits != 0);\n+          }\n+        }\n+      }\n+    }\n+  }\n+  NORMALIZE_CHECK;\n+  return res;\n+}\n+\n+\n+static void LzmaDec_InitRc(CLzmaDec *p, const Byte *data)\n+{\n+  p->code = ((UInt32)data[1] << 24) | ((UInt32)data[2] << 16) | ((UInt32)data[3] << 8) | ((UInt32)data[4]);\n+  p->range = 0xFFFFFFFF;\n+  p->needFlush = 0;\n+}\n+\n+static void LzmaDec_InitDicAndState(CLzmaDec *p, Bool initDic, Bool initState) \n+{ \n+  p->needFlush = 1; \n+  p->remainLen = 0; \n+  p->tempBufSize = 0; \n+\n+  if (initDic)\n+  {\n+    p->processedPos = 0;\n+    p->checkDicSize = 0;\n+    p->needInitState = 1;\n+  }\n+  if (initState)\n+    p->needInitState = 1;\n+}\n+\n+void LzmaDec_Init(CLzmaDec *p) \n+{ \n+  p->dicPos = 0; \n+  LzmaDec_InitDicAndState(p, True, True);\n+}\n+\n+static void LzmaDec_InitStateReal(CLzmaDec *p)\n+{\n+  UInt32 numProbs = Literal + ((UInt32)LZMA_LIT_SIZE << (p->prop.lc + p->prop.lp));\n+  UInt32 i;\n+  CLzmaProb *probs = p->probs;\n+  for (i = 0; i < numProbs; i++)\n+    probs[i] = kBitModelTotal >> 1; \n+  p->reps[0] = p->reps[1] = p->reps[2] = p->reps[3] = 1;\n+  p->state = 0;\n+  p->needInitState = 0;\n+}\n+\n+SRes LzmaDec_DecodeToDic(CLzmaDec *p, SizeT dicLimit, const Byte *src, SizeT *srcLen, \n+    ELzmaFinishMode finishMode, ELzmaStatus *status)\n+{\n+  SizeT inSize = *srcLen;\n+  (*srcLen) = 0;\n+  LzmaDec_WriteRem(p, dicLimit);\n+  \n+  *status = LZMA_STATUS_NOT_SPECIFIED;\n+\n+  while (p->remainLen != kMatchSpecLenStart)\n+  {\n+      int checkEndMarkNow;\n+\n+      if (p->needFlush != 0)\n+      {\n+        for (; inSize > 0 && p->tempBufSize < RC_INIT_SIZE; (*srcLen)++, inSize--)\n+          p->tempBuf[p->tempBufSize++] = *src++;\n+        if (p->tempBufSize < RC_INIT_SIZE)\n+        {\n+          *status = LZMA_STATUS_NEEDS_MORE_INPUT;\n+          return SZ_OK;\n+        }\n+        if (p->tempBuf[0] != 0)\n+          return SZ_ERROR_DATA;\n+\n+        LzmaDec_InitRc(p, p->tempBuf);\n+        p->tempBufSize = 0;\n+      }\n+\n+      checkEndMarkNow = 0;\n+      if (p->dicPos >= dicLimit)\n+      {\n+        if (p->remainLen == 0 && p->code == 0)\n+        {\n+          *status = LZMA_STATUS_MAYBE_FINISHED_WITHOUT_MARK;\n+          return SZ_OK;\n+        }\n+        if (finishMode == LZMA_FINISH_ANY)\n+        {\n+          *status = LZMA_STATUS_NOT_FINISHED;\n+          return SZ_OK;\n+        }\n+        if (p->remainLen != 0)\n+        {\n+          *status = LZMA_STATUS_NOT_FINISHED;\n+          return SZ_ERROR_DATA;\n+        }\n+        checkEndMarkNow = 1;\n+      }\n+\n+      if (p->needInitState)\n+        LzmaDec_InitStateReal(p);\n+  \n+      if (p->tempBufSize == 0)\n+      {\n+        SizeT processed;\n+        const Byte *bufLimit;\n+        if (inSize < LZMA_REQUIRED_INPUT_MAX || checkEndMarkNow)\n+        {\n+          int dummyRes = LzmaDec_TryDummy(p, src, inSize);\n+          if (dummyRes == DUMMY_ERROR)\n+          {\n+            memcpy(p->tempBuf, src, inSize);\n+            p->tempBufSize = (unsigned)inSize;\n+            (*srcLen) += inSize;\n+            *status = LZMA_STATUS_NEEDS_MORE_INPUT;\n+            return SZ_OK;\n+          }\n+          if (checkEndMarkNow && dummyRes != DUMMY_MATCH)\n+          {\n+            *status = LZMA_STATUS_NOT_FINISHED;\n+            return SZ_ERROR_DATA;\n+          }\n+          bufLimit = src;\n+        }\n+        else\n+          bufLimit = src + inSize - LZMA_REQUIRED_INPUT_MAX;\n+        p->buf = src;\n+        if (LzmaDec_DecodeReal2(p, dicLimit, bufLimit) != 0)\n+          return SZ_ERROR_DATA;\n+        processed = p->buf - src;\n+        (*srcLen) += processed;\n+        src += processed;\n+        inSize -= processed;\n+      }\n+      else\n+      {\n+        unsigned rem = p->tempBufSize, lookAhead = 0;\n+        while (rem < LZMA_REQUIRED_INPUT_MAX && lookAhead < inSize)\n+          p->tempBuf[rem++] = src[lookAhead++];\n+        p->tempBufSize = rem;\n+        if (rem < LZMA_REQUIRED_INPUT_MAX || checkEndMarkNow)\n+        {\n+          int dummyRes = LzmaDec_TryDummy(p, p->tempBuf, rem);\n+          if (dummyRes == DUMMY_ERROR)\n+          {\n+            (*srcLen) += lookAhead;\n+            *status = LZMA_STATUS_NEEDS_MORE_INPUT;\n+            return SZ_OK;\n+          }\n+          if (checkEndMarkNow && dummyRes != DUMMY_MATCH)\n+          {\n+            *status = LZMA_STATUS_NOT_FINISHED;\n+            return SZ_ERROR_DATA;\n+          }\n+        }\n+        p->buf = p->tempBuf;\n+        if (LzmaDec_DecodeReal2(p, dicLimit, p->buf) != 0)\n+          return SZ_ERROR_DATA;\n+        lookAhead -= (rem - (unsigned)(p->buf - p->tempBuf));\n+        (*srcLen) += lookAhead;\n+        src += lookAhead;\n+        inSize -= lookAhead;\n+        p->tempBufSize = 0;\n+      }\n+  }\n+  if (p->code == 0) \n+    *status = LZMA_STATUS_FINISHED_WITH_MARK;\n+  return (p->code == 0) ? SZ_OK : SZ_ERROR_DATA;\n+}\n+\n+SRes LzmaDec_DecodeToBuf(CLzmaDec *p, Byte *dest, SizeT *destLen, const Byte *src, SizeT *srcLen, ELzmaFinishMode finishMode, ELzmaStatus *status)\n+{\n+  SizeT outSize = *destLen;\n+  SizeT inSize = *srcLen;\n+  *srcLen = *destLen = 0;\n+  for (;;)\n+  {\n+    SizeT inSizeCur = inSize, outSizeCur, dicPos;\n+    ELzmaFinishMode curFinishMode;\n+    SRes res;\n+    if (p->dicPos == p->dicBufSize)\n+      p->dicPos = 0;\n+    dicPos = p->dicPos;\n+    if (outSize > p->dicBufSize - dicPos)\n+    {\n+      outSizeCur = p->dicBufSize;\n+      curFinishMode = LZMA_FINISH_ANY;\n+    }\n+    else\n+    {\n+      outSizeCur = dicPos + outSize;\n+      curFinishMode = finishMode;\n+    }\n+\n+    res = LzmaDec_DecodeToDic(p, outSizeCur, src, &inSizeCur, curFinishMode, status);\n+    src += inSizeCur;\n+    inSize -= inSizeCur;\n+    *srcLen += inSizeCur;\n+    outSizeCur = p->dicPos - dicPos;\n+    memcpy(dest, p->dic + dicPos, outSizeCur);\n+    dest += outSizeCur;\n+    outSize -= outSizeCur;\n+    *destLen += outSizeCur;\n+    if (res != 0)\n+      return res;\n+    if (outSizeCur == 0 || outSize == 0)\n+      return SZ_OK;\n+  }\n+}\n+\n+void LzmaDec_FreeProbs(CLzmaDec *p, ISzAlloc *alloc) \n+{ \n+  alloc->Free(alloc, p->probs);  \n+  p->probs = 0; \n+}\n+\n+static void LzmaDec_FreeDict(CLzmaDec *p, ISzAlloc *alloc) \n+{ \n+  alloc->Free(alloc, p->dic); \n+  p->dic = 0; \n+}\n+\n+void LzmaDec_Free(CLzmaDec *p, ISzAlloc *alloc)\n+{\n+  LzmaDec_FreeProbs(p, alloc);\n+  LzmaDec_FreeDict(p, alloc);\n+}\n+\n+SRes LzmaProps_Decode(CLzmaProps *p, const Byte *data, unsigned size)\n+{\n+  UInt32 dicSize; \n+  Byte d;\n+  \n+  if (size < LZMA_PROPS_SIZE)\n+    return SZ_ERROR_UNSUPPORTED;\n+  else\n+    dicSize = data[1] | ((UInt32)data[2] << 8) | ((UInt32)data[3] << 16) | ((UInt32)data[4] << 24);\n+ \n+  if (dicSize < LZMA_DIC_MIN)\n+    dicSize = LZMA_DIC_MIN;\n+  p->dicSize = dicSize;\n+\n+  d = data[0];\n+  if (d >= (9 * 5 * 5))\n+    return SZ_ERROR_UNSUPPORTED;\n+\n+  p->lc = d % 9;\n+  d /= 9;\n+  p->pb = d / 5;\n+  p->lp = d % 5;\n+\n+  return SZ_OK;\n+}\n+\n+static SRes LzmaDec_AllocateProbs2(CLzmaDec *p, const CLzmaProps *propNew, ISzAlloc *alloc)\n+{\n+  UInt32 numProbs = LzmaProps_GetNumProbs(propNew);\n+  if (p->probs == 0 || numProbs != p->numProbs)\n+  {\n+    LzmaDec_FreeProbs(p, alloc);\n+    p->probs = (CLzmaProb *)alloc->Alloc(alloc, numProbs * sizeof(CLzmaProb));\n+    p->numProbs = numProbs;\n+    if (p->probs == 0)\n+      return SZ_ERROR_MEM;\n+  }\n+  return SZ_OK;\n+}\n+\n+SRes LzmaDec_AllocateProbs(CLzmaDec *p, const Byte *props, unsigned propsSize, ISzAlloc *alloc)\n+{\n+  CLzmaProps propNew;\n+  RINOK(LzmaProps_Decode(&propNew, props, propsSize));\n+  RINOK(LzmaDec_AllocateProbs2(p, &propNew, alloc));\n+  p->prop = propNew;\n+  return SZ_OK;\n+}\n+\n+SRes LzmaDec_Allocate(CLzmaDec *p, const Byte *props, unsigned propsSize, ISzAlloc *alloc)\n+{\n+  CLzmaProps propNew;\n+  SizeT dicBufSize;\n+  RINOK(LzmaProps_Decode(&propNew, props, propsSize));\n+  RINOK(LzmaDec_AllocateProbs2(p, &propNew, alloc));\n+  dicBufSize = propNew.dicSize;\n+  if (p->dic == 0 || dicBufSize != p->dicBufSize)\n+  {\n+    LzmaDec_FreeDict(p, alloc);\n+    p->dic = (Byte *)alloc->Alloc(alloc, dicBufSize);\n+    if (p->dic == 0)\n+    {\n+      LzmaDec_FreeProbs(p, alloc);\n+      return SZ_ERROR_MEM;\n+    }\n+  }\n+  p->dicBufSize = dicBufSize;\n+  p->prop = propNew;\n+  return SZ_OK;\n+}\n+\n+SRes LzmaDecode(Byte *dest, SizeT *destLen, const Byte *src, SizeT *srcLen,\n+    const Byte *propData, unsigned propSize, ELzmaFinishMode finishMode, \n+    ELzmaStatus *status, ISzAlloc *alloc)\n+{\n+  CLzmaDec p;\n+  SRes res;\n+  SizeT inSize = *srcLen;\n+  SizeT outSize = *destLen;\n+  *srcLen = *destLen = 0;\n+  if (inSize < RC_INIT_SIZE)\n+    return SZ_ERROR_INPUT_EOF;\n+\n+  LzmaDec_Construct(&p);\n+  res = LzmaDec_AllocateProbs(&p, propData, propSize, alloc);\n+  if (res != 0)\n+    return res;\n+  p.dic = dest;\n+  p.dicBufSize = outSize;\n+\n+  LzmaDec_Init(&p);\n+  \n+  *srcLen = inSize;\n+  res = LzmaDec_DecodeToDic(&p, outSize, src, srcLen, finishMode, status);\n+\n+  if (res == SZ_OK && *status == LZMA_STATUS_NEEDS_MORE_INPUT)\n+    res = SZ_ERROR_INPUT_EOF;\n+\n+  (*destLen) = p.dicPos;\n+  LzmaDec_FreeProbs(&p, alloc);\n+  return res;\n+}\n--- /dev/null\n+++ b/jffsX-utils/lzma/LzmaEnc.c\n@@ -0,0 +1,2335 @@\n+/* LzmaEnc.c -- LZMA Encoder\n+2008-04-28\n+Copyright (c) 1999-2008 Igor Pavlov\n+Read LzmaEnc.h for license options */\n+\n+#if defined(SHOW_STAT) || defined(SHOW_STAT2)\n+#include <stdio.h>\n+#endif\n+\n+#include <string.h>\n+\n+#include \"LzmaEnc.h\"\n+\n+#include \"LzFind.h\"\n+#ifdef COMPRESS_MF_MT\n+#include \"LzFindMt.h\"\n+#endif\n+\n+/* #define SHOW_STAT */\n+/* #define SHOW_STAT2 */\n+\n+#ifdef SHOW_STAT\n+static int ttt = 0;\n+#endif\n+\n+#define kBlockSizeMax ((1 << LZMA_NUM_BLOCK_SIZE_BITS) - 1)\n+\n+#define kBlockSize (9 << 10)\n+#define kUnpackBlockSize (1 << 18)\n+#define kMatchArraySize (1 << 21)\n+#define kMatchRecordMaxSize ((LZMA_MATCH_LEN_MAX * 2 + 3) * LZMA_MATCH_LEN_MAX)\n+\n+#define kNumMaxDirectBits (31)\n+\n+#define kNumTopBits 24\n+#define kTopValue ((UInt32)1 << kNumTopBits)\n+\n+#define kNumBitModelTotalBits 11\n+#define kBitModelTotal (1 << kNumBitModelTotalBits)\n+#define kNumMoveBits 5\n+#define kProbInitValue (kBitModelTotal >> 1)\n+\n+#define kNumMoveReducingBits 4\n+#define kNumBitPriceShiftBits 4\n+#define kBitPrice (1 << kNumBitPriceShiftBits)\n+\n+void LzmaEncProps_Init(CLzmaEncProps *p)\n+{\n+  p->level = 5;\n+  p->dictSize = p->mc = 0;\n+  p->lc = p->lp = p->pb = p->algo = p->fb = p->btMode = p->numHashBytes = p->numThreads = -1;\n+  p->writeEndMark = 0;\n+}\n+\n+void LzmaEncProps_Normalize(CLzmaEncProps *p)\n+{\n+  int level = p->level;\n+  if (level < 0) level = 5;\n+  p->level = level;\n+  if (p->dictSize == 0) p->dictSize = (level <= 5 ? (1 << (level * 2 + 14)) : (level == 6 ? (1 << 25) : (1 << 26)));\n+  if (p->lc < 0) p->lc = 3; \n+  if (p->lp < 0) p->lp = 0; \n+  if (p->pb < 0) p->pb = 2; \n+  if (p->algo < 0) p->algo = (level < 5 ? 0 : 1); \n+  if (p->fb < 0) p->fb = (level < 7 ? 32 : 64); \n+  if (p->btMode < 0) p->btMode = (p->algo == 0 ? 0 : 1); \n+  if (p->numHashBytes < 0) p->numHashBytes = 4; \n+  if (p->mc == 0)  p->mc = (16 + (p->fb >> 1)) >> (p->btMode ? 0 : 1);\n+  if (p->numThreads < 0) p->numThreads = ((p->btMode && p->algo) ? 2 : 1);\n+}\n+\n+UInt32 LzmaEncProps_GetDictSize(const CLzmaEncProps *props2)\n+{\n+  CLzmaEncProps props = *props2;\n+  LzmaEncProps_Normalize(&props);\n+  return props.dictSize;\n+}\n+\n+/* #define LZMA_LOG_BSR */\n+/* Define it for Intel's CPU */\n+\n+\n+#ifdef LZMA_LOG_BSR\n+\n+#define kDicLogSizeMaxCompress 30\n+\n+#define BSR2_RET(pos, res) { unsigned long i; _BitScanReverse(&i, (pos)); res = (i + i) + ((pos >> (i - 1)) & 1); }\n+\n+UInt32 GetPosSlot1(UInt32 pos) \n+{ \n+  UInt32 res; \n+  BSR2_RET(pos, res); \n+  return res; \n+}\n+#define GetPosSlot2(pos, res) { BSR2_RET(pos, res); }\n+#define GetPosSlot(pos, res) { if (pos < 2) res = pos; else BSR2_RET(pos, res); }\n+\n+#else\n+\n+#define kNumLogBits (9 + (int)sizeof(size_t) / 2)\n+#define kDicLogSizeMaxCompress ((kNumLogBits - 1) * 2 + 7)\n+\n+static void LzmaEnc_FastPosInit(Byte *g_FastPos)\n+{\n+  int c = 2, slotFast;\n+  g_FastPos[0] = 0;\n+  g_FastPos[1] = 1;\n+  \n+  for (slotFast = 2; slotFast < kNumLogBits * 2; slotFast++)\n+  {\n+    UInt32 k = (1 << ((slotFast >> 1) - 1));\n+    UInt32 j;\n+    for (j = 0; j < k; j++, c++)\n+      g_FastPos[c] = (Byte)slotFast;\n+  }\n+}\n+\n+#define BSR2_RET(pos, res) { UInt32 i = 6 + ((kNumLogBits - 1) & \\\n+  (0 - (((((UInt32)1 << (kNumLogBits + 6)) - 1) - pos) >> 31))); \\\n+  res = p->g_FastPos[pos >> i] + (i * 2); }\n+/*\n+#define BSR2_RET(pos, res) { res = (pos < (1 << (kNumLogBits + 6))) ? \\\n+  p->g_FastPos[pos >> 6] + 12 : \\\n+  p->g_FastPos[pos >> (6 + kNumLogBits - 1)] + (6 + (kNumLogBits - 1)) * 2; }\n+*/\n+\n+#define GetPosSlot1(pos) p->g_FastPos[pos]\n+#define GetPosSlot2(pos, res) { BSR2_RET(pos, res); }\n+#define GetPosSlot(pos, res) { if (pos < kNumFullDistances) res = p->g_FastPos[pos]; else BSR2_RET(pos, res); }\n+\n+#endif\n+\n+\n+#define LZMA_NUM_REPS 4\n+\n+typedef unsigned CState;\n+\n+typedef struct _COptimal\n+{\n+  UInt32 price;    \n+\n+  CState state;\n+  int prev1IsChar;\n+  int prev2;\n+\n+  UInt32 posPrev2;\n+  UInt32 backPrev2;     \n+\n+  UInt32 posPrev;\n+  UInt32 backPrev;     \n+  UInt32 backs[LZMA_NUM_REPS];\n+} COptimal;\n+\n+#define kNumOpts (1 << 12)\n+\n+#define kNumLenToPosStates 4\n+#define kNumPosSlotBits 6 \n+#define kDicLogSizeMin 0 \n+#define kDicLogSizeMax 32 \n+#define kDistTableSizeMax (kDicLogSizeMax * 2)\n+\n+\n+#define kNumAlignBits 4\n+#define kAlignTableSize (1 << kNumAlignBits)\n+#define kAlignMask (kAlignTableSize - 1)\n+\n+#define kStartPosModelIndex 4\n+#define kEndPosModelIndex 14\n+#define kNumPosModels (kEndPosModelIndex - kStartPosModelIndex)\n+\n+#define kNumFullDistances (1 << (kEndPosModelIndex / 2))\n+\n+#ifdef _LZMA_PROB32\n+#define CLzmaProb UInt32\n+#else\n+#define CLzmaProb UInt16\n+#endif\n+\n+#define LZMA_PB_MAX 4\n+#define LZMA_LC_MAX 8\n+#define LZMA_LP_MAX 4\n+\n+#define LZMA_NUM_PB_STATES_MAX (1 << LZMA_PB_MAX)\n+\n+\n+#define kLenNumLowBits 3\n+#define kLenNumLowSymbols (1 << kLenNumLowBits)\n+#define kLenNumMidBits 3\n+#define kLenNumMidSymbols (1 << kLenNumMidBits)\n+#define kLenNumHighBits 8\n+#define kLenNumHighSymbols (1 << kLenNumHighBits)\n+\n+#define kLenNumSymbolsTotal (kLenNumLowSymbols + kLenNumMidSymbols + kLenNumHighSymbols)\n+\n+#define LZMA_MATCH_LEN_MIN 2\n+#define LZMA_MATCH_LEN_MAX (LZMA_MATCH_LEN_MIN + kLenNumSymbolsTotal - 1)\n+\n+#define kNumStates 12\n+\n+typedef struct\n+{\n+  CLzmaProb choice;\n+  CLzmaProb choice2;\n+  CLzmaProb low[LZMA_NUM_PB_STATES_MAX << kLenNumLowBits];\n+  CLzmaProb mid[LZMA_NUM_PB_STATES_MAX << kLenNumMidBits];\n+  CLzmaProb high[kLenNumHighSymbols];\n+} CLenEnc;\n+\n+typedef struct\n+{\n+  CLenEnc p;\n+  UInt32 prices[LZMA_NUM_PB_STATES_MAX][kLenNumSymbolsTotal];\n+  UInt32 tableSize;\n+  UInt32 counters[LZMA_NUM_PB_STATES_MAX];\n+} CLenPriceEnc;\n+\n+typedef struct _CRangeEnc\n+{\n+  UInt32 range;\n+  Byte cache;\n+  UInt64 low;\n+  UInt64 cacheSize;\n+  Byte *buf;\n+  Byte *bufLim;\n+  Byte *bufBase;\n+  ISeqOutStream *outStream;\n+  UInt64 processed;\n+  SRes res;\n+} CRangeEnc;\n+\n+typedef struct _CSeqInStreamBuf\n+{\n+  ISeqInStream funcTable;\n+  const Byte *data;\n+  SizeT rem;\n+} CSeqInStreamBuf;\n+\n+static SRes MyRead(void *pp, void *data, size_t *size)\n+{\n+  size_t curSize = *size;\n+  CSeqInStreamBuf *p = (CSeqInStreamBuf *)pp;\n+  if (p->rem < curSize)\n+    curSize = p->rem;\n+  memcpy(data, p->data, curSize);\n+  p->rem -= curSize;\n+  p->data += curSize;\n+  *size = curSize;\n+  return SZ_OK;\n+}\n+\n+typedef struct \n+{\n+  CLzmaProb *litProbs;\n+\n+  CLzmaProb isMatch[kNumStates][LZMA_NUM_PB_STATES_MAX];\n+  CLzmaProb isRep[kNumStates];\n+  CLzmaProb isRepG0[kNumStates];\n+  CLzmaProb isRepG1[kNumStates];\n+  CLzmaProb isRepG2[kNumStates];\n+  CLzmaProb isRep0Long[kNumStates][LZMA_NUM_PB_STATES_MAX];\n+\n+  CLzmaProb posSlotEncoder[kNumLenToPosStates][1 << kNumPosSlotBits];\n+  CLzmaProb posEncoders[kNumFullDistances - kEndPosModelIndex];\n+  CLzmaProb posAlignEncoder[1 << kNumAlignBits];\n+  \n+  CLenPriceEnc lenEnc;\n+  CLenPriceEnc repLenEnc;\n+\n+  UInt32 reps[LZMA_NUM_REPS];\n+  UInt32 state;\n+} CSaveState;\n+\n+typedef struct _CLzmaEnc\n+{\n+  IMatchFinder matchFinder;\n+  void *matchFinderObj;\n+\n+  #ifdef COMPRESS_MF_MT\n+  Bool mtMode;\n+  CMatchFinderMt matchFinderMt;\n+  #endif\n+\n+  CMatchFinder matchFinderBase;\n+\n+  #ifdef COMPRESS_MF_MT\n+  Byte pad[128];\n+  #endif\n+  \n+  UInt32 optimumEndIndex;\n+  UInt32 optimumCurrentIndex;\n+\n+  Bool longestMatchWasFound;\n+  UInt32 longestMatchLength;    \n+  UInt32 numDistancePairs;\n+\n+  COptimal opt[kNumOpts];\n+  \n+  #ifndef LZMA_LOG_BSR\n+  Byte g_FastPos[1 << kNumLogBits];\n+  #endif\n+\n+  UInt32 ProbPrices[kBitModelTotal >> kNumMoveReducingBits];\n+  UInt32 matchDistances[LZMA_MATCH_LEN_MAX * 2 + 2 + 1];\n+  UInt32 numFastBytes;\n+  UInt32 additionalOffset;\n+  UInt32 reps[LZMA_NUM_REPS];\n+  UInt32 state;\n+\n+  UInt32 posSlotPrices[kNumLenToPosStates][kDistTableSizeMax];\n+  UInt32 distancesPrices[kNumLenToPosStates][kNumFullDistances];\n+  UInt32 alignPrices[kAlignTableSize];\n+  UInt32 alignPriceCount;\n+\n+  UInt32 distTableSize;\n+\n+  unsigned lc, lp, pb;\n+  unsigned lpMask, pbMask;\n+\n+  CLzmaProb *litProbs;\n+\n+  CLzmaProb isMatch[kNumStates][LZMA_NUM_PB_STATES_MAX];\n+  CLzmaProb isRep[kNumStates];\n+  CLzmaProb isRepG0[kNumStates];\n+  CLzmaProb isRepG1[kNumStates];\n+  CLzmaProb isRepG2[kNumStates];\n+  CLzmaProb isRep0Long[kNumStates][LZMA_NUM_PB_STATES_MAX];\n+\n+  CLzmaProb posSlotEncoder[kNumLenToPosStates][1 << kNumPosSlotBits];\n+  CLzmaProb posEncoders[kNumFullDistances - kEndPosModelIndex];\n+  CLzmaProb posAlignEncoder[1 << kNumAlignBits];\n+  \n+  CLenPriceEnc lenEnc;\n+  CLenPriceEnc repLenEnc;\n+\n+  unsigned lclp;\n+\n+  Bool fastMode;\n+  \n+  CRangeEnc rc;\n+\n+  Bool writeEndMark;\n+  UInt64 nowPos64;\n+  UInt32 matchPriceCount;\n+  Bool finished;\n+  Bool multiThread;\n+\n+  SRes result;\n+  UInt32 dictSize;\n+  UInt32 matchFinderCycles;\n+\n+  ISeqInStream *inStream;\n+  CSeqInStreamBuf seqBufInStream;\n+\n+  CSaveState saveState;\n+} CLzmaEnc;\n+\n+static void LzmaEnc_SaveState(CLzmaEncHandle pp)\n+{\n+  CLzmaEnc *p = (CLzmaEnc *)pp;\n+  CSaveState *dest = &p->saveState;\n+  int i;\n+  dest->lenEnc = p->lenEnc;\n+  dest->repLenEnc = p->repLenEnc;\n+  dest->state = p->state;\n+\n+  for (i = 0; i < kNumStates; i++)\n+  {\n+    memcpy(dest->isMatch[i], p->isMatch[i], sizeof(p->isMatch[i]));\n+    memcpy(dest->isRep0Long[i], p->isRep0Long[i], sizeof(p->isRep0Long[i]));\n+  }\n+  for (i = 0; i < kNumLenToPosStates; i++)\n+    memcpy(dest->posSlotEncoder[i], p->posSlotEncoder[i], sizeof(p->posSlotEncoder[i]));\n+  memcpy(dest->isRep, p->isRep, sizeof(p->isRep));\n+  memcpy(dest->isRepG0, p->isRepG0, sizeof(p->isRepG0));\n+  memcpy(dest->isRepG1, p->isRepG1, sizeof(p->isRepG1));\n+  memcpy(dest->isRepG2, p->isRepG2, sizeof(p->isRepG2));\n+  memcpy(dest->posEncoders, p->posEncoders, sizeof(p->posEncoders));\n+  memcpy(dest->posAlignEncoder, p->posAlignEncoder, sizeof(p->posAlignEncoder));\n+  memcpy(dest->reps, p->reps, sizeof(p->reps));\n+  memcpy(dest->litProbs, p->litProbs, (0x300 << p->lclp) * sizeof(CLzmaProb));\n+}\n+\n+static void LzmaEnc_RestoreState(CLzmaEncHandle pp)\n+{\n+  CLzmaEnc *dest = (CLzmaEnc *)pp;\n+  const CSaveState *p = &dest->saveState;\n+  int i;\n+  dest->lenEnc = p->lenEnc;\n+  dest->repLenEnc = p->repLenEnc;\n+  dest->state = p->state;\n+\n+  for (i = 0; i < kNumStates; i++)\n+  {\n+    memcpy(dest->isMatch[i], p->isMatch[i], sizeof(p->isMatch[i]));\n+    memcpy(dest->isRep0Long[i], p->isRep0Long[i], sizeof(p->isRep0Long[i]));\n+  }\n+  for (i = 0; i < kNumLenToPosStates; i++)\n+    memcpy(dest->posSlotEncoder[i], p->posSlotEncoder[i], sizeof(p->posSlotEncoder[i]));\n+  memcpy(dest->isRep, p->isRep, sizeof(p->isRep));\n+  memcpy(dest->isRepG0, p->isRepG0, sizeof(p->isRepG0));\n+  memcpy(dest->isRepG1, p->isRepG1, sizeof(p->isRepG1));\n+  memcpy(dest->isRepG2, p->isRepG2, sizeof(p->isRepG2));\n+  memcpy(dest->posEncoders, p->posEncoders, sizeof(p->posEncoders));\n+  memcpy(dest->posAlignEncoder, p->posAlignEncoder, sizeof(p->posAlignEncoder));\n+  memcpy(dest->reps, p->reps, sizeof(p->reps));\n+  memcpy(dest->litProbs, p->litProbs, (0x300 << dest->lclp) * sizeof(CLzmaProb));\n+}\n+\n+SRes LzmaEnc_SetProps(CLzmaEncHandle pp, const CLzmaEncProps *props2)\n+{\n+  CLzmaEnc *p = (CLzmaEnc *)pp;\n+  CLzmaEncProps props = *props2;\n+  LzmaEncProps_Normalize(&props);\n+\n+  if (props.lc > LZMA_LC_MAX || props.lp > LZMA_LP_MAX || props.pb > LZMA_PB_MAX ||\n+      props.dictSize > (1 << kDicLogSizeMaxCompress) || props.dictSize > (1 << 30))\n+    return SZ_ERROR_PARAM;\n+  p->dictSize = props.dictSize;\n+  p->matchFinderCycles = props.mc;\n+  {\n+    unsigned fb = props.fb;\n+    if (fb < 5)\n+      fb = 5;\n+    if (fb > LZMA_MATCH_LEN_MAX)\n+      fb = LZMA_MATCH_LEN_MAX;\n+    p->numFastBytes = fb;\n+  }\n+  p->lc = props.lc;\n+  p->lp = props.lp;\n+  p->pb = props.pb;\n+  p->fastMode = (props.algo == 0);\n+  p->matchFinderBase.btMode = props.btMode;\n+  {\n+    UInt32 numHashBytes = 4;\n+    if (props.btMode)\n+    {\n+      if (props.numHashBytes < 2)\n+        numHashBytes = 2;\n+      else if (props.numHashBytes < 4)\n+        numHashBytes = props.numHashBytes;\n+    }\n+    p->matchFinderBase.numHashBytes = numHashBytes;\n+  }\n+\n+  p->matchFinderBase.cutValue = props.mc;\n+\n+  p->writeEndMark = props.writeEndMark;\n+\n+  #ifdef COMPRESS_MF_MT\n+  /*\n+  if (newMultiThread != _multiThread)\n+  {\n+    ReleaseMatchFinder();\n+    _multiThread = newMultiThread;\n+  }\n+  */\n+  p->multiThread = (props.numThreads > 1);\n+  #endif\n+\n+  return SZ_OK;\n+}\n+\n+static const int kLiteralNextStates[kNumStates] = {0, 0, 0, 0, 1, 2, 3, 4,  5,  6,   4, 5};\n+static const int kMatchNextStates[kNumStates]   = {7, 7, 7, 7, 7, 7, 7, 10, 10, 10, 10, 10};\n+static const int kRepNextStates[kNumStates]     = {8, 8, 8, 8, 8, 8, 8, 11, 11, 11, 11, 11};\n+static const int kShortRepNextStates[kNumStates]= {9, 9, 9, 9, 9, 9, 9, 11, 11, 11, 11, 11};\n+\n+/*\n+  void UpdateChar() { Index = kLiteralNextStates[Index]; }\n+  void UpdateMatch() { Index = kMatchNextStates[Index]; }\n+  void UpdateRep() { Index = kRepNextStates[Index]; }\n+  void UpdateShortRep() { Index = kShortRepNextStates[Index]; }\n+*/\n+\n+#define IsCharState(s) ((s) < 7)\n+\n+\n+#define GetLenToPosState(len) (((len) < kNumLenToPosStates + 1) ? (len) - 2 : kNumLenToPosStates - 1)\n+\n+#define kInfinityPrice (1 << 30)\n+\n+static void RangeEnc_Construct(CRangeEnc *p)\n+{\n+  p->outStream = 0;\n+  p->bufBase = 0;\n+}\n+\n+#define RangeEnc_GetProcessed(p) ((p)->processed + ((p)->buf - (p)->bufBase) + (p)->cacheSize)\n+\n+#define RC_BUF_SIZE (1 << 16)\n+static int RangeEnc_Alloc(CRangeEnc *p, ISzAlloc *alloc)\n+{\n+  if (p->bufBase == 0)\n+  {\n+    p->bufBase = (Byte *)alloc->Alloc(alloc, RC_BUF_SIZE);\n+    if (p->bufBase == 0)\n+      return 0;\n+    p->bufLim = p->bufBase + RC_BUF_SIZE;\n+  }\n+  return 1;\n+}\n+\n+static void RangeEnc_Free(CRangeEnc *p, ISzAlloc *alloc)\n+{\n+  alloc->Free(alloc, p->bufBase);\n+  p->bufBase = 0;\n+}\n+\n+static void RangeEnc_Init(CRangeEnc *p)\n+{\n+  /* Stream.Init(); */\n+  p->low = 0;\n+  p->range = 0xFFFFFFFF;\n+  p->cacheSize = 1;\n+  p->cache = 0;\n+\n+  p->buf = p->bufBase;\n+\n+  p->processed = 0;\n+  p->res = SZ_OK;\n+}\n+\n+static void RangeEnc_FlushStream(CRangeEnc *p)\n+{\n+  size_t num;\n+  if (p->res != SZ_OK)\n+    return;\n+  num = p->buf - p->bufBase;\n+  if (num != p->outStream->Write(p->outStream, p->bufBase, num))\n+    p->res = SZ_ERROR_WRITE;\n+  p->processed += num;\n+  p->buf = p->bufBase;\n+}\n+\n+static void MY_FAST_CALL RangeEnc_ShiftLow(CRangeEnc *p)\n+{\n+  if ((UInt32)p->low < (UInt32)0xFF000000 || (int)(p->low >> 32) != 0) \n+  {\n+    Byte temp = p->cache;\n+    do\n+    {\n+      Byte *buf = p->buf;\n+      *buf++ = (Byte)(temp + (Byte)(p->low >> 32));\n+      p->buf = buf;\n+      if (buf == p->bufLim)\n+        RangeEnc_FlushStream(p);\n+      temp = 0xFF;\n+    }\n+    while (--p->cacheSize != 0);\n+    p->cache = (Byte)((UInt32)p->low >> 24);                      \n+  } \n+  p->cacheSize++;                               \n+  p->low = (UInt32)p->low << 8;                           \n+}\n+\n+static void RangeEnc_FlushData(CRangeEnc *p)\n+{\n+  int i;\n+  for (i = 0; i < 5; i++)\n+    RangeEnc_ShiftLow(p);\n+}\n+\n+static void RangeEnc_EncodeDirectBits(CRangeEnc *p, UInt32 value, int numBits)\n+{\n+  do\n+  {\n+    p->range >>= 1;\n+    p->low += p->range & (0 - ((value >> --numBits) & 1));\n+    if (p->range < kTopValue)\n+    {\n+      p->range <<= 8;\n+      RangeEnc_ShiftLow(p);\n+    }\n+  }\n+  while (numBits != 0);\n+}\n+\n+static void RangeEnc_EncodeBit(CRangeEnc *p, CLzmaProb *prob, UInt32 symbol)\n+{\n+  UInt32 ttt = *prob;\n+  UInt32 newBound = (p->range >> kNumBitModelTotalBits) * ttt;\n+  if (symbol == 0)\n+  {\n+    p->range = newBound;\n+    ttt += (kBitModelTotal - ttt) >> kNumMoveBits;\n+  }\n+  else\n+  {\n+    p->low += newBound;\n+    p->range -= newBound;\n+    ttt -= ttt >> kNumMoveBits;\n+  }\n+  *prob = (CLzmaProb)ttt;\n+  if (p->range < kTopValue)\n+  {\n+    p->range <<= 8;\n+    RangeEnc_ShiftLow(p);\n+  }\n+}\n+\n+static void LitEnc_Encode(CRangeEnc *p, CLzmaProb *probs, UInt32 symbol)\n+{\n+  symbol |= 0x100;\n+  do \n+  {\n+    RangeEnc_EncodeBit(p, probs + (symbol >> 8), (symbol >> 7) & 1);\n+    symbol <<= 1;\n+  }\n+  while (symbol < 0x10000);\n+}\n+\n+static void LitEnc_EncodeMatched(CRangeEnc *p, CLzmaProb *probs, UInt32 symbol, UInt32 matchByte)\n+{\n+  UInt32 offs = 0x100;\n+  symbol |= 0x100;\n+  do \n+  {\n+    matchByte <<= 1;\n+    RangeEnc_EncodeBit(p, probs + (offs + (matchByte & offs) + (symbol >> 8)), (symbol >> 7) & 1);\n+    symbol <<= 1;\n+    offs &= ~(matchByte ^ symbol);\n+  }\n+  while (symbol < 0x10000);\n+}\n+\n+static void LzmaEnc_InitPriceTables(UInt32 *ProbPrices)\n+{\n+  UInt32 i;\n+  for (i = (1 << kNumMoveReducingBits) / 2; i < kBitModelTotal; i += (1 << kNumMoveReducingBits))\n+  {\n+    const int kCyclesBits = kNumBitPriceShiftBits;\n+    UInt32 w = i;\n+    UInt32 bitCount = 0;\n+    int j;\n+    for (j = 0; j < kCyclesBits; j++)\n+    {\n+      w = w * w;\n+      bitCount <<= 1;\n+      while (w >= ((UInt32)1 << 16))\n+      {\n+        w >>= 1;\n+        bitCount++;\n+      }\n+    }\n+    ProbPrices[i >> kNumMoveReducingBits] = ((kNumBitModelTotalBits << kCyclesBits) - 15 - bitCount);\n+  }\n+}\n+\n+\n+#define GET_PRICE(prob, symbol) \\\n+  p->ProbPrices[((prob) ^ (((-(int)(symbol))) & (kBitModelTotal - 1))) >> kNumMoveReducingBits];\n+\n+#define GET_PRICEa(prob, symbol) \\\n+  ProbPrices[((prob) ^ ((-((int)(symbol))) & (kBitModelTotal - 1))) >> kNumMoveReducingBits];\n+\n+#define GET_PRICE_0(prob) p->ProbPrices[(prob) >> kNumMoveReducingBits]\n+#define GET_PRICE_1(prob) p->ProbPrices[((prob) ^ (kBitModelTotal - 1)) >> kNumMoveReducingBits]\n+\n+#define GET_PRICE_0a(prob) ProbPrices[(prob) >> kNumMoveReducingBits]\n+#define GET_PRICE_1a(prob) ProbPrices[((prob) ^ (kBitModelTotal - 1)) >> kNumMoveReducingBits]\n+\n+static UInt32 LitEnc_GetPrice(const CLzmaProb *probs, UInt32 symbol, UInt32 *ProbPrices)\n+{\n+  UInt32 price = 0;\n+  symbol |= 0x100;\n+  do\n+  {\n+    price += GET_PRICEa(probs[symbol >> 8], (symbol >> 7) & 1);\n+    symbol <<= 1;\n+  }\n+  while (symbol < 0x10000);\n+  return price;\n+};\n+\n+static UInt32 LitEnc_GetPriceMatched(const CLzmaProb *probs, UInt32 symbol, UInt32 matchByte, UInt32 *ProbPrices)\n+{\n+  UInt32 price = 0;\n+  UInt32 offs = 0x100;\n+  symbol |= 0x100;\n+  do \n+  {\n+    matchByte <<= 1;\n+    price += GET_PRICEa(probs[offs + (matchByte & offs) + (symbol >> 8)], (symbol >> 7) & 1);\n+    symbol <<= 1;\n+    offs &= ~(matchByte ^ symbol);\n+  }\n+  while (symbol < 0x10000);\n+  return price;\n+};\n+\n+\n+static void RcTree_Encode(CRangeEnc *rc, CLzmaProb *probs, int numBitLevels, UInt32 symbol)\n+{\n+  UInt32 m = 1;\n+  int i;\n+  for (i = numBitLevels; i != 0 ;)\n+  {\n+    UInt32 bit;\n+    i--;\n+    bit = (symbol >> i) & 1;\n+    RangeEnc_EncodeBit(rc, probs + m, bit);\n+    m = (m << 1) | bit;\n+  }\n+};\n+\n+static void RcTree_ReverseEncode(CRangeEnc *rc, CLzmaProb *probs, int numBitLevels, UInt32 symbol)\n+{\n+  UInt32 m = 1;\n+  int i;\n+  for (i = 0; i < numBitLevels; i++)\n+  {\n+    UInt32 bit = symbol & 1;\n+    RangeEnc_EncodeBit(rc, probs + m, bit);\n+    m = (m << 1) | bit;\n+    symbol >>= 1;\n+  }\n+}\n+\n+static UInt32 RcTree_GetPrice(const CLzmaProb *probs, int numBitLevels, UInt32 symbol, UInt32 *ProbPrices)\n+{\n+  UInt32 price = 0;\n+  symbol |= (1 << numBitLevels);\n+  while (symbol != 1)\n+  {\n+    price += GET_PRICEa(probs[symbol >> 1], symbol & 1);\n+    symbol >>= 1;\n+  }\n+  return price;\n+}\n+\n+static UInt32 RcTree_ReverseGetPrice(const CLzmaProb *probs, int numBitLevels, UInt32 symbol, UInt32 *ProbPrices)\n+{\n+  UInt32 price = 0;\n+  UInt32 m = 1;\n+  int i;\n+  for (i = numBitLevels; i != 0; i--)\n+  {\n+    UInt32 bit = symbol & 1;\n+    symbol >>= 1;\n+    price += GET_PRICEa(probs[m], bit);\n+    m = (m << 1) | bit;\n+  }\n+  return price;\n+}\n+\n+\n+static void LenEnc_Init(CLenEnc *p)\n+{\n+  unsigned i;\n+  p->choice = p->choice2 = kProbInitValue;\n+  for (i = 0; i < (LZMA_NUM_PB_STATES_MAX << kLenNumLowBits); i++)\n+    p->low[i] = kProbInitValue;\n+  for (i = 0; i < (LZMA_NUM_PB_STATES_MAX << kLenNumMidBits); i++)\n+    p->mid[i] = kProbInitValue;\n+  for (i = 0; i < kLenNumHighSymbols; i++)\n+    p->high[i] = kProbInitValue;\n+}\n+\n+static void LenEnc_Encode(CLenEnc *p, CRangeEnc *rc, UInt32 symbol, UInt32 posState)\n+{\n+  if (symbol < kLenNumLowSymbols)\n+  {\n+    RangeEnc_EncodeBit(rc, &p->choice, 0);\n+    RcTree_Encode(rc, p->low + (posState << kLenNumLowBits), kLenNumLowBits, symbol);\n+  }\n+  else\n+  {\n+    RangeEnc_EncodeBit(rc, &p->choice, 1);\n+    if (symbol < kLenNumLowSymbols + kLenNumMidSymbols)\n+    {\n+      RangeEnc_EncodeBit(rc, &p->choice2, 0);\n+      RcTree_Encode(rc, p->mid + (posState << kLenNumMidBits), kLenNumMidBits, symbol - kLenNumLowSymbols);\n+    }\n+    else\n+    {\n+      RangeEnc_EncodeBit(rc, &p->choice2, 1);\n+      RcTree_Encode(rc, p->high, kLenNumHighBits, symbol - kLenNumLowSymbols - kLenNumMidSymbols);\n+    }\n+  }\n+}\n+\n+static void LenEnc_SetPrices(CLenEnc *p, UInt32 posState, UInt32 numSymbols, UInt32 *prices, UInt32 *ProbPrices)\n+{\n+  UInt32 a0 = GET_PRICE_0a(p->choice);\n+  UInt32 a1 = GET_PRICE_1a(p->choice);\n+  UInt32 b0 = a1 + GET_PRICE_0a(p->choice2);\n+  UInt32 b1 = a1 + GET_PRICE_1a(p->choice2);\n+  UInt32 i = 0;\n+  for (i = 0; i < kLenNumLowSymbols; i++)\n+  {\n+    if (i >= numSymbols)\n+      return;\n+    prices[i] = a0 + RcTree_GetPrice(p->low + (posState << kLenNumLowBits), kLenNumLowBits, i, ProbPrices);\n+  }\n+  for (; i < kLenNumLowSymbols + kLenNumMidSymbols; i++)\n+  {\n+    if (i >= numSymbols)\n+      return;\n+    prices[i] = b0 + RcTree_GetPrice(p->mid + (posState << kLenNumMidBits), kLenNumMidBits, i - kLenNumLowSymbols, ProbPrices);\n+  }\n+  for (; i < numSymbols; i++)\n+    prices[i] = b1 + RcTree_GetPrice(p->high, kLenNumHighBits, i - kLenNumLowSymbols - kLenNumMidSymbols, ProbPrices);\n+}\n+\n+static void MY_FAST_CALL LenPriceEnc_UpdateTable(CLenPriceEnc *p, UInt32 posState, UInt32 *ProbPrices)\n+{\n+  LenEnc_SetPrices(&p->p, posState, p->tableSize, p->prices[posState], ProbPrices);\n+  p->counters[posState] = p->tableSize;\n+}\n+\n+static void LenPriceEnc_UpdateTables(CLenPriceEnc *p, UInt32 numPosStates, UInt32 *ProbPrices)\n+{\n+  UInt32 posState;\n+  for (posState = 0; posState < numPosStates; posState++)\n+    LenPriceEnc_UpdateTable(p, posState, ProbPrices);\n+}\n+\n+static void LenEnc_Encode2(CLenPriceEnc *p, CRangeEnc *rc, UInt32 symbol, UInt32 posState, Bool updatePrice, UInt32 *ProbPrices)\n+{\n+  LenEnc_Encode(&p->p, rc, symbol, posState);\n+  if (updatePrice)\n+    if (--p->counters[posState] == 0)\n+      LenPriceEnc_UpdateTable(p, posState, ProbPrices);\n+}\n+\n+\n+\n+\n+static void MovePos(CLzmaEnc *p, UInt32 num)\n+{\n+  #ifdef SHOW_STAT\n+  ttt += num;\n+  printf(\"\\n MovePos %d\", num);\n+  #endif\n+  if (num != 0)\n+  {\n+    p->additionalOffset += num;\n+    p->matchFinder.Skip(p->matchFinderObj, num);\n+  }\n+}\n+\n+static UInt32 ReadMatchDistances(CLzmaEnc *p, UInt32 *numDistancePairsRes)\n+{\n+  UInt32 lenRes = 0, numDistancePairs;\n+  numDistancePairs = p->matchFinder.GetMatches(p->matchFinderObj, p->matchDistances);\n+  #ifdef SHOW_STAT\n+  printf(\"\\n i = %d numPairs = %d    \", ttt, numDistancePairs / 2);\n+  if (ttt >= 61994)\n+    ttt = ttt;\n+\n+  ttt++;\n+  {\n+    UInt32 i;\n+  for (i = 0; i < numDistancePairs; i += 2)\n+    printf(\"%2d %6d   | \", p->matchDistances[i], p->matchDistances[i + 1]);\n+  }\n+  #endif\n+  if (numDistancePairs > 0)\n+  {\n+    lenRes = p->matchDistances[numDistancePairs - 2];\n+    if (lenRes == p->numFastBytes)\n+    {\n+      UInt32 numAvail = p->matchFinder.GetNumAvailableBytes(p->matchFinderObj) + 1;\n+      const Byte *pby = p->matchFinder.GetPointerToCurrentPos(p->matchFinderObj) - 1;\n+      UInt32 distance = p->matchDistances[numDistancePairs - 1] + 1;\n+      if (numAvail > LZMA_MATCH_LEN_MAX)\n+        numAvail = LZMA_MATCH_LEN_MAX;\n+\n+      {\n+        const Byte *pby2 = pby - distance;\n+        for (; lenRes < numAvail && pby[lenRes] == pby2[lenRes]; lenRes++);\n+      }\n+    }\n+  }\n+  p->additionalOffset++;\n+  *numDistancePairsRes = numDistancePairs;\n+  return lenRes;\n+}\n+\n+\n+#define MakeAsChar(p) (p)->backPrev = (UInt32)(-1); (p)->prev1IsChar = False;\n+#define MakeAsShortRep(p) (p)->backPrev = 0; (p)->prev1IsChar = False;\n+#define IsShortRep(p) ((p)->backPrev == 0)\n+\n+static UInt32 GetRepLen1Price(CLzmaEnc *p, UInt32 state, UInt32 posState)\n+{\n+  return \n+    GET_PRICE_0(p->isRepG0[state]) +\n+    GET_PRICE_0(p->isRep0Long[state][posState]);\n+}\n+\n+static UInt32 GetPureRepPrice(CLzmaEnc *p, UInt32 repIndex, UInt32 state, UInt32 posState)\n+{\n+  UInt32 price;\n+  if (repIndex == 0)\n+  {\n+    price = GET_PRICE_0(p->isRepG0[state]);\n+    price += GET_PRICE_1(p->isRep0Long[state][posState]);\n+  }\n+  else\n+  {\n+    price = GET_PRICE_1(p->isRepG0[state]);\n+    if (repIndex == 1)\n+      price += GET_PRICE_0(p->isRepG1[state]);\n+    else\n+    {\n+      price += GET_PRICE_1(p->isRepG1[state]);\n+      price += GET_PRICE(p->isRepG2[state], repIndex - 2);\n+    }\n+  }\n+  return price;\n+}\n+\n+static UInt32 GetRepPrice(CLzmaEnc *p, UInt32 repIndex, UInt32 len, UInt32 state, UInt32 posState)\n+{\n+  return p->repLenEnc.prices[posState][len - LZMA_MATCH_LEN_MIN] +\n+    GetPureRepPrice(p, repIndex, state, posState);\n+}\n+\n+static UInt32 Backward(CLzmaEnc *p, UInt32 *backRes, UInt32 cur)\n+{\n+  UInt32 posMem = p->opt[cur].posPrev;\n+  UInt32 backMem = p->opt[cur].backPrev;\n+  p->optimumEndIndex = cur;\n+  do\n+  {\n+    if (p->opt[cur].prev1IsChar)\n+    {\n+      MakeAsChar(&p->opt[posMem])\n+      p->opt[posMem].posPrev = posMem - 1;\n+      if (p->opt[cur].prev2)\n+      {\n+        p->opt[posMem - 1].prev1IsChar = False;\n+        p->opt[posMem - 1].posPrev = p->opt[cur].posPrev2;\n+        p->opt[posMem - 1].backPrev = p->opt[cur].backPrev2;\n+      }\n+    }\n+    {\n+      UInt32 posPrev = posMem;\n+      UInt32 backCur = backMem;\n+      \n+      backMem = p->opt[posPrev].backPrev;\n+      posMem = p->opt[posPrev].posPrev;\n+      \n+      p->opt[posPrev].backPrev = backCur;\n+      p->opt[posPrev].posPrev = cur;\n+      cur = posPrev;\n+    }\n+  }\n+  while (cur != 0);\n+  *backRes = p->opt[0].backPrev;\n+  p->optimumCurrentIndex  = p->opt[0].posPrev;\n+  return p->optimumCurrentIndex; \n+}\n+\n+#define LIT_PROBS(pos, prevByte) (p->litProbs + ((((pos) & p->lpMask) << p->lc) + ((prevByte) >> (8 - p->lc))) * 0x300)\n+\n+static UInt32 GetOptimum(CLzmaEnc *p, UInt32 position, UInt32 *backRes)\n+{\n+  UInt32 numAvailableBytes, lenMain, numDistancePairs;\n+  const Byte *data;\n+  UInt32 reps[LZMA_NUM_REPS];\n+  UInt32 repLens[LZMA_NUM_REPS];\n+  UInt32 repMaxIndex, i;\n+  UInt32 *matchDistances;\n+  Byte currentByte, matchByte; \n+  UInt32 posState;\n+  UInt32 matchPrice, repMatchPrice;\n+  UInt32 lenEnd;\n+  UInt32 len;\n+  UInt32 normalMatchPrice;\n+  UInt32 cur;\n+  if (p->optimumEndIndex != p->optimumCurrentIndex)\n+  {\n+    const COptimal *opt = &p->opt[p->optimumCurrentIndex];\n+    UInt32 lenRes = opt->posPrev - p->optimumCurrentIndex;\n+    *backRes = opt->backPrev;\n+    p->optimumCurrentIndex = opt->posPrev;\n+    return lenRes;\n+  }\n+  p->optimumCurrentIndex = p->optimumEndIndex = 0;\n+  \n+  numAvailableBytes = p->matchFinder.GetNumAvailableBytes(p->matchFinderObj);\n+\n+  if (!p->longestMatchWasFound)\n+  {\n+    lenMain = ReadMatchDistances(p, &numDistancePairs);\n+  }\n+  else\n+  {\n+    lenMain = p->longestMatchLength;\n+    numDistancePairs = p->numDistancePairs;\n+    p->longestMatchWasFound = False;\n+  }\n+\n+  data = p->matchFinder.GetPointerToCurrentPos(p->matchFinderObj) - 1;\n+  if (numAvailableBytes < 2)\n+  {\n+    *backRes = (UInt32)(-1);\n+    return 1;\n+  }\n+  if (numAvailableBytes > LZMA_MATCH_LEN_MAX)\n+    numAvailableBytes = LZMA_MATCH_LEN_MAX;\n+\n+  repMaxIndex = 0;\n+  for (i = 0; i < LZMA_NUM_REPS; i++)\n+  {\n+    UInt32 lenTest;\n+    const Byte *data2;\n+    reps[i] = p->reps[i];\n+    data2 = data - (reps[i] + 1);\n+    if (data[0] != data2[0] || data[1] != data2[1])\n+    {\n+      repLens[i] = 0;\n+      continue;\n+    }\n+    for (lenTest = 2; lenTest < numAvailableBytes && data[lenTest] == data2[lenTest]; lenTest++);\n+    repLens[i] = lenTest;\n+    if (lenTest > repLens[repMaxIndex])\n+      repMaxIndex = i;\n+  }\n+  if (repLens[repMaxIndex] >= p->numFastBytes)\n+  {\n+    UInt32 lenRes;\n+    *backRes = repMaxIndex;\n+    lenRes = repLens[repMaxIndex];\n+    MovePos(p, lenRes - 1);\n+    return lenRes;\n+  }\n+\n+  matchDistances = p->matchDistances;\n+  if (lenMain >= p->numFastBytes)\n+  {\n+    *backRes = matchDistances[numDistancePairs - 1] + LZMA_NUM_REPS; \n+    MovePos(p, lenMain - 1);\n+    return lenMain;\n+  }\n+  currentByte = *data;\n+  matchByte = *(data - (reps[0] + 1));\n+\n+  if (lenMain < 2 && currentByte != matchByte && repLens[repMaxIndex] < 2)\n+  {\n+    *backRes = (UInt32)-1;\n+    return 1;\n+  }\n+\n+  p->opt[0].state = (CState)p->state;\n+\n+  posState = (position & p->pbMask);\n+\n+  {\n+    const CLzmaProb *probs = LIT_PROBS(position, *(data - 1));\n+    p->opt[1].price = GET_PRICE_0(p->isMatch[p->state][posState]) + \n+        (!IsCharState(p->state) ? \n+          LitEnc_GetPriceMatched(probs, currentByte, matchByte, p->ProbPrices) :\n+          LitEnc_GetPrice(probs, currentByte, p->ProbPrices));\n+  }\n+\n+  MakeAsChar(&p->opt[1]);\n+\n+  matchPrice = GET_PRICE_1(p->isMatch[p->state][posState]);\n+  repMatchPrice = matchPrice + GET_PRICE_1(p->isRep[p->state]);\n+\n+  if (matchByte == currentByte)\n+  {\n+    UInt32 shortRepPrice = repMatchPrice + GetRepLen1Price(p, p->state, posState);\n+    if (shortRepPrice < p->opt[1].price)\n+    {\n+      p->opt[1].price = shortRepPrice;\n+      MakeAsShortRep(&p->opt[1]);\n+    }\n+  }\n+  lenEnd = ((lenMain >= repLens[repMaxIndex]) ? lenMain : repLens[repMaxIndex]);\n+\n+  if (lenEnd < 2)\n+  {\n+    *backRes = p->opt[1].backPrev;\n+    return 1;\n+  }\n+\n+  p->opt[1].posPrev = 0;\n+  for (i = 0; i < LZMA_NUM_REPS; i++)\n+    p->opt[0].backs[i] = reps[i];\n+\n+  len = lenEnd;\n+  do\n+    p->opt[len--].price = kInfinityPrice;\n+  while (len >= 2);\n+\n+  for (i = 0; i < LZMA_NUM_REPS; i++)\n+  {\n+    UInt32 repLen = repLens[i];\n+    UInt32 price;\n+    if (repLen < 2)\n+      continue;\n+    price = repMatchPrice + GetPureRepPrice(p, i, p->state, posState);\n+    do\n+    {\n+      UInt32 curAndLenPrice = price + p->repLenEnc.prices[posState][repLen - 2];\n+      COptimal *opt = &p->opt[repLen];\n+      if (curAndLenPrice < opt->price) \n+      {\n+        opt->price = curAndLenPrice;\n+        opt->posPrev = 0;\n+        opt->backPrev = i;\n+        opt->prev1IsChar = False;\n+      }\n+    }\n+    while (--repLen >= 2);\n+  }\n+\n+  normalMatchPrice = matchPrice + GET_PRICE_0(p->isRep[p->state]);\n+\n+  len = ((repLens[0] >= 2) ? repLens[0] + 1 : 2);\n+  if (len <= lenMain)\n+  {\n+    UInt32 offs = 0;\n+    while (len > matchDistances[offs])\n+      offs += 2;\n+    for (; ; len++)\n+    {\n+      COptimal *opt;\n+      UInt32 distance = matchDistances[offs + 1];\n+\n+      UInt32 curAndLenPrice = normalMatchPrice + p->lenEnc.prices[posState][len - LZMA_MATCH_LEN_MIN];\n+      UInt32 lenToPosState = GetLenToPosState(len);\n+      if (distance < kNumFullDistances)\n+        curAndLenPrice += p->distancesPrices[lenToPosState][distance];\n+      else\n+      {\n+        UInt32 slot;\n+        GetPosSlot2(distance, slot);\n+        curAndLenPrice += p->alignPrices[distance & kAlignMask] + p->posSlotPrices[lenToPosState][slot];\n+      }\n+      opt = &p->opt[len];\n+      if (curAndLenPrice < opt->price) \n+      {\n+        opt->price = curAndLenPrice;\n+        opt->posPrev = 0;\n+        opt->backPrev = distance + LZMA_NUM_REPS;\n+        opt->prev1IsChar = False;\n+      }\n+      if (len == matchDistances[offs])\n+      {\n+        offs += 2;\n+        if (offs == numDistancePairs)\n+          break;\n+      }\n+    }\n+  }\n+\n+  cur = 0;\n+\n+    #ifdef SHOW_STAT2\n+    if (position >= 0)\n+    {\n+      unsigned i;\n+      printf(\"\\n pos = %4X\", position);\n+      for (i = cur; i <= lenEnd; i++)\n+      printf(\"\\nprice[%4X] = %d\", position - cur + i, p->opt[i].price);\n+    }\n+    #endif\n+\n+  for (;;)\n+  {\n+    UInt32 numAvailableBytesFull, newLen, numDistancePairs;\n+    COptimal *curOpt;\n+    UInt32 posPrev;\n+    UInt32 state;\n+    UInt32 curPrice;\n+    Bool nextIsChar;\n+    const Byte *data;\n+    Byte currentByte, matchByte;\n+    UInt32 posState;\n+    UInt32 curAnd1Price;\n+    COptimal *nextOpt;\n+    UInt32 matchPrice, repMatchPrice;  \n+    UInt32 numAvailableBytes;\n+    UInt32 startLen;\n+\n+    cur++;\n+    if (cur == lenEnd)\n+      return Backward(p, backRes, cur);\n+\n+    numAvailableBytesFull = p->matchFinder.GetNumAvailableBytes(p->matchFinderObj);\n+    newLen = ReadMatchDistances(p, &numDistancePairs);\n+    if (newLen >= p->numFastBytes)\n+    {\n+      p->numDistancePairs = numDistancePairs;\n+      p->longestMatchLength = newLen;\n+      p->longestMatchWasFound = True;\n+      return Backward(p, backRes, cur);\n+    }\n+    position++;\n+    curOpt = &p->opt[cur];\n+    posPrev = curOpt->posPrev;\n+    if (curOpt->prev1IsChar)\n+    {\n+      posPrev--;\n+      if (curOpt->prev2)\n+      {\n+        state = p->opt[curOpt->posPrev2].state;\n+        if (curOpt->backPrev2 < LZMA_NUM_REPS)\n+          state = kRepNextStates[state];\n+        else\n+          state = kMatchNextStates[state];\n+      }\n+      else\n+        state = p->opt[posPrev].state;\n+      state = kLiteralNextStates[state];\n+    }\n+    else\n+      state = p->opt[posPrev].state;\n+    if (posPrev == cur - 1)\n+    {\n+      if (IsShortRep(curOpt))\n+        state = kShortRepNextStates[state];\n+      else\n+        state = kLiteralNextStates[state];\n+    }\n+    else\n+    {\n+      UInt32 pos;\n+      const COptimal *prevOpt;\n+      if (curOpt->prev1IsChar && curOpt->prev2)\n+      {\n+        posPrev = curOpt->posPrev2;\n+        pos = curOpt->backPrev2;\n+        state = kRepNextStates[state];\n+      }\n+      else\n+      {\n+        pos = curOpt->backPrev;\n+        if (pos < LZMA_NUM_REPS)\n+          state = kRepNextStates[state];\n+        else\n+          state = kMatchNextStates[state];\n+      }\n+      prevOpt = &p->opt[posPrev];\n+      if (pos < LZMA_NUM_REPS)\n+      {\n+        UInt32 i;\n+        reps[0] = prevOpt->backs[pos];\n+        for (i = 1; i <= pos; i++)\n+          reps[i] = prevOpt->backs[i - 1];\n+        for (; i < LZMA_NUM_REPS; i++)\n+          reps[i] = prevOpt->backs[i];\n+      }\n+      else\n+      {\n+        UInt32 i;\n+        reps[0] = (pos - LZMA_NUM_REPS);\n+        for (i = 1; i < LZMA_NUM_REPS; i++)\n+          reps[i] = prevOpt->backs[i - 1];\n+      }\n+    }\n+    curOpt->state = (CState)state;\n+\n+    curOpt->backs[0] = reps[0];\n+    curOpt->backs[1] = reps[1];\n+    curOpt->backs[2] = reps[2];\n+    curOpt->backs[3] = reps[3];\n+\n+    curPrice = curOpt->price; \n+    nextIsChar = False;\n+    data = p->matchFinder.GetPointerToCurrentPos(p->matchFinderObj) - 1;\n+    currentByte = *data;\n+    matchByte = *(data - (reps[0] + 1));\n+\n+    posState = (position & p->pbMask);\n+\n+    curAnd1Price = curPrice + GET_PRICE_0(p->isMatch[state][posState]);\n+    {\n+      const CLzmaProb *probs = LIT_PROBS(position, *(data - 1));\n+      curAnd1Price += \n+        (!IsCharState(state) ? \n+          LitEnc_GetPriceMatched(probs, currentByte, matchByte, p->ProbPrices) :\n+          LitEnc_GetPrice(probs, currentByte, p->ProbPrices));\n+    }   \n+\n+    nextOpt = &p->opt[cur + 1];\n+\n+    if (curAnd1Price < nextOpt->price) \n+    {\n+      nextOpt->price = curAnd1Price;\n+      nextOpt->posPrev = cur;\n+      MakeAsChar(nextOpt);\n+      nextIsChar = True;\n+    }\n+\n+    matchPrice = curPrice + GET_PRICE_1(p->isMatch[state][posState]);\n+    repMatchPrice = matchPrice + GET_PRICE_1(p->isRep[state]);\n+    \n+    if (matchByte == currentByte && !(nextOpt->posPrev < cur && nextOpt->backPrev == 0))\n+    {\n+      UInt32 shortRepPrice = repMatchPrice + GetRepLen1Price(p, state, posState);\n+      if (shortRepPrice <= nextOpt->price)\n+      {\n+        nextOpt->price = shortRepPrice;\n+        nextOpt->posPrev = cur;\n+        MakeAsShortRep(nextOpt);\n+        nextIsChar = True;\n+      }\n+    }\n+\n+    {\n+      UInt32 temp = kNumOpts - 1 - cur;\n+      if (temp <  numAvailableBytesFull)\n+        numAvailableBytesFull = temp;\n+    }\n+    numAvailableBytes = numAvailableBytesFull;\n+\n+    if (numAvailableBytes < 2)\n+      continue;\n+    if (numAvailableBytes > p->numFastBytes)\n+      numAvailableBytes = p->numFastBytes;\n+    if (!nextIsChar && matchByte != currentByte) /* speed optimization */\n+    {\n+      /* try Literal + rep0 */\n+      UInt32 temp;\n+      UInt32 lenTest2;\n+      const Byte *data2 = data - (reps[0] + 1);\n+      UInt32 limit = p->numFastBytes + 1;\n+      if (limit > numAvailableBytesFull)\n+        limit = numAvailableBytesFull;\n+\n+      for (temp = 1; temp < limit && data[temp] == data2[temp]; temp++);\n+      lenTest2 = temp - 1;\n+      if (lenTest2 >= 2)\n+      {\n+        UInt32 state2 = kLiteralNextStates[state];\n+        UInt32 posStateNext = (position + 1) & p->pbMask;\n+        UInt32 nextRepMatchPrice = curAnd1Price + \n+            GET_PRICE_1(p->isMatch[state2][posStateNext]) +\n+            GET_PRICE_1(p->isRep[state2]);\n+        /* for (; lenTest2 >= 2; lenTest2--) */\n+        {\n+          UInt32 curAndLenPrice;\n+          COptimal *opt;\n+          UInt32 offset = cur + 1 + lenTest2;\n+          while (lenEnd < offset)\n+            p->opt[++lenEnd].price = kInfinityPrice;\n+          curAndLenPrice = nextRepMatchPrice + GetRepPrice(p, 0, lenTest2, state2, posStateNext);\n+          opt = &p->opt[offset];\n+          if (curAndLenPrice < opt->price) \n+          {\n+            opt->price = curAndLenPrice;\n+            opt->posPrev = cur + 1;\n+            opt->backPrev = 0;\n+            opt->prev1IsChar = True;\n+            opt->prev2 = False;\n+          }\n+        }\n+      }\n+    }\n+    \n+    startLen = 2; /* speed optimization */\n+    {\n+    UInt32 repIndex;\n+    for (repIndex = 0; repIndex < LZMA_NUM_REPS; repIndex++)\n+    {\n+      UInt32 lenTest;\n+      UInt32 lenTestTemp;\n+      UInt32 price;\n+      const Byte *data2 = data - (reps[repIndex] + 1);\n+      if (data[0] != data2[0] || data[1] != data2[1])\n+        continue;\n+      for (lenTest = 2; lenTest < numAvailableBytes && data[lenTest] == data2[lenTest]; lenTest++);\n+      while (lenEnd < cur + lenTest)\n+        p->opt[++lenEnd].price = kInfinityPrice;\n+      lenTestTemp = lenTest;\n+      price = repMatchPrice + GetPureRepPrice(p, repIndex, state, posState);\n+      do\n+      {\n+        UInt32 curAndLenPrice = price + p->repLenEnc.prices[posState][lenTest - 2];\n+        COptimal *opt = &p->opt[cur + lenTest];\n+        if (curAndLenPrice < opt->price) \n+        {\n+          opt->price = curAndLenPrice;\n+          opt->posPrev = cur;\n+          opt->backPrev = repIndex;\n+          opt->prev1IsChar = False;\n+        }\n+      }\n+      while (--lenTest >= 2);\n+      lenTest = lenTestTemp;\n+      \n+      if (repIndex == 0)\n+        startLen = lenTest + 1;\n+        \n+      /* if (_maxMode) */\n+        {\n+          UInt32 lenTest2 = lenTest + 1;\n+          UInt32 limit = lenTest2 + p->numFastBytes;\n+          UInt32 nextRepMatchPrice;\n+          if (limit > numAvailableBytesFull)\n+            limit = numAvailableBytesFull;\n+          for (; lenTest2 < limit && data[lenTest2] == data2[lenTest2]; lenTest2++);\n+          lenTest2 -= lenTest + 1;\n+          if (lenTest2 >= 2)\n+          {\n+            UInt32 state2 = kRepNextStates[state];\n+            UInt32 posStateNext = (position + lenTest) & p->pbMask;\n+            UInt32 curAndLenCharPrice = \n+                price + p->repLenEnc.prices[posState][lenTest - 2] + \n+                GET_PRICE_0(p->isMatch[state2][posStateNext]) +\n+                LitEnc_GetPriceMatched(LIT_PROBS(position + lenTest, data[lenTest - 1]),\n+                    data[lenTest], data2[lenTest], p->ProbPrices);\n+            state2 = kLiteralNextStates[state2];\n+            posStateNext = (position + lenTest + 1) & p->pbMask;\n+            nextRepMatchPrice = curAndLenCharPrice + \n+                GET_PRICE_1(p->isMatch[state2][posStateNext]) +\n+                GET_PRICE_1(p->isRep[state2]);\n+            \n+            /* for (; lenTest2 >= 2; lenTest2--) */\n+            {\n+              UInt32 curAndLenPrice;\n+              COptimal *opt;\n+              UInt32 offset = cur + lenTest + 1 + lenTest2;\n+              while (lenEnd < offset)\n+                p->opt[++lenEnd].price = kInfinityPrice;\n+              curAndLenPrice = nextRepMatchPrice + GetRepPrice(p, 0, lenTest2, state2, posStateNext);\n+              opt = &p->opt[offset];\n+              if (curAndLenPrice < opt->price) \n+              {\n+                opt->price = curAndLenPrice;\n+                opt->posPrev = cur + lenTest + 1;\n+                opt->backPrev = 0;\n+                opt->prev1IsChar = True;\n+                opt->prev2 = True;\n+                opt->posPrev2 = cur;\n+                opt->backPrev2 = repIndex;\n+              }\n+            }\n+          }\n+        }\n+    }\n+    }\n+    /* for (UInt32 lenTest = 2; lenTest <= newLen; lenTest++) */\n+    if (newLen > numAvailableBytes)\n+    {\n+      newLen = numAvailableBytes;\n+      for (numDistancePairs = 0; newLen > matchDistances[numDistancePairs]; numDistancePairs += 2);\n+      matchDistances[numDistancePairs] = newLen;\n+      numDistancePairs += 2;\n+    }\n+    if (newLen >= startLen)\n+    {\n+      UInt32 normalMatchPrice = matchPrice + GET_PRICE_0(p->isRep[state]);\n+      UInt32 offs, curBack, posSlot;\n+      UInt32 lenTest;\n+      while (lenEnd < cur + newLen)\n+        p->opt[++lenEnd].price = kInfinityPrice;\n+\n+      offs = 0;\n+      while (startLen > matchDistances[offs])\n+        offs += 2;\n+      curBack = matchDistances[offs + 1];\n+      GetPosSlot2(curBack, posSlot);\n+      for (lenTest = /*2*/ startLen; ; lenTest++)\n+      {\n+        UInt32 curAndLenPrice = normalMatchPrice + p->lenEnc.prices[posState][lenTest - LZMA_MATCH_LEN_MIN];\n+        UInt32 lenToPosState = GetLenToPosState(lenTest);\n+        COptimal *opt;\n+        if (curBack < kNumFullDistances)\n+          curAndLenPrice += p->distancesPrices[lenToPosState][curBack];\n+        else\n+          curAndLenPrice += p->posSlotPrices[lenToPosState][posSlot] + p->alignPrices[curBack & kAlignMask];\n+        \n+        opt = &p->opt[cur + lenTest];\n+        if (curAndLenPrice < opt->price) \n+        {\n+          opt->price = curAndLenPrice;\n+          opt->posPrev = cur;\n+          opt->backPrev = curBack + LZMA_NUM_REPS;\n+          opt->prev1IsChar = False;\n+        }\n+\n+        if (/*_maxMode && */lenTest == matchDistances[offs])\n+        {\n+          /* Try Match + Literal + Rep0 */\n+          const Byte *data2 = data - (curBack + 1);\n+          UInt32 lenTest2 = lenTest + 1;\n+          UInt32 limit = lenTest2 + p->numFastBytes;\n+          UInt32 nextRepMatchPrice;\n+          if (limit > numAvailableBytesFull)\n+            limit = numAvailableBytesFull;\n+          for (; lenTest2 < limit && data[lenTest2] == data2[lenTest2]; lenTest2++);\n+          lenTest2 -= lenTest + 1;\n+          if (lenTest2 >= 2)\n+          {\n+            UInt32 state2 = kMatchNextStates[state];\n+            UInt32 posStateNext = (position + lenTest) & p->pbMask;\n+            UInt32 curAndLenCharPrice = curAndLenPrice + \n+                GET_PRICE_0(p->isMatch[state2][posStateNext]) +\n+                LitEnc_GetPriceMatched(LIT_PROBS(position + lenTest, data[lenTest - 1]),\n+                    data[lenTest], data2[lenTest], p->ProbPrices);\n+            state2 = kLiteralNextStates[state2];\n+            posStateNext = (posStateNext + 1) & p->pbMask;\n+            nextRepMatchPrice = curAndLenCharPrice + \n+                GET_PRICE_1(p->isMatch[state2][posStateNext]) +\n+                GET_PRICE_1(p->isRep[state2]);\n+            \n+            /* for (; lenTest2 >= 2; lenTest2--) */\n+            {\n+              UInt32 offset = cur + lenTest + 1 + lenTest2;\n+              UInt32 curAndLenPrice;\n+              COptimal *opt;\n+              while (lenEnd < offset)\n+                p->opt[++lenEnd].price = kInfinityPrice;\n+              curAndLenPrice = nextRepMatchPrice + GetRepPrice(p, 0, lenTest2, state2, posStateNext);\n+              opt = &p->opt[offset];\n+              if (curAndLenPrice < opt->price) \n+              {\n+                opt->price = curAndLenPrice;\n+                opt->posPrev = cur + lenTest + 1;\n+                opt->backPrev = 0;\n+                opt->prev1IsChar = True;\n+                opt->prev2 = True;\n+                opt->posPrev2 = cur;\n+                opt->backPrev2 = curBack + LZMA_NUM_REPS;\n+              }\n+            }\n+          }\n+          offs += 2;\n+          if (offs == numDistancePairs)\n+            break;\n+          curBack = matchDistances[offs + 1];\n+          if (curBack >= kNumFullDistances)\n+            GetPosSlot2(curBack, posSlot);\n+        }\n+      }\n+    }\n+  }\n+}\n+\n+#define ChangePair(smallDist, bigDist) (((bigDist) >> 7) > (smallDist))\n+\n+static UInt32 GetOptimumFast(CLzmaEnc *p, UInt32 *backRes)\n+{\n+  UInt32 numAvailableBytes = p->matchFinder.GetNumAvailableBytes(p->matchFinderObj);\n+  UInt32 lenMain, numDistancePairs;\n+  const Byte *data;\n+  UInt32 repLens[LZMA_NUM_REPS];\n+  UInt32 repMaxIndex, i;\n+  UInt32 *matchDistances;\n+  UInt32 backMain;\n+\n+  if (!p->longestMatchWasFound)\n+  {\n+    lenMain = ReadMatchDistances(p, &numDistancePairs);\n+  }\n+  else\n+  {\n+    lenMain = p->longestMatchLength;\n+    numDistancePairs = p->numDistancePairs;\n+    p->longestMatchWasFound = False;\n+  }\n+\n+  data = p->matchFinder.GetPointerToCurrentPos(p->matchFinderObj) - 1;\n+  if (numAvailableBytes > LZMA_MATCH_LEN_MAX)\n+    numAvailableBytes = LZMA_MATCH_LEN_MAX;\n+  if (numAvailableBytes < 2)\n+  {\n+    *backRes = (UInt32)(-1);\n+    return 1;\n+  }\n+\n+  repMaxIndex = 0;\n+\n+  for (i = 0; i < LZMA_NUM_REPS; i++)\n+  {\n+    const Byte *data2 = data - (p->reps[i] + 1);\n+    UInt32 len;\n+    if (data[0] != data2[0] || data[1] != data2[1])\n+    {\n+      repLens[i] = 0;\n+      continue;\n+    }\n+    for (len = 2; len < numAvailableBytes && data[len] == data2[len]; len++);\n+    if (len >= p->numFastBytes)\n+    {\n+      *backRes = i;\n+      MovePos(p, len - 1);\n+      return len;\n+    }\n+    repLens[i] = len;\n+    if (len > repLens[repMaxIndex])\n+      repMaxIndex = i;\n+  }\n+  matchDistances = p->matchDistances;\n+  if (lenMain >= p->numFastBytes)\n+  {\n+    *backRes = matchDistances[numDistancePairs - 1] + LZMA_NUM_REPS; \n+    MovePos(p, lenMain - 1);\n+    return lenMain;\n+  }\n+\n+  backMain = 0; /* for GCC */\n+  if (lenMain >= 2)\n+  {\n+    backMain = matchDistances[numDistancePairs - 1];\n+    while (numDistancePairs > 2 && lenMain == matchDistances[numDistancePairs - 4] + 1)\n+    {\n+      if (!ChangePair(matchDistances[numDistancePairs - 3], backMain))\n+        break;\n+      numDistancePairs -= 2;\n+      lenMain = matchDistances[numDistancePairs - 2];\n+      backMain = matchDistances[numDistancePairs - 1];\n+    }\n+    if (lenMain == 2 && backMain >= 0x80)\n+      lenMain = 1;\n+  }\n+\n+  if (repLens[repMaxIndex] >= 2)\n+  {\n+    if (repLens[repMaxIndex] + 1 >= lenMain || \n+        (repLens[repMaxIndex] + 2 >= lenMain && (backMain > (1 << 9))) ||\n+        (repLens[repMaxIndex] + 3 >= lenMain && (backMain > (1 << 15))))\n+    {\n+      UInt32 lenRes;\n+      *backRes = repMaxIndex;\n+      lenRes = repLens[repMaxIndex];\n+      MovePos(p, lenRes - 1);\n+      return lenRes;\n+    }\n+  }\n+  \n+  if (lenMain >= 2 && numAvailableBytes > 2)\n+  {\n+    UInt32 i;\n+    numAvailableBytes = p->matchFinder.GetNumAvailableBytes(p->matchFinderObj);\n+    p->longestMatchLength = ReadMatchDistances(p, &p->numDistancePairs);\n+    if (p->longestMatchLength >= 2)\n+    {\n+      UInt32 newDistance = matchDistances[p->numDistancePairs - 1];\n+      if ((p->longestMatchLength >= lenMain && newDistance < backMain) || \n+          (p->longestMatchLength == lenMain + 1 && !ChangePair(backMain, newDistance)) ||\n+          (p->longestMatchLength > lenMain + 1) ||\n+          (p->longestMatchLength + 1 >= lenMain && lenMain >= 3 && ChangePair(newDistance, backMain)))\n+      {\n+        p->longestMatchWasFound = True;\n+        *backRes = (UInt32)(-1);\n+        return 1;\n+      }\n+    }\n+    data = p->matchFinder.GetPointerToCurrentPos(p->matchFinderObj) - 1;\n+    for (i = 0; i < LZMA_NUM_REPS; i++)\n+    {\n+      UInt32 len;\n+      const Byte *data2 = data - (p->reps[i] + 1);\n+      if (data[1] != data2[1] || data[2] != data2[2])\n+      {\n+        repLens[i] = 0;\n+        continue;\n+      }\n+      for (len = 2; len < numAvailableBytes && data[len] == data2[len]; len++);\n+      if (len + 1 >= lenMain)\n+      {\n+        p->longestMatchWasFound = True;\n+        *backRes = (UInt32)(-1);\n+        return 1;\n+      }\n+    }\n+    *backRes = backMain + LZMA_NUM_REPS; \n+    MovePos(p, lenMain - 2);\n+    return lenMain;\n+  }\n+  *backRes = (UInt32)(-1);\n+  return 1;\n+}\n+\n+static void WriteEndMarker(CLzmaEnc *p, UInt32 posState)\n+{\n+  UInt32 len;\n+  RangeEnc_EncodeBit(&p->rc, &p->isMatch[p->state][posState], 1);\n+  RangeEnc_EncodeBit(&p->rc, &p->isRep[p->state], 0);\n+  p->state = kMatchNextStates[p->state];\n+  len = LZMA_MATCH_LEN_MIN;\n+  LenEnc_Encode2(&p->lenEnc, &p->rc, len - LZMA_MATCH_LEN_MIN, posState, !p->fastMode, p->ProbPrices);\n+  RcTree_Encode(&p->rc, p->posSlotEncoder[GetLenToPosState(len)], kNumPosSlotBits, (1 << kNumPosSlotBits) - 1);\n+  RangeEnc_EncodeDirectBits(&p->rc, (((UInt32)1 << 30) - 1) >> kNumAlignBits, 30 - kNumAlignBits);\n+  RcTree_ReverseEncode(&p->rc, p->posAlignEncoder, kNumAlignBits, kAlignMask);\n+}\n+\n+static SRes CheckErrors(CLzmaEnc *p)\n+{\n+  if (p->result != SZ_OK)\n+    return p->result;\n+  if (p->rc.res != SZ_OK)\n+    p->result = SZ_ERROR_WRITE;\n+  if (p->matchFinderBase.result != SZ_OK)\n+    p->result = SZ_ERROR_READ;\n+  if (p->result != SZ_OK)\n+    p->finished = True;\n+  return p->result;\n+}\n+\n+static SRes Flush(CLzmaEnc *p, UInt32 nowPos)\n+{\n+  /* ReleaseMFStream(); */\n+  p->finished = True;\n+  if (p->writeEndMark)\n+    WriteEndMarker(p, nowPos & p->pbMask);\n+  RangeEnc_FlushData(&p->rc);\n+  RangeEnc_FlushStream(&p->rc);\n+  return CheckErrors(p);\n+}\n+\n+static void FillAlignPrices(CLzmaEnc *p)\n+{\n+  UInt32 i;\n+  for (i = 0; i < kAlignTableSize; i++)\n+    p->alignPrices[i] = RcTree_ReverseGetPrice(p->posAlignEncoder, kNumAlignBits, i, p->ProbPrices);\n+  p->alignPriceCount = 0;\n+}\n+\n+static void FillDistancesPrices(CLzmaEnc *p)\n+{\n+  UInt32 tempPrices[kNumFullDistances];\n+  UInt32 i, lenToPosState;\n+  for (i = kStartPosModelIndex; i < kNumFullDistances; i++)\n+  { \n+    UInt32 posSlot = GetPosSlot1(i);\n+    UInt32 footerBits = ((posSlot >> 1) - 1);\n+    UInt32 base = ((2 | (posSlot & 1)) << footerBits);\n+    tempPrices[i] = RcTree_ReverseGetPrice(p->posEncoders + base - posSlot - 1, footerBits, i - base, p->ProbPrices);\n+  }\n+\n+  for (lenToPosState = 0; lenToPosState < kNumLenToPosStates; lenToPosState++)\n+  {\n+    UInt32 posSlot;\n+    const CLzmaProb *encoder = p->posSlotEncoder[lenToPosState];\n+    UInt32 *posSlotPrices = p->posSlotPrices[lenToPosState];\n+    for (posSlot = 0; posSlot < p->distTableSize; posSlot++)\n+      posSlotPrices[posSlot] = RcTree_GetPrice(encoder, kNumPosSlotBits, posSlot, p->ProbPrices);\n+    for (posSlot = kEndPosModelIndex; posSlot < p->distTableSize; posSlot++)\n+      posSlotPrices[posSlot] += ((((posSlot >> 1) - 1) - kNumAlignBits) << kNumBitPriceShiftBits);\n+\n+    {\n+      UInt32 *distancesPrices = p->distancesPrices[lenToPosState];\n+      UInt32 i;\n+      for (i = 0; i < kStartPosModelIndex; i++)\n+        distancesPrices[i] = posSlotPrices[i];\n+      for (; i < kNumFullDistances; i++)\n+        distancesPrices[i] = posSlotPrices[GetPosSlot1(i)] + tempPrices[i];\n+    }\n+  }\n+  p->matchPriceCount = 0;\n+}\n+\n+static void LzmaEnc_Construct(CLzmaEnc *p)\n+{\n+  RangeEnc_Construct(&p->rc);\n+  MatchFinder_Construct(&p->matchFinderBase);\n+  #ifdef COMPRESS_MF_MT\n+  MatchFinderMt_Construct(&p->matchFinderMt);\n+  p->matchFinderMt.MatchFinder = &p->matchFinderBase;\n+  #endif\n+\n+  {\n+    CLzmaEncProps props;\n+    LzmaEncProps_Init(&props);\n+    LzmaEnc_SetProps(p, &props);\n+  }\n+\n+  #ifndef LZMA_LOG_BSR\n+  LzmaEnc_FastPosInit(p->g_FastPos);\n+  #endif\n+\n+  LzmaEnc_InitPriceTables(p->ProbPrices);\n+  p->litProbs = 0;\n+  p->saveState.litProbs = 0;\n+}\n+\n+CLzmaEncHandle LzmaEnc_Create(ISzAlloc *alloc)\n+{\n+  void *p;\n+  p = alloc->Alloc(alloc, sizeof(CLzmaEnc));\n+  if (p != 0)\n+    LzmaEnc_Construct((CLzmaEnc *)p);\n+  return p;\n+}\n+\n+static void LzmaEnc_FreeLits(CLzmaEnc *p, ISzAlloc *alloc)\n+{\n+  alloc->Free(alloc, p->litProbs);\n+  alloc->Free(alloc, p->saveState.litProbs);\n+  p->litProbs = 0;\n+  p->saveState.litProbs = 0;\n+}\n+\n+static void LzmaEnc_Destruct(CLzmaEnc *p, ISzAlloc *alloc, ISzAlloc *allocBig)\n+{\n+  #ifdef COMPRESS_MF_MT\n+  MatchFinderMt_Destruct(&p->matchFinderMt, allocBig);\n+  #endif\n+  MatchFinder_Free(&p->matchFinderBase, allocBig);\n+  LzmaEnc_FreeLits(p, alloc);\n+  RangeEnc_Free(&p->rc, alloc);\n+}\n+\n+void LzmaEnc_Destroy(CLzmaEncHandle p, ISzAlloc *alloc, ISzAlloc *allocBig)\n+{\n+  LzmaEnc_Destruct((CLzmaEnc *)p, alloc, allocBig);\n+  alloc->Free(alloc, p);\n+}\n+\n+static SRes LzmaEnc_CodeOneBlock(CLzmaEnc *p, Bool useLimits, UInt32 maxPackSize, UInt32 maxUnpackSize)\n+{\n+  UInt32 nowPos32, startPos32;\n+  if (p->inStream != 0)\n+  {\n+    p->matchFinderBase.stream = p->inStream;\n+    p->matchFinder.Init(p->matchFinderObj);\n+    p->inStream = 0;\n+  }\n+\n+  if (p->finished)\n+    return p->result;\n+  RINOK(CheckErrors(p));\n+\n+  nowPos32 = (UInt32)p->nowPos64;\n+  startPos32 = nowPos32;\n+\n+  if (p->nowPos64 == 0)\n+  {\n+    UInt32 numDistancePairs;\n+    Byte curByte;\n+    if (p->matchFinder.GetNumAvailableBytes(p->matchFinderObj) == 0)\n+      return Flush(p, nowPos32);\n+    ReadMatchDistances(p, &numDistancePairs);\n+    RangeEnc_EncodeBit(&p->rc, &p->isMatch[p->state][0], 0);\n+    p->state = kLiteralNextStates[p->state];\n+    curByte = p->matchFinder.GetIndexByte(p->matchFinderObj, 0 - p->additionalOffset);\n+    LitEnc_Encode(&p->rc, p->litProbs, curByte);\n+    p->additionalOffset--;\n+    nowPos32++;\n+  }\n+\n+  if (p->matchFinder.GetNumAvailableBytes(p->matchFinderObj) != 0)\n+  for (;;)\n+  {\n+    UInt32 pos, len, posState;\n+\n+    if (p->fastMode)\n+      len = GetOptimumFast(p, &pos);\n+    else\n+      len = GetOptimum(p, nowPos32, &pos);\n+\n+    #ifdef SHOW_STAT2\n+    printf(\"\\n pos = %4X,   len = %d   pos = %d\", nowPos32, len, pos);\n+    #endif\n+\n+    posState = nowPos32 & p->pbMask;\n+    if (len == 1 && pos == 0xFFFFFFFF)\n+    {\n+      Byte curByte;\n+      CLzmaProb *probs;\n+      const Byte *data;\n+\n+      RangeEnc_EncodeBit(&p->rc, &p->isMatch[p->state][posState], 0);\n+      data = p->matchFinder.GetPointerToCurrentPos(p->matchFinderObj) - p->additionalOffset;\n+      curByte = *data;\n+      probs = LIT_PROBS(nowPos32, *(data - 1));\n+      if (IsCharState(p->state))\n+        LitEnc_Encode(&p->rc, probs, curByte);\n+      else\n+        LitEnc_EncodeMatched(&p->rc, probs, curByte, *(data - p->reps[0] - 1));\n+      p->state = kLiteralNextStates[p->state];\n+    }\n+    else\n+    {\n+      RangeEnc_EncodeBit(&p->rc, &p->isMatch[p->state][posState], 1);\n+      if (pos < LZMA_NUM_REPS)\n+      {\n+        RangeEnc_EncodeBit(&p->rc, &p->isRep[p->state], 1);\n+        if (pos == 0)\n+        {\n+          RangeEnc_EncodeBit(&p->rc, &p->isRepG0[p->state], 0);\n+          RangeEnc_EncodeBit(&p->rc, &p->isRep0Long[p->state][posState], ((len == 1) ? 0 : 1));\n+        }\n+        else\n+        {\n+          UInt32 distance = p->reps[pos];\n+          RangeEnc_EncodeBit(&p->rc, &p->isRepG0[p->state], 1);\n+          if (pos == 1)\n+            RangeEnc_EncodeBit(&p->rc, &p->isRepG1[p->state], 0);\n+          else\n+          {\n+            RangeEnc_EncodeBit(&p->rc, &p->isRepG1[p->state], 1);\n+            RangeEnc_EncodeBit(&p->rc, &p->isRepG2[p->state], pos - 2);\n+            if (pos == 3)\n+              p->reps[3] = p->reps[2];\n+            p->reps[2] = p->reps[1];\n+          }\n+          p->reps[1] = p->reps[0];\n+          p->reps[0] = distance;\n+        }\n+        if (len == 1)\n+          p->state = kShortRepNextStates[p->state];\n+        else\n+        {\n+          LenEnc_Encode2(&p->repLenEnc, &p->rc, len - LZMA_MATCH_LEN_MIN, posState, !p->fastMode, p->ProbPrices);\n+          p->state = kRepNextStates[p->state];\n+        }\n+      }\n+      else\n+      {\n+        UInt32 posSlot;\n+        RangeEnc_EncodeBit(&p->rc, &p->isRep[p->state], 0);\n+        p->state = kMatchNextStates[p->state];\n+        LenEnc_Encode2(&p->lenEnc, &p->rc, len - LZMA_MATCH_LEN_MIN, posState, !p->fastMode, p->ProbPrices);\n+        pos -= LZMA_NUM_REPS;\n+        GetPosSlot(pos, posSlot);\n+        RcTree_Encode(&p->rc, p->posSlotEncoder[GetLenToPosState(len)], kNumPosSlotBits, posSlot);\n+        \n+        if (posSlot >= kStartPosModelIndex)\n+        {\n+          UInt32 footerBits = ((posSlot >> 1) - 1);\n+          UInt32 base = ((2 | (posSlot & 1)) << footerBits);\n+          UInt32 posReduced = pos - base;\n+\n+          if (posSlot < kEndPosModelIndex)\n+            RcTree_ReverseEncode(&p->rc, p->posEncoders + base - posSlot - 1, footerBits, posReduced);\n+          else\n+          {\n+            RangeEnc_EncodeDirectBits(&p->rc, posReduced >> kNumAlignBits, footerBits - kNumAlignBits);\n+            RcTree_ReverseEncode(&p->rc, p->posAlignEncoder, kNumAlignBits, posReduced & kAlignMask);\n+            p->alignPriceCount++;\n+          }\n+        }\n+        p->reps[3] = p->reps[2];\n+        p->reps[2] = p->reps[1];\n+        p->reps[1] = p->reps[0];\n+        p->reps[0] = pos;\n+        p->matchPriceCount++;\n+      }\n+    }\n+    p->additionalOffset -= len;\n+    nowPos32 += len;\n+    if (p->additionalOffset == 0)\n+    {\n+      UInt32 processed;\n+      if (!p->fastMode)\n+      {\n+        if (p->matchPriceCount >= (1 << 7))\n+          FillDistancesPrices(p);\n+        if (p->alignPriceCount >= kAlignTableSize)\n+          FillAlignPrices(p);\n+      }\n+      if (p->matchFinder.GetNumAvailableBytes(p->matchFinderObj) == 0)\n+        break;\n+      processed = nowPos32 - startPos32;\n+      if (useLimits)\n+      {\n+        if (processed + kNumOpts + 300 >= maxUnpackSize ||\n+            RangeEnc_GetProcessed(&p->rc) + kNumOpts * 2 >= maxPackSize)\n+          break;\n+      }\n+      else if (processed >= (1 << 15))\n+      {\n+        p->nowPos64 += nowPos32 - startPos32;\n+        return CheckErrors(p);\n+      }\n+    }\n+  }\n+  p->nowPos64 += nowPos32 - startPos32;\n+  return Flush(p, nowPos32);\n+}\n+\n+#define kBigHashDicLimit ((UInt32)1 << 24)\n+\n+static SRes LzmaEnc_Alloc(CLzmaEnc *p, UInt32 keepWindowSize, ISzAlloc *alloc, ISzAlloc *allocBig)\n+{\n+  UInt32 beforeSize = kNumOpts;\n+  Bool btMode;\n+  if (!RangeEnc_Alloc(&p->rc, alloc))\n+    return SZ_ERROR_MEM;\n+  btMode = (p->matchFinderBase.btMode != 0);\n+  #ifdef COMPRESS_MF_MT\n+  p->mtMode = (p->multiThread && !p->fastMode && btMode);\n+  #endif\n+\n+  {\n+    unsigned lclp = p->lc + p->lp;\n+    if (p->litProbs == 0 || p->saveState.litProbs == 0 || p->lclp != lclp)\n+    {\n+      LzmaEnc_FreeLits(p, alloc);\n+      p->litProbs = (CLzmaProb *)alloc->Alloc(alloc, (0x300 << lclp) * sizeof(CLzmaProb));\n+      p->saveState.litProbs = (CLzmaProb *)alloc->Alloc(alloc, (0x300 << lclp) * sizeof(CLzmaProb));\n+      if (p->litProbs == 0 || p->saveState.litProbs == 0)\n+      {\n+        LzmaEnc_FreeLits(p, alloc);\n+        return SZ_ERROR_MEM;\n+      }\n+      p->lclp = lclp;\n+    }\n+  }\n+\n+  p->matchFinderBase.bigHash = (p->dictSize > kBigHashDicLimit);\n+\n+  if (beforeSize + p->dictSize < keepWindowSize)\n+    beforeSize = keepWindowSize - p->dictSize;\n+\n+  #ifdef COMPRESS_MF_MT\n+  if (p->mtMode)\n+  {\n+    RINOK(MatchFinderMt_Create(&p->matchFinderMt, p->dictSize, beforeSize, p->numFastBytes, LZMA_MATCH_LEN_MAX, allocBig));\n+    p->matchFinderObj = &p->matchFinderMt;\n+    MatchFinderMt_CreateVTable(&p->matchFinderMt, &p->matchFinder);\n+  }\n+  else\n+  #endif\n+  {\n+    if (!MatchFinder_Create(&p->matchFinderBase, p->dictSize, beforeSize, p->numFastBytes, LZMA_MATCH_LEN_MAX, allocBig))\n+      return SZ_ERROR_MEM;\n+    p->matchFinderObj = &p->matchFinderBase;\n+    MatchFinder_CreateVTable(&p->matchFinderBase, &p->matchFinder);\n+  }\n+  return SZ_OK;\n+}\n+\n+static void LzmaEnc_Init(CLzmaEnc *p)\n+{\n+  UInt32 i;\n+  p->state = 0;\n+  for(i = 0 ; i < LZMA_NUM_REPS; i++)\n+    p->reps[i] = 0;\n+\n+  RangeEnc_Init(&p->rc);\n+\n+\n+  for (i = 0; i < kNumStates; i++)\n+  {\n+    UInt32 j;\n+    for (j = 0; j < LZMA_NUM_PB_STATES_MAX; j++)\n+    {\n+      p->isMatch[i][j] = kProbInitValue;\n+      p->isRep0Long[i][j] = kProbInitValue;\n+    }\n+    p->isRep[i] = kProbInitValue;\n+    p->isRepG0[i] = kProbInitValue;\n+    p->isRepG1[i] = kProbInitValue;\n+    p->isRepG2[i] = kProbInitValue;\n+  }\n+\n+  {\n+    UInt32 num = 0x300 << (p->lp + p->lc);\n+    for (i = 0; i < num; i++)\n+      p->litProbs[i] = kProbInitValue;\n+  }\n+\n+  {\n+    for (i = 0; i < kNumLenToPosStates; i++)\n+    {\n+      CLzmaProb *probs = p->posSlotEncoder[i];\n+      UInt32 j;\n+      for (j = 0; j < (1 << kNumPosSlotBits); j++)\n+        probs[j] = kProbInitValue;\n+    }\n+  }\n+  {\n+    for(i = 0; i < kNumFullDistances - kEndPosModelIndex; i++)\n+      p->posEncoders[i] = kProbInitValue;\n+  }\n+\n+  LenEnc_Init(&p->lenEnc.p);\n+  LenEnc_Init(&p->repLenEnc.p);\n+\n+  for (i = 0; i < (1 << kNumAlignBits); i++)\n+    p->posAlignEncoder[i] = kProbInitValue;\n+\n+  p->longestMatchWasFound = False;\n+  p->optimumEndIndex = 0;\n+  p->optimumCurrentIndex = 0;\n+  p->additionalOffset = 0;\n+\n+  p->pbMask = (1 << p->pb) - 1;\n+  p->lpMask = (1 << p->lp) - 1;\n+}\n+\n+static void LzmaEnc_InitPrices(CLzmaEnc *p)\n+{\n+  if (!p->fastMode)\n+  {\n+    FillDistancesPrices(p);\n+    FillAlignPrices(p);\n+  }\n+\n+  p->lenEnc.tableSize = \n+  p->repLenEnc.tableSize = \n+      p->numFastBytes + 1 - LZMA_MATCH_LEN_MIN;\n+  LenPriceEnc_UpdateTables(&p->lenEnc, 1 << p->pb, p->ProbPrices);\n+  LenPriceEnc_UpdateTables(&p->repLenEnc, 1 << p->pb, p->ProbPrices);\n+}\n+\n+static SRes LzmaEnc_AllocAndInit(CLzmaEnc *p, UInt32 keepWindowSize, ISzAlloc *alloc, ISzAlloc *allocBig)\n+{\n+  UInt32 i;\n+  for (i = 0; i < (UInt32)kDicLogSizeMaxCompress; i++)\n+    if (p->dictSize <= ((UInt32)1 << i))\n+      break;\n+  p->distTableSize = i * 2;\n+\n+  p->finished = False;\n+  p->result = SZ_OK;\n+  RINOK(LzmaEnc_Alloc(p, keepWindowSize, alloc, allocBig));\n+  LzmaEnc_Init(p);\n+  LzmaEnc_InitPrices(p);\n+  p->nowPos64 = 0;\n+  return SZ_OK;\n+}\n+\n+static SRes LzmaEnc_Prepare(CLzmaEncHandle pp, ISeqInStream *inStream, ISeqOutStream *outStream,\n+    ISzAlloc *alloc, ISzAlloc *allocBig)\n+{\n+  CLzmaEnc *p = (CLzmaEnc *)pp;\n+  p->inStream = inStream;\n+  p->rc.outStream = outStream;\n+  return LzmaEnc_AllocAndInit(p, 0, alloc, allocBig);\n+}\n+\n+static SRes LzmaEnc_PrepareForLzma2(CLzmaEncHandle pp, \n+    ISeqInStream *inStream, UInt32 keepWindowSize,\n+    ISzAlloc *alloc, ISzAlloc *allocBig)\n+{\n+  CLzmaEnc *p = (CLzmaEnc *)pp;\n+  p->inStream = inStream;\n+  return LzmaEnc_AllocAndInit(p, keepWindowSize, alloc, allocBig);\n+}\n+\n+static void LzmaEnc_SetInputBuf(CLzmaEnc *p, const Byte *src, SizeT srcLen)\n+{\n+  p->seqBufInStream.funcTable.Read = MyRead;\n+  p->seqBufInStream.data = src;\n+  p->seqBufInStream.rem = srcLen;\n+}\n+\n+static SRes LzmaEnc_MemPrepare(CLzmaEncHandle pp, const Byte *src, SizeT srcLen,\n+    UInt32 keepWindowSize, ISzAlloc *alloc, ISzAlloc *allocBig)\n+{\n+  CLzmaEnc *p = (CLzmaEnc *)pp;\n+  LzmaEnc_SetInputBuf(p, src, srcLen);\n+  p->inStream = &p->seqBufInStream.funcTable;\n+  return LzmaEnc_AllocAndInit(p, keepWindowSize, alloc, allocBig);\n+}\n+\n+static void LzmaEnc_Finish(CLzmaEncHandle pp)\n+{\n+  #ifdef COMPRESS_MF_MT\n+  CLzmaEnc *p = (CLzmaEnc *)pp;\n+  if (p->mtMode)\n+    MatchFinderMt_ReleaseStream(&p->matchFinderMt);\n+  #endif\n+}\n+\n+typedef struct _CSeqOutStreamBuf\n+{\n+  ISeqOutStream funcTable;\n+  Byte *data;\n+  SizeT rem;\n+  Bool overflow;\n+} CSeqOutStreamBuf;\n+\n+static size_t MyWrite(void *pp, const void *data, size_t size)\n+{\n+  CSeqOutStreamBuf *p = (CSeqOutStreamBuf *)pp;\n+  if (p->rem < size)\n+  {\n+    size = p->rem;\n+    p->overflow = True;\n+  }\n+  memcpy(p->data, data, size);\n+  p->rem -= size;\n+  p->data += size;\n+  return size;\n+}\n+\n+\n+static UInt32 LzmaEnc_GetNumAvailableBytes(CLzmaEncHandle pp)\n+{\n+  const CLzmaEnc *p = (CLzmaEnc *)pp;\n+  return p->matchFinder.GetNumAvailableBytes(p->matchFinderObj);\n+}\n+\n+static const Byte *LzmaEnc_GetCurBuf(CLzmaEncHandle pp)\n+{\n+  const CLzmaEnc *p = (CLzmaEnc *)pp;\n+  return p->matchFinder.GetPointerToCurrentPos(p->matchFinderObj) - p->additionalOffset;\n+}\n+\n+static SRes LzmaEnc_CodeOneMemBlock(CLzmaEncHandle pp, Bool reInit, \n+    Byte *dest, size_t *destLen, UInt32 desiredPackSize, UInt32 *unpackSize)\n+{\n+  CLzmaEnc *p = (CLzmaEnc *)pp;\n+  UInt64 nowPos64;\n+  SRes res;\n+  CSeqOutStreamBuf outStream;\n+\n+  outStream.funcTable.Write = MyWrite;\n+  outStream.data = dest;\n+  outStream.rem = *destLen;\n+  outStream.overflow = False;\n+\n+  p->writeEndMark = False;\n+  p->finished = False;\n+  p->result = SZ_OK;\n+\n+  if (reInit)\n+    LzmaEnc_Init(p);\n+  LzmaEnc_InitPrices(p);\n+  nowPos64 = p->nowPos64;\n+  RangeEnc_Init(&p->rc);\n+  p->rc.outStream = &outStream.funcTable;\n+\n+  res = LzmaEnc_CodeOneBlock(pp, True, desiredPackSize, *unpackSize);\n+  \n+  *unpackSize = (UInt32)(p->nowPos64 - nowPos64);\n+  *destLen -= outStream.rem;\n+  if (outStream.overflow)\n+    return SZ_ERROR_OUTPUT_EOF;\n+\n+  return res;\n+}\n+\n+SRes LzmaEnc_Encode(CLzmaEncHandle pp, ISeqOutStream *outStream, ISeqInStream *inStream, ICompressProgress *progress,\n+    ISzAlloc *alloc, ISzAlloc *allocBig)\n+{\n+  CLzmaEnc *p = (CLzmaEnc *)pp;\n+  SRes res = SZ_OK;\n+\n+  #ifdef COMPRESS_MF_MT\n+  Byte allocaDummy[0x300];\n+  int i = 0;\n+  for (i = 0; i < 16; i++)\n+    allocaDummy[i] = (Byte)i;\n+  #endif\n+\n+  RINOK(LzmaEnc_Prepare(pp, inStream, outStream, alloc, allocBig));\n+\n+  for (;;)\n+  {\n+    res = LzmaEnc_CodeOneBlock(pp, False, 0, 0);\n+    if (res != SZ_OK || p->finished != 0)\n+      break;\n+    if (progress != 0)\n+    {\n+      res = progress->Progress(progress, p->nowPos64, RangeEnc_GetProcessed(&p->rc));\n+      if (res != SZ_OK)\n+      {\n+        res = SZ_ERROR_PROGRESS;\n+        break;\n+      }\n+    }\n+  }\n+  LzmaEnc_Finish(pp);\n+  return res;\n+}\n+\n+SRes LzmaEnc_WriteProperties(CLzmaEncHandle pp, Byte *props, SizeT *size)\n+{\n+  CLzmaEnc *p = (CLzmaEnc *)pp;\n+  int i;\n+  UInt32 dictSize = p->dictSize;\n+  if (*size < LZMA_PROPS_SIZE)\n+    return SZ_ERROR_PARAM;\n+  *size = LZMA_PROPS_SIZE;\n+  props[0] = (Byte)((p->pb * 5 + p->lp) * 9 + p->lc);\n+\n+  for (i = 11; i <= 30; i++)\n+  {\n+    if (dictSize <= ((UInt32)2 << i))\n+    {\n+      dictSize = (2 << i);\n+      break;\n+    }\n+    if (dictSize <= ((UInt32)3 << i))\n+    {\n+      dictSize = (3 << i);\n+      break;\n+    }\n+  }\n+\n+  for (i = 0; i < 4; i++)\n+    props[1 + i] = (Byte)(dictSize >> (8 * i));\n+  return SZ_OK;\n+}\n+\n+SRes LzmaEnc_MemEncode(CLzmaEncHandle pp, Byte *dest, SizeT *destLen, const Byte *src, SizeT srcLen,\n+    int writeEndMark, ICompressProgress *progress, ISzAlloc *alloc, ISzAlloc *allocBig)\n+{\n+  SRes res;\n+  CLzmaEnc *p = (CLzmaEnc *)pp;\n+\n+  CSeqOutStreamBuf outStream;\n+\n+  LzmaEnc_SetInputBuf(p, src, srcLen);\n+\n+  outStream.funcTable.Write = MyWrite;\n+  outStream.data = dest;\n+  outStream.rem = *destLen;\n+  outStream.overflow = False;\n+\n+  p->writeEndMark = writeEndMark;\n+  res = LzmaEnc_Encode(pp, &outStream.funcTable, &p->seqBufInStream.funcTable, \n+      progress, alloc, allocBig);\n+\n+  *destLen -= outStream.rem;\n+  if (outStream.overflow)\n+    return SZ_ERROR_OUTPUT_EOF;\n+  return res;\n+}\n+\n+SRes LzmaEncode(Byte *dest, SizeT *destLen, const Byte *src, SizeT srcLen,\n+    const CLzmaEncProps *props, Byte *propsEncoded, SizeT *propsSize, int writeEndMark, \n+    ICompressProgress *progress, ISzAlloc *alloc, ISzAlloc *allocBig)\n+{\n+  CLzmaEnc *p = (CLzmaEnc *)LzmaEnc_Create(alloc);\n+  SRes res;\n+  if (p == 0)\n+    return SZ_ERROR_MEM;\n+\n+  res = LzmaEnc_SetProps(p, props);\n+  if (res == SZ_OK)\n+  {\n+    res = LzmaEnc_WriteProperties(p, propsEncoded, propsSize);\n+    if (res == SZ_OK)\n+      res = LzmaEnc_MemEncode(p, dest, destLen, src, srcLen,\n+          writeEndMark, progress, alloc, allocBig);\n+  }\n+\n+  LzmaEnc_Destroy(p, alloc, allocBig);\n+  return res;\n+}\n--- a/jffsX-utils/mkfs.jffs2.c\n+++ b/jffsX-utils/mkfs.jffs2.c\n@@ -1667,11 +1667,11 @@ int main(int argc, char **argv)\n \t\t\t\t\t\t  }\n \t\t\t\t\t\t  erase_block_size *= units;\n \n-\t\t\t\t\t\t  /* If it's less than 8KiB, they're not allowed */\n-\t\t\t\t\t\t  if (erase_block_size < 0x2000) {\n-\t\t\t\t\t\t\t  fprintf(stderr, \"Erase size 0x%x too small. Increasing to 8KiB minimum\\n\",\n+\t\t\t\t\t\t  /* If it's less than 4KiB, they're not allowed */\n+\t\t\t\t\t\t  if (erase_block_size < 0x1000) {\n+\t\t\t\t\t\t\t  fprintf(stderr, \"Erase size 0x%x too small. Increasing to 4KiB minimum\\n\",\n \t\t\t\t\t\t\t\t\t  erase_block_size);\n-\t\t\t\t\t\t\t  erase_block_size = 0x2000;\n+\t\t\t\t\t\t\t  erase_block_size = 0x1000;\n \t\t\t\t\t\t  }\n \t\t\t\t\t\t  break;\n \t\t\t\t\t  }\n"
  },
  {
    "path": "tools/mtd-utils/patches/134-freebsd_loff_t.patch",
    "content": "--- a/include/mtd/mtd-abi.h\n+++ b/include/mtd/mtd-abi.h\n@@ -171,9 +171,9 @@ struct otp_info {\n /* Get info about OOB modes (e.g., RAW, PLACE, AUTO) - legacy interface */\n #define MEMGETOOBSEL\t\t_IOR('M', 10, struct nand_oobinfo)\n /* Check if an eraseblock is bad */\n-#define MEMGETBADBLOCK\t\t_IOW('M', 11, __kernel_loff_t)\n+#define MEMGETBADBLOCK\t\t_IOW('M', 11, loff_t)\n /* Mark an eraseblock as bad */\n-#define MEMSETBADBLOCK\t\t_IOW('M', 12, __kernel_loff_t)\n+#define MEMSETBADBLOCK\t\t_IOW('M', 12, loff_t)\n /* Set OTP (One-Time Programmable) mode (factory vs. user) */\n #define OTPSELECT\t\t_IOR('M', 13, int)\n /* Get number of OTP (One-Time Programmable) regions */\n"
  },
  {
    "path": "tools/mtd-utils/patches/200-libubigen-add-ubigen_write_terminator-function.patch",
    "content": "--- a/lib/libubigen.c\n+++ b/lib/libubigen.c\n@@ -122,8 +122,9 @@ int ubigen_add_volume(const struct ubige\n \treturn 0;\n }\n \n-void ubigen_init_ec_hdr(const struct ubigen_info *ui,\n-\t\t        struct ubi_ec_hdr *hdr, long long ec)\n+static void __ubigen_init_ec_hdr(const struct ubigen_info *ui,\n+\t\t\t\t struct ubi_ec_hdr *hdr, long long ec,\n+\t\t\t\t int eof)\n {\n \tuint32_t crc;\n \n@@ -136,10 +137,22 @@ void ubigen_init_ec_hdr(const struct ubi\n \thdr->data_offset = cpu_to_be32(ui->data_offs);\n \thdr->image_seq = cpu_to_be32(ui->image_seq);\n \n+\tif (eof) {\n+\t\thdr->padding1[0] = 'E';\n+\t\thdr->padding1[1] = 'O';\n+\t\thdr->padding1[2] = 'F';\n+\t}\n+\n \tcrc = mtd_crc32(UBI_CRC32_INIT, hdr, UBI_EC_HDR_SIZE_CRC);\n \thdr->hdr_crc = cpu_to_be32(crc);\n }\n \n+void ubigen_init_ec_hdr(const struct ubigen_info *ui,\n+\t\t        struct ubi_ec_hdr *hdr, long long ec)\n+{\n+\t__ubigen_init_ec_hdr(ui, hdr, ec, 0);\n+}\n+\n void ubigen_init_vid_hdr(const struct ubigen_info *ui,\n \t\t\t const struct ubigen_vol_info *vi,\n \t\t\t struct ubi_vid_hdr *hdr, int lnum,\n@@ -307,6 +320,39 @@ int ubigen_write_layout_vol(const struct\n \t}\n \n \tfree(outbuf);\n+\treturn 0;\n+\n+out_free:\n+\tfree(outbuf);\n+\treturn -1;\n+}\n+\n+int ubigen_write_eof_markers(const struct ubigen_info *ui, long long ec,\n+\t\t\t     int count, int out_fd)\n+{\n+\tchar *outbuf;\n+\tint peb_size = ui->peb_size;\n+\n+\toutbuf = malloc(peb_size);\n+\tif (!outbuf) {\n+\t\tsys_errmsg(\"cannot allocate %d bytes of memory\", peb_size);\n+\t\treturn -1;\n+\t}\n+\n+\tmemset(outbuf, 0xFF, peb_size);\n+\t__ubigen_init_ec_hdr(ui, (struct ubi_ec_hdr *)outbuf, ec, 1);\n+\n+\twhile (count) {\n+\t\tif (write(out_fd, outbuf, peb_size) != peb_size) {\n+\t\t\tsys_errmsg(\"cannot write %d bytes to the output file\",\n+\t\t\t\t   peb_size);\n+\t\t\tgoto out_free;\n+\t\t}\n+\n+\t\tcount--;\n+\t}\n+\n+\tfree(outbuf);\n \treturn 0;\n \n out_free:\n--- a/include/libubigen.h\n+++ b/include/libubigen.h\n@@ -187,6 +187,9 @@ int ubigen_write_layout_vol(const struct\n \t\t\t    long long ec1, long long ec2,\n \t\t\t    struct ubi_vtbl_record *vtbl, int fd);\n \n+int ubigen_write_eof_markers(const struct ubigen_info *ui, long long ec,\n+\t\t\t     int count, int out_fd);\n+\n #ifdef __cplusplus\n }\n #endif\n"
  },
  {
    "path": "tools/mtd-utils/patches/201-ubinize-add-terminator-support.patch",
    "content": "--- a/ubi-utils/ubinize.c\n+++ b/ubi-utils/ubinize.c\n@@ -60,6 +60,8 @@ static const char optionsstr[] =\n \"                             (default is 1)\\n\"\n \"-Q, --image-seq=<num>        32-bit UBI image sequence number to use\\n\"\n \"                             (by default a random number is picked)\\n\"\n+\"-E, --eof-markers=<num>      number of eof-markers to put at the end of the\\n\"\n+\"                             output image\\n\"\n \"-v, --verbose                be verbose\\n\"\n \"-h, --help                   print help message\\n\"\n \"-V, --version                print program version\\n\\n\";\n@@ -79,6 +81,7 @@ static const struct option long_options[\n \t{ .name = \"erase-counter\",  .has_arg = 1, .flag = NULL, .val = 'e' },\n \t{ .name = \"ubi-ver\",        .has_arg = 1, .flag = NULL, .val = 'x' },\n \t{ .name = \"image-seq\",      .has_arg = 1, .flag = NULL, .val = 'Q' },\n+\t{ .name = \"eof-markers\",    .has_arg = 1, .flag = NULL, .val = 'E' },\n \t{ .name = \"verbose\",        .has_arg = 0, .flag = NULL, .val = 'v' },\n \t{ .name = \"help\",           .has_arg = 0, .flag = NULL, .val = 'h' },\n \t{ .name = \"version\",        .has_arg = 0, .flag = NULL, .val = 'V' },\n@@ -98,6 +101,7 @@ struct args {\n \tuint32_t image_seq;\n \tint verbose;\n \tdictionary *dict;\n+\tint eof_markers;\n };\n \n static struct args args = {\n@@ -116,7 +120,7 @@ static int parse_opt(int argc, char * co\n \t\tint key, error = 0;\n \t\tunsigned long int image_seq;\n \n-\t\tkey = getopt_long(argc, argv, \"o:p:m:s:O:e:x:Q:vhV\", long_options, NULL);\n+\t\tkey = getopt_long(argc, argv, \"o:p:m:s:O:e:x:Q:E:vhV\", long_options, NULL);\n \t\tif (key == -1)\n \t\t\tbreak;\n \n@@ -176,6 +180,12 @@ static int parse_opt(int argc, char * co\n \t\t\targs.image_seq = image_seq;\n \t\t\tbreak;\n \n+\t\tcase 'E':\n+\t\t\targs.eof_markers = simple_strtoul(optarg, &error);\n+\t\t\tif (error)\n+\t\t\t\treturn errmsg(\"bad number of eof-markers: \\\"%s\\\"\", optarg);\n+\t\t\tbreak;\n+\n \t\tcase 'v':\n \t\t\targs.verbose = 1;\n \t\t\tbreak;\n@@ -582,6 +592,18 @@ int main(int argc, char * const argv[])\n \t\t\tprintf(\"\\n\");\n \t}\n \n+\tif (args.eof_markers) {\n+\t\tverbose(args.verbose, \"writing %d eof-marker blocks\",\n+\t\t\targs.eof_markers);\n+\n+\t\terr = ubigen_write_eof_markers(&ui, args.ec, args.eof_markers,\n+\t\t\t\t\t       args.out_fd);\n+\t\tif (err) {\n+\t\t\terrmsg(\"cannot write eof-marker blocks\");\n+\t\t\tgoto out_free;\n+\t\t}\n+\t}\n+\n \tverbose(args.verbose, \"writing layout volume\");\n \n \terr = ubigen_write_layout_vol(&ui, 0, 1, args.ec, args.ec, vtbl, args.out_fd);\n"
  },
  {
    "path": "tools/mtd-utils/patches/320-mkfs.jffs2-SOURCE_DATE_EPOCH.patch",
    "content": "--- a/jffsX-utils/mkfs.jffs2.c\n+++ b/jffsX-utils/mkfs.jffs2.c\n@@ -109,7 +109,7 @@ static char *rootdir = default_rootdir;\n static int verbose = 0;\n static int squash_uids = 0;\n static int squash_perms = 0;\n-static int fake_times = 0;\n+static time_t fixed_timestamp = -1;\n int target_endian = __BYTE_ORDER;\n \n static uint32_t find_hardlink(struct filesystem_entry *e)\n@@ -251,8 +251,8 @@ static struct filesystem_entry *add_host\n \t\t\tmode &= ~(S_ISUID | S_ISGID);\n \t\t}\n \t}\n-\tif (fake_times) {\n-\t\ttimestamp = 0;\n+\tif (fixed_timestamp != -1) {\n+\t\ttimestamp = fixed_timestamp;\n \t}\n \n \tentry = xcalloc(1, sizeof(struct filesystem_entry));\n@@ -1558,6 +1558,20 @@ static void parse_image(void){\n \tclose(in_fd);\n }\n \n+static void set_source_date_epoch() {\n+\tchar *env = getenv(\"SOURCE_DATE_EPOCH\");\n+\tchar *endptr = env;\n+\terrno = 0;\n+\tif (env && *env) {\n+\t\tfixed_timestamp = strtoull(env, &endptr, 10);\n+\t\tif (errno || (endptr && *endptr != '\\0')) {\n+\t\t\tfprintf(stderr, \"Invalid SOURCE_DATE_EPOCH\");\n+\t\t\texit(1);\n+\t\t}\n+\t}\n+}\n+\n+\n int main(int argc, char **argv)\n {\n \tint c, opt;\n@@ -1576,6 +1590,7 @@ int main(int argc, char **argv)\n \t\twarn_page_size = 1; /* warn user if page size not 4096 */\n \n \tjffs2_compressors_init();\n+\tset_source_date_epoch();\n \n \twhile ((opt = getopt_long(argc, argv,\n \t\t\t\t\t\"D:d:r:s:o:qUPfh?vVe:lbp::nc:m:x:X:Lty:i:\", long_options, &c)) >= 0)\n@@ -1626,7 +1641,7 @@ int main(int argc, char **argv)\n \t\t\t\tbreak;\n \n \t\t\tcase 'f':\n-\t\t\t\tfake_times = 1;\n+\t\t\t\tfixed_timestamp = 0;\n \t\t\t\tbreak;\n \n \t\t\tcase 'h':\n"
  },
  {
    "path": "tools/mtools/Makefile",
    "content": "# \n# Copyright (C) 2012-2013 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=mtools\nPKG_VERSION:=4.0.39\n\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.bz2\nPKG_SOURCE_URL:=@GNU/$(PKG_NAME)\nPKG_HASH:=397f1e2b7b7a2a270eb7970fa363e445f956926ec51e8170c3869da85b0987bd\n\nHOST_BUILD_PARALLEL:=1\n\ninclude $(INCLUDE_DIR)/host-build.mk\n\nHOST_CONFIGURE_ARGS += --without-x\n\nHOST_CONFIGURE_VARS += \\\n\tac_cv_header_iconv_h=no\n\ndefine Host/Compile\n\t$(MAKE) -C $(HOST_BUILD_DIR) mcopy mmd\nendef\n\ndefine Host/Install\n\t$(INSTALL_BIN) $(HOST_BUILD_DIR)/mcopy $(STAGING_DIR_HOST)/bin/\n\t$(INSTALL_BIN) $(HOST_BUILD_DIR)/mmd $(STAGING_DIR_HOST)/bin/\nendef\n\ndefine Host/Clean\n\trm -f $(STAGING_DIR_HOST)/bin/mcopy\n\trm -f $(STAGING_DIR_HOST)/bin/mmd\nendef\n\n$(eval $(call HostBuild))\n"
  },
  {
    "path": "tools/ninja/Makefile",
    "content": "include $(TOPDIR)/rules.mk\n\nPKG_NAME:=ninja\nPKG_VERSION:=1.10.2\nPKG_RELEASE:=1\n\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz\nPKG_SOURCE_URL:=https://codeload.github.com/ninja-build/ninja/tar.gz/v$(PKG_VERSION)?\nPKG_HASH:=ce35865411f0490368a8fc383f29071de6690cbadc27704734978221f25e2bed\n\ninclude $(INCLUDE_DIR)/host-build.mk\n\nCONFIGURE_ARGS:=\nifneq ($(findstring c,$(OPENWRT_VERBOSE)),)\n  CONFIGURE_ARGS+=--verbose\nendif\n\ndefine Host/Configure\nendef\n\ndefine Host/Compile\n\tcd $(HOST_BUILD_DIR) && \\\n\t\tCXX=\"$(HOSTCXX_NOCACHE)\" \\\n\t\tCXXFLAGS=\"$(HOST_CXXFLAGS) $(HOST_CPPFLAGS)\" \\\n\t\tLDFLAGS=\"$(HOST_LDFLAGS)\" \\\n\t\t$(STAGING_DIR_HOST)/bin/$(PYTHON) configure.py --bootstrap $(CONFIGURE_ARGS)\nendef\n\ndefine Host/Install\n\t$(INSTALL_DIR) $(STAGING_DIR_HOST)/bin\n\t$(INSTALL_BIN) $(HOST_BUILD_DIR)/ninja $(STAGING_DIR_HOST)/bin/\nendef\n\ndefine Host/Clean\n\t$(call Host/Clean/Default)\n\trm -f $(STAGING_DIR_HOST)/bin/ninja\nendef\n\n$(eval $(call HostBuild))\n"
  },
  {
    "path": "tools/ninja/patches/100-make_jobserver_support.patch",
    "content": "From c1a081c00f803fc28e51f155f25abe8346ce5f13 Mon Sep 17 00:00:00 2001\nFrom: Stefan Becker <stefanb@gpartner-nvidia.com>\nDate: Tue, 22 Mar 2016 13:48:07 +0200\nSubject: [PATCH] Add GNU make jobserver client support\n\n- add new TokenPool interface\n- GNU make implementation for TokenPool parses and verifies the magic\n  information from the MAKEFLAGS environment variable\n- RealCommandRunner tries to acquire TokenPool\n  * if no token pool is available then there is no change in behaviour\n- When a token pool is available then RealCommandRunner behaviour\n  changes as follows\n  * CanRunMore() only returns true if TokenPool::Acquire() returns true\n  * StartCommand() calls TokenPool::Reserve()\n  * WaitForCommand() calls TokenPool::Release()\n\nDocumentation for GNU make jobserver\n\n  http://make.mad-scientist.net/papers/jobserver-implementation/\n\nFixes https://github.com/ninja-build/ninja/issues/1139\n\nAdd TokenPool monitoring to SubprocessSet::DoWork()\n\nImprove on the original jobserver client implementation. This makes\nninja a more aggressive GNU make jobserver client.\n\n- add monitor interface to TokenPool\n- TokenPool is passed down when main loop indicates that more work is\n  ready and would be allowed to start if a token becomes available\n- posix: update DoWork() to monitor TokenPool read file descriptor\n- WaitForCommand() exits when DoWork() sets token flag\n- Main loop starts over when WaitForCommand() sets token exit status\n\nIgnore jobserver when -jN is forced on command line\n\nThis emulates the behaviour of GNU make.\n\n- add parallelism_from_cmdline flag to build configuration\n- set the flag when -jN is given on command line\n- pass the flag to TokenPool::Get()\n- GNUmakeTokenPool::Setup()\n  * prints a warning when the flag is true and jobserver was detected\n  * returns false, i.e. jobserver will be ignored\n- ignore config.parallelism in CanRunMore() when we have a valid\n  TokenPool, because it gets always initialized to a default when not\n  given on the command line\n\nHonor -lN from MAKEFLAGS\n\nThis emulates the behaviour of GNU make.\n\n- build: make a copy of max_load_average and pass it to TokenPool.\n- GNUmakeTokenPool: if we detect a jobserver and a valid -lN argument in\n  MAKEFLAGS then set max_load_average to N.\n\nUse LinePrinter for TokenPool messages\n\n- replace printf() with calls to LinePrinter\n- print GNU make jobserver message only when verbose build is requested\n\nPrepare PR for merging\n\n- fix Windows build error in no-op TokenPool implementation\n- improve Acquire() to block for a maximum of 100ms\n- address review comments\n\nAdd tests for TokenPool\n\n- TokenPool setup\n- GetMonitorFd() API\n- implicit token and tokens in jobserver pipe\n- Acquire() / Reserve() / Release() protocol\n- Clear() API\n\nAdd tests for subprocess module\n\n- add TokenPoolTest stub to provide TokenPool::GetMonitorFd()\n- add two tests\n  * both tests set up a dummy GNUmake jobserver pipe\n  * both tests call DoWork() with TokenPoolTest\n  * test 1: verify that DoWork() detects when a token is available\n  * test 2: verify that DoWork() works as before without a token\n- the tests are not compiled in under Windows\n\nAdd tests for build module\n\nAdd tests that verify the token functionality of the builder main loop.\nWe replace the default fake command runner with a special version where\nthe tests can control each call to AcquireToken(), CanRunMore() and\nWaitForCommand().\n\nAdd Win32 implementation for GNUmakeTokenPool\n\nGNU make uses a semaphore as jobserver protocol on Win32. See also\n\n   https://www.gnu.org/software/make/manual/html_node/Windows-Jobserver.html\n\nUsage is pretty simple and straightforward, i.e. WaitForSingleObject()\nto obtain a token and ReleaseSemaphore() to return it.\n\nUnfortunately subprocess-win32.cc uses an I/O completion port (IOCP).\nIOCPs aren't waitable objects, i.e. we can't use WaitForMultipleObjects()\nto wait on the IOCP and the token semaphore at the same time.\n\nTherefore GNUmakeTokenPoolWin32 creates a child thread that waits on the\ntoken semaphore and posts a dummy I/O completion status on the IOCP when\nit was able to obtain a token. That unblocks SubprocessSet::DoWork() and\nit can then check if a token became available or not.\n\n- split existing GNUmakeTokenPool into common and platform bits\n- add GNUmakeTokenPool interface\n- move the Posix bits to GNUmakeTokenPoolPosix\n- add the Win32 bits as GNUmakeTokenPoolWin32\n- move Setup() method up to TokenPool interface\n- update Subprocess & TokenPool tests accordingly\n\nPrepare PR for merging - part II\n\n- remove unnecessary \"struct\" from TokenPool\n- add PAPCFUNC cast to QueryUserAPC()\n- remove hard-coded MAKEFLAGS string from win32\n- remove useless build test CompleteNoWork\n- rename TokenPoolTest to TestTokenPool\n- add tokenpool modules to CMake build\n- remove unused no-op TokenPool implementation\n- address review comments from\n\nhttps://github.com/ninja-build/ninja/pull/1140#pullrequestreview-195195803\nhttps://github.com/ninja-build/ninja/pull/1140#pullrequestreview-185089255\nhttps://github.com/ninja-build/ninja/pull/1140#issuecomment-473898963\nhttps://github.com/ninja-build/ninja/pull/1140#issuecomment-596624610\n---\n CMakeLists.txt                  |   8 +-\n configure.py                    |   7 +-\n src/build.cc                    | 127 ++++++++---\n src/build.h                     |  12 +-\n src/build_test.cc               | 363 +++++++++++++++++++++++++++++++-\n src/exit_status.h               |   3 +-\n src/ninja.cc                    |   1 +\n src/subprocess-posix.cc         |  33 ++-\n src/subprocess-win32.cc         |  11 +-\n src/subprocess.h                |   8 +-\n src/subprocess_test.cc          | 149 +++++++++++--\n src/tokenpool-gnu-make-posix.cc | 202 ++++++++++++++++++\n src/tokenpool-gnu-make-win32.cc | 239 +++++++++++++++++++++\n src/tokenpool-gnu-make.cc       | 108 ++++++++++\n src/tokenpool-gnu-make.h        |  40 ++++\n src/tokenpool.h                 |  42 ++++\n src/tokenpool_test.cc           | 269 +++++++++++++++++++++++\n 17 files changed, 1562 insertions(+), 60 deletions(-)\n create mode 100644 src/tokenpool-gnu-make-posix.cc\n create mode 100644 src/tokenpool-gnu-make-win32.cc\n create mode 100644 src/tokenpool-gnu-make.cc\n create mode 100644 src/tokenpool-gnu-make.h\n create mode 100644 src/tokenpool.h\n create mode 100644 src/tokenpool_test.cc\n\n--- a/CMakeLists.txt\n+++ b/CMakeLists.txt\n@@ -94,6 +94,7 @@ add_library(libninja OBJECT\n \tsrc/parser.cc\n \tsrc/state.cc\n \tsrc/string_piece_util.cc\n+\tsrc/tokenpool-gnu-make.cc\n \tsrc/util.cc\n \tsrc/version.cc\n )\n@@ -104,12 +105,16 @@ if(WIN32)\n \t\tsrc/msvc_helper-win32.cc\n \t\tsrc/msvc_helper_main-win32.cc\n \t\tsrc/getopt.c\n+\t\tsrc/tokenpool-gnu-make-win32.cc\n \t)\n \tif(MSVC)\n \t\ttarget_sources(libninja PRIVATE src/minidump-win32.cc)\n \tendif()\n else()\n-\ttarget_sources(libninja PRIVATE src/subprocess-posix.cc)\n+\ttarget_sources(libninja PRIVATE\n+\t\tsrc/subprocess-posix.cc\n+\t\tsrc/tokenpool-gnu-make-posix.cc\n+\t)\n \tif(CMAKE_SYSTEM_NAME STREQUAL \"OS400\" OR CMAKE_SYSTEM_NAME STREQUAL \"AIX\")\n \t\ttarget_sources(libninja PRIVATE src/getopt.c)\n \tendif()\n@@ -182,6 +187,7 @@ if(BUILD_TESTING)\n     src/string_piece_util_test.cc\n     src/subprocess_test.cc\n     src/test.cc\n+    src/tokenpool_test.cc\n     src/util_test.cc\n   )\n   if(WIN32)\n--- a/configure.py\n+++ b/configure.py\n@@ -514,11 +514,13 @@ for name in ['build',\n              'parser',\n              'state',\n              'string_piece_util',\n+             'tokenpool-gnu-make',\n              'util',\n              'version']:\n     objs += cxx(name, variables=cxxvariables)\n if platform.is_windows():\n     for name in ['subprocess-win32',\n+                 'tokenpool-gnu-make-win32',\n                  'includes_normalize-win32',\n                  'msvc_helper-win32',\n                  'msvc_helper_main-win32']:\n@@ -527,7 +529,9 @@ if platform.is_windows():\n         objs += cxx('minidump-win32', variables=cxxvariables)\n     objs += cc('getopt')\n else:\n-    objs += cxx('subprocess-posix')\n+    for name in ['subprocess-posix',\n+                 'tokenpool-gnu-make-posix']:\n+        objs += cxx(name)\n if platform.is_aix():\n     objs += cc('getopt')\n if platform.is_msvc():\n@@ -582,6 +586,7 @@ for name in ['build_log_test',\n              'string_piece_util_test',\n              'subprocess_test',\n              'test',\n+             'tokenpool_test',\n              'util_test']:\n     objs += cxx(name, variables=cxxvariables)\n if platform.is_windows():\n--- a/src/build.cc\n+++ b/src/build.cc\n@@ -38,6 +38,7 @@\n #include \"graph.h\"\n #include \"state.h\"\n #include \"subprocess.h\"\n+#include \"tokenpool.h\"\n #include \"util.h\"\n \n using namespace std;\n@@ -50,8 +51,9 @@ struct DryRunCommandRunner : public Comm\n \n   // Overridden from CommandRunner:\n   virtual bool CanRunMore() const;\n+  virtual bool AcquireToken();\n   virtual bool StartCommand(Edge* edge);\n-  virtual bool WaitForCommand(Result* result);\n+  virtual bool WaitForCommand(Result* result, bool more_ready);\n \n  private:\n   queue<Edge*> finished_;\n@@ -61,12 +63,16 @@ bool DryRunCommandRunner::CanRunMore() c\n   return true;\n }\n \n+bool DryRunCommandRunner::AcquireToken() {\n+  return true;\n+}\n+\n bool DryRunCommandRunner::StartCommand(Edge* edge) {\n   finished_.push(edge);\n   return true;\n }\n \n-bool DryRunCommandRunner::WaitForCommand(Result* result) {\n+bool DryRunCommandRunner::WaitForCommand(Result* result, bool more_ready) {\n    if (finished_.empty())\n      return false;\n \n@@ -379,7 +385,7 @@ void Plan::EdgeWanted(const Edge* edge)\n }\n \n Edge* Plan::FindWork() {\n-  if (ready_.empty())\n+  if (!more_ready())\n     return NULL;\n   set<Edge*>::iterator e = ready_.begin();\n   Edge* edge = *e;\n@@ -665,19 +671,39 @@ void Plan::Dump() const {\n }\n \n struct RealCommandRunner : public CommandRunner {\n-  explicit RealCommandRunner(const BuildConfig& config) : config_(config) {}\n-  virtual ~RealCommandRunner() {}\n+  explicit RealCommandRunner(const BuildConfig& config);\n+  virtual ~RealCommandRunner();\n   virtual bool CanRunMore() const;\n+  virtual bool AcquireToken();\n   virtual bool StartCommand(Edge* edge);\n-  virtual bool WaitForCommand(Result* result);\n+  virtual bool WaitForCommand(Result* result, bool more_ready);\n   virtual vector<Edge*> GetActiveEdges();\n   virtual void Abort();\n \n   const BuildConfig& config_;\n+  // copy of config_.max_load_average; can be modified by TokenPool setup\n+  double max_load_average_;\n   SubprocessSet subprocs_;\n+  TokenPool* tokens_;\n   map<const Subprocess*, Edge*> subproc_to_edge_;\n };\n \n+RealCommandRunner::RealCommandRunner(const BuildConfig& config) : config_(config) {\n+  max_load_average_ = config.max_load_average;\n+  if ((tokens_ = TokenPool::Get()) != NULL) {\n+    if (!tokens_->Setup(config_.parallelism_from_cmdline,\n+                        config_.verbosity == BuildConfig::VERBOSE,\n+                        max_load_average_)) {\n+      delete tokens_;\n+      tokens_ = NULL;\n+    }\n+  }\n+}\n+\n+RealCommandRunner::~RealCommandRunner() {\n+  delete tokens_;\n+}\n+\n vector<Edge*> RealCommandRunner::GetActiveEdges() {\n   vector<Edge*> edges;\n   for (map<const Subprocess*, Edge*>::iterator e = subproc_to_edge_.begin();\n@@ -688,14 +714,23 @@ vector<Edge*> RealCommandRunner::GetActi\n \n void RealCommandRunner::Abort() {\n   subprocs_.Clear();\n+  if (tokens_)\n+    tokens_->Clear();\n }\n \n bool RealCommandRunner::CanRunMore() const {\n-  size_t subproc_number =\n-      subprocs_.running_.size() + subprocs_.finished_.size();\n-  return (int)subproc_number < config_.parallelism\n-    && ((subprocs_.running_.empty() || config_.max_load_average <= 0.0f)\n-        || GetLoadAverage() < config_.max_load_average);\n+  bool parallelism_limit_not_reached =\n+    tokens_ || // ignore config_.parallelism\n+    ((int) (subprocs_.running_.size() +\n+            subprocs_.finished_.size()) < config_.parallelism);\n+  return parallelism_limit_not_reached\n+    && (subprocs_.running_.empty() ||\n+        (max_load_average_ <= 0.0f ||\n+         GetLoadAverage() < max_load_average_));\n+}\n+\n+bool RealCommandRunner::AcquireToken() {\n+  return (!tokens_ || tokens_->Acquire());\n }\n \n bool RealCommandRunner::StartCommand(Edge* edge) {\n@@ -703,19 +738,33 @@ bool RealCommandRunner::StartCommand(Edg\n   Subprocess* subproc = subprocs_.Add(command, edge->use_console());\n   if (!subproc)\n     return false;\n+  if (tokens_)\n+    tokens_->Reserve();\n   subproc_to_edge_.insert(make_pair(subproc, edge));\n \n   return true;\n }\n \n-bool RealCommandRunner::WaitForCommand(Result* result) {\n+bool RealCommandRunner::WaitForCommand(Result* result, bool more_ready) {\n   Subprocess* subproc;\n-  while ((subproc = subprocs_.NextFinished()) == NULL) {\n-    bool interrupted = subprocs_.DoWork();\n+  subprocs_.ResetTokenAvailable();\n+  while (((subproc = subprocs_.NextFinished()) == NULL) &&\n+         !subprocs_.IsTokenAvailable()) {\n+    bool interrupted = subprocs_.DoWork(more_ready ? tokens_ : NULL);\n     if (interrupted)\n       return false;\n   }\n \n+  // token became available\n+  if (subproc == NULL) {\n+    result->status = ExitTokenAvailable;\n+    return true;\n+  }\n+\n+  // command completed\n+  if (tokens_)\n+    tokens_->Release();\n+\n   result->status = subproc->Finish();\n   result->output = subproc->GetOutput();\n \n@@ -825,38 +874,42 @@ bool Builder::Build(string* err) {\n   // command runner.\n   // Second, we attempt to wait for / reap the next finished command.\n   while (plan_.more_to_do()) {\n-    // See if we can start any more commands.\n-    if (failures_allowed && command_runner_->CanRunMore()) {\n-      if (Edge* edge = plan_.FindWork()) {\n-        if (edge->GetBindingBool(\"generator\")) {\n-          scan_.build_log()->Close();\n-        }\n+    // See if we can start any more commands...\n+    bool can_run_more =\n+        failures_allowed   &&\n+        plan_.more_ready() &&\n+        command_runner_->CanRunMore();\n+\n+    // ... but we also need a token to do that.\n+    if (can_run_more && command_runner_->AcquireToken()) {\n+      Edge* edge = plan_.FindWork();\n+      if (edge->GetBindingBool(\"generator\")) {\n+        scan_.build_log()->Close();\n+      }\n+      if (!StartEdge(edge, err)) {\n+        Cleanup();\n+        status_->BuildFinished();\n+        return false;\n+      }\n \n-        if (!StartEdge(edge, err)) {\n+      if (edge->is_phony()) {\n+        if (!plan_.EdgeFinished(edge, Plan::kEdgeSucceeded, err)) {\n           Cleanup();\n           status_->BuildFinished();\n           return false;\n         }\n-\n-        if (edge->is_phony()) {\n-          if (!plan_.EdgeFinished(edge, Plan::kEdgeSucceeded, err)) {\n-            Cleanup();\n-            status_->BuildFinished();\n-            return false;\n-          }\n-        } else {\n-          ++pending_commands;\n-        }\n-\n-        // We made some progress; go back to the main loop.\n-        continue;\n+      } else {\n+        ++pending_commands;\n       }\n+\n+      // We made some progress; go back to the main loop.\n+      continue;\n     }\n \n     // See if we can reap any finished commands.\n     if (pending_commands) {\n       CommandRunner::Result result;\n-      if (!command_runner_->WaitForCommand(&result) ||\n+      if (!command_runner_->WaitForCommand(&result, can_run_more) ||\n           result.status == ExitInterrupted) {\n         Cleanup();\n         status_->BuildFinished();\n@@ -864,6 +917,10 @@ bool Builder::Build(string* err) {\n         return false;\n       }\n \n+      // We might be able to start another command; start the main loop over.\n+      if (result.status == ExitTokenAvailable)\n+        continue;\n+\n       --pending_commands;\n       if (!FinishCommand(&result, err)) {\n         Cleanup();\n--- a/src/build.h\n+++ b/src/build.h\n@@ -55,6 +55,9 @@ struct Plan {\n   /// Returns true if there's more work to be done.\n   bool more_to_do() const { return wanted_edges_ > 0 && command_edges_ > 0; }\n \n+  /// Returns true if there's more edges ready to start\n+  bool more_ready() const { return !ready_.empty(); }\n+\n   /// Dumps the current state of the plan.\n   void Dump() const;\n \n@@ -139,6 +142,7 @@ private:\n struct CommandRunner {\n   virtual ~CommandRunner() {}\n   virtual bool CanRunMore() const = 0;\n+  virtual bool AcquireToken() = 0;\n   virtual bool StartCommand(Edge* edge) = 0;\n \n   /// The result of waiting for a command.\n@@ -150,7 +154,9 @@ struct CommandRunner {\n     bool success() const { return status == ExitSuccess; }\n   };\n   /// Wait for a command to complete, or return false if interrupted.\n-  virtual bool WaitForCommand(Result* result) = 0;\n+  /// If more_ready is true then the optional TokenPool is monitored too\n+  /// and we return when a token becomes available.\n+  virtual bool WaitForCommand(Result* result, bool more_ready) = 0;\n \n   virtual std::vector<Edge*> GetActiveEdges() { return std::vector<Edge*>(); }\n   virtual void Abort() {}\n@@ -158,7 +164,8 @@ struct CommandRunner {\n \n /// Options (e.g. verbosity, parallelism) passed to a build.\n struct BuildConfig {\n-  BuildConfig() : verbosity(NORMAL), dry_run(false), parallelism(1),\n+  BuildConfig() : verbosity(NORMAL), dry_run(false),\n+                  parallelism(1), parallelism_from_cmdline(false),\n                   failures_allowed(1), max_load_average(-0.0f) {}\n \n   enum Verbosity {\n@@ -169,6 +176,7 @@ struct BuildConfig {\n   Verbosity verbosity;\n   bool dry_run;\n   int parallelism;\n+  bool parallelism_from_cmdline;\n   int failures_allowed;\n   /// The maximum load average we must not exceed. A negative value\n   /// means that we do not have any limit.\n--- a/src/build_test.cc\n+++ b/src/build_test.cc\n@@ -15,6 +15,7 @@\n #include \"build.h\"\n \n #include <assert.h>\n+#include <stdarg.h>\n \n #include \"build_log.h\"\n #include \"deps_log.h\"\n@@ -473,8 +474,9 @@ struct FakeCommandRunner : public Comman\n \n   // CommandRunner impl\n   virtual bool CanRunMore() const;\n+  virtual bool AcquireToken();\n   virtual bool StartCommand(Edge* edge);\n-  virtual bool WaitForCommand(Result* result);\n+  virtual bool WaitForCommand(Result* result, bool more_ready);\n   virtual vector<Edge*> GetActiveEdges();\n   virtual void Abort();\n \n@@ -580,6 +582,10 @@ bool FakeCommandRunner::CanRunMore() con\n   return active_edges_.size() < max_active_edges_;\n }\n \n+bool FakeCommandRunner::AcquireToken() {\n+  return true;\n+}\n+\n bool FakeCommandRunner::StartCommand(Edge* edge) {\n   assert(active_edges_.size() < max_active_edges_);\n   assert(find(active_edges_.begin(), active_edges_.end(), edge)\n@@ -625,7 +631,7 @@ bool FakeCommandRunner::StartCommand(Edg\n   return true;\n }\n \n-bool FakeCommandRunner::WaitForCommand(Result* result) {\n+bool FakeCommandRunner::WaitForCommand(Result* result, bool more_ready) {\n   if (active_edges_.empty())\n     return false;\n \n@@ -3302,3 +3308,356 @@ TEST_F(BuildTest, DyndepTwoLevelDiscover\n   EXPECT_EQ(\"touch tmp\", command_runner_.commands_ran_[3]);\n   EXPECT_EQ(\"touch out\", command_runner_.commands_ran_[4]);\n }\n+\n+/// The token tests are concerned with the main loop functionality when\n+// the CommandRunner has an active TokenPool. It is therefore intentional\n+// that the plan doesn't complete and that builder_.Build() returns false!\n+\n+/// Fake implementation of CommandRunner that simulates a TokenPool\n+struct FakeTokenCommandRunner : public CommandRunner {\n+  explicit FakeTokenCommandRunner() {}\n+\n+  // CommandRunner impl\n+  virtual bool CanRunMore() const;\n+  virtual bool AcquireToken();\n+  virtual bool StartCommand(Edge* edge);\n+  virtual bool WaitForCommand(Result* result, bool more_ready);\n+  virtual vector<Edge*> GetActiveEdges();\n+  virtual void Abort();\n+\n+  vector<string> commands_ran_;\n+  vector<Edge *> edges_;\n+\n+  vector<bool> acquire_token_;\n+  vector<bool> can_run_more_;\n+  vector<bool> wait_for_command_;\n+};\n+\n+bool FakeTokenCommandRunner::CanRunMore() const {\n+  if (can_run_more_.size() == 0) {\n+    EXPECT_FALSE(\"unexpected call to CommandRunner::CanRunMore()\");\n+    return false;\n+  }\n+\n+  bool result = can_run_more_[0];\n+\n+  // Unfortunately CanRunMore() isn't \"const\" for tests\n+  const_cast<FakeTokenCommandRunner*>(this)->can_run_more_.erase(\n+    const_cast<FakeTokenCommandRunner*>(this)->can_run_more_.begin()\n+  );\n+\n+  return result;\n+}\n+\n+bool FakeTokenCommandRunner::AcquireToken() {\n+  if (acquire_token_.size() == 0) {\n+    EXPECT_FALSE(\"unexpected call to CommandRunner::AcquireToken()\");\n+    return false;\n+  }\n+\n+  bool result = acquire_token_[0];\n+  acquire_token_.erase(acquire_token_.begin());\n+  return result;\n+}\n+\n+bool FakeTokenCommandRunner::StartCommand(Edge* edge) {\n+  commands_ran_.push_back(edge->EvaluateCommand());\n+  edges_.push_back(edge);\n+  return true;\n+}\n+\n+bool FakeTokenCommandRunner::WaitForCommand(Result* result, bool more_ready) {\n+  if (wait_for_command_.size() == 0) {\n+    EXPECT_FALSE(\"unexpected call to CommandRunner::WaitForCommand()\");\n+    return false;\n+  }\n+\n+  bool expected = wait_for_command_[0];\n+  if (expected != more_ready) {\n+    EXPECT_EQ(expected, more_ready);\n+    return false;\n+  }\n+  wait_for_command_.erase(wait_for_command_.begin());\n+\n+  if (edges_.size() == 0)\n+    return false;\n+\n+  Edge* edge = edges_[0];\n+  result->edge = edge;\n+\n+  if (more_ready &&\n+      (edge->rule().name() == \"token-available\")) {\n+    result->status = ExitTokenAvailable;\n+  } else {\n+    edges_.erase(edges_.begin());\n+    result->status = ExitSuccess;\n+  }\n+\n+  return true;\n+}\n+\n+vector<Edge*> FakeTokenCommandRunner::GetActiveEdges() {\n+  return edges_;\n+}\n+\n+void FakeTokenCommandRunner::Abort() {\n+  edges_.clear();\n+}\n+\n+struct BuildTokenTest : public BuildTest {\n+  virtual void SetUp();\n+  virtual void TearDown();\n+\n+  FakeTokenCommandRunner token_command_runner_;\n+\n+  void ExpectAcquireToken(int count, ...);\n+  void ExpectCanRunMore(int count, ...);\n+  void ExpectWaitForCommand(int count, ...);\n+\n+private:\n+  void EnqueueBooleans(vector<bool>& booleans, int count, va_list ao);\n+};\n+\n+void BuildTokenTest::SetUp() {\n+  BuildTest::SetUp();\n+\n+  // replace FakeCommandRunner with FakeTokenCommandRunner\n+  builder_.command_runner_.release();\n+  builder_.command_runner_.reset(&token_command_runner_);\n+}\n+void BuildTokenTest::TearDown() {\n+  EXPECT_EQ(0u, token_command_runner_.acquire_token_.size());\n+  EXPECT_EQ(0u, token_command_runner_.can_run_more_.size());\n+  EXPECT_EQ(0u, token_command_runner_.wait_for_command_.size());\n+\n+  BuildTest::TearDown();\n+}\n+\n+void BuildTokenTest::ExpectAcquireToken(int count, ...) {\n+  va_list ap;\n+  va_start(ap, count);\n+  EnqueueBooleans(token_command_runner_.acquire_token_, count, ap);\n+  va_end(ap);\n+}\n+\n+void BuildTokenTest::ExpectCanRunMore(int count, ...) {\n+  va_list ap;\n+  va_start(ap, count);\n+  EnqueueBooleans(token_command_runner_.can_run_more_, count, ap);\n+  va_end(ap);\n+}\n+\n+void BuildTokenTest::ExpectWaitForCommand(int count, ...) {\n+  va_list ap;\n+  va_start(ap, count);\n+  EnqueueBooleans(token_command_runner_.wait_for_command_, count, ap);\n+  va_end(ap);\n+}\n+\n+void BuildTokenTest::EnqueueBooleans(vector<bool>& booleans, int count, va_list ap) {\n+  while (count--) {\n+    int value = va_arg(ap, int);\n+    booleans.push_back(!!value); // force bool\n+  }\n+}\n+\n+TEST_F(BuildTokenTest, DoNotAquireToken) {\n+  // plan should execute one command\n+  string err;\n+  EXPECT_TRUE(builder_.AddTarget(\"cat1\", &err));\n+  ASSERT_EQ(\"\", err);\n+\n+  // pretend we can't run anything\n+  ExpectCanRunMore(1, false);\n+\n+  EXPECT_FALSE(builder_.Build(&err));\n+  EXPECT_EQ(\"stuck [this is a bug]\", err);\n+\n+  EXPECT_EQ(0u, token_command_runner_.commands_ran_.size());\n+}\n+\n+TEST_F(BuildTokenTest, DoNotStartWithoutToken) {\n+  // plan should execute one command\n+  string err;\n+  EXPECT_TRUE(builder_.AddTarget(\"cat1\", &err));\n+  ASSERT_EQ(\"\", err);\n+\n+  // we could run a command but do not have a token for it\n+  ExpectCanRunMore(1,   true);\n+  ExpectAcquireToken(1, false);\n+\n+  EXPECT_FALSE(builder_.Build(&err));\n+  EXPECT_EQ(\"stuck [this is a bug]\", err);\n+\n+  EXPECT_EQ(0u, token_command_runner_.commands_ran_.size());\n+}\n+\n+TEST_F(BuildTokenTest, CompleteOneStep) {\n+  // plan should execute one command\n+  string err;\n+  EXPECT_TRUE(builder_.AddTarget(\"cat1\", &err));\n+  ASSERT_EQ(\"\", err);\n+\n+  // allow running of one command\n+  ExpectCanRunMore(1,   true);\n+  ExpectAcquireToken(1, true);\n+  // block and wait for command to finalize\n+  ExpectWaitForCommand(1, false);\n+\n+  EXPECT_TRUE(builder_.Build(&err));\n+  EXPECT_EQ(\"\", err);\n+\n+  EXPECT_EQ(1u, token_command_runner_.commands_ran_.size());\n+  EXPECT_TRUE(token_command_runner_.commands_ran_[0] == \"cat in1 > cat1\");\n+}\n+\n+TEST_F(BuildTokenTest, AcquireOneToken) {\n+  // plan should execute more than one command\n+  string err;\n+  EXPECT_TRUE(builder_.AddTarget(\"cat12\", &err));\n+  ASSERT_EQ(\"\", err);\n+\n+  // allow running of one command\n+  ExpectCanRunMore(3,     true, false, false);\n+  ExpectAcquireToken(1,   true);\n+  // block and wait for command to finalize\n+  ExpectWaitForCommand(1, false);\n+\n+  EXPECT_FALSE(builder_.Build(&err));\n+  EXPECT_EQ(\"stuck [this is a bug]\", err);\n+\n+  EXPECT_EQ(1u, token_command_runner_.commands_ran_.size());\n+  // any of the two dependencies could have been executed\n+  EXPECT_TRUE(token_command_runner_.commands_ran_[0] == \"cat in1 > cat1\" ||\n+              token_command_runner_.commands_ran_[0] == \"cat in1 in2 > cat2\");\n+}\n+\n+TEST_F(BuildTokenTest, WantTwoTokens) {\n+  // plan should execute more than one command\n+  string err;\n+  EXPECT_TRUE(builder_.AddTarget(\"cat12\", &err));\n+  ASSERT_EQ(\"\", err);\n+\n+  // allow running of one command\n+  ExpectCanRunMore(3,     true, true, false);\n+  ExpectAcquireToken(2,   true, false);\n+  // wait for command to finalize or token to become available\n+  ExpectWaitForCommand(1, true);\n+\n+  EXPECT_FALSE(builder_.Build(&err));\n+  EXPECT_EQ(\"stuck [this is a bug]\", err);\n+\n+  EXPECT_EQ(1u, token_command_runner_.commands_ran_.size());\n+  // any of the two dependencies could have been executed\n+  EXPECT_TRUE(token_command_runner_.commands_ran_[0] == \"cat in1 > cat1\" ||\n+              token_command_runner_.commands_ran_[0] == \"cat in1 in2 > cat2\");\n+}\n+\n+TEST_F(BuildTokenTest, CompleteTwoSteps) {\n+  ASSERT_NO_FATAL_FAILURE(AssertParse(&state_,\n+\"build out1: cat in1\\n\"\n+\"build out2: cat out1\\n\"));\n+\n+  // plan should execute more than one command\n+  string err;\n+  EXPECT_TRUE(builder_.AddTarget(\"out2\", &err));\n+  ASSERT_EQ(\"\", err);\n+\n+  // allow running of two commands\n+  ExpectCanRunMore(2,     true, true);\n+  ExpectAcquireToken(2,   true, true);\n+  // wait for commands to finalize\n+  ExpectWaitForCommand(2, false, false);\n+\n+  EXPECT_TRUE(builder_.Build(&err));\n+  EXPECT_EQ(\"\", err);\n+\n+  EXPECT_EQ(2u, token_command_runner_.commands_ran_.size());\n+  EXPECT_TRUE(token_command_runner_.commands_ran_[0] == \"cat in1 > out1\");\n+  EXPECT_TRUE(token_command_runner_.commands_ran_[1] == \"cat out1 > out2\");\n+}\n+\n+TEST_F(BuildTokenTest, TwoCommandsInParallel) {\n+  ASSERT_NO_FATAL_FAILURE(AssertParse(&state_,\n+\"rule token-available\\n\"\n+\"  command = cat $in > $out\\n\"\n+\"build out1: token-available in1\\n\"\n+\"build out2: token-available in2\\n\"\n+\"build out12: cat out1 out2\\n\"));\n+\n+  // plan should execute more than one command\n+  string err;\n+  EXPECT_TRUE(builder_.AddTarget(\"out12\", &err));\n+  ASSERT_EQ(\"\", err);\n+\n+  // 1st command: token available -> allow running\n+  // 2nd command: no token available but becomes available later\n+  ExpectCanRunMore(4,     true, true,  true,  false);\n+  ExpectAcquireToken(3,   true, false, true);\n+  // 1st call waits for command to finalize or token to become available\n+  // 2nd call waits for command to finalize\n+  // 3rd call waits for command to finalize\n+  ExpectWaitForCommand(3, true, false, false);\n+\n+  EXPECT_FALSE(builder_.Build(&err));\n+  EXPECT_EQ(\"stuck [this is a bug]\", err);\n+\n+  EXPECT_EQ(2u, token_command_runner_.commands_ran_.size());\n+  EXPECT_TRUE((token_command_runner_.commands_ran_[0] == \"cat in1 > out1\" &&\n+               token_command_runner_.commands_ran_[1] == \"cat in2 > out2\") ||\n+              (token_command_runner_.commands_ran_[0] == \"cat in2 > out2\" &&\n+               token_command_runner_.commands_ran_[1] == \"cat in1 > out1\"));\n+}\n+\n+TEST_F(BuildTokenTest, CompleteThreeStepsSerial) {\n+  // plan should execute more than one command\n+  string err;\n+  EXPECT_TRUE(builder_.AddTarget(\"cat12\", &err));\n+  ASSERT_EQ(\"\", err);\n+\n+  // allow running of all commands\n+  ExpectCanRunMore(4,     true, true,  true,  true);\n+  ExpectAcquireToken(4,   true, false, true,  true);\n+  // wait for commands to finalize\n+  ExpectWaitForCommand(3, true, false, false);\n+\n+  EXPECT_TRUE(builder_.Build(&err));\n+  EXPECT_EQ(\"\", err);\n+\n+  EXPECT_EQ(3u, token_command_runner_.commands_ran_.size());\n+  EXPECT_TRUE((token_command_runner_.commands_ran_[0] == \"cat in1 > cat1\"     &&\n+               token_command_runner_.commands_ran_[1] == \"cat in1 in2 > cat2\") ||\n+              (token_command_runner_.commands_ran_[0] == \"cat in1 in2 > cat2\" &&\n+               token_command_runner_.commands_ran_[1] == \"cat in1 > cat1\"    ));\n+  EXPECT_TRUE(token_command_runner_.commands_ran_[2] == \"cat cat1 cat2 > cat12\");\n+}\n+\n+TEST_F(BuildTokenTest, CompleteThreeStepsParallel) {\n+  ASSERT_NO_FATAL_FAILURE(AssertParse(&state_,\n+\"rule token-available\\n\"\n+\"  command = cat $in > $out\\n\"\n+\"build out1: token-available in1\\n\"\n+\"build out2: token-available in2\\n\"\n+\"build out12: cat out1 out2\\n\"));\n+\n+  // plan should execute more than one command\n+  string err;\n+  EXPECT_TRUE(builder_.AddTarget(\"out12\", &err));\n+  ASSERT_EQ(\"\", err);\n+\n+  // allow running of all commands\n+  ExpectCanRunMore(4,     true, true,  true,  true);\n+  ExpectAcquireToken(4,   true, false, true,  true);\n+  // wait for commands to finalize\n+  ExpectWaitForCommand(4, true, false, false, false);\n+\n+  EXPECT_TRUE(builder_.Build(&err));\n+  EXPECT_EQ(\"\", err);\n+\n+  EXPECT_EQ(3u, token_command_runner_.commands_ran_.size());\n+  EXPECT_TRUE((token_command_runner_.commands_ran_[0] == \"cat in1 > out1\" &&\n+               token_command_runner_.commands_ran_[1] == \"cat in2 > out2\") ||\n+              (token_command_runner_.commands_ran_[0] == \"cat in2 > out2\" &&\n+               token_command_runner_.commands_ran_[1] == \"cat in1 > out1\"));\n+  EXPECT_TRUE(token_command_runner_.commands_ran_[2] == \"cat out1 out2 > out12\");\n+}\n--- a/src/exit_status.h\n+++ b/src/exit_status.h\n@@ -18,7 +18,8 @@\n enum ExitStatus {\n   ExitSuccess,\n   ExitFailure,\n-  ExitInterrupted\n+  ExitTokenAvailable,\n+  ExitInterrupted,\n };\n \n #endif  // NINJA_EXIT_STATUS_H_\n--- a/src/ninja.cc\n+++ b/src/ninja.cc\n@@ -1289,6 +1289,7 @@ int ReadFlags(int* argc, char*** argv,\n         // We want to run N jobs in parallel. For N = 0, INT_MAX\n         // is close enough to infinite for most sane builds.\n         config->parallelism = value > 0 ? value : INT_MAX;\n+        config->parallelism_from_cmdline = true;\n         break;\n       }\n       case 'k': {\n--- a/src/subprocess-posix.cc\n+++ b/src/subprocess-posix.cc\n@@ -13,6 +13,7 @@\n // limitations under the License.\n \n #include \"subprocess.h\"\n+#include \"tokenpool.h\"\n \n #include <sys/select.h>\n #include <assert.h>\n@@ -249,7 +250,7 @@ Subprocess *SubprocessSet::Add(const str\n }\n \n #ifdef USE_PPOLL\n-bool SubprocessSet::DoWork() {\n+bool SubprocessSet::DoWork(TokenPool* tokens) {\n   vector<pollfd> fds;\n   nfds_t nfds = 0;\n \n@@ -263,6 +264,12 @@ bool SubprocessSet::DoWork() {\n     ++nfds;\n   }\n \n+  if (tokens) {\n+    pollfd pfd = { tokens->GetMonitorFd(), POLLIN | POLLPRI, 0 };\n+    fds.push_back(pfd);\n+    ++nfds;\n+  }\n+\n   interrupted_ = 0;\n   int ret = ppoll(&fds.front(), nfds, NULL, &old_mask_);\n   if (ret == -1) {\n@@ -295,11 +302,20 @@ bool SubprocessSet::DoWork() {\n     ++i;\n   }\n \n+  if (tokens) {\n+    pollfd *pfd = &fds[nfds - 1];\n+    if (pfd->fd >= 0) {\n+      assert(pfd->fd == tokens->GetMonitorFd());\n+      if (pfd->revents != 0)\n+        token_available_ = true;\n+    }\n+  }\n+\n   return IsInterrupted();\n }\n \n #else  // !defined(USE_PPOLL)\n-bool SubprocessSet::DoWork() {\n+bool SubprocessSet::DoWork(TokenPool* tokens) {\n   fd_set set;\n   int nfds = 0;\n   FD_ZERO(&set);\n@@ -314,6 +330,13 @@ bool SubprocessSet::DoWork() {\n     }\n   }\n \n+  if (tokens) {\n+    int fd = tokens->GetMonitorFd();\n+    FD_SET(fd, &set);\n+    if (nfds < fd+1)\n+      nfds = fd+1;\n+  }\n+\n   interrupted_ = 0;\n   int ret = pselect(nfds, &set, 0, 0, 0, &old_mask_);\n   if (ret == -1) {\n@@ -342,6 +365,12 @@ bool SubprocessSet::DoWork() {\n     ++i;\n   }\n \n+  if (tokens) {\n+    int fd = tokens->GetMonitorFd();\n+    if ((fd >= 0) && FD_ISSET(fd, &set))\n+    token_available_ = true;\n+  }\n+\n   return IsInterrupted();\n }\n #endif  // !defined(USE_PPOLL)\n--- a/src/subprocess-win32.cc\n+++ b/src/subprocess-win32.cc\n@@ -13,6 +13,7 @@\n // limitations under the License.\n \n #include \"subprocess.h\"\n+#include \"tokenpool.h\"\n \n #include <assert.h>\n #include <stdio.h>\n@@ -251,11 +252,14 @@ Subprocess *SubprocessSet::Add(const str\n   return subprocess;\n }\n \n-bool SubprocessSet::DoWork() {\n+bool SubprocessSet::DoWork(TokenPool* tokens) {\n   DWORD bytes_read;\n   Subprocess* subproc;\n   OVERLAPPED* overlapped;\n \n+  if (tokens)\n+    tokens->WaitForTokenAvailability(ioport_);\n+\n   if (!GetQueuedCompletionStatus(ioport_, &bytes_read, (PULONG_PTR)&subproc,\n                                  &overlapped, INFINITE)) {\n     if (GetLastError() != ERROR_BROKEN_PIPE)\n@@ -266,6 +270,11 @@ bool SubprocessSet::DoWork() {\n                 // delivered by NotifyInterrupted above.\n     return true;\n \n+  if (tokens && tokens->TokenIsAvailable((ULONG_PTR)subproc)) {\n+    token_available_ = true;\n+    return false;\n+  }\n+\n   subproc->OnPipeReady();\n \n   if (subproc->Done()) {\n--- a/src/subprocess.h\n+++ b/src/subprocess.h\n@@ -76,6 +76,8 @@ struct Subprocess {\n   friend struct SubprocessSet;\n };\n \n+struct TokenPool;\n+\n /// SubprocessSet runs a ppoll/pselect() loop around a set of Subprocesses.\n /// DoWork() waits for any state change in subprocesses; finished_\n /// is a queue of subprocesses as they finish.\n@@ -84,13 +86,17 @@ struct SubprocessSet {\n   ~SubprocessSet();\n \n   Subprocess* Add(const std::string& command, bool use_console = false);\n-  bool DoWork();\n+  bool DoWork(struct TokenPool* tokens);\n   Subprocess* NextFinished();\n   void Clear();\n \n   std::vector<Subprocess*> running_;\n   std::queue<Subprocess*> finished_;\n \n+  bool token_available_;\n+  bool IsTokenAvailable() { return token_available_; }\n+  void ResetTokenAvailable() { token_available_ = false; }\n+\n #ifdef _WIN32\n   static BOOL WINAPI NotifyInterrupted(DWORD dwCtrlType);\n   static HANDLE ioport_;\n--- a/src/subprocess_test.cc\n+++ b/src/subprocess_test.cc\n@@ -13,6 +13,7 @@\n // limitations under the License.\n \n #include \"subprocess.h\"\n+#include \"tokenpool.h\"\n \n #include \"test.h\"\n \n@@ -34,8 +35,30 @@ const char* kSimpleCommand = \"cmd /c dir\n const char* kSimpleCommand = \"ls /\";\n #endif\n \n+struct TestTokenPool : public TokenPool {\n+  bool Acquire()     { return false; }\n+  void Reserve()     {}\n+  void Release()     {}\n+  void Clear()       {}\n+  bool Setup(bool ignore_unused, bool verbose, double& max_load_average) { return false; }\n+\n+#ifdef _WIN32\n+  bool _token_available;\n+  void WaitForTokenAvailability(HANDLE ioport) {\n+    if (_token_available)\n+      // unblock GetQueuedCompletionStatus()\n+      PostQueuedCompletionStatus(ioport, 0, (ULONG_PTR) this, NULL);\n+  }\n+  bool TokenIsAvailable(ULONG_PTR key) { return key == (ULONG_PTR) this; }\n+#else\n+  int _fd;\n+  int GetMonitorFd() { return _fd; }\n+#endif\n+};\n+\n struct SubprocessTest : public testing::Test {\n   SubprocessSet subprocs_;\n+  TestTokenPool tokens_;\n };\n \n }  // anonymous namespace\n@@ -45,10 +68,12 @@ TEST_F(SubprocessTest, BadCommandStderr)\n   Subprocess* subproc = subprocs_.Add(\"cmd /c ninja_no_such_command\");\n   ASSERT_NE((Subprocess *) 0, subproc);\n \n+  subprocs_.ResetTokenAvailable();\n   while (!subproc->Done()) {\n     // Pretend we discovered that stderr was ready for writing.\n-    subprocs_.DoWork();\n+    subprocs_.DoWork(NULL);\n   }\n+  ASSERT_FALSE(subprocs_.IsTokenAvailable());\n \n   EXPECT_EQ(ExitFailure, subproc->Finish());\n   EXPECT_NE(\"\", subproc->GetOutput());\n@@ -59,10 +84,12 @@ TEST_F(SubprocessTest, NoSuchCommand) {\n   Subprocess* subproc = subprocs_.Add(\"ninja_no_such_command\");\n   ASSERT_NE((Subprocess *) 0, subproc);\n \n+  subprocs_.ResetTokenAvailable();\n   while (!subproc->Done()) {\n     // Pretend we discovered that stderr was ready for writing.\n-    subprocs_.DoWork();\n+    subprocs_.DoWork(NULL);\n   }\n+  ASSERT_FALSE(subprocs_.IsTokenAvailable());\n \n   EXPECT_EQ(ExitFailure, subproc->Finish());\n   EXPECT_NE(\"\", subproc->GetOutput());\n@@ -78,9 +105,11 @@ TEST_F(SubprocessTest, InterruptChild) {\n   Subprocess* subproc = subprocs_.Add(\"kill -INT $$\");\n   ASSERT_NE((Subprocess *) 0, subproc);\n \n+  subprocs_.ResetTokenAvailable();\n   while (!subproc->Done()) {\n-    subprocs_.DoWork();\n+    subprocs_.DoWork(NULL);\n   }\n+  ASSERT_FALSE(subprocs_.IsTokenAvailable());\n \n   EXPECT_EQ(ExitInterrupted, subproc->Finish());\n }\n@@ -90,7 +119,7 @@ TEST_F(SubprocessTest, InterruptParent)\n   ASSERT_NE((Subprocess *) 0, subproc);\n \n   while (!subproc->Done()) {\n-    bool interrupted = subprocs_.DoWork();\n+    bool interrupted = subprocs_.DoWork(NULL);\n     if (interrupted)\n       return;\n   }\n@@ -102,9 +131,11 @@ TEST_F(SubprocessTest, InterruptChildWit\n   Subprocess* subproc = subprocs_.Add(\"kill -TERM $$\");\n   ASSERT_NE((Subprocess *) 0, subproc);\n \n+  subprocs_.ResetTokenAvailable();\n   while (!subproc->Done()) {\n-    subprocs_.DoWork();\n+    subprocs_.DoWork(NULL);\n   }\n+  ASSERT_FALSE(subprocs_.IsTokenAvailable());\n \n   EXPECT_EQ(ExitInterrupted, subproc->Finish());\n }\n@@ -114,7 +145,7 @@ TEST_F(SubprocessTest, InterruptParentWi\n   ASSERT_NE((Subprocess *) 0, subproc);\n \n   while (!subproc->Done()) {\n-    bool interrupted = subprocs_.DoWork();\n+    bool interrupted = subprocs_.DoWork(NULL);\n     if (interrupted)\n       return;\n   }\n@@ -126,9 +157,11 @@ TEST_F(SubprocessTest, InterruptChildWit\n   Subprocess* subproc = subprocs_.Add(\"kill -HUP $$\");\n   ASSERT_NE((Subprocess *) 0, subproc);\n \n+  subprocs_.ResetTokenAvailable();\n   while (!subproc->Done()) {\n-    subprocs_.DoWork();\n+    subprocs_.DoWork(NULL);\n   }\n+  ASSERT_FALSE(subprocs_.IsTokenAvailable());\n \n   EXPECT_EQ(ExitInterrupted, subproc->Finish());\n }\n@@ -138,7 +171,7 @@ TEST_F(SubprocessTest, InterruptParentWi\n   ASSERT_NE((Subprocess *) 0, subproc);\n \n   while (!subproc->Done()) {\n-    bool interrupted = subprocs_.DoWork();\n+    bool interrupted = subprocs_.DoWork(NULL);\n     if (interrupted)\n       return;\n   }\n@@ -153,9 +186,11 @@ TEST_F(SubprocessTest, Console) {\n         subprocs_.Add(\"test -t 0 -a -t 1 -a -t 2\", /*use_console=*/true);\n     ASSERT_NE((Subprocess*)0, subproc);\n \n+    subprocs_.ResetTokenAvailable();\n     while (!subproc->Done()) {\n-      subprocs_.DoWork();\n+      subprocs_.DoWork(NULL);\n     }\n+    ASSERT_FALSE(subprocs_.IsTokenAvailable());\n \n     EXPECT_EQ(ExitSuccess, subproc->Finish());\n   }\n@@ -167,9 +202,11 @@ TEST_F(SubprocessTest, SetWithSingle) {\n   Subprocess* subproc = subprocs_.Add(kSimpleCommand);\n   ASSERT_NE((Subprocess *) 0, subproc);\n \n+  subprocs_.ResetTokenAvailable();\n   while (!subproc->Done()) {\n-    subprocs_.DoWork();\n+    subprocs_.DoWork(NULL);\n   }\n+  ASSERT_FALSE(subprocs_.IsTokenAvailable());\n   ASSERT_EQ(ExitSuccess, subproc->Finish());\n   ASSERT_NE(\"\", subproc->GetOutput());\n \n@@ -200,12 +237,13 @@ TEST_F(SubprocessTest, SetWithMulti) {\n     ASSERT_EQ(\"\", processes[i]->GetOutput());\n   }\n \n+  subprocs_.ResetTokenAvailable();\n   while (!processes[0]->Done() || !processes[1]->Done() ||\n          !processes[2]->Done()) {\n     ASSERT_GT(subprocs_.running_.size(), 0u);\n-    subprocs_.DoWork();\n+    subprocs_.DoWork(NULL);\n   }\n-\n+  ASSERT_FALSE(subprocs_.IsTokenAvailable());\n   ASSERT_EQ(0u, subprocs_.running_.size());\n   ASSERT_EQ(3u, subprocs_.finished_.size());\n \n@@ -237,8 +275,10 @@ TEST_F(SubprocessTest, SetWithLots) {\n     ASSERT_NE((Subprocess *) 0, subproc);\n     procs.push_back(subproc);\n   }\n+  subprocs_.ResetTokenAvailable();\n   while (!subprocs_.running_.empty())\n-    subprocs_.DoWork();\n+    subprocs_.DoWork(NULL);\n+  ASSERT_FALSE(subprocs_.IsTokenAvailable());\n   for (size_t i = 0; i < procs.size(); ++i) {\n     ASSERT_EQ(ExitSuccess, procs[i]->Finish());\n     ASSERT_NE(\"\", procs[i]->GetOutput());\n@@ -254,10 +294,91 @@ TEST_F(SubprocessTest, SetWithLots) {\n // that stdin is closed.\n TEST_F(SubprocessTest, ReadStdin) {\n   Subprocess* subproc = subprocs_.Add(\"cat -\");\n+  subprocs_.ResetTokenAvailable();\n   while (!subproc->Done()) {\n-    subprocs_.DoWork();\n+    subprocs_.DoWork(NULL);\n   }\n+  ASSERT_FALSE(subprocs_.IsTokenAvailable());\n   ASSERT_EQ(ExitSuccess, subproc->Finish());\n   ASSERT_EQ(1u, subprocs_.finished_.size());\n }\n #endif  // _WIN32\n+\n+TEST_F(SubprocessTest, TokenAvailable) {\n+  Subprocess* subproc = subprocs_.Add(kSimpleCommand);\n+  ASSERT_NE((Subprocess *) 0, subproc);\n+\n+  // simulate GNUmake jobserver pipe with 1 token\n+#ifdef _WIN32\n+  tokens_._token_available = true;\n+#else\n+  int fds[2];\n+  ASSERT_EQ(0u, pipe(fds));\n+  tokens_._fd = fds[0];\n+  ASSERT_EQ(1u, write(fds[1], \"T\", 1));\n+#endif\n+\n+  subprocs_.ResetTokenAvailable();\n+  subprocs_.DoWork(&tokens_);\n+#ifdef _WIN32\n+  tokens_._token_available = false;\n+  // we need to loop here as we have no conrol where the token\n+  // I/O completion post ends up in the queue\n+  while (!subproc->Done() && !subprocs_.IsTokenAvailable()) {\n+    subprocs_.DoWork(&tokens_);\n+  }\n+#endif\n+\n+  EXPECT_TRUE(subprocs_.IsTokenAvailable());\n+  EXPECT_EQ(0u, subprocs_.finished_.size());\n+\n+  // remove token to let DoWork() wait for command again\n+#ifndef _WIN32\n+  char token;\n+  ASSERT_EQ(1u, read(fds[0], &token, 1));\n+#endif\n+\n+  while (!subproc->Done()) {\n+    subprocs_.DoWork(&tokens_);\n+  }\n+\n+#ifndef _WIN32\n+  close(fds[1]);\n+  close(fds[0]);\n+#endif\n+\n+  EXPECT_EQ(ExitSuccess, subproc->Finish());\n+  EXPECT_NE(\"\", subproc->GetOutput());\n+\n+  EXPECT_EQ(1u, subprocs_.finished_.size());\n+}\n+\n+TEST_F(SubprocessTest, TokenNotAvailable) {\n+  Subprocess* subproc = subprocs_.Add(kSimpleCommand);\n+  ASSERT_NE((Subprocess *) 0, subproc);\n+\n+  // simulate GNUmake jobserver pipe with 0 tokens\n+#ifdef _WIN32\n+  tokens_._token_available = false;\n+#else\n+  int fds[2];\n+  ASSERT_EQ(0u, pipe(fds));\n+  tokens_._fd = fds[0];\n+#endif\n+\n+  subprocs_.ResetTokenAvailable();\n+  while (!subproc->Done()) {\n+    subprocs_.DoWork(&tokens_);\n+  }\n+\n+#ifndef _WIN32\n+  close(fds[1]);\n+  close(fds[0]);\n+#endif\n+\n+  EXPECT_FALSE(subprocs_.IsTokenAvailable());\n+  EXPECT_EQ(ExitSuccess, subproc->Finish());\n+  EXPECT_NE(\"\", subproc->GetOutput());\n+\n+  EXPECT_EQ(1u, subprocs_.finished_.size());\n+}\n--- /dev/null\n+++ b/src/tokenpool-gnu-make-posix.cc\n@@ -0,0 +1,202 @@\n+// Copyright 2016-2018 Google Inc. All Rights Reserved.\n+//\n+// Licensed under the Apache License, Version 2.0 (the \"License\");\n+// you may not use this file except in compliance with the License.\n+// You may obtain a copy of the License at\n+//\n+//     http://www.apache.org/licenses/LICENSE-2.0\n+//\n+// Unless required by applicable law or agreed to in writing, software\n+// distributed under the License is distributed on an \"AS IS\" BASIS,\n+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n+// See the License for the specific language governing permissions and\n+// limitations under the License.\n+\n+#include \"tokenpool-gnu-make.h\"\n+\n+#include <errno.h>\n+#include <fcntl.h>\n+#include <poll.h>\n+#include <unistd.h>\n+#include <signal.h>\n+#include <sys/time.h>\n+#include <stdio.h>\n+#include <string.h>\n+#include <stdlib.h>\n+\n+// TokenPool implementation for GNU make jobserver - POSIX implementation\n+// (http://make.mad-scientist.net/papers/jobserver-implementation/)\n+struct GNUmakeTokenPoolPosix : public GNUmakeTokenPool {\n+  GNUmakeTokenPoolPosix();\n+  virtual ~GNUmakeTokenPoolPosix();\n+\n+  virtual int GetMonitorFd();\n+\n+  virtual const char* GetEnv(const char* name) { return getenv(name); };\n+  virtual bool ParseAuth(const char* jobserver);\n+  virtual bool AcquireToken();\n+  virtual bool ReturnToken();\n+\n+ private:\n+  int rfd_;\n+  int wfd_;\n+\n+  struct sigaction old_act_;\n+  bool restore_;\n+\n+  static int dup_rfd_;\n+  static void CloseDupRfd(int signum);\n+\n+  bool CheckFd(int fd);\n+  bool SetAlarmHandler();\n+};\n+\n+GNUmakeTokenPoolPosix::GNUmakeTokenPoolPosix() : rfd_(-1), wfd_(-1), restore_(false) {\n+}\n+\n+GNUmakeTokenPoolPosix::~GNUmakeTokenPoolPosix() {\n+  Clear();\n+  if (restore_)\n+    sigaction(SIGALRM, &old_act_, NULL);\n+}\n+\n+bool GNUmakeTokenPoolPosix::CheckFd(int fd) {\n+  if (fd < 0)\n+    return false;\n+  int ret = fcntl(fd, F_GETFD);\n+  if (ret < 0)\n+    return false;\n+  return true;\n+}\n+\n+int GNUmakeTokenPoolPosix::dup_rfd_ = -1;\n+\n+void GNUmakeTokenPoolPosix::CloseDupRfd(int signum) {\n+  close(dup_rfd_);\n+  dup_rfd_ = -1;\n+}\n+\n+bool GNUmakeTokenPoolPosix::SetAlarmHandler() {\n+  struct sigaction act;\n+  memset(&act, 0, sizeof(act));\n+  act.sa_handler = CloseDupRfd;\n+  if (sigaction(SIGALRM, &act, &old_act_) < 0) {\n+    perror(\"sigaction:\");\n+    return false;\n+  }\n+  restore_ = true;\n+  return true;\n+}\n+\n+bool GNUmakeTokenPoolPosix::ParseAuth(const char* jobserver) {\n+  int rfd = -1;\n+  int wfd = -1;\n+  if ((sscanf(jobserver, \"%*[^=]=%d,%d\", &rfd, &wfd) == 2) &&\n+      CheckFd(rfd) &&\n+      CheckFd(wfd) &&\n+      SetAlarmHandler()) {\n+    rfd_ = rfd;\n+    wfd_ = wfd;\n+    return true;\n+  }\n+\n+  return false;\n+}\n+\n+bool GNUmakeTokenPoolPosix::AcquireToken() {\n+  // Please read\n+  //\n+  //   http://make.mad-scientist.net/papers/jobserver-implementation/\n+  //\n+  // for the reasoning behind the following code.\n+  //\n+  // Try to read one character from the pipe. Returns true on success.\n+  //\n+  // First check if read() would succeed without blocking.\n+#ifdef USE_PPOLL\n+  pollfd pollfds[] = {{rfd_, POLLIN, 0}};\n+  int ret = poll(pollfds, 1, 0);\n+#else\n+  fd_set set;\n+  struct timeval timeout = { 0, 0 };\n+  FD_ZERO(&set);\n+  FD_SET(rfd_, &set);\n+  int ret = select(rfd_ + 1, &set, NULL, NULL, &timeout);\n+#endif\n+  if (ret > 0) {\n+    // Handle potential race condition:\n+    //  - the above check succeeded, i.e. read() should not block\n+    //  - the character disappears before we call read()\n+    //\n+    // Create a duplicate of rfd_. The duplicate file descriptor dup_rfd_\n+    // can safely be closed by signal handlers without affecting rfd_.\n+    dup_rfd_ = dup(rfd_);\n+\n+    if (dup_rfd_ != -1) {\n+      struct sigaction act, old_act;\n+      int ret = 0;\n+\n+      // Temporarily replace SIGCHLD handler with our own\n+      memset(&act, 0, sizeof(act));\n+      act.sa_handler = CloseDupRfd;\n+      if (sigaction(SIGCHLD, &act, &old_act) == 0) {\n+        struct itimerval timeout;\n+\n+        // install a 100ms timeout that generates SIGALARM on expiration\n+        memset(&timeout, 0, sizeof(timeout));\n+        timeout.it_value.tv_usec = 100 * 1000; // [ms] -> [usec]\n+        if (setitimer(ITIMER_REAL, &timeout, NULL) == 0) {\n+          char buf;\n+\n+          // Now try to read() from dup_rfd_. Return values from read():\n+          //\n+          // 1. token read                               ->  1\n+          // 2. pipe closed                              ->  0\n+          // 3. alarm expires                            -> -1 (EINTR)\n+          // 4. child exits                              -> -1 (EINTR)\n+          // 5. alarm expired before entering read()     -> -1 (EBADF)\n+          // 6. child exited before entering read()      -> -1 (EBADF)\n+          // 7. child exited before handler is installed -> go to 1 - 3\n+          ret = read(dup_rfd_, &buf, 1);\n+\n+          // disarm timer\n+          memset(&timeout, 0, sizeof(timeout));\n+          setitimer(ITIMER_REAL, &timeout, NULL);\n+        }\n+\n+        sigaction(SIGCHLD, &old_act, NULL);\n+      }\n+\n+      CloseDupRfd(0);\n+\n+      // Case 1 from above list\n+      if (ret > 0)\n+        return true;\n+    }\n+  }\n+\n+  // read() would block, i.e. no token available,\n+  // cases 2-6 from above list or\n+  // select() / poll() / dup() / sigaction() / setitimer() failed\n+  return false;\n+}\n+\n+bool GNUmakeTokenPoolPosix::ReturnToken() {\n+  const char buf = '+';\n+  while (1) {\n+    int ret = write(wfd_, &buf, 1);\n+    if (ret > 0)\n+      return true;\n+    if ((ret != -1) || (errno != EINTR))\n+      return false;\n+    // write got interrupted - retry\n+  }\n+}\n+\n+int GNUmakeTokenPoolPosix::GetMonitorFd() {\n+  return rfd_;\n+}\n+\n+TokenPool* TokenPool::Get() {\n+  return new GNUmakeTokenPoolPosix;\n+}\n--- /dev/null\n+++ b/src/tokenpool-gnu-make-win32.cc\n@@ -0,0 +1,239 @@\n+// Copyright 2018 Google Inc. All Rights Reserved.\n+//\n+// Licensed under the Apache License, Version 2.0 (the \"License\");\n+// you may not use this file except in compliance with the License.\n+// You may obtain a copy of the License at\n+//\n+//     http://www.apache.org/licenses/LICENSE-2.0\n+//\n+// Unless required by applicable law or agreed to in writing, software\n+// distributed under the License is distributed on an \"AS IS\" BASIS,\n+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n+// See the License for the specific language governing permissions and\n+// limitations under the License.\n+\n+#include \"tokenpool-gnu-make.h\"\n+\n+// Always include this first.\n+// Otherwise the other system headers don't work correctly under Win32\n+#include <windows.h>\n+\n+#include <ctype.h>\n+#include <stdlib.h>\n+#include <string.h>\n+\n+#include \"util.h\"\n+\n+// TokenPool implementation for GNU make jobserver - Win32 implementation\n+// (https://www.gnu.org/software/make/manual/html_node/Windows-Jobserver.html)\n+struct GNUmakeTokenPoolWin32 : public GNUmakeTokenPool {\n+  GNUmakeTokenPoolWin32();\n+  virtual ~GNUmakeTokenPoolWin32();\n+\n+  virtual void WaitForTokenAvailability(HANDLE ioport);\n+  virtual bool TokenIsAvailable(ULONG_PTR key);\n+\n+  virtual const char* GetEnv(const char* name);\n+  virtual bool ParseAuth(const char* jobserver);\n+  virtual bool AcquireToken();\n+  virtual bool ReturnToken();\n+\n+ private:\n+  // Semaphore for GNU make jobserver protocol\n+  HANDLE semaphore_jobserver_;\n+  // Semaphore Child -> Parent\n+  // - child releases it before entering wait on jobserver semaphore\n+  // - parent blocks on it to know when child enters wait\n+  HANDLE semaphore_enter_wait_;\n+  // Semaphore Parent -> Child\n+  // - parent releases it to allow child to restart loop\n+  // - child blocks on it to know when to restart loop\n+  HANDLE semaphore_restart_;\n+  // set to false if child should exit loop and terminate thread\n+  bool running_;\n+  // child thread\n+  HANDLE child_;\n+  // I/O completion port from SubprocessSet\n+  HANDLE ioport_;\n+\n+\n+  DWORD SemaphoreThread();\n+  void ReleaseSemaphore(HANDLE semaphore);\n+  void WaitForObject(HANDLE object);\n+  static DWORD WINAPI SemaphoreThreadWrapper(LPVOID param);\n+  static void NoopAPCFunc(ULONG_PTR param);\n+};\n+\n+GNUmakeTokenPoolWin32::GNUmakeTokenPoolWin32() : semaphore_jobserver_(NULL),\n+                                                 semaphore_enter_wait_(NULL),\n+                                                 semaphore_restart_(NULL),\n+                                                 running_(false),\n+                                                 child_(NULL),\n+                                                 ioport_(NULL) {\n+}\n+\n+GNUmakeTokenPoolWin32::~GNUmakeTokenPoolWin32() {\n+  Clear();\n+  CloseHandle(semaphore_jobserver_);\n+  semaphore_jobserver_ = NULL;\n+\n+  if (child_) {\n+    // tell child thread to exit\n+    running_ = false;\n+    ReleaseSemaphore(semaphore_restart_);\n+\n+    // wait for child thread to exit\n+    WaitForObject(child_);\n+    CloseHandle(child_);\n+    child_ = NULL;\n+  }\n+\n+  if (semaphore_restart_) {\n+    CloseHandle(semaphore_restart_);\n+    semaphore_restart_ = NULL;\n+  }\n+\n+  if (semaphore_enter_wait_) {\n+    CloseHandle(semaphore_enter_wait_);\n+    semaphore_enter_wait_ = NULL;\n+  }\n+}\n+\n+const char* GNUmakeTokenPoolWin32::GetEnv(const char* name) {\n+  // getenv() does not work correctly together with tokenpool_tests.cc\n+  static char buffer[MAX_PATH + 1];\n+  if (GetEnvironmentVariable(name, buffer, sizeof(buffer)) == 0)\n+    return NULL;\n+  return buffer;\n+}\n+\n+bool GNUmakeTokenPoolWin32::ParseAuth(const char* jobserver) {\n+  // match \"--jobserver-auth=gmake_semaphore_<INTEGER>...\"\n+  const char* start = strchr(jobserver, '=');\n+  if (start) {\n+    const char* end = start;\n+    unsigned int len;\n+    char c, *auth;\n+\n+    while ((c = *++end) != '\\0')\n+      if (!(isalnum(c) || (c == '_')))\n+        break;\n+    len = end - start; // includes string terminator in count\n+\n+    if ((len > 1) && ((auth = (char*)malloc(len)) != NULL)) {\n+      strncpy(auth, start + 1, len - 1);\n+      auth[len - 1] = '\\0';\n+\n+      if ((semaphore_jobserver_ =\n+           OpenSemaphore(SEMAPHORE_ALL_ACCESS, /* Semaphore access setting */\n+                         FALSE,                /* Child processes DON'T inherit */\n+                         auth                  /* Semaphore name */\n+                        )) != NULL) {\n+        free(auth);\n+        return true;\n+      }\n+\n+      free(auth);\n+    }\n+  }\n+\n+  return false;\n+}\n+\n+bool GNUmakeTokenPoolWin32::AcquireToken() {\n+  return WaitForSingleObject(semaphore_jobserver_, 0) == WAIT_OBJECT_0;\n+}\n+\n+bool GNUmakeTokenPoolWin32::ReturnToken() {\n+  ReleaseSemaphore(semaphore_jobserver_);\n+  return true;\n+}\n+\n+DWORD GNUmakeTokenPoolWin32::SemaphoreThread() {\n+  while (running_) {\n+    // indicate to parent that we are entering wait\n+    ReleaseSemaphore(semaphore_enter_wait_);\n+\n+    // alertable wait forever on token semaphore\n+    if (WaitForSingleObjectEx(semaphore_jobserver_, INFINITE, TRUE) == WAIT_OBJECT_0) {\n+      // release token again for AcquireToken()\n+      ReleaseSemaphore(semaphore_jobserver_);\n+\n+      // indicate to parent on ioport that a token might be available\n+      if (!PostQueuedCompletionStatus(ioport_, 0, (ULONG_PTR) this, NULL))\n+        Win32Fatal(\"PostQueuedCompletionStatus\");\n+    }\n+\n+    // wait for parent to allow loop restart\n+    WaitForObject(semaphore_restart_);\n+    // semaphore is now in nonsignaled state again for next run...\n+  }\n+\n+  return 0;\n+}\n+\n+DWORD WINAPI GNUmakeTokenPoolWin32::SemaphoreThreadWrapper(LPVOID param) {\n+  GNUmakeTokenPoolWin32* This = (GNUmakeTokenPoolWin32*) param;\n+  return This->SemaphoreThread();\n+}\n+\n+void GNUmakeTokenPoolWin32::NoopAPCFunc(ULONG_PTR param) {\n+}\n+\n+void GNUmakeTokenPoolWin32::WaitForTokenAvailability(HANDLE ioport) {\n+  if (child_ == NULL) {\n+    // first invocation\n+    //\n+    // subprocess-win32.cc uses I/O completion port (IOCP) which can't be\n+    // used as a waitable object. Therefore we can't use WaitMultipleObjects()\n+    // to wait on the IOCP and the token semaphore at the same time. Create\n+    // a child thread that waits on the semaphore and posts an I/O completion\n+    ioport_ = ioport;\n+\n+    // create both semaphores in nonsignaled state\n+    if ((semaphore_enter_wait_ = CreateSemaphore(NULL, 0, 1, NULL))\n+        == NULL)\n+      Win32Fatal(\"CreateSemaphore/enter_wait\");\n+    if ((semaphore_restart_ = CreateSemaphore(NULL, 0, 1, NULL))\n+        == NULL)\n+      Win32Fatal(\"CreateSemaphore/restart\");\n+\n+    // start child thread\n+    running_ = true;\n+    if ((child_ = CreateThread(NULL, 0, &SemaphoreThreadWrapper, this, 0, NULL))\n+        == NULL)\n+      Win32Fatal(\"CreateThread\");\n+\n+  } else {\n+    // all further invocations - allow child thread to loop\n+    ReleaseSemaphore(semaphore_restart_);\n+  }\n+\n+  // wait for child thread to enter wait\n+  WaitForObject(semaphore_enter_wait_);\n+  // semaphore is now in nonsignaled state again for next run...\n+\n+  // now SubprocessSet::DoWork() can enter GetQueuedCompletionStatus()...\n+}\n+\n+bool GNUmakeTokenPoolWin32::TokenIsAvailable(ULONG_PTR key) {\n+  // alert child thread to break wait on token semaphore\n+  QueueUserAPC((PAPCFUNC)&NoopAPCFunc, child_, (ULONG_PTR)NULL);\n+\n+  // return true when GetQueuedCompletionStatus() returned our key\n+  return key == (ULONG_PTR) this;\n+}\n+\n+void GNUmakeTokenPoolWin32::ReleaseSemaphore(HANDLE semaphore) {\n+  if (!::ReleaseSemaphore(semaphore, 1, NULL))\n+    Win32Fatal(\"ReleaseSemaphore\");\n+}\n+\n+void GNUmakeTokenPoolWin32::WaitForObject(HANDLE object) {\n+  if (WaitForSingleObject(object, INFINITE) != WAIT_OBJECT_0)\n+    Win32Fatal(\"WaitForSingleObject\");\n+}\n+\n+TokenPool* TokenPool::Get() {\n+  return new GNUmakeTokenPoolWin32;\n+}\n--- /dev/null\n+++ b/src/tokenpool-gnu-make.cc\n@@ -0,0 +1,108 @@\n+// Copyright 2016-2018 Google Inc. All Rights Reserved.\n+//\n+// Licensed under the Apache License, Version 2.0 (the \"License\");\n+// you may not use this file except in compliance with the License.\n+// You may obtain a copy of the License at\n+//\n+//     http://www.apache.org/licenses/LICENSE-2.0\n+//\n+// Unless required by applicable law or agreed to in writing, software\n+// distributed under the License is distributed on an \"AS IS\" BASIS,\n+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n+// See the License for the specific language governing permissions and\n+// limitations under the License.\n+\n+#include \"tokenpool-gnu-make.h\"\n+\n+#include <stdlib.h>\n+#include <stdio.h>\n+#include <string.h>\n+\n+#include \"line_printer.h\"\n+\n+// TokenPool implementation for GNU make jobserver - common bits\n+// every instance owns an implicit token -> available_ == 1\n+GNUmakeTokenPool::GNUmakeTokenPool() : available_(1), used_(0) {\n+}\n+\n+GNUmakeTokenPool::~GNUmakeTokenPool() {\n+}\n+\n+bool GNUmakeTokenPool::Setup(bool ignore,\n+                             bool verbose,\n+                             double& max_load_average) {\n+  const char* value = GetEnv(\"MAKEFLAGS\");\n+  if (!value)\n+    return false;\n+\n+  // GNU make <= 4.1\n+  const char* jobserver = strstr(value, \"--jobserver-fds=\");\n+  if (!jobserver)\n+    // GNU make => 4.2\n+    jobserver = strstr(value, \"--jobserver-auth=\");\n+  if (jobserver) {\n+    LinePrinter printer;\n+\n+    if (ignore) {\n+      printer.PrintOnNewLine(\"ninja: warning: -jN forced on command line; ignoring GNU make jobserver.\\n\");\n+    } else {\n+      if (ParseAuth(jobserver)) {\n+        const char* l_arg = strstr(value, \" -l\");\n+        int load_limit = -1;\n+\n+        if (verbose) {\n+          printer.PrintOnNewLine(\"ninja: using GNU make jobserver.\\n\");\n+        }\n+\n+        // translate GNU make -lN to ninja -lN\n+        if (l_arg &&\n+            (sscanf(l_arg + 3, \"%d \", &load_limit) == 1) &&\n+            (load_limit > 0)) {\n+          max_load_average = load_limit;\n+        }\n+\n+        return true;\n+      }\n+    }\n+  }\n+\n+  return false;\n+}\n+\n+bool GNUmakeTokenPool::Acquire() {\n+  if (available_ > 0)\n+    return true;\n+\n+  if (AcquireToken()) {\n+    // token acquired\n+    available_++;\n+    return true;\n+  }\n+\n+  // no token available\n+  return false;\n+}\n+\n+void GNUmakeTokenPool::Reserve() {\n+  available_--;\n+  used_++;\n+}\n+\n+void GNUmakeTokenPool::Return() {\n+  if (ReturnToken())\n+    available_--;\n+}\n+\n+void GNUmakeTokenPool::Release() {\n+  available_++;\n+  used_--;\n+  if (available_ > 1)\n+    Return();\n+}\n+\n+void GNUmakeTokenPool::Clear() {\n+  while (used_ > 0)\n+    Release();\n+  while (available_ > 1)\n+    Return();\n+}\n--- /dev/null\n+++ b/src/tokenpool-gnu-make.h\n@@ -0,0 +1,40 @@\n+// Copyright 2016-2018 Google Inc. All Rights Reserved.\n+//\n+// Licensed under the Apache License, Version 2.0 (the \"License\");\n+// you may not use this file except in compliance with the License.\n+// You may obtain a copy of the License at\n+//\n+//     http://www.apache.org/licenses/LICENSE-2.0\n+//\n+// Unless required by applicable law or agreed to in writing, software\n+// distributed under the License is distributed on an \"AS IS\" BASIS,\n+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n+// See the License for the specific language governing permissions and\n+// limitations under the License.\n+\n+#include \"tokenpool.h\"\n+\n+// interface to GNU make token pool\n+struct GNUmakeTokenPool : public TokenPool {\n+  GNUmakeTokenPool();\n+  ~GNUmakeTokenPool();\n+\n+  // token pool implementation\n+  virtual bool Acquire();\n+  virtual void Reserve();\n+  virtual void Release();\n+  virtual void Clear();\n+  virtual bool Setup(bool ignore, bool verbose, double& max_load_average);\n+\n+  // platform specific implementation\n+  virtual const char* GetEnv(const char* name) = 0;\n+  virtual bool ParseAuth(const char* jobserver) = 0;\n+  virtual bool AcquireToken() = 0;\n+  virtual bool ReturnToken() = 0;\n+\n+ private:\n+  int available_;\n+  int used_;\n+\n+  void Return();\n+};\n--- /dev/null\n+++ b/src/tokenpool.h\n@@ -0,0 +1,42 @@\n+// Copyright 2016-2018 Google Inc. All Rights Reserved.\n+//\n+// Licensed under the Apache License, Version 2.0 (the \"License\");\n+// you may not use this file except in compliance with the License.\n+// You may obtain a copy of the License at\n+//\n+//     http://www.apache.org/licenses/LICENSE-2.0\n+//\n+// Unless required by applicable law or agreed to in writing, software\n+// distributed under the License is distributed on an \"AS IS\" BASIS,\n+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n+// See the License for the specific language governing permissions and\n+// limitations under the License.\n+\n+#ifdef _WIN32\n+#include <windows.h>\n+#endif\n+\n+// interface to token pool\n+struct TokenPool {\n+  virtual ~TokenPool() {}\n+\n+  virtual bool Acquire() = 0;\n+  virtual void Reserve() = 0;\n+  virtual void Release() = 0;\n+  virtual void Clear() = 0;\n+\n+  // returns false if token pool setup failed\n+  virtual bool Setup(bool ignore, bool verbose, double& max_load_average) = 0;\n+\n+#ifdef _WIN32\n+  virtual void WaitForTokenAvailability(HANDLE ioport) = 0;\n+  // returns true if a token has become available\n+  // key is result from GetQueuedCompletionStatus()\n+  virtual bool TokenIsAvailable(ULONG_PTR key) = 0;\n+#else\n+  virtual int GetMonitorFd() = 0;\n+#endif\n+\n+  // returns NULL if token pool is not available\n+  static TokenPool* Get();\n+};\n--- /dev/null\n+++ b/src/tokenpool_test.cc\n@@ -0,0 +1,269 @@\n+// Copyright 2018 Google Inc. All Rights Reserved.\n+//\n+// Licensed under the Apache License, Version 2.0 (the \"License\");\n+// you may not use this file except in compliance with the License.\n+// You may obtain a copy of the License at\n+//\n+//     http://www.apache.org/licenses/LICENSE-2.0\n+//\n+// Unless required by applicable law or agreed to in writing, software\n+// distributed under the License is distributed on an \"AS IS\" BASIS,\n+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n+// See the License for the specific language governing permissions and\n+// limitations under the License.\n+\n+#include \"tokenpool.h\"\n+\n+#include \"test.h\"\n+\n+#ifdef _WIN32\n+#include <windows.h>\n+#else\n+#include <unistd.h>\n+#endif\n+\n+#include <stdio.h>\n+#include <stdlib.h>\n+\n+#ifdef _WIN32\n+// should contain all valid characters\n+#define SEMAPHORE_NAME      \"abcdefghijklmnopqrstwxyz01234567890_\"\n+#define AUTH_FORMAT(tmpl)   \"foo \" tmpl \"=%s bar\"\n+#define ENVIRONMENT_CLEAR() SetEnvironmentVariable(\"MAKEFLAGS\", NULL)\n+#define ENVIRONMENT_INIT(v) SetEnvironmentVariable(\"MAKEFLAGS\", v)\n+#else\n+#define AUTH_FORMAT(tmpl)   \"foo \" tmpl \"=%d,%d bar\"\n+#define ENVIRONMENT_CLEAR() unsetenv(\"MAKEFLAGS\")\n+#define ENVIRONMENT_INIT(v) setenv(\"MAKEFLAGS\", v, true)\n+#endif\n+\n+namespace {\n+\n+const double kLoadAverageDefault = -1.23456789;\n+\n+struct TokenPoolTest : public testing::Test {\n+  double load_avg_;\n+  TokenPool* tokens_;\n+  char buf_[1024];\n+#ifdef _WIN32\n+  const char* semaphore_name_;\n+  HANDLE semaphore_;\n+#else\n+  int fds_[2];\n+#endif\n+\n+  virtual void SetUp() {\n+    load_avg_ = kLoadAverageDefault;\n+    tokens_ = NULL;\n+    ENVIRONMENT_CLEAR();\n+#ifdef _WIN32\n+    semaphore_name_ = SEMAPHORE_NAME;\n+    if ((semaphore_ = CreateSemaphore(0, 0, 2, SEMAPHORE_NAME)) == NULL)\n+#else\n+    if (pipe(fds_) < 0)\n+#endif\n+      ASSERT_TRUE(false);\n+  }\n+\n+  void CreatePool(const char* format, bool ignore_jobserver = false) {\n+    if (format) {\n+      sprintf(buf_, format,\n+#ifdef _WIN32\n+              semaphore_name_\n+#else\n+              fds_[0], fds_[1]\n+#endif\n+      );\n+      ENVIRONMENT_INIT(buf_);\n+    }\n+    if ((tokens_ = TokenPool::Get()) != NULL) {\n+      if (!tokens_->Setup(ignore_jobserver, false, load_avg_)) {\n+        delete tokens_;\n+        tokens_ = NULL;\n+      }\n+    }\n+  }\n+\n+  void CreateDefaultPool() {\n+    CreatePool(AUTH_FORMAT(\"--jobserver-auth\"));\n+  }\n+\n+  virtual void TearDown() {\n+    if (tokens_)\n+      delete tokens_;\n+#ifdef _WIN32\n+    CloseHandle(semaphore_);\n+#else\n+    close(fds_[0]);\n+    close(fds_[1]);\n+#endif\n+    ENVIRONMENT_CLEAR();\n+  }\n+};\n+\n+} // anonymous namespace\n+\n+// verifies none implementation\n+TEST_F(TokenPoolTest, NoTokenPool) {\n+  CreatePool(NULL, false);\n+\n+  EXPECT_EQ(NULL, tokens_);\n+  EXPECT_EQ(kLoadAverageDefault, load_avg_);\n+}\n+\n+TEST_F(TokenPoolTest, SuccessfulOldSetup) {\n+  // GNUmake <= 4.1\n+  CreatePool(AUTH_FORMAT(\"--jobserver-fds\"));\n+\n+  EXPECT_NE(NULL, tokens_);\n+  EXPECT_EQ(kLoadAverageDefault, load_avg_);\n+}\n+\n+TEST_F(TokenPoolTest, SuccessfulNewSetup) {\n+  // GNUmake => 4.2\n+  CreateDefaultPool();\n+\n+  EXPECT_NE(NULL, tokens_);\n+  EXPECT_EQ(kLoadAverageDefault, load_avg_);\n+}\n+\n+TEST_F(TokenPoolTest, IgnoreWithJN) {\n+  CreatePool(AUTH_FORMAT(\"--jobserver-auth\"), true);\n+\n+  EXPECT_EQ(NULL, tokens_);\n+  EXPECT_EQ(kLoadAverageDefault, load_avg_);\n+}\n+\n+TEST_F(TokenPoolTest, HonorLN) {\n+  CreatePool(AUTH_FORMAT(\"-l9 --jobserver-auth\"));\n+\n+  EXPECT_NE(NULL, tokens_);\n+  EXPECT_EQ(9.0, load_avg_);\n+}\n+\n+#ifdef _WIN32\n+TEST_F(TokenPoolTest, SemaphoreNotFound) {\n+  semaphore_name_ = SEMAPHORE_NAME \"_foobar\";\n+  CreateDefaultPool();\n+\n+  EXPECT_EQ(NULL, tokens_);\n+  EXPECT_EQ(kLoadAverageDefault, load_avg_);\n+}\n+\n+TEST_F(TokenPoolTest, TokenIsAvailable) {\n+  CreateDefaultPool();\n+\n+  ASSERT_NE(NULL, tokens_);\n+  EXPECT_EQ(kLoadAverageDefault, load_avg_);\n+\n+  EXPECT_TRUE(tokens_->TokenIsAvailable((ULONG_PTR)tokens_));\n+}\n+#else\n+TEST_F(TokenPoolTest, MonitorFD) {\n+  CreateDefaultPool();\n+\n+  ASSERT_NE(NULL, tokens_);\n+  EXPECT_EQ(kLoadAverageDefault, load_avg_);\n+\n+  EXPECT_EQ(fds_[0], tokens_->GetMonitorFd());\n+}\n+#endif\n+\n+TEST_F(TokenPoolTest, ImplicitToken) {\n+  CreateDefaultPool();\n+\n+  ASSERT_NE(NULL, tokens_);\n+  EXPECT_EQ(kLoadAverageDefault, load_avg_);\n+\n+  EXPECT_TRUE(tokens_->Acquire());\n+  tokens_->Reserve();\n+  EXPECT_FALSE(tokens_->Acquire());\n+  tokens_->Release();\n+  EXPECT_TRUE(tokens_->Acquire());\n+}\n+\n+TEST_F(TokenPoolTest, TwoTokens) {\n+  CreateDefaultPool();\n+\n+  ASSERT_NE(NULL, tokens_);\n+  EXPECT_EQ(kLoadAverageDefault, load_avg_);\n+\n+  // implicit token\n+  EXPECT_TRUE(tokens_->Acquire());\n+  tokens_->Reserve();\n+  EXPECT_FALSE(tokens_->Acquire());\n+\n+  // jobserver offers 2nd token\n+#ifdef _WIN32\n+  LONG previous;\n+  ASSERT_TRUE(ReleaseSemaphore(semaphore_, 1, &previous));\n+  ASSERT_EQ(0, previous);\n+#else\n+  ASSERT_EQ(1u, write(fds_[1], \"T\", 1));\n+#endif\n+  EXPECT_TRUE(tokens_->Acquire());\n+  tokens_->Reserve();\n+  EXPECT_FALSE(tokens_->Acquire());\n+\n+  // release 2nd token\n+  tokens_->Release();\n+  EXPECT_TRUE(tokens_->Acquire());\n+\n+  // release implict token - must return 2nd token back to jobserver\n+  tokens_->Release();\n+  EXPECT_TRUE(tokens_->Acquire());\n+\n+  // there must be one token available\n+#ifdef _WIN32\n+  EXPECT_EQ(WAIT_OBJECT_0, WaitForSingleObject(semaphore_, 0));\n+  EXPECT_TRUE(ReleaseSemaphore(semaphore_, 1, &previous));\n+  EXPECT_EQ(0, previous);\n+#else\n+  EXPECT_EQ(1u, read(fds_[0], buf_, sizeof(buf_)));\n+#endif\n+\n+  // implicit token\n+  EXPECT_TRUE(tokens_->Acquire());\n+}\n+\n+TEST_F(TokenPoolTest, Clear) {\n+  CreateDefaultPool();\n+\n+  ASSERT_NE(NULL, tokens_);\n+  EXPECT_EQ(kLoadAverageDefault, load_avg_);\n+\n+  // implicit token\n+  EXPECT_TRUE(tokens_->Acquire());\n+  tokens_->Reserve();\n+  EXPECT_FALSE(tokens_->Acquire());\n+\n+  // jobserver offers 2nd & 3rd token\n+#ifdef _WIN32\n+  LONG previous;\n+  ASSERT_TRUE(ReleaseSemaphore(semaphore_, 2, &previous));\n+  ASSERT_EQ(0, previous);\n+#else\n+  ASSERT_EQ(2u, write(fds_[1], \"TT\", 2));\n+#endif\n+  EXPECT_TRUE(tokens_->Acquire());\n+  tokens_->Reserve();\n+  EXPECT_TRUE(tokens_->Acquire());\n+  tokens_->Reserve();\n+  EXPECT_FALSE(tokens_->Acquire());\n+\n+  tokens_->Clear();\n+  EXPECT_TRUE(tokens_->Acquire());\n+\n+  // there must be two tokens available\n+#ifdef _WIN32\n+  EXPECT_EQ(WAIT_OBJECT_0, WaitForSingleObject(semaphore_, 0));\n+  EXPECT_EQ(WAIT_OBJECT_0, WaitForSingleObject(semaphore_, 0));\n+  EXPECT_TRUE(ReleaseSemaphore(semaphore_, 2, &previous));\n+  EXPECT_EQ(0, previous);\n+#else\n+  EXPECT_EQ(2u, read(fds_[0], buf_, sizeof(buf_)));\n+#endif\n+\n+  // implicit token\n+  EXPECT_TRUE(tokens_->Acquire());\n+}\n"
  },
  {
    "path": "tools/padjffs2/Makefile",
    "content": "#\n# Copyright (C) 2011-2012 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=padjffs2\nPKG_RELEASE:=1\n\ninclude $(INCLUDE_DIR)/host-build.mk\n\ndefine Host/Prepare\n\tmkdir -p $(HOST_BUILD_DIR)\n\t$(CP) ./src/* $(HOST_BUILD_DIR)/\n\tfind $(HOST_BUILD_DIR) -name .svn | $(XARGS) rm -rf\nendef\n\ndefine Host/Compile\n\t$(MAKE) -C $(HOST_BUILD_DIR)\nendef\n\ndefine Host/Configure\nendef\n\ndefine Host/Install\n\t$(CP) $(HOST_BUILD_DIR)/padjffs2 $(STAGING_DIR_HOST)/bin/\nendef\n\ndefine Host/Clean\n\trm -f $(STAGING_DIR_HOST)/bin/padjffs2\nendef\n\n$(eval $(call HostBuild))\n"
  },
  {
    "path": "tools/padjffs2/src/Makefile",
    "content": "CC = gcc\nCFLAGS =\nWFLAGS = -Wall -Werror\npadjffs2-objs = padjffs2.o\n\nall: padjffs2\n\n%.o: %.c\n\t$(CC) $(CFLAGS) $(WFLAGS) -c -o $@ $<\n\npadjffs2: $(padjffs2-objs)\n\t$(CC) $(LDFLAGS) -o $@ $(padjffs2-objs)\n\nclean:\n\trm -f padjffs2 *.o\n"
  },
  {
    "path": "tools/padjffs2/src/padjffs2.c",
    "content": "/*\n * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>\n *\n * This program is free software; you can redistribute it and/or modify it\n * under the terms of the GNU General Public License version 2 as published\n * by the Free Software Foundation.\n *\n */\n\n#include <errno.h>\n#include <fcntl.h>\n#include <libgen.h>\n#include <stdio.h>\n#include <stdint.h>\n#include <stdlib.h>\n#include <string.h>\n#include <unistd.h>\n#include <stdbool.h>\n#include <sys/types.h>\n#include <sys/stat.h>\n\nstatic char *progname;\nstatic unsigned int xtra_offset;\nstatic unsigned char eof_mark[4] = {0xde, 0xad, 0xc0, 0xde};\nstatic unsigned char jffs2_pad_be[] = \"\\x19\\x85\\x20\\x04\\x04\\x00\\x00\\x00\\xc4\\x94\\xdb\\xf4\";\nstatic unsigned char jffs2_pad_le[] = \"\\x85\\x19\\x04\\x20\\x00\\x00\\x00\\x04\\xa8\\xfb\\xa0\\xb4\";\nstatic unsigned char *pad = eof_mark;\nstatic int pad_len = sizeof(eof_mark);\nstatic bool pad_to_stdout = false;\n\n#define ERR(fmt, ...) do { \\\n\tfflush(0); \\\n\tfprintf(stderr, \"[%s] *** error: \" fmt \"\\n\", \\\n\t\t\tprogname, ## __VA_ARGS__ ); \\\n} while (0)\n\n#define ERRS(fmt, ...) do { \\\n\tint save = errno; \\\n\tfflush(0); \\\n\tfprintf(stderr, \"[%s] *** error: \" fmt \", %s\\n\", \\\n\t\t\tprogname, ## __VA_ARGS__, strerror(save)); \\\n} while (0)\n\n#define BUF_SIZE\t(64 * 1024)\n#define ALIGN(_x,_y)\t(((_x) + ((_y) - 1)) & ~((_y) - 1))\n\nstatic int pad_image(char *name, uint32_t pad_mask)\n{\n\tchar *buf;\n\tint fd;\n\tint outfd;\n\tssize_t in_len;\n\tssize_t out_len;\n\tint ret = -1;\n\n\tbuf = malloc(BUF_SIZE);\n\tif (!buf) {\n\t\tERR(\"No memory for buffer\");\n\t\tgoto out;\n\t}\n\n\tfd = open(name, O_RDWR);\n\tif (fd < 0) {\n\t\tERRS(\"Unable to open %s\", name);\n\t\tgoto free_buf;\n\t}\n\n\tin_len = lseek(fd, 0, SEEK_END);\n\tif (in_len < 0)\n\t\tgoto close;\n\n\tif (!pad_to_stdout)\n\t\toutfd = fd;\n\telse\n\t\toutfd = STDOUT_FILENO;\n\n\tmemset(buf, '\\xff', BUF_SIZE);\n\n\tin_len += xtra_offset;\n\n\tout_len = in_len;\n\twhile (pad_mask) {\n\t\tuint32_t mask;\n\t\tssize_t t;\n\t\tint i;\n\n\t\tfor (i = 10; i < 32; i++) {\n\t\t\tmask = 1UL << i;\n\t\t\tif (pad_mask & mask)\n\t\t\t\tbreak;\n\t\t}\n\n\t\tin_len = ALIGN(in_len, mask);\n\n\t\tfor (i = 10; i < 32; i++) {\n\t\t\tmask = 1UL << i;\n\t\t\tif ((in_len & (mask - 1)) == 0)\n\t\t\t\tpad_mask &= ~mask;\n\t\t}\n\n\t\tfprintf(stderr, \"padding image to %08x\\n\", (unsigned int) in_len - xtra_offset);\n\n\t\twhile (out_len < in_len) {\n\t\t\tssize_t len;\n\n\t\t\tlen = in_len - out_len;\n\t\t\tif (len > BUF_SIZE)\n\t\t\t\tlen = BUF_SIZE;\n\n\t\t\tt = write(outfd, buf, len);\n\t\t\tif (t != len) {\n\t\t\t\tERRS(\"Unable to write to %s\", name);\n\t\t\t\tgoto close;\n\t\t\t}\n\n\t\t\tout_len += len;\n\t\t}\n\n\t\t/* write out the JFFS end-of-filesystem marker */\n\t\tt = write(outfd, pad, pad_len);\n\t\tif (t != pad_len) {\n\t\t\tERRS(\"Unable to write to %s\", name);\n\t\t\tgoto close;\n\t\t}\n\t\tout_len += pad_len;\n\t}\n\n\tret = 0;\n\nclose:\n\tclose(fd);\nfree_buf:\n\tfree(buf);\nout:\n\treturn ret;\n}\n\nstatic int usage(void)\n{\n\tfprintf(stderr,\n\t\t\"Usage: %s file [<options>] [pad0] [pad1] [padN]\\n\"\n\t\t\"Options:\\n\"\n\t\t\"  -x <offset>:          Add an extra offset for padding data\\n\"\n\t\t\"  -J:                   Use a fake big-endian jffs2 padding element instead of EOF\\n\"\n\t\t\"                        This is used to work around broken boot loaders that\\n\"\n\t\t\"                        try to parse the entire firmware area as one big jffs2\\n\"\n\t\t\"  -j:                   (like -J, but little-endian instead of big-endian)\\n\"\n\t\t\"  -c:                   write padding to stdout\\n\"\n\t\t\"\\n\",\n\t\tprogname);\n\treturn EXIT_FAILURE;\n}\n\nint main(int argc, char* argv[])\n{\n\tchar *image;\n\tuint32_t pad_mask;\n\tint ret = EXIT_FAILURE;\n\tint err;\n\tint ch, i;\n\n\tprogname = basename(argv[0]);\n\n\tif (argc < 2)\n\t\treturn usage();\n\n\timage = argv[1];\n\targv++;\n\targc--;\n\n\tpad_mask = 0;\n\twhile ((ch = getopt(argc, argv, \"x:Jjc\")) != -1) {\n\t\tswitch (ch) {\n\t\tcase 'x':\n\t\t\txtra_offset = strtoul(optarg, NULL, 0);\n\t\t\tfprintf(stderr, \"assuming %u bytes offset\\n\",\n\t\t\t\txtra_offset);\n\t\t\tbreak;\n\t\tcase 'J':\n\t\t\tpad = jffs2_pad_be;\n\t\t\tpad_len = sizeof(jffs2_pad_be) - 1;\n\t\t\tbreak;\n\t\tcase 'j':\n\t\t\tpad = jffs2_pad_le;\n\t\t\tpad_len = sizeof(jffs2_pad_le) - 1;\n\t\t\tbreak;\n\t\tcase 'c':\n\t\t\tpad_to_stdout = true;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\treturn usage();\n\t\t}\n\t}\n\n\tfor (i = optind; i < argc; i++)\n\t\tpad_mask |= strtoul(argv[i], NULL, 0) * 1024;\n\n\tif (pad_mask == 0)\n\t\tpad_mask = (4 * 1024) | (8 * 1024) | (64 * 1024) |\n\t\t\t   (128 * 1024);\n\n\terr = pad_image(image, pad_mask);\n\tif (err)\n\t\tgoto out;\n\n\tret = EXIT_SUCCESS;\n\nout:\n\treturn ret;\n}\n"
  },
  {
    "path": "tools/patch/Makefile",
    "content": "# \n# Copyright (C) 2013 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=patch\nPKG_VERSION:=2.7.6\nPKG_RELEASE:=6\nPKG_CPE_ID:=cpe:/a:gnu:patch\n\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz\nPKG_SOURCE_URL:=@GNU/patch\nPKG_HASH:=ac610bda97abe0d9f6b7c963255a11dcb196c25e337c61f94e4778d632f1d8fd\n\nHOST_BUILD_PARALLEL := 1\n\ninclude $(INCLUDE_DIR)/host-build.mk\n\nHOSTCC := $(HOSTCC_NOCACHE)\nHOSTCXX := $(HOSTCXX_NOCACHE)\n\n$(eval $(call HostBuild))\n"
  },
  {
    "path": "tools/patch/patches/010-CVE-2018-6951.patch",
    "content": "From 1f7853c05f9949d81da9be7a02b90cc64284d1f8 Mon Sep 17 00:00:00 2001\nFrom: Andreas Gruenbacher <agruen@gnu.org>\nDate: Mon, 12 Feb 2018 16:48:24 +0100\nSubject: [PATCH] Fix segfault with mangled rename patch\n\nhttp://savannah.gnu.org/bugs/?53132\n* src/pch.c (intuit_diff_type): Ensure that two filenames are specified\nfor renames and copies (fix the existing check).\n---\n src/pch.c | 3 ++-\n 1 file changed, 2 insertions(+), 1 deletion(-)\n\n--- a/src/pch.c\n+++ b/src/pch.c\n@@ -974,7 +974,8 @@ intuit_diff_type (bool need_header, mode\n     if ((pch_rename () || pch_copy ())\n \t&& ! inname\n \t&& ! ((i == OLD || i == NEW) &&\n-\t      p_name[! reverse] &&\n+\t      p_name[reverse] && p_name[! reverse] &&\n+\t      name_is_valid (p_name[reverse]) &&\n \t      name_is_valid (p_name[! reverse])))\n       {\n \tsay (\"Cannot %s file without two valid file names\\n\", pch_rename () ? \"rename\" : \"copy\");\n"
  },
  {
    "path": "tools/patch/patches/020-CVE-2018-1000156.patch",
    "content": "From b3a0ca3deed00334f9feece43f76776b6a168e47 Mon Sep 17 00:00:00 2001\nFrom: Andreas Gruenbacher <agruen@gnu.org>\nDate: Fri, 6 Apr 2018 12:14:49 +0200\nSubject: [PATCH] Fix arbitrary command execution in ed-style patches\n (CVE-2018-1000156)\n\n* src/pch.c (do_ed_script): Write ed script to a temporary file instead\nof piping it to ed: this will cause ed to abort on invalid commands\ninstead of rejecting them and carrying on.\n* tests/ed-style: New test case.\n* tests/Makefile.am (TESTS): Add test case.\n---\n src/pch.c | 89 +++++++++++++++++++++++++++++++++++++++++--------------\n 1 file changed, 66 insertions(+), 23 deletions(-)\n\n--- a/src/pch.c\n+++ b/src/pch.c\n@@ -33,6 +33,7 @@\n # include <io.h>\n #endif\n #include <safe.h>\n+#include <sys/wait.h>\n \n #define INITHUNKMAX 125\t\t\t/* initial dynamic allocation size */\n \n@@ -2389,22 +2390,28 @@ do_ed_script (char const *inname, char c\n     static char const editor_program[] = EDITOR_PROGRAM;\n \n     file_offset beginning_of_this_line;\n-    FILE *pipefp = 0;\n     size_t chars_read;\n+    FILE *tmpfp = 0;\n+    char const *tmpname;\n+    int tmpfd;\n+    pid_t pid;\n+\n+    if (! dry_run && ! skip_rest_of_patch)\n+      {\n+\t/* Write ed script to a temporary file.  This causes ed to abort on\n+\t   invalid commands such as when line numbers or ranges exceed the\n+\t   number of available lines.  When ed reads from a pipe, it rejects\n+\t   invalid commands and treats the next line as a new command, which\n+\t   can lead to arbitrary command execution.  */\n+\n+\ttmpfd = make_tempfile (&tmpname, 'e', NULL, O_RDWR | O_BINARY, 0);\n+\tif (tmpfd == -1)\n+\t  pfatal (\"Can't create temporary file %s\", quotearg (tmpname));\n+\ttmpfp = fdopen (tmpfd, \"w+b\");\n+\tif (! tmpfp)\n+\t  pfatal (\"Can't open stream for file %s\", quotearg (tmpname));\n+      }\n \n-    if (! dry_run && ! skip_rest_of_patch) {\n-\tint exclusive = *outname_needs_removal ? 0 : O_EXCL;\n-\tassert (! inerrno);\n-\t*outname_needs_removal = true;\n-\tcopy_file (inname, outname, 0, exclusive, instat.st_mode, true);\n-\tsprintf (buf, \"%s %s%s\", editor_program,\n-\t\t verbosity == VERBOSE ? \"\" : \"- \",\n-\t\t outname);\n-\tfflush (stdout);\n-\tpipefp = popen(buf, binary_transput ? \"wb\" : \"w\");\n-\tif (!pipefp)\n-\t  pfatal (\"Can't open pipe to %s\", quotearg (buf));\n-    }\n     for (;;) {\n \tchar ed_command_letter;\n \tbeginning_of_this_line = file_tell (pfp);\n@@ -2415,14 +2422,14 @@ do_ed_script (char const *inname, char c\n \t}\n \ted_command_letter = get_ed_command_letter (buf);\n \tif (ed_command_letter) {\n-\t    if (pipefp)\n-\t\tif (! fwrite (buf, sizeof *buf, chars_read, pipefp))\n+\t    if (tmpfp)\n+\t\tif (! fwrite (buf, sizeof *buf, chars_read, tmpfp))\n \t\t    write_fatal ();\n \t    if (ed_command_letter != 'd' && ed_command_letter != 's') {\n \t        p_pass_comments_through = true;\n \t\twhile ((chars_read = get_line ()) != 0) {\n-\t\t    if (pipefp)\n-\t\t\tif (! fwrite (buf, sizeof *buf, chars_read, pipefp))\n+\t\t    if (tmpfp)\n+\t\t\tif (! fwrite (buf, sizeof *buf, chars_read, tmpfp))\n \t\t\t    write_fatal ();\n \t\t    if (chars_read == 2  &&  strEQ (buf, \".\\n\"))\n \t\t\tbreak;\n@@ -2435,13 +2442,49 @@ do_ed_script (char const *inname, char c\n \t    break;\n \t}\n     }\n-    if (!pipefp)\n+    if (!tmpfp)\n       return;\n-    if (fwrite (\"w\\nq\\n\", sizeof (char), (size_t) 4, pipefp) == 0\n-\t|| fflush (pipefp) != 0)\n+    if (fwrite (\"w\\nq\\n\", sizeof (char), (size_t) 4, tmpfp) == 0\n+\t|| fflush (tmpfp) != 0)\n       write_fatal ();\n-    if (pclose (pipefp) != 0)\n-      fatal (\"%s FAILED\", editor_program);\n+\n+    if (lseek (tmpfd, 0, SEEK_SET) == -1)\n+      pfatal (\"Can't rewind to the beginning of file %s\", quotearg (tmpname));\n+\n+    if (! dry_run && ! skip_rest_of_patch) {\n+\tint exclusive = *outname_needs_removal ? 0 : O_EXCL;\n+\t*outname_needs_removal = true;\n+\tif (inerrno != ENOENT)\n+\t  {\n+\t    *outname_needs_removal = true;\n+\t    copy_file (inname, outname, 0, exclusive, instat.st_mode, true);\n+\t  }\n+\tsprintf (buf, \"%s %s%s\", editor_program,\n+\t\t verbosity == VERBOSE ? \"\" : \"- \",\n+\t\t outname);\n+\tfflush (stdout);\n+\n+\tpid = fork();\n+\tif (pid == -1)\n+\t  pfatal (\"Can't fork\");\n+\telse if (pid == 0)\n+\t  {\n+\t    dup2 (tmpfd, 0);\n+\t    execl (\"/bin/sh\", \"sh\", \"-c\", buf, (char *) 0);\n+\t    _exit (2);\n+\t  }\n+\telse\n+\t  {\n+\t    int wstatus;\n+\t    if (waitpid (pid, &wstatus, 0) == -1\n+\t        || ! WIFEXITED (wstatus)\n+\t\t|| WEXITSTATUS (wstatus) != 0)\n+\t      fatal (\"%s FAILED\", editor_program);\n+\t  }\n+    }\n+\n+    fclose (tmpfp);\n+    safe_unlink (tmpname);\n \n     if (ofp)\n       {\n"
  },
  {
    "path": "tools/patch/patches/030-CVE-2018-6952.patch",
    "content": "From df40f2ea17254de269a3624319a12a93a4e395ff Mon Sep 17 00:00:00 2001\nFrom: Andreas Gruenbacher <agruen@gnu.org>\nDate: Fri, 17 Aug 2018 13:35:40 +0200\nSubject: [PATCH] Fix swapping fake lines in pch_swap\n\n* src/pch.c (pch_swap): Fix swapping p_bfake and p_efake when there is a\nblank line in the middle of a context-diff hunk: that empty line stays\nin the middle of the hunk and isn't swapped.\n\nFixes: https://savannah.gnu.org/bugs/index.php?53133\n---\n src/pch.c | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/src/pch.c\n+++ b/src/pch.c\n@@ -2115,7 +2115,7 @@ pch_swap (void)\n     }\n     if (p_efake >= 0) {\t\t\t/* fix non-freeable ptr range */\n \tif (p_efake <= i)\n-\t    n = p_end - i + 1;\n+\t    n = p_end - p_ptrn_lines;\n \telse\n \t    n = -i;\n \tp_efake += n;\n"
  },
  {
    "path": "tools/patch/patches/040-Fix-error-handling-with-git-style-patches.patch",
    "content": "From 424da221cec76ea200cff1fa9b08a6f3d94c28a7 Mon Sep 17 00:00:00 2001\nFrom: Lubomir Rintel <lkundrak@v3.sk>\nDate: Wed, 31 Oct 2018 16:39:13 -0700\nSubject: [PATCH] Fix error handling with git-style patches\n\nWhen an error is encountered in output_files(), the subsequent call to\ncleanup() calls back into output_files() resulting in an infinte recursion.\nThis is trivially reproduced with a git-style patch (which utilizes\noutput_file_later()) that tries to patch a nonexistent or unreadable\nfile (see attached test case).\n\n* src/patch.c: (output_files) clear the files_to_output list before\niterating it, so that recursive calls won't iterate the same files.\n---\n src/patch.c | 12 ++++++++----\n 1 file changed, 8 insertions(+), 4 deletions(-)\n\n--- a/src/patch.c\n+++ b/src/patch.c\n@@ -1938,8 +1938,12 @@ output_files (struct stat const *st)\n {\n   gl_list_iterator_t iter;\n   const void *elt;\n+  gl_list_t files;\n \n-  iter = gl_list_iterator (files_to_output);\n+  files = files_to_output;\n+  init_files_to_output ();\n+\n+  iter = gl_list_iterator (files);\n   while (gl_list_iterator_next (&iter, &elt, NULL))\n     {\n       const struct file_to_output *file_to_output = elt;\n@@ -1957,8 +1961,8 @@ output_files (struct stat const *st)\n \t  /* Free the list up to here. */\n \t  for (;;)\n \t    {\n-\t      const void *elt2 = gl_list_get_at (files_to_output, 0);\n-\t      gl_list_remove_at (files_to_output, 0);\n+\t      const void *elt2 = gl_list_get_at (files, 0);\n+\t      gl_list_remove_at (files, 0);\n \t      if (elt == elt2)\n \t\tbreak;\n \t    }\n@@ -1967,7 +1971,7 @@ output_files (struct stat const *st)\n \t}\n     }\n   gl_list_iterator_free (&iter);\n-  gl_list_clear (files_to_output);\n+  gl_list_clear (files);\n }\n \n /* Fatal exit with cleanup. */\n"
  },
  {
    "path": "tools/patch/patches/050-CVE-2019-13636.patch",
    "content": "From dce4683cbbe107a95f1f0d45fabc304acfb5d71a Mon Sep 17 00:00:00 2001\nFrom: Andreas Gruenbacher <agruen@gnu.org>\nDate: Mon, 15 Jul 2019 16:21:48 +0200\nSubject: Don't follow symlinks unless --follow-symlinks is given\n\n* src/inp.c (plan_a, plan_b), src/util.c (copy_to_fd, copy_file,\nappend_to_file): Unless the --follow-symlinks option is given, open files with\nthe O_NOFOLLOW flag to avoid following symlinks.  So far, we were only doing\nthat consistently for input files.\n* src/util.c (create_backup): When creating empty backup files, (re)create them\nwith O_CREAT | O_EXCL to avoid following symlinks in that case as well.\n---\n src/inp.c  | 12 ++++++++++--\n src/util.c | 14 +++++++++++---\n 2 files changed, 21 insertions(+), 5 deletions(-)\n\ndiff --git a/src/inp.c b/src/inp.c\nindex 32d0919..22d7473 100644\n--- a/src/inp.c\n+++ b/src/inp.c\n@@ -238,8 +238,13 @@ plan_a (char const *filename)\n     {\n       if (S_ISREG (instat.st_mode))\n         {\n-\t  int ifd = safe_open (filename, O_RDONLY|binary_transput, 0);\n+\t  int flags = O_RDONLY | binary_transput;\n \t  size_t buffered = 0, n;\n+\t  int ifd;\n+\n+\t  if (! follow_symlinks)\n+\t    flags |= O_NOFOLLOW;\n+\t  ifd = safe_open (filename, flags, 0);\n \t  if (ifd < 0)\n \t    pfatal (\"can't open file %s\", quotearg (filename));\n \n@@ -340,6 +345,7 @@ plan_a (char const *filename)\n static void\n plan_b (char const *filename)\n {\n+  int flags = O_RDONLY | binary_transput;\n   int ifd;\n   FILE *ifp;\n   int c;\n@@ -353,7 +359,9 @@ plan_b (char const *filename)\n \n   if (instat.st_size == 0)\n     filename = NULL_DEVICE;\n-  if ((ifd = safe_open (filename, O_RDONLY | binary_transput, 0)) < 0\n+  if (! follow_symlinks)\n+    flags |= O_NOFOLLOW;\n+  if ((ifd = safe_open (filename, flags, 0)) < 0\n       || ! (ifp = fdopen (ifd, binary_transput ? \"rb\" : \"r\")))\n     pfatal (\"Can't open file %s\", quotearg (filename));\n   if (TMPINNAME_needs_removal)\ndiff --git a/src/util.c b/src/util.c\nindex 1cc08ba..fb38307 100644\n--- a/src/util.c\n+++ b/src/util.c\n@@ -388,7 +388,7 @@ create_backup (char const *to, const struct stat *to_st, bool leave_original)\n \n \t  try_makedirs_errno = ENOENT;\n \t  safe_unlink (bakname);\n-\t  while ((fd = safe_open (bakname, O_CREAT | O_WRONLY | O_TRUNC, 0666)) < 0)\n+\t  while ((fd = safe_open (bakname, O_CREAT | O_EXCL | O_WRONLY | O_TRUNC, 0666)) < 0)\n \t    {\n \t      if (errno != try_makedirs_errno)\n \t\tpfatal (\"Can't create file %s\", quotearg (bakname));\n@@ -579,10 +579,13 @@ create_file (char const *file, int open_flags, mode_t mode,\n static void\n copy_to_fd (const char *from, int tofd)\n {\n+  int from_flags = O_RDONLY | O_BINARY;\n   int fromfd;\n   ssize_t i;\n \n-  if ((fromfd = safe_open (from, O_RDONLY | O_BINARY, 0)) < 0)\n+  if (! follow_symlinks)\n+    from_flags |= O_NOFOLLOW;\n+  if ((fromfd = safe_open (from, from_flags, 0)) < 0)\n     pfatal (\"Can't reopen file %s\", quotearg (from));\n   while ((i = read (fromfd, buf, bufsize)) != 0)\n     {\n@@ -625,6 +628,8 @@ copy_file (char const *from, char const *to, struct stat *tost,\n   else\n     {\n       assert (S_ISREG (mode));\n+      if (! follow_symlinks)\n+\tto_flags |= O_NOFOLLOW;\n       tofd = create_file (to, O_WRONLY | O_BINARY | to_flags, mode,\n \t\t\t  to_dir_known_to_exist);\n       copy_to_fd (from, tofd);\n@@ -640,9 +645,12 @@ copy_file (char const *from, char const *to, struct stat *tost,\n void\n append_to_file (char const *from, char const *to)\n {\n+  int to_flags = O_WRONLY | O_APPEND | O_BINARY;\n   int tofd;\n \n-  if ((tofd = safe_open (to, O_WRONLY | O_BINARY | O_APPEND, 0)) < 0)\n+  if (! follow_symlinks)\n+    to_flags |= O_NOFOLLOW;\n+  if ((tofd = safe_open (to, to_flags, 0)) < 0)\n     pfatal (\"Can't reopen file %s\", quotearg (to));\n   copy_to_fd (from, tofd);\n   if (close (tofd) != 0)\n-- \ncgit v1.0-41-gc330\n\n"
  },
  {
    "path": "tools/patch/patches/060-CVE-2019-13638.patch",
    "content": "From 3fcd042d26d70856e826a42b5f93dc4854d80bf0 Mon Sep 17 00:00:00 2001\nFrom: Andreas Gruenbacher <agruen@gnu.org>\nDate: Fri, 6 Apr 2018 19:36:15 +0200\nSubject: Invoke ed directly instead of using the shell\n\n* src/pch.c (do_ed_script): Invoke ed directly instead of using a shell\ncommand to avoid quoting vulnerabilities.\n---\n src/pch.c | 6 ++----\n 1 file changed, 2 insertions(+), 4 deletions(-)\n\ndiff --git a/src/pch.c b/src/pch.c\nindex 4fd5a05..16e001a 100644\n--- a/src/pch.c\n+++ b/src/pch.c\n@@ -2459,9 +2459,6 @@ do_ed_script (char const *inname, char const *outname,\n \t    *outname_needs_removal = true;\n \t    copy_file (inname, outname, 0, exclusive, instat.st_mode, true);\n \t  }\n-\tsprintf (buf, \"%s %s%s\", editor_program,\n-\t\t verbosity == VERBOSE ? \"\" : \"- \",\n-\t\t outname);\n \tfflush (stdout);\n \n \tpid = fork();\n@@ -2470,7 +2467,8 @@ do_ed_script (char const *inname, char const *outname,\n \telse if (pid == 0)\n \t  {\n \t    dup2 (tmpfd, 0);\n-\t    execl (\"/bin/sh\", \"sh\", \"-c\", buf, (char *) 0);\n+\t    assert (outname[0] != '!' && outname[0] != '-');\n+\t    execlp (editor_program, editor_program, \"-\", outname, (char  *) NULL);\n \t    _exit (2);\n \t  }\n \telse\n-- \ncgit v1.0-41-gc330\n\n"
  },
  {
    "path": "tools/patch-image/Makefile",
    "content": "# \n# Copyright (C) 2007-2020 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=patch-image\nPKG_RELEASE:=1\n\ninclude $(INCLUDE_DIR)/host-build.mk\n\ndefine Host/Compile\n\t$(HOSTCC) $(HOST_CFLAGS) -include endian.h -o $(HOST_BUILD_DIR)/patch-cmdline src/patch-cmdline.c\n\t$(HOSTCC) $(HOST_CFLAGS) -include endian.h -o $(HOST_BUILD_DIR)/patch-dtb src/patch-dtb.c\nendef\n\ndefine Host/Install\n\t$(CP) $(HOST_BUILD_DIR)/patch-cmdline $(STAGING_DIR_HOST)/bin/\n\t$(CP) $(HOST_BUILD_DIR)/patch-dtb $(STAGING_DIR_HOST)/bin/\nendef\n\ndefine Host/Clean\n\trm -f $(STAGING_DIR_HOST)/bin/patch-cmdline\n\trm -f $(STAGING_DIR_HOST)/bin/patch-dtb\nendef\n\n$(eval $(call HostBuild))\n"
  },
  {
    "path": "tools/patch-image/src/patch-cmdline.c",
    "content": "/*\n * patch-cmdline.c - patch the kernel command line\n *\n * Copyright (C) 2006 Felix Fietkau <nbd@nbd.name>\n *\n * This program is free software; you can redistribute it and/or\n * modify it under the terms of the GNU General Public License\n * as published by the Free Software Foundation; either version 2\n * of the License, or (at your option) any later version.\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n * GNU General Public License for more details.\n *\n * You should have received a copy of the GNU General Public License\n * along with this program; if not, write to the Free Software\n * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.\n *\n */\n\n#include <stdio.h>\n#include <stdlib.h>\n#include <stddef.h>\n#include <unistd.h>\n#include <fcntl.h>\n#include <sys/mman.h>\n#include <sys/stat.h>\n#include <string.h>\n\n#define SEARCH_SPACE\t(16 * 1024)\n#define CMDLINE_MAX\t\t512\n\nint main(int argc, char **argv)\n{\n\tint fd, found = 0, len, ret = -1;\n\tchar *ptr, *p;\n\tunsigned int search_space;\n\n\tif (argc <= 2 || argc > 4) {\n\t\tfprintf(stderr, \"Usage: %s <file> <cmdline> [size]\\n\", argv[0]);\n\t\tgoto err1;\n\t} else if (argc == 3) {\n\t\tfprintf(stdout, \"search space used is default of 16KB\\n\");\n\t\tsearch_space = SEARCH_SPACE;\n\t} else {\n\t\tsearch_space = atoi(argv[3]);\n\t}\n\tlen = strlen(argv[2]);\n\tif (len + 9 > CMDLINE_MAX) {\n\t\tfprintf(stderr, \"Command line string too long\\n\");\n\t\tgoto err1;\n\t}\n\t\n\tif (((fd = open(argv[1], O_RDWR)) < 0) ||\n\t\t(ptr = (char *) mmap(0, search_space + CMDLINE_MAX, PROT_READ|PROT_WRITE, MAP_SHARED, fd, 0)) == (void *) (-1)) {\n\t\tfprintf(stderr, \"Could not open kernel image\");\n\t\tgoto err2;\n\t}\n\t\n\tfor (p = ptr; p < (ptr + search_space); p += 4) {\n\t\tif (memcmp(p, \"CMDLINE:\", 8) == 0) {\n\t\t\tfound = 1;\n\t\t\tp += 8;\n\t\t\tbreak;\n\t\t}\n\t}\n\tif (!found) {\n\t\tfprintf(stderr, \"Command line marker not found!\\n\");\n\t\tgoto err3;\n\t}\n\n\tmemset(p, 0, CMDLINE_MAX - 8);\n\tstrcpy(p, argv[2]);\n\tmsync(p, CMDLINE_MAX, MS_SYNC|MS_INVALIDATE);\n\tret = 0;\n\nerr3:\n\tmunmap((void *) ptr, len);\nerr2:\n\tif (fd > 0)\n\t\tclose(fd);\nerr1:\n\treturn ret;\n}\n"
  },
  {
    "path": "tools/patch-image/src/patch-dtb.c",
    "content": "/*\n * patch-dtb.c - patch a dtb into an image\n *\n * Copyright (C) 2006 Felix Fietkau <nbd@nbd.name>\n * Copyright (C) 2012 John Crispin <blogic@openwrt.org>\n *\n * This program is free software; you can redistribute it and/or\n * modify it under the terms of the GNU General Public License\n * as published by the Free Software Foundation; either version 2\n * of the License, or (at your option) any later version.\n *\n * This program is distributed in the hope that it will be useful,\n * but WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n * GNU General Public License for more details.\n *\n * You should have received a copy of the GNU General Public License\n * along with this program; if not, write to the Free Software\n * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.\n *\n * based on patch-cmdline.c\n */\n\n#include <stdio.h>\n#include <stdlib.h>\n#include <stddef.h>\n#include <unistd.h>\n#include <fcntl.h>\n#include <sys/mman.h>\n#include <sys/stat.h>\n#include <string.h>\n\n#define DTB_MAX\t(16 * 1024)\n\nint main(int argc, char **argv)\n{\n\tint fd, fddtb, found = 0, len, ret = -1;\n\tchar *ptr, *ptrdtb, *p;\n\tstruct stat s;\n\tunsigned int search_space , dtb_max_size;\n\n\tif (argc <= 2 || argc > 4) {\n\t\tfprintf(stderr, \"Usage: %s <file> <dtb> [size]\\n\", argv[0]);\n\t\tgoto err1;\n\t} else if (argc == 3) {\n\t\tfprintf(stdout, \"DT size used is default of 16KB\\n\");\n\t\tsearch_space = dtb_max_size = DTB_MAX;\n\t} else {\n\t\tsearch_space = dtb_max_size = atoi(argv[3]);\n\t}\n\n\tif (stat(argv[2], &s)) {\n\t\tfprintf(stderr, \"DTB not found\\n\");\n\t\tgoto err1;\n\t}\n\n\tlen = s.st_size;\n\tif (len + 8 > dtb_max_size) {\n\t\tfprintf(stderr, \"DTB too big\\n\");\n\t\tgoto err1;\n\t}\n\n        if (((fddtb = open(argv[2], O_RDONLY)) < 0) ||\n\t\t(ptrdtb = (char *) mmap(0, dtb_max_size, PROT_READ, MAP_SHARED, fddtb, 0)) == (void *) (-1)) {\n\t\tfprintf(stderr, \"Could not open DTB\");\n\t\tgoto err2;\n\t}\n\n\tif (((fd = open(argv[1], O_RDWR)) < 0) ||\n\t\t(ptr = (char *) mmap(0, search_space + dtb_max_size, PROT_READ|PROT_WRITE, MAP_SHARED, fd, 0)) == (void *) (-1)) {\n\t\tfprintf(stderr, \"Could not open kernel image\");\n\t\tgoto err3;\n\t}\n\n\tfor (p = ptr; p < (ptr + search_space); p += 4) {\n\t\tif (memcmp(p, \"OWRTDTB:\", 8) == 0) {\n\t\t\tfound = 1;\n\t\t\tp += 8;\n\t\t\tbreak;\n\t\t}\n\t}\n\tif (!found) {\n\t\tfprintf(stderr, \"DTB marker not found!\\n\");\n\t\tgoto err4;\n\t}\n\n\tmemset(p, 0, dtb_max_size - 8);\n\tmemcpy(p, ptrdtb, len);\n\tmsync(p, len, MS_SYNC|MS_INVALIDATE);\n\tret = 0;\n\nerr4:\n\tmunmap((void *) ptr, len);\nerr3:\n\tif (fd > 0)\n\t\tclose(fd);\n\tmunmap((void *) ptrdtb, len);\nerr2:\n\tif (fddtb > 0)\n\t\tclose(fddtb);\nerr1:\n\treturn ret;\n}\n"
  },
  {
    "path": "tools/patchelf/Makefile",
    "content": "# \n# Copyright (C) 2015 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=patchelf\n\nPKG_SOURCE_PROTO:=git\nPKG_SOURCE_URL:=https://github.com/NixOS/patchelf.git\nPKG_SOURCE_VERSION:=f34751b88bd07d7f44f5cd3200fb4122bf916c7e\nPKG_SOURCE_DATE:=2020-12-07\nPKG_MIRROR_HASH:=ac746930b919b97da40f259cfc9ab7bbd48a0c9cbf2eebd8cee5ae19a94356fd\n\nHOST_BUILD_PARALLEL:=1\nHOST_FIXUP:=autoreconf\n\ninclude $(INCLUDE_DIR)/host-build.mk\n\ndefine Host/Install\n\t$(INSTALL_DIR) $(STAGING_DIR_HOST)/bin\n\t$(INSTALL_BIN) $(HOST_BUILD_DIR)/src/patchelf $(STAGING_DIR_HOST)/bin/patchelf\nendef\n\n$(eval $(call HostBuild))\n"
  },
  {
    "path": "tools/pkgconf/Makefile",
    "content": "#\n# Copyright (C) 2006-2016 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=pkgconf\nPKG_VERSION:=1.8.0\n\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz\nPKG_SOURCE_URL:=https://distfiles.dereferenced.org/pkgconf\nPKG_HASH:=ef9c7e61822b7cb8356e6e9e1dca58d9556f3200d78acab35e4347e9d4c2bbaf\n\ninclude $(INCLUDE_DIR)/host-build.mk\ninclude $(INCLUDE_DIR)/meson.mk\n\nunexport PKG_CONFIG\n\nHOSTCC := $(HOSTCC_NOCACHE)\n\nMESON_HOST_ARGS += \\\n\t-Ddefault_library=static \\\n\t-Dtests=false\n\ndefine Host/Install\n\t$(call Host/Install/Meson)\n\tmv $(STAGING_DIR_HOST)/bin/pkgconf $(STAGING_DIR_HOST)/bin/pkg-config.real\n\t$(INSTALL_BIN) ./files/pkg-config $(STAGING_DIR_HOST)/bin/pkg-config\nendef\n\ndefine Host/Clean\n\trm -f $(STAGING_DIR_HOST)/bin/pkg-config.real $(STAGING_DIR_HOST)/bin/pkg-config\n\t$(call Host/Clean/Meson)\nendef\n\n$(eval $(call HostBuild))\n"
  },
  {
    "path": "tools/pkgconf/files/pkg-config",
    "content": "#!/bin/sh\n\npkg-config.real \\\n--keep-system-cflags \\\n--keep-system-libs \\\n--define-variable=prefix=\"${STAGING_PREFIX}\" \\\n--define-variable=exec_prefix=\"${STAGING_PREFIX}\" \\\n--define-variable=bindir=\"${STAGING_PREFIX}/bin\" \\\n$PKG_CONFIG_EXTRAARGS \"$@\"\n"
  },
  {
    "path": "tools/quilt/Makefile",
    "content": "# \n# Copyright (C) 2006-2015 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=quilt\nPKG_VERSION:=0.67\n\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz\nPKG_SOURCE_URL:=@SAVANNAH/quilt\nPKG_HASH:=3be3be0987e72a6c364678bb827e3e1fcc10322b56bc5f02b576698f55013cc2\n\ninclude $(INCLUDE_DIR)/host-build.mk\n\ndefine Host/Configure\n\tcd $(HOST_BUILD_DIR) && autoconf\n\t$(call Host/Configure/Default)\n\t[ -f $(HOST_BUILD_DIR)/Makefile ]\nendef\n\ndefine Host/Compile\n\t$(MAKE) -C $(HOST_BUILD_DIR) SHELL=\"$(BASH)\" all\nendef\n\ndefine Host/Install\n\t$(MAKE) -C $(HOST_BUILD_DIR) SHELL=\"$(BASH)\" install\nendef\n\ndefine Host/Clean\n\trm -f $(STAGING_DIR_HOST)/bin/quilt\nendef\n\n$(eval $(call HostBuild))\n"
  },
  {
    "path": "tools/quilt/patches/000-relocatable.patch",
    "content": "--- a/bin/quilt.in\n+++ b/bin/quilt.in\n@@ -15,14 +15,22 @@ unset POSIXLY_CORRECT\n unset GREP_OPTIONS\n \n export TEXTDOMAIN=quilt\n-export TEXTDOMAINDIR=@LOCALEDIR@\n \n-: ${QUILT_DIR=@QUILT_DIR@}\n+if test -n \"$STAGING_DIR_HOST\"; then\n+\texport TEXTDOMAINDIR=\"$STAGING_DIR_HOST/share/locale\"\n+\t: ${QUILT_DIR=$STAGING_DIR_HOST/share/quilt} ${QUILT_LIB=$STAGING_DIR_HOST/lib/quilt}\n+\t: ${QUILT_ETC=$STAGING_DIR_HOST/etc}\n+else\n+\texport TEXTDOMAINDIR=@LOCALEDIR@\n+\t: ${QUILT_DIR=@QUILT_DIR@}\n+\t: ${QUILT_ETC=@ETCDIR@}\n+fi\n+\n export QUILT_DIR\n \n if [ -z \"$QUILTRC\" ]\n then\n-\tfor QUILTRC in $HOME/.quiltrc @ETCDIR@/quilt.quiltrc; do\n+\tfor QUILTRC in $HOME/.quiltrc $QUILT_ETC/quilt.quiltrc; do\n \t\t[ -e $QUILTRC ] && break\n \tdone\n \texport QUILTRC\n--- a/quilt/scripts/edmail.in\n+++ b/quilt/scripts/edmail.in\n@@ -1,4 +1,6 @@\n-#! @PERL@ -w\n+#! @PERL@\n+\n+use warnings;\n \n # RFCs important for this script:\n #\n@@ -29,7 +31,7 @@ BEGIN {\n }\n \n setlocale(LC_MESSAGES, \"\");\n-bindtextdomain(\"quilt\", \"@LOCALEDIR@\");\n+bindtextdomain(\"quilt\", $ENV{'STAGING_DIR_HOST'} ? $ENV{'STAGING_DIR_HOST'} . '/share/locale' : \"@LOCALEDIR@\");\n textdomain(\"quilt\");\n \n sub _($) {\n--- a/quilt/scripts/patchfns.in\n+++ b/quilt/scripts/patchfns.in\n@@ -8,7 +8,11 @@\n #  See the COPYING and AUTHORS files for more details.\n \n export TEXTDOMAIN=quilt\n-export TEXTDOMAINDIR=@LOCALEDIR@\n+if [ -n \"$STAGING_DIR_HOST\" ]; then\n+\texport TEXTDOMAINDIR=\"$STAGING_DIR_HOST/share/locale\"\n+else\n+\texport TEXTDOMAINDIR=@LOCALEDIR@\n+fi\n \n : ${LC_CTYPE:=$LANG}\n : ${LC_MESSAGES:=$LANG}\n--- a/quilt/scripts/remove-trailing-ws.in\n+++ b/quilt/scripts/remove-trailing-ws.in\n@@ -1,4 +1,6 @@\n-#! @PERL@ -w\n+#! @PERL@\n+\n+use warnings;\n \n # Remove trailing whitespace from modified lines in working files.\n #\n@@ -31,7 +33,7 @@ BEGIN {\n }\n \n setlocale(LC_MESSAGES, \"\");\n-bindtextdomain(\"quilt\", \"@LOCALEDIR@\");\n+bindtextdomain(\"quilt\", $ENV{'STAGING_DIR_HOST'} ? $ENV{'STAGING_DIR_HOST'} . '/share/locale' : \"@LOCALEDIR@\");\n textdomain(\"quilt\");\n \n sub _($) {\n--- a/Makefile.in\n+++ b/Makefile.in\n@@ -21,8 +21,8 @@ COLUMN :=\t@COLUMN@\n GETOPT :=\t@GETOPT@\n CP :=\t\t@CP@\n DATE :=\t\t@DATE@\n-PERL :=\t\t@PERL@\n-BASH :=\t\t@BASH@\n+PERL :=\t\t/usr/bin/env perl\n+BASH :=\t\t/usr/bin/env bash\n SHELL:=\t\t@BASH@ # It does not work if dash is used as a shell, for example\n GREP :=\t\t@GREP@\n TAIL :=\t\t@TAIL@\n@@ -33,7 +33,7 @@ AWK :=\t\t@AWK@\n FIND :=\t\t@FIND@\n XARGS :=\t@XARGS@\n DIFF :=\t\t@DIFF@\n-PATCH :=\t@PATCH@\n+PATCH :=\t/usr/bin/env patch\n MKTEMP :=\t@MKTEMP@\n MSGMERGE :=\t@MSGMERGE@\n MSGFMT :=\t@MSGFMT@\n@@ -50,8 +50,8 @@ USE_NLS :=\t@USE_NLS@\n STAT_HARDLINK := @STAT_HARDLINK@\n PATCH_WRAPPER := @PATCH_WRAPPER@\n \n-COMPAT_SYMLINKS\t:= @COMPAT_SYMLINKS@\n-COMPAT_PROGRAMS\t:= @COMPAT_PROGRAMS@\n+COMPAT_SYMLINKS\t:=\n+COMPAT_PROGRAMS\t:=\n \n default: all\n \n--- a/quilt/scripts/backup-files.in\n+++ b/quilt/scripts/backup-files.in\n@@ -53,7 +53,12 @@ usage ()\n \"\n }\n \n-: ${QUILT_DIR=@QUILT_DIR@}\n+if test -n \"$STAGING_DIR_HOST\"; then\n+\t: ${QUILT_DIR=\"$STAGING_DIR_HOST/share/quilt\"}\n+else\n+\t: ${QUILT_DIR=@QUILT_DIR@}\n+fi\n+\n . $QUILT_DIR/scripts/utilfns\n \n ensure_nolinks()\n--- a/bin/guards.in\n+++ b/bin/guards.in\n@@ -1,4 +1,6 @@\n-#!@PERL@ -w\n+#!@PERL@\n+\n+use warnings;\n \n #  This script is free software; you can redistribute it and/or modify\n #  it under the terms of the GNU General Public License version 2 as\n--- a/compat/date.in\n+++ b/compat/date.in\n@@ -1,4 +1,6 @@\n-#! @PERL@ -w\n+#! @PERL@\n+\n+use warnings;\n \n #  This script is free software; you can redistribute it and/or modify\n #  it under the terms of the GNU General Public License version 2 as\n--- a/compat/getopt.in\n+++ b/compat/getopt.in\n@@ -1,4 +1,6 @@\n-#! @PERL@ -w\n+#! @PERL@\n+\n+use warnings;\n \n #  This script is free software; you can redistribute it and/or modify\n #  it under the terms of the GNU General Public License version 2 as\n--- a/quilt/scripts/dependency-graph.in\n+++ b/quilt/scripts/dependency-graph.in\n@@ -1,4 +1,6 @@\n-#!@PERL@ -w\n+#!@PERL@\n+\n+use warnings;\n \n #  This script is free software; you can redistribute it and/or modify\n #  it under the terms of the GNU General Public License version 2 as\n"
  },
  {
    "path": "tools/quilt/patches/001-fix_compile.patch",
    "content": "--- a/Makefile.in\n+++ b/Makefile.in\n@@ -276,13 +276,10 @@ $(patsubst %.in,%,$(wildcard bin/*.in qu\n \t@$(if $(filter $@,$(NON_EXEC_IN)),,chmod +x $@)\n \n configure : configure.ac aclocal.m4\n-\tautoconf\n-\t@echo \"Please run ./configure\"\n-\t@false\n+\t@touch $@\n \n Makefile : Makefile.in configure\n-\t@echo \"Please run ./configure\"\n-\t@false\n+\t@touch $@\n \n compat_leftover := $(filter-out $(COMPAT),$(shell $(FIND) compat -type f -perm -0100))\n \n"
  },
  {
    "path": "tools/sdimage/Makefile",
    "content": "#\n# Copyright (C) 2015 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=imx-uuc\nPKG_RELEASE:=1\n\nPKG_SOURCE_PROTO:=git\nPKG_SOURCE_URL:=https://github.com/mhei/fsl-imx-uuc.git\nPKG_SOURCE_DATE:=2018-11-18\nPKG_SOURCE_VERSION:=c6536ac5b4388b33c217bde2c3a76a4e96d64176\nPKG_MIRROR_HASH:=747fb640a0596cab7d516979188e1f85be58c470df85cf1f7e3dcf8a4c1b36e5\n\nPKG_LICENSE:=GPL-2.0+\nPKG_LICENSE_FILES:=LICENSE\n\ninclude $(INCLUDE_DIR)/host-build.mk\n\ndefine Host/Configure\nendef\n\ndefine Host/Install\n\t$(INSTALL_BIN) $(HOST_BUILD_DIR)/sdimage $(STAGING_DIR_HOST)/bin/sdimage\nendef\n\ndefine Host/Clean\n\trm -f $(STAGING_DIR_HOST)/bin/sdimage\nendef\n\n$(eval $(call HostBuild))\n"
  },
  {
    "path": "tools/sdimage/patches/100-deactivate-ufb.patch",
    "content": "Deactivate ufb, this needs the UAPI Linux kernel headers from >= 3.18, \nthis tools is currently not used, so just remove it for now.\n\n--- a/Makefile\n+++ b/Makefile\n@@ -1,6 +1,6 @@\n CC ?= $(CROSS_COMPILE)gcc\n BINDIR ?= /usr/sbin\n-PROGRAMS = uuc sdimage ufb\n+PROGRAMS = uuc sdimage\n LIBS ?= -lpthread\n \n all: $(PROGRAMS)\n"
  },
  {
    "path": "tools/sed/Makefile",
    "content": "# \n# Copyright (C) 2006-2013 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=sed\nPKG_VERSION:=4.8\n\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz\nPKG_SOURCE_URL:=@GNU/$(PKG_NAME)\nPKG_HASH:=f79b0cfea71b37a8eeec8490db6c5f7ae7719c35587f21edb0617f370eeff633\nexport SED:=\n\nHOST_BUILD_PARALLEL:=1\n\nHOSTCC := $(HOSTCC_NOCACHE)\nHOSTCXX := $(HOSTCXX_NOCACHE)\n\ninclude $(INCLUDE_DIR)/host-build.mk\n\nHOST_CONFIGURE_ARGS += \\\n\t--disable-acl \\\n\t--disable-nls \\\n\t--enable-threads=posix \\\n\t--disable-i18n \\\n\t--without-selinux\n\nHOST_CONFIGURE_VARS += \\\n\tac_cv_search_setfilecon=no \\\n\tac_cv_header_selinux_context_h=no \\\n\tac_cv_header_selinux_selinux_h=no \\\n\ndefine Host/Compile\n\t+$(MAKE) $(HOST_JOBS) -C $(HOST_BUILD_DIR) SHELL=\"$(BASH)\"\nendef\n\ndefine Host/Install\n\t$(INSTALL_BIN) $(HOST_BUILD_DIR)/sed/sed $(STAGING_DIR_HOST)/bin/\nendef\n\ndefine Host/Clean\n\trm -f $(STAGING_DIR_HOST)/bin/sed\nendef\n\n$(eval $(call HostBuild))\n"
  },
  {
    "path": "tools/sparse/Makefile",
    "content": "#\n# Copyright (C) 2014 Qualcomm-Atheros Inc.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=sparse\n\nPKG_VERSION:=0.6.4\nPKG_HASH:=6ab28b4991bc6aedbd73550291360aa6ab3df41f59206a9bde9690208a6e387c\nPKG_RELEASE:=1\n\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz\nPKG_SOURCE_URL:=@KERNEL/software/devel/sparse/dist/\n\nPKG_BUILD_PARALLEL:=1\n\ninclude $(INCLUDE_DIR)/host-build.mk\n\ndefine Host/Install\n       $(INSTALL_BIN) $(HOST_BUILD_DIR)/sparse $(STAGING_DIR_HOST)/bin\nendef\n\n$(eval $(call HostBuild))\n"
  },
  {
    "path": "tools/squashfs/Makefile",
    "content": "# \n# Copyright (C) 2006-2012 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=squashfs\nPKG_CPE_ID:=cpe:/a:phillip_lougher:squashfs\nPKG_VERSION:=3.0\n\nPKG_SOURCE:=$(PKG_NAME)$(PKG_VERSION).tar.gz\nPKG_SOURCE_URL:=@SF/squashfs\nPKG_HASH:=39dbda43cf118536deb746c7730b468702d514a19f4cfab73b710e32908ddf20\nPKG_CAT:=zcat\n\nHOST_BUILD_DIR:=$(BUILD_DIR_HOST)/$(PKG_NAME)$(PKG_VERSION)\n\ninclude $(INCLUDE_DIR)/host-build.mk\n\ndefine Host/Compile\n\t$(MAKE) -C $(HOST_BUILD_DIR)/squashfs-tools \\\n\t\tCC=\"$(HOSTCC)\" \\\n\t\tCFLAGS=\"$(HOST_CFLAGS) -D_FILE_OFFSET_BITS=64 -D_LARGEFILE_SOURCE -I.\" \\\n\t\tCXX=\"$(CXX)\" \\\n\t\tLZMAPATH=$(STAGING_DIR_HOST)/lib \\\n\t\tmksquashfs-lzma unsquashfs-lzma \nendef\n\ndefine Host/Install\n\t$(INSTALL_BIN) $(HOST_BUILD_DIR)/squashfs-tools/mksquashfs-lzma $(STAGING_DIR_HOST)/bin/\n\t$(INSTALL_BIN) $(HOST_BUILD_DIR)/squashfs-tools/unsquashfs-lzma $(STAGING_DIR_HOST)/bin/\nendef\n\ndefine Host/Clean\n\trm -f $(STAGING_DIR_HOST)/bin/mksquashfs-lzma\n\trm -f $(STAGING_DIR_HOST)/bin/unsquashfs-lzma\nendef\n\n$(eval $(call HostBuild))\n"
  },
  {
    "path": "tools/squashfs/patches/100-lzma.patch",
    "content": "--- a/squashfs-tools/Makefile\n+++ b/squashfs-tools/Makefile\n@@ -7,6 +7,9 @@ all: mksquashfs unsquashfs\n mksquashfs: mksquashfs.o read_fs.o sort.o\n \t$(CC) mksquashfs.o read_fs.o sort.o -lz -o $@\n \n+mksquashfs-lzma: mksquashfs.o read_fs.o sort.o\n+\t$(CXX) mksquashfs.o read_fs.o sort.o -L$(LZMAPATH) -llzma-old -o $@\n+\n mksquashfs.o: mksquashfs.c squashfs_fs.h mksquashfs.h global.h sort.h\n \n read_fs.o: read_fs.c squashfs_fs.h read_fs.h global.h\n@@ -16,4 +19,9 @@ sort.o: sort.c squashfs_fs.h global.h so\n unsquashfs: unsquashfs.o\n \t$(CC) unsquashfs.o -lz -o $@\n \n+unsquashfs-lzma: unsquashfs.o\n+\t$(CXX) unsquashfs.o -L$(LZMAPATH) -llzma-old -o $@\n+\n unsquashfs.o: unsquashfs.c squashfs_fs.h read_fs.h global.h\n+\n+clean:\n"
  },
  {
    "path": "tools/squashfs/patches/110-no_nonstatic_inline.patch",
    "content": "--- a/squashfs-tools/mksquashfs.c\n+++ b/squashfs-tools/mksquashfs.c\n@@ -1347,7 +1347,7 @@ struct inode_info *lookup_inode(struct s\n }\n \n \n-inline void add_dir_entry(char *name, char *pathname, struct dir_info *sub_dir, struct inode_info *inode_info, void *data, struct dir_info *dir)\n+static inline void add_dir_entry(char *name, char *pathname, struct dir_info *sub_dir, struct inode_info *inode_info, void *data, struct dir_info *dir)\n {\n \tif((dir->count % DIR_ENTRIES) == 0)\n \t\tif((dir->list = realloc(dir->list, (dir->count + DIR_ENTRIES) * sizeof(struct dir_ent *))) == NULL)\n"
  },
  {
    "path": "tools/squashfs/patches/120-add-fixed-timestamp-support.patch",
    "content": "--- a/squashfs-tools/mksquashfs.c\n+++ b/squashfs-tools/mksquashfs.c\n@@ -117,6 +117,9 @@ unsigned int inode_bytes = 0, inode_size\n char *data_cache = NULL;\n unsigned int cache_bytes = 0, cache_size = 0, inode_count = 0;\n \n+/* override all timestamps */\n+time_t fixed_time = -1;\n+\n /* in memory directory data */\n #define I_COUNT_SIZE\t\t128\n #define DIR_ENTRIES\t\t32\n@@ -1554,6 +1557,11 @@ void dir_scan(squashfs_inode *inode, cha\n \t\tperror(buffer);\n \t\treturn;\n \t}\n+\n+\t/* override timestamp of lstat if fixed_time is given */\n+\tif(fixed_time != -1)\n+\t\tinode_info->buf.st_mtime = fixed_time;\n+\n \tif(sorted)\n \t\tsort_files_and_write(dir_info);\n \tdir_scan2(inode, dir_info);\n@@ -1582,6 +1590,10 @@ struct dir_info *dir_scan1(char *pathnam\n \t\t\tperror(buffer);\n \t\t\tcontinue;\n \t\t}\n+\n+\t\tif(fixed_time != -1)\n+\t\t\tbuf.st_mtime = fixed_time;\n+\n \t\tif(excluded(filename, &buf))\n \t\t\tcontinue;\n \n@@ -1621,6 +1633,9 @@ int dir_scan2(squashfs_inode *inode, str\n \t\tchar *dir_name = dir_ent->name;\n \t\tunsigned int inode_number = ((buf->st_mode & S_IFMT) == S_IFDIR) ? dir_ent->inode->inode_number : dir_ent->inode->inode_number + dir_inode_no;\n \n+\t\tif(fixed_time != -1)\n+\t\t\tbuf->st_mtime = fixed_time;\n+\n \t\tif(dir_ent->inode->inode == SQUASHFS_INVALID_BLK) {\n \t\t\tswitch(buf->st_mode & S_IFMT) {\n \t\t\t\tcase S_IFREG:\n@@ -1898,6 +1913,16 @@ int main(int argc, char *argv[])\n \t\t\t\t\texit(1);\n \t\t\t\t}\n \t\t\t}\n+\t\t} else if(strcmp(argv[i], \"-fixed-time\") == 0) {\n+\t\t\tif(++i == argc) {\n+\t\t\t\tERROR(\"%s: -fixed-time missing a timestamp\\n\", argv[0]);\n+\t\t\t\texit(1);\n+\t\t\t}\n+\t\t\tfixed_time = strtoll(argv[i], &b, 10);\n+\t\t\tif(*b != '\\0') {\n+\t\t\t\tERROR(\"%s: -fixed-time has an invalid number\\n\", argv[0]);\n+\t\t\t\texit(1);\n+\t\t\t}\n \t\t} else if(strcmp(argv[i], \"-noI\") == 0 ||\n \t\t\t\tstrcmp(argv[i], \"-noInodeCompression\") == 0)\n \t\t\tnoI = TRUE;\n@@ -1967,6 +1992,7 @@ printOptions:\n \t\t\tERROR(\"-all-root\\t\\tmake all files owned by root\\n\");\n \t\t\tERROR(\"-force-uid uid\\t\\tset all file uids to uid\\n\");\n \t\t\tERROR(\"-force-gid gid\\t\\tset all file gids to gid\\n\");\n+\t\t\tERROR(\"-fixed-time timestamp\\tset all timestamps to timestamp\\n\");\n \t\t\tERROR(\"-le\\t\\t\\tcreate a little endian filesystem\\n\");\n \t\t\tERROR(\"-be\\t\\t\\tcreate a big endian filesystem\\n\");\n \t\t\tERROR(\"-nopad\\t\\t\\tdo not pad filesystem to a multiple of 4K\\n\");\n@@ -2190,7 +2216,7 @@ printOptions:\n \tsBlk.block_size = block_size;\n \tsBlk.block_log = block_log;\n \tsBlk.flags = SQUASHFS_MKFLAGS(noI, noD, check_data, noF, no_fragments, always_use_fragments, duplicate_checking);\n-\tsBlk.mkfs_time = time(NULL);\n+\tsBlk.mkfs_time = fixed_time != -1 ? fixed_time : time(NULL);\n \n restore_filesystem:\n \twrite_fragment();\n"
  },
  {
    "path": "tools/squashfs/patches/130-include_sysmacros.patch",
    "content": "--- a/squashfs-tools/mksquashfs.c\n+++ b/squashfs-tools/mksquashfs.c\n@@ -30,6 +30,7 @@\n #include <unistd.h>\n #include <stdio.h>\n #include <sys/types.h>\n+#include <sys/sysmacros.h>\n #include <sys/stat.h>\n #include <fcntl.h>\n #include <errno.h>\n--- a/squashfs-tools/unsquashfs.c\n+++ b/squashfs-tools/unsquashfs.c\n@@ -25,6 +25,7 @@\n #define FALSE 0\n #include <stdio.h>\n #include <sys/types.h>\n+#include <sys/sysmacros.h>\n #include <sys/stat.h>\n #include <fcntl.h>\n #include <errno.h>\n"
  },
  {
    "path": "tools/squashfs/patches/140-gcc-10-fix.patch",
    "content": "Fixes the following build error with GCC 10:\n\t/usr/bin/ld: read_fs.o:(.bss+0x0): multiple definition of `swap'; mksquashfs.o:(.bss+0x1b2a88): first defined here\nAnd a compile warning.\n\n--- a/squashfs-tools/read_fs.c\n+++ b/squashfs-tools/read_fs.c\n@@ -61,7 +61,7 @@ extern int add_file(long long, long long\n \t\t\t\t\t\tfprintf(stderr, s, ## args); \\\n \t\t\t\t\t} while(0)\n \n-int swap;\n+static int swap;\n \n int read_block(int fd, long long start, long long *next, unsigned char *block, squashfs_super_block *sBlk)\n {\n--- a/squashfs-tools/mksquashfs.c\n+++ b/squashfs-tools/mksquashfs.c\n@@ -258,6 +258,7 @@ int read_sort_file(char *filename, int s\n void sort_files_and_write(struct dir_info *dir);\n struct file_info *duplicate(char *(get_next_file_block)(struct duplicate_buffer_handle *, unsigned int), struct duplicate_buffer_handle *file_start, long long bytes, unsigned int **block_list, long long *start, int blocks, struct fragment **fragment, char *frag_data, int frag_bytes);\n struct dir_info *dir_scan1(char *, int (_readdir)(char *, char *, struct dir_info *));\n+int dir_scan2(squashfs_inode *inode, struct dir_info *dir_info);\n \n #define MKINODE(A)\t((squashfs_inode)(((squashfs_inode) inode_bytes << 16) + (((char *)A) - data_cache)))\n \n"
  },
  {
    "path": "tools/squashfskit4/Makefile",
    "content": "#\n# Copyright (C) 2009-2012 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=squashfskit4\nPKG_VERSION:=4.14\nPKG_RELEASE:=3\nPKG_SOURCE:=squashfskit-v$(PKG_VERSION).tar.xz\nPKG_SOURCE_URL:=https://github.com/squashfskit/squashfskit/releases/download/v$(PKG_VERSION)/\nPKG_HASH:=5761aaa3aedc4f7112b708367d891c9abdc1ffea972e3fe47923ddba23984d95\n\nHOST_BUILD_DIR:=$(BUILD_DIR_HOST)/squashfskit-v$(PKG_VERSION)\n\ninclude $(INCLUDE_DIR)/host-build.mk\n\ndefine Host/Compile\n\t+$(HOST_MAKE_VARS) \\\n\t$(MAKE) -C $(HOST_BUILD_DIR)/squashfs-tools \\\n\t\tXZ_SUPPORT=1 \\\n\t\tLZMA_XZ_SUPPORT=1 \\\n\t\tXATTR_SUPPORT=1 \\\n\t\tLZMA_LIB=\"$(STAGING_DIR_HOST)/lib/liblzma.a\" \\\n\t\tEXTRA_CFLAGS=\"-I$(STAGING_DIR_HOST)/include\" \\\n\t\tmksquashfs unsquashfs\nendef\n\ndefine Host/Install\n\t$(INSTALL_BIN) $(HOST_BUILD_DIR)/squashfs-tools/mksquashfs $(STAGING_DIR_HOST)/bin/mksquashfs4\n\t$(INSTALL_BIN) $(HOST_BUILD_DIR)/squashfs-tools/unsquashfs $(STAGING_DIR_HOST)/bin/unsquashfs4\nendef\n\ndefine Host/Clean\n\trm -f $(STAGING_DIR_HOST)/bin/mksquashfs4\n\trm -f $(STAGING_DIR_HOST)/bin/unsquashfs4\nendef\n\n$(eval $(call HostBuild))\n"
  },
  {
    "path": "tools/squashfskit4/patches/0001-fix-version.sh.patch",
    "content": "--- a/squashfs-tools/version.sh\n+++ b/squashfs-tools/version.sh\n@@ -27,13 +27,11 @@ if [ -z \"$OUTPUT\" ] ; then\n fi\n \n our_date() {\n-case $(uname) in\n-NetBSD|OpenBSD|DragonFly|FreeBSD|Darwin)\n-        date -r \"$1\" \"$2\"\n-        ;;\n-*)\n-        date -d \"@$1\" \"$2\"\n-esac\n+\tif date --version 2>&1 | grep -q \"GNU coreutils\"; then\n+\t\tdate -d \"@$1\" \"$2\"\n+\telse\n+\t\tdate -r \"$1\" \"$2\"\n+\tfi\n }\n \n try_version() {\n"
  },
  {
    "path": "tools/squashfskit4/patches/0002-fix-build-failure-against-gcc-10.patch",
    "content": "From fe2f5da4b0f8994169c53e84b7cb8a0feefc97b5 Mon Sep 17 00:00:00 2001\nFrom: Sergei Trofimovich <slyfox@gentoo.org>\nDate: Sun, 26 Jan 2020 18:35:13 +0000\nSubject: [PATCH] squashfs-tools: fix build failure against gcc-10\nMIME-Version: 1.0\nContent-Type: text/plain; charset=UTF-8\nContent-Transfer-Encoding: 8bit\n\nOn gcc-10 (and gcc-9 -fno-common) build fails as:\n\n```\ncc ... -o mksquashfs\nld: read_fs.o:(.bss+0x0):\n  multiple definition of `fwriter_buffer'; mksquashfs.o:(.bss+0x400c90): first defined here\nld: read_fs.o:(.bss+0x8):\n  multiple definition of `bwriter_buffer'; mksquashfs.o:(.bss+0x400c98): first defined here\n```\n\ngcc-10 will change the default from -fcommon to fno-common:\nhttps://gcc.gnu.org/PR85678.\n\nThe error also happens if CFLAGS=-fno-common passed explicitly.\n\nReported-by: Toralf Förster\nBug: https://bugs.gentoo.org/706456\nSigned-off-by: Sergei Trofimovich <slyfox@gentoo.org>\n---\n squashfs-tools/mksquashfs.h | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\n\n--- a/squashfs-tools/mksquashfs.h\n+++ b/squashfs-tools/mksquashfs.h\n@@ -133,7 +133,7 @@ struct append_file {\n #define BLOCK_OFFSET 2\n \n extern struct cache *reader_buffer, *fragment_buffer, *reserve_cache;\n-struct cache *bwriter_buffer, *fwriter_buffer;\n+extern struct cache *bwriter_buffer, *fwriter_buffer;\n extern struct queue *to_reader, *to_deflate, *to_writer, *from_writer,\n \t       *locked_fragment, *to_process_frag;\n extern struct append_file **file_mapping;\n"
  },
  {
    "path": "tools/squashfskit4/patches/0010-portability.patch",
    "content": "--- a/squashfs-tools/xattr.c\n+++ b/squashfs-tools/xattr.c\n@@ -113,6 +113,7 @@ static int get_prefix(struct xattr_list\n \n static int read_xattrs_from_system(char *filename, struct xattr_list **xattrs)\n {\n+#if defined(linux)\n \tssize_t size, vsize;\n \tchar *xattr_names, *p;\n \tint i;\n@@ -222,6 +223,10 @@ failed:\n \tfree(xattr_list);\n \tfree(xattr_names);\n \treturn 0;\n+#else\n+\t*xattrs = NULL;\n+\treturn 0;\n+#endif\n }\n \n \n--- a/squashfs-tools/unsquashfs_xattr.c\n+++ b/squashfs-tools/unsquashfs_xattr.c\n@@ -34,6 +34,7 @@ extern int user_xattrs;\n \n void write_xattr(char *pathname, unsigned int xattr)\n {\n+#if defined(linux)\n \tunsigned int count;\n \tstruct xattr_list *xattr_list;\n \tint i;\n@@ -136,4 +137,5 @@ void write_xattr(char *pathname, unsigne\n \t}\n \n \tfree_xattr(xattr_list, count);\n+#endif\n }\n"
  },
  {
    "path": "tools/squashfskit4/patches/0020-big-endian.patch",
    "content": "--- a/squashfs-tools/xz_wrapper.c\n+++ b/squashfs-tools/xz_wrapper.c\n@@ -192,7 +192,10 @@ static void xz_display_options(void *buf\n \tif(size != sizeof(struct comp_opts))\n \t\tgoto failed;\n \n-\tSQUASHFS_INSWAP_LZMA_COMP_OPTS(comp_opts);\n+#if __BYTE_ORDER == __BIG_ENDIAN\n+\tcomp_opts->dictionary_size = inswap_le32(comp_opts->dictionary_size);\n+\tcomp_opts->flags = inswap_le32(comp_opts->flags);\n+#endif\n \n \tdictionary_size = comp_opts->dictionary_size;\n \tflags = comp_opts->flags;\n"
  },
  {
    "path": "tools/sstrip/Makefile",
    "content": "# \n# Copyright (C) 2006-2012 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=sstrip\nPKG_VERSION:=3.2\n\nHOST_BUILD_DIR:=$(BUILD_DIR_HOST)/ELFkickers-$(PKG_VERSION)\nPKG_SOURCE_URL:=https://www.muppetlabs.com/~breadbox/pub/software\nPKG_SOURCE:=ELFkickers-$(PKG_VERSION).tar.gz\nPKG_HASH:=9b81e6c53e0c94fc198d9882eb737156f36d565152dc32118897c77b06a2687c\n\nPKG_RELEASE:=1\n\ninclude $(INCLUDE_DIR)/host-build.mk\n\ndefine Host/Install\n\t$(CP) $(HOST_BUILD_DIR)/bin/sstrip $(STAGING_DIR_HOST)/bin/\nendef\n\ndefine Host/Clean\n\trm -f $(STAGING_DIR_HOST)/bin/sstrip\nendef\n\n$(eval $(call HostBuild))\n"
  },
  {
    "path": "tools/sstrip/patches/001-disable-elftoc-compilation.patch",
    "content": "From: Rui Salvaterra <rsalvaterra@gmail.com>\nSubject: sstrip: don't try to compile elftoc\n\nWe only need sstrip itself and elftoc doesn't compile with musl's elf.h, so\ndisable the elftoc compilation in the makefile.\n\nSigned-off-by: Rui Salvaterra <rsalvaterra@gmail.com>\n---\n\n--- a/Makefile\n+++ b/Makefile\n@@ -2,7 +2,7 @@\n \n prefix = /usr/local\n \n-PROGRAMS = elfls objres rebind sstrip elftoc ebfc infect\n+PROGRAMS = elfls objres rebind sstrip ebfc infect\n \n all: $(PROGRAMS)\n \n@@ -19,7 +19,6 @@ elfls: bin/elfls doc/elfls.1\n objres: bin/objres doc/objres.1\n rebind: bin/rebind doc/rebind.1\n sstrip: bin/sstrip doc/sstrip.1\n-elftoc: bin/elftoc doc/elftoc.1\n ebfc: bin/ebfc doc/ebfc.1\n infect: bin/infect doc/infect.1\n \n"
  },
  {
    "path": "tools/tar/Makefile",
    "content": "#\n# Copyright (C) 2015 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=tar\nPKG_CPE_ID:=cpe:/a:gnu:tar\nPKG_VERSION:=1.34\n\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz\nPKG_SOURCE_URL:=@GNU/tar\nPKG_HASH:=63bebd26879c5e1eea4352f0d03c991f966aeb3ddeb3c7445c902568d5411d28\n\nHOST_BUILD_PARALLEL:=1\n\ninclude $(INCLUDE_DIR)/host-build.mk\n\nHOSTCC := $(HOSTCC_NOCACHE)\nHOSTCXX := $(HOSTCXX_NOCACHE)\n\nHOST_CONFIGURE_ARGS += \\\n\t--without-posix-acls \\\n\t--without-selinux \\\n\t--without-xattrs \\\n\t--disable-acl \\\n\t--disable-nls\n\n$(eval $(call HostBuild))\n"
  },
  {
    "path": "tools/tar/patches/100-symlink-force-root-name.patch",
    "content": "Force root/root as names for uid0/gid0 instead of using the system\nnames. This helps make packed download tarballs more reproducible\n\nSigned-off-by: Felix Fietkau <nbd@nbd.name>\n---\n--- a/src/create.c\n+++ b/src/create.c\n@@ -543,17 +543,8 @@ write_gnu_long_link (struct tar_stat_inf\n   union block *header;\n \n   header = start_private_header (\"././@LongLink\", size, 0);\n-  if (! numeric_owner_option)\n-    {\n-      static char *uname, *gname;\n-      if (!uname)\n-\t{\n-\t  uid_to_uname (0, &uname);\n-\t  gid_to_gname (0, &gname);\n-\t}\n-      UNAME_TO_CHARS (uname, header->header.uname);\n-      GNAME_TO_CHARS (gname, header->header.gname);\n-    }\n+  UNAME_TO_CHARS (\"root\", header->header.uname);\n+  GNAME_TO_CHARS (\"root\", header->header.gname);\n \n   strcpy (header->buffer + offsetof (struct posix_header, magic),\n \t  OLDGNU_MAGIC);\n"
  },
  {
    "path": "tools/tar/patches/110-symlink-force-permissions.patch",
    "content": "--- a/src/create.c\n+++ b/src/create.c\n@@ -1844,6 +1844,7 @@ dump_file0 (struct tar_stat_info *st, ch\n #ifdef HAVE_READLINK\n   else if (S_ISLNK (st->stat.st_mode))\n     {\n+      st->stat.st_mode |= 0777; /* make permissions portable */\n       st->link_name = areadlinkat_with_size (parentfd, name, st->stat.st_size);\n       if (!st->link_name)\n \t{\n"
  },
  {
    "path": "tools/xxd/Makefile",
    "content": "# SPDX-License-Identifier: GPL-2.0-or-later\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=xxd\nPKG_VERSION:=1.10\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz\nPKG_SOURCE_URL:=http://grail.cba.csuohio.edu/~somos/\nPKG_HASH:=9bf05c19b9084973e3cc877696a7f9881a5c87fa5a9fa438d9962519726559f9\nPKG_CPE_ID:=cpe:/a:vim:vim\n\ninclude $(INCLUDE_DIR)/host-build.mk\n\ndefine Host/Install\n\t$(INSTALL_DIR) $(STAGING_DIR_HOST)/bin\n\t$(INSTALL_BIN) $(HOST_BUILD_DIR)/xxd $(STAGING_DIR_HOST)/bin/\nendef\n\n$(eval $(call HostBuild))\n"
  },
  {
    "path": "tools/xz/Makefile",
    "content": "#\n# Copyright (C) 2006-2015 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=xz\nPKG_VERSION:=5.2.5\n\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.bz2\nPKG_SOURCE_URL:=@SF/lzmautils \\\n\t\thttp://tukaani.org/xz\nPKG_HASH:=5117f930900b341493827d63aa910ff5e011e0b994197c3b71c08a20228a42df\nPKG_CPE_ID:=cpe:/a:tukaani:xz\n\nHOST_BUILD_PARALLEL:=1\n\ninclude $(INCLUDE_DIR)/host-build.mk\n\nHOSTCC := $(HOSTCC_NOCACHE)\nHOSTCXX := $(HOSTCXX_NOCACHE)\n\nHOST_CONFIGURE_ARGS += \\\n\t--enable-static=yes \\\n\t--enable-shared=no \\\n\t--disable-doc \\\n\t--disable-nls \\\n\t--with-pic\n\ndefine Host/Install\n\t+$(MAKE) $(HOST_JOBS) -C $(HOST_BUILD_DIR) install xzlinks=\"unxz xzcat\"\nendef\n\n$(eval $(call HostBuild))\n"
  },
  {
    "path": "tools/zip/Makefile",
    "content": "#\n# Copyright (C) 2007-2016 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=zip\nPKG_REV:=30\nPKG_VERSION:=3.0\n\nPKG_SOURCE:=$(PKG_NAME)$(PKG_REV).tar.gz\nPKG_SOURCE_URL:=@SF/infozip\nPKG_HASH:=f0e8bb1f9b7eb0b01285495a2699df3a4b766784c1765a8f1aeedf63c0806369\n\nPKG_LICENSE:=BSD-4-Clause\nPKG_LICENSE_FILES:=LICENSE\n\nHOST_BUILD_DIR:=$(BUILD_DIR_HOST)/$(PKG_NAME)-$(PKG_VERSION)/zip$(PKG_REV)\nHOST_BUILD_PARALLEL:=1\n\ninclude $(INCLUDE_DIR)/host-build.mk\n\ndefine Host/Compile\n\t+$(HOST_MAKE_VARS) $(MAKE) $(HOST_JOBS) -C $(HOST_BUILD_DIR) -I. -f unix/Makefile zip\nendef\n\ndefine Host/Install\n\t$(INSTALL_DIR) $(STAGING_DIR_HOST)/bin/\n\t$(INSTALL_BIN) $(HOST_BUILD_DIR)/zip $(STAGING_DIR_HOST)/bin/\nendef\n\n$(eval $(call HostBuild))\n#$(eval $(call BuildPackage,zip))\n"
  },
  {
    "path": "tools/zip/patches/001-unix-configure-borrow-the-LFS-test-from-autotools.patch",
    "content": "From fc392c939b9a18959482f588aff0afc29dd6d30a Mon Sep 17 00:00:00 2001\nFrom: Romain Naour <romain.naour at openwide.fr>\nDate: Fri, 23 Jan 2015 22:20:18 +0100\nSubject: [PATCH 6/6] unix/configure: borrow the LFS test from autotools.\n\nInfozip's LFS check can't work for cross-compilation\nsince it try to run a target's binary on the host system.\n\nInstead, use to LFS test used by autotools which is a\ncompilation test.\n(see autotools/lib/autoconf/specific.m4)\n\nReported-by: Richard Genoud <richard.genoud at gmail.com>\nSigned-off-by: Romain Naour <romain.naour at openwide.fr>\n---\n configure |   46 +++++++++++++++-------------------------------\n 1 file changed, 15 insertions(+), 31 deletions(-)\n\n--- a/unix/configure\n+++ b/unix/configure\n@@ -399,9 +399,8 @@ else\n fi\n \n \n-# Now we set the 64-bit file environment and check the size of off_t\n-# Added 11/4/2003 EG\n-# Revised 8/12/2004 EG\n+# LFS check borrowed from autotools sources\n+# lib/autoconf/specific.m4\n \n echo Check for Large File Support\n cat > conftest.c << _EOF_\n@@ -410,23 +409,19 @@ cat > conftest.c << _EOF_\n # define _FILE_OFFSET_BITS 64       /* select default interface as 64 bit */\n # define _LARGE_FILES        /* some OSes need this for 64-bit off_t */\n #include <sys/types.h>\n-#include <sys/stat.h>\n-#include <unistd.h>\n-#include <stdio.h>\n+\n+ /* Check that off_t can represent 2**63 - 1 correctly.\n+    We can't simply define LARGE_OFF_T to be 9223372036854775807,\n+    since some C++ compilers masquerading as C compilers\n+    incorrectly reject 9223372036854775807.  */\n+#define LARGE_OFF_T (((off_t) 1 << 62) - 1 + ((off_t) 1 << 62))\n+  int off_t_is_large[(LARGE_OFF_T % 2147483629 == 721\n+\t\t       && LARGE_OFF_T % 2147483647 == 1)\n+\t\t      ? 1 : -1];\n+\n int main()\n {\n-  off_t offset;\n-  struct stat s;\n-  /* see if have 64-bit off_t */\n-  if (sizeof(offset) < 8)\n-    return 1;\n-  printf(\"  off_t is %d bytes\\n\", sizeof(off_t));\n-  /* see if have 64-bit stat */\n-  if (sizeof(s.st_size) < 8) {\n-    printf(\"  s.st_size is %d bytes\\n\", sizeof(s.st_size));\n-    return 2;\n-  }\n-  return 3;\n+  return 0;\n }\n _EOF_\n # compile it\n@@ -434,19 +429,8 @@ $CC -o conftest conftest.c >/dev/null 2>\n if [ $? -ne 0 ]; then\n   echo -- no Large File Support\n else\n-# run it\n-  ./conftest\n-  r=$?\n-  if [ $r -eq 1 ]; then\n-    echo -- no Large File Support - no 64-bit off_t\n-  elif [ $r -eq 2 ]; then\n-    echo -- no Large File Support - no 64-bit stat\n-  elif [ $r -eq 3 ]; then\n-    echo -- yes we have Large File Support!\n-    CFLAGS=\"${CFLAGS} -DLARGE_FILE_SUPPORT\"\n-  else\n-    echo -- no Large File Support - conftest returned $r\n-  fi\n+  echo -- yes we have Large File Support!\n+  CFLAGS=\"${CFLAGS} -DLARGE_FILE_SUPPORT\"\n fi\n \n \n"
  },
  {
    "path": "tools/zip/patches/004-do-not-set-unwanted-cflags.patch",
    "content": "From: Santiago Vila <sanvila@debian.org>\nSubject: Do not set unwanted CFLAGS, as it breaks DEB_BUILD_OPTIONS\nX-Debian-version: 2.32-1\n\n--- a/unix/configure\n+++ b/unix/configure\n@@ -98,7 +98,7 @@ int main()\n _EOF_\n       $CC $CFLAGS -c conftest.c > /dev/null 2>/dev/null\n       if test $? -eq 0; then\n-        CFLAGS_OPT='-O3'\n+        # CFLAGS_OPT='-O3'\n         echo \"  GNU C ($CFLAGS_OPT)\"\n         # Special Mac OS X shared library \"ld\" option?\n         if test ` uname -s 2> /dev/null ` = 'Darwin'; then\n"
  },
  {
    "path": "tools/zip/patches/006-stack-markings-to-avoid-executable-stack.patch",
    "content": "From: Kees Cook <kees@debian.org>\nSubject: put stack markings in i386 assembly to avoid executable stack\nBug-Debian: http://bugs.debian.org/528280\nX-Debian-version: 3.0-2\n\n--- a/crc_i386.S\n+++ b/crc_i386.S\n@@ -302,3 +302,5 @@ _crc32:                         /* ulg c\n #endif /* i386 || _i386 || _I386 || __i386 */\n \n #endif /* !USE_ZLIB && !CRC_TABLE_ONLY */\n+.section .note.GNU-stack, \"\", @progbits\n+.previous\n--- a/match.S\n+++ b/match.S\n@@ -405,3 +405,5 @@ L__return:\n #endif /* i386 || _I386 || _i386 || __i386  */\n \n #endif /* !USE_ZLIB */\n+.section .note.GNU-stack, \"\", @progbits\n+.previous\n"
  },
  {
    "path": "tools/zip/patches/007-fclose-in-file-not-fclose-x.patch",
    "content": "From: Christian Spieler\nSubject: zipnote.c: Close in_file instead of undefined file x\nBug-Debian: http://bugs.debian.org/628594\nX-Debian-version: 3.0-4\n\n--- a/zipnote.c\n+++ b/zipnote.c\n@@ -661,7 +661,7 @@ char **argv;            /* command line\n     if ((r = zipcopy(z)) != ZE_OK)\n       ziperr(r, \"was copying an entry\");\n   }\n-  fclose(x);\n+  fclose(in_file);\n \n   /* Write central directory and end of central directory with new comments */\n   if ((c = zftello(y)) == (zoff_t)-1)    /* get start of central */\n"
  },
  {
    "path": "tools/zip/patches/008-hardening-build-fix-1.patch",
    "content": "From: Santiago Vila <sanvila@debian.org>\nSubject: Use format specifier %s to print strings, not the string itself\nBug-Debian: http://bugs.debian.org/673476\nX-Debian-version: 3.0-5\n\n--- a/zip.c\n+++ b/zip.c\n@@ -1028,7 +1028,7 @@ local void help_extended()\n \n   for (i = 0; i < sizeof(text)/sizeof(char *); i++)\n   {\n-    printf(text[i]);\n+    printf(\"%s\", text[i]);\n     putchar('\\n');\n   }\n #ifdef DOS\n@@ -1225,7 +1225,7 @@ local void version_info()\n             CR_MAJORVER, CR_MINORVER, CR_BETA_VER, CR_VERSION_DATE);\n   for (i = 0; i < sizeof(cryptnote)/sizeof(char *); i++)\n   {\n-    printf(cryptnote[i]);\n+    printf(\"%s\", cryptnote[i]);\n     putchar('\\n');\n   }\n   ++i;  /* crypt support means there IS at least one compilation option */\n"
  },
  {
    "path": "tools/zip/patches/009-hardening-build-fix-2.patch",
    "content": "From: Santiago Vila <sanvila@debian.org>\nSubject: unix/configure: Take linking flags from the environment\nBug-Debian: http://bugs.debian.org/673476\nX-Debian-version: 3.0-5\n\n--- a/unix/configure\n+++ b/unix/configure\n@@ -18,7 +18,7 @@ trap \"rm -f conftest* core a.out; exit 1\n \n CC=${1-cc}\n CFLAGS=${2-\"-I. -DUNIX\"}\n-LFLAGS1=''\n+LFLAGS1=${LDFLAGS}\n LFLAGS2=''\n LN=\"ln -s\"\n \n"
  },
  {
    "path": "tools/zip/patches/010-remove-build-date.patch",
    "content": "From: Santiago Vila <sanvila@debian.org>\nSubject: Remove (optional) build date to make the build reproducible\nBug-Debian: http://bugs.debian.org/779042\n\n--- a/unix/unix.c\n+++ b/unix/unix.c\n@@ -1020,7 +1020,7 @@ void version_local()\n \n \n /* Define the compile date string */\n-#ifdef __DATE__\n+#if 0\n #  define COMPILE_DATE \" on \" __DATE__\n #else\n #  define COMPILE_DATE \"\"\n"
  },
  {
    "path": "tools/zip/patches/011-reproducible-mtime.patch",
    "content": "From 501ae4e93fd6fa2f7d20d00d1b011f9006802eae Mon Sep 17 00:00:00 2001\nFrom: \"Bernhard M. Wiedemann\" <bwiedemann@suse.de>\nDate: Fri, 3 May 2019 16:32:24 +0200\nSubject: [PATCH] Override mtime with zip -X\n\nwith SOURCE_DATE_EPOCH\nto allow for reproducible builds of .zip files\n\nSee https://reproducible-builds.org/ for why this is good\nand https://reproducible-builds.org/specs/source-date-epoch/\nfor the definition of this variable.\n\nUses clamping to keep older mtimes than SOURCE_DATE_EPOCH intact.\n---\n zipup.c | 8 ++++++++\n 1 file changed, 8 insertions(+)\n\n--- a/zipup.c\n+++ b/zipup.c\n@@ -414,6 +414,7 @@ struct zlist far *z;    /* zip entry to\n   ush tempcext = 0;\n   char *tempextra = NULL;\n   char *tempcextra = NULL;\n+  const char *source_date_epoch;\n \n \n #ifdef WINDLL\n@@ -674,6 +675,13 @@ struct zlist far *z;    /* zip entry to\n \n   } /* strcmp(z->name, \"-\") == 0 */\n \n+  if (extra_fields == 0 && (source_date_epoch = getenv(\"SOURCE_DATE_EPOCH\")) != NULL) {\n+     time_t epoch = strtoull(source_date_epoch, NULL, 10);\n+     if (epoch > 0) {\n+       ulg epochtim = unix2dostime(&epoch);\n+       if (z->tim > epochtim) z->tim = epochtim;\n+     }\n+  }\n   if (extra_fields == 2) {\n     unsigned len;\n     char *p;\n"
  },
  {
    "path": "tools/zip/patches/012-make-encrypted-archives-reproducible.patch",
    "content": "From db9165814823401d57383a8f9e82642129cf4223 Mon Sep 17 00:00:00 2001\nFrom: Sungbo Eo <mans0n@gorani.run>\nDate: Sat, 12 Feb 2022 16:42:14 +0900\nSubject: [PATCH] make encrypted archives reproducible\n\nZip always try to generate new encryption header depending on execution\ntime and process id, which is far from being reproducible. This commit\nchanges the zip srand() seed to a predictable value to generate\nreproducible random bytes for the encryption header. This will compromise\nthe goal of secure archive encryption, but it would not be a big problem\nfor our purpose.\n\nSigned-off-by: Sungbo Eo <mans0n@gorani.run>\n---\n crypt.c   | 8 ++++++--\n globals.c | 1 +\n zip.h     | 1 +\n zipup.c   | 2 +-\n 4 files changed, 9 insertions(+), 3 deletions(-)\n\n--- a/crypt.c\n+++ b/crypt.c\n@@ -29,7 +29,6 @@\n   version without encryption capabilities).\n  */\n \n-#define ZCRYPT_INTERNAL\n #include \"zip.h\"\n #include \"crypt.h\"\n #include \"ttyio.h\"\n@@ -219,7 +218,12 @@ void crypthead(passwd, crc)\n      * often poorly implemented.\n      */\n     if (++calls == 1) {\n-        srand((unsigned)time(NULL) ^ ZCR_SEED2);\n+        unsigned zcr_seed1 = (unsigned)time(NULL);\n+#ifndef ZCRYPT_INTERNAL\n+        if (epoch > 0)\n+            zcr_seed1 = (unsigned)epoch;\n+#endif\n+        srand(zcr_seed1 ^ ZCR_SEED2);\n     }\n     init_keys(passwd);\n     for (n = 0; n < RAND_HEAD_LEN-2; n++) {\n--- a/globals.c\n+++ b/globals.c\n@@ -206,6 +206,7 @@ int read_split_archive = 0;       /* 1=s\n int split_method = 0;             /* 0=no splits, 1=seekable, 2=data desc, -1=no */\n uzoff_t split_size = 0;           /* how big each split should be */\n int split_bell = 0;               /* when pause for next split ring bell */\n+time_t epoch = 0;                 /* timestamp from SOURCE_DATE_EPOCH */\n uzoff_t bytes_prev_splits = 0;    /* total bytes written to all splits before this */\n uzoff_t bytes_this_entry = 0;     /* bytes written for this entry across all splits */\n int noisy_splits = 0;             /* note when splits are being created */\n--- a/zip.h\n+++ b/zip.h\n@@ -502,6 +502,7 @@ extern uzoff_t bytes_this_split; /* byte\n extern int read_split_archive;   /* 1=scanzipf_reg detected spanning signature */\n extern int split_method;         /* 0=no splits, 1=seekable, 2=data descs, -1=no */\n extern uzoff_t split_size;       /* how big each split should be */\n+extern time_t epoch;             /* timestamp from SOURCE_DATE_EPOCH */\n extern int split_bell;           /* when pause for next split ring bell */\n extern uzoff_t bytes_prev_splits; /* total bytes written to all splits before this */\n extern uzoff_t bytes_this_entry; /* bytes written for this entry across all splits */\n--- a/zipup.c\n+++ b/zipup.c\n@@ -676,7 +676,7 @@ struct zlist far *z;    /* zip entry to\n   } /* strcmp(z->name, \"-\") == 0 */\n \n   if (extra_fields == 0 && (source_date_epoch = getenv(\"SOURCE_DATE_EPOCH\")) != NULL) {\n-     time_t epoch = strtoull(source_date_epoch, NULL, 10);\n+     epoch = strtoull(source_date_epoch, NULL, 10);\n      if (epoch > 0) {\n        ulg epochtim = unix2dostime(&epoch);\n        if (z->tim > epochtim) z->tim = epochtim;\n"
  },
  {
    "path": "tools/zlib/Makefile",
    "content": "#\n# Copyright (C) 2006-2013 OpenWrt.org\n#\n# This is free software, licensed under the GNU General Public License v2.\n# See /LICENSE for more information.\n#\n\ninclude $(TOPDIR)/rules.mk\n\nPKG_NAME:=zlib\nPKG_VERSION:=1.2.12\nPKG_RELEASE:=1\n\nPKG_SOURCE_PROTO:=git\nPKG_SOURCE_URL:=https://github.com/madler/zlib\nPKG_MIRROR_HASH:=a162fc219763635f0c1591ec515d4b08684e4b0bfb4b1c8e65e4eab18d597c27\nPKG_SOURCE_VERSION:=21767c654d31d2dccdde4330529775c6c5fd5389\n\nPKG_LICENSE:=Zlib\nPKG_LICENSE_FILES:=README\nPKG_CPE_ID:=cpe:/a:gnu:zlib\n\ninclude $(INCLUDE_DIR)/host-build.mk\ninclude $(INCLUDE_DIR)/cmake.mk\n\nHOST_CFLAGS +=-fPIC\n\ndefine Host/Install\n\t$(CP) $(HOST_BUILD_DIR)/libz.a $(STAGING_DIR_HOST)/lib/\n\t$(CP) $(HOST_BUILD_DIR)/zconf.h $(STAGING_DIR_HOST)/include/\n\t$(CP) $(HOST_BUILD_DIR)/zlib.h $(STAGING_DIR_HOST)/include/\n\t$(CP) $(HOST_BUILD_DIR)/zlib.pc $(STAGING_DIR_HOST)/lib/pkgconfig/\nendef\n\ndefine Host/Clean\n\trm -f $(STAGING_DIR_HOST)/lib/libz.a\n\trm -f $(STAGING_DIR_HOST)/include/zconf.h\n\trm -f $(STAGING_DIR_HOST)/include/zlib.h\n\trm -f $(STAGING_DIR_HOST)/lib/pkgconfig//zlib.pc\nendef\n\n$(eval $(call HostBuild))\n"
  },
  {
    "path": "tools/zlib/patches/900-overridable-pc-exec-prefix.patch",
    "content": "--- a/zlib.pc.cmakein\n+++ b/zlib.pc.cmakein\n@@ -1,8 +1,8 @@\n prefix=@CMAKE_INSTALL_PREFIX@\n exec_prefix=@CMAKE_INSTALL_PREFIX@\n-libdir=@INSTALL_LIB_DIR@\n-sharedlibdir=@INSTALL_LIB_DIR@\n-includedir=@INSTALL_INC_DIR@\n+libdir=${prefix}/lib\n+sharedlibdir=${prefix}/lib\n+includedir=${prefix}/include\n \n Name: zlib\n Description: zlib compression library\n"
  },
  {
    "path": "tools/zstd/Makefile",
    "content": "include $(TOPDIR)/rules.mk\n\nPKG_NAME:=zstd\nPKG_VERSION:=1.5.2\n\nPKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz\nPKG_SOURCE_URL:=https://github.com/facebook/zstd/releases/download/v$(PKG_VERSION)\nPKG_HASH:=7c42d56fac126929a6a85dbc73ff1db2411d04f104fae9bdea51305663a83fd0\n\nPKG_LICENSE:=BSD-3-Clause\nPKG_LICENSE_FILES:=LICENSE\nPKG_CPE_ID:=cpe:/a:facebook:zstandard\n\ninclude $(INCLUDE_DIR)/host-build.mk\ninclude $(INCLUDE_DIR)/meson.mk\n\nMESON_HOST_BUILD_DIR:=$(HOST_BUILD_DIR)/build/meson/openwrt-build\n\nHOSTCC:= $(HOSTCC_NOCACHE)\nHOST_LDFLAGS += -Wl,-rpath,$(STAGING_DIR_HOST)/lib\n\nMESON_HOST_ARGS += \\\n\t-Dlegacy_level=7 \\\n\t-Ddebug_level=0 \\\n\t-Dbacktrace=false \\\n\t-Dstatic_runtime=false \\\n\t-Dbin_programs=true \\\n\t-Dbin_tests=false \\\n\t-Dbin_contrib=false \\\n\t-Dmulti_thread=enabled \\\n\t-Dzlib=disabled \\\n\t-Dlzma=disabled \\\n\t-Dlz4=disabled\n\n$(eval $(call HostBuild))\n"
  }
]